From 47e383545f4aac3bfaec0563429cc721540e665a Mon Sep 17 00:00:00 2001 From: Jeff Glaum Date: Mon, 8 Sep 2025 15:15:38 -0700 Subject: Initial commit --- .github/workflows/cargo-vet-pr-comment.yml | 137 +++++++++++++++++ .github/workflows/cargo-vet.yml | 53 +++++++ .github/workflows/check.yml | 169 ++++++++++++++++++++ .github/workflows/nostd.yml | 30 ++++ .gitignore | 14 ++ .vscode/settings.json | 14 ++ CODEOWNERS | 1 + CODE_OF_CONDUCT.md | 132 ++++++++++++++++ CONTRIBUTING.md | 35 +++++ Cargo.toml | 19 +++ LICENSE | 21 +++ README.md | 63 ++++++++ SECURITY.md | 66 ++++++++ deny.toml | 239 +++++++++++++++++++++++++++++ rust-toolchain.toml | 2 + rustfmt.toml | 1 + src/baremetal/mod.rs | 6 + src/main.rs | 18 +++ supply-chain/README.md | 83 ++++++++++ supply-chain/audits.toml | 4 + supply-chain/config.toml | 14 ++ supply-chain/imports.lock | 8 + 22 files changed, 1129 insertions(+) create mode 100644 .github/workflows/cargo-vet-pr-comment.yml create mode 100644 .github/workflows/cargo-vet.yml create mode 100644 .github/workflows/check.yml create mode 100644 .github/workflows/nostd.yml create mode 100644 .gitignore create mode 100644 .vscode/settings.json create mode 100644 CODEOWNERS create mode 100644 CODE_OF_CONDUCT.md create mode 100644 CONTRIBUTING.md create mode 100644 Cargo.toml create mode 100644 LICENSE create mode 100644 README.md create mode 100644 SECURITY.md create mode 100644 deny.toml create mode 100644 rust-toolchain.toml create mode 100644 rustfmt.toml create mode 100644 src/baremetal/mod.rs create mode 100644 src/main.rs create mode 100644 supply-chain/README.md create mode 100644 supply-chain/audits.toml create mode 100644 supply-chain/config.toml create mode 100644 supply-chain/imports.lock diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml new file mode 100644 index 000000000..dd8ef37a6 --- /dev/null +++ b/.github/workflows/cargo-vet-pr-comment.yml @@ -0,0 +1,137 @@ +# This workflow triggers after cargo-vet workflow has run. +# It adds a comment to the PR with the results of the cargo vet run. +# It first adds a comment if the cargo vet run fails, +# and updates the comment if the cargo vet run succeeds after having failed at least once. + +name: Cargo vet PR comment + +on: + workflow_run: + workflows: [cargo-vet] + types: + - completed + +permissions: + contents: read + pull-requests: write + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +jobs: + + find-pr-comment: + # This job runs when the cargo-vet job fails or succeeds + # It will download the artifact from the failed job and post a comment on the PR + runs-on: ubuntu-latest + outputs: + comment-id: ${{ steps.get-comment-id.outputs.comment-id }} + pr-number: ${{ steps.get-pr-number.outputs.pr_number }} + if: github.event.workflow_run.event == 'pull_request' + steps: + - name: 'Download artifact' + uses: actions/download-artifact@v4 + with: + github-token: ${{ secrets.GITHUB_TOKEN }} + name: pr + path: pr/ + run-id: ${{ github.event.workflow_run.id }} + + - name: 'Get PR number' + id: get-pr-number + run: echo "pr_number=$(cat ./pr/NR)" >> $GITHUB_OUTPUT + + - name: 'Find existing comment' + id: find-comment + uses: peter-evans/find-comment@v3 + with: + issue-number: ${{ steps.get-pr-number.outputs.pr_number }} + comment-author: 'github-actions[bot]' + body-includes: 'comment-tag: [cargo-vet]' + + - name: 'Get comment ID' + id: get-comment-id + if: ${{ steps.find-comment.outputs.comment-id != '' }} + run: echo "comment-id=${{ steps.find-comment.outputs.comment-id }}" >> $GITHUB_OUTPUT + + post-comment-failure: + # This job runs when the cargo-vet job fails + # It will download the artifact from the failed job and post a comment on the PR + runs-on: ubuntu-latest + needs: find-pr-comment + if: github.event.workflow_run.conclusion == 'failure' + steps: + - name: 'Comment on PR - Failure' + uses: peter-evans/create-or-update-comment@v4 + with: + comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} + issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} + body: | + # Cargo Vet Audit Failed + + `cargo vet` has failed in this PR. Please run `cargo vet --locked` locally to check for new or updated unvetted dependencies. + Details about the vetting process can be found in [supply-chain/README.md](../blob/main/supply-chain/README.md) + + ## If the unvetted dependencies are not needed + Please modify Cargo.toml file to avoid including the dependencies. + + ## If the unvetted dependencies are needed + Post a new comment with the questionnaire below to the PR to help the auditors vet the dependencies. + After the auditors have vetted the dependencies, the PR will need to be rebased to pick up the new audits and pass this check. + + ### Copy and paste the questionnaire as a new comment and provide your answers: + + **1. What crates (with version) need to be audited?** + + **2. How many of the crates are version updates vs new dependencies?** + + **3. To confirm none of the already included crates serve your needs, please provide a brief description of the purpose of the new crates.** + + **4. Any extra notes to the auditors to help with their audits.** + + + edit-mode: replace + + - name: 'Label PR' + uses: actions/github-script@v7 + with: + script: | + github.rest.issues.addLabels({ + issue_number: ${{ needs.find-pr-comment.outputs.pr-number }}, + owner: context.repo.owner, + repo: context.repo.repo, + labels: ['cargo vet'] + }) + + post-comment-success: + # This job runs when the cargo-vet job succeeds + # It will update the comment on the PR with a success message + runs-on: ubuntu-latest + needs: find-pr-comment + if: github.event.workflow_run.conclusion == 'success' + steps: + - name: 'Comment on PR - Success' + # Only update the comment if it exists + # This is to avoid creating a new comment if the cargo-vet job has never failed before + if: ${{ needs.find-pr-comment.outputs.comment-id }} + uses: peter-evans/create-or-update-comment@v4 + with: + comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} + issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} + body: | + # Cargo Vet Audit Passed + `cargo vet` has passed in this PR. No new unvetted dependencies were found. + + + edit-mode: replace \ No newline at end of file diff --git a/.github/workflows/cargo-vet.yml b/.github/workflows/cargo-vet.yml new file mode 100644 index 000000000..864c138e9 --- /dev/null +++ b/.github/workflows/cargo-vet.yml @@ -0,0 +1,53 @@ +# This workflow runs whenever a PR is opened or updated. It runs cargo vet to check for unvetted dependencies in the Cargo.lock file. +permissions: + contents: read +on: + pull_request: + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +name: cargo-vet +jobs: + vet: + # cargo-vet checks for unvetted dependencies in the Cargo.lock file + # This is to ensure that new dependencies are vetted before they are added to the project + name: vet-dependencies + runs-on: ubuntu-latest + env: + CARGO_VET_VERSION: 0.10.1 + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - uses: actions/cache@v4 + with: + path: ${{ runner.tool_cache }}/cargo-vet + key: cargo-vet-bin-${{ env.CARGO_VET_VERSION }} + + - name: Add the tool cache directory to the search path + run: echo "${{ runner.tool_cache }}/cargo-vet/bin" >> $GITHUB_PATH + + - name: Ensure that the tool cache is populated with the cargo-vet binary + run: cargo install --root ${{ runner.tool_cache }}/cargo-vet --version ${{ env.CARGO_VET_VERSION }} cargo-vet + + - name: Invoke cargo-vet + run: cargo vet --locked + + - name: Save PR number + # PR number is saved as an artifact so it can be used to determine the PR to comment on by the vet-pr-comment workflow + # vet-pr-comment workflow is triggered by the workflow_run event so it runs in the context of the base branch and not the PR branch + if: ${{ failure() }} || ${{ success() }} + run: | + mkdir -p ./pr + echo ${{ github.event.number }} > ./pr/NR + - uses: actions/upload-artifact@v4 + # Need to upload the artifact in both success and failure cases so comment can be updated in either case + if: ${{ failure() }} || ${{ success() }} + with: + name: pr + path: pr/ + overwrite: true \ No newline at end of file diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml new file mode 100644 index 000000000..9bf402d61 --- /dev/null +++ b/.github/workflows/check.yml @@ -0,0 +1,169 @@ +# This workflow runs whenever a PR is opened or updated, or a commit is pushed to main. It runs +# several checks: +# - commit_list: produces a list of commits to be checked +# - fmt: checks that the code is formatted according to rustfmt +# - clippy: checks that the code does not contain any clippy warnings +# - doc: checks that the code can be documented without errors +# - hack: check combinations of feature flags +# - msrv: check that the msrv specified in the crate is correct +permissions: + contents: read +# This configuration allows maintainers of this repo to create a branch and pull request based on +# the new branch. Restricting the push trigger to the main branch ensures that the PR only gets +# built once. +on: + push: + branches: [main] + pull_request: +# If new code is pushed to a PR branch, then cancel in progress workflows for that PR. Ensures that +# we don't waste CI time, and returns results quicker https://github.com/jonhoo/rust-ci-conf/pull/5 +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true +name: check +jobs: + fmt: + runs-on: ubuntu-latest + name: stable / fmt + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install stable + uses: dtolnay/rust-toolchain@stable + with: + components: rustfmt + - name: cargo fmt --check + run: cargo fmt --check + + clippy: + runs-on: ubuntu-latest + name: ${{ matrix.toolchain }} / clippy + permissions: + contents: read + checks: write + strategy: + fail-fast: false + matrix: + # Get early warning of new lints which are regularly introduced in beta channels. + toolchain: [stable, beta] + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install ${{ matrix.toolchain }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.toolchain }} + components: clippy + - name: cargo clippy + uses: giraffate/clippy-action@v1 + with: + reporter: 'github-pr-check' + github_token: ${{ secrets.GITHUB_TOKEN }} + + # Enable once we have a released crate + # semver: + # runs-on: ubuntu-latest + # name: semver + # strategy: + # fail-fast: false + # steps: + # - uses: actions/checkout@v4 + # with: + # submodules: true + # - name: Install stable + # uses: dtolnay/rust-toolchain@stable + # with: + # components: rustfmt + # - name: cargo-semver-checks + # uses: obi1kenobi/cargo-semver-checks-action@v2 + + doc: + # run docs generation on nightly rather than stable. This enables features like + # https://doc.rust-lang.org/beta/unstable-book/language-features/doc-cfg.html which allows an + # API be documented as only available in some specific platforms. + runs-on: ubuntu-latest + name: nightly / doc + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install nightly + uses: dtolnay/rust-toolchain@nightly + - name: cargo doc + run: cargo doc --no-deps --all-features + env: + RUSTDOCFLAGS: --cfg docsrs + + hack: + # cargo-hack checks combinations of feature flags to ensure that features are all additive + # which is required for feature unification + runs-on: ubuntu-latest + name: ubuntu / stable / features + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install stable + uses: dtolnay/rust-toolchain@stable + - name: cargo install cargo-hack + uses: taiki-e/install-action@cargo-hack + # intentionally no target specifier; see https://github.com/jonhoo/rust-ci-conf/pull/4 + # --feature-powerset runs for every combination of features + - name: cargo hack + run: cargo hack --feature-powerset check + + deny: + # cargo-deny checks licenses, advisories, sources, and bans for + # our dependencies. + runs-on: ubuntu-latest + name: ubuntu / stable / deny + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install stable + uses: dtolnay/rust-toolchain@stable + - name: cargo install cargo-deny + uses: EmbarkStudios/cargo-deny-action@v2 + with: + log-level: warn + manifest-path: ./Cargo.toml + command: check + arguments: --all-features + + test: + runs-on: ubuntu-latest + name: ubuntu / stable / test + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install stable + uses: dtolnay/rust-toolchain@stable + - name: cargo install cargo-hack + uses: taiki-e/install-action@cargo-hack + - name: cargo test + run: cargo hack --feature-powerset test + + msrv: + # check that we can build using the minimal rust version that is specified by this crate + runs-on: ubuntu-latest + # we use a matrix here just because env can't be used in job names + # https://docs.github.com/en/actions/learn-github-actions/contexts#context-availability + strategy: + fail-fast: false + matrix: + msrv: ["1.85"] + name: ubuntu / ${{ matrix.msrv }} + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install ${{ matrix.msrv }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.msrv }} + - name: cargo +${{ matrix.msrv }} check + run: cargo check diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml new file mode 100644 index 000000000..532235851 --- /dev/null +++ b/.github/workflows/nostd.yml @@ -0,0 +1,30 @@ +# This workflow checks whether the library is able to run without the std library (e.g., embedded). +# This entire file should be removed if this crate does not support no-std. See check.yml for +# information about how the concurrency cancellation and workflow triggering works +permissions: + contents: read +on: + push: + branches: [main] + pull_request: +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true +name: no-std +jobs: + nostd: + runs-on: ubuntu-latest + name: ${{ matrix.target }} + strategy: + matrix: + target: [thumbv8m.main-none-eabihf] + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install stable + uses: dtolnay/rust-toolchain@stable + - name: rustup target add ${{ matrix.target }} + run: rustup target add ${{ matrix.target }} + - name: cargo check + run: cargo check --target ${{ matrix.target }} diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..6985cf1bd --- /dev/null +++ b/.gitignore @@ -0,0 +1,14 @@ +# Generated by Cargo +# will have compiled files and executables +debug/ +target/ + +# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries +# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock + +# These are backup files generated by rustfmt +**/*.rs.bk + +# MSVC Windows builds of rustc generate these, which store debugging information +*.pdb diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 000000000..ace00d468 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,14 @@ +{ + "editor.formatOnSave": true, + "rust-analyzer.checkOnSave": true, + "rust-analyzer.check.allTargets": false, + "rust-analyzer.cargo.target": "thumbv8m.main-none-eabihf", + "rust-analyzer.cargo.features": "all", + "rust-analyzer.check.command": "clippy", + "[toml]": { + "editor.defaultFormatter": "tamasfe.even-better-toml" + }, + "[rust]": { + "editor.defaultFormatter": "rust-lang.rust-analyzer" + } +} diff --git a/CODEOWNERS b/CODEOWNERS new file mode 100644 index 000000000..e2a52ae39 --- /dev/null +++ b/CODEOWNERS @@ -0,0 +1 @@ +* @felipebalbi @jerrysxie @tullom @RobertZ2011 @dymk diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md new file mode 100644 index 000000000..8603671fb --- /dev/null +++ b/CODE_OF_CONDUCT.md @@ -0,0 +1,132 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +We as members, contributors, and leaders pledge to make participation in our +community a harassment-free experience for everyone, regardless of age, body +size, visible or invisible disability, ethnicity, sex characteristics, gender +identity and expression, level of experience, education, socio-economic status, +nationality, personal appearance, race, caste, color, religion, or sexual +identity and orientation. + +We pledge to act and interact in ways that contribute to an open, welcoming, +diverse, inclusive, and healthy community. + +## Our Standards + +Examples of behavior that contributes to a positive environment for our +community include: + +* Demonstrating empathy and kindness toward other people +* Being respectful of differing opinions, viewpoints, and experiences +* Giving and gracefully accepting constructive feedback +* Accepting responsibility and apologizing to those affected by our mistakes, + and learning from the experience +* Focusing on what is best not just for us as individuals, but for the overall + community + +Examples of unacceptable behavior include: + +* The use of sexualized language or imagery, and sexual attention or advances of + any kind +* Trolling, insulting or derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or email address, + without their explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Enforcement Responsibilities + +Community leaders are responsible for clarifying and enforcing our standards of +acceptable behavior and will take appropriate and fair corrective action in +response to any behavior that they deem inappropriate, threatening, offensive, +or harmful. + +Community leaders have the right and responsibility to remove, edit, or reject +comments, commits, code, wiki edits, issues, and other contributions that are +not aligned to this Code of Conduct, and will communicate reasons for moderation +decisions when appropriate. + +## Scope + +This Code of Conduct applies within all community spaces, and also applies when +an individual is officially representing the community in public spaces. +Examples of representing our community include using an official e-mail address, +posting via an official social media account, or acting as an appointed +representative at an online or offline event. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported to the community leaders responsible for enforcement at +odpadmin@microsoft.com. +All complaints will be reviewed and investigated promptly and fairly. + +All community leaders are obligated to respect the privacy and security of the +reporter of any incident. + +## Enforcement Guidelines + +Community leaders will follow these Community Impact Guidelines in determining +the consequences for any action they deem in violation of this Code of Conduct: + +### 1. Correction + +**Community Impact**: Use of inappropriate language or other behavior deemed +unprofessional or unwelcome in the community. + +**Consequence**: A private, written warning from community leaders, providing +clarity around the nature of the violation and an explanation of why the +behavior was inappropriate. A public apology may be requested. + +### 2. Warning + +**Community Impact**: A violation through a single incident or series of +actions. + +**Consequence**: A warning with consequences for continued behavior. No +interaction with the people involved, including unsolicited interaction with +those enforcing the Code of Conduct, for a specified period of time. This +includes avoiding interactions in community spaces as well as external channels +like social media. Violating these terms may lead to a temporary or permanent +ban. + +### 3. Temporary Ban + +**Community Impact**: A serious violation of community standards, including +sustained inappropriate behavior. + +**Consequence**: A temporary ban from any sort of interaction or public +communication with the community for a specified period of time. No public or +private interaction with the people involved, including unsolicited interaction +with those enforcing the Code of Conduct, is allowed during this period. +Violating these terms may lead to a permanent ban. + +### 4. Permanent Ban + +**Community Impact**: Demonstrating a pattern of violation of community +standards, including sustained inappropriate behavior, harassment of an +individual, or aggression toward or disparagement of classes of individuals. + +**Consequence**: A permanent ban from any sort of public interaction within the +community. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], +version 2.1, available at +[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1]. + +Community Impact Guidelines were inspired by +[Mozilla's code of conduct enforcement ladder][Mozilla CoC]. + +For answers to common questions about this code of conduct, see the FAQ at +[https://www.contributor-covenant.org/faq][FAQ]. Translations are available at +[https://www.contributor-covenant.org/translations][translations]. + +[homepage]: https://www.contributor-covenant.org +[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html +[Mozilla CoC]: https://github.com/mozilla/diversity +[FAQ]: https://www.contributor-covenant.org/faq +[translations]: https://www.contributor-covenant.org/translations \ No newline at end of file diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 000000000..c45bc8e43 --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,35 @@ +# Contributing to Open Device Partnership + +The Open Device Partnership project welcomes your suggestions and contributions! Before opening your first issue or pull request, please review our +[Code of Conduct](CODE_OF_CONDUCT.md) to understand how our community interacts in an inclusive and respectful manner. + +## Contribution Licensing + +Most of our code is distributed under the terms of the [MIT license](LICENSE), and when you contribute code that you wrote to our repositories, +you agree that you are contributing under those same terms. In addition, by submitting your contributions you are indicating that +you have the right to submit those contributions under those terms. + +## Other Contribution Information + +If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your +pull request so that the project team can discuss the situation with you. + +## Commit Message + +* Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html) + +## PR Etiquette + +* Create a draft PR first +* Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers. + +## Clean Commit History + +We disabled squashing of commit and would like to maintain a clean commit history. So please reorganize your commits with the following items: + +* Each commit builds successfully without warning +* Miscellaneous commits to fix typos + formatting are squashed + +## Regressions + +When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster. diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 000000000..71c4806fe --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "embedded-rust-template" +version = "0.1.0" +edition = "2021" +license = "MIT" +repository = "https://github.com/OpenDevicePartnership/embedded-rust-template" +rust-version = "1.85" + +[dependencies] +# dependencies for all targets + +[target.'cfg(target_os = "none")'.dependencies] +# dependencies for no-std targets + +[lints.clippy] +suspicious = "forbid" +correctness = "forbid" +perf = "forbid" +style = "forbid" diff --git a/LICENSE b/LICENSE new file mode 100644 index 000000000..75092dc47 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2025 Open Device Partnership + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 000000000..60b09c0a6 --- /dev/null +++ b/README.md @@ -0,0 +1,63 @@ +# embedded-rust-template +Template repository for Embedded Rust development + +## Customizing This Template + +### Changing the Target Architecture + +This template is configured for `thumbv8m.main-none-eabihf`, by default, but you can modify it for other targets (i.e. `aarch64-unknown-none`): + +1. **VSCode Settings**: Update the target in `.vscode/settings.json`: + ```json + "rust-analyzer.cargo.target": "your-target-architecture" + ``` + + +This configuration ensures that: +- Only the specified target architecture is analyzed, not the host platform +- Code is checked against the no_std environment + +To temporarily analyze code for the host platform instead, you can remove the `rust-analyzer.cargo.target` setting. + +2. **GitHub Workflows**: Modify the target in two workflow files: + - `.github/workflows/nostd.yml`: Update the targets in the matrix: + ```yaml + matrix: + target: [your-target-architecture] + ``` + - `.github/workflows/check.yml`: If there are any target-specific checks, update them accordingly. + +3. **Cargo Configuration**: If needed, you can add target-specific configuration in a `.cargo/config.toml` file. + +### Converting from Binary to Library + +To convert this project from a binary to a library: + +1. **Cargo.toml**: Update your project structure: + ```toml + [lib] + name = "your_library_name" + ``` + +2. **Directory Structure**: + - For a library, ensure you have a `src/lib.rs` file instead of `src/main.rs` + - Move your code from `main.rs` to `lib.rs` and adjust as needed + +3. **No-std Configuration**: If you're creating a no-std library, ensure you have: + ```rust + // In lib.rs + #![cfg_attr(target_os = "none", no_std)] + // Add other attributes as needed + ``` + +### Project Dependencies + +Update the dependencies in `Cargo.toml` based on your target platform: + +```toml +[dependencies] +# Common dependencies for all targets + +[target.'cfg(target_os = "none")'.dependencies] +# Dependencies for no-std targets +``` diff --git a/SECURITY.md b/SECURITY.md new file mode 100644 index 000000000..6ed358156 --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,66 @@ +# Vulnerability Disclosure and Embargo Policy + +The Open Device Partnership project welcomes the responsible disclosure of vulnerabilities. + +## Initial Contact + +All security bugs in Open Device Partnership should be reported to the security team. +To do so, please reach out in the form of a +[Github Security Advisory](https://docs.github.com/en/code-security/security-advisories/guidance-on-reporting-and-writing-information-about-vulnerabilities). + +You will be invited to join this private area to discuss specifics. Doing so +allows us to start with a high level of confidentiality and relax it if the +issue is less critical, moving to work on the fix in the open. + +Your initial contact will be acknowledged within 48 hours, and you’ll receive +a more detailed response within 96 hours indicating the next steps in handling +your report. + +After the initial reply to your report, the security team will endeavor to +keep you informed of the progress being made towards a fix and full +announcement. As recommended by +[RFPolicy](https://dl.packetstormsecurity.net/papers/general/rfpolicy-2.0.txt), +these updates will be sent at least every five working days. + +## Disclosure Policy + +The Open Device Partnership project has a 5 step disclosure process. + +1. Contact is established, a private channel created, and the security report + is received and is assigned a primary handler. This person will coordinate + the fix and release process. +2. The problem is confirmed and a list of all affected versions is determined. + If an embargo is needed (see below), details of the embargo are decided. +3. Code is audited to find any potential similar problems. +4. Fixes are prepared for all releases which are still under maintenance. In + case of embargo, these fixes are not committed to the public repository but + rather held in a private fork pending the announcement. +5. The changes are pushed to the public repository and new builds are deployed. + +This process can take some time, especially when coordination is required +with maintainers of other projects. Every effort will be made to handle the bug +in as timely a manner as possible, however it is important that we follow the +release process above to ensure that the disclosure is handled in a consistent +manner. + +## Embargoes + +While the Open Device Partnership project aims to follow the highest standards of +transparency and openness, handling some security issues may pose such an +immediate threat to various stakeholders and require coordination between +various actors that it cannot be made immediately public. + +In this case, security issues will fall under an embargo. + +An embargo can be called for in various cases: + +- when disclosing the issue without simultaneously providing a mitigation + would seriously endanger users, +- when producing a fix requires coordinating between multiple actors (such as + upstream or downstream/dependency projects), or simply +- when proper analysis of the issue and its ramifications demands time. + +If we determine that an issue you report requires an embargo, we will discuss +this with you and try to find a reasonable expiry date (aka “embargo +completion date”), as well as who should be included in the list of +need-to-know people. \ No newline at end of file diff --git a/deny.toml b/deny.toml new file mode 100644 index 000000000..9ddd12fca --- /dev/null +++ b/deny.toml @@ -0,0 +1,239 @@ +# This template contains all of the possible sections and their default values + +# Note that all fields that take a lint level have these possible values: +# * deny - An error will be produced and the check will fail +# * warn - A warning will be produced, but the check will not fail +# * allow - No warning or error will be produced, though in some cases a note +# will be + +# The values provided in this template are the default values that will be used +# when any section or field is not specified in your own configuration + +# Root options + +# The graph table configures how the dependency graph is constructed and thus +# which crates the checks are performed against +[graph] +# If 1 or more target triples (and optionally, target_features) are specified, +# only the specified targets will be checked when running `cargo deny check`. +# This means, if a particular package is only ever used as a target specific +# dependency, such as, for example, the `nix` crate only being used via the +# `target_family = "unix"` configuration, that only having windows targets in +# this list would mean the nix crate, as well as any of its exclusive +# dependencies not shared by any other crates, would be ignored, as the target +# list here is effectively saying which targets you are building for. +targets = [ + # The triple can be any string, but only the target triples built in to + # rustc (as of 1.40) can be checked against actual config expressions + #"x86_64-unknown-linux-musl", + # You can also specify which target_features you promise are enabled for a + # particular target. target_features are currently not validated against + # the actual valid features supported by the target architecture. + #{ triple = "wasm32-unknown-unknown", features = ["atomics"] }, +] +# When creating the dependency graph used as the source of truth when checks are +# executed, this field can be used to prune crates from the graph, removing them +# from the view of cargo-deny. This is an extremely heavy hammer, as if a crate +# is pruned from the graph, all of its dependencies will also be pruned unless +# they are connected to another crate in the graph that hasn't been pruned, +# so it should be used with care. The identifiers are [Package ID Specifications] +# (https://doc.rust-lang.org/cargo/reference/pkgid-spec.html) +#exclude = [] +# If true, metadata will be collected with `--all-features`. Note that this can't +# be toggled off if true, if you want to conditionally enable `--all-features` it +# is recommended to pass `--all-features` on the cmd line instead +all-features = false +# If true, metadata will be collected with `--no-default-features`. The same +# caveat with `all-features` applies +no-default-features = false +# If set, these feature will be enabled when collecting metadata. If `--features` +# is specified on the cmd line they will take precedence over this option. +#features = [] + +# The output table provides options for how/if diagnostics are outputted +[output] +# When outputting inclusion graphs in diagnostics that include features, this +# option can be used to specify the depth at which feature edges will be added. +# This option is included since the graphs can be quite large and the addition +# of features from the crate(s) to all of the graph roots can be far too verbose. +# This option can be overridden via `--feature-depth` on the cmd line +feature-depth = 1 + +# This section is considered when running `cargo deny check advisories` +# More documentation for the advisories section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/advisories/cfg.html +[advisories] +# The path where the advisory databases are cloned/fetched into +#db-path = "$CARGO_HOME/advisory-dbs" +# The url(s) of the advisory databases to use +#db-urls = ["https://github.com/rustsec/advisory-db"] +# A list of advisory IDs to ignore. Note that ignored advisories will still +# output a note when they are encountered. +ignore = [ + #"RUSTSEC-0000-0000", + #{ id = "RUSTSEC-0000-0000", reason = "you can specify a reason the advisory is ignored" }, + #"a-crate-that-is-yanked@0.1.1", # you can also ignore yanked crate versions if you wish + #{ crate = "a-crate-that-is-yanked@0.1.1", reason = "you can specify why you are ignoring the yanked crate" }, + { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." }, + { id = "RUSTSEC-2024-0436", reason = "there are no suitable replacements for paste right now; paste has been archived as read-only. It only affects compile time concatenation in macros. We will allow it for now" }, +] +# If this is true, then cargo deny will use the git executable to fetch advisory database. +# If this is false, then it uses a built-in git library. +# Setting this to true can be helpful if you have special authentication requirements that cargo-deny does not support. +# See Git Authentication for more information about setting up git authentication. +#git-fetch-with-cli = true + +# This section is considered when running `cargo deny check licenses` +# More documentation for the licenses section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/licenses/cfg.html +[licenses] +# List of explicitly allowed licenses +# See https://spdx.org/licenses/ for list of possible licenses +# [possible values: any SPDX 3.11 short identifier (+ optional exception)]. +allow = [ + "MIT", + "Apache-2.0", + "Unicode-3.0", + "BSD-3-Clause", + #"Apache-2.0 WITH LLVM-exception", +] +# The confidence threshold for detecting a license from license text. +# The higher the value, the more closely the license text must be to the +# canonical license text of a valid SPDX license file. +# [possible values: any between 0.0 and 1.0]. +confidence-threshold = 0.8 +# Allow 1 or more licenses on a per-crate basis, so that particular licenses +# aren't accepted for every possible crate as with the normal allow list +exceptions = [ + # Each entry is the crate and version constraint, and its specific allow + # list + #{ allow = ["Zlib"], crate = "adler32" }, +] + +# Some crates don't have (easily) machine readable licensing information, +# adding a clarification entry for it allows you to manually specify the +# licensing information +#[[licenses.clarify]] +# The package spec the clarification applies to +#crate = "ring" +# The SPDX expression for the license requirements of the crate +#expression = "MIT AND ISC AND OpenSSL" +# One or more files in the crate's source used as the "source of truth" for +# the license expression. If the contents match, the clarification will be used +# when running the license check, otherwise the clarification will be ignored +# and the crate will be checked normally, which may produce warnings or errors +# depending on the rest of your configuration +#license-files = [ +# Each entry is a crate relative path, and the (opaque) hash of its contents +#{ path = "LICENSE", hash = 0xbd0eed23 } +#] + +[licenses.private] +# If true, ignores workspace crates that aren't published, or are only +# published to private registries. +# To see how to mark a crate as unpublished (to the official registry), +# visit https://doc.rust-lang.org/cargo/reference/manifest.html#the-publish-field. +ignore = false +# One or more private registries that you might publish crates to, if a crate +# is only published to private registries, and ignore is true, the crate will +# not have its license(s) checked +registries = [ + #"https://sekretz.com/registry +] + +# This section is considered when running `cargo deny check bans`. +# More documentation about the 'bans' section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/bans/cfg.html +[bans] +# Lint level for when multiple versions of the same crate are detected +multiple-versions = "warn" +# Lint level for when a crate version requirement is `*` +wildcards = "allow" +# The graph highlighting used when creating dotgraphs for crates +# with multiple versions +# * lowest-version - The path to the lowest versioned duplicate is highlighted +# * simplest-path - The path to the version with the fewest edges is highlighted +# * all - Both lowest-version and simplest-path are used +highlight = "all" +# The default lint level for `default` features for crates that are members of +# the workspace that is being checked. This can be overridden by allowing/denying +# `default` on a crate-by-crate basis if desired. +workspace-default-features = "allow" +# The default lint level for `default` features for external crates that are not +# members of the workspace. This can be overridden by allowing/denying `default` +# on a crate-by-crate basis if desired. +external-default-features = "allow" +# List of crates that are allowed. Use with care! +allow = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is allowed" }, +] +# List of crates to deny +deny = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is banned" }, + # Wrapper crates can optionally be specified to allow the crate when it + # is a direct dependency of the otherwise banned crate + #{ crate = "ansi_term@0.11.0", wrappers = ["this-crate-directly-depends-on-ansi_term"] }, +] + +# List of features to allow/deny +# Each entry the name of a crate and a version range. If version is +# not specified, all versions will be matched. +#[[bans.features]] +#crate = "reqwest" +# Features to not allow +#deny = ["json"] +# Features to allow +#allow = [ +# "rustls", +# "__rustls", +# "__tls", +# "hyper-rustls", +# "rustls", +# "rustls-pemfile", +# "rustls-tls-webpki-roots", +# "tokio-rustls", +# "webpki-roots", +#] +# If true, the allowed features must exactly match the enabled feature set. If +# this is set there is no point setting `deny` +#exact = true + +# Certain crates/versions that will be skipped when doing duplicate detection. +skip = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason why it can't be updated/removed" }, +] +# Similarly to `skip` allows you to skip certain crates during duplicate +# detection. Unlike skip, it also includes the entire tree of transitive +# dependencies starting at the specified crate, up to a certain depth, which is +# by default infinite. +skip-tree = [ + #"ansi_term@0.11.0", # will be skipped along with _all_ of its direct and transitive dependencies + #{ crate = "ansi_term@0.11.0", depth = 20 }, +] + +# This section is considered when running `cargo deny check sources`. +# More documentation about the 'sources' section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/sources/cfg.html +[sources] +# Lint level for what to happen when a crate from a crate registry that is not +# in the allow list is encountered +unknown-registry = "warn" +# Lint level for what to happen when a crate from a git repository that is not +# in the allow list is encountered +unknown-git = "warn" +# List of URLs for allowed crate registries. Defaults to the crates.io index +# if not specified. If it is specified but empty, no registries are allowed. +allow-registry = ["https://github.com/rust-lang/crates.io-index"] +# List of URLs for allowed Git repositories +allow-git = [] + +[sources.allow-org] +# github.com organizations to allow git sources for +github = ["embassy-rs"] +# gitlab.com organizations to allow git sources for +gitlab = [] +# bitbucket.org organizations to allow git sources for +bitbucket = [] diff --git a/rust-toolchain.toml b/rust-toolchain.toml new file mode 100644 index 000000000..367cc1fc3 --- /dev/null +++ b/rust-toolchain.toml @@ -0,0 +1,2 @@ +[toolchain] +components = ["rustfmt", "clippy"] diff --git a/rustfmt.toml b/rustfmt.toml new file mode 100644 index 000000000..753065179 --- /dev/null +++ b/rustfmt.toml @@ -0,0 +1 @@ +max_width = 120 diff --git a/src/baremetal/mod.rs b/src/baremetal/mod.rs new file mode 100644 index 000000000..c03b9538b --- /dev/null +++ b/src/baremetal/mod.rs @@ -0,0 +1,6 @@ +use core::panic::PanicInfo; + +#[panic_handler] +fn panic(_info: &PanicInfo) -> ! { + loop {} +} diff --git a/src/main.rs b/src/main.rs new file mode 100644 index 000000000..7111536ff --- /dev/null +++ b/src/main.rs @@ -0,0 +1,18 @@ +#![cfg_attr(target_os = "none", no_std)] +#![cfg_attr(target_os = "none", no_main)] + +#[cfg(target_os = "none")] +mod baremetal; + +#[cfg(not(target_os = "none"))] +fn main() { + println!("Hello, world!"); +} + +#[cfg(test)] +mod tests { + #[test] + fn it_works() { + assert_eq!(2 + 2, 4); + } +} diff --git a/supply-chain/README.md b/supply-chain/README.md new file mode 100644 index 000000000..d43d50485 --- /dev/null +++ b/supply-chain/README.md @@ -0,0 +1,83 @@ +# Working with cargo vet + +## Introduction + +`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity. +It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust. +To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet) + +--- + +## Adding a new dependency + +When updating or adding a new dependency, we need to ensure it's audited before being merged into main. +For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository. +_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._ +Follow the process below to ensure compliance: + +### For Developers +1. **Respond to `cargo vet` failures**: + - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire + - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies + +2. **Engage with auditors**: + - Respond to any questions that the auditors might have regarding the need of any new dependencies + +3. **Rebase and verify**: + - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository + - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet` + ```bash + git fetch upstream + git rebase upstream/main + cargo vet + ``` + +4. **Update PR**: + - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR + - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase + ```bash + git push -f + ``` + +5. **Check PR status**: + - The existing PR comment from the previous failure will be updated with a success message once the check passes + +### For Auditors + +1. **Review the questionnaire**: + - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure + - Respond to the developer comment in case more information is needed + +2. **Audit new dependencies**: + - Inspect the `cargo vet` failures using your preferred method + - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked` + - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked` + - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally) + +3. **Follow `cargo vet` recommendations**: + - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies + +4. **Record audits**: + - Use `cargo vet certify` to add new audits to _audits.toml_ + - Verify all dependencies pass using `cargo vet` + +5. **Decide audit location**: + - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) + - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits + +6. **Communicate successful audit**: + - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass + +--- + +## Tips for using `cargo vet`: + +- **Update _imports.lock_**: + - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project. + +- **Add exemptions**: + - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption ` to add the dependency to exemptions in _config.toml_ + - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions` + +- **Prune unnecessary entries**: + - Remove unnecessary exemptions and imports using `cargo vet prune` \ No newline at end of file diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml new file mode 100644 index 000000000..2772ccb21 --- /dev/null +++ b/supply-chain/audits.toml @@ -0,0 +1,4 @@ + +# cargo-vet audits file + +[audits] diff --git a/supply-chain/config.toml b/supply-chain/config.toml new file mode 100644 index 000000000..55618c2ff --- /dev/null +++ b/supply-chain/config.toml @@ -0,0 +1,14 @@ + +# cargo-vet config file + +[cargo-vet] +version = "0.10" + +[imports.OpenDevicePartnership] +url = "https://raw.githubusercontent.com/OpenDevicePartnership/rust-crate-audits/main/audits.toml" + +[imports.google] +url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" + +[imports.mozilla] +url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock new file mode 100644 index 000000000..219dba4ee --- /dev/null +++ b/supply-chain/imports.lock @@ -0,0 +1,8 @@ + +# cargo-vet imports lock + +[audits.OpenDevicePartnership.audits] + +[audits.google.audits] + +[audits.mozilla.audits] -- cgit From 0443134bc47918d2f8f0ede1b292b372629f8894 Mon Sep 17 00:00:00 2001 From: Bogdan Petru Chircu Mare Date: Fri, 31 Oct 2025 21:44:48 -0700 Subject: feat(mcxa276): initial HAL import --- .cargo/config.toml | 19 + .github/workflows/cargo-vet-pr-comment.yml | 137 - .github/workflows/cargo-vet.yml | 53 - .github/workflows/check.yml | 169 - .github/workflows/nostd.yml | 30 - .gitignore | 28 +- .vscode/settings.json | 14 - CODEOWNERS | 1 - CODE_OF_CONDUCT.md | 132 - CONTRIBUTING.md | 35 - Cargo.toml | 126 +- Embed.toml | 28 + LICENSE | 21 - License.txt | 22 + README.md | 63 - README.txt | 340 + SECURITY.md | 66 - SW-Content-Register.txt | 76 + build.rs | 20 + defmt.x | 6 + deny.toml | 239 - examples/adc_interrupt.rs | 106 + examples/adc_polling.rs | 95 + examples/blink.rs | 93 + examples/common/mod.rs | 45 + examples/hello.rs | 126 + examples/lpuart_buffered.rs | 88 + examples/lpuart_polling.rs | 67 + examples/ostimer_alarm.rs | 126 + examples/ostimer_async.rs | 76 + examples/ostimer_counter.rs | 142 + examples/ostimer_race_test.rs | 411 ++ examples/rtc_alarm.rs | 105 + examples/uart_interrupt.rs | 86 + mcxa276-pac/Cargo.toml | 17 + mcxa276-pac/build.rs | 17 + mcxa276-pac/device.x | 129 + mcxa276-pac/device.x.backup | 105 + mcxa276-pac/src/adc0.rs | 448 ++ mcxa276-pac/src/adc0/cal_gar.rs | 35 + mcxa276-pac/src/adc0/cfg.rs | 518 ++ mcxa276-pac/src/adc0/cfg2.rs | 177 + mcxa276-pac/src/adc0/cmdh1.rs | 900 +++ mcxa276-pac/src/adc0/cmdh2.rs | 900 +++ mcxa276-pac/src/adc0/cmdh3.rs | 900 +++ mcxa276-pac/src/adc0/cmdh4.rs | 900 +++ mcxa276-pac/src/adc0/cmdh5.rs | 900 +++ mcxa276-pac/src/adc0/cmdh6.rs | 900 +++ mcxa276-pac/src/adc0/cmdh7.rs | 900 +++ mcxa276-pac/src/adc0/cmdl1.rs | 331 + mcxa276-pac/src/adc0/cmdl2.rs | 323 + mcxa276-pac/src/adc0/cmdl3.rs | 323 + mcxa276-pac/src/adc0/cmdl4.rs | 323 + mcxa276-pac/src/adc0/cmdl5.rs | 323 + mcxa276-pac/src/adc0/cmdl6.rs | 323 + mcxa276-pac/src/adc0/cmdl7.rs | 323 + mcxa276-pac/src/adc0/ctrl.rs | 649 ++ mcxa276-pac/src/adc0/cv.rs | 49 + mcxa276-pac/src/adc0/de.rs | 84 + mcxa276-pac/src/adc0/fctrl0.rs | 42 + mcxa276-pac/src/adc0/gcc0.rs | 61 + mcxa276-pac/src/adc0/gcr0.rs | 100 + mcxa276-pac/src/adc0/hstrim.rs | 35 + mcxa276-pac/src/adc0/ie.rs | 397 ++ mcxa276-pac/src/adc0/ofstrim.rs | 35 + mcxa276-pac/src/adc0/param.rs | 115 + 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+ mcxa276-pac/src/can0/encbt.rs | 63 + mcxa276-pac/src/can0/eprs.rs | 49 + mcxa276-pac/src/can0/erfcr.rs | 140 + mcxa276-pac/src/can0/erffel.rs | 35 + mcxa276-pac/src/can0/erfier.rs | 273 + mcxa276-pac/src/can0/erfsr.rs | 426 ++ mcxa276-pac/src/can0/esr1.rs | 1278 ++++ mcxa276-pac/src/can0/esr2.rs | 102 + mcxa276-pac/src/can0/etdc.rs | 232 + mcxa276-pac/src/can0/fdcbt.rs | 91 + mcxa276-pac/src/can0/fdcrc.rs | 27 + mcxa276-pac/src/can0/fdctrl.rs | 330 + mcxa276-pac/src/can0/flt_dlc.rs | 51 + mcxa276-pac/src/can0/flt_id1.rs | 161 + mcxa276-pac/src/can0/flt_id2_idmask.rs | 161 + mcxa276-pac/src/can0/iflag1.rs | 302 + mcxa276-pac/src/can0/imask1.rs | 35 + mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs | 147 + mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs | 63 + mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs | 147 + mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs | 63 + .../src/can0/mb_16b_group_mb10_16b_word0.rs | 77 + .../src/can0/mb_16b_group_mb10_16b_word1.rs | 77 + .../src/can0/mb_16b_group_mb10_16b_word2.rs | 77 + .../src/can0/mb_16b_group_mb10_16b_word3.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs | 147 + mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs | 63 + .../src/can0/mb_16b_group_mb11_16b_word0.rs | 77 + .../src/can0/mb_16b_group_mb11_16b_word1.rs | 77 + .../src/can0/mb_16b_group_mb11_16b_word2.rs | 77 + .../src/can0/mb_16b_group_mb11_16b_word3.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs | 147 + mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs | 63 + .../src/can0/mb_16b_group_mb12_16b_word0.rs | 77 + .../src/can0/mb_16b_group_mb12_16b_word1.rs | 77 + .../src/can0/mb_16b_group_mb12_16b_word2.rs | 77 + .../src/can0/mb_16b_group_mb12_16b_word3.rs | 77 + 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| 147 + mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs | 63 + .../src/can0/mb_16b_group_mb16_16b_word0.rs | 77 + .../src/can0/mb_16b_group_mb16_16b_word1.rs | 77 + .../src/can0/mb_16b_group_mb16_16b_word2.rs | 77 + .../src/can0/mb_16b_group_mb16_16b_word3.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs | 147 + mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs | 63 + .../src/can0/mb_16b_group_mb17_16b_word0.rs | 77 + .../src/can0/mb_16b_group_mb17_16b_word1.rs | 77 + .../src/can0/mb_16b_group_mb17_16b_word2.rs | 77 + .../src/can0/mb_16b_group_mb17_16b_word3.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs | 147 + mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs | 63 + .../src/can0/mb_16b_group_mb18_16b_word0.rs | 77 + .../src/can0/mb_16b_group_mb18_16b_word1.rs | 77 + .../src/can0/mb_16b_group_mb18_16b_word2.rs | 77 + .../src/can0/mb_16b_group_mb18_16b_word3.rs | 77 + mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs | 147 + 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| 147 + mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb31_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb31_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb3_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb3_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb4_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb4_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb5_8b_cs.rs | 147 + mcxa276-pac/src/can0/mb_8b_group_mb5_8b_id.rs | 63 + mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word0.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word1.rs | 77 + mcxa276-pac/src/can0/mb_8b_group_mb6_8b_cs.rs | 147 + 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mcxa276-pac/src/can0/mb_group_id22.rs | 63 + mcxa276-pac/src/can0/mb_group_id23.rs | 63 + mcxa276-pac/src/can0/mb_group_id24.rs | 63 + mcxa276-pac/src/can0/mb_group_id25.rs | 63 + mcxa276-pac/src/can0/mb_group_id26.rs | 63 + mcxa276-pac/src/can0/mb_group_id27.rs | 63 + mcxa276-pac/src/can0/mb_group_id28.rs | 63 + mcxa276-pac/src/can0/mb_group_id29.rs | 63 + mcxa276-pac/src/can0/mb_group_id3.rs | 63 + mcxa276-pac/src/can0/mb_group_id30.rs | 63 + mcxa276-pac/src/can0/mb_group_id31.rs | 63 + mcxa276-pac/src/can0/mb_group_id4.rs | 63 + mcxa276-pac/src/can0/mb_group_id5.rs | 63 + mcxa276-pac/src/can0/mb_group_id6.rs | 63 + mcxa276-pac/src/can0/mb_group_id7.rs | 63 + mcxa276-pac/src/can0/mb_group_id8.rs | 63 + mcxa276-pac/src/can0/mb_group_id9.rs | 63 + mcxa276-pac/src/can0/mb_group_word00.rs | 77 + mcxa276-pac/src/can0/mb_group_word01.rs | 77 + mcxa276-pac/src/can0/mb_group_word010.rs | 77 + mcxa276-pac/src/can0/mb_group_word011.rs | 77 + mcxa276-pac/src/can0/mb_group_word012.rs | 77 + mcxa276-pac/src/can0/mb_group_word013.rs | 77 + mcxa276-pac/src/can0/mb_group_word014.rs | 77 + mcxa276-pac/src/can0/mb_group_word015.rs | 77 + mcxa276-pac/src/can0/mb_group_word016.rs | 77 + mcxa276-pac/src/can0/mb_group_word017.rs | 77 + mcxa276-pac/src/can0/mb_group_word018.rs | 77 + mcxa276-pac/src/can0/mb_group_word019.rs | 77 + mcxa276-pac/src/can0/mb_group_word02.rs | 77 + mcxa276-pac/src/can0/mb_group_word020.rs | 77 + mcxa276-pac/src/can0/mb_group_word021.rs | 77 + mcxa276-pac/src/can0/mb_group_word022.rs | 77 + mcxa276-pac/src/can0/mb_group_word023.rs | 77 + mcxa276-pac/src/can0/mb_group_word024.rs | 77 + mcxa276-pac/src/can0/mb_group_word025.rs | 77 + mcxa276-pac/src/can0/mb_group_word026.rs | 77 + mcxa276-pac/src/can0/mb_group_word027.rs | 77 + mcxa276-pac/src/can0/mb_group_word028.rs | 77 + mcxa276-pac/src/can0/mb_group_word029.rs | 77 + mcxa276-pac/src/can0/mb_group_word03.rs | 77 + mcxa276-pac/src/can0/mb_group_word030.rs | 77 + mcxa276-pac/src/can0/mb_group_word031.rs | 77 + mcxa276-pac/src/can0/mb_group_word04.rs | 77 + mcxa276-pac/src/can0/mb_group_word05.rs | 77 + mcxa276-pac/src/can0/mb_group_word06.rs | 77 + mcxa276-pac/src/can0/mb_group_word07.rs | 77 + mcxa276-pac/src/can0/mb_group_word08.rs | 77 + mcxa276-pac/src/can0/mb_group_word09.rs | 77 + mcxa276-pac/src/can0/mb_group_word10.rs | 77 + mcxa276-pac/src/can0/mb_group_word11.rs | 77 + mcxa276-pac/src/can0/mb_group_word110.rs | 77 + mcxa276-pac/src/can0/mb_group_word111.rs | 77 + mcxa276-pac/src/can0/mb_group_word112.rs | 77 + mcxa276-pac/src/can0/mb_group_word113.rs | 77 + mcxa276-pac/src/can0/mb_group_word114.rs | 77 + mcxa276-pac/src/can0/mb_group_word115.rs | 77 + mcxa276-pac/src/can0/mb_group_word116.rs | 77 + mcxa276-pac/src/can0/mb_group_word117.rs | 77 + mcxa276-pac/src/can0/mb_group_word118.rs | 77 + mcxa276-pac/src/can0/mb_group_word119.rs | 77 + mcxa276-pac/src/can0/mb_group_word12.rs | 77 + mcxa276-pac/src/can0/mb_group_word120.rs | 77 + mcxa276-pac/src/can0/mb_group_word121.rs | 77 + mcxa276-pac/src/can0/mb_group_word122.rs | 77 + mcxa276-pac/src/can0/mb_group_word123.rs | 77 + mcxa276-pac/src/can0/mb_group_word124.rs | 77 + mcxa276-pac/src/can0/mb_group_word125.rs | 77 + mcxa276-pac/src/can0/mb_group_word126.rs | 77 + mcxa276-pac/src/can0/mb_group_word127.rs | 77 + mcxa276-pac/src/can0/mb_group_word128.rs | 77 + mcxa276-pac/src/can0/mb_group_word129.rs | 77 + mcxa276-pac/src/can0/mb_group_word13.rs | 77 + mcxa276-pac/src/can0/mb_group_word130.rs | 77 + mcxa276-pac/src/can0/mb_group_word131.rs | 77 + mcxa276-pac/src/can0/mb_group_word14.rs | 77 + mcxa276-pac/src/can0/mb_group_word15.rs | 77 + mcxa276-pac/src/can0/mb_group_word16.rs | 77 + mcxa276-pac/src/can0/mb_group_word17.rs | 77 + mcxa276-pac/src/can0/mb_group_word18.rs | 77 + mcxa276-pac/src/can0/mb_group_word19.rs | 77 + mcxa276-pac/src/can0/mcr.rs | 1390 ++++ mcxa276-pac/src/can0/pl1_hi.rs | 77 + mcxa276-pac/src/can0/pl1_lo.rs | 77 + mcxa276-pac/src/can0/pl2_plmask_hi.rs | 77 + mcxa276-pac/src/can0/pl2_plmask_lo.rs | 77 + mcxa276-pac/src/can0/rx14mask.rs | 35 + mcxa276-pac/src/can0/rx15mask.rs | 35 + mcxa276-pac/src/can0/rxfgmask.rs | 35 + mcxa276-pac/src/can0/rxfir.rs | 20 + mcxa276-pac/src/can0/rximr.rs | 35 + mcxa276-pac/src/can0/rxmgmask.rs | 35 + mcxa276-pac/src/can0/timer.rs | 35 + mcxa276-pac/src/can0/wmb.rs | 51 + mcxa276-pac/src/can0/wmb/wmb_cs.rs | 143 + mcxa276-pac/src/can0/wmb/wmb_d03.rs | 41 + mcxa276-pac/src/can0/wmb/wmb_d47.rs | 41 + mcxa276-pac/src/can0/wmb/wmb_id.rs | 20 + mcxa276-pac/src/can0/wu_mtc.rs | 155 + mcxa276-pac/src/cdog0.rs | 216 + mcxa276-pac/src/cdog0/add.rs | 22 + mcxa276-pac/src/cdog0/add1.rs | 22 + mcxa276-pac/src/cdog0/add16.rs | 22 + mcxa276-pac/src/cdog0/add256.rs | 22 + mcxa276-pac/src/cdog0/assert16.rs | 22 + mcxa276-pac/src/cdog0/control.rs | 648 ++ mcxa276-pac/src/cdog0/flags.rs | 465 ++ mcxa276-pac/src/cdog0/instruction_timer.rs | 22 + mcxa276-pac/src/cdog0/persistent.rs | 35 + mcxa276-pac/src/cdog0/reload.rs | 37 + mcxa276-pac/src/cdog0/restart.rs | 22 + mcxa276-pac/src/cdog0/start.rs | 22 + mcxa276-pac/src/cdog0/status.rs | 43 + mcxa276-pac/src/cdog0/status2.rs | 34 + mcxa276-pac/src/cdog0/stop.rs | 22 + mcxa276-pac/src/cdog0/sub.rs | 22 + mcxa276-pac/src/cdog0/sub1.rs | 22 + mcxa276-pac/src/cdog0/sub16.rs | 22 + mcxa276-pac/src/cdog0/sub256.rs | 22 + mcxa276-pac/src/cmc.rs | 189 + mcxa276-pac/src/cmc/ckctrl.rs | 167 + mcxa276-pac/src/cmc/ckstat.rs | 147 + mcxa276-pac/src/cmc/corectl.rs | 84 + mcxa276-pac/src/cmc/dbgctl.rs | 84 + mcxa276-pac/src/cmc/flashcr.rs | 210 + mcxa276-pac/src/cmc/fm0.rs | 84 + mcxa276-pac/src/cmc/gpmctrl.rs | 35 + mcxa276-pac/src/cmc/mr0.rs | 36 + mcxa276-pac/src/cmc/pmctrlmain.rs | 117 + mcxa276-pac/src/cmc/pmprot.rs | 336 + mcxa276-pac/src/cmc/rpc.rs | 161 + mcxa276-pac/src/cmc/srie.rs | 590 ++ mcxa276-pac/src/cmc/srif.rs | 526 ++ mcxa276-pac/src/cmc/srs.rs | 710 ++ mcxa276-pac/src/cmc/ssrs.rs | 1073 +++ mcxa276-pac/src/cmc/verid.rs | 36 + mcxa276-pac/src/cmp0.rs | 151 + mcxa276-pac/src/cmp0/ccr0.rs | 149 + mcxa276-pac/src/cmp0/ccr1.rs | 992 +++ mcxa276-pac/src/cmp0/ccr2.rs | 513 ++ mcxa276-pac/src/cmp0/csr.rs | 218 + mcxa276-pac/src/cmp0/dcr.rs | 224 + mcxa276-pac/src/cmp0/ier.rs | 210 + mcxa276-pac/src/cmp0/param.rs | 102 + mcxa276-pac/src/cmp0/rrcr0.rs | 1018 +++ mcxa276-pac/src/cmp0/rrcr1.rs | 736 ++ mcxa276-pac/src/cmp0/rrcr2.rs | 98 + mcxa276-pac/src/cmp0/rrcsr.rs | 133 + mcxa276-pac/src/cmp0/rrsr.rs | 526 ++ mcxa276-pac/src/cmp0/verid.rs | 68 + mcxa276-pac/src/crc0.rs | 39 + mcxa276-pac/src/crc0/ctrl.rs | 402 ++ mcxa276-pac/src/crc0/data.rs | 79 + mcxa276-pac/src/crc0/gpoly.rs | 51 + mcxa276-pac/src/ctimer0.rs | 168 + mcxa276-pac/src/ctimer0/ccr.rs | 777 +++ mcxa276-pac/src/ctimer0/cr.rs | 20 + mcxa276-pac/src/ctimer0/ctcr.rs | 375 + mcxa276-pac/src/ctimer0/emr.rs | 657 ++ mcxa276-pac/src/ctimer0/ir.rs | 133 + mcxa276-pac/src/ctimer0/mcr.rs | 1029 +++ mcxa276-pac/src/ctimer0/mr.rs | 35 + mcxa276-pac/src/ctimer0/msr.rs | 35 + mcxa276-pac/src/ctimer0/pc.rs | 35 + mcxa276-pac/src/ctimer0/pr.rs | 35 + mcxa276-pac/src/ctimer0/pwmc.rs | 273 + mcxa276-pac/src/ctimer0/tc.rs | 35 + mcxa276-pac/src/ctimer0/tcr.rs | 273 + mcxa276-pac/src/dac0.rs | 138 + mcxa276-pac/src/dac0/data.rs | 35 + mcxa276-pac/src/dac0/der.rs | 147 + mcxa276-pac/src/dac0/fcr.rs | 35 + mcxa276-pac/src/dac0/fpr.rs | 27 + mcxa276-pac/src/dac0/fsr.rs | 399 ++ mcxa276-pac/src/dac0/gcr.rs | 687 ++ mcxa276-pac/src/dac0/ier.rs | 462 ++ mcxa276-pac/src/dac0/param.rs | 102 + mcxa276-pac/src/dac0/pcr.rs | 49 + mcxa276-pac/src/dac0/rcr.rs | 147 + mcxa276-pac/src/dac0/tcr.rs | 84 + mcxa276-pac/src/dac0/verid.rs | 36 + mcxa276-pac/src/dbgmailbox.rs | 51 + mcxa276-pac/src/dbgmailbox/csw.rs | 399 ++ mcxa276-pac/src/dbgmailbox/id.rs | 22 + mcxa276-pac/src/dbgmailbox/request.rs | 35 + mcxa276-pac/src/dbgmailbox/return_.rs | 35 + mcxa276-pac/src/dma0.rs | 68 + mcxa276-pac/src/dma0/ch_grpri.rs | 35 + mcxa276-pac/src/dma0/mp_csr.rs | 575 ++ mcxa276-pac/src/dma0/mp_es.rs | 430 ++ mcxa276-pac/src/dma0/mp_hrs.rs | 20 + mcxa276-pac/src/dma0/mp_int.rs | 20 + mcxa276-pac/src/edma_0_tcd0.rs | 26 + mcxa276-pac/src/edma_0_tcd0/tcd.rs | 229 + mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs | 295 + mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs | 413 ++ mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs | 85 + mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs | 35 + mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs | 161 + mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs | 134 + .../edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs | 98 + .../edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs | 98 + .../edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs | 112 + .../edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs | 112 + .../edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs | 161 + .../tcd/mloffyes_tcd_nbytes_mloffyes.rs | 175 + mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs | 241 + mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs | 622 ++ mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs | 35 + mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs | 35 + mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs | 35 + mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs | 35 + mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs | 35 + mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs | 35 + mcxa276-pac/src/eim0.rs | 51 + mcxa276-pac/src/eim0/eichd0_word0.rs | 35 + mcxa276-pac/src/eim0/eichd0_word1.rs | 35 + mcxa276-pac/src/eim0/eichen.rs | 84 + mcxa276-pac/src/eim0/eimcr.rs | 84 + mcxa276-pac/src/eqdc0.rs | 441 ++ mcxa276-pac/src/eqdc0/ctrl.rs | 1030 +++ mcxa276-pac/src/eqdc0/ctrl2.rs | 567 ++ mcxa276-pac/src/eqdc0/filt.rs | 126 + mcxa276-pac/src/eqdc0/imr.rs | 317 + mcxa276-pac/src/eqdc0/intctrl.rs | 1030 +++ mcxa276-pac/src/eqdc0/lastedge.rs | 22 + mcxa276-pac/src/eqdc0/lastedgeh.rs | 22 + mcxa276-pac/src/eqdc0/lcomp0.rs | 35 + mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs | 22 + mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs | 22 + mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs | 22 + mcxa276-pac/src/eqdc0/linit.rs | 35 + mcxa276-pac/src/eqdc0/lmod.rs | 35 + mcxa276-pac/src/eqdc0/lpos.rs | 35 + mcxa276-pac/src/eqdc0/lposh.rs | 20 + mcxa276-pac/src/eqdc0/lposh1_lposh1.rs | 20 + mcxa276-pac/src/eqdc0/lposh2_lposh2.rs | 20 + mcxa276-pac/src/eqdc0/lposh3_lposh3.rs | 20 + mcxa276-pac/src/eqdc0/lverid.rs | 22 + mcxa276-pac/src/eqdc0/posd.rs | 35 + mcxa276-pac/src/eqdc0/posdh.rs | 20 + mcxa276-pac/src/eqdc0/posdper.rs | 22 + mcxa276-pac/src/eqdc0/posdperbfr.rs | 22 + mcxa276-pac/src/eqdc0/posdperh.rs | 22 + mcxa276-pac/src/eqdc0/rev.rs | 35 + mcxa276-pac/src/eqdc0/revh.rs | 20 + mcxa276-pac/src/eqdc0/tst.rs | 238 + mcxa276-pac/src/eqdc0/ucomp0.rs | 37 + mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs | 24 + mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs | 24 + mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs | 24 + mcxa276-pac/src/eqdc0/uinit.rs | 35 + mcxa276-pac/src/eqdc0/umod.rs | 35 + mcxa276-pac/src/eqdc0/upos.rs | 35 + mcxa276-pac/src/eqdc0/uposh.rs | 20 + mcxa276-pac/src/eqdc0/uposh1_uposh1.rs | 20 + mcxa276-pac/src/eqdc0/uposh2_uposh2.rs | 20 + mcxa276-pac/src/eqdc0/uposh3_uposh3.rs | 20 + mcxa276-pac/src/eqdc0/uverid.rs | 22 + mcxa276-pac/src/eqdc0/wtr.rs | 35 + mcxa276-pac/src/erm0.rs | 75 + mcxa276-pac/src/erm0/corr_err_cnt0.rs | 35 + mcxa276-pac/src/erm0/corr_err_cnt1.rs | 35 + mcxa276-pac/src/erm0/cr0.rs | 273 + mcxa276-pac/src/erm0/ear0.rs | 20 + mcxa276-pac/src/erm0/sr0.rs | 274 + mcxa276-pac/src/erm0/syn0.rs | 20 + mcxa276-pac/src/flexio0.rs | 556 ++ mcxa276-pac/src/flexio0/ctrl.rs | 336 + mcxa276-pac/src/flexio0/param.rs | 43 + mcxa276-pac/src/flexio0/pin.rs | 20 + mcxa276-pac/src/flexio0/pinfen.rs | 35 + mcxa276-pac/src/flexio0/pinien.rs | 35 + mcxa276-pac/src/flexio0/pinoutclr.rs | 35 + mcxa276-pac/src/flexio0/pinoutd.rs | 35 + mcxa276-pac/src/flexio0/pinoutdis.rs | 35 + mcxa276-pac/src/flexio0/pinoute.rs | 35 + mcxa276-pac/src/flexio0/pinoutset.rs | 35 + mcxa276-pac/src/flexio0/pinouttog.rs | 35 + mcxa276-pac/src/flexio0/pinren.rs | 35 + mcxa276-pac/src/flexio0/pinstat.rs | 92 + mcxa276-pac/src/flexio0/shiftbuf.rs | 35 + mcxa276-pac/src/flexio0/shiftbufbbs.rs | 35 + mcxa276-pac/src/flexio0/shiftbufbis.rs | 35 + mcxa276-pac/src/flexio0/shiftbufbys.rs | 35 + mcxa276-pac/src/flexio0/shiftbufeos.rs | 35 + mcxa276-pac/src/flexio0/shiftbufhbs.rs | 35 + mcxa276-pac/src/flexio0/shiftbufhws.rs | 35 + mcxa276-pac/src/flexio0/shiftbufnbs.rs | 35 + mcxa276-pac/src/flexio0/shiftbufnis.rs | 35 + mcxa276-pac/src/flexio0/shiftbufoes.rs | 35 + mcxa276-pac/src/flexio0/shiftcfg.rs | 416 ++ mcxa276-pac/src/flexio0/shiftctl.rs | 406 ++ mcxa276-pac/src/flexio0/shifteien.rs | 35 + mcxa276-pac/src/flexio0/shifterr.rs | 92 + mcxa276-pac/src/flexio0/shiftsden.rs | 35 + mcxa276-pac/src/flexio0/shiftsien.rs | 35 + mcxa276-pac/src/flexio0/shiftstat.rs | 92 + mcxa276-pac/src/flexio0/shiftstate.rs | 35 + mcxa276-pac/src/flexio0/timcfg.rs | 842 +++ mcxa276-pac/src/flexio0/timcmp.rs | 35 + mcxa276-pac/src/flexio0/timctl.rs | 608 ++ mcxa276-pac/src/flexio0/timersden.rs | 35 + mcxa276-pac/src/flexio0/timien.rs | 35 + mcxa276-pac/src/flexio0/timstat.rs | 92 + mcxa276-pac/src/flexio0/trgstat.rs | 92 + mcxa276-pac/src/flexio0/trigien.rs | 35 + mcxa276-pac/src/flexio0/verid.rs | 92 + mcxa276-pac/src/flexpwm0.rs | 1303 ++++ mcxa276-pac/src/flexpwm0/dtsrcsel.rs | 737 ++ mcxa276-pac/src/flexpwm0/fctrl0.rs | 301 + mcxa276-pac/src/flexpwm0/fctrl20.rs | 91 + mcxa276-pac/src/flexpwm0/ffilt0.rs | 112 + mcxa276-pac/src/flexpwm0/fsts0.rs | 238 + mcxa276-pac/src/flexpwm0/ftst0.rs | 84 + mcxa276-pac/src/flexpwm0/mask.rs | 70 + mcxa276-pac/src/flexpwm0/mctrl.rs | 245 + mcxa276-pac/src/flexpwm0/mctrl2.rs | 213 + mcxa276-pac/src/flexpwm0/outen.rs | 63 + mcxa276-pac/src/flexpwm0/sm0captcompx.rs | 42 + mcxa276-pac/src/flexpwm0/sm0captctrlx.rs | 493 ++ mcxa276-pac/src/flexpwm0/sm0captfiltx.rs | 49 + mcxa276-pac/src/flexpwm0/sm0cnt.rs | 20 + mcxa276-pac/src/flexpwm0/sm0ctrl.rs | 871 +++ mcxa276-pac/src/flexpwm0/sm0ctrl2.rs | 607 ++ mcxa276-pac/src/flexpwm0/sm0cval0.rs | 20 + mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm0cval1.rs | 20 + mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm0dismap0.rs | 65 + mcxa276-pac/src/flexpwm0/sm0dmaen.rs | 271 + mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs | 37 + mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs | 37 + mcxa276-pac/src/flexpwm0/sm0init.rs | 35 + mcxa276-pac/src/flexpwm0/sm0inten.rs | 343 + mcxa276-pac/src/flexpwm0/sm0octrl.rs | 519 ++ mcxa276-pac/src/flexpwm0/sm0sts.rs | 287 + mcxa276-pac/src/flexpwm0/sm0tctrl.rs | 267 + mcxa276-pac/src/flexpwm0/sm0val0.rs | 35 + mcxa276-pac/src/flexpwm0/sm0val1.rs | 35 + mcxa276-pac/src/flexpwm0/sm0val2.rs | 35 + mcxa276-pac/src/flexpwm0/sm0val3.rs | 35 + mcxa276-pac/src/flexpwm0/sm0val4.rs | 35 + mcxa276-pac/src/flexpwm0/sm0val5.rs | 35 + mcxa276-pac/src/flexpwm0/sm1captcompx.rs | 42 + mcxa276-pac/src/flexpwm0/sm1captctrlx.rs | 493 ++ mcxa276-pac/src/flexpwm0/sm1captfiltx.rs | 49 + mcxa276-pac/src/flexpwm0/sm1cnt.rs | 20 + mcxa276-pac/src/flexpwm0/sm1ctrl.rs | 871 +++ mcxa276-pac/src/flexpwm0/sm1ctrl2.rs | 607 ++ mcxa276-pac/src/flexpwm0/sm1cval0.rs | 20 + mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm1cval1.rs | 20 + mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm1dismap0.rs | 65 + mcxa276-pac/src/flexpwm0/sm1dmaen.rs | 271 + mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs | 37 + mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs | 37 + mcxa276-pac/src/flexpwm0/sm1init.rs | 35 + mcxa276-pac/src/flexpwm0/sm1inten.rs | 343 + mcxa276-pac/src/flexpwm0/sm1octrl.rs | 519 ++ mcxa276-pac/src/flexpwm0/sm1phasedly.rs | 35 + mcxa276-pac/src/flexpwm0/sm1sts.rs | 287 + mcxa276-pac/src/flexpwm0/sm1tctrl.rs | 267 + mcxa276-pac/src/flexpwm0/sm1val0.rs | 35 + mcxa276-pac/src/flexpwm0/sm1val1.rs | 35 + mcxa276-pac/src/flexpwm0/sm1val2.rs | 35 + mcxa276-pac/src/flexpwm0/sm1val3.rs | 35 + mcxa276-pac/src/flexpwm0/sm1val4.rs | 35 + mcxa276-pac/src/flexpwm0/sm1val5.rs | 35 + mcxa276-pac/src/flexpwm0/sm2captcompx.rs | 42 + mcxa276-pac/src/flexpwm0/sm2captctrlx.rs | 493 ++ mcxa276-pac/src/flexpwm0/sm2captfiltx.rs | 49 + mcxa276-pac/src/flexpwm0/sm2cnt.rs | 20 + mcxa276-pac/src/flexpwm0/sm2ctrl.rs | 871 +++ mcxa276-pac/src/flexpwm0/sm2ctrl2.rs | 607 ++ mcxa276-pac/src/flexpwm0/sm2cval0.rs | 20 + mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm2cval1.rs | 20 + mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm2dismap0.rs | 65 + mcxa276-pac/src/flexpwm0/sm2dmaen.rs | 271 + mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs | 37 + mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs | 37 + mcxa276-pac/src/flexpwm0/sm2init.rs | 35 + mcxa276-pac/src/flexpwm0/sm2inten.rs | 343 + mcxa276-pac/src/flexpwm0/sm2octrl.rs | 519 ++ mcxa276-pac/src/flexpwm0/sm2phasedly.rs | 35 + mcxa276-pac/src/flexpwm0/sm2sts.rs | 287 + mcxa276-pac/src/flexpwm0/sm2tctrl.rs | 267 + mcxa276-pac/src/flexpwm0/sm2val0.rs | 35 + mcxa276-pac/src/flexpwm0/sm2val1.rs | 35 + mcxa276-pac/src/flexpwm0/sm2val2.rs | 35 + mcxa276-pac/src/flexpwm0/sm2val3.rs | 35 + mcxa276-pac/src/flexpwm0/sm2val4.rs | 35 + mcxa276-pac/src/flexpwm0/sm2val5.rs | 35 + mcxa276-pac/src/flexpwm0/sm3captcompx.rs | 42 + mcxa276-pac/src/flexpwm0/sm3captctrlx.rs | 493 ++ mcxa276-pac/src/flexpwm0/sm3captfiltx.rs | 49 + mcxa276-pac/src/flexpwm0/sm3cnt.rs | 20 + mcxa276-pac/src/flexpwm0/sm3ctrl.rs | 871 +++ mcxa276-pac/src/flexpwm0/sm3ctrl2.rs | 607 ++ mcxa276-pac/src/flexpwm0/sm3cval0.rs | 20 + mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm3cval1.rs | 20 + mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs | 20 + mcxa276-pac/src/flexpwm0/sm3dismap0.rs | 65 + mcxa276-pac/src/flexpwm0/sm3dmaen.rs | 271 + mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs | 37 + mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs | 37 + mcxa276-pac/src/flexpwm0/sm3init.rs | 35 + mcxa276-pac/src/flexpwm0/sm3inten.rs | 343 + mcxa276-pac/src/flexpwm0/sm3octrl.rs | 519 ++ mcxa276-pac/src/flexpwm0/sm3phasedly.rs | 35 + mcxa276-pac/src/flexpwm0/sm3sts.rs | 287 + mcxa276-pac/src/flexpwm0/sm3tctrl.rs | 267 + mcxa276-pac/src/flexpwm0/sm3val0.rs | 35 + mcxa276-pac/src/flexpwm0/sm3val1.rs | 35 + mcxa276-pac/src/flexpwm0/sm3val2.rs | 35 + mcxa276-pac/src/flexpwm0/sm3val3.rs | 35 + mcxa276-pac/src/flexpwm0/sm3val4.rs | 35 + mcxa276-pac/src/flexpwm0/sm3val5.rs | 35 + mcxa276-pac/src/flexpwm0/swcout.rs | 525 ++ mcxa276-pac/src/fmc0.rs | 18 + mcxa276-pac/src/fmc0/remap.rs | 112 + mcxa276-pac/src/fmu0.rs | 57 + mcxa276-pac/src/fmu0/fccob.rs | 35 + mcxa276-pac/src/fmu0/fcnfg.rs | 282 + mcxa276-pac/src/fmu0/fctrl.rs | 226 + mcxa276-pac/src/fmu0/fstat.rs | 713 ++ mcxa276-pac/src/freqme0.rs | 60 + mcxa276-pac/src/freqme0/ctrlstat.rs | 505 ++ mcxa276-pac/src/freqme0/max.rs | 37 + mcxa276-pac/src/freqme0/min.rs | 35 + mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs | 61 + mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs | 274 + mcxa276-pac/src/generic.rs | 768 +++ mcxa276-pac/src/generic/raw.rs | 95 + mcxa276-pac/src/glikey0.rs | 62 + mcxa276-pac/src/glikey0/ctrl_0.rs | 128 + mcxa276-pac/src/glikey0/ctrl_1.rs | 79 + mcxa276-pac/src/glikey0/intr_ctrl.rs | 119 + mcxa276-pac/src/glikey0/status.rs | 198 + mcxa276-pac/src/glikey0/version.rs | 71 + mcxa276-pac/src/gpio0.rs | 175 + mcxa276-pac/src/gpio0/gichr.rs | 1043 +++ mcxa276-pac/src/gpio0/giclr.rs | 1043 +++ mcxa276-pac/src/gpio0/icr.rs | 311 + mcxa276-pac/src/gpio0/isfr0.rs | 2038 ++++++ mcxa276-pac/src/gpio0/param.rs | 22 + mcxa276-pac/src/gpio0/pcor.rs | 2037 ++++++ mcxa276-pac/src/gpio0/pddr.rs | 2037 ++++++ mcxa276-pac/src/gpio0/pdir.rs | 1325 ++++ mcxa276-pac/src/gpio0/pdor.rs | 2037 ++++++ mcxa276-pac/src/gpio0/pdr.rs | 84 + mcxa276-pac/src/gpio0/pidr.rs | 2037 ++++++ mcxa276-pac/src/gpio0/psor.rs | 2037 ++++++ mcxa276-pac/src/gpio0/ptor.rs | 2037 ++++++ mcxa276-pac/src/gpio0/verid.rs | 76 + mcxa276-pac/src/i3c0.rs | 639 ++ mcxa276-pac/src/i3c0/byte_mwdatab1.rs | 22 + mcxa276-pac/src/i3c0/byte_swdatab1.rs | 22 + .../src/i3c0/control2_mwmsg_ddr_control2.rs | 58 + mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs | 22 + mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs | 137 + mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs | 22 + mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs | 22 + mcxa276-pac/src/i3c0/halfword_mwdatah1.rs | 22 + mcxa276-pac/src/i3c0/halfword_swdatah1.rs | 22 + mcxa276-pac/src/i3c0/ibiext1.rs | 86 + mcxa276-pac/src/i3c0/ibiext2.rs | 77 + mcxa276-pac/src/i3c0/mconfig.rs | 472 ++ mcxa276-pac/src/i3c0/mconfig_ext.rs | 213 + mcxa276-pac/src/i3c0/mctrl.rs | 426 ++ mcxa276-pac/src/i3c0/mdatactrl.rs | 419 ++ mcxa276-pac/src/i3c0/mdmactrl.rs | 272 + mcxa276-pac/src/i3c0/mdynaddr.rs | 98 + mcxa276-pac/src/i3c0/merrwarn.rs | 715 ++ mcxa276-pac/src/i3c0/mibirules.rs | 217 + mcxa276-pac/src/i3c0/mintclr.rs | 526 ++ mcxa276-pac/src/i3c0/mintmasked.rs | 307 + mcxa276-pac/src/i3c0/mintset.rs | 477 ++ mcxa276-pac/src/i3c0/mrdatab.rs | 20 + mcxa276-pac/src/i3c0/mrdatah.rs | 27 + mcxa276-pac/src/i3c0/mrmsg_ddr.rs | 20 + mcxa276-pac/src/i3c0/mrmsg_sdr.rs | 20 + mcxa276-pac/src/i3c0/mstatus.rs | 709 ++ mcxa276-pac/src/i3c0/mwdatab.rs | 94 + mcxa276-pac/src/i3c0/mwdatabe.rs | 22 + mcxa276-pac/src/i3c0/mwdatah.rs | 65 + mcxa276-pac/src/i3c0/mwdatahe.rs | 29 + mcxa276-pac/src/i3c0/scapabilities.rs | 674 ++ mcxa276-pac/src/i3c0/scapabilities2.rs | 413 ++ mcxa276-pac/src/i3c0/sconfig.rs | 429 ++ mcxa276-pac/src/i3c0/sctrl.rs | 236 + mcxa276-pac/src/i3c0/sdatactrl.rs | 419 ++ mcxa276-pac/src/i3c0/sdmactrl.rs | 272 + mcxa276-pac/src/i3c0/sdynaddr.rs | 126 + mcxa276-pac/src/i3c0/serrwarn.rs | 715 ++ mcxa276-pac/src/i3c0/sid.rs | 22 + mcxa276-pac/src/i3c0/sidext.rs | 51 + mcxa276-pac/src/i3c0/sidpartno.rs | 37 + mcxa276-pac/src/i3c0/sintclr.rs | 176 + mcxa276-pac/src/i3c0/sintmasked.rs | 90 + mcxa276-pac/src/i3c0/sintset.rs | 715 ++ mcxa276-pac/src/i3c0/smapctrl0.rs | 132 + mcxa276-pac/src/i3c0/smaxlimits.rs | 49 + mcxa276-pac/src/i3c0/smsgmapaddr.rs | 75 + mcxa276-pac/src/i3c0/srdatab.rs | 20 + mcxa276-pac/src/i3c0/srdatah.rs | 27 + mcxa276-pac/src/i3c0/sstatus.rs | 1216 ++++ mcxa276-pac/src/i3c0/stcclock.rs | 51 + mcxa276-pac/src/i3c0/svendorid.rs | 37 + mcxa276-pac/src/i3c0/swdatab.rs | 94 + mcxa276-pac/src/i3c0/swdatabe.rs | 22 + mcxa276-pac/src/i3c0/swdatah.rs | 65 + mcxa276-pac/src/i3c0/swdatahe.rs | 29 + mcxa276-pac/src/inputmux0.rs | 1012 +++ mcxa276-pac/src/inputmux0/adc0_trig.rs | 782 +++ mcxa276-pac/src/inputmux0/adc1_trig.rs | 782 +++ mcxa276-pac/src/inputmux0/adc2_trig.rs | 782 +++ mcxa276-pac/src/inputmux0/adc3_trig.rs | 782 +++ mcxa276-pac/src/inputmux0/aoi0_input.rs | 1302 ++++ mcxa276-pac/src/inputmux0/aoi1_input.rs | 1302 ++++ mcxa276-pac/src/inputmux0/cmp0_trig.rs | 652 ++ mcxa276-pac/src/inputmux0/cmp1_trig.rs | 652 ++ mcxa276-pac/src/inputmux0/cmp2_trig.rs | 652 ++ mcxa276-pac/src/inputmux0/ctimer0cap.rs | 1471 ++++ mcxa276-pac/src/inputmux0/ctimer1cap.rs | 1471 ++++ mcxa276-pac/src/inputmux0/ctimer2cap.rs | 1471 ++++ mcxa276-pac/src/inputmux0/ctimer3cap.rs | 1627 +++++ mcxa276-pac/src/inputmux0/ctimer4cap.rs | 1627 +++++ mcxa276-pac/src/inputmux0/dac0_trig.rs | 652 ++ mcxa276-pac/src/inputmux0/ext_trig.rs | 288 + mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_force.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_force.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs | 808 +++ mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs | 808 +++ mcxa276-pac/src/inputmux0/flexio_trig.rs | 1094 +++ mcxa276-pac/src/inputmux0/freqmeas_ref.rs | 418 ++ mcxa276-pac/src/inputmux0/freqmeas_tar.rs | 418 ++ mcxa276-pac/src/inputmux0/lpi2c0_trig.rs | 587 ++ mcxa276-pac/src/inputmux0/lpi2c1_trig.rs | 587 ++ mcxa276-pac/src/inputmux0/lpi2c2_trig.rs | 587 ++ mcxa276-pac/src/inputmux0/lpi2c3_trig.rs | 587 ++ mcxa276-pac/src/inputmux0/lpspi0_trig.rs | 587 ++ mcxa276-pac/src/inputmux0/lpspi1_trig.rs | 587 ++ mcxa276-pac/src/inputmux0/lpuart0.rs | 652 ++ mcxa276-pac/src/inputmux0/lpuart1.rs | 652 ++ mcxa276-pac/src/inputmux0/lpuart2.rs | 652 ++ mcxa276-pac/src/inputmux0/lpuart3.rs | 652 ++ mcxa276-pac/src/inputmux0/lpuart4.rs | 652 ++ mcxa276-pac/src/inputmux0/lpuart5.rs | 652 ++ mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs | 171 + mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs | 171 + mcxa276-pac/src/inputmux0/qdc0_home.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc0_icap1.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc0_icap2.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc0_icap3.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc0_index.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc0_phasea.rs | 756 +++ mcxa276-pac/src/inputmux0/qdc0_phaseb.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc0_trig.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_home.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_icap1.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_icap2.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_icap3.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_index.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_phasea.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_phaseb.rs | 782 +++ mcxa276-pac/src/inputmux0/qdc1_trig.rs | 782 +++ mcxa276-pac/src/inputmux0/smart_dma_trig.rs | 1081 +++ mcxa276-pac/src/inputmux0/timer0trig.rs | 1471 ++++ mcxa276-pac/src/inputmux0/timer1trig.rs | 1471 ++++ mcxa276-pac/src/inputmux0/timer2trig.rs | 1471 ++++ mcxa276-pac/src/inputmux0/timer3trig.rs | 1627 +++++ mcxa276-pac/src/inputmux0/timer4trig.rs | 1627 +++++ mcxa276-pac/src/inputmux0/trigfil.rs | 49 + mcxa276-pac/src/inputmux0/trigfil_prsc.rs | 180 + mcxa276-pac/src/inputmux0/trigfil_stat0.rs | 505 ++ mcxa276-pac/src/inputmux0/usbfs_trig.rs | 145 + mcxa276-pac/src/lib.rs | 1555 +++++ mcxa276-pac/src/lpi2c0.rs | 360 + mcxa276-pac/src/lpi2c0/mccr0.rs | 77 + mcxa276-pac/src/lpi2c0/mccr1.rs | 77 + mcxa276-pac/src/lpi2c0/mcfgr0.rs | 525 ++ mcxa276-pac/src/lpi2c0/mcfgr1.rs | 767 +++ mcxa276-pac/src/lpi2c0/mcfgr2.rs | 63 + mcxa276-pac/src/lpi2c0/mcfgr3.rs | 35 + mcxa276-pac/src/lpi2c0/mcr.rs | 399 ++ mcxa276-pac/src/lpi2c0/mder.rs | 147 + mcxa276-pac/src/lpi2c0/mdmr.rs | 49 + mcxa276-pac/src/lpi2c0/mfcr.rs | 49 + mcxa276-pac/src/lpi2c0/mfsr.rs | 27 + mcxa276-pac/src/lpi2c0/mier.rs | 651 ++ mcxa276-pac/src/lpi2c0/mrdr.rs | 63 + mcxa276-pac/src/lpi2c0/mrdror.rs | 63 + mcxa276-pac/src/lpi2c0/msr.rs | 692 ++ mcxa276-pac/src/lpi2c0/mtdr.rs | 114 + mcxa276-pac/src/lpi2c0/param.rs | 29 + mcxa276-pac/src/lpi2c0/samr.rs | 49 + mcxa276-pac/src/lpi2c0/sasr.rs | 63 + mcxa276-pac/src/lpi2c0/scfgr0.rs | 125 + mcxa276-pac/src/lpi2c0/scfgr1.rs | 1057 +++ mcxa276-pac/src/lpi2c0/scfgr2.rs | 77 + mcxa276-pac/src/lpi2c0/scr.rs | 399 ++ mcxa276-pac/src/lpi2c0/sder.rs | 336 + mcxa276-pac/src/lpi2c0/sier.rs | 777 +++ mcxa276-pac/src/lpi2c0/srdr.rs | 111 + mcxa276-pac/src/lpi2c0/srdror.rs | 111 + mcxa276-pac/src/lpi2c0/ssr.rs | 684 ++ mcxa276-pac/src/lpi2c0/star.rs | 84 + mcxa276-pac/src/lpi2c0/stdr.rs | 22 + mcxa276-pac/src/lpi2c0/verid.rs | 76 + mcxa276-pac/src/lpspi0.rs | 266 + mcxa276-pac/src/lpspi0/ccr.rs | 77 + mcxa276-pac/src/lpspi0/ccr1.rs | 77 + mcxa276-pac/src/lpspi0/cfgr0.rs | 399 ++ mcxa276-pac/src/lpspi0/cfgr1.rs | 763 +++ mcxa276-pac/src/lpspi0/cr.rs | 282 + mcxa276-pac/src/lpspi0/der.rs | 210 + mcxa276-pac/src/lpspi0/dmr0.rs | 35 + mcxa276-pac/src/lpspi0/dmr1.rs | 35 + mcxa276-pac/src/lpspi0/fcr.rs | 49 + mcxa276-pac/src/lpspi0/fsr.rs | 27 + mcxa276-pac/src/lpspi0/ier.rs | 525 ++ mcxa276-pac/src/lpspi0/param.rs | 36 + mcxa276-pac/src/lpspi0/rdbr.rs | 20 + mcxa276-pac/src/lpspi0/rdr.rs | 20 + mcxa276-pac/src/lpspi0/rdror.rs | 20 + mcxa276-pac/src/lpspi0/rsr.rs | 97 + mcxa276-pac/src/lpspi0/sr.rs | 525 ++ mcxa276-pac/src/lpspi0/tcbr.rs | 22 + mcxa276-pac/src/lpspi0/tcr.rs | 868 +++ mcxa276-pac/src/lpspi0/tdbr.rs | 22 + mcxa276-pac/src/lpspi0/tdr.rs | 22 + mcxa276-pac/src/lpspi0/verid.rs | 68 + mcxa276-pac/src/lptmr0.rs | 50 + mcxa276-pac/src/lptmr0/cmr.rs | 35 + mcxa276-pac/src/lptmr0/cnr.rs | 35 + mcxa276-pac/src/lptmr0/csr.rs | 559 ++ mcxa276-pac/src/lptmr0/psr.rs | 432 ++ mcxa276-pac/src/lpuart0.rs | 149 + mcxa276-pac/src/lpuart0/baud.rs | 1260 ++++ mcxa276-pac/src/lpuart0/ctrl.rs | 1835 +++++ mcxa276-pac/src/lpuart0/data.rs | 431 ++ mcxa276-pac/src/lpuart0/dataro.rs | 22 + mcxa276-pac/src/lpuart0/fifo.rs | 948 +++ mcxa276-pac/src/lpuart0/global.rs | 84 + mcxa276-pac/src/lpuart0/match_.rs | 49 + mcxa276-pac/src/lpuart0/modir.rs | 572 ++ mcxa276-pac/src/lpuart0/param.rs | 29 + mcxa276-pac/src/lpuart0/pincfg.rs | 117 + mcxa276-pac/src/lpuart0/stat.rs | 1196 ++++ mcxa276-pac/src/lpuart0/verid.rs | 76 + mcxa276-pac/src/lpuart0/water.rs | 63 + mcxa276-pac/src/mau0.rs | 119 + mcxa276-pac/src/mau0/gexp_status.rs | 84 + mcxa276-pac/src/mau0/gexp_status_ie.rs | 84 + mcxa276-pac/src/mau0/op_ctrl.rs | 657 ++ mcxa276-pac/src/mau0/res0.rs | 35 + mcxa276-pac/src/mau0/res1.rs | 35 + mcxa276-pac/src/mau0/res2.rs | 35 + mcxa276-pac/src/mau0/res3.rs | 35 + mcxa276-pac/src/mau0/res_status.rs | 2037 ++++++ mcxa276-pac/src/mau0/res_status_ie.rs | 273 + mcxa276-pac/src/mau0/sys_ctlr.rs | 86 + mcxa276-pac/src/mbc0.rs | 350 + mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs | 1709 +++++ mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs | 29 + mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs | 29 + mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs | 29 + mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs | 49 + mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs | 779 +++ mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs | 842 +++ mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs | 842 +++ mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs | 842 +++ mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs | 842 +++ mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs | 842 +++ mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs | 842 +++ mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs | 842 +++ mcxa276-pac/src/mrcc0.rs | 986 +++ mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs | 175 + mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs | 104 + mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs | 119 + mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs | 119 + mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs | 2039 ++++++ mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs | 1848 +++++ mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs | 653 ++ mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs | 2039 ++++++ mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs | 24 + mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs | 24 + mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs | 1911 ++++++ mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs | 651 ++ mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs | 1911 ++++++ mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs | 1659 +++++ mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs | 399 ++ mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs | 22 + mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs | 132 + mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs | 145 + mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs | 93 + mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs | 106 + mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs | 177 + mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs | 106 + mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs | 175 + mcxa276-pac/src/opamp0.rs | 39 + mcxa276-pac/src/opamp0/opamp_ctrl.rs | 276 + mcxa276-pac/src/opamp0/param.rs | 16 + mcxa276-pac/src/opamp0/verid.rs | 34 + mcxa276-pac/src/ostimer0.rs | 84 + mcxa276-pac/src/ostimer0/capture_h.rs | 20 + mcxa276-pac/src/ostimer0/capture_l.rs | 20 + mcxa276-pac/src/ostimer0/evtimerh.rs | 20 + mcxa276-pac/src/ostimer0/evtimerl.rs | 20 + mcxa276-pac/src/ostimer0/match_h.rs | 37 + mcxa276-pac/src/ostimer0/match_l.rs | 37 + mcxa276-pac/src/ostimer0/osevent_ctrl.rs | 171 + mcxa276-pac/src/pkc0.rs | 300 + mcxa276-pac/src/pkc0/pkc_access_err.rs | 69 + mcxa276-pac/src/pkc0/pkc_access_err_clr.rs | 22 + mcxa276-pac/src/pkc0/pkc_cfg.rs | 149 + mcxa276-pac/src/pkc0/pkc_ctrl.rs | 191 + mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs | 22 + mcxa276-pac/src/pkc0/pkc_int_clr_status.rs | 22 + mcxa276-pac/src/pkc0/pkc_int_enable.rs | 20 + mcxa276-pac/src/pkc0/pkc_int_set_enable.rs | 22 + mcxa276-pac/src/pkc0/pkc_int_set_status.rs | 22 + mcxa276-pac/src/pkc0/pkc_int_status.rs | 20 + mcxa276-pac/src/pkc0/pkc_len1.rs | 49 + mcxa276-pac/src/pkc0/pkc_len2.rs | 49 + mcxa276-pac/src/pkc0/pkc_mcdata.rs | 35 + mcxa276-pac/src/pkc0/pkc_mode1.rs | 35 + mcxa276-pac/src/pkc0/pkc_mode2.rs | 35 + mcxa276-pac/src/pkc0/pkc_module_id.rs | 43 + mcxa276-pac/src/pkc0/pkc_soft_rst.rs | 22 + mcxa276-pac/src/pkc0/pkc_status.rs | 48 + mcxa276-pac/src/pkc0/pkc_ulen.rs | 35 + mcxa276-pac/src/pkc0/pkc_uptr.rs | 35 + mcxa276-pac/src/pkc0/pkc_uptrt.rs | 35 + mcxa276-pac/src/pkc0/pkc_version.rs | 124 + mcxa276-pac/src/pkc0/pkc_xyptr1.rs | 49 + mcxa276-pac/src/pkc0/pkc_xyptr2.rs | 49 + mcxa276-pac/src/pkc0/pkc_zrptr1.rs | 49 + mcxa276-pac/src/pkc0/pkc_zrptr2.rs | 49 + mcxa276-pac/src/port0.rs | 428 ++ mcxa276-pac/src/port0/calib0.rs | 49 + mcxa276-pac/src/port0/calib1.rs | 49 + mcxa276-pac/src/port0/config.rs | 84 + mcxa276-pac/src/port0/gpchr.rs | 1043 +++ mcxa276-pac/src/port0/gpclr.rs | 1043 +++ mcxa276-pac/src/port0/pcr0.rs | 675 ++ mcxa276-pac/src/port0/pcr1.rs | 675 ++ mcxa276-pac/src/port0/pcr10.rs | 525 ++ mcxa276-pac/src/port0/pcr11.rs | 525 ++ mcxa276-pac/src/port0/pcr12.rs | 751 ++ mcxa276-pac/src/port0/pcr13.rs | 751 ++ mcxa276-pac/src/port0/pcr14.rs | 751 ++ mcxa276-pac/src/port0/pcr15.rs | 751 ++ mcxa276-pac/src/port0/pcr16.rs | 940 +++ mcxa276-pac/src/port0/pcr17.rs | 877 +++ mcxa276-pac/src/port0/pcr18.rs | 751 ++ mcxa276-pac/src/port0/pcr19.rs | 751 ++ mcxa276-pac/src/port0/pcr2.rs | 753 ++ mcxa276-pac/src/port0/pcr20.rs | 751 ++ mcxa276-pac/src/port0/pcr21.rs | 751 ++ mcxa276-pac/src/port0/pcr22.rs | 751 ++ mcxa276-pac/src/port0/pcr23.rs | 751 ++ mcxa276-pac/src/port0/pcr24.rs | 751 ++ mcxa276-pac/src/port0/pcr25.rs | 751 ++ mcxa276-pac/src/port0/pcr26.rs | 751 ++ mcxa276-pac/src/port0/pcr27.rs | 751 ++ mcxa276-pac/src/port0/pcr28.rs | 525 ++ mcxa276-pac/src/port0/pcr29.rs | 525 ++ mcxa276-pac/src/port0/pcr3.rs | 753 ++ mcxa276-pac/src/port0/pcr30.rs | 525 ++ mcxa276-pac/src/port0/pcr31.rs | 525 ++ mcxa276-pac/src/port0/pcr4.rs | 751 ++ mcxa276-pac/src/port0/pcr5.rs | 751 ++ mcxa276-pac/src/port0/pcr6.rs | 753 ++ mcxa276-pac/src/port0/pcr7.rs | 673 ++ mcxa276-pac/src/port0/pcr8.rs | 525 ++ mcxa276-pac/src/port0/pcr9.rs | 525 ++ mcxa276-pac/src/port0/verid.rs | 68 + mcxa276-pac/src/port1.rs | 428 ++ mcxa276-pac/src/port1/calib0.rs | 49 + mcxa276-pac/src/port1/calib1.rs | 49 + mcxa276-pac/src/port1/config.rs | 84 + mcxa276-pac/src/port1/gpchr.rs | 1043 +++ mcxa276-pac/src/port1/gpclr.rs | 1043 +++ mcxa276-pac/src/port1/pcr0.rs | 814 +++ mcxa276-pac/src/port1/pcr1.rs | 814 +++ mcxa276-pac/src/port1/pcr10.rs | 751 ++ mcxa276-pac/src/port1/pcr11.rs | 751 ++ mcxa276-pac/src/port1/pcr12.rs | 751 ++ mcxa276-pac/src/port1/pcr13.rs | 751 ++ mcxa276-pac/src/port1/pcr14.rs | 751 ++ mcxa276-pac/src/port1/pcr15.rs | 751 ++ mcxa276-pac/src/port1/pcr16.rs | 751 ++ mcxa276-pac/src/port1/pcr17.rs | 751 ++ mcxa276-pac/src/port1/pcr18.rs | 751 ++ mcxa276-pac/src/port1/pcr19.rs | 751 ++ mcxa276-pac/src/port1/pcr2.rs | 751 ++ mcxa276-pac/src/port1/pcr20.rs | 525 ++ mcxa276-pac/src/port1/pcr21.rs | 525 ++ mcxa276-pac/src/port1/pcr22.rs | 525 ++ mcxa276-pac/src/port1/pcr23.rs | 525 ++ mcxa276-pac/src/port1/pcr24.rs | 525 ++ mcxa276-pac/src/port1/pcr25.rs | 525 ++ mcxa276-pac/src/port1/pcr26.rs | 525 ++ mcxa276-pac/src/port1/pcr27.rs | 525 ++ mcxa276-pac/src/port1/pcr28.rs | 525 ++ mcxa276-pac/src/port1/pcr29.rs | 749 ++ mcxa276-pac/src/port1/pcr3.rs | 751 ++ mcxa276-pac/src/port1/pcr30.rs | 940 +++ mcxa276-pac/src/port1/pcr31.rs | 877 +++ mcxa276-pac/src/port1/pcr4.rs | 751 ++ mcxa276-pac/src/port1/pcr5.rs | 751 ++ mcxa276-pac/src/port1/pcr6.rs | 751 ++ mcxa276-pac/src/port1/pcr7.rs | 751 ++ mcxa276-pac/src/port1/pcr8.rs | 940 +++ mcxa276-pac/src/port1/pcr9.rs | 877 +++ mcxa276-pac/src/port1/verid.rs | 68 + mcxa276-pac/src/port2.rs | 405 ++ mcxa276-pac/src/port2/config.rs | 84 + mcxa276-pac/src/port2/gpchr.rs | 1043 +++ mcxa276-pac/src/port2/gpclr.rs | 1043 +++ mcxa276-pac/src/port2/pcr0.rs | 751 ++ mcxa276-pac/src/port2/pcr1.rs | 751 ++ mcxa276-pac/src/port2/pcr10.rs | 673 ++ mcxa276-pac/src/port2/pcr11.rs | 673 ++ mcxa276-pac/src/port2/pcr12.rs | 751 ++ mcxa276-pac/src/port2/pcr13.rs | 751 ++ mcxa276-pac/src/port2/pcr14.rs | 673 ++ mcxa276-pac/src/port2/pcr15.rs | 751 ++ mcxa276-pac/src/port2/pcr16.rs | 751 ++ mcxa276-pac/src/port2/pcr17.rs | 673 ++ mcxa276-pac/src/port2/pcr18.rs | 673 ++ mcxa276-pac/src/port2/pcr19.rs | 673 ++ mcxa276-pac/src/port2/pcr2.rs | 673 ++ mcxa276-pac/src/port2/pcr20.rs | 673 ++ mcxa276-pac/src/port2/pcr21.rs | 673 ++ mcxa276-pac/src/port2/pcr22.rs | 673 ++ mcxa276-pac/src/port2/pcr23.rs | 673 ++ mcxa276-pac/src/port2/pcr24.rs | 673 ++ mcxa276-pac/src/port2/pcr25.rs | 673 ++ mcxa276-pac/src/port2/pcr26.rs | 673 ++ mcxa276-pac/src/port2/pcr27.rs | 525 ++ mcxa276-pac/src/port2/pcr28.rs | 525 ++ mcxa276-pac/src/port2/pcr29.rs | 525 ++ mcxa276-pac/src/port2/pcr3.rs | 751 ++ mcxa276-pac/src/port2/pcr30.rs | 525 ++ mcxa276-pac/src/port2/pcr31.rs | 525 ++ mcxa276-pac/src/port2/pcr4.rs | 673 ++ mcxa276-pac/src/port2/pcr5.rs | 673 ++ mcxa276-pac/src/port2/pcr6.rs | 673 ++ mcxa276-pac/src/port2/pcr7.rs | 751 ++ mcxa276-pac/src/port2/pcr8.rs | 673 ++ mcxa276-pac/src/port2/pcr9.rs | 673 ++ mcxa276-pac/src/port2/verid.rs | 68 + mcxa276-pac/src/port3.rs | 428 ++ mcxa276-pac/src/port3/calib0.rs | 49 + mcxa276-pac/src/port3/calib1.rs | 49 + mcxa276-pac/src/port3/config.rs | 84 + mcxa276-pac/src/port3/gpchr.rs | 1043 +++ mcxa276-pac/src/port3/gpclr.rs | 1043 +++ mcxa276-pac/src/port3/pcr0.rs | 877 +++ mcxa276-pac/src/port3/pcr1.rs | 877 +++ mcxa276-pac/src/port3/pcr10.rs | 751 ++ mcxa276-pac/src/port3/pcr11.rs | 751 ++ mcxa276-pac/src/port3/pcr12.rs | 751 ++ mcxa276-pac/src/port3/pcr13.rs | 751 ++ mcxa276-pac/src/port3/pcr14.rs | 751 ++ mcxa276-pac/src/port3/pcr15.rs | 751 ++ mcxa276-pac/src/port3/pcr16.rs | 751 ++ mcxa276-pac/src/port3/pcr17.rs | 751 ++ mcxa276-pac/src/port3/pcr18.rs | 814 +++ mcxa276-pac/src/port3/pcr19.rs | 814 +++ mcxa276-pac/src/port3/pcr2.rs | 751 ++ mcxa276-pac/src/port3/pcr20.rs | 751 ++ mcxa276-pac/src/port3/pcr21.rs | 751 ++ mcxa276-pac/src/port3/pcr22.rs | 751 ++ mcxa276-pac/src/port3/pcr23.rs | 751 ++ mcxa276-pac/src/port3/pcr24.rs | 751 ++ mcxa276-pac/src/port3/pcr25.rs | 814 +++ mcxa276-pac/src/port3/pcr26.rs | 814 +++ mcxa276-pac/src/port3/pcr27.rs | 814 +++ mcxa276-pac/src/port3/pcr28.rs | 814 +++ mcxa276-pac/src/port3/pcr29.rs | 816 +++ mcxa276-pac/src/port3/pcr3.rs | 751 ++ mcxa276-pac/src/port3/pcr30.rs | 751 ++ mcxa276-pac/src/port3/pcr31.rs | 814 +++ mcxa276-pac/src/port3/pcr4.rs | 751 ++ mcxa276-pac/src/port3/pcr5.rs | 751 ++ mcxa276-pac/src/port3/pcr6.rs | 751 ++ mcxa276-pac/src/port3/pcr7.rs | 751 ++ mcxa276-pac/src/port3/pcr8.rs | 751 ++ mcxa276-pac/src/port3/pcr9.rs | 751 ++ mcxa276-pac/src/port3/verid.rs | 68 + mcxa276-pac/src/port4.rs | 428 ++ mcxa276-pac/src/port4/calib0.rs | 49 + mcxa276-pac/src/port4/calib1.rs | 49 + mcxa276-pac/src/port4/config.rs | 84 + mcxa276-pac/src/port4/gpchr.rs | 1043 +++ mcxa276-pac/src/port4/gpclr.rs | 1043 +++ mcxa276-pac/src/port4/pcr0.rs | 673 ++ mcxa276-pac/src/port4/pcr1.rs | 673 ++ mcxa276-pac/src/port4/pcr10.rs | 525 ++ mcxa276-pac/src/port4/pcr11.rs | 525 ++ mcxa276-pac/src/port4/pcr12.rs | 525 ++ mcxa276-pac/src/port4/pcr13.rs | 525 ++ mcxa276-pac/src/port4/pcr14.rs | 525 ++ mcxa276-pac/src/port4/pcr15.rs | 525 ++ mcxa276-pac/src/port4/pcr16.rs | 525 ++ mcxa276-pac/src/port4/pcr17.rs | 525 ++ mcxa276-pac/src/port4/pcr18.rs | 525 ++ mcxa276-pac/src/port4/pcr19.rs | 525 ++ mcxa276-pac/src/port4/pcr2.rs | 673 ++ mcxa276-pac/src/port4/pcr20.rs | 525 ++ mcxa276-pac/src/port4/pcr21.rs | 525 ++ mcxa276-pac/src/port4/pcr22.rs | 525 ++ mcxa276-pac/src/port4/pcr23.rs | 525 ++ mcxa276-pac/src/port4/pcr24.rs | 525 ++ mcxa276-pac/src/port4/pcr25.rs | 525 ++ mcxa276-pac/src/port4/pcr26.rs | 525 ++ mcxa276-pac/src/port4/pcr27.rs | 525 ++ mcxa276-pac/src/port4/pcr28.rs | 525 ++ mcxa276-pac/src/port4/pcr29.rs | 525 ++ mcxa276-pac/src/port4/pcr3.rs | 673 ++ mcxa276-pac/src/port4/pcr30.rs | 525 ++ mcxa276-pac/src/port4/pcr31.rs | 525 ++ mcxa276-pac/src/port4/pcr4.rs | 673 ++ mcxa276-pac/src/port4/pcr5.rs | 673 ++ mcxa276-pac/src/port4/pcr6.rs | 673 ++ mcxa276-pac/src/port4/pcr7.rs | 673 ++ mcxa276-pac/src/port4/pcr8.rs | 525 ++ mcxa276-pac/src/port4/pcr9.rs | 525 ++ mcxa276-pac/src/port4/verid.rs | 68 + mcxa276-pac/src/rtc0.rs | 94 + mcxa276-pac/src/rtc0/cr.rs | 212 + mcxa276-pac/src/rtc0/ier.rs | 423 ++ mcxa276-pac/src/rtc0/lr.rs | 275 + mcxa276-pac/src/rtc0/sr.rs | 209 + mcxa276-pac/src/rtc0/tar.rs | 35 + mcxa276-pac/src/rtc0/tcr.rs | 184 + mcxa276-pac/src/rtc0/tpr.rs | 35 + mcxa276-pac/src/rtc0/tsr.rs | 35 + mcxa276-pac/src/sau.rs | 84 + mcxa276-pac/src/sau/ctrl.rs | 147 + mcxa276-pac/src/sau/rbar.rs | 35 + mcxa276-pac/src/sau/rlar.rs | 161 + mcxa276-pac/src/sau/rnr.rs | 35 + mcxa276-pac/src/sau/sfar.rs | 35 + mcxa276-pac/src/sau/sfsr.rs | 525 ++ mcxa276-pac/src/sau/type_.rs | 35 + mcxa276-pac/src/scg0.rs | 305 + mcxa276-pac/src/scg0/csr.rs | 86 + mcxa276-pac/src/scg0/firccfg.rs | 119 + mcxa276-pac/src/scg0/firccsr.rs | 651 ++ mcxa276-pac/src/scg0/firctrim.rs | 77 + mcxa276-pac/src/scg0/ldocsr.rs | 338 + mcxa276-pac/src/scg0/param.rs | 220 + mcxa276-pac/src/scg0/rccr.rs | 132 + mcxa276-pac/src/scg0/rosccsr.rs | 230 + mcxa276-pac/src/scg0/sirccsr.rs | 651 ++ mcxa276-pac/src/scg0/sircstat.rs | 49 + mcxa276-pac/src/scg0/sirctcfg.rs | 92 + mcxa276-pac/src/scg0/sirctrim.rs | 77 + mcxa276-pac/src/scg0/sosccfg.rs | 180 + mcxa276-pac/src/scg0/sosccsr.rs | 608 ++ mcxa276-pac/src/scg0/spllcsr.rs | 671 ++ mcxa276-pac/src/scg0/spllctrl.rs | 537 ++ mcxa276-pac/src/scg0/splllock_cnfg.rs | 37 + mcxa276-pac/src/scg0/spllmdiv.rs | 100 + mcxa276-pac/src/scg0/spllndiv.rs | 100 + mcxa276-pac/src/scg0/spllpdiv.rs | 100 + mcxa276-pac/src/scg0/spllsscg0.rs | 35 + mcxa276-pac/src/scg0/spllsscg1.rs | 331 + mcxa276-pac/src/scg0/spllsscgstat.rs | 54 + mcxa276-pac/src/scg0/spllstat.rs | 177 + mcxa276-pac/src/scg0/trim_lock.rs | 161 + mcxa276-pac/src/scg0/verid.rs | 20 + mcxa276-pac/src/scn_scb.rs | 18 + mcxa276-pac/src/scn_scb/cppwr.rs | 1183 ++++ mcxa276-pac/src/sgi0.rs | 863 +++ mcxa276-pac/src/sgi0/sgi_access_err.rs | 77 + mcxa276-pac/src/sgi0/sgi_access_err_clr.rs | 42 + mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs | 63 + mcxa276-pac/src/sgi0/sgi_auto_mode.rs | 199 + mcxa276-pac/src/sgi0/sgi_config.rs | 188 + mcxa276-pac/src/sgi0/sgi_config2.rs | 62 + mcxa276-pac/src/sgi0/sgi_count.rs | 42 + mcxa276-pac/src/sgi0/sgi_ctrl.rs | 231 + mcxa276-pac/src/sgi0/sgi_ctrl2.rs | 231 + mcxa276-pac/src/sgi0/sgi_datin0a.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin0b.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin0c.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin0d.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin1a.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin1b.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin1c.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin1d.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin2a.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin2b.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin2c.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin2d.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin3a.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin3b.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin3c.rs | 35 + mcxa276-pac/src/sgi0/sgi_datin3d.rs | 35 + mcxa276-pac/src/sgi0/sgi_datouta.rs | 35 + mcxa276-pac/src/sgi0/sgi_datoutb.rs | 35 + mcxa276-pac/src/sgi0/sgi_datoutc.rs | 35 + mcxa276-pac/src/sgi0/sgi_datoutd.rs | 35 + mcxa276-pac/src/sgi0/sgi_dummy_ctrl.rs | 63 + mcxa276-pac/src/sgi0/sgi_int_enable.rs | 42 + mcxa276-pac/src/sgi0/sgi_int_status.rs | 27 + mcxa276-pac/src/sgi0/sgi_int_status_clr.rs | 42 + mcxa276-pac/src/sgi0/sgi_int_status_set.rs | 42 + mcxa276-pac/src/sgi0/sgi_key0a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key0b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key0c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key0d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key1a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key1b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key1c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key1d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key2a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key2b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key2c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key2d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key3a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key3b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key3c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key3d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key4a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key4b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key4c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key4d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key5a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key5b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key5c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key5d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key6a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key6b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key6c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key6d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key7a.rs | 35 + mcxa276-pac/src/sgi0/sgi_key7b.rs | 35 + mcxa276-pac/src/sgi0/sgi_key7c.rs | 35 + mcxa276-pac/src/sgi0/sgi_key7d.rs | 35 + mcxa276-pac/src/sgi0/sgi_key_ctrl.rs | 35 + mcxa276-pac/src/sgi0/sgi_key_wrap.rs | 20 + mcxa276-pac/src/sgi0/sgi_keychk.rs | 35 + mcxa276-pac/src/sgi0/sgi_module_id.rs | 20 + mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs | 35 + mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs | 35 + mcxa276-pac/src/sgi0/sgi_sfrseed.rs | 35 + mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs | 149 + mcxa276-pac/src/sgi0/sgi_sha_fifo.rs | 35 + mcxa276-pac/src/sgi0/sgi_status.rs | 203 + mcxa276-pac/src/sgi0/sgi_version.rs | 55 + mcxa276-pac/src/slcd0.rs | 111 + mcxa276-pac/src/slcd0/lcd_ar.rs | 351 + mcxa276-pac/src/slcd0/lcd_bpen0.rs | 2037 ++++++ mcxa276-pac/src/slcd0/lcd_bpen1.rs | 1029 +++ mcxa276-pac/src/slcd0/lcd_fdcr.rs | 457 ++ mcxa276-pac/src/slcd0/lcd_fdsr.rs | 92 + mcxa276-pac/src/slcd0/lcd_gcr.rs | 616 ++ mcxa276-pac/src/slcd0/lcd_pen0.rs | 2037 ++++++ mcxa276-pac/src/slcd0/lcd_pen1.rs | 1029 +++ mcxa276-pac/src/slcd0/lcd_wfto.rs | 77 + mcxa276-pac/src/smartdma0.rs | 128 + mcxa276-pac/src/smartdma0/arm2ezh.rs | 49 + mcxa276-pac/src/smartdma0/bootadr.rs | 35 + mcxa276-pac/src/smartdma0/break_addr.rs | 35 + mcxa276-pac/src/smartdma0/break_vect.rs | 35 + mcxa276-pac/src/smartdma0/ctrl.rs | 105 + mcxa276-pac/src/smartdma0/emer_sel.rs | 49 + mcxa276-pac/src/smartdma0/emer_vect.rs | 35 + mcxa276-pac/src/smartdma0/ezh2arm.rs | 35 + mcxa276-pac/src/smartdma0/pc.rs | 20 + mcxa276-pac/src/smartdma0/pendtrap.rs | 63 + mcxa276-pac/src/smartdma0/sp.rs | 20 + mcxa276-pac/src/spc0.rs | 214 + mcxa276-pac/src/spc0/active_cfg.rs | 504 ++ mcxa276-pac/src/spc0/active_cfg1.rs | 37 + mcxa276-pac/src/spc0/active_vdelay.rs | 37 + mcxa276-pac/src/spc0/coreldo_cfg.rs | 16 + mcxa276-pac/src/spc0/evd_cfg.rs | 56 + mcxa276-pac/src/spc0/lp_cfg.rs | 567 ++ mcxa276-pac/src/spc0/lp_cfg1.rs | 37 + mcxa276-pac/src/spc0/lpreq_cfg.rs | 230 + mcxa276-pac/src/spc0/lpwkup_delay.rs | 35 + mcxa276-pac/src/spc0/pd_status0.rs | 189 + mcxa276-pac/src/spc0/sc.rs | 203 + mcxa276-pac/src/spc0/sramctl.rs | 197 + mcxa276-pac/src/spc0/sramretldo_cntrl.rs | 100 + mcxa276-pac/src/spc0/sramretldo_reftrim.rs | 37 + mcxa276-pac/src/spc0/vd_core_cfg.rs | 212 + mcxa276-pac/src/spc0/vd_stat.rs | 211 + mcxa276-pac/src/spc0/vd_sys_cfg.rs | 338 + mcxa276-pac/src/spc0/verid.rs | 66 + mcxa276-pac/src/syscon.rs | 497 ++ mcxa276-pac/src/syscon/ahbclkdiv.rs | 76 + mcxa276-pac/src/syscon/ahbmatprio.rs | 695 ++ mcxa276-pac/src/syscon/binary_code_lsb.rs | 20 + mcxa276-pac/src/syscon/binary_code_msb.rs | 20 + mcxa276-pac/src/syscon/busclkdiv.rs | 197 + mcxa276-pac/src/syscon/clkunlock.rs | 84 + mcxa276-pac/src/syscon/cpu0nstckcal.rs | 161 + mcxa276-pac/src/syscon/cpustat.rs | 95 + mcxa276-pac/src/syscon/ctimerglobalstarten.rs | 336 + mcxa276-pac/src/syscon/debug_auth_beacon.rs | 35 + mcxa276-pac/src/syscon/debug_features.rs | 161 + mcxa276-pac/src/syscon/debug_features_dp.rs | 161 + mcxa276-pac/src/syscon/debug_lock_en.rs | 93 + mcxa276-pac/src/syscon/device_id0.rs | 297 + mcxa276-pac/src/syscon/device_type.rs | 157 + mcxa276-pac/src/syscon/dieid.rs | 36 + mcxa276-pac/src/syscon/els_otp_lc_state.rs | 20 + mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs | 20 + mcxa276-pac/src/syscon/els_udf.rs | 231 + mcxa276-pac/src/syscon/els_uid.rs | 35 + mcxa276-pac/src/syscon/frohfdiv.rs | 204 + mcxa276-pac/src/syscon/frolfdiv.rs | 204 + mcxa276-pac/src/syscon/gray_code_lsb.rs | 35 + mcxa276-pac/src/syscon/gray_code_msb.rs | 35 + mcxa276-pac/src/syscon/jtag_id.rs | 22 + mcxa276-pac/src/syscon/lpcac_ctrl.rs | 464 ++ mcxa276-pac/src/syscon/msfcfg.rs | 336 + mcxa276-pac/src/syscon/nmisrc.rs | 98 + mcxa276-pac/src/syscon/nvm_ctrl.rs | 338 + mcxa276-pac/src/syscon/pll1clkdiv.rs | 204 + mcxa276-pac/src/syscon/protlvl.rs | 210 + mcxa276-pac/src/syscon/pwm0subctl.rs | 273 + mcxa276-pac/src/syscon/pwm1subctl.rs | 273 + mcxa276-pac/src/syscon/ram_ctrl.rs | 338 + mcxa276-pac/src/syscon/ram_interleave.rs | 84 + mcxa276-pac/src/syscon/remap.rs | 504 ++ mcxa276-pac/src/syscon/rop_state.rs | 20 + mcxa276-pac/src/syscon/slowclkdiv.rs | 197 + mcxa276-pac/src/syscon/smart_dmaint.rs | 1533 +++++ mcxa276-pac/src/syscon/sram_xen.rs | 462 ++ mcxa276-pac/src/syscon/sram_xen_dp.rs | 105 + mcxa276-pac/src/syscon/swd_access_cpu0.rs | 91 + mcxa276-pac/src/tdet0.rs | 103 + mcxa276-pac/src/tdet0/cr.rs | 350 + mcxa276-pac/src/tdet0/ier.rs | 1155 ++++ mcxa276-pac/src/tdet0/lr.rs | 842 +++ mcxa276-pac/src/tdet0/pgfr.rs | 668 ++ mcxa276-pac/src/tdet0/ppr.rs | 645 ++ mcxa276-pac/src/tdet0/sr.rs | 1219 ++++ mcxa276-pac/src/tdet0/ter.rs | 1092 +++ mcxa276-pac/src/tdet0/tsr.rs | 35 + mcxa276-pac/src/trng0.rs | 492 ++ mcxa276-pac/src/trng0/csclr.rs | 159 + mcxa276-pac/src/trng0/cser.rs | 177 + mcxa276-pac/src/trng0/ent0.rs | 20 + mcxa276-pac/src/trng0/frqcnt_frqcnt.rs | 20 + mcxa276-pac/src/trng0/frqmax_frqmax.rs | 37 + mcxa276-pac/src/trng0/frqmin_frqmin.rs | 37 + mcxa276-pac/src/trng0/int_ctrl.rs | 275 + mcxa276-pac/src/trng0/int_mask.rs | 273 + mcxa276-pac/src/trng0/int_status.rs | 177 + mcxa276-pac/src/trng0/mctl.rs | 515 ++ mcxa276-pac/src/trng0/osc2_ctl.rs | 478 ++ mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs | 20 + mcxa276-pac/src/trng0/pkrcnt10.rs | 27 + mcxa276-pac/src/trng0/pkrcnt32.rs | 27 + mcxa276-pac/src/trng0/pkrcnt54.rs | 27 + mcxa276-pac/src/trng0/pkrcnt76.rs | 27 + mcxa276-pac/src/trng0/pkrcnt98.rs | 27 + mcxa276-pac/src/trng0/pkrcntba.rs | 27 + mcxa276-pac/src/trng0/pkrcntdc.rs | 27 + mcxa276-pac/src/trng0/pkrcntfe.rs | 27 + mcxa276-pac/src/trng0/pkrmax_pkrmax.rs | 37 + mcxa276-pac/src/trng0/pkrrng.rs | 37 + mcxa276-pac/src/trng0/pkrsq_pkrsq.rs | 20 + mcxa276-pac/src/trng0/sblim_sblim.rs | 37 + mcxa276-pac/src/trng0/scmc_scmc.rs | 20 + mcxa276-pac/src/trng0/scmisc.rs | 51 + mcxa276-pac/src/trng0/scml_scml.rs | 51 + mcxa276-pac/src/trng0/scr1c_scr1c.rs | 27 + mcxa276-pac/src/trng0/scr1l_scr1l.rs | 51 + mcxa276-pac/src/trng0/scr2c_scr2c.rs | 27 + mcxa276-pac/src/trng0/scr2l_scr2l.rs | 51 + mcxa276-pac/src/trng0/scr3c_scr3c.rs | 27 + mcxa276-pac/src/trng0/scr3l_scr3l.rs | 51 + mcxa276-pac/src/trng0/scr4c_scr4c.rs | 27 + mcxa276-pac/src/trng0/scr4l_scr4l.rs | 51 + mcxa276-pac/src/trng0/scr5c_scr5c.rs | 27 + mcxa276-pac/src/trng0/scr5l_scr5l.rs | 51 + mcxa276-pac/src/trng0/scr6pc_scr6pc.rs | 27 + mcxa276-pac/src/trng0/scr6pl_scr6pl.rs | 51 + mcxa276-pac/src/trng0/sdctl.rs | 51 + mcxa276-pac/src/trng0/sec_cfg.rs | 84 + mcxa276-pac/src/trng0/status.rs | 676 ++ mcxa276-pac/src/trng0/totsam_totsam.rs | 20 + mcxa276-pac/src/trng0/vid1.rs | 132 + mcxa276-pac/src/trng0/vid2.rs | 171 + mcxa276-pac/src/udf0.rs | 50 + mcxa276-pac/src/udf0/udf_ctrl.rs | 128 + mcxa276-pac/src/udf0/udf_rd_data.rs | 20 + mcxa276-pac/src/udf0/udf_status.rs | 100 + mcxa276-pac/src/udf0/udf_wr_data.rs | 22 + mcxa276-pac/src/usb0.rs | 493 ++ mcxa276-pac/src/usb0/addinfo.rs | 56 + mcxa276-pac/src/usb0/addr.rs | 49 + mcxa276-pac/src/usb0/bdtpage1.rs | 35 + mcxa276-pac/src/usb0/bdtpage2.rs | 35 + mcxa276-pac/src/usb0/bdtpage3.rs | 35 + mcxa276-pac/src/usb0/clk_recover_ctrl.rs | 273 + mcxa276-pac/src/usb0/clk_recover_int_en.rs | 86 + mcxa276-pac/src/usb0/clk_recover_int_status.rs | 85 + mcxa276-pac/src/usb0/clk_recover_irc_en.rs | 86 + mcxa276-pac/src/usb0/control.rs | 176 + mcxa276-pac/src/usb0/ctl.rs | 280 + mcxa276-pac/src/usb0/endpoint.rs | 18 + mcxa276-pac/src/usb0/endpoint/endpt.rs | 266 + mcxa276-pac/src/usb0/erren.rs | 525 ++ mcxa276-pac/src/usb0/errstat.rs | 526 ++ mcxa276-pac/src/usb0/frmnumh.rs | 20 + mcxa276-pac/src/usb0/frmnuml.rs | 20 + mcxa276-pac/src/usb0/idcomp.rs | 22 + mcxa276-pac/src/usb0/inten.rs | 525 ++ mcxa276-pac/src/usb0/istat.rs | 526 ++ mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs | 25 + mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs | 25 + mcxa276-pac/src/usb0/miscctrl.rs | 399 ++ mcxa276-pac/src/usb0/observe.rs | 138 + mcxa276-pac/src/usb0/otgctl.rs | 273 + mcxa276-pac/src/usb0/otgicr.rs | 147 + mcxa276-pac/src/usb0/otgistat.rs | 148 + mcxa276-pac/src/usb0/otgstat.rs | 61 + mcxa276-pac/src/usb0/perid.rs | 22 + mcxa276-pac/src/usb0/rev.rs | 22 + mcxa276-pac/src/usb0/softhld.rs | 35 + mcxa276-pac/src/usb0/stall_ih_dis.rs | 525 ++ mcxa276-pac/src/usb0/stall_il_dis.rs | 525 ++ mcxa276-pac/src/usb0/stall_oh_dis.rs | 525 ++ mcxa276-pac/src/usb0/stall_ol_dis.rs | 525 ++ mcxa276-pac/src/usb0/stat.rs | 102 + mcxa276-pac/src/usb0/token.rs | 118 + mcxa276-pac/src/usb0/usbctrl.rs | 401 ++ mcxa276-pac/src/usb0/usbfrmadjust.rs | 35 + mcxa276-pac/src/usb0/usbtrc0.rs | 298 + mcxa276-pac/src/utick0.rs | 67 + mcxa276-pac/src/utick0/cap.rs | 61 + mcxa276-pac/src/utick0/capclr.rs | 159 + mcxa276-pac/src/utick0/cfg.rs | 525 ++ mcxa276-pac/src/utick0/ctrl.rs | 98 + mcxa276-pac/src/utick0/stat.rs | 126 + mcxa276-pac/src/vbat0.rs | 97 + mcxa276-pac/src/vbat0/froclke.rs | 35 + mcxa276-pac/src/vbat0/froctla.rs | 86 + mcxa276-pac/src/vbat0/frolcka.rs | 84 + mcxa276-pac/src/vbat0/verid.rs | 36 + mcxa276-pac/src/vbat0/wakeup.rs | 18 + mcxa276-pac/src/vbat0/wakeup/wakeupa.rs | 35 + mcxa276-pac/src/vbat0/waklcka.rs | 84 + mcxa276-pac/src/waketimer0.rs | 29 + mcxa276-pac/src/waketimer0/wake_timer_cnt.rs | 35 + mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs | 247 + mcxa276-pac/src/wuu0.rs | 155 + mcxa276-pac/src/wuu0/de.rs | 210 + mcxa276-pac/src/wuu0/fdc.rs | 187 + mcxa276-pac/src/wuu0/filt.rs | 368 + mcxa276-pac/src/wuu0/fmc.rs | 147 + mcxa276-pac/src/wuu0/me.rs | 399 ++ mcxa276-pac/src/wuu0/param.rs | 43 + mcxa276-pac/src/wuu0/pdc1.rs | 1557 +++++ mcxa276-pac/src/wuu0/pdc2.rs | 1557 +++++ mcxa276-pac/src/wuu0/pe1.rs | 1557 +++++ mcxa276-pac/src/wuu0/pe2.rs | 1557 +++++ mcxa276-pac/src/wuu0/pf.rs | 2038 ++++++ mcxa276-pac/src/wuu0/pmc.rs | 2037 ++++++ mcxa276-pac/src/wuu0/verid.rs | 76 + mcxa276-pac/src/wwdt0.rs | 73 + mcxa276-pac/src/wwdt0/feed.rs | 22 + mcxa276-pac/src/wwdt0/mod_.rs | 463 ++ mcxa276-pac/src/wwdt0/tc.rs | 37 + mcxa276-pac/src/wwdt0/tv.rs | 22 + mcxa276-pac/src/wwdt0/warnint.rs | 35 + mcxa276-pac/src/wwdt0/window.rs | 37 + memory.x | 10 + ram.ld | 109 + run.sh | 93 + rust-toolchain.toml | 2 - rustfmt.toml | 8 +- src/adc.rs | 376 + src/baremetal/mod.rs | 6 - src/board.rs | 14 + src/clocks.rs | 136 + src/config.rs | 20 + src/gpio.rs | 246 + src/interrupt.rs | 349 + src/lib.rs | 165 + src/lpuart/buffered.rs | 686 ++ src/lpuart/mod.rs | 1208 ++++ src/main.rs | 18 - src/ostimer.rs | 704 ++ src/pins.rs | 127 + src/reset.rs | 112 + src/rtc.rs | 281 + src/uart.rs | 308 + supply-chain/README.md | 83 - supply-chain/audits.toml | 4 - supply-chain/config.toml | 14 - supply-chain/imports.lock | 8 - tools/run_and_attach_rtt.sh | 24 + tools/run_jlink_noblock.sh | 76 + 2065 files changed, 537297 insertions(+), 1119 deletions(-) create mode 100644 .cargo/config.toml delete mode 100644 .github/workflows/cargo-vet-pr-comment.yml delete mode 100644 .github/workflows/cargo-vet.yml delete mode 100644 .github/workflows/check.yml delete mode 100644 .github/workflows/nostd.yml delete mode 100644 .vscode/settings.json delete mode 100644 CODEOWNERS delete mode 100644 CODE_OF_CONDUCT.md delete mode 100644 CONTRIBUTING.md create mode 100644 Embed.toml delete mode 100644 LICENSE create mode 100644 License.txt delete mode 100644 README.md create mode 100644 README.txt delete mode 100644 SECURITY.md create mode 100644 SW-Content-Register.txt create mode 100644 build.rs create mode 100644 defmt.x delete mode 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100644 mcxa276-pac/src/i3c0/sintset.rs create mode 100644 mcxa276-pac/src/i3c0/smapctrl0.rs create mode 100644 mcxa276-pac/src/i3c0/smaxlimits.rs create mode 100644 mcxa276-pac/src/i3c0/smsgmapaddr.rs create mode 100644 mcxa276-pac/src/i3c0/srdatab.rs create mode 100644 mcxa276-pac/src/i3c0/srdatah.rs create mode 100644 mcxa276-pac/src/i3c0/sstatus.rs create mode 100644 mcxa276-pac/src/i3c0/stcclock.rs create mode 100644 mcxa276-pac/src/i3c0/svendorid.rs create mode 100644 mcxa276-pac/src/i3c0/swdatab.rs create mode 100644 mcxa276-pac/src/i3c0/swdatabe.rs create mode 100644 mcxa276-pac/src/i3c0/swdatah.rs create mode 100644 mcxa276-pac/src/i3c0/swdatahe.rs create mode 100644 mcxa276-pac/src/inputmux0.rs create mode 100644 mcxa276-pac/src/inputmux0/adc0_trig.rs create mode 100644 mcxa276-pac/src/inputmux0/adc1_trig.rs create mode 100644 mcxa276-pac/src/inputmux0/adc2_trig.rs create mode 100644 mcxa276-pac/src/inputmux0/adc3_trig.rs create mode 100644 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tools/run_and_attach_rtt.sh create mode 100644 tools/run_jlink_noblock.sh diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 000000000..3286be01c --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,19 @@ +[build] +target = "thumbv8m.main-none-eabihf" + +[target.thumbv8m.main-none-eabihf] +runner = "./run.sh" +# Use our custom ram.ld for RAM-execution +rustflags = ["-C", "link-arg=-Tdefmt.x", "-C", "link-arg=-Tram.ld"] + +[alias] +# Build examples with defmt+RTT and LPUART2 enabled +build-defmt = ["build", "--features", "defmt defmt-rtt lpuart2", "--examples"] +# Blocking run (uses run.sh). Good for one-terminal flash+run. +run-defmt = ["run", "--features", "defmt defmt-rtt lpuart2", "--example", "hello"] +# Non-blocking flash to RAM via J-Link; frees probe for RTT attach +flash-nb = ["!./tools/run_jlink_noblock.sh", "target/thumbv8m.main-none-eabihf/debug/examples/hello", "1366:0101:000600110607", "MCXA276", "500"] +# Attach-only viewer that decodes defmt over RTT using J-Link +# Requires PROBE_RS_PROBE exported (or it will prompt) +defmt-attach = ["embed", "--features", "defmt defmt-rtt lpuart2", "--example", "hello"] + diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml deleted file mode 100644 index dd8ef37a6..000000000 --- a/.github/workflows/cargo-vet-pr-comment.yml +++ /dev/null @@ -1,137 +0,0 @@ -# This workflow triggers after cargo-vet workflow has run. -# It adds a comment to the PR with the results of the cargo vet run. -# It first adds a comment if the cargo vet run fails, -# and updates the comment if the cargo vet run succeeds after having failed at least once. - -name: Cargo vet PR comment - -on: - workflow_run: - workflows: [cargo-vet] - types: - - completed - -permissions: - contents: read - pull-requests: write - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -jobs: - - find-pr-comment: - # This job runs when the cargo-vet job fails or succeeds - # It will download the artifact from the failed job and post a comment on the PR - runs-on: ubuntu-latest - outputs: - comment-id: ${{ steps.get-comment-id.outputs.comment-id }} - pr-number: ${{ steps.get-pr-number.outputs.pr_number }} - if: github.event.workflow_run.event == 'pull_request' - steps: - - name: 'Download artifact' - uses: actions/download-artifact@v4 - with: - github-token: ${{ secrets.GITHUB_TOKEN }} - name: pr - path: pr/ - run-id: ${{ github.event.workflow_run.id }} - - - name: 'Get PR number' - id: get-pr-number - run: echo "pr_number=$(cat ./pr/NR)" >> $GITHUB_OUTPUT - - - name: 'Find existing comment' - id: find-comment - uses: peter-evans/find-comment@v3 - with: - issue-number: ${{ steps.get-pr-number.outputs.pr_number }} - comment-author: 'github-actions[bot]' - body-includes: 'comment-tag: [cargo-vet]' - - - name: 'Get comment ID' - id: get-comment-id - if: ${{ steps.find-comment.outputs.comment-id != '' }} - run: echo "comment-id=${{ steps.find-comment.outputs.comment-id }}" >> $GITHUB_OUTPUT - - post-comment-failure: - # This job runs when the cargo-vet job fails - # It will download the artifact from the failed job and post a comment on the PR - runs-on: ubuntu-latest - needs: find-pr-comment - if: github.event.workflow_run.conclusion == 'failure' - steps: - - name: 'Comment on PR - Failure' - uses: peter-evans/create-or-update-comment@v4 - with: - comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} - issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} - body: | - # Cargo Vet Audit Failed - - `cargo vet` has failed in this PR. Please run `cargo vet --locked` locally to check for new or updated unvetted dependencies. - Details about the vetting process can be found in [supply-chain/README.md](../blob/main/supply-chain/README.md) - - ## If the unvetted dependencies are not needed - Please modify Cargo.toml file to avoid including the dependencies. - - ## If the unvetted dependencies are needed - Post a new comment with the questionnaire below to the PR to help the auditors vet the dependencies. - After the auditors have vetted the dependencies, the PR will need to be rebased to pick up the new audits and pass this check. - - ### Copy and paste the questionnaire as a new comment and provide your answers: - - **1. What crates (with version) need to be audited?** - - **2. How many of the crates are version updates vs new dependencies?** - - **3. To confirm none of the already included crates serve your needs, please provide a brief description of the purpose of the new crates.** - - **4. Any extra notes to the auditors to help with their audits.** - - - edit-mode: replace - - - name: 'Label PR' - uses: actions/github-script@v7 - with: - script: | - github.rest.issues.addLabels({ - issue_number: ${{ needs.find-pr-comment.outputs.pr-number }}, - owner: context.repo.owner, - repo: context.repo.repo, - labels: ['cargo vet'] - }) - - post-comment-success: - # This job runs when the cargo-vet job succeeds - # It will update the comment on the PR with a success message - runs-on: ubuntu-latest - needs: find-pr-comment - if: github.event.workflow_run.conclusion == 'success' - steps: - - name: 'Comment on PR - Success' - # Only update the comment if it exists - # This is to avoid creating a new comment if the cargo-vet job has never failed before - if: ${{ needs.find-pr-comment.outputs.comment-id }} - uses: peter-evans/create-or-update-comment@v4 - with: - comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} - issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} - body: | - # Cargo Vet Audit Passed - `cargo vet` has passed in this PR. No new unvetted dependencies were found. - - - edit-mode: replace \ No newline at end of file diff --git a/.github/workflows/cargo-vet.yml b/.github/workflows/cargo-vet.yml deleted file mode 100644 index 864c138e9..000000000 --- a/.github/workflows/cargo-vet.yml +++ /dev/null @@ -1,53 +0,0 @@ -# This workflow runs whenever a PR is opened or updated. It runs cargo vet to check for unvetted dependencies in the Cargo.lock file. -permissions: - contents: read -on: - pull_request: - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -name: cargo-vet -jobs: - vet: - # cargo-vet checks for unvetted dependencies in the Cargo.lock file - # This is to ensure that new dependencies are vetted before they are added to the project - name: vet-dependencies - runs-on: ubuntu-latest - env: - CARGO_VET_VERSION: 0.10.1 - - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - - uses: actions/cache@v4 - with: - path: ${{ runner.tool_cache }}/cargo-vet - key: cargo-vet-bin-${{ env.CARGO_VET_VERSION }} - - - name: Add the tool cache directory to the search path - run: echo "${{ runner.tool_cache }}/cargo-vet/bin" >> $GITHUB_PATH - - - name: Ensure that the tool cache is populated with the cargo-vet binary - run: cargo install --root ${{ runner.tool_cache }}/cargo-vet --version ${{ env.CARGO_VET_VERSION }} cargo-vet - - - name: Invoke cargo-vet - run: cargo vet --locked - - - name: Save PR number - # PR number is saved as an artifact so it can be used to determine the PR to comment on by the vet-pr-comment workflow - # vet-pr-comment workflow is triggered by the workflow_run event so it runs in the context of the base branch and not the PR branch - if: ${{ failure() }} || ${{ success() }} - run: | - mkdir -p ./pr - echo ${{ github.event.number }} > ./pr/NR - - uses: actions/upload-artifact@v4 - # Need to upload the artifact in both success and failure cases so comment can be updated in either case - if: ${{ failure() }} || ${{ success() }} - with: - name: pr - path: pr/ - overwrite: true \ No newline at end of file diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml deleted file mode 100644 index 9bf402d61..000000000 --- a/.github/workflows/check.yml +++ /dev/null @@ -1,169 +0,0 @@ -# This workflow runs whenever a PR is opened or updated, or a commit is pushed to main. It runs -# several checks: -# - commit_list: produces a list of commits to be checked -# - fmt: checks that the code is formatted according to rustfmt -# - clippy: checks that the code does not contain any clippy warnings -# - doc: checks that the code can be documented without errors -# - hack: check combinations of feature flags -# - msrv: check that the msrv specified in the crate is correct -permissions: - contents: read -# This configuration allows maintainers of this repo to create a branch and pull request based on -# the new branch. Restricting the push trigger to the main branch ensures that the PR only gets -# built once. -on: - push: - branches: [main] - pull_request: -# If new code is pushed to a PR branch, then cancel in progress workflows for that PR. Ensures that -# we don't waste CI time, and returns results quicker https://github.com/jonhoo/rust-ci-conf/pull/5 -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true -name: check -jobs: - fmt: - runs-on: ubuntu-latest - name: stable / fmt - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - components: rustfmt - - name: cargo fmt --check - run: cargo fmt --check - - clippy: - runs-on: ubuntu-latest - name: ${{ matrix.toolchain }} / clippy - permissions: - contents: read - checks: write - strategy: - fail-fast: false - matrix: - # Get early warning of new lints which are regularly introduced in beta channels. - toolchain: [stable, beta] - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install ${{ matrix.toolchain }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.toolchain }} - components: clippy - - name: cargo clippy - uses: giraffate/clippy-action@v1 - with: - reporter: 'github-pr-check' - github_token: ${{ secrets.GITHUB_TOKEN }} - - # Enable once we have a released crate - # semver: - # runs-on: ubuntu-latest - # name: semver - # strategy: - # fail-fast: false - # steps: - # - uses: actions/checkout@v4 - # with: - # submodules: true - # - name: Install stable - # uses: dtolnay/rust-toolchain@stable - # with: - # components: rustfmt - # - name: cargo-semver-checks - # uses: obi1kenobi/cargo-semver-checks-action@v2 - - doc: - # run docs generation on nightly rather than stable. This enables features like - # https://doc.rust-lang.org/beta/unstable-book/language-features/doc-cfg.html which allows an - # API be documented as only available in some specific platforms. - runs-on: ubuntu-latest - name: nightly / doc - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install nightly - uses: dtolnay/rust-toolchain@nightly - - name: cargo doc - run: cargo doc --no-deps --all-features - env: - RUSTDOCFLAGS: --cfg docsrs - - hack: - # cargo-hack checks combinations of feature flags to ensure that features are all additive - # which is required for feature unification - runs-on: ubuntu-latest - name: ubuntu / stable / features - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install stable - uses: dtolnay/rust-toolchain@stable - - name: cargo install cargo-hack - uses: taiki-e/install-action@cargo-hack - # intentionally no target specifier; see https://github.com/jonhoo/rust-ci-conf/pull/4 - # --feature-powerset runs for every combination of features - - name: cargo hack - run: cargo hack --feature-powerset check - - deny: - # cargo-deny checks licenses, advisories, sources, and bans for - # our dependencies. - runs-on: ubuntu-latest - name: ubuntu / stable / deny - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install stable - uses: dtolnay/rust-toolchain@stable - - name: cargo install cargo-deny - uses: EmbarkStudios/cargo-deny-action@v2 - with: - log-level: warn - manifest-path: ./Cargo.toml - command: check - arguments: --all-features - - test: - runs-on: ubuntu-latest - name: ubuntu / stable / test - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install stable - uses: dtolnay/rust-toolchain@stable - - name: cargo install cargo-hack - uses: taiki-e/install-action@cargo-hack - - name: cargo test - run: cargo hack --feature-powerset test - - msrv: - # check that we can build using the minimal rust version that is specified by this crate - runs-on: ubuntu-latest - # we use a matrix here just because env can't be used in job names - # https://docs.github.com/en/actions/learn-github-actions/contexts#context-availability - strategy: - fail-fast: false - matrix: - msrv: ["1.85"] - name: ubuntu / ${{ matrix.msrv }} - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install ${{ matrix.msrv }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.msrv }} - - name: cargo +${{ matrix.msrv }} check - run: cargo check diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml deleted file mode 100644 index 532235851..000000000 --- a/.github/workflows/nostd.yml +++ /dev/null @@ -1,30 +0,0 @@ -# This workflow checks whether the library is able to run without the std library (e.g., embedded). -# This entire file should be removed if this crate does not support no-std. See check.yml for -# information about how the concurrency cancellation and workflow triggering works -permissions: - contents: read -on: - push: - branches: [main] - pull_request: -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true -name: no-std -jobs: - nostd: - runs-on: ubuntu-latest - name: ${{ matrix.target }} - strategy: - matrix: - target: [thumbv8m.main-none-eabihf] - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - name: Install stable - uses: dtolnay/rust-toolchain@stable - - name: rustup target add ${{ matrix.target }} - run: rustup target add ${{ matrix.target }} - - name: cargo check - run: cargo check --target ${{ matrix.target }} diff --git a/.gitignore b/.gitignore index 6985cf1bd..a23881a76 100644 --- a/.gitignore +++ b/.gitignore @@ -1,14 +1,20 @@ -# Generated by Cargo -# will have compiled files and executables -debug/ -target/ - -# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries -# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +# Rust +/target/ Cargo.lock -# These are backup files generated by rustfmt -**/*.rs.bk +# IDE +.vscode/ +.idea/ + +# OS +.DS_Store +Thumbs.db + +# Embedded +*.bin +*.hex +*.elf +*.map -# MSVC Windows builds of rustc generate these, which store debugging information -*.pdb +# Debug +*.log diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index ace00d468..000000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "editor.formatOnSave": true, - "rust-analyzer.checkOnSave": true, - "rust-analyzer.check.allTargets": false, - "rust-analyzer.cargo.target": "thumbv8m.main-none-eabihf", - "rust-analyzer.cargo.features": "all", - "rust-analyzer.check.command": "clippy", - "[toml]": { - "editor.defaultFormatter": "tamasfe.even-better-toml" - }, - "[rust]": { - "editor.defaultFormatter": "rust-lang.rust-analyzer" - } -} diff --git a/CODEOWNERS b/CODEOWNERS deleted file mode 100644 index e2a52ae39..000000000 --- a/CODEOWNERS +++ /dev/null @@ -1 +0,0 @@ -* @felipebalbi @jerrysxie @tullom @RobertZ2011 @dymk diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md deleted file mode 100644 index 8603671fb..000000000 --- a/CODE_OF_CONDUCT.md +++ /dev/null @@ -1,132 +0,0 @@ -# Contributor Covenant Code of Conduct - -## Our Pledge - -We as members, contributors, and leaders pledge to make participation in our -community a harassment-free experience for everyone, regardless of age, body -size, visible or invisible disability, ethnicity, sex characteristics, gender -identity and expression, level of experience, education, socio-economic status, -nationality, personal appearance, race, caste, color, religion, or sexual -identity and orientation. - -We pledge to act and interact in ways that contribute to an open, welcoming, -diverse, inclusive, and healthy community. - -## Our Standards - -Examples of behavior that contributes to a positive environment for our -community include: - -* Demonstrating empathy and kindness toward other people -* Being respectful of differing opinions, viewpoints, and experiences -* Giving and gracefully accepting constructive feedback -* Accepting responsibility and apologizing to those affected by our mistakes, - and learning from the experience -* Focusing on what is best not just for us as individuals, but for the overall - community - -Examples of unacceptable behavior include: - -* The use of sexualized language or imagery, and sexual attention or advances of - any kind -* Trolling, insulting or derogatory comments, and personal or political attacks -* Public or private harassment -* Publishing others' private information, such as a physical or email address, - without their explicit permission -* Other conduct which could reasonably be considered inappropriate in a - professional setting - -## Enforcement Responsibilities - -Community leaders are responsible for clarifying and enforcing our standards of -acceptable behavior and will take appropriate and fair corrective action in -response to any behavior that they deem inappropriate, threatening, offensive, -or harmful. - -Community leaders have the right and responsibility to remove, edit, or reject -comments, commits, code, wiki edits, issues, and other contributions that are -not aligned to this Code of Conduct, and will communicate reasons for moderation -decisions when appropriate. - -## Scope - -This Code of Conduct applies within all community spaces, and also applies when -an individual is officially representing the community in public spaces. -Examples of representing our community include using an official e-mail address, -posting via an official social media account, or acting as an appointed -representative at an online or offline event. - -## Enforcement - -Instances of abusive, harassing, or otherwise unacceptable behavior may be -reported to the community leaders responsible for enforcement at -odpadmin@microsoft.com. -All complaints will be reviewed and investigated promptly and fairly. - -All community leaders are obligated to respect the privacy and security of the -reporter of any incident. - -## Enforcement Guidelines - -Community leaders will follow these Community Impact Guidelines in determining -the consequences for any action they deem in violation of this Code of Conduct: - -### 1. Correction - -**Community Impact**: Use of inappropriate language or other behavior deemed -unprofessional or unwelcome in the community. - -**Consequence**: A private, written warning from community leaders, providing -clarity around the nature of the violation and an explanation of why the -behavior was inappropriate. A public apology may be requested. - -### 2. Warning - -**Community Impact**: A violation through a single incident or series of -actions. - -**Consequence**: A warning with consequences for continued behavior. No -interaction with the people involved, including unsolicited interaction with -those enforcing the Code of Conduct, for a specified period of time. This -includes avoiding interactions in community spaces as well as external channels -like social media. Violating these terms may lead to a temporary or permanent -ban. - -### 3. Temporary Ban - -**Community Impact**: A serious violation of community standards, including -sustained inappropriate behavior. - -**Consequence**: A temporary ban from any sort of interaction or public -communication with the community for a specified period of time. No public or -private interaction with the people involved, including unsolicited interaction -with those enforcing the Code of Conduct, is allowed during this period. -Violating these terms may lead to a permanent ban. - -### 4. Permanent Ban - -**Community Impact**: Demonstrating a pattern of violation of community -standards, including sustained inappropriate behavior, harassment of an -individual, or aggression toward or disparagement of classes of individuals. - -**Consequence**: A permanent ban from any sort of public interaction within the -community. - -## Attribution - -This Code of Conduct is adapted from the [Contributor Covenant][homepage], -version 2.1, available at -[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1]. - -Community Impact Guidelines were inspired by -[Mozilla's code of conduct enforcement ladder][Mozilla CoC]. - -For answers to common questions about this code of conduct, see the FAQ at -[https://www.contributor-covenant.org/faq][FAQ]. Translations are available at -[https://www.contributor-covenant.org/translations][translations]. - -[homepage]: https://www.contributor-covenant.org -[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html -[Mozilla CoC]: https://github.com/mozilla/diversity -[FAQ]: https://www.contributor-covenant.org/faq -[translations]: https://www.contributor-covenant.org/translations \ No newline at end of file diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md deleted file mode 100644 index c45bc8e43..000000000 --- a/CONTRIBUTING.md +++ /dev/null @@ -1,35 +0,0 @@ -# Contributing to Open Device Partnership - -The Open Device Partnership project welcomes your suggestions and contributions! Before opening your first issue or pull request, please review our -[Code of Conduct](CODE_OF_CONDUCT.md) to understand how our community interacts in an inclusive and respectful manner. - -## Contribution Licensing - -Most of our code is distributed under the terms of the [MIT license](LICENSE), and when you contribute code that you wrote to our repositories, -you agree that you are contributing under those same terms. In addition, by submitting your contributions you are indicating that -you have the right to submit those contributions under those terms. - -## Other Contribution Information - -If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your -pull request so that the project team can discuss the situation with you. - -## Commit Message - -* Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html) - -## PR Etiquette - -* Create a draft PR first -* Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers. - -## Clean Commit History - -We disabled squashing of commit and would like to maintain a clean commit history. So please reorganize your commits with the following items: - -* Each commit builds successfully without warning -* Miscellaneous commits to fix typos + formatting are squashed - -## Regressions - -When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster. diff --git a/Cargo.toml b/Cargo.toml index 71c4806fe..858dc0974 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,19 +1,121 @@ [package] -name = "embedded-rust-template" +name = "embassy-mcxa276" version = "0.1.0" edition = "2021" -license = "MIT" -repository = "https://github.com/OpenDevicePartnership/embedded-rust-template" -rust-version = "1.85" +license = "MIT OR Apache-2.0" +description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA276" +keywords = ["embedded", "hal", "nxp", "mcxa276", "embassy"] +categories = ["embedded", "hardware-support", "no-std"] + +[lib] +name = "embassy_mcxa276" [dependencies] -# dependencies for all targets +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +cortex-m-rt = { version = "0.7", features = ["device"] } +mcxa276-pac = { path = "./mcxa276-pac", features = ["rt"] } +embedded-io = "0.6" +# Optional defmt support +defmt = { version = "0.3", optional = true } +defmt-rtt = { version = "0.4", optional = true } +rtt-target = { version = "0.4", optional = true } +panic-probe = { version = "0.3", features = ["print-defmt"], optional = true } +embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } +embassy-time = "0.5.0" +embassy-time-driver = "0.2.1" +embassy-sync = "0.7.2" +embassy-embedded-hal = "0.5.0" +embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] } +critical-section = "1.2.0" +paste = "1.0.15" +heapless = "0.8" + +embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [ + "unproven", +] } +embedded-hal = { package = "embedded-hal", version = "1.0" } +embedded-hal-async = { version = "1.0" } +embedded-hal-nb = { version = "1.0" } +embedded-io-async = { version = "0.6.1" } +nb = "1.1.0" + +[features] +default = [] +uart-debug = [] +gpio = [] +lpuart2 = [] +ostimer0 = [] +rtc0 = [] +adc1 = [] +rt = [] +# Base defmt feature enables core + panic handler +# Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) +defmt = ["dep:defmt", "dep:panic-probe"] +# RTT logger +# Usage: cargo embed --features "defmt defmt-rtt lpuart2" --example hello +# or: PROBE_RS_PROBE= cargo embed --features "defmt defmt-rtt lpuart2" --example hello +defmt-rtt = ["dep:defmt-rtt", "dep:rtt-target"] +# Optional: UART-based defmt (no RTT). Enable with `--features defmt-uart defmt`. +# defmt-uart = [] # Removed - no longer needed + + +[[example]] +name = "hello" +required-features = ["lpuart2"] + +[[example]] +name = "blink" +required-features = ["gpio", "ostimer0"] + +[[example]] +name = "uart_interrupt" +required-features = ["lpuart2", "ostimer0"] + +[[example]] +name = "ostimer_alarm" +required-features = ["lpuart2", "ostimer0"] + +[[example]] +name = "ostimer_async" +required-features = ["lpuart2", "ostimer0"] + +[[example]] +name = "ostimer_counter" +required-features = ["lpuart2", "ostimer0"] + +[[example]] +name = "ostimer_race_test" +required-features = ["lpuart2", "ostimer0"] + +[[example]] +name = "lpuart_polling" +required-features = ["lpuart2", "ostimer0"] + +[[example]] +name = "lpuart_buffered" +required-features = ["lpuart2", "ostimer0"] + +[[example]] +name = "rtc_alarm" +required-features = ["lpuart2", "rtc0"] + +[[example]] +name = "adc_polling" +required-features = ["adc1", "lpuart2"] + +[[example]] +name = "adc_interrupt" +required-features = ["adc1", "lpuart2"] + +[profile.release] +debug = 2 +lto = true +opt-level = "s" + +[profile.dev] +debug = 2 +opt-level = 1 + +[dev-dependencies] -[target.'cfg(target_os = "none")'.dependencies] -# dependencies for no-std targets -[lints.clippy] -suspicious = "forbid" -correctness = "forbid" -perf = "forbid" -style = "forbid" diff --git a/Embed.toml b/Embed.toml new file mode 100644 index 000000000..40218c8bf --- /dev/null +++ b/Embed.toml @@ -0,0 +1,28 @@ +[default.probe] +# Use the first available probe +protocol = "Swd" +speed = 1000 + +[default.flashing] +# Attach-only: don't flash (we already loaded to RAM) +enabled = false + +[default.reset] +# Don't reset; keep running app started by run_jlink_noblock.sh +enabled = false + +[default.general] +# The chip name of the target +chip = "MCXA276" + +[default.gdb] +# Whether or not a GDB server should be opened after loading +enabled = false + +[default.rtt] +# Enable RTT for debugging output +enabled = true + +# Increase timeout for RTT CB discovery +up_channels = [ { channel = 0, mode = "BlockIfFull" } ] +timeout = 5000 diff --git a/LICENSE b/LICENSE deleted file mode 100644 index 75092dc47..000000000 --- a/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2025 Open Device Partnership - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. \ No newline at end of file diff --git a/License.txt b/License.txt new file mode 100644 index 000000000..479657c89 --- /dev/null +++ b/License.txt @@ -0,0 +1,22 @@ +MIT License + +Copyright (c) 2025 OEMWCSE + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + diff --git a/README.md b/README.md deleted file mode 100644 index 60b09c0a6..000000000 --- a/README.md +++ /dev/null @@ -1,63 +0,0 @@ -# embedded-rust-template -Template repository for Embedded Rust development - -## Customizing This Template - -### Changing the Target Architecture - -This template is configured for `thumbv8m.main-none-eabihf`, by default, but you can modify it for other targets (i.e. `aarch64-unknown-none`): - -1. **VSCode Settings**: Update the target in `.vscode/settings.json`: - ```json - "rust-analyzer.cargo.target": "your-target-architecture" - ``` - - -This configuration ensures that: -- Only the specified target architecture is analyzed, not the host platform -- Code is checked against the no_std environment - -To temporarily analyze code for the host platform instead, you can remove the `rust-analyzer.cargo.target` setting. - -2. **GitHub Workflows**: Modify the target in two workflow files: - - `.github/workflows/nostd.yml`: Update the targets in the matrix: - ```yaml - matrix: - target: [your-target-architecture] - ``` - - `.github/workflows/check.yml`: If there are any target-specific checks, update them accordingly. - -3. **Cargo Configuration**: If needed, you can add target-specific configuration in a `.cargo/config.toml` file. - -### Converting from Binary to Library - -To convert this project from a binary to a library: - -1. **Cargo.toml**: Update your project structure: - ```toml - [lib] - name = "your_library_name" - ``` - -2. **Directory Structure**: - - For a library, ensure you have a `src/lib.rs` file instead of `src/main.rs` - - Move your code from `main.rs` to `lib.rs` and adjust as needed - -3. **No-std Configuration**: If you're creating a no-std library, ensure you have: - ```rust - // In lib.rs - #![cfg_attr(target_os = "none", no_std)] - // Add other attributes as needed - ``` - -### Project Dependencies - -Update the dependencies in `Cargo.toml` based on your target platform: - -```toml -[dependencies] -# Common dependencies for all targets - -[target.'cfg(target_os = "none")'.dependencies] -# Dependencies for no-std targets -``` diff --git a/README.txt b/README.txt new file mode 100644 index 000000000..7baf8a9cb --- /dev/null +++ b/README.txt @@ -0,0 +1,340 @@ +# Embassy MCXA276 HAL + +A Hardware Abstraction Layer (HAL) for the NXP MCXA276 microcontroller using the Embassy async framework. This HAL provides safe, idiomatic Rust interfaces for GPIO, UART, and OSTIMER peripherals. + +## Prerequisites + +### Ubuntu/Debian Setup + +```bash +# Install Rust toolchain +curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh +source ~/.cargo/env + +# Add target for MCXA276 (ARM Cortex-M33) +rustup target add thumbv8m.main-none-eabihf + +# Install required tools +sudo apt update +sudo apt install -y gdb-multiarch curl wget + +# Install probe-rs for running and debugging +cargo install probe-rs --features cli +``` + +### Windows Setup + +- Install Rust via https://rustup.rs (default options are fine) +- Add the MCXA276 target: + ```powershell + rustup target add thumbv8m.main-none-eabihf + ``` +- Install probe-rs CLI (we will use it directly; no GDB required): + ```powershell + cargo install probe-rs --features cli + ``` +- Install a serial terminal (e.g., Tera Term): https://ttssh2.osdn.jp/ +- USB drivers: Windows 10/11 usually picks up the board as a USB CDC device automatically (COM port) + + + +### Hardware Requirements + +- NXP FRDM-MCXA276 development board +- Debug probe (CMSIS-DAP compatible) +- USB cable for power and programming + +## Examples + +This HAL includes several examples demonstrating different peripherals: + +### GPIO Examples + +#### `blink` +Blinks an LED connected to GPIO pin. Demonstrates basic GPIO output operations. + +### UART Examples + +#### `hello` +Interactive UART2 demo: prints a banner and supports `help`, `echo `, `hex `. + +### OSTIMER Examples + +#### `ostimer_alarm` + +Demonstrates setting and waiting for OSTIMER alarms. + +#### `ostimer_async` +Shows asynchronous OSTIMER operations with Embassy's async runtime. + +#### `ostimer_counter` +Demonstrates OSTIMER counter functionality. + +#### `ostimer_race_test` +Advanced example testing OSTIMER race conditions and synchronization. + +### RTC Example + +#### `rtc_alarm` +Demonstrates how to enable and use the RTC to generate an interrupt after 10seconds. + +## Build and Run + +### Using probe-rs + +All examples require specifying your debug probe. First, find your probe ID: + +```bash +probe-rs list +``` + +Then run examples with your probe ID (replace `1fc9:0143:H3AYDQVQMTROB` with your actual probe): + +```bash +# GPIO blink example +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "gpio ostimer0" --example blink + + + +# UART hello example +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example hello + +# OSTIMER examples +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_async +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_counter +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_race_test + +# RTC example +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 rtc0" --example rtc_alarm +``` +**Note:** All examples run from RAM, not flash memory. They are loaded directly into RAM for faster development iteration. + +**Important:** After pressing the RESET button on the board, the first `cargo run` attempt may fail with a connection error. This is expected - simply run the command again and it will work. The run.sh script now properly sets the Vector Table Offset Register (VTOR) to point to the RAM-based vector table, ensuring the correct stack pointer and reset vector are used. + +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink + Finished `release` profile [optimized + debuginfo] target(s) in 0.07s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` +probe-rs gdb server failed to connect to target. Log: +----- probe-rs gdb log ----- + Error: Connecting to the chip was unsuccessful. + + Caused by: + 0: An ARM specific error occurred. + 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. + 2: Failed to read register DRW at address 0xd0c + 3: An error occurred in the communication with an access port or debug port. + 4: Target device responded with a FAULT response to the request. +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink + Finished `release` profile [optimized + debuginfo] target(s) in 0.02s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` + +### Additional UART Examples + +#### `uart_interrupt` +Interrupt-driven UART2 echo. Type in the serial terminal; each byte is echoed back from the IRQ handler path. + +#### `lpuart_polling` +Blocking TX/RX echo over UART2 using the simple polling driver. + +#### `lpuart_buffered` +Async buffered driver with separate TX/RX tasks; echoes typed characters in chunks. + +Pins: UART2 TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. + +### ADC Examples + +#### `adc_polling` +Configures ADC1 channel A8 (pin P1_10) and prints conversion values to UART2 periodically. + +#### `adc_interrupt` +Triggers a conversion and signals completion via ADC1 interrupt, printing a notification on UART2. + +0x20002040 in ?? () +Supported Commands: + + info - print session information + reset - reset target + reset halt - reset target and halt afterwards + +Loading section .vector_table, size 0x224 lma 0x20000000 +Loading section .text, size 0x97e lma 0x20000224 +Loading section .Reset, size 0x58 lma 0x20000ba4 +Loading section .rodata, size 0x28 lma 0x20000bfc +Start address 0x20000ba4, load size 3106 +Transfer rate: 13 KB/sec, 776 bytes/write. + +then I see the LED blinking. I press CTRL+C to exit. It will show me ^C +Program received signal SIGINT, Interrupt. +0x20000880 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 +106 asm!("wfe"); +[Inferior 1 (process 1) detached] +Program loaded and started (no reset) +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ \ + +Then I press RESET again and I want to run another example, like ostimer_alarm. I open the console using sudo picocom -b 115200 /dev/ttyACM0 and I start running the example: + +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm + Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` +probe-rs gdb server failed to connect to target. Log: +----- probe-rs gdb log ----- + Error: Connecting to the chip was unsuccessful. + + Caused by: + 0: An ARM specific error occurred. + 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. + 2: Failed to read register DRW at address 0xd0c + 3: An error occurred in the communication with an access port or debug port. + 4: Target device responded with a FAULT response to the request. +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm + Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` +0x20002040 in core::panicking::panic_const::panic_const_mul_overflow () at library/core/src/panicking.rs:175 +warning: 175 library/core/src/panicking.rs: No such file or directory +Supported Commands: + + info - print session information + reset - reset target + reset halt - reset target and halt afterwards + +Loading section .vector_table, size 0x224 lma 0x20000000 +Loading section .text, size 0x2226 lma 0x20000224 +Loading section .Reset, size 0x58 lma 0x2000244c +Loading section .rodata, size 0x6dc lma 0x200024a4 +Start address 0x2000244c, load size 11134 +Transfer rate: 16 KB/sec, 1855 bytes/write. + +I can see in the console +OSTIMER Alarm Example +Scheduling alarm for 2 seconds... +Alarm scheduled successfully +Alarm expired! Callback executed. +Scheduling another alarm for 3 seconds... +Alarm scheduled. Waiting 1 second then canceling... +Alarm canceled +Alarm was successfully canceled +Example complete + +then I press CTRL+C to stop running + +^C +Program received signal SIGINT, Interrupt. +0x20000e64 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 +106 asm!("wfe"); +[Inferior 1 (process 1) detached] +Program loaded and started (no reset) +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ + + +### Windows: Running examples (RAM, no RTT/defmt) + +Important: On Windows, do not use `cargo run` because `.cargo/config.toml` sets a Linux-only runner (`./run.sh`). Instead, use `probe-rs run` directly. + +1) Find your probe and COM port +- List probes: + ```powershell + probe-rs list + ``` +- If multiple probes are attached, set the specific one (replace with your ID): + ```powershell + $env:PROBE_RS_PROBE = "1366:0101:000600110607" + ``` +- Check Windows Device Manager → Ports (COM & LPT) for the board’s COM port. + +2) Build the example +```powershell +cargo build --example hello --features "lpuart2" +``` + +3) Run from RAM with probe-rs +```powershell +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/hello +``` +You will see a short probe-rs warning like "unknown variant, try to set watch point"; it’s harmless. + +4) View output in Tera Term +- Open Tera Term, select the board’s COMx port, 115200 8N1 +- Expected behavior per example: + - hello: prints a banner; simple UART output + - lpuart_polling / lpuart_buffered / uart_interrupt: echo typed characters + - adc_polling: prints ADC values periodically (ADC1 channel A8 on P1_10) + - adc_interrupt: prints "*** ADC interrupt TRIGGERED! ***" upon conversion completion + - blink: LED on PIO3_18 blinks "SOS" pattern + - rtc_alarm: schedules, cancels and reports alarm events on UART + +Notes +- All examples run from RAM (not flashed). Reset clears the program. +- If the first attempt after a reset fails to connect, just run the command again. +- UART2 pins: TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. + +Quick commands for other examples (PowerShell) +```powershell +# Build +cargo build --example blink --features "gpio ostimer0" +cargo build --example lpuart_polling --features "lpuart2 ostimer0" +cargo build --example lpuart_buffered --features "lpuart2 ostimer0" +cargo build --example uart_interrupt --features "lpuart2 ostimer0" +cargo build --example rtc_alarm --features "lpuart2 rtc0" +cargo build --example adc_polling --features "adc1 lpuart2" +cargo build --example adc_interrupt --features "adc1 lpuart2" + +# Run (RAM) +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/blink +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_polling +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_buffered +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/uart_interrupt +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/rtc_alarm +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_polling +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_interrupt +``` + +How I tested on Windows +- Windows 11; Rust stable; probe-rs 0.29.x +- Built each example as above; ran with `probe-rs run` (RAM execution) +- Observed UART output in Tera Term at 115200 8N1; all examples behaved as expected +- No RTT/defmt used; purely UART or LED observation + +### Build Only + +To build without running: + +```bash +cargo build --features "gpio ostimer0" --example blink +cargo build --features "lpuart2 ostimer0" --example hello +cargo build --features "lpuart2 ostimer0" --example ostimer_alarm +cargo build --features "lpuart2 rtc0" --example rtc_alarm +# etc. +``` + + +## Development Notes + +### Critical Fix: MCXA276 Interrupt Vector Table + +**Problem:** The OSTIMER examples crashed during interrupt handling with a hardfault (SP=0x00000000). Investigation revealed the OS_EVENT interrupt vector was NULL in the vector table, causing the CPU to jump to address 0 when OSTIMER interrupts fired. + +**Root Cause:** The `mcxa276-pac/src/lib.rs` file (generated from the SVD file) was missing the `WAKETIMER0` interrupt handler declaration. This caused the `__INTERRUPTS` array to have an off-by-one error, placing OS_EVENT at IRQ 58 instead of the correct IRQ 57 position. + +**Solution:** Manually edited `mcxa276-pac/src/lib.rs` to add the missing WAKETIMER0 interrupt: + +1. Added `fn WAKETIMER0()` to the `extern "C"` block +2. Fixed the `__INTERRUPTS: [Vector; 122]` array sequence: + - Changed from: `LPTMR0, _reserved, _reserved, OS_EVENT, _reserved, UTICK0, ...` + - Changed to: `LPTMR0, _reserved, OS_EVENT, WAKETIMER0, UTICK0, WWDT0, _reserved, ADC0, ...` +3. Added `WAKETIMER0 = 58` to the `Interrupt` enum + +**Verification:** Binary analysis confirmed OS_EVENT is now at the correct position: +- IRQ 57 = word 73 = offset 0x124 in vector table +- OS_EVENT handler: 0x20000BB1 (verified with `arm-none-eabi-objdump`) + +**Note:** This is likely an issue with the NXP MCXA276.svd file or svd2rust generation. The WAKETIMER0 peripheral exists in the PAC but the interrupt handler was missing. Future regeneration of the PAC from SVD may require reapplying this fix. + +### Warning: Avoid `#[inline(always)]` in Performance-Critical Code + +Using `#[inline(always)]` can cause the Rust compiler to generate incorrect assembly, leading to register corruption or unexpected behavior. For example, in tight polling loops like those in the OSTIMER driver, this attribute may result in invalid instructions that zero registers (e.g., `movs r1, r0` causing r1=0), triggering hardfaults. + + +## License + +This project is licensed under MIT OR Apache-2.0. diff --git a/SECURITY.md b/SECURITY.md deleted file mode 100644 index 6ed358156..000000000 --- a/SECURITY.md +++ /dev/null @@ -1,66 +0,0 @@ -# Vulnerability Disclosure and Embargo Policy - -The Open Device Partnership project welcomes the responsible disclosure of vulnerabilities. - -## Initial Contact - -All security bugs in Open Device Partnership should be reported to the security team. -To do so, please reach out in the form of a -[Github Security Advisory](https://docs.github.com/en/code-security/security-advisories/guidance-on-reporting-and-writing-information-about-vulnerabilities). - -You will be invited to join this private area to discuss specifics. Doing so -allows us to start with a high level of confidentiality and relax it if the -issue is less critical, moving to work on the fix in the open. - -Your initial contact will be acknowledged within 48 hours, and you’ll receive -a more detailed response within 96 hours indicating the next steps in handling -your report. - -After the initial reply to your report, the security team will endeavor to -keep you informed of the progress being made towards a fix and full -announcement. As recommended by -[RFPolicy](https://dl.packetstormsecurity.net/papers/general/rfpolicy-2.0.txt), -these updates will be sent at least every five working days. - -## Disclosure Policy - -The Open Device Partnership project has a 5 step disclosure process. - -1. Contact is established, a private channel created, and the security report - is received and is assigned a primary handler. This person will coordinate - the fix and release process. -2. The problem is confirmed and a list of all affected versions is determined. - If an embargo is needed (see below), details of the embargo are decided. -3. Code is audited to find any potential similar problems. -4. Fixes are prepared for all releases which are still under maintenance. In - case of embargo, these fixes are not committed to the public repository but - rather held in a private fork pending the announcement. -5. The changes are pushed to the public repository and new builds are deployed. - -This process can take some time, especially when coordination is required -with maintainers of other projects. Every effort will be made to handle the bug -in as timely a manner as possible, however it is important that we follow the -release process above to ensure that the disclosure is handled in a consistent -manner. - -## Embargoes - -While the Open Device Partnership project aims to follow the highest standards of -transparency and openness, handling some security issues may pose such an -immediate threat to various stakeholders and require coordination between -various actors that it cannot be made immediately public. - -In this case, security issues will fall under an embargo. - -An embargo can be called for in various cases: - -- when disclosing the issue without simultaneously providing a mitigation - would seriously endanger users, -- when producing a fix requires coordinating between multiple actors (such as - upstream or downstream/dependency projects), or simply -- when proper analysis of the issue and its ramifications demands time. - -If we determine that an issue you report requires an embargo, we will discuss -this with you and try to find a reasonable expiry date (aka “embargo -completion date”), as well as who should be included in the list of -need-to-know people. \ No newline at end of file diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt new file mode 100644 index 000000000..7f9bee9e5 --- /dev/null +++ b/SW-Content-Register.txt @@ -0,0 +1,76 @@ +Release Name: Embassy MCXA276 HAL +Release Version: 0.1.0 +Package License: MIT (see ./License.txt) +Note: The crate is dual-licensed “MIT OR Apache-2.0” per Cargo.toml; choosing MIT satisfies the dual-license terms. + +Scope of this Register +This file documents software content that is part of this repository and, for transparency, lists major non-vendored Rust dependencies that are resolved from crates.io during builds. Components that are not present in the repository (e.g., external crates) are listed under “Non‑vendored Rust dependencies”. + +Repository Components (included in this release) + +embassy_mcxa276_hal Name: Embassy MCXA276 HAL (library + examples) + Version: 0.1.0 + Outgoing License: MIT + License File: ./License.txt + Format: Rust source code, examples, scripts, linker scripts + Description: Hardware Abstraction Layer for NXP MCXA276 using the Embassy async framework. Implements drivers and helpers for: + - LPUART2 (UART), OSTIMER0, RTC0, ADC1, GPIO + - Embassy integration (executors, time) + Location: ./src, ./examples, ./build.rs, ./memory.x, ./ram.ld, ./defmt.x, ./.cargo/config.toml, ./run.sh, ./tools/ + Origin: OEMWCSE (MIT) + URL: https://bitbucket.sw.nxp.com/scm/oemwcse/mcxa_rust.git + +mcxa276_pac Name: MCXA276 Peripheral Access Crate (PAC) + Version: 0.1.0 + Outgoing License: MIT OR Apache-2.0 + License File: (see crate metadata) + Format: Rust source code (auto-generated PAC) + Description: Auto-generated register mappings for MCXA276 peripherals (svd2rust). Includes device.x and interrupt vectors. This tree contains a small manual correction for a missing WAKETIMER0 vector/enum entry. + Location: ./mcxa276-pac + Origin: Generated by svd2rust from NXP SVD; local adjustments by OEMWCSE + URL: N/A (generated from NXP SVD) + +examples Name: Example applications + Version: N/A + Outgoing License: MIT + License File: ./License.txt + Format: Rust source code (examples) + Description: Demonstrations for HAL peripherals and features: + - hello, blink + - lpuart_polling, lpuart_buffered, uart_interrupt + - rtc_alarm + - adc_polling, adc_interrupt + - ostimer_alarm, ostimer_async, ostimer_counter, ostimer_race_test + Location: ./examples + Origin: OEMWCSE (MIT) + +Non‑vendored Rust dependencies (resolved from crates.io at build time) +The following crates are not vendored in this repository. They are fetched during builds via Cargo. See Cargo.lock for exact versions. License summaries below are for convenience; consult each crate for authoritative terms. + +cortex-m License: MIT OR Apache-2.0 Purpose: Cortex-M core support +cortex-m-rt License: MIT OR Apache-2.0 Purpose: Cortex-M runtime (vectors, reset) +embassy-executor License: MIT OR Apache-2.0 Purpose: Async executor for Cortex-M +embassy-time (+ driver) License: MIT OR Apache-2.0 Purpose: Time abstraction and drivers +embassy-sync License: MIT OR Apache-2.0 Purpose: No-std synchronization primitives +embassy-embedded-hal License: MIT OR Apache-2.0 Purpose: Traits/adapters for embedded-hal +embassy-hal-internal License: MIT OR Apache-2.0 Purpose: HAL building blocks (peripherals!) +embedded-hal (1.0) License: MIT OR Apache-2.0 Purpose: Core embedded hardware traits +embedded-hal (0.2.6) License: MIT OR Apache-2.0 Purpose: Legacy HAL traits ("unproven") +embedded-hal-async License: MIT OR Apache-2.0 Purpose: Async HAL traits +embedded-hal-nb License: MIT OR Apache-2.0 Purpose: Non-blocking HAL traits +embedded-io / embedded-io-async License: MIT OR Apache-2.0 Purpose: IO traits +critical-section License: MIT OR Apache-2.0 Purpose: Critical-section abstraction +heapless License: MIT OR Apache-2.0 Purpose: Fixed-capacity data structures +paste License: MIT OR Apache-2.0 Purpose: Macro hygiene utility +nb License: MIT OR Apache-2.0 Purpose: Non-blocking result type +vcell License: MIT OR Apache-2.0 Purpose: Volatile cell (PAC dependency) + +defmt, defmt-rtt, rtt-target, panic-probe License: MIT OR Apache-2.0 Purpose: Optional (feature-gated) logging/panic crates + +Attribution notes +- MCXA276 PAC was generated from NXP SVD data using svd2rust and locally adjusted (see README “Development Notes” for the WAKETIMER0 vector fix). +- Examples run from RAM using custom linker setup; see README.txt for platform-specific instructions. + +Compliance +- This repository’s distributed source is covered by MIT (see License.txt). Where crates are pulled from crates.io, those crates retain their own licenses; the dual-license compatibility (MIT OR Apache-2.0) is standard in the Rust embedded ecosystem and is compatible with this project’s selected MIT distribution. + diff --git a/build.rs b/build.rs new file mode 100644 index 000000000..645843590 --- /dev/null +++ b/build.rs @@ -0,0 +1,20 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + + // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH" + // cortex-m-rt expects FLASH for code, RAM for data/bss/stack + // Both are in RAM, but separated to satisfy cortex-m-rt's expectations + // MCXA276 has 128KB RAM total + File::create(out.join("memory.x")) + .unwrap() + .write_all(b"/* MCXA276 RAM-execution: FLASH region holds code, RAM region for data/stack */\nMEMORY { FLASH : ORIGIN = 0x20000000, LENGTH = 64K\n RAM : ORIGIN = 0x20010000, LENGTH = 64K }\n") + .unwrap(); + + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=memory.x"); +} diff --git a/defmt.x b/defmt.x new file mode 100644 index 000000000..dbd6d0850 --- /dev/null +++ b/defmt.x @@ -0,0 +1,6 @@ +/* + Dummy defmt.x to satisfy -Tdefmt.x when building without the `defmt` feature. + When `defmt` is enabled, the real defmt.x provided by the defmt crate is used via the linker search path. + This file intentionally contains no SECTIONS so it won't override ram.ld. +*/ + diff --git a/deny.toml b/deny.toml deleted file mode 100644 index 9ddd12fca..000000000 --- a/deny.toml +++ /dev/null @@ -1,239 +0,0 @@ -# This template contains all of the possible sections and their default values - -# Note that all fields that take a lint level have these possible values: -# * deny - An error will be produced and the check will fail -# * warn - A warning will be produced, but the check will not fail -# * allow - No warning or error will be produced, though in some cases a note -# will be - -# The values provided in this template are the default values that will be used -# when any section or field is not specified in your own configuration - -# Root options - -# The graph table configures how the dependency graph is constructed and thus -# which crates the checks are performed against -[graph] -# If 1 or more target triples (and optionally, target_features) are specified, -# only the specified targets will be checked when running `cargo deny check`. -# This means, if a particular package is only ever used as a target specific -# dependency, such as, for example, the `nix` crate only being used via the -# `target_family = "unix"` configuration, that only having windows targets in -# this list would mean the nix crate, as well as any of its exclusive -# dependencies not shared by any other crates, would be ignored, as the target -# list here is effectively saying which targets you are building for. -targets = [ - # The triple can be any string, but only the target triples built in to - # rustc (as of 1.40) can be checked against actual config expressions - #"x86_64-unknown-linux-musl", - # You can also specify which target_features you promise are enabled for a - # particular target. target_features are currently not validated against - # the actual valid features supported by the target architecture. - #{ triple = "wasm32-unknown-unknown", features = ["atomics"] }, -] -# When creating the dependency graph used as the source of truth when checks are -# executed, this field can be used to prune crates from the graph, removing them -# from the view of cargo-deny. This is an extremely heavy hammer, as if a crate -# is pruned from the graph, all of its dependencies will also be pruned unless -# they are connected to another crate in the graph that hasn't been pruned, -# so it should be used with care. The identifiers are [Package ID Specifications] -# (https://doc.rust-lang.org/cargo/reference/pkgid-spec.html) -#exclude = [] -# If true, metadata will be collected with `--all-features`. Note that this can't -# be toggled off if true, if you want to conditionally enable `--all-features` it -# is recommended to pass `--all-features` on the cmd line instead -all-features = false -# If true, metadata will be collected with `--no-default-features`. The same -# caveat with `all-features` applies -no-default-features = false -# If set, these feature will be enabled when collecting metadata. If `--features` -# is specified on the cmd line they will take precedence over this option. -#features = [] - -# The output table provides options for how/if diagnostics are outputted -[output] -# When outputting inclusion graphs in diagnostics that include features, this -# option can be used to specify the depth at which feature edges will be added. -# This option is included since the graphs can be quite large and the addition -# of features from the crate(s) to all of the graph roots can be far too verbose. -# This option can be overridden via `--feature-depth` on the cmd line -feature-depth = 1 - -# This section is considered when running `cargo deny check advisories` -# More documentation for the advisories section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/advisories/cfg.html -[advisories] -# The path where the advisory databases are cloned/fetched into -#db-path = "$CARGO_HOME/advisory-dbs" -# The url(s) of the advisory databases to use -#db-urls = ["https://github.com/rustsec/advisory-db"] -# A list of advisory IDs to ignore. Note that ignored advisories will still -# output a note when they are encountered. -ignore = [ - #"RUSTSEC-0000-0000", - #{ id = "RUSTSEC-0000-0000", reason = "you can specify a reason the advisory is ignored" }, - #"a-crate-that-is-yanked@0.1.1", # you can also ignore yanked crate versions if you wish - #{ crate = "a-crate-that-is-yanked@0.1.1", reason = "you can specify why you are ignoring the yanked crate" }, - { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." }, - { id = "RUSTSEC-2024-0436", reason = "there are no suitable replacements for paste right now; paste has been archived as read-only. It only affects compile time concatenation in macros. We will allow it for now" }, -] -# If this is true, then cargo deny will use the git executable to fetch advisory database. -# If this is false, then it uses a built-in git library. -# Setting this to true can be helpful if you have special authentication requirements that cargo-deny does not support. -# See Git Authentication for more information about setting up git authentication. -#git-fetch-with-cli = true - -# This section is considered when running `cargo deny check licenses` -# More documentation for the licenses section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/licenses/cfg.html -[licenses] -# List of explicitly allowed licenses -# See https://spdx.org/licenses/ for list of possible licenses -# [possible values: any SPDX 3.11 short identifier (+ optional exception)]. -allow = [ - "MIT", - "Apache-2.0", - "Unicode-3.0", - "BSD-3-Clause", - #"Apache-2.0 WITH LLVM-exception", -] -# The confidence threshold for detecting a license from license text. -# The higher the value, the more closely the license text must be to the -# canonical license text of a valid SPDX license file. -# [possible values: any between 0.0 and 1.0]. -confidence-threshold = 0.8 -# Allow 1 or more licenses on a per-crate basis, so that particular licenses -# aren't accepted for every possible crate as with the normal allow list -exceptions = [ - # Each entry is the crate and version constraint, and its specific allow - # list - #{ allow = ["Zlib"], crate = "adler32" }, -] - -# Some crates don't have (easily) machine readable licensing information, -# adding a clarification entry for it allows you to manually specify the -# licensing information -#[[licenses.clarify]] -# The package spec the clarification applies to -#crate = "ring" -# The SPDX expression for the license requirements of the crate -#expression = "MIT AND ISC AND OpenSSL" -# One or more files in the crate's source used as the "source of truth" for -# the license expression. If the contents match, the clarification will be used -# when running the license check, otherwise the clarification will be ignored -# and the crate will be checked normally, which may produce warnings or errors -# depending on the rest of your configuration -#license-files = [ -# Each entry is a crate relative path, and the (opaque) hash of its contents -#{ path = "LICENSE", hash = 0xbd0eed23 } -#] - -[licenses.private] -# If true, ignores workspace crates that aren't published, or are only -# published to private registries. -# To see how to mark a crate as unpublished (to the official registry), -# visit https://doc.rust-lang.org/cargo/reference/manifest.html#the-publish-field. -ignore = false -# One or more private registries that you might publish crates to, if a crate -# is only published to private registries, and ignore is true, the crate will -# not have its license(s) checked -registries = [ - #"https://sekretz.com/registry -] - -# This section is considered when running `cargo deny check bans`. -# More documentation about the 'bans' section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/bans/cfg.html -[bans] -# Lint level for when multiple versions of the same crate are detected -multiple-versions = "warn" -# Lint level for when a crate version requirement is `*` -wildcards = "allow" -# The graph highlighting used when creating dotgraphs for crates -# with multiple versions -# * lowest-version - The path to the lowest versioned duplicate is highlighted -# * simplest-path - The path to the version with the fewest edges is highlighted -# * all - Both lowest-version and simplest-path are used -highlight = "all" -# The default lint level for `default` features for crates that are members of -# the workspace that is being checked. This can be overridden by allowing/denying -# `default` on a crate-by-crate basis if desired. -workspace-default-features = "allow" -# The default lint level for `default` features for external crates that are not -# members of the workspace. This can be overridden by allowing/denying `default` -# on a crate-by-crate basis if desired. -external-default-features = "allow" -# List of crates that are allowed. Use with care! -allow = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is allowed" }, -] -# List of crates to deny -deny = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is banned" }, - # Wrapper crates can optionally be specified to allow the crate when it - # is a direct dependency of the otherwise banned crate - #{ crate = "ansi_term@0.11.0", wrappers = ["this-crate-directly-depends-on-ansi_term"] }, -] - -# List of features to allow/deny -# Each entry the name of a crate and a version range. If version is -# not specified, all versions will be matched. -#[[bans.features]] -#crate = "reqwest" -# Features to not allow -#deny = ["json"] -# Features to allow -#allow = [ -# "rustls", -# "__rustls", -# "__tls", -# "hyper-rustls", -# "rustls", -# "rustls-pemfile", -# "rustls-tls-webpki-roots", -# "tokio-rustls", -# "webpki-roots", -#] -# If true, the allowed features must exactly match the enabled feature set. If -# this is set there is no point setting `deny` -#exact = true - -# Certain crates/versions that will be skipped when doing duplicate detection. -skip = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason why it can't be updated/removed" }, -] -# Similarly to `skip` allows you to skip certain crates during duplicate -# detection. Unlike skip, it also includes the entire tree of transitive -# dependencies starting at the specified crate, up to a certain depth, which is -# by default infinite. -skip-tree = [ - #"ansi_term@0.11.0", # will be skipped along with _all_ of its direct and transitive dependencies - #{ crate = "ansi_term@0.11.0", depth = 20 }, -] - -# This section is considered when running `cargo deny check sources`. -# More documentation about the 'sources' section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/sources/cfg.html -[sources] -# Lint level for what to happen when a crate from a crate registry that is not -# in the allow list is encountered -unknown-registry = "warn" -# Lint level for what to happen when a crate from a git repository that is not -# in the allow list is encountered -unknown-git = "warn" -# List of URLs for allowed crate registries. Defaults to the crates.io index -# if not specified. If it is specified but empty, no registries are allowed. -allow-registry = ["https://github.com/rust-lang/crates.io-index"] -# List of URLs for allowed Git repositories -allow-git = [] - -[sources.allow-org] -# github.com organizations to allow git sources for -github = ["embassy-rs"] -# gitlab.com organizations to allow git sources for -gitlab = [] -# bitbucket.org organizations to allow git sources for -bitbucket = [] diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs new file mode 100644 index 000000000..452eaae01 --- /dev/null +++ b/examples/adc_interrupt.rs @@ -0,0 +1,106 @@ +#![no_std] +#![no_main] + +use embassy_mcxa276 as hal; +use cortex_m; +use embassy_executor::Spawner; + +use hal::adc::{TriggerPriorityPolicy, LpadcConfig}; +use hal::pac::adc1::cfg::{Refsel, Pwrsel}; +use hal::pac::adc1::tctrl::{Tcmd}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::{CalAvgs}; + +use hal::uart; +mod common; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use hal::bind_interrupts; +use hal::InterruptExt; + +bind_interrupts!(struct Irqs { + ADC1 => hal::adc::AdcHandler; +}); + +#[used] +#[no_mangle] +static KEEP_ADC: unsafe extern "C" fn() = ADC1; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + unsafe { + common::init_uart2(hal::pac()); + } + + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); + + unsafe { + common::init_adc(hal::pac()); + } + + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + + adc.enable_interrupt(0x1); + + unsafe { + hal::interrupt::ADC1.enable(); + } + + unsafe { + cortex_m::interrupt::enable(); + } + + loop { + adc.do_software_trigger(1); + while !adc.is_interrupt_triggered() { + // Wait until the interrupt is triggered + } + uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); + //TBD need to print the value + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} \ No newline at end of file diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs new file mode 100644 index 000000000..7cb728e91 --- /dev/null +++ b/examples/adc_polling.rs @@ -0,0 +1,95 @@ +#![no_std] +#![no_main] + +use embassy_mcxa276 as hal; + +use embassy_executor::Spawner; + +use hal::adc::{TriggerPriorityPolicy, LpadcConfig, ConvResult}; +use hal::pac::adc1::cfg::{Refsel, Pwrsel}; +use hal::pac::adc1::tctrl::{Tcmd}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::{CalAvgs}; + +use hal::uart; + +mod common; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use core::fmt::Write; +use heapless::String; + + +const G_LPADC_RESULT_SHIFT: u32 = 0; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + unsafe { + common::init_uart2(hal::pac()); + } + + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n"); + + unsafe { + common::init_adc(hal::pac()); + } + + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + + loop { + adc.do_software_trigger(1); + let mut result: Option = None; + while result.is_none() { + result = hal::adc::get_conv_result(); + } + let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; + let mut buf: String<16> = String::new(); // adjust size as needed + write!(buf, "\r\nvalue: {}\r\n", value).unwrap(); + uart.write_str_blocking(&buf); + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} \ No newline at end of file diff --git a/examples/blink.rs b/examples/blink.rs new file mode 100644 index 000000000..6289ac14e --- /dev/null +++ b/examples/blink.rs @@ -0,0 +1,93 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa276 as hal; +use embassy_time::{Duration, Timer}; +use hal::gpio::pins::PIO3_18; +use hal::gpio::{Level, Output}; + +mod common; + +use embassy_mcxa276::bind_interrupts; + +// Bind only OS_EVENT for timer interrupts +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + + // Board-style init: enable LED GPIO/PORT clocks used by blink + unsafe { + common::init_led(hal::pac()); + } + // Initialize OSTIMER for async timing + unsafe { + common::init_ostimer0(hal::pac()); + } + + // Initialize embassy-time global driver backed by OSTIMER0 + hal::ostimer::time_driver::init( + hal::config::Config::default().time_interrupt_priority, + 1_000_000, + ); + + // Configure LED pin for GPIO mode + PIO3_18::set_mux_gpio(); + + let mut led = Output::new(PIO3_18::degrade(), Level::High); + + // Complex blinking pattern: SOS in Morse code + // S: ... (3 short) + // O: --- (3 long) + // S: ... (3 short) + // With pauses between letters and words + + loop { + // S: three short blinks + for _ in 0..3 { + led.set_low(); + Timer::after(Duration::from_millis(150)).await; + led.set_high(); + Timer::after(Duration::from_millis(150)).await; + } + + // Pause between letters + Timer::after(Duration::from_millis(300)).await; + + // O: three long blinks + for _ in 0..3 { + led.set_low(); + Timer::after(Duration::from_millis(450)).await; + led.set_high(); + Timer::after(Duration::from_millis(150)).await; + } + + // Pause between letters + Timer::after(Duration::from_millis(300)).await; + + // S: three short blinks + for _ in 0..3 { + led.set_low(); + Timer::after(Duration::from_millis(150)).await; + led.set_high(); + Timer::after(Duration::from_millis(150)).await; + } + + // Long pause between words (SOS repeats) + Timer::after(Duration::from_millis(1000)).await; + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/common/mod.rs b/examples/common/mod.rs new file mode 100644 index 000000000..7ada4c456 --- /dev/null +++ b/examples/common/mod.rs @@ -0,0 +1,45 @@ +//! Shared board-specific helpers for the FRDM-MCXA276 examples. +//! These live with the examples so the HAL stays generic. + +use embassy_mcxa276 as hal; +use hal::{clocks, pins, reset}; + +/// Initialize clocks and pin muxing for UART2 debug console. +/// Safe to call multiple times; writes are idempotent for our use. +#[allow(dead_code)] +pub unsafe fn init_uart2(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_uart2_port2(p); + reset::release_reset_port2(p); + reset::release_reset_lpuart2(p); + pins::configure_uart2_pins_port2(); + clocks::select_uart2_clock(p); +} + +/// Initialize clocks for the LED GPIO/PORT used by the blink example. +#[allow(dead_code)] +pub unsafe fn init_led(p: &hal::pac::Peripherals) { + clocks::enable_led_port(p); + reset::release_reset_gpio3(p); + reset::release_reset_port3(p); +} + +/// Initialize clocks for OSTIMER0 (1 MHz source). +#[allow(dead_code)] +pub unsafe fn init_ostimer0(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_ostimer0(p); + reset::release_reset_ostimer0(p); + clocks::select_ostimer0_clock_1m(p); +} + +/// Initialize clocks and pin muxing for ADC. +#[allow(dead_code)] +pub unsafe fn init_adc(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_adc(p); + reset::release_reset_port1(p); + reset::release_reset_adc1(p); + pins::configure_adc_pins(); + clocks::select_adc_clock(p); +} diff --git a/examples/hello.rs b/examples/hello.rs new file mode 100644 index 000000000..591bf2460 --- /dev/null +++ b/examples/hello.rs @@ -0,0 +1,126 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa276 as hal; +use hal::uart; + +mod common; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +/// Simple helper to write a byte as hex to UART +fn write_hex_byte(uart: &hal::uart::Uart, byte: u8) { + const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; + uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); + uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + #[cfg(feature = "defmt")] + defmt::info!("boot"); + + // Board-level init for UART2 clocks and pins. + unsafe { + common::init_uart2(hal::pac()); + } + + // Get UART source frequency from clock configuration + // Using hardcoded frequency for now - dynamic detection may have issues + let src = 12_000_000; // FRO_LF_DIV at 12MHz with DIV=0 + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + // Print welcome message before any async delays to guarantee early console output + uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + uart.write_str_blocking("Type a command: "); + + let mut buffer = [0u8; 64]; + let mut buf_idx = 0; + + loop { + // Read a byte from UART + let byte = uart.read_byte_blocking(); + + // Echo the character back + if byte == b'\r' || byte == b'\n' { + // Enter pressed - process command + uart.write_str_blocking("\r\n"); + + if buf_idx > 0 { + let command = &buffer[0..buf_idx]; + + if command == b"help" { + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + } else if command.starts_with(b"echo ") && command.len() > 5 { + uart.write_str_blocking("Echo: "); + uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } else if command.starts_with(b"hex ") && command.len() > 4 { + // Parse the byte value + let num_str = &command[4..]; + if let Ok(num) = parse_u8(num_str) { + uart.write_str_blocking("Hex: 0x"); + write_hex_byte(&uart, num); + uart.write_str_blocking("\r\n"); + } else { + uart.write_str_blocking("Invalid number for hex command\r\n"); + } + } else if command.len() > 0 { + uart.write_str_blocking("Unknown command: "); + uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } + } + + // Reset buffer and prompt + buf_idx = 0; + uart.write_str_blocking("Type a command: "); + } else if byte == 8 || byte == 127 { + // Backspace + if buf_idx > 0 { + buf_idx -= 1; + uart.write_str_blocking("\x08 \x08"); // Erase character + } + } else if buf_idx < buffer.len() - 1 { + // Regular character + buffer[buf_idx] = byte; + buf_idx += 1; + uart.write_byte(byte); + } + } +} + +/// Simple parser for u8 from ASCII bytes +fn parse_u8(bytes: &[u8]) -> Result { + let mut result = 0u8; + for &b in bytes { + if b >= b'0' && b <= b'9' { + result = result.checked_mul(10).ok_or(())?; + result = result.checked_add(b - b'0').ok_or(())?; + } else { + return Err(()); + } + } + Ok(result) +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs new file mode 100644 index 000000000..88f256096 --- /dev/null +++ b/examples/lpuart_buffered.rs @@ -0,0 +1,88 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa276 as hal; +use embassy_mcxa276::interrupt::typelevel::Handler; +use embassy_mcxa276::lpuart; +use embassy_mcxa276::lpuart::buffered::BufferedLpuart; + +use embedded_io_async::{Read, Write}; + +use embassy_mcxa276::bind_interrupts; + +mod common; + +// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver +bind_interrupts!(struct Irqs { + LPUART2 => lpuart::buffered::BufferedInterruptHandler::; +}); + +// Wrapper function for the interrupt handler +unsafe extern "C" fn lpuart2_handler() { + lpuart::buffered::BufferedInterruptHandler::::on_interrupt(); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + let p2 = lpuart::lib::init(); + + unsafe { + hal::interrupt::install_irq_handler(mcxa276_pac::Interrupt::LPUART2, lpuart2_handler); + } + + // Configure NVIC for LPUART2 + hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); + + unsafe { + common::init_uart2(hal::pac()); + common::init_ostimer0(hal::pac()); + } + + // UART configuration (enable both TX and RX) + let config = lpuart::Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + rx_fifo_watermark: 0, + tx_fifo_watermark: 0, + ..Default::default() + }; + + let mut tx_buf = [0u8; 256]; + let mut rx_buf = [0u8; 256]; + + // Create a buffered LPUART2 instance with both TX and RX + let mut uart = BufferedLpuart::new( + p2.LPUART2, + p2.PIO2_2, // TX pin + p2.PIO2_3, // RX pin + Irqs, + &mut tx_buf, + &mut rx_buf, + config, + ) + .unwrap(); + + // Split into TX and RX parts + let (tx, rx) = uart.split_ref(); + + tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); + tx.write(b"Type characters to echo them back.\r\n") + .await + .unwrap(); + + // Echo loop + let mut buf = [0u8; 4]; + loop { + rx.read_exact(&mut buf[..]).await.unwrap(); + tx.write_all(&buf[..]).await.unwrap(); + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/lpuart_polling.rs b/examples/lpuart_polling.rs new file mode 100644 index 000000000..c83c959e8 --- /dev/null +++ b/examples/lpuart_polling.rs @@ -0,0 +1,67 @@ +#![no_std] +#![no_main] + +use crate::hal::lpuart::{lib, Config, Lpuart}; +use embassy_executor::Spawner; +use embassy_mcxa276 as hal; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +mod common; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + let p2 = lib::init(); + + #[cfg(feature = "defmt")] + defmt::info!("boot"); + + // Board-level init for UART2 clocks and pins. + unsafe { + common::init_uart2(hal::pac()); + } + + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + let lpuart = Lpuart::new_blocking( + p2.LPUART2, // Peripheral + p2.PIO2_2, // TX pin + p2.PIO2_3, // RX pin + config, + ) + .unwrap(); + + // Split into separate TX and RX parts + let (mut tx, mut rx) = lpuart.split(); + + // Write hello messages + tx.blocking_write(b"Hello world.\r\n").unwrap(); + tx.blocking_write(b"Echoing. Type characters...\r\n") + .unwrap(); + + // Echo loop + loop { + let mut buf = [0u8; 1]; + rx.blocking_read(&mut buf).unwrap(); + tx.blocking_write(&buf).unwrap(); + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs new file mode 100644 index 000000000..823e37c15 --- /dev/null +++ b/examples/ostimer_alarm.rs @@ -0,0 +1,126 @@ +#![no_std] +#![no_main] + +use core::sync::atomic::{AtomicBool, Ordering}; +use cortex_m; +use embassy_executor::Spawner; +use embassy_mcxa276 as hal; +use hal::uart; + +mod common; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use embassy_mcxa276::bind_interrupts; + +// Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +// Global flag for alarm callback +static ALARM_FLAG: AtomicBool = AtomicBool::new(false); + +// Alarm callback function +fn alarm_callback() { + ALARM_FLAG.store(true, Ordering::Release); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + common::init_ostimer0(hal::pac()); + } + unsafe { + common::init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + uart.write_str_blocking("OSTIMER Alarm Example\n"); + + // Initialize embassy-time global driver backed by OSTIMER0 + hal::ostimer::time_driver::init( + hal::config::Config::default().time_interrupt_priority, + 1_000_000, + ); + + // Create OSTIMER instance + let config = hal::ostimer::Config { + init_match_max: true, + clock_frequency_hz: 1_000_000, // 1MHz + }; + let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); + + // Create alarm with callback + let alarm = hal::ostimer::Alarm::new() + .with_callback(alarm_callback) + .with_flag(&ALARM_FLAG); + + uart.write_str_blocking("Scheduling alarm for 2 seconds...\n"); + + // Schedule alarm to expire in 2 seconds (2,000,000 microseconds) + let scheduled = ostimer.schedule_alarm_delay(&alarm, 2_000_000); + if scheduled { + uart.write_str_blocking("Alarm scheduled successfully\n"); + } else { + uart.write_str_blocking("Failed to schedule alarm (would exceed timer capacity)\n"); + return; + } + + // Wait for alarm to expire + loop { + // Check if alarm has expired + if ALARM_FLAG.load(Ordering::Acquire) { + uart.write_str_blocking("Alarm expired! Callback executed.\n"); + break; + } + + // Busy wait - don't use Timer::after_millis as it interferes with alarm MATCH + for _ in 0..100000 { + cortex_m::asm::nop(); + } + } + + // Demonstrate canceling an alarm + uart.write_str_blocking("Scheduling another alarm for 3 seconds...\n"); + ALARM_FLAG.store(false, Ordering::Release); // Reset flag + + let scheduled = ostimer.schedule_alarm_delay(&alarm, 3_000_000); + if scheduled { + uart.write_str_blocking("Alarm scheduled. Waiting 1 second then canceling...\n"); + + // Wait 1 second + embassy_time::Timer::after_millis(1000).await; + + // Cancel the alarm + ostimer.cancel_alarm(&alarm); + uart.write_str_blocking("Alarm canceled\n"); + + // Check immediately if alarm flag is set + if !ALARM_FLAG.load(Ordering::Acquire) { + uart.write_str_blocking("Alarm was successfully canceled\n"); + } else { + uart.write_str_blocking("Alarm fired despite cancellation\n"); + } + } + + uart.write_str_blocking("Example complete\n"); +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/ostimer_async.rs b/examples/ostimer_async.rs new file mode 100644 index 000000000..181ce58ef --- /dev/null +++ b/examples/ostimer_async.rs @@ -0,0 +1,76 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa276 as hal; +use hal::uart; + +mod common; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use embassy_time::{Duration, Timer}; + +use embassy_mcxa276::bind_interrupts; + +// Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed. +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + common::init_ostimer0(hal::pac()); + } + unsafe { + common::init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); + uart.write_str_blocking("boot\n"); + + // Avoid mass NVIC writes here; DefaultHandler now safely returns. + + // Initialize embassy-time global driver backed by OSTIMER0 (re-enables OS_EVENT with priority) + // The bind_interrupts! macro handles handler binding automatically + + // Initialize OSTIMER with default 1MHz frequency + // Adjust this value to match your actual OSTIMER clock frequency + hal::ostimer::time_driver::init( + hal::config::Config::default().time_interrupt_priority, + 1_000_000, + ); + + // Removed force-pend; rely on real hardware match to trigger OS_EVENT. + + // Log using defmt if enabled + #[cfg(feature = "defmt")] + defmt::info!("OSTIMER async example starting..."); + + loop { + #[cfg(feature = "defmt")] + defmt::info!("tick"); + #[cfg(not(feature = "defmt"))] + uart.write_str_blocking("tick\n"); + Timer::after(Duration::from_millis(1000)).await; + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs new file mode 100644 index 000000000..3af0f03f2 --- /dev/null +++ b/examples/ostimer_counter.rs @@ -0,0 +1,142 @@ +//! # OSTIMER Counter Reading and Reset Example +//! +//! This example demonstrates the new timer counter reading and reset functionality +//! of the OSTIMER driver. + +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::{Duration, Timer}; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use embassy_mcxa276 as hal; +use hal::bind_interrupts; + +mod common; + +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(Default::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + common::init_ostimer0(hal::pac()); + } + unsafe { + common::init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + + uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); + + // Initialize the OSTIMER time driver + hal::ostimer::time_driver::init( + hal::interrupt::Priority::from(3), + 1_000_000, // 1MHz clock + ); + + // Create OSTIMER instance + let ostimer = hal::ostimer::Ostimer::::new( + p.OSTIMER0, + hal::ostimer::Config { + init_match_max: true, + clock_frequency_hz: 1_000_000, + }, + hal::pac(), + ); + + // Read initial counter value + let initial_counter = ostimer.now(); + uart.write_str_blocking("Initial counter value: "); + write_u64(&mut uart, initial_counter); + uart.write_str_blocking("\n"); + + // Wait a bit to let counter increment + Timer::after(Duration::from_millis(100)).await; + + // Read counter again + let counter_after_wait = ostimer.now(); + uart.write_str_blocking("Counter after 100ms wait: "); + write_u64(&mut uart, counter_after_wait); + uart.write_str_blocking("\n"); + uart.write_str_blocking("Difference: "); + write_u64(&mut uart, counter_after_wait - initial_counter); + uart.write_str_blocking(" ticks\n"); + + // Reset the timer + uart.write_str_blocking("Resetting timer...\n"); + ostimer.reset(hal::pac()); + + // Read counter after reset + let counter_after_reset = ostimer.now(); + uart.write_str_blocking("Counter after reset: "); + write_u64(&mut uart, counter_after_reset); + uart.write_str_blocking("\n"); + + // Wait again to verify timer is working + Timer::after(Duration::from_millis(50)).await; + + let final_counter = ostimer.now(); + uart.write_str_blocking("Counter after another 50ms: "); + write_u64(&mut uart, final_counter); + uart.write_str_blocking("\n"); + uart.write_str_blocking("Difference after reset: "); + write_u64(&mut uart, final_counter - counter_after_reset); + uart.write_str_blocking(" ticks\n"); + + uart.write_str_blocking("Example complete\n"); +} + +// Helper function to write a u64 value as decimal string +fn write_u64(uart: &mut hal::uart::Uart, value: u64) { + if value == 0 { + uart.write_str_blocking("0"); + return; + } + + let mut buffer = [0u8; 20]; // Enough for max u64 + let mut i = 0; + let mut v = value; + + while v > 0 { + buffer[i] = b'0' + (v % 10) as u8; + v /= 10; + i += 1; + } + + // Write digits in reverse order + while i > 0 { + i -= 1; + match buffer[i] { + b'0' => uart.write_str_blocking("0"), + b'1' => uart.write_str_blocking("1"), + b'2' => uart.write_str_blocking("2"), + b'3' => uart.write_str_blocking("3"), + b'4' => uart.write_str_blocking("4"), + b'5' => uart.write_str_blocking("5"), + b'6' => uart.write_str_blocking("6"), + b'7' => uart.write_str_blocking("7"), + b'8' => uart.write_str_blocking("8"), + b'9' => uart.write_str_blocking("9"), + _ => uart.write_str_blocking("?"), + } + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs new file mode 100644 index 000000000..4470b65fd --- /dev/null +++ b/examples/ostimer_race_test.rs @@ -0,0 +1,411 @@ +//! # OSTIMER Race Condition Test +//! +//! This example tests for race conditions in the OSTIMER driver by: +//! - Scheduling alarms sequentially (hardware limitation: only one at a time) +//! - Reading the counter during interrupt-heavy periods +//! - Testing concurrent timer operations +//! - Stress testing interrupt handling + +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::{Duration, Timer}; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use core::sync::atomic::{AtomicU32, Ordering}; +use embassy_mcxa276 as hal; +use hal::bind_interrupts; + +mod common; + +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +// Global counters for race condition detection +static ALARM_CALLBACK_COUNT: AtomicU32 = AtomicU32::new(0); +static INTERRUPT_COUNT: AtomicU32 = AtomicU32::new(0); +static RACE_DETECTED: AtomicU32 = AtomicU32::new(0); + +// Alarm callback function +fn alarm_callback() { + let _count = ALARM_CALLBACK_COUNT.fetch_add(1, Ordering::SeqCst); + INTERRUPT_COUNT.fetch_add(1, Ordering::SeqCst); + + // Simulate some work in the callback to increase chance of races + for _ in 0..10 { + cortex_m::asm::nop(); + } +} + +fn report_default_handler(uart: &mut hal::uart::Uart) { + let snapshot = hal::interrupt::default_handler_snapshot(); + if snapshot.count == 0 { + return; + } + + uart.write_str_blocking("WARNING: DefaultHandler executed "); + write_u32(uart, snapshot.count); + uart.write_str_blocking(" time(s). Vector="); + write_u32(uart, snapshot.vector as u32); + uart.write_str_blocking(" CFSR=0x"); + write_hex32(uart, snapshot.cfsr); + uart.write_str_blocking(" HFSR=0x"); + write_hex32(uart, snapshot.hfsr); + uart.write_str_blocking(" PC=0x"); + write_hex32(uart, snapshot.stacked_pc); + uart.write_str_blocking(" LR=0x"); + write_hex32(uart, snapshot.stacked_lr); + uart.write_str_blocking(" SP=0x"); + write_hex32(uart, snapshot.stacked_sp); + uart.write_str_blocking("\n"); + + hal::interrupt::clear_default_handler_snapshot(); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(Default::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + common::init_ostimer0(hal::pac()); + } + unsafe { + common::init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + + uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); + + // The bind_interrupts! macro handles handler binding automatically + + // Initialize the OSTIMER time driver FIRST + hal::ostimer::time_driver::init( + hal::interrupt::Priority::from(3), + 1_000_000, // 1MHz clock + ); + + uart.write_str_blocking("Time driver initialized\n"); + + // Create OSTIMER instance + let ostimer = hal::ostimer::Ostimer::::new( + p.OSTIMER0, + hal::ostimer::Config { + init_match_max: true, + clock_frequency_hz: 1_000_000, + }, + hal::pac(), + ); + + uart.write_str_blocking("OSTIMER instance created\n"); + + // Test 1: Sequential alarm scheduling (OSTIMER only supports one alarm at a time) + uart.write_str_blocking("Test 1: Sequential alarm scheduling...\n"); + test_rapid_alarms(&ostimer, &mut uart).await; + report_default_handler(&mut uart); + + // Test 2: Counter reading during interrupts + uart.write_str_blocking("Test 2: Counter reading during interrupts...\n"); + test_counter_reading_during_interrupts(&ostimer, &mut uart).await; + report_default_handler(&mut uart); + + // Test 3: Concurrent timer operations + uart.write_str_blocking("Test 3: Concurrent timer operations...\n"); + test_concurrent_operations(&ostimer, &mut uart).await; + report_default_handler(&mut uart); + + // Test 4: Timer reset during operation + uart.write_str_blocking("Test 4: Timer reset during operation...\n"); + test_reset_during_operation(&ostimer, &mut uart, hal::pac()).await; + report_default_handler(&mut uart); + + // Report results + uart.write_str_blocking("Race condition test complete\n"); + uart.write_str_blocking("Callback count: "); + write_u32(&mut uart, ALARM_CALLBACK_COUNT.load(Ordering::SeqCst)); + uart.write_str_blocking("\nInterrupt count: "); + write_u32(&mut uart, INTERRUPT_COUNT.load(Ordering::SeqCst)); + uart.write_str_blocking("\nRaces detected: "); + write_u32(&mut uart, RACE_DETECTED.load(Ordering::SeqCst)); + uart.write_str_blocking("\n"); +} + +// Test rapid alarm scheduling to stress interrupt handling +async fn test_rapid_alarms( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, +) { + let initial_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); + + // Schedule 10 alarms sequentially (OSTIMER only supports one alarm at a time) + for _i in 0..10 { + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + let delay_us = 1000; // 1ms delay for each alarm + if ostimer.schedule_alarm_delay(&alarm, delay_us) { + // Wait for this alarm to complete before scheduling the next + Timer::after(Duration::from_micros(delay_us + 100)).await; + report_default_handler(uart); + } else { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm (match not ready)\n"); + } + } + + // All alarms should have completed by now + let final_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); + let expected_count = initial_count + 10; + + if final_count != expected_count { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Expected "); + write_u32(uart, expected_count); + uart.write_str_blocking(" callbacks, got "); + write_u32(uart, final_count); + uart.write_str_blocking("\n"); + } else { + uart.write_str_blocking("PASS: All rapid alarms executed\n"); + } +} + +// Test reading counter while interrupts are firing +async fn test_counter_reading_during_interrupts( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, +) { + let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + // Schedule an alarm that will fire soon + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + if !ostimer.schedule_alarm_delay(&alarm, 500) { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before counter stress\n"); + } + + // While alarm is pending, read the counter many times rapidly + // This tests if counter reading is atomic and doesn't get corrupted by interrupts + let mut last_counter = ostimer.now(); + let mut consistent_reads = 0; + let mut total_reads = 0; + + for _ in 0..1000 { + let current_counter = ostimer.now(); + total_reads += 1; + + // Check if counter is monotonically increasing (basic sanity check) + if current_counter >= last_counter { + consistent_reads += 1; + } + last_counter = current_counter; + + // Small delay between reads + for _ in 0..10 { + cortex_m::asm::nop(); + } + + report_default_handler(uart); + } + + // Wait for alarm to complete + Timer::after(Duration::from_millis(1)).await; + + let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + if consistent_reads == total_reads { + uart.write_str_blocking("PASS: Counter reading consistent during interrupts\n"); + } else { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Counter reading inconsistent: "); + write_u32(uart, consistent_reads); + uart.write_str_blocking("/"); + write_u32(uart, total_reads); + uart.write_str_blocking(" consistent\n"); + } + + if final_interrupt_count > initial_interrupt_count { + uart.write_str_blocking("PASS: Interrupt fired during counter reading test\n"); + } else { + uart.write_str_blocking("WARNING: No interrupt fired during counter reading test\n"); + } +} + +// Test concurrent timer operations (embassy-time + alarms) +async fn test_concurrent_operations( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, +) { + let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + // Start an embassy-time timer + let timer_future = Timer::after(Duration::from_millis(2)); + + // Schedule an alarm that should fire before the timer + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + if !ostimer.schedule_alarm_delay(&alarm, 1000) { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking( + "ERROR: Failed to program OSTIMER alarm before concurrent operations\n", + ); + } + + // Wait for both to complete + timer_future.await; + + let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + if final_interrupt_count > initial_interrupt_count { + uart.write_str_blocking("PASS: Concurrent operations completed\n"); + } else { + uart.write_str_blocking("WARNING: No interrupts during concurrent operations\n"); + } +} + +// Test timer reset during active operations +async fn test_reset_during_operation( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, + peripherals: &hal::pac::Peripherals, +) { + let initial_counter = ostimer.now(); + + // Schedule an alarm + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + if !ostimer.schedule_alarm_delay(&alarm, 2000) { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before reset test\n"); + } + + // Wait a bit then reset the timer + Timer::after(Duration::from_millis(1)).await; + ostimer.reset(peripherals); + + // Check counter after reset + let counter_after_reset = ostimer.now(); + + // Wait to see if the alarm still fires (it shouldn't after reset) + Timer::after(Duration::from_millis(2)).await; + + let final_counter = ostimer.now(); + + if counter_after_reset < initial_counter { + uart.write_str_blocking("PASS: Timer reset successful\n"); + } else { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Timer reset may have failed\n"); + } + + uart.write_str_blocking("Counter progression after reset: "); + write_u64(uart, initial_counter); + uart.write_str_blocking(" -> "); + write_u64(uart, counter_after_reset); + uart.write_str_blocking(" -> "); + write_u64(uart, final_counter); + uart.write_str_blocking("\n"); +} + +// Helper function to write a u32 value as decimal string +fn write_u32(uart: &mut hal::uart::Uart, value: u32) { + if value == 0 { + uart.write_str_blocking("0"); + return; + } + + let mut buffer = [0u8; 10]; // Enough for max u32 + let mut i = 0; + let mut v = value; + + while v > 0 { + buffer[i] = b'0' + (v % 10) as u8; + v /= 10; + i += 1; + } + + // Write digits in reverse order + while i > 0 { + i -= 1; + match buffer[i] { + b'0' => uart.write_str_blocking("0"), + b'1' => uart.write_str_blocking("1"), + b'2' => uart.write_str_blocking("2"), + b'3' => uart.write_str_blocking("3"), + b'4' => uart.write_str_blocking("4"), + b'5' => uart.write_str_blocking("5"), + b'6' => uart.write_str_blocking("6"), + b'7' => uart.write_str_blocking("7"), + b'8' => uart.write_str_blocking("8"), + b'9' => uart.write_str_blocking("9"), + _ => uart.write_str_blocking("?"), + } + } +} + +fn write_hex32(uart: &mut hal::uart::Uart, value: u32) { + let mut buf = [b'0'; 8]; + let mut tmp = value; + for i in (0..8).rev() { + let digit = (tmp & 0xF) as u8; + buf[i] = match digit { + 0..=9 => b'0' + digit, + 10..=15 => b'A' + (digit - 10), + _ => b'?', + }; + tmp >>= 4; + } + for b in &buf { + uart.write_byte(*b); + } +} + +// Helper function to write a u64 value as decimal string +fn write_u64(uart: &mut hal::uart::Uart, value: u64) { + if value == 0 { + uart.write_str_blocking("0"); + return; + } + + let mut buffer = [0u8; 20]; // Enough for max u64 + let mut i = 0; + let mut v = value; + + while v > 0 { + buffer[i] = b'0' + (v % 10) as u8; + v /= 10; + i += 1; + } + + // Write digits in reverse order + while i > 0 { + i -= 1; + match buffer[i] { + b'0' => uart.write_str_blocking("0"), + b'1' => uart.write_str_blocking("1"), + b'2' => uart.write_str_blocking("2"), + b'3' => uart.write_str_blocking("3"), + b'4' => uart.write_str_blocking("4"), + b'5' => uart.write_str_blocking("5"), + b'6' => uart.write_str_blocking("6"), + b'7' => uart.write_str_blocking("7"), + b'8' => uart.write_str_blocking("8"), + b'9' => uart.write_str_blocking("9"), + _ => uart.write_str_blocking("?"), + } + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs new file mode 100644 index 000000000..8f4ff1623 --- /dev/null +++ b/examples/rtc_alarm.rs @@ -0,0 +1,105 @@ +#![no_std] +#![no_main] + + +use embassy_mcxa276 as hal; +use cortex_m; +use embassy_executor::Spawner; +use hal::rtc::{RtcDateTime, RtcInterruptEnable}; +use hal::uart; +use hal::InterruptExt; + +mod common; + +type MyRtc = hal::rtc::Rtc; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use embassy_mcxa276::bind_interrupts; +bind_interrupts!(struct Irqs { + RTC => hal::rtc::RtcHandler; +}); + +#[used] +#[no_mangle] +static KEEP_RTC: unsafe extern "C" fn() = RTC; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + + let p = hal::init(hal::config::Config::default()); + + unsafe { + common::init_uart2(hal::pac()); + } + + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + uart.write_str_blocking("\r\n=== RTC Alarm Example ===\r\n"); + + unsafe { hal::clocks::init_fro16k(hal::pac()) }; + + let rtc_config = hal::rtc::get_default_config(); + + let rtc = MyRtc::new(p.RTC0, rtc_config); + + let now = RtcDateTime { + year: 2025, + month: 10, + day: 15, + hour: 14, + minute: 30, + second: 0, + }; + + + rtc.stop(); + + uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n"); + rtc.set_datetime(now); + + let mut alarm = now; + alarm.second += 10; + + rtc.set_alarm(alarm); + uart.write_str_blocking("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)\r\n"); + + rtc.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); + + unsafe { + hal::interrupt::RTC.enable(); + } + + unsafe { + cortex_m::interrupt::enable(); + } + + rtc.start(); + + uart.write_str_blocking("RTC started, waiting for alarm...\r\n"); + + loop { + if rtc.is_alarm_triggered() { + uart.write_str_blocking("\r\n*** ALARM TRIGGERED! ***\r\n"); + break; + } + } + + uart.write_str_blocking("Example complete - Test PASSED!\r\n"); + + loop { + + } +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs new file mode 100644 index 000000000..b309ce973 --- /dev/null +++ b/examples/uart_interrupt.rs @@ -0,0 +1,86 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa276 as hal; +use hal::interrupt::typelevel::Handler; +use hal::uart; + +mod common; + +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use defmt_rtt as _; +#[cfg(feature = "defmt")] +use panic_probe as _; +#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] +use rtt_target as _; + +use embassy_mcxa276::bind_interrupts; + +// Bind LPUART2 interrupt to our handler +bind_interrupts!(struct Irqs { + LPUART2 => hal::uart::UartInterruptHandler; +}); + +#[used] +#[no_mangle] +static KEEP_LPUART2: unsafe extern "C" fn() = LPUART2; + +// Wrapper function for the interrupt handler +unsafe extern "C" fn lpuart2_handler() { + hal::uart::UartInterruptHandler::on_interrupt(); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + + // Enable/clock UART2 before touching its registers + unsafe { + common::init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); + + // Configure LPUART2 interrupt for UART operation BEFORE any UART usage + hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3)); + + // Manually install the interrupt handler + unsafe { + hal::interrupt::LPUART2.install_handler(lpuart2_handler); + } + + // Print welcome message + uart.write_str_blocking("UART interrupt echo demo starting...\r\n"); + uart.write_str_blocking("Type characters to echo them back.\r\n"); + + // Log using defmt if enabled + #[cfg(feature = "defmt")] + defmt::info!("UART interrupt echo demo starting..."); + + loop { + // Check if we have received any data + if uart.rx_data_available() { + if let Some(byte) = uart.try_read_byte() { + // Echo it back + uart.write_byte(byte); + uart.write_str_blocking(" (received)\r\n"); + } + } else { + // No data available, wait a bit before checking again + cortex_m::asm::delay(12_000_000); // ~1 second at 12MHz + } + } +} + +#[cfg(feature = "defmt")] +#[export_name = "_defmt_timestamp"] +fn defmt_timestamp(_fmt: defmt::Formatter<'_>) { + // Return empty timestamp for now +} + +#[cfg(not(feature = "defmt"))] +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop {} +} diff --git a/mcxa276-pac/Cargo.toml b/mcxa276-pac/Cargo.toml new file mode 100644 index 000000000..7060ceaab --- /dev/null +++ b/mcxa276-pac/Cargo.toml @@ -0,0 +1,17 @@ +[package] +name = "mcxa276-pac" +version = "0.1.0" +edition = "2021" +license = "MIT OR Apache-2.0" + +[lib] +path = "src/lib.rs" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[features] +default = [] +rt = ["cortex-m/inline-asm"] +critical-section = [] diff --git a/mcxa276-pac/build.rs b/mcxa276-pac/build.rs new file mode 100644 index 000000000..d0781acdb --- /dev/null +++ b/mcxa276-pac/build.rs @@ -0,0 +1,17 @@ +#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/mcxa276-pac/device.x b/mcxa276-pac/device.x new file mode 100644 index 000000000..5f61e8ec0 --- /dev/null +++ b/mcxa276-pac/device.x @@ -0,0 +1,129 @@ +/* Ensure the OS_EVENT ISR symbol is retained by the linker, even if not + * referenced from Rust code due to LTO/GC. This matches how the C SDK keeps + * ISR symbols alive via the vector table. + */ +EXTERN(OS_EVENT); + + +PROVIDE(Reserved16 = DefaultHandler); +PROVIDE(CMC = DefaultHandler); +PROVIDE(DMA_CH0 = DefaultHandler); +PROVIDE(DMA_CH1 = DefaultHandler); +PROVIDE(DMA_CH2 = DefaultHandler); +PROVIDE(DMA_CH3 = DefaultHandler); +PROVIDE(DMA_CH4 = DefaultHandler); +PROVIDE(DMA_CH5 = DefaultHandler); +PROVIDE(DMA_CH6 = DefaultHandler); +PROVIDE(DMA_CH7 = DefaultHandler); +PROVIDE(ERM0_SINGLE_BIT = DefaultHandler); +PROVIDE(ERM0_MULTI_BIT = DefaultHandler); +PROVIDE(FMU0 = DefaultHandler); +PROVIDE(GLIKEY0 = DefaultHandler); +PROVIDE(MBC0 = DefaultHandler); +PROVIDE(SCG0 = DefaultHandler); +PROVIDE(SPC0 = DefaultHandler); +PROVIDE(TDET = DefaultHandler); +PROVIDE(WUU0 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(RESERVED21 = DefaultHandler); +PROVIDE(RESERVED22 = DefaultHandler); +PROVIDE(FLEXIO = DefaultHandler); +PROVIDE(I3C0 = DefaultHandler); +PROVIDE(RESERVED25 = DefaultHandler); +PROVIDE(LPI2C0 = DefaultHandler); +PROVIDE(LPI2C1 = DefaultHandler); +PROVIDE(LPSPI0 = DefaultHandler); +PROVIDE(LPSPI1 = DefaultHandler); +PROVIDE(RESERVED30 = DefaultHandler); +PROVIDE(LPUART0 = DefaultHandler); +PROVIDE(LPUART1 = DefaultHandler); +PROVIDE(LPUART2 = DefaultHandler); +PROVIDE(LPUART3 = DefaultHandler); +PROVIDE(LPUART4 = DefaultHandler); +PROVIDE(USB0 = DefaultHandler); +PROVIDE(RESERVED37 = DefaultHandler); +PROVIDE(CDOG0 = DefaultHandler); +PROVIDE(CTIMER0 = DefaultHandler); +PROVIDE(CTIMER1 = DefaultHandler); +PROVIDE(CTIMER2 = DefaultHandler); +PROVIDE(CTIMER3 = DefaultHandler); +PROVIDE(CTIMER4 = DefaultHandler); +PROVIDE(FLEXPWM0_RELOAD_ERROR = DefaultHandler); +PROVIDE(FLEXPWM0_FAULT = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE0 = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE1 = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE2 = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE3 = DefaultHandler); +PROVIDE(EQDC0_COMPARE = DefaultHandler); +PROVIDE(EQDC0_HOME = DefaultHandler); +PROVIDE(EQDC0_WATCHDOG = DefaultHandler); +PROVIDE(EQDC0_INDEX = DefaultHandler); +PROVIDE(FREQME0 = DefaultHandler); +PROVIDE(LPTMR0 = DefaultHandler); +PROVIDE(RESERVED56 = DefaultHandler); +PROVIDE(OS_EVENT = DefaultHandler); /* IRQ 57 */ +PROVIDE(WAKETIMER0 = DefaultHandler); +PROVIDE(UTICK0 = DefaultHandler); +PROVIDE(WWDT0 = DefaultHandler); +PROVIDE(RESERVED61 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(ADC1 = DefaultHandler); +PROVIDE(CMP0 = DefaultHandler); +PROVIDE(CMP1 = DefaultHandler); +PROVIDE(CMP2 = DefaultHandler); +PROVIDE(DAC0 = DefaultHandler); +PROVIDE(RESERVED68 = DefaultHandler); +PROVIDE(RESERVED69 = DefaultHandler); +PROVIDE(RESERVED70 = DefaultHandler); +PROVIDE(GPIO0 = DefaultHandler); +PROVIDE(GPIO1 = DefaultHandler); +PROVIDE(GPIO2 = DefaultHandler); +PROVIDE(GPIO3 = DefaultHandler); +PROVIDE(GPIO4 = DefaultHandler); +PROVIDE(RESERVED76 = DefaultHandler); +PROVIDE(LPI2C2 = DefaultHandler); +PROVIDE(LPI2C3 = DefaultHandler); +PROVIDE(FLEXPWM1_RELOAD_ERROR = DefaultHandler); +PROVIDE(FLEXPWM1_FAULT = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE0 = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE1 = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE2 = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE3 = DefaultHandler); +PROVIDE(EQDC1_COMPARE = DefaultHandler); +PROVIDE(EQDC1_HOME = DefaultHandler); +PROVIDE(EQDC1_WATCHDOG = DefaultHandler); +PROVIDE(EQDC1_INDEX = DefaultHandler); +PROVIDE(RESERVED89 = DefaultHandler); +PROVIDE(RESERVED90 = DefaultHandler); +PROVIDE(RESERVED91 = DefaultHandler); +PROVIDE(RESERVED92 = DefaultHandler); +PROVIDE(RESERVED93 = DefaultHandler); +PROVIDE(RESERVED94 = DefaultHandler); +PROVIDE(LPUART5 = DefaultHandler); +PROVIDE(RESERVED96 = DefaultHandler); +PROVIDE(RESERVED97 = DefaultHandler); +PROVIDE(RESERVED98 = DefaultHandler); +PROVIDE(RESERVED99 = DefaultHandler); +PROVIDE(RESERVED100 = DefaultHandler); +PROVIDE(RESERVED101 = DefaultHandler); +PROVIDE(RESERVED102 = DefaultHandler); +PROVIDE(RESERVED103 = DefaultHandler); +PROVIDE(RESERVED104 = DefaultHandler); +PROVIDE(RESERVED105 = DefaultHandler); +PROVIDE(RESERVED106 = DefaultHandler); +PROVIDE(MAU = DefaultHandler); +PROVIDE(SMARTDMA = DefaultHandler); +PROVIDE(CDOG1 = DefaultHandler); +PROVIDE(PKC = DefaultHandler); +PROVIDE(SGI = DefaultHandler); +PROVIDE(RESERVED112 = DefaultHandler); +PROVIDE(TRNG0 = DefaultHandler); +PROVIDE(SECURE_ERR = DefaultHandler); +PROVIDE(RESERVED115 = DefaultHandler); +PROVIDE(ADC2 = DefaultHandler); +PROVIDE(ADC3 = DefaultHandler); +PROVIDE(RESERVED118 = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(RTC_1HZ = DefaultHandler); +PROVIDE(SLCD = DefaultHandler); diff --git a/mcxa276-pac/device.x.backup b/mcxa276-pac/device.x.backup new file mode 100644 index 000000000..e1e189cf7 --- /dev/null +++ b/mcxa276-pac/device.x.backup @@ -0,0 +1,105 @@ +/* Ensure the OS_EVENT ISR symbol is retained by the linker, even if not + * referenced from Rust code due to LTO/GC. This matches how the C SDK keeps + * ISR symbols alive via the vector table. + */ +EXTERN(OS_EVENT); + + +PROVIDE(Reserved16 = DefaultHandler); +PROVIDE(CMC = DefaultHandler); +PROVIDE(DMA_CH0 = DefaultHandler); +PROVIDE(DMA_CH1 = DefaultHandler); +PROVIDE(DMA_CH2 = DefaultHandler); +PROVIDE(DMA_CH3 = DefaultHandler); +PROVIDE(DMA_CH4 = DefaultHandler); +PROVIDE(DMA_CH5 = DefaultHandler); +PROVIDE(DMA_CH6 = DefaultHandler); +PROVIDE(DMA_CH7 = DefaultHandler); +PROVIDE(ERM0_SINGLE_BIT = DefaultHandler); +PROVIDE(ERM0_MULTI_BIT = DefaultHandler); +PROVIDE(FMU0 = DefaultHandler); +PROVIDE(GLIKEY0 = DefaultHandler); +PROVIDE(MBC0 = DefaultHandler); +PROVIDE(SCG0 = DefaultHandler); +PROVIDE(SPC0 = DefaultHandler); +PROVIDE(TDET = DefaultHandler); +PROVIDE(WUU0 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(RESERVED21 = DefaultHandler); /* IRQ 21 - reserved */ +PROVIDE(RESERVED22 = DefaultHandler); /* IRQ 22 - reserved */ +PROVIDE(FLEXIO = DefaultHandler); +PROVIDE(I3C0 = DefaultHandler); +PROVIDE(RESERVED25 = DefaultHandler); /* IRQ 25 - reserved */ +PROVIDE(LPI2C0 = DefaultHandler); +PROVIDE(LPI2C1 = DefaultHandler); +PROVIDE(LPSPI0 = DefaultHandler); +PROVIDE(LPSPI1 = DefaultHandler); +PROVIDE(RESERVED30 = DefaultHandler); /* IRQ 30 - reserved */ +PROVIDE(LPUART0 = DefaultHandler); +PROVIDE(LPUART1 = DefaultHandler); +PROVIDE(LPUART2 = DefaultHandler); +PROVIDE(LPUART3 = DefaultHandler); +PROVIDE(LPUART4 = DefaultHandler); +PROVIDE(USB0 = DefaultHandler); +PROVIDE(RESERVED37 = DefaultHandler); /* IRQ 37 - reserved */ +PROVIDE(CDOG0 = DefaultHandler); +PROVIDE(CTIMER0 = DefaultHandler); +PROVIDE(CTIMER1 = DefaultHandler); +PROVIDE(CTIMER2 = DefaultHandler); +PROVIDE(CTIMER3 = DefaultHandler); +PROVIDE(CTIMER4 = DefaultHandler); +PROVIDE(FLEXPWM0_RELOAD_ERROR = DefaultHandler); +PROVIDE(FLEXPWM0_FAULT = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE0 = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE1 = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE2 = DefaultHandler); +PROVIDE(FLEXPWM0_SUBMODULE3 = DefaultHandler); +PROVIDE(EQDC0_COMPARE = DefaultHandler); +PROVIDE(EQDC0_HOME = DefaultHandler); +PROVIDE(EQDC0_WATCHDOG = DefaultHandler); +PROVIDE(EQDC0_INDEX = DefaultHandler); +PROVIDE(FREQME0 = DefaultHandler); +PROVIDE(LPTMR0 = DefaultHandler); +PROVIDE(RESERVED56 = DefaultHandler); /* IRQ 56 - reserved */ +PROVIDE(OS_EVENT = DefaultHandler); /* IRQ 57 */ +PROVIDE(WAKETIMER0 = DefaultHandler); +PROVIDE(UTICK0 = DefaultHandler); +PROVIDE(WWDT0 = DefaultHandler); +PROVIDE(RESERVED61 = DefaultHandler); /* IRQ 61 - reserved */ +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(ADC1 = DefaultHandler); +PROVIDE(CMP0 = DefaultHandler); +PROVIDE(CMP1 = DefaultHandler); +PROVIDE(CMP2 = DefaultHandler); +PROVIDE(DAC0 = DefaultHandler); +PROVIDE(GPIO0 = DefaultHandler); +PROVIDE(GPIO1 = DefaultHandler); +PROVIDE(GPIO2 = DefaultHandler); +PROVIDE(GPIO3 = DefaultHandler); +PROVIDE(GPIO4 = DefaultHandler); +PROVIDE(LPI2C2 = DefaultHandler); +PROVIDE(LPI2C3 = DefaultHandler); +PROVIDE(FLEXPWM1_RELOAD_ERROR = DefaultHandler); +PROVIDE(FLEXPWM1_FAULT = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE0 = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE1 = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE2 = DefaultHandler); +PROVIDE(FLEXPWM1_SUBMODULE3 = DefaultHandler); +PROVIDE(EQDC1_COMPARE = DefaultHandler); +PROVIDE(EQDC1_HOME = DefaultHandler); +PROVIDE(EQDC1_WATCHDOG = DefaultHandler); +PROVIDE(EQDC1_INDEX = DefaultHandler); +PROVIDE(LPUART5 = DefaultHandler); +PROVIDE(MAU = DefaultHandler); +PROVIDE(SMARTDMA = DefaultHandler); +PROVIDE(CDOG1 = DefaultHandler); +PROVIDE(PKC = DefaultHandler); +PROVIDE(SGI = DefaultHandler); +PROVIDE(TRNG0 = DefaultHandler); +PROVIDE(ADC2 = DefaultHandler); +PROVIDE(ADC3 = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(RTC_1HZ = DefaultHandler); +PROVIDE(SLCD = DefaultHandler); + diff --git a/mcxa276-pac/src/adc0.rs b/mcxa276-pac/src/adc0.rs new file mode 100644 index 000000000..7daa8401f --- /dev/null +++ b/mcxa276-pac/src/adc0.rs @@ -0,0 +1,448 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + _reserved2: [u8; 0x08], + ctrl: Ctrl, + stat: Stat, + ie: Ie, + de: De, + cfg: Cfg, + pause: Pause, + _reserved8: [u8; 0x0c], + swtrig: Swtrig, + tstat: Tstat, + _reserved10: [u8; 0x04], + ofstrim: Ofstrim, + _reserved11: [u8; 0x04], + hstrim: Hstrim, + _reserved12: [u8; 0x54], + tctrl: [Tctrl; 4], + _reserved13: [u8; 0x30], + fctrl0: Fctrl0, + _reserved14: [u8; 0x0c], + gcc0: Gcc0, + _reserved15: [u8; 0x04], + gcr0: Gcr0, + _reserved16: [u8; 0x04], + cmdl1: Cmdl1, + cmdh1: Cmdh1, + cmdl2: Cmdl2, + cmdh2: Cmdh2, + cmdl3: Cmdl3, + cmdh3: Cmdh3, + cmdl4: Cmdl4, + cmdh4: Cmdh4, + cmdl5: Cmdl5, + cmdh5: Cmdh5, + cmdl6: Cmdl6, + cmdh6: Cmdh6, + cmdl7: Cmdl7, + cmdh7: Cmdh7, + _reserved30: [u8; 0xc8], + cv: [Cv; 7], + _reserved31: [u8; 0xe4], + resfifo0: Resfifo0, + _reserved32: [u8; 0xfc], + cal_gar: [CalGar; 34], + _reserved33: [u8; 0x0b70], + cfg2: Cfg2, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID Register"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter Register"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x10 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x14 - Status Register"] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } + #[doc = "0x18 - Interrupt Enable Register"] + #[inline(always)] + pub const fn ie(&self) -> &Ie { + &self.ie + } + #[doc = "0x1c - DMA Enable Register"] + #[inline(always)] + pub const fn de(&self) -> &De { + &self.de + } + #[doc = "0x20 - Configuration Register"] + #[inline(always)] + pub const fn cfg(&self) -> &Cfg { + &self.cfg + } + #[doc = "0x24 - Pause Register"] + #[inline(always)] + pub const fn pause(&self) -> &Pause { + &self.pause + } + #[doc = "0x34 - Software Trigger Register"] + #[inline(always)] + pub const fn swtrig(&self) -> &Swtrig { + &self.swtrig + } + #[doc = "0x38 - Trigger Status Register"] + #[inline(always)] + pub const fn tstat(&self) -> &Tstat { + &self.tstat + } + #[doc = "0x40 - Offset Trim Register"] + #[inline(always)] + pub const fn ofstrim(&self) -> &Ofstrim { + &self.ofstrim + } + #[doc = "0x48 - High Speed Trim Register"] + #[inline(always)] + pub const fn hstrim(&self) -> &Hstrim { + &self.hstrim + } + #[doc = "0xa0..0xb0 - Trigger Control Register"] + #[inline(always)] + pub const fn tctrl(&self, n: usize) -> &Tctrl { + &self.tctrl[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xa0..0xb0 - Trigger Control Register"] + #[inline(always)] + pub fn tctrl_iter(&self) -> impl Iterator { + self.tctrl.iter() + } + #[doc = "0xe0 - FIFO Control Register"] + #[inline(always)] + pub const fn fctrl0(&self) -> &Fctrl0 { + &self.fctrl0 + } + #[doc = "0xf0 - Gain Calibration Control"] + #[inline(always)] + pub const fn gcc0(&self) -> &Gcc0 { + &self.gcc0 + } + #[doc = "0xf8 - Gain Calculation Result"] + #[inline(always)] + pub const fn gcr0(&self) -> &Gcr0 { + &self.gcr0 + } + #[doc = "0x100 - Command Low Buffer Register"] + #[inline(always)] + pub const fn cmdl1(&self) -> &Cmdl1 { + &self.cmdl1 + } + #[doc = "0x104 - Command High Buffer Register"] + #[inline(always)] + pub const fn cmdh1(&self) -> &Cmdh1 { + &self.cmdh1 + } + #[doc = "0x108 - Command Low Buffer Register"] + #[inline(always)] + pub const fn cmdl2(&self) -> &Cmdl2 { + &self.cmdl2 + } + #[doc = "0x10c - Command High Buffer Register"] + #[inline(always)] + pub const fn cmdh2(&self) -> &Cmdh2 { + &self.cmdh2 + } + #[doc = "0x110 - Command Low Buffer Register"] + #[inline(always)] + pub const fn cmdl3(&self) -> &Cmdl3 { + &self.cmdl3 + } + #[doc = "0x114 - Command High Buffer Register"] + #[inline(always)] + pub const fn cmdh3(&self) -> &Cmdh3 { + &self.cmdh3 + } + #[doc = "0x118 - Command Low Buffer Register"] + #[inline(always)] + pub const fn cmdl4(&self) -> &Cmdl4 { + &self.cmdl4 + } + #[doc = "0x11c - Command High Buffer Register"] + #[inline(always)] + pub const fn cmdh4(&self) -> &Cmdh4 { + &self.cmdh4 + } + #[doc = "0x120 - Command Low Buffer Register"] + #[inline(always)] + pub const fn cmdl5(&self) -> &Cmdl5 { + &self.cmdl5 + } + #[doc = "0x124 - Command High Buffer Register"] + #[inline(always)] + pub const fn cmdh5(&self) -> &Cmdh5 { + &self.cmdh5 + } + #[doc = "0x128 - Command Low Buffer Register"] + #[inline(always)] + pub const fn cmdl6(&self) -> &Cmdl6 { + &self.cmdl6 + } + #[doc = "0x12c - Command High Buffer Register"] + #[inline(always)] + pub const fn cmdh6(&self) -> &Cmdh6 { + &self.cmdh6 + } + #[doc = "0x130 - Command Low Buffer Register"] + #[inline(always)] + pub const fn cmdl7(&self) -> &Cmdl7 { + &self.cmdl7 + } + #[doc = "0x134 - Command High Buffer Register"] + #[inline(always)] + pub const fn cmdh7(&self) -> &Cmdh7 { + &self.cmdh7 + } + #[doc = "0x200..0x21c - Compare Value Register"] + #[doc = ""] + #[doc = "
`n` is the index of register in the array. `n == 0` corresponds to `CV1` register.
"] + #[inline(always)] + pub const fn cv(&self, n: usize) -> &Cv { + &self.cv[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x200..0x21c - Compare Value Register"] + #[inline(always)] + pub fn cv_iter(&self) -> impl Iterator { + self.cv.iter() + } + #[doc = "0x200 - Compare Value Register"] + #[inline(always)] + pub const fn cv1(&self) -> &Cv { + self.cv(0) + } + #[doc = "0x204 - Compare Value Register"] + #[inline(always)] + pub const fn cv2(&self) -> &Cv { + self.cv(1) + } + #[doc = "0x208 - Compare Value Register"] + #[inline(always)] + pub const fn cv3(&self) -> &Cv { + self.cv(2) + } + #[doc = "0x20c - Compare Value Register"] + #[inline(always)] + pub const fn cv4(&self) -> &Cv { + self.cv(3) + } + #[doc = "0x210 - Compare Value Register"] + #[inline(always)] + pub const fn cv5(&self) -> &Cv { + self.cv(4) + } + #[doc = "0x214 - Compare Value Register"] + #[inline(always)] + pub const fn cv6(&self) -> &Cv { + self.cv(5) + } + #[doc = "0x218 - Compare Value Register"] + #[inline(always)] + pub const fn cv7(&self) -> &Cv { + self.cv(6) + } + #[doc = "0x300 - Data Result FIFO Register"] + #[inline(always)] + pub const fn resfifo0(&self) -> &Resfifo0 { + &self.resfifo0 + } + #[doc = "0x400..0x488 - Calibration General A-Side Registers"] + #[inline(always)] + pub const fn cal_gar(&self, n: usize) -> &CalGar { + &self.cal_gar[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x400..0x488 - Calibration General A-Side Registers"] + #[inline(always)] + pub fn cal_gar_iter(&self) -> impl Iterator { + self.cal_gar.iter() + } + #[doc = "0xff8 - Configuration 2 Register"] + #[inline(always)] + pub const fn cfg2(&self) -> &Cfg2 { + &self.cfg2 + } +} +#[doc = "VERID (r) register accessor: Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID Register"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter Register"] +pub mod param; +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "STAT (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "Status Register"] +pub mod stat; +#[doc = "IE (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`] module"] +#[doc(alias = "IE")] +pub type Ie = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod ie; +#[doc = "DE (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@de`] module"] +#[doc(alias = "DE")] +pub type De = crate::Reg; +#[doc = "DMA Enable Register"] +pub mod de; +#[doc = "CFG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`] module"] +#[doc(alias = "CFG")] +pub type Cfg = crate::Reg; +#[doc = "Configuration Register"] +pub mod cfg; +#[doc = "PAUSE (rw) register accessor: Pause Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pause::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pause`] module"] +#[doc(alias = "PAUSE")] +pub type Pause = crate::Reg; +#[doc = "Pause Register"] +pub mod pause; +#[doc = "SWTRIG (rw) register accessor: Software Trigger Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swtrig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swtrig`] module"] +#[doc(alias = "SWTRIG")] +pub type Swtrig = crate::Reg; +#[doc = "Software Trigger Register"] +pub mod swtrig; +#[doc = "TSTAT (rw) register accessor: Trigger Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstat`] module"] +#[doc(alias = "TSTAT")] +pub type Tstat = crate::Reg; +#[doc = "Trigger Status Register"] +pub mod tstat; +#[doc = "OFSTRIM (rw) register accessor: Offset Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ofstrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ofstrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ofstrim`] module"] +#[doc(alias = "OFSTRIM")] +pub type Ofstrim = crate::Reg; +#[doc = "Offset Trim Register"] +pub mod ofstrim; +#[doc = "HSTRIM (rw) register accessor: High Speed Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hstrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hstrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hstrim`] module"] +#[doc(alias = "HSTRIM")] +pub type Hstrim = crate::Reg; +#[doc = "High Speed Trim Register"] +pub mod hstrim; +#[doc = "TCTRL (rw) register accessor: Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tctrl`] module"] +#[doc(alias = "TCTRL")] +pub type Tctrl = crate::Reg; +#[doc = "Trigger Control Register"] +pub mod tctrl; +#[doc = "FCTRL0 (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl0`] module"] +#[doc(alias = "FCTRL0")] +pub type Fctrl0 = crate::Reg; +#[doc = "FIFO Control Register"] +pub mod fctrl0; +#[doc = "GCC0 (r) register accessor: Gain Calibration Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcc0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcc0`] module"] +#[doc(alias = "GCC0")] +pub type Gcc0 = crate::Reg; +#[doc = "Gain Calibration Control"] +pub mod gcc0; +#[doc = "GCR0 (rw) register accessor: Gain Calculation Result\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr0`] module"] +#[doc(alias = "GCR0")] +pub type Gcr0 = crate::Reg; +#[doc = "Gain Calculation Result"] +pub mod gcr0; +#[doc = "CMDL1 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl1`] module"] +#[doc(alias = "CMDL1")] +pub type Cmdl1 = crate::Reg; +#[doc = "Command Low Buffer Register"] +pub mod cmdl1; +#[doc = "CMDH1 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh1`] module"] +#[doc(alias = "CMDH1")] +pub type Cmdh1 = crate::Reg; +#[doc = "Command High Buffer Register"] +pub mod cmdh1; +#[doc = "CMDL2 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl2`] module"] +#[doc(alias = "CMDL2")] +pub type Cmdl2 = crate::Reg; +#[doc = "Command Low Buffer Register"] +pub mod cmdl2; +#[doc = "CMDH2 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh2`] module"] +#[doc(alias = "CMDH2")] +pub type Cmdh2 = crate::Reg; +#[doc = "Command High Buffer Register"] +pub mod cmdh2; +#[doc = "CMDL3 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl3`] module"] +#[doc(alias = "CMDL3")] +pub type Cmdl3 = crate::Reg; +#[doc = "Command Low Buffer Register"] +pub mod cmdl3; +#[doc = "CMDH3 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh3`] module"] +#[doc(alias = "CMDH3")] +pub type Cmdh3 = crate::Reg; +#[doc = "Command High Buffer Register"] +pub mod cmdh3; +#[doc = "CMDL4 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl4`] module"] +#[doc(alias = "CMDL4")] +pub type Cmdl4 = crate::Reg; +#[doc = "Command Low Buffer Register"] +pub mod cmdl4; +#[doc = "CMDH4 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh4`] module"] +#[doc(alias = "CMDH4")] +pub type Cmdh4 = crate::Reg; +#[doc = "Command High Buffer Register"] +pub mod cmdh4; +#[doc = "CMDL5 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl5`] module"] +#[doc(alias = "CMDL5")] +pub type Cmdl5 = crate::Reg; +#[doc = "Command Low Buffer Register"] +pub mod cmdl5; +#[doc = "CMDH5 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh5`] module"] +#[doc(alias = "CMDH5")] +pub type Cmdh5 = crate::Reg; +#[doc = "Command High Buffer Register"] +pub mod cmdh5; +#[doc = "CMDL6 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl6`] module"] +#[doc(alias = "CMDL6")] +pub type Cmdl6 = crate::Reg; +#[doc = "Command Low Buffer Register"] +pub mod cmdl6; +#[doc = "CMDH6 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh6`] module"] +#[doc(alias = "CMDH6")] +pub type Cmdh6 = crate::Reg; +#[doc = "Command High Buffer Register"] +pub mod cmdh6; +#[doc = "CMDL7 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl7`] module"] +#[doc(alias = "CMDL7")] +pub type Cmdl7 = crate::Reg; +#[doc = "Command Low Buffer Register"] +pub mod cmdl7; +#[doc = "CMDH7 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh7`] module"] +#[doc(alias = "CMDH7")] +pub type Cmdh7 = crate::Reg; +#[doc = "Command High Buffer Register"] +pub mod cmdh7; +#[doc = "CV (rw) register accessor: Compare Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cv`] module"] +#[doc(alias = "CV")] +pub type Cv = crate::Reg; +#[doc = "Compare Value Register"] +pub mod cv; +#[doc = "RESFIFO0 (r) register accessor: Data Result FIFO Register\n\nYou can [`read`](crate::Reg::read) this register and get [`resfifo0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resfifo0`] module"] +#[doc(alias = "RESFIFO0")] +pub type Resfifo0 = crate::Reg; +#[doc = "Data Result FIFO Register"] +pub mod resfifo0; +#[doc = "CAL_GAR (rw) register accessor: Calibration General A-Side Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`cal_gar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cal_gar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cal_gar`] module"] +#[doc(alias = "CAL_GAR")] +pub type CalGar = crate::Reg; +#[doc = "Calibration General A-Side Registers"] +pub mod cal_gar; +#[doc = "CFG2 (rw) register accessor: Configuration 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg2`] module"] +#[doc(alias = "CFG2")] +pub type Cfg2 = crate::Reg; +#[doc = "Configuration 2 Register"] +pub mod cfg2; diff --git a/mcxa276-pac/src/adc0/cal_gar.rs b/mcxa276-pac/src/adc0/cal_gar.rs new file mode 100644 index 000000000..3a3375b33 --- /dev/null +++ b/mcxa276-pac/src/adc0/cal_gar.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CAL_GAR[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `CAL_GAR[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `CAL_GAR_VAL` reader - Calibration General A Side Register Element"] +pub type CalGarValR = crate::FieldReader; +#[doc = "Field `CAL_GAR_VAL` writer - Calibration General A Side Register Element"] +pub type CalGarValW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Calibration General A Side Register Element"] + #[inline(always)] + pub fn cal_gar_val(&self) -> CalGarValR { + CalGarValR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Calibration General A Side Register Element"] + #[inline(always)] + pub fn cal_gar_val(&mut self) -> CalGarValW { + CalGarValW::new(self, 0) + } +} +#[doc = "Calibration General A-Side Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`cal_gar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cal_gar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CalGarSpec; +impl crate::RegisterSpec for CalGarSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cal_gar::R`](R) reader structure"] +impl crate::Readable for CalGarSpec {} +#[doc = "`write(|w| ..)` method takes [`cal_gar::W`](W) writer structure"] +impl crate::Writable for CalGarSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CAL_GAR[%s] to value 0"] +impl crate::Resettable for CalGarSpec {} diff --git a/mcxa276-pac/src/adc0/cfg.rs b/mcxa276-pac/src/adc0/cfg.rs new file mode 100644 index 000000000..97c500db0 --- /dev/null +++ b/mcxa276-pac/src/adc0/cfg.rs @@ -0,0 +1,518 @@ +#[doc = "Register `CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CFG` writer"] +pub type W = crate::W; +#[doc = "ADC Trigger Priority Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tprictrl { + #[doc = "0: If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."] + AbortCurrentOnPriority = 0, + #[doc = "1: If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."] + FinishCurrentOnPriority = 1, + #[doc = "2: If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."] + FinishSequenceOnPriority = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tprictrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tprictrl { + type Ux = u8; +} +impl crate::IsEnum for Tprictrl {} +#[doc = "Field `TPRICTRL` reader - ADC Trigger Priority Control"] +pub type TprictrlR = crate::FieldReader; +impl TprictrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Tprictrl::AbortCurrentOnPriority), + 1 => Some(Tprictrl::FinishCurrentOnPriority), + 2 => Some(Tprictrl::FinishSequenceOnPriority), + _ => None, + } + } + #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."] + #[inline(always)] + pub fn is_abort_current_on_priority(&self) -> bool { + *self == Tprictrl::AbortCurrentOnPriority + } + #[doc = "If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."] + #[inline(always)] + pub fn is_finish_current_on_priority(&self) -> bool { + *self == Tprictrl::FinishCurrentOnPriority + } + #[doc = "If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."] + #[inline(always)] + pub fn is_finish_sequence_on_priority(&self) -> bool { + *self == Tprictrl::FinishSequenceOnPriority + } +} +#[doc = "Field `TPRICTRL` writer - ADC Trigger Priority Control"] +pub type TprictrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tprictrl>; +impl<'a, REG> TprictrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."] + #[inline(always)] + pub fn abort_current_on_priority(self) -> &'a mut crate::W { + self.variant(Tprictrl::AbortCurrentOnPriority) + } + #[doc = "If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."] + #[inline(always)] + pub fn finish_current_on_priority(self) -> &'a mut crate::W { + self.variant(Tprictrl::FinishCurrentOnPriority) + } + #[doc = "If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."] + #[inline(always)] + pub fn finish_sequence_on_priority(self) -> &'a mut crate::W { + self.variant(Tprictrl::FinishSequenceOnPriority) + } +} +#[doc = "Power Configuration Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwrsel { + #[doc = "0: Low power"] + Lowest = 0, + #[doc = "1: High power"] + Highest = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwrsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWRSEL` reader - Power Configuration Select"] +pub type PwrselR = crate::BitReader; +impl PwrselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwrsel { + match self.bits { + false => Pwrsel::Lowest, + true => Pwrsel::Highest, + } + } + #[doc = "Low power"] + #[inline(always)] + pub fn is_lowest(&self) -> bool { + *self == Pwrsel::Lowest + } + #[doc = "High power"] + #[inline(always)] + pub fn is_highest(&self) -> bool { + *self == Pwrsel::Highest + } +} +#[doc = "Field `PWRSEL` writer - Power Configuration Select"] +pub type PwrselW<'a, REG> = crate::BitWriter<'a, REG, Pwrsel>; +impl<'a, REG> PwrselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low power"] + #[inline(always)] + pub fn lowest(self) -> &'a mut crate::W { + self.variant(Pwrsel::Lowest) + } + #[doc = "High power"] + #[inline(always)] + pub fn highest(self) -> &'a mut crate::W { + self.variant(Pwrsel::Highest) + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Refsel { + #[doc = "0: (Default) Option 1 setting."] + Option1 = 0, + #[doc = "1: Option 2 setting."] + Option2 = 1, + #[doc = "2: Option 3 setting."] + Option3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Refsel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Refsel { + type Ux = u8; +} +impl crate::IsEnum for Refsel {} +#[doc = "Field `REFSEL` reader - Voltage Reference Selection"] +pub type RefselR = crate::FieldReader; +impl RefselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Refsel::Option1), + 1 => Some(Refsel::Option2), + 2 => Some(Refsel::Option3), + _ => None, + } + } + #[doc = "(Default) Option 1 setting."] + #[inline(always)] + pub fn is_option_1(&self) -> bool { + *self == Refsel::Option1 + } + #[doc = "Option 2 setting."] + #[inline(always)] + pub fn is_option_2(&self) -> bool { + *self == Refsel::Option2 + } + #[doc = "Option 3 setting."] + #[inline(always)] + pub fn is_option_3(&self) -> bool { + *self == Refsel::Option3 + } +} +#[doc = "Field `REFSEL` writer - Voltage Reference Selection"] +pub type RefselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Refsel>; +impl<'a, REG> RefselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "(Default) Option 1 setting."] + #[inline(always)] + pub fn option_1(self) -> &'a mut crate::W { + self.variant(Refsel::Option1) + } + #[doc = "Option 2 setting."] + #[inline(always)] + pub fn option_2(self) -> &'a mut crate::W { + self.variant(Refsel::Option2) + } + #[doc = "Option 3 setting."] + #[inline(always)] + pub fn option_3(self) -> &'a mut crate::W { + self.variant(Refsel::Option3) + } +} +#[doc = "Trigger Resume Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tres { + #[doc = "0: Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."] + Disabled = 0, + #[doc = "1: Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tres) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRES` reader - Trigger Resume Enable"] +pub type TresR = crate::BitReader; +impl TresR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tres { + match self.bits { + false => Tres::Disabled, + true => Tres::Enabled, + } + } + #[doc = "Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tres::Disabled + } + #[doc = "Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tres::Enabled + } +} +#[doc = "Field `TRES` writer - Trigger Resume Enable"] +pub type TresW<'a, REG> = crate::BitWriter<'a, REG, Tres>; +impl<'a, REG> TresW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tres::Disabled) + } + #[doc = "Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tres::Enabled) + } +} +#[doc = "Trigger Command Resume\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tcmdres { + #[doc = "0: Trigger sequences interrupted by a high priority trigger exception is automatically restarted."] + Disabled = 0, + #[doc = "1: Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tcmdres) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCMDRES` reader - Trigger Command Resume"] +pub type TcmdresR = crate::BitReader; +impl TcmdresR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcmdres { + match self.bits { + false => Tcmdres::Disabled, + true => Tcmdres::Enabled, + } + } + #[doc = "Trigger sequences interrupted by a high priority trigger exception is automatically restarted."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tcmdres::Disabled + } + #[doc = "Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tcmdres::Enabled + } +} +#[doc = "Field `TCMDRES` writer - Trigger Command Resume"] +pub type TcmdresW<'a, REG> = crate::BitWriter<'a, REG, Tcmdres>; +impl<'a, REG> TcmdresW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trigger sequences interrupted by a high priority trigger exception is automatically restarted."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tcmdres::Disabled) + } + #[doc = "Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tcmdres::Enabled) + } +} +#[doc = "High Priority Trigger Exception Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HptExdi { + #[doc = "0: High priority trigger exceptions are enabled."] + Enabled = 0, + #[doc = "1: High priority trigger exceptions are disabled."] + Disabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HptExdi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HPT_EXDI` reader - High Priority Trigger Exception Disable"] +pub type HptExdiR = crate::BitReader; +impl HptExdiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> HptExdi { + match self.bits { + false => HptExdi::Enabled, + true => HptExdi::Disabled, + } + } + #[doc = "High priority trigger exceptions are enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == HptExdi::Enabled + } + #[doc = "High priority trigger exceptions are disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == HptExdi::Disabled + } +} +#[doc = "Field `HPT_EXDI` writer - High Priority Trigger Exception Disable"] +pub type HptExdiW<'a, REG> = crate::BitWriter<'a, REG, HptExdi>; +impl<'a, REG> HptExdiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "High priority trigger exceptions are enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(HptExdi::Enabled) + } + #[doc = "High priority trigger exceptions are disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(HptExdi::Disabled) + } +} +#[doc = "Field `PUDLY` reader - Power Up Delay"] +pub type PudlyR = crate::FieldReader; +#[doc = "Field `PUDLY` writer - Power Up Delay"] +pub type PudlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "ADC Analog Pre-Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwren { + #[doc = "0: ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."] + NotPreEnabled = 0, + #[doc = "1: ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."] + PreEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWREN` reader - ADC Analog Pre-Enable"] +pub type PwrenR = crate::BitReader; +impl PwrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwren { + match self.bits { + false => Pwren::NotPreEnabled, + true => Pwren::PreEnabled, + } + } + #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."] + #[inline(always)] + pub fn is_not_pre_enabled(&self) -> bool { + *self == Pwren::NotPreEnabled + } + #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."] + #[inline(always)] + pub fn is_pre_enabled(&self) -> bool { + *self == Pwren::PreEnabled + } +} +#[doc = "Field `PWREN` writer - ADC Analog Pre-Enable"] +pub type PwrenW<'a, REG> = crate::BitWriter<'a, REG, Pwren>; +impl<'a, REG> PwrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."] + #[inline(always)] + pub fn not_pre_enabled(self) -> &'a mut crate::W { + self.variant(Pwren::NotPreEnabled) + } + #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."] + #[inline(always)] + pub fn pre_enabled(self) -> &'a mut crate::W { + self.variant(Pwren::PreEnabled) + } +} +impl R { + #[doc = "Bits 0:1 - ADC Trigger Priority Control"] + #[inline(always)] + pub fn tprictrl(&self) -> TprictrlR { + TprictrlR::new((self.bits & 3) as u8) + } + #[doc = "Bit 5 - Power Configuration Select"] + #[inline(always)] + pub fn pwrsel(&self) -> PwrselR { + PwrselR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Voltage Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> RefselR { + RefselR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - Trigger Resume Enable"] + #[inline(always)] + pub fn tres(&self) -> TresR { + TresR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Trigger Command Resume"] + #[inline(always)] + pub fn tcmdres(&self) -> TcmdresR { + TcmdresR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High Priority Trigger Exception Disable"] + #[inline(always)] + pub fn hpt_exdi(&self) -> HptExdiR { + HptExdiR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 16:23 - Power Up Delay"] + #[inline(always)] + pub fn pudly(&self) -> PudlyR { + PudlyR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 28 - ADC Analog Pre-Enable"] + #[inline(always)] + pub fn pwren(&self) -> PwrenR { + PwrenR::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - ADC Trigger Priority Control"] + #[inline(always)] + pub fn tprictrl(&mut self) -> TprictrlW { + TprictrlW::new(self, 0) + } + #[doc = "Bit 5 - Power Configuration Select"] + #[inline(always)] + pub fn pwrsel(&mut self) -> PwrselW { + PwrselW::new(self, 5) + } + #[doc = "Bits 6:7 - Voltage Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> RefselW { + RefselW::new(self, 6) + } + #[doc = "Bit 8 - Trigger Resume Enable"] + #[inline(always)] + pub fn tres(&mut self) -> TresW { + TresW::new(self, 8) + } + #[doc = "Bit 9 - Trigger Command Resume"] + #[inline(always)] + pub fn tcmdres(&mut self) -> TcmdresW { + TcmdresW::new(self, 9) + } + #[doc = "Bit 10 - High Priority Trigger Exception Disable"] + #[inline(always)] + pub fn hpt_exdi(&mut self) -> HptExdiW { + HptExdiW::new(self, 10) + } + #[doc = "Bits 16:23 - Power Up Delay"] + #[inline(always)] + pub fn pudly(&mut self) -> PudlyW { + PudlyW::new(self, 16) + } + #[doc = "Bit 28 - ADC Analog Pre-Enable"] + #[inline(always)] + pub fn pwren(&mut self) -> PwrenW { + PwrenW::new(self, 28) + } +} +#[doc = "Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CfgSpec; +impl crate::RegisterSpec for CfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfg::R`](R) reader structure"] +impl crate::Readable for CfgSpec {} +#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] +impl crate::Writable for CfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CFG to value 0x0080_0000"] +impl crate::Resettable for CfgSpec { + const RESET_VALUE: u32 = 0x0080_0000; +} diff --git a/mcxa276-pac/src/adc0/cfg2.rs b/mcxa276-pac/src/adc0/cfg2.rs new file mode 100644 index 000000000..c4023415a --- /dev/null +++ b/mcxa276-pac/src/adc0/cfg2.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CFG2` reader"] +pub type R = crate::R; +#[doc = "Register `CFG2` writer"] +pub type W = crate::W; +#[doc = "Field `JLEFT` reader - Justified Left Enable register"] +pub type JleftR = crate::BitReader; +#[doc = "Field `JLEFT` writer - Justified Left Enable register"] +pub type JleftW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "High Speed Enable register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hs { + #[doc = "0: High speed conversion mode disabled"] + Disabled = 0, + #[doc = "1: High speed conversion mode enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HS` reader - High Speed Enable register"] +pub type HsR = crate::BitReader; +impl HsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hs { + match self.bits { + false => Hs::Disabled, + true => Hs::Enabled, + } + } + #[doc = "High speed conversion mode disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Hs::Disabled + } + #[doc = "High speed conversion mode enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Hs::Enabled + } +} +#[doc = "Field `HS` writer - High Speed Enable register"] +pub type HsW<'a, REG> = crate::BitWriter<'a, REG, Hs>; +impl<'a, REG> HsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "High speed conversion mode disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Hs::Disabled) + } + #[doc = "High speed conversion mode enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Hs::Enabled) + } +} +#[doc = "High Speed Extra register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hsextra { + #[doc = "0: No extra cycle added"] + Hsextra0 = 0, + #[doc = "1: Extra cycle added"] + Hsextra1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hsextra) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HSEXTRA` reader - High Speed Extra register"] +pub type HsextraR = crate::BitReader; +impl HsextraR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hsextra { + match self.bits { + false => Hsextra::Hsextra0, + true => Hsextra::Hsextra1, + } + } + #[doc = "No extra cycle added"] + #[inline(always)] + pub fn is_hsextra_0(&self) -> bool { + *self == Hsextra::Hsextra0 + } + #[doc = "Extra cycle added"] + #[inline(always)] + pub fn is_hsextra_1(&self) -> bool { + *self == Hsextra::Hsextra1 + } +} +#[doc = "Field `HSEXTRA` writer - High Speed Extra register"] +pub type HsextraW<'a, REG> = crate::BitWriter<'a, REG, Hsextra>; +impl<'a, REG> HsextraW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No extra cycle added"] + #[inline(always)] + pub fn hsextra_0(self) -> &'a mut crate::W { + self.variant(Hsextra::Hsextra0) + } + #[doc = "Extra cycle added"] + #[inline(always)] + pub fn hsextra_1(self) -> &'a mut crate::W { + self.variant(Hsextra::Hsextra1) + } +} +#[doc = "Field `TUNE` reader - Tune Mode register"] +pub type TuneR = crate::FieldReader; +#[doc = "Field `TUNE` writer - Tune Mode register"] +pub type TuneW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 8 - Justified Left Enable register"] + #[inline(always)] + pub fn jleft(&self) -> JleftR { + JleftR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - High Speed Enable register"] + #[inline(always)] + pub fn hs(&self) -> HsR { + HsR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High Speed Extra register"] + #[inline(always)] + pub fn hsextra(&self) -> HsextraR { + HsextraR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 12:13 - Tune Mode register"] + #[inline(always)] + pub fn tune(&self) -> TuneR { + TuneR::new(((self.bits >> 12) & 3) as u8) + } +} +impl W { + #[doc = "Bit 8 - Justified Left Enable register"] + #[inline(always)] + pub fn jleft(&mut self) -> JleftW { + JleftW::new(self, 8) + } + #[doc = "Bit 9 - High Speed Enable register"] + #[inline(always)] + pub fn hs(&mut self) -> HsW { + HsW::new(self, 9) + } + #[doc = "Bit 10 - High Speed Extra register"] + #[inline(always)] + pub fn hsextra(&mut self) -> HsextraW { + HsextraW::new(self, 10) + } + #[doc = "Bits 12:13 - Tune Mode register"] + #[inline(always)] + pub fn tune(&mut self) -> TuneW { + TuneW::new(self, 12) + } +} +#[doc = "Configuration 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cfg2Spec; +impl crate::RegisterSpec for Cfg2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfg2::R`](R) reader structure"] +impl crate::Readable for Cfg2Spec {} +#[doc = "`write(|w| ..)` method takes [`cfg2::W`](W) writer structure"] +impl crate::Writable for Cfg2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CFG2 to value 0x1000"] +impl crate::Resettable for Cfg2Spec { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/mcxa276-pac/src/adc0/cmdh1.rs b/mcxa276-pac/src/adc0/cmdh1.rs new file mode 100644 index 000000000..84204853f --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdh1.rs @@ -0,0 +1,900 @@ +#[doc = "Register `CMDH1` reader"] +pub type R = crate::R; +#[doc = "Register `CMDH1` writer"] +pub type W = crate::W; +#[doc = "Compare Function Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpen { + #[doc = "0: Compare disabled."] + DisabledAlwaysStoreResult = 0, + #[doc = "2: Compare enabled. Store on true."] + CompareResultStoreIfTrue = 2, + #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpen { + type Ux = u8; +} +impl crate::IsEnum for Cmpen {} +#[doc = "Field `CMPEN` reader - Compare Function Enable"] +pub type CmpenR = crate::FieldReader; +impl CmpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpen::DisabledAlwaysStoreResult), + 2 => Some(Cmpen::CompareResultStoreIfTrue), + 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), + _ => None, + } + } + #[doc = "Compare disabled."] + #[inline(always)] + pub fn is_disabled_always_store_result(&self) -> bool { + *self == Cmpen::DisabledAlwaysStoreResult + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn is_compare_result_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultStoreIfTrue + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue + } +} +#[doc = "Field `CMPEN` writer - Compare Function Enable"] +pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; +impl<'a, REG> CmpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Compare disabled."] + #[inline(always)] + pub fn disabled_always_store_result(self) -> &'a mut crate::W { + self.variant(Cmpen::DisabledAlwaysStoreResult) + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn compare_result_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultStoreIfTrue) + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) + } +} +#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WaitTrig { + #[doc = "0: This command will be automatically executed."] + Disabled = 0, + #[doc = "1: The active trigger must be asserted again before executing this command."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WaitTrig) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] +pub type WaitTrigR = crate::BitReader; +impl WaitTrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WaitTrig { + match self.bits { + false => WaitTrig::Disabled, + true => WaitTrig::Enabled, + } + } + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WaitTrig::Disabled + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WaitTrig::Enabled + } +} +#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] +pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; +impl<'a, REG> WaitTrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Disabled) + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Enabled) + } +} +#[doc = "Loop with Increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lwi { + #[doc = "0: Auto channel increment disabled"] + Disabled = 0, + #[doc = "1: Auto channel increment enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lwi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LWI` reader - Loop with Increment"] +pub type LwiR = crate::BitReader; +impl LwiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lwi { + match self.bits { + false => Lwi::Disabled, + true => Lwi::Enabled, + } + } + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lwi::Disabled + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lwi::Enabled + } +} +#[doc = "Field `LWI` writer - Loop with Increment"] +pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; +impl<'a, REG> LwiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lwi::Disabled) + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lwi::Enabled) + } +} +#[doc = "Sample Time Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sts { + #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0, + #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + Sample5p5 = 1, + #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + Sample7p5 = 2, + #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + Sample11p5 = 3, + #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + Sample19p5 = 4, + #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + Sample35p5 = 5, + #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + Sample67p5 = 6, + #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + Sample131p5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sts) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sts { + type Ux = u8; +} +impl crate::IsEnum for Sts {} +#[doc = "Field `STS` reader - Sample Time Select"] +pub type StsR = crate::FieldReader; +impl StsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sts { + match self.bits { + 0 => Sts::Sample3p5, + 1 => Sts::Sample5p5, + 2 => Sts::Sample7p5, + 3 => Sts::Sample11p5, + 4 => Sts::Sample19p5, + 5 => Sts::Sample35p5, + 6 => Sts::Sample67p5, + 7 => Sts::Sample131p5, + _ => unreachable!(), + } + } + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn is_sample_3p5(&self) -> bool { + *self == Sts::Sample3p5 + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_5p5(&self) -> bool { + *self == Sts::Sample5p5 + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_7p5(&self) -> bool { + *self == Sts::Sample7p5 + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_11p5(&self) -> bool { + *self == Sts::Sample11p5 + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_19p5(&self) -> bool { + *self == Sts::Sample19p5 + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_35p5(&self) -> bool { + *self == Sts::Sample35p5 + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_67p5(&self) -> bool { + *self == Sts::Sample67p5 + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_131p5(&self) -> bool { + *self == Sts::Sample131p5 + } +} +#[doc = "Field `STS` writer - Sample Time Select"] +pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; +impl<'a, REG> StsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn sample_3p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample3p5) + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_5p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample5p5) + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_7p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample7p5) + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_11p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample11p5) + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_19p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample19p5) + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_35p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample35p5) + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_67p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample67p5) + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_131p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample131p5) + } +} +#[doc = "Hardware Average Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Avgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Avgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Avgs { + type Ux = u8; +} +impl crate::IsEnum for Avgs {} +#[doc = "Field `AVGS` reader - Hardware Average Select"] +pub type AvgsR = crate::FieldReader; +impl AvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Avgs::NoAverage), + 1 => Some(Avgs::Average2), + 2 => Some(Avgs::Average4), + 3 => Some(Avgs::Average8), + 4 => Some(Avgs::Average16), + 5 => Some(Avgs::Average32), + 6 => Some(Avgs::Average64), + 7 => Some(Avgs::Average128), + 8 => Some(Avgs::Average256), + 9 => Some(Avgs::Average512), + 10 => Some(Avgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == Avgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == Avgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == Avgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == Avgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == Avgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == Avgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == Avgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == Avgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == Avgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == Avgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == Avgs::Average1024 + } +} +#[doc = "Field `AVGS` writer - Hardware Average Select"] +pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; +impl<'a, REG> AvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(Avgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(Avgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(Avgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(Avgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(Avgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(Avgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(Avgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(Avgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(Avgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(Avgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(Avgs::Average1024) + } +} +#[doc = "Loop Count Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loop { + #[doc = "0: Looping not enabled. Command executes 1 time."] + CmdExec1x = 0, + #[doc = "1: Loop 1 time. Command executes 2 times."] + CmdExec2x = 1, + #[doc = "2: Loop 2 times. Command executes 3 times."] + CmdExec3x = 2, + #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes3 = 3, + #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes4 = 4, + #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes5 = 5, + #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes6 = 6, + #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes7 = 7, + #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes8 = 8, + #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes9 = 9, + #[doc = "15: Loop 15 times. Command executes 16 times."] + CmdExec15x = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loop { + type Ux = u8; +} +impl crate::IsEnum for Loop {} +#[doc = "Field `LOOP` reader - Loop Count Select"] +pub type LoopR = crate::FieldReader; +impl LoopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loop::CmdExec1x), + 1 => Some(Loop::CmdExec2x), + 2 => Some(Loop::CmdExec3x), + 3 => Some(Loop::CmdExecutesCorrespondingTimes3), + 4 => Some(Loop::CmdExecutesCorrespondingTimes4), + 5 => Some(Loop::CmdExecutesCorrespondingTimes5), + 6 => Some(Loop::CmdExecutesCorrespondingTimes6), + 7 => Some(Loop::CmdExecutesCorrespondingTimes7), + 8 => Some(Loop::CmdExecutesCorrespondingTimes8), + 9 => Some(Loop::CmdExecutesCorrespondingTimes9), + 15 => Some(Loop::CmdExec15x), + _ => None, + } + } + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn is_cmd_exec_1x(&self) -> bool { + *self == Loop::CmdExec1x + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn is_cmd_exec_2x(&self) -> bool { + *self == Loop::CmdExec2x + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn is_cmd_exec_3x(&self) -> bool { + *self == Loop::CmdExec3x + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes3 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes4 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes5 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes6 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes7 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes8 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes9 + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn is_cmd_exec_15x(&self) -> bool { + *self == Loop::CmdExec15x + } +} +#[doc = "Field `LOOP` writer - Loop Count Select"] +pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; +impl<'a, REG> LoopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn cmd_exec_1x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec1x) + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn cmd_exec_2x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec2x) + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn cmd_exec_3x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec3x) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes3) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes4) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes5) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes6) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes7) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes8) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes9) + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn cmd_exec_15x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec15x) + } +} +#[doc = "Next Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Next { + #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + NoNextCmdTerminateOnFinish = 0, + #[doc = "1: Select CMD1 command buffer register as next command."] + DoCmd1Next = 1, + #[doc = "2: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext2 = 2, + #[doc = "3: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext3 = 3, + #[doc = "4: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext4 = 4, + #[doc = "5: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext5 = 5, + #[doc = "6: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext6 = 6, + #[doc = "7: Select CMD7 command buffer register as next command."] + DoCmd7Next = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Next) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Next { + type Ux = u8; +} +impl crate::IsEnum for Next {} +#[doc = "Field `NEXT` reader - Next Command Select"] +pub type NextR = crate::FieldReader; +impl NextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Next { + match self.bits { + 0 => Next::NoNextCmdTerminateOnFinish, + 1 => Next::DoCmd1Next, + 2 => Next::DoCorrespondingCmdNext2, + 3 => Next::DoCorrespondingCmdNext3, + 4 => Next::DoCorrespondingCmdNext4, + 5 => Next::DoCorrespondingCmdNext5, + 6 => Next::DoCorrespondingCmdNext6, + 7 => Next::DoCmd7Next, + _ => unreachable!(), + } + } + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { + *self == Next::NoNextCmdTerminateOnFinish + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd1_next(&self) -> bool { + *self == Next::DoCmd1Next + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_2(&self) -> bool { + *self == Next::DoCorrespondingCmdNext2 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_3(&self) -> bool { + *self == Next::DoCorrespondingCmdNext3 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_4(&self) -> bool { + *self == Next::DoCorrespondingCmdNext4 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_5(&self) -> bool { + *self == Next::DoCorrespondingCmdNext5 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_6(&self) -> bool { + *self == Next::DoCorrespondingCmdNext6 + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd7_next(&self) -> bool { + *self == Next::DoCmd7Next + } +} +#[doc = "Field `NEXT` writer - Next Command Select"] +pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; +impl<'a, REG> NextW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { + self.variant(Next::NoNextCmdTerminateOnFinish) + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd1_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd1Next) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext2) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext3) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext4) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext5) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext6) + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd7_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd7Next) + } +} +impl R { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&self) -> CmpenR { + CmpenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&self) -> WaitTrigR { + WaitTrigR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&self) -> LwiR { + LwiR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&self) -> StsR { + StsR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&self) -> AvgsR { + AvgsR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&self) -> LoopR { + LoopR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&self) -> NextR { + NextR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&mut self) -> CmpenW { + CmpenW::new(self, 0) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&mut self) -> WaitTrigW { + WaitTrigW::new(self, 2) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&mut self) -> LwiW { + LwiW::new(self, 7) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&mut self) -> StsW { + StsW::new(self, 8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&mut self) -> AvgsW { + AvgsW::new(self, 12) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&mut self) -> LoopW { + LoopW::new(self, 16) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&mut self) -> NextW { + NextW::new(self, 24) + } +} +#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdh1Spec; +impl crate::RegisterSpec for Cmdh1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdh1::R`](R) reader structure"] +impl crate::Readable for Cmdh1Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdh1::W`](W) writer structure"] +impl crate::Writable for Cmdh1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDH1 to value 0"] +impl crate::Resettable for Cmdh1Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh2.rs b/mcxa276-pac/src/adc0/cmdh2.rs new file mode 100644 index 000000000..782af4a8c --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdh2.rs @@ -0,0 +1,900 @@ +#[doc = "Register `CMDH2` reader"] +pub type R = crate::R; +#[doc = "Register `CMDH2` writer"] +pub type W = crate::W; +#[doc = "Compare Function Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpen { + #[doc = "0: Compare disabled."] + DisabledAlwaysStoreResult = 0, + #[doc = "2: Compare enabled. Store on true."] + CompareResultStoreIfTrue = 2, + #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpen { + type Ux = u8; +} +impl crate::IsEnum for Cmpen {} +#[doc = "Field `CMPEN` reader - Compare Function Enable"] +pub type CmpenR = crate::FieldReader; +impl CmpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpen::DisabledAlwaysStoreResult), + 2 => Some(Cmpen::CompareResultStoreIfTrue), + 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), + _ => None, + } + } + #[doc = "Compare disabled."] + #[inline(always)] + pub fn is_disabled_always_store_result(&self) -> bool { + *self == Cmpen::DisabledAlwaysStoreResult + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn is_compare_result_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultStoreIfTrue + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue + } +} +#[doc = "Field `CMPEN` writer - Compare Function Enable"] +pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; +impl<'a, REG> CmpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Compare disabled."] + #[inline(always)] + pub fn disabled_always_store_result(self) -> &'a mut crate::W { + self.variant(Cmpen::DisabledAlwaysStoreResult) + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn compare_result_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultStoreIfTrue) + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) + } +} +#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WaitTrig { + #[doc = "0: This command will be automatically executed."] + Disabled = 0, + #[doc = "1: The active trigger must be asserted again before executing this command."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WaitTrig) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] +pub type WaitTrigR = crate::BitReader; +impl WaitTrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WaitTrig { + match self.bits { + false => WaitTrig::Disabled, + true => WaitTrig::Enabled, + } + } + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WaitTrig::Disabled + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WaitTrig::Enabled + } +} +#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] +pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; +impl<'a, REG> WaitTrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Disabled) + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Enabled) + } +} +#[doc = "Loop with Increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lwi { + #[doc = "0: Auto channel increment disabled"] + Disabled = 0, + #[doc = "1: Auto channel increment enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lwi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LWI` reader - Loop with Increment"] +pub type LwiR = crate::BitReader; +impl LwiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lwi { + match self.bits { + false => Lwi::Disabled, + true => Lwi::Enabled, + } + } + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lwi::Disabled + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lwi::Enabled + } +} +#[doc = "Field `LWI` writer - Loop with Increment"] +pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; +impl<'a, REG> LwiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lwi::Disabled) + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lwi::Enabled) + } +} +#[doc = "Sample Time Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sts { + #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0, + #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + Sample5p5 = 1, + #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + Sample7p5 = 2, + #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + Sample11p5 = 3, + #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + Sample19p5 = 4, + #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + Sample35p5 = 5, + #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + Sample67p5 = 6, + #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + Sample131p5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sts) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sts { + type Ux = u8; +} +impl crate::IsEnum for Sts {} +#[doc = "Field `STS` reader - Sample Time Select"] +pub type StsR = crate::FieldReader; +impl StsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sts { + match self.bits { + 0 => Sts::Sample3p5, + 1 => Sts::Sample5p5, + 2 => Sts::Sample7p5, + 3 => Sts::Sample11p5, + 4 => Sts::Sample19p5, + 5 => Sts::Sample35p5, + 6 => Sts::Sample67p5, + 7 => Sts::Sample131p5, + _ => unreachable!(), + } + } + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn is_sample_3p5(&self) -> bool { + *self == Sts::Sample3p5 + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_5p5(&self) -> bool { + *self == Sts::Sample5p5 + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_7p5(&self) -> bool { + *self == Sts::Sample7p5 + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_11p5(&self) -> bool { + *self == Sts::Sample11p5 + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_19p5(&self) -> bool { + *self == Sts::Sample19p5 + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_35p5(&self) -> bool { + *self == Sts::Sample35p5 + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_67p5(&self) -> bool { + *self == Sts::Sample67p5 + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_131p5(&self) -> bool { + *self == Sts::Sample131p5 + } +} +#[doc = "Field `STS` writer - Sample Time Select"] +pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; +impl<'a, REG> StsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn sample_3p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample3p5) + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_5p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample5p5) + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_7p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample7p5) + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_11p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample11p5) + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_19p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample19p5) + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_35p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample35p5) + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_67p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample67p5) + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_131p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample131p5) + } +} +#[doc = "Hardware Average Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Avgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Avgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Avgs { + type Ux = u8; +} +impl crate::IsEnum for Avgs {} +#[doc = "Field `AVGS` reader - Hardware Average Select"] +pub type AvgsR = crate::FieldReader; +impl AvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Avgs::NoAverage), + 1 => Some(Avgs::Average2), + 2 => Some(Avgs::Average4), + 3 => Some(Avgs::Average8), + 4 => Some(Avgs::Average16), + 5 => Some(Avgs::Average32), + 6 => Some(Avgs::Average64), + 7 => Some(Avgs::Average128), + 8 => Some(Avgs::Average256), + 9 => Some(Avgs::Average512), + 10 => Some(Avgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == Avgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == Avgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == Avgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == Avgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == Avgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == Avgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == Avgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == Avgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == Avgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == Avgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == Avgs::Average1024 + } +} +#[doc = "Field `AVGS` writer - Hardware Average Select"] +pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; +impl<'a, REG> AvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(Avgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(Avgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(Avgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(Avgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(Avgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(Avgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(Avgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(Avgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(Avgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(Avgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(Avgs::Average1024) + } +} +#[doc = "Loop Count Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loop { + #[doc = "0: Looping not enabled. Command executes 1 time."] + CmdExec1x = 0, + #[doc = "1: Loop 1 time. Command executes 2 times."] + CmdExec2x = 1, + #[doc = "2: Loop 2 times. Command executes 3 times."] + CmdExec3x = 2, + #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes3 = 3, + #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes4 = 4, + #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes5 = 5, + #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes6 = 6, + #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes7 = 7, + #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes8 = 8, + #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes9 = 9, + #[doc = "15: Loop 15 times. Command executes 16 times."] + CmdExec15x = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loop { + type Ux = u8; +} +impl crate::IsEnum for Loop {} +#[doc = "Field `LOOP` reader - Loop Count Select"] +pub type LoopR = crate::FieldReader; +impl LoopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loop::CmdExec1x), + 1 => Some(Loop::CmdExec2x), + 2 => Some(Loop::CmdExec3x), + 3 => Some(Loop::CmdExecutesCorrespondingTimes3), + 4 => Some(Loop::CmdExecutesCorrespondingTimes4), + 5 => Some(Loop::CmdExecutesCorrespondingTimes5), + 6 => Some(Loop::CmdExecutesCorrespondingTimes6), + 7 => Some(Loop::CmdExecutesCorrespondingTimes7), + 8 => Some(Loop::CmdExecutesCorrespondingTimes8), + 9 => Some(Loop::CmdExecutesCorrespondingTimes9), + 15 => Some(Loop::CmdExec15x), + _ => None, + } + } + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn is_cmd_exec_1x(&self) -> bool { + *self == Loop::CmdExec1x + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn is_cmd_exec_2x(&self) -> bool { + *self == Loop::CmdExec2x + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn is_cmd_exec_3x(&self) -> bool { + *self == Loop::CmdExec3x + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes3 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes4 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes5 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes6 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes7 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes8 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes9 + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn is_cmd_exec_15x(&self) -> bool { + *self == Loop::CmdExec15x + } +} +#[doc = "Field `LOOP` writer - Loop Count Select"] +pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; +impl<'a, REG> LoopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn cmd_exec_1x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec1x) + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn cmd_exec_2x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec2x) + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn cmd_exec_3x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec3x) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes3) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes4) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes5) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes6) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes7) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes8) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes9) + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn cmd_exec_15x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec15x) + } +} +#[doc = "Next Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Next { + #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + NoNextCmdTerminateOnFinish = 0, + #[doc = "1: Select CMD1 command buffer register as next command."] + DoCmd1Next = 1, + #[doc = "2: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext2 = 2, + #[doc = "3: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext3 = 3, + #[doc = "4: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext4 = 4, + #[doc = "5: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext5 = 5, + #[doc = "6: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext6 = 6, + #[doc = "7: Select CMD7 command buffer register as next command."] + DoCmd7Next = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Next) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Next { + type Ux = u8; +} +impl crate::IsEnum for Next {} +#[doc = "Field `NEXT` reader - Next Command Select"] +pub type NextR = crate::FieldReader; +impl NextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Next { + match self.bits { + 0 => Next::NoNextCmdTerminateOnFinish, + 1 => Next::DoCmd1Next, + 2 => Next::DoCorrespondingCmdNext2, + 3 => Next::DoCorrespondingCmdNext3, + 4 => Next::DoCorrespondingCmdNext4, + 5 => Next::DoCorrespondingCmdNext5, + 6 => Next::DoCorrespondingCmdNext6, + 7 => Next::DoCmd7Next, + _ => unreachable!(), + } + } + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { + *self == Next::NoNextCmdTerminateOnFinish + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd1_next(&self) -> bool { + *self == Next::DoCmd1Next + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_2(&self) -> bool { + *self == Next::DoCorrespondingCmdNext2 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_3(&self) -> bool { + *self == Next::DoCorrespondingCmdNext3 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_4(&self) -> bool { + *self == Next::DoCorrespondingCmdNext4 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_5(&self) -> bool { + *self == Next::DoCorrespondingCmdNext5 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_6(&self) -> bool { + *self == Next::DoCorrespondingCmdNext6 + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd7_next(&self) -> bool { + *self == Next::DoCmd7Next + } +} +#[doc = "Field `NEXT` writer - Next Command Select"] +pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; +impl<'a, REG> NextW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { + self.variant(Next::NoNextCmdTerminateOnFinish) + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd1_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd1Next) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext2) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext3) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext4) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext5) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext6) + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd7_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd7Next) + } +} +impl R { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&self) -> CmpenR { + CmpenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&self) -> WaitTrigR { + WaitTrigR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&self) -> LwiR { + LwiR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&self) -> StsR { + StsR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&self) -> AvgsR { + AvgsR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&self) -> LoopR { + LoopR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&self) -> NextR { + NextR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&mut self) -> CmpenW { + CmpenW::new(self, 0) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&mut self) -> WaitTrigW { + WaitTrigW::new(self, 2) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&mut self) -> LwiW { + LwiW::new(self, 7) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&mut self) -> StsW { + StsW::new(self, 8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&mut self) -> AvgsW { + AvgsW::new(self, 12) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&mut self) -> LoopW { + LoopW::new(self, 16) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&mut self) -> NextW { + NextW::new(self, 24) + } +} +#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdh2Spec; +impl crate::RegisterSpec for Cmdh2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdh2::R`](R) reader structure"] +impl crate::Readable for Cmdh2Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdh2::W`](W) writer structure"] +impl crate::Writable for Cmdh2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDH2 to value 0"] +impl crate::Resettable for Cmdh2Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh3.rs b/mcxa276-pac/src/adc0/cmdh3.rs new file mode 100644 index 000000000..ad98b405f --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdh3.rs @@ -0,0 +1,900 @@ +#[doc = "Register `CMDH3` reader"] +pub type R = crate::R; +#[doc = "Register `CMDH3` writer"] +pub type W = crate::W; +#[doc = "Compare Function Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpen { + #[doc = "0: Compare disabled."] + DisabledAlwaysStoreResult = 0, + #[doc = "2: Compare enabled. Store on true."] + CompareResultStoreIfTrue = 2, + #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpen { + type Ux = u8; +} +impl crate::IsEnum for Cmpen {} +#[doc = "Field `CMPEN` reader - Compare Function Enable"] +pub type CmpenR = crate::FieldReader; +impl CmpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpen::DisabledAlwaysStoreResult), + 2 => Some(Cmpen::CompareResultStoreIfTrue), + 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), + _ => None, + } + } + #[doc = "Compare disabled."] + #[inline(always)] + pub fn is_disabled_always_store_result(&self) -> bool { + *self == Cmpen::DisabledAlwaysStoreResult + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn is_compare_result_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultStoreIfTrue + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue + } +} +#[doc = "Field `CMPEN` writer - Compare Function Enable"] +pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; +impl<'a, REG> CmpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Compare disabled."] + #[inline(always)] + pub fn disabled_always_store_result(self) -> &'a mut crate::W { + self.variant(Cmpen::DisabledAlwaysStoreResult) + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn compare_result_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultStoreIfTrue) + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) + } +} +#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WaitTrig { + #[doc = "0: This command will be automatically executed."] + Disabled = 0, + #[doc = "1: The active trigger must be asserted again before executing this command."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WaitTrig) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] +pub type WaitTrigR = crate::BitReader; +impl WaitTrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WaitTrig { + match self.bits { + false => WaitTrig::Disabled, + true => WaitTrig::Enabled, + } + } + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WaitTrig::Disabled + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WaitTrig::Enabled + } +} +#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] +pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; +impl<'a, REG> WaitTrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Disabled) + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Enabled) + } +} +#[doc = "Loop with Increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lwi { + #[doc = "0: Auto channel increment disabled"] + Disabled = 0, + #[doc = "1: Auto channel increment enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lwi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LWI` reader - Loop with Increment"] +pub type LwiR = crate::BitReader; +impl LwiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lwi { + match self.bits { + false => Lwi::Disabled, + true => Lwi::Enabled, + } + } + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lwi::Disabled + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lwi::Enabled + } +} +#[doc = "Field `LWI` writer - Loop with Increment"] +pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; +impl<'a, REG> LwiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lwi::Disabled) + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lwi::Enabled) + } +} +#[doc = "Sample Time Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sts { + #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0, + #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + Sample5p5 = 1, + #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + Sample7p5 = 2, + #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + Sample11p5 = 3, + #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + Sample19p5 = 4, + #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + Sample35p5 = 5, + #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + Sample67p5 = 6, + #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + Sample131p5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sts) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sts { + type Ux = u8; +} +impl crate::IsEnum for Sts {} +#[doc = "Field `STS` reader - Sample Time Select"] +pub type StsR = crate::FieldReader; +impl StsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sts { + match self.bits { + 0 => Sts::Sample3p5, + 1 => Sts::Sample5p5, + 2 => Sts::Sample7p5, + 3 => Sts::Sample11p5, + 4 => Sts::Sample19p5, + 5 => Sts::Sample35p5, + 6 => Sts::Sample67p5, + 7 => Sts::Sample131p5, + _ => unreachable!(), + } + } + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn is_sample_3p5(&self) -> bool { + *self == Sts::Sample3p5 + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_5p5(&self) -> bool { + *self == Sts::Sample5p5 + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_7p5(&self) -> bool { + *self == Sts::Sample7p5 + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_11p5(&self) -> bool { + *self == Sts::Sample11p5 + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_19p5(&self) -> bool { + *self == Sts::Sample19p5 + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_35p5(&self) -> bool { + *self == Sts::Sample35p5 + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_67p5(&self) -> bool { + *self == Sts::Sample67p5 + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_131p5(&self) -> bool { + *self == Sts::Sample131p5 + } +} +#[doc = "Field `STS` writer - Sample Time Select"] +pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; +impl<'a, REG> StsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn sample_3p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample3p5) + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_5p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample5p5) + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_7p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample7p5) + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_11p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample11p5) + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_19p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample19p5) + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_35p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample35p5) + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_67p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample67p5) + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_131p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample131p5) + } +} +#[doc = "Hardware Average Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Avgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Avgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Avgs { + type Ux = u8; +} +impl crate::IsEnum for Avgs {} +#[doc = "Field `AVGS` reader - Hardware Average Select"] +pub type AvgsR = crate::FieldReader; +impl AvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Avgs::NoAverage), + 1 => Some(Avgs::Average2), + 2 => Some(Avgs::Average4), + 3 => Some(Avgs::Average8), + 4 => Some(Avgs::Average16), + 5 => Some(Avgs::Average32), + 6 => Some(Avgs::Average64), + 7 => Some(Avgs::Average128), + 8 => Some(Avgs::Average256), + 9 => Some(Avgs::Average512), + 10 => Some(Avgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == Avgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == Avgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == Avgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == Avgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == Avgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == Avgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == Avgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == Avgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == Avgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == Avgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == Avgs::Average1024 + } +} +#[doc = "Field `AVGS` writer - Hardware Average Select"] +pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; +impl<'a, REG> AvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(Avgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(Avgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(Avgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(Avgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(Avgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(Avgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(Avgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(Avgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(Avgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(Avgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(Avgs::Average1024) + } +} +#[doc = "Loop Count Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loop { + #[doc = "0: Looping not enabled. Command executes 1 time."] + CmdExec1x = 0, + #[doc = "1: Loop 1 time. Command executes 2 times."] + CmdExec2x = 1, + #[doc = "2: Loop 2 times. Command executes 3 times."] + CmdExec3x = 2, + #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes3 = 3, + #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes4 = 4, + #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes5 = 5, + #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes6 = 6, + #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes7 = 7, + #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes8 = 8, + #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes9 = 9, + #[doc = "15: Loop 15 times. Command executes 16 times."] + CmdExec15x = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loop { + type Ux = u8; +} +impl crate::IsEnum for Loop {} +#[doc = "Field `LOOP` reader - Loop Count Select"] +pub type LoopR = crate::FieldReader; +impl LoopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loop::CmdExec1x), + 1 => Some(Loop::CmdExec2x), + 2 => Some(Loop::CmdExec3x), + 3 => Some(Loop::CmdExecutesCorrespondingTimes3), + 4 => Some(Loop::CmdExecutesCorrespondingTimes4), + 5 => Some(Loop::CmdExecutesCorrespondingTimes5), + 6 => Some(Loop::CmdExecutesCorrespondingTimes6), + 7 => Some(Loop::CmdExecutesCorrespondingTimes7), + 8 => Some(Loop::CmdExecutesCorrespondingTimes8), + 9 => Some(Loop::CmdExecutesCorrespondingTimes9), + 15 => Some(Loop::CmdExec15x), + _ => None, + } + } + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn is_cmd_exec_1x(&self) -> bool { + *self == Loop::CmdExec1x + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn is_cmd_exec_2x(&self) -> bool { + *self == Loop::CmdExec2x + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn is_cmd_exec_3x(&self) -> bool { + *self == Loop::CmdExec3x + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes3 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes4 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes5 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes6 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes7 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes8 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes9 + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn is_cmd_exec_15x(&self) -> bool { + *self == Loop::CmdExec15x + } +} +#[doc = "Field `LOOP` writer - Loop Count Select"] +pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; +impl<'a, REG> LoopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn cmd_exec_1x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec1x) + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn cmd_exec_2x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec2x) + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn cmd_exec_3x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec3x) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes3) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes4) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes5) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes6) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes7) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes8) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes9) + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn cmd_exec_15x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec15x) + } +} +#[doc = "Next Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Next { + #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + NoNextCmdTerminateOnFinish = 0, + #[doc = "1: Select CMD1 command buffer register as next command."] + DoCmd1Next = 1, + #[doc = "2: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext2 = 2, + #[doc = "3: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext3 = 3, + #[doc = "4: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext4 = 4, + #[doc = "5: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext5 = 5, + #[doc = "6: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext6 = 6, + #[doc = "7: Select CMD7 command buffer register as next command."] + DoCmd7Next = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Next) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Next { + type Ux = u8; +} +impl crate::IsEnum for Next {} +#[doc = "Field `NEXT` reader - Next Command Select"] +pub type NextR = crate::FieldReader; +impl NextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Next { + match self.bits { + 0 => Next::NoNextCmdTerminateOnFinish, + 1 => Next::DoCmd1Next, + 2 => Next::DoCorrespondingCmdNext2, + 3 => Next::DoCorrespondingCmdNext3, + 4 => Next::DoCorrespondingCmdNext4, + 5 => Next::DoCorrespondingCmdNext5, + 6 => Next::DoCorrespondingCmdNext6, + 7 => Next::DoCmd7Next, + _ => unreachable!(), + } + } + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { + *self == Next::NoNextCmdTerminateOnFinish + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd1_next(&self) -> bool { + *self == Next::DoCmd1Next + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_2(&self) -> bool { + *self == Next::DoCorrespondingCmdNext2 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_3(&self) -> bool { + *self == Next::DoCorrespondingCmdNext3 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_4(&self) -> bool { + *self == Next::DoCorrespondingCmdNext4 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_5(&self) -> bool { + *self == Next::DoCorrespondingCmdNext5 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_6(&self) -> bool { + *self == Next::DoCorrespondingCmdNext6 + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd7_next(&self) -> bool { + *self == Next::DoCmd7Next + } +} +#[doc = "Field `NEXT` writer - Next Command Select"] +pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; +impl<'a, REG> NextW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { + self.variant(Next::NoNextCmdTerminateOnFinish) + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd1_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd1Next) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext2) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext3) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext4) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext5) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext6) + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd7_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd7Next) + } +} +impl R { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&self) -> CmpenR { + CmpenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&self) -> WaitTrigR { + WaitTrigR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&self) -> LwiR { + LwiR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&self) -> StsR { + StsR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&self) -> AvgsR { + AvgsR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&self) -> LoopR { + LoopR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&self) -> NextR { + NextR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&mut self) -> CmpenW { + CmpenW::new(self, 0) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&mut self) -> WaitTrigW { + WaitTrigW::new(self, 2) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&mut self) -> LwiW { + LwiW::new(self, 7) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&mut self) -> StsW { + StsW::new(self, 8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&mut self) -> AvgsW { + AvgsW::new(self, 12) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&mut self) -> LoopW { + LoopW::new(self, 16) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&mut self) -> NextW { + NextW::new(self, 24) + } +} +#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdh3Spec; +impl crate::RegisterSpec for Cmdh3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdh3::R`](R) reader structure"] +impl crate::Readable for Cmdh3Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdh3::W`](W) writer structure"] +impl crate::Writable for Cmdh3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDH3 to value 0"] +impl crate::Resettable for Cmdh3Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh4.rs b/mcxa276-pac/src/adc0/cmdh4.rs new file mode 100644 index 000000000..56eb3de39 --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdh4.rs @@ -0,0 +1,900 @@ +#[doc = "Register `CMDH4` reader"] +pub type R = crate::R; +#[doc = "Register `CMDH4` writer"] +pub type W = crate::W; +#[doc = "Compare Function Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpen { + #[doc = "0: Compare disabled."] + DisabledAlwaysStoreResult = 0, + #[doc = "2: Compare enabled. Store on true."] + CompareResultStoreIfTrue = 2, + #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpen { + type Ux = u8; +} +impl crate::IsEnum for Cmpen {} +#[doc = "Field `CMPEN` reader - Compare Function Enable"] +pub type CmpenR = crate::FieldReader; +impl CmpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpen::DisabledAlwaysStoreResult), + 2 => Some(Cmpen::CompareResultStoreIfTrue), + 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), + _ => None, + } + } + #[doc = "Compare disabled."] + #[inline(always)] + pub fn is_disabled_always_store_result(&self) -> bool { + *self == Cmpen::DisabledAlwaysStoreResult + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn is_compare_result_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultStoreIfTrue + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue + } +} +#[doc = "Field `CMPEN` writer - Compare Function Enable"] +pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; +impl<'a, REG> CmpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Compare disabled."] + #[inline(always)] + pub fn disabled_always_store_result(self) -> &'a mut crate::W { + self.variant(Cmpen::DisabledAlwaysStoreResult) + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn compare_result_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultStoreIfTrue) + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) + } +} +#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WaitTrig { + #[doc = "0: This command will be automatically executed."] + Disabled = 0, + #[doc = "1: The active trigger must be asserted again before executing this command."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WaitTrig) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] +pub type WaitTrigR = crate::BitReader; +impl WaitTrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WaitTrig { + match self.bits { + false => WaitTrig::Disabled, + true => WaitTrig::Enabled, + } + } + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WaitTrig::Disabled + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WaitTrig::Enabled + } +} +#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] +pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; +impl<'a, REG> WaitTrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Disabled) + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Enabled) + } +} +#[doc = "Loop with Increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lwi { + #[doc = "0: Auto channel increment disabled"] + Disabled = 0, + #[doc = "1: Auto channel increment enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lwi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LWI` reader - Loop with Increment"] +pub type LwiR = crate::BitReader; +impl LwiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lwi { + match self.bits { + false => Lwi::Disabled, + true => Lwi::Enabled, + } + } + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lwi::Disabled + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lwi::Enabled + } +} +#[doc = "Field `LWI` writer - Loop with Increment"] +pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; +impl<'a, REG> LwiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lwi::Disabled) + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lwi::Enabled) + } +} +#[doc = "Sample Time Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sts { + #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0, + #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + Sample5p5 = 1, + #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + Sample7p5 = 2, + #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + Sample11p5 = 3, + #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + Sample19p5 = 4, + #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + Sample35p5 = 5, + #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + Sample67p5 = 6, + #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + Sample131p5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sts) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sts { + type Ux = u8; +} +impl crate::IsEnum for Sts {} +#[doc = "Field `STS` reader - Sample Time Select"] +pub type StsR = crate::FieldReader; +impl StsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sts { + match self.bits { + 0 => Sts::Sample3p5, + 1 => Sts::Sample5p5, + 2 => Sts::Sample7p5, + 3 => Sts::Sample11p5, + 4 => Sts::Sample19p5, + 5 => Sts::Sample35p5, + 6 => Sts::Sample67p5, + 7 => Sts::Sample131p5, + _ => unreachable!(), + } + } + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn is_sample_3p5(&self) -> bool { + *self == Sts::Sample3p5 + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_5p5(&self) -> bool { + *self == Sts::Sample5p5 + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_7p5(&self) -> bool { + *self == Sts::Sample7p5 + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_11p5(&self) -> bool { + *self == Sts::Sample11p5 + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_19p5(&self) -> bool { + *self == Sts::Sample19p5 + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_35p5(&self) -> bool { + *self == Sts::Sample35p5 + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_67p5(&self) -> bool { + *self == Sts::Sample67p5 + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_131p5(&self) -> bool { + *self == Sts::Sample131p5 + } +} +#[doc = "Field `STS` writer - Sample Time Select"] +pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; +impl<'a, REG> StsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn sample_3p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample3p5) + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_5p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample5p5) + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_7p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample7p5) + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_11p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample11p5) + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_19p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample19p5) + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_35p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample35p5) + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_67p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample67p5) + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_131p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample131p5) + } +} +#[doc = "Hardware Average Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Avgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Avgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Avgs { + type Ux = u8; +} +impl crate::IsEnum for Avgs {} +#[doc = "Field `AVGS` reader - Hardware Average Select"] +pub type AvgsR = crate::FieldReader; +impl AvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Avgs::NoAverage), + 1 => Some(Avgs::Average2), + 2 => Some(Avgs::Average4), + 3 => Some(Avgs::Average8), + 4 => Some(Avgs::Average16), + 5 => Some(Avgs::Average32), + 6 => Some(Avgs::Average64), + 7 => Some(Avgs::Average128), + 8 => Some(Avgs::Average256), + 9 => Some(Avgs::Average512), + 10 => Some(Avgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == Avgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == Avgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == Avgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == Avgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == Avgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == Avgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == Avgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == Avgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == Avgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == Avgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == Avgs::Average1024 + } +} +#[doc = "Field `AVGS` writer - Hardware Average Select"] +pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; +impl<'a, REG> AvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(Avgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(Avgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(Avgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(Avgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(Avgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(Avgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(Avgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(Avgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(Avgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(Avgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(Avgs::Average1024) + } +} +#[doc = "Loop Count Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loop { + #[doc = "0: Looping not enabled. Command executes 1 time."] + CmdExec1x = 0, + #[doc = "1: Loop 1 time. Command executes 2 times."] + CmdExec2x = 1, + #[doc = "2: Loop 2 times. Command executes 3 times."] + CmdExec3x = 2, + #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes3 = 3, + #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes4 = 4, + #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes5 = 5, + #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes6 = 6, + #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes7 = 7, + #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes8 = 8, + #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes9 = 9, + #[doc = "15: Loop 15 times. Command executes 16 times."] + CmdExec15x = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loop { + type Ux = u8; +} +impl crate::IsEnum for Loop {} +#[doc = "Field `LOOP` reader - Loop Count Select"] +pub type LoopR = crate::FieldReader; +impl LoopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loop::CmdExec1x), + 1 => Some(Loop::CmdExec2x), + 2 => Some(Loop::CmdExec3x), + 3 => Some(Loop::CmdExecutesCorrespondingTimes3), + 4 => Some(Loop::CmdExecutesCorrespondingTimes4), + 5 => Some(Loop::CmdExecutesCorrespondingTimes5), + 6 => Some(Loop::CmdExecutesCorrespondingTimes6), + 7 => Some(Loop::CmdExecutesCorrespondingTimes7), + 8 => Some(Loop::CmdExecutesCorrespondingTimes8), + 9 => Some(Loop::CmdExecutesCorrespondingTimes9), + 15 => Some(Loop::CmdExec15x), + _ => None, + } + } + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn is_cmd_exec_1x(&self) -> bool { + *self == Loop::CmdExec1x + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn is_cmd_exec_2x(&self) -> bool { + *self == Loop::CmdExec2x + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn is_cmd_exec_3x(&self) -> bool { + *self == Loop::CmdExec3x + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes3 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes4 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes5 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes6 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes7 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes8 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes9 + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn is_cmd_exec_15x(&self) -> bool { + *self == Loop::CmdExec15x + } +} +#[doc = "Field `LOOP` writer - Loop Count Select"] +pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; +impl<'a, REG> LoopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn cmd_exec_1x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec1x) + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn cmd_exec_2x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec2x) + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn cmd_exec_3x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec3x) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes3) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes4) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes5) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes6) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes7) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes8) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes9) + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn cmd_exec_15x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec15x) + } +} +#[doc = "Next Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Next { + #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + NoNextCmdTerminateOnFinish = 0, + #[doc = "1: Select CMD1 command buffer register as next command."] + DoCmd1Next = 1, + #[doc = "2: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext2 = 2, + #[doc = "3: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext3 = 3, + #[doc = "4: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext4 = 4, + #[doc = "5: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext5 = 5, + #[doc = "6: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext6 = 6, + #[doc = "7: Select CMD7 command buffer register as next command."] + DoCmd7Next = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Next) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Next { + type Ux = u8; +} +impl crate::IsEnum for Next {} +#[doc = "Field `NEXT` reader - Next Command Select"] +pub type NextR = crate::FieldReader; +impl NextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Next { + match self.bits { + 0 => Next::NoNextCmdTerminateOnFinish, + 1 => Next::DoCmd1Next, + 2 => Next::DoCorrespondingCmdNext2, + 3 => Next::DoCorrespondingCmdNext3, + 4 => Next::DoCorrespondingCmdNext4, + 5 => Next::DoCorrespondingCmdNext5, + 6 => Next::DoCorrespondingCmdNext6, + 7 => Next::DoCmd7Next, + _ => unreachable!(), + } + } + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { + *self == Next::NoNextCmdTerminateOnFinish + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd1_next(&self) -> bool { + *self == Next::DoCmd1Next + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_2(&self) -> bool { + *self == Next::DoCorrespondingCmdNext2 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_3(&self) -> bool { + *self == Next::DoCorrespondingCmdNext3 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_4(&self) -> bool { + *self == Next::DoCorrespondingCmdNext4 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_5(&self) -> bool { + *self == Next::DoCorrespondingCmdNext5 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_6(&self) -> bool { + *self == Next::DoCorrespondingCmdNext6 + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd7_next(&self) -> bool { + *self == Next::DoCmd7Next + } +} +#[doc = "Field `NEXT` writer - Next Command Select"] +pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; +impl<'a, REG> NextW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { + self.variant(Next::NoNextCmdTerminateOnFinish) + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd1_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd1Next) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext2) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext3) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext4) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext5) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext6) + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd7_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd7Next) + } +} +impl R { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&self) -> CmpenR { + CmpenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&self) -> WaitTrigR { + WaitTrigR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&self) -> LwiR { + LwiR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&self) -> StsR { + StsR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&self) -> AvgsR { + AvgsR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&self) -> LoopR { + LoopR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&self) -> NextR { + NextR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&mut self) -> CmpenW { + CmpenW::new(self, 0) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&mut self) -> WaitTrigW { + WaitTrigW::new(self, 2) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&mut self) -> LwiW { + LwiW::new(self, 7) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&mut self) -> StsW { + StsW::new(self, 8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&mut self) -> AvgsW { + AvgsW::new(self, 12) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&mut self) -> LoopW { + LoopW::new(self, 16) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&mut self) -> NextW { + NextW::new(self, 24) + } +} +#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdh4Spec; +impl crate::RegisterSpec for Cmdh4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdh4::R`](R) reader structure"] +impl crate::Readable for Cmdh4Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdh4::W`](W) writer structure"] +impl crate::Writable for Cmdh4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDH4 to value 0"] +impl crate::Resettable for Cmdh4Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh5.rs b/mcxa276-pac/src/adc0/cmdh5.rs new file mode 100644 index 000000000..eac28578c --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdh5.rs @@ -0,0 +1,900 @@ +#[doc = "Register `CMDH5` reader"] +pub type R = crate::R; +#[doc = "Register `CMDH5` writer"] +pub type W = crate::W; +#[doc = "Compare Function Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpen { + #[doc = "0: Compare disabled."] + DisabledAlwaysStoreResult = 0, + #[doc = "2: Compare enabled. Store on true."] + CompareResultStoreIfTrue = 2, + #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpen { + type Ux = u8; +} +impl crate::IsEnum for Cmpen {} +#[doc = "Field `CMPEN` reader - Compare Function Enable"] +pub type CmpenR = crate::FieldReader; +impl CmpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpen::DisabledAlwaysStoreResult), + 2 => Some(Cmpen::CompareResultStoreIfTrue), + 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), + _ => None, + } + } + #[doc = "Compare disabled."] + #[inline(always)] + pub fn is_disabled_always_store_result(&self) -> bool { + *self == Cmpen::DisabledAlwaysStoreResult + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn is_compare_result_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultStoreIfTrue + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue + } +} +#[doc = "Field `CMPEN` writer - Compare Function Enable"] +pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; +impl<'a, REG> CmpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Compare disabled."] + #[inline(always)] + pub fn disabled_always_store_result(self) -> &'a mut crate::W { + self.variant(Cmpen::DisabledAlwaysStoreResult) + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn compare_result_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultStoreIfTrue) + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) + } +} +#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WaitTrig { + #[doc = "0: This command will be automatically executed."] + Disabled = 0, + #[doc = "1: The active trigger must be asserted again before executing this command."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WaitTrig) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] +pub type WaitTrigR = crate::BitReader; +impl WaitTrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WaitTrig { + match self.bits { + false => WaitTrig::Disabled, + true => WaitTrig::Enabled, + } + } + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WaitTrig::Disabled + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WaitTrig::Enabled + } +} +#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] +pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; +impl<'a, REG> WaitTrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Disabled) + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Enabled) + } +} +#[doc = "Loop with Increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lwi { + #[doc = "0: Auto channel increment disabled"] + Disabled = 0, + #[doc = "1: Auto channel increment enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lwi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LWI` reader - Loop with Increment"] +pub type LwiR = crate::BitReader; +impl LwiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lwi { + match self.bits { + false => Lwi::Disabled, + true => Lwi::Enabled, + } + } + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lwi::Disabled + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lwi::Enabled + } +} +#[doc = "Field `LWI` writer - Loop with Increment"] +pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; +impl<'a, REG> LwiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lwi::Disabled) + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lwi::Enabled) + } +} +#[doc = "Sample Time Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sts { + #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0, + #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + Sample5p5 = 1, + #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + Sample7p5 = 2, + #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + Sample11p5 = 3, + #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + Sample19p5 = 4, + #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + Sample35p5 = 5, + #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + Sample67p5 = 6, + #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + Sample131p5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sts) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sts { + type Ux = u8; +} +impl crate::IsEnum for Sts {} +#[doc = "Field `STS` reader - Sample Time Select"] +pub type StsR = crate::FieldReader; +impl StsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sts { + match self.bits { + 0 => Sts::Sample3p5, + 1 => Sts::Sample5p5, + 2 => Sts::Sample7p5, + 3 => Sts::Sample11p5, + 4 => Sts::Sample19p5, + 5 => Sts::Sample35p5, + 6 => Sts::Sample67p5, + 7 => Sts::Sample131p5, + _ => unreachable!(), + } + } + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn is_sample_3p5(&self) -> bool { + *self == Sts::Sample3p5 + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_5p5(&self) -> bool { + *self == Sts::Sample5p5 + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_7p5(&self) -> bool { + *self == Sts::Sample7p5 + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_11p5(&self) -> bool { + *self == Sts::Sample11p5 + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_19p5(&self) -> bool { + *self == Sts::Sample19p5 + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_35p5(&self) -> bool { + *self == Sts::Sample35p5 + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_67p5(&self) -> bool { + *self == Sts::Sample67p5 + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_131p5(&self) -> bool { + *self == Sts::Sample131p5 + } +} +#[doc = "Field `STS` writer - Sample Time Select"] +pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; +impl<'a, REG> StsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn sample_3p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample3p5) + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_5p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample5p5) + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_7p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample7p5) + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_11p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample11p5) + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_19p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample19p5) + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_35p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample35p5) + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_67p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample67p5) + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_131p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample131p5) + } +} +#[doc = "Hardware Average Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Avgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Avgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Avgs { + type Ux = u8; +} +impl crate::IsEnum for Avgs {} +#[doc = "Field `AVGS` reader - Hardware Average Select"] +pub type AvgsR = crate::FieldReader; +impl AvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Avgs::NoAverage), + 1 => Some(Avgs::Average2), + 2 => Some(Avgs::Average4), + 3 => Some(Avgs::Average8), + 4 => Some(Avgs::Average16), + 5 => Some(Avgs::Average32), + 6 => Some(Avgs::Average64), + 7 => Some(Avgs::Average128), + 8 => Some(Avgs::Average256), + 9 => Some(Avgs::Average512), + 10 => Some(Avgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == Avgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == Avgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == Avgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == Avgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == Avgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == Avgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == Avgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == Avgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == Avgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == Avgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == Avgs::Average1024 + } +} +#[doc = "Field `AVGS` writer - Hardware Average Select"] +pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; +impl<'a, REG> AvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(Avgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(Avgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(Avgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(Avgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(Avgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(Avgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(Avgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(Avgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(Avgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(Avgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(Avgs::Average1024) + } +} +#[doc = "Loop Count Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loop { + #[doc = "0: Looping not enabled. Command executes 1 time."] + CmdExec1x = 0, + #[doc = "1: Loop 1 time. Command executes 2 times."] + CmdExec2x = 1, + #[doc = "2: Loop 2 times. Command executes 3 times."] + CmdExec3x = 2, + #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes3 = 3, + #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes4 = 4, + #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes5 = 5, + #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes6 = 6, + #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes7 = 7, + #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes8 = 8, + #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes9 = 9, + #[doc = "15: Loop 15 times. Command executes 16 times."] + CmdExec15x = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loop { + type Ux = u8; +} +impl crate::IsEnum for Loop {} +#[doc = "Field `LOOP` reader - Loop Count Select"] +pub type LoopR = crate::FieldReader; +impl LoopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loop::CmdExec1x), + 1 => Some(Loop::CmdExec2x), + 2 => Some(Loop::CmdExec3x), + 3 => Some(Loop::CmdExecutesCorrespondingTimes3), + 4 => Some(Loop::CmdExecutesCorrespondingTimes4), + 5 => Some(Loop::CmdExecutesCorrespondingTimes5), + 6 => Some(Loop::CmdExecutesCorrespondingTimes6), + 7 => Some(Loop::CmdExecutesCorrespondingTimes7), + 8 => Some(Loop::CmdExecutesCorrespondingTimes8), + 9 => Some(Loop::CmdExecutesCorrespondingTimes9), + 15 => Some(Loop::CmdExec15x), + _ => None, + } + } + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn is_cmd_exec_1x(&self) -> bool { + *self == Loop::CmdExec1x + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn is_cmd_exec_2x(&self) -> bool { + *self == Loop::CmdExec2x + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn is_cmd_exec_3x(&self) -> bool { + *self == Loop::CmdExec3x + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes3 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes4 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes5 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes6 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes7 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes8 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes9 + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn is_cmd_exec_15x(&self) -> bool { + *self == Loop::CmdExec15x + } +} +#[doc = "Field `LOOP` writer - Loop Count Select"] +pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; +impl<'a, REG> LoopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn cmd_exec_1x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec1x) + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn cmd_exec_2x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec2x) + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn cmd_exec_3x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec3x) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes3) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes4) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes5) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes6) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes7) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes8) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes9) + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn cmd_exec_15x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec15x) + } +} +#[doc = "Next Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Next { + #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + NoNextCmdTerminateOnFinish = 0, + #[doc = "1: Select CMD1 command buffer register as next command."] + DoCmd1Next = 1, + #[doc = "2: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext2 = 2, + #[doc = "3: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext3 = 3, + #[doc = "4: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext4 = 4, + #[doc = "5: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext5 = 5, + #[doc = "6: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext6 = 6, + #[doc = "7: Select CMD7 command buffer register as next command."] + DoCmd7Next = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Next) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Next { + type Ux = u8; +} +impl crate::IsEnum for Next {} +#[doc = "Field `NEXT` reader - Next Command Select"] +pub type NextR = crate::FieldReader; +impl NextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Next { + match self.bits { + 0 => Next::NoNextCmdTerminateOnFinish, + 1 => Next::DoCmd1Next, + 2 => Next::DoCorrespondingCmdNext2, + 3 => Next::DoCorrespondingCmdNext3, + 4 => Next::DoCorrespondingCmdNext4, + 5 => Next::DoCorrespondingCmdNext5, + 6 => Next::DoCorrespondingCmdNext6, + 7 => Next::DoCmd7Next, + _ => unreachable!(), + } + } + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { + *self == Next::NoNextCmdTerminateOnFinish + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd1_next(&self) -> bool { + *self == Next::DoCmd1Next + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_2(&self) -> bool { + *self == Next::DoCorrespondingCmdNext2 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_3(&self) -> bool { + *self == Next::DoCorrespondingCmdNext3 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_4(&self) -> bool { + *self == Next::DoCorrespondingCmdNext4 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_5(&self) -> bool { + *self == Next::DoCorrespondingCmdNext5 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_6(&self) -> bool { + *self == Next::DoCorrespondingCmdNext6 + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd7_next(&self) -> bool { + *self == Next::DoCmd7Next + } +} +#[doc = "Field `NEXT` writer - Next Command Select"] +pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; +impl<'a, REG> NextW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { + self.variant(Next::NoNextCmdTerminateOnFinish) + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd1_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd1Next) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext2) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext3) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext4) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext5) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext6) + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd7_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd7Next) + } +} +impl R { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&self) -> CmpenR { + CmpenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&self) -> WaitTrigR { + WaitTrigR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&self) -> LwiR { + LwiR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&self) -> StsR { + StsR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&self) -> AvgsR { + AvgsR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&self) -> LoopR { + LoopR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&self) -> NextR { + NextR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&mut self) -> CmpenW { + CmpenW::new(self, 0) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&mut self) -> WaitTrigW { + WaitTrigW::new(self, 2) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&mut self) -> LwiW { + LwiW::new(self, 7) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&mut self) -> StsW { + StsW::new(self, 8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&mut self) -> AvgsW { + AvgsW::new(self, 12) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&mut self) -> LoopW { + LoopW::new(self, 16) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&mut self) -> NextW { + NextW::new(self, 24) + } +} +#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdh5Spec; +impl crate::RegisterSpec for Cmdh5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdh5::R`](R) reader structure"] +impl crate::Readable for Cmdh5Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdh5::W`](W) writer structure"] +impl crate::Writable for Cmdh5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDH5 to value 0"] +impl crate::Resettable for Cmdh5Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh6.rs b/mcxa276-pac/src/adc0/cmdh6.rs new file mode 100644 index 000000000..c1e7d09a6 --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdh6.rs @@ -0,0 +1,900 @@ +#[doc = "Register `CMDH6` reader"] +pub type R = crate::R; +#[doc = "Register `CMDH6` writer"] +pub type W = crate::W; +#[doc = "Compare Function Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpen { + #[doc = "0: Compare disabled."] + DisabledAlwaysStoreResult = 0, + #[doc = "2: Compare enabled. Store on true."] + CompareResultStoreIfTrue = 2, + #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpen { + type Ux = u8; +} +impl crate::IsEnum for Cmpen {} +#[doc = "Field `CMPEN` reader - Compare Function Enable"] +pub type CmpenR = crate::FieldReader; +impl CmpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpen::DisabledAlwaysStoreResult), + 2 => Some(Cmpen::CompareResultStoreIfTrue), + 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), + _ => None, + } + } + #[doc = "Compare disabled."] + #[inline(always)] + pub fn is_disabled_always_store_result(&self) -> bool { + *self == Cmpen::DisabledAlwaysStoreResult + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn is_compare_result_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultStoreIfTrue + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue + } +} +#[doc = "Field `CMPEN` writer - Compare Function Enable"] +pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; +impl<'a, REG> CmpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Compare disabled."] + #[inline(always)] + pub fn disabled_always_store_result(self) -> &'a mut crate::W { + self.variant(Cmpen::DisabledAlwaysStoreResult) + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn compare_result_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultStoreIfTrue) + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) + } +} +#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WaitTrig { + #[doc = "0: This command will be automatically executed."] + Disabled = 0, + #[doc = "1: The active trigger must be asserted again before executing this command."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WaitTrig) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] +pub type WaitTrigR = crate::BitReader; +impl WaitTrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WaitTrig { + match self.bits { + false => WaitTrig::Disabled, + true => WaitTrig::Enabled, + } + } + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WaitTrig::Disabled + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WaitTrig::Enabled + } +} +#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] +pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; +impl<'a, REG> WaitTrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Disabled) + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Enabled) + } +} +#[doc = "Loop with Increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lwi { + #[doc = "0: Auto channel increment disabled"] + Disabled = 0, + #[doc = "1: Auto channel increment enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lwi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LWI` reader - Loop with Increment"] +pub type LwiR = crate::BitReader; +impl LwiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lwi { + match self.bits { + false => Lwi::Disabled, + true => Lwi::Enabled, + } + } + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lwi::Disabled + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lwi::Enabled + } +} +#[doc = "Field `LWI` writer - Loop with Increment"] +pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; +impl<'a, REG> LwiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lwi::Disabled) + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lwi::Enabled) + } +} +#[doc = "Sample Time Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sts { + #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0, + #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + Sample5p5 = 1, + #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + Sample7p5 = 2, + #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + Sample11p5 = 3, + #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + Sample19p5 = 4, + #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + Sample35p5 = 5, + #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + Sample67p5 = 6, + #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + Sample131p5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sts) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sts { + type Ux = u8; +} +impl crate::IsEnum for Sts {} +#[doc = "Field `STS` reader - Sample Time Select"] +pub type StsR = crate::FieldReader; +impl StsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sts { + match self.bits { + 0 => Sts::Sample3p5, + 1 => Sts::Sample5p5, + 2 => Sts::Sample7p5, + 3 => Sts::Sample11p5, + 4 => Sts::Sample19p5, + 5 => Sts::Sample35p5, + 6 => Sts::Sample67p5, + 7 => Sts::Sample131p5, + _ => unreachable!(), + } + } + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn is_sample_3p5(&self) -> bool { + *self == Sts::Sample3p5 + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_5p5(&self) -> bool { + *self == Sts::Sample5p5 + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_7p5(&self) -> bool { + *self == Sts::Sample7p5 + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_11p5(&self) -> bool { + *self == Sts::Sample11p5 + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_19p5(&self) -> bool { + *self == Sts::Sample19p5 + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_35p5(&self) -> bool { + *self == Sts::Sample35p5 + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_67p5(&self) -> bool { + *self == Sts::Sample67p5 + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_131p5(&self) -> bool { + *self == Sts::Sample131p5 + } +} +#[doc = "Field `STS` writer - Sample Time Select"] +pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; +impl<'a, REG> StsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn sample_3p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample3p5) + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_5p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample5p5) + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_7p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample7p5) + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_11p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample11p5) + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_19p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample19p5) + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_35p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample35p5) + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_67p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample67p5) + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_131p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample131p5) + } +} +#[doc = "Hardware Average Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Avgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Avgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Avgs { + type Ux = u8; +} +impl crate::IsEnum for Avgs {} +#[doc = "Field `AVGS` reader - Hardware Average Select"] +pub type AvgsR = crate::FieldReader; +impl AvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Avgs::NoAverage), + 1 => Some(Avgs::Average2), + 2 => Some(Avgs::Average4), + 3 => Some(Avgs::Average8), + 4 => Some(Avgs::Average16), + 5 => Some(Avgs::Average32), + 6 => Some(Avgs::Average64), + 7 => Some(Avgs::Average128), + 8 => Some(Avgs::Average256), + 9 => Some(Avgs::Average512), + 10 => Some(Avgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == Avgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == Avgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == Avgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == Avgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == Avgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == Avgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == Avgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == Avgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == Avgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == Avgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == Avgs::Average1024 + } +} +#[doc = "Field `AVGS` writer - Hardware Average Select"] +pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; +impl<'a, REG> AvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(Avgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(Avgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(Avgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(Avgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(Avgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(Avgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(Avgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(Avgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(Avgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(Avgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(Avgs::Average1024) + } +} +#[doc = "Loop Count Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loop { + #[doc = "0: Looping not enabled. Command executes 1 time."] + CmdExec1x = 0, + #[doc = "1: Loop 1 time. Command executes 2 times."] + CmdExec2x = 1, + #[doc = "2: Loop 2 times. Command executes 3 times."] + CmdExec3x = 2, + #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes3 = 3, + #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes4 = 4, + #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes5 = 5, + #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes6 = 6, + #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes7 = 7, + #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes8 = 8, + #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes9 = 9, + #[doc = "15: Loop 15 times. Command executes 16 times."] + CmdExec15x = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loop { + type Ux = u8; +} +impl crate::IsEnum for Loop {} +#[doc = "Field `LOOP` reader - Loop Count Select"] +pub type LoopR = crate::FieldReader; +impl LoopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loop::CmdExec1x), + 1 => Some(Loop::CmdExec2x), + 2 => Some(Loop::CmdExec3x), + 3 => Some(Loop::CmdExecutesCorrespondingTimes3), + 4 => Some(Loop::CmdExecutesCorrespondingTimes4), + 5 => Some(Loop::CmdExecutesCorrespondingTimes5), + 6 => Some(Loop::CmdExecutesCorrespondingTimes6), + 7 => Some(Loop::CmdExecutesCorrespondingTimes7), + 8 => Some(Loop::CmdExecutesCorrespondingTimes8), + 9 => Some(Loop::CmdExecutesCorrespondingTimes9), + 15 => Some(Loop::CmdExec15x), + _ => None, + } + } + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn is_cmd_exec_1x(&self) -> bool { + *self == Loop::CmdExec1x + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn is_cmd_exec_2x(&self) -> bool { + *self == Loop::CmdExec2x + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn is_cmd_exec_3x(&self) -> bool { + *self == Loop::CmdExec3x + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes3 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes4 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes5 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes6 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes7 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes8 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes9 + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn is_cmd_exec_15x(&self) -> bool { + *self == Loop::CmdExec15x + } +} +#[doc = "Field `LOOP` writer - Loop Count Select"] +pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; +impl<'a, REG> LoopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn cmd_exec_1x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec1x) + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn cmd_exec_2x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec2x) + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn cmd_exec_3x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec3x) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes3) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes4) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes5) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes6) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes7) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes8) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes9) + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn cmd_exec_15x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec15x) + } +} +#[doc = "Next Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Next { + #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + NoNextCmdTerminateOnFinish = 0, + #[doc = "1: Select CMD1 command buffer register as next command."] + DoCmd1Next = 1, + #[doc = "2: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext2 = 2, + #[doc = "3: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext3 = 3, + #[doc = "4: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext4 = 4, + #[doc = "5: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext5 = 5, + #[doc = "6: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext6 = 6, + #[doc = "7: Select CMD7 command buffer register as next command."] + DoCmd7Next = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Next) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Next { + type Ux = u8; +} +impl crate::IsEnum for Next {} +#[doc = "Field `NEXT` reader - Next Command Select"] +pub type NextR = crate::FieldReader; +impl NextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Next { + match self.bits { + 0 => Next::NoNextCmdTerminateOnFinish, + 1 => Next::DoCmd1Next, + 2 => Next::DoCorrespondingCmdNext2, + 3 => Next::DoCorrespondingCmdNext3, + 4 => Next::DoCorrespondingCmdNext4, + 5 => Next::DoCorrespondingCmdNext5, + 6 => Next::DoCorrespondingCmdNext6, + 7 => Next::DoCmd7Next, + _ => unreachable!(), + } + } + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { + *self == Next::NoNextCmdTerminateOnFinish + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd1_next(&self) -> bool { + *self == Next::DoCmd1Next + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_2(&self) -> bool { + *self == Next::DoCorrespondingCmdNext2 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_3(&self) -> bool { + *self == Next::DoCorrespondingCmdNext3 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_4(&self) -> bool { + *self == Next::DoCorrespondingCmdNext4 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_5(&self) -> bool { + *self == Next::DoCorrespondingCmdNext5 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_6(&self) -> bool { + *self == Next::DoCorrespondingCmdNext6 + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd7_next(&self) -> bool { + *self == Next::DoCmd7Next + } +} +#[doc = "Field `NEXT` writer - Next Command Select"] +pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; +impl<'a, REG> NextW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { + self.variant(Next::NoNextCmdTerminateOnFinish) + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd1_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd1Next) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext2) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext3) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext4) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext5) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext6) + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd7_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd7Next) + } +} +impl R { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&self) -> CmpenR { + CmpenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&self) -> WaitTrigR { + WaitTrigR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&self) -> LwiR { + LwiR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&self) -> StsR { + StsR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&self) -> AvgsR { + AvgsR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&self) -> LoopR { + LoopR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&self) -> NextR { + NextR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&mut self) -> CmpenW { + CmpenW::new(self, 0) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&mut self) -> WaitTrigW { + WaitTrigW::new(self, 2) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&mut self) -> LwiW { + LwiW::new(self, 7) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&mut self) -> StsW { + StsW::new(self, 8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&mut self) -> AvgsW { + AvgsW::new(self, 12) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&mut self) -> LoopW { + LoopW::new(self, 16) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&mut self) -> NextW { + NextW::new(self, 24) + } +} +#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdh6Spec; +impl crate::RegisterSpec for Cmdh6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdh6::R`](R) reader structure"] +impl crate::Readable for Cmdh6Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdh6::W`](W) writer structure"] +impl crate::Writable for Cmdh6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDH6 to value 0"] +impl crate::Resettable for Cmdh6Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh7.rs b/mcxa276-pac/src/adc0/cmdh7.rs new file mode 100644 index 000000000..696d7fdbd --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdh7.rs @@ -0,0 +1,900 @@ +#[doc = "Register `CMDH7` reader"] +pub type R = crate::R; +#[doc = "Register `CMDH7` writer"] +pub type W = crate::W; +#[doc = "Compare Function Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpen { + #[doc = "0: Compare disabled."] + DisabledAlwaysStoreResult = 0, + #[doc = "2: Compare enabled. Store on true."] + CompareResultStoreIfTrue = 2, + #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpen { + type Ux = u8; +} +impl crate::IsEnum for Cmpen {} +#[doc = "Field `CMPEN` reader - Compare Function Enable"] +pub type CmpenR = crate::FieldReader; +impl CmpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpen::DisabledAlwaysStoreResult), + 2 => Some(Cmpen::CompareResultStoreIfTrue), + 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), + _ => None, + } + } + #[doc = "Compare disabled."] + #[inline(always)] + pub fn is_disabled_always_store_result(&self) -> bool { + *self == Cmpen::DisabledAlwaysStoreResult + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn is_compare_result_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultStoreIfTrue + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { + *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue + } +} +#[doc = "Field `CMPEN` writer - Compare Function Enable"] +pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; +impl<'a, REG> CmpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Compare disabled."] + #[inline(always)] + pub fn disabled_always_store_result(self) -> &'a mut crate::W { + self.variant(Cmpen::DisabledAlwaysStoreResult) + } + #[doc = "Compare enabled. Store on true."] + #[inline(always)] + pub fn compare_result_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultStoreIfTrue) + } + #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] + #[inline(always)] + pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { + self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) + } +} +#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WaitTrig { + #[doc = "0: This command will be automatically executed."] + Disabled = 0, + #[doc = "1: The active trigger must be asserted again before executing this command."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WaitTrig) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] +pub type WaitTrigR = crate::BitReader; +impl WaitTrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WaitTrig { + match self.bits { + false => WaitTrig::Disabled, + true => WaitTrig::Enabled, + } + } + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WaitTrig::Disabled + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WaitTrig::Enabled + } +} +#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] +pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; +impl<'a, REG> WaitTrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This command will be automatically executed."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Disabled) + } + #[doc = "The active trigger must be asserted again before executing this command."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WaitTrig::Enabled) + } +} +#[doc = "Loop with Increment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lwi { + #[doc = "0: Auto channel increment disabled"] + Disabled = 0, + #[doc = "1: Auto channel increment enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lwi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LWI` reader - Loop with Increment"] +pub type LwiR = crate::BitReader; +impl LwiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lwi { + match self.bits { + false => Lwi::Disabled, + true => Lwi::Enabled, + } + } + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lwi::Disabled + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lwi::Enabled + } +} +#[doc = "Field `LWI` writer - Loop with Increment"] +pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; +impl<'a, REG> LwiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto channel increment disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lwi::Disabled) + } + #[doc = "Auto channel increment enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lwi::Enabled) + } +} +#[doc = "Sample Time Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sts { + #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0, + #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + Sample5p5 = 1, + #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + Sample7p5 = 2, + #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + Sample11p5 = 3, + #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + Sample19p5 = 4, + #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + Sample35p5 = 5, + #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + Sample67p5 = 6, + #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + Sample131p5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sts) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sts { + type Ux = u8; +} +impl crate::IsEnum for Sts {} +#[doc = "Field `STS` reader - Sample Time Select"] +pub type StsR = crate::FieldReader; +impl StsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sts { + match self.bits { + 0 => Sts::Sample3p5, + 1 => Sts::Sample5p5, + 2 => Sts::Sample7p5, + 3 => Sts::Sample11p5, + 4 => Sts::Sample19p5, + 5 => Sts::Sample35p5, + 6 => Sts::Sample67p5, + 7 => Sts::Sample131p5, + _ => unreachable!(), + } + } + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn is_sample_3p5(&self) -> bool { + *self == Sts::Sample3p5 + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_5p5(&self) -> bool { + *self == Sts::Sample5p5 + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_7p5(&self) -> bool { + *self == Sts::Sample7p5 + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_11p5(&self) -> bool { + *self == Sts::Sample11p5 + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_19p5(&self) -> bool { + *self == Sts::Sample19p5 + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_35p5(&self) -> bool { + *self == Sts::Sample35p5 + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_67p5(&self) -> bool { + *self == Sts::Sample67p5 + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn is_sample_131p5(&self) -> bool { + *self == Sts::Sample131p5 + } +} +#[doc = "Field `STS` writer - Sample Time Select"] +pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; +impl<'a, REG> StsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Minimum sample time of 3.5 ADCK cycles."] + #[inline(always)] + pub fn sample_3p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample3p5) + } + #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_5p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample5p5) + } + #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_7p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample7p5) + } + #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_11p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample11p5) + } + #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_19p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample19p5) + } + #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_35p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample35p5) + } + #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_67p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample67p5) + } + #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] + #[inline(always)] + pub fn sample_131p5(self) -> &'a mut crate::W { + self.variant(Sts::Sample131p5) + } +} +#[doc = "Hardware Average Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Avgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Avgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Avgs { + type Ux = u8; +} +impl crate::IsEnum for Avgs {} +#[doc = "Field `AVGS` reader - Hardware Average Select"] +pub type AvgsR = crate::FieldReader; +impl AvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Avgs::NoAverage), + 1 => Some(Avgs::Average2), + 2 => Some(Avgs::Average4), + 3 => Some(Avgs::Average8), + 4 => Some(Avgs::Average16), + 5 => Some(Avgs::Average32), + 6 => Some(Avgs::Average64), + 7 => Some(Avgs::Average128), + 8 => Some(Avgs::Average256), + 9 => Some(Avgs::Average512), + 10 => Some(Avgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == Avgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == Avgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == Avgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == Avgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == Avgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == Avgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == Avgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == Avgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == Avgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == Avgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == Avgs::Average1024 + } +} +#[doc = "Field `AVGS` writer - Hardware Average Select"] +pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; +impl<'a, REG> AvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(Avgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(Avgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(Avgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(Avgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(Avgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(Avgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(Avgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(Avgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(Avgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(Avgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(Avgs::Average1024) + } +} +#[doc = "Loop Count Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loop { + #[doc = "0: Looping not enabled. Command executes 1 time."] + CmdExec1x = 0, + #[doc = "1: Loop 1 time. Command executes 2 times."] + CmdExec2x = 1, + #[doc = "2: Loop 2 times. Command executes 3 times."] + CmdExec3x = 2, + #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes3 = 3, + #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes4 = 4, + #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes5 = 5, + #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes6 = 6, + #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes7 = 7, + #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes8 = 8, + #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] + CmdExecutesCorrespondingTimes9 = 9, + #[doc = "15: Loop 15 times. Command executes 16 times."] + CmdExec15x = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loop { + type Ux = u8; +} +impl crate::IsEnum for Loop {} +#[doc = "Field `LOOP` reader - Loop Count Select"] +pub type LoopR = crate::FieldReader; +impl LoopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loop::CmdExec1x), + 1 => Some(Loop::CmdExec2x), + 2 => Some(Loop::CmdExec3x), + 3 => Some(Loop::CmdExecutesCorrespondingTimes3), + 4 => Some(Loop::CmdExecutesCorrespondingTimes4), + 5 => Some(Loop::CmdExecutesCorrespondingTimes5), + 6 => Some(Loop::CmdExecutesCorrespondingTimes6), + 7 => Some(Loop::CmdExecutesCorrespondingTimes7), + 8 => Some(Loop::CmdExecutesCorrespondingTimes8), + 9 => Some(Loop::CmdExecutesCorrespondingTimes9), + 15 => Some(Loop::CmdExec15x), + _ => None, + } + } + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn is_cmd_exec_1x(&self) -> bool { + *self == Loop::CmdExec1x + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn is_cmd_exec_2x(&self) -> bool { + *self == Loop::CmdExec2x + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn is_cmd_exec_3x(&self) -> bool { + *self == Loop::CmdExec3x + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes3 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes4 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes5 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes6 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes7 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes8 + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { + *self == Loop::CmdExecutesCorrespondingTimes9 + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn is_cmd_exec_15x(&self) -> bool { + *self == Loop::CmdExec15x + } +} +#[doc = "Field `LOOP` writer - Loop Count Select"] +pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; +impl<'a, REG> LoopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Looping not enabled. Command executes 1 time."] + #[inline(always)] + pub fn cmd_exec_1x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec1x) + } + #[doc = "Loop 1 time. Command executes 2 times."] + #[inline(always)] + pub fn cmd_exec_2x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec2x) + } + #[doc = "Loop 2 times. Command executes 3 times."] + #[inline(always)] + pub fn cmd_exec_3x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec3x) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes3) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes4) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes5) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes6) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes7) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes8) + } + #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] + #[inline(always)] + pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { + self.variant(Loop::CmdExecutesCorrespondingTimes9) + } + #[doc = "Loop 15 times. Command executes 16 times."] + #[inline(always)] + pub fn cmd_exec_15x(self) -> &'a mut crate::W { + self.variant(Loop::CmdExec15x) + } +} +#[doc = "Next Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Next { + #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + NoNextCmdTerminateOnFinish = 0, + #[doc = "1: Select CMD1 command buffer register as next command."] + DoCmd1Next = 1, + #[doc = "2: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext2 = 2, + #[doc = "3: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext3 = 3, + #[doc = "4: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext4 = 4, + #[doc = "5: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext5 = 5, + #[doc = "6: Select corresponding CMD command buffer register as next command"] + DoCorrespondingCmdNext6 = 6, + #[doc = "7: Select CMD7 command buffer register as next command."] + DoCmd7Next = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Next) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Next { + type Ux = u8; +} +impl crate::IsEnum for Next {} +#[doc = "Field `NEXT` reader - Next Command Select"] +pub type NextR = crate::FieldReader; +impl NextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Next { + match self.bits { + 0 => Next::NoNextCmdTerminateOnFinish, + 1 => Next::DoCmd1Next, + 2 => Next::DoCorrespondingCmdNext2, + 3 => Next::DoCorrespondingCmdNext3, + 4 => Next::DoCorrespondingCmdNext4, + 5 => Next::DoCorrespondingCmdNext5, + 6 => Next::DoCorrespondingCmdNext6, + 7 => Next::DoCmd7Next, + _ => unreachable!(), + } + } + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { + *self == Next::NoNextCmdTerminateOnFinish + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd1_next(&self) -> bool { + *self == Next::DoCmd1Next + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_2(&self) -> bool { + *self == Next::DoCorrespondingCmdNext2 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_3(&self) -> bool { + *self == Next::DoCorrespondingCmdNext3 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_4(&self) -> bool { + *self == Next::DoCorrespondingCmdNext4 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_5(&self) -> bool { + *self == Next::DoCorrespondingCmdNext5 + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn is_do_corresponding_cmd_next_6(&self) -> bool { + *self == Next::DoCorrespondingCmdNext6 + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn is_do_cmd7_next(&self) -> bool { + *self == Next::DoCmd7Next + } +} +#[doc = "Field `NEXT` writer - Next Command Select"] +pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; +impl<'a, REG> NextW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] + #[inline(always)] + pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { + self.variant(Next::NoNextCmdTerminateOnFinish) + } + #[doc = "Select CMD1 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd1_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd1Next) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext2) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext3) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext4) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext5) + } + #[doc = "Select corresponding CMD command buffer register as next command"] + #[inline(always)] + pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { + self.variant(Next::DoCorrespondingCmdNext6) + } + #[doc = "Select CMD7 command buffer register as next command."] + #[inline(always)] + pub fn do_cmd7_next(self) -> &'a mut crate::W { + self.variant(Next::DoCmd7Next) + } +} +impl R { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&self) -> CmpenR { + CmpenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&self) -> WaitTrigR { + WaitTrigR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&self) -> LwiR { + LwiR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&self) -> StsR { + StsR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&self) -> AvgsR { + AvgsR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&self) -> LoopR { + LoopR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&self) -> NextR { + NextR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Compare Function Enable"] + #[inline(always)] + pub fn cmpen(&mut self) -> CmpenW { + CmpenW::new(self, 0) + } + #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] + #[inline(always)] + pub fn wait_trig(&mut self) -> WaitTrigW { + WaitTrigW::new(self, 2) + } + #[doc = "Bit 7 - Loop with Increment"] + #[inline(always)] + pub fn lwi(&mut self) -> LwiW { + LwiW::new(self, 7) + } + #[doc = "Bits 8:10 - Sample Time Select"] + #[inline(always)] + pub fn sts(&mut self) -> StsW { + StsW::new(self, 8) + } + #[doc = "Bits 12:15 - Hardware Average Select"] + #[inline(always)] + pub fn avgs(&mut self) -> AvgsW { + AvgsW::new(self, 12) + } + #[doc = "Bits 16:19 - Loop Count Select"] + #[inline(always)] + pub fn loop_(&mut self) -> LoopW { + LoopW::new(self, 16) + } + #[doc = "Bits 24:26 - Next Command Select"] + #[inline(always)] + pub fn next(&mut self) -> NextW { + NextW::new(self, 24) + } +} +#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdh7Spec; +impl crate::RegisterSpec for Cmdh7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdh7::R`](R) reader structure"] +impl crate::Readable for Cmdh7Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdh7::W`](W) writer structure"] +impl crate::Writable for Cmdh7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDH7 to value 0"] +impl crate::Resettable for Cmdh7Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl1.rs b/mcxa276-pac/src/adc0/cmdl1.rs new file mode 100644 index 000000000..e11d25b2b --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdl1.rs @@ -0,0 +1,331 @@ +#[doc = "Register `CMDL1` reader"] +pub type R = crate::R; +#[doc = "Register `CMDL1` writer"] +pub type W = crate::W; +#[doc = "Input Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Adch { + #[doc = "0: Select CH0A."] + SelectCh0 = 0, + #[doc = "1: Select CH1A."] + SelectCh1 = 1, + #[doc = "2: Select CH2A."] + SelectCh2 = 2, + #[doc = "3: Select CH3A."] + SelectCh3 = 3, + #[doc = "4: Select corresponding channel CHnA."] + SelectCorrespondingChannel4 = 4, + #[doc = "5: Select corresponding channel CHnA."] + SelectCorrespondingChannel5 = 5, + #[doc = "6: Select corresponding channel CHnA."] + SelectCorrespondingChannel6 = 6, + #[doc = "7: Select corresponding channel CHnA."] + SelectCorrespondingChannel7 = 7, + #[doc = "8: Select corresponding channel CHnA."] + SelectCorrespondingChannel8 = 8, + #[doc = "9: Select corresponding channel CHnA."] + SelectCorrespondingChannel9 = 9, + #[doc = "30: Select CH30A."] + SelectCh30 = 30, + #[doc = "31: Select CH31A."] + SelectCh31 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Adch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Adch { + type Ux = u8; +} +impl crate::IsEnum for Adch {} +#[doc = "Field `ADCH` reader - Input Channel Select"] +pub type AdchR = crate::FieldReader; +impl AdchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Adch::SelectCh0), + 1 => Some(Adch::SelectCh1), + 2 => Some(Adch::SelectCh2), + 3 => Some(Adch::SelectCh3), + 4 => Some(Adch::SelectCorrespondingChannel4), + 5 => Some(Adch::SelectCorrespondingChannel5), + 6 => Some(Adch::SelectCorrespondingChannel6), + 7 => Some(Adch::SelectCorrespondingChannel7), + 8 => Some(Adch::SelectCorrespondingChannel8), + 9 => Some(Adch::SelectCorrespondingChannel9), + 30 => Some(Adch::SelectCh30), + 31 => Some(Adch::SelectCh31), + _ => None, + } + } + #[doc = "Select CH0A."] + #[inline(always)] + pub fn is_select_ch0(&self) -> bool { + *self == Adch::SelectCh0 + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn is_select_ch1(&self) -> bool { + *self == Adch::SelectCh1 + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn is_select_ch2(&self) -> bool { + *self == Adch::SelectCh2 + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn is_select_ch3(&self) -> bool { + *self == Adch::SelectCh3 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_4(&self) -> bool { + *self == Adch::SelectCorrespondingChannel4 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_5(&self) -> bool { + *self == Adch::SelectCorrespondingChannel5 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_6(&self) -> bool { + *self == Adch::SelectCorrespondingChannel6 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_7(&self) -> bool { + *self == Adch::SelectCorrespondingChannel7 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_8(&self) -> bool { + *self == Adch::SelectCorrespondingChannel8 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_9(&self) -> bool { + *self == Adch::SelectCorrespondingChannel9 + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn is_select_ch30(&self) -> bool { + *self == Adch::SelectCh30 + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn is_select_ch31(&self) -> bool { + *self == Adch::SelectCh31 + } +} +#[doc = "Field `ADCH` writer - Input Channel Select"] +pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; +impl<'a, REG> AdchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select CH0A."] + #[inline(always)] + pub fn select_ch0(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh0) + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn select_ch1(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh1) + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn select_ch2(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh2) + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn select_ch3(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh3) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel4) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel5) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel6) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel7) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel8) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel9) + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn select_ch30(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh30) + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn select_ch31(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh31) + } +} +#[doc = "Conversion Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctype { + #[doc = "0: Single-Ended Mode. Only A side channel is converted."] + SingleEndedASideChannel = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctype { + type Ux = u8; +} +impl crate::IsEnum for Ctype {} +#[doc = "Field `CTYPE` reader - Conversion Type"] +pub type CtypeR = crate::FieldReader; +impl CtypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ctype::SingleEndedASideChannel), + _ => None, + } + } + #[doc = "Single-Ended Mode. Only A side channel is converted."] + #[inline(always)] + pub fn is_single_ended_a_side_channel(&self) -> bool { + *self == Ctype::SingleEndedASideChannel + } +} + +pub type CtypeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ctype>; + +#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] + Data12Bits = 0, + #[doc = "1: High resolution. Single-ended 16-bit conversion."] + Data16Bits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Select Resolution of Conversions"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Data12Bits, + true => Mode::Data16Bits, + } + } + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn is_data_12_bits(&self) -> bool { + *self == Mode::Data12Bits + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn is_data_16_bits(&self) -> bool { + *self == Mode::Data16Bits + } +} +#[doc = "Field `MODE` writer - Select Resolution of Conversions"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn data_12_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data12Bits) + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn data_16_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data16Bits) + } +} +impl R { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&self) -> AdchR { + AdchR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&self) -> CtypeR { + CtypeR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&mut self) -> AdchW { + AdchW::new(self, 0) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&mut self) -> CtypeW { + CtypeW::new(self, 5) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 7) + } +} +#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdl1Spec; +impl crate::RegisterSpec for Cmdl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdl1::R`](R) reader structure"] +impl crate::Readable for Cmdl1Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdl1::W`](W) writer structure"] +impl crate::Writable for Cmdl1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDL1 to value 0"] +impl crate::Resettable for Cmdl1Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl2.rs b/mcxa276-pac/src/adc0/cmdl2.rs new file mode 100644 index 000000000..89f46de66 --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdl2.rs @@ -0,0 +1,323 @@ +#[doc = "Register `CMDL2` reader"] +pub type R = crate::R; +#[doc = "Register `CMDL2` writer"] +pub type W = crate::W; +#[doc = "Input Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Adch { + #[doc = "0: Select CH0A."] + SelectCh0 = 0, + #[doc = "1: Select CH1A."] + SelectCh1 = 1, + #[doc = "2: Select CH2A."] + SelectCh2 = 2, + #[doc = "3: Select CH3A."] + SelectCh3 = 3, + #[doc = "4: Select corresponding channel CHnA."] + SelectCorrespondingChannel4 = 4, + #[doc = "5: Select corresponding channel CHnA."] + SelectCorrespondingChannel5 = 5, + #[doc = "6: Select corresponding channel CHnA."] + SelectCorrespondingChannel6 = 6, + #[doc = "7: Select corresponding channel CHnA."] + SelectCorrespondingChannel7 = 7, + #[doc = "8: Select corresponding channel CHnA."] + SelectCorrespondingChannel8 = 8, + #[doc = "9: Select corresponding channel CHnA."] + SelectCorrespondingChannel9 = 9, + #[doc = "30: Select CH30A."] + SelectCh30 = 30, + #[doc = "31: Select CH31A."] + SelectCh31 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Adch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Adch { + type Ux = u8; +} +impl crate::IsEnum for Adch {} +#[doc = "Field `ADCH` reader - Input Channel Select"] +pub type AdchR = crate::FieldReader; +impl AdchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Adch::SelectCh0), + 1 => Some(Adch::SelectCh1), + 2 => Some(Adch::SelectCh2), + 3 => Some(Adch::SelectCh3), + 4 => Some(Adch::SelectCorrespondingChannel4), + 5 => Some(Adch::SelectCorrespondingChannel5), + 6 => Some(Adch::SelectCorrespondingChannel6), + 7 => Some(Adch::SelectCorrespondingChannel7), + 8 => Some(Adch::SelectCorrespondingChannel8), + 9 => Some(Adch::SelectCorrespondingChannel9), + 30 => Some(Adch::SelectCh30), + 31 => Some(Adch::SelectCh31), + _ => None, + } + } + #[doc = "Select CH0A."] + #[inline(always)] + pub fn is_select_ch0(&self) -> bool { + *self == Adch::SelectCh0 + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn is_select_ch1(&self) -> bool { + *self == Adch::SelectCh1 + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn is_select_ch2(&self) -> bool { + *self == Adch::SelectCh2 + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn is_select_ch3(&self) -> bool { + *self == Adch::SelectCh3 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_4(&self) -> bool { + *self == Adch::SelectCorrespondingChannel4 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_5(&self) -> bool { + *self == Adch::SelectCorrespondingChannel5 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_6(&self) -> bool { + *self == Adch::SelectCorrespondingChannel6 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_7(&self) -> bool { + *self == Adch::SelectCorrespondingChannel7 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_8(&self) -> bool { + *self == Adch::SelectCorrespondingChannel8 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_9(&self) -> bool { + *self == Adch::SelectCorrespondingChannel9 + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn is_select_ch30(&self) -> bool { + *self == Adch::SelectCh30 + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn is_select_ch31(&self) -> bool { + *self == Adch::SelectCh31 + } +} +#[doc = "Field `ADCH` writer - Input Channel Select"] +pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; +impl<'a, REG> AdchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select CH0A."] + #[inline(always)] + pub fn select_ch0(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh0) + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn select_ch1(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh1) + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn select_ch2(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh2) + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn select_ch3(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh3) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel4) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel5) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel6) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel7) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel8) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel9) + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn select_ch30(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh30) + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn select_ch31(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh31) + } +} +#[doc = "Conversion Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctype { + #[doc = "0: Single-Ended Mode. Only A side channel is converted."] + SingleEndedASideChannel = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctype { + type Ux = u8; +} +impl crate::IsEnum for Ctype {} +#[doc = "Field `CTYPE` reader - Conversion Type"] +pub type CtypeR = crate::FieldReader; +impl CtypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ctype::SingleEndedASideChannel), + _ => None, + } + } + #[doc = "Single-Ended Mode. Only A side channel is converted."] + #[inline(always)] + pub fn is_single_ended_a_side_channel(&self) -> bool { + *self == Ctype::SingleEndedASideChannel + } +} +#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] + Data12Bits = 0, + #[doc = "1: High resolution. Single-ended 16-bit conversion."] + Data16Bits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Select Resolution of Conversions"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Data12Bits, + true => Mode::Data16Bits, + } + } + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn is_data_12_bits(&self) -> bool { + *self == Mode::Data12Bits + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn is_data_16_bits(&self) -> bool { + *self == Mode::Data16Bits + } +} +#[doc = "Field `MODE` writer - Select Resolution of Conversions"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn data_12_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data12Bits) + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn data_16_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data16Bits) + } +} +impl R { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&self) -> AdchR { + AdchR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&self) -> CtypeR { + CtypeR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&mut self) -> AdchW { + AdchW::new(self, 0) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 7) + } +} +#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdl2Spec; +impl crate::RegisterSpec for Cmdl2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdl2::R`](R) reader structure"] +impl crate::Readable for Cmdl2Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdl2::W`](W) writer structure"] +impl crate::Writable for Cmdl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDL2 to value 0"] +impl crate::Resettable for Cmdl2Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl3.rs b/mcxa276-pac/src/adc0/cmdl3.rs new file mode 100644 index 000000000..4a8104641 --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdl3.rs @@ -0,0 +1,323 @@ +#[doc = "Register `CMDL3` reader"] +pub type R = crate::R; +#[doc = "Register `CMDL3` writer"] +pub type W = crate::W; +#[doc = "Input Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Adch { + #[doc = "0: Select CH0A."] + SelectCh0 = 0, + #[doc = "1: Select CH1A."] + SelectCh1 = 1, + #[doc = "2: Select CH2A."] + SelectCh2 = 2, + #[doc = "3: Select CH3A."] + SelectCh3 = 3, + #[doc = "4: Select corresponding channel CHnA."] + SelectCorrespondingChannel4 = 4, + #[doc = "5: Select corresponding channel CHnA."] + SelectCorrespondingChannel5 = 5, + #[doc = "6: Select corresponding channel CHnA."] + SelectCorrespondingChannel6 = 6, + #[doc = "7: Select corresponding channel CHnA."] + SelectCorrespondingChannel7 = 7, + #[doc = "8: Select corresponding channel CHnA."] + SelectCorrespondingChannel8 = 8, + #[doc = "9: Select corresponding channel CHnA."] + SelectCorrespondingChannel9 = 9, + #[doc = "30: Select CH30A."] + SelectCh30 = 30, + #[doc = "31: Select CH31A."] + SelectCh31 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Adch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Adch { + type Ux = u8; +} +impl crate::IsEnum for Adch {} +#[doc = "Field `ADCH` reader - Input Channel Select"] +pub type AdchR = crate::FieldReader; +impl AdchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Adch::SelectCh0), + 1 => Some(Adch::SelectCh1), + 2 => Some(Adch::SelectCh2), + 3 => Some(Adch::SelectCh3), + 4 => Some(Adch::SelectCorrespondingChannel4), + 5 => Some(Adch::SelectCorrespondingChannel5), + 6 => Some(Adch::SelectCorrespondingChannel6), + 7 => Some(Adch::SelectCorrespondingChannel7), + 8 => Some(Adch::SelectCorrespondingChannel8), + 9 => Some(Adch::SelectCorrespondingChannel9), + 30 => Some(Adch::SelectCh30), + 31 => Some(Adch::SelectCh31), + _ => None, + } + } + #[doc = "Select CH0A."] + #[inline(always)] + pub fn is_select_ch0(&self) -> bool { + *self == Adch::SelectCh0 + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn is_select_ch1(&self) -> bool { + *self == Adch::SelectCh1 + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn is_select_ch2(&self) -> bool { + *self == Adch::SelectCh2 + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn is_select_ch3(&self) -> bool { + *self == Adch::SelectCh3 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_4(&self) -> bool { + *self == Adch::SelectCorrespondingChannel4 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_5(&self) -> bool { + *self == Adch::SelectCorrespondingChannel5 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_6(&self) -> bool { + *self == Adch::SelectCorrespondingChannel6 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_7(&self) -> bool { + *self == Adch::SelectCorrespondingChannel7 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_8(&self) -> bool { + *self == Adch::SelectCorrespondingChannel8 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_9(&self) -> bool { + *self == Adch::SelectCorrespondingChannel9 + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn is_select_ch30(&self) -> bool { + *self == Adch::SelectCh30 + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn is_select_ch31(&self) -> bool { + *self == Adch::SelectCh31 + } +} +#[doc = "Field `ADCH` writer - Input Channel Select"] +pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; +impl<'a, REG> AdchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select CH0A."] + #[inline(always)] + pub fn select_ch0(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh0) + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn select_ch1(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh1) + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn select_ch2(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh2) + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn select_ch3(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh3) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel4) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel5) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel6) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel7) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel8) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel9) + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn select_ch30(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh30) + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn select_ch31(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh31) + } +} +#[doc = "Conversion Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctype { + #[doc = "0: Single-Ended Mode. Only A side channel is converted."] + SingleEndedASideChannel = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctype { + type Ux = u8; +} +impl crate::IsEnum for Ctype {} +#[doc = "Field `CTYPE` reader - Conversion Type"] +pub type CtypeR = crate::FieldReader; +impl CtypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ctype::SingleEndedASideChannel), + _ => None, + } + } + #[doc = "Single-Ended Mode. Only A side channel is converted."] + #[inline(always)] + pub fn is_single_ended_a_side_channel(&self) -> bool { + *self == Ctype::SingleEndedASideChannel + } +} +#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] + Data12Bits = 0, + #[doc = "1: High resolution. Single-ended 16-bit conversion."] + Data16Bits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Select Resolution of Conversions"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Data12Bits, + true => Mode::Data16Bits, + } + } + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn is_data_12_bits(&self) -> bool { + *self == Mode::Data12Bits + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn is_data_16_bits(&self) -> bool { + *self == Mode::Data16Bits + } +} +#[doc = "Field `MODE` writer - Select Resolution of Conversions"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn data_12_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data12Bits) + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn data_16_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data16Bits) + } +} +impl R { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&self) -> AdchR { + AdchR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&self) -> CtypeR { + CtypeR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&mut self) -> AdchW { + AdchW::new(self, 0) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 7) + } +} +#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdl3Spec; +impl crate::RegisterSpec for Cmdl3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdl3::R`](R) reader structure"] +impl crate::Readable for Cmdl3Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdl3::W`](W) writer structure"] +impl crate::Writable for Cmdl3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDL3 to value 0"] +impl crate::Resettable for Cmdl3Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl4.rs b/mcxa276-pac/src/adc0/cmdl4.rs new file mode 100644 index 000000000..46e64f7d4 --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdl4.rs @@ -0,0 +1,323 @@ +#[doc = "Register `CMDL4` reader"] +pub type R = crate::R; +#[doc = "Register `CMDL4` writer"] +pub type W = crate::W; +#[doc = "Input Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Adch { + #[doc = "0: Select CH0A."] + SelectCh0 = 0, + #[doc = "1: Select CH1A."] + SelectCh1 = 1, + #[doc = "2: Select CH2A."] + SelectCh2 = 2, + #[doc = "3: Select CH3A."] + SelectCh3 = 3, + #[doc = "4: Select corresponding channel CHnA."] + SelectCorrespondingChannel4 = 4, + #[doc = "5: Select corresponding channel CHnA."] + SelectCorrespondingChannel5 = 5, + #[doc = "6: Select corresponding channel CHnA."] + SelectCorrespondingChannel6 = 6, + #[doc = "7: Select corresponding channel CHnA."] + SelectCorrespondingChannel7 = 7, + #[doc = "8: Select corresponding channel CHnA."] + SelectCorrespondingChannel8 = 8, + #[doc = "9: Select corresponding channel CHnA."] + SelectCorrespondingChannel9 = 9, + #[doc = "30: Select CH30A."] + SelectCh30 = 30, + #[doc = "31: Select CH31A."] + SelectCh31 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Adch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Adch { + type Ux = u8; +} +impl crate::IsEnum for Adch {} +#[doc = "Field `ADCH` reader - Input Channel Select"] +pub type AdchR = crate::FieldReader; +impl AdchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Adch::SelectCh0), + 1 => Some(Adch::SelectCh1), + 2 => Some(Adch::SelectCh2), + 3 => Some(Adch::SelectCh3), + 4 => Some(Adch::SelectCorrespondingChannel4), + 5 => Some(Adch::SelectCorrespondingChannel5), + 6 => Some(Adch::SelectCorrespondingChannel6), + 7 => Some(Adch::SelectCorrespondingChannel7), + 8 => Some(Adch::SelectCorrespondingChannel8), + 9 => Some(Adch::SelectCorrespondingChannel9), + 30 => Some(Adch::SelectCh30), + 31 => Some(Adch::SelectCh31), + _ => None, + } + } + #[doc = "Select CH0A."] + #[inline(always)] + pub fn is_select_ch0(&self) -> bool { + *self == Adch::SelectCh0 + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn is_select_ch1(&self) -> bool { + *self == Adch::SelectCh1 + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn is_select_ch2(&self) -> bool { + *self == Adch::SelectCh2 + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn is_select_ch3(&self) -> bool { + *self == Adch::SelectCh3 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_4(&self) -> bool { + *self == Adch::SelectCorrespondingChannel4 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_5(&self) -> bool { + *self == Adch::SelectCorrespondingChannel5 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_6(&self) -> bool { + *self == Adch::SelectCorrespondingChannel6 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_7(&self) -> bool { + *self == Adch::SelectCorrespondingChannel7 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_8(&self) -> bool { + *self == Adch::SelectCorrespondingChannel8 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_9(&self) -> bool { + *self == Adch::SelectCorrespondingChannel9 + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn is_select_ch30(&self) -> bool { + *self == Adch::SelectCh30 + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn is_select_ch31(&self) -> bool { + *self == Adch::SelectCh31 + } +} +#[doc = "Field `ADCH` writer - Input Channel Select"] +pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; +impl<'a, REG> AdchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select CH0A."] + #[inline(always)] + pub fn select_ch0(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh0) + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn select_ch1(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh1) + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn select_ch2(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh2) + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn select_ch3(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh3) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel4) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel5) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel6) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel7) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel8) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel9) + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn select_ch30(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh30) + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn select_ch31(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh31) + } +} +#[doc = "Conversion Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctype { + #[doc = "0: Single-Ended Mode. Only A side channel is converted."] + SingleEndedASideChannel = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctype { + type Ux = u8; +} +impl crate::IsEnum for Ctype {} +#[doc = "Field `CTYPE` reader - Conversion Type"] +pub type CtypeR = crate::FieldReader; +impl CtypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ctype::SingleEndedASideChannel), + _ => None, + } + } + #[doc = "Single-Ended Mode. Only A side channel is converted."] + #[inline(always)] + pub fn is_single_ended_a_side_channel(&self) -> bool { + *self == Ctype::SingleEndedASideChannel + } +} +#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] + Data12Bits = 0, + #[doc = "1: High resolution. Single-ended 16-bit conversion."] + Data16Bits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Select Resolution of Conversions"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Data12Bits, + true => Mode::Data16Bits, + } + } + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn is_data_12_bits(&self) -> bool { + *self == Mode::Data12Bits + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn is_data_16_bits(&self) -> bool { + *self == Mode::Data16Bits + } +} +#[doc = "Field `MODE` writer - Select Resolution of Conversions"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn data_12_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data12Bits) + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn data_16_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data16Bits) + } +} +impl R { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&self) -> AdchR { + AdchR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&self) -> CtypeR { + CtypeR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&mut self) -> AdchW { + AdchW::new(self, 0) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 7) + } +} +#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdl4Spec; +impl crate::RegisterSpec for Cmdl4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdl4::R`](R) reader structure"] +impl crate::Readable for Cmdl4Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdl4::W`](W) writer structure"] +impl crate::Writable for Cmdl4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDL4 to value 0"] +impl crate::Resettable for Cmdl4Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl5.rs b/mcxa276-pac/src/adc0/cmdl5.rs new file mode 100644 index 000000000..00f76e7dc --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdl5.rs @@ -0,0 +1,323 @@ +#[doc = "Register `CMDL5` reader"] +pub type R = crate::R; +#[doc = "Register `CMDL5` writer"] +pub type W = crate::W; +#[doc = "Input Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Adch { + #[doc = "0: Select CH0A."] + SelectCh0 = 0, + #[doc = "1: Select CH1A."] + SelectCh1 = 1, + #[doc = "2: Select CH2A."] + SelectCh2 = 2, + #[doc = "3: Select CH3A."] + SelectCh3 = 3, + #[doc = "4: Select corresponding channel CHnA."] + SelectCorrespondingChannel4 = 4, + #[doc = "5: Select corresponding channel CHnA."] + SelectCorrespondingChannel5 = 5, + #[doc = "6: Select corresponding channel CHnA."] + SelectCorrespondingChannel6 = 6, + #[doc = "7: Select corresponding channel CHnA."] + SelectCorrespondingChannel7 = 7, + #[doc = "8: Select corresponding channel CHnA."] + SelectCorrespondingChannel8 = 8, + #[doc = "9: Select corresponding channel CHnA."] + SelectCorrespondingChannel9 = 9, + #[doc = "30: Select CH30A."] + SelectCh30 = 30, + #[doc = "31: Select CH31A."] + SelectCh31 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Adch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Adch { + type Ux = u8; +} +impl crate::IsEnum for Adch {} +#[doc = "Field `ADCH` reader - Input Channel Select"] +pub type AdchR = crate::FieldReader; +impl AdchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Adch::SelectCh0), + 1 => Some(Adch::SelectCh1), + 2 => Some(Adch::SelectCh2), + 3 => Some(Adch::SelectCh3), + 4 => Some(Adch::SelectCorrespondingChannel4), + 5 => Some(Adch::SelectCorrespondingChannel5), + 6 => Some(Adch::SelectCorrespondingChannel6), + 7 => Some(Adch::SelectCorrespondingChannel7), + 8 => Some(Adch::SelectCorrespondingChannel8), + 9 => Some(Adch::SelectCorrespondingChannel9), + 30 => Some(Adch::SelectCh30), + 31 => Some(Adch::SelectCh31), + _ => None, + } + } + #[doc = "Select CH0A."] + #[inline(always)] + pub fn is_select_ch0(&self) -> bool { + *self == Adch::SelectCh0 + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn is_select_ch1(&self) -> bool { + *self == Adch::SelectCh1 + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn is_select_ch2(&self) -> bool { + *self == Adch::SelectCh2 + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn is_select_ch3(&self) -> bool { + *self == Adch::SelectCh3 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_4(&self) -> bool { + *self == Adch::SelectCorrespondingChannel4 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_5(&self) -> bool { + *self == Adch::SelectCorrespondingChannel5 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_6(&self) -> bool { + *self == Adch::SelectCorrespondingChannel6 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_7(&self) -> bool { + *self == Adch::SelectCorrespondingChannel7 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_8(&self) -> bool { + *self == Adch::SelectCorrespondingChannel8 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_9(&self) -> bool { + *self == Adch::SelectCorrespondingChannel9 + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn is_select_ch30(&self) -> bool { + *self == Adch::SelectCh30 + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn is_select_ch31(&self) -> bool { + *self == Adch::SelectCh31 + } +} +#[doc = "Field `ADCH` writer - Input Channel Select"] +pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; +impl<'a, REG> AdchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select CH0A."] + #[inline(always)] + pub fn select_ch0(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh0) + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn select_ch1(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh1) + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn select_ch2(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh2) + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn select_ch3(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh3) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel4) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel5) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel6) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel7) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel8) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel9) + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn select_ch30(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh30) + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn select_ch31(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh31) + } +} +#[doc = "Conversion Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctype { + #[doc = "0: Single-Ended Mode. Only A side channel is converted."] + SingleEndedASideChannel = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctype { + type Ux = u8; +} +impl crate::IsEnum for Ctype {} +#[doc = "Field `CTYPE` reader - Conversion Type"] +pub type CtypeR = crate::FieldReader; +impl CtypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ctype::SingleEndedASideChannel), + _ => None, + } + } + #[doc = "Single-Ended Mode. Only A side channel is converted."] + #[inline(always)] + pub fn is_single_ended_a_side_channel(&self) -> bool { + *self == Ctype::SingleEndedASideChannel + } +} +#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] + Data12Bits = 0, + #[doc = "1: High resolution. Single-ended 16-bit conversion."] + Data16Bits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Select Resolution of Conversions"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Data12Bits, + true => Mode::Data16Bits, + } + } + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn is_data_12_bits(&self) -> bool { + *self == Mode::Data12Bits + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn is_data_16_bits(&self) -> bool { + *self == Mode::Data16Bits + } +} +#[doc = "Field `MODE` writer - Select Resolution of Conversions"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn data_12_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data12Bits) + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn data_16_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data16Bits) + } +} +impl R { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&self) -> AdchR { + AdchR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&self) -> CtypeR { + CtypeR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&mut self) -> AdchW { + AdchW::new(self, 0) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 7) + } +} +#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdl5Spec; +impl crate::RegisterSpec for Cmdl5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdl5::R`](R) reader structure"] +impl crate::Readable for Cmdl5Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdl5::W`](W) writer structure"] +impl crate::Writable for Cmdl5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDL5 to value 0"] +impl crate::Resettable for Cmdl5Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl6.rs b/mcxa276-pac/src/adc0/cmdl6.rs new file mode 100644 index 000000000..de768847c --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdl6.rs @@ -0,0 +1,323 @@ +#[doc = "Register `CMDL6` reader"] +pub type R = crate::R; +#[doc = "Register `CMDL6` writer"] +pub type W = crate::W; +#[doc = "Input Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Adch { + #[doc = "0: Select CH0A."] + SelectCh0 = 0, + #[doc = "1: Select CH1A."] + SelectCh1 = 1, + #[doc = "2: Select CH2A."] + SelectCh2 = 2, + #[doc = "3: Select CH3A."] + SelectCh3 = 3, + #[doc = "4: Select corresponding channel CHnA."] + SelectCorrespondingChannel4 = 4, + #[doc = "5: Select corresponding channel CHnA."] + SelectCorrespondingChannel5 = 5, + #[doc = "6: Select corresponding channel CHnA."] + SelectCorrespondingChannel6 = 6, + #[doc = "7: Select corresponding channel CHnA."] + SelectCorrespondingChannel7 = 7, + #[doc = "8: Select corresponding channel CHnA."] + SelectCorrespondingChannel8 = 8, + #[doc = "9: Select corresponding channel CHnA."] + SelectCorrespondingChannel9 = 9, + #[doc = "30: Select CH30A."] + SelectCh30 = 30, + #[doc = "31: Select CH31A."] + SelectCh31 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Adch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Adch { + type Ux = u8; +} +impl crate::IsEnum for Adch {} +#[doc = "Field `ADCH` reader - Input Channel Select"] +pub type AdchR = crate::FieldReader; +impl AdchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Adch::SelectCh0), + 1 => Some(Adch::SelectCh1), + 2 => Some(Adch::SelectCh2), + 3 => Some(Adch::SelectCh3), + 4 => Some(Adch::SelectCorrespondingChannel4), + 5 => Some(Adch::SelectCorrespondingChannel5), + 6 => Some(Adch::SelectCorrespondingChannel6), + 7 => Some(Adch::SelectCorrespondingChannel7), + 8 => Some(Adch::SelectCorrespondingChannel8), + 9 => Some(Adch::SelectCorrespondingChannel9), + 30 => Some(Adch::SelectCh30), + 31 => Some(Adch::SelectCh31), + _ => None, + } + } + #[doc = "Select CH0A."] + #[inline(always)] + pub fn is_select_ch0(&self) -> bool { + *self == Adch::SelectCh0 + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn is_select_ch1(&self) -> bool { + *self == Adch::SelectCh1 + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn is_select_ch2(&self) -> bool { + *self == Adch::SelectCh2 + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn is_select_ch3(&self) -> bool { + *self == Adch::SelectCh3 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_4(&self) -> bool { + *self == Adch::SelectCorrespondingChannel4 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_5(&self) -> bool { + *self == Adch::SelectCorrespondingChannel5 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_6(&self) -> bool { + *self == Adch::SelectCorrespondingChannel6 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_7(&self) -> bool { + *self == Adch::SelectCorrespondingChannel7 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_8(&self) -> bool { + *self == Adch::SelectCorrespondingChannel8 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_9(&self) -> bool { + *self == Adch::SelectCorrespondingChannel9 + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn is_select_ch30(&self) -> bool { + *self == Adch::SelectCh30 + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn is_select_ch31(&self) -> bool { + *self == Adch::SelectCh31 + } +} +#[doc = "Field `ADCH` writer - Input Channel Select"] +pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; +impl<'a, REG> AdchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select CH0A."] + #[inline(always)] + pub fn select_ch0(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh0) + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn select_ch1(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh1) + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn select_ch2(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh2) + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn select_ch3(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh3) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel4) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel5) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel6) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel7) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel8) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel9) + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn select_ch30(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh30) + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn select_ch31(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh31) + } +} +#[doc = "Conversion Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctype { + #[doc = "0: Single-Ended Mode. Only A side channel is converted."] + SingleEndedASideChannel = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctype { + type Ux = u8; +} +impl crate::IsEnum for Ctype {} +#[doc = "Field `CTYPE` reader - Conversion Type"] +pub type CtypeR = crate::FieldReader; +impl CtypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ctype::SingleEndedASideChannel), + _ => None, + } + } + #[doc = "Single-Ended Mode. Only A side channel is converted."] + #[inline(always)] + pub fn is_single_ended_a_side_channel(&self) -> bool { + *self == Ctype::SingleEndedASideChannel + } +} +#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] + Data12Bits = 0, + #[doc = "1: High resolution. Single-ended 16-bit conversion."] + Data16Bits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Select Resolution of Conversions"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Data12Bits, + true => Mode::Data16Bits, + } + } + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn is_data_12_bits(&self) -> bool { + *self == Mode::Data12Bits + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn is_data_16_bits(&self) -> bool { + *self == Mode::Data16Bits + } +} +#[doc = "Field `MODE` writer - Select Resolution of Conversions"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn data_12_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data12Bits) + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn data_16_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data16Bits) + } +} +impl R { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&self) -> AdchR { + AdchR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&self) -> CtypeR { + CtypeR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&mut self) -> AdchW { + AdchW::new(self, 0) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 7) + } +} +#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdl6Spec; +impl crate::RegisterSpec for Cmdl6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdl6::R`](R) reader structure"] +impl crate::Readable for Cmdl6Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdl6::W`](W) writer structure"] +impl crate::Writable for Cmdl6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDL6 to value 0"] +impl crate::Resettable for Cmdl6Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl7.rs b/mcxa276-pac/src/adc0/cmdl7.rs new file mode 100644 index 000000000..08bef528a --- /dev/null +++ b/mcxa276-pac/src/adc0/cmdl7.rs @@ -0,0 +1,323 @@ +#[doc = "Register `CMDL7` reader"] +pub type R = crate::R; +#[doc = "Register `CMDL7` writer"] +pub type W = crate::W; +#[doc = "Input Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Adch { + #[doc = "0: Select CH0A."] + SelectCh0 = 0, + #[doc = "1: Select CH1A."] + SelectCh1 = 1, + #[doc = "2: Select CH2A."] + SelectCh2 = 2, + #[doc = "3: Select CH3A."] + SelectCh3 = 3, + #[doc = "4: Select corresponding channel CHnA."] + SelectCorrespondingChannel4 = 4, + #[doc = "5: Select corresponding channel CHnA."] + SelectCorrespondingChannel5 = 5, + #[doc = "6: Select corresponding channel CHnA."] + SelectCorrespondingChannel6 = 6, + #[doc = "7: Select corresponding channel CHnA."] + SelectCorrespondingChannel7 = 7, + #[doc = "8: Select corresponding channel CHnA."] + SelectCorrespondingChannel8 = 8, + #[doc = "9: Select corresponding channel CHnA."] + SelectCorrespondingChannel9 = 9, + #[doc = "30: Select CH30A."] + SelectCh30 = 30, + #[doc = "31: Select CH31A."] + SelectCh31 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Adch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Adch { + type Ux = u8; +} +impl crate::IsEnum for Adch {} +#[doc = "Field `ADCH` reader - Input Channel Select"] +pub type AdchR = crate::FieldReader; +impl AdchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Adch::SelectCh0), + 1 => Some(Adch::SelectCh1), + 2 => Some(Adch::SelectCh2), + 3 => Some(Adch::SelectCh3), + 4 => Some(Adch::SelectCorrespondingChannel4), + 5 => Some(Adch::SelectCorrespondingChannel5), + 6 => Some(Adch::SelectCorrespondingChannel6), + 7 => Some(Adch::SelectCorrespondingChannel7), + 8 => Some(Adch::SelectCorrespondingChannel8), + 9 => Some(Adch::SelectCorrespondingChannel9), + 30 => Some(Adch::SelectCh30), + 31 => Some(Adch::SelectCh31), + _ => None, + } + } + #[doc = "Select CH0A."] + #[inline(always)] + pub fn is_select_ch0(&self) -> bool { + *self == Adch::SelectCh0 + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn is_select_ch1(&self) -> bool { + *self == Adch::SelectCh1 + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn is_select_ch2(&self) -> bool { + *self == Adch::SelectCh2 + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn is_select_ch3(&self) -> bool { + *self == Adch::SelectCh3 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_4(&self) -> bool { + *self == Adch::SelectCorrespondingChannel4 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_5(&self) -> bool { + *self == Adch::SelectCorrespondingChannel5 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_6(&self) -> bool { + *self == Adch::SelectCorrespondingChannel6 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_7(&self) -> bool { + *self == Adch::SelectCorrespondingChannel7 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_8(&self) -> bool { + *self == Adch::SelectCorrespondingChannel8 + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn is_select_corresponding_channel_9(&self) -> bool { + *self == Adch::SelectCorrespondingChannel9 + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn is_select_ch30(&self) -> bool { + *self == Adch::SelectCh30 + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn is_select_ch31(&self) -> bool { + *self == Adch::SelectCh31 + } +} +#[doc = "Field `ADCH` writer - Input Channel Select"] +pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; +impl<'a, REG> AdchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select CH0A."] + #[inline(always)] + pub fn select_ch0(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh0) + } + #[doc = "Select CH1A."] + #[inline(always)] + pub fn select_ch1(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh1) + } + #[doc = "Select CH2A."] + #[inline(always)] + pub fn select_ch2(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh2) + } + #[doc = "Select CH3A."] + #[inline(always)] + pub fn select_ch3(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh3) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel4) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel5) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel6) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel7) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel8) + } + #[doc = "Select corresponding channel CHnA."] + #[inline(always)] + pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { + self.variant(Adch::SelectCorrespondingChannel9) + } + #[doc = "Select CH30A."] + #[inline(always)] + pub fn select_ch30(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh30) + } + #[doc = "Select CH31A."] + #[inline(always)] + pub fn select_ch31(self) -> &'a mut crate::W { + self.variant(Adch::SelectCh31) + } +} +#[doc = "Conversion Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctype { + #[doc = "0: Single-Ended Mode. Only A side channel is converted."] + SingleEndedASideChannel = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctype { + type Ux = u8; +} +impl crate::IsEnum for Ctype {} +#[doc = "Field `CTYPE` reader - Conversion Type"] +pub type CtypeR = crate::FieldReader; +impl CtypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ctype::SingleEndedASideChannel), + _ => None, + } + } + #[doc = "Single-Ended Mode. Only A side channel is converted."] + #[inline(always)] + pub fn is_single_ended_a_side_channel(&self) -> bool { + *self == Ctype::SingleEndedASideChannel + } +} +#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] + Data12Bits = 0, + #[doc = "1: High resolution. Single-ended 16-bit conversion."] + Data16Bits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Select Resolution of Conversions"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Data12Bits, + true => Mode::Data16Bits, + } + } + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn is_data_12_bits(&self) -> bool { + *self == Mode::Data12Bits + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn is_data_16_bits(&self) -> bool { + *self == Mode::Data16Bits + } +} +#[doc = "Field `MODE` writer - Select Resolution of Conversions"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard resolution. Single-ended 12-bit conversion."] + #[inline(always)] + pub fn data_12_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data12Bits) + } + #[doc = "High resolution. Single-ended 16-bit conversion."] + #[inline(always)] + pub fn data_16_bits(self) -> &'a mut crate::W { + self.variant(Mode::Data16Bits) + } +} +impl R { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&self) -> AdchR { + AdchR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Conversion Type"] + #[inline(always)] + pub fn ctype(&self) -> CtypeR { + CtypeR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Input Channel Select"] + #[inline(always)] + pub fn adch(&mut self) -> AdchW { + AdchW::new(self, 0) + } + #[doc = "Bit 7 - Select Resolution of Conversions"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 7) + } +} +#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmdl7Spec; +impl crate::RegisterSpec for Cmdl7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdl7::R`](R) reader structure"] +impl crate::Readable for Cmdl7Spec {} +#[doc = "`write(|w| ..)` method takes [`cmdl7::W`](W) writer structure"] +impl crate::Writable for Cmdl7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMDL7 to value 0"] +impl crate::Resettable for Cmdl7Spec {} diff --git a/mcxa276-pac/src/adc0/ctrl.rs b/mcxa276-pac/src/adc0/ctrl.rs new file mode 100644 index 000000000..b774553a4 --- /dev/null +++ b/mcxa276-pac/src/adc0/ctrl.rs @@ -0,0 +1,649 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "ADC Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adcen { + #[doc = "0: ADC is disabled."] + Disabled = 0, + #[doc = "1: ADC is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADCEN` reader - ADC Enable"] +pub type AdcenR = crate::BitReader; +impl AdcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adcen { + match self.bits { + false => Adcen::Disabled, + true => Adcen::Enabled, + } + } + #[doc = "ADC is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adcen::Disabled + } + #[doc = "ADC is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adcen::Enabled + } +} +#[doc = "Field `ADCEN` writer - ADC Enable"] +pub type AdcenW<'a, REG> = crate::BitWriter<'a, REG, Adcen>; +impl<'a, REG> AdcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ADC is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adcen::Disabled) + } + #[doc = "ADC is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adcen::Enabled) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rst { + #[doc = "0: ADC logic is not reset."] + ReleasedFromReset = 0, + #[doc = "1: ADC logic is reset."] + HeldInReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RST` reader - Software Reset"] +pub type RstR = crate::BitReader; +impl RstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rst { + match self.bits { + false => Rst::ReleasedFromReset, + true => Rst::HeldInReset, + } + } + #[doc = "ADC logic is not reset."] + #[inline(always)] + pub fn is_released_from_reset(&self) -> bool { + *self == Rst::ReleasedFromReset + } + #[doc = "ADC logic is reset."] + #[inline(always)] + pub fn is_held_in_reset(&self) -> bool { + *self == Rst::HeldInReset + } +} +#[doc = "Field `RST` writer - Software Reset"] +pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; +impl<'a, REG> RstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ADC logic is not reset."] + #[inline(always)] + pub fn released_from_reset(self) -> &'a mut crate::W { + self.variant(Rst::ReleasedFromReset) + } + #[doc = "ADC logic is reset."] + #[inline(always)] + pub fn held_in_reset(self) -> &'a mut crate::W { + self.variant(Rst::HeldInReset) + } +} +#[doc = "Doze Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dozen { + #[doc = "0: ADC is enabled in low power mode."] + Enabled = 0, + #[doc = "1: ADC is disabled in low power mode."] + Disabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dozen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DOZEN` reader - Doze Enable"] +pub type DozenR = crate::BitReader; +impl DozenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dozen { + match self.bits { + false => Dozen::Enabled, + true => Dozen::Disabled, + } + } + #[doc = "ADC is enabled in low power mode."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dozen::Enabled + } + #[doc = "ADC is disabled in low power mode."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dozen::Disabled + } +} +#[doc = "Field `DOZEN` writer - Doze Enable"] +pub type DozenW<'a, REG> = crate::BitWriter<'a, REG, Dozen>; +impl<'a, REG> DozenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ADC is enabled in low power mode."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dozen::Enabled) + } + #[doc = "ADC is disabled in low power mode."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dozen::Disabled) + } +} +#[doc = "Auto-Calibration Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CalReq { + #[doc = "0: No request for hardware calibration has been made"] + NoCalibrationRequest = 0, + #[doc = "1: A request for hardware calibration has been made"] + CalibrationRequestPending = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CalReq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAL_REQ` reader - Auto-Calibration Request"] +pub type CalReqR = crate::BitReader; +impl CalReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CalReq { + match self.bits { + false => CalReq::NoCalibrationRequest, + true => CalReq::CalibrationRequestPending, + } + } + #[doc = "No request for hardware calibration has been made"] + #[inline(always)] + pub fn is_no_calibration_request(&self) -> bool { + *self == CalReq::NoCalibrationRequest + } + #[doc = "A request for hardware calibration has been made"] + #[inline(always)] + pub fn is_calibration_request_pending(&self) -> bool { + *self == CalReq::CalibrationRequestPending + } +} +#[doc = "Field `CAL_REQ` writer - Auto-Calibration Request"] +pub type CalReqW<'a, REG> = crate::BitWriter<'a, REG, CalReq>; +impl<'a, REG> CalReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No request for hardware calibration has been made"] + #[inline(always)] + pub fn no_calibration_request(self) -> &'a mut crate::W { + self.variant(CalReq::NoCalibrationRequest) + } + #[doc = "A request for hardware calibration has been made"] + #[inline(always)] + pub fn calibration_request_pending(self) -> &'a mut crate::W { + self.variant(CalReq::CalibrationRequestPending) + } +} +#[doc = "Offset Calibration Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Calofs { + #[doc = "0: No request for offset calibration has been made"] + NoActiveOffsetCalibrationRequest = 0, + #[doc = "1: Request for offset calibration function"] + OffsetCalibrationRequestPending = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Calofs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CALOFS` reader - Offset Calibration Request"] +pub type CalofsR = crate::BitReader; +impl CalofsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Calofs { + match self.bits { + false => Calofs::NoActiveOffsetCalibrationRequest, + true => Calofs::OffsetCalibrationRequestPending, + } + } + #[doc = "No request for offset calibration has been made"] + #[inline(always)] + pub fn is_no_active_offset_calibration_request(&self) -> bool { + *self == Calofs::NoActiveOffsetCalibrationRequest + } + #[doc = "Request for offset calibration function"] + #[inline(always)] + pub fn is_offset_calibration_request_pending(&self) -> bool { + *self == Calofs::OffsetCalibrationRequestPending + } +} +#[doc = "Field `CALOFS` writer - Offset Calibration Request"] +pub type CalofsW<'a, REG> = crate::BitWriter<'a, REG, Calofs>; +impl<'a, REG> CalofsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No request for offset calibration has been made"] + #[inline(always)] + pub fn no_active_offset_calibration_request(self) -> &'a mut crate::W { + self.variant(Calofs::NoActiveOffsetCalibrationRequest) + } + #[doc = "Request for offset calibration function"] + #[inline(always)] + pub fn offset_calibration_request_pending(self) -> &'a mut crate::W { + self.variant(Calofs::OffsetCalibrationRequestPending) + } +} +#[doc = "High Speed Mode Trim Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Calhs { + #[doc = "0: No request for high speed mode trim has been made"] + NoActiveHsTrimRequest = 0, + #[doc = "1: Request for high speed mode trim has been made"] + HsTrimRequestPending = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Calhs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CALHS` reader - High Speed Mode Trim Request"] +pub type CalhsR = crate::BitReader; +impl CalhsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Calhs { + match self.bits { + false => Calhs::NoActiveHsTrimRequest, + true => Calhs::HsTrimRequestPending, + } + } + #[doc = "No request for high speed mode trim has been made"] + #[inline(always)] + pub fn is_no_active_hs_trim_request(&self) -> bool { + *self == Calhs::NoActiveHsTrimRequest + } + #[doc = "Request for high speed mode trim has been made"] + #[inline(always)] + pub fn is_hs_trim_request_pending(&self) -> bool { + *self == Calhs::HsTrimRequestPending + } +} +#[doc = "Field `CALHS` writer - High Speed Mode Trim Request"] +pub type CalhsW<'a, REG> = crate::BitWriter<'a, REG, Calhs>; +impl<'a, REG> CalhsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No request for high speed mode trim has been made"] + #[inline(always)] + pub fn no_active_hs_trim_request(self) -> &'a mut crate::W { + self.variant(Calhs::NoActiveHsTrimRequest) + } + #[doc = "Request for high speed mode trim has been made"] + #[inline(always)] + pub fn hs_trim_request_pending(self) -> &'a mut crate::W { + self.variant(Calhs::HsTrimRequestPending) + } +} +#[doc = "Reset FIFO 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rstfifo0 { + #[doc = "0: No effect."] + NoAction = 0, + #[doc = "1: FIFO 0 is reset."] + TriggerReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rstfifo0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSTFIFO0` reader - Reset FIFO 0"] +pub type Rstfifo0R = crate::BitReader; +impl Rstfifo0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rstfifo0 { + match self.bits { + false => Rstfifo0::NoAction, + true => Rstfifo0::TriggerReset, + } + } + #[doc = "No effect."] + #[inline(always)] + pub fn is_no_action(&self) -> bool { + *self == Rstfifo0::NoAction + } + #[doc = "FIFO 0 is reset."] + #[inline(always)] + pub fn is_trigger_reset(&self) -> bool { + *self == Rstfifo0::TriggerReset + } +} +#[doc = "Field `RSTFIFO0` writer - Reset FIFO 0"] +pub type Rstfifo0W<'a, REG> = crate::BitWriter<'a, REG, Rstfifo0>; +impl<'a, REG> Rstfifo0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect."] + #[inline(always)] + pub fn no_action(self) -> &'a mut crate::W { + self.variant(Rstfifo0::NoAction) + } + #[doc = "FIFO 0 is reset."] + #[inline(always)] + pub fn trigger_reset(self) -> &'a mut crate::W { + self.variant(Rstfifo0::TriggerReset) + } +} +#[doc = "Auto-Calibration Averages\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CalAvgs { + #[doc = "0: Single conversion."] + NoAverage = 0, + #[doc = "1: 2 conversions averaged."] + Average2 = 1, + #[doc = "2: 4 conversions averaged."] + Average4 = 2, + #[doc = "3: 8 conversions averaged."] + Average8 = 3, + #[doc = "4: 16 conversions averaged."] + Average16 = 4, + #[doc = "5: 32 conversions averaged."] + Average32 = 5, + #[doc = "6: 64 conversions averaged."] + Average64 = 6, + #[doc = "7: 128 conversions averaged."] + Average128 = 7, + #[doc = "8: 256 conversions averaged."] + Average256 = 8, + #[doc = "9: 512 conversions averaged."] + Average512 = 9, + #[doc = "10: 1024 conversions averaged."] + Average1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CalAvgs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CalAvgs { + type Ux = u8; +} +impl crate::IsEnum for CalAvgs {} +#[doc = "Field `CAL_AVGS` reader - Auto-Calibration Averages"] +pub type CalAvgsR = crate::FieldReader; +impl CalAvgsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(CalAvgs::NoAverage), + 1 => Some(CalAvgs::Average2), + 2 => Some(CalAvgs::Average4), + 3 => Some(CalAvgs::Average8), + 4 => Some(CalAvgs::Average16), + 5 => Some(CalAvgs::Average32), + 6 => Some(CalAvgs::Average64), + 7 => Some(CalAvgs::Average128), + 8 => Some(CalAvgs::Average256), + 9 => Some(CalAvgs::Average512), + 10 => Some(CalAvgs::Average1024), + _ => None, + } + } + #[doc = "Single conversion."] + #[inline(always)] + pub fn is_no_average(&self) -> bool { + *self == CalAvgs::NoAverage + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn is_average_2(&self) -> bool { + *self == CalAvgs::Average2 + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn is_average_4(&self) -> bool { + *self == CalAvgs::Average4 + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn is_average_8(&self) -> bool { + *self == CalAvgs::Average8 + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn is_average_16(&self) -> bool { + *self == CalAvgs::Average16 + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn is_average_32(&self) -> bool { + *self == CalAvgs::Average32 + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn is_average_64(&self) -> bool { + *self == CalAvgs::Average64 + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn is_average_128(&self) -> bool { + *self == CalAvgs::Average128 + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn is_average_256(&self) -> bool { + *self == CalAvgs::Average256 + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn is_average_512(&self) -> bool { + *self == CalAvgs::Average512 + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn is_average_1024(&self) -> bool { + *self == CalAvgs::Average1024 + } +} +#[doc = "Field `CAL_AVGS` writer - Auto-Calibration Averages"] +pub type CalAvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, CalAvgs>; +impl<'a, REG> CalAvgsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single conversion."] + #[inline(always)] + pub fn no_average(self) -> &'a mut crate::W { + self.variant(CalAvgs::NoAverage) + } + #[doc = "2 conversions averaged."] + #[inline(always)] + pub fn average_2(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average2) + } + #[doc = "4 conversions averaged."] + #[inline(always)] + pub fn average_4(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average4) + } + #[doc = "8 conversions averaged."] + #[inline(always)] + pub fn average_8(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average8) + } + #[doc = "16 conversions averaged."] + #[inline(always)] + pub fn average_16(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average16) + } + #[doc = "32 conversions averaged."] + #[inline(always)] + pub fn average_32(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average32) + } + #[doc = "64 conversions averaged."] + #[inline(always)] + pub fn average_64(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average64) + } + #[doc = "128 conversions averaged."] + #[inline(always)] + pub fn average_128(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average128) + } + #[doc = "256 conversions averaged."] + #[inline(always)] + pub fn average_256(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average256) + } + #[doc = "512 conversions averaged."] + #[inline(always)] + pub fn average_512(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average512) + } + #[doc = "1024 conversions averaged."] + #[inline(always)] + pub fn average_1024(self) -> &'a mut crate::W { + self.variant(CalAvgs::Average1024) + } +} +impl R { + #[doc = "Bit 0 - ADC Enable"] + #[inline(always)] + pub fn adcen(&self) -> AdcenR { + AdcenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&self) -> RstR { + RstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doze Enable"] + #[inline(always)] + pub fn dozen(&self) -> DozenR { + DozenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Auto-Calibration Request"] + #[inline(always)] + pub fn cal_req(&self) -> CalReqR { + CalReqR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Offset Calibration Request"] + #[inline(always)] + pub fn calofs(&self) -> CalofsR { + CalofsR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - High Speed Mode Trim Request"] + #[inline(always)] + pub fn calhs(&self) -> CalhsR { + CalhsR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Reset FIFO 0"] + #[inline(always)] + pub fn rstfifo0(&self) -> Rstfifo0R { + Rstfifo0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 16:19 - Auto-Calibration Averages"] + #[inline(always)] + pub fn cal_avgs(&self) -> CalAvgsR { + CalAvgsR::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - ADC Enable"] + #[inline(always)] + pub fn adcen(&mut self) -> AdcenW { + AdcenW::new(self, 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RstW { + RstW::new(self, 1) + } + #[doc = "Bit 2 - Doze Enable"] + #[inline(always)] + pub fn dozen(&mut self) -> DozenW { + DozenW::new(self, 2) + } + #[doc = "Bit 3 - Auto-Calibration Request"] + #[inline(always)] + pub fn cal_req(&mut self) -> CalReqW { + CalReqW::new(self, 3) + } + #[doc = "Bit 4 - Offset Calibration Request"] + #[inline(always)] + pub fn calofs(&mut self) -> CalofsW { + CalofsW::new(self, 4) + } + #[doc = "Bit 6 - High Speed Mode Trim Request"] + #[inline(always)] + pub fn calhs(&mut self) -> CalhsW { + CalhsW::new(self, 6) + } + #[doc = "Bit 8 - Reset FIFO 0"] + #[inline(always)] + pub fn rstfifo0(&mut self) -> Rstfifo0W { + Rstfifo0W::new(self, 8) + } + #[doc = "Bits 16:19 - Auto-Calibration Averages"] + #[inline(always)] + pub fn cal_avgs(&mut self) -> CalAvgsW { + CalAvgsW::new(self, 16) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/adc0/cv.rs b/mcxa276-pac/src/adc0/cv.rs new file mode 100644 index 000000000..a40845af8 --- /dev/null +++ b/mcxa276-pac/src/adc0/cv.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CV%s` reader"] +pub type R = crate::R; +#[doc = "Register `CV%s` writer"] +pub type W = crate::W; +#[doc = "Field `CVL` reader - Compare Value Low"] +pub type CvlR = crate::FieldReader; +#[doc = "Field `CVL` writer - Compare Value Low"] +pub type CvlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CVH` reader - Compare Value High"] +pub type CvhR = crate::FieldReader; +#[doc = "Field `CVH` writer - Compare Value High"] +pub type CvhW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Compare Value Low"] + #[inline(always)] + pub fn cvl(&self) -> CvlR { + CvlR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Compare Value High"] + #[inline(always)] + pub fn cvh(&self) -> CvhR { + CvhR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value Low"] + #[inline(always)] + pub fn cvl(&mut self) -> CvlW { + CvlW::new(self, 0) + } + #[doc = "Bits 16:31 - Compare Value High"] + #[inline(always)] + pub fn cvh(&mut self) -> CvhW { + CvhW::new(self, 16) + } +} +#[doc = "Compare Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CvSpec; +impl crate::RegisterSpec for CvSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cv::R`](R) reader structure"] +impl crate::Readable for CvSpec {} +#[doc = "`write(|w| ..)` method takes [`cv::W`](W) writer structure"] +impl crate::Writable for CvSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CV%s to value 0"] +impl crate::Resettable for CvSpec {} diff --git a/mcxa276-pac/src/adc0/de.rs b/mcxa276-pac/src/adc0/de.rs new file mode 100644 index 000000000..6a75e90a3 --- /dev/null +++ b/mcxa276-pac/src/adc0/de.rs @@ -0,0 +1,84 @@ +#[doc = "Register `DE` reader"] +pub type R = crate::R; +#[doc = "Register `DE` writer"] +pub type W = crate::W; +#[doc = "FIFO 0 Watermark DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fwmde0 { + #[doc = "0: DMA request disabled."] + Disabled = 0, + #[doc = "1: DMA request enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fwmde0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FWMDE0` reader - FIFO 0 Watermark DMA Enable"] +pub type Fwmde0R = crate::BitReader; +impl Fwmde0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fwmde0 { + match self.bits { + false => Fwmde0::Disabled, + true => Fwmde0::Enabled, + } + } + #[doc = "DMA request disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fwmde0::Disabled + } + #[doc = "DMA request enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fwmde0::Enabled + } +} +#[doc = "Field `FWMDE0` writer - FIFO 0 Watermark DMA Enable"] +pub type Fwmde0W<'a, REG> = crate::BitWriter<'a, REG, Fwmde0>; +impl<'a, REG> Fwmde0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DMA request disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fwmde0::Disabled) + } + #[doc = "DMA request enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fwmde0::Enabled) + } +} +impl R { + #[doc = "Bit 0 - FIFO 0 Watermark DMA Enable"] + #[inline(always)] + pub fn fwmde0(&self) -> Fwmde0R { + Fwmde0R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FIFO 0 Watermark DMA Enable"] + #[inline(always)] + pub fn fwmde0(&mut self) -> Fwmde0W { + Fwmde0W::new(self, 0) + } +} +#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DeSpec; +impl crate::RegisterSpec for DeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`de::R`](R) reader structure"] +impl crate::Readable for DeSpec {} +#[doc = "`write(|w| ..)` method takes [`de::W`](W) writer structure"] +impl crate::Writable for DeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DE to value 0"] +impl crate::Resettable for DeSpec {} diff --git a/mcxa276-pac/src/adc0/fctrl0.rs b/mcxa276-pac/src/adc0/fctrl0.rs new file mode 100644 index 000000000..3acc78aad --- /dev/null +++ b/mcxa276-pac/src/adc0/fctrl0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FCTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `FCTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `FCOUNT` reader - Result FIFO Counter"] +pub type FcountR = crate::FieldReader; +#[doc = "Field `FWMARK` reader - Watermark Level Selection"] +pub type FwmarkR = crate::FieldReader; +#[doc = "Field `FWMARK` writer - Watermark Level Selection"] +pub type FwmarkW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Result FIFO Counter"] + #[inline(always)] + pub fn fcount(&self) -> FcountR { + FcountR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 16:18 - Watermark Level Selection"] + #[inline(always)] + pub fn fwmark(&self) -> FwmarkR { + FwmarkR::new(((self.bits >> 16) & 7) as u8) + } +} +impl W { + #[doc = "Bits 16:18 - Watermark Level Selection"] + #[inline(always)] + pub fn fwmark(&mut self) -> FwmarkW { + FwmarkW::new(self, 16) + } +} +#[doc = "FIFO Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fctrl0Spec; +impl crate::RegisterSpec for Fctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fctrl0::R`](R) reader structure"] +impl crate::Readable for Fctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`fctrl0::W`](W) writer structure"] +impl crate::Writable for Fctrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCTRL0 to value 0"] +impl crate::Resettable for Fctrl0Spec {} diff --git a/mcxa276-pac/src/adc0/gcc0.rs b/mcxa276-pac/src/adc0/gcc0.rs new file mode 100644 index 000000000..6b612c927 --- /dev/null +++ b/mcxa276-pac/src/adc0/gcc0.rs @@ -0,0 +1,61 @@ +#[doc = "Register `GCC0` reader"] +pub type R = crate::R; +#[doc = "Field `GAIN_CAL` reader - Gain Calibration Value"] +pub type GainCalR = crate::FieldReader; +#[doc = "Gain Calibration Value Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdy { + #[doc = "0: The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set."] + GainCalNotValid = 0, + #[doc = "1: The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa\\[GCALR\\]."] + HardwareCalRoutineCompleted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdy) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDY` reader - Gain Calibration Value Valid"] +pub type RdyR = crate::BitReader; +impl RdyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdy { + match self.bits { + false => Rdy::GainCalNotValid, + true => Rdy::HardwareCalRoutineCompleted, + } + } + #[doc = "The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set."] + #[inline(always)] + pub fn is_gain_cal_not_valid(&self) -> bool { + *self == Rdy::GainCalNotValid + } + #[doc = "The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa\\[GCALR\\]."] + #[inline(always)] + pub fn is_hardware_cal_routine_completed(&self) -> bool { + *self == Rdy::HardwareCalRoutineCompleted + } +} +impl R { + #[doc = "Bits 0:15 - Gain Calibration Value"] + #[inline(always)] + pub fn gain_cal(&self) -> GainCalR { + GainCalR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 24 - Gain Calibration Value Valid"] + #[inline(always)] + pub fn rdy(&self) -> RdyR { + RdyR::new(((self.bits >> 24) & 1) != 0) + } +} +#[doc = "Gain Calibration Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcc0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Gcc0Spec; +impl crate::RegisterSpec for Gcc0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gcc0::R`](R) reader structure"] +impl crate::Readable for Gcc0Spec {} +#[doc = "`reset()` method sets GCC0 to value 0"] +impl crate::Resettable for Gcc0Spec {} diff --git a/mcxa276-pac/src/adc0/gcr0.rs b/mcxa276-pac/src/adc0/gcr0.rs new file mode 100644 index 000000000..c62e2dc56 --- /dev/null +++ b/mcxa276-pac/src/adc0/gcr0.rs @@ -0,0 +1,100 @@ +#[doc = "Register `GCR0` reader"] +pub type R = crate::R; +#[doc = "Register `GCR0` writer"] +pub type W = crate::W; +#[doc = "Field `GCALR` reader - Gain Calculation Result"] +pub type GcalrR = crate::FieldReader; +#[doc = "Field `GCALR` writer - Gain Calculation Result"] +pub type GcalrW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +#[doc = "Gain Calculation Ready\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdy { + #[doc = "0: The GCALR value is invalid."] + NotValid = 0, + #[doc = "1: The GCALR value is valid."] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdy) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDY` reader - Gain Calculation Ready"] +pub type RdyR = crate::BitReader; +impl RdyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdy { + match self.bits { + false => Rdy::NotValid, + true => Rdy::Valid, + } + } + #[doc = "The GCALR value is invalid."] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Rdy::NotValid + } + #[doc = "The GCALR value is valid."] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Rdy::Valid + } +} +#[doc = "Field `RDY` writer - Gain Calculation Ready"] +pub type RdyW<'a, REG> = crate::BitWriter<'a, REG, Rdy>; +impl<'a, REG> RdyW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The GCALR value is invalid."] + #[inline(always)] + pub fn not_valid(self) -> &'a mut crate::W { + self.variant(Rdy::NotValid) + } + #[doc = "The GCALR value is valid."] + #[inline(always)] + pub fn valid(self) -> &'a mut crate::W { + self.variant(Rdy::Valid) + } +} +impl R { + #[doc = "Bits 0:16 - Gain Calculation Result"] + #[inline(always)] + pub fn gcalr(&self) -> GcalrR { + GcalrR::new(self.bits & 0x0001_ffff) + } + #[doc = "Bit 24 - Gain Calculation Ready"] + #[inline(always)] + pub fn rdy(&self) -> RdyR { + RdyR::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:16 - Gain Calculation Result"] + #[inline(always)] + pub fn gcalr(&mut self) -> GcalrW { + GcalrW::new(self, 0) + } + #[doc = "Bit 24 - Gain Calculation Ready"] + #[inline(always)] + pub fn rdy(&mut self) -> RdyW { + RdyW::new(self, 24) + } +} +#[doc = "Gain Calculation Result\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Gcr0Spec; +impl crate::RegisterSpec for Gcr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gcr0::R`](R) reader structure"] +impl crate::Readable for Gcr0Spec {} +#[doc = "`write(|w| ..)` method takes [`gcr0::W`](W) writer structure"] +impl crate::Writable for Gcr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GCR0 to value 0x0001_0000"] +impl crate::Resettable for Gcr0Spec { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/mcxa276-pac/src/adc0/hstrim.rs b/mcxa276-pac/src/adc0/hstrim.rs new file mode 100644 index 000000000..b4c32e480 --- /dev/null +++ b/mcxa276-pac/src/adc0/hstrim.rs @@ -0,0 +1,35 @@ +#[doc = "Register `HSTRIM` reader"] +pub type R = crate::R; +#[doc = "Register `HSTRIM` writer"] +pub type W = crate::W; +#[doc = "Field `HSTRIM` reader - Trim for High Speed Conversions"] +pub type HstrimR = crate::FieldReader; +#[doc = "Field `HSTRIM` writer - Trim for High Speed Conversions"] +pub type HstrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Trim for High Speed Conversions"] + #[inline(always)] + pub fn hstrim(&self) -> HstrimR { + HstrimR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Trim for High Speed Conversions"] + #[inline(always)] + pub fn hstrim(&mut self) -> HstrimW { + HstrimW::new(self, 0) + } +} +#[doc = "High Speed Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hstrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hstrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HstrimSpec; +impl crate::RegisterSpec for HstrimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`hstrim::R`](R) reader structure"] +impl crate::Readable for HstrimSpec {} +#[doc = "`write(|w| ..)` method takes [`hstrim::W`](W) writer structure"] +impl crate::Writable for HstrimSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets HSTRIM to value 0"] +impl crate::Resettable for HstrimSpec {} diff --git a/mcxa276-pac/src/adc0/ie.rs b/mcxa276-pac/src/adc0/ie.rs new file mode 100644 index 000000000..660d53d43 --- /dev/null +++ b/mcxa276-pac/src/adc0/ie.rs @@ -0,0 +1,397 @@ +#[doc = "Register `IE` reader"] +pub type R = crate::R; +#[doc = "Register `IE` writer"] +pub type W = crate::W; +#[doc = "FIFO 0 Watermark Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fwmie0 { + #[doc = "0: FIFO 0 watermark interrupts are not enabled."] + Disabled = 0, + #[doc = "1: FIFO 0 watermark interrupts are enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fwmie0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FWMIE0` reader - FIFO 0 Watermark Interrupt Enable"] +pub type Fwmie0R = crate::BitReader; +impl Fwmie0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fwmie0 { + match self.bits { + false => Fwmie0::Disabled, + true => Fwmie0::Enabled, + } + } + #[doc = "FIFO 0 watermark interrupts are not enabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fwmie0::Disabled + } + #[doc = "FIFO 0 watermark interrupts are enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fwmie0::Enabled + } +} +#[doc = "Field `FWMIE0` writer - FIFO 0 Watermark Interrupt Enable"] +pub type Fwmie0W<'a, REG> = crate::BitWriter<'a, REG, Fwmie0>; +impl<'a, REG> Fwmie0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FIFO 0 watermark interrupts are not enabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fwmie0::Disabled) + } + #[doc = "FIFO 0 watermark interrupts are enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fwmie0::Enabled) + } +} +#[doc = "Result FIFO 0 Overflow Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fofie0 { + #[doc = "0: FIFO 0 overflow interrupts are not enabled."] + Disabled = 0, + #[doc = "1: FIFO 0 overflow interrupts are enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fofie0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FOFIE0` reader - Result FIFO 0 Overflow Interrupt Enable"] +pub type Fofie0R = crate::BitReader; +impl Fofie0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fofie0 { + match self.bits { + false => Fofie0::Disabled, + true => Fofie0::Enabled, + } + } + #[doc = "FIFO 0 overflow interrupts are not enabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fofie0::Disabled + } + #[doc = "FIFO 0 overflow interrupts are enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fofie0::Enabled + } +} +#[doc = "Field `FOFIE0` writer - Result FIFO 0 Overflow Interrupt Enable"] +pub type Fofie0W<'a, REG> = crate::BitWriter<'a, REG, Fofie0>; +impl<'a, REG> Fofie0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FIFO 0 overflow interrupts are not enabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fofie0::Disabled) + } + #[doc = "FIFO 0 overflow interrupts are enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fofie0::Enabled) + } +} +#[doc = "Trigger Exception Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TexcIe { + #[doc = "0: Trigger exception interrupts are disabled."] + Disabled = 0, + #[doc = "1: Trigger exception interrupts are enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TexcIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEXC_IE` reader - Trigger Exception Interrupt Enable"] +pub type TexcIeR = crate::BitReader; +impl TexcIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TexcIe { + match self.bits { + false => TexcIe::Disabled, + true => TexcIe::Enabled, + } + } + #[doc = "Trigger exception interrupts are disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TexcIe::Disabled + } + #[doc = "Trigger exception interrupts are enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TexcIe::Enabled + } +} +#[doc = "Field `TEXC_IE` writer - Trigger Exception Interrupt Enable"] +pub type TexcIeW<'a, REG> = crate::BitWriter<'a, REG, TexcIe>; +impl<'a, REG> TexcIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trigger exception interrupts are disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(TexcIe::Disabled) + } + #[doc = "Trigger exception interrupts are enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(TexcIe::Enabled) + } +} +#[doc = "Trigger Completion Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TcompIe { + #[doc = "0: Trigger completion interrupts are disabled."] + Disabled = 0, + #[doc = "1: Trigger completion interrupts are enabled for trigger source 0 only."] + Trigger0CompleteEnabled = 1, + #[doc = "2: Trigger completion interrupts are enabled for trigger source 1 only."] + Trigger1CompleteEnabled = 2, + #[doc = "3: Associated trigger completion interrupts are enabled."] + TriggerXCompleteEnabled3 = 3, + #[doc = "4: Associated trigger completion interrupts are enabled."] + TriggerXCompleteEnabled4 = 4, + #[doc = "5: Associated trigger completion interrupts are enabled."] + TriggerXCompleteEnabled5 = 5, + #[doc = "6: Associated trigger completion interrupts are enabled."] + TriggerXCompleteEnabled6 = 6, + #[doc = "7: Associated trigger completion interrupts are enabled."] + TriggerXCompleteEnabled7 = 7, + #[doc = "8: Associated trigger completion interrupts are enabled."] + TriggerXCompleteEnabled8 = 8, + #[doc = "9: Associated trigger completion interrupts are enabled."] + TriggerXCompleteEnabled9 = 9, + #[doc = "15: Trigger completion interrupts are enabled for every trigger source."] + AllTriggerCompletesEnabled = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TcompIe) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TcompIe { + type Ux = u8; +} +impl crate::IsEnum for TcompIe {} +#[doc = "Field `TCOMP_IE` reader - Trigger Completion Interrupt Enable"] +pub type TcompIeR = crate::FieldReader; +impl TcompIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(TcompIe::Disabled), + 1 => Some(TcompIe::Trigger0CompleteEnabled), + 2 => Some(TcompIe::Trigger1CompleteEnabled), + 3 => Some(TcompIe::TriggerXCompleteEnabled3), + 4 => Some(TcompIe::TriggerXCompleteEnabled4), + 5 => Some(TcompIe::TriggerXCompleteEnabled5), + 6 => Some(TcompIe::TriggerXCompleteEnabled6), + 7 => Some(TcompIe::TriggerXCompleteEnabled7), + 8 => Some(TcompIe::TriggerXCompleteEnabled8), + 9 => Some(TcompIe::TriggerXCompleteEnabled9), + 15 => Some(TcompIe::AllTriggerCompletesEnabled), + _ => None, + } + } + #[doc = "Trigger completion interrupts are disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TcompIe::Disabled + } + #[doc = "Trigger completion interrupts are enabled for trigger source 0 only."] + #[inline(always)] + pub fn is_trigger_0_complete_enabled(&self) -> bool { + *self == TcompIe::Trigger0CompleteEnabled + } + #[doc = "Trigger completion interrupts are enabled for trigger source 1 only."] + #[inline(always)] + pub fn is_trigger_1_complete_enabled(&self) -> bool { + *self == TcompIe::Trigger1CompleteEnabled + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn is_trigger_x_complete_enabled_3(&self) -> bool { + *self == TcompIe::TriggerXCompleteEnabled3 + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn is_trigger_x_complete_enabled_4(&self) -> bool { + *self == TcompIe::TriggerXCompleteEnabled4 + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn is_trigger_x_complete_enabled_5(&self) -> bool { + *self == TcompIe::TriggerXCompleteEnabled5 + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn is_trigger_x_complete_enabled_6(&self) -> bool { + *self == TcompIe::TriggerXCompleteEnabled6 + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn is_trigger_x_complete_enabled_7(&self) -> bool { + *self == TcompIe::TriggerXCompleteEnabled7 + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn is_trigger_x_complete_enabled_8(&self) -> bool { + *self == TcompIe::TriggerXCompleteEnabled8 + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn is_trigger_x_complete_enabled_9(&self) -> bool { + *self == TcompIe::TriggerXCompleteEnabled9 + } + #[doc = "Trigger completion interrupts are enabled for every trigger source."] + #[inline(always)] + pub fn is_all_trigger_completes_enabled(&self) -> bool { + *self == TcompIe::AllTriggerCompletesEnabled + } +} +#[doc = "Field `TCOMP_IE` writer - Trigger Completion Interrupt Enable"] +pub type TcompIeW<'a, REG> = crate::FieldWriter<'a, REG, 4, TcompIe>; +impl<'a, REG> TcompIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Trigger completion interrupts are disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(TcompIe::Disabled) + } + #[doc = "Trigger completion interrupts are enabled for trigger source 0 only."] + #[inline(always)] + pub fn trigger_0_complete_enabled(self) -> &'a mut crate::W { + self.variant(TcompIe::Trigger0CompleteEnabled) + } + #[doc = "Trigger completion interrupts are enabled for trigger source 1 only."] + #[inline(always)] + pub fn trigger_1_complete_enabled(self) -> &'a mut crate::W { + self.variant(TcompIe::Trigger1CompleteEnabled) + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn trigger_x_complete_enabled_3(self) -> &'a mut crate::W { + self.variant(TcompIe::TriggerXCompleteEnabled3) + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn trigger_x_complete_enabled_4(self) -> &'a mut crate::W { + self.variant(TcompIe::TriggerXCompleteEnabled4) + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn trigger_x_complete_enabled_5(self) -> &'a mut crate::W { + self.variant(TcompIe::TriggerXCompleteEnabled5) + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn trigger_x_complete_enabled_6(self) -> &'a mut crate::W { + self.variant(TcompIe::TriggerXCompleteEnabled6) + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn trigger_x_complete_enabled_7(self) -> &'a mut crate::W { + self.variant(TcompIe::TriggerXCompleteEnabled7) + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn trigger_x_complete_enabled_8(self) -> &'a mut crate::W { + self.variant(TcompIe::TriggerXCompleteEnabled8) + } + #[doc = "Associated trigger completion interrupts are enabled."] + #[inline(always)] + pub fn trigger_x_complete_enabled_9(self) -> &'a mut crate::W { + self.variant(TcompIe::TriggerXCompleteEnabled9) + } + #[doc = "Trigger completion interrupts are enabled for every trigger source."] + #[inline(always)] + pub fn all_trigger_completes_enabled(self) -> &'a mut crate::W { + self.variant(TcompIe::AllTriggerCompletesEnabled) + } +} +impl R { + #[doc = "Bit 0 - FIFO 0 Watermark Interrupt Enable"] + #[inline(always)] + pub fn fwmie0(&self) -> Fwmie0R { + Fwmie0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Result FIFO 0 Overflow Interrupt Enable"] + #[inline(always)] + pub fn fofie0(&self) -> Fofie0R { + Fofie0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Trigger Exception Interrupt Enable"] + #[inline(always)] + pub fn texc_ie(&self) -> TexcIeR { + TexcIeR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 16:19 - Trigger Completion Interrupt Enable"] + #[inline(always)] + pub fn tcomp_ie(&self) -> TcompIeR { + TcompIeR::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - FIFO 0 Watermark Interrupt Enable"] + #[inline(always)] + pub fn fwmie0(&mut self) -> Fwmie0W { + Fwmie0W::new(self, 0) + } + #[doc = "Bit 1 - Result FIFO 0 Overflow Interrupt Enable"] + #[inline(always)] + pub fn fofie0(&mut self) -> Fofie0W { + Fofie0W::new(self, 1) + } + #[doc = "Bit 8 - Trigger Exception Interrupt Enable"] + #[inline(always)] + pub fn texc_ie(&mut self) -> TexcIeW { + TexcIeW::new(self, 8) + } + #[doc = "Bits 16:19 - Trigger Completion Interrupt Enable"] + #[inline(always)] + pub fn tcomp_ie(&mut self) -> TcompIeW { + TcompIeW::new(self, 16) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IeSpec; +impl crate::RegisterSpec for IeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ie::R`](R) reader structure"] +impl crate::Readable for IeSpec {} +#[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"] +impl crate::Writable for IeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IE to value 0"] +impl crate::Resettable for IeSpec {} diff --git a/mcxa276-pac/src/adc0/ofstrim.rs b/mcxa276-pac/src/adc0/ofstrim.rs new file mode 100644 index 000000000..db8115307 --- /dev/null +++ b/mcxa276-pac/src/adc0/ofstrim.rs @@ -0,0 +1,35 @@ +#[doc = "Register `OFSTRIM` reader"] +pub type R = crate::R; +#[doc = "Register `OFSTRIM` writer"] +pub type W = crate::W; +#[doc = "Field `OFSTRIM` reader - Trim for Offset"] +pub type OfstrimR = crate::FieldReader; +#[doc = "Field `OFSTRIM` writer - Trim for Offset"] +pub type OfstrimW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Trim for Offset"] + #[inline(always)] + pub fn ofstrim(&self) -> OfstrimR { + OfstrimR::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Trim for Offset"] + #[inline(always)] + pub fn ofstrim(&mut self) -> OfstrimW { + OfstrimW::new(self, 0) + } +} +#[doc = "Offset Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ofstrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ofstrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OfstrimSpec; +impl crate::RegisterSpec for OfstrimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ofstrim::R`](R) reader structure"] +impl crate::Readable for OfstrimSpec {} +#[doc = "`write(|w| ..)` method takes [`ofstrim::W`](W) writer structure"] +impl crate::Writable for OfstrimSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets OFSTRIM to value 0"] +impl crate::Resettable for OfstrimSpec {} diff --git a/mcxa276-pac/src/adc0/param.rs b/mcxa276-pac/src/adc0/param.rs new file mode 100644 index 000000000..7ad41472c --- /dev/null +++ b/mcxa276-pac/src/adc0/param.rs @@ -0,0 +1,115 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "Field `TRIG_NUM` reader - Trigger Number"] +pub type TrigNumR = crate::FieldReader; +#[doc = "Result FIFO Depth\n\nValue on reset: 8"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fifosize { + #[doc = "1: Result FIFO depth = 2 dataword."] + Entries2 = 1, + #[doc = "4: Result FIFO depth = 4 datawords."] + Entries4 = 4, + #[doc = "8: Result FIFO depth = 8 datawords."] + Entries8 = 8, + #[doc = "16: Result FIFO depth = 16 datawords."] + Entries16 = 16, + #[doc = "32: Result FIFO depth = 32 datawords."] + Entries32 = 32, + #[doc = "64: Result FIFO depth = 64 datawords."] + Entries64 = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fifosize) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fifosize { + type Ux = u8; +} +impl crate::IsEnum for Fifosize {} +#[doc = "Field `FIFOSIZE` reader - Result FIFO Depth"] +pub type FifosizeR = crate::FieldReader; +impl FifosizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Fifosize::Entries2), + 4 => Some(Fifosize::Entries4), + 8 => Some(Fifosize::Entries8), + 16 => Some(Fifosize::Entries16), + 32 => Some(Fifosize::Entries32), + 64 => Some(Fifosize::Entries64), + _ => None, + } + } + #[doc = "Result FIFO depth = 2 dataword."] + #[inline(always)] + pub fn is_entries_2(&self) -> bool { + *self == Fifosize::Entries2 + } + #[doc = "Result FIFO depth = 4 datawords."] + #[inline(always)] + pub fn is_entries_4(&self) -> bool { + *self == Fifosize::Entries4 + } + #[doc = "Result FIFO depth = 8 datawords."] + #[inline(always)] + pub fn is_entries_8(&self) -> bool { + *self == Fifosize::Entries8 + } + #[doc = "Result FIFO depth = 16 datawords."] + #[inline(always)] + pub fn is_entries_16(&self) -> bool { + *self == Fifosize::Entries16 + } + #[doc = "Result FIFO depth = 32 datawords."] + #[inline(always)] + pub fn is_entries_32(&self) -> bool { + *self == Fifosize::Entries32 + } + #[doc = "Result FIFO depth = 64 datawords."] + #[inline(always)] + pub fn is_entries_64(&self) -> bool { + *self == Fifosize::Entries64 + } +} +#[doc = "Field `CV_NUM` reader - Compare Value Number"] +pub type CvNumR = crate::FieldReader; +#[doc = "Field `CMD_NUM` reader - Command Buffer Number"] +pub type CmdNumR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Trigger Number"] + #[inline(always)] + pub fn trig_num(&self) -> TrigNumR { + TrigNumR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Result FIFO Depth"] + #[inline(always)] + pub fn fifosize(&self) -> FifosizeR { + FifosizeR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Compare Value Number"] + #[inline(always)] + pub fn cv_num(&self) -> CvNumR { + CvNumR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Command Buffer Number"] + #[inline(always)] + pub fn cmd_num(&self) -> CmdNumR { + CmdNumR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x0707_0804"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x0707_0804; +} diff --git a/mcxa276-pac/src/adc0/pause.rs b/mcxa276-pac/src/adc0/pause.rs new file mode 100644 index 000000000..2f3ea34b7 --- /dev/null +++ b/mcxa276-pac/src/adc0/pause.rs @@ -0,0 +1,98 @@ +#[doc = "Register `PAUSE` reader"] +pub type R = crate::R; +#[doc = "Register `PAUSE` writer"] +pub type W = crate::W; +#[doc = "Field `PAUSEDLY` reader - Pause Delay"] +pub type PausedlyR = crate::FieldReader; +#[doc = "Field `PAUSEDLY` writer - Pause Delay"] +pub type PausedlyW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "PAUSE Option Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pauseen { + #[doc = "0: Pause operation disabled"] + Disabled = 0, + #[doc = "1: Pause operation enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pauseen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PAUSEEN` reader - PAUSE Option Enable"] +pub type PauseenR = crate::BitReader; +impl PauseenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pauseen { + match self.bits { + false => Pauseen::Disabled, + true => Pauseen::Enabled, + } + } + #[doc = "Pause operation disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pauseen::Disabled + } + #[doc = "Pause operation enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pauseen::Enabled + } +} +#[doc = "Field `PAUSEEN` writer - PAUSE Option Enable"] +pub type PauseenW<'a, REG> = crate::BitWriter<'a, REG, Pauseen>; +impl<'a, REG> PauseenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pause operation disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pauseen::Disabled) + } + #[doc = "Pause operation enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pauseen::Enabled) + } +} +impl R { + #[doc = "Bits 0:8 - Pause Delay"] + #[inline(always)] + pub fn pausedly(&self) -> PausedlyR { + PausedlyR::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bit 31 - PAUSE Option Enable"] + #[inline(always)] + pub fn pauseen(&self) -> PauseenR { + PauseenR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Pause Delay"] + #[inline(always)] + pub fn pausedly(&mut self) -> PausedlyW { + PausedlyW::new(self, 0) + } + #[doc = "Bit 31 - PAUSE Option Enable"] + #[inline(always)] + pub fn pauseen(&mut self) -> PauseenW { + PauseenW::new(self, 31) + } +} +#[doc = "Pause Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PauseSpec; +impl crate::RegisterSpec for PauseSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pause::R`](R) reader structure"] +impl crate::Readable for PauseSpec {} +#[doc = "`write(|w| ..)` method takes [`pause::W`](W) writer structure"] +impl crate::Writable for PauseSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PAUSE to value 0"] +impl crate::Resettable for PauseSpec {} diff --git a/mcxa276-pac/src/adc0/resfifo0.rs b/mcxa276-pac/src/adc0/resfifo0.rs new file mode 100644 index 000000000..f90df21ac --- /dev/null +++ b/mcxa276-pac/src/adc0/resfifo0.rs @@ -0,0 +1,338 @@ +#[doc = "Register `RESFIFO0` reader"] +pub type R = crate::R; +#[doc = "Field `D` reader - Data Result"] +pub type DR = crate::FieldReader; +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tsrc { + #[doc = "0: Trigger source 0 initiated this conversion."] + Trigger0 = 0, + #[doc = "1: Trigger source 1 initiated this conversion."] + Trigger1 = 1, + #[doc = "2: Trigger source 2 initiated this conversion."] + Trigger2 = 2, + #[doc = "3: Trigger source 3 initiated this conversion."] + Trigger3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tsrc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tsrc { + type Ux = u8; +} +impl crate::IsEnum for Tsrc {} +#[doc = "Field `TSRC` reader - Trigger Source"] +pub type TsrcR = crate::FieldReader; +impl TsrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tsrc { + match self.bits { + 0 => Tsrc::Trigger0, + 1 => Tsrc::Trigger1, + 2 => Tsrc::Trigger2, + 3 => Tsrc::Trigger3, + _ => unreachable!(), + } + } + #[doc = "Trigger source 0 initiated this conversion."] + #[inline(always)] + pub fn is_trigger_0(&self) -> bool { + *self == Tsrc::Trigger0 + } + #[doc = "Trigger source 1 initiated this conversion."] + #[inline(always)] + pub fn is_trigger_1(&self) -> bool { + *self == Tsrc::Trigger1 + } + #[doc = "Trigger source 2 initiated this conversion."] + #[inline(always)] + pub fn is_trigger_2(&self) -> bool { + *self == Tsrc::Trigger2 + } + #[doc = "Trigger source 3 initiated this conversion."] + #[inline(always)] + pub fn is_trigger_3(&self) -> bool { + *self == Tsrc::Trigger3 + } +} +#[doc = "Loop Count Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Loopcnt { + #[doc = "0: Result is from initial conversion in command."] + Result1 = 0, + #[doc = "1: Result is from second conversion in command."] + Result2 = 1, + #[doc = "2: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult2 = 2, + #[doc = "3: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult3 = 3, + #[doc = "4: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult4 = 4, + #[doc = "5: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult5 = 5, + #[doc = "6: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult6 = 6, + #[doc = "7: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult7 = 7, + #[doc = "8: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult8 = 8, + #[doc = "9: Result is from LOOPCNT+1 conversion in command."] + CorrespondingResult9 = 9, + #[doc = "15: Result is from 16th conversion in command."] + Result16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Loopcnt) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Loopcnt { + type Ux = u8; +} +impl crate::IsEnum for Loopcnt {} +#[doc = "Field `LOOPCNT` reader - Loop Count Value"] +pub type LoopcntR = crate::FieldReader; +impl LoopcntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Loopcnt::Result1), + 1 => Some(Loopcnt::Result2), + 2 => Some(Loopcnt::CorrespondingResult2), + 3 => Some(Loopcnt::CorrespondingResult3), + 4 => Some(Loopcnt::CorrespondingResult4), + 5 => Some(Loopcnt::CorrespondingResult5), + 6 => Some(Loopcnt::CorrespondingResult6), + 7 => Some(Loopcnt::CorrespondingResult7), + 8 => Some(Loopcnt::CorrespondingResult8), + 9 => Some(Loopcnt::CorrespondingResult9), + 15 => Some(Loopcnt::Result16), + _ => None, + } + } + #[doc = "Result is from initial conversion in command."] + #[inline(always)] + pub fn is_result_1(&self) -> bool { + *self == Loopcnt::Result1 + } + #[doc = "Result is from second conversion in command."] + #[inline(always)] + pub fn is_result_2(&self) -> bool { + *self == Loopcnt::Result2 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_2(&self) -> bool { + *self == Loopcnt::CorrespondingResult2 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_3(&self) -> bool { + *self == Loopcnt::CorrespondingResult3 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_4(&self) -> bool { + *self == Loopcnt::CorrespondingResult4 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_5(&self) -> bool { + *self == Loopcnt::CorrespondingResult5 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_6(&self) -> bool { + *self == Loopcnt::CorrespondingResult6 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_7(&self) -> bool { + *self == Loopcnt::CorrespondingResult7 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_8(&self) -> bool { + *self == Loopcnt::CorrespondingResult8 + } + #[doc = "Result is from LOOPCNT+1 conversion in command."] + #[inline(always)] + pub fn is_corresponding_result_9(&self) -> bool { + *self == Loopcnt::CorrespondingResult9 + } + #[doc = "Result is from 16th conversion in command."] + #[inline(always)] + pub fn is_result_16(&self) -> bool { + *self == Loopcnt::Result16 + } +} +#[doc = "Command Buffer Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmdsrc { + #[doc = "0: Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer."] + NotValid = 0, + #[doc = "1: CMD1 buffer used as control settings for this conversion."] + Cmd1 = 1, + #[doc = "2: Corresponding command buffer used as control settings for this conversion."] + CorrespondingCmd2 = 2, + #[doc = "3: Corresponding command buffer used as control settings for this conversion."] + CorrespondingCmd3 = 3, + #[doc = "4: Corresponding command buffer used as control settings for this conversion."] + CorrespondingCmd4 = 4, + #[doc = "5: Corresponding command buffer used as control settings for this conversion."] + CorrespondingCmd5 = 5, + #[doc = "6: Corresponding command buffer used as control settings for this conversion."] + CorrespondingCmd6 = 6, + #[doc = "7: CMD7 buffer used as control settings for this conversion."] + Cmd7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmdsrc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmdsrc { + type Ux = u8; +} +impl crate::IsEnum for Cmdsrc {} +#[doc = "Field `CMDSRC` reader - Command Buffer Source"] +pub type CmdsrcR = crate::FieldReader; +impl CmdsrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmdsrc { + match self.bits { + 0 => Cmdsrc::NotValid, + 1 => Cmdsrc::Cmd1, + 2 => Cmdsrc::CorrespondingCmd2, + 3 => Cmdsrc::CorrespondingCmd3, + 4 => Cmdsrc::CorrespondingCmd4, + 5 => Cmdsrc::CorrespondingCmd5, + 6 => Cmdsrc::CorrespondingCmd6, + 7 => Cmdsrc::Cmd7, + _ => unreachable!(), + } + } + #[doc = "Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer."] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Cmdsrc::NotValid + } + #[doc = "CMD1 buffer used as control settings for this conversion."] + #[inline(always)] + pub fn is_cmd1(&self) -> bool { + *self == Cmdsrc::Cmd1 + } + #[doc = "Corresponding command buffer used as control settings for this conversion."] + #[inline(always)] + pub fn is_corresponding_cmd_2(&self) -> bool { + *self == Cmdsrc::CorrespondingCmd2 + } + #[doc = "Corresponding command buffer used as control settings for this conversion."] + #[inline(always)] + pub fn is_corresponding_cmd_3(&self) -> bool { + *self == Cmdsrc::CorrespondingCmd3 + } + #[doc = "Corresponding command buffer used as control settings for this conversion."] + #[inline(always)] + pub fn is_corresponding_cmd_4(&self) -> bool { + *self == Cmdsrc::CorrespondingCmd4 + } + #[doc = "Corresponding command buffer used as control settings for this conversion."] + #[inline(always)] + pub fn is_corresponding_cmd_5(&self) -> bool { + *self == Cmdsrc::CorrespondingCmd5 + } + #[doc = "Corresponding command buffer used as control settings for this conversion."] + #[inline(always)] + pub fn is_corresponding_cmd_6(&self) -> bool { + *self == Cmdsrc::CorrespondingCmd6 + } + #[doc = "CMD7 buffer used as control settings for this conversion."] + #[inline(always)] + pub fn is_cmd7(&self) -> bool { + *self == Cmdsrc::Cmd7 + } +} +#[doc = "FIFO Entry is Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Valid { + #[doc = "0: FIFO is empty. Discard any read from RESFIFO."] + NotValid = 0, + #[doc = "1: FIFO record read from RESFIFO is valid."] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Valid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VALID` reader - FIFO Entry is Valid"] +pub type ValidR = crate::BitReader; +impl ValidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Valid { + match self.bits { + false => Valid::NotValid, + true => Valid::Valid, + } + } + #[doc = "FIFO is empty. Discard any read from RESFIFO."] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Valid::NotValid + } + #[doc = "FIFO record read from RESFIFO is valid."] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Valid::Valid + } +} +impl R { + #[doc = "Bits 0:15 - Data Result"] + #[inline(always)] + pub fn d(&self) -> DR { + DR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:17 - Trigger Source"] + #[inline(always)] + pub fn tsrc(&self) -> TsrcR { + TsrcR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 20:23 - Loop Count Value"] + #[inline(always)] + pub fn loopcnt(&self) -> LoopcntR { + LoopcntR::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:26 - Command Buffer Source"] + #[inline(always)] + pub fn cmdsrc(&self) -> CmdsrcR { + CmdsrcR::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 31 - FIFO Entry is Valid"] + #[inline(always)] + pub fn valid(&self) -> ValidR { + ValidR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Data Result FIFO Register\n\nYou can [`read`](crate::Reg::read) this register and get [`resfifo0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Resfifo0Spec; +impl crate::RegisterSpec for Resfifo0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`resfifo0::R`](R) reader structure"] +impl crate::Readable for Resfifo0Spec {} +#[doc = "`reset()` method sets RESFIFO0 to value 0"] +impl crate::Resettable for Resfifo0Spec {} diff --git a/mcxa276-pac/src/adc0/stat.rs b/mcxa276-pac/src/adc0/stat.rs new file mode 100644 index 000000000..785b363cf --- /dev/null +++ b/mcxa276-pac/src/adc0/stat.rs @@ -0,0 +1,492 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Register `STAT` writer"] +pub type W = crate::W; +#[doc = "Result FIFO 0 Ready Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdy0 { + #[doc = "0: Result FIFO 0 data level not above watermark level."] + BelowThreshold = 0, + #[doc = "1: Result FIFO 0 holding data above watermark level."] + AboveThreshold = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdy0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDY0` reader - Result FIFO 0 Ready Flag"] +pub type Rdy0R = crate::BitReader; +impl Rdy0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdy0 { + match self.bits { + false => Rdy0::BelowThreshold, + true => Rdy0::AboveThreshold, + } + } + #[doc = "Result FIFO 0 data level not above watermark level."] + #[inline(always)] + pub fn is_below_threshold(&self) -> bool { + *self == Rdy0::BelowThreshold + } + #[doc = "Result FIFO 0 holding data above watermark level."] + #[inline(always)] + pub fn is_above_threshold(&self) -> bool { + *self == Rdy0::AboveThreshold + } +} +#[doc = "Result FIFO 0 Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fof0 { + #[doc = "0: No result FIFO 0 overflow has occurred since the last time the flag was cleared."] + NoOverflow = 0, + #[doc = "1: At least one result FIFO 0 overflow has occurred since the last time the flag was cleared."] + OverflowDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fof0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FOF0` reader - Result FIFO 0 Overflow Flag"] +pub type Fof0R = crate::BitReader; +impl Fof0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fof0 { + match self.bits { + false => Fof0::NoOverflow, + true => Fof0::OverflowDetected, + } + } + #[doc = "No result FIFO 0 overflow has occurred since the last time the flag was cleared."] + #[inline(always)] + pub fn is_no_overflow(&self) -> bool { + *self == Fof0::NoOverflow + } + #[doc = "At least one result FIFO 0 overflow has occurred since the last time the flag was cleared."] + #[inline(always)] + pub fn is_overflow_detected(&self) -> bool { + *self == Fof0::OverflowDetected + } +} +#[doc = "Field `FOF0` writer - Result FIFO 0 Overflow Flag"] +pub type Fof0W<'a, REG> = crate::BitWriter1C<'a, REG, Fof0>; +impl<'a, REG> Fof0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No result FIFO 0 overflow has occurred since the last time the flag was cleared."] + #[inline(always)] + pub fn no_overflow(self) -> &'a mut crate::W { + self.variant(Fof0::NoOverflow) + } + #[doc = "At least one result FIFO 0 overflow has occurred since the last time the flag was cleared."] + #[inline(always)] + pub fn overflow_detected(self) -> &'a mut crate::W { + self.variant(Fof0::OverflowDetected) + } +} +#[doc = "Interrupt Flag For High Priority Trigger Exception\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TexcInt { + #[doc = "0: No trigger exceptions have occurred."] + NoException = 0, + #[doc = "1: A trigger exception has occurred and is pending acknowledgement."] + ExceptionDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TexcInt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEXC_INT` reader - Interrupt Flag For High Priority Trigger Exception"] +pub type TexcIntR = crate::BitReader; +impl TexcIntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TexcInt { + match self.bits { + false => TexcInt::NoException, + true => TexcInt::ExceptionDetected, + } + } + #[doc = "No trigger exceptions have occurred."] + #[inline(always)] + pub fn is_no_exception(&self) -> bool { + *self == TexcInt::NoException + } + #[doc = "A trigger exception has occurred and is pending acknowledgement."] + #[inline(always)] + pub fn is_exception_detected(&self) -> bool { + *self == TexcInt::ExceptionDetected + } +} +#[doc = "Field `TEXC_INT` writer - Interrupt Flag For High Priority Trigger Exception"] +pub type TexcIntW<'a, REG> = crate::BitWriter1C<'a, REG, TexcInt>; +impl<'a, REG> TexcIntW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No trigger exceptions have occurred."] + #[inline(always)] + pub fn no_exception(self) -> &'a mut crate::W { + self.variant(TexcInt::NoException) + } + #[doc = "A trigger exception has occurred and is pending acknowledgement."] + #[inline(always)] + pub fn exception_detected(self) -> &'a mut crate::W { + self.variant(TexcInt::ExceptionDetected) + } +} +#[doc = "Interrupt Flag For Trigger Completion\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TcompInt { + #[doc = "0: Either IE\\[TCOMP_IE\\] is set to 0, or no trigger sequences have run to completion."] + FlagClear = 0, + #[doc = "1: Trigger sequence has been completed and all data is stored in the associated FIFO."] + CompletionDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TcompInt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCOMP_INT` reader - Interrupt Flag For Trigger Completion"] +pub type TcompIntR = crate::BitReader; +impl TcompIntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TcompInt { + match self.bits { + false => TcompInt::FlagClear, + true => TcompInt::CompletionDetected, + } + } + #[doc = "Either IE\\[TCOMP_IE\\] is set to 0, or no trigger sequences have run to completion."] + #[inline(always)] + pub fn is_flag_clear(&self) -> bool { + *self == TcompInt::FlagClear + } + #[doc = "Trigger sequence has been completed and all data is stored in the associated FIFO."] + #[inline(always)] + pub fn is_completion_detected(&self) -> bool { + *self == TcompInt::CompletionDetected + } +} +#[doc = "Field `TCOMP_INT` writer - Interrupt Flag For Trigger Completion"] +pub type TcompIntW<'a, REG> = crate::BitWriter1C<'a, REG, TcompInt>; +impl<'a, REG> TcompIntW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Either IE\\[TCOMP_IE\\] is set to 0, or no trigger sequences have run to completion."] + #[inline(always)] + pub fn flag_clear(self) -> &'a mut crate::W { + self.variant(TcompInt::FlagClear) + } + #[doc = "Trigger sequence has been completed and all data is stored in the associated FIFO."] + #[inline(always)] + pub fn completion_detected(self) -> &'a mut crate::W { + self.variant(TcompInt::CompletionDetected) + } +} +#[doc = "Calibration Ready\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CalRdy { + #[doc = "0: Calibration is incomplete or hasn't been ran."] + NotSet = 0, + #[doc = "1: The ADC is calibrated."] + HardwareCalStepCompleted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CalRdy) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAL_RDY` reader - Calibration Ready"] +pub type CalRdyR = crate::BitReader; +impl CalRdyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CalRdy { + match self.bits { + false => CalRdy::NotSet, + true => CalRdy::HardwareCalStepCompleted, + } + } + #[doc = "Calibration is incomplete or hasn't been ran."] + #[inline(always)] + pub fn is_not_set(&self) -> bool { + *self == CalRdy::NotSet + } + #[doc = "The ADC is calibrated."] + #[inline(always)] + pub fn is_hardware_cal_step_completed(&self) -> bool { + *self == CalRdy::HardwareCalStepCompleted + } +} +#[doc = "ADC Active\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum AdcActive { + #[doc = "0: The ADC is IDLE. There are no pending triggers to service and no active commands are being processed."] + NotActive = 0, + #[doc = "1: The ADC is processing a conversion, running through the power up delay, or servicing a trigger."] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: AdcActive) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC_ACTIVE` reader - ADC Active"] +pub type AdcActiveR = crate::BitReader; +impl AdcActiveR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> AdcActive { + match self.bits { + false => AdcActive::NotActive, + true => AdcActive::Busy, + } + } + #[doc = "The ADC is IDLE. There are no pending triggers to service and no active commands are being processed."] + #[inline(always)] + pub fn is_not_active(&self) -> bool { + *self == AdcActive::NotActive + } + #[doc = "The ADC is processing a conversion, running through the power up delay, or servicing a trigger."] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == AdcActive::Busy + } +} +#[doc = "Trigger Active\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trgact { + #[doc = "0: Command (sequence) associated with Trigger 0 currently being executed."] + Trig0 = 0, + #[doc = "1: Command (sequence) associated with Trigger 1 currently being executed."] + Trig1 = 1, + #[doc = "2: Command (sequence) associated with Trigger 2 currently being executed."] + Trig2 = 2, + #[doc = "3: Command (sequence) associated with Trigger 3 currently being executed."] + Trig3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trgact) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trgact { + type Ux = u8; +} +impl crate::IsEnum for Trgact {} +#[doc = "Field `TRGACT` reader - Trigger Active"] +pub type TrgactR = crate::FieldReader; +impl TrgactR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgact { + match self.bits { + 0 => Trgact::Trig0, + 1 => Trgact::Trig1, + 2 => Trgact::Trig2, + 3 => Trgact::Trig3, + _ => unreachable!(), + } + } + #[doc = "Command (sequence) associated with Trigger 0 currently being executed."] + #[inline(always)] + pub fn is_trig_0(&self) -> bool { + *self == Trgact::Trig0 + } + #[doc = "Command (sequence) associated with Trigger 1 currently being executed."] + #[inline(always)] + pub fn is_trig_1(&self) -> bool { + *self == Trgact::Trig1 + } + #[doc = "Command (sequence) associated with Trigger 2 currently being executed."] + #[inline(always)] + pub fn is_trig_2(&self) -> bool { + *self == Trgact::Trig2 + } + #[doc = "Command (sequence) associated with Trigger 3 currently being executed."] + #[inline(always)] + pub fn is_trig_3(&self) -> bool { + *self == Trgact::Trig3 + } +} +#[doc = "Command Active\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmdact { + #[doc = "0: No command is currently in progress."] + NoCommandActive = 0, + #[doc = "1: Command 1 currently being executed."] + Command1 = 1, + #[doc = "2: Command 2 currently being executed."] + Command2 = 2, + #[doc = "3: Associated command number is currently being executed."] + CommandX3 = 3, + #[doc = "4: Associated command number is currently being executed."] + CommandX4 = 4, + #[doc = "5: Associated command number is currently being executed."] + CommandX5 = 5, + #[doc = "6: Associated command number is currently being executed."] + CommandX6 = 6, + #[doc = "7: Associated command number is currently being executed."] + CommandX7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmdact) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmdact { + type Ux = u8; +} +impl crate::IsEnum for Cmdact {} +#[doc = "Field `CMDACT` reader - Command Active"] +pub type CmdactR = crate::FieldReader; +impl CmdactR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmdact { + match self.bits { + 0 => Cmdact::NoCommandActive, + 1 => Cmdact::Command1, + 2 => Cmdact::Command2, + 3 => Cmdact::CommandX3, + 4 => Cmdact::CommandX4, + 5 => Cmdact::CommandX5, + 6 => Cmdact::CommandX6, + 7 => Cmdact::CommandX7, + _ => unreachable!(), + } + } + #[doc = "No command is currently in progress."] + #[inline(always)] + pub fn is_no_command_active(&self) -> bool { + *self == Cmdact::NoCommandActive + } + #[doc = "Command 1 currently being executed."] + #[inline(always)] + pub fn is_command_1(&self) -> bool { + *self == Cmdact::Command1 + } + #[doc = "Command 2 currently being executed."] + #[inline(always)] + pub fn is_command_2(&self) -> bool { + *self == Cmdact::Command2 + } + #[doc = "Associated command number is currently being executed."] + #[inline(always)] + pub fn is_command_x_3(&self) -> bool { + *self == Cmdact::CommandX3 + } + #[doc = "Associated command number is currently being executed."] + #[inline(always)] + pub fn is_command_x_4(&self) -> bool { + *self == Cmdact::CommandX4 + } + #[doc = "Associated command number is currently being executed."] + #[inline(always)] + pub fn is_command_x_5(&self) -> bool { + *self == Cmdact::CommandX5 + } + #[doc = "Associated command number is currently being executed."] + #[inline(always)] + pub fn is_command_x_6(&self) -> bool { + *self == Cmdact::CommandX6 + } + #[doc = "Associated command number is currently being executed."] + #[inline(always)] + pub fn is_command_x_7(&self) -> bool { + *self == Cmdact::CommandX7 + } +} +impl R { + #[doc = "Bit 0 - Result FIFO 0 Ready Flag"] + #[inline(always)] + pub fn rdy0(&self) -> Rdy0R { + Rdy0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Result FIFO 0 Overflow Flag"] + #[inline(always)] + pub fn fof0(&self) -> Fof0R { + Fof0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt Flag For High Priority Trigger Exception"] + #[inline(always)] + pub fn texc_int(&self) -> TexcIntR { + TexcIntR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt Flag For Trigger Completion"] + #[inline(always)] + pub fn tcomp_int(&self) -> TcompIntR { + TcompIntR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Calibration Ready"] + #[inline(always)] + pub fn cal_rdy(&self) -> CalRdyR { + CalRdyR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - ADC Active"] + #[inline(always)] + pub fn adc_active(&self) -> AdcActiveR { + AdcActiveR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:17 - Trigger Active"] + #[inline(always)] + pub fn trgact(&self) -> TrgactR { + TrgactR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 24:26 - Command Active"] + #[inline(always)] + pub fn cmdact(&self) -> CmdactR { + CmdactR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bit 1 - Result FIFO 0 Overflow Flag"] + #[inline(always)] + pub fn fof0(&mut self) -> Fof0W { + Fof0W::new(self, 1) + } + #[doc = "Bit 8 - Interrupt Flag For High Priority Trigger Exception"] + #[inline(always)] + pub fn texc_int(&mut self) -> TexcIntW { + TexcIntW::new(self, 8) + } + #[doc = "Bit 9 - Interrupt Flag For Trigger Completion"] + #[inline(always)] + pub fn tcomp_int(&mut self) -> TcompIntW { + TcompIntW::new(self, 9) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] +impl crate::Writable for StatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0302; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for StatSpec {} diff --git a/mcxa276-pac/src/adc0/swtrig.rs b/mcxa276-pac/src/adc0/swtrig.rs new file mode 100644 index 000000000..9b9a45a94 --- /dev/null +++ b/mcxa276-pac/src/adc0/swtrig.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SWTRIG` reader"] +pub type R = crate::R; +#[doc = "Register `SWTRIG` writer"] +pub type W = crate::W; +#[doc = "Software Trigger 0 Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swt0 { + #[doc = "0: No trigger 0 event generated."] + NoTrigger = 0, + #[doc = "1: Trigger 0 event generated."] + InitiateTrigger0 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swt0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWT0` reader - Software Trigger 0 Event"] +pub type Swt0R = crate::BitReader; +impl Swt0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swt0 { + match self.bits { + false => Swt0::NoTrigger, + true => Swt0::InitiateTrigger0, + } + } + #[doc = "No trigger 0 event generated."] + #[inline(always)] + pub fn is_no_trigger(&self) -> bool { + *self == Swt0::NoTrigger + } + #[doc = "Trigger 0 event generated."] + #[inline(always)] + pub fn is_initiate_trigger_0(&self) -> bool { + *self == Swt0::InitiateTrigger0 + } +} +#[doc = "Field `SWT0` writer - Software Trigger 0 Event"] +pub type Swt0W<'a, REG> = crate::BitWriter<'a, REG, Swt0>; +impl<'a, REG> Swt0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No trigger 0 event generated."] + #[inline(always)] + pub fn no_trigger(self) -> &'a mut crate::W { + self.variant(Swt0::NoTrigger) + } + #[doc = "Trigger 0 event generated."] + #[inline(always)] + pub fn initiate_trigger_0(self) -> &'a mut crate::W { + self.variant(Swt0::InitiateTrigger0) + } +} +#[doc = "Software Trigger 1 Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swt1 { + #[doc = "0: No trigger 1 event generated."] + NoTrigger = 0, + #[doc = "1: Trigger 1 event generated."] + InitiateTrigger1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swt1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWT1` reader - Software Trigger 1 Event"] +pub type Swt1R = crate::BitReader; +impl Swt1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swt1 { + match self.bits { + false => Swt1::NoTrigger, + true => Swt1::InitiateTrigger1, + } + } + #[doc = "No trigger 1 event generated."] + #[inline(always)] + pub fn is_no_trigger(&self) -> bool { + *self == Swt1::NoTrigger + } + #[doc = "Trigger 1 event generated."] + #[inline(always)] + pub fn is_initiate_trigger_1(&self) -> bool { + *self == Swt1::InitiateTrigger1 + } +} +#[doc = "Field `SWT1` writer - Software Trigger 1 Event"] +pub type Swt1W<'a, REG> = crate::BitWriter<'a, REG, Swt1>; +impl<'a, REG> Swt1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No trigger 1 event generated."] + #[inline(always)] + pub fn no_trigger(self) -> &'a mut crate::W { + self.variant(Swt1::NoTrigger) + } + #[doc = "Trigger 1 event generated."] + #[inline(always)] + pub fn initiate_trigger_1(self) -> &'a mut crate::W { + self.variant(Swt1::InitiateTrigger1) + } +} +#[doc = "Software Trigger 2 Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swt2 { + #[doc = "0: No trigger 2 event generated."] + NoTrigger = 0, + #[doc = "1: Trigger 2 event generated."] + InitiateTrigger2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swt2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWT2` reader - Software Trigger 2 Event"] +pub type Swt2R = crate::BitReader; +impl Swt2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swt2 { + match self.bits { + false => Swt2::NoTrigger, + true => Swt2::InitiateTrigger2, + } + } + #[doc = "No trigger 2 event generated."] + #[inline(always)] + pub fn is_no_trigger(&self) -> bool { + *self == Swt2::NoTrigger + } + #[doc = "Trigger 2 event generated."] + #[inline(always)] + pub fn is_initiate_trigger_2(&self) -> bool { + *self == Swt2::InitiateTrigger2 + } +} +#[doc = "Field `SWT2` writer - Software Trigger 2 Event"] +pub type Swt2W<'a, REG> = crate::BitWriter<'a, REG, Swt2>; +impl<'a, REG> Swt2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No trigger 2 event generated."] + #[inline(always)] + pub fn no_trigger(self) -> &'a mut crate::W { + self.variant(Swt2::NoTrigger) + } + #[doc = "Trigger 2 event generated."] + #[inline(always)] + pub fn initiate_trigger_2(self) -> &'a mut crate::W { + self.variant(Swt2::InitiateTrigger2) + } +} +#[doc = "Software Trigger 3 Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swt3 { + #[doc = "0: No trigger 3 event generated."] + NoTrigger = 0, + #[doc = "1: Trigger 3 event generated."] + InitiateTrigger3 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swt3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWT3` reader - Software Trigger 3 Event"] +pub type Swt3R = crate::BitReader; +impl Swt3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swt3 { + match self.bits { + false => Swt3::NoTrigger, + true => Swt3::InitiateTrigger3, + } + } + #[doc = "No trigger 3 event generated."] + #[inline(always)] + pub fn is_no_trigger(&self) -> bool { + *self == Swt3::NoTrigger + } + #[doc = "Trigger 3 event generated."] + #[inline(always)] + pub fn is_initiate_trigger_3(&self) -> bool { + *self == Swt3::InitiateTrigger3 + } +} +#[doc = "Field `SWT3` writer - Software Trigger 3 Event"] +pub type Swt3W<'a, REG> = crate::BitWriter<'a, REG, Swt3>; +impl<'a, REG> Swt3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No trigger 3 event generated."] + #[inline(always)] + pub fn no_trigger(self) -> &'a mut crate::W { + self.variant(Swt3::NoTrigger) + } + #[doc = "Trigger 3 event generated."] + #[inline(always)] + pub fn initiate_trigger_3(self) -> &'a mut crate::W { + self.variant(Swt3::InitiateTrigger3) + } +} +impl R { + #[doc = "Bit 0 - Software Trigger 0 Event"] + #[inline(always)] + pub fn swt0(&self) -> Swt0R { + Swt0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software Trigger 1 Event"] + #[inline(always)] + pub fn swt1(&self) -> Swt1R { + Swt1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Software Trigger 2 Event"] + #[inline(always)] + pub fn swt2(&self) -> Swt2R { + Swt2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Software Trigger 3 Event"] + #[inline(always)] + pub fn swt3(&self) -> Swt3R { + Swt3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Trigger 0 Event"] + #[inline(always)] + pub fn swt0(&mut self) -> Swt0W { + Swt0W::new(self, 0) + } + #[doc = "Bit 1 - Software Trigger 1 Event"] + #[inline(always)] + pub fn swt1(&mut self) -> Swt1W { + Swt1W::new(self, 1) + } + #[doc = "Bit 2 - Software Trigger 2 Event"] + #[inline(always)] + pub fn swt2(&mut self) -> Swt2W { + Swt2W::new(self, 2) + } + #[doc = "Bit 3 - Software Trigger 3 Event"] + #[inline(always)] + pub fn swt3(&mut self) -> Swt3W { + Swt3W::new(self, 3) + } +} +#[doc = "Software Trigger Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swtrig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwtrigSpec; +impl crate::RegisterSpec for SwtrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`swtrig::R`](R) reader structure"] +impl crate::Readable for SwtrigSpec {} +#[doc = "`write(|w| ..)` method takes [`swtrig::W`](W) writer structure"] +impl crate::Writable for SwtrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SwtrigSpec {} diff --git a/mcxa276-pac/src/adc0/tctrl.rs b/mcxa276-pac/src/adc0/tctrl.rs new file mode 100644 index 000000000..148e1ca68 --- /dev/null +++ b/mcxa276-pac/src/adc0/tctrl.rs @@ -0,0 +1,370 @@ +#[doc = "Register `TCTRL[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `TCTRL[%s]` writer"] +pub type W = crate::W; +#[doc = "Trigger Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hten { + #[doc = "0: Hardware trigger source disabled"] + Disabled = 0, + #[doc = "1: Hardware trigger source enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HTEN` reader - Trigger Enable"] +pub type HtenR = crate::BitReader; +impl HtenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hten { + match self.bits { + false => Hten::Disabled, + true => Hten::Enabled, + } + } + #[doc = "Hardware trigger source disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Hten::Disabled + } + #[doc = "Hardware trigger source enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Hten::Enabled + } +} +#[doc = "Field `HTEN` writer - Trigger Enable"] +pub type HtenW<'a, REG> = crate::BitWriter<'a, REG, Hten>; +impl<'a, REG> HtenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Hardware trigger source disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Hten::Disabled) + } + #[doc = "Hardware trigger source enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Hten::Enabled) + } +} +#[doc = "Trigger Priority Setting\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tpri { + #[doc = "0: Set to highest priority, Level 1"] + HighestPriority = 0, + #[doc = "1: Set to corresponding priority level"] + CorrespondingLowerPriority1 = 1, + #[doc = "2: Set to corresponding priority level"] + CorrespondingLowerPriority2 = 2, + #[doc = "3: Set to lowest priority, Level 4"] + LowestPriority = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tpri) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tpri { + type Ux = u8; +} +impl crate::IsEnum for Tpri {} +#[doc = "Field `TPRI` reader - Trigger Priority Setting"] +pub type TpriR = crate::FieldReader; +impl TpriR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpri { + match self.bits { + 0 => Tpri::HighestPriority, + 1 => Tpri::CorrespondingLowerPriority1, + 2 => Tpri::CorrespondingLowerPriority2, + 3 => Tpri::LowestPriority, + _ => unreachable!(), + } + } + #[doc = "Set to highest priority, Level 1"] + #[inline(always)] + pub fn is_highest_priority(&self) -> bool { + *self == Tpri::HighestPriority + } + #[doc = "Set to corresponding priority level"] + #[inline(always)] + pub fn is_corresponding_lower_priority_1(&self) -> bool { + *self == Tpri::CorrespondingLowerPriority1 + } + #[doc = "Set to corresponding priority level"] + #[inline(always)] + pub fn is_corresponding_lower_priority_2(&self) -> bool { + *self == Tpri::CorrespondingLowerPriority2 + } + #[doc = "Set to lowest priority, Level 4"] + #[inline(always)] + pub fn is_lowest_priority(&self) -> bool { + *self == Tpri::LowestPriority + } +} +#[doc = "Field `TPRI` writer - Trigger Priority Setting"] +pub type TpriW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tpri, crate::Safe>; +impl<'a, REG> TpriW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Set to highest priority, Level 1"] + #[inline(always)] + pub fn highest_priority(self) -> &'a mut crate::W { + self.variant(Tpri::HighestPriority) + } + #[doc = "Set to corresponding priority level"] + #[inline(always)] + pub fn corresponding_lower_priority_1(self) -> &'a mut crate::W { + self.variant(Tpri::CorrespondingLowerPriority1) + } + #[doc = "Set to corresponding priority level"] + #[inline(always)] + pub fn corresponding_lower_priority_2(self) -> &'a mut crate::W { + self.variant(Tpri::CorrespondingLowerPriority2) + } + #[doc = "Set to lowest priority, Level 4"] + #[inline(always)] + pub fn lowest_priority(self) -> &'a mut crate::W { + self.variant(Tpri::LowestPriority) + } +} +#[doc = "Field `RSYNC` reader - Trigger Resync"] +pub type RsyncR = crate::BitReader; +#[doc = "Field `RSYNC` writer - Trigger Resync"] +pub type RsyncW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TDLY` reader - Trigger Delay Select"] +pub type TdlyR = crate::FieldReader; +#[doc = "Field `TDLY` writer - Trigger Delay Select"] +pub type TdlyW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TSYNC` reader - Trigger Synchronous Select"] +pub type TsyncR = crate::BitReader; +#[doc = "Field `TSYNC` writer - Trigger Synchronous Select"] +pub type TsyncW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Trigger Command Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tcmd { + #[doc = "0: Not a valid selection from the command buffer. Trigger event is ignored."] + NotValid = 0, + #[doc = "1: CMD1 is executed"] + ExecuteCmd1 = 1, + #[doc = "2: Corresponding CMD is executed"] + ExecuteCorrespondingCmd2 = 2, + #[doc = "3: Corresponding CMD is executed"] + ExecuteCorrespondingCmd3 = 3, + #[doc = "4: Corresponding CMD is executed"] + ExecuteCorrespondingCmd4 = 4, + #[doc = "5: Corresponding CMD is executed"] + ExecuteCorrespondingCmd5 = 5, + #[doc = "6: Corresponding CMD is executed"] + ExecuteCorrespondingCmd6 = 6, + #[doc = "7: CMD7 is executed"] + ExecuteCmd7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tcmd) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tcmd { + type Ux = u8; +} +impl crate::IsEnum for Tcmd {} +#[doc = "Field `TCMD` reader - Trigger Command Select"] +pub type TcmdR = crate::FieldReader; +impl TcmdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcmd { + match self.bits { + 0 => Tcmd::NotValid, + 1 => Tcmd::ExecuteCmd1, + 2 => Tcmd::ExecuteCorrespondingCmd2, + 3 => Tcmd::ExecuteCorrespondingCmd3, + 4 => Tcmd::ExecuteCorrespondingCmd4, + 5 => Tcmd::ExecuteCorrespondingCmd5, + 6 => Tcmd::ExecuteCorrespondingCmd6, + 7 => Tcmd::ExecuteCmd7, + _ => unreachable!(), + } + } + #[doc = "Not a valid selection from the command buffer. Trigger event is ignored."] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Tcmd::NotValid + } + #[doc = "CMD1 is executed"] + #[inline(always)] + pub fn is_execute_cmd1(&self) -> bool { + *self == Tcmd::ExecuteCmd1 + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn is_execute_corresponding_cmd_2(&self) -> bool { + *self == Tcmd::ExecuteCorrespondingCmd2 + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn is_execute_corresponding_cmd_3(&self) -> bool { + *self == Tcmd::ExecuteCorrespondingCmd3 + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn is_execute_corresponding_cmd_4(&self) -> bool { + *self == Tcmd::ExecuteCorrespondingCmd4 + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn is_execute_corresponding_cmd_5(&self) -> bool { + *self == Tcmd::ExecuteCorrespondingCmd5 + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn is_execute_corresponding_cmd_6(&self) -> bool { + *self == Tcmd::ExecuteCorrespondingCmd6 + } + #[doc = "CMD7 is executed"] + #[inline(always)] + pub fn is_execute_cmd7(&self) -> bool { + *self == Tcmd::ExecuteCmd7 + } +} +#[doc = "Field `TCMD` writer - Trigger Command Select"] +pub type TcmdW<'a, REG> = crate::FieldWriter<'a, REG, 3, Tcmd, crate::Safe>; +impl<'a, REG> TcmdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Not a valid selection from the command buffer. Trigger event is ignored."] + #[inline(always)] + pub fn not_valid(self) -> &'a mut crate::W { + self.variant(Tcmd::NotValid) + } + #[doc = "CMD1 is executed"] + #[inline(always)] + pub fn execute_cmd1(self) -> &'a mut crate::W { + self.variant(Tcmd::ExecuteCmd1) + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn execute_corresponding_cmd_2(self) -> &'a mut crate::W { + self.variant(Tcmd::ExecuteCorrespondingCmd2) + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn execute_corresponding_cmd_3(self) -> &'a mut crate::W { + self.variant(Tcmd::ExecuteCorrespondingCmd3) + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn execute_corresponding_cmd_4(self) -> &'a mut crate::W { + self.variant(Tcmd::ExecuteCorrespondingCmd4) + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn execute_corresponding_cmd_5(self) -> &'a mut crate::W { + self.variant(Tcmd::ExecuteCorrespondingCmd5) + } + #[doc = "Corresponding CMD is executed"] + #[inline(always)] + pub fn execute_corresponding_cmd_6(self) -> &'a mut crate::W { + self.variant(Tcmd::ExecuteCorrespondingCmd6) + } + #[doc = "CMD7 is executed"] + #[inline(always)] + pub fn execute_cmd7(self) -> &'a mut crate::W { + self.variant(Tcmd::ExecuteCmd7) + } +} +impl R { + #[doc = "Bit 0 - Trigger Enable"] + #[inline(always)] + pub fn hten(&self) -> HtenR { + HtenR::new((self.bits & 1) != 0) + } + #[doc = "Bits 8:9 - Trigger Priority Setting"] + #[inline(always)] + pub fn tpri(&self) -> TpriR { + TpriR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 15 - Trigger Resync"] + #[inline(always)] + pub fn rsync(&self) -> RsyncR { + RsyncR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:19 - Trigger Delay Select"] + #[inline(always)] + pub fn tdly(&self) -> TdlyR { + TdlyR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Trigger Synchronous Select"] + #[inline(always)] + pub fn tsync(&self) -> TsyncR { + TsyncR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Trigger Command Select"] + #[inline(always)] + pub fn tcmd(&self) -> TcmdR { + TcmdR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Trigger Enable"] + #[inline(always)] + pub fn hten(&mut self) -> HtenW { + HtenW::new(self, 0) + } + #[doc = "Bits 8:9 - Trigger Priority Setting"] + #[inline(always)] + pub fn tpri(&mut self) -> TpriW { + TpriW::new(self, 8) + } + #[doc = "Bit 15 - Trigger Resync"] + #[inline(always)] + pub fn rsync(&mut self) -> RsyncW { + RsyncW::new(self, 15) + } + #[doc = "Bits 16:19 - Trigger Delay Select"] + #[inline(always)] + pub fn tdly(&mut self) -> TdlyW { + TdlyW::new(self, 16) + } + #[doc = "Bit 23 - Trigger Synchronous Select"] + #[inline(always)] + pub fn tsync(&mut self) -> TsyncW { + TsyncW::new(self, 23) + } + #[doc = "Bits 24:26 - Trigger Command Select"] + #[inline(always)] + pub fn tcmd(&mut self) -> TcmdW { + TcmdW::new(self, 24) + } +} +#[doc = "Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TctrlSpec; +impl crate::RegisterSpec for TctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tctrl::R`](R) reader structure"] +impl crate::Readable for TctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`tctrl::W`](W) writer structure"] +impl crate::Writable for TctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCTRL[%s] to value 0"] +impl crate::Resettable for TctrlSpec {} diff --git a/mcxa276-pac/src/adc0/tstat.rs b/mcxa276-pac/src/adc0/tstat.rs new file mode 100644 index 000000000..0c729a97d --- /dev/null +++ b/mcxa276-pac/src/adc0/tstat.rs @@ -0,0 +1,396 @@ +#[doc = "Register `TSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `TSTAT` writer"] +pub type W = crate::W; +#[doc = "Trigger Exception Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TexcNum { + #[doc = "0: No triggers have been interrupted by a high priority exception. Or CFG\\[TRES\\] = 1."] + NoExceptions = 0, + #[doc = "1: Trigger 0 has been interrupted by a high priority exception."] + Bit0MeansTrigger0Interrupted = 1, + #[doc = "2: Trigger 1 has been interrupted by a high priority exception."] + Bit1MeansTrigger1Interrupted = 2, + #[doc = "3: Associated trigger sequence has interrupted by a high priority exception."] + SetBitsIndicateTriggerXInterrupted3 = 3, + #[doc = "4: Associated trigger sequence has interrupted by a high priority exception."] + SetBitsIndicateTriggerXInterrupted4 = 4, + #[doc = "5: Associated trigger sequence has interrupted by a high priority exception."] + SetBitsIndicateTriggerXInterrupted5 = 5, + #[doc = "6: Associated trigger sequence has interrupted by a high priority exception."] + SetBitsIndicateTriggerXInterrupted6 = 6, + #[doc = "7: Associated trigger sequence has interrupted by a high priority exception."] + SetBitsIndicateTriggerXInterrupted7 = 7, + #[doc = "8: Associated trigger sequence has interrupted by a high priority exception."] + SetBitsIndicateTriggerXInterrupted8 = 8, + #[doc = "9: Associated trigger sequence has interrupted by a high priority exception."] + SetBitsIndicateTriggerXInterrupted9 = 9, + #[doc = "15: Every trigger sequence has been interrupted by a high priority exception."] + AllBitsSetIndicateAllTriggersInterrupted = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TexcNum) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TexcNum { + type Ux = u8; +} +impl crate::IsEnum for TexcNum {} +#[doc = "Field `TEXC_NUM` reader - Trigger Exception Number"] +pub type TexcNumR = crate::FieldReader; +impl TexcNumR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(TexcNum::NoExceptions), + 1 => Some(TexcNum::Bit0MeansTrigger0Interrupted), + 2 => Some(TexcNum::Bit1MeansTrigger1Interrupted), + 3 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted3), + 4 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted4), + 5 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted5), + 6 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted6), + 7 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted7), + 8 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted8), + 9 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted9), + 15 => Some(TexcNum::AllBitsSetIndicateAllTriggersInterrupted), + _ => None, + } + } + #[doc = "No triggers have been interrupted by a high priority exception. Or CFG\\[TRES\\] = 1."] + #[inline(always)] + pub fn is_no_exceptions(&self) -> bool { + *self == TexcNum::NoExceptions + } + #[doc = "Trigger 0 has been interrupted by a high priority exception."] + #[inline(always)] + pub fn is_bit0_means_trigger_0_interrupted(&self) -> bool { + *self == TexcNum::Bit0MeansTrigger0Interrupted + } + #[doc = "Trigger 1 has been interrupted by a high priority exception."] + #[inline(always)] + pub fn is_bit1_means_trigger_1_interrupted(&self) -> bool { + *self == TexcNum::Bit1MeansTrigger1Interrupted + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_interrupted_3(&self) -> bool { + *self == TexcNum::SetBitsIndicateTriggerXInterrupted3 + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_interrupted_4(&self) -> bool { + *self == TexcNum::SetBitsIndicateTriggerXInterrupted4 + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_interrupted_5(&self) -> bool { + *self == TexcNum::SetBitsIndicateTriggerXInterrupted5 + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_interrupted_6(&self) -> bool { + *self == TexcNum::SetBitsIndicateTriggerXInterrupted6 + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_interrupted_7(&self) -> bool { + *self == TexcNum::SetBitsIndicateTriggerXInterrupted7 + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_interrupted_8(&self) -> bool { + *self == TexcNum::SetBitsIndicateTriggerXInterrupted8 + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_interrupted_9(&self) -> bool { + *self == TexcNum::SetBitsIndicateTriggerXInterrupted9 + } + #[doc = "Every trigger sequence has been interrupted by a high priority exception."] + #[inline(always)] + pub fn is_all_bits_set_indicate_all_triggers_interrupted(&self) -> bool { + *self == TexcNum::AllBitsSetIndicateAllTriggersInterrupted + } +} +#[doc = "Field `TEXC_NUM` writer - Trigger Exception Number"] +pub type TexcNumW<'a, REG> = crate::FieldWriter<'a, REG, 4, TexcNum>; +impl<'a, REG> TexcNumW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No triggers have been interrupted by a high priority exception. Or CFG\\[TRES\\] = 1."] + #[inline(always)] + pub fn no_exceptions(self) -> &'a mut crate::W { + self.variant(TexcNum::NoExceptions) + } + #[doc = "Trigger 0 has been interrupted by a high priority exception."] + #[inline(always)] + pub fn bit0_means_trigger_0_interrupted(self) -> &'a mut crate::W { + self.variant(TexcNum::Bit0MeansTrigger0Interrupted) + } + #[doc = "Trigger 1 has been interrupted by a high priority exception."] + #[inline(always)] + pub fn bit1_means_trigger_1_interrupted(self) -> &'a mut crate::W { + self.variant(TexcNum::Bit1MeansTrigger1Interrupted) + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_interrupted_3(self) -> &'a mut crate::W { + self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted3) + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_interrupted_4(self) -> &'a mut crate::W { + self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted4) + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_interrupted_5(self) -> &'a mut crate::W { + self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted5) + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_interrupted_6(self) -> &'a mut crate::W { + self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted6) + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_interrupted_7(self) -> &'a mut crate::W { + self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted7) + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_interrupted_8(self) -> &'a mut crate::W { + self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted8) + } + #[doc = "Associated trigger sequence has interrupted by a high priority exception."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_interrupted_9(self) -> &'a mut crate::W { + self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted9) + } + #[doc = "Every trigger sequence has been interrupted by a high priority exception."] + #[inline(always)] + pub fn all_bits_set_indicate_all_triggers_interrupted(self) -> &'a mut crate::W { + self.variant(TexcNum::AllBitsSetIndicateAllTriggersInterrupted) + } +} +#[doc = "Trigger Completion Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TcompFlag { + #[doc = "0: No triggers have been completed. Trigger completion interrupts are disabled."] + NoTrigger = 0, + #[doc = "1: Trigger 0 has been completed and trigger 0 has enabled completion interrupts."] + Bit0MeansTrigger0Completed = 1, + #[doc = "2: Trigger 1 has been completed and trigger 1 has enabled completion interrupts."] + Bit1MeansTrigger1Completed = 2, + #[doc = "3: Associated trigger sequence has completed and has enabled completion interrupts."] + SetBitsIndicateTriggerXCompleted3 = 3, + #[doc = "4: Associated trigger sequence has completed and has enabled completion interrupts."] + SetBitsIndicateTriggerXCompleted4 = 4, + #[doc = "5: Associated trigger sequence has completed and has enabled completion interrupts."] + SetBitsIndicateTriggerXCompleted5 = 5, + #[doc = "6: Associated trigger sequence has completed and has enabled completion interrupts."] + SetBitsIndicateTriggerXCompleted6 = 6, + #[doc = "7: Associated trigger sequence has completed and has enabled completion interrupts."] + SetBitsIndicateTriggerXCompleted7 = 7, + #[doc = "8: Associated trigger sequence has completed and has enabled completion interrupts."] + SetBitsIndicateTriggerXCompleted8 = 8, + #[doc = "9: Associated trigger sequence has completed and has enabled completion interrupts."] + SetBitsIndicateTriggerXCompleted9 = 9, + #[doc = "15: Every trigger sequence has been completed and every trigger has enabled completion interrupts."] + AllBitsSetIndicateAllTriggersCompleted = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TcompFlag) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TcompFlag { + type Ux = u8; +} +impl crate::IsEnum for TcompFlag {} +#[doc = "Field `TCOMP_FLAG` reader - Trigger Completion Flag"] +pub type TcompFlagR = crate::FieldReader; +impl TcompFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(TcompFlag::NoTrigger), + 1 => Some(TcompFlag::Bit0MeansTrigger0Completed), + 2 => Some(TcompFlag::Bit1MeansTrigger1Completed), + 3 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted3), + 4 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted4), + 5 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted5), + 6 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted6), + 7 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted7), + 8 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted8), + 9 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted9), + 15 => Some(TcompFlag::AllBitsSetIndicateAllTriggersCompleted), + _ => None, + } + } + #[doc = "No triggers have been completed. Trigger completion interrupts are disabled."] + #[inline(always)] + pub fn is_no_trigger(&self) -> bool { + *self == TcompFlag::NoTrigger + } + #[doc = "Trigger 0 has been completed and trigger 0 has enabled completion interrupts."] + #[inline(always)] + pub fn is_bit0_means_trigger_0_completed(&self) -> bool { + *self == TcompFlag::Bit0MeansTrigger0Completed + } + #[doc = "Trigger 1 has been completed and trigger 1 has enabled completion interrupts."] + #[inline(always)] + pub fn is_bit1_means_trigger_1_completed(&self) -> bool { + *self == TcompFlag::Bit1MeansTrigger1Completed + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_completed_3(&self) -> bool { + *self == TcompFlag::SetBitsIndicateTriggerXCompleted3 + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_completed_4(&self) -> bool { + *self == TcompFlag::SetBitsIndicateTriggerXCompleted4 + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_completed_5(&self) -> bool { + *self == TcompFlag::SetBitsIndicateTriggerXCompleted5 + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_completed_6(&self) -> bool { + *self == TcompFlag::SetBitsIndicateTriggerXCompleted6 + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_completed_7(&self) -> bool { + *self == TcompFlag::SetBitsIndicateTriggerXCompleted7 + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_completed_8(&self) -> bool { + *self == TcompFlag::SetBitsIndicateTriggerXCompleted8 + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn is_set_bits_indicate_trigger_x_completed_9(&self) -> bool { + *self == TcompFlag::SetBitsIndicateTriggerXCompleted9 + } + #[doc = "Every trigger sequence has been completed and every trigger has enabled completion interrupts."] + #[inline(always)] + pub fn is_all_bits_set_indicate_all_triggers_completed(&self) -> bool { + *self == TcompFlag::AllBitsSetIndicateAllTriggersCompleted + } +} +#[doc = "Field `TCOMP_FLAG` writer - Trigger Completion Flag"] +pub type TcompFlagW<'a, REG> = crate::FieldWriter<'a, REG, 4, TcompFlag>; +impl<'a, REG> TcompFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No triggers have been completed. Trigger completion interrupts are disabled."] + #[inline(always)] + pub fn no_trigger(self) -> &'a mut crate::W { + self.variant(TcompFlag::NoTrigger) + } + #[doc = "Trigger 0 has been completed and trigger 0 has enabled completion interrupts."] + #[inline(always)] + pub fn bit0_means_trigger_0_completed(self) -> &'a mut crate::W { + self.variant(TcompFlag::Bit0MeansTrigger0Completed) + } + #[doc = "Trigger 1 has been completed and trigger 1 has enabled completion interrupts."] + #[inline(always)] + pub fn bit1_means_trigger_1_completed(self) -> &'a mut crate::W { + self.variant(TcompFlag::Bit1MeansTrigger1Completed) + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_completed_3(self) -> &'a mut crate::W { + self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted3) + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_completed_4(self) -> &'a mut crate::W { + self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted4) + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_completed_5(self) -> &'a mut crate::W { + self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted5) + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_completed_6(self) -> &'a mut crate::W { + self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted6) + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_completed_7(self) -> &'a mut crate::W { + self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted7) + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_completed_8(self) -> &'a mut crate::W { + self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted8) + } + #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] + #[inline(always)] + pub fn set_bits_indicate_trigger_x_completed_9(self) -> &'a mut crate::W { + self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted9) + } + #[doc = "Every trigger sequence has been completed and every trigger has enabled completion interrupts."] + #[inline(always)] + pub fn all_bits_set_indicate_all_triggers_completed(self) -> &'a mut crate::W { + self.variant(TcompFlag::AllBitsSetIndicateAllTriggersCompleted) + } +} +impl R { + #[doc = "Bits 0:3 - Trigger Exception Number"] + #[inline(always)] + pub fn texc_num(&self) -> TexcNumR { + TexcNumR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Trigger Completion Flag"] + #[inline(always)] + pub fn tcomp_flag(&self) -> TcompFlagR { + TcompFlagR::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Trigger Exception Number"] + #[inline(always)] + pub fn texc_num(&mut self) -> TexcNumW { + TexcNumW::new(self, 0) + } + #[doc = "Bits 16:19 - Trigger Completion Flag"] + #[inline(always)] + pub fn tcomp_flag(&mut self) -> TcompFlagW { + TcompFlagW::new(self, 16) + } +} +#[doc = "Trigger Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstatSpec; +impl crate::RegisterSpec for TstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstat::R`](R) reader structure"] +impl crate::Readable for TstatSpec {} +#[doc = "`write(|w| ..)` method takes [`tstat::W`](W) writer structure"] +impl crate::Writable for TstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_000f; +} +#[doc = "`reset()` method sets TSTAT to value 0"] +impl crate::Resettable for TstatSpec {} diff --git a/mcxa276-pac/src/adc0/verid.rs b/mcxa276-pac/src/adc0/verid.rs new file mode 100644 index 000000000..4621a8e42 --- /dev/null +++ b/mcxa276-pac/src/adc0/verid.rs @@ -0,0 +1,442 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Resolution\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res { + #[doc = "0: Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] + Max13Bit = 0, + #[doc = "1: Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] + Max16Bit = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES` reader - Resolution"] +pub type ResR = crate::BitReader; +impl ResR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res { + match self.bits { + false => Res::Max13Bit, + true => Res::Max16Bit, + } + } + #[doc = "Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] + #[inline(always)] + pub fn is_max_13_bit(&self) -> bool { + *self == Res::Max13Bit + } + #[doc = "Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] + #[inline(always)] + pub fn is_max_16_bit(&self) -> bool { + *self == Res::Max16Bit + } +} +#[doc = "Differential Supported\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Diffen { + #[doc = "0: Differential operation not supported."] + DifferentialNotSupported = 0, + #[doc = "1: Differential operation supported."] + DifferentialSupported = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Diffen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIFFEN` reader - Differential Supported"] +pub type DiffenR = crate::BitReader; +impl DiffenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Diffen { + match self.bits { + false => Diffen::DifferentialNotSupported, + true => Diffen::DifferentialSupported, + } + } + #[doc = "Differential operation not supported."] + #[inline(always)] + pub fn is_differential_not_supported(&self) -> bool { + *self == Diffen::DifferentialNotSupported + } + #[doc = "Differential operation supported."] + #[inline(always)] + pub fn is_differential_supported(&self) -> bool { + *self == Diffen::DifferentialSupported + } +} +#[doc = "Multi Vref Implemented\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mvi { + #[doc = "0: Single voltage reference high (VREFH) input supported."] + MultipleRefNotSupported = 0, + #[doc = "1: Multiple voltage reference high (VREFH) inputs supported."] + MultipleRefSupported = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mvi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MVI` reader - Multi Vref Implemented"] +pub type MviR = crate::BitReader; +impl MviR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mvi { + match self.bits { + false => Mvi::MultipleRefNotSupported, + true => Mvi::MultipleRefSupported, + } + } + #[doc = "Single voltage reference high (VREFH) input supported."] + #[inline(always)] + pub fn is_multiple_ref_not_supported(&self) -> bool { + *self == Mvi::MultipleRefNotSupported + } + #[doc = "Multiple voltage reference high (VREFH) inputs supported."] + #[inline(always)] + pub fn is_multiple_ref_supported(&self) -> bool { + *self == Mvi::MultipleRefSupported + } +} +#[doc = "Channel Scale Width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Csw { + #[doc = "0: Channel scaling not supported."] + CscaleNotSupported = 0, + #[doc = "1: Channel scaling supported. 1-bit CSCALE control field."] + BitWidth1 = 1, + #[doc = "6: Channel scaling supported. 6-bit CSCALE control field."] + BitWidth6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Csw) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Csw { + type Ux = u8; +} +impl crate::IsEnum for Csw {} +#[doc = "Field `CSW` reader - Channel Scale Width"] +pub type CswR = crate::FieldReader; +impl CswR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Csw::CscaleNotSupported), + 1 => Some(Csw::BitWidth1), + 6 => Some(Csw::BitWidth6), + _ => None, + } + } + #[doc = "Channel scaling not supported."] + #[inline(always)] + pub fn is_cscale_not_supported(&self) -> bool { + *self == Csw::CscaleNotSupported + } + #[doc = "Channel scaling supported. 1-bit CSCALE control field."] + #[inline(always)] + pub fn is_bit_width_1(&self) -> bool { + *self == Csw::BitWidth1 + } + #[doc = "Channel scaling supported. 6-bit CSCALE control field."] + #[inline(always)] + pub fn is_bit_width_6(&self) -> bool { + *self == Csw::BitWidth6 + } +} +#[doc = "Voltage Reference 1 Range Control Bit Implemented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Vr1rngi { + #[doc = "0: Range control not required. CFG\\[VREF1RNG\\] is not implemented."] + Ref1FixedVoltageRange = 0, + #[doc = "1: Range control required. CFG\\[VREF1RNG\\] is implemented."] + Ref1SelectableVoltageRange = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Vr1rngi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VR1RNGI` reader - Voltage Reference 1 Range Control Bit Implemented"] +pub type Vr1rngiR = crate::BitReader; +impl Vr1rngiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Vr1rngi { + match self.bits { + false => Vr1rngi::Ref1FixedVoltageRange, + true => Vr1rngi::Ref1SelectableVoltageRange, + } + } + #[doc = "Range control not required. CFG\\[VREF1RNG\\] is not implemented."] + #[inline(always)] + pub fn is_ref1_fixed_voltage_range(&self) -> bool { + *self == Vr1rngi::Ref1FixedVoltageRange + } + #[doc = "Range control required. CFG\\[VREF1RNG\\] is implemented."] + #[inline(always)] + pub fn is_ref1_selectable_voltage_range(&self) -> bool { + *self == Vr1rngi::Ref1SelectableVoltageRange + } +} +#[doc = "Internal ADC Clock Implemented\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Iadcki { + #[doc = "0: Internal clock source not implemented."] + InternalClkNotAvailable = 0, + #[doc = "1: Internal clock source (and CFG\\[ADCKEN\\]) implemented."] + InternalClkAvailable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Iadcki) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IADCKI` reader - Internal ADC Clock Implemented"] +pub type IadckiR = crate::BitReader; +impl IadckiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Iadcki { + match self.bits { + false => Iadcki::InternalClkNotAvailable, + true => Iadcki::InternalClkAvailable, + } + } + #[doc = "Internal clock source not implemented."] + #[inline(always)] + pub fn is_internal_clk_not_available(&self) -> bool { + *self == Iadcki::InternalClkNotAvailable + } + #[doc = "Internal clock source (and CFG\\[ADCKEN\\]) implemented."] + #[inline(always)] + pub fn is_internal_clk_available(&self) -> bool { + *self == Iadcki::InternalClkAvailable + } +} +#[doc = "Calibration Function Implemented\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Calofsi { + #[doc = "0: Calibration Not Implemented."] + CalFunctionNotAvailable = 0, + #[doc = "1: Calibration Implemented."] + CalFunctionAvailable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Calofsi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CALOFSI` reader - Calibration Function Implemented"] +pub type CalofsiR = crate::BitReader; +impl CalofsiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Calofsi { + match self.bits { + false => Calofsi::CalFunctionNotAvailable, + true => Calofsi::CalFunctionAvailable, + } + } + #[doc = "Calibration Not Implemented."] + #[inline(always)] + pub fn is_cal_function_not_available(&self) -> bool { + *self == Calofsi::CalFunctionNotAvailable + } + #[doc = "Calibration Implemented."] + #[inline(always)] + pub fn is_cal_function_available(&self) -> bool { + *self == Calofsi::CalFunctionAvailable + } +} +#[doc = "Number of Single Ended Outputs Supported\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NumSec { + #[doc = "0: This design supports one single ended conversion at a time."] + SingleConvertor = 0, + #[doc = "1: This design supports two simultaneous single ended conversions."] + DualConvertor = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NumSec) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUM_SEC` reader - Number of Single Ended Outputs Supported"] +pub type NumSecR = crate::BitReader; +impl NumSecR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NumSec { + match self.bits { + false => NumSec::SingleConvertor, + true => NumSec::DualConvertor, + } + } + #[doc = "This design supports one single ended conversion at a time."] + #[inline(always)] + pub fn is_single_convertor(&self) -> bool { + *self == NumSec::SingleConvertor + } + #[doc = "This design supports two simultaneous single ended conversions."] + #[inline(always)] + pub fn is_dual_convertor(&self) -> bool { + *self == NumSec::DualConvertor + } +} +#[doc = "Number of FIFOs\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NumFifo { + #[doc = "0: N/A"] + NoFifoImplemented = 0, + #[doc = "1: This design supports one result FIFO."] + Cnt1 = 1, + #[doc = "2: This design supports two result FIFOs."] + Cnt2 = 2, + #[doc = "3: This design supports three result FIFOs."] + Cnt3 = 3, + #[doc = "4: This design supports four result FIFOs."] + Cnt4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NumFifo) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NumFifo { + type Ux = u8; +} +impl crate::IsEnum for NumFifo {} +#[doc = "Field `NUM_FIFO` reader - Number of FIFOs"] +pub type NumFifoR = crate::FieldReader; +impl NumFifoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NumFifo::NoFifoImplemented), + 1 => Some(NumFifo::Cnt1), + 2 => Some(NumFifo::Cnt2), + 3 => Some(NumFifo::Cnt3), + 4 => Some(NumFifo::Cnt4), + _ => None, + } + } + #[doc = "N/A"] + #[inline(always)] + pub fn is_no_fifo_implemented(&self) -> bool { + *self == NumFifo::NoFifoImplemented + } + #[doc = "This design supports one result FIFO."] + #[inline(always)] + pub fn is_cnt_1(&self) -> bool { + *self == NumFifo::Cnt1 + } + #[doc = "This design supports two result FIFOs."] + #[inline(always)] + pub fn is_cnt_2(&self) -> bool { + *self == NumFifo::Cnt2 + } + #[doc = "This design supports three result FIFOs."] + #[inline(always)] + pub fn is_cnt_3(&self) -> bool { + *self == NumFifo::Cnt3 + } + #[doc = "This design supports four result FIFOs."] + #[inline(always)] + pub fn is_cnt_4(&self) -> bool { + *self == NumFifo::Cnt4 + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Resolution"] + #[inline(always)] + pub fn res(&self) -> ResR { + ResR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Differential Supported"] + #[inline(always)] + pub fn diffen(&self) -> DiffenR { + DiffenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Multi Vref Implemented"] + #[inline(always)] + pub fn mvi(&self) -> MviR { + MviR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Channel Scale Width"] + #[inline(always)] + pub fn csw(&self) -> CswR { + CswR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 8 - Voltage Reference 1 Range Control Bit Implemented"] + #[inline(always)] + pub fn vr1rngi(&self) -> Vr1rngiR { + Vr1rngiR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Internal ADC Clock Implemented"] + #[inline(always)] + pub fn iadcki(&self) -> IadckiR { + IadckiR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Calibration Function Implemented"] + #[inline(always)] + pub fn calofsi(&self) -> CalofsiR { + CalofsiR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Number of Single Ended Outputs Supported"] + #[inline(always)] + pub fn num_sec(&self) -> NumSecR { + NumSecR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Number of FIFOs"] + #[inline(always)] + pub fn num_fifo(&self) -> NumFifoR { + NumFifoR::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0200_1409"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0200_1409; +} diff --git a/mcxa276-pac/src/aoi0.rs b/mcxa276-pac/src/aoi0.rs new file mode 100644 index 000000000..dabdec3c2 --- /dev/null +++ b/mcxa276-pac/src/aoi0.rs @@ -0,0 +1,94 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + bfcrt010: Bfcrt010, + bfcrt230: Bfcrt230, + bfcrt011: Bfcrt011, + bfcrt231: Bfcrt231, + bfcrt012: Bfcrt012, + bfcrt232: Bfcrt232, + bfcrt013: Bfcrt013, + bfcrt233: Bfcrt233, +} +impl RegisterBlock { + #[doc = "0x00 - Boolean Function Term 0 and 1 Configuration for EVENT0"] + #[inline(always)] + pub const fn bfcrt010(&self) -> &Bfcrt010 { + &self.bfcrt010 + } + #[doc = "0x02 - Boolean Function Term 2 and 3 Configuration for EVENT0"] + #[inline(always)] + pub const fn bfcrt230(&self) -> &Bfcrt230 { + &self.bfcrt230 + } + #[doc = "0x04 - Boolean Function Term 0 and 1 Configuration for EVENT1"] + #[inline(always)] + pub const fn bfcrt011(&self) -> &Bfcrt011 { + &self.bfcrt011 + } + #[doc = "0x06 - Boolean Function Term 2 and 3 Configuration for EVENT1"] + #[inline(always)] + pub const fn bfcrt231(&self) -> &Bfcrt231 { + &self.bfcrt231 + } + #[doc = "0x08 - Boolean Function Term 0 and 1 Configuration for EVENT2"] + #[inline(always)] + pub const fn bfcrt012(&self) -> &Bfcrt012 { + &self.bfcrt012 + } + #[doc = "0x0a - Boolean Function Term 2 and 3 Configuration for EVENT2"] + #[inline(always)] + pub const fn bfcrt232(&self) -> &Bfcrt232 { + &self.bfcrt232 + } + #[doc = "0x0c - Boolean Function Term 0 and 1 Configuration for EVENT3"] + #[inline(always)] + pub const fn bfcrt013(&self) -> &Bfcrt013 { + &self.bfcrt013 + } + #[doc = "0x0e - Boolean Function Term 2 and 3 Configuration for EVENT3"] + #[inline(always)] + pub const fn bfcrt233(&self) -> &Bfcrt233 { + &self.bfcrt233 + } +} +#[doc = "BFCRT010 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt010::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt010::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt010`] module"] +#[doc(alias = "BFCRT010")] +pub type Bfcrt010 = crate::Reg; +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT0"] +pub mod bfcrt010; +#[doc = "BFCRT230 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt230::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt230::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt230`] module"] +#[doc(alias = "BFCRT230")] +pub type Bfcrt230 = crate::Reg; +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT0"] +pub mod bfcrt230; +#[doc = "BFCRT011 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt011::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt011::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt011`] module"] +#[doc(alias = "BFCRT011")] +pub type Bfcrt011 = crate::Reg; +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT1"] +pub mod bfcrt011; +#[doc = "BFCRT231 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt231::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt231::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt231`] module"] +#[doc(alias = "BFCRT231")] +pub type Bfcrt231 = crate::Reg; +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT1"] +pub mod bfcrt231; +#[doc = "BFCRT012 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt012::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt012::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt012`] module"] +#[doc(alias = "BFCRT012")] +pub type Bfcrt012 = crate::Reg; +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT2"] +pub mod bfcrt012; +#[doc = "BFCRT232 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt232::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt232::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt232`] module"] +#[doc(alias = "BFCRT232")] +pub type Bfcrt232 = crate::Reg; +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT2"] +pub mod bfcrt232; +#[doc = "BFCRT013 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt013::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt013::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt013`] module"] +#[doc(alias = "BFCRT013")] +pub type Bfcrt013 = crate::Reg; +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT3"] +pub mod bfcrt013; +#[doc = "BFCRT233 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt233::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt233::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt233`] module"] +#[doc(alias = "BFCRT233")] +pub type Bfcrt233 = crate::Reg; +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT3"] +pub mod bfcrt233; diff --git a/mcxa276-pac/src/aoi0/bfcrt010.rs b/mcxa276-pac/src/aoi0/bfcrt010.rs new file mode 100644 index 000000000..d26fb9721 --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt010.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT010` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT010` writer"] +pub type W = crate::W; +#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Dc {} +#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] +pub type Pt1DcR = crate::FieldReader; +impl Pt1DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Dc { + match self.bits { + 0 => Pt1Dc::Force0, + 1 => Pt1Dc::Pass, + 2 => Pt1Dc::Complement, + 3 => Pt1Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Dc::Force1 + } +} +#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] +pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; +impl<'a, REG> Pt1DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force1) + } +} +#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Cc {} +#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] +pub type Pt1CcR = crate::FieldReader; +impl Pt1CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Cc { + match self.bits { + 0 => Pt1Cc::Force0, + 1 => Pt1Cc::Pass, + 2 => Pt1Cc::Complement, + 3 => Pt1Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Cc::Force1 + } +} +#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] +pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; +impl<'a, REG> Pt1CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force1) + } +} +#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Bc {} +#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] +pub type Pt1BcR = crate::FieldReader; +impl Pt1BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Bc { + match self.bits { + 0 => Pt1Bc::Force0, + 1 => Pt1Bc::Pass, + 2 => Pt1Bc::Complement, + 3 => Pt1Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Bc::Force1 + } +} +#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] +pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; +impl<'a, REG> Pt1BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force1) + } +} +#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt1Ac {} +#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] +pub type Pt1AcR = crate::FieldReader; +impl Pt1AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Ac { + match self.bits { + 0 => Pt1Ac::Force0, + 1 => Pt1Ac::Pass, + 2 => Pt1Ac::Complement, + 3 => Pt1Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Ac::Force1 + } +} +#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] +pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; +impl<'a, REG> Pt1AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force1) + } +} +#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Dc {} +#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] +pub type Pt0DcR = crate::FieldReader; +impl Pt0DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Dc { + match self.bits { + 0 => Pt0Dc::Force0, + 1 => Pt0Dc::Pass, + 2 => Pt0Dc::Complement, + 3 => Pt0Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Dc::Force1 + } +} +#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] +pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; +impl<'a, REG> Pt0DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force1) + } +} +#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Cc {} +#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] +pub type Pt0CcR = crate::FieldReader; +impl Pt0CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Cc { + match self.bits { + 0 => Pt0Cc::Force0, + 1 => Pt0Cc::Pass, + 2 => Pt0Cc::Complement, + 3 => Pt0Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Cc::Force1 + } +} +#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] +pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; +impl<'a, REG> Pt0CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force1) + } +} +#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Bc {} +#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] +pub type Pt0BcR = crate::FieldReader; +impl Pt0BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Bc { + match self.bits { + 0 => Pt0Bc::Force0, + 1 => Pt0Bc::Pass, + 2 => Pt0Bc::Complement, + 3 => Pt0Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Bc::Force1 + } +} +#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] +pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; +impl<'a, REG> Pt0BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force1) + } +} +#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt0Ac {} +#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] +pub type Pt0AcR = crate::FieldReader; +impl Pt0AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Ac { + match self.bits { + 0 => Pt0Ac::Force0, + 1 => Pt0Ac::Pass, + 2 => Pt0Ac::Complement, + 3 => Pt0Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Ac::Force1 + } +} +#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] +pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; +impl<'a, REG> Pt0AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&self) -> Pt1DcR { + Pt1DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&self) -> Pt1CcR { + Pt1CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&self) -> Pt1BcR { + Pt1BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&self) -> Pt1AcR { + Pt1AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&self) -> Pt0DcR { + Pt0DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&self) -> Pt0CcR { + Pt0CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&self) -> Pt0BcR { + Pt0BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&self) -> Pt0AcR { + Pt0AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&mut self) -> Pt1DcW { + Pt1DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&mut self) -> Pt1CcW { + Pt1CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&mut self) -> Pt1BcW { + Pt1BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&mut self) -> Pt1AcW { + Pt1AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&mut self) -> Pt0DcW { + Pt0DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&mut self) -> Pt0CcW { + Pt0CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&mut self) -> Pt0BcW { + Pt0BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&mut self) -> Pt0AcW { + Pt0AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt010::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt010::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt010Spec; +impl crate::RegisterSpec for Bfcrt010Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt010::R`](R) reader structure"] +impl crate::Readable for Bfcrt010Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt010::W`](W) writer structure"] +impl crate::Writable for Bfcrt010Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT010 to value 0"] +impl crate::Resettable for Bfcrt010Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt011.rs b/mcxa276-pac/src/aoi0/bfcrt011.rs new file mode 100644 index 000000000..ae3cdeca1 --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt011.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT011` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT011` writer"] +pub type W = crate::W; +#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Dc {} +#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] +pub type Pt1DcR = crate::FieldReader; +impl Pt1DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Dc { + match self.bits { + 0 => Pt1Dc::Force0, + 1 => Pt1Dc::Pass, + 2 => Pt1Dc::Complement, + 3 => Pt1Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Dc::Force1 + } +} +#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] +pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; +impl<'a, REG> Pt1DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force1) + } +} +#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Cc {} +#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] +pub type Pt1CcR = crate::FieldReader; +impl Pt1CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Cc { + match self.bits { + 0 => Pt1Cc::Force0, + 1 => Pt1Cc::Pass, + 2 => Pt1Cc::Complement, + 3 => Pt1Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Cc::Force1 + } +} +#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] +pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; +impl<'a, REG> Pt1CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force1) + } +} +#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Bc {} +#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] +pub type Pt1BcR = crate::FieldReader; +impl Pt1BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Bc { + match self.bits { + 0 => Pt1Bc::Force0, + 1 => Pt1Bc::Pass, + 2 => Pt1Bc::Complement, + 3 => Pt1Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Bc::Force1 + } +} +#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] +pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; +impl<'a, REG> Pt1BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force1) + } +} +#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt1Ac {} +#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] +pub type Pt1AcR = crate::FieldReader; +impl Pt1AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Ac { + match self.bits { + 0 => Pt1Ac::Force0, + 1 => Pt1Ac::Pass, + 2 => Pt1Ac::Complement, + 3 => Pt1Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Ac::Force1 + } +} +#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] +pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; +impl<'a, REG> Pt1AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force1) + } +} +#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Dc {} +#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] +pub type Pt0DcR = crate::FieldReader; +impl Pt0DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Dc { + match self.bits { + 0 => Pt0Dc::Force0, + 1 => Pt0Dc::Pass, + 2 => Pt0Dc::Complement, + 3 => Pt0Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Dc::Force1 + } +} +#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] +pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; +impl<'a, REG> Pt0DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force1) + } +} +#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Cc {} +#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] +pub type Pt0CcR = crate::FieldReader; +impl Pt0CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Cc { + match self.bits { + 0 => Pt0Cc::Force0, + 1 => Pt0Cc::Pass, + 2 => Pt0Cc::Complement, + 3 => Pt0Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Cc::Force1 + } +} +#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] +pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; +impl<'a, REG> Pt0CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force1) + } +} +#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Bc {} +#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] +pub type Pt0BcR = crate::FieldReader; +impl Pt0BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Bc { + match self.bits { + 0 => Pt0Bc::Force0, + 1 => Pt0Bc::Pass, + 2 => Pt0Bc::Complement, + 3 => Pt0Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Bc::Force1 + } +} +#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] +pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; +impl<'a, REG> Pt0BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force1) + } +} +#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt0Ac {} +#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] +pub type Pt0AcR = crate::FieldReader; +impl Pt0AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Ac { + match self.bits { + 0 => Pt0Ac::Force0, + 1 => Pt0Ac::Pass, + 2 => Pt0Ac::Complement, + 3 => Pt0Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Ac::Force1 + } +} +#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] +pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; +impl<'a, REG> Pt0AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&self) -> Pt1DcR { + Pt1DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&self) -> Pt1CcR { + Pt1CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&self) -> Pt1BcR { + Pt1BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&self) -> Pt1AcR { + Pt1AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&self) -> Pt0DcR { + Pt0DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&self) -> Pt0CcR { + Pt0CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&self) -> Pt0BcR { + Pt0BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&self) -> Pt0AcR { + Pt0AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&mut self) -> Pt1DcW { + Pt1DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&mut self) -> Pt1CcW { + Pt1CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&mut self) -> Pt1BcW { + Pt1BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&mut self) -> Pt1AcW { + Pt1AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&mut self) -> Pt0DcW { + Pt0DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&mut self) -> Pt0CcW { + Pt0CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&mut self) -> Pt0BcW { + Pt0BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&mut self) -> Pt0AcW { + Pt0AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt011::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt011::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt011Spec; +impl crate::RegisterSpec for Bfcrt011Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt011::R`](R) reader structure"] +impl crate::Readable for Bfcrt011Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt011::W`](W) writer structure"] +impl crate::Writable for Bfcrt011Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT011 to value 0"] +impl crate::Resettable for Bfcrt011Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt012.rs b/mcxa276-pac/src/aoi0/bfcrt012.rs new file mode 100644 index 000000000..50c1efd38 --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt012.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT012` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT012` writer"] +pub type W = crate::W; +#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Dc {} +#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] +pub type Pt1DcR = crate::FieldReader; +impl Pt1DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Dc { + match self.bits { + 0 => Pt1Dc::Force0, + 1 => Pt1Dc::Pass, + 2 => Pt1Dc::Complement, + 3 => Pt1Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Dc::Force1 + } +} +#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] +pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; +impl<'a, REG> Pt1DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force1) + } +} +#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Cc {} +#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] +pub type Pt1CcR = crate::FieldReader; +impl Pt1CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Cc { + match self.bits { + 0 => Pt1Cc::Force0, + 1 => Pt1Cc::Pass, + 2 => Pt1Cc::Complement, + 3 => Pt1Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Cc::Force1 + } +} +#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] +pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; +impl<'a, REG> Pt1CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force1) + } +} +#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Bc {} +#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] +pub type Pt1BcR = crate::FieldReader; +impl Pt1BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Bc { + match self.bits { + 0 => Pt1Bc::Force0, + 1 => Pt1Bc::Pass, + 2 => Pt1Bc::Complement, + 3 => Pt1Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Bc::Force1 + } +} +#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] +pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; +impl<'a, REG> Pt1BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force1) + } +} +#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt1Ac {} +#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] +pub type Pt1AcR = crate::FieldReader; +impl Pt1AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Ac { + match self.bits { + 0 => Pt1Ac::Force0, + 1 => Pt1Ac::Pass, + 2 => Pt1Ac::Complement, + 3 => Pt1Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Ac::Force1 + } +} +#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] +pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; +impl<'a, REG> Pt1AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force1) + } +} +#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Dc {} +#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] +pub type Pt0DcR = crate::FieldReader; +impl Pt0DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Dc { + match self.bits { + 0 => Pt0Dc::Force0, + 1 => Pt0Dc::Pass, + 2 => Pt0Dc::Complement, + 3 => Pt0Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Dc::Force1 + } +} +#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] +pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; +impl<'a, REG> Pt0DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force1) + } +} +#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Cc {} +#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] +pub type Pt0CcR = crate::FieldReader; +impl Pt0CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Cc { + match self.bits { + 0 => Pt0Cc::Force0, + 1 => Pt0Cc::Pass, + 2 => Pt0Cc::Complement, + 3 => Pt0Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Cc::Force1 + } +} +#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] +pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; +impl<'a, REG> Pt0CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force1) + } +} +#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Bc {} +#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] +pub type Pt0BcR = crate::FieldReader; +impl Pt0BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Bc { + match self.bits { + 0 => Pt0Bc::Force0, + 1 => Pt0Bc::Pass, + 2 => Pt0Bc::Complement, + 3 => Pt0Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Bc::Force1 + } +} +#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] +pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; +impl<'a, REG> Pt0BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force1) + } +} +#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt0Ac {} +#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] +pub type Pt0AcR = crate::FieldReader; +impl Pt0AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Ac { + match self.bits { + 0 => Pt0Ac::Force0, + 1 => Pt0Ac::Pass, + 2 => Pt0Ac::Complement, + 3 => Pt0Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Ac::Force1 + } +} +#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] +pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; +impl<'a, REG> Pt0AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&self) -> Pt1DcR { + Pt1DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&self) -> Pt1CcR { + Pt1CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&self) -> Pt1BcR { + Pt1BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&self) -> Pt1AcR { + Pt1AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&self) -> Pt0DcR { + Pt0DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&self) -> Pt0CcR { + Pt0CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&self) -> Pt0BcR { + Pt0BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&self) -> Pt0AcR { + Pt0AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&mut self) -> Pt1DcW { + Pt1DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&mut self) -> Pt1CcW { + Pt1CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&mut self) -> Pt1BcW { + Pt1BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&mut self) -> Pt1AcW { + Pt1AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&mut self) -> Pt0DcW { + Pt0DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&mut self) -> Pt0CcW { + Pt0CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&mut self) -> Pt0BcW { + Pt0BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&mut self) -> Pt0AcW { + Pt0AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt012::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt012::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt012Spec; +impl crate::RegisterSpec for Bfcrt012Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt012::R`](R) reader structure"] +impl crate::Readable for Bfcrt012Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt012::W`](W) writer structure"] +impl crate::Writable for Bfcrt012Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT012 to value 0"] +impl crate::Resettable for Bfcrt012Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt013.rs b/mcxa276-pac/src/aoi0/bfcrt013.rs new file mode 100644 index 000000000..09ae259bd --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt013.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT013` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT013` writer"] +pub type W = crate::W; +#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Dc {} +#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] +pub type Pt1DcR = crate::FieldReader; +impl Pt1DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Dc { + match self.bits { + 0 => Pt1Dc::Force0, + 1 => Pt1Dc::Pass, + 2 => Pt1Dc::Complement, + 3 => Pt1Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Dc::Force1 + } +} +#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] +pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; +impl<'a, REG> Pt1DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Dc::Force1) + } +} +#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Cc {} +#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] +pub type Pt1CcR = crate::FieldReader; +impl Pt1CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Cc { + match self.bits { + 0 => Pt1Cc::Force0, + 1 => Pt1Cc::Pass, + 2 => Pt1Cc::Complement, + 3 => Pt1Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Cc::Force1 + } +} +#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] +pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; +impl<'a, REG> Pt1CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Cc::Force1) + } +} +#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt1Bc {} +#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] +pub type Pt1BcR = crate::FieldReader; +impl Pt1BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Bc { + match self.bits { + 0 => Pt1Bc::Force0, + 1 => Pt1Bc::Pass, + 2 => Pt1Bc::Complement, + 3 => Pt1Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Bc::Force1 + } +} +#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] +pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; +impl<'a, REG> Pt1BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Bc::Force1) + } +} +#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt1Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt1Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt1Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt1Ac {} +#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] +pub type Pt1AcR = crate::FieldReader; +impl Pt1AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt1Ac { + match self.bits { + 0 => Pt1Ac::Force0, + 1 => Pt1Ac::Pass, + 2 => Pt1Ac::Complement, + 3 => Pt1Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt1Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt1Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt1Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt1Ac::Force1 + } +} +#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] +pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; +impl<'a, REG> Pt1AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt1Ac::Force1) + } +} +#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Dc {} +#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] +pub type Pt0DcR = crate::FieldReader; +impl Pt0DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Dc { + match self.bits { + 0 => Pt0Dc::Force0, + 1 => Pt0Dc::Pass, + 2 => Pt0Dc::Complement, + 3 => Pt0Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Dc::Force1 + } +} +#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] +pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; +impl<'a, REG> Pt0DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Dc::Force1) + } +} +#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Cc {} +#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] +pub type Pt0CcR = crate::FieldReader; +impl Pt0CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Cc { + match self.bits { + 0 => Pt0Cc::Force0, + 1 => Pt0Cc::Pass, + 2 => Pt0Cc::Complement, + 3 => Pt0Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Cc::Force1 + } +} +#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] +pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; +impl<'a, REG> Pt0CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Cc::Force1) + } +} +#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt0Bc {} +#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] +pub type Pt0BcR = crate::FieldReader; +impl Pt0BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Bc { + match self.bits { + 0 => Pt0Bc::Force0, + 1 => Pt0Bc::Pass, + 2 => Pt0Bc::Complement, + 3 => Pt0Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Bc::Force1 + } +} +#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] +pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; +impl<'a, REG> Pt0BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Bc::Force1) + } +} +#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt0Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt0Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt0Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt0Ac {} +#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] +pub type Pt0AcR = crate::FieldReader; +impl Pt0AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt0Ac { + match self.bits { + 0 => Pt0Ac::Force0, + 1 => Pt0Ac::Pass, + 2 => Pt0Ac::Complement, + 3 => Pt0Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt0Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt0Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt0Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt0Ac::Force1 + } +} +#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] +pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; +impl<'a, REG> Pt0AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt0Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&self) -> Pt1DcR { + Pt1DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&self) -> Pt1CcR { + Pt1CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&self) -> Pt1BcR { + Pt1BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&self) -> Pt1AcR { + Pt1AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&self) -> Pt0DcR { + Pt0DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&self) -> Pt0CcR { + Pt0CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&self) -> Pt0BcR { + Pt0BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&self) -> Pt0AcR { + Pt0AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] + #[inline(always)] + pub fn pt1_dc(&mut self) -> Pt1DcW { + Pt1DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] + #[inline(always)] + pub fn pt1_cc(&mut self) -> Pt1CcW { + Pt1CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] + #[inline(always)] + pub fn pt1_bc(&mut self) -> Pt1BcW { + Pt1BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] + #[inline(always)] + pub fn pt1_ac(&mut self) -> Pt1AcW { + Pt1AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] + #[inline(always)] + pub fn pt0_dc(&mut self) -> Pt0DcW { + Pt0DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] + #[inline(always)] + pub fn pt0_cc(&mut self) -> Pt0CcW { + Pt0CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] + #[inline(always)] + pub fn pt0_bc(&mut self) -> Pt0BcW { + Pt0BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] + #[inline(always)] + pub fn pt0_ac(&mut self) -> Pt0AcW { + Pt0AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt013::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt013::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt013Spec; +impl crate::RegisterSpec for Bfcrt013Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt013::R`](R) reader structure"] +impl crate::Readable for Bfcrt013Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt013::W`](W) writer structure"] +impl crate::Writable for Bfcrt013Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT013 to value 0"] +impl crate::Resettable for Bfcrt013Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt230.rs b/mcxa276-pac/src/aoi0/bfcrt230.rs new file mode 100644 index 000000000..ab9f3f29e --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt230.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT230` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT230` writer"] +pub type W = crate::W; +#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Dc {} +#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] +pub type Pt3DcR = crate::FieldReader; +impl Pt3DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Dc { + match self.bits { + 0 => Pt3Dc::Force0, + 1 => Pt3Dc::Pass, + 2 => Pt3Dc::Complement, + 3 => Pt3Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Dc::Force1 + } +} +#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] +pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; +impl<'a, REG> Pt3DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force1) + } +} +#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Cc {} +#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] +pub type Pt3CcR = crate::FieldReader; +impl Pt3CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Cc { + match self.bits { + 0 => Pt3Cc::Force0, + 1 => Pt3Cc::Pass, + 2 => Pt3Cc::Complement, + 3 => Pt3Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Cc::Force1 + } +} +#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] +pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; +impl<'a, REG> Pt3CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force1) + } +} +#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Bc {} +#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] +pub type Pt3BcR = crate::FieldReader; +impl Pt3BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Bc { + match self.bits { + 0 => Pt3Bc::Force0, + 1 => Pt3Bc::Pass, + 2 => Pt3Bc::Complement, + 3 => Pt3Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Bc::Force1 + } +} +#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] +pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; +impl<'a, REG> Pt3BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force1) + } +} +#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt3Ac {} +#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] +pub type Pt3AcR = crate::FieldReader; +impl Pt3AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Ac { + match self.bits { + 0 => Pt3Ac::Force0, + 1 => Pt3Ac::Pass, + 2 => Pt3Ac::Complement, + 3 => Pt3Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Ac::Complement + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Ac::Force1 + } +} +#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] +pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; +impl<'a, REG> Pt3AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Complement) + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force1) + } +} +#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Dc {} +#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] +pub type Pt2DcR = crate::FieldReader; +impl Pt2DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Dc { + match self.bits { + 0 => Pt2Dc::Force0, + 1 => Pt2Dc::Pass, + 2 => Pt2Dc::Complement, + 3 => Pt2Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Dc::Force1 + } +} +#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] +pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; +impl<'a, REG> Pt2DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force1) + } +} +#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Cc {} +#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] +pub type Pt2CcR = crate::FieldReader; +impl Pt2CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Cc { + match self.bits { + 0 => Pt2Cc::Force0, + 1 => Pt2Cc::Pass, + 2 => Pt2Cc::Complement, + 3 => Pt2Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Cc::Force1 + } +} +#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] +pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; +impl<'a, REG> Pt2CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force1) + } +} +#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Bc {} +#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] +pub type Pt2BcR = crate::FieldReader; +impl Pt2BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Bc { + match self.bits { + 0 => Pt2Bc::Force0, + 1 => Pt2Bc::Pass, + 2 => Pt2Bc::Complement, + 3 => Pt2Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Bc::Force1 + } +} +#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] +pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; +impl<'a, REG> Pt2BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force1) + } +} +#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt2Ac {} +#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] +pub type Pt2AcR = crate::FieldReader; +impl Pt2AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Ac { + match self.bits { + 0 => Pt2Ac::Force0, + 1 => Pt2Ac::Pass, + 2 => Pt2Ac::Complement, + 3 => Pt2Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Ac::Force1 + } +} +#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] +pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; +impl<'a, REG> Pt2AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&self) -> Pt3DcR { + Pt3DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&self) -> Pt3CcR { + Pt3CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&self) -> Pt3BcR { + Pt3BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&self) -> Pt3AcR { + Pt3AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&self) -> Pt2DcR { + Pt2DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&self) -> Pt2CcR { + Pt2CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&self) -> Pt2BcR { + Pt2BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&self) -> Pt2AcR { + Pt2AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&mut self) -> Pt3DcW { + Pt3DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&mut self) -> Pt3CcW { + Pt3CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&mut self) -> Pt3BcW { + Pt3BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&mut self) -> Pt3AcW { + Pt3AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&mut self) -> Pt2DcW { + Pt2DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&mut self) -> Pt2CcW { + Pt2CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&mut self) -> Pt2BcW { + Pt2BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&mut self) -> Pt2AcW { + Pt2AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt230::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt230::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt230Spec; +impl crate::RegisterSpec for Bfcrt230Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt230::R`](R) reader structure"] +impl crate::Readable for Bfcrt230Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt230::W`](W) writer structure"] +impl crate::Writable for Bfcrt230Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT230 to value 0"] +impl crate::Resettable for Bfcrt230Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt231.rs b/mcxa276-pac/src/aoi0/bfcrt231.rs new file mode 100644 index 000000000..01844e802 --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt231.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT231` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT231` writer"] +pub type W = crate::W; +#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Dc {} +#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] +pub type Pt3DcR = crate::FieldReader; +impl Pt3DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Dc { + match self.bits { + 0 => Pt3Dc::Force0, + 1 => Pt3Dc::Pass, + 2 => Pt3Dc::Complement, + 3 => Pt3Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Dc::Force1 + } +} +#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] +pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; +impl<'a, REG> Pt3DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force1) + } +} +#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Cc {} +#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] +pub type Pt3CcR = crate::FieldReader; +impl Pt3CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Cc { + match self.bits { + 0 => Pt3Cc::Force0, + 1 => Pt3Cc::Pass, + 2 => Pt3Cc::Complement, + 3 => Pt3Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Cc::Force1 + } +} +#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] +pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; +impl<'a, REG> Pt3CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force1) + } +} +#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Bc {} +#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] +pub type Pt3BcR = crate::FieldReader; +impl Pt3BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Bc { + match self.bits { + 0 => Pt3Bc::Force0, + 1 => Pt3Bc::Pass, + 2 => Pt3Bc::Complement, + 3 => Pt3Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Bc::Force1 + } +} +#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] +pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; +impl<'a, REG> Pt3BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force1) + } +} +#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt3Ac {} +#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] +pub type Pt3AcR = crate::FieldReader; +impl Pt3AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Ac { + match self.bits { + 0 => Pt3Ac::Force0, + 1 => Pt3Ac::Pass, + 2 => Pt3Ac::Complement, + 3 => Pt3Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Ac::Complement + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Ac::Force1 + } +} +#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] +pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; +impl<'a, REG> Pt3AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Complement) + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force1) + } +} +#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Dc {} +#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] +pub type Pt2DcR = crate::FieldReader; +impl Pt2DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Dc { + match self.bits { + 0 => Pt2Dc::Force0, + 1 => Pt2Dc::Pass, + 2 => Pt2Dc::Complement, + 3 => Pt2Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Dc::Force1 + } +} +#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] +pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; +impl<'a, REG> Pt2DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force1) + } +} +#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Cc {} +#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] +pub type Pt2CcR = crate::FieldReader; +impl Pt2CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Cc { + match self.bits { + 0 => Pt2Cc::Force0, + 1 => Pt2Cc::Pass, + 2 => Pt2Cc::Complement, + 3 => Pt2Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Cc::Force1 + } +} +#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] +pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; +impl<'a, REG> Pt2CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force1) + } +} +#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Bc {} +#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] +pub type Pt2BcR = crate::FieldReader; +impl Pt2BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Bc { + match self.bits { + 0 => Pt2Bc::Force0, + 1 => Pt2Bc::Pass, + 2 => Pt2Bc::Complement, + 3 => Pt2Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Bc::Force1 + } +} +#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] +pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; +impl<'a, REG> Pt2BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force1) + } +} +#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt2Ac {} +#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] +pub type Pt2AcR = crate::FieldReader; +impl Pt2AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Ac { + match self.bits { + 0 => Pt2Ac::Force0, + 1 => Pt2Ac::Pass, + 2 => Pt2Ac::Complement, + 3 => Pt2Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Ac::Force1 + } +} +#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] +pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; +impl<'a, REG> Pt2AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&self) -> Pt3DcR { + Pt3DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&self) -> Pt3CcR { + Pt3CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&self) -> Pt3BcR { + Pt3BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&self) -> Pt3AcR { + Pt3AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&self) -> Pt2DcR { + Pt2DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&self) -> Pt2CcR { + Pt2CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&self) -> Pt2BcR { + Pt2BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&self) -> Pt2AcR { + Pt2AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&mut self) -> Pt3DcW { + Pt3DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&mut self) -> Pt3CcW { + Pt3CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&mut self) -> Pt3BcW { + Pt3BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&mut self) -> Pt3AcW { + Pt3AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&mut self) -> Pt2DcW { + Pt2DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&mut self) -> Pt2CcW { + Pt2CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&mut self) -> Pt2BcW { + Pt2BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&mut self) -> Pt2AcW { + Pt2AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt231::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt231::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt231Spec; +impl crate::RegisterSpec for Bfcrt231Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt231::R`](R) reader structure"] +impl crate::Readable for Bfcrt231Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt231::W`](W) writer structure"] +impl crate::Writable for Bfcrt231Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT231 to value 0"] +impl crate::Resettable for Bfcrt231Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt232.rs b/mcxa276-pac/src/aoi0/bfcrt232.rs new file mode 100644 index 000000000..abbf0c7ba --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt232.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT232` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT232` writer"] +pub type W = crate::W; +#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Dc {} +#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] +pub type Pt3DcR = crate::FieldReader; +impl Pt3DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Dc { + match self.bits { + 0 => Pt3Dc::Force0, + 1 => Pt3Dc::Pass, + 2 => Pt3Dc::Complement, + 3 => Pt3Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Dc::Force1 + } +} +#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] +pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; +impl<'a, REG> Pt3DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force1) + } +} +#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Cc {} +#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] +pub type Pt3CcR = crate::FieldReader; +impl Pt3CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Cc { + match self.bits { + 0 => Pt3Cc::Force0, + 1 => Pt3Cc::Pass, + 2 => Pt3Cc::Complement, + 3 => Pt3Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Cc::Force1 + } +} +#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] +pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; +impl<'a, REG> Pt3CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force1) + } +} +#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Bc {} +#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] +pub type Pt3BcR = crate::FieldReader; +impl Pt3BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Bc { + match self.bits { + 0 => Pt3Bc::Force0, + 1 => Pt3Bc::Pass, + 2 => Pt3Bc::Complement, + 3 => Pt3Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Bc::Force1 + } +} +#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] +pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; +impl<'a, REG> Pt3BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force1) + } +} +#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt3Ac {} +#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] +pub type Pt3AcR = crate::FieldReader; +impl Pt3AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Ac { + match self.bits { + 0 => Pt3Ac::Force0, + 1 => Pt3Ac::Pass, + 2 => Pt3Ac::Complement, + 3 => Pt3Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Ac::Complement + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Ac::Force1 + } +} +#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] +pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; +impl<'a, REG> Pt3AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Complement) + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force1) + } +} +#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Dc {} +#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] +pub type Pt2DcR = crate::FieldReader; +impl Pt2DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Dc { + match self.bits { + 0 => Pt2Dc::Force0, + 1 => Pt2Dc::Pass, + 2 => Pt2Dc::Complement, + 3 => Pt2Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Dc::Force1 + } +} +#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] +pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; +impl<'a, REG> Pt2DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force1) + } +} +#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Cc {} +#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] +pub type Pt2CcR = crate::FieldReader; +impl Pt2CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Cc { + match self.bits { + 0 => Pt2Cc::Force0, + 1 => Pt2Cc::Pass, + 2 => Pt2Cc::Complement, + 3 => Pt2Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Cc::Force1 + } +} +#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] +pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; +impl<'a, REG> Pt2CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force1) + } +} +#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Bc {} +#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] +pub type Pt2BcR = crate::FieldReader; +impl Pt2BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Bc { + match self.bits { + 0 => Pt2Bc::Force0, + 1 => Pt2Bc::Pass, + 2 => Pt2Bc::Complement, + 3 => Pt2Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Bc::Force1 + } +} +#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] +pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; +impl<'a, REG> Pt2BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force1) + } +} +#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt2Ac {} +#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] +pub type Pt2AcR = crate::FieldReader; +impl Pt2AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Ac { + match self.bits { + 0 => Pt2Ac::Force0, + 1 => Pt2Ac::Pass, + 2 => Pt2Ac::Complement, + 3 => Pt2Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Ac::Force1 + } +} +#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] +pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; +impl<'a, REG> Pt2AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&self) -> Pt3DcR { + Pt3DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&self) -> Pt3CcR { + Pt3CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&self) -> Pt3BcR { + Pt3BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&self) -> Pt3AcR { + Pt3AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&self) -> Pt2DcR { + Pt2DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&self) -> Pt2CcR { + Pt2CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&self) -> Pt2BcR { + Pt2BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&self) -> Pt2AcR { + Pt2AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&mut self) -> Pt3DcW { + Pt3DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&mut self) -> Pt3CcW { + Pt3CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&mut self) -> Pt3BcW { + Pt3BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&mut self) -> Pt3AcW { + Pt3AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&mut self) -> Pt2DcW { + Pt2DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&mut self) -> Pt2CcW { + Pt2CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&mut self) -> Pt2BcW { + Pt2BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&mut self) -> Pt2AcW { + Pt2AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt232::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt232::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt232Spec; +impl crate::RegisterSpec for Bfcrt232Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt232::R`](R) reader structure"] +impl crate::Readable for Bfcrt232Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt232::W`](W) writer structure"] +impl crate::Writable for Bfcrt232Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT232 to value 0"] +impl crate::Resettable for Bfcrt232Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt233.rs b/mcxa276-pac/src/aoi0/bfcrt233.rs new file mode 100644 index 000000000..b478f4f86 --- /dev/null +++ b/mcxa276-pac/src/aoi0/bfcrt233.rs @@ -0,0 +1,789 @@ +#[doc = "Register `BFCRT233` reader"] +pub type R = crate::R; +#[doc = "Register `BFCRT233` writer"] +pub type W = crate::W; +#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Dc {} +#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] +pub type Pt3DcR = crate::FieldReader; +impl Pt3DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Dc { + match self.bits { + 0 => Pt3Dc::Force0, + 1 => Pt3Dc::Pass, + 2 => Pt3Dc::Complement, + 3 => Pt3Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Dc::Force1 + } +} +#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] +pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; +impl<'a, REG> Pt3DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Dc::Force1) + } +} +#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Cc {} +#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] +pub type Pt3CcR = crate::FieldReader; +impl Pt3CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Cc { + match self.bits { + 0 => Pt3Cc::Force0, + 1 => Pt3Cc::Pass, + 2 => Pt3Cc::Complement, + 3 => Pt3Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Cc::Force1 + } +} +#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] +pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; +impl<'a, REG> Pt3CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Cc::Force1) + } +} +#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt3Bc {} +#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] +pub type Pt3BcR = crate::FieldReader; +impl Pt3BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Bc { + match self.bits { + 0 => Pt3Bc::Force0, + 1 => Pt3Bc::Pass, + 2 => Pt3Bc::Complement, + 3 => Pt3Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Bc::Force1 + } +} +#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] +pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; +impl<'a, REG> Pt3BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Bc::Force1) + } +} +#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt3Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt3Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt3Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt3Ac {} +#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] +pub type Pt3AcR = crate::FieldReader; +impl Pt3AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt3Ac { + match self.bits { + 0 => Pt3Ac::Force0, + 1 => Pt3Ac::Pass, + 2 => Pt3Ac::Complement, + 3 => Pt3Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt3Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt3Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt3Ac::Complement + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt3Ac::Force1 + } +} +#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] +pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; +impl<'a, REG> Pt3AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Complement) + } + #[doc = "Force input to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt3Ac::Force1) + } +} +#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Dc { + #[doc = "0: Force input D to become 0"] + Force0 = 0, + #[doc = "1: Pass input D"] + Pass = 1, + #[doc = "2: Complement input D"] + Complement = 2, + #[doc = "3: Force input D to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Dc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Dc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Dc {} +#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] +pub type Pt2DcR = crate::FieldReader; +impl Pt2DcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Dc { + match self.bits { + 0 => Pt2Dc::Force0, + 1 => Pt2Dc::Pass, + 2 => Pt2Dc::Complement, + 3 => Pt2Dc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Dc::Force0 + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Dc::Pass + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Dc::Complement + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Dc::Force1 + } +} +#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] +pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; +impl<'a, REG> Pt2DcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input D to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force0) + } + #[doc = "Pass input D"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Pass) + } + #[doc = "Complement input D"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Complement) + } + #[doc = "Force input D to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Dc::Force1) + } +} +#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Cc { + #[doc = "0: Force input C to become 0"] + Force0 = 0, + #[doc = "1: Pass input C"] + Pass = 1, + #[doc = "2: Complement input C"] + Complement = 2, + #[doc = "3: Force input C to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Cc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Cc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Cc {} +#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] +pub type Pt2CcR = crate::FieldReader; +impl Pt2CcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Cc { + match self.bits { + 0 => Pt2Cc::Force0, + 1 => Pt2Cc::Pass, + 2 => Pt2Cc::Complement, + 3 => Pt2Cc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Cc::Force0 + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Cc::Pass + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Cc::Complement + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Cc::Force1 + } +} +#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] +pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; +impl<'a, REG> Pt2CcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input C to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force0) + } + #[doc = "Pass input C"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Pass) + } + #[doc = "Complement input C"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Complement) + } + #[doc = "Force input C to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Cc::Force1) + } +} +#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Bc { + #[doc = "0: Force input B to become 0"] + Force0 = 0, + #[doc = "1: Pass input B"] + Pass = 1, + #[doc = "2: Complement input B"] + Complement = 2, + #[doc = "3: Force input B to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Bc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Bc { + type Ux = u8; +} +impl crate::IsEnum for Pt2Bc {} +#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] +pub type Pt2BcR = crate::FieldReader; +impl Pt2BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Bc { + match self.bits { + 0 => Pt2Bc::Force0, + 1 => Pt2Bc::Pass, + 2 => Pt2Bc::Complement, + 3 => Pt2Bc::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Bc::Force0 + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Bc::Pass + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Bc::Complement + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Bc::Force1 + } +} +#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] +pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; +impl<'a, REG> Pt2BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input B to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force0) + } + #[doc = "Pass input B"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Pass) + } + #[doc = "Complement input B"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Complement) + } + #[doc = "Force input B to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Bc::Force1) + } +} +#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pt2Ac { + #[doc = "0: Force input A to become 0"] + Force0 = 0, + #[doc = "1: Pass input A"] + Pass = 1, + #[doc = "2: Complement input A"] + Complement = 2, + #[doc = "3: Force input A to become 1"] + Force1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pt2Ac) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pt2Ac { + type Ux = u8; +} +impl crate::IsEnum for Pt2Ac {} +#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] +pub type Pt2AcR = crate::FieldReader; +impl Pt2AcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt2Ac { + match self.bits { + 0 => Pt2Ac::Force0, + 1 => Pt2Ac::Pass, + 2 => Pt2Ac::Complement, + 3 => Pt2Ac::Force1, + _ => unreachable!(), + } + } + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn is_force_0(&self) -> bool { + *self == Pt2Ac::Force0 + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == Pt2Ac::Pass + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn is_complement(&self) -> bool { + *self == Pt2Ac::Complement + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn is_force_1(&self) -> bool { + *self == Pt2Ac::Force1 + } +} +#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] +pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; +impl<'a, REG> Pt2AcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Force input A to become 0"] + #[inline(always)] + pub fn force_0(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force0) + } + #[doc = "Pass input A"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Pass) + } + #[doc = "Complement input A"] + #[inline(always)] + pub fn complement(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Complement) + } + #[doc = "Force input A to become 1"] + #[inline(always)] + pub fn force_1(self) -> &'a mut crate::W { + self.variant(Pt2Ac::Force1) + } +} +impl R { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&self) -> Pt3DcR { + Pt3DcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&self) -> Pt3CcR { + Pt3CcR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&self) -> Pt3BcR { + Pt3BcR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&self) -> Pt3AcR { + Pt3AcR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&self) -> Pt2DcR { + Pt2DcR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&self) -> Pt2CcR { + Pt2CcR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&self) -> Pt2BcR { + Pt2BcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&self) -> Pt2AcR { + Pt2AcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] + #[inline(always)] + pub fn pt3_dc(&mut self) -> Pt3DcW { + Pt3DcW::new(self, 0) + } + #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] + #[inline(always)] + pub fn pt3_cc(&mut self) -> Pt3CcW { + Pt3CcW::new(self, 2) + } + #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] + #[inline(always)] + pub fn pt3_bc(&mut self) -> Pt3BcW { + Pt3BcW::new(self, 4) + } + #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] + #[inline(always)] + pub fn pt3_ac(&mut self) -> Pt3AcW { + Pt3AcW::new(self, 6) + } + #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] + #[inline(always)] + pub fn pt2_dc(&mut self) -> Pt2DcW { + Pt2DcW::new(self, 8) + } + #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] + #[inline(always)] + pub fn pt2_cc(&mut self) -> Pt2CcW { + Pt2CcW::new(self, 10) + } + #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] + #[inline(always)] + pub fn pt2_bc(&mut self) -> Pt2BcW { + Pt2BcW::new(self, 12) + } + #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] + #[inline(always)] + pub fn pt2_ac(&mut self) -> Pt2AcW { + Pt2AcW::new(self, 14) + } +} +#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt233::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt233::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bfcrt233Spec; +impl crate::RegisterSpec for Bfcrt233Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`bfcrt233::R`](R) reader structure"] +impl crate::Readable for Bfcrt233Spec {} +#[doc = "`write(|w| ..)` method takes [`bfcrt233::W`](W) writer structure"] +impl crate::Writable for Bfcrt233Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BFCRT233 to value 0"] +impl crate::Resettable for Bfcrt233Spec {} diff --git a/mcxa276-pac/src/can0.rs b/mcxa276-pac/src/can0.rs new file mode 100644 index 000000000..b328a994f --- /dev/null +++ b/mcxa276-pac/src/can0.rs @@ -0,0 +1,7163 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mcr: Mcr, + ctrl1: Ctrl1, + timer: Timer, + _reserved3: [u8; 0x04], + rxmgmask: Rxmgmask, + rx14mask: Rx14mask, + rx15mask: Rx15mask, + ecr: Ecr, + esr1: Esr1, + _reserved8: [u8; 0x04], + imask1: Imask1, + _reserved9: [u8; 0x04], + iflag1: Iflag1, + ctrl2: Ctrl2, + esr2: Esr2, + _reserved12: [u8; 0x08], + crcr: Crcr, + rxfgmask: Rxfgmask, + rxfir: Rxfir, + cbt: Cbt, + _reserved16: [u8; 0x2c], + _reserved_16_mb_: [u8; 0x04], + _reserved_17_mb_: [u8; 0x04], + _reserved_18_mb: [u8; 0x04], + _reserved_19_mb: [u8; 0x04], + _reserved_20_mb_: [u8; 0x04], + _reserved_21_mb_: [u8; 0x04], + _reserved_22_mb: [u8; 0x04], + _reserved_23_mb: [u8; 0x04], + _reserved_24_mb_: [u8; 0x04], + _reserved_25_mb_: [u8; 0x04], + _reserved_26_mb: [u8; 0x04], + _reserved_27_mb: [u8; 0x04], + _reserved_28_mb_: [u8; 0x04], + _reserved_29_mb_: [u8; 0x04], + _reserved_30_mb: [u8; 0x04], + _reserved_31_mb: [u8; 0x04], + _reserved_32_mb_: [u8; 0x04], + _reserved_33_mb_: [u8; 0x04], + _reserved_34_mb: [u8; 0x04], + _reserved_35_mb: [u8; 0x04], + _reserved_36_mb_: [u8; 0x04], + _reserved_37_mb_: [u8; 0x04], + _reserved_38_mb: [u8; 0x04], + _reserved_39_mb: [u8; 0x04], + _reserved_40_mb_: [u8; 0x04], + _reserved_41_mb_: [u8; 0x04], + _reserved_42_mb: [u8; 0x04], + _reserved_43_mb: [u8; 0x04], + _reserved_44_mb_: [u8; 0x04], + _reserved_45_mb_: [u8; 0x04], + _reserved_46_mb: [u8; 0x04], + _reserved_47_mb: [u8; 0x04], + _reserved_48_mb_: [u8; 0x04], + _reserved_49_mb_: [u8; 0x04], + _reserved_50_mb: [u8; 0x04], + _reserved_51_mb: [u8; 0x04], + _reserved_52_mb_: [u8; 0x04], + _reserved_53_mb_: [u8; 0x04], + _reserved_54_mb: [u8; 0x04], + _reserved_55_mb: [u8; 0x04], + _reserved_56_mb_: [u8; 0x04], + _reserved_57_mb_: [u8; 0x04], + _reserved_58_mb: [u8; 0x04], + _reserved_59_mb: [u8; 0x04], + _reserved_60_mb_: [u8; 0x04], + _reserved_61_mb_: [u8; 0x04], + _reserved_62_mb: [u8; 0x04], + _reserved_63_mb: [u8; 0x04], + _reserved_64_mb_: [u8; 0x04], + _reserved_65_mb_: [u8; 0x04], + _reserved_66_mb: [u8; 0x04], + _reserved_67_mb: [u8; 0x04], + _reserved_68_mb_: [u8; 0x04], + _reserved_69_mb_: [u8; 0x04], + _reserved_70_mb: [u8; 0x04], + _reserved_71_mb: [u8; 0x04], + _reserved_72_mb_: [u8; 0x04], + _reserved_73_mb_: [u8; 0x04], + _reserved_74_mb: [u8; 0x04], + _reserved_75_mb: [u8; 0x04], + _reserved_76_mb_: [u8; 0x04], + _reserved_77_mb_: [u8; 0x04], + _reserved_78_mb: [u8; 0x04], + _reserved_79_mb: [u8; 0x04], + _reserved_80_mb_: [u8; 0x04], + _reserved_81_mb_: [u8; 0x04], + _reserved_82_mb: [u8; 0x04], + _reserved_83_mb: [u8; 0x04], + _reserved_84_mb_: [u8; 0x04], + _reserved_85_mb_: [u8; 0x04], + _reserved_86_mb: [u8; 0x04], + _reserved_87_mb: [u8; 0x04], + _reserved_88_mb_: [u8; 0x04], + _reserved_89_mb_: [u8; 0x04], + _reserved_90_mb: [u8; 0x04], + _reserved_91_mb: [u8; 0x04], + _reserved_92_mb_: [u8; 0x04], + _reserved_93_mb_: [u8; 0x04], + _reserved_94_mb: [u8; 0x04], + _reserved_95_mb: [u8; 0x04], + _reserved_96_mb_: [u8; 0x04], + _reserved_97_mb_: [u8; 0x04], + _reserved_98_mb: [u8; 0x04], + _reserved_99_mb: [u8; 0x04], + _reserved_100_mb_: [u8; 0x04], + _reserved_101_mb_: [u8; 0x04], + _reserved_102_mb: [u8; 0x04], + _reserved_103_mb: [u8; 0x04], + _reserved_104_mb_: [u8; 0x04], + _reserved_105_mb_: [u8; 0x04], + _reserved_106_mb: [u8; 0x04], + _reserved_107_mb: [u8; 0x04], + _reserved_108_mb_: [u8; 0x04], + _reserved_109_mb_: [u8; 0x04], + _reserved_110_mb: [u8; 0x04], + _reserved_111_mb: [u8; 0x04], + _reserved_112_mb_: [u8; 0x04], + _reserved_113_mb_: [u8; 0x04], + _reserved_114_mb: [u8; 0x04], + _reserved_115_mb: [u8; 0x04], + _reserved_116_mb_: [u8; 0x04], + _reserved_117_mb_: [u8; 0x04], + _reserved_118_mb: [u8; 0x04], + _reserved_119_mb: [u8; 0x04], + _reserved_120_mb_: [u8; 0x04], + _reserved_121_mb_: [u8; 0x04], + _reserved_122_mb: [u8; 0x04], + _reserved_123_mb: [u8; 0x04], + _reserved_124_mb_: [u8; 0x04], + _reserved_125_mb_: [u8; 0x04], + _reserved_126_mb: [u8; 0x04], + _reserved_127_mb: [u8; 0x04], + _reserved_128_mb_: [u8; 0x04], + _reserved_129_mb_: [u8; 0x04], + _reserved_130_mb: [u8; 0x04], + _reserved_131_mb: [u8; 0x04], + _reserved_132_mb_: [u8; 0x04], + _reserved_133_mb_: [u8; 0x04], + _reserved_134_mb: [u8; 0x04], + _reserved_135_mb: [u8; 0x04], + _reserved_136_mb_: [u8; 0x04], + _reserved_137_mb_: [u8; 0x04], + _reserved_138_mb: [u8; 0x04], + _reserved_139_mb: [u8; 0x04], + _reserved_140_mb_: [u8; 0x04], + _reserved_141_mb_: [u8; 0x04], + _reserved_142_mb: [u8; 0x04], + _reserved_143_mb: [u8; 0x04], + _reserved144: [u8; 0x0600], + rximr: [Rximr; 32], + _reserved145: [u8; 0x0200], + ctrl1_pn: Ctrl1Pn, + ctrl2_pn: Ctrl2Pn, + wu_mtc: WuMtc, + flt_id1: FltId1, + flt_dlc: FltDlc, + pl1_lo: Pl1Lo, + pl1_hi: Pl1Hi, + flt_id2_idmask: FltId2Idmask, + pl2_plmask_lo: Pl2PlmaskLo, + pl2_plmask_hi: Pl2PlmaskHi, + _reserved155: [u8; 0x18], + wmb: [Wmb; 4], + _reserved156: [u8; 0x70], + eprs: Eprs, + encbt: Encbt, + edcbt: Edcbt, + etdc: Etdc, + fdctrl: Fdctrl, + fdcbt: Fdcbt, + fdcrc: Fdcrc, + erfcr: Erfcr, + erfier: Erfier, + erfsr: Erfsr, + _reserved166: [u8; 0x23e8], + erffel: [Erffel; 32], +} +impl RegisterBlock { + #[doc = "0x00 - Module Configuration"] + #[inline(always)] + pub const fn mcr(&self) -> &Mcr { + &self.mcr + } + #[doc = "0x04 - Control 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } + #[doc = "0x08 - Free-Running Timer"] + #[inline(always)] + pub const fn timer(&self) -> &Timer { + &self.timer + } + #[doc = "0x10 - RX Message Buffers Global Mask"] + #[inline(always)] + pub const fn rxmgmask(&self) -> &Rxmgmask { + &self.rxmgmask + } + #[doc = "0x14 - Receive 14 Mask"] + #[inline(always)] + pub const fn rx14mask(&self) -> &Rx14mask { + &self.rx14mask + } + #[doc = "0x18 - Receive 15 Mask"] + #[inline(always)] + pub const fn rx15mask(&self) -> &Rx15mask { + &self.rx15mask + } + #[doc = "0x1c - Error Counter"] + #[inline(always)] + pub const fn ecr(&self) -> &Ecr { + &self.ecr + } + #[doc = "0x20 - Error and Status 1"] + #[inline(always)] + pub const fn esr1(&self) -> &Esr1 { + &self.esr1 + } + #[doc = "0x28 - Interrupt Masks 1"] + #[inline(always)] + pub const fn imask1(&self) -> &Imask1 { + &self.imask1 + } + #[doc = "0x30 - Interrupt Flags 1"] + #[inline(always)] + pub const fn iflag1(&self) -> &Iflag1 { + &self.iflag1 + } + #[doc = "0x34 - Control 2"] + #[inline(always)] + pub const fn ctrl2(&self) -> &Ctrl2 { + &self.ctrl2 + } + #[doc = "0x38 - Error and Status 2"] + #[inline(always)] + pub const fn esr2(&self) -> &Esr2 { + &self.esr2 + } + #[doc = "0x44 - Cyclic Redundancy Check"] + #[inline(always)] + pub const fn crcr(&self) -> &Crcr { + &self.crcr + } + #[doc = "0x48 - Legacy RX FIFO Global Mask"] + #[inline(always)] + pub const fn rxfgmask(&self) -> &Rxfgmask { + &self.rxfgmask + } + #[doc = "0x4c - Legacy RX FIFO Information"] + #[inline(always)] + pub const fn rxfir(&self) -> &Rxfir { + &self.rxfir + } + #[doc = "0x50 - CAN Bit Timing"] + #[inline(always)] + pub const fn cbt(&self) -> &Cbt { + &self.cbt + } + #[doc = "0x80 - Message Buffer 0 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb0_8b_cs(&self) -> &Mb8bGroupMb0_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } + } + #[doc = "0x80 - Message Buffer 0 CS Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_cs(&self) -> &Mb64bGroupMb0_64bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } + } + #[doc = "0x80 - Message Buffer 0 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_cs(&self) -> &Mb32bGroupMb0_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } + } + #[doc = "0x80 - Message Buffer 0 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb0_16b_cs(&self) -> &Mb16bGroupMb0_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } + } + #[doc = "0x80 - Message Buffer 0 CS Register"] + #[inline(always)] + pub const fn mb_group_cs0(&self) -> &MbGroupCs0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } + } + #[doc = "0x84 - Message Buffer 0 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb0_8b_id(&self) -> &Mb8bGroupMb0_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } + } + #[doc = "0x84 - Message Buffer 0 ID Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_id(&self) -> &Mb64bGroupMb0_64bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } + } + #[doc = "0x84 - Message Buffer 0 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_id(&self) -> &Mb32bGroupMb0_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } + } + #[doc = "0x84 - Message Buffer 0 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb0_16b_id(&self) -> &Mb16bGroupMb0_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } + } + #[doc = "0x84 - Message Buffer 0 ID Register"] + #[inline(always)] + pub const fn mb_group_id0(&self) -> &MbGroupId0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } + } + #[doc = "0x88 - Message Buffer 0 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word00(&self) -> &MbGroupWord00 { + unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } + } + #[doc = "0x88 - Message Buffer 0 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb0_8b_word0(&self) -> &Mb8bGroupMb0_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } + } + #[doc = "0x88 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word0(&self) -> &Mb64bGroupMb0_64bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } + } + #[doc = "0x88 - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word0(&self) -> &Mb32bGroupMb0_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } + } + #[doc = "0x88 - Message Buffer 0 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb0_16b_word0(&self) -> &Mb16bGroupMb0_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } + } + #[doc = "0x8c - Message Buffer 0 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word10(&self) -> &MbGroupWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } + } + #[doc = "0x8c - Message Buffer 0 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb0_8b_word1(&self) -> &Mb8bGroupMb0_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } + } + #[doc = "0x8c - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word1(&self) -> &Mb64bGroupMb0_64bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } + } + #[doc = "0x8c - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word1(&self) -> &Mb32bGroupMb0_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } + } + #[doc = "0x8c - Message Buffer 0 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb0_16b_word1(&self) -> &Mb16bGroupMb0_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } + } + #[doc = "0x90 - Message Buffer 1 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb1_8b_cs(&self) -> &Mb8bGroupMb1_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } + } + #[doc = "0x90 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word2(&self) -> &Mb64bGroupMb0_64bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } + } + #[doc = "0x90 - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word2(&self) -> &Mb32bGroupMb0_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } + } + #[doc = "0x90 - Message Buffer 0 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb0_16b_word2(&self) -> &Mb16bGroupMb0_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } + } + #[doc = "0x90 - Message Buffer 1 CS Register"] + #[inline(always)] + pub const fn mb_group_cs1(&self) -> &MbGroupCs1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } + } + #[doc = "0x94 - Message Buffer 1 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb1_8b_id(&self) -> &Mb8bGroupMb1_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } + } + #[doc = "0x94 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word3(&self) -> &Mb64bGroupMb0_64bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } + } + #[doc = "0x94 - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word3(&self) -> &Mb32bGroupMb0_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } + } + #[doc = "0x94 - Message Buffer 0 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb0_16b_word3(&self) -> &Mb16bGroupMb0_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } + } + #[doc = "0x94 - Message Buffer 1 ID Register"] + #[inline(always)] + pub const fn mb_group_id1(&self) -> &MbGroupId1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } + } + #[doc = "0x98 - Message Buffer 1 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word01(&self) -> &MbGroupWord01 { + unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } + } + #[doc = "0x98 - Message Buffer 1 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb1_8b_word0(&self) -> &Mb8bGroupMb1_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } + } + #[doc = "0x98 - Message Buffer 1 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb1_16b_cs(&self) -> &Mb16bGroupMb1_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } + } + #[doc = "0x98 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word4(&self) -> &Mb64bGroupMb0_64bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } + } + #[doc = "0x98 - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word4(&self) -> &Mb32bGroupMb0_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } + } + #[doc = "0x9c - Message Buffer 1 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word11(&self) -> &MbGroupWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } + } + #[doc = "0x9c - Message Buffer 1 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb1_8b_word1(&self) -> &Mb8bGroupMb1_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } + } + #[doc = "0x9c - Message Buffer 1 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb1_16b_id(&self) -> &Mb16bGroupMb1_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } + } + #[doc = "0x9c - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word5(&self) -> &Mb64bGroupMb0_64bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } + } + #[doc = "0x9c - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word5(&self) -> &Mb32bGroupMb0_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } + } + #[doc = "0xa0 - Message Buffer 2 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb2_8b_cs(&self) -> &Mb8bGroupMb2_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } + } + #[doc = "0xa0 - Message Buffer 1 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb1_16b_word0(&self) -> &Mb16bGroupMb1_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } + } + #[doc = "0xa0 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word6(&self) -> &Mb64bGroupMb0_64bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } + } + #[doc = "0xa0 - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word6(&self) -> &Mb32bGroupMb0_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } + } + #[doc = "0xa0 - Message Buffer 2 CS Register"] + #[inline(always)] + pub const fn mb_group_cs2(&self) -> &MbGroupCs2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } + } + #[doc = "0xa4 - Message Buffer 2 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb2_8b_id(&self) -> &Mb8bGroupMb2_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } + } + #[doc = "0xa4 - Message Buffer 1 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb1_16b_word1(&self) -> &Mb16bGroupMb1_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } + } + #[doc = "0xa4 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word7(&self) -> &Mb64bGroupMb0_64bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } + } + #[doc = "0xa4 - Message Buffer 0 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb0_32b_word7(&self) -> &Mb32bGroupMb0_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } + } + #[doc = "0xa4 - Message Buffer 2 ID Register"] + #[inline(always)] + pub const fn mb_group_id2(&self) -> &MbGroupId2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } + } + #[doc = "0xa8 - Message Buffer 2 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word02(&self) -> &MbGroupWord02 { + unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } + } + #[doc = "0xa8 - Message Buffer 2 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb2_8b_word0(&self) -> &Mb8bGroupMb2_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } + } + #[doc = "0xa8 - Message Buffer 1 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_cs(&self) -> &Mb32bGroupMb1_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } + } + #[doc = "0xa8 - Message Buffer 1 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb1_16b_word2(&self) -> &Mb16bGroupMb1_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } + } + #[doc = "0xa8 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word8(&self) -> &Mb64bGroupMb0_64bWord8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } + } + #[doc = "0xac - Message Buffer 2 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word12(&self) -> &MbGroupWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } + } + #[doc = "0xac - Message Buffer 2 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb2_8b_word1(&self) -> &Mb8bGroupMb2_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } + } + #[doc = "0xac - Message Buffer 1 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_id(&self) -> &Mb32bGroupMb1_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } + } + #[doc = "0xac - Message Buffer 1 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb1_16b_word3(&self) -> &Mb16bGroupMb1_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } + } + #[doc = "0xac - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word9(&self) -> &Mb64bGroupMb0_64bWord9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } + } + #[doc = "0xb0 - Message Buffer 3 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb3_8b_cs(&self) -> &Mb8bGroupMb3_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } + } + #[doc = "0xb0 - Message Buffer 2 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb2_16b_cs(&self) -> &Mb16bGroupMb2_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } + } + #[doc = "0xb0 - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word0(&self) -> &Mb32bGroupMb1_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } + } + #[doc = "0xb0 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word10(&self) -> &Mb64bGroupMb0_64bWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } + } + #[doc = "0xb0 - Message Buffer 3 CS Register"] + #[inline(always)] + pub const fn mb_group_cs3(&self) -> &MbGroupCs3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } + } + #[doc = "0xb4 - Message Buffer 3 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb3_8b_id(&self) -> &Mb8bGroupMb3_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } + } + #[doc = "0xb4 - Message Buffer 2 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb2_16b_id(&self) -> &Mb16bGroupMb2_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } + } + #[doc = "0xb4 - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word1(&self) -> &Mb32bGroupMb1_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } + } + #[doc = "0xb4 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word11(&self) -> &Mb64bGroupMb0_64bWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } + } + #[doc = "0xb4 - Message Buffer 3 ID Register"] + #[inline(always)] + pub const fn mb_group_id3(&self) -> &MbGroupId3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } + } + #[doc = "0xb8 - Message Buffer 3 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word03(&self) -> &MbGroupWord03 { + unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } + } + #[doc = "0xb8 - Message Buffer 3 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb3_8b_word0(&self) -> &Mb8bGroupMb3_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } + } + #[doc = "0xb8 - Message Buffer 2 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb2_16b_word0(&self) -> &Mb16bGroupMb2_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } + } + #[doc = "0xb8 - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word2(&self) -> &Mb32bGroupMb1_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } + } + #[doc = "0xb8 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word12(&self) -> &Mb64bGroupMb0_64bWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } + } + #[doc = "0xbc - Message Buffer 3 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word13(&self) -> &MbGroupWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } + } + #[doc = "0xbc - Message Buffer 3 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb3_8b_word1(&self) -> &Mb8bGroupMb3_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } + } + #[doc = "0xbc - Message Buffer 2 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb2_16b_word1(&self) -> &Mb16bGroupMb2_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } + } + #[doc = "0xbc - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word3(&self) -> &Mb32bGroupMb1_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } + } + #[doc = "0xbc - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word13(&self) -> &Mb64bGroupMb0_64bWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } + } + #[doc = "0xc0 - Message Buffer 4 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb4_8b_cs(&self) -> &Mb8bGroupMb4_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } + } + #[doc = "0xc0 - Message Buffer 2 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb2_16b_word2(&self) -> &Mb16bGroupMb2_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } + } + #[doc = "0xc0 - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word4(&self) -> &Mb32bGroupMb1_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } + } + #[doc = "0xc0 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word14(&self) -> &Mb64bGroupMb0_64bWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } + } + #[doc = "0xc0 - Message Buffer 4 CS Register"] + #[inline(always)] + pub const fn mb_group_cs4(&self) -> &MbGroupCs4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } + } + #[doc = "0xc4 - Message Buffer 4 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb4_8b_id(&self) -> &Mb8bGroupMb4_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } + } + #[doc = "0xc4 - Message Buffer 2 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb2_16b_word3(&self) -> &Mb16bGroupMb2_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } + } + #[doc = "0xc4 - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word5(&self) -> &Mb32bGroupMb1_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } + } + #[doc = "0xc4 - Message Buffer 0 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb0_64b_word15(&self) -> &Mb64bGroupMb0_64bWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } + } + #[doc = "0xc4 - Message Buffer 4 ID Register"] + #[inline(always)] + pub const fn mb_group_id4(&self) -> &MbGroupId4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } + } + #[doc = "0xc8 - Message Buffer 4 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word04(&self) -> &MbGroupWord04 { + unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } + } + #[doc = "0xc8 - Message Buffer 4 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb4_8b_word0(&self) -> &Mb8bGroupMb4_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } + } + #[doc = "0xc8 - Message Buffer 3 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb3_16b_cs(&self) -> &Mb16bGroupMb3_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } + } + #[doc = "0xc8 - Message Buffer 1 CS Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_cs(&self) -> &Mb64bGroupMb1_64bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } + } + #[doc = "0xc8 - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word6(&self) -> &Mb32bGroupMb1_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } + } + #[doc = "0xcc - Message Buffer 4 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word14(&self) -> &MbGroupWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } + } + #[doc = "0xcc - Message Buffer 4 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb4_8b_word1(&self) -> &Mb8bGroupMb4_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } + } + #[doc = "0xcc - Message Buffer 3 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb3_16b_id(&self) -> &Mb16bGroupMb3_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } + } + #[doc = "0xcc - Message Buffer 1 ID Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_id(&self) -> &Mb64bGroupMb1_64bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } + } + #[doc = "0xcc - Message Buffer 1 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb1_32b_word7(&self) -> &Mb32bGroupMb1_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } + } + #[doc = "0xd0 - Message Buffer 5 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb5_8b_cs(&self) -> &Mb8bGroupMb5_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } + } + #[doc = "0xd0 - Message Buffer 3 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb3_16b_word0(&self) -> &Mb16bGroupMb3_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } + } + #[doc = "0xd0 - Message Buffer 2 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_cs(&self) -> &Mb32bGroupMb2_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } + } + #[doc = "0xd0 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word0(&self) -> &Mb64bGroupMb1_64bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } + } + #[doc = "0xd0 - Message Buffer 5 CS Register"] + #[inline(always)] + pub const fn mb_group_cs5(&self) -> &MbGroupCs5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } + } + #[doc = "0xd4 - Message Buffer 5 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb5_8b_id(&self) -> &Mb8bGroupMb5_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } + } + #[doc = "0xd4 - Message Buffer 3 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb3_16b_word1(&self) -> &Mb16bGroupMb3_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } + } + #[doc = "0xd4 - Message Buffer 2 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_id(&self) -> &Mb32bGroupMb2_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } + } + #[doc = "0xd4 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word1(&self) -> &Mb64bGroupMb1_64bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } + } + #[doc = "0xd4 - Message Buffer 5 ID Register"] + #[inline(always)] + pub const fn mb_group_id5(&self) -> &MbGroupId5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } + } + #[doc = "0xd8 - Message Buffer 5 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word05(&self) -> &MbGroupWord05 { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xd8 - Message Buffer 5 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb5_8b_word0(&self) -> &Mb8bGroupMb5_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xd8 - Message Buffer 3 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb3_16b_word2(&self) -> &Mb16bGroupMb3_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xd8 - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word0(&self) -> &Mb32bGroupMb2_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xd8 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word2(&self) -> &Mb64bGroupMb1_64bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xdc - Message Buffer 5 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word15(&self) -> &MbGroupWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } + } + #[doc = "0xdc - Message Buffer 5 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb5_8b_word1(&self) -> &Mb8bGroupMb5_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } + } + #[doc = "0xdc - Message Buffer 3 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb3_16b_word3(&self) -> &Mb16bGroupMb3_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } + } + #[doc = "0xdc - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word1(&self) -> &Mb32bGroupMb2_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } + } + #[doc = "0xdc - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word3(&self) -> &Mb64bGroupMb1_64bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } + } + #[doc = "0xe0 - Message Buffer 6 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb6_8b_cs(&self) -> &Mb8bGroupMb6_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } + } + #[doc = "0xe0 - Message Buffer 4 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb4_16b_cs(&self) -> &Mb16bGroupMb4_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } + } + #[doc = "0xe0 - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word2(&self) -> &Mb32bGroupMb2_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } + } + #[doc = "0xe0 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word4(&self) -> &Mb64bGroupMb1_64bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } + } + #[doc = "0xe0 - Message Buffer 6 CS Register"] + #[inline(always)] + pub const fn mb_group_cs6(&self) -> &MbGroupCs6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } + } + #[doc = "0xe4 - Message Buffer 6 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb6_8b_id(&self) -> &Mb8bGroupMb6_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } + } + #[doc = "0xe4 - Message Buffer 4 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb4_16b_id(&self) -> &Mb16bGroupMb4_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } + } + #[doc = "0xe4 - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word3(&self) -> &Mb32bGroupMb2_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } + } + #[doc = "0xe4 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word5(&self) -> &Mb64bGroupMb1_64bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } + } + #[doc = "0xe4 - Message Buffer 6 ID Register"] + #[inline(always)] + pub const fn mb_group_id6(&self) -> &MbGroupId6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } + } + #[doc = "0xe8 - Message Buffer 6 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word06(&self) -> &MbGroupWord06 { + unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } + } + #[doc = "0xe8 - Message Buffer 6 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb6_8b_word0(&self) -> &Mb8bGroupMb6_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } + } + #[doc = "0xe8 - Message Buffer 4 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb4_16b_word0(&self) -> &Mb16bGroupMb4_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } + } + #[doc = "0xe8 - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word4(&self) -> &Mb32bGroupMb2_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } + } + #[doc = "0xe8 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word6(&self) -> &Mb64bGroupMb1_64bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } + } + #[doc = "0xec - Message Buffer 6 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word16(&self) -> &MbGroupWord16 { + unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } + } + #[doc = "0xec - Message Buffer 6 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb6_8b_word1(&self) -> &Mb8bGroupMb6_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } + } + #[doc = "0xec - Message Buffer 4 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb4_16b_word1(&self) -> &Mb16bGroupMb4_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } + } + #[doc = "0xec - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word5(&self) -> &Mb32bGroupMb2_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } + } + #[doc = "0xec - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word7(&self) -> &Mb64bGroupMb1_64bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } + } + #[doc = "0xf0 - Message Buffer 7 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb7_8b_cs(&self) -> &Mb8bGroupMb7_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } + } + #[doc = "0xf0 - Message Buffer 4 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb4_16b_word2(&self) -> &Mb16bGroupMb4_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } + } + #[doc = "0xf0 - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word6(&self) -> &Mb32bGroupMb2_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } + } + #[doc = "0xf0 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word8(&self) -> &Mb64bGroupMb1_64bWord8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } + } + #[doc = "0xf0 - Message Buffer 7 CS Register"] + #[inline(always)] + pub const fn mb_group_cs7(&self) -> &MbGroupCs7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } + } + #[doc = "0xf4 - Message Buffer 7 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb7_8b_id(&self) -> &Mb8bGroupMb7_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } + } + #[doc = "0xf4 - Message Buffer 4 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb4_16b_word3(&self) -> &Mb16bGroupMb4_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } + } + #[doc = "0xf4 - Message Buffer 2 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb2_32b_word7(&self) -> &Mb32bGroupMb2_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } + } + #[doc = "0xf4 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word9(&self) -> &Mb64bGroupMb1_64bWord9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } + } + #[doc = "0xf4 - Message Buffer 7 ID Register"] + #[inline(always)] + pub const fn mb_group_id7(&self) -> &MbGroupId7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } + } + #[doc = "0xf8 - Message Buffer 7 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word07(&self) -> &MbGroupWord07 { + unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } + } + #[doc = "0xf8 - Message Buffer 7 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb7_8b_word0(&self) -> &Mb8bGroupMb7_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } + } + #[doc = "0xf8 - Message Buffer 5 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb5_16b_cs(&self) -> &Mb16bGroupMb5_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } + } + #[doc = "0xf8 - Message Buffer 3 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_cs(&self) -> &Mb32bGroupMb3_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } + } + #[doc = "0xf8 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word10(&self) -> &Mb64bGroupMb1_64bWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } + } + #[doc = "0xfc - Message Buffer 7 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word17(&self) -> &MbGroupWord17 { + unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } + } + #[doc = "0xfc - Message Buffer 7 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb7_8b_word1(&self) -> &Mb8bGroupMb7_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } + } + #[doc = "0xfc - Message Buffer 5 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb5_16b_id(&self) -> &Mb16bGroupMb5_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } + } + #[doc = "0xfc - Message Buffer 3 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_id(&self) -> &Mb32bGroupMb3_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } + } + #[doc = "0xfc - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word11(&self) -> &Mb64bGroupMb1_64bWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } + } + #[doc = "0x100 - Message Buffer 8 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb8_8b_cs(&self) -> &Mb8bGroupMb8_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } + } + #[doc = "0x100 - Message Buffer 5 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb5_16b_word0(&self) -> &Mb16bGroupMb5_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } + } + #[doc = "0x100 - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word0(&self) -> &Mb32bGroupMb3_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } + } + #[doc = "0x100 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word12(&self) -> &Mb64bGroupMb1_64bWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } + } + #[doc = "0x100 - Message Buffer 8 CS Register"] + #[inline(always)] + pub const fn mb_group_cs8(&self) -> &MbGroupCs8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } + } + #[doc = "0x104 - Message Buffer 8 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb8_8b_id(&self) -> &Mb8bGroupMb8_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } + } + #[doc = "0x104 - Message Buffer 5 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb5_16b_word1(&self) -> &Mb16bGroupMb5_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } + } + #[doc = "0x104 - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word1(&self) -> &Mb32bGroupMb3_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } + } + #[doc = "0x104 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word13(&self) -> &Mb64bGroupMb1_64bWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } + } + #[doc = "0x104 - Message Buffer 8 ID Register"] + #[inline(always)] + pub const fn mb_group_id8(&self) -> &MbGroupId8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } + } + #[doc = "0x108 - Message Buffer 8 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word08(&self) -> &MbGroupWord08 { + unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } + } + #[doc = "0x108 - Message Buffer 8 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb8_8b_word0(&self) -> &Mb8bGroupMb8_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } + } + #[doc = "0x108 - Message Buffer 5 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb5_16b_word2(&self) -> &Mb16bGroupMb5_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } + } + #[doc = "0x108 - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word2(&self) -> &Mb32bGroupMb3_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } + } + #[doc = "0x108 - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word14(&self) -> &Mb64bGroupMb1_64bWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } + } + #[doc = "0x10c - Message Buffer 8 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word18(&self) -> &MbGroupWord18 { + unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } + } + #[doc = "0x10c - Message Buffer 8 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb8_8b_word1(&self) -> &Mb8bGroupMb8_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } + } + #[doc = "0x10c - Message Buffer 5 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb5_16b_word3(&self) -> &Mb16bGroupMb5_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } + } + #[doc = "0x10c - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word3(&self) -> &Mb32bGroupMb3_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } + } + #[doc = "0x10c - Message Buffer 1 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb1_64b_word15(&self) -> &Mb64bGroupMb1_64bWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } + } + #[doc = "0x110 - Message Buffer 9 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb9_8b_cs(&self) -> &Mb8bGroupMb9_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } + } + #[doc = "0x110 - Message Buffer 6 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb6_16b_cs(&self) -> &Mb16bGroupMb6_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } + } + #[doc = "0x110 - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word4(&self) -> &Mb32bGroupMb3_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } + } + #[doc = "0x110 - Message Buffer 2 CS Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_cs(&self) -> &Mb64bGroupMb2_64bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } + } + #[doc = "0x110 - Message Buffer 9 CS Register"] + #[inline(always)] + pub const fn mb_group_cs9(&self) -> &MbGroupCs9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } + } + #[doc = "0x114 - Message Buffer 9 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb9_8b_id(&self) -> &Mb8bGroupMb9_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } + } + #[doc = "0x114 - Message Buffer 6 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb6_16b_id(&self) -> &Mb16bGroupMb6_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } + } + #[doc = "0x114 - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word5(&self) -> &Mb32bGroupMb3_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } + } + #[doc = "0x114 - Message Buffer 2 ID Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_id(&self) -> &Mb64bGroupMb2_64bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } + } + #[doc = "0x114 - Message Buffer 9 ID Register"] + #[inline(always)] + pub const fn mb_group_id9(&self) -> &MbGroupId9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } + } + #[doc = "0x118 - Message Buffer 9 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word09(&self) -> &MbGroupWord09 { + unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } + } + #[doc = "0x118 - Message Buffer 9 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb9_8b_word0(&self) -> &Mb8bGroupMb9_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } + } + #[doc = "0x118 - Message Buffer 6 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb6_16b_word0(&self) -> &Mb16bGroupMb6_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } + } + #[doc = "0x118 - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word6(&self) -> &Mb32bGroupMb3_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } + } + #[doc = "0x118 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word0(&self) -> &Mb64bGroupMb2_64bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } + } + #[doc = "0x11c - Message Buffer 9 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word19(&self) -> &MbGroupWord19 { + unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } + } + #[doc = "0x11c - Message Buffer 9 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb9_8b_word1(&self) -> &Mb8bGroupMb9_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } + } + #[doc = "0x11c - Message Buffer 6 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb6_16b_word1(&self) -> &Mb16bGroupMb6_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } + } + #[doc = "0x11c - Message Buffer 3 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb3_32b_word7(&self) -> &Mb32bGroupMb3_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } + } + #[doc = "0x11c - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word1(&self) -> &Mb64bGroupMb2_64bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } + } + #[doc = "0x120 - Message Buffer 6 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb6_16b_word2(&self) -> &Mb16bGroupMb6_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } + } + #[doc = "0x120 - Message Buffer 4 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_cs(&self) -> &Mb32bGroupMb4_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } + } + #[doc = "0x120 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word2(&self) -> &Mb64bGroupMb2_64bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } + } + #[doc = "0x120 - Message Buffer 10 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb10_8b_cs(&self) -> &Mb8bGroupMb10_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } + } + #[doc = "0x120 - Message Buffer 10 CS Register"] + #[inline(always)] + pub const fn mb_group_cs10(&self) -> &MbGroupCs10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } + } + #[doc = "0x124 - Message Buffer 6 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb6_16b_word3(&self) -> &Mb16bGroupMb6_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } + } + #[doc = "0x124 - Message Buffer 4 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_id(&self) -> &Mb32bGroupMb4_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } + } + #[doc = "0x124 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word3(&self) -> &Mb64bGroupMb2_64bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } + } + #[doc = "0x124 - Message Buffer 10 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb10_8b_id(&self) -> &Mb8bGroupMb10_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } + } + #[doc = "0x124 - Message Buffer 10 ID Register"] + #[inline(always)] + pub const fn mb_group_id10(&self) -> &MbGroupId10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } + } + #[doc = "0x128 - Message Buffer 10 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word010(&self) -> &MbGroupWord010 { + unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } + } + #[doc = "0x128 - Message Buffer 7 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb7_16b_cs(&self) -> &Mb16bGroupMb7_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } + } + #[doc = "0x128 - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word0(&self) -> &Mb32bGroupMb4_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } + } + #[doc = "0x128 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word4(&self) -> &Mb64bGroupMb2_64bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } + } + #[doc = "0x128 - Message Buffer 10 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb10_8b_word0(&self) -> &Mb8bGroupMb10_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } + } + #[doc = "0x12c - Message Buffer 10 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word110(&self) -> &MbGroupWord110 { + unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } + } + #[doc = "0x12c - Message Buffer 7 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb7_16b_id(&self) -> &Mb16bGroupMb7_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } + } + #[doc = "0x12c - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word1(&self) -> &Mb32bGroupMb4_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } + } + #[doc = "0x12c - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word5(&self) -> &Mb64bGroupMb2_64bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } + } + #[doc = "0x12c - Message Buffer 10 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb10_8b_word1(&self) -> &Mb8bGroupMb10_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } + } + #[doc = "0x130 - Message Buffer 7 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb7_16b_word0(&self) -> &Mb16bGroupMb7_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } + } + #[doc = "0x130 - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word2(&self) -> &Mb32bGroupMb4_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } + } + #[doc = "0x130 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word6(&self) -> &Mb64bGroupMb2_64bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } + } + #[doc = "0x130 - Message Buffer 11 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb11_8b_cs(&self) -> &Mb8bGroupMb11_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } + } + #[doc = "0x130 - Message Buffer 11 CS Register"] + #[inline(always)] + pub const fn mb_group_cs11(&self) -> &MbGroupCs11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } + } + #[doc = "0x134 - Message Buffer 7 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb7_16b_word1(&self) -> &Mb16bGroupMb7_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } + } + #[doc = "0x134 - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word3(&self) -> &Mb32bGroupMb4_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } + } + #[doc = "0x134 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word7(&self) -> &Mb64bGroupMb2_64bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } + } + #[doc = "0x134 - Message Buffer 11 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb11_8b_id(&self) -> &Mb8bGroupMb11_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } + } + #[doc = "0x134 - Message Buffer 11 ID Register"] + #[inline(always)] + pub const fn mb_group_id11(&self) -> &MbGroupId11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } + } + #[doc = "0x138 - Message Buffer 11 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word011(&self) -> &MbGroupWord011 { + unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } + } + #[doc = "0x138 - Message Buffer 7 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb7_16b_word2(&self) -> &Mb16bGroupMb7_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } + } + #[doc = "0x138 - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word4(&self) -> &Mb32bGroupMb4_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } + } + #[doc = "0x138 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word8(&self) -> &Mb64bGroupMb2_64bWord8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } + } + #[doc = "0x138 - Message Buffer 11 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb11_8b_word0(&self) -> &Mb8bGroupMb11_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } + } + #[doc = "0x13c - Message Buffer 11 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word111(&self) -> &MbGroupWord111 { + unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } + } + #[doc = "0x13c - Message Buffer 7 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb7_16b_word3(&self) -> &Mb16bGroupMb7_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } + } + #[doc = "0x13c - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word5(&self) -> &Mb32bGroupMb4_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } + } + #[doc = "0x13c - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word9(&self) -> &Mb64bGroupMb2_64bWord9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } + } + #[doc = "0x13c - Message Buffer 11 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb11_8b_word1(&self) -> &Mb8bGroupMb11_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } + } + #[doc = "0x140 - Message Buffer 8 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb8_16b_cs(&self) -> &Mb16bGroupMb8_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } + } + #[doc = "0x140 - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word6(&self) -> &Mb32bGroupMb4_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } + } + #[doc = "0x140 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word10(&self) -> &Mb64bGroupMb2_64bWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } + } + #[doc = "0x140 - Message Buffer 12 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb12_8b_cs(&self) -> &Mb8bGroupMb12_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } + } + #[doc = "0x140 - Message Buffer 12 CS Register"] + #[inline(always)] + pub const fn mb_group_cs12(&self) -> &MbGroupCs12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } + } + #[doc = "0x144 - Message Buffer 8 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb8_16b_id(&self) -> &Mb16bGroupMb8_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } + } + #[doc = "0x144 - Message Buffer 4 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb4_32b_word7(&self) -> &Mb32bGroupMb4_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } + } + #[doc = "0x144 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word11(&self) -> &Mb64bGroupMb2_64bWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } + } + #[doc = "0x144 - Message Buffer 12 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb12_8b_id(&self) -> &Mb8bGroupMb12_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } + } + #[doc = "0x144 - Message Buffer 12 ID Register"] + #[inline(always)] + pub const fn mb_group_id12(&self) -> &MbGroupId12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } + } + #[doc = "0x148 - Message Buffer 12 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word012(&self) -> &MbGroupWord012 { + unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } + } + #[doc = "0x148 - Message Buffer 8 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb8_16b_word0(&self) -> &Mb16bGroupMb8_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } + } + #[doc = "0x148 - Message Buffer 5 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_cs(&self) -> &Mb32bGroupMb5_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } + } + #[doc = "0x148 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word12(&self) -> &Mb64bGroupMb2_64bWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } + } + #[doc = "0x148 - Message Buffer 12 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb12_8b_word0(&self) -> &Mb8bGroupMb12_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } + } + #[doc = "0x14c - Message Buffer 12 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word112(&self) -> &MbGroupWord112 { + unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } + } + #[doc = "0x14c - Message Buffer 8 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb8_16b_word1(&self) -> &Mb16bGroupMb8_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } + } + #[doc = "0x14c - Message Buffer 5 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_id(&self) -> &Mb32bGroupMb5_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } + } + #[doc = "0x14c - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word13(&self) -> &Mb64bGroupMb2_64bWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } + } + #[doc = "0x14c - Message Buffer 12 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb12_8b_word1(&self) -> &Mb8bGroupMb12_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } + } + #[doc = "0x150 - Message Buffer 8 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb8_16b_word2(&self) -> &Mb16bGroupMb8_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } + } + #[doc = "0x150 - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word0(&self) -> &Mb32bGroupMb5_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } + } + #[doc = "0x150 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word14(&self) -> &Mb64bGroupMb2_64bWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } + } + #[doc = "0x150 - Message Buffer 13 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb13_8b_cs(&self) -> &Mb8bGroupMb13_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } + } + #[doc = "0x150 - Message Buffer 13 CS Register"] + #[inline(always)] + pub const fn mb_group_cs13(&self) -> &MbGroupCs13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } + } + #[doc = "0x154 - Message Buffer 8 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb8_16b_word3(&self) -> &Mb16bGroupMb8_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } + } + #[doc = "0x154 - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word1(&self) -> &Mb32bGroupMb5_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } + } + #[doc = "0x154 - Message Buffer 2 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb2_64b_word15(&self) -> &Mb64bGroupMb2_64bWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } + } + #[doc = "0x154 - Message Buffer 13 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb13_8b_id(&self) -> &Mb8bGroupMb13_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } + } + #[doc = "0x154 - Message Buffer 13 ID Register"] + #[inline(always)] + pub const fn mb_group_id13(&self) -> &MbGroupId13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } + } + #[doc = "0x158 - Message Buffer 13 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word013(&self) -> &MbGroupWord013 { + unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } + } + #[doc = "0x158 - Message Buffer 9 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb9_16b_cs(&self) -> &Mb16bGroupMb9_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } + } + #[doc = "0x158 - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word2(&self) -> &Mb32bGroupMb5_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } + } + #[doc = "0x158 - Message Buffer 3 CS Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_cs(&self) -> &Mb64bGroupMb3_64bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } + } + #[doc = "0x158 - Message Buffer 13 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb13_8b_word0(&self) -> &Mb8bGroupMb13_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } + } + #[doc = "0x15c - Message Buffer 13 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word113(&self) -> &MbGroupWord113 { + unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } + } + #[doc = "0x15c - Message Buffer 9 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb9_16b_id(&self) -> &Mb16bGroupMb9_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } + } + #[doc = "0x15c - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word3(&self) -> &Mb32bGroupMb5_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } + } + #[doc = "0x15c - Message Buffer 3 ID Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_id(&self) -> &Mb64bGroupMb3_64bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } + } + #[doc = "0x15c - Message Buffer 13 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb13_8b_word1(&self) -> &Mb8bGroupMb13_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } + } + #[doc = "0x160 - Message Buffer 9 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb9_16b_word0(&self) -> &Mb16bGroupMb9_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } + } + #[doc = "0x160 - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word4(&self) -> &Mb32bGroupMb5_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } + } + #[doc = "0x160 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word0(&self) -> &Mb64bGroupMb3_64bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } + } + #[doc = "0x160 - Message Buffer 14 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb14_8b_cs(&self) -> &Mb8bGroupMb14_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } + } + #[doc = "0x160 - Message Buffer 14 CS Register"] + #[inline(always)] + pub const fn mb_group_cs14(&self) -> &MbGroupCs14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } + } + #[doc = "0x164 - Message Buffer 9 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb9_16b_word1(&self) -> &Mb16bGroupMb9_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } + } + #[doc = "0x164 - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word5(&self) -> &Mb32bGroupMb5_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } + } + #[doc = "0x164 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word1(&self) -> &Mb64bGroupMb3_64bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } + } + #[doc = "0x164 - Message Buffer 14 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb14_8b_id(&self) -> &Mb8bGroupMb14_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } + } + #[doc = "0x164 - Message Buffer 14 ID Register"] + #[inline(always)] + pub const fn mb_group_id14(&self) -> &MbGroupId14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } + } + #[doc = "0x168 - Message Buffer 14 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word014(&self) -> &MbGroupWord014 { + unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } + } + #[doc = "0x168 - Message Buffer 9 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb9_16b_word2(&self) -> &Mb16bGroupMb9_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } + } + #[doc = "0x168 - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word6(&self) -> &Mb32bGroupMb5_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } + } + #[doc = "0x168 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word2(&self) -> &Mb64bGroupMb3_64bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } + } + #[doc = "0x168 - Message Buffer 14 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb14_8b_word0(&self) -> &Mb8bGroupMb14_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } + } + #[doc = "0x16c - Message Buffer 14 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word114(&self) -> &MbGroupWord114 { + unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } + } + #[doc = "0x16c - Message Buffer 9 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb9_16b_word3(&self) -> &Mb16bGroupMb9_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } + } + #[doc = "0x16c - Message Buffer 5 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb5_32b_word7(&self) -> &Mb32bGroupMb5_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } + } + #[doc = "0x16c - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word3(&self) -> &Mb64bGroupMb3_64bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } + } + #[doc = "0x16c - Message Buffer 14 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb14_8b_word1(&self) -> &Mb8bGroupMb14_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } + } + #[doc = "0x170 - Message Buffer 6 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_cs(&self) -> &Mb32bGroupMb6_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } + } + #[doc = "0x170 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word4(&self) -> &Mb64bGroupMb3_64bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } + } + #[doc = "0x170 - Message Buffer 15 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb15_8b_cs(&self) -> &Mb8bGroupMb15_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } + } + #[doc = "0x170 - Message Buffer 10 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb10_16b_cs(&self) -> &Mb16bGroupMb10_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } + } + #[doc = "0x170 - Message Buffer 15 CS Register"] + #[inline(always)] + pub const fn mb_group_cs15(&self) -> &MbGroupCs15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } + } + #[doc = "0x174 - Message Buffer 6 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_id(&self) -> &Mb32bGroupMb6_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } + } + #[doc = "0x174 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word5(&self) -> &Mb64bGroupMb3_64bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } + } + #[doc = "0x174 - Message Buffer 15 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb15_8b_id(&self) -> &Mb8bGroupMb15_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } + } + #[doc = "0x174 - Message Buffer 10 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb10_16b_id(&self) -> &Mb16bGroupMb10_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } + } + #[doc = "0x174 - Message Buffer 15 ID Register"] + #[inline(always)] + pub const fn mb_group_id15(&self) -> &MbGroupId15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } + } + #[doc = "0x178 - Message Buffer 15 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word015(&self) -> &MbGroupWord015 { + unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } + } + #[doc = "0x178 - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word0(&self) -> &Mb32bGroupMb6_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } + } + #[doc = "0x178 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word6(&self) -> &Mb64bGroupMb3_64bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } + } + #[doc = "0x178 - Message Buffer 15 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb15_8b_word0(&self) -> &Mb8bGroupMb15_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } + } + #[doc = "0x178 - Message Buffer 10 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb10_16b_word0(&self) -> &Mb16bGroupMb10_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } + } + #[doc = "0x17c - Message Buffer 15 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word115(&self) -> &MbGroupWord115 { + unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } + } + #[doc = "0x17c - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word1(&self) -> &Mb32bGroupMb6_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } + } + #[doc = "0x17c - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word7(&self) -> &Mb64bGroupMb3_64bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } + } + #[doc = "0x17c - Message Buffer 15 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb15_8b_word1(&self) -> &Mb8bGroupMb15_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } + } + #[doc = "0x17c - Message Buffer 10 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb10_16b_word1(&self) -> &Mb16bGroupMb10_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } + } + #[doc = "0x180 - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word2(&self) -> &Mb32bGroupMb6_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } + } + #[doc = "0x180 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word8(&self) -> &Mb64bGroupMb3_64bWord8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } + } + #[doc = "0x180 - Message Buffer 16 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb16_8b_cs(&self) -> &Mb8bGroupMb16_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } + } + #[doc = "0x180 - Message Buffer 10 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb10_16b_word2(&self) -> &Mb16bGroupMb10_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } + } + #[doc = "0x180 - Message Buffer 16 CS Register"] + #[inline(always)] + pub const fn mb_group_cs16(&self) -> &MbGroupCs16 { + unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } + } + #[doc = "0x184 - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word3(&self) -> &Mb32bGroupMb6_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } + } + #[doc = "0x184 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word9(&self) -> &Mb64bGroupMb3_64bWord9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } + } + #[doc = "0x184 - Message Buffer 16 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb16_8b_id(&self) -> &Mb8bGroupMb16_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } + } + #[doc = "0x184 - Message Buffer 10 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb10_16b_word3(&self) -> &Mb16bGroupMb10_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } + } + #[doc = "0x184 - Message Buffer 16 ID Register"] + #[inline(always)] + pub const fn mb_group_id16(&self) -> &MbGroupId16 { + unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } + } + #[doc = "0x188 - Message Buffer 16 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word016(&self) -> &MbGroupWord016 { + unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } + } + #[doc = "0x188 - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word4(&self) -> &Mb32bGroupMb6_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } + } + #[doc = "0x188 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word10(&self) -> &Mb64bGroupMb3_64bWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } + } + #[doc = "0x188 - Message Buffer 16 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb16_8b_word0(&self) -> &Mb8bGroupMb16_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } + } + #[doc = "0x188 - Message Buffer 11 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb11_16b_cs(&self) -> &Mb16bGroupMb11_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } + } + #[doc = "0x18c - Message Buffer 16 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word116(&self) -> &MbGroupWord116 { + unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } + } + #[doc = "0x18c - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word5(&self) -> &Mb32bGroupMb6_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } + } + #[doc = "0x18c - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word11(&self) -> &Mb64bGroupMb3_64bWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } + } + #[doc = "0x18c - Message Buffer 16 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb16_8b_word1(&self) -> &Mb8bGroupMb16_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } + } + #[doc = "0x18c - Message Buffer 11 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb11_16b_id(&self) -> &Mb16bGroupMb11_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } + } + #[doc = "0x190 - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word6(&self) -> &Mb32bGroupMb6_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } + } + #[doc = "0x190 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word12(&self) -> &Mb64bGroupMb3_64bWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } + } + #[doc = "0x190 - Message Buffer 17 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb17_8b_cs(&self) -> &Mb8bGroupMb17_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } + } + #[doc = "0x190 - Message Buffer 11 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb11_16b_word0(&self) -> &Mb16bGroupMb11_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } + } + #[doc = "0x190 - Message Buffer 17 CS Register"] + #[inline(always)] + pub const fn mb_group_cs17(&self) -> &MbGroupCs17 { + unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } + } + #[doc = "0x194 - Message Buffer 6 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb6_32b_word7(&self) -> &Mb32bGroupMb6_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } + } + #[doc = "0x194 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word13(&self) -> &Mb64bGroupMb3_64bWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } + } + #[doc = "0x194 - Message Buffer 17 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb17_8b_id(&self) -> &Mb8bGroupMb17_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } + } + #[doc = "0x194 - Message Buffer 11 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb11_16b_word1(&self) -> &Mb16bGroupMb11_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } + } + #[doc = "0x194 - Message Buffer 17 ID Register"] + #[inline(always)] + pub const fn mb_group_id17(&self) -> &MbGroupId17 { + unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } + } + #[doc = "0x198 - Message Buffer 17 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word017(&self) -> &MbGroupWord017 { + unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } + } + #[doc = "0x198 - Message Buffer 7 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_cs(&self) -> &Mb32bGroupMb7_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } + } + #[doc = "0x198 - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word14(&self) -> &Mb64bGroupMb3_64bWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } + } + #[doc = "0x198 - Message Buffer 17 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb17_8b_word0(&self) -> &Mb8bGroupMb17_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } + } + #[doc = "0x198 - Message Buffer 11 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb11_16b_word2(&self) -> &Mb16bGroupMb11_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } + } + #[doc = "0x19c - Message Buffer 17 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word117(&self) -> &MbGroupWord117 { + unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } + } + #[doc = "0x19c - Message Buffer 7 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_id(&self) -> &Mb32bGroupMb7_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } + } + #[doc = "0x19c - Message Buffer 3 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb3_64b_word15(&self) -> &Mb64bGroupMb3_64bWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } + } + #[doc = "0x19c - Message Buffer 17 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb17_8b_word1(&self) -> &Mb8bGroupMb17_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } + } + #[doc = "0x19c - Message Buffer 11 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb11_16b_word3(&self) -> &Mb16bGroupMb11_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } + } + #[doc = "0x1a0 - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word0(&self) -> &Mb32bGroupMb7_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } + } + #[doc = "0x1a0 - Message Buffer 4 CS Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_cs(&self) -> &Mb64bGroupMb4_64bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } + } + #[doc = "0x1a0 - Message Buffer 18 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb18_8b_cs(&self) -> &Mb8bGroupMb18_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } + } + #[doc = "0x1a0 - Message Buffer 12 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb12_16b_cs(&self) -> &Mb16bGroupMb12_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } + } + #[doc = "0x1a0 - Message Buffer 18 CS Register"] + #[inline(always)] + pub const fn mb_group_cs18(&self) -> &MbGroupCs18 { + unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } + } + #[doc = "0x1a4 - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word1(&self) -> &Mb32bGroupMb7_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } + } + #[doc = "0x1a4 - Message Buffer 4 ID Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_id(&self) -> &Mb64bGroupMb4_64bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } + } + #[doc = "0x1a4 - Message Buffer 18 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb18_8b_id(&self) -> &Mb8bGroupMb18_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } + } + #[doc = "0x1a4 - Message Buffer 12 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb12_16b_id(&self) -> &Mb16bGroupMb12_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } + } + #[doc = "0x1a4 - Message Buffer 18 ID Register"] + #[inline(always)] + pub const fn mb_group_id18(&self) -> &MbGroupId18 { + unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } + } + #[doc = "0x1a8 - Message Buffer 18 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word018(&self) -> &MbGroupWord018 { + unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } + } + #[doc = "0x1a8 - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word2(&self) -> &Mb32bGroupMb7_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } + } + #[doc = "0x1a8 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word0(&self) -> &Mb64bGroupMb4_64bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } + } + #[doc = "0x1a8 - Message Buffer 18 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb18_8b_word0(&self) -> &Mb8bGroupMb18_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } + } + #[doc = "0x1a8 - Message Buffer 12 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb12_16b_word0(&self) -> &Mb16bGroupMb12_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } + } + #[doc = "0x1ac - Message Buffer 18 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word118(&self) -> &MbGroupWord118 { + unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } + } + #[doc = "0x1ac - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word3(&self) -> &Mb32bGroupMb7_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } + } + #[doc = "0x1ac - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word1(&self) -> &Mb64bGroupMb4_64bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } + } + #[doc = "0x1ac - Message Buffer 18 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb18_8b_word1(&self) -> &Mb8bGroupMb18_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } + } + #[doc = "0x1ac - Message Buffer 12 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb12_16b_word1(&self) -> &Mb16bGroupMb12_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } + } + #[doc = "0x1b0 - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word4(&self) -> &Mb32bGroupMb7_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } + } + #[doc = "0x1b0 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word2(&self) -> &Mb64bGroupMb4_64bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } + } + #[doc = "0x1b0 - Message Buffer 19 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb19_8b_cs(&self) -> &Mb8bGroupMb19_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } + } + #[doc = "0x1b0 - Message Buffer 12 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb12_16b_word2(&self) -> &Mb16bGroupMb12_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } + } + #[doc = "0x1b0 - Message Buffer 19 CS Register"] + #[inline(always)] + pub const fn mb_group_cs19(&self) -> &MbGroupCs19 { + unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } + } + #[doc = "0x1b4 - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word5(&self) -> &Mb32bGroupMb7_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } + } + #[doc = "0x1b4 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word3(&self) -> &Mb64bGroupMb4_64bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } + } + #[doc = "0x1b4 - Message Buffer 19 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb19_8b_id(&self) -> &Mb8bGroupMb19_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } + } + #[doc = "0x1b4 - Message Buffer 12 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb12_16b_word3(&self) -> &Mb16bGroupMb12_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } + } + #[doc = "0x1b4 - Message Buffer 19 ID Register"] + #[inline(always)] + pub const fn mb_group_id19(&self) -> &MbGroupId19 { + unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } + } + #[doc = "0x1b8 - Message Buffer 19 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word019(&self) -> &MbGroupWord019 { + unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } + } + #[doc = "0x1b8 - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word6(&self) -> &Mb32bGroupMb7_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } + } + #[doc = "0x1b8 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word4(&self) -> &Mb64bGroupMb4_64bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } + } + #[doc = "0x1b8 - Message Buffer 19 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb19_8b_word0(&self) -> &Mb8bGroupMb19_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } + } + #[doc = "0x1b8 - Message Buffer 13 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb13_16b_cs(&self) -> &Mb16bGroupMb13_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } + } + #[doc = "0x1bc - Message Buffer 19 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word119(&self) -> &MbGroupWord119 { + unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } + } + #[doc = "0x1bc - Message Buffer 7 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb7_32b_word7(&self) -> &Mb32bGroupMb7_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } + } + #[doc = "0x1bc - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word5(&self) -> &Mb64bGroupMb4_64bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } + } + #[doc = "0x1bc - Message Buffer 19 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb19_8b_word1(&self) -> &Mb8bGroupMb19_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } + } + #[doc = "0x1bc - Message Buffer 13 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb13_16b_id(&self) -> &Mb16bGroupMb13_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } + } + #[doc = "0x1c0 - Message Buffer 8 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_cs(&self) -> &Mb32bGroupMb8_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } + } + #[doc = "0x1c0 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word6(&self) -> &Mb64bGroupMb4_64bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } + } + #[doc = "0x1c0 - Message Buffer 20 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb20_8b_cs(&self) -> &Mb8bGroupMb20_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } + } + #[doc = "0x1c0 - Message Buffer 13 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb13_16b_word0(&self) -> &Mb16bGroupMb13_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } + } + #[doc = "0x1c0 - Message Buffer 20 CS Register"] + #[inline(always)] + pub const fn mb_group_cs20(&self) -> &MbGroupCs20 { + unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } + } + #[doc = "0x1c4 - Message Buffer 8 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_id(&self) -> &Mb32bGroupMb8_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } + } + #[doc = "0x1c4 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word7(&self) -> &Mb64bGroupMb4_64bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } + } + #[doc = "0x1c4 - Message Buffer 20 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb20_8b_id(&self) -> &Mb8bGroupMb20_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } + } + #[doc = "0x1c4 - Message Buffer 13 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb13_16b_word1(&self) -> &Mb16bGroupMb13_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } + } + #[doc = "0x1c4 - Message Buffer 20 ID Register"] + #[inline(always)] + pub const fn mb_group_id20(&self) -> &MbGroupId20 { + unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } + } + #[doc = "0x1c8 - Message Buffer 20 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word020(&self) -> &MbGroupWord020 { + unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } + } + #[doc = "0x1c8 - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word0(&self) -> &Mb32bGroupMb8_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } + } + #[doc = "0x1c8 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word8(&self) -> &Mb64bGroupMb4_64bWord8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } + } + #[doc = "0x1c8 - Message Buffer 20 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb20_8b_word0(&self) -> &Mb8bGroupMb20_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } + } + #[doc = "0x1c8 - Message Buffer 13 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb13_16b_word2(&self) -> &Mb16bGroupMb13_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } + } + #[doc = "0x1cc - Message Buffer 20 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word120(&self) -> &MbGroupWord120 { + unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } + } + #[doc = "0x1cc - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word1(&self) -> &Mb32bGroupMb8_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } + } + #[doc = "0x1cc - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word9(&self) -> &Mb64bGroupMb4_64bWord9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } + } + #[doc = "0x1cc - Message Buffer 20 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb20_8b_word1(&self) -> &Mb8bGroupMb20_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } + } + #[doc = "0x1cc - Message Buffer 13 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb13_16b_word3(&self) -> &Mb16bGroupMb13_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } + } + #[doc = "0x1d0 - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word2(&self) -> &Mb32bGroupMb8_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } + } + #[doc = "0x1d0 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word10(&self) -> &Mb64bGroupMb4_64bWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } + } + #[doc = "0x1d0 - Message Buffer 21 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb21_8b_cs(&self) -> &Mb8bGroupMb21_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } + } + #[doc = "0x1d0 - Message Buffer 14 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb14_16b_cs(&self) -> &Mb16bGroupMb14_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } + } + #[doc = "0x1d0 - Message Buffer 21 CS Register"] + #[inline(always)] + pub const fn mb_group_cs21(&self) -> &MbGroupCs21 { + unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } + } + #[doc = "0x1d4 - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word3(&self) -> &Mb32bGroupMb8_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } + } + #[doc = "0x1d4 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word11(&self) -> &Mb64bGroupMb4_64bWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } + } + #[doc = "0x1d4 - Message Buffer 21 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb21_8b_id(&self) -> &Mb8bGroupMb21_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } + } + #[doc = "0x1d4 - Message Buffer 14 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb14_16b_id(&self) -> &Mb16bGroupMb14_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } + } + #[doc = "0x1d4 - Message Buffer 21 ID Register"] + #[inline(always)] + pub const fn mb_group_id21(&self) -> &MbGroupId21 { + unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } + } + #[doc = "0x1d8 - Message Buffer 21 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word021(&self) -> &MbGroupWord021 { + unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } + } + #[doc = "0x1d8 - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word4(&self) -> &Mb32bGroupMb8_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } + } + #[doc = "0x1d8 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word12(&self) -> &Mb64bGroupMb4_64bWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } + } + #[doc = "0x1d8 - Message Buffer 21 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb21_8b_word0(&self) -> &Mb8bGroupMb21_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } + } + #[doc = "0x1d8 - Message Buffer 14 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb14_16b_word0(&self) -> &Mb16bGroupMb14_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } + } + #[doc = "0x1dc - Message Buffer 21 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word121(&self) -> &MbGroupWord121 { + unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } + } + #[doc = "0x1dc - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word5(&self) -> &Mb32bGroupMb8_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } + } + #[doc = "0x1dc - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word13(&self) -> &Mb64bGroupMb4_64bWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } + } + #[doc = "0x1dc - Message Buffer 21 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb21_8b_word1(&self) -> &Mb8bGroupMb21_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } + } + #[doc = "0x1dc - Message Buffer 14 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb14_16b_word1(&self) -> &Mb16bGroupMb14_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } + } + #[doc = "0x1e0 - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word6(&self) -> &Mb32bGroupMb8_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } + } + #[doc = "0x1e0 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word14(&self) -> &Mb64bGroupMb4_64bWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } + } + #[doc = "0x1e0 - Message Buffer 22 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb22_8b_cs(&self) -> &Mb8bGroupMb22_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } + } + #[doc = "0x1e0 - Message Buffer 14 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb14_16b_word2(&self) -> &Mb16bGroupMb14_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } + } + #[doc = "0x1e0 - Message Buffer 22 CS Register"] + #[inline(always)] + pub const fn mb_group_cs22(&self) -> &MbGroupCs22 { + unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } + } + #[doc = "0x1e4 - Message Buffer 8 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb8_32b_word7(&self) -> &Mb32bGroupMb8_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } + } + #[doc = "0x1e4 - Message Buffer 4 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb4_64b_word15(&self) -> &Mb64bGroupMb4_64bWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } + } + #[doc = "0x1e4 - Message Buffer 22 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb22_8b_id(&self) -> &Mb8bGroupMb22_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } + } + #[doc = "0x1e4 - Message Buffer 14 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb14_16b_word3(&self) -> &Mb16bGroupMb14_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } + } + #[doc = "0x1e4 - Message Buffer 22 ID Register"] + #[inline(always)] + pub const fn mb_group_id22(&self) -> &MbGroupId22 { + unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } + } + #[doc = "0x1e8 - Message Buffer 22 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word022(&self) -> &MbGroupWord022 { + unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } + } + #[doc = "0x1e8 - Message Buffer 9 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_cs(&self) -> &Mb32bGroupMb9_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } + } + #[doc = "0x1e8 - Message Buffer 5 CS Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_cs(&self) -> &Mb64bGroupMb5_64bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } + } + #[doc = "0x1e8 - Message Buffer 22 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb22_8b_word0(&self) -> &Mb8bGroupMb22_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } + } + #[doc = "0x1e8 - Message Buffer 15 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb15_16b_cs(&self) -> &Mb16bGroupMb15_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } + } + #[doc = "0x1ec - Message Buffer 22 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word122(&self) -> &MbGroupWord122 { + unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } + } + #[doc = "0x1ec - Message Buffer 9 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_id(&self) -> &Mb32bGroupMb9_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } + } + #[doc = "0x1ec - Message Buffer 5 ID Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_id(&self) -> &Mb64bGroupMb5_64bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } + } + #[doc = "0x1ec - Message Buffer 22 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb22_8b_word1(&self) -> &Mb8bGroupMb22_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } + } + #[doc = "0x1ec - Message Buffer 15 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb15_16b_id(&self) -> &Mb16bGroupMb15_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } + } + #[doc = "0x1f0 - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word0(&self) -> &Mb32bGroupMb9_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } + } + #[doc = "0x1f0 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word0(&self) -> &Mb64bGroupMb5_64bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } + } + #[doc = "0x1f0 - Message Buffer 23 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb23_8b_cs(&self) -> &Mb8bGroupMb23_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } + } + #[doc = "0x1f0 - Message Buffer 15 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb15_16b_word0(&self) -> &Mb16bGroupMb15_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } + } + #[doc = "0x1f0 - Message Buffer 23 CS Register"] + #[inline(always)] + pub const fn mb_group_cs23(&self) -> &MbGroupCs23 { + unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } + } + #[doc = "0x1f4 - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word1(&self) -> &Mb32bGroupMb9_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } + } + #[doc = "0x1f4 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word1(&self) -> &Mb64bGroupMb5_64bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } + } + #[doc = "0x1f4 - Message Buffer 23 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb23_8b_id(&self) -> &Mb8bGroupMb23_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } + } + #[doc = "0x1f4 - Message Buffer 15 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb15_16b_word1(&self) -> &Mb16bGroupMb15_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } + } + #[doc = "0x1f4 - Message Buffer 23 ID Register"] + #[inline(always)] + pub const fn mb_group_id23(&self) -> &MbGroupId23 { + unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } + } + #[doc = "0x1f8 - Message Buffer 23 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word023(&self) -> &MbGroupWord023 { + unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } + } + #[doc = "0x1f8 - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word2(&self) -> &Mb32bGroupMb9_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } + } + #[doc = "0x1f8 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word2(&self) -> &Mb64bGroupMb5_64bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } + } + #[doc = "0x1f8 - Message Buffer 23 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb23_8b_word0(&self) -> &Mb8bGroupMb23_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } + } + #[doc = "0x1f8 - Message Buffer 15 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb15_16b_word2(&self) -> &Mb16bGroupMb15_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } + } + #[doc = "0x1fc - Message Buffer 23 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word123(&self) -> &MbGroupWord123 { + unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } + } + #[doc = "0x1fc - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word3(&self) -> &Mb32bGroupMb9_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } + } + #[doc = "0x1fc - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word3(&self) -> &Mb64bGroupMb5_64bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } + } + #[doc = "0x1fc - Message Buffer 23 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb23_8b_word1(&self) -> &Mb8bGroupMb23_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } + } + #[doc = "0x1fc - Message Buffer 15 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb15_16b_word3(&self) -> &Mb16bGroupMb15_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } + } + #[doc = "0x200 - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word4(&self) -> &Mb32bGroupMb9_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } + } + #[doc = "0x200 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word4(&self) -> &Mb64bGroupMb5_64bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } + } + #[doc = "0x200 - Message Buffer 24 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb24_8b_cs(&self) -> &Mb8bGroupMb24_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } + } + #[doc = "0x200 - Message Buffer 16 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb16_16b_cs(&self) -> &Mb16bGroupMb16_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } + } + #[doc = "0x200 - Message Buffer 24 CS Register"] + #[inline(always)] + pub const fn mb_group_cs24(&self) -> &MbGroupCs24 { + unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } + } + #[doc = "0x204 - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word5(&self) -> &Mb32bGroupMb9_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } + } + #[doc = "0x204 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word5(&self) -> &Mb64bGroupMb5_64bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } + } + #[doc = "0x204 - Message Buffer 24 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb24_8b_id(&self) -> &Mb8bGroupMb24_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } + } + #[doc = "0x204 - Message Buffer 16 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb16_16b_id(&self) -> &Mb16bGroupMb16_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } + } + #[doc = "0x204 - Message Buffer 24 ID Register"] + #[inline(always)] + pub const fn mb_group_id24(&self) -> &MbGroupId24 { + unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } + } + #[doc = "0x208 - Message Buffer 24 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word024(&self) -> &MbGroupWord024 { + unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } + } + #[doc = "0x208 - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word6(&self) -> &Mb32bGroupMb9_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } + } + #[doc = "0x208 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word6(&self) -> &Mb64bGroupMb5_64bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } + } + #[doc = "0x208 - Message Buffer 24 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb24_8b_word0(&self) -> &Mb8bGroupMb24_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } + } + #[doc = "0x208 - Message Buffer 16 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb16_16b_word0(&self) -> &Mb16bGroupMb16_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } + } + #[doc = "0x20c - Message Buffer 24 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word124(&self) -> &MbGroupWord124 { + unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } + } + #[doc = "0x20c - Message Buffer 9 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb9_32b_word7(&self) -> &Mb32bGroupMb9_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } + } + #[doc = "0x20c - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word7(&self) -> &Mb64bGroupMb5_64bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } + } + #[doc = "0x20c - Message Buffer 24 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb24_8b_word1(&self) -> &Mb8bGroupMb24_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } + } + #[doc = "0x20c - Message Buffer 16 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb16_16b_word1(&self) -> &Mb16bGroupMb16_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } + } + #[doc = "0x210 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word8(&self) -> &Mb64bGroupMb5_64bWord8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } + } + #[doc = "0x210 - Message Buffer 25 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb25_8b_cs(&self) -> &Mb8bGroupMb25_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } + } + #[doc = "0x210 - Message Buffer 16 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb16_16b_word2(&self) -> &Mb16bGroupMb16_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } + } + #[doc = "0x210 - Message Buffer 10 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_cs(&self) -> &Mb32bGroupMb10_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } + } + #[doc = "0x210 - Message Buffer 25 CS Register"] + #[inline(always)] + pub const fn mb_group_cs25(&self) -> &MbGroupCs25 { + unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } + } + #[doc = "0x214 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word9(&self) -> &Mb64bGroupMb5_64bWord9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } + } + #[doc = "0x214 - Message Buffer 25 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb25_8b_id(&self) -> &Mb8bGroupMb25_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } + } + #[doc = "0x214 - Message Buffer 16 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb16_16b_word3(&self) -> &Mb16bGroupMb16_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } + } + #[doc = "0x214 - Message Buffer 10 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_id(&self) -> &Mb32bGroupMb10_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } + } + #[doc = "0x214 - Message Buffer 25 ID Register"] + #[inline(always)] + pub const fn mb_group_id25(&self) -> &MbGroupId25 { + unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } + } + #[doc = "0x218 - Message Buffer 25 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word025(&self) -> &MbGroupWord025 { + unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } + } + #[doc = "0x218 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word10(&self) -> &Mb64bGroupMb5_64bWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } + } + #[doc = "0x218 - Message Buffer 25 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb25_8b_word0(&self) -> &Mb8bGroupMb25_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } + } + #[doc = "0x218 - Message Buffer 17 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb17_16b_cs(&self) -> &Mb16bGroupMb17_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } + } + #[doc = "0x218 - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word0(&self) -> &Mb32bGroupMb10_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } + } + #[doc = "0x21c - Message Buffer 25 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word125(&self) -> &MbGroupWord125 { + unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } + } + #[doc = "0x21c - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word11(&self) -> &Mb64bGroupMb5_64bWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } + } + #[doc = "0x21c - Message Buffer 25 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb25_8b_word1(&self) -> &Mb8bGroupMb25_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } + } + #[doc = "0x21c - Message Buffer 17 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb17_16b_id(&self) -> &Mb16bGroupMb17_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } + } + #[doc = "0x21c - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word1(&self) -> &Mb32bGroupMb10_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } + } + #[doc = "0x220 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word12(&self) -> &Mb64bGroupMb5_64bWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } + } + #[doc = "0x220 - Message Buffer 26 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb26_8b_cs(&self) -> &Mb8bGroupMb26_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } + } + #[doc = "0x220 - Message Buffer 17 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb17_16b_word0(&self) -> &Mb16bGroupMb17_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } + } + #[doc = "0x220 - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word2(&self) -> &Mb32bGroupMb10_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } + } + #[doc = "0x220 - Message Buffer 26 CS Register"] + #[inline(always)] + pub const fn mb_group_cs26(&self) -> &MbGroupCs26 { + unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } + } + #[doc = "0x224 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word13(&self) -> &Mb64bGroupMb5_64bWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } + } + #[doc = "0x224 - Message Buffer 26 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb26_8b_id(&self) -> &Mb8bGroupMb26_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } + } + #[doc = "0x224 - Message Buffer 17 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb17_16b_word1(&self) -> &Mb16bGroupMb17_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } + } + #[doc = "0x224 - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word3(&self) -> &Mb32bGroupMb10_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } + } + #[doc = "0x224 - Message Buffer 26 ID Register"] + #[inline(always)] + pub const fn mb_group_id26(&self) -> &MbGroupId26 { + unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } + } + #[doc = "0x228 - Message Buffer 26 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word026(&self) -> &MbGroupWord026 { + unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } + } + #[doc = "0x228 - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word14(&self) -> &Mb64bGroupMb5_64bWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } + } + #[doc = "0x228 - Message Buffer 26 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb26_8b_word0(&self) -> &Mb8bGroupMb26_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } + } + #[doc = "0x228 - Message Buffer 17 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb17_16b_word2(&self) -> &Mb16bGroupMb17_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } + } + #[doc = "0x228 - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word4(&self) -> &Mb32bGroupMb10_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } + } + #[doc = "0x22c - Message Buffer 26 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word126(&self) -> &MbGroupWord126 { + unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } + } + #[doc = "0x22c - Message Buffer 5 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb5_64b_word15(&self) -> &Mb64bGroupMb5_64bWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } + } + #[doc = "0x22c - Message Buffer 26 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb26_8b_word1(&self) -> &Mb8bGroupMb26_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } + } + #[doc = "0x22c - Message Buffer 17 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb17_16b_word3(&self) -> &Mb16bGroupMb17_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } + } + #[doc = "0x22c - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word5(&self) -> &Mb32bGroupMb10_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } + } + #[doc = "0x230 - Message Buffer 6 CS Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_cs(&self) -> &Mb64bGroupMb6_64bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } + } + #[doc = "0x230 - Message Buffer 27 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb27_8b_cs(&self) -> &Mb8bGroupMb27_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } + } + #[doc = "0x230 - Message Buffer 18 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb18_16b_cs(&self) -> &Mb16bGroupMb18_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } + } + #[doc = "0x230 - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word6(&self) -> &Mb32bGroupMb10_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } + } + #[doc = "0x230 - Message Buffer 27 CS Register"] + #[inline(always)] + pub const fn mb_group_cs27(&self) -> &MbGroupCs27 { + unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } + } + #[doc = "0x234 - Message Buffer 6 ID Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_id(&self) -> &Mb64bGroupMb6_64bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } + } + #[doc = "0x234 - Message Buffer 27 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb27_8b_id(&self) -> &Mb8bGroupMb27_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } + } + #[doc = "0x234 - Message Buffer 18 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb18_16b_id(&self) -> &Mb16bGroupMb18_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } + } + #[doc = "0x234 - Message Buffer 10 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb10_32b_word7(&self) -> &Mb32bGroupMb10_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } + } + #[doc = "0x234 - Message Buffer 27 ID Register"] + #[inline(always)] + pub const fn mb_group_id27(&self) -> &MbGroupId27 { + unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } + } + #[doc = "0x238 - Message Buffer 27 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word027(&self) -> &MbGroupWord027 { + unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } + } + #[doc = "0x238 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word0(&self) -> &Mb64bGroupMb6_64bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } + } + #[doc = "0x238 - Message Buffer 27 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb27_8b_word0(&self) -> &Mb8bGroupMb27_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } + } + #[doc = "0x238 - Message Buffer 18 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb18_16b_word0(&self) -> &Mb16bGroupMb18_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } + } + #[doc = "0x238 - Message Buffer 11 CS Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_cs(&self) -> &Mb32bGroupMb11_32bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } + } + #[doc = "0x23c - Message Buffer 27 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word127(&self) -> &MbGroupWord127 { + unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } + } + #[doc = "0x23c - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word1(&self) -> &Mb64bGroupMb6_64bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } + } + #[doc = "0x23c - Message Buffer 27 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb27_8b_word1(&self) -> &Mb8bGroupMb27_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } + } + #[doc = "0x23c - Message Buffer 18 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb18_16b_word1(&self) -> &Mb16bGroupMb18_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } + } + #[doc = "0x23c - Message Buffer 11 ID Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_id(&self) -> &Mb32bGroupMb11_32bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } + } + #[doc = "0x240 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word2(&self) -> &Mb64bGroupMb6_64bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } + } + #[doc = "0x240 - Message Buffer 28 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb28_8b_cs(&self) -> &Mb8bGroupMb28_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } + } + #[doc = "0x240 - Message Buffer 18 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb18_16b_word2(&self) -> &Mb16bGroupMb18_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } + } + #[doc = "0x240 - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word0(&self) -> &Mb32bGroupMb11_32bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } + } + #[doc = "0x240 - Message Buffer 28 CS Register"] + #[inline(always)] + pub const fn mb_group_cs28(&self) -> &MbGroupCs28 { + unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } + } + #[doc = "0x244 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word3(&self) -> &Mb64bGroupMb6_64bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } + } + #[doc = "0x244 - Message Buffer 28 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb28_8b_id(&self) -> &Mb8bGroupMb28_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } + } + #[doc = "0x244 - Message Buffer 18 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb18_16b_word3(&self) -> &Mb16bGroupMb18_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } + } + #[doc = "0x244 - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word1(&self) -> &Mb32bGroupMb11_32bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } + } + #[doc = "0x244 - Message Buffer 28 ID Register"] + #[inline(always)] + pub const fn mb_group_id28(&self) -> &MbGroupId28 { + unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } + } + #[doc = "0x248 - Message Buffer 28 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word028(&self) -> &MbGroupWord028 { + unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } + } + #[doc = "0x248 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word4(&self) -> &Mb64bGroupMb6_64bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } + } + #[doc = "0x248 - Message Buffer 28 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb28_8b_word0(&self) -> &Mb8bGroupMb28_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } + } + #[doc = "0x248 - Message Buffer 19 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb19_16b_cs(&self) -> &Mb16bGroupMb19_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } + } + #[doc = "0x248 - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word2(&self) -> &Mb32bGroupMb11_32bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } + } + #[doc = "0x24c - Message Buffer 28 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word128(&self) -> &MbGroupWord128 { + unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } + } + #[doc = "0x24c - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word5(&self) -> &Mb64bGroupMb6_64bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } + } + #[doc = "0x24c - Message Buffer 28 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb28_8b_word1(&self) -> &Mb8bGroupMb28_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } + } + #[doc = "0x24c - Message Buffer 19 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb19_16b_id(&self) -> &Mb16bGroupMb19_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } + } + #[doc = "0x24c - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word3(&self) -> &Mb32bGroupMb11_32bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } + } + #[doc = "0x250 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word6(&self) -> &Mb64bGroupMb6_64bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } + } + #[doc = "0x250 - Message Buffer 29 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb29_8b_cs(&self) -> &Mb8bGroupMb29_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } + } + #[doc = "0x250 - Message Buffer 19 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb19_16b_word0(&self) -> &Mb16bGroupMb19_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } + } + #[doc = "0x250 - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word4(&self) -> &Mb32bGroupMb11_32bWord4 { + unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } + } + #[doc = "0x250 - Message Buffer 29 CS Register"] + #[inline(always)] + pub const fn mb_group_cs29(&self) -> &MbGroupCs29 { + unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } + } + #[doc = "0x254 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word7(&self) -> &Mb64bGroupMb6_64bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } + } + #[doc = "0x254 - Message Buffer 29 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb29_8b_id(&self) -> &Mb8bGroupMb29_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } + } + #[doc = "0x254 - Message Buffer 19 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb19_16b_word1(&self) -> &Mb16bGroupMb19_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } + } + #[doc = "0x254 - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word5(&self) -> &Mb32bGroupMb11_32bWord5 { + unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } + } + #[doc = "0x254 - Message Buffer 29 ID Register"] + #[inline(always)] + pub const fn mb_group_id29(&self) -> &MbGroupId29 { + unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } + } + #[doc = "0x258 - Message Buffer 29 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word029(&self) -> &MbGroupWord029 { + unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } + } + #[doc = "0x258 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word8(&self) -> &Mb64bGroupMb6_64bWord8 { + unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } + } + #[doc = "0x258 - Message Buffer 29 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb29_8b_word0(&self) -> &Mb8bGroupMb29_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } + } + #[doc = "0x258 - Message Buffer 19 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb19_16b_word2(&self) -> &Mb16bGroupMb19_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } + } + #[doc = "0x258 - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word6(&self) -> &Mb32bGroupMb11_32bWord6 { + unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } + } + #[doc = "0x25c - Message Buffer 29 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word129(&self) -> &MbGroupWord129 { + unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } + } + #[doc = "0x25c - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word9(&self) -> &Mb64bGroupMb6_64bWord9 { + unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } + } + #[doc = "0x25c - Message Buffer 29 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb29_8b_word1(&self) -> &Mb8bGroupMb29_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } + } + #[doc = "0x25c - Message Buffer 19 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb19_16b_word3(&self) -> &Mb16bGroupMb19_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } + } + #[doc = "0x25c - Message Buffer 11 WORD_32B Register"] + #[inline(always)] + pub const fn mb_32b_group_mb11_32b_word7(&self) -> &Mb32bGroupMb11_32bWord7 { + unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } + } + #[doc = "0x260 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word10(&self) -> &Mb64bGroupMb6_64bWord10 { + unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } + } + #[doc = "0x260 - Message Buffer 30 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb30_8b_cs(&self) -> &Mb8bGroupMb30_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } + } + #[doc = "0x260 - Message Buffer 20 CS Register"] + #[inline(always)] + pub const fn mb_16b_group_mb20_16b_cs(&self) -> &Mb16bGroupMb20_16bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } + } + #[doc = "0x260 - Message Buffer 30 CS Register"] + #[inline(always)] + pub const fn mb_group_cs30(&self) -> &MbGroupCs30 { + unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } + } + #[doc = "0x264 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word11(&self) -> &Mb64bGroupMb6_64bWord11 { + unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } + } + #[doc = "0x264 - Message Buffer 30 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb30_8b_id(&self) -> &Mb8bGroupMb30_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } + } + #[doc = "0x264 - Message Buffer 20 ID Register"] + #[inline(always)] + pub const fn mb_16b_group_mb20_16b_id(&self) -> &Mb16bGroupMb20_16bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } + } + #[doc = "0x264 - Message Buffer 30 ID Register"] + #[inline(always)] + pub const fn mb_group_id30(&self) -> &MbGroupId30 { + unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } + } + #[doc = "0x268 - Message Buffer 30 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word030(&self) -> &MbGroupWord030 { + unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } + } + #[doc = "0x268 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word12(&self) -> &Mb64bGroupMb6_64bWord12 { + unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } + } + #[doc = "0x268 - Message Buffer 30 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb30_8b_word0(&self) -> &Mb8bGroupMb30_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } + } + #[doc = "0x268 - Message Buffer 20 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb20_16b_word0(&self) -> &Mb16bGroupMb20_16bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } + } + #[doc = "0x26c - Message Buffer 30 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word130(&self) -> &MbGroupWord130 { + unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } + } + #[doc = "0x26c - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word13(&self) -> &Mb64bGroupMb6_64bWord13 { + unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } + } + #[doc = "0x26c - Message Buffer 30 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb30_8b_word1(&self) -> &Mb8bGroupMb30_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } + } + #[doc = "0x26c - Message Buffer 20 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb20_16b_word1(&self) -> &Mb16bGroupMb20_16bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } + } + #[doc = "0x270 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word14(&self) -> &Mb64bGroupMb6_64bWord14 { + unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } + } + #[doc = "0x270 - Message Buffer 31 CS Register"] + #[inline(always)] + pub const fn mb_8b_group_mb31_8b_cs(&self) -> &Mb8bGroupMb31_8bCs { + unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } + } + #[doc = "0x270 - Message Buffer 20 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb20_16b_word2(&self) -> &Mb16bGroupMb20_16bWord2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } + } + #[doc = "0x270 - Message Buffer 31 CS Register"] + #[inline(always)] + pub const fn mb_group_cs31(&self) -> &MbGroupCs31 { + unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } + } + #[doc = "0x274 - Message Buffer 6 WORD_64B Register"] + #[inline(always)] + pub const fn mb_64b_group_mb6_64b_word15(&self) -> &Mb64bGroupMb6_64bWord15 { + unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } + } + #[doc = "0x274 - Message Buffer 31 ID Register"] + #[inline(always)] + pub const fn mb_8b_group_mb31_8b_id(&self) -> &Mb8bGroupMb31_8bId { + unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } + } + #[doc = "0x274 - Message Buffer 20 WORD_16B Register"] + #[inline(always)] + pub const fn mb_16b_group_mb20_16b_word3(&self) -> &Mb16bGroupMb20_16bWord3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } + } + #[doc = "0x274 - Message Buffer 31 ID Register"] + #[inline(always)] + pub const fn mb_group_id31(&self) -> &MbGroupId31 { + unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } + } + #[doc = "0x278 - Message Buffer 31 WORD0 Register"] + #[inline(always)] + pub const fn mb_group_word031(&self) -> &MbGroupWord031 { + unsafe { &*core::ptr::from_ref(self).cast::().add(632).cast() } + } + #[doc = "0x278 - Message Buffer 31 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb31_8b_word0(&self) -> &Mb8bGroupMb31_8bWord0 { + unsafe { &*core::ptr::from_ref(self).cast::().add(632).cast() } + } + #[doc = "0x27c - Message Buffer 31 WORD1 Register"] + #[inline(always)] + pub const fn mb_group_word131(&self) -> &MbGroupWord131 { + unsafe { &*core::ptr::from_ref(self).cast::().add(636).cast() } + } + #[doc = "0x27c - Message Buffer 31 WORD_8B Register"] + #[inline(always)] + pub const fn mb_8b_group_mb31_8b_word1(&self) -> &Mb8bGroupMb31_8bWord1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(636).cast() } + } + #[doc = "0x880..0x900 - Receive Individual Mask"] + #[inline(always)] + pub const fn rximr(&self, n: usize) -> &Rximr { + &self.rximr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x880..0x900 - Receive Individual Mask"] + #[inline(always)] + pub fn rximr_iter(&self) -> impl Iterator { + self.rximr.iter() + } + #[doc = "0xb00 - Pretended Networking Control 1"] + #[inline(always)] + pub const fn ctrl1_pn(&self) -> &Ctrl1Pn { + &self.ctrl1_pn + } + #[doc = "0xb04 - Pretended Networking Control 2"] + #[inline(always)] + pub const fn ctrl2_pn(&self) -> &Ctrl2Pn { + &self.ctrl2_pn + } + #[doc = "0xb08 - Pretended Networking Wake-Up Match"] + #[inline(always)] + pub const fn wu_mtc(&self) -> &WuMtc { + &self.wu_mtc + } + #[doc = "0xb0c - Pretended Networking ID Filter 1"] + #[inline(always)] + pub const fn flt_id1(&self) -> &FltId1 { + &self.flt_id1 + } + #[doc = "0xb10 - Pretended Networking Data Length Code (DLC) Filter"] + #[inline(always)] + pub const fn flt_dlc(&self) -> &FltDlc { + &self.flt_dlc + } + #[doc = "0xb14 - Pretended Networking Payload Low Filter 1"] + #[inline(always)] + pub const fn pl1_lo(&self) -> &Pl1Lo { + &self.pl1_lo + } + #[doc = "0xb18 - Pretended Networking Payload High Filter 1"] + #[inline(always)] + pub const fn pl1_hi(&self) -> &Pl1Hi { + &self.pl1_hi + } + #[doc = "0xb1c - Pretended Networking ID Filter 2 or ID Mask"] + #[inline(always)] + pub const fn flt_id2_idmask(&self) -> &FltId2Idmask { + &self.flt_id2_idmask + } + #[doc = "0xb20 - Pretended Networking Payload Low Filter 2 and Payload Low Mask"] + #[inline(always)] + pub const fn pl2_plmask_lo(&self) -> &Pl2PlmaskLo { + &self.pl2_plmask_lo + } + #[doc = "0xb24 - Pretended Networking Payload High Filter 2 and Payload High Mask"] + #[inline(always)] + pub const fn pl2_plmask_hi(&self) -> &Pl2PlmaskHi { + &self.pl2_plmask_hi + } + #[doc = "0xb40..0xb80 - Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] + #[inline(always)] + pub const fn wmb(&self, n: usize) -> &Wmb { + &self.wmb[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xb40..0xb80 - Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] + #[inline(always)] + pub fn wmb_iter(&self) -> impl Iterator { + self.wmb.iter() + } + #[doc = "0xbf0 - Enhanced CAN Bit Timing Prescalers"] + #[inline(always)] + pub const fn eprs(&self) -> &Eprs { + &self.eprs + } + #[doc = "0xbf4 - Enhanced Nominal CAN Bit Timing"] + #[inline(always)] + pub const fn encbt(&self) -> &Encbt { + &self.encbt + } + #[doc = "0xbf8 - Enhanced Data Phase CAN Bit Timing"] + #[inline(always)] + pub const fn edcbt(&self) -> &Edcbt { + &self.edcbt + } + #[doc = "0xbfc - Enhanced Transceiver Delay Compensation"] + #[inline(always)] + pub const fn etdc(&self) -> &Etdc { + &self.etdc + } + #[doc = "0xc00 - CAN FD Control"] + #[inline(always)] + pub const fn fdctrl(&self) -> &Fdctrl { + &self.fdctrl + } + #[doc = "0xc04 - CAN FD Bit Timing"] + #[inline(always)] + pub const fn fdcbt(&self) -> &Fdcbt { + &self.fdcbt + } + #[doc = "0xc08 - CAN FD CRC"] + #[inline(always)] + pub const fn fdcrc(&self) -> &Fdcrc { + &self.fdcrc + } + #[doc = "0xc0c - Enhanced RX FIFO Control"] + #[inline(always)] + pub const fn erfcr(&self) -> &Erfcr { + &self.erfcr + } + #[doc = "0xc10 - Enhanced RX FIFO Interrupt Enable"] + #[inline(always)] + pub const fn erfier(&self) -> &Erfier { + &self.erfier + } + #[doc = "0xc14 - Enhanced RX FIFO Status"] + #[inline(always)] + pub const fn erfsr(&self) -> &Erfsr { + &self.erfsr + } + #[doc = "0x3000..0x3080 - Enhanced RX FIFO Filter Element"] + #[inline(always)] + pub const fn erffel(&self, n: usize) -> &Erffel { + &self.erffel[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x3000..0x3080 - Enhanced RX FIFO Filter Element"] + #[inline(always)] + pub fn erffel_iter(&self) -> impl Iterator { + self.erffel.iter() + } +} +#[doc = "MCR (rw) register accessor: Module Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] +#[doc(alias = "MCR")] +pub type Mcr = crate::Reg; +#[doc = "Module Configuration"] +pub mod mcr; +#[doc = "CTRL1 (rw) register accessor: Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Control 1"] +pub mod ctrl1; +#[doc = "TIMER (rw) register accessor: Free-Running Timer\n\nYou can [`read`](crate::Reg::read) this register and get [`timer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer`] module"] +#[doc(alias = "TIMER")] +pub type Timer = crate::Reg; +#[doc = "Free-Running Timer"] +pub mod timer; +#[doc = "RXMGMASK (rw) register accessor: RX Message Buffers Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxmgmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxmgmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxmgmask`] module"] +#[doc(alias = "RXMGMASK")] +pub type Rxmgmask = crate::Reg; +#[doc = "RX Message Buffers Global Mask"] +pub mod rxmgmask; +#[doc = "RX14MASK (rw) register accessor: Receive 14 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx14mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx14mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx14mask`] module"] +#[doc(alias = "RX14MASK")] +pub type Rx14mask = crate::Reg; +#[doc = "Receive 14 Mask"] +pub mod rx14mask; +#[doc = "RX15MASK (rw) register accessor: Receive 15 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx15mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx15mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx15mask`] module"] +#[doc(alias = "RX15MASK")] +pub type Rx15mask = crate::Reg; +#[doc = "Receive 15 Mask"] +pub mod rx15mask; +#[doc = "ECR (rw) register accessor: Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`] module"] +#[doc(alias = "ECR")] +pub type Ecr = crate::Reg; +#[doc = "Error Counter"] +pub mod ecr; +#[doc = "ESR1 (rw) register accessor: Error and Status 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr1`] module"] +#[doc(alias = "ESR1")] +pub type Esr1 = crate::Reg; +#[doc = "Error and Status 1"] +pub mod esr1; +#[doc = "IMASK1 (rw) register accessor: Interrupt Masks 1\n\nYou can [`read`](crate::Reg::read) this register and get [`imask1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imask1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask1`] module"] +#[doc(alias = "IMASK1")] +pub type Imask1 = crate::Reg; +#[doc = "Interrupt Masks 1"] +pub mod imask1; +#[doc = "IFLAG1 (rw) register accessor: Interrupt Flags 1\n\nYou can [`read`](crate::Reg::read) this register and get [`iflag1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iflag1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iflag1`] module"] +#[doc(alias = "IFLAG1")] +pub type Iflag1 = crate::Reg; +#[doc = "Interrupt Flags 1"] +pub mod iflag1; +#[doc = "CTRL2 (rw) register accessor: Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"] +#[doc(alias = "CTRL2")] +pub type Ctrl2 = crate::Reg; +#[doc = "Control 2"] +pub mod ctrl2; +#[doc = "ESR2 (r) register accessor: Error and Status 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr2`] module"] +#[doc(alias = "ESR2")] +pub type Esr2 = crate::Reg; +#[doc = "Error and Status 2"] +pub mod esr2; +#[doc = "CRCR (r) register accessor: Cyclic Redundancy Check\n\nYou can [`read`](crate::Reg::read) this register and get [`crcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcr`] module"] +#[doc(alias = "CRCR")] +pub type Crcr = crate::Reg; +#[doc = "Cyclic Redundancy Check"] +pub mod crcr; +#[doc = "RXFGMASK (rw) register accessor: Legacy RX FIFO Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfgmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfgmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfgmask`] module"] +#[doc(alias = "RXFGMASK")] +pub type Rxfgmask = crate::Reg; +#[doc = "Legacy RX FIFO Global Mask"] +pub mod rxfgmask; +#[doc = "RXFIR (r) register accessor: Legacy RX FIFO Information\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfir`] module"] +#[doc(alias = "RXFIR")] +pub type Rxfir = crate::Reg; +#[doc = "Legacy RX FIFO Information"] +pub mod rxfir; +#[doc = "CBT (rw) register accessor: CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`cbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbt`] module"] +#[doc(alias = "CBT")] +pub type Cbt = crate::Reg; +#[doc = "CAN Bit Timing"] +pub mod cbt; +#[doc = "MB_GROUP_CS0 (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs0`] module"] +#[doc(alias = "MB_GROUP_CS0")] +pub type MbGroupCs0 = crate::Reg; +#[doc = "Message Buffer 0 CS Register"] +pub mod mb_group_cs0; +#[doc = "MB_16B_GROUP_MB0_16B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB0_16B_CS")] +pub type Mb16bGroupMb0_16bCs = crate::Reg; +#[doc = "Message Buffer 0 CS Register"] +pub mod mb_16b_group_mb0_16b_cs; +#[doc = "MB_32B_GROUP_MB0_32B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_CS")] +pub type Mb32bGroupMb0_32bCs = crate::Reg; +#[doc = "Message Buffer 0 CS Register"] +pub mod mb_32b_group_mb0_32b_cs; +#[doc = "MB_64B_GROUP_MB0_64B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_cs`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_CS")] +pub type Mb64bGroupMb0_64bCs = crate::Reg; +#[doc = "Message Buffer 0 CS Register"] +pub mod mb_64b_group_mb0_64b_cs; +#[doc = "MB_8B_GROUP_MB0_8B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB0_8B_CS")] +pub type Mb8bGroupMb0_8bCs = crate::Reg; +#[doc = "Message Buffer 0 CS Register"] +pub mod mb_8b_group_mb0_8b_cs; +#[doc = "MB_GROUP_ID0 (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id0`] module"] +#[doc(alias = "MB_GROUP_ID0")] +pub type MbGroupId0 = crate::Reg; +#[doc = "Message Buffer 0 ID Register"] +pub mod mb_group_id0; +#[doc = "MB_16B_GROUP_MB0_16B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB0_16B_ID")] +pub type Mb16bGroupMb0_16bId = crate::Reg; +#[doc = "Message Buffer 0 ID Register"] +pub mod mb_16b_group_mb0_16b_id; +#[doc = "MB_32B_GROUP_MB0_32B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_ID")] +pub type Mb32bGroupMb0_32bId = crate::Reg; +#[doc = "Message Buffer 0 ID Register"] +pub mod mb_32b_group_mb0_32b_id; +#[doc = "MB_64B_GROUP_MB0_64B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_id`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_ID")] +pub type Mb64bGroupMb0_64bId = crate::Reg; +#[doc = "Message Buffer 0 ID Register"] +pub mod mb_64b_group_mb0_64b_id; +#[doc = "MB_8B_GROUP_MB0_8B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB0_8B_ID")] +pub type Mb8bGroupMb0_8bId = crate::Reg; +#[doc = "Message Buffer 0 ID Register"] +pub mod mb_8b_group_mb0_8b_id; +#[doc = "MB_16B_GROUP_MB0_16B_WORD0 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD0")] +pub type Mb16bGroupMb0_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_16B Register"] +pub mod mb_16b_group_mb0_16b_word0; +#[doc = "MB_32B_GROUP_MB0_32B_WORD0 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD0")] +pub type Mb32bGroupMb0_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word0; +#[doc = "MB_64B_GROUP_MB0_64B_WORD0 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word0`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD0")] +pub type Mb64bGroupMb0_64bWord0 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word0; +#[doc = "MB_8B_GROUP_MB0_8B_WORD0 (rw) register accessor: Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB0_8B_WORD0")] +pub type Mb8bGroupMb0_8bWord0 = crate::Reg; +#[doc = "Message Buffer 0 WORD_8B Register"] +pub mod mb_8b_group_mb0_8b_word0; +#[doc = "MB_GROUP_WORD00 (rw) register accessor: Message Buffer 0 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word00::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word00::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word00`] module"] +#[doc(alias = "MB_GROUP_WORD00")] +pub type MbGroupWord00 = crate::Reg; +#[doc = "Message Buffer 0 WORD0 Register"] +pub mod mb_group_word00; +#[doc = "MB_16B_GROUP_MB0_16B_WORD1 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD1")] +pub type Mb16bGroupMb0_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_16B Register"] +pub mod mb_16b_group_mb0_16b_word1; +#[doc = "MB_32B_GROUP_MB0_32B_WORD1 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD1")] +pub type Mb32bGroupMb0_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word1; +#[doc = "MB_64B_GROUP_MB0_64B_WORD1 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word1`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD1")] +pub type Mb64bGroupMb0_64bWord1 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word1; +#[doc = "MB_8B_GROUP_MB0_8B_WORD1 (rw) register accessor: Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB0_8B_WORD1")] +pub type Mb8bGroupMb0_8bWord1 = crate::Reg; +#[doc = "Message Buffer 0 WORD_8B Register"] +pub mod mb_8b_group_mb0_8b_word1; +#[doc = "MB_GROUP_WORD10 (rw) register accessor: Message Buffer 0 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word10`] module"] +#[doc(alias = "MB_GROUP_WORD10")] +pub type MbGroupWord10 = crate::Reg; +#[doc = "Message Buffer 0 WORD1 Register"] +pub mod mb_group_word10; +#[doc = "MB_GROUP_CS1 (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs1`] module"] +#[doc(alias = "MB_GROUP_CS1")] +pub type MbGroupCs1 = crate::Reg; +#[doc = "Message Buffer 1 CS Register"] +pub mod mb_group_cs1; +#[doc = "MB_16B_GROUP_MB0_16B_WORD2 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD2")] +pub type Mb16bGroupMb0_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_16B Register"] +pub mod mb_16b_group_mb0_16b_word2; +#[doc = "MB_32B_GROUP_MB0_32B_WORD2 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD2")] +pub type Mb32bGroupMb0_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word2; +#[doc = "MB_64B_GROUP_MB0_64B_WORD2 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word2`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD2")] +pub type Mb64bGroupMb0_64bWord2 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word2; +#[doc = "MB_8B_GROUP_MB1_8B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB1_8B_CS")] +pub type Mb8bGroupMb1_8bCs = crate::Reg; +#[doc = "Message Buffer 1 CS Register"] +pub mod mb_8b_group_mb1_8b_cs; +#[doc = "MB_GROUP_ID1 (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id1`] module"] +#[doc(alias = "MB_GROUP_ID1")] +pub type MbGroupId1 = crate::Reg; +#[doc = "Message Buffer 1 ID Register"] +pub mod mb_group_id1; +#[doc = "MB_16B_GROUP_MB0_16B_WORD3 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD3")] +pub type Mb16bGroupMb0_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_16B Register"] +pub mod mb_16b_group_mb0_16b_word3; +#[doc = "MB_32B_GROUP_MB0_32B_WORD3 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD3")] +pub type Mb32bGroupMb0_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word3; +#[doc = "MB_64B_GROUP_MB0_64B_WORD3 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word3`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD3")] +pub type Mb64bGroupMb0_64bWord3 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word3; +#[doc = "MB_8B_GROUP_MB1_8B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB1_8B_ID")] +pub type Mb8bGroupMb1_8bId = crate::Reg; +#[doc = "Message Buffer 1 ID Register"] +pub mod mb_8b_group_mb1_8b_id; +#[doc = "MB_32B_GROUP_MB0_32B_WORD4 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD4")] +pub type Mb32bGroupMb0_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word4; +#[doc = "MB_64B_GROUP_MB0_64B_WORD4 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word4`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD4")] +pub type Mb64bGroupMb0_64bWord4 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word4; +#[doc = "MB_16B_GROUP_MB1_16B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB1_16B_CS")] +pub type Mb16bGroupMb1_16bCs = crate::Reg; +#[doc = "Message Buffer 1 CS Register"] +pub mod mb_16b_group_mb1_16b_cs; +#[doc = "MB_8B_GROUP_MB1_8B_WORD0 (rw) register accessor: Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB1_8B_WORD0")] +pub type Mb8bGroupMb1_8bWord0 = crate::Reg; +#[doc = "Message Buffer 1 WORD_8B Register"] +pub mod mb_8b_group_mb1_8b_word0; +#[doc = "MB_GROUP_WORD01 (rw) register accessor: Message Buffer 1 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word01::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word01::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word01`] module"] +#[doc(alias = "MB_GROUP_WORD01")] +pub type MbGroupWord01 = crate::Reg; +#[doc = "Message Buffer 1 WORD0 Register"] +pub mod mb_group_word01; +#[doc = "MB_32B_GROUP_MB0_32B_WORD5 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD5")] +pub type Mb32bGroupMb0_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word5; +#[doc = "MB_64B_GROUP_MB0_64B_WORD5 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word5`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD5")] +pub type Mb64bGroupMb0_64bWord5 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word5; +#[doc = "MB_16B_GROUP_MB1_16B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB1_16B_ID")] +pub type Mb16bGroupMb1_16bId = crate::Reg; +#[doc = "Message Buffer 1 ID Register"] +pub mod mb_16b_group_mb1_16b_id; +#[doc = "MB_8B_GROUP_MB1_8B_WORD1 (rw) register accessor: Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB1_8B_WORD1")] +pub type Mb8bGroupMb1_8bWord1 = crate::Reg; +#[doc = "Message Buffer 1 WORD_8B Register"] +pub mod mb_8b_group_mb1_8b_word1; +#[doc = "MB_GROUP_WORD11 (rw) register accessor: Message Buffer 1 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word11`] module"] +#[doc(alias = "MB_GROUP_WORD11")] +pub type MbGroupWord11 = crate::Reg; +#[doc = "Message Buffer 1 WORD1 Register"] +pub mod mb_group_word11; +#[doc = "MB_GROUP_CS2 (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs2`] module"] +#[doc(alias = "MB_GROUP_CS2")] +pub type MbGroupCs2 = crate::Reg; +#[doc = "Message Buffer 2 CS Register"] +pub mod mb_group_cs2; +#[doc = "MB_32B_GROUP_MB0_32B_WORD6 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD6")] +pub type Mb32bGroupMb0_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word6; +#[doc = "MB_64B_GROUP_MB0_64B_WORD6 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word6`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD6")] +pub type Mb64bGroupMb0_64bWord6 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word6; +#[doc = "MB_16B_GROUP_MB1_16B_WORD0 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD0")] +pub type Mb16bGroupMb1_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_16B Register"] +pub mod mb_16b_group_mb1_16b_word0; +#[doc = "MB_8B_GROUP_MB2_8B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB2_8B_CS")] +pub type Mb8bGroupMb2_8bCs = crate::Reg; +#[doc = "Message Buffer 2 CS Register"] +pub mod mb_8b_group_mb2_8b_cs; +#[doc = "MB_GROUP_ID2 (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id2`] module"] +#[doc(alias = "MB_GROUP_ID2")] +pub type MbGroupId2 = crate::Reg; +#[doc = "Message Buffer 2 ID Register"] +pub mod mb_group_id2; +#[doc = "MB_32B_GROUP_MB0_32B_WORD7 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD7")] +pub type Mb32bGroupMb0_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_32B Register"] +pub mod mb_32b_group_mb0_32b_word7; +#[doc = "MB_64B_GROUP_MB0_64B_WORD7 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word7`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD7")] +pub type Mb64bGroupMb0_64bWord7 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word7; +#[doc = "MB_16B_GROUP_MB1_16B_WORD1 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD1")] +pub type Mb16bGroupMb1_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_16B Register"] +pub mod mb_16b_group_mb1_16b_word1; +#[doc = "MB_8B_GROUP_MB2_8B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB2_8B_ID")] +pub type Mb8bGroupMb2_8bId = crate::Reg; +#[doc = "Message Buffer 2 ID Register"] +pub mod mb_8b_group_mb2_8b_id; +#[doc = "MB_64B_GROUP_MB0_64B_WORD8 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word8`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD8")] +pub type Mb64bGroupMb0_64bWord8 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word8; +#[doc = "MB_16B_GROUP_MB1_16B_WORD2 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD2")] +pub type Mb16bGroupMb1_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_16B Register"] +pub mod mb_16b_group_mb1_16b_word2; +#[doc = "MB_32B_GROUP_MB1_32B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_CS")] +pub type Mb32bGroupMb1_32bCs = crate::Reg; +#[doc = "Message Buffer 1 CS Register"] +pub mod mb_32b_group_mb1_32b_cs; +#[doc = "MB_8B_GROUP_MB2_8B_WORD0 (rw) register accessor: Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB2_8B_WORD0")] +pub type Mb8bGroupMb2_8bWord0 = crate::Reg; +#[doc = "Message Buffer 2 WORD_8B Register"] +pub mod mb_8b_group_mb2_8b_word0; +#[doc = "MB_GROUP_WORD02 (rw) register accessor: Message Buffer 2 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word02::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word02::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word02`] module"] +#[doc(alias = "MB_GROUP_WORD02")] +pub type MbGroupWord02 = crate::Reg; +#[doc = "Message Buffer 2 WORD0 Register"] +pub mod mb_group_word02; +#[doc = "MB_64B_GROUP_MB0_64B_WORD9 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word9`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD9")] +pub type Mb64bGroupMb0_64bWord9 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word9; +#[doc = "MB_16B_GROUP_MB1_16B_WORD3 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD3")] +pub type Mb16bGroupMb1_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_16B Register"] +pub mod mb_16b_group_mb1_16b_word3; +#[doc = "MB_32B_GROUP_MB1_32B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_ID")] +pub type Mb32bGroupMb1_32bId = crate::Reg; +#[doc = "Message Buffer 1 ID Register"] +pub mod mb_32b_group_mb1_32b_id; +#[doc = "MB_8B_GROUP_MB2_8B_WORD1 (rw) register accessor: Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB2_8B_WORD1")] +pub type Mb8bGroupMb2_8bWord1 = crate::Reg; +#[doc = "Message Buffer 2 WORD_8B Register"] +pub mod mb_8b_group_mb2_8b_word1; +#[doc = "MB_GROUP_WORD12 (rw) register accessor: Message Buffer 2 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word12`] module"] +#[doc(alias = "MB_GROUP_WORD12")] +pub type MbGroupWord12 = crate::Reg; +#[doc = "Message Buffer 2 WORD1 Register"] +pub mod mb_group_word12; +#[doc = "MB_GROUP_CS3 (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs3`] module"] +#[doc(alias = "MB_GROUP_CS3")] +pub type MbGroupCs3 = crate::Reg; +#[doc = "Message Buffer 3 CS Register"] +pub mod mb_group_cs3; +#[doc = "MB_64B_GROUP_MB0_64B_WORD10 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word10`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD10")] +pub type Mb64bGroupMb0_64bWord10 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word10; +#[doc = "MB_32B_GROUP_MB1_32B_WORD0 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD0")] +pub type Mb32bGroupMb1_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word0; +#[doc = "MB_16B_GROUP_MB2_16B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB2_16B_CS")] +pub type Mb16bGroupMb2_16bCs = crate::Reg; +#[doc = "Message Buffer 2 CS Register"] +pub mod mb_16b_group_mb2_16b_cs; +#[doc = "MB_8B_GROUP_MB3_8B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB3_8B_CS")] +pub type Mb8bGroupMb3_8bCs = crate::Reg; +#[doc = "Message Buffer 3 CS Register"] +pub mod mb_8b_group_mb3_8b_cs; +#[doc = "MB_GROUP_ID3 (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id3`] module"] +#[doc(alias = "MB_GROUP_ID3")] +pub type MbGroupId3 = crate::Reg; +#[doc = "Message Buffer 3 ID Register"] +pub mod mb_group_id3; +#[doc = "MB_64B_GROUP_MB0_64B_WORD11 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word11`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD11")] +pub type Mb64bGroupMb0_64bWord11 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word11; +#[doc = "MB_32B_GROUP_MB1_32B_WORD1 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD1")] +pub type Mb32bGroupMb1_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word1; +#[doc = "MB_16B_GROUP_MB2_16B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB2_16B_ID")] +pub type Mb16bGroupMb2_16bId = crate::Reg; +#[doc = "Message Buffer 2 ID Register"] +pub mod mb_16b_group_mb2_16b_id; +#[doc = "MB_8B_GROUP_MB3_8B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB3_8B_ID")] +pub type Mb8bGroupMb3_8bId = crate::Reg; +#[doc = "Message Buffer 3 ID Register"] +pub mod mb_8b_group_mb3_8b_id; +#[doc = "MB_64B_GROUP_MB0_64B_WORD12 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word12`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD12")] +pub type Mb64bGroupMb0_64bWord12 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word12; +#[doc = "MB_32B_GROUP_MB1_32B_WORD2 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD2")] +pub type Mb32bGroupMb1_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word2; +#[doc = "MB_16B_GROUP_MB2_16B_WORD0 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD0")] +pub type Mb16bGroupMb2_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_16B Register"] +pub mod mb_16b_group_mb2_16b_word0; +#[doc = "MB_8B_GROUP_MB3_8B_WORD0 (rw) register accessor: Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB3_8B_WORD0")] +pub type Mb8bGroupMb3_8bWord0 = crate::Reg; +#[doc = "Message Buffer 3 WORD_8B Register"] +pub mod mb_8b_group_mb3_8b_word0; +#[doc = "MB_GROUP_WORD03 (rw) register accessor: Message Buffer 3 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word03::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word03::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word03`] module"] +#[doc(alias = "MB_GROUP_WORD03")] +pub type MbGroupWord03 = crate::Reg; +#[doc = "Message Buffer 3 WORD0 Register"] +pub mod mb_group_word03; +#[doc = "MB_64B_GROUP_MB0_64B_WORD13 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word13`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD13")] +pub type Mb64bGroupMb0_64bWord13 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word13; +#[doc = "MB_32B_GROUP_MB1_32B_WORD3 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD3")] +pub type Mb32bGroupMb1_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word3; +#[doc = "MB_16B_GROUP_MB2_16B_WORD1 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD1")] +pub type Mb16bGroupMb2_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_16B Register"] +pub mod mb_16b_group_mb2_16b_word1; +#[doc = "MB_8B_GROUP_MB3_8B_WORD1 (rw) register accessor: Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB3_8B_WORD1")] +pub type Mb8bGroupMb3_8bWord1 = crate::Reg; +#[doc = "Message Buffer 3 WORD_8B Register"] +pub mod mb_8b_group_mb3_8b_word1; +#[doc = "MB_GROUP_WORD13 (rw) register accessor: Message Buffer 3 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word13`] module"] +#[doc(alias = "MB_GROUP_WORD13")] +pub type MbGroupWord13 = crate::Reg; +#[doc = "Message Buffer 3 WORD1 Register"] +pub mod mb_group_word13; +#[doc = "MB_GROUP_CS4 (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs4`] module"] +#[doc(alias = "MB_GROUP_CS4")] +pub type MbGroupCs4 = crate::Reg; +#[doc = "Message Buffer 4 CS Register"] +pub mod mb_group_cs4; +#[doc = "MB_64B_GROUP_MB0_64B_WORD14 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word14`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD14")] +pub type Mb64bGroupMb0_64bWord14 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word14; +#[doc = "MB_32B_GROUP_MB1_32B_WORD4 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD4")] +pub type Mb32bGroupMb1_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word4; +#[doc = "MB_16B_GROUP_MB2_16B_WORD2 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD2")] +pub type Mb16bGroupMb2_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_16B Register"] +pub mod mb_16b_group_mb2_16b_word2; +#[doc = "MB_8B_GROUP_MB4_8B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB4_8B_CS")] +pub type Mb8bGroupMb4_8bCs = crate::Reg; +#[doc = "Message Buffer 4 CS Register"] +pub mod mb_8b_group_mb4_8b_cs; +#[doc = "MB_GROUP_ID4 (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id4`] module"] +#[doc(alias = "MB_GROUP_ID4")] +pub type MbGroupId4 = crate::Reg; +#[doc = "Message Buffer 4 ID Register"] +pub mod mb_group_id4; +#[doc = "MB_64B_GROUP_MB0_64B_WORD15 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word15`] module"] +#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD15")] +pub type Mb64bGroupMb0_64bWord15 = + crate::Reg; +#[doc = "Message Buffer 0 WORD_64B Register"] +pub mod mb_64b_group_mb0_64b_word15; +#[doc = "MB_32B_GROUP_MB1_32B_WORD5 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD5")] +pub type Mb32bGroupMb1_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word5; +#[doc = "MB_16B_GROUP_MB2_16B_WORD3 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD3")] +pub type Mb16bGroupMb2_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_16B Register"] +pub mod mb_16b_group_mb2_16b_word3; +#[doc = "MB_8B_GROUP_MB4_8B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB4_8B_ID")] +pub type Mb8bGroupMb4_8bId = crate::Reg; +#[doc = "Message Buffer 4 ID Register"] +pub mod mb_8b_group_mb4_8b_id; +#[doc = "MB_32B_GROUP_MB1_32B_WORD6 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD6")] +pub type Mb32bGroupMb1_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word6; +#[doc = "MB_64B_GROUP_MB1_64B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_cs`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_CS")] +pub type Mb64bGroupMb1_64bCs = crate::Reg; +#[doc = "Message Buffer 1 CS Register"] +pub mod mb_64b_group_mb1_64b_cs; +#[doc = "MB_16B_GROUP_MB3_16B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB3_16B_CS")] +pub type Mb16bGroupMb3_16bCs = crate::Reg; +#[doc = "Message Buffer 3 CS Register"] +pub mod mb_16b_group_mb3_16b_cs; +#[doc = "MB_8B_GROUP_MB4_8B_WORD0 (rw) register accessor: Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB4_8B_WORD0")] +pub type Mb8bGroupMb4_8bWord0 = crate::Reg; +#[doc = "Message Buffer 4 WORD_8B Register"] +pub mod mb_8b_group_mb4_8b_word0; +#[doc = "MB_GROUP_WORD04 (rw) register accessor: Message Buffer 4 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word04::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word04::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word04`] module"] +#[doc(alias = "MB_GROUP_WORD04")] +pub type MbGroupWord04 = crate::Reg; +#[doc = "Message Buffer 4 WORD0 Register"] +pub mod mb_group_word04; +#[doc = "MB_32B_GROUP_MB1_32B_WORD7 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD7")] +pub type Mb32bGroupMb1_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_32B Register"] +pub mod mb_32b_group_mb1_32b_word7; +#[doc = "MB_64B_GROUP_MB1_64B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_id`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_ID")] +pub type Mb64bGroupMb1_64bId = crate::Reg; +#[doc = "Message Buffer 1 ID Register"] +pub mod mb_64b_group_mb1_64b_id; +#[doc = "MB_16B_GROUP_MB3_16B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB3_16B_ID")] +pub type Mb16bGroupMb3_16bId = crate::Reg; +#[doc = "Message Buffer 3 ID Register"] +pub mod mb_16b_group_mb3_16b_id; +#[doc = "MB_8B_GROUP_MB4_8B_WORD1 (rw) register accessor: Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB4_8B_WORD1")] +pub type Mb8bGroupMb4_8bWord1 = crate::Reg; +#[doc = "Message Buffer 4 WORD_8B Register"] +pub mod mb_8b_group_mb4_8b_word1; +#[doc = "MB_GROUP_WORD14 (rw) register accessor: Message Buffer 4 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word14`] module"] +#[doc(alias = "MB_GROUP_WORD14")] +pub type MbGroupWord14 = crate::Reg; +#[doc = "Message Buffer 4 WORD1 Register"] +pub mod mb_group_word14; +#[doc = "MB_GROUP_CS5 (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs5`] module"] +#[doc(alias = "MB_GROUP_CS5")] +pub type MbGroupCs5 = crate::Reg; +#[doc = "Message Buffer 5 CS Register"] +pub mod mb_group_cs5; +#[doc = "MB_64B_GROUP_MB1_64B_WORD0 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word0`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD0")] +pub type Mb64bGroupMb1_64bWord0 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word0; +#[doc = "MB_32B_GROUP_MB2_32B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_CS")] +pub type Mb32bGroupMb2_32bCs = crate::Reg; +#[doc = "Message Buffer 2 CS Register"] +pub mod mb_32b_group_mb2_32b_cs; +#[doc = "MB_16B_GROUP_MB3_16B_WORD0 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD0")] +pub type Mb16bGroupMb3_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_16B Register"] +pub mod mb_16b_group_mb3_16b_word0; +#[doc = "MB_8B_GROUP_MB5_8B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB5_8B_CS")] +pub type Mb8bGroupMb5_8bCs = crate::Reg; +#[doc = "Message Buffer 5 CS Register"] +pub mod mb_8b_group_mb5_8b_cs; +#[doc = "MB_GROUP_ID5 (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id5`] module"] +#[doc(alias = "MB_GROUP_ID5")] +pub type MbGroupId5 = crate::Reg; +#[doc = "Message Buffer 5 ID Register"] +pub mod mb_group_id5; +#[doc = "MB_64B_GROUP_MB1_64B_WORD1 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word1`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD1")] +pub type Mb64bGroupMb1_64bWord1 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word1; +#[doc = "MB_32B_GROUP_MB2_32B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_ID")] +pub type Mb32bGroupMb2_32bId = crate::Reg; +#[doc = "Message Buffer 2 ID Register"] +pub mod mb_32b_group_mb2_32b_id; +#[doc = "MB_16B_GROUP_MB3_16B_WORD1 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD1")] +pub type Mb16bGroupMb3_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_16B Register"] +pub mod mb_16b_group_mb3_16b_word1; +#[doc = "MB_8B_GROUP_MB5_8B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB5_8B_ID")] +pub type Mb8bGroupMb5_8bId = crate::Reg; +#[doc = "Message Buffer 5 ID Register"] +pub mod mb_8b_group_mb5_8b_id; +#[doc = "MB_64B_GROUP_MB1_64B_WORD2 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word2`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD2")] +pub type Mb64bGroupMb1_64bWord2 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word2; +#[doc = "MB_32B_GROUP_MB2_32B_WORD0 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD0")] +pub type Mb32bGroupMb2_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word0; +#[doc = "MB_16B_GROUP_MB3_16B_WORD2 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD2")] +pub type Mb16bGroupMb3_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_16B Register"] +pub mod mb_16b_group_mb3_16b_word2; +#[doc = "MB_8B_GROUP_MB5_8B_WORD0 (rw) register accessor: Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB5_8B_WORD0")] +pub type Mb8bGroupMb5_8bWord0 = crate::Reg; +#[doc = "Message Buffer 5 WORD_8B Register"] +pub mod mb_8b_group_mb5_8b_word0; +#[doc = "MB_GROUP_WORD05 (rw) register accessor: Message Buffer 5 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word05::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word05::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word05`] module"] +#[doc(alias = "MB_GROUP_WORD05")] +pub type MbGroupWord05 = crate::Reg; +#[doc = "Message Buffer 5 WORD0 Register"] +pub mod mb_group_word05; +#[doc = "MB_64B_GROUP_MB1_64B_WORD3 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word3`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD3")] +pub type Mb64bGroupMb1_64bWord3 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word3; +#[doc = "MB_32B_GROUP_MB2_32B_WORD1 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD1")] +pub type Mb32bGroupMb2_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word1; +#[doc = "MB_16B_GROUP_MB3_16B_WORD3 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD3")] +pub type Mb16bGroupMb3_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_16B Register"] +pub mod mb_16b_group_mb3_16b_word3; +#[doc = "MB_8B_GROUP_MB5_8B_WORD1 (rw) register accessor: Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB5_8B_WORD1")] +pub type Mb8bGroupMb5_8bWord1 = crate::Reg; +#[doc = "Message Buffer 5 WORD_8B Register"] +pub mod mb_8b_group_mb5_8b_word1; +#[doc = "MB_GROUP_WORD15 (rw) register accessor: Message Buffer 5 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word15`] module"] +#[doc(alias = "MB_GROUP_WORD15")] +pub type MbGroupWord15 = crate::Reg; +#[doc = "Message Buffer 5 WORD1 Register"] +pub mod mb_group_word15; +#[doc = "MB_GROUP_CS6 (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs6`] module"] +#[doc(alias = "MB_GROUP_CS6")] +pub type MbGroupCs6 = crate::Reg; +#[doc = "Message Buffer 6 CS Register"] +pub mod mb_group_cs6; +#[doc = "MB_64B_GROUP_MB1_64B_WORD4 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word4`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD4")] +pub type Mb64bGroupMb1_64bWord4 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word4; +#[doc = "MB_32B_GROUP_MB2_32B_WORD2 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD2")] +pub type Mb32bGroupMb2_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word2; +#[doc = "MB_16B_GROUP_MB4_16B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB4_16B_CS")] +pub type Mb16bGroupMb4_16bCs = crate::Reg; +#[doc = "Message Buffer 4 CS Register"] +pub mod mb_16b_group_mb4_16b_cs; +#[doc = "MB_8B_GROUP_MB6_8B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB6_8B_CS")] +pub type Mb8bGroupMb6_8bCs = crate::Reg; +#[doc = "Message Buffer 6 CS Register"] +pub mod mb_8b_group_mb6_8b_cs; +#[doc = "MB_GROUP_ID6 (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id6`] module"] +#[doc(alias = "MB_GROUP_ID6")] +pub type MbGroupId6 = crate::Reg; +#[doc = "Message Buffer 6 ID Register"] +pub mod mb_group_id6; +#[doc = "MB_64B_GROUP_MB1_64B_WORD5 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word5`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD5")] +pub type Mb64bGroupMb1_64bWord5 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word5; +#[doc = "MB_32B_GROUP_MB2_32B_WORD3 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD3")] +pub type Mb32bGroupMb2_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word3; +#[doc = "MB_16B_GROUP_MB4_16B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB4_16B_ID")] +pub type Mb16bGroupMb4_16bId = crate::Reg; +#[doc = "Message Buffer 4 ID Register"] +pub mod mb_16b_group_mb4_16b_id; +#[doc = "MB_8B_GROUP_MB6_8B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB6_8B_ID")] +pub type Mb8bGroupMb6_8bId = crate::Reg; +#[doc = "Message Buffer 6 ID Register"] +pub mod mb_8b_group_mb6_8b_id; +#[doc = "MB_64B_GROUP_MB1_64B_WORD6 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word6`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD6")] +pub type Mb64bGroupMb1_64bWord6 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word6; +#[doc = "MB_32B_GROUP_MB2_32B_WORD4 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD4")] +pub type Mb32bGroupMb2_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word4; +#[doc = "MB_16B_GROUP_MB4_16B_WORD0 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD0")] +pub type Mb16bGroupMb4_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_16B Register"] +pub mod mb_16b_group_mb4_16b_word0; +#[doc = "MB_8B_GROUP_MB6_8B_WORD0 (rw) register accessor: Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB6_8B_WORD0")] +pub type Mb8bGroupMb6_8bWord0 = crate::Reg; +#[doc = "Message Buffer 6 WORD_8B Register"] +pub mod mb_8b_group_mb6_8b_word0; +#[doc = "MB_GROUP_WORD06 (rw) register accessor: Message Buffer 6 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word06::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word06::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word06`] module"] +#[doc(alias = "MB_GROUP_WORD06")] +pub type MbGroupWord06 = crate::Reg; +#[doc = "Message Buffer 6 WORD0 Register"] +pub mod mb_group_word06; +#[doc = "MB_64B_GROUP_MB1_64B_WORD7 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word7`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD7")] +pub type Mb64bGroupMb1_64bWord7 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word7; +#[doc = "MB_32B_GROUP_MB2_32B_WORD5 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD5")] +pub type Mb32bGroupMb2_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word5; +#[doc = "MB_16B_GROUP_MB4_16B_WORD1 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD1")] +pub type Mb16bGroupMb4_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_16B Register"] +pub mod mb_16b_group_mb4_16b_word1; +#[doc = "MB_8B_GROUP_MB6_8B_WORD1 (rw) register accessor: Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB6_8B_WORD1")] +pub type Mb8bGroupMb6_8bWord1 = crate::Reg; +#[doc = "Message Buffer 6 WORD_8B Register"] +pub mod mb_8b_group_mb6_8b_word1; +#[doc = "MB_GROUP_WORD16 (rw) register accessor: Message Buffer 6 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word16`] module"] +#[doc(alias = "MB_GROUP_WORD16")] +pub type MbGroupWord16 = crate::Reg; +#[doc = "Message Buffer 6 WORD1 Register"] +pub mod mb_group_word16; +#[doc = "MB_GROUP_CS7 (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs7`] module"] +#[doc(alias = "MB_GROUP_CS7")] +pub type MbGroupCs7 = crate::Reg; +#[doc = "Message Buffer 7 CS Register"] +pub mod mb_group_cs7; +#[doc = "MB_64B_GROUP_MB1_64B_WORD8 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word8`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD8")] +pub type Mb64bGroupMb1_64bWord8 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word8; +#[doc = "MB_32B_GROUP_MB2_32B_WORD6 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD6")] +pub type Mb32bGroupMb2_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word6; +#[doc = "MB_16B_GROUP_MB4_16B_WORD2 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD2")] +pub type Mb16bGroupMb4_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_16B Register"] +pub mod mb_16b_group_mb4_16b_word2; +#[doc = "MB_8B_GROUP_MB7_8B_CS (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB7_8B_CS")] +pub type Mb8bGroupMb7_8bCs = crate::Reg; +#[doc = "Message Buffer 7 CS Register"] +pub mod mb_8b_group_mb7_8b_cs; +#[doc = "MB_GROUP_ID7 (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id7`] module"] +#[doc(alias = "MB_GROUP_ID7")] +pub type MbGroupId7 = crate::Reg; +#[doc = "Message Buffer 7 ID Register"] +pub mod mb_group_id7; +#[doc = "MB_64B_GROUP_MB1_64B_WORD9 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word9`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD9")] +pub type Mb64bGroupMb1_64bWord9 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word9; +#[doc = "MB_32B_GROUP_MB2_32B_WORD7 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD7")] +pub type Mb32bGroupMb2_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_32B Register"] +pub mod mb_32b_group_mb2_32b_word7; +#[doc = "MB_16B_GROUP_MB4_16B_WORD3 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD3")] +pub type Mb16bGroupMb4_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_16B Register"] +pub mod mb_16b_group_mb4_16b_word3; +#[doc = "MB_8B_GROUP_MB7_8B_ID (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB7_8B_ID")] +pub type Mb8bGroupMb7_8bId = crate::Reg; +#[doc = "Message Buffer 7 ID Register"] +pub mod mb_8b_group_mb7_8b_id; +#[doc = "MB_64B_GROUP_MB1_64B_WORD10 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word10`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD10")] +pub type Mb64bGroupMb1_64bWord10 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word10; +#[doc = "MB_32B_GROUP_MB3_32B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_CS")] +pub type Mb32bGroupMb3_32bCs = crate::Reg; +#[doc = "Message Buffer 3 CS Register"] +pub mod mb_32b_group_mb3_32b_cs; +#[doc = "MB_16B_GROUP_MB5_16B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB5_16B_CS")] +pub type Mb16bGroupMb5_16bCs = crate::Reg; +#[doc = "Message Buffer 5 CS Register"] +pub mod mb_16b_group_mb5_16b_cs; +#[doc = "MB_8B_GROUP_MB7_8B_WORD0 (rw) register accessor: Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB7_8B_WORD0")] +pub type Mb8bGroupMb7_8bWord0 = crate::Reg; +#[doc = "Message Buffer 7 WORD_8B Register"] +pub mod mb_8b_group_mb7_8b_word0; +#[doc = "MB_GROUP_WORD07 (rw) register accessor: Message Buffer 7 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word07::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word07::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word07`] module"] +#[doc(alias = "MB_GROUP_WORD07")] +pub type MbGroupWord07 = crate::Reg; +#[doc = "Message Buffer 7 WORD0 Register"] +pub mod mb_group_word07; +#[doc = "MB_64B_GROUP_MB1_64B_WORD11 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word11`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD11")] +pub type Mb64bGroupMb1_64bWord11 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word11; +#[doc = "MB_32B_GROUP_MB3_32B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_ID")] +pub type Mb32bGroupMb3_32bId = crate::Reg; +#[doc = "Message Buffer 3 ID Register"] +pub mod mb_32b_group_mb3_32b_id; +#[doc = "MB_16B_GROUP_MB5_16B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB5_16B_ID")] +pub type Mb16bGroupMb5_16bId = crate::Reg; +#[doc = "Message Buffer 5 ID Register"] +pub mod mb_16b_group_mb5_16b_id; +#[doc = "MB_8B_GROUP_MB7_8B_WORD1 (rw) register accessor: Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB7_8B_WORD1")] +pub type Mb8bGroupMb7_8bWord1 = crate::Reg; +#[doc = "Message Buffer 7 WORD_8B Register"] +pub mod mb_8b_group_mb7_8b_word1; +#[doc = "MB_GROUP_WORD17 (rw) register accessor: Message Buffer 7 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word17`] module"] +#[doc(alias = "MB_GROUP_WORD17")] +pub type MbGroupWord17 = crate::Reg; +#[doc = "Message Buffer 7 WORD1 Register"] +pub mod mb_group_word17; +#[doc = "MB_GROUP_CS8 (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs8`] module"] +#[doc(alias = "MB_GROUP_CS8")] +pub type MbGroupCs8 = crate::Reg; +#[doc = "Message Buffer 8 CS Register"] +pub mod mb_group_cs8; +#[doc = "MB_64B_GROUP_MB1_64B_WORD12 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word12`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD12")] +pub type Mb64bGroupMb1_64bWord12 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word12; +#[doc = "MB_32B_GROUP_MB3_32B_WORD0 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD0")] +pub type Mb32bGroupMb3_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word0; +#[doc = "MB_16B_GROUP_MB5_16B_WORD0 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD0")] +pub type Mb16bGroupMb5_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_16B Register"] +pub mod mb_16b_group_mb5_16b_word0; +#[doc = "MB_8B_GROUP_MB8_8B_CS (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB8_8B_CS")] +pub type Mb8bGroupMb8_8bCs = crate::Reg; +#[doc = "Message Buffer 8 CS Register"] +pub mod mb_8b_group_mb8_8b_cs; +#[doc = "MB_GROUP_ID8 (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id8`] module"] +#[doc(alias = "MB_GROUP_ID8")] +pub type MbGroupId8 = crate::Reg; +#[doc = "Message Buffer 8 ID Register"] +pub mod mb_group_id8; +#[doc = "MB_64B_GROUP_MB1_64B_WORD13 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word13`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD13")] +pub type Mb64bGroupMb1_64bWord13 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word13; +#[doc = "MB_32B_GROUP_MB3_32B_WORD1 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD1")] +pub type Mb32bGroupMb3_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word1; +#[doc = "MB_16B_GROUP_MB5_16B_WORD1 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD1")] +pub type Mb16bGroupMb5_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_16B Register"] +pub mod mb_16b_group_mb5_16b_word1; +#[doc = "MB_8B_GROUP_MB8_8B_ID (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB8_8B_ID")] +pub type Mb8bGroupMb8_8bId = crate::Reg; +#[doc = "Message Buffer 8 ID Register"] +pub mod mb_8b_group_mb8_8b_id; +#[doc = "MB_64B_GROUP_MB1_64B_WORD14 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word14`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD14")] +pub type Mb64bGroupMb1_64bWord14 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word14; +#[doc = "MB_32B_GROUP_MB3_32B_WORD2 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD2")] +pub type Mb32bGroupMb3_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word2; +#[doc = "MB_16B_GROUP_MB5_16B_WORD2 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD2")] +pub type Mb16bGroupMb5_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_16B Register"] +pub mod mb_16b_group_mb5_16b_word2; +#[doc = "MB_8B_GROUP_MB8_8B_WORD0 (rw) register accessor: Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB8_8B_WORD0")] +pub type Mb8bGroupMb8_8bWord0 = crate::Reg; +#[doc = "Message Buffer 8 WORD_8B Register"] +pub mod mb_8b_group_mb8_8b_word0; +#[doc = "MB_GROUP_WORD08 (rw) register accessor: Message Buffer 8 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word08::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word08::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word08`] module"] +#[doc(alias = "MB_GROUP_WORD08")] +pub type MbGroupWord08 = crate::Reg; +#[doc = "Message Buffer 8 WORD0 Register"] +pub mod mb_group_word08; +#[doc = "MB_64B_GROUP_MB1_64B_WORD15 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word15`] module"] +#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD15")] +pub type Mb64bGroupMb1_64bWord15 = + crate::Reg; +#[doc = "Message Buffer 1 WORD_64B Register"] +pub mod mb_64b_group_mb1_64b_word15; +#[doc = "MB_32B_GROUP_MB3_32B_WORD3 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD3")] +pub type Mb32bGroupMb3_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word3; +#[doc = "MB_16B_GROUP_MB5_16B_WORD3 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD3")] +pub type Mb16bGroupMb5_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_16B Register"] +pub mod mb_16b_group_mb5_16b_word3; +#[doc = "MB_8B_GROUP_MB8_8B_WORD1 (rw) register accessor: Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB8_8B_WORD1")] +pub type Mb8bGroupMb8_8bWord1 = crate::Reg; +#[doc = "Message Buffer 8 WORD_8B Register"] +pub mod mb_8b_group_mb8_8b_word1; +#[doc = "MB_GROUP_WORD18 (rw) register accessor: Message Buffer 8 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word18`] module"] +#[doc(alias = "MB_GROUP_WORD18")] +pub type MbGroupWord18 = crate::Reg; +#[doc = "Message Buffer 8 WORD1 Register"] +pub mod mb_group_word18; +#[doc = "MB_GROUP_CS9 (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs9`] module"] +#[doc(alias = "MB_GROUP_CS9")] +pub type MbGroupCs9 = crate::Reg; +#[doc = "Message Buffer 9 CS Register"] +pub mod mb_group_cs9; +#[doc = "MB_64B_GROUP_MB2_64B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_cs`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_CS")] +pub type Mb64bGroupMb2_64bCs = crate::Reg; +#[doc = "Message Buffer 2 CS Register"] +pub mod mb_64b_group_mb2_64b_cs; +#[doc = "MB_32B_GROUP_MB3_32B_WORD4 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD4")] +pub type Mb32bGroupMb3_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word4; +#[doc = "MB_16B_GROUP_MB6_16B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB6_16B_CS")] +pub type Mb16bGroupMb6_16bCs = crate::Reg; +#[doc = "Message Buffer 6 CS Register"] +pub mod mb_16b_group_mb6_16b_cs; +#[doc = "MB_8B_GROUP_MB9_8B_CS (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB9_8B_CS")] +pub type Mb8bGroupMb9_8bCs = crate::Reg; +#[doc = "Message Buffer 9 CS Register"] +pub mod mb_8b_group_mb9_8b_cs; +#[doc = "MB_GROUP_ID9 (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id9`] module"] +#[doc(alias = "MB_GROUP_ID9")] +pub type MbGroupId9 = crate::Reg; +#[doc = "Message Buffer 9 ID Register"] +pub mod mb_group_id9; +#[doc = "MB_64B_GROUP_MB2_64B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_id`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_ID")] +pub type Mb64bGroupMb2_64bId = crate::Reg; +#[doc = "Message Buffer 2 ID Register"] +pub mod mb_64b_group_mb2_64b_id; +#[doc = "MB_32B_GROUP_MB3_32B_WORD5 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD5")] +pub type Mb32bGroupMb3_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word5; +#[doc = "MB_16B_GROUP_MB6_16B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB6_16B_ID")] +pub type Mb16bGroupMb6_16bId = crate::Reg; +#[doc = "Message Buffer 6 ID Register"] +pub mod mb_16b_group_mb6_16b_id; +#[doc = "MB_8B_GROUP_MB9_8B_ID (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB9_8B_ID")] +pub type Mb8bGroupMb9_8bId = crate::Reg; +#[doc = "Message Buffer 9 ID Register"] +pub mod mb_8b_group_mb9_8b_id; +#[doc = "MB_64B_GROUP_MB2_64B_WORD0 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word0`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD0")] +pub type Mb64bGroupMb2_64bWord0 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word0; +#[doc = "MB_32B_GROUP_MB3_32B_WORD6 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD6")] +pub type Mb32bGroupMb3_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word6; +#[doc = "MB_16B_GROUP_MB6_16B_WORD0 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD0")] +pub type Mb16bGroupMb6_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_16B Register"] +pub mod mb_16b_group_mb6_16b_word0; +#[doc = "MB_8B_GROUP_MB9_8B_WORD0 (rw) register accessor: Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB9_8B_WORD0")] +pub type Mb8bGroupMb9_8bWord0 = crate::Reg; +#[doc = "Message Buffer 9 WORD_8B Register"] +pub mod mb_8b_group_mb9_8b_word0; +#[doc = "MB_GROUP_WORD09 (rw) register accessor: Message Buffer 9 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word09::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word09::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word09`] module"] +#[doc(alias = "MB_GROUP_WORD09")] +pub type MbGroupWord09 = crate::Reg; +#[doc = "Message Buffer 9 WORD0 Register"] +pub mod mb_group_word09; +#[doc = "MB_64B_GROUP_MB2_64B_WORD1 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word1`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD1")] +pub type Mb64bGroupMb2_64bWord1 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word1; +#[doc = "MB_32B_GROUP_MB3_32B_WORD7 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD7")] +pub type Mb32bGroupMb3_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_32B Register"] +pub mod mb_32b_group_mb3_32b_word7; +#[doc = "MB_16B_GROUP_MB6_16B_WORD1 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD1")] +pub type Mb16bGroupMb6_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_16B Register"] +pub mod mb_16b_group_mb6_16b_word1; +#[doc = "MB_8B_GROUP_MB9_8B_WORD1 (rw) register accessor: Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB9_8B_WORD1")] +pub type Mb8bGroupMb9_8bWord1 = crate::Reg; +#[doc = "Message Buffer 9 WORD_8B Register"] +pub mod mb_8b_group_mb9_8b_word1; +#[doc = "MB_GROUP_WORD19 (rw) register accessor: Message Buffer 9 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word19`] module"] +#[doc(alias = "MB_GROUP_WORD19")] +pub type MbGroupWord19 = crate::Reg; +#[doc = "Message Buffer 9 WORD1 Register"] +pub mod mb_group_word19; +#[doc = "MB_GROUP_CS10 (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs10`] module"] +#[doc(alias = "MB_GROUP_CS10")] +pub type MbGroupCs10 = crate::Reg; +#[doc = "Message Buffer 10 CS Register"] +pub mod mb_group_cs10; +#[doc = "MB_8B_GROUP_MB10_8B_CS (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB10_8B_CS")] +pub type Mb8bGroupMb10_8bCs = crate::Reg; +#[doc = "Message Buffer 10 CS Register"] +pub mod mb_8b_group_mb10_8b_cs; +#[doc = "MB_64B_GROUP_MB2_64B_WORD2 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word2`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD2")] +pub type Mb64bGroupMb2_64bWord2 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word2; +#[doc = "MB_32B_GROUP_MB4_32B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_CS")] +pub type Mb32bGroupMb4_32bCs = crate::Reg; +#[doc = "Message Buffer 4 CS Register"] +pub mod mb_32b_group_mb4_32b_cs; +#[doc = "MB_16B_GROUP_MB6_16B_WORD2 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD2")] +pub type Mb16bGroupMb6_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_16B Register"] +pub mod mb_16b_group_mb6_16b_word2; +#[doc = "MB_GROUP_ID10 (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id10`] module"] +#[doc(alias = "MB_GROUP_ID10")] +pub type MbGroupId10 = crate::Reg; +#[doc = "Message Buffer 10 ID Register"] +pub mod mb_group_id10; +#[doc = "MB_8B_GROUP_MB10_8B_ID (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB10_8B_ID")] +pub type Mb8bGroupMb10_8bId = crate::Reg; +#[doc = "Message Buffer 10 ID Register"] +pub mod mb_8b_group_mb10_8b_id; +#[doc = "MB_64B_GROUP_MB2_64B_WORD3 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word3`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD3")] +pub type Mb64bGroupMb2_64bWord3 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word3; +#[doc = "MB_32B_GROUP_MB4_32B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_ID")] +pub type Mb32bGroupMb4_32bId = crate::Reg; +#[doc = "Message Buffer 4 ID Register"] +pub mod mb_32b_group_mb4_32b_id; +#[doc = "MB_16B_GROUP_MB6_16B_WORD3 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD3")] +pub type Mb16bGroupMb6_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_16B Register"] +pub mod mb_16b_group_mb6_16b_word3; +#[doc = "MB_8B_GROUP_MB10_8B_WORD0 (rw) register accessor: Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB10_8B_WORD0")] +pub type Mb8bGroupMb10_8bWord0 = crate::Reg; +#[doc = "Message Buffer 10 WORD_8B Register"] +pub mod mb_8b_group_mb10_8b_word0; +#[doc = "MB_64B_GROUP_MB2_64B_WORD4 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word4`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD4")] +pub type Mb64bGroupMb2_64bWord4 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word4; +#[doc = "MB_32B_GROUP_MB4_32B_WORD0 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD0")] +pub type Mb32bGroupMb4_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word0; +#[doc = "MB_16B_GROUP_MB7_16B_CS (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB7_16B_CS")] +pub type Mb16bGroupMb7_16bCs = crate::Reg; +#[doc = "Message Buffer 7 CS Register"] +pub mod mb_16b_group_mb7_16b_cs; +#[doc = "MB_GROUP_WORD010 (rw) register accessor: Message Buffer 10 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word010::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word010::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word010`] module"] +#[doc(alias = "MB_GROUP_WORD010")] +pub type MbGroupWord010 = crate::Reg; +#[doc = "Message Buffer 10 WORD0 Register"] +pub mod mb_group_word010; +#[doc = "MB_8B_GROUP_MB10_8B_WORD1 (rw) register accessor: Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB10_8B_WORD1")] +pub type Mb8bGroupMb10_8bWord1 = crate::Reg; +#[doc = "Message Buffer 10 WORD_8B Register"] +pub mod mb_8b_group_mb10_8b_word1; +#[doc = "MB_64B_GROUP_MB2_64B_WORD5 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word5`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD5")] +pub type Mb64bGroupMb2_64bWord5 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word5; +#[doc = "MB_32B_GROUP_MB4_32B_WORD1 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD1")] +pub type Mb32bGroupMb4_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word1; +#[doc = "MB_16B_GROUP_MB7_16B_ID (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB7_16B_ID")] +pub type Mb16bGroupMb7_16bId = crate::Reg; +#[doc = "Message Buffer 7 ID Register"] +pub mod mb_16b_group_mb7_16b_id; +#[doc = "MB_GROUP_WORD110 (rw) register accessor: Message Buffer 10 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word110::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word110::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word110`] module"] +#[doc(alias = "MB_GROUP_WORD110")] +pub type MbGroupWord110 = crate::Reg; +#[doc = "Message Buffer 10 WORD1 Register"] +pub mod mb_group_word110; +#[doc = "MB_GROUP_CS11 (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs11`] module"] +#[doc(alias = "MB_GROUP_CS11")] +pub type MbGroupCs11 = crate::Reg; +#[doc = "Message Buffer 11 CS Register"] +pub mod mb_group_cs11; +#[doc = "MB_8B_GROUP_MB11_8B_CS (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB11_8B_CS")] +pub type Mb8bGroupMb11_8bCs = crate::Reg; +#[doc = "Message Buffer 11 CS Register"] +pub mod mb_8b_group_mb11_8b_cs; +#[doc = "MB_64B_GROUP_MB2_64B_WORD6 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word6`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD6")] +pub type Mb64bGroupMb2_64bWord6 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word6; +#[doc = "MB_32B_GROUP_MB4_32B_WORD2 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD2")] +pub type Mb32bGroupMb4_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word2; +#[doc = "MB_16B_GROUP_MB7_16B_WORD0 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD0")] +pub type Mb16bGroupMb7_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_16B Register"] +pub mod mb_16b_group_mb7_16b_word0; +#[doc = "MB_GROUP_ID11 (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id11`] module"] +#[doc(alias = "MB_GROUP_ID11")] +pub type MbGroupId11 = crate::Reg; +#[doc = "Message Buffer 11 ID Register"] +pub mod mb_group_id11; +#[doc = "MB_8B_GROUP_MB11_8B_ID (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB11_8B_ID")] +pub type Mb8bGroupMb11_8bId = crate::Reg; +#[doc = "Message Buffer 11 ID Register"] +pub mod mb_8b_group_mb11_8b_id; +#[doc = "MB_64B_GROUP_MB2_64B_WORD7 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word7`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD7")] +pub type Mb64bGroupMb2_64bWord7 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word7; +#[doc = "MB_32B_GROUP_MB4_32B_WORD3 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD3")] +pub type Mb32bGroupMb4_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word3; +#[doc = "MB_16B_GROUP_MB7_16B_WORD1 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD1")] +pub type Mb16bGroupMb7_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_16B Register"] +pub mod mb_16b_group_mb7_16b_word1; +#[doc = "MB_8B_GROUP_MB11_8B_WORD0 (rw) register accessor: Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB11_8B_WORD0")] +pub type Mb8bGroupMb11_8bWord0 = crate::Reg; +#[doc = "Message Buffer 11 WORD_8B Register"] +pub mod mb_8b_group_mb11_8b_word0; +#[doc = "MB_64B_GROUP_MB2_64B_WORD8 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word8`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD8")] +pub type Mb64bGroupMb2_64bWord8 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word8; +#[doc = "MB_32B_GROUP_MB4_32B_WORD4 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD4")] +pub type Mb32bGroupMb4_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word4; +#[doc = "MB_16B_GROUP_MB7_16B_WORD2 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD2")] +pub type Mb16bGroupMb7_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_16B Register"] +pub mod mb_16b_group_mb7_16b_word2; +#[doc = "MB_GROUP_WORD011 (rw) register accessor: Message Buffer 11 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word011::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word011::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word011`] module"] +#[doc(alias = "MB_GROUP_WORD011")] +pub type MbGroupWord011 = crate::Reg; +#[doc = "Message Buffer 11 WORD0 Register"] +pub mod mb_group_word011; +#[doc = "MB_8B_GROUP_MB11_8B_WORD1 (rw) register accessor: Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB11_8B_WORD1")] +pub type Mb8bGroupMb11_8bWord1 = crate::Reg; +#[doc = "Message Buffer 11 WORD_8B Register"] +pub mod mb_8b_group_mb11_8b_word1; +#[doc = "MB_64B_GROUP_MB2_64B_WORD9 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word9`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD9")] +pub type Mb64bGroupMb2_64bWord9 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word9; +#[doc = "MB_32B_GROUP_MB4_32B_WORD5 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD5")] +pub type Mb32bGroupMb4_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word5; +#[doc = "MB_16B_GROUP_MB7_16B_WORD3 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD3")] +pub type Mb16bGroupMb7_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_16B Register"] +pub mod mb_16b_group_mb7_16b_word3; +#[doc = "MB_GROUP_WORD111 (rw) register accessor: Message Buffer 11 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word111::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word111::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word111`] module"] +#[doc(alias = "MB_GROUP_WORD111")] +pub type MbGroupWord111 = crate::Reg; +#[doc = "Message Buffer 11 WORD1 Register"] +pub mod mb_group_word111; +#[doc = "MB_GROUP_CS12 (rw) register accessor: Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs12`] module"] +#[doc(alias = "MB_GROUP_CS12")] +pub type MbGroupCs12 = crate::Reg; +#[doc = "Message Buffer 12 CS Register"] +pub mod mb_group_cs12; +#[doc = "MB_8B_GROUP_MB12_8B_CS (rw) register accessor: Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB12_8B_CS")] +pub type Mb8bGroupMb12_8bCs = crate::Reg; +#[doc = "Message Buffer 12 CS Register"] +pub mod mb_8b_group_mb12_8b_cs; +#[doc = "MB_64B_GROUP_MB2_64B_WORD10 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word10`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD10")] +pub type Mb64bGroupMb2_64bWord10 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word10; +#[doc = "MB_32B_GROUP_MB4_32B_WORD6 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD6")] +pub type Mb32bGroupMb4_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word6; +#[doc = "MB_16B_GROUP_MB8_16B_CS (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB8_16B_CS")] +pub type Mb16bGroupMb8_16bCs = crate::Reg; +#[doc = "Message Buffer 8 CS Register"] +pub mod mb_16b_group_mb8_16b_cs; +#[doc = "MB_GROUP_ID12 (rw) register accessor: Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id12`] module"] +#[doc(alias = "MB_GROUP_ID12")] +pub type MbGroupId12 = crate::Reg; +#[doc = "Message Buffer 12 ID Register"] +pub mod mb_group_id12; +#[doc = "MB_8B_GROUP_MB12_8B_ID (rw) register accessor: Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB12_8B_ID")] +pub type Mb8bGroupMb12_8bId = crate::Reg; +#[doc = "Message Buffer 12 ID Register"] +pub mod mb_8b_group_mb12_8b_id; +#[doc = "MB_64B_GROUP_MB2_64B_WORD11 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word11`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD11")] +pub type Mb64bGroupMb2_64bWord11 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word11; +#[doc = "MB_32B_GROUP_MB4_32B_WORD7 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD7")] +pub type Mb32bGroupMb4_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_32B Register"] +pub mod mb_32b_group_mb4_32b_word7; +#[doc = "MB_16B_GROUP_MB8_16B_ID (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB8_16B_ID")] +pub type Mb16bGroupMb8_16bId = crate::Reg; +#[doc = "Message Buffer 8 ID Register"] +pub mod mb_16b_group_mb8_16b_id; +#[doc = "MB_8B_GROUP_MB12_8B_WORD0 (rw) register accessor: Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB12_8B_WORD0")] +pub type Mb8bGroupMb12_8bWord0 = crate::Reg; +#[doc = "Message Buffer 12 WORD_8B Register"] +pub mod mb_8b_group_mb12_8b_word0; +#[doc = "MB_64B_GROUP_MB2_64B_WORD12 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word12`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD12")] +pub type Mb64bGroupMb2_64bWord12 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word12; +#[doc = "MB_32B_GROUP_MB5_32B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_CS")] +pub type Mb32bGroupMb5_32bCs = crate::Reg; +#[doc = "Message Buffer 5 CS Register"] +pub mod mb_32b_group_mb5_32b_cs; +#[doc = "MB_16B_GROUP_MB8_16B_WORD0 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD0")] +pub type Mb16bGroupMb8_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_16B Register"] +pub mod mb_16b_group_mb8_16b_word0; +#[doc = "MB_GROUP_WORD012 (rw) register accessor: Message Buffer 12 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word012::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word012::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word012`] module"] +#[doc(alias = "MB_GROUP_WORD012")] +pub type MbGroupWord012 = crate::Reg; +#[doc = "Message Buffer 12 WORD0 Register"] +pub mod mb_group_word012; +#[doc = "MB_8B_GROUP_MB12_8B_WORD1 (rw) register accessor: Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB12_8B_WORD1")] +pub type Mb8bGroupMb12_8bWord1 = crate::Reg; +#[doc = "Message Buffer 12 WORD_8B Register"] +pub mod mb_8b_group_mb12_8b_word1; +#[doc = "MB_64B_GROUP_MB2_64B_WORD13 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word13`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD13")] +pub type Mb64bGroupMb2_64bWord13 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word13; +#[doc = "MB_32B_GROUP_MB5_32B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_ID")] +pub type Mb32bGroupMb5_32bId = crate::Reg; +#[doc = "Message Buffer 5 ID Register"] +pub mod mb_32b_group_mb5_32b_id; +#[doc = "MB_16B_GROUP_MB8_16B_WORD1 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD1")] +pub type Mb16bGroupMb8_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_16B Register"] +pub mod mb_16b_group_mb8_16b_word1; +#[doc = "MB_GROUP_WORD112 (rw) register accessor: Message Buffer 12 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word112::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word112::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word112`] module"] +#[doc(alias = "MB_GROUP_WORD112")] +pub type MbGroupWord112 = crate::Reg; +#[doc = "Message Buffer 12 WORD1 Register"] +pub mod mb_group_word112; +#[doc = "MB_GROUP_CS13 (rw) register accessor: Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs13`] module"] +#[doc(alias = "MB_GROUP_CS13")] +pub type MbGroupCs13 = crate::Reg; +#[doc = "Message Buffer 13 CS Register"] +pub mod mb_group_cs13; +#[doc = "MB_8B_GROUP_MB13_8B_CS (rw) register accessor: Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB13_8B_CS")] +pub type Mb8bGroupMb13_8bCs = crate::Reg; +#[doc = "Message Buffer 13 CS Register"] +pub mod mb_8b_group_mb13_8b_cs; +#[doc = "MB_64B_GROUP_MB2_64B_WORD14 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word14`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD14")] +pub type Mb64bGroupMb2_64bWord14 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word14; +#[doc = "MB_32B_GROUP_MB5_32B_WORD0 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD0")] +pub type Mb32bGroupMb5_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word0; +#[doc = "MB_16B_GROUP_MB8_16B_WORD2 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD2")] +pub type Mb16bGroupMb8_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_16B Register"] +pub mod mb_16b_group_mb8_16b_word2; +#[doc = "MB_GROUP_ID13 (rw) register accessor: Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id13`] module"] +#[doc(alias = "MB_GROUP_ID13")] +pub type MbGroupId13 = crate::Reg; +#[doc = "Message Buffer 13 ID Register"] +pub mod mb_group_id13; +#[doc = "MB_8B_GROUP_MB13_8B_ID (rw) register accessor: Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB13_8B_ID")] +pub type Mb8bGroupMb13_8bId = crate::Reg; +#[doc = "Message Buffer 13 ID Register"] +pub mod mb_8b_group_mb13_8b_id; +#[doc = "MB_64B_GROUP_MB2_64B_WORD15 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word15`] module"] +#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD15")] +pub type Mb64bGroupMb2_64bWord15 = + crate::Reg; +#[doc = "Message Buffer 2 WORD_64B Register"] +pub mod mb_64b_group_mb2_64b_word15; +#[doc = "MB_32B_GROUP_MB5_32B_WORD1 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD1")] +pub type Mb32bGroupMb5_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word1; +#[doc = "MB_16B_GROUP_MB8_16B_WORD3 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD3")] +pub type Mb16bGroupMb8_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_16B Register"] +pub mod mb_16b_group_mb8_16b_word3; +#[doc = "MB_8B_GROUP_MB13_8B_WORD0 (rw) register accessor: Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB13_8B_WORD0")] +pub type Mb8bGroupMb13_8bWord0 = crate::Reg; +#[doc = "Message Buffer 13 WORD_8B Register"] +pub mod mb_8b_group_mb13_8b_word0; +#[doc = "MB_64B_GROUP_MB3_64B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_cs`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_CS")] +pub type Mb64bGroupMb3_64bCs = crate::Reg; +#[doc = "Message Buffer 3 CS Register"] +pub mod mb_64b_group_mb3_64b_cs; +#[doc = "MB_32B_GROUP_MB5_32B_WORD2 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD2")] +pub type Mb32bGroupMb5_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word2; +#[doc = "MB_16B_GROUP_MB9_16B_CS (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB9_16B_CS")] +pub type Mb16bGroupMb9_16bCs = crate::Reg; +#[doc = "Message Buffer 9 CS Register"] +pub mod mb_16b_group_mb9_16b_cs; +#[doc = "MB_GROUP_WORD013 (rw) register accessor: Message Buffer 13 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word013::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word013::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word013`] module"] +#[doc(alias = "MB_GROUP_WORD013")] +pub type MbGroupWord013 = crate::Reg; +#[doc = "Message Buffer 13 WORD0 Register"] +pub mod mb_group_word013; +#[doc = "MB_8B_GROUP_MB13_8B_WORD1 (rw) register accessor: Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB13_8B_WORD1")] +pub type Mb8bGroupMb13_8bWord1 = crate::Reg; +#[doc = "Message Buffer 13 WORD_8B Register"] +pub mod mb_8b_group_mb13_8b_word1; +#[doc = "MB_64B_GROUP_MB3_64B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_id`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_ID")] +pub type Mb64bGroupMb3_64bId = crate::Reg; +#[doc = "Message Buffer 3 ID Register"] +pub mod mb_64b_group_mb3_64b_id; +#[doc = "MB_32B_GROUP_MB5_32B_WORD3 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD3")] +pub type Mb32bGroupMb5_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word3; +#[doc = "MB_16B_GROUP_MB9_16B_ID (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB9_16B_ID")] +pub type Mb16bGroupMb9_16bId = crate::Reg; +#[doc = "Message Buffer 9 ID Register"] +pub mod mb_16b_group_mb9_16b_id; +#[doc = "MB_GROUP_WORD113 (rw) register accessor: Message Buffer 13 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word113::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word113::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word113`] module"] +#[doc(alias = "MB_GROUP_WORD113")] +pub type MbGroupWord113 = crate::Reg; +#[doc = "Message Buffer 13 WORD1 Register"] +pub mod mb_group_word113; +#[doc = "MB_GROUP_CS14 (rw) register accessor: Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs14`] module"] +#[doc(alias = "MB_GROUP_CS14")] +pub type MbGroupCs14 = crate::Reg; +#[doc = "Message Buffer 14 CS Register"] +pub mod mb_group_cs14; +#[doc = "MB_8B_GROUP_MB14_8B_CS (rw) register accessor: Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB14_8B_CS")] +pub type Mb8bGroupMb14_8bCs = crate::Reg; +#[doc = "Message Buffer 14 CS Register"] +pub mod mb_8b_group_mb14_8b_cs; +#[doc = "MB_64B_GROUP_MB3_64B_WORD0 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word0`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD0")] +pub type Mb64bGroupMb3_64bWord0 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word0; +#[doc = "MB_32B_GROUP_MB5_32B_WORD4 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD4")] +pub type Mb32bGroupMb5_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word4; +#[doc = "MB_16B_GROUP_MB9_16B_WORD0 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD0")] +pub type Mb16bGroupMb9_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_16B Register"] +pub mod mb_16b_group_mb9_16b_word0; +#[doc = "MB_GROUP_ID14 (rw) register accessor: Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id14`] module"] +#[doc(alias = "MB_GROUP_ID14")] +pub type MbGroupId14 = crate::Reg; +#[doc = "Message Buffer 14 ID Register"] +pub mod mb_group_id14; +#[doc = "MB_8B_GROUP_MB14_8B_ID (rw) register accessor: Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB14_8B_ID")] +pub type Mb8bGroupMb14_8bId = crate::Reg; +#[doc = "Message Buffer 14 ID Register"] +pub mod mb_8b_group_mb14_8b_id; +#[doc = "MB_64B_GROUP_MB3_64B_WORD1 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word1`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD1")] +pub type Mb64bGroupMb3_64bWord1 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word1; +#[doc = "MB_32B_GROUP_MB5_32B_WORD5 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD5")] +pub type Mb32bGroupMb5_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word5; +#[doc = "MB_16B_GROUP_MB9_16B_WORD1 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD1")] +pub type Mb16bGroupMb9_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_16B Register"] +pub mod mb_16b_group_mb9_16b_word1; +#[doc = "MB_8B_GROUP_MB14_8B_WORD0 (rw) register accessor: Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB14_8B_WORD0")] +pub type Mb8bGroupMb14_8bWord0 = crate::Reg; +#[doc = "Message Buffer 14 WORD_8B Register"] +pub mod mb_8b_group_mb14_8b_word0; +#[doc = "MB_64B_GROUP_MB3_64B_WORD2 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word2`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD2")] +pub type Mb64bGroupMb3_64bWord2 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word2; +#[doc = "MB_32B_GROUP_MB5_32B_WORD6 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD6")] +pub type Mb32bGroupMb5_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word6; +#[doc = "MB_16B_GROUP_MB9_16B_WORD2 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD2")] +pub type Mb16bGroupMb9_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_16B Register"] +pub mod mb_16b_group_mb9_16b_word2; +#[doc = "MB_GROUP_WORD014 (rw) register accessor: Message Buffer 14 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word014::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word014::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word014`] module"] +#[doc(alias = "MB_GROUP_WORD014")] +pub type MbGroupWord014 = crate::Reg; +#[doc = "Message Buffer 14 WORD0 Register"] +pub mod mb_group_word014; +#[doc = "MB_8B_GROUP_MB14_8B_WORD1 (rw) register accessor: Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB14_8B_WORD1")] +pub type Mb8bGroupMb14_8bWord1 = crate::Reg; +#[doc = "Message Buffer 14 WORD_8B Register"] +pub mod mb_8b_group_mb14_8b_word1; +#[doc = "MB_64B_GROUP_MB3_64B_WORD3 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word3`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD3")] +pub type Mb64bGroupMb3_64bWord3 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word3; +#[doc = "MB_32B_GROUP_MB5_32B_WORD7 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD7")] +pub type Mb32bGroupMb5_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_32B Register"] +pub mod mb_32b_group_mb5_32b_word7; +#[doc = "MB_16B_GROUP_MB9_16B_WORD3 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD3")] +pub type Mb16bGroupMb9_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_16B Register"] +pub mod mb_16b_group_mb9_16b_word3; +#[doc = "MB_GROUP_WORD114 (rw) register accessor: Message Buffer 14 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word114::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word114::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word114`] module"] +#[doc(alias = "MB_GROUP_WORD114")] +pub type MbGroupWord114 = crate::Reg; +#[doc = "Message Buffer 14 WORD1 Register"] +pub mod mb_group_word114; +#[doc = "MB_GROUP_CS15 (rw) register accessor: Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs15`] module"] +#[doc(alias = "MB_GROUP_CS15")] +pub type MbGroupCs15 = crate::Reg; +#[doc = "Message Buffer 15 CS Register"] +pub mod mb_group_cs15; +#[doc = "MB_16B_GROUP_MB10_16B_CS (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB10_16B_CS")] +pub type Mb16bGroupMb10_16bCs = crate::Reg; +#[doc = "Message Buffer 10 CS Register"] +pub mod mb_16b_group_mb10_16b_cs; +#[doc = "MB_8B_GROUP_MB15_8B_CS (rw) register accessor: Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB15_8B_CS")] +pub type Mb8bGroupMb15_8bCs = crate::Reg; +#[doc = "Message Buffer 15 CS Register"] +pub mod mb_8b_group_mb15_8b_cs; +#[doc = "MB_64B_GROUP_MB3_64B_WORD4 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word4`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD4")] +pub type Mb64bGroupMb3_64bWord4 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word4; +#[doc = "MB_32B_GROUP_MB6_32B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_CS")] +pub type Mb32bGroupMb6_32bCs = crate::Reg; +#[doc = "Message Buffer 6 CS Register"] +pub mod mb_32b_group_mb6_32b_cs; +#[doc = "MB_GROUP_ID15 (rw) register accessor: Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id15`] module"] +#[doc(alias = "MB_GROUP_ID15")] +pub type MbGroupId15 = crate::Reg; +#[doc = "Message Buffer 15 ID Register"] +pub mod mb_group_id15; +#[doc = "MB_16B_GROUP_MB10_16B_ID (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB10_16B_ID")] +pub type Mb16bGroupMb10_16bId = crate::Reg; +#[doc = "Message Buffer 10 ID Register"] +pub mod mb_16b_group_mb10_16b_id; +#[doc = "MB_8B_GROUP_MB15_8B_ID (rw) register accessor: Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB15_8B_ID")] +pub type Mb8bGroupMb15_8bId = crate::Reg; +#[doc = "Message Buffer 15 ID Register"] +pub mod mb_8b_group_mb15_8b_id; +#[doc = "MB_64B_GROUP_MB3_64B_WORD5 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word5`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD5")] +pub type Mb64bGroupMb3_64bWord5 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word5; +#[doc = "MB_32B_GROUP_MB6_32B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_ID")] +pub type Mb32bGroupMb6_32bId = crate::Reg; +#[doc = "Message Buffer 6 ID Register"] +pub mod mb_32b_group_mb6_32b_id; +#[doc = "MB_16B_GROUP_MB10_16B_WORD0 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD0")] +pub type Mb16bGroupMb10_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_16B Register"] +pub mod mb_16b_group_mb10_16b_word0; +#[doc = "MB_8B_GROUP_MB15_8B_WORD0 (rw) register accessor: Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB15_8B_WORD0")] +pub type Mb8bGroupMb15_8bWord0 = crate::Reg; +#[doc = "Message Buffer 15 WORD_8B Register"] +pub mod mb_8b_group_mb15_8b_word0; +#[doc = "MB_64B_GROUP_MB3_64B_WORD6 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word6`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD6")] +pub type Mb64bGroupMb3_64bWord6 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word6; +#[doc = "MB_32B_GROUP_MB6_32B_WORD0 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD0")] +pub type Mb32bGroupMb6_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word0; +#[doc = "MB_GROUP_WORD015 (rw) register accessor: Message Buffer 15 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word015::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word015::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word015`] module"] +#[doc(alias = "MB_GROUP_WORD015")] +pub type MbGroupWord015 = crate::Reg; +#[doc = "Message Buffer 15 WORD0 Register"] +pub mod mb_group_word015; +#[doc = "MB_16B_GROUP_MB10_16B_WORD1 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD1")] +pub type Mb16bGroupMb10_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_16B Register"] +pub mod mb_16b_group_mb10_16b_word1; +#[doc = "MB_8B_GROUP_MB15_8B_WORD1 (rw) register accessor: Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB15_8B_WORD1")] +pub type Mb8bGroupMb15_8bWord1 = crate::Reg; +#[doc = "Message Buffer 15 WORD_8B Register"] +pub mod mb_8b_group_mb15_8b_word1; +#[doc = "MB_64B_GROUP_MB3_64B_WORD7 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word7`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD7")] +pub type Mb64bGroupMb3_64bWord7 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word7; +#[doc = "MB_32B_GROUP_MB6_32B_WORD1 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD1")] +pub type Mb32bGroupMb6_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word1; +#[doc = "MB_GROUP_WORD115 (rw) register accessor: Message Buffer 15 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word115::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word115::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word115`] module"] +#[doc(alias = "MB_GROUP_WORD115")] +pub type MbGroupWord115 = crate::Reg; +#[doc = "Message Buffer 15 WORD1 Register"] +pub mod mb_group_word115; +#[doc = "MB_GROUP_CS16 (rw) register accessor: Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs16`] module"] +#[doc(alias = "MB_GROUP_CS16")] +pub type MbGroupCs16 = crate::Reg; +#[doc = "Message Buffer 16 CS Register"] +pub mod mb_group_cs16; +#[doc = "MB_16B_GROUP_MB10_16B_WORD2 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD2")] +pub type Mb16bGroupMb10_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_16B Register"] +pub mod mb_16b_group_mb10_16b_word2; +#[doc = "MB_8B_GROUP_MB16_8B_CS (rw) register accessor: Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB16_8B_CS")] +pub type Mb8bGroupMb16_8bCs = crate::Reg; +#[doc = "Message Buffer 16 CS Register"] +pub mod mb_8b_group_mb16_8b_cs; +#[doc = "MB_64B_GROUP_MB3_64B_WORD8 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word8`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD8")] +pub type Mb64bGroupMb3_64bWord8 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word8; +#[doc = "MB_32B_GROUP_MB6_32B_WORD2 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD2")] +pub type Mb32bGroupMb6_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word2; +#[doc = "MB_GROUP_ID16 (rw) register accessor: Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id16`] module"] +#[doc(alias = "MB_GROUP_ID16")] +pub type MbGroupId16 = crate::Reg; +#[doc = "Message Buffer 16 ID Register"] +pub mod mb_group_id16; +#[doc = "MB_16B_GROUP_MB10_16B_WORD3 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD3")] +pub type Mb16bGroupMb10_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_16B Register"] +pub mod mb_16b_group_mb10_16b_word3; +#[doc = "MB_8B_GROUP_MB16_8B_ID (rw) register accessor: Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB16_8B_ID")] +pub type Mb8bGroupMb16_8bId = crate::Reg; +#[doc = "Message Buffer 16 ID Register"] +pub mod mb_8b_group_mb16_8b_id; +#[doc = "MB_64B_GROUP_MB3_64B_WORD9 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word9`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD9")] +pub type Mb64bGroupMb3_64bWord9 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word9; +#[doc = "MB_32B_GROUP_MB6_32B_WORD3 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD3")] +pub type Mb32bGroupMb6_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word3; +#[doc = "MB_16B_GROUP_MB11_16B_CS (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB11_16B_CS")] +pub type Mb16bGroupMb11_16bCs = crate::Reg; +#[doc = "Message Buffer 11 CS Register"] +pub mod mb_16b_group_mb11_16b_cs; +#[doc = "MB_8B_GROUP_MB16_8B_WORD0 (rw) register accessor: Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB16_8B_WORD0")] +pub type Mb8bGroupMb16_8bWord0 = crate::Reg; +#[doc = "Message Buffer 16 WORD_8B Register"] +pub mod mb_8b_group_mb16_8b_word0; +#[doc = "MB_64B_GROUP_MB3_64B_WORD10 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word10`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD10")] +pub type Mb64bGroupMb3_64bWord10 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word10; +#[doc = "MB_32B_GROUP_MB6_32B_WORD4 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD4")] +pub type Mb32bGroupMb6_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word4; +#[doc = "MB_GROUP_WORD016 (rw) register accessor: Message Buffer 16 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word016::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word016::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word016`] module"] +#[doc(alias = "MB_GROUP_WORD016")] +pub type MbGroupWord016 = crate::Reg; +#[doc = "Message Buffer 16 WORD0 Register"] +pub mod mb_group_word016; +#[doc = "MB_16B_GROUP_MB11_16B_ID (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB11_16B_ID")] +pub type Mb16bGroupMb11_16bId = crate::Reg; +#[doc = "Message Buffer 11 ID Register"] +pub mod mb_16b_group_mb11_16b_id; +#[doc = "MB_8B_GROUP_MB16_8B_WORD1 (rw) register accessor: Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB16_8B_WORD1")] +pub type Mb8bGroupMb16_8bWord1 = crate::Reg; +#[doc = "Message Buffer 16 WORD_8B Register"] +pub mod mb_8b_group_mb16_8b_word1; +#[doc = "MB_64B_GROUP_MB3_64B_WORD11 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word11`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD11")] +pub type Mb64bGroupMb3_64bWord11 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word11; +#[doc = "MB_32B_GROUP_MB6_32B_WORD5 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD5")] +pub type Mb32bGroupMb6_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word5; +#[doc = "MB_GROUP_WORD116 (rw) register accessor: Message Buffer 16 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word116::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word116::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word116`] module"] +#[doc(alias = "MB_GROUP_WORD116")] +pub type MbGroupWord116 = crate::Reg; +#[doc = "Message Buffer 16 WORD1 Register"] +pub mod mb_group_word116; +#[doc = "MB_GROUP_CS17 (rw) register accessor: Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs17`] module"] +#[doc(alias = "MB_GROUP_CS17")] +pub type MbGroupCs17 = crate::Reg; +#[doc = "Message Buffer 17 CS Register"] +pub mod mb_group_cs17; +#[doc = "MB_16B_GROUP_MB11_16B_WORD0 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD0")] +pub type Mb16bGroupMb11_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_16B Register"] +pub mod mb_16b_group_mb11_16b_word0; +#[doc = "MB_8B_GROUP_MB17_8B_CS (rw) register accessor: Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB17_8B_CS")] +pub type Mb8bGroupMb17_8bCs = crate::Reg; +#[doc = "Message Buffer 17 CS Register"] +pub mod mb_8b_group_mb17_8b_cs; +#[doc = "MB_64B_GROUP_MB3_64B_WORD12 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word12`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD12")] +pub type Mb64bGroupMb3_64bWord12 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word12; +#[doc = "MB_32B_GROUP_MB6_32B_WORD6 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD6")] +pub type Mb32bGroupMb6_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word6; +#[doc = "MB_GROUP_ID17 (rw) register accessor: Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id17`] module"] +#[doc(alias = "MB_GROUP_ID17")] +pub type MbGroupId17 = crate::Reg; +#[doc = "Message Buffer 17 ID Register"] +pub mod mb_group_id17; +#[doc = "MB_16B_GROUP_MB11_16B_WORD1 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD1")] +pub type Mb16bGroupMb11_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_16B Register"] +pub mod mb_16b_group_mb11_16b_word1; +#[doc = "MB_8B_GROUP_MB17_8B_ID (rw) register accessor: Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB17_8B_ID")] +pub type Mb8bGroupMb17_8bId = crate::Reg; +#[doc = "Message Buffer 17 ID Register"] +pub mod mb_8b_group_mb17_8b_id; +#[doc = "MB_64B_GROUP_MB3_64B_WORD13 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word13`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD13")] +pub type Mb64bGroupMb3_64bWord13 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word13; +#[doc = "MB_32B_GROUP_MB6_32B_WORD7 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD7")] +pub type Mb32bGroupMb6_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_32B Register"] +pub mod mb_32b_group_mb6_32b_word7; +#[doc = "MB_16B_GROUP_MB11_16B_WORD2 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD2")] +pub type Mb16bGroupMb11_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_16B Register"] +pub mod mb_16b_group_mb11_16b_word2; +#[doc = "MB_8B_GROUP_MB17_8B_WORD0 (rw) register accessor: Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB17_8B_WORD0")] +pub type Mb8bGroupMb17_8bWord0 = crate::Reg; +#[doc = "Message Buffer 17 WORD_8B Register"] +pub mod mb_8b_group_mb17_8b_word0; +#[doc = "MB_64B_GROUP_MB3_64B_WORD14 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word14`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD14")] +pub type Mb64bGroupMb3_64bWord14 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word14; +#[doc = "MB_32B_GROUP_MB7_32B_CS (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_CS")] +pub type Mb32bGroupMb7_32bCs = crate::Reg; +#[doc = "Message Buffer 7 CS Register"] +pub mod mb_32b_group_mb7_32b_cs; +#[doc = "MB_GROUP_WORD017 (rw) register accessor: Message Buffer 17 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word017::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word017::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word017`] module"] +#[doc(alias = "MB_GROUP_WORD017")] +pub type MbGroupWord017 = crate::Reg; +#[doc = "Message Buffer 17 WORD0 Register"] +pub mod mb_group_word017; +#[doc = "MB_16B_GROUP_MB11_16B_WORD3 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD3")] +pub type Mb16bGroupMb11_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_16B Register"] +pub mod mb_16b_group_mb11_16b_word3; +#[doc = "MB_8B_GROUP_MB17_8B_WORD1 (rw) register accessor: Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB17_8B_WORD1")] +pub type Mb8bGroupMb17_8bWord1 = crate::Reg; +#[doc = "Message Buffer 17 WORD_8B Register"] +pub mod mb_8b_group_mb17_8b_word1; +#[doc = "MB_64B_GROUP_MB3_64B_WORD15 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word15`] module"] +#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD15")] +pub type Mb64bGroupMb3_64bWord15 = + crate::Reg; +#[doc = "Message Buffer 3 WORD_64B Register"] +pub mod mb_64b_group_mb3_64b_word15; +#[doc = "MB_32B_GROUP_MB7_32B_ID (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_ID")] +pub type Mb32bGroupMb7_32bId = crate::Reg; +#[doc = "Message Buffer 7 ID Register"] +pub mod mb_32b_group_mb7_32b_id; +#[doc = "MB_GROUP_WORD117 (rw) register accessor: Message Buffer 17 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word117::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word117::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word117`] module"] +#[doc(alias = "MB_GROUP_WORD117")] +pub type MbGroupWord117 = crate::Reg; +#[doc = "Message Buffer 17 WORD1 Register"] +pub mod mb_group_word117; +#[doc = "MB_GROUP_CS18 (rw) register accessor: Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs18`] module"] +#[doc(alias = "MB_GROUP_CS18")] +pub type MbGroupCs18 = crate::Reg; +#[doc = "Message Buffer 18 CS Register"] +pub mod mb_group_cs18; +#[doc = "MB_16B_GROUP_MB12_16B_CS (rw) register accessor: Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB12_16B_CS")] +pub type Mb16bGroupMb12_16bCs = crate::Reg; +#[doc = "Message Buffer 12 CS Register"] +pub mod mb_16b_group_mb12_16b_cs; +#[doc = "MB_8B_GROUP_MB18_8B_CS (rw) register accessor: Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB18_8B_CS")] +pub type Mb8bGroupMb18_8bCs = crate::Reg; +#[doc = "Message Buffer 18 CS Register"] +pub mod mb_8b_group_mb18_8b_cs; +#[doc = "MB_64B_GROUP_MB4_64B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_cs`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_CS")] +pub type Mb64bGroupMb4_64bCs = crate::Reg; +#[doc = "Message Buffer 4 CS Register"] +pub mod mb_64b_group_mb4_64b_cs; +#[doc = "MB_32B_GROUP_MB7_32B_WORD0 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD0")] +pub type Mb32bGroupMb7_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word0; +#[doc = "MB_GROUP_ID18 (rw) register accessor: Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id18`] module"] +#[doc(alias = "MB_GROUP_ID18")] +pub type MbGroupId18 = crate::Reg; +#[doc = "Message Buffer 18 ID Register"] +pub mod mb_group_id18; +#[doc = "MB_16B_GROUP_MB12_16B_ID (rw) register accessor: Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB12_16B_ID")] +pub type Mb16bGroupMb12_16bId = crate::Reg; +#[doc = "Message Buffer 12 ID Register"] +pub mod mb_16b_group_mb12_16b_id; +#[doc = "MB_8B_GROUP_MB18_8B_ID (rw) register accessor: Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB18_8B_ID")] +pub type Mb8bGroupMb18_8bId = crate::Reg; +#[doc = "Message Buffer 18 ID Register"] +pub mod mb_8b_group_mb18_8b_id; +#[doc = "MB_64B_GROUP_MB4_64B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_id`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_ID")] +pub type Mb64bGroupMb4_64bId = crate::Reg; +#[doc = "Message Buffer 4 ID Register"] +pub mod mb_64b_group_mb4_64b_id; +#[doc = "MB_32B_GROUP_MB7_32B_WORD1 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD1")] +pub type Mb32bGroupMb7_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word1; +#[doc = "MB_16B_GROUP_MB12_16B_WORD0 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD0")] +pub type Mb16bGroupMb12_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 12 WORD_16B Register"] +pub mod mb_16b_group_mb12_16b_word0; +#[doc = "MB_8B_GROUP_MB18_8B_WORD0 (rw) register accessor: Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB18_8B_WORD0")] +pub type Mb8bGroupMb18_8bWord0 = crate::Reg; +#[doc = "Message Buffer 18 WORD_8B Register"] +pub mod mb_8b_group_mb18_8b_word0; +#[doc = "MB_64B_GROUP_MB4_64B_WORD0 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word0`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD0")] +pub type Mb64bGroupMb4_64bWord0 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word0; +#[doc = "MB_32B_GROUP_MB7_32B_WORD2 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD2")] +pub type Mb32bGroupMb7_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word2; +#[doc = "MB_GROUP_WORD018 (rw) register accessor: Message Buffer 18 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word018::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word018::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word018`] module"] +#[doc(alias = "MB_GROUP_WORD018")] +pub type MbGroupWord018 = crate::Reg; +#[doc = "Message Buffer 18 WORD0 Register"] +pub mod mb_group_word018; +#[doc = "MB_16B_GROUP_MB12_16B_WORD1 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD1")] +pub type Mb16bGroupMb12_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 12 WORD_16B Register"] +pub mod mb_16b_group_mb12_16b_word1; +#[doc = "MB_8B_GROUP_MB18_8B_WORD1 (rw) register accessor: Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB18_8B_WORD1")] +pub type Mb8bGroupMb18_8bWord1 = crate::Reg; +#[doc = "Message Buffer 18 WORD_8B Register"] +pub mod mb_8b_group_mb18_8b_word1; +#[doc = "MB_64B_GROUP_MB4_64B_WORD1 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word1`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD1")] +pub type Mb64bGroupMb4_64bWord1 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word1; +#[doc = "MB_32B_GROUP_MB7_32B_WORD3 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD3")] +pub type Mb32bGroupMb7_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word3; +#[doc = "MB_GROUP_WORD118 (rw) register accessor: Message Buffer 18 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word118::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word118::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word118`] module"] +#[doc(alias = "MB_GROUP_WORD118")] +pub type MbGroupWord118 = crate::Reg; +#[doc = "Message Buffer 18 WORD1 Register"] +pub mod mb_group_word118; +#[doc = "MB_GROUP_CS19 (rw) register accessor: Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs19`] module"] +#[doc(alias = "MB_GROUP_CS19")] +pub type MbGroupCs19 = crate::Reg; +#[doc = "Message Buffer 19 CS Register"] +pub mod mb_group_cs19; +#[doc = "MB_16B_GROUP_MB12_16B_WORD2 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD2")] +pub type Mb16bGroupMb12_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 12 WORD_16B Register"] +pub mod mb_16b_group_mb12_16b_word2; +#[doc = "MB_8B_GROUP_MB19_8B_CS (rw) register accessor: Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB19_8B_CS")] +pub type Mb8bGroupMb19_8bCs = crate::Reg; +#[doc = "Message Buffer 19 CS Register"] +pub mod mb_8b_group_mb19_8b_cs; +#[doc = "MB_64B_GROUP_MB4_64B_WORD2 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word2`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD2")] +pub type Mb64bGroupMb4_64bWord2 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word2; +#[doc = "MB_32B_GROUP_MB7_32B_WORD4 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD4")] +pub type Mb32bGroupMb7_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word4; +#[doc = "MB_GROUP_ID19 (rw) register accessor: Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id19`] module"] +#[doc(alias = "MB_GROUP_ID19")] +pub type MbGroupId19 = crate::Reg; +#[doc = "Message Buffer 19 ID Register"] +pub mod mb_group_id19; +#[doc = "MB_16B_GROUP_MB12_16B_WORD3 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD3")] +pub type Mb16bGroupMb12_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 12 WORD_16B Register"] +pub mod mb_16b_group_mb12_16b_word3; +#[doc = "MB_8B_GROUP_MB19_8B_ID (rw) register accessor: Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB19_8B_ID")] +pub type Mb8bGroupMb19_8bId = crate::Reg; +#[doc = "Message Buffer 19 ID Register"] +pub mod mb_8b_group_mb19_8b_id; +#[doc = "MB_64B_GROUP_MB4_64B_WORD3 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word3`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD3")] +pub type Mb64bGroupMb4_64bWord3 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word3; +#[doc = "MB_32B_GROUP_MB7_32B_WORD5 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD5")] +pub type Mb32bGroupMb7_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word5; +#[doc = "MB_16B_GROUP_MB13_16B_CS (rw) register accessor: Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB13_16B_CS")] +pub type Mb16bGroupMb13_16bCs = crate::Reg; +#[doc = "Message Buffer 13 CS Register"] +pub mod mb_16b_group_mb13_16b_cs; +#[doc = "MB_8B_GROUP_MB19_8B_WORD0 (rw) register accessor: Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB19_8B_WORD0")] +pub type Mb8bGroupMb19_8bWord0 = crate::Reg; +#[doc = "Message Buffer 19 WORD_8B Register"] +pub mod mb_8b_group_mb19_8b_word0; +#[doc = "MB_64B_GROUP_MB4_64B_WORD4 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word4`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD4")] +pub type Mb64bGroupMb4_64bWord4 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word4; +#[doc = "MB_32B_GROUP_MB7_32B_WORD6 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD6")] +pub type Mb32bGroupMb7_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word6; +#[doc = "MB_GROUP_WORD019 (rw) register accessor: Message Buffer 19 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word019::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word019::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word019`] module"] +#[doc(alias = "MB_GROUP_WORD019")] +pub type MbGroupWord019 = crate::Reg; +#[doc = "Message Buffer 19 WORD0 Register"] +pub mod mb_group_word019; +#[doc = "MB_16B_GROUP_MB13_16B_ID (rw) register accessor: Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB13_16B_ID")] +pub type Mb16bGroupMb13_16bId = crate::Reg; +#[doc = "Message Buffer 13 ID Register"] +pub mod mb_16b_group_mb13_16b_id; +#[doc = "MB_8B_GROUP_MB19_8B_WORD1 (rw) register accessor: Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB19_8B_WORD1")] +pub type Mb8bGroupMb19_8bWord1 = crate::Reg; +#[doc = "Message Buffer 19 WORD_8B Register"] +pub mod mb_8b_group_mb19_8b_word1; +#[doc = "MB_64B_GROUP_MB4_64B_WORD5 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word5`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD5")] +pub type Mb64bGroupMb4_64bWord5 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word5; +#[doc = "MB_32B_GROUP_MB7_32B_WORD7 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD7")] +pub type Mb32bGroupMb7_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 7 WORD_32B Register"] +pub mod mb_32b_group_mb7_32b_word7; +#[doc = "MB_GROUP_WORD119 (rw) register accessor: Message Buffer 19 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word119::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word119::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word119`] module"] +#[doc(alias = "MB_GROUP_WORD119")] +pub type MbGroupWord119 = crate::Reg; +#[doc = "Message Buffer 19 WORD1 Register"] +pub mod mb_group_word119; +#[doc = "MB_GROUP_CS20 (rw) register accessor: Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs20`] module"] +#[doc(alias = "MB_GROUP_CS20")] +pub type MbGroupCs20 = crate::Reg; +#[doc = "Message Buffer 20 CS Register"] +pub mod mb_group_cs20; +#[doc = "MB_16B_GROUP_MB13_16B_WORD0 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD0")] +pub type Mb16bGroupMb13_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 13 WORD_16B Register"] +pub mod mb_16b_group_mb13_16b_word0; +#[doc = "MB_8B_GROUP_MB20_8B_CS (rw) register accessor: Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB20_8B_CS")] +pub type Mb8bGroupMb20_8bCs = crate::Reg; +#[doc = "Message Buffer 20 CS Register"] +pub mod mb_8b_group_mb20_8b_cs; +#[doc = "MB_64B_GROUP_MB4_64B_WORD6 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word6`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD6")] +pub type Mb64bGroupMb4_64bWord6 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word6; +#[doc = "MB_32B_GROUP_MB8_32B_CS (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_CS")] +pub type Mb32bGroupMb8_32bCs = crate::Reg; +#[doc = "Message Buffer 8 CS Register"] +pub mod mb_32b_group_mb8_32b_cs; +#[doc = "MB_GROUP_ID20 (rw) register accessor: Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id20`] module"] +#[doc(alias = "MB_GROUP_ID20")] +pub type MbGroupId20 = crate::Reg; +#[doc = "Message Buffer 20 ID Register"] +pub mod mb_group_id20; +#[doc = "MB_16B_GROUP_MB13_16B_WORD1 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD1")] +pub type Mb16bGroupMb13_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 13 WORD_16B Register"] +pub mod mb_16b_group_mb13_16b_word1; +#[doc = "MB_8B_GROUP_MB20_8B_ID (rw) register accessor: Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB20_8B_ID")] +pub type Mb8bGroupMb20_8bId = crate::Reg; +#[doc = "Message Buffer 20 ID Register"] +pub mod mb_8b_group_mb20_8b_id; +#[doc = "MB_64B_GROUP_MB4_64B_WORD7 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word7`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD7")] +pub type Mb64bGroupMb4_64bWord7 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word7; +#[doc = "MB_32B_GROUP_MB8_32B_ID (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_ID")] +pub type Mb32bGroupMb8_32bId = crate::Reg; +#[doc = "Message Buffer 8 ID Register"] +pub mod mb_32b_group_mb8_32b_id; +#[doc = "MB_16B_GROUP_MB13_16B_WORD2 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD2")] +pub type Mb16bGroupMb13_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 13 WORD_16B Register"] +pub mod mb_16b_group_mb13_16b_word2; +#[doc = "MB_8B_GROUP_MB20_8B_WORD0 (rw) register accessor: Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB20_8B_WORD0")] +pub type Mb8bGroupMb20_8bWord0 = crate::Reg; +#[doc = "Message Buffer 20 WORD_8B Register"] +pub mod mb_8b_group_mb20_8b_word0; +#[doc = "MB_64B_GROUP_MB4_64B_WORD8 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word8`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD8")] +pub type Mb64bGroupMb4_64bWord8 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word8; +#[doc = "MB_32B_GROUP_MB8_32B_WORD0 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD0")] +pub type Mb32bGroupMb8_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word0; +#[doc = "MB_GROUP_WORD020 (rw) register accessor: Message Buffer 20 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word020::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word020::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word020`] module"] +#[doc(alias = "MB_GROUP_WORD020")] +pub type MbGroupWord020 = crate::Reg; +#[doc = "Message Buffer 20 WORD0 Register"] +pub mod mb_group_word020; +#[doc = "MB_16B_GROUP_MB13_16B_WORD3 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD3")] +pub type Mb16bGroupMb13_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 13 WORD_16B Register"] +pub mod mb_16b_group_mb13_16b_word3; +#[doc = "MB_8B_GROUP_MB20_8B_WORD1 (rw) register accessor: Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB20_8B_WORD1")] +pub type Mb8bGroupMb20_8bWord1 = crate::Reg; +#[doc = "Message Buffer 20 WORD_8B Register"] +pub mod mb_8b_group_mb20_8b_word1; +#[doc = "MB_64B_GROUP_MB4_64B_WORD9 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word9`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD9")] +pub type Mb64bGroupMb4_64bWord9 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word9; +#[doc = "MB_32B_GROUP_MB8_32B_WORD1 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD1")] +pub type Mb32bGroupMb8_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word1; +#[doc = "MB_GROUP_WORD120 (rw) register accessor: Message Buffer 20 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word120::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word120::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word120`] module"] +#[doc(alias = "MB_GROUP_WORD120")] +pub type MbGroupWord120 = crate::Reg; +#[doc = "Message Buffer 20 WORD1 Register"] +pub mod mb_group_word120; +#[doc = "MB_GROUP_CS21 (rw) register accessor: Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs21`] module"] +#[doc(alias = "MB_GROUP_CS21")] +pub type MbGroupCs21 = crate::Reg; +#[doc = "Message Buffer 21 CS Register"] +pub mod mb_group_cs21; +#[doc = "MB_16B_GROUP_MB14_16B_CS (rw) register accessor: Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB14_16B_CS")] +pub type Mb16bGroupMb14_16bCs = crate::Reg; +#[doc = "Message Buffer 14 CS Register"] +pub mod mb_16b_group_mb14_16b_cs; +#[doc = "MB_8B_GROUP_MB21_8B_CS (rw) register accessor: Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB21_8B_CS")] +pub type Mb8bGroupMb21_8bCs = crate::Reg; +#[doc = "Message Buffer 21 CS Register"] +pub mod mb_8b_group_mb21_8b_cs; +#[doc = "MB_64B_GROUP_MB4_64B_WORD10 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word10`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD10")] +pub type Mb64bGroupMb4_64bWord10 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word10; +#[doc = "MB_32B_GROUP_MB8_32B_WORD2 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD2")] +pub type Mb32bGroupMb8_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word2; +#[doc = "MB_GROUP_ID21 (rw) register accessor: Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id21`] module"] +#[doc(alias = "MB_GROUP_ID21")] +pub type MbGroupId21 = crate::Reg; +#[doc = "Message Buffer 21 ID Register"] +pub mod mb_group_id21; +#[doc = "MB_16B_GROUP_MB14_16B_ID (rw) register accessor: Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB14_16B_ID")] +pub type Mb16bGroupMb14_16bId = crate::Reg; +#[doc = "Message Buffer 14 ID Register"] +pub mod mb_16b_group_mb14_16b_id; +#[doc = "MB_8B_GROUP_MB21_8B_ID (rw) register accessor: Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB21_8B_ID")] +pub type Mb8bGroupMb21_8bId = crate::Reg; +#[doc = "Message Buffer 21 ID Register"] +pub mod mb_8b_group_mb21_8b_id; +#[doc = "MB_64B_GROUP_MB4_64B_WORD11 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word11`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD11")] +pub type Mb64bGroupMb4_64bWord11 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word11; +#[doc = "MB_32B_GROUP_MB8_32B_WORD3 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD3")] +pub type Mb32bGroupMb8_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word3; +#[doc = "MB_16B_GROUP_MB14_16B_WORD0 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD0")] +pub type Mb16bGroupMb14_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 14 WORD_16B Register"] +pub mod mb_16b_group_mb14_16b_word0; +#[doc = "MB_8B_GROUP_MB21_8B_WORD0 (rw) register accessor: Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB21_8B_WORD0")] +pub type Mb8bGroupMb21_8bWord0 = crate::Reg; +#[doc = "Message Buffer 21 WORD_8B Register"] +pub mod mb_8b_group_mb21_8b_word0; +#[doc = "MB_64B_GROUP_MB4_64B_WORD12 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word12`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD12")] +pub type Mb64bGroupMb4_64bWord12 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word12; +#[doc = "MB_32B_GROUP_MB8_32B_WORD4 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD4")] +pub type Mb32bGroupMb8_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word4; +#[doc = "MB_GROUP_WORD021 (rw) register accessor: Message Buffer 21 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word021::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word021::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word021`] module"] +#[doc(alias = "MB_GROUP_WORD021")] +pub type MbGroupWord021 = crate::Reg; +#[doc = "Message Buffer 21 WORD0 Register"] +pub mod mb_group_word021; +#[doc = "MB_16B_GROUP_MB14_16B_WORD1 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD1")] +pub type Mb16bGroupMb14_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 14 WORD_16B Register"] +pub mod mb_16b_group_mb14_16b_word1; +#[doc = "MB_8B_GROUP_MB21_8B_WORD1 (rw) register accessor: Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB21_8B_WORD1")] +pub type Mb8bGroupMb21_8bWord1 = crate::Reg; +#[doc = "Message Buffer 21 WORD_8B Register"] +pub mod mb_8b_group_mb21_8b_word1; +#[doc = "MB_64B_GROUP_MB4_64B_WORD13 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word13`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD13")] +pub type Mb64bGroupMb4_64bWord13 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word13; +#[doc = "MB_32B_GROUP_MB8_32B_WORD5 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD5")] +pub type Mb32bGroupMb8_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word5; +#[doc = "MB_GROUP_WORD121 (rw) register accessor: Message Buffer 21 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word121::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word121::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word121`] module"] +#[doc(alias = "MB_GROUP_WORD121")] +pub type MbGroupWord121 = crate::Reg; +#[doc = "Message Buffer 21 WORD1 Register"] +pub mod mb_group_word121; +#[doc = "MB_GROUP_CS22 (rw) register accessor: Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs22`] module"] +#[doc(alias = "MB_GROUP_CS22")] +pub type MbGroupCs22 = crate::Reg; +#[doc = "Message Buffer 22 CS Register"] +pub mod mb_group_cs22; +#[doc = "MB_16B_GROUP_MB14_16B_WORD2 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD2")] +pub type Mb16bGroupMb14_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 14 WORD_16B Register"] +pub mod mb_16b_group_mb14_16b_word2; +#[doc = "MB_8B_GROUP_MB22_8B_CS (rw) register accessor: Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB22_8B_CS")] +pub type Mb8bGroupMb22_8bCs = crate::Reg; +#[doc = "Message Buffer 22 CS Register"] +pub mod mb_8b_group_mb22_8b_cs; +#[doc = "MB_64B_GROUP_MB4_64B_WORD14 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word14`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD14")] +pub type Mb64bGroupMb4_64bWord14 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word14; +#[doc = "MB_32B_GROUP_MB8_32B_WORD6 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD6")] +pub type Mb32bGroupMb8_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word6; +#[doc = "MB_GROUP_ID22 (rw) register accessor: Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id22`] module"] +#[doc(alias = "MB_GROUP_ID22")] +pub type MbGroupId22 = crate::Reg; +#[doc = "Message Buffer 22 ID Register"] +pub mod mb_group_id22; +#[doc = "MB_16B_GROUP_MB14_16B_WORD3 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD3")] +pub type Mb16bGroupMb14_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 14 WORD_16B Register"] +pub mod mb_16b_group_mb14_16b_word3; +#[doc = "MB_8B_GROUP_MB22_8B_ID (rw) register accessor: Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB22_8B_ID")] +pub type Mb8bGroupMb22_8bId = crate::Reg; +#[doc = "Message Buffer 22 ID Register"] +pub mod mb_8b_group_mb22_8b_id; +#[doc = "MB_64B_GROUP_MB4_64B_WORD15 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word15`] module"] +#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD15")] +pub type Mb64bGroupMb4_64bWord15 = + crate::Reg; +#[doc = "Message Buffer 4 WORD_64B Register"] +pub mod mb_64b_group_mb4_64b_word15; +#[doc = "MB_32B_GROUP_MB8_32B_WORD7 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD7")] +pub type Mb32bGroupMb8_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 8 WORD_32B Register"] +pub mod mb_32b_group_mb8_32b_word7; +#[doc = "MB_16B_GROUP_MB15_16B_CS (rw) register accessor: Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB15_16B_CS")] +pub type Mb16bGroupMb15_16bCs = crate::Reg; +#[doc = "Message Buffer 15 CS Register"] +pub mod mb_16b_group_mb15_16b_cs; +#[doc = "MB_8B_GROUP_MB22_8B_WORD0 (rw) register accessor: Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB22_8B_WORD0")] +pub type Mb8bGroupMb22_8bWord0 = crate::Reg; +#[doc = "Message Buffer 22 WORD_8B Register"] +pub mod mb_8b_group_mb22_8b_word0; +#[doc = "MB_64B_GROUP_MB5_64B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_cs`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_CS")] +pub type Mb64bGroupMb5_64bCs = crate::Reg; +#[doc = "Message Buffer 5 CS Register"] +pub mod mb_64b_group_mb5_64b_cs; +#[doc = "MB_32B_GROUP_MB9_32B_CS (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_CS")] +pub type Mb32bGroupMb9_32bCs = crate::Reg; +#[doc = "Message Buffer 9 CS Register"] +pub mod mb_32b_group_mb9_32b_cs; +#[doc = "MB_GROUP_WORD022 (rw) register accessor: Message Buffer 22 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word022::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word022::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word022`] module"] +#[doc(alias = "MB_GROUP_WORD022")] +pub type MbGroupWord022 = crate::Reg; +#[doc = "Message Buffer 22 WORD0 Register"] +pub mod mb_group_word022; +#[doc = "MB_16B_GROUP_MB15_16B_ID (rw) register accessor: Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB15_16B_ID")] +pub type Mb16bGroupMb15_16bId = crate::Reg; +#[doc = "Message Buffer 15 ID Register"] +pub mod mb_16b_group_mb15_16b_id; +#[doc = "MB_8B_GROUP_MB22_8B_WORD1 (rw) register accessor: Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB22_8B_WORD1")] +pub type Mb8bGroupMb22_8bWord1 = crate::Reg; +#[doc = "Message Buffer 22 WORD_8B Register"] +pub mod mb_8b_group_mb22_8b_word1; +#[doc = "MB_64B_GROUP_MB5_64B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_id`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_ID")] +pub type Mb64bGroupMb5_64bId = crate::Reg; +#[doc = "Message Buffer 5 ID Register"] +pub mod mb_64b_group_mb5_64b_id; +#[doc = "MB_32B_GROUP_MB9_32B_ID (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_ID")] +pub type Mb32bGroupMb9_32bId = crate::Reg; +#[doc = "Message Buffer 9 ID Register"] +pub mod mb_32b_group_mb9_32b_id; +#[doc = "MB_GROUP_WORD122 (rw) register accessor: Message Buffer 22 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word122::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word122::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word122`] module"] +#[doc(alias = "MB_GROUP_WORD122")] +pub type MbGroupWord122 = crate::Reg; +#[doc = "Message Buffer 22 WORD1 Register"] +pub mod mb_group_word122; +#[doc = "MB_GROUP_CS23 (rw) register accessor: Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs23`] module"] +#[doc(alias = "MB_GROUP_CS23")] +pub type MbGroupCs23 = crate::Reg; +#[doc = "Message Buffer 23 CS Register"] +pub mod mb_group_cs23; +#[doc = "MB_16B_GROUP_MB15_16B_WORD0 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD0")] +pub type Mb16bGroupMb15_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 15 WORD_16B Register"] +pub mod mb_16b_group_mb15_16b_word0; +#[doc = "MB_8B_GROUP_MB23_8B_CS (rw) register accessor: Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB23_8B_CS")] +pub type Mb8bGroupMb23_8bCs = crate::Reg; +#[doc = "Message Buffer 23 CS Register"] +pub mod mb_8b_group_mb23_8b_cs; +#[doc = "MB_64B_GROUP_MB5_64B_WORD0 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word0`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD0")] +pub type Mb64bGroupMb5_64bWord0 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word0; +#[doc = "MB_32B_GROUP_MB9_32B_WORD0 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD0")] +pub type Mb32bGroupMb9_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word0; +#[doc = "MB_GROUP_ID23 (rw) register accessor: Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id23`] module"] +#[doc(alias = "MB_GROUP_ID23")] +pub type MbGroupId23 = crate::Reg; +#[doc = "Message Buffer 23 ID Register"] +pub mod mb_group_id23; +#[doc = "MB_16B_GROUP_MB15_16B_WORD1 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD1")] +pub type Mb16bGroupMb15_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 15 WORD_16B Register"] +pub mod mb_16b_group_mb15_16b_word1; +#[doc = "MB_8B_GROUP_MB23_8B_ID (rw) register accessor: Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB23_8B_ID")] +pub type Mb8bGroupMb23_8bId = crate::Reg; +#[doc = "Message Buffer 23 ID Register"] +pub mod mb_8b_group_mb23_8b_id; +#[doc = "MB_64B_GROUP_MB5_64B_WORD1 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word1`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD1")] +pub type Mb64bGroupMb5_64bWord1 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word1; +#[doc = "MB_32B_GROUP_MB9_32B_WORD1 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD1")] +pub type Mb32bGroupMb9_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word1; +#[doc = "MB_16B_GROUP_MB15_16B_WORD2 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD2")] +pub type Mb16bGroupMb15_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 15 WORD_16B Register"] +pub mod mb_16b_group_mb15_16b_word2; +#[doc = "MB_8B_GROUP_MB23_8B_WORD0 (rw) register accessor: Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB23_8B_WORD0")] +pub type Mb8bGroupMb23_8bWord0 = crate::Reg; +#[doc = "Message Buffer 23 WORD_8B Register"] +pub mod mb_8b_group_mb23_8b_word0; +#[doc = "MB_64B_GROUP_MB5_64B_WORD2 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word2`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD2")] +pub type Mb64bGroupMb5_64bWord2 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word2; +#[doc = "MB_32B_GROUP_MB9_32B_WORD2 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD2")] +pub type Mb32bGroupMb9_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word2; +#[doc = "MB_GROUP_WORD023 (rw) register accessor: Message Buffer 23 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word023::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word023::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word023`] module"] +#[doc(alias = "MB_GROUP_WORD023")] +pub type MbGroupWord023 = crate::Reg; +#[doc = "Message Buffer 23 WORD0 Register"] +pub mod mb_group_word023; +#[doc = "MB_16B_GROUP_MB15_16B_WORD3 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD3")] +pub type Mb16bGroupMb15_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 15 WORD_16B Register"] +pub mod mb_16b_group_mb15_16b_word3; +#[doc = "MB_8B_GROUP_MB23_8B_WORD1 (rw) register accessor: Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB23_8B_WORD1")] +pub type Mb8bGroupMb23_8bWord1 = crate::Reg; +#[doc = "Message Buffer 23 WORD_8B Register"] +pub mod mb_8b_group_mb23_8b_word1; +#[doc = "MB_64B_GROUP_MB5_64B_WORD3 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word3`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD3")] +pub type Mb64bGroupMb5_64bWord3 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word3; +#[doc = "MB_32B_GROUP_MB9_32B_WORD3 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD3")] +pub type Mb32bGroupMb9_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word3; +#[doc = "MB_GROUP_WORD123 (rw) register accessor: Message Buffer 23 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word123::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word123::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word123`] module"] +#[doc(alias = "MB_GROUP_WORD123")] +pub type MbGroupWord123 = crate::Reg; +#[doc = "Message Buffer 23 WORD1 Register"] +pub mod mb_group_word123; +#[doc = "MB_GROUP_CS24 (rw) register accessor: Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs24`] module"] +#[doc(alias = "MB_GROUP_CS24")] +pub type MbGroupCs24 = crate::Reg; +#[doc = "Message Buffer 24 CS Register"] +pub mod mb_group_cs24; +#[doc = "MB_16B_GROUP_MB16_16B_CS (rw) register accessor: Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB16_16B_CS")] +pub type Mb16bGroupMb16_16bCs = crate::Reg; +#[doc = "Message Buffer 16 CS Register"] +pub mod mb_16b_group_mb16_16b_cs; +#[doc = "MB_8B_GROUP_MB24_8B_CS (rw) register accessor: Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB24_8B_CS")] +pub type Mb8bGroupMb24_8bCs = crate::Reg; +#[doc = "Message Buffer 24 CS Register"] +pub mod mb_8b_group_mb24_8b_cs; +#[doc = "MB_64B_GROUP_MB5_64B_WORD4 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word4`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD4")] +pub type Mb64bGroupMb5_64bWord4 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word4; +#[doc = "MB_32B_GROUP_MB9_32B_WORD4 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD4")] +pub type Mb32bGroupMb9_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word4; +#[doc = "MB_GROUP_ID24 (rw) register accessor: Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id24`] module"] +#[doc(alias = "MB_GROUP_ID24")] +pub type MbGroupId24 = crate::Reg; +#[doc = "Message Buffer 24 ID Register"] +pub mod mb_group_id24; +#[doc = "MB_16B_GROUP_MB16_16B_ID (rw) register accessor: Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB16_16B_ID")] +pub type Mb16bGroupMb16_16bId = crate::Reg; +#[doc = "Message Buffer 16 ID Register"] +pub mod mb_16b_group_mb16_16b_id; +#[doc = "MB_8B_GROUP_MB24_8B_ID (rw) register accessor: Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB24_8B_ID")] +pub type Mb8bGroupMb24_8bId = crate::Reg; +#[doc = "Message Buffer 24 ID Register"] +pub mod mb_8b_group_mb24_8b_id; +#[doc = "MB_64B_GROUP_MB5_64B_WORD5 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word5`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD5")] +pub type Mb64bGroupMb5_64bWord5 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word5; +#[doc = "MB_32B_GROUP_MB9_32B_WORD5 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD5")] +pub type Mb32bGroupMb9_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word5; +#[doc = "MB_16B_GROUP_MB16_16B_WORD0 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD0")] +pub type Mb16bGroupMb16_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 16 WORD_16B Register"] +pub mod mb_16b_group_mb16_16b_word0; +#[doc = "MB_8B_GROUP_MB24_8B_WORD0 (rw) register accessor: Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB24_8B_WORD0")] +pub type Mb8bGroupMb24_8bWord0 = crate::Reg; +#[doc = "Message Buffer 24 WORD_8B Register"] +pub mod mb_8b_group_mb24_8b_word0; +#[doc = "MB_64B_GROUP_MB5_64B_WORD6 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word6`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD6")] +pub type Mb64bGroupMb5_64bWord6 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word6; +#[doc = "MB_32B_GROUP_MB9_32B_WORD6 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD6")] +pub type Mb32bGroupMb9_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word6; +#[doc = "MB_GROUP_WORD024 (rw) register accessor: Message Buffer 24 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word024::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word024::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word024`] module"] +#[doc(alias = "MB_GROUP_WORD024")] +pub type MbGroupWord024 = crate::Reg; +#[doc = "Message Buffer 24 WORD0 Register"] +pub mod mb_group_word024; +#[doc = "MB_16B_GROUP_MB16_16B_WORD1 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD1")] +pub type Mb16bGroupMb16_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 16 WORD_16B Register"] +pub mod mb_16b_group_mb16_16b_word1; +#[doc = "MB_8B_GROUP_MB24_8B_WORD1 (rw) register accessor: Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB24_8B_WORD1")] +pub type Mb8bGroupMb24_8bWord1 = crate::Reg; +#[doc = "Message Buffer 24 WORD_8B Register"] +pub mod mb_8b_group_mb24_8b_word1; +#[doc = "MB_64B_GROUP_MB5_64B_WORD7 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word7`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD7")] +pub type Mb64bGroupMb5_64bWord7 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word7; +#[doc = "MB_32B_GROUP_MB9_32B_WORD7 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD7")] +pub type Mb32bGroupMb9_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 9 WORD_32B Register"] +pub mod mb_32b_group_mb9_32b_word7; +#[doc = "MB_GROUP_WORD124 (rw) register accessor: Message Buffer 24 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word124::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word124::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word124`] module"] +#[doc(alias = "MB_GROUP_WORD124")] +pub type MbGroupWord124 = crate::Reg; +#[doc = "Message Buffer 24 WORD1 Register"] +pub mod mb_group_word124; +#[doc = "MB_GROUP_CS25 (rw) register accessor: Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs25`] module"] +#[doc(alias = "MB_GROUP_CS25")] +pub type MbGroupCs25 = crate::Reg; +#[doc = "Message Buffer 25 CS Register"] +pub mod mb_group_cs25; +#[doc = "MB_32B_GROUP_MB10_32B_CS (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_CS")] +pub type Mb32bGroupMb10_32bCs = crate::Reg; +#[doc = "Message Buffer 10 CS Register"] +pub mod mb_32b_group_mb10_32b_cs; +#[doc = "MB_16B_GROUP_MB16_16B_WORD2 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD2")] +pub type Mb16bGroupMb16_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 16 WORD_16B Register"] +pub mod mb_16b_group_mb16_16b_word2; +#[doc = "MB_8B_GROUP_MB25_8B_CS (rw) register accessor: Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB25_8B_CS")] +pub type Mb8bGroupMb25_8bCs = crate::Reg; +#[doc = "Message Buffer 25 CS Register"] +pub mod mb_8b_group_mb25_8b_cs; +#[doc = "MB_64B_GROUP_MB5_64B_WORD8 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word8`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD8")] +pub type Mb64bGroupMb5_64bWord8 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word8; +#[doc = "MB_GROUP_ID25 (rw) register accessor: Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id25`] module"] +#[doc(alias = "MB_GROUP_ID25")] +pub type MbGroupId25 = crate::Reg; +#[doc = "Message Buffer 25 ID Register"] +pub mod mb_group_id25; +#[doc = "MB_32B_GROUP_MB10_32B_ID (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_ID")] +pub type Mb32bGroupMb10_32bId = crate::Reg; +#[doc = "Message Buffer 10 ID Register"] +pub mod mb_32b_group_mb10_32b_id; +#[doc = "MB_16B_GROUP_MB16_16B_WORD3 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD3")] +pub type Mb16bGroupMb16_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 16 WORD_16B Register"] +pub mod mb_16b_group_mb16_16b_word3; +#[doc = "MB_8B_GROUP_MB25_8B_ID (rw) register accessor: Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB25_8B_ID")] +pub type Mb8bGroupMb25_8bId = crate::Reg; +#[doc = "Message Buffer 25 ID Register"] +pub mod mb_8b_group_mb25_8b_id; +#[doc = "MB_64B_GROUP_MB5_64B_WORD9 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word9`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD9")] +pub type Mb64bGroupMb5_64bWord9 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word9; +#[doc = "MB_32B_GROUP_MB10_32B_WORD0 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD0")] +pub type Mb32bGroupMb10_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word0; +#[doc = "MB_16B_GROUP_MB17_16B_CS (rw) register accessor: Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB17_16B_CS")] +pub type Mb16bGroupMb17_16bCs = crate::Reg; +#[doc = "Message Buffer 17 CS Register"] +pub mod mb_16b_group_mb17_16b_cs; +#[doc = "MB_8B_GROUP_MB25_8B_WORD0 (rw) register accessor: Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB25_8B_WORD0")] +pub type Mb8bGroupMb25_8bWord0 = crate::Reg; +#[doc = "Message Buffer 25 WORD_8B Register"] +pub mod mb_8b_group_mb25_8b_word0; +#[doc = "MB_64B_GROUP_MB5_64B_WORD10 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word10`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD10")] +pub type Mb64bGroupMb5_64bWord10 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word10; +#[doc = "MB_GROUP_WORD025 (rw) register accessor: Message Buffer 25 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word025::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word025::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word025`] module"] +#[doc(alias = "MB_GROUP_WORD025")] +pub type MbGroupWord025 = crate::Reg; +#[doc = "Message Buffer 25 WORD0 Register"] +pub mod mb_group_word025; +#[doc = "MB_32B_GROUP_MB10_32B_WORD1 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD1")] +pub type Mb32bGroupMb10_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word1; +#[doc = "MB_16B_GROUP_MB17_16B_ID (rw) register accessor: Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB17_16B_ID")] +pub type Mb16bGroupMb17_16bId = crate::Reg; +#[doc = "Message Buffer 17 ID Register"] +pub mod mb_16b_group_mb17_16b_id; +#[doc = "MB_8B_GROUP_MB25_8B_WORD1 (rw) register accessor: Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB25_8B_WORD1")] +pub type Mb8bGroupMb25_8bWord1 = crate::Reg; +#[doc = "Message Buffer 25 WORD_8B Register"] +pub mod mb_8b_group_mb25_8b_word1; +#[doc = "MB_64B_GROUP_MB5_64B_WORD11 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word11`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD11")] +pub type Mb64bGroupMb5_64bWord11 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word11; +#[doc = "MB_GROUP_WORD125 (rw) register accessor: Message Buffer 25 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word125::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word125::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word125`] module"] +#[doc(alias = "MB_GROUP_WORD125")] +pub type MbGroupWord125 = crate::Reg; +#[doc = "Message Buffer 25 WORD1 Register"] +pub mod mb_group_word125; +#[doc = "MB_GROUP_CS26 (rw) register accessor: Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs26`] module"] +#[doc(alias = "MB_GROUP_CS26")] +pub type MbGroupCs26 = crate::Reg; +#[doc = "Message Buffer 26 CS Register"] +pub mod mb_group_cs26; +#[doc = "MB_32B_GROUP_MB10_32B_WORD2 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD2")] +pub type Mb32bGroupMb10_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word2; +#[doc = "MB_16B_GROUP_MB17_16B_WORD0 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD0")] +pub type Mb16bGroupMb17_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 17 WORD_16B Register"] +pub mod mb_16b_group_mb17_16b_word0; +#[doc = "MB_8B_GROUP_MB26_8B_CS (rw) register accessor: Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB26_8B_CS")] +pub type Mb8bGroupMb26_8bCs = crate::Reg; +#[doc = "Message Buffer 26 CS Register"] +pub mod mb_8b_group_mb26_8b_cs; +#[doc = "MB_64B_GROUP_MB5_64B_WORD12 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word12`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD12")] +pub type Mb64bGroupMb5_64bWord12 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word12; +#[doc = "MB_GROUP_ID26 (rw) register accessor: Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id26`] module"] +#[doc(alias = "MB_GROUP_ID26")] +pub type MbGroupId26 = crate::Reg; +#[doc = "Message Buffer 26 ID Register"] +pub mod mb_group_id26; +#[doc = "MB_32B_GROUP_MB10_32B_WORD3 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD3")] +pub type Mb32bGroupMb10_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word3; +#[doc = "MB_16B_GROUP_MB17_16B_WORD1 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD1")] +pub type Mb16bGroupMb17_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 17 WORD_16B Register"] +pub mod mb_16b_group_mb17_16b_word1; +#[doc = "MB_8B_GROUP_MB26_8B_ID (rw) register accessor: Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB26_8B_ID")] +pub type Mb8bGroupMb26_8bId = crate::Reg; +#[doc = "Message Buffer 26 ID Register"] +pub mod mb_8b_group_mb26_8b_id; +#[doc = "MB_64B_GROUP_MB5_64B_WORD13 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word13`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD13")] +pub type Mb64bGroupMb5_64bWord13 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word13; +#[doc = "MB_32B_GROUP_MB10_32B_WORD4 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD4")] +pub type Mb32bGroupMb10_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word4; +#[doc = "MB_16B_GROUP_MB17_16B_WORD2 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD2")] +pub type Mb16bGroupMb17_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 17 WORD_16B Register"] +pub mod mb_16b_group_mb17_16b_word2; +#[doc = "MB_8B_GROUP_MB26_8B_WORD0 (rw) register accessor: Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB26_8B_WORD0")] +pub type Mb8bGroupMb26_8bWord0 = crate::Reg; +#[doc = "Message Buffer 26 WORD_8B Register"] +pub mod mb_8b_group_mb26_8b_word0; +#[doc = "MB_64B_GROUP_MB5_64B_WORD14 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word14`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD14")] +pub type Mb64bGroupMb5_64bWord14 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word14; +#[doc = "MB_GROUP_WORD026 (rw) register accessor: Message Buffer 26 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word026::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word026::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word026`] module"] +#[doc(alias = "MB_GROUP_WORD026")] +pub type MbGroupWord026 = crate::Reg; +#[doc = "Message Buffer 26 WORD0 Register"] +pub mod mb_group_word026; +#[doc = "MB_32B_GROUP_MB10_32B_WORD5 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD5")] +pub type Mb32bGroupMb10_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word5; +#[doc = "MB_16B_GROUP_MB17_16B_WORD3 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD3")] +pub type Mb16bGroupMb17_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 17 WORD_16B Register"] +pub mod mb_16b_group_mb17_16b_word3; +#[doc = "MB_8B_GROUP_MB26_8B_WORD1 (rw) register accessor: Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB26_8B_WORD1")] +pub type Mb8bGroupMb26_8bWord1 = crate::Reg; +#[doc = "Message Buffer 26 WORD_8B Register"] +pub mod mb_8b_group_mb26_8b_word1; +#[doc = "MB_64B_GROUP_MB5_64B_WORD15 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word15`] module"] +#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD15")] +pub type Mb64bGroupMb5_64bWord15 = + crate::Reg; +#[doc = "Message Buffer 5 WORD_64B Register"] +pub mod mb_64b_group_mb5_64b_word15; +#[doc = "MB_GROUP_WORD126 (rw) register accessor: Message Buffer 26 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word126::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word126::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word126`] module"] +#[doc(alias = "MB_GROUP_WORD126")] +pub type MbGroupWord126 = crate::Reg; +#[doc = "Message Buffer 26 WORD1 Register"] +pub mod mb_group_word126; +#[doc = "MB_GROUP_CS27 (rw) register accessor: Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs27`] module"] +#[doc(alias = "MB_GROUP_CS27")] +pub type MbGroupCs27 = crate::Reg; +#[doc = "Message Buffer 27 CS Register"] +pub mod mb_group_cs27; +#[doc = "MB_32B_GROUP_MB10_32B_WORD6 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD6")] +pub type Mb32bGroupMb10_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word6; +#[doc = "MB_16B_GROUP_MB18_16B_CS (rw) register accessor: Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB18_16B_CS")] +pub type Mb16bGroupMb18_16bCs = crate::Reg; +#[doc = "Message Buffer 18 CS Register"] +pub mod mb_16b_group_mb18_16b_cs; +#[doc = "MB_8B_GROUP_MB27_8B_CS (rw) register accessor: Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB27_8B_CS")] +pub type Mb8bGroupMb27_8bCs = crate::Reg; +#[doc = "Message Buffer 27 CS Register"] +pub mod mb_8b_group_mb27_8b_cs; +#[doc = "MB_64B_GROUP_MB6_64B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_cs`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_CS")] +pub type Mb64bGroupMb6_64bCs = crate::Reg; +#[doc = "Message Buffer 6 CS Register"] +pub mod mb_64b_group_mb6_64b_cs; +#[doc = "MB_GROUP_ID27 (rw) register accessor: Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id27`] module"] +#[doc(alias = "MB_GROUP_ID27")] +pub type MbGroupId27 = crate::Reg; +#[doc = "Message Buffer 27 ID Register"] +pub mod mb_group_id27; +#[doc = "MB_32B_GROUP_MB10_32B_WORD7 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD7")] +pub type Mb32bGroupMb10_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 10 WORD_32B Register"] +pub mod mb_32b_group_mb10_32b_word7; +#[doc = "MB_16B_GROUP_MB18_16B_ID (rw) register accessor: Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB18_16B_ID")] +pub type Mb16bGroupMb18_16bId = crate::Reg; +#[doc = "Message Buffer 18 ID Register"] +pub mod mb_16b_group_mb18_16b_id; +#[doc = "MB_8B_GROUP_MB27_8B_ID (rw) register accessor: Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB27_8B_ID")] +pub type Mb8bGroupMb27_8bId = crate::Reg; +#[doc = "Message Buffer 27 ID Register"] +pub mod mb_8b_group_mb27_8b_id; +#[doc = "MB_64B_GROUP_MB6_64B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_id`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_ID")] +pub type Mb64bGroupMb6_64bId = crate::Reg; +#[doc = "Message Buffer 6 ID Register"] +pub mod mb_64b_group_mb6_64b_id; +#[doc = "MB_32B_GROUP_MB11_32B_CS (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_cs`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_CS")] +pub type Mb32bGroupMb11_32bCs = crate::Reg; +#[doc = "Message Buffer 11 CS Register"] +pub mod mb_32b_group_mb11_32b_cs; +#[doc = "MB_16B_GROUP_MB18_16B_WORD0 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD0")] +pub type Mb16bGroupMb18_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 18 WORD_16B Register"] +pub mod mb_16b_group_mb18_16b_word0; +#[doc = "MB_8B_GROUP_MB27_8B_WORD0 (rw) register accessor: Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB27_8B_WORD0")] +pub type Mb8bGroupMb27_8bWord0 = crate::Reg; +#[doc = "Message Buffer 27 WORD_8B Register"] +pub mod mb_8b_group_mb27_8b_word0; +#[doc = "MB_64B_GROUP_MB6_64B_WORD0 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word0`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD0")] +pub type Mb64bGroupMb6_64bWord0 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word0; +#[doc = "MB_GROUP_WORD027 (rw) register accessor: Message Buffer 27 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word027::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word027::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word027`] module"] +#[doc(alias = "MB_GROUP_WORD027")] +pub type MbGroupWord027 = crate::Reg; +#[doc = "Message Buffer 27 WORD0 Register"] +pub mod mb_group_word027; +#[doc = "MB_32B_GROUP_MB11_32B_ID (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_id`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_ID")] +pub type Mb32bGroupMb11_32bId = crate::Reg; +#[doc = "Message Buffer 11 ID Register"] +pub mod mb_32b_group_mb11_32b_id; +#[doc = "MB_16B_GROUP_MB18_16B_WORD1 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD1")] +pub type Mb16bGroupMb18_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 18 WORD_16B Register"] +pub mod mb_16b_group_mb18_16b_word1; +#[doc = "MB_8B_GROUP_MB27_8B_WORD1 (rw) register accessor: Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB27_8B_WORD1")] +pub type Mb8bGroupMb27_8bWord1 = crate::Reg; +#[doc = "Message Buffer 27 WORD_8B Register"] +pub mod mb_8b_group_mb27_8b_word1; +#[doc = "MB_64B_GROUP_MB6_64B_WORD1 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word1`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD1")] +pub type Mb64bGroupMb6_64bWord1 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word1; +#[doc = "MB_GROUP_WORD127 (rw) register accessor: Message Buffer 27 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word127::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word127::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word127`] module"] +#[doc(alias = "MB_GROUP_WORD127")] +pub type MbGroupWord127 = crate::Reg; +#[doc = "Message Buffer 27 WORD1 Register"] +pub mod mb_group_word127; +#[doc = "MB_GROUP_CS28 (rw) register accessor: Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs28`] module"] +#[doc(alias = "MB_GROUP_CS28")] +pub type MbGroupCs28 = crate::Reg; +#[doc = "Message Buffer 28 CS Register"] +pub mod mb_group_cs28; +#[doc = "MB_32B_GROUP_MB11_32B_WORD0 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word0`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD0")] +pub type Mb32bGroupMb11_32bWord0 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word0; +#[doc = "MB_16B_GROUP_MB18_16B_WORD2 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD2")] +pub type Mb16bGroupMb18_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 18 WORD_16B Register"] +pub mod mb_16b_group_mb18_16b_word2; +#[doc = "MB_8B_GROUP_MB28_8B_CS (rw) register accessor: Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB28_8B_CS")] +pub type Mb8bGroupMb28_8bCs = crate::Reg; +#[doc = "Message Buffer 28 CS Register"] +pub mod mb_8b_group_mb28_8b_cs; +#[doc = "MB_64B_GROUP_MB6_64B_WORD2 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word2`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD2")] +pub type Mb64bGroupMb6_64bWord2 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word2; +#[doc = "MB_GROUP_ID28 (rw) register accessor: Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id28`] module"] +#[doc(alias = "MB_GROUP_ID28")] +pub type MbGroupId28 = crate::Reg; +#[doc = "Message Buffer 28 ID Register"] +pub mod mb_group_id28; +#[doc = "MB_32B_GROUP_MB11_32B_WORD1 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word1`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD1")] +pub type Mb32bGroupMb11_32bWord1 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word1; +#[doc = "MB_16B_GROUP_MB18_16B_WORD3 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD3")] +pub type Mb16bGroupMb18_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 18 WORD_16B Register"] +pub mod mb_16b_group_mb18_16b_word3; +#[doc = "MB_8B_GROUP_MB28_8B_ID (rw) register accessor: Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB28_8B_ID")] +pub type Mb8bGroupMb28_8bId = crate::Reg; +#[doc = "Message Buffer 28 ID Register"] +pub mod mb_8b_group_mb28_8b_id; +#[doc = "MB_64B_GROUP_MB6_64B_WORD3 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word3`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD3")] +pub type Mb64bGroupMb6_64bWord3 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word3; +#[doc = "MB_32B_GROUP_MB11_32B_WORD2 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word2`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD2")] +pub type Mb32bGroupMb11_32bWord2 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word2; +#[doc = "MB_16B_GROUP_MB19_16B_CS (rw) register accessor: Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB19_16B_CS")] +pub type Mb16bGroupMb19_16bCs = crate::Reg; +#[doc = "Message Buffer 19 CS Register"] +pub mod mb_16b_group_mb19_16b_cs; +#[doc = "MB_8B_GROUP_MB28_8B_WORD0 (rw) register accessor: Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB28_8B_WORD0")] +pub type Mb8bGroupMb28_8bWord0 = crate::Reg; +#[doc = "Message Buffer 28 WORD_8B Register"] +pub mod mb_8b_group_mb28_8b_word0; +#[doc = "MB_64B_GROUP_MB6_64B_WORD4 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word4`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD4")] +pub type Mb64bGroupMb6_64bWord4 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word4; +#[doc = "MB_GROUP_WORD028 (rw) register accessor: Message Buffer 28 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word028::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word028::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word028`] module"] +#[doc(alias = "MB_GROUP_WORD028")] +pub type MbGroupWord028 = crate::Reg; +#[doc = "Message Buffer 28 WORD0 Register"] +pub mod mb_group_word028; +#[doc = "MB_32B_GROUP_MB11_32B_WORD3 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word3`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD3")] +pub type Mb32bGroupMb11_32bWord3 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word3; +#[doc = "MB_16B_GROUP_MB19_16B_ID (rw) register accessor: Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB19_16B_ID")] +pub type Mb16bGroupMb19_16bId = crate::Reg; +#[doc = "Message Buffer 19 ID Register"] +pub mod mb_16b_group_mb19_16b_id; +#[doc = "MB_8B_GROUP_MB28_8B_WORD1 (rw) register accessor: Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB28_8B_WORD1")] +pub type Mb8bGroupMb28_8bWord1 = crate::Reg; +#[doc = "Message Buffer 28 WORD_8B Register"] +pub mod mb_8b_group_mb28_8b_word1; +#[doc = "MB_64B_GROUP_MB6_64B_WORD5 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word5`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD5")] +pub type Mb64bGroupMb6_64bWord5 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word5; +#[doc = "MB_GROUP_WORD128 (rw) register accessor: Message Buffer 28 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word128::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word128::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word128`] module"] +#[doc(alias = "MB_GROUP_WORD128")] +pub type MbGroupWord128 = crate::Reg; +#[doc = "Message Buffer 28 WORD1 Register"] +pub mod mb_group_word128; +#[doc = "MB_GROUP_CS29 (rw) register accessor: Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs29`] module"] +#[doc(alias = "MB_GROUP_CS29")] +pub type MbGroupCs29 = crate::Reg; +#[doc = "Message Buffer 29 CS Register"] +pub mod mb_group_cs29; +#[doc = "MB_32B_GROUP_MB11_32B_WORD4 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word4`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD4")] +pub type Mb32bGroupMb11_32bWord4 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word4; +#[doc = "MB_16B_GROUP_MB19_16B_WORD0 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD0")] +pub type Mb16bGroupMb19_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 19 WORD_16B Register"] +pub mod mb_16b_group_mb19_16b_word0; +#[doc = "MB_8B_GROUP_MB29_8B_CS (rw) register accessor: Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB29_8B_CS")] +pub type Mb8bGroupMb29_8bCs = crate::Reg; +#[doc = "Message Buffer 29 CS Register"] +pub mod mb_8b_group_mb29_8b_cs; +#[doc = "MB_64B_GROUP_MB6_64B_WORD6 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word6`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD6")] +pub type Mb64bGroupMb6_64bWord6 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word6; +#[doc = "MB_GROUP_ID29 (rw) register accessor: Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id29`] module"] +#[doc(alias = "MB_GROUP_ID29")] +pub type MbGroupId29 = crate::Reg; +#[doc = "Message Buffer 29 ID Register"] +pub mod mb_group_id29; +#[doc = "MB_32B_GROUP_MB11_32B_WORD5 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word5`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD5")] +pub type Mb32bGroupMb11_32bWord5 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word5; +#[doc = "MB_16B_GROUP_MB19_16B_WORD1 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD1")] +pub type Mb16bGroupMb19_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 19 WORD_16B Register"] +pub mod mb_16b_group_mb19_16b_word1; +#[doc = "MB_8B_GROUP_MB29_8B_ID (rw) register accessor: Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB29_8B_ID")] +pub type Mb8bGroupMb29_8bId = crate::Reg; +#[doc = "Message Buffer 29 ID Register"] +pub mod mb_8b_group_mb29_8b_id; +#[doc = "MB_64B_GROUP_MB6_64B_WORD7 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word7`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD7")] +pub type Mb64bGroupMb6_64bWord7 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word7; +#[doc = "MB_32B_GROUP_MB11_32B_WORD6 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word6`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD6")] +pub type Mb32bGroupMb11_32bWord6 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word6; +#[doc = "MB_16B_GROUP_MB19_16B_WORD2 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD2")] +pub type Mb16bGroupMb19_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 19 WORD_16B Register"] +pub mod mb_16b_group_mb19_16b_word2; +#[doc = "MB_8B_GROUP_MB29_8B_WORD0 (rw) register accessor: Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB29_8B_WORD0")] +pub type Mb8bGroupMb29_8bWord0 = crate::Reg; +#[doc = "Message Buffer 29 WORD_8B Register"] +pub mod mb_8b_group_mb29_8b_word0; +#[doc = "MB_64B_GROUP_MB6_64B_WORD8 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word8`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD8")] +pub type Mb64bGroupMb6_64bWord8 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word8; +#[doc = "MB_GROUP_WORD029 (rw) register accessor: Message Buffer 29 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word029::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word029::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word029`] module"] +#[doc(alias = "MB_GROUP_WORD029")] +pub type MbGroupWord029 = crate::Reg; +#[doc = "Message Buffer 29 WORD0 Register"] +pub mod mb_group_word029; +#[doc = "MB_32B_GROUP_MB11_32B_WORD7 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word7`] module"] +#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD7")] +pub type Mb32bGroupMb11_32bWord7 = + crate::Reg; +#[doc = "Message Buffer 11 WORD_32B Register"] +pub mod mb_32b_group_mb11_32b_word7; +#[doc = "MB_16B_GROUP_MB19_16B_WORD3 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD3")] +pub type Mb16bGroupMb19_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 19 WORD_16B Register"] +pub mod mb_16b_group_mb19_16b_word3; +#[doc = "MB_8B_GROUP_MB29_8B_WORD1 (rw) register accessor: Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB29_8B_WORD1")] +pub type Mb8bGroupMb29_8bWord1 = crate::Reg; +#[doc = "Message Buffer 29 WORD_8B Register"] +pub mod mb_8b_group_mb29_8b_word1; +#[doc = "MB_64B_GROUP_MB6_64B_WORD9 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word9`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD9")] +pub type Mb64bGroupMb6_64bWord9 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word9; +#[doc = "MB_GROUP_WORD129 (rw) register accessor: Message Buffer 29 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word129::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word129::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word129`] module"] +#[doc(alias = "MB_GROUP_WORD129")] +pub type MbGroupWord129 = crate::Reg; +#[doc = "Message Buffer 29 WORD1 Register"] +pub mod mb_group_word129; +#[doc = "MB_GROUP_CS30 (rw) register accessor: Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs30`] module"] +#[doc(alias = "MB_GROUP_CS30")] +pub type MbGroupCs30 = crate::Reg; +#[doc = "Message Buffer 30 CS Register"] +pub mod mb_group_cs30; +#[doc = "MB_16B_GROUP_MB20_16B_CS (rw) register accessor: Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_cs`] module"] +#[doc(alias = "MB_16B_GROUP_MB20_16B_CS")] +pub type Mb16bGroupMb20_16bCs = crate::Reg; +#[doc = "Message Buffer 20 CS Register"] +pub mod mb_16b_group_mb20_16b_cs; +#[doc = "MB_8B_GROUP_MB30_8B_CS (rw) register accessor: Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB30_8B_CS")] +pub type Mb8bGroupMb30_8bCs = crate::Reg; +#[doc = "Message Buffer 30 CS Register"] +pub mod mb_8b_group_mb30_8b_cs; +#[doc = "MB_64B_GROUP_MB6_64B_WORD10 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word10`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD10")] +pub type Mb64bGroupMb6_64bWord10 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word10; +#[doc = "MB_GROUP_ID30 (rw) register accessor: Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id30`] module"] +#[doc(alias = "MB_GROUP_ID30")] +pub type MbGroupId30 = crate::Reg; +#[doc = "Message Buffer 30 ID Register"] +pub mod mb_group_id30; +#[doc = "MB_16B_GROUP_MB20_16B_ID (rw) register accessor: Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_id`] module"] +#[doc(alias = "MB_16B_GROUP_MB20_16B_ID")] +pub type Mb16bGroupMb20_16bId = crate::Reg; +#[doc = "Message Buffer 20 ID Register"] +pub mod mb_16b_group_mb20_16b_id; +#[doc = "MB_8B_GROUP_MB30_8B_ID (rw) register accessor: Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB30_8B_ID")] +pub type Mb8bGroupMb30_8bId = crate::Reg; +#[doc = "Message Buffer 30 ID Register"] +pub mod mb_8b_group_mb30_8b_id; +#[doc = "MB_64B_GROUP_MB6_64B_WORD11 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word11`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD11")] +pub type Mb64bGroupMb6_64bWord11 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word11; +#[doc = "MB_16B_GROUP_MB20_16B_WORD0 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word0`] module"] +#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD0")] +pub type Mb16bGroupMb20_16bWord0 = + crate::Reg; +#[doc = "Message Buffer 20 WORD_16B Register"] +pub mod mb_16b_group_mb20_16b_word0; +#[doc = "MB_8B_GROUP_MB30_8B_WORD0 (rw) register accessor: Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB30_8B_WORD0")] +pub type Mb8bGroupMb30_8bWord0 = crate::Reg; +#[doc = "Message Buffer 30 WORD_8B Register"] +pub mod mb_8b_group_mb30_8b_word0; +#[doc = "MB_64B_GROUP_MB6_64B_WORD12 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word12`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD12")] +pub type Mb64bGroupMb6_64bWord12 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word12; +#[doc = "MB_GROUP_WORD030 (rw) register accessor: Message Buffer 30 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word030::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word030::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word030`] module"] +#[doc(alias = "MB_GROUP_WORD030")] +pub type MbGroupWord030 = crate::Reg; +#[doc = "Message Buffer 30 WORD0 Register"] +pub mod mb_group_word030; +#[doc = "MB_16B_GROUP_MB20_16B_WORD1 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word1`] module"] +#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD1")] +pub type Mb16bGroupMb20_16bWord1 = + crate::Reg; +#[doc = "Message Buffer 20 WORD_16B Register"] +pub mod mb_16b_group_mb20_16b_word1; +#[doc = "MB_8B_GROUP_MB30_8B_WORD1 (rw) register accessor: Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB30_8B_WORD1")] +pub type Mb8bGroupMb30_8bWord1 = crate::Reg; +#[doc = "Message Buffer 30 WORD_8B Register"] +pub mod mb_8b_group_mb30_8b_word1; +#[doc = "MB_64B_GROUP_MB6_64B_WORD13 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word13`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD13")] +pub type Mb64bGroupMb6_64bWord13 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word13; +#[doc = "MB_GROUP_WORD130 (rw) register accessor: Message Buffer 30 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word130::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word130::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word130`] module"] +#[doc(alias = "MB_GROUP_WORD130")] +pub type MbGroupWord130 = crate::Reg; +#[doc = "Message Buffer 30 WORD1 Register"] +pub mod mb_group_word130; +#[doc = "MB_GROUP_CS31 (rw) register accessor: Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs31`] module"] +#[doc(alias = "MB_GROUP_CS31")] +pub type MbGroupCs31 = crate::Reg; +#[doc = "Message Buffer 31 CS Register"] +pub mod mb_group_cs31; +#[doc = "MB_16B_GROUP_MB20_16B_WORD2 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word2`] module"] +#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD2")] +pub type Mb16bGroupMb20_16bWord2 = + crate::Reg; +#[doc = "Message Buffer 20 WORD_16B Register"] +pub mod mb_16b_group_mb20_16b_word2; +#[doc = "MB_8B_GROUP_MB31_8B_CS (rw) register accessor: Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_cs`] module"] +#[doc(alias = "MB_8B_GROUP_MB31_8B_CS")] +pub type Mb8bGroupMb31_8bCs = crate::Reg; +#[doc = "Message Buffer 31 CS Register"] +pub mod mb_8b_group_mb31_8b_cs; +#[doc = "MB_64B_GROUP_MB6_64B_WORD14 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word14`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD14")] +pub type Mb64bGroupMb6_64bWord14 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word14; +#[doc = "MB_GROUP_ID31 (rw) register accessor: Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id31`] module"] +#[doc(alias = "MB_GROUP_ID31")] +pub type MbGroupId31 = crate::Reg; +#[doc = "Message Buffer 31 ID Register"] +pub mod mb_group_id31; +#[doc = "MB_16B_GROUP_MB20_16B_WORD3 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word3`] module"] +#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD3")] +pub type Mb16bGroupMb20_16bWord3 = + crate::Reg; +#[doc = "Message Buffer 20 WORD_16B Register"] +pub mod mb_16b_group_mb20_16b_word3; +#[doc = "MB_8B_GROUP_MB31_8B_ID (rw) register accessor: Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_id`] module"] +#[doc(alias = "MB_8B_GROUP_MB31_8B_ID")] +pub type Mb8bGroupMb31_8bId = crate::Reg; +#[doc = "Message Buffer 31 ID Register"] +pub mod mb_8b_group_mb31_8b_id; +#[doc = "MB_64B_GROUP_MB6_64B_WORD15 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word15`] module"] +#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD15")] +pub type Mb64bGroupMb6_64bWord15 = + crate::Reg; +#[doc = "Message Buffer 6 WORD_64B Register"] +pub mod mb_64b_group_mb6_64b_word15; +#[doc = "MB_8B_GROUP_MB31_8B_WORD0 (rw) register accessor: Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_word0`] module"] +#[doc(alias = "MB_8B_GROUP_MB31_8B_WORD0")] +pub type Mb8bGroupMb31_8bWord0 = crate::Reg; +#[doc = "Message Buffer 31 WORD_8B Register"] +pub mod mb_8b_group_mb31_8b_word0; +#[doc = "MB_GROUP_WORD031 (rw) register accessor: Message Buffer 31 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word031::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word031::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word031`] module"] +#[doc(alias = "MB_GROUP_WORD031")] +pub type MbGroupWord031 = crate::Reg; +#[doc = "Message Buffer 31 WORD0 Register"] +pub mod mb_group_word031; +#[doc = "MB_8B_GROUP_MB31_8B_WORD1 (rw) register accessor: Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_word1`] module"] +#[doc(alias = "MB_8B_GROUP_MB31_8B_WORD1")] +pub type Mb8bGroupMb31_8bWord1 = crate::Reg; +#[doc = "Message Buffer 31 WORD_8B Register"] +pub mod mb_8b_group_mb31_8b_word1; +#[doc = "MB_GROUP_WORD131 (rw) register accessor: Message Buffer 31 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word131::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word131::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word131`] module"] +#[doc(alias = "MB_GROUP_WORD131")] +pub type MbGroupWord131 = crate::Reg; +#[doc = "Message Buffer 31 WORD1 Register"] +pub mod mb_group_word131; +#[doc = "RXIMR (rw) register accessor: Receive Individual Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rximr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rximr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rximr`] module"] +#[doc(alias = "RXIMR")] +pub type Rximr = crate::Reg; +#[doc = "Receive Individual Mask"] +pub mod rximr; +#[doc = "CTRL1_PN (rw) register accessor: Pretended Networking Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1_pn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1_pn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1_pn`] module"] +#[doc(alias = "CTRL1_PN")] +pub type Ctrl1Pn = crate::Reg; +#[doc = "Pretended Networking Control 1"] +pub mod ctrl1_pn; +#[doc = "CTRL2_PN (rw) register accessor: Pretended Networking Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2_pn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2_pn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2_pn`] module"] +#[doc(alias = "CTRL2_PN")] +pub type Ctrl2Pn = crate::Reg; +#[doc = "Pretended Networking Control 2"] +pub mod ctrl2_pn; +#[doc = "WU_MTC (rw) register accessor: Pretended Networking Wake-Up Match\n\nYou can [`read`](crate::Reg::read) this register and get [`wu_mtc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wu_mtc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wu_mtc`] module"] +#[doc(alias = "WU_MTC")] +pub type WuMtc = crate::Reg; +#[doc = "Pretended Networking Wake-Up Match"] +pub mod wu_mtc; +#[doc = "FLT_ID1 (rw) register accessor: Pretended Networking ID Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flt_id1`] module"] +#[doc(alias = "FLT_ID1")] +pub type FltId1 = crate::Reg; +#[doc = "Pretended Networking ID Filter 1"] +pub mod flt_id1; +#[doc = "FLT_DLC (rw) register accessor: Pretended Networking Data Length Code (DLC) Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_dlc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_dlc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flt_dlc`] module"] +#[doc(alias = "FLT_DLC")] +pub type FltDlc = crate::Reg; +#[doc = "Pretended Networking Data Length Code (DLC) Filter"] +pub mod flt_dlc; +#[doc = "PL1_LO (rw) register accessor: Pretended Networking Payload Low Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_lo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_lo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl1_lo`] module"] +#[doc(alias = "PL1_LO")] +pub type Pl1Lo = crate::Reg; +#[doc = "Pretended Networking Payload Low Filter 1"] +pub mod pl1_lo; +#[doc = "PL1_HI (rw) register accessor: Pretended Networking Payload High Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl1_hi`] module"] +#[doc(alias = "PL1_HI")] +pub type Pl1Hi = crate::Reg; +#[doc = "Pretended Networking Payload High Filter 1"] +pub mod pl1_hi; +#[doc = "FLT_ID2_IDMASK (rw) register accessor: Pretended Networking ID Filter 2 or ID Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id2_idmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id2_idmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flt_id2_idmask`] module"] +#[doc(alias = "FLT_ID2_IDMASK")] +pub type FltId2Idmask = crate::Reg; +#[doc = "Pretended Networking ID Filter 2 or ID Mask"] +pub mod flt_id2_idmask; +#[doc = "PL2_PLMASK_LO (rw) register accessor: Pretended Networking Payload Low Filter 2 and Payload Low Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_lo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_lo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl2_plmask_lo`] module"] +#[doc(alias = "PL2_PLMASK_LO")] +pub type Pl2PlmaskLo = crate::Reg; +#[doc = "Pretended Networking Payload Low Filter 2 and Payload Low Mask"] +pub mod pl2_plmask_lo; +#[doc = "PL2_PLMASK_HI (rw) register accessor: Pretended Networking Payload High Filter 2 and Payload High Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl2_plmask_hi`] module"] +#[doc(alias = "PL2_PLMASK_HI")] +pub type Pl2PlmaskHi = crate::Reg; +#[doc = "Pretended Networking Payload High Filter 2 and Payload High Mask"] +pub mod pl2_plmask_hi; +#[doc = "Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] +pub use self::wmb::Wmb; +#[doc = r"Cluster"] +#[doc = "Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] +pub mod wmb; +#[doc = "EPRS (rw) register accessor: Enhanced CAN Bit Timing Prescalers\n\nYou can [`read`](crate::Reg::read) this register and get [`eprs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eprs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eprs`] module"] +#[doc(alias = "EPRS")] +pub type Eprs = crate::Reg; +#[doc = "Enhanced CAN Bit Timing Prescalers"] +pub mod eprs; +#[doc = "ENCBT (rw) register accessor: Enhanced Nominal CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`encbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`encbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@encbt`] module"] +#[doc(alias = "ENCBT")] +pub type Encbt = crate::Reg; +#[doc = "Enhanced Nominal CAN Bit Timing"] +pub mod encbt; +#[doc = "EDCBT (rw) register accessor: Enhanced Data Phase CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`edcbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edcbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edcbt`] module"] +#[doc(alias = "EDCBT")] +pub type Edcbt = crate::Reg; +#[doc = "Enhanced Data Phase CAN Bit Timing"] +pub mod edcbt; +#[doc = "ETDC (rw) register accessor: Enhanced Transceiver Delay Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`etdc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etdc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etdc`] module"] +#[doc(alias = "ETDC")] +pub type Etdc = crate::Reg; +#[doc = "Enhanced Transceiver Delay Compensation"] +pub mod etdc; +#[doc = "FDCTRL (rw) register accessor: CAN FD Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fdctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdctrl`] module"] +#[doc(alias = "FDCTRL")] +pub type Fdctrl = crate::Reg; +#[doc = "CAN FD Control"] +pub mod fdctrl; +#[doc = "FDCBT (rw) register accessor: CAN FD Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdcbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdcbt`] module"] +#[doc(alias = "FDCBT")] +pub type Fdcbt = crate::Reg; +#[doc = "CAN FD Bit Timing"] +pub mod fdcbt; +#[doc = "FDCRC (r) register accessor: CAN FD CRC\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcrc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdcrc`] module"] +#[doc(alias = "FDCRC")] +pub type Fdcrc = crate::Reg; +#[doc = "CAN FD CRC"] +pub mod fdcrc; +#[doc = "ERFCR (rw) register accessor: Enhanced RX FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`erfcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erfcr`] module"] +#[doc(alias = "ERFCR")] +pub type Erfcr = crate::Reg; +#[doc = "Enhanced RX FIFO Control"] +pub mod erfcr; +#[doc = "ERFIER (rw) register accessor: Enhanced RX FIFO Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erfier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erfier`] module"] +#[doc(alias = "ERFIER")] +pub type Erfier = crate::Reg; +#[doc = "Enhanced RX FIFO Interrupt Enable"] +pub mod erfier; +#[doc = "ERFSR (rw) register accessor: Enhanced RX FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`erfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erfsr`] module"] +#[doc(alias = "ERFSR")] +pub type Erfsr = crate::Reg; +#[doc = "Enhanced RX FIFO Status"] +pub mod erfsr; +#[doc = "ERFFEL (rw) register accessor: Enhanced RX FIFO Filter Element\n\nYou can [`read`](crate::Reg::read) this register and get [`erffel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erffel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erffel`] module"] +#[doc(alias = "ERFFEL")] +pub type Erffel = crate::Reg; +#[doc = "Enhanced RX FIFO Filter Element"] +pub mod erffel; diff --git a/mcxa276-pac/src/can0/cbt.rs b/mcxa276-pac/src/can0/cbt.rs new file mode 100644 index 000000000..674a3e036 --- /dev/null +++ b/mcxa276-pac/src/can0/cbt.rs @@ -0,0 +1,154 @@ +#[doc = "Register `CBT` reader"] +pub type R = crate::R; +#[doc = "Register `CBT` writer"] +pub type W = crate::W; +#[doc = "Field `EPSEG2` reader - Extended Phase Segment 2"] +pub type Epseg2R = crate::FieldReader; +#[doc = "Field `EPSEG2` writer - Extended Phase Segment 2"] +pub type Epseg2W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `EPSEG1` reader - Extended Phase Segment 1"] +pub type Epseg1R = crate::FieldReader; +#[doc = "Field `EPSEG1` writer - Extended Phase Segment 1"] +pub type Epseg1W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `EPROPSEG` reader - Extended Propagation Segment"] +pub type EpropsegR = crate::FieldReader; +#[doc = "Field `EPROPSEG` writer - Extended Propagation Segment"] +pub type EpropsegW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ERJW` reader - Extended Resync Jump Width"] +pub type ErjwR = crate::FieldReader; +#[doc = "Field `ERJW` writer - Extended Resync Jump Width"] +pub type ErjwW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `EPRESDIV` reader - Extended Prescaler Division Factor"] +pub type EpresdivR = crate::FieldReader; +#[doc = "Field `EPRESDIV` writer - Extended Prescaler Division Factor"] +pub type EpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Bit Timing Format Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Btf { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Btf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BTF` reader - Bit Timing Format Enable"] +pub type BtfR = crate::BitReader; +impl BtfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Btf { + match self.bits { + false => Btf::Disable, + true => Btf::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Btf::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Btf::Enable + } +} +#[doc = "Field `BTF` writer - Bit Timing Format Enable"] +pub type BtfW<'a, REG> = crate::BitWriter<'a, REG, Btf>; +impl<'a, REG> BtfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Btf::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Btf::Enable) + } +} +impl R { + #[doc = "Bits 0:4 - Extended Phase Segment 2"] + #[inline(always)] + pub fn epseg2(&self) -> Epseg2R { + Epseg2R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - Extended Phase Segment 1"] + #[inline(always)] + pub fn epseg1(&self) -> Epseg1R { + Epseg1R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:15 - Extended Propagation Segment"] + #[inline(always)] + pub fn epropseg(&self) -> EpropsegR { + EpropsegR::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:20 - Extended Resync Jump Width"] + #[inline(always)] + pub fn erjw(&self) -> ErjwR { + ErjwR::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:30 - Extended Prescaler Division Factor"] + #[inline(always)] + pub fn epresdiv(&self) -> EpresdivR { + EpresdivR::new(((self.bits >> 21) & 0x03ff) as u16) + } + #[doc = "Bit 31 - Bit Timing Format Enable"] + #[inline(always)] + pub fn btf(&self) -> BtfR { + BtfR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Extended Phase Segment 2"] + #[inline(always)] + pub fn epseg2(&mut self) -> Epseg2W { + Epseg2W::new(self, 0) + } + #[doc = "Bits 5:9 - Extended Phase Segment 1"] + #[inline(always)] + pub fn epseg1(&mut self) -> Epseg1W { + Epseg1W::new(self, 5) + } + #[doc = "Bits 10:15 - Extended Propagation Segment"] + #[inline(always)] + pub fn epropseg(&mut self) -> EpropsegW { + EpropsegW::new(self, 10) + } + #[doc = "Bits 16:20 - Extended Resync Jump Width"] + #[inline(always)] + pub fn erjw(&mut self) -> ErjwW { + ErjwW::new(self, 16) + } + #[doc = "Bits 21:30 - Extended Prescaler Division Factor"] + #[inline(always)] + pub fn epresdiv(&mut self) -> EpresdivW { + EpresdivW::new(self, 21) + } + #[doc = "Bit 31 - Bit Timing Format Enable"] + #[inline(always)] + pub fn btf(&mut self) -> BtfW { + BtfW::new(self, 31) + } +} +#[doc = "CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`cbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CbtSpec; +impl crate::RegisterSpec for CbtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cbt::R`](R) reader structure"] +impl crate::Readable for CbtSpec {} +#[doc = "`write(|w| ..)` method takes [`cbt::W`](W) writer structure"] +impl crate::Writable for CbtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CBT to value 0"] +impl crate::Resettable for CbtSpec {} diff --git a/mcxa276-pac/src/can0/crcr.rs b/mcxa276-pac/src/can0/crcr.rs new file mode 100644 index 000000000..1a5388f16 --- /dev/null +++ b/mcxa276-pac/src/can0/crcr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CRCR` reader"] +pub type R = crate::R; +#[doc = "Field `TXCRC` reader - Transmitted CRC value"] +pub type TxcrcR = crate::FieldReader; +#[doc = "Field `MBCRC` reader - CRC Message Buffer"] +pub type MbcrcR = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - Transmitted CRC value"] + #[inline(always)] + pub fn txcrc(&self) -> TxcrcR { + TxcrcR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bits 16:22 - CRC Message Buffer"] + #[inline(always)] + pub fn mbcrc(&self) -> MbcrcR { + MbcrcR::new(((self.bits >> 16) & 0x7f) as u8) + } +} +#[doc = "Cyclic Redundancy Check\n\nYou can [`read`](crate::Reg::read) this register and get [`crcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrcrSpec; +impl crate::RegisterSpec for CrcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`crcr::R`](R) reader structure"] +impl crate::Readable for CrcrSpec {} +#[doc = "`reset()` method sets CRCR to value 0"] +impl crate::Resettable for CrcrSpec {} diff --git a/mcxa276-pac/src/can0/ctrl1.rs b/mcxa276-pac/src/can0/ctrl1.rs new file mode 100644 index 000000000..02c6ef133 --- /dev/null +++ b/mcxa276-pac/src/can0/ctrl1.rs @@ -0,0 +1,721 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `PROPSEG` reader - Propagation Segment"] +pub type PropsegR = crate::FieldReader; +#[doc = "Field `PROPSEG` writer - Propagation Segment"] +pub type PropsegW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Listen-Only Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lom { + #[doc = "0: Listen-Only mode is deactivated."] + ListenOnlyModeDisabled = 0, + #[doc = "1: FlexCAN module operates in Listen-Only mode."] + ListenOnlyModeEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lom) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOM` reader - Listen-Only Mode"] +pub type LomR = crate::BitReader; +impl LomR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lom { + match self.bits { + false => Lom::ListenOnlyModeDisabled, + true => Lom::ListenOnlyModeEnabled, + } + } + #[doc = "Listen-Only mode is deactivated."] + #[inline(always)] + pub fn is_listen_only_mode_disabled(&self) -> bool { + *self == Lom::ListenOnlyModeDisabled + } + #[doc = "FlexCAN module operates in Listen-Only mode."] + #[inline(always)] + pub fn is_listen_only_mode_enabled(&self) -> bool { + *self == Lom::ListenOnlyModeEnabled + } +} +#[doc = "Field `LOM` writer - Listen-Only Mode"] +pub type LomW<'a, REG> = crate::BitWriter<'a, REG, Lom>; +impl<'a, REG> LomW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Listen-Only mode is deactivated."] + #[inline(always)] + pub fn listen_only_mode_disabled(self) -> &'a mut crate::W { + self.variant(Lom::ListenOnlyModeDisabled) + } + #[doc = "FlexCAN module operates in Listen-Only mode."] + #[inline(always)] + pub fn listen_only_mode_enabled(self) -> &'a mut crate::W { + self.variant(Lom::ListenOnlyModeEnabled) + } +} +#[doc = "Lowest Buffer Transmitted First\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lbuf { + #[doc = "0: Buffer with highest priority is transmitted first."] + HighestBufferFirst = 0, + #[doc = "1: Lowest number buffer is transmitted first."] + LowestBufferFirst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lbuf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LBUF` reader - Lowest Buffer Transmitted First"] +pub type LbufR = crate::BitReader; +impl LbufR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lbuf { + match self.bits { + false => Lbuf::HighestBufferFirst, + true => Lbuf::LowestBufferFirst, + } + } + #[doc = "Buffer with highest priority is transmitted first."] + #[inline(always)] + pub fn is_highest_buffer_first(&self) -> bool { + *self == Lbuf::HighestBufferFirst + } + #[doc = "Lowest number buffer is transmitted first."] + #[inline(always)] + pub fn is_lowest_buffer_first(&self) -> bool { + *self == Lbuf::LowestBufferFirst + } +} +#[doc = "Field `LBUF` writer - Lowest Buffer Transmitted First"] +pub type LbufW<'a, REG> = crate::BitWriter<'a, REG, Lbuf>; +impl<'a, REG> LbufW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Buffer with highest priority is transmitted first."] + #[inline(always)] + pub fn highest_buffer_first(self) -> &'a mut crate::W { + self.variant(Lbuf::HighestBufferFirst) + } + #[doc = "Lowest number buffer is transmitted first."] + #[inline(always)] + pub fn lowest_buffer_first(self) -> &'a mut crate::W { + self.variant(Lbuf::LowestBufferFirst) + } +} +#[doc = "Timer Sync\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tsyn { + #[doc = "0: Disable"] + TimerSyncDisabled = 0, + #[doc = "1: Enable"] + TimerSyncEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tsyn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TSYN` reader - Timer Sync"] +pub type TsynR = crate::BitReader; +impl TsynR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tsyn { + match self.bits { + false => Tsyn::TimerSyncDisabled, + true => Tsyn::TimerSyncEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_timer_sync_disabled(&self) -> bool { + *self == Tsyn::TimerSyncDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_timer_sync_enabled(&self) -> bool { + *self == Tsyn::TimerSyncEnabled + } +} +#[doc = "Field `TSYN` writer - Timer Sync"] +pub type TsynW<'a, REG> = crate::BitWriter<'a, REG, Tsyn>; +impl<'a, REG> TsynW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn timer_sync_disabled(self) -> &'a mut crate::W { + self.variant(Tsyn::TimerSyncDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn timer_sync_enabled(self) -> &'a mut crate::W { + self.variant(Tsyn::TimerSyncEnabled) + } +} +#[doc = "Bus Off Recovery\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Boffrec { + #[doc = "0: Enabled"] + AutoRecoverEnabled = 0, + #[doc = "1: Disabled"] + AutoRecoverDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Boffrec) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOFFREC` reader - Bus Off Recovery"] +pub type BoffrecR = crate::BitReader; +impl BoffrecR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Boffrec { + match self.bits { + false => Boffrec::AutoRecoverEnabled, + true => Boffrec::AutoRecoverDisabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_auto_recover_enabled(&self) -> bool { + *self == Boffrec::AutoRecoverEnabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_auto_recover_disabled(&self) -> bool { + *self == Boffrec::AutoRecoverDisabled + } +} +#[doc = "Field `BOFFREC` writer - Bus Off Recovery"] +pub type BoffrecW<'a, REG> = crate::BitWriter<'a, REG, Boffrec>; +impl<'a, REG> BoffrecW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn auto_recover_enabled(self) -> &'a mut crate::W { + self.variant(Boffrec::AutoRecoverEnabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn auto_recover_disabled(self) -> &'a mut crate::W { + self.variant(Boffrec::AutoRecoverDisabled) + } +} +#[doc = "CAN Bit Sampling\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Smp { + #[doc = "0: One sample is used to determine the bit value."] + OneSample = 0, + #[doc = "1: Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples. A majority rule is used."] + ThreeSample = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Smp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SMP` reader - CAN Bit Sampling"] +pub type SmpR = crate::BitReader; +impl SmpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Smp { + match self.bits { + false => Smp::OneSample, + true => Smp::ThreeSample, + } + } + #[doc = "One sample is used to determine the bit value."] + #[inline(always)] + pub fn is_one_sample(&self) -> bool { + *self == Smp::OneSample + } + #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples. A majority rule is used."] + #[inline(always)] + pub fn is_three_sample(&self) -> bool { + *self == Smp::ThreeSample + } +} +#[doc = "Field `SMP` writer - CAN Bit Sampling"] +pub type SmpW<'a, REG> = crate::BitWriter<'a, REG, Smp>; +impl<'a, REG> SmpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "One sample is used to determine the bit value."] + #[inline(always)] + pub fn one_sample(self) -> &'a mut crate::W { + self.variant(Smp::OneSample) + } + #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples. A majority rule is used."] + #[inline(always)] + pub fn three_sample(self) -> &'a mut crate::W { + self.variant(Smp::ThreeSample) + } +} +#[doc = "RX Warning Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rwrnmsk { + #[doc = "0: Disabled"] + RxWarningIntDisabled = 0, + #[doc = "1: Enabled"] + RxWarningIntEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rwrnmsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RWRNMSK` reader - RX Warning Interrupt Mask"] +pub type RwrnmskR = crate::BitReader; +impl RwrnmskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rwrnmsk { + match self.bits { + false => Rwrnmsk::RxWarningIntDisabled, + true => Rwrnmsk::RxWarningIntEnabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_rx_warning_int_disabled(&self) -> bool { + *self == Rwrnmsk::RxWarningIntDisabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_rx_warning_int_enabled(&self) -> bool { + *self == Rwrnmsk::RxWarningIntEnabled + } +} +#[doc = "Field `RWRNMSK` writer - RX Warning Interrupt Mask"] +pub type RwrnmskW<'a, REG> = crate::BitWriter<'a, REG, Rwrnmsk>; +impl<'a, REG> RwrnmskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn rx_warning_int_disabled(self) -> &'a mut crate::W { + self.variant(Rwrnmsk::RxWarningIntDisabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn rx_warning_int_enabled(self) -> &'a mut crate::W { + self.variant(Rwrnmsk::RxWarningIntEnabled) + } +} +#[doc = "TX Warning Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Twrnmsk { + #[doc = "0: Disabled"] + TxWarningIntDisabled = 0, + #[doc = "1: Enabled"] + TxWarningIntEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Twrnmsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TWRNMSK` reader - TX Warning Interrupt Mask"] +pub type TwrnmskR = crate::BitReader; +impl TwrnmskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Twrnmsk { + match self.bits { + false => Twrnmsk::TxWarningIntDisabled, + true => Twrnmsk::TxWarningIntEnabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_tx_warning_int_disabled(&self) -> bool { + *self == Twrnmsk::TxWarningIntDisabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_tx_warning_int_enabled(&self) -> bool { + *self == Twrnmsk::TxWarningIntEnabled + } +} +#[doc = "Field `TWRNMSK` writer - TX Warning Interrupt Mask"] +pub type TwrnmskW<'a, REG> = crate::BitWriter<'a, REG, Twrnmsk>; +impl<'a, REG> TwrnmskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn tx_warning_int_disabled(self) -> &'a mut crate::W { + self.variant(Twrnmsk::TxWarningIntDisabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn tx_warning_int_enabled(self) -> &'a mut crate::W { + self.variant(Twrnmsk::TxWarningIntEnabled) + } +} +#[doc = "Loopback Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpb { + #[doc = "0: Disabled"] + LoopbackDisabled = 0, + #[doc = "1: Enabled"] + LoopbackEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPB` reader - Loopback Mode"] +pub type LpbR = crate::BitReader; +impl LpbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpb { + match self.bits { + false => Lpb::LoopbackDisabled, + true => Lpb::LoopbackEnabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_loopback_disabled(&self) -> bool { + *self == Lpb::LoopbackDisabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_loopback_enabled(&self) -> bool { + *self == Lpb::LoopbackEnabled + } +} +#[doc = "Field `LPB` writer - Loopback Mode"] +pub type LpbW<'a, REG> = crate::BitWriter<'a, REG, Lpb>; +impl<'a, REG> LpbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn loopback_disabled(self) -> &'a mut crate::W { + self.variant(Lpb::LoopbackDisabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn loopback_enabled(self) -> &'a mut crate::W { + self.variant(Lpb::LoopbackEnabled) + } +} +#[doc = "Error Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errmsk { + #[doc = "0: Interrupt disabled"] + ErrorIntDisabled = 0, + #[doc = "1: Interrupt enabled"] + ErrorIntEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errmsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRMSK` reader - Error Interrupt Mask"] +pub type ErrmskR = crate::BitReader; +impl ErrmskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errmsk { + match self.bits { + false => Errmsk::ErrorIntDisabled, + true => Errmsk::ErrorIntEnabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_error_int_disabled(&self) -> bool { + *self == Errmsk::ErrorIntDisabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_error_int_enabled(&self) -> bool { + *self == Errmsk::ErrorIntEnabled + } +} +#[doc = "Field `ERRMSK` writer - Error Interrupt Mask"] +pub type ErrmskW<'a, REG> = crate::BitWriter<'a, REG, Errmsk>; +impl<'a, REG> ErrmskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn error_int_disabled(self) -> &'a mut crate::W { + self.variant(Errmsk::ErrorIntDisabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn error_int_enabled(self) -> &'a mut crate::W { + self.variant(Errmsk::ErrorIntEnabled) + } +} +#[doc = "Bus Off Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Boffmsk { + #[doc = "0: Interrupt disabled"] + BusOffIntDisabled = 0, + #[doc = "1: Interrupt enabled"] + BusOffIntEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Boffmsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOFFMSK` reader - Bus Off Interrupt Mask"] +pub type BoffmskR = crate::BitReader; +impl BoffmskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Boffmsk { + match self.bits { + false => Boffmsk::BusOffIntDisabled, + true => Boffmsk::BusOffIntEnabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_bus_off_int_disabled(&self) -> bool { + *self == Boffmsk::BusOffIntDisabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_bus_off_int_enabled(&self) -> bool { + *self == Boffmsk::BusOffIntEnabled + } +} +#[doc = "Field `BOFFMSK` writer - Bus Off Interrupt Mask"] +pub type BoffmskW<'a, REG> = crate::BitWriter<'a, REG, Boffmsk>; +impl<'a, REG> BoffmskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn bus_off_int_disabled(self) -> &'a mut crate::W { + self.variant(Boffmsk::BusOffIntDisabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn bus_off_int_enabled(self) -> &'a mut crate::W { + self.variant(Boffmsk::BusOffIntEnabled) + } +} +#[doc = "Field `PSEG2` reader - Phase Segment 2"] +pub type Pseg2R = crate::FieldReader; +#[doc = "Field `PSEG2` writer - Phase Segment 2"] +pub type Pseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `PSEG1` reader - Phase Segment 1"] +pub type Pseg1R = crate::FieldReader; +#[doc = "Field `PSEG1` writer - Phase Segment 1"] +pub type Pseg1W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `RJW` reader - Resync Jump Width"] +pub type RjwR = crate::FieldReader; +#[doc = "Field `RJW` writer - Resync Jump Width"] +pub type RjwW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PRESDIV` reader - Prescaler Division Factor"] +pub type PresdivR = crate::FieldReader; +#[doc = "Field `PRESDIV` writer - Prescaler Division Factor"] +pub type PresdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:2 - Propagation Segment"] + #[inline(always)] + pub fn propseg(&self) -> PropsegR { + PropsegR::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Listen-Only Mode"] + #[inline(always)] + pub fn lom(&self) -> LomR { + LomR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Lowest Buffer Transmitted First"] + #[inline(always)] + pub fn lbuf(&self) -> LbufR { + LbufR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Timer Sync"] + #[inline(always)] + pub fn tsyn(&self) -> TsynR { + TsynR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Bus Off Recovery"] + #[inline(always)] + pub fn boffrec(&self) -> BoffrecR { + BoffrecR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CAN Bit Sampling"] + #[inline(always)] + pub fn smp(&self) -> SmpR { + SmpR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - RX Warning Interrupt Mask"] + #[inline(always)] + pub fn rwrnmsk(&self) -> RwrnmskR { + RwrnmskR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TX Warning Interrupt Mask"] + #[inline(always)] + pub fn twrnmsk(&self) -> TwrnmskR { + TwrnmskR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + pub fn lpb(&self) -> LpbR { + LpbR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - Error Interrupt Mask"] + #[inline(always)] + pub fn errmsk(&self) -> ErrmskR { + ErrmskR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Bus Off Interrupt Mask"] + #[inline(always)] + pub fn boffmsk(&self) -> BoffmskR { + BoffmskR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Phase Segment 2"] + #[inline(always)] + pub fn pseg2(&self) -> Pseg2R { + Pseg2R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - Phase Segment 1"] + #[inline(always)] + pub fn pseg1(&self) -> Pseg1R { + Pseg1R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:23 - Resync Jump Width"] + #[inline(always)] + pub fn rjw(&self) -> RjwR { + RjwR::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:31 - Prescaler Division Factor"] + #[inline(always)] + pub fn presdiv(&self) -> PresdivR { + PresdivR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Propagation Segment"] + #[inline(always)] + pub fn propseg(&mut self) -> PropsegW { + PropsegW::new(self, 0) + } + #[doc = "Bit 3 - Listen-Only Mode"] + #[inline(always)] + pub fn lom(&mut self) -> LomW { + LomW::new(self, 3) + } + #[doc = "Bit 4 - Lowest Buffer Transmitted First"] + #[inline(always)] + pub fn lbuf(&mut self) -> LbufW { + LbufW::new(self, 4) + } + #[doc = "Bit 5 - Timer Sync"] + #[inline(always)] + pub fn tsyn(&mut self) -> TsynW { + TsynW::new(self, 5) + } + #[doc = "Bit 6 - Bus Off Recovery"] + #[inline(always)] + pub fn boffrec(&mut self) -> BoffrecW { + BoffrecW::new(self, 6) + } + #[doc = "Bit 7 - CAN Bit Sampling"] + #[inline(always)] + pub fn smp(&mut self) -> SmpW { + SmpW::new(self, 7) + } + #[doc = "Bit 10 - RX Warning Interrupt Mask"] + #[inline(always)] + pub fn rwrnmsk(&mut self) -> RwrnmskW { + RwrnmskW::new(self, 10) + } + #[doc = "Bit 11 - TX Warning Interrupt Mask"] + #[inline(always)] + pub fn twrnmsk(&mut self) -> TwrnmskW { + TwrnmskW::new(self, 11) + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + pub fn lpb(&mut self) -> LpbW { + LpbW::new(self, 12) + } + #[doc = "Bit 14 - Error Interrupt Mask"] + #[inline(always)] + pub fn errmsk(&mut self) -> ErrmskW { + ErrmskW::new(self, 14) + } + #[doc = "Bit 15 - Bus Off Interrupt Mask"] + #[inline(always)] + pub fn boffmsk(&mut self) -> BoffmskW { + BoffmskW::new(self, 15) + } + #[doc = "Bits 16:18 - Phase Segment 2"] + #[inline(always)] + pub fn pseg2(&mut self) -> Pseg2W { + Pseg2W::new(self, 16) + } + #[doc = "Bits 19:21 - Phase Segment 1"] + #[inline(always)] + pub fn pseg1(&mut self) -> Pseg1W { + Pseg1W::new(self, 19) + } + #[doc = "Bits 22:23 - Resync Jump Width"] + #[inline(always)] + pub fn rjw(&mut self) -> RjwW { + RjwW::new(self, 22) + } + #[doc = "Bits 24:31 - Prescaler Division Factor"] + #[inline(always)] + pub fn presdiv(&mut self) -> PresdivW { + PresdivW::new(self, 24) + } +} +#[doc = "Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec {} diff --git a/mcxa276-pac/src/can0/ctrl1_pn.rs b/mcxa276-pac/src/can0/ctrl1_pn.rs new file mode 100644 index 000000000..d583247f9 --- /dev/null +++ b/mcxa276-pac/src/can0/ctrl1_pn.rs @@ -0,0 +1,520 @@ +#[doc = "Register `CTRL1_PN` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1_PN` writer"] +pub type W = crate::W; +#[doc = "Filtering Combination Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fcs { + #[doc = "0: Message ID filtering only"] + IdFiltering = 0, + #[doc = "1: Message ID filtering and payload filtering"] + IdPayloadFiltering = 1, + #[doc = "2: Message ID filtering occurring a specified number of times"] + IdFilteringNumber = 2, + #[doc = "3: Message ID filtering and payload filtering a specified number of times"] + IdPayloadFilteringNumber = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fcs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fcs { + type Ux = u8; +} +impl crate::IsEnum for Fcs {} +#[doc = "Field `FCS` reader - Filtering Combination Selection"] +pub type FcsR = crate::FieldReader; +impl FcsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fcs { + match self.bits { + 0 => Fcs::IdFiltering, + 1 => Fcs::IdPayloadFiltering, + 2 => Fcs::IdFilteringNumber, + 3 => Fcs::IdPayloadFilteringNumber, + _ => unreachable!(), + } + } + #[doc = "Message ID filtering only"] + #[inline(always)] + pub fn is_id_filtering(&self) -> bool { + *self == Fcs::IdFiltering + } + #[doc = "Message ID filtering and payload filtering"] + #[inline(always)] + pub fn is_id_payload_filtering(&self) -> bool { + *self == Fcs::IdPayloadFiltering + } + #[doc = "Message ID filtering occurring a specified number of times"] + #[inline(always)] + pub fn is_id_filtering_number(&self) -> bool { + *self == Fcs::IdFilteringNumber + } + #[doc = "Message ID filtering and payload filtering a specified number of times"] + #[inline(always)] + pub fn is_id_payload_filtering_number(&self) -> bool { + *self == Fcs::IdPayloadFilteringNumber + } +} +#[doc = "Field `FCS` writer - Filtering Combination Selection"] +pub type FcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Fcs, crate::Safe>; +impl<'a, REG> FcsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Message ID filtering only"] + #[inline(always)] + pub fn id_filtering(self) -> &'a mut crate::W { + self.variant(Fcs::IdFiltering) + } + #[doc = "Message ID filtering and payload filtering"] + #[inline(always)] + pub fn id_payload_filtering(self) -> &'a mut crate::W { + self.variant(Fcs::IdPayloadFiltering) + } + #[doc = "Message ID filtering occurring a specified number of times"] + #[inline(always)] + pub fn id_filtering_number(self) -> &'a mut crate::W { + self.variant(Fcs::IdFilteringNumber) + } + #[doc = "Message ID filtering and payload filtering a specified number of times"] + #[inline(always)] + pub fn id_payload_filtering_number(self) -> &'a mut crate::W { + self.variant(Fcs::IdPayloadFilteringNumber) + } +} +#[doc = "ID Filtering Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Idfs { + #[doc = "0: Match ID contents to an exact target value"] + MatchExact = 0, + #[doc = "1: Match an ID value greater than or equal to a specified target value"] + MatchGte = 1, + #[doc = "2: Match an ID value smaller than or equal to a specified target value"] + MatchLte = 2, + #[doc = "3: Match an ID value within a range of values, inclusive"] + MatchRange = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Idfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Idfs { + type Ux = u8; +} +impl crate::IsEnum for Idfs {} +#[doc = "Field `IDFS` reader - ID Filtering Selection"] +pub type IdfsR = crate::FieldReader; +impl IdfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Idfs { + match self.bits { + 0 => Idfs::MatchExact, + 1 => Idfs::MatchGte, + 2 => Idfs::MatchLte, + 3 => Idfs::MatchRange, + _ => unreachable!(), + } + } + #[doc = "Match ID contents to an exact target value"] + #[inline(always)] + pub fn is_match_exact(&self) -> bool { + *self == Idfs::MatchExact + } + #[doc = "Match an ID value greater than or equal to a specified target value"] + #[inline(always)] + pub fn is_match_gte(&self) -> bool { + *self == Idfs::MatchGte + } + #[doc = "Match an ID value smaller than or equal to a specified target value"] + #[inline(always)] + pub fn is_match_lte(&self) -> bool { + *self == Idfs::MatchLte + } + #[doc = "Match an ID value within a range of values, inclusive"] + #[inline(always)] + pub fn is_match_range(&self) -> bool { + *self == Idfs::MatchRange + } +} +#[doc = "Field `IDFS` writer - ID Filtering Selection"] +pub type IdfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Idfs, crate::Safe>; +impl<'a, REG> IdfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Match ID contents to an exact target value"] + #[inline(always)] + pub fn match_exact(self) -> &'a mut crate::W { + self.variant(Idfs::MatchExact) + } + #[doc = "Match an ID value greater than or equal to a specified target value"] + #[inline(always)] + pub fn match_gte(self) -> &'a mut crate::W { + self.variant(Idfs::MatchGte) + } + #[doc = "Match an ID value smaller than or equal to a specified target value"] + #[inline(always)] + pub fn match_lte(self) -> &'a mut crate::W { + self.variant(Idfs::MatchLte) + } + #[doc = "Match an ID value within a range of values, inclusive"] + #[inline(always)] + pub fn match_range(self) -> &'a mut crate::W { + self.variant(Idfs::MatchRange) + } +} +#[doc = "Payload Filtering Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Plfs { + #[doc = "0: Match payload contents to an exact target value"] + MatchExact = 0, + #[doc = "1: Match a payload value greater than or equal to a specified target value"] + MatchGte = 1, + #[doc = "2: Match a payload value smaller than or equal to a specified target value"] + MatchLte = 2, + #[doc = "3: Match upon a payload value within a range of values, inclusive"] + MatchRange = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Plfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Plfs { + type Ux = u8; +} +impl crate::IsEnum for Plfs {} +#[doc = "Field `PLFS` reader - Payload Filtering Selection"] +pub type PlfsR = crate::FieldReader; +impl PlfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Plfs { + match self.bits { + 0 => Plfs::MatchExact, + 1 => Plfs::MatchGte, + 2 => Plfs::MatchLte, + 3 => Plfs::MatchRange, + _ => unreachable!(), + } + } + #[doc = "Match payload contents to an exact target value"] + #[inline(always)] + pub fn is_match_exact(&self) -> bool { + *self == Plfs::MatchExact + } + #[doc = "Match a payload value greater than or equal to a specified target value"] + #[inline(always)] + pub fn is_match_gte(&self) -> bool { + *self == Plfs::MatchGte + } + #[doc = "Match a payload value smaller than or equal to a specified target value"] + #[inline(always)] + pub fn is_match_lte(&self) -> bool { + *self == Plfs::MatchLte + } + #[doc = "Match upon a payload value within a range of values, inclusive"] + #[inline(always)] + pub fn is_match_range(&self) -> bool { + *self == Plfs::MatchRange + } +} +#[doc = "Field `PLFS` writer - Payload Filtering Selection"] +pub type PlfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Plfs, crate::Safe>; +impl<'a, REG> PlfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Match payload contents to an exact target value"] + #[inline(always)] + pub fn match_exact(self) -> &'a mut crate::W { + self.variant(Plfs::MatchExact) + } + #[doc = "Match a payload value greater than or equal to a specified target value"] + #[inline(always)] + pub fn match_gte(self) -> &'a mut crate::W { + self.variant(Plfs::MatchGte) + } + #[doc = "Match a payload value smaller than or equal to a specified target value"] + #[inline(always)] + pub fn match_lte(self) -> &'a mut crate::W { + self.variant(Plfs::MatchLte) + } + #[doc = "Match upon a payload value within a range of values, inclusive"] + #[inline(always)] + pub fn match_range(self) -> &'a mut crate::W { + self.variant(Plfs::MatchRange) + } +} +#[doc = "Number of Messages Matching the Same Filtering Criteria\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Nmatch { + #[doc = "1: Once"] + Match1 = 1, + #[doc = "2: Twice"] + Match2 = 2, + #[doc = "255: 255 times"] + Match255 = 255, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Nmatch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Nmatch { + type Ux = u8; +} +impl crate::IsEnum for Nmatch {} +#[doc = "Field `NMATCH` reader - Number of Messages Matching the Same Filtering Criteria"] +pub type NmatchR = crate::FieldReader; +impl NmatchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Nmatch::Match1), + 2 => Some(Nmatch::Match2), + 255 => Some(Nmatch::Match255), + _ => None, + } + } + #[doc = "Once"] + #[inline(always)] + pub fn is_match_1(&self) -> bool { + *self == Nmatch::Match1 + } + #[doc = "Twice"] + #[inline(always)] + pub fn is_match_2(&self) -> bool { + *self == Nmatch::Match2 + } + #[doc = "255 times"] + #[inline(always)] + pub fn is_match_255(&self) -> bool { + *self == Nmatch::Match255 + } +} +#[doc = "Field `NMATCH` writer - Number of Messages Matching the Same Filtering Criteria"] +pub type NmatchW<'a, REG> = crate::FieldWriter<'a, REG, 8, Nmatch>; +impl<'a, REG> NmatchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Once"] + #[inline(always)] + pub fn match_1(self) -> &'a mut crate::W { + self.variant(Nmatch::Match1) + } + #[doc = "Twice"] + #[inline(always)] + pub fn match_2(self) -> &'a mut crate::W { + self.variant(Nmatch::Match2) + } + #[doc = "255 times"] + #[inline(always)] + pub fn match_255(self) -> &'a mut crate::W { + self.variant(Nmatch::Match255) + } +} +#[doc = "Wake-up by Matching Flag Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WumfMsk { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WumfMsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUMF_MSK` reader - Wake-up by Matching Flag Mask"] +pub type WumfMskR = crate::BitReader; +impl WumfMskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WumfMsk { + match self.bits { + false => WumfMsk::Disable, + true => WumfMsk::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WumfMsk::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == WumfMsk::Enable + } +} +#[doc = "Field `WUMF_MSK` writer - Wake-up by Matching Flag Mask"] +pub type WumfMskW<'a, REG> = crate::BitWriter<'a, REG, WumfMsk>; +impl<'a, REG> WumfMskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(WumfMsk::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(WumfMsk::Enable) + } +} +#[doc = "Wake-up by Timeout Flag Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WtofMsk { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WtofMsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WTOF_MSK` reader - Wake-up by Timeout Flag Mask"] +pub type WtofMskR = crate::BitReader; +impl WtofMskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WtofMsk { + match self.bits { + false => WtofMsk::Disable, + true => WtofMsk::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WtofMsk::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == WtofMsk::Enable + } +} +#[doc = "Field `WTOF_MSK` writer - Wake-up by Timeout Flag Mask"] +pub type WtofMskW<'a, REG> = crate::BitWriter<'a, REG, WtofMsk>; +impl<'a, REG> WtofMskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(WtofMsk::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(WtofMsk::Enable) + } +} +impl R { + #[doc = "Bits 0:1 - Filtering Combination Selection"] + #[inline(always)] + pub fn fcs(&self) -> FcsR { + FcsR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - ID Filtering Selection"] + #[inline(always)] + pub fn idfs(&self) -> IdfsR { + IdfsR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Payload Filtering Selection"] + #[inline(always)] + pub fn plfs(&self) -> PlfsR { + PlfsR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Number of Messages Matching the Same Filtering Criteria"] + #[inline(always)] + pub fn nmatch(&self) -> NmatchR { + NmatchR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - Wake-up by Matching Flag Mask"] + #[inline(always)] + pub fn wumf_msk(&self) -> WumfMskR { + WumfMskR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Wake-up by Timeout Flag Mask"] + #[inline(always)] + pub fn wtof_msk(&self) -> WtofMskR { + WtofMskR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Filtering Combination Selection"] + #[inline(always)] + pub fn fcs(&mut self) -> FcsW { + FcsW::new(self, 0) + } + #[doc = "Bits 2:3 - ID Filtering Selection"] + #[inline(always)] + pub fn idfs(&mut self) -> IdfsW { + IdfsW::new(self, 2) + } + #[doc = "Bits 4:5 - Payload Filtering Selection"] + #[inline(always)] + pub fn plfs(&mut self) -> PlfsW { + PlfsW::new(self, 4) + } + #[doc = "Bits 8:15 - Number of Messages Matching the Same Filtering Criteria"] + #[inline(always)] + pub fn nmatch(&mut self) -> NmatchW { + NmatchW::new(self, 8) + } + #[doc = "Bit 16 - Wake-up by Matching Flag Mask"] + #[inline(always)] + pub fn wumf_msk(&mut self) -> WumfMskW { + WumfMskW::new(self, 16) + } + #[doc = "Bit 17 - Wake-up by Timeout Flag Mask"] + #[inline(always)] + pub fn wtof_msk(&mut self) -> WtofMskW { + WtofMskW::new(self, 17) + } +} +#[doc = "Pretended Networking Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1_pn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1_pn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1PnSpec; +impl crate::RegisterSpec for Ctrl1PnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1_pn::R`](R) reader structure"] +impl crate::Readable for Ctrl1PnSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1_pn::W`](W) writer structure"] +impl crate::Writable for Ctrl1PnSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL1_PN to value 0x0100"] +impl crate::Resettable for Ctrl1PnSpec { + const RESET_VALUE: u32 = 0x0100; +} diff --git a/mcxa276-pac/src/can0/ctrl2.rs b/mcxa276-pac/src/can0/ctrl2.rs new file mode 100644 index 000000000..dddf3b20c --- /dev/null +++ b/mcxa276-pac/src/can0/ctrl2.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL2` writer"] +pub type W = crate::W; +#[doc = "Payload Byte and Bit Order Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pes { + #[doc = "0: Big-endian"] + BigEnd = 0, + #[doc = "1: Little-endian"] + LittleEnd = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pes) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PES` reader - Payload Byte and Bit Order Selection"] +pub type PesR = crate::BitReader; +impl PesR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pes { + match self.bits { + false => Pes::BigEnd, + true => Pes::LittleEnd, + } + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn is_big_end(&self) -> bool { + *self == Pes::BigEnd + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn is_little_end(&self) -> bool { + *self == Pes::LittleEnd + } +} +#[doc = "Field `PES` writer - Payload Byte and Bit Order Selection"] +pub type PesW<'a, REG> = crate::BitWriter<'a, REG, Pes>; +impl<'a, REG> PesW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Big-endian"] + #[inline(always)] + pub fn big_end(self) -> &'a mut crate::W { + self.variant(Pes::BigEnd) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn little_end(self) -> &'a mut crate::W { + self.variant(Pes::LittleEnd) + } +} +#[doc = "ACK Suppression Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Asd { + #[doc = "0: Enabled"] + Enable = 0, + #[doc = "1: Disabled"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Asd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ASD` reader - ACK Suppression Disable"] +pub type AsdR = crate::BitReader; +impl AsdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Asd { + match self.bits { + false => Asd::Enable, + true => Asd::Disable, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Asd::Enable + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Asd::Disable + } +} +#[doc = "Field `ASD` writer - ACK Suppression Disable"] +pub type AsdW<'a, REG> = crate::BitWriter<'a, REG, Asd>; +impl<'a, REG> AsdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Asd::Enable) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Asd::Disable) + } +} +#[doc = "Edge Filter Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Edfltdis { + #[doc = "0: Enabled"] + Enable = 0, + #[doc = "1: Disabled"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Edfltdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EDFLTDIS` reader - Edge Filter Disable"] +pub type EdfltdisR = crate::BitReader; +impl EdfltdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edfltdis { + match self.bits { + false => Edfltdis::Enable, + true => Edfltdis::Disable, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Edfltdis::Enable + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Edfltdis::Disable + } +} +#[doc = "Field `EDFLTDIS` writer - Edge Filter Disable"] +pub type EdfltdisW<'a, REG> = crate::BitWriter<'a, REG, Edfltdis>; +impl<'a, REG> EdfltdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Edfltdis::Enable) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Edfltdis::Disable) + } +} +#[doc = "ISO CAN FD Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isocanfden { + #[doc = "0: Disable"] + NonIso = 0, + #[doc = "1: Enable"] + Iso = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isocanfden) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISOCANFDEN` reader - ISO CAN FD Enable"] +pub type IsocanfdenR = crate::BitReader; +impl IsocanfdenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isocanfden { + match self.bits { + false => Isocanfden::NonIso, + true => Isocanfden::Iso, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_non_iso(&self) -> bool { + *self == Isocanfden::NonIso + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_iso(&self) -> bool { + *self == Isocanfden::Iso + } +} +#[doc = "Field `ISOCANFDEN` writer - ISO CAN FD Enable"] +pub type IsocanfdenW<'a, REG> = crate::BitWriter<'a, REG, Isocanfden>; +impl<'a, REG> IsocanfdenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn non_iso(self) -> &'a mut crate::W { + self.variant(Isocanfden::NonIso) + } + #[doc = "Enable"] + #[inline(always)] + pub fn iso(self) -> &'a mut crate::W { + self.variant(Isocanfden::Iso) + } +} +#[doc = "Bit Timing Expansion Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bte { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bte) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BTE` reader - Bit Timing Expansion Enable"] +pub type BteR = crate::BitReader; +impl BteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bte { + match self.bits { + false => Bte::Disable, + true => Bte::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Bte::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Bte::Enable + } +} +#[doc = "Field `BTE` writer - Bit Timing Expansion Enable"] +pub type BteW<'a, REG> = crate::BitWriter<'a, REG, Bte>; +impl<'a, REG> BteW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Bte::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Bte::Enable) + } +} +#[doc = "Protocol Exception Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Prexcen { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Prexcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PREXCEN` reader - Protocol Exception Enable"] +pub type PrexcenR = crate::BitReader; +impl PrexcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prexcen { + match self.bits { + false => Prexcen::Disable, + true => Prexcen::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Prexcen::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Prexcen::Enable + } +} +#[doc = "Field `PREXCEN` writer - Protocol Exception Enable"] +pub type PrexcenW<'a, REG> = crate::BitWriter<'a, REG, Prexcen>; +impl<'a, REG> PrexcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Prexcen::Disable) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Prexcen::Enable) + } +} +#[doc = "Entire Frame Arbitration Field Comparison Enable for RX Message Buffers\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Eacen { + #[doc = "0: Disable"] + RtrCompareNo = 0, + #[doc = "1: Enable"] + RtrCompareYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Eacen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EACEN` reader - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] +pub type EacenR = crate::BitReader; +impl EacenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Eacen { + match self.bits { + false => Eacen::RtrCompareNo, + true => Eacen::RtrCompareYes, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_rtr_compare_no(&self) -> bool { + *self == Eacen::RtrCompareNo + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_rtr_compare_yes(&self) -> bool { + *self == Eacen::RtrCompareYes + } +} +#[doc = "Field `EACEN` writer - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] +pub type EacenW<'a, REG> = crate::BitWriter<'a, REG, Eacen>; +impl<'a, REG> EacenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn rtr_compare_no(self) -> &'a mut crate::W { + self.variant(Eacen::RtrCompareNo) + } + #[doc = "Enable"] + #[inline(always)] + pub fn rtr_compare_yes(self) -> &'a mut crate::W { + self.variant(Eacen::RtrCompareYes) + } +} +#[doc = "Remote Request Storing\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rrs { + #[doc = "0: Generated"] + RemoteResponseFrameNotGenerated = 0, + #[doc = "1: Stored"] + RemoteResponseFrameGenerated = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rrs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRS` reader - Remote Request Storing"] +pub type RrsR = crate::BitReader; +impl RrsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rrs { + match self.bits { + false => Rrs::RemoteResponseFrameNotGenerated, + true => Rrs::RemoteResponseFrameGenerated, + } + } + #[doc = "Generated"] + #[inline(always)] + pub fn is_remote_response_frame_not_generated(&self) -> bool { + *self == Rrs::RemoteResponseFrameNotGenerated + } + #[doc = "Stored"] + #[inline(always)] + pub fn is_remote_response_frame_generated(&self) -> bool { + *self == Rrs::RemoteResponseFrameGenerated + } +} +#[doc = "Field `RRS` writer - Remote Request Storing"] +pub type RrsW<'a, REG> = crate::BitWriter<'a, REG, Rrs>; +impl<'a, REG> RrsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Generated"] + #[inline(always)] + pub fn remote_response_frame_not_generated(self) -> &'a mut crate::W { + self.variant(Rrs::RemoteResponseFrameNotGenerated) + } + #[doc = "Stored"] + #[inline(always)] + pub fn remote_response_frame_generated(self) -> &'a mut crate::W { + self.variant(Rrs::RemoteResponseFrameGenerated) + } +} +#[doc = "Message Buffers Reception Priority\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mrp { + #[doc = "0: Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers."] + Id1 = 0, + #[doc = "1: Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO."] + Id3 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mrp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MRP` reader - Message Buffers Reception Priority"] +pub type MrpR = crate::BitReader; +impl MrpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mrp { + match self.bits { + false => Mrp::Id1, + true => Mrp::Id3, + } + } + #[doc = "Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers."] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Mrp::Id1 + } + #[doc = "Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO."] + #[inline(always)] + pub fn is_id3(&self) -> bool { + *self == Mrp::Id3 + } +} +#[doc = "Field `MRP` writer - Message Buffers Reception Priority"] +pub type MrpW<'a, REG> = crate::BitWriter<'a, REG, Mrp>; +impl<'a, REG> MrpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers."] + #[inline(always)] + pub fn id1(self) -> &'a mut crate::W { + self.variant(Mrp::Id1) + } + #[doc = "Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO."] + #[inline(always)] + pub fn id3(self) -> &'a mut crate::W { + self.variant(Mrp::Id3) + } +} +#[doc = "Field `TASD` reader - Transmission Arbitration Start Delay"] +pub type TasdR = crate::FieldReader; +#[doc = "Field `TASD` writer - Transmission Arbitration Start Delay"] +pub type TasdW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `RFFN` reader - Number of Legacy Receive FIFO Filters"] +pub type RffnR = crate::FieldReader; +#[doc = "Field `RFFN` writer - Number of Legacy Receive FIFO Filters"] +pub type RffnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Bus Off Done Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Boffdonemsk { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Boffdonemsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOFFDONEMSK` reader - Bus Off Done Interrupt Mask"] +pub type BoffdonemskR = crate::BitReader; +impl BoffdonemskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Boffdonemsk { + match self.bits { + false => Boffdonemsk::Disable, + true => Boffdonemsk::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Boffdonemsk::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Boffdonemsk::Enable + } +} +#[doc = "Field `BOFFDONEMSK` writer - Bus Off Done Interrupt Mask"] +pub type BoffdonemskW<'a, REG> = crate::BitWriter<'a, REG, Boffdonemsk>; +impl<'a, REG> BoffdonemskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Boffdonemsk::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Boffdonemsk::Enable) + } +} +#[doc = "Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ErrmskFast { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ErrmskFast) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRMSK_FAST` reader - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] +pub type ErrmskFastR = crate::BitReader; +impl ErrmskFastR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ErrmskFast { + match self.bits { + false => ErrmskFast::Disable, + true => ErrmskFast::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == ErrmskFast::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == ErrmskFast::Enable + } +} +#[doc = "Field `ERRMSK_FAST` writer - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] +pub type ErrmskFastW<'a, REG> = crate::BitWriter<'a, REG, ErrmskFast>; +impl<'a, REG> ErrmskFastW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ErrmskFast::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ErrmskFast::Enable) + } +} +impl R { + #[doc = "Bit 0 - Payload Byte and Bit Order Selection"] + #[inline(always)] + pub fn pes(&self) -> PesR { + PesR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ACK Suppression Disable"] + #[inline(always)] + pub fn asd(&self) -> AsdR { + AsdR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 11 - Edge Filter Disable"] + #[inline(always)] + pub fn edfltdis(&self) -> EdfltdisR { + EdfltdisR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - ISO CAN FD Enable"] + #[inline(always)] + pub fn isocanfden(&self) -> IsocanfdenR { + IsocanfdenR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Bit Timing Expansion Enable"] + #[inline(always)] + pub fn bte(&self) -> BteR { + BteR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Protocol Exception Enable"] + #[inline(always)] + pub fn prexcen(&self) -> PrexcenR { + PrexcenR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] + #[inline(always)] + pub fn eacen(&self) -> EacenR { + EacenR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Remote Request Storing"] + #[inline(always)] + pub fn rrs(&self) -> RrsR { + RrsR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Message Buffers Reception Priority"] + #[inline(always)] + pub fn mrp(&self) -> MrpR { + MrpR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:23 - Transmission Arbitration Start Delay"] + #[inline(always)] + pub fn tasd(&self) -> TasdR { + TasdR::new(((self.bits >> 19) & 0x1f) as u8) + } + #[doc = "Bits 24:27 - Number of Legacy Receive FIFO Filters"] + #[inline(always)] + pub fn rffn(&self) -> RffnR { + RffnR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 30 - Bus Off Done Interrupt Mask"] + #[inline(always)] + pub fn boffdonemsk(&self) -> BoffdonemskR { + BoffdonemskR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] + #[inline(always)] + pub fn errmsk_fast(&self) -> ErrmskFastR { + ErrmskFastR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Payload Byte and Bit Order Selection"] + #[inline(always)] + pub fn pes(&mut self) -> PesW { + PesW::new(self, 0) + } + #[doc = "Bit 1 - ACK Suppression Disable"] + #[inline(always)] + pub fn asd(&mut self) -> AsdW { + AsdW::new(self, 1) + } + #[doc = "Bit 11 - Edge Filter Disable"] + #[inline(always)] + pub fn edfltdis(&mut self) -> EdfltdisW { + EdfltdisW::new(self, 11) + } + #[doc = "Bit 12 - ISO CAN FD Enable"] + #[inline(always)] + pub fn isocanfden(&mut self) -> IsocanfdenW { + IsocanfdenW::new(self, 12) + } + #[doc = "Bit 13 - Bit Timing Expansion Enable"] + #[inline(always)] + pub fn bte(&mut self) -> BteW { + BteW::new(self, 13) + } + #[doc = "Bit 14 - Protocol Exception Enable"] + #[inline(always)] + pub fn prexcen(&mut self) -> PrexcenW { + PrexcenW::new(self, 14) + } + #[doc = "Bit 16 - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] + #[inline(always)] + pub fn eacen(&mut self) -> EacenW { + EacenW::new(self, 16) + } + #[doc = "Bit 17 - Remote Request Storing"] + #[inline(always)] + pub fn rrs(&mut self) -> RrsW { + RrsW::new(self, 17) + } + #[doc = "Bit 18 - Message Buffers Reception Priority"] + #[inline(always)] + pub fn mrp(&mut self) -> MrpW { + MrpW::new(self, 18) + } + #[doc = "Bits 19:23 - Transmission Arbitration Start Delay"] + #[inline(always)] + pub fn tasd(&mut self) -> TasdW { + TasdW::new(self, 19) + } + #[doc = "Bits 24:27 - Number of Legacy Receive FIFO Filters"] + #[inline(always)] + pub fn rffn(&mut self) -> RffnW { + RffnW::new(self, 24) + } + #[doc = "Bit 30 - Bus Off Done Interrupt Mask"] + #[inline(always)] + pub fn boffdonemsk(&mut self) -> BoffdonemskW { + BoffdonemskW::new(self, 30) + } + #[doc = "Bit 31 - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] + #[inline(always)] + pub fn errmsk_fast(&mut self) -> ErrmskFastW { + ErrmskFastW::new(self, 31) + } +} +#[doc = "Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl2Spec; +impl crate::RegisterSpec for Ctrl2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"] +impl crate::Readable for Ctrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"] +impl crate::Writable for Ctrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL2 to value 0x00a0_0000"] +impl crate::Resettable for Ctrl2Spec { + const RESET_VALUE: u32 = 0x00a0_0000; +} diff --git a/mcxa276-pac/src/can0/ctrl2_pn.rs b/mcxa276-pac/src/can0/ctrl2_pn.rs new file mode 100644 index 000000000..8a2e137dd --- /dev/null +++ b/mcxa276-pac/src/can0/ctrl2_pn.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CTRL2_PN` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL2_PN` writer"] +pub type W = crate::W; +#[doc = "Field `MATCHTO` reader - Timeout for No Message Matching the Filtering Criteria"] +pub type MatchtoR = crate::FieldReader; +#[doc = "Field `MATCHTO` writer - Timeout for No Message Matching the Filtering Criteria"] +pub type MatchtoW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"] + #[inline(always)] + pub fn matchto(&self) -> MatchtoR { + MatchtoR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"] + #[inline(always)] + pub fn matchto(&mut self) -> MatchtoW { + MatchtoW::new(self, 0) + } +} +#[doc = "Pretended Networking Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2_pn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2_pn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl2PnSpec; +impl crate::RegisterSpec for Ctrl2PnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl2_pn::R`](R) reader structure"] +impl crate::Readable for Ctrl2PnSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl2_pn::W`](W) writer structure"] +impl crate::Writable for Ctrl2PnSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL2_PN to value 0"] +impl crate::Resettable for Ctrl2PnSpec {} diff --git a/mcxa276-pac/src/can0/ecr.rs b/mcxa276-pac/src/can0/ecr.rs new file mode 100644 index 000000000..a19c075aa --- /dev/null +++ b/mcxa276-pac/src/can0/ecr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `ECR` reader"] +pub type R = crate::R; +#[doc = "Register `ECR` writer"] +pub type W = crate::W; +#[doc = "Field `TXERRCNT` reader - Transmit Error Counter"] +pub type TxerrcntR = crate::FieldReader; +#[doc = "Field `TXERRCNT` writer - Transmit Error Counter"] +pub type TxerrcntW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RXERRCNT` reader - Receive Error Counter"] +pub type RxerrcntR = crate::FieldReader; +#[doc = "Field `RXERRCNT` writer - Receive Error Counter"] +pub type RxerrcntW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TXERRCNT_FAST` reader - Transmit Error Counter for Fast Bits"] +pub type TxerrcntFastR = crate::FieldReader; +#[doc = "Field `TXERRCNT_FAST` writer - Transmit Error Counter for Fast Bits"] +pub type TxerrcntFastW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RXERRCNT_FAST` reader - Receive Error Counter for Fast Bits"] +pub type RxerrcntFastR = crate::FieldReader; +#[doc = "Field `RXERRCNT_FAST` writer - Receive Error Counter for Fast Bits"] +pub type RxerrcntFastW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn txerrcnt(&self) -> TxerrcntR { + TxerrcntR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + pub fn rxerrcnt(&self) -> RxerrcntR { + RxerrcntR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Transmit Error Counter for Fast Bits"] + #[inline(always)] + pub fn txerrcnt_fast(&self) -> TxerrcntFastR { + TxerrcntFastR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Receive Error Counter for Fast Bits"] + #[inline(always)] + pub fn rxerrcnt_fast(&self) -> RxerrcntFastR { + RxerrcntFastR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn txerrcnt(&mut self) -> TxerrcntW { + TxerrcntW::new(self, 0) + } + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + pub fn rxerrcnt(&mut self) -> RxerrcntW { + RxerrcntW::new(self, 8) + } + #[doc = "Bits 16:23 - Transmit Error Counter for Fast Bits"] + #[inline(always)] + pub fn txerrcnt_fast(&mut self) -> TxerrcntFastW { + TxerrcntFastW::new(self, 16) + } + #[doc = "Bits 24:31 - Receive Error Counter for Fast Bits"] + #[inline(always)] + pub fn rxerrcnt_fast(&mut self) -> RxerrcntFastW { + RxerrcntFastW::new(self, 24) + } +} +#[doc = "Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EcrSpec; +impl crate::RegisterSpec for EcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ecr::R`](R) reader structure"] +impl crate::Readable for EcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"] +impl crate::Writable for EcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for EcrSpec {} diff --git a/mcxa276-pac/src/can0/edcbt.rs b/mcxa276-pac/src/can0/edcbt.rs new file mode 100644 index 000000000..c5a63dda0 --- /dev/null +++ b/mcxa276-pac/src/can0/edcbt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `EDCBT` reader"] +pub type R = crate::R; +#[doc = "Register `EDCBT` writer"] +pub type W = crate::W; +#[doc = "Field `DTSEG1` reader - Data Phase Segment 1"] +pub type Dtseg1R = crate::FieldReader; +#[doc = "Field `DTSEG1` writer - Data Phase Segment 1"] +pub type Dtseg1W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `DTSEG2` reader - Data Phase Time Segment 2"] +pub type Dtseg2R = crate::FieldReader; +#[doc = "Field `DTSEG2` writer - Data Phase Time Segment 2"] +pub type Dtseg2W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DRJW` reader - Data Phase Resynchronization Jump Width"] +pub type DrjwR = crate::FieldReader; +#[doc = "Field `DRJW` writer - Data Phase Resynchronization Jump Width"] +pub type DrjwW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:4 - Data Phase Segment 1"] + #[inline(always)] + pub fn dtseg1(&self) -> Dtseg1R { + Dtseg1R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 12:15 - Data Phase Time Segment 2"] + #[inline(always)] + pub fn dtseg2(&self) -> Dtseg2R { + Dtseg2R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 22:25 - Data Phase Resynchronization Jump Width"] + #[inline(always)] + pub fn drjw(&self) -> DrjwR { + DrjwR::new(((self.bits >> 22) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Data Phase Segment 1"] + #[inline(always)] + pub fn dtseg1(&mut self) -> Dtseg1W { + Dtseg1W::new(self, 0) + } + #[doc = "Bits 12:15 - Data Phase Time Segment 2"] + #[inline(always)] + pub fn dtseg2(&mut self) -> Dtseg2W { + Dtseg2W::new(self, 12) + } + #[doc = "Bits 22:25 - Data Phase Resynchronization Jump Width"] + #[inline(always)] + pub fn drjw(&mut self) -> DrjwW { + DrjwW::new(self, 22) + } +} +#[doc = "Enhanced Data Phase CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`edcbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edcbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EdcbtSpec; +impl crate::RegisterSpec for EdcbtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`edcbt::R`](R) reader structure"] +impl crate::Readable for EdcbtSpec {} +#[doc = "`write(|w| ..)` method takes [`edcbt::W`](W) writer structure"] +impl crate::Writable for EdcbtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EDCBT to value 0"] +impl crate::Resettable for EdcbtSpec {} diff --git a/mcxa276-pac/src/can0/encbt.rs b/mcxa276-pac/src/can0/encbt.rs new file mode 100644 index 000000000..a2419451a --- /dev/null +++ b/mcxa276-pac/src/can0/encbt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ENCBT` reader"] +pub type R = crate::R; +#[doc = "Register `ENCBT` writer"] +pub type W = crate::W; +#[doc = "Field `NTSEG1` reader - Nominal Time Segment 1"] +pub type Ntseg1R = crate::FieldReader; +#[doc = "Field `NTSEG1` writer - Nominal Time Segment 1"] +pub type Ntseg1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `NTSEG2` reader - Nominal Time Segment 2"] +pub type Ntseg2R = crate::FieldReader; +#[doc = "Field `NTSEG2` writer - Nominal Time Segment 2"] +pub type Ntseg2W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `NRJW` reader - Nominal Resynchronization Jump Width"] +pub type NrjwR = crate::FieldReader; +#[doc = "Field `NRJW` writer - Nominal Resynchronization Jump Width"] +pub type NrjwW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:7 - Nominal Time Segment 1"] + #[inline(always)] + pub fn ntseg1(&self) -> Ntseg1R { + Ntseg1R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 12:18 - Nominal Time Segment 2"] + #[inline(always)] + pub fn ntseg2(&self) -> Ntseg2R { + Ntseg2R::new(((self.bits >> 12) & 0x7f) as u8) + } + #[doc = "Bits 22:28 - Nominal Resynchronization Jump Width"] + #[inline(always)] + pub fn nrjw(&self) -> NrjwR { + NrjwR::new(((self.bits >> 22) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Nominal Time Segment 1"] + #[inline(always)] + pub fn ntseg1(&mut self) -> Ntseg1W { + Ntseg1W::new(self, 0) + } + #[doc = "Bits 12:18 - Nominal Time Segment 2"] + #[inline(always)] + pub fn ntseg2(&mut self) -> Ntseg2W { + Ntseg2W::new(self, 12) + } + #[doc = "Bits 22:28 - Nominal Resynchronization Jump Width"] + #[inline(always)] + pub fn nrjw(&mut self) -> NrjwW { + NrjwW::new(self, 22) + } +} +#[doc = "Enhanced Nominal CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`encbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`encbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EncbtSpec; +impl crate::RegisterSpec for EncbtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`encbt::R`](R) reader structure"] +impl crate::Readable for EncbtSpec {} +#[doc = "`write(|w| ..)` method takes [`encbt::W`](W) writer structure"] +impl crate::Writable for EncbtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ENCBT to value 0"] +impl crate::Resettable for EncbtSpec {} diff --git a/mcxa276-pac/src/can0/eprs.rs b/mcxa276-pac/src/can0/eprs.rs new file mode 100644 index 000000000..8f77c94f4 --- /dev/null +++ b/mcxa276-pac/src/can0/eprs.rs @@ -0,0 +1,49 @@ +#[doc = "Register `EPRS` reader"] +pub type R = crate::R; +#[doc = "Register `EPRS` writer"] +pub type W = crate::W; +#[doc = "Field `ENPRESDIV` reader - Extended Nominal Prescaler Division Factor"] +pub type EnpresdivR = crate::FieldReader; +#[doc = "Field `ENPRESDIV` writer - Extended Nominal Prescaler Division Factor"] +pub type EnpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `EDPRESDIV` reader - Extended Data Phase Prescaler Division Factor"] +pub type EdpresdivR = crate::FieldReader; +#[doc = "Field `EDPRESDIV` writer - Extended Data Phase Prescaler Division Factor"] +pub type EdpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Extended Nominal Prescaler Division Factor"] + #[inline(always)] + pub fn enpresdiv(&self) -> EnpresdivR { + EnpresdivR::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:25 - Extended Data Phase Prescaler Division Factor"] + #[inline(always)] + pub fn edpresdiv(&self) -> EdpresdivR { + EdpresdivR::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Extended Nominal Prescaler Division Factor"] + #[inline(always)] + pub fn enpresdiv(&mut self) -> EnpresdivW { + EnpresdivW::new(self, 0) + } + #[doc = "Bits 16:25 - Extended Data Phase Prescaler Division Factor"] + #[inline(always)] + pub fn edpresdiv(&mut self) -> EdpresdivW { + EdpresdivW::new(self, 16) + } +} +#[doc = "Enhanced CAN Bit Timing Prescalers\n\nYou can [`read`](crate::Reg::read) this register and get [`eprs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eprs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EprsSpec; +impl crate::RegisterSpec for EprsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`eprs::R`](R) reader structure"] +impl crate::Readable for EprsSpec {} +#[doc = "`write(|w| ..)` method takes [`eprs::W`](W) writer structure"] +impl crate::Writable for EprsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EPRS to value 0"] +impl crate::Resettable for EprsSpec {} diff --git a/mcxa276-pac/src/can0/erfcr.rs b/mcxa276-pac/src/can0/erfcr.rs new file mode 100644 index 000000000..a2e9a8f21 --- /dev/null +++ b/mcxa276-pac/src/can0/erfcr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ERFCR` reader"] +pub type R = crate::R; +#[doc = "Register `ERFCR` writer"] +pub type W = crate::W; +#[doc = "Field `ERFWM` reader - Enhanced RX FIFO Watermark"] +pub type ErfwmR = crate::FieldReader; +#[doc = "Field `ERFWM` writer - Enhanced RX FIFO Watermark"] +pub type ErfwmW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `NFE` reader - Number of Enhanced RX FIFO Filter Elements"] +pub type NfeR = crate::FieldReader; +#[doc = "Field `NFE` writer - Number of Enhanced RX FIFO Filter Elements"] +pub type NfeW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `NEXIF` reader - Number of Extended ID Filter Elements"] +pub type NexifR = crate::FieldReader; +#[doc = "Field `NEXIF` writer - Number of Extended ID Filter Elements"] +pub type NexifW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `DMALW` reader - DMA Last Word"] +pub type DmalwR = crate::FieldReader; +#[doc = "Field `DMALW` writer - DMA Last Word"] +pub type DmalwW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Enhanced RX FIFO enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfen { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFEN` reader - Enhanced RX FIFO enable"] +pub type ErfenR = crate::BitReader; +impl ErfenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfen { + match self.bits { + false => Erfen::Disable, + true => Erfen::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Erfen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Erfen::Enable + } +} +#[doc = "Field `ERFEN` writer - Enhanced RX FIFO enable"] +pub type ErfenW<'a, REG> = crate::BitWriter<'a, REG, Erfen>; +impl<'a, REG> ErfenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Erfen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Erfen::Enable) + } +} +impl R { + #[doc = "Bits 0:4 - Enhanced RX FIFO Watermark"] + #[inline(always)] + pub fn erfwm(&self) -> ErfwmR { + ErfwmR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:13 - Number of Enhanced RX FIFO Filter Elements"] + #[inline(always)] + pub fn nfe(&self) -> NfeR { + NfeR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:22 - Number of Extended ID Filter Elements"] + #[inline(always)] + pub fn nexif(&self) -> NexifR { + NexifR::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 26:30 - DMA Last Word"] + #[inline(always)] + pub fn dmalw(&self) -> DmalwR { + DmalwR::new(((self.bits >> 26) & 0x1f) as u8) + } + #[doc = "Bit 31 - Enhanced RX FIFO enable"] + #[inline(always)] + pub fn erfen(&self) -> ErfenR { + ErfenR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Enhanced RX FIFO Watermark"] + #[inline(always)] + pub fn erfwm(&mut self) -> ErfwmW { + ErfwmW::new(self, 0) + } + #[doc = "Bits 8:13 - Number of Enhanced RX FIFO Filter Elements"] + #[inline(always)] + pub fn nfe(&mut self) -> NfeW { + NfeW::new(self, 8) + } + #[doc = "Bits 16:22 - Number of Extended ID Filter Elements"] + #[inline(always)] + pub fn nexif(&mut self) -> NexifW { + NexifW::new(self, 16) + } + #[doc = "Bits 26:30 - DMA Last Word"] + #[inline(always)] + pub fn dmalw(&mut self) -> DmalwW { + DmalwW::new(self, 26) + } + #[doc = "Bit 31 - Enhanced RX FIFO enable"] + #[inline(always)] + pub fn erfen(&mut self) -> ErfenW { + ErfenW::new(self, 31) + } +} +#[doc = "Enhanced RX FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`erfcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErfcrSpec; +impl crate::RegisterSpec for ErfcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`erfcr::R`](R) reader structure"] +impl crate::Readable for ErfcrSpec {} +#[doc = "`write(|w| ..)` method takes [`erfcr::W`](W) writer structure"] +impl crate::Writable for ErfcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ERFCR to value 0"] +impl crate::Resettable for ErfcrSpec {} diff --git a/mcxa276-pac/src/can0/erffel.rs b/mcxa276-pac/src/can0/erffel.rs new file mode 100644 index 000000000..6d1be69d9 --- /dev/null +++ b/mcxa276-pac/src/can0/erffel.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ERFFEL[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `ERFFEL[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `FEL` reader - Filter Element Bits"] +pub type FelR = crate::FieldReader; +#[doc = "Field `FEL` writer - Filter Element Bits"] +pub type FelW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Filter Element Bits"] + #[inline(always)] + pub fn fel(&self) -> FelR { + FelR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Filter Element Bits"] + #[inline(always)] + pub fn fel(&mut self) -> FelW { + FelW::new(self, 0) + } +} +#[doc = "Enhanced RX FIFO Filter Element\n\nYou can [`read`](crate::Reg::read) this register and get [`erffel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erffel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErffelSpec; +impl crate::RegisterSpec for ErffelSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`erffel::R`](R) reader structure"] +impl crate::Readable for ErffelSpec {} +#[doc = "`write(|w| ..)` method takes [`erffel::W`](W) writer structure"] +impl crate::Writable for ErffelSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ERFFEL[%s] to value 0"] +impl crate::Resettable for ErffelSpec {} diff --git a/mcxa276-pac/src/can0/erfier.rs b/mcxa276-pac/src/can0/erfier.rs new file mode 100644 index 000000000..e988db9b8 --- /dev/null +++ b/mcxa276-pac/src/can0/erfier.rs @@ -0,0 +1,273 @@ +#[doc = "Register `ERFIER` reader"] +pub type R = crate::R; +#[doc = "Register `ERFIER` writer"] +pub type W = crate::W; +#[doc = "Enhanced RX FIFO Data Available Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfdaie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfdaie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFDAIE` reader - Enhanced RX FIFO Data Available Interrupt Enable"] +pub type ErfdaieR = crate::BitReader; +impl ErfdaieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfdaie { + match self.bits { + false => Erfdaie::Disable, + true => Erfdaie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Erfdaie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Erfdaie::Enable + } +} +#[doc = "Field `ERFDAIE` writer - Enhanced RX FIFO Data Available Interrupt Enable"] +pub type ErfdaieW<'a, REG> = crate::BitWriter<'a, REG, Erfdaie>; +impl<'a, REG> ErfdaieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Erfdaie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Erfdaie::Enable) + } +} +#[doc = "Enhanced RX FIFO Watermark Indication Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfwmiie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfwmiie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFWMIIE` reader - Enhanced RX FIFO Watermark Indication Interrupt Enable"] +pub type ErfwmiieR = crate::BitReader; +impl ErfwmiieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfwmiie { + match self.bits { + false => Erfwmiie::Disable, + true => Erfwmiie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Erfwmiie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Erfwmiie::Enable + } +} +#[doc = "Field `ERFWMIIE` writer - Enhanced RX FIFO Watermark Indication Interrupt Enable"] +pub type ErfwmiieW<'a, REG> = crate::BitWriter<'a, REG, Erfwmiie>; +impl<'a, REG> ErfwmiieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Erfwmiie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Erfwmiie::Enable) + } +} +#[doc = "Enhanced RX FIFO Overflow Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfovfie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfovfie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFOVFIE` reader - Enhanced RX FIFO Overflow Interrupt Enable"] +pub type ErfovfieR = crate::BitReader; +impl ErfovfieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfovfie { + match self.bits { + false => Erfovfie::Disable, + true => Erfovfie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Erfovfie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Erfovfie::Enable + } +} +#[doc = "Field `ERFOVFIE` writer - Enhanced RX FIFO Overflow Interrupt Enable"] +pub type ErfovfieW<'a, REG> = crate::BitWriter<'a, REG, Erfovfie>; +impl<'a, REG> ErfovfieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Erfovfie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Erfovfie::Enable) + } +} +#[doc = "Enhanced RX FIFO Underflow Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfufwie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfufwie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFUFWIE` reader - Enhanced RX FIFO Underflow Interrupt Enable"] +pub type ErfufwieR = crate::BitReader; +impl ErfufwieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfufwie { + match self.bits { + false => Erfufwie::Disable, + true => Erfufwie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Erfufwie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Erfufwie::Enable + } +} +#[doc = "Field `ERFUFWIE` writer - Enhanced RX FIFO Underflow Interrupt Enable"] +pub type ErfufwieW<'a, REG> = crate::BitWriter<'a, REG, Erfufwie>; +impl<'a, REG> ErfufwieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Erfufwie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Erfufwie::Enable) + } +} +impl R { + #[doc = "Bit 28 - Enhanced RX FIFO Data Available Interrupt Enable"] + #[inline(always)] + pub fn erfdaie(&self) -> ErfdaieR { + ErfdaieR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Interrupt Enable"] + #[inline(always)] + pub fn erfwmiie(&self) -> ErfwmiieR { + ErfwmiieR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Enhanced RX FIFO Overflow Interrupt Enable"] + #[inline(always)] + pub fn erfovfie(&self) -> ErfovfieR { + ErfovfieR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Enhanced RX FIFO Underflow Interrupt Enable"] + #[inline(always)] + pub fn erfufwie(&self) -> ErfufwieR { + ErfufwieR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 28 - Enhanced RX FIFO Data Available Interrupt Enable"] + #[inline(always)] + pub fn erfdaie(&mut self) -> ErfdaieW { + ErfdaieW::new(self, 28) + } + #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Interrupt Enable"] + #[inline(always)] + pub fn erfwmiie(&mut self) -> ErfwmiieW { + ErfwmiieW::new(self, 29) + } + #[doc = "Bit 30 - Enhanced RX FIFO Overflow Interrupt Enable"] + #[inline(always)] + pub fn erfovfie(&mut self) -> ErfovfieW { + ErfovfieW::new(self, 30) + } + #[doc = "Bit 31 - Enhanced RX FIFO Underflow Interrupt Enable"] + #[inline(always)] + pub fn erfufwie(&mut self) -> ErfufwieW { + ErfufwieW::new(self, 31) + } +} +#[doc = "Enhanced RX FIFO Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erfier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErfierSpec; +impl crate::RegisterSpec for ErfierSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`erfier::R`](R) reader structure"] +impl crate::Readable for ErfierSpec {} +#[doc = "`write(|w| ..)` method takes [`erfier::W`](W) writer structure"] +impl crate::Writable for ErfierSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ERFIER to value 0"] +impl crate::Resettable for ErfierSpec {} diff --git a/mcxa276-pac/src/can0/erfsr.rs b/mcxa276-pac/src/can0/erfsr.rs new file mode 100644 index 000000000..f3ecc3357 --- /dev/null +++ b/mcxa276-pac/src/can0/erfsr.rs @@ -0,0 +1,426 @@ +#[doc = "Register `ERFSR` reader"] +pub type R = crate::R; +#[doc = "Register `ERFSR` writer"] +pub type W = crate::W; +#[doc = "Field `ERFEL` reader - Enhanced RX FIFO Elements"] +pub type ErfelR = crate::FieldReader; +#[doc = "Enhanced RX FIFO Full Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erff { + #[doc = "0: Not full"] + NotFull = 0, + #[doc = "1: Full"] + Full = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erff) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFF` reader - Enhanced RX FIFO Full Flag"] +pub type ErffR = crate::BitReader; +impl ErffR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erff { + match self.bits { + false => Erff::NotFull, + true => Erff::Full, + } + } + #[doc = "Not full"] + #[inline(always)] + pub fn is_not_full(&self) -> bool { + *self == Erff::NotFull + } + #[doc = "Full"] + #[inline(always)] + pub fn is_full(&self) -> bool { + *self == Erff::Full + } +} +#[doc = "Enhanced RX FIFO Empty Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfe { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFE` reader - Enhanced RX FIFO Empty Flag"] +pub type ErfeR = crate::BitReader; +impl ErfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfe { + match self.bits { + false => Erfe::NotEmpty, + true => Erfe::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Erfe::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Erfe::Empty + } +} +#[doc = "Enhanced RX FIFO Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfclr { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Clear enhanced RX FIFO content"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfclr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFCLR` reader - Enhanced RX FIFO Clear"] +pub type ErfclrR = crate::BitReader; +impl ErfclrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfclr { + match self.bits { + false => Erfclr::NoEffect, + true => Erfclr::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Erfclr::NoEffect + } + #[doc = "Clear enhanced RX FIFO content"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Erfclr::Clear + } +} +#[doc = "Field `ERFCLR` writer - Enhanced RX FIFO Clear"] +pub type ErfclrW<'a, REG> = crate::BitWriter<'a, REG, Erfclr>; +impl<'a, REG> ErfclrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Erfclr::NoEffect) + } + #[doc = "Clear enhanced RX FIFO content"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Erfclr::Clear) + } +} +#[doc = "Enhanced RX FIFO Data Available Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfda { + #[doc = "0: No such occurrence"] + NoMessageStored = 0, + #[doc = "1: At least one message stored in Enhanced RX FIFO"] + MessageStored = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfda) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFDA` reader - Enhanced RX FIFO Data Available Flag"] +pub type ErfdaR = crate::BitReader; +impl ErfdaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfda { + match self.bits { + false => Erfda::NoMessageStored, + true => Erfda::MessageStored, + } + } + #[doc = "No such occurrence"] + #[inline(always)] + pub fn is_no_message_stored(&self) -> bool { + *self == Erfda::NoMessageStored + } + #[doc = "At least one message stored in Enhanced RX FIFO"] + #[inline(always)] + pub fn is_message_stored(&self) -> bool { + *self == Erfda::MessageStored + } +} +#[doc = "Field `ERFDA` writer - Enhanced RX FIFO Data Available Flag"] +pub type ErfdaW<'a, REG> = crate::BitWriter1C<'a, REG, Erfda>; +impl<'a, REG> ErfdaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence"] + #[inline(always)] + pub fn no_message_stored(self) -> &'a mut crate::W { + self.variant(Erfda::NoMessageStored) + } + #[doc = "At least one message stored in Enhanced RX FIFO"] + #[inline(always)] + pub fn message_stored(self) -> &'a mut crate::W { + self.variant(Erfda::MessageStored) + } +} +#[doc = "Enhanced RX FIFO Watermark Indication Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfwmi { + #[doc = "0: No such occurrence"] + WatermarkNo = 0, + #[doc = "1: Number of messages in FIFO is greater than the watermark"] + WatermarkYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfwmi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFWMI` reader - Enhanced RX FIFO Watermark Indication Flag"] +pub type ErfwmiR = crate::BitReader; +impl ErfwmiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfwmi { + match self.bits { + false => Erfwmi::WatermarkNo, + true => Erfwmi::WatermarkYes, + } + } + #[doc = "No such occurrence"] + #[inline(always)] + pub fn is_watermark_no(&self) -> bool { + *self == Erfwmi::WatermarkNo + } + #[doc = "Number of messages in FIFO is greater than the watermark"] + #[inline(always)] + pub fn is_watermark_yes(&self) -> bool { + *self == Erfwmi::WatermarkYes + } +} +#[doc = "Field `ERFWMI` writer - Enhanced RX FIFO Watermark Indication Flag"] +pub type ErfwmiW<'a, REG> = crate::BitWriter1C<'a, REG, Erfwmi>; +impl<'a, REG> ErfwmiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence"] + #[inline(always)] + pub fn watermark_no(self) -> &'a mut crate::W { + self.variant(Erfwmi::WatermarkNo) + } + #[doc = "Number of messages in FIFO is greater than the watermark"] + #[inline(always)] + pub fn watermark_yes(self) -> &'a mut crate::W { + self.variant(Erfwmi::WatermarkYes) + } +} +#[doc = "Enhanced RX FIFO Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfovf { + #[doc = "0: No such occurrence"] + NoOverflow = 0, + #[doc = "1: Overflow"] + Overflow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfovf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFOVF` reader - Enhanced RX FIFO Overflow Flag"] +pub type ErfovfR = crate::BitReader; +impl ErfovfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfovf { + match self.bits { + false => Erfovf::NoOverflow, + true => Erfovf::Overflow, + } + } + #[doc = "No such occurrence"] + #[inline(always)] + pub fn is_no_overflow(&self) -> bool { + *self == Erfovf::NoOverflow + } + #[doc = "Overflow"] + #[inline(always)] + pub fn is_overflow(&self) -> bool { + *self == Erfovf::Overflow + } +} +#[doc = "Field `ERFOVF` writer - Enhanced RX FIFO Overflow Flag"] +pub type ErfovfW<'a, REG> = crate::BitWriter1C<'a, REG, Erfovf>; +impl<'a, REG> ErfovfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence"] + #[inline(always)] + pub fn no_overflow(self) -> &'a mut crate::W { + self.variant(Erfovf::NoOverflow) + } + #[doc = "Overflow"] + #[inline(always)] + pub fn overflow(self) -> &'a mut crate::W { + self.variant(Erfovf::Overflow) + } +} +#[doc = "Enhanced RX FIFO Underflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erfufw { + #[doc = "0: No such occurrence"] + NoUnderflow = 0, + #[doc = "1: Underflow"] + Underflow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erfufw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERFUFW` reader - Enhanced RX FIFO Underflow Flag"] +pub type ErfufwR = crate::BitReader; +impl ErfufwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erfufw { + match self.bits { + false => Erfufw::NoUnderflow, + true => Erfufw::Underflow, + } + } + #[doc = "No such occurrence"] + #[inline(always)] + pub fn is_no_underflow(&self) -> bool { + *self == Erfufw::NoUnderflow + } + #[doc = "Underflow"] + #[inline(always)] + pub fn is_underflow(&self) -> bool { + *self == Erfufw::Underflow + } +} +#[doc = "Field `ERFUFW` writer - Enhanced RX FIFO Underflow Flag"] +pub type ErfufwW<'a, REG> = crate::BitWriter1C<'a, REG, Erfufw>; +impl<'a, REG> ErfufwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence"] + #[inline(always)] + pub fn no_underflow(self) -> &'a mut crate::W { + self.variant(Erfufw::NoUnderflow) + } + #[doc = "Underflow"] + #[inline(always)] + pub fn underflow(self) -> &'a mut crate::W { + self.variant(Erfufw::Underflow) + } +} +impl R { + #[doc = "Bits 0:5 - Enhanced RX FIFO Elements"] + #[inline(always)] + pub fn erfel(&self) -> ErfelR { + ErfelR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 16 - Enhanced RX FIFO Full Flag"] + #[inline(always)] + pub fn erff(&self) -> ErffR { + ErffR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enhanced RX FIFO Empty Flag"] + #[inline(always)] + pub fn erfe(&self) -> ErfeR { + ErfeR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 27 - Enhanced RX FIFO Clear"] + #[inline(always)] + pub fn erfclr(&self) -> ErfclrR { + ErfclrR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Enhanced RX FIFO Data Available Flag"] + #[inline(always)] + pub fn erfda(&self) -> ErfdaR { + ErfdaR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Flag"] + #[inline(always)] + pub fn erfwmi(&self) -> ErfwmiR { + ErfwmiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Enhanced RX FIFO Overflow Flag"] + #[inline(always)] + pub fn erfovf(&self) -> ErfovfR { + ErfovfR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Enhanced RX FIFO Underflow Flag"] + #[inline(always)] + pub fn erfufw(&self) -> ErfufwR { + ErfufwR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 27 - Enhanced RX FIFO Clear"] + #[inline(always)] + pub fn erfclr(&mut self) -> ErfclrW { + ErfclrW::new(self, 27) + } + #[doc = "Bit 28 - Enhanced RX FIFO Data Available Flag"] + #[inline(always)] + pub fn erfda(&mut self) -> ErfdaW { + ErfdaW::new(self, 28) + } + #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Flag"] + #[inline(always)] + pub fn erfwmi(&mut self) -> ErfwmiW { + ErfwmiW::new(self, 29) + } + #[doc = "Bit 30 - Enhanced RX FIFO Overflow Flag"] + #[inline(always)] + pub fn erfovf(&mut self) -> ErfovfW { + ErfovfW::new(self, 30) + } + #[doc = "Bit 31 - Enhanced RX FIFO Underflow Flag"] + #[inline(always)] + pub fn erfufw(&mut self) -> ErfufwW { + ErfufwW::new(self, 31) + } +} +#[doc = "Enhanced RX FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`erfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErfsrSpec; +impl crate::RegisterSpec for ErfsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`erfsr::R`](R) reader structure"] +impl crate::Readable for ErfsrSpec {} +#[doc = "`write(|w| ..)` method takes [`erfsr::W`](W) writer structure"] +impl crate::Writable for ErfsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xf000_0000; +} +#[doc = "`reset()` method sets ERFSR to value 0"] +impl crate::Resettable for ErfsrSpec {} diff --git a/mcxa276-pac/src/can0/esr1.rs b/mcxa276-pac/src/can0/esr1.rs new file mode 100644 index 000000000..710716c5d --- /dev/null +++ b/mcxa276-pac/src/can0/esr1.rs @@ -0,0 +1,1278 @@ +#[doc = "Register `ESR1` reader"] +pub type R = crate::R; +#[doc = "Register `ESR1` writer"] +pub type W = crate::W; +#[doc = "Wake-up Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wakint { + #[doc = "0: No such occurrence."] + Disable = 0, + #[doc = "1: Indicates that a recessive-to-dominant transition was received on the CAN bus."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wakint) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKINT` reader - Wake-up Interrupt Flag"] +pub type WakintR = crate::BitReader; +impl WakintR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wakint { + match self.bits { + false => Wakint::Disable, + true => Wakint::Enable, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wakint::Disable + } + #[doc = "Indicates that a recessive-to-dominant transition was received on the CAN bus."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wakint::Enable + } +} +#[doc = "Field `WAKINT` writer - Wake-up Interrupt Flag"] +pub type WakintW<'a, REG> = crate::BitWriter1C<'a, REG, Wakint>; +impl<'a, REG> WakintW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wakint::Disable) + } + #[doc = "Indicates that a recessive-to-dominant transition was received on the CAN bus."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wakint::Enable) + } +} +#[doc = "Error Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errint { + #[doc = "0: No such occurrence."] + Disable = 0, + #[doc = "1: Indicates setting of any error flag in the Error and Status register."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errint) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRINT` reader - Error Interrupt Flag"] +pub type ErrintR = crate::BitReader; +impl ErrintR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errint { + match self.bits { + false => Errint::Disable, + true => Errint::Enable, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Errint::Disable + } + #[doc = "Indicates setting of any error flag in the Error and Status register."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Errint::Enable + } +} +#[doc = "Field `ERRINT` writer - Error Interrupt Flag"] +pub type ErrintW<'a, REG> = crate::BitWriter1C<'a, REG, Errint>; +impl<'a, REG> ErrintW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Errint::Disable) + } + #[doc = "Indicates setting of any error flag in the Error and Status register."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Errint::Enable) + } +} +#[doc = "Bus Off Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Boffint { + #[doc = "0: No such occurrence."] + Disable = 0, + #[doc = "1: FlexCAN module entered Bus Off state."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Boffint) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOFFINT` reader - Bus Off Interrupt Flag"] +pub type BoffintR = crate::BitReader; +impl BoffintR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Boffint { + match self.bits { + false => Boffint::Disable, + true => Boffint::Enable, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Boffint::Disable + } + #[doc = "FlexCAN module entered Bus Off state."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Boffint::Enable + } +} +#[doc = "Field `BOFFINT` writer - Bus Off Interrupt Flag"] +pub type BoffintW<'a, REG> = crate::BitWriter1C<'a, REG, Boffint>; +impl<'a, REG> BoffintW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Boffint::Disable) + } + #[doc = "FlexCAN module entered Bus Off state."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Boffint::Enable) + } +} +#[doc = "FlexCAN in Reception Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rx { + #[doc = "0: Not receiving"] + Disable = 0, + #[doc = "1: Receiving"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RX` reader - FlexCAN in Reception Flag"] +pub type RxR = crate::BitReader; +impl RxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rx { + match self.bits { + false => Rx::Disable, + true => Rx::Enable, + } + } + #[doc = "Not receiving"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rx::Disable + } + #[doc = "Receiving"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rx::Enable + } +} +#[doc = "Fault Confinement State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fltconf { + #[doc = "0: Error Active"] + ErrorActive = 0, + #[doc = "1: Error Passive"] + ErrorPassive = 1, + #[doc = "2: Bus Off"] + BusOff = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fltconf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fltconf { + type Ux = u8; +} +impl crate::IsEnum for Fltconf {} +#[doc = "Field `FLTCONF` reader - Fault Confinement State"] +pub type FltconfR = crate::FieldReader; +impl FltconfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Fltconf::ErrorActive), + 1 => Some(Fltconf::ErrorPassive), + 2 => Some(Fltconf::BusOff), + _ => None, + } + } + #[doc = "Error Active"] + #[inline(always)] + pub fn is_error_active(&self) -> bool { + *self == Fltconf::ErrorActive + } + #[doc = "Error Passive"] + #[inline(always)] + pub fn is_error_passive(&self) -> bool { + *self == Fltconf::ErrorPassive + } + #[doc = "Bus Off"] + #[inline(always)] + pub fn is_bus_off(&self) -> bool { + *self == Fltconf::BusOff + } +} +#[doc = "FlexCAN In Transmission\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tx { + #[doc = "0: Not transmitting"] + TransmitMessageNo = 0, + #[doc = "1: Transmitting"] + TransmitMessageYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TX` reader - FlexCAN In Transmission"] +pub type TxR = crate::BitReader; +impl TxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tx { + match self.bits { + false => Tx::TransmitMessageNo, + true => Tx::TransmitMessageYes, + } + } + #[doc = "Not transmitting"] + #[inline(always)] + pub fn is_transmit_message_no(&self) -> bool { + *self == Tx::TransmitMessageNo + } + #[doc = "Transmitting"] + #[inline(always)] + pub fn is_transmit_message_yes(&self) -> bool { + *self == Tx::TransmitMessageYes + } +} +#[doc = "Idle\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Idle { + #[doc = "0: Not IDLE"] + CanBusNotIdle = 0, + #[doc = "1: IDLE"] + CanBusIdle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Idle) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IDLE` reader - Idle"] +pub type IdleR = crate::BitReader; +impl IdleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Idle { + match self.bits { + false => Idle::CanBusNotIdle, + true => Idle::CanBusIdle, + } + } + #[doc = "Not IDLE"] + #[inline(always)] + pub fn is_can_bus_not_idle(&self) -> bool { + *self == Idle::CanBusNotIdle + } + #[doc = "IDLE"] + #[inline(always)] + pub fn is_can_bus_idle(&self) -> bool { + *self == Idle::CanBusIdle + } +} +#[doc = "RX Error Warning Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxwrn { + #[doc = "0: No such occurrence."] + RxerrcntLt96 = 0, + #[doc = "1: RXERRCNT is greater than or equal to 96."] + RxerrcntGte96 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxwrn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXWRN` reader - RX Error Warning Flag"] +pub type RxwrnR = crate::BitReader; +impl RxwrnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxwrn { + match self.bits { + false => Rxwrn::RxerrcntLt96, + true => Rxwrn::RxerrcntGte96, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_rxerrcnt_lt_96(&self) -> bool { + *self == Rxwrn::RxerrcntLt96 + } + #[doc = "RXERRCNT is greater than or equal to 96."] + #[inline(always)] + pub fn is_rxerrcnt_gte_96(&self) -> bool { + *self == Rxwrn::RxerrcntGte96 + } +} +#[doc = "TX Error Warning Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txwrn { + #[doc = "0: No such occurrence."] + TxerrcntLt96 = 0, + #[doc = "1: TXERRCNT is 96 or greater."] + TxerrcntGte96 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txwrn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXWRN` reader - TX Error Warning Flag"] +pub type TxwrnR = crate::BitReader; +impl TxwrnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txwrn { + match self.bits { + false => Txwrn::TxerrcntLt96, + true => Txwrn::TxerrcntGte96, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_txerrcnt_lt_96(&self) -> bool { + *self == Txwrn::TxerrcntLt96 + } + #[doc = "TXERRCNT is 96 or greater."] + #[inline(always)] + pub fn is_txerrcnt_gte_96(&self) -> bool { + *self == Txwrn::TxerrcntGte96 + } +} +#[doc = "Stuffing Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stferr { + #[doc = "0: No error"] + StuffingErrorNo = 0, + #[doc = "1: Error occurred since last read of this register."] + StuffingErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stferr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STFERR` reader - Stuffing Error Flag"] +pub type StferrR = crate::BitReader; +impl StferrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stferr { + match self.bits { + false => Stferr::StuffingErrorNo, + true => Stferr::StuffingErrorYes, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_stuffing_error_no(&self) -> bool { + *self == Stferr::StuffingErrorNo + } + #[doc = "Error occurred since last read of this register."] + #[inline(always)] + pub fn is_stuffing_error_yes(&self) -> bool { + *self == Stferr::StuffingErrorYes + } +} +#[doc = "Form Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frmerr { + #[doc = "0: No error"] + FormErrorNo = 0, + #[doc = "1: Error occurred since last read of this register."] + FormErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frmerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRMERR` reader - Form Error Flag"] +pub type FrmerrR = crate::BitReader; +impl FrmerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frmerr { + match self.bits { + false => Frmerr::FormErrorNo, + true => Frmerr::FormErrorYes, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_form_error_no(&self) -> bool { + *self == Frmerr::FormErrorNo + } + #[doc = "Error occurred since last read of this register."] + #[inline(always)] + pub fn is_form_error_yes(&self) -> bool { + *self == Frmerr::FormErrorYes + } +} +#[doc = "Cyclic Redundancy Check Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crcerr { + #[doc = "0: No error"] + CrcErrorNo = 0, + #[doc = "1: Error occurred since last read of this register."] + CrcErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crcerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRCERR` reader - Cyclic Redundancy Check Error Flag"] +pub type CrcerrR = crate::BitReader; +impl CrcerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crcerr { + match self.bits { + false => Crcerr::CrcErrorNo, + true => Crcerr::CrcErrorYes, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_crc_error_no(&self) -> bool { + *self == Crcerr::CrcErrorNo + } + #[doc = "Error occurred since last read of this register."] + #[inline(always)] + pub fn is_crc_error_yes(&self) -> bool { + *self == Crcerr::CrcErrorYes + } +} +#[doc = "Acknowledge Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ackerr { + #[doc = "0: No error"] + AckErrorNo = 0, + #[doc = "1: Error occurred since last read of this register."] + AckErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ackerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACKERR` reader - Acknowledge Error Flag"] +pub type AckerrR = crate::BitReader; +impl AckerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ackerr { + match self.bits { + false => Ackerr::AckErrorNo, + true => Ackerr::AckErrorYes, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_ack_error_no(&self) -> bool { + *self == Ackerr::AckErrorNo + } + #[doc = "Error occurred since last read of this register."] + #[inline(always)] + pub fn is_ack_error_yes(&self) -> bool { + *self == Ackerr::AckErrorYes + } +} +#[doc = "Bit0 Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bit0err { + #[doc = "0: No such occurrence."] + Bit0ErrorNo = 0, + #[doc = "1: At least one bit sent as dominant is received as recessive."] + Bit0ErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bit0err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BIT0ERR` reader - Bit0 Error Flag"] +pub type Bit0errR = crate::BitReader; +impl Bit0errR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bit0err { + match self.bits { + false => Bit0err::Bit0ErrorNo, + true => Bit0err::Bit0ErrorYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_bit0_error_no(&self) -> bool { + *self == Bit0err::Bit0ErrorNo + } + #[doc = "At least one bit sent as dominant is received as recessive."] + #[inline(always)] + pub fn is_bit0_error_yes(&self) -> bool { + *self == Bit0err::Bit0ErrorYes + } +} +#[doc = "Bit1 Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bit1err { + #[doc = "0: No such occurrence."] + Bit1ErrorNo = 0, + #[doc = "1: At least one bit sent as recessive is received as dominant."] + Bit1ErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bit1err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BIT1ERR` reader - Bit1 Error Flag"] +pub type Bit1errR = crate::BitReader; +impl Bit1errR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bit1err { + match self.bits { + false => Bit1err::Bit1ErrorNo, + true => Bit1err::Bit1ErrorYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_bit1_error_no(&self) -> bool { + *self == Bit1err::Bit1ErrorNo + } + #[doc = "At least one bit sent as recessive is received as dominant."] + #[inline(always)] + pub fn is_bit1_error_yes(&self) -> bool { + *self == Bit1err::Bit1ErrorYes + } +} +#[doc = "RX Warning Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rwrnint { + #[doc = "0: No such occurrence"] + RxWarningIntNo = 0, + #[doc = "1: RX error counter changed from less than 96 to greater than or equal to 96."] + RxWarningIntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rwrnint) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RWRNINT` reader - RX Warning Interrupt Flag"] +pub type RwrnintR = crate::BitReader; +impl RwrnintR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rwrnint { + match self.bits { + false => Rwrnint::RxWarningIntNo, + true => Rwrnint::RxWarningIntYes, + } + } + #[doc = "No such occurrence"] + #[inline(always)] + pub fn is_rx_warning_int_no(&self) -> bool { + *self == Rwrnint::RxWarningIntNo + } + #[doc = "RX error counter changed from less than 96 to greater than or equal to 96."] + #[inline(always)] + pub fn is_rx_warning_int_yes(&self) -> bool { + *self == Rwrnint::RxWarningIntYes + } +} +#[doc = "Field `RWRNINT` writer - RX Warning Interrupt Flag"] +pub type RwrnintW<'a, REG> = crate::BitWriter1C<'a, REG, Rwrnint>; +impl<'a, REG> RwrnintW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence"] + #[inline(always)] + pub fn rx_warning_int_no(self) -> &'a mut crate::W { + self.variant(Rwrnint::RxWarningIntNo) + } + #[doc = "RX error counter changed from less than 96 to greater than or equal to 96."] + #[inline(always)] + pub fn rx_warning_int_yes(self) -> &'a mut crate::W { + self.variant(Rwrnint::RxWarningIntYes) + } +} +#[doc = "TX Warning Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Twrnint { + #[doc = "0: No such occurrence"] + TxWarningIntNo = 0, + #[doc = "1: TX error counter changed from less than 96 to greater than or equal to 96."] + TxWarningIntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Twrnint) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TWRNINT` reader - TX Warning Interrupt Flag"] +pub type TwrnintR = crate::BitReader; +impl TwrnintR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Twrnint { + match self.bits { + false => Twrnint::TxWarningIntNo, + true => Twrnint::TxWarningIntYes, + } + } + #[doc = "No such occurrence"] + #[inline(always)] + pub fn is_tx_warning_int_no(&self) -> bool { + *self == Twrnint::TxWarningIntNo + } + #[doc = "TX error counter changed from less than 96 to greater than or equal to 96."] + #[inline(always)] + pub fn is_tx_warning_int_yes(&self) -> bool { + *self == Twrnint::TxWarningIntYes + } +} +#[doc = "Field `TWRNINT` writer - TX Warning Interrupt Flag"] +pub type TwrnintW<'a, REG> = crate::BitWriter1C<'a, REG, Twrnint>; +impl<'a, REG> TwrnintW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence"] + #[inline(always)] + pub fn tx_warning_int_no(self) -> &'a mut crate::W { + self.variant(Twrnint::TxWarningIntNo) + } + #[doc = "TX error counter changed from less than 96 to greater than or equal to 96."] + #[inline(always)] + pub fn tx_warning_int_yes(self) -> &'a mut crate::W { + self.variant(Twrnint::TxWarningIntYes) + } +} +#[doc = "CAN Synchronization Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Synch { + #[doc = "0: Not synchronized"] + CanBusSyncNo = 0, + #[doc = "1: Synchronized"] + CanBusSyncYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Synch) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYNCH` reader - CAN Synchronization Status Flag"] +pub type SynchR = crate::BitReader; +impl SynchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Synch { + match self.bits { + false => Synch::CanBusSyncNo, + true => Synch::CanBusSyncYes, + } + } + #[doc = "Not synchronized"] + #[inline(always)] + pub fn is_can_bus_sync_no(&self) -> bool { + *self == Synch::CanBusSyncNo + } + #[doc = "Synchronized"] + #[inline(always)] + pub fn is_can_bus_sync_yes(&self) -> bool { + *self == Synch::CanBusSyncYes + } +} +#[doc = "Bus Off Done Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Boffdoneint { + #[doc = "0: No such occurrence"] + BusOffNotDone = 0, + #[doc = "1: FlexCAN module has completed Bus Off process."] + BusOffDone = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Boffdoneint) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOFFDONEINT` reader - Bus Off Done Interrupt Flag"] +pub type BoffdoneintR = crate::BitReader; +impl BoffdoneintR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Boffdoneint { + match self.bits { + false => Boffdoneint::BusOffNotDone, + true => Boffdoneint::BusOffDone, + } + } + #[doc = "No such occurrence"] + #[inline(always)] + pub fn is_bus_off_not_done(&self) -> bool { + *self == Boffdoneint::BusOffNotDone + } + #[doc = "FlexCAN module has completed Bus Off process."] + #[inline(always)] + pub fn is_bus_off_done(&self) -> bool { + *self == Boffdoneint::BusOffDone + } +} +#[doc = "Field `BOFFDONEINT` writer - Bus Off Done Interrupt Flag"] +pub type BoffdoneintW<'a, REG> = crate::BitWriter1C<'a, REG, Boffdoneint>; +impl<'a, REG> BoffdoneintW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence"] + #[inline(always)] + pub fn bus_off_not_done(self) -> &'a mut crate::W { + self.variant(Boffdoneint::BusOffNotDone) + } + #[doc = "FlexCAN module has completed Bus Off process."] + #[inline(always)] + pub fn bus_off_done(self) -> &'a mut crate::W { + self.variant(Boffdoneint::BusOffDone) + } +} +#[doc = "Fast Error Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ErrintFast { + #[doc = "0: No such occurrence."] + ErrorsDataPhaseNo = 0, + #[doc = "1: Error flag set in the data phase of CAN FD frames that have BRS = 1."] + ErrorsDataPhaseYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ErrintFast) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRINT_FAST` reader - Fast Error Interrupt Flag"] +pub type ErrintFastR = crate::BitReader; +impl ErrintFastR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ErrintFast { + match self.bits { + false => ErrintFast::ErrorsDataPhaseNo, + true => ErrintFast::ErrorsDataPhaseYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_errors_data_phase_no(&self) -> bool { + *self == ErrintFast::ErrorsDataPhaseNo + } + #[doc = "Error flag set in the data phase of CAN FD frames that have BRS = 1."] + #[inline(always)] + pub fn is_errors_data_phase_yes(&self) -> bool { + *self == ErrintFast::ErrorsDataPhaseYes + } +} +#[doc = "Field `ERRINT_FAST` writer - Fast Error Interrupt Flag"] +pub type ErrintFastW<'a, REG> = crate::BitWriter1C<'a, REG, ErrintFast>; +impl<'a, REG> ErrintFastW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No such occurrence."] + #[inline(always)] + pub fn errors_data_phase_no(self) -> &'a mut crate::W { + self.variant(ErrintFast::ErrorsDataPhaseNo) + } + #[doc = "Error flag set in the data phase of CAN FD frames that have BRS = 1."] + #[inline(always)] + pub fn errors_data_phase_yes(self) -> &'a mut crate::W { + self.variant(ErrintFast::ErrorsDataPhaseYes) + } +} +#[doc = "Error Overrun Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errovr { + #[doc = "0: No overrun"] + OverrunNotOccurred = 0, + #[doc = "1: Overrun"] + OverrunOccurred = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errovr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROVR` reader - Error Overrun Flag"] +pub type ErrovrR = crate::BitReader; +impl ErrovrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errovr { + match self.bits { + false => Errovr::OverrunNotOccurred, + true => Errovr::OverrunOccurred, + } + } + #[doc = "No overrun"] + #[inline(always)] + pub fn is_overrun_not_occurred(&self) -> bool { + *self == Errovr::OverrunNotOccurred + } + #[doc = "Overrun"] + #[inline(always)] + pub fn is_overrun_occurred(&self) -> bool { + *self == Errovr::OverrunOccurred + } +} +#[doc = "Field `ERROVR` writer - Error Overrun Flag"] +pub type ErrovrW<'a, REG> = crate::BitWriter1C<'a, REG, Errovr>; +impl<'a, REG> ErrovrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overrun"] + #[inline(always)] + pub fn overrun_not_occurred(self) -> &'a mut crate::W { + self.variant(Errovr::OverrunNotOccurred) + } + #[doc = "Overrun"] + #[inline(always)] + pub fn overrun_occurred(self) -> &'a mut crate::W { + self.variant(Errovr::OverrunOccurred) + } +} +#[doc = "Fast Stuffing Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StferrFast { + #[doc = "0: No such occurrence."] + StuffingErrorNo = 0, + #[doc = "1: A stuffing error occurred since last read of this register."] + StuffingErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StferrFast) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STFERR_FAST` reader - Fast Stuffing Error Flag"] +pub type StferrFastR = crate::BitReader; +impl StferrFastR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StferrFast { + match self.bits { + false => StferrFast::StuffingErrorNo, + true => StferrFast::StuffingErrorYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_stuffing_error_no(&self) -> bool { + *self == StferrFast::StuffingErrorNo + } + #[doc = "A stuffing error occurred since last read of this register."] + #[inline(always)] + pub fn is_stuffing_error_yes(&self) -> bool { + *self == StferrFast::StuffingErrorYes + } +} +#[doc = "Fast Form Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FrmerrFast { + #[doc = "0: No such occurrence."] + FormErrorNo = 0, + #[doc = "1: A form error occurred since last read of this register."] + FormErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FrmerrFast) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRMERR_FAST` reader - Fast Form Error Flag"] +pub type FrmerrFastR = crate::BitReader; +impl FrmerrFastR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FrmerrFast { + match self.bits { + false => FrmerrFast::FormErrorNo, + true => FrmerrFast::FormErrorYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_form_error_no(&self) -> bool { + *self == FrmerrFast::FormErrorNo + } + #[doc = "A form error occurred since last read of this register."] + #[inline(always)] + pub fn is_form_error_yes(&self) -> bool { + *self == FrmerrFast::FormErrorYes + } +} +#[doc = "Fast Cyclic Redundancy Check Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CrcerrFast { + #[doc = "0: No such occurrence."] + CrcErrorNo = 0, + #[doc = "1: A CRC error occurred since last read of this register."] + CrcErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CrcerrFast) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRCERR_FAST` reader - Fast Cyclic Redundancy Check Error Flag"] +pub type CrcerrFastR = crate::BitReader; +impl CrcerrFastR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CrcerrFast { + match self.bits { + false => CrcerrFast::CrcErrorNo, + true => CrcerrFast::CrcErrorYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_crc_error_no(&self) -> bool { + *self == CrcerrFast::CrcErrorNo + } + #[doc = "A CRC error occurred since last read of this register."] + #[inline(always)] + pub fn is_crc_error_yes(&self) -> bool { + *self == CrcerrFast::CrcErrorYes + } +} +#[doc = "Fast Bit0 Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bit0errFast { + #[doc = "0: No such occurrence."] + Bit0ErrorNo = 0, + #[doc = "1: At least one bit transmitted as dominant is received as recessive."] + Bit0ErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bit0errFast) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BIT0ERR_FAST` reader - Fast Bit0 Error Flag"] +pub type Bit0errFastR = crate::BitReader; +impl Bit0errFastR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bit0errFast { + match self.bits { + false => Bit0errFast::Bit0ErrorNo, + true => Bit0errFast::Bit0ErrorYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_bit0_error_no(&self) -> bool { + *self == Bit0errFast::Bit0ErrorNo + } + #[doc = "At least one bit transmitted as dominant is received as recessive."] + #[inline(always)] + pub fn is_bit0_error_yes(&self) -> bool { + *self == Bit0errFast::Bit0ErrorYes + } +} +#[doc = "Fast Bit1 Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bit1errFast { + #[doc = "0: No such occurrence."] + Bit1ErrorNo = 0, + #[doc = "1: At least one bit transmitted as recessive is received as dominant."] + Bit1ErrorYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bit1errFast) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BIT1ERR_FAST` reader - Fast Bit1 Error Flag"] +pub type Bit1errFastR = crate::BitReader; +impl Bit1errFastR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bit1errFast { + match self.bits { + false => Bit1errFast::Bit1ErrorNo, + true => Bit1errFast::Bit1ErrorYes, + } + } + #[doc = "No such occurrence."] + #[inline(always)] + pub fn is_bit1_error_no(&self) -> bool { + *self == Bit1errFast::Bit1ErrorNo + } + #[doc = "At least one bit transmitted as recessive is received as dominant."] + #[inline(always)] + pub fn is_bit1_error_yes(&self) -> bool { + *self == Bit1errFast::Bit1ErrorYes + } +} +impl R { + #[doc = "Bit 0 - Wake-up Interrupt Flag"] + #[inline(always)] + pub fn wakint(&self) -> WakintR { + WakintR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Error Interrupt Flag"] + #[inline(always)] + pub fn errint(&self) -> ErrintR { + ErrintR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Bus Off Interrupt Flag"] + #[inline(always)] + pub fn boffint(&self) -> BoffintR { + BoffintR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FlexCAN in Reception Flag"] + #[inline(always)] + pub fn rx(&self) -> RxR { + RxR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Fault Confinement State"] + #[inline(always)] + pub fn fltconf(&self) -> FltconfR { + FltconfR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - FlexCAN In Transmission"] + #[inline(always)] + pub fn tx(&self) -> TxR { + TxR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX Error Warning Flag"] + #[inline(always)] + pub fn rxwrn(&self) -> RxwrnR { + RxwrnR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TX Error Warning Flag"] + #[inline(always)] + pub fn txwrn(&self) -> TxwrnR { + TxwrnR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Stuffing Error Flag"] + #[inline(always)] + pub fn stferr(&self) -> StferrR { + StferrR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Form Error Flag"] + #[inline(always)] + pub fn frmerr(&self) -> FrmerrR { + FrmerrR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Cyclic Redundancy Check Error Flag"] + #[inline(always)] + pub fn crcerr(&self) -> CrcerrR { + CrcerrR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Acknowledge Error Flag"] + #[inline(always)] + pub fn ackerr(&self) -> AckerrR { + AckerrR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Bit0 Error Flag"] + #[inline(always)] + pub fn bit0err(&self) -> Bit0errR { + Bit0errR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Bit1 Error Flag"] + #[inline(always)] + pub fn bit1err(&self) -> Bit1errR { + Bit1errR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - RX Warning Interrupt Flag"] + #[inline(always)] + pub fn rwrnint(&self) -> RwrnintR { + RwrnintR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - TX Warning Interrupt Flag"] + #[inline(always)] + pub fn twrnint(&self) -> TwrnintR { + TwrnintR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - CAN Synchronization Status Flag"] + #[inline(always)] + pub fn synch(&self) -> SynchR { + SynchR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Bus Off Done Interrupt Flag"] + #[inline(always)] + pub fn boffdoneint(&self) -> BoffdoneintR { + BoffdoneintR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Fast Error Interrupt Flag"] + #[inline(always)] + pub fn errint_fast(&self) -> ErrintFastR { + ErrintFastR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Error Overrun Flag"] + #[inline(always)] + pub fn errovr(&self) -> ErrovrR { + ErrovrR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 26 - Fast Stuffing Error Flag"] + #[inline(always)] + pub fn stferr_fast(&self) -> StferrFastR { + StferrFastR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Fast Form Error Flag"] + #[inline(always)] + pub fn frmerr_fast(&self) -> FrmerrFastR { + FrmerrFastR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Fast Cyclic Redundancy Check Error Flag"] + #[inline(always)] + pub fn crcerr_fast(&self) -> CrcerrFastR { + CrcerrFastR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 30 - Fast Bit0 Error Flag"] + #[inline(always)] + pub fn bit0err_fast(&self) -> Bit0errFastR { + Bit0errFastR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Fast Bit1 Error Flag"] + #[inline(always)] + pub fn bit1err_fast(&self) -> Bit1errFastR { + Bit1errFastR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Wake-up Interrupt Flag"] + #[inline(always)] + pub fn wakint(&mut self) -> WakintW { + WakintW::new(self, 0) + } + #[doc = "Bit 1 - Error Interrupt Flag"] + #[inline(always)] + pub fn errint(&mut self) -> ErrintW { + ErrintW::new(self, 1) + } + #[doc = "Bit 2 - Bus Off Interrupt Flag"] + #[inline(always)] + pub fn boffint(&mut self) -> BoffintW { + BoffintW::new(self, 2) + } + #[doc = "Bit 16 - RX Warning Interrupt Flag"] + #[inline(always)] + pub fn rwrnint(&mut self) -> RwrnintW { + RwrnintW::new(self, 16) + } + #[doc = "Bit 17 - TX Warning Interrupt Flag"] + #[inline(always)] + pub fn twrnint(&mut self) -> TwrnintW { + TwrnintW::new(self, 17) + } + #[doc = "Bit 19 - Bus Off Done Interrupt Flag"] + #[inline(always)] + pub fn boffdoneint(&mut self) -> BoffdoneintW { + BoffdoneintW::new(self, 19) + } + #[doc = "Bit 20 - Fast Error Interrupt Flag"] + #[inline(always)] + pub fn errint_fast(&mut self) -> ErrintFastW { + ErrintFastW::new(self, 20) + } + #[doc = "Bit 21 - Error Overrun Flag"] + #[inline(always)] + pub fn errovr(&mut self) -> ErrovrW { + ErrovrW::new(self, 21) + } +} +#[doc = "Error and Status 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Esr1Spec; +impl crate::RegisterSpec for Esr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`esr1::R`](R) reader structure"] +impl crate::Readable for Esr1Spec {} +#[doc = "`write(|w| ..)` method takes [`esr1::W`](W) writer structure"] +impl crate::Writable for Esr1Spec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x003b_0007; +} +#[doc = "`reset()` method sets ESR1 to value 0"] +impl crate::Resettable for Esr1Spec {} diff --git a/mcxa276-pac/src/can0/esr2.rs b/mcxa276-pac/src/can0/esr2.rs new file mode 100644 index 000000000..f1ad5f534 --- /dev/null +++ b/mcxa276-pac/src/can0/esr2.rs @@ -0,0 +1,102 @@ +#[doc = "Register `ESR2` reader"] +pub type R = crate::R; +#[doc = "Inactive Message Buffer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Imb { + #[doc = "0: Message buffer indicated by ESR2\\[LPTM\\] is not inactive."] + InactiveMailboxNo = 0, + #[doc = "1: At least one message buffer is inactive."] + InactiveMailboxYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Imb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IMB` reader - Inactive Message Buffer"] +pub type ImbR = crate::BitReader; +impl ImbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Imb { + match self.bits { + false => Imb::InactiveMailboxNo, + true => Imb::InactiveMailboxYes, + } + } + #[doc = "Message buffer indicated by ESR2\\[LPTM\\] is not inactive."] + #[inline(always)] + pub fn is_inactive_mailbox_no(&self) -> bool { + *self == Imb::InactiveMailboxNo + } + #[doc = "At least one message buffer is inactive."] + #[inline(always)] + pub fn is_inactive_mailbox_yes(&self) -> bool { + *self == Imb::InactiveMailboxYes + } +} +#[doc = "Valid Priority Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Vps { + #[doc = "0: Invalid"] + Invalid = 0, + #[doc = "1: Valid"] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Vps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VPS` reader - Valid Priority Status"] +pub type VpsR = crate::BitReader; +impl VpsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Vps { + match self.bits { + false => Vps::Invalid, + true => Vps::Valid, + } + } + #[doc = "Invalid"] + #[inline(always)] + pub fn is_invalid(&self) -> bool { + *self == Vps::Invalid + } + #[doc = "Valid"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Vps::Valid + } +} +#[doc = "Field `LPTM` reader - Lowest Priority TX Message Buffer"] +pub type LptmR = crate::FieldReader; +impl R { + #[doc = "Bit 13 - Inactive Message Buffer"] + #[inline(always)] + pub fn imb(&self) -> ImbR { + ImbR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Valid Priority Status"] + #[inline(always)] + pub fn vps(&self) -> VpsR { + VpsR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 16:22 - Lowest Priority TX Message Buffer"] + #[inline(always)] + pub fn lptm(&self) -> LptmR { + LptmR::new(((self.bits >> 16) & 0x7f) as u8) + } +} +#[doc = "Error and Status 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Esr2Spec; +impl crate::RegisterSpec for Esr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`esr2::R`](R) reader structure"] +impl crate::Readable for Esr2Spec {} +#[doc = "`reset()` method sets ESR2 to value 0"] +impl crate::Resettable for Esr2Spec {} diff --git a/mcxa276-pac/src/can0/etdc.rs b/mcxa276-pac/src/can0/etdc.rs new file mode 100644 index 000000000..63bc0f19e --- /dev/null +++ b/mcxa276-pac/src/can0/etdc.rs @@ -0,0 +1,232 @@ +#[doc = "Register `ETDC` reader"] +pub type R = crate::R; +#[doc = "Register `ETDC` writer"] +pub type W = crate::W; +#[doc = "Field `ETDCVAL` reader - Enhanced Transceiver Delay Compensation Value"] +pub type EtdcvalR = crate::FieldReader; +#[doc = "Transceiver Delay Compensation Fail\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Etdcfail { + #[doc = "0: In range"] + InRange = 0, + #[doc = "1: Out of range"] + OutOfRange = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Etdcfail) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ETDCFAIL` reader - Transceiver Delay Compensation Fail"] +pub type EtdcfailR = crate::BitReader; +impl EtdcfailR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Etdcfail { + match self.bits { + false => Etdcfail::InRange, + true => Etdcfail::OutOfRange, + } + } + #[doc = "In range"] + #[inline(always)] + pub fn is_in_range(&self) -> bool { + *self == Etdcfail::InRange + } + #[doc = "Out of range"] + #[inline(always)] + pub fn is_out_of_range(&self) -> bool { + *self == Etdcfail::OutOfRange + } +} +#[doc = "Field `ETDCFAIL` writer - Transceiver Delay Compensation Fail"] +pub type EtdcfailW<'a, REG> = crate::BitWriter1C<'a, REG, Etdcfail>; +impl<'a, REG> EtdcfailW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "In range"] + #[inline(always)] + pub fn in_range(self) -> &'a mut crate::W { + self.variant(Etdcfail::InRange) + } + #[doc = "Out of range"] + #[inline(always)] + pub fn out_of_range(self) -> &'a mut crate::W { + self.variant(Etdcfail::OutOfRange) + } +} +#[doc = "Field `ETDCOFF` reader - Enhanced Transceiver Delay Compensation Offset"] +pub type EtdcoffR = crate::FieldReader; +#[doc = "Field `ETDCOFF` writer - Enhanced Transceiver Delay Compensation Offset"] +pub type EtdcoffW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Transceiver Delay Measurement Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdmdis { + #[doc = "0: Enable"] + Enable = 0, + #[doc = "1: Disable"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdmdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDMDIS` reader - Transceiver Delay Measurement Disable"] +pub type TdmdisR = crate::BitReader; +impl TdmdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdmdis { + match self.bits { + false => Tdmdis::Enable, + true => Tdmdis::Disable, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tdmdis::Enable + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tdmdis::Disable + } +} +#[doc = "Field `TDMDIS` writer - Transceiver Delay Measurement Disable"] +pub type TdmdisW<'a, REG> = crate::BitWriter<'a, REG, Tdmdis>; +impl<'a, REG> TdmdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tdmdis::Enable) + } + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tdmdis::Disable) + } +} +#[doc = "Transceiver Delay Compensation Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Etdcen { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Etdcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ETDCEN` reader - Transceiver Delay Compensation Enable"] +pub type EtdcenR = crate::BitReader; +impl EtdcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Etdcen { + match self.bits { + false => Etdcen::Disable, + true => Etdcen::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Etdcen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Etdcen::Enable + } +} +#[doc = "Field `ETDCEN` writer - Transceiver Delay Compensation Enable"] +pub type EtdcenW<'a, REG> = crate::BitWriter<'a, REG, Etdcen>; +impl<'a, REG> EtdcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Etdcen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Etdcen::Enable) + } +} +impl R { + #[doc = "Bits 0:7 - Enhanced Transceiver Delay Compensation Value"] + #[inline(always)] + pub fn etdcval(&self) -> EtdcvalR { + EtdcvalR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 15 - Transceiver Delay Compensation Fail"] + #[inline(always)] + pub fn etdcfail(&self) -> EtdcfailR { + EtdcfailR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:22 - Enhanced Transceiver Delay Compensation Offset"] + #[inline(always)] + pub fn etdcoff(&self) -> EtdcoffR { + EtdcoffR::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bit 30 - Transceiver Delay Measurement Disable"] + #[inline(always)] + pub fn tdmdis(&self) -> TdmdisR { + TdmdisR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Transceiver Delay Compensation Enable"] + #[inline(always)] + pub fn etdcen(&self) -> EtdcenR { + EtdcenR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 15 - Transceiver Delay Compensation Fail"] + #[inline(always)] + pub fn etdcfail(&mut self) -> EtdcfailW { + EtdcfailW::new(self, 15) + } + #[doc = "Bits 16:22 - Enhanced Transceiver Delay Compensation Offset"] + #[inline(always)] + pub fn etdcoff(&mut self) -> EtdcoffW { + EtdcoffW::new(self, 16) + } + #[doc = "Bit 30 - Transceiver Delay Measurement Disable"] + #[inline(always)] + pub fn tdmdis(&mut self) -> TdmdisW { + TdmdisW::new(self, 30) + } + #[doc = "Bit 31 - Transceiver Delay Compensation Enable"] + #[inline(always)] + pub fn etdcen(&mut self) -> EtdcenW { + EtdcenW::new(self, 31) + } +} +#[doc = "Enhanced Transceiver Delay Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`etdc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etdc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EtdcSpec; +impl crate::RegisterSpec for EtdcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`etdc::R`](R) reader structure"] +impl crate::Readable for EtdcSpec {} +#[doc = "`write(|w| ..)` method takes [`etdc::W`](W) writer structure"] +impl crate::Writable for EtdcSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000; +} +#[doc = "`reset()` method sets ETDC to value 0"] +impl crate::Resettable for EtdcSpec {} diff --git a/mcxa276-pac/src/can0/fdcbt.rs b/mcxa276-pac/src/can0/fdcbt.rs new file mode 100644 index 000000000..ec76ed206 --- /dev/null +++ b/mcxa276-pac/src/can0/fdcbt.rs @@ -0,0 +1,91 @@ +#[doc = "Register `FDCBT` reader"] +pub type R = crate::R; +#[doc = "Register `FDCBT` writer"] +pub type W = crate::W; +#[doc = "Field `FPSEG2` reader - Fast Phase Segment 2"] +pub type Fpseg2R = crate::FieldReader; +#[doc = "Field `FPSEG2` writer - Fast Phase Segment 2"] +pub type Fpseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `FPSEG1` reader - Fast Phase Segment 1"] +pub type Fpseg1R = crate::FieldReader; +#[doc = "Field `FPSEG1` writer - Fast Phase Segment 1"] +pub type Fpseg1W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `FPROPSEG` reader - Fast Propagation Segment"] +pub type FpropsegR = crate::FieldReader; +#[doc = "Field `FPROPSEG` writer - Fast Propagation Segment"] +pub type FpropsegW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `FRJW` reader - Fast Resync Jump Width"] +pub type FrjwR = crate::FieldReader; +#[doc = "Field `FRJW` writer - Fast Resync Jump Width"] +pub type FrjwW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `FPRESDIV` reader - Fast Prescaler Division Factor"] +pub type FpresdivR = crate::FieldReader; +#[doc = "Field `FPRESDIV` writer - Fast Prescaler Division Factor"] +pub type FpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:2 - Fast Phase Segment 2"] + #[inline(always)] + pub fn fpseg2(&self) -> Fpseg2R { + Fpseg2R::new((self.bits & 7) as u8) + } + #[doc = "Bits 5:7 - Fast Phase Segment 1"] + #[inline(always)] + pub fn fpseg1(&self) -> Fpseg1R { + Fpseg1R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 10:14 - Fast Propagation Segment"] + #[inline(always)] + pub fn fpropseg(&self) -> FpropsegR { + FpropsegR::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bits 16:18 - Fast Resync Jump Width"] + #[inline(always)] + pub fn frjw(&self) -> FrjwR { + FrjwR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 20:29 - Fast Prescaler Division Factor"] + #[inline(always)] + pub fn fpresdiv(&self) -> FpresdivR { + FpresdivR::new(((self.bits >> 20) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Fast Phase Segment 2"] + #[inline(always)] + pub fn fpseg2(&mut self) -> Fpseg2W { + Fpseg2W::new(self, 0) + } + #[doc = "Bits 5:7 - Fast Phase Segment 1"] + #[inline(always)] + pub fn fpseg1(&mut self) -> Fpseg1W { + Fpseg1W::new(self, 5) + } + #[doc = "Bits 10:14 - Fast Propagation Segment"] + #[inline(always)] + pub fn fpropseg(&mut self) -> FpropsegW { + FpropsegW::new(self, 10) + } + #[doc = "Bits 16:18 - Fast Resync Jump Width"] + #[inline(always)] + pub fn frjw(&mut self) -> FrjwW { + FrjwW::new(self, 16) + } + #[doc = "Bits 20:29 - Fast Prescaler Division Factor"] + #[inline(always)] + pub fn fpresdiv(&mut self) -> FpresdivW { + FpresdivW::new(self, 20) + } +} +#[doc = "CAN FD Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdcbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FdcbtSpec; +impl crate::RegisterSpec for FdcbtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fdcbt::R`](R) reader structure"] +impl crate::Readable for FdcbtSpec {} +#[doc = "`write(|w| ..)` method takes [`fdcbt::W`](W) writer structure"] +impl crate::Writable for FdcbtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FDCBT to value 0"] +impl crate::Resettable for FdcbtSpec {} diff --git a/mcxa276-pac/src/can0/fdcrc.rs b/mcxa276-pac/src/can0/fdcrc.rs new file mode 100644 index 000000000..6066b3bbb --- /dev/null +++ b/mcxa276-pac/src/can0/fdcrc.rs @@ -0,0 +1,27 @@ +#[doc = "Register `FDCRC` reader"] +pub type R = crate::R; +#[doc = "Field `FD_TXCRC` reader - Extended Transmitted CRC value"] +pub type FdTxcrcR = crate::FieldReader; +#[doc = "Field `FD_MBCRC` reader - CRC Message Buffer Number for FD_TXCRC"] +pub type FdMbcrcR = crate::FieldReader; +impl R { + #[doc = "Bits 0:20 - Extended Transmitted CRC value"] + #[inline(always)] + pub fn fd_txcrc(&self) -> FdTxcrcR { + FdTxcrcR::new(self.bits & 0x001f_ffff) + } + #[doc = "Bits 24:30 - CRC Message Buffer Number for FD_TXCRC"] + #[inline(always)] + pub fn fd_mbcrc(&self) -> FdMbcrcR { + FdMbcrcR::new(((self.bits >> 24) & 0x7f) as u8) + } +} +#[doc = "CAN FD CRC\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcrc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FdcrcSpec; +impl crate::RegisterSpec for FdcrcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fdcrc::R`](R) reader structure"] +impl crate::Readable for FdcrcSpec {} +#[doc = "`reset()` method sets FDCRC to value 0"] +impl crate::Resettable for FdcrcSpec {} diff --git a/mcxa276-pac/src/can0/fdctrl.rs b/mcxa276-pac/src/can0/fdctrl.rs new file mode 100644 index 000000000..8e1315d39 --- /dev/null +++ b/mcxa276-pac/src/can0/fdctrl.rs @@ -0,0 +1,330 @@ +#[doc = "Register `FDCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `FDCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TDCVAL` reader - Transceiver Delay Compensation Value"] +pub type TdcvalR = crate::FieldReader; +#[doc = "Field `TDCOFF` reader - Transceiver Delay Compensation Offset"] +pub type TdcoffR = crate::FieldReader; +#[doc = "Field `TDCOFF` writer - Transceiver Delay Compensation Offset"] +pub type TdcoffW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Transceiver Delay Compensation Fail\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdcfail { + #[doc = "0: In range"] + InRange = 0, + #[doc = "1: Out of range"] + OutOfRange = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdcfail) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDCFAIL` reader - Transceiver Delay Compensation Fail"] +pub type TdcfailR = crate::BitReader; +impl TdcfailR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdcfail { + match self.bits { + false => Tdcfail::InRange, + true => Tdcfail::OutOfRange, + } + } + #[doc = "In range"] + #[inline(always)] + pub fn is_in_range(&self) -> bool { + *self == Tdcfail::InRange + } + #[doc = "Out of range"] + #[inline(always)] + pub fn is_out_of_range(&self) -> bool { + *self == Tdcfail::OutOfRange + } +} +#[doc = "Field `TDCFAIL` writer - Transceiver Delay Compensation Fail"] +pub type TdcfailW<'a, REG> = crate::BitWriter1C<'a, REG, Tdcfail>; +impl<'a, REG> TdcfailW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "In range"] + #[inline(always)] + pub fn in_range(self) -> &'a mut crate::W { + self.variant(Tdcfail::InRange) + } + #[doc = "Out of range"] + #[inline(always)] + pub fn out_of_range(self) -> &'a mut crate::W { + self.variant(Tdcfail::OutOfRange) + } +} +#[doc = "Transceiver Delay Compensation Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdcen { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDCEN` reader - Transceiver Delay Compensation Enable"] +pub type TdcenR = crate::BitReader; +impl TdcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdcen { + match self.bits { + false => Tdcen::Disable, + true => Tdcen::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tdcen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tdcen::Enable + } +} +#[doc = "Field `TDCEN` writer - Transceiver Delay Compensation Enable"] +pub type TdcenW<'a, REG> = crate::BitWriter<'a, REG, Tdcen>; +impl<'a, REG> TdcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tdcen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tdcen::Enable) + } +} +#[doc = "Message Buffer Data Size for Region 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbdsr0 { + #[doc = "0: 8 bytes"] + R0_8Bytes = 0, + #[doc = "1: 16 bytes"] + R0_16Bytes = 1, + #[doc = "2: 32 bytes"] + R0_32Bytes = 2, + #[doc = "3: 64 bytes"] + R0_64Bytes = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbdsr0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbdsr0 { + type Ux = u8; +} +impl crate::IsEnum for Mbdsr0 {} +#[doc = "Field `MBDSR0` reader - Message Buffer Data Size for Region 0"] +pub type Mbdsr0R = crate::FieldReader; +impl Mbdsr0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbdsr0 { + match self.bits { + 0 => Mbdsr0::R0_8Bytes, + 1 => Mbdsr0::R0_16Bytes, + 2 => Mbdsr0::R0_32Bytes, + 3 => Mbdsr0::R0_64Bytes, + _ => unreachable!(), + } + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn is_r0_8_bytes(&self) -> bool { + *self == Mbdsr0::R0_8Bytes + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn is_r0_16_bytes(&self) -> bool { + *self == Mbdsr0::R0_16Bytes + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn is_r0_32_bytes(&self) -> bool { + *self == Mbdsr0::R0_32Bytes + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn is_r0_64_bytes(&self) -> bool { + *self == Mbdsr0::R0_64Bytes + } +} +#[doc = "Field `MBDSR0` writer - Message Buffer Data Size for Region 0"] +pub type Mbdsr0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Mbdsr0, crate::Safe>; +impl<'a, REG> Mbdsr0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "8 bytes"] + #[inline(always)] + pub fn r0_8_bytes(self) -> &'a mut crate::W { + self.variant(Mbdsr0::R0_8Bytes) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn r0_16_bytes(self) -> &'a mut crate::W { + self.variant(Mbdsr0::R0_16Bytes) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn r0_32_bytes(self) -> &'a mut crate::W { + self.variant(Mbdsr0::R0_32Bytes) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn r0_64_bytes(self) -> &'a mut crate::W { + self.variant(Mbdsr0::R0_64Bytes) + } +} +#[doc = "Bit Rate Switch Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fdrate { + #[doc = "0: Disable"] + Nominal = 0, + #[doc = "1: Enable"] + BitRateSwitching = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fdrate) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FDRATE` reader - Bit Rate Switch Enable"] +pub type FdrateR = crate::BitReader; +impl FdrateR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fdrate { + match self.bits { + false => Fdrate::Nominal, + true => Fdrate::BitRateSwitching, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_nominal(&self) -> bool { + *self == Fdrate::Nominal + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_bit_rate_switching(&self) -> bool { + *self == Fdrate::BitRateSwitching + } +} +#[doc = "Field `FDRATE` writer - Bit Rate Switch Enable"] +pub type FdrateW<'a, REG> = crate::BitWriter<'a, REG, Fdrate>; +impl<'a, REG> FdrateW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn nominal(self) -> &'a mut crate::W { + self.variant(Fdrate::Nominal) + } + #[doc = "Enable"] + #[inline(always)] + pub fn bit_rate_switching(self) -> &'a mut crate::W { + self.variant(Fdrate::BitRateSwitching) + } +} +impl R { + #[doc = "Bits 0:5 - Transceiver Delay Compensation Value"] + #[inline(always)] + pub fn tdcval(&self) -> TdcvalR { + TdcvalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"] + #[inline(always)] + pub fn tdcoff(&self) -> TdcoffR { + TdcoffR::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 14 - Transceiver Delay Compensation Fail"] + #[inline(always)] + pub fn tdcfail(&self) -> TdcfailR { + TdcfailR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Transceiver Delay Compensation Enable"] + #[inline(always)] + pub fn tdcen(&self) -> TdcenR { + TdcenR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"] + #[inline(always)] + pub fn mbdsr0(&self) -> Mbdsr0R { + Mbdsr0R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 31 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn fdrate(&self) -> FdrateR { + FdrateR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"] + #[inline(always)] + pub fn tdcoff(&mut self) -> TdcoffW { + TdcoffW::new(self, 8) + } + #[doc = "Bit 14 - Transceiver Delay Compensation Fail"] + #[inline(always)] + pub fn tdcfail(&mut self) -> TdcfailW { + TdcfailW::new(self, 14) + } + #[doc = "Bit 15 - Transceiver Delay Compensation Enable"] + #[inline(always)] + pub fn tdcen(&mut self) -> TdcenW { + TdcenW::new(self, 15) + } + #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"] + #[inline(always)] + pub fn mbdsr0(&mut self) -> Mbdsr0W { + Mbdsr0W::new(self, 16) + } + #[doc = "Bit 31 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn fdrate(&mut self) -> FdrateW { + FdrateW::new(self, 31) + } +} +#[doc = "CAN FD Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fdctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FdctrlSpec; +impl crate::RegisterSpec for FdctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fdctrl::R`](R) reader structure"] +impl crate::Readable for FdctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`fdctrl::W`](W) writer structure"] +impl crate::Writable for FdctrlSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x4000; +} +#[doc = "`reset()` method sets FDCTRL to value 0x8000_0100"] +impl crate::Resettable for FdctrlSpec { + const RESET_VALUE: u32 = 0x8000_0100; +} diff --git a/mcxa276-pac/src/can0/flt_dlc.rs b/mcxa276-pac/src/can0/flt_dlc.rs new file mode 100644 index 000000000..1a58a1fed --- /dev/null +++ b/mcxa276-pac/src/can0/flt_dlc.rs @@ -0,0 +1,51 @@ +#[doc = "Register `FLT_DLC` reader"] +pub type R = crate::R; +#[doc = "Register `FLT_DLC` writer"] +pub type W = crate::W; +#[doc = "Field `FLT_DLC_HI` reader - Upper Limit for Length of Data Bytes Filter"] +pub type FltDlcHiR = crate::FieldReader; +#[doc = "Field `FLT_DLC_HI` writer - Upper Limit for Length of Data Bytes Filter"] +pub type FltDlcHiW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `FLT_DLC_LO` reader - Lower Limit for Length of Data Bytes Filter"] +pub type FltDlcLoR = crate::FieldReader; +#[doc = "Field `FLT_DLC_LO` writer - Lower Limit for Length of Data Bytes Filter"] +pub type FltDlcLoW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"] + #[inline(always)] + pub fn flt_dlc_hi(&self) -> FltDlcHiR { + FltDlcHiR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"] + #[inline(always)] + pub fn flt_dlc_lo(&self) -> FltDlcLoR { + FltDlcLoR::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"] + #[inline(always)] + pub fn flt_dlc_hi(&mut self) -> FltDlcHiW { + FltDlcHiW::new(self, 0) + } + #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"] + #[inline(always)] + pub fn flt_dlc_lo(&mut self) -> FltDlcLoW { + FltDlcLoW::new(self, 16) + } +} +#[doc = "Pretended Networking Data Length Code (DLC) Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_dlc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_dlc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FltDlcSpec; +impl crate::RegisterSpec for FltDlcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flt_dlc::R`](R) reader structure"] +impl crate::Readable for FltDlcSpec {} +#[doc = "`write(|w| ..)` method takes [`flt_dlc::W`](W) writer structure"] +impl crate::Writable for FltDlcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FLT_DLC to value 0x08"] +impl crate::Resettable for FltDlcSpec { + const RESET_VALUE: u32 = 0x08; +} diff --git a/mcxa276-pac/src/can0/flt_id1.rs b/mcxa276-pac/src/can0/flt_id1.rs new file mode 100644 index 000000000..515c44a7e --- /dev/null +++ b/mcxa276-pac/src/can0/flt_id1.rs @@ -0,0 +1,161 @@ +#[doc = "Register `FLT_ID1` reader"] +pub type R = crate::R; +#[doc = "Register `FLT_ID1` writer"] +pub type W = crate::W; +#[doc = "Field `FLT_ID1` reader - ID Filter 1 for Pretended Networking filtering"] +pub type FltId1R = crate::FieldReader; +#[doc = "Field `FLT_ID1` writer - ID Filter 1 for Pretended Networking filtering"] +pub type FltId1W<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Remote Transmission Request Filter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FltRtr { + #[doc = "0: Reject remote frame (accept data frame)"] + Reject = 0, + #[doc = "1: Accept remote frame"] + Accept = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FltRtr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLT_RTR` reader - Remote Transmission Request Filter"] +pub type FltRtrR = crate::BitReader; +impl FltRtrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FltRtr { + match self.bits { + false => FltRtr::Reject, + true => FltRtr::Accept, + } + } + #[doc = "Reject remote frame (accept data frame)"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + *self == FltRtr::Reject + } + #[doc = "Accept remote frame"] + #[inline(always)] + pub fn is_accept(&self) -> bool { + *self == FltRtr::Accept + } +} +#[doc = "Field `FLT_RTR` writer - Remote Transmission Request Filter"] +pub type FltRtrW<'a, REG> = crate::BitWriter<'a, REG, FltRtr>; +impl<'a, REG> FltRtrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reject remote frame (accept data frame)"] + #[inline(always)] + pub fn reject(self) -> &'a mut crate::W { + self.variant(FltRtr::Reject) + } + #[doc = "Accept remote frame"] + #[inline(always)] + pub fn accept(self) -> &'a mut crate::W { + self.variant(FltRtr::Accept) + } +} +#[doc = "ID Extended Filter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FltIde { + #[doc = "0: Standard"] + Standard = 0, + #[doc = "1: Extended"] + Extended = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FltIde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLT_IDE` reader - ID Extended Filter"] +pub type FltIdeR = crate::BitReader; +impl FltIdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FltIde { + match self.bits { + false => FltIde::Standard, + true => FltIde::Extended, + } + } + #[doc = "Standard"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == FltIde::Standard + } + #[doc = "Extended"] + #[inline(always)] + pub fn is_extended(&self) -> bool { + *self == FltIde::Extended + } +} +#[doc = "Field `FLT_IDE` writer - ID Extended Filter"] +pub type FltIdeW<'a, REG> = crate::BitWriter<'a, REG, FltIde>; +impl<'a, REG> FltIdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard"] + #[inline(always)] + pub fn standard(self) -> &'a mut crate::W { + self.variant(FltIde::Standard) + } + #[doc = "Extended"] + #[inline(always)] + pub fn extended(self) -> &'a mut crate::W { + self.variant(FltIde::Extended) + } +} +impl R { + #[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"] + #[inline(always)] + pub fn flt_id1(&self) -> FltId1R { + FltId1R::new(self.bits & 0x1fff_ffff) + } + #[doc = "Bit 29 - Remote Transmission Request Filter"] + #[inline(always)] + pub fn flt_rtr(&self) -> FltRtrR { + FltRtrR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ID Extended Filter"] + #[inline(always)] + pub fn flt_ide(&self) -> FltIdeR { + FltIdeR::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"] + #[inline(always)] + pub fn flt_id1(&mut self) -> FltId1W { + FltId1W::new(self, 0) + } + #[doc = "Bit 29 - Remote Transmission Request Filter"] + #[inline(always)] + pub fn flt_rtr(&mut self) -> FltRtrW { + FltRtrW::new(self, 29) + } + #[doc = "Bit 30 - ID Extended Filter"] + #[inline(always)] + pub fn flt_ide(&mut self) -> FltIdeW { + FltIdeW::new(self, 30) + } +} +#[doc = "Pretended Networking ID Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FltId1Spec; +impl crate::RegisterSpec for FltId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flt_id1::R`](R) reader structure"] +impl crate::Readable for FltId1Spec {} +#[doc = "`write(|w| ..)` method takes [`flt_id1::W`](W) writer structure"] +impl crate::Writable for FltId1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FLT_ID1 to value 0"] +impl crate::Resettable for FltId1Spec {} diff --git a/mcxa276-pac/src/can0/flt_id2_idmask.rs b/mcxa276-pac/src/can0/flt_id2_idmask.rs new file mode 100644 index 000000000..634def50c --- /dev/null +++ b/mcxa276-pac/src/can0/flt_id2_idmask.rs @@ -0,0 +1,161 @@ +#[doc = "Register `FLT_ID2_IDMASK` reader"] +pub type R = crate::R; +#[doc = "Register `FLT_ID2_IDMASK` writer"] +pub type W = crate::W; +#[doc = "Field `FLT_ID2_IDMASK` reader - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] +pub type FltId2IdmaskR = crate::FieldReader; +#[doc = "Field `FLT_ID2_IDMASK` writer - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] +pub type FltId2IdmaskW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Remote Transmission Request Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RtrMsk { + #[doc = "0: The corresponding bit in the filter is \"don't care.\""] + FrameTypeNo = 0, + #[doc = "1: The corresponding bit in the filter is checked."] + FrameTypeYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RtrMsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RTR_MSK` reader - Remote Transmission Request Mask"] +pub type RtrMskR = crate::BitReader; +impl RtrMskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RtrMsk { + match self.bits { + false => RtrMsk::FrameTypeNo, + true => RtrMsk::FrameTypeYes, + } + } + #[doc = "The corresponding bit in the filter is \"don't care.\""] + #[inline(always)] + pub fn is_frame_type_no(&self) -> bool { + *self == RtrMsk::FrameTypeNo + } + #[doc = "The corresponding bit in the filter is checked."] + #[inline(always)] + pub fn is_frame_type_yes(&self) -> bool { + *self == RtrMsk::FrameTypeYes + } +} +#[doc = "Field `RTR_MSK` writer - Remote Transmission Request Mask"] +pub type RtrMskW<'a, REG> = crate::BitWriter<'a, REG, RtrMsk>; +impl<'a, REG> RtrMskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The corresponding bit in the filter is \"don't care.\""] + #[inline(always)] + pub fn frame_type_no(self) -> &'a mut crate::W { + self.variant(RtrMsk::FrameTypeNo) + } + #[doc = "The corresponding bit in the filter is checked."] + #[inline(always)] + pub fn frame_type_yes(self) -> &'a mut crate::W { + self.variant(RtrMsk::FrameTypeYes) + } +} +#[doc = "ID Extended Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IdeMsk { + #[doc = "0: The corresponding bit in the filter is \"don't care.\""] + FrameFormatNo = 0, + #[doc = "1: The corresponding bit in the filter is checked."] + FrameFormatYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IdeMsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IDE_MSK` reader - ID Extended Mask"] +pub type IdeMskR = crate::BitReader; +impl IdeMskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IdeMsk { + match self.bits { + false => IdeMsk::FrameFormatNo, + true => IdeMsk::FrameFormatYes, + } + } + #[doc = "The corresponding bit in the filter is \"don't care.\""] + #[inline(always)] + pub fn is_frame_format_no(&self) -> bool { + *self == IdeMsk::FrameFormatNo + } + #[doc = "The corresponding bit in the filter is checked."] + #[inline(always)] + pub fn is_frame_format_yes(&self) -> bool { + *self == IdeMsk::FrameFormatYes + } +} +#[doc = "Field `IDE_MSK` writer - ID Extended Mask"] +pub type IdeMskW<'a, REG> = crate::BitWriter<'a, REG, IdeMsk>; +impl<'a, REG> IdeMskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The corresponding bit in the filter is \"don't care.\""] + #[inline(always)] + pub fn frame_format_no(self) -> &'a mut crate::W { + self.variant(IdeMsk::FrameFormatNo) + } + #[doc = "The corresponding bit in the filter is checked."] + #[inline(always)] + pub fn frame_format_yes(self) -> &'a mut crate::W { + self.variant(IdeMsk::FrameFormatYes) + } +} +impl R { + #[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] + #[inline(always)] + pub fn flt_id2_idmask(&self) -> FltId2IdmaskR { + FltId2IdmaskR::new(self.bits & 0x1fff_ffff) + } + #[doc = "Bit 29 - Remote Transmission Request Mask"] + #[inline(always)] + pub fn rtr_msk(&self) -> RtrMskR { + RtrMskR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ID Extended Mask"] + #[inline(always)] + pub fn ide_msk(&self) -> IdeMskR { + IdeMskR::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] + #[inline(always)] + pub fn flt_id2_idmask(&mut self) -> FltId2IdmaskW { + FltId2IdmaskW::new(self, 0) + } + #[doc = "Bit 29 - Remote Transmission Request Mask"] + #[inline(always)] + pub fn rtr_msk(&mut self) -> RtrMskW { + RtrMskW::new(self, 29) + } + #[doc = "Bit 30 - ID Extended Mask"] + #[inline(always)] + pub fn ide_msk(&mut self) -> IdeMskW { + IdeMskW::new(self, 30) + } +} +#[doc = "Pretended Networking ID Filter 2 or ID Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id2_idmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id2_idmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FltId2IdmaskSpec; +impl crate::RegisterSpec for FltId2IdmaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flt_id2_idmask::R`](R) reader structure"] +impl crate::Readable for FltId2IdmaskSpec {} +#[doc = "`write(|w| ..)` method takes [`flt_id2_idmask::W`](W) writer structure"] +impl crate::Writable for FltId2IdmaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FLT_ID2_IDMASK to value 0"] +impl crate::Resettable for FltId2IdmaskSpec {} diff --git a/mcxa276-pac/src/can0/iflag1.rs b/mcxa276-pac/src/can0/iflag1.rs new file mode 100644 index 000000000..deb77b87c --- /dev/null +++ b/mcxa276-pac/src/can0/iflag1.rs @@ -0,0 +1,302 @@ +#[doc = "Register `IFLAG1` reader"] +pub type R = crate::R; +#[doc = "Register `IFLAG1` writer"] +pub type W = crate::W; +#[doc = "Buffer MB0 Interrupt or Clear Legacy FIFO bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Buf0i { + #[doc = "0: MB0 has no occurrence of successfully completed transmission or reception."] + BufferTxRxNotComplete = 0, + #[doc = "1: MB0 has successfully completed transmission or reception."] + BufferTxRxComplete = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Buf0i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUF0I` reader - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] +pub type Buf0iR = crate::BitReader; +impl Buf0iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Buf0i { + match self.bits { + false => Buf0i::BufferTxRxNotComplete, + true => Buf0i::BufferTxRxComplete, + } + } + #[doc = "MB0 has no occurrence of successfully completed transmission or reception."] + #[inline(always)] + pub fn is_buffer_tx_rx_not_complete(&self) -> bool { + *self == Buf0i::BufferTxRxNotComplete + } + #[doc = "MB0 has successfully completed transmission or reception."] + #[inline(always)] + pub fn is_buffer_tx_rx_complete(&self) -> bool { + *self == Buf0i::BufferTxRxComplete + } +} +#[doc = "Field `BUF0I` writer - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] +pub type Buf0iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf0i>; +impl<'a, REG> Buf0iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "MB0 has no occurrence of successfully completed transmission or reception."] + #[inline(always)] + pub fn buffer_tx_rx_not_complete(self) -> &'a mut crate::W { + self.variant(Buf0i::BufferTxRxNotComplete) + } + #[doc = "MB0 has successfully completed transmission or reception."] + #[inline(always)] + pub fn buffer_tx_rx_complete(self) -> &'a mut crate::W { + self.variant(Buf0i::BufferTxRxComplete) + } +} +#[doc = "Field `BUF4TO1I` reader - Buffer MBi Interrupt or Reserved"] +pub type Buf4to1iR = crate::FieldReader; +#[doc = "Field `BUF4TO1I` writer - Buffer MBi Interrupt or Reserved"] +pub type Buf4to1iW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Buffer MB5 Interrupt or Frames available in Legacy RX FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Buf5i { + #[doc = "0: No occurrence of completed transmission or reception, or no frames available"] + Id1 = 0, + #[doc = "1: MB5 completed transmission or reception, or frames available"] + Id2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Buf5i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUF5I` reader - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] +pub type Buf5iR = crate::BitReader; +impl Buf5iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Buf5i { + match self.bits { + false => Buf5i::Id1, + true => Buf5i::Id2, + } + } + #[doc = "No occurrence of completed transmission or reception, or no frames available"] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Buf5i::Id1 + } + #[doc = "MB5 completed transmission or reception, or frames available"] + #[inline(always)] + pub fn is_id2(&self) -> bool { + *self == Buf5i::Id2 + } +} +#[doc = "Field `BUF5I` writer - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] +pub type Buf5iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf5i>; +impl<'a, REG> Buf5iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No occurrence of completed transmission or reception, or no frames available"] + #[inline(always)] + pub fn id1(self) -> &'a mut crate::W { + self.variant(Buf5i::Id1) + } + #[doc = "MB5 completed transmission or reception, or frames available"] + #[inline(always)] + pub fn id2(self) -> &'a mut crate::W { + self.variant(Buf5i::Id2) + } +} +#[doc = "Buffer MB6 Interrupt or Legacy RX FIFO Warning\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Buf6i { + #[doc = "0: No occurrence of MB6 completing transmission or reception, or FIFO not almost full."] + Id1 = 0, + #[doc = "1: MB6 completed transmission or reception, or FIFO almost full."] + Id2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Buf6i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUF6I` reader - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] +pub type Buf6iR = crate::BitReader; +impl Buf6iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Buf6i { + match self.bits { + false => Buf6i::Id1, + true => Buf6i::Id2, + } + } + #[doc = "No occurrence of MB6 completing transmission or reception, or FIFO not almost full."] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Buf6i::Id1 + } + #[doc = "MB6 completed transmission or reception, or FIFO almost full."] + #[inline(always)] + pub fn is_id2(&self) -> bool { + *self == Buf6i::Id2 + } +} +#[doc = "Field `BUF6I` writer - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] +pub type Buf6iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf6i>; +impl<'a, REG> Buf6iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No occurrence of MB6 completing transmission or reception, or FIFO not almost full."] + #[inline(always)] + pub fn id1(self) -> &'a mut crate::W { + self.variant(Buf6i::Id1) + } + #[doc = "MB6 completed transmission or reception, or FIFO almost full."] + #[inline(always)] + pub fn id2(self) -> &'a mut crate::W { + self.variant(Buf6i::Id2) + } +} +#[doc = "Buffer MB7 Interrupt or Legacy RX FIFO Overflow\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Buf7i { + #[doc = "0: No occurrence of MB7 completing transmission or reception, or no FIFO overflow."] + Id1 = 0, + #[doc = "1: MB7 completed transmission or reception, or FIFO overflow."] + Id2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Buf7i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUF7I` reader - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] +pub type Buf7iR = crate::BitReader; +impl Buf7iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Buf7i { + match self.bits { + false => Buf7i::Id1, + true => Buf7i::Id2, + } + } + #[doc = "No occurrence of MB7 completing transmission or reception, or no FIFO overflow."] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Buf7i::Id1 + } + #[doc = "MB7 completed transmission or reception, or FIFO overflow."] + #[inline(always)] + pub fn is_id2(&self) -> bool { + *self == Buf7i::Id2 + } +} +#[doc = "Field `BUF7I` writer - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] +pub type Buf7iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf7i>; +impl<'a, REG> Buf7iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No occurrence of MB7 completing transmission or reception, or no FIFO overflow."] + #[inline(always)] + pub fn id1(self) -> &'a mut crate::W { + self.variant(Buf7i::Id1) + } + #[doc = "MB7 completed transmission or reception, or FIFO overflow."] + #[inline(always)] + pub fn id2(self) -> &'a mut crate::W { + self.variant(Buf7i::Id2) + } +} +#[doc = "Field `BUF31TO8I` reader - Buffer MBi Interrupt"] +pub type Buf31to8iR = crate::FieldReader; +#[doc = "Field `BUF31TO8I` writer - Buffer MBi Interrupt"] +pub type Buf31to8iW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bit 0 - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] + #[inline(always)] + pub fn buf0i(&self) -> Buf0iR { + Buf0iR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:4 - Buffer MBi Interrupt or Reserved"] + #[inline(always)] + pub fn buf4to1i(&self) -> Buf4to1iR { + Buf4to1iR::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 5 - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] + #[inline(always)] + pub fn buf5i(&self) -> Buf5iR { + Buf5iR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] + #[inline(always)] + pub fn buf6i(&self) -> Buf6iR { + Buf6iR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] + #[inline(always)] + pub fn buf7i(&self) -> Buf7iR { + Buf7iR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:31 - Buffer MBi Interrupt"] + #[inline(always)] + pub fn buf31to8i(&self) -> Buf31to8iR { + Buf31to8iR::new((self.bits >> 8) & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] + #[inline(always)] + pub fn buf0i(&mut self) -> Buf0iW { + Buf0iW::new(self, 0) + } + #[doc = "Bits 1:4 - Buffer MBi Interrupt or Reserved"] + #[inline(always)] + pub fn buf4to1i(&mut self) -> Buf4to1iW { + Buf4to1iW::new(self, 1) + } + #[doc = "Bit 5 - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] + #[inline(always)] + pub fn buf5i(&mut self) -> Buf5iW { + Buf5iW::new(self, 5) + } + #[doc = "Bit 6 - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] + #[inline(always)] + pub fn buf6i(&mut self) -> Buf6iW { + Buf6iW::new(self, 6) + } + #[doc = "Bit 7 - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] + #[inline(always)] + pub fn buf7i(&mut self) -> Buf7iW { + Buf7iW::new(self, 7) + } + #[doc = "Bits 8:31 - Buffer MBi Interrupt"] + #[inline(always)] + pub fn buf31to8i(&mut self) -> Buf31to8iW { + Buf31to8iW::new(self, 8) + } +} +#[doc = "Interrupt Flags 1\n\nYou can [`read`](crate::Reg::read) this register and get [`iflag1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iflag1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Iflag1Spec; +impl crate::RegisterSpec for Iflag1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`iflag1::R`](R) reader structure"] +impl crate::Readable for Iflag1Spec {} +#[doc = "`write(|w| ..)` method takes [`iflag1::W`](W) writer structure"] +impl crate::Writable for Iflag1Spec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets IFLAG1 to value 0"] +impl crate::Resettable for Iflag1Spec {} diff --git a/mcxa276-pac/src/can0/imask1.rs b/mcxa276-pac/src/can0/imask1.rs new file mode 100644 index 000000000..5986ccdb8 --- /dev/null +++ b/mcxa276-pac/src/can0/imask1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `IMASK1` reader"] +pub type R = crate::R; +#[doc = "Register `IMASK1` writer"] +pub type W = crate::W; +#[doc = "Field `BUF31TO0M` reader - Buffer MBi Mask"] +pub type Buf31to0mR = crate::FieldReader; +#[doc = "Field `BUF31TO0M` writer - Buffer MBi Mask"] +pub type Buf31to0mW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Buffer MBi Mask"] + #[inline(always)] + pub fn buf31to0m(&self) -> Buf31to0mR { + Buf31to0mR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Buffer MBi Mask"] + #[inline(always)] + pub fn buf31to0m(&mut self) -> Buf31to0mW { + Buf31to0mW::new(self, 0) + } +} +#[doc = "Interrupt Masks 1\n\nYou can [`read`](crate::Reg::read) this register and get [`imask1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imask1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Imask1Spec; +impl crate::RegisterSpec for Imask1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`imask1::R`](R) reader structure"] +impl crate::Readable for Imask1Spec {} +#[doc = "`write(|w| ..)` method takes [`imask1::W`](W) writer structure"] +impl crate::Writable for Imask1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IMASK1 to value 0"] +impl crate::Resettable for Imask1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs new file mode 100644 index 000000000..c29340f74 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB0_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb0_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb0_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb0_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb0_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb0_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs new file mode 100644 index 000000000..e19ad4c67 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB0_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb0_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb0_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb0_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb0_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb0_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs new file mode 100644 index 000000000..332317c9b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb0_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb0_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb0_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb0_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb0_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs new file mode 100644 index 000000000..0fab7b675 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb0_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb0_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb0_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb0_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb0_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs new file mode 100644 index 000000000..29222b9a0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb0_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb0_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb0_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb0_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb0_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs new file mode 100644 index 000000000..575981d40 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb0_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb0_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb0_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb0_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb0_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs new file mode 100644 index 000000000..430e55b50 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB10_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb10_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb10_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb10_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb10_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb10_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs new file mode 100644 index 000000000..2922c6d28 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB10_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb10_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb10_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb10_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb10_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb10_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word0.rs new file mode 100644 index 000000000..7ab1489bc --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb10_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb10_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb10_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb10_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb10_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word1.rs new file mode 100644 index 000000000..953a98e59 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb10_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb10_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb10_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb10_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb10_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word2.rs new file mode 100644 index 000000000..6204cc1a3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb10_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb10_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb10_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb10_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb10_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word3.rs new file mode 100644 index 000000000..680442f7b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb10_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb10_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb10_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb10_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb10_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs new file mode 100644 index 000000000..b22de9f28 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB11_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb11_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb11_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb11_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb11_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb11_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs new file mode 100644 index 000000000..125c596e1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB11_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb11_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb11_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb11_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb11_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb11_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word0.rs new file mode 100644 index 000000000..785ed8be5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb11_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb11_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb11_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb11_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb11_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word1.rs new file mode 100644 index 000000000..c3965cf1a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb11_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb11_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb11_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb11_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb11_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word2.rs new file mode 100644 index 000000000..c660785c8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb11_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb11_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb11_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb11_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb11_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word3.rs new file mode 100644 index 000000000..07a278f42 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb11_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb11_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb11_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb11_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb11_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs new file mode 100644 index 000000000..24585d132 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB12_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb12_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb12_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb12_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb12_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb12_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs new file mode 100644 index 000000000..8a69cf7c0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB12_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb12_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb12_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb12_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb12_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb12_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word0.rs new file mode 100644 index 000000000..8b41e97b4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB12_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb12_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb12_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb12_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb12_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb12_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word1.rs new file mode 100644 index 000000000..d436e50b9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB12_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb12_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb12_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb12_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb12_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb12_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word2.rs new file mode 100644 index 000000000..2e7612119 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB12_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb12_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb12_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb12_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb12_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb12_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word3.rs new file mode 100644 index 000000000..a5a152f17 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB12_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb12_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb12_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb12_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb12_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb12_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_cs.rs new file mode 100644 index 000000000..7ceb531c7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB13_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb13_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb13_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb13_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb13_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb13_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_id.rs new file mode 100644 index 000000000..0b46483f9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB13_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb13_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb13_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb13_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb13_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb13_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word0.rs new file mode 100644 index 000000000..c41f50217 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB13_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb13_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb13_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb13_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb13_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb13_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word1.rs new file mode 100644 index 000000000..6970b5615 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB13_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb13_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb13_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb13_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb13_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb13_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word2.rs new file mode 100644 index 000000000..3fea5973a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB13_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb13_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb13_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb13_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb13_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb13_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word3.rs new file mode 100644 index 000000000..5d3b410ca --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB13_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb13_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb13_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb13_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb13_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb13_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_cs.rs new file mode 100644 index 000000000..948fd734f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB14_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb14_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb14_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb14_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb14_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb14_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_id.rs new file mode 100644 index 000000000..080ea3d76 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB14_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb14_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb14_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb14_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb14_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb14_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word0.rs new file mode 100644 index 000000000..fe975bc76 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB14_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb14_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb14_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb14_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb14_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb14_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word1.rs new file mode 100644 index 000000000..e2b11b779 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB14_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb14_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb14_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb14_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb14_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb14_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word2.rs new file mode 100644 index 000000000..f90366aeb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB14_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb14_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb14_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb14_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb14_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb14_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word3.rs new file mode 100644 index 000000000..3827e0cce --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB14_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb14_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb14_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb14_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb14_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb14_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_cs.rs new file mode 100644 index 000000000..1fdc8daba --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB15_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb15_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb15_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb15_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb15_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb15_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_id.rs new file mode 100644 index 000000000..b4bf7a53e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB15_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb15_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb15_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb15_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb15_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb15_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word0.rs new file mode 100644 index 000000000..cda954a25 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB15_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb15_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb15_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb15_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb15_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb15_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word1.rs new file mode 100644 index 000000000..91947932e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB15_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb15_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb15_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb15_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb15_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb15_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word2.rs new file mode 100644 index 000000000..315a6e7f7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB15_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb15_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb15_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb15_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb15_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb15_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word3.rs new file mode 100644 index 000000000..e27cf31ab --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB15_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb15_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb15_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb15_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb15_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb15_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_cs.rs new file mode 100644 index 000000000..d9a648edf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB16_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb16_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb16_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb16_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb16_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb16_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs new file mode 100644 index 000000000..1af53e305 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB16_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb16_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb16_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb16_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb16_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb16_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word0.rs new file mode 100644 index 000000000..e8bffa515 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB16_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb16_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb16_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb16_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb16_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb16_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word1.rs new file mode 100644 index 000000000..f0f249b26 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB16_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb16_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb16_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb16_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb16_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb16_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word2.rs new file mode 100644 index 000000000..b49cee5c9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB16_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb16_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb16_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb16_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb16_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb16_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word3.rs new file mode 100644 index 000000000..34b90351a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB16_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb16_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb16_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb16_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb16_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb16_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs new file mode 100644 index 000000000..224e1cf7f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB17_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb17_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb17_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb17_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb17_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb17_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs new file mode 100644 index 000000000..fa139a9e7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB17_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb17_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb17_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb17_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb17_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb17_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word0.rs new file mode 100644 index 000000000..e14f01a0c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB17_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb17_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb17_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb17_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb17_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb17_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word1.rs new file mode 100644 index 000000000..64455ba31 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB17_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb17_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb17_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb17_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb17_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb17_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word2.rs new file mode 100644 index 000000000..d80679cf8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB17_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb17_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb17_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb17_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb17_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb17_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word3.rs new file mode 100644 index 000000000..4c13c6b41 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB17_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb17_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb17_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb17_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb17_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb17_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs new file mode 100644 index 000000000..4ad2f753d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB18_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb18_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb18_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb18_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb18_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb18_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs new file mode 100644 index 000000000..4399fe2a3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB18_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb18_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb18_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb18_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb18_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb18_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word0.rs new file mode 100644 index 000000000..c6cad94d4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB18_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb18_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb18_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb18_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb18_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb18_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word1.rs new file mode 100644 index 000000000..b8c414931 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB18_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb18_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb18_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb18_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb18_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb18_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word2.rs new file mode 100644 index 000000000..eaf1e0fe3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB18_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb18_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb18_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb18_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb18_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb18_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word3.rs new file mode 100644 index 000000000..2650e0bcf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB18_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb18_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb18_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb18_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb18_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb18_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs new file mode 100644 index 000000000..5e511d69c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB19_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb19_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb19_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb19_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb19_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb19_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_id.rs new file mode 100644 index 000000000..ce7080934 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB19_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb19_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb19_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb19_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb19_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb19_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word0.rs new file mode 100644 index 000000000..3c487ef19 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB19_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb19_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb19_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb19_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb19_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb19_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word1.rs new file mode 100644 index 000000000..e0e0aedba --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB19_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb19_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb19_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb19_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb19_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb19_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word2.rs new file mode 100644 index 000000000..d2d99ba39 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB19_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb19_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb19_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb19_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb19_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb19_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word3.rs new file mode 100644 index 000000000..00767ff58 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB19_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb19_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb19_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb19_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb19_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb19_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_cs.rs new file mode 100644 index 000000000..cb7efd9ae --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB1_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb1_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb1_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb1_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb1_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb1_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_id.rs new file mode 100644 index 000000000..259e9f19a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB1_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb1_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb1_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb1_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb1_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb1_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word0.rs new file mode 100644 index 000000000..f21e2d94d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb1_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb1_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb1_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb1_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb1_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word1.rs new file mode 100644 index 000000000..0c15b09b5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb1_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb1_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb1_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb1_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb1_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word2.rs new file mode 100644 index 000000000..c04cb3992 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb1_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb1_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb1_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb1_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb1_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word3.rs new file mode 100644 index 000000000..c9ecc19ac --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb1_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb1_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb1_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb1_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb1_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_cs.rs new file mode 100644 index 000000000..ab229e3db --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB20_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb20_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb20_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb20_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb20_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb20_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_id.rs new file mode 100644 index 000000000..d8fb8761d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB20_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb20_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb20_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb20_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb20_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb20_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word0.rs new file mode 100644 index 000000000..b637d1854 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB20_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb20_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb20_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb20_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb20_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb20_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word1.rs new file mode 100644 index 000000000..9c30a9bc9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB20_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb20_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb20_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb20_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb20_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb20_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word2.rs new file mode 100644 index 000000000..783d96107 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB20_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb20_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb20_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb20_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb20_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb20_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word3.rs new file mode 100644 index 000000000..bc4df50d1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB20_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb20_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb20_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb20_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb20_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb20_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_cs.rs new file mode 100644 index 000000000..2d5dfb6b2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB2_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb2_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb2_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb2_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb2_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb2_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_id.rs new file mode 100644 index 000000000..68ee1b1cc --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB2_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb2_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb2_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb2_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb2_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb2_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word0.rs new file mode 100644 index 000000000..a7e570efa --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb2_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb2_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb2_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb2_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb2_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word1.rs new file mode 100644 index 000000000..e28b201fe --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb2_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb2_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb2_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb2_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb2_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word2.rs new file mode 100644 index 000000000..f7f8e46aa --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb2_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb2_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb2_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb2_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb2_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word3.rs new file mode 100644 index 000000000..4eb044066 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb2_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb2_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb2_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb2_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb2_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_cs.rs new file mode 100644 index 000000000..058fe743b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB3_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb3_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb3_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb3_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb3_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb3_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_id.rs new file mode 100644 index 000000000..b67b967ba --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB3_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb3_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb3_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb3_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb3_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb3_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word0.rs new file mode 100644 index 000000000..9054eeb51 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb3_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb3_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb3_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb3_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb3_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word1.rs new file mode 100644 index 000000000..fa3770840 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb3_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb3_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb3_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb3_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb3_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word2.rs new file mode 100644 index 000000000..f14b5778c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb3_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb3_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb3_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb3_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb3_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word3.rs new file mode 100644 index 000000000..c04a9c2fe --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb3_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb3_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb3_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb3_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb3_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_cs.rs new file mode 100644 index 000000000..42d4eb98c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB4_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb4_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb4_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb4_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb4_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb4_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_id.rs new file mode 100644 index 000000000..287d2806b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB4_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb4_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb4_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb4_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb4_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb4_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word0.rs new file mode 100644 index 000000000..761e0aceb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb4_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb4_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb4_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb4_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb4_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word1.rs new file mode 100644 index 000000000..a4bd9817e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb4_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb4_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb4_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb4_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb4_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word2.rs new file mode 100644 index 000000000..6f26be3ea --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb4_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb4_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb4_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb4_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb4_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word3.rs new file mode 100644 index 000000000..862656876 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb4_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb4_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb4_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb4_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb4_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_cs.rs new file mode 100644 index 000000000..d4ff540db --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB5_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb5_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb5_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb5_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb5_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb5_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_id.rs new file mode 100644 index 000000000..eb4cfd3e6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB5_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb5_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb5_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb5_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb5_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb5_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word0.rs new file mode 100644 index 000000000..d7105b181 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb5_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb5_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb5_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb5_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb5_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word1.rs new file mode 100644 index 000000000..4e7398430 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb5_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb5_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb5_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb5_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb5_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word2.rs new file mode 100644 index 000000000..f1c0145e2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb5_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb5_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb5_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb5_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb5_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word3.rs new file mode 100644 index 000000000..df620238b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb5_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb5_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb5_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb5_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb5_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_cs.rs new file mode 100644 index 000000000..215142dc9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB6_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb6_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb6_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb6_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb6_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb6_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_id.rs new file mode 100644 index 000000000..d9806f764 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB6_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb6_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb6_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb6_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb6_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb6_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word0.rs new file mode 100644 index 000000000..39236f1a8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb6_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb6_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb6_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb6_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb6_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word1.rs new file mode 100644 index 000000000..8ea4c1185 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb6_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb6_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb6_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb6_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb6_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word2.rs new file mode 100644 index 000000000..0367a8d13 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb6_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb6_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb6_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb6_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb6_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word3.rs new file mode 100644 index 000000000..d96e8e741 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb6_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb6_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb6_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb6_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb6_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_cs.rs new file mode 100644 index 000000000..e5b0cb760 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB7_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb7_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb7_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb7_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb7_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb7_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_id.rs new file mode 100644 index 000000000..1d04c519b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB7_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb7_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb7_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb7_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb7_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb7_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word0.rs new file mode 100644 index 000000000..78f1549a2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb7_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb7_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb7_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb7_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb7_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word1.rs new file mode 100644 index 000000000..f161f9bca --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb7_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb7_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb7_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb7_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb7_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word2.rs new file mode 100644 index 000000000..7b6d45f9d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb7_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb7_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb7_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb7_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb7_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word3.rs new file mode 100644 index 000000000..3bea26157 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb7_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb7_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb7_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb7_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb7_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_cs.rs new file mode 100644 index 000000000..c2801f800 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB8_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb8_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb8_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb8_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb8_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb8_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_id.rs new file mode 100644 index 000000000..1f95b479d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB8_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb8_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb8_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb8_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb8_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb8_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word0.rs new file mode 100644 index 000000000..d8d277abc --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb8_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb8_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb8_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb8_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb8_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word1.rs new file mode 100644 index 000000000..e54d7a788 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb8_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb8_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb8_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb8_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb8_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word2.rs new file mode 100644 index 000000000..186ccb68c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb8_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb8_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb8_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb8_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb8_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word3.rs new file mode 100644 index 000000000..3e39d7f33 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb8_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb8_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb8_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb8_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb8_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_cs.rs new file mode 100644 index 000000000..17e9c958a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB9_16B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_16B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb9_16bCsSpec; +impl crate::RegisterSpec for Mb16bGroupMb9_16bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_cs::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb9_16bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_cs::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb9_16bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_16B_CS to value 0"] +impl crate::Resettable for Mb16bGroupMb9_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_id.rs new file mode 100644 index 000000000..9ed56573a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB9_16B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_16B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb9_16bIdSpec; +impl crate::RegisterSpec for Mb16bGroupMb9_16bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_id::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb9_16bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_id::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb9_16bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_16B_ID to value 0"] +impl crate::Resettable for Mb16bGroupMb9_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word0.rs new file mode 100644 index 000000000..e981fa693 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_16B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_16B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb9_16bWord0Spec; +impl crate::RegisterSpec for Mb16bGroupMb9_16bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word0::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb9_16bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word0::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb9_16bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_16B_WORD0 to value 0"] +impl crate::Resettable for Mb16bGroupMb9_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word1.rs new file mode 100644 index 000000000..b73f4b095 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_16B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_16B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb9_16bWord1Spec; +impl crate::RegisterSpec for Mb16bGroupMb9_16bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word1::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb9_16bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word1::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb9_16bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_16B_WORD1 to value 0"] +impl crate::Resettable for Mb16bGroupMb9_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word2.rs new file mode 100644 index 000000000..9c42757b2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_16B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_16B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb9_16bWord2Spec; +impl crate::RegisterSpec for Mb16bGroupMb9_16bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word2::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb9_16bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word2::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb9_16bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_16B_WORD2 to value 0"] +impl crate::Resettable for Mb16bGroupMb9_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word3.rs new file mode 100644 index 000000000..d25fc7766 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_16B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_16B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb16bGroupMb9_16bWord3Spec; +impl crate::RegisterSpec for Mb16bGroupMb9_16bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word3::R`](R) reader structure"] +impl crate::Readable for Mb16bGroupMb9_16bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word3::W`](W) writer structure"] +impl crate::Writable for Mb16bGroupMb9_16bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_16B_WORD3 to value 0"] +impl crate::Resettable for Mb16bGroupMb9_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_cs.rs new file mode 100644 index 000000000..467d57757 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB0_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_id.rs new file mode 100644 index 000000000..79f2779b4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB0_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word0.rs new file mode 100644 index 000000000..a387d6732 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word1.rs new file mode 100644 index 000000000..432439a3e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word2.rs new file mode 100644 index 000000000..129b48cfd --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word3.rs new file mode 100644 index 000000000..25971d452 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word4.rs new file mode 100644 index 000000000..10c434dd6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word5.rs new file mode 100644 index 000000000..990bf3d05 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word6.rs new file mode 100644 index 000000000..246952dbb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word7.rs new file mode 100644 index 000000000..604431468 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb0_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb0_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb0_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb0_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb0_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_cs.rs new file mode 100644 index 000000000..4f1e20248 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB10_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_id.rs new file mode 100644 index 000000000..1acb1da9c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB10_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word0.rs new file mode 100644 index 000000000..656e177e1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word1.rs new file mode 100644 index 000000000..3f3c8e3dd --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word2.rs new file mode 100644 index 000000000..e1dbdd349 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word3.rs new file mode 100644 index 000000000..6f196e1a3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word4.rs new file mode 100644 index 000000000..92474dc28 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word5.rs new file mode 100644 index 000000000..b0ffed129 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word6.rs new file mode 100644 index 000000000..8ff483249 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word7.rs new file mode 100644 index 000000000..637c8e200 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb10_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb10_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb10_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb10_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb10_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_cs.rs new file mode 100644 index 000000000..36b1a5555 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB11_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_id.rs new file mode 100644 index 000000000..8f9d7c60f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB11_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word0.rs new file mode 100644 index 000000000..ca8d38f71 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word1.rs new file mode 100644 index 000000000..1a3069b3a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word2.rs new file mode 100644 index 000000000..c05130819 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word3.rs new file mode 100644 index 000000000..b5f8fc0ae --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word4.rs new file mode 100644 index 000000000..6b4e2b511 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word5.rs new file mode 100644 index 000000000..aab54a566 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word6.rs new file mode 100644 index 000000000..ff793261e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word7.rs new file mode 100644 index 000000000..ab589dec3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb11_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb11_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb11_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb11_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb11_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_cs.rs new file mode 100644 index 000000000..23f4f08b7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB1_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_id.rs new file mode 100644 index 000000000..086617499 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB1_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word0.rs new file mode 100644 index 000000000..e5f5035f0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word1.rs new file mode 100644 index 000000000..08a95adc0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word2.rs new file mode 100644 index 000000000..d83ee61bf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word3.rs new file mode 100644 index 000000000..48b94082a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word4.rs new file mode 100644 index 000000000..a343fac56 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word5.rs new file mode 100644 index 000000000..910ac5f43 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word6.rs new file mode 100644 index 000000000..e137c129a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word7.rs new file mode 100644 index 000000000..2c6e371ec --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb1_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb1_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb1_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb1_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb1_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_cs.rs new file mode 100644 index 000000000..988c5f86c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB2_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_id.rs new file mode 100644 index 000000000..2906375c2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB2_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word0.rs new file mode 100644 index 000000000..2f4965a78 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word1.rs new file mode 100644 index 000000000..f48b2ee62 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word2.rs new file mode 100644 index 000000000..b422f8cce --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word3.rs new file mode 100644 index 000000000..5e2914bc6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word4.rs new file mode 100644 index 000000000..d85b8ecac --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word5.rs new file mode 100644 index 000000000..3d17bd888 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word6.rs new file mode 100644 index 000000000..cf72152d9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word7.rs new file mode 100644 index 000000000..968f8b0b0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb2_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb2_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb2_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb2_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb2_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_cs.rs new file mode 100644 index 000000000..d33d57e28 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB3_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_id.rs new file mode 100644 index 000000000..569d47314 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB3_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word0.rs new file mode 100644 index 000000000..e46841da9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word1.rs new file mode 100644 index 000000000..5a19c29e6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word2.rs new file mode 100644 index 000000000..25fd22c8d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word3.rs new file mode 100644 index 000000000..660694e3e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word4.rs new file mode 100644 index 000000000..6c0f0c5fd --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word5.rs new file mode 100644 index 000000000..92c575bbf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word6.rs new file mode 100644 index 000000000..e53f9efa5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word7.rs new file mode 100644 index 000000000..9b933c07f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb3_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb3_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb3_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb3_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb3_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_cs.rs new file mode 100644 index 000000000..5b6cfcc36 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB4_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_id.rs new file mode 100644 index 000000000..afb2e5fc4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB4_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word0.rs new file mode 100644 index 000000000..ef7d272ee --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word1.rs new file mode 100644 index 000000000..e56910867 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word2.rs new file mode 100644 index 000000000..5de3df94f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word3.rs new file mode 100644 index 000000000..c4e211cc0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word4.rs new file mode 100644 index 000000000..0819e875c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word5.rs new file mode 100644 index 000000000..e8c491f85 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word6.rs new file mode 100644 index 000000000..977da0c17 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word7.rs new file mode 100644 index 000000000..37efefcab --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb4_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb4_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb4_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb4_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb4_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_cs.rs new file mode 100644 index 000000000..e87b29f90 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB5_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_id.rs new file mode 100644 index 000000000..145ab2a68 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB5_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word0.rs new file mode 100644 index 000000000..c3bf8fba4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word1.rs new file mode 100644 index 000000000..577ece605 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word2.rs new file mode 100644 index 000000000..d036cabe7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word3.rs new file mode 100644 index 000000000..f5129b317 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word4.rs new file mode 100644 index 000000000..b5af7b961 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word5.rs new file mode 100644 index 000000000..d538364c5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word6.rs new file mode 100644 index 000000000..6a280cf42 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word7.rs new file mode 100644 index 000000000..a60a19bb4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb5_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb5_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb5_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb5_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb5_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_cs.rs new file mode 100644 index 000000000..fd6908b79 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB6_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_id.rs new file mode 100644 index 000000000..9cfe777a0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB6_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word0.rs new file mode 100644 index 000000000..24f7b47f9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word1.rs new file mode 100644 index 000000000..632c1c1a8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word2.rs new file mode 100644 index 000000000..fac2552ed --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word3.rs new file mode 100644 index 000000000..bb31710f3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word4.rs new file mode 100644 index 000000000..69e7bfb9e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word5.rs new file mode 100644 index 000000000..20fe09611 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word6.rs new file mode 100644 index 000000000..e80370b2b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word7.rs new file mode 100644 index 000000000..49736d108 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb6_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb6_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb6_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb6_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb6_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_cs.rs new file mode 100644 index 000000000..0aa1b1fae --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB7_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_id.rs new file mode 100644 index 000000000..8ba4363d0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB7_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word0.rs new file mode 100644 index 000000000..c2d3a2f33 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word1.rs new file mode 100644 index 000000000..362a42282 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word2.rs new file mode 100644 index 000000000..05a753799 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word3.rs new file mode 100644 index 000000000..fc71a3a73 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word4.rs new file mode 100644 index 000000000..7a1beb53d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word5.rs new file mode 100644 index 000000000..3a90c35af --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word6.rs new file mode 100644 index 000000000..4296781ac --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word7.rs new file mode 100644 index 000000000..663482e2a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb7_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb7_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb7_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb7_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb7_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_cs.rs new file mode 100644 index 000000000..3c6c91e4f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB8_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_id.rs new file mode 100644 index 000000000..b7a836be3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB8_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word0.rs new file mode 100644 index 000000000..ce539c14a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word1.rs new file mode 100644 index 000000000..532fd7383 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word2.rs new file mode 100644 index 000000000..e3661723c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word3.rs new file mode 100644 index 000000000..6e9e51eaa --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word4.rs new file mode 100644 index 000000000..8bdf9b5fb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word5.rs new file mode 100644 index 000000000..224f5c3fa --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word6.rs new file mode 100644 index 000000000..54da88f10 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word7.rs new file mode 100644 index 000000000..1bffb4321 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb8_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb8_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb8_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb8_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb8_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_cs.rs new file mode 100644 index 000000000..da396702e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB9_32B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bCsSpec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_cs::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_cs::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_CS to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_id.rs new file mode 100644 index 000000000..23e966337 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB9_32B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bIdSpec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_id::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_id::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_ID to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word0.rs new file mode 100644 index 000000000..2fdc71d30 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord0Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word0::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word0::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD0 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word1.rs new file mode 100644 index 000000000..6141a6833 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord1Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word1::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word1::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD1 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word2.rs new file mode 100644 index 000000000..e74137add --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord2Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word2::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word2::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD2 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word3.rs new file mode 100644 index 000000000..baee3cf8b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord3Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word3::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word3::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD3 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word4.rs new file mode 100644 index 000000000..b3031a494 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord4Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word4::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word4::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD4 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word5.rs new file mode 100644 index 000000000..35b8ec062 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord5Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word5::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word5::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD5 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word6.rs new file mode 100644 index 000000000..46bed45fc --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord6Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word6::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word6::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD6 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word7.rs new file mode 100644 index 000000000..b048c142a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_32B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_32B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb32bGroupMb9_32bWord7Spec; +impl crate::RegisterSpec for Mb32bGroupMb9_32bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word7::R`](R) reader structure"] +impl crate::Readable for Mb32bGroupMb9_32bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word7::W`](W) writer structure"] +impl crate::Writable for Mb32bGroupMb9_32bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_32B_WORD7 to value 0"] +impl crate::Resettable for Mb32bGroupMb9_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_cs.rs new file mode 100644 index 000000000..e472bf9b2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB0_64B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bCsSpec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_cs::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_cs::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_CS to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_id.rs new file mode 100644 index 000000000..e7ec8fc22 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB0_64B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bIdSpec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_id::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_id::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_ID to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word0.rs new file mode 100644 index 000000000..52b560d2a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord0Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word0::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word0::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD0 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word1.rs new file mode 100644 index 000000000..db57f1a9f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord1Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word1::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word1::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD1 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word10.rs new file mode 100644 index 000000000..80571ca7e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte43R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte42R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte41R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte40R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&self) -> DataByte43R { + DataByte43R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&self) -> DataByte42R { + DataByte42R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&self) -> DataByte41R { + DataByte41R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&self) -> DataByte40R { + DataByte40R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&mut self) -> DataByte43W { + DataByte43W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&mut self) -> DataByte42W { + DataByte42W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&mut self) -> DataByte41W { + DataByte41W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&mut self) -> DataByte40W { + DataByte40W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord10Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word10::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word10::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD10 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word11.rs new file mode 100644 index 000000000..57f152338 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte47R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte46R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte45R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte44R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&self) -> DataByte47R { + DataByte47R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&self) -> DataByte46R { + DataByte46R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&self) -> DataByte45R { + DataByte45R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&self) -> DataByte44R { + DataByte44R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&mut self) -> DataByte47W { + DataByte47W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&mut self) -> DataByte46W { + DataByte46W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&mut self) -> DataByte45W { + DataByte45W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&mut self) -> DataByte44W { + DataByte44W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord11Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word11::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word11::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD11 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word12.rs new file mode 100644 index 000000000..d40138602 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte51R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte50R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte49R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte48R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&self) -> DataByte51R { + DataByte51R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&self) -> DataByte50R { + DataByte50R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&self) -> DataByte49R { + DataByte49R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&self) -> DataByte48R { + DataByte48R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&mut self) -> DataByte51W { + DataByte51W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&mut self) -> DataByte50W { + DataByte50W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&mut self) -> DataByte49W { + DataByte49W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&mut self) -> DataByte48W { + DataByte48W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord12Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word12::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word12::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD12 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word13.rs new file mode 100644 index 000000000..19a217728 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte55R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte54R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte53R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte52R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&self) -> DataByte55R { + DataByte55R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&self) -> DataByte54R { + DataByte54R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&self) -> DataByte53R { + DataByte53R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&self) -> DataByte52R { + DataByte52R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&mut self) -> DataByte55W { + DataByte55W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&mut self) -> DataByte54W { + DataByte54W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&mut self) -> DataByte53W { + DataByte53W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&mut self) -> DataByte52W { + DataByte52W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord13Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word13::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word13::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD13 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word14.rs new file mode 100644 index 000000000..4152a3698 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte59R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte58R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte57R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte56R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&self) -> DataByte59R { + DataByte59R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&self) -> DataByte58R { + DataByte58R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&self) -> DataByte57R { + DataByte57R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&self) -> DataByte56R { + DataByte56R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&mut self) -> DataByte59W { + DataByte59W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&mut self) -> DataByte58W { + DataByte58W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&mut self) -> DataByte57W { + DataByte57W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&mut self) -> DataByte56W { + DataByte56W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord14Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word14::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word14::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD14 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word15.rs new file mode 100644 index 000000000..84551327c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte63R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte62R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte61R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte60R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&self) -> DataByte63R { + DataByte63R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&self) -> DataByte62R { + DataByte62R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&self) -> DataByte61R { + DataByte61R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&self) -> DataByte60R { + DataByte60R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&mut self) -> DataByte63W { + DataByte63W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&mut self) -> DataByte62W { + DataByte62W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&mut self) -> DataByte61W { + DataByte61W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&mut self) -> DataByte60W { + DataByte60W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord15Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word15::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word15::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD15 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word2.rs new file mode 100644 index 000000000..11224e817 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord2Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word2::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word2::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD2 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word3.rs new file mode 100644 index 000000000..518e81e10 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord3Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word3::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word3::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD3 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word4.rs new file mode 100644 index 000000000..00a7b21a5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord4Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word4::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word4::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD4 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word5.rs new file mode 100644 index 000000000..7fa733ead --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord5Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word5::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word5::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD5 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word6.rs new file mode 100644 index 000000000..d84ec29a8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord6Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word6::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word6::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD6 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word7.rs new file mode 100644 index 000000000..e7316091d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord7Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word7::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word7::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD7 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word8.rs new file mode 100644 index 000000000..c98cba9bb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word8.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD8` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte35R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte34R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte33R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte32R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&self) -> DataByte35R { + DataByte35R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&self) -> DataByte34R { + DataByte34R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&self) -> DataByte33R { + DataByte33R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&self) -> DataByte32R { + DataByte32R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&mut self) -> DataByte35W { + DataByte35W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&mut self) -> DataByte34W { + DataByte34W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&mut self) -> DataByte33W { + DataByte33W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&mut self) -> DataByte32W { + DataByte32W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord8Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word8::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word8::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD8 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word9.rs new file mode 100644 index 000000000..853c59ac9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word9.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_64B_WORD9` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_64B_WORD9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte39R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte38R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte37R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte36R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&self) -> DataByte39R { + DataByte39R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&self) -> DataByte38R { + DataByte38R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&self) -> DataByte37R { + DataByte37R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&self) -> DataByte36R { + DataByte36R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&mut self) -> DataByte39W { + DataByte39W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&mut self) -> DataByte38W { + DataByte38W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&mut self) -> DataByte37W { + DataByte37W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&mut self) -> DataByte36W { + DataByte36W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb0_64bWord9Spec; +impl crate::RegisterSpec for Mb64bGroupMb0_64bWord9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word9::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb0_64bWord9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word9::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb0_64bWord9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_64B_WORD9 to value 0"] +impl crate::Resettable for Mb64bGroupMb0_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_cs.rs new file mode 100644 index 000000000..332b83754 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB1_64B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bCsSpec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_cs::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_cs::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_CS to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_id.rs new file mode 100644 index 000000000..e48e6c866 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB1_64B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bIdSpec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_id::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_id::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_ID to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word0.rs new file mode 100644 index 000000000..3d6c5956b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord0Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word0::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word0::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD0 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word1.rs new file mode 100644 index 000000000..a1962ffca --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord1Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word1::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word1::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD1 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word10.rs new file mode 100644 index 000000000..34dcd5f45 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte43R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte42R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte41R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte40R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&self) -> DataByte43R { + DataByte43R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&self) -> DataByte42R { + DataByte42R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&self) -> DataByte41R { + DataByte41R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&self) -> DataByte40R { + DataByte40R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&mut self) -> DataByte43W { + DataByte43W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&mut self) -> DataByte42W { + DataByte42W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&mut self) -> DataByte41W { + DataByte41W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&mut self) -> DataByte40W { + DataByte40W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord10Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word10::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word10::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD10 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word11.rs new file mode 100644 index 000000000..5aedc20d2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte47R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte46R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte45R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte44R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&self) -> DataByte47R { + DataByte47R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&self) -> DataByte46R { + DataByte46R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&self) -> DataByte45R { + DataByte45R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&self) -> DataByte44R { + DataByte44R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&mut self) -> DataByte47W { + DataByte47W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&mut self) -> DataByte46W { + DataByte46W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&mut self) -> DataByte45W { + DataByte45W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&mut self) -> DataByte44W { + DataByte44W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord11Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word11::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word11::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD11 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word12.rs new file mode 100644 index 000000000..b06007f12 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte51R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte50R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte49R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte48R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&self) -> DataByte51R { + DataByte51R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&self) -> DataByte50R { + DataByte50R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&self) -> DataByte49R { + DataByte49R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&self) -> DataByte48R { + DataByte48R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&mut self) -> DataByte51W { + DataByte51W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&mut self) -> DataByte50W { + DataByte50W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&mut self) -> DataByte49W { + DataByte49W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&mut self) -> DataByte48W { + DataByte48W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord12Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word12::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word12::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD12 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word13.rs new file mode 100644 index 000000000..5d63a7340 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte55R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte54R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte53R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte52R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&self) -> DataByte55R { + DataByte55R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&self) -> DataByte54R { + DataByte54R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&self) -> DataByte53R { + DataByte53R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&self) -> DataByte52R { + DataByte52R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&mut self) -> DataByte55W { + DataByte55W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&mut self) -> DataByte54W { + DataByte54W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&mut self) -> DataByte53W { + DataByte53W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&mut self) -> DataByte52W { + DataByte52W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord13Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word13::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word13::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD13 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word14.rs new file mode 100644 index 000000000..4dc6e8291 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte59R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte58R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte57R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte56R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&self) -> DataByte59R { + DataByte59R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&self) -> DataByte58R { + DataByte58R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&self) -> DataByte57R { + DataByte57R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&self) -> DataByte56R { + DataByte56R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&mut self) -> DataByte59W { + DataByte59W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&mut self) -> DataByte58W { + DataByte58W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&mut self) -> DataByte57W { + DataByte57W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&mut self) -> DataByte56W { + DataByte56W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord14Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word14::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word14::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD14 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word15.rs new file mode 100644 index 000000000..a7a638d88 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte63R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte62R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte61R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte60R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&self) -> DataByte63R { + DataByte63R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&self) -> DataByte62R { + DataByte62R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&self) -> DataByte61R { + DataByte61R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&self) -> DataByte60R { + DataByte60R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&mut self) -> DataByte63W { + DataByte63W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&mut self) -> DataByte62W { + DataByte62W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&mut self) -> DataByte61W { + DataByte61W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&mut self) -> DataByte60W { + DataByte60W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord15Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word15::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word15::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD15 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word2.rs new file mode 100644 index 000000000..bd3a55625 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord2Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word2::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word2::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD2 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word3.rs new file mode 100644 index 000000000..052320ee6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord3Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word3::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word3::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD3 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word4.rs new file mode 100644 index 000000000..15c0ef307 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord4Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word4::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word4::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD4 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word5.rs new file mode 100644 index 000000000..c14450dee --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord5Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word5::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word5::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD5 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word6.rs new file mode 100644 index 000000000..8372f9a6a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord6Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word6::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word6::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD6 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word7.rs new file mode 100644 index 000000000..d4d516f6f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord7Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word7::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word7::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD7 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word8.rs new file mode 100644 index 000000000..60cf48c9f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word8.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD8` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte35R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte34R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte33R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte32R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&self) -> DataByte35R { + DataByte35R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&self) -> DataByte34R { + DataByte34R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&self) -> DataByte33R { + DataByte33R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&self) -> DataByte32R { + DataByte32R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&mut self) -> DataByte35W { + DataByte35W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&mut self) -> DataByte34W { + DataByte34W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&mut self) -> DataByte33W { + DataByte33W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&mut self) -> DataByte32W { + DataByte32W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord8Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word8::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word8::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD8 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word9.rs new file mode 100644 index 000000000..64bc4e92e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word9.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_64B_WORD9` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_64B_WORD9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte39R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte38R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte37R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte36R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&self) -> DataByte39R { + DataByte39R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&self) -> DataByte38R { + DataByte38R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&self) -> DataByte37R { + DataByte37R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&self) -> DataByte36R { + DataByte36R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&mut self) -> DataByte39W { + DataByte39W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&mut self) -> DataByte38W { + DataByte38W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&mut self) -> DataByte37W { + DataByte37W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&mut self) -> DataByte36W { + DataByte36W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb1_64bWord9Spec; +impl crate::RegisterSpec for Mb64bGroupMb1_64bWord9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word9::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb1_64bWord9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word9::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb1_64bWord9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_64B_WORD9 to value 0"] +impl crate::Resettable for Mb64bGroupMb1_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_cs.rs new file mode 100644 index 000000000..7a6d6a66a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB2_64B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bCsSpec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_cs::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_cs::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_CS to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_id.rs new file mode 100644 index 000000000..1b5fe0b7b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB2_64B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bIdSpec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_id::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_id::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_ID to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word0.rs new file mode 100644 index 000000000..2db921e6e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord0Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word0::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word0::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD0 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word1.rs new file mode 100644 index 000000000..57d77091d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord1Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word1::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word1::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD1 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word10.rs new file mode 100644 index 000000000..724b649e0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte43R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte42R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte41R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte40R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&self) -> DataByte43R { + DataByte43R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&self) -> DataByte42R { + DataByte42R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&self) -> DataByte41R { + DataByte41R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&self) -> DataByte40R { + DataByte40R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&mut self) -> DataByte43W { + DataByte43W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&mut self) -> DataByte42W { + DataByte42W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&mut self) -> DataByte41W { + DataByte41W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&mut self) -> DataByte40W { + DataByte40W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord10Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word10::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word10::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD10 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word11.rs new file mode 100644 index 000000000..d9976e613 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte47R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte46R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte45R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte44R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&self) -> DataByte47R { + DataByte47R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&self) -> DataByte46R { + DataByte46R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&self) -> DataByte45R { + DataByte45R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&self) -> DataByte44R { + DataByte44R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&mut self) -> DataByte47W { + DataByte47W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&mut self) -> DataByte46W { + DataByte46W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&mut self) -> DataByte45W { + DataByte45W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&mut self) -> DataByte44W { + DataByte44W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord11Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word11::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word11::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD11 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word12.rs new file mode 100644 index 000000000..2c1ecaeab --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte51R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte50R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte49R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte48R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&self) -> DataByte51R { + DataByte51R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&self) -> DataByte50R { + DataByte50R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&self) -> DataByte49R { + DataByte49R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&self) -> DataByte48R { + DataByte48R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&mut self) -> DataByte51W { + DataByte51W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&mut self) -> DataByte50W { + DataByte50W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&mut self) -> DataByte49W { + DataByte49W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&mut self) -> DataByte48W { + DataByte48W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord12Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word12::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word12::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD12 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word13.rs new file mode 100644 index 000000000..47d63fa30 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte55R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte54R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte53R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte52R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&self) -> DataByte55R { + DataByte55R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&self) -> DataByte54R { + DataByte54R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&self) -> DataByte53R { + DataByte53R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&self) -> DataByte52R { + DataByte52R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&mut self) -> DataByte55W { + DataByte55W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&mut self) -> DataByte54W { + DataByte54W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&mut self) -> DataByte53W { + DataByte53W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&mut self) -> DataByte52W { + DataByte52W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord13Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word13::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word13::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD13 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word14.rs new file mode 100644 index 000000000..328f7460f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte59R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte58R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte57R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte56R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&self) -> DataByte59R { + DataByte59R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&self) -> DataByte58R { + DataByte58R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&self) -> DataByte57R { + DataByte57R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&self) -> DataByte56R { + DataByte56R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&mut self) -> DataByte59W { + DataByte59W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&mut self) -> DataByte58W { + DataByte58W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&mut self) -> DataByte57W { + DataByte57W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&mut self) -> DataByte56W { + DataByte56W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord14Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word14::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word14::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD14 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word15.rs new file mode 100644 index 000000000..bea90d785 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte63R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte62R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte61R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte60R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&self) -> DataByte63R { + DataByte63R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&self) -> DataByte62R { + DataByte62R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&self) -> DataByte61R { + DataByte61R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&self) -> DataByte60R { + DataByte60R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&mut self) -> DataByte63W { + DataByte63W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&mut self) -> DataByte62W { + DataByte62W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&mut self) -> DataByte61W { + DataByte61W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&mut self) -> DataByte60W { + DataByte60W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord15Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word15::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word15::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD15 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word2.rs new file mode 100644 index 000000000..41e25e7dd --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord2Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word2::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word2::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD2 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word3.rs new file mode 100644 index 000000000..bc8354c3c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord3Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word3::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word3::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD3 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word4.rs new file mode 100644 index 000000000..e0f91aa67 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord4Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word4::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word4::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD4 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word5.rs new file mode 100644 index 000000000..832d989cf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord5Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word5::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word5::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD5 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word6.rs new file mode 100644 index 000000000..c93aa6cba --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord6Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word6::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word6::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD6 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word7.rs new file mode 100644 index 000000000..f57ea8d3f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord7Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word7::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word7::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD7 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word8.rs new file mode 100644 index 000000000..f68b4feea --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word8.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD8` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte35R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte34R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte33R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte32R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&self) -> DataByte35R { + DataByte35R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&self) -> DataByte34R { + DataByte34R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&self) -> DataByte33R { + DataByte33R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&self) -> DataByte32R { + DataByte32R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&mut self) -> DataByte35W { + DataByte35W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&mut self) -> DataByte34W { + DataByte34W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&mut self) -> DataByte33W { + DataByte33W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&mut self) -> DataByte32W { + DataByte32W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord8Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word8::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word8::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD8 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word9.rs new file mode 100644 index 000000000..b7f3dab95 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word9.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_64B_WORD9` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_64B_WORD9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte39R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte38R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte37R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte36R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&self) -> DataByte39R { + DataByte39R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&self) -> DataByte38R { + DataByte38R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&self) -> DataByte37R { + DataByte37R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&self) -> DataByte36R { + DataByte36R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&mut self) -> DataByte39W { + DataByte39W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&mut self) -> DataByte38W { + DataByte38W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&mut self) -> DataByte37W { + DataByte37W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&mut self) -> DataByte36W { + DataByte36W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb2_64bWord9Spec; +impl crate::RegisterSpec for Mb64bGroupMb2_64bWord9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word9::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb2_64bWord9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word9::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb2_64bWord9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_64B_WORD9 to value 0"] +impl crate::Resettable for Mb64bGroupMb2_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_cs.rs new file mode 100644 index 000000000..1cd000c8f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB3_64B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bCsSpec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_cs::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_cs::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_CS to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_id.rs new file mode 100644 index 000000000..58301678e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB3_64B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bIdSpec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_id::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_id::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_ID to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word0.rs new file mode 100644 index 000000000..5299186a3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord0Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word0::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word0::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD0 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word1.rs new file mode 100644 index 000000000..1359f2f45 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord1Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word1::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word1::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD1 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word10.rs new file mode 100644 index 000000000..254589653 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte43R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte42R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte41R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte40R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&self) -> DataByte43R { + DataByte43R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&self) -> DataByte42R { + DataByte42R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&self) -> DataByte41R { + DataByte41R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&self) -> DataByte40R { + DataByte40R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&mut self) -> DataByte43W { + DataByte43W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&mut self) -> DataByte42W { + DataByte42W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&mut self) -> DataByte41W { + DataByte41W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&mut self) -> DataByte40W { + DataByte40W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord10Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word10::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word10::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD10 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word11.rs new file mode 100644 index 000000000..3a7880f5e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte47R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte46R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte45R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte44R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&self) -> DataByte47R { + DataByte47R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&self) -> DataByte46R { + DataByte46R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&self) -> DataByte45R { + DataByte45R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&self) -> DataByte44R { + DataByte44R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&mut self) -> DataByte47W { + DataByte47W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&mut self) -> DataByte46W { + DataByte46W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&mut self) -> DataByte45W { + DataByte45W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&mut self) -> DataByte44W { + DataByte44W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord11Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word11::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word11::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD11 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word12.rs new file mode 100644 index 000000000..a7f80eb7a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte51R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte50R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte49R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte48R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&self) -> DataByte51R { + DataByte51R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&self) -> DataByte50R { + DataByte50R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&self) -> DataByte49R { + DataByte49R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&self) -> DataByte48R { + DataByte48R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&mut self) -> DataByte51W { + DataByte51W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&mut self) -> DataByte50W { + DataByte50W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&mut self) -> DataByte49W { + DataByte49W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&mut self) -> DataByte48W { + DataByte48W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord12Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word12::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word12::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD12 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word13.rs new file mode 100644 index 000000000..e64bfd83c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte55R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte54R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte53R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte52R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&self) -> DataByte55R { + DataByte55R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&self) -> DataByte54R { + DataByte54R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&self) -> DataByte53R { + DataByte53R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&self) -> DataByte52R { + DataByte52R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&mut self) -> DataByte55W { + DataByte55W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&mut self) -> DataByte54W { + DataByte54W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&mut self) -> DataByte53W { + DataByte53W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&mut self) -> DataByte52W { + DataByte52W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord13Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word13::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word13::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD13 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word14.rs new file mode 100644 index 000000000..5fb44aaa7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte59R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte58R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte57R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte56R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&self) -> DataByte59R { + DataByte59R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&self) -> DataByte58R { + DataByte58R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&self) -> DataByte57R { + DataByte57R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&self) -> DataByte56R { + DataByte56R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&mut self) -> DataByte59W { + DataByte59W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&mut self) -> DataByte58W { + DataByte58W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&mut self) -> DataByte57W { + DataByte57W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&mut self) -> DataByte56W { + DataByte56W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord14Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word14::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word14::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD14 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word15.rs new file mode 100644 index 000000000..1b763ce55 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte63R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte62R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte61R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte60R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&self) -> DataByte63R { + DataByte63R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&self) -> DataByte62R { + DataByte62R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&self) -> DataByte61R { + DataByte61R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&self) -> DataByte60R { + DataByte60R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&mut self) -> DataByte63W { + DataByte63W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&mut self) -> DataByte62W { + DataByte62W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&mut self) -> DataByte61W { + DataByte61W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&mut self) -> DataByte60W { + DataByte60W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord15Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word15::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word15::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD15 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word2.rs new file mode 100644 index 000000000..8b389288f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord2Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word2::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word2::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD2 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word3.rs new file mode 100644 index 000000000..e09997021 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord3Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word3::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word3::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD3 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word4.rs new file mode 100644 index 000000000..257f1d0be --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord4Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word4::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word4::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD4 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word5.rs new file mode 100644 index 000000000..203f3b504 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord5Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word5::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word5::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD5 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word6.rs new file mode 100644 index 000000000..49c0f9025 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord6Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word6::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word6::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD6 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word7.rs new file mode 100644 index 000000000..1b5bde3ee --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord7Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word7::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word7::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD7 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word8.rs new file mode 100644 index 000000000..b1e7b64fb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word8.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD8` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte35R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte34R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte33R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte32R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&self) -> DataByte35R { + DataByte35R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&self) -> DataByte34R { + DataByte34R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&self) -> DataByte33R { + DataByte33R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&self) -> DataByte32R { + DataByte32R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&mut self) -> DataByte35W { + DataByte35W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&mut self) -> DataByte34W { + DataByte34W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&mut self) -> DataByte33W { + DataByte33W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&mut self) -> DataByte32W { + DataByte32W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord8Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word8::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word8::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD8 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word9.rs new file mode 100644 index 000000000..b42b9f577 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word9.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_64B_WORD9` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_64B_WORD9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte39R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte38R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte37R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte36R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&self) -> DataByte39R { + DataByte39R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&self) -> DataByte38R { + DataByte38R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&self) -> DataByte37R { + DataByte37R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&self) -> DataByte36R { + DataByte36R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&mut self) -> DataByte39W { + DataByte39W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&mut self) -> DataByte38W { + DataByte38W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&mut self) -> DataByte37W { + DataByte37W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&mut self) -> DataByte36W { + DataByte36W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb3_64bWord9Spec; +impl crate::RegisterSpec for Mb64bGroupMb3_64bWord9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word9::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb3_64bWord9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word9::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb3_64bWord9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_64B_WORD9 to value 0"] +impl crate::Resettable for Mb64bGroupMb3_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_cs.rs new file mode 100644 index 000000000..9067b5e59 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB4_64B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bCsSpec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_cs::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_cs::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_CS to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_id.rs new file mode 100644 index 000000000..2394e3ff5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB4_64B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bIdSpec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_id::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_id::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_ID to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word0.rs new file mode 100644 index 000000000..421d1e203 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord0Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word0::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word0::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD0 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word1.rs new file mode 100644 index 000000000..433e30849 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord1Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word1::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word1::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD1 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word10.rs new file mode 100644 index 000000000..f816ece1c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte43R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte42R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte41R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte40R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&self) -> DataByte43R { + DataByte43R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&self) -> DataByte42R { + DataByte42R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&self) -> DataByte41R { + DataByte41R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&self) -> DataByte40R { + DataByte40R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&mut self) -> DataByte43W { + DataByte43W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&mut self) -> DataByte42W { + DataByte42W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&mut self) -> DataByte41W { + DataByte41W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&mut self) -> DataByte40W { + DataByte40W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord10Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word10::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word10::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD10 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word11.rs new file mode 100644 index 000000000..1aea88db4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte47R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte46R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte45R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte44R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&self) -> DataByte47R { + DataByte47R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&self) -> DataByte46R { + DataByte46R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&self) -> DataByte45R { + DataByte45R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&self) -> DataByte44R { + DataByte44R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&mut self) -> DataByte47W { + DataByte47W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&mut self) -> DataByte46W { + DataByte46W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&mut self) -> DataByte45W { + DataByte45W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&mut self) -> DataByte44W { + DataByte44W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord11Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word11::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word11::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD11 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word12.rs new file mode 100644 index 000000000..c74731dbc --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte51R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte50R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte49R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte48R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&self) -> DataByte51R { + DataByte51R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&self) -> DataByte50R { + DataByte50R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&self) -> DataByte49R { + DataByte49R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&self) -> DataByte48R { + DataByte48R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&mut self) -> DataByte51W { + DataByte51W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&mut self) -> DataByte50W { + DataByte50W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&mut self) -> DataByte49W { + DataByte49W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&mut self) -> DataByte48W { + DataByte48W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord12Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word12::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word12::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD12 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word13.rs new file mode 100644 index 000000000..e6dcd9554 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte55R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte54R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte53R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte52R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&self) -> DataByte55R { + DataByte55R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&self) -> DataByte54R { + DataByte54R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&self) -> DataByte53R { + DataByte53R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&self) -> DataByte52R { + DataByte52R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&mut self) -> DataByte55W { + DataByte55W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&mut self) -> DataByte54W { + DataByte54W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&mut self) -> DataByte53W { + DataByte53W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&mut self) -> DataByte52W { + DataByte52W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord13Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word13::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word13::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD13 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word14.rs new file mode 100644 index 000000000..fba5e83d6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte59R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte58R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte57R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte56R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&self) -> DataByte59R { + DataByte59R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&self) -> DataByte58R { + DataByte58R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&self) -> DataByte57R { + DataByte57R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&self) -> DataByte56R { + DataByte56R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&mut self) -> DataByte59W { + DataByte59W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&mut self) -> DataByte58W { + DataByte58W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&mut self) -> DataByte57W { + DataByte57W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&mut self) -> DataByte56W { + DataByte56W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord14Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word14::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word14::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD14 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word15.rs new file mode 100644 index 000000000..3d08b2ba8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte63R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte62R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte61R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte60R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&self) -> DataByte63R { + DataByte63R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&self) -> DataByte62R { + DataByte62R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&self) -> DataByte61R { + DataByte61R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&self) -> DataByte60R { + DataByte60R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&mut self) -> DataByte63W { + DataByte63W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&mut self) -> DataByte62W { + DataByte62W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&mut self) -> DataByte61W { + DataByte61W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&mut self) -> DataByte60W { + DataByte60W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord15Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word15::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word15::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD15 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word2.rs new file mode 100644 index 000000000..b31317180 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord2Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word2::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word2::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD2 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word3.rs new file mode 100644 index 000000000..1dc351d86 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord3Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word3::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word3::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD3 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word4.rs new file mode 100644 index 000000000..3ad5f0fe8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord4Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word4::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word4::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD4 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word5.rs new file mode 100644 index 000000000..26877c4c3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord5Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word5::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word5::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD5 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word6.rs new file mode 100644 index 000000000..a6783d6bf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord6Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word6::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word6::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD6 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word7.rs new file mode 100644 index 000000000..4a7f71501 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord7Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word7::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word7::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD7 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word8.rs new file mode 100644 index 000000000..2893e4772 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word8.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD8` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte35R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte34R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte33R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte32R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&self) -> DataByte35R { + DataByte35R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&self) -> DataByte34R { + DataByte34R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&self) -> DataByte33R { + DataByte33R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&self) -> DataByte32R { + DataByte32R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&mut self) -> DataByte35W { + DataByte35W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&mut self) -> DataByte34W { + DataByte34W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&mut self) -> DataByte33W { + DataByte33W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&mut self) -> DataByte32W { + DataByte32W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord8Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word8::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word8::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD8 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word9.rs new file mode 100644 index 000000000..1acab9847 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word9.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_64B_WORD9` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_64B_WORD9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte39R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte38R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte37R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte36R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&self) -> DataByte39R { + DataByte39R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&self) -> DataByte38R { + DataByte38R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&self) -> DataByte37R { + DataByte37R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&self) -> DataByte36R { + DataByte36R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&mut self) -> DataByte39W { + DataByte39W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&mut self) -> DataByte38W { + DataByte38W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&mut self) -> DataByte37W { + DataByte37W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&mut self) -> DataByte36W { + DataByte36W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb4_64bWord9Spec; +impl crate::RegisterSpec for Mb64bGroupMb4_64bWord9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word9::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb4_64bWord9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word9::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb4_64bWord9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_64B_WORD9 to value 0"] +impl crate::Resettable for Mb64bGroupMb4_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_cs.rs new file mode 100644 index 000000000..ddad14de2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB5_64B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bCsSpec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_cs::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_cs::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_CS to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_id.rs new file mode 100644 index 000000000..587fba280 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB5_64B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bIdSpec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_id::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_id::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_ID to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word0.rs new file mode 100644 index 000000000..a33487a2f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord0Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word0::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word0::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD0 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word1.rs new file mode 100644 index 000000000..af557ac31 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord1Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word1::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word1::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD1 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word10.rs new file mode 100644 index 000000000..2dbec434c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte43R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte42R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte41R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte40R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&self) -> DataByte43R { + DataByte43R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&self) -> DataByte42R { + DataByte42R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&self) -> DataByte41R { + DataByte41R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&self) -> DataByte40R { + DataByte40R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&mut self) -> DataByte43W { + DataByte43W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&mut self) -> DataByte42W { + DataByte42W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&mut self) -> DataByte41W { + DataByte41W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&mut self) -> DataByte40W { + DataByte40W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord10Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word10::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word10::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD10 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word11.rs new file mode 100644 index 000000000..00217fd09 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte47R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte46R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte45R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte44R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&self) -> DataByte47R { + DataByte47R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&self) -> DataByte46R { + DataByte46R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&self) -> DataByte45R { + DataByte45R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&self) -> DataByte44R { + DataByte44R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&mut self) -> DataByte47W { + DataByte47W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&mut self) -> DataByte46W { + DataByte46W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&mut self) -> DataByte45W { + DataByte45W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&mut self) -> DataByte44W { + DataByte44W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord11Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word11::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word11::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD11 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word12.rs new file mode 100644 index 000000000..e04dac374 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte51R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte50R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte49R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte48R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&self) -> DataByte51R { + DataByte51R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&self) -> DataByte50R { + DataByte50R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&self) -> DataByte49R { + DataByte49R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&self) -> DataByte48R { + DataByte48R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&mut self) -> DataByte51W { + DataByte51W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&mut self) -> DataByte50W { + DataByte50W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&mut self) -> DataByte49W { + DataByte49W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&mut self) -> DataByte48W { + DataByte48W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord12Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word12::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word12::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD12 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word13.rs new file mode 100644 index 000000000..55b20069a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte55R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte54R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte53R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte52R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&self) -> DataByte55R { + DataByte55R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&self) -> DataByte54R { + DataByte54R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&self) -> DataByte53R { + DataByte53R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&self) -> DataByte52R { + DataByte52R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&mut self) -> DataByte55W { + DataByte55W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&mut self) -> DataByte54W { + DataByte54W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&mut self) -> DataByte53W { + DataByte53W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&mut self) -> DataByte52W { + DataByte52W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord13Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word13::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word13::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD13 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word14.rs new file mode 100644 index 000000000..2d7b49d63 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte59R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte58R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte57R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte56R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&self) -> DataByte59R { + DataByte59R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&self) -> DataByte58R { + DataByte58R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&self) -> DataByte57R { + DataByte57R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&self) -> DataByte56R { + DataByte56R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&mut self) -> DataByte59W { + DataByte59W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&mut self) -> DataByte58W { + DataByte58W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&mut self) -> DataByte57W { + DataByte57W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&mut self) -> DataByte56W { + DataByte56W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord14Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word14::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word14::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD14 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word15.rs new file mode 100644 index 000000000..3f3c2840f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte63R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte62R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte61R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte60R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&self) -> DataByte63R { + DataByte63R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&self) -> DataByte62R { + DataByte62R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&self) -> DataByte61R { + DataByte61R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&self) -> DataByte60R { + DataByte60R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&mut self) -> DataByte63W { + DataByte63W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&mut self) -> DataByte62W { + DataByte62W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&mut self) -> DataByte61W { + DataByte61W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&mut self) -> DataByte60W { + DataByte60W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord15Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word15::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word15::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD15 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word2.rs new file mode 100644 index 000000000..20868cd42 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord2Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word2::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word2::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD2 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word3.rs new file mode 100644 index 000000000..251487533 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord3Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word3::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word3::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD3 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word4.rs new file mode 100644 index 000000000..7443e932a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord4Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word4::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word4::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD4 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word5.rs new file mode 100644 index 000000000..d3e3243f9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord5Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word5::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word5::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD5 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word6.rs new file mode 100644 index 000000000..c53968433 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord6Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word6::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word6::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD6 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word7.rs new file mode 100644 index 000000000..6ef3bc4a9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord7Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word7::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word7::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD7 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word8.rs new file mode 100644 index 000000000..ccae23acb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word8.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD8` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte35R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte34R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte33R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte32R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&self) -> DataByte35R { + DataByte35R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&self) -> DataByte34R { + DataByte34R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&self) -> DataByte33R { + DataByte33R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&self) -> DataByte32R { + DataByte32R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&mut self) -> DataByte35W { + DataByte35W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&mut self) -> DataByte34W { + DataByte34W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&mut self) -> DataByte33W { + DataByte33W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&mut self) -> DataByte32W { + DataByte32W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord8Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word8::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word8::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD8 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word9.rs new file mode 100644 index 000000000..e0c740a42 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word9.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_64B_WORD9` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_64B_WORD9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte39R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte38R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte37R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte36R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&self) -> DataByte39R { + DataByte39R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&self) -> DataByte38R { + DataByte38R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&self) -> DataByte37R { + DataByte37R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&self) -> DataByte36R { + DataByte36R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&mut self) -> DataByte39W { + DataByte39W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&mut self) -> DataByte38W { + DataByte38W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&mut self) -> DataByte37W { + DataByte37W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&mut self) -> DataByte36W { + DataByte36W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb5_64bWord9Spec; +impl crate::RegisterSpec for Mb64bGroupMb5_64bWord9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word9::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb5_64bWord9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word9::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb5_64bWord9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_64B_WORD9 to value 0"] +impl crate::Resettable for Mb64bGroupMb5_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_cs.rs new file mode 100644 index 000000000..ebe364c60 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB6_64B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bCsSpec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_cs::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_cs::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_CS to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_id.rs new file mode 100644 index 000000000..7ab4b38cf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB6_64B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bIdSpec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_id::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_id::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_ID to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word0.rs new file mode 100644 index 000000000..bafda4748 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord0Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word0::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word0::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD0 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word1.rs new file mode 100644 index 000000000..9d8bbc6a7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord1Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word1::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word1::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD1 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word10.rs new file mode 100644 index 000000000..926ae993f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte43R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte42R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte41R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte40R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&self) -> DataByte43R { + DataByte43R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&self) -> DataByte42R { + DataByte42R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&self) -> DataByte41R { + DataByte41R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&self) -> DataByte40R { + DataByte40R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_43(&mut self) -> DataByte43W { + DataByte43W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_42(&mut self) -> DataByte42W { + DataByte42W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_41(&mut self) -> DataByte41W { + DataByte41W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_40(&mut self) -> DataByte40W { + DataByte40W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord10Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word10::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word10::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD10 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word11.rs new file mode 100644 index 000000000..b51a9b41b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte47R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte46R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte45R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte44R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&self) -> DataByte47R { + DataByte47R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&self) -> DataByte46R { + DataByte46R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&self) -> DataByte45R { + DataByte45R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&self) -> DataByte44R { + DataByte44R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_47(&mut self) -> DataByte47W { + DataByte47W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_46(&mut self) -> DataByte46W { + DataByte46W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_45(&mut self) -> DataByte45W { + DataByte45W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_44(&mut self) -> DataByte44W { + DataByte44W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord11Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word11::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word11::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD11 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word12.rs new file mode 100644 index 000000000..24630ed6a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte51R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte50R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte49R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte48R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&self) -> DataByte51R { + DataByte51R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&self) -> DataByte50R { + DataByte50R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&self) -> DataByte49R { + DataByte49R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&self) -> DataByte48R { + DataByte48R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_51(&mut self) -> DataByte51W { + DataByte51W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_50(&mut self) -> DataByte50W { + DataByte50W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_49(&mut self) -> DataByte49W { + DataByte49W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_48(&mut self) -> DataByte48W { + DataByte48W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord12Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word12::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word12::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD12 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word13.rs new file mode 100644 index 000000000..6468e9eb8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte55R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte54R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte53R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte52R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&self) -> DataByte55R { + DataByte55R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&self) -> DataByte54R { + DataByte54R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&self) -> DataByte53R { + DataByte53R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&self) -> DataByte52R { + DataByte52R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_55(&mut self) -> DataByte55W { + DataByte55W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_54(&mut self) -> DataByte54W { + DataByte54W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_53(&mut self) -> DataByte53W { + DataByte53W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_52(&mut self) -> DataByte52W { + DataByte52W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord13Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word13::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word13::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD13 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word14.rs new file mode 100644 index 000000000..99c593175 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte59R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte58R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte57R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte56R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&self) -> DataByte59R { + DataByte59R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&self) -> DataByte58R { + DataByte58R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&self) -> DataByte57R { + DataByte57R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&self) -> DataByte56R { + DataByte56R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_59(&mut self) -> DataByte59W { + DataByte59W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_58(&mut self) -> DataByte58W { + DataByte58W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_57(&mut self) -> DataByte57W { + DataByte57W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_56(&mut self) -> DataByte56W { + DataByte56W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord14Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word14::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word14::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD14 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word15.rs new file mode 100644 index 000000000..6afd5c30f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte63R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte62R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte61R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte60R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&self) -> DataByte63R { + DataByte63R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&self) -> DataByte62R { + DataByte62R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&self) -> DataByte61R { + DataByte61R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&self) -> DataByte60R { + DataByte60R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_63(&mut self) -> DataByte63W { + DataByte63W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_62(&mut self) -> DataByte62W { + DataByte62W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_61(&mut self) -> DataByte61W { + DataByte61W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_60(&mut self) -> DataByte60W { + DataByte60W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord15Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word15::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word15::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD15 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word2.rs new file mode 100644 index 000000000..139fe50f4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD2` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte11R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte10R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte9R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte8R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&self) -> DataByte11R { + DataByte11R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&self) -> DataByte10R { + DataByte10R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&self) -> DataByte9R { + DataByte9R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&self) -> DataByte8R { + DataByte8R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_11(&mut self) -> DataByte11W { + DataByte11W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_10(&mut self) -> DataByte10W { + DataByte10W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_9(&mut self) -> DataByte9W { + DataByte9W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_8(&mut self) -> DataByte8W { + DataByte8W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord2Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word2::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word2::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD2 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word3.rs new file mode 100644 index 000000000..e19ed78d7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD3` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte15R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte14R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte13R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte12R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&self) -> DataByte15R { + DataByte15R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&self) -> DataByte14R { + DataByte14R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&self) -> DataByte13R { + DataByte13R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&self) -> DataByte12R { + DataByte12R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_15(&mut self) -> DataByte15W { + DataByte15W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_14(&mut self) -> DataByte14W { + DataByte14W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_13(&mut self) -> DataByte13W { + DataByte13W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_12(&mut self) -> DataByte12W { + DataByte12W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord3Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word3::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word3::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD3 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word4.rs new file mode 100644 index 000000000..e2675e2be --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD4` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte19R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte18R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte17R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte16R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&self) -> DataByte19R { + DataByte19R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&self) -> DataByte18R { + DataByte18R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&self) -> DataByte17R { + DataByte17R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&self) -> DataByte16R { + DataByte16R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_19(&mut self) -> DataByte19W { + DataByte19W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_18(&mut self) -> DataByte18W { + DataByte18W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_17(&mut self) -> DataByte17W { + DataByte17W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_16(&mut self) -> DataByte16W { + DataByte16W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord4Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word4::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word4::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD4 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word5.rs new file mode 100644 index 000000000..d82598368 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD5` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte23R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte22R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte21R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte20R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&self) -> DataByte23R { + DataByte23R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&self) -> DataByte22R { + DataByte22R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&self) -> DataByte21R { + DataByte21R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&self) -> DataByte20R { + DataByte20R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_23(&mut self) -> DataByte23W { + DataByte23W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_22(&mut self) -> DataByte22W { + DataByte22W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_21(&mut self) -> DataByte21W { + DataByte21W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_20(&mut self) -> DataByte20W { + DataByte20W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord5Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word5::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word5::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD5 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word6.rs new file mode 100644 index 000000000..428012fe8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word6.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD6` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte27R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte26R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte25R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte24R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&self) -> DataByte27R { + DataByte27R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&self) -> DataByte26R { + DataByte26R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&self) -> DataByte25R { + DataByte25R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&self) -> DataByte24R { + DataByte24R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_27(&mut self) -> DataByte27W { + DataByte27W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_26(&mut self) -> DataByte26W { + DataByte26W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_25(&mut self) -> DataByte25W { + DataByte25W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_24(&mut self) -> DataByte24W { + DataByte24W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord6Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word6::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word6::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD6 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word7.rs new file mode 100644 index 000000000..062ca1f11 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word7.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD7` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte31R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte30R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte29R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte28R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&self) -> DataByte31R { + DataByte31R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&self) -> DataByte30R { + DataByte30R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&self) -> DataByte29R { + DataByte29R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&self) -> DataByte28R { + DataByte28R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_31(&mut self) -> DataByte31W { + DataByte31W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_30(&mut self) -> DataByte30W { + DataByte30W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_29(&mut self) -> DataByte29W { + DataByte29W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_28(&mut self) -> DataByte28W { + DataByte28W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord7Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word7::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word7::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD7 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word8.rs new file mode 100644 index 000000000..82b461123 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word8.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD8` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte35R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte34R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte33R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte32R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&self) -> DataByte35R { + DataByte35R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&self) -> DataByte34R { + DataByte34R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&self) -> DataByte33R { + DataByte33R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&self) -> DataByte32R { + DataByte32R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_35(&mut self) -> DataByte35W { + DataByte35W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_34(&mut self) -> DataByte34W { + DataByte34W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_33(&mut self) -> DataByte33W { + DataByte33W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_32(&mut self) -> DataByte32W { + DataByte32W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord8Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word8::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word8::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD8 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word9.rs new file mode 100644 index 000000000..98b72b62a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word9.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_64B_WORD9` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_64B_WORD9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte39R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte38R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte37R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte36R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&self) -> DataByte39R { + DataByte39R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&self) -> DataByte38R { + DataByte38R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&self) -> DataByte37R { + DataByte37R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&self) -> DataByte36R { + DataByte36R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_39(&mut self) -> DataByte39W { + DataByte39W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_38(&mut self) -> DataByte38W { + DataByte38W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_37(&mut self) -> DataByte37W { + DataByte37W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_36(&mut self) -> DataByte36W { + DataByte36W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb64bGroupMb6_64bWord9Spec; +impl crate::RegisterSpec for Mb64bGroupMb6_64bWord9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word9::R`](R) reader structure"] +impl crate::Readable for Mb64bGroupMb6_64bWord9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word9::W`](W) writer structure"] +impl crate::Writable for Mb64bGroupMb6_64bWord9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_64B_WORD9 to value 0"] +impl crate::Resettable for Mb64bGroupMb6_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_cs.rs new file mode 100644 index 000000000..64d91968d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB0_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb0_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb0_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb0_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb0_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb0_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_id.rs new file mode 100644 index 000000000..831cd7ebe --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB0_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb0_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb0_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb0_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb0_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb0_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word0.rs new file mode 100644 index 000000000..91a7e70b5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb0_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb0_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb0_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb0_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb0_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word1.rs new file mode 100644 index 000000000..64595986c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB0_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB0_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb0_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb0_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb0_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb0_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB0_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb0_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_cs.rs new file mode 100644 index 000000000..fabd51c24 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB10_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb10_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb10_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb10_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb10_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb10_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_id.rs new file mode 100644 index 000000000..d540ed50e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB10_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb10_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb10_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb10_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb10_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb10_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word0.rs new file mode 100644 index 000000000..07faacbd1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb10_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb10_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb10_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb10_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb10_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word1.rs new file mode 100644 index 000000000..df2a992fd --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB10_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB10_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb10_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb10_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb10_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb10_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB10_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb10_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_cs.rs new file mode 100644 index 000000000..1b8b3b2c2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB11_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb11_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb11_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb11_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb11_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb11_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_id.rs new file mode 100644 index 000000000..2c497a5aa --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB11_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb11_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb11_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb11_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb11_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb11_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word0.rs new file mode 100644 index 000000000..9992eed11 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb11_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb11_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb11_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb11_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb11_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word1.rs new file mode 100644 index 000000000..d141dbfe7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB11_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB11_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb11_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb11_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb11_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb11_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB11_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb11_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_cs.rs new file mode 100644 index 000000000..b262164a7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB12_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb12_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb12_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb12_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb12_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb12_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_id.rs new file mode 100644 index 000000000..4997280e6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB12_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb12_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb12_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb12_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb12_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb12_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word0.rs new file mode 100644 index 000000000..34e0535d8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB12_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb12_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb12_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb12_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb12_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb12_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word1.rs new file mode 100644 index 000000000..1a0788eb9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB12_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB12_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb12_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb12_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb12_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb12_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB12_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb12_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_cs.rs new file mode 100644 index 000000000..6d1ddc6f4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB13_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb13_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb13_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb13_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb13_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb13_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_id.rs new file mode 100644 index 000000000..63440ee65 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB13_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb13_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb13_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb13_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb13_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb13_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word0.rs new file mode 100644 index 000000000..80aca89a8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB13_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb13_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb13_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb13_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb13_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb13_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word1.rs new file mode 100644 index 000000000..ba4a393b9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB13_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB13_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb13_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb13_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb13_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb13_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB13_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb13_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_cs.rs new file mode 100644 index 000000000..18597af49 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB14_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb14_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb14_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb14_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb14_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb14_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_id.rs new file mode 100644 index 000000000..1870f7106 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB14_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb14_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb14_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb14_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb14_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb14_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word0.rs new file mode 100644 index 000000000..1c9bb7c55 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB14_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb14_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb14_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb14_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb14_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb14_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word1.rs new file mode 100644 index 000000000..81b888cb2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB14_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB14_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb14_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb14_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb14_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb14_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB14_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb14_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_cs.rs new file mode 100644 index 000000000..2a2ce8530 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB15_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb15_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb15_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb15_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb15_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb15_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_id.rs new file mode 100644 index 000000000..b4f8fec8a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB15_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb15_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb15_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb15_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb15_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb15_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word0.rs new file mode 100644 index 000000000..c327b6d19 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB15_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb15_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb15_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb15_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb15_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb15_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word1.rs new file mode 100644 index 000000000..efc4f8606 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB15_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB15_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb15_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb15_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb15_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb15_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB15_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb15_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_cs.rs new file mode 100644 index 000000000..8a3fdfb5f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB16_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb16_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb16_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb16_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb16_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb16_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_id.rs new file mode 100644 index 000000000..27e447ae0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB16_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb16_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb16_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb16_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb16_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb16_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word0.rs new file mode 100644 index 000000000..7211d905f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB16_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb16_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb16_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb16_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb16_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb16_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word1.rs new file mode 100644 index 000000000..8e8e99534 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB16_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB16_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb16_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb16_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb16_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb16_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB16_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb16_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_cs.rs new file mode 100644 index 000000000..513461780 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB17_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb17_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb17_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb17_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb17_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb17_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_id.rs new file mode 100644 index 000000000..48fdf7076 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB17_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb17_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb17_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb17_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb17_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb17_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word0.rs new file mode 100644 index 000000000..d0284594f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB17_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb17_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb17_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb17_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb17_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb17_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word1.rs new file mode 100644 index 000000000..523ab671e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB17_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB17_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb17_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb17_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb17_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb17_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB17_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb17_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_cs.rs new file mode 100644 index 000000000..291706aa8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB18_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb18_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb18_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb18_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb18_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb18_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_id.rs new file mode 100644 index 000000000..9c17ec139 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB18_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb18_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb18_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb18_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb18_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb18_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word0.rs new file mode 100644 index 000000000..20e99a7b5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB18_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb18_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb18_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb18_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb18_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb18_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word1.rs new file mode 100644 index 000000000..0aa8cde57 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB18_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB18_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb18_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb18_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb18_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb18_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB18_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb18_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_cs.rs new file mode 100644 index 000000000..f8f0cb63d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB19_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb19_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb19_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb19_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb19_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb19_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_id.rs new file mode 100644 index 000000000..6175f3bdf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB19_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb19_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb19_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb19_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb19_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb19_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word0.rs new file mode 100644 index 000000000..9cbe96ecd --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB19_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb19_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb19_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb19_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb19_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb19_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word1.rs new file mode 100644 index 000000000..e86c69de0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB19_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB19_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb19_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb19_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb19_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb19_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB19_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb19_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_cs.rs new file mode 100644 index 000000000..195c7173c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB1_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb1_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb1_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb1_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb1_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb1_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_id.rs new file mode 100644 index 000000000..e8ad195cf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB1_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb1_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb1_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb1_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb1_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb1_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word0.rs new file mode 100644 index 000000000..a78bf2957 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb1_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb1_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb1_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb1_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb1_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word1.rs new file mode 100644 index 000000000..56caed8c9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB1_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB1_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb1_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb1_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb1_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb1_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB1_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb1_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_cs.rs new file mode 100644 index 000000000..63339f97c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB20_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb20_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb20_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb20_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb20_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb20_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_id.rs new file mode 100644 index 000000000..451fb759c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB20_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb20_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb20_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb20_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb20_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb20_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word0.rs new file mode 100644 index 000000000..b024fae73 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB20_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb20_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb20_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb20_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb20_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb20_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word1.rs new file mode 100644 index 000000000..c6a355d52 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB20_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB20_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb20_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb20_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb20_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb20_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB20_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb20_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_cs.rs new file mode 100644 index 000000000..15edf45d2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB21_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB21_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb21_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb21_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb21_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb21_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB21_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb21_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_id.rs new file mode 100644 index 000000000..6d6da8057 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB21_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB21_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb21_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb21_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb21_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb21_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB21_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb21_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word0.rs new file mode 100644 index 000000000..670dea523 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB21_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB21_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb21_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb21_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb21_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb21_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB21_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb21_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word1.rs new file mode 100644 index 000000000..7acf2755e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB21_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB21_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb21_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb21_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb21_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb21_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB21_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb21_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_cs.rs new file mode 100644 index 000000000..79f5cb974 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB22_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB22_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb22_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb22_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb22_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb22_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB22_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb22_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_id.rs new file mode 100644 index 000000000..f17b27ede --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB22_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB22_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb22_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb22_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb22_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb22_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB22_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb22_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word0.rs new file mode 100644 index 000000000..5ee011550 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB22_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB22_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb22_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb22_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb22_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb22_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB22_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb22_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word1.rs new file mode 100644 index 000000000..9b20b1ce5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB22_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB22_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb22_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb22_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb22_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb22_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB22_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb22_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_cs.rs new file mode 100644 index 000000000..f019a7d03 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB23_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB23_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb23_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb23_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb23_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb23_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB23_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb23_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_id.rs new file mode 100644 index 000000000..494eb7ea8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB23_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB23_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb23_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb23_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb23_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb23_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB23_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb23_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word0.rs new file mode 100644 index 000000000..324272bd0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB23_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB23_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb23_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb23_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb23_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb23_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB23_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb23_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word1.rs new file mode 100644 index 000000000..99f81153a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB23_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB23_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb23_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb23_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb23_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb23_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB23_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb23_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_cs.rs new file mode 100644 index 000000000..65445b5d8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB24_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB24_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb24_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb24_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb24_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb24_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB24_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb24_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_id.rs new file mode 100644 index 000000000..163558c45 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB24_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB24_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb24_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb24_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb24_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb24_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB24_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb24_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word0.rs new file mode 100644 index 000000000..904296003 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB24_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB24_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb24_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb24_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb24_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb24_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB24_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb24_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word1.rs new file mode 100644 index 000000000..c22fed693 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB24_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB24_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb24_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb24_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb24_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb24_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB24_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb24_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_cs.rs new file mode 100644 index 000000000..24ef381f5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB25_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB25_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb25_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb25_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb25_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb25_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB25_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb25_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_id.rs new file mode 100644 index 000000000..959365154 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB25_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB25_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb25_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb25_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb25_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb25_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB25_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb25_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word0.rs new file mode 100644 index 000000000..1b8041311 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB25_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB25_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb25_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb25_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb25_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb25_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB25_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb25_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word1.rs new file mode 100644 index 000000000..5bddfc97a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB25_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB25_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb25_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb25_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb25_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb25_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB25_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb25_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_cs.rs new file mode 100644 index 000000000..7c14cc278 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB26_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB26_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb26_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb26_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb26_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb26_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB26_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb26_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_id.rs new file mode 100644 index 000000000..94fbd33d7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB26_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB26_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb26_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb26_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb26_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb26_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB26_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb26_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word0.rs new file mode 100644 index 000000000..7f9688b70 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB26_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB26_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb26_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb26_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb26_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb26_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB26_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb26_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word1.rs new file mode 100644 index 000000000..0253e3d35 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB26_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB26_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb26_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb26_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb26_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb26_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB26_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb26_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_cs.rs new file mode 100644 index 000000000..a461fd6f6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB27_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB27_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb27_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb27_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb27_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb27_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB27_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb27_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs new file mode 100644 index 000000000..ba3fe6be8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB27_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB27_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb27_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb27_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb27_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb27_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB27_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb27_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs new file mode 100644 index 000000000..0f94dacc8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB27_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB27_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb27_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb27_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb27_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb27_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB27_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb27_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs new file mode 100644 index 000000000..2061574a5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB27_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB27_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb27_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb27_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb27_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb27_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB27_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb27_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs new file mode 100644 index 000000000..01c3df95c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB28_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB28_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb28_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb28_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb28_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb28_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB28_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb28_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs new file mode 100644 index 000000000..9151a84e5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB28_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB28_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb28_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb28_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb28_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb28_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB28_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb28_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs new file mode 100644 index 000000000..8add84844 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB28_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB28_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb28_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb28_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb28_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb28_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB28_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb28_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs new file mode 100644 index 000000000..cb4312410 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB28_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB28_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb28_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb28_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb28_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb28_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB28_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb28_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs new file mode 100644 index 000000000..3a6aef983 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB29_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB29_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb29_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb29_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb29_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb29_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB29_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb29_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs new file mode 100644 index 000000000..0347e3aa0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB29_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB29_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb29_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb29_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb29_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb29_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB29_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb29_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs new file mode 100644 index 000000000..bfb171199 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB29_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB29_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb29_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb29_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb29_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb29_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB29_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb29_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs new file mode 100644 index 000000000..7ec594406 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB29_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB29_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb29_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb29_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb29_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb29_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB29_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb29_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs new file mode 100644 index 000000000..3837df2be --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB2_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb2_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb2_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb2_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb2_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb2_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs new file mode 100644 index 000000000..a2bba19e6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB2_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb2_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb2_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb2_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb2_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb2_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs new file mode 100644 index 000000000..2305ed6a6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb2_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb2_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb2_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb2_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb2_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs new file mode 100644 index 000000000..fe0c62124 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB2_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB2_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb2_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb2_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb2_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb2_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB2_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb2_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs new file mode 100644 index 000000000..25c367b8f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB30_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB30_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb30_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb30_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb30_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb30_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB30_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb30_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs new file mode 100644 index 000000000..5f9647ab3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB30_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB30_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb30_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb30_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb30_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb30_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB30_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb30_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word0.rs new file mode 100644 index 000000000..92b97c8e1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB30_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB30_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb30_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb30_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb30_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb30_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB30_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb30_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word1.rs new file mode 100644 index 000000000..3acacbf5f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB30_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB30_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb30_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb30_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb30_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb30_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB30_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb30_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_cs.rs new file mode 100644 index 000000000..64768c412 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB31_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB31_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb31_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb31_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb31_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb31_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB31_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb31_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_id.rs new file mode 100644 index 000000000..8f785ced7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB31_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB31_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb31_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb31_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb31_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb31_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB31_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb31_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word0.rs new file mode 100644 index 000000000..56ba1f800 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB31_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB31_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb31_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb31_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb31_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb31_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB31_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb31_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word1.rs new file mode 100644 index 000000000..936d6b103 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB31_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB31_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb31_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb31_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb31_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb31_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB31_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb31_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_cs.rs new file mode 100644 index 000000000..77794ccb1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB3_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb3_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb3_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb3_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb3_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb3_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_id.rs new file mode 100644 index 000000000..8b3a0b328 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB3_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb3_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb3_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb3_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb3_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb3_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word0.rs new file mode 100644 index 000000000..daf69a22b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb3_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb3_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb3_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb3_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb3_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word1.rs new file mode 100644 index 000000000..e4de46f92 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB3_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB3_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb3_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb3_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb3_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb3_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB3_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb3_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_cs.rs new file mode 100644 index 000000000..4085893c4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB4_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb4_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb4_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb4_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb4_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb4_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_id.rs new file mode 100644 index 000000000..09ddcc317 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB4_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb4_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb4_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb4_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb4_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb4_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word0.rs new file mode 100644 index 000000000..08b5c0470 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb4_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb4_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb4_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb4_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb4_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word1.rs new file mode 100644 index 000000000..adbf2004a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB4_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB4_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb4_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb4_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb4_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb4_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB4_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb4_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_cs.rs new file mode 100644 index 000000000..3b85482ff --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB5_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb5_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb5_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb5_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb5_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb5_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_id.rs new file mode 100644 index 000000000..11e48ecc0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB5_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb5_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb5_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb5_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb5_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb5_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word0.rs new file mode 100644 index 000000000..1c4f4b76f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb5_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb5_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb5_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb5_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb5_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word1.rs new file mode 100644 index 000000000..498ad7512 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB5_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB5_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb5_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb5_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb5_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb5_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB5_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb5_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_cs.rs new file mode 100644 index 000000000..a7d2b6e6e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB6_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb6_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb6_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb6_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb6_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb6_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_id.rs new file mode 100644 index 000000000..8819e5218 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB6_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb6_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb6_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb6_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb6_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb6_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word0.rs new file mode 100644 index 000000000..7547cc88a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb6_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb6_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb6_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb6_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb6_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word1.rs new file mode 100644 index 000000000..0880c7628 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB6_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB6_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb6_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb6_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb6_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb6_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB6_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb6_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_cs.rs new file mode 100644 index 000000000..1b4b05793 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB7_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb7_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb7_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb7_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb7_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb7_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_id.rs new file mode 100644 index 000000000..1fbcf6e51 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB7_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb7_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb7_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb7_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb7_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb7_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word0.rs new file mode 100644 index 000000000..22bb2cd92 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb7_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb7_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb7_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb7_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb7_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word1.rs new file mode 100644 index 000000000..f2ea8eaca --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB7_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB7_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb7_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb7_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb7_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb7_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB7_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb7_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_cs.rs new file mode 100644 index 000000000..d8cd1ee67 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB8_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb8_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb8_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb8_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb8_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb8_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_id.rs new file mode 100644 index 000000000..8a95c1fae --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB8_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb8_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb8_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb8_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb8_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb8_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word0.rs new file mode 100644 index 000000000..30b369d0e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb8_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb8_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb8_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb8_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb8_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word1.rs new file mode 100644 index 000000000..d76c4a9a6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB8_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB8_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb8_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb8_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb8_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb8_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB8_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb8_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_cs.rs new file mode 100644 index 000000000..347e36ef8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_cs.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MB9_8B_CS` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_8B_CS` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb9_8bCsSpec; +impl crate::RegisterSpec for Mb8bGroupMb9_8bCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_cs::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb9_8bCsSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_cs::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb9_8bCsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_8B_CS to value 0"] +impl crate::Resettable for Mb8bGroupMb9_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_id.rs new file mode 100644 index 000000000..16a78a2cc --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MB9_8B_ID` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_8B_ID` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb9_8bIdSpec; +impl crate::RegisterSpec for Mb8bGroupMb9_8bIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_id::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb9_8bIdSpec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_id::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb9_8bIdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_8B_ID to value 0"] +impl crate::Resettable for Mb8bGroupMb9_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word0.rs new file mode 100644 index 000000000..fc0d4b252 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_8B_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_8B_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb9_8bWord0Spec; +impl crate::RegisterSpec for Mb8bGroupMb9_8bWord0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_word0::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb9_8bWord0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_word0::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb9_8bWord0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_8B_WORD0 to value 0"] +impl crate::Resettable for Mb8bGroupMb9_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word1.rs new file mode 100644 index 000000000..d4413a60a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MB9_8B_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `MB9_8B_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mb8bGroupMb9_8bWord1Spec; +impl crate::RegisterSpec for Mb8bGroupMb9_8bWord1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_word1::R`](R) reader structure"] +impl crate::Readable for Mb8bGroupMb9_8bWord1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_word1::W`](W) writer structure"] +impl crate::Writable for Mb8bGroupMb9_8bWord1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MB9_8B_WORD1 to value 0"] +impl crate::Resettable for Mb8bGroupMb9_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs0.rs b/mcxa276-pac/src/can0/mb_group_cs0.rs new file mode 100644 index 000000000..769483906 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS0` reader"] +pub type R = crate::R; +#[doc = "Register `CS0` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs0Spec; +impl crate::RegisterSpec for MbGroupCs0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs0::R`](R) reader structure"] +impl crate::Readable for MbGroupCs0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs0::W`](W) writer structure"] +impl crate::Writable for MbGroupCs0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS0 to value 0"] +impl crate::Resettable for MbGroupCs0Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs1.rs b/mcxa276-pac/src/can0/mb_group_cs1.rs new file mode 100644 index 000000000..9330bfc8c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS1` reader"] +pub type R = crate::R; +#[doc = "Register `CS1` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs1Spec; +impl crate::RegisterSpec for MbGroupCs1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs1::R`](R) reader structure"] +impl crate::Readable for MbGroupCs1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs1::W`](W) writer structure"] +impl crate::Writable for MbGroupCs1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS1 to value 0"] +impl crate::Resettable for MbGroupCs1Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs10.rs b/mcxa276-pac/src/can0/mb_group_cs10.rs new file mode 100644 index 000000000..e1379bf42 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs10.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS10` reader"] +pub type R = crate::R; +#[doc = "Register `CS10` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs10Spec; +impl crate::RegisterSpec for MbGroupCs10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs10::R`](R) reader structure"] +impl crate::Readable for MbGroupCs10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs10::W`](W) writer structure"] +impl crate::Writable for MbGroupCs10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS10 to value 0"] +impl crate::Resettable for MbGroupCs10Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs11.rs b/mcxa276-pac/src/can0/mb_group_cs11.rs new file mode 100644 index 000000000..c3efc1f76 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs11.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS11` reader"] +pub type R = crate::R; +#[doc = "Register `CS11` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs11Spec; +impl crate::RegisterSpec for MbGroupCs11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs11::R`](R) reader structure"] +impl crate::Readable for MbGroupCs11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs11::W`](W) writer structure"] +impl crate::Writable for MbGroupCs11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS11 to value 0"] +impl crate::Resettable for MbGroupCs11Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs12.rs b/mcxa276-pac/src/can0/mb_group_cs12.rs new file mode 100644 index 000000000..c306e5143 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs12.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS12` reader"] +pub type R = crate::R; +#[doc = "Register `CS12` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs12Spec; +impl crate::RegisterSpec for MbGroupCs12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs12::R`](R) reader structure"] +impl crate::Readable for MbGroupCs12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs12::W`](W) writer structure"] +impl crate::Writable for MbGroupCs12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS12 to value 0"] +impl crate::Resettable for MbGroupCs12Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs13.rs b/mcxa276-pac/src/can0/mb_group_cs13.rs new file mode 100644 index 000000000..567f0cc88 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs13.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS13` reader"] +pub type R = crate::R; +#[doc = "Register `CS13` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs13Spec; +impl crate::RegisterSpec for MbGroupCs13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs13::R`](R) reader structure"] +impl crate::Readable for MbGroupCs13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs13::W`](W) writer structure"] +impl crate::Writable for MbGroupCs13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS13 to value 0"] +impl crate::Resettable for MbGroupCs13Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs14.rs b/mcxa276-pac/src/can0/mb_group_cs14.rs new file mode 100644 index 000000000..85d1b95f9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs14.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS14` reader"] +pub type R = crate::R; +#[doc = "Register `CS14` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs14Spec; +impl crate::RegisterSpec for MbGroupCs14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs14::R`](R) reader structure"] +impl crate::Readable for MbGroupCs14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs14::W`](W) writer structure"] +impl crate::Writable for MbGroupCs14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS14 to value 0"] +impl crate::Resettable for MbGroupCs14Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs15.rs b/mcxa276-pac/src/can0/mb_group_cs15.rs new file mode 100644 index 000000000..f2a4c7f91 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs15.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS15` reader"] +pub type R = crate::R; +#[doc = "Register `CS15` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs15Spec; +impl crate::RegisterSpec for MbGroupCs15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs15::R`](R) reader structure"] +impl crate::Readable for MbGroupCs15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs15::W`](W) writer structure"] +impl crate::Writable for MbGroupCs15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS15 to value 0"] +impl crate::Resettable for MbGroupCs15Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs16.rs b/mcxa276-pac/src/can0/mb_group_cs16.rs new file mode 100644 index 000000000..c8e9ae120 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs16.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS16` reader"] +pub type R = crate::R; +#[doc = "Register `CS16` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs16Spec; +impl crate::RegisterSpec for MbGroupCs16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs16::R`](R) reader structure"] +impl crate::Readable for MbGroupCs16Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs16::W`](W) writer structure"] +impl crate::Writable for MbGroupCs16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS16 to value 0"] +impl crate::Resettable for MbGroupCs16Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs17.rs b/mcxa276-pac/src/can0/mb_group_cs17.rs new file mode 100644 index 000000000..f5150c686 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs17.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS17` reader"] +pub type R = crate::R; +#[doc = "Register `CS17` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs17Spec; +impl crate::RegisterSpec for MbGroupCs17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs17::R`](R) reader structure"] +impl crate::Readable for MbGroupCs17Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs17::W`](W) writer structure"] +impl crate::Writable for MbGroupCs17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS17 to value 0"] +impl crate::Resettable for MbGroupCs17Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs18.rs b/mcxa276-pac/src/can0/mb_group_cs18.rs new file mode 100644 index 000000000..2abac4b34 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs18.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS18` reader"] +pub type R = crate::R; +#[doc = "Register `CS18` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs18Spec; +impl crate::RegisterSpec for MbGroupCs18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs18::R`](R) reader structure"] +impl crate::Readable for MbGroupCs18Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs18::W`](W) writer structure"] +impl crate::Writable for MbGroupCs18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS18 to value 0"] +impl crate::Resettable for MbGroupCs18Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs19.rs b/mcxa276-pac/src/can0/mb_group_cs19.rs new file mode 100644 index 000000000..42d209cd5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs19.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS19` reader"] +pub type R = crate::R; +#[doc = "Register `CS19` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs19Spec; +impl crate::RegisterSpec for MbGroupCs19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs19::R`](R) reader structure"] +impl crate::Readable for MbGroupCs19Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs19::W`](W) writer structure"] +impl crate::Writable for MbGroupCs19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS19 to value 0"] +impl crate::Resettable for MbGroupCs19Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs2.rs b/mcxa276-pac/src/can0/mb_group_cs2.rs new file mode 100644 index 000000000..be1a59e3a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs2.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS2` reader"] +pub type R = crate::R; +#[doc = "Register `CS2` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs2Spec; +impl crate::RegisterSpec for MbGroupCs2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs2::R`](R) reader structure"] +impl crate::Readable for MbGroupCs2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs2::W`](W) writer structure"] +impl crate::Writable for MbGroupCs2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS2 to value 0"] +impl crate::Resettable for MbGroupCs2Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs20.rs b/mcxa276-pac/src/can0/mb_group_cs20.rs new file mode 100644 index 000000000..a06ec6212 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs20.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS20` reader"] +pub type R = crate::R; +#[doc = "Register `CS20` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs20Spec; +impl crate::RegisterSpec for MbGroupCs20Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs20::R`](R) reader structure"] +impl crate::Readable for MbGroupCs20Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs20::W`](W) writer structure"] +impl crate::Writable for MbGroupCs20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS20 to value 0"] +impl crate::Resettable for MbGroupCs20Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs21.rs b/mcxa276-pac/src/can0/mb_group_cs21.rs new file mode 100644 index 000000000..c357f07ed --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs21.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS21` reader"] +pub type R = crate::R; +#[doc = "Register `CS21` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs21Spec; +impl crate::RegisterSpec for MbGroupCs21Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs21::R`](R) reader structure"] +impl crate::Readable for MbGroupCs21Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs21::W`](W) writer structure"] +impl crate::Writable for MbGroupCs21Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS21 to value 0"] +impl crate::Resettable for MbGroupCs21Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs22.rs b/mcxa276-pac/src/can0/mb_group_cs22.rs new file mode 100644 index 000000000..ef7177879 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs22.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS22` reader"] +pub type R = crate::R; +#[doc = "Register `CS22` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs22Spec; +impl crate::RegisterSpec for MbGroupCs22Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs22::R`](R) reader structure"] +impl crate::Readable for MbGroupCs22Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs22::W`](W) writer structure"] +impl crate::Writable for MbGroupCs22Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS22 to value 0"] +impl crate::Resettable for MbGroupCs22Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs23.rs b/mcxa276-pac/src/can0/mb_group_cs23.rs new file mode 100644 index 000000000..524b32d71 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs23.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS23` reader"] +pub type R = crate::R; +#[doc = "Register `CS23` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs23Spec; +impl crate::RegisterSpec for MbGroupCs23Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs23::R`](R) reader structure"] +impl crate::Readable for MbGroupCs23Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs23::W`](W) writer structure"] +impl crate::Writable for MbGroupCs23Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS23 to value 0"] +impl crate::Resettable for MbGroupCs23Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs24.rs b/mcxa276-pac/src/can0/mb_group_cs24.rs new file mode 100644 index 000000000..76be50495 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs24.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS24` reader"] +pub type R = crate::R; +#[doc = "Register `CS24` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs24Spec; +impl crate::RegisterSpec for MbGroupCs24Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs24::R`](R) reader structure"] +impl crate::Readable for MbGroupCs24Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs24::W`](W) writer structure"] +impl crate::Writable for MbGroupCs24Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS24 to value 0"] +impl crate::Resettable for MbGroupCs24Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs25.rs b/mcxa276-pac/src/can0/mb_group_cs25.rs new file mode 100644 index 000000000..b08373c7f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs25.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS25` reader"] +pub type R = crate::R; +#[doc = "Register `CS25` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs25Spec; +impl crate::RegisterSpec for MbGroupCs25Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs25::R`](R) reader structure"] +impl crate::Readable for MbGroupCs25Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs25::W`](W) writer structure"] +impl crate::Writable for MbGroupCs25Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS25 to value 0"] +impl crate::Resettable for MbGroupCs25Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs26.rs b/mcxa276-pac/src/can0/mb_group_cs26.rs new file mode 100644 index 000000000..43cca1e61 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs26.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS26` reader"] +pub type R = crate::R; +#[doc = "Register `CS26` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs26Spec; +impl crate::RegisterSpec for MbGroupCs26Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs26::R`](R) reader structure"] +impl crate::Readable for MbGroupCs26Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs26::W`](W) writer structure"] +impl crate::Writable for MbGroupCs26Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS26 to value 0"] +impl crate::Resettable for MbGroupCs26Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs27.rs b/mcxa276-pac/src/can0/mb_group_cs27.rs new file mode 100644 index 000000000..c2bc40667 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs27.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS27` reader"] +pub type R = crate::R; +#[doc = "Register `CS27` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs27Spec; +impl crate::RegisterSpec for MbGroupCs27Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs27::R`](R) reader structure"] +impl crate::Readable for MbGroupCs27Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs27::W`](W) writer structure"] +impl crate::Writable for MbGroupCs27Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS27 to value 0"] +impl crate::Resettable for MbGroupCs27Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs28.rs b/mcxa276-pac/src/can0/mb_group_cs28.rs new file mode 100644 index 000000000..38321681d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs28.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS28` reader"] +pub type R = crate::R; +#[doc = "Register `CS28` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs28Spec; +impl crate::RegisterSpec for MbGroupCs28Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs28::R`](R) reader structure"] +impl crate::Readable for MbGroupCs28Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs28::W`](W) writer structure"] +impl crate::Writable for MbGroupCs28Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS28 to value 0"] +impl crate::Resettable for MbGroupCs28Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs29.rs b/mcxa276-pac/src/can0/mb_group_cs29.rs new file mode 100644 index 000000000..2d82aef84 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs29.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS29` reader"] +pub type R = crate::R; +#[doc = "Register `CS29` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs29Spec; +impl crate::RegisterSpec for MbGroupCs29Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs29::R`](R) reader structure"] +impl crate::Readable for MbGroupCs29Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs29::W`](W) writer structure"] +impl crate::Writable for MbGroupCs29Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS29 to value 0"] +impl crate::Resettable for MbGroupCs29Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs3.rs b/mcxa276-pac/src/can0/mb_group_cs3.rs new file mode 100644 index 000000000..a42c3e4b0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs3.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS3` reader"] +pub type R = crate::R; +#[doc = "Register `CS3` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs3Spec; +impl crate::RegisterSpec for MbGroupCs3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs3::R`](R) reader structure"] +impl crate::Readable for MbGroupCs3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs3::W`](W) writer structure"] +impl crate::Writable for MbGroupCs3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS3 to value 0"] +impl crate::Resettable for MbGroupCs3Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs30.rs b/mcxa276-pac/src/can0/mb_group_cs30.rs new file mode 100644 index 000000000..e8fd7468b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs30.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS30` reader"] +pub type R = crate::R; +#[doc = "Register `CS30` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs30Spec; +impl crate::RegisterSpec for MbGroupCs30Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs30::R`](R) reader structure"] +impl crate::Readable for MbGroupCs30Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs30::W`](W) writer structure"] +impl crate::Writable for MbGroupCs30Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS30 to value 0"] +impl crate::Resettable for MbGroupCs30Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs31.rs b/mcxa276-pac/src/can0/mb_group_cs31.rs new file mode 100644 index 000000000..11edfae3e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs31.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS31` reader"] +pub type R = crate::R; +#[doc = "Register `CS31` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs31Spec; +impl crate::RegisterSpec for MbGroupCs31Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs31::R`](R) reader structure"] +impl crate::Readable for MbGroupCs31Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs31::W`](W) writer structure"] +impl crate::Writable for MbGroupCs31Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS31 to value 0"] +impl crate::Resettable for MbGroupCs31Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs4.rs b/mcxa276-pac/src/can0/mb_group_cs4.rs new file mode 100644 index 000000000..e6f2125d1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs4.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS4` reader"] +pub type R = crate::R; +#[doc = "Register `CS4` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs4Spec; +impl crate::RegisterSpec for MbGroupCs4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs4::R`](R) reader structure"] +impl crate::Readable for MbGroupCs4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs4::W`](W) writer structure"] +impl crate::Writable for MbGroupCs4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS4 to value 0"] +impl crate::Resettable for MbGroupCs4Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs5.rs b/mcxa276-pac/src/can0/mb_group_cs5.rs new file mode 100644 index 000000000..0103fd6b3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs5.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS5` reader"] +pub type R = crate::R; +#[doc = "Register `CS5` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs5Spec; +impl crate::RegisterSpec for MbGroupCs5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs5::R`](R) reader structure"] +impl crate::Readable for MbGroupCs5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs5::W`](W) writer structure"] +impl crate::Writable for MbGroupCs5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS5 to value 0"] +impl crate::Resettable for MbGroupCs5Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs6.rs b/mcxa276-pac/src/can0/mb_group_cs6.rs new file mode 100644 index 000000000..52bf61660 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs6.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS6` reader"] +pub type R = crate::R; +#[doc = "Register `CS6` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs6Spec; +impl crate::RegisterSpec for MbGroupCs6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs6::R`](R) reader structure"] +impl crate::Readable for MbGroupCs6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs6::W`](W) writer structure"] +impl crate::Writable for MbGroupCs6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS6 to value 0"] +impl crate::Resettable for MbGroupCs6Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs7.rs b/mcxa276-pac/src/can0/mb_group_cs7.rs new file mode 100644 index 000000000..cfb694949 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs7.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS7` reader"] +pub type R = crate::R; +#[doc = "Register `CS7` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs7Spec; +impl crate::RegisterSpec for MbGroupCs7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs7::R`](R) reader structure"] +impl crate::Readable for MbGroupCs7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs7::W`](W) writer structure"] +impl crate::Writable for MbGroupCs7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS7 to value 0"] +impl crate::Resettable for MbGroupCs7Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs8.rs b/mcxa276-pac/src/can0/mb_group_cs8.rs new file mode 100644 index 000000000..6fe0e149f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs8.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS8` reader"] +pub type R = crate::R; +#[doc = "Register `CS8` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs8Spec; +impl crate::RegisterSpec for MbGroupCs8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs8::R`](R) reader structure"] +impl crate::Readable for MbGroupCs8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs8::W`](W) writer structure"] +impl crate::Writable for MbGroupCs8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS8 to value 0"] +impl crate::Resettable for MbGroupCs8Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs9.rs b/mcxa276-pac/src/can0/mb_group_cs9.rs new file mode 100644 index 000000000..22266fe90 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_cs9.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CS9` reader"] +pub type R = crate::R; +#[doc = "Register `CS9` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampR = crate::FieldReader; +#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] +pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrR = crate::BitReader; +#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] +pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeR = crate::FieldReader; +#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] +pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiR = crate::BitReader; +#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] +pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsR = crate::BitReader; +#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] +pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlR = crate::BitReader; +#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] +pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&self) -> TimeStampR { + TimeStampR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&self) -> CodeR { + CodeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&self) -> EsiR { + EsiR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&self) -> BrsR { + BrsR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&self) -> EdlR { + EdlR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] + #[inline(always)] + pub fn time_stamp(&mut self) -> TimeStampW { + TimeStampW::new(self, 0) + } + #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 16) + } + #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 20) + } + #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] + #[inline(always)] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 21) + } + #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] + #[inline(always)] + pub fn srr(&mut self) -> SrrW { + SrrW::new(self, 22) + } + #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] + #[inline(always)] + pub fn code(&mut self) -> CodeW { + CodeW::new(self, 24) + } + #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] + #[inline(always)] + pub fn esi(&mut self) -> EsiW { + EsiW::new(self, 29) + } + #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] + #[inline(always)] + pub fn brs(&mut self) -> BrsW { + BrsW::new(self, 30) + } + #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] + #[inline(always)] + pub fn edl(&mut self) -> EdlW { + EdlW::new(self, 31) + } +} +#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupCs9Spec; +impl crate::RegisterSpec for MbGroupCs9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_cs9::R`](R) reader structure"] +impl crate::Readable for MbGroupCs9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_cs9::W`](W) writer structure"] +impl crate::Writable for MbGroupCs9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CS9 to value 0"] +impl crate::Resettable for MbGroupCs9Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id0.rs b/mcxa276-pac/src/can0/mb_group_id0.rs new file mode 100644 index 000000000..e3d894434 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID0` reader"] +pub type R = crate::R; +#[doc = "Register `ID0` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId0Spec; +impl crate::RegisterSpec for MbGroupId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id0::R`](R) reader structure"] +impl crate::Readable for MbGroupId0Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id0::W`](W) writer structure"] +impl crate::Writable for MbGroupId0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0 to value 0"] +impl crate::Resettable for MbGroupId0Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id1.rs b/mcxa276-pac/src/can0/mb_group_id1.rs new file mode 100644 index 000000000..619300055 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID1` reader"] +pub type R = crate::R; +#[doc = "Register `ID1` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId1Spec; +impl crate::RegisterSpec for MbGroupId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id1::R`](R) reader structure"] +impl crate::Readable for MbGroupId1Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id1::W`](W) writer structure"] +impl crate::Writable for MbGroupId1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1 to value 0"] +impl crate::Resettable for MbGroupId1Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id10.rs b/mcxa276-pac/src/can0/mb_group_id10.rs new file mode 100644 index 000000000..233cbe14b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id10.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID10` reader"] +pub type R = crate::R; +#[doc = "Register `ID10` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId10Spec; +impl crate::RegisterSpec for MbGroupId10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id10::R`](R) reader structure"] +impl crate::Readable for MbGroupId10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id10::W`](W) writer structure"] +impl crate::Writable for MbGroupId10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID10 to value 0"] +impl crate::Resettable for MbGroupId10Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id11.rs b/mcxa276-pac/src/can0/mb_group_id11.rs new file mode 100644 index 000000000..10c07330d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id11.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID11` reader"] +pub type R = crate::R; +#[doc = "Register `ID11` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId11Spec; +impl crate::RegisterSpec for MbGroupId11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id11::R`](R) reader structure"] +impl crate::Readable for MbGroupId11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id11::W`](W) writer structure"] +impl crate::Writable for MbGroupId11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID11 to value 0"] +impl crate::Resettable for MbGroupId11Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id12.rs b/mcxa276-pac/src/can0/mb_group_id12.rs new file mode 100644 index 000000000..adae1a5d0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id12.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID12` reader"] +pub type R = crate::R; +#[doc = "Register `ID12` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId12Spec; +impl crate::RegisterSpec for MbGroupId12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id12::R`](R) reader structure"] +impl crate::Readable for MbGroupId12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id12::W`](W) writer structure"] +impl crate::Writable for MbGroupId12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID12 to value 0"] +impl crate::Resettable for MbGroupId12Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id13.rs b/mcxa276-pac/src/can0/mb_group_id13.rs new file mode 100644 index 000000000..8e3cdc83f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id13.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID13` reader"] +pub type R = crate::R; +#[doc = "Register `ID13` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId13Spec; +impl crate::RegisterSpec for MbGroupId13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id13::R`](R) reader structure"] +impl crate::Readable for MbGroupId13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id13::W`](W) writer structure"] +impl crate::Writable for MbGroupId13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID13 to value 0"] +impl crate::Resettable for MbGroupId13Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id14.rs b/mcxa276-pac/src/can0/mb_group_id14.rs new file mode 100644 index 000000000..5e4705e52 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id14.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID14` reader"] +pub type R = crate::R; +#[doc = "Register `ID14` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId14Spec; +impl crate::RegisterSpec for MbGroupId14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id14::R`](R) reader structure"] +impl crate::Readable for MbGroupId14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id14::W`](W) writer structure"] +impl crate::Writable for MbGroupId14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID14 to value 0"] +impl crate::Resettable for MbGroupId14Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id15.rs b/mcxa276-pac/src/can0/mb_group_id15.rs new file mode 100644 index 000000000..1665afe8b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id15.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID15` reader"] +pub type R = crate::R; +#[doc = "Register `ID15` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId15Spec; +impl crate::RegisterSpec for MbGroupId15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id15::R`](R) reader structure"] +impl crate::Readable for MbGroupId15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id15::W`](W) writer structure"] +impl crate::Writable for MbGroupId15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID15 to value 0"] +impl crate::Resettable for MbGroupId15Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id16.rs b/mcxa276-pac/src/can0/mb_group_id16.rs new file mode 100644 index 000000000..6a30b2f27 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id16.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID16` reader"] +pub type R = crate::R; +#[doc = "Register `ID16` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId16Spec; +impl crate::RegisterSpec for MbGroupId16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id16::R`](R) reader structure"] +impl crate::Readable for MbGroupId16Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id16::W`](W) writer structure"] +impl crate::Writable for MbGroupId16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID16 to value 0"] +impl crate::Resettable for MbGroupId16Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id17.rs b/mcxa276-pac/src/can0/mb_group_id17.rs new file mode 100644 index 000000000..1d5544aee --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id17.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID17` reader"] +pub type R = crate::R; +#[doc = "Register `ID17` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId17Spec; +impl crate::RegisterSpec for MbGroupId17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id17::R`](R) reader structure"] +impl crate::Readable for MbGroupId17Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id17::W`](W) writer structure"] +impl crate::Writable for MbGroupId17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID17 to value 0"] +impl crate::Resettable for MbGroupId17Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id18.rs b/mcxa276-pac/src/can0/mb_group_id18.rs new file mode 100644 index 000000000..61dc3e48d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id18.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID18` reader"] +pub type R = crate::R; +#[doc = "Register `ID18` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId18Spec; +impl crate::RegisterSpec for MbGroupId18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id18::R`](R) reader structure"] +impl crate::Readable for MbGroupId18Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id18::W`](W) writer structure"] +impl crate::Writable for MbGroupId18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID18 to value 0"] +impl crate::Resettable for MbGroupId18Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id19.rs b/mcxa276-pac/src/can0/mb_group_id19.rs new file mode 100644 index 000000000..a4f3b2284 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id19.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID19` reader"] +pub type R = crate::R; +#[doc = "Register `ID19` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId19Spec; +impl crate::RegisterSpec for MbGroupId19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id19::R`](R) reader structure"] +impl crate::Readable for MbGroupId19Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id19::W`](W) writer structure"] +impl crate::Writable for MbGroupId19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID19 to value 0"] +impl crate::Resettable for MbGroupId19Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id2.rs b/mcxa276-pac/src/can0/mb_group_id2.rs new file mode 100644 index 000000000..14c8e9289 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID2` reader"] +pub type R = crate::R; +#[doc = "Register `ID2` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId2Spec; +impl crate::RegisterSpec for MbGroupId2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id2::R`](R) reader structure"] +impl crate::Readable for MbGroupId2Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id2::W`](W) writer structure"] +impl crate::Writable for MbGroupId2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID2 to value 0"] +impl crate::Resettable for MbGroupId2Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id20.rs b/mcxa276-pac/src/can0/mb_group_id20.rs new file mode 100644 index 000000000..8421b0af7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id20.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID20` reader"] +pub type R = crate::R; +#[doc = "Register `ID20` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId20Spec; +impl crate::RegisterSpec for MbGroupId20Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id20::R`](R) reader structure"] +impl crate::Readable for MbGroupId20Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id20::W`](W) writer structure"] +impl crate::Writable for MbGroupId20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID20 to value 0"] +impl crate::Resettable for MbGroupId20Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id21.rs b/mcxa276-pac/src/can0/mb_group_id21.rs new file mode 100644 index 000000000..40cff6b4c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id21.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID21` reader"] +pub type R = crate::R; +#[doc = "Register `ID21` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId21Spec; +impl crate::RegisterSpec for MbGroupId21Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id21::R`](R) reader structure"] +impl crate::Readable for MbGroupId21Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id21::W`](W) writer structure"] +impl crate::Writable for MbGroupId21Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID21 to value 0"] +impl crate::Resettable for MbGroupId21Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id22.rs b/mcxa276-pac/src/can0/mb_group_id22.rs new file mode 100644 index 000000000..887ed99e1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id22.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID22` reader"] +pub type R = crate::R; +#[doc = "Register `ID22` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId22Spec; +impl crate::RegisterSpec for MbGroupId22Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id22::R`](R) reader structure"] +impl crate::Readable for MbGroupId22Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id22::W`](W) writer structure"] +impl crate::Writable for MbGroupId22Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID22 to value 0"] +impl crate::Resettable for MbGroupId22Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id23.rs b/mcxa276-pac/src/can0/mb_group_id23.rs new file mode 100644 index 000000000..7860d067d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id23.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID23` reader"] +pub type R = crate::R; +#[doc = "Register `ID23` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId23Spec; +impl crate::RegisterSpec for MbGroupId23Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id23::R`](R) reader structure"] +impl crate::Readable for MbGroupId23Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id23::W`](W) writer structure"] +impl crate::Writable for MbGroupId23Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID23 to value 0"] +impl crate::Resettable for MbGroupId23Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id24.rs b/mcxa276-pac/src/can0/mb_group_id24.rs new file mode 100644 index 000000000..d3294c2b8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id24.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID24` reader"] +pub type R = crate::R; +#[doc = "Register `ID24` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId24Spec; +impl crate::RegisterSpec for MbGroupId24Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id24::R`](R) reader structure"] +impl crate::Readable for MbGroupId24Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id24::W`](W) writer structure"] +impl crate::Writable for MbGroupId24Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID24 to value 0"] +impl crate::Resettable for MbGroupId24Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id25.rs b/mcxa276-pac/src/can0/mb_group_id25.rs new file mode 100644 index 000000000..46d8a49d6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id25.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID25` reader"] +pub type R = crate::R; +#[doc = "Register `ID25` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId25Spec; +impl crate::RegisterSpec for MbGroupId25Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id25::R`](R) reader structure"] +impl crate::Readable for MbGroupId25Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id25::W`](W) writer structure"] +impl crate::Writable for MbGroupId25Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID25 to value 0"] +impl crate::Resettable for MbGroupId25Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id26.rs b/mcxa276-pac/src/can0/mb_group_id26.rs new file mode 100644 index 000000000..4eea3ac3d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id26.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID26` reader"] +pub type R = crate::R; +#[doc = "Register `ID26` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId26Spec; +impl crate::RegisterSpec for MbGroupId26Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id26::R`](R) reader structure"] +impl crate::Readable for MbGroupId26Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id26::W`](W) writer structure"] +impl crate::Writable for MbGroupId26Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID26 to value 0"] +impl crate::Resettable for MbGroupId26Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id27.rs b/mcxa276-pac/src/can0/mb_group_id27.rs new file mode 100644 index 000000000..89c2b2c6c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id27.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID27` reader"] +pub type R = crate::R; +#[doc = "Register `ID27` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId27Spec; +impl crate::RegisterSpec for MbGroupId27Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id27::R`](R) reader structure"] +impl crate::Readable for MbGroupId27Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id27::W`](W) writer structure"] +impl crate::Writable for MbGroupId27Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID27 to value 0"] +impl crate::Resettable for MbGroupId27Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id28.rs b/mcxa276-pac/src/can0/mb_group_id28.rs new file mode 100644 index 000000000..5aeff5356 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id28.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID28` reader"] +pub type R = crate::R; +#[doc = "Register `ID28` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId28Spec; +impl crate::RegisterSpec for MbGroupId28Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id28::R`](R) reader structure"] +impl crate::Readable for MbGroupId28Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id28::W`](W) writer structure"] +impl crate::Writable for MbGroupId28Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID28 to value 0"] +impl crate::Resettable for MbGroupId28Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id29.rs b/mcxa276-pac/src/can0/mb_group_id29.rs new file mode 100644 index 000000000..32f887329 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id29.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID29` reader"] +pub type R = crate::R; +#[doc = "Register `ID29` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId29Spec; +impl crate::RegisterSpec for MbGroupId29Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id29::R`](R) reader structure"] +impl crate::Readable for MbGroupId29Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id29::W`](W) writer structure"] +impl crate::Writable for MbGroupId29Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID29 to value 0"] +impl crate::Resettable for MbGroupId29Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id3.rs b/mcxa276-pac/src/can0/mb_group_id3.rs new file mode 100644 index 000000000..7aeb45c76 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID3` reader"] +pub type R = crate::R; +#[doc = "Register `ID3` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId3Spec; +impl crate::RegisterSpec for MbGroupId3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id3::R`](R) reader structure"] +impl crate::Readable for MbGroupId3Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id3::W`](W) writer structure"] +impl crate::Writable for MbGroupId3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID3 to value 0"] +impl crate::Resettable for MbGroupId3Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id30.rs b/mcxa276-pac/src/can0/mb_group_id30.rs new file mode 100644 index 000000000..3583657ec --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id30.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID30` reader"] +pub type R = crate::R; +#[doc = "Register `ID30` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId30Spec; +impl crate::RegisterSpec for MbGroupId30Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id30::R`](R) reader structure"] +impl crate::Readable for MbGroupId30Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id30::W`](W) writer structure"] +impl crate::Writable for MbGroupId30Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID30 to value 0"] +impl crate::Resettable for MbGroupId30Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id31.rs b/mcxa276-pac/src/can0/mb_group_id31.rs new file mode 100644 index 000000000..fa3972aa7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id31.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID31` reader"] +pub type R = crate::R; +#[doc = "Register `ID31` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId31Spec; +impl crate::RegisterSpec for MbGroupId31Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id31::R`](R) reader structure"] +impl crate::Readable for MbGroupId31Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id31::W`](W) writer structure"] +impl crate::Writable for MbGroupId31Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID31 to value 0"] +impl crate::Resettable for MbGroupId31Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id4.rs b/mcxa276-pac/src/can0/mb_group_id4.rs new file mode 100644 index 000000000..26619251d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID4` reader"] +pub type R = crate::R; +#[doc = "Register `ID4` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId4Spec; +impl crate::RegisterSpec for MbGroupId4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id4::R`](R) reader structure"] +impl crate::Readable for MbGroupId4Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id4::W`](W) writer structure"] +impl crate::Writable for MbGroupId4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID4 to value 0"] +impl crate::Resettable for MbGroupId4Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id5.rs b/mcxa276-pac/src/can0/mb_group_id5.rs new file mode 100644 index 000000000..40602ee2c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID5` reader"] +pub type R = crate::R; +#[doc = "Register `ID5` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId5Spec; +impl crate::RegisterSpec for MbGroupId5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id5::R`](R) reader structure"] +impl crate::Readable for MbGroupId5Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id5::W`](W) writer structure"] +impl crate::Writable for MbGroupId5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID5 to value 0"] +impl crate::Resettable for MbGroupId5Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id6.rs b/mcxa276-pac/src/can0/mb_group_id6.rs new file mode 100644 index 000000000..1e22cfbc7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id6.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID6` reader"] +pub type R = crate::R; +#[doc = "Register `ID6` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId6Spec; +impl crate::RegisterSpec for MbGroupId6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id6::R`](R) reader structure"] +impl crate::Readable for MbGroupId6Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id6::W`](W) writer structure"] +impl crate::Writable for MbGroupId6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID6 to value 0"] +impl crate::Resettable for MbGroupId6Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id7.rs b/mcxa276-pac/src/can0/mb_group_id7.rs new file mode 100644 index 000000000..e63b16d20 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id7.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID7` reader"] +pub type R = crate::R; +#[doc = "Register `ID7` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId7Spec; +impl crate::RegisterSpec for MbGroupId7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id7::R`](R) reader structure"] +impl crate::Readable for MbGroupId7Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id7::W`](W) writer structure"] +impl crate::Writable for MbGroupId7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID7 to value 0"] +impl crate::Resettable for MbGroupId7Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id8.rs b/mcxa276-pac/src/can0/mb_group_id8.rs new file mode 100644 index 000000000..47f5e1756 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id8.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID8` reader"] +pub type R = crate::R; +#[doc = "Register `ID8` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId8Spec; +impl crate::RegisterSpec for MbGroupId8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id8::R`](R) reader structure"] +impl crate::Readable for MbGroupId8Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id8::W`](W) writer structure"] +impl crate::Writable for MbGroupId8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID8 to value 0"] +impl crate::Resettable for MbGroupId8Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id9.rs b/mcxa276-pac/src/can0/mb_group_id9.rs new file mode 100644 index 000000000..882ebea03 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_id9.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID9` reader"] +pub type R = crate::R; +#[doc = "Register `ID9` writer"] +pub type W = crate::W; +#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] +pub type ExtR = crate::FieldReader; +#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] +pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdR = crate::FieldReader; +#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] +pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioR = crate::FieldReader; +#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] +pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&self) -> ExtR { + ExtR::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&self) -> StdR { + StdR::new(((self.bits >> 18) & 0x07ff) as u16) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&self) -> PrioR { + PrioR::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] + #[inline(always)] + pub fn ext(&mut self) -> ExtW { + ExtW::new(self, 0) + } + #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] + #[inline(always)] + pub fn std(&mut self) -> StdW { + StdW::new(self, 18) + } + #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] + #[inline(always)] + pub fn prio(&mut self) -> PrioW { + PrioW::new(self, 29) + } +} +#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupId9Spec; +impl crate::RegisterSpec for MbGroupId9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_id9::R`](R) reader structure"] +impl crate::Readable for MbGroupId9Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_id9::W`](W) writer structure"] +impl crate::Writable for MbGroupId9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID9 to value 0"] +impl crate::Resettable for MbGroupId9Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word00.rs b/mcxa276-pac/src/can0/mb_group_word00.rs new file mode 100644 index 000000000..d8857f3ed --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word00.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD00` reader"] +pub type R = crate::R; +#[doc = "Register `WORD00` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word00::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word00::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord00Spec; +impl crate::RegisterSpec for MbGroupWord00Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word00::R`](R) reader structure"] +impl crate::Readable for MbGroupWord00Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word00::W`](W) writer structure"] +impl crate::Writable for MbGroupWord00Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD00 to value 0"] +impl crate::Resettable for MbGroupWord00Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word01.rs b/mcxa276-pac/src/can0/mb_group_word01.rs new file mode 100644 index 000000000..31a4461c6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word01.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD01` reader"] +pub type R = crate::R; +#[doc = "Register `WORD01` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word01::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word01::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord01Spec; +impl crate::RegisterSpec for MbGroupWord01Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word01::R`](R) reader structure"] +impl crate::Readable for MbGroupWord01Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word01::W`](W) writer structure"] +impl crate::Writable for MbGroupWord01Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD01 to value 0"] +impl crate::Resettable for MbGroupWord01Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word010.rs b/mcxa276-pac/src/can0/mb_group_word010.rs new file mode 100644 index 000000000..c2ceee444 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word010.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD010` reader"] +pub type R = crate::R; +#[doc = "Register `WORD010` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word010::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word010::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord010Spec; +impl crate::RegisterSpec for MbGroupWord010Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word010::R`](R) reader structure"] +impl crate::Readable for MbGroupWord010Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word010::W`](W) writer structure"] +impl crate::Writable for MbGroupWord010Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD010 to value 0"] +impl crate::Resettable for MbGroupWord010Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word011.rs b/mcxa276-pac/src/can0/mb_group_word011.rs new file mode 100644 index 000000000..fad4380b1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word011.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD011` reader"] +pub type R = crate::R; +#[doc = "Register `WORD011` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word011::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word011::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord011Spec; +impl crate::RegisterSpec for MbGroupWord011Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word011::R`](R) reader structure"] +impl crate::Readable for MbGroupWord011Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word011::W`](W) writer structure"] +impl crate::Writable for MbGroupWord011Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD011 to value 0"] +impl crate::Resettable for MbGroupWord011Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word012.rs b/mcxa276-pac/src/can0/mb_group_word012.rs new file mode 100644 index 000000000..8049c514a --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word012.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD012` reader"] +pub type R = crate::R; +#[doc = "Register `WORD012` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word012::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word012::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord012Spec; +impl crate::RegisterSpec for MbGroupWord012Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word012::R`](R) reader structure"] +impl crate::Readable for MbGroupWord012Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word012::W`](W) writer structure"] +impl crate::Writable for MbGroupWord012Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD012 to value 0"] +impl crate::Resettable for MbGroupWord012Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word013.rs b/mcxa276-pac/src/can0/mb_group_word013.rs new file mode 100644 index 000000000..602e8354e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word013.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD013` reader"] +pub type R = crate::R; +#[doc = "Register `WORD013` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word013::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word013::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord013Spec; +impl crate::RegisterSpec for MbGroupWord013Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word013::R`](R) reader structure"] +impl crate::Readable for MbGroupWord013Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word013::W`](W) writer structure"] +impl crate::Writable for MbGroupWord013Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD013 to value 0"] +impl crate::Resettable for MbGroupWord013Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word014.rs b/mcxa276-pac/src/can0/mb_group_word014.rs new file mode 100644 index 000000000..0e4914c24 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word014.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD014` reader"] +pub type R = crate::R; +#[doc = "Register `WORD014` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word014::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word014::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord014Spec; +impl crate::RegisterSpec for MbGroupWord014Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word014::R`](R) reader structure"] +impl crate::Readable for MbGroupWord014Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word014::W`](W) writer structure"] +impl crate::Writable for MbGroupWord014Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD014 to value 0"] +impl crate::Resettable for MbGroupWord014Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word015.rs b/mcxa276-pac/src/can0/mb_group_word015.rs new file mode 100644 index 000000000..2d6aabaea --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word015.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD015` reader"] +pub type R = crate::R; +#[doc = "Register `WORD015` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word015::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word015::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord015Spec; +impl crate::RegisterSpec for MbGroupWord015Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word015::R`](R) reader structure"] +impl crate::Readable for MbGroupWord015Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word015::W`](W) writer structure"] +impl crate::Writable for MbGroupWord015Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD015 to value 0"] +impl crate::Resettable for MbGroupWord015Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word016.rs b/mcxa276-pac/src/can0/mb_group_word016.rs new file mode 100644 index 000000000..a3bc01eff --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word016.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD016` reader"] +pub type R = crate::R; +#[doc = "Register `WORD016` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word016::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word016::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord016Spec; +impl crate::RegisterSpec for MbGroupWord016Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word016::R`](R) reader structure"] +impl crate::Readable for MbGroupWord016Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word016::W`](W) writer structure"] +impl crate::Writable for MbGroupWord016Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD016 to value 0"] +impl crate::Resettable for MbGroupWord016Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word017.rs b/mcxa276-pac/src/can0/mb_group_word017.rs new file mode 100644 index 000000000..d1d2d29c5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word017.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD017` reader"] +pub type R = crate::R; +#[doc = "Register `WORD017` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word017::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word017::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord017Spec; +impl crate::RegisterSpec for MbGroupWord017Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word017::R`](R) reader structure"] +impl crate::Readable for MbGroupWord017Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word017::W`](W) writer structure"] +impl crate::Writable for MbGroupWord017Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD017 to value 0"] +impl crate::Resettable for MbGroupWord017Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word018.rs b/mcxa276-pac/src/can0/mb_group_word018.rs new file mode 100644 index 000000000..bd584b8d3 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word018.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD018` reader"] +pub type R = crate::R; +#[doc = "Register `WORD018` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word018::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word018::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord018Spec; +impl crate::RegisterSpec for MbGroupWord018Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word018::R`](R) reader structure"] +impl crate::Readable for MbGroupWord018Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word018::W`](W) writer structure"] +impl crate::Writable for MbGroupWord018Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD018 to value 0"] +impl crate::Resettable for MbGroupWord018Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word019.rs b/mcxa276-pac/src/can0/mb_group_word019.rs new file mode 100644 index 000000000..85711056b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word019.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD019` reader"] +pub type R = crate::R; +#[doc = "Register `WORD019` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word019::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word019::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord019Spec; +impl crate::RegisterSpec for MbGroupWord019Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word019::R`](R) reader structure"] +impl crate::Readable for MbGroupWord019Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word019::W`](W) writer structure"] +impl crate::Writable for MbGroupWord019Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD019 to value 0"] +impl crate::Resettable for MbGroupWord019Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word02.rs b/mcxa276-pac/src/can0/mb_group_word02.rs new file mode 100644 index 000000000..b54221d12 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word02.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD02` reader"] +pub type R = crate::R; +#[doc = "Register `WORD02` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word02::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word02::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord02Spec; +impl crate::RegisterSpec for MbGroupWord02Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word02::R`](R) reader structure"] +impl crate::Readable for MbGroupWord02Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word02::W`](W) writer structure"] +impl crate::Writable for MbGroupWord02Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD02 to value 0"] +impl crate::Resettable for MbGroupWord02Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word020.rs b/mcxa276-pac/src/can0/mb_group_word020.rs new file mode 100644 index 000000000..e42568514 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word020.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD020` reader"] +pub type R = crate::R; +#[doc = "Register `WORD020` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word020::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word020::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord020Spec; +impl crate::RegisterSpec for MbGroupWord020Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word020::R`](R) reader structure"] +impl crate::Readable for MbGroupWord020Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word020::W`](W) writer structure"] +impl crate::Writable for MbGroupWord020Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD020 to value 0"] +impl crate::Resettable for MbGroupWord020Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word021.rs b/mcxa276-pac/src/can0/mb_group_word021.rs new file mode 100644 index 000000000..0aadc8a92 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word021.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD021` reader"] +pub type R = crate::R; +#[doc = "Register `WORD021` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 21 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word021::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word021::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord021Spec; +impl crate::RegisterSpec for MbGroupWord021Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word021::R`](R) reader structure"] +impl crate::Readable for MbGroupWord021Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word021::W`](W) writer structure"] +impl crate::Writable for MbGroupWord021Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD021 to value 0"] +impl crate::Resettable for MbGroupWord021Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word022.rs b/mcxa276-pac/src/can0/mb_group_word022.rs new file mode 100644 index 000000000..c99006982 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word022.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD022` reader"] +pub type R = crate::R; +#[doc = "Register `WORD022` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 22 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word022::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word022::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord022Spec; +impl crate::RegisterSpec for MbGroupWord022Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word022::R`](R) reader structure"] +impl crate::Readable for MbGroupWord022Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word022::W`](W) writer structure"] +impl crate::Writable for MbGroupWord022Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD022 to value 0"] +impl crate::Resettable for MbGroupWord022Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word023.rs b/mcxa276-pac/src/can0/mb_group_word023.rs new file mode 100644 index 000000000..4d56fc116 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word023.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD023` reader"] +pub type R = crate::R; +#[doc = "Register `WORD023` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 23 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word023::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word023::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord023Spec; +impl crate::RegisterSpec for MbGroupWord023Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word023::R`](R) reader structure"] +impl crate::Readable for MbGroupWord023Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word023::W`](W) writer structure"] +impl crate::Writable for MbGroupWord023Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD023 to value 0"] +impl crate::Resettable for MbGroupWord023Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word024.rs b/mcxa276-pac/src/can0/mb_group_word024.rs new file mode 100644 index 000000000..625d0bcf9 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word024.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD024` reader"] +pub type R = crate::R; +#[doc = "Register `WORD024` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 24 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word024::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word024::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord024Spec; +impl crate::RegisterSpec for MbGroupWord024Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word024::R`](R) reader structure"] +impl crate::Readable for MbGroupWord024Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word024::W`](W) writer structure"] +impl crate::Writable for MbGroupWord024Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD024 to value 0"] +impl crate::Resettable for MbGroupWord024Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word025.rs b/mcxa276-pac/src/can0/mb_group_word025.rs new file mode 100644 index 000000000..bebd23261 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word025.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD025` reader"] +pub type R = crate::R; +#[doc = "Register `WORD025` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 25 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word025::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word025::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord025Spec; +impl crate::RegisterSpec for MbGroupWord025Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word025::R`](R) reader structure"] +impl crate::Readable for MbGroupWord025Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word025::W`](W) writer structure"] +impl crate::Writable for MbGroupWord025Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD025 to value 0"] +impl crate::Resettable for MbGroupWord025Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word026.rs b/mcxa276-pac/src/can0/mb_group_word026.rs new file mode 100644 index 000000000..fbb3112df --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word026.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD026` reader"] +pub type R = crate::R; +#[doc = "Register `WORD026` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 26 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word026::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word026::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord026Spec; +impl crate::RegisterSpec for MbGroupWord026Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word026::R`](R) reader structure"] +impl crate::Readable for MbGroupWord026Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word026::W`](W) writer structure"] +impl crate::Writable for MbGroupWord026Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD026 to value 0"] +impl crate::Resettable for MbGroupWord026Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word027.rs b/mcxa276-pac/src/can0/mb_group_word027.rs new file mode 100644 index 000000000..a21f55fdb --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word027.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD027` reader"] +pub type R = crate::R; +#[doc = "Register `WORD027` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 27 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word027::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word027::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord027Spec; +impl crate::RegisterSpec for MbGroupWord027Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word027::R`](R) reader structure"] +impl crate::Readable for MbGroupWord027Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word027::W`](W) writer structure"] +impl crate::Writable for MbGroupWord027Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD027 to value 0"] +impl crate::Resettable for MbGroupWord027Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word028.rs b/mcxa276-pac/src/can0/mb_group_word028.rs new file mode 100644 index 000000000..9529fb1c2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word028.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD028` reader"] +pub type R = crate::R; +#[doc = "Register `WORD028` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 28 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word028::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word028::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord028Spec; +impl crate::RegisterSpec for MbGroupWord028Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word028::R`](R) reader structure"] +impl crate::Readable for MbGroupWord028Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word028::W`](W) writer structure"] +impl crate::Writable for MbGroupWord028Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD028 to value 0"] +impl crate::Resettable for MbGroupWord028Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word029.rs b/mcxa276-pac/src/can0/mb_group_word029.rs new file mode 100644 index 000000000..6a33706dd --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word029.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD029` reader"] +pub type R = crate::R; +#[doc = "Register `WORD029` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 29 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word029::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word029::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord029Spec; +impl crate::RegisterSpec for MbGroupWord029Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word029::R`](R) reader structure"] +impl crate::Readable for MbGroupWord029Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word029::W`](W) writer structure"] +impl crate::Writable for MbGroupWord029Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD029 to value 0"] +impl crate::Resettable for MbGroupWord029Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word03.rs b/mcxa276-pac/src/can0/mb_group_word03.rs new file mode 100644 index 000000000..8cb49f8a0 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word03.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD03` reader"] +pub type R = crate::R; +#[doc = "Register `WORD03` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word03::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word03::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord03Spec; +impl crate::RegisterSpec for MbGroupWord03Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word03::R`](R) reader structure"] +impl crate::Readable for MbGroupWord03Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word03::W`](W) writer structure"] +impl crate::Writable for MbGroupWord03Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD03 to value 0"] +impl crate::Resettable for MbGroupWord03Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word030.rs b/mcxa276-pac/src/can0/mb_group_word030.rs new file mode 100644 index 000000000..46e693ee5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word030.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD030` reader"] +pub type R = crate::R; +#[doc = "Register `WORD030` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 30 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word030::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word030::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord030Spec; +impl crate::RegisterSpec for MbGroupWord030Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word030::R`](R) reader structure"] +impl crate::Readable for MbGroupWord030Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word030::W`](W) writer structure"] +impl crate::Writable for MbGroupWord030Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD030 to value 0"] +impl crate::Resettable for MbGroupWord030Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word031.rs b/mcxa276-pac/src/can0/mb_group_word031.rs new file mode 100644 index 000000000..4f875a2b6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word031.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD031` reader"] +pub type R = crate::R; +#[doc = "Register `WORD031` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 31 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word031::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word031::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord031Spec; +impl crate::RegisterSpec for MbGroupWord031Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word031::R`](R) reader structure"] +impl crate::Readable for MbGroupWord031Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word031::W`](W) writer structure"] +impl crate::Writable for MbGroupWord031Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD031 to value 0"] +impl crate::Resettable for MbGroupWord031Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word04.rs b/mcxa276-pac/src/can0/mb_group_word04.rs new file mode 100644 index 000000000..9465fd728 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word04.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD04` reader"] +pub type R = crate::R; +#[doc = "Register `WORD04` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word04::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word04::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord04Spec; +impl crate::RegisterSpec for MbGroupWord04Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word04::R`](R) reader structure"] +impl crate::Readable for MbGroupWord04Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word04::W`](W) writer structure"] +impl crate::Writable for MbGroupWord04Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD04 to value 0"] +impl crate::Resettable for MbGroupWord04Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word05.rs b/mcxa276-pac/src/can0/mb_group_word05.rs new file mode 100644 index 000000000..402d381b2 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word05.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD05` reader"] +pub type R = crate::R; +#[doc = "Register `WORD05` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word05::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word05::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord05Spec; +impl crate::RegisterSpec for MbGroupWord05Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word05::R`](R) reader structure"] +impl crate::Readable for MbGroupWord05Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word05::W`](W) writer structure"] +impl crate::Writable for MbGroupWord05Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD05 to value 0"] +impl crate::Resettable for MbGroupWord05Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word06.rs b/mcxa276-pac/src/can0/mb_group_word06.rs new file mode 100644 index 000000000..232588181 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word06.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD06` reader"] +pub type R = crate::R; +#[doc = "Register `WORD06` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word06::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word06::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord06Spec; +impl crate::RegisterSpec for MbGroupWord06Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word06::R`](R) reader structure"] +impl crate::Readable for MbGroupWord06Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word06::W`](W) writer structure"] +impl crate::Writable for MbGroupWord06Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD06 to value 0"] +impl crate::Resettable for MbGroupWord06Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word07.rs b/mcxa276-pac/src/can0/mb_group_word07.rs new file mode 100644 index 000000000..76ad0aefa --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word07.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD07` reader"] +pub type R = crate::R; +#[doc = "Register `WORD07` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word07::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word07::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord07Spec; +impl crate::RegisterSpec for MbGroupWord07Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word07::R`](R) reader structure"] +impl crate::Readable for MbGroupWord07Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word07::W`](W) writer structure"] +impl crate::Writable for MbGroupWord07Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD07 to value 0"] +impl crate::Resettable for MbGroupWord07Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word08.rs b/mcxa276-pac/src/can0/mb_group_word08.rs new file mode 100644 index 000000000..339da890d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word08.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD08` reader"] +pub type R = crate::R; +#[doc = "Register `WORD08` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word08::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word08::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord08Spec; +impl crate::RegisterSpec for MbGroupWord08Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word08::R`](R) reader structure"] +impl crate::Readable for MbGroupWord08Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word08::W`](W) writer structure"] +impl crate::Writable for MbGroupWord08Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD08 to value 0"] +impl crate::Resettable for MbGroupWord08Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word09.rs b/mcxa276-pac/src/can0/mb_group_word09.rs new file mode 100644 index 000000000..789d72676 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word09.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD09` reader"] +pub type R = crate::R; +#[doc = "Register `WORD09` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word09::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word09::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord09Spec; +impl crate::RegisterSpec for MbGroupWord09Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word09::R`](R) reader structure"] +impl crate::Readable for MbGroupWord09Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word09::W`](W) writer structure"] +impl crate::Writable for MbGroupWord09Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD09 to value 0"] +impl crate::Resettable for MbGroupWord09Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word10.rs b/mcxa276-pac/src/can0/mb_group_word10.rs new file mode 100644 index 000000000..e02ef24da --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word10.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD10` reader"] +pub type R = crate::R; +#[doc = "Register `WORD10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 0 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord10Spec; +impl crate::RegisterSpec for MbGroupWord10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word10::R`](R) reader structure"] +impl crate::Readable for MbGroupWord10Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word10::W`](W) writer structure"] +impl crate::Writable for MbGroupWord10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD10 to value 0"] +impl crate::Resettable for MbGroupWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word11.rs b/mcxa276-pac/src/can0/mb_group_word11.rs new file mode 100644 index 000000000..27eec95aa --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word11.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD11` reader"] +pub type R = crate::R; +#[doc = "Register `WORD11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 1 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord11Spec; +impl crate::RegisterSpec for MbGroupWord11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word11::R`](R) reader structure"] +impl crate::Readable for MbGroupWord11Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word11::W`](W) writer structure"] +impl crate::Writable for MbGroupWord11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD11 to value 0"] +impl crate::Resettable for MbGroupWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word110.rs b/mcxa276-pac/src/can0/mb_group_word110.rs new file mode 100644 index 000000000..4d5d3ccf6 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word110.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD110` reader"] +pub type R = crate::R; +#[doc = "Register `WORD110` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 10 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word110::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word110::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord110Spec; +impl crate::RegisterSpec for MbGroupWord110Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word110::R`](R) reader structure"] +impl crate::Readable for MbGroupWord110Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word110::W`](W) writer structure"] +impl crate::Writable for MbGroupWord110Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD110 to value 0"] +impl crate::Resettable for MbGroupWord110Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word111.rs b/mcxa276-pac/src/can0/mb_group_word111.rs new file mode 100644 index 000000000..ae0b3cf5b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word111.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD111` reader"] +pub type R = crate::R; +#[doc = "Register `WORD111` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 11 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word111::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word111::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord111Spec; +impl crate::RegisterSpec for MbGroupWord111Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word111::R`](R) reader structure"] +impl crate::Readable for MbGroupWord111Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word111::W`](W) writer structure"] +impl crate::Writable for MbGroupWord111Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD111 to value 0"] +impl crate::Resettable for MbGroupWord111Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word112.rs b/mcxa276-pac/src/can0/mb_group_word112.rs new file mode 100644 index 000000000..82fbe454c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word112.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD112` reader"] +pub type R = crate::R; +#[doc = "Register `WORD112` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 12 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word112::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word112::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord112Spec; +impl crate::RegisterSpec for MbGroupWord112Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word112::R`](R) reader structure"] +impl crate::Readable for MbGroupWord112Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word112::W`](W) writer structure"] +impl crate::Writable for MbGroupWord112Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD112 to value 0"] +impl crate::Resettable for MbGroupWord112Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word113.rs b/mcxa276-pac/src/can0/mb_group_word113.rs new file mode 100644 index 000000000..1b6f0100d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word113.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD113` reader"] +pub type R = crate::R; +#[doc = "Register `WORD113` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 13 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word113::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word113::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord113Spec; +impl crate::RegisterSpec for MbGroupWord113Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word113::R`](R) reader structure"] +impl crate::Readable for MbGroupWord113Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word113::W`](W) writer structure"] +impl crate::Writable for MbGroupWord113Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD113 to value 0"] +impl crate::Resettable for MbGroupWord113Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word114.rs b/mcxa276-pac/src/can0/mb_group_word114.rs new file mode 100644 index 000000000..948f94239 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word114.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD114` reader"] +pub type R = crate::R; +#[doc = "Register `WORD114` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 14 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word114::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word114::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord114Spec; +impl crate::RegisterSpec for MbGroupWord114Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word114::R`](R) reader structure"] +impl crate::Readable for MbGroupWord114Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word114::W`](W) writer structure"] +impl crate::Writable for MbGroupWord114Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD114 to value 0"] +impl crate::Resettable for MbGroupWord114Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word115.rs b/mcxa276-pac/src/can0/mb_group_word115.rs new file mode 100644 index 000000000..e46fb8c0d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word115.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD115` reader"] +pub type R = crate::R; +#[doc = "Register `WORD115` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 15 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word115::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word115::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord115Spec; +impl crate::RegisterSpec for MbGroupWord115Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word115::R`](R) reader structure"] +impl crate::Readable for MbGroupWord115Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word115::W`](W) writer structure"] +impl crate::Writable for MbGroupWord115Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD115 to value 0"] +impl crate::Resettable for MbGroupWord115Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word116.rs b/mcxa276-pac/src/can0/mb_group_word116.rs new file mode 100644 index 000000000..30168273c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word116.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD116` reader"] +pub type R = crate::R; +#[doc = "Register `WORD116` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 16 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word116::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word116::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord116Spec; +impl crate::RegisterSpec for MbGroupWord116Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word116::R`](R) reader structure"] +impl crate::Readable for MbGroupWord116Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word116::W`](W) writer structure"] +impl crate::Writable for MbGroupWord116Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD116 to value 0"] +impl crate::Resettable for MbGroupWord116Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word117.rs b/mcxa276-pac/src/can0/mb_group_word117.rs new file mode 100644 index 000000000..7ee2bc3c7 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word117.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD117` reader"] +pub type R = crate::R; +#[doc = "Register `WORD117` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 17 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word117::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word117::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord117Spec; +impl crate::RegisterSpec for MbGroupWord117Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word117::R`](R) reader structure"] +impl crate::Readable for MbGroupWord117Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word117::W`](W) writer structure"] +impl crate::Writable for MbGroupWord117Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD117 to value 0"] +impl crate::Resettable for MbGroupWord117Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word118.rs b/mcxa276-pac/src/can0/mb_group_word118.rs new file mode 100644 index 000000000..07b5be19e --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word118.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD118` reader"] +pub type R = crate::R; +#[doc = "Register `WORD118` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 18 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word118::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word118::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord118Spec; +impl crate::RegisterSpec for MbGroupWord118Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word118::R`](R) reader structure"] +impl crate::Readable for MbGroupWord118Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word118::W`](W) writer structure"] +impl crate::Writable for MbGroupWord118Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD118 to value 0"] +impl crate::Resettable for MbGroupWord118Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word119.rs b/mcxa276-pac/src/can0/mb_group_word119.rs new file mode 100644 index 000000000..8147c69f1 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word119.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD119` reader"] +pub type R = crate::R; +#[doc = "Register `WORD119` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 19 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word119::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word119::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord119Spec; +impl crate::RegisterSpec for MbGroupWord119Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word119::R`](R) reader structure"] +impl crate::Readable for MbGroupWord119Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word119::W`](W) writer structure"] +impl crate::Writable for MbGroupWord119Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD119 to value 0"] +impl crate::Resettable for MbGroupWord119Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word12.rs b/mcxa276-pac/src/can0/mb_group_word12.rs new file mode 100644 index 000000000..22cc7177c --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word12.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD12` reader"] +pub type R = crate::R; +#[doc = "Register `WORD12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 2 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord12Spec; +impl crate::RegisterSpec for MbGroupWord12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word12::R`](R) reader structure"] +impl crate::Readable for MbGroupWord12Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word12::W`](W) writer structure"] +impl crate::Writable for MbGroupWord12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD12 to value 0"] +impl crate::Resettable for MbGroupWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word120.rs b/mcxa276-pac/src/can0/mb_group_word120.rs new file mode 100644 index 000000000..2d8093796 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word120.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD120` reader"] +pub type R = crate::R; +#[doc = "Register `WORD120` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 20 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word120::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word120::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord120Spec; +impl crate::RegisterSpec for MbGroupWord120Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word120::R`](R) reader structure"] +impl crate::Readable for MbGroupWord120Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word120::W`](W) writer structure"] +impl crate::Writable for MbGroupWord120Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD120 to value 0"] +impl crate::Resettable for MbGroupWord120Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word121.rs b/mcxa276-pac/src/can0/mb_group_word121.rs new file mode 100644 index 000000000..80914c0db --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word121.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD121` reader"] +pub type R = crate::R; +#[doc = "Register `WORD121` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 21 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word121::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word121::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord121Spec; +impl crate::RegisterSpec for MbGroupWord121Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word121::R`](R) reader structure"] +impl crate::Readable for MbGroupWord121Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word121::W`](W) writer structure"] +impl crate::Writable for MbGroupWord121Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD121 to value 0"] +impl crate::Resettable for MbGroupWord121Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word122.rs b/mcxa276-pac/src/can0/mb_group_word122.rs new file mode 100644 index 000000000..fc3f4676d --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word122.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD122` reader"] +pub type R = crate::R; +#[doc = "Register `WORD122` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 22 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word122::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word122::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord122Spec; +impl crate::RegisterSpec for MbGroupWord122Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word122::R`](R) reader structure"] +impl crate::Readable for MbGroupWord122Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word122::W`](W) writer structure"] +impl crate::Writable for MbGroupWord122Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD122 to value 0"] +impl crate::Resettable for MbGroupWord122Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word123.rs b/mcxa276-pac/src/can0/mb_group_word123.rs new file mode 100644 index 000000000..992311d65 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word123.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD123` reader"] +pub type R = crate::R; +#[doc = "Register `WORD123` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 23 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word123::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word123::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord123Spec; +impl crate::RegisterSpec for MbGroupWord123Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word123::R`](R) reader structure"] +impl crate::Readable for MbGroupWord123Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word123::W`](W) writer structure"] +impl crate::Writable for MbGroupWord123Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD123 to value 0"] +impl crate::Resettable for MbGroupWord123Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word124.rs b/mcxa276-pac/src/can0/mb_group_word124.rs new file mode 100644 index 000000000..cbd8a2b01 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word124.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD124` reader"] +pub type R = crate::R; +#[doc = "Register `WORD124` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 24 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word124::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word124::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord124Spec; +impl crate::RegisterSpec for MbGroupWord124Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word124::R`](R) reader structure"] +impl crate::Readable for MbGroupWord124Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word124::W`](W) writer structure"] +impl crate::Writable for MbGroupWord124Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD124 to value 0"] +impl crate::Resettable for MbGroupWord124Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word125.rs b/mcxa276-pac/src/can0/mb_group_word125.rs new file mode 100644 index 000000000..df56a3b91 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word125.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD125` reader"] +pub type R = crate::R; +#[doc = "Register `WORD125` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 25 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word125::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word125::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord125Spec; +impl crate::RegisterSpec for MbGroupWord125Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word125::R`](R) reader structure"] +impl crate::Readable for MbGroupWord125Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word125::W`](W) writer structure"] +impl crate::Writable for MbGroupWord125Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD125 to value 0"] +impl crate::Resettable for MbGroupWord125Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word126.rs b/mcxa276-pac/src/can0/mb_group_word126.rs new file mode 100644 index 000000000..df72b768f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word126.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD126` reader"] +pub type R = crate::R; +#[doc = "Register `WORD126` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 26 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word126::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word126::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord126Spec; +impl crate::RegisterSpec for MbGroupWord126Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word126::R`](R) reader structure"] +impl crate::Readable for MbGroupWord126Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word126::W`](W) writer structure"] +impl crate::Writable for MbGroupWord126Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD126 to value 0"] +impl crate::Resettable for MbGroupWord126Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word127.rs b/mcxa276-pac/src/can0/mb_group_word127.rs new file mode 100644 index 000000000..60dc29d96 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word127.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD127` reader"] +pub type R = crate::R; +#[doc = "Register `WORD127` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 27 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word127::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word127::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord127Spec; +impl crate::RegisterSpec for MbGroupWord127Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word127::R`](R) reader structure"] +impl crate::Readable for MbGroupWord127Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word127::W`](W) writer structure"] +impl crate::Writable for MbGroupWord127Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD127 to value 0"] +impl crate::Resettable for MbGroupWord127Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word128.rs b/mcxa276-pac/src/can0/mb_group_word128.rs new file mode 100644 index 000000000..6225aeacf --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word128.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD128` reader"] +pub type R = crate::R; +#[doc = "Register `WORD128` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 28 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word128::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word128::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord128Spec; +impl crate::RegisterSpec for MbGroupWord128Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word128::R`](R) reader structure"] +impl crate::Readable for MbGroupWord128Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word128::W`](W) writer structure"] +impl crate::Writable for MbGroupWord128Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD128 to value 0"] +impl crate::Resettable for MbGroupWord128Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word129.rs b/mcxa276-pac/src/can0/mb_group_word129.rs new file mode 100644 index 000000000..40a5dac5b --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word129.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD129` reader"] +pub type R = crate::R; +#[doc = "Register `WORD129` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 29 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word129::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word129::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord129Spec; +impl crate::RegisterSpec for MbGroupWord129Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word129::R`](R) reader structure"] +impl crate::Readable for MbGroupWord129Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word129::W`](W) writer structure"] +impl crate::Writable for MbGroupWord129Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD129 to value 0"] +impl crate::Resettable for MbGroupWord129Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word13.rs b/mcxa276-pac/src/can0/mb_group_word13.rs new file mode 100644 index 000000000..f326e476f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word13.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD13` reader"] +pub type R = crate::R; +#[doc = "Register `WORD13` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 3 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord13Spec; +impl crate::RegisterSpec for MbGroupWord13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word13::R`](R) reader structure"] +impl crate::Readable for MbGroupWord13Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word13::W`](W) writer structure"] +impl crate::Writable for MbGroupWord13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD13 to value 0"] +impl crate::Resettable for MbGroupWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word130.rs b/mcxa276-pac/src/can0/mb_group_word130.rs new file mode 100644 index 000000000..75ca1b4e8 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word130.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD130` reader"] +pub type R = crate::R; +#[doc = "Register `WORD130` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 30 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word130::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word130::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord130Spec; +impl crate::RegisterSpec for MbGroupWord130Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word130::R`](R) reader structure"] +impl crate::Readable for MbGroupWord130Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word130::W`](W) writer structure"] +impl crate::Writable for MbGroupWord130Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD130 to value 0"] +impl crate::Resettable for MbGroupWord130Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word131.rs b/mcxa276-pac/src/can0/mb_group_word131.rs new file mode 100644 index 000000000..f164b5517 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word131.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD131` reader"] +pub type R = crate::R; +#[doc = "Register `WORD131` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 31 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word131::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word131::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord131Spec; +impl crate::RegisterSpec for MbGroupWord131Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word131::R`](R) reader structure"] +impl crate::Readable for MbGroupWord131Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word131::W`](W) writer structure"] +impl crate::Writable for MbGroupWord131Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD131 to value 0"] +impl crate::Resettable for MbGroupWord131Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word14.rs b/mcxa276-pac/src/can0/mb_group_word14.rs new file mode 100644 index 000000000..dc26547f5 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word14.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD14` reader"] +pub type R = crate::R; +#[doc = "Register `WORD14` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 4 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord14Spec; +impl crate::RegisterSpec for MbGroupWord14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word14::R`](R) reader structure"] +impl crate::Readable for MbGroupWord14Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word14::W`](W) writer structure"] +impl crate::Writable for MbGroupWord14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD14 to value 0"] +impl crate::Resettable for MbGroupWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word15.rs b/mcxa276-pac/src/can0/mb_group_word15.rs new file mode 100644 index 000000000..03bfed5f4 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word15.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD15` reader"] +pub type R = crate::R; +#[doc = "Register `WORD15` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 5 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord15Spec; +impl crate::RegisterSpec for MbGroupWord15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word15::R`](R) reader structure"] +impl crate::Readable for MbGroupWord15Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word15::W`](W) writer structure"] +impl crate::Writable for MbGroupWord15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD15 to value 0"] +impl crate::Resettable for MbGroupWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word16.rs b/mcxa276-pac/src/can0/mb_group_word16.rs new file mode 100644 index 000000000..aa217c012 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word16.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD16` reader"] +pub type R = crate::R; +#[doc = "Register `WORD16` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 6 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord16Spec; +impl crate::RegisterSpec for MbGroupWord16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word16::R`](R) reader structure"] +impl crate::Readable for MbGroupWord16Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word16::W`](W) writer structure"] +impl crate::Writable for MbGroupWord16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD16 to value 0"] +impl crate::Resettable for MbGroupWord16Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word17.rs b/mcxa276-pac/src/can0/mb_group_word17.rs new file mode 100644 index 000000000..379218a35 --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word17.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD17` reader"] +pub type R = crate::R; +#[doc = "Register `WORD17` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 7 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord17Spec; +impl crate::RegisterSpec for MbGroupWord17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word17::R`](R) reader structure"] +impl crate::Readable for MbGroupWord17Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word17::W`](W) writer structure"] +impl crate::Writable for MbGroupWord17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD17 to value 0"] +impl crate::Resettable for MbGroupWord17Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word18.rs b/mcxa276-pac/src/can0/mb_group_word18.rs new file mode 100644 index 000000000..4149ab04f --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word18.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD18` reader"] +pub type R = crate::R; +#[doc = "Register `WORD18` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 8 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord18Spec; +impl crate::RegisterSpec for MbGroupWord18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word18::R`](R) reader structure"] +impl crate::Readable for MbGroupWord18Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word18::W`](W) writer structure"] +impl crate::Writable for MbGroupWord18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD18 to value 0"] +impl crate::Resettable for MbGroupWord18Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word19.rs b/mcxa276-pac/src/can0/mb_group_word19.rs new file mode 100644 index 000000000..dd0e33cde --- /dev/null +++ b/mcxa276-pac/src/can0/mb_group_word19.rs @@ -0,0 +1,77 @@ +#[doc = "Register `WORD19` reader"] +pub type R = crate::R; +#[doc = "Register `WORD19` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Message Buffer 9 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MbGroupWord19Spec; +impl crate::RegisterSpec for MbGroupWord19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_group_word19::R`](R) reader structure"] +impl crate::Readable for MbGroupWord19Spec {} +#[doc = "`write(|w| ..)` method takes [`mb_group_word19::W`](W) writer structure"] +impl crate::Writable for MbGroupWord19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORD19 to value 0"] +impl crate::Resettable for MbGroupWord19Spec {} diff --git a/mcxa276-pac/src/can0/mcr.rs b/mcxa276-pac/src/can0/mcr.rs new file mode 100644 index 000000000..75bac1515 --- /dev/null +++ b/mcxa276-pac/src/can0/mcr.rs @@ -0,0 +1,1390 @@ +#[doc = "Register `MCR` reader"] +pub type R = crate::R; +#[doc = "Register `MCR` writer"] +pub type W = crate::W; +#[doc = "Field `MAXMB` reader - Number of the Last Message Buffer"] +pub type MaxmbR = crate::FieldReader; +#[doc = "Field `MAXMB` writer - Number of the Last Message Buffer"] +pub type MaxmbW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "ID Acceptance Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Idam { + #[doc = "0: Format A: One full ID (standard and extended) per ID filter table element."] + OneFullId = 0, + #[doc = "1: Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element."] + TwoFullId = 1, + #[doc = "2: Format C: Four partial 8-bit standard IDs per ID filter table element."] + FourPartialId = 2, + #[doc = "3: Format D: All frames rejected."] + AllFramesRejected = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Idam) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Idam { + type Ux = u8; +} +impl crate::IsEnum for Idam {} +#[doc = "Field `IDAM` reader - ID Acceptance Mode"] +pub type IdamR = crate::FieldReader; +impl IdamR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Idam { + match self.bits { + 0 => Idam::OneFullId, + 1 => Idam::TwoFullId, + 2 => Idam::FourPartialId, + 3 => Idam::AllFramesRejected, + _ => unreachable!(), + } + } + #[doc = "Format A: One full ID (standard and extended) per ID filter table element."] + #[inline(always)] + pub fn is_one_full_id(&self) -> bool { + *self == Idam::OneFullId + } + #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element."] + #[inline(always)] + pub fn is_two_full_id(&self) -> bool { + *self == Idam::TwoFullId + } + #[doc = "Format C: Four partial 8-bit standard IDs per ID filter table element."] + #[inline(always)] + pub fn is_four_partial_id(&self) -> bool { + *self == Idam::FourPartialId + } + #[doc = "Format D: All frames rejected."] + #[inline(always)] + pub fn is_all_frames_rejected(&self) -> bool { + *self == Idam::AllFramesRejected + } +} +#[doc = "Field `IDAM` writer - ID Acceptance Mode"] +pub type IdamW<'a, REG> = crate::FieldWriter<'a, REG, 2, Idam, crate::Safe>; +impl<'a, REG> IdamW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Format A: One full ID (standard and extended) per ID filter table element."] + #[inline(always)] + pub fn one_full_id(self) -> &'a mut crate::W { + self.variant(Idam::OneFullId) + } + #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element."] + #[inline(always)] + pub fn two_full_id(self) -> &'a mut crate::W { + self.variant(Idam::TwoFullId) + } + #[doc = "Format C: Four partial 8-bit standard IDs per ID filter table element."] + #[inline(always)] + pub fn four_partial_id(self) -> &'a mut crate::W { + self.variant(Idam::FourPartialId) + } + #[doc = "Format D: All frames rejected."] + #[inline(always)] + pub fn all_frames_rejected(self) -> &'a mut crate::W { + self.variant(Idam::AllFramesRejected) + } +} +#[doc = "CAN FD Operation Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fden { + #[doc = "0: Disable"] + CanFdDisabled = 0, + #[doc = "1: Enable"] + CanFdEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fden) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FDEN` reader - CAN FD Operation Enable"] +pub type FdenR = crate::BitReader; +impl FdenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fden { + match self.bits { + false => Fden::CanFdDisabled, + true => Fden::CanFdEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_can_fd_disabled(&self) -> bool { + *self == Fden::CanFdDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_can_fd_enabled(&self) -> bool { + *self == Fden::CanFdEnabled + } +} +#[doc = "Field `FDEN` writer - CAN FD Operation Enable"] +pub type FdenW<'a, REG> = crate::BitWriter<'a, REG, Fden>; +impl<'a, REG> FdenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn can_fd_disabled(self) -> &'a mut crate::W { + self.variant(Fden::CanFdDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn can_fd_enabled(self) -> &'a mut crate::W { + self.variant(Fden::CanFdEnabled) + } +} +#[doc = "Abort Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aen { + #[doc = "0: Disabled"] + AbortDisabled = 0, + #[doc = "1: Enabled"] + AbortEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AEN` reader - Abort Enable"] +pub type AenR = crate::BitReader; +impl AenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aen { + match self.bits { + false => Aen::AbortDisabled, + true => Aen::AbortEnabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_abort_disabled(&self) -> bool { + *self == Aen::AbortDisabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_abort_enabled(&self) -> bool { + *self == Aen::AbortEnabled + } +} +#[doc = "Field `AEN` writer - Abort Enable"] +pub type AenW<'a, REG> = crate::BitWriter<'a, REG, Aen>; +impl<'a, REG> AenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn abort_disabled(self) -> &'a mut crate::W { + self.variant(Aen::AbortDisabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn abort_enabled(self) -> &'a mut crate::W { + self.variant(Aen::AbortEnabled) + } +} +#[doc = "Local Priority Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lprioen { + #[doc = "0: Disable"] + LocalPriorityDisabled = 0, + #[doc = "1: Enable"] + LocalPriorityEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lprioen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPRIOEN` reader - Local Priority Enable"] +pub type LprioenR = crate::BitReader; +impl LprioenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lprioen { + match self.bits { + false => Lprioen::LocalPriorityDisabled, + true => Lprioen::LocalPriorityEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_local_priority_disabled(&self) -> bool { + *self == Lprioen::LocalPriorityDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_local_priority_enabled(&self) -> bool { + *self == Lprioen::LocalPriorityEnabled + } +} +#[doc = "Field `LPRIOEN` writer - Local Priority Enable"] +pub type LprioenW<'a, REG> = crate::BitWriter<'a, REG, Lprioen>; +impl<'a, REG> LprioenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn local_priority_disabled(self) -> &'a mut crate::W { + self.variant(Lprioen::LocalPriorityDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn local_priority_enabled(self) -> &'a mut crate::W { + self.variant(Lprioen::LocalPriorityEnabled) + } +} +#[doc = "Pretended Networking Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PnetEn { + #[doc = "0: Disable"] + PnDisabled = 0, + #[doc = "1: Enable"] + PnEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PnetEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PNET_EN` reader - Pretended Networking Enable"] +pub type PnetEnR = crate::BitReader; +impl PnetEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PnetEn { + match self.bits { + false => PnetEn::PnDisabled, + true => PnetEn::PnEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_pn_disabled(&self) -> bool { + *self == PnetEn::PnDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_pn_enabled(&self) -> bool { + *self == PnetEn::PnEnabled + } +} +#[doc = "Field `PNET_EN` writer - Pretended Networking Enable"] +pub type PnetEnW<'a, REG> = crate::BitWriter<'a, REG, PnetEn>; +impl<'a, REG> PnetEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn pn_disabled(self) -> &'a mut crate::W { + self.variant(PnetEn::PnDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn pn_enabled(self) -> &'a mut crate::W { + self.variant(PnetEn::PnEnabled) + } +} +#[doc = "DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dma { + #[doc = "0: Disable"] + Id1 = 0, + #[doc = "1: Enable"] + Id2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dma) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA` reader - DMA Enable"] +pub type DmaR = crate::BitReader; +impl DmaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dma { + match self.bits { + false => Dma::Id1, + true => Dma::Id2, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Dma::Id1 + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_id2(&self) -> bool { + *self == Dma::Id2 + } +} +#[doc = "Field `DMA` writer - DMA Enable"] +pub type DmaW<'a, REG> = crate::BitWriter<'a, REG, Dma>; +impl<'a, REG> DmaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn id1(self) -> &'a mut crate::W { + self.variant(Dma::Id1) + } + #[doc = "Enable"] + #[inline(always)] + pub fn id2(self) -> &'a mut crate::W { + self.variant(Dma::Id2) + } +} +#[doc = "Individual RX Masking and Queue Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Irmq { + #[doc = "0: Disable"] + IndividualRxMaskingDisabled = 0, + #[doc = "1: Enable"] + IndividualRxMaskingEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Irmq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IRMQ` reader - Individual RX Masking and Queue Enable"] +pub type IrmqR = crate::BitReader; +impl IrmqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Irmq { + match self.bits { + false => Irmq::IndividualRxMaskingDisabled, + true => Irmq::IndividualRxMaskingEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_individual_rx_masking_disabled(&self) -> bool { + *self == Irmq::IndividualRxMaskingDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_individual_rx_masking_enabled(&self) -> bool { + *self == Irmq::IndividualRxMaskingEnabled + } +} +#[doc = "Field `IRMQ` writer - Individual RX Masking and Queue Enable"] +pub type IrmqW<'a, REG> = crate::BitWriter<'a, REG, Irmq>; +impl<'a, REG> IrmqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn individual_rx_masking_disabled(self) -> &'a mut crate::W { + self.variant(Irmq::IndividualRxMaskingDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn individual_rx_masking_enabled(self) -> &'a mut crate::W { + self.variant(Irmq::IndividualRxMaskingEnabled) + } +} +#[doc = "Self-Reception Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Srxdis { + #[doc = "0: Enable"] + SelfReceptionEnabled = 0, + #[doc = "1: Disable"] + SelfReceptionDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Srxdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRXDIS` reader - Self-Reception Disable"] +pub type SrxdisR = crate::BitReader; +impl SrxdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Srxdis { + match self.bits { + false => Srxdis::SelfReceptionEnabled, + true => Srxdis::SelfReceptionDisabled, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_self_reception_enabled(&self) -> bool { + *self == Srxdis::SelfReceptionEnabled + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_self_reception_disabled(&self) -> bool { + *self == Srxdis::SelfReceptionDisabled + } +} +#[doc = "Field `SRXDIS` writer - Self-Reception Disable"] +pub type SrxdisW<'a, REG> = crate::BitWriter<'a, REG, Srxdis>; +impl<'a, REG> SrxdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn self_reception_enabled(self) -> &'a mut crate::W { + self.variant(Srxdis::SelfReceptionEnabled) + } + #[doc = "Disable"] + #[inline(always)] + pub fn self_reception_disabled(self) -> &'a mut crate::W { + self.variant(Srxdis::SelfReceptionDisabled) + } +} +#[doc = "Doze Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Doze { + #[doc = "0: Disable"] + LowPowerDozeDisabled = 0, + #[doc = "1: Enable"] + LowPowerDozeEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Doze) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DOZE` reader - Doze Mode Enable"] +pub type DozeR = crate::BitReader; +impl DozeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Doze { + match self.bits { + false => Doze::LowPowerDozeDisabled, + true => Doze::LowPowerDozeEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_low_power_doze_disabled(&self) -> bool { + *self == Doze::LowPowerDozeDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_low_power_doze_enabled(&self) -> bool { + *self == Doze::LowPowerDozeEnabled + } +} +#[doc = "Field `DOZE` writer - Doze Mode Enable"] +pub type DozeW<'a, REG> = crate::BitWriter<'a, REG, Doze>; +impl<'a, REG> DozeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn low_power_doze_disabled(self) -> &'a mut crate::W { + self.variant(Doze::LowPowerDozeDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn low_power_doze_enabled(self) -> &'a mut crate::W { + self.variant(Doze::LowPowerDozeEnabled) + } +} +#[doc = "Wake-Up Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Waksrc { + #[doc = "0: No filter applied"] + UnfilteredRxInput = 0, + #[doc = "1: Filter applied"] + FilteredRxInput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Waksrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKSRC` reader - Wake-Up Source"] +pub type WaksrcR = crate::BitReader; +impl WaksrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Waksrc { + match self.bits { + false => Waksrc::UnfilteredRxInput, + true => Waksrc::FilteredRxInput, + } + } + #[doc = "No filter applied"] + #[inline(always)] + pub fn is_unfiltered_rx_input(&self) -> bool { + *self == Waksrc::UnfilteredRxInput + } + #[doc = "Filter applied"] + #[inline(always)] + pub fn is_filtered_rx_input(&self) -> bool { + *self == Waksrc::FilteredRxInput + } +} +#[doc = "Field `WAKSRC` writer - Wake-Up Source"] +pub type WaksrcW<'a, REG> = crate::BitWriter<'a, REG, Waksrc>; +impl<'a, REG> WaksrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No filter applied"] + #[inline(always)] + pub fn unfiltered_rx_input(self) -> &'a mut crate::W { + self.variant(Waksrc::UnfilteredRxInput) + } + #[doc = "Filter applied"] + #[inline(always)] + pub fn filtered_rx_input(self) -> &'a mut crate::W { + self.variant(Waksrc::FilteredRxInput) + } +} +#[doc = "Low-Power Mode Acknowledge\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpmack { + #[doc = "0: Not in a low-power mode"] + LowPowerNo = 0, + #[doc = "1: In a low-power mode"] + LowPowerYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpmack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPMACK` reader - Low-Power Mode Acknowledge"] +pub type LpmackR = crate::BitReader; +impl LpmackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpmack { + match self.bits { + false => Lpmack::LowPowerNo, + true => Lpmack::LowPowerYes, + } + } + #[doc = "Not in a low-power mode"] + #[inline(always)] + pub fn is_low_power_no(&self) -> bool { + *self == Lpmack::LowPowerNo + } + #[doc = "In a low-power mode"] + #[inline(always)] + pub fn is_low_power_yes(&self) -> bool { + *self == Lpmack::LowPowerYes + } +} +#[doc = "Warning Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wrnen { + #[doc = "0: Disable"] + TwrnintRwrnintInactive = 0, + #[doc = "1: Enable"] + TwrnintRwrnintActive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wrnen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WRNEN` reader - Warning Interrupt Enable"] +pub type WrnenR = crate::BitReader; +impl WrnenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wrnen { + match self.bits { + false => Wrnen::TwrnintRwrnintInactive, + true => Wrnen::TwrnintRwrnintActive, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_twrnint_rwrnint_inactive(&self) -> bool { + *self == Wrnen::TwrnintRwrnintInactive + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_twrnint_rwrnint_active(&self) -> bool { + *self == Wrnen::TwrnintRwrnintActive + } +} +#[doc = "Field `WRNEN` writer - Warning Interrupt Enable"] +pub type WrnenW<'a, REG> = crate::BitWriter<'a, REG, Wrnen>; +impl<'a, REG> WrnenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn twrnint_rwrnint_inactive(self) -> &'a mut crate::W { + self.variant(Wrnen::TwrnintRwrnintInactive) + } + #[doc = "Enable"] + #[inline(always)] + pub fn twrnint_rwrnint_active(self) -> &'a mut crate::W { + self.variant(Wrnen::TwrnintRwrnintActive) + } +} +#[doc = "Self Wake-up\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slfwak { + #[doc = "0: Disable"] + SelfWakeupDisabled = 0, + #[doc = "1: Enable"] + SelfWakeupEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slfwak) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLFWAK` reader - Self Wake-up"] +pub type SlfwakR = crate::BitReader; +impl SlfwakR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slfwak { + match self.bits { + false => Slfwak::SelfWakeupDisabled, + true => Slfwak::SelfWakeupEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_self_wakeup_disabled(&self) -> bool { + *self == Slfwak::SelfWakeupDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_self_wakeup_enabled(&self) -> bool { + *self == Slfwak::SelfWakeupEnabled + } +} +#[doc = "Field `SLFWAK` writer - Self Wake-up"] +pub type SlfwakW<'a, REG> = crate::BitWriter<'a, REG, Slfwak>; +impl<'a, REG> SlfwakW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn self_wakeup_disabled(self) -> &'a mut crate::W { + self.variant(Slfwak::SelfWakeupDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn self_wakeup_enabled(self) -> &'a mut crate::W { + self.variant(Slfwak::SelfWakeupEnabled) + } +} +#[doc = "Supervisor Mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Supv { + #[doc = "0: User mode"] + Id1 = 0, + #[doc = "1: Supervisor mode"] + Id2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Supv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUPV` reader - Supervisor Mode"] +pub type SupvR = crate::BitReader; +impl SupvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Supv { + match self.bits { + false => Supv::Id1, + true => Supv::Id2, + } + } + #[doc = "User mode"] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Supv::Id1 + } + #[doc = "Supervisor mode"] + #[inline(always)] + pub fn is_id2(&self) -> bool { + *self == Supv::Id2 + } +} +#[doc = "Field `SUPV` writer - Supervisor Mode"] +pub type SupvW<'a, REG> = crate::BitWriter<'a, REG, Supv>; +impl<'a, REG> SupvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "User mode"] + #[inline(always)] + pub fn id1(self) -> &'a mut crate::W { + self.variant(Supv::Id1) + } + #[doc = "Supervisor mode"] + #[inline(always)] + pub fn id2(self) -> &'a mut crate::W { + self.variant(Supv::Id2) + } +} +#[doc = "Freeze Mode Acknowledge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frzack { + #[doc = "0: Not in Freeze mode, prescaler running."] + FreezeModeNo = 0, + #[doc = "1: In Freeze mode, prescaler stopped."] + FreezeModeYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frzack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRZACK` reader - Freeze Mode Acknowledge"] +pub type FrzackR = crate::BitReader; +impl FrzackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frzack { + match self.bits { + false => Frzack::FreezeModeNo, + true => Frzack::FreezeModeYes, + } + } + #[doc = "Not in Freeze mode, prescaler running."] + #[inline(always)] + pub fn is_freeze_mode_no(&self) -> bool { + *self == Frzack::FreezeModeNo + } + #[doc = "In Freeze mode, prescaler stopped."] + #[inline(always)] + pub fn is_freeze_mode_yes(&self) -> bool { + *self == Frzack::FreezeModeYes + } +} +#[doc = "Soft Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Softrst { + #[doc = "0: No reset"] + SoftrstNoResetRequest = 0, + #[doc = "1: Soft reset affects reset registers"] + SoftrstResetRegisters = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Softrst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOFTRST` reader - Soft Reset"] +pub type SoftrstR = crate::BitReader; +impl SoftrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Softrst { + match self.bits { + false => Softrst::SoftrstNoResetRequest, + true => Softrst::SoftrstResetRegisters, + } + } + #[doc = "No reset"] + #[inline(always)] + pub fn is_softrst_no_reset_request(&self) -> bool { + *self == Softrst::SoftrstNoResetRequest + } + #[doc = "Soft reset affects reset registers"] + #[inline(always)] + pub fn is_softrst_reset_registers(&self) -> bool { + *self == Softrst::SoftrstResetRegisters + } +} +#[doc = "Field `SOFTRST` writer - Soft Reset"] +pub type SoftrstW<'a, REG> = crate::BitWriter<'a, REG, Softrst>; +impl<'a, REG> SoftrstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No reset"] + #[inline(always)] + pub fn softrst_no_reset_request(self) -> &'a mut crate::W { + self.variant(Softrst::SoftrstNoResetRequest) + } + #[doc = "Soft reset affects reset registers"] + #[inline(always)] + pub fn softrst_reset_registers(self) -> &'a mut crate::W { + self.variant(Softrst::SoftrstResetRegisters) + } +} +#[doc = "Wake-up Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wakmsk { + #[doc = "0: Disabled"] + WakeupInterruptDisabled = 0, + #[doc = "1: Enabled"] + WakeupInterruptEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wakmsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKMSK` reader - Wake-up Interrupt Mask"] +pub type WakmskR = crate::BitReader; +impl WakmskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wakmsk { + match self.bits { + false => Wakmsk::WakeupInterruptDisabled, + true => Wakmsk::WakeupInterruptEnabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_wakeup_interrupt_disabled(&self) -> bool { + *self == Wakmsk::WakeupInterruptDisabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_wakeup_interrupt_enabled(&self) -> bool { + *self == Wakmsk::WakeupInterruptEnabled + } +} +#[doc = "Field `WAKMSK` writer - Wake-up Interrupt Mask"] +pub type WakmskW<'a, REG> = crate::BitWriter<'a, REG, Wakmsk>; +impl<'a, REG> WakmskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn wakeup_interrupt_disabled(self) -> &'a mut crate::W { + self.variant(Wakmsk::WakeupInterruptDisabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn wakeup_interrupt_enabled(self) -> &'a mut crate::W { + self.variant(Wakmsk::WakeupInterruptEnabled) + } +} +#[doc = "FlexCAN Not Ready\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Notrdy { + #[doc = "0: FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode."] + Id1 = 0, + #[doc = "1: FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode."] + Id2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Notrdy) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOTRDY` reader - FlexCAN Not Ready"] +pub type NotrdyR = crate::BitReader; +impl NotrdyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Notrdy { + match self.bits { + false => Notrdy::Id1, + true => Notrdy::Id2, + } + } + #[doc = "FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode."] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Notrdy::Id1 + } + #[doc = "FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode."] + #[inline(always)] + pub fn is_id2(&self) -> bool { + *self == Notrdy::Id2 + } +} +#[doc = "Halt FlexCAN\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: No request"] + HaltDisable = 0, + #[doc = "1: Enter Freeze mode, if MCR\\[FRZ\\] = 1."] + HaltEnable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt FlexCAN"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::HaltDisable, + true => Halt::HaltEnable, + } + } + #[doc = "No request"] + #[inline(always)] + pub fn is_halt_disable(&self) -> bool { + *self == Halt::HaltDisable + } + #[doc = "Enter Freeze mode, if MCR\\[FRZ\\] = 1."] + #[inline(always)] + pub fn is_halt_enable(&self) -> bool { + *self == Halt::HaltEnable + } +} +#[doc = "Field `HALT` writer - Halt FlexCAN"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No request"] + #[inline(always)] + pub fn halt_disable(self) -> &'a mut crate::W { + self.variant(Halt::HaltDisable) + } + #[doc = "Enter Freeze mode, if MCR\\[FRZ\\] = 1."] + #[inline(always)] + pub fn halt_enable(self) -> &'a mut crate::W { + self.variant(Halt::HaltEnable) + } +} +#[doc = "Legacy RX FIFO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rfen { + #[doc = "0: Disable"] + Id1 = 0, + #[doc = "1: Enable"] + Id2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rfen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RFEN` reader - Legacy RX FIFO Enable"] +pub type RfenR = crate::BitReader; +impl RfenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rfen { + match self.bits { + false => Rfen::Id1, + true => Rfen::Id2, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_id1(&self) -> bool { + *self == Rfen::Id1 + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_id2(&self) -> bool { + *self == Rfen::Id2 + } +} +#[doc = "Field `RFEN` writer - Legacy RX FIFO Enable"] +pub type RfenW<'a, REG> = crate::BitWriter<'a, REG, Rfen>; +impl<'a, REG> RfenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn id1(self) -> &'a mut crate::W { + self.variant(Rfen::Id1) + } + #[doc = "Enable"] + #[inline(always)] + pub fn id2(self) -> &'a mut crate::W { + self.variant(Rfen::Id2) + } +} +#[doc = "Freeze Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frz { + #[doc = "0: Disable"] + FreezeModeDisabled = 0, + #[doc = "1: Enable"] + FreezeModeEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frz) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRZ` reader - Freeze Enable"] +pub type FrzR = crate::BitReader; +impl FrzR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frz { + match self.bits { + false => Frz::FreezeModeDisabled, + true => Frz::FreezeModeEnabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_freeze_mode_disabled(&self) -> bool { + *self == Frz::FreezeModeDisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_freeze_mode_enabled(&self) -> bool { + *self == Frz::FreezeModeEnabled + } +} +#[doc = "Field `FRZ` writer - Freeze Enable"] +pub type FrzW<'a, REG> = crate::BitWriter<'a, REG, Frz>; +impl<'a, REG> FrzW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn freeze_mode_disabled(self) -> &'a mut crate::W { + self.variant(Frz::FreezeModeDisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn freeze_mode_enabled(self) -> &'a mut crate::W { + self.variant(Frz::FreezeModeEnabled) + } +} +#[doc = "Module Disable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mdis { + #[doc = "0: Enable"] + FlexcanEnabled = 0, + #[doc = "1: Disable"] + FlexcanDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MDIS` reader - Module Disable"] +pub type MdisR = crate::BitReader; +impl MdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mdis { + match self.bits { + false => Mdis::FlexcanEnabled, + true => Mdis::FlexcanDisabled, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_flexcan_enabled(&self) -> bool { + *self == Mdis::FlexcanEnabled + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_flexcan_disabled(&self) -> bool { + *self == Mdis::FlexcanDisabled + } +} +#[doc = "Field `MDIS` writer - Module Disable"] +pub type MdisW<'a, REG> = crate::BitWriter<'a, REG, Mdis>; +impl<'a, REG> MdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn flexcan_enabled(self) -> &'a mut crate::W { + self.variant(Mdis::FlexcanEnabled) + } + #[doc = "Disable"] + #[inline(always)] + pub fn flexcan_disabled(self) -> &'a mut crate::W { + self.variant(Mdis::FlexcanDisabled) + } +} +impl R { + #[doc = "Bits 0:6 - Number of the Last Message Buffer"] + #[inline(always)] + pub fn maxmb(&self) -> MaxmbR { + MaxmbR::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - ID Acceptance Mode"] + #[inline(always)] + pub fn idam(&self) -> IdamR { + IdamR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 11 - CAN FD Operation Enable"] + #[inline(always)] + pub fn fden(&self) -> FdenR { + FdenR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Abort Enable"] + #[inline(always)] + pub fn aen(&self) -> AenR { + AenR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Local Priority Enable"] + #[inline(always)] + pub fn lprioen(&self) -> LprioenR { + LprioenR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pretended Networking Enable"] + #[inline(always)] + pub fn pnet_en(&self) -> PnetEnR { + PnetEnR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - DMA Enable"] + #[inline(always)] + pub fn dma(&self) -> DmaR { + DmaR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Individual RX Masking and Queue Enable"] + #[inline(always)] + pub fn irmq(&self) -> IrmqR { + IrmqR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Self-Reception Disable"] + #[inline(always)] + pub fn srxdis(&self) -> SrxdisR { + SrxdisR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Doze Mode Enable"] + #[inline(always)] + pub fn doze(&self) -> DozeR { + DozeR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Wake-Up Source"] + #[inline(always)] + pub fn waksrc(&self) -> WaksrcR { + WaksrcR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Low-Power Mode Acknowledge"] + #[inline(always)] + pub fn lpmack(&self) -> LpmackR { + LpmackR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Warning Interrupt Enable"] + #[inline(always)] + pub fn wrnen(&self) -> WrnenR { + WrnenR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Self Wake-up"] + #[inline(always)] + pub fn slfwak(&self) -> SlfwakR { + SlfwakR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Supervisor Mode"] + #[inline(always)] + pub fn supv(&self) -> SupvR { + SupvR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Freeze Mode Acknowledge"] + #[inline(always)] + pub fn frzack(&self) -> FrzackR { + FrzackR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Soft Reset"] + #[inline(always)] + pub fn softrst(&self) -> SoftrstR { + SoftrstR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Wake-up Interrupt Mask"] + #[inline(always)] + pub fn wakmsk(&self) -> WakmskR { + WakmskR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - FlexCAN Not Ready"] + #[inline(always)] + pub fn notrdy(&self) -> NotrdyR { + NotrdyR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Halt FlexCAN"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Legacy RX FIFO Enable"] + #[inline(always)] + pub fn rfen(&self) -> RfenR { + RfenR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Freeze Enable"] + #[inline(always)] + pub fn frz(&self) -> FrzR { + FrzR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Module Disable"] + #[inline(always)] + pub fn mdis(&self) -> MdisR { + MdisR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Number of the Last Message Buffer"] + #[inline(always)] + pub fn maxmb(&mut self) -> MaxmbW { + MaxmbW::new(self, 0) + } + #[doc = "Bits 8:9 - ID Acceptance Mode"] + #[inline(always)] + pub fn idam(&mut self) -> IdamW { + IdamW::new(self, 8) + } + #[doc = "Bit 11 - CAN FD Operation Enable"] + #[inline(always)] + pub fn fden(&mut self) -> FdenW { + FdenW::new(self, 11) + } + #[doc = "Bit 12 - Abort Enable"] + #[inline(always)] + pub fn aen(&mut self) -> AenW { + AenW::new(self, 12) + } + #[doc = "Bit 13 - Local Priority Enable"] + #[inline(always)] + pub fn lprioen(&mut self) -> LprioenW { + LprioenW::new(self, 13) + } + #[doc = "Bit 14 - Pretended Networking Enable"] + #[inline(always)] + pub fn pnet_en(&mut self) -> PnetEnW { + PnetEnW::new(self, 14) + } + #[doc = "Bit 15 - DMA Enable"] + #[inline(always)] + pub fn dma(&mut self) -> DmaW { + DmaW::new(self, 15) + } + #[doc = "Bit 16 - Individual RX Masking and Queue Enable"] + #[inline(always)] + pub fn irmq(&mut self) -> IrmqW { + IrmqW::new(self, 16) + } + #[doc = "Bit 17 - Self-Reception Disable"] + #[inline(always)] + pub fn srxdis(&mut self) -> SrxdisW { + SrxdisW::new(self, 17) + } + #[doc = "Bit 18 - Doze Mode Enable"] + #[inline(always)] + pub fn doze(&mut self) -> DozeW { + DozeW::new(self, 18) + } + #[doc = "Bit 19 - Wake-Up Source"] + #[inline(always)] + pub fn waksrc(&mut self) -> WaksrcW { + WaksrcW::new(self, 19) + } + #[doc = "Bit 21 - Warning Interrupt Enable"] + #[inline(always)] + pub fn wrnen(&mut self) -> WrnenW { + WrnenW::new(self, 21) + } + #[doc = "Bit 22 - Self Wake-up"] + #[inline(always)] + pub fn slfwak(&mut self) -> SlfwakW { + SlfwakW::new(self, 22) + } + #[doc = "Bit 23 - Supervisor Mode"] + #[inline(always)] + pub fn supv(&mut self) -> SupvW { + SupvW::new(self, 23) + } + #[doc = "Bit 25 - Soft Reset"] + #[inline(always)] + pub fn softrst(&mut self) -> SoftrstW { + SoftrstW::new(self, 25) + } + #[doc = "Bit 26 - Wake-up Interrupt Mask"] + #[inline(always)] + pub fn wakmsk(&mut self) -> WakmskW { + WakmskW::new(self, 26) + } + #[doc = "Bit 28 - Halt FlexCAN"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 28) + } + #[doc = "Bit 29 - Legacy RX FIFO Enable"] + #[inline(always)] + pub fn rfen(&mut self) -> RfenW { + RfenW::new(self, 29) + } + #[doc = "Bit 30 - Freeze Enable"] + #[inline(always)] + pub fn frz(&mut self) -> FrzW { + FrzW::new(self, 30) + } + #[doc = "Bit 31 - Module Disable"] + #[inline(always)] + pub fn mdis(&mut self) -> MdisW { + MdisW::new(self, 31) + } +} +#[doc = "Module Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct McrSpec; +impl crate::RegisterSpec for McrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for McrSpec {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] +impl crate::Writable for McrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCR to value 0xd890_000f"] +impl crate::Resettable for McrSpec { + const RESET_VALUE: u32 = 0xd890_000f; +} diff --git a/mcxa276-pac/src/can0/pl1_hi.rs b/mcxa276-pac/src/can0/pl1_hi.rs new file mode 100644 index 000000000..0af299fc5 --- /dev/null +++ b/mcxa276-pac/src/can0/pl1_hi.rs @@ -0,0 +1,77 @@ +#[doc = "Register `PL1_HI` reader"] +pub type R = crate::R; +#[doc = "Register `PL1_HI` writer"] +pub type W = crate::W; +#[doc = "Field `Data_byte_7` reader - Data byte 7"] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `Data_byte_7` writer - Data byte 7"] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_6` reader - Data byte 6"] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `Data_byte_6` writer - Data byte 6"] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_5` reader - Data byte 5"] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `Data_byte_5` writer - Data byte 5"] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_4` reader - Data byte 4"] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `Data_byte_4` writer - Data byte 4"] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 7"] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 6"] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 5"] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 4"] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 7"] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 6"] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 5"] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 4"] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Pretended Networking Payload High Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pl1HiSpec; +impl crate::RegisterSpec for Pl1HiSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pl1_hi::R`](R) reader structure"] +impl crate::Readable for Pl1HiSpec {} +#[doc = "`write(|w| ..)` method takes [`pl1_hi::W`](W) writer structure"] +impl crate::Writable for Pl1HiSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PL1_HI to value 0"] +impl crate::Resettable for Pl1HiSpec {} diff --git a/mcxa276-pac/src/can0/pl1_lo.rs b/mcxa276-pac/src/can0/pl1_lo.rs new file mode 100644 index 000000000..63525cbb8 --- /dev/null +++ b/mcxa276-pac/src/can0/pl1_lo.rs @@ -0,0 +1,77 @@ +#[doc = "Register `PL1_LO` reader"] +pub type R = crate::R; +#[doc = "Register `PL1_LO` writer"] +pub type W = crate::W; +#[doc = "Field `Data_byte_3` reader - Data byte 3"] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `Data_byte_3` writer - Data byte 3"] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_2` reader - Data byte 2"] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `Data_byte_2` writer - Data byte 2"] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_1` reader - Data byte 1"] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `Data_byte_1` writer - Data byte 1"] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_0` reader - Data byte 0"] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `Data_byte_0` writer - Data byte 0"] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data byte 3"] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data byte 2"] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data byte 1"] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data byte 0"] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data byte 3"] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data byte 2"] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data byte 1"] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data byte 0"] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Pretended Networking Payload Low Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_lo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_lo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pl1LoSpec; +impl crate::RegisterSpec for Pl1LoSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pl1_lo::R`](R) reader structure"] +impl crate::Readable for Pl1LoSpec {} +#[doc = "`write(|w| ..)` method takes [`pl1_lo::W`](W) writer structure"] +impl crate::Writable for Pl1LoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PL1_LO to value 0"] +impl crate::Resettable for Pl1LoSpec {} diff --git a/mcxa276-pac/src/can0/pl2_plmask_hi.rs b/mcxa276-pac/src/can0/pl2_plmask_hi.rs new file mode 100644 index 000000000..ff872f444 --- /dev/null +++ b/mcxa276-pac/src/can0/pl2_plmask_hi.rs @@ -0,0 +1,77 @@ +#[doc = "Register `PL2_PLMASK_HI` reader"] +pub type R = crate::R; +#[doc = "Register `PL2_PLMASK_HI` writer"] +pub type W = crate::W; +#[doc = "Field `Data_byte_7` reader - Data Byte 7"] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `Data_byte_7` writer - Data Byte 7"] +pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_6` reader - Data Byte 6"] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `Data_byte_6` writer - Data Byte 6"] +pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_5` reader - Data Byte 5"] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `Data_byte_5` writer - Data Byte 5"] +pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_4` reader - Data Byte 4"] +pub type DataByte4R = crate::FieldReader; +#[doc = "Field `Data_byte_4` writer - Data Byte 4"] +pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 7"] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 6"] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data Byte 5"] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data Byte 4"] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 7"] + #[inline(always)] + pub fn data_byte_7(&mut self) -> DataByte7W { + DataByte7W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 6"] + #[inline(always)] + pub fn data_byte_6(&mut self) -> DataByte6W { + DataByte6W::new(self, 8) + } + #[doc = "Bits 16:23 - Data Byte 5"] + #[inline(always)] + pub fn data_byte_5(&mut self) -> DataByte5W { + DataByte5W::new(self, 16) + } + #[doc = "Bits 24:31 - Data Byte 4"] + #[inline(always)] + pub fn data_byte_4(&mut self) -> DataByte4W { + DataByte4W::new(self, 24) + } +} +#[doc = "Pretended Networking Payload High Filter 2 and Payload High Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pl2PlmaskHiSpec; +impl crate::RegisterSpec for Pl2PlmaskHiSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pl2_plmask_hi::R`](R) reader structure"] +impl crate::Readable for Pl2PlmaskHiSpec {} +#[doc = "`write(|w| ..)` method takes [`pl2_plmask_hi::W`](W) writer structure"] +impl crate::Writable for Pl2PlmaskHiSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PL2_PLMASK_HI to value 0"] +impl crate::Resettable for Pl2PlmaskHiSpec {} diff --git a/mcxa276-pac/src/can0/pl2_plmask_lo.rs b/mcxa276-pac/src/can0/pl2_plmask_lo.rs new file mode 100644 index 000000000..c1f826020 --- /dev/null +++ b/mcxa276-pac/src/can0/pl2_plmask_lo.rs @@ -0,0 +1,77 @@ +#[doc = "Register `PL2_PLMASK_LO` reader"] +pub type R = crate::R; +#[doc = "Register `PL2_PLMASK_LO` writer"] +pub type W = crate::W; +#[doc = "Field `Data_byte_3` reader - Data Byte 3"] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `Data_byte_3` writer - Data Byte 3"] +pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_2` reader - Data Byte 2"] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `Data_byte_2` writer - Data Byte 2"] +pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_1` reader - Data Byte 1"] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `Data_byte_1` writer - Data Byte 1"] +pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Data_byte_0` reader - Data Byte 0"] +pub type DataByte0R = crate::FieldReader; +#[doc = "Field `Data_byte_0` writer - Data Byte 0"] +pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 3"] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 2"] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data Byte 1"] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data Byte 0"] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 3"] + #[inline(always)] + pub fn data_byte_3(&mut self) -> DataByte3W { + DataByte3W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 2"] + #[inline(always)] + pub fn data_byte_2(&mut self) -> DataByte2W { + DataByte2W::new(self, 8) + } + #[doc = "Bits 16:23 - Data Byte 1"] + #[inline(always)] + pub fn data_byte_1(&mut self) -> DataByte1W { + DataByte1W::new(self, 16) + } + #[doc = "Bits 24:31 - Data Byte 0"] + #[inline(always)] + pub fn data_byte_0(&mut self) -> DataByte0W { + DataByte0W::new(self, 24) + } +} +#[doc = "Pretended Networking Payload Low Filter 2 and Payload Low Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_lo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_lo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pl2PlmaskLoSpec; +impl crate::RegisterSpec for Pl2PlmaskLoSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pl2_plmask_lo::R`](R) reader structure"] +impl crate::Readable for Pl2PlmaskLoSpec {} +#[doc = "`write(|w| ..)` method takes [`pl2_plmask_lo::W`](W) writer structure"] +impl crate::Writable for Pl2PlmaskLoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PL2_PLMASK_LO to value 0"] +impl crate::Resettable for Pl2PlmaskLoSpec {} diff --git a/mcxa276-pac/src/can0/rx14mask.rs b/mcxa276-pac/src/can0/rx14mask.rs new file mode 100644 index 000000000..008dde3e2 --- /dev/null +++ b/mcxa276-pac/src/can0/rx14mask.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RX14MASK` reader"] +pub type R = crate::R; +#[doc = "Register `RX14MASK` writer"] +pub type W = crate::W; +#[doc = "Field `RX14M` reader - RX Buffer 14 Mask Bits"] +pub type Rx14mR = crate::FieldReader; +#[doc = "Field `RX14M` writer - RX Buffer 14 Mask Bits"] +pub type Rx14mW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - RX Buffer 14 Mask Bits"] + #[inline(always)] + pub fn rx14m(&self) -> Rx14mR { + Rx14mR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - RX Buffer 14 Mask Bits"] + #[inline(always)] + pub fn rx14m(&mut self) -> Rx14mW { + Rx14mW::new(self, 0) + } +} +#[doc = "Receive 14 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx14mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx14mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx14maskSpec; +impl crate::RegisterSpec for Rx14maskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx14mask::R`](R) reader structure"] +impl crate::Readable for Rx14maskSpec {} +#[doc = "`write(|w| ..)` method takes [`rx14mask::W`](W) writer structure"] +impl crate::Writable for Rx14maskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RX14MASK to value 0"] +impl crate::Resettable for Rx14maskSpec {} diff --git a/mcxa276-pac/src/can0/rx15mask.rs b/mcxa276-pac/src/can0/rx15mask.rs new file mode 100644 index 000000000..3232c334c --- /dev/null +++ b/mcxa276-pac/src/can0/rx15mask.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RX15MASK` reader"] +pub type R = crate::R; +#[doc = "Register `RX15MASK` writer"] +pub type W = crate::W; +#[doc = "Field `RX15M` reader - RX Buffer 15 Mask Bits"] +pub type Rx15mR = crate::FieldReader; +#[doc = "Field `RX15M` writer - RX Buffer 15 Mask Bits"] +pub type Rx15mW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - RX Buffer 15 Mask Bits"] + #[inline(always)] + pub fn rx15m(&self) -> Rx15mR { + Rx15mR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - RX Buffer 15 Mask Bits"] + #[inline(always)] + pub fn rx15m(&mut self) -> Rx15mW { + Rx15mW::new(self, 0) + } +} +#[doc = "Receive 15 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx15mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx15mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx15maskSpec; +impl crate::RegisterSpec for Rx15maskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx15mask::R`](R) reader structure"] +impl crate::Readable for Rx15maskSpec {} +#[doc = "`write(|w| ..)` method takes [`rx15mask::W`](W) writer structure"] +impl crate::Writable for Rx15maskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RX15MASK to value 0"] +impl crate::Resettable for Rx15maskSpec {} diff --git a/mcxa276-pac/src/can0/rxfgmask.rs b/mcxa276-pac/src/can0/rxfgmask.rs new file mode 100644 index 000000000..d3fa8aa5e --- /dev/null +++ b/mcxa276-pac/src/can0/rxfgmask.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RXFGMASK` reader"] +pub type R = crate::R; +#[doc = "Register `RXFGMASK` writer"] +pub type W = crate::W; +#[doc = "Field `FGM` reader - Legacy RX FIFO Global Mask Bits"] +pub type FgmR = crate::FieldReader; +#[doc = "Field `FGM` writer - Legacy RX FIFO Global Mask Bits"] +pub type FgmW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Legacy RX FIFO Global Mask Bits"] + #[inline(always)] + pub fn fgm(&self) -> FgmR { + FgmR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Legacy RX FIFO Global Mask Bits"] + #[inline(always)] + pub fn fgm(&mut self) -> FgmW { + FgmW::new(self, 0) + } +} +#[doc = "Legacy RX FIFO Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfgmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfgmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfgmaskSpec; +impl crate::RegisterSpec for RxfgmaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfgmask::R`](R) reader structure"] +impl crate::Readable for RxfgmaskSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfgmask::W`](W) writer structure"] +impl crate::Writable for RxfgmaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFGMASK to value 0"] +impl crate::Resettable for RxfgmaskSpec {} diff --git a/mcxa276-pac/src/can0/rxfir.rs b/mcxa276-pac/src/can0/rxfir.rs new file mode 100644 index 000000000..8358bfd79 --- /dev/null +++ b/mcxa276-pac/src/can0/rxfir.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXFIR` reader"] +pub type R = crate::R; +#[doc = "Field `IDHIT` reader - Identifier Acceptance Filter Hit Indicator"] +pub type IdhitR = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - Identifier Acceptance Filter Hit Indicator"] + #[inline(always)] + pub fn idhit(&self) -> IdhitR { + IdhitR::new((self.bits & 0x01ff) as u16) + } +} +#[doc = "Legacy RX FIFO Information\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfirSpec; +impl crate::RegisterSpec for RxfirSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfir::R`](R) reader structure"] +impl crate::Readable for RxfirSpec {} +#[doc = "`reset()` method sets RXFIR to value 0"] +impl crate::Resettable for RxfirSpec {} diff --git a/mcxa276-pac/src/can0/rximr.rs b/mcxa276-pac/src/can0/rximr.rs new file mode 100644 index 000000000..23d4d8868 --- /dev/null +++ b/mcxa276-pac/src/can0/rximr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RXIMR[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `RXIMR[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `MI` reader - Individual Mask Bits"] +pub type MiR = crate::FieldReader; +#[doc = "Field `MI` writer - Individual Mask Bits"] +pub type MiW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Individual Mask Bits"] + #[inline(always)] + pub fn mi(&self) -> MiR { + MiR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Individual Mask Bits"] + #[inline(always)] + pub fn mi(&mut self) -> MiW { + MiW::new(self, 0) + } +} +#[doc = "Receive Individual Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rximr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rximr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RximrSpec; +impl crate::RegisterSpec for RximrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rximr::R`](R) reader structure"] +impl crate::Readable for RximrSpec {} +#[doc = "`write(|w| ..)` method takes [`rximr::W`](W) writer structure"] +impl crate::Writable for RximrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXIMR[%s] to value 0"] +impl crate::Resettable for RximrSpec {} diff --git a/mcxa276-pac/src/can0/rxmgmask.rs b/mcxa276-pac/src/can0/rxmgmask.rs new file mode 100644 index 000000000..f2ebaa2ab --- /dev/null +++ b/mcxa276-pac/src/can0/rxmgmask.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RXMGMASK` reader"] +pub type R = crate::R; +#[doc = "Register `RXMGMASK` writer"] +pub type W = crate::W; +#[doc = "Field `MG` reader - Global Mask for RX Message Buffers"] +pub type MgR = crate::FieldReader; +#[doc = "Field `MG` writer - Global Mask for RX Message Buffers"] +pub type MgW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Global Mask for RX Message Buffers"] + #[inline(always)] + pub fn mg(&self) -> MgR { + MgR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Global Mask for RX Message Buffers"] + #[inline(always)] + pub fn mg(&mut self) -> MgW { + MgW::new(self, 0) + } +} +#[doc = "RX Message Buffers Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxmgmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxmgmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxmgmaskSpec; +impl crate::RegisterSpec for RxmgmaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxmgmask::R`](R) reader structure"] +impl crate::Readable for RxmgmaskSpec {} +#[doc = "`write(|w| ..)` method takes [`rxmgmask::W`](W) writer structure"] +impl crate::Writable for RxmgmaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXMGMASK to value 0"] +impl crate::Resettable for RxmgmaskSpec {} diff --git a/mcxa276-pac/src/can0/timer.rs b/mcxa276-pac/src/can0/timer.rs new file mode 100644 index 000000000..080ae41a3 --- /dev/null +++ b/mcxa276-pac/src/can0/timer.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TIMER` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER` reader - Timer Value"] +pub type TimerR = crate::FieldReader; +#[doc = "Field `TIMER` writer - Timer Value"] +pub type TimerW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timer Value"] + #[inline(always)] + pub fn timer(&self) -> TimerR { + TimerR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timer Value"] + #[inline(always)] + pub fn timer(&mut self) -> TimerW { + TimerW::new(self, 0) + } +} +#[doc = "Free-Running Timer\n\nYou can [`read`](crate::Reg::read) this register and get [`timer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimerSpec; +impl crate::RegisterSpec for TimerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer::R`](R) reader structure"] +impl crate::Readable for TimerSpec {} +#[doc = "`write(|w| ..)` method takes [`timer::W`](W) writer structure"] +impl crate::Writable for TimerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMER to value 0"] +impl crate::Resettable for TimerSpec {} diff --git a/mcxa276-pac/src/can0/wmb.rs b/mcxa276-pac/src/can0/wmb.rs new file mode 100644 index 000000000..d7b31fcdc --- /dev/null +++ b/mcxa276-pac/src/can0/wmb.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] +#[doc(alias = "WMB")] +pub struct Wmb { + wmb_cs: WmbCs, + wmb_id: WmbId, + wmb_d03: WmbD03, + wmb_d47: WmbD47, +} +impl Wmb { + #[doc = "0x00 - Wake-Up Message Buffer"] + #[inline(always)] + pub const fn wmb_cs(&self) -> &WmbCs { + &self.wmb_cs + } + #[doc = "0x04 - Wake-Up Message Buffer for ID"] + #[inline(always)] + pub const fn wmb_id(&self) -> &WmbId { + &self.wmb_id + } + #[doc = "0x08 - Wake-Up Message Buffer for Data 0-3"] + #[inline(always)] + pub const fn wmb_d03(&self) -> &WmbD03 { + &self.wmb_d03 + } + #[doc = "0x0c - Wake-Up Message Buffer Register Data 4-7"] + #[inline(always)] + pub const fn wmb_d47(&self) -> &WmbD47 { + &self.wmb_d47 + } +} +#[doc = "WMB_CS (r) register accessor: Wake-Up Message Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_cs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_cs`] module"] +#[doc(alias = "WMB_CS")] +pub type WmbCs = crate::Reg; +#[doc = "Wake-Up Message Buffer"] +pub mod wmb_cs; +#[doc = "WMB_ID (r) register accessor: Wake-Up Message Buffer for ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_id`] module"] +#[doc(alias = "WMB_ID")] +pub type WmbId = crate::Reg; +#[doc = "Wake-Up Message Buffer for ID"] +pub mod wmb_id; +#[doc = "WMB_D03 (r) register accessor: Wake-Up Message Buffer for Data 0-3\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d03::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_d03`] module"] +#[doc(alias = "WMB_D03")] +pub type WmbD03 = crate::Reg; +#[doc = "Wake-Up Message Buffer for Data 0-3"] +pub mod wmb_d03; +#[doc = "WMB_D47 (r) register accessor: Wake-Up Message Buffer Register Data 4-7\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d47::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_d47`] module"] +#[doc(alias = "WMB_D47")] +pub type WmbD47 = crate::Reg; +#[doc = "Wake-Up Message Buffer Register Data 4-7"] +pub mod wmb_d47; diff --git a/mcxa276-pac/src/can0/wmb/wmb_cs.rs b/mcxa276-pac/src/can0/wmb/wmb_cs.rs new file mode 100644 index 000000000..7e448ab72 --- /dev/null +++ b/mcxa276-pac/src/can0/wmb/wmb_cs.rs @@ -0,0 +1,143 @@ +#[doc = "Register `WMB_CS` reader"] +pub type R = crate::R; +#[doc = "Field `DLC` reader - Length of Data in Bytes"] +pub type DlcR = crate::FieldReader; +#[doc = "Remote Transmission Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rtr { + #[doc = "0: Data"] + NotRemote = 0, + #[doc = "1: Remote"] + Remote = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rtr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RTR` reader - Remote Transmission Request"] +pub type RtrR = crate::BitReader; +impl RtrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rtr { + match self.bits { + false => Rtr::NotRemote, + true => Rtr::Remote, + } + } + #[doc = "Data"] + #[inline(always)] + pub fn is_not_remote(&self) -> bool { + *self == Rtr::NotRemote + } + #[doc = "Remote"] + #[inline(always)] + pub fn is_remote(&self) -> bool { + *self == Rtr::Remote + } +} +#[doc = "ID Extended Bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ide { + #[doc = "0: Standard"] + Standard = 0, + #[doc = "1: Extended"] + Extended = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ide) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IDE` reader - ID Extended Bit"] +pub type IdeR = crate::BitReader; +impl IdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ide { + match self.bits { + false => Ide::Standard, + true => Ide::Extended, + } + } + #[doc = "Standard"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == Ide::Standard + } + #[doc = "Extended"] + #[inline(always)] + pub fn is_extended(&self) -> bool { + *self == Ide::Extended + } +} +#[doc = "Substitute Remote Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Srr { + #[doc = "0: Dominant"] + Dominant = 0, + #[doc = "1: Recessive"] + Recessive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Srr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRR` reader - Substitute Remote Request"] +pub type SrrR = crate::BitReader; +impl SrrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Srr { + match self.bits { + false => Srr::Dominant, + true => Srr::Recessive, + } + } + #[doc = "Dominant"] + #[inline(always)] + pub fn is_dominant(&self) -> bool { + *self == Srr::Dominant + } + #[doc = "Recessive"] + #[inline(always)] + pub fn is_recessive(&self) -> bool { + *self == Srr::Recessive + } +} +impl R { + #[doc = "Bits 16:19 - Length of Data in Bytes"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Remote Transmission Request"] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ID Extended Bit"] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Substitute Remote Request"] + #[inline(always)] + pub fn srr(&self) -> SrrR { + SrrR::new(((self.bits >> 22) & 1) != 0) + } +} +#[doc = "Wake-Up Message Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_cs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WmbCsSpec; +impl crate::RegisterSpec for WmbCsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wmb_cs::R`](R) reader structure"] +impl crate::Readable for WmbCsSpec {} +#[doc = "`reset()` method sets WMB_CS to value 0"] +impl crate::Resettable for WmbCsSpec {} diff --git a/mcxa276-pac/src/can0/wmb/wmb_d03.rs b/mcxa276-pac/src/can0/wmb/wmb_d03.rs new file mode 100644 index 000000000..afcbf6dce --- /dev/null +++ b/mcxa276-pac/src/can0/wmb/wmb_d03.rs @@ -0,0 +1,41 @@ +#[doc = "Register `WMB_D03` reader"] +pub type R = crate::R; +#[doc = "Field `Data_byte_3` reader - Data Byte 3"] +pub type DataByte3R = crate::FieldReader; +#[doc = "Field `Data_byte_2` reader - Data Byte 2"] +pub type DataByte2R = crate::FieldReader; +#[doc = "Field `Data_byte_1` reader - Data Byte 1"] +pub type DataByte1R = crate::FieldReader; +#[doc = "Field `Data_byte_0` reader - Data Byte 0"] +pub type DataByte0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Data Byte 3"] + #[inline(always)] + pub fn data_byte_3(&self) -> DataByte3R { + DataByte3R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 2"] + #[inline(always)] + pub fn data_byte_2(&self) -> DataByte2R { + DataByte2R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data Byte 1"] + #[inline(always)] + pub fn data_byte_1(&self) -> DataByte1R { + DataByte1R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data Byte 0"] + #[inline(always)] + pub fn data_byte_0(&self) -> DataByte0R { + DataByte0R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Wake-Up Message Buffer for Data 0-3\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d03::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WmbD03Spec; +impl crate::RegisterSpec for WmbD03Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wmb_d03::R`](R) reader structure"] +impl crate::Readable for WmbD03Spec {} +#[doc = "`reset()` method sets WMB_D03 to value 0"] +impl crate::Resettable for WmbD03Spec {} diff --git a/mcxa276-pac/src/can0/wmb/wmb_d47.rs b/mcxa276-pac/src/can0/wmb/wmb_d47.rs new file mode 100644 index 000000000..38f88ea35 --- /dev/null +++ b/mcxa276-pac/src/can0/wmb/wmb_d47.rs @@ -0,0 +1,41 @@ +#[doc = "Register `WMB_D47` reader"] +pub type R = crate::R; +#[doc = "Field `Data_byte_7` reader - Data Byte 7"] +pub type DataByte7R = crate::FieldReader; +#[doc = "Field `Data_byte_6` reader - Data Byte 6"] +pub type DataByte6R = crate::FieldReader; +#[doc = "Field `Data_byte_5` reader - Data Byte 5"] +pub type DataByte5R = crate::FieldReader; +#[doc = "Field `Data_byte_4` reader - Data Byte 4"] +pub type DataByte4R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Data Byte 7"] + #[inline(always)] + pub fn data_byte_7(&self) -> DataByte7R { + DataByte7R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 6"] + #[inline(always)] + pub fn data_byte_6(&self) -> DataByte6R { + DataByte6R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Data Byte 5"] + #[inline(always)] + pub fn data_byte_5(&self) -> DataByte5R { + DataByte5R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Data Byte 4"] + #[inline(always)] + pub fn data_byte_4(&self) -> DataByte4R { + DataByte4R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Wake-Up Message Buffer Register Data 4-7\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d47::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WmbD47Spec; +impl crate::RegisterSpec for WmbD47Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wmb_d47::R`](R) reader structure"] +impl crate::Readable for WmbD47Spec {} +#[doc = "`reset()` method sets WMB_D47 to value 0"] +impl crate::Resettable for WmbD47Spec {} diff --git a/mcxa276-pac/src/can0/wmb/wmb_id.rs b/mcxa276-pac/src/can0/wmb/wmb_id.rs new file mode 100644 index 000000000..a2fb06787 --- /dev/null +++ b/mcxa276-pac/src/can0/wmb/wmb_id.rs @@ -0,0 +1,20 @@ +#[doc = "Register `WMB_ID` reader"] +pub type R = crate::R; +#[doc = "Field `ID` reader - Received ID in Pretended Networking Mode"] +pub type IdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:28 - Received ID in Pretended Networking Mode"] + #[inline(always)] + pub fn id(&self) -> IdR { + IdR::new(self.bits & 0x1fff_ffff) + } +} +#[doc = "Wake-Up Message Buffer for ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WmbIdSpec; +impl crate::RegisterSpec for WmbIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wmb_id::R`](R) reader structure"] +impl crate::Readable for WmbIdSpec {} +#[doc = "`reset()` method sets WMB_ID to value 0"] +impl crate::Resettable for WmbIdSpec {} diff --git a/mcxa276-pac/src/can0/wu_mtc.rs b/mcxa276-pac/src/can0/wu_mtc.rs new file mode 100644 index 000000000..779145c87 --- /dev/null +++ b/mcxa276-pac/src/can0/wu_mtc.rs @@ -0,0 +1,155 @@ +#[doc = "Register `WU_MTC` reader"] +pub type R = crate::R; +#[doc = "Register `WU_MTC` writer"] +pub type W = crate::W; +#[doc = "Field `MCOUNTER` reader - Number of Matches in Pretended Networking"] +pub type McounterR = crate::FieldReader; +#[doc = "Wake-up by Match Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wumf { + #[doc = "0: No event detected"] + NoMatch = 0, + #[doc = "1: Event detected"] + Match = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wumf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUMF` reader - Wake-up by Match Flag"] +pub type WumfR = crate::BitReader; +impl WumfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wumf { + match self.bits { + false => Wumf::NoMatch, + true => Wumf::Match, + } + } + #[doc = "No event detected"] + #[inline(always)] + pub fn is_no_match(&self) -> bool { + *self == Wumf::NoMatch + } + #[doc = "Event detected"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Wumf::Match + } +} +#[doc = "Field `WUMF` writer - Wake-up by Match Flag"] +pub type WumfW<'a, REG> = crate::BitWriter1C<'a, REG, Wumf>; +impl<'a, REG> WumfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No event detected"] + #[inline(always)] + pub fn no_match(self) -> &'a mut crate::W { + self.variant(Wumf::NoMatch) + } + #[doc = "Event detected"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Wumf::Match) + } +} +#[doc = "Wake-up by Timeout Flag Bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wtof { + #[doc = "0: No event detected"] + NoWakeup = 0, + #[doc = "1: Event detected"] + Wakeup = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wtof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WTOF` reader - Wake-up by Timeout Flag Bit"] +pub type WtofR = crate::BitReader; +impl WtofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wtof { + match self.bits { + false => Wtof::NoWakeup, + true => Wtof::Wakeup, + } + } + #[doc = "No event detected"] + #[inline(always)] + pub fn is_no_wakeup(&self) -> bool { + *self == Wtof::NoWakeup + } + #[doc = "Event detected"] + #[inline(always)] + pub fn is_wakeup(&self) -> bool { + *self == Wtof::Wakeup + } +} +#[doc = "Field `WTOF` writer - Wake-up by Timeout Flag Bit"] +pub type WtofW<'a, REG> = crate::BitWriter1C<'a, REG, Wtof>; +impl<'a, REG> WtofW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No event detected"] + #[inline(always)] + pub fn no_wakeup(self) -> &'a mut crate::W { + self.variant(Wtof::NoWakeup) + } + #[doc = "Event detected"] + #[inline(always)] + pub fn wakeup(self) -> &'a mut crate::W { + self.variant(Wtof::Wakeup) + } +} +impl R { + #[doc = "Bits 8:15 - Number of Matches in Pretended Networking"] + #[inline(always)] + pub fn mcounter(&self) -> McounterR { + McounterR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - Wake-up by Match Flag"] + #[inline(always)] + pub fn wumf(&self) -> WumfR { + WumfR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Wake-up by Timeout Flag Bit"] + #[inline(always)] + pub fn wtof(&self) -> WtofR { + WtofR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 16 - Wake-up by Match Flag"] + #[inline(always)] + pub fn wumf(&mut self) -> WumfW { + WumfW::new(self, 16) + } + #[doc = "Bit 17 - Wake-up by Timeout Flag Bit"] + #[inline(always)] + pub fn wtof(&mut self) -> WtofW { + WtofW::new(self, 17) + } +} +#[doc = "Pretended Networking Wake-Up Match\n\nYou can [`read`](crate::Reg::read) this register and get [`wu_mtc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wu_mtc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WuMtcSpec; +impl crate::RegisterSpec for WuMtcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wu_mtc::R`](R) reader structure"] +impl crate::Readable for WuMtcSpec {} +#[doc = "`write(|w| ..)` method takes [`wu_mtc::W`](W) writer structure"] +impl crate::Writable for WuMtcSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0003_0000; +} +#[doc = "`reset()` method sets WU_MTC to value 0"] +impl crate::Resettable for WuMtcSpec {} diff --git a/mcxa276-pac/src/cdog0.rs b/mcxa276-pac/src/cdog0.rs new file mode 100644 index 000000000..4af471705 --- /dev/null +++ b/mcxa276-pac/src/cdog0.rs @@ -0,0 +1,216 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + control: Control, + reload: Reload, + instruction_timer: InstructionTimer, + _reserved3: [u8; 0x04], + status: Status, + status2: Status2, + flags: Flags, + persistent: Persistent, + start: Start, + stop: Stop, + restart: Restart, + add: Add, + add1: Add1, + add16: Add16, + add256: Add256, + sub: Sub, + sub1: Sub1, + sub16: Sub16, + sub256: Sub256, + assert16: Assert16, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn control(&self) -> &Control { + &self.control + } + #[doc = "0x04 - Instruction Timer Reload Register"] + #[inline(always)] + pub const fn reload(&self) -> &Reload { + &self.reload + } + #[doc = "0x08 - Instruction Timer Register"] + #[inline(always)] + pub const fn instruction_timer(&self) -> &InstructionTimer { + &self.instruction_timer + } + #[doc = "0x10 - Status 1 Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x14 - Status 2 Register"] + #[inline(always)] + pub const fn status2(&self) -> &Status2 { + &self.status2 + } + #[doc = "0x18 - Flags Register"] + #[inline(always)] + pub const fn flags(&self) -> &Flags { + &self.flags + } + #[doc = "0x1c - Persistent Data Storage Register"] + #[inline(always)] + pub const fn persistent(&self) -> &Persistent { + &self.persistent + } + #[doc = "0x20 - START Command Register"] + #[inline(always)] + pub const fn start(&self) -> &Start { + &self.start + } + #[doc = "0x24 - STOP Command Register"] + #[inline(always)] + pub const fn stop(&self) -> &Stop { + &self.stop + } + #[doc = "0x28 - RESTART Command Register"] + #[inline(always)] + pub const fn restart(&self) -> &Restart { + &self.restart + } + #[doc = "0x2c - ADD Command Register"] + #[inline(always)] + pub const fn add(&self) -> &Add { + &self.add + } + #[doc = "0x30 - ADD1 Command Register"] + #[inline(always)] + pub const fn add1(&self) -> &Add1 { + &self.add1 + } + #[doc = "0x34 - ADD16 Command Register"] + #[inline(always)] + pub const fn add16(&self) -> &Add16 { + &self.add16 + } + #[doc = "0x38 - ADD256 Command Register"] + #[inline(always)] + pub const fn add256(&self) -> &Add256 { + &self.add256 + } + #[doc = "0x3c - SUB Command Register"] + #[inline(always)] + pub const fn sub(&self) -> &Sub { + &self.sub + } + #[doc = "0x40 - SUB1 Command Register"] + #[inline(always)] + pub const fn sub1(&self) -> &Sub1 { + &self.sub1 + } + #[doc = "0x44 - SUB16 Command Register"] + #[inline(always)] + pub const fn sub16(&self) -> &Sub16 { + &self.sub16 + } + #[doc = "0x48 - SUB256 Command Register"] + #[inline(always)] + pub const fn sub256(&self) -> &Sub256 { + &self.sub256 + } + #[doc = "0x4c - ASSERT16 Command Register"] + #[inline(always)] + pub const fn assert16(&self) -> &Assert16 { + &self.assert16 + } +} +#[doc = "CONTROL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`] module"] +#[doc(alias = "CONTROL")] +pub type Control = crate::Reg; +#[doc = "Control Register"] +pub mod control; +#[doc = "RELOAD (rw) register accessor: Instruction Timer Reload Register\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reload`] module"] +#[doc(alias = "RELOAD")] +pub type Reload = crate::Reg; +#[doc = "Instruction Timer Reload Register"] +pub mod reload; +#[doc = "INSTRUCTION_TIMER (r) register accessor: Instruction Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`instruction_timer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@instruction_timer`] module"] +#[doc(alias = "INSTRUCTION_TIMER")] +pub type InstructionTimer = crate::Reg; +#[doc = "Instruction Timer Register"] +pub mod instruction_timer; +#[doc = "STATUS (r) register accessor: Status 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status 1 Register"] +pub mod status; +#[doc = "STATUS2 (r) register accessor: Status 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status2`] module"] +#[doc(alias = "STATUS2")] +pub type Status2 = crate::Reg; +#[doc = "Status 2 Register"] +pub mod status2; +#[doc = "FLAGS (rw) register accessor: Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flags::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flags::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flags`] module"] +#[doc(alias = "FLAGS")] +pub type Flags = crate::Reg; +#[doc = "Flags Register"] +pub mod flags; +#[doc = "PERSISTENT (rw) register accessor: Persistent Data Storage Register\n\nYou can [`read`](crate::Reg::read) this register and get [`persistent::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`persistent::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@persistent`] module"] +#[doc(alias = "PERSISTENT")] +pub type Persistent = crate::Reg; +#[doc = "Persistent Data Storage Register"] +pub mod persistent; +#[doc = "START (w) register accessor: START Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@start`] module"] +#[doc(alias = "START")] +pub type Start = crate::Reg; +#[doc = "START Command Register"] +pub mod start; +#[doc = "STOP (w) register accessor: STOP Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stop::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stop`] module"] +#[doc(alias = "STOP")] +pub type Stop = crate::Reg; +#[doc = "STOP Command Register"] +pub mod stop; +#[doc = "RESTART (w) register accessor: RESTART Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`restart::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@restart`] module"] +#[doc(alias = "RESTART")] +pub type Restart = crate::Reg; +#[doc = "RESTART Command Register"] +pub mod restart; +#[doc = "ADD (w) register accessor: ADD Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add`] module"] +#[doc(alias = "ADD")] +pub type Add = crate::Reg; +#[doc = "ADD Command Register"] +pub mod add; +#[doc = "ADD1 (w) register accessor: ADD1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add1`] module"] +#[doc(alias = "ADD1")] +pub type Add1 = crate::Reg; +#[doc = "ADD1 Command Register"] +pub mod add1; +#[doc = "ADD16 (w) register accessor: ADD16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add16::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add16`] module"] +#[doc(alias = "ADD16")] +pub type Add16 = crate::Reg; +#[doc = "ADD16 Command Register"] +pub mod add16; +#[doc = "ADD256 (w) register accessor: ADD256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add256::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add256`] module"] +#[doc(alias = "ADD256")] +pub type Add256 = crate::Reg; +#[doc = "ADD256 Command Register"] +pub mod add256; +#[doc = "SUB (w) register accessor: SUB Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub`] module"] +#[doc(alias = "SUB")] +pub type Sub = crate::Reg; +#[doc = "SUB Command Register"] +pub mod sub; +#[doc = "SUB1 (w) register accessor: SUB1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub1`] module"] +#[doc(alias = "SUB1")] +pub type Sub1 = crate::Reg; +#[doc = "SUB1 Command Register"] +pub mod sub1; +#[doc = "SUB16 (w) register accessor: SUB16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub16::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub16`] module"] +#[doc(alias = "SUB16")] +pub type Sub16 = crate::Reg; +#[doc = "SUB16 Command Register"] +pub mod sub16; +#[doc = "SUB256 (w) register accessor: SUB256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub256::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub256`] module"] +#[doc(alias = "SUB256")] +pub type Sub256 = crate::Reg; +#[doc = "SUB256 Command Register"] +pub mod sub256; +#[doc = "ASSERT16 (w) register accessor: ASSERT16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`assert16::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@assert16`] module"] +#[doc(alias = "ASSERT16")] +pub type Assert16 = crate::Reg; +#[doc = "ASSERT16 Command Register"] +pub mod assert16; diff --git a/mcxa276-pac/src/cdog0/add.rs b/mcxa276-pac/src/cdog0/add.rs new file mode 100644 index 000000000..5d96221f0 --- /dev/null +++ b/mcxa276-pac/src/cdog0/add.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ADD` writer"] +pub type W = crate::W; +#[doc = "Field `AD` writer - ADD Write Value"] +pub type AdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - ADD Write Value"] + #[inline(always)] + pub fn ad(&mut self) -> AdW { + AdW::new(self, 0) + } +} +#[doc = "ADD Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AddSpec; +impl crate::RegisterSpec for AddSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`add::W`](W) writer structure"] +impl crate::Writable for AddSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADD to value 0"] +impl crate::Resettable for AddSpec {} diff --git a/mcxa276-pac/src/cdog0/add1.rs b/mcxa276-pac/src/cdog0/add1.rs new file mode 100644 index 000000000..01ef747ee --- /dev/null +++ b/mcxa276-pac/src/cdog0/add1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ADD1` writer"] +pub type W = crate::W; +#[doc = "Field `AD1` writer - ADD 1"] +pub type Ad1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - ADD 1"] + #[inline(always)] + pub fn ad1(&mut self) -> Ad1W { + Ad1W::new(self, 0) + } +} +#[doc = "ADD1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Add1Spec; +impl crate::RegisterSpec for Add1Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`add1::W`](W) writer structure"] +impl crate::Writable for Add1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADD1 to value 0"] +impl crate::Resettable for Add1Spec {} diff --git a/mcxa276-pac/src/cdog0/add16.rs b/mcxa276-pac/src/cdog0/add16.rs new file mode 100644 index 000000000..bb0f9d388 --- /dev/null +++ b/mcxa276-pac/src/cdog0/add16.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ADD16` writer"] +pub type W = crate::W; +#[doc = "Field `AD16` writer - ADD 16"] +pub type Ad16W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - ADD 16"] + #[inline(always)] + pub fn ad16(&mut self) -> Ad16W { + Ad16W::new(self, 0) + } +} +#[doc = "ADD16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add16::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Add16Spec; +impl crate::RegisterSpec for Add16Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`add16::W`](W) writer structure"] +impl crate::Writable for Add16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADD16 to value 0"] +impl crate::Resettable for Add16Spec {} diff --git a/mcxa276-pac/src/cdog0/add256.rs b/mcxa276-pac/src/cdog0/add256.rs new file mode 100644 index 000000000..c85048dcf --- /dev/null +++ b/mcxa276-pac/src/cdog0/add256.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ADD256` writer"] +pub type W = crate::W; +#[doc = "Field `AD256` writer - ADD 256"] +pub type Ad256W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - ADD 256"] + #[inline(always)] + pub fn ad256(&mut self) -> Ad256W { + Ad256W::new(self, 0) + } +} +#[doc = "ADD256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add256::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Add256Spec; +impl crate::RegisterSpec for Add256Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`add256::W`](W) writer structure"] +impl crate::Writable for Add256Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADD256 to value 0"] +impl crate::Resettable for Add256Spec {} diff --git a/mcxa276-pac/src/cdog0/assert16.rs b/mcxa276-pac/src/cdog0/assert16.rs new file mode 100644 index 000000000..c7fcd6b5e --- /dev/null +++ b/mcxa276-pac/src/cdog0/assert16.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ASSERT16` writer"] +pub type W = crate::W; +#[doc = "Field `AST16` writer - ASSERT16 Command"] +pub type Ast16W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - ASSERT16 Command"] + #[inline(always)] + pub fn ast16(&mut self) -> Ast16W { + Ast16W::new(self, 0) + } +} +#[doc = "ASSERT16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`assert16::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Assert16Spec; +impl crate::RegisterSpec for Assert16Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`assert16::W`](W) writer structure"] +impl crate::Writable for Assert16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ASSERT16 to value 0"] +impl crate::Resettable for Assert16Spec {} diff --git a/mcxa276-pac/src/cdog0/control.rs b/mcxa276-pac/src/cdog0/control.rs new file mode 100644 index 000000000..7cdd49906 --- /dev/null +++ b/mcxa276-pac/src/cdog0/control.rs @@ -0,0 +1,648 @@ +#[doc = "Register `CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `CONTROL` writer"] +pub type W = crate::W; +#[doc = "Lock control\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LockCtrl { + #[doc = "1: Locked"] + Locked = 1, + #[doc = "2: Unlocked"] + Unlocked = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LockCtrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LockCtrl { + type Ux = u8; +} +impl crate::IsEnum for LockCtrl {} +#[doc = "Field `LOCK_CTRL` reader - Lock control"] +pub type LockCtrlR = crate::FieldReader; +impl LockCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(LockCtrl::Locked), + 2 => Some(LockCtrl::Unlocked), + _ => None, + } + } + #[doc = "Locked"] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == LockCtrl::Locked + } + #[doc = "Unlocked"] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == LockCtrl::Unlocked + } +} +#[doc = "Field `LOCK_CTRL` writer - Lock control"] +pub type LockCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, LockCtrl>; +impl<'a, REG> LockCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Locked"] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(LockCtrl::Locked) + } + #[doc = "Unlocked"] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(LockCtrl::Unlocked) + } +} +#[doc = "TIMEOUT fault control\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TimeoutCtrl { + #[doc = "1: Enable reset"] + EnableReset = 1, + #[doc = "2: Enable interrupt"] + EnableInterrupt = 2, + #[doc = "4: Disable both reset and interrupt"] + DisableBoth = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TimeoutCtrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TimeoutCtrl { + type Ux = u8; +} +impl crate::IsEnum for TimeoutCtrl {} +#[doc = "Field `TIMEOUT_CTRL` reader - TIMEOUT fault control"] +pub type TimeoutCtrlR = crate::FieldReader; +impl TimeoutCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(TimeoutCtrl::EnableReset), + 2 => Some(TimeoutCtrl::EnableInterrupt), + 4 => Some(TimeoutCtrl::DisableBoth), + _ => None, + } + } + #[doc = "Enable reset"] + #[inline(always)] + pub fn is_enable_reset(&self) -> bool { + *self == TimeoutCtrl::EnableReset + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn is_enable_interrupt(&self) -> bool { + *self == TimeoutCtrl::EnableInterrupt + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn is_disable_both(&self) -> bool { + *self == TimeoutCtrl::DisableBoth + } +} +#[doc = "Field `TIMEOUT_CTRL` writer - TIMEOUT fault control"] +pub type TimeoutCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, TimeoutCtrl>; +impl<'a, REG> TimeoutCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Enable reset"] + #[inline(always)] + pub fn enable_reset(self) -> &'a mut crate::W { + self.variant(TimeoutCtrl::EnableReset) + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn enable_interrupt(self) -> &'a mut crate::W { + self.variant(TimeoutCtrl::EnableInterrupt) + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn disable_both(self) -> &'a mut crate::W { + self.variant(TimeoutCtrl::DisableBoth) + } +} +#[doc = "MISCOMPARE fault control\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MiscompareCtrl { + #[doc = "1: Enable reset"] + EnableReset = 1, + #[doc = "2: Enable interrupt"] + EnableInterrupt = 2, + #[doc = "4: Disable both reset and interrupt"] + DisableBoth = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MiscompareCtrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for MiscompareCtrl { + type Ux = u8; +} +impl crate::IsEnum for MiscompareCtrl {} +#[doc = "Field `MISCOMPARE_CTRL` reader - MISCOMPARE fault control"] +pub type MiscompareCtrlR = crate::FieldReader; +impl MiscompareCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(MiscompareCtrl::EnableReset), + 2 => Some(MiscompareCtrl::EnableInterrupt), + 4 => Some(MiscompareCtrl::DisableBoth), + _ => None, + } + } + #[doc = "Enable reset"] + #[inline(always)] + pub fn is_enable_reset(&self) -> bool { + *self == MiscompareCtrl::EnableReset + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn is_enable_interrupt(&self) -> bool { + *self == MiscompareCtrl::EnableInterrupt + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn is_disable_both(&self) -> bool { + *self == MiscompareCtrl::DisableBoth + } +} +#[doc = "Field `MISCOMPARE_CTRL` writer - MISCOMPARE fault control"] +pub type MiscompareCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, MiscompareCtrl>; +impl<'a, REG> MiscompareCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Enable reset"] + #[inline(always)] + pub fn enable_reset(self) -> &'a mut crate::W { + self.variant(MiscompareCtrl::EnableReset) + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn enable_interrupt(self) -> &'a mut crate::W { + self.variant(MiscompareCtrl::EnableInterrupt) + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn disable_both(self) -> &'a mut crate::W { + self.variant(MiscompareCtrl::DisableBoth) + } +} +#[doc = "SEQUENCE fault control\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SequenceCtrl { + #[doc = "1: Enable reset"] + EnableReset = 1, + #[doc = "2: Enable interrupt"] + EnableInterrupt = 2, + #[doc = "4: Disable both reset and interrupt"] + DisableBoth = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SequenceCtrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SequenceCtrl { + type Ux = u8; +} +impl crate::IsEnum for SequenceCtrl {} +#[doc = "Field `SEQUENCE_CTRL` reader - SEQUENCE fault control"] +pub type SequenceCtrlR = crate::FieldReader; +impl SequenceCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(SequenceCtrl::EnableReset), + 2 => Some(SequenceCtrl::EnableInterrupt), + 4 => Some(SequenceCtrl::DisableBoth), + _ => None, + } + } + #[doc = "Enable reset"] + #[inline(always)] + pub fn is_enable_reset(&self) -> bool { + *self == SequenceCtrl::EnableReset + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn is_enable_interrupt(&self) -> bool { + *self == SequenceCtrl::EnableInterrupt + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn is_disable_both(&self) -> bool { + *self == SequenceCtrl::DisableBoth + } +} +#[doc = "Field `SEQUENCE_CTRL` writer - SEQUENCE fault control"] +pub type SequenceCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, SequenceCtrl>; +impl<'a, REG> SequenceCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Enable reset"] + #[inline(always)] + pub fn enable_reset(self) -> &'a mut crate::W { + self.variant(SequenceCtrl::EnableReset) + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn enable_interrupt(self) -> &'a mut crate::W { + self.variant(SequenceCtrl::EnableInterrupt) + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn disable_both(self) -> &'a mut crate::W { + self.variant(SequenceCtrl::DisableBoth) + } +} +#[doc = "STATE fault control\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum StateCtrl { + #[doc = "1: Enable reset"] + EnableReset = 1, + #[doc = "2: Enable interrupt"] + EnableInterrupt = 2, + #[doc = "4: Disable both reset and interrupt"] + DisableBoth = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: StateCtrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for StateCtrl { + type Ux = u8; +} +impl crate::IsEnum for StateCtrl {} +#[doc = "Field `STATE_CTRL` reader - STATE fault control"] +pub type StateCtrlR = crate::FieldReader; +impl StateCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(StateCtrl::EnableReset), + 2 => Some(StateCtrl::EnableInterrupt), + 4 => Some(StateCtrl::DisableBoth), + _ => None, + } + } + #[doc = "Enable reset"] + #[inline(always)] + pub fn is_enable_reset(&self) -> bool { + *self == StateCtrl::EnableReset + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn is_enable_interrupt(&self) -> bool { + *self == StateCtrl::EnableInterrupt + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn is_disable_both(&self) -> bool { + *self == StateCtrl::DisableBoth + } +} +#[doc = "Field `STATE_CTRL` writer - STATE fault control"] +pub type StateCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, StateCtrl>; +impl<'a, REG> StateCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Enable reset"] + #[inline(always)] + pub fn enable_reset(self) -> &'a mut crate::W { + self.variant(StateCtrl::EnableReset) + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn enable_interrupt(self) -> &'a mut crate::W { + self.variant(StateCtrl::EnableInterrupt) + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn disable_both(self) -> &'a mut crate::W { + self.variant(StateCtrl::DisableBoth) + } +} +#[doc = "ADDRESS fault control\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AddressCtrl { + #[doc = "1: Enable reset"] + EnableReset = 1, + #[doc = "2: Enable interrupt"] + EnableInterrupt = 2, + #[doc = "4: Disable both reset and interrupt"] + DisableBoth = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AddressCtrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AddressCtrl { + type Ux = u8; +} +impl crate::IsEnum for AddressCtrl {} +#[doc = "Field `ADDRESS_CTRL` reader - ADDRESS fault control"] +pub type AddressCtrlR = crate::FieldReader; +impl AddressCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(AddressCtrl::EnableReset), + 2 => Some(AddressCtrl::EnableInterrupt), + 4 => Some(AddressCtrl::DisableBoth), + _ => None, + } + } + #[doc = "Enable reset"] + #[inline(always)] + pub fn is_enable_reset(&self) -> bool { + *self == AddressCtrl::EnableReset + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn is_enable_interrupt(&self) -> bool { + *self == AddressCtrl::EnableInterrupt + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn is_disable_both(&self) -> bool { + *self == AddressCtrl::DisableBoth + } +} +#[doc = "Field `ADDRESS_CTRL` writer - ADDRESS fault control"] +pub type AddressCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, AddressCtrl>; +impl<'a, REG> AddressCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Enable reset"] + #[inline(always)] + pub fn enable_reset(self) -> &'a mut crate::W { + self.variant(AddressCtrl::EnableReset) + } + #[doc = "Enable interrupt"] + #[inline(always)] + pub fn enable_interrupt(self) -> &'a mut crate::W { + self.variant(AddressCtrl::EnableInterrupt) + } + #[doc = "Disable both reset and interrupt"] + #[inline(always)] + pub fn disable_both(self) -> &'a mut crate::W { + self.variant(AddressCtrl::DisableBoth) + } +} +#[doc = "IRQ pause control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IrqPause { + #[doc = "1: Keep the timer running"] + RunTimer = 1, + #[doc = "2: Stop the timer"] + PauseTimer = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IrqPause) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IrqPause { + type Ux = u8; +} +impl crate::IsEnum for IrqPause {} +#[doc = "Field `IRQ_PAUSE` reader - IRQ pause control"] +pub type IrqPauseR = crate::FieldReader; +impl IrqPauseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(IrqPause::RunTimer), + 2 => Some(IrqPause::PauseTimer), + _ => None, + } + } + #[doc = "Keep the timer running"] + #[inline(always)] + pub fn is_run_timer(&self) -> bool { + *self == IrqPause::RunTimer + } + #[doc = "Stop the timer"] + #[inline(always)] + pub fn is_pause_timer(&self) -> bool { + *self == IrqPause::PauseTimer + } +} +#[doc = "Field `IRQ_PAUSE` writer - IRQ pause control"] +pub type IrqPauseW<'a, REG> = crate::FieldWriter<'a, REG, 2, IrqPause>; +impl<'a, REG> IrqPauseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Keep the timer running"] + #[inline(always)] + pub fn run_timer(self) -> &'a mut crate::W { + self.variant(IrqPause::RunTimer) + } + #[doc = "Stop the timer"] + #[inline(always)] + pub fn pause_timer(self) -> &'a mut crate::W { + self.variant(IrqPause::PauseTimer) + } +} +#[doc = "DEBUG_HALT control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DebugHaltCtrl { + #[doc = "1: Keep the timer running"] + RunTimer = 1, + #[doc = "2: Stop the timer"] + PauseTimer = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DebugHaltCtrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DebugHaltCtrl { + type Ux = u8; +} +impl crate::IsEnum for DebugHaltCtrl {} +#[doc = "Field `DEBUG_HALT_CTRL` reader - DEBUG_HALT control"] +pub type DebugHaltCtrlR = crate::FieldReader; +impl DebugHaltCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(DebugHaltCtrl::RunTimer), + 2 => Some(DebugHaltCtrl::PauseTimer), + _ => None, + } + } + #[doc = "Keep the timer running"] + #[inline(always)] + pub fn is_run_timer(&self) -> bool { + *self == DebugHaltCtrl::RunTimer + } + #[doc = "Stop the timer"] + #[inline(always)] + pub fn is_pause_timer(&self) -> bool { + *self == DebugHaltCtrl::PauseTimer + } +} +#[doc = "Field `DEBUG_HALT_CTRL` writer - DEBUG_HALT control"] +pub type DebugHaltCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, DebugHaltCtrl>; +impl<'a, REG> DebugHaltCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Keep the timer running"] + #[inline(always)] + pub fn run_timer(self) -> &'a mut crate::W { + self.variant(DebugHaltCtrl::RunTimer) + } + #[doc = "Stop the timer"] + #[inline(always)] + pub fn pause_timer(self) -> &'a mut crate::W { + self.variant(DebugHaltCtrl::PauseTimer) + } +} +impl R { + #[doc = "Bits 0:1 - Lock control"] + #[inline(always)] + pub fn lock_ctrl(&self) -> LockCtrlR { + LockCtrlR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:4 - TIMEOUT fault control"] + #[inline(always)] + pub fn timeout_ctrl(&self) -> TimeoutCtrlR { + TimeoutCtrlR::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bits 5:7 - MISCOMPARE fault control"] + #[inline(always)] + pub fn miscompare_ctrl(&self) -> MiscompareCtrlR { + MiscompareCtrlR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:10 - SEQUENCE fault control"] + #[inline(always)] + pub fn sequence_ctrl(&self) -> SequenceCtrlR { + SequenceCtrlR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 14:16 - STATE fault control"] + #[inline(always)] + pub fn state_ctrl(&self) -> StateCtrlR { + StateCtrlR::new(((self.bits >> 14) & 7) as u8) + } + #[doc = "Bits 17:19 - ADDRESS fault control"] + #[inline(always)] + pub fn address_ctrl(&self) -> AddressCtrlR { + AddressCtrlR::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bits 28:29 - IRQ pause control"] + #[inline(always)] + pub fn irq_pause(&self) -> IrqPauseR { + IrqPauseR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - DEBUG_HALT control"] + #[inline(always)] + pub fn debug_halt_ctrl(&self) -> DebugHaltCtrlR { + DebugHaltCtrlR::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Lock control"] + #[inline(always)] + pub fn lock_ctrl(&mut self) -> LockCtrlW { + LockCtrlW::new(self, 0) + } + #[doc = "Bits 2:4 - TIMEOUT fault control"] + #[inline(always)] + pub fn timeout_ctrl(&mut self) -> TimeoutCtrlW { + TimeoutCtrlW::new(self, 2) + } + #[doc = "Bits 5:7 - MISCOMPARE fault control"] + #[inline(always)] + pub fn miscompare_ctrl(&mut self) -> MiscompareCtrlW { + MiscompareCtrlW::new(self, 5) + } + #[doc = "Bits 8:10 - SEQUENCE fault control"] + #[inline(always)] + pub fn sequence_ctrl(&mut self) -> SequenceCtrlW { + SequenceCtrlW::new(self, 8) + } + #[doc = "Bits 14:16 - STATE fault control"] + #[inline(always)] + pub fn state_ctrl(&mut self) -> StateCtrlW { + StateCtrlW::new(self, 14) + } + #[doc = "Bits 17:19 - ADDRESS fault control"] + #[inline(always)] + pub fn address_ctrl(&mut self) -> AddressCtrlW { + AddressCtrlW::new(self, 17) + } + #[doc = "Bits 28:29 - IRQ pause control"] + #[inline(always)] + pub fn irq_pause(&mut self) -> IrqPauseW { + IrqPauseW::new(self, 28) + } + #[doc = "Bits 30:31 - DEBUG_HALT control"] + #[inline(always)] + pub fn debug_halt_ctrl(&mut self) -> DebugHaltCtrlW { + DebugHaltCtrlW::new(self, 30) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ControlSpec; +impl crate::RegisterSpec for ControlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`control::R`](R) reader structure"] +impl crate::Readable for ControlSpec {} +#[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"] +impl crate::Writable for ControlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONTROL to value 0x5009_2492"] +impl crate::Resettable for ControlSpec { + const RESET_VALUE: u32 = 0x5009_2492; +} diff --git a/mcxa276-pac/src/cdog0/flags.rs b/mcxa276-pac/src/cdog0/flags.rs new file mode 100644 index 000000000..1ab254e8c --- /dev/null +++ b/mcxa276-pac/src/cdog0/flags.rs @@ -0,0 +1,465 @@ +#[doc = "Register `FLAGS` reader"] +pub type R = crate::R; +#[doc = "Register `FLAGS` writer"] +pub type W = crate::W; +#[doc = "TIMEOUT fault flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ToFlag { + #[doc = "0: A TIMEOUT fault has not occurred"] + NoFlag = 0, + #[doc = "1: A TIMEOUT fault has occurred"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ToFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TO_FLAG` reader - TIMEOUT fault flag"] +pub type ToFlagR = crate::BitReader; +impl ToFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ToFlag { + match self.bits { + false => ToFlag::NoFlag, + true => ToFlag::Flag, + } + } + #[doc = "A TIMEOUT fault has not occurred"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == ToFlag::NoFlag + } + #[doc = "A TIMEOUT fault has occurred"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == ToFlag::Flag + } +} +#[doc = "Field `TO_FLAG` writer - TIMEOUT fault flag"] +pub type ToFlagW<'a, REG> = crate::BitWriter1C<'a, REG, ToFlag>; +impl<'a, REG> ToFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A TIMEOUT fault has not occurred"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(ToFlag::NoFlag) + } + #[doc = "A TIMEOUT fault has occurred"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(ToFlag::Flag) + } +} +#[doc = "MISCOMPARE fault flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MiscomFlag { + #[doc = "0: A MISCOMPARE fault has not occurred"] + NoFlag = 0, + #[doc = "1: A MISCOMPARE fault has occurred"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MiscomFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MISCOM_FLAG` reader - MISCOMPARE fault flag"] +pub type MiscomFlagR = crate::BitReader; +impl MiscomFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MiscomFlag { + match self.bits { + false => MiscomFlag::NoFlag, + true => MiscomFlag::Flag, + } + } + #[doc = "A MISCOMPARE fault has not occurred"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == MiscomFlag::NoFlag + } + #[doc = "A MISCOMPARE fault has occurred"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == MiscomFlag::Flag + } +} +#[doc = "Field `MISCOM_FLAG` writer - MISCOMPARE fault flag"] +pub type MiscomFlagW<'a, REG> = crate::BitWriter1C<'a, REG, MiscomFlag>; +impl<'a, REG> MiscomFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A MISCOMPARE fault has not occurred"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(MiscomFlag::NoFlag) + } + #[doc = "A MISCOMPARE fault has occurred"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(MiscomFlag::Flag) + } +} +#[doc = "SEQUENCE fault flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SeqFlag { + #[doc = "0: A SEQUENCE fault has not occurred"] + NoFlag = 0, + #[doc = "1: A SEQUENCE fault has occurred"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SeqFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEQ_FLAG` reader - SEQUENCE fault flag"] +pub type SeqFlagR = crate::BitReader; +impl SeqFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SeqFlag { + match self.bits { + false => SeqFlag::NoFlag, + true => SeqFlag::Flag, + } + } + #[doc = "A SEQUENCE fault has not occurred"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == SeqFlag::NoFlag + } + #[doc = "A SEQUENCE fault has occurred"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == SeqFlag::Flag + } +} +#[doc = "Field `SEQ_FLAG` writer - SEQUENCE fault flag"] +pub type SeqFlagW<'a, REG> = crate::BitWriter1C<'a, REG, SeqFlag>; +impl<'a, REG> SeqFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A SEQUENCE fault has not occurred"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(SeqFlag::NoFlag) + } + #[doc = "A SEQUENCE fault has occurred"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(SeqFlag::Flag) + } +} +#[doc = "CONTROL fault flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CntFlag { + #[doc = "0: A CONTROL fault has not occurred"] + NoFlag = 0, + #[doc = "1: A CONTROL fault has occurred"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CntFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CNT_FLAG` reader - CONTROL fault flag"] +pub type CntFlagR = crate::BitReader; +impl CntFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CntFlag { + match self.bits { + false => CntFlag::NoFlag, + true => CntFlag::Flag, + } + } + #[doc = "A CONTROL fault has not occurred"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == CntFlag::NoFlag + } + #[doc = "A CONTROL fault has occurred"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == CntFlag::Flag + } +} +#[doc = "Field `CNT_FLAG` writer - CONTROL fault flag"] +pub type CntFlagW<'a, REG> = crate::BitWriter1C<'a, REG, CntFlag>; +impl<'a, REG> CntFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A CONTROL fault has not occurred"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(CntFlag::NoFlag) + } + #[doc = "A CONTROL fault has occurred"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(CntFlag::Flag) + } +} +#[doc = "STATE fault flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StateFlag { + #[doc = "0: A STATE fault has not occurred"] + NoFlag = 0, + #[doc = "1: A STATE fault has occurred"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StateFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STATE_FLAG` reader - STATE fault flag"] +pub type StateFlagR = crate::BitReader; +impl StateFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StateFlag { + match self.bits { + false => StateFlag::NoFlag, + true => StateFlag::Flag, + } + } + #[doc = "A STATE fault has not occurred"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == StateFlag::NoFlag + } + #[doc = "A STATE fault has occurred"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == StateFlag::Flag + } +} +#[doc = "Field `STATE_FLAG` writer - STATE fault flag"] +pub type StateFlagW<'a, REG> = crate::BitWriter1C<'a, REG, StateFlag>; +impl<'a, REG> StateFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A STATE fault has not occurred"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(StateFlag::NoFlag) + } + #[doc = "A STATE fault has occurred"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(StateFlag::Flag) + } +} +#[doc = "ADDRESS fault flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum AddrFlag { + #[doc = "0: An ADDRESS fault has not occurred"] + NoFlag = 0, + #[doc = "1: An ADDRESS fault has occurred"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: AddrFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADDR_FLAG` reader - ADDRESS fault flag"] +pub type AddrFlagR = crate::BitReader; +impl AddrFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> AddrFlag { + match self.bits { + false => AddrFlag::NoFlag, + true => AddrFlag::Flag, + } + } + #[doc = "An ADDRESS fault has not occurred"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == AddrFlag::NoFlag + } + #[doc = "An ADDRESS fault has occurred"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == AddrFlag::Flag + } +} +#[doc = "Field `ADDR_FLAG` writer - ADDRESS fault flag"] +pub type AddrFlagW<'a, REG> = crate::BitWriter1C<'a, REG, AddrFlag>; +impl<'a, REG> AddrFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "An ADDRESS fault has not occurred"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(AddrFlag::NoFlag) + } + #[doc = "An ADDRESS fault has occurred"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(AddrFlag::Flag) + } +} +#[doc = "Power-on reset flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PorFlag { + #[doc = "0: A Power-on reset event has not occurred"] + NoFlag = 0, + #[doc = "1: A Power-on reset event has occurred"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PorFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POR_FLAG` reader - Power-on reset flag"] +pub type PorFlagR = crate::BitReader; +impl PorFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PorFlag { + match self.bits { + false => PorFlag::NoFlag, + true => PorFlag::Flag, + } + } + #[doc = "A Power-on reset event has not occurred"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == PorFlag::NoFlag + } + #[doc = "A Power-on reset event has occurred"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == PorFlag::Flag + } +} +#[doc = "Field `POR_FLAG` writer - Power-on reset flag"] +pub type PorFlagW<'a, REG> = crate::BitWriter1C<'a, REG, PorFlag>; +impl<'a, REG> PorFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A Power-on reset event has not occurred"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(PorFlag::NoFlag) + } + #[doc = "A Power-on reset event has occurred"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(PorFlag::Flag) + } +} +impl R { + #[doc = "Bit 0 - TIMEOUT fault flag"] + #[inline(always)] + pub fn to_flag(&self) -> ToFlagR { + ToFlagR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MISCOMPARE fault flag"] + #[inline(always)] + pub fn miscom_flag(&self) -> MiscomFlagR { + MiscomFlagR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SEQUENCE fault flag"] + #[inline(always)] + pub fn seq_flag(&self) -> SeqFlagR { + SeqFlagR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - CONTROL fault flag"] + #[inline(always)] + pub fn cnt_flag(&self) -> CntFlagR { + CntFlagR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - STATE fault flag"] + #[inline(always)] + pub fn state_flag(&self) -> StateFlagR { + StateFlagR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ADDRESS fault flag"] + #[inline(always)] + pub fn addr_flag(&self) -> AddrFlagR { + AddrFlagR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - Power-on reset flag"] + #[inline(always)] + pub fn por_flag(&self) -> PorFlagR { + PorFlagR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - TIMEOUT fault flag"] + #[inline(always)] + pub fn to_flag(&mut self) -> ToFlagW { + ToFlagW::new(self, 0) + } + #[doc = "Bit 1 - MISCOMPARE fault flag"] + #[inline(always)] + pub fn miscom_flag(&mut self) -> MiscomFlagW { + MiscomFlagW::new(self, 1) + } + #[doc = "Bit 2 - SEQUENCE fault flag"] + #[inline(always)] + pub fn seq_flag(&mut self) -> SeqFlagW { + SeqFlagW::new(self, 2) + } + #[doc = "Bit 3 - CONTROL fault flag"] + #[inline(always)] + pub fn cnt_flag(&mut self) -> CntFlagW { + CntFlagW::new(self, 3) + } + #[doc = "Bit 4 - STATE fault flag"] + #[inline(always)] + pub fn state_flag(&mut self) -> StateFlagW { + StateFlagW::new(self, 4) + } + #[doc = "Bit 5 - ADDRESS fault flag"] + #[inline(always)] + pub fn addr_flag(&mut self) -> AddrFlagW { + AddrFlagW::new(self, 5) + } + #[doc = "Bit 16 - Power-on reset flag"] + #[inline(always)] + pub fn por_flag(&mut self) -> PorFlagW { + PorFlagW::new(self, 16) + } +} +#[doc = "Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flags::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flags::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlagsSpec; +impl crate::RegisterSpec for FlagsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flags::R`](R) reader structure"] +impl crate::Readable for FlagsSpec {} +#[doc = "`write(|w| ..)` method takes [`flags::W`](W) writer structure"] +impl crate::Writable for FlagsSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0001_003f; +} +#[doc = "`reset()` method sets FLAGS to value 0x0001_0000"] +impl crate::Resettable for FlagsSpec { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/mcxa276-pac/src/cdog0/instruction_timer.rs b/mcxa276-pac/src/cdog0/instruction_timer.rs new file mode 100644 index 000000000..b0eff2d6a --- /dev/null +++ b/mcxa276-pac/src/cdog0/instruction_timer.rs @@ -0,0 +1,22 @@ +#[doc = "Register `INSTRUCTION_TIMER` reader"] +pub type R = crate::R; +#[doc = "Field `INSTIM` reader - Current value of the Instruction Timer"] +pub type InstimR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Current value of the Instruction Timer"] + #[inline(always)] + pub fn instim(&self) -> InstimR { + InstimR::new(self.bits) + } +} +#[doc = "Instruction Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`instruction_timer::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct InstructionTimerSpec; +impl crate::RegisterSpec for InstructionTimerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`instruction_timer::R`](R) reader structure"] +impl crate::Readable for InstructionTimerSpec {} +#[doc = "`reset()` method sets INSTRUCTION_TIMER to value 0xffff_ffff"] +impl crate::Resettable for InstructionTimerSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/mcxa276-pac/src/cdog0/persistent.rs b/mcxa276-pac/src/cdog0/persistent.rs new file mode 100644 index 000000000..3cce57e04 --- /dev/null +++ b/mcxa276-pac/src/cdog0/persistent.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PERSISTENT` reader"] +pub type R = crate::R; +#[doc = "Register `PERSISTENT` writer"] +pub type W = crate::W; +#[doc = "Field `PERSIS` reader - Persistent Storage"] +pub type PersisR = crate::FieldReader; +#[doc = "Field `PERSIS` writer - Persistent Storage"] +pub type PersisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Persistent Storage"] + #[inline(always)] + pub fn persis(&self) -> PersisR { + PersisR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Persistent Storage"] + #[inline(always)] + pub fn persis(&mut self) -> PersisW { + PersisW::new(self, 0) + } +} +#[doc = "Persistent Data Storage Register\n\nYou can [`read`](crate::Reg::read) this register and get [`persistent::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`persistent::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PersistentSpec; +impl crate::RegisterSpec for PersistentSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`persistent::R`](R) reader structure"] +impl crate::Readable for PersistentSpec {} +#[doc = "`write(|w| ..)` method takes [`persistent::W`](W) writer structure"] +impl crate::Writable for PersistentSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERSISTENT to value 0"] +impl crate::Resettable for PersistentSpec {} diff --git a/mcxa276-pac/src/cdog0/reload.rs b/mcxa276-pac/src/cdog0/reload.rs new file mode 100644 index 000000000..78a96ff6e --- /dev/null +++ b/mcxa276-pac/src/cdog0/reload.rs @@ -0,0 +1,37 @@ +#[doc = "Register `RELOAD` reader"] +pub type R = crate::R; +#[doc = "Register `RELOAD` writer"] +pub type W = crate::W; +#[doc = "Field `RLOAD` reader - Instruction Timer reload value"] +pub type RloadR = crate::FieldReader; +#[doc = "Field `RLOAD` writer - Instruction Timer reload value"] +pub type RloadW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Instruction Timer reload value"] + #[inline(always)] + pub fn rload(&self) -> RloadR { + RloadR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Instruction Timer reload value"] + #[inline(always)] + pub fn rload(&mut self) -> RloadW { + RloadW::new(self, 0) + } +} +#[doc = "Instruction Timer Reload Register\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ReloadSpec; +impl crate::RegisterSpec for ReloadSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`reload::R`](R) reader structure"] +impl crate::Readable for ReloadSpec {} +#[doc = "`write(|w| ..)` method takes [`reload::W`](W) writer structure"] +impl crate::Writable for ReloadSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RELOAD to value 0xffff_ffff"] +impl crate::Resettable for ReloadSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/mcxa276-pac/src/cdog0/restart.rs b/mcxa276-pac/src/cdog0/restart.rs new file mode 100644 index 000000000..5061b53c6 --- /dev/null +++ b/mcxa276-pac/src/cdog0/restart.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RESTART` writer"] +pub type W = crate::W; +#[doc = "Field `RSTRT` writer - Restart command"] +pub type RstrtW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Restart command"] + #[inline(always)] + pub fn rstrt(&mut self) -> RstrtW { + RstrtW::new(self, 0) + } +} +#[doc = "RESTART Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`restart::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RestartSpec; +impl crate::RegisterSpec for RestartSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`restart::W`](W) writer structure"] +impl crate::Writable for RestartSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RESTART to value 0"] +impl crate::Resettable for RestartSpec {} diff --git a/mcxa276-pac/src/cdog0/start.rs b/mcxa276-pac/src/cdog0/start.rs new file mode 100644 index 000000000..ea2ba9cde --- /dev/null +++ b/mcxa276-pac/src/cdog0/start.rs @@ -0,0 +1,22 @@ +#[doc = "Register `START` writer"] +pub type W = crate::W; +#[doc = "Field `STRT` writer - Start command"] +pub type StrtW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Start command"] + #[inline(always)] + pub fn strt(&mut self) -> StrtW { + StrtW::new(self, 0) + } +} +#[doc = "START Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StartSpec; +impl crate::RegisterSpec for StartSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`start::W`](W) writer structure"] +impl crate::Writable for StartSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets START to value 0"] +impl crate::Resettable for StartSpec {} diff --git a/mcxa276-pac/src/cdog0/status.rs b/mcxa276-pac/src/cdog0/status.rs new file mode 100644 index 000000000..3fa1e0604 --- /dev/null +++ b/mcxa276-pac/src/cdog0/status.rs @@ -0,0 +1,43 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `NUMTOF` reader - Number of TIMEOUT faults (FLAGS\\[TIMEOUT_FLAG\\]) since the last POR"] +pub type NumtofR = crate::FieldReader; +#[doc = "Field `NUMMISCOMPF` reader - Number of MISCOMPARE faults (FLAGS\\[MISCOMPARE_FLAG\\]) since the last POR"] +pub type NummiscompfR = crate::FieldReader; +#[doc = "Field `NUMILSEQF` reader - Number of SEQUENCE faults (FLAGS\\[SEQUENCE_FLAG\\]) since the last POR"] +pub type NumilseqfR = crate::FieldReader; +#[doc = "Field `CURST` reader - Current State"] +pub type CurstR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Number of TIMEOUT faults (FLAGS\\[TIMEOUT_FLAG\\]) since the last POR"] + #[inline(always)] + pub fn numtof(&self) -> NumtofR { + NumtofR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Number of MISCOMPARE faults (FLAGS\\[MISCOMPARE_FLAG\\]) since the last POR"] + #[inline(always)] + pub fn nummiscompf(&self) -> NummiscompfR { + NummiscompfR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Number of SEQUENCE faults (FLAGS\\[SEQUENCE_FLAG\\]) since the last POR"] + #[inline(always)] + pub fn numilseqf(&self) -> NumilseqfR { + NumilseqfR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 28:31 - Current State"] + #[inline(always)] + pub fn curst(&self) -> CurstR { + CurstR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Status 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0x5000_0000"] +impl crate::Resettable for StatusSpec { + const RESET_VALUE: u32 = 0x5000_0000; +} diff --git a/mcxa276-pac/src/cdog0/status2.rs b/mcxa276-pac/src/cdog0/status2.rs new file mode 100644 index 000000000..57b68032f --- /dev/null +++ b/mcxa276-pac/src/cdog0/status2.rs @@ -0,0 +1,34 @@ +#[doc = "Register `STATUS2` reader"] +pub type R = crate::R; +#[doc = "Field `NUMCNTF` reader - Number of CONTROL faults (FLAGS\\[CONTROL_FLAG\\]) since the last POR"] +pub type NumcntfR = crate::FieldReader; +#[doc = "Field `NUMILLSTF` reader - Number of STATE faults (FLAGS\\[STATE_FLAG\\]) since the last POR"] +pub type NumillstfR = crate::FieldReader; +#[doc = "Field `NUMILLA` reader - Number of ADDRESS faults (FLAGS\\[ADDR_FLAG\\]) since the last POR"] +pub type NumillaR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Number of CONTROL faults (FLAGS\\[CONTROL_FLAG\\]) since the last POR"] + #[inline(always)] + pub fn numcntf(&self) -> NumcntfR { + NumcntfR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Number of STATE faults (FLAGS\\[STATE_FLAG\\]) since the last POR"] + #[inline(always)] + pub fn numillstf(&self) -> NumillstfR { + NumillstfR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Number of ADDRESS faults (FLAGS\\[ADDR_FLAG\\]) since the last POR"] + #[inline(always)] + pub fn numilla(&self) -> NumillaR { + NumillaR::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[doc = "Status 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Status2Spec; +impl crate::RegisterSpec for Status2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status2::R`](R) reader structure"] +impl crate::Readable for Status2Spec {} +#[doc = "`reset()` method sets STATUS2 to value 0"] +impl crate::Resettable for Status2Spec {} diff --git a/mcxa276-pac/src/cdog0/stop.rs b/mcxa276-pac/src/cdog0/stop.rs new file mode 100644 index 000000000..dedaaac8d --- /dev/null +++ b/mcxa276-pac/src/cdog0/stop.rs @@ -0,0 +1,22 @@ +#[doc = "Register `STOP` writer"] +pub type W = crate::W; +#[doc = "Field `STP` writer - Stop command"] +pub type StpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Stop command"] + #[inline(always)] + pub fn stp(&mut self) -> StpW { + StpW::new(self, 0) + } +} +#[doc = "STOP Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stop::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StopSpec; +impl crate::RegisterSpec for StopSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`stop::W`](W) writer structure"] +impl crate::Writable for StopSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STOP to value 0"] +impl crate::Resettable for StopSpec {} diff --git a/mcxa276-pac/src/cdog0/sub.rs b/mcxa276-pac/src/cdog0/sub.rs new file mode 100644 index 000000000..e8351bdc2 --- /dev/null +++ b/mcxa276-pac/src/cdog0/sub.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SUB` writer"] +pub type W = crate::W; +#[doc = "Field `SB` writer - Subtract Write Value"] +pub type SbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Subtract Write Value"] + #[inline(always)] + pub fn sb(&mut self) -> SbW { + SbW::new(self, 0) + } +} +#[doc = "SUB Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SubSpec; +impl crate::RegisterSpec for SubSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`sub::W`](W) writer structure"] +impl crate::Writable for SubSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SUB to value 0"] +impl crate::Resettable for SubSpec {} diff --git a/mcxa276-pac/src/cdog0/sub1.rs b/mcxa276-pac/src/cdog0/sub1.rs new file mode 100644 index 000000000..61ae47103 --- /dev/null +++ b/mcxa276-pac/src/cdog0/sub1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SUB1` writer"] +pub type W = crate::W; +#[doc = "Field `SB1` writer - Subtract 1"] +pub type Sb1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Subtract 1"] + #[inline(always)] + pub fn sb1(&mut self) -> Sb1W { + Sb1W::new(self, 0) + } +} +#[doc = "SUB1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sub1Spec; +impl crate::RegisterSpec for Sub1Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`sub1::W`](W) writer structure"] +impl crate::Writable for Sub1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SUB1 to value 0"] +impl crate::Resettable for Sub1Spec {} diff --git a/mcxa276-pac/src/cdog0/sub16.rs b/mcxa276-pac/src/cdog0/sub16.rs new file mode 100644 index 000000000..be61a4821 --- /dev/null +++ b/mcxa276-pac/src/cdog0/sub16.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SUB16` writer"] +pub type W = crate::W; +#[doc = "Field `SB16` writer - Subtract 16"] +pub type Sb16W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Subtract 16"] + #[inline(always)] + pub fn sb16(&mut self) -> Sb16W { + Sb16W::new(self, 0) + } +} +#[doc = "SUB16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub16::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sub16Spec; +impl crate::RegisterSpec for Sub16Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`sub16::W`](W) writer structure"] +impl crate::Writable for Sub16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SUB16 to value 0"] +impl crate::Resettable for Sub16Spec {} diff --git a/mcxa276-pac/src/cdog0/sub256.rs b/mcxa276-pac/src/cdog0/sub256.rs new file mode 100644 index 000000000..68a53c4ce --- /dev/null +++ b/mcxa276-pac/src/cdog0/sub256.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SUB256` writer"] +pub type W = crate::W; +#[doc = "Field `SB256` writer - Subtract 256"] +pub type Sb256W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Subtract 256"] + #[inline(always)] + pub fn sb256(&mut self) -> Sb256W { + Sb256W::new(self, 0) + } +} +#[doc = "SUB256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub256::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sub256Spec; +impl crate::RegisterSpec for Sub256Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`sub256::W`](W) writer structure"] +impl crate::Writable for Sub256Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SUB256 to value 0"] +impl crate::Resettable for Sub256Spec {} diff --git a/mcxa276-pac/src/cmc.rs b/mcxa276-pac/src/cmc.rs new file mode 100644 index 000000000..cb40e7748 --- /dev/null +++ b/mcxa276-pac/src/cmc.rs @@ -0,0 +1,189 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x0c], + ckctrl: Ckctrl, + ckstat: Ckstat, + pmprot: Pmprot, + gpmctrl: Gpmctrl, + pmctrlmain: Pmctrlmain, + _reserved6: [u8; 0x5c], + srs: Srs, + rpc: Rpc, + ssrs: Ssrs, + srie: Srie, + srif: Srif, + _reserved11: [u8; 0x0c], + mr0: Mr0, + _reserved12: [u8; 0x0c], + fm0: Fm0, + _reserved13: [u8; 0x2c], + flashcr: Flashcr, + _reserved14: [u8; 0x2c], + corectl: Corectl, + _reserved15: [u8; 0x0c], + dbgctl: Dbgctl, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x10 - Clock Control"] + #[inline(always)] + pub const fn ckctrl(&self) -> &Ckctrl { + &self.ckctrl + } + #[doc = "0x14 - Clock Status"] + #[inline(always)] + pub const fn ckstat(&self) -> &Ckstat { + &self.ckstat + } + #[doc = "0x18 - Power Mode Protection"] + #[inline(always)] + pub const fn pmprot(&self) -> &Pmprot { + &self.pmprot + } + #[doc = "0x1c - Global Power Mode Control"] + #[inline(always)] + pub const fn gpmctrl(&self) -> &Gpmctrl { + &self.gpmctrl + } + #[doc = "0x20 - Power Mode Control"] + #[inline(always)] + pub const fn pmctrlmain(&self) -> &Pmctrlmain { + &self.pmctrlmain + } + #[doc = "0x80 - System Reset Status"] + #[inline(always)] + pub const fn srs(&self) -> &Srs { + &self.srs + } + #[doc = "0x84 - Reset Pin Control"] + #[inline(always)] + pub const fn rpc(&self) -> &Rpc { + &self.rpc + } + #[doc = "0x88 - Sticky System Reset Status"] + #[inline(always)] + pub const fn ssrs(&self) -> &Ssrs { + &self.ssrs + } + #[doc = "0x8c - System Reset Interrupt Enable"] + #[inline(always)] + pub const fn srie(&self) -> &Srie { + &self.srie + } + #[doc = "0x90 - System Reset Interrupt Flag"] + #[inline(always)] + pub const fn srif(&self) -> &Srif { + &self.srif + } + #[doc = "0xa0 - Mode"] + #[inline(always)] + pub const fn mr0(&self) -> &Mr0 { + &self.mr0 + } + #[doc = "0xb0 - Force Mode"] + #[inline(always)] + pub const fn fm0(&self) -> &Fm0 { + &self.fm0 + } + #[doc = "0xe0 - Flash Control"] + #[inline(always)] + pub const fn flashcr(&self) -> &Flashcr { + &self.flashcr + } + #[doc = "0x110 - Core Control"] + #[inline(always)] + pub const fn corectl(&self) -> &Corectl { + &self.corectl + } + #[doc = "0x120 - Debug Control"] + #[inline(always)] + pub const fn dbgctl(&self) -> &Dbgctl { + &self.dbgctl + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "CKCTRL (rw) register accessor: Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ckctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ckctrl`] module"] +#[doc(alias = "CKCTRL")] +pub type Ckctrl = crate::Reg; +#[doc = "Clock Control"] +pub mod ckctrl; +#[doc = "CKSTAT (rw) register accessor: Clock Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ckstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ckstat`] module"] +#[doc(alias = "CKSTAT")] +pub type Ckstat = crate::Reg; +#[doc = "Clock Status"] +pub mod ckstat; +#[doc = "PMPROT (rw) register accessor: Power Mode Protection\n\nYou can [`read`](crate::Reg::read) this register and get [`pmprot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmprot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmprot`] module"] +#[doc(alias = "PMPROT")] +pub type Pmprot = crate::Reg; +#[doc = "Power Mode Protection"] +pub mod pmprot; +#[doc = "GPMCTRL (rw) register accessor: Global Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gpmctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpmctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpmctrl`] module"] +#[doc(alias = "GPMCTRL")] +pub type Gpmctrl = crate::Reg; +#[doc = "Global Power Mode Control"] +pub mod gpmctrl; +#[doc = "PMCTRLMAIN (rw) register accessor: Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pmctrlmain::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmctrlmain::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmctrlmain`] module"] +#[doc(alias = "PMCTRLMAIN")] +pub type Pmctrlmain = crate::Reg; +#[doc = "Power Mode Control"] +pub mod pmctrlmain; +#[doc = "SRS (r) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`srs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srs`] module"] +#[doc(alias = "SRS")] +pub type Srs = crate::Reg; +#[doc = "System Reset Status"] +pub mod srs; +#[doc = "RPC (rw) register accessor: Reset Pin Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rpc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpc`] module"] +#[doc(alias = "RPC")] +pub type Rpc = crate::Reg; +#[doc = "Reset Pin Control"] +pub mod rpc; +#[doc = "SSRS (rw) register accessor: Sticky System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssrs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssrs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssrs`] module"] +#[doc(alias = "SSRS")] +pub type Ssrs = crate::Reg; +#[doc = "Sticky System Reset Status"] +pub mod ssrs; +#[doc = "SRIE (rw) register accessor: System Reset Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`srie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srie`] module"] +#[doc(alias = "SRIE")] +pub type Srie = crate::Reg; +#[doc = "System Reset Interrupt Enable"] +pub mod srie; +#[doc = "SRIF (rw) register accessor: System Reset Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`srif::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srif::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srif`] module"] +#[doc(alias = "SRIF")] +pub type Srif = crate::Reg; +#[doc = "System Reset Interrupt Flag"] +pub mod srif; +#[doc = "MR0 (rw) register accessor: Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr0`] module"] +#[doc(alias = "MR0")] +pub type Mr0 = crate::Reg; +#[doc = "Mode"] +pub mod mr0; +#[doc = "FM0 (rw) register accessor: Force Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`fm0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fm0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fm0`] module"] +#[doc(alias = "FM0")] +pub type Fm0 = crate::Reg; +#[doc = "Force Mode"] +pub mod fm0; +#[doc = "FLASHCR (rw) register accessor: Flash Control\n\nYou can [`read`](crate::Reg::read) this register and get [`flashcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashcr`] module"] +#[doc(alias = "FLASHCR")] +pub type Flashcr = crate::Reg; +#[doc = "Flash Control"] +pub mod flashcr; +#[doc = "CORECTL (rw) register accessor: Core Control\n\nYou can [`read`](crate::Reg::read) this register and get [`corectl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corectl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@corectl`] module"] +#[doc(alias = "CORECTL")] +pub type Corectl = crate::Reg; +#[doc = "Core Control"] +pub mod corectl; +#[doc = "DBGCTL (rw) register accessor: Debug Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dbgctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbgctl`] module"] +#[doc(alias = "DBGCTL")] +pub type Dbgctl = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctl; diff --git a/mcxa276-pac/src/cmc/ckctrl.rs b/mcxa276-pac/src/cmc/ckctrl.rs new file mode 100644 index 000000000..32c829009 --- /dev/null +++ b/mcxa276-pac/src/cmc/ckctrl.rs @@ -0,0 +1,167 @@ +#[doc = "Register `CKCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CKCTRL` writer"] +pub type W = crate::W; +#[doc = "Clocking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ckmode { + #[doc = "0: Core clock is on"] + Ckmode0000 = 0, + #[doc = "1: Core clock is off"] + Ckmode0001 = 1, + #[doc = "15: Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] + Ckmode1111 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ckmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ckmode { + type Ux = u8; +} +impl crate::IsEnum for Ckmode {} +#[doc = "Field `CKMODE` reader - Clocking Mode"] +pub type CkmodeR = crate::FieldReader; +impl CkmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ckmode::Ckmode0000), + 1 => Some(Ckmode::Ckmode0001), + 15 => Some(Ckmode::Ckmode1111), + _ => None, + } + } + #[doc = "Core clock is on"] + #[inline(always)] + pub fn is_ckmode0000(&self) -> bool { + *self == Ckmode::Ckmode0000 + } + #[doc = "Core clock is off"] + #[inline(always)] + pub fn is_ckmode0001(&self) -> bool { + *self == Ckmode::Ckmode0001 + } + #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] + #[inline(always)] + pub fn is_ckmode1111(&self) -> bool { + *self == Ckmode::Ckmode1111 + } +} +#[doc = "Field `CKMODE` writer - Clocking Mode"] +pub type CkmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ckmode>; +impl<'a, REG> CkmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Core clock is on"] + #[inline(always)] + pub fn ckmode0000(self) -> &'a mut crate::W { + self.variant(Ckmode::Ckmode0000) + } + #[doc = "Core clock is off"] + #[inline(always)] + pub fn ckmode0001(self) -> &'a mut crate::W { + self.variant(Ckmode::Ckmode0001) + } + #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] + #[inline(always)] + pub fn ckmode1111(self) -> &'a mut crate::W { + self.variant(Ckmode::Ckmode1111) + } +} +#[doc = "Lock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: Allowed"] + Disabled = 0, + #[doc = "1: Blocked"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - Lock"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Disabled, + true => Lock::Enabled, + } + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lock::Disabled + } + #[doc = "Blocked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lock::Enabled + } +} +#[doc = "Field `LOCK` writer - Lock"] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Allowed"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lock::Disabled) + } + #[doc = "Blocked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lock::Enabled) + } +} +impl R { + #[doc = "Bits 0:3 - Clocking Mode"] + #[inline(always)] + pub fn ckmode(&self) -> CkmodeR { + CkmodeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 31 - Lock"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Clocking Mode"] + #[inline(always)] + pub fn ckmode(&mut self) -> CkmodeW { + CkmodeW::new(self, 0) + } + #[doc = "Bit 31 - Lock"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 31) + } +} +#[doc = "Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ckctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CkctrlSpec; +impl crate::RegisterSpec for CkctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ckctrl::R`](R) reader structure"] +impl crate::Readable for CkctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ckctrl::W`](W) writer structure"] +impl crate::Writable for CkctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CKCTRL to value 0"] +impl crate::Resettable for CkctrlSpec {} diff --git a/mcxa276-pac/src/cmc/ckstat.rs b/mcxa276-pac/src/cmc/ckstat.rs new file mode 100644 index 000000000..50cc409bb --- /dev/null +++ b/mcxa276-pac/src/cmc/ckstat.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CKSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `CKSTAT` writer"] +pub type W = crate::W; +#[doc = "Low Power Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ckmode { + #[doc = "0: Core clock is on"] + Ckmode0000 = 0, + #[doc = "1: Core clock is off"] + Ckmode0001 = 1, + #[doc = "15: Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] + Ckmode1111 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ckmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ckmode { + type Ux = u8; +} +impl crate::IsEnum for Ckmode {} +#[doc = "Field `CKMODE` reader - Low Power Status"] +pub type CkmodeR = crate::FieldReader; +impl CkmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ckmode::Ckmode0000), + 1 => Some(Ckmode::Ckmode0001), + 15 => Some(Ckmode::Ckmode1111), + _ => None, + } + } + #[doc = "Core clock is on"] + #[inline(always)] + pub fn is_ckmode0000(&self) -> bool { + *self == Ckmode::Ckmode0000 + } + #[doc = "Core clock is off"] + #[inline(always)] + pub fn is_ckmode0001(&self) -> bool { + *self == Ckmode::Ckmode0001 + } + #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] + #[inline(always)] + pub fn is_ckmode1111(&self) -> bool { + *self == Ckmode::Ckmode1111 + } +} +#[doc = "Field `WAKEUP` reader - Wake-up Source"] +pub type WakeupR = crate::FieldReader; +#[doc = "Clock Status Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Valid { + #[doc = "0: Core clock not gated"] + Disabled = 0, + #[doc = "1: Core clock was gated due to Low-Power mode entry"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Valid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VALID` reader - Clock Status Valid"] +pub type ValidR = crate::BitReader; +impl ValidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Valid { + match self.bits { + false => Valid::Disabled, + true => Valid::Enabled, + } + } + #[doc = "Core clock not gated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Valid::Disabled + } + #[doc = "Core clock was gated due to Low-Power mode entry"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Valid::Enabled + } +} +#[doc = "Field `VALID` writer - Clock Status Valid"] +pub type ValidW<'a, REG> = crate::BitWriter1C<'a, REG, Valid>; +impl<'a, REG> ValidW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Core clock not gated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Valid::Disabled) + } + #[doc = "Core clock was gated due to Low-Power mode entry"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Valid::Enabled) + } +} +impl R { + #[doc = "Bits 0:3 - Low Power Status"] + #[inline(always)] + pub fn ckmode(&self) -> CkmodeR { + CkmodeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:15 - Wake-up Source"] + #[inline(always)] + pub fn wakeup(&self) -> WakeupR { + WakeupR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 31 - Clock Status Valid"] + #[inline(always)] + pub fn valid(&self) -> ValidR { + ValidR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 31 - Clock Status Valid"] + #[inline(always)] + pub fn valid(&mut self) -> ValidW { + ValidW::new(self, 31) + } +} +#[doc = "Clock Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ckstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CkstatSpec; +impl crate::RegisterSpec for CkstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ckstat::R`](R) reader structure"] +impl crate::Readable for CkstatSpec {} +#[doc = "`write(|w| ..)` method takes [`ckstat::W`](W) writer structure"] +impl crate::Writable for CkstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000; +} +#[doc = "`reset()` method sets CKSTAT to value 0"] +impl crate::Resettable for CkstatSpec {} diff --git a/mcxa276-pac/src/cmc/corectl.rs b/mcxa276-pac/src/cmc/corectl.rs new file mode 100644 index 000000000..693a9681d --- /dev/null +++ b/mcxa276-pac/src/cmc/corectl.rs @@ -0,0 +1,84 @@ +#[doc = "Register `CORECTL` reader"] +pub type R = crate::R; +#[doc = "Register `CORECTL` writer"] +pub type W = crate::W; +#[doc = "Non-maskable Pin Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npie { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPIE` reader - Non-maskable Pin Interrupt Enable"] +pub type NpieR = crate::BitReader; +impl NpieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npie { + match self.bits { + false => Npie::Disabled, + true => Npie::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Npie::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Npie::Enabled + } +} +#[doc = "Field `NPIE` writer - Non-maskable Pin Interrupt Enable"] +pub type NpieW<'a, REG> = crate::BitWriter<'a, REG, Npie>; +impl<'a, REG> NpieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Npie::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Npie::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Non-maskable Pin Interrupt Enable"] + #[inline(always)] + pub fn npie(&self) -> NpieR { + NpieR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Non-maskable Pin Interrupt Enable"] + #[inline(always)] + pub fn npie(&mut self) -> NpieW { + NpieW::new(self, 0) + } +} +#[doc = "Core Control\n\nYou can [`read`](crate::Reg::read) this register and get [`corectl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corectl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CorectlSpec; +impl crate::RegisterSpec for CorectlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`corectl::R`](R) reader structure"] +impl crate::Readable for CorectlSpec {} +#[doc = "`write(|w| ..)` method takes [`corectl::W`](W) writer structure"] +impl crate::Writable for CorectlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CORECTL to value 0"] +impl crate::Resettable for CorectlSpec {} diff --git a/mcxa276-pac/src/cmc/dbgctl.rs b/mcxa276-pac/src/cmc/dbgctl.rs new file mode 100644 index 000000000..13a06527c --- /dev/null +++ b/mcxa276-pac/src/cmc/dbgctl.rs @@ -0,0 +1,84 @@ +#[doc = "Register `DBGCTL` reader"] +pub type R = crate::R; +#[doc = "Register `DBGCTL` writer"] +pub type W = crate::W; +#[doc = "Sleep Or Debug\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sod { + #[doc = "0: Remains enabled"] + Disabled = 0, + #[doc = "1: Disabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOD` reader - Sleep Or Debug"] +pub type SodR = crate::BitReader; +impl SodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sod { + match self.bits { + false => Sod::Disabled, + true => Sod::Enabled, + } + } + #[doc = "Remains enabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sod::Disabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sod::Enabled + } +} +#[doc = "Field `SOD` writer - Sleep Or Debug"] +pub type SodW<'a, REG> = crate::BitWriter<'a, REG, Sod>; +impl<'a, REG> SodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Remains enabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sod::Disabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sod::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Sleep Or Debug"] + #[inline(always)] + pub fn sod(&self) -> SodR { + SodR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Sleep Or Debug"] + #[inline(always)] + pub fn sod(&mut self) -> SodW { + SodW::new(self, 0) + } +} +#[doc = "Debug Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dbgctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DbgctlSpec; +impl crate::RegisterSpec for DbgctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbgctl::R`](R) reader structure"] +impl crate::Readable for DbgctlSpec {} +#[doc = "`write(|w| ..)` method takes [`dbgctl::W`](W) writer structure"] +impl crate::Writable for DbgctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DBGCTL to value 0"] +impl crate::Resettable for DbgctlSpec {} diff --git a/mcxa276-pac/src/cmc/flashcr.rs b/mcxa276-pac/src/cmc/flashcr.rs new file mode 100644 index 000000000..c196aaaa4 --- /dev/null +++ b/mcxa276-pac/src/cmc/flashcr.rs @@ -0,0 +1,210 @@ +#[doc = "Register `FLASHCR` reader"] +pub type R = crate::R; +#[doc = "Register `FLASHCR` writer"] +pub type W = crate::W; +#[doc = "Flash Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flashdis { + #[doc = "0: No effect"] + Disabled = 0, + #[doc = "1: Flash memory is disabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flashdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASHDIS` reader - Flash Disable"] +pub type FlashdisR = crate::BitReader; +impl FlashdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flashdis { + match self.bits { + false => Flashdis::Disabled, + true => Flashdis::Enabled, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flashdis::Disabled + } + #[doc = "Flash memory is disabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flashdis::Enabled + } +} +#[doc = "Field `FLASHDIS` writer - Flash Disable"] +pub type FlashdisW<'a, REG> = crate::BitWriter<'a, REG, Flashdis>; +impl<'a, REG> FlashdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flashdis::Disabled) + } + #[doc = "Flash memory is disabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flashdis::Enabled) + } +} +#[doc = "Flash Doze\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flashdoze { + #[doc = "0: No effect"] + Disabled = 0, + #[doc = "1: Flash memory is disabled when core is sleeping (CKMODE > 0)"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flashdoze) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASHDOZE` reader - Flash Doze"] +pub type FlashdozeR = crate::BitReader; +impl FlashdozeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flashdoze { + match self.bits { + false => Flashdoze::Disabled, + true => Flashdoze::Enabled, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flashdoze::Disabled + } + #[doc = "Flash memory is disabled when core is sleeping (CKMODE > 0)"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flashdoze::Enabled + } +} +#[doc = "Field `FLASHDOZE` writer - Flash Doze"] +pub type FlashdozeW<'a, REG> = crate::BitWriter<'a, REG, Flashdoze>; +impl<'a, REG> FlashdozeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flashdoze::Disabled) + } + #[doc = "Flash memory is disabled when core is sleeping (CKMODE > 0)"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flashdoze::Enabled) + } +} +#[doc = "Flash Wake\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flashwake { + #[doc = "0: No effect"] + Disabled = 0, + #[doc = "1: Flash memory is not disabled during flash memory accesses"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flashwake) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASHWAKE` reader - Flash Wake"] +pub type FlashwakeR = crate::BitReader; +impl FlashwakeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flashwake { + match self.bits { + false => Flashwake::Disabled, + true => Flashwake::Enabled, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flashwake::Disabled + } + #[doc = "Flash memory is not disabled during flash memory accesses"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flashwake::Enabled + } +} +#[doc = "Field `FLASHWAKE` writer - Flash Wake"] +pub type FlashwakeW<'a, REG> = crate::BitWriter<'a, REG, Flashwake>; +impl<'a, REG> FlashwakeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flashwake::Disabled) + } + #[doc = "Flash memory is not disabled during flash memory accesses"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flashwake::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Flash Disable"] + #[inline(always)] + pub fn flashdis(&self) -> FlashdisR { + FlashdisR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Flash Doze"] + #[inline(always)] + pub fn flashdoze(&self) -> FlashdozeR { + FlashdozeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Flash Wake"] + #[inline(always)] + pub fn flashwake(&self) -> FlashwakeR { + FlashwakeR::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flash Disable"] + #[inline(always)] + pub fn flashdis(&mut self) -> FlashdisW { + FlashdisW::new(self, 0) + } + #[doc = "Bit 1 - Flash Doze"] + #[inline(always)] + pub fn flashdoze(&mut self) -> FlashdozeW { + FlashdozeW::new(self, 1) + } + #[doc = "Bit 2 - Flash Wake"] + #[inline(always)] + pub fn flashwake(&mut self) -> FlashwakeW { + FlashwakeW::new(self, 2) + } +} +#[doc = "Flash Control\n\nYou can [`read`](crate::Reg::read) this register and get [`flashcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlashcrSpec; +impl crate::RegisterSpec for FlashcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flashcr::R`](R) reader structure"] +impl crate::Readable for FlashcrSpec {} +#[doc = "`write(|w| ..)` method takes [`flashcr::W`](W) writer structure"] +impl crate::Writable for FlashcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FLASHCR to value 0"] +impl crate::Resettable for FlashcrSpec {} diff --git a/mcxa276-pac/src/cmc/fm0.rs b/mcxa276-pac/src/cmc/fm0.rs new file mode 100644 index 000000000..21b886d9e --- /dev/null +++ b/mcxa276-pac/src/cmc/fm0.rs @@ -0,0 +1,84 @@ +#[doc = "Register `FM0` reader"] +pub type R = crate::R; +#[doc = "Register `FM0` writer"] +pub type W = crate::W; +#[doc = "Boot Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Forcecfg { + #[doc = "0: No effect"] + Disabled = 0, + #[doc = "1: Asserts"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Forcecfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FORCECFG` reader - Boot Configuration"] +pub type ForcecfgR = crate::BitReader; +impl ForcecfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Forcecfg { + match self.bits { + false => Forcecfg::Disabled, + true => Forcecfg::Enabled, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Forcecfg::Disabled + } + #[doc = "Asserts"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Forcecfg::Enabled + } +} +#[doc = "Field `FORCECFG` writer - Boot Configuration"] +pub type ForcecfgW<'a, REG> = crate::BitWriter<'a, REG, Forcecfg>; +impl<'a, REG> ForcecfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Forcecfg::Disabled) + } + #[doc = "Asserts"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Forcecfg::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Boot Configuration"] + #[inline(always)] + pub fn forcecfg(&self) -> ForcecfgR { + ForcecfgR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Boot Configuration"] + #[inline(always)] + pub fn forcecfg(&mut self) -> ForcecfgW { + ForcecfgW::new(self, 0) + } +} +#[doc = "Force Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`fm0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fm0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fm0Spec; +impl crate::RegisterSpec for Fm0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fm0::R`](R) reader structure"] +impl crate::Readable for Fm0Spec {} +#[doc = "`write(|w| ..)` method takes [`fm0::W`](W) writer structure"] +impl crate::Writable for Fm0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FM0 to value 0"] +impl crate::Resettable for Fm0Spec {} diff --git a/mcxa276-pac/src/cmc/gpmctrl.rs b/mcxa276-pac/src/cmc/gpmctrl.rs new file mode 100644 index 000000000..a9061e1d1 --- /dev/null +++ b/mcxa276-pac/src/cmc/gpmctrl.rs @@ -0,0 +1,35 @@ +#[doc = "Register `GPMCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `GPMCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LPMODE` reader - Low-Power Mode"] +pub type LpmodeR = crate::FieldReader; +#[doc = "Field `LPMODE` writer - Low-Power Mode"] +pub type LpmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Low-Power Mode"] + #[inline(always)] + pub fn lpmode(&self) -> LpmodeR { + LpmodeR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Low-Power Mode"] + #[inline(always)] + pub fn lpmode(&mut self) -> LpmodeW { + LpmodeW::new(self, 0) + } +} +#[doc = "Global Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gpmctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpmctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpmctrlSpec; +impl crate::RegisterSpec for GpmctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpmctrl::R`](R) reader structure"] +impl crate::Readable for GpmctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`gpmctrl::W`](W) writer structure"] +impl crate::Writable for GpmctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPMCTRL to value 0"] +impl crate::Resettable for GpmctrlSpec {} diff --git a/mcxa276-pac/src/cmc/mr0.rs b/mcxa276-pac/src/cmc/mr0.rs new file mode 100644 index 000000000..980f4ba52 --- /dev/null +++ b/mcxa276-pac/src/cmc/mr0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `MR0` reader"] +pub type R = crate::R; +#[doc = "Register `MR0` writer"] +pub type W = crate::W; +#[doc = "Field `ISPMODE_n` reader - In System Programming Mode"] +pub type IspmodeNR = crate::BitReader; +#[doc = "Field `ISPMODE_n` writer - In System Programming Mode"] +pub type IspmodeNW<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0 - In System Programming Mode"] + #[inline(always)] + pub fn ispmode_n(&self) -> IspmodeNR { + IspmodeNR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - In System Programming Mode"] + #[inline(always)] + pub fn ispmode_n(&mut self) -> IspmodeNW { + IspmodeNW::new(self, 0) + } +} +#[doc = "Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mr0Spec; +impl crate::RegisterSpec for Mr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mr0::R`](R) reader structure"] +impl crate::Readable for Mr0Spec {} +#[doc = "`write(|w| ..)` method takes [`mr0::W`](W) writer structure"] +impl crate::Writable for Mr0Spec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets MR0 to value 0"] +impl crate::Resettable for Mr0Spec {} diff --git a/mcxa276-pac/src/cmc/pmctrlmain.rs b/mcxa276-pac/src/cmc/pmctrlmain.rs new file mode 100644 index 000000000..6d5bd0c57 --- /dev/null +++ b/mcxa276-pac/src/cmc/pmctrlmain.rs @@ -0,0 +1,117 @@ +#[doc = "Register `PMCTRLMAIN` reader"] +pub type R = crate::R; +#[doc = "Register `PMCTRLMAIN` writer"] +pub type W = crate::W; +#[doc = "Low-Power Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Lpmode { + #[doc = "0: Active/Sleep"] + Lpmode0000 = 0, + #[doc = "1: Deep Sleep"] + Lpmode0001 = 1, + #[doc = "3: Power Down"] + Lpmode0011 = 3, + #[doc = "15: Deep-Power Down"] + Lpmode1111 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Lpmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Lpmode { + type Ux = u8; +} +impl crate::IsEnum for Lpmode {} +#[doc = "Field `LPMODE` reader - Low-Power Mode"] +pub type LpmodeR = crate::FieldReader; +impl LpmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Lpmode::Lpmode0000), + 1 => Some(Lpmode::Lpmode0001), + 3 => Some(Lpmode::Lpmode0011), + 15 => Some(Lpmode::Lpmode1111), + _ => None, + } + } + #[doc = "Active/Sleep"] + #[inline(always)] + pub fn is_lpmode0000(&self) -> bool { + *self == Lpmode::Lpmode0000 + } + #[doc = "Deep Sleep"] + #[inline(always)] + pub fn is_lpmode0001(&self) -> bool { + *self == Lpmode::Lpmode0001 + } + #[doc = "Power Down"] + #[inline(always)] + pub fn is_lpmode0011(&self) -> bool { + *self == Lpmode::Lpmode0011 + } + #[doc = "Deep-Power Down"] + #[inline(always)] + pub fn is_lpmode1111(&self) -> bool { + *self == Lpmode::Lpmode1111 + } +} +#[doc = "Field `LPMODE` writer - Low-Power Mode"] +pub type LpmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Lpmode>; +impl<'a, REG> LpmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Active/Sleep"] + #[inline(always)] + pub fn lpmode0000(self) -> &'a mut crate::W { + self.variant(Lpmode::Lpmode0000) + } + #[doc = "Deep Sleep"] + #[inline(always)] + pub fn lpmode0001(self) -> &'a mut crate::W { + self.variant(Lpmode::Lpmode0001) + } + #[doc = "Power Down"] + #[inline(always)] + pub fn lpmode0011(self) -> &'a mut crate::W { + self.variant(Lpmode::Lpmode0011) + } + #[doc = "Deep-Power Down"] + #[inline(always)] + pub fn lpmode1111(self) -> &'a mut crate::W { + self.variant(Lpmode::Lpmode1111) + } +} +impl R { + #[doc = "Bits 0:3 - Low-Power Mode"] + #[inline(always)] + pub fn lpmode(&self) -> LpmodeR { + LpmodeR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Low-Power Mode"] + #[inline(always)] + pub fn lpmode(&mut self) -> LpmodeW { + LpmodeW::new(self, 0) + } +} +#[doc = "Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pmctrlmain::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmctrlmain::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PmctrlmainSpec; +impl crate::RegisterSpec for PmctrlmainSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmctrlmain::R`](R) reader structure"] +impl crate::Readable for PmctrlmainSpec {} +#[doc = "`write(|w| ..)` method takes [`pmctrlmain::W`](W) writer structure"] +impl crate::Writable for PmctrlmainSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PMCTRLMAIN to value 0"] +impl crate::Resettable for PmctrlmainSpec {} diff --git a/mcxa276-pac/src/cmc/pmprot.rs b/mcxa276-pac/src/cmc/pmprot.rs new file mode 100644 index 000000000..8ceca76df --- /dev/null +++ b/mcxa276-pac/src/cmc/pmprot.rs @@ -0,0 +1,336 @@ +#[doc = "Register `PMPROT` reader"] +pub type R = crate::R; +#[doc = "Register `PMPROT` writer"] +pub type W = crate::W; +#[doc = "Low-Power Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Lpmode { + #[doc = "0: Not allowed"] + Disabled = 0, + #[doc = "1: Allowed"] + En = 1, + #[doc = "2: Allowed"] + En1 = 2, + #[doc = "3: Allowed"] + En2 = 3, + #[doc = "4: Allowed"] + En3 = 4, + #[doc = "5: Allowed"] + En4 = 5, + #[doc = "6: Allowed"] + En5 = 6, + #[doc = "7: Allowed"] + En6 = 7, + #[doc = "8: Allowed"] + En7 = 8, + #[doc = "9: Allowed"] + En8 = 9, + #[doc = "10: Allowed"] + En9 = 10, + #[doc = "11: Allowed"] + En10 = 11, + #[doc = "12: Allowed"] + En11 = 12, + #[doc = "13: Allowed"] + En12 = 13, + #[doc = "14: Allowed"] + En13 = 14, + #[doc = "15: Allowed"] + En14 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Lpmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Lpmode { + type Ux = u8; +} +impl crate::IsEnum for Lpmode {} +#[doc = "Field `LPMODE` reader - Low-Power Mode"] +pub type LpmodeR = crate::FieldReader; +impl LpmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpmode { + match self.bits { + 0 => Lpmode::Disabled, + 1 => Lpmode::En, + 2 => Lpmode::En1, + 3 => Lpmode::En2, + 4 => Lpmode::En3, + 5 => Lpmode::En4, + 6 => Lpmode::En5, + 7 => Lpmode::En6, + 8 => Lpmode::En7, + 9 => Lpmode::En8, + 10 => Lpmode::En9, + 11 => Lpmode::En10, + 12 => Lpmode::En11, + 13 => Lpmode::En12, + 14 => Lpmode::En13, + 15 => Lpmode::En14, + _ => unreachable!(), + } + } + #[doc = "Not allowed"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpmode::Disabled + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en(&self) -> bool { + *self == Lpmode::En + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en1(&self) -> bool { + *self == Lpmode::En1 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en2(&self) -> bool { + *self == Lpmode::En2 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en3(&self) -> bool { + *self == Lpmode::En3 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en4(&self) -> bool { + *self == Lpmode::En4 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en5(&self) -> bool { + *self == Lpmode::En5 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en6(&self) -> bool { + *self == Lpmode::En6 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en7(&self) -> bool { + *self == Lpmode::En7 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en8(&self) -> bool { + *self == Lpmode::En8 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en9(&self) -> bool { + *self == Lpmode::En9 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en10(&self) -> bool { + *self == Lpmode::En10 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en11(&self) -> bool { + *self == Lpmode::En11 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en12(&self) -> bool { + *self == Lpmode::En12 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en13(&self) -> bool { + *self == Lpmode::En13 + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_en14(&self) -> bool { + *self == Lpmode::En14 + } +} +#[doc = "Field `LPMODE` writer - Low-Power Mode"] +pub type LpmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Lpmode, crate::Safe>; +impl<'a, REG> LpmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Not allowed"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpmode::Disabled) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en(self) -> &'a mut crate::W { + self.variant(Lpmode::En) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en1(self) -> &'a mut crate::W { + self.variant(Lpmode::En1) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en2(self) -> &'a mut crate::W { + self.variant(Lpmode::En2) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en3(self) -> &'a mut crate::W { + self.variant(Lpmode::En3) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en4(self) -> &'a mut crate::W { + self.variant(Lpmode::En4) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en5(self) -> &'a mut crate::W { + self.variant(Lpmode::En5) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en6(self) -> &'a mut crate::W { + self.variant(Lpmode::En6) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en7(self) -> &'a mut crate::W { + self.variant(Lpmode::En7) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en8(self) -> &'a mut crate::W { + self.variant(Lpmode::En8) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en9(self) -> &'a mut crate::W { + self.variant(Lpmode::En9) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en10(self) -> &'a mut crate::W { + self.variant(Lpmode::En10) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en11(self) -> &'a mut crate::W { + self.variant(Lpmode::En11) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en12(self) -> &'a mut crate::W { + self.variant(Lpmode::En12) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en13(self) -> &'a mut crate::W { + self.variant(Lpmode::En13) + } + #[doc = "Allowed"] + #[inline(always)] + pub fn en14(self) -> &'a mut crate::W { + self.variant(Lpmode::En14) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: Allowed"] + Disabled = 0, + #[doc = "1: Blocked"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - Lock Register"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Disabled, + true => Lock::Enabled, + } + } + #[doc = "Allowed"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lock::Disabled + } + #[doc = "Blocked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lock::Enabled + } +} +#[doc = "Field `LOCK` writer - Lock Register"] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Allowed"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lock::Disabled) + } + #[doc = "Blocked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lock::Enabled) + } +} +impl R { + #[doc = "Bits 0:3 - Low-Power Mode"] + #[inline(always)] + pub fn lpmode(&self) -> LpmodeR { + LpmodeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 31 - Lock Register"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Low-Power Mode"] + #[inline(always)] + pub fn lpmode(&mut self) -> LpmodeW { + LpmodeW::new(self, 0) + } + #[doc = "Bit 31 - Lock Register"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 31) + } +} +#[doc = "Power Mode Protection\n\nYou can [`read`](crate::Reg::read) this register and get [`pmprot::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmprot::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PmprotSpec; +impl crate::RegisterSpec for PmprotSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmprot::R`](R) reader structure"] +impl crate::Readable for PmprotSpec {} +#[doc = "`write(|w| ..)` method takes [`pmprot::W`](W) writer structure"] +impl crate::Writable for PmprotSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PMPROT to value 0"] +impl crate::Resettable for PmprotSpec {} diff --git a/mcxa276-pac/src/cmc/rpc.rs b/mcxa276-pac/src/cmc/rpc.rs new file mode 100644 index 000000000..e7aa3ff80 --- /dev/null +++ b/mcxa276-pac/src/cmc/rpc.rs @@ -0,0 +1,161 @@ +#[doc = "Register `RPC` reader"] +pub type R = crate::R; +#[doc = "Register `RPC` writer"] +pub type W = crate::W; +#[doc = "Field `FILTCFG` reader - Reset Filter Configuration"] +pub type FiltcfgR = crate::FieldReader; +#[doc = "Field `FILTCFG` writer - Reset Filter Configuration"] +pub type FiltcfgW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Filten { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Filten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILTEN` reader - Filter Enable"] +pub type FiltenR = crate::BitReader; +impl FiltenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filten { + match self.bits { + false => Filten::Disabled, + true => Filten::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Filten::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Filten::Enabled + } +} +#[doc = "Field `FILTEN` writer - Filter Enable"] +pub type FiltenW<'a, REG> = crate::BitWriter<'a, REG, Filten>; +impl<'a, REG> FiltenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Filten::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Filten::Enabled) + } +} +#[doc = "Low-Power Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpfen { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpfen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPFEN` reader - Low-Power Filter Enable"] +pub type LpfenR = crate::BitReader; +impl LpfenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpfen { + match self.bits { + false => Lpfen::Disabled, + true => Lpfen::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpfen::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpfen::Enabled + } +} +#[doc = "Field `LPFEN` writer - Low-Power Filter Enable"] +pub type LpfenW<'a, REG> = crate::BitWriter<'a, REG, Lpfen>; +impl<'a, REG> LpfenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpfen::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpfen::Enabled) + } +} +impl R { + #[doc = "Bits 0:4 - Reset Filter Configuration"] + #[inline(always)] + pub fn filtcfg(&self) -> FiltcfgR { + FiltcfgR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 8 - Filter Enable"] + #[inline(always)] + pub fn filten(&self) -> FiltenR { + FiltenR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Low-Power Filter Enable"] + #[inline(always)] + pub fn lpfen(&self) -> LpfenR { + LpfenR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Reset Filter Configuration"] + #[inline(always)] + pub fn filtcfg(&mut self) -> FiltcfgW { + FiltcfgW::new(self, 0) + } + #[doc = "Bit 8 - Filter Enable"] + #[inline(always)] + pub fn filten(&mut self) -> FiltenW { + FiltenW::new(self, 8) + } + #[doc = "Bit 9 - Low-Power Filter Enable"] + #[inline(always)] + pub fn lpfen(&mut self) -> LpfenW { + LpfenW::new(self, 9) + } +} +#[doc = "Reset Pin Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rpc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RpcSpec; +impl crate::RegisterSpec for RpcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rpc::R`](R) reader structure"] +impl crate::Readable for RpcSpec {} +#[doc = "`write(|w| ..)` method takes [`rpc::W`](W) writer structure"] +impl crate::Writable for RpcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RPC to value 0"] +impl crate::Resettable for RpcSpec {} diff --git a/mcxa276-pac/src/cmc/srie.rs b/mcxa276-pac/src/cmc/srie.rs new file mode 100644 index 000000000..50de5f4de --- /dev/null +++ b/mcxa276-pac/src/cmc/srie.rs @@ -0,0 +1,590 @@ +#[doc = "Register `SRIE` reader"] +pub type R = crate::R; +#[doc = "Register `SRIE` writer"] +pub type W = crate::W; +#[doc = "Pin Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN` reader - Pin Reset"] +pub type PinR = crate::BitReader; +impl PinR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin { + match self.bits { + false => Pin::Disabled, + true => Pin::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pin::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pin::Enabled + } +} +#[doc = "Field `PIN` writer - Pin Reset"] +pub type PinW<'a, REG> = crate::BitWriter<'a, REG, Pin>; +impl<'a, REG> PinW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pin::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pin::Enabled) + } +} +#[doc = "DAP Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dap { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dap) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAP` reader - DAP Reset"] +pub type DapR = crate::BitReader; +impl DapR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dap { + match self.bits { + false => Dap::Disabled, + true => Dap::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dap::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dap::Enabled + } +} +#[doc = "Field `DAP` writer - DAP Reset"] +pub type DapW<'a, REG> = crate::BitWriter<'a, REG, Dap>; +impl<'a, REG> DapW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dap::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dap::Enabled) + } +} +#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpack { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] +pub type LpackR = crate::BitReader; +impl LpackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpack { + match self.bits { + false => Lpack::Disabled, + true => Lpack::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpack::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpack::Enabled + } +} +#[doc = "Field `LPACK` writer - Low Power Acknowledge Timeout Reset"] +pub type LpackW<'a, REG> = crate::BitWriter<'a, REG, Lpack>; +impl<'a, REG> LpackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpack::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpack::Enabled) + } +} +#[doc = "System Clock Generation Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Scg { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Scg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SCG` reader - System Clock Generation Reset"] +pub type ScgR = crate::BitReader; +impl ScgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Scg { + match self.bits { + false => Scg::Disabled, + true => Scg::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Scg::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Scg::Enabled + } +} +#[doc = "Field `SCG` writer - System Clock Generation Reset"] +pub type ScgW<'a, REG> = crate::BitWriter<'a, REG, Scg>; +impl<'a, REG> ScgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Scg::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Scg::Enabled) + } +} +#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wwdt0 { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wwdt0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] +pub type Wwdt0R = crate::BitReader; +impl Wwdt0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wwdt0 { + match self.bits { + false => Wwdt0::Disabled, + true => Wwdt0::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wwdt0::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wwdt0::Enabled + } +} +#[doc = "Field `WWDT0` writer - Windowed Watchdog 0 Reset"] +pub type Wwdt0W<'a, REG> = crate::BitWriter<'a, REG, Wwdt0>; +impl<'a, REG> Wwdt0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Enabled) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sw { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SW` reader - Software Reset"] +pub type SwR = crate::BitReader; +impl SwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sw { + match self.bits { + false => Sw::Disabled, + true => Sw::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sw::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sw::Enabled + } +} +#[doc = "Field `SW` writer - Software Reset"] +pub type SwW<'a, REG> = crate::BitWriter<'a, REG, Sw>; +impl<'a, REG> SwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sw::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sw::Enabled) + } +} +#[doc = "Lockup Reset\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lockup { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lockup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCKUP` reader - Lockup Reset"] +pub type LockupR = crate::BitReader; +impl LockupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lockup { + match self.bits { + false => Lockup::Disabled, + true => Lockup::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lockup::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lockup::Enabled + } +} +#[doc = "Field `LOCKUP` writer - Lockup Reset"] +pub type LockupW<'a, REG> = crate::BitWriter<'a, REG, Lockup>; +impl<'a, REG> LockupW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lockup::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lockup::Enabled) + } +} +#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog0 { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] +pub type Cdog0R = crate::BitReader; +impl Cdog0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog0 { + match self.bits { + false => Cdog0::Disabled, + true => Cdog0::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog0::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog0::Enabled + } +} +#[doc = "Field `CDOG0` writer - Code Watchdog 0 Reset"] +pub type Cdog0W<'a, REG> = crate::BitWriter<'a, REG, Cdog0>; +impl<'a, REG> Cdog0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cdog0::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cdog0::Enabled) + } +} +#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog1 { + #[doc = "0: Interrupt disabled"] + Disabled = 0, + #[doc = "1: Interrupt enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] +pub type Cdog1R = crate::BitReader; +impl Cdog1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog1 { + match self.bits { + false => Cdog1::Disabled, + true => Cdog1::Enabled, + } + } + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog1::Disabled + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog1::Enabled + } +} +#[doc = "Field `CDOG1` writer - Code Watchdog 1 Reset"] +pub type Cdog1W<'a, REG> = crate::BitWriter<'a, REG, Cdog1>; +impl<'a, REG> Cdog1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cdog1::Disabled) + } + #[doc = "Interrupt enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cdog1::Enabled) + } +} +impl R { + #[doc = "Bit 8 - Pin Reset"] + #[inline(always)] + pub fn pin(&self) -> PinR { + PinR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - DAP Reset"] + #[inline(always)] + pub fn dap(&self) -> DapR { + DapR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] + #[inline(always)] + pub fn lpack(&self) -> LpackR { + LpackR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - System Clock Generation Reset"] + #[inline(always)] + pub fn scg(&self) -> ScgR { + ScgR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] + #[inline(always)] + pub fn wwdt0(&self) -> Wwdt0R { + Wwdt0R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software Reset"] + #[inline(always)] + pub fn sw(&self) -> SwR { + SwR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Lockup Reset"] + #[inline(always)] + pub fn lockup(&self) -> LockupR { + LockupR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 26 - Code Watchdog 0 Reset"] + #[inline(always)] + pub fn cdog0(&self) -> Cdog0R { + Cdog0R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Code Watchdog 1 Reset"] + #[inline(always)] + pub fn cdog1(&self) -> Cdog1R { + Cdog1R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Pin Reset"] + #[inline(always)] + pub fn pin(&mut self) -> PinW { + PinW::new(self, 8) + } + #[doc = "Bit 9 - DAP Reset"] + #[inline(always)] + pub fn dap(&mut self) -> DapW { + DapW::new(self, 9) + } + #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] + #[inline(always)] + pub fn lpack(&mut self) -> LpackW { + LpackW::new(self, 11) + } + #[doc = "Bit 12 - System Clock Generation Reset"] + #[inline(always)] + pub fn scg(&mut self) -> ScgW { + ScgW::new(self, 12) + } + #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] + #[inline(always)] + pub fn wwdt0(&mut self) -> Wwdt0W { + Wwdt0W::new(self, 13) + } + #[doc = "Bit 14 - Software Reset"] + #[inline(always)] + pub fn sw(&mut self) -> SwW { + SwW::new(self, 14) + } + #[doc = "Bit 15 - Lockup Reset"] + #[inline(always)] + pub fn lockup(&mut self) -> LockupW { + LockupW::new(self, 15) + } + #[doc = "Bit 26 - Code Watchdog 0 Reset"] + #[inline(always)] + pub fn cdog0(&mut self) -> Cdog0W { + Cdog0W::new(self, 26) + } + #[doc = "Bit 27 - Code Watchdog 1 Reset"] + #[inline(always)] + pub fn cdog1(&mut self) -> Cdog1W { + Cdog1W::new(self, 27) + } +} +#[doc = "System Reset Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`srie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrieSpec; +impl crate::RegisterSpec for SrieSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`srie::R`](R) reader structure"] +impl crate::Readable for SrieSpec {} +#[doc = "`write(|w| ..)` method takes [`srie::W`](W) writer structure"] +impl crate::Writable for SrieSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SRIE to value 0x8800"] +impl crate::Resettable for SrieSpec { + const RESET_VALUE: u32 = 0x8800; +} diff --git a/mcxa276-pac/src/cmc/srif.rs b/mcxa276-pac/src/cmc/srif.rs new file mode 100644 index 000000000..f77b6780e --- /dev/null +++ b/mcxa276-pac/src/cmc/srif.rs @@ -0,0 +1,526 @@ +#[doc = "Register `SRIF` reader"] +pub type R = crate::R; +#[doc = "Register `SRIF` writer"] +pub type W = crate::W; +#[doc = "Pin Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN` reader - Pin Reset"] +pub type PinR = crate::BitReader; +impl PinR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin { + match self.bits { + false => Pin::Disabled, + true => Pin::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pin::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pin::Enabled + } +} +#[doc = "Field `PIN` writer - Pin Reset"] +pub type PinW<'a, REG> = crate::BitWriter1C<'a, REG, Pin>; +impl<'a, REG> PinW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pin::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pin::Enabled) + } +} +#[doc = "DAP Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dap { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dap) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAP` reader - DAP Reset"] +pub type DapR = crate::BitReader; +impl DapR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dap { + match self.bits { + false => Dap::Disabled, + true => Dap::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dap::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dap::Enabled + } +} +#[doc = "Field `DAP` writer - DAP Reset"] +pub type DapW<'a, REG> = crate::BitWriter1C<'a, REG, Dap>; +impl<'a, REG> DapW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dap::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dap::Enabled) + } +} +#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpack { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] +pub type LpackR = crate::BitReader; +impl LpackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpack { + match self.bits { + false => Lpack::Disabled, + true => Lpack::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpack::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpack::Enabled + } +} +#[doc = "Field `LPACK` writer - Low Power Acknowledge Timeout Reset"] +pub type LpackW<'a, REG> = crate::BitWriter1C<'a, REG, Lpack>; +impl<'a, REG> LpackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpack::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpack::Enabled) + } +} +#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wwdt0 { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wwdt0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] +pub type Wwdt0R = crate::BitReader; +impl Wwdt0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wwdt0 { + match self.bits { + false => Wwdt0::Disabled, + true => Wwdt0::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wwdt0::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wwdt0::Enabled + } +} +#[doc = "Field `WWDT0` writer - Windowed Watchdog 0 Reset"] +pub type Wwdt0W<'a, REG> = crate::BitWriter1C<'a, REG, Wwdt0>; +impl<'a, REG> Wwdt0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Enabled) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sw { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SW` reader - Software Reset"] +pub type SwR = crate::BitReader; +impl SwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sw { + match self.bits { + false => Sw::Disabled, + true => Sw::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sw::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sw::Enabled + } +} +#[doc = "Field `SW` writer - Software Reset"] +pub type SwW<'a, REG> = crate::BitWriter1C<'a, REG, Sw>; +impl<'a, REG> SwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sw::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sw::Enabled) + } +} +#[doc = "Lockup Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lockup { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lockup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCKUP` reader - Lockup Reset"] +pub type LockupR = crate::BitReader; +impl LockupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lockup { + match self.bits { + false => Lockup::Disabled, + true => Lockup::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lockup::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lockup::Enabled + } +} +#[doc = "Field `LOCKUP` writer - Lockup Reset"] +pub type LockupW<'a, REG> = crate::BitWriter1C<'a, REG, Lockup>; +impl<'a, REG> LockupW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lockup::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lockup::Enabled) + } +} +#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog0 { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] +pub type Cdog0R = crate::BitReader; +impl Cdog0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog0 { + match self.bits { + false => Cdog0::Disabled, + true => Cdog0::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog0::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog0::Enabled + } +} +#[doc = "Field `CDOG0` writer - Code Watchdog 0 Reset"] +pub type Cdog0W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog0>; +impl<'a, REG> Cdog0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cdog0::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cdog0::Enabled) + } +} +#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog1 { + #[doc = "0: Reset source not pending"] + Disabled = 0, + #[doc = "1: Reset source pending"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] +pub type Cdog1R = crate::BitReader; +impl Cdog1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog1 { + match self.bits { + false => Cdog1::Disabled, + true => Cdog1::Enabled, + } + } + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog1::Disabled + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog1::Enabled + } +} +#[doc = "Field `CDOG1` writer - Code Watchdog 1 Reset"] +pub type Cdog1W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog1>; +impl<'a, REG> Cdog1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset source not pending"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cdog1::Disabled) + } + #[doc = "Reset source pending"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cdog1::Enabled) + } +} +impl R { + #[doc = "Bit 8 - Pin Reset"] + #[inline(always)] + pub fn pin(&self) -> PinR { + PinR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - DAP Reset"] + #[inline(always)] + pub fn dap(&self) -> DapR { + DapR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] + #[inline(always)] + pub fn lpack(&self) -> LpackR { + LpackR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] + #[inline(always)] + pub fn wwdt0(&self) -> Wwdt0R { + Wwdt0R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software Reset"] + #[inline(always)] + pub fn sw(&self) -> SwR { + SwR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Lockup Reset"] + #[inline(always)] + pub fn lockup(&self) -> LockupR { + LockupR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 26 - Code Watchdog 0 Reset"] + #[inline(always)] + pub fn cdog0(&self) -> Cdog0R { + Cdog0R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Code Watchdog 1 Reset"] + #[inline(always)] + pub fn cdog1(&self) -> Cdog1R { + Cdog1R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Pin Reset"] + #[inline(always)] + pub fn pin(&mut self) -> PinW { + PinW::new(self, 8) + } + #[doc = "Bit 9 - DAP Reset"] + #[inline(always)] + pub fn dap(&mut self) -> DapW { + DapW::new(self, 9) + } + #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] + #[inline(always)] + pub fn lpack(&mut self) -> LpackW { + LpackW::new(self, 11) + } + #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] + #[inline(always)] + pub fn wwdt0(&mut self) -> Wwdt0W { + Wwdt0W::new(self, 13) + } + #[doc = "Bit 14 - Software Reset"] + #[inline(always)] + pub fn sw(&mut self) -> SwW { + SwW::new(self, 14) + } + #[doc = "Bit 15 - Lockup Reset"] + #[inline(always)] + pub fn lockup(&mut self) -> LockupW { + LockupW::new(self, 15) + } + #[doc = "Bit 26 - Code Watchdog 0 Reset"] + #[inline(always)] + pub fn cdog0(&mut self) -> Cdog0W { + Cdog0W::new(self, 26) + } + #[doc = "Bit 27 - Code Watchdog 1 Reset"] + #[inline(always)] + pub fn cdog1(&mut self) -> Cdog1W { + Cdog1W::new(self, 27) + } +} +#[doc = "System Reset Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`srif::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srif::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrifSpec; +impl crate::RegisterSpec for SrifSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`srif::R`](R) reader structure"] +impl crate::Readable for SrifSpec {} +#[doc = "`write(|w| ..)` method takes [`srif::W`](W) writer structure"] +impl crate::Writable for SrifSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c00_eb00; +} +#[doc = "`reset()` method sets SRIF to value 0"] +impl crate::Resettable for SrifSpec {} diff --git a/mcxa276-pac/src/cmc/srs.rs b/mcxa276-pac/src/cmc/srs.rs new file mode 100644 index 000000000..d0e91fb63 --- /dev/null +++ b/mcxa276-pac/src/cmc/srs.rs @@ -0,0 +1,710 @@ +#[doc = "Register `SRS` reader"] +pub type R = crate::R; +#[doc = "Wake-up Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wakeup { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wakeup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKEUP` reader - Wake-up Reset"] +pub type WakeupR = crate::BitReader; +impl WakeupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wakeup { + match self.bits { + false => Wakeup::Disabled, + true => Wakeup::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wakeup::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wakeup::Enabled + } +} +#[doc = "Power-on Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Por { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Por) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POR` reader - Power-on Reset"] +pub type PorR = crate::BitReader; +impl PorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Por { + match self.bits { + false => Por::Disabled, + true => Por::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Por::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Por::Enabled + } +} +#[doc = "Voltage Detect Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Vd { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Vd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VD` reader - Voltage Detect Reset"] +pub type VdR = crate::BitReader; +impl VdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Vd { + match self.bits { + false => Vd::Disabled, + true => Vd::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Vd::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Vd::Enabled + } +} +#[doc = "Warm Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Warm { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Warm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WARM` reader - Warm Reset"] +pub type WarmR = crate::BitReader; +impl WarmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Warm { + match self.bits { + false => Warm::Disabled, + true => Warm::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Warm::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Warm::Enabled + } +} +#[doc = "Fatal Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fatal { + #[doc = "0: Reset was not generated"] + Disabled = 0, + #[doc = "1: Reset was generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fatal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FATAL` reader - Fatal Reset"] +pub type FatalR = crate::BitReader; +impl FatalR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fatal { + match self.bits { + false => Fatal::Disabled, + true => Fatal::Enabled, + } + } + #[doc = "Reset was not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fatal::Disabled + } + #[doc = "Reset was generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fatal::Enabled + } +} +#[doc = "Pin Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin { + #[doc = "0: Reset was not generated"] + Disabled = 0, + #[doc = "1: Reset was generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN` reader - Pin Reset"] +pub type PinR = crate::BitReader; +impl PinR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin { + match self.bits { + false => Pin::Disabled, + true => Pin::Enabled, + } + } + #[doc = "Reset was not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pin::Disabled + } + #[doc = "Reset was generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pin::Enabled + } +} +#[doc = "Debug Access Port Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dap { + #[doc = "0: Reset was not generated"] + Disabled = 0, + #[doc = "1: Reset was generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dap) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAP` reader - Debug Access Port Reset"] +pub type DapR = crate::BitReader; +impl DapR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dap { + match self.bits { + false => Dap::Disabled, + true => Dap::Enabled, + } + } + #[doc = "Reset was not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dap::Disabled + } + #[doc = "Reset was generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dap::Enabled + } +} +#[doc = "Reset Timeout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rstack { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rstack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSTACK` reader - Reset Timeout"] +pub type RstackR = crate::BitReader; +impl RstackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rstack { + match self.bits { + false => Rstack::Disabled, + true => Rstack::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rstack::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rstack::Enabled + } +} +#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpack { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] +pub type LpackR = crate::BitReader; +impl LpackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpack { + match self.bits { + false => Lpack::Disabled, + true => Lpack::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpack::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpack::Enabled + } +} +#[doc = "System Clock Generation Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Scg { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Scg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SCG` reader - System Clock Generation Reset"] +pub type ScgR = crate::BitReader; +impl ScgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Scg { + match self.bits { + false => Scg::Disabled, + true => Scg::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Scg::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Scg::Enabled + } +} +#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wwdt0 { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wwdt0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] +pub type Wwdt0R = crate::BitReader; +impl Wwdt0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wwdt0 { + match self.bits { + false => Wwdt0::Disabled, + true => Wwdt0::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wwdt0::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wwdt0::Enabled + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sw { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SW` reader - Software Reset"] +pub type SwR = crate::BitReader; +impl SwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sw { + match self.bits { + false => Sw::Disabled, + true => Sw::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sw::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sw::Enabled + } +} +#[doc = "Lockup Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lockup { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lockup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCKUP` reader - Lockup Reset"] +pub type LockupR = crate::BitReader; +impl LockupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lockup { + match self.bits { + false => Lockup::Disabled, + true => Lockup::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lockup::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lockup::Enabled + } +} +#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog0 { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] +pub type Cdog0R = crate::BitReader; +impl Cdog0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog0 { + match self.bits { + false => Cdog0::Disabled, + true => Cdog0::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog0::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog0::Enabled + } +} +#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog1 { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] +pub type Cdog1R = crate::BitReader; +impl Cdog1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog1 { + match self.bits { + false => Cdog1::Disabled, + true => Cdog1::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog1::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog1::Enabled + } +} +#[doc = "JTAG System Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Jtag { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Jtag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `JTAG` reader - JTAG System Reset"] +pub type JtagR = crate::BitReader; +impl JtagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Jtag { + match self.bits { + false => Jtag::Disabled, + true => Jtag::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Jtag::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Jtag::Enabled + } +} +#[doc = "Tamper Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tamper { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tamper) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TAMPER` reader - Tamper Reset"] +pub type TamperR = crate::BitReader; +impl TamperR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tamper { + match self.bits { + false => Tamper::Disabled, + true => Tamper::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tamper::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tamper::Enabled + } +} +impl R { + #[doc = "Bit 0 - Wake-up Reset"] + #[inline(always)] + pub fn wakeup(&self) -> WakeupR { + WakeupR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Power-on Reset"] + #[inline(always)] + pub fn por(&self) -> PorR { + PorR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Voltage Detect Reset"] + #[inline(always)] + pub fn vd(&self) -> VdR { + VdR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Warm Reset"] + #[inline(always)] + pub fn warm(&self) -> WarmR { + WarmR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Fatal Reset"] + #[inline(always)] + pub fn fatal(&self) -> FatalR { + FatalR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Pin Reset"] + #[inline(always)] + pub fn pin(&self) -> PinR { + PinR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Debug Access Port Reset"] + #[inline(always)] + pub fn dap(&self) -> DapR { + DapR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reset Timeout"] + #[inline(always)] + pub fn rstack(&self) -> RstackR { + RstackR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] + #[inline(always)] + pub fn lpack(&self) -> LpackR { + LpackR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - System Clock Generation Reset"] + #[inline(always)] + pub fn scg(&self) -> ScgR { + ScgR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] + #[inline(always)] + pub fn wwdt0(&self) -> Wwdt0R { + Wwdt0R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software Reset"] + #[inline(always)] + pub fn sw(&self) -> SwR { + SwR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Lockup Reset"] + #[inline(always)] + pub fn lockup(&self) -> LockupR { + LockupR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 26 - Code Watchdog 0 Reset"] + #[inline(always)] + pub fn cdog0(&self) -> Cdog0R { + Cdog0R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Code Watchdog 1 Reset"] + #[inline(always)] + pub fn cdog1(&self) -> Cdog1R { + Cdog1R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - JTAG System Reset"] + #[inline(always)] + pub fn jtag(&self) -> JtagR { + JtagR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 31 - Tamper Reset"] + #[inline(always)] + pub fn tamper(&self) -> TamperR { + TamperR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`srs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrsSpec; +impl crate::RegisterSpec for SrsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`srs::R`](R) reader structure"] +impl crate::Readable for SrsSpec {} +#[doc = "`reset()` method sets SRS to value 0"] +impl crate::Resettable for SrsSpec {} diff --git a/mcxa276-pac/src/cmc/ssrs.rs b/mcxa276-pac/src/cmc/ssrs.rs new file mode 100644 index 000000000..4b69c139f --- /dev/null +++ b/mcxa276-pac/src/cmc/ssrs.rs @@ -0,0 +1,1073 @@ +#[doc = "Register `SSRS` reader"] +pub type R = crate::R; +#[doc = "Register `SSRS` writer"] +pub type W = crate::W; +#[doc = "Wake-up Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wakeup { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wakeup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKEUP` reader - Wake-up Reset"] +pub type WakeupR = crate::BitReader; +impl WakeupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wakeup { + match self.bits { + false => Wakeup::Disabled, + true => Wakeup::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wakeup::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wakeup::Enabled + } +} +#[doc = "Field `WAKEUP` writer - Wake-up Reset"] +pub type WakeupW<'a, REG> = crate::BitWriter1C<'a, REG, Wakeup>; +impl<'a, REG> WakeupW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wakeup::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wakeup::Enabled) + } +} +#[doc = "Power-on Reset\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Por { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Por) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POR` reader - Power-on Reset"] +pub type PorR = crate::BitReader; +impl PorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Por { + match self.bits { + false => Por::Disabled, + true => Por::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Por::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Por::Enabled + } +} +#[doc = "Field `POR` writer - Power-on Reset"] +pub type PorW<'a, REG> = crate::BitWriter1C<'a, REG, Por>; +impl<'a, REG> PorW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Por::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Por::Enabled) + } +} +#[doc = "Voltage Detect Reset\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Vd { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Vd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VD` reader - Voltage Detect Reset"] +pub type VdR = crate::BitReader; +impl VdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Vd { + match self.bits { + false => Vd::Disabled, + true => Vd::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Vd::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Vd::Enabled + } +} +#[doc = "Warm Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Warm { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Warm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WARM` reader - Warm Reset"] +pub type WarmR = crate::BitReader; +impl WarmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Warm { + match self.bits { + false => Warm::Disabled, + true => Warm::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Warm::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Warm::Enabled + } +} +#[doc = "Field `WARM` writer - Warm Reset"] +pub type WarmW<'a, REG> = crate::BitWriter1C<'a, REG, Warm>; +impl<'a, REG> WarmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Warm::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Warm::Enabled) + } +} +#[doc = "Fatal Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fatal { + #[doc = "0: Reset was not generated"] + Disabled = 0, + #[doc = "1: Reset was generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fatal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FATAL` reader - Fatal Reset"] +pub type FatalR = crate::BitReader; +impl FatalR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fatal { + match self.bits { + false => Fatal::Disabled, + true => Fatal::Enabled, + } + } + #[doc = "Reset was not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fatal::Disabled + } + #[doc = "Reset was generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fatal::Enabled + } +} +#[doc = "Field `FATAL` writer - Fatal Reset"] +pub type FatalW<'a, REG> = crate::BitWriter1C<'a, REG, Fatal>; +impl<'a, REG> FatalW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset was not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fatal::Disabled) + } + #[doc = "Reset was generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fatal::Enabled) + } +} +#[doc = "Pin Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN` reader - Pin Reset"] +pub type PinR = crate::BitReader; +impl PinR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin { + match self.bits { + false => Pin::Disabled, + true => Pin::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pin::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pin::Enabled + } +} +#[doc = "Field `PIN` writer - Pin Reset"] +pub type PinW<'a, REG> = crate::BitWriter1C<'a, REG, Pin>; +impl<'a, REG> PinW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pin::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pin::Enabled) + } +} +#[doc = "DAP Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dap { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dap) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAP` reader - DAP Reset"] +pub type DapR = crate::BitReader; +impl DapR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dap { + match self.bits { + false => Dap::Disabled, + true => Dap::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dap::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dap::Enabled + } +} +#[doc = "Field `DAP` writer - DAP Reset"] +pub type DapW<'a, REG> = crate::BitWriter1C<'a, REG, Dap>; +impl<'a, REG> DapW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dap::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dap::Enabled) + } +} +#[doc = "Reset Timeout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rstack { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rstack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSTACK` reader - Reset Timeout"] +pub type RstackR = crate::BitReader; +impl RstackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rstack { + match self.bits { + false => Rstack::Disabled, + true => Rstack::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rstack::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rstack::Enabled + } +} +#[doc = "Field `RSTACK` writer - Reset Timeout"] +pub type RstackW<'a, REG> = crate::BitWriter1C<'a, REG, Rstack>; +impl<'a, REG> RstackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rstack::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rstack::Enabled) + } +} +#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpack { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] +pub type LpackR = crate::BitReader; +impl LpackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpack { + match self.bits { + false => Lpack::Disabled, + true => Lpack::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpack::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpack::Enabled + } +} +#[doc = "Field `LPACK` writer - Low Power Acknowledge Timeout Reset"] +pub type LpackW<'a, REG> = crate::BitWriter1C<'a, REG, Lpack>; +impl<'a, REG> LpackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpack::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpack::Enabled) + } +} +#[doc = "System Clock Generation Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Scg { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Scg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SCG` reader - System Clock Generation Reset"] +pub type ScgR = crate::BitReader; +impl ScgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Scg { + match self.bits { + false => Scg::Disabled, + true => Scg::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Scg::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Scg::Enabled + } +} +#[doc = "Field `SCG` writer - System Clock Generation Reset"] +pub type ScgW<'a, REG> = crate::BitWriter1C<'a, REG, Scg>; +impl<'a, REG> ScgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Scg::Disabled) + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Scg::Enabled) + } +} +#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wwdt0 { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wwdt0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] +pub type Wwdt0R = crate::BitReader; +impl Wwdt0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wwdt0 { + match self.bits { + false => Wwdt0::Disabled, + true => Wwdt0::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wwdt0::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wwdt0::Enabled + } +} +#[doc = "Field `WWDT0` writer - Windowed Watchdog 0 Reset"] +pub type Wwdt0W<'a, REG> = crate::BitWriter1C<'a, REG, Wwdt0>; +impl<'a, REG> Wwdt0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Disabled) + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Enabled) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sw { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SW` reader - Software Reset"] +pub type SwR = crate::BitReader; +impl SwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sw { + match self.bits { + false => Sw::Disabled, + true => Sw::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sw::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sw::Enabled + } +} +#[doc = "Field `SW` writer - Software Reset"] +pub type SwW<'a, REG> = crate::BitWriter1C<'a, REG, Sw>; +impl<'a, REG> SwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sw::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sw::Enabled) + } +} +#[doc = "Lockup Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lockup { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lockup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCKUP` reader - Lockup Reset"] +pub type LockupR = crate::BitReader; +impl LockupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lockup { + match self.bits { + false => Lockup::Disabled, + true => Lockup::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lockup::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lockup::Enabled + } +} +#[doc = "Field `LOCKUP` writer - Lockup Reset"] +pub type LockupW<'a, REG> = crate::BitWriter1C<'a, REG, Lockup>; +impl<'a, REG> LockupW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lockup::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lockup::Enabled) + } +} +#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog0 { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] +pub type Cdog0R = crate::BitReader; +impl Cdog0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog0 { + match self.bits { + false => Cdog0::Disabled, + true => Cdog0::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog0::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog0::Enabled + } +} +#[doc = "Field `CDOG0` writer - Code Watchdog 0 Reset"] +pub type Cdog0W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog0>; +impl<'a, REG> Cdog0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cdog0::Disabled) + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cdog0::Enabled) + } +} +#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cdog1 { + #[doc = "0: Reset is not generated"] + Disabled = 0, + #[doc = "1: Reset is generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cdog1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] +pub type Cdog1R = crate::BitReader; +impl Cdog1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cdog1 { + match self.bits { + false => Cdog1::Disabled, + true => Cdog1::Enabled, + } + } + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cdog1::Disabled + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cdog1::Enabled + } +} +#[doc = "Field `CDOG1` writer - Code Watchdog 1 Reset"] +pub type Cdog1W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog1>; +impl<'a, REG> Cdog1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset is not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cdog1::Disabled) + } + #[doc = "Reset is generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cdog1::Enabled) + } +} +#[doc = "JTAG System Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Jtag { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Jtag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `JTAG` reader - JTAG System Reset"] +pub type JtagR = crate::BitReader; +impl JtagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Jtag { + match self.bits { + false => Jtag::Disabled, + true => Jtag::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Jtag::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Jtag::Enabled + } +} +#[doc = "Field `JTAG` writer - JTAG System Reset"] +pub type JtagW<'a, REG> = crate::BitWriter1C<'a, REG, Jtag>; +impl<'a, REG> JtagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Jtag::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Jtag::Enabled) + } +} +#[doc = "Tamper Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tamper { + #[doc = "0: Reset not generated"] + Disabled = 0, + #[doc = "1: Reset generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tamper) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TAMPER` reader - Tamper Reset"] +pub type TamperR = crate::BitReader; +impl TamperR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tamper { + match self.bits { + false => Tamper::Disabled, + true => Tamper::Enabled, + } + } + #[doc = "Reset not generated"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tamper::Disabled + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tamper::Enabled + } +} +#[doc = "Field `TAMPER` writer - Tamper Reset"] +pub type TamperW<'a, REG> = crate::BitWriter1C<'a, REG, Tamper>; +impl<'a, REG> TamperW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset not generated"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tamper::Disabled) + } + #[doc = "Reset generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tamper::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Wake-up Reset"] + #[inline(always)] + pub fn wakeup(&self) -> WakeupR { + WakeupR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Power-on Reset"] + #[inline(always)] + pub fn por(&self) -> PorR { + PorR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Voltage Detect Reset"] + #[inline(always)] + pub fn vd(&self) -> VdR { + VdR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Warm Reset"] + #[inline(always)] + pub fn warm(&self) -> WarmR { + WarmR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Fatal Reset"] + #[inline(always)] + pub fn fatal(&self) -> FatalR { + FatalR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Pin Reset"] + #[inline(always)] + pub fn pin(&self) -> PinR { + PinR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - DAP Reset"] + #[inline(always)] + pub fn dap(&self) -> DapR { + DapR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reset Timeout"] + #[inline(always)] + pub fn rstack(&self) -> RstackR { + RstackR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] + #[inline(always)] + pub fn lpack(&self) -> LpackR { + LpackR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - System Clock Generation Reset"] + #[inline(always)] + pub fn scg(&self) -> ScgR { + ScgR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] + #[inline(always)] + pub fn wwdt0(&self) -> Wwdt0R { + Wwdt0R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software Reset"] + #[inline(always)] + pub fn sw(&self) -> SwR { + SwR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Lockup Reset"] + #[inline(always)] + pub fn lockup(&self) -> LockupR { + LockupR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 26 - Code Watchdog 0 Reset"] + #[inline(always)] + pub fn cdog0(&self) -> Cdog0R { + Cdog0R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Code Watchdog 1 Reset"] + #[inline(always)] + pub fn cdog1(&self) -> Cdog1R { + Cdog1R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - JTAG System Reset"] + #[inline(always)] + pub fn jtag(&self) -> JtagR { + JtagR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 31 - Tamper Reset"] + #[inline(always)] + pub fn tamper(&self) -> TamperR { + TamperR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Wake-up Reset"] + #[inline(always)] + pub fn wakeup(&mut self) -> WakeupW { + WakeupW::new(self, 0) + } + #[doc = "Bit 1 - Power-on Reset"] + #[inline(always)] + pub fn por(&mut self) -> PorW { + PorW::new(self, 1) + } + #[doc = "Bit 4 - Warm Reset"] + #[inline(always)] + pub fn warm(&mut self) -> WarmW { + WarmW::new(self, 4) + } + #[doc = "Bit 5 - Fatal Reset"] + #[inline(always)] + pub fn fatal(&mut self) -> FatalW { + FatalW::new(self, 5) + } + #[doc = "Bit 8 - Pin Reset"] + #[inline(always)] + pub fn pin(&mut self) -> PinW { + PinW::new(self, 8) + } + #[doc = "Bit 9 - DAP Reset"] + #[inline(always)] + pub fn dap(&mut self) -> DapW { + DapW::new(self, 9) + } + #[doc = "Bit 10 - Reset Timeout"] + #[inline(always)] + pub fn rstack(&mut self) -> RstackW { + RstackW::new(self, 10) + } + #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] + #[inline(always)] + pub fn lpack(&mut self) -> LpackW { + LpackW::new(self, 11) + } + #[doc = "Bit 12 - System Clock Generation Reset"] + #[inline(always)] + pub fn scg(&mut self) -> ScgW { + ScgW::new(self, 12) + } + #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] + #[inline(always)] + pub fn wwdt0(&mut self) -> Wwdt0W { + Wwdt0W::new(self, 13) + } + #[doc = "Bit 14 - Software Reset"] + #[inline(always)] + pub fn sw(&mut self) -> SwW { + SwW::new(self, 14) + } + #[doc = "Bit 15 - Lockup Reset"] + #[inline(always)] + pub fn lockup(&mut self) -> LockupW { + LockupW::new(self, 15) + } + #[doc = "Bit 26 - Code Watchdog 0 Reset"] + #[inline(always)] + pub fn cdog0(&mut self) -> Cdog0W { + Cdog0W::new(self, 26) + } + #[doc = "Bit 27 - Code Watchdog 1 Reset"] + #[inline(always)] + pub fn cdog1(&mut self) -> Cdog1W { + Cdog1W::new(self, 27) + } + #[doc = "Bit 28 - JTAG System Reset"] + #[inline(always)] + pub fn jtag(&mut self) -> JtagW { + JtagW::new(self, 28) + } + #[doc = "Bit 31 - Tamper Reset"] + #[inline(always)] + pub fn tamper(&mut self) -> TamperW { + TamperW::new(self, 31) + } +} +#[doc = "Sticky System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssrs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssrs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SsrsSpec; +impl crate::RegisterSpec for SsrsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssrs::R`](R) reader structure"] +impl crate::Readable for SsrsSpec {} +#[doc = "`write(|w| ..)` method takes [`ssrs::W`](W) writer structure"] +impl crate::Writable for SsrsSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x9c00_ff33; +} +#[doc = "`reset()` method sets SSRS to value 0x06"] +impl crate::Resettable for SsrsSpec { + const RESET_VALUE: u32 = 0x06; +} diff --git a/mcxa276-pac/src/cmc/verid.rs b/mcxa276-pac/src/cmc/verid.rs new file mode 100644 index 000000000..00564cf8e --- /dev/null +++ b/mcxa276-pac/src/cmc/verid.rs @@ -0,0 +1,36 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0300_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0300_0000; +} diff --git a/mcxa276-pac/src/cmp0.rs b/mcxa276-pac/src/cmp0.rs new file mode 100644 index 000000000..837ef6a8b --- /dev/null +++ b/mcxa276-pac/src/cmp0.rs @@ -0,0 +1,151 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + ccr0: Ccr0, + ccr1: Ccr1, + ccr2: Ccr2, + _reserved5: [u8; 0x04], + dcr: Dcr, + ier: Ier, + csr: Csr, + rrcr0: Rrcr0, + rrcr1: Rrcr1, + rrcsr: Rrcsr, + rrsr: Rrsr, + _reserved12: [u8; 0x04], + rrcr2: Rrcr2, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x08 - Comparator Control Register 0"] + #[inline(always)] + pub const fn ccr0(&self) -> &Ccr0 { + &self.ccr0 + } + #[doc = "0x0c - Comparator Control Register 1"] + #[inline(always)] + pub const fn ccr1(&self) -> &Ccr1 { + &self.ccr1 + } + #[doc = "0x10 - Comparator Control Register 2"] + #[inline(always)] + pub const fn ccr2(&self) -> &Ccr2 { + &self.ccr2 + } + #[doc = "0x18 - DAC Control"] + #[inline(always)] + pub const fn dcr(&self) -> &Dcr { + &self.dcr + } + #[doc = "0x1c - Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &Ier { + &self.ier + } + #[doc = "0x20 - Comparator Status"] + #[inline(always)] + pub const fn csr(&self) -> &Csr { + &self.csr + } + #[doc = "0x24 - Round Robin Control Register 0"] + #[inline(always)] + pub const fn rrcr0(&self) -> &Rrcr0 { + &self.rrcr0 + } + #[doc = "0x28 - Round Robin Control Register 1"] + #[inline(always)] + pub const fn rrcr1(&self) -> &Rrcr1 { + &self.rrcr1 + } + #[doc = "0x2c - Round Robin Control and Status"] + #[inline(always)] + pub const fn rrcsr(&self) -> &Rrcsr { + &self.rrcsr + } + #[doc = "0x30 - Round Robin Status"] + #[inline(always)] + pub const fn rrsr(&self) -> &Rrsr { + &self.rrsr + } + #[doc = "0x38 - Round Robin Control Register 2"] + #[inline(always)] + pub const fn rrcr2(&self) -> &Rrcr2 { + &self.rrcr2 + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "CCR0 (rw) register accessor: Comparator Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr0`] module"] +#[doc(alias = "CCR0")] +pub type Ccr0 = crate::Reg; +#[doc = "Comparator Control Register 0"] +pub mod ccr0; +#[doc = "CCR1 (rw) register accessor: Comparator Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`] module"] +#[doc(alias = "CCR1")] +pub type Ccr1 = crate::Reg; +#[doc = "Comparator Control Register 1"] +pub mod ccr1; +#[doc = "CCR2 (rw) register accessor: Comparator Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`] module"] +#[doc(alias = "CCR2")] +pub type Ccr2 = crate::Reg; +#[doc = "Comparator Control Register 2"] +pub mod ccr2; +#[doc = "DCR (rw) register accessor: DAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcr`] module"] +#[doc(alias = "DCR")] +pub type Dcr = crate::Reg; +#[doc = "DAC Control"] +pub mod dcr; +#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] +#[doc(alias = "IER")] +pub type Ier = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ier; +#[doc = "CSR (rw) register accessor: Comparator Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`] module"] +#[doc(alias = "CSR")] +pub type Csr = crate::Reg; +#[doc = "Comparator Status"] +pub mod csr; +#[doc = "RRCR0 (rw) register accessor: Round Robin Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcr0`] module"] +#[doc(alias = "RRCR0")] +pub type Rrcr0 = crate::Reg; +#[doc = "Round Robin Control Register 0"] +pub mod rrcr0; +#[doc = "RRCR1 (rw) register accessor: Round Robin Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcr1`] module"] +#[doc(alias = "RRCR1")] +pub type Rrcr1 = crate::Reg; +#[doc = "Round Robin Control Register 1"] +pub mod rrcr1; +#[doc = "RRCSR (rw) register accessor: Round Robin Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcsr`] module"] +#[doc(alias = "RRCSR")] +pub type Rrcsr = crate::Reg; +#[doc = "Round Robin Control and Status"] +pub mod rrcsr; +#[doc = "RRSR (rw) register accessor: Round Robin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrsr`] module"] +#[doc(alias = "RRSR")] +pub type Rrsr = crate::Reg; +#[doc = "Round Robin Status"] +pub mod rrsr; +#[doc = "RRCR2 (rw) register accessor: Round Robin Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcr2`] module"] +#[doc(alias = "RRCR2")] +pub type Rrcr2 = crate::Reg; +#[doc = "Round Robin Control Register 2"] +pub mod rrcr2; diff --git a/mcxa276-pac/src/cmp0/ccr0.rs b/mcxa276-pac/src/cmp0/ccr0.rs new file mode 100644 index 000000000..fdc16d63d --- /dev/null +++ b/mcxa276-pac/src/cmp0/ccr0.rs @@ -0,0 +1,149 @@ +#[doc = "Register `CCR0` reader"] +pub type R = crate::R; +#[doc = "Register `CCR0` writer"] +pub type W = crate::W; +#[doc = "Comparator Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CmpEn { + #[doc = "0: Disable (The analog logic remains off and consumes no power.)"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CmpEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP_EN` reader - Comparator Enable"] +pub type CmpEnR = crate::BitReader; +impl CmpEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CmpEn { + match self.bits { + false => CmpEn::Disable, + true => CmpEn::Enable, + } + } + #[doc = "Disable (The analog logic remains off and consumes no power.)"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CmpEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CmpEn::Enable + } +} +#[doc = "Field `CMP_EN` writer - Comparator Enable"] +pub type CmpEnW<'a, REG> = crate::BitWriter<'a, REG, CmpEn>; +impl<'a, REG> CmpEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable (The analog logic remains off and consumes no power.)"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(CmpEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(CmpEn::Enable) + } +} +#[doc = "Comparator Deep Sleep Mode Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CmpStopEn { + #[doc = "0: Disables the analog comparator regardless of CMP_EN."] + Disable = 0, + #[doc = "1: Allows CMP_EN to enable the analog comparator."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CmpStopEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP_STOP_EN` reader - Comparator Deep Sleep Mode Enable"] +pub type CmpStopEnR = crate::BitReader; +impl CmpStopEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CmpStopEn { + match self.bits { + false => CmpStopEn::Disable, + true => CmpStopEn::Enable, + } + } + #[doc = "Disables the analog comparator regardless of CMP_EN."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CmpStopEn::Disable + } + #[doc = "Allows CMP_EN to enable the analog comparator."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CmpStopEn::Enable + } +} +#[doc = "Field `CMP_STOP_EN` writer - Comparator Deep Sleep Mode Enable"] +pub type CmpStopEnW<'a, REG> = crate::BitWriter<'a, REG, CmpStopEn>; +impl<'a, REG> CmpStopEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables the analog comparator regardless of CMP_EN."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(CmpStopEn::Disable) + } + #[doc = "Allows CMP_EN to enable the analog comparator."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(CmpStopEn::Enable) + } +} +impl R { + #[doc = "Bit 0 - Comparator Enable"] + #[inline(always)] + pub fn cmp_en(&self) -> CmpEnR { + CmpEnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator Deep Sleep Mode Enable"] + #[inline(always)] + pub fn cmp_stop_en(&self) -> CmpStopEnR { + CmpStopEnR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator Enable"] + #[inline(always)] + pub fn cmp_en(&mut self) -> CmpEnW { + CmpEnW::new(self, 0) + } + #[doc = "Bit 1 - Comparator Deep Sleep Mode Enable"] + #[inline(always)] + pub fn cmp_stop_en(&mut self) -> CmpStopEnW { + CmpStopEnW::new(self, 1) + } +} +#[doc = "Comparator Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ccr0Spec; +impl crate::RegisterSpec for Ccr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr0::R`](R) reader structure"] +impl crate::Readable for Ccr0Spec {} +#[doc = "`write(|w| ..)` method takes [`ccr0::W`](W) writer structure"] +impl crate::Writable for Ccr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CCR0 to value 0x02"] +impl crate::Resettable for Ccr0Spec { + const RESET_VALUE: u32 = 0x02; +} diff --git a/mcxa276-pac/src/cmp0/ccr1.rs b/mcxa276-pac/src/cmp0/ccr1.rs new file mode 100644 index 000000000..d8fb4bcfb --- /dev/null +++ b/mcxa276-pac/src/cmp0/ccr1.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CCR1` reader"] +pub type R = crate::R; +#[doc = "Register `CCR1` writer"] +pub type W = crate::W; +#[doc = "Windowing Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WindowEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WindowEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WINDOW_EN` reader - Windowing Enable"] +pub type WindowEnR = crate::BitReader; +impl WindowEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WindowEn { + match self.bits { + false => WindowEn::Disable, + true => WindowEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WindowEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == WindowEn::Enable + } +} +#[doc = "Field `WINDOW_EN` writer - Windowing Enable"] +pub type WindowEnW<'a, REG> = crate::BitWriter<'a, REG, WindowEn>; +impl<'a, REG> WindowEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(WindowEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(WindowEn::Enable) + } +} +#[doc = "Sampling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SampleEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SampleEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SAMPLE_EN` reader - Sampling Enable"] +pub type SampleEnR = crate::BitReader; +impl SampleEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SampleEn { + match self.bits { + false => SampleEn::Disable, + true => SampleEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SampleEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SampleEn::Enable + } +} +#[doc = "Field `SAMPLE_EN` writer - Sampling Enable"] +pub type SampleEnW<'a, REG> = crate::BitWriter<'a, REG, SampleEn>; +impl<'a, REG> SampleEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SampleEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SampleEn::Enable) + } +} +#[doc = "DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DmaEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DmaEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA_EN` reader - DMA Enable"] +pub type DmaEnR = crate::BitReader; +impl DmaEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DmaEn { + match self.bits { + false => DmaEn::Disable, + true => DmaEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DmaEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DmaEn::Enable + } +} +#[doc = "Field `DMA_EN` writer - DMA Enable"] +pub type DmaEnW<'a, REG> = crate::BitWriter<'a, REG, DmaEn>; +impl<'a, REG> DmaEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DmaEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DmaEn::Enable) + } +} +#[doc = "Comparator Invert\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoutInv { + #[doc = "0: Do not invert"] + NoInvert = 0, + #[doc = "1: Invert"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoutInv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COUT_INV` reader - Comparator Invert"] +pub type CoutInvR = crate::BitReader; +impl CoutInvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoutInv { + match self.bits { + false => CoutInv::NoInvert, + true => CoutInv::Invert, + } + } + #[doc = "Do not invert"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == CoutInv::NoInvert + } + #[doc = "Invert"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == CoutInv::Invert + } +} +#[doc = "Field `COUT_INV` writer - Comparator Invert"] +pub type CoutInvW<'a, REG> = crate::BitWriter<'a, REG, CoutInv>; +impl<'a, REG> CoutInvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Do not invert"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(CoutInv::NoInvert) + } + #[doc = "Invert"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(CoutInv::Invert) + } +} +#[doc = "Comparator Output Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoutSel { + #[doc = "0: Use COUT (filtered)"] + Cout = 0, + #[doc = "1: Use COUTA (unfiltered)"] + Couta = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoutSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COUT_SEL` reader - Comparator Output Select"] +pub type CoutSelR = crate::BitReader; +impl CoutSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoutSel { + match self.bits { + false => CoutSel::Cout, + true => CoutSel::Couta, + } + } + #[doc = "Use COUT (filtered)"] + #[inline(always)] + pub fn is_cout(&self) -> bool { + *self == CoutSel::Cout + } + #[doc = "Use COUTA (unfiltered)"] + #[inline(always)] + pub fn is_couta(&self) -> bool { + *self == CoutSel::Couta + } +} +#[doc = "Field `COUT_SEL` writer - Comparator Output Select"] +pub type CoutSelW<'a, REG> = crate::BitWriter<'a, REG, CoutSel>; +impl<'a, REG> CoutSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Use COUT (filtered)"] + #[inline(always)] + pub fn cout(self) -> &'a mut crate::W { + self.variant(CoutSel::Cout) + } + #[doc = "Use COUTA (unfiltered)"] + #[inline(always)] + pub fn couta(self) -> &'a mut crate::W { + self.variant(CoutSel::Couta) + } +} +#[doc = "Comparator Output Pin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoutPen { + #[doc = "0: Not available"] + Unavailable = 0, + #[doc = "1: Available"] + Available = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoutPen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COUT_PEN` reader - Comparator Output Pin Enable"] +pub type CoutPenR = crate::BitReader; +impl CoutPenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoutPen { + match self.bits { + false => CoutPen::Unavailable, + true => CoutPen::Available, + } + } + #[doc = "Not available"] + #[inline(always)] + pub fn is_unavailable(&self) -> bool { + *self == CoutPen::Unavailable + } + #[doc = "Available"] + #[inline(always)] + pub fn is_available(&self) -> bool { + *self == CoutPen::Available + } +} +#[doc = "Field `COUT_PEN` writer - Comparator Output Pin Enable"] +pub type CoutPenW<'a, REG> = crate::BitWriter<'a, REG, CoutPen>; +impl<'a, REG> CoutPenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not available"] + #[inline(always)] + pub fn unavailable(self) -> &'a mut crate::W { + self.variant(CoutPen::Unavailable) + } + #[doc = "Available"] + #[inline(always)] + pub fn available(self) -> &'a mut crate::W { + self.variant(CoutPen::Available) + } +} +#[doc = "COUTA_OW Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoutaOwen { + #[doc = "0: COUTA holds the last sampled value."] + Sampled = 0, + #[doc = "1: Enables the COUTA signal value to be defined by COUTA_OW."] + CoutaOw = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoutaOwen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COUTA_OWEN` reader - COUTA_OW Enable"] +pub type CoutaOwenR = crate::BitReader; +impl CoutaOwenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoutaOwen { + match self.bits { + false => CoutaOwen::Sampled, + true => CoutaOwen::CoutaOw, + } + } + #[doc = "COUTA holds the last sampled value."] + #[inline(always)] + pub fn is_sampled(&self) -> bool { + *self == CoutaOwen::Sampled + } + #[doc = "Enables the COUTA signal value to be defined by COUTA_OW."] + #[inline(always)] + pub fn is_couta_ow(&self) -> bool { + *self == CoutaOwen::CoutaOw + } +} +#[doc = "Field `COUTA_OWEN` writer - COUTA_OW Enable"] +pub type CoutaOwenW<'a, REG> = crate::BitWriter<'a, REG, CoutaOwen>; +impl<'a, REG> CoutaOwenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "COUTA holds the last sampled value."] + #[inline(always)] + pub fn sampled(self) -> &'a mut crate::W { + self.variant(CoutaOwen::Sampled) + } + #[doc = "Enables the COUTA signal value to be defined by COUTA_OW."] + #[inline(always)] + pub fn couta_ow(self) -> &'a mut crate::W { + self.variant(CoutaOwen::CoutaOw) + } +} +#[doc = "COUTA Output Level for Closed Window\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoutaOw { + #[doc = "0: COUTA is 0"] + Couta0 = 0, + #[doc = "1: COUTA is 1"] + Couta1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoutaOw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COUTA_OW` reader - COUTA Output Level for Closed Window"] +pub type CoutaOwR = crate::BitReader; +impl CoutaOwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoutaOw { + match self.bits { + false => CoutaOw::Couta0, + true => CoutaOw::Couta1, + } + } + #[doc = "COUTA is 0"] + #[inline(always)] + pub fn is_couta_0(&self) -> bool { + *self == CoutaOw::Couta0 + } + #[doc = "COUTA is 1"] + #[inline(always)] + pub fn is_couta_1(&self) -> bool { + *self == CoutaOw::Couta1 + } +} +#[doc = "Field `COUTA_OW` writer - COUTA Output Level for Closed Window"] +pub type CoutaOwW<'a, REG> = crate::BitWriter<'a, REG, CoutaOw>; +impl<'a, REG> CoutaOwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "COUTA is 0"] + #[inline(always)] + pub fn couta_0(self) -> &'a mut crate::W { + self.variant(CoutaOw::Couta0) + } + #[doc = "COUTA is 1"] + #[inline(always)] + pub fn couta_1(self) -> &'a mut crate::W { + self.variant(CoutaOw::Couta1) + } +} +#[doc = "WINDOW/SAMPLE Signal Invert\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WindowInv { + #[doc = "0: Do not invert"] + NoInvert = 0, + #[doc = "1: Invert"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WindowInv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WINDOW_INV` reader - WINDOW/SAMPLE Signal Invert"] +pub type WindowInvR = crate::BitReader; +impl WindowInvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WindowInv { + match self.bits { + false => WindowInv::NoInvert, + true => WindowInv::Invert, + } + } + #[doc = "Do not invert"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == WindowInv::NoInvert + } + #[doc = "Invert"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == WindowInv::Invert + } +} +#[doc = "Field `WINDOW_INV` writer - WINDOW/SAMPLE Signal Invert"] +pub type WindowInvW<'a, REG> = crate::BitWriter<'a, REG, WindowInv>; +impl<'a, REG> WindowInvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Do not invert"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(WindowInv::NoInvert) + } + #[doc = "Invert"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(WindowInv::Invert) + } +} +#[doc = "COUT Event Window Close\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WindowCls { + #[doc = "0: COUT event cannot close the window"] + NoClose = 0, + #[doc = "1: COUT event can close the window"] + Close = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WindowCls) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WINDOW_CLS` reader - COUT Event Window Close"] +pub type WindowClsR = crate::BitReader; +impl WindowClsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WindowCls { + match self.bits { + false => WindowCls::NoClose, + true => WindowCls::Close, + } + } + #[doc = "COUT event cannot close the window"] + #[inline(always)] + pub fn is_no_close(&self) -> bool { + *self == WindowCls::NoClose + } + #[doc = "COUT event can close the window"] + #[inline(always)] + pub fn is_close(&self) -> bool { + *self == WindowCls::Close + } +} +#[doc = "Field `WINDOW_CLS` writer - COUT Event Window Close"] +pub type WindowClsW<'a, REG> = crate::BitWriter<'a, REG, WindowCls>; +impl<'a, REG> WindowClsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "COUT event cannot close the window"] + #[inline(always)] + pub fn no_close(self) -> &'a mut crate::W { + self.variant(WindowCls::NoClose) + } + #[doc = "COUT event can close the window"] + #[inline(always)] + pub fn close(self) -> &'a mut crate::W { + self.variant(WindowCls::Close) + } +} +#[doc = "COUT Event Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EvtSel { + #[doc = "0: Rising edge"] + Rising = 0, + #[doc = "1: Falling edge"] + Falling = 1, + #[doc = "2: Both edges"] + Both = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EvtSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for EvtSel { + type Ux = u8; +} +impl crate::IsEnum for EvtSel {} +#[doc = "Field `EVT_SEL` reader - COUT Event Select"] +pub type EvtSelR = crate::FieldReader; +impl EvtSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(EvtSel::Rising), + 1 => Some(EvtSel::Falling), + 2 => Some(EvtSel::Both), + _ => None, + } + } + #[doc = "Rising edge"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + *self == EvtSel::Rising + } + #[doc = "Falling edge"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + *self == EvtSel::Falling + } + #[doc = "Both edges"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == EvtSel::Both + } +} +#[doc = "Field `EVT_SEL` writer - COUT Event Select"] +pub type EvtSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, EvtSel>; +impl<'a, REG> EvtSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Rising edge"] + #[inline(always)] + pub fn rising(self) -> &'a mut crate::W { + self.variant(EvtSel::Rising) + } + #[doc = "Falling edge"] + #[inline(always)] + pub fn falling(self) -> &'a mut crate::W { + self.variant(EvtSel::Falling) + } + #[doc = "Both edges"] + #[inline(always)] + pub fn both(self) -> &'a mut crate::W { + self.variant(EvtSel::Both) + } +} +#[doc = "Functional Clock Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FuncClkSel { + #[doc = "0: Select functional clock source 0"] + Func0 = 0, + #[doc = "1: Select functional clock source 1"] + Func1 = 1, + #[doc = "2: Select functional clock source 2"] + Func2 = 2, + #[doc = "3: Select functional clock source 3"] + Func3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FuncClkSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FuncClkSel { + type Ux = u8; +} +impl crate::IsEnum for FuncClkSel {} +#[doc = "Field `FUNC_CLK_SEL` reader - Functional Clock Source Select"] +pub type FuncClkSelR = crate::FieldReader; +impl FuncClkSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FuncClkSel { + match self.bits { + 0 => FuncClkSel::Func0, + 1 => FuncClkSel::Func1, + 2 => FuncClkSel::Func2, + 3 => FuncClkSel::Func3, + _ => unreachable!(), + } + } + #[doc = "Select functional clock source 0"] + #[inline(always)] + pub fn is_func0(&self) -> bool { + *self == FuncClkSel::Func0 + } + #[doc = "Select functional clock source 1"] + #[inline(always)] + pub fn is_func1(&self) -> bool { + *self == FuncClkSel::Func1 + } + #[doc = "Select functional clock source 2"] + #[inline(always)] + pub fn is_func2(&self) -> bool { + *self == FuncClkSel::Func2 + } + #[doc = "Select functional clock source 3"] + #[inline(always)] + pub fn is_func3(&self) -> bool { + *self == FuncClkSel::Func3 + } +} +#[doc = "Field `FUNC_CLK_SEL` writer - Functional Clock Source Select"] +pub type FuncClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, FuncClkSel, crate::Safe>; +impl<'a, REG> FuncClkSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select functional clock source 0"] + #[inline(always)] + pub fn func0(self) -> &'a mut crate::W { + self.variant(FuncClkSel::Func0) + } + #[doc = "Select functional clock source 1"] + #[inline(always)] + pub fn func1(self) -> &'a mut crate::W { + self.variant(FuncClkSel::Func1) + } + #[doc = "Select functional clock source 2"] + #[inline(always)] + pub fn func2(self) -> &'a mut crate::W { + self.variant(FuncClkSel::Func2) + } + #[doc = "Select functional clock source 3"] + #[inline(always)] + pub fn func3(self) -> &'a mut crate::W { + self.variant(FuncClkSel::Func3) + } +} +#[doc = "Filter Sample Count\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FiltCnt { + #[doc = "0: Filter is bypassed: COUT = COUTA"] + Bypassed = 0, + #[doc = "1: 1 consecutive sample (Comparator output is simply sampled.)"] + Sample1 = 1, + #[doc = "2: 2 consecutive samples"] + Sample2 = 2, + #[doc = "3: 3 consecutive samples"] + Sample3 = 3, + #[doc = "4: 4 consecutive samples"] + Sample4 = 4, + #[doc = "5: 5 consecutive samples"] + Sample5 = 5, + #[doc = "6: 6 consecutive samples"] + Sample6 = 6, + #[doc = "7: 7 consecutive samples"] + Sample7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FiltCnt) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FiltCnt { + type Ux = u8; +} +impl crate::IsEnum for FiltCnt {} +#[doc = "Field `FILT_CNT` reader - Filter Sample Count"] +pub type FiltCntR = crate::FieldReader; +impl FiltCntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FiltCnt { + match self.bits { + 0 => FiltCnt::Bypassed, + 1 => FiltCnt::Sample1, + 2 => FiltCnt::Sample2, + 3 => FiltCnt::Sample3, + 4 => FiltCnt::Sample4, + 5 => FiltCnt::Sample5, + 6 => FiltCnt::Sample6, + 7 => FiltCnt::Sample7, + _ => unreachable!(), + } + } + #[doc = "Filter is bypassed: COUT = COUTA"] + #[inline(always)] + pub fn is_bypassed(&self) -> bool { + *self == FiltCnt::Bypassed + } + #[doc = "1 consecutive sample (Comparator output is simply sampled.)"] + #[inline(always)] + pub fn is_sample_1(&self) -> bool { + *self == FiltCnt::Sample1 + } + #[doc = "2 consecutive samples"] + #[inline(always)] + pub fn is_sample_2(&self) -> bool { + *self == FiltCnt::Sample2 + } + #[doc = "3 consecutive samples"] + #[inline(always)] + pub fn is_sample_3(&self) -> bool { + *self == FiltCnt::Sample3 + } + #[doc = "4 consecutive samples"] + #[inline(always)] + pub fn is_sample_4(&self) -> bool { + *self == FiltCnt::Sample4 + } + #[doc = "5 consecutive samples"] + #[inline(always)] + pub fn is_sample_5(&self) -> bool { + *self == FiltCnt::Sample5 + } + #[doc = "6 consecutive samples"] + #[inline(always)] + pub fn is_sample_6(&self) -> bool { + *self == FiltCnt::Sample6 + } + #[doc = "7 consecutive samples"] + #[inline(always)] + pub fn is_sample_7(&self) -> bool { + *self == FiltCnt::Sample7 + } +} +#[doc = "Field `FILT_CNT` writer - Filter Sample Count"] +pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3, FiltCnt, crate::Safe>; +impl<'a, REG> FiltCntW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Filter is bypassed: COUT = COUTA"] + #[inline(always)] + pub fn bypassed(self) -> &'a mut crate::W { + self.variant(FiltCnt::Bypassed) + } + #[doc = "1 consecutive sample (Comparator output is simply sampled.)"] + #[inline(always)] + pub fn sample_1(self) -> &'a mut crate::W { + self.variant(FiltCnt::Sample1) + } + #[doc = "2 consecutive samples"] + #[inline(always)] + pub fn sample_2(self) -> &'a mut crate::W { + self.variant(FiltCnt::Sample2) + } + #[doc = "3 consecutive samples"] + #[inline(always)] + pub fn sample_3(self) -> &'a mut crate::W { + self.variant(FiltCnt::Sample3) + } + #[doc = "4 consecutive samples"] + #[inline(always)] + pub fn sample_4(self) -> &'a mut crate::W { + self.variant(FiltCnt::Sample4) + } + #[doc = "5 consecutive samples"] + #[inline(always)] + pub fn sample_5(self) -> &'a mut crate::W { + self.variant(FiltCnt::Sample5) + } + #[doc = "6 consecutive samples"] + #[inline(always)] + pub fn sample_6(self) -> &'a mut crate::W { + self.variant(FiltCnt::Sample6) + } + #[doc = "7 consecutive samples"] + #[inline(always)] + pub fn sample_7(self) -> &'a mut crate::W { + self.variant(FiltCnt::Sample7) + } +} +#[doc = "Field `FILT_PER` reader - Filter Sample Period"] +pub type FiltPerR = crate::FieldReader; +#[doc = "Field `FILT_PER` writer - Filter Sample Period"] +pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - Windowing Enable"] + #[inline(always)] + pub fn window_en(&self) -> WindowEnR { + WindowEnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Sampling Enable"] + #[inline(always)] + pub fn sample_en(&self) -> SampleEnR { + SampleEnR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Enable"] + #[inline(always)] + pub fn dma_en(&self) -> DmaEnR { + DmaEnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Comparator Invert"] + #[inline(always)] + pub fn cout_inv(&self) -> CoutInvR { + CoutInvR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Comparator Output Select"] + #[inline(always)] + pub fn cout_sel(&self) -> CoutSelR { + CoutSelR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Comparator Output Pin Enable"] + #[inline(always)] + pub fn cout_pen(&self) -> CoutPenR { + CoutPenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - COUTA_OW Enable"] + #[inline(always)] + pub fn couta_owen(&self) -> CoutaOwenR { + CoutaOwenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - COUTA Output Level for Closed Window"] + #[inline(always)] + pub fn couta_ow(&self) -> CoutaOwR { + CoutaOwR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - WINDOW/SAMPLE Signal Invert"] + #[inline(always)] + pub fn window_inv(&self) -> WindowInvR { + WindowInvR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - COUT Event Window Close"] + #[inline(always)] + pub fn window_cls(&self) -> WindowClsR { + WindowClsR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - COUT Event Select"] + #[inline(always)] + pub fn evt_sel(&self) -> EvtSelR { + EvtSelR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Functional Clock Source Select"] + #[inline(always)] + pub fn func_clk_sel(&self) -> FuncClkSelR { + FuncClkSelR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 16:18 - Filter Sample Count"] + #[inline(always)] + pub fn filt_cnt(&self) -> FiltCntR { + FiltCntR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 24:31 - Filter Sample Period"] + #[inline(always)] + pub fn filt_per(&self) -> FiltPerR { + FiltPerR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 0 - Windowing Enable"] + #[inline(always)] + pub fn window_en(&mut self) -> WindowEnW { + WindowEnW::new(self, 0) + } + #[doc = "Bit 1 - Sampling Enable"] + #[inline(always)] + pub fn sample_en(&mut self) -> SampleEnW { + SampleEnW::new(self, 1) + } + #[doc = "Bit 2 - DMA Enable"] + #[inline(always)] + pub fn dma_en(&mut self) -> DmaEnW { + DmaEnW::new(self, 2) + } + #[doc = "Bit 3 - Comparator Invert"] + #[inline(always)] + pub fn cout_inv(&mut self) -> CoutInvW { + CoutInvW::new(self, 3) + } + #[doc = "Bit 4 - Comparator Output Select"] + #[inline(always)] + pub fn cout_sel(&mut self) -> CoutSelW { + CoutSelW::new(self, 4) + } + #[doc = "Bit 5 - Comparator Output Pin Enable"] + #[inline(always)] + pub fn cout_pen(&mut self) -> CoutPenW { + CoutPenW::new(self, 5) + } + #[doc = "Bit 6 - COUTA_OW Enable"] + #[inline(always)] + pub fn couta_owen(&mut self) -> CoutaOwenW { + CoutaOwenW::new(self, 6) + } + #[doc = "Bit 7 - COUTA Output Level for Closed Window"] + #[inline(always)] + pub fn couta_ow(&mut self) -> CoutaOwW { + CoutaOwW::new(self, 7) + } + #[doc = "Bit 8 - WINDOW/SAMPLE Signal Invert"] + #[inline(always)] + pub fn window_inv(&mut self) -> WindowInvW { + WindowInvW::new(self, 8) + } + #[doc = "Bit 9 - COUT Event Window Close"] + #[inline(always)] + pub fn window_cls(&mut self) -> WindowClsW { + WindowClsW::new(self, 9) + } + #[doc = "Bits 10:11 - COUT Event Select"] + #[inline(always)] + pub fn evt_sel(&mut self) -> EvtSelW { + EvtSelW::new(self, 10) + } + #[doc = "Bits 12:13 - Functional Clock Source Select"] + #[inline(always)] + pub fn func_clk_sel(&mut self) -> FuncClkSelW { + FuncClkSelW::new(self, 12) + } + #[doc = "Bits 16:18 - Filter Sample Count"] + #[inline(always)] + pub fn filt_cnt(&mut self) -> FiltCntW { + FiltCntW::new(self, 16) + } + #[doc = "Bits 24:31 - Filter Sample Period"] + #[inline(always)] + pub fn filt_per(&mut self) -> FiltPerW { + FiltPerW::new(self, 24) + } +} +#[doc = "Comparator Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ccr1Spec; +impl crate::RegisterSpec for Ccr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"] +impl crate::Readable for Ccr1Spec {} +#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"] +impl crate::Writable for Ccr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CCR1 to value 0"] +impl crate::Resettable for Ccr1Spec {} diff --git a/mcxa276-pac/src/cmp0/ccr2.rs b/mcxa276-pac/src/cmp0/ccr2.rs new file mode 100644 index 000000000..9dc96d0d1 --- /dev/null +++ b/mcxa276-pac/src/cmp0/ccr2.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CCR2` reader"] +pub type R = crate::R; +#[doc = "Register `CCR2` writer"] +pub type W = crate::W; +#[doc = "CMP High Power Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CmpHpmd { + #[doc = "0: Low power (speed) comparison mode"] + Low = 0, + #[doc = "1: High power (speed) comparison mode"] + High = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CmpHpmd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP_HPMD` reader - CMP High Power Mode Select"] +pub type CmpHpmdR = crate::BitReader; +impl CmpHpmdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CmpHpmd { + match self.bits { + false => CmpHpmd::Low, + true => CmpHpmd::High, + } + } + #[doc = "Low power (speed) comparison mode"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == CmpHpmd::Low + } + #[doc = "High power (speed) comparison mode"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == CmpHpmd::High + } +} +#[doc = "Field `CMP_HPMD` writer - CMP High Power Mode Select"] +pub type CmpHpmdW<'a, REG> = crate::BitWriter<'a, REG, CmpHpmd>; +impl<'a, REG> CmpHpmdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low power (speed) comparison mode"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(CmpHpmd::Low) + } + #[doc = "High power (speed) comparison mode"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(CmpHpmd::High) + } +} +#[doc = "CMP Nano Power Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CmpNpmd { + #[doc = "0: Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."] + NoNano = 0, + #[doc = "1: Enables CMP Nano power mode."] + Nano = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CmpNpmd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP_NPMD` reader - CMP Nano Power Mode Select"] +pub type CmpNpmdR = crate::BitReader; +impl CmpNpmdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CmpNpmd { + match self.bits { + false => CmpNpmd::NoNano, + true => CmpNpmd::Nano, + } + } + #[doc = "Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."] + #[inline(always)] + pub fn is_no_nano(&self) -> bool { + *self == CmpNpmd::NoNano + } + #[doc = "Enables CMP Nano power mode."] + #[inline(always)] + pub fn is_nano(&self) -> bool { + *self == CmpNpmd::Nano + } +} +#[doc = "Field `CMP_NPMD` writer - CMP Nano Power Mode Select"] +pub type CmpNpmdW<'a, REG> = crate::BitWriter<'a, REG, CmpNpmd>; +impl<'a, REG> CmpNpmdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."] + #[inline(always)] + pub fn no_nano(self) -> &'a mut crate::W { + self.variant(CmpNpmd::NoNano) + } + #[doc = "Enables CMP Nano power mode."] + #[inline(always)] + pub fn nano(self) -> &'a mut crate::W { + self.variant(CmpNpmd::Nano) + } +} +#[doc = "Comparator Hysteresis Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Hystctr { + #[doc = "0: Level 0: Analog comparator hysteresis 0 mV."] + Level0 = 0, + #[doc = "1: Level 1: Analog comparator hysteresis 10 mV."] + Level1 = 1, + #[doc = "2: Level 2: Analog comparator hysteresis 20 mV."] + Level2 = 2, + #[doc = "3: Level 3: Analog comparator hysteresis 30 mV."] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Hystctr) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Hystctr { + type Ux = u8; +} +impl crate::IsEnum for Hystctr {} +#[doc = "Field `HYSTCTR` reader - Comparator Hysteresis Control"] +pub type HystctrR = crate::FieldReader; +impl HystctrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hystctr { + match self.bits { + 0 => Hystctr::Level0, + 1 => Hystctr::Level1, + 2 => Hystctr::Level2, + 3 => Hystctr::Level3, + _ => unreachable!(), + } + } + #[doc = "Level 0: Analog comparator hysteresis 0 mV."] + #[inline(always)] + pub fn is_level_0(&self) -> bool { + *self == Hystctr::Level0 + } + #[doc = "Level 1: Analog comparator hysteresis 10 mV."] + #[inline(always)] + pub fn is_level_1(&self) -> bool { + *self == Hystctr::Level1 + } + #[doc = "Level 2: Analog comparator hysteresis 20 mV."] + #[inline(always)] + pub fn is_level_2(&self) -> bool { + *self == Hystctr::Level2 + } + #[doc = "Level 3: Analog comparator hysteresis 30 mV."] + #[inline(always)] + pub fn is_level_3(&self) -> bool { + *self == Hystctr::Level3 + } +} +#[doc = "Field `HYSTCTR` writer - Comparator Hysteresis Control"] +pub type HystctrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hystctr, crate::Safe>; +impl<'a, REG> HystctrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Level 0: Analog comparator hysteresis 0 mV."] + #[inline(always)] + pub fn level_0(self) -> &'a mut crate::W { + self.variant(Hystctr::Level0) + } + #[doc = "Level 1: Analog comparator hysteresis 10 mV."] + #[inline(always)] + pub fn level_1(self) -> &'a mut crate::W { + self.variant(Hystctr::Level1) + } + #[doc = "Level 2: Analog comparator hysteresis 20 mV."] + #[inline(always)] + pub fn level_2(self) -> &'a mut crate::W { + self.variant(Hystctr::Level2) + } + #[doc = "Level 3: Analog comparator hysteresis 30 mV."] + #[inline(always)] + pub fn level_3(self) -> &'a mut crate::W { + self.variant(Hystctr::Level3) + } +} +#[doc = "Plus Input MUX Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Psel { + #[doc = "0: Input 0p"] + Input0 = 0, + #[doc = "1: Input 1p"] + Input1 = 1, + #[doc = "2: Input 2p"] + Input2 = 2, + #[doc = "3: Input 3p"] + Input3 = 3, + #[doc = "4: Input 4p"] + Input4 = 4, + #[doc = "5: Input 5p"] + Input5 = 5, + #[doc = "7: Internal DAC output"] + Input7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Psel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Psel { + type Ux = u8; +} +impl crate::IsEnum for Psel {} +#[doc = "Field `PSEL` reader - Plus Input MUX Select"] +pub type PselR = crate::FieldReader; +impl PselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Psel::Input0), + 1 => Some(Psel::Input1), + 2 => Some(Psel::Input2), + 3 => Some(Psel::Input3), + 4 => Some(Psel::Input4), + 5 => Some(Psel::Input5), + 7 => Some(Psel::Input7), + _ => None, + } + } + #[doc = "Input 0p"] + #[inline(always)] + pub fn is_input_0(&self) -> bool { + *self == Psel::Input0 + } + #[doc = "Input 1p"] + #[inline(always)] + pub fn is_input_1(&self) -> bool { + *self == Psel::Input1 + } + #[doc = "Input 2p"] + #[inline(always)] + pub fn is_input_2(&self) -> bool { + *self == Psel::Input2 + } + #[doc = "Input 3p"] + #[inline(always)] + pub fn is_input_3(&self) -> bool { + *self == Psel::Input3 + } + #[doc = "Input 4p"] + #[inline(always)] + pub fn is_input_4(&self) -> bool { + *self == Psel::Input4 + } + #[doc = "Input 5p"] + #[inline(always)] + pub fn is_input_5(&self) -> bool { + *self == Psel::Input5 + } + #[doc = "Internal DAC output"] + #[inline(always)] + pub fn is_input_7(&self) -> bool { + *self == Psel::Input7 + } +} +#[doc = "Field `PSEL` writer - Plus Input MUX Select"] +pub type PselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Psel>; +impl<'a, REG> PselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Input 0p"] + #[inline(always)] + pub fn input_0(self) -> &'a mut crate::W { + self.variant(Psel::Input0) + } + #[doc = "Input 1p"] + #[inline(always)] + pub fn input_1(self) -> &'a mut crate::W { + self.variant(Psel::Input1) + } + #[doc = "Input 2p"] + #[inline(always)] + pub fn input_2(self) -> &'a mut crate::W { + self.variant(Psel::Input2) + } + #[doc = "Input 3p"] + #[inline(always)] + pub fn input_3(self) -> &'a mut crate::W { + self.variant(Psel::Input3) + } + #[doc = "Input 4p"] + #[inline(always)] + pub fn input_4(self) -> &'a mut crate::W { + self.variant(Psel::Input4) + } + #[doc = "Input 5p"] + #[inline(always)] + pub fn input_5(self) -> &'a mut crate::W { + self.variant(Psel::Input5) + } + #[doc = "Internal DAC output"] + #[inline(always)] + pub fn input_7(self) -> &'a mut crate::W { + self.variant(Psel::Input7) + } +} +#[doc = "Minus Input MUX Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Msel { + #[doc = "0: Input 0m"] + Input0 = 0, + #[doc = "1: Input 1m"] + Input1 = 1, + #[doc = "2: Input 2m"] + Input2 = 2, + #[doc = "3: Input 3m"] + Input3 = 3, + #[doc = "4: Input 4m"] + Input4 = 4, + #[doc = "5: Input 5m"] + Input5 = 5, + #[doc = "7: Internal DAC output"] + Input7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Msel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Msel { + type Ux = u8; +} +impl crate::IsEnum for Msel {} +#[doc = "Field `MSEL` reader - Minus Input MUX Select"] +pub type MselR = crate::FieldReader; +impl MselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Msel::Input0), + 1 => Some(Msel::Input1), + 2 => Some(Msel::Input2), + 3 => Some(Msel::Input3), + 4 => Some(Msel::Input4), + 5 => Some(Msel::Input5), + 7 => Some(Msel::Input7), + _ => None, + } + } + #[doc = "Input 0m"] + #[inline(always)] + pub fn is_input_0(&self) -> bool { + *self == Msel::Input0 + } + #[doc = "Input 1m"] + #[inline(always)] + pub fn is_input_1(&self) -> bool { + *self == Msel::Input1 + } + #[doc = "Input 2m"] + #[inline(always)] + pub fn is_input_2(&self) -> bool { + *self == Msel::Input2 + } + #[doc = "Input 3m"] + #[inline(always)] + pub fn is_input_3(&self) -> bool { + *self == Msel::Input3 + } + #[doc = "Input 4m"] + #[inline(always)] + pub fn is_input_4(&self) -> bool { + *self == Msel::Input4 + } + #[doc = "Input 5m"] + #[inline(always)] + pub fn is_input_5(&self) -> bool { + *self == Msel::Input5 + } + #[doc = "Internal DAC output"] + #[inline(always)] + pub fn is_input_7(&self) -> bool { + *self == Msel::Input7 + } +} +#[doc = "Field `MSEL` writer - Minus Input MUX Select"] +pub type MselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Msel>; +impl<'a, REG> MselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Input 0m"] + #[inline(always)] + pub fn input_0(self) -> &'a mut crate::W { + self.variant(Msel::Input0) + } + #[doc = "Input 1m"] + #[inline(always)] + pub fn input_1(self) -> &'a mut crate::W { + self.variant(Msel::Input1) + } + #[doc = "Input 2m"] + #[inline(always)] + pub fn input_2(self) -> &'a mut crate::W { + self.variant(Msel::Input2) + } + #[doc = "Input 3m"] + #[inline(always)] + pub fn input_3(self) -> &'a mut crate::W { + self.variant(Msel::Input3) + } + #[doc = "Input 4m"] + #[inline(always)] + pub fn input_4(self) -> &'a mut crate::W { + self.variant(Msel::Input4) + } + #[doc = "Input 5m"] + #[inline(always)] + pub fn input_5(self) -> &'a mut crate::W { + self.variant(Msel::Input5) + } + #[doc = "Internal DAC output"] + #[inline(always)] + pub fn input_7(self) -> &'a mut crate::W { + self.variant(Msel::Input7) + } +} +impl R { + #[doc = "Bit 0 - CMP High Power Mode Select"] + #[inline(always)] + pub fn cmp_hpmd(&self) -> CmpHpmdR { + CmpHpmdR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CMP Nano Power Mode Select"] + #[inline(always)] + pub fn cmp_npmd(&self) -> CmpNpmdR { + CmpNpmdR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:5 - Comparator Hysteresis Control"] + #[inline(always)] + pub fn hystctr(&self) -> HystctrR { + HystctrR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 16:18 - Plus Input MUX Select"] + #[inline(always)] + pub fn psel(&self) -> PselR { + PselR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 20:22 - Minus Input MUX Select"] + #[inline(always)] + pub fn msel(&self) -> MselR { + MselR::new(((self.bits >> 20) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - CMP High Power Mode Select"] + #[inline(always)] + pub fn cmp_hpmd(&mut self) -> CmpHpmdW { + CmpHpmdW::new(self, 0) + } + #[doc = "Bit 1 - CMP Nano Power Mode Select"] + #[inline(always)] + pub fn cmp_npmd(&mut self) -> CmpNpmdW { + CmpNpmdW::new(self, 1) + } + #[doc = "Bits 4:5 - Comparator Hysteresis Control"] + #[inline(always)] + pub fn hystctr(&mut self) -> HystctrW { + HystctrW::new(self, 4) + } + #[doc = "Bits 16:18 - Plus Input MUX Select"] + #[inline(always)] + pub fn psel(&mut self) -> PselW { + PselW::new(self, 16) + } + #[doc = "Bits 20:22 - Minus Input MUX Select"] + #[inline(always)] + pub fn msel(&mut self) -> MselW { + MselW::new(self, 20) + } +} +#[doc = "Comparator Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ccr2Spec; +impl crate::RegisterSpec for Ccr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"] +impl crate::Readable for Ccr2Spec {} +#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"] +impl crate::Writable for Ccr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CCR2 to value 0"] +impl crate::Resettable for Ccr2Spec {} diff --git a/mcxa276-pac/src/cmp0/csr.rs b/mcxa276-pac/src/cmp0/csr.rs new file mode 100644 index 000000000..61ed95e3f --- /dev/null +++ b/mcxa276-pac/src/cmp0/csr.rs @@ -0,0 +1,218 @@ +#[doc = "Register `CSR` reader"] +pub type R = crate::R; +#[doc = "Register `CSR` writer"] +pub type W = crate::W; +#[doc = "Analog Comparator Flag Rising\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cfr { + #[doc = "0: Not detected"] + NotDetected = 0, + #[doc = "1: Detected"] + Detected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cfr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CFR` reader - Analog Comparator Flag Rising"] +pub type CfrR = crate::BitReader; +impl CfrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cfr { + match self.bits { + false => Cfr::NotDetected, + true => Cfr::Detected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == Cfr::NotDetected + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == Cfr::Detected + } +} +#[doc = "Field `CFR` writer - Analog Comparator Flag Rising"] +pub type CfrW<'a, REG> = crate::BitWriter1C<'a, REG, Cfr>; +impl<'a, REG> CfrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut crate::W { + self.variant(Cfr::NotDetected) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut crate::W { + self.variant(Cfr::Detected) + } +} +#[doc = "Analog Comparator Flag Falling\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cff { + #[doc = "0: Not detected"] + NotDetected = 0, + #[doc = "1: Detected"] + Detected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cff) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CFF` reader - Analog Comparator Flag Falling"] +pub type CffR = crate::BitReader; +impl CffR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cff { + match self.bits { + false => Cff::NotDetected, + true => Cff::Detected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == Cff::NotDetected + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == Cff::Detected + } +} +#[doc = "Field `CFF` writer - Analog Comparator Flag Falling"] +pub type CffW<'a, REG> = crate::BitWriter1C<'a, REG, Cff>; +impl<'a, REG> CffW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut crate::W { + self.variant(Cff::NotDetected) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut crate::W { + self.variant(Cff::Detected) + } +} +#[doc = "Round-Robin Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rrf { + #[doc = "0: Not detected"] + NotDetected = 0, + #[doc = "1: Detected"] + Detected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rrf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRF` reader - Round-Robin Flag"] +pub type RrfR = crate::BitReader; +impl RrfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rrf { + match self.bits { + false => Rrf::NotDetected, + true => Rrf::Detected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == Rrf::NotDetected + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == Rrf::Detected + } +} +#[doc = "Field `RRF` writer - Round-Robin Flag"] +pub type RrfW<'a, REG> = crate::BitWriter1C<'a, REG, Rrf>; +impl<'a, REG> RrfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut crate::W { + self.variant(Rrf::NotDetected) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut crate::W { + self.variant(Rrf::Detected) + } +} +#[doc = "Field `COUT` reader - Analog Comparator Output"] +pub type CoutR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Analog Comparator Flag Rising"] + #[inline(always)] + pub fn cfr(&self) -> CfrR { + CfrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Analog Comparator Flag Falling"] + #[inline(always)] + pub fn cff(&self) -> CffR { + CffR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Round-Robin Flag"] + #[inline(always)] + pub fn rrf(&self) -> RrfR { + RrfR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Analog Comparator Output"] + #[inline(always)] + pub fn cout(&self) -> CoutR { + CoutR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Analog Comparator Flag Rising"] + #[inline(always)] + pub fn cfr(&mut self) -> CfrW { + CfrW::new(self, 0) + } + #[doc = "Bit 1 - Analog Comparator Flag Falling"] + #[inline(always)] + pub fn cff(&mut self) -> CffW { + CffW::new(self, 1) + } + #[doc = "Bit 2 - Round-Robin Flag"] + #[inline(always)] + pub fn rrf(&mut self) -> RrfW { + RrfW::new(self, 2) + } +} +#[doc = "Comparator Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CsrSpec; +impl crate::RegisterSpec for CsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CsrSpec {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] +impl crate::Writable for CsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07; +} +#[doc = "`reset()` method sets CSR to value 0"] +impl crate::Resettable for CsrSpec {} diff --git a/mcxa276-pac/src/cmp0/dcr.rs b/mcxa276-pac/src/cmp0/dcr.rs new file mode 100644 index 000000000..4f96bbdc7 --- /dev/null +++ b/mcxa276-pac/src/cmp0/dcr.rs @@ -0,0 +1,224 @@ +#[doc = "Register `DCR` reader"] +pub type R = crate::R; +#[doc = "Register `DCR` writer"] +pub type W = crate::W; +#[doc = "DAC Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DacEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DacEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAC_EN` reader - DAC Enable"] +pub type DacEnR = crate::BitReader; +impl DacEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DacEn { + match self.bits { + false => DacEn::Disable, + true => DacEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DacEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DacEn::Enable + } +} +#[doc = "Field `DAC_EN` writer - DAC Enable"] +pub type DacEnW<'a, REG> = crate::BitWriter<'a, REG, DacEn>; +impl<'a, REG> DacEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DacEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DacEn::Enable) + } +} +#[doc = "DAC High Power Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DacHpmd { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DacHpmd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAC_HPMD` reader - DAC High Power Mode"] +pub type DacHpmdR = crate::BitReader; +impl DacHpmdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DacHpmd { + match self.bits { + false => DacHpmd::Disable, + true => DacHpmd::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DacHpmd::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DacHpmd::Enable + } +} +#[doc = "Field `DAC_HPMD` writer - DAC High Power Mode"] +pub type DacHpmdW<'a, REG> = crate::BitWriter<'a, REG, DacHpmd>; +impl<'a, REG> DacHpmdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DacHpmd::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DacHpmd::Enable) + } +} +#[doc = "DAC Reference High Voltage Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Vrsel { + #[doc = "0: VREFH0"] + Vref0 = 0, + #[doc = "1: VREFH1"] + Vref1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Vrsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VRSEL` reader - DAC Reference High Voltage Source Select"] +pub type VrselR = crate::BitReader; +impl VrselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Vrsel { + match self.bits { + false => Vrsel::Vref0, + true => Vrsel::Vref1, + } + } + #[doc = "VREFH0"] + #[inline(always)] + pub fn is_vref0(&self) -> bool { + *self == Vrsel::Vref0 + } + #[doc = "VREFH1"] + #[inline(always)] + pub fn is_vref1(&self) -> bool { + *self == Vrsel::Vref1 + } +} +#[doc = "Field `VRSEL` writer - DAC Reference High Voltage Source Select"] +pub type VrselW<'a, REG> = crate::BitWriter<'a, REG, Vrsel>; +impl<'a, REG> VrselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "VREFH0"] + #[inline(always)] + pub fn vref0(self) -> &'a mut crate::W { + self.variant(Vrsel::Vref0) + } + #[doc = "VREFH1"] + #[inline(always)] + pub fn vref1(self) -> &'a mut crate::W { + self.variant(Vrsel::Vref1) + } +} +#[doc = "Field `DAC_DATA` reader - DAC Output Voltage Select"] +pub type DacDataR = crate::FieldReader; +#[doc = "Field `DAC_DATA` writer - DAC Output Voltage Select"] +pub type DacDataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - DAC Enable"] + #[inline(always)] + pub fn dac_en(&self) -> DacEnR { + DacEnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DAC High Power Mode"] + #[inline(always)] + pub fn dac_hpmd(&self) -> DacHpmdR { + DacHpmdR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - DAC Reference High Voltage Source Select"] + #[inline(always)] + pub fn vrsel(&self) -> VrselR { + VrselR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 16:23 - DAC Output Voltage Select"] + #[inline(always)] + pub fn dac_data(&self) -> DacDataR { + DacDataR::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 0 - DAC Enable"] + #[inline(always)] + pub fn dac_en(&mut self) -> DacEnW { + DacEnW::new(self, 0) + } + #[doc = "Bit 1 - DAC High Power Mode"] + #[inline(always)] + pub fn dac_hpmd(&mut self) -> DacHpmdW { + DacHpmdW::new(self, 1) + } + #[doc = "Bit 8 - DAC Reference High Voltage Source Select"] + #[inline(always)] + pub fn vrsel(&mut self) -> VrselW { + VrselW::new(self, 8) + } + #[doc = "Bits 16:23 - DAC Output Voltage Select"] + #[inline(always)] + pub fn dac_data(&mut self) -> DacDataW { + DacDataW::new(self, 16) + } +} +#[doc = "DAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DcrSpec; +impl crate::RegisterSpec for DcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcr::R`](R) reader structure"] +impl crate::Readable for DcrSpec {} +#[doc = "`write(|w| ..)` method takes [`dcr::W`](W) writer structure"] +impl crate::Writable for DcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DCR to value 0"] +impl crate::Resettable for DcrSpec {} diff --git a/mcxa276-pac/src/cmp0/ier.rs b/mcxa276-pac/src/cmp0/ier.rs new file mode 100644 index 000000000..779ec81ca --- /dev/null +++ b/mcxa276-pac/src/cmp0/ier.rs @@ -0,0 +1,210 @@ +#[doc = "Register `IER` reader"] +pub type R = crate::R; +#[doc = "Register `IER` writer"] +pub type W = crate::W; +#[doc = "Comparator Flag Rising Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CfrIe { + #[doc = "0: Disables the comparator flag rising interrupt."] + Disable = 0, + #[doc = "1: Enables the comparator flag rising interrupt when CFR is set."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CfrIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CFR_IE` reader - Comparator Flag Rising Interrupt Enable"] +pub type CfrIeR = crate::BitReader; +impl CfrIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CfrIe { + match self.bits { + false => CfrIe::Disable, + true => CfrIe::Enable, + } + } + #[doc = "Disables the comparator flag rising interrupt."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CfrIe::Disable + } + #[doc = "Enables the comparator flag rising interrupt when CFR is set."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CfrIe::Enable + } +} +#[doc = "Field `CFR_IE` writer - Comparator Flag Rising Interrupt Enable"] +pub type CfrIeW<'a, REG> = crate::BitWriter<'a, REG, CfrIe>; +impl<'a, REG> CfrIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables the comparator flag rising interrupt."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(CfrIe::Disable) + } + #[doc = "Enables the comparator flag rising interrupt when CFR is set."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(CfrIe::Enable) + } +} +#[doc = "Comparator Flag Falling Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CffIe { + #[doc = "0: Disables the comparator flag falling interrupt."] + Disable = 0, + #[doc = "1: Enables the comparator flag falling interrupt when CFF is set."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CffIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CFF_IE` reader - Comparator Flag Falling Interrupt Enable"] +pub type CffIeR = crate::BitReader; +impl CffIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CffIe { + match self.bits { + false => CffIe::Disable, + true => CffIe::Enable, + } + } + #[doc = "Disables the comparator flag falling interrupt."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CffIe::Disable + } + #[doc = "Enables the comparator flag falling interrupt when CFF is set."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CffIe::Enable + } +} +#[doc = "Field `CFF_IE` writer - Comparator Flag Falling Interrupt Enable"] +pub type CffIeW<'a, REG> = crate::BitWriter<'a, REG, CffIe>; +impl<'a, REG> CffIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables the comparator flag falling interrupt."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(CffIe::Disable) + } + #[doc = "Enables the comparator flag falling interrupt when CFF is set."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(CffIe::Enable) + } +} +#[doc = "Round-Robin Flag Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrfIe { + #[doc = "0: Disables the round-robin flag interrupt."] + Disable = 0, + #[doc = "1: Enables the round-robin flag interrupt when the comparison result changes for a given channel."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrfIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRF_IE` reader - Round-Robin Flag Interrupt Enable"] +pub type RrfIeR = crate::BitReader; +impl RrfIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrfIe { + match self.bits { + false => RrfIe::Disable, + true => RrfIe::Enable, + } + } + #[doc = "Disables the round-robin flag interrupt."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrfIe::Disable + } + #[doc = "Enables the round-robin flag interrupt when the comparison result changes for a given channel."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrfIe::Enable + } +} +#[doc = "Field `RRF_IE` writer - Round-Robin Flag Interrupt Enable"] +pub type RrfIeW<'a, REG> = crate::BitWriter<'a, REG, RrfIe>; +impl<'a, REG> RrfIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables the round-robin flag interrupt."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrfIe::Disable) + } + #[doc = "Enables the round-robin flag interrupt when the comparison result changes for a given channel."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrfIe::Enable) + } +} +impl R { + #[doc = "Bit 0 - Comparator Flag Rising Interrupt Enable"] + #[inline(always)] + pub fn cfr_ie(&self) -> CfrIeR { + CfrIeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator Flag Falling Interrupt Enable"] + #[inline(always)] + pub fn cff_ie(&self) -> CffIeR { + CffIeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Round-Robin Flag Interrupt Enable"] + #[inline(always)] + pub fn rrf_ie(&self) -> RrfIeR { + RrfIeR::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator Flag Rising Interrupt Enable"] + #[inline(always)] + pub fn cfr_ie(&mut self) -> CfrIeW { + CfrIeW::new(self, 0) + } + #[doc = "Bit 1 - Comparator Flag Falling Interrupt Enable"] + #[inline(always)] + pub fn cff_ie(&mut self) -> CffIeW { + CffIeW::new(self, 1) + } + #[doc = "Bit 2 - Round-Robin Flag Interrupt Enable"] + #[inline(always)] + pub fn rrf_ie(&mut self) -> RrfIeW { + RrfIeW::new(self, 2) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IerSpec; +impl crate::RegisterSpec for IerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IerSpec {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] +impl crate::Writable for IerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/cmp0/param.rs b/mcxa276-pac/src/cmp0/param.rs new file mode 100644 index 000000000..ae1716e32 --- /dev/null +++ b/mcxa276-pac/src/cmp0/param.rs @@ -0,0 +1,102 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "DAC Resolution\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DacRes { + #[doc = "0: 4-bit DAC"] + Reso4 = 0, + #[doc = "1: 6-bit DAC"] + Reso6 = 1, + #[doc = "2: 8-bit DAC"] + Reso8 = 2, + #[doc = "3: 10-bit DAC"] + Reso10 = 3, + #[doc = "4: 12-bit DAC"] + Reso12 = 4, + #[doc = "5: 14-bit DAC"] + Reso14 = 5, + #[doc = "6: 16-bit DAC"] + Reso16 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DacRes) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DacRes { + type Ux = u8; +} +impl crate::IsEnum for DacRes {} +#[doc = "Field `DAC_RES` reader - DAC Resolution"] +pub type DacResR = crate::FieldReader; +impl DacResR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DacRes::Reso4), + 1 => Some(DacRes::Reso6), + 2 => Some(DacRes::Reso8), + 3 => Some(DacRes::Reso10), + 4 => Some(DacRes::Reso12), + 5 => Some(DacRes::Reso14), + 6 => Some(DacRes::Reso16), + _ => None, + } + } + #[doc = "4-bit DAC"] + #[inline(always)] + pub fn is_reso_4(&self) -> bool { + *self == DacRes::Reso4 + } + #[doc = "6-bit DAC"] + #[inline(always)] + pub fn is_reso_6(&self) -> bool { + *self == DacRes::Reso6 + } + #[doc = "8-bit DAC"] + #[inline(always)] + pub fn is_reso_8(&self) -> bool { + *self == DacRes::Reso8 + } + #[doc = "10-bit DAC"] + #[inline(always)] + pub fn is_reso_10(&self) -> bool { + *self == DacRes::Reso10 + } + #[doc = "12-bit DAC"] + #[inline(always)] + pub fn is_reso_12(&self) -> bool { + *self == DacRes::Reso12 + } + #[doc = "14-bit DAC"] + #[inline(always)] + pub fn is_reso_14(&self) -> bool { + *self == DacRes::Reso14 + } + #[doc = "16-bit DAC"] + #[inline(always)] + pub fn is_reso_16(&self) -> bool { + *self == DacRes::Reso16 + } +} +impl R { + #[doc = "Bits 0:3 - DAC Resolution"] + #[inline(always)] + pub fn dac_res(&self) -> DacResR { + DacResR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x02"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x02; +} diff --git a/mcxa276-pac/src/cmp0/rrcr0.rs b/mcxa276-pac/src/cmp0/rrcr0.rs new file mode 100644 index 000000000..308dcbd49 --- /dev/null +++ b/mcxa276-pac/src/cmp0/rrcr0.rs @@ -0,0 +1,1018 @@ +#[doc = "Register `RRCR0` reader"] +pub type R = crate::R; +#[doc = "Register `RRCR0` writer"] +pub type W = crate::W; +#[doc = "Round-Robin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_EN` reader - Round-Robin Enable"] +pub type RrEnR = crate::BitReader; +impl RrEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrEn { + match self.bits { + false => RrEn::Disable, + true => RrEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrEn::Enable + } +} +#[doc = "Field `RR_EN` writer - Round-Robin Enable"] +pub type RrEnW<'a, REG> = crate::BitWriter<'a, REG, RrEn>; +impl<'a, REG> RrEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrEn::Enable) + } +} +#[doc = "Round-Robin Trigger Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrTrgSel { + #[doc = "0: External trigger"] + Enable = 0, + #[doc = "1: Internal trigger"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrTrgSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_TRG_SEL` reader - Round-Robin Trigger Select"] +pub type RrTrgSelR = crate::BitReader; +impl RrTrgSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrTrgSel { + match self.bits { + false => RrTrgSel::Enable, + true => RrTrgSel::Disable, + } + } + #[doc = "External trigger"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrTrgSel::Enable + } + #[doc = "Internal trigger"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrTrgSel::Disable + } +} +#[doc = "Field `RR_TRG_SEL` writer - Round-Robin Trigger Select"] +pub type RrTrgSelW<'a, REG> = crate::BitWriter<'a, REG, RrTrgSel>; +impl<'a, REG> RrTrgSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "External trigger"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrTrgSel::Enable) + } + #[doc = "Internal trigger"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrTrgSel::Disable) + } +} +#[doc = "Number of Sample Clocks\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RrNsam { + #[doc = "0: 0 clock"] + Wait0 = 0, + #[doc = "1: 1 clock"] + Wait1 = 1, + #[doc = "2: 2 clocks"] + Wait2 = 2, + #[doc = "3: 3 clocks"] + Wait3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RrNsam) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RrNsam { + type Ux = u8; +} +impl crate::IsEnum for RrNsam {} +#[doc = "Field `RR_NSAM` reader - Number of Sample Clocks"] +pub type RrNsamR = crate::FieldReader; +impl RrNsamR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrNsam { + match self.bits { + 0 => RrNsam::Wait0, + 1 => RrNsam::Wait1, + 2 => RrNsam::Wait2, + 3 => RrNsam::Wait3, + _ => unreachable!(), + } + } + #[doc = "0 clock"] + #[inline(always)] + pub fn is_wait_0(&self) -> bool { + *self == RrNsam::Wait0 + } + #[doc = "1 clock"] + #[inline(always)] + pub fn is_wait_1(&self) -> bool { + *self == RrNsam::Wait1 + } + #[doc = "2 clocks"] + #[inline(always)] + pub fn is_wait_2(&self) -> bool { + *self == RrNsam::Wait2 + } + #[doc = "3 clocks"] + #[inline(always)] + pub fn is_wait_3(&self) -> bool { + *self == RrNsam::Wait3 + } +} +#[doc = "Field `RR_NSAM` writer - Number of Sample Clocks"] +pub type RrNsamW<'a, REG> = crate::FieldWriter<'a, REG, 2, RrNsam, crate::Safe>; +impl<'a, REG> RrNsamW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "0 clock"] + #[inline(always)] + pub fn wait_0(self) -> &'a mut crate::W { + self.variant(RrNsam::Wait0) + } + #[doc = "1 clock"] + #[inline(always)] + pub fn wait_1(self) -> &'a mut crate::W { + self.variant(RrNsam::Wait1) + } + #[doc = "2 clocks"] + #[inline(always)] + pub fn wait_2(self) -> &'a mut crate::W { + self.variant(RrNsam::Wait2) + } + #[doc = "3 clocks"] + #[inline(always)] + pub fn wait_3(self) -> &'a mut crate::W { + self.variant(RrNsam::Wait3) + } +} +#[doc = "Round Robin Clock Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RrClkSel { + #[doc = "0: Select Round Robin clock Source 0"] + Rr0 = 0, + #[doc = "1: Select Round Robin clock Source 1"] + Rr1 = 1, + #[doc = "2: Select Round Robin clock Source 2"] + Rr2 = 2, + #[doc = "3: Select Round Robin clock Source 3"] + Rr3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RrClkSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RrClkSel { + type Ux = u8; +} +impl crate::IsEnum for RrClkSel {} +#[doc = "Field `RR_CLK_SEL` reader - Round Robin Clock Source Select"] +pub type RrClkSelR = crate::FieldReader; +impl RrClkSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrClkSel { + match self.bits { + 0 => RrClkSel::Rr0, + 1 => RrClkSel::Rr1, + 2 => RrClkSel::Rr2, + 3 => RrClkSel::Rr3, + _ => unreachable!(), + } + } + #[doc = "Select Round Robin clock Source 0"] + #[inline(always)] + pub fn is_rr0(&self) -> bool { + *self == RrClkSel::Rr0 + } + #[doc = "Select Round Robin clock Source 1"] + #[inline(always)] + pub fn is_rr1(&self) -> bool { + *self == RrClkSel::Rr1 + } + #[doc = "Select Round Robin clock Source 2"] + #[inline(always)] + pub fn is_rr2(&self) -> bool { + *self == RrClkSel::Rr2 + } + #[doc = "Select Round Robin clock Source 3"] + #[inline(always)] + pub fn is_rr3(&self) -> bool { + *self == RrClkSel::Rr3 + } +} +#[doc = "Field `RR_CLK_SEL` writer - Round Robin Clock Source Select"] +pub type RrClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, RrClkSel, crate::Safe>; +impl<'a, REG> RrClkSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select Round Robin clock Source 0"] + #[inline(always)] + pub fn rr0(self) -> &'a mut crate::W { + self.variant(RrClkSel::Rr0) + } + #[doc = "Select Round Robin clock Source 1"] + #[inline(always)] + pub fn rr1(self) -> &'a mut crate::W { + self.variant(RrClkSel::Rr1) + } + #[doc = "Select Round Robin clock Source 2"] + #[inline(always)] + pub fn rr2(self) -> &'a mut crate::W { + self.variant(RrClkSel::Rr2) + } + #[doc = "Select Round Robin clock Source 3"] + #[inline(always)] + pub fn rr3(self) -> &'a mut crate::W { + self.variant(RrClkSel::Rr3) + } +} +#[doc = "Initialization Delay Modulus\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RrInitmod { + #[doc = "0: 63 cycles (same as 111111b)"] + Mod63 = 0, + #[doc = "1: 1 to 63 cycles"] + Mod1_63_1 = 1, + #[doc = "2: 1 to 63 cycles"] + Mod1_63_2 = 2, + #[doc = "3: 1 to 63 cycles"] + Mod1_63_3 = 3, + #[doc = "4: 1 to 63 cycles"] + Mod1_63_4 = 4, + #[doc = "5: 1 to 63 cycles"] + Mod1_63_5 = 5, + #[doc = "6: 1 to 63 cycles"] + Mod1_63_6 = 6, + #[doc = "7: 1 to 63 cycles"] + Mod1_63_7 = 7, + #[doc = "8: 1 to 63 cycles"] + Mod1_63_8 = 8, + #[doc = "9: 1 to 63 cycles"] + Mod1_63_9 = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RrInitmod) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RrInitmod { + type Ux = u8; +} +impl crate::IsEnum for RrInitmod {} +#[doc = "Field `RR_INITMOD` reader - Initialization Delay Modulus"] +pub type RrInitmodR = crate::FieldReader; +impl RrInitmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(RrInitmod::Mod63), + 1 => Some(RrInitmod::Mod1_63_1), + 2 => Some(RrInitmod::Mod1_63_2), + 3 => Some(RrInitmod::Mod1_63_3), + 4 => Some(RrInitmod::Mod1_63_4), + 5 => Some(RrInitmod::Mod1_63_5), + 6 => Some(RrInitmod::Mod1_63_6), + 7 => Some(RrInitmod::Mod1_63_7), + 8 => Some(RrInitmod::Mod1_63_8), + 9 => Some(RrInitmod::Mod1_63_9), + _ => None, + } + } + #[doc = "63 cycles (same as 111111b)"] + #[inline(always)] + pub fn is_mod_63(&self) -> bool { + *self == RrInitmod::Mod63 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_1(&self) -> bool { + *self == RrInitmod::Mod1_63_1 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_2(&self) -> bool { + *self == RrInitmod::Mod1_63_2 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_3(&self) -> bool { + *self == RrInitmod::Mod1_63_3 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_4(&self) -> bool { + *self == RrInitmod::Mod1_63_4 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_5(&self) -> bool { + *self == RrInitmod::Mod1_63_5 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_6(&self) -> bool { + *self == RrInitmod::Mod1_63_6 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_7(&self) -> bool { + *self == RrInitmod::Mod1_63_7 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_8(&self) -> bool { + *self == RrInitmod::Mod1_63_8 + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn is_mod_1_63_9(&self) -> bool { + *self == RrInitmod::Mod1_63_9 + } +} +#[doc = "Field `RR_INITMOD` writer - Initialization Delay Modulus"] +pub type RrInitmodW<'a, REG> = crate::FieldWriter<'a, REG, 6, RrInitmod>; +impl<'a, REG> RrInitmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "63 cycles (same as 111111b)"] + #[inline(always)] + pub fn mod_63(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod63) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_1(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_1) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_2(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_2) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_3(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_3) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_4(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_4) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_5(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_5) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_6(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_6) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_7(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_7) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_8(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_8) + } + #[doc = "1 to 63 cycles"] + #[inline(always)] + pub fn mod_1_63_9(self) -> &'a mut crate::W { + self.variant(RrInitmod::Mod1_63_9) + } +} +#[doc = "Number of Sample for One Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RrSampleCnt { + #[doc = "0: 1 samples"] + Sample0 = 0, + #[doc = "1: 2 samples"] + Sample1 = 1, + #[doc = "2: 3 samples"] + Sample2 = 2, + #[doc = "3: 4 samples"] + Sample3 = 3, + #[doc = "4: 5 samples"] + Sample4 = 4, + #[doc = "5: 6 samples"] + Sample5 = 5, + #[doc = "6: 7 samples"] + Sample6 = 6, + #[doc = "7: 8 samples"] + Sample7 = 7, + #[doc = "8: 9 samples"] + Sample8 = 8, + #[doc = "9: 10 samples"] + Sample9 = 9, + #[doc = "10: 11 samples"] + Sample10 = 10, + #[doc = "11: 12 samples"] + Sample11 = 11, + #[doc = "12: 13 samples"] + Sample12 = 12, + #[doc = "13: 14 samples"] + Sample13 = 13, + #[doc = "14: 15 samples"] + Sample14 = 14, + #[doc = "15: 16 samples"] + Sample15 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RrSampleCnt) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RrSampleCnt { + type Ux = u8; +} +impl crate::IsEnum for RrSampleCnt {} +#[doc = "Field `RR_SAMPLE_CNT` reader - Number of Sample for One Channel"] +pub type RrSampleCntR = crate::FieldReader; +impl RrSampleCntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrSampleCnt { + match self.bits { + 0 => RrSampleCnt::Sample0, + 1 => RrSampleCnt::Sample1, + 2 => RrSampleCnt::Sample2, + 3 => RrSampleCnt::Sample3, + 4 => RrSampleCnt::Sample4, + 5 => RrSampleCnt::Sample5, + 6 => RrSampleCnt::Sample6, + 7 => RrSampleCnt::Sample7, + 8 => RrSampleCnt::Sample8, + 9 => RrSampleCnt::Sample9, + 10 => RrSampleCnt::Sample10, + 11 => RrSampleCnt::Sample11, + 12 => RrSampleCnt::Sample12, + 13 => RrSampleCnt::Sample13, + 14 => RrSampleCnt::Sample14, + 15 => RrSampleCnt::Sample15, + _ => unreachable!(), + } + } + #[doc = "1 samples"] + #[inline(always)] + pub fn is_sample_0(&self) -> bool { + *self == RrSampleCnt::Sample0 + } + #[doc = "2 samples"] + #[inline(always)] + pub fn is_sample_1(&self) -> bool { + *self == RrSampleCnt::Sample1 + } + #[doc = "3 samples"] + #[inline(always)] + pub fn is_sample_2(&self) -> bool { + *self == RrSampleCnt::Sample2 + } + #[doc = "4 samples"] + #[inline(always)] + pub fn is_sample_3(&self) -> bool { + *self == RrSampleCnt::Sample3 + } + #[doc = "5 samples"] + #[inline(always)] + pub fn is_sample_4(&self) -> bool { + *self == RrSampleCnt::Sample4 + } + #[doc = "6 samples"] + #[inline(always)] + pub fn is_sample_5(&self) -> bool { + *self == RrSampleCnt::Sample5 + } + #[doc = "7 samples"] + #[inline(always)] + pub fn is_sample_6(&self) -> bool { + *self == RrSampleCnt::Sample6 + } + #[doc = "8 samples"] + #[inline(always)] + pub fn is_sample_7(&self) -> bool { + *self == RrSampleCnt::Sample7 + } + #[doc = "9 samples"] + #[inline(always)] + pub fn is_sample_8(&self) -> bool { + *self == RrSampleCnt::Sample8 + } + #[doc = "10 samples"] + #[inline(always)] + pub fn is_sample_9(&self) -> bool { + *self == RrSampleCnt::Sample9 + } + #[doc = "11 samples"] + #[inline(always)] + pub fn is_sample_10(&self) -> bool { + *self == RrSampleCnt::Sample10 + } + #[doc = "12 samples"] + #[inline(always)] + pub fn is_sample_11(&self) -> bool { + *self == RrSampleCnt::Sample11 + } + #[doc = "13 samples"] + #[inline(always)] + pub fn is_sample_12(&self) -> bool { + *self == RrSampleCnt::Sample12 + } + #[doc = "14 samples"] + #[inline(always)] + pub fn is_sample_13(&self) -> bool { + *self == RrSampleCnt::Sample13 + } + #[doc = "15 samples"] + #[inline(always)] + pub fn is_sample_14(&self) -> bool { + *self == RrSampleCnt::Sample14 + } + #[doc = "16 samples"] + #[inline(always)] + pub fn is_sample_15(&self) -> bool { + *self == RrSampleCnt::Sample15 + } +} +#[doc = "Field `RR_SAMPLE_CNT` writer - Number of Sample for One Channel"] +pub type RrSampleCntW<'a, REG> = crate::FieldWriter<'a, REG, 4, RrSampleCnt, crate::Safe>; +impl<'a, REG> RrSampleCntW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1 samples"] + #[inline(always)] + pub fn sample_0(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample0) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn sample_1(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample1) + } + #[doc = "3 samples"] + #[inline(always)] + pub fn sample_2(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn sample_3(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample3) + } + #[doc = "5 samples"] + #[inline(always)] + pub fn sample_4(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample4) + } + #[doc = "6 samples"] + #[inline(always)] + pub fn sample_5(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample5) + } + #[doc = "7 samples"] + #[inline(always)] + pub fn sample_6(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample6) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn sample_7(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample7) + } + #[doc = "9 samples"] + #[inline(always)] + pub fn sample_8(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample8) + } + #[doc = "10 samples"] + #[inline(always)] + pub fn sample_9(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample9) + } + #[doc = "11 samples"] + #[inline(always)] + pub fn sample_10(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample10) + } + #[doc = "12 samples"] + #[inline(always)] + pub fn sample_11(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample11) + } + #[doc = "13 samples"] + #[inline(always)] + pub fn sample_12(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample12) + } + #[doc = "14 samples"] + #[inline(always)] + pub fn sample_13(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample13) + } + #[doc = "15 samples"] + #[inline(always)] + pub fn sample_14(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample14) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn sample_15(self) -> &'a mut crate::W { + self.variant(RrSampleCnt::Sample15) + } +} +#[doc = "Sample Time Threshold\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RrSampleThreshold { + #[doc = "0: At least 1 sampled \"1\", the final result is \"1\""] + Sample0 = 0, + #[doc = "1: At least 2 sampled \"1\", the final result is \"1\""] + Sample1 = 1, + #[doc = "2: At least 3 sampled \"1\", the final result is \"1\""] + Sample2 = 2, + #[doc = "3: At least 4 sampled \"1\", the final result is \"1\""] + Sample3 = 3, + #[doc = "4: At least 5 sampled \"1\", the final result is \"1\""] + Sample4 = 4, + #[doc = "5: At least 6 sampled \"1\", the final result is \"1\""] + Sample5 = 5, + #[doc = "6: At least 7 sampled \"1\", the final result is \"1\""] + Sample6 = 6, + #[doc = "7: At least 8 sampled \"1\", the final result is \"1\""] + Sample7 = 7, + #[doc = "8: At least 9 sampled \"1\", the final result is \"1\""] + Sample8 = 8, + #[doc = "9: At least 10 sampled \"1\", the final result is \"1\""] + Sample9 = 9, + #[doc = "10: At least 11 sampled \"1\", the final result is \"1\""] + Sample10 = 10, + #[doc = "11: At least 12 sampled \"1\", the final result is \"1\""] + Sample11 = 11, + #[doc = "12: At least 13 sampled \"1\", the final result is \"1\""] + Sample12 = 12, + #[doc = "13: At least 14 sampled \"1\", the final result is \"1\""] + Sample13 = 13, + #[doc = "14: At least 15 sampled \"1\", the final result is \"1\""] + Sample14 = 14, + #[doc = "15: At least 16 sampled \"1\", the final result is \"1\""] + Sample15 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RrSampleThreshold) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RrSampleThreshold { + type Ux = u8; +} +impl crate::IsEnum for RrSampleThreshold {} +#[doc = "Field `RR_SAMPLE_THRESHOLD` reader - Sample Time Threshold"] +pub type RrSampleThresholdR = crate::FieldReader; +impl RrSampleThresholdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrSampleThreshold { + match self.bits { + 0 => RrSampleThreshold::Sample0, + 1 => RrSampleThreshold::Sample1, + 2 => RrSampleThreshold::Sample2, + 3 => RrSampleThreshold::Sample3, + 4 => RrSampleThreshold::Sample4, + 5 => RrSampleThreshold::Sample5, + 6 => RrSampleThreshold::Sample6, + 7 => RrSampleThreshold::Sample7, + 8 => RrSampleThreshold::Sample8, + 9 => RrSampleThreshold::Sample9, + 10 => RrSampleThreshold::Sample10, + 11 => RrSampleThreshold::Sample11, + 12 => RrSampleThreshold::Sample12, + 13 => RrSampleThreshold::Sample13, + 14 => RrSampleThreshold::Sample14, + 15 => RrSampleThreshold::Sample15, + _ => unreachable!(), + } + } + #[doc = "At least 1 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_0(&self) -> bool { + *self == RrSampleThreshold::Sample0 + } + #[doc = "At least 2 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_1(&self) -> bool { + *self == RrSampleThreshold::Sample1 + } + #[doc = "At least 3 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_2(&self) -> bool { + *self == RrSampleThreshold::Sample2 + } + #[doc = "At least 4 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_3(&self) -> bool { + *self == RrSampleThreshold::Sample3 + } + #[doc = "At least 5 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_4(&self) -> bool { + *self == RrSampleThreshold::Sample4 + } + #[doc = "At least 6 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_5(&self) -> bool { + *self == RrSampleThreshold::Sample5 + } + #[doc = "At least 7 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_6(&self) -> bool { + *self == RrSampleThreshold::Sample6 + } + #[doc = "At least 8 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_7(&self) -> bool { + *self == RrSampleThreshold::Sample7 + } + #[doc = "At least 9 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_8(&self) -> bool { + *self == RrSampleThreshold::Sample8 + } + #[doc = "At least 10 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_9(&self) -> bool { + *self == RrSampleThreshold::Sample9 + } + #[doc = "At least 11 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_10(&self) -> bool { + *self == RrSampleThreshold::Sample10 + } + #[doc = "At least 12 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_11(&self) -> bool { + *self == RrSampleThreshold::Sample11 + } + #[doc = "At least 13 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_12(&self) -> bool { + *self == RrSampleThreshold::Sample12 + } + #[doc = "At least 14 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_13(&self) -> bool { + *self == RrSampleThreshold::Sample13 + } + #[doc = "At least 15 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_14(&self) -> bool { + *self == RrSampleThreshold::Sample14 + } + #[doc = "At least 16 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn is_sample_15(&self) -> bool { + *self == RrSampleThreshold::Sample15 + } +} +#[doc = "Field `RR_SAMPLE_THRESHOLD` writer - Sample Time Threshold"] +pub type RrSampleThresholdW<'a, REG> = + crate::FieldWriter<'a, REG, 4, RrSampleThreshold, crate::Safe>; +impl<'a, REG> RrSampleThresholdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "At least 1 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_0(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample0) + } + #[doc = "At least 2 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_1(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample1) + } + #[doc = "At least 3 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_2(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample2) + } + #[doc = "At least 4 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_3(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample3) + } + #[doc = "At least 5 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_4(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample4) + } + #[doc = "At least 6 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_5(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample5) + } + #[doc = "At least 7 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_6(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample6) + } + #[doc = "At least 8 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_7(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample7) + } + #[doc = "At least 9 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_8(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample8) + } + #[doc = "At least 10 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_9(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample9) + } + #[doc = "At least 11 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_10(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample10) + } + #[doc = "At least 12 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_11(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample11) + } + #[doc = "At least 13 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_12(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample12) + } + #[doc = "At least 14 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_13(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample13) + } + #[doc = "At least 15 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_14(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample14) + } + #[doc = "At least 16 sampled \"1\", the final result is \"1\""] + #[inline(always)] + pub fn sample_15(self) -> &'a mut crate::W { + self.variant(RrSampleThreshold::Sample15) + } +} +impl R { + #[doc = "Bit 0 - Round-Robin Enable"] + #[inline(always)] + pub fn rr_en(&self) -> RrEnR { + RrEnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Round-Robin Trigger Select"] + #[inline(always)] + pub fn rr_trg_sel(&self) -> RrTrgSelR { + RrTrgSelR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 8:9 - Number of Sample Clocks"] + #[inline(always)] + pub fn rr_nsam(&self) -> RrNsamR { + RrNsamR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 12:13 - Round Robin Clock Source Select"] + #[inline(always)] + pub fn rr_clk_sel(&self) -> RrClkSelR { + RrClkSelR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 16:21 - Initialization Delay Modulus"] + #[inline(always)] + pub fn rr_initmod(&self) -> RrInitmodR { + RrInitmodR::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:27 - Number of Sample for One Channel"] + #[inline(always)] + pub fn rr_sample_cnt(&self) -> RrSampleCntR { + RrSampleCntR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Sample Time Threshold"] + #[inline(always)] + pub fn rr_sample_threshold(&self) -> RrSampleThresholdR { + RrSampleThresholdR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Round-Robin Enable"] + #[inline(always)] + pub fn rr_en(&mut self) -> RrEnW { + RrEnW::new(self, 0) + } + #[doc = "Bit 1 - Round-Robin Trigger Select"] + #[inline(always)] + pub fn rr_trg_sel(&mut self) -> RrTrgSelW { + RrTrgSelW::new(self, 1) + } + #[doc = "Bits 8:9 - Number of Sample Clocks"] + #[inline(always)] + pub fn rr_nsam(&mut self) -> RrNsamW { + RrNsamW::new(self, 8) + } + #[doc = "Bits 12:13 - Round Robin Clock Source Select"] + #[inline(always)] + pub fn rr_clk_sel(&mut self) -> RrClkSelW { + RrClkSelW::new(self, 12) + } + #[doc = "Bits 16:21 - Initialization Delay Modulus"] + #[inline(always)] + pub fn rr_initmod(&mut self) -> RrInitmodW { + RrInitmodW::new(self, 16) + } + #[doc = "Bits 24:27 - Number of Sample for One Channel"] + #[inline(always)] + pub fn rr_sample_cnt(&mut self) -> RrSampleCntW { + RrSampleCntW::new(self, 24) + } + #[doc = "Bits 28:31 - Sample Time Threshold"] + #[inline(always)] + pub fn rr_sample_threshold(&mut self) -> RrSampleThresholdW { + RrSampleThresholdW::new(self, 28) + } +} +#[doc = "Round Robin Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rrcr0Spec; +impl crate::RegisterSpec for Rrcr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rrcr0::R`](R) reader structure"] +impl crate::Readable for Rrcr0Spec {} +#[doc = "`write(|w| ..)` method takes [`rrcr0::W`](W) writer structure"] +impl crate::Writable for Rrcr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RRCR0 to value 0"] +impl crate::Resettable for Rrcr0Spec {} diff --git a/mcxa276-pac/src/cmp0/rrcr1.rs b/mcxa276-pac/src/cmp0/rrcr1.rs new file mode 100644 index 000000000..5f4eac415 --- /dev/null +++ b/mcxa276-pac/src/cmp0/rrcr1.rs @@ -0,0 +1,736 @@ +#[doc = "Register `RRCR1` reader"] +pub type R = crate::R; +#[doc = "Register `RRCR1` writer"] +pub type W = crate::W; +#[doc = "Channel 0 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh0en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh0en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH0EN` reader - Channel 0 Input Enable in Trigger Mode"] +pub type RrCh0enR = crate::BitReader; +impl RrCh0enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh0en { + match self.bits { + false => RrCh0en::Disable, + true => RrCh0en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh0en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh0en::Enable + } +} +#[doc = "Field `RR_CH0EN` writer - Channel 0 Input Enable in Trigger Mode"] +pub type RrCh0enW<'a, REG> = crate::BitWriter<'a, REG, RrCh0en>; +impl<'a, REG> RrCh0enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh0en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh0en::Enable) + } +} +#[doc = "Channel 1 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh1en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh1en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH1EN` reader - Channel 1 Input Enable in Trigger Mode"] +pub type RrCh1enR = crate::BitReader; +impl RrCh1enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh1en { + match self.bits { + false => RrCh1en::Disable, + true => RrCh1en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh1en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh1en::Enable + } +} +#[doc = "Field `RR_CH1EN` writer - Channel 1 Input Enable in Trigger Mode"] +pub type RrCh1enW<'a, REG> = crate::BitWriter<'a, REG, RrCh1en>; +impl<'a, REG> RrCh1enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh1en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh1en::Enable) + } +} +#[doc = "Channel 2 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh2en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh2en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH2EN` reader - Channel 2 Input Enable in Trigger Mode"] +pub type RrCh2enR = crate::BitReader; +impl RrCh2enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh2en { + match self.bits { + false => RrCh2en::Disable, + true => RrCh2en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh2en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh2en::Enable + } +} +#[doc = "Field `RR_CH2EN` writer - Channel 2 Input Enable in Trigger Mode"] +pub type RrCh2enW<'a, REG> = crate::BitWriter<'a, REG, RrCh2en>; +impl<'a, REG> RrCh2enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh2en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh2en::Enable) + } +} +#[doc = "Channel 3 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh3en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh3en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH3EN` reader - Channel 3 Input Enable in Trigger Mode"] +pub type RrCh3enR = crate::BitReader; +impl RrCh3enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh3en { + match self.bits { + false => RrCh3en::Disable, + true => RrCh3en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh3en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh3en::Enable + } +} +#[doc = "Field `RR_CH3EN` writer - Channel 3 Input Enable in Trigger Mode"] +pub type RrCh3enW<'a, REG> = crate::BitWriter<'a, REG, RrCh3en>; +impl<'a, REG> RrCh3enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh3en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh3en::Enable) + } +} +#[doc = "Channel 4 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh4en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh4en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH4EN` reader - Channel 4 Input Enable in Trigger Mode"] +pub type RrCh4enR = crate::BitReader; +impl RrCh4enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh4en { + match self.bits { + false => RrCh4en::Disable, + true => RrCh4en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh4en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh4en::Enable + } +} +#[doc = "Field `RR_CH4EN` writer - Channel 4 Input Enable in Trigger Mode"] +pub type RrCh4enW<'a, REG> = crate::BitWriter<'a, REG, RrCh4en>; +impl<'a, REG> RrCh4enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh4en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh4en::Enable) + } +} +#[doc = "Channel 5 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh5en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh5en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH5EN` reader - Channel 5 Input Enable in Trigger Mode"] +pub type RrCh5enR = crate::BitReader; +impl RrCh5enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh5en { + match self.bits { + false => RrCh5en::Disable, + true => RrCh5en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh5en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh5en::Enable + } +} +#[doc = "Field `RR_CH5EN` writer - Channel 5 Input Enable in Trigger Mode"] +pub type RrCh5enW<'a, REG> = crate::BitWriter<'a, REG, RrCh5en>; +impl<'a, REG> RrCh5enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh5en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh5en::Enable) + } +} +#[doc = "Channel 6 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh6en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh6en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH6EN` reader - Channel 6 Input Enable in Trigger Mode"] +pub type RrCh6enR = crate::BitReader; +impl RrCh6enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh6en { + match self.bits { + false => RrCh6en::Disable, + true => RrCh6en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh6en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh6en::Enable + } +} +#[doc = "Field `RR_CH6EN` writer - Channel 6 Input Enable in Trigger Mode"] +pub type RrCh6enW<'a, REG> = crate::BitWriter<'a, REG, RrCh6en>; +impl<'a, REG> RrCh6enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh6en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh6en::Enable) + } +} +#[doc = "Channel 7 Input Enable in Trigger Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh7en { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh7en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH7EN` reader - Channel 7 Input Enable in Trigger Mode"] +pub type RrCh7enR = crate::BitReader; +impl RrCh7enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh7en { + match self.bits { + false => RrCh7en::Disable, + true => RrCh7en::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrCh7en::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrCh7en::Enable + } +} +#[doc = "Field `RR_CH7EN` writer - Channel 7 Input Enable in Trigger Mode"] +pub type RrCh7enW<'a, REG> = crate::BitWriter<'a, REG, RrCh7en>; +impl<'a, REG> RrCh7enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrCh7en::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrCh7en::Enable) + } +} +#[doc = "Fixed Port\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fixp { + #[doc = "0: Fix the plus port. Sweep only the inputs to the minus port."] + FixPlus = 0, + #[doc = "1: Fix the minus port. Sweep only the inputs to the plus port."] + FixMinus = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fixp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIXP` reader - Fixed Port"] +pub type FixpR = crate::BitReader; +impl FixpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fixp { + match self.bits { + false => Fixp::FixPlus, + true => Fixp::FixMinus, + } + } + #[doc = "Fix the plus port. Sweep only the inputs to the minus port."] + #[inline(always)] + pub fn is_fix_plus(&self) -> bool { + *self == Fixp::FixPlus + } + #[doc = "Fix the minus port. Sweep only the inputs to the plus port."] + #[inline(always)] + pub fn is_fix_minus(&self) -> bool { + *self == Fixp::FixMinus + } +} +#[doc = "Field `FIXP` writer - Fixed Port"] +pub type FixpW<'a, REG> = crate::BitWriter<'a, REG, Fixp>; +impl<'a, REG> FixpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fix the plus port. Sweep only the inputs to the minus port."] + #[inline(always)] + pub fn fix_plus(self) -> &'a mut crate::W { + self.variant(Fixp::FixPlus) + } + #[doc = "Fix the minus port. Sweep only the inputs to the plus port."] + #[inline(always)] + pub fn fix_minus(self) -> &'a mut crate::W { + self.variant(Fixp::FixMinus) + } +} +#[doc = "Fixed Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fixch { + #[doc = "0: Channel 0"] + FixCh0 = 0, + #[doc = "1: Channel 1"] + FixCh1 = 1, + #[doc = "2: Channel 2"] + FixCh2 = 2, + #[doc = "3: Channel 3"] + FixCh3 = 3, + #[doc = "4: Channel 4"] + FixCh4 = 4, + #[doc = "5: Channel 5"] + FixCh5 = 5, + #[doc = "6: Channel 6"] + FixCh6 = 6, + #[doc = "7: Channel 7"] + FixCh7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fixch) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fixch { + type Ux = u8; +} +impl crate::IsEnum for Fixch {} +#[doc = "Field `FIXCH` reader - Fixed Channel Select"] +pub type FixchR = crate::FieldReader; +impl FixchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fixch { + match self.bits { + 0 => Fixch::FixCh0, + 1 => Fixch::FixCh1, + 2 => Fixch::FixCh2, + 3 => Fixch::FixCh3, + 4 => Fixch::FixCh4, + 5 => Fixch::FixCh5, + 6 => Fixch::FixCh6, + 7 => Fixch::FixCh7, + _ => unreachable!(), + } + } + #[doc = "Channel 0"] + #[inline(always)] + pub fn is_fix_ch0(&self) -> bool { + *self == Fixch::FixCh0 + } + #[doc = "Channel 1"] + #[inline(always)] + pub fn is_fix_ch1(&self) -> bool { + *self == Fixch::FixCh1 + } + #[doc = "Channel 2"] + #[inline(always)] + pub fn is_fix_ch2(&self) -> bool { + *self == Fixch::FixCh2 + } + #[doc = "Channel 3"] + #[inline(always)] + pub fn is_fix_ch3(&self) -> bool { + *self == Fixch::FixCh3 + } + #[doc = "Channel 4"] + #[inline(always)] + pub fn is_fix_ch4(&self) -> bool { + *self == Fixch::FixCh4 + } + #[doc = "Channel 5"] + #[inline(always)] + pub fn is_fix_ch5(&self) -> bool { + *self == Fixch::FixCh5 + } + #[doc = "Channel 6"] + #[inline(always)] + pub fn is_fix_ch6(&self) -> bool { + *self == Fixch::FixCh6 + } + #[doc = "Channel 7"] + #[inline(always)] + pub fn is_fix_ch7(&self) -> bool { + *self == Fixch::FixCh7 + } +} +#[doc = "Field `FIXCH` writer - Fixed Channel Select"] +pub type FixchW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fixch, crate::Safe>; +impl<'a, REG> FixchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Channel 0"] + #[inline(always)] + pub fn fix_ch0(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh0) + } + #[doc = "Channel 1"] + #[inline(always)] + pub fn fix_ch1(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh1) + } + #[doc = "Channel 2"] + #[inline(always)] + pub fn fix_ch2(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh2) + } + #[doc = "Channel 3"] + #[inline(always)] + pub fn fix_ch3(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh3) + } + #[doc = "Channel 4"] + #[inline(always)] + pub fn fix_ch4(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh4) + } + #[doc = "Channel 5"] + #[inline(always)] + pub fn fix_ch5(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh5) + } + #[doc = "Channel 6"] + #[inline(always)] + pub fn fix_ch6(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh6) + } + #[doc = "Channel 7"] + #[inline(always)] + pub fn fix_ch7(self) -> &'a mut crate::W { + self.variant(Fixch::FixCh7) + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch0en(&self) -> RrCh0enR { + RrCh0enR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch1en(&self) -> RrCh1enR { + RrCh1enR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch2en(&self) -> RrCh2enR { + RrCh2enR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch3en(&self) -> RrCh3enR { + RrCh3enR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch4en(&self) -> RrCh4enR { + RrCh4enR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch5en(&self) -> RrCh5enR { + RrCh5enR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch6en(&self) -> RrCh6enR { + RrCh6enR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch7en(&self) -> RrCh7enR { + RrCh7enR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - Fixed Port"] + #[inline(always)] + pub fn fixp(&self) -> FixpR { + FixpR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 20:22 - Fixed Channel Select"] + #[inline(always)] + pub fn fixch(&self) -> FixchR { + FixchR::new(((self.bits >> 20) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch0en(&mut self) -> RrCh0enW { + RrCh0enW::new(self, 0) + } + #[doc = "Bit 1 - Channel 1 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch1en(&mut self) -> RrCh1enW { + RrCh1enW::new(self, 1) + } + #[doc = "Bit 2 - Channel 2 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch2en(&mut self) -> RrCh2enW { + RrCh2enW::new(self, 2) + } + #[doc = "Bit 3 - Channel 3 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch3en(&mut self) -> RrCh3enW { + RrCh3enW::new(self, 3) + } + #[doc = "Bit 4 - Channel 4 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch4en(&mut self) -> RrCh4enW { + RrCh4enW::new(self, 4) + } + #[doc = "Bit 5 - Channel 5 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch5en(&mut self) -> RrCh5enW { + RrCh5enW::new(self, 5) + } + #[doc = "Bit 6 - Channel 6 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch6en(&mut self) -> RrCh6enW { + RrCh6enW::new(self, 6) + } + #[doc = "Bit 7 - Channel 7 Input Enable in Trigger Mode"] + #[inline(always)] + pub fn rr_ch7en(&mut self) -> RrCh7enW { + RrCh7enW::new(self, 7) + } + #[doc = "Bit 16 - Fixed Port"] + #[inline(always)] + pub fn fixp(&mut self) -> FixpW { + FixpW::new(self, 16) + } + #[doc = "Bits 20:22 - Fixed Channel Select"] + #[inline(always)] + pub fn fixch(&mut self) -> FixchW { + FixchW::new(self, 20) + } +} +#[doc = "Round Robin Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rrcr1Spec; +impl crate::RegisterSpec for Rrcr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rrcr1::R`](R) reader structure"] +impl crate::Readable for Rrcr1Spec {} +#[doc = "`write(|w| ..)` method takes [`rrcr1::W`](W) writer structure"] +impl crate::Writable for Rrcr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RRCR1 to value 0"] +impl crate::Resettable for Rrcr1Spec {} diff --git a/mcxa276-pac/src/cmp0/rrcr2.rs b/mcxa276-pac/src/cmp0/rrcr2.rs new file mode 100644 index 000000000..3ad05ae0d --- /dev/null +++ b/mcxa276-pac/src/cmp0/rrcr2.rs @@ -0,0 +1,98 @@ +#[doc = "Register `RRCR2` reader"] +pub type R = crate::R; +#[doc = "Register `RRCR2` writer"] +pub type W = crate::W; +#[doc = "Field `RR_TIMER_RELOAD` reader - Number of Sample Clocks"] +pub type RrTimerReloadR = crate::FieldReader; +#[doc = "Field `RR_TIMER_RELOAD` writer - Number of Sample Clocks"] +pub type RrTimerReloadW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +#[doc = "Round-Robin Internal Timer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrTimerEn { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrTimerEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_TIMER_EN` reader - Round-Robin Internal Timer Enable"] +pub type RrTimerEnR = crate::BitReader; +impl RrTimerEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrTimerEn { + match self.bits { + false => RrTimerEn::Disable, + true => RrTimerEn::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RrTimerEn::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RrTimerEn::Enable + } +} +#[doc = "Field `RR_TIMER_EN` writer - Round-Robin Internal Timer Enable"] +pub type RrTimerEnW<'a, REG> = crate::BitWriter<'a, REG, RrTimerEn>; +impl<'a, REG> RrTimerEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RrTimerEn::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RrTimerEn::Enable) + } +} +impl R { + #[doc = "Bits 0:27 - Number of Sample Clocks"] + #[inline(always)] + pub fn rr_timer_reload(&self) -> RrTimerReloadR { + RrTimerReloadR::new(self.bits & 0x0fff_ffff) + } + #[doc = "Bit 31 - Round-Robin Internal Timer Enable"] + #[inline(always)] + pub fn rr_timer_en(&self) -> RrTimerEnR { + RrTimerEnR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:27 - Number of Sample Clocks"] + #[inline(always)] + pub fn rr_timer_reload(&mut self) -> RrTimerReloadW { + RrTimerReloadW::new(self, 0) + } + #[doc = "Bit 31 - Round-Robin Internal Timer Enable"] + #[inline(always)] + pub fn rr_timer_en(&mut self) -> RrTimerEnW { + RrTimerEnW::new(self, 31) + } +} +#[doc = "Round Robin Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rrcr2Spec; +impl crate::RegisterSpec for Rrcr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rrcr2::R`](R) reader structure"] +impl crate::Readable for Rrcr2Spec {} +#[doc = "`write(|w| ..)` method takes [`rrcr2::W`](W) writer structure"] +impl crate::Writable for Rrcr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RRCR2 to value 0"] +impl crate::Resettable for Rrcr2Spec {} diff --git a/mcxa276-pac/src/cmp0/rrcsr.rs b/mcxa276-pac/src/cmp0/rrcsr.rs new file mode 100644 index 000000000..4fcab1c43 --- /dev/null +++ b/mcxa276-pac/src/cmp0/rrcsr.rs @@ -0,0 +1,133 @@ +#[doc = "Register `RRCSR` reader"] +pub type R = crate::R; +#[doc = "Register `RRCSR` writer"] +pub type W = crate::W; +#[doc = "Field `RR_CH0OUT` reader - Comparison Result for Channel 0"] +pub type RrCh0outR = crate::BitReader; +#[doc = "Field `RR_CH0OUT` writer - Comparison Result for Channel 0"] +pub type RrCh0outW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RR_CH1OUT` reader - Comparison Result for Channel 1"] +pub type RrCh1outR = crate::BitReader; +#[doc = "Field `RR_CH1OUT` writer - Comparison Result for Channel 1"] +pub type RrCh1outW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RR_CH2OUT` reader - Comparison Result for Channel 2"] +pub type RrCh2outR = crate::BitReader; +#[doc = "Field `RR_CH2OUT` writer - Comparison Result for Channel 2"] +pub type RrCh2outW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RR_CH3OUT` reader - Comparison Result for Channel 3"] +pub type RrCh3outR = crate::BitReader; +#[doc = "Field `RR_CH3OUT` writer - Comparison Result for Channel 3"] +pub type RrCh3outW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RR_CH4OUT` reader - Comparison Result for Channel 4"] +pub type RrCh4outR = crate::BitReader; +#[doc = "Field `RR_CH4OUT` writer - Comparison Result for Channel 4"] +pub type RrCh4outW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RR_CH5OUT` reader - Comparison Result for Channel 5"] +pub type RrCh5outR = crate::BitReader; +#[doc = "Field `RR_CH5OUT` writer - Comparison Result for Channel 5"] +pub type RrCh5outW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RR_CH6OUT` reader - Comparison Result for Channel 6"] +pub type RrCh6outR = crate::BitReader; +#[doc = "Field `RR_CH6OUT` writer - Comparison Result for Channel 6"] +pub type RrCh6outW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RR_CH7OUT` reader - Comparison Result for Channel 7"] +pub type RrCh7outR = crate::BitReader; +#[doc = "Field `RR_CH7OUT` writer - Comparison Result for Channel 7"] +pub type RrCh7outW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Comparison Result for Channel 0"] + #[inline(always)] + pub fn rr_ch0out(&self) -> RrCh0outR { + RrCh0outR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparison Result for Channel 1"] + #[inline(always)] + pub fn rr_ch1out(&self) -> RrCh1outR { + RrCh1outR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Comparison Result for Channel 2"] + #[inline(always)] + pub fn rr_ch2out(&self) -> RrCh2outR { + RrCh2outR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Comparison Result for Channel 3"] + #[inline(always)] + pub fn rr_ch3out(&self) -> RrCh3outR { + RrCh3outR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Comparison Result for Channel 4"] + #[inline(always)] + pub fn rr_ch4out(&self) -> RrCh4outR { + RrCh4outR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Comparison Result for Channel 5"] + #[inline(always)] + pub fn rr_ch5out(&self) -> RrCh5outR { + RrCh5outR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Comparison Result for Channel 6"] + #[inline(always)] + pub fn rr_ch6out(&self) -> RrCh6outR { + RrCh6outR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Comparison Result for Channel 7"] + #[inline(always)] + pub fn rr_ch7out(&self) -> RrCh7outR { + RrCh7outR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparison Result for Channel 0"] + #[inline(always)] + pub fn rr_ch0out(&mut self) -> RrCh0outW { + RrCh0outW::new(self, 0) + } + #[doc = "Bit 1 - Comparison Result for Channel 1"] + #[inline(always)] + pub fn rr_ch1out(&mut self) -> RrCh1outW { + RrCh1outW::new(self, 1) + } + #[doc = "Bit 2 - Comparison Result for Channel 2"] + #[inline(always)] + pub fn rr_ch2out(&mut self) -> RrCh2outW { + RrCh2outW::new(self, 2) + } + #[doc = "Bit 3 - Comparison Result for Channel 3"] + #[inline(always)] + pub fn rr_ch3out(&mut self) -> RrCh3outW { + RrCh3outW::new(self, 3) + } + #[doc = "Bit 4 - Comparison Result for Channel 4"] + #[inline(always)] + pub fn rr_ch4out(&mut self) -> RrCh4outW { + RrCh4outW::new(self, 4) + } + #[doc = "Bit 5 - Comparison Result for Channel 5"] + #[inline(always)] + pub fn rr_ch5out(&mut self) -> RrCh5outW { + RrCh5outW::new(self, 5) + } + #[doc = "Bit 6 - Comparison Result for Channel 6"] + #[inline(always)] + pub fn rr_ch6out(&mut self) -> RrCh6outW { + RrCh6outW::new(self, 6) + } + #[doc = "Bit 7 - Comparison Result for Channel 7"] + #[inline(always)] + pub fn rr_ch7out(&mut self) -> RrCh7outW { + RrCh7outW::new(self, 7) + } +} +#[doc = "Round Robin Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RrcsrSpec; +impl crate::RegisterSpec for RrcsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rrcsr::R`](R) reader structure"] +impl crate::Readable for RrcsrSpec {} +#[doc = "`write(|w| ..)` method takes [`rrcsr::W`](W) writer structure"] +impl crate::Writable for RrcsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RRCSR to value 0"] +impl crate::Resettable for RrcsrSpec {} diff --git a/mcxa276-pac/src/cmp0/rrsr.rs b/mcxa276-pac/src/cmp0/rrsr.rs new file mode 100644 index 000000000..995a7a59f --- /dev/null +++ b/mcxa276-pac/src/cmp0/rrsr.rs @@ -0,0 +1,526 @@ +#[doc = "Register `RRSR` reader"] +pub type R = crate::R; +#[doc = "Register `RRSR` writer"] +pub type W = crate::W; +#[doc = "Channel 0 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh0f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh0f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH0F` reader - Channel 0 Input Changed Flag"] +pub type RrCh0fR = crate::BitReader; +impl RrCh0fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh0f { + match self.bits { + false => RrCh0f::NotDifferent, + true => RrCh0f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh0f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh0f::Different + } +} +#[doc = "Field `RR_CH0F` writer - Channel 0 Input Changed Flag"] +pub type RrCh0fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh0f>; +impl<'a, REG> RrCh0fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh0f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh0f::Different) + } +} +#[doc = "Channel 1 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh1f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh1f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH1F` reader - Channel 1 Input Changed Flag"] +pub type RrCh1fR = crate::BitReader; +impl RrCh1fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh1f { + match self.bits { + false => RrCh1f::NotDifferent, + true => RrCh1f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh1f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh1f::Different + } +} +#[doc = "Field `RR_CH1F` writer - Channel 1 Input Changed Flag"] +pub type RrCh1fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh1f>; +impl<'a, REG> RrCh1fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh1f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh1f::Different) + } +} +#[doc = "Channel 2 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh2f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh2f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH2F` reader - Channel 2 Input Changed Flag"] +pub type RrCh2fR = crate::BitReader; +impl RrCh2fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh2f { + match self.bits { + false => RrCh2f::NotDifferent, + true => RrCh2f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh2f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh2f::Different + } +} +#[doc = "Field `RR_CH2F` writer - Channel 2 Input Changed Flag"] +pub type RrCh2fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh2f>; +impl<'a, REG> RrCh2fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh2f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh2f::Different) + } +} +#[doc = "Channel 3 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh3f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh3f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH3F` reader - Channel 3 Input Changed Flag"] +pub type RrCh3fR = crate::BitReader; +impl RrCh3fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh3f { + match self.bits { + false => RrCh3f::NotDifferent, + true => RrCh3f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh3f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh3f::Different + } +} +#[doc = "Field `RR_CH3F` writer - Channel 3 Input Changed Flag"] +pub type RrCh3fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh3f>; +impl<'a, REG> RrCh3fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh3f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh3f::Different) + } +} +#[doc = "Channel 4 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh4f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh4f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH4F` reader - Channel 4 Input Changed Flag"] +pub type RrCh4fR = crate::BitReader; +impl RrCh4fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh4f { + match self.bits { + false => RrCh4f::NotDifferent, + true => RrCh4f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh4f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh4f::Different + } +} +#[doc = "Field `RR_CH4F` writer - Channel 4 Input Changed Flag"] +pub type RrCh4fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh4f>; +impl<'a, REG> RrCh4fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh4f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh4f::Different) + } +} +#[doc = "Channel 5 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh5f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh5f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH5F` reader - Channel 5 Input Changed Flag"] +pub type RrCh5fR = crate::BitReader; +impl RrCh5fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh5f { + match self.bits { + false => RrCh5f::NotDifferent, + true => RrCh5f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh5f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh5f::Different + } +} +#[doc = "Field `RR_CH5F` writer - Channel 5 Input Changed Flag"] +pub type RrCh5fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh5f>; +impl<'a, REG> RrCh5fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh5f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh5f::Different) + } +} +#[doc = "Channel 6 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh6f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh6f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH6F` reader - Channel 6 Input Changed Flag"] +pub type RrCh6fR = crate::BitReader; +impl RrCh6fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh6f { + match self.bits { + false => RrCh6f::NotDifferent, + true => RrCh6f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh6f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh6f::Different + } +} +#[doc = "Field `RR_CH6F` writer - Channel 6 Input Changed Flag"] +pub type RrCh6fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh6f>; +impl<'a, REG> RrCh6fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh6f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh6f::Different) + } +} +#[doc = "Channel 7 Input Changed Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RrCh7f { + #[doc = "0: No different"] + NotDifferent = 0, + #[doc = "1: Different"] + Different = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RrCh7f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RR_CH7F` reader - Channel 7 Input Changed Flag"] +pub type RrCh7fR = crate::BitReader; +impl RrCh7fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RrCh7f { + match self.bits { + false => RrCh7f::NotDifferent, + true => RrCh7f::Different, + } + } + #[doc = "No different"] + #[inline(always)] + pub fn is_not_different(&self) -> bool { + *self == RrCh7f::NotDifferent + } + #[doc = "Different"] + #[inline(always)] + pub fn is_different(&self) -> bool { + *self == RrCh7f::Different + } +} +#[doc = "Field `RR_CH7F` writer - Channel 7 Input Changed Flag"] +pub type RrCh7fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh7f>; +impl<'a, REG> RrCh7fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No different"] + #[inline(always)] + pub fn not_different(self) -> &'a mut crate::W { + self.variant(RrCh7f::NotDifferent) + } + #[doc = "Different"] + #[inline(always)] + pub fn different(self) -> &'a mut crate::W { + self.variant(RrCh7f::Different) + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch0f(&self) -> RrCh0fR { + RrCh0fR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch1f(&self) -> RrCh1fR { + RrCh1fR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch2f(&self) -> RrCh2fR { + RrCh2fR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch3f(&self) -> RrCh3fR { + RrCh3fR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch4f(&self) -> RrCh4fR { + RrCh4fR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch5f(&self) -> RrCh5fR { + RrCh5fR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch6f(&self) -> RrCh6fR { + RrCh6fR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch7f(&self) -> RrCh7fR { + RrCh7fR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch0f(&mut self) -> RrCh0fW { + RrCh0fW::new(self, 0) + } + #[doc = "Bit 1 - Channel 1 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch1f(&mut self) -> RrCh1fW { + RrCh1fW::new(self, 1) + } + #[doc = "Bit 2 - Channel 2 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch2f(&mut self) -> RrCh2fW { + RrCh2fW::new(self, 2) + } + #[doc = "Bit 3 - Channel 3 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch3f(&mut self) -> RrCh3fW { + RrCh3fW::new(self, 3) + } + #[doc = "Bit 4 - Channel 4 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch4f(&mut self) -> RrCh4fW { + RrCh4fW::new(self, 4) + } + #[doc = "Bit 5 - Channel 5 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch5f(&mut self) -> RrCh5fW { + RrCh5fW::new(self, 5) + } + #[doc = "Bit 6 - Channel 6 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch6f(&mut self) -> RrCh6fW { + RrCh6fW::new(self, 6) + } + #[doc = "Bit 7 - Channel 7 Input Changed Flag"] + #[inline(always)] + pub fn rr_ch7f(&mut self) -> RrCh7fW { + RrCh7fW::new(self, 7) + } +} +#[doc = "Round Robin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RrsrSpec; +impl crate::RegisterSpec for RrsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rrsr::R`](R) reader structure"] +impl crate::Readable for RrsrSpec {} +#[doc = "`write(|w| ..)` method takes [`rrsr::W`](W) writer structure"] +impl crate::Writable for RrsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; +} +#[doc = "`reset()` method sets RRSR to value 0"] +impl crate::Resettable for RrsrSpec {} diff --git a/mcxa276-pac/src/cmp0/verid.rs b/mcxa276-pac/src/cmp0/verid.rs new file mode 100644 index 000000000..ed1c0af21 --- /dev/null +++ b/mcxa276-pac/src/cmp0/verid.rs @@ -0,0 +1,68 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "1: Round robin feature"] + RoundRobin = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Feature::RoundRobin), + _ => None, + } + } + #[doc = "Round robin feature"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + *self == Feature::RoundRobin + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0100_0001"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0100_0001; +} diff --git a/mcxa276-pac/src/crc0.rs b/mcxa276-pac/src/crc0.rs new file mode 100644 index 000000000..87c4e88a2 --- /dev/null +++ b/mcxa276-pac/src/crc0.rs @@ -0,0 +1,39 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + data: Data, + gpoly: Gpoly, + ctrl: Ctrl, +} +impl RegisterBlock { + #[doc = "0x00 - Data"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x04 - Polynomial"] + #[inline(always)] + pub const fn gpoly(&self) -> &Gpoly { + &self.gpoly + } + #[doc = "0x08 - Control"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } +} +#[doc = "DATA (rw) register accessor: Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "GPOLY (rw) register accessor: Polynomial\n\nYou can [`read`](crate::Reg::read) this register and get [`gpoly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpoly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpoly`] module"] +#[doc(alias = "GPOLY")] +pub type Gpoly = crate::Reg; +#[doc = "Polynomial"] +pub mod gpoly; +#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control"] +pub mod ctrl; diff --git a/mcxa276-pac/src/crc0/ctrl.rs b/mcxa276-pac/src/crc0/ctrl.rs new file mode 100644 index 000000000..f83243b2f --- /dev/null +++ b/mcxa276-pac/src/crc0/ctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "TCRC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tcrc { + #[doc = "0: 16 bits"] + B16 = 0, + #[doc = "1: 32 bits"] + B32 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tcrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCRC` reader - TCRC"] +pub type TcrcR = crate::BitReader; +impl TcrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcrc { + match self.bits { + false => Tcrc::B16, + true => Tcrc::B32, + } + } + #[doc = "16 bits"] + #[inline(always)] + pub fn is_b16(&self) -> bool { + *self == Tcrc::B16 + } + #[doc = "32 bits"] + #[inline(always)] + pub fn is_b32(&self) -> bool { + *self == Tcrc::B32 + } +} +#[doc = "Field `TCRC` writer - TCRC"] +pub type TcrcW<'a, REG> = crate::BitWriter<'a, REG, Tcrc>; +impl<'a, REG> TcrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "16 bits"] + #[inline(always)] + pub fn b16(self) -> &'a mut crate::W { + self.variant(Tcrc::B16) + } + #[doc = "32 bits"] + #[inline(always)] + pub fn b32(self) -> &'a mut crate::W { + self.variant(Tcrc::B32) + } +} +#[doc = "Write as Seed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Was { + #[doc = "0: Data values"] + Data = 0, + #[doc = "1: Seed values"] + Seed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Was) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAS` reader - Write as Seed"] +pub type WasR = crate::BitReader; +impl WasR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Was { + match self.bits { + false => Was::Data, + true => Was::Seed, + } + } + #[doc = "Data values"] + #[inline(always)] + pub fn is_data(&self) -> bool { + *self == Was::Data + } + #[doc = "Seed values"] + #[inline(always)] + pub fn is_seed(&self) -> bool { + *self == Was::Seed + } +} +#[doc = "Field `WAS` writer - Write as Seed"] +pub type WasW<'a, REG> = crate::BitWriter<'a, REG, Was>; +impl<'a, REG> WasW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Data values"] + #[inline(always)] + pub fn data(self) -> &'a mut crate::W { + self.variant(Was::Data) + } + #[doc = "Seed values"] + #[inline(always)] + pub fn seed(self) -> &'a mut crate::W { + self.variant(Was::Seed) + } +} +#[doc = "Complement Read of CRC Data Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fxor { + #[doc = "0: Disables XOR on reading data."] + Noxor = 0, + #[doc = "1: Inverts or complements the read value of the CRC Data."] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fxor) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FXOR` reader - Complement Read of CRC Data Register"] +pub type FxorR = crate::BitReader; +impl FxorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fxor { + match self.bits { + false => Fxor::Noxor, + true => Fxor::Invert, + } + } + #[doc = "Disables XOR on reading data."] + #[inline(always)] + pub fn is_noxor(&self) -> bool { + *self == Fxor::Noxor + } + #[doc = "Inverts or complements the read value of the CRC Data."] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == Fxor::Invert + } +} +#[doc = "Field `FXOR` writer - Complement Read of CRC Data Register"] +pub type FxorW<'a, REG> = crate::BitWriter<'a, REG, Fxor>; +impl<'a, REG> FxorW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables XOR on reading data."] + #[inline(always)] + pub fn noxor(self) -> &'a mut crate::W { + self.variant(Fxor::Noxor) + } + #[doc = "Inverts or complements the read value of the CRC Data."] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(Fxor::Invert) + } +} +#[doc = "Transpose Type for Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Totr { + #[doc = "0: No transposition"] + Notrnps = 0, + #[doc = "1: Bits in bytes are transposed, but bytes are not transposed."] + BtsTrnps = 1, + #[doc = "2: Both bits in bytes and bytes are transposed."] + BytsBtsTrnps = 2, + #[doc = "3: Only bytes are transposed, no bits in a byte are transposed."] + BytsTrnps = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Totr) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Totr { + type Ux = u8; +} +impl crate::IsEnum for Totr {} +#[doc = "Field `TOTR` reader - Transpose Type for Read"] +pub type TotrR = crate::FieldReader; +impl TotrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Totr { + match self.bits { + 0 => Totr::Notrnps, + 1 => Totr::BtsTrnps, + 2 => Totr::BytsBtsTrnps, + 3 => Totr::BytsTrnps, + _ => unreachable!(), + } + } + #[doc = "No transposition"] + #[inline(always)] + pub fn is_notrnps(&self) -> bool { + *self == Totr::Notrnps + } + #[doc = "Bits in bytes are transposed, but bytes are not transposed."] + #[inline(always)] + pub fn is_bts_trnps(&self) -> bool { + *self == Totr::BtsTrnps + } + #[doc = "Both bits in bytes and bytes are transposed."] + #[inline(always)] + pub fn is_byts_bts_trnps(&self) -> bool { + *self == Totr::BytsBtsTrnps + } + #[doc = "Only bytes are transposed, no bits in a byte are transposed."] + #[inline(always)] + pub fn is_byts_trnps(&self) -> bool { + *self == Totr::BytsTrnps + } +} +#[doc = "Field `TOTR` writer - Transpose Type for Read"] +pub type TotrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Totr, crate::Safe>; +impl<'a, REG> TotrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No transposition"] + #[inline(always)] + pub fn notrnps(self) -> &'a mut crate::W { + self.variant(Totr::Notrnps) + } + #[doc = "Bits in bytes are transposed, but bytes are not transposed."] + #[inline(always)] + pub fn bts_trnps(self) -> &'a mut crate::W { + self.variant(Totr::BtsTrnps) + } + #[doc = "Both bits in bytes and bytes are transposed."] + #[inline(always)] + pub fn byts_bts_trnps(self) -> &'a mut crate::W { + self.variant(Totr::BytsBtsTrnps) + } + #[doc = "Only bytes are transposed, no bits in a byte are transposed."] + #[inline(always)] + pub fn byts_trnps(self) -> &'a mut crate::W { + self.variant(Totr::BytsTrnps) + } +} +#[doc = "Transpose Type for Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tot { + #[doc = "0: No transposition"] + Notrnps = 0, + #[doc = "1: Bits in bytes are transposed, but bytes are not transposed."] + BtsTrnps = 1, + #[doc = "2: Both bits in bytes and bytes are transposed."] + BytsBtsTrnps = 2, + #[doc = "3: Only bytes are transposed, no bits in a byte are transposed."] + BytsTrnps = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tot) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tot { + type Ux = u8; +} +impl crate::IsEnum for Tot {} +#[doc = "Field `TOT` reader - Transpose Type for Write"] +pub type TotR = crate::FieldReader; +impl TotR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tot { + match self.bits { + 0 => Tot::Notrnps, + 1 => Tot::BtsTrnps, + 2 => Tot::BytsBtsTrnps, + 3 => Tot::BytsTrnps, + _ => unreachable!(), + } + } + #[doc = "No transposition"] + #[inline(always)] + pub fn is_notrnps(&self) -> bool { + *self == Tot::Notrnps + } + #[doc = "Bits in bytes are transposed, but bytes are not transposed."] + #[inline(always)] + pub fn is_bts_trnps(&self) -> bool { + *self == Tot::BtsTrnps + } + #[doc = "Both bits in bytes and bytes are transposed."] + #[inline(always)] + pub fn is_byts_bts_trnps(&self) -> bool { + *self == Tot::BytsBtsTrnps + } + #[doc = "Only bytes are transposed, no bits in a byte are transposed."] + #[inline(always)] + pub fn is_byts_trnps(&self) -> bool { + *self == Tot::BytsTrnps + } +} +#[doc = "Field `TOT` writer - Transpose Type for Write"] +pub type TotW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tot, crate::Safe>; +impl<'a, REG> TotW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No transposition"] + #[inline(always)] + pub fn notrnps(self) -> &'a mut crate::W { + self.variant(Tot::Notrnps) + } + #[doc = "Bits in bytes are transposed, but bytes are not transposed."] + #[inline(always)] + pub fn bts_trnps(self) -> &'a mut crate::W { + self.variant(Tot::BtsTrnps) + } + #[doc = "Both bits in bytes and bytes are transposed."] + #[inline(always)] + pub fn byts_bts_trnps(self) -> &'a mut crate::W { + self.variant(Tot::BytsBtsTrnps) + } + #[doc = "Only bytes are transposed, no bits in a byte are transposed."] + #[inline(always)] + pub fn byts_trnps(self) -> &'a mut crate::W { + self.variant(Tot::BytsTrnps) + } +} +impl R { + #[doc = "Bit 24 - TCRC"] + #[inline(always)] + pub fn tcrc(&self) -> TcrcR { + TcrcR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write as Seed"] + #[inline(always)] + pub fn was(&self) -> WasR { + WasR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Complement Read of CRC Data Register"] + #[inline(always)] + pub fn fxor(&self) -> FxorR { + FxorR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bits 28:29 - Transpose Type for Read"] + #[inline(always)] + pub fn totr(&self) -> TotrR { + TotrR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Transpose Type for Write"] + #[inline(always)] + pub fn tot(&self) -> TotR { + TotR::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bit 24 - TCRC"] + #[inline(always)] + pub fn tcrc(&mut self) -> TcrcW { + TcrcW::new(self, 24) + } + #[doc = "Bit 25 - Write as Seed"] + #[inline(always)] + pub fn was(&mut self) -> WasW { + WasW::new(self, 25) + } + #[doc = "Bit 26 - Complement Read of CRC Data Register"] + #[inline(always)] + pub fn fxor(&mut self) -> FxorW { + FxorW::new(self, 26) + } + #[doc = "Bits 28:29 - Transpose Type for Read"] + #[inline(always)] + pub fn totr(&mut self) -> TotrW { + TotrW::new(self, 28) + } + #[doc = "Bits 30:31 - Transpose Type for Write"] + #[inline(always)] + pub fn tot(&mut self) -> TotW { + TotW::new(self, 30) + } +} +#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/crc0/data.rs b/mcxa276-pac/src/crc0/data.rs new file mode 100644 index 000000000..4240630f1 --- /dev/null +++ b/mcxa276-pac/src/crc0/data.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[doc = "Field `LL` reader - Lower Part of Low Byte"] +pub type LlR = crate::FieldReader; +#[doc = "Field `LL` writer - Lower Part of Low Byte"] +pub type LlW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LU` reader - Upper Part of Low Byte"] +pub type LuR = crate::FieldReader; +#[doc = "Field `LU` writer - Upper Part of Low Byte"] +pub type LuW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HL` reader - Lower Part of High Byte"] +pub type HlR = crate::FieldReader; +#[doc = "Field `HL` writer - Lower Part of High Byte"] +pub type HlW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HU` reader - Upper Part of High Byte"] +pub type HuR = crate::FieldReader; +#[doc = "Field `HU` writer - Upper Part of High Byte"] +pub type HuW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Lower Part of Low Byte"] + #[inline(always)] + pub fn ll(&self) -> LlR { + LlR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Upper Part of Low Byte"] + #[inline(always)] + pub fn lu(&self) -> LuR { + LuR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Lower Part of High Byte"] + #[inline(always)] + pub fn hl(&self) -> HlR { + HlR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Upper Part of High Byte"] + #[inline(always)] + pub fn hu(&self) -> HuR { + HuR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Lower Part of Low Byte"] + #[inline(always)] + pub fn ll(&mut self) -> LlW { + LlW::new(self, 0) + } + #[doc = "Bits 8:15 - Upper Part of Low Byte"] + #[inline(always)] + pub fn lu(&mut self) -> LuW { + LuW::new(self, 8) + } + #[doc = "Bits 16:23 - Lower Part of High Byte"] + #[inline(always)] + pub fn hl(&mut self) -> HlW { + HlW::new(self, 16) + } + #[doc = "Bits 24:31 - Upper Part of High Byte"] + #[inline(always)] + pub fn hu(&mut self) -> HuW { + HuW::new(self, 24) + } +} +#[doc = "Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0xffff_ffff"] +impl crate::Resettable for DataSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/mcxa276-pac/src/crc0/gpoly.rs b/mcxa276-pac/src/crc0/gpoly.rs new file mode 100644 index 000000000..8ae5e16f0 --- /dev/null +++ b/mcxa276-pac/src/crc0/gpoly.rs @@ -0,0 +1,51 @@ +#[doc = "Register `GPOLY` reader"] +pub type R = crate::R; +#[doc = "Register `GPOLY` writer"] +pub type W = crate::W; +#[doc = "Field `LOW` reader - Low Half-Word"] +pub type LowR = crate::FieldReader; +#[doc = "Field `LOW` writer - Low Half-Word"] +pub type LowW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `HIGH` reader - High Half-Word"] +pub type HighR = crate::FieldReader; +#[doc = "Field `HIGH` writer - High Half-Word"] +pub type HighW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Low Half-Word"] + #[inline(always)] + pub fn low(&self) -> LowR { + LowR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - High Half-Word"] + #[inline(always)] + pub fn high(&self) -> HighR { + HighR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Low Half-Word"] + #[inline(always)] + pub fn low(&mut self) -> LowW { + LowW::new(self, 0) + } + #[doc = "Bits 16:31 - High Half-Word"] + #[inline(always)] + pub fn high(&mut self) -> HighW { + HighW::new(self, 16) + } +} +#[doc = "Polynomial\n\nYou can [`read`](crate::Reg::read) this register and get [`gpoly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpoly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpolySpec; +impl crate::RegisterSpec for GpolySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpoly::R`](R) reader structure"] +impl crate::Readable for GpolySpec {} +#[doc = "`write(|w| ..)` method takes [`gpoly::W`](W) writer structure"] +impl crate::Writable for GpolySpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPOLY to value 0x1021"] +impl crate::Resettable for GpolySpec { + const RESET_VALUE: u32 = 0x1021; +} diff --git a/mcxa276-pac/src/ctimer0.rs b/mcxa276-pac/src/ctimer0.rs new file mode 100644 index 000000000..07cf09412 --- /dev/null +++ b/mcxa276-pac/src/ctimer0.rs @@ -0,0 +1,168 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ir: Ir, + tcr: Tcr, + tc: Tc, + pr: Pr, + pc: Pc, + mcr: Mcr, + mr: [Mr; 4], + ccr: Ccr, + cr: [Cr; 4], + emr: Emr, + _reserved10: [u8; 0x30], + ctcr: Ctcr, + pwmc: Pwmc, + msr: [Msr; 4], +} +impl RegisterBlock { + #[doc = "0x00 - Interrupt"] + #[inline(always)] + pub const fn ir(&self) -> &Ir { + &self.ir + } + #[doc = "0x04 - Timer Control"] + #[inline(always)] + pub const fn tcr(&self) -> &Tcr { + &self.tcr + } + #[doc = "0x08 - Timer Counter"] + #[inline(always)] + pub const fn tc(&self) -> &Tc { + &self.tc + } + #[doc = "0x0c - Prescale"] + #[inline(always)] + pub const fn pr(&self) -> &Pr { + &self.pr + } + #[doc = "0x10 - Prescale Counter"] + #[inline(always)] + pub const fn pc(&self) -> &Pc { + &self.pc + } + #[doc = "0x14 - Match Control"] + #[inline(always)] + pub const fn mcr(&self) -> &Mcr { + &self.mcr + } + #[doc = "0x18..0x28 - Match"] + #[inline(always)] + pub const fn mr(&self, n: usize) -> &Mr { + &self.mr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x18..0x28 - Match"] + #[inline(always)] + pub fn mr_iter(&self) -> impl Iterator { + self.mr.iter() + } + #[doc = "0x28 - Capture Control"] + #[inline(always)] + pub const fn ccr(&self) -> &Ccr { + &self.ccr + } + #[doc = "0x2c..0x3c - Capture"] + #[inline(always)] + pub const fn cr(&self, n: usize) -> &Cr { + &self.cr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c..0x3c - Capture"] + #[inline(always)] + pub fn cr_iter(&self) -> impl Iterator { + self.cr.iter() + } + #[doc = "0x3c - External Match"] + #[inline(always)] + pub const fn emr(&self) -> &Emr { + &self.emr + } + #[doc = "0x70 - Count Control"] + #[inline(always)] + pub const fn ctcr(&self) -> &Ctcr { + &self.ctcr + } + #[doc = "0x74 - PWM Control"] + #[inline(always)] + pub const fn pwmc(&self) -> &Pwmc { + &self.pwmc + } + #[doc = "0x78..0x88 - Match Shadow"] + #[inline(always)] + pub const fn msr(&self, n: usize) -> &Msr { + &self.msr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x78..0x88 - Match Shadow"] + #[inline(always)] + pub fn msr_iter(&self) -> impl Iterator { + self.msr.iter() + } +} +#[doc = "IR (rw) register accessor: Interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`] module"] +#[doc(alias = "IR")] +pub type Ir = crate::Reg; +#[doc = "Interrupt"] +pub mod ir; +#[doc = "TCR (rw) register accessor: Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] +#[doc(alias = "TCR")] +pub type Tcr = crate::Reg; +#[doc = "Timer Control"] +pub mod tcr; +#[doc = "TC (rw) register accessor: Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] module"] +#[doc(alias = "TC")] +pub type Tc = crate::Reg; +#[doc = "Timer Counter"] +pub mod tc; +#[doc = "PR (rw) register accessor: Prescale\n\nYou can [`read`](crate::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`] module"] +#[doc(alias = "PR")] +pub type Pr = crate::Reg; +#[doc = "Prescale"] +pub mod pr; +#[doc = "PC (rw) register accessor: Prescale Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`] module"] +#[doc(alias = "PC")] +pub type Pc = crate::Reg; +#[doc = "Prescale Counter"] +pub mod pc; +#[doc = "MCR (rw) register accessor: Match Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] +#[doc(alias = "MCR")] +pub type Mcr = crate::Reg; +#[doc = "Match Control"] +pub mod mcr; +#[doc = "MR (rw) register accessor: Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`] module"] +#[doc(alias = "MR")] +pub type Mr = crate::Reg; +#[doc = "Match"] +pub mod mr; +#[doc = "CCR (rw) register accessor: Capture Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`] module"] +#[doc(alias = "CCR")] +pub type Ccr = crate::Reg; +#[doc = "Capture Control"] +pub mod ccr; +#[doc = "CR (r) register accessor: Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] +#[doc(alias = "CR")] +pub type Cr = crate::Reg; +#[doc = "Capture"] +pub mod cr; +#[doc = "EMR (rw) register accessor: External Match\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`] module"] +#[doc(alias = "EMR")] +pub type Emr = crate::Reg; +#[doc = "External Match"] +pub mod emr; +#[doc = "CTCR (rw) register accessor: Count Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`] module"] +#[doc(alias = "CTCR")] +pub type Ctcr = crate::Reg; +#[doc = "Count Control"] +pub mod ctcr; +#[doc = "PWMC (rw) register accessor: PWM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`] module"] +#[doc(alias = "PWMC")] +pub type Pwmc = crate::Reg; +#[doc = "PWM Control"] +pub mod pwmc; +#[doc = "MSR (rw) register accessor: Match Shadow\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] +#[doc(alias = "MSR")] +pub type Msr = crate::Reg; +#[doc = "Match Shadow"] +pub mod msr; diff --git a/mcxa276-pac/src/ctimer0/ccr.rs b/mcxa276-pac/src/ctimer0/ccr.rs new file mode 100644 index 000000000..cddce8dee --- /dev/null +++ b/mcxa276-pac/src/ctimer0/ccr.rs @@ -0,0 +1,777 @@ +#[doc = "Register `CCR` reader"] +pub type R = crate::R; +#[doc = "Register `CCR` writer"] +pub type W = crate::W; +#[doc = "Rising Edge of Capture Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0re { + #[doc = "0: Does not load"] + Cap0re0 = 0, + #[doc = "1: Loads"] + Capore1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0RE` reader - Rising Edge of Capture Channel 0"] +pub type Cap0reR = crate::BitReader; +impl Cap0reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0re { + match self.bits { + false => Cap0re::Cap0re0, + true => Cap0re::Capore1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap0re_0(&self) -> bool { + *self == Cap0re::Cap0re0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_capore_1(&self) -> bool { + *self == Cap0re::Capore1 + } +} +#[doc = "Field `CAP0RE` writer - Rising Edge of Capture Channel 0"] +pub type Cap0reW<'a, REG> = crate::BitWriter<'a, REG, Cap0re>; +impl<'a, REG> Cap0reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap0re_0(self) -> &'a mut crate::W { + self.variant(Cap0re::Cap0re0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn capore_1(self) -> &'a mut crate::W { + self.variant(Cap0re::Capore1) + } +} +#[doc = "Falling Edge of Capture Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0fe { + #[doc = "0: Does not load"] + Cap0fe0 = 0, + #[doc = "1: Loads"] + Capofe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0FE` reader - Falling Edge of Capture Channel 0"] +pub type Cap0feR = crate::BitReader; +impl Cap0feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0fe { + match self.bits { + false => Cap0fe::Cap0fe0, + true => Cap0fe::Capofe1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap0fe_0(&self) -> bool { + *self == Cap0fe::Cap0fe0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_capofe_1(&self) -> bool { + *self == Cap0fe::Capofe1 + } +} +#[doc = "Field `CAP0FE` writer - Falling Edge of Capture Channel 0"] +pub type Cap0feW<'a, REG> = crate::BitWriter<'a, REG, Cap0fe>; +impl<'a, REG> Cap0feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap0fe_0(self) -> &'a mut crate::W { + self.variant(Cap0fe::Cap0fe0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn capofe_1(self) -> &'a mut crate::W { + self.variant(Cap0fe::Capofe1) + } +} +#[doc = "Generate Interrupt on Channel 0 Capture Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0i { + #[doc = "0: Does not generate"] + Cap0i0 = 0, + #[doc = "1: Generates"] + Capoi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0I` reader - Generate Interrupt on Channel 0 Capture Event"] +pub type Cap0iR = crate::BitReader; +impl Cap0iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0i { + match self.bits { + false => Cap0i::Cap0i0, + true => Cap0i::Capoi1, + } + } + #[doc = "Does not generate"] + #[inline(always)] + pub fn is_cap0i_0(&self) -> bool { + *self == Cap0i::Cap0i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_capoi_1(&self) -> bool { + *self == Cap0i::Capoi1 + } +} +#[doc = "Field `CAP0I` writer - Generate Interrupt on Channel 0 Capture Event"] +pub type Cap0iW<'a, REG> = crate::BitWriter<'a, REG, Cap0i>; +impl<'a, REG> Cap0iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generate"] + #[inline(always)] + pub fn cap0i_0(self) -> &'a mut crate::W { + self.variant(Cap0i::Cap0i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn capoi_1(self) -> &'a mut crate::W { + self.variant(Cap0i::Capoi1) + } +} +#[doc = "Rising Edge of Capture Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1re { + #[doc = "0: Does not load"] + Cap1re0 = 0, + #[doc = "1: Loads"] + Cap1re1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1RE` reader - Rising Edge of Capture Channel 1"] +pub type Cap1reR = crate::BitReader; +impl Cap1reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1re { + match self.bits { + false => Cap1re::Cap1re0, + true => Cap1re::Cap1re1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap1re_0(&self) -> bool { + *self == Cap1re::Cap1re0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_cap1re_1(&self) -> bool { + *self == Cap1re::Cap1re1 + } +} +#[doc = "Field `CAP1RE` writer - Rising Edge of Capture Channel 1"] +pub type Cap1reW<'a, REG> = crate::BitWriter<'a, REG, Cap1re>; +impl<'a, REG> Cap1reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap1re_0(self) -> &'a mut crate::W { + self.variant(Cap1re::Cap1re0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn cap1re_1(self) -> &'a mut crate::W { + self.variant(Cap1re::Cap1re1) + } +} +#[doc = "Falling Edge of Capture Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1fe { + #[doc = "0: Does not load"] + Cap1fe0 = 0, + #[doc = "1: Loads"] + Cap1fe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1FE` reader - Falling Edge of Capture Channel 1"] +pub type Cap1feR = crate::BitReader; +impl Cap1feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1fe { + match self.bits { + false => Cap1fe::Cap1fe0, + true => Cap1fe::Cap1fe1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap1fe_0(&self) -> bool { + *self == Cap1fe::Cap1fe0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_cap1fe_1(&self) -> bool { + *self == Cap1fe::Cap1fe1 + } +} +#[doc = "Field `CAP1FE` writer - Falling Edge of Capture Channel 1"] +pub type Cap1feW<'a, REG> = crate::BitWriter<'a, REG, Cap1fe>; +impl<'a, REG> Cap1feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap1fe_0(self) -> &'a mut crate::W { + self.variant(Cap1fe::Cap1fe0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn cap1fe_1(self) -> &'a mut crate::W { + self.variant(Cap1fe::Cap1fe1) + } +} +#[doc = "Generate Interrupt on Channel 1 Capture Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1i { + #[doc = "0: Does not generates"] + Cap1i0 = 0, + #[doc = "1: Generates"] + Cap1i1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1I` reader - Generate Interrupt on Channel 1 Capture Event"] +pub type Cap1iR = crate::BitReader; +impl Cap1iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1i { + match self.bits { + false => Cap1i::Cap1i0, + true => Cap1i::Cap1i1, + } + } + #[doc = "Does not generates"] + #[inline(always)] + pub fn is_cap1i_0(&self) -> bool { + *self == Cap1i::Cap1i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_cap1i_1(&self) -> bool { + *self == Cap1i::Cap1i1 + } +} +#[doc = "Field `CAP1I` writer - Generate Interrupt on Channel 1 Capture Event"] +pub type Cap1iW<'a, REG> = crate::BitWriter<'a, REG, Cap1i>; +impl<'a, REG> Cap1iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generates"] + #[inline(always)] + pub fn cap1i_0(self) -> &'a mut crate::W { + self.variant(Cap1i::Cap1i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn cap1i_1(self) -> &'a mut crate::W { + self.variant(Cap1i::Cap1i1) + } +} +#[doc = "Rising Edge of Capture Channel 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap2re { + #[doc = "0: Does not load"] + Cap2re0 = 0, + #[doc = "1: Loads"] + Cap2re1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap2re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP2RE` reader - Rising Edge of Capture Channel 2"] +pub type Cap2reR = crate::BitReader; +impl Cap2reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap2re { + match self.bits { + false => Cap2re::Cap2re0, + true => Cap2re::Cap2re1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap2re_0(&self) -> bool { + *self == Cap2re::Cap2re0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_cap2re_1(&self) -> bool { + *self == Cap2re::Cap2re1 + } +} +#[doc = "Field `CAP2RE` writer - Rising Edge of Capture Channel 2"] +pub type Cap2reW<'a, REG> = crate::BitWriter<'a, REG, Cap2re>; +impl<'a, REG> Cap2reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap2re_0(self) -> &'a mut crate::W { + self.variant(Cap2re::Cap2re0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn cap2re_1(self) -> &'a mut crate::W { + self.variant(Cap2re::Cap2re1) + } +} +#[doc = "Falling Edge of Capture Channel 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap2fe { + #[doc = "0: Does not load"] + Cap2fe0 = 0, + #[doc = "1: Loads"] + Cap2fe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap2fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP2FE` reader - Falling Edge of Capture Channel 2"] +pub type Cap2feR = crate::BitReader; +impl Cap2feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap2fe { + match self.bits { + false => Cap2fe::Cap2fe0, + true => Cap2fe::Cap2fe1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap2fe_0(&self) -> bool { + *self == Cap2fe::Cap2fe0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_cap2fe_1(&self) -> bool { + *self == Cap2fe::Cap2fe1 + } +} +#[doc = "Field `CAP2FE` writer - Falling Edge of Capture Channel 2"] +pub type Cap2feW<'a, REG> = crate::BitWriter<'a, REG, Cap2fe>; +impl<'a, REG> Cap2feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap2fe_0(self) -> &'a mut crate::W { + self.variant(Cap2fe::Cap2fe0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn cap2fe_1(self) -> &'a mut crate::W { + self.variant(Cap2fe::Cap2fe1) + } +} +#[doc = "Generate Interrupt on Channel 2 Capture Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap2i { + #[doc = "0: Does not generate"] + Cap2i0 = 0, + #[doc = "1: Generates"] + Cap2i1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap2i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP2I` reader - Generate Interrupt on Channel 2 Capture Event"] +pub type Cap2iR = crate::BitReader; +impl Cap2iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap2i { + match self.bits { + false => Cap2i::Cap2i0, + true => Cap2i::Cap2i1, + } + } + #[doc = "Does not generate"] + #[inline(always)] + pub fn is_cap2i_0(&self) -> bool { + *self == Cap2i::Cap2i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_cap2i_1(&self) -> bool { + *self == Cap2i::Cap2i1 + } +} +#[doc = "Field `CAP2I` writer - Generate Interrupt on Channel 2 Capture Event"] +pub type Cap2iW<'a, REG> = crate::BitWriter<'a, REG, Cap2i>; +impl<'a, REG> Cap2iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generate"] + #[inline(always)] + pub fn cap2i_0(self) -> &'a mut crate::W { + self.variant(Cap2i::Cap2i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn cap2i_1(self) -> &'a mut crate::W { + self.variant(Cap2i::Cap2i1) + } +} +#[doc = "Rising Edge of Capture Channel 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap3re { + #[doc = "0: Does not load"] + Cap3re0 = 0, + #[doc = "1: Loads"] + Cap3re1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap3re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP3RE` reader - Rising Edge of Capture Channel 3"] +pub type Cap3reR = crate::BitReader; +impl Cap3reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap3re { + match self.bits { + false => Cap3re::Cap3re0, + true => Cap3re::Cap3re1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap3re_0(&self) -> bool { + *self == Cap3re::Cap3re0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_cap3re_1(&self) -> bool { + *self == Cap3re::Cap3re1 + } +} +#[doc = "Field `CAP3RE` writer - Rising Edge of Capture Channel 3"] +pub type Cap3reW<'a, REG> = crate::BitWriter<'a, REG, Cap3re>; +impl<'a, REG> Cap3reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap3re_0(self) -> &'a mut crate::W { + self.variant(Cap3re::Cap3re0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn cap3re_1(self) -> &'a mut crate::W { + self.variant(Cap3re::Cap3re1) + } +} +#[doc = "Falling Edge of Capture Channel 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap3fe { + #[doc = "0: Does not load"] + Cap3fe0 = 0, + #[doc = "1: Loads"] + Cap3fe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap3fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP3FE` reader - Falling Edge of Capture Channel 3"] +pub type Cap3feR = crate::BitReader; +impl Cap3feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap3fe { + match self.bits { + false => Cap3fe::Cap3fe0, + true => Cap3fe::Cap3fe1, + } + } + #[doc = "Does not load"] + #[inline(always)] + pub fn is_cap3fe_0(&self) -> bool { + *self == Cap3fe::Cap3fe0 + } + #[doc = "Loads"] + #[inline(always)] + pub fn is_cap3fe_1(&self) -> bool { + *self == Cap3fe::Cap3fe1 + } +} +#[doc = "Field `CAP3FE` writer - Falling Edge of Capture Channel 3"] +pub type Cap3feW<'a, REG> = crate::BitWriter<'a, REG, Cap3fe>; +impl<'a, REG> Cap3feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not load"] + #[inline(always)] + pub fn cap3fe_0(self) -> &'a mut crate::W { + self.variant(Cap3fe::Cap3fe0) + } + #[doc = "Loads"] + #[inline(always)] + pub fn cap3fe_1(self) -> &'a mut crate::W { + self.variant(Cap3fe::Cap3fe1) + } +} +#[doc = "Generate Interrupt on Channel 3 Capture Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap3i { + #[doc = "0: Does not generate"] + Cap3i0 = 0, + #[doc = "1: Generates"] + Cap3i1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap3i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP3I` reader - Generate Interrupt on Channel 3 Capture Event"] +pub type Cap3iR = crate::BitReader; +impl Cap3iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap3i { + match self.bits { + false => Cap3i::Cap3i0, + true => Cap3i::Cap3i1, + } + } + #[doc = "Does not generate"] + #[inline(always)] + pub fn is_cap3i_0(&self) -> bool { + *self == Cap3i::Cap3i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_cap3i_1(&self) -> bool { + *self == Cap3i::Cap3i1 + } +} +#[doc = "Field `CAP3I` writer - Generate Interrupt on Channel 3 Capture Event"] +pub type Cap3iW<'a, REG> = crate::BitWriter<'a, REG, Cap3i>; +impl<'a, REG> Cap3iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generate"] + #[inline(always)] + pub fn cap3i_0(self) -> &'a mut crate::W { + self.variant(Cap3i::Cap3i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn cap3i_1(self) -> &'a mut crate::W { + self.variant(Cap3i::Cap3i1) + } +} +impl R { + #[doc = "Bit 0 - Rising Edge of Capture Channel 0"] + #[inline(always)] + pub fn cap0re(&self) -> Cap0reR { + Cap0reR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Falling Edge of Capture Channel 0"] + #[inline(always)] + pub fn cap0fe(&self) -> Cap0feR { + Cap0feR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Generate Interrupt on Channel 0 Capture Event"] + #[inline(always)] + pub fn cap0i(&self) -> Cap0iR { + Cap0iR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Rising Edge of Capture Channel 1"] + #[inline(always)] + pub fn cap1re(&self) -> Cap1reR { + Cap1reR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Falling Edge of Capture Channel 1"] + #[inline(always)] + pub fn cap1fe(&self) -> Cap1feR { + Cap1feR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Generate Interrupt on Channel 1 Capture Event"] + #[inline(always)] + pub fn cap1i(&self) -> Cap1iR { + Cap1iR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Rising Edge of Capture Channel 2"] + #[inline(always)] + pub fn cap2re(&self) -> Cap2reR { + Cap2reR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Falling Edge of Capture Channel 2"] + #[inline(always)] + pub fn cap2fe(&self) -> Cap2feR { + Cap2feR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Generate Interrupt on Channel 2 Capture Event"] + #[inline(always)] + pub fn cap2i(&self) -> Cap2iR { + Cap2iR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Rising Edge of Capture Channel 3"] + #[inline(always)] + pub fn cap3re(&self) -> Cap3reR { + Cap3reR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Falling Edge of Capture Channel 3"] + #[inline(always)] + pub fn cap3fe(&self) -> Cap3feR { + Cap3feR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Generate Interrupt on Channel 3 Capture Event"] + #[inline(always)] + pub fn cap3i(&self) -> Cap3iR { + Cap3iR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rising Edge of Capture Channel 0"] + #[inline(always)] + pub fn cap0re(&mut self) -> Cap0reW { + Cap0reW::new(self, 0) + } + #[doc = "Bit 1 - Falling Edge of Capture Channel 0"] + #[inline(always)] + pub fn cap0fe(&mut self) -> Cap0feW { + Cap0feW::new(self, 1) + } + #[doc = "Bit 2 - Generate Interrupt on Channel 0 Capture Event"] + #[inline(always)] + pub fn cap0i(&mut self) -> Cap0iW { + Cap0iW::new(self, 2) + } + #[doc = "Bit 3 - Rising Edge of Capture Channel 1"] + #[inline(always)] + pub fn cap1re(&mut self) -> Cap1reW { + Cap1reW::new(self, 3) + } + #[doc = "Bit 4 - Falling Edge of Capture Channel 1"] + #[inline(always)] + pub fn cap1fe(&mut self) -> Cap1feW { + Cap1feW::new(self, 4) + } + #[doc = "Bit 5 - Generate Interrupt on Channel 1 Capture Event"] + #[inline(always)] + pub fn cap1i(&mut self) -> Cap1iW { + Cap1iW::new(self, 5) + } + #[doc = "Bit 6 - Rising Edge of Capture Channel 2"] + #[inline(always)] + pub fn cap2re(&mut self) -> Cap2reW { + Cap2reW::new(self, 6) + } + #[doc = "Bit 7 - Falling Edge of Capture Channel 2"] + #[inline(always)] + pub fn cap2fe(&mut self) -> Cap2feW { + Cap2feW::new(self, 7) + } + #[doc = "Bit 8 - Generate Interrupt on Channel 2 Capture Event"] + #[inline(always)] + pub fn cap2i(&mut self) -> Cap2iW { + Cap2iW::new(self, 8) + } + #[doc = "Bit 9 - Rising Edge of Capture Channel 3"] + #[inline(always)] + pub fn cap3re(&mut self) -> Cap3reW { + Cap3reW::new(self, 9) + } + #[doc = "Bit 10 - Falling Edge of Capture Channel 3"] + #[inline(always)] + pub fn cap3fe(&mut self) -> Cap3feW { + Cap3feW::new(self, 10) + } + #[doc = "Bit 11 - Generate Interrupt on Channel 3 Capture Event"] + #[inline(always)] + pub fn cap3i(&mut self) -> Cap3iW { + Cap3iW::new(self, 11) + } +} +#[doc = "Capture Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CcrSpec; +impl crate::RegisterSpec for CcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] +impl crate::Readable for CcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] +impl crate::Writable for CcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CCR to value 0"] +impl crate::Resettable for CcrSpec {} diff --git a/mcxa276-pac/src/ctimer0/cr.rs b/mcxa276-pac/src/ctimer0/cr.rs new file mode 100644 index 000000000..c0123971d --- /dev/null +++ b/mcxa276-pac/src/ctimer0/cr.rs @@ -0,0 +1,20 @@ +#[doc = "Register `CR[%s]` reader"] +pub type R = crate::R; +#[doc = "Field `CAP` reader - Timer Counter Capture Value"] +pub type CapR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Timer Counter Capture Value"] + #[inline(always)] + pub fn cap(&self) -> CapR { + CapR::new(self.bits) + } +} +#[doc = "Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrSpec; +impl crate::RegisterSpec for CrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CrSpec {} +#[doc = "`reset()` method sets CR[%s] to value 0"] +impl crate::Resettable for CrSpec {} diff --git a/mcxa276-pac/src/ctimer0/ctcr.rs b/mcxa276-pac/src/ctimer0/ctcr.rs new file mode 100644 index 000000000..52376d1d8 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/ctcr.rs @@ -0,0 +1,375 @@ +#[doc = "Register `CTCR` reader"] +pub type R = crate::R; +#[doc = "Register `CTCR` writer"] +pub type W = crate::W; +#[doc = "Counter Timer Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctmode { + #[doc = "0: Timer mode"] + Timer = 0, + #[doc = "1: Counter mode rising edge"] + CounterRisingEdge = 1, + #[doc = "2: Counter mode falling edge"] + CounterFallingEdge = 2, + #[doc = "3: Counter mode dual edge"] + CounterDualEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctmode { + type Ux = u8; +} +impl crate::IsEnum for Ctmode {} +#[doc = "Field `CTMODE` reader - Counter Timer Mode"] +pub type CtmodeR = crate::FieldReader; +impl CtmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctmode { + match self.bits { + 0 => Ctmode::Timer, + 1 => Ctmode::CounterRisingEdge, + 2 => Ctmode::CounterFallingEdge, + 3 => Ctmode::CounterDualEdge, + _ => unreachable!(), + } + } + #[doc = "Timer mode"] + #[inline(always)] + pub fn is_timer(&self) -> bool { + *self == Ctmode::Timer + } + #[doc = "Counter mode rising edge"] + #[inline(always)] + pub fn is_counter_rising_edge(&self) -> bool { + *self == Ctmode::CounterRisingEdge + } + #[doc = "Counter mode falling edge"] + #[inline(always)] + pub fn is_counter_falling_edge(&self) -> bool { + *self == Ctmode::CounterFallingEdge + } + #[doc = "Counter mode dual edge"] + #[inline(always)] + pub fn is_counter_dual_edge(&self) -> bool { + *self == Ctmode::CounterDualEdge + } +} +#[doc = "Field `CTMODE` writer - Counter Timer Mode"] +pub type CtmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ctmode, crate::Safe>; +impl<'a, REG> CtmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Timer mode"] + #[inline(always)] + pub fn timer(self) -> &'a mut crate::W { + self.variant(Ctmode::Timer) + } + #[doc = "Counter mode rising edge"] + #[inline(always)] + pub fn counter_rising_edge(self) -> &'a mut crate::W { + self.variant(Ctmode::CounterRisingEdge) + } + #[doc = "Counter mode falling edge"] + #[inline(always)] + pub fn counter_falling_edge(self) -> &'a mut crate::W { + self.variant(Ctmode::CounterFallingEdge) + } + #[doc = "Counter mode dual edge"] + #[inline(always)] + pub fn counter_dual_edge(self) -> &'a mut crate::W { + self.variant(Ctmode::CounterDualEdge) + } +} +#[doc = "Count Input Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cinsel { + #[doc = "0: Channel 0, CAPn\\[0\\] for CTIMERn"] + Channel0 = 0, + #[doc = "1: Channel 1, CAPn\\[1\\] for CTIMERn"] + Channel1 = 1, + #[doc = "2: Channel 2, CAPn\\[2\\] for CTIMERn"] + Channel2 = 2, + #[doc = "3: Channel 3, CAPn\\[3\\] for CTIMERn"] + Channel3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cinsel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cinsel { + type Ux = u8; +} +impl crate::IsEnum for Cinsel {} +#[doc = "Field `CINSEL` reader - Count Input Select"] +pub type CinselR = crate::FieldReader; +impl CinselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cinsel { + match self.bits { + 0 => Cinsel::Channel0, + 1 => Cinsel::Channel1, + 2 => Cinsel::Channel2, + 3 => Cinsel::Channel3, + _ => unreachable!(), + } + } + #[doc = "Channel 0, CAPn\\[0\\] for CTIMERn"] + #[inline(always)] + pub fn is_channel_0(&self) -> bool { + *self == Cinsel::Channel0 + } + #[doc = "Channel 1, CAPn\\[1\\] for CTIMERn"] + #[inline(always)] + pub fn is_channel_1(&self) -> bool { + *self == Cinsel::Channel1 + } + #[doc = "Channel 2, CAPn\\[2\\] for CTIMERn"] + #[inline(always)] + pub fn is_channel_2(&self) -> bool { + *self == Cinsel::Channel2 + } + #[doc = "Channel 3, CAPn\\[3\\] for CTIMERn"] + #[inline(always)] + pub fn is_channel_3(&self) -> bool { + *self == Cinsel::Channel3 + } +} +#[doc = "Field `CINSEL` writer - Count Input Select"] +pub type CinselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cinsel, crate::Safe>; +impl<'a, REG> CinselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Channel 0, CAPn\\[0\\] for CTIMERn"] + #[inline(always)] + pub fn channel_0(self) -> &'a mut crate::W { + self.variant(Cinsel::Channel0) + } + #[doc = "Channel 1, CAPn\\[1\\] for CTIMERn"] + #[inline(always)] + pub fn channel_1(self) -> &'a mut crate::W { + self.variant(Cinsel::Channel1) + } + #[doc = "Channel 2, CAPn\\[2\\] for CTIMERn"] + #[inline(always)] + pub fn channel_2(self) -> &'a mut crate::W { + self.variant(Cinsel::Channel2) + } + #[doc = "Channel 3, CAPn\\[3\\] for CTIMERn"] + #[inline(always)] + pub fn channel_3(self) -> &'a mut crate::W { + self.variant(Cinsel::Channel3) + } +} +#[doc = "Field `ENCC` reader - Capture Channel Enable"] +pub type EnccR = crate::BitReader; +#[doc = "Field `ENCC` writer - Capture Channel Enable"] +pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Edge Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Selcc { + #[doc = "0: Capture channel 0 rising edge"] + Channel0Rising = 0, + #[doc = "1: Capture channel 0 falling edge"] + Channel0Falling = 1, + #[doc = "2: Capture channel 1 rising edge"] + Channel1Rising = 2, + #[doc = "3: Capture channel 1 falling edge"] + Channel1Falling = 3, + #[doc = "4: Capture channel 2 rising edge"] + Channel2Rising = 4, + #[doc = "5: Capture channel 2 falling edge"] + Channel2Falling = 5, + #[doc = "6: Capture channel 3 rising edge"] + Channel3Rising = 6, + #[doc = "7: Capture channel 3 falling edge"] + Channel3Falling = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Selcc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Selcc { + type Ux = u8; +} +impl crate::IsEnum for Selcc {} +#[doc = "Field `SELCC` reader - Edge Select"] +pub type SelccR = crate::FieldReader; +impl SelccR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Selcc { + match self.bits { + 0 => Selcc::Channel0Rising, + 1 => Selcc::Channel0Falling, + 2 => Selcc::Channel1Rising, + 3 => Selcc::Channel1Falling, + 4 => Selcc::Channel2Rising, + 5 => Selcc::Channel2Falling, + 6 => Selcc::Channel3Rising, + 7 => Selcc::Channel3Falling, + _ => unreachable!(), + } + } + #[doc = "Capture channel 0 rising edge"] + #[inline(always)] + pub fn is_channel_0_rising(&self) -> bool { + *self == Selcc::Channel0Rising + } + #[doc = "Capture channel 0 falling edge"] + #[inline(always)] + pub fn is_channel_0_falling(&self) -> bool { + *self == Selcc::Channel0Falling + } + #[doc = "Capture channel 1 rising edge"] + #[inline(always)] + pub fn is_channel_1_rising(&self) -> bool { + *self == Selcc::Channel1Rising + } + #[doc = "Capture channel 1 falling edge"] + #[inline(always)] + pub fn is_channel_1_falling(&self) -> bool { + *self == Selcc::Channel1Falling + } + #[doc = "Capture channel 2 rising edge"] + #[inline(always)] + pub fn is_channel_2_rising(&self) -> bool { + *self == Selcc::Channel2Rising + } + #[doc = "Capture channel 2 falling edge"] + #[inline(always)] + pub fn is_channel_2_falling(&self) -> bool { + *self == Selcc::Channel2Falling + } + #[doc = "Capture channel 3 rising edge"] + #[inline(always)] + pub fn is_channel_3_rising(&self) -> bool { + *self == Selcc::Channel3Rising + } + #[doc = "Capture channel 3 falling edge"] + #[inline(always)] + pub fn is_channel_3_falling(&self) -> bool { + *self == Selcc::Channel3Falling + } +} +#[doc = "Field `SELCC` writer - Edge Select"] +pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc, crate::Safe>; +impl<'a, REG> SelccW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Capture channel 0 rising edge"] + #[inline(always)] + pub fn channel_0_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Channel0Rising) + } + #[doc = "Capture channel 0 falling edge"] + #[inline(always)] + pub fn channel_0_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Channel0Falling) + } + #[doc = "Capture channel 1 rising edge"] + #[inline(always)] + pub fn channel_1_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Channel1Rising) + } + #[doc = "Capture channel 1 falling edge"] + #[inline(always)] + pub fn channel_1_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Channel1Falling) + } + #[doc = "Capture channel 2 rising edge"] + #[inline(always)] + pub fn channel_2_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Channel2Rising) + } + #[doc = "Capture channel 2 falling edge"] + #[inline(always)] + pub fn channel_2_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Channel2Falling) + } + #[doc = "Capture channel 3 rising edge"] + #[inline(always)] + pub fn channel_3_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Channel3Rising) + } + #[doc = "Capture channel 3 falling edge"] + #[inline(always)] + pub fn channel_3_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Channel3Falling) + } +} +impl R { + #[doc = "Bits 0:1 - Counter Timer Mode"] + #[inline(always)] + pub fn ctmode(&self) -> CtmodeR { + CtmodeR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Count Input Select"] + #[inline(always)] + pub fn cinsel(&self) -> CinselR { + CinselR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Capture Channel Enable"] + #[inline(always)] + pub fn encc(&self) -> EnccR { + EnccR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - Edge Select"] + #[inline(always)] + pub fn selcc(&self) -> SelccR { + SelccR::new(((self.bits >> 5) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Counter Timer Mode"] + #[inline(always)] + pub fn ctmode(&mut self) -> CtmodeW { + CtmodeW::new(self, 0) + } + #[doc = "Bits 2:3 - Count Input Select"] + #[inline(always)] + pub fn cinsel(&mut self) -> CinselW { + CinselW::new(self, 2) + } + #[doc = "Bit 4 - Capture Channel Enable"] + #[inline(always)] + pub fn encc(&mut self) -> EnccW { + EnccW::new(self, 4) + } + #[doc = "Bits 5:7 - Edge Select"] + #[inline(always)] + pub fn selcc(&mut self) -> SelccW { + SelccW::new(self, 5) + } +} +#[doc = "Count Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtcrSpec; +impl crate::RegisterSpec for CtcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"] +impl crate::Readable for CtcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"] +impl crate::Writable for CtcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTCR to value 0"] +impl crate::Resettable for CtcrSpec {} diff --git a/mcxa276-pac/src/ctimer0/emr.rs b/mcxa276-pac/src/ctimer0/emr.rs new file mode 100644 index 000000000..30ae43a01 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/emr.rs @@ -0,0 +1,657 @@ +#[doc = "Register `EMR` reader"] +pub type R = crate::R; +#[doc = "Register `EMR` writer"] +pub type W = crate::W; +#[doc = "External Match 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Em0 { + #[doc = "0: Low"] + Clear = 0, + #[doc = "1: High"] + Set = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Em0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EM0` reader - External Match 0"] +pub type Em0R = crate::BitReader; +impl Em0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Em0 { + match self.bits { + false => Em0::Clear, + true => Em0::Set, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Em0::Clear + } + #[doc = "High"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Em0::Set + } +} +#[doc = "Field `EM0` writer - External Match 0"] +pub type Em0W<'a, REG> = crate::BitWriter<'a, REG, Em0>; +impl<'a, REG> Em0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Em0::Clear) + } + #[doc = "High"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Em0::Set) + } +} +#[doc = "External Match 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Em1 { + #[doc = "0: Low"] + Clear = 0, + #[doc = "1: High"] + Set = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Em1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EM1` reader - External Match 1"] +pub type Em1R = crate::BitReader; +impl Em1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Em1 { + match self.bits { + false => Em1::Clear, + true => Em1::Set, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Em1::Clear + } + #[doc = "High"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Em1::Set + } +} +#[doc = "Field `EM1` writer - External Match 1"] +pub type Em1W<'a, REG> = crate::BitWriter<'a, REG, Em1>; +impl<'a, REG> Em1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Em1::Clear) + } + #[doc = "High"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Em1::Set) + } +} +#[doc = "External Match 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Em2 { + #[doc = "0: Low"] + Clear = 0, + #[doc = "1: High"] + Set = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Em2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EM2` reader - External Match 2"] +pub type Em2R = crate::BitReader; +impl Em2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Em2 { + match self.bits { + false => Em2::Clear, + true => Em2::Set, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Em2::Clear + } + #[doc = "High"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Em2::Set + } +} +#[doc = "Field `EM2` writer - External Match 2"] +pub type Em2W<'a, REG> = crate::BitWriter<'a, REG, Em2>; +impl<'a, REG> Em2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Em2::Clear) + } + #[doc = "High"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Em2::Set) + } +} +#[doc = "External Match 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Em3 { + #[doc = "0: Low"] + Clear = 0, + #[doc = "1: High"] + Set = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Em3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EM3` reader - External Match 3"] +pub type Em3R = crate::BitReader; +impl Em3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Em3 { + match self.bits { + false => Em3::Clear, + true => Em3::Set, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Em3::Clear + } + #[doc = "High"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Em3::Set + } +} +#[doc = "Field `EM3` writer - External Match 3"] +pub type Em3W<'a, REG> = crate::BitWriter<'a, REG, Em3>; +impl<'a, REG> Em3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Em3::Clear) + } + #[doc = "High"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Em3::Set) + } +} +#[doc = "External Match Control 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc0 { + #[doc = "0: Does nothing"] + DoNothing = 0, + #[doc = "1: Goes low"] + Clear = 1, + #[doc = "2: Goes high"] + Set = 2, + #[doc = "3: Toggles"] + Toggle = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc0 { + type Ux = u8; +} +impl crate::IsEnum for Emc0 {} +#[doc = "Field `EMC0` reader - External Match Control 0"] +pub type Emc0R = crate::FieldReader; +impl Emc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc0 { + match self.bits { + 0 => Emc0::DoNothing, + 1 => Emc0::Clear, + 2 => Emc0::Set, + 3 => Emc0::Toggle, + _ => unreachable!(), + } + } + #[doc = "Does nothing"] + #[inline(always)] + pub fn is_do_nothing(&self) -> bool { + *self == Emc0::DoNothing + } + #[doc = "Goes low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Emc0::Clear + } + #[doc = "Goes high"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Emc0::Set + } + #[doc = "Toggles"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == Emc0::Toggle + } +} +#[doc = "Field `EMC0` writer - External Match Control 0"] +pub type Emc0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc0, crate::Safe>; +impl<'a, REG> Emc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn do_nothing(self) -> &'a mut crate::W { + self.variant(Emc0::DoNothing) + } + #[doc = "Goes low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Emc0::Clear) + } + #[doc = "Goes high"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Emc0::Set) + } + #[doc = "Toggles"] + #[inline(always)] + pub fn toggle(self) -> &'a mut crate::W { + self.variant(Emc0::Toggle) + } +} +#[doc = "External Match Control 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc1 { + #[doc = "0: Does nothing"] + DoNothing = 0, + #[doc = "1: Goes low"] + Clear = 1, + #[doc = "2: Goes high"] + Set = 2, + #[doc = "3: Toggles"] + Toggle = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc1 { + type Ux = u8; +} +impl crate::IsEnum for Emc1 {} +#[doc = "Field `EMC1` reader - External Match Control 1"] +pub type Emc1R = crate::FieldReader; +impl Emc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc1 { + match self.bits { + 0 => Emc1::DoNothing, + 1 => Emc1::Clear, + 2 => Emc1::Set, + 3 => Emc1::Toggle, + _ => unreachable!(), + } + } + #[doc = "Does nothing"] + #[inline(always)] + pub fn is_do_nothing(&self) -> bool { + *self == Emc1::DoNothing + } + #[doc = "Goes low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Emc1::Clear + } + #[doc = "Goes high"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Emc1::Set + } + #[doc = "Toggles"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == Emc1::Toggle + } +} +#[doc = "Field `EMC1` writer - External Match Control 1"] +pub type Emc1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc1, crate::Safe>; +impl<'a, REG> Emc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn do_nothing(self) -> &'a mut crate::W { + self.variant(Emc1::DoNothing) + } + #[doc = "Goes low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Emc1::Clear) + } + #[doc = "Goes high"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Emc1::Set) + } + #[doc = "Toggles"] + #[inline(always)] + pub fn toggle(self) -> &'a mut crate::W { + self.variant(Emc1::Toggle) + } +} +#[doc = "External Match Control 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc2 { + #[doc = "0: Does nothing"] + DoNothing = 0, + #[doc = "1: Goes low"] + Clear = 1, + #[doc = "2: Goes high"] + Set = 2, + #[doc = "3: Toggles"] + Toggle = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc2 { + type Ux = u8; +} +impl crate::IsEnum for Emc2 {} +#[doc = "Field `EMC2` reader - External Match Control 2"] +pub type Emc2R = crate::FieldReader; +impl Emc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc2 { + match self.bits { + 0 => Emc2::DoNothing, + 1 => Emc2::Clear, + 2 => Emc2::Set, + 3 => Emc2::Toggle, + _ => unreachable!(), + } + } + #[doc = "Does nothing"] + #[inline(always)] + pub fn is_do_nothing(&self) -> bool { + *self == Emc2::DoNothing + } + #[doc = "Goes low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Emc2::Clear + } + #[doc = "Goes high"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Emc2::Set + } + #[doc = "Toggles"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == Emc2::Toggle + } +} +#[doc = "Field `EMC2` writer - External Match Control 2"] +pub type Emc2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc2, crate::Safe>; +impl<'a, REG> Emc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn do_nothing(self) -> &'a mut crate::W { + self.variant(Emc2::DoNothing) + } + #[doc = "Goes low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Emc2::Clear) + } + #[doc = "Goes high"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Emc2::Set) + } + #[doc = "Toggles"] + #[inline(always)] + pub fn toggle(self) -> &'a mut crate::W { + self.variant(Emc2::Toggle) + } +} +#[doc = "External Match Control 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc3 { + #[doc = "0: Does nothing"] + DoNothing = 0, + #[doc = "1: Goes low"] + Clear = 1, + #[doc = "2: Goes high"] + Set = 2, + #[doc = "3: Toggles"] + Toggle = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc3 { + type Ux = u8; +} +impl crate::IsEnum for Emc3 {} +#[doc = "Field `EMC3` reader - External Match Control 3"] +pub type Emc3R = crate::FieldReader; +impl Emc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc3 { + match self.bits { + 0 => Emc3::DoNothing, + 1 => Emc3::Clear, + 2 => Emc3::Set, + 3 => Emc3::Toggle, + _ => unreachable!(), + } + } + #[doc = "Does nothing"] + #[inline(always)] + pub fn is_do_nothing(&self) -> bool { + *self == Emc3::DoNothing + } + #[doc = "Goes low"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Emc3::Clear + } + #[doc = "Goes high"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Emc3::Set + } + #[doc = "Toggles"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == Emc3::Toggle + } +} +#[doc = "Field `EMC3` writer - External Match Control 3"] +pub type Emc3W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc3, crate::Safe>; +impl<'a, REG> Emc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn do_nothing(self) -> &'a mut crate::W { + self.variant(Emc3::DoNothing) + } + #[doc = "Goes low"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Emc3::Clear) + } + #[doc = "Goes high"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Emc3::Set) + } + #[doc = "Toggles"] + #[inline(always)] + pub fn toggle(self) -> &'a mut crate::W { + self.variant(Emc3::Toggle) + } +} +impl R { + #[doc = "Bit 0 - External Match 0"] + #[inline(always)] + pub fn em0(&self) -> Em0R { + Em0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - External Match 1"] + #[inline(always)] + pub fn em1(&self) -> Em1R { + Em1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - External Match 2"] + #[inline(always)] + pub fn em2(&self) -> Em2R { + Em2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - External Match 3"] + #[inline(always)] + pub fn em3(&self) -> Em3R { + Em3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - External Match Control 0"] + #[inline(always)] + pub fn emc0(&self) -> Emc0R { + Emc0R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - External Match Control 1"] + #[inline(always)] + pub fn emc1(&self) -> Emc1R { + Emc1R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - External Match Control 2"] + #[inline(always)] + pub fn emc2(&self) -> Emc2R { + Emc2R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - External Match Control 3"] + #[inline(always)] + pub fn emc3(&self) -> Emc3R { + Emc3R::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Match 0"] + #[inline(always)] + pub fn em0(&mut self) -> Em0W { + Em0W::new(self, 0) + } + #[doc = "Bit 1 - External Match 1"] + #[inline(always)] + pub fn em1(&mut self) -> Em1W { + Em1W::new(self, 1) + } + #[doc = "Bit 2 - External Match 2"] + #[inline(always)] + pub fn em2(&mut self) -> Em2W { + Em2W::new(self, 2) + } + #[doc = "Bit 3 - External Match 3"] + #[inline(always)] + pub fn em3(&mut self) -> Em3W { + Em3W::new(self, 3) + } + #[doc = "Bits 4:5 - External Match Control 0"] + #[inline(always)] + pub fn emc0(&mut self) -> Emc0W { + Emc0W::new(self, 4) + } + #[doc = "Bits 6:7 - External Match Control 1"] + #[inline(always)] + pub fn emc1(&mut self) -> Emc1W { + Emc1W::new(self, 6) + } + #[doc = "Bits 8:9 - External Match Control 2"] + #[inline(always)] + pub fn emc2(&mut self) -> Emc2W { + Emc2W::new(self, 8) + } + #[doc = "Bits 10:11 - External Match Control 3"] + #[inline(always)] + pub fn emc3(&mut self) -> Emc3W { + Emc3W::new(self, 10) + } +} +#[doc = "External Match\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EmrSpec; +impl crate::RegisterSpec for EmrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`emr::R`](R) reader structure"] +impl crate::Readable for EmrSpec {} +#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"] +impl crate::Writable for EmrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EMR to value 0"] +impl crate::Resettable for EmrSpec {} diff --git a/mcxa276-pac/src/ctimer0/ir.rs b/mcxa276-pac/src/ctimer0/ir.rs new file mode 100644 index 000000000..2ab9e5dd9 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/ir.rs @@ -0,0 +1,133 @@ +#[doc = "Register `IR` reader"] +pub type R = crate::R; +#[doc = "Register `IR` writer"] +pub type W = crate::W; +#[doc = "Field `MR0INT` reader - Interrupt Flag for Match Channel 0 Event"] +pub type Mr0intR = crate::BitReader; +#[doc = "Field `MR0INT` writer - Interrupt Flag for Match Channel 0 Event"] +pub type Mr0intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR1INT` reader - Interrupt Flag for Match Channel 1 Event"] +pub type Mr1intR = crate::BitReader; +#[doc = "Field `MR1INT` writer - Interrupt Flag for Match Channel 1 Event"] +pub type Mr1intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR2INT` reader - Interrupt Flag for Match Channel 2 Event"] +pub type Mr2intR = crate::BitReader; +#[doc = "Field `MR2INT` writer - Interrupt Flag for Match Channel 2 Event"] +pub type Mr2intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR3INT` reader - Interrupt Flag for Match Channel 3 Event"] +pub type Mr3intR = crate::BitReader; +#[doc = "Field `MR3INT` writer - Interrupt Flag for Match Channel 3 Event"] +pub type Mr3intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR0INT` reader - Interrupt Flag for Capture Channel 0 Event"] +pub type Cr0intR = crate::BitReader; +#[doc = "Field `CR0INT` writer - Interrupt Flag for Capture Channel 0 Event"] +pub type Cr0intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR1INT` reader - Interrupt Flag for Capture Channel 1 Event"] +pub type Cr1intR = crate::BitReader; +#[doc = "Field `CR1INT` writer - Interrupt Flag for Capture Channel 1 Event"] +pub type Cr1intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR2INT` reader - Interrupt Flag for Capture Channel 2 Event"] +pub type Cr2intR = crate::BitReader; +#[doc = "Field `CR2INT` writer - Interrupt Flag for Capture Channel 2 Event"] +pub type Cr2intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR3INT` reader - Interrupt Flag for Capture Channel 3 Event"] +pub type Cr3intR = crate::BitReader; +#[doc = "Field `CR3INT` writer - Interrupt Flag for Capture Channel 3 Event"] +pub type Cr3intW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Interrupt Flag for Match Channel 0 Event"] + #[inline(always)] + pub fn mr0int(&self) -> Mr0intR { + Mr0intR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt Flag for Match Channel 1 Event"] + #[inline(always)] + pub fn mr1int(&self) -> Mr1intR { + Mr1intR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt Flag for Match Channel 2 Event"] + #[inline(always)] + pub fn mr2int(&self) -> Mr2intR { + Mr2intR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt Flag for Match Channel 3 Event"] + #[inline(always)] + pub fn mr3int(&self) -> Mr3intR { + Mr3intR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt Flag for Capture Channel 0 Event"] + #[inline(always)] + pub fn cr0int(&self) -> Cr0intR { + Cr0intR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt Flag for Capture Channel 1 Event"] + #[inline(always)] + pub fn cr1int(&self) -> Cr1intR { + Cr1intR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt Flag for Capture Channel 2 Event"] + #[inline(always)] + pub fn cr2int(&self) -> Cr2intR { + Cr2intR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt Flag for Capture Channel 3 Event"] + #[inline(always)] + pub fn cr3int(&self) -> Cr3intR { + Cr3intR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt Flag for Match Channel 0 Event"] + #[inline(always)] + pub fn mr0int(&mut self) -> Mr0intW { + Mr0intW::new(self, 0) + } + #[doc = "Bit 1 - Interrupt Flag for Match Channel 1 Event"] + #[inline(always)] + pub fn mr1int(&mut self) -> Mr1intW { + Mr1intW::new(self, 1) + } + #[doc = "Bit 2 - Interrupt Flag for Match Channel 2 Event"] + #[inline(always)] + pub fn mr2int(&mut self) -> Mr2intW { + Mr2intW::new(self, 2) + } + #[doc = "Bit 3 - Interrupt Flag for Match Channel 3 Event"] + #[inline(always)] + pub fn mr3int(&mut self) -> Mr3intW { + Mr3intW::new(self, 3) + } + #[doc = "Bit 4 - Interrupt Flag for Capture Channel 0 Event"] + #[inline(always)] + pub fn cr0int(&mut self) -> Cr0intW { + Cr0intW::new(self, 4) + } + #[doc = "Bit 5 - Interrupt Flag for Capture Channel 1 Event"] + #[inline(always)] + pub fn cr1int(&mut self) -> Cr1intW { + Cr1intW::new(self, 5) + } + #[doc = "Bit 6 - Interrupt Flag for Capture Channel 2 Event"] + #[inline(always)] + pub fn cr2int(&mut self) -> Cr2intW { + Cr2intW::new(self, 6) + } + #[doc = "Bit 7 - Interrupt Flag for Capture Channel 3 Event"] + #[inline(always)] + pub fn cr3int(&mut self) -> Cr3intW { + Cr3intW::new(self, 7) + } +} +#[doc = "Interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrSpec; +impl crate::RegisterSpec for IrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ir::R`](R) reader structure"] +impl crate::Readable for IrSpec {} +#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"] +impl crate::Writable for IrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IR to value 0"] +impl crate::Resettable for IrSpec {} diff --git a/mcxa276-pac/src/ctimer0/mcr.rs b/mcxa276-pac/src/ctimer0/mcr.rs new file mode 100644 index 000000000..36a580ff8 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/mcr.rs @@ -0,0 +1,1029 @@ +#[doc = "Register `MCR` reader"] +pub type R = crate::R; +#[doc = "Register `MCR` writer"] +pub type W = crate::W; +#[doc = "Interrupt on MR0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0i { + #[doc = "0: Does not generate"] + Mr0i0 = 0, + #[doc = "1: Generates"] + Mr0i1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0I` reader - Interrupt on MR0"] +pub type Mr0iR = crate::BitReader; +impl Mr0iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0i { + match self.bits { + false => Mr0i::Mr0i0, + true => Mr0i::Mr0i1, + } + } + #[doc = "Does not generate"] + #[inline(always)] + pub fn is_mr0i_0(&self) -> bool { + *self == Mr0i::Mr0i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_mr0i_1(&self) -> bool { + *self == Mr0i::Mr0i1 + } +} +#[doc = "Field `MR0I` writer - Interrupt on MR0"] +pub type Mr0iW<'a, REG> = crate::BitWriter<'a, REG, Mr0i>; +impl<'a, REG> Mr0iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generate"] + #[inline(always)] + pub fn mr0i_0(self) -> &'a mut crate::W { + self.variant(Mr0i::Mr0i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn mr0i_1(self) -> &'a mut crate::W { + self.variant(Mr0i::Mr0i1) + } +} +#[doc = "Reset on MR0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0r { + #[doc = "0: Does not reset"] + Mr0r0 = 0, + #[doc = "1: Resets"] + Mr0r1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0R` reader - Reset on MR0"] +pub type Mr0rR = crate::BitReader; +impl Mr0rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0r { + match self.bits { + false => Mr0r::Mr0r0, + true => Mr0r::Mr0r1, + } + } + #[doc = "Does not reset"] + #[inline(always)] + pub fn is_mr0r_0(&self) -> bool { + *self == Mr0r::Mr0r0 + } + #[doc = "Resets"] + #[inline(always)] + pub fn is_mr0r_1(&self) -> bool { + *self == Mr0r::Mr0r1 + } +} +#[doc = "Field `MR0R` writer - Reset on MR0"] +pub type Mr0rW<'a, REG> = crate::BitWriter<'a, REG, Mr0r>; +impl<'a, REG> Mr0rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reset"] + #[inline(always)] + pub fn mr0r_0(self) -> &'a mut crate::W { + self.variant(Mr0r::Mr0r0) + } + #[doc = "Resets"] + #[inline(always)] + pub fn mr0r_1(self) -> &'a mut crate::W { + self.variant(Mr0r::Mr0r1) + } +} +#[doc = "Stop on MR0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0s { + #[doc = "0: Does not stop"] + Mr0s0 = 0, + #[doc = "1: Stops"] + Mr0s1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0S` reader - Stop on MR0"] +pub type Mr0sR = crate::BitReader; +impl Mr0sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0s { + match self.bits { + false => Mr0s::Mr0s0, + true => Mr0s::Mr0s1, + } + } + #[doc = "Does not stop"] + #[inline(always)] + pub fn is_mr0s_0(&self) -> bool { + *self == Mr0s::Mr0s0 + } + #[doc = "Stops"] + #[inline(always)] + pub fn is_mr0s_1(&self) -> bool { + *self == Mr0s::Mr0s1 + } +} +#[doc = "Field `MR0S` writer - Stop on MR0"] +pub type Mr0sW<'a, REG> = crate::BitWriter<'a, REG, Mr0s>; +impl<'a, REG> Mr0sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not stop"] + #[inline(always)] + pub fn mr0s_0(self) -> &'a mut crate::W { + self.variant(Mr0s::Mr0s0) + } + #[doc = "Stops"] + #[inline(always)] + pub fn mr0s_1(self) -> &'a mut crate::W { + self.variant(Mr0s::Mr0s1) + } +} +#[doc = "Interrupt on MR1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1i { + #[doc = "0: Does not generate"] + Mr1i0 = 0, + #[doc = "1: Generates"] + Mr1i1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1I` reader - Interrupt on MR1"] +pub type Mr1iR = crate::BitReader; +impl Mr1iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1i { + match self.bits { + false => Mr1i::Mr1i0, + true => Mr1i::Mr1i1, + } + } + #[doc = "Does not generate"] + #[inline(always)] + pub fn is_mr1i_0(&self) -> bool { + *self == Mr1i::Mr1i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_mr1i_1(&self) -> bool { + *self == Mr1i::Mr1i1 + } +} +#[doc = "Field `MR1I` writer - Interrupt on MR1"] +pub type Mr1iW<'a, REG> = crate::BitWriter<'a, REG, Mr1i>; +impl<'a, REG> Mr1iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generate"] + #[inline(always)] + pub fn mr1i_0(self) -> &'a mut crate::W { + self.variant(Mr1i::Mr1i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn mr1i_1(self) -> &'a mut crate::W { + self.variant(Mr1i::Mr1i1) + } +} +#[doc = "Reset on MR1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1r { + #[doc = "0: Does not reset"] + Mr1r0 = 0, + #[doc = "1: Resets"] + Mr1r1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1R` reader - Reset on MR1"] +pub type Mr1rR = crate::BitReader; +impl Mr1rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1r { + match self.bits { + false => Mr1r::Mr1r0, + true => Mr1r::Mr1r1, + } + } + #[doc = "Does not reset"] + #[inline(always)] + pub fn is_mr1r_0(&self) -> bool { + *self == Mr1r::Mr1r0 + } + #[doc = "Resets"] + #[inline(always)] + pub fn is_mr1r_1(&self) -> bool { + *self == Mr1r::Mr1r1 + } +} +#[doc = "Field `MR1R` writer - Reset on MR1"] +pub type Mr1rW<'a, REG> = crate::BitWriter<'a, REG, Mr1r>; +impl<'a, REG> Mr1rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reset"] + #[inline(always)] + pub fn mr1r_0(self) -> &'a mut crate::W { + self.variant(Mr1r::Mr1r0) + } + #[doc = "Resets"] + #[inline(always)] + pub fn mr1r_1(self) -> &'a mut crate::W { + self.variant(Mr1r::Mr1r1) + } +} +#[doc = "Stop on MR1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1s { + #[doc = "0: Does not stop"] + Mris0 = 0, + #[doc = "1: Stops"] + Mris1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1S` reader - Stop on MR1"] +pub type Mr1sR = crate::BitReader; +impl Mr1sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1s { + match self.bits { + false => Mr1s::Mris0, + true => Mr1s::Mris1, + } + } + #[doc = "Does not stop"] + #[inline(always)] + pub fn is_mris_0(&self) -> bool { + *self == Mr1s::Mris0 + } + #[doc = "Stops"] + #[inline(always)] + pub fn is_mris_1(&self) -> bool { + *self == Mr1s::Mris1 + } +} +#[doc = "Field `MR1S` writer - Stop on MR1"] +pub type Mr1sW<'a, REG> = crate::BitWriter<'a, REG, Mr1s>; +impl<'a, REG> Mr1sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not stop"] + #[inline(always)] + pub fn mris_0(self) -> &'a mut crate::W { + self.variant(Mr1s::Mris0) + } + #[doc = "Stops"] + #[inline(always)] + pub fn mris_1(self) -> &'a mut crate::W { + self.variant(Mr1s::Mris1) + } +} +#[doc = "Interrupt on MR2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2i { + #[doc = "0: Does not generate"] + Mr2i0 = 0, + #[doc = "1: Generates"] + Mr2i1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2I` reader - Interrupt on MR2"] +pub type Mr2iR = crate::BitReader; +impl Mr2iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2i { + match self.bits { + false => Mr2i::Mr2i0, + true => Mr2i::Mr2i1, + } + } + #[doc = "Does not generate"] + #[inline(always)] + pub fn is_mr2i_0(&self) -> bool { + *self == Mr2i::Mr2i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_mr2i_1(&self) -> bool { + *self == Mr2i::Mr2i1 + } +} +#[doc = "Field `MR2I` writer - Interrupt on MR2"] +pub type Mr2iW<'a, REG> = crate::BitWriter<'a, REG, Mr2i>; +impl<'a, REG> Mr2iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generate"] + #[inline(always)] + pub fn mr2i_0(self) -> &'a mut crate::W { + self.variant(Mr2i::Mr2i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn mr2i_1(self) -> &'a mut crate::W { + self.variant(Mr2i::Mr2i1) + } +} +#[doc = "Reset on MR2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2r { + #[doc = "0: Does not reset"] + Mr2r0 = 0, + #[doc = "1: Resets"] + Mr2r1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2R` reader - Reset on MR2"] +pub type Mr2rR = crate::BitReader; +impl Mr2rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2r { + match self.bits { + false => Mr2r::Mr2r0, + true => Mr2r::Mr2r1, + } + } + #[doc = "Does not reset"] + #[inline(always)] + pub fn is_mr2r_0(&self) -> bool { + *self == Mr2r::Mr2r0 + } + #[doc = "Resets"] + #[inline(always)] + pub fn is_mr2r_1(&self) -> bool { + *self == Mr2r::Mr2r1 + } +} +#[doc = "Field `MR2R` writer - Reset on MR2"] +pub type Mr2rW<'a, REG> = crate::BitWriter<'a, REG, Mr2r>; +impl<'a, REG> Mr2rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reset"] + #[inline(always)] + pub fn mr2r_0(self) -> &'a mut crate::W { + self.variant(Mr2r::Mr2r0) + } + #[doc = "Resets"] + #[inline(always)] + pub fn mr2r_1(self) -> &'a mut crate::W { + self.variant(Mr2r::Mr2r1) + } +} +#[doc = "Stop on MR2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2s { + #[doc = "0: Does not stop"] + Mr2s0 = 0, + #[doc = "1: Stops"] + Mr2s1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2S` reader - Stop on MR2"] +pub type Mr2sR = crate::BitReader; +impl Mr2sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2s { + match self.bits { + false => Mr2s::Mr2s0, + true => Mr2s::Mr2s1, + } + } + #[doc = "Does not stop"] + #[inline(always)] + pub fn is_mr2s_0(&self) -> bool { + *self == Mr2s::Mr2s0 + } + #[doc = "Stops"] + #[inline(always)] + pub fn is_mr2s_1(&self) -> bool { + *self == Mr2s::Mr2s1 + } +} +#[doc = "Field `MR2S` writer - Stop on MR2"] +pub type Mr2sW<'a, REG> = crate::BitWriter<'a, REG, Mr2s>; +impl<'a, REG> Mr2sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not stop"] + #[inline(always)] + pub fn mr2s_0(self) -> &'a mut crate::W { + self.variant(Mr2s::Mr2s0) + } + #[doc = "Stops"] + #[inline(always)] + pub fn mr2s_1(self) -> &'a mut crate::W { + self.variant(Mr2s::Mr2s1) + } +} +#[doc = "Interrupt on MR3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3i { + #[doc = "0: Does not generate"] + Mr3i0 = 0, + #[doc = "1: Generates"] + Mr3i1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3I` reader - Interrupt on MR3"] +pub type Mr3iR = crate::BitReader; +impl Mr3iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3i { + match self.bits { + false => Mr3i::Mr3i0, + true => Mr3i::Mr3i1, + } + } + #[doc = "Does not generate"] + #[inline(always)] + pub fn is_mr3i_0(&self) -> bool { + *self == Mr3i::Mr3i0 + } + #[doc = "Generates"] + #[inline(always)] + pub fn is_mr3i_1(&self) -> bool { + *self == Mr3i::Mr3i1 + } +} +#[doc = "Field `MR3I` writer - Interrupt on MR3"] +pub type Mr3iW<'a, REG> = crate::BitWriter<'a, REG, Mr3i>; +impl<'a, REG> Mr3iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not generate"] + #[inline(always)] + pub fn mr3i_0(self) -> &'a mut crate::W { + self.variant(Mr3i::Mr3i0) + } + #[doc = "Generates"] + #[inline(always)] + pub fn mr3i_1(self) -> &'a mut crate::W { + self.variant(Mr3i::Mr3i1) + } +} +#[doc = "Reset on MR3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3r { + #[doc = "0: Does not reset"] + Mr3r0 = 0, + #[doc = "1: Resets"] + Mr3r1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3R` reader - Reset on MR3"] +pub type Mr3rR = crate::BitReader; +impl Mr3rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3r { + match self.bits { + false => Mr3r::Mr3r0, + true => Mr3r::Mr3r1, + } + } + #[doc = "Does not reset"] + #[inline(always)] + pub fn is_mr3r_0(&self) -> bool { + *self == Mr3r::Mr3r0 + } + #[doc = "Resets"] + #[inline(always)] + pub fn is_mr3r_1(&self) -> bool { + *self == Mr3r::Mr3r1 + } +} +#[doc = "Field `MR3R` writer - Reset on MR3"] +pub type Mr3rW<'a, REG> = crate::BitWriter<'a, REG, Mr3r>; +impl<'a, REG> Mr3rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reset"] + #[inline(always)] + pub fn mr3r_0(self) -> &'a mut crate::W { + self.variant(Mr3r::Mr3r0) + } + #[doc = "Resets"] + #[inline(always)] + pub fn mr3r_1(self) -> &'a mut crate::W { + self.variant(Mr3r::Mr3r1) + } +} +#[doc = "Stop on MR3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3s { + #[doc = "0: Does not stop"] + Mr3s0 = 0, + #[doc = "1: Stops"] + Mr3s1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3S` reader - Stop on MR3"] +pub type Mr3sR = crate::BitReader; +impl Mr3sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3s { + match self.bits { + false => Mr3s::Mr3s0, + true => Mr3s::Mr3s1, + } + } + #[doc = "Does not stop"] + #[inline(always)] + pub fn is_mr3s_0(&self) -> bool { + *self == Mr3s::Mr3s0 + } + #[doc = "Stops"] + #[inline(always)] + pub fn is_mr3s_1(&self) -> bool { + *self == Mr3s::Mr3s1 + } +} +#[doc = "Field `MR3S` writer - Stop on MR3"] +pub type Mr3sW<'a, REG> = crate::BitWriter<'a, REG, Mr3s>; +impl<'a, REG> Mr3sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not stop"] + #[inline(always)] + pub fn mr3s_0(self) -> &'a mut crate::W { + self.variant(Mr3s::Mr3s0) + } + #[doc = "Stops"] + #[inline(always)] + pub fn mr3s_1(self) -> &'a mut crate::W { + self.variant(Mr3s::Mr3s1) + } +} +#[doc = "Reload MR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0rl { + #[doc = "0: Does not reload"] + Mr0rl0 = 0, + #[doc = "1: Reloads"] + Mr0rl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0rl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0RL` reader - Reload MR"] +pub type Mr0rlR = crate::BitReader; +impl Mr0rlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0rl { + match self.bits { + false => Mr0rl::Mr0rl0, + true => Mr0rl::Mr0rl1, + } + } + #[doc = "Does not reload"] + #[inline(always)] + pub fn is_mr0rl_0(&self) -> bool { + *self == Mr0rl::Mr0rl0 + } + #[doc = "Reloads"] + #[inline(always)] + pub fn is_mr0rl_1(&self) -> bool { + *self == Mr0rl::Mr0rl1 + } +} +#[doc = "Field `MR0RL` writer - Reload MR"] +pub type Mr0rlW<'a, REG> = crate::BitWriter<'a, REG, Mr0rl>; +impl<'a, REG> Mr0rlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reload"] + #[inline(always)] + pub fn mr0rl_0(self) -> &'a mut crate::W { + self.variant(Mr0rl::Mr0rl0) + } + #[doc = "Reloads"] + #[inline(always)] + pub fn mr0rl_1(self) -> &'a mut crate::W { + self.variant(Mr0rl::Mr0rl1) + } +} +#[doc = "Reload MR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1rl { + #[doc = "0: Does not reload"] + Mr1rl0 = 0, + #[doc = "1: Reloads"] + Mr1rl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1rl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1RL` reader - Reload MR"] +pub type Mr1rlR = crate::BitReader; +impl Mr1rlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1rl { + match self.bits { + false => Mr1rl::Mr1rl0, + true => Mr1rl::Mr1rl1, + } + } + #[doc = "Does not reload"] + #[inline(always)] + pub fn is_mr1rl_0(&self) -> bool { + *self == Mr1rl::Mr1rl0 + } + #[doc = "Reloads"] + #[inline(always)] + pub fn is_mr1rl_1(&self) -> bool { + *self == Mr1rl::Mr1rl1 + } +} +#[doc = "Field `MR1RL` writer - Reload MR"] +pub type Mr1rlW<'a, REG> = crate::BitWriter<'a, REG, Mr1rl>; +impl<'a, REG> Mr1rlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reload"] + #[inline(always)] + pub fn mr1rl_0(self) -> &'a mut crate::W { + self.variant(Mr1rl::Mr1rl0) + } + #[doc = "Reloads"] + #[inline(always)] + pub fn mr1rl_1(self) -> &'a mut crate::W { + self.variant(Mr1rl::Mr1rl1) + } +} +#[doc = "Reload MR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2rl { + #[doc = "0: Does not reload"] + Mr2rl0 = 0, + #[doc = "1: Reloads"] + Mr2rl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2rl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2RL` reader - Reload MR"] +pub type Mr2rlR = crate::BitReader; +impl Mr2rlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2rl { + match self.bits { + false => Mr2rl::Mr2rl0, + true => Mr2rl::Mr2rl1, + } + } + #[doc = "Does not reload"] + #[inline(always)] + pub fn is_mr2rl_0(&self) -> bool { + *self == Mr2rl::Mr2rl0 + } + #[doc = "Reloads"] + #[inline(always)] + pub fn is_mr2rl_1(&self) -> bool { + *self == Mr2rl::Mr2rl1 + } +} +#[doc = "Field `MR2RL` writer - Reload MR"] +pub type Mr2rlW<'a, REG> = crate::BitWriter<'a, REG, Mr2rl>; +impl<'a, REG> Mr2rlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reload"] + #[inline(always)] + pub fn mr2rl_0(self) -> &'a mut crate::W { + self.variant(Mr2rl::Mr2rl0) + } + #[doc = "Reloads"] + #[inline(always)] + pub fn mr2rl_1(self) -> &'a mut crate::W { + self.variant(Mr2rl::Mr2rl1) + } +} +#[doc = "Reload MR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3rl { + #[doc = "0: Does not reload"] + Mr3rl0 = 0, + #[doc = "1: Reloads"] + Mr3rl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3rl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3RL` reader - Reload MR"] +pub type Mr3rlR = crate::BitReader; +impl Mr3rlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3rl { + match self.bits { + false => Mr3rl::Mr3rl0, + true => Mr3rl::Mr3rl1, + } + } + #[doc = "Does not reload"] + #[inline(always)] + pub fn is_mr3rl_0(&self) -> bool { + *self == Mr3rl::Mr3rl0 + } + #[doc = "Reloads"] + #[inline(always)] + pub fn is_mr3rl_1(&self) -> bool { + *self == Mr3rl::Mr3rl1 + } +} +#[doc = "Field `MR3RL` writer - Reload MR"] +pub type Mr3rlW<'a, REG> = crate::BitWriter<'a, REG, Mr3rl>; +impl<'a, REG> Mr3rlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not reload"] + #[inline(always)] + pub fn mr3rl_0(self) -> &'a mut crate::W { + self.variant(Mr3rl::Mr3rl0) + } + #[doc = "Reloads"] + #[inline(always)] + pub fn mr3rl_1(self) -> &'a mut crate::W { + self.variant(Mr3rl::Mr3rl1) + } +} +impl R { + #[doc = "Bit 0 - Interrupt on MR0"] + #[inline(always)] + pub fn mr0i(&self) -> Mr0iR { + Mr0iR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reset on MR0"] + #[inline(always)] + pub fn mr0r(&self) -> Mr0rR { + Mr0rR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Stop on MR0"] + #[inline(always)] + pub fn mr0s(&self) -> Mr0sR { + Mr0sR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt on MR1"] + #[inline(always)] + pub fn mr1i(&self) -> Mr1iR { + Mr1iR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reset on MR1"] + #[inline(always)] + pub fn mr1r(&self) -> Mr1rR { + Mr1rR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stop on MR1"] + #[inline(always)] + pub fn mr1s(&self) -> Mr1sR { + Mr1sR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt on MR2"] + #[inline(always)] + pub fn mr2i(&self) -> Mr2iR { + Mr2iR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reset on MR2"] + #[inline(always)] + pub fn mr2r(&self) -> Mr2rR { + Mr2rR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Stop on MR2"] + #[inline(always)] + pub fn mr2s(&self) -> Mr2sR { + Mr2sR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on MR3"] + #[inline(always)] + pub fn mr3i(&self) -> Mr3iR { + Mr3iR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reset on MR3"] + #[inline(always)] + pub fn mr3r(&self) -> Mr3rR { + Mr3rR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Stop on MR3"] + #[inline(always)] + pub fn mr3s(&self) -> Mr3sR { + Mr3sR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 24 - Reload MR"] + #[inline(always)] + pub fn mr0rl(&self) -> Mr0rlR { + Mr0rlR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reload MR"] + #[inline(always)] + pub fn mr1rl(&self) -> Mr1rlR { + Mr1rlR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reload MR"] + #[inline(always)] + pub fn mr2rl(&self) -> Mr2rlR { + Mr2rlR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reload MR"] + #[inline(always)] + pub fn mr3rl(&self) -> Mr3rlR { + Mr3rlR::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt on MR0"] + #[inline(always)] + pub fn mr0i(&mut self) -> Mr0iW { + Mr0iW::new(self, 0) + } + #[doc = "Bit 1 - Reset on MR0"] + #[inline(always)] + pub fn mr0r(&mut self) -> Mr0rW { + Mr0rW::new(self, 1) + } + #[doc = "Bit 2 - Stop on MR0"] + #[inline(always)] + pub fn mr0s(&mut self) -> Mr0sW { + Mr0sW::new(self, 2) + } + #[doc = "Bit 3 - Interrupt on MR1"] + #[inline(always)] + pub fn mr1i(&mut self) -> Mr1iW { + Mr1iW::new(self, 3) + } + #[doc = "Bit 4 - Reset on MR1"] + #[inline(always)] + pub fn mr1r(&mut self) -> Mr1rW { + Mr1rW::new(self, 4) + } + #[doc = "Bit 5 - Stop on MR1"] + #[inline(always)] + pub fn mr1s(&mut self) -> Mr1sW { + Mr1sW::new(self, 5) + } + #[doc = "Bit 6 - Interrupt on MR2"] + #[inline(always)] + pub fn mr2i(&mut self) -> Mr2iW { + Mr2iW::new(self, 6) + } + #[doc = "Bit 7 - Reset on MR2"] + #[inline(always)] + pub fn mr2r(&mut self) -> Mr2rW { + Mr2rW::new(self, 7) + } + #[doc = "Bit 8 - Stop on MR2"] + #[inline(always)] + pub fn mr2s(&mut self) -> Mr2sW { + Mr2sW::new(self, 8) + } + #[doc = "Bit 9 - Interrupt on MR3"] + #[inline(always)] + pub fn mr3i(&mut self) -> Mr3iW { + Mr3iW::new(self, 9) + } + #[doc = "Bit 10 - Reset on MR3"] + #[inline(always)] + pub fn mr3r(&mut self) -> Mr3rW { + Mr3rW::new(self, 10) + } + #[doc = "Bit 11 - Stop on MR3"] + #[inline(always)] + pub fn mr3s(&mut self) -> Mr3sW { + Mr3sW::new(self, 11) + } + #[doc = "Bit 24 - Reload MR"] + #[inline(always)] + pub fn mr0rl(&mut self) -> Mr0rlW { + Mr0rlW::new(self, 24) + } + #[doc = "Bit 25 - Reload MR"] + #[inline(always)] + pub fn mr1rl(&mut self) -> Mr1rlW { + Mr1rlW::new(self, 25) + } + #[doc = "Bit 26 - Reload MR"] + #[inline(always)] + pub fn mr2rl(&mut self) -> Mr2rlW { + Mr2rlW::new(self, 26) + } + #[doc = "Bit 27 - Reload MR"] + #[inline(always)] + pub fn mr3rl(&mut self) -> Mr3rlW { + Mr3rlW::new(self, 27) + } +} +#[doc = "Match Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct McrSpec; +impl crate::RegisterSpec for McrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for McrSpec {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] +impl crate::Writable for McrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for McrSpec {} diff --git a/mcxa276-pac/src/ctimer0/mr.rs b/mcxa276-pac/src/ctimer0/mr.rs new file mode 100644 index 000000000..6b5bc4957 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/mr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `MR[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `MR[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH` reader - Timer Counter Match Value"] +pub type MatchR = crate::FieldReader; +#[doc = "Field `MATCH` writer - Timer Counter Match Value"] +pub type MatchW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timer Counter Match Value"] + #[inline(always)] + pub fn match_(&self) -> MatchR { + MatchR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timer Counter Match Value"] + #[inline(always)] + pub fn match_(&mut self) -> MatchW { + MatchW::new(self, 0) + } +} +#[doc = "Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrSpec; +impl crate::RegisterSpec for MrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MrSpec {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] +impl crate::Writable for MrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MR[%s] to value 0"] +impl crate::Resettable for MrSpec {} diff --git a/mcxa276-pac/src/ctimer0/msr.rs b/mcxa276-pac/src/ctimer0/msr.rs new file mode 100644 index 000000000..3062f4419 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/msr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `MSR[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `MSR[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH_SHADOW` reader - Timer Counter Match Shadow Value"] +pub type MatchShadowR = crate::FieldReader; +#[doc = "Field `MATCH_SHADOW` writer - Timer Counter Match Shadow Value"] +pub type MatchShadowW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timer Counter Match Shadow Value"] + #[inline(always)] + pub fn match_shadow(&self) -> MatchShadowR { + MatchShadowR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timer Counter Match Shadow Value"] + #[inline(always)] + pub fn match_shadow(&mut self) -> MatchShadowW { + MatchShadowW::new(self, 0) + } +} +#[doc = "Match Shadow\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MsrSpec; +impl crate::RegisterSpec for MsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`msr::R`](R) reader structure"] +impl crate::Readable for MsrSpec {} +#[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"] +impl crate::Writable for MsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MSR[%s] to value 0"] +impl crate::Resettable for MsrSpec {} diff --git a/mcxa276-pac/src/ctimer0/pc.rs b/mcxa276-pac/src/ctimer0/pc.rs new file mode 100644 index 000000000..a9ab5d2b6 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/pc.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PC` reader"] +pub type R = crate::R; +#[doc = "Register `PC` writer"] +pub type W = crate::W; +#[doc = "Field `PCVAL` reader - Prescale Counter Value"] +pub type PcvalR = crate::FieldReader; +#[doc = "Field `PCVAL` writer - Prescale Counter Value"] +pub type PcvalW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Prescale Counter Value"] + #[inline(always)] + pub fn pcval(&self) -> PcvalR { + PcvalR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Prescale Counter Value"] + #[inline(always)] + pub fn pcval(&mut self) -> PcvalW { + PcvalW::new(self, 0) + } +} +#[doc = "Prescale Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PcSpec; +impl crate::RegisterSpec for PcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pc::R`](R) reader structure"] +impl crate::Readable for PcSpec {} +#[doc = "`write(|w| ..)` method takes [`pc::W`](W) writer structure"] +impl crate::Writable for PcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PC to value 0"] +impl crate::Resettable for PcSpec {} diff --git a/mcxa276-pac/src/ctimer0/pr.rs b/mcxa276-pac/src/ctimer0/pr.rs new file mode 100644 index 000000000..03868904c --- /dev/null +++ b/mcxa276-pac/src/ctimer0/pr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PR` reader"] +pub type R = crate::R; +#[doc = "Register `PR` writer"] +pub type W = crate::W; +#[doc = "Field `PRVAL` reader - Prescale Reload Value"] +pub type PrvalR = crate::FieldReader; +#[doc = "Field `PRVAL` writer - Prescale Reload Value"] +pub type PrvalW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Prescale Reload Value"] + #[inline(always)] + pub fn prval(&self) -> PrvalR { + PrvalR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Prescale Reload Value"] + #[inline(always)] + pub fn prval(&mut self) -> PrvalW { + PrvalW::new(self, 0) + } +} +#[doc = "Prescale\n\nYou can [`read`](crate::Reg::read) this register and get [`pr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrSpec; +impl crate::RegisterSpec for PrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pr::R`](R) reader structure"] +impl crate::Readable for PrSpec {} +#[doc = "`write(|w| ..)` method takes [`pr::W`](W) writer structure"] +impl crate::Writable for PrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PR to value 0"] +impl crate::Resettable for PrSpec {} diff --git a/mcxa276-pac/src/ctimer0/pwmc.rs b/mcxa276-pac/src/ctimer0/pwmc.rs new file mode 100644 index 000000000..f285983f1 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/pwmc.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PWMC` reader"] +pub type R = crate::R; +#[doc = "Register `PWMC` writer"] +pub type W = crate::W; +#[doc = "PWM Mode Enable for Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen0 { + #[doc = "0: Disable"] + Match = 0, + #[doc = "1: Enable"] + Pwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN0` reader - PWM Mode Enable for Channel 0"] +pub type Pwmen0R = crate::BitReader; +impl Pwmen0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen0 { + match self.bits { + false => Pwmen0::Match, + true => Pwmen0::Pwm, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Pwmen0::Match + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == Pwmen0::Pwm + } +} +#[doc = "Field `PWMEN0` writer - PWM Mode Enable for Channel 0"] +pub type Pwmen0W<'a, REG> = crate::BitWriter<'a, REG, Pwmen0>; +impl<'a, REG> Pwmen0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Pwmen0::Match) + } + #[doc = "Enable"] + #[inline(always)] + pub fn pwm(self) -> &'a mut crate::W { + self.variant(Pwmen0::Pwm) + } +} +#[doc = "PWM Mode Enable for Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen1 { + #[doc = "0: Disable"] + Match = 0, + #[doc = "1: Enable"] + Pwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN1` reader - PWM Mode Enable for Channel 1"] +pub type Pwmen1R = crate::BitReader; +impl Pwmen1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen1 { + match self.bits { + false => Pwmen1::Match, + true => Pwmen1::Pwm, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Pwmen1::Match + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == Pwmen1::Pwm + } +} +#[doc = "Field `PWMEN1` writer - PWM Mode Enable for Channel 1"] +pub type Pwmen1W<'a, REG> = crate::BitWriter<'a, REG, Pwmen1>; +impl<'a, REG> Pwmen1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Pwmen1::Match) + } + #[doc = "Enable"] + #[inline(always)] + pub fn pwm(self) -> &'a mut crate::W { + self.variant(Pwmen1::Pwm) + } +} +#[doc = "PWM Mode Enable for Channel 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen2 { + #[doc = "0: Disable"] + Match = 0, + #[doc = "1: Enable"] + Pwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN2` reader - PWM Mode Enable for Channel 2"] +pub type Pwmen2R = crate::BitReader; +impl Pwmen2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen2 { + match self.bits { + false => Pwmen2::Match, + true => Pwmen2::Pwm, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Pwmen2::Match + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == Pwmen2::Pwm + } +} +#[doc = "Field `PWMEN2` writer - PWM Mode Enable for Channel 2"] +pub type Pwmen2W<'a, REG> = crate::BitWriter<'a, REG, Pwmen2>; +impl<'a, REG> Pwmen2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Pwmen2::Match) + } + #[doc = "Enable"] + #[inline(always)] + pub fn pwm(self) -> &'a mut crate::W { + self.variant(Pwmen2::Pwm) + } +} +#[doc = "PWM Mode Enable for Channel 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen3 { + #[doc = "0: Disable"] + Match = 0, + #[doc = "1: Enable"] + Pwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN3` reader - PWM Mode Enable for Channel 3"] +pub type Pwmen3R = crate::BitReader; +impl Pwmen3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen3 { + match self.bits { + false => Pwmen3::Match, + true => Pwmen3::Pwm, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Pwmen3::Match + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == Pwmen3::Pwm + } +} +#[doc = "Field `PWMEN3` writer - PWM Mode Enable for Channel 3"] +pub type Pwmen3W<'a, REG> = crate::BitWriter<'a, REG, Pwmen3>; +impl<'a, REG> Pwmen3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Pwmen3::Match) + } + #[doc = "Enable"] + #[inline(always)] + pub fn pwm(self) -> &'a mut crate::W { + self.variant(Pwmen3::Pwm) + } +} +impl R { + #[doc = "Bit 0 - PWM Mode Enable for Channel 0"] + #[inline(always)] + pub fn pwmen0(&self) -> Pwmen0R { + Pwmen0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PWM Mode Enable for Channel 1"] + #[inline(always)] + pub fn pwmen1(&self) -> Pwmen1R { + Pwmen1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - PWM Mode Enable for Channel 2"] + #[inline(always)] + pub fn pwmen2(&self) -> Pwmen2R { + Pwmen2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PWM Mode Enable for Channel 3"] + #[inline(always)] + pub fn pwmen3(&self) -> Pwmen3R { + Pwmen3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PWM Mode Enable for Channel 0"] + #[inline(always)] + pub fn pwmen0(&mut self) -> Pwmen0W { + Pwmen0W::new(self, 0) + } + #[doc = "Bit 1 - PWM Mode Enable for Channel 1"] + #[inline(always)] + pub fn pwmen1(&mut self) -> Pwmen1W { + Pwmen1W::new(self, 1) + } + #[doc = "Bit 2 - PWM Mode Enable for Channel 2"] + #[inline(always)] + pub fn pwmen2(&mut self) -> Pwmen2W { + Pwmen2W::new(self, 2) + } + #[doc = "Bit 3 - PWM Mode Enable for Channel 3"] + #[inline(always)] + pub fn pwmen3(&mut self) -> Pwmen3W { + Pwmen3W::new(self, 3) + } +} +#[doc = "PWM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmcSpec; +impl crate::RegisterSpec for PwmcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwmc::R`](R) reader structure"] +impl crate::Readable for PwmcSpec {} +#[doc = "`write(|w| ..)` method takes [`pwmc::W`](W) writer structure"] +impl crate::Writable for PwmcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWMC to value 0"] +impl crate::Resettable for PwmcSpec {} diff --git a/mcxa276-pac/src/ctimer0/tc.rs b/mcxa276-pac/src/ctimer0/tc.rs new file mode 100644 index 000000000..95f86f58c --- /dev/null +++ b/mcxa276-pac/src/ctimer0/tc.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TC` reader"] +pub type R = crate::R; +#[doc = "Register `TC` writer"] +pub type W = crate::W; +#[doc = "Field `TCVAL` reader - Timer Counter Value"] +pub type TcvalR = crate::FieldReader; +#[doc = "Field `TCVAL` writer - Timer Counter Value"] +pub type TcvalW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timer Counter Value"] + #[inline(always)] + pub fn tcval(&self) -> TcvalR { + TcvalR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timer Counter Value"] + #[inline(always)] + pub fn tcval(&mut self) -> TcvalW { + TcvalW::new(self, 0) + } +} +#[doc = "Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcSpec; +impl crate::RegisterSpec for TcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tc::R`](R) reader structure"] +impl crate::Readable for TcSpec {} +#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] +impl crate::Writable for TcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TC to value 0"] +impl crate::Resettable for TcSpec {} diff --git a/mcxa276-pac/src/ctimer0/tcr.rs b/mcxa276-pac/src/ctimer0/tcr.rs new file mode 100644 index 000000000..5b4dc8770 --- /dev/null +++ b/mcxa276-pac/src/ctimer0/tcr.rs @@ -0,0 +1,273 @@ +#[doc = "Register `TCR` reader"] +pub type R = crate::R; +#[doc = "Register `TCR` writer"] +pub type W = crate::W; +#[doc = "Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cen { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CEN` reader - Counter Enable"] +pub type CenR = crate::BitReader; +impl CenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cen { + match self.bits { + false => Cen::Disabled, + true => Cen::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cen::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cen::Enabled + } +} +#[doc = "Field `CEN` writer - Counter Enable"] +pub type CenW<'a, REG> = crate::BitWriter<'a, REG, Cen>; +impl<'a, REG> CenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cen::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cen::Enabled) + } +} +#[doc = "Counter Reset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crst { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRST` reader - Counter Reset Enable"] +pub type CrstR = crate::BitReader; +impl CrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crst { + match self.bits { + false => Crst::Disabled, + true => Crst::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Crst::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Crst::Enabled + } +} +#[doc = "Field `CRST` writer - Counter Reset Enable"] +pub type CrstW<'a, REG> = crate::BitWriter<'a, REG, Crst>; +impl<'a, REG> CrstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Crst::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Crst::Enabled) + } +} +#[doc = "Allow Global Count Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Agcen { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Agcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AGCEN` reader - Allow Global Count Enable"] +pub type AgcenR = crate::BitReader; +impl AgcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Agcen { + match self.bits { + false => Agcen::Disable, + true => Agcen::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Agcen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Agcen::Enable + } +} +#[doc = "Field `AGCEN` writer - Allow Global Count Enable"] +pub type AgcenW<'a, REG> = crate::BitWriter<'a, REG, Agcen>; +impl<'a, REG> AgcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Agcen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Agcen::Enable) + } +} +#[doc = "Allow Trigger Count Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Atcen { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Atcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ATCEN` reader - Allow Trigger Count Enable"] +pub type AtcenR = crate::BitReader; +impl AtcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Atcen { + match self.bits { + false => Atcen::Disable, + true => Atcen::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Atcen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Atcen::Enable + } +} +#[doc = "Field `ATCEN` writer - Allow Trigger Count Enable"] +pub type AtcenW<'a, REG> = crate::BitWriter<'a, REG, Atcen>; +impl<'a, REG> AtcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Atcen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Atcen::Enable) + } +} +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn cen(&self) -> CenR { + CenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Counter Reset Enable"] + #[inline(always)] + pub fn crst(&self) -> CrstR { + CrstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Allow Global Count Enable"] + #[inline(always)] + pub fn agcen(&self) -> AgcenR { + AgcenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Allow Trigger Count Enable"] + #[inline(always)] + pub fn atcen(&self) -> AtcenR { + AtcenR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn cen(&mut self) -> CenW { + CenW::new(self, 0) + } + #[doc = "Bit 1 - Counter Reset Enable"] + #[inline(always)] + pub fn crst(&mut self) -> CrstW { + CrstW::new(self, 1) + } + #[doc = "Bit 4 - Allow Global Count Enable"] + #[inline(always)] + pub fn agcen(&mut self) -> AgcenW { + AgcenW::new(self, 4) + } + #[doc = "Bit 5 - Allow Trigger Count Enable"] + #[inline(always)] + pub fn atcen(&mut self) -> AtcenW { + AtcenW::new(self, 5) + } +} +#[doc = "Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcrSpec; +impl crate::RegisterSpec for TcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] +impl crate::Readable for TcrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] +impl crate::Writable for TcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCR to value 0"] +impl crate::Resettable for TcrSpec {} diff --git a/mcxa276-pac/src/dac0.rs b/mcxa276-pac/src/dac0.rs new file mode 100644 index 000000000..b5ff97eab --- /dev/null +++ b/mcxa276-pac/src/dac0.rs @@ -0,0 +1,138 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + data: Data, + gcr: Gcr, + fcr: Fcr, + fpr: Fpr, + fsr: Fsr, + ier: Ier, + der: Der, + rcr: Rcr, + tcr: Tcr, + pcr: Pcr, +} +impl RegisterBlock { + #[doc = "0x00 - Version Identifier"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x08 - Data"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x0c - Global Control"] + #[inline(always)] + pub const fn gcr(&self) -> &Gcr { + &self.gcr + } + #[doc = "0x10 - DAC FIFO Control"] + #[inline(always)] + pub const fn fcr(&self) -> &Fcr { + &self.fcr + } + #[doc = "0x14 - DAC FIFO Pointer"] + #[inline(always)] + pub const fn fpr(&self) -> &Fpr { + &self.fpr + } + #[doc = "0x18 - FIFO Status"] + #[inline(always)] + pub const fn fsr(&self) -> &Fsr { + &self.fsr + } + #[doc = "0x1c - Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &Ier { + &self.ier + } + #[doc = "0x20 - DMA Enable"] + #[inline(always)] + pub const fn der(&self) -> &Der { + &self.der + } + #[doc = "0x24 - Reset Control"] + #[inline(always)] + pub const fn rcr(&self) -> &Rcr { + &self.rcr + } + #[doc = "0x28 - Trigger Control"] + #[inline(always)] + pub const fn tcr(&self) -> &Tcr { + &self.tcr + } + #[doc = "0x2c - Periodic Trigger Control"] + #[inline(always)] + pub const fn pcr(&self) -> &Pcr { + &self.pcr + } +} +#[doc = "VERID (r) register accessor: Version Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version Identifier"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "DATA (rw) register accessor: Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "GCR (rw) register accessor: Global Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr`] module"] +#[doc(alias = "GCR")] +pub type Gcr = crate::Reg; +#[doc = "Global Control"] +pub mod gcr; +#[doc = "FCR (rw) register accessor: DAC FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] +#[doc(alias = "FCR")] +pub type Fcr = crate::Reg; +#[doc = "DAC FIFO Control"] +pub mod fcr; +#[doc = "FPR (r) register accessor: DAC FIFO Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`fpr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpr`] module"] +#[doc(alias = "FPR")] +pub type Fpr = crate::Reg; +#[doc = "DAC FIFO Pointer"] +pub mod fpr; +#[doc = "FSR (rw) register accessor: FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsr`] module"] +#[doc(alias = "FSR")] +pub type Fsr = crate::Reg; +#[doc = "FIFO Status"] +pub mod fsr; +#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] +#[doc(alias = "IER")] +pub type Ier = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ier; +#[doc = "DER (rw) register accessor: DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@der`] module"] +#[doc(alias = "DER")] +pub type Der = crate::Reg; +#[doc = "DMA Enable"] +pub mod der; +#[doc = "RCR (rw) register accessor: Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcr`] module"] +#[doc(alias = "RCR")] +pub type Rcr = crate::Reg; +#[doc = "Reset Control"] +pub mod rcr; +#[doc = "TCR (rw) register accessor: Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] +#[doc(alias = "TCR")] +pub type Tcr = crate::Reg; +#[doc = "Trigger Control"] +pub mod tcr; +#[doc = "PCR (rw) register accessor: Periodic Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr`] module"] +#[doc(alias = "PCR")] +pub type Pcr = crate::Reg; +#[doc = "Periodic Trigger Control"] +pub mod pcr; diff --git a/mcxa276-pac/src/dac0/data.rs b/mcxa276-pac/src/dac0/data.rs new file mode 100644 index 000000000..8834695da --- /dev/null +++ b/mcxa276-pac/src/dac0/data.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` reader - FIFO Entry or Buffer Entry"] +pub type DataR = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO Entry or Buffer Entry"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - FIFO Entry or Buffer Entry"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - FIFO Entry or Buffer Entry"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec {} diff --git a/mcxa276-pac/src/dac0/der.rs b/mcxa276-pac/src/dac0/der.rs new file mode 100644 index 000000000..98df40938 --- /dev/null +++ b/mcxa276-pac/src/dac0/der.rs @@ -0,0 +1,147 @@ +#[doc = "Register `DER` reader"] +pub type R = crate::R; +#[doc = "Register `DER` writer"] +pub type W = crate::W; +#[doc = "FIFO Empty DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EmptyDmaen { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EmptyDmaen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EMPTY_DMAEN` reader - FIFO Empty DMA Enable"] +pub type EmptyDmaenR = crate::BitReader; +impl EmptyDmaenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EmptyDmaen { + match self.bits { + false => EmptyDmaen::Disabled, + true => EmptyDmaen::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EmptyDmaen::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EmptyDmaen::Enabled + } +} +#[doc = "Field `EMPTY_DMAEN` writer - FIFO Empty DMA Enable"] +pub type EmptyDmaenW<'a, REG> = crate::BitWriter<'a, REG, EmptyDmaen>; +impl<'a, REG> EmptyDmaenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(EmptyDmaen::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(EmptyDmaen::Enabled) + } +} +#[doc = "FIFO Watermark DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WmDmaen { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WmDmaen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WM_DMAEN` reader - FIFO Watermark DMA Enable"] +pub type WmDmaenR = crate::BitReader; +impl WmDmaenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WmDmaen { + match self.bits { + false => WmDmaen::Disabled, + true => WmDmaen::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WmDmaen::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WmDmaen::Enabled + } +} +#[doc = "Field `WM_DMAEN` writer - FIFO Watermark DMA Enable"] +pub type WmDmaenW<'a, REG> = crate::BitWriter<'a, REG, WmDmaen>; +impl<'a, REG> WmDmaenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WmDmaen::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WmDmaen::Enabled) + } +} +impl R { + #[doc = "Bit 1 - FIFO Empty DMA Enable"] + #[inline(always)] + pub fn empty_dmaen(&self) -> EmptyDmaenR { + EmptyDmaenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO Watermark DMA Enable"] + #[inline(always)] + pub fn wm_dmaen(&self) -> WmDmaenR { + WmDmaenR::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - FIFO Empty DMA Enable"] + #[inline(always)] + pub fn empty_dmaen(&mut self) -> EmptyDmaenW { + EmptyDmaenW::new(self, 1) + } + #[doc = "Bit 2 - FIFO Watermark DMA Enable"] + #[inline(always)] + pub fn wm_dmaen(&mut self) -> WmDmaenW { + WmDmaenW::new(self, 2) + } +} +#[doc = "DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DerSpec; +impl crate::RegisterSpec for DerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`der::R`](R) reader structure"] +impl crate::Readable for DerSpec {} +#[doc = "`write(|w| ..)` method takes [`der::W`](W) writer structure"] +impl crate::Writable for DerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DER to value 0"] +impl crate::Resettable for DerSpec {} diff --git a/mcxa276-pac/src/dac0/fcr.rs b/mcxa276-pac/src/dac0/fcr.rs new file mode 100644 index 000000000..504eb077e --- /dev/null +++ b/mcxa276-pac/src/dac0/fcr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `FCR` reader"] +pub type R = crate::R; +#[doc = "Register `FCR` writer"] +pub type W = crate::W; +#[doc = "Field `WML` reader - Watermark Level"] +pub type WmlR = crate::FieldReader; +#[doc = "Field `WML` writer - Watermark Level"] +pub type WmlW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Watermark Level"] + #[inline(always)] + pub fn wml(&self) -> WmlR { + WmlR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Watermark Level"] + #[inline(always)] + pub fn wml(&mut self) -> WmlW { + WmlW::new(self, 0) + } +} +#[doc = "DAC FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FcrSpec; +impl crate::RegisterSpec for FcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fcr::R`](R) reader structure"] +impl crate::Readable for FcrSpec {} +#[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] +impl crate::Writable for FcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCR to value 0"] +impl crate::Resettable for FcrSpec {} diff --git a/mcxa276-pac/src/dac0/fpr.rs b/mcxa276-pac/src/dac0/fpr.rs new file mode 100644 index 000000000..0ee0c0cb8 --- /dev/null +++ b/mcxa276-pac/src/dac0/fpr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `FPR` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_RPT` reader - FIFO Read Pointer"] +pub type FifoRptR = crate::FieldReader; +#[doc = "Field `FIFO_WPT` reader - FIFO Write Pointer"] +pub type FifoWptR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - FIFO Read Pointer"] + #[inline(always)] + pub fn fifo_rpt(&self) -> FifoRptR { + FifoRptR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 16:19 - FIFO Write Pointer"] + #[inline(always)] + pub fn fifo_wpt(&self) -> FifoWptR { + FifoWptR::new(((self.bits >> 16) & 0x0f) as u8) + } +} +#[doc = "DAC FIFO Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`fpr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FprSpec; +impl crate::RegisterSpec for FprSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fpr::R`](R) reader structure"] +impl crate::Readable for FprSpec {} +#[doc = "`reset()` method sets FPR to value 0"] +impl crate::Resettable for FprSpec {} diff --git a/mcxa276-pac/src/dac0/fsr.rs b/mcxa276-pac/src/dac0/fsr.rs new file mode 100644 index 000000000..2f88b9375 --- /dev/null +++ b/mcxa276-pac/src/dac0/fsr.rs @@ -0,0 +1,399 @@ +#[doc = "Register `FSR` reader"] +pub type R = crate::R; +#[doc = "Register `FSR` writer"] +pub type W = crate::W; +#[doc = "FIFO Full Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Full { + #[doc = "0: Not full"] + NotFull = 0, + #[doc = "1: Full"] + Full = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FULL` reader - FIFO Full Flag"] +pub type FullR = crate::BitReader; +impl FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Full { + match self.bits { + false => Full::NotFull, + true => Full::Full, + } + } + #[doc = "Not full"] + #[inline(always)] + pub fn is_not_full(&self) -> bool { + *self == Full::NotFull + } + #[doc = "Full"] + #[inline(always)] + pub fn is_full(&self) -> bool { + *self == Full::Full + } +} +#[doc = "FIFO Empty Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Empty { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Empty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EMPTY` reader - FIFO Empty Flag"] +pub type EmptyR = crate::BitReader; +impl EmptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Empty { + match self.bits { + false => Empty::NotEmpty, + true => Empty::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Empty::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Empty::Empty + } +} +#[doc = "FIFO Watermark Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wm { + #[doc = "0: Data in FIFO is more than watermark level"] + MoreThanWlevel = 0, + #[doc = "1: Data in FIFO is less than or equal to watermark level"] + LessThanWlevel = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WM` reader - FIFO Watermark Status Flag"] +pub type WmR = crate::BitReader; +impl WmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wm { + match self.bits { + false => Wm::MoreThanWlevel, + true => Wm::LessThanWlevel, + } + } + #[doc = "Data in FIFO is more than watermark level"] + #[inline(always)] + pub fn is_more_than_wlevel(&self) -> bool { + *self == Wm::MoreThanWlevel + } + #[doc = "Data in FIFO is less than or equal to watermark level"] + #[inline(always)] + pub fn is_less_than_wlevel(&self) -> bool { + *self == Wm::LessThanWlevel + } +} +#[doc = "Swing Back One Cycle Complete Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swbk { + #[doc = "0: No swing back cycle has completed since the last time the flag was cleared"] + NoSwing = 0, + #[doc = "1: At least one swing back cycle has occurred since the last time the flag was cleared"] + SwingBack = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swbk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWBK` reader - Swing Back One Cycle Complete Flag"] +pub type SwbkR = crate::BitReader; +impl SwbkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swbk { + match self.bits { + false => Swbk::NoSwing, + true => Swbk::SwingBack, + } + } + #[doc = "No swing back cycle has completed since the last time the flag was cleared"] + #[inline(always)] + pub fn is_no_swing(&self) -> bool { + *self == Swbk::NoSwing + } + #[doc = "At least one swing back cycle has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn is_swing_back(&self) -> bool { + *self == Swbk::SwingBack + } +} +#[doc = "Field `SWBK` writer - Swing Back One Cycle Complete Flag"] +pub type SwbkW<'a, REG> = crate::BitWriter1C<'a, REG, Swbk>; +impl<'a, REG> SwbkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No swing back cycle has completed since the last time the flag was cleared"] + #[inline(always)] + pub fn no_swing(self) -> &'a mut crate::W { + self.variant(Swbk::NoSwing) + } + #[doc = "At least one swing back cycle has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn swing_back(self) -> &'a mut crate::W { + self.variant(Swbk::SwingBack) + } +} +#[doc = "FIFO Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Of { + #[doc = "0: No overflow has occurred since the last time the flag was cleared"] + NoOverflow = 0, + #[doc = "1: At least one FIFO overflow has occurred since the last time the flag was cleared"] + Overflow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Of) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OF` reader - FIFO Overflow Flag"] +pub type OfR = crate::BitReader; +impl OfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Of { + match self.bits { + false => Of::NoOverflow, + true => Of::Overflow, + } + } + #[doc = "No overflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn is_no_overflow(&self) -> bool { + *self == Of::NoOverflow + } + #[doc = "At least one FIFO overflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn is_overflow(&self) -> bool { + *self == Of::Overflow + } +} +#[doc = "Field `OF` writer - FIFO Overflow Flag"] +pub type OfW<'a, REG> = crate::BitWriter1C<'a, REG, Of>; +impl<'a, REG> OfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn no_overflow(self) -> &'a mut crate::W { + self.variant(Of::NoOverflow) + } + #[doc = "At least one FIFO overflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn overflow(self) -> &'a mut crate::W { + self.variant(Of::Overflow) + } +} +#[doc = "FIFO Underflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Uf { + #[doc = "0: No underflow has occurred since the last time the flag was cleared"] + NoUnderflow = 0, + #[doc = "1: At least one trigger underflow has occurred since the last time the flag was cleared"] + Underflow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Uf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UF` reader - FIFO Underflow Flag"] +pub type UfR = crate::BitReader; +impl UfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Uf { + match self.bits { + false => Uf::NoUnderflow, + true => Uf::Underflow, + } + } + #[doc = "No underflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn is_no_underflow(&self) -> bool { + *self == Uf::NoUnderflow + } + #[doc = "At least one trigger underflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn is_underflow(&self) -> bool { + *self == Uf::Underflow + } +} +#[doc = "Field `UF` writer - FIFO Underflow Flag"] +pub type UfW<'a, REG> = crate::BitWriter1C<'a, REG, Uf>; +impl<'a, REG> UfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No underflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn no_underflow(self) -> &'a mut crate::W { + self.variant(Uf::NoUnderflow) + } + #[doc = "At least one trigger underflow has occurred since the last time the flag was cleared"] + #[inline(always)] + pub fn underflow(self) -> &'a mut crate::W { + self.variant(Uf::Underflow) + } +} +#[doc = "Period Trigger Mode Conversion Complete Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptgcoco { + #[doc = "0: Not completed or not started"] + NotStart = 0, + #[doc = "1: Completed"] + Completed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptgcoco) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTGCOCO` reader - Period Trigger Mode Conversion Complete Flag"] +pub type PtgcocoR = crate::BitReader; +impl PtgcocoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptgcoco { + match self.bits { + false => Ptgcoco::NotStart, + true => Ptgcoco::Completed, + } + } + #[doc = "Not completed or not started"] + #[inline(always)] + pub fn is_not_start(&self) -> bool { + *self == Ptgcoco::NotStart + } + #[doc = "Completed"] + #[inline(always)] + pub fn is_completed(&self) -> bool { + *self == Ptgcoco::Completed + } +} +#[doc = "Field `PTGCOCO` writer - Period Trigger Mode Conversion Complete Flag"] +pub type PtgcocoW<'a, REG> = crate::BitWriter1C<'a, REG, Ptgcoco>; +impl<'a, REG> PtgcocoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not completed or not started"] + #[inline(always)] + pub fn not_start(self) -> &'a mut crate::W { + self.variant(Ptgcoco::NotStart) + } + #[doc = "Completed"] + #[inline(always)] + pub fn completed(self) -> &'a mut crate::W { + self.variant(Ptgcoco::Completed) + } +} +impl R { + #[doc = "Bit 0 - FIFO Full Flag"] + #[inline(always)] + pub fn full(&self) -> FullR { + FullR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIFO Empty Flag"] + #[inline(always)] + pub fn empty(&self) -> EmptyR { + EmptyR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO Watermark Status Flag"] + #[inline(always)] + pub fn wm(&self) -> WmR { + WmR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Swing Back One Cycle Complete Flag"] + #[inline(always)] + pub fn swbk(&self) -> SwbkR { + SwbkR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - FIFO Overflow Flag"] + #[inline(always)] + pub fn of(&self) -> OfR { + OfR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FIFO Underflow Flag"] + #[inline(always)] + pub fn uf(&self) -> UfR { + UfR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Period Trigger Mode Conversion Complete Flag"] + #[inline(always)] + pub fn ptgcoco(&self) -> PtgcocoR { + PtgcocoR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Swing Back One Cycle Complete Flag"] + #[inline(always)] + pub fn swbk(&mut self) -> SwbkW { + SwbkW::new(self, 3) + } + #[doc = "Bit 6 - FIFO Overflow Flag"] + #[inline(always)] + pub fn of(&mut self) -> OfW { + OfW::new(self, 6) + } + #[doc = "Bit 7 - FIFO Underflow Flag"] + #[inline(always)] + pub fn uf(&mut self) -> UfW { + UfW::new(self, 7) + } + #[doc = "Bit 8 - Period Trigger Mode Conversion Complete Flag"] + #[inline(always)] + pub fn ptgcoco(&mut self) -> PtgcocoW { + PtgcocoW::new(self, 8) + } +} +#[doc = "FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FsrSpec; +impl crate::RegisterSpec for FsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fsr::R`](R) reader structure"] +impl crate::Readable for FsrSpec {} +#[doc = "`write(|w| ..)` method takes [`fsr::W`](W) writer structure"] +impl crate::Writable for FsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01c8; +} +#[doc = "`reset()` method sets FSR to value 0x02"] +impl crate::Resettable for FsrSpec { + const RESET_VALUE: u32 = 0x02; +} diff --git a/mcxa276-pac/src/dac0/gcr.rs b/mcxa276-pac/src/dac0/gcr.rs new file mode 100644 index 000000000..0122737b0 --- /dev/null +++ b/mcxa276-pac/src/dac0/gcr.rs @@ -0,0 +1,687 @@ +#[doc = "Register `GCR` reader"] +pub type R = crate::R; +#[doc = "Register `GCR` writer"] +pub type W = crate::W; +#[doc = "DAC Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dacen { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dacen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DACEN` reader - DAC Enable"] +pub type DacenR = crate::BitReader; +impl DacenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dacen { + match self.bits { + false => Dacen::Disabled, + true => Dacen::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dacen::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dacen::Enabled + } +} +#[doc = "Field `DACEN` writer - DAC Enable"] +pub type DacenW<'a, REG> = crate::BitWriter<'a, REG, Dacen>; +impl<'a, REG> DacenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dacen::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dacen::Enabled) + } +} +#[doc = "DAC Reference Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dacrfs { + #[doc = "0: Selects VREFH0 as the reference voltage."] + Vrefh0 = 0, + #[doc = "1: Selects VREFH1 as the reference voltage."] + Vrefh1 = 1, + #[doc = "2: Selects VREFH2 as the reference voltage."] + Vrefh2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dacrfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dacrfs { + type Ux = u8; +} +impl crate::IsEnum for Dacrfs {} +#[doc = "Field `DACRFS` reader - DAC Reference Select"] +pub type DacrfsR = crate::FieldReader; +impl DacrfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dacrfs::Vrefh0), + 1 => Some(Dacrfs::Vrefh1), + 2 => Some(Dacrfs::Vrefh2), + _ => None, + } + } + #[doc = "Selects VREFH0 as the reference voltage."] + #[inline(always)] + pub fn is_vrefh0(&self) -> bool { + *self == Dacrfs::Vrefh0 + } + #[doc = "Selects VREFH1 as the reference voltage."] + #[inline(always)] + pub fn is_vrefh1(&self) -> bool { + *self == Dacrfs::Vrefh1 + } + #[doc = "Selects VREFH2 as the reference voltage."] + #[inline(always)] + pub fn is_vrefh2(&self) -> bool { + *self == Dacrfs::Vrefh2 + } +} +#[doc = "Field `DACRFS` writer - DAC Reference Select"] +pub type DacrfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dacrfs>; +impl<'a, REG> DacrfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects VREFH0 as the reference voltage."] + #[inline(always)] + pub fn vrefh0(self) -> &'a mut crate::W { + self.variant(Dacrfs::Vrefh0) + } + #[doc = "Selects VREFH1 as the reference voltage."] + #[inline(always)] + pub fn vrefh1(self) -> &'a mut crate::W { + self.variant(Dacrfs::Vrefh1) + } + #[doc = "Selects VREFH2 as the reference voltage."] + #[inline(always)] + pub fn vrefh2(self) -> &'a mut crate::W { + self.variant(Dacrfs::Vrefh2) + } +} +#[doc = "FIFO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fifoen { + #[doc = "0: Disables FIFO mode and enables Buffer mode. Any data written to DATA\\[DATA\\] goes to buffer then goes to conversion."] + BufferMode = 0, + #[doc = "1: Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion."] + FifoMode = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fifoen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIFOEN` reader - FIFO Enable"] +pub type FifoenR = crate::BitReader; +impl FifoenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fifoen { + match self.bits { + false => Fifoen::BufferMode, + true => Fifoen::FifoMode, + } + } + #[doc = "Disables FIFO mode and enables Buffer mode. Any data written to DATA\\[DATA\\] goes to buffer then goes to conversion."] + #[inline(always)] + pub fn is_buffer_mode(&self) -> bool { + *self == Fifoen::BufferMode + } + #[doc = "Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion."] + #[inline(always)] + pub fn is_fifo_mode(&self) -> bool { + *self == Fifoen::FifoMode + } +} +#[doc = "Field `FIFOEN` writer - FIFO Enable"] +pub type FifoenW<'a, REG> = crate::BitWriter<'a, REG, Fifoen>; +impl<'a, REG> FifoenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables FIFO mode and enables Buffer mode. Any data written to DATA\\[DATA\\] goes to buffer then goes to conversion."] + #[inline(always)] + pub fn buffer_mode(self) -> &'a mut crate::W { + self.variant(Fifoen::BufferMode) + } + #[doc = "Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion."] + #[inline(always)] + pub fn fifo_mode(self) -> &'a mut crate::W { + self.variant(Fifoen::FifoMode) + } +} +#[doc = "Swing Back Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swmd { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swmd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWMD` reader - Swing Back Mode"] +pub type SwmdR = crate::BitReader; +impl SwmdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swmd { + match self.bits { + false => Swmd::Disable, + true => Swmd::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Swmd::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Swmd::Enable + } +} +#[doc = "Field `SWMD` writer - Swing Back Mode"] +pub type SwmdW<'a, REG> = crate::BitWriter<'a, REG, Swmd>; +impl<'a, REG> SwmdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Swmd::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Swmd::Enable) + } +} +#[doc = "DAC Trigger Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trgsel { + #[doc = "0: Hardware trigger"] + Hardware = 0, + #[doc = "1: Software trigger"] + Software = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trgsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRGSEL` reader - DAC Trigger Select"] +pub type TrgselR = crate::BitReader; +impl TrgselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgsel { + match self.bits { + false => Trgsel::Hardware, + true => Trgsel::Software, + } + } + #[doc = "Hardware trigger"] + #[inline(always)] + pub fn is_hardware(&self) -> bool { + *self == Trgsel::Hardware + } + #[doc = "Software trigger"] + #[inline(always)] + pub fn is_software(&self) -> bool { + *self == Trgsel::Software + } +} +#[doc = "Field `TRGSEL` writer - DAC Trigger Select"] +pub type TrgselW<'a, REG> = crate::BitWriter<'a, REG, Trgsel>; +impl<'a, REG> TrgselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Hardware trigger"] + #[inline(always)] + pub fn hardware(self) -> &'a mut crate::W { + self.variant(Trgsel::Hardware) + } + #[doc = "Software trigger"] + #[inline(always)] + pub fn software(self) -> &'a mut crate::W { + self.variant(Trgsel::Software) + } +} +#[doc = "DAC Periodic Trigger Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptgen { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptgen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTGEN` reader - DAC Periodic Trigger Mode Enable"] +pub type PtgenR = crate::BitReader; +impl PtgenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptgen { + match self.bits { + false => Ptgen::Disabled, + true => Ptgen::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ptgen::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ptgen::Enabled + } +} +#[doc = "Field `PTGEN` writer - DAC Periodic Trigger Mode Enable"] +pub type PtgenW<'a, REG> = crate::BitWriter<'a, REG, Ptgen>; +impl<'a, REG> PtgenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ptgen::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ptgen::Enabled) + } +} +#[doc = "Field `LATCH_CYC` reader - RCLK Cycles Before Data Latch"] +pub type LatchCycR = crate::FieldReader; +#[doc = "Field `LATCH_CYC` writer - RCLK Cycles Before Data Latch"] +pub type LatchCycW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum BufEn { + #[doc = "0: Not used"] + UseBuf = 0, + #[doc = "1: Used"] + NoUseBuf = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BufEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUF_EN` reader - Buffer Enable"] +pub type BufEnR = crate::BitReader; +impl BufEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> BufEn { + match self.bits { + false => BufEn::UseBuf, + true => BufEn::NoUseBuf, + } + } + #[doc = "Not used"] + #[inline(always)] + pub fn is_use_buf(&self) -> bool { + *self == BufEn::UseBuf + } + #[doc = "Used"] + #[inline(always)] + pub fn is_no_use_buf(&self) -> bool { + *self == BufEn::NoUseBuf + } +} +#[doc = "Field `BUF_EN` writer - Buffer Enable"] +pub type BufEnW<'a, REG> = crate::BitWriter<'a, REG, BufEn>; +impl<'a, REG> BufEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not used"] + #[inline(always)] + pub fn use_buf(self) -> &'a mut crate::W { + self.variant(BufEn::UseBuf) + } + #[doc = "Used"] + #[inline(always)] + pub fn no_use_buf(self) -> &'a mut crate::W { + self.variant(BufEn::NoUseBuf) + } +} +#[doc = "External On-Chip PTAT Current Reference Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IrefPtatExtSel { + #[doc = "0: Not selected"] + NotSelected = 0, + #[doc = "1: Selected"] + Selected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IrefPtatExtSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IREF_PTAT_EXT_SEL` reader - External On-Chip PTAT Current Reference Select"] +pub type IrefPtatExtSelR = crate::BitReader; +impl IrefPtatExtSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IrefPtatExtSel { + match self.bits { + false => IrefPtatExtSel::NotSelected, + true => IrefPtatExtSel::Selected, + } + } + #[doc = "Not selected"] + #[inline(always)] + pub fn is_not_selected(&self) -> bool { + *self == IrefPtatExtSel::NotSelected + } + #[doc = "Selected"] + #[inline(always)] + pub fn is_selected(&self) -> bool { + *self == IrefPtatExtSel::Selected + } +} +#[doc = "Field `IREF_PTAT_EXT_SEL` writer - External On-Chip PTAT Current Reference Select"] +pub type IrefPtatExtSelW<'a, REG> = crate::BitWriter<'a, REG, IrefPtatExtSel>; +impl<'a, REG> IrefPtatExtSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not selected"] + #[inline(always)] + pub fn not_selected(self) -> &'a mut crate::W { + self.variant(IrefPtatExtSel::NotSelected) + } + #[doc = "Selected"] + #[inline(always)] + pub fn selected(self) -> &'a mut crate::W { + self.variant(IrefPtatExtSel::Selected) + } +} +#[doc = "External On-Chip ZTC Current Reference Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IrefZtcExtSel { + #[doc = "0: Not selected"] + NotSelected = 0, + #[doc = "1: Selected"] + Selected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IrefZtcExtSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IREF_ZTC_EXT_SEL` reader - External On-Chip ZTC Current Reference Select"] +pub type IrefZtcExtSelR = crate::BitReader; +impl IrefZtcExtSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IrefZtcExtSel { + match self.bits { + false => IrefZtcExtSel::NotSelected, + true => IrefZtcExtSel::Selected, + } + } + #[doc = "Not selected"] + #[inline(always)] + pub fn is_not_selected(&self) -> bool { + *self == IrefZtcExtSel::NotSelected + } + #[doc = "Selected"] + #[inline(always)] + pub fn is_selected(&self) -> bool { + *self == IrefZtcExtSel::Selected + } +} +#[doc = "Field `IREF_ZTC_EXT_SEL` writer - External On-Chip ZTC Current Reference Select"] +pub type IrefZtcExtSelW<'a, REG> = crate::BitWriter<'a, REG, IrefZtcExtSel>; +impl<'a, REG> IrefZtcExtSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not selected"] + #[inline(always)] + pub fn not_selected(self) -> &'a mut crate::W { + self.variant(IrefZtcExtSel::NotSelected) + } + #[doc = "Selected"] + #[inline(always)] + pub fn selected(self) -> &'a mut crate::W { + self.variant(IrefZtcExtSel::Selected) + } +} +#[doc = "OPAMP as Buffer, Speed Control Signal\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum BufSpdCtrl { + #[doc = "0: Lower Low-Power mode"] + LlpMode = 0, + #[doc = "1: Low-Power mode"] + LpMode = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BufSpdCtrl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUF_SPD_CTRL` reader - OPAMP as Buffer, Speed Control Signal"] +pub type BufSpdCtrlR = crate::BitReader; +impl BufSpdCtrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> BufSpdCtrl { + match self.bits { + false => BufSpdCtrl::LlpMode, + true => BufSpdCtrl::LpMode, + } + } + #[doc = "Lower Low-Power mode"] + #[inline(always)] + pub fn is_llp_mode(&self) -> bool { + *self == BufSpdCtrl::LlpMode + } + #[doc = "Low-Power mode"] + #[inline(always)] + pub fn is_lp_mode(&self) -> bool { + *self == BufSpdCtrl::LpMode + } +} +#[doc = "Field `BUF_SPD_CTRL` writer - OPAMP as Buffer, Speed Control Signal"] +pub type BufSpdCtrlW<'a, REG> = crate::BitWriter<'a, REG, BufSpdCtrl>; +impl<'a, REG> BufSpdCtrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Lower Low-Power mode"] + #[inline(always)] + pub fn llp_mode(self) -> &'a mut crate::W { + self.variant(BufSpdCtrl::LlpMode) + } + #[doc = "Low-Power mode"] + #[inline(always)] + pub fn lp_mode(self) -> &'a mut crate::W { + self.variant(BufSpdCtrl::LpMode) + } +} +impl R { + #[doc = "Bit 0 - DAC Enable"] + #[inline(always)] + pub fn dacen(&self) -> DacenR { + DacenR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - DAC Reference Select"] + #[inline(always)] + pub fn dacrfs(&self) -> DacrfsR { + DacrfsR::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - FIFO Enable"] + #[inline(always)] + pub fn fifoen(&self) -> FifoenR { + FifoenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Swing Back Mode"] + #[inline(always)] + pub fn swmd(&self) -> SwmdR { + SwmdR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DAC Trigger Select"] + #[inline(always)] + pub fn trgsel(&self) -> TrgselR { + TrgselR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - DAC Periodic Trigger Mode Enable"] + #[inline(always)] + pub fn ptgen(&self) -> PtgenR { + PtgenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - RCLK Cycles Before Data Latch"] + #[inline(always)] + pub fn latch_cyc(&self) -> LatchCycR { + LatchCycR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 17 - Buffer Enable"] + #[inline(always)] + pub fn buf_en(&self) -> BufEnR { + BufEnR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 20 - External On-Chip PTAT Current Reference Select"] + #[inline(always)] + pub fn iref_ptat_ext_sel(&self) -> IrefPtatExtSelR { + IrefPtatExtSelR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - External On-Chip ZTC Current Reference Select"] + #[inline(always)] + pub fn iref_ztc_ext_sel(&self) -> IrefZtcExtSelR { + IrefZtcExtSelR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - OPAMP as Buffer, Speed Control Signal"] + #[inline(always)] + pub fn buf_spd_ctrl(&self) -> BufSpdCtrlR { + BufSpdCtrlR::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DAC Enable"] + #[inline(always)] + pub fn dacen(&mut self) -> DacenW { + DacenW::new(self, 0) + } + #[doc = "Bits 1:2 - DAC Reference Select"] + #[inline(always)] + pub fn dacrfs(&mut self) -> DacrfsW { + DacrfsW::new(self, 1) + } + #[doc = "Bit 3 - FIFO Enable"] + #[inline(always)] + pub fn fifoen(&mut self) -> FifoenW { + FifoenW::new(self, 3) + } + #[doc = "Bit 4 - Swing Back Mode"] + #[inline(always)] + pub fn swmd(&mut self) -> SwmdW { + SwmdW::new(self, 4) + } + #[doc = "Bit 5 - DAC Trigger Select"] + #[inline(always)] + pub fn trgsel(&mut self) -> TrgselW { + TrgselW::new(self, 5) + } + #[doc = "Bit 6 - DAC Periodic Trigger Mode Enable"] + #[inline(always)] + pub fn ptgen(&mut self) -> PtgenW { + PtgenW::new(self, 6) + } + #[doc = "Bits 8:11 - RCLK Cycles Before Data Latch"] + #[inline(always)] + pub fn latch_cyc(&mut self) -> LatchCycW { + LatchCycW::new(self, 8) + } + #[doc = "Bit 17 - Buffer Enable"] + #[inline(always)] + pub fn buf_en(&mut self) -> BufEnW { + BufEnW::new(self, 17) + } + #[doc = "Bit 20 - External On-Chip PTAT Current Reference Select"] + #[inline(always)] + pub fn iref_ptat_ext_sel(&mut self) -> IrefPtatExtSelW { + IrefPtatExtSelW::new(self, 20) + } + #[doc = "Bit 21 - External On-Chip ZTC Current Reference Select"] + #[inline(always)] + pub fn iref_ztc_ext_sel(&mut self) -> IrefZtcExtSelW { + IrefZtcExtSelW::new(self, 21) + } + #[doc = "Bit 23 - OPAMP as Buffer, Speed Control Signal"] + #[inline(always)] + pub fn buf_spd_ctrl(&mut self) -> BufSpdCtrlW { + BufSpdCtrlW::new(self, 23) + } +} +#[doc = "Global Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GcrSpec; +impl crate::RegisterSpec for GcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gcr::R`](R) reader structure"] +impl crate::Readable for GcrSpec {} +#[doc = "`write(|w| ..)` method takes [`gcr::W`](W) writer structure"] +impl crate::Writable for GcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GCR to value 0x0100"] +impl crate::Resettable for GcrSpec { + const RESET_VALUE: u32 = 0x0100; +} diff --git a/mcxa276-pac/src/dac0/ier.rs b/mcxa276-pac/src/dac0/ier.rs new file mode 100644 index 000000000..ad3c4b72c --- /dev/null +++ b/mcxa276-pac/src/dac0/ier.rs @@ -0,0 +1,462 @@ +#[doc = "Register `IER` reader"] +pub type R = crate::R; +#[doc = "Register `IER` writer"] +pub type W = crate::W; +#[doc = "FIFO Full Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FullIe { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FullIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FULL_IE` reader - FIFO Full Interrupt Enable"] +pub type FullIeR = crate::BitReader; +impl FullIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FullIe { + match self.bits { + false => FullIe::Disabled, + true => FullIe::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == FullIe::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == FullIe::Enabled + } +} +#[doc = "Field `FULL_IE` writer - FIFO Full Interrupt Enable"] +pub type FullIeW<'a, REG> = crate::BitWriter<'a, REG, FullIe>; +impl<'a, REG> FullIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(FullIe::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(FullIe::Enabled) + } +} +#[doc = "FIFO Empty Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EmptyIe { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EmptyIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EMPTY_IE` reader - FIFO Empty Interrupt Enable"] +pub type EmptyIeR = crate::BitReader; +impl EmptyIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EmptyIe { + match self.bits { + false => EmptyIe::Disabled, + true => EmptyIe::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EmptyIe::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EmptyIe::Enabled + } +} +#[doc = "Field `EMPTY_IE` writer - FIFO Empty Interrupt Enable"] +pub type EmptyIeW<'a, REG> = crate::BitWriter<'a, REG, EmptyIe>; +impl<'a, REG> EmptyIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(EmptyIe::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(EmptyIe::Enabled) + } +} +#[doc = "FIFO Watermark Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WmIe { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WmIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WM_IE` reader - FIFO Watermark Interrupt Enable"] +pub type WmIeR = crate::BitReader; +impl WmIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WmIe { + match self.bits { + false => WmIe::Disabled, + true => WmIe::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == WmIe::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == WmIe::Enabled + } +} +#[doc = "Field `WM_IE` writer - FIFO Watermark Interrupt Enable"] +pub type WmIeW<'a, REG> = crate::BitWriter<'a, REG, WmIe>; +impl<'a, REG> WmIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(WmIe::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(WmIe::Enabled) + } +} +#[doc = "Swing Back One Cycle Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SwbkIe { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SwbkIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWBK_IE` reader - Swing Back One Cycle Complete Interrupt Enable"] +pub type SwbkIeR = crate::BitReader; +impl SwbkIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SwbkIe { + match self.bits { + false => SwbkIe::Disabled, + true => SwbkIe::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SwbkIe::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SwbkIe::Enabled + } +} +#[doc = "Field `SWBK_IE` writer - Swing Back One Cycle Complete Interrupt Enable"] +pub type SwbkIeW<'a, REG> = crate::BitWriter<'a, REG, SwbkIe>; +impl<'a, REG> SwbkIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(SwbkIe::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(SwbkIe::Enabled) + } +} +#[doc = "FIFO Overflow Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OfIe { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OfIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OF_IE` reader - FIFO Overflow Interrupt Enable"] +pub type OfIeR = crate::BitReader; +impl OfIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OfIe { + match self.bits { + false => OfIe::Disabled, + true => OfIe::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == OfIe::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == OfIe::Enabled + } +} +#[doc = "Field `OF_IE` writer - FIFO Overflow Interrupt Enable"] +pub type OfIeW<'a, REG> = crate::BitWriter<'a, REG, OfIe>; +impl<'a, REG> OfIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(OfIe::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(OfIe::Enabled) + } +} +#[doc = "FIFO Underflow Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum UfIe { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UfIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UF_IE` reader - FIFO Underflow Interrupt Enable"] +pub type UfIeR = crate::BitReader; +impl UfIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> UfIe { + match self.bits { + false => UfIe::Disabled, + true => UfIe::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == UfIe::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == UfIe::Enabled + } +} +#[doc = "Field `UF_IE` writer - FIFO Underflow Interrupt Enable"] +pub type UfIeW<'a, REG> = crate::BitWriter<'a, REG, UfIe>; +impl<'a, REG> UfIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(UfIe::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(UfIe::Enabled) + } +} +#[doc = "PTG Mode Conversion Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PtgcocoIe { + #[doc = "0: Disables"] + Disabled = 0, + #[doc = "1: Enables"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PtgcocoIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTGCOCO_IE` reader - PTG Mode Conversion Complete Interrupt Enable"] +pub type PtgcocoIeR = crate::BitReader; +impl PtgcocoIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PtgcocoIe { + match self.bits { + false => PtgcocoIe::Disabled, + true => PtgcocoIe::Enabled, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == PtgcocoIe::Disabled + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == PtgcocoIe::Enabled + } +} +#[doc = "Field `PTGCOCO_IE` writer - PTG Mode Conversion Complete Interrupt Enable"] +pub type PtgcocoIeW<'a, REG> = crate::BitWriter<'a, REG, PtgcocoIe>; +impl<'a, REG> PtgcocoIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(PtgcocoIe::Disabled) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(PtgcocoIe::Enabled) + } +} +impl R { + #[doc = "Bit 0 - FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn full_ie(&self) -> FullIeR { + FullIeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn empty_ie(&self) -> EmptyIeR { + EmptyIeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO Watermark Interrupt Enable"] + #[inline(always)] + pub fn wm_ie(&self) -> WmIeR { + WmIeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Swing Back One Cycle Complete Interrupt Enable"] + #[inline(always)] + pub fn swbk_ie(&self) -> SwbkIeR { + SwbkIeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - FIFO Overflow Interrupt Enable"] + #[inline(always)] + pub fn of_ie(&self) -> OfIeR { + OfIeR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FIFO Underflow Interrupt Enable"] + #[inline(always)] + pub fn uf_ie(&self) -> UfIeR { + UfIeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PTG Mode Conversion Complete Interrupt Enable"] + #[inline(always)] + pub fn ptgcoco_ie(&self) -> PtgcocoIeR { + PtgcocoIeR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn full_ie(&mut self) -> FullIeW { + FullIeW::new(self, 0) + } + #[doc = "Bit 1 - FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn empty_ie(&mut self) -> EmptyIeW { + EmptyIeW::new(self, 1) + } + #[doc = "Bit 2 - FIFO Watermark Interrupt Enable"] + #[inline(always)] + pub fn wm_ie(&mut self) -> WmIeW { + WmIeW::new(self, 2) + } + #[doc = "Bit 3 - Swing Back One Cycle Complete Interrupt Enable"] + #[inline(always)] + pub fn swbk_ie(&mut self) -> SwbkIeW { + SwbkIeW::new(self, 3) + } + #[doc = "Bit 6 - FIFO Overflow Interrupt Enable"] + #[inline(always)] + pub fn of_ie(&mut self) -> OfIeW { + OfIeW::new(self, 6) + } + #[doc = "Bit 7 - FIFO Underflow Interrupt Enable"] + #[inline(always)] + pub fn uf_ie(&mut self) -> UfIeW { + UfIeW::new(self, 7) + } + #[doc = "Bit 8 - PTG Mode Conversion Complete Interrupt Enable"] + #[inline(always)] + pub fn ptgcoco_ie(&mut self) -> PtgcocoIeW { + PtgcocoIeW::new(self, 8) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IerSpec; +impl crate::RegisterSpec for IerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IerSpec {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] +impl crate::Writable for IerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/dac0/param.rs b/mcxa276-pac/src/dac0/param.rs new file mode 100644 index 000000000..df3ecd81e --- /dev/null +++ b/mcxa276-pac/src/dac0/param.rs @@ -0,0 +1,102 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "FIFO Size\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fifosz { + #[doc = "1: FIFO depth is 4"] + Val1 = 1, + #[doc = "2: FIFO depth is 8"] + Val2 = 2, + #[doc = "3: FIFO depth is 16"] + Val3 = 3, + #[doc = "4: FIFO depth is 32"] + Val4 = 4, + #[doc = "5: FIFO depth is 64"] + Val5 = 5, + #[doc = "6: FIFO depth is 128"] + Val6 = 6, + #[doc = "7: FIFO depth is 256"] + Val7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fifosz) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fifosz { + type Ux = u8; +} +impl crate::IsEnum for Fifosz {} +#[doc = "Field `FIFOSZ` reader - FIFO Size"] +pub type FifoszR = crate::FieldReader; +impl FifoszR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Fifosz::Val1), + 2 => Some(Fifosz::Val2), + 3 => Some(Fifosz::Val3), + 4 => Some(Fifosz::Val4), + 5 => Some(Fifosz::Val5), + 6 => Some(Fifosz::Val6), + 7 => Some(Fifosz::Val7), + _ => None, + } + } + #[doc = "FIFO depth is 4"] + #[inline(always)] + pub fn is_val_1(&self) -> bool { + *self == Fifosz::Val1 + } + #[doc = "FIFO depth is 8"] + #[inline(always)] + pub fn is_val_2(&self) -> bool { + *self == Fifosz::Val2 + } + #[doc = "FIFO depth is 16"] + #[inline(always)] + pub fn is_val_3(&self) -> bool { + *self == Fifosz::Val3 + } + #[doc = "FIFO depth is 32"] + #[inline(always)] + pub fn is_val_4(&self) -> bool { + *self == Fifosz::Val4 + } + #[doc = "FIFO depth is 64"] + #[inline(always)] + pub fn is_val_5(&self) -> bool { + *self == Fifosz::Val5 + } + #[doc = "FIFO depth is 128"] + #[inline(always)] + pub fn is_val_6(&self) -> bool { + *self == Fifosz::Val6 + } + #[doc = "FIFO depth is 256"] + #[inline(always)] + pub fn is_val_7(&self) -> bool { + *self == Fifosz::Val7 + } +} +impl R { + #[doc = "Bits 0:2 - FIFO Size"] + #[inline(always)] + pub fn fifosz(&self) -> FifoszR { + FifoszR::new((self.bits & 7) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x03"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x03; +} diff --git a/mcxa276-pac/src/dac0/pcr.rs b/mcxa276-pac/src/dac0/pcr.rs new file mode 100644 index 000000000..de8ace6c1 --- /dev/null +++ b/mcxa276-pac/src/dac0/pcr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `PCR` reader"] +pub type R = crate::R; +#[doc = "Register `PCR` writer"] +pub type W = crate::W; +#[doc = "Field `PTG_NUM` reader - Periodic Trigger Number"] +pub type PtgNumR = crate::FieldReader; +#[doc = "Field `PTG_NUM` writer - Periodic Trigger Number"] +pub type PtgNumW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PTG_PERIOD` reader - Periodic Trigger Period Width"] +pub type PtgPeriodR = crate::FieldReader; +#[doc = "Field `PTG_PERIOD` writer - Periodic Trigger Period Width"] +pub type PtgPeriodW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Periodic Trigger Number"] + #[inline(always)] + pub fn ptg_num(&self) -> PtgNumR { + PtgNumR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Periodic Trigger Period Width"] + #[inline(always)] + pub fn ptg_period(&self) -> PtgPeriodR { + PtgPeriodR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Periodic Trigger Number"] + #[inline(always)] + pub fn ptg_num(&mut self) -> PtgNumW { + PtgNumW::new(self, 0) + } + #[doc = "Bits 16:31 - Periodic Trigger Period Width"] + #[inline(always)] + pub fn ptg_period(&mut self) -> PtgPeriodW { + PtgPeriodW::new(self, 16) + } +} +#[doc = "Periodic Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PcrSpec; +impl crate::RegisterSpec for PcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr::R`](R) reader structure"] +impl crate::Readable for PcrSpec {} +#[doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] +impl crate::Writable for PcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR to value 0"] +impl crate::Resettable for PcrSpec {} diff --git a/mcxa276-pac/src/dac0/rcr.rs b/mcxa276-pac/src/dac0/rcr.rs new file mode 100644 index 000000000..3606c34e0 --- /dev/null +++ b/mcxa276-pac/src/dac0/rcr.rs @@ -0,0 +1,147 @@ +#[doc = "Register `RCR` reader"] +pub type R = crate::R; +#[doc = "Register `RCR` writer"] +pub type W = crate::W; +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swrst { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Software reset"] + SoftwareReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swrst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SwrstR = crate::BitReader; +impl SwrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swrst { + match self.bits { + false => Swrst::NoEffect, + true => Swrst::SoftwareReset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Swrst::NoEffect + } + #[doc = "Software reset"] + #[inline(always)] + pub fn is_software_reset(&self) -> bool { + *self == Swrst::SoftwareReset + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG, Swrst>; +impl<'a, REG> SwrstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Swrst::NoEffect) + } + #[doc = "Software reset"] + #[inline(always)] + pub fn software_reset(self) -> &'a mut crate::W { + self.variant(Swrst::SoftwareReset) + } +} +#[doc = "FIFO Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fiforst { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: FIFO reset"] + FifoReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fiforst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIFORST` reader - FIFO Reset"] +pub type FiforstR = crate::BitReader; +impl FiforstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fiforst { + match self.bits { + false => Fiforst::NoEffect, + true => Fiforst::FifoReset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Fiforst::NoEffect + } + #[doc = "FIFO reset"] + #[inline(always)] + pub fn is_fifo_reset(&self) -> bool { + *self == Fiforst::FifoReset + } +} +#[doc = "Field `FIFORST` writer - FIFO Reset"] +pub type FiforstW<'a, REG> = crate::BitWriter<'a, REG, Fiforst>; +impl<'a, REG> FiforstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Fiforst::NoEffect) + } + #[doc = "FIFO reset"] + #[inline(always)] + pub fn fifo_reset(self) -> &'a mut crate::W { + self.variant(Fiforst::FifoReset) + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SwrstR { + SwrstR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIFO Reset"] + #[inline(always)] + pub fn fiforst(&self) -> FiforstR { + FiforstR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SwrstW { + SwrstW::new(self, 0) + } + #[doc = "Bit 1 - FIFO Reset"] + #[inline(always)] + pub fn fiforst(&mut self) -> FiforstW { + FiforstW::new(self, 1) + } +} +#[doc = "Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RcrSpec; +impl crate::RegisterSpec for RcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rcr::R`](R) reader structure"] +impl crate::Readable for RcrSpec {} +#[doc = "`write(|w| ..)` method takes [`rcr::W`](W) writer structure"] +impl crate::Writable for RcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RCR to value 0"] +impl crate::Resettable for RcrSpec {} diff --git a/mcxa276-pac/src/dac0/tcr.rs b/mcxa276-pac/src/dac0/tcr.rs new file mode 100644 index 000000000..45f4f562f --- /dev/null +++ b/mcxa276-pac/src/dac0/tcr.rs @@ -0,0 +1,84 @@ +#[doc = "Register `TCR` reader"] +pub type R = crate::R; +#[doc = "Register `TCR` writer"] +pub type W = crate::W; +#[doc = "Software Trigger\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swtrg { + #[doc = "0: Not valid"] + NotValid = 0, + #[doc = "1: Valid"] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swtrg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWTRG` reader - Software Trigger"] +pub type SwtrgR = crate::BitReader; +impl SwtrgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swtrg { + match self.bits { + false => Swtrg::NotValid, + true => Swtrg::Valid, + } + } + #[doc = "Not valid"] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Swtrg::NotValid + } + #[doc = "Valid"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Swtrg::Valid + } +} +#[doc = "Field `SWTRG` writer - Software Trigger"] +pub type SwtrgW<'a, REG> = crate::BitWriter<'a, REG, Swtrg>; +impl<'a, REG> SwtrgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not valid"] + #[inline(always)] + pub fn not_valid(self) -> &'a mut crate::W { + self.variant(Swtrg::NotValid) + } + #[doc = "Valid"] + #[inline(always)] + pub fn valid(self) -> &'a mut crate::W { + self.variant(Swtrg::Valid) + } +} +impl R { + #[doc = "Bit 0 - Software Trigger"] + #[inline(always)] + pub fn swtrg(&self) -> SwtrgR { + SwtrgR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Trigger"] + #[inline(always)] + pub fn swtrg(&mut self) -> SwtrgW { + SwtrgW::new(self, 0) + } +} +#[doc = "Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcrSpec; +impl crate::RegisterSpec for TcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] +impl crate::Readable for TcrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] +impl crate::Writable for TcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCR to value 0"] +impl crate::Resettable for TcrSpec {} diff --git a/mcxa276-pac/src/dac0/verid.rs b/mcxa276-pac/src/dac0/verid.rs new file mode 100644 index 000000000..8399c41cc --- /dev/null +++ b/mcxa276-pac/src/dac0/verid.rs @@ -0,0 +1,36 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Field `FEATURE` reader - Feature Identification Number"] +pub type FeatureR = crate::FieldReader; +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Identification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0100_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0100_0000; +} diff --git a/mcxa276-pac/src/dbgmailbox.rs b/mcxa276-pac/src/dbgmailbox.rs new file mode 100644 index 000000000..c3ac277be --- /dev/null +++ b/mcxa276-pac/src/dbgmailbox.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + csw: Csw, + request: Request, + return_: Return, + _reserved3: [u8; 0xf0], + id: Id, +} +impl RegisterBlock { + #[doc = "0x00 - Command and Status Word"] + #[inline(always)] + pub const fn csw(&self) -> &Csw { + &self.csw + } + #[doc = "0x04 - Request Value"] + #[inline(always)] + pub const fn request(&self) -> &Request { + &self.request + } + #[doc = "0x08 - Return Value"] + #[inline(always)] + pub const fn return_(&self) -> &Return { + &self.return_ + } + #[doc = "0xfc - Identification"] + #[inline(always)] + pub const fn id(&self) -> &Id { + &self.id + } +} +#[doc = "CSW (rw) register accessor: Command and Status Word\n\nYou can [`read`](crate::Reg::read) this register and get [`csw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csw`] module"] +#[doc(alias = "CSW")] +pub type Csw = crate::Reg; +#[doc = "Command and Status Word"] +pub mod csw; +#[doc = "REQUEST (rw) register accessor: Request Value\n\nYou can [`read`](crate::Reg::read) this register and get [`request::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`request::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@request`] module"] +#[doc(alias = "REQUEST")] +pub type Request = crate::Reg; +#[doc = "Request Value"] +pub mod request; +#[doc = "RETURN (rw) register accessor: Return Value\n\nYou can [`read`](crate::Reg::read) this register and get [`return_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`return_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@return_`] module"] +#[doc(alias = "RETURN")] +pub type Return = crate::Reg; +#[doc = "Return Value"] +pub mod return_; +#[doc = "ID (r) register accessor: Identification\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`] module"] +#[doc(alias = "ID")] +pub type Id = crate::Reg; +#[doc = "Identification"] +pub mod id; diff --git a/mcxa276-pac/src/dbgmailbox/csw.rs b/mcxa276-pac/src/dbgmailbox/csw.rs new file mode 100644 index 000000000..e29511de4 --- /dev/null +++ b/mcxa276-pac/src/dbgmailbox/csw.rs @@ -0,0 +1,399 @@ +#[doc = "Register `CSW` reader"] +pub type R = crate::R; +#[doc = "Register `CSW` writer"] +pub type W = crate::W; +#[doc = "Resynchronization Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ResynchReq { + #[doc = "0: No request"] + NoRequest = 0, + #[doc = "1: Request for resynchronization"] + Request = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ResynchReq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESYNCH_REQ` reader - Resynchronization Request"] +pub type ResynchReqR = crate::BitReader; +impl ResynchReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ResynchReq { + match self.bits { + false => ResynchReq::NoRequest, + true => ResynchReq::Request, + } + } + #[doc = "No request"] + #[inline(always)] + pub fn is_no_request(&self) -> bool { + *self == ResynchReq::NoRequest + } + #[doc = "Request for resynchronization"] + #[inline(always)] + pub fn is_request(&self) -> bool { + *self == ResynchReq::Request + } +} +#[doc = "Field `RESYNCH_REQ` writer - Resynchronization Request"] +pub type ResynchReqW<'a, REG> = crate::BitWriter<'a, REG, ResynchReq>; +impl<'a, REG> ResynchReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No request"] + #[inline(always)] + pub fn no_request(self) -> &'a mut crate::W { + self.variant(ResynchReq::NoRequest) + } + #[doc = "Request for resynchronization"] + #[inline(always)] + pub fn request(self) -> &'a mut crate::W { + self.variant(ResynchReq::Request) + } +} +#[doc = "Request Pending\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ReqPending { + #[doc = "0: No request pending"] + NoRequestPending = 0, + #[doc = "1: Request for resynchronization pending"] + RequestPending = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ReqPending) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REQ_PENDING` reader - Request Pending"] +pub type ReqPendingR = crate::BitReader; +impl ReqPendingR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ReqPending { + match self.bits { + false => ReqPending::NoRequestPending, + true => ReqPending::RequestPending, + } + } + #[doc = "No request pending"] + #[inline(always)] + pub fn is_no_request_pending(&self) -> bool { + *self == ReqPending::NoRequestPending + } + #[doc = "Request for resynchronization pending"] + #[inline(always)] + pub fn is_request_pending(&self) -> bool { + *self == ReqPending::RequestPending + } +} +#[doc = "Field `REQ_PENDING` writer - Request Pending"] +pub type ReqPendingW<'a, REG> = crate::BitWriter<'a, REG, ReqPending>; +impl<'a, REG> ReqPendingW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No request pending"] + #[inline(always)] + pub fn no_request_pending(self) -> &'a mut crate::W { + self.variant(ReqPending::NoRequestPending) + } + #[doc = "Request for resynchronization pending"] + #[inline(always)] + pub fn request_pending(self) -> &'a mut crate::W { + self.variant(ReqPending::RequestPending) + } +} +#[doc = "DBGMB Overrun Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DbgOrErr { + #[doc = "0: No overrun"] + NoOverrunErr = 0, + #[doc = "1: Overrun occurred"] + OverrunErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DbgOrErr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBG_OR_ERR` reader - DBGMB Overrun Error"] +pub type DbgOrErrR = crate::BitReader; +impl DbgOrErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DbgOrErr { + match self.bits { + false => DbgOrErr::NoOverrunErr, + true => DbgOrErr::OverrunErr, + } + } + #[doc = "No overrun"] + #[inline(always)] + pub fn is_no_overrun_err(&self) -> bool { + *self == DbgOrErr::NoOverrunErr + } + #[doc = "Overrun occurred"] + #[inline(always)] + pub fn is_overrun_err(&self) -> bool { + *self == DbgOrErr::OverrunErr + } +} +#[doc = "Field `DBG_OR_ERR` writer - DBGMB Overrun Error"] +pub type DbgOrErrW<'a, REG> = crate::BitWriter<'a, REG, DbgOrErr>; +impl<'a, REG> DbgOrErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overrun"] + #[inline(always)] + pub fn no_overrun_err(self) -> &'a mut crate::W { + self.variant(DbgOrErr::NoOverrunErr) + } + #[doc = "Overrun occurred"] + #[inline(always)] + pub fn overrun_err(self) -> &'a mut crate::W { + self.variant(DbgOrErr::OverrunErr) + } +} +#[doc = "AHB Overrun Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum AhbOrErr { + #[doc = "0: No overrun"] + NoAhbOverrunErr = 0, + #[doc = "1: Overrun occurred"] + AhbOverrunErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: AhbOrErr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AHB_OR_ERR` reader - AHB Overrun Error"] +pub type AhbOrErrR = crate::BitReader; +impl AhbOrErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> AhbOrErr { + match self.bits { + false => AhbOrErr::NoAhbOverrunErr, + true => AhbOrErr::AhbOverrunErr, + } + } + #[doc = "No overrun"] + #[inline(always)] + pub fn is_no_ahb_overrun_err(&self) -> bool { + *self == AhbOrErr::NoAhbOverrunErr + } + #[doc = "Overrun occurred"] + #[inline(always)] + pub fn is_ahb_overrun_err(&self) -> bool { + *self == AhbOrErr::AhbOverrunErr + } +} +#[doc = "Field `AHB_OR_ERR` writer - AHB Overrun Error"] +pub type AhbOrErrW<'a, REG> = crate::BitWriter<'a, REG, AhbOrErr>; +impl<'a, REG> AhbOrErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overrun"] + #[inline(always)] + pub fn no_ahb_overrun_err(self) -> &'a mut crate::W { + self.variant(AhbOrErr::NoAhbOverrunErr) + } + #[doc = "Overrun occurred"] + #[inline(always)] + pub fn ahb_overrun_err(self) -> &'a mut crate::W { + self.variant(AhbOrErr::AhbOverrunErr) + } +} +#[doc = "Soft Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SoftReset { + #[doc = "0: No effect"] + NoEff = 0, + #[doc = "1: Reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SoftReset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOFT_RESET` reader - Soft Reset"] +pub type SoftResetR = crate::BitReader; +impl SoftResetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SoftReset { + match self.bits { + false => SoftReset::NoEff, + true => SoftReset::Reset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_eff(&self) -> bool { + *self == SoftReset::NoEff + } + #[doc = "Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == SoftReset::Reset + } +} +#[doc = "Field `SOFT_RESET` writer - Soft Reset"] +pub type SoftResetW<'a, REG> = crate::BitWriter<'a, REG, SoftReset>; +impl<'a, REG> SoftResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_eff(self) -> &'a mut crate::W { + self.variant(SoftReset::NoEff) + } + #[doc = "Reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(SoftReset::Reset) + } +} +#[doc = "Chip Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ChipResetReq { + #[doc = "0: No effect"] + NoEff = 0, + #[doc = "1: Reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ChipResetReq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CHIP_RESET_REQ` reader - Chip Reset Request"] +pub type ChipResetReqR = crate::BitReader; +impl ChipResetReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ChipResetReq { + match self.bits { + false => ChipResetReq::NoEff, + true => ChipResetReq::Reset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_eff(&self) -> bool { + *self == ChipResetReq::NoEff + } + #[doc = "Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == ChipResetReq::Reset + } +} +#[doc = "Field `CHIP_RESET_REQ` writer - Chip Reset Request"] +pub type ChipResetReqW<'a, REG> = crate::BitWriter<'a, REG, ChipResetReq>; +impl<'a, REG> ChipResetReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_eff(self) -> &'a mut crate::W { + self.variant(ChipResetReq::NoEff) + } + #[doc = "Reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(ChipResetReq::Reset) + } +} +impl R { + #[doc = "Bit 0 - Resynchronization Request"] + #[inline(always)] + pub fn resynch_req(&self) -> ResynchReqR { + ResynchReqR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Request Pending"] + #[inline(always)] + pub fn req_pending(&self) -> ReqPendingR { + ReqPendingR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DBGMB Overrun Error"] + #[inline(always)] + pub fn dbg_or_err(&self) -> DbgOrErrR { + DbgOrErrR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - AHB Overrun Error"] + #[inline(always)] + pub fn ahb_or_err(&self) -> AhbOrErrR { + AhbOrErrR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Soft Reset"] + #[inline(always)] + pub fn soft_reset(&self) -> SoftResetR { + SoftResetR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Chip Reset Request"] + #[inline(always)] + pub fn chip_reset_req(&self) -> ChipResetReqR { + ChipResetReqR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Resynchronization Request"] + #[inline(always)] + pub fn resynch_req(&mut self) -> ResynchReqW { + ResynchReqW::new(self, 0) + } + #[doc = "Bit 1 - Request Pending"] + #[inline(always)] + pub fn req_pending(&mut self) -> ReqPendingW { + ReqPendingW::new(self, 1) + } + #[doc = "Bit 2 - DBGMB Overrun Error"] + #[inline(always)] + pub fn dbg_or_err(&mut self) -> DbgOrErrW { + DbgOrErrW::new(self, 2) + } + #[doc = "Bit 3 - AHB Overrun Error"] + #[inline(always)] + pub fn ahb_or_err(&mut self) -> AhbOrErrW { + AhbOrErrW::new(self, 3) + } + #[doc = "Bit 4 - Soft Reset"] + #[inline(always)] + pub fn soft_reset(&mut self) -> SoftResetW { + SoftResetW::new(self, 4) + } + #[doc = "Bit 5 - Chip Reset Request"] + #[inline(always)] + pub fn chip_reset_req(&mut self) -> ChipResetReqW { + ChipResetReqW::new(self, 5) + } +} +#[doc = "Command and Status Word\n\nYou can [`read`](crate::Reg::read) this register and get [`csw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CswSpec; +impl crate::RegisterSpec for CswSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`csw::R`](R) reader structure"] +impl crate::Readable for CswSpec {} +#[doc = "`write(|w| ..)` method takes [`csw::W`](W) writer structure"] +impl crate::Writable for CswSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CSW to value 0"] +impl crate::Resettable for CswSpec {} diff --git a/mcxa276-pac/src/dbgmailbox/id.rs b/mcxa276-pac/src/dbgmailbox/id.rs new file mode 100644 index 000000000..302e7ac82 --- /dev/null +++ b/mcxa276-pac/src/dbgmailbox/id.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ID` reader"] +pub type R = crate::R; +#[doc = "Field `ID` reader - Identification Value"] +pub type IdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Identification Value"] + #[inline(always)] + pub fn id(&self) -> IdR { + IdR::new(self.bits) + } +} +#[doc = "Identification\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IdSpec; +impl crate::RegisterSpec for IdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id::R`](R) reader structure"] +impl crate::Readable for IdSpec {} +#[doc = "`reset()` method sets ID to value 0x002a_0000"] +impl crate::Resettable for IdSpec { + const RESET_VALUE: u32 = 0x002a_0000; +} diff --git a/mcxa276-pac/src/dbgmailbox/request.rs b/mcxa276-pac/src/dbgmailbox/request.rs new file mode 100644 index 000000000..9b19c2b26 --- /dev/null +++ b/mcxa276-pac/src/dbgmailbox/request.rs @@ -0,0 +1,35 @@ +#[doc = "Register `REQUEST` reader"] +pub type R = crate::R; +#[doc = "Register `REQUEST` writer"] +pub type W = crate::W; +#[doc = "Field `REQUEST` reader - Request Value"] +pub type RequestR = crate::FieldReader; +#[doc = "Field `REQUEST` writer - Request Value"] +pub type RequestW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Request Value"] + #[inline(always)] + pub fn request(&self) -> RequestR { + RequestR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Request Value"] + #[inline(always)] + pub fn request(&mut self) -> RequestW { + RequestW::new(self, 0) + } +} +#[doc = "Request Value\n\nYou can [`read`](crate::Reg::read) this register and get [`request::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`request::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RequestSpec; +impl crate::RegisterSpec for RequestSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`request::R`](R) reader structure"] +impl crate::Readable for RequestSpec {} +#[doc = "`write(|w| ..)` method takes [`request::W`](W) writer structure"] +impl crate::Writable for RequestSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets REQUEST to value 0"] +impl crate::Resettable for RequestSpec {} diff --git a/mcxa276-pac/src/dbgmailbox/return_.rs b/mcxa276-pac/src/dbgmailbox/return_.rs new file mode 100644 index 000000000..4e9817191 --- /dev/null +++ b/mcxa276-pac/src/dbgmailbox/return_.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RETURN` reader"] +pub type R = crate::R; +#[doc = "Register `RETURN` writer"] +pub type W = crate::W; +#[doc = "Field `RET` reader - Return Value"] +pub type RetR = crate::FieldReader; +#[doc = "Field `RET` writer - Return Value"] +pub type RetW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Return Value"] + #[inline(always)] + pub fn ret(&self) -> RetR { + RetR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Return Value"] + #[inline(always)] + pub fn ret(&mut self) -> RetW { + RetW::new(self, 0) + } +} +#[doc = "Return Value\n\nYou can [`read`](crate::Reg::read) this register and get [`return_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`return_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ReturnSpec; +impl crate::RegisterSpec for ReturnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`return_::R`](R) reader structure"] +impl crate::Readable for ReturnSpec {} +#[doc = "`write(|w| ..)` method takes [`return_::W`](W) writer structure"] +impl crate::Writable for ReturnSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RETURN to value 0"] +impl crate::Resettable for ReturnSpec {} diff --git a/mcxa276-pac/src/dma0.rs b/mcxa276-pac/src/dma0.rs new file mode 100644 index 000000000..c28e9155d --- /dev/null +++ b/mcxa276-pac/src/dma0.rs @@ -0,0 +1,68 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mp_csr: MpCsr, + mp_es: MpEs, + mp_int: MpInt, + mp_hrs: MpHrs, + _reserved4: [u8; 0xf0], + ch_grpri: [ChGrpri; 8], +} +impl RegisterBlock { + #[doc = "0x00 - Management Page Control"] + #[inline(always)] + pub const fn mp_csr(&self) -> &MpCsr { + &self.mp_csr + } + #[doc = "0x04 - Management Page Error Status"] + #[inline(always)] + pub const fn mp_es(&self) -> &MpEs { + &self.mp_es + } + #[doc = "0x08 - Management Page Interrupt Request Status"] + #[inline(always)] + pub const fn mp_int(&self) -> &MpInt { + &self.mp_int + } + #[doc = "0x0c - Management Page Hardware Request Status"] + #[inline(always)] + pub const fn mp_hrs(&self) -> &MpHrs { + &self.mp_hrs + } + #[doc = "0x100..0x120 - Channel Arbitration Group"] + #[inline(always)] + pub const fn ch_grpri(&self, n: usize) -> &ChGrpri { + &self.ch_grpri[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x100..0x120 - Channel Arbitration Group"] + #[inline(always)] + pub fn ch_grpri_iter(&self) -> impl Iterator { + self.ch_grpri.iter() + } +} +#[doc = "MP_CSR (rw) register accessor: Management Page Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mp_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_csr`] module"] +#[doc(alias = "MP_CSR")] +pub type MpCsr = crate::Reg; +#[doc = "Management Page Control"] +pub mod mp_csr; +#[doc = "MP_ES (r) register accessor: Management Page Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_es::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_es`] module"] +#[doc(alias = "MP_ES")] +pub type MpEs = crate::Reg; +#[doc = "Management Page Error Status"] +pub mod mp_es; +#[doc = "MP_INT (r) register accessor: Management Page Interrupt Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_int::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_int`] module"] +#[doc(alias = "MP_INT")] +pub type MpInt = crate::Reg; +#[doc = "Management Page Interrupt Request Status"] +pub mod mp_int; +#[doc = "MP_HRS (r) register accessor: Management Page Hardware Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_hrs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_hrs`] module"] +#[doc(alias = "MP_HRS")] +pub type MpHrs = crate::Reg; +#[doc = "Management Page Hardware Request Status"] +pub mod mp_hrs; +#[doc = "CH_GRPRI (rw) register accessor: Channel Arbitration Group\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_grpri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_grpri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_grpri`] module"] +#[doc(alias = "CH_GRPRI")] +pub type ChGrpri = crate::Reg; +#[doc = "Channel Arbitration Group"] +pub mod ch_grpri; diff --git a/mcxa276-pac/src/dma0/ch_grpri.rs b/mcxa276-pac/src/dma0/ch_grpri.rs new file mode 100644 index 000000000..910ba4f1a --- /dev/null +++ b/mcxa276-pac/src/dma0/ch_grpri.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CH_GRPRI[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `CH_GRPRI[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `GRPRI` reader - Arbitration Group For Channel n"] +pub type GrpriR = crate::FieldReader; +#[doc = "Field `GRPRI` writer - Arbitration Group For Channel n"] +pub type GrpriW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Arbitration Group For Channel n"] + #[inline(always)] + pub fn grpri(&self) -> GrpriR { + GrpriR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Arbitration Group For Channel n"] + #[inline(always)] + pub fn grpri(&mut self) -> GrpriW { + GrpriW::new(self, 0) + } +} +#[doc = "Channel Arbitration Group\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_grpri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_grpri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChGrpriSpec; +impl crate::RegisterSpec for ChGrpriSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_grpri::R`](R) reader structure"] +impl crate::Readable for ChGrpriSpec {} +#[doc = "`write(|w| ..)` method takes [`ch_grpri::W`](W) writer structure"] +impl crate::Writable for ChGrpriSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CH_GRPRI[%s] to value 0"] +impl crate::Resettable for ChGrpriSpec {} diff --git a/mcxa276-pac/src/dma0/mp_csr.rs b/mcxa276-pac/src/dma0/mp_csr.rs new file mode 100644 index 000000000..fb7aab24f --- /dev/null +++ b/mcxa276-pac/src/dma0/mp_csr.rs @@ -0,0 +1,575 @@ +#[doc = "Register `MP_CSR` reader"] +pub type R = crate::R; +#[doc = "Register `MP_CSR` writer"] +pub type W = crate::W; +#[doc = "Enable Debug\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Edbg { + #[doc = "0: Debug mode disabled"] + Disable = 0, + #[doc = "1: Debug mode is enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Edbg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EDBG` reader - Enable Debug"] +pub type EdbgR = crate::BitReader; +impl EdbgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edbg { + match self.bits { + false => Edbg::Disable, + true => Edbg::Enable, + } + } + #[doc = "Debug mode disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Edbg::Disable + } + #[doc = "Debug mode is enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Edbg::Enable + } +} +#[doc = "Field `EDBG` writer - Enable Debug"] +pub type EdbgW<'a, REG> = crate::BitWriter<'a, REG, Edbg>; +impl<'a, REG> EdbgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Debug mode disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Edbg::Disable) + } + #[doc = "Debug mode is enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Edbg::Enable) + } +} +#[doc = "Enable Round Robin Channel Arbitration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erca { + #[doc = "0: Round-robin channel arbitration disabled"] + Disable = 0, + #[doc = "1: Round-robin channel arbitration enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erca) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERCA` reader - Enable Round Robin Channel Arbitration"] +pub type ErcaR = crate::BitReader; +impl ErcaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erca { + match self.bits { + false => Erca::Disable, + true => Erca::Enable, + } + } + #[doc = "Round-robin channel arbitration disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Erca::Disable + } + #[doc = "Round-robin channel arbitration enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Erca::Enable + } +} +#[doc = "Field `ERCA` writer - Enable Round Robin Channel Arbitration"] +pub type ErcaW<'a, REG> = crate::BitWriter<'a, REG, Erca>; +impl<'a, REG> ErcaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Round-robin channel arbitration disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Erca::Disable) + } + #[doc = "Round-robin channel arbitration enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Erca::Enable) + } +} +#[doc = "Halt After Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hae { + #[doc = "0: Normal operation"] + NormalOperation = 0, + #[doc = "1: Any error causes the HALT field to be set to 1"] + Halt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HAE` reader - Halt After Error"] +pub type HaeR = crate::BitReader; +impl HaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hae { + match self.bits { + false => Hae::NormalOperation, + true => Hae::Halt, + } + } + #[doc = "Normal operation"] + #[inline(always)] + pub fn is_normal_operation(&self) -> bool { + *self == Hae::NormalOperation + } + #[doc = "Any error causes the HALT field to be set to 1"] + #[inline(always)] + pub fn is_halt(&self) -> bool { + *self == Hae::Halt + } +} +#[doc = "Field `HAE` writer - Halt After Error"] +pub type HaeW<'a, REG> = crate::BitWriter<'a, REG, Hae>; +impl<'a, REG> HaeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal operation"] + #[inline(always)] + pub fn normal_operation(self) -> &'a mut crate::W { + self.variant(Hae::NormalOperation) + } + #[doc = "Any error causes the HALT field to be set to 1"] + #[inline(always)] + pub fn halt(self) -> &'a mut crate::W { + self.variant(Hae::Halt) + } +} +#[doc = "Halt DMA Operations\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Normal operation"] + NormalOperation = 0, + #[doc = "1: Stall the start of any new channels"] + Stall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt DMA Operations"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::NormalOperation, + true => Halt::Stall, + } + } + #[doc = "Normal operation"] + #[inline(always)] + pub fn is_normal_operation(&self) -> bool { + *self == Halt::NormalOperation + } + #[doc = "Stall the start of any new channels"] + #[inline(always)] + pub fn is_stall(&self) -> bool { + *self == Halt::Stall + } +} +#[doc = "Field `HALT` writer - Halt DMA Operations"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal operation"] + #[inline(always)] + pub fn normal_operation(self) -> &'a mut crate::W { + self.variant(Halt::NormalOperation) + } + #[doc = "Stall the start of any new channels"] + #[inline(always)] + pub fn stall(self) -> &'a mut crate::W { + self.variant(Halt::Stall) + } +} +#[doc = "Global Channel Linking Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gclc { + #[doc = "0: Channel linking disabled for all channels"] + Disable = 0, + #[doc = "1: Channel linking available and controlled by each channel's link settings"] + Available = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gclc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GCLC` reader - Global Channel Linking Control"] +pub type GclcR = crate::BitReader; +impl GclcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gclc { + match self.bits { + false => Gclc::Disable, + true => Gclc::Available, + } + } + #[doc = "Channel linking disabled for all channels"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Gclc::Disable + } + #[doc = "Channel linking available and controlled by each channel's link settings"] + #[inline(always)] + pub fn is_available(&self) -> bool { + *self == Gclc::Available + } +} +#[doc = "Field `GCLC` writer - Global Channel Linking Control"] +pub type GclcW<'a, REG> = crate::BitWriter<'a, REG, Gclc>; +impl<'a, REG> GclcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel linking disabled for all channels"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Gclc::Disable) + } + #[doc = "Channel linking available and controlled by each channel's link settings"] + #[inline(always)] + pub fn available(self) -> &'a mut crate::W { + self.variant(Gclc::Available) + } +} +#[doc = "Global Master ID Replication Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gmrc { + #[doc = "0: Master ID replication disabled for all channels"] + Disable = 0, + #[doc = "1: Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"] + Available = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gmrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GMRC` reader - Global Master ID Replication Control"] +pub type GmrcR = crate::BitReader; +impl GmrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gmrc { + match self.bits { + false => Gmrc::Disable, + true => Gmrc::Available, + } + } + #[doc = "Master ID replication disabled for all channels"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Gmrc::Disable + } + #[doc = "Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"] + #[inline(always)] + pub fn is_available(&self) -> bool { + *self == Gmrc::Available + } +} +#[doc = "Field `GMRC` writer - Global Master ID Replication Control"] +pub type GmrcW<'a, REG> = crate::BitWriter<'a, REG, Gmrc>; +impl<'a, REG> GmrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Master ID replication disabled for all channels"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Gmrc::Disable) + } + #[doc = "Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"] + #[inline(always)] + pub fn available(self) -> &'a mut crate::W { + self.variant(Gmrc::Available) + } +} +#[doc = "Cancel Transfer With Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ecx { + #[doc = "0: Normal operation"] + NormalOperation = 0, + #[doc = "1: Cancel the remaining data transfer"] + Cancel = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ecx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ECX` reader - Cancel Transfer With Error"] +pub type EcxR = crate::BitReader; +impl EcxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ecx { + match self.bits { + false => Ecx::NormalOperation, + true => Ecx::Cancel, + } + } + #[doc = "Normal operation"] + #[inline(always)] + pub fn is_normal_operation(&self) -> bool { + *self == Ecx::NormalOperation + } + #[doc = "Cancel the remaining data transfer"] + #[inline(always)] + pub fn is_cancel(&self) -> bool { + *self == Ecx::Cancel + } +} +#[doc = "Field `ECX` writer - Cancel Transfer With Error"] +pub type EcxW<'a, REG> = crate::BitWriter<'a, REG, Ecx>; +impl<'a, REG> EcxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal operation"] + #[inline(always)] + pub fn normal_operation(self) -> &'a mut crate::W { + self.variant(Ecx::NormalOperation) + } + #[doc = "Cancel the remaining data transfer"] + #[inline(always)] + pub fn cancel(self) -> &'a mut crate::W { + self.variant(Ecx::Cancel) + } +} +#[doc = "Cancel Transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx { + #[doc = "0: Normal operation"] + NormalOperation = 0, + #[doc = "1: Cancel the remaining data transfer"] + DataTransferCancel = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX` reader - Cancel Transfer"] +pub type CxR = crate::BitReader; +impl CxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx { + match self.bits { + false => Cx::NormalOperation, + true => Cx::DataTransferCancel, + } + } + #[doc = "Normal operation"] + #[inline(always)] + pub fn is_normal_operation(&self) -> bool { + *self == Cx::NormalOperation + } + #[doc = "Cancel the remaining data transfer"] + #[inline(always)] + pub fn is_data_transfer_cancel(&self) -> bool { + *self == Cx::DataTransferCancel + } +} +#[doc = "Field `CX` writer - Cancel Transfer"] +pub type CxW<'a, REG> = crate::BitWriter<'a, REG, Cx>; +impl<'a, REG> CxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal operation"] + #[inline(always)] + pub fn normal_operation(self) -> &'a mut crate::W { + self.variant(Cx::NormalOperation) + } + #[doc = "Cancel the remaining data transfer"] + #[inline(always)] + pub fn data_transfer_cancel(self) -> &'a mut crate::W { + self.variant(Cx::DataTransferCancel) + } +} +#[doc = "Field `ACTIVE_ID` reader - Active Channel ID"] +pub type ActiveIdR = crate::FieldReader; +#[doc = "DMA Active Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Active { + #[doc = "0: eDMA is idle"] + Idle = 0, + #[doc = "1: eDMA is executing a channel"] + Execution = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Active) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACTIVE` reader - DMA Active Status"] +pub type ActiveR = crate::BitReader; +impl ActiveR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Active { + match self.bits { + false => Active::Idle, + true => Active::Execution, + } + } + #[doc = "eDMA is idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Active::Idle + } + #[doc = "eDMA is executing a channel"] + #[inline(always)] + pub fn is_execution(&self) -> bool { + *self == Active::Execution + } +} +impl R { + #[doc = "Bit 1 - Enable Debug"] + #[inline(always)] + pub fn edbg(&self) -> EdbgR { + EdbgR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"] + #[inline(always)] + pub fn erca(&self) -> ErcaR { + ErcaR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Halt After Error"] + #[inline(always)] + pub fn hae(&self) -> HaeR { + HaeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Halt DMA Operations"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global Channel Linking Control"] + #[inline(always)] + pub fn gclc(&self) -> GclcR { + GclcR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global Master ID Replication Control"] + #[inline(always)] + pub fn gmrc(&self) -> GmrcR { + GmrcR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Cancel Transfer With Error"] + #[inline(always)] + pub fn ecx(&self) -> EcxR { + EcxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Cancel Transfer"] + #[inline(always)] + pub fn cx(&self) -> CxR { + CxR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 24:26 - Active Channel ID"] + #[inline(always)] + pub fn active_id(&self) -> ActiveIdR { + ActiveIdR::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 31 - DMA Active Status"] + #[inline(always)] + pub fn active(&self) -> ActiveR { + ActiveR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable Debug"] + #[inline(always)] + pub fn edbg(&mut self) -> EdbgW { + EdbgW::new(self, 1) + } + #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"] + #[inline(always)] + pub fn erca(&mut self) -> ErcaW { + ErcaW::new(self, 2) + } + #[doc = "Bit 4 - Halt After Error"] + #[inline(always)] + pub fn hae(&mut self) -> HaeW { + HaeW::new(self, 4) + } + #[doc = "Bit 5 - Halt DMA Operations"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 5) + } + #[doc = "Bit 6 - Global Channel Linking Control"] + #[inline(always)] + pub fn gclc(&mut self) -> GclcW { + GclcW::new(self, 6) + } + #[doc = "Bit 7 - Global Master ID Replication Control"] + #[inline(always)] + pub fn gmrc(&mut self) -> GmrcW { + GmrcW::new(self, 7) + } + #[doc = "Bit 8 - Cancel Transfer With Error"] + #[inline(always)] + pub fn ecx(&mut self) -> EcxW { + EcxW::new(self, 8) + } + #[doc = "Bit 9 - Cancel Transfer"] + #[inline(always)] + pub fn cx(&mut self) -> CxW { + CxW::new(self, 9) + } +} +#[doc = "Management Page Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mp_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MpCsrSpec; +impl crate::RegisterSpec for MpCsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mp_csr::R`](R) reader structure"] +impl crate::Readable for MpCsrSpec {} +#[doc = "`write(|w| ..)` method takes [`mp_csr::W`](W) writer structure"] +impl crate::Writable for MpCsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MP_CSR to value 0x0031_0000"] +impl crate::Resettable for MpCsrSpec { + const RESET_VALUE: u32 = 0x0031_0000; +} diff --git a/mcxa276-pac/src/dma0/mp_es.rs b/mcxa276-pac/src/dma0/mp_es.rs new file mode 100644 index 000000000..60cba71dd --- /dev/null +++ b/mcxa276-pac/src/dma0/mp_es.rs @@ -0,0 +1,430 @@ +#[doc = "Register `MP_ES` reader"] +pub type R = crate::R; +#[doc = "Destination Bus Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dbe { + #[doc = "0: No destination bus error"] + NoError = 0, + #[doc = "1: Last recorded error was a bus error on a destination write"] + BusError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dbe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBE` reader - Destination Bus Error"] +pub type DbeR = crate::BitReader; +impl DbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dbe { + match self.bits { + false => Dbe::NoError, + true => Dbe::BusError, + } + } + #[doc = "No destination bus error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Dbe::NoError + } + #[doc = "Last recorded error was a bus error on a destination write"] + #[inline(always)] + pub fn is_bus_error(&self) -> bool { + *self == Dbe::BusError + } +} +#[doc = "Source Bus Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbe { + #[doc = "0: No source bus error"] + NoError = 0, + #[doc = "1: Last recorded error was a bus error on a source read"] + BusError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBE` reader - Source Bus Error"] +pub type SbeR = crate::BitReader; +impl SbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbe { + match self.bits { + false => Sbe::NoError, + true => Sbe::BusError, + } + } + #[doc = "No source bus error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Sbe::NoError + } + #[doc = "Last recorded error was a bus error on a source read"] + #[inline(always)] + pub fn is_bus_error(&self) -> bool { + *self == Sbe::BusError + } +} +#[doc = "Scatter/Gather Configuration Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sge { + #[doc = "0: No scatter/gather configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] + ConfigurationError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sge) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SGE` reader - Scatter/Gather Configuration Error"] +pub type SgeR = crate::BitReader; +impl SgeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sge { + match self.bits { + false => Sge::NoError, + true => Sge::ConfigurationError, + } + } + #[doc = "No scatter/gather configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Sge::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] + #[inline(always)] + pub fn is_configuration_error(&self) -> bool { + *self == Sge::ConfigurationError + } +} +#[doc = "NBYTES/CITER Configuration Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nce { + #[doc = "0: No NBYTES/CITER configuration error"] + NoError = 0, + #[doc = "1: The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error"] + ConfigurationError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nce) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NCE` reader - NBYTES/CITER Configuration Error"] +pub type NceR = crate::BitReader; +impl NceR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nce { + match self.bits { + false => Nce::NoError, + true => Nce::ConfigurationError, + } + } + #[doc = "No NBYTES/CITER configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Nce::NoError + } + #[doc = "The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error"] + #[inline(always)] + pub fn is_configuration_error(&self) -> bool { + *self == Nce::ConfigurationError + } +} +#[doc = "Destination Offset Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Doe { + #[doc = "0: No destination offset configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DOFF field"] + ConfigurationError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Doe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DOE` reader - Destination Offset Error"] +pub type DoeR = crate::BitReader; +impl DoeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Doe { + match self.bits { + false => Doe::NoError, + true => Doe::ConfigurationError, + } + } + #[doc = "No destination offset configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Doe::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_DOFF field"] + #[inline(always)] + pub fn is_configuration_error(&self) -> bool { + *self == Doe::ConfigurationError + } +} +#[doc = "Destination Address Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dae { + #[doc = "0: No destination address configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DADDR field"] + ConfigurationError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAE` reader - Destination Address Error"] +pub type DaeR = crate::BitReader; +impl DaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dae { + match self.bits { + false => Dae::NoError, + true => Dae::ConfigurationError, + } + } + #[doc = "No destination address configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Dae::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_DADDR field"] + #[inline(always)] + pub fn is_configuration_error(&self) -> bool { + *self == Dae::ConfigurationError + } +} +#[doc = "Source Offset Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soe { + #[doc = "0: No source offset configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SOFF field"] + ConfigurationError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOE` reader - Source Offset Error"] +pub type SoeR = crate::BitReader; +impl SoeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soe { + match self.bits { + false => Soe::NoError, + true => Soe::ConfigurationError, + } + } + #[doc = "No source offset configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Soe::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_SOFF field"] + #[inline(always)] + pub fn is_configuration_error(&self) -> bool { + *self == Soe::ConfigurationError + } +} +#[doc = "Source Address Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sae { + #[doc = "0: No source address configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SADDR field"] + ConfigurationError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SAE` reader - Source Address Error"] +pub type SaeR = crate::BitReader; +impl SaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sae { + match self.bits { + false => Sae::NoError, + true => Sae::ConfigurationError, + } + } + #[doc = "No source address configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Sae::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_SADDR field"] + #[inline(always)] + pub fn is_configuration_error(&self) -> bool { + *self == Sae::ConfigurationError + } +} +#[doc = "Transfer Canceled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ecx { + #[doc = "0: No canceled transfers"] + NoCanceledTransfers = 0, + #[doc = "1: Last recorded entry was a canceled transfer by the error cancel transfer input"] + CanceledTransfer = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ecx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ECX` reader - Transfer Canceled"] +pub type EcxR = crate::BitReader; +impl EcxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ecx { + match self.bits { + false => Ecx::NoCanceledTransfers, + true => Ecx::CanceledTransfer, + } + } + #[doc = "No canceled transfers"] + #[inline(always)] + pub fn is_no_canceled_transfers(&self) -> bool { + *self == Ecx::NoCanceledTransfers + } + #[doc = "Last recorded entry was a canceled transfer by the error cancel transfer input"] + #[inline(always)] + pub fn is_canceled_transfer(&self) -> bool { + *self == Ecx::CanceledTransfer + } +} +#[doc = "Field `ERRCHN` reader - Error Channel Number or Canceled Channel Number"] +pub type ErrchnR = crate::FieldReader; +#[doc = "Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Vld { + #[doc = "0: No CHn_ES\\[ERR\\] fields are set to 1"] + NoFieldSetOne = 0, + #[doc = "1: At least one CHn_ES\\[ERR\\] field is set to 1, indicating a valid error exists that software has not cleared"] + AtleastOneField = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Vld) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VLD` reader - Valid"] +pub type VldR = crate::BitReader; +impl VldR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Vld { + match self.bits { + false => Vld::NoFieldSetOne, + true => Vld::AtleastOneField, + } + } + #[doc = "No CHn_ES\\[ERR\\] fields are set to 1"] + #[inline(always)] + pub fn is_no_field_set_one(&self) -> bool { + *self == Vld::NoFieldSetOne + } + #[doc = "At least one CHn_ES\\[ERR\\] field is set to 1, indicating a valid error exists that software has not cleared"] + #[inline(always)] + pub fn is_atleast_one_field(&self) -> bool { + *self == Vld::AtleastOneField + } +} +impl R { + #[doc = "Bit 0 - Destination Bus Error"] + #[inline(always)] + pub fn dbe(&self) -> DbeR { + DbeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Source Bus Error"] + #[inline(always)] + pub fn sbe(&self) -> SbeR { + SbeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Scatter/Gather Configuration Error"] + #[inline(always)] + pub fn sge(&self) -> SgeR { + SgeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NBYTES/CITER Configuration Error"] + #[inline(always)] + pub fn nce(&self) -> NceR { + NceR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Destination Offset Error"] + #[inline(always)] + pub fn doe(&self) -> DoeR { + DoeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Destination Address Error"] + #[inline(always)] + pub fn dae(&self) -> DaeR { + DaeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Source Offset Error"] + #[inline(always)] + pub fn soe(&self) -> SoeR { + SoeR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Source Address Error"] + #[inline(always)] + pub fn sae(&self) -> SaeR { + SaeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transfer Canceled"] + #[inline(always)] + pub fn ecx(&self) -> EcxR { + EcxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 24:26 - Error Channel Number or Canceled Channel Number"] + #[inline(always)] + pub fn errchn(&self) -> ErrchnR { + ErrchnR::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 31 - Valid"] + #[inline(always)] + pub fn vld(&self) -> VldR { + VldR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Management Page Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_es::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MpEsSpec; +impl crate::RegisterSpec for MpEsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mp_es::R`](R) reader structure"] +impl crate::Readable for MpEsSpec {} +#[doc = "`reset()` method sets MP_ES to value 0"] +impl crate::Resettable for MpEsSpec {} diff --git a/mcxa276-pac/src/dma0/mp_hrs.rs b/mcxa276-pac/src/dma0/mp_hrs.rs new file mode 100644 index 000000000..460f3dad0 --- /dev/null +++ b/mcxa276-pac/src/dma0/mp_hrs.rs @@ -0,0 +1,20 @@ +#[doc = "Register `MP_HRS` reader"] +pub type R = crate::R; +#[doc = "Field `HRS` reader - Hardware Request Status"] +pub type HrsR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Hardware Request Status"] + #[inline(always)] + pub fn hrs(&self) -> HrsR { + HrsR::new(self.bits) + } +} +#[doc = "Management Page Hardware Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_hrs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MpHrsSpec; +impl crate::RegisterSpec for MpHrsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mp_hrs::R`](R) reader structure"] +impl crate::Readable for MpHrsSpec {} +#[doc = "`reset()` method sets MP_HRS to value 0"] +impl crate::Resettable for MpHrsSpec {} diff --git a/mcxa276-pac/src/dma0/mp_int.rs b/mcxa276-pac/src/dma0/mp_int.rs new file mode 100644 index 000000000..6807bede7 --- /dev/null +++ b/mcxa276-pac/src/dma0/mp_int.rs @@ -0,0 +1,20 @@ +#[doc = "Register `MP_INT` reader"] +pub type R = crate::R; +#[doc = "Field `INT` reader - Interrupt Request Status"] +pub type IntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Interrupt Request Status"] + #[inline(always)] + pub fn int(&self) -> IntR { + IntR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Management Page Interrupt Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_int::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MpIntSpec; +impl crate::RegisterSpec for MpIntSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mp_int::R`](R) reader structure"] +impl crate::Readable for MpIntSpec {} +#[doc = "`reset()` method sets MP_INT to value 0"] +impl crate::Resettable for MpIntSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0.rs b/mcxa276-pac/src/edma_0_tcd0.rs new file mode 100644 index 000000000..185852cca --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0.rs @@ -0,0 +1,26 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + tcd: (), +} +impl RegisterBlock { + #[doc = "0x00..0x200 - Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] + #[inline(always)] + pub const fn tcd(&self, n: usize) -> &Tcd { + #[allow(clippy::no_effect)] + [(); 8][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(4096 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x200 - Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] + #[inline(always)] + pub fn tcd_iter(&self) -> impl Iterator { + (0..8) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(4096 * n).cast() }) + } +} +#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] +pub use self::tcd::Tcd; +#[doc = r"Cluster"] +#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] +pub mod tcd; diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd.rs b/mcxa276-pac/src/edma_0_tcd0/tcd.rs new file mode 100644 index 000000000..675be7afd --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd.rs @@ -0,0 +1,229 @@ +#[repr(C)] +#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] +#[doc(alias = "TCD")] +pub struct Tcd { + ch_csr: ChCsr, + ch_es: ChEs, + ch_int: ChInt, + ch_sbr: ChSbr, + ch_pri: ChPri, + ch_mux: ChMux, + _reserved6: [u8; 0x08], + tcd_saddr: TcdSaddr, + tcd_soff: TcdSoff, + tcd_attr: TcdAttr, + _reserved_9_mloffno_tcd_nbytes_mloffno: [u8; 0x04], + tcd_slast_sda: TcdSlastSda, + tcd_daddr: TcdDaddr, + tcd_doff: TcdDoff, + _reserved_13_elinkno_tcd_citer_elinkno: [u8; 0x02], + tcd_dlast_sga: TcdDlastSga, + tcd_csr: TcdCsr, + _reserved_16_elinkno_tcd_biter_elinkno: [u8; 0x02], +} +impl Tcd { + #[doc = "0x00 - Channel Control and Status"] + #[inline(always)] + pub const fn ch_csr(&self) -> &ChCsr { + &self.ch_csr + } + #[doc = "0x04 - Channel Error Status"] + #[inline(always)] + pub const fn ch_es(&self) -> &ChEs { + &self.ch_es + } + #[doc = "0x08 - Channel Interrupt Status"] + #[inline(always)] + pub const fn ch_int(&self) -> &ChInt { + &self.ch_int + } + #[doc = "0x0c - Channel System Bus"] + #[inline(always)] + pub const fn ch_sbr(&self) -> &ChSbr { + &self.ch_sbr + } + #[doc = "0x10 - Channel Priority"] + #[inline(always)] + pub const fn ch_pri(&self) -> &ChPri { + &self.ch_pri + } + #[doc = "0x14 - Channel Multiplexor Configuration"] + #[inline(always)] + pub const fn ch_mux(&self) -> &ChMux { + &self.ch_mux + } + #[doc = "0x20 - TCD Source Address"] + #[inline(always)] + pub const fn tcd_saddr(&self) -> &TcdSaddr { + &self.tcd_saddr + } + #[doc = "0x24 - TCD Signed Source Address Offset"] + #[inline(always)] + pub const fn tcd_soff(&self) -> &TcdSoff { + &self.tcd_soff + } + #[doc = "0x26 - TCD Transfer Attributes"] + #[inline(always)] + pub const fn tcd_attr(&self) -> &TcdAttr { + &self.tcd_attr + } + #[doc = "0x28 - TCD Transfer Size with Minor Loop Offsets"] + #[inline(always)] + pub const fn mloffyes_tcd_nbytes_mloffyes(&self) -> &MloffyesTcdNbytesMloffyes { + unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } + } + #[doc = "0x28 - TCD Transfer Size Without Minor Loop Offsets"] + #[inline(always)] + pub const fn mloffno_tcd_nbytes_mloffno(&self) -> &MloffnoTcdNbytesMloffno { + unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } + } + #[doc = "0x2c - TCD Last Source Address Adjustment / Store DADDR Address"] + #[inline(always)] + pub const fn tcd_slast_sda(&self) -> &TcdSlastSda { + &self.tcd_slast_sda + } + #[doc = "0x30 - TCD Destination Address"] + #[inline(always)] + pub const fn tcd_daddr(&self) -> &TcdDaddr { + &self.tcd_daddr + } + #[doc = "0x34 - TCD Signed Destination Address Offset"] + #[inline(always)] + pub const fn tcd_doff(&self) -> &TcdDoff { + &self.tcd_doff + } + #[doc = "0x36 - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"] + #[inline(always)] + pub const fn elinkyes_tcd_citer_elinkyes(&self) -> &ElinkyesTcdCiterElinkyes { + unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } + } + #[doc = "0x36 - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"] + #[inline(always)] + pub const fn elinkno_tcd_citer_elinkno(&self) -> &ElinknoTcdCiterElinkno { + unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } + } + #[doc = "0x38 - TCD Last Destination Address Adjustment / Scatter Gather Address"] + #[inline(always)] + pub const fn tcd_dlast_sga(&self) -> &TcdDlastSga { + &self.tcd_dlast_sga + } + #[doc = "0x3c - TCD Control and Status"] + #[inline(always)] + pub const fn tcd_csr(&self) -> &TcdCsr { + &self.tcd_csr + } + #[doc = "0x3e - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"] + #[inline(always)] + pub const fn elinkyes_tcd_biter_elinkyes(&self) -> &ElinkyesTcdBiterElinkyes { + unsafe { &*core::ptr::from_ref(self).cast::().add(62).cast() } + } + #[doc = "0x3e - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"] + #[inline(always)] + pub const fn elinkno_tcd_biter_elinkno(&self) -> &ElinknoTcdBiterElinkno { + unsafe { &*core::ptr::from_ref(self).cast::().add(62).cast() } + } +} +#[doc = "CH_CSR (rw) register accessor: Channel Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_csr`] module"] +#[doc(alias = "CH_CSR")] +pub type ChCsr = crate::Reg; +#[doc = "Channel Control and Status"] +pub mod ch_csr; +#[doc = "CH_ES (rw) register accessor: Channel Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_es::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_es::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_es`] module"] +#[doc(alias = "CH_ES")] +pub type ChEs = crate::Reg; +#[doc = "Channel Error Status"] +pub mod ch_es; +#[doc = "CH_INT (rw) register accessor: Channel Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_int`] module"] +#[doc(alias = "CH_INT")] +pub type ChInt = crate::Reg; +#[doc = "Channel Interrupt Status"] +pub mod ch_int; +#[doc = "CH_SBR (rw) register accessor: Channel System Bus\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_sbr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_sbr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_sbr`] module"] +#[doc(alias = "CH_SBR")] +pub type ChSbr = crate::Reg; +#[doc = "Channel System Bus"] +pub mod ch_sbr; +#[doc = "CH_PRI (rw) register accessor: Channel Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_pri`] module"] +#[doc(alias = "CH_PRI")] +pub type ChPri = crate::Reg; +#[doc = "Channel Priority"] +pub mod ch_pri; +#[doc = "CH_MUX (rw) register accessor: Channel Multiplexor Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_mux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_mux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_mux`] module"] +#[doc(alias = "CH_MUX")] +pub type ChMux = crate::Reg; +#[doc = "Channel Multiplexor Configuration"] +pub mod ch_mux; +#[doc = "TCD_SADDR (rw) register accessor: TCD Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_saddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_saddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_saddr`] module"] +#[doc(alias = "TCD_SADDR")] +pub type TcdSaddr = crate::Reg; +#[doc = "TCD Source Address"] +pub mod tcd_saddr; +#[doc = "TCD_SOFF (rw) register accessor: TCD Signed Source Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_soff::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_soff::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_soff`] module"] +#[doc(alias = "TCD_SOFF")] +pub type TcdSoff = crate::Reg; +#[doc = "TCD Signed Source Address Offset"] +pub mod tcd_soff; +#[doc = "TCD_ATTR (rw) register accessor: TCD Transfer Attributes\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_attr`] module"] +#[doc(alias = "TCD_ATTR")] +pub type TcdAttr = crate::Reg; +#[doc = "TCD Transfer Attributes"] +pub mod tcd_attr; +#[doc = "MLOFFNO_TCD_NBYTES_MLOFFNO (rw) register accessor: TCD Transfer Size Without Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffno_tcd_nbytes_mloffno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffno_tcd_nbytes_mloffno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mloffno_tcd_nbytes_mloffno`] module"] +#[doc(alias = "MLOFFNO_TCD_NBYTES_MLOFFNO")] +pub type MloffnoTcdNbytesMloffno = + crate::Reg; +#[doc = "TCD Transfer Size Without Minor Loop Offsets"] +pub mod mloffno_tcd_nbytes_mloffno; +#[doc = "MLOFFYES_TCD_NBYTES_MLOFFYES (rw) register accessor: TCD Transfer Size with Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffyes_tcd_nbytes_mloffyes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffyes_tcd_nbytes_mloffyes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mloffyes_tcd_nbytes_mloffyes`] module"] +#[doc(alias = "MLOFFYES_TCD_NBYTES_MLOFFYES")] +pub type MloffyesTcdNbytesMloffyes = + crate::Reg; +#[doc = "TCD Transfer Size with Minor Loop Offsets"] +pub mod mloffyes_tcd_nbytes_mloffyes; +#[doc = "TCD_SLAST_SDA (rw) register accessor: TCD Last Source Address Adjustment / Store DADDR Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_slast_sda::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_slast_sda::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_slast_sda`] module"] +#[doc(alias = "TCD_SLAST_SDA")] +pub type TcdSlastSda = crate::Reg; +#[doc = "TCD Last Source Address Adjustment / Store DADDR Address"] +pub mod tcd_slast_sda; +#[doc = "TCD_DADDR (rw) register accessor: TCD Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_daddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_daddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_daddr`] module"] +#[doc(alias = "TCD_DADDR")] +pub type TcdDaddr = crate::Reg; +#[doc = "TCD Destination Address"] +pub mod tcd_daddr; +#[doc = "TCD_DOFF (rw) register accessor: TCD Signed Destination Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_doff::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_doff::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_doff`] module"] +#[doc(alias = "TCD_DOFF")] +pub type TcdDoff = crate::Reg; +#[doc = "TCD Signed Destination Address Offset"] +pub mod tcd_doff; +#[doc = "ELINKNO_TCD_CITER_ELINKNO (rw) register accessor: TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_citer_elinkno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_citer_elinkno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkno_tcd_citer_elinkno`] module"] +#[doc(alias = "ELINKNO_TCD_CITER_ELINKNO")] +pub type ElinknoTcdCiterElinkno = crate::Reg; +#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"] +pub mod elinkno_tcd_citer_elinkno; +#[doc = "ELINKYES_TCD_CITER_ELINKYES (rw) register accessor: TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_citer_elinkyes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_citer_elinkyes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkyes_tcd_citer_elinkyes`] module"] +#[doc(alias = "ELINKYES_TCD_CITER_ELINKYES")] +pub type ElinkyesTcdCiterElinkyes = + crate::Reg; +#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"] +pub mod elinkyes_tcd_citer_elinkyes; +#[doc = "TCD_DLAST_SGA (rw) register accessor: TCD Last Destination Address Adjustment / Scatter Gather Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_dlast_sga::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_dlast_sga::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_dlast_sga`] module"] +#[doc(alias = "TCD_DLAST_SGA")] +pub type TcdDlastSga = crate::Reg; +#[doc = "TCD Last Destination Address Adjustment / Scatter Gather Address"] +pub mod tcd_dlast_sga; +#[doc = "TCD_CSR (rw) register accessor: TCD Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_csr`] module"] +#[doc(alias = "TCD_CSR")] +pub type TcdCsr = crate::Reg; +#[doc = "TCD Control and Status"] +pub mod tcd_csr; +#[doc = "ELINKNO_TCD_BITER_ELINKNO (rw) register accessor: TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_biter_elinkno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_biter_elinkno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkno_tcd_biter_elinkno`] module"] +#[doc(alias = "ELINKNO_TCD_BITER_ELINKNO")] +pub type ElinknoTcdBiterElinkno = crate::Reg; +#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"] +pub mod elinkno_tcd_biter_elinkno; +#[doc = "ELINKYES_TCD_BITER_ELINKYES (rw) register accessor: TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_biter_elinkyes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_biter_elinkyes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkyes_tcd_biter_elinkyes`] module"] +#[doc(alias = "ELINKYES_TCD_BITER_ELINKYES")] +pub type ElinkyesTcdBiterElinkyes = + crate::Reg; +#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"] +pub mod elinkyes_tcd_biter_elinkyes; diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs new file mode 100644 index 000000000..56aa4348b --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs @@ -0,0 +1,295 @@ +#[doc = "Register `CH_CSR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_CSR` writer"] +pub type W = crate::W; +#[doc = "Enable DMA Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erq { + #[doc = "0: DMA hardware request signal for corresponding channel disabled"] + Disable = 0, + #[doc = "1: DMA hardware request signal for corresponding channel enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERQ` reader - Enable DMA Request"] +pub type ErqR = crate::BitReader; +impl ErqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erq { + match self.bits { + false => Erq::Disable, + true => Erq::Enable, + } + } + #[doc = "DMA hardware request signal for corresponding channel disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Erq::Disable + } + #[doc = "DMA hardware request signal for corresponding channel enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Erq::Enable + } +} +#[doc = "Field `ERQ` writer - Enable DMA Request"] +pub type ErqW<'a, REG> = crate::BitWriter<'a, REG, Erq>; +impl<'a, REG> ErqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DMA hardware request signal for corresponding channel disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Erq::Disable) + } + #[doc = "DMA hardware request signal for corresponding channel enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Erq::Enable) + } +} +#[doc = "Enable Asynchronous DMA Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Earq { + #[doc = "0: Disable asynchronous DMA request for the channel"] + Disable = 0, + #[doc = "1: Enable asynchronous DMA request for the channel"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Earq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EARQ` reader - Enable Asynchronous DMA Request"] +pub type EarqR = crate::BitReader; +impl EarqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Earq { + match self.bits { + false => Earq::Disable, + true => Earq::Enable, + } + } + #[doc = "Disable asynchronous DMA request for the channel"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Earq::Disable + } + #[doc = "Enable asynchronous DMA request for the channel"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Earq::Enable + } +} +#[doc = "Field `EARQ` writer - Enable Asynchronous DMA Request"] +pub type EarqW<'a, REG> = crate::BitWriter<'a, REG, Earq>; +impl<'a, REG> EarqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable asynchronous DMA request for the channel"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Earq::Disable) + } + #[doc = "Enable asynchronous DMA request for the channel"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Earq::Enable) + } +} +#[doc = "Enable Error Interrupt\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Eei { + #[doc = "0: Error signal for corresponding channel does not generate error interrupt"] + NoError = 0, + #[doc = "1: Assertion of error signal for corresponding channel generates error interrupt request"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Eei) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EEI` reader - Enable Error Interrupt"] +pub type EeiR = crate::BitReader; +impl EeiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Eei { + match self.bits { + false => Eei::NoError, + true => Eei::Error, + } + } + #[doc = "Error signal for corresponding channel does not generate error interrupt"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Eei::NoError + } + #[doc = "Assertion of error signal for corresponding channel generates error interrupt request"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Eei::Error + } +} +#[doc = "Field `EEI` writer - Enable Error Interrupt"] +pub type EeiW<'a, REG> = crate::BitWriter<'a, REG, Eei>; +impl<'a, REG> EeiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error signal for corresponding channel does not generate error interrupt"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Eei::NoError) + } + #[doc = "Assertion of error signal for corresponding channel generates error interrupt request"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Eei::Error) + } +} +#[doc = "Enable Buffered Writes\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ebw { + #[doc = "0: Buffered writes on system bus disabled"] + Disable = 0, + #[doc = "1: Buffered writes on system bus enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ebw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EBW` reader - Enable Buffered Writes"] +pub type EbwR = crate::BitReader; +impl EbwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ebw { + match self.bits { + false => Ebw::Disable, + true => Ebw::Enable, + } + } + #[doc = "Buffered writes on system bus disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ebw::Disable + } + #[doc = "Buffered writes on system bus enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ebw::Enable + } +} +#[doc = "Field `EBW` writer - Enable Buffered Writes"] +pub type EbwW<'a, REG> = crate::BitWriter<'a, REG, Ebw>; +impl<'a, REG> EbwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Buffered writes on system bus disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ebw::Disable) + } + #[doc = "Buffered writes on system bus enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ebw::Enable) + } +} +#[doc = "Field `DONE` reader - Channel Done"] +pub type DoneR = crate::BitReader; +#[doc = "Field `DONE` writer - Channel Done"] +pub type DoneW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ACTIVE` reader - Channel Active"] +pub type ActiveR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Enable DMA Request"] + #[inline(always)] + pub fn erq(&self) -> ErqR { + ErqR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Asynchronous DMA Request"] + #[inline(always)] + pub fn earq(&self) -> EarqR { + EarqR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable Error Interrupt"] + #[inline(always)] + pub fn eei(&self) -> EeiR { + EeiR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable Buffered Writes"] + #[inline(always)] + pub fn ebw(&self) -> EbwR { + EbwR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 30 - Channel Done"] + #[inline(always)] + pub fn done(&self) -> DoneR { + DoneR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Channel Active"] + #[inline(always)] + pub fn active(&self) -> ActiveR { + ActiveR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable DMA Request"] + #[inline(always)] + pub fn erq(&mut self) -> ErqW { + ErqW::new(self, 0) + } + #[doc = "Bit 1 - Enable Asynchronous DMA Request"] + #[inline(always)] + pub fn earq(&mut self) -> EarqW { + EarqW::new(self, 1) + } + #[doc = "Bit 2 - Enable Error Interrupt"] + #[inline(always)] + pub fn eei(&mut self) -> EeiW { + EeiW::new(self, 2) + } + #[doc = "Bit 3 - Enable Buffered Writes"] + #[inline(always)] + pub fn ebw(&mut self) -> EbwW { + EbwW::new(self, 3) + } + #[doc = "Bit 30 - Channel Done"] + #[inline(always)] + pub fn done(&mut self) -> DoneW { + DoneW::new(self, 30) + } +} +#[doc = "Channel Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChCsrSpec; +impl crate::RegisterSpec for ChCsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_csr::R`](R) reader structure"] +impl crate::Readable for ChCsrSpec {} +#[doc = "`write(|w| ..)` method takes [`ch_csr::W`](W) writer structure"] +impl crate::Writable for ChCsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x4000_0000; +} +#[doc = "`reset()` method sets CH_CSR to value 0"] +impl crate::Resettable for ChCsrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs new file mode 100644 index 000000000..b7bd233ac --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs @@ -0,0 +1,413 @@ +#[doc = "Register `CH_ES` reader"] +pub type R = crate::R; +#[doc = "Register `CH_ES` writer"] +pub type W = crate::W; +#[doc = "Destination Bus Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dbe { + #[doc = "0: No destination bus error"] + NoError = 0, + #[doc = "1: Last recorded error was bus error on destination write"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dbe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBE` reader - Destination Bus Error"] +pub type DbeR = crate::BitReader; +impl DbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dbe { + match self.bits { + false => Dbe::NoError, + true => Dbe::Error, + } + } + #[doc = "No destination bus error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Dbe::NoError + } + #[doc = "Last recorded error was bus error on destination write"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Dbe::Error + } +} +#[doc = "Source Bus Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbe { + #[doc = "0: No source bus error"] + NoError = 0, + #[doc = "1: Last recorded error was bus error on source read"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBE` reader - Source Bus Error"] +pub type SbeR = crate::BitReader; +impl SbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbe { + match self.bits { + false => Sbe::NoError, + true => Sbe::Error, + } + } + #[doc = "No source bus error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Sbe::NoError + } + #[doc = "Last recorded error was bus error on source read"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Sbe::Error + } +} +#[doc = "Scatter/Gather Configuration Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sge { + #[doc = "0: No scatter/gather configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sge) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SGE` reader - Scatter/Gather Configuration Error"] +pub type SgeR = crate::BitReader; +impl SgeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sge { + match self.bits { + false => Sge::NoError, + true => Sge::Error, + } + } + #[doc = "No scatter/gather configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Sge::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Sge::Error + } +} +#[doc = "NBYTES/CITER Configuration Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nce { + #[doc = "0: No NBYTES/CITER configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nce) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NCE` reader - NBYTES/CITER Configuration Error"] +pub type NceR = crate::BitReader; +impl NceR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nce { + match self.bits { + false => Nce::NoError, + true => Nce::Error, + } + } + #[doc = "No NBYTES/CITER configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Nce::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Nce::Error + } +} +#[doc = "Destination Offset Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Doe { + #[doc = "0: No destination offset configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DOFF field"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Doe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DOE` reader - Destination Offset Error"] +pub type DoeR = crate::BitReader; +impl DoeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Doe { + match self.bits { + false => Doe::NoError, + true => Doe::Error, + } + } + #[doc = "No destination offset configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Doe::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_DOFF field"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Doe::Error + } +} +#[doc = "Destination Address Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dae { + #[doc = "0: No destination address configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DADDR field"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAE` reader - Destination Address Error"] +pub type DaeR = crate::BitReader; +impl DaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dae { + match self.bits { + false => Dae::NoError, + true => Dae::Error, + } + } + #[doc = "No destination address configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Dae::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_DADDR field"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Dae::Error + } +} +#[doc = "Source Offset Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soe { + #[doc = "0: No source offset configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SOFF field"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOE` reader - Source Offset Error"] +pub type SoeR = crate::BitReader; +impl SoeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soe { + match self.bits { + false => Soe::NoError, + true => Soe::Error, + } + } + #[doc = "No source offset configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Soe::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_SOFF field"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Soe::Error + } +} +#[doc = "Source Address Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sae { + #[doc = "0: No source address configuration error"] + NoError = 0, + #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SADDR field"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SAE` reader - Source Address Error"] +pub type SaeR = crate::BitReader; +impl SaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sae { + match self.bits { + false => Sae::NoError, + true => Sae::Error, + } + } + #[doc = "No source address configuration error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Sae::NoError + } + #[doc = "Last recorded error was a configuration error detected in the TCDn_SADDR field"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Sae::Error + } +} +#[doc = "Error In Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Err { + #[doc = "0: An error in this channel has not occurred"] + NoError = 0, + #[doc = "1: An error in this channel has occurred"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERR` reader - Error In Channel"] +pub type ErrR = crate::BitReader; +impl ErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Err { + match self.bits { + false => Err::NoError, + true => Err::Error, + } + } + #[doc = "An error in this channel has not occurred"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Err::NoError + } + #[doc = "An error in this channel has occurred"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Err::Error + } +} +#[doc = "Field `ERR` writer - Error In Channel"] +pub type ErrW<'a, REG> = crate::BitWriter1C<'a, REG, Err>; +impl<'a, REG> ErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "An error in this channel has not occurred"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Err::NoError) + } + #[doc = "An error in this channel has occurred"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Err::Error) + } +} +impl R { + #[doc = "Bit 0 - Destination Bus Error"] + #[inline(always)] + pub fn dbe(&self) -> DbeR { + DbeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Source Bus Error"] + #[inline(always)] + pub fn sbe(&self) -> SbeR { + SbeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Scatter/Gather Configuration Error"] + #[inline(always)] + pub fn sge(&self) -> SgeR { + SgeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NBYTES/CITER Configuration Error"] + #[inline(always)] + pub fn nce(&self) -> NceR { + NceR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Destination Offset Error"] + #[inline(always)] + pub fn doe(&self) -> DoeR { + DoeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Destination Address Error"] + #[inline(always)] + pub fn dae(&self) -> DaeR { + DaeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Source Offset Error"] + #[inline(always)] + pub fn soe(&self) -> SoeR { + SoeR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Source Address Error"] + #[inline(always)] + pub fn sae(&self) -> SaeR { + SaeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 31 - Error In Channel"] + #[inline(always)] + pub fn err(&self) -> ErrR { + ErrR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 31 - Error In Channel"] + #[inline(always)] + pub fn err(&mut self) -> ErrW { + ErrW::new(self, 31) + } +} +#[doc = "Channel Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_es::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_es::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChEsSpec; +impl crate::RegisterSpec for ChEsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_es::R`](R) reader structure"] +impl crate::Readable for ChEsSpec {} +#[doc = "`write(|w| ..)` method takes [`ch_es::W`](W) writer structure"] +impl crate::Writable for ChEsSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000; +} +#[doc = "`reset()` method sets CH_ES to value 0"] +impl crate::Resettable for ChEsSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs new file mode 100644 index 000000000..459d2be13 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH_INT` reader"] +pub type R = crate::R; +#[doc = "Register `CH_INT` writer"] +pub type W = crate::W; +#[doc = "Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int { + #[doc = "0: Interrupt request for corresponding channel cleared"] + InterruptCleared = 0, + #[doc = "1: Interrupt request for corresponding channel active"] + InterruptActive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT` reader - Interrupt Request"] +pub type IntR = crate::BitReader; +impl IntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int { + match self.bits { + false => Int::InterruptCleared, + true => Int::InterruptActive, + } + } + #[doc = "Interrupt request for corresponding channel cleared"] + #[inline(always)] + pub fn is_interrupt_cleared(&self) -> bool { + *self == Int::InterruptCleared + } + #[doc = "Interrupt request for corresponding channel active"] + #[inline(always)] + pub fn is_interrupt_active(&self) -> bool { + *self == Int::InterruptActive + } +} +#[doc = "Field `INT` writer - Interrupt Request"] +pub type IntW<'a, REG> = crate::BitWriter1C<'a, REG, Int>; +impl<'a, REG> IntW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request for corresponding channel cleared"] + #[inline(always)] + pub fn interrupt_cleared(self) -> &'a mut crate::W { + self.variant(Int::InterruptCleared) + } + #[doc = "Interrupt request for corresponding channel active"] + #[inline(always)] + pub fn interrupt_active(self) -> &'a mut crate::W { + self.variant(Int::InterruptActive) + } +} +impl R { + #[doc = "Bit 0 - Interrupt Request"] + #[inline(always)] + pub fn int(&self) -> IntR { + IntR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt Request"] + #[inline(always)] + pub fn int(&mut self) -> IntW { + IntW::new(self, 0) + } +} +#[doc = "Channel Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChIntSpec; +impl crate::RegisterSpec for ChIntSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_int::R`](R) reader structure"] +impl crate::Readable for ChIntSpec {} +#[doc = "`write(|w| ..)` method takes [`ch_int::W`](W) writer structure"] +impl crate::Writable for ChIntSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets CH_INT to value 0"] +impl crate::Resettable for ChIntSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs new file mode 100644 index 000000000..5b8f04c55 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CH_MUX` reader"] +pub type R = crate::R; +#[doc = "Register `CH_MUX` writer"] +pub type W = crate::W; +#[doc = "Field `SRC` reader - Service Request Source"] +pub type SrcR = crate::FieldReader; +#[doc = "Field `SRC` writer - Service Request Source"] +pub type SrcW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Service Request Source"] + #[inline(always)] + pub fn src(&self) -> SrcR { + SrcR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Service Request Source"] + #[inline(always)] + pub fn src(&mut self) -> SrcW { + SrcW::new(self, 0) + } +} +#[doc = "Channel Multiplexor Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChMuxSpec; +impl crate::RegisterSpec for ChMuxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_mux::R`](R) reader structure"] +impl crate::Readable for ChMuxSpec {} +#[doc = "`write(|w| ..)` method takes [`ch_mux::W`](W) writer structure"] +impl crate::Writable for ChMuxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CH_MUX to value 0"] +impl crate::Resettable for ChMuxSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs new file mode 100644 index 000000000..e21686d29 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs @@ -0,0 +1,161 @@ +#[doc = "Register `CH_PRI` reader"] +pub type R = crate::R; +#[doc = "Register `CH_PRI` writer"] +pub type W = crate::W; +#[doc = "Field `APL` reader - Arbitration Priority Level"] +pub type AplR = crate::FieldReader; +#[doc = "Field `APL` writer - Arbitration Priority Level"] +pub type AplW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Disable Preempt Ability\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dpa { + #[doc = "0: Channel can suspend a lower-priority channel"] + Suspend = 0, + #[doc = "1: Channel cannot suspend any other channel, regardless of channel priority"] + CannotSuspend = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dpa) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPA` reader - Disable Preempt Ability"] +pub type DpaR = crate::BitReader; +impl DpaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dpa { + match self.bits { + false => Dpa::Suspend, + true => Dpa::CannotSuspend, + } + } + #[doc = "Channel can suspend a lower-priority channel"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == Dpa::Suspend + } + #[doc = "Channel cannot suspend any other channel, regardless of channel priority"] + #[inline(always)] + pub fn is_cannot_suspend(&self) -> bool { + *self == Dpa::CannotSuspend + } +} +#[doc = "Field `DPA` writer - Disable Preempt Ability"] +pub type DpaW<'a, REG> = crate::BitWriter<'a, REG, Dpa>; +impl<'a, REG> DpaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel can suspend a lower-priority channel"] + #[inline(always)] + pub fn suspend(self) -> &'a mut crate::W { + self.variant(Dpa::Suspend) + } + #[doc = "Channel cannot suspend any other channel, regardless of channel priority"] + #[inline(always)] + pub fn cannot_suspend(self) -> &'a mut crate::W { + self.variant(Dpa::CannotSuspend) + } +} +#[doc = "Enable Channel Preemption\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ecp { + #[doc = "0: Channel cannot be suspended by a higher-priority channel's service request"] + CannotSuspend = 0, + #[doc = "1: Channel can be temporarily suspended by a higher-priority channel's service request"] + Suspend = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ecp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ECP` reader - Enable Channel Preemption"] +pub type EcpR = crate::BitReader; +impl EcpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ecp { + match self.bits { + false => Ecp::CannotSuspend, + true => Ecp::Suspend, + } + } + #[doc = "Channel cannot be suspended by a higher-priority channel's service request"] + #[inline(always)] + pub fn is_cannot_suspend(&self) -> bool { + *self == Ecp::CannotSuspend + } + #[doc = "Channel can be temporarily suspended by a higher-priority channel's service request"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == Ecp::Suspend + } +} +#[doc = "Field `ECP` writer - Enable Channel Preemption"] +pub type EcpW<'a, REG> = crate::BitWriter<'a, REG, Ecp>; +impl<'a, REG> EcpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel cannot be suspended by a higher-priority channel's service request"] + #[inline(always)] + pub fn cannot_suspend(self) -> &'a mut crate::W { + self.variant(Ecp::CannotSuspend) + } + #[doc = "Channel can be temporarily suspended by a higher-priority channel's service request"] + #[inline(always)] + pub fn suspend(self) -> &'a mut crate::W { + self.variant(Ecp::Suspend) + } +} +impl R { + #[doc = "Bits 0:2 - Arbitration Priority Level"] + #[inline(always)] + pub fn apl(&self) -> AplR { + AplR::new((self.bits & 7) as u8) + } + #[doc = "Bit 30 - Disable Preempt Ability"] + #[inline(always)] + pub fn dpa(&self) -> DpaR { + DpaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Enable Channel Preemption"] + #[inline(always)] + pub fn ecp(&self) -> EcpR { + EcpR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Arbitration Priority Level"] + #[inline(always)] + pub fn apl(&mut self) -> AplW { + AplW::new(self, 0) + } + #[doc = "Bit 30 - Disable Preempt Ability"] + #[inline(always)] + pub fn dpa(&mut self) -> DpaW { + DpaW::new(self, 30) + } + #[doc = "Bit 31 - Enable Channel Preemption"] + #[inline(always)] + pub fn ecp(&mut self) -> EcpW { + EcpW::new(self, 31) + } +} +#[doc = "Channel Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_pri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_pri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChPriSpec; +impl crate::RegisterSpec for ChPriSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_pri::R`](R) reader structure"] +impl crate::Readable for ChPriSpec {} +#[doc = "`write(|w| ..)` method takes [`ch_pri::W`](W) writer structure"] +impl crate::Writable for ChPriSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CH_PRI to value 0"] +impl crate::Resettable for ChPriSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs new file mode 100644 index 000000000..c248fb02d --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs @@ -0,0 +1,134 @@ +#[doc = "Register `CH_SBR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_SBR` writer"] +pub type W = crate::W; +#[doc = "Field `MID` reader - Master ID"] +pub type MidR = crate::FieldReader; +#[doc = "Privileged Access Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pal { + #[doc = "0: User protection level for DMA transfers"] + UserProtection = 0, + #[doc = "1: Privileged protection level for DMA transfers"] + PrivilegedProtection = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PAL` reader - Privileged Access Level"] +pub type PalR = crate::BitReader; +impl PalR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pal { + match self.bits { + false => Pal::UserProtection, + true => Pal::PrivilegedProtection, + } + } + #[doc = "User protection level for DMA transfers"] + #[inline(always)] + pub fn is_user_protection(&self) -> bool { + *self == Pal::UserProtection + } + #[doc = "Privileged protection level for DMA transfers"] + #[inline(always)] + pub fn is_privileged_protection(&self) -> bool { + *self == Pal::PrivilegedProtection + } +} +#[doc = "Enable Master ID Replication\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Emi { + #[doc = "0: Master ID replication is disabled"] + Disable = 0, + #[doc = "1: Master ID replication is enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Emi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EMI` reader - Enable Master ID Replication"] +pub type EmiR = crate::BitReader; +impl EmiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emi { + match self.bits { + false => Emi::Disable, + true => Emi::Enable, + } + } + #[doc = "Master ID replication is disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Emi::Disable + } + #[doc = "Master ID replication is enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Emi::Enable + } +} +#[doc = "Field `EMI` writer - Enable Master ID Replication"] +pub type EmiW<'a, REG> = crate::BitWriter<'a, REG, Emi>; +impl<'a, REG> EmiW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Master ID replication is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Emi::Disable) + } + #[doc = "Master ID replication is enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Emi::Enable) + } +} +impl R { + #[doc = "Bits 0:3 - Master ID"] + #[inline(always)] + pub fn mid(&self) -> MidR { + MidR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 15 - Privileged Access Level"] + #[inline(always)] + pub fn pal(&self) -> PalR { + PalR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable Master ID Replication"] + #[inline(always)] + pub fn emi(&self) -> EmiR { + EmiR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 16 - Enable Master ID Replication"] + #[inline(always)] + pub fn emi(&mut self) -> EmiW { + EmiW::new(self, 16) + } +} +#[doc = "Channel System Bus\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_sbr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_sbr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChSbrSpec; +impl crate::RegisterSpec for ChSbrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_sbr::R`](R) reader structure"] +impl crate::Readable for ChSbrSpec {} +#[doc = "`write(|w| ..)` method takes [`ch_sbr::W`](W) writer structure"] +impl crate::Writable for ChSbrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CH_SBR to value 0x05"] +impl crate::Resettable for ChSbrSpec { + const RESET_VALUE: u32 = 0x05; +} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs new file mode 100644 index 000000000..97d857cfc --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs @@ -0,0 +1,98 @@ +#[doc = "Register `TCD_BITER_ELINKNO` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_BITER_ELINKNO` writer"] +pub type W = crate::W; +#[doc = "Field `BITER` reader - Starting Major Iteration Count"] +pub type BiterR = crate::FieldReader; +#[doc = "Field `BITER` writer - Starting Major Iteration Count"] +pub type BiterW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Enables Link\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Elink { + #[doc = "0: Channel-to-channel linking disabled"] + Disable = 0, + #[doc = "1: Channel-to-channel linking enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Elink) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ELINK` reader - Enables Link"] +pub type ElinkR = crate::BitReader; +impl ElinkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Elink { + match self.bits { + false => Elink::Disable, + true => Elink::Enable, + } + } + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Elink::Disable + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Elink::Enable + } +} +#[doc = "Field `ELINK` writer - Enables Link"] +pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; +impl<'a, REG> ElinkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Elink::Disable) + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Elink::Enable) + } +} +impl R { + #[doc = "Bits 0:14 - Starting Major Iteration Count"] + #[inline(always)] + pub fn biter(&self) -> BiterR { + BiterR::new(self.bits & 0x7fff) + } + #[doc = "Bit 15 - Enables Link"] + #[inline(always)] + pub fn elink(&self) -> ElinkR { + ElinkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Starting Major Iteration Count"] + #[inline(always)] + pub fn biter(&mut self) -> BiterW { + BiterW::new(self, 0) + } + #[doc = "Bit 15 - Enables Link"] + #[inline(always)] + pub fn elink(&mut self) -> ElinkW { + ElinkW::new(self, 15) + } +} +#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_biter_elinkno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_biter_elinkno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElinknoTcdBiterElinknoSpec; +impl crate::RegisterSpec for ElinknoTcdBiterElinknoSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`elinkno_tcd_biter_elinkno::R`](R) reader structure"] +impl crate::Readable for ElinknoTcdBiterElinknoSpec {} +#[doc = "`write(|w| ..)` method takes [`elinkno_tcd_biter_elinkno::W`](W) writer structure"] +impl crate::Writable for ElinknoTcdBiterElinknoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_BITER_ELINKNO to value 0"] +impl crate::Resettable for ElinknoTcdBiterElinknoSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs new file mode 100644 index 000000000..701f9541b --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs @@ -0,0 +1,98 @@ +#[doc = "Register `TCD_CITER_ELINKNO` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_CITER_ELINKNO` writer"] +pub type W = crate::W; +#[doc = "Field `CITER` reader - Current Major Iteration Count"] +pub type CiterR = crate::FieldReader; +#[doc = "Field `CITER` writer - Current Major Iteration Count"] +pub type CiterW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Enable Link\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Elink { + #[doc = "0: Channel-to-channel linking disabled"] + Disable = 0, + #[doc = "1: Channel-to-channel linking enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Elink) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ELINK` reader - Enable Link"] +pub type ElinkR = crate::BitReader; +impl ElinkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Elink { + match self.bits { + false => Elink::Disable, + true => Elink::Enable, + } + } + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Elink::Disable + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Elink::Enable + } +} +#[doc = "Field `ELINK` writer - Enable Link"] +pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; +impl<'a, REG> ElinkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Elink::Disable) + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Elink::Enable) + } +} +impl R { + #[doc = "Bits 0:14 - Current Major Iteration Count"] + #[inline(always)] + pub fn citer(&self) -> CiterR { + CiterR::new(self.bits & 0x7fff) + } + #[doc = "Bit 15 - Enable Link"] + #[inline(always)] + pub fn elink(&self) -> ElinkR { + ElinkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Current Major Iteration Count"] + #[inline(always)] + pub fn citer(&mut self) -> CiterW { + CiterW::new(self, 0) + } + #[doc = "Bit 15 - Enable Link"] + #[inline(always)] + pub fn elink(&mut self) -> ElinkW { + ElinkW::new(self, 15) + } +} +#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_citer_elinkno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_citer_elinkno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElinknoTcdCiterElinknoSpec; +impl crate::RegisterSpec for ElinknoTcdCiterElinknoSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`elinkno_tcd_citer_elinkno::R`](R) reader structure"] +impl crate::Readable for ElinknoTcdCiterElinknoSpec {} +#[doc = "`write(|w| ..)` method takes [`elinkno_tcd_citer_elinkno::W`](W) writer structure"] +impl crate::Writable for ElinknoTcdCiterElinknoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_CITER_ELINKNO to value 0"] +impl crate::Resettable for ElinknoTcdCiterElinknoSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs new file mode 100644 index 000000000..145ee5789 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs @@ -0,0 +1,112 @@ +#[doc = "Register `TCD_BITER_ELINKYES` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_BITER_ELINKYES` writer"] +pub type W = crate::W; +#[doc = "Field `BITER` reader - Starting Major Iteration Count"] +pub type BiterR = crate::FieldReader; +#[doc = "Field `BITER` writer - Starting Major Iteration Count"] +pub type BiterW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `LINKCH` reader - Link Channel Number"] +pub type LinkchR = crate::FieldReader; +#[doc = "Field `LINKCH` writer - Link Channel Number"] +pub type LinkchW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Enable Link\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Elink { + #[doc = "0: Channel-to-channel linking disabled"] + Disable = 0, + #[doc = "1: Channel-to-channel linking enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Elink) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ELINK` reader - Enable Link"] +pub type ElinkR = crate::BitReader; +impl ElinkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Elink { + match self.bits { + false => Elink::Disable, + true => Elink::Enable, + } + } + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Elink::Disable + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Elink::Enable + } +} +#[doc = "Field `ELINK` writer - Enable Link"] +pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; +impl<'a, REG> ElinkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Elink::Disable) + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Elink::Enable) + } +} +impl R { + #[doc = "Bits 0:8 - Starting Major Iteration Count"] + #[inline(always)] + pub fn biter(&self) -> BiterR { + BiterR::new(self.bits & 0x01ff) + } + #[doc = "Bits 9:11 - Link Channel Number"] + #[inline(always)] + pub fn linkch(&self) -> LinkchR { + LinkchR::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 15 - Enable Link"] + #[inline(always)] + pub fn elink(&self) -> ElinkR { + ElinkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Starting Major Iteration Count"] + #[inline(always)] + pub fn biter(&mut self) -> BiterW { + BiterW::new(self, 0) + } + #[doc = "Bits 9:11 - Link Channel Number"] + #[inline(always)] + pub fn linkch(&mut self) -> LinkchW { + LinkchW::new(self, 9) + } + #[doc = "Bit 15 - Enable Link"] + #[inline(always)] + pub fn elink(&mut self) -> ElinkW { + ElinkW::new(self, 15) + } +} +#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_biter_elinkyes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_biter_elinkyes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElinkyesTcdBiterElinkyesSpec; +impl crate::RegisterSpec for ElinkyesTcdBiterElinkyesSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`elinkyes_tcd_biter_elinkyes::R`](R) reader structure"] +impl crate::Readable for ElinkyesTcdBiterElinkyesSpec {} +#[doc = "`write(|w| ..)` method takes [`elinkyes_tcd_biter_elinkyes::W`](W) writer structure"] +impl crate::Writable for ElinkyesTcdBiterElinkyesSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_BITER_ELINKYES to value 0"] +impl crate::Resettable for ElinkyesTcdBiterElinkyesSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs new file mode 100644 index 000000000..6c878f783 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs @@ -0,0 +1,112 @@ +#[doc = "Register `TCD_CITER_ELINKYES` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_CITER_ELINKYES` writer"] +pub type W = crate::W; +#[doc = "Field `CITER` reader - Current Major Iteration Count"] +pub type CiterR = crate::FieldReader; +#[doc = "Field `CITER` writer - Current Major Iteration Count"] +pub type CiterW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `LINKCH` reader - Minor Loop Link Channel Number"] +pub type LinkchR = crate::FieldReader; +#[doc = "Field `LINKCH` writer - Minor Loop Link Channel Number"] +pub type LinkchW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Enable Link\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Elink { + #[doc = "0: Channel-to-channel linking disabled"] + Disable = 0, + #[doc = "1: Channel-to-channel linking enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Elink) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ELINK` reader - Enable Link"] +pub type ElinkR = crate::BitReader; +impl ElinkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Elink { + match self.bits { + false => Elink::Disable, + true => Elink::Enable, + } + } + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Elink::Disable + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Elink::Enable + } +} +#[doc = "Field `ELINK` writer - Enable Link"] +pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; +impl<'a, REG> ElinkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Elink::Disable) + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Elink::Enable) + } +} +impl R { + #[doc = "Bits 0:8 - Current Major Iteration Count"] + #[inline(always)] + pub fn citer(&self) -> CiterR { + CiterR::new(self.bits & 0x01ff) + } + #[doc = "Bits 9:11 - Minor Loop Link Channel Number"] + #[inline(always)] + pub fn linkch(&self) -> LinkchR { + LinkchR::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 15 - Enable Link"] + #[inline(always)] + pub fn elink(&self) -> ElinkR { + ElinkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Current Major Iteration Count"] + #[inline(always)] + pub fn citer(&mut self) -> CiterW { + CiterW::new(self, 0) + } + #[doc = "Bits 9:11 - Minor Loop Link Channel Number"] + #[inline(always)] + pub fn linkch(&mut self) -> LinkchW { + LinkchW::new(self, 9) + } + #[doc = "Bit 15 - Enable Link"] + #[inline(always)] + pub fn elink(&mut self) -> ElinkW { + ElinkW::new(self, 15) + } +} +#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_citer_elinkyes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_citer_elinkyes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElinkyesTcdCiterElinkyesSpec; +impl crate::RegisterSpec for ElinkyesTcdCiterElinkyesSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`elinkyes_tcd_citer_elinkyes::R`](R) reader structure"] +impl crate::Readable for ElinkyesTcdCiterElinkyesSpec {} +#[doc = "`write(|w| ..)` method takes [`elinkyes_tcd_citer_elinkyes::W`](W) writer structure"] +impl crate::Writable for ElinkyesTcdCiterElinkyesSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_CITER_ELINKYES to value 0"] +impl crate::Resettable for ElinkyesTcdCiterElinkyesSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs new file mode 100644 index 000000000..0d9dbadd0 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs @@ -0,0 +1,161 @@ +#[doc = "Register `TCD_NBYTES_MLOFFNO` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_NBYTES_MLOFFNO` writer"] +pub type W = crate::W; +#[doc = "Field `NBYTES` reader - Number of Bytes To Transfer Per Service Request"] +pub type NbytesR = crate::FieldReader; +#[doc = "Field `NBYTES` writer - Number of Bytes To Transfer Per Service Request"] +pub type NbytesW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +#[doc = "Destination Minor Loop Offset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmloe { + #[doc = "0: Minor loop offset not applied to DADDR"] + OffsetNotApplied = 0, + #[doc = "1: Minor loop offset applied to DADDR"] + OffsetApplied = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmloe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMLOE` reader - Destination Minor Loop Offset Enable"] +pub type DmloeR = crate::BitReader; +impl DmloeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmloe { + match self.bits { + false => Dmloe::OffsetNotApplied, + true => Dmloe::OffsetApplied, + } + } + #[doc = "Minor loop offset not applied to DADDR"] + #[inline(always)] + pub fn is_offset_not_applied(&self) -> bool { + *self == Dmloe::OffsetNotApplied + } + #[doc = "Minor loop offset applied to DADDR"] + #[inline(always)] + pub fn is_offset_applied(&self) -> bool { + *self == Dmloe::OffsetApplied + } +} +#[doc = "Field `DMLOE` writer - Destination Minor Loop Offset Enable"] +pub type DmloeW<'a, REG> = crate::BitWriter<'a, REG, Dmloe>; +impl<'a, REG> DmloeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Minor loop offset not applied to DADDR"] + #[inline(always)] + pub fn offset_not_applied(self) -> &'a mut crate::W { + self.variant(Dmloe::OffsetNotApplied) + } + #[doc = "Minor loop offset applied to DADDR"] + #[inline(always)] + pub fn offset_applied(self) -> &'a mut crate::W { + self.variant(Dmloe::OffsetApplied) + } +} +#[doc = "Source Minor Loop Offset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Smloe { + #[doc = "0: Minor loop offset not applied to SADDR"] + OffsetNotApplied = 0, + #[doc = "1: Minor loop offset applied to SADDR"] + OffsetApplied = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Smloe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SMLOE` reader - Source Minor Loop Offset Enable"] +pub type SmloeR = crate::BitReader; +impl SmloeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Smloe { + match self.bits { + false => Smloe::OffsetNotApplied, + true => Smloe::OffsetApplied, + } + } + #[doc = "Minor loop offset not applied to SADDR"] + #[inline(always)] + pub fn is_offset_not_applied(&self) -> bool { + *self == Smloe::OffsetNotApplied + } + #[doc = "Minor loop offset applied to SADDR"] + #[inline(always)] + pub fn is_offset_applied(&self) -> bool { + *self == Smloe::OffsetApplied + } +} +#[doc = "Field `SMLOE` writer - Source Minor Loop Offset Enable"] +pub type SmloeW<'a, REG> = crate::BitWriter<'a, REG, Smloe>; +impl<'a, REG> SmloeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Minor loop offset not applied to SADDR"] + #[inline(always)] + pub fn offset_not_applied(self) -> &'a mut crate::W { + self.variant(Smloe::OffsetNotApplied) + } + #[doc = "Minor loop offset applied to SADDR"] + #[inline(always)] + pub fn offset_applied(self) -> &'a mut crate::W { + self.variant(Smloe::OffsetApplied) + } +} +impl R { + #[doc = "Bits 0:29 - Number of Bytes To Transfer Per Service Request"] + #[inline(always)] + pub fn nbytes(&self) -> NbytesR { + NbytesR::new(self.bits & 0x3fff_ffff) + } + #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] + #[inline(always)] + pub fn dmloe(&self) -> DmloeR { + DmloeR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Source Minor Loop Offset Enable"] + #[inline(always)] + pub fn smloe(&self) -> SmloeR { + SmloeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:29 - Number of Bytes To Transfer Per Service Request"] + #[inline(always)] + pub fn nbytes(&mut self) -> NbytesW { + NbytesW::new(self, 0) + } + #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] + #[inline(always)] + pub fn dmloe(&mut self) -> DmloeW { + DmloeW::new(self, 30) + } + #[doc = "Bit 31 - Source Minor Loop Offset Enable"] + #[inline(always)] + pub fn smloe(&mut self) -> SmloeW { + SmloeW::new(self, 31) + } +} +#[doc = "TCD Transfer Size Without Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffno_tcd_nbytes_mloffno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffno_tcd_nbytes_mloffno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MloffnoTcdNbytesMloffnoSpec; +impl crate::RegisterSpec for MloffnoTcdNbytesMloffnoSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mloffno_tcd_nbytes_mloffno::R`](R) reader structure"] +impl crate::Readable for MloffnoTcdNbytesMloffnoSpec {} +#[doc = "`write(|w| ..)` method takes [`mloffno_tcd_nbytes_mloffno::W`](W) writer structure"] +impl crate::Writable for MloffnoTcdNbytesMloffnoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_NBYTES_MLOFFNO to value 0"] +impl crate::Resettable for MloffnoTcdNbytesMloffnoSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/mloffyes_tcd_nbytes_mloffyes.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/mloffyes_tcd_nbytes_mloffyes.rs new file mode 100644 index 000000000..971b10f7f --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/mloffyes_tcd_nbytes_mloffyes.rs @@ -0,0 +1,175 @@ +#[doc = "Register `TCD_NBYTES_MLOFFYES` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_NBYTES_MLOFFYES` writer"] +pub type W = crate::W; +#[doc = "Field `NBYTES` reader - Number of Bytes To Transfer Per Service Request"] +pub type NbytesR = crate::FieldReader; +#[doc = "Field `NBYTES` writer - Number of Bytes To Transfer Per Service Request"] +pub type NbytesW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `MLOFF` reader - Minor Loop Offset"] +pub type MloffR = crate::FieldReader; +#[doc = "Field `MLOFF` writer - Minor Loop Offset"] +pub type MloffW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Destination Minor Loop Offset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmloe { + #[doc = "0: Minor loop offset not applied to DADDR"] + OffsetNotApplied = 0, + #[doc = "1: Minor loop offset applied to DADDR"] + OffsetApplied = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmloe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMLOE` reader - Destination Minor Loop Offset Enable"] +pub type DmloeR = crate::BitReader; +impl DmloeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmloe { + match self.bits { + false => Dmloe::OffsetNotApplied, + true => Dmloe::OffsetApplied, + } + } + #[doc = "Minor loop offset not applied to DADDR"] + #[inline(always)] + pub fn is_offset_not_applied(&self) -> bool { + *self == Dmloe::OffsetNotApplied + } + #[doc = "Minor loop offset applied to DADDR"] + #[inline(always)] + pub fn is_offset_applied(&self) -> bool { + *self == Dmloe::OffsetApplied + } +} +#[doc = "Field `DMLOE` writer - Destination Minor Loop Offset Enable"] +pub type DmloeW<'a, REG> = crate::BitWriter<'a, REG, Dmloe>; +impl<'a, REG> DmloeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Minor loop offset not applied to DADDR"] + #[inline(always)] + pub fn offset_not_applied(self) -> &'a mut crate::W { + self.variant(Dmloe::OffsetNotApplied) + } + #[doc = "Minor loop offset applied to DADDR"] + #[inline(always)] + pub fn offset_applied(self) -> &'a mut crate::W { + self.variant(Dmloe::OffsetApplied) + } +} +#[doc = "Source Minor Loop Offset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Smloe { + #[doc = "0: Minor loop offset not applied to SADDR"] + OffsetNotApplied = 0, + #[doc = "1: Minor loop offset applied to SADDR"] + OffsetApplied = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Smloe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SMLOE` reader - Source Minor Loop Offset Enable"] +pub type SmloeR = crate::BitReader; +impl SmloeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Smloe { + match self.bits { + false => Smloe::OffsetNotApplied, + true => Smloe::OffsetApplied, + } + } + #[doc = "Minor loop offset not applied to SADDR"] + #[inline(always)] + pub fn is_offset_not_applied(&self) -> bool { + *self == Smloe::OffsetNotApplied + } + #[doc = "Minor loop offset applied to SADDR"] + #[inline(always)] + pub fn is_offset_applied(&self) -> bool { + *self == Smloe::OffsetApplied + } +} +#[doc = "Field `SMLOE` writer - Source Minor Loop Offset Enable"] +pub type SmloeW<'a, REG> = crate::BitWriter<'a, REG, Smloe>; +impl<'a, REG> SmloeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Minor loop offset not applied to SADDR"] + #[inline(always)] + pub fn offset_not_applied(self) -> &'a mut crate::W { + self.variant(Smloe::OffsetNotApplied) + } + #[doc = "Minor loop offset applied to SADDR"] + #[inline(always)] + pub fn offset_applied(self) -> &'a mut crate::W { + self.variant(Smloe::OffsetApplied) + } +} +impl R { + #[doc = "Bits 0:9 - Number of Bytes To Transfer Per Service Request"] + #[inline(always)] + pub fn nbytes(&self) -> NbytesR { + NbytesR::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:29 - Minor Loop Offset"] + #[inline(always)] + pub fn mloff(&self) -> MloffR { + MloffR::new((self.bits >> 10) & 0x000f_ffff) + } + #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] + #[inline(always)] + pub fn dmloe(&self) -> DmloeR { + DmloeR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Source Minor Loop Offset Enable"] + #[inline(always)] + pub fn smloe(&self) -> SmloeR { + SmloeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:9 - Number of Bytes To Transfer Per Service Request"] + #[inline(always)] + pub fn nbytes(&mut self) -> NbytesW { + NbytesW::new(self, 0) + } + #[doc = "Bits 10:29 - Minor Loop Offset"] + #[inline(always)] + pub fn mloff(&mut self) -> MloffW { + MloffW::new(self, 10) + } + #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] + #[inline(always)] + pub fn dmloe(&mut self) -> DmloeW { + DmloeW::new(self, 30) + } + #[doc = "Bit 31 - Source Minor Loop Offset Enable"] + #[inline(always)] + pub fn smloe(&mut self) -> SmloeW { + SmloeW::new(self, 31) + } +} +#[doc = "TCD Transfer Size with Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffyes_tcd_nbytes_mloffyes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffyes_tcd_nbytes_mloffyes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MloffyesTcdNbytesMloffyesSpec; +impl crate::RegisterSpec for MloffyesTcdNbytesMloffyesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mloffyes_tcd_nbytes_mloffyes::R`](R) reader structure"] +impl crate::Readable for MloffyesTcdNbytesMloffyesSpec {} +#[doc = "`write(|w| ..)` method takes [`mloffyes_tcd_nbytes_mloffyes::W`](W) writer structure"] +impl crate::Writable for MloffyesTcdNbytesMloffyesSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_NBYTES_MLOFFYES to value 0"] +impl crate::Resettable for MloffyesTcdNbytesMloffyesSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs new file mode 100644 index 000000000..5a7921095 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs @@ -0,0 +1,241 @@ +#[doc = "Register `TCD_ATTR` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_ATTR` writer"] +pub type W = crate::W; +#[doc = "Field `DSIZE` reader - Destination Data Transfer Size"] +pub type DsizeR = crate::FieldReader; +#[doc = "Field `DSIZE` writer - Destination Data Transfer Size"] +pub type DsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DMOD` reader - Destination Address Modulo"] +pub type DmodR = crate::FieldReader; +#[doc = "Field `DMOD` writer - Destination Address Modulo"] +pub type DmodW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Source Data Transfer Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ssize { + #[doc = "0: 8-bit"] + EightBit = 0, + #[doc = "1: 16-bit"] + SixteenBit = 1, + #[doc = "2: 32-bit"] + ThirtytwoBit = 2, + #[doc = "3: 64-bit"] + SixtyfourBit = 3, + #[doc = "4: 16-byte"] + SixteenByte = 4, + #[doc = "5: 32-byte"] + ThirtytwoByte = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ssize) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ssize { + type Ux = u8; +} +impl crate::IsEnum for Ssize {} +#[doc = "Field `SSIZE` reader - Source Data Transfer Size"] +pub type SsizeR = crate::FieldReader; +impl SsizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ssize::EightBit), + 1 => Some(Ssize::SixteenBit), + 2 => Some(Ssize::ThirtytwoBit), + 3 => Some(Ssize::SixtyfourBit), + 4 => Some(Ssize::SixteenByte), + 5 => Some(Ssize::ThirtytwoByte), + _ => None, + } + } + #[doc = "8-bit"] + #[inline(always)] + pub fn is_eight_bit(&self) -> bool { + *self == Ssize::EightBit + } + #[doc = "16-bit"] + #[inline(always)] + pub fn is_sixteen_bit(&self) -> bool { + *self == Ssize::SixteenBit + } + #[doc = "32-bit"] + #[inline(always)] + pub fn is_thirtytwo_bit(&self) -> bool { + *self == Ssize::ThirtytwoBit + } + #[doc = "64-bit"] + #[inline(always)] + pub fn is_sixtyfour_bit(&self) -> bool { + *self == Ssize::SixtyfourBit + } + #[doc = "16-byte"] + #[inline(always)] + pub fn is_sixteen_byte(&self) -> bool { + *self == Ssize::SixteenByte + } + #[doc = "32-byte"] + #[inline(always)] + pub fn is_thirtytwo_byte(&self) -> bool { + *self == Ssize::ThirtytwoByte + } +} +#[doc = "Field `SSIZE` writer - Source Data Transfer Size"] +pub type SsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Ssize>; +impl<'a, REG> SsizeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "8-bit"] + #[inline(always)] + pub fn eight_bit(self) -> &'a mut crate::W { + self.variant(Ssize::EightBit) + } + #[doc = "16-bit"] + #[inline(always)] + pub fn sixteen_bit(self) -> &'a mut crate::W { + self.variant(Ssize::SixteenBit) + } + #[doc = "32-bit"] + #[inline(always)] + pub fn thirtytwo_bit(self) -> &'a mut crate::W { + self.variant(Ssize::ThirtytwoBit) + } + #[doc = "64-bit"] + #[inline(always)] + pub fn sixtyfour_bit(self) -> &'a mut crate::W { + self.variant(Ssize::SixtyfourBit) + } + #[doc = "16-byte"] + #[inline(always)] + pub fn sixteen_byte(self) -> &'a mut crate::W { + self.variant(Ssize::SixteenByte) + } + #[doc = "32-byte"] + #[inline(always)] + pub fn thirtytwo_byte(self) -> &'a mut crate::W { + self.variant(Ssize::ThirtytwoByte) + } +} +#[doc = "Source Address Modulo\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Smod { + #[doc = "0: Source address modulo feature disabled"] + Disable = 0, + #[doc = "1: Source address modulo feature enabled for any non-zero value \\[1-31\\]"] + Enable = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Smod) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Smod { + type Ux = u8; +} +impl crate::IsEnum for Smod {} +#[doc = "Field `SMOD` reader - Source Address Modulo"] +pub type SmodR = crate::FieldReader; +impl SmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Smod::Disable), + 1 => Some(Smod::Enable), + _ => None, + } + } + #[doc = "Source address modulo feature disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Smod::Disable + } + #[doc = "Source address modulo feature enabled for any non-zero value \\[1-31\\]"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Smod::Enable + } +} +#[doc = "Field `SMOD` writer - Source Address Modulo"] +pub type SmodW<'a, REG> = crate::FieldWriter<'a, REG, 5, Smod>; +impl<'a, REG> SmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Source address modulo feature disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Smod::Disable) + } + #[doc = "Source address modulo feature enabled for any non-zero value \\[1-31\\]"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Smod::Enable) + } +} +impl R { + #[doc = "Bits 0:2 - Destination Data Transfer Size"] + #[inline(always)] + pub fn dsize(&self) -> DsizeR { + DsizeR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:7 - Destination Address Modulo"] + #[inline(always)] + pub fn dmod(&self) -> DmodR { + DmodR::new(((self.bits >> 3) & 0x1f) as u8) + } + #[doc = "Bits 8:10 - Source Data Transfer Size"] + #[inline(always)] + pub fn ssize(&self) -> SsizeR { + SsizeR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 11:15 - Source Address Modulo"] + #[inline(always)] + pub fn smod(&self) -> SmodR { + SmodR::new(((self.bits >> 11) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Destination Data Transfer Size"] + #[inline(always)] + pub fn dsize(&mut self) -> DsizeW { + DsizeW::new(self, 0) + } + #[doc = "Bits 3:7 - Destination Address Modulo"] + #[inline(always)] + pub fn dmod(&mut self) -> DmodW { + DmodW::new(self, 3) + } + #[doc = "Bits 8:10 - Source Data Transfer Size"] + #[inline(always)] + pub fn ssize(&mut self) -> SsizeW { + SsizeW::new(self, 8) + } + #[doc = "Bits 11:15 - Source Address Modulo"] + #[inline(always)] + pub fn smod(&mut self) -> SmodW { + SmodW::new(self, 11) + } +} +#[doc = "TCD Transfer Attributes\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdAttrSpec; +impl crate::RegisterSpec for TcdAttrSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`tcd_attr::R`](R) reader structure"] +impl crate::Readable for TcdAttrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_attr::W`](W) writer structure"] +impl crate::Writable for TcdAttrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_ATTR to value 0"] +impl crate::Resettable for TcdAttrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs new file mode 100644 index 000000000..e08414837 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs @@ -0,0 +1,622 @@ +#[doc = "Register `TCD_CSR` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_CSR` writer"] +pub type W = crate::W; +#[doc = "Channel Start\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Start { + #[doc = "0: Channel not explicitly started"] + ChannelNotStarted = 0, + #[doc = "1: Channel explicitly started via a software-initiated service request"] + ChannelStarted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Start) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `START` reader - Channel Start"] +pub type StartR = crate::BitReader; +impl StartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Start { + match self.bits { + false => Start::ChannelNotStarted, + true => Start::ChannelStarted, + } + } + #[doc = "Channel not explicitly started"] + #[inline(always)] + pub fn is_channel_not_started(&self) -> bool { + *self == Start::ChannelNotStarted + } + #[doc = "Channel explicitly started via a software-initiated service request"] + #[inline(always)] + pub fn is_channel_started(&self) -> bool { + *self == Start::ChannelStarted + } +} +#[doc = "Field `START` writer - Channel Start"] +pub type StartW<'a, REG> = crate::BitWriter<'a, REG, Start>; +impl<'a, REG> StartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel not explicitly started"] + #[inline(always)] + pub fn channel_not_started(self) -> &'a mut crate::W { + self.variant(Start::ChannelNotStarted) + } + #[doc = "Channel explicitly started via a software-initiated service request"] + #[inline(always)] + pub fn channel_started(self) -> &'a mut crate::W { + self.variant(Start::ChannelStarted) + } +} +#[doc = "Enable Interrupt If Major count complete\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Intmajor { + #[doc = "0: End-of-major loop interrupt disabled"] + Disable = 0, + #[doc = "1: End-of-major loop interrupt enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Intmajor) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTMAJOR` reader - Enable Interrupt If Major count complete"] +pub type IntmajorR = crate::BitReader; +impl IntmajorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Intmajor { + match self.bits { + false => Intmajor::Disable, + true => Intmajor::Enable, + } + } + #[doc = "End-of-major loop interrupt disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Intmajor::Disable + } + #[doc = "End-of-major loop interrupt enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Intmajor::Enable + } +} +#[doc = "Field `INTMAJOR` writer - Enable Interrupt If Major count complete"] +pub type IntmajorW<'a, REG> = crate::BitWriter<'a, REG, Intmajor>; +impl<'a, REG> IntmajorW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "End-of-major loop interrupt disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Intmajor::Disable) + } + #[doc = "End-of-major loop interrupt enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Intmajor::Enable) + } +} +#[doc = "Enable Interrupt If Major Counter Half-complete\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inthalf { + #[doc = "0: Halfway point interrupt disabled"] + Disable = 0, + #[doc = "1: Halfway point interrupt enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inthalf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTHALF` reader - Enable Interrupt If Major Counter Half-complete"] +pub type InthalfR = crate::BitReader; +impl InthalfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inthalf { + match self.bits { + false => Inthalf::Disable, + true => Inthalf::Enable, + } + } + #[doc = "Halfway point interrupt disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Inthalf::Disable + } + #[doc = "Halfway point interrupt enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Inthalf::Enable + } +} +#[doc = "Field `INTHALF` writer - Enable Interrupt If Major Counter Half-complete"] +pub type InthalfW<'a, REG> = crate::BitWriter<'a, REG, Inthalf>; +impl<'a, REG> InthalfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Halfway point interrupt disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Inthalf::Disable) + } + #[doc = "Halfway point interrupt enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Inthalf::Enable) + } +} +#[doc = "Disable Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dreq { + #[doc = "0: No operation"] + ChannelNotAffected = 0, + #[doc = "1: Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"] + ErqFieldClear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dreq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DREQ` reader - Disable Request"] +pub type DreqR = crate::BitReader; +impl DreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dreq { + match self.bits { + false => Dreq::ChannelNotAffected, + true => Dreq::ErqFieldClear, + } + } + #[doc = "No operation"] + #[inline(always)] + pub fn is_channel_not_affected(&self) -> bool { + *self == Dreq::ChannelNotAffected + } + #[doc = "Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"] + #[inline(always)] + pub fn is_erq_field_clear(&self) -> bool { + *self == Dreq::ErqFieldClear + } +} +#[doc = "Field `DREQ` writer - Disable Request"] +pub type DreqW<'a, REG> = crate::BitWriter<'a, REG, Dreq>; +impl<'a, REG> DreqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No operation"] + #[inline(always)] + pub fn channel_not_affected(self) -> &'a mut crate::W { + self.variant(Dreq::ChannelNotAffected) + } + #[doc = "Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"] + #[inline(always)] + pub fn erq_field_clear(self) -> &'a mut crate::W { + self.variant(Dreq::ErqFieldClear) + } +} +#[doc = "Enable Scatter/Gather Processing\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Esg { + #[doc = "0: Current channel's TCD is normal format"] + NormalFormat = 0, + #[doc = "1: Current channel's TCD specifies scatter/gather format."] + ScatterGatherFormat = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Esg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ESG` reader - Enable Scatter/Gather Processing"] +pub type EsgR = crate::BitReader; +impl EsgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Esg { + match self.bits { + false => Esg::NormalFormat, + true => Esg::ScatterGatherFormat, + } + } + #[doc = "Current channel's TCD is normal format"] + #[inline(always)] + pub fn is_normal_format(&self) -> bool { + *self == Esg::NormalFormat + } + #[doc = "Current channel's TCD specifies scatter/gather format."] + #[inline(always)] + pub fn is_scatter_gather_format(&self) -> bool { + *self == Esg::ScatterGatherFormat + } +} +#[doc = "Field `ESG` writer - Enable Scatter/Gather Processing"] +pub type EsgW<'a, REG> = crate::BitWriter<'a, REG, Esg>; +impl<'a, REG> EsgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Current channel's TCD is normal format"] + #[inline(always)] + pub fn normal_format(self) -> &'a mut crate::W { + self.variant(Esg::NormalFormat) + } + #[doc = "Current channel's TCD specifies scatter/gather format."] + #[inline(always)] + pub fn scatter_gather_format(self) -> &'a mut crate::W { + self.variant(Esg::ScatterGatherFormat) + } +} +#[doc = "Enable Link When Major Loop Complete\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Majorelink { + #[doc = "0: Channel-to-channel linking disabled"] + Disable = 0, + #[doc = "1: Channel-to-channel linking enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Majorelink) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MAJORELINK` reader - Enable Link When Major Loop Complete"] +pub type MajorelinkR = crate::BitReader; +impl MajorelinkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Majorelink { + match self.bits { + false => Majorelink::Disable, + true => Majorelink::Enable, + } + } + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Majorelink::Disable + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Majorelink::Enable + } +} +#[doc = "Field `MAJORELINK` writer - Enable Link When Major Loop Complete"] +pub type MajorelinkW<'a, REG> = crate::BitWriter<'a, REG, Majorelink>; +impl<'a, REG> MajorelinkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Channel-to-channel linking disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Majorelink::Disable) + } + #[doc = "Channel-to-channel linking enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Majorelink::Enable) + } +} +#[doc = "Enable End-Of-Packet Processing\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Eeop { + #[doc = "0: End-of-packet operation disabled"] + Disable = 0, + #[doc = "1: End-of-packet hardware input signal enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Eeop) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EEOP` reader - Enable End-Of-Packet Processing"] +pub type EeopR = crate::BitReader; +impl EeopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Eeop { + match self.bits { + false => Eeop::Disable, + true => Eeop::Enable, + } + } + #[doc = "End-of-packet operation disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Eeop::Disable + } + #[doc = "End-of-packet hardware input signal enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Eeop::Enable + } +} +#[doc = "Field `EEOP` writer - Enable End-Of-Packet Processing"] +pub type EeopW<'a, REG> = crate::BitWriter<'a, REG, Eeop>; +impl<'a, REG> EeopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "End-of-packet operation disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Eeop::Disable) + } + #[doc = "End-of-packet hardware input signal enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Eeop::Enable) + } +} +#[doc = "Enable Store Destination Address\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Esda { + #[doc = "0: Ability to store destination address to system memory disabled"] + Disable = 0, + #[doc = "1: Ability to store destination address to system memory enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Esda) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ESDA` reader - Enable Store Destination Address"] +pub type EsdaR = crate::BitReader; +impl EsdaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Esda { + match self.bits { + false => Esda::Disable, + true => Esda::Enable, + } + } + #[doc = "Ability to store destination address to system memory disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Esda::Disable + } + #[doc = "Ability to store destination address to system memory enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Esda::Enable + } +} +#[doc = "Field `ESDA` writer - Enable Store Destination Address"] +pub type EsdaW<'a, REG> = crate::BitWriter<'a, REG, Esda>; +impl<'a, REG> EsdaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Ability to store destination address to system memory disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Esda::Disable) + } + #[doc = "Ability to store destination address to system memory enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Esda::Enable) + } +} +#[doc = "Field `MAJORLINKCH` reader - Major Loop Link Channel Number"] +pub type MajorlinkchR = crate::FieldReader; +#[doc = "Field `MAJORLINKCH` writer - Major Loop Link Channel Number"] +pub type MajorlinkchW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Bandwidth Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Bwc { + #[doc = "0: No eDMA engine stalls"] + NoStall = 0, + #[doc = "2: eDMA engine stalls for 4 cycles after each R/W"] + EngineStallsFour = 2, + #[doc = "3: eDMA engine stalls for 8 cycles after each R/W"] + EngineStallsEight = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Bwc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Bwc { + type Ux = u8; +} +impl crate::IsEnum for Bwc {} +#[doc = "Field `BWC` reader - Bandwidth Control"] +pub type BwcR = crate::FieldReader; +impl BwcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Bwc::NoStall), + 2 => Some(Bwc::EngineStallsFour), + 3 => Some(Bwc::EngineStallsEight), + _ => None, + } + } + #[doc = "No eDMA engine stalls"] + #[inline(always)] + pub fn is_no_stall(&self) -> bool { + *self == Bwc::NoStall + } + #[doc = "eDMA engine stalls for 4 cycles after each R/W"] + #[inline(always)] + pub fn is_engine_stalls_four(&self) -> bool { + *self == Bwc::EngineStallsFour + } + #[doc = "eDMA engine stalls for 8 cycles after each R/W"] + #[inline(always)] + pub fn is_engine_stalls_eight(&self) -> bool { + *self == Bwc::EngineStallsEight + } +} +#[doc = "Field `BWC` writer - Bandwidth Control"] +pub type BwcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bwc>; +impl<'a, REG> BwcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No eDMA engine stalls"] + #[inline(always)] + pub fn no_stall(self) -> &'a mut crate::W { + self.variant(Bwc::NoStall) + } + #[doc = "eDMA engine stalls for 4 cycles after each R/W"] + #[inline(always)] + pub fn engine_stalls_four(self) -> &'a mut crate::W { + self.variant(Bwc::EngineStallsFour) + } + #[doc = "eDMA engine stalls for 8 cycles after each R/W"] + #[inline(always)] + pub fn engine_stalls_eight(self) -> &'a mut crate::W { + self.variant(Bwc::EngineStallsEight) + } +} +impl R { + #[doc = "Bit 0 - Channel Start"] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Interrupt If Major count complete"] + #[inline(always)] + pub fn intmajor(&self) -> IntmajorR { + IntmajorR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable Interrupt If Major Counter Half-complete"] + #[inline(always)] + pub fn inthalf(&self) -> InthalfR { + InthalfR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Disable Request"] + #[inline(always)] + pub fn dreq(&self) -> DreqR { + DreqR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable Scatter/Gather Processing"] + #[inline(always)] + pub fn esg(&self) -> EsgR { + EsgR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable Link When Major Loop Complete"] + #[inline(always)] + pub fn majorelink(&self) -> MajorelinkR { + MajorelinkR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable End-Of-Packet Processing"] + #[inline(always)] + pub fn eeop(&self) -> EeopR { + EeopR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable Store Destination Address"] + #[inline(always)] + pub fn esda(&self) -> EsdaR { + EsdaR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Major Loop Link Channel Number"] + #[inline(always)] + pub fn majorlinkch(&self) -> MajorlinkchR { + MajorlinkchR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 14:15 - Bandwidth Control"] + #[inline(always)] + pub fn bwc(&self) -> BwcR { + BwcR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Channel Start"] + #[inline(always)] + pub fn start(&mut self) -> StartW { + StartW::new(self, 0) + } + #[doc = "Bit 1 - Enable Interrupt If Major count complete"] + #[inline(always)] + pub fn intmajor(&mut self) -> IntmajorW { + IntmajorW::new(self, 1) + } + #[doc = "Bit 2 - Enable Interrupt If Major Counter Half-complete"] + #[inline(always)] + pub fn inthalf(&mut self) -> InthalfW { + InthalfW::new(self, 2) + } + #[doc = "Bit 3 - Disable Request"] + #[inline(always)] + pub fn dreq(&mut self) -> DreqW { + DreqW::new(self, 3) + } + #[doc = "Bit 4 - Enable Scatter/Gather Processing"] + #[inline(always)] + pub fn esg(&mut self) -> EsgW { + EsgW::new(self, 4) + } + #[doc = "Bit 5 - Enable Link When Major Loop Complete"] + #[inline(always)] + pub fn majorelink(&mut self) -> MajorelinkW { + MajorelinkW::new(self, 5) + } + #[doc = "Bit 6 - Enable End-Of-Packet Processing"] + #[inline(always)] + pub fn eeop(&mut self) -> EeopW { + EeopW::new(self, 6) + } + #[doc = "Bit 7 - Enable Store Destination Address"] + #[inline(always)] + pub fn esda(&mut self) -> EsdaW { + EsdaW::new(self, 7) + } + #[doc = "Bits 8:10 - Major Loop Link Channel Number"] + #[inline(always)] + pub fn majorlinkch(&mut self) -> MajorlinkchW { + MajorlinkchW::new(self, 8) + } + #[doc = "Bits 14:15 - Bandwidth Control"] + #[inline(always)] + pub fn bwc(&mut self) -> BwcW { + BwcW::new(self, 14) + } +} +#[doc = "TCD Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdCsrSpec; +impl crate::RegisterSpec for TcdCsrSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`tcd_csr::R`](R) reader structure"] +impl crate::Readable for TcdCsrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_csr::W`](W) writer structure"] +impl crate::Writable for TcdCsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_CSR to value 0"] +impl crate::Resettable for TcdCsrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs new file mode 100644 index 000000000..49bd118ff --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TCD_DADDR` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_DADDR` writer"] +pub type W = crate::W; +#[doc = "Field `DADDR` reader - Destination Address"] +pub type DaddrR = crate::FieldReader; +#[doc = "Field `DADDR` writer - Destination Address"] +pub type DaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Destination Address"] + #[inline(always)] + pub fn daddr(&self) -> DaddrR { + DaddrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Destination Address"] + #[inline(always)] + pub fn daddr(&mut self) -> DaddrW { + DaddrW::new(self, 0) + } +} +#[doc = "TCD Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_daddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_daddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdDaddrSpec; +impl crate::RegisterSpec for TcdDaddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcd_daddr::R`](R) reader structure"] +impl crate::Readable for TcdDaddrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_daddr::W`](W) writer structure"] +impl crate::Writable for TcdDaddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_DADDR to value 0"] +impl crate::Resettable for TcdDaddrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs new file mode 100644 index 000000000..f7fd4fac8 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TCD_DLAST_SGA` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_DLAST_SGA` writer"] +pub type W = crate::W; +#[doc = "Field `DLAST_SGA` reader - Last Destination Address Adjustment / Scatter Gather Address"] +pub type DlastSgaR = crate::FieldReader; +#[doc = "Field `DLAST_SGA` writer - Last Destination Address Adjustment / Scatter Gather Address"] +pub type DlastSgaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Last Destination Address Adjustment / Scatter Gather Address"] + #[inline(always)] + pub fn dlast_sga(&self) -> DlastSgaR { + DlastSgaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Last Destination Address Adjustment / Scatter Gather Address"] + #[inline(always)] + pub fn dlast_sga(&mut self) -> DlastSgaW { + DlastSgaW::new(self, 0) + } +} +#[doc = "TCD Last Destination Address Adjustment / Scatter Gather Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_dlast_sga::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_dlast_sga::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdDlastSgaSpec; +impl crate::RegisterSpec for TcdDlastSgaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcd_dlast_sga::R`](R) reader structure"] +impl crate::Readable for TcdDlastSgaSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_dlast_sga::W`](W) writer structure"] +impl crate::Writable for TcdDlastSgaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_DLAST_SGA to value 0"] +impl crate::Resettable for TcdDlastSgaSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs new file mode 100644 index 000000000..a7206017c --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TCD_DOFF` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_DOFF` writer"] +pub type W = crate::W; +#[doc = "Field `DOFF` reader - Destination Address Signed Offset"] +pub type DoffR = crate::FieldReader; +#[doc = "Field `DOFF` writer - Destination Address Signed Offset"] +pub type DoffW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Destination Address Signed Offset"] + #[inline(always)] + pub fn doff(&self) -> DoffR { + DoffR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Destination Address Signed Offset"] + #[inline(always)] + pub fn doff(&mut self) -> DoffW { + DoffW::new(self, 0) + } +} +#[doc = "TCD Signed Destination Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_doff::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_doff::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdDoffSpec; +impl crate::RegisterSpec for TcdDoffSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`tcd_doff::R`](R) reader structure"] +impl crate::Readable for TcdDoffSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_doff::W`](W) writer structure"] +impl crate::Writable for TcdDoffSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_DOFF to value 0"] +impl crate::Resettable for TcdDoffSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs new file mode 100644 index 000000000..855a38687 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TCD_SADDR` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_SADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SADDR` reader - Source Address"] +pub type SaddrR = crate::FieldReader; +#[doc = "Field `SADDR` writer - Source Address"] +pub type SaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Source Address"] + #[inline(always)] + pub fn saddr(&self) -> SaddrR { + SaddrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Source Address"] + #[inline(always)] + pub fn saddr(&mut self) -> SaddrW { + SaddrW::new(self, 0) + } +} +#[doc = "TCD Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_saddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_saddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdSaddrSpec; +impl crate::RegisterSpec for TcdSaddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcd_saddr::R`](R) reader structure"] +impl crate::Readable for TcdSaddrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_saddr::W`](W) writer structure"] +impl crate::Writable for TcdSaddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_SADDR to value 0"] +impl crate::Resettable for TcdSaddrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs new file mode 100644 index 000000000..7d1b33587 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TCD_SLAST_SDA` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_SLAST_SDA` writer"] +pub type W = crate::W; +#[doc = "Field `SLAST_SDA` reader - Last Source Address Adjustment / Store DADDR Address"] +pub type SlastSdaR = crate::FieldReader; +#[doc = "Field `SLAST_SDA` writer - Last Source Address Adjustment / Store DADDR Address"] +pub type SlastSdaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Last Source Address Adjustment / Store DADDR Address"] + #[inline(always)] + pub fn slast_sda(&self) -> SlastSdaR { + SlastSdaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Last Source Address Adjustment / Store DADDR Address"] + #[inline(always)] + pub fn slast_sda(&mut self) -> SlastSdaW { + SlastSdaW::new(self, 0) + } +} +#[doc = "TCD Last Source Address Adjustment / Store DADDR Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_slast_sda::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_slast_sda::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdSlastSdaSpec; +impl crate::RegisterSpec for TcdSlastSdaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcd_slast_sda::R`](R) reader structure"] +impl crate::Readable for TcdSlastSdaSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_slast_sda::W`](W) writer structure"] +impl crate::Writable for TcdSlastSdaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_SLAST_SDA to value 0"] +impl crate::Resettable for TcdSlastSdaSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs new file mode 100644 index 000000000..a202598d1 --- /dev/null +++ b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TCD_SOFF` reader"] +pub type R = crate::R; +#[doc = "Register `TCD_SOFF` writer"] +pub type W = crate::W; +#[doc = "Field `SOFF` reader - Source Address Signed Offset"] +pub type SoffR = crate::FieldReader; +#[doc = "Field `SOFF` writer - Source Address Signed Offset"] +pub type SoffW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Source Address Signed Offset"] + #[inline(always)] + pub fn soff(&self) -> SoffR { + SoffR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Source Address Signed Offset"] + #[inline(always)] + pub fn soff(&mut self) -> SoffW { + SoffW::new(self, 0) + } +} +#[doc = "TCD Signed Source Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_soff::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_soff::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcdSoffSpec; +impl crate::RegisterSpec for TcdSoffSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`tcd_soff::R`](R) reader structure"] +impl crate::Readable for TcdSoffSpec {} +#[doc = "`write(|w| ..)` method takes [`tcd_soff::W`](W) writer structure"] +impl crate::Writable for TcdSoffSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCD_SOFF to value 0"] +impl crate::Resettable for TcdSoffSpec {} diff --git a/mcxa276-pac/src/eim0.rs b/mcxa276-pac/src/eim0.rs new file mode 100644 index 000000000..ed857f2b0 --- /dev/null +++ b/mcxa276-pac/src/eim0.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + eimcr: Eimcr, + eichen: Eichen, + _reserved2: [u8; 0xf8], + eichd0_word0: Eichd0Word0, + eichd0_word1: Eichd0Word1, +} +impl RegisterBlock { + #[doc = "0x00 - Error Injection Module Configuration Register"] + #[inline(always)] + pub const fn eimcr(&self) -> &Eimcr { + &self.eimcr + } + #[doc = "0x04 - Error Injection Channel Enable register"] + #[inline(always)] + pub const fn eichen(&self) -> &Eichen { + &self.eichen + } + #[doc = "0x100 - Error Injection Channel Descriptor 0, Word0"] + #[inline(always)] + pub const fn eichd0_word0(&self) -> &Eichd0Word0 { + &self.eichd0_word0 + } + #[doc = "0x104 - Error Injection Channel Descriptor 0, Word1"] + #[inline(always)] + pub const fn eichd0_word1(&self) -> &Eichd0Word1 { + &self.eichd0_word1 + } +} +#[doc = "EIMCR (rw) register accessor: Error Injection Module Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eimcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eimcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eimcr`] module"] +#[doc(alias = "EIMCR")] +pub type Eimcr = crate::Reg; +#[doc = "Error Injection Module Configuration Register"] +pub mod eimcr; +#[doc = "EICHEN (rw) register accessor: Error Injection Channel Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`eichen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eichen`] module"] +#[doc(alias = "EICHEN")] +pub type Eichen = crate::Reg; +#[doc = "Error Injection Channel Enable register"] +pub mod eichen; +#[doc = "EICHD0_WORD0 (rw) register accessor: Error Injection Channel Descriptor 0, Word0\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eichd0_word0`] module"] +#[doc(alias = "EICHD0_WORD0")] +pub type Eichd0Word0 = crate::Reg; +#[doc = "Error Injection Channel Descriptor 0, Word0"] +pub mod eichd0_word0; +#[doc = "EICHD0_WORD1 (rw) register accessor: Error Injection Channel Descriptor 0, Word1\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eichd0_word1`] module"] +#[doc(alias = "EICHD0_WORD1")] +pub type Eichd0Word1 = crate::Reg; +#[doc = "Error Injection Channel Descriptor 0, Word1"] +pub mod eichd0_word1; diff --git a/mcxa276-pac/src/eim0/eichd0_word0.rs b/mcxa276-pac/src/eim0/eichd0_word0.rs new file mode 100644 index 000000000..0dfe456fa --- /dev/null +++ b/mcxa276-pac/src/eim0/eichd0_word0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EICHD0_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `EICHD0_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `CHKBIT_MASK` reader - Checkbit Mask"] +pub type ChkbitMaskR = crate::FieldReader; +#[doc = "Field `CHKBIT_MASK` writer - Checkbit Mask"] +pub type ChkbitMaskW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 25:31 - Checkbit Mask"] + #[inline(always)] + pub fn chkbit_mask(&self) -> ChkbitMaskR { + ChkbitMaskR::new(((self.bits >> 25) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 25:31 - Checkbit Mask"] + #[inline(always)] + pub fn chkbit_mask(&mut self) -> ChkbitMaskW { + ChkbitMaskW::new(self, 25) + } +} +#[doc = "Error Injection Channel Descriptor 0, Word0\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Eichd0Word0Spec; +impl crate::RegisterSpec for Eichd0Word0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`eichd0_word0::R`](R) reader structure"] +impl crate::Readable for Eichd0Word0Spec {} +#[doc = "`write(|w| ..)` method takes [`eichd0_word0::W`](W) writer structure"] +impl crate::Writable for Eichd0Word0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EICHD0_WORD0 to value 0"] +impl crate::Resettable for Eichd0Word0Spec {} diff --git a/mcxa276-pac/src/eim0/eichd0_word1.rs b/mcxa276-pac/src/eim0/eichd0_word1.rs new file mode 100644 index 000000000..dd14d3c4e --- /dev/null +++ b/mcxa276-pac/src/eim0/eichd0_word1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EICHD0_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `EICHD0_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `B0_3DATA_MASK` reader - Data Mask Bytes 0-3"] +pub type B0_3dataMaskR = crate::FieldReader; +#[doc = "Field `B0_3DATA_MASK` writer - Data Mask Bytes 0-3"] +pub type B0_3dataMaskW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data Mask Bytes 0-3"] + #[inline(always)] + pub fn b0_3data_mask(&self) -> B0_3dataMaskR { + B0_3dataMaskR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data Mask Bytes 0-3"] + #[inline(always)] + pub fn b0_3data_mask(&mut self) -> B0_3dataMaskW { + B0_3dataMaskW::new(self, 0) + } +} +#[doc = "Error Injection Channel Descriptor 0, Word1\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Eichd0Word1Spec; +impl crate::RegisterSpec for Eichd0Word1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`eichd0_word1::R`](R) reader structure"] +impl crate::Readable for Eichd0Word1Spec {} +#[doc = "`write(|w| ..)` method takes [`eichd0_word1::W`](W) writer structure"] +impl crate::Writable for Eichd0Word1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EICHD0_WORD1 to value 0"] +impl crate::Resettable for Eichd0Word1Spec {} diff --git a/mcxa276-pac/src/eim0/eichen.rs b/mcxa276-pac/src/eim0/eichen.rs new file mode 100644 index 000000000..21daadd2b --- /dev/null +++ b/mcxa276-pac/src/eim0/eichen.rs @@ -0,0 +1,84 @@ +#[doc = "Register `EICHEN` reader"] +pub type R = crate::R; +#[doc = "Register `EICHEN` writer"] +pub type W = crate::W; +#[doc = "Error Injection Channel 0 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Eich0en { + #[doc = "0: Error injection is disabled on Error Injection Channel 0"] + Disable = 0, + #[doc = "1: Error injection is enabled on Error Injection Channel 0"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Eich0en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EICH0EN` reader - Error Injection Channel 0 Enable"] +pub type Eich0enR = crate::BitReader; +impl Eich0enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Eich0en { + match self.bits { + false => Eich0en::Disable, + true => Eich0en::Enable, + } + } + #[doc = "Error injection is disabled on Error Injection Channel 0"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Eich0en::Disable + } + #[doc = "Error injection is enabled on Error Injection Channel 0"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Eich0en::Enable + } +} +#[doc = "Field `EICH0EN` writer - Error Injection Channel 0 Enable"] +pub type Eich0enW<'a, REG> = crate::BitWriter<'a, REG, Eich0en>; +impl<'a, REG> Eich0enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error injection is disabled on Error Injection Channel 0"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Eich0en::Disable) + } + #[doc = "Error injection is enabled on Error Injection Channel 0"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Eich0en::Enable) + } +} +impl R { + #[doc = "Bit 31 - Error Injection Channel 0 Enable"] + #[inline(always)] + pub fn eich0en(&self) -> Eich0enR { + Eich0enR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 31 - Error Injection Channel 0 Enable"] + #[inline(always)] + pub fn eich0en(&mut self) -> Eich0enW { + Eich0enW::new(self, 31) + } +} +#[doc = "Error Injection Channel Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`eichen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EichenSpec; +impl crate::RegisterSpec for EichenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`eichen::R`](R) reader structure"] +impl crate::Readable for EichenSpec {} +#[doc = "`write(|w| ..)` method takes [`eichen::W`](W) writer structure"] +impl crate::Writable for EichenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EICHEN to value 0"] +impl crate::Resettable for EichenSpec {} diff --git a/mcxa276-pac/src/eim0/eimcr.rs b/mcxa276-pac/src/eim0/eimcr.rs new file mode 100644 index 000000000..12e308c44 --- /dev/null +++ b/mcxa276-pac/src/eim0/eimcr.rs @@ -0,0 +1,84 @@ +#[doc = "Register `EIMCR` reader"] +pub type R = crate::R; +#[doc = "Register `EIMCR` writer"] +pub type W = crate::W; +#[doc = "Global Error Injection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Geien { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Geien) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GEIEN` reader - Global Error Injection Enable"] +pub type GeienR = crate::BitReader; +impl GeienR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Geien { + match self.bits { + false => Geien::Disable, + true => Geien::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Geien::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Geien::Enable + } +} +#[doc = "Field `GEIEN` writer - Global Error Injection Enable"] +pub type GeienW<'a, REG> = crate::BitWriter<'a, REG, Geien>; +impl<'a, REG> GeienW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Geien::Disable) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Geien::Enable) + } +} +impl R { + #[doc = "Bit 0 - Global Error Injection Enable"] + #[inline(always)] + pub fn geien(&self) -> GeienR { + GeienR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Global Error Injection Enable"] + #[inline(always)] + pub fn geien(&mut self) -> GeienW { + GeienW::new(self, 0) + } +} +#[doc = "Error Injection Module Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eimcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eimcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EimcrSpec; +impl crate::RegisterSpec for EimcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`eimcr::R`](R) reader structure"] +impl crate::Readable for EimcrSpec {} +#[doc = "`write(|w| ..)` method takes [`eimcr::W`](W) writer structure"] +impl crate::Writable for EimcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EIMCR to value 0"] +impl crate::Resettable for EimcrSpec {} diff --git a/mcxa276-pac/src/eqdc0.rs b/mcxa276-pac/src/eqdc0.rs new file mode 100644 index 000000000..0e60b58a6 --- /dev/null +++ b/mcxa276-pac/src/eqdc0.rs @@ -0,0 +1,441 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + ctrl2: Ctrl2, + filt: Filt, + lastedge: Lastedge, + posdper: Posdper, + posdperbfr: Posdperbfr, + upos: Upos, + lpos: Lpos, + posd: Posd, + posdh: Posdh, + uposh: Uposh, + lposh: Lposh, + lastedgeh: Lastedgeh, + posdperh: Posdperh, + revh: Revh, + rev: Rev, + uinit: Uinit, + linit: Linit, + umod: Umod, + lmod: Lmod, + ucomp0: Ucomp0, + lcomp0: Lcomp0, + _reserved_22_ucomp1_ucomp1: [u8; 0x02], + _reserved_23_lcomp1_lcomp1: [u8; 0x02], + _reserved_24_ucomp2_ucomp2: [u8; 0x02], + _reserved_25_lcomp2_lcomp2: [u8; 0x02], + _reserved_26_ucomp3_ucomp3: [u8; 0x02], + _reserved_27_lcomp3_lcomp3: [u8; 0x02], + intctrl: Intctrl, + wtr: Wtr, + imr: Imr, + tst: Tst, + _reserved32: [u8; 0x10], + uverid: Uverid, + lverid: Lverid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x02 - Control 2 Register"] + #[inline(always)] + pub const fn ctrl2(&self) -> &Ctrl2 { + &self.ctrl2 + } + #[doc = "0x04 - Input Filter Register"] + #[inline(always)] + pub const fn filt(&self) -> &Filt { + &self.filt + } + #[doc = "0x06 - Last Edge Time Register"] + #[inline(always)] + pub const fn lastedge(&self) -> &Lastedge { + &self.lastedge + } + #[doc = "0x08 - Position Difference Period Counter Register"] + #[inline(always)] + pub const fn posdper(&self) -> &Posdper { + &self.posdper + } + #[doc = "0x0a - Position Difference Period Buffer Register"] + #[inline(always)] + pub const fn posdperbfr(&self) -> &Posdperbfr { + &self.posdperbfr + } + #[doc = "0x0c - Upper Position Counter Register"] + #[inline(always)] + pub const fn upos(&self) -> &Upos { + &self.upos + } + #[doc = "0x0e - Lower Position Counter Register"] + #[inline(always)] + pub const fn lpos(&self) -> &Lpos { + &self.lpos + } + #[doc = "0x10 - Position Difference Counter Register"] + #[inline(always)] + pub const fn posd(&self) -> &Posd { + &self.posd + } + #[doc = "0x12 - Position Difference Hold Register"] + #[inline(always)] + pub const fn posdh(&self) -> &Posdh { + &self.posdh + } + #[doc = "0x14 - Upper Position Hold Register"] + #[inline(always)] + pub const fn uposh(&self) -> &Uposh { + &self.uposh + } + #[doc = "0x16 - Lower Position Hold Register"] + #[inline(always)] + pub const fn lposh(&self) -> &Lposh { + &self.lposh + } + #[doc = "0x18 - Last Edge Time Hold Register"] + #[inline(always)] + pub const fn lastedgeh(&self) -> &Lastedgeh { + &self.lastedgeh + } + #[doc = "0x1a - Position Difference Period Hold Register"] + #[inline(always)] + pub const fn posdperh(&self) -> &Posdperh { + &self.posdperh + } + #[doc = "0x1c - Revolution Hold Register"] + #[inline(always)] + pub const fn revh(&self) -> &Revh { + &self.revh + } + #[doc = "0x1e - Revolution Counter Register"] + #[inline(always)] + pub const fn rev(&self) -> &Rev { + &self.rev + } + #[doc = "0x20 - Upper Initialization Register"] + #[inline(always)] + pub const fn uinit(&self) -> &Uinit { + &self.uinit + } + #[doc = "0x22 - Lower Initialization Register"] + #[inline(always)] + pub const fn linit(&self) -> &Linit { + &self.linit + } + #[doc = "0x24 - Upper Modulus Register"] + #[inline(always)] + pub const fn umod(&self) -> &Umod { + &self.umod + } + #[doc = "0x26 - Lower Modulus Register"] + #[inline(always)] + pub const fn lmod(&self) -> &Lmod { + &self.lmod + } + #[doc = "0x28 - Upper Position Compare Register 0"] + #[inline(always)] + pub const fn ucomp0(&self) -> &Ucomp0 { + &self.ucomp0 + } + #[doc = "0x2a - Lower Position Compare Register 0"] + #[inline(always)] + pub const fn lcomp0(&self) -> &Lcomp0 { + &self.lcomp0 + } + #[doc = "0x2c - Upper Position Holder Register 1"] + #[inline(always)] + pub const fn uposh1_uposh1(&self) -> &Uposh1Uposh1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } + } + #[doc = "0x2c - Upper Position Compare 1"] + #[inline(always)] + pub const fn ucomp1_ucomp1(&self) -> &Ucomp1Ucomp1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } + } + #[doc = "0x2e - Lower Position Holder Register 1"] + #[inline(always)] + pub const fn lposh1_lposh1(&self) -> &Lposh1Lposh1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(46).cast() } + } + #[doc = "0x2e - Lower Position Compare 1"] + #[inline(always)] + pub const fn lcomp1_lcomp1(&self) -> &Lcomp1Lcomp1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(46).cast() } + } + #[doc = "0x30 - Upper Position Holder Register 3"] + #[inline(always)] + pub const fn uposh2_uposh2(&self) -> &Uposh2Uposh2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } + } + #[doc = "0x30 - Upper Position Compare 2"] + #[inline(always)] + pub const fn ucomp2_ucomp2(&self) -> &Ucomp2Ucomp2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } + } + #[doc = "0x32 - Lower Position Holder Register 2"] + #[inline(always)] + pub const fn lposh2_lposh2(&self) -> &Lposh2Lposh2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(50).cast() } + } + #[doc = "0x32 - Lower Position Compare 2"] + #[inline(always)] + pub const fn lcomp2_lcomp2(&self) -> &Lcomp2Lcomp2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(50).cast() } + } + #[doc = "0x34 - Upper Position Holder Register 3"] + #[inline(always)] + pub const fn uposh3_uposh3(&self) -> &Uposh3Uposh3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } + } + #[doc = "0x34 - Upper Position Compare 3"] + #[inline(always)] + pub const fn ucomp3_ucomp3(&self) -> &Ucomp3Ucomp3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } + } + #[doc = "0x36 - Lower Position Holder Register 3"] + #[inline(always)] + pub const fn lposh3_lposh3(&self) -> &Lposh3Lposh3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } + } + #[doc = "0x36 - Lower Position Compare 3"] + #[inline(always)] + pub const fn lcomp3_lcomp3(&self) -> &Lcomp3Lcomp3 { + unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } + } + #[doc = "0x38 - Interrupt Control Register"] + #[inline(always)] + pub const fn intctrl(&self) -> &Intctrl { + &self.intctrl + } + #[doc = "0x3a - Watchdog Timeout Register"] + #[inline(always)] + pub const fn wtr(&self) -> &Wtr { + &self.wtr + } + #[doc = "0x3c - Input Monitor Register"] + #[inline(always)] + pub const fn imr(&self) -> &Imr { + &self.imr + } + #[doc = "0x3e - Test Register"] + #[inline(always)] + pub const fn tst(&self) -> &Tst { + &self.tst + } + #[doc = "0x50 - Upper VERID"] + #[inline(always)] + pub const fn uverid(&self) -> &Uverid { + &self.uverid + } + #[doc = "0x52 - Lower VERID"] + #[inline(always)] + pub const fn lverid(&self) -> &Lverid { + &self.lverid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"] +#[doc(alias = "CTRL2")] +pub type Ctrl2 = crate::Reg; +#[doc = "Control 2 Register"] +pub mod ctrl2; +#[doc = "FILT (rw) register accessor: Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filt`] module"] +#[doc(alias = "FILT")] +pub type Filt = crate::Reg; +#[doc = "Input Filter Register"] +pub mod filt; +#[doc = "LASTEDGE (r) register accessor: Last Edge Time Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedge::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lastedge`] module"] +#[doc(alias = "LASTEDGE")] +pub type Lastedge = crate::Reg; +#[doc = "Last Edge Time Register"] +pub mod lastedge; +#[doc = "POSDPER (r) register accessor: Position Difference Period Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdper::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdper`] module"] +#[doc(alias = "POSDPER")] +pub type Posdper = crate::Reg; +#[doc = "Position Difference Period Counter Register"] +pub mod posdper; +#[doc = "POSDPERBFR (r) register accessor: Position Difference Period Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperbfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdperbfr`] module"] +#[doc(alias = "POSDPERBFR")] +pub type Posdperbfr = crate::Reg; +#[doc = "Position Difference Period Buffer Register"] +pub mod posdperbfr; +#[doc = "UPOS (rw) register accessor: Upper Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`upos::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`upos::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upos`] module"] +#[doc(alias = "UPOS")] +pub type Upos = crate::Reg; +#[doc = "Upper Position Counter Register"] +pub mod upos; +#[doc = "LPOS (rw) register accessor: Lower Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lpos::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpos::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpos`] module"] +#[doc(alias = "LPOS")] +pub type Lpos = crate::Reg; +#[doc = "Lower Position Counter Register"] +pub mod lpos; +#[doc = "POSD (rw) register accessor: Position Difference Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`posd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posd`] module"] +#[doc(alias = "POSD")] +pub type Posd = crate::Reg; +#[doc = "Position Difference Counter Register"] +pub mod posd; +#[doc = "POSDH (r) register accessor: Position Difference Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdh`] module"] +#[doc(alias = "POSDH")] +pub type Posdh = crate::Reg; +#[doc = "Position Difference Hold Register"] +pub mod posdh; +#[doc = "UPOSH (r) register accessor: Upper Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh`] module"] +#[doc(alias = "UPOSH")] +pub type Uposh = crate::Reg; +#[doc = "Upper Position Hold Register"] +pub mod uposh; +#[doc = "LPOSH (r) register accessor: Lower Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh`] module"] +#[doc(alias = "LPOSH")] +pub type Lposh = crate::Reg; +#[doc = "Lower Position Hold Register"] +pub mod lposh; +#[doc = "LASTEDGEH (r) register accessor: Last Edge Time Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedgeh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lastedgeh`] module"] +#[doc(alias = "LASTEDGEH")] +pub type Lastedgeh = crate::Reg; +#[doc = "Last Edge Time Hold Register"] +pub mod lastedgeh; +#[doc = "POSDPERH (r) register accessor: Position Difference Period Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdperh`] module"] +#[doc(alias = "POSDPERH")] +pub type Posdperh = crate::Reg; +#[doc = "Position Difference Period Hold Register"] +pub mod posdperh; +#[doc = "REVH (r) register accessor: Revolution Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`revh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@revh`] module"] +#[doc(alias = "REVH")] +pub type Revh = crate::Reg; +#[doc = "Revolution Hold Register"] +pub mod revh; +#[doc = "REV (rw) register accessor: Revolution Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rev::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rev`] module"] +#[doc(alias = "REV")] +pub type Rev = crate::Reg; +#[doc = "Revolution Counter Register"] +pub mod rev; +#[doc = "UINIT (rw) register accessor: Upper Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uinit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uinit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uinit`] module"] +#[doc(alias = "UINIT")] +pub type Uinit = crate::Reg; +#[doc = "Upper Initialization Register"] +pub mod uinit; +#[doc = "LINIT (rw) register accessor: Lower Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`linit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linit`] module"] +#[doc(alias = "LINIT")] +pub type Linit = crate::Reg; +#[doc = "Lower Initialization Register"] +pub mod linit; +#[doc = "UMOD (rw) register accessor: Upper Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`umod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`umod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@umod`] module"] +#[doc(alias = "UMOD")] +pub type Umod = crate::Reg; +#[doc = "Upper Modulus Register"] +pub mod umod; +#[doc = "LMOD (rw) register accessor: Lower Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lmod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lmod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lmod`] module"] +#[doc(alias = "LMOD")] +pub type Lmod = crate::Reg; +#[doc = "Lower Modulus Register"] +pub mod lmod; +#[doc = "UCOMP0 (rw) register accessor: Upper Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucomp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp0`] module"] +#[doc(alias = "UCOMP0")] +pub type Ucomp0 = crate::Reg; +#[doc = "Upper Position Compare Register 0"] +pub mod ucomp0; +#[doc = "LCOMP0 (rw) register accessor: Lower Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcomp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp0`] module"] +#[doc(alias = "LCOMP0")] +pub type Lcomp0 = crate::Reg; +#[doc = "Lower Position Compare Register 0"] +pub mod lcomp0; +#[doc = "UCOMP1_UCOMP1 (w) register accessor: Upper Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp1_ucomp1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp1_ucomp1`] module"] +#[doc(alias = "UCOMP1_UCOMP1")] +pub type Ucomp1Ucomp1 = crate::Reg; +#[doc = "Upper Position Compare 1"] +pub mod ucomp1_ucomp1; +#[doc = "UPOSH1_UPOSH1 (r) register accessor: Upper Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh1_uposh1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh1_uposh1`] module"] +#[doc(alias = "UPOSH1_UPOSH1")] +pub type Uposh1Uposh1 = crate::Reg; +#[doc = "Upper Position Holder Register 1"] +pub mod uposh1_uposh1; +#[doc = "LCOMP1_LCOMP1 (w) register accessor: Lower Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp1_lcomp1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp1_lcomp1`] module"] +#[doc(alias = "LCOMP1_LCOMP1")] +pub type Lcomp1Lcomp1 = crate::Reg; +#[doc = "Lower Position Compare 1"] +pub mod lcomp1_lcomp1; +#[doc = "LPOSH1_LPOSH1 (r) register accessor: Lower Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh1_lposh1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh1_lposh1`] module"] +#[doc(alias = "LPOSH1_LPOSH1")] +pub type Lposh1Lposh1 = crate::Reg; +#[doc = "Lower Position Holder Register 1"] +pub mod lposh1_lposh1; +#[doc = "UCOMP2_UCOMP2 (w) register accessor: Upper Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp2_ucomp2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp2_ucomp2`] module"] +#[doc(alias = "UCOMP2_UCOMP2")] +pub type Ucomp2Ucomp2 = crate::Reg; +#[doc = "Upper Position Compare 2"] +pub mod ucomp2_ucomp2; +#[doc = "UPOSH2_UPOSH2 (r) register accessor: Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh2_uposh2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh2_uposh2`] module"] +#[doc(alias = "UPOSH2_UPOSH2")] +pub type Uposh2Uposh2 = crate::Reg; +#[doc = "Upper Position Holder Register 3"] +pub mod uposh2_uposh2; +#[doc = "LCOMP2_LCOMP2 (w) register accessor: Lower Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp2_lcomp2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp2_lcomp2`] module"] +#[doc(alias = "LCOMP2_LCOMP2")] +pub type Lcomp2Lcomp2 = crate::Reg; +#[doc = "Lower Position Compare 2"] +pub mod lcomp2_lcomp2; +#[doc = "LPOSH2_LPOSH2 (r) register accessor: Lower Position Holder Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh2_lposh2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh2_lposh2`] module"] +#[doc(alias = "LPOSH2_LPOSH2")] +pub type Lposh2Lposh2 = crate::Reg; +#[doc = "Lower Position Holder Register 2"] +pub mod lposh2_lposh2; +#[doc = "UCOMP3_UCOMP3 (w) register accessor: Upper Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp3_ucomp3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp3_ucomp3`] module"] +#[doc(alias = "UCOMP3_UCOMP3")] +pub type Ucomp3Ucomp3 = crate::Reg; +#[doc = "Upper Position Compare 3"] +pub mod ucomp3_ucomp3; +#[doc = "UPOSH3_UPOSH3 (r) register accessor: Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh3_uposh3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh3_uposh3`] module"] +#[doc(alias = "UPOSH3_UPOSH3")] +pub type Uposh3Uposh3 = crate::Reg; +#[doc = "Upper Position Holder Register 3"] +pub mod uposh3_uposh3; +#[doc = "LCOMP3_LCOMP3 (w) register accessor: Lower Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp3_lcomp3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp3_lcomp3`] module"] +#[doc(alias = "LCOMP3_LCOMP3")] +pub type Lcomp3Lcomp3 = crate::Reg; +#[doc = "Lower Position Compare 3"] +pub mod lcomp3_lcomp3; +#[doc = "LPOSH3_LPOSH3 (r) register accessor: Lower Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh3_lposh3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh3_lposh3`] module"] +#[doc(alias = "LPOSH3_LPOSH3")] +pub type Lposh3Lposh3 = crate::Reg; +#[doc = "Lower Position Holder Register 3"] +pub mod lposh3_lposh3; +#[doc = "INTCTRL (rw) register accessor: Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intctrl`] module"] +#[doc(alias = "INTCTRL")] +pub type Intctrl = crate::Reg; +#[doc = "Interrupt Control Register"] +pub mod intctrl; +#[doc = "WTR (rw) register accessor: Watchdog Timeout Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wtr`] module"] +#[doc(alias = "WTR")] +pub type Wtr = crate::Reg; +#[doc = "Watchdog Timeout Register"] +pub mod wtr; +#[doc = "IMR (rw) register accessor: Input Monitor Register\n\nYou can [`read`](crate::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imr`] module"] +#[doc(alias = "IMR")] +pub type Imr = crate::Reg; +#[doc = "Input Monitor Register"] +pub mod imr; +#[doc = "TST (rw) register accessor: Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tst`] module"] +#[doc(alias = "TST")] +pub type Tst = crate::Reg; +#[doc = "Test Register"] +pub mod tst; +#[doc = "UVERID (r) register accessor: Upper VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`uverid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uverid`] module"] +#[doc(alias = "UVERID")] +pub type Uverid = crate::Reg; +#[doc = "Upper VERID"] +pub mod uverid; +#[doc = "LVERID (r) register accessor: Lower VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`lverid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lverid`] module"] +#[doc(alias = "LVERID")] +pub type Lverid = crate::Reg; +#[doc = "Lower VERID"] +pub mod lverid; diff --git a/mcxa276-pac/src/eqdc0/ctrl.rs b/mcxa276-pac/src/eqdc0/ctrl.rs new file mode 100644 index 000000000..7b3fc2c2e --- /dev/null +++ b/mcxa276-pac/src/eqdc0/ctrl.rs @@ -0,0 +1,1030 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Load Okay\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldok { + #[doc = "0: No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)"] + Ldok0 = 0, + #[doc = "1: Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2\\[LDMOD\\]."] + Ldok1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldok) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDOK` reader - Load Okay"] +pub type LdokR = crate::BitReader; +impl LdokR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldok { + match self.bits { + false => Ldok::Ldok0, + true => Ldok::Ldok1, + } + } + #[doc = "No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)"] + #[inline(always)] + pub fn is_ldok0(&self) -> bool { + *self == Ldok::Ldok0 + } + #[doc = "Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2\\[LDMOD\\]."] + #[inline(always)] + pub fn is_ldok1(&self) -> bool { + *self == Ldok::Ldok1 + } +} +#[doc = "Field `LDOK` writer - Load Okay"] +pub type LdokW<'a, REG> = crate::BitWriter<'a, REG, Ldok>; +impl<'a, REG> LdokW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)"] + #[inline(always)] + pub fn ldok0(self) -> &'a mut crate::W { + self.variant(Ldok::Ldok0) + } + #[doc = "Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2\\[LDMOD\\]."] + #[inline(always)] + pub fn ldok1(self) -> &'a mut crate::W { + self.variant(Ldok::Ldok1) + } +} +#[doc = "DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmaen { + #[doc = "0: DMA is disabled"] + Dmaen0 = 0, + #[doc = "1: DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be loaded into inner-set which in turn triggers DMA again."] + Dmaen1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmaen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMAEN` reader - DMA Enable"] +pub type DmaenR = crate::BitReader; +impl DmaenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmaen { + match self.bits { + false => Dmaen::Dmaen0, + true => Dmaen::Dmaen1, + } + } + #[doc = "DMA is disabled"] + #[inline(always)] + pub fn is_dmaen_0(&self) -> bool { + *self == Dmaen::Dmaen0 + } + #[doc = "DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be loaded into inner-set which in turn triggers DMA again."] + #[inline(always)] + pub fn is_dmaen_1(&self) -> bool { + *self == Dmaen::Dmaen1 + } +} +#[doc = "Field `DMAEN` writer - DMA Enable"] +pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG, Dmaen>; +impl<'a, REG> DmaenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DMA is disabled"] + #[inline(always)] + pub fn dmaen_0(self) -> &'a mut crate::W { + self.variant(Dmaen::Dmaen0) + } + #[doc = "DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be loaded into inner-set which in turn triggers DMA again."] + #[inline(always)] + pub fn dmaen_1(self) -> &'a mut crate::W { + self.variant(Dmaen::Dmaen1) + } +} +#[doc = "Watchdog Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wde { + #[doc = "0: Disabled"] + Wde0 = 0, + #[doc = "1: Enabled"] + Wde1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDE` reader - Watchdog Enable"] +pub type WdeR = crate::BitReader; +impl WdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wde { + match self.bits { + false => Wde::Wde0, + true => Wde::Wde1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_wde0(&self) -> bool { + *self == Wde::Wde0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_wde1(&self) -> bool { + *self == Wde::Wde1 + } +} +#[doc = "Field `WDE` writer - Watchdog Enable"] +pub type WdeW<'a, REG> = crate::BitWriter<'a, REG, Wde>; +impl<'a, REG> WdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn wde0(self) -> &'a mut crate::W { + self.variant(Wde::Wde0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn wde1(self) -> &'a mut crate::W { + self.variant(Wde::Wde1) + } +} +#[doc = "Watchdog Timeout Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdie { + #[doc = "0: Disabled"] + Wdie0 = 0, + #[doc = "1: Enabled"] + Wdie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDIE` reader - Watchdog Timeout Interrupt Enable"] +pub type WdieR = crate::BitReader; +impl WdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdie { + match self.bits { + false => Wdie::Wdie0, + true => Wdie::Wdie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_wdie0(&self) -> bool { + *self == Wdie::Wdie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_wdie1(&self) -> bool { + *self == Wdie::Wdie1 + } +} +#[doc = "Field `WDIE` writer - Watchdog Timeout Interrupt Enable"] +pub type WdieW<'a, REG> = crate::BitWriter<'a, REG, Wdie>; +impl<'a, REG> WdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn wdie0(self) -> &'a mut crate::W { + self.variant(Wdie::Wdie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn wdie1(self) -> &'a mut crate::W { + self.variant(Wdie::Wdie1) + } +} +#[doc = "Watchdog Timeout Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdirq { + #[doc = "0: No Watchdog timeout interrupt has occurred"] + Wdirq0 = 0, + #[doc = "1: Watchdog timeout interrupt has occurred"] + Wdirq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdirq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDIRQ` reader - Watchdog Timeout Interrupt Request"] +pub type WdirqR = crate::BitReader; +impl WdirqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdirq { + match self.bits { + false => Wdirq::Wdirq0, + true => Wdirq::Wdirq1, + } + } + #[doc = "No Watchdog timeout interrupt has occurred"] + #[inline(always)] + pub fn is_wdirq0(&self) -> bool { + *self == Wdirq::Wdirq0 + } + #[doc = "Watchdog timeout interrupt has occurred"] + #[inline(always)] + pub fn is_wdirq1(&self) -> bool { + *self == Wdirq::Wdirq1 + } +} +#[doc = "Field `WDIRQ` writer - Watchdog Timeout Interrupt Request"] +pub type WdirqW<'a, REG> = crate::BitWriter1C<'a, REG, Wdirq>; +impl<'a, REG> WdirqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No Watchdog timeout interrupt has occurred"] + #[inline(always)] + pub fn wdirq0(self) -> &'a mut crate::W { + self.variant(Wdirq::Wdirq0) + } + #[doc = "Watchdog timeout interrupt has occurred"] + #[inline(always)] + pub fn wdirq1(self) -> &'a mut crate::W { + self.variant(Wdirq::Wdirq1) + } +} +#[doc = "Select Positive/Negative Edge of INDEX/PRESET Pulse\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Xne { + #[doc = "0: Use positive edge of INDEX/PRESET pulse"] + Xne0 = 0, + #[doc = "1: Use negative edge of INDEX/PRESET pulse"] + Xne1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Xne) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `XNE` reader - Select Positive/Negative Edge of INDEX/PRESET Pulse"] +pub type XneR = crate::BitReader; +impl XneR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Xne { + match self.bits { + false => Xne::Xne0, + true => Xne::Xne1, + } + } + #[doc = "Use positive edge of INDEX/PRESET pulse"] + #[inline(always)] + pub fn is_xne0(&self) -> bool { + *self == Xne::Xne0 + } + #[doc = "Use negative edge of INDEX/PRESET pulse"] + #[inline(always)] + pub fn is_xne1(&self) -> bool { + *self == Xne::Xne1 + } +} +#[doc = "Field `XNE` writer - Select Positive/Negative Edge of INDEX/PRESET Pulse"] +pub type XneW<'a, REG> = crate::BitWriter<'a, REG, Xne>; +impl<'a, REG> XneW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Use positive edge of INDEX/PRESET pulse"] + #[inline(always)] + pub fn xne0(self) -> &'a mut crate::W { + self.variant(Xne::Xne0) + } + #[doc = "Use negative edge of INDEX/PRESET pulse"] + #[inline(always)] + pub fn xne1(self) -> &'a mut crate::W { + self.variant(Xne::Xne1) + } +} +#[doc = "INDEX Triggered Initialization of Position Counters UPOS and LPOS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Xip { + #[doc = "0: INDEX pulse does not initialize the position counter"] + Xip0 = 0, + #[doc = "1: INDEX pulse initializes the position counter"] + Xip1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Xip) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `XIP` reader - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] +pub type XipR = crate::BitReader; +impl XipR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Xip { + match self.bits { + false => Xip::Xip0, + true => Xip::Xip1, + } + } + #[doc = "INDEX pulse does not initialize the position counter"] + #[inline(always)] + pub fn is_xip0(&self) -> bool { + *self == Xip::Xip0 + } + #[doc = "INDEX pulse initializes the position counter"] + #[inline(always)] + pub fn is_xip1(&self) -> bool { + *self == Xip::Xip1 + } +} +#[doc = "Field `XIP` writer - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] +pub type XipW<'a, REG> = crate::BitWriter<'a, REG, Xip>; +impl<'a, REG> XipW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "INDEX pulse does not initialize the position counter"] + #[inline(always)] + pub fn xip0(self) -> &'a mut crate::W { + self.variant(Xip::Xip0) + } + #[doc = "INDEX pulse initializes the position counter"] + #[inline(always)] + pub fn xip1(self) -> &'a mut crate::W { + self.variant(Xip::Xip1) + } +} +#[doc = "INDEX/PRESET Pulse Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Xie { + #[doc = "0: Disabled"] + Xie0 = 0, + #[doc = "1: Enabled"] + Xie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Xie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `XIE` reader - INDEX/PRESET Pulse Interrupt Enable"] +pub type XieR = crate::BitReader; +impl XieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Xie { + match self.bits { + false => Xie::Xie0, + true => Xie::Xie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_xie0(&self) -> bool { + *self == Xie::Xie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_xie1(&self) -> bool { + *self == Xie::Xie1 + } +} +#[doc = "Field `XIE` writer - INDEX/PRESET Pulse Interrupt Enable"] +pub type XieW<'a, REG> = crate::BitWriter<'a, REG, Xie>; +impl<'a, REG> XieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn xie0(self) -> &'a mut crate::W { + self.variant(Xie::Xie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn xie1(self) -> &'a mut crate::W { + self.variant(Xie::Xie1) + } +} +#[doc = "INDEX/PRESET Pulse Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Xirq { + #[doc = "0: INDEX/PRESET pulse has not occurred"] + Xirq0 = 0, + #[doc = "1: INDEX/PRESET pulse has occurred"] + Xirq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Xirq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `XIRQ` reader - INDEX/PRESET Pulse Interrupt Request"] +pub type XirqR = crate::BitReader; +impl XirqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Xirq { + match self.bits { + false => Xirq::Xirq0, + true => Xirq::Xirq1, + } + } + #[doc = "INDEX/PRESET pulse has not occurred"] + #[inline(always)] + pub fn is_xirq0(&self) -> bool { + *self == Xirq::Xirq0 + } + #[doc = "INDEX/PRESET pulse has occurred"] + #[inline(always)] + pub fn is_xirq1(&self) -> bool { + *self == Xirq::Xirq1 + } +} +#[doc = "Field `XIRQ` writer - INDEX/PRESET Pulse Interrupt Request"] +pub type XirqW<'a, REG> = crate::BitWriter1C<'a, REG, Xirq>; +impl<'a, REG> XirqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "INDEX/PRESET pulse has not occurred"] + #[inline(always)] + pub fn xirq0(self) -> &'a mut crate::W { + self.variant(Xirq::Xirq0) + } + #[doc = "INDEX/PRESET pulse has occurred"] + #[inline(always)] + pub fn xirq1(self) -> &'a mut crate::W { + self.variant(Xirq::Xirq1) + } +} +#[doc = "Enable Single Phase Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ph1 { + #[doc = "0: Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal."] + Ph10 = 0, + #[doc = "1: Single phase mode, bypass the quadrature decoder, refer to CTRL2\\[CMODE\\] description"] + Ph11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ph1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PH1` reader - Enable Single Phase Mode"] +pub type Ph1R = crate::BitReader; +impl Ph1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ph1 { + match self.bits { + false => Ph1::Ph10, + true => Ph1::Ph11, + } + } + #[doc = "Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal."] + #[inline(always)] + pub fn is_ph10(&self) -> bool { + *self == Ph1::Ph10 + } + #[doc = "Single phase mode, bypass the quadrature decoder, refer to CTRL2\\[CMODE\\] description"] + #[inline(always)] + pub fn is_ph11(&self) -> bool { + *self == Ph1::Ph11 + } +} +#[doc = "Field `PH1` writer - Enable Single Phase Mode"] +pub type Ph1W<'a, REG> = crate::BitWriter<'a, REG, Ph1>; +impl<'a, REG> Ph1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal."] + #[inline(always)] + pub fn ph10(self) -> &'a mut crate::W { + self.variant(Ph1::Ph10) + } + #[doc = "Single phase mode, bypass the quadrature decoder, refer to CTRL2\\[CMODE\\] description"] + #[inline(always)] + pub fn ph11(self) -> &'a mut crate::W { + self.variant(Ph1::Ph11) + } +} +#[doc = "Enable Reverse Direction Counting\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rev { + #[doc = "0: Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT"] + Rev0 = 0, + #[doc = "1: Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD"] + Rev1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rev) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REV` reader - Enable Reverse Direction Counting"] +pub type RevR = crate::BitReader; +impl RevR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rev { + match self.bits { + false => Rev::Rev0, + true => Rev::Rev1, + } + } + #[doc = "Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT"] + #[inline(always)] + pub fn is_rev0(&self) -> bool { + *self == Rev::Rev0 + } + #[doc = "Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD"] + #[inline(always)] + pub fn is_rev1(&self) -> bool { + *self == Rev::Rev1 + } +} +#[doc = "Field `REV` writer - Enable Reverse Direction Counting"] +pub type RevW<'a, REG> = crate::BitWriter<'a, REG, Rev>; +impl<'a, REG> RevW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT"] + #[inline(always)] + pub fn rev0(self) -> &'a mut crate::W { + self.variant(Rev::Rev0) + } + #[doc = "Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD"] + #[inline(always)] + pub fn rev1(self) -> &'a mut crate::W { + self.variant(Rev::Rev1) + } +} +#[doc = "Software-Triggered Initialization of Position Counters UPOS and LPOS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swip { + #[doc = "0: No action"] + Swip0 = 0, + #[doc = "1: Initialize position counter"] + Swip1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swip) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWIP` reader - Software-Triggered Initialization of Position Counters UPOS and LPOS"] +pub type SwipR = crate::BitReader; +impl SwipR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swip { + match self.bits { + false => Swip::Swip0, + true => Swip::Swip1, + } + } + #[doc = "No action"] + #[inline(always)] + pub fn is_swip0(&self) -> bool { + *self == Swip::Swip0 + } + #[doc = "Initialize position counter"] + #[inline(always)] + pub fn is_swip1(&self) -> bool { + *self == Swip::Swip1 + } +} +#[doc = "Field `SWIP` writer - Software-Triggered Initialization of Position Counters UPOS and LPOS"] +pub type SwipW<'a, REG> = crate::BitWriter<'a, REG, Swip>; +impl<'a, REG> SwipW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No action"] + #[inline(always)] + pub fn swip0(self) -> &'a mut crate::W { + self.variant(Swip::Swip0) + } + #[doc = "Initialize position counter"] + #[inline(always)] + pub fn swip1(self) -> &'a mut crate::W { + self.variant(Swip::Swip1) + } +} +#[doc = "Use Negative Edge of HOME/ENABLE Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hne { + #[doc = "0: When CTRL\\[OPMODE\\] = 0,use HOME positive edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters"] + Hne0 = 0, + #[doc = "1: When CTRL\\[OPMODE\\] = 0,use HOME negative edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters"] + Hne1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hne) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HNE` reader - Use Negative Edge of HOME/ENABLE Input"] +pub type HneR = crate::BitReader; +impl HneR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hne { + match self.bits { + false => Hne::Hne0, + true => Hne::Hne1, + } + } + #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME positive edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters"] + #[inline(always)] + pub fn is_hne0(&self) -> bool { + *self == Hne::Hne0 + } + #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME negative edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters"] + #[inline(always)] + pub fn is_hne1(&self) -> bool { + *self == Hne::Hne1 + } +} +#[doc = "Field `HNE` writer - Use Negative Edge of HOME/ENABLE Input"] +pub type HneW<'a, REG> = crate::BitWriter<'a, REG, Hne>; +impl<'a, REG> HneW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME positive edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters"] + #[inline(always)] + pub fn hne0(self) -> &'a mut crate::W { + self.variant(Hne::Hne0) + } + #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME negative edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters"] + #[inline(always)] + pub fn hne1(self) -> &'a mut crate::W { + self.variant(Hne::Hne1) + } +} +#[doc = "Enable HOME to Initialize Position Counter UPOS/LPOS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hip { + #[doc = "0: No action"] + Hip0 = 0, + #[doc = "1: HOME signal initializes the position counter"] + Hip1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hip) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HIP` reader - Enable HOME to Initialize Position Counter UPOS/LPOS"] +pub type HipR = crate::BitReader; +impl HipR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hip { + match self.bits { + false => Hip::Hip0, + true => Hip::Hip1, + } + } + #[doc = "No action"] + #[inline(always)] + pub fn is_hip0(&self) -> bool { + *self == Hip::Hip0 + } + #[doc = "HOME signal initializes the position counter"] + #[inline(always)] + pub fn is_hip1(&self) -> bool { + *self == Hip::Hip1 + } +} +#[doc = "Field `HIP` writer - Enable HOME to Initialize Position Counter UPOS/LPOS"] +pub type HipW<'a, REG> = crate::BitWriter<'a, REG, Hip>; +impl<'a, REG> HipW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No action"] + #[inline(always)] + pub fn hip0(self) -> &'a mut crate::W { + self.variant(Hip::Hip0) + } + #[doc = "HOME signal initializes the position counter"] + #[inline(always)] + pub fn hip1(self) -> &'a mut crate::W { + self.variant(Hip::Hip1) + } +} +#[doc = "HOME/ENABLE Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hie { + #[doc = "0: Disabled"] + Hie0 = 0, + #[doc = "1: Enabled"] + Hie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HIE` reader - HOME/ENABLE Interrupt Enable"] +pub type HieR = crate::BitReader; +impl HieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hie { + match self.bits { + false => Hie::Hie0, + true => Hie::Hie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_hie0(&self) -> bool { + *self == Hie::Hie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_hie1(&self) -> bool { + *self == Hie::Hie1 + } +} +#[doc = "Field `HIE` writer - HOME/ENABLE Interrupt Enable"] +pub type HieW<'a, REG> = crate::BitWriter<'a, REG, Hie>; +impl<'a, REG> HieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn hie0(self) -> &'a mut crate::W { + self.variant(Hie::Hie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn hie1(self) -> &'a mut crate::W { + self.variant(Hie::Hie1) + } +} +#[doc = "HOME/ENABLE Signal Transition Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hirq { + #[doc = "0: No transition on the HOME/ENABLE signal has occurred"] + Hirq0 = 0, + #[doc = "1: A transition on the HOME/ENABLE signal has occurred"] + Hirq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hirq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HIRQ` reader - HOME/ENABLE Signal Transition Interrupt Request"] +pub type HirqR = crate::BitReader; +impl HirqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hirq { + match self.bits { + false => Hirq::Hirq0, + true => Hirq::Hirq1, + } + } + #[doc = "No transition on the HOME/ENABLE signal has occurred"] + #[inline(always)] + pub fn is_hirq0(&self) -> bool { + *self == Hirq::Hirq0 + } + #[doc = "A transition on the HOME/ENABLE signal has occurred"] + #[inline(always)] + pub fn is_hirq1(&self) -> bool { + *self == Hirq::Hirq1 + } +} +#[doc = "Field `HIRQ` writer - HOME/ENABLE Signal Transition Interrupt Request"] +pub type HirqW<'a, REG> = crate::BitWriter1C<'a, REG, Hirq>; +impl<'a, REG> HirqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No transition on the HOME/ENABLE signal has occurred"] + #[inline(always)] + pub fn hirq0(self) -> &'a mut crate::W { + self.variant(Hirq::Hirq0) + } + #[doc = "A transition on the HOME/ENABLE signal has occurred"] + #[inline(always)] + pub fn hirq1(self) -> &'a mut crate::W { + self.variant(Hirq::Hirq1) + } +} +impl R { + #[doc = "Bit 0 - Load Okay"] + #[inline(always)] + pub fn ldok(&self) -> LdokR { + LdokR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaen(&self) -> DmaenR { + DmaenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Watchdog Enable"] + #[inline(always)] + pub fn wde(&self) -> WdeR { + WdeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Watchdog Timeout Interrupt Enable"] + #[inline(always)] + pub fn wdie(&self) -> WdieR { + WdieR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Watchdog Timeout Interrupt Request"] + #[inline(always)] + pub fn wdirq(&self) -> WdirqR { + WdirqR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Select Positive/Negative Edge of INDEX/PRESET Pulse"] + #[inline(always)] + pub fn xne(&self) -> XneR { + XneR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] + #[inline(always)] + pub fn xip(&self) -> XipR { + XipR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - INDEX/PRESET Pulse Interrupt Enable"] + #[inline(always)] + pub fn xie(&self) -> XieR { + XieR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - INDEX/PRESET Pulse Interrupt Request"] + #[inline(always)] + pub fn xirq(&self) -> XirqR { + XirqR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable Single Phase Mode"] + #[inline(always)] + pub fn ph1(&self) -> Ph1R { + Ph1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable Reverse Direction Counting"] + #[inline(always)] + pub fn rev(&self) -> RevR { + RevR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software-Triggered Initialization of Position Counters UPOS and LPOS"] + #[inline(always)] + pub fn swip(&self) -> SwipR { + SwipR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Use Negative Edge of HOME/ENABLE Input"] + #[inline(always)] + pub fn hne(&self) -> HneR { + HneR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable HOME to Initialize Position Counter UPOS/LPOS"] + #[inline(always)] + pub fn hip(&self) -> HipR { + HipR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - HOME/ENABLE Interrupt Enable"] + #[inline(always)] + pub fn hie(&self) -> HieR { + HieR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - HOME/ENABLE Signal Transition Interrupt Request"] + #[inline(always)] + pub fn hirq(&self) -> HirqR { + HirqR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Load Okay"] + #[inline(always)] + pub fn ldok(&mut self) -> LdokW { + LdokW::new(self, 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaen(&mut self) -> DmaenW { + DmaenW::new(self, 1) + } + #[doc = "Bit 2 - Watchdog Enable"] + #[inline(always)] + pub fn wde(&mut self) -> WdeW { + WdeW::new(self, 2) + } + #[doc = "Bit 3 - Watchdog Timeout Interrupt Enable"] + #[inline(always)] + pub fn wdie(&mut self) -> WdieW { + WdieW::new(self, 3) + } + #[doc = "Bit 4 - Watchdog Timeout Interrupt Request"] + #[inline(always)] + pub fn wdirq(&mut self) -> WdirqW { + WdirqW::new(self, 4) + } + #[doc = "Bit 5 - Select Positive/Negative Edge of INDEX/PRESET Pulse"] + #[inline(always)] + pub fn xne(&mut self) -> XneW { + XneW::new(self, 5) + } + #[doc = "Bit 6 - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] + #[inline(always)] + pub fn xip(&mut self) -> XipW { + XipW::new(self, 6) + } + #[doc = "Bit 7 - INDEX/PRESET Pulse Interrupt Enable"] + #[inline(always)] + pub fn xie(&mut self) -> XieW { + XieW::new(self, 7) + } + #[doc = "Bit 8 - INDEX/PRESET Pulse Interrupt Request"] + #[inline(always)] + pub fn xirq(&mut self) -> XirqW { + XirqW::new(self, 8) + } + #[doc = "Bit 9 - Enable Single Phase Mode"] + #[inline(always)] + pub fn ph1(&mut self) -> Ph1W { + Ph1W::new(self, 9) + } + #[doc = "Bit 10 - Enable Reverse Direction Counting"] + #[inline(always)] + pub fn rev(&mut self) -> RevW { + RevW::new(self, 10) + } + #[doc = "Bit 11 - Software-Triggered Initialization of Position Counters UPOS and LPOS"] + #[inline(always)] + pub fn swip(&mut self) -> SwipW { + SwipW::new(self, 11) + } + #[doc = "Bit 12 - Use Negative Edge of HOME/ENABLE Input"] + #[inline(always)] + pub fn hne(&mut self) -> HneW { + HneW::new(self, 12) + } + #[doc = "Bit 13 - Enable HOME to Initialize Position Counter UPOS/LPOS"] + #[inline(always)] + pub fn hip(&mut self) -> HipW { + HipW::new(self, 13) + } + #[doc = "Bit 14 - HOME/ENABLE Interrupt Enable"] + #[inline(always)] + pub fn hie(&mut self) -> HieW { + HieW::new(self, 14) + } + #[doc = "Bit 15 - HOME/ENABLE Signal Transition Interrupt Request"] + #[inline(always)] + pub fn hirq(&mut self) -> HirqW { + HirqW::new(self, 15) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x8110; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/eqdc0/ctrl2.rs b/mcxa276-pac/src/eqdc0/ctrl2.rs new file mode 100644 index 000000000..d8f6394bd --- /dev/null +++ b/mcxa276-pac/src/eqdc0/ctrl2.rs @@ -0,0 +1,567 @@ +#[doc = "Register `CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `UPDHLD` reader - Update Hold Registers"] +pub type UpdhldR = crate::BitReader; +#[doc = "Field `UPDHLD` writer - Update Hold Registers"] +pub type UpdhldW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UPDPOS` reader - Update Position Registers"] +pub type UpdposR = crate::BitReader; +#[doc = "Field `UPDPOS` writer - Update Position Registers"] +pub type UpdposW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Operation Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opmode { + #[doc = "0: Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."] + Opmode0 = 0, + #[doc = "1: Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."] + Opmode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opmode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPMODE` reader - Operation Mode Select"] +pub type OpmodeR = crate::BitReader; +impl OpmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opmode { + match self.bits { + false => Opmode::Opmode0, + true => Opmode::Opmode1, + } + } + #[doc = "Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."] + #[inline(always)] + pub fn is_opmode0(&self) -> bool { + *self == Opmode::Opmode0 + } + #[doc = "Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."] + #[inline(always)] + pub fn is_opmode1(&self) -> bool { + *self == Opmode::Opmode1 + } +} +#[doc = "Field `OPMODE` writer - Operation Mode Select"] +pub type OpmodeW<'a, REG> = crate::BitWriter<'a, REG, Opmode>; +impl<'a, REG> OpmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."] + #[inline(always)] + pub fn opmode0(self) -> &'a mut crate::W { + self.variant(Opmode::Opmode0) + } + #[doc = "Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."] + #[inline(always)] + pub fn opmode1(self) -> &'a mut crate::W { + self.variant(Opmode::Opmode1) + } +} +#[doc = "Buffered Register Load (Update) Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldmod { + #[doc = "0: Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."] + Ldmod0 = 0, + #[doc = "1: Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."] + Ldmod1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldmod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDMOD` reader - Buffered Register Load (Update) Mode Select"] +pub type LdmodR = crate::BitReader; +impl LdmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldmod { + match self.bits { + false => Ldmod::Ldmod0, + true => Ldmod::Ldmod1, + } + } + #[doc = "Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn is_ldmod0(&self) -> bool { + *self == Ldmod::Ldmod0 + } + #[doc = "Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn is_ldmod1(&self) -> bool { + *self == Ldmod::Ldmod1 + } +} +#[doc = "Field `LDMOD` writer - Buffered Register Load (Update) Mode Select"] +pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; +impl<'a, REG> LdmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn ldmod0(self) -> &'a mut crate::W { + self.variant(Ldmod::Ldmod0) + } + #[doc = "Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn ldmod1(self) -> &'a mut crate::W { + self.variant(Ldmod::Ldmod1) + } +} +#[doc = "Revolution Counter Modulus Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Revmod { + #[doc = "0: Use INDEX pulse to increment/decrement revolution counter (REV)"] + Revmod0 = 0, + #[doc = "1: Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"] + Revmod1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Revmod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REVMOD` reader - Revolution Counter Modulus Enable"] +pub type RevmodR = crate::BitReader; +impl RevmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Revmod { + match self.bits { + false => Revmod::Revmod0, + true => Revmod::Revmod1, + } + } + #[doc = "Use INDEX pulse to increment/decrement revolution counter (REV)"] + #[inline(always)] + pub fn is_revmod0(&self) -> bool { + *self == Revmod::Revmod0 + } + #[doc = "Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"] + #[inline(always)] + pub fn is_revmod1(&self) -> bool { + *self == Revmod::Revmod1 + } +} +#[doc = "Field `REVMOD` writer - Revolution Counter Modulus Enable"] +pub type RevmodW<'a, REG> = crate::BitWriter<'a, REG, Revmod>; +impl<'a, REG> RevmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Use INDEX pulse to increment/decrement revolution counter (REV)"] + #[inline(always)] + pub fn revmod0(self) -> &'a mut crate::W { + self.variant(Revmod::Revmod0) + } + #[doc = "Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"] + #[inline(always)] + pub fn revmod1(self) -> &'a mut crate::W { + self.variant(Revmod::Revmod1) + } +} +#[doc = "Output Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Outctl { + #[doc = "0: POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"] + Outctl0 = 0, + #[doc = "1: All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"] + Outctl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Outctl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OUTCTL` reader - Output Control"] +pub type OutctlR = crate::BitReader; +impl OutctlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Outctl { + match self.bits { + false => Outctl::Outctl0, + true => Outctl::Outctl1, + } + } + #[doc = "POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"] + #[inline(always)] + pub fn is_outctl0(&self) -> bool { + *self == Outctl::Outctl0 + } + #[doc = "All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"] + #[inline(always)] + pub fn is_outctl1(&self) -> bool { + *self == Outctl::Outctl1 + } +} +#[doc = "Field `OUTCTL` writer - Output Control"] +pub type OutctlW<'a, REG> = crate::BitWriter<'a, REG, Outctl>; +impl<'a, REG> OutctlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"] + #[inline(always)] + pub fn outctl0(self) -> &'a mut crate::W { + self.variant(Outctl::Outctl0) + } + #[doc = "All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"] + #[inline(always)] + pub fn outctl1(self) -> &'a mut crate::W { + self.variant(Outctl::Outctl1) + } +} +#[doc = "Period measurement function enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pmen { + #[doc = "0: Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."] + Pmen0 = 0, + #[doc = "1: Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."] + Pmen1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pmen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMEN` reader - Period measurement function enable"] +pub type PmenR = crate::BitReader; +impl PmenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pmen { + match self.bits { + false => Pmen::Pmen0, + true => Pmen::Pmen1, + } + } + #[doc = "Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."] + #[inline(always)] + pub fn is_pmen0(&self) -> bool { + *self == Pmen::Pmen0 + } + #[doc = "Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."] + #[inline(always)] + pub fn is_pmen1(&self) -> bool { + *self == Pmen::Pmen1 + } +} +#[doc = "Field `PMEN` writer - Period measurement function enable"] +pub type PmenW<'a, REG> = crate::BitWriter<'a, REG, Pmen>; +impl<'a, REG> PmenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."] + #[inline(always)] + pub fn pmen0(self) -> &'a mut crate::W { + self.variant(Pmen::Pmen0) + } + #[doc = "Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."] + #[inline(always)] + pub fn pmen1(self) -> &'a mut crate::W { + self.variant(Pmen::Pmen1) + } +} +#[doc = "Enables/disables the position counter to be initialized by Index Event Edge Mark\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Emip { + #[doc = "0: disables the position counter to be initialized by Index Event Edge Mark"] + Emip0 = 0, + #[doc = "1: enables the position counter to be initialized by Index Event Edge Mark."] + Emip1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Emip) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EMIP` reader - Enables/disables the position counter to be initialized by Index Event Edge Mark"] +pub type EmipR = crate::BitReader; +impl EmipR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emip { + match self.bits { + false => Emip::Emip0, + true => Emip::Emip1, + } + } + #[doc = "disables the position counter to be initialized by Index Event Edge Mark"] + #[inline(always)] + pub fn is_emip0(&self) -> bool { + *self == Emip::Emip0 + } + #[doc = "enables the position counter to be initialized by Index Event Edge Mark."] + #[inline(always)] + pub fn is_emip1(&self) -> bool { + *self == Emip::Emip1 + } +} +#[doc = "Field `EMIP` writer - Enables/disables the position counter to be initialized by Index Event Edge Mark"] +pub type EmipW<'a, REG> = crate::BitWriter<'a, REG, Emip>; +impl<'a, REG> EmipW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "disables the position counter to be initialized by Index Event Edge Mark"] + #[inline(always)] + pub fn emip0(self) -> &'a mut crate::W { + self.variant(Emip::Emip0) + } + #[doc = "enables the position counter to be initialized by Index Event Edge Mark."] + #[inline(always)] + pub fn emip1(self) -> &'a mut crate::W { + self.variant(Emip::Emip1) + } +} +#[doc = "Initial Position Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Initpos { + #[doc = "0: Don't initialize position counter on rising edge of TRIGGER"] + Initpos0 = 0, + #[doc = "1: Initialize position counter on rising edge of TRIGGER"] + Initpos1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Initpos) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INITPOS` reader - Initial Position Register"] +pub type InitposR = crate::BitReader; +impl InitposR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Initpos { + match self.bits { + false => Initpos::Initpos0, + true => Initpos::Initpos1, + } + } + #[doc = "Don't initialize position counter on rising edge of TRIGGER"] + #[inline(always)] + pub fn is_initpos0(&self) -> bool { + *self == Initpos::Initpos0 + } + #[doc = "Initialize position counter on rising edge of TRIGGER"] + #[inline(always)] + pub fn is_initpos1(&self) -> bool { + *self == Initpos::Initpos1 + } +} +#[doc = "Field `INITPOS` writer - Initial Position Register"] +pub type InitposW<'a, REG> = crate::BitWriter<'a, REG, Initpos>; +impl<'a, REG> InitposW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Don't initialize position counter on rising edge of TRIGGER"] + #[inline(always)] + pub fn initpos0(self) -> &'a mut crate::W { + self.variant(Initpos::Initpos0) + } + #[doc = "Initialize position counter on rising edge of TRIGGER"] + #[inline(always)] + pub fn initpos1(self) -> &'a mut crate::W { + self.variant(Initpos::Initpos1) + } +} +#[doc = "Count Once\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Once { + #[doc = "0: Position counter counts repeatedly"] + Once0 = 0, + #[doc = "1: Position counter counts until roll-over or roll-under, then stop."] + Once1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Once) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONCE` reader - Count Once"] +pub type OnceR = crate::BitReader; +impl OnceR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Once { + match self.bits { + false => Once::Once0, + true => Once::Once1, + } + } + #[doc = "Position counter counts repeatedly"] + #[inline(always)] + pub fn is_once0(&self) -> bool { + *self == Once::Once0 + } + #[doc = "Position counter counts until roll-over or roll-under, then stop."] + #[inline(always)] + pub fn is_once1(&self) -> bool { + *self == Once::Once1 + } +} +#[doc = "Field `ONCE` writer - Count Once"] +pub type OnceW<'a, REG> = crate::BitWriter<'a, REG, Once>; +impl<'a, REG> OnceW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Position counter counts repeatedly"] + #[inline(always)] + pub fn once0(self) -> &'a mut crate::W { + self.variant(Once::Once0) + } + #[doc = "Position counter counts until roll-over or roll-under, then stop."] + #[inline(always)] + pub fn once1(self) -> &'a mut crate::W { + self.variant(Once::Once1) + } +} +#[doc = "Field `CMODE` reader - Counting Mode"] +pub type CmodeR = crate::FieldReader; +#[doc = "Field `CMODE` writer - Counting Mode"] +pub type CmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Update Hold Registers"] + #[inline(always)] + pub fn updhld(&self) -> UpdhldR { + UpdhldR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Update Position Registers"] + #[inline(always)] + pub fn updpos(&self) -> UpdposR { + UpdposR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Operation Mode Select"] + #[inline(always)] + pub fn opmode(&self) -> OpmodeR { + OpmodeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Buffered Register Load (Update) Mode Select"] + #[inline(always)] + pub fn ldmod(&self) -> LdmodR { + LdmodR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Revolution Counter Modulus Enable"] + #[inline(always)] + pub fn revmod(&self) -> RevmodR { + RevmodR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Output Control"] + #[inline(always)] + pub fn outctl(&self) -> OutctlR { + OutctlR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Period measurement function enable"] + #[inline(always)] + pub fn pmen(&self) -> PmenR { + PmenR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enables/disables the position counter to be initialized by Index Event Edge Mark"] + #[inline(always)] + pub fn emip(&self) -> EmipR { + EmipR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Initial Position Register"] + #[inline(always)] + pub fn initpos(&self) -> InitposR { + InitposR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Count Once"] + #[inline(always)] + pub fn once(&self) -> OnceR { + OnceR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:15 - Counting Mode"] + #[inline(always)] + pub fn cmode(&self) -> CmodeR { + CmodeR::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Update Hold Registers"] + #[inline(always)] + pub fn updhld(&mut self) -> UpdhldW { + UpdhldW::new(self, 0) + } + #[doc = "Bit 1 - Update Position Registers"] + #[inline(always)] + pub fn updpos(&mut self) -> UpdposW { + UpdposW::new(self, 1) + } + #[doc = "Bit 2 - Operation Mode Select"] + #[inline(always)] + pub fn opmode(&mut self) -> OpmodeW { + OpmodeW::new(self, 2) + } + #[doc = "Bit 3 - Buffered Register Load (Update) Mode Select"] + #[inline(always)] + pub fn ldmod(&mut self) -> LdmodW { + LdmodW::new(self, 3) + } + #[doc = "Bit 8 - Revolution Counter Modulus Enable"] + #[inline(always)] + pub fn revmod(&mut self) -> RevmodW { + RevmodW::new(self, 8) + } + #[doc = "Bit 9 - Output Control"] + #[inline(always)] + pub fn outctl(&mut self) -> OutctlW { + OutctlW::new(self, 9) + } + #[doc = "Bit 10 - Period measurement function enable"] + #[inline(always)] + pub fn pmen(&mut self) -> PmenW { + PmenW::new(self, 10) + } + #[doc = "Bit 11 - Enables/disables the position counter to be initialized by Index Event Edge Mark"] + #[inline(always)] + pub fn emip(&mut self) -> EmipW { + EmipW::new(self, 11) + } + #[doc = "Bit 12 - Initial Position Register"] + #[inline(always)] + pub fn initpos(&mut self) -> InitposW { + InitposW::new(self, 12) + } + #[doc = "Bit 13 - Count Once"] + #[inline(always)] + pub fn once(&mut self) -> OnceW { + OnceW::new(self, 13) + } + #[doc = "Bits 14:15 - Counting Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CmodeW { + CmodeW::new(self, 14) + } +} +#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl2Spec; +impl crate::RegisterSpec for Ctrl2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"] +impl crate::Readable for Ctrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"] +impl crate::Writable for Ctrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL2 to value 0"] +impl crate::Resettable for Ctrl2Spec {} diff --git a/mcxa276-pac/src/eqdc0/filt.rs b/mcxa276-pac/src/eqdc0/filt.rs new file mode 100644 index 000000000..dc4b6dc7b --- /dev/null +++ b/mcxa276-pac/src/eqdc0/filt.rs @@ -0,0 +1,126 @@ +#[doc = "Register `FILT` reader"] +pub type R = crate::R; +#[doc = "Register `FILT` writer"] +pub type W = crate::W; +#[doc = "Field `FILT_PER` reader - Input Filter Sample Period"] +pub type FiltPerR = crate::FieldReader; +#[doc = "Field `FILT_PER` writer - Input Filter Sample Period"] +pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `FILT_CNT` reader - Input Filter Sample Count"] +pub type FiltCntR = crate::FieldReader; +#[doc = "Field `FILT_CNT` writer - Input Filter Sample Count"] +pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Filter Clock Source selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FiltCs { + #[doc = "0: Peripheral Clock"] + FiltCs0 = 0, + #[doc = "1: Prescaled peripheral clock by PRSC"] + FiltCs1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FiltCs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILT_CS` reader - Filter Clock Source selection"] +pub type FiltCsR = crate::BitReader; +impl FiltCsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FiltCs { + match self.bits { + false => FiltCs::FiltCs0, + true => FiltCs::FiltCs1, + } + } + #[doc = "Peripheral Clock"] + #[inline(always)] + pub fn is_filt_cs0(&self) -> bool { + *self == FiltCs::FiltCs0 + } + #[doc = "Prescaled peripheral clock by PRSC"] + #[inline(always)] + pub fn is_filt_cs1(&self) -> bool { + *self == FiltCs::FiltCs1 + } +} +#[doc = "Field `FILT_CS` writer - Filter Clock Source selection"] +pub type FiltCsW<'a, REG> = crate::BitWriter<'a, REG, FiltCs>; +impl<'a, REG> FiltCsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral Clock"] + #[inline(always)] + pub fn filt_cs0(self) -> &'a mut crate::W { + self.variant(FiltCs::FiltCs0) + } + #[doc = "Prescaled peripheral clock by PRSC"] + #[inline(always)] + pub fn filt_cs1(self) -> &'a mut crate::W { + self.variant(FiltCs::FiltCs1) + } +} +#[doc = "Field `PRSC` reader - Prescaler"] +pub type PrscR = crate::FieldReader; +#[doc = "Field `PRSC` writer - Prescaler"] +pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:7 - Input Filter Sample Period"] + #[inline(always)] + pub fn filt_per(&self) -> FiltPerR { + FiltPerR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Input Filter Sample Count"] + #[inline(always)] + pub fn filt_cnt(&self) -> FiltCntR { + FiltCntR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Filter Clock Source selection"] + #[inline(always)] + pub fn filt_cs(&self) -> FiltCsR { + FiltCsR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - Prescaler"] + #[inline(always)] + pub fn prsc(&self) -> PrscR { + PrscR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Input Filter Sample Period"] + #[inline(always)] + pub fn filt_per(&mut self) -> FiltPerW { + FiltPerW::new(self, 0) + } + #[doc = "Bits 8:10 - Input Filter Sample Count"] + #[inline(always)] + pub fn filt_cnt(&mut self) -> FiltCntW { + FiltCntW::new(self, 8) + } + #[doc = "Bit 11 - Filter Clock Source selection"] + #[inline(always)] + pub fn filt_cs(&mut self) -> FiltCsW { + FiltCsW::new(self, 11) + } + #[doc = "Bits 12:15 - Prescaler"] + #[inline(always)] + pub fn prsc(&mut self) -> PrscW { + PrscW::new(self, 12) + } +} +#[doc = "Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FiltSpec; +impl crate::RegisterSpec for FiltSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`filt::R`](R) reader structure"] +impl crate::Readable for FiltSpec {} +#[doc = "`write(|w| ..)` method takes [`filt::W`](W) writer structure"] +impl crate::Writable for FiltSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FILT to value 0"] +impl crate::Resettable for FiltSpec {} diff --git a/mcxa276-pac/src/eqdc0/imr.rs b/mcxa276-pac/src/eqdc0/imr.rs new file mode 100644 index 000000000..ed46ea7b4 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/imr.rs @@ -0,0 +1,317 @@ +#[doc = "Register `IMR` reader"] +pub type R = crate::R; +#[doc = "Register `IMR` writer"] +pub type W = crate::W; +#[doc = "Field `HOME_ENABLE` reader - HOME_ENABLE"] +pub type HomeEnableR = crate::BitReader; +#[doc = "Field `INDEX_PRESET` reader - INDEX_PRESET"] +pub type IndexPresetR = crate::BitReader; +#[doc = "Field `PHB` reader - PHB"] +pub type PhbR = crate::BitReader; +#[doc = "Field `PHA` reader - PHA"] +pub type PhaR = crate::BitReader; +#[doc = "Field `FHOM_ENA` reader - filter operation on HOME/ENABLE input"] +pub type FhomEnaR = crate::BitReader; +#[doc = "Field `FHOM_ENA` writer - filter operation on HOME/ENABLE input"] +pub type FhomEnaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIND_PRE` reader - filter operation on INDEX/PRESET input"] +pub type FindPreR = crate::BitReader; +#[doc = "Field `FIND_PRE` writer - filter operation on INDEX/PRESET input"] +pub type FindPreW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FPHB` reader - filter operation on PHASEB input"] +pub type FphbR = crate::BitReader; +#[doc = "Field `FPHB` writer - filter operation on PHASEB input"] +pub type FphbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FPHA` reader - filter operation on PHASEA input"] +pub type FphaR = crate::BitReader; +#[doc = "Field `FPHA` writer - filter operation on PHASEA input"] +pub type FphaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Position Compare 0 Flag Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmpf0 { + #[doc = "0: When the position counter is less than value of COMP0 register"] + Cmpf00 = 0, + #[doc = "1: When the position counter is greater or equal than value of COMP0 register"] + Cmpf01 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmpf0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMPF0` reader - Position Compare 0 Flag Output"] +pub type Cmpf0R = crate::BitReader; +impl Cmpf0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmpf0 { + match self.bits { + false => Cmpf0::Cmpf00, + true => Cmpf0::Cmpf01, + } + } + #[doc = "When the position counter is less than value of COMP0 register"] + #[inline(always)] + pub fn is_cmpf00(&self) -> bool { + *self == Cmpf0::Cmpf00 + } + #[doc = "When the position counter is greater or equal than value of COMP0 register"] + #[inline(always)] + pub fn is_cmpf01(&self) -> bool { + *self == Cmpf0::Cmpf01 + } +} +#[doc = "Position Compare1 Flag Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp1f { + #[doc = "0: When the position counter is less than value of COMP1 register"] + Cmp1f0 = 0, + #[doc = "1: When the position counter is greater or equal than value of COMP1 register"] + Cmp1f1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp1f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP1F` reader - Position Compare1 Flag Output"] +pub type Cmp1fR = crate::BitReader; +impl Cmp1fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp1f { + match self.bits { + false => Cmp1f::Cmp1f0, + true => Cmp1f::Cmp1f1, + } + } + #[doc = "When the position counter is less than value of COMP1 register"] + #[inline(always)] + pub fn is_cmp1f0(&self) -> bool { + *self == Cmp1f::Cmp1f0 + } + #[doc = "When the position counter is greater or equal than value of COMP1 register"] + #[inline(always)] + pub fn is_cmp1f1(&self) -> bool { + *self == Cmp1f::Cmp1f1 + } +} +#[doc = "Position Compare2 Flag Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp2f { + #[doc = "0: When the position counter is less than value of COMP2 register"] + Cmp2f0 = 0, + #[doc = "1: When the position counter is greater or equal than value of COMP2 register"] + Cmp2f1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp2f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP2F` reader - Position Compare2 Flag Output"] +pub type Cmp2fR = crate::BitReader; +impl Cmp2fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp2f { + match self.bits { + false => Cmp2f::Cmp2f0, + true => Cmp2f::Cmp2f1, + } + } + #[doc = "When the position counter is less than value of COMP2 register"] + #[inline(always)] + pub fn is_cmp2f0(&self) -> bool { + *self == Cmp2f::Cmp2f0 + } + #[doc = "When the position counter is greater or equal than value of COMP2 register"] + #[inline(always)] + pub fn is_cmp2f1(&self) -> bool { + *self == Cmp2f::Cmp2f1 + } +} +#[doc = "Position Compare3 Flag Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp3f { + #[doc = "0: When the position counter value is less than value of COMP3 register"] + Cmp3f0 = 0, + #[doc = "1: When the position counter is greater or equal than value of COMP3 register"] + Cmp3f1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp3f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP3F` reader - Position Compare3 Flag Output"] +pub type Cmp3fR = crate::BitReader; +impl Cmp3fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp3f { + match self.bits { + false => Cmp3f::Cmp3f0, + true => Cmp3f::Cmp3f1, + } + } + #[doc = "When the position counter value is less than value of COMP3 register"] + #[inline(always)] + pub fn is_cmp3f0(&self) -> bool { + *self == Cmp3f::Cmp3f0 + } + #[doc = "When the position counter is greater or equal than value of COMP3 register"] + #[inline(always)] + pub fn is_cmp3f1(&self) -> bool { + *self == Cmp3f::Cmp3f1 + } +} +#[doc = "Field `DIRH` reader - Count Direction Flag Hold"] +pub type DirhR = crate::BitReader; +#[doc = "Count Direction Flag Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dir { + #[doc = "0: Current count was in the down direction"] + Dir0 = 0, + #[doc = "1: Current count was in the up direction"] + Dir1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dir) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIR` reader - Count Direction Flag Output"] +pub type DirR = crate::BitReader; +impl DirR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dir { + match self.bits { + false => Dir::Dir0, + true => Dir::Dir1, + } + } + #[doc = "Current count was in the down direction"] + #[inline(always)] + pub fn is_dir0(&self) -> bool { + *self == Dir::Dir0 + } + #[doc = "Current count was in the up direction"] + #[inline(always)] + pub fn is_dir1(&self) -> bool { + *self == Dir::Dir1 + } +} +impl R { + #[doc = "Bit 0 - HOME_ENABLE"] + #[inline(always)] + pub fn home_enable(&self) -> HomeEnableR { + HomeEnableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - INDEX_PRESET"] + #[inline(always)] + pub fn index_preset(&self) -> IndexPresetR { + IndexPresetR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - PHB"] + #[inline(always)] + pub fn phb(&self) -> PhbR { + PhbR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PHA"] + #[inline(always)] + pub fn pha(&self) -> PhaR { + PhaR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - filter operation on HOME/ENABLE input"] + #[inline(always)] + pub fn fhom_ena(&self) -> FhomEnaR { + FhomEnaR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - filter operation on INDEX/PRESET input"] + #[inline(always)] + pub fn find_pre(&self) -> FindPreR { + FindPreR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - filter operation on PHASEB input"] + #[inline(always)] + pub fn fphb(&self) -> FphbR { + FphbR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - filter operation on PHASEA input"] + #[inline(always)] + pub fn fpha(&self) -> FphaR { + FphaR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Position Compare 0 Flag Output"] + #[inline(always)] + pub fn cmpf0(&self) -> Cmpf0R { + Cmpf0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Position Compare1 Flag Output"] + #[inline(always)] + pub fn cmp1f(&self) -> Cmp1fR { + Cmp1fR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Position Compare2 Flag Output"] + #[inline(always)] + pub fn cmp2f(&self) -> Cmp2fR { + Cmp2fR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Position Compare3 Flag Output"] + #[inline(always)] + pub fn cmp3f(&self) -> Cmp3fR { + Cmp3fR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - Count Direction Flag Hold"] + #[inline(always)] + pub fn dirh(&self) -> DirhR { + DirhR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Count Direction Flag Output"] + #[inline(always)] + pub fn dir(&self) -> DirR { + DirR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - filter operation on HOME/ENABLE input"] + #[inline(always)] + pub fn fhom_ena(&mut self) -> FhomEnaW { + FhomEnaW::new(self, 4) + } + #[doc = "Bit 5 - filter operation on INDEX/PRESET input"] + #[inline(always)] + pub fn find_pre(&mut self) -> FindPreW { + FindPreW::new(self, 5) + } + #[doc = "Bit 6 - filter operation on PHASEB input"] + #[inline(always)] + pub fn fphb(&mut self) -> FphbW { + FphbW::new(self, 6) + } + #[doc = "Bit 7 - filter operation on PHASEA input"] + #[inline(always)] + pub fn fpha(&mut self) -> FphaW { + FphaW::new(self, 7) + } +} +#[doc = "Input Monitor Register\n\nYou can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ImrSpec; +impl crate::RegisterSpec for ImrSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for ImrSpec {} +#[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"] +impl crate::Writable for ImrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IMR to value 0"] +impl crate::Resettable for ImrSpec {} diff --git a/mcxa276-pac/src/eqdc0/intctrl.rs b/mcxa276-pac/src/eqdc0/intctrl.rs new file mode 100644 index 000000000..037853cc2 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/intctrl.rs @@ -0,0 +1,1030 @@ +#[doc = "Register `INTCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `INTCTRL` writer"] +pub type W = crate::W; +#[doc = "Simultaneous PHASEA and PHASEB Change Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sabie { + #[doc = "0: Disabled"] + Sabie0 = 0, + #[doc = "1: Enabled"] + Sabie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sabie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SABIE` reader - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] +pub type SabieR = crate::BitReader; +impl SabieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sabie { + match self.bits { + false => Sabie::Sabie0, + true => Sabie::Sabie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_sabie0(&self) -> bool { + *self == Sabie::Sabie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_sabie1(&self) -> bool { + *self == Sabie::Sabie1 + } +} +#[doc = "Field `SABIE` writer - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] +pub type SabieW<'a, REG> = crate::BitWriter<'a, REG, Sabie>; +impl<'a, REG> SabieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn sabie0(self) -> &'a mut crate::W { + self.variant(Sabie::Sabie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn sabie1(self) -> &'a mut crate::W { + self.variant(Sabie::Sabie1) + } +} +#[doc = "Simultaneous PHASEA and PHASEB Change Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sabirq { + #[doc = "0: No simultaneous change of PHASEA and PHASEB has occurred"] + Sabirq0 = 0, + #[doc = "1: A simultaneous change of PHASEA and PHASEB has occurred"] + Sabirq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sabirq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SABIRQ` reader - Simultaneous PHASEA and PHASEB Change Interrupt Request"] +pub type SabirqR = crate::BitReader; +impl SabirqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sabirq { + match self.bits { + false => Sabirq::Sabirq0, + true => Sabirq::Sabirq1, + } + } + #[doc = "No simultaneous change of PHASEA and PHASEB has occurred"] + #[inline(always)] + pub fn is_sabirq0(&self) -> bool { + *self == Sabirq::Sabirq0 + } + #[doc = "A simultaneous change of PHASEA and PHASEB has occurred"] + #[inline(always)] + pub fn is_sabirq1(&self) -> bool { + *self == Sabirq::Sabirq1 + } +} +#[doc = "Field `SABIRQ` writer - Simultaneous PHASEA and PHASEB Change Interrupt Request"] +pub type SabirqW<'a, REG> = crate::BitWriter1C<'a, REG, Sabirq>; +impl<'a, REG> SabirqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No simultaneous change of PHASEA and PHASEB has occurred"] + #[inline(always)] + pub fn sabirq0(self) -> &'a mut crate::W { + self.variant(Sabirq::Sabirq0) + } + #[doc = "A simultaneous change of PHASEA and PHASEB has occurred"] + #[inline(always)] + pub fn sabirq1(self) -> &'a mut crate::W { + self.variant(Sabirq::Sabirq1) + } +} +#[doc = "Count direction change interrupt enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dirie { + #[doc = "0: Disabled"] + Dirie0 = 0, + #[doc = "1: Enabled"] + Dirie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dirie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIRIE` reader - Count direction change interrupt enable"] +pub type DirieR = crate::BitReader; +impl DirieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dirie { + match self.bits { + false => Dirie::Dirie0, + true => Dirie::Dirie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_dirie0(&self) -> bool { + *self == Dirie::Dirie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_dirie1(&self) -> bool { + *self == Dirie::Dirie1 + } +} +#[doc = "Field `DIRIE` writer - Count direction change interrupt enable"] +pub type DirieW<'a, REG> = crate::BitWriter<'a, REG, Dirie>; +impl<'a, REG> DirieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn dirie0(self) -> &'a mut crate::W { + self.variant(Dirie::Dirie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn dirie1(self) -> &'a mut crate::W { + self.variant(Dirie::Dirie1) + } +} +#[doc = "Count direction change interrupt\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dirirq { + #[doc = "0: Count direction unchanged"] + Dirirq0 = 0, + #[doc = "1: Count direction changed"] + Dirirq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dirirq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIRIRQ` reader - Count direction change interrupt"] +pub type DirirqR = crate::BitReader; +impl DirirqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dirirq { + match self.bits { + false => Dirirq::Dirirq0, + true => Dirirq::Dirirq1, + } + } + #[doc = "Count direction unchanged"] + #[inline(always)] + pub fn is_dirirq0(&self) -> bool { + *self == Dirirq::Dirirq0 + } + #[doc = "Count direction changed"] + #[inline(always)] + pub fn is_dirirq1(&self) -> bool { + *self == Dirirq::Dirirq1 + } +} +#[doc = "Field `DIRIRQ` writer - Count direction change interrupt"] +pub type DirirqW<'a, REG> = crate::BitWriter1C<'a, REG, Dirirq>; +impl<'a, REG> DirirqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Count direction unchanged"] + #[inline(always)] + pub fn dirirq0(self) -> &'a mut crate::W { + self.variant(Dirirq::Dirirq0) + } + #[doc = "Count direction changed"] + #[inline(always)] + pub fn dirirq1(self) -> &'a mut crate::W { + self.variant(Dirirq::Dirirq1) + } +} +#[doc = "Roll-under Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ruie { + #[doc = "0: Disabled"] + Ruie0 = 0, + #[doc = "1: Enabled"] + Ruie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ruie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RUIE` reader - Roll-under Interrupt Enable"] +pub type RuieR = crate::BitReader; +impl RuieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ruie { + match self.bits { + false => Ruie::Ruie0, + true => Ruie::Ruie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_ruie0(&self) -> bool { + *self == Ruie::Ruie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_ruie1(&self) -> bool { + *self == Ruie::Ruie1 + } +} +#[doc = "Field `RUIE` writer - Roll-under Interrupt Enable"] +pub type RuieW<'a, REG> = crate::BitWriter<'a, REG, Ruie>; +impl<'a, REG> RuieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn ruie0(self) -> &'a mut crate::W { + self.variant(Ruie::Ruie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn ruie1(self) -> &'a mut crate::W { + self.variant(Ruie::Ruie1) + } +} +#[doc = "Roll-under Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ruirq { + #[doc = "0: No roll-under has occurred"] + Ruirq0 = 0, + #[doc = "1: Roll-under has occurred"] + Ruirq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ruirq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RUIRQ` reader - Roll-under Interrupt Request"] +pub type RuirqR = crate::BitReader; +impl RuirqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ruirq { + match self.bits { + false => Ruirq::Ruirq0, + true => Ruirq::Ruirq1, + } + } + #[doc = "No roll-under has occurred"] + #[inline(always)] + pub fn is_ruirq0(&self) -> bool { + *self == Ruirq::Ruirq0 + } + #[doc = "Roll-under has occurred"] + #[inline(always)] + pub fn is_ruirq1(&self) -> bool { + *self == Ruirq::Ruirq1 + } +} +#[doc = "Field `RUIRQ` writer - Roll-under Interrupt Request"] +pub type RuirqW<'a, REG> = crate::BitWriter1C<'a, REG, Ruirq>; +impl<'a, REG> RuirqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No roll-under has occurred"] + #[inline(always)] + pub fn ruirq0(self) -> &'a mut crate::W { + self.variant(Ruirq::Ruirq0) + } + #[doc = "Roll-under has occurred"] + #[inline(always)] + pub fn ruirq1(self) -> &'a mut crate::W { + self.variant(Ruirq::Ruirq1) + } +} +#[doc = "Roll-over Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Roie { + #[doc = "0: Disabled"] + Roie = 0, + #[doc = "1: Enabled"] + Roie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Roie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROIE` reader - Roll-over Interrupt Enable"] +pub type RoieR = crate::BitReader; +impl RoieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Roie { + match self.bits { + false => Roie::Roie, + true => Roie::Roie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_roie(&self) -> bool { + *self == Roie::Roie + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_roie1(&self) -> bool { + *self == Roie::Roie1 + } +} +#[doc = "Field `ROIE` writer - Roll-over Interrupt Enable"] +pub type RoieW<'a, REG> = crate::BitWriter<'a, REG, Roie>; +impl<'a, REG> RoieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn roie(self) -> &'a mut crate::W { + self.variant(Roie::Roie) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn roie1(self) -> &'a mut crate::W { + self.variant(Roie::Roie1) + } +} +#[doc = "Roll-over Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Roirq { + #[doc = "0: No roll-over has occurred"] + Roirq0 = 0, + #[doc = "1: Roll-over has occurred"] + Roirq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Roirq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROIRQ` reader - Roll-over Interrupt Request"] +pub type RoirqR = crate::BitReader; +impl RoirqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Roirq { + match self.bits { + false => Roirq::Roirq0, + true => Roirq::Roirq1, + } + } + #[doc = "No roll-over has occurred"] + #[inline(always)] + pub fn is_roirq0(&self) -> bool { + *self == Roirq::Roirq0 + } + #[doc = "Roll-over has occurred"] + #[inline(always)] + pub fn is_roirq1(&self) -> bool { + *self == Roirq::Roirq1 + } +} +#[doc = "Field `ROIRQ` writer - Roll-over Interrupt Request"] +pub type RoirqW<'a, REG> = crate::BitWriter1C<'a, REG, Roirq>; +impl<'a, REG> RoirqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No roll-over has occurred"] + #[inline(always)] + pub fn roirq0(self) -> &'a mut crate::W { + self.variant(Roirq::Roirq0) + } + #[doc = "Roll-over has occurred"] + #[inline(always)] + pub fn roirq1(self) -> &'a mut crate::W { + self.variant(Roirq::Roirq1) + } +} +#[doc = "Compare 0 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp0ie { + #[doc = "0: Disabled"] + Cmp0ie0 = 0, + #[doc = "1: Enabled"] + Cmp0ie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp0ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP0IE` reader - Compare 0 Interrupt Enable"] +pub type Cmp0ieR = crate::BitReader; +impl Cmp0ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp0ie { + match self.bits { + false => Cmp0ie::Cmp0ie0, + true => Cmp0ie::Cmp0ie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_cmp0ie0(&self) -> bool { + *self == Cmp0ie::Cmp0ie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_cmp0ie1(&self) -> bool { + *self == Cmp0ie::Cmp0ie1 + } +} +#[doc = "Field `CMP0IE` writer - Compare 0 Interrupt Enable"] +pub type Cmp0ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp0ie>; +impl<'a, REG> Cmp0ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn cmp0ie0(self) -> &'a mut crate::W { + self.variant(Cmp0ie::Cmp0ie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn cmp0ie1(self) -> &'a mut crate::W { + self.variant(Cmp0ie::Cmp0ie1) + } +} +#[doc = "Compare 0 Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp0irq { + #[doc = "0: No match has occurred (the position counter does not match the COMP0 value)"] + Cmp0irq0 = 0, + #[doc = "1: COMP match has occurred (the position counter matches the COMP0 value)"] + Cmp0irq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp0irq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP0IRQ` reader - Compare 0 Interrupt Request"] +pub type Cmp0irqR = crate::BitReader; +impl Cmp0irqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp0irq { + match self.bits { + false => Cmp0irq::Cmp0irq0, + true => Cmp0irq::Cmp0irq1, + } + } + #[doc = "No match has occurred (the position counter does not match the COMP0 value)"] + #[inline(always)] + pub fn is_cmp0irq0(&self) -> bool { + *self == Cmp0irq::Cmp0irq0 + } + #[doc = "COMP match has occurred (the position counter matches the COMP0 value)"] + #[inline(always)] + pub fn is_cmp0irq1(&self) -> bool { + *self == Cmp0irq::Cmp0irq1 + } +} +#[doc = "Field `CMP0IRQ` writer - Compare 0 Interrupt Request"] +pub type Cmp0irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp0irq>; +impl<'a, REG> Cmp0irqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No match has occurred (the position counter does not match the COMP0 value)"] + #[inline(always)] + pub fn cmp0irq0(self) -> &'a mut crate::W { + self.variant(Cmp0irq::Cmp0irq0) + } + #[doc = "COMP match has occurred (the position counter matches the COMP0 value)"] + #[inline(always)] + pub fn cmp0irq1(self) -> &'a mut crate::W { + self.variant(Cmp0irq::Cmp0irq1) + } +} +#[doc = "Compare1 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp1ie { + #[doc = "0: Disabled"] + Cmp1ie0 = 0, + #[doc = "1: Enabled"] + Cmp1ie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp1ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP1IE` reader - Compare1 Interrupt Enable"] +pub type Cmp1ieR = crate::BitReader; +impl Cmp1ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp1ie { + match self.bits { + false => Cmp1ie::Cmp1ie0, + true => Cmp1ie::Cmp1ie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_cmp1ie0(&self) -> bool { + *self == Cmp1ie::Cmp1ie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_cmp1ie1(&self) -> bool { + *self == Cmp1ie::Cmp1ie1 + } +} +#[doc = "Field `CMP1IE` writer - Compare1 Interrupt Enable"] +pub type Cmp1ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp1ie>; +impl<'a, REG> Cmp1ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn cmp1ie0(self) -> &'a mut crate::W { + self.variant(Cmp1ie::Cmp1ie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn cmp1ie1(self) -> &'a mut crate::W { + self.variant(Cmp1ie::Cmp1ie1) + } +} +#[doc = "Compare1 Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp1irq { + #[doc = "0: No match has occurred (the position counter does not match the COMP1 value)"] + Cmp1irq0 = 0, + #[doc = "1: COMP1 match has occurred (the position counter matches the COMP1 value)"] + Cmp1irq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp1irq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP1IRQ` reader - Compare1 Interrupt Request"] +pub type Cmp1irqR = crate::BitReader; +impl Cmp1irqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp1irq { + match self.bits { + false => Cmp1irq::Cmp1irq0, + true => Cmp1irq::Cmp1irq1, + } + } + #[doc = "No match has occurred (the position counter does not match the COMP1 value)"] + #[inline(always)] + pub fn is_cmp1irq0(&self) -> bool { + *self == Cmp1irq::Cmp1irq0 + } + #[doc = "COMP1 match has occurred (the position counter matches the COMP1 value)"] + #[inline(always)] + pub fn is_cmp1irq1(&self) -> bool { + *self == Cmp1irq::Cmp1irq1 + } +} +#[doc = "Field `CMP1IRQ` writer - Compare1 Interrupt Request"] +pub type Cmp1irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp1irq>; +impl<'a, REG> Cmp1irqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No match has occurred (the position counter does not match the COMP1 value)"] + #[inline(always)] + pub fn cmp1irq0(self) -> &'a mut crate::W { + self.variant(Cmp1irq::Cmp1irq0) + } + #[doc = "COMP1 match has occurred (the position counter matches the COMP1 value)"] + #[inline(always)] + pub fn cmp1irq1(self) -> &'a mut crate::W { + self.variant(Cmp1irq::Cmp1irq1) + } +} +#[doc = "Compare2 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp2ie { + #[doc = "0: Disabled"] + Cmp2ie0 = 0, + #[doc = "1: Enabled"] + Cmp2ie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp2ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP2IE` reader - Compare2 Interrupt Enable"] +pub type Cmp2ieR = crate::BitReader; +impl Cmp2ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp2ie { + match self.bits { + false => Cmp2ie::Cmp2ie0, + true => Cmp2ie::Cmp2ie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_cmp2ie0(&self) -> bool { + *self == Cmp2ie::Cmp2ie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_cmp2ie1(&self) -> bool { + *self == Cmp2ie::Cmp2ie1 + } +} +#[doc = "Field `CMP2IE` writer - Compare2 Interrupt Enable"] +pub type Cmp2ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp2ie>; +impl<'a, REG> Cmp2ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn cmp2ie0(self) -> &'a mut crate::W { + self.variant(Cmp2ie::Cmp2ie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn cmp2ie1(self) -> &'a mut crate::W { + self.variant(Cmp2ie::Cmp2ie1) + } +} +#[doc = "Compare2 Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp2irq { + #[doc = "0: No match has occurred (the position counter does not match the COMP2 value)"] + Cmp2irq0 = 0, + #[doc = "1: COMP2 match has occurred (the position counter matches the COMP2 value)"] + Cmp2irq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp2irq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP2IRQ` reader - Compare2 Interrupt Request"] +pub type Cmp2irqR = crate::BitReader; +impl Cmp2irqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp2irq { + match self.bits { + false => Cmp2irq::Cmp2irq0, + true => Cmp2irq::Cmp2irq1, + } + } + #[doc = "No match has occurred (the position counter does not match the COMP2 value)"] + #[inline(always)] + pub fn is_cmp2irq0(&self) -> bool { + *self == Cmp2irq::Cmp2irq0 + } + #[doc = "COMP2 match has occurred (the position counter matches the COMP2 value)"] + #[inline(always)] + pub fn is_cmp2irq1(&self) -> bool { + *self == Cmp2irq::Cmp2irq1 + } +} +#[doc = "Field `CMP2IRQ` writer - Compare2 Interrupt Request"] +pub type Cmp2irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp2irq>; +impl<'a, REG> Cmp2irqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No match has occurred (the position counter does not match the COMP2 value)"] + #[inline(always)] + pub fn cmp2irq0(self) -> &'a mut crate::W { + self.variant(Cmp2irq::Cmp2irq0) + } + #[doc = "COMP2 match has occurred (the position counter matches the COMP2 value)"] + #[inline(always)] + pub fn cmp2irq1(self) -> &'a mut crate::W { + self.variant(Cmp2irq::Cmp2irq1) + } +} +#[doc = "Compare3 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp3ie { + #[doc = "0: Disabled"] + Cmp3ie0 = 0, + #[doc = "1: Enabled"] + Cmp3ie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp3ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP3IE` reader - Compare3 Interrupt Enable"] +pub type Cmp3ieR = crate::BitReader; +impl Cmp3ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp3ie { + match self.bits { + false => Cmp3ie::Cmp3ie0, + true => Cmp3ie::Cmp3ie1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_cmp3ie0(&self) -> bool { + *self == Cmp3ie::Cmp3ie0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_cmp3ie1(&self) -> bool { + *self == Cmp3ie::Cmp3ie1 + } +} +#[doc = "Field `CMP3IE` writer - Compare3 Interrupt Enable"] +pub type Cmp3ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp3ie>; +impl<'a, REG> Cmp3ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn cmp3ie0(self) -> &'a mut crate::W { + self.variant(Cmp3ie::Cmp3ie0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn cmp3ie1(self) -> &'a mut crate::W { + self.variant(Cmp3ie::Cmp3ie1) + } +} +#[doc = "Compare3 Interrupt Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp3irq { + #[doc = "0: No match has occurred (the position counter does not match the COMP3 value)"] + Cmp3irq0 = 0, + #[doc = "1: COMP3 match has occurred (the position counter matches the COMP3 value)"] + Cmp3irq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp3irq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP3IRQ` reader - Compare3 Interrupt Request"] +pub type Cmp3irqR = crate::BitReader; +impl Cmp3irqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp3irq { + match self.bits { + false => Cmp3irq::Cmp3irq0, + true => Cmp3irq::Cmp3irq1, + } + } + #[doc = "No match has occurred (the position counter does not match the COMP3 value)"] + #[inline(always)] + pub fn is_cmp3irq0(&self) -> bool { + *self == Cmp3irq::Cmp3irq0 + } + #[doc = "COMP3 match has occurred (the position counter matches the COMP3 value)"] + #[inline(always)] + pub fn is_cmp3irq1(&self) -> bool { + *self == Cmp3irq::Cmp3irq1 + } +} +#[doc = "Field `CMP3IRQ` writer - Compare3 Interrupt Request"] +pub type Cmp3irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp3irq>; +impl<'a, REG> Cmp3irqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No match has occurred (the position counter does not match the COMP3 value)"] + #[inline(always)] + pub fn cmp3irq0(self) -> &'a mut crate::W { + self.variant(Cmp3irq::Cmp3irq0) + } + #[doc = "COMP3 match has occurred (the position counter matches the COMP3 value)"] + #[inline(always)] + pub fn cmp3irq1(self) -> &'a mut crate::W { + self.variant(Cmp3irq::Cmp3irq1) + } +} +impl R { + #[doc = "Bit 0 - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] + #[inline(always)] + pub fn sabie(&self) -> SabieR { + SabieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Simultaneous PHASEA and PHASEB Change Interrupt Request"] + #[inline(always)] + pub fn sabirq(&self) -> SabirqR { + SabirqR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Count direction change interrupt enable"] + #[inline(always)] + pub fn dirie(&self) -> DirieR { + DirieR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Count direction change interrupt"] + #[inline(always)] + pub fn dirirq(&self) -> DirirqR { + DirirqR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Roll-under Interrupt Enable"] + #[inline(always)] + pub fn ruie(&self) -> RuieR { + RuieR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Roll-under Interrupt Request"] + #[inline(always)] + pub fn ruirq(&self) -> RuirqR { + RuirqR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Roll-over Interrupt Enable"] + #[inline(always)] + pub fn roie(&self) -> RoieR { + RoieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Roll-over Interrupt Request"] + #[inline(always)] + pub fn roirq(&self) -> RoirqR { + RoirqR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0ie(&self) -> Cmp0ieR { + Cmp0ieR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Compare 0 Interrupt Request"] + #[inline(always)] + pub fn cmp0irq(&self) -> Cmp0irqR { + Cmp0irqR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Compare1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1ie(&self) -> Cmp1ieR { + Cmp1ieR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Compare1 Interrupt Request"] + #[inline(always)] + pub fn cmp1irq(&self) -> Cmp1irqR { + Cmp1irqR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Compare2 Interrupt Enable"] + #[inline(always)] + pub fn cmp2ie(&self) -> Cmp2ieR { + Cmp2ieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Compare2 Interrupt Request"] + #[inline(always)] + pub fn cmp2irq(&self) -> Cmp2irqR { + Cmp2irqR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Compare3 Interrupt Enable"] + #[inline(always)] + pub fn cmp3ie(&self) -> Cmp3ieR { + Cmp3ieR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Compare3 Interrupt Request"] + #[inline(always)] + pub fn cmp3irq(&self) -> Cmp3irqR { + Cmp3irqR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] + #[inline(always)] + pub fn sabie(&mut self) -> SabieW { + SabieW::new(self, 0) + } + #[doc = "Bit 1 - Simultaneous PHASEA and PHASEB Change Interrupt Request"] + #[inline(always)] + pub fn sabirq(&mut self) -> SabirqW { + SabirqW::new(self, 1) + } + #[doc = "Bit 2 - Count direction change interrupt enable"] + #[inline(always)] + pub fn dirie(&mut self) -> DirieW { + DirieW::new(self, 2) + } + #[doc = "Bit 3 - Count direction change interrupt"] + #[inline(always)] + pub fn dirirq(&mut self) -> DirirqW { + DirirqW::new(self, 3) + } + #[doc = "Bit 4 - Roll-under Interrupt Enable"] + #[inline(always)] + pub fn ruie(&mut self) -> RuieW { + RuieW::new(self, 4) + } + #[doc = "Bit 5 - Roll-under Interrupt Request"] + #[inline(always)] + pub fn ruirq(&mut self) -> RuirqW { + RuirqW::new(self, 5) + } + #[doc = "Bit 6 - Roll-over Interrupt Enable"] + #[inline(always)] + pub fn roie(&mut self) -> RoieW { + RoieW::new(self, 6) + } + #[doc = "Bit 7 - Roll-over Interrupt Request"] + #[inline(always)] + pub fn roirq(&mut self) -> RoirqW { + RoirqW::new(self, 7) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0ie(&mut self) -> Cmp0ieW { + Cmp0ieW::new(self, 8) + } + #[doc = "Bit 9 - Compare 0 Interrupt Request"] + #[inline(always)] + pub fn cmp0irq(&mut self) -> Cmp0irqW { + Cmp0irqW::new(self, 9) + } + #[doc = "Bit 10 - Compare1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1ie(&mut self) -> Cmp1ieW { + Cmp1ieW::new(self, 10) + } + #[doc = "Bit 11 - Compare1 Interrupt Request"] + #[inline(always)] + pub fn cmp1irq(&mut self) -> Cmp1irqW { + Cmp1irqW::new(self, 11) + } + #[doc = "Bit 12 - Compare2 Interrupt Enable"] + #[inline(always)] + pub fn cmp2ie(&mut self) -> Cmp2ieW { + Cmp2ieW::new(self, 12) + } + #[doc = "Bit 13 - Compare2 Interrupt Request"] + #[inline(always)] + pub fn cmp2irq(&mut self) -> Cmp2irqW { + Cmp2irqW::new(self, 13) + } + #[doc = "Bit 14 - Compare3 Interrupt Enable"] + #[inline(always)] + pub fn cmp3ie(&mut self) -> Cmp3ieW { + Cmp3ieW::new(self, 14) + } + #[doc = "Bit 15 - Compare3 Interrupt Request"] + #[inline(always)] + pub fn cmp3irq(&mut self) -> Cmp3irqW { + Cmp3irqW::new(self, 15) + } +} +#[doc = "Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntctrlSpec; +impl crate::RegisterSpec for IntctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`intctrl::R`](R) reader structure"] +impl crate::Readable for IntctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`intctrl::W`](W) writer structure"] +impl crate::Writable for IntctrlSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0xaaaa; +} +#[doc = "`reset()` method sets INTCTRL to value 0"] +impl crate::Resettable for IntctrlSpec {} diff --git a/mcxa276-pac/src/eqdc0/lastedge.rs b/mcxa276-pac/src/eqdc0/lastedge.rs new file mode 100644 index 000000000..291fcbc53 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lastedge.rs @@ -0,0 +1,22 @@ +#[doc = "Register `LASTEDGE` reader"] +pub type R = crate::R; +#[doc = "Field `LASTEDGE` reader - Last Edge Time Counter"] +pub type LastedgeR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Last Edge Time Counter"] + #[inline(always)] + pub fn lastedge(&self) -> LastedgeR { + LastedgeR::new(self.bits) + } +} +#[doc = "Last Edge Time Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedge::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LastedgeSpec; +impl crate::RegisterSpec for LastedgeSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lastedge::R`](R) reader structure"] +impl crate::Readable for LastedgeSpec {} +#[doc = "`reset()` method sets LASTEDGE to value 0xffff"] +impl crate::Resettable for LastedgeSpec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/eqdc0/lastedgeh.rs b/mcxa276-pac/src/eqdc0/lastedgeh.rs new file mode 100644 index 000000000..c4ed73af4 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lastedgeh.rs @@ -0,0 +1,22 @@ +#[doc = "Register `LASTEDGEH` reader"] +pub type R = crate::R; +#[doc = "Field `LASTEDGEH` reader - Last Edge Time Hold"] +pub type LastedgehR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Last Edge Time Hold"] + #[inline(always)] + pub fn lastedgeh(&self) -> LastedgehR { + LastedgehR::new(self.bits) + } +} +#[doc = "Last Edge Time Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedgeh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LastedgehSpec; +impl crate::RegisterSpec for LastedgehSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lastedgeh::R`](R) reader structure"] +impl crate::Readable for LastedgehSpec {} +#[doc = "`reset()` method sets LASTEDGEH to value 0xffff"] +impl crate::Resettable for LastedgehSpec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/eqdc0/lcomp0.rs b/mcxa276-pac/src/eqdc0/lcomp0.rs new file mode 100644 index 000000000..33f8dda54 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lcomp0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `LCOMP0` reader"] +pub type R = crate::R; +#[doc = "Register `LCOMP0` writer"] +pub type W = crate::W; +#[doc = "Field `LCOMP0` reader - LCOMP0"] +pub type Lcomp0R = crate::FieldReader; +#[doc = "Field `LCOMP0` writer - LCOMP0"] +pub type Lcomp0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - LCOMP0"] + #[inline(always)] + pub fn lcomp0(&self) -> Lcomp0R { + Lcomp0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - LCOMP0"] + #[inline(always)] + pub fn lcomp0(&mut self) -> Lcomp0W { + Lcomp0W::new(self, 0) + } +} +#[doc = "Lower Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcomp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lcomp0Spec; +impl crate::RegisterSpec for Lcomp0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lcomp0::R`](R) reader structure"] +impl crate::Readable for Lcomp0Spec {} +#[doc = "`write(|w| ..)` method takes [`lcomp0::W`](W) writer structure"] +impl crate::Writable for Lcomp0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCOMP0 to value 0"] +impl crate::Resettable for Lcomp0Spec {} diff --git a/mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs b/mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs new file mode 100644 index 000000000..599f3480e --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `LCOMP1` writer"] +pub type W = crate::W; +#[doc = "Field `LCOMP1` writer - LCOMP1"] +pub type Lcomp1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - LCOMP1"] + #[inline(always)] + pub fn lcomp1(&mut self) -> Lcomp1W { + Lcomp1W::new(self, 0) + } +} +#[doc = "Lower Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp1_lcomp1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lcomp1Lcomp1Spec; +impl crate::RegisterSpec for Lcomp1Lcomp1Spec { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [`lcomp1_lcomp1::W`](W) writer structure"] +impl crate::Writable for Lcomp1Lcomp1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCOMP1 to value 0"] +impl crate::Resettable for Lcomp1Lcomp1Spec {} diff --git a/mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs b/mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs new file mode 100644 index 000000000..6beaa54e2 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs @@ -0,0 +1,22 @@ +#[doc = "Register `LCOMP2` writer"] +pub type W = crate::W; +#[doc = "Field `LCOMP2` writer - LCOMP2"] +pub type Lcomp2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - LCOMP2"] + #[inline(always)] + pub fn lcomp2(&mut self) -> Lcomp2W { + Lcomp2W::new(self, 0) + } +} +#[doc = "Lower Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp2_lcomp2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lcomp2Lcomp2Spec; +impl crate::RegisterSpec for Lcomp2Lcomp2Spec { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [`lcomp2_lcomp2::W`](W) writer structure"] +impl crate::Writable for Lcomp2Lcomp2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCOMP2 to value 0"] +impl crate::Resettable for Lcomp2Lcomp2Spec {} diff --git a/mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs b/mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs new file mode 100644 index 000000000..c2befa513 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs @@ -0,0 +1,22 @@ +#[doc = "Register `LCOMP3` writer"] +pub type W = crate::W; +#[doc = "Field `LCOMP3` writer - LCOMP3"] +pub type Lcomp3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - LCOMP3"] + #[inline(always)] + pub fn lcomp3(&mut self) -> Lcomp3W { + Lcomp3W::new(self, 0) + } +} +#[doc = "Lower Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp3_lcomp3::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lcomp3Lcomp3Spec; +impl crate::RegisterSpec for Lcomp3Lcomp3Spec { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [`lcomp3_lcomp3::W`](W) writer structure"] +impl crate::Writable for Lcomp3Lcomp3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCOMP3 to value 0"] +impl crate::Resettable for Lcomp3Lcomp3Spec {} diff --git a/mcxa276-pac/src/eqdc0/linit.rs b/mcxa276-pac/src/eqdc0/linit.rs new file mode 100644 index 000000000..432aaf653 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/linit.rs @@ -0,0 +1,35 @@ +#[doc = "Register `LINIT` reader"] +pub type R = crate::R; +#[doc = "Register `LINIT` writer"] +pub type W = crate::W; +#[doc = "Field `INIT` reader - INIT"] +pub type InitR = crate::FieldReader; +#[doc = "Field `INIT` writer - INIT"] +pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - INIT"] + #[inline(always)] + pub fn init(&self) -> InitR { + InitR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - INIT"] + #[inline(always)] + pub fn init(&mut self) -> InitW { + InitW::new(self, 0) + } +} +#[doc = "Lower Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`linit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LinitSpec; +impl crate::RegisterSpec for LinitSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`linit::R`](R) reader structure"] +impl crate::Readable for LinitSpec {} +#[doc = "`write(|w| ..)` method takes [`linit::W`](W) writer structure"] +impl crate::Writable for LinitSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LINIT to value 0"] +impl crate::Resettable for LinitSpec {} diff --git a/mcxa276-pac/src/eqdc0/lmod.rs b/mcxa276-pac/src/eqdc0/lmod.rs new file mode 100644 index 000000000..5abcab005 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lmod.rs @@ -0,0 +1,35 @@ +#[doc = "Register `LMOD` reader"] +pub type R = crate::R; +#[doc = "Register `LMOD` writer"] +pub type W = crate::W; +#[doc = "Field `MOD` reader - MOD"] +pub type ModR = crate::FieldReader; +#[doc = "Field `MOD` writer - MOD"] +pub type ModW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - MOD"] + #[inline(always)] + pub fn mod_(&self) -> ModR { + ModR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - MOD"] + #[inline(always)] + pub fn mod_(&mut self) -> ModW { + ModW::new(self, 0) + } +} +#[doc = "Lower Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lmod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lmod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LmodSpec; +impl crate::RegisterSpec for LmodSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lmod::R`](R) reader structure"] +impl crate::Readable for LmodSpec {} +#[doc = "`write(|w| ..)` method takes [`lmod::W`](W) writer structure"] +impl crate::Writable for LmodSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LMOD to value 0"] +impl crate::Resettable for LmodSpec {} diff --git a/mcxa276-pac/src/eqdc0/lpos.rs b/mcxa276-pac/src/eqdc0/lpos.rs new file mode 100644 index 000000000..b1d030dd9 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lpos.rs @@ -0,0 +1,35 @@ +#[doc = "Register `LPOS` reader"] +pub type R = crate::R; +#[doc = "Register `LPOS` writer"] +pub type W = crate::W; +#[doc = "Field `POS` reader - POS"] +pub type PosR = crate::FieldReader; +#[doc = "Field `POS` writer - POS"] +pub type PosW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - POS"] + #[inline(always)] + pub fn pos(&self) -> PosR { + PosR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - POS"] + #[inline(always)] + pub fn pos(&mut self) -> PosW { + PosW::new(self, 0) + } +} +#[doc = "Lower Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lpos::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpos::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LposSpec; +impl crate::RegisterSpec for LposSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lpos::R`](R) reader structure"] +impl crate::Readable for LposSpec {} +#[doc = "`write(|w| ..)` method takes [`lpos::W`](W) writer structure"] +impl crate::Writable for LposSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPOS to value 0"] +impl crate::Resettable for LposSpec {} diff --git a/mcxa276-pac/src/eqdc0/lposh.rs b/mcxa276-pac/src/eqdc0/lposh.rs new file mode 100644 index 000000000..d8c490a30 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lposh.rs @@ -0,0 +1,20 @@ +#[doc = "Register `LPOSH` reader"] +pub type R = crate::R; +#[doc = "Field `LPOSH` reader - POSH"] +pub type LposhR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - POSH"] + #[inline(always)] + pub fn lposh(&self) -> LposhR { + LposhR::new(self.bits) + } +} +#[doc = "Lower Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LposhSpec; +impl crate::RegisterSpec for LposhSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lposh::R`](R) reader structure"] +impl crate::Readable for LposhSpec {} +#[doc = "`reset()` method sets LPOSH to value 0"] +impl crate::Resettable for LposhSpec {} diff --git a/mcxa276-pac/src/eqdc0/lposh1_lposh1.rs b/mcxa276-pac/src/eqdc0/lposh1_lposh1.rs new file mode 100644 index 000000000..be342ef9c --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lposh1_lposh1.rs @@ -0,0 +1,20 @@ +#[doc = "Register `LPOSH1` reader"] +pub type R = crate::R; +#[doc = "Field `LPOSH1` reader - LPOSH1"] +pub type Lposh1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - LPOSH1"] + #[inline(always)] + pub fn lposh1(&self) -> Lposh1R { + Lposh1R::new(self.bits) + } +} +#[doc = "Lower Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh1_lposh1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lposh1Lposh1Spec; +impl crate::RegisterSpec for Lposh1Lposh1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lposh1_lposh1::R`](R) reader structure"] +impl crate::Readable for Lposh1Lposh1Spec {} +#[doc = "`reset()` method sets LPOSH1 to value 0"] +impl crate::Resettable for Lposh1Lposh1Spec {} diff --git a/mcxa276-pac/src/eqdc0/lposh2_lposh2.rs b/mcxa276-pac/src/eqdc0/lposh2_lposh2.rs new file mode 100644 index 000000000..561660484 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lposh2_lposh2.rs @@ -0,0 +1,20 @@ +#[doc = "Register `LPOSH2` reader"] +pub type R = crate::R; +#[doc = "Field `LPOSH2` reader - LPOSH2"] +pub type Lposh2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - LPOSH2"] + #[inline(always)] + pub fn lposh2(&self) -> Lposh2R { + Lposh2R::new(self.bits) + } +} +#[doc = "Lower Position Holder Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh2_lposh2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lposh2Lposh2Spec; +impl crate::RegisterSpec for Lposh2Lposh2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lposh2_lposh2::R`](R) reader structure"] +impl crate::Readable for Lposh2Lposh2Spec {} +#[doc = "`reset()` method sets LPOSH2 to value 0"] +impl crate::Resettable for Lposh2Lposh2Spec {} diff --git a/mcxa276-pac/src/eqdc0/lposh3_lposh3.rs b/mcxa276-pac/src/eqdc0/lposh3_lposh3.rs new file mode 100644 index 000000000..5abd16bb2 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lposh3_lposh3.rs @@ -0,0 +1,20 @@ +#[doc = "Register `LPOSH3` reader"] +pub type R = crate::R; +#[doc = "Field `LPOSH3` reader - LPOSH3"] +pub type Lposh3R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - LPOSH3"] + #[inline(always)] + pub fn lposh3(&self) -> Lposh3R { + Lposh3R::new(self.bits) + } +} +#[doc = "Lower Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh3_lposh3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lposh3Lposh3Spec; +impl crate::RegisterSpec for Lposh3Lposh3Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lposh3_lposh3::R`](R) reader structure"] +impl crate::Readable for Lposh3Lposh3Spec {} +#[doc = "`reset()` method sets LPOSH3 to value 0"] +impl crate::Resettable for Lposh3Lposh3Spec {} diff --git a/mcxa276-pac/src/eqdc0/lverid.rs b/mcxa276-pac/src/eqdc0/lverid.rs new file mode 100644 index 000000000..03f861874 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/lverid.rs @@ -0,0 +1,22 @@ +#[doc = "Register `LVERID` reader"] +pub type R = crate::R; +#[doc = "Field `LVERID` reader - LVERID"] +pub type LveridR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - LVERID"] + #[inline(always)] + pub fn lverid(&self) -> LveridR { + LveridR::new(self.bits) + } +} +#[doc = "Lower VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`lverid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LveridSpec; +impl crate::RegisterSpec for LveridSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`lverid::R`](R) reader structure"] +impl crate::Readable for LveridSpec {} +#[doc = "`reset()` method sets LVERID to value 0x01"] +impl crate::Resettable for LveridSpec { + const RESET_VALUE: u16 = 0x01; +} diff --git a/mcxa276-pac/src/eqdc0/posd.rs b/mcxa276-pac/src/eqdc0/posd.rs new file mode 100644 index 000000000..707140327 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/posd.rs @@ -0,0 +1,35 @@ +#[doc = "Register `POSD` reader"] +pub type R = crate::R; +#[doc = "Register `POSD` writer"] +pub type W = crate::W; +#[doc = "Field `POSD` reader - POSD"] +pub type PosdR = crate::FieldReader; +#[doc = "Field `POSD` writer - POSD"] +pub type PosdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - POSD"] + #[inline(always)] + pub fn posd(&self) -> PosdR { + PosdR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - POSD"] + #[inline(always)] + pub fn posd(&mut self) -> PosdW { + PosdW::new(self, 0) + } +} +#[doc = "Position Difference Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`posd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PosdSpec; +impl crate::RegisterSpec for PosdSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`posd::R`](R) reader structure"] +impl crate::Readable for PosdSpec {} +#[doc = "`write(|w| ..)` method takes [`posd::W`](W) writer structure"] +impl crate::Writable for PosdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets POSD to value 0"] +impl crate::Resettable for PosdSpec {} diff --git a/mcxa276-pac/src/eqdc0/posdh.rs b/mcxa276-pac/src/eqdc0/posdh.rs new file mode 100644 index 000000000..894f692af --- /dev/null +++ b/mcxa276-pac/src/eqdc0/posdh.rs @@ -0,0 +1,20 @@ +#[doc = "Register `POSDH` reader"] +pub type R = crate::R; +#[doc = "Field `POSDH` reader - POSDH"] +pub type PosdhR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - POSDH"] + #[inline(always)] + pub fn posdh(&self) -> PosdhR { + PosdhR::new(self.bits) + } +} +#[doc = "Position Difference Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PosdhSpec; +impl crate::RegisterSpec for PosdhSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`posdh::R`](R) reader structure"] +impl crate::Readable for PosdhSpec {} +#[doc = "`reset()` method sets POSDH to value 0"] +impl crate::Resettable for PosdhSpec {} diff --git a/mcxa276-pac/src/eqdc0/posdper.rs b/mcxa276-pac/src/eqdc0/posdper.rs new file mode 100644 index 000000000..37d40edbb --- /dev/null +++ b/mcxa276-pac/src/eqdc0/posdper.rs @@ -0,0 +1,22 @@ +#[doc = "Register `POSDPER` reader"] +pub type R = crate::R; +#[doc = "Field `POSDPER` reader - Position difference period"] +pub type PosdperR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Position difference period"] + #[inline(always)] + pub fn posdper(&self) -> PosdperR { + PosdperR::new(self.bits) + } +} +#[doc = "Position Difference Period Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdper::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PosdperSpec; +impl crate::RegisterSpec for PosdperSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`posdper::R`](R) reader structure"] +impl crate::Readable for PosdperSpec {} +#[doc = "`reset()` method sets POSDPER to value 0xffff"] +impl crate::Resettable for PosdperSpec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/eqdc0/posdperbfr.rs b/mcxa276-pac/src/eqdc0/posdperbfr.rs new file mode 100644 index 000000000..897b8eb70 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/posdperbfr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `POSDPERBFR` reader"] +pub type R = crate::R; +#[doc = "Field `POSDPERBFR` reader - Position difference period buffer"] +pub type PosdperbfrR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Position difference period buffer"] + #[inline(always)] + pub fn posdperbfr(&self) -> PosdperbfrR { + PosdperbfrR::new(self.bits) + } +} +#[doc = "Position Difference Period Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperbfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PosdperbfrSpec; +impl crate::RegisterSpec for PosdperbfrSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`posdperbfr::R`](R) reader structure"] +impl crate::Readable for PosdperbfrSpec {} +#[doc = "`reset()` method sets POSDPERBFR to value 0xffff"] +impl crate::Resettable for PosdperbfrSpec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/eqdc0/posdperh.rs b/mcxa276-pac/src/eqdc0/posdperh.rs new file mode 100644 index 000000000..1a972bc10 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/posdperh.rs @@ -0,0 +1,22 @@ +#[doc = "Register `POSDPERH` reader"] +pub type R = crate::R; +#[doc = "Field `POSDPERH` reader - Position difference period hold"] +pub type PosdperhR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Position difference period hold"] + #[inline(always)] + pub fn posdperh(&self) -> PosdperhR { + PosdperhR::new(self.bits) + } +} +#[doc = "Position Difference Period Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PosdperhSpec; +impl crate::RegisterSpec for PosdperhSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`posdperh::R`](R) reader structure"] +impl crate::Readable for PosdperhSpec {} +#[doc = "`reset()` method sets POSDPERH to value 0xffff"] +impl crate::Resettable for PosdperhSpec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/eqdc0/rev.rs b/mcxa276-pac/src/eqdc0/rev.rs new file mode 100644 index 000000000..73cb03d17 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/rev.rs @@ -0,0 +1,35 @@ +#[doc = "Register `REV` reader"] +pub type R = crate::R; +#[doc = "Register `REV` writer"] +pub type W = crate::W; +#[doc = "Field `REV` reader - REV"] +pub type RevR = crate::FieldReader; +#[doc = "Field `REV` writer - REV"] +pub type RevW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - REV"] + #[inline(always)] + pub fn rev(&self) -> RevR { + RevR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - REV"] + #[inline(always)] + pub fn rev(&mut self) -> RevW { + RevW::new(self, 0) + } +} +#[doc = "Revolution Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rev::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RevSpec; +impl crate::RegisterSpec for RevSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`rev::R`](R) reader structure"] +impl crate::Readable for RevSpec {} +#[doc = "`write(|w| ..)` method takes [`rev::W`](W) writer structure"] +impl crate::Writable for RevSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets REV to value 0"] +impl crate::Resettable for RevSpec {} diff --git a/mcxa276-pac/src/eqdc0/revh.rs b/mcxa276-pac/src/eqdc0/revh.rs new file mode 100644 index 000000000..ef0aa96b1 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/revh.rs @@ -0,0 +1,20 @@ +#[doc = "Register `REVH` reader"] +pub type R = crate::R; +#[doc = "Field `REVH` reader - REVH"] +pub type RevhR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - REVH"] + #[inline(always)] + pub fn revh(&self) -> RevhR { + RevhR::new(self.bits) + } +} +#[doc = "Revolution Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`revh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RevhSpec; +impl crate::RegisterSpec for RevhSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`revh::R`](R) reader structure"] +impl crate::Readable for RevhSpec {} +#[doc = "`reset()` method sets REVH to value 0"] +impl crate::Resettable for RevhSpec {} diff --git a/mcxa276-pac/src/eqdc0/tst.rs b/mcxa276-pac/src/eqdc0/tst.rs new file mode 100644 index 000000000..ae86f62c3 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/tst.rs @@ -0,0 +1,238 @@ +#[doc = "Register `TST` reader"] +pub type R = crate::R; +#[doc = "Register `TST` writer"] +pub type W = crate::W; +#[doc = "Field `TEST_COUNT` reader - TEST_COUNT"] +pub type TestCountR = crate::FieldReader; +#[doc = "Field `TEST_COUNT` writer - TEST_COUNT"] +pub type TestCountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TEST_PERIOD` reader - TEST_PERIOD"] +pub type TestPeriodR = crate::FieldReader; +#[doc = "Field `TEST_PERIOD` writer - TEST_PERIOD"] +pub type TestPeriodW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Quadrature Decoder Negative Signal\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Qdn { + #[doc = "0: Generates a positive quadrature decoder signal"] + Qdn0 = 0, + #[doc = "1: Generates a negative quadrature decoder signal"] + Qdn1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Qdn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `QDN` reader - Quadrature Decoder Negative Signal"] +pub type QdnR = crate::BitReader; +impl QdnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Qdn { + match self.bits { + false => Qdn::Qdn0, + true => Qdn::Qdn1, + } + } + #[doc = "Generates a positive quadrature decoder signal"] + #[inline(always)] + pub fn is_qdn0(&self) -> bool { + *self == Qdn::Qdn0 + } + #[doc = "Generates a negative quadrature decoder signal"] + #[inline(always)] + pub fn is_qdn1(&self) -> bool { + *self == Qdn::Qdn1 + } +} +#[doc = "Field `QDN` writer - Quadrature Decoder Negative Signal"] +pub type QdnW<'a, REG> = crate::BitWriter<'a, REG, Qdn>; +impl<'a, REG> QdnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Generates a positive quadrature decoder signal"] + #[inline(always)] + pub fn qdn0(self) -> &'a mut crate::W { + self.variant(Qdn::Qdn0) + } + #[doc = "Generates a negative quadrature decoder signal"] + #[inline(always)] + pub fn qdn1(self) -> &'a mut crate::W { + self.variant(Qdn::Qdn1) + } +} +#[doc = "Test Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tce { + #[doc = "0: Disabled"] + Tce0 = 0, + #[doc = "1: Enabled"] + Tce1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tce) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCE` reader - Test Counter Enable"] +pub type TceR = crate::BitReader; +impl TceR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tce { + match self.bits { + false => Tce::Tce0, + true => Tce::Tce1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_tce0(&self) -> bool { + *self == Tce::Tce0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_tce1(&self) -> bool { + *self == Tce::Tce1 + } +} +#[doc = "Field `TCE` writer - Test Counter Enable"] +pub type TceW<'a, REG> = crate::BitWriter<'a, REG, Tce>; +impl<'a, REG> TceW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn tce0(self) -> &'a mut crate::W { + self.variant(Tce::Tce0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn tce1(self) -> &'a mut crate::W { + self.variant(Tce::Tce1) + } +} +#[doc = "Test Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ten { + #[doc = "0: Disabled"] + Ten0 = 0, + #[doc = "1: Enabled"] + Ten1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEN` reader - Test Mode Enable"] +pub type TenR = crate::BitReader; +impl TenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ten { + match self.bits { + false => Ten::Ten0, + true => Ten::Ten1, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_ten0(&self) -> bool { + *self == Ten::Ten0 + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_ten1(&self) -> bool { + *self == Ten::Ten1 + } +} +#[doc = "Field `TEN` writer - Test Mode Enable"] +pub type TenW<'a, REG> = crate::BitWriter<'a, REG, Ten>; +impl<'a, REG> TenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn ten0(self) -> &'a mut crate::W { + self.variant(Ten::Ten0) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn ten1(self) -> &'a mut crate::W { + self.variant(Ten::Ten1) + } +} +impl R { + #[doc = "Bits 0:7 - TEST_COUNT"] + #[inline(always)] + pub fn test_count(&self) -> TestCountR { + TestCountR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:12 - TEST_PERIOD"] + #[inline(always)] + pub fn test_period(&self) -> TestPeriodR { + TestPeriodR::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 13 - Quadrature Decoder Negative Signal"] + #[inline(always)] + pub fn qdn(&self) -> QdnR { + QdnR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Test Counter Enable"] + #[inline(always)] + pub fn tce(&self) -> TceR { + TceR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Test Mode Enable"] + #[inline(always)] + pub fn ten(&self) -> TenR { + TenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - TEST_COUNT"] + #[inline(always)] + pub fn test_count(&mut self) -> TestCountW { + TestCountW::new(self, 0) + } + #[doc = "Bits 8:12 - TEST_PERIOD"] + #[inline(always)] + pub fn test_period(&mut self) -> TestPeriodW { + TestPeriodW::new(self, 8) + } + #[doc = "Bit 13 - Quadrature Decoder Negative Signal"] + #[inline(always)] + pub fn qdn(&mut self) -> QdnW { + QdnW::new(self, 13) + } + #[doc = "Bit 14 - Test Counter Enable"] + #[inline(always)] + pub fn tce(&mut self) -> TceW { + TceW::new(self, 14) + } + #[doc = "Bit 15 - Test Mode Enable"] + #[inline(always)] + pub fn ten(&mut self) -> TenW { + TenW::new(self, 15) + } +} +#[doc = "Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstSpec; +impl crate::RegisterSpec for TstSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`tst::R`](R) reader structure"] +impl crate::Readable for TstSpec {} +#[doc = "`write(|w| ..)` method takes [`tst::W`](W) writer structure"] +impl crate::Writable for TstSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TST to value 0"] +impl crate::Resettable for TstSpec {} diff --git a/mcxa276-pac/src/eqdc0/ucomp0.rs b/mcxa276-pac/src/eqdc0/ucomp0.rs new file mode 100644 index 000000000..a53613e16 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/ucomp0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `UCOMP0` reader"] +pub type R = crate::R; +#[doc = "Register `UCOMP0` writer"] +pub type W = crate::W; +#[doc = "Field `UCOMP0` reader - UCOMP0"] +pub type Ucomp0R = crate::FieldReader; +#[doc = "Field `UCOMP0` writer - UCOMP0"] +pub type Ucomp0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - UCOMP0"] + #[inline(always)] + pub fn ucomp0(&self) -> Ucomp0R { + Ucomp0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - UCOMP0"] + #[inline(always)] + pub fn ucomp0(&mut self) -> Ucomp0W { + Ucomp0W::new(self, 0) + } +} +#[doc = "Upper Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucomp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ucomp0Spec; +impl crate::RegisterSpec for Ucomp0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`ucomp0::R`](R) reader structure"] +impl crate::Readable for Ucomp0Spec {} +#[doc = "`write(|w| ..)` method takes [`ucomp0::W`](W) writer structure"] +impl crate::Writable for Ucomp0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets UCOMP0 to value 0x8000"] +impl crate::Resettable for Ucomp0Spec { + const RESET_VALUE: u16 = 0x8000; +} diff --git a/mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs b/mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs new file mode 100644 index 000000000..edeff1ed0 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs @@ -0,0 +1,24 @@ +#[doc = "Register `UCOMP1` writer"] +pub type W = crate::W; +#[doc = "Field `UCOMP1` writer - UCOMP1"] +pub type Ucomp1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - UCOMP1"] + #[inline(always)] + pub fn ucomp1(&mut self) -> Ucomp1W { + Ucomp1W::new(self, 0) + } +} +#[doc = "Upper Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp1_ucomp1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ucomp1Ucomp1Spec; +impl crate::RegisterSpec for Ucomp1Ucomp1Spec { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [`ucomp1_ucomp1::W`](W) writer structure"] +impl crate::Writable for Ucomp1Ucomp1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets UCOMP1 to value 0x8000"] +impl crate::Resettable for Ucomp1Ucomp1Spec { + const RESET_VALUE: u16 = 0x8000; +} diff --git a/mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs b/mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs new file mode 100644 index 000000000..505072d53 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs @@ -0,0 +1,24 @@ +#[doc = "Register `UCOMP2` writer"] +pub type W = crate::W; +#[doc = "Field `UCOMP2` writer - UCOMP2"] +pub type Ucomp2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - UCOMP2"] + #[inline(always)] + pub fn ucomp2(&mut self) -> Ucomp2W { + Ucomp2W::new(self, 0) + } +} +#[doc = "Upper Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp2_ucomp2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ucomp2Ucomp2Spec; +impl crate::RegisterSpec for Ucomp2Ucomp2Spec { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [`ucomp2_ucomp2::W`](W) writer structure"] +impl crate::Writable for Ucomp2Ucomp2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets UCOMP2 to value 0x8000"] +impl crate::Resettable for Ucomp2Ucomp2Spec { + const RESET_VALUE: u16 = 0x8000; +} diff --git a/mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs b/mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs new file mode 100644 index 000000000..2e58ab227 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs @@ -0,0 +1,24 @@ +#[doc = "Register `UCOMP3` writer"] +pub type W = crate::W; +#[doc = "Field `UCOMP3` writer - UCOMP3"] +pub type Ucomp3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - UCOMP3"] + #[inline(always)] + pub fn ucomp3(&mut self) -> Ucomp3W { + Ucomp3W::new(self, 0) + } +} +#[doc = "Upper Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp3_ucomp3::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ucomp3Ucomp3Spec; +impl crate::RegisterSpec for Ucomp3Ucomp3Spec { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [`ucomp3_ucomp3::W`](W) writer structure"] +impl crate::Writable for Ucomp3Ucomp3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets UCOMP3 to value 0x8000"] +impl crate::Resettable for Ucomp3Ucomp3Spec { + const RESET_VALUE: u16 = 0x8000; +} diff --git a/mcxa276-pac/src/eqdc0/uinit.rs b/mcxa276-pac/src/eqdc0/uinit.rs new file mode 100644 index 000000000..1c83a48aa --- /dev/null +++ b/mcxa276-pac/src/eqdc0/uinit.rs @@ -0,0 +1,35 @@ +#[doc = "Register `UINIT` reader"] +pub type R = crate::R; +#[doc = "Register `UINIT` writer"] +pub type W = crate::W; +#[doc = "Field `INIT` reader - INIT"] +pub type InitR = crate::FieldReader; +#[doc = "Field `INIT` writer - INIT"] +pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - INIT"] + #[inline(always)] + pub fn init(&self) -> InitR { + InitR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - INIT"] + #[inline(always)] + pub fn init(&mut self) -> InitW { + InitW::new(self, 0) + } +} +#[doc = "Upper Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uinit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uinit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UinitSpec; +impl crate::RegisterSpec for UinitSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`uinit::R`](R) reader structure"] +impl crate::Readable for UinitSpec {} +#[doc = "`write(|w| ..)` method takes [`uinit::W`](W) writer structure"] +impl crate::Writable for UinitSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets UINIT to value 0"] +impl crate::Resettable for UinitSpec {} diff --git a/mcxa276-pac/src/eqdc0/umod.rs b/mcxa276-pac/src/eqdc0/umod.rs new file mode 100644 index 000000000..d27df9085 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/umod.rs @@ -0,0 +1,35 @@ +#[doc = "Register `UMOD` reader"] +pub type R = crate::R; +#[doc = "Register `UMOD` writer"] +pub type W = crate::W; +#[doc = "Field `MOD` reader - MOD"] +pub type ModR = crate::FieldReader; +#[doc = "Field `MOD` writer - MOD"] +pub type ModW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - MOD"] + #[inline(always)] + pub fn mod_(&self) -> ModR { + ModR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - MOD"] + #[inline(always)] + pub fn mod_(&mut self) -> ModW { + ModW::new(self, 0) + } +} +#[doc = "Upper Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`umod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`umod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UmodSpec; +impl crate::RegisterSpec for UmodSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`umod::R`](R) reader structure"] +impl crate::Readable for UmodSpec {} +#[doc = "`write(|w| ..)` method takes [`umod::W`](W) writer structure"] +impl crate::Writable for UmodSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets UMOD to value 0"] +impl crate::Resettable for UmodSpec {} diff --git a/mcxa276-pac/src/eqdc0/upos.rs b/mcxa276-pac/src/eqdc0/upos.rs new file mode 100644 index 000000000..6b0c64027 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/upos.rs @@ -0,0 +1,35 @@ +#[doc = "Register `UPOS` reader"] +pub type R = crate::R; +#[doc = "Register `UPOS` writer"] +pub type W = crate::W; +#[doc = "Field `POS` reader - POS"] +pub type PosR = crate::FieldReader; +#[doc = "Field `POS` writer - POS"] +pub type PosW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - POS"] + #[inline(always)] + pub fn pos(&self) -> PosR { + PosR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - POS"] + #[inline(always)] + pub fn pos(&mut self) -> PosW { + PosW::new(self, 0) + } +} +#[doc = "Upper Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`upos::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`upos::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UposSpec; +impl crate::RegisterSpec for UposSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`upos::R`](R) reader structure"] +impl crate::Readable for UposSpec {} +#[doc = "`write(|w| ..)` method takes [`upos::W`](W) writer structure"] +impl crate::Writable for UposSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets UPOS to value 0"] +impl crate::Resettable for UposSpec {} diff --git a/mcxa276-pac/src/eqdc0/uposh.rs b/mcxa276-pac/src/eqdc0/uposh.rs new file mode 100644 index 000000000..bc8b94910 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/uposh.rs @@ -0,0 +1,20 @@ +#[doc = "Register `UPOSH` reader"] +pub type R = crate::R; +#[doc = "Field `POSH` reader - POSH"] +pub type PoshR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - POSH"] + #[inline(always)] + pub fn posh(&self) -> PoshR { + PoshR::new(self.bits) + } +} +#[doc = "Upper Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UposhSpec; +impl crate::RegisterSpec for UposhSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`uposh::R`](R) reader structure"] +impl crate::Readable for UposhSpec {} +#[doc = "`reset()` method sets UPOSH to value 0"] +impl crate::Resettable for UposhSpec {} diff --git a/mcxa276-pac/src/eqdc0/uposh1_uposh1.rs b/mcxa276-pac/src/eqdc0/uposh1_uposh1.rs new file mode 100644 index 000000000..ccda5f8f8 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/uposh1_uposh1.rs @@ -0,0 +1,20 @@ +#[doc = "Register `UPOSH1` reader"] +pub type R = crate::R; +#[doc = "Field `UPOSH1` reader - UPOSH1"] +pub type Uposh1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - UPOSH1"] + #[inline(always)] + pub fn uposh1(&self) -> Uposh1R { + Uposh1R::new(self.bits) + } +} +#[doc = "Upper Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh1_uposh1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Uposh1Uposh1Spec; +impl crate::RegisterSpec for Uposh1Uposh1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`uposh1_uposh1::R`](R) reader structure"] +impl crate::Readable for Uposh1Uposh1Spec {} +#[doc = "`reset()` method sets UPOSH1 to value 0"] +impl crate::Resettable for Uposh1Uposh1Spec {} diff --git a/mcxa276-pac/src/eqdc0/uposh2_uposh2.rs b/mcxa276-pac/src/eqdc0/uposh2_uposh2.rs new file mode 100644 index 000000000..a26dbcdf8 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/uposh2_uposh2.rs @@ -0,0 +1,20 @@ +#[doc = "Register `UPOSH2` reader"] +pub type R = crate::R; +#[doc = "Field `UPOSH2` reader - UPOSH2"] +pub type Uposh2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - UPOSH2"] + #[inline(always)] + pub fn uposh2(&self) -> Uposh2R { + Uposh2R::new(self.bits) + } +} +#[doc = "Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh2_uposh2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Uposh2Uposh2Spec; +impl crate::RegisterSpec for Uposh2Uposh2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`uposh2_uposh2::R`](R) reader structure"] +impl crate::Readable for Uposh2Uposh2Spec {} +#[doc = "`reset()` method sets UPOSH2 to value 0"] +impl crate::Resettable for Uposh2Uposh2Spec {} diff --git a/mcxa276-pac/src/eqdc0/uposh3_uposh3.rs b/mcxa276-pac/src/eqdc0/uposh3_uposh3.rs new file mode 100644 index 000000000..5d2f4a77d --- /dev/null +++ b/mcxa276-pac/src/eqdc0/uposh3_uposh3.rs @@ -0,0 +1,20 @@ +#[doc = "Register `UPOSH3` reader"] +pub type R = crate::R; +#[doc = "Field `UPOSH3` reader - UPOSH3"] +pub type Uposh3R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - UPOSH3"] + #[inline(always)] + pub fn uposh3(&self) -> Uposh3R { + Uposh3R::new(self.bits) + } +} +#[doc = "Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh3_uposh3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Uposh3Uposh3Spec; +impl crate::RegisterSpec for Uposh3Uposh3Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`uposh3_uposh3::R`](R) reader structure"] +impl crate::Readable for Uposh3Uposh3Spec {} +#[doc = "`reset()` method sets UPOSH3 to value 0"] +impl crate::Resettable for Uposh3Uposh3Spec {} diff --git a/mcxa276-pac/src/eqdc0/uverid.rs b/mcxa276-pac/src/eqdc0/uverid.rs new file mode 100644 index 000000000..23baa3db6 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/uverid.rs @@ -0,0 +1,22 @@ +#[doc = "Register `UVERID` reader"] +pub type R = crate::R; +#[doc = "Field `UVERID` reader - UVERID"] +pub type UveridR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - UVERID"] + #[inline(always)] + pub fn uverid(&self) -> UveridR { + UveridR::new(self.bits) + } +} +#[doc = "Upper VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`uverid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UveridSpec; +impl crate::RegisterSpec for UveridSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`uverid::R`](R) reader structure"] +impl crate::Readable for UveridSpec {} +#[doc = "`reset()` method sets UVERID to value 0x01"] +impl crate::Resettable for UveridSpec { + const RESET_VALUE: u16 = 0x01; +} diff --git a/mcxa276-pac/src/eqdc0/wtr.rs b/mcxa276-pac/src/eqdc0/wtr.rs new file mode 100644 index 000000000..75f973d46 --- /dev/null +++ b/mcxa276-pac/src/eqdc0/wtr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `WTR` reader"] +pub type R = crate::R; +#[doc = "Register `WTR` writer"] +pub type W = crate::W; +#[doc = "Field `WDOG` reader - WDOG"] +pub type WdogR = crate::FieldReader; +#[doc = "Field `WDOG` writer - WDOG"] +pub type WdogW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - WDOG"] + #[inline(always)] + pub fn wdog(&self) -> WdogR { + WdogR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - WDOG"] + #[inline(always)] + pub fn wdog(&mut self) -> WdogW { + WdogW::new(self, 0) + } +} +#[doc = "Watchdog Timeout Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WtrSpec; +impl crate::RegisterSpec for WtrSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`wtr::R`](R) reader structure"] +impl crate::Readable for WtrSpec {} +#[doc = "`write(|w| ..)` method takes [`wtr::W`](W) writer structure"] +impl crate::Writable for WtrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WTR to value 0"] +impl crate::Resettable for WtrSpec {} diff --git a/mcxa276-pac/src/erm0.rs b/mcxa276-pac/src/erm0.rs new file mode 100644 index 000000000..61516f9c6 --- /dev/null +++ b/mcxa276-pac/src/erm0.rs @@ -0,0 +1,75 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cr0: Cr0, + _reserved1: [u8; 0x0c], + sr0: Sr0, + _reserved2: [u8; 0xec], + ear0: Ear0, + syn0: Syn0, + corr_err_cnt0: CorrErrCnt0, + _reserved5: [u8; 0x0c], + corr_err_cnt1: CorrErrCnt1, +} +impl RegisterBlock { + #[doc = "0x00 - ERM Configuration Register 0"] + #[inline(always)] + pub const fn cr0(&self) -> &Cr0 { + &self.cr0 + } + #[doc = "0x10 - ERM Status Register 0"] + #[inline(always)] + pub const fn sr0(&self) -> &Sr0 { + &self.sr0 + } + #[doc = "0x100 - ERM Memory 0 Error Address Register"] + #[inline(always)] + pub const fn ear0(&self) -> &Ear0 { + &self.ear0 + } + #[doc = "0x104 - ERM Memory 0 Syndrome Register"] + #[inline(always)] + pub const fn syn0(&self) -> &Syn0 { + &self.syn0 + } + #[doc = "0x108 - ERM Memory 0 Correctable Error Count Register"] + #[inline(always)] + pub const fn corr_err_cnt0(&self) -> &CorrErrCnt0 { + &self.corr_err_cnt0 + } + #[doc = "0x118 - ERM Memory 1 Correctable Error Count Register"] + #[inline(always)] + pub const fn corr_err_cnt1(&self) -> &CorrErrCnt1 { + &self.corr_err_cnt1 + } +} +#[doc = "CR0 (rw) register accessor: ERM Configuration Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr0`] module"] +#[doc(alias = "CR0")] +pub type Cr0 = crate::Reg; +#[doc = "ERM Configuration Register 0"] +pub mod cr0; +#[doc = "SR0 (rw) register accessor: ERM Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr0`] module"] +#[doc(alias = "SR0")] +pub type Sr0 = crate::Reg; +#[doc = "ERM Status Register 0"] +pub mod sr0; +#[doc = "EAR0 (r) register accessor: ERM Memory 0 Error Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ear0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ear0`] module"] +#[doc(alias = "EAR0")] +pub type Ear0 = crate::Reg; +#[doc = "ERM Memory 0 Error Address Register"] +pub mod ear0; +#[doc = "SYN0 (r) register accessor: ERM Memory 0 Syndrome Register\n\nYou can [`read`](crate::Reg::read) this register and get [`syn0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syn0`] module"] +#[doc(alias = "SYN0")] +pub type Syn0 = crate::Reg; +#[doc = "ERM Memory 0 Syndrome Register"] +pub mod syn0; +#[doc = "CORR_ERR_CNT0 (rw) register accessor: ERM Memory 0 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@corr_err_cnt0`] module"] +#[doc(alias = "CORR_ERR_CNT0")] +pub type CorrErrCnt0 = crate::Reg; +#[doc = "ERM Memory 0 Correctable Error Count Register"] +pub mod corr_err_cnt0; +#[doc = "CORR_ERR_CNT1 (rw) register accessor: ERM Memory 1 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@corr_err_cnt1`] module"] +#[doc(alias = "CORR_ERR_CNT1")] +pub type CorrErrCnt1 = crate::Reg; +#[doc = "ERM Memory 1 Correctable Error Count Register"] +pub mod corr_err_cnt1; diff --git a/mcxa276-pac/src/erm0/corr_err_cnt0.rs b/mcxa276-pac/src/erm0/corr_err_cnt0.rs new file mode 100644 index 000000000..4cc41ae4c --- /dev/null +++ b/mcxa276-pac/src/erm0/corr_err_cnt0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CORR_ERR_CNT0` reader"] +pub type R = crate::R; +#[doc = "Register `CORR_ERR_CNT0` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - Memory n Correctable Error Count"] +pub type CountR = crate::FieldReader; +#[doc = "Field `COUNT` writer - Memory n Correctable Error Count"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Memory n Correctable Error Count"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Memory n Correctable Error Count"] + #[inline(always)] + pub fn count(&mut self) -> CountW { + CountW::new(self, 0) + } +} +#[doc = "ERM Memory 0 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CorrErrCnt0Spec; +impl crate::RegisterSpec for CorrErrCnt0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`corr_err_cnt0::R`](R) reader structure"] +impl crate::Readable for CorrErrCnt0Spec {} +#[doc = "`write(|w| ..)` method takes [`corr_err_cnt0::W`](W) writer structure"] +impl crate::Writable for CorrErrCnt0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CORR_ERR_CNT0 to value 0"] +impl crate::Resettable for CorrErrCnt0Spec {} diff --git a/mcxa276-pac/src/erm0/corr_err_cnt1.rs b/mcxa276-pac/src/erm0/corr_err_cnt1.rs new file mode 100644 index 000000000..73c5cbbaf --- /dev/null +++ b/mcxa276-pac/src/erm0/corr_err_cnt1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CORR_ERR_CNT1` reader"] +pub type R = crate::R; +#[doc = "Register `CORR_ERR_CNT1` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - Memory n Correctable Error Count"] +pub type CountR = crate::FieldReader; +#[doc = "Field `COUNT` writer - Memory n Correctable Error Count"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Memory n Correctable Error Count"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Memory n Correctable Error Count"] + #[inline(always)] + pub fn count(&mut self) -> CountW { + CountW::new(self, 0) + } +} +#[doc = "ERM Memory 1 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CorrErrCnt1Spec; +impl crate::RegisterSpec for CorrErrCnt1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`corr_err_cnt1::R`](R) reader structure"] +impl crate::Readable for CorrErrCnt1Spec {} +#[doc = "`write(|w| ..)` method takes [`corr_err_cnt1::W`](W) writer structure"] +impl crate::Writable for CorrErrCnt1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CORR_ERR_CNT1 to value 0"] +impl crate::Resettable for CorrErrCnt1Spec {} diff --git a/mcxa276-pac/src/erm0/cr0.rs b/mcxa276-pac/src/erm0/cr0.rs new file mode 100644 index 000000000..5bb94e07c --- /dev/null +++ b/mcxa276-pac/src/erm0/cr0.rs @@ -0,0 +1,273 @@ +#[doc = "Register `CR0` reader"] +pub type R = crate::R; +#[doc = "Register `CR0` writer"] +pub type W = crate::W; +#[doc = "ENCIE1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Encie1 { + #[doc = "0: Interrupt notification of Memory 1 non-correctable error events is disabled."] + Disable = 0, + #[doc = "1: Interrupt notification of Memory 1 non-correctable error events is enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Encie1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENCIE1` reader - ENCIE1"] +pub type Encie1R = crate::BitReader; +impl Encie1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Encie1 { + match self.bits { + false => Encie1::Disable, + true => Encie1::Enable, + } + } + #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Encie1::Disable + } + #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Encie1::Enable + } +} +#[doc = "Field `ENCIE1` writer - ENCIE1"] +pub type Encie1W<'a, REG> = crate::BitWriter<'a, REG, Encie1>; +impl<'a, REG> Encie1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Encie1::Disable) + } + #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Encie1::Enable) + } +} +#[doc = "ESCIE1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Escie1 { + #[doc = "0: Interrupt notification of Memory 1 single-bit correction events is disabled."] + Disable = 0, + #[doc = "1: Interrupt notification of Memory 1 single-bit correction events is enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Escie1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ESCIE1` reader - ESCIE1"] +pub type Escie1R = crate::BitReader; +impl Escie1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Escie1 { + match self.bits { + false => Escie1::Disable, + true => Escie1::Enable, + } + } + #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Escie1::Disable + } + #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Escie1::Enable + } +} +#[doc = "Field `ESCIE1` writer - ESCIE1"] +pub type Escie1W<'a, REG> = crate::BitWriter<'a, REG, Escie1>; +impl<'a, REG> Escie1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Escie1::Disable) + } + #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Escie1::Enable) + } +} +#[doc = "ENCIE0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Encie0 { + #[doc = "0: Interrupt notification of Memory 0 non-correctable error events is disabled."] + Disable = 0, + #[doc = "1: Interrupt notification of Memory 0 non-correctable error events is enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Encie0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENCIE0` reader - ENCIE0"] +pub type Encie0R = crate::BitReader; +impl Encie0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Encie0 { + match self.bits { + false => Encie0::Disable, + true => Encie0::Enable, + } + } + #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Encie0::Disable + } + #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Encie0::Enable + } +} +#[doc = "Field `ENCIE0` writer - ENCIE0"] +pub type Encie0W<'a, REG> = crate::BitWriter<'a, REG, Encie0>; +impl<'a, REG> Encie0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Encie0::Disable) + } + #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Encie0::Enable) + } +} +#[doc = "ESCIE0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Escie0 { + #[doc = "0: Interrupt notification of Memory 0 single-bit correction events is disabled."] + Disable = 0, + #[doc = "1: Interrupt notification of Memory 0 single-bit correction events is enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Escie0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ESCIE0` reader - ESCIE0"] +pub type Escie0R = crate::BitReader; +impl Escie0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Escie0 { + match self.bits { + false => Escie0::Disable, + true => Escie0::Enable, + } + } + #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Escie0::Disable + } + #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Escie0::Enable + } +} +#[doc = "Field `ESCIE0` writer - ESCIE0"] +pub type Escie0W<'a, REG> = crate::BitWriter<'a, REG, Escie0>; +impl<'a, REG> Escie0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Escie0::Disable) + } + #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Escie0::Enable) + } +} +impl R { + #[doc = "Bit 26 - ENCIE1"] + #[inline(always)] + pub fn encie1(&self) -> Encie1R { + Encie1R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - ESCIE1"] + #[inline(always)] + pub fn escie1(&self) -> Escie1R { + Escie1R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 30 - ENCIE0"] + #[inline(always)] + pub fn encie0(&self) -> Encie0R { + Encie0R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ESCIE0"] + #[inline(always)] + pub fn escie0(&self) -> Escie0R { + Escie0R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 26 - ENCIE1"] + #[inline(always)] + pub fn encie1(&mut self) -> Encie1W { + Encie1W::new(self, 26) + } + #[doc = "Bit 27 - ESCIE1"] + #[inline(always)] + pub fn escie1(&mut self) -> Escie1W { + Escie1W::new(self, 27) + } + #[doc = "Bit 30 - ENCIE0"] + #[inline(always)] + pub fn encie0(&mut self) -> Encie0W { + Encie0W::new(self, 30) + } + #[doc = "Bit 31 - ESCIE0"] + #[inline(always)] + pub fn escie0(&mut self) -> Escie0W { + Escie0W::new(self, 31) + } +} +#[doc = "ERM Configuration Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cr0Spec; +impl crate::RegisterSpec for Cr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr0::R`](R) reader structure"] +impl crate::Readable for Cr0Spec {} +#[doc = "`write(|w| ..)` method takes [`cr0::W`](W) writer structure"] +impl crate::Writable for Cr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CR0 to value 0"] +impl crate::Resettable for Cr0Spec {} diff --git a/mcxa276-pac/src/erm0/ear0.rs b/mcxa276-pac/src/erm0/ear0.rs new file mode 100644 index 000000000..94c672c4f --- /dev/null +++ b/mcxa276-pac/src/erm0/ear0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `EAR0` reader"] +pub type R = crate::R; +#[doc = "Field `EAR` reader - EAR"] +pub type EarR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - EAR"] + #[inline(always)] + pub fn ear(&self) -> EarR { + EarR::new(self.bits) + } +} +#[doc = "ERM Memory 0 Error Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ear0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ear0Spec; +impl crate::RegisterSpec for Ear0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ear0::R`](R) reader structure"] +impl crate::Readable for Ear0Spec {} +#[doc = "`reset()` method sets EAR0 to value 0"] +impl crate::Resettable for Ear0Spec {} diff --git a/mcxa276-pac/src/erm0/sr0.rs b/mcxa276-pac/src/erm0/sr0.rs new file mode 100644 index 000000000..6a8ff0995 --- /dev/null +++ b/mcxa276-pac/src/erm0/sr0.rs @@ -0,0 +1,274 @@ +#[doc = "Register `SR0` reader"] +pub type R = crate::R; +#[doc = "Register `SR0` writer"] +pub type W = crate::W; +#[doc = "NCE1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nce1 { + #[doc = "0: No non-correctable error event on Memory 1 detected."] + NoError = 0, + #[doc = "1: Non-correctable error event on Memory 1 detected."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nce1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NCE1` reader - NCE1"] +pub type Nce1R = crate::BitReader; +impl Nce1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nce1 { + match self.bits { + false => Nce1::NoError, + true => Nce1::Error, + } + } + #[doc = "No non-correctable error event on Memory 1 detected."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Nce1::NoError + } + #[doc = "Non-correctable error event on Memory 1 detected."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Nce1::Error + } +} +#[doc = "Field `NCE1` writer - NCE1"] +pub type Nce1W<'a, REG> = crate::BitWriter1C<'a, REG, Nce1>; +impl<'a, REG> Nce1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No non-correctable error event on Memory 1 detected."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Nce1::NoError) + } + #[doc = "Non-correctable error event on Memory 1 detected."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Nce1::Error) + } +} +#[doc = "SBC1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbc1 { + #[doc = "0: No single-bit correction event on Memory 1 detected."] + NoEvent = 0, + #[doc = "1: Single-bit correction event on Memory 1 detected."] + Event = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBC1` reader - SBC1"] +pub type Sbc1R = crate::BitReader; +impl Sbc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbc1 { + match self.bits { + false => Sbc1::NoEvent, + true => Sbc1::Event, + } + } + #[doc = "No single-bit correction event on Memory 1 detected."] + #[inline(always)] + pub fn is_no_event(&self) -> bool { + *self == Sbc1::NoEvent + } + #[doc = "Single-bit correction event on Memory 1 detected."] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == Sbc1::Event + } +} +#[doc = "Field `SBC1` writer - SBC1"] +pub type Sbc1W<'a, REG> = crate::BitWriter1C<'a, REG, Sbc1>; +impl<'a, REG> Sbc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No single-bit correction event on Memory 1 detected."] + #[inline(always)] + pub fn no_event(self) -> &'a mut crate::W { + self.variant(Sbc1::NoEvent) + } + #[doc = "Single-bit correction event on Memory 1 detected."] + #[inline(always)] + pub fn event(self) -> &'a mut crate::W { + self.variant(Sbc1::Event) + } +} +#[doc = "NCE0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nce0 { + #[doc = "0: No non-correctable error event on Memory 0 detected."] + NoError = 0, + #[doc = "1: Non-correctable error event on Memory 0 detected."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nce0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NCE0` reader - NCE0"] +pub type Nce0R = crate::BitReader; +impl Nce0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nce0 { + match self.bits { + false => Nce0::NoError, + true => Nce0::Error, + } + } + #[doc = "No non-correctable error event on Memory 0 detected."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Nce0::NoError + } + #[doc = "Non-correctable error event on Memory 0 detected."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Nce0::Error + } +} +#[doc = "Field `NCE0` writer - NCE0"] +pub type Nce0W<'a, REG> = crate::BitWriter1C<'a, REG, Nce0>; +impl<'a, REG> Nce0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No non-correctable error event on Memory 0 detected."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Nce0::NoError) + } + #[doc = "Non-correctable error event on Memory 0 detected."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Nce0::Error) + } +} +#[doc = "SBC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbc0 { + #[doc = "0: No single-bit correction event on Memory 0 detected."] + NoEvent = 0, + #[doc = "1: Single-bit correction event on Memory 0 detected."] + Event = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBC0` reader - SBC0"] +pub type Sbc0R = crate::BitReader; +impl Sbc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbc0 { + match self.bits { + false => Sbc0::NoEvent, + true => Sbc0::Event, + } + } + #[doc = "No single-bit correction event on Memory 0 detected."] + #[inline(always)] + pub fn is_no_event(&self) -> bool { + *self == Sbc0::NoEvent + } + #[doc = "Single-bit correction event on Memory 0 detected."] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == Sbc0::Event + } +} +#[doc = "Field `SBC0` writer - SBC0"] +pub type Sbc0W<'a, REG> = crate::BitWriter1C<'a, REG, Sbc0>; +impl<'a, REG> Sbc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No single-bit correction event on Memory 0 detected."] + #[inline(always)] + pub fn no_event(self) -> &'a mut crate::W { + self.variant(Sbc0::NoEvent) + } + #[doc = "Single-bit correction event on Memory 0 detected."] + #[inline(always)] + pub fn event(self) -> &'a mut crate::W { + self.variant(Sbc0::Event) + } +} +impl R { + #[doc = "Bit 26 - NCE1"] + #[inline(always)] + pub fn nce1(&self) -> Nce1R { + Nce1R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - SBC1"] + #[inline(always)] + pub fn sbc1(&self) -> Sbc1R { + Sbc1R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 30 - NCE0"] + #[inline(always)] + pub fn nce0(&self) -> Nce0R { + Nce0R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - SBC0"] + #[inline(always)] + pub fn sbc0(&self) -> Sbc0R { + Sbc0R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 26 - NCE1"] + #[inline(always)] + pub fn nce1(&mut self) -> Nce1W { + Nce1W::new(self, 26) + } + #[doc = "Bit 27 - SBC1"] + #[inline(always)] + pub fn sbc1(&mut self) -> Sbc1W { + Sbc1W::new(self, 27) + } + #[doc = "Bit 30 - NCE0"] + #[inline(always)] + pub fn nce0(&mut self) -> Nce0W { + Nce0W::new(self, 30) + } + #[doc = "Bit 31 - SBC0"] + #[inline(always)] + pub fn sbc0(&mut self) -> Sbc0W { + Sbc0W::new(self, 31) + } +} +#[doc = "ERM Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sr0Spec; +impl crate::RegisterSpec for Sr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr0::R`](R) reader structure"] +impl crate::Readable for Sr0Spec {} +#[doc = "`write(|w| ..)` method takes [`sr0::W`](W) writer structure"] +impl crate::Writable for Sr0Spec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xcc00_0000; +} +#[doc = "`reset()` method sets SR0 to value 0"] +impl crate::Resettable for Sr0Spec {} diff --git a/mcxa276-pac/src/erm0/syn0.rs b/mcxa276-pac/src/erm0/syn0.rs new file mode 100644 index 000000000..a869c7776 --- /dev/null +++ b/mcxa276-pac/src/erm0/syn0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SYN0` reader"] +pub type R = crate::R; +#[doc = "Field `SYNDROME` reader - SYNDROME"] +pub type SyndromeR = crate::FieldReader; +impl R { + #[doc = "Bits 24:31 - SYNDROME"] + #[inline(always)] + pub fn syndrome(&self) -> SyndromeR { + SyndromeR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "ERM Memory 0 Syndrome Register\n\nYou can [`read`](crate::Reg::read) this register and get [`syn0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Syn0Spec; +impl crate::RegisterSpec for Syn0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`syn0::R`](R) reader structure"] +impl crate::Readable for Syn0Spec {} +#[doc = "`reset()` method sets SYN0 to value 0"] +impl crate::Resettable for Syn0Spec {} diff --git a/mcxa276-pac/src/flexio0.rs b/mcxa276-pac/src/flexio0.rs new file mode 100644 index 000000000..b38b79569 --- /dev/null +++ b/mcxa276-pac/src/flexio0.rs @@ -0,0 +1,556 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + ctrl: Ctrl, + pin: Pin, + shiftstat: Shiftstat, + shifterr: Shifterr, + timstat: Timstat, + _reserved7: [u8; 0x04], + shiftsien: Shiftsien, + shifteien: Shifteien, + timien: Timien, + _reserved10: [u8; 0x04], + shiftsden: Shiftsden, + _reserved11: [u8; 0x04], + timersden: Timersden, + _reserved12: [u8; 0x04], + shiftstate: Shiftstate, + _reserved13: [u8; 0x04], + trgstat: Trgstat, + trigien: Trigien, + pinstat: Pinstat, + pinien: Pinien, + pinren: Pinren, + pinfen: Pinfen, + pinoutd: Pinoutd, + pinoute: Pinoute, + pinoutdis: Pinoutdis, + pinoutclr: Pinoutclr, + pinoutset: Pinoutset, + pinouttog: Pinouttog, + _reserved25: [u8; 0x08], + shiftctl: [Shiftctl; 4], + _reserved26: [u8; 0x70], + shiftcfg: [Shiftcfg; 4], + _reserved27: [u8; 0xf0], + shiftbuf: [Shiftbuf; 4], + _reserved28: [u8; 0x70], + shiftbufbis: [Shiftbufbis; 4], + _reserved29: [u8; 0x70], + shiftbufbys: [Shiftbufbys; 4], + _reserved30: [u8; 0x70], + shiftbufbbs: [Shiftbufbbs; 4], + _reserved31: [u8; 0x70], + timctl: [Timctl; 4], + _reserved32: [u8; 0x70], + timcfg: [Timcfg; 4], + _reserved33: [u8; 0x70], + timcmp: [Timcmp; 4], + _reserved34: [u8; 0x0170], + shiftbufnbs: [Shiftbufnbs; 4], + _reserved35: [u8; 0x70], + shiftbufhws: [Shiftbufhws; 4], + _reserved36: [u8; 0x70], + shiftbufnis: [Shiftbufnis; 4], + _reserved37: [u8; 0x70], + shiftbufoes: [Shiftbufoes; 4], + _reserved38: [u8; 0x70], + shiftbufeos: [Shiftbufeos; 4], + _reserved39: [u8; 0x70], + shiftbufhbs: [Shiftbufhbs; 4], +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x08 - FLEXIO Control"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x0c - Pin State"] + #[inline(always)] + pub const fn pin(&self) -> &Pin { + &self.pin + } + #[doc = "0x10 - Shifter Status"] + #[inline(always)] + pub const fn shiftstat(&self) -> &Shiftstat { + &self.shiftstat + } + #[doc = "0x14 - Shifter Error"] + #[inline(always)] + pub const fn shifterr(&self) -> &Shifterr { + &self.shifterr + } + #[doc = "0x18 - Timer Status Flag"] + #[inline(always)] + pub const fn timstat(&self) -> &Timstat { + &self.timstat + } + #[doc = "0x20 - Shifter Status Interrupt Enable"] + #[inline(always)] + pub const fn shiftsien(&self) -> &Shiftsien { + &self.shiftsien + } + #[doc = "0x24 - Shifter Error Interrupt Enable"] + #[inline(always)] + pub const fn shifteien(&self) -> &Shifteien { + &self.shifteien + } + #[doc = "0x28 - Timer Interrupt Enable"] + #[inline(always)] + pub const fn timien(&self) -> &Timien { + &self.timien + } + #[doc = "0x30 - Shifter Status DMA Enable"] + #[inline(always)] + pub const fn shiftsden(&self) -> &Shiftsden { + &self.shiftsden + } + #[doc = "0x38 - Timer Status DMA Enable"] + #[inline(always)] + pub const fn timersden(&self) -> &Timersden { + &self.timersden + } + #[doc = "0x40 - Shifter State"] + #[inline(always)] + pub const fn shiftstate(&self) -> &Shiftstate { + &self.shiftstate + } + #[doc = "0x48 - Trigger Status"] + #[inline(always)] + pub const fn trgstat(&self) -> &Trgstat { + &self.trgstat + } + #[doc = "0x4c - External Trigger Interrupt Enable"] + #[inline(always)] + pub const fn trigien(&self) -> &Trigien { + &self.trigien + } + #[doc = "0x50 - Pin Status"] + #[inline(always)] + pub const fn pinstat(&self) -> &Pinstat { + &self.pinstat + } + #[doc = "0x54 - Pin Interrupt Enable"] + #[inline(always)] + pub const fn pinien(&self) -> &Pinien { + &self.pinien + } + #[doc = "0x58 - Pin Rising Edge Enable"] + #[inline(always)] + pub const fn pinren(&self) -> &Pinren { + &self.pinren + } + #[doc = "0x5c - Pin Falling Edge Enable"] + #[inline(always)] + pub const fn pinfen(&self) -> &Pinfen { + &self.pinfen + } + #[doc = "0x60 - Pin Output Data"] + #[inline(always)] + pub const fn pinoutd(&self) -> &Pinoutd { + &self.pinoutd + } + #[doc = "0x64 - Pin Output Enable"] + #[inline(always)] + pub const fn pinoute(&self) -> &Pinoute { + &self.pinoute + } + #[doc = "0x68 - Pin Output Disable"] + #[inline(always)] + pub const fn pinoutdis(&self) -> &Pinoutdis { + &self.pinoutdis + } + #[doc = "0x6c - Pin Output Clear"] + #[inline(always)] + pub const fn pinoutclr(&self) -> &Pinoutclr { + &self.pinoutclr + } + #[doc = "0x70 - Pin Output Set"] + #[inline(always)] + pub const fn pinoutset(&self) -> &Pinoutset { + &self.pinoutset + } + #[doc = "0x74 - Pin Output Toggle"] + #[inline(always)] + pub const fn pinouttog(&self) -> &Pinouttog { + &self.pinouttog + } + #[doc = "0x80..0x90 - Shifter Control"] + #[inline(always)] + pub const fn shiftctl(&self, n: usize) -> &Shiftctl { + &self.shiftctl[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0x90 - Shifter Control"] + #[inline(always)] + pub fn shiftctl_iter(&self) -> impl Iterator { + self.shiftctl.iter() + } + #[doc = "0x100..0x110 - Shifter Configuration"] + #[inline(always)] + pub const fn shiftcfg(&self, n: usize) -> &Shiftcfg { + &self.shiftcfg[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x100..0x110 - Shifter Configuration"] + #[inline(always)] + pub fn shiftcfg_iter(&self) -> impl Iterator { + self.shiftcfg.iter() + } + #[doc = "0x200..0x210 - Shifter Buffer"] + #[inline(always)] + pub const fn shiftbuf(&self, n: usize) -> &Shiftbuf { + &self.shiftbuf[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x200..0x210 - Shifter Buffer"] + #[inline(always)] + pub fn shiftbuf_iter(&self) -> impl Iterator { + self.shiftbuf.iter() + } + #[doc = "0x280..0x290 - Shifter Buffer Bit Swapped"] + #[inline(always)] + pub const fn shiftbufbis(&self, n: usize) -> &Shiftbufbis { + &self.shiftbufbis[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x280..0x290 - Shifter Buffer Bit Swapped"] + #[inline(always)] + pub fn shiftbufbis_iter(&self) -> impl Iterator { + self.shiftbufbis.iter() + } + #[doc = "0x300..0x310 - Shifter Buffer Byte Swapped"] + #[inline(always)] + pub const fn shiftbufbys(&self, n: usize) -> &Shiftbufbys { + &self.shiftbufbys[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x300..0x310 - Shifter Buffer Byte Swapped"] + #[inline(always)] + pub fn shiftbufbys_iter(&self) -> impl Iterator { + self.shiftbufbys.iter() + } + #[doc = "0x380..0x390 - Shifter Buffer Bit Byte Swapped"] + #[inline(always)] + pub const fn shiftbufbbs(&self, n: usize) -> &Shiftbufbbs { + &self.shiftbufbbs[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x380..0x390 - Shifter Buffer Bit Byte Swapped"] + #[inline(always)] + pub fn shiftbufbbs_iter(&self) -> impl Iterator { + self.shiftbufbbs.iter() + } + #[doc = "0x400..0x410 - Timer Control"] + #[inline(always)] + pub const fn timctl(&self, n: usize) -> &Timctl { + &self.timctl[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x400..0x410 - Timer Control"] + #[inline(always)] + pub fn timctl_iter(&self) -> impl Iterator { + self.timctl.iter() + } + #[doc = "0x480..0x490 - Timer Configuration"] + #[inline(always)] + pub const fn timcfg(&self, n: usize) -> &Timcfg { + &self.timcfg[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x480..0x490 - Timer Configuration"] + #[inline(always)] + pub fn timcfg_iter(&self) -> impl Iterator { + self.timcfg.iter() + } + #[doc = "0x500..0x510 - Timer Compare"] + #[inline(always)] + pub const fn timcmp(&self, n: usize) -> &Timcmp { + &self.timcmp[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x500..0x510 - Timer Compare"] + #[inline(always)] + pub fn timcmp_iter(&self) -> impl Iterator { + self.timcmp.iter() + } + #[doc = "0x680..0x690 - Shifter Buffer Nibble Byte Swapped"] + #[inline(always)] + pub const fn shiftbufnbs(&self, n: usize) -> &Shiftbufnbs { + &self.shiftbufnbs[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x680..0x690 - Shifter Buffer Nibble Byte Swapped"] + #[inline(always)] + pub fn shiftbufnbs_iter(&self) -> impl Iterator { + self.shiftbufnbs.iter() + } + #[doc = "0x700..0x710 - Shifter Buffer Halfword Swapped"] + #[inline(always)] + pub const fn shiftbufhws(&self, n: usize) -> &Shiftbufhws { + &self.shiftbufhws[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x700..0x710 - Shifter Buffer Halfword Swapped"] + #[inline(always)] + pub fn shiftbufhws_iter(&self) -> impl Iterator { + self.shiftbufhws.iter() + } + #[doc = "0x780..0x790 - Shifter Buffer Nibble Swapped"] + #[inline(always)] + pub const fn shiftbufnis(&self, n: usize) -> &Shiftbufnis { + &self.shiftbufnis[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x780..0x790 - Shifter Buffer Nibble Swapped"] + #[inline(always)] + pub fn shiftbufnis_iter(&self) -> impl Iterator { + self.shiftbufnis.iter() + } + #[doc = "0x800..0x810 - Shifter Buffer Odd Even Swapped"] + #[inline(always)] + pub const fn shiftbufoes(&self, n: usize) -> &Shiftbufoes { + &self.shiftbufoes[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x800..0x810 - Shifter Buffer Odd Even Swapped"] + #[inline(always)] + pub fn shiftbufoes_iter(&self) -> impl Iterator { + self.shiftbufoes.iter() + } + #[doc = "0x880..0x890 - Shifter Buffer Even Odd Swapped"] + #[inline(always)] + pub const fn shiftbufeos(&self, n: usize) -> &Shiftbufeos { + &self.shiftbufeos[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x880..0x890 - Shifter Buffer Even Odd Swapped"] + #[inline(always)] + pub fn shiftbufeos_iter(&self) -> impl Iterator { + self.shiftbufeos.iter() + } + #[doc = "0x900..0x910 - Shifter Buffer Halfword Byte Swapped"] + #[inline(always)] + pub const fn shiftbufhbs(&self, n: usize) -> &Shiftbufhbs { + &self.shiftbufhbs[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x900..0x910 - Shifter Buffer Halfword Byte Swapped"] + #[inline(always)] + pub fn shiftbufhbs_iter(&self) -> impl Iterator { + self.shiftbufhbs.iter() + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "CTRL (rw) register accessor: FLEXIO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "FLEXIO Control"] +pub mod ctrl; +#[doc = "PIN (r) register accessor: Pin State\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin`] module"] +#[doc(alias = "PIN")] +pub type Pin = crate::Reg; +#[doc = "Pin State"] +pub mod pin; +#[doc = "SHIFTSTAT (rw) register accessor: Shifter Status\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftstat`] module"] +#[doc(alias = "SHIFTSTAT")] +pub type Shiftstat = crate::Reg; +#[doc = "Shifter Status"] +pub mod shiftstat; +#[doc = "SHIFTERR (rw) register accessor: Shifter Error\n\nYou can [`read`](crate::Reg::read) this register and get [`shifterr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifterr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shifterr`] module"] +#[doc(alias = "SHIFTERR")] +pub type Shifterr = crate::Reg; +#[doc = "Shifter Error"] +pub mod shifterr; +#[doc = "TIMSTAT (rw) register accessor: Timer Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`timstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timstat`] module"] +#[doc(alias = "TIMSTAT")] +pub type Timstat = crate::Reg; +#[doc = "Timer Status Flag"] +pub mod timstat; +#[doc = "SHIFTSIEN (rw) register accessor: Shifter Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftsien`] module"] +#[doc(alias = "SHIFTSIEN")] +pub type Shiftsien = crate::Reg; +#[doc = "Shifter Status Interrupt Enable"] +pub mod shiftsien; +#[doc = "SHIFTEIEN (rw) register accessor: Shifter Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shifteien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifteien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shifteien`] module"] +#[doc(alias = "SHIFTEIEN")] +pub type Shifteien = crate::Reg; +#[doc = "Shifter Error Interrupt Enable"] +pub mod shifteien; +#[doc = "TIMIEN (rw) register accessor: Timer Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timien`] module"] +#[doc(alias = "TIMIEN")] +pub type Timien = crate::Reg; +#[doc = "Timer Interrupt Enable"] +pub mod timien; +#[doc = "SHIFTSDEN (rw) register accessor: Shifter Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsden::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsden::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftsden`] module"] +#[doc(alias = "SHIFTSDEN")] +pub type Shiftsden = crate::Reg; +#[doc = "Shifter Status DMA Enable"] +pub mod shiftsden; +#[doc = "TIMERSDEN (rw) register accessor: Timer Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timersden::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timersden::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timersden`] module"] +#[doc(alias = "TIMERSDEN")] +pub type Timersden = crate::Reg; +#[doc = "Timer Status DMA Enable"] +pub mod timersden; +#[doc = "SHIFTSTATE (rw) register accessor: Shifter State\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftstate`] module"] +#[doc(alias = "SHIFTSTATE")] +pub type Shiftstate = crate::Reg; +#[doc = "Shifter State"] +pub mod shiftstate; +#[doc = "TRGSTAT (rw) register accessor: Trigger Status\n\nYou can [`read`](crate::Reg::read) this register and get [`trgstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trgstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trgstat`] module"] +#[doc(alias = "TRGSTAT")] +pub type Trgstat = crate::Reg; +#[doc = "Trigger Status"] +pub mod trgstat; +#[doc = "TRIGIEN (rw) register accessor: External Trigger Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`trigien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigien`] module"] +#[doc(alias = "TRIGIEN")] +pub type Trigien = crate::Reg; +#[doc = "External Trigger Interrupt Enable"] +pub mod trigien; +#[doc = "PINSTAT (rw) register accessor: Pin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pinstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinstat`] module"] +#[doc(alias = "PINSTAT")] +pub type Pinstat = crate::Reg; +#[doc = "Pin Status"] +pub mod pinstat; +#[doc = "PINIEN (rw) register accessor: Pin Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinien`] module"] +#[doc(alias = "PINIEN")] +pub type Pinien = crate::Reg; +#[doc = "Pin Interrupt Enable"] +pub mod pinien; +#[doc = "PINREN (rw) register accessor: Pin Rising Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinren`] module"] +#[doc(alias = "PINREN")] +pub type Pinren = crate::Reg; +#[doc = "Pin Rising Edge Enable"] +pub mod pinren; +#[doc = "PINFEN (rw) register accessor: Pin Falling Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinfen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinfen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinfen`] module"] +#[doc(alias = "PINFEN")] +pub type Pinfen = crate::Reg; +#[doc = "Pin Falling Edge Enable"] +pub mod pinfen; +#[doc = "PINOUTD (rw) register accessor: Pin Output Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutd`] module"] +#[doc(alias = "PINOUTD")] +pub type Pinoutd = crate::Reg; +#[doc = "Pin Output Data"] +pub mod pinoutd; +#[doc = "PINOUTE (rw) register accessor: Pin Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoute::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoute::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoute`] module"] +#[doc(alias = "PINOUTE")] +pub type Pinoute = crate::Reg; +#[doc = "Pin Output Enable"] +pub mod pinoute; +#[doc = "PINOUTDIS (rw) register accessor: Pin Output Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutdis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutdis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutdis`] module"] +#[doc(alias = "PINOUTDIS")] +pub type Pinoutdis = crate::Reg; +#[doc = "Pin Output Disable"] +pub mod pinoutdis; +#[doc = "PINOUTCLR (rw) register accessor: Pin Output Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutclr`] module"] +#[doc(alias = "PINOUTCLR")] +pub type Pinoutclr = crate::Reg; +#[doc = "Pin Output Clear"] +pub mod pinoutclr; +#[doc = "PINOUTSET (rw) register accessor: Pin Output Set\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutset`] module"] +#[doc(alias = "PINOUTSET")] +pub type Pinoutset = crate::Reg; +#[doc = "Pin Output Set"] +pub mod pinoutset; +#[doc = "PINOUTTOG (rw) register accessor: Pin Output Toggle\n\nYou can [`read`](crate::Reg::read) this register and get [`pinouttog::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinouttog::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinouttog`] module"] +#[doc(alias = "PINOUTTOG")] +pub type Pinouttog = crate::Reg; +#[doc = "Pin Output Toggle"] +pub mod pinouttog; +#[doc = "SHIFTCTL (rw) register accessor: Shifter Control\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftctl`] module"] +#[doc(alias = "SHIFTCTL")] +pub type Shiftctl = crate::Reg; +#[doc = "Shifter Control"] +pub mod shiftctl; +#[doc = "SHIFTCFG (rw) register accessor: Shifter Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftcfg`] module"] +#[doc(alias = "SHIFTCFG")] +pub type Shiftcfg = crate::Reg; +#[doc = "Shifter Configuration"] +pub mod shiftcfg; +#[doc = "SHIFTBUF (rw) register accessor: Shifter Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbuf`] module"] +#[doc(alias = "SHIFTBUF")] +pub type Shiftbuf = crate::Reg; +#[doc = "Shifter Buffer"] +pub mod shiftbuf; +#[doc = "SHIFTBUFBIS (rw) register accessor: Shifter Buffer Bit Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufbis`] module"] +#[doc(alias = "SHIFTBUFBIS")] +pub type Shiftbufbis = crate::Reg; +#[doc = "Shifter Buffer Bit Swapped"] +pub mod shiftbufbis; +#[doc = "SHIFTBUFBYS (rw) register accessor: Shifter Buffer Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbys::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbys::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufbys`] module"] +#[doc(alias = "SHIFTBUFBYS")] +pub type Shiftbufbys = crate::Reg; +#[doc = "Shifter Buffer Byte Swapped"] +pub mod shiftbufbys; +#[doc = "SHIFTBUFBBS (rw) register accessor: Shifter Buffer Bit Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbbs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbbs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufbbs`] module"] +#[doc(alias = "SHIFTBUFBBS")] +pub type Shiftbufbbs = crate::Reg; +#[doc = "Shifter Buffer Bit Byte Swapped"] +pub mod shiftbufbbs; +#[doc = "TIMCTL (rw) register accessor: Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`timctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timctl`] module"] +#[doc(alias = "TIMCTL")] +pub type Timctl = crate::Reg; +#[doc = "Timer Control"] +pub mod timctl; +#[doc = "TIMCFG (rw) register accessor: Timer Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`timcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timcfg`] module"] +#[doc(alias = "TIMCFG")] +pub type Timcfg = crate::Reg; +#[doc = "Timer Configuration"] +pub mod timcfg; +#[doc = "TIMCMP (rw) register accessor: Timer Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`timcmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timcmp`] module"] +#[doc(alias = "TIMCMP")] +pub type Timcmp = crate::Reg; +#[doc = "Timer Compare"] +pub mod timcmp; +#[doc = "SHIFTBUFNBS (rw) register accessor: Shifter Buffer Nibble Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnbs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnbs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufnbs`] module"] +#[doc(alias = "SHIFTBUFNBS")] +pub type Shiftbufnbs = crate::Reg; +#[doc = "Shifter Buffer Nibble Byte Swapped"] +pub mod shiftbufnbs; +#[doc = "SHIFTBUFHWS (rw) register accessor: Shifter Buffer Halfword Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhws::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhws::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufhws`] module"] +#[doc(alias = "SHIFTBUFHWS")] +pub type Shiftbufhws = crate::Reg; +#[doc = "Shifter Buffer Halfword Swapped"] +pub mod shiftbufhws; +#[doc = "SHIFTBUFNIS (rw) register accessor: Shifter Buffer Nibble Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufnis`] module"] +#[doc(alias = "SHIFTBUFNIS")] +pub type Shiftbufnis = crate::Reg; +#[doc = "Shifter Buffer Nibble Swapped"] +pub mod shiftbufnis; +#[doc = "SHIFTBUFOES (rw) register accessor: Shifter Buffer Odd Even Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufoes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufoes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufoes`] module"] +#[doc(alias = "SHIFTBUFOES")] +pub type Shiftbufoes = crate::Reg; +#[doc = "Shifter Buffer Odd Even Swapped"] +pub mod shiftbufoes; +#[doc = "SHIFTBUFEOS (rw) register accessor: Shifter Buffer Even Odd Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufeos::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufeos::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufeos`] module"] +#[doc(alias = "SHIFTBUFEOS")] +pub type Shiftbufeos = crate::Reg; +#[doc = "Shifter Buffer Even Odd Swapped"] +pub mod shiftbufeos; +#[doc = "SHIFTBUFHBS (rw) register accessor: Shifter Buffer Halfword Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhbs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhbs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufhbs`] module"] +#[doc(alias = "SHIFTBUFHBS")] +pub type Shiftbufhbs = crate::Reg; +#[doc = "Shifter Buffer Halfword Byte Swapped"] +pub mod shiftbufhbs; diff --git a/mcxa276-pac/src/flexio0/ctrl.rs b/mcxa276-pac/src/flexio0/ctrl.rs new file mode 100644 index 000000000..01255862b --- /dev/null +++ b/mcxa276-pac/src/flexio0/ctrl.rs @@ -0,0 +1,336 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "FLEXIO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexen { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXEN` reader - FLEXIO Enable"] +pub type FlexenR = crate::BitReader; +impl FlexenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexen { + match self.bits { + false => Flexen::Disable, + true => Flexen::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Flexen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Flexen::Enable + } +} +#[doc = "Field `FLEXEN` writer - FLEXIO Enable"] +pub type FlexenW<'a, REG> = crate::BitWriter<'a, REG, Flexen>; +impl<'a, REG> FlexenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Flexen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Flexen::Enable) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swrst { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swrst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SwrstR = crate::BitReader; +impl SwrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swrst { + match self.bits { + false => Swrst::Disable, + true => Swrst::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Swrst::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Swrst::Enable + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG, Swrst>; +impl<'a, REG> SwrstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Swrst::Disable) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Swrst::Enable) + } +} +#[doc = "Fast Access\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fastacc { + #[doc = "0: Normal"] + Normal = 0, + #[doc = "1: Fast"] + Fast = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fastacc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FASTACC` reader - Fast Access"] +pub type FastaccR = crate::BitReader; +impl FastaccR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fastacc { + match self.bits { + false => Fastacc::Normal, + true => Fastacc::Fast, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == Fastacc::Normal + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_fast(&self) -> bool { + *self == Fastacc::Fast + } +} +#[doc = "Field `FASTACC` writer - Fast Access"] +pub type FastaccW<'a, REG> = crate::BitWriter<'a, REG, Fastacc>; +impl<'a, REG> FastaccW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(Fastacc::Normal) + } + #[doc = "Fast"] + #[inline(always)] + pub fn fast(self) -> &'a mut crate::W { + self.variant(Fastacc::Fast) + } +} +#[doc = "Debug Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dbge { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Emable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dbge) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBGE` reader - Debug Enable"] +pub type DbgeR = crate::BitReader; +impl DbgeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dbge { + match self.bits { + false => Dbge::Disable, + true => Dbge::Emable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Dbge::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_emable(&self) -> bool { + *self == Dbge::Emable + } +} +#[doc = "Field `DBGE` writer - Debug Enable"] +pub type DbgeW<'a, REG> = crate::BitWriter<'a, REG, Dbge>; +impl<'a, REG> DbgeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Dbge::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn emable(self) -> &'a mut crate::W { + self.variant(Dbge::Emable) + } +} +#[doc = "Doze Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dozen { + #[doc = "0: Enable"] + Enable = 0, + #[doc = "1: Disable"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dozen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DOZEN` reader - Doze Enable"] +pub type DozenR = crate::BitReader; +impl DozenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dozen { + match self.bits { + false => Dozen::Enable, + true => Dozen::Disable, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dozen::Enable + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Dozen::Disable + } +} +#[doc = "Field `DOZEN` writer - Doze Enable"] +pub type DozenW<'a, REG> = crate::BitWriter<'a, REG, Dozen>; +impl<'a, REG> DozenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dozen::Enable) + } + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Dozen::Disable) + } +} +impl R { + #[doc = "Bit 0 - FLEXIO Enable"] + #[inline(always)] + pub fn flexen(&self) -> FlexenR { + FlexenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SwrstR { + SwrstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Fast Access"] + #[inline(always)] + pub fn fastacc(&self) -> FastaccR { + FastaccR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 30 - Debug Enable"] + #[inline(always)] + pub fn dbge(&self) -> DbgeR { + DbgeR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Doze Enable"] + #[inline(always)] + pub fn dozen(&self) -> DozenR { + DozenR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLEXIO Enable"] + #[inline(always)] + pub fn flexen(&mut self) -> FlexenW { + FlexenW::new(self, 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SwrstW { + SwrstW::new(self, 1) + } + #[doc = "Bit 2 - Fast Access"] + #[inline(always)] + pub fn fastacc(&mut self) -> FastaccW { + FastaccW::new(self, 2) + } + #[doc = "Bit 30 - Debug Enable"] + #[inline(always)] + pub fn dbge(&mut self) -> DbgeW { + DbgeW::new(self, 30) + } + #[doc = "Bit 31 - Doze Enable"] + #[inline(always)] + pub fn dozen(&mut self) -> DozenW { + DozenW::new(self, 31) + } +} +#[doc = "FLEXIO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/flexio0/param.rs b/mcxa276-pac/src/flexio0/param.rs new file mode 100644 index 000000000..3bd5b8365 --- /dev/null +++ b/mcxa276-pac/src/flexio0/param.rs @@ -0,0 +1,43 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "Field `SHIFTER` reader - Shifter Number"] +pub type ShifterR = crate::FieldReader; +#[doc = "Field `TIMER` reader - Timer Number"] +pub type TimerR = crate::FieldReader; +#[doc = "Field `PIN` reader - Pin Number"] +pub type PinR = crate::FieldReader; +#[doc = "Field `TRIGGER` reader - Trigger Number"] +pub type TriggerR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Shifter Number"] + #[inline(always)] + pub fn shifter(&self) -> ShifterR { + ShifterR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Timer Number"] + #[inline(always)] + pub fn timer(&self) -> TimerR { + TimerR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Pin Number"] + #[inline(always)] + pub fn pin(&self) -> PinR { + PinR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Trigger Number"] + #[inline(always)] + pub fn trigger(&self) -> TriggerR { + TriggerR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x0420_0404"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x0420_0404; +} diff --git a/mcxa276-pac/src/flexio0/pin.rs b/mcxa276-pac/src/flexio0/pin.rs new file mode 100644 index 000000000..32ee93af4 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pin.rs @@ -0,0 +1,20 @@ +#[doc = "Register `PIN` reader"] +pub type R = crate::R; +#[doc = "Field `PDI` reader - Pin Data Input"] +pub type PdiR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Pin Data Input"] + #[inline(always)] + pub fn pdi(&self) -> PdiR { + PdiR::new(self.bits) + } +} +#[doc = "Pin State\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinSpec; +impl crate::RegisterSpec for PinSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin::R`](R) reader structure"] +impl crate::Readable for PinSpec {} +#[doc = "`reset()` method sets PIN to value 0"] +impl crate::Resettable for PinSpec {} diff --git a/mcxa276-pac/src/flexio0/pinfen.rs b/mcxa276-pac/src/flexio0/pinfen.rs new file mode 100644 index 000000000..5b25594a4 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinfen.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINFEN` reader"] +pub type R = crate::R; +#[doc = "Register `PINFEN` writer"] +pub type W = crate::W; +#[doc = "Field `PFE` reader - Pin Falling Edge"] +pub type PfeR = crate::FieldReader; +#[doc = "Field `PFE` writer - Pin Falling Edge"] +pub type PfeW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Pin Falling Edge"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Pin Falling Edge"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 0) + } +} +#[doc = "Pin Falling Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinfen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinfen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinfenSpec; +impl crate::RegisterSpec for PinfenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinfen::R`](R) reader structure"] +impl crate::Readable for PinfenSpec {} +#[doc = "`write(|w| ..)` method takes [`pinfen::W`](W) writer structure"] +impl crate::Writable for PinfenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINFEN to value 0"] +impl crate::Resettable for PinfenSpec {} diff --git a/mcxa276-pac/src/flexio0/pinien.rs b/mcxa276-pac/src/flexio0/pinien.rs new file mode 100644 index 000000000..a26dd10b3 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinien.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINIEN` reader"] +pub type R = crate::R; +#[doc = "Register `PINIEN` writer"] +pub type W = crate::W; +#[doc = "Field `PSIE` reader - Pin Status Interrupt Enable"] +pub type PsieR = crate::FieldReader; +#[doc = "Field `PSIE` writer - Pin Status Interrupt Enable"] +pub type PsieW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Pin Status Interrupt Enable"] + #[inline(always)] + pub fn psie(&self) -> PsieR { + PsieR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Pin Status Interrupt Enable"] + #[inline(always)] + pub fn psie(&mut self) -> PsieW { + PsieW::new(self, 0) + } +} +#[doc = "Pin Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinienSpec; +impl crate::RegisterSpec for PinienSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinien::R`](R) reader structure"] +impl crate::Readable for PinienSpec {} +#[doc = "`write(|w| ..)` method takes [`pinien::W`](W) writer structure"] +impl crate::Writable for PinienSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINIEN to value 0"] +impl crate::Resettable for PinienSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutclr.rs b/mcxa276-pac/src/flexio0/pinoutclr.rs new file mode 100644 index 000000000..298cbda09 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinoutclr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINOUTCLR` reader"] +pub type R = crate::R; +#[doc = "Register `PINOUTCLR` writer"] +pub type W = crate::W; +#[doc = "Field `OUTCLR` reader - Output Clear"] +pub type OutclrR = crate::FieldReader; +#[doc = "Field `OUTCLR` writer - Output Clear"] +pub type OutclrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Clear"] + #[inline(always)] + pub fn outclr(&self) -> OutclrR { + OutclrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Clear"] + #[inline(always)] + pub fn outclr(&mut self) -> OutclrW { + OutclrW::new(self, 0) + } +} +#[doc = "Pin Output Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinoutclrSpec; +impl crate::RegisterSpec for PinoutclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinoutclr::R`](R) reader structure"] +impl crate::Readable for PinoutclrSpec {} +#[doc = "`write(|w| ..)` method takes [`pinoutclr::W`](W) writer structure"] +impl crate::Writable for PinoutclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINOUTCLR to value 0"] +impl crate::Resettable for PinoutclrSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutd.rs b/mcxa276-pac/src/flexio0/pinoutd.rs new file mode 100644 index 000000000..5dd228031 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinoutd.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINOUTD` reader"] +pub type R = crate::R; +#[doc = "Register `PINOUTD` writer"] +pub type W = crate::W; +#[doc = "Field `OUTD` reader - Output Data"] +pub type OutdR = crate::FieldReader; +#[doc = "Field `OUTD` writer - Output Data"] +pub type OutdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Data"] + #[inline(always)] + pub fn outd(&self) -> OutdR { + OutdR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Data"] + #[inline(always)] + pub fn outd(&mut self) -> OutdW { + OutdW::new(self, 0) + } +} +#[doc = "Pin Output Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinoutdSpec; +impl crate::RegisterSpec for PinoutdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinoutd::R`](R) reader structure"] +impl crate::Readable for PinoutdSpec {} +#[doc = "`write(|w| ..)` method takes [`pinoutd::W`](W) writer structure"] +impl crate::Writable for PinoutdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINOUTD to value 0"] +impl crate::Resettable for PinoutdSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutdis.rs b/mcxa276-pac/src/flexio0/pinoutdis.rs new file mode 100644 index 000000000..9b51a07a0 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinoutdis.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINOUTDIS` reader"] +pub type R = crate::R; +#[doc = "Register `PINOUTDIS` writer"] +pub type W = crate::W; +#[doc = "Field `OUTDIS` reader - Output Disable"] +pub type OutdisR = crate::FieldReader; +#[doc = "Field `OUTDIS` writer - Output Disable"] +pub type OutdisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Disable"] + #[inline(always)] + pub fn outdis(&self) -> OutdisR { + OutdisR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Disable"] + #[inline(always)] + pub fn outdis(&mut self) -> OutdisW { + OutdisW::new(self, 0) + } +} +#[doc = "Pin Output Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutdis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutdis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinoutdisSpec; +impl crate::RegisterSpec for PinoutdisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinoutdis::R`](R) reader structure"] +impl crate::Readable for PinoutdisSpec {} +#[doc = "`write(|w| ..)` method takes [`pinoutdis::W`](W) writer structure"] +impl crate::Writable for PinoutdisSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINOUTDIS to value 0"] +impl crate::Resettable for PinoutdisSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoute.rs b/mcxa276-pac/src/flexio0/pinoute.rs new file mode 100644 index 000000000..4309e68f9 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinoute.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINOUTE` reader"] +pub type R = crate::R; +#[doc = "Register `PINOUTE` writer"] +pub type W = crate::W; +#[doc = "Field `OUTE` reader - Output Enable"] +pub type OuteR = crate::FieldReader; +#[doc = "Field `OUTE` writer - Output Enable"] +pub type OuteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Enable"] + #[inline(always)] + pub fn oute(&self) -> OuteR { + OuteR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Enable"] + #[inline(always)] + pub fn oute(&mut self) -> OuteW { + OuteW::new(self, 0) + } +} +#[doc = "Pin Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoute::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoute::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinouteSpec; +impl crate::RegisterSpec for PinouteSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinoute::R`](R) reader structure"] +impl crate::Readable for PinouteSpec {} +#[doc = "`write(|w| ..)` method takes [`pinoute::W`](W) writer structure"] +impl crate::Writable for PinouteSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINOUTE to value 0"] +impl crate::Resettable for PinouteSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutset.rs b/mcxa276-pac/src/flexio0/pinoutset.rs new file mode 100644 index 000000000..9ce1b747f --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinoutset.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINOUTSET` reader"] +pub type R = crate::R; +#[doc = "Register `PINOUTSET` writer"] +pub type W = crate::W; +#[doc = "Field `OUTSET` reader - Output Set"] +pub type OutsetR = crate::FieldReader; +#[doc = "Field `OUTSET` writer - Output Set"] +pub type OutsetW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Set"] + #[inline(always)] + pub fn outset(&self) -> OutsetR { + OutsetR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Set"] + #[inline(always)] + pub fn outset(&mut self) -> OutsetW { + OutsetW::new(self, 0) + } +} +#[doc = "Pin Output Set\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinoutsetSpec; +impl crate::RegisterSpec for PinoutsetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinoutset::R`](R) reader structure"] +impl crate::Readable for PinoutsetSpec {} +#[doc = "`write(|w| ..)` method takes [`pinoutset::W`](W) writer structure"] +impl crate::Writable for PinoutsetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINOUTSET to value 0"] +impl crate::Resettable for PinoutsetSpec {} diff --git a/mcxa276-pac/src/flexio0/pinouttog.rs b/mcxa276-pac/src/flexio0/pinouttog.rs new file mode 100644 index 000000000..ae9c6b7b8 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinouttog.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINOUTTOG` reader"] +pub type R = crate::R; +#[doc = "Register `PINOUTTOG` writer"] +pub type W = crate::W; +#[doc = "Field `OUTTOG` reader - Output Toggle"] +pub type OuttogR = crate::FieldReader; +#[doc = "Field `OUTTOG` writer - Output Toggle"] +pub type OuttogW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Toggle"] + #[inline(always)] + pub fn outtog(&self) -> OuttogR { + OuttogR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Toggle"] + #[inline(always)] + pub fn outtog(&mut self) -> OuttogW { + OuttogW::new(self, 0) + } +} +#[doc = "Pin Output Toggle\n\nYou can [`read`](crate::Reg::read) this register and get [`pinouttog::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinouttog::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinouttogSpec; +impl crate::RegisterSpec for PinouttogSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinouttog::R`](R) reader structure"] +impl crate::Readable for PinouttogSpec {} +#[doc = "`write(|w| ..)` method takes [`pinouttog::W`](W) writer structure"] +impl crate::Writable for PinouttogSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINOUTTOG to value 0"] +impl crate::Resettable for PinouttogSpec {} diff --git a/mcxa276-pac/src/flexio0/pinren.rs b/mcxa276-pac/src/flexio0/pinren.rs new file mode 100644 index 000000000..ca357706e --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinren.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PINREN` reader"] +pub type R = crate::R; +#[doc = "Register `PINREN` writer"] +pub type W = crate::W; +#[doc = "Field `PRE` reader - Pin Rising Edge"] +pub type PreR = crate::FieldReader; +#[doc = "Field `PRE` writer - Pin Rising Edge"] +pub type PreW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Pin Rising Edge"] + #[inline(always)] + pub fn pre(&self) -> PreR { + PreR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Pin Rising Edge"] + #[inline(always)] + pub fn pre(&mut self) -> PreW { + PreW::new(self, 0) + } +} +#[doc = "Pin Rising Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinrenSpec; +impl crate::RegisterSpec for PinrenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinren::R`](R) reader structure"] +impl crate::Readable for PinrenSpec {} +#[doc = "`write(|w| ..)` method takes [`pinren::W`](W) writer structure"] +impl crate::Writable for PinrenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINREN to value 0"] +impl crate::Resettable for PinrenSpec {} diff --git a/mcxa276-pac/src/flexio0/pinstat.rs b/mcxa276-pac/src/flexio0/pinstat.rs new file mode 100644 index 000000000..0509218c1 --- /dev/null +++ b/mcxa276-pac/src/flexio0/pinstat.rs @@ -0,0 +1,92 @@ +#[doc = "Register `PINSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `PINSTAT` writer"] +pub type W = crate::W; +#[doc = "Pin Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum Psf { + #[doc = "0: Clear"] + Clr = 0, + #[doc = "1: Set"] + Set = 1, +} +impl From for u32 { + #[inline(always)] + fn from(variant: Psf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Psf { + type Ux = u32; +} +impl crate::IsEnum for Psf {} +#[doc = "Field `PSF` reader - Pin Status Flag"] +pub type PsfR = crate::FieldReader; +impl PsfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Psf::Clr), + 1 => Some(Psf::Set), + _ => None, + } + } + #[doc = "Clear"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + *self == Psf::Clr + } + #[doc = "Set"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Psf::Set + } +} +#[doc = "Field `PSF` writer - Pin Status Flag"] +pub type PsfW<'a, REG> = crate::FieldWriter<'a, REG, 32, Psf>; +impl<'a, REG> PsfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Clear"] + #[inline(always)] + pub fn clr(self) -> &'a mut crate::W { + self.variant(Psf::Clr) + } + #[doc = "Set"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Psf::Set) + } +} +impl R { + #[doc = "Bits 0:31 - Pin Status Flag"] + #[inline(always)] + pub fn psf(&self) -> PsfR { + PsfR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Pin Status Flag"] + #[inline(always)] + pub fn psf(&mut self) -> PsfW { + PsfW::new(self, 0) + } +} +#[doc = "Pin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pinstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PinstatSpec; +impl crate::RegisterSpec for PinstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pinstat::R`](R) reader structure"] +impl crate::Readable for PinstatSpec {} +#[doc = "`write(|w| ..)` method takes [`pinstat::W`](W) writer structure"] +impl crate::Writable for PinstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets PINSTAT to value 0"] +impl crate::Resettable for PinstatSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbuf.rs b/mcxa276-pac/src/flexio0/shiftbuf.rs new file mode 100644 index 000000000..aa11c9ff4 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbuf.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUF[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUF[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUF` reader - Shift Buffer"] +pub type ShiftbufR = crate::FieldReader; +#[doc = "Field `SHIFTBUF` writer - Shift Buffer"] +pub type ShiftbufW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbuf(&self) -> ShiftbufR { + ShiftbufR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbuf(&mut self) -> ShiftbufW { + ShiftbufW::new(self, 0) + } +} +#[doc = "Shifter Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufSpec; +impl crate::RegisterSpec for ShiftbufSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbuf::R`](R) reader structure"] +impl crate::Readable for ShiftbufSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbuf::W`](W) writer structure"] +impl crate::Writable for ShiftbufSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUF[%s] to value 0"] +impl crate::Resettable for ShiftbufSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufbbs.rs b/mcxa276-pac/src/flexio0/shiftbufbbs.rs new file mode 100644 index 000000000..3b24c5fe4 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufbbs.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFBBS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFBBS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFBBS` reader - Shift Buffer"] +pub type ShiftbufbbsR = crate::FieldReader; +#[doc = "Field `SHIFTBUFBBS` writer - Shift Buffer"] +pub type ShiftbufbbsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufbbs(&self) -> ShiftbufbbsR { + ShiftbufbbsR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufbbs(&mut self) -> ShiftbufbbsW { + ShiftbufbbsW::new(self, 0) + } +} +#[doc = "Shifter Buffer Bit Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbbs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbbs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufbbsSpec; +impl crate::RegisterSpec for ShiftbufbbsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufbbs::R`](R) reader structure"] +impl crate::Readable for ShiftbufbbsSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufbbs::W`](W) writer structure"] +impl crate::Writable for ShiftbufbbsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFBBS[%s] to value 0"] +impl crate::Resettable for ShiftbufbbsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufbis.rs b/mcxa276-pac/src/flexio0/shiftbufbis.rs new file mode 100644 index 000000000..466ad0f08 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufbis.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFBIS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFBIS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFBIS` reader - Shift Buffer"] +pub type ShiftbufbisR = crate::FieldReader; +#[doc = "Field `SHIFTBUFBIS` writer - Shift Buffer"] +pub type ShiftbufbisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufbis(&self) -> ShiftbufbisR { + ShiftbufbisR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufbis(&mut self) -> ShiftbufbisW { + ShiftbufbisW::new(self, 0) + } +} +#[doc = "Shifter Buffer Bit Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufbisSpec; +impl crate::RegisterSpec for ShiftbufbisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufbis::R`](R) reader structure"] +impl crate::Readable for ShiftbufbisSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufbis::W`](W) writer structure"] +impl crate::Writable for ShiftbufbisSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFBIS[%s] to value 0"] +impl crate::Resettable for ShiftbufbisSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufbys.rs b/mcxa276-pac/src/flexio0/shiftbufbys.rs new file mode 100644 index 000000000..eb4eb394a --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufbys.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFBYS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFBYS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFBYS` reader - Shift Buffer"] +pub type ShiftbufbysR = crate::FieldReader; +#[doc = "Field `SHIFTBUFBYS` writer - Shift Buffer"] +pub type ShiftbufbysW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufbys(&self) -> ShiftbufbysR { + ShiftbufbysR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufbys(&mut self) -> ShiftbufbysW { + ShiftbufbysW::new(self, 0) + } +} +#[doc = "Shifter Buffer Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbys::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbys::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufbysSpec; +impl crate::RegisterSpec for ShiftbufbysSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufbys::R`](R) reader structure"] +impl crate::Readable for ShiftbufbysSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufbys::W`](W) writer structure"] +impl crate::Writable for ShiftbufbysSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFBYS[%s] to value 0"] +impl crate::Resettable for ShiftbufbysSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufeos.rs b/mcxa276-pac/src/flexio0/shiftbufeos.rs new file mode 100644 index 000000000..beb07fc8d --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufeos.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFEOS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFEOS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFEOS` reader - Shift Buffer"] +pub type ShiftbufeosR = crate::FieldReader; +#[doc = "Field `SHIFTBUFEOS` writer - Shift Buffer"] +pub type ShiftbufeosW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufeos(&self) -> ShiftbufeosR { + ShiftbufeosR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufeos(&mut self) -> ShiftbufeosW { + ShiftbufeosW::new(self, 0) + } +} +#[doc = "Shifter Buffer Even Odd Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufeos::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufeos::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufeosSpec; +impl crate::RegisterSpec for ShiftbufeosSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufeos::R`](R) reader structure"] +impl crate::Readable for ShiftbufeosSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufeos::W`](W) writer structure"] +impl crate::Writable for ShiftbufeosSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFEOS[%s] to value 0"] +impl crate::Resettable for ShiftbufeosSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufhbs.rs b/mcxa276-pac/src/flexio0/shiftbufhbs.rs new file mode 100644 index 000000000..95481c89d --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufhbs.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFHBS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFHBS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFHBS` reader - Shift Buffer"] +pub type ShiftbufhbsR = crate::FieldReader; +#[doc = "Field `SHIFTBUFHBS` writer - Shift Buffer"] +pub type ShiftbufhbsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufhbs(&self) -> ShiftbufhbsR { + ShiftbufhbsR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufhbs(&mut self) -> ShiftbufhbsW { + ShiftbufhbsW::new(self, 0) + } +} +#[doc = "Shifter Buffer Halfword Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhbs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhbs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufhbsSpec; +impl crate::RegisterSpec for ShiftbufhbsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufhbs::R`](R) reader structure"] +impl crate::Readable for ShiftbufhbsSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufhbs::W`](W) writer structure"] +impl crate::Writable for ShiftbufhbsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFHBS[%s] to value 0"] +impl crate::Resettable for ShiftbufhbsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufhws.rs b/mcxa276-pac/src/flexio0/shiftbufhws.rs new file mode 100644 index 000000000..62f4477d2 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufhws.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFHWS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFHWS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFHWS` reader - Shift Buffer"] +pub type ShiftbufhwsR = crate::FieldReader; +#[doc = "Field `SHIFTBUFHWS` writer - Shift Buffer"] +pub type ShiftbufhwsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufhws(&self) -> ShiftbufhwsR { + ShiftbufhwsR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufhws(&mut self) -> ShiftbufhwsW { + ShiftbufhwsW::new(self, 0) + } +} +#[doc = "Shifter Buffer Halfword Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhws::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhws::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufhwsSpec; +impl crate::RegisterSpec for ShiftbufhwsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufhws::R`](R) reader structure"] +impl crate::Readable for ShiftbufhwsSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufhws::W`](W) writer structure"] +impl crate::Writable for ShiftbufhwsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFHWS[%s] to value 0"] +impl crate::Resettable for ShiftbufhwsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufnbs.rs b/mcxa276-pac/src/flexio0/shiftbufnbs.rs new file mode 100644 index 000000000..6e2d36f22 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufnbs.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFNBS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFNBS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFNBS` reader - Shift Buffer"] +pub type ShiftbufnbsR = crate::FieldReader; +#[doc = "Field `SHIFTBUFNBS` writer - Shift Buffer"] +pub type ShiftbufnbsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufnbs(&self) -> ShiftbufnbsR { + ShiftbufnbsR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufnbs(&mut self) -> ShiftbufnbsW { + ShiftbufnbsW::new(self, 0) + } +} +#[doc = "Shifter Buffer Nibble Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnbs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnbs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufnbsSpec; +impl crate::RegisterSpec for ShiftbufnbsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufnbs::R`](R) reader structure"] +impl crate::Readable for ShiftbufnbsSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufnbs::W`](W) writer structure"] +impl crate::Writable for ShiftbufnbsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFNBS[%s] to value 0"] +impl crate::Resettable for ShiftbufnbsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufnis.rs b/mcxa276-pac/src/flexio0/shiftbufnis.rs new file mode 100644 index 000000000..fe18a30af --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufnis.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFNIS[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFNIS[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFNIS` reader - Shift Buffer"] +pub type ShiftbufnisR = crate::FieldReader; +#[doc = "Field `SHIFTBUFNIS` writer - Shift Buffer"] +pub type ShiftbufnisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufnis(&self) -> ShiftbufnisR { + ShiftbufnisR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufnis(&mut self) -> ShiftbufnisW { + ShiftbufnisW::new(self, 0) + } +} +#[doc = "Shifter Buffer Nibble Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufnisSpec; +impl crate::RegisterSpec for ShiftbufnisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufnis::R`](R) reader structure"] +impl crate::Readable for ShiftbufnisSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufnis::W`](W) writer structure"] +impl crate::Writable for ShiftbufnisSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFNIS[%s] to value 0"] +impl crate::Resettable for ShiftbufnisSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufoes.rs b/mcxa276-pac/src/flexio0/shiftbufoes.rs new file mode 100644 index 000000000..efb211a47 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftbufoes.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTBUFOES[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTBUFOES[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFTBUFOES` reader - Shift Buffer"] +pub type ShiftbufoesR = crate::FieldReader; +#[doc = "Field `SHIFTBUFOES` writer - Shift Buffer"] +pub type ShiftbufoesW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufoes(&self) -> ShiftbufoesR { + ShiftbufoesR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Shift Buffer"] + #[inline(always)] + pub fn shiftbufoes(&mut self) -> ShiftbufoesW { + ShiftbufoesW::new(self, 0) + } +} +#[doc = "Shifter Buffer Odd Even Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufoes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufoes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftbufoesSpec; +impl crate::RegisterSpec for ShiftbufoesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftbufoes::R`](R) reader structure"] +impl crate::Readable for ShiftbufoesSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftbufoes::W`](W) writer structure"] +impl crate::Writable for ShiftbufoesSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTBUFOES[%s] to value 0"] +impl crate::Resettable for ShiftbufoesSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftcfg.rs b/mcxa276-pac/src/flexio0/shiftcfg.rs new file mode 100644 index 000000000..7e742935a --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftcfg.rs @@ -0,0 +1,416 @@ +#[doc = "Register `SHIFTCFG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTCFG[%s]` writer"] +pub type W = crate::W; +#[doc = "Shifter Start\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sstart { + #[doc = "0: Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable"] + Value00 = 0, + #[doc = "1: Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift"] + Value01 = 1, + #[doc = "2: Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, Receiver and Match Store modes set error flag"] + Value10 = 2, + #[doc = "3: Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, Receiver and Match Store modes set error flag"] + Value11 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sstart) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sstart { + type Ux = u8; +} +impl crate::IsEnum for Sstart {} +#[doc = "Field `SSTART` reader - Shifter Start"] +pub type SstartR = crate::FieldReader; +impl SstartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sstart { + match self.bits { + 0 => Sstart::Value00, + 1 => Sstart::Value01, + 2 => Sstart::Value10, + 3 => Sstart::Value11, + _ => unreachable!(), + } + } + #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable"] + #[inline(always)] + pub fn is_value00(&self) -> bool { + *self == Sstart::Value00 + } + #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift"] + #[inline(always)] + pub fn is_value01(&self) -> bool { + *self == Sstart::Value01 + } + #[doc = "Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, Receiver and Match Store modes set error flag"] + #[inline(always)] + pub fn is_value10(&self) -> bool { + *self == Sstart::Value10 + } + #[doc = "Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, Receiver and Match Store modes set error flag"] + #[inline(always)] + pub fn is_value11(&self) -> bool { + *self == Sstart::Value11 + } +} +#[doc = "Field `SSTART` writer - Shifter Start"] +pub type SstartW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sstart, crate::Safe>; +impl<'a, REG> SstartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable"] + #[inline(always)] + pub fn value00(self) -> &'a mut crate::W { + self.variant(Sstart::Value00) + } + #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift"] + #[inline(always)] + pub fn value01(self) -> &'a mut crate::W { + self.variant(Sstart::Value01) + } + #[doc = "Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, Receiver and Match Store modes set error flag"] + #[inline(always)] + pub fn value10(self) -> &'a mut crate::W { + self.variant(Sstart::Value10) + } + #[doc = "Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, Receiver and Match Store modes set error flag"] + #[inline(always)] + pub fn value11(self) -> &'a mut crate::W { + self.variant(Sstart::Value11) + } +} +#[doc = "Shifter Stop\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sstop { + #[doc = "0: Stop bit disabled for Transmitter, Receiver, and Match Store modes"] + Value00 = 0, + #[doc = "1: Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, Receiver and Match Store modes store receive data on the configured shift edge"] + Value01 = 1, + #[doc = "2: Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] + Value10 = 2, + #[doc = "3: Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] + Value11 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sstop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sstop { + type Ux = u8; +} +impl crate::IsEnum for Sstop {} +#[doc = "Field `SSTOP` reader - Shifter Stop"] +pub type SstopR = crate::FieldReader; +impl SstopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sstop { + match self.bits { + 0 => Sstop::Value00, + 1 => Sstop::Value01, + 2 => Sstop::Value10, + 3 => Sstop::Value11, + _ => unreachable!(), + } + } + #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes"] + #[inline(always)] + pub fn is_value00(&self) -> bool { + *self == Sstop::Value00 + } + #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, Receiver and Match Store modes store receive data on the configured shift edge"] + #[inline(always)] + pub fn is_value01(&self) -> bool { + *self == Sstop::Value01 + } + #[doc = "Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] + #[inline(always)] + pub fn is_value10(&self) -> bool { + *self == Sstop::Value10 + } + #[doc = "Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] + #[inline(always)] + pub fn is_value11(&self) -> bool { + *self == Sstop::Value11 + } +} +#[doc = "Field `SSTOP` writer - Shifter Stop"] +pub type SstopW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sstop, crate::Safe>; +impl<'a, REG> SstopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes"] + #[inline(always)] + pub fn value00(self) -> &'a mut crate::W { + self.variant(Sstop::Value00) + } + #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, Receiver and Match Store modes store receive data on the configured shift edge"] + #[inline(always)] + pub fn value01(self) -> &'a mut crate::W { + self.variant(Sstop::Value01) + } + #[doc = "Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] + #[inline(always)] + pub fn value10(self) -> &'a mut crate::W { + self.variant(Sstop::Value10) + } + #[doc = "Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] + #[inline(always)] + pub fn value11(self) -> &'a mut crate::W { + self.variant(Sstop::Value11) + } +} +#[doc = "Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Insrc { + #[doc = "0: Pin"] + Pin = 0, + #[doc = "1: Shifter n+1 output"] + ShifterNplus1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Insrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INSRC` reader - Input Source"] +pub type InsrcR = crate::BitReader; +impl InsrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Insrc { + match self.bits { + false => Insrc::Pin, + true => Insrc::ShifterNplus1, + } + } + #[doc = "Pin"] + #[inline(always)] + pub fn is_pin(&self) -> bool { + *self == Insrc::Pin + } + #[doc = "Shifter n+1 output"] + #[inline(always)] + pub fn is_shifter_nplus1(&self) -> bool { + *self == Insrc::ShifterNplus1 + } +} +#[doc = "Field `INSRC` writer - Input Source"] +pub type InsrcW<'a, REG> = crate::BitWriter<'a, REG, Insrc>; +impl<'a, REG> InsrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin"] + #[inline(always)] + pub fn pin(self) -> &'a mut crate::W { + self.variant(Insrc::Pin) + } + #[doc = "Shifter n+1 output"] + #[inline(always)] + pub fn shifter_nplus1(self) -> &'a mut crate::W { + self.variant(Insrc::ShifterNplus1) + } +} +#[doc = "Late Store\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Latst { + #[doc = "0: Store the pre-shift register state"] + Preshift = 0, + #[doc = "1: Store the post-shift register state"] + Postshift = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Latst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LATST` reader - Late Store"] +pub type LatstR = crate::BitReader; +impl LatstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Latst { + match self.bits { + false => Latst::Preshift, + true => Latst::Postshift, + } + } + #[doc = "Store the pre-shift register state"] + #[inline(always)] + pub fn is_preshift(&self) -> bool { + *self == Latst::Preshift + } + #[doc = "Store the post-shift register state"] + #[inline(always)] + pub fn is_postshift(&self) -> bool { + *self == Latst::Postshift + } +} +#[doc = "Field `LATST` writer - Late Store"] +pub type LatstW<'a, REG> = crate::BitWriter<'a, REG, Latst>; +impl<'a, REG> LatstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Store the pre-shift register state"] + #[inline(always)] + pub fn preshift(self) -> &'a mut crate::W { + self.variant(Latst::Preshift) + } + #[doc = "Store the post-shift register state"] + #[inline(always)] + pub fn postshift(self) -> &'a mut crate::W { + self.variant(Latst::Postshift) + } +} +#[doc = "Shifter Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ssize { + #[doc = "0: 32-bit"] + Width32 = 0, + #[doc = "1: 24-bit"] + Width24 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ssize) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSIZE` reader - Shifter Size"] +pub type SsizeR = crate::BitReader; +impl SsizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ssize { + match self.bits { + false => Ssize::Width32, + true => Ssize::Width24, + } + } + #[doc = "32-bit"] + #[inline(always)] + pub fn is_width32(&self) -> bool { + *self == Ssize::Width32 + } + #[doc = "24-bit"] + #[inline(always)] + pub fn is_width24(&self) -> bool { + *self == Ssize::Width24 + } +} +#[doc = "Field `SSIZE` writer - Shifter Size"] +pub type SsizeW<'a, REG> = crate::BitWriter<'a, REG, Ssize>; +impl<'a, REG> SsizeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "32-bit"] + #[inline(always)] + pub fn width32(self) -> &'a mut crate::W { + self.variant(Ssize::Width32) + } + #[doc = "24-bit"] + #[inline(always)] + pub fn width24(self) -> &'a mut crate::W { + self.variant(Ssize::Width24) + } +} +#[doc = "Field `PWIDTH` reader - Parallel Width"] +pub type PwidthR = crate::FieldReader; +#[doc = "Field `PWIDTH` writer - Parallel Width"] +pub type PwidthW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:1 - Shifter Start"] + #[inline(always)] + pub fn sstart(&self) -> SstartR { + SstartR::new((self.bits & 3) as u8) + } + #[doc = "Bits 4:5 - Shifter Stop"] + #[inline(always)] + pub fn sstop(&self) -> SstopR { + SstopR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 8 - Input Source"] + #[inline(always)] + pub fn insrc(&self) -> InsrcR { + InsrcR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Late Store"] + #[inline(always)] + pub fn latst(&self) -> LatstR { + LatstR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Shifter Size"] + #[inline(always)] + pub fn ssize(&self) -> SsizeR { + SsizeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:20 - Parallel Width"] + #[inline(always)] + pub fn pwidth(&self) -> PwidthR { + PwidthR::new(((self.bits >> 16) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Shifter Start"] + #[inline(always)] + pub fn sstart(&mut self) -> SstartW { + SstartW::new(self, 0) + } + #[doc = "Bits 4:5 - Shifter Stop"] + #[inline(always)] + pub fn sstop(&mut self) -> SstopW { + SstopW::new(self, 4) + } + #[doc = "Bit 8 - Input Source"] + #[inline(always)] + pub fn insrc(&mut self) -> InsrcW { + InsrcW::new(self, 8) + } + #[doc = "Bit 9 - Late Store"] + #[inline(always)] + pub fn latst(&mut self) -> LatstW { + LatstW::new(self, 9) + } + #[doc = "Bit 12 - Shifter Size"] + #[inline(always)] + pub fn ssize(&mut self) -> SsizeW { + SsizeW::new(self, 12) + } + #[doc = "Bits 16:20 - Parallel Width"] + #[inline(always)] + pub fn pwidth(&mut self) -> PwidthW { + PwidthW::new(self, 16) + } +} +#[doc = "Shifter Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftcfgSpec; +impl crate::RegisterSpec for ShiftcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftcfg::R`](R) reader structure"] +impl crate::Readable for ShiftcfgSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftcfg::W`](W) writer structure"] +impl crate::Writable for ShiftcfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTCFG[%s] to value 0"] +impl crate::Resettable for ShiftcfgSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftctl.rs b/mcxa276-pac/src/flexio0/shiftctl.rs new file mode 100644 index 000000000..74b1032ee --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftctl.rs @@ -0,0 +1,406 @@ +#[doc = "Register `SHIFTCTL[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTCTL[%s]` writer"] +pub type W = crate::W; +#[doc = "Shifter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Smod { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer"] + Receive = 1, + #[doc = "2: Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer"] + Transmit = 2, + #[doc = "4: Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer"] + Matchstore = 4, + #[doc = "5: Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents"] + Matchcont = 5, + #[doc = "6: State mode; SHIFTBUF contents store programmable state attributes"] + State = 6, + #[doc = "7: Logic mode; SHIFTBUF contents implement programmable logic lookup table"] + Logic = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Smod) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Smod { + type Ux = u8; +} +impl crate::IsEnum for Smod {} +#[doc = "Field `SMOD` reader - Shifter Mode"] +pub type SmodR = crate::FieldReader; +impl SmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Smod::Disable), + 1 => Some(Smod::Receive), + 2 => Some(Smod::Transmit), + 4 => Some(Smod::Matchstore), + 5 => Some(Smod::Matchcont), + 6 => Some(Smod::State), + 7 => Some(Smod::Logic), + _ => None, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Smod::Disable + } + #[doc = "Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer"] + #[inline(always)] + pub fn is_receive(&self) -> bool { + *self == Smod::Receive + } + #[doc = "Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer"] + #[inline(always)] + pub fn is_transmit(&self) -> bool { + *self == Smod::Transmit + } + #[doc = "Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer"] + #[inline(always)] + pub fn is_matchstore(&self) -> bool { + *self == Smod::Matchstore + } + #[doc = "Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents"] + #[inline(always)] + pub fn is_matchcont(&self) -> bool { + *self == Smod::Matchcont + } + #[doc = "State mode; SHIFTBUF contents store programmable state attributes"] + #[inline(always)] + pub fn is_state(&self) -> bool { + *self == Smod::State + } + #[doc = "Logic mode; SHIFTBUF contents implement programmable logic lookup table"] + #[inline(always)] + pub fn is_logic(&self) -> bool { + *self == Smod::Logic + } +} +#[doc = "Field `SMOD` writer - Shifter Mode"] +pub type SmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Smod>; +impl<'a, REG> SmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Smod::Disable) + } + #[doc = "Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer"] + #[inline(always)] + pub fn receive(self) -> &'a mut crate::W { + self.variant(Smod::Receive) + } + #[doc = "Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer"] + #[inline(always)] + pub fn transmit(self) -> &'a mut crate::W { + self.variant(Smod::Transmit) + } + #[doc = "Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer"] + #[inline(always)] + pub fn matchstore(self) -> &'a mut crate::W { + self.variant(Smod::Matchstore) + } + #[doc = "Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents"] + #[inline(always)] + pub fn matchcont(self) -> &'a mut crate::W { + self.variant(Smod::Matchcont) + } + #[doc = "State mode; SHIFTBUF contents store programmable state attributes"] + #[inline(always)] + pub fn state(self) -> &'a mut crate::W { + self.variant(Smod::State) + } + #[doc = "Logic mode; SHIFTBUF contents implement programmable logic lookup table"] + #[inline(always)] + pub fn logic(self) -> &'a mut crate::W { + self.variant(Smod::Logic) + } +} +#[doc = "Shifter Pin Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pinpol { + #[doc = "0: Active high"] + ActiveHigh = 0, + #[doc = "1: Active low"] + ActiveLow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pinpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PINPOL` reader - Shifter Pin Polarity"] +pub type PinpolR = crate::BitReader; +impl PinpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pinpol { + match self.bits { + false => Pinpol::ActiveHigh, + true => Pinpol::ActiveLow, + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == Pinpol::ActiveHigh + } + #[doc = "Active low"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == Pinpol::ActiveLow + } +} +#[doc = "Field `PINPOL` writer - Shifter Pin Polarity"] +pub type PinpolW<'a, REG> = crate::BitWriter<'a, REG, Pinpol>; +impl<'a, REG> PinpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut crate::W { + self.variant(Pinpol::ActiveHigh) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut crate::W { + self.variant(Pinpol::ActiveLow) + } +} +#[doc = "Field `PINSEL` reader - Shifter Pin Select"] +pub type PinselR = crate::FieldReader; +#[doc = "Field `PINSEL` writer - Shifter Pin Select"] +pub type PinselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Shifter Pin Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pincfg { + #[doc = "0: Shifter pin output disabled"] + Disable = 0, + #[doc = "1: Shifter pin open-drain or bidirectional output enable"] + OpendBidirouten = 1, + #[doc = "2: Shifter pin bidirectional output data"] + BidirOutdata = 2, + #[doc = "3: Shifter pin output"] + Output = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pincfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pincfg { + type Ux = u8; +} +impl crate::IsEnum for Pincfg {} +#[doc = "Field `PINCFG` reader - Shifter Pin Configuration"] +pub type PincfgR = crate::FieldReader; +impl PincfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pincfg { + match self.bits { + 0 => Pincfg::Disable, + 1 => Pincfg::OpendBidirouten, + 2 => Pincfg::BidirOutdata, + 3 => Pincfg::Output, + _ => unreachable!(), + } + } + #[doc = "Shifter pin output disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pincfg::Disable + } + #[doc = "Shifter pin open-drain or bidirectional output enable"] + #[inline(always)] + pub fn is_opend_bidirouten(&self) -> bool { + *self == Pincfg::OpendBidirouten + } + #[doc = "Shifter pin bidirectional output data"] + #[inline(always)] + pub fn is_bidir_outdata(&self) -> bool { + *self == Pincfg::BidirOutdata + } + #[doc = "Shifter pin output"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == Pincfg::Output + } +} +#[doc = "Field `PINCFG` writer - Shifter Pin Configuration"] +pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pincfg, crate::Safe>; +impl<'a, REG> PincfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Shifter pin output disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pincfg::Disable) + } + #[doc = "Shifter pin open-drain or bidirectional output enable"] + #[inline(always)] + pub fn opend_bidirouten(self) -> &'a mut crate::W { + self.variant(Pincfg::OpendBidirouten) + } + #[doc = "Shifter pin bidirectional output data"] + #[inline(always)] + pub fn bidir_outdata(self) -> &'a mut crate::W { + self.variant(Pincfg::BidirOutdata) + } + #[doc = "Shifter pin output"] + #[inline(always)] + pub fn output(self) -> &'a mut crate::W { + self.variant(Pincfg::Output) + } +} +#[doc = "Timer Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Timpol { + #[doc = "0: Positive edge"] + Posedge = 0, + #[doc = "1: Negative edge"] + Negedge = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Timpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIMPOL` reader - Timer Polarity"] +pub type TimpolR = crate::BitReader; +impl TimpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timpol { + match self.bits { + false => Timpol::Posedge, + true => Timpol::Negedge, + } + } + #[doc = "Positive edge"] + #[inline(always)] + pub fn is_posedge(&self) -> bool { + *self == Timpol::Posedge + } + #[doc = "Negative edge"] + #[inline(always)] + pub fn is_negedge(&self) -> bool { + *self == Timpol::Negedge + } +} +#[doc = "Field `TIMPOL` writer - Timer Polarity"] +pub type TimpolW<'a, REG> = crate::BitWriter<'a, REG, Timpol>; +impl<'a, REG> TimpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Positive edge"] + #[inline(always)] + pub fn posedge(self) -> &'a mut crate::W { + self.variant(Timpol::Posedge) + } + #[doc = "Negative edge"] + #[inline(always)] + pub fn negedge(self) -> &'a mut crate::W { + self.variant(Timpol::Negedge) + } +} +#[doc = "Field `TIMSEL` reader - Timer Select"] +pub type TimselR = crate::FieldReader; +#[doc = "Field `TIMSEL` writer - Timer Select"] +pub type TimselW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:2 - Shifter Mode"] + #[inline(always)] + pub fn smod(&self) -> SmodR { + SmodR::new((self.bits & 7) as u8) + } + #[doc = "Bit 7 - Shifter Pin Polarity"] + #[inline(always)] + pub fn pinpol(&self) -> PinpolR { + PinpolR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - Shifter Pin Select"] + #[inline(always)] + pub fn pinsel(&self) -> PinselR { + PinselR::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:17 - Shifter Pin Configuration"] + #[inline(always)] + pub fn pincfg(&self) -> PincfgR { + PincfgR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 23 - Timer Polarity"] + #[inline(always)] + pub fn timpol(&self) -> TimpolR { + TimpolR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:25 - Timer Select"] + #[inline(always)] + pub fn timsel(&self) -> TimselR { + TimselR::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Shifter Mode"] + #[inline(always)] + pub fn smod(&mut self) -> SmodW { + SmodW::new(self, 0) + } + #[doc = "Bit 7 - Shifter Pin Polarity"] + #[inline(always)] + pub fn pinpol(&mut self) -> PinpolW { + PinpolW::new(self, 7) + } + #[doc = "Bits 8:12 - Shifter Pin Select"] + #[inline(always)] + pub fn pinsel(&mut self) -> PinselW { + PinselW::new(self, 8) + } + #[doc = "Bits 16:17 - Shifter Pin Configuration"] + #[inline(always)] + pub fn pincfg(&mut self) -> PincfgW { + PincfgW::new(self, 16) + } + #[doc = "Bit 23 - Timer Polarity"] + #[inline(always)] + pub fn timpol(&mut self) -> TimpolW { + TimpolW::new(self, 23) + } + #[doc = "Bits 24:25 - Timer Select"] + #[inline(always)] + pub fn timsel(&mut self) -> TimselW { + TimselW::new(self, 24) + } +} +#[doc = "Shifter Control\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftctlSpec; +impl crate::RegisterSpec for ShiftctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftctl::R`](R) reader structure"] +impl crate::Readable for ShiftctlSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftctl::W`](W) writer structure"] +impl crate::Writable for ShiftctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTCTL[%s] to value 0"] +impl crate::Resettable for ShiftctlSpec {} diff --git a/mcxa276-pac/src/flexio0/shifteien.rs b/mcxa276-pac/src/flexio0/shifteien.rs new file mode 100644 index 000000000..f470cbc76 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shifteien.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTEIEN` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTEIEN` writer"] +pub type W = crate::W; +#[doc = "Field `SEIE` reader - Shifter Error Interrupt Enable"] +pub type SeieR = crate::FieldReader; +#[doc = "Field `SEIE` writer - Shifter Error Interrupt Enable"] +pub type SeieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Shifter Error Interrupt Enable"] + #[inline(always)] + pub fn seie(&self) -> SeieR { + SeieR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shifter Error Interrupt Enable"] + #[inline(always)] + pub fn seie(&mut self) -> SeieW { + SeieW::new(self, 0) + } +} +#[doc = "Shifter Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shifteien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifteien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShifteienSpec; +impl crate::RegisterSpec for ShifteienSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shifteien::R`](R) reader structure"] +impl crate::Readable for ShifteienSpec {} +#[doc = "`write(|w| ..)` method takes [`shifteien::W`](W) writer structure"] +impl crate::Writable for ShifteienSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTEIEN to value 0"] +impl crate::Resettable for ShifteienSpec {} diff --git a/mcxa276-pac/src/flexio0/shifterr.rs b/mcxa276-pac/src/flexio0/shifterr.rs new file mode 100644 index 000000000..11329f918 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shifterr.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SHIFTERR` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTERR` writer"] +pub type W = crate::W; +#[doc = "Shifter Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sef { + #[doc = "0: Clear"] + Clr = 0, + #[doc = "1: Set"] + Set = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sef) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sef { + type Ux = u8; +} +impl crate::IsEnum for Sef {} +#[doc = "Field `SEF` reader - Shifter Error Flag"] +pub type SefR = crate::FieldReader; +impl SefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Sef::Clr), + 1 => Some(Sef::Set), + _ => None, + } + } + #[doc = "Clear"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + *self == Sef::Clr + } + #[doc = "Set"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Sef::Set + } +} +#[doc = "Field `SEF` writer - Shifter Error Flag"] +pub type SefW<'a, REG> = crate::FieldWriter<'a, REG, 4, Sef>; +impl<'a, REG> SefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Clear"] + #[inline(always)] + pub fn clr(self) -> &'a mut crate::W { + self.variant(Sef::Clr) + } + #[doc = "Set"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Sef::Set) + } +} +impl R { + #[doc = "Bits 0:3 - Shifter Error Flag"] + #[inline(always)] + pub fn sef(&self) -> SefR { + SefR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shifter Error Flag"] + #[inline(always)] + pub fn sef(&mut self) -> SefW { + SefW::new(self, 0) + } +} +#[doc = "Shifter Error\n\nYou can [`read`](crate::Reg::read) this register and get [`shifterr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifterr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShifterrSpec; +impl crate::RegisterSpec for ShifterrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shifterr::R`](R) reader structure"] +impl crate::Readable for ShifterrSpec {} +#[doc = "`write(|w| ..)` method takes [`shifterr::W`](W) writer structure"] +impl crate::Writable for ShifterrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets SHIFTERR to value 0"] +impl crate::Resettable for ShifterrSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftsden.rs b/mcxa276-pac/src/flexio0/shiftsden.rs new file mode 100644 index 000000000..fd7127afb --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftsden.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTSDEN` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTSDEN` writer"] +pub type W = crate::W; +#[doc = "Field `SSDE` reader - Shifter Status DMA Enable"] +pub type SsdeR = crate::FieldReader; +#[doc = "Field `SSDE` writer - Shifter Status DMA Enable"] +pub type SsdeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Shifter Status DMA Enable"] + #[inline(always)] + pub fn ssde(&self) -> SsdeR { + SsdeR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shifter Status DMA Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SsdeW { + SsdeW::new(self, 0) + } +} +#[doc = "Shifter Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsden::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsden::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftsdenSpec; +impl crate::RegisterSpec for ShiftsdenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftsden::R`](R) reader structure"] +impl crate::Readable for ShiftsdenSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftsden::W`](W) writer structure"] +impl crate::Writable for ShiftsdenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTSDEN to value 0"] +impl crate::Resettable for ShiftsdenSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftsien.rs b/mcxa276-pac/src/flexio0/shiftsien.rs new file mode 100644 index 000000000..455485028 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftsien.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTSIEN` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTSIEN` writer"] +pub type W = crate::W; +#[doc = "Field `SSIE` reader - Shifter Status Interrupt Enable"] +pub type SsieR = crate::FieldReader; +#[doc = "Field `SSIE` writer - Shifter Status Interrupt Enable"] +pub type SsieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"] + #[inline(always)] + pub fn ssie(&self) -> SsieR { + SsieR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"] + #[inline(always)] + pub fn ssie(&mut self) -> SsieW { + SsieW::new(self, 0) + } +} +#[doc = "Shifter Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftsienSpec; +impl crate::RegisterSpec for ShiftsienSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftsien::R`](R) reader structure"] +impl crate::Readable for ShiftsienSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftsien::W`](W) writer structure"] +impl crate::Writable for ShiftsienSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTSIEN to value 0"] +impl crate::Resettable for ShiftsienSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftstat.rs b/mcxa276-pac/src/flexio0/shiftstat.rs new file mode 100644 index 000000000..514033f6f --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftstat.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SHIFTSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTSTAT` writer"] +pub type W = crate::W; +#[doc = "Shifter Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ssf { + #[doc = "0: Clear"] + Clr = 0, + #[doc = "1: Set"] + Set = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ssf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ssf { + type Ux = u8; +} +impl crate::IsEnum for Ssf {} +#[doc = "Field `SSF` reader - Shifter Status Flag"] +pub type SsfR = crate::FieldReader; +impl SsfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ssf::Clr), + 1 => Some(Ssf::Set), + _ => None, + } + } + #[doc = "Clear"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + *self == Ssf::Clr + } + #[doc = "Set"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Ssf::Set + } +} +#[doc = "Field `SSF` writer - Shifter Status Flag"] +pub type SsfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ssf>; +impl<'a, REG> SsfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Clear"] + #[inline(always)] + pub fn clr(self) -> &'a mut crate::W { + self.variant(Ssf::Clr) + } + #[doc = "Set"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Ssf::Set) + } +} +impl R { + #[doc = "Bits 0:3 - Shifter Status Flag"] + #[inline(always)] + pub fn ssf(&self) -> SsfR { + SsfR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shifter Status Flag"] + #[inline(always)] + pub fn ssf(&mut self) -> SsfW { + SsfW::new(self, 0) + } +} +#[doc = "Shifter Status\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftstatSpec; +impl crate::RegisterSpec for ShiftstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftstat::R`](R) reader structure"] +impl crate::Readable for ShiftstatSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftstat::W`](W) writer structure"] +impl crate::Writable for ShiftstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets SHIFTSTAT to value 0"] +impl crate::Resettable for ShiftstatSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftstate.rs b/mcxa276-pac/src/flexio0/shiftstate.rs new file mode 100644 index 000000000..a3578c3b8 --- /dev/null +++ b/mcxa276-pac/src/flexio0/shiftstate.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SHIFTSTATE` reader"] +pub type R = crate::R; +#[doc = "Register `SHIFTSTATE` writer"] +pub type W = crate::W; +#[doc = "Field `STATE` reader - Current State Pointer"] +pub type StateR = crate::FieldReader; +#[doc = "Field `STATE` writer - Current State Pointer"] +pub type StateW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Current State Pointer"] + #[inline(always)] + pub fn state(&self) -> StateR { + StateR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Current State Pointer"] + #[inline(always)] + pub fn state(&mut self) -> StateW { + StateW::new(self, 0) + } +} +#[doc = "Shifter State\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ShiftstateSpec; +impl crate::RegisterSpec for ShiftstateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`shiftstate::R`](R) reader structure"] +impl crate::Readable for ShiftstateSpec {} +#[doc = "`write(|w| ..)` method takes [`shiftstate::W`](W) writer structure"] +impl crate::Writable for ShiftstateSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SHIFTSTATE to value 0"] +impl crate::Resettable for ShiftstateSpec {} diff --git a/mcxa276-pac/src/flexio0/timcfg.rs b/mcxa276-pac/src/flexio0/timcfg.rs new file mode 100644 index 000000000..6b4c19875 --- /dev/null +++ b/mcxa276-pac/src/flexio0/timcfg.rs @@ -0,0 +1,842 @@ +#[doc = "Register `TIMCFG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `TIMCFG[%s]` writer"] +pub type W = crate::W; +#[doc = "Timer Start\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tstart { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tstart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TSTART` reader - Timer Start"] +pub type TstartR = crate::BitReader; +impl TstartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tstart { + match self.bits { + false => Tstart::Disable, + true => Tstart::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tstart::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tstart::Enable + } +} +#[doc = "Field `TSTART` writer - Timer Start"] +pub type TstartW<'a, REG> = crate::BitWriter<'a, REG, Tstart>; +impl<'a, REG> TstartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tstart::Disable) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tstart::Enable) + } +} +#[doc = "Timer Stop\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tstop { + #[doc = "0: Disabled"] + StopDisable = 0, + #[doc = "1: Enabled on timer compare"] + EnableTmrcmp = 1, + #[doc = "2: Enabled on timer disable"] + EnableTmrdisable = 2, + #[doc = "3: Enabled on timer compare and timer disable"] + EnableTmrCmpDis = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tstop) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tstop { + type Ux = u8; +} +impl crate::IsEnum for Tstop {} +#[doc = "Field `TSTOP` reader - Timer Stop"] +pub type TstopR = crate::FieldReader; +impl TstopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tstop { + match self.bits { + 0 => Tstop::StopDisable, + 1 => Tstop::EnableTmrcmp, + 2 => Tstop::EnableTmrdisable, + 3 => Tstop::EnableTmrCmpDis, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_stop_disable(&self) -> bool { + *self == Tstop::StopDisable + } + #[doc = "Enabled on timer compare"] + #[inline(always)] + pub fn is_enable_tmrcmp(&self) -> bool { + *self == Tstop::EnableTmrcmp + } + #[doc = "Enabled on timer disable"] + #[inline(always)] + pub fn is_enable_tmrdisable(&self) -> bool { + *self == Tstop::EnableTmrdisable + } + #[doc = "Enabled on timer compare and timer disable"] + #[inline(always)] + pub fn is_enable_tmr_cmp_dis(&self) -> bool { + *self == Tstop::EnableTmrCmpDis + } +} +#[doc = "Field `TSTOP` writer - Timer Stop"] +pub type TstopW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tstop, crate::Safe>; +impl<'a, REG> TstopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn stop_disable(self) -> &'a mut crate::W { + self.variant(Tstop::StopDisable) + } + #[doc = "Enabled on timer compare"] + #[inline(always)] + pub fn enable_tmrcmp(self) -> &'a mut crate::W { + self.variant(Tstop::EnableTmrcmp) + } + #[doc = "Enabled on timer disable"] + #[inline(always)] + pub fn enable_tmrdisable(self) -> &'a mut crate::W { + self.variant(Tstop::EnableTmrdisable) + } + #[doc = "Enabled on timer compare and timer disable"] + #[inline(always)] + pub fn enable_tmr_cmp_dis(self) -> &'a mut crate::W { + self.variant(Tstop::EnableTmrCmpDis) + } +} +#[doc = "Timer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Timena { + #[doc = "0: Timer always enabled"] + Enable = 0, + #[doc = "1: Timer enabled on timer n-1 enable"] + TmrNminus1En = 1, + #[doc = "2: Timer enabled on trigger high"] + TmrTrighiEn = 2, + #[doc = "3: Timer enabled on trigger high and pin high"] + TmrTrigPinHiEn = 3, + #[doc = "4: Timer enabled on pin rising edge"] + TmrPinriseEn = 4, + #[doc = "5: Timer enabled on pin rising edge and trigger high"] + TmrPinriseTrighiEn = 5, + #[doc = "6: Timer enabled on trigger rising edge"] + TmrTrigriseEn = 6, + #[doc = "7: Timer enabled on trigger rising or falling edge"] + TmrTrigedgeEn = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Timena) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Timena { + type Ux = u8; +} +impl crate::IsEnum for Timena {} +#[doc = "Field `TIMENA` reader - Timer Enable"] +pub type TimenaR = crate::FieldReader; +impl TimenaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timena { + match self.bits { + 0 => Timena::Enable, + 1 => Timena::TmrNminus1En, + 2 => Timena::TmrTrighiEn, + 3 => Timena::TmrTrigPinHiEn, + 4 => Timena::TmrPinriseEn, + 5 => Timena::TmrPinriseTrighiEn, + 6 => Timena::TmrTrigriseEn, + 7 => Timena::TmrTrigedgeEn, + _ => unreachable!(), + } + } + #[doc = "Timer always enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Timena::Enable + } + #[doc = "Timer enabled on timer n-1 enable"] + #[inline(always)] + pub fn is_tmr_nminus1_en(&self) -> bool { + *self == Timena::TmrNminus1En + } + #[doc = "Timer enabled on trigger high"] + #[inline(always)] + pub fn is_tmr_trighi_en(&self) -> bool { + *self == Timena::TmrTrighiEn + } + #[doc = "Timer enabled on trigger high and pin high"] + #[inline(always)] + pub fn is_tmr_trig_pin_hi_en(&self) -> bool { + *self == Timena::TmrTrigPinHiEn + } + #[doc = "Timer enabled on pin rising edge"] + #[inline(always)] + pub fn is_tmr_pinrise_en(&self) -> bool { + *self == Timena::TmrPinriseEn + } + #[doc = "Timer enabled on pin rising edge and trigger high"] + #[inline(always)] + pub fn is_tmr_pinrise_trighi_en(&self) -> bool { + *self == Timena::TmrPinriseTrighiEn + } + #[doc = "Timer enabled on trigger rising edge"] + #[inline(always)] + pub fn is_tmr_trigrise_en(&self) -> bool { + *self == Timena::TmrTrigriseEn + } + #[doc = "Timer enabled on trigger rising or falling edge"] + #[inline(always)] + pub fn is_tmr_trigedge_en(&self) -> bool { + *self == Timena::TmrTrigedgeEn + } +} +#[doc = "Field `TIMENA` writer - Timer Enable"] +pub type TimenaW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timena, crate::Safe>; +impl<'a, REG> TimenaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Timer always enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Timena::Enable) + } + #[doc = "Timer enabled on timer n-1 enable"] + #[inline(always)] + pub fn tmr_nminus1_en(self) -> &'a mut crate::W { + self.variant(Timena::TmrNminus1En) + } + #[doc = "Timer enabled on trigger high"] + #[inline(always)] + pub fn tmr_trighi_en(self) -> &'a mut crate::W { + self.variant(Timena::TmrTrighiEn) + } + #[doc = "Timer enabled on trigger high and pin high"] + #[inline(always)] + pub fn tmr_trig_pin_hi_en(self) -> &'a mut crate::W { + self.variant(Timena::TmrTrigPinHiEn) + } + #[doc = "Timer enabled on pin rising edge"] + #[inline(always)] + pub fn tmr_pinrise_en(self) -> &'a mut crate::W { + self.variant(Timena::TmrPinriseEn) + } + #[doc = "Timer enabled on pin rising edge and trigger high"] + #[inline(always)] + pub fn tmr_pinrise_trighi_en(self) -> &'a mut crate::W { + self.variant(Timena::TmrPinriseTrighiEn) + } + #[doc = "Timer enabled on trigger rising edge"] + #[inline(always)] + pub fn tmr_trigrise_en(self) -> &'a mut crate::W { + self.variant(Timena::TmrTrigriseEn) + } + #[doc = "Timer enabled on trigger rising or falling edge"] + #[inline(always)] + pub fn tmr_trigedge_en(self) -> &'a mut crate::W { + self.variant(Timena::TmrTrigedgeEn) + } +} +#[doc = "Timer Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Timdis { + #[doc = "0: Timer never disabled"] + Never = 0, + #[doc = "1: Timer disabled on timer n-1 disable"] + TmrNminus1 = 1, + #[doc = "2: Timer disabled on timer compare (upper 8 bits match and decrement)"] + TmrCmp = 2, + #[doc = "3: Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"] + TmrCmpTriglow = 3, + #[doc = "4: Timer disabled on pin rising or falling edge"] + PinEdge = 4, + #[doc = "5: Timer disabled on pin rising or falling edge provided trigger is high"] + PinEdgeTrighi = 5, + #[doc = "6: Timer disabled on trigger falling edge"] + TrigFalledge = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Timdis) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Timdis { + type Ux = u8; +} +impl crate::IsEnum for Timdis {} +#[doc = "Field `TIMDIS` reader - Timer Disable"] +pub type TimdisR = crate::FieldReader; +impl TimdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Timdis::Never), + 1 => Some(Timdis::TmrNminus1), + 2 => Some(Timdis::TmrCmp), + 3 => Some(Timdis::TmrCmpTriglow), + 4 => Some(Timdis::PinEdge), + 5 => Some(Timdis::PinEdgeTrighi), + 6 => Some(Timdis::TrigFalledge), + _ => None, + } + } + #[doc = "Timer never disabled"] + #[inline(always)] + pub fn is_never(&self) -> bool { + *self == Timdis::Never + } + #[doc = "Timer disabled on timer n-1 disable"] + #[inline(always)] + pub fn is_tmr_nminus1(&self) -> bool { + *self == Timdis::TmrNminus1 + } + #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement)"] + #[inline(always)] + pub fn is_tmr_cmp(&self) -> bool { + *self == Timdis::TmrCmp + } + #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"] + #[inline(always)] + pub fn is_tmr_cmp_triglow(&self) -> bool { + *self == Timdis::TmrCmpTriglow + } + #[doc = "Timer disabled on pin rising or falling edge"] + #[inline(always)] + pub fn is_pin_edge(&self) -> bool { + *self == Timdis::PinEdge + } + #[doc = "Timer disabled on pin rising or falling edge provided trigger is high"] + #[inline(always)] + pub fn is_pin_edge_trighi(&self) -> bool { + *self == Timdis::PinEdgeTrighi + } + #[doc = "Timer disabled on trigger falling edge"] + #[inline(always)] + pub fn is_trig_falledge(&self) -> bool { + *self == Timdis::TrigFalledge + } +} +#[doc = "Field `TIMDIS` writer - Timer Disable"] +pub type TimdisW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timdis>; +impl<'a, REG> TimdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Timer never disabled"] + #[inline(always)] + pub fn never(self) -> &'a mut crate::W { + self.variant(Timdis::Never) + } + #[doc = "Timer disabled on timer n-1 disable"] + #[inline(always)] + pub fn tmr_nminus1(self) -> &'a mut crate::W { + self.variant(Timdis::TmrNminus1) + } + #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement)"] + #[inline(always)] + pub fn tmr_cmp(self) -> &'a mut crate::W { + self.variant(Timdis::TmrCmp) + } + #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"] + #[inline(always)] + pub fn tmr_cmp_triglow(self) -> &'a mut crate::W { + self.variant(Timdis::TmrCmpTriglow) + } + #[doc = "Timer disabled on pin rising or falling edge"] + #[inline(always)] + pub fn pin_edge(self) -> &'a mut crate::W { + self.variant(Timdis::PinEdge) + } + #[doc = "Timer disabled on pin rising or falling edge provided trigger is high"] + #[inline(always)] + pub fn pin_edge_trighi(self) -> &'a mut crate::W { + self.variant(Timdis::PinEdgeTrighi) + } + #[doc = "Timer disabled on trigger falling edge"] + #[inline(always)] + pub fn trig_falledge(self) -> &'a mut crate::W { + self.variant(Timdis::TrigFalledge) + } +} +#[doc = "Timer Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Timrst { + #[doc = "0: Never reset timer"] + Never = 0, + #[doc = "1: Timer reset on timer output high."] + TmrOutHi = 1, + #[doc = "2: Timer reset on timer pin equal to timer output"] + PinEqTmrOut = 2, + #[doc = "3: Timer reset on timer trigger equal to timer output"] + TrigEqTmrOut = 3, + #[doc = "4: Timer reset on timer pin rising edge"] + PinRiseEdge = 4, + #[doc = "6: Timer reset on trigger rising edge"] + TrigRiseEdge = 6, + #[doc = "7: Timer reset on trigger rising or falling edge"] + TrigEdge = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Timrst) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Timrst { + type Ux = u8; +} +impl crate::IsEnum for Timrst {} +#[doc = "Field `TIMRST` reader - Timer Reset"] +pub type TimrstR = crate::FieldReader; +impl TimrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Timrst::Never), + 1 => Some(Timrst::TmrOutHi), + 2 => Some(Timrst::PinEqTmrOut), + 3 => Some(Timrst::TrigEqTmrOut), + 4 => Some(Timrst::PinRiseEdge), + 6 => Some(Timrst::TrigRiseEdge), + 7 => Some(Timrst::TrigEdge), + _ => None, + } + } + #[doc = "Never reset timer"] + #[inline(always)] + pub fn is_never(&self) -> bool { + *self == Timrst::Never + } + #[doc = "Timer reset on timer output high."] + #[inline(always)] + pub fn is_tmr_out_hi(&self) -> bool { + *self == Timrst::TmrOutHi + } + #[doc = "Timer reset on timer pin equal to timer output"] + #[inline(always)] + pub fn is_pin_eq_tmr_out(&self) -> bool { + *self == Timrst::PinEqTmrOut + } + #[doc = "Timer reset on timer trigger equal to timer output"] + #[inline(always)] + pub fn is_trig_eq_tmr_out(&self) -> bool { + *self == Timrst::TrigEqTmrOut + } + #[doc = "Timer reset on timer pin rising edge"] + #[inline(always)] + pub fn is_pin_rise_edge(&self) -> bool { + *self == Timrst::PinRiseEdge + } + #[doc = "Timer reset on trigger rising edge"] + #[inline(always)] + pub fn is_trig_rise_edge(&self) -> bool { + *self == Timrst::TrigRiseEdge + } + #[doc = "Timer reset on trigger rising or falling edge"] + #[inline(always)] + pub fn is_trig_edge(&self) -> bool { + *self == Timrst::TrigEdge + } +} +#[doc = "Field `TIMRST` writer - Timer Reset"] +pub type TimrstW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timrst>; +impl<'a, REG> TimrstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Never reset timer"] + #[inline(always)] + pub fn never(self) -> &'a mut crate::W { + self.variant(Timrst::Never) + } + #[doc = "Timer reset on timer output high."] + #[inline(always)] + pub fn tmr_out_hi(self) -> &'a mut crate::W { + self.variant(Timrst::TmrOutHi) + } + #[doc = "Timer reset on timer pin equal to timer output"] + #[inline(always)] + pub fn pin_eq_tmr_out(self) -> &'a mut crate::W { + self.variant(Timrst::PinEqTmrOut) + } + #[doc = "Timer reset on timer trigger equal to timer output"] + #[inline(always)] + pub fn trig_eq_tmr_out(self) -> &'a mut crate::W { + self.variant(Timrst::TrigEqTmrOut) + } + #[doc = "Timer reset on timer pin rising edge"] + #[inline(always)] + pub fn pin_rise_edge(self) -> &'a mut crate::W { + self.variant(Timrst::PinRiseEdge) + } + #[doc = "Timer reset on trigger rising edge"] + #[inline(always)] + pub fn trig_rise_edge(self) -> &'a mut crate::W { + self.variant(Timrst::TrigRiseEdge) + } + #[doc = "Timer reset on trigger rising or falling edge"] + #[inline(always)] + pub fn trig_edge(self) -> &'a mut crate::W { + self.variant(Timrst::TrigEdge) + } +} +#[doc = "Timer Decrement\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Timdec { + #[doc = "0: Decrement counter on FLEXIO clock; shift clock equals timer output"] + FlexioClkShiftclkTmrOut = 0, + #[doc = "1: Decrement counter on trigger input (both edges); shift clock equals timer output"] + TrigEdgeShiftclkTmrOut = 1, + #[doc = "2: Decrement counter on pin input (both edges); shift clock equals pin input"] + PinEdgeShiftclkTmrOut = 2, + #[doc = "3: Decrement counter on trigger input (both edges); shift clock equals trigger input"] + TrigEdgeShiftclkTrigIn = 3, + #[doc = "4: Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"] + FlexioClkDiv16ShiftclkTmrOut = 4, + #[doc = "5: Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"] + FlexioClkDiv256ShiftclkTmrOut = 5, + #[doc = "6: Decrement counter on pin input (rising edge); shift clock equals pin input"] + PinRiseShiftclkPinIn = 6, + #[doc = "7: Decrement counter on trigger input (rising edge); shift clock equals trigger input"] + TrigRiseShiftclkTrigIn = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Timdec) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Timdec { + type Ux = u8; +} +impl crate::IsEnum for Timdec {} +#[doc = "Field `TIMDEC` reader - Timer Decrement"] +pub type TimdecR = crate::FieldReader; +impl TimdecR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timdec { + match self.bits { + 0 => Timdec::FlexioClkShiftclkTmrOut, + 1 => Timdec::TrigEdgeShiftclkTmrOut, + 2 => Timdec::PinEdgeShiftclkTmrOut, + 3 => Timdec::TrigEdgeShiftclkTrigIn, + 4 => Timdec::FlexioClkDiv16ShiftclkTmrOut, + 5 => Timdec::FlexioClkDiv256ShiftclkTmrOut, + 6 => Timdec::PinRiseShiftclkPinIn, + 7 => Timdec::TrigRiseShiftclkTrigIn, + _ => unreachable!(), + } + } + #[doc = "Decrement counter on FLEXIO clock; shift clock equals timer output"] + #[inline(always)] + pub fn is_flexio_clk_shiftclk_tmr_out(&self) -> bool { + *self == Timdec::FlexioClkShiftclkTmrOut + } + #[doc = "Decrement counter on trigger input (both edges); shift clock equals timer output"] + #[inline(always)] + pub fn is_trig_edge_shiftclk_tmr_out(&self) -> bool { + *self == Timdec::TrigEdgeShiftclkTmrOut + } + #[doc = "Decrement counter on pin input (both edges); shift clock equals pin input"] + #[inline(always)] + pub fn is_pin_edge_shiftclk_tmr_out(&self) -> bool { + *self == Timdec::PinEdgeShiftclkTmrOut + } + #[doc = "Decrement counter on trigger input (both edges); shift clock equals trigger input"] + #[inline(always)] + pub fn is_trig_edge_shiftclk_trig_in(&self) -> bool { + *self == Timdec::TrigEdgeShiftclkTrigIn + } + #[doc = "Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"] + #[inline(always)] + pub fn is_flexio_clk_div16_shiftclk_tmr_out(&self) -> bool { + *self == Timdec::FlexioClkDiv16ShiftclkTmrOut + } + #[doc = "Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"] + #[inline(always)] + pub fn is_flexio_clk_div256_shiftclk_tmr_out(&self) -> bool { + *self == Timdec::FlexioClkDiv256ShiftclkTmrOut + } + #[doc = "Decrement counter on pin input (rising edge); shift clock equals pin input"] + #[inline(always)] + pub fn is_pin_rise_shiftclk_pin_in(&self) -> bool { + *self == Timdec::PinRiseShiftclkPinIn + } + #[doc = "Decrement counter on trigger input (rising edge); shift clock equals trigger input"] + #[inline(always)] + pub fn is_trig_rise_shiftclk_trig_in(&self) -> bool { + *self == Timdec::TrigRiseShiftclkTrigIn + } +} +#[doc = "Field `TIMDEC` writer - Timer Decrement"] +pub type TimdecW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timdec, crate::Safe>; +impl<'a, REG> TimdecW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Decrement counter on FLEXIO clock; shift clock equals timer output"] + #[inline(always)] + pub fn flexio_clk_shiftclk_tmr_out(self) -> &'a mut crate::W { + self.variant(Timdec::FlexioClkShiftclkTmrOut) + } + #[doc = "Decrement counter on trigger input (both edges); shift clock equals timer output"] + #[inline(always)] + pub fn trig_edge_shiftclk_tmr_out(self) -> &'a mut crate::W { + self.variant(Timdec::TrigEdgeShiftclkTmrOut) + } + #[doc = "Decrement counter on pin input (both edges); shift clock equals pin input"] + #[inline(always)] + pub fn pin_edge_shiftclk_tmr_out(self) -> &'a mut crate::W { + self.variant(Timdec::PinEdgeShiftclkTmrOut) + } + #[doc = "Decrement counter on trigger input (both edges); shift clock equals trigger input"] + #[inline(always)] + pub fn trig_edge_shiftclk_trig_in(self) -> &'a mut crate::W { + self.variant(Timdec::TrigEdgeShiftclkTrigIn) + } + #[doc = "Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"] + #[inline(always)] + pub fn flexio_clk_div16_shiftclk_tmr_out(self) -> &'a mut crate::W { + self.variant(Timdec::FlexioClkDiv16ShiftclkTmrOut) + } + #[doc = "Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"] + #[inline(always)] + pub fn flexio_clk_div256_shiftclk_tmr_out(self) -> &'a mut crate::W { + self.variant(Timdec::FlexioClkDiv256ShiftclkTmrOut) + } + #[doc = "Decrement counter on pin input (rising edge); shift clock equals pin input"] + #[inline(always)] + pub fn pin_rise_shiftclk_pin_in(self) -> &'a mut crate::W { + self.variant(Timdec::PinRiseShiftclkPinIn) + } + #[doc = "Decrement counter on trigger input (rising edge); shift clock equals trigger input"] + #[inline(always)] + pub fn trig_rise_shiftclk_trig_in(self) -> &'a mut crate::W { + self.variant(Timdec::TrigRiseShiftclkTrigIn) + } +} +#[doc = "Timer Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Timout { + #[doc = "0: Logic one when enabled; not affected by timer reset"] + One = 0, + #[doc = "1: Logic zero when enabled; not affected by timer reset"] + Zero = 1, + #[doc = "2: Logic one when enabled and on timer reset"] + OneTmrreset = 2, + #[doc = "3: Logic zero when enabled and on timer reset"] + ZeroTmrreset = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Timout) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Timout { + type Ux = u8; +} +impl crate::IsEnum for Timout {} +#[doc = "Field `TIMOUT` reader - Timer Output"] +pub type TimoutR = crate::FieldReader; +impl TimoutR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timout { + match self.bits { + 0 => Timout::One, + 1 => Timout::Zero, + 2 => Timout::OneTmrreset, + 3 => Timout::ZeroTmrreset, + _ => unreachable!(), + } + } + #[doc = "Logic one when enabled; not affected by timer reset"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Timout::One + } + #[doc = "Logic zero when enabled; not affected by timer reset"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + *self == Timout::Zero + } + #[doc = "Logic one when enabled and on timer reset"] + #[inline(always)] + pub fn is_one_tmrreset(&self) -> bool { + *self == Timout::OneTmrreset + } + #[doc = "Logic zero when enabled and on timer reset"] + #[inline(always)] + pub fn is_zero_tmrreset(&self) -> bool { + *self == Timout::ZeroTmrreset + } +} +#[doc = "Field `TIMOUT` writer - Timer Output"] +pub type TimoutW<'a, REG> = crate::FieldWriter<'a, REG, 2, Timout, crate::Safe>; +impl<'a, REG> TimoutW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Logic one when enabled; not affected by timer reset"] + #[inline(always)] + pub fn one(self) -> &'a mut crate::W { + self.variant(Timout::One) + } + #[doc = "Logic zero when enabled; not affected by timer reset"] + #[inline(always)] + pub fn zero(self) -> &'a mut crate::W { + self.variant(Timout::Zero) + } + #[doc = "Logic one when enabled and on timer reset"] + #[inline(always)] + pub fn one_tmrreset(self) -> &'a mut crate::W { + self.variant(Timout::OneTmrreset) + } + #[doc = "Logic zero when enabled and on timer reset"] + #[inline(always)] + pub fn zero_tmrreset(self) -> &'a mut crate::W { + self.variant(Timout::ZeroTmrreset) + } +} +impl R { + #[doc = "Bit 1 - Timer Start"] + #[inline(always)] + pub fn tstart(&self) -> TstartR { + TstartR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:5 - Timer Stop"] + #[inline(always)] + pub fn tstop(&self) -> TstopR { + TstopR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:10 - Timer Enable"] + #[inline(always)] + pub fn timena(&self) -> TimenaR { + TimenaR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:14 - Timer Disable"] + #[inline(always)] + pub fn timdis(&self) -> TimdisR { + TimdisR::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 16:18 - Timer Reset"] + #[inline(always)] + pub fn timrst(&self) -> TimrstR { + TimrstR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 20:22 - Timer Decrement"] + #[inline(always)] + pub fn timdec(&self) -> TimdecR { + TimdecR::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bits 24:25 - Timer Output"] + #[inline(always)] + pub fn timout(&self) -> TimoutR { + TimoutR::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bit 1 - Timer Start"] + #[inline(always)] + pub fn tstart(&mut self) -> TstartW { + TstartW::new(self, 1) + } + #[doc = "Bits 4:5 - Timer Stop"] + #[inline(always)] + pub fn tstop(&mut self) -> TstopW { + TstopW::new(self, 4) + } + #[doc = "Bits 8:10 - Timer Enable"] + #[inline(always)] + pub fn timena(&mut self) -> TimenaW { + TimenaW::new(self, 8) + } + #[doc = "Bits 12:14 - Timer Disable"] + #[inline(always)] + pub fn timdis(&mut self) -> TimdisW { + TimdisW::new(self, 12) + } + #[doc = "Bits 16:18 - Timer Reset"] + #[inline(always)] + pub fn timrst(&mut self) -> TimrstW { + TimrstW::new(self, 16) + } + #[doc = "Bits 20:22 - Timer Decrement"] + #[inline(always)] + pub fn timdec(&mut self) -> TimdecW { + TimdecW::new(self, 20) + } + #[doc = "Bits 24:25 - Timer Output"] + #[inline(always)] + pub fn timout(&mut self) -> TimoutW { + TimoutW::new(self, 24) + } +} +#[doc = "Timer Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`timcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimcfgSpec; +impl crate::RegisterSpec for TimcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timcfg::R`](R) reader structure"] +impl crate::Readable for TimcfgSpec {} +#[doc = "`write(|w| ..)` method takes [`timcfg::W`](W) writer structure"] +impl crate::Writable for TimcfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMCFG[%s] to value 0"] +impl crate::Resettable for TimcfgSpec {} diff --git a/mcxa276-pac/src/flexio0/timcmp.rs b/mcxa276-pac/src/flexio0/timcmp.rs new file mode 100644 index 000000000..24ba62c6d --- /dev/null +++ b/mcxa276-pac/src/flexio0/timcmp.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TIMCMP[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `TIMCMP[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `CMP` reader - Timer Compare Value"] +pub type CmpR = crate::FieldReader; +#[doc = "Field `CMP` writer - Timer Compare Value"] +pub type CmpW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timer Compare Value"] + #[inline(always)] + pub fn cmp(&self) -> CmpR { + CmpR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timer Compare Value"] + #[inline(always)] + pub fn cmp(&mut self) -> CmpW { + CmpW::new(self, 0) + } +} +#[doc = "Timer Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`timcmp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcmp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimcmpSpec; +impl crate::RegisterSpec for TimcmpSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timcmp::R`](R) reader structure"] +impl crate::Readable for TimcmpSpec {} +#[doc = "`write(|w| ..)` method takes [`timcmp::W`](W) writer structure"] +impl crate::Writable for TimcmpSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMCMP[%s] to value 0"] +impl crate::Resettable for TimcmpSpec {} diff --git a/mcxa276-pac/src/flexio0/timctl.rs b/mcxa276-pac/src/flexio0/timctl.rs new file mode 100644 index 000000000..333ef6ad1 --- /dev/null +++ b/mcxa276-pac/src/flexio0/timctl.rs @@ -0,0 +1,608 @@ +#[doc = "Register `TIMCTL[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `TIMCTL[%s]` writer"] +pub type W = crate::W; +#[doc = "Timer Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Timod { + #[doc = "0: Timer disabled"] + Disable = 0, + #[doc = "1: Dual 8-bit counters baud mode"] + Dual8bitBaud = 1, + #[doc = "2: Dual 8-bit counters PWM high mode"] + Dual8bitPwmH = 2, + #[doc = "3: Single 16-bit counter mode"] + Single16bit = 3, + #[doc = "4: Single 16-bit counter disable mode"] + Single16bitDisable = 4, + #[doc = "5: Dual 8-bit counters word mode"] + Dual8bitWord = 5, + #[doc = "6: Dual 8-bit counters PWM low mode"] + Dual8bitPwmL = 6, + #[doc = "7: Single 16-bit input capture mode"] + Single16bitInCapture = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Timod) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Timod { + type Ux = u8; +} +impl crate::IsEnum for Timod {} +#[doc = "Field `TIMOD` reader - Timer Mode"] +pub type TimodR = crate::FieldReader; +impl TimodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timod { + match self.bits { + 0 => Timod::Disable, + 1 => Timod::Dual8bitBaud, + 2 => Timod::Dual8bitPwmH, + 3 => Timod::Single16bit, + 4 => Timod::Single16bitDisable, + 5 => Timod::Dual8bitWord, + 6 => Timod::Dual8bitPwmL, + 7 => Timod::Single16bitInCapture, + _ => unreachable!(), + } + } + #[doc = "Timer disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Timod::Disable + } + #[doc = "Dual 8-bit counters baud mode"] + #[inline(always)] + pub fn is_dual8bit_baud(&self) -> bool { + *self == Timod::Dual8bitBaud + } + #[doc = "Dual 8-bit counters PWM high mode"] + #[inline(always)] + pub fn is_dual8bit_pwm_h(&self) -> bool { + *self == Timod::Dual8bitPwmH + } + #[doc = "Single 16-bit counter mode"] + #[inline(always)] + pub fn is_single16bit(&self) -> bool { + *self == Timod::Single16bit + } + #[doc = "Single 16-bit counter disable mode"] + #[inline(always)] + pub fn is_single16bit_disable(&self) -> bool { + *self == Timod::Single16bitDisable + } + #[doc = "Dual 8-bit counters word mode"] + #[inline(always)] + pub fn is_dual8bit_word(&self) -> bool { + *self == Timod::Dual8bitWord + } + #[doc = "Dual 8-bit counters PWM low mode"] + #[inline(always)] + pub fn is_dual8bit_pwm_l(&self) -> bool { + *self == Timod::Dual8bitPwmL + } + #[doc = "Single 16-bit input capture mode"] + #[inline(always)] + pub fn is_single16bit_in_capture(&self) -> bool { + *self == Timod::Single16bitInCapture + } +} +#[doc = "Field `TIMOD` writer - Timer Mode"] +pub type TimodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timod, crate::Safe>; +impl<'a, REG> TimodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Timer disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Timod::Disable) + } + #[doc = "Dual 8-bit counters baud mode"] + #[inline(always)] + pub fn dual8bit_baud(self) -> &'a mut crate::W { + self.variant(Timod::Dual8bitBaud) + } + #[doc = "Dual 8-bit counters PWM high mode"] + #[inline(always)] + pub fn dual8bit_pwm_h(self) -> &'a mut crate::W { + self.variant(Timod::Dual8bitPwmH) + } + #[doc = "Single 16-bit counter mode"] + #[inline(always)] + pub fn single16bit(self) -> &'a mut crate::W { + self.variant(Timod::Single16bit) + } + #[doc = "Single 16-bit counter disable mode"] + #[inline(always)] + pub fn single16bit_disable(self) -> &'a mut crate::W { + self.variant(Timod::Single16bitDisable) + } + #[doc = "Dual 8-bit counters word mode"] + #[inline(always)] + pub fn dual8bit_word(self) -> &'a mut crate::W { + self.variant(Timod::Dual8bitWord) + } + #[doc = "Dual 8-bit counters PWM low mode"] + #[inline(always)] + pub fn dual8bit_pwm_l(self) -> &'a mut crate::W { + self.variant(Timod::Dual8bitPwmL) + } + #[doc = "Single 16-bit input capture mode"] + #[inline(always)] + pub fn single16bit_in_capture(self) -> &'a mut crate::W { + self.variant(Timod::Single16bitInCapture) + } +} +#[doc = "Timer One Time Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Onetim { + #[doc = "0: Generate the timer enable event as normal"] + NotBlocked = 0, + #[doc = "1: Block the timer enable event unless the timer status flag is clear"] + Blocked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Onetim) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONETIM` reader - Timer One Time Operation"] +pub type OnetimR = crate::BitReader; +impl OnetimR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Onetim { + match self.bits { + false => Onetim::NotBlocked, + true => Onetim::Blocked, + } + } + #[doc = "Generate the timer enable event as normal"] + #[inline(always)] + pub fn is_not_blocked(&self) -> bool { + *self == Onetim::NotBlocked + } + #[doc = "Block the timer enable event unless the timer status flag is clear"] + #[inline(always)] + pub fn is_blocked(&self) -> bool { + *self == Onetim::Blocked + } +} +#[doc = "Field `ONETIM` writer - Timer One Time Operation"] +pub type OnetimW<'a, REG> = crate::BitWriter<'a, REG, Onetim>; +impl<'a, REG> OnetimW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Generate the timer enable event as normal"] + #[inline(always)] + pub fn not_blocked(self) -> &'a mut crate::W { + self.variant(Onetim::NotBlocked) + } + #[doc = "Block the timer enable event unless the timer status flag is clear"] + #[inline(always)] + pub fn blocked(self) -> &'a mut crate::W { + self.variant(Onetim::Blocked) + } +} +#[doc = "Timer Pin Input Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pinins { + #[doc = "0: PINSEL selects timer pin input and output"] + Pinsel = 0, + #[doc = "1: PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL"] + Pinselplus1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pinins) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PININS` reader - Timer Pin Input Select"] +pub type PininsR = crate::BitReader; +impl PininsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pinins { + match self.bits { + false => Pinins::Pinsel, + true => Pinins::Pinselplus1, + } + } + #[doc = "PINSEL selects timer pin input and output"] + #[inline(always)] + pub fn is_pinsel(&self) -> bool { + *self == Pinins::Pinsel + } + #[doc = "PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL"] + #[inline(always)] + pub fn is_pinselplus1(&self) -> bool { + *self == Pinins::Pinselplus1 + } +} +#[doc = "Field `PININS` writer - Timer Pin Input Select"] +pub type PininsW<'a, REG> = crate::BitWriter<'a, REG, Pinins>; +impl<'a, REG> PininsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PINSEL selects timer pin input and output"] + #[inline(always)] + pub fn pinsel(self) -> &'a mut crate::W { + self.variant(Pinins::Pinsel) + } + #[doc = "PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL"] + #[inline(always)] + pub fn pinselplus1(self) -> &'a mut crate::W { + self.variant(Pinins::Pinselplus1) + } +} +#[doc = "Timer Pin Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pinpol { + #[doc = "0: Active high"] + ActiveHigh = 0, + #[doc = "1: Active low"] + ActiveLow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pinpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PINPOL` reader - Timer Pin Polarity"] +pub type PinpolR = crate::BitReader; +impl PinpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pinpol { + match self.bits { + false => Pinpol::ActiveHigh, + true => Pinpol::ActiveLow, + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == Pinpol::ActiveHigh + } + #[doc = "Active low"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == Pinpol::ActiveLow + } +} +#[doc = "Field `PINPOL` writer - Timer Pin Polarity"] +pub type PinpolW<'a, REG> = crate::BitWriter<'a, REG, Pinpol>; +impl<'a, REG> PinpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut crate::W { + self.variant(Pinpol::ActiveHigh) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut crate::W { + self.variant(Pinpol::ActiveLow) + } +} +#[doc = "Field `PINSEL` reader - Timer Pin Select"] +pub type PinselR = crate::FieldReader; +#[doc = "Field `PINSEL` writer - Timer Pin Select"] +pub type PinselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Timer Pin Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pincfg { + #[doc = "0: Timer pin output disabled"] + Outdisable = 0, + #[doc = "1: Timer pin open-drain or bidirectional output enable"] + OpendBidirouten = 1, + #[doc = "2: Timer pin bidirectional output data"] + BidirOutdata = 2, + #[doc = "3: Timer pin output"] + Output = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pincfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pincfg { + type Ux = u8; +} +impl crate::IsEnum for Pincfg {} +#[doc = "Field `PINCFG` reader - Timer Pin Configuration"] +pub type PincfgR = crate::FieldReader; +impl PincfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pincfg { + match self.bits { + 0 => Pincfg::Outdisable, + 1 => Pincfg::OpendBidirouten, + 2 => Pincfg::BidirOutdata, + 3 => Pincfg::Output, + _ => unreachable!(), + } + } + #[doc = "Timer pin output disabled"] + #[inline(always)] + pub fn is_outdisable(&self) -> bool { + *self == Pincfg::Outdisable + } + #[doc = "Timer pin open-drain or bidirectional output enable"] + #[inline(always)] + pub fn is_opend_bidirouten(&self) -> bool { + *self == Pincfg::OpendBidirouten + } + #[doc = "Timer pin bidirectional output data"] + #[inline(always)] + pub fn is_bidir_outdata(&self) -> bool { + *self == Pincfg::BidirOutdata + } + #[doc = "Timer pin output"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == Pincfg::Output + } +} +#[doc = "Field `PINCFG` writer - Timer Pin Configuration"] +pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pincfg, crate::Safe>; +impl<'a, REG> PincfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Timer pin output disabled"] + #[inline(always)] + pub fn outdisable(self) -> &'a mut crate::W { + self.variant(Pincfg::Outdisable) + } + #[doc = "Timer pin open-drain or bidirectional output enable"] + #[inline(always)] + pub fn opend_bidirouten(self) -> &'a mut crate::W { + self.variant(Pincfg::OpendBidirouten) + } + #[doc = "Timer pin bidirectional output data"] + #[inline(always)] + pub fn bidir_outdata(self) -> &'a mut crate::W { + self.variant(Pincfg::BidirOutdata) + } + #[doc = "Timer pin output"] + #[inline(always)] + pub fn output(self) -> &'a mut crate::W { + self.variant(Pincfg::Output) + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trgsrc { + #[doc = "0: External"] + ExtTrig = 0, + #[doc = "1: Internal"] + InternalTrig = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trgsrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRGSRC` reader - Trigger Source"] +pub type TrgsrcR = crate::BitReader; +impl TrgsrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgsrc { + match self.bits { + false => Trgsrc::ExtTrig, + true => Trgsrc::InternalTrig, + } + } + #[doc = "External"] + #[inline(always)] + pub fn is_ext_trig(&self) -> bool { + *self == Trgsrc::ExtTrig + } + #[doc = "Internal"] + #[inline(always)] + pub fn is_internal_trig(&self) -> bool { + *self == Trgsrc::InternalTrig + } +} +#[doc = "Field `TRGSRC` writer - Trigger Source"] +pub type TrgsrcW<'a, REG> = crate::BitWriter<'a, REG, Trgsrc>; +impl<'a, REG> TrgsrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "External"] + #[inline(always)] + pub fn ext_trig(self) -> &'a mut crate::W { + self.variant(Trgsrc::ExtTrig) + } + #[doc = "Internal"] + #[inline(always)] + pub fn internal_trig(self) -> &'a mut crate::W { + self.variant(Trgsrc::InternalTrig) + } +} +#[doc = "Trigger Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trgpol { + #[doc = "0: Active high"] + ActiveHigh = 0, + #[doc = "1: Active low"] + ActiveLow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trgpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRGPOL` reader - Trigger Polarity"] +pub type TrgpolR = crate::BitReader; +impl TrgpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgpol { + match self.bits { + false => Trgpol::ActiveHigh, + true => Trgpol::ActiveLow, + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == Trgpol::ActiveHigh + } + #[doc = "Active low"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == Trgpol::ActiveLow + } +} +#[doc = "Field `TRGPOL` writer - Trigger Polarity"] +pub type TrgpolW<'a, REG> = crate::BitWriter<'a, REG, Trgpol>; +impl<'a, REG> TrgpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut crate::W { + self.variant(Trgpol::ActiveHigh) + } + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut crate::W { + self.variant(Trgpol::ActiveLow) + } +} +#[doc = "Field `TRGSEL` reader - Trigger Select"] +pub type TrgselR = crate::FieldReader; +#[doc = "Field `TRGSEL` writer - Trigger Select"] +pub type TrgselW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:2 - Timer Mode"] + #[inline(always)] + pub fn timod(&self) -> TimodR { + TimodR::new((self.bits & 7) as u8) + } + #[doc = "Bit 5 - Timer One Time Operation"] + #[inline(always)] + pub fn onetim(&self) -> OnetimR { + OnetimR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Timer Pin Input Select"] + #[inline(always)] + pub fn pinins(&self) -> PininsR { + PininsR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Timer Pin Polarity"] + #[inline(always)] + pub fn pinpol(&self) -> PinpolR { + PinpolR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - Timer Pin Select"] + #[inline(always)] + pub fn pinsel(&self) -> PinselR { + PinselR::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:17 - Timer Pin Configuration"] + #[inline(always)] + pub fn pincfg(&self) -> PincfgR { + PincfgR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 22 - Trigger Source"] + #[inline(always)] + pub fn trgsrc(&self) -> TrgsrcR { + TrgsrcR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Trigger Polarity"] + #[inline(always)] + pub fn trgpol(&self) -> TrgpolR { + TrgpolR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:29 - Trigger Select"] + #[inline(always)] + pub fn trgsel(&self) -> TrgselR { + TrgselR::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Timer Mode"] + #[inline(always)] + pub fn timod(&mut self) -> TimodW { + TimodW::new(self, 0) + } + #[doc = "Bit 5 - Timer One Time Operation"] + #[inline(always)] + pub fn onetim(&mut self) -> OnetimW { + OnetimW::new(self, 5) + } + #[doc = "Bit 6 - Timer Pin Input Select"] + #[inline(always)] + pub fn pinins(&mut self) -> PininsW { + PininsW::new(self, 6) + } + #[doc = "Bit 7 - Timer Pin Polarity"] + #[inline(always)] + pub fn pinpol(&mut self) -> PinpolW { + PinpolW::new(self, 7) + } + #[doc = "Bits 8:12 - Timer Pin Select"] + #[inline(always)] + pub fn pinsel(&mut self) -> PinselW { + PinselW::new(self, 8) + } + #[doc = "Bits 16:17 - Timer Pin Configuration"] + #[inline(always)] + pub fn pincfg(&mut self) -> PincfgW { + PincfgW::new(self, 16) + } + #[doc = "Bit 22 - Trigger Source"] + #[inline(always)] + pub fn trgsrc(&mut self) -> TrgsrcW { + TrgsrcW::new(self, 22) + } + #[doc = "Bit 23 - Trigger Polarity"] + #[inline(always)] + pub fn trgpol(&mut self) -> TrgpolW { + TrgpolW::new(self, 23) + } + #[doc = "Bits 24:29 - Trigger Select"] + #[inline(always)] + pub fn trgsel(&mut self) -> TrgselW { + TrgselW::new(self, 24) + } +} +#[doc = "Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`timctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimctlSpec; +impl crate::RegisterSpec for TimctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timctl::R`](R) reader structure"] +impl crate::Readable for TimctlSpec {} +#[doc = "`write(|w| ..)` method takes [`timctl::W`](W) writer structure"] +impl crate::Writable for TimctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMCTL[%s] to value 0"] +impl crate::Resettable for TimctlSpec {} diff --git a/mcxa276-pac/src/flexio0/timersden.rs b/mcxa276-pac/src/flexio0/timersden.rs new file mode 100644 index 000000000..d0ef77437 --- /dev/null +++ b/mcxa276-pac/src/flexio0/timersden.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TIMERSDEN` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERSDEN` writer"] +pub type W = crate::W; +#[doc = "Field `TSDE` reader - Timer Status DMA Enable"] +pub type TsdeR = crate::FieldReader; +#[doc = "Field `TSDE` writer - Timer Status DMA Enable"] +pub type TsdeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Timer Status DMA Enable"] + #[inline(always)] + pub fn tsde(&self) -> TsdeR { + TsdeR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Timer Status DMA Enable"] + #[inline(always)] + pub fn tsde(&mut self) -> TsdeW { + TsdeW::new(self, 0) + } +} +#[doc = "Timer Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timersden::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timersden::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimersdenSpec; +impl crate::RegisterSpec for TimersdenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timersden::R`](R) reader structure"] +impl crate::Readable for TimersdenSpec {} +#[doc = "`write(|w| ..)` method takes [`timersden::W`](W) writer structure"] +impl crate::Writable for TimersdenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMERSDEN to value 0"] +impl crate::Resettable for TimersdenSpec {} diff --git a/mcxa276-pac/src/flexio0/timien.rs b/mcxa276-pac/src/flexio0/timien.rs new file mode 100644 index 000000000..eff390467 --- /dev/null +++ b/mcxa276-pac/src/flexio0/timien.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TIMIEN` reader"] +pub type R = crate::R; +#[doc = "Register `TIMIEN` writer"] +pub type W = crate::W; +#[doc = "Field `TEIE` reader - Timer Status Interrupt Enable"] +pub type TeieR = crate::FieldReader; +#[doc = "Field `TEIE` writer - Timer Status Interrupt Enable"] +pub type TeieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Timer Status Interrupt Enable"] + #[inline(always)] + pub fn teie(&self) -> TeieR { + TeieR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Timer Status Interrupt Enable"] + #[inline(always)] + pub fn teie(&mut self) -> TeieW { + TeieW::new(self, 0) + } +} +#[doc = "Timer Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimienSpec; +impl crate::RegisterSpec for TimienSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timien::R`](R) reader structure"] +impl crate::Readable for TimienSpec {} +#[doc = "`write(|w| ..)` method takes [`timien::W`](W) writer structure"] +impl crate::Writable for TimienSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMIEN to value 0"] +impl crate::Resettable for TimienSpec {} diff --git a/mcxa276-pac/src/flexio0/timstat.rs b/mcxa276-pac/src/flexio0/timstat.rs new file mode 100644 index 000000000..e8ff9ab62 --- /dev/null +++ b/mcxa276-pac/src/flexio0/timstat.rs @@ -0,0 +1,92 @@ +#[doc = "Register `TIMSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `TIMSTAT` writer"] +pub type W = crate::W; +#[doc = "Timer Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tsf { + #[doc = "0: Clear"] + Clr = 0, + #[doc = "1: Set"] + Set = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tsf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tsf { + type Ux = u8; +} +impl crate::IsEnum for Tsf {} +#[doc = "Field `TSF` reader - Timer Status Flag"] +pub type TsfR = crate::FieldReader; +impl TsfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Tsf::Clr), + 1 => Some(Tsf::Set), + _ => None, + } + } + #[doc = "Clear"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + *self == Tsf::Clr + } + #[doc = "Set"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Tsf::Set + } +} +#[doc = "Field `TSF` writer - Timer Status Flag"] +pub type TsfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Tsf>; +impl<'a, REG> TsfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Clear"] + #[inline(always)] + pub fn clr(self) -> &'a mut crate::W { + self.variant(Tsf::Clr) + } + #[doc = "Set"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Tsf::Set) + } +} +impl R { + #[doc = "Bits 0:3 - Timer Status Flag"] + #[inline(always)] + pub fn tsf(&self) -> TsfR { + TsfR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Timer Status Flag"] + #[inline(always)] + pub fn tsf(&mut self) -> TsfW { + TsfW::new(self, 0) + } +} +#[doc = "Timer Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`timstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimstatSpec; +impl crate::RegisterSpec for TimstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timstat::R`](R) reader structure"] +impl crate::Readable for TimstatSpec {} +#[doc = "`write(|w| ..)` method takes [`timstat::W`](W) writer structure"] +impl crate::Writable for TimstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets TIMSTAT to value 0"] +impl crate::Resettable for TimstatSpec {} diff --git a/mcxa276-pac/src/flexio0/trgstat.rs b/mcxa276-pac/src/flexio0/trgstat.rs new file mode 100644 index 000000000..77aaa7022 --- /dev/null +++ b/mcxa276-pac/src/flexio0/trgstat.rs @@ -0,0 +1,92 @@ +#[doc = "Register `TRGSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `TRGSTAT` writer"] +pub type W = crate::W; +#[doc = "External Trigger Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Etsf { + #[doc = "0: Clear"] + Clr = 0, + #[doc = "1: Set"] + Set = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Etsf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Etsf { + type Ux = u8; +} +impl crate::IsEnum for Etsf {} +#[doc = "Field `ETSF` reader - External Trigger Status Flag"] +pub type EtsfR = crate::FieldReader; +impl EtsfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Etsf::Clr), + 1 => Some(Etsf::Set), + _ => None, + } + } + #[doc = "Clear"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + *self == Etsf::Clr + } + #[doc = "Set"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == Etsf::Set + } +} +#[doc = "Field `ETSF` writer - External Trigger Status Flag"] +pub type EtsfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Etsf>; +impl<'a, REG> EtsfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Clear"] + #[inline(always)] + pub fn clr(self) -> &'a mut crate::W { + self.variant(Etsf::Clr) + } + #[doc = "Set"] + #[inline(always)] + pub fn set_(self) -> &'a mut crate::W { + self.variant(Etsf::Set) + } +} +impl R { + #[doc = "Bits 0:3 - External Trigger Status Flag"] + #[inline(always)] + pub fn etsf(&self) -> EtsfR { + EtsfR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - External Trigger Status Flag"] + #[inline(always)] + pub fn etsf(&mut self) -> EtsfW { + EtsfW::new(self, 0) + } +} +#[doc = "Trigger Status\n\nYou can [`read`](crate::Reg::read) this register and get [`trgstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trgstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TrgstatSpec; +impl crate::RegisterSpec for TrgstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`trgstat::R`](R) reader structure"] +impl crate::Readable for TrgstatSpec {} +#[doc = "`write(|w| ..)` method takes [`trgstat::W`](W) writer structure"] +impl crate::Writable for TrgstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets TRGSTAT to value 0"] +impl crate::Resettable for TrgstatSpec {} diff --git a/mcxa276-pac/src/flexio0/trigien.rs b/mcxa276-pac/src/flexio0/trigien.rs new file mode 100644 index 000000000..473c50d5a --- /dev/null +++ b/mcxa276-pac/src/flexio0/trigien.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TRIGIEN` reader"] +pub type R = crate::R; +#[doc = "Register `TRIGIEN` writer"] +pub type W = crate::W; +#[doc = "Field `TRIE` reader - External Trigger Interrupt Enable"] +pub type TrieR = crate::FieldReader; +#[doc = "Field `TRIE` writer - External Trigger Interrupt Enable"] +pub type TrieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - External Trigger Interrupt Enable"] + #[inline(always)] + pub fn trie(&self) -> TrieR { + TrieR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - External Trigger Interrupt Enable"] + #[inline(always)] + pub fn trie(&mut self) -> TrieW { + TrieW::new(self, 0) + } +} +#[doc = "External Trigger Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`trigien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TrigienSpec; +impl crate::RegisterSpec for TrigienSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`trigien::R`](R) reader structure"] +impl crate::Readable for TrigienSpec {} +#[doc = "`write(|w| ..)` method takes [`trigien::W`](W) writer structure"] +impl crate::Writable for TrigienSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TRIGIEN to value 0"] +impl crate::Resettable for TrigienSpec {} diff --git a/mcxa276-pac/src/flexio0/verid.rs b/mcxa276-pac/src/flexio0/verid.rs new file mode 100644 index 000000000..0a1eda3e8 --- /dev/null +++ b/mcxa276-pac/src/flexio0/verid.rs @@ -0,0 +1,92 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Standard features implemented"] + Standard = 0, + #[doc = "1: State, logic, and parallel modes supported"] + StateLogicParallel = 1, + #[doc = "2: Pin control registers supported"] + Pinctrl = 2, + #[doc = "3: State, logic, and parallel modes, plus pin control registers supported"] + StateLogicParallelPinctrl = 3, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Standard), + 1 => Some(Feature::StateLogicParallel), + 2 => Some(Feature::Pinctrl), + 3 => Some(Feature::StateLogicParallelPinctrl), + _ => None, + } + } + #[doc = "Standard features implemented"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == Feature::Standard + } + #[doc = "State, logic, and parallel modes supported"] + #[inline(always)] + pub fn is_state_logic_parallel(&self) -> bool { + *self == Feature::StateLogicParallel + } + #[doc = "Pin control registers supported"] + #[inline(always)] + pub fn is_pinctrl(&self) -> bool { + *self == Feature::Pinctrl + } + #[doc = "State, logic, and parallel modes, plus pin control registers supported"] + #[inline(always)] + pub fn is_state_logic_parallel_pinctrl(&self) -> bool { + *self == Feature::StateLogicParallelPinctrl + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0201_0003"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0201_0003; +} diff --git a/mcxa276-pac/src/flexpwm0.rs b/mcxa276-pac/src/flexpwm0.rs new file mode 100644 index 000000000..dd714afa1 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0.rs @@ -0,0 +1,1303 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + sm0cnt: Sm0cnt, + sm0init: Sm0init, + sm0ctrl2: Sm0ctrl2, + sm0ctrl: Sm0ctrl, + _reserved4: [u8; 0x02], + sm0val0: Sm0val0, + _reserved5: [u8; 0x02], + sm0val1: Sm0val1, + _reserved6: [u8; 0x02], + sm0val2: Sm0val2, + _reserved7: [u8; 0x02], + sm0val3: Sm0val3, + _reserved8: [u8; 0x02], + sm0val4: Sm0val4, + _reserved9: [u8; 0x02], + sm0val5: Sm0val5, + _reserved10: [u8; 0x02], + sm0octrl: Sm0octrl, + sm0sts: Sm0sts, + sm0inten: Sm0inten, + sm0dmaen: Sm0dmaen, + sm0tctrl: Sm0tctrl, + sm0dismap0: Sm0dismap0, + _reserved16: [u8; 0x02], + sm0dtcnt0: Sm0dtcnt0, + sm0dtcnt1: Sm0dtcnt1, + _reserved18: [u8; 0x08], + sm0captctrlx: Sm0captctrlx, + sm0captcompx: Sm0captcompx, + sm0cval0: Sm0cval0, + sm0cval0cyc: Sm0cval0cyc, + sm0cval1: Sm0cval1, + sm0cval1cyc: Sm0cval1cyc, + _reserved24: [u8; 0x16], + sm0captfiltx: Sm0captfiltx, + sm1cnt: Sm1cnt, + sm1init: Sm1init, + sm1ctrl2: Sm1ctrl2, + sm1ctrl: Sm1ctrl, + _reserved29: [u8; 0x02], + sm1val0: Sm1val0, + _reserved30: [u8; 0x02], + sm1val1: Sm1val1, + _reserved31: [u8; 0x02], + sm1val2: Sm1val2, + _reserved32: [u8; 0x02], + sm1val3: Sm1val3, + _reserved33: [u8; 0x02], + sm1val4: Sm1val4, + _reserved34: [u8; 0x02], + sm1val5: Sm1val5, + _reserved35: [u8; 0x02], + sm1octrl: Sm1octrl, + sm1sts: Sm1sts, + sm1inten: Sm1inten, + sm1dmaen: Sm1dmaen, + sm1tctrl: Sm1tctrl, + sm1dismap0: Sm1dismap0, + _reserved41: [u8; 0x02], + sm1dtcnt0: Sm1dtcnt0, + sm1dtcnt1: Sm1dtcnt1, + _reserved43: [u8; 0x08], + sm1captctrlx: Sm1captctrlx, + sm1captcompx: Sm1captcompx, + sm1cval0: Sm1cval0, + sm1cval0cyc: Sm1cval0cyc, + sm1cval1: Sm1cval1, + sm1cval1cyc: Sm1cval1cyc, + _reserved49: [u8; 0x10], + sm1phasedly: Sm1phasedly, + _reserved50: [u8; 0x04], + sm1captfiltx: Sm1captfiltx, + sm2cnt: Sm2cnt, + sm2init: Sm2init, + sm2ctrl2: Sm2ctrl2, + sm2ctrl: Sm2ctrl, + _reserved55: [u8; 0x02], + sm2val0: Sm2val0, + _reserved56: [u8; 0x02], + sm2val1: Sm2val1, + _reserved57: [u8; 0x02], + sm2val2: Sm2val2, + _reserved58: [u8; 0x02], + sm2val3: Sm2val3, + _reserved59: [u8; 0x02], + sm2val4: Sm2val4, + _reserved60: [u8; 0x02], + sm2val5: Sm2val5, + _reserved61: [u8; 0x02], + sm2octrl: Sm2octrl, + sm2sts: Sm2sts, + sm2inten: Sm2inten, + sm2dmaen: Sm2dmaen, + sm2tctrl: Sm2tctrl, + sm2dismap0: Sm2dismap0, + _reserved67: [u8; 0x02], + sm2dtcnt0: Sm2dtcnt0, + sm2dtcnt1: Sm2dtcnt1, + _reserved69: [u8; 0x08], + sm2captctrlx: Sm2captctrlx, + sm2captcompx: Sm2captcompx, + sm2cval0: Sm2cval0, + sm2cval0cyc: Sm2cval0cyc, + sm2cval1: Sm2cval1, + sm2cval1cyc: Sm2cval1cyc, + _reserved75: [u8; 0x10], + sm2phasedly: Sm2phasedly, + _reserved76: [u8; 0x04], + sm2captfiltx: Sm2captfiltx, + sm3cnt: Sm3cnt, + sm3init: Sm3init, + sm3ctrl2: Sm3ctrl2, + sm3ctrl: Sm3ctrl, + _reserved81: [u8; 0x02], + sm3val0: Sm3val0, + _reserved82: [u8; 0x02], + sm3val1: Sm3val1, + _reserved83: [u8; 0x02], + sm3val2: Sm3val2, + _reserved84: [u8; 0x02], + sm3val3: Sm3val3, + _reserved85: [u8; 0x02], + sm3val4: Sm3val4, + _reserved86: [u8; 0x02], + sm3val5: Sm3val5, + _reserved87: [u8; 0x02], + sm3octrl: Sm3octrl, + sm3sts: Sm3sts, + sm3inten: Sm3inten, + sm3dmaen: Sm3dmaen, + sm3tctrl: Sm3tctrl, + sm3dismap0: Sm3dismap0, + _reserved93: [u8; 0x02], + sm3dtcnt0: Sm3dtcnt0, + sm3dtcnt1: Sm3dtcnt1, + _reserved95: [u8; 0x08], + sm3captctrlx: Sm3captctrlx, + sm3captcompx: Sm3captcompx, + sm3cval0: Sm3cval0, + sm3cval0cyc: Sm3cval0cyc, + sm3cval1: Sm3cval1, + sm3cval1cyc: Sm3cval1cyc, + _reserved101: [u8; 0x10], + sm3phasedly: Sm3phasedly, + _reserved102: [u8; 0x04], + sm3captfiltx: Sm3captfiltx, + outen: Outen, + mask: Mask, + swcout: Swcout, + dtsrcsel: Dtsrcsel, + mctrl: Mctrl, + mctrl2: Mctrl2, + fctrl0: Fctrl0, + fsts0: Fsts0, + ffilt0: Ffilt0, + ftst0: Ftst0, + fctrl20: Fctrl20, +} +impl RegisterBlock { + #[doc = "0x00 - Counter Register"] + #[inline(always)] + pub const fn sm0cnt(&self) -> &Sm0cnt { + &self.sm0cnt + } + #[doc = "0x02 - Initial Count Register"] + #[inline(always)] + pub const fn sm0init(&self) -> &Sm0init { + &self.sm0init + } + #[doc = "0x04 - Control 2 Register"] + #[inline(always)] + pub const fn sm0ctrl2(&self) -> &Sm0ctrl2 { + &self.sm0ctrl2 + } + #[doc = "0x06 - Control Register"] + #[inline(always)] + pub const fn sm0ctrl(&self) -> &Sm0ctrl { + &self.sm0ctrl + } + #[doc = "0x0a - Value Register 0"] + #[inline(always)] + pub const fn sm0val0(&self) -> &Sm0val0 { + &self.sm0val0 + } + #[doc = "0x0e - Value Register 1"] + #[inline(always)] + pub const fn sm0val1(&self) -> &Sm0val1 { + &self.sm0val1 + } + #[doc = "0x12 - Value Register 2"] + #[inline(always)] + pub const fn sm0val2(&self) -> &Sm0val2 { + &self.sm0val2 + } + #[doc = "0x16 - Value Register 3"] + #[inline(always)] + pub const fn sm0val3(&self) -> &Sm0val3 { + &self.sm0val3 + } + #[doc = "0x1a - Value Register 4"] + #[inline(always)] + pub const fn sm0val4(&self) -> &Sm0val4 { + &self.sm0val4 + } + #[doc = "0x1e - Value Register 5"] + #[inline(always)] + pub const fn sm0val5(&self) -> &Sm0val5 { + &self.sm0val5 + } + #[doc = "0x22 - Output Control Register"] + #[inline(always)] + pub const fn sm0octrl(&self) -> &Sm0octrl { + &self.sm0octrl + } + #[doc = "0x24 - Status Register"] + #[inline(always)] + pub const fn sm0sts(&self) -> &Sm0sts { + &self.sm0sts + } + #[doc = "0x26 - Interrupt Enable Register"] + #[inline(always)] + pub const fn sm0inten(&self) -> &Sm0inten { + &self.sm0inten + } + #[doc = "0x28 - DMA Enable Register"] + #[inline(always)] + pub const fn sm0dmaen(&self) -> &Sm0dmaen { + &self.sm0dmaen + } + #[doc = "0x2a - Output Trigger Control Register"] + #[inline(always)] + pub const fn sm0tctrl(&self) -> &Sm0tctrl { + &self.sm0tctrl + } + #[doc = "0x2c - Fault Disable Mapping Register 0"] + #[inline(always)] + pub const fn sm0dismap0(&self) -> &Sm0dismap0 { + &self.sm0dismap0 + } + #[doc = "0x30 - Deadtime Count Register 0"] + #[inline(always)] + pub const fn sm0dtcnt0(&self) -> &Sm0dtcnt0 { + &self.sm0dtcnt0 + } + #[doc = "0x32 - Deadtime Count Register 1"] + #[inline(always)] + pub const fn sm0dtcnt1(&self) -> &Sm0dtcnt1 { + &self.sm0dtcnt1 + } + #[doc = "0x3c - Capture Control X Register"] + #[inline(always)] + pub const fn sm0captctrlx(&self) -> &Sm0captctrlx { + &self.sm0captctrlx + } + #[doc = "0x3e - Capture Compare X Register"] + #[inline(always)] + pub const fn sm0captcompx(&self) -> &Sm0captcompx { + &self.sm0captcompx + } + #[doc = "0x40 - Capture Value 0 Register"] + #[inline(always)] + pub const fn sm0cval0(&self) -> &Sm0cval0 { + &self.sm0cval0 + } + #[doc = "0x42 - Capture Value 0 Cycle Register"] + #[inline(always)] + pub const fn sm0cval0cyc(&self) -> &Sm0cval0cyc { + &self.sm0cval0cyc + } + #[doc = "0x44 - Capture Value 1 Register"] + #[inline(always)] + pub const fn sm0cval1(&self) -> &Sm0cval1 { + &self.sm0cval1 + } + #[doc = "0x46 - Capture Value 1 Cycle Register"] + #[inline(always)] + pub const fn sm0cval1cyc(&self) -> &Sm0cval1cyc { + &self.sm0cval1cyc + } + #[doc = "0x5e - Capture PWM_X Input Filter Register"] + #[inline(always)] + pub const fn sm0captfiltx(&self) -> &Sm0captfiltx { + &self.sm0captfiltx + } + #[doc = "0x60 - Counter Register"] + #[inline(always)] + pub const fn sm1cnt(&self) -> &Sm1cnt { + &self.sm1cnt + } + #[doc = "0x62 - Initial Count Register"] + #[inline(always)] + pub const fn sm1init(&self) -> &Sm1init { + &self.sm1init + } + #[doc = "0x64 - Control 2 Register"] + #[inline(always)] + pub const fn sm1ctrl2(&self) -> &Sm1ctrl2 { + &self.sm1ctrl2 + } + #[doc = "0x66 - Control Register"] + #[inline(always)] + pub const fn sm1ctrl(&self) -> &Sm1ctrl { + &self.sm1ctrl + } + #[doc = "0x6a - Value Register 0"] + #[inline(always)] + pub const fn sm1val0(&self) -> &Sm1val0 { + &self.sm1val0 + } + #[doc = "0x6e - Value Register 1"] + #[inline(always)] + pub const fn sm1val1(&self) -> &Sm1val1 { + &self.sm1val1 + } + #[doc = "0x72 - Value Register 2"] + #[inline(always)] + pub const fn sm1val2(&self) -> &Sm1val2 { + &self.sm1val2 + } + #[doc = "0x76 - Value Register 3"] + #[inline(always)] + pub const fn sm1val3(&self) -> &Sm1val3 { + &self.sm1val3 + } + #[doc = "0x7a - Value Register 4"] + #[inline(always)] + pub const fn sm1val4(&self) -> &Sm1val4 { + &self.sm1val4 + } + #[doc = "0x7e - Value Register 5"] + #[inline(always)] + pub const fn sm1val5(&self) -> &Sm1val5 { + &self.sm1val5 + } + #[doc = "0x82 - Output Control Register"] + #[inline(always)] + pub const fn sm1octrl(&self) -> &Sm1octrl { + &self.sm1octrl + } + #[doc = "0x84 - Status Register"] + #[inline(always)] + pub const fn sm1sts(&self) -> &Sm1sts { + &self.sm1sts + } + #[doc = "0x86 - Interrupt Enable Register"] + #[inline(always)] + pub const fn sm1inten(&self) -> &Sm1inten { + &self.sm1inten + } + #[doc = "0x88 - DMA Enable Register"] + #[inline(always)] + pub const fn sm1dmaen(&self) -> &Sm1dmaen { + &self.sm1dmaen + } + #[doc = "0x8a - Output Trigger Control Register"] + #[inline(always)] + pub const fn sm1tctrl(&self) -> &Sm1tctrl { + &self.sm1tctrl + } + #[doc = "0x8c - Fault Disable Mapping Register 0"] + #[inline(always)] + pub const fn sm1dismap0(&self) -> &Sm1dismap0 { + &self.sm1dismap0 + } + #[doc = "0x90 - Deadtime Count Register 0"] + #[inline(always)] + pub const fn sm1dtcnt0(&self) -> &Sm1dtcnt0 { + &self.sm1dtcnt0 + } + #[doc = "0x92 - Deadtime Count Register 1"] + #[inline(always)] + pub const fn sm1dtcnt1(&self) -> &Sm1dtcnt1 { + &self.sm1dtcnt1 + } + #[doc = "0x9c - Capture Control X Register"] + #[inline(always)] + pub const fn sm1captctrlx(&self) -> &Sm1captctrlx { + &self.sm1captctrlx + } + #[doc = "0x9e - Capture Compare X Register"] + #[inline(always)] + pub const fn sm1captcompx(&self) -> &Sm1captcompx { + &self.sm1captcompx + } + #[doc = "0xa0 - Capture Value 0 Register"] + #[inline(always)] + pub const fn sm1cval0(&self) -> &Sm1cval0 { + &self.sm1cval0 + } + #[doc = "0xa2 - Capture Value 0 Cycle Register"] + #[inline(always)] + pub const fn sm1cval0cyc(&self) -> &Sm1cval0cyc { + &self.sm1cval0cyc + } + #[doc = "0xa4 - Capture Value 1 Register"] + #[inline(always)] + pub const fn sm1cval1(&self) -> &Sm1cval1 { + &self.sm1cval1 + } + #[doc = "0xa6 - Capture Value 1 Cycle Register"] + #[inline(always)] + pub const fn sm1cval1cyc(&self) -> &Sm1cval1cyc { + &self.sm1cval1cyc + } + #[doc = "0xb8 - Phase Delay Register"] + #[inline(always)] + pub const fn sm1phasedly(&self) -> &Sm1phasedly { + &self.sm1phasedly + } + #[doc = "0xbe - Capture PWM_X Input Filter Register"] + #[inline(always)] + pub const fn sm1captfiltx(&self) -> &Sm1captfiltx { + &self.sm1captfiltx + } + #[doc = "0xc0 - Counter Register"] + #[inline(always)] + pub const fn sm2cnt(&self) -> &Sm2cnt { + &self.sm2cnt + } + #[doc = "0xc2 - Initial Count Register"] + #[inline(always)] + pub const fn sm2init(&self) -> &Sm2init { + &self.sm2init + } + #[doc = "0xc4 - Control 2 Register"] + #[inline(always)] + pub const fn sm2ctrl2(&self) -> &Sm2ctrl2 { + &self.sm2ctrl2 + } + #[doc = "0xc6 - Control Register"] + #[inline(always)] + pub const fn sm2ctrl(&self) -> &Sm2ctrl { + &self.sm2ctrl + } + #[doc = "0xca - Value Register 0"] + #[inline(always)] + pub const fn sm2val0(&self) -> &Sm2val0 { + &self.sm2val0 + } + #[doc = "0xce - Value Register 1"] + #[inline(always)] + pub const fn sm2val1(&self) -> &Sm2val1 { + &self.sm2val1 + } + #[doc = "0xd2 - Value Register 2"] + #[inline(always)] + pub const fn sm2val2(&self) -> &Sm2val2 { + &self.sm2val2 + } + #[doc = "0xd6 - Value Register 3"] + #[inline(always)] + pub const fn sm2val3(&self) -> &Sm2val3 { + &self.sm2val3 + } + #[doc = "0xda - Value Register 4"] + #[inline(always)] + pub const fn sm2val4(&self) -> &Sm2val4 { + &self.sm2val4 + } + #[doc = "0xde - Value Register 5"] + #[inline(always)] + pub const fn sm2val5(&self) -> &Sm2val5 { + &self.sm2val5 + } + #[doc = "0xe2 - Output Control Register"] + #[inline(always)] + pub const fn sm2octrl(&self) -> &Sm2octrl { + &self.sm2octrl + } + #[doc = "0xe4 - Status Register"] + #[inline(always)] + pub const fn sm2sts(&self) -> &Sm2sts { + &self.sm2sts + } + #[doc = "0xe6 - Interrupt Enable Register"] + #[inline(always)] + pub const fn sm2inten(&self) -> &Sm2inten { + &self.sm2inten + } + #[doc = "0xe8 - DMA Enable Register"] + #[inline(always)] + pub const fn sm2dmaen(&self) -> &Sm2dmaen { + &self.sm2dmaen + } + #[doc = "0xea - Output Trigger Control Register"] + #[inline(always)] + pub const fn sm2tctrl(&self) -> &Sm2tctrl { + &self.sm2tctrl + } + #[doc = "0xec - Fault Disable Mapping Register 0"] + #[inline(always)] + pub const fn sm2dismap0(&self) -> &Sm2dismap0 { + &self.sm2dismap0 + } + #[doc = "0xf0 - Deadtime Count Register 0"] + #[inline(always)] + pub const fn sm2dtcnt0(&self) -> &Sm2dtcnt0 { + &self.sm2dtcnt0 + } + #[doc = "0xf2 - Deadtime Count Register 1"] + #[inline(always)] + pub const fn sm2dtcnt1(&self) -> &Sm2dtcnt1 { + &self.sm2dtcnt1 + } + #[doc = "0xfc - Capture Control X Register"] + #[inline(always)] + pub const fn sm2captctrlx(&self) -> &Sm2captctrlx { + &self.sm2captctrlx + } + #[doc = "0xfe - Capture Compare X Register"] + #[inline(always)] + pub const fn sm2captcompx(&self) -> &Sm2captcompx { + &self.sm2captcompx + } + #[doc = "0x100 - Capture Value 0 Register"] + #[inline(always)] + pub const fn sm2cval0(&self) -> &Sm2cval0 { + &self.sm2cval0 + } + #[doc = "0x102 - Capture Value 0 Cycle Register"] + #[inline(always)] + pub const fn sm2cval0cyc(&self) -> &Sm2cval0cyc { + &self.sm2cval0cyc + } + #[doc = "0x104 - Capture Value 1 Register"] + #[inline(always)] + pub const fn sm2cval1(&self) -> &Sm2cval1 { + &self.sm2cval1 + } + #[doc = "0x106 - Capture Value 1 Cycle Register"] + #[inline(always)] + pub const fn sm2cval1cyc(&self) -> &Sm2cval1cyc { + &self.sm2cval1cyc + } + #[doc = "0x118 - Phase Delay Register"] + #[inline(always)] + pub const fn sm2phasedly(&self) -> &Sm2phasedly { + &self.sm2phasedly + } + #[doc = "0x11e - Capture PWM_X Input Filter Register"] + #[inline(always)] + pub const fn sm2captfiltx(&self) -> &Sm2captfiltx { + &self.sm2captfiltx + } + #[doc = "0x120 - Counter Register"] + #[inline(always)] + pub const fn sm3cnt(&self) -> &Sm3cnt { + &self.sm3cnt + } + #[doc = "0x122 - Initial Count Register"] + #[inline(always)] + pub const fn sm3init(&self) -> &Sm3init { + &self.sm3init + } + #[doc = "0x124 - Control 2 Register"] + #[inline(always)] + pub const fn sm3ctrl2(&self) -> &Sm3ctrl2 { + &self.sm3ctrl2 + } + #[doc = "0x126 - Control Register"] + #[inline(always)] + pub const fn sm3ctrl(&self) -> &Sm3ctrl { + &self.sm3ctrl + } + #[doc = "0x12a - Value Register 0"] + #[inline(always)] + pub const fn sm3val0(&self) -> &Sm3val0 { + &self.sm3val0 + } + #[doc = "0x12e - Value Register 1"] + #[inline(always)] + pub const fn sm3val1(&self) -> &Sm3val1 { + &self.sm3val1 + } + #[doc = "0x132 - Value Register 2"] + #[inline(always)] + pub const fn sm3val2(&self) -> &Sm3val2 { + &self.sm3val2 + } + #[doc = "0x136 - Value Register 3"] + #[inline(always)] + pub const fn sm3val3(&self) -> &Sm3val3 { + &self.sm3val3 + } + #[doc = "0x13a - Value Register 4"] + #[inline(always)] + pub const fn sm3val4(&self) -> &Sm3val4 { + &self.sm3val4 + } + #[doc = "0x13e - Value Register 5"] + #[inline(always)] + pub const fn sm3val5(&self) -> &Sm3val5 { + &self.sm3val5 + } + #[doc = "0x142 - Output Control Register"] + #[inline(always)] + pub const fn sm3octrl(&self) -> &Sm3octrl { + &self.sm3octrl + } + #[doc = "0x144 - Status Register"] + #[inline(always)] + pub const fn sm3sts(&self) -> &Sm3sts { + &self.sm3sts + } + #[doc = "0x146 - Interrupt Enable Register"] + #[inline(always)] + pub const fn sm3inten(&self) -> &Sm3inten { + &self.sm3inten + } + #[doc = "0x148 - DMA Enable Register"] + #[inline(always)] + pub const fn sm3dmaen(&self) -> &Sm3dmaen { + &self.sm3dmaen + } + #[doc = "0x14a - Output Trigger Control Register"] + #[inline(always)] + pub const fn sm3tctrl(&self) -> &Sm3tctrl { + &self.sm3tctrl + } + #[doc = "0x14c - Fault Disable Mapping Register 0"] + #[inline(always)] + pub const fn sm3dismap0(&self) -> &Sm3dismap0 { + &self.sm3dismap0 + } + #[doc = "0x150 - Deadtime Count Register 0"] + #[inline(always)] + pub const fn sm3dtcnt0(&self) -> &Sm3dtcnt0 { + &self.sm3dtcnt0 + } + #[doc = "0x152 - Deadtime Count Register 1"] + #[inline(always)] + pub const fn sm3dtcnt1(&self) -> &Sm3dtcnt1 { + &self.sm3dtcnt1 + } + #[doc = "0x15c - Capture Control X Register"] + #[inline(always)] + pub const fn sm3captctrlx(&self) -> &Sm3captctrlx { + &self.sm3captctrlx + } + #[doc = "0x15e - Capture Compare X Register"] + #[inline(always)] + pub const fn sm3captcompx(&self) -> &Sm3captcompx { + &self.sm3captcompx + } + #[doc = "0x160 - Capture Value 0 Register"] + #[inline(always)] + pub const fn sm3cval0(&self) -> &Sm3cval0 { + &self.sm3cval0 + } + #[doc = "0x162 - Capture Value 0 Cycle Register"] + #[inline(always)] + pub const fn sm3cval0cyc(&self) -> &Sm3cval0cyc { + &self.sm3cval0cyc + } + #[doc = "0x164 - Capture Value 1 Register"] + #[inline(always)] + pub const fn sm3cval1(&self) -> &Sm3cval1 { + &self.sm3cval1 + } + #[doc = "0x166 - Capture Value 1 Cycle Register"] + #[inline(always)] + pub const fn sm3cval1cyc(&self) -> &Sm3cval1cyc { + &self.sm3cval1cyc + } + #[doc = "0x178 - Phase Delay Register"] + #[inline(always)] + pub const fn sm3phasedly(&self) -> &Sm3phasedly { + &self.sm3phasedly + } + #[doc = "0x17e - Capture PWM_X Input Filter Register"] + #[inline(always)] + pub const fn sm3captfiltx(&self) -> &Sm3captfiltx { + &self.sm3captfiltx + } + #[doc = "0x180 - Output Enable Register"] + #[inline(always)] + pub const fn outen(&self) -> &Outen { + &self.outen + } + #[doc = "0x182 - Mask Register"] + #[inline(always)] + pub const fn mask(&self) -> &Mask { + &self.mask + } + #[doc = "0x184 - Software Controlled Output Register"] + #[inline(always)] + pub const fn swcout(&self) -> &Swcout { + &self.swcout + } + #[doc = "0x186 - PWM Source Select Register"] + #[inline(always)] + pub const fn dtsrcsel(&self) -> &Dtsrcsel { + &self.dtsrcsel + } + #[doc = "0x188 - Master Control Register"] + #[inline(always)] + pub const fn mctrl(&self) -> &Mctrl { + &self.mctrl + } + #[doc = "0x18a - Master Control 2 Register"] + #[inline(always)] + pub const fn mctrl2(&self) -> &Mctrl2 { + &self.mctrl2 + } + #[doc = "0x18c - Fault Control Register"] + #[inline(always)] + pub const fn fctrl0(&self) -> &Fctrl0 { + &self.fctrl0 + } + #[doc = "0x18e - Fault Status Register"] + #[inline(always)] + pub const fn fsts0(&self) -> &Fsts0 { + &self.fsts0 + } + #[doc = "0x190 - Fault Filter Register"] + #[inline(always)] + pub const fn ffilt0(&self) -> &Ffilt0 { + &self.ffilt0 + } + #[doc = "0x192 - Fault Test Register"] + #[inline(always)] + pub const fn ftst0(&self) -> &Ftst0 { + &self.ftst0 + } + #[doc = "0x194 - Fault Control 2 Register"] + #[inline(always)] + pub const fn fctrl20(&self) -> &Fctrl20 { + &self.fctrl20 + } +} +#[doc = "SM0CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cnt`] module"] +#[doc(alias = "SM0CNT")] +pub type Sm0cnt = crate::Reg; +#[doc = "Counter Register"] +pub mod sm0cnt; +#[doc = "SM0INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0init`] module"] +#[doc(alias = "SM0INIT")] +pub type Sm0init = crate::Reg; +#[doc = "Initial Count Register"] +pub mod sm0init; +#[doc = "SM0CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0ctrl2`] module"] +#[doc(alias = "SM0CTRL2")] +pub type Sm0ctrl2 = crate::Reg; +#[doc = "Control 2 Register"] +pub mod sm0ctrl2; +#[doc = "SM0CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0ctrl`] module"] +#[doc(alias = "SM0CTRL")] +pub type Sm0ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod sm0ctrl; +#[doc = "SM0VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val0`] module"] +#[doc(alias = "SM0VAL0")] +pub type Sm0val0 = crate::Reg; +#[doc = "Value Register 0"] +pub mod sm0val0; +#[doc = "SM0VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val1`] module"] +#[doc(alias = "SM0VAL1")] +pub type Sm0val1 = crate::Reg; +#[doc = "Value Register 1"] +pub mod sm0val1; +#[doc = "SM0VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val2`] module"] +#[doc(alias = "SM0VAL2")] +pub type Sm0val2 = crate::Reg; +#[doc = "Value Register 2"] +pub mod sm0val2; +#[doc = "SM0VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val3`] module"] +#[doc(alias = "SM0VAL3")] +pub type Sm0val3 = crate::Reg; +#[doc = "Value Register 3"] +pub mod sm0val3; +#[doc = "SM0VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val4`] module"] +#[doc(alias = "SM0VAL4")] +pub type Sm0val4 = crate::Reg; +#[doc = "Value Register 4"] +pub mod sm0val4; +#[doc = "SM0VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val5`] module"] +#[doc(alias = "SM0VAL5")] +pub type Sm0val5 = crate::Reg; +#[doc = "Value Register 5"] +pub mod sm0val5; +#[doc = "SM0OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0octrl`] module"] +#[doc(alias = "SM0OCTRL")] +pub type Sm0octrl = crate::Reg; +#[doc = "Output Control Register"] +pub mod sm0octrl; +#[doc = "SM0STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0sts`] module"] +#[doc(alias = "SM0STS")] +pub type Sm0sts = crate::Reg; +#[doc = "Status Register"] +pub mod sm0sts; +#[doc = "SM0INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0inten`] module"] +#[doc(alias = "SM0INTEN")] +pub type Sm0inten = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod sm0inten; +#[doc = "SM0DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dmaen`] module"] +#[doc(alias = "SM0DMAEN")] +pub type Sm0dmaen = crate::Reg; +#[doc = "DMA Enable Register"] +pub mod sm0dmaen; +#[doc = "SM0TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0tctrl`] module"] +#[doc(alias = "SM0TCTRL")] +pub type Sm0tctrl = crate::Reg; +#[doc = "Output Trigger Control Register"] +pub mod sm0tctrl; +#[doc = "SM0DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dismap0`] module"] +#[doc(alias = "SM0DISMAP0")] +pub type Sm0dismap0 = crate::Reg; +#[doc = "Fault Disable Mapping Register 0"] +pub mod sm0dismap0; +#[doc = "SM0DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dtcnt0`] module"] +#[doc(alias = "SM0DTCNT0")] +pub type Sm0dtcnt0 = crate::Reg; +#[doc = "Deadtime Count Register 0"] +pub mod sm0dtcnt0; +#[doc = "SM0DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dtcnt1`] module"] +#[doc(alias = "SM0DTCNT1")] +pub type Sm0dtcnt1 = crate::Reg; +#[doc = "Deadtime Count Register 1"] +pub mod sm0dtcnt1; +#[doc = "SM0CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0captctrlx`] module"] +#[doc(alias = "SM0CAPTCTRLX")] +pub type Sm0captctrlx = crate::Reg; +#[doc = "Capture Control X Register"] +pub mod sm0captctrlx; +#[doc = "SM0CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0captcompx`] module"] +#[doc(alias = "SM0CAPTCOMPX")] +pub type Sm0captcompx = crate::Reg; +#[doc = "Capture Compare X Register"] +pub mod sm0captcompx; +#[doc = "SM0CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval0`] module"] +#[doc(alias = "SM0CVAL0")] +pub type Sm0cval0 = crate::Reg; +#[doc = "Capture Value 0 Register"] +pub mod sm0cval0; +#[doc = "SM0CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval0cyc`] module"] +#[doc(alias = "SM0CVAL0CYC")] +pub type Sm0cval0cyc = crate::Reg; +#[doc = "Capture Value 0 Cycle Register"] +pub mod sm0cval0cyc; +#[doc = "SM0CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval1`] module"] +#[doc(alias = "SM0CVAL1")] +pub type Sm0cval1 = crate::Reg; +#[doc = "Capture Value 1 Register"] +pub mod sm0cval1; +#[doc = "SM0CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval1cyc`] module"] +#[doc(alias = "SM0CVAL1CYC")] +pub type Sm0cval1cyc = crate::Reg; +#[doc = "Capture Value 1 Cycle Register"] +pub mod sm0cval1cyc; +#[doc = "SM0CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0captfiltx`] module"] +#[doc(alias = "SM0CAPTFILTX")] +pub type Sm0captfiltx = crate::Reg; +#[doc = "Capture PWM_X Input Filter Register"] +pub mod sm0captfiltx; +#[doc = "SM1CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cnt`] module"] +#[doc(alias = "SM1CNT")] +pub type Sm1cnt = crate::Reg; +#[doc = "Counter Register"] +pub mod sm1cnt; +#[doc = "SM1INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1init`] module"] +#[doc(alias = "SM1INIT")] +pub type Sm1init = crate::Reg; +#[doc = "Initial Count Register"] +pub mod sm1init; +#[doc = "SM1CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1ctrl2`] module"] +#[doc(alias = "SM1CTRL2")] +pub type Sm1ctrl2 = crate::Reg; +#[doc = "Control 2 Register"] +pub mod sm1ctrl2; +#[doc = "SM1CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1ctrl`] module"] +#[doc(alias = "SM1CTRL")] +pub type Sm1ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod sm1ctrl; +#[doc = "SM1VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val0`] module"] +#[doc(alias = "SM1VAL0")] +pub type Sm1val0 = crate::Reg; +#[doc = "Value Register 0"] +pub mod sm1val0; +#[doc = "SM1VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val1`] module"] +#[doc(alias = "SM1VAL1")] +pub type Sm1val1 = crate::Reg; +#[doc = "Value Register 1"] +pub mod sm1val1; +#[doc = "SM1VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val2`] module"] +#[doc(alias = "SM1VAL2")] +pub type Sm1val2 = crate::Reg; +#[doc = "Value Register 2"] +pub mod sm1val2; +#[doc = "SM1VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val3`] module"] +#[doc(alias = "SM1VAL3")] +pub type Sm1val3 = crate::Reg; +#[doc = "Value Register 3"] +pub mod sm1val3; +#[doc = "SM1VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val4`] module"] +#[doc(alias = "SM1VAL4")] +pub type Sm1val4 = crate::Reg; +#[doc = "Value Register 4"] +pub mod sm1val4; +#[doc = "SM1VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val5`] module"] +#[doc(alias = "SM1VAL5")] +pub type Sm1val5 = crate::Reg; +#[doc = "Value Register 5"] +pub mod sm1val5; +#[doc = "SM1OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1octrl`] module"] +#[doc(alias = "SM1OCTRL")] +pub type Sm1octrl = crate::Reg; +#[doc = "Output Control Register"] +pub mod sm1octrl; +#[doc = "SM1STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1sts`] module"] +#[doc(alias = "SM1STS")] +pub type Sm1sts = crate::Reg; +#[doc = "Status Register"] +pub mod sm1sts; +#[doc = "SM1INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1inten`] module"] +#[doc(alias = "SM1INTEN")] +pub type Sm1inten = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod sm1inten; +#[doc = "SM1DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dmaen`] module"] +#[doc(alias = "SM1DMAEN")] +pub type Sm1dmaen = crate::Reg; +#[doc = "DMA Enable Register"] +pub mod sm1dmaen; +#[doc = "SM1TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1tctrl`] module"] +#[doc(alias = "SM1TCTRL")] +pub type Sm1tctrl = crate::Reg; +#[doc = "Output Trigger Control Register"] +pub mod sm1tctrl; +#[doc = "SM1DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dismap0`] module"] +#[doc(alias = "SM1DISMAP0")] +pub type Sm1dismap0 = crate::Reg; +#[doc = "Fault Disable Mapping Register 0"] +pub mod sm1dismap0; +#[doc = "SM1DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dtcnt0`] module"] +#[doc(alias = "SM1DTCNT0")] +pub type Sm1dtcnt0 = crate::Reg; +#[doc = "Deadtime Count Register 0"] +pub mod sm1dtcnt0; +#[doc = "SM1DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dtcnt1`] module"] +#[doc(alias = "SM1DTCNT1")] +pub type Sm1dtcnt1 = crate::Reg; +#[doc = "Deadtime Count Register 1"] +pub mod sm1dtcnt1; +#[doc = "SM1CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1captctrlx`] module"] +#[doc(alias = "SM1CAPTCTRLX")] +pub type Sm1captctrlx = crate::Reg; +#[doc = "Capture Control X Register"] +pub mod sm1captctrlx; +#[doc = "SM1CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1captcompx`] module"] +#[doc(alias = "SM1CAPTCOMPX")] +pub type Sm1captcompx = crate::Reg; +#[doc = "Capture Compare X Register"] +pub mod sm1captcompx; +#[doc = "SM1CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval0`] module"] +#[doc(alias = "SM1CVAL0")] +pub type Sm1cval0 = crate::Reg; +#[doc = "Capture Value 0 Register"] +pub mod sm1cval0; +#[doc = "SM1CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval0cyc`] module"] +#[doc(alias = "SM1CVAL0CYC")] +pub type Sm1cval0cyc = crate::Reg; +#[doc = "Capture Value 0 Cycle Register"] +pub mod sm1cval0cyc; +#[doc = "SM1CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval1`] module"] +#[doc(alias = "SM1CVAL1")] +pub type Sm1cval1 = crate::Reg; +#[doc = "Capture Value 1 Register"] +pub mod sm1cval1; +#[doc = "SM1CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval1cyc`] module"] +#[doc(alias = "SM1CVAL1CYC")] +pub type Sm1cval1cyc = crate::Reg; +#[doc = "Capture Value 1 Cycle Register"] +pub mod sm1cval1cyc; +#[doc = "SM1PHASEDLY (rw) register accessor: Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1phasedly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1phasedly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1phasedly`] module"] +#[doc(alias = "SM1PHASEDLY")] +pub type Sm1phasedly = crate::Reg; +#[doc = "Phase Delay Register"] +pub mod sm1phasedly; +#[doc = "SM1CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1captfiltx`] module"] +#[doc(alias = "SM1CAPTFILTX")] +pub type Sm1captfiltx = crate::Reg; +#[doc = "Capture PWM_X Input Filter Register"] +pub mod sm1captfiltx; +#[doc = "SM2CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cnt`] module"] +#[doc(alias = "SM2CNT")] +pub type Sm2cnt = crate::Reg; +#[doc = "Counter Register"] +pub mod sm2cnt; +#[doc = "SM2INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2init`] module"] +#[doc(alias = "SM2INIT")] +pub type Sm2init = crate::Reg; +#[doc = "Initial Count Register"] +pub mod sm2init; +#[doc = "SM2CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2ctrl2`] module"] +#[doc(alias = "SM2CTRL2")] +pub type Sm2ctrl2 = crate::Reg; +#[doc = "Control 2 Register"] +pub mod sm2ctrl2; +#[doc = "SM2CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2ctrl`] module"] +#[doc(alias = "SM2CTRL")] +pub type Sm2ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod sm2ctrl; +#[doc = "SM2VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val0`] module"] +#[doc(alias = "SM2VAL0")] +pub type Sm2val0 = crate::Reg; +#[doc = "Value Register 0"] +pub mod sm2val0; +#[doc = "SM2VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val1`] module"] +#[doc(alias = "SM2VAL1")] +pub type Sm2val1 = crate::Reg; +#[doc = "Value Register 1"] +pub mod sm2val1; +#[doc = "SM2VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val2`] module"] +#[doc(alias = "SM2VAL2")] +pub type Sm2val2 = crate::Reg; +#[doc = "Value Register 2"] +pub mod sm2val2; +#[doc = "SM2VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val3`] module"] +#[doc(alias = "SM2VAL3")] +pub type Sm2val3 = crate::Reg; +#[doc = "Value Register 3"] +pub mod sm2val3; +#[doc = "SM2VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val4`] module"] +#[doc(alias = "SM2VAL4")] +pub type Sm2val4 = crate::Reg; +#[doc = "Value Register 4"] +pub mod sm2val4; +#[doc = "SM2VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val5`] module"] +#[doc(alias = "SM2VAL5")] +pub type Sm2val5 = crate::Reg; +#[doc = "Value Register 5"] +pub mod sm2val5; +#[doc = "SM2OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2octrl`] module"] +#[doc(alias = "SM2OCTRL")] +pub type Sm2octrl = crate::Reg; +#[doc = "Output Control Register"] +pub mod sm2octrl; +#[doc = "SM2STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2sts`] module"] +#[doc(alias = "SM2STS")] +pub type Sm2sts = crate::Reg; +#[doc = "Status Register"] +pub mod sm2sts; +#[doc = "SM2INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2inten`] module"] +#[doc(alias = "SM2INTEN")] +pub type Sm2inten = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod sm2inten; +#[doc = "SM2DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dmaen`] module"] +#[doc(alias = "SM2DMAEN")] +pub type Sm2dmaen = crate::Reg; +#[doc = "DMA Enable Register"] +pub mod sm2dmaen; +#[doc = "SM2TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2tctrl`] module"] +#[doc(alias = "SM2TCTRL")] +pub type Sm2tctrl = crate::Reg; +#[doc = "Output Trigger Control Register"] +pub mod sm2tctrl; +#[doc = "SM2DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dismap0`] module"] +#[doc(alias = "SM2DISMAP0")] +pub type Sm2dismap0 = crate::Reg; +#[doc = "Fault Disable Mapping Register 0"] +pub mod sm2dismap0; +#[doc = "SM2DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dtcnt0`] module"] +#[doc(alias = "SM2DTCNT0")] +pub type Sm2dtcnt0 = crate::Reg; +#[doc = "Deadtime Count Register 0"] +pub mod sm2dtcnt0; +#[doc = "SM2DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dtcnt1`] module"] +#[doc(alias = "SM2DTCNT1")] +pub type Sm2dtcnt1 = crate::Reg; +#[doc = "Deadtime Count Register 1"] +pub mod sm2dtcnt1; +#[doc = "SM2CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2captctrlx`] module"] +#[doc(alias = "SM2CAPTCTRLX")] +pub type Sm2captctrlx = crate::Reg; +#[doc = "Capture Control X Register"] +pub mod sm2captctrlx; +#[doc = "SM2CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2captcompx`] module"] +#[doc(alias = "SM2CAPTCOMPX")] +pub type Sm2captcompx = crate::Reg; +#[doc = "Capture Compare X Register"] +pub mod sm2captcompx; +#[doc = "SM2CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval0`] module"] +#[doc(alias = "SM2CVAL0")] +pub type Sm2cval0 = crate::Reg; +#[doc = "Capture Value 0 Register"] +pub mod sm2cval0; +#[doc = "SM2CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval0cyc`] module"] +#[doc(alias = "SM2CVAL0CYC")] +pub type Sm2cval0cyc = crate::Reg; +#[doc = "Capture Value 0 Cycle Register"] +pub mod sm2cval0cyc; +#[doc = "SM2CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval1`] module"] +#[doc(alias = "SM2CVAL1")] +pub type Sm2cval1 = crate::Reg; +#[doc = "Capture Value 1 Register"] +pub mod sm2cval1; +#[doc = "SM2CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval1cyc`] module"] +#[doc(alias = "SM2CVAL1CYC")] +pub type Sm2cval1cyc = crate::Reg; +#[doc = "Capture Value 1 Cycle Register"] +pub mod sm2cval1cyc; +#[doc = "SM2PHASEDLY (rw) register accessor: Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2phasedly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2phasedly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2phasedly`] module"] +#[doc(alias = "SM2PHASEDLY")] +pub type Sm2phasedly = crate::Reg; +#[doc = "Phase Delay Register"] +pub mod sm2phasedly; +#[doc = "SM2CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2captfiltx`] module"] +#[doc(alias = "SM2CAPTFILTX")] +pub type Sm2captfiltx = crate::Reg; +#[doc = "Capture PWM_X Input Filter Register"] +pub mod sm2captfiltx; +#[doc = "SM3CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cnt`] module"] +#[doc(alias = "SM3CNT")] +pub type Sm3cnt = crate::Reg; +#[doc = "Counter Register"] +pub mod sm3cnt; +#[doc = "SM3INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3init`] module"] +#[doc(alias = "SM3INIT")] +pub type Sm3init = crate::Reg; +#[doc = "Initial Count Register"] +pub mod sm3init; +#[doc = "SM3CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3ctrl2`] module"] +#[doc(alias = "SM3CTRL2")] +pub type Sm3ctrl2 = crate::Reg; +#[doc = "Control 2 Register"] +pub mod sm3ctrl2; +#[doc = "SM3CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3ctrl`] module"] +#[doc(alias = "SM3CTRL")] +pub type Sm3ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod sm3ctrl; +#[doc = "SM3VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val0`] module"] +#[doc(alias = "SM3VAL0")] +pub type Sm3val0 = crate::Reg; +#[doc = "Value Register 0"] +pub mod sm3val0; +#[doc = "SM3VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val1`] module"] +#[doc(alias = "SM3VAL1")] +pub type Sm3val1 = crate::Reg; +#[doc = "Value Register 1"] +pub mod sm3val1; +#[doc = "SM3VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val2`] module"] +#[doc(alias = "SM3VAL2")] +pub type Sm3val2 = crate::Reg; +#[doc = "Value Register 2"] +pub mod sm3val2; +#[doc = "SM3VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val3`] module"] +#[doc(alias = "SM3VAL3")] +pub type Sm3val3 = crate::Reg; +#[doc = "Value Register 3"] +pub mod sm3val3; +#[doc = "SM3VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val4`] module"] +#[doc(alias = "SM3VAL4")] +pub type Sm3val4 = crate::Reg; +#[doc = "Value Register 4"] +pub mod sm3val4; +#[doc = "SM3VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val5`] module"] +#[doc(alias = "SM3VAL5")] +pub type Sm3val5 = crate::Reg; +#[doc = "Value Register 5"] +pub mod sm3val5; +#[doc = "SM3OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3octrl`] module"] +#[doc(alias = "SM3OCTRL")] +pub type Sm3octrl = crate::Reg; +#[doc = "Output Control Register"] +pub mod sm3octrl; +#[doc = "SM3STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3sts`] module"] +#[doc(alias = "SM3STS")] +pub type Sm3sts = crate::Reg; +#[doc = "Status Register"] +pub mod sm3sts; +#[doc = "SM3INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3inten`] module"] +#[doc(alias = "SM3INTEN")] +pub type Sm3inten = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod sm3inten; +#[doc = "SM3DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dmaen`] module"] +#[doc(alias = "SM3DMAEN")] +pub type Sm3dmaen = crate::Reg; +#[doc = "DMA Enable Register"] +pub mod sm3dmaen; +#[doc = "SM3TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3tctrl`] module"] +#[doc(alias = "SM3TCTRL")] +pub type Sm3tctrl = crate::Reg; +#[doc = "Output Trigger Control Register"] +pub mod sm3tctrl; +#[doc = "SM3DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dismap0`] module"] +#[doc(alias = "SM3DISMAP0")] +pub type Sm3dismap0 = crate::Reg; +#[doc = "Fault Disable Mapping Register 0"] +pub mod sm3dismap0; +#[doc = "SM3DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dtcnt0`] module"] +#[doc(alias = "SM3DTCNT0")] +pub type Sm3dtcnt0 = crate::Reg; +#[doc = "Deadtime Count Register 0"] +pub mod sm3dtcnt0; +#[doc = "SM3DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dtcnt1`] module"] +#[doc(alias = "SM3DTCNT1")] +pub type Sm3dtcnt1 = crate::Reg; +#[doc = "Deadtime Count Register 1"] +pub mod sm3dtcnt1; +#[doc = "SM3CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3captctrlx`] module"] +#[doc(alias = "SM3CAPTCTRLX")] +pub type Sm3captctrlx = crate::Reg; +#[doc = "Capture Control X Register"] +pub mod sm3captctrlx; +#[doc = "SM3CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3captcompx`] module"] +#[doc(alias = "SM3CAPTCOMPX")] +pub type Sm3captcompx = crate::Reg; +#[doc = "Capture Compare X Register"] +pub mod sm3captcompx; +#[doc = "SM3CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval0`] module"] +#[doc(alias = "SM3CVAL0")] +pub type Sm3cval0 = crate::Reg; +#[doc = "Capture Value 0 Register"] +pub mod sm3cval0; +#[doc = "SM3CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval0cyc`] module"] +#[doc(alias = "SM3CVAL0CYC")] +pub type Sm3cval0cyc = crate::Reg; +#[doc = "Capture Value 0 Cycle Register"] +pub mod sm3cval0cyc; +#[doc = "SM3CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval1`] module"] +#[doc(alias = "SM3CVAL1")] +pub type Sm3cval1 = crate::Reg; +#[doc = "Capture Value 1 Register"] +pub mod sm3cval1; +#[doc = "SM3CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval1cyc`] module"] +#[doc(alias = "SM3CVAL1CYC")] +pub type Sm3cval1cyc = crate::Reg; +#[doc = "Capture Value 1 Cycle Register"] +pub mod sm3cval1cyc; +#[doc = "SM3PHASEDLY (rw) register accessor: Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3phasedly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3phasedly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3phasedly`] module"] +#[doc(alias = "SM3PHASEDLY")] +pub type Sm3phasedly = crate::Reg; +#[doc = "Phase Delay Register"] +pub mod sm3phasedly; +#[doc = "SM3CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3captfiltx`] module"] +#[doc(alias = "SM3CAPTFILTX")] +pub type Sm3captfiltx = crate::Reg; +#[doc = "Capture PWM_X Input Filter Register"] +pub mod sm3captfiltx; +#[doc = "OUTEN (rw) register accessor: Output Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outen`] module"] +#[doc(alias = "OUTEN")] +pub type Outen = crate::Reg; +#[doc = "Output Enable Register"] +pub mod outen; +#[doc = "MASK (rw) register accessor: Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mask`] module"] +#[doc(alias = "MASK")] +pub type Mask = crate::Reg; +#[doc = "Mask Register"] +pub mod mask; +#[doc = "SWCOUT (rw) register accessor: Software Controlled Output Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swcout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swcout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swcout`] module"] +#[doc(alias = "SWCOUT")] +pub type Swcout = crate::Reg; +#[doc = "Software Controlled Output Register"] +pub mod swcout; +#[doc = "DTSRCSEL (rw) register accessor: PWM Source Select Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dtsrcsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtsrcsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtsrcsel`] module"] +#[doc(alias = "DTSRCSEL")] +pub type Dtsrcsel = crate::Reg; +#[doc = "PWM Source Select Register"] +pub mod dtsrcsel; +#[doc = "MCTRL (rw) register accessor: Master Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctrl`] module"] +#[doc(alias = "MCTRL")] +pub type Mctrl = crate::Reg; +#[doc = "Master Control Register"] +pub mod mctrl; +#[doc = "MCTRL2 (rw) register accessor: Master Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctrl2`] module"] +#[doc(alias = "MCTRL2")] +pub type Mctrl2 = crate::Reg; +#[doc = "Master Control 2 Register"] +pub mod mctrl2; +#[doc = "FCTRL0 (rw) register accessor: Fault Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl0`] module"] +#[doc(alias = "FCTRL0")] +pub type Fctrl0 = crate::Reg; +#[doc = "Fault Control Register"] +pub mod fctrl0; +#[doc = "FSTS0 (rw) register accessor: Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fsts0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsts0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsts0`] module"] +#[doc(alias = "FSTS0")] +pub type Fsts0 = crate::Reg; +#[doc = "Fault Status Register"] +pub mod fsts0; +#[doc = "FFILT0 (rw) register accessor: Fault Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ffilt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ffilt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ffilt0`] module"] +#[doc(alias = "FFILT0")] +pub type Ffilt0 = crate::Reg; +#[doc = "Fault Filter Register"] +pub mod ffilt0; +#[doc = "FTST0 (rw) register accessor: Fault Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ftst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ftst0`] module"] +#[doc(alias = "FTST0")] +pub type Ftst0 = crate::Reg; +#[doc = "Fault Test Register"] +pub mod ftst0; +#[doc = "FCTRL20 (rw) register accessor: Fault Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl20`] module"] +#[doc(alias = "FCTRL20")] +pub type Fctrl20 = crate::Reg; +#[doc = "Fault Control 2 Register"] +pub mod fctrl20; diff --git a/mcxa276-pac/src/flexpwm0/dtsrcsel.rs b/mcxa276-pac/src/flexpwm0/dtsrcsel.rs new file mode 100644 index 000000000..3326af76d --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/dtsrcsel.rs @@ -0,0 +1,737 @@ +#[doc = "Register `DTSRCSEL` reader"] +pub type R = crate::R; +#[doc = "Register `DTSRCSEL` writer"] +pub type W = crate::W; +#[doc = "Submodule 0 PWM45 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm0sel45 { + #[doc = "0: Generated SM0PWM45 signal used by the deadtime logic."] + Sm0pwm45 = 0, + #[doc = "1: Inverted generated SM0PWM45 signal used by the deadtime logic."] + InvertedSm0pwm45 = 1, + #[doc = "2: SWCOUT\\[SM0OUT45\\] used by the deadtime logic."] + Sm0out45 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm0sel45) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm0sel45 { + type Ux = u8; +} +impl crate::IsEnum for Sm0sel45 {} +#[doc = "Field `SM0SEL45` reader - Submodule 0 PWM45 Control Select"] +pub type Sm0sel45R = crate::FieldReader; +impl Sm0sel45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Sm0sel45::Sm0pwm45), + 1 => Some(Sm0sel45::InvertedSm0pwm45), + 2 => Some(Sm0sel45::Sm0out45), + _ => None, + } + } + #[doc = "Generated SM0PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm0pwm45(&self) -> bool { + *self == Sm0sel45::Sm0pwm45 + } + #[doc = "Inverted generated SM0PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm0pwm45(&self) -> bool { + *self == Sm0sel45::InvertedSm0pwm45 + } + #[doc = "SWCOUT\\[SM0OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm0out45(&self) -> bool { + *self == Sm0sel45::Sm0out45 + } +} +#[doc = "Field `SM0SEL45` writer - Submodule 0 PWM45 Control Select"] +pub type Sm0sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm0sel45>; +impl<'a, REG> Sm0sel45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM0PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm0pwm45(self) -> &'a mut crate::W { + self.variant(Sm0sel45::Sm0pwm45) + } + #[doc = "Inverted generated SM0PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm0pwm45(self) -> &'a mut crate::W { + self.variant(Sm0sel45::InvertedSm0pwm45) + } + #[doc = "SWCOUT\\[SM0OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm0out45(self) -> &'a mut crate::W { + self.variant(Sm0sel45::Sm0out45) + } +} +#[doc = "Submodule 0 PWM23 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm0sel23 { + #[doc = "0: Generated SM0PWM23 signal used by the deadtime logic."] + Sm0pwm23 = 0, + #[doc = "1: Inverted generated SM0PWM23 signal used by the deadtime logic."] + InvertedSm0pwm23 = 1, + #[doc = "2: SWCOUT\\[SM0OUT23\\] used by the deadtime logic."] + Sm0out23 = 2, + #[doc = "3: PWM0_EXTA signal used by the deadtime logic."] + Pwm0Exta = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm0sel23) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm0sel23 { + type Ux = u8; +} +impl crate::IsEnum for Sm0sel23 {} +#[doc = "Field `SM0SEL23` reader - Submodule 0 PWM23 Control Select"] +pub type Sm0sel23R = crate::FieldReader; +impl Sm0sel23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm0sel23 { + match self.bits { + 0 => Sm0sel23::Sm0pwm23, + 1 => Sm0sel23::InvertedSm0pwm23, + 2 => Sm0sel23::Sm0out23, + 3 => Sm0sel23::Pwm0Exta, + _ => unreachable!(), + } + } + #[doc = "Generated SM0PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm0pwm23(&self) -> bool { + *self == Sm0sel23::Sm0pwm23 + } + #[doc = "Inverted generated SM0PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm0pwm23(&self) -> bool { + *self == Sm0sel23::InvertedSm0pwm23 + } + #[doc = "SWCOUT\\[SM0OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm0out23(&self) -> bool { + *self == Sm0sel23::Sm0out23 + } + #[doc = "PWM0_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn is_pwm0_exta(&self) -> bool { + *self == Sm0sel23::Pwm0Exta + } +} +#[doc = "Field `SM0SEL23` writer - Submodule 0 PWM23 Control Select"] +pub type Sm0sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm0sel23, crate::Safe>; +impl<'a, REG> Sm0sel23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM0PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm0pwm23(self) -> &'a mut crate::W { + self.variant(Sm0sel23::Sm0pwm23) + } + #[doc = "Inverted generated SM0PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm0pwm23(self) -> &'a mut crate::W { + self.variant(Sm0sel23::InvertedSm0pwm23) + } + #[doc = "SWCOUT\\[SM0OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm0out23(self) -> &'a mut crate::W { + self.variant(Sm0sel23::Sm0out23) + } + #[doc = "PWM0_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn pwm0_exta(self) -> &'a mut crate::W { + self.variant(Sm0sel23::Pwm0Exta) + } +} +#[doc = "Submodule 1 PWM45 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm1sel45 { + #[doc = "0: Generated SM1PWM45 signal used by the deadtime logic."] + Sm1pwm45 = 0, + #[doc = "1: Inverted generated SM1PWM45 signal used by the deadtime logic."] + InvertedSm1pwm45 = 1, + #[doc = "2: SWCOUT\\[SM1OUT45\\] used by the deadtime logic."] + Sm1out45 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm1sel45) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm1sel45 { + type Ux = u8; +} +impl crate::IsEnum for Sm1sel45 {} +#[doc = "Field `SM1SEL45` reader - Submodule 1 PWM45 Control Select"] +pub type Sm1sel45R = crate::FieldReader; +impl Sm1sel45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Sm1sel45::Sm1pwm45), + 1 => Some(Sm1sel45::InvertedSm1pwm45), + 2 => Some(Sm1sel45::Sm1out45), + _ => None, + } + } + #[doc = "Generated SM1PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm1pwm45(&self) -> bool { + *self == Sm1sel45::Sm1pwm45 + } + #[doc = "Inverted generated SM1PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm1pwm45(&self) -> bool { + *self == Sm1sel45::InvertedSm1pwm45 + } + #[doc = "SWCOUT\\[SM1OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm1out45(&self) -> bool { + *self == Sm1sel45::Sm1out45 + } +} +#[doc = "Field `SM1SEL45` writer - Submodule 1 PWM45 Control Select"] +pub type Sm1sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm1sel45>; +impl<'a, REG> Sm1sel45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM1PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm1pwm45(self) -> &'a mut crate::W { + self.variant(Sm1sel45::Sm1pwm45) + } + #[doc = "Inverted generated SM1PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm1pwm45(self) -> &'a mut crate::W { + self.variant(Sm1sel45::InvertedSm1pwm45) + } + #[doc = "SWCOUT\\[SM1OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm1out45(self) -> &'a mut crate::W { + self.variant(Sm1sel45::Sm1out45) + } +} +#[doc = "Submodule 1 PWM23 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm1sel23 { + #[doc = "0: Generated SM1PWM23 signal used by the deadtime logic."] + Sm1pwm23 = 0, + #[doc = "1: Inverted generated SM1PWM23 signal used by the deadtime logic."] + InvertedSm1pwm23 = 1, + #[doc = "2: SWCOUT\\[SM1OUT23\\] used by the deadtime logic."] + Sm1out23 = 2, + #[doc = "3: PWM1_EXTA signal used by the deadtime logic."] + Pwm1Exta = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm1sel23) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm1sel23 { + type Ux = u8; +} +impl crate::IsEnum for Sm1sel23 {} +#[doc = "Field `SM1SEL23` reader - Submodule 1 PWM23 Control Select"] +pub type Sm1sel23R = crate::FieldReader; +impl Sm1sel23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm1sel23 { + match self.bits { + 0 => Sm1sel23::Sm1pwm23, + 1 => Sm1sel23::InvertedSm1pwm23, + 2 => Sm1sel23::Sm1out23, + 3 => Sm1sel23::Pwm1Exta, + _ => unreachable!(), + } + } + #[doc = "Generated SM1PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm1pwm23(&self) -> bool { + *self == Sm1sel23::Sm1pwm23 + } + #[doc = "Inverted generated SM1PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm1pwm23(&self) -> bool { + *self == Sm1sel23::InvertedSm1pwm23 + } + #[doc = "SWCOUT\\[SM1OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm1out23(&self) -> bool { + *self == Sm1sel23::Sm1out23 + } + #[doc = "PWM1_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn is_pwm1_exta(&self) -> bool { + *self == Sm1sel23::Pwm1Exta + } +} +#[doc = "Field `SM1SEL23` writer - Submodule 1 PWM23 Control Select"] +pub type Sm1sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm1sel23, crate::Safe>; +impl<'a, REG> Sm1sel23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM1PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm1pwm23(self) -> &'a mut crate::W { + self.variant(Sm1sel23::Sm1pwm23) + } + #[doc = "Inverted generated SM1PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm1pwm23(self) -> &'a mut crate::W { + self.variant(Sm1sel23::InvertedSm1pwm23) + } + #[doc = "SWCOUT\\[SM1OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm1out23(self) -> &'a mut crate::W { + self.variant(Sm1sel23::Sm1out23) + } + #[doc = "PWM1_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn pwm1_exta(self) -> &'a mut crate::W { + self.variant(Sm1sel23::Pwm1Exta) + } +} +#[doc = "Submodule 2 PWM45 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm2sel45 { + #[doc = "0: Generated SM2PWM45 signal used by the deadtime logic."] + Sm2pwm45 = 0, + #[doc = "1: Inverted generated SM2PWM45 signal used by the deadtime logic."] + InvertedSm2pwm45 = 1, + #[doc = "2: SWCOUT\\[SM2OUT45\\] used by the deadtime logic."] + Sm2out45 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm2sel45) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm2sel45 { + type Ux = u8; +} +impl crate::IsEnum for Sm2sel45 {} +#[doc = "Field `SM2SEL45` reader - Submodule 2 PWM45 Control Select"] +pub type Sm2sel45R = crate::FieldReader; +impl Sm2sel45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Sm2sel45::Sm2pwm45), + 1 => Some(Sm2sel45::InvertedSm2pwm45), + 2 => Some(Sm2sel45::Sm2out45), + _ => None, + } + } + #[doc = "Generated SM2PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm2pwm45(&self) -> bool { + *self == Sm2sel45::Sm2pwm45 + } + #[doc = "Inverted generated SM2PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm2pwm45(&self) -> bool { + *self == Sm2sel45::InvertedSm2pwm45 + } + #[doc = "SWCOUT\\[SM2OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm2out45(&self) -> bool { + *self == Sm2sel45::Sm2out45 + } +} +#[doc = "Field `SM2SEL45` writer - Submodule 2 PWM45 Control Select"] +pub type Sm2sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm2sel45>; +impl<'a, REG> Sm2sel45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM2PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm2pwm45(self) -> &'a mut crate::W { + self.variant(Sm2sel45::Sm2pwm45) + } + #[doc = "Inverted generated SM2PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm2pwm45(self) -> &'a mut crate::W { + self.variant(Sm2sel45::InvertedSm2pwm45) + } + #[doc = "SWCOUT\\[SM2OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm2out45(self) -> &'a mut crate::W { + self.variant(Sm2sel45::Sm2out45) + } +} +#[doc = "Submodule 2 PWM23 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm2sel23 { + #[doc = "0: Generated SM2PWM23 signal used by the deadtime logic."] + Sm2pwm23 = 0, + #[doc = "1: Inverted generated SM2PWM23 signal used by the deadtime logic."] + InvertedSm2pwm23 = 1, + #[doc = "2: SWCOUT\\[SM2OUT23\\] used by the deadtime logic."] + Sm2out23 = 2, + #[doc = "3: PWM2_EXTA signal used by the deadtime logic."] + Pwm2Exta = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm2sel23) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm2sel23 { + type Ux = u8; +} +impl crate::IsEnum for Sm2sel23 {} +#[doc = "Field `SM2SEL23` reader - Submodule 2 PWM23 Control Select"] +pub type Sm2sel23R = crate::FieldReader; +impl Sm2sel23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm2sel23 { + match self.bits { + 0 => Sm2sel23::Sm2pwm23, + 1 => Sm2sel23::InvertedSm2pwm23, + 2 => Sm2sel23::Sm2out23, + 3 => Sm2sel23::Pwm2Exta, + _ => unreachable!(), + } + } + #[doc = "Generated SM2PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm2pwm23(&self) -> bool { + *self == Sm2sel23::Sm2pwm23 + } + #[doc = "Inverted generated SM2PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm2pwm23(&self) -> bool { + *self == Sm2sel23::InvertedSm2pwm23 + } + #[doc = "SWCOUT\\[SM2OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm2out23(&self) -> bool { + *self == Sm2sel23::Sm2out23 + } + #[doc = "PWM2_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn is_pwm2_exta(&self) -> bool { + *self == Sm2sel23::Pwm2Exta + } +} +#[doc = "Field `SM2SEL23` writer - Submodule 2 PWM23 Control Select"] +pub type Sm2sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm2sel23, crate::Safe>; +impl<'a, REG> Sm2sel23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM2PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm2pwm23(self) -> &'a mut crate::W { + self.variant(Sm2sel23::Sm2pwm23) + } + #[doc = "Inverted generated SM2PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm2pwm23(self) -> &'a mut crate::W { + self.variant(Sm2sel23::InvertedSm2pwm23) + } + #[doc = "SWCOUT\\[SM2OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm2out23(self) -> &'a mut crate::W { + self.variant(Sm2sel23::Sm2out23) + } + #[doc = "PWM2_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn pwm2_exta(self) -> &'a mut crate::W { + self.variant(Sm2sel23::Pwm2Exta) + } +} +#[doc = "Submodule 3 PWM45 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm3sel45 { + #[doc = "0: Generated SM3PWM45 signal used by the deadtime logic."] + Sm3pwm45 = 0, + #[doc = "1: Inverted generated SM3PWM45 signal used by the deadtime logic."] + InvertedSm3pwm45 = 1, + #[doc = "2: SWCOUT\\[SM3OUT45\\] used by the deadtime logic."] + Sm3out45 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm3sel45) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm3sel45 { + type Ux = u8; +} +impl crate::IsEnum for Sm3sel45 {} +#[doc = "Field `SM3SEL45` reader - Submodule 3 PWM45 Control Select"] +pub type Sm3sel45R = crate::FieldReader; +impl Sm3sel45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Sm3sel45::Sm3pwm45), + 1 => Some(Sm3sel45::InvertedSm3pwm45), + 2 => Some(Sm3sel45::Sm3out45), + _ => None, + } + } + #[doc = "Generated SM3PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm3pwm45(&self) -> bool { + *self == Sm3sel45::Sm3pwm45 + } + #[doc = "Inverted generated SM3PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm3pwm45(&self) -> bool { + *self == Sm3sel45::InvertedSm3pwm45 + } + #[doc = "SWCOUT\\[SM3OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm3out45(&self) -> bool { + *self == Sm3sel45::Sm3out45 + } +} +#[doc = "Field `SM3SEL45` writer - Submodule 3 PWM45 Control Select"] +pub type Sm3sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm3sel45>; +impl<'a, REG> Sm3sel45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM3PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm3pwm45(self) -> &'a mut crate::W { + self.variant(Sm3sel45::Sm3pwm45) + } + #[doc = "Inverted generated SM3PWM45 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm3pwm45(self) -> &'a mut crate::W { + self.variant(Sm3sel45::InvertedSm3pwm45) + } + #[doc = "SWCOUT\\[SM3OUT45\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm3out45(self) -> &'a mut crate::W { + self.variant(Sm3sel45::Sm3out45) + } +} +#[doc = "Submodule 3 PWM23 Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sm3sel23 { + #[doc = "0: Generated SM3PWM23 signal used by the deadtime logic."] + Sm3pwm23 = 0, + #[doc = "1: Inverted generated SM3PWM23 signal used by the deadtime logic."] + InvertedSm3pwm23 = 1, + #[doc = "2: SWCOUT\\[SM3OUT23\\] used by the deadtime logic."] + Sm3out23 = 2, + #[doc = "3: PWM3_EXTA signal used by the deadtime logic."] + Pwm3Exta = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sm3sel23) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sm3sel23 { + type Ux = u8; +} +impl crate::IsEnum for Sm3sel23 {} +#[doc = "Field `SM3SEL23` reader - Submodule 3 PWM23 Control Select"] +pub type Sm3sel23R = crate::FieldReader; +impl Sm3sel23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm3sel23 { + match self.bits { + 0 => Sm3sel23::Sm3pwm23, + 1 => Sm3sel23::InvertedSm3pwm23, + 2 => Sm3sel23::Sm3out23, + 3 => Sm3sel23::Pwm3Exta, + _ => unreachable!(), + } + } + #[doc = "Generated SM3PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_sm3pwm23(&self) -> bool { + *self == Sm3sel23::Sm3pwm23 + } + #[doc = "Inverted generated SM3PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn is_inverted_sm3pwm23(&self) -> bool { + *self == Sm3sel23::InvertedSm3pwm23 + } + #[doc = "SWCOUT\\[SM3OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn is_sm3out23(&self) -> bool { + *self == Sm3sel23::Sm3out23 + } + #[doc = "PWM3_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn is_pwm3_exta(&self) -> bool { + *self == Sm3sel23::Pwm3Exta + } +} +#[doc = "Field `SM3SEL23` writer - Submodule 3 PWM23 Control Select"] +pub type Sm3sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm3sel23, crate::Safe>; +impl<'a, REG> Sm3sel23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Generated SM3PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn sm3pwm23(self) -> &'a mut crate::W { + self.variant(Sm3sel23::Sm3pwm23) + } + #[doc = "Inverted generated SM3PWM23 signal used by the deadtime logic."] + #[inline(always)] + pub fn inverted_sm3pwm23(self) -> &'a mut crate::W { + self.variant(Sm3sel23::InvertedSm3pwm23) + } + #[doc = "SWCOUT\\[SM3OUT23\\] used by the deadtime logic."] + #[inline(always)] + pub fn sm3out23(self) -> &'a mut crate::W { + self.variant(Sm3sel23::Sm3out23) + } + #[doc = "PWM3_EXTA signal used by the deadtime logic."] + #[inline(always)] + pub fn pwm3_exta(self) -> &'a mut crate::W { + self.variant(Sm3sel23::Pwm3Exta) + } +} +impl R { + #[doc = "Bits 0:1 - Submodule 0 PWM45 Control Select"] + #[inline(always)] + pub fn sm0sel45(&self) -> Sm0sel45R { + Sm0sel45R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Submodule 0 PWM23 Control Select"] + #[inline(always)] + pub fn sm0sel23(&self) -> Sm0sel23R { + Sm0sel23R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Submodule 1 PWM45 Control Select"] + #[inline(always)] + pub fn sm1sel45(&self) -> Sm1sel45R { + Sm1sel45R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Submodule 1 PWM23 Control Select"] + #[inline(always)] + pub fn sm1sel23(&self) -> Sm1sel23R { + Sm1sel23R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Submodule 2 PWM45 Control Select"] + #[inline(always)] + pub fn sm2sel45(&self) -> Sm2sel45R { + Sm2sel45R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Submodule 2 PWM23 Control Select"] + #[inline(always)] + pub fn sm2sel23(&self) -> Sm2sel23R { + Sm2sel23R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Submodule 3 PWM45 Control Select"] + #[inline(always)] + pub fn sm3sel45(&self) -> Sm3sel45R { + Sm3sel45R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Submodule 3 PWM23 Control Select"] + #[inline(always)] + pub fn sm3sel23(&self) -> Sm3sel23R { + Sm3sel23R::new(((self.bits >> 14) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Submodule 0 PWM45 Control Select"] + #[inline(always)] + pub fn sm0sel45(&mut self) -> Sm0sel45W { + Sm0sel45W::new(self, 0) + } + #[doc = "Bits 2:3 - Submodule 0 PWM23 Control Select"] + #[inline(always)] + pub fn sm0sel23(&mut self) -> Sm0sel23W { + Sm0sel23W::new(self, 2) + } + #[doc = "Bits 4:5 - Submodule 1 PWM45 Control Select"] + #[inline(always)] + pub fn sm1sel45(&mut self) -> Sm1sel45W { + Sm1sel45W::new(self, 4) + } + #[doc = "Bits 6:7 - Submodule 1 PWM23 Control Select"] + #[inline(always)] + pub fn sm1sel23(&mut self) -> Sm1sel23W { + Sm1sel23W::new(self, 6) + } + #[doc = "Bits 8:9 - Submodule 2 PWM45 Control Select"] + #[inline(always)] + pub fn sm2sel45(&mut self) -> Sm2sel45W { + Sm2sel45W::new(self, 8) + } + #[doc = "Bits 10:11 - Submodule 2 PWM23 Control Select"] + #[inline(always)] + pub fn sm2sel23(&mut self) -> Sm2sel23W { + Sm2sel23W::new(self, 10) + } + #[doc = "Bits 12:13 - Submodule 3 PWM45 Control Select"] + #[inline(always)] + pub fn sm3sel45(&mut self) -> Sm3sel45W { + Sm3sel45W::new(self, 12) + } + #[doc = "Bits 14:15 - Submodule 3 PWM23 Control Select"] + #[inline(always)] + pub fn sm3sel23(&mut self) -> Sm3sel23W { + Sm3sel23W::new(self, 14) + } +} +#[doc = "PWM Source Select Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dtsrcsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtsrcsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DtsrcselSpec; +impl crate::RegisterSpec for DtsrcselSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`dtsrcsel::R`](R) reader structure"] +impl crate::Readable for DtsrcselSpec {} +#[doc = "`write(|w| ..)` method takes [`dtsrcsel::W`](W) writer structure"] +impl crate::Writable for DtsrcselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DTSRCSEL to value 0"] +impl crate::Resettable for DtsrcselSpec {} diff --git a/mcxa276-pac/src/flexpwm0/fctrl0.rs b/mcxa276-pac/src/flexpwm0/fctrl0.rs new file mode 100644 index 000000000..cdc5147e6 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/fctrl0.rs @@ -0,0 +1,301 @@ +#[doc = "Register `FCTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `FCTRL0` writer"] +pub type W = crate::W; +#[doc = "Fault Interrupt Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fie { + #[doc = "0: FAULTx CPU interrupt requests disabled."] + Disabled = 0, + #[doc = "1: FAULTx CPU interrupt requests enabled."] + Enabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fie) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fie { + type Ux = u8; +} +impl crate::IsEnum for Fie {} +#[doc = "Field `FIE` reader - Fault Interrupt Enables"] +pub type FieR = crate::FieldReader; +impl FieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Fie::Disabled), + 1 => Some(Fie::Enabled), + _ => None, + } + } + #[doc = "FAULTx CPU interrupt requests disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fie::Disabled + } + #[doc = "FAULTx CPU interrupt requests enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fie::Enabled + } +} +#[doc = "Field `FIE` writer - Fault Interrupt Enables"] +pub type FieW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fie>; +impl<'a, REG> FieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FAULTx CPU interrupt requests disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fie::Disabled) + } + #[doc = "FAULTx CPU interrupt requests enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fie::Enabled) + } +} +#[doc = "Fault Safety Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fsafe { + #[doc = "0: Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."] + Normal = 0, + #[doc = "1: Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."] + Safe = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fsafe) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fsafe { + type Ux = u8; +} +impl crate::IsEnum for Fsafe {} +#[doc = "Field `FSAFE` reader - Fault Safety Mode"] +pub type FsafeR = crate::FieldReader; +impl FsafeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Fsafe::Normal), + 1 => Some(Fsafe::Safe), + _ => None, + } + } + #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == Fsafe::Normal + } + #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."] + #[inline(always)] + pub fn is_safe(&self) -> bool { + *self == Fsafe::Safe + } +} +#[doc = "Field `FSAFE` writer - Fault Safety Mode"] +pub type FsafeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fsafe>; +impl<'a, REG> FsafeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(Fsafe::Normal) + } + #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."] + #[inline(always)] + pub fn safe(self) -> &'a mut crate::W { + self.variant(Fsafe::Safe) + } +} +#[doc = "Automatic Fault Clearing\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fauto { + #[doc = "0: Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."] + Manual = 0, + #[doc = "1: Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."] + Automatic = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fauto) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fauto { + type Ux = u8; +} +impl crate::IsEnum for Fauto {} +#[doc = "Field `FAUTO` reader - Automatic Fault Clearing"] +pub type FautoR = crate::FieldReader; +impl FautoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Fauto::Manual), + 1 => Some(Fauto::Automatic), + _ => None, + } + } + #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."] + #[inline(always)] + pub fn is_manual(&self) -> bool { + *self == Fauto::Manual + } + #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."] + #[inline(always)] + pub fn is_automatic(&self) -> bool { + *self == Fauto::Automatic + } +} +#[doc = "Field `FAUTO` writer - Automatic Fault Clearing"] +pub type FautoW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fauto>; +impl<'a, REG> FautoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."] + #[inline(always)] + pub fn manual(self) -> &'a mut crate::W { + self.variant(Fauto::Manual) + } + #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."] + #[inline(always)] + pub fn automatic(self) -> &'a mut crate::W { + self.variant(Fauto::Automatic) + } +} +#[doc = "Fault Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Flvl { + #[doc = "0: A logic 0 on the fault input indicates a fault condition."] + Logic0 = 0, + #[doc = "1: A logic 1 on the fault input indicates a fault condition."] + Logic1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Flvl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Flvl { + type Ux = u8; +} +impl crate::IsEnum for Flvl {} +#[doc = "Field `FLVL` reader - Fault Level"] +pub type FlvlR = crate::FieldReader; +impl FlvlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Flvl::Logic0), + 1 => Some(Flvl::Logic1), + _ => None, + } + } + #[doc = "A logic 0 on the fault input indicates a fault condition."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Flvl::Logic0 + } + #[doc = "A logic 1 on the fault input indicates a fault condition."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Flvl::Logic1 + } +} +#[doc = "Field `FLVL` writer - Fault Level"] +pub type FlvlW<'a, REG> = crate::FieldWriter<'a, REG, 4, Flvl>; +impl<'a, REG> FlvlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "A logic 0 on the fault input indicates a fault condition."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Flvl::Logic0) + } + #[doc = "A logic 1 on the fault input indicates a fault condition."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Flvl::Logic1) + } +} +impl R { + #[doc = "Bits 0:3 - Fault Interrupt Enables"] + #[inline(always)] + pub fn fie(&self) -> FieR { + FieR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Fault Safety Mode"] + #[inline(always)] + pub fn fsafe(&self) -> FsafeR { + FsafeR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Automatic Fault Clearing"] + #[inline(always)] + pub fn fauto(&self) -> FautoR { + FautoR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Fault Level"] + #[inline(always)] + pub fn flvl(&self) -> FlvlR { + FlvlR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Fault Interrupt Enables"] + #[inline(always)] + pub fn fie(&mut self) -> FieW { + FieW::new(self, 0) + } + #[doc = "Bits 4:7 - Fault Safety Mode"] + #[inline(always)] + pub fn fsafe(&mut self) -> FsafeW { + FsafeW::new(self, 4) + } + #[doc = "Bits 8:11 - Automatic Fault Clearing"] + #[inline(always)] + pub fn fauto(&mut self) -> FautoW { + FautoW::new(self, 8) + } + #[doc = "Bits 12:15 - Fault Level"] + #[inline(always)] + pub fn flvl(&mut self) -> FlvlW { + FlvlW::new(self, 12) + } +} +#[doc = "Fault Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fctrl0Spec; +impl crate::RegisterSpec for Fctrl0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`fctrl0::R`](R) reader structure"] +impl crate::Readable for Fctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`fctrl0::W`](W) writer structure"] +impl crate::Writable for Fctrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCTRL0 to value 0"] +impl crate::Resettable for Fctrl0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/fctrl20.rs b/mcxa276-pac/src/flexpwm0/fctrl20.rs new file mode 100644 index 000000000..9042f9d77 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/fctrl20.rs @@ -0,0 +1,91 @@ +#[doc = "Register `FCTRL20` reader"] +pub type R = crate::R; +#[doc = "Register `FCTRL20` writer"] +pub type W = crate::W; +#[doc = "No Combinational Path From Fault Input To PWM Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Nocomb { + #[doc = "0: There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."] + Enabled = 0, + #[doc = "1: The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."] + Disabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Nocomb) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Nocomb { + type Ux = u8; +} +impl crate::IsEnum for Nocomb {} +#[doc = "Field `NOCOMB` reader - No Combinational Path From Fault Input To PWM Output"] +pub type NocombR = crate::FieldReader; +impl NocombR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Nocomb::Enabled), + 1 => Some(Nocomb::Disabled), + _ => None, + } + } + #[doc = "There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Nocomb::Enabled + } + #[doc = "The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Nocomb::Disabled + } +} +#[doc = "Field `NOCOMB` writer - No Combinational Path From Fault Input To PWM Output"] +pub type NocombW<'a, REG> = crate::FieldWriter<'a, REG, 4, Nocomb>; +impl<'a, REG> NocombW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Nocomb::Enabled) + } + #[doc = "The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Nocomb::Disabled) + } +} +impl R { + #[doc = "Bits 0:3 - No Combinational Path From Fault Input To PWM Output"] + #[inline(always)] + pub fn nocomb(&self) -> NocombR { + NocombR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - No Combinational Path From Fault Input To PWM Output"] + #[inline(always)] + pub fn nocomb(&mut self) -> NocombW { + NocombW::new(self, 0) + } +} +#[doc = "Fault Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fctrl20Spec; +impl crate::RegisterSpec for Fctrl20Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`fctrl20::R`](R) reader structure"] +impl crate::Readable for Fctrl20Spec {} +#[doc = "`write(|w| ..)` method takes [`fctrl20::W`](W) writer structure"] +impl crate::Writable for Fctrl20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCTRL20 to value 0"] +impl crate::Resettable for Fctrl20Spec {} diff --git a/mcxa276-pac/src/flexpwm0/ffilt0.rs b/mcxa276-pac/src/flexpwm0/ffilt0.rs new file mode 100644 index 000000000..787387a5a --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/ffilt0.rs @@ -0,0 +1,112 @@ +#[doc = "Register `FFILT0` reader"] +pub type R = crate::R; +#[doc = "Register `FFILT0` writer"] +pub type W = crate::W; +#[doc = "Field `FILT_PER` reader - Fault Filter Period"] +pub type FiltPerR = crate::FieldReader; +#[doc = "Field `FILT_PER` writer - Fault Filter Period"] +pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `FILT_CNT` reader - Fault Filter Count"] +pub type FiltCntR = crate::FieldReader; +#[doc = "Field `FILT_CNT` writer - Fault Filter Count"] +pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Fault Glitch Stretch Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gstr { + #[doc = "0: Fault input glitch stretching is disabled."] + Disabled = 0, + #[doc = "1: Input fault signals are stretched to at least 2 IPBus clock cycles."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gstr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GSTR` reader - Fault Glitch Stretch Enable"] +pub type GstrR = crate::BitReader; +impl GstrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gstr { + match self.bits { + false => Gstr::Disabled, + true => Gstr::Enabled, + } + } + #[doc = "Fault input glitch stretching is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gstr::Disabled + } + #[doc = "Input fault signals are stretched to at least 2 IPBus clock cycles."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gstr::Enabled + } +} +#[doc = "Field `GSTR` writer - Fault Glitch Stretch Enable"] +pub type GstrW<'a, REG> = crate::BitWriter<'a, REG, Gstr>; +impl<'a, REG> GstrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fault input glitch stretching is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gstr::Disabled) + } + #[doc = "Input fault signals are stretched to at least 2 IPBus clock cycles."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gstr::Enabled) + } +} +impl R { + #[doc = "Bits 0:7 - Fault Filter Period"] + #[inline(always)] + pub fn filt_per(&self) -> FiltPerR { + FiltPerR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Fault Filter Count"] + #[inline(always)] + pub fn filt_cnt(&self) -> FiltCntR { + FiltCntR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 15 - Fault Glitch Stretch Enable"] + #[inline(always)] + pub fn gstr(&self) -> GstrR { + GstrR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Fault Filter Period"] + #[inline(always)] + pub fn filt_per(&mut self) -> FiltPerW { + FiltPerW::new(self, 0) + } + #[doc = "Bits 8:10 - Fault Filter Count"] + #[inline(always)] + pub fn filt_cnt(&mut self) -> FiltCntW { + FiltCntW::new(self, 8) + } + #[doc = "Bit 15 - Fault Glitch Stretch Enable"] + #[inline(always)] + pub fn gstr(&mut self) -> GstrW { + GstrW::new(self, 15) + } +} +#[doc = "Fault Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ffilt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ffilt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ffilt0Spec; +impl crate::RegisterSpec for Ffilt0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`ffilt0::R`](R) reader structure"] +impl crate::Readable for Ffilt0Spec {} +#[doc = "`write(|w| ..)` method takes [`ffilt0::W`](W) writer structure"] +impl crate::Writable for Ffilt0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FFILT0 to value 0"] +impl crate::Resettable for Ffilt0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/fsts0.rs b/mcxa276-pac/src/flexpwm0/fsts0.rs new file mode 100644 index 000000000..9c16b9485 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/fsts0.rs @@ -0,0 +1,238 @@ +#[doc = "Register `FSTS0` reader"] +pub type R = crate::R; +#[doc = "Register `FSTS0` writer"] +pub type W = crate::W; +#[doc = "Fault Flags\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fflag { + #[doc = "0: No fault on the FAULTx pin."] + NoFlag = 0, + #[doc = "1: Fault on the FAULTx pin."] + Flag = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fflag) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fflag { + type Ux = u8; +} +impl crate::IsEnum for Fflag {} +#[doc = "Field `FFLAG` reader - Fault Flags"] +pub type FflagR = crate::FieldReader; +impl FflagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Fflag::NoFlag), + 1 => Some(Fflag::Flag), + _ => None, + } + } + #[doc = "No fault on the FAULTx pin."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Fflag::NoFlag + } + #[doc = "Fault on the FAULTx pin."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Fflag::Flag + } +} +#[doc = "Field `FFLAG` writer - Fault Flags"] +pub type FflagW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fflag>; +impl<'a, REG> FflagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No fault on the FAULTx pin."] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Fflag::NoFlag) + } + #[doc = "Fault on the FAULTx pin."] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Fflag::Flag) + } +} +#[doc = "Full Cycle\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ffull { + #[doc = "0: PWM outputs are not re-enabled at the start of a full cycle"] + PwmOutputsNotReenabled = 0, + #[doc = "1: PWM outputs are re-enabled at the start of a full cycle"] + PwmOutputsReenabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ffull) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ffull { + type Ux = u8; +} +impl crate::IsEnum for Ffull {} +#[doc = "Field `FFULL` reader - Full Cycle"] +pub type FfullR = crate::FieldReader; +impl FfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ffull::PwmOutputsNotReenabled), + 1 => Some(Ffull::PwmOutputsReenabled), + _ => None, + } + } + #[doc = "PWM outputs are not re-enabled at the start of a full cycle"] + #[inline(always)] + pub fn is_pwm_outputs_not_reenabled(&self) -> bool { + *self == Ffull::PwmOutputsNotReenabled + } + #[doc = "PWM outputs are re-enabled at the start of a full cycle"] + #[inline(always)] + pub fn is_pwm_outputs_reenabled(&self) -> bool { + *self == Ffull::PwmOutputsReenabled + } +} +#[doc = "Field `FFULL` writer - Full Cycle"] +pub type FfullW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ffull>; +impl<'a, REG> FfullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM outputs are not re-enabled at the start of a full cycle"] + #[inline(always)] + pub fn pwm_outputs_not_reenabled(self) -> &'a mut crate::W { + self.variant(Ffull::PwmOutputsNotReenabled) + } + #[doc = "PWM outputs are re-enabled at the start of a full cycle"] + #[inline(always)] + pub fn pwm_outputs_reenabled(self) -> &'a mut crate::W { + self.variant(Ffull::PwmOutputsReenabled) + } +} +#[doc = "Field `FFPIN` reader - Filtered Fault Pins"] +pub type FfpinR = crate::FieldReader; +#[doc = "Half Cycle Fault Recovery\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fhalf { + #[doc = "0: PWM outputs are not re-enabled at the start of a half cycle."] + PwmOutputsNotReenabled = 0, + #[doc = "1: PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."] + PwmOutputsReenabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fhalf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fhalf { + type Ux = u8; +} +impl crate::IsEnum for Fhalf {} +#[doc = "Field `FHALF` reader - Half Cycle Fault Recovery"] +pub type FhalfR = crate::FieldReader; +impl FhalfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Fhalf::PwmOutputsNotReenabled), + 1 => Some(Fhalf::PwmOutputsReenabled), + _ => None, + } + } + #[doc = "PWM outputs are not re-enabled at the start of a half cycle."] + #[inline(always)] + pub fn is_pwm_outputs_not_reenabled(&self) -> bool { + *self == Fhalf::PwmOutputsNotReenabled + } + #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."] + #[inline(always)] + pub fn is_pwm_outputs_reenabled(&self) -> bool { + *self == Fhalf::PwmOutputsReenabled + } +} +#[doc = "Field `FHALF` writer - Half Cycle Fault Recovery"] +pub type FhalfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fhalf>; +impl<'a, REG> FhalfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM outputs are not re-enabled at the start of a half cycle."] + #[inline(always)] + pub fn pwm_outputs_not_reenabled(self) -> &'a mut crate::W { + self.variant(Fhalf::PwmOutputsNotReenabled) + } + #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."] + #[inline(always)] + pub fn pwm_outputs_reenabled(self) -> &'a mut crate::W { + self.variant(Fhalf::PwmOutputsReenabled) + } +} +impl R { + #[doc = "Bits 0:3 - Fault Flags"] + #[inline(always)] + pub fn fflag(&self) -> FflagR { + FflagR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Full Cycle"] + #[inline(always)] + pub fn ffull(&self) -> FfullR { + FfullR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Filtered Fault Pins"] + #[inline(always)] + pub fn ffpin(&self) -> FfpinR { + FfpinR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Half Cycle Fault Recovery"] + #[inline(always)] + pub fn fhalf(&self) -> FhalfR { + FhalfR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Fault Flags"] + #[inline(always)] + pub fn fflag(&mut self) -> FflagW { + FflagW::new(self, 0) + } + #[doc = "Bits 4:7 - Full Cycle"] + #[inline(always)] + pub fn ffull(&mut self) -> FfullW { + FfullW::new(self, 4) + } + #[doc = "Bits 12:15 - Half Cycle Fault Recovery"] + #[inline(always)] + pub fn fhalf(&mut self) -> FhalfW { + FhalfW::new(self, 12) + } +} +#[doc = "Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fsts0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsts0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fsts0Spec; +impl crate::RegisterSpec for Fsts0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`fsts0::R`](R) reader structure"] +impl crate::Readable for Fsts0Spec {} +#[doc = "`write(|w| ..)` method takes [`fsts0::W`](W) writer structure"] +impl crate::Writable for Fsts0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FSTS0 to value 0"] +impl crate::Resettable for Fsts0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/ftst0.rs b/mcxa276-pac/src/flexpwm0/ftst0.rs new file mode 100644 index 000000000..11b12404d --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/ftst0.rs @@ -0,0 +1,84 @@ +#[doc = "Register `FTST0` reader"] +pub type R = crate::R; +#[doc = "Register `FTST0` writer"] +pub type W = crate::W; +#[doc = "Fault Test\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ftest { + #[doc = "0: No fault"] + NoFault = 0, + #[doc = "1: Cause a simulated fault"] + Fault = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ftest) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FTEST` reader - Fault Test"] +pub type FtestR = crate::BitReader; +impl FtestR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ftest { + match self.bits { + false => Ftest::NoFault, + true => Ftest::Fault, + } + } + #[doc = "No fault"] + #[inline(always)] + pub fn is_no_fault(&self) -> bool { + *self == Ftest::NoFault + } + #[doc = "Cause a simulated fault"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + *self == Ftest::Fault + } +} +#[doc = "Field `FTEST` writer - Fault Test"] +pub type FtestW<'a, REG> = crate::BitWriter<'a, REG, Ftest>; +impl<'a, REG> FtestW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No fault"] + #[inline(always)] + pub fn no_fault(self) -> &'a mut crate::W { + self.variant(Ftest::NoFault) + } + #[doc = "Cause a simulated fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut crate::W { + self.variant(Ftest::Fault) + } +} +impl R { + #[doc = "Bit 0 - Fault Test"] + #[inline(always)] + pub fn ftest(&self) -> FtestR { + FtestR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Fault Test"] + #[inline(always)] + pub fn ftest(&mut self) -> FtestW { + FtestW::new(self, 0) + } +} +#[doc = "Fault Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ftst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ftst0Spec; +impl crate::RegisterSpec for Ftst0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`ftst0::R`](R) reader structure"] +impl crate::Readable for Ftst0Spec {} +#[doc = "`write(|w| ..)` method takes [`ftst0::W`](W) writer structure"] +impl crate::Writable for Ftst0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FTST0 to value 0"] +impl crate::Resettable for Ftst0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/mask.rs b/mcxa276-pac/src/flexpwm0/mask.rs new file mode 100644 index 000000000..8a8ec7566 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/mask.rs @@ -0,0 +1,70 @@ +#[doc = "Register `MASK` reader"] +pub type R = crate::R; +#[doc = "Register `MASK` writer"] +pub type W = crate::W; +#[doc = "Field `MASKX` reader - PWM_X Masks"] +pub type MaskxR = crate::FieldReader; +#[doc = "Field `MASKX` writer - PWM_X Masks"] +pub type MaskxW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `MASKB` reader - PWM_B Masks"] +pub type MaskbR = crate::FieldReader; +#[doc = "Field `MASKB` writer - PWM_B Masks"] +pub type MaskbW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `MASKA` reader - PWM_A Masks"] +pub type MaskaR = crate::FieldReader; +#[doc = "Field `MASKA` writer - PWM_A Masks"] +pub type MaskaW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `UPDATE_MASK` writer - Update Mask Bits Immediately"] +pub type UpdateMaskW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - PWM_X Masks"] + #[inline(always)] + pub fn maskx(&self) -> MaskxR { + MaskxR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - PWM_B Masks"] + #[inline(always)] + pub fn maskb(&self) -> MaskbR { + MaskbR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - PWM_A Masks"] + #[inline(always)] + pub fn maska(&self) -> MaskaR { + MaskaR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - PWM_X Masks"] + #[inline(always)] + pub fn maskx(&mut self) -> MaskxW { + MaskxW::new(self, 0) + } + #[doc = "Bits 4:7 - PWM_B Masks"] + #[inline(always)] + pub fn maskb(&mut self) -> MaskbW { + MaskbW::new(self, 4) + } + #[doc = "Bits 8:11 - PWM_A Masks"] + #[inline(always)] + pub fn maska(&mut self) -> MaskaW { + MaskaW::new(self, 8) + } + #[doc = "Bits 12:15 - Update Mask Bits Immediately"] + #[inline(always)] + pub fn update_mask(&mut self) -> UpdateMaskW { + UpdateMaskW::new(self, 12) + } +} +#[doc = "Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MaskSpec; +impl crate::RegisterSpec for MaskSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`mask::R`](R) reader structure"] +impl crate::Readable for MaskSpec {} +#[doc = "`write(|w| ..)` method takes [`mask::W`](W) writer structure"] +impl crate::Writable for MaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MaskSpec {} diff --git a/mcxa276-pac/src/flexpwm0/mctrl.rs b/mcxa276-pac/src/flexpwm0/mctrl.rs new file mode 100644 index 000000000..4ab080fde --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/mctrl.rs @@ -0,0 +1,245 @@ +#[doc = "Register `MCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MCTRL` writer"] +pub type W = crate::W; +#[doc = "Load Okay\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ldok { + #[doc = "0: Do not load new values."] + Disabled = 0, + #[doc = "1: Load prescaler, modulus, and PWM values of the corresponding submodule."] + Enabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ldok) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ldok { + type Ux = u8; +} +impl crate::IsEnum for Ldok {} +#[doc = "Field `LDOK` reader - Load Okay"] +pub type LdokR = crate::FieldReader; +impl LdokR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ldok::Disabled), + 1 => Some(Ldok::Enabled), + _ => None, + } + } + #[doc = "Do not load new values."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ldok::Disabled + } + #[doc = "Load prescaler, modulus, and PWM values of the corresponding submodule."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ldok::Enabled + } +} +#[doc = "Field `LDOK` writer - Load Okay"] +pub type LdokW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldok>; +impl<'a, REG> LdokW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do not load new values."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ldok::Disabled) + } + #[doc = "Load prescaler, modulus, and PWM values of the corresponding submodule."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ldok::Enabled) + } +} +#[doc = "Field `CLDOK` reader - Clear Load Okay"] +pub type CldokR = crate::FieldReader; +#[doc = "Field `CLDOK` writer - Clear Load Okay"] +pub type CldokW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Run\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Run { + #[doc = "0: PWM counter is stopped, but PWM outputs hold the current state."] + Disabled = 0, + #[doc = "1: PWM counter is started in the corresponding submodule."] + Enabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Run) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Run { + type Ux = u8; +} +impl crate::IsEnum for Run {} +#[doc = "Field `RUN` reader - Run"] +pub type RunR = crate::FieldReader; +impl RunR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Run::Disabled), + 1 => Some(Run::Enabled), + _ => None, + } + } + #[doc = "PWM counter is stopped, but PWM outputs hold the current state."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Run::Disabled + } + #[doc = "PWM counter is started in the corresponding submodule."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Run::Enabled + } +} +#[doc = "Field `RUN` writer - Run"] +pub type RunW<'a, REG> = crate::FieldWriter<'a, REG, 4, Run>; +impl<'a, REG> RunW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM counter is stopped, but PWM outputs hold the current state."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Run::Disabled) + } + #[doc = "PWM counter is started in the corresponding submodule."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Run::Enabled) + } +} +#[doc = "Current Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ipol { + #[doc = "0: PWM23 is used to generate complementary PWM pair in the corresponding submodule."] + Pwm23 = 0, + #[doc = "1: PWM45 is used to generate complementary PWM pair in the corresponding submodule."] + Pwm45 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ipol) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ipol { + type Ux = u8; +} +impl crate::IsEnum for Ipol {} +#[doc = "Field `IPOL` reader - Current Polarity"] +pub type IpolR = crate::FieldReader; +impl IpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ipol::Pwm23), + 1 => Some(Ipol::Pwm45), + _ => None, + } + } + #[doc = "PWM23 is used to generate complementary PWM pair in the corresponding submodule."] + #[inline(always)] + pub fn is_pwm23(&self) -> bool { + *self == Ipol::Pwm23 + } + #[doc = "PWM45 is used to generate complementary PWM pair in the corresponding submodule."] + #[inline(always)] + pub fn is_pwm45(&self) -> bool { + *self == Ipol::Pwm45 + } +} +#[doc = "Field `IPOL` writer - Current Polarity"] +pub type IpolW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ipol>; +impl<'a, REG> IpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM23 is used to generate complementary PWM pair in the corresponding submodule."] + #[inline(always)] + pub fn pwm23(self) -> &'a mut crate::W { + self.variant(Ipol::Pwm23) + } + #[doc = "PWM45 is used to generate complementary PWM pair in the corresponding submodule."] + #[inline(always)] + pub fn pwm45(self) -> &'a mut crate::W { + self.variant(Ipol::Pwm45) + } +} +impl R { + #[doc = "Bits 0:3 - Load Okay"] + #[inline(always)] + pub fn ldok(&self) -> LdokR { + LdokR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Clear Load Okay"] + #[inline(always)] + pub fn cldok(&self) -> CldokR { + CldokR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Run"] + #[inline(always)] + pub fn run(&self) -> RunR { + RunR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Current Polarity"] + #[inline(always)] + pub fn ipol(&self) -> IpolR { + IpolR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Load Okay"] + #[inline(always)] + pub fn ldok(&mut self) -> LdokW { + LdokW::new(self, 0) + } + #[doc = "Bits 4:7 - Clear Load Okay"] + #[inline(always)] + pub fn cldok(&mut self) -> CldokW { + CldokW::new(self, 4) + } + #[doc = "Bits 8:11 - Run"] + #[inline(always)] + pub fn run(&mut self) -> RunW { + RunW::new(self, 8) + } + #[doc = "Bits 12:15 - Current Polarity"] + #[inline(always)] + pub fn ipol(&mut self) -> IpolW { + IpolW::new(self, 12) + } +} +#[doc = "Master Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MctrlSpec; +impl crate::RegisterSpec for MctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`mctrl::R`](R) reader structure"] +impl crate::Readable for MctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mctrl::W`](W) writer structure"] +impl crate::Writable for MctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCTRL to value 0"] +impl crate::Resettable for MctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/mctrl2.rs b/mcxa276-pac/src/flexpwm0/mctrl2.rs new file mode 100644 index 000000000..f8a69d710 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/mctrl2.rs @@ -0,0 +1,213 @@ +#[doc = "Register `MCTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `MCTRL2` writer"] +pub type W = crate::W; +#[doc = "Write protect\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wrprot { + #[doc = "0: Write protection off (default)."] + Disabled = 0, + #[doc = "1: Write protection on."] + Enabled = 1, + #[doc = "2: Write protection off and locked until chip reset."] + DisabledLocked = 2, + #[doc = "3: Write protection on and locked until chip reset."] + EnabledLocked = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wrprot) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wrprot { + type Ux = u8; +} +impl crate::IsEnum for Wrprot {} +#[doc = "Field `WRPROT` reader - Write protect"] +pub type WrprotR = crate::FieldReader; +impl WrprotR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wrprot { + match self.bits { + 0 => Wrprot::Disabled, + 1 => Wrprot::Enabled, + 2 => Wrprot::DisabledLocked, + 3 => Wrprot::EnabledLocked, + _ => unreachable!(), + } + } + #[doc = "Write protection off (default)."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wrprot::Disabled + } + #[doc = "Write protection on."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wrprot::Enabled + } + #[doc = "Write protection off and locked until chip reset."] + #[inline(always)] + pub fn is_disabled_locked(&self) -> bool { + *self == Wrprot::DisabledLocked + } + #[doc = "Write protection on and locked until chip reset."] + #[inline(always)] + pub fn is_enabled_locked(&self) -> bool { + *self == Wrprot::EnabledLocked + } +} +#[doc = "Field `WRPROT` writer - Write protect"] +pub type WrprotW<'a, REG> = crate::FieldWriter<'a, REG, 2, Wrprot, crate::Safe>; +impl<'a, REG> WrprotW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Write protection off (default)."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wrprot::Disabled) + } + #[doc = "Write protection on."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wrprot::Enabled) + } + #[doc = "Write protection off and locked until chip reset."] + #[inline(always)] + pub fn disabled_locked(self) -> &'a mut crate::W { + self.variant(Wrprot::DisabledLocked) + } + #[doc = "Write protection on and locked until chip reset."] + #[inline(always)] + pub fn enabled_locked(self) -> &'a mut crate::W { + self.variant(Wrprot::EnabledLocked) + } +} +#[doc = "Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum StretchCntPrsc { + #[doc = "0: Stretch count is zero, no stretch."] + Disabled = 0, + #[doc = "1: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period."] + Enabled = 1, + #[doc = "2: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period."] + DisabledLocked = 2, + #[doc = "3: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period."] + EnabledLocked = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: StretchCntPrsc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for StretchCntPrsc { + type Ux = u8; +} +impl crate::IsEnum for StretchCntPrsc {} +#[doc = "Field `STRETCH_CNT_PRSC` reader - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] +pub type StretchCntPrscR = crate::FieldReader; +impl StretchCntPrscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StretchCntPrsc { + match self.bits { + 0 => StretchCntPrsc::Disabled, + 1 => StretchCntPrsc::Enabled, + 2 => StretchCntPrsc::DisabledLocked, + 3 => StretchCntPrsc::EnabledLocked, + _ => unreachable!(), + } + } + #[doc = "Stretch count is zero, no stretch."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == StretchCntPrsc::Disabled + } + #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == StretchCntPrsc::Enabled + } + #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period."] + #[inline(always)] + pub fn is_disabled_locked(&self) -> bool { + *self == StretchCntPrsc::DisabledLocked + } + #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period."] + #[inline(always)] + pub fn is_enabled_locked(&self) -> bool { + *self == StretchCntPrsc::EnabledLocked + } +} +#[doc = "Field `STRETCH_CNT_PRSC` writer - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] +pub type StretchCntPrscW<'a, REG> = crate::FieldWriter<'a, REG, 2, StretchCntPrsc, crate::Safe>; +impl<'a, REG> StretchCntPrscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Stretch count is zero, no stretch."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(StretchCntPrsc::Disabled) + } + #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(StretchCntPrsc::Enabled) + } + #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period."] + #[inline(always)] + pub fn disabled_locked(self) -> &'a mut crate::W { + self.variant(StretchCntPrsc::DisabledLocked) + } + #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period."] + #[inline(always)] + pub fn enabled_locked(self) -> &'a mut crate::W { + self.variant(StretchCntPrsc::EnabledLocked) + } +} +impl R { + #[doc = "Bits 2:3 - Write protect"] + #[inline(always)] + pub fn wrprot(&self) -> WrprotR { + WrprotR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 6:7 - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] + #[inline(always)] + pub fn stretch_cnt_prsc(&self) -> StretchCntPrscR { + StretchCntPrscR::new(((self.bits >> 6) & 3) as u8) + } +} +impl W { + #[doc = "Bits 2:3 - Write protect"] + #[inline(always)] + pub fn wrprot(&mut self) -> WrprotW { + WrprotW::new(self, 2) + } + #[doc = "Bits 6:7 - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] + #[inline(always)] + pub fn stretch_cnt_prsc(&mut self) -> StretchCntPrscW { + StretchCntPrscW::new(self, 6) + } +} +#[doc = "Master Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mctrl2Spec; +impl crate::RegisterSpec for Mctrl2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`mctrl2::R`](R) reader structure"] +impl crate::Readable for Mctrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`mctrl2::W`](W) writer structure"] +impl crate::Writable for Mctrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCTRL2 to value 0"] +impl crate::Resettable for Mctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/outen.rs b/mcxa276-pac/src/flexpwm0/outen.rs new file mode 100644 index 000000000..a69227e19 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/outen.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUTEN` reader"] +pub type R = crate::R; +#[doc = "Register `OUTEN` writer"] +pub type W = crate::W; +#[doc = "Field `PWMX_EN` reader - PWM_X Output Enables"] +pub type PwmxEnR = crate::FieldReader; +#[doc = "Field `PWMX_EN` writer - PWM_X Output Enables"] +pub type PwmxEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PWMB_EN` reader - PWM_B Output Enables"] +pub type PwmbEnR = crate::FieldReader; +#[doc = "Field `PWMB_EN` writer - PWM_B Output Enables"] +pub type PwmbEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PWMA_EN` reader - PWM_A Output Enables"] +pub type PwmaEnR = crate::FieldReader; +#[doc = "Field `PWMA_EN` writer - PWM_A Output Enables"] +pub type PwmaEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - PWM_X Output Enables"] + #[inline(always)] + pub fn pwmx_en(&self) -> PwmxEnR { + PwmxEnR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - PWM_B Output Enables"] + #[inline(always)] + pub fn pwmb_en(&self) -> PwmbEnR { + PwmbEnR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - PWM_A Output Enables"] + #[inline(always)] + pub fn pwma_en(&self) -> PwmaEnR { + PwmaEnR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - PWM_X Output Enables"] + #[inline(always)] + pub fn pwmx_en(&mut self) -> PwmxEnW { + PwmxEnW::new(self, 0) + } + #[doc = "Bits 4:7 - PWM_B Output Enables"] + #[inline(always)] + pub fn pwmb_en(&mut self) -> PwmbEnW { + PwmbEnW::new(self, 4) + } + #[doc = "Bits 8:11 - PWM_A Output Enables"] + #[inline(always)] + pub fn pwma_en(&mut self) -> PwmaEnW { + PwmaEnW::new(self, 8) + } +} +#[doc = "Output Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OutenSpec; +impl crate::RegisterSpec for OutenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`outen::R`](R) reader structure"] +impl crate::Readable for OutenSpec {} +#[doc = "`write(|w| ..)` method takes [`outen::W`](W) writer structure"] +impl crate::Writable for OutenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets OUTEN to value 0"] +impl crate::Resettable for OutenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0captcompx.rs b/mcxa276-pac/src/flexpwm0/sm0captcompx.rs new file mode 100644 index 000000000..90a7ac13d --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0captcompx.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SM0CAPTCOMPX` reader"] +pub type R = crate::R; +#[doc = "Register `SM0CAPTCOMPX` writer"] +pub type W = crate::W; +#[doc = "Field `EDGCMPX` reader - Edge Compare X"] +pub type EdgcmpxR = crate::FieldReader; +#[doc = "Field `EDGCMPX` writer - Edge Compare X"] +pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EDGCNTX` reader - Edge Counter X"] +pub type EdgcntxR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&self) -> EdgcmpxR { + EdgcmpxR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Edge Counter X"] + #[inline(always)] + pub fn edgcntx(&self) -> EdgcntxR { + EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&mut self) -> EdgcmpxW { + EdgcmpxW::new(self, 0) + } +} +#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0captcompxSpec; +impl crate::RegisterSpec for Sm0captcompxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0captcompx::R`](R) reader structure"] +impl crate::Readable for Sm0captcompxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0captcompx::W`](W) writer structure"] +impl crate::Writable for Sm0captcompxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0CAPTCOMPX to value 0"] +impl crate::Resettable for Sm0captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm0captctrlx.rs new file mode 100644 index 000000000..fa6ebc270 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0captctrlx.rs @@ -0,0 +1,493 @@ +#[doc = "Register `SM0CAPTCTRLX` reader"] +pub type R = crate::R; +#[doc = "Register `SM0CAPTCTRLX` writer"] +pub type W = crate::W; +#[doc = "Arm X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Armx { + #[doc = "0: Input capture operation is disabled."] + Disabled = 0, + #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Armx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARMX` reader - Arm X"] +pub type ArmxR = crate::BitReader; +impl ArmxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Armx { + match self.bits { + false => Armx::Disabled, + true => Armx::Enabled, + } + } + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Armx::Disabled + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Armx::Enabled + } +} +#[doc = "Field `ARMX` writer - Arm X"] +pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; +impl<'a, REG> ArmxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Armx::Disabled) + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Armx::Enabled) + } +} +#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oneshotx { + #[doc = "0: Free Running"] + FreeRunning = 0, + #[doc = "1: One Shot"] + OneShot = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oneshotx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] +pub type OneshotxR = crate::BitReader; +impl OneshotxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oneshotx { + match self.bits { + false => Oneshotx::FreeRunning, + true => Oneshotx::OneShot, + } + } + #[doc = "Free Running"] + #[inline(always)] + pub fn is_free_running(&self) -> bool { + *self == Oneshotx::FreeRunning + } + #[doc = "One Shot"] + #[inline(always)] + pub fn is_one_shot(&self) -> bool { + *self == Oneshotx::OneShot + } +} +#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] +pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; +impl<'a, REG> OneshotxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Free Running"] + #[inline(always)] + pub fn free_running(self) -> &'a mut crate::W { + self.variant(Oneshotx::FreeRunning) + } + #[doc = "One Shot"] + #[inline(always)] + pub fn one_shot(self) -> &'a mut crate::W { + self.variant(Oneshotx::OneShot) + } +} +#[doc = "Edge X 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx0 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx0 { + type Ux = u8; +} +impl crate::IsEnum for Edgx0 {} +#[doc = "Field `EDGX0` reader - Edge X 0"] +pub type Edgx0R = crate::FieldReader; +impl Edgx0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx0 { + match self.bits { + 0 => Edgx0::Disabled, + 1 => Edgx0::FallingEdge, + 2 => Edgx0::RisingEdge, + 3 => Edgx0::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx0::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx0::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx0::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx0::AnyEdge + } +} +#[doc = "Field `EDGX0` writer - Edge X 0"] +pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; +impl<'a, REG> Edgx0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx0::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::AnyEdge) + } +} +#[doc = "Edge X 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx1 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx1 { + type Ux = u8; +} +impl crate::IsEnum for Edgx1 {} +#[doc = "Field `EDGX1` reader - Edge X 1"] +pub type Edgx1R = crate::FieldReader; +impl Edgx1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx1 { + match self.bits { + 0 => Edgx1::Disabled, + 1 => Edgx1::FallingEdge, + 2 => Edgx1::RisingEdge, + 3 => Edgx1::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx1::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx1::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx1::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx1::AnyEdge + } +} +#[doc = "Field `EDGX1` writer - Edge X 1"] +pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; +impl<'a, REG> Edgx1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx1::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::AnyEdge) + } +} +#[doc = "Input Select X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum InpSelx { + #[doc = "0: Raw PWM_X input signal selected as source."] + PwmX = 0, + #[doc = "1: Edge Counter"] + EdgeCounter = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: InpSelx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INP_SELX` reader - Input Select X"] +pub type InpSelxR = crate::BitReader; +impl InpSelxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InpSelx { + match self.bits { + false => InpSelx::PwmX, + true => InpSelx::EdgeCounter, + } + } + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InpSelx::PwmX + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn is_edge_counter(&self) -> bool { + *self == InpSelx::EdgeCounter + } +} +#[doc = "Field `INP_SELX` writer - Input Select X"] +pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; +impl<'a, REG> InpSelxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InpSelx::PwmX) + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn edge_counter(self) -> &'a mut crate::W { + self.variant(InpSelx::EdgeCounter) + } +} +#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EdgcntxEn { + #[doc = "0: Edge counter disabled and held in reset"] + Disabled = 0, + #[doc = "1: Edge counter enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EdgcntxEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] +pub type EdgcntxEnR = crate::BitReader; +impl EdgcntxEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EdgcntxEn { + match self.bits { + false => EdgcntxEn::Disabled, + true => EdgcntxEn::Enabled, + } + } + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EdgcntxEn::Disabled + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EdgcntxEn::Enabled + } +} +#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] +pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; +impl<'a, REG> EdgcntxEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Disabled) + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Enabled) + } +} +#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] +pub type CfxwmR = crate::FieldReader; +#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] +pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] +pub type Cx0cntR = crate::FieldReader; +#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] +pub type Cx1cntR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&self) -> ArmxR { + ArmxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&self) -> OneshotxR { + OneshotxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&self) -> Edgx0R { + Edgx0R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&self) -> Edgx1R { + Edgx1R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&self) -> InpSelxR { + InpSelxR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&self) -> EdgcntxEnR { + EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&self) -> CfxwmR { + CfxwmR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] + #[inline(always)] + pub fn cx0cnt(&self) -> Cx0cntR { + Cx0cntR::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] + #[inline(always)] + pub fn cx1cnt(&self) -> Cx1cntR { + Cx1cntR::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&mut self) -> ArmxW { + ArmxW::new(self, 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&mut self) -> OneshotxW { + OneshotxW::new(self, 1) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&mut self) -> Edgx0W { + Edgx0W::new(self, 2) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&mut self) -> Edgx1W { + Edgx1W::new(self, 4) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&mut self) -> InpSelxW { + InpSelxW::new(self, 6) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&mut self) -> EdgcntxEnW { + EdgcntxEnW::new(self, 7) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&mut self) -> CfxwmW { + CfxwmW::new(self, 8) + } +} +#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0captctrlxSpec; +impl crate::RegisterSpec for Sm0captctrlxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0captctrlx::R`](R) reader structure"] +impl crate::Readable for Sm0captctrlxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0captctrlx::W`](W) writer structure"] +impl crate::Writable for Sm0captctrlxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0CAPTCTRLX to value 0"] +impl crate::Resettable for Sm0captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm0captfiltx.rs new file mode 100644 index 000000000..4457d33d6 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0captfiltx.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SM0CAPTFILTX` reader"] +pub type R = crate::R; +#[doc = "Register `SM0CAPTFILTX` writer"] +pub type W = crate::W; +#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] +pub type CaptxFiltPerR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] +pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] +pub type CaptxFiltCntR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] +pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&self) -> CaptxFiltPerR { + CaptxFiltPerR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { + CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { + CaptxFiltPerW::new(self, 0) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { + CaptxFiltCntW::new(self, 8) + } +} +#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0captfiltxSpec; +impl crate::RegisterSpec for Sm0captfiltxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0captfiltx::R`](R) reader structure"] +impl crate::Readable for Sm0captfiltxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0captfiltx::W`](W) writer structure"] +impl crate::Writable for Sm0captfiltxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0CAPTFILTX to value 0"] +impl crate::Resettable for Sm0captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cnt.rs b/mcxa276-pac/src/flexpwm0/sm0cnt.rs new file mode 100644 index 000000000..628826230 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0cnt.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM0CNT` reader"] +pub type R = crate::R; +#[doc = "Field `CNT` reader - Counter Register Bits"] +pub type CntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Counter Register Bits"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0cntSpec; +impl crate::RegisterSpec for Sm0cntSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0cnt::R`](R) reader structure"] +impl crate::Readable for Sm0cntSpec {} +#[doc = "`reset()` method sets SM0CNT to value 0"] +impl crate::Resettable for Sm0cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0ctrl.rs b/mcxa276-pac/src/flexpwm0/sm0ctrl.rs new file mode 100644 index 000000000..123bd6598 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0ctrl.rs @@ -0,0 +1,871 @@ +#[doc = "Register `SM0CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM0CTRL` writer"] +pub type W = crate::W; +#[doc = "Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblen { + #[doc = "0: Double switching disabled."] + Disabled = 0, + #[doc = "1: Double switching enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLEN` reader - Double Switching Enable"] +pub type DblenR = crate::BitReader; +impl DblenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblen { + match self.bits { + false => Dblen::Disabled, + true => Dblen::Enabled, + } + } + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblen::Disabled + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblen::Enabled + } +} +#[doc = "Field `DBLEN` writer - Double Switching Enable"] +pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; +impl<'a, REG> DblenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblen::Disabled) + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblen::Enabled) + } +} +#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblx { + #[doc = "0: PWM_X double pulse disabled."] + Disabled = 0, + #[doc = "1: PWM_X double pulse enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] +pub type DblxR = crate::BitReader; +impl DblxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblx { + match self.bits { + false => Dblx::Disabled, + true => Dblx::Enabled, + } + } + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblx::Disabled + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblx::Enabled + } +} +#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] +pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; +impl<'a, REG> DblxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblx::Disabled) + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblx::Enabled) + } +} +#[doc = "Load Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldmod { + #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + NextPwmReload = 0, + #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + MtctrlLdokSet = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldmod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDMOD` reader - Load Mode Select"] +pub type LdmodR = crate::BitReader; +impl LdmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldmod { + match self.bits { + false => Ldmod::NextPwmReload, + true => Ldmod::MtctrlLdokSet, + } + } + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn is_next_pwm_reload(&self) -> bool { + *self == Ldmod::NextPwmReload + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn is_mtctrl_ldok_set(&self) -> bool { + *self == Ldmod::MtctrlLdokSet + } +} +#[doc = "Field `LDMOD` writer - Load Mode Select"] +pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; +impl<'a, REG> LdmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn next_pwm_reload(self) -> &'a mut crate::W { + self.variant(Ldmod::NextPwmReload) + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { + self.variant(Ldmod::MtctrlLdokSet) + } +} +#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Split { + #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + Disabled = 0, + #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Split) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitR = crate::BitReader; +impl SplitR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Split { + match self.bits { + false => Split::Disabled, + true => Split::Enabled, + } + } + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Split::Disabled + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Split::Enabled + } +} +#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; +impl<'a, REG> SplitW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Split::Disabled) + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Split::Enabled) + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Prsc { + #[doc = "0: Prescaler 1"] + One = 0, + #[doc = "1: Prescaler 2"] + Two = 1, + #[doc = "2: Prescaler 4"] + Four = 2, + #[doc = "3: Prescaler 8"] + Eight = 3, + #[doc = "4: Prescaler 16"] + Sixteen = 4, + #[doc = "5: Prescaler 32"] + Thirtytwo = 5, + #[doc = "6: Prescaler 64"] + Sixtyfour = 6, + #[doc = "7: Prescaler 128"] + Hundredtwentyeight = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Prsc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Prsc { + type Ux = u8; +} +impl crate::IsEnum for Prsc {} +#[doc = "Field `PRSC` reader - Prescaler"] +pub type PrscR = crate::FieldReader; +impl PrscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prsc { + match self.bits { + 0 => Prsc::One, + 1 => Prsc::Two, + 2 => Prsc::Four, + 3 => Prsc::Eight, + 4 => Prsc::Sixteen, + 5 => Prsc::Thirtytwo, + 6 => Prsc::Sixtyfour, + 7 => Prsc::Hundredtwentyeight, + _ => unreachable!(), + } + } + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Prsc::One + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn is_two(&self) -> bool { + *self == Prsc::Two + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn is_four(&self) -> bool { + *self == Prsc::Four + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn is_eight(&self) -> bool { + *self == Prsc::Eight + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn is_sixteen(&self) -> bool { + *self == Prsc::Sixteen + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn is_thirtytwo(&self) -> bool { + *self == Prsc::Thirtytwo + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn is_sixtyfour(&self) -> bool { + *self == Prsc::Sixtyfour + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn is_hundredtwentyeight(&self) -> bool { + *self == Prsc::Hundredtwentyeight + } +} +#[doc = "Field `PRSC` writer - Prescaler"] +pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; +impl<'a, REG> PrscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn one(self) -> &'a mut crate::W { + self.variant(Prsc::One) + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn two(self) -> &'a mut crate::W { + self.variant(Prsc::Two) + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn four(self) -> &'a mut crate::W { + self.variant(Prsc::Four) + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn eight(self) -> &'a mut crate::W { + self.variant(Prsc::Eight) + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn sixteen(self) -> &'a mut crate::W { + self.variant(Prsc::Sixteen) + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn thirtytwo(self) -> &'a mut crate::W { + self.variant(Prsc::Thirtytwo) + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn sixtyfour(self) -> &'a mut crate::W { + self.variant(Prsc::Sixtyfour) + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn hundredtwentyeight(self) -> &'a mut crate::W { + self.variant(Prsc::Hundredtwentyeight) + } +} +#[doc = "Compare Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Compmode { + #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + EqualTo = 0, + #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + EqualToOrGreaterThan = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Compmode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPMODE` reader - Compare Mode"] +pub type CompmodeR = crate::BitReader; +impl CompmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Compmode { + match self.bits { + false => Compmode::EqualTo, + true => Compmode::EqualToOrGreaterThan, + } + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn is_equal_to(&self) -> bool { + *self == Compmode::EqualTo + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn is_equal_to_or_greater_than(&self) -> bool { + *self == Compmode::EqualToOrGreaterThan + } +} +#[doc = "Field `COMPMODE` writer - Compare Mode"] +pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; +impl<'a, REG> CompmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn equal_to(self) -> &'a mut crate::W { + self.variant(Compmode::EqualTo) + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { + self.variant(Compmode::EqualToOrGreaterThan) + } +} +#[doc = "Field `DT` reader - Deadtime"] +pub type DtR = crate::FieldReader; +#[doc = "Full Cycle Reload\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Full { + #[doc = "0: Full-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Full-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FULL` reader - Full Cycle Reload"] +pub type FullR = crate::BitReader; +impl FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Full { + match self.bits { + false => Full::Disabled, + true => Full::Enabled, + } + } + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Full::Disabled + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Full::Enabled + } +} +#[doc = "Field `FULL` writer - Full Cycle Reload"] +pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; +impl<'a, REG> FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Full::Disabled) + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Full::Enabled) + } +} +#[doc = "Half Cycle Reload\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Half { + #[doc = "0: Half-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Half-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Half) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALF` reader - Half Cycle Reload"] +pub type HalfR = crate::BitReader; +impl HalfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Half { + match self.bits { + false => Half::Disabled, + true => Half::Enabled, + } + } + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Half::Disabled + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Half::Enabled + } +} +#[doc = "Field `HALF` writer - Half Cycle Reload"] +pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; +impl<'a, REG> HalfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Half::Disabled) + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Half::Enabled) + } +} +#[doc = "Load Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ldfq { + #[doc = "0: Every PWM opportunity"] + Everypwm = 0, + #[doc = "1: Every 2 PWM opportunities"] + Every2pwm = 1, + #[doc = "2: Every 3 PWM opportunities"] + Every3pwm = 2, + #[doc = "3: Every 4 PWM opportunities"] + Every4pwm = 3, + #[doc = "4: Every 5 PWM opportunities"] + Every5pwm = 4, + #[doc = "5: Every 6 PWM opportunities"] + Every6pwm = 5, + #[doc = "6: Every 7 PWM opportunities"] + Every7pwm = 6, + #[doc = "7: Every 8 PWM opportunities"] + Every8pwm = 7, + #[doc = "8: Every 9 PWM opportunities"] + Every9pwm = 8, + #[doc = "9: Every 10 PWM opportunities"] + Every10pwm = 9, + #[doc = "10: Every 11 PWM opportunities"] + Every11pwm = 10, + #[doc = "11: Every 12 PWM opportunities"] + Every12pwm = 11, + #[doc = "12: Every 13 PWM opportunities"] + Every13pwm = 12, + #[doc = "13: Every 14 PWM opportunities"] + Every14pwm = 13, + #[doc = "14: Every 15 PWM opportunities"] + Every15pwm = 14, + #[doc = "15: Every 16 PWM opportunities"] + Every16pwm = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ldfq) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ldfq { + type Ux = u8; +} +impl crate::IsEnum for Ldfq {} +#[doc = "Field `LDFQ` reader - Load Frequency"] +pub type LdfqR = crate::FieldReader; +impl LdfqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldfq { + match self.bits { + 0 => Ldfq::Everypwm, + 1 => Ldfq::Every2pwm, + 2 => Ldfq::Every3pwm, + 3 => Ldfq::Every4pwm, + 4 => Ldfq::Every5pwm, + 5 => Ldfq::Every6pwm, + 6 => Ldfq::Every7pwm, + 7 => Ldfq::Every8pwm, + 8 => Ldfq::Every9pwm, + 9 => Ldfq::Every10pwm, + 10 => Ldfq::Every11pwm, + 11 => Ldfq::Every12pwm, + 12 => Ldfq::Every13pwm, + 13 => Ldfq::Every14pwm, + 14 => Ldfq::Every15pwm, + 15 => Ldfq::Every16pwm, + _ => unreachable!(), + } + } + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Ldfq::Everypwm + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn is_every2pwm(&self) -> bool { + *self == Ldfq::Every2pwm + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn is_every3pwm(&self) -> bool { + *self == Ldfq::Every3pwm + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn is_every4pwm(&self) -> bool { + *self == Ldfq::Every4pwm + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn is_every5pwm(&self) -> bool { + *self == Ldfq::Every5pwm + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn is_every6pwm(&self) -> bool { + *self == Ldfq::Every6pwm + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn is_every7pwm(&self) -> bool { + *self == Ldfq::Every7pwm + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn is_every8pwm(&self) -> bool { + *self == Ldfq::Every8pwm + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn is_every9pwm(&self) -> bool { + *self == Ldfq::Every9pwm + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn is_every10pwm(&self) -> bool { + *self == Ldfq::Every10pwm + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn is_every11pwm(&self) -> bool { + *self == Ldfq::Every11pwm + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn is_every12pwm(&self) -> bool { + *self == Ldfq::Every12pwm + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn is_every13pwm(&self) -> bool { + *self == Ldfq::Every13pwm + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn is_every14pwm(&self) -> bool { + *self == Ldfq::Every14pwm + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn is_every15pwm(&self) -> bool { + *self == Ldfq::Every15pwm + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn is_every16pwm(&self) -> bool { + *self == Ldfq::Every16pwm + } +} +#[doc = "Field `LDFQ` writer - Load Frequency"] +pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; +impl<'a, REG> LdfqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Everypwm) + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn every2pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every2pwm) + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn every3pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every3pwm) + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn every4pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every4pwm) + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn every5pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every5pwm) + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn every6pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every6pwm) + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn every7pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every7pwm) + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn every8pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every8pwm) + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn every9pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every9pwm) + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn every10pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every10pwm) + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn every11pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every11pwm) + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn every12pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every12pwm) + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn every13pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every13pwm) + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn every14pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every14pwm) + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn every15pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every15pwm) + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn every16pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every16pwm) + } +} +impl R { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&self) -> DblenR { + DblenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&self) -> DblxR { + DblxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&self) -> LdmodR { + LdmodR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&self) -> SplitR { + SplitR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&self) -> PrscR { + PrscR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&self) -> CompmodeR { + CompmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Deadtime"] + #[inline(always)] + pub fn dt(&self) -> DtR { + DtR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&self) -> FullR { + FullR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&self) -> HalfR { + HalfR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&self) -> LdfqR { + LdfqR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&mut self) -> DblenW { + DblenW::new(self, 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&mut self) -> DblxW { + DblxW::new(self, 1) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&mut self) -> LdmodW { + LdmodW::new(self, 2) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&mut self) -> SplitW { + SplitW::new(self, 3) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&mut self) -> PrscW { + PrscW::new(self, 4) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&mut self) -> CompmodeW { + CompmodeW::new(self, 7) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&mut self) -> FullW { + FullW::new(self, 10) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&mut self) -> HalfW { + HalfW::new(self, 11) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&mut self) -> LdfqW { + LdfqW::new(self, 12) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0ctrlSpec; +impl crate::RegisterSpec for Sm0ctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0ctrl::R`](R) reader structure"] +impl crate::Readable for Sm0ctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0ctrl::W`](W) writer structure"] +impl crate::Writable for Sm0ctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0CTRL to value 0x0400"] +impl crate::Resettable for Sm0ctrlSpec { + const RESET_VALUE: u16 = 0x0400; +} diff --git a/mcxa276-pac/src/flexpwm0/sm0ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm0ctrl2.rs new file mode 100644 index 000000000..a76bf79b9 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0ctrl2.rs @@ -0,0 +1,607 @@ +#[doc = "Register `SM0CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM0CTRL2` writer"] +pub type W = crate::W; +#[doc = "Clock Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ClkSel { + #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] + Ipbus = 0, + #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] + ExtClk = 1, + #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + AuxClk = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ClkSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ClkSel { + type Ux = u8; +} +impl crate::IsEnum for ClkSel {} +#[doc = "Field `CLK_SEL` reader - Clock Source Select"] +pub type ClkSelR = crate::FieldReader; +impl ClkSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ClkSel::Ipbus), + 1 => Some(ClkSel::ExtClk), + 2 => Some(ClkSel::AuxClk), + _ => None, + } + } + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ipbus(&self) -> bool { + *self == ClkSel::Ipbus + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ext_clk(&self) -> bool { + *self == ClkSel::ExtClk + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn is_aux_clk(&self) -> bool { + *self == ClkSel::AuxClk + } +} +#[doc = "Field `CLK_SEL` writer - Clock Source Select"] +pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; +impl<'a, REG> ClkSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ipbus(self) -> &'a mut crate::W { + self.variant(ClkSel::Ipbus) + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ext_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::ExtClk) + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn aux_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::AuxClk) + } +} +#[doc = "Reload Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ReloadSel { + #[doc = "0: The local RELOAD signal is used to reload registers."] + Local = 0, + #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + Master = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ReloadSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] +pub type ReloadSelR = crate::BitReader; +impl ReloadSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ReloadSel { + match self.bits { + false => ReloadSel::Local, + true => ReloadSel::Master, + } + } + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ReloadSel::Local + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ReloadSel::Master + } +} +#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] +pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; +impl<'a, REG> ReloadSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ReloadSel::Local) + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ReloadSel::Master) + } +} +#[doc = "Force Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ForceSel { + #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + Local = 0, + #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + Master = 1, + #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + LocalReload = 2, + #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterReload = 3, + #[doc = "4: The local sync signal from this submodule is used to force updates."] + LocalSync = 4, + #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterSync = 5, + #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + ExtForce = 6, + #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + ExtSync = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ForceSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ForceSel { + type Ux = u8; +} +impl crate::IsEnum for ForceSel {} +#[doc = "Field `FORCE_SEL` reader - Force Select"] +pub type ForceSelR = crate::FieldReader; +impl ForceSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ForceSel { + match self.bits { + 0 => ForceSel::Local, + 1 => ForceSel::Master, + 2 => ForceSel::LocalReload, + 3 => ForceSel::MasterReload, + 4 => ForceSel::LocalSync, + 5 => ForceSel::MasterSync, + 6 => ForceSel::ExtForce, + 7 => ForceSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ForceSel::Local + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ForceSel::Master + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == ForceSel::LocalReload + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == ForceSel::MasterReload + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == ForceSel::LocalSync + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == ForceSel::MasterSync + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_force(&self) -> bool { + *self == ForceSel::ExtForce + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == ForceSel::ExtSync + } +} +#[doc = "Field `FORCE_SEL` writer - Force Select"] +pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; +impl<'a, REG> ForceSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ForceSel::Local) + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ForceSel::Master) + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalReload) + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterReload) + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalSync) + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterSync) + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_force(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtForce) + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtSync) + } +} +#[doc = "Field `FORCE` reader - Force Initialization"] +pub type ForceR = crate::BitReader; +#[doc = "Field `FORCE` writer - Force Initialization"] +pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Force Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frcen { + #[doc = "0: Initialization from a FORCE_OUT is disabled."] + Disabled = 0, + #[doc = "1: Initialization from a FORCE_OUT is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRCEN` reader - Force Enable"] +pub type FrcenR = crate::BitReader; +impl FrcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frcen { + match self.bits { + false => Frcen::Disabled, + true => Frcen::Enabled, + } + } + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Frcen::Disabled + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Frcen::Enabled + } +} +#[doc = "Field `FRCEN` writer - Force Enable"] +pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; +impl<'a, REG> FrcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Frcen::Disabled) + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Frcen::Enabled) + } +} +#[doc = "Initialization Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum InitSel { + #[doc = "0: Local sync (PWM_X) causes initialization."] + PwmX = 0, + #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + MasterReload = 1, + #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + MasterSync = 2, + #[doc = "3: EXT_SYNC causes initialization."] + ExtSync = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: InitSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for InitSel { + type Ux = u8; +} +impl crate::IsEnum for InitSel {} +#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] +pub type InitSelR = crate::FieldReader; +impl InitSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InitSel { + match self.bits { + 0 => InitSel::PwmX, + 1 => InitSel::MasterReload, + 2 => InitSel::MasterSync, + 3 => InitSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InitSel::PwmX + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == InitSel::MasterReload + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == InitSel::MasterSync + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == InitSel::ExtSync + } +} +#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] +pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; +impl<'a, REG> InitSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InitSel::PwmX) + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(InitSel::MasterReload) + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(InitSel::MasterSync) + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(InitSel::ExtSync) + } +} +#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] +pub type PwmxInitR = crate::BitReader; +#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] +pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] +pub type Pwm45InitR = crate::BitReader; +#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] +pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] +pub type Pwm23InitR = crate::BitReader; +#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] +pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Indep { + #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] + Complementary = 0, + #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] + Independent = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Indep) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] +pub type IndepR = crate::BitReader; +impl IndepR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Indep { + match self.bits { + false => Indep::Complementary, + true => Indep::Independent, + } + } + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn is_complementary(&self) -> bool { + *self == Indep::Complementary + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn is_independent(&self) -> bool { + *self == Indep::Independent + } +} +#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] +pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; +impl<'a, REG> IndepW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn complementary(self) -> &'a mut crate::W { + self.variant(Indep::Complementary) + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn independent(self) -> &'a mut crate::W { + self.variant(Indep::Independent) + } +} +#[doc = "Field `DBGEN` reader - Debug Enable"] +pub type DbgenR = crate::BitReader; +#[doc = "Field `DBGEN` writer - Debug Enable"] +pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&self) -> ClkSelR { + ClkSelR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&self) -> ReloadSelR { + ReloadSelR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&self) -> ForceSelR { + ForceSelR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&self) -> ForceR { + ForceR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&self) -> FrcenR { + FrcenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&self) -> InitSelR { + InitSelR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&self) -> PwmxInitR { + PwmxInitR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&self) -> Pwm45InitR { + Pwm45InitR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&self) -> Pwm23InitR { + Pwm23InitR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&self) -> IndepR { + IndepR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&self) -> DbgenR { + DbgenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&mut self) -> ClkSelW { + ClkSelW::new(self, 0) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&mut self) -> ReloadSelW { + ReloadSelW::new(self, 2) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&mut self) -> ForceSelW { + ForceSelW::new(self, 3) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&mut self) -> ForceW { + ForceW::new(self, 6) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&mut self) -> FrcenW { + FrcenW::new(self, 7) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&mut self) -> InitSelW { + InitSelW::new(self, 8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&mut self) -> PwmxInitW { + PwmxInitW::new(self, 10) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&mut self) -> Pwm45InitW { + Pwm45InitW::new(self, 11) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&mut self) -> Pwm23InitW { + Pwm23InitW::new(self, 12) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&mut self) -> IndepW { + IndepW::new(self, 13) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&mut self) -> DbgenW { + DbgenW::new(self, 15) + } +} +#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0ctrl2Spec; +impl crate::RegisterSpec for Sm0ctrl2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0ctrl2::R`](R) reader structure"] +impl crate::Readable for Sm0ctrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0ctrl2::W`](W) writer structure"] +impl crate::Writable for Sm0ctrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0CTRL2 to value 0"] +impl crate::Resettable for Sm0ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval0.rs b/mcxa276-pac/src/flexpwm0/sm0cval0.rs new file mode 100644 index 000000000..49f95676a --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0cval0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM0CVAL0` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] +pub type Captval0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 0"] + #[inline(always)] + pub fn captval0(&self) -> Captval0R { + Captval0R::new(self.bits) + } +} +#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0cval0Spec; +impl crate::RegisterSpec for Sm0cval0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0cval0::R`](R) reader structure"] +impl crate::Readable for Sm0cval0Spec {} +#[doc = "`reset()` method sets SM0CVAL0 to value 0"] +impl crate::Resettable for Sm0cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs new file mode 100644 index 000000000..9ae3f990b --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM0CVAL0CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] +pub type Cval0cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 0 Cycle"] + #[inline(always)] + pub fn cval0cyc(&self) -> Cval0cycR { + Cval0cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0cval0cycSpec; +impl crate::RegisterSpec for Sm0cval0cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0cval0cyc::R`](R) reader structure"] +impl crate::Readable for Sm0cval0cycSpec {} +#[doc = "`reset()` method sets SM0CVAL0CYC to value 0"] +impl crate::Resettable for Sm0cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval1.rs b/mcxa276-pac/src/flexpwm0/sm0cval1.rs new file mode 100644 index 000000000..2dd690fa0 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0cval1.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM0CVAL1` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] +pub type Captval1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 1"] + #[inline(always)] + pub fn captval1(&self) -> Captval1R { + Captval1R::new(self.bits) + } +} +#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0cval1Spec; +impl crate::RegisterSpec for Sm0cval1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0cval1::R`](R) reader structure"] +impl crate::Readable for Sm0cval1Spec {} +#[doc = "`reset()` method sets SM0CVAL1 to value 0"] +impl crate::Resettable for Sm0cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs new file mode 100644 index 000000000..fd9d7737b --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM0CVAL1CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] +pub type Cval1cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 1 Cycle"] + #[inline(always)] + pub fn cval1cyc(&self) -> Cval1cycR { + Cval1cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0cval1cycSpec; +impl crate::RegisterSpec for Sm0cval1cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0cval1cyc::R`](R) reader structure"] +impl crate::Readable for Sm0cval1cycSpec {} +#[doc = "`reset()` method sets SM0CVAL1CYC to value 0"] +impl crate::Resettable for Sm0cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0dismap0.rs b/mcxa276-pac/src/flexpwm0/sm0dismap0.rs new file mode 100644 index 000000000..ec64ffdf9 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0dismap0.rs @@ -0,0 +1,65 @@ +#[doc = "Register `SM0DISMAP0` reader"] +pub type R = crate::R; +#[doc = "Register `SM0DISMAP0` writer"] +pub type W = crate::W; +#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] +pub type Dis0aR = crate::FieldReader; +#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] +pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] +pub type Dis0bR = crate::FieldReader; +#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] +pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] +pub type Dis0xR = crate::FieldReader; +#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] +pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&self) -> Dis0aR { + Dis0aR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&self) -> Dis0bR { + Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&self) -> Dis0xR { + Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&mut self) -> Dis0aW { + Dis0aW::new(self, 0) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&mut self) -> Dis0bW { + Dis0bW::new(self, 4) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&mut self) -> Dis0xW { + Dis0xW::new(self, 8) + } +} +#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0dismap0Spec; +impl crate::RegisterSpec for Sm0dismap0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0dismap0::R`](R) reader structure"] +impl crate::Readable for Sm0dismap0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0dismap0::W`](W) writer structure"] +impl crate::Writable for Sm0dismap0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0DISMAP0 to value 0xffff"] +impl crate::Resettable for Sm0dismap0Spec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm0dmaen.rs b/mcxa276-pac/src/flexpwm0/sm0dmaen.rs new file mode 100644 index 000000000..d6719ff21 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0dmaen.rs @@ -0,0 +1,271 @@ +#[doc = "Register `SM0DMAEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM0DMAEN` writer"] +pub type W = crate::W; +#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] +pub type Cx0deR = crate::BitReader; +#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] +pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] +pub type Cx1deR = crate::BitReader; +#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] +pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Captde { + #[doc = "0: Read DMA requests disabled."] + Disabled = 0, + #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + Exceedfifo = 1, + #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] + LocalSync = 2, + #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] + LocalReload = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Captde) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Captde { + type Ux = u8; +} +impl crate::IsEnum for Captde {} +#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] +pub type CaptdeR = crate::FieldReader; +impl CaptdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Captde { + match self.bits { + 0 => Captde::Disabled, + 1 => Captde::Exceedfifo, + 2 => Captde::LocalSync, + 3 => Captde::LocalReload, + _ => unreachable!(), + } + } + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Captde::Disabled + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn is_exceedfifo(&self) -> bool { + *self == Captde::Exceedfifo + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == Captde::LocalSync + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == Captde::LocalReload + } +} +#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] +pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; +impl<'a, REG> CaptdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Captde::Disabled) + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn exceedfifo(self) -> &'a mut crate::W { + self.variant(Captde::Exceedfifo) + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(Captde::LocalSync) + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(Captde::LocalReload) + } +} +#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fand { + #[doc = "0: Selected FIFO watermarks are OR'ed together."] + Or = 0, + #[doc = "1: Selected FIFO watermarks are AND'ed together."] + And = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fand) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] +pub type FandR = crate::BitReader; +impl FandR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fand { + match self.bits { + false => Fand::Or, + true => Fand::And, + } + } + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn is_or(&self) -> bool { + *self == Fand::Or + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn is_and(&self) -> bool { + *self == Fand::And + } +} +#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] +pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; +impl<'a, REG> FandW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn or(self) -> &'a mut crate::W { + self.variant(Fand::Or) + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn and(self) -> &'a mut crate::W { + self.variant(Fand::And) + } +} +#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Valde { + #[doc = "0: DMA write requests disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Valde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] +pub type ValdeR = crate::BitReader; +impl ValdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Valde { + match self.bits { + false => Valde::Disabled, + true => Valde::Enabled, + } + } + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Valde::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Valde::Enabled + } +} +#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] +pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; +impl<'a, REG> ValdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Valde::Disabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Valde::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&self) -> Cx0deR { + Cx0deR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&self) -> Cx1deR { + Cx1deR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&self) -> CaptdeR { + CaptdeR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&self) -> FandR { + FandR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&self) -> ValdeR { + ValdeR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&mut self) -> Cx0deW { + Cx0deW::new(self, 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&mut self) -> Cx1deW { + Cx1deW::new(self, 1) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&mut self) -> CaptdeW { + CaptdeW::new(self, 6) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&mut self) -> FandW { + FandW::new(self, 8) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&mut self) -> ValdeW { + ValdeW::new(self, 9) + } +} +#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0dmaenSpec; +impl crate::RegisterSpec for Sm0dmaenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0dmaen::R`](R) reader structure"] +impl crate::Readable for Sm0dmaenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0dmaen::W`](W) writer structure"] +impl crate::Writable for Sm0dmaenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0DMAEN to value 0"] +impl crate::Resettable for Sm0dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs new file mode 100644 index 000000000..f5548e94c --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM0DTCNT0` reader"] +pub type R = crate::R; +#[doc = "Register `SM0DTCNT0` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] +pub type Dtcnt0R = crate::FieldReader; +#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] +pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&self) -> Dtcnt0R { + Dtcnt0R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&mut self) -> Dtcnt0W { + Dtcnt0W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0dtcnt0Spec; +impl crate::RegisterSpec for Sm0dtcnt0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0dtcnt0::R`](R) reader structure"] +impl crate::Readable for Sm0dtcnt0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0dtcnt0::W`](W) writer structure"] +impl crate::Writable for Sm0dtcnt0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0DTCNT0 to value 0x07ff"] +impl crate::Resettable for Sm0dtcnt0Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs new file mode 100644 index 000000000..408c6739f --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM0DTCNT1` reader"] +pub type R = crate::R; +#[doc = "Register `SM0DTCNT1` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] +pub type Dtcnt1R = crate::FieldReader; +#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] +pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&self) -> Dtcnt1R { + Dtcnt1R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&mut self) -> Dtcnt1W { + Dtcnt1W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0dtcnt1Spec; +impl crate::RegisterSpec for Sm0dtcnt1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0dtcnt1::R`](R) reader structure"] +impl crate::Readable for Sm0dtcnt1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0dtcnt1::W`](W) writer structure"] +impl crate::Writable for Sm0dtcnt1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0DTCNT1 to value 0x07ff"] +impl crate::Resettable for Sm0dtcnt1Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm0init.rs b/mcxa276-pac/src/flexpwm0/sm0init.rs new file mode 100644 index 000000000..c2b0617d3 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0init.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM0INIT` reader"] +pub type R = crate::R; +#[doc = "Register `SM0INIT` writer"] +pub type W = crate::W; +#[doc = "Field `INIT` reader - Initial Count Register Bits"] +pub type InitR = crate::FieldReader; +#[doc = "Field `INIT` writer - Initial Count Register Bits"] +pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&self) -> InitR { + InitR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&mut self) -> InitW { + InitW::new(self, 0) + } +} +#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0initSpec; +impl crate::RegisterSpec for Sm0initSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0init::R`](R) reader structure"] +impl crate::Readable for Sm0initSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0init::W`](W) writer structure"] +impl crate::Writable for Sm0initSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0INIT to value 0"] +impl crate::Resettable for Sm0initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0inten.rs b/mcxa276-pac/src/flexpwm0/sm0inten.rs new file mode 100644 index 000000000..6f2cdae10 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0inten.rs @@ -0,0 +1,343 @@ +#[doc = "Register `SM0INTEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM0INTEN` writer"] +pub type W = crate::W; +#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpie { + #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + Disabled = 0, + #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + Enabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpie) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpie { + type Ux = u8; +} +impl crate::IsEnum for Cmpie {} +#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] +pub type CmpieR = crate::FieldReader; +impl CmpieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpie::Disabled), + 1 => Some(Cmpie::Enabled), + _ => None, + } + } + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmpie::Disabled + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmpie::Enabled + } +} +#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] +pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; +impl<'a, REG> CmpieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Disabled) + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Enabled) + } +} +#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx0ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx0ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] +pub type Cx0ieR = crate::BitReader; +impl Cx0ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx0ie { + match self.bits { + false => Cx0ie::Disabled, + true => Cx0ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx0ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx0ie::Enabled + } +} +#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] +pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; +impl<'a, REG> Cx0ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Enabled) + } +} +#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx1ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx1ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] +pub type Cx1ieR = crate::BitReader; +impl Cx1ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx1ie { + match self.bits { + false => Cx1ie::Disabled, + true => Cx1ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx1ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx1ie::Enabled + } +} +#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] +pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; +impl<'a, REG> Cx1ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Enabled) + } +} +#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rie { + #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RIE` reader - Reload Interrupt Enable"] +pub type RieR = crate::BitReader; +impl RieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rie { + match self.bits { + false => Rie::Disabled, + true => Rie::Enabled, + } + } + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rie::Disabled + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rie::Enabled + } +} +#[doc = "Field `RIE` writer - Reload Interrupt Enable"] +pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; +impl<'a, REG> RieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rie::Disabled) + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rie::Enabled) + } +} +#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reie { + #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] +pub type ReieR = crate::BitReader; +impl ReieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reie { + match self.bits { + false => Reie::Disabled, + true => Reie::Enabled, + } + } + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Reie::Disabled + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Reie::Enabled + } +} +#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] +pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; +impl<'a, REG> ReieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Reie::Disabled) + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Reie::Enabled) + } +} +impl R { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&self) -> CmpieR { + CmpieR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&self) -> Cx0ieR { + Cx0ieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&self) -> Cx1ieR { + Cx1ieR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RieR { + RieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&self) -> ReieR { + ReieR::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&mut self) -> CmpieW { + CmpieW::new(self, 0) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&mut self) -> Cx0ieW { + Cx0ieW::new(self, 6) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&mut self) -> Cx1ieW { + Cx1ieW::new(self, 7) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&mut self) -> RieW { + RieW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&mut self) -> ReieW { + ReieW::new(self, 13) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0intenSpec; +impl crate::RegisterSpec for Sm0intenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0inten::R`](R) reader structure"] +impl crate::Readable for Sm0intenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0inten::W`](W) writer structure"] +impl crate::Writable for Sm0intenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0INTEN to value 0"] +impl crate::Resettable for Sm0intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0octrl.rs b/mcxa276-pac/src/flexpwm0/sm0octrl.rs new file mode 100644 index 000000000..9eac3b923 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0octrl.rs @@ -0,0 +1,519 @@ +#[doc = "Register `SM0OCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM0OCTRL` writer"] +pub type W = crate::W; +#[doc = "PWM_X Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmxfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmxfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmxfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmxfs {} +#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] +pub type PwmxfsR = crate::FieldReader; +impl PwmxfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmxfs { + match self.bits { + 0 => Pwmxfs::Logic0, + 1 => Pwmxfs::Logic1, + 2 => Pwmxfs::Tristated2, + 3 => Pwmxfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmxfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmxfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmxfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmxfs::Tristated3 + } +} +#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] +pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; +impl<'a, REG> PwmxfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated3) + } +} +#[doc = "PWM_B Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmbfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmbfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmbfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmbfs {} +#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] +pub type PwmbfsR = crate::FieldReader; +impl PwmbfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmbfs { + match self.bits { + 0 => Pwmbfs::Logic0, + 1 => Pwmbfs::Logic1, + 2 => Pwmbfs::Tristated2, + 3 => Pwmbfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmbfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmbfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmbfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmbfs::Tristated3 + } +} +#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] +pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; +impl<'a, REG> PwmbfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated3) + } +} +#[doc = "PWM_A Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmafs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmafs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmafs { + type Ux = u8; +} +impl crate::IsEnum for Pwmafs {} +#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] +pub type PwmafsR = crate::FieldReader; +impl PwmafsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmafs { + match self.bits { + 0 => Pwmafs::Logic0, + 1 => Pwmafs::Logic1, + 2 => Pwmafs::Tristated2, + 3 => Pwmafs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmafs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmafs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmafs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmafs::Tristated3 + } +} +#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] +pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; +impl<'a, REG> PwmafsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated3) + } +} +#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polx { + #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLX` reader - PWM_X Output Polarity"] +pub type PolxR = crate::BitReader; +impl PolxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polx { + match self.bits { + false => Polx::NotInverted, + true => Polx::Inverted, + } + } + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polx::NotInverted + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polx::Inverted + } +} +#[doc = "Field `POLX` writer - PWM_X Output Polarity"] +pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; +impl<'a, REG> PolxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polx::NotInverted) + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polx::Inverted) + } +} +#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polb { + #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLB` reader - PWM_B Output Polarity"] +pub type PolbR = crate::BitReader; +impl PolbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polb { + match self.bits { + false => Polb::NotInverted, + true => Polb::Inverted, + } + } + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polb::NotInverted + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polb::Inverted + } +} +#[doc = "Field `POLB` writer - PWM_B Output Polarity"] +pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; +impl<'a, REG> PolbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polb::NotInverted) + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polb::Inverted) + } +} +#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pola { + #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pola) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLA` reader - PWM_A Output Polarity"] +pub type PolaR = crate::BitReader; +impl PolaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pola { + match self.bits { + false => Pola::NotInverted, + true => Pola::Inverted, + } + } + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Pola::NotInverted + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Pola::Inverted + } +} +#[doc = "Field `POLA` writer - PWM_A Output Polarity"] +pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; +impl<'a, REG> PolaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Pola::NotInverted) + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Pola::Inverted) + } +} +#[doc = "Field `PWMX_IN` reader - PWM_X Input"] +pub type PwmxInR = crate::BitReader; +#[doc = "Field `PWMB_IN` reader - PWM_B Input"] +pub type PwmbInR = crate::BitReader; +#[doc = "Field `PWMA_IN` reader - PWM_A Input"] +pub type PwmaInR = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&self) -> PwmxfsR { + PwmxfsR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&self) -> PwmbfsR { + PwmbfsR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&self) -> PwmafsR { + PwmafsR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&self) -> PolxR { + PolxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&self) -> PolbR { + PolbR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&self) -> PolaR { + PolaR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - PWM_X Input"] + #[inline(always)] + pub fn pwmx_in(&self) -> PwmxInR { + PwmxInR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PWM_B Input"] + #[inline(always)] + pub fn pwmb_in(&self) -> PwmbInR { + PwmbInR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - PWM_A Input"] + #[inline(always)] + pub fn pwma_in(&self) -> PwmaInR { + PwmaInR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&mut self) -> PwmxfsW { + PwmxfsW::new(self, 0) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&mut self) -> PwmbfsW { + PwmbfsW::new(self, 2) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&mut self) -> PwmafsW { + PwmafsW::new(self, 4) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&mut self) -> PolxW { + PolxW::new(self, 8) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&mut self) -> PolbW { + PolbW::new(self, 9) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&mut self) -> PolaW { + PolaW::new(self, 10) + } +} +#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0octrlSpec; +impl crate::RegisterSpec for Sm0octrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0octrl::R`](R) reader structure"] +impl crate::Readable for Sm0octrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0octrl::W`](W) writer structure"] +impl crate::Writable for Sm0octrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0OCTRL to value 0"] +impl crate::Resettable for Sm0octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0sts.rs b/mcxa276-pac/src/flexpwm0/sm0sts.rs new file mode 100644 index 000000000..087cd434e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0sts.rs @@ -0,0 +1,287 @@ +#[doc = "Register `SM0STS` reader"] +pub type R = crate::R; +#[doc = "Register `SM0STS` writer"] +pub type W = crate::W; +#[doc = "Compare Flags\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpf { + #[doc = "0: No compare event has occurred for a particular VALx value."] + NoEvent = 0, + #[doc = "1: A compare event has occurred for a particular VALx value."] + Event = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpf { + type Ux = u8; +} +impl crate::IsEnum for Cmpf {} +#[doc = "Field `CMPF` reader - Compare Flags"] +pub type CmpfR = crate::FieldReader; +impl CmpfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpf::NoEvent), + 1 => Some(Cmpf::Event), + _ => None, + } + } + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_no_event(&self) -> bool { + *self == Cmpf::NoEvent + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == Cmpf::Event + } +} +#[doc = "Field `CMPF` writer - Compare Flags"] +pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; +impl<'a, REG> CmpfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn no_event(self) -> &'a mut crate::W { + self.variant(Cmpf::NoEvent) + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn event(self) -> &'a mut crate::W { + self.variant(Cmpf::Event) + } +} +#[doc = "Field `CFX0` reader - Capture Flag X0"] +pub type Cfx0R = crate::BitReader; +#[doc = "Field `CFX0` writer - Capture Flag X0"] +pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CFX1` reader - Capture Flag X1"] +pub type Cfx1R = crate::BitReader; +#[doc = "Field `CFX1` writer - Capture Flag X1"] +pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Reload Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rf { + #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] + NoFlag = 0, + #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RF` reader - Reload Flag"] +pub type RfR = crate::BitReader; +impl RfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rf { + match self.bits { + false => Rf::NoFlag, + true => Rf::Flag, + } + } + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Rf::NoFlag + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Rf::Flag + } +} +#[doc = "Field `RF` writer - Reload Flag"] +pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; +impl<'a, REG> RfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Rf::NoFlag) + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Rf::Flag) + } +} +#[doc = "Reload Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ref { + #[doc = "0: No reload error occurred."] + NoFlag = 0, + #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ref) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REF` reader - Reload Error Flag"] +pub type RefR = crate::BitReader; +impl RefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ref { + match self.bits { + false => Ref::NoFlag, + true => Ref::Flag, + } + } + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ref::NoFlag + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ref::Flag + } +} +#[doc = "Field `REF` writer - Reload Error Flag"] +pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; +impl<'a, REG> RefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Ref::NoFlag) + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Ref::Flag) + } +} +#[doc = "Registers Updated Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ruf { + #[doc = "0: No register update has occurred since last reload."] + NoFlag = 0, + #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ruf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RUF` reader - Registers Updated Flag"] +pub type RufR = crate::BitReader; +impl RufR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ruf { + match self.bits { + false => Ruf::NoFlag, + true => Ruf::Flag, + } + } + #[doc = "No register update has occurred since last reload."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ruf::NoFlag + } + #[doc = "At least one of the double buffered registers has been updated since the last reload."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ruf::Flag + } +} +impl R { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&self) -> CmpfR { + CmpfR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&self) -> Cfx0R { + Cfx0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&self) -> Cfx1R { + Cfx1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&self) -> RfR { + RfR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&self) -> RefR { + RefR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Registers Updated Flag"] + #[inline(always)] + pub fn ruf(&self) -> RufR { + RufR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&mut self) -> CmpfW { + CmpfW::new(self, 0) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&mut self) -> Cfx0W { + Cfx0W::new(self, 6) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&mut self) -> Cfx1W { + Cfx1W::new(self, 7) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&mut self) -> RfW { + RfW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&mut self) -> RefW { + RefW::new(self, 13) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0stsSpec; +impl crate::RegisterSpec for Sm0stsSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0sts::R`](R) reader structure"] +impl crate::Readable for Sm0stsSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0sts::W`](W) writer structure"] +impl crate::Writable for Sm0stsSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; +} +#[doc = "`reset()` method sets SM0STS to value 0"] +impl crate::Resettable for Sm0stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0tctrl.rs b/mcxa276-pac/src/flexpwm0/sm0tctrl.rs new file mode 100644 index 000000000..c4976fdb1 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0tctrl.rs @@ -0,0 +1,267 @@ +#[doc = "Register `SM0TCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM0TCTRL` writer"] +pub type W = crate::W; +#[doc = "Output Trigger Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OutTrigEn { + #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + Val0 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OutTrigEn) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OutTrigEn { + type Ux = u8; +} +impl crate::IsEnum for OutTrigEn {} +#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] +pub type OutTrigEnR = crate::FieldReader; +impl OutTrigEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(OutTrigEn::Val0), + _ => None, + } + } + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == OutTrigEn::Val0 + } +} +#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] +pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; +impl<'a, REG> OutTrigEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn val0(self) -> &'a mut crate::W { + self.variant(OutTrigEn::Val0) + } +} +#[doc = "Trigger Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trgfrq { + #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Everypwm = 0, + #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Finalpwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trgfrq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] +pub type TrgfrqR = crate::BitReader; +impl TrgfrqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgfrq { + match self.bits { + false => Trgfrq::Everypwm, + true => Trgfrq::Finalpwm, + } + } + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Trgfrq::Everypwm + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_finalpwm(&self) -> bool { + *self == Trgfrq::Finalpwm + } +} +#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] +pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; +impl<'a, REG> TrgfrqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Everypwm) + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn finalpwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Finalpwm) + } +} +#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwbot1 { + #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + PwmOutTrig1Signal = 0, + #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] + PwmbOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwbot1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] +pub type Pwbot1R = crate::BitReader; +impl Pwbot1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwbot1 { + match self.bits { + false => Pwbot1::PwmOutTrig1Signal, + true => Pwbot1::PwmbOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwm_out_trig1_signal(&self) -> bool { + *self == Pwbot1::PwmOutTrig1Signal + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwmb_output(&self) -> bool { + *self == Pwbot1::PwmbOutput + } +} +#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] +pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; +impl<'a, REG> Pwbot1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmOutTrig1Signal) + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwmb_output(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmbOutput) + } +} +#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwaot0 { + #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + PwmOutTrig0Signal = 0, + #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] + PwmaOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwaot0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] +pub type Pwaot0R = crate::BitReader; +impl Pwaot0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwaot0 { + match self.bits { + false => Pwaot0::PwmOutTrig0Signal, + true => Pwaot0::PwmaOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwm_out_trig0_signal(&self) -> bool { + *self == Pwaot0::PwmOutTrig0Signal + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwma_output(&self) -> bool { + *self == Pwaot0::PwmaOutput + } +} +#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] +pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; +impl<'a, REG> Pwaot0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmOutTrig0Signal) + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwma_output(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmaOutput) + } +} +impl R { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&self) -> OutTrigEnR { + OutTrigEnR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&self) -> TrgfrqR { + TrgfrqR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&self) -> Pwbot1R { + Pwbot1R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&self) -> Pwaot0R { + Pwaot0R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&mut self) -> OutTrigEnW { + OutTrigEnW::new(self, 0) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&mut self) -> TrgfrqW { + TrgfrqW::new(self, 12) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&mut self) -> Pwbot1W { + Pwbot1W::new(self, 14) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&mut self) -> Pwaot0W { + Pwaot0W::new(self, 15) + } +} +#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0tctrlSpec; +impl crate::RegisterSpec for Sm0tctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0tctrl::R`](R) reader structure"] +impl crate::Readable for Sm0tctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm0tctrl::W`](W) writer structure"] +impl crate::Writable for Sm0tctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0TCTRL to value 0"] +impl crate::Resettable for Sm0tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val0.rs b/mcxa276-pac/src/flexpwm0/sm0val0.rs new file mode 100644 index 000000000..3f15605b5 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0val0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM0VAL0` reader"] +pub type R = crate::R; +#[doc = "Register `SM0VAL0` writer"] +pub type W = crate::W; +#[doc = "Field `VAL0` reader - Value 0"] +pub type Val0R = crate::FieldReader; +#[doc = "Field `VAL0` writer - Value 0"] +pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&self) -> Val0R { + Val0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&mut self) -> Val0W { + Val0W::new(self, 0) + } +} +#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0val0Spec; +impl crate::RegisterSpec for Sm0val0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0val0::R`](R) reader structure"] +impl crate::Readable for Sm0val0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0val0::W`](W) writer structure"] +impl crate::Writable for Sm0val0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0VAL0 to value 0"] +impl crate::Resettable for Sm0val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val1.rs b/mcxa276-pac/src/flexpwm0/sm0val1.rs new file mode 100644 index 000000000..b924478d1 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0val1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM0VAL1` reader"] +pub type R = crate::R; +#[doc = "Register `SM0VAL1` writer"] +pub type W = crate::W; +#[doc = "Field `VAL1` reader - Value 1"] +pub type Val1R = crate::FieldReader; +#[doc = "Field `VAL1` writer - Value 1"] +pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&self) -> Val1R { + Val1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&mut self) -> Val1W { + Val1W::new(self, 0) + } +} +#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0val1Spec; +impl crate::RegisterSpec for Sm0val1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0val1::R`](R) reader structure"] +impl crate::Readable for Sm0val1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0val1::W`](W) writer structure"] +impl crate::Writable for Sm0val1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0VAL1 to value 0"] +impl crate::Resettable for Sm0val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val2.rs b/mcxa276-pac/src/flexpwm0/sm0val2.rs new file mode 100644 index 000000000..bee801ffb --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0val2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM0VAL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM0VAL2` writer"] +pub type W = crate::W; +#[doc = "Field `VAL2` reader - Value 2"] +pub type Val2R = crate::FieldReader; +#[doc = "Field `VAL2` writer - Value 2"] +pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&self) -> Val2R { + Val2R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&mut self) -> Val2W { + Val2W::new(self, 0) + } +} +#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0val2Spec; +impl crate::RegisterSpec for Sm0val2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0val2::R`](R) reader structure"] +impl crate::Readable for Sm0val2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0val2::W`](W) writer structure"] +impl crate::Writable for Sm0val2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0VAL2 to value 0"] +impl crate::Resettable for Sm0val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val3.rs b/mcxa276-pac/src/flexpwm0/sm0val3.rs new file mode 100644 index 000000000..a1831ca34 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0val3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM0VAL3` reader"] +pub type R = crate::R; +#[doc = "Register `SM0VAL3` writer"] +pub type W = crate::W; +#[doc = "Field `VAL3` reader - Value 3"] +pub type Val3R = crate::FieldReader; +#[doc = "Field `VAL3` writer - Value 3"] +pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&self) -> Val3R { + Val3R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&mut self) -> Val3W { + Val3W::new(self, 0) + } +} +#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0val3Spec; +impl crate::RegisterSpec for Sm0val3Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0val3::R`](R) reader structure"] +impl crate::Readable for Sm0val3Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0val3::W`](W) writer structure"] +impl crate::Writable for Sm0val3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0VAL3 to value 0"] +impl crate::Resettable for Sm0val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val4.rs b/mcxa276-pac/src/flexpwm0/sm0val4.rs new file mode 100644 index 000000000..1e1f114dd --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0val4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM0VAL4` reader"] +pub type R = crate::R; +#[doc = "Register `SM0VAL4` writer"] +pub type W = crate::W; +#[doc = "Field `VAL4` reader - Value 4"] +pub type Val4R = crate::FieldReader; +#[doc = "Field `VAL4` writer - Value 4"] +pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&self) -> Val4R { + Val4R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&mut self) -> Val4W { + Val4W::new(self, 0) + } +} +#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0val4Spec; +impl crate::RegisterSpec for Sm0val4Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0val4::R`](R) reader structure"] +impl crate::Readable for Sm0val4Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0val4::W`](W) writer structure"] +impl crate::Writable for Sm0val4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0VAL4 to value 0"] +impl crate::Resettable for Sm0val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val5.rs b/mcxa276-pac/src/flexpwm0/sm0val5.rs new file mode 100644 index 000000000..6b7f10d45 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm0val5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM0VAL5` reader"] +pub type R = crate::R; +#[doc = "Register `SM0VAL5` writer"] +pub type W = crate::W; +#[doc = "Field `VAL5` reader - Value 5"] +pub type Val5R = crate::FieldReader; +#[doc = "Field `VAL5` writer - Value 5"] +pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&self) -> Val5R { + Val5R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&mut self) -> Val5W { + Val5W::new(self, 0) + } +} +#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm0val5Spec; +impl crate::RegisterSpec for Sm0val5Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm0val5::R`](R) reader structure"] +impl crate::Readable for Sm0val5Spec {} +#[doc = "`write(|w| ..)` method takes [`sm0val5::W`](W) writer structure"] +impl crate::Writable for Sm0val5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM0VAL5 to value 0"] +impl crate::Resettable for Sm0val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1captcompx.rs b/mcxa276-pac/src/flexpwm0/sm1captcompx.rs new file mode 100644 index 000000000..abb6a9523 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1captcompx.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SM1CAPTCOMPX` reader"] +pub type R = crate::R; +#[doc = "Register `SM1CAPTCOMPX` writer"] +pub type W = crate::W; +#[doc = "Field `EDGCMPX` reader - Edge Compare X"] +pub type EdgcmpxR = crate::FieldReader; +#[doc = "Field `EDGCMPX` writer - Edge Compare X"] +pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EDGCNTX` reader - Edge Counter X"] +pub type EdgcntxR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&self) -> EdgcmpxR { + EdgcmpxR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Edge Counter X"] + #[inline(always)] + pub fn edgcntx(&self) -> EdgcntxR { + EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&mut self) -> EdgcmpxW { + EdgcmpxW::new(self, 0) + } +} +#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1captcompxSpec; +impl crate::RegisterSpec for Sm1captcompxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1captcompx::R`](R) reader structure"] +impl crate::Readable for Sm1captcompxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1captcompx::W`](W) writer structure"] +impl crate::Writable for Sm1captcompxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1CAPTCOMPX to value 0"] +impl crate::Resettable for Sm1captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm1captctrlx.rs new file mode 100644 index 000000000..0eb57f95b --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1captctrlx.rs @@ -0,0 +1,493 @@ +#[doc = "Register `SM1CAPTCTRLX` reader"] +pub type R = crate::R; +#[doc = "Register `SM1CAPTCTRLX` writer"] +pub type W = crate::W; +#[doc = "Arm X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Armx { + #[doc = "0: Input capture operation is disabled."] + Disabled = 0, + #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Armx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARMX` reader - Arm X"] +pub type ArmxR = crate::BitReader; +impl ArmxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Armx { + match self.bits { + false => Armx::Disabled, + true => Armx::Enabled, + } + } + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Armx::Disabled + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Armx::Enabled + } +} +#[doc = "Field `ARMX` writer - Arm X"] +pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; +impl<'a, REG> ArmxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Armx::Disabled) + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Armx::Enabled) + } +} +#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oneshotx { + #[doc = "0: Free Running"] + FreeRunning = 0, + #[doc = "1: One Shot"] + OneShot = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oneshotx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] +pub type OneshotxR = crate::BitReader; +impl OneshotxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oneshotx { + match self.bits { + false => Oneshotx::FreeRunning, + true => Oneshotx::OneShot, + } + } + #[doc = "Free Running"] + #[inline(always)] + pub fn is_free_running(&self) -> bool { + *self == Oneshotx::FreeRunning + } + #[doc = "One Shot"] + #[inline(always)] + pub fn is_one_shot(&self) -> bool { + *self == Oneshotx::OneShot + } +} +#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] +pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; +impl<'a, REG> OneshotxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Free Running"] + #[inline(always)] + pub fn free_running(self) -> &'a mut crate::W { + self.variant(Oneshotx::FreeRunning) + } + #[doc = "One Shot"] + #[inline(always)] + pub fn one_shot(self) -> &'a mut crate::W { + self.variant(Oneshotx::OneShot) + } +} +#[doc = "Edge X 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx0 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx0 { + type Ux = u8; +} +impl crate::IsEnum for Edgx0 {} +#[doc = "Field `EDGX0` reader - Edge X 0"] +pub type Edgx0R = crate::FieldReader; +impl Edgx0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx0 { + match self.bits { + 0 => Edgx0::Disabled, + 1 => Edgx0::FallingEdge, + 2 => Edgx0::RisingEdge, + 3 => Edgx0::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx0::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx0::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx0::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx0::AnyEdge + } +} +#[doc = "Field `EDGX0` writer - Edge X 0"] +pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; +impl<'a, REG> Edgx0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx0::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::AnyEdge) + } +} +#[doc = "Edge X 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx1 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx1 { + type Ux = u8; +} +impl crate::IsEnum for Edgx1 {} +#[doc = "Field `EDGX1` reader - Edge X 1"] +pub type Edgx1R = crate::FieldReader; +impl Edgx1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx1 { + match self.bits { + 0 => Edgx1::Disabled, + 1 => Edgx1::FallingEdge, + 2 => Edgx1::RisingEdge, + 3 => Edgx1::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx1::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx1::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx1::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx1::AnyEdge + } +} +#[doc = "Field `EDGX1` writer - Edge X 1"] +pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; +impl<'a, REG> Edgx1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx1::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::AnyEdge) + } +} +#[doc = "Input Select X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum InpSelx { + #[doc = "0: Raw PWM_X input signal selected as source."] + PwmX = 0, + #[doc = "1: Edge Counter"] + EdgeCounter = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: InpSelx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INP_SELX` reader - Input Select X"] +pub type InpSelxR = crate::BitReader; +impl InpSelxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InpSelx { + match self.bits { + false => InpSelx::PwmX, + true => InpSelx::EdgeCounter, + } + } + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InpSelx::PwmX + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn is_edge_counter(&self) -> bool { + *self == InpSelx::EdgeCounter + } +} +#[doc = "Field `INP_SELX` writer - Input Select X"] +pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; +impl<'a, REG> InpSelxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InpSelx::PwmX) + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn edge_counter(self) -> &'a mut crate::W { + self.variant(InpSelx::EdgeCounter) + } +} +#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EdgcntxEn { + #[doc = "0: Edge counter disabled and held in reset"] + Disabled = 0, + #[doc = "1: Edge counter enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EdgcntxEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] +pub type EdgcntxEnR = crate::BitReader; +impl EdgcntxEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EdgcntxEn { + match self.bits { + false => EdgcntxEn::Disabled, + true => EdgcntxEn::Enabled, + } + } + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EdgcntxEn::Disabled + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EdgcntxEn::Enabled + } +} +#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] +pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; +impl<'a, REG> EdgcntxEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Disabled) + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Enabled) + } +} +#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] +pub type CfxwmR = crate::FieldReader; +#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] +pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] +pub type Cx0cntR = crate::FieldReader; +#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] +pub type Cx1cntR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&self) -> ArmxR { + ArmxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&self) -> OneshotxR { + OneshotxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&self) -> Edgx0R { + Edgx0R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&self) -> Edgx1R { + Edgx1R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&self) -> InpSelxR { + InpSelxR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&self) -> EdgcntxEnR { + EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&self) -> CfxwmR { + CfxwmR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] + #[inline(always)] + pub fn cx0cnt(&self) -> Cx0cntR { + Cx0cntR::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] + #[inline(always)] + pub fn cx1cnt(&self) -> Cx1cntR { + Cx1cntR::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&mut self) -> ArmxW { + ArmxW::new(self, 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&mut self) -> OneshotxW { + OneshotxW::new(self, 1) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&mut self) -> Edgx0W { + Edgx0W::new(self, 2) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&mut self) -> Edgx1W { + Edgx1W::new(self, 4) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&mut self) -> InpSelxW { + InpSelxW::new(self, 6) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&mut self) -> EdgcntxEnW { + EdgcntxEnW::new(self, 7) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&mut self) -> CfxwmW { + CfxwmW::new(self, 8) + } +} +#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1captctrlxSpec; +impl crate::RegisterSpec for Sm1captctrlxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1captctrlx::R`](R) reader structure"] +impl crate::Readable for Sm1captctrlxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1captctrlx::W`](W) writer structure"] +impl crate::Writable for Sm1captctrlxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1CAPTCTRLX to value 0"] +impl crate::Resettable for Sm1captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm1captfiltx.rs new file mode 100644 index 000000000..886ae63ba --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1captfiltx.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SM1CAPTFILTX` reader"] +pub type R = crate::R; +#[doc = "Register `SM1CAPTFILTX` writer"] +pub type W = crate::W; +#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] +pub type CaptxFiltPerR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] +pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] +pub type CaptxFiltCntR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] +pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&self) -> CaptxFiltPerR { + CaptxFiltPerR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { + CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { + CaptxFiltPerW::new(self, 0) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { + CaptxFiltCntW::new(self, 8) + } +} +#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1captfiltxSpec; +impl crate::RegisterSpec for Sm1captfiltxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1captfiltx::R`](R) reader structure"] +impl crate::Readable for Sm1captfiltxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1captfiltx::W`](W) writer structure"] +impl crate::Writable for Sm1captfiltxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1CAPTFILTX to value 0"] +impl crate::Resettable for Sm1captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cnt.rs b/mcxa276-pac/src/flexpwm0/sm1cnt.rs new file mode 100644 index 000000000..356cc2e91 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1cnt.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM1CNT` reader"] +pub type R = crate::R; +#[doc = "Field `CNT` reader - Counter Register Bits"] +pub type CntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Counter Register Bits"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1cntSpec; +impl crate::RegisterSpec for Sm1cntSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1cnt::R`](R) reader structure"] +impl crate::Readable for Sm1cntSpec {} +#[doc = "`reset()` method sets SM1CNT to value 0"] +impl crate::Resettable for Sm1cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1ctrl.rs b/mcxa276-pac/src/flexpwm0/sm1ctrl.rs new file mode 100644 index 000000000..c4871e038 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1ctrl.rs @@ -0,0 +1,871 @@ +#[doc = "Register `SM1CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM1CTRL` writer"] +pub type W = crate::W; +#[doc = "Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblen { + #[doc = "0: Double switching disabled."] + Disabled = 0, + #[doc = "1: Double switching enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLEN` reader - Double Switching Enable"] +pub type DblenR = crate::BitReader; +impl DblenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblen { + match self.bits { + false => Dblen::Disabled, + true => Dblen::Enabled, + } + } + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblen::Disabled + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblen::Enabled + } +} +#[doc = "Field `DBLEN` writer - Double Switching Enable"] +pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; +impl<'a, REG> DblenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblen::Disabled) + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblen::Enabled) + } +} +#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblx { + #[doc = "0: PWM_X double pulse disabled."] + Disabled = 0, + #[doc = "1: PWM_X double pulse enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] +pub type DblxR = crate::BitReader; +impl DblxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblx { + match self.bits { + false => Dblx::Disabled, + true => Dblx::Enabled, + } + } + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblx::Disabled + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblx::Enabled + } +} +#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] +pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; +impl<'a, REG> DblxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblx::Disabled) + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblx::Enabled) + } +} +#[doc = "Load Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldmod { + #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + NextPwmReload = 0, + #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + MtctrlLdokSet = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldmod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDMOD` reader - Load Mode Select"] +pub type LdmodR = crate::BitReader; +impl LdmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldmod { + match self.bits { + false => Ldmod::NextPwmReload, + true => Ldmod::MtctrlLdokSet, + } + } + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn is_next_pwm_reload(&self) -> bool { + *self == Ldmod::NextPwmReload + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn is_mtctrl_ldok_set(&self) -> bool { + *self == Ldmod::MtctrlLdokSet + } +} +#[doc = "Field `LDMOD` writer - Load Mode Select"] +pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; +impl<'a, REG> LdmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn next_pwm_reload(self) -> &'a mut crate::W { + self.variant(Ldmod::NextPwmReload) + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { + self.variant(Ldmod::MtctrlLdokSet) + } +} +#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Split { + #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + Disabled = 0, + #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Split) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitR = crate::BitReader; +impl SplitR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Split { + match self.bits { + false => Split::Disabled, + true => Split::Enabled, + } + } + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Split::Disabled + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Split::Enabled + } +} +#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; +impl<'a, REG> SplitW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Split::Disabled) + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Split::Enabled) + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Prsc { + #[doc = "0: Prescaler 1"] + One = 0, + #[doc = "1: Prescaler 2"] + Two = 1, + #[doc = "2: Prescaler 4"] + Four = 2, + #[doc = "3: Prescaler 8"] + Eight = 3, + #[doc = "4: Prescaler 16"] + Sixteen = 4, + #[doc = "5: Prescaler 32"] + Thirtytwo = 5, + #[doc = "6: Prescaler 64"] + Sixtyfour = 6, + #[doc = "7: Prescaler 128"] + Hundredtwentyeight = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Prsc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Prsc { + type Ux = u8; +} +impl crate::IsEnum for Prsc {} +#[doc = "Field `PRSC` reader - Prescaler"] +pub type PrscR = crate::FieldReader; +impl PrscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prsc { + match self.bits { + 0 => Prsc::One, + 1 => Prsc::Two, + 2 => Prsc::Four, + 3 => Prsc::Eight, + 4 => Prsc::Sixteen, + 5 => Prsc::Thirtytwo, + 6 => Prsc::Sixtyfour, + 7 => Prsc::Hundredtwentyeight, + _ => unreachable!(), + } + } + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Prsc::One + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn is_two(&self) -> bool { + *self == Prsc::Two + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn is_four(&self) -> bool { + *self == Prsc::Four + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn is_eight(&self) -> bool { + *self == Prsc::Eight + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn is_sixteen(&self) -> bool { + *self == Prsc::Sixteen + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn is_thirtytwo(&self) -> bool { + *self == Prsc::Thirtytwo + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn is_sixtyfour(&self) -> bool { + *self == Prsc::Sixtyfour + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn is_hundredtwentyeight(&self) -> bool { + *self == Prsc::Hundredtwentyeight + } +} +#[doc = "Field `PRSC` writer - Prescaler"] +pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; +impl<'a, REG> PrscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn one(self) -> &'a mut crate::W { + self.variant(Prsc::One) + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn two(self) -> &'a mut crate::W { + self.variant(Prsc::Two) + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn four(self) -> &'a mut crate::W { + self.variant(Prsc::Four) + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn eight(self) -> &'a mut crate::W { + self.variant(Prsc::Eight) + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn sixteen(self) -> &'a mut crate::W { + self.variant(Prsc::Sixteen) + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn thirtytwo(self) -> &'a mut crate::W { + self.variant(Prsc::Thirtytwo) + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn sixtyfour(self) -> &'a mut crate::W { + self.variant(Prsc::Sixtyfour) + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn hundredtwentyeight(self) -> &'a mut crate::W { + self.variant(Prsc::Hundredtwentyeight) + } +} +#[doc = "Compare Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Compmode { + #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + EqualTo = 0, + #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + EqualToOrGreaterThan = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Compmode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPMODE` reader - Compare Mode"] +pub type CompmodeR = crate::BitReader; +impl CompmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Compmode { + match self.bits { + false => Compmode::EqualTo, + true => Compmode::EqualToOrGreaterThan, + } + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn is_equal_to(&self) -> bool { + *self == Compmode::EqualTo + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn is_equal_to_or_greater_than(&self) -> bool { + *self == Compmode::EqualToOrGreaterThan + } +} +#[doc = "Field `COMPMODE` writer - Compare Mode"] +pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; +impl<'a, REG> CompmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn equal_to(self) -> &'a mut crate::W { + self.variant(Compmode::EqualTo) + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { + self.variant(Compmode::EqualToOrGreaterThan) + } +} +#[doc = "Field `DT` reader - Deadtime"] +pub type DtR = crate::FieldReader; +#[doc = "Full Cycle Reload\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Full { + #[doc = "0: Full-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Full-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FULL` reader - Full Cycle Reload"] +pub type FullR = crate::BitReader; +impl FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Full { + match self.bits { + false => Full::Disabled, + true => Full::Enabled, + } + } + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Full::Disabled + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Full::Enabled + } +} +#[doc = "Field `FULL` writer - Full Cycle Reload"] +pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; +impl<'a, REG> FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Full::Disabled) + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Full::Enabled) + } +} +#[doc = "Half Cycle Reload\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Half { + #[doc = "0: Half-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Half-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Half) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALF` reader - Half Cycle Reload"] +pub type HalfR = crate::BitReader; +impl HalfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Half { + match self.bits { + false => Half::Disabled, + true => Half::Enabled, + } + } + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Half::Disabled + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Half::Enabled + } +} +#[doc = "Field `HALF` writer - Half Cycle Reload"] +pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; +impl<'a, REG> HalfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Half::Disabled) + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Half::Enabled) + } +} +#[doc = "Load Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ldfq { + #[doc = "0: Every PWM opportunity"] + Everypwm = 0, + #[doc = "1: Every 2 PWM opportunities"] + Every2pwm = 1, + #[doc = "2: Every 3 PWM opportunities"] + Every3pwm = 2, + #[doc = "3: Every 4 PWM opportunities"] + Every4pwm = 3, + #[doc = "4: Every 5 PWM opportunities"] + Every5pwm = 4, + #[doc = "5: Every 6 PWM opportunities"] + Every6pwm = 5, + #[doc = "6: Every 7 PWM opportunities"] + Every7pwm = 6, + #[doc = "7: Every 8 PWM opportunities"] + Every8pwm = 7, + #[doc = "8: Every 9 PWM opportunities"] + Every9pwm = 8, + #[doc = "9: Every 10 PWM opportunities"] + Every10pwm = 9, + #[doc = "10: Every 11 PWM opportunities"] + Every11pwm = 10, + #[doc = "11: Every 12 PWM opportunities"] + Every12pwm = 11, + #[doc = "12: Every 13 PWM opportunities"] + Every13pwm = 12, + #[doc = "13: Every 14 PWM opportunities"] + Every14pwm = 13, + #[doc = "14: Every 15 PWM opportunities"] + Every15pwm = 14, + #[doc = "15: Every 16 PWM opportunities"] + Every16pwm = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ldfq) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ldfq { + type Ux = u8; +} +impl crate::IsEnum for Ldfq {} +#[doc = "Field `LDFQ` reader - Load Frequency"] +pub type LdfqR = crate::FieldReader; +impl LdfqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldfq { + match self.bits { + 0 => Ldfq::Everypwm, + 1 => Ldfq::Every2pwm, + 2 => Ldfq::Every3pwm, + 3 => Ldfq::Every4pwm, + 4 => Ldfq::Every5pwm, + 5 => Ldfq::Every6pwm, + 6 => Ldfq::Every7pwm, + 7 => Ldfq::Every8pwm, + 8 => Ldfq::Every9pwm, + 9 => Ldfq::Every10pwm, + 10 => Ldfq::Every11pwm, + 11 => Ldfq::Every12pwm, + 12 => Ldfq::Every13pwm, + 13 => Ldfq::Every14pwm, + 14 => Ldfq::Every15pwm, + 15 => Ldfq::Every16pwm, + _ => unreachable!(), + } + } + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Ldfq::Everypwm + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn is_every2pwm(&self) -> bool { + *self == Ldfq::Every2pwm + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn is_every3pwm(&self) -> bool { + *self == Ldfq::Every3pwm + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn is_every4pwm(&self) -> bool { + *self == Ldfq::Every4pwm + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn is_every5pwm(&self) -> bool { + *self == Ldfq::Every5pwm + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn is_every6pwm(&self) -> bool { + *self == Ldfq::Every6pwm + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn is_every7pwm(&self) -> bool { + *self == Ldfq::Every7pwm + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn is_every8pwm(&self) -> bool { + *self == Ldfq::Every8pwm + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn is_every9pwm(&self) -> bool { + *self == Ldfq::Every9pwm + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn is_every10pwm(&self) -> bool { + *self == Ldfq::Every10pwm + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn is_every11pwm(&self) -> bool { + *self == Ldfq::Every11pwm + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn is_every12pwm(&self) -> bool { + *self == Ldfq::Every12pwm + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn is_every13pwm(&self) -> bool { + *self == Ldfq::Every13pwm + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn is_every14pwm(&self) -> bool { + *self == Ldfq::Every14pwm + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn is_every15pwm(&self) -> bool { + *self == Ldfq::Every15pwm + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn is_every16pwm(&self) -> bool { + *self == Ldfq::Every16pwm + } +} +#[doc = "Field `LDFQ` writer - Load Frequency"] +pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; +impl<'a, REG> LdfqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Everypwm) + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn every2pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every2pwm) + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn every3pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every3pwm) + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn every4pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every4pwm) + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn every5pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every5pwm) + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn every6pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every6pwm) + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn every7pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every7pwm) + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn every8pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every8pwm) + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn every9pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every9pwm) + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn every10pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every10pwm) + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn every11pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every11pwm) + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn every12pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every12pwm) + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn every13pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every13pwm) + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn every14pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every14pwm) + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn every15pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every15pwm) + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn every16pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every16pwm) + } +} +impl R { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&self) -> DblenR { + DblenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&self) -> DblxR { + DblxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&self) -> LdmodR { + LdmodR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&self) -> SplitR { + SplitR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&self) -> PrscR { + PrscR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&self) -> CompmodeR { + CompmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Deadtime"] + #[inline(always)] + pub fn dt(&self) -> DtR { + DtR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&self) -> FullR { + FullR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&self) -> HalfR { + HalfR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&self) -> LdfqR { + LdfqR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&mut self) -> DblenW { + DblenW::new(self, 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&mut self) -> DblxW { + DblxW::new(self, 1) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&mut self) -> LdmodW { + LdmodW::new(self, 2) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&mut self) -> SplitW { + SplitW::new(self, 3) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&mut self) -> PrscW { + PrscW::new(self, 4) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&mut self) -> CompmodeW { + CompmodeW::new(self, 7) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&mut self) -> FullW { + FullW::new(self, 10) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&mut self) -> HalfW { + HalfW::new(self, 11) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&mut self) -> LdfqW { + LdfqW::new(self, 12) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1ctrlSpec; +impl crate::RegisterSpec for Sm1ctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1ctrl::R`](R) reader structure"] +impl crate::Readable for Sm1ctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1ctrl::W`](W) writer structure"] +impl crate::Writable for Sm1ctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1CTRL to value 0x0400"] +impl crate::Resettable for Sm1ctrlSpec { + const RESET_VALUE: u16 = 0x0400; +} diff --git a/mcxa276-pac/src/flexpwm0/sm1ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm1ctrl2.rs new file mode 100644 index 000000000..f3a7ec0fe --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1ctrl2.rs @@ -0,0 +1,607 @@ +#[doc = "Register `SM1CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM1CTRL2` writer"] +pub type W = crate::W; +#[doc = "Clock Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ClkSel { + #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] + Ipbus = 0, + #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] + ExtClk = 1, + #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + AuxClk = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ClkSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ClkSel { + type Ux = u8; +} +impl crate::IsEnum for ClkSel {} +#[doc = "Field `CLK_SEL` reader - Clock Source Select"] +pub type ClkSelR = crate::FieldReader; +impl ClkSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ClkSel::Ipbus), + 1 => Some(ClkSel::ExtClk), + 2 => Some(ClkSel::AuxClk), + _ => None, + } + } + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ipbus(&self) -> bool { + *self == ClkSel::Ipbus + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ext_clk(&self) -> bool { + *self == ClkSel::ExtClk + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn is_aux_clk(&self) -> bool { + *self == ClkSel::AuxClk + } +} +#[doc = "Field `CLK_SEL` writer - Clock Source Select"] +pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; +impl<'a, REG> ClkSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ipbus(self) -> &'a mut crate::W { + self.variant(ClkSel::Ipbus) + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ext_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::ExtClk) + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn aux_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::AuxClk) + } +} +#[doc = "Reload Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ReloadSel { + #[doc = "0: The local RELOAD signal is used to reload registers."] + Local = 0, + #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + Master = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ReloadSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] +pub type ReloadSelR = crate::BitReader; +impl ReloadSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ReloadSel { + match self.bits { + false => ReloadSel::Local, + true => ReloadSel::Master, + } + } + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ReloadSel::Local + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ReloadSel::Master + } +} +#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] +pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; +impl<'a, REG> ReloadSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ReloadSel::Local) + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ReloadSel::Master) + } +} +#[doc = "Force Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ForceSel { + #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + Local = 0, + #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + Master = 1, + #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + LocalReload = 2, + #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterReload = 3, + #[doc = "4: The local sync signal from this submodule is used to force updates."] + LocalSync = 4, + #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterSync = 5, + #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + ExtForce = 6, + #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + ExtSync = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ForceSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ForceSel { + type Ux = u8; +} +impl crate::IsEnum for ForceSel {} +#[doc = "Field `FORCE_SEL` reader - Force Select"] +pub type ForceSelR = crate::FieldReader; +impl ForceSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ForceSel { + match self.bits { + 0 => ForceSel::Local, + 1 => ForceSel::Master, + 2 => ForceSel::LocalReload, + 3 => ForceSel::MasterReload, + 4 => ForceSel::LocalSync, + 5 => ForceSel::MasterSync, + 6 => ForceSel::ExtForce, + 7 => ForceSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ForceSel::Local + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ForceSel::Master + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == ForceSel::LocalReload + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == ForceSel::MasterReload + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == ForceSel::LocalSync + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == ForceSel::MasterSync + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_force(&self) -> bool { + *self == ForceSel::ExtForce + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == ForceSel::ExtSync + } +} +#[doc = "Field `FORCE_SEL` writer - Force Select"] +pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; +impl<'a, REG> ForceSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ForceSel::Local) + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ForceSel::Master) + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalReload) + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterReload) + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalSync) + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterSync) + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_force(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtForce) + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtSync) + } +} +#[doc = "Field `FORCE` reader - Force Initialization"] +pub type ForceR = crate::BitReader; +#[doc = "Field `FORCE` writer - Force Initialization"] +pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Force Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frcen { + #[doc = "0: Initialization from a FORCE_OUT is disabled."] + Disabled = 0, + #[doc = "1: Initialization from a FORCE_OUT is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRCEN` reader - Force Enable"] +pub type FrcenR = crate::BitReader; +impl FrcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frcen { + match self.bits { + false => Frcen::Disabled, + true => Frcen::Enabled, + } + } + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Frcen::Disabled + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Frcen::Enabled + } +} +#[doc = "Field `FRCEN` writer - Force Enable"] +pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; +impl<'a, REG> FrcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Frcen::Disabled) + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Frcen::Enabled) + } +} +#[doc = "Initialization Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum InitSel { + #[doc = "0: Local sync (PWM_X) causes initialization."] + PwmX = 0, + #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + MasterReload = 1, + #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + MasterSync = 2, + #[doc = "3: EXT_SYNC causes initialization."] + ExtSync = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: InitSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for InitSel { + type Ux = u8; +} +impl crate::IsEnum for InitSel {} +#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] +pub type InitSelR = crate::FieldReader; +impl InitSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InitSel { + match self.bits { + 0 => InitSel::PwmX, + 1 => InitSel::MasterReload, + 2 => InitSel::MasterSync, + 3 => InitSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InitSel::PwmX + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == InitSel::MasterReload + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == InitSel::MasterSync + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == InitSel::ExtSync + } +} +#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] +pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; +impl<'a, REG> InitSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InitSel::PwmX) + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(InitSel::MasterReload) + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(InitSel::MasterSync) + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(InitSel::ExtSync) + } +} +#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] +pub type PwmxInitR = crate::BitReader; +#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] +pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] +pub type Pwm45InitR = crate::BitReader; +#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] +pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] +pub type Pwm23InitR = crate::BitReader; +#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] +pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Indep { + #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] + Complementary = 0, + #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] + Independent = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Indep) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] +pub type IndepR = crate::BitReader; +impl IndepR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Indep { + match self.bits { + false => Indep::Complementary, + true => Indep::Independent, + } + } + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn is_complementary(&self) -> bool { + *self == Indep::Complementary + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn is_independent(&self) -> bool { + *self == Indep::Independent + } +} +#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] +pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; +impl<'a, REG> IndepW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn complementary(self) -> &'a mut crate::W { + self.variant(Indep::Complementary) + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn independent(self) -> &'a mut crate::W { + self.variant(Indep::Independent) + } +} +#[doc = "Field `DBGEN` reader - Debug Enable"] +pub type DbgenR = crate::BitReader; +#[doc = "Field `DBGEN` writer - Debug Enable"] +pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&self) -> ClkSelR { + ClkSelR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&self) -> ReloadSelR { + ReloadSelR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&self) -> ForceSelR { + ForceSelR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&self) -> ForceR { + ForceR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&self) -> FrcenR { + FrcenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&self) -> InitSelR { + InitSelR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&self) -> PwmxInitR { + PwmxInitR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&self) -> Pwm45InitR { + Pwm45InitR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&self) -> Pwm23InitR { + Pwm23InitR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&self) -> IndepR { + IndepR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&self) -> DbgenR { + DbgenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&mut self) -> ClkSelW { + ClkSelW::new(self, 0) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&mut self) -> ReloadSelW { + ReloadSelW::new(self, 2) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&mut self) -> ForceSelW { + ForceSelW::new(self, 3) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&mut self) -> ForceW { + ForceW::new(self, 6) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&mut self) -> FrcenW { + FrcenW::new(self, 7) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&mut self) -> InitSelW { + InitSelW::new(self, 8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&mut self) -> PwmxInitW { + PwmxInitW::new(self, 10) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&mut self) -> Pwm45InitW { + Pwm45InitW::new(self, 11) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&mut self) -> Pwm23InitW { + Pwm23InitW::new(self, 12) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&mut self) -> IndepW { + IndepW::new(self, 13) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&mut self) -> DbgenW { + DbgenW::new(self, 15) + } +} +#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1ctrl2Spec; +impl crate::RegisterSpec for Sm1ctrl2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1ctrl2::R`](R) reader structure"] +impl crate::Readable for Sm1ctrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1ctrl2::W`](W) writer structure"] +impl crate::Writable for Sm1ctrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1CTRL2 to value 0"] +impl crate::Resettable for Sm1ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval0.rs b/mcxa276-pac/src/flexpwm0/sm1cval0.rs new file mode 100644 index 000000000..fff0002f4 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1cval0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM1CVAL0` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] +pub type Captval0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 0"] + #[inline(always)] + pub fn captval0(&self) -> Captval0R { + Captval0R::new(self.bits) + } +} +#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1cval0Spec; +impl crate::RegisterSpec for Sm1cval0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1cval0::R`](R) reader structure"] +impl crate::Readable for Sm1cval0Spec {} +#[doc = "`reset()` method sets SM1CVAL0 to value 0"] +impl crate::Resettable for Sm1cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs new file mode 100644 index 000000000..4189165fe --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM1CVAL0CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] +pub type Cval0cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 0 Cycle"] + #[inline(always)] + pub fn cval0cyc(&self) -> Cval0cycR { + Cval0cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1cval0cycSpec; +impl crate::RegisterSpec for Sm1cval0cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1cval0cyc::R`](R) reader structure"] +impl crate::Readable for Sm1cval0cycSpec {} +#[doc = "`reset()` method sets SM1CVAL0CYC to value 0"] +impl crate::Resettable for Sm1cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval1.rs b/mcxa276-pac/src/flexpwm0/sm1cval1.rs new file mode 100644 index 000000000..9b04841aa --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1cval1.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM1CVAL1` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] +pub type Captval1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 1"] + #[inline(always)] + pub fn captval1(&self) -> Captval1R { + Captval1R::new(self.bits) + } +} +#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1cval1Spec; +impl crate::RegisterSpec for Sm1cval1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1cval1::R`](R) reader structure"] +impl crate::Readable for Sm1cval1Spec {} +#[doc = "`reset()` method sets SM1CVAL1 to value 0"] +impl crate::Resettable for Sm1cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs new file mode 100644 index 000000000..7127a47c1 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM1CVAL1CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] +pub type Cval1cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 1 Cycle"] + #[inline(always)] + pub fn cval1cyc(&self) -> Cval1cycR { + Cval1cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1cval1cycSpec; +impl crate::RegisterSpec for Sm1cval1cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1cval1cyc::R`](R) reader structure"] +impl crate::Readable for Sm1cval1cycSpec {} +#[doc = "`reset()` method sets SM1CVAL1CYC to value 0"] +impl crate::Resettable for Sm1cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1dismap0.rs b/mcxa276-pac/src/flexpwm0/sm1dismap0.rs new file mode 100644 index 000000000..cf2fa86f5 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1dismap0.rs @@ -0,0 +1,65 @@ +#[doc = "Register `SM1DISMAP0` reader"] +pub type R = crate::R; +#[doc = "Register `SM1DISMAP0` writer"] +pub type W = crate::W; +#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] +pub type Dis0aR = crate::FieldReader; +#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] +pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] +pub type Dis0bR = crate::FieldReader; +#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] +pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] +pub type Dis0xR = crate::FieldReader; +#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] +pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&self) -> Dis0aR { + Dis0aR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&self) -> Dis0bR { + Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&self) -> Dis0xR { + Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&mut self) -> Dis0aW { + Dis0aW::new(self, 0) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&mut self) -> Dis0bW { + Dis0bW::new(self, 4) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&mut self) -> Dis0xW { + Dis0xW::new(self, 8) + } +} +#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1dismap0Spec; +impl crate::RegisterSpec for Sm1dismap0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1dismap0::R`](R) reader structure"] +impl crate::Readable for Sm1dismap0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1dismap0::W`](W) writer structure"] +impl crate::Writable for Sm1dismap0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1DISMAP0 to value 0xffff"] +impl crate::Resettable for Sm1dismap0Spec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm1dmaen.rs b/mcxa276-pac/src/flexpwm0/sm1dmaen.rs new file mode 100644 index 000000000..7d907159e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1dmaen.rs @@ -0,0 +1,271 @@ +#[doc = "Register `SM1DMAEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM1DMAEN` writer"] +pub type W = crate::W; +#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] +pub type Cx0deR = crate::BitReader; +#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] +pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] +pub type Cx1deR = crate::BitReader; +#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] +pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Captde { + #[doc = "0: Read DMA requests disabled."] + Disabled = 0, + #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + Exceedfifo = 1, + #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] + LocalSync = 2, + #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] + LocalReload = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Captde) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Captde { + type Ux = u8; +} +impl crate::IsEnum for Captde {} +#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] +pub type CaptdeR = crate::FieldReader; +impl CaptdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Captde { + match self.bits { + 0 => Captde::Disabled, + 1 => Captde::Exceedfifo, + 2 => Captde::LocalSync, + 3 => Captde::LocalReload, + _ => unreachable!(), + } + } + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Captde::Disabled + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn is_exceedfifo(&self) -> bool { + *self == Captde::Exceedfifo + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == Captde::LocalSync + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == Captde::LocalReload + } +} +#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] +pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; +impl<'a, REG> CaptdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Captde::Disabled) + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn exceedfifo(self) -> &'a mut crate::W { + self.variant(Captde::Exceedfifo) + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(Captde::LocalSync) + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(Captde::LocalReload) + } +} +#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fand { + #[doc = "0: Selected FIFO watermarks are OR'ed together."] + Or = 0, + #[doc = "1: Selected FIFO watermarks are AND'ed together."] + And = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fand) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] +pub type FandR = crate::BitReader; +impl FandR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fand { + match self.bits { + false => Fand::Or, + true => Fand::And, + } + } + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn is_or(&self) -> bool { + *self == Fand::Or + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn is_and(&self) -> bool { + *self == Fand::And + } +} +#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] +pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; +impl<'a, REG> FandW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn or(self) -> &'a mut crate::W { + self.variant(Fand::Or) + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn and(self) -> &'a mut crate::W { + self.variant(Fand::And) + } +} +#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Valde { + #[doc = "0: DMA write requests disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Valde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] +pub type ValdeR = crate::BitReader; +impl ValdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Valde { + match self.bits { + false => Valde::Disabled, + true => Valde::Enabled, + } + } + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Valde::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Valde::Enabled + } +} +#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] +pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; +impl<'a, REG> ValdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Valde::Disabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Valde::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&self) -> Cx0deR { + Cx0deR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&self) -> Cx1deR { + Cx1deR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&self) -> CaptdeR { + CaptdeR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&self) -> FandR { + FandR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&self) -> ValdeR { + ValdeR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&mut self) -> Cx0deW { + Cx0deW::new(self, 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&mut self) -> Cx1deW { + Cx1deW::new(self, 1) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&mut self) -> CaptdeW { + CaptdeW::new(self, 6) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&mut self) -> FandW { + FandW::new(self, 8) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&mut self) -> ValdeW { + ValdeW::new(self, 9) + } +} +#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1dmaenSpec; +impl crate::RegisterSpec for Sm1dmaenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1dmaen::R`](R) reader structure"] +impl crate::Readable for Sm1dmaenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1dmaen::W`](W) writer structure"] +impl crate::Writable for Sm1dmaenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1DMAEN to value 0"] +impl crate::Resettable for Sm1dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs new file mode 100644 index 000000000..79641844e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM1DTCNT0` reader"] +pub type R = crate::R; +#[doc = "Register `SM1DTCNT0` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] +pub type Dtcnt0R = crate::FieldReader; +#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] +pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&self) -> Dtcnt0R { + Dtcnt0R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&mut self) -> Dtcnt0W { + Dtcnt0W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1dtcnt0Spec; +impl crate::RegisterSpec for Sm1dtcnt0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1dtcnt0::R`](R) reader structure"] +impl crate::Readable for Sm1dtcnt0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1dtcnt0::W`](W) writer structure"] +impl crate::Writable for Sm1dtcnt0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1DTCNT0 to value 0x07ff"] +impl crate::Resettable for Sm1dtcnt0Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs new file mode 100644 index 000000000..6c4da6a1e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM1DTCNT1` reader"] +pub type R = crate::R; +#[doc = "Register `SM1DTCNT1` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] +pub type Dtcnt1R = crate::FieldReader; +#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] +pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&self) -> Dtcnt1R { + Dtcnt1R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&mut self) -> Dtcnt1W { + Dtcnt1W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1dtcnt1Spec; +impl crate::RegisterSpec for Sm1dtcnt1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1dtcnt1::R`](R) reader structure"] +impl crate::Readable for Sm1dtcnt1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1dtcnt1::W`](W) writer structure"] +impl crate::Writable for Sm1dtcnt1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1DTCNT1 to value 0x07ff"] +impl crate::Resettable for Sm1dtcnt1Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm1init.rs b/mcxa276-pac/src/flexpwm0/sm1init.rs new file mode 100644 index 000000000..7aa2d506e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1init.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1INIT` reader"] +pub type R = crate::R; +#[doc = "Register `SM1INIT` writer"] +pub type W = crate::W; +#[doc = "Field `INIT` reader - Initial Count Register Bits"] +pub type InitR = crate::FieldReader; +#[doc = "Field `INIT` writer - Initial Count Register Bits"] +pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&self) -> InitR { + InitR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&mut self) -> InitW { + InitW::new(self, 0) + } +} +#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1initSpec; +impl crate::RegisterSpec for Sm1initSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1init::R`](R) reader structure"] +impl crate::Readable for Sm1initSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1init::W`](W) writer structure"] +impl crate::Writable for Sm1initSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1INIT to value 0"] +impl crate::Resettable for Sm1initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1inten.rs b/mcxa276-pac/src/flexpwm0/sm1inten.rs new file mode 100644 index 000000000..3ede52ad7 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1inten.rs @@ -0,0 +1,343 @@ +#[doc = "Register `SM1INTEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM1INTEN` writer"] +pub type W = crate::W; +#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpie { + #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + Disabled = 0, + #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + Enabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpie) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpie { + type Ux = u8; +} +impl crate::IsEnum for Cmpie {} +#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] +pub type CmpieR = crate::FieldReader; +impl CmpieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpie::Disabled), + 1 => Some(Cmpie::Enabled), + _ => None, + } + } + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmpie::Disabled + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmpie::Enabled + } +} +#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] +pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; +impl<'a, REG> CmpieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Disabled) + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Enabled) + } +} +#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx0ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx0ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] +pub type Cx0ieR = crate::BitReader; +impl Cx0ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx0ie { + match self.bits { + false => Cx0ie::Disabled, + true => Cx0ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx0ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx0ie::Enabled + } +} +#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] +pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; +impl<'a, REG> Cx0ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Enabled) + } +} +#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx1ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx1ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] +pub type Cx1ieR = crate::BitReader; +impl Cx1ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx1ie { + match self.bits { + false => Cx1ie::Disabled, + true => Cx1ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx1ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx1ie::Enabled + } +} +#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] +pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; +impl<'a, REG> Cx1ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Enabled) + } +} +#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rie { + #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RIE` reader - Reload Interrupt Enable"] +pub type RieR = crate::BitReader; +impl RieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rie { + match self.bits { + false => Rie::Disabled, + true => Rie::Enabled, + } + } + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rie::Disabled + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rie::Enabled + } +} +#[doc = "Field `RIE` writer - Reload Interrupt Enable"] +pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; +impl<'a, REG> RieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rie::Disabled) + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rie::Enabled) + } +} +#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reie { + #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] +pub type ReieR = crate::BitReader; +impl ReieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reie { + match self.bits { + false => Reie::Disabled, + true => Reie::Enabled, + } + } + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Reie::Disabled + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Reie::Enabled + } +} +#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] +pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; +impl<'a, REG> ReieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Reie::Disabled) + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Reie::Enabled) + } +} +impl R { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&self) -> CmpieR { + CmpieR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&self) -> Cx0ieR { + Cx0ieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&self) -> Cx1ieR { + Cx1ieR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RieR { + RieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&self) -> ReieR { + ReieR::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&mut self) -> CmpieW { + CmpieW::new(self, 0) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&mut self) -> Cx0ieW { + Cx0ieW::new(self, 6) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&mut self) -> Cx1ieW { + Cx1ieW::new(self, 7) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&mut self) -> RieW { + RieW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&mut self) -> ReieW { + ReieW::new(self, 13) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1intenSpec; +impl crate::RegisterSpec for Sm1intenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1inten::R`](R) reader structure"] +impl crate::Readable for Sm1intenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1inten::W`](W) writer structure"] +impl crate::Writable for Sm1intenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1INTEN to value 0"] +impl crate::Resettable for Sm1intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1octrl.rs b/mcxa276-pac/src/flexpwm0/sm1octrl.rs new file mode 100644 index 000000000..a5f6c4d2c --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1octrl.rs @@ -0,0 +1,519 @@ +#[doc = "Register `SM1OCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM1OCTRL` writer"] +pub type W = crate::W; +#[doc = "PWM_X Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmxfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmxfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmxfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmxfs {} +#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] +pub type PwmxfsR = crate::FieldReader; +impl PwmxfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmxfs { + match self.bits { + 0 => Pwmxfs::Logic0, + 1 => Pwmxfs::Logic1, + 2 => Pwmxfs::Tristated2, + 3 => Pwmxfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmxfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmxfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmxfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmxfs::Tristated3 + } +} +#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] +pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; +impl<'a, REG> PwmxfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated3) + } +} +#[doc = "PWM_B Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmbfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmbfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmbfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmbfs {} +#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] +pub type PwmbfsR = crate::FieldReader; +impl PwmbfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmbfs { + match self.bits { + 0 => Pwmbfs::Logic0, + 1 => Pwmbfs::Logic1, + 2 => Pwmbfs::Tristated2, + 3 => Pwmbfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmbfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmbfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmbfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmbfs::Tristated3 + } +} +#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] +pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; +impl<'a, REG> PwmbfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated3) + } +} +#[doc = "PWM_A Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmafs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmafs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmafs { + type Ux = u8; +} +impl crate::IsEnum for Pwmafs {} +#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] +pub type PwmafsR = crate::FieldReader; +impl PwmafsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmafs { + match self.bits { + 0 => Pwmafs::Logic0, + 1 => Pwmafs::Logic1, + 2 => Pwmafs::Tristated2, + 3 => Pwmafs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmafs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmafs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmafs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmafs::Tristated3 + } +} +#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] +pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; +impl<'a, REG> PwmafsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated3) + } +} +#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polx { + #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLX` reader - PWM_X Output Polarity"] +pub type PolxR = crate::BitReader; +impl PolxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polx { + match self.bits { + false => Polx::NotInverted, + true => Polx::Inverted, + } + } + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polx::NotInverted + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polx::Inverted + } +} +#[doc = "Field `POLX` writer - PWM_X Output Polarity"] +pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; +impl<'a, REG> PolxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polx::NotInverted) + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polx::Inverted) + } +} +#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polb { + #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLB` reader - PWM_B Output Polarity"] +pub type PolbR = crate::BitReader; +impl PolbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polb { + match self.bits { + false => Polb::NotInverted, + true => Polb::Inverted, + } + } + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polb::NotInverted + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polb::Inverted + } +} +#[doc = "Field `POLB` writer - PWM_B Output Polarity"] +pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; +impl<'a, REG> PolbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polb::NotInverted) + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polb::Inverted) + } +} +#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pola { + #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pola) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLA` reader - PWM_A Output Polarity"] +pub type PolaR = crate::BitReader; +impl PolaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pola { + match self.bits { + false => Pola::NotInverted, + true => Pola::Inverted, + } + } + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Pola::NotInverted + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Pola::Inverted + } +} +#[doc = "Field `POLA` writer - PWM_A Output Polarity"] +pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; +impl<'a, REG> PolaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Pola::NotInverted) + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Pola::Inverted) + } +} +#[doc = "Field `PWMX_IN` reader - PWM_X Input"] +pub type PwmxInR = crate::BitReader; +#[doc = "Field `PWMB_IN` reader - PWM_B Input"] +pub type PwmbInR = crate::BitReader; +#[doc = "Field `PWMA_IN` reader - PWM_A Input"] +pub type PwmaInR = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&self) -> PwmxfsR { + PwmxfsR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&self) -> PwmbfsR { + PwmbfsR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&self) -> PwmafsR { + PwmafsR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&self) -> PolxR { + PolxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&self) -> PolbR { + PolbR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&self) -> PolaR { + PolaR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - PWM_X Input"] + #[inline(always)] + pub fn pwmx_in(&self) -> PwmxInR { + PwmxInR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PWM_B Input"] + #[inline(always)] + pub fn pwmb_in(&self) -> PwmbInR { + PwmbInR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - PWM_A Input"] + #[inline(always)] + pub fn pwma_in(&self) -> PwmaInR { + PwmaInR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&mut self) -> PwmxfsW { + PwmxfsW::new(self, 0) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&mut self) -> PwmbfsW { + PwmbfsW::new(self, 2) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&mut self) -> PwmafsW { + PwmafsW::new(self, 4) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&mut self) -> PolxW { + PolxW::new(self, 8) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&mut self) -> PolbW { + PolbW::new(self, 9) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&mut self) -> PolaW { + PolaW::new(self, 10) + } +} +#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1octrlSpec; +impl crate::RegisterSpec for Sm1octrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1octrl::R`](R) reader structure"] +impl crate::Readable for Sm1octrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1octrl::W`](W) writer structure"] +impl crate::Writable for Sm1octrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1OCTRL to value 0"] +impl crate::Resettable for Sm1octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1phasedly.rs b/mcxa276-pac/src/flexpwm0/sm1phasedly.rs new file mode 100644 index 000000000..a12b72dc8 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1phasedly.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1PHASEDLY` reader"] +pub type R = crate::R; +#[doc = "Register `SM1PHASEDLY` writer"] +pub type W = crate::W; +#[doc = "Field `PHASEDLY` reader - Initial Count Register Bits"] +pub type PhasedlyR = crate::FieldReader; +#[doc = "Field `PHASEDLY` writer - Initial Count Register Bits"] +pub type PhasedlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn phasedly(&self) -> PhasedlyR { + PhasedlyR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn phasedly(&mut self) -> PhasedlyW { + PhasedlyW::new(self, 0) + } +} +#[doc = "Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1phasedly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1phasedly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1phasedlySpec; +impl crate::RegisterSpec for Sm1phasedlySpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1phasedly::R`](R) reader structure"] +impl crate::Readable for Sm1phasedlySpec {} +#[doc = "`write(|w| ..)` method takes [`sm1phasedly::W`](W) writer structure"] +impl crate::Writable for Sm1phasedlySpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1PHASEDLY to value 0"] +impl crate::Resettable for Sm1phasedlySpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1sts.rs b/mcxa276-pac/src/flexpwm0/sm1sts.rs new file mode 100644 index 000000000..f3d7abadd --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1sts.rs @@ -0,0 +1,287 @@ +#[doc = "Register `SM1STS` reader"] +pub type R = crate::R; +#[doc = "Register `SM1STS` writer"] +pub type W = crate::W; +#[doc = "Compare Flags\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpf { + #[doc = "0: No compare event has occurred for a particular VALx value."] + NoEvent = 0, + #[doc = "1: A compare event has occurred for a particular VALx value."] + Event = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpf { + type Ux = u8; +} +impl crate::IsEnum for Cmpf {} +#[doc = "Field `CMPF` reader - Compare Flags"] +pub type CmpfR = crate::FieldReader; +impl CmpfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpf::NoEvent), + 1 => Some(Cmpf::Event), + _ => None, + } + } + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_no_event(&self) -> bool { + *self == Cmpf::NoEvent + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == Cmpf::Event + } +} +#[doc = "Field `CMPF` writer - Compare Flags"] +pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; +impl<'a, REG> CmpfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn no_event(self) -> &'a mut crate::W { + self.variant(Cmpf::NoEvent) + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn event(self) -> &'a mut crate::W { + self.variant(Cmpf::Event) + } +} +#[doc = "Field `CFX0` reader - Capture Flag X0"] +pub type Cfx0R = crate::BitReader; +#[doc = "Field `CFX0` writer - Capture Flag X0"] +pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CFX1` reader - Capture Flag X1"] +pub type Cfx1R = crate::BitReader; +#[doc = "Field `CFX1` writer - Capture Flag X1"] +pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Reload Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rf { + #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] + NoFlag = 0, + #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RF` reader - Reload Flag"] +pub type RfR = crate::BitReader; +impl RfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rf { + match self.bits { + false => Rf::NoFlag, + true => Rf::Flag, + } + } + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Rf::NoFlag + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Rf::Flag + } +} +#[doc = "Field `RF` writer - Reload Flag"] +pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; +impl<'a, REG> RfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Rf::NoFlag) + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Rf::Flag) + } +} +#[doc = "Reload Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ref { + #[doc = "0: No reload error occurred."] + NoFlag = 0, + #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ref) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REF` reader - Reload Error Flag"] +pub type RefR = crate::BitReader; +impl RefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ref { + match self.bits { + false => Ref::NoFlag, + true => Ref::Flag, + } + } + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ref::NoFlag + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ref::Flag + } +} +#[doc = "Field `REF` writer - Reload Error Flag"] +pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; +impl<'a, REG> RefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Ref::NoFlag) + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Ref::Flag) + } +} +#[doc = "Registers Updated Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ruf { + #[doc = "0: No register update has occurred since last reload."] + NoFlag = 0, + #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ruf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RUF` reader - Registers Updated Flag"] +pub type RufR = crate::BitReader; +impl RufR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ruf { + match self.bits { + false => Ruf::NoFlag, + true => Ruf::Flag, + } + } + #[doc = "No register update has occurred since last reload."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ruf::NoFlag + } + #[doc = "At least one of the double buffered registers has been updated since the last reload."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ruf::Flag + } +} +impl R { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&self) -> CmpfR { + CmpfR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&self) -> Cfx0R { + Cfx0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&self) -> Cfx1R { + Cfx1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&self) -> RfR { + RfR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&self) -> RefR { + RefR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Registers Updated Flag"] + #[inline(always)] + pub fn ruf(&self) -> RufR { + RufR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&mut self) -> CmpfW { + CmpfW::new(self, 0) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&mut self) -> Cfx0W { + Cfx0W::new(self, 6) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&mut self) -> Cfx1W { + Cfx1W::new(self, 7) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&mut self) -> RfW { + RfW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&mut self) -> RefW { + RefW::new(self, 13) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1stsSpec; +impl crate::RegisterSpec for Sm1stsSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1sts::R`](R) reader structure"] +impl crate::Readable for Sm1stsSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1sts::W`](W) writer structure"] +impl crate::Writable for Sm1stsSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; +} +#[doc = "`reset()` method sets SM1STS to value 0"] +impl crate::Resettable for Sm1stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1tctrl.rs b/mcxa276-pac/src/flexpwm0/sm1tctrl.rs new file mode 100644 index 000000000..d7771b5ab --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1tctrl.rs @@ -0,0 +1,267 @@ +#[doc = "Register `SM1TCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM1TCTRL` writer"] +pub type W = crate::W; +#[doc = "Output Trigger Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OutTrigEn { + #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + Val0 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OutTrigEn) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OutTrigEn { + type Ux = u8; +} +impl crate::IsEnum for OutTrigEn {} +#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] +pub type OutTrigEnR = crate::FieldReader; +impl OutTrigEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(OutTrigEn::Val0), + _ => None, + } + } + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == OutTrigEn::Val0 + } +} +#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] +pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; +impl<'a, REG> OutTrigEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn val0(self) -> &'a mut crate::W { + self.variant(OutTrigEn::Val0) + } +} +#[doc = "Trigger Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trgfrq { + #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Everypwm = 0, + #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Finalpwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trgfrq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] +pub type TrgfrqR = crate::BitReader; +impl TrgfrqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgfrq { + match self.bits { + false => Trgfrq::Everypwm, + true => Trgfrq::Finalpwm, + } + } + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Trgfrq::Everypwm + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_finalpwm(&self) -> bool { + *self == Trgfrq::Finalpwm + } +} +#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] +pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; +impl<'a, REG> TrgfrqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Everypwm) + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn finalpwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Finalpwm) + } +} +#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwbot1 { + #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + PwmOutTrig1Signal = 0, + #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] + PwmbOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwbot1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] +pub type Pwbot1R = crate::BitReader; +impl Pwbot1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwbot1 { + match self.bits { + false => Pwbot1::PwmOutTrig1Signal, + true => Pwbot1::PwmbOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwm_out_trig1_signal(&self) -> bool { + *self == Pwbot1::PwmOutTrig1Signal + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwmb_output(&self) -> bool { + *self == Pwbot1::PwmbOutput + } +} +#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] +pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; +impl<'a, REG> Pwbot1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmOutTrig1Signal) + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwmb_output(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmbOutput) + } +} +#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwaot0 { + #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + PwmOutTrig0Signal = 0, + #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] + PwmaOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwaot0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] +pub type Pwaot0R = crate::BitReader; +impl Pwaot0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwaot0 { + match self.bits { + false => Pwaot0::PwmOutTrig0Signal, + true => Pwaot0::PwmaOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwm_out_trig0_signal(&self) -> bool { + *self == Pwaot0::PwmOutTrig0Signal + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwma_output(&self) -> bool { + *self == Pwaot0::PwmaOutput + } +} +#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] +pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; +impl<'a, REG> Pwaot0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmOutTrig0Signal) + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwma_output(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmaOutput) + } +} +impl R { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&self) -> OutTrigEnR { + OutTrigEnR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&self) -> TrgfrqR { + TrgfrqR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&self) -> Pwbot1R { + Pwbot1R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&self) -> Pwaot0R { + Pwaot0R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&mut self) -> OutTrigEnW { + OutTrigEnW::new(self, 0) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&mut self) -> TrgfrqW { + TrgfrqW::new(self, 12) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&mut self) -> Pwbot1W { + Pwbot1W::new(self, 14) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&mut self) -> Pwaot0W { + Pwaot0W::new(self, 15) + } +} +#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1tctrlSpec; +impl crate::RegisterSpec for Sm1tctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1tctrl::R`](R) reader structure"] +impl crate::Readable for Sm1tctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm1tctrl::W`](W) writer structure"] +impl crate::Writable for Sm1tctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1TCTRL to value 0"] +impl crate::Resettable for Sm1tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val0.rs b/mcxa276-pac/src/flexpwm0/sm1val0.rs new file mode 100644 index 000000000..4ac06c756 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1val0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1VAL0` reader"] +pub type R = crate::R; +#[doc = "Register `SM1VAL0` writer"] +pub type W = crate::W; +#[doc = "Field `VAL0` reader - Value 0"] +pub type Val0R = crate::FieldReader; +#[doc = "Field `VAL0` writer - Value 0"] +pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&self) -> Val0R { + Val0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&mut self) -> Val0W { + Val0W::new(self, 0) + } +} +#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1val0Spec; +impl crate::RegisterSpec for Sm1val0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1val0::R`](R) reader structure"] +impl crate::Readable for Sm1val0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1val0::W`](W) writer structure"] +impl crate::Writable for Sm1val0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1VAL0 to value 0"] +impl crate::Resettable for Sm1val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val1.rs b/mcxa276-pac/src/flexpwm0/sm1val1.rs new file mode 100644 index 000000000..9450fd208 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1val1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1VAL1` reader"] +pub type R = crate::R; +#[doc = "Register `SM1VAL1` writer"] +pub type W = crate::W; +#[doc = "Field `VAL1` reader - Value 1"] +pub type Val1R = crate::FieldReader; +#[doc = "Field `VAL1` writer - Value 1"] +pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&self) -> Val1R { + Val1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&mut self) -> Val1W { + Val1W::new(self, 0) + } +} +#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1val1Spec; +impl crate::RegisterSpec for Sm1val1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1val1::R`](R) reader structure"] +impl crate::Readable for Sm1val1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1val1::W`](W) writer structure"] +impl crate::Writable for Sm1val1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1VAL1 to value 0"] +impl crate::Resettable for Sm1val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val2.rs b/mcxa276-pac/src/flexpwm0/sm1val2.rs new file mode 100644 index 000000000..f25eef07e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1val2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1VAL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM1VAL2` writer"] +pub type W = crate::W; +#[doc = "Field `VAL2` reader - Value 2"] +pub type Val2R = crate::FieldReader; +#[doc = "Field `VAL2` writer - Value 2"] +pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&self) -> Val2R { + Val2R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&mut self) -> Val2W { + Val2W::new(self, 0) + } +} +#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1val2Spec; +impl crate::RegisterSpec for Sm1val2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1val2::R`](R) reader structure"] +impl crate::Readable for Sm1val2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1val2::W`](W) writer structure"] +impl crate::Writable for Sm1val2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1VAL2 to value 0"] +impl crate::Resettable for Sm1val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val3.rs b/mcxa276-pac/src/flexpwm0/sm1val3.rs new file mode 100644 index 000000000..fb3238584 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1val3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1VAL3` reader"] +pub type R = crate::R; +#[doc = "Register `SM1VAL3` writer"] +pub type W = crate::W; +#[doc = "Field `VAL3` reader - Value 3"] +pub type Val3R = crate::FieldReader; +#[doc = "Field `VAL3` writer - Value 3"] +pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&self) -> Val3R { + Val3R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&mut self) -> Val3W { + Val3W::new(self, 0) + } +} +#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1val3Spec; +impl crate::RegisterSpec for Sm1val3Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1val3::R`](R) reader structure"] +impl crate::Readable for Sm1val3Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1val3::W`](W) writer structure"] +impl crate::Writable for Sm1val3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1VAL3 to value 0"] +impl crate::Resettable for Sm1val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val4.rs b/mcxa276-pac/src/flexpwm0/sm1val4.rs new file mode 100644 index 000000000..17e62368b --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1val4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1VAL4` reader"] +pub type R = crate::R; +#[doc = "Register `SM1VAL4` writer"] +pub type W = crate::W; +#[doc = "Field `VAL4` reader - Value 4"] +pub type Val4R = crate::FieldReader; +#[doc = "Field `VAL4` writer - Value 4"] +pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&self) -> Val4R { + Val4R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&mut self) -> Val4W { + Val4W::new(self, 0) + } +} +#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1val4Spec; +impl crate::RegisterSpec for Sm1val4Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1val4::R`](R) reader structure"] +impl crate::Readable for Sm1val4Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1val4::W`](W) writer structure"] +impl crate::Writable for Sm1val4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1VAL4 to value 0"] +impl crate::Resettable for Sm1val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val5.rs b/mcxa276-pac/src/flexpwm0/sm1val5.rs new file mode 100644 index 000000000..cb367d28e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm1val5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM1VAL5` reader"] +pub type R = crate::R; +#[doc = "Register `SM1VAL5` writer"] +pub type W = crate::W; +#[doc = "Field `VAL5` reader - Value 5"] +pub type Val5R = crate::FieldReader; +#[doc = "Field `VAL5` writer - Value 5"] +pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&self) -> Val5R { + Val5R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&mut self) -> Val5W { + Val5W::new(self, 0) + } +} +#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm1val5Spec; +impl crate::RegisterSpec for Sm1val5Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm1val5::R`](R) reader structure"] +impl crate::Readable for Sm1val5Spec {} +#[doc = "`write(|w| ..)` method takes [`sm1val5::W`](W) writer structure"] +impl crate::Writable for Sm1val5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM1VAL5 to value 0"] +impl crate::Resettable for Sm1val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2captcompx.rs b/mcxa276-pac/src/flexpwm0/sm2captcompx.rs new file mode 100644 index 000000000..37563946f --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2captcompx.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SM2CAPTCOMPX` reader"] +pub type R = crate::R; +#[doc = "Register `SM2CAPTCOMPX` writer"] +pub type W = crate::W; +#[doc = "Field `EDGCMPX` reader - Edge Compare X"] +pub type EdgcmpxR = crate::FieldReader; +#[doc = "Field `EDGCMPX` writer - Edge Compare X"] +pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EDGCNTX` reader - Edge Counter X"] +pub type EdgcntxR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&self) -> EdgcmpxR { + EdgcmpxR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Edge Counter X"] + #[inline(always)] + pub fn edgcntx(&self) -> EdgcntxR { + EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&mut self) -> EdgcmpxW { + EdgcmpxW::new(self, 0) + } +} +#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2captcompxSpec; +impl crate::RegisterSpec for Sm2captcompxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2captcompx::R`](R) reader structure"] +impl crate::Readable for Sm2captcompxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2captcompx::W`](W) writer structure"] +impl crate::Writable for Sm2captcompxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2CAPTCOMPX to value 0"] +impl crate::Resettable for Sm2captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm2captctrlx.rs new file mode 100644 index 000000000..4e71b6d60 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2captctrlx.rs @@ -0,0 +1,493 @@ +#[doc = "Register `SM2CAPTCTRLX` reader"] +pub type R = crate::R; +#[doc = "Register `SM2CAPTCTRLX` writer"] +pub type W = crate::W; +#[doc = "Arm X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Armx { + #[doc = "0: Input capture operation is disabled."] + Disabled = 0, + #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Armx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARMX` reader - Arm X"] +pub type ArmxR = crate::BitReader; +impl ArmxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Armx { + match self.bits { + false => Armx::Disabled, + true => Armx::Enabled, + } + } + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Armx::Disabled + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Armx::Enabled + } +} +#[doc = "Field `ARMX` writer - Arm X"] +pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; +impl<'a, REG> ArmxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Armx::Disabled) + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Armx::Enabled) + } +} +#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oneshotx { + #[doc = "0: Free Running"] + FreeRunning = 0, + #[doc = "1: One Shot"] + OneShot = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oneshotx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] +pub type OneshotxR = crate::BitReader; +impl OneshotxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oneshotx { + match self.bits { + false => Oneshotx::FreeRunning, + true => Oneshotx::OneShot, + } + } + #[doc = "Free Running"] + #[inline(always)] + pub fn is_free_running(&self) -> bool { + *self == Oneshotx::FreeRunning + } + #[doc = "One Shot"] + #[inline(always)] + pub fn is_one_shot(&self) -> bool { + *self == Oneshotx::OneShot + } +} +#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] +pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; +impl<'a, REG> OneshotxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Free Running"] + #[inline(always)] + pub fn free_running(self) -> &'a mut crate::W { + self.variant(Oneshotx::FreeRunning) + } + #[doc = "One Shot"] + #[inline(always)] + pub fn one_shot(self) -> &'a mut crate::W { + self.variant(Oneshotx::OneShot) + } +} +#[doc = "Edge X 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx0 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx0 { + type Ux = u8; +} +impl crate::IsEnum for Edgx0 {} +#[doc = "Field `EDGX0` reader - Edge X 0"] +pub type Edgx0R = crate::FieldReader; +impl Edgx0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx0 { + match self.bits { + 0 => Edgx0::Disabled, + 1 => Edgx0::FallingEdge, + 2 => Edgx0::RisingEdge, + 3 => Edgx0::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx0::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx0::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx0::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx0::AnyEdge + } +} +#[doc = "Field `EDGX0` writer - Edge X 0"] +pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; +impl<'a, REG> Edgx0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx0::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::AnyEdge) + } +} +#[doc = "Edge X 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx1 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx1 { + type Ux = u8; +} +impl crate::IsEnum for Edgx1 {} +#[doc = "Field `EDGX1` reader - Edge X 1"] +pub type Edgx1R = crate::FieldReader; +impl Edgx1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx1 { + match self.bits { + 0 => Edgx1::Disabled, + 1 => Edgx1::FallingEdge, + 2 => Edgx1::RisingEdge, + 3 => Edgx1::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx1::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx1::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx1::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx1::AnyEdge + } +} +#[doc = "Field `EDGX1` writer - Edge X 1"] +pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; +impl<'a, REG> Edgx1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx1::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::AnyEdge) + } +} +#[doc = "Input Select X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum InpSelx { + #[doc = "0: Raw PWM_X input signal selected as source."] + PwmX = 0, + #[doc = "1: Edge Counter"] + EdgeCounter = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: InpSelx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INP_SELX` reader - Input Select X"] +pub type InpSelxR = crate::BitReader; +impl InpSelxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InpSelx { + match self.bits { + false => InpSelx::PwmX, + true => InpSelx::EdgeCounter, + } + } + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InpSelx::PwmX + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn is_edge_counter(&self) -> bool { + *self == InpSelx::EdgeCounter + } +} +#[doc = "Field `INP_SELX` writer - Input Select X"] +pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; +impl<'a, REG> InpSelxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InpSelx::PwmX) + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn edge_counter(self) -> &'a mut crate::W { + self.variant(InpSelx::EdgeCounter) + } +} +#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EdgcntxEn { + #[doc = "0: Edge counter disabled and held in reset"] + Disabled = 0, + #[doc = "1: Edge counter enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EdgcntxEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] +pub type EdgcntxEnR = crate::BitReader; +impl EdgcntxEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EdgcntxEn { + match self.bits { + false => EdgcntxEn::Disabled, + true => EdgcntxEn::Enabled, + } + } + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EdgcntxEn::Disabled + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EdgcntxEn::Enabled + } +} +#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] +pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; +impl<'a, REG> EdgcntxEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Disabled) + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Enabled) + } +} +#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] +pub type CfxwmR = crate::FieldReader; +#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] +pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] +pub type Cx0cntR = crate::FieldReader; +#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] +pub type Cx1cntR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&self) -> ArmxR { + ArmxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&self) -> OneshotxR { + OneshotxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&self) -> Edgx0R { + Edgx0R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&self) -> Edgx1R { + Edgx1R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&self) -> InpSelxR { + InpSelxR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&self) -> EdgcntxEnR { + EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&self) -> CfxwmR { + CfxwmR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] + #[inline(always)] + pub fn cx0cnt(&self) -> Cx0cntR { + Cx0cntR::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] + #[inline(always)] + pub fn cx1cnt(&self) -> Cx1cntR { + Cx1cntR::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&mut self) -> ArmxW { + ArmxW::new(self, 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&mut self) -> OneshotxW { + OneshotxW::new(self, 1) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&mut self) -> Edgx0W { + Edgx0W::new(self, 2) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&mut self) -> Edgx1W { + Edgx1W::new(self, 4) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&mut self) -> InpSelxW { + InpSelxW::new(self, 6) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&mut self) -> EdgcntxEnW { + EdgcntxEnW::new(self, 7) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&mut self) -> CfxwmW { + CfxwmW::new(self, 8) + } +} +#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2captctrlxSpec; +impl crate::RegisterSpec for Sm2captctrlxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2captctrlx::R`](R) reader structure"] +impl crate::Readable for Sm2captctrlxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2captctrlx::W`](W) writer structure"] +impl crate::Writable for Sm2captctrlxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2CAPTCTRLX to value 0"] +impl crate::Resettable for Sm2captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm2captfiltx.rs new file mode 100644 index 000000000..760637d43 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2captfiltx.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SM2CAPTFILTX` reader"] +pub type R = crate::R; +#[doc = "Register `SM2CAPTFILTX` writer"] +pub type W = crate::W; +#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] +pub type CaptxFiltPerR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] +pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] +pub type CaptxFiltCntR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] +pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&self) -> CaptxFiltPerR { + CaptxFiltPerR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { + CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { + CaptxFiltPerW::new(self, 0) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { + CaptxFiltCntW::new(self, 8) + } +} +#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2captfiltxSpec; +impl crate::RegisterSpec for Sm2captfiltxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2captfiltx::R`](R) reader structure"] +impl crate::Readable for Sm2captfiltxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2captfiltx::W`](W) writer structure"] +impl crate::Writable for Sm2captfiltxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2CAPTFILTX to value 0"] +impl crate::Resettable for Sm2captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cnt.rs b/mcxa276-pac/src/flexpwm0/sm2cnt.rs new file mode 100644 index 000000000..81d78d086 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2cnt.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM2CNT` reader"] +pub type R = crate::R; +#[doc = "Field `CNT` reader - Counter Register Bits"] +pub type CntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Counter Register Bits"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2cntSpec; +impl crate::RegisterSpec for Sm2cntSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2cnt::R`](R) reader structure"] +impl crate::Readable for Sm2cntSpec {} +#[doc = "`reset()` method sets SM2CNT to value 0"] +impl crate::Resettable for Sm2cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2ctrl.rs b/mcxa276-pac/src/flexpwm0/sm2ctrl.rs new file mode 100644 index 000000000..2856a9962 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2ctrl.rs @@ -0,0 +1,871 @@ +#[doc = "Register `SM2CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM2CTRL` writer"] +pub type W = crate::W; +#[doc = "Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblen { + #[doc = "0: Double switching disabled."] + Disabled = 0, + #[doc = "1: Double switching enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLEN` reader - Double Switching Enable"] +pub type DblenR = crate::BitReader; +impl DblenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblen { + match self.bits { + false => Dblen::Disabled, + true => Dblen::Enabled, + } + } + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblen::Disabled + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblen::Enabled + } +} +#[doc = "Field `DBLEN` writer - Double Switching Enable"] +pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; +impl<'a, REG> DblenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblen::Disabled) + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblen::Enabled) + } +} +#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblx { + #[doc = "0: PWM_X double pulse disabled."] + Disabled = 0, + #[doc = "1: PWM_X double pulse enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] +pub type DblxR = crate::BitReader; +impl DblxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblx { + match self.bits { + false => Dblx::Disabled, + true => Dblx::Enabled, + } + } + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblx::Disabled + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblx::Enabled + } +} +#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] +pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; +impl<'a, REG> DblxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblx::Disabled) + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblx::Enabled) + } +} +#[doc = "Load Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldmod { + #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + NextPwmReload = 0, + #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + MtctrlLdokSet = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldmod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDMOD` reader - Load Mode Select"] +pub type LdmodR = crate::BitReader; +impl LdmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldmod { + match self.bits { + false => Ldmod::NextPwmReload, + true => Ldmod::MtctrlLdokSet, + } + } + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn is_next_pwm_reload(&self) -> bool { + *self == Ldmod::NextPwmReload + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn is_mtctrl_ldok_set(&self) -> bool { + *self == Ldmod::MtctrlLdokSet + } +} +#[doc = "Field `LDMOD` writer - Load Mode Select"] +pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; +impl<'a, REG> LdmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn next_pwm_reload(self) -> &'a mut crate::W { + self.variant(Ldmod::NextPwmReload) + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { + self.variant(Ldmod::MtctrlLdokSet) + } +} +#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Split { + #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + Disabled = 0, + #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Split) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitR = crate::BitReader; +impl SplitR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Split { + match self.bits { + false => Split::Disabled, + true => Split::Enabled, + } + } + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Split::Disabled + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Split::Enabled + } +} +#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; +impl<'a, REG> SplitW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Split::Disabled) + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Split::Enabled) + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Prsc { + #[doc = "0: Prescaler 1"] + One = 0, + #[doc = "1: Prescaler 2"] + Two = 1, + #[doc = "2: Prescaler 4"] + Four = 2, + #[doc = "3: Prescaler 8"] + Eight = 3, + #[doc = "4: Prescaler 16"] + Sixteen = 4, + #[doc = "5: Prescaler 32"] + Thirtytwo = 5, + #[doc = "6: Prescaler 64"] + Sixtyfour = 6, + #[doc = "7: Prescaler 128"] + Hundredtwentyeight = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Prsc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Prsc { + type Ux = u8; +} +impl crate::IsEnum for Prsc {} +#[doc = "Field `PRSC` reader - Prescaler"] +pub type PrscR = crate::FieldReader; +impl PrscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prsc { + match self.bits { + 0 => Prsc::One, + 1 => Prsc::Two, + 2 => Prsc::Four, + 3 => Prsc::Eight, + 4 => Prsc::Sixteen, + 5 => Prsc::Thirtytwo, + 6 => Prsc::Sixtyfour, + 7 => Prsc::Hundredtwentyeight, + _ => unreachable!(), + } + } + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Prsc::One + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn is_two(&self) -> bool { + *self == Prsc::Two + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn is_four(&self) -> bool { + *self == Prsc::Four + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn is_eight(&self) -> bool { + *self == Prsc::Eight + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn is_sixteen(&self) -> bool { + *self == Prsc::Sixteen + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn is_thirtytwo(&self) -> bool { + *self == Prsc::Thirtytwo + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn is_sixtyfour(&self) -> bool { + *self == Prsc::Sixtyfour + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn is_hundredtwentyeight(&self) -> bool { + *self == Prsc::Hundredtwentyeight + } +} +#[doc = "Field `PRSC` writer - Prescaler"] +pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; +impl<'a, REG> PrscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn one(self) -> &'a mut crate::W { + self.variant(Prsc::One) + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn two(self) -> &'a mut crate::W { + self.variant(Prsc::Two) + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn four(self) -> &'a mut crate::W { + self.variant(Prsc::Four) + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn eight(self) -> &'a mut crate::W { + self.variant(Prsc::Eight) + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn sixteen(self) -> &'a mut crate::W { + self.variant(Prsc::Sixteen) + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn thirtytwo(self) -> &'a mut crate::W { + self.variant(Prsc::Thirtytwo) + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn sixtyfour(self) -> &'a mut crate::W { + self.variant(Prsc::Sixtyfour) + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn hundredtwentyeight(self) -> &'a mut crate::W { + self.variant(Prsc::Hundredtwentyeight) + } +} +#[doc = "Compare Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Compmode { + #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + EqualTo = 0, + #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + EqualToOrGreaterThan = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Compmode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPMODE` reader - Compare Mode"] +pub type CompmodeR = crate::BitReader; +impl CompmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Compmode { + match self.bits { + false => Compmode::EqualTo, + true => Compmode::EqualToOrGreaterThan, + } + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn is_equal_to(&self) -> bool { + *self == Compmode::EqualTo + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn is_equal_to_or_greater_than(&self) -> bool { + *self == Compmode::EqualToOrGreaterThan + } +} +#[doc = "Field `COMPMODE` writer - Compare Mode"] +pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; +impl<'a, REG> CompmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn equal_to(self) -> &'a mut crate::W { + self.variant(Compmode::EqualTo) + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { + self.variant(Compmode::EqualToOrGreaterThan) + } +} +#[doc = "Field `DT` reader - Deadtime"] +pub type DtR = crate::FieldReader; +#[doc = "Full Cycle Reload\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Full { + #[doc = "0: Full-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Full-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FULL` reader - Full Cycle Reload"] +pub type FullR = crate::BitReader; +impl FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Full { + match self.bits { + false => Full::Disabled, + true => Full::Enabled, + } + } + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Full::Disabled + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Full::Enabled + } +} +#[doc = "Field `FULL` writer - Full Cycle Reload"] +pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; +impl<'a, REG> FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Full::Disabled) + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Full::Enabled) + } +} +#[doc = "Half Cycle Reload\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Half { + #[doc = "0: Half-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Half-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Half) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALF` reader - Half Cycle Reload"] +pub type HalfR = crate::BitReader; +impl HalfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Half { + match self.bits { + false => Half::Disabled, + true => Half::Enabled, + } + } + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Half::Disabled + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Half::Enabled + } +} +#[doc = "Field `HALF` writer - Half Cycle Reload"] +pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; +impl<'a, REG> HalfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Half::Disabled) + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Half::Enabled) + } +} +#[doc = "Load Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ldfq { + #[doc = "0: Every PWM opportunity"] + Everypwm = 0, + #[doc = "1: Every 2 PWM opportunities"] + Every2pwm = 1, + #[doc = "2: Every 3 PWM opportunities"] + Every3pwm = 2, + #[doc = "3: Every 4 PWM opportunities"] + Every4pwm = 3, + #[doc = "4: Every 5 PWM opportunities"] + Every5pwm = 4, + #[doc = "5: Every 6 PWM opportunities"] + Every6pwm = 5, + #[doc = "6: Every 7 PWM opportunities"] + Every7pwm = 6, + #[doc = "7: Every 8 PWM opportunities"] + Every8pwm = 7, + #[doc = "8: Every 9 PWM opportunities"] + Every9pwm = 8, + #[doc = "9: Every 10 PWM opportunities"] + Every10pwm = 9, + #[doc = "10: Every 11 PWM opportunities"] + Every11pwm = 10, + #[doc = "11: Every 12 PWM opportunities"] + Every12pwm = 11, + #[doc = "12: Every 13 PWM opportunities"] + Every13pwm = 12, + #[doc = "13: Every 14 PWM opportunities"] + Every14pwm = 13, + #[doc = "14: Every 15 PWM opportunities"] + Every15pwm = 14, + #[doc = "15: Every 16 PWM opportunities"] + Every16pwm = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ldfq) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ldfq { + type Ux = u8; +} +impl crate::IsEnum for Ldfq {} +#[doc = "Field `LDFQ` reader - Load Frequency"] +pub type LdfqR = crate::FieldReader; +impl LdfqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldfq { + match self.bits { + 0 => Ldfq::Everypwm, + 1 => Ldfq::Every2pwm, + 2 => Ldfq::Every3pwm, + 3 => Ldfq::Every4pwm, + 4 => Ldfq::Every5pwm, + 5 => Ldfq::Every6pwm, + 6 => Ldfq::Every7pwm, + 7 => Ldfq::Every8pwm, + 8 => Ldfq::Every9pwm, + 9 => Ldfq::Every10pwm, + 10 => Ldfq::Every11pwm, + 11 => Ldfq::Every12pwm, + 12 => Ldfq::Every13pwm, + 13 => Ldfq::Every14pwm, + 14 => Ldfq::Every15pwm, + 15 => Ldfq::Every16pwm, + _ => unreachable!(), + } + } + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Ldfq::Everypwm + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn is_every2pwm(&self) -> bool { + *self == Ldfq::Every2pwm + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn is_every3pwm(&self) -> bool { + *self == Ldfq::Every3pwm + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn is_every4pwm(&self) -> bool { + *self == Ldfq::Every4pwm + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn is_every5pwm(&self) -> bool { + *self == Ldfq::Every5pwm + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn is_every6pwm(&self) -> bool { + *self == Ldfq::Every6pwm + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn is_every7pwm(&self) -> bool { + *self == Ldfq::Every7pwm + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn is_every8pwm(&self) -> bool { + *self == Ldfq::Every8pwm + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn is_every9pwm(&self) -> bool { + *self == Ldfq::Every9pwm + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn is_every10pwm(&self) -> bool { + *self == Ldfq::Every10pwm + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn is_every11pwm(&self) -> bool { + *self == Ldfq::Every11pwm + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn is_every12pwm(&self) -> bool { + *self == Ldfq::Every12pwm + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn is_every13pwm(&self) -> bool { + *self == Ldfq::Every13pwm + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn is_every14pwm(&self) -> bool { + *self == Ldfq::Every14pwm + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn is_every15pwm(&self) -> bool { + *self == Ldfq::Every15pwm + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn is_every16pwm(&self) -> bool { + *self == Ldfq::Every16pwm + } +} +#[doc = "Field `LDFQ` writer - Load Frequency"] +pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; +impl<'a, REG> LdfqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Everypwm) + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn every2pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every2pwm) + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn every3pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every3pwm) + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn every4pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every4pwm) + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn every5pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every5pwm) + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn every6pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every6pwm) + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn every7pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every7pwm) + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn every8pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every8pwm) + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn every9pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every9pwm) + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn every10pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every10pwm) + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn every11pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every11pwm) + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn every12pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every12pwm) + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn every13pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every13pwm) + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn every14pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every14pwm) + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn every15pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every15pwm) + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn every16pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every16pwm) + } +} +impl R { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&self) -> DblenR { + DblenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&self) -> DblxR { + DblxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&self) -> LdmodR { + LdmodR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&self) -> SplitR { + SplitR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&self) -> PrscR { + PrscR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&self) -> CompmodeR { + CompmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Deadtime"] + #[inline(always)] + pub fn dt(&self) -> DtR { + DtR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&self) -> FullR { + FullR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&self) -> HalfR { + HalfR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&self) -> LdfqR { + LdfqR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&mut self) -> DblenW { + DblenW::new(self, 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&mut self) -> DblxW { + DblxW::new(self, 1) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&mut self) -> LdmodW { + LdmodW::new(self, 2) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&mut self) -> SplitW { + SplitW::new(self, 3) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&mut self) -> PrscW { + PrscW::new(self, 4) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&mut self) -> CompmodeW { + CompmodeW::new(self, 7) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&mut self) -> FullW { + FullW::new(self, 10) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&mut self) -> HalfW { + HalfW::new(self, 11) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&mut self) -> LdfqW { + LdfqW::new(self, 12) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2ctrlSpec; +impl crate::RegisterSpec for Sm2ctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2ctrl::R`](R) reader structure"] +impl crate::Readable for Sm2ctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2ctrl::W`](W) writer structure"] +impl crate::Writable for Sm2ctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2CTRL to value 0x0400"] +impl crate::Resettable for Sm2ctrlSpec { + const RESET_VALUE: u16 = 0x0400; +} diff --git a/mcxa276-pac/src/flexpwm0/sm2ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm2ctrl2.rs new file mode 100644 index 000000000..2b115e937 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2ctrl2.rs @@ -0,0 +1,607 @@ +#[doc = "Register `SM2CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM2CTRL2` writer"] +pub type W = crate::W; +#[doc = "Clock Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ClkSel { + #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] + Ipbus = 0, + #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] + ExtClk = 1, + #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + AuxClk = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ClkSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ClkSel { + type Ux = u8; +} +impl crate::IsEnum for ClkSel {} +#[doc = "Field `CLK_SEL` reader - Clock Source Select"] +pub type ClkSelR = crate::FieldReader; +impl ClkSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ClkSel::Ipbus), + 1 => Some(ClkSel::ExtClk), + 2 => Some(ClkSel::AuxClk), + _ => None, + } + } + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ipbus(&self) -> bool { + *self == ClkSel::Ipbus + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ext_clk(&self) -> bool { + *self == ClkSel::ExtClk + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn is_aux_clk(&self) -> bool { + *self == ClkSel::AuxClk + } +} +#[doc = "Field `CLK_SEL` writer - Clock Source Select"] +pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; +impl<'a, REG> ClkSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ipbus(self) -> &'a mut crate::W { + self.variant(ClkSel::Ipbus) + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ext_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::ExtClk) + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn aux_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::AuxClk) + } +} +#[doc = "Reload Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ReloadSel { + #[doc = "0: The local RELOAD signal is used to reload registers."] + Local = 0, + #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + Master = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ReloadSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] +pub type ReloadSelR = crate::BitReader; +impl ReloadSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ReloadSel { + match self.bits { + false => ReloadSel::Local, + true => ReloadSel::Master, + } + } + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ReloadSel::Local + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ReloadSel::Master + } +} +#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] +pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; +impl<'a, REG> ReloadSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ReloadSel::Local) + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ReloadSel::Master) + } +} +#[doc = "Force Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ForceSel { + #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + Local = 0, + #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + Master = 1, + #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + LocalReload = 2, + #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterReload = 3, + #[doc = "4: The local sync signal from this submodule is used to force updates."] + LocalSync = 4, + #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterSync = 5, + #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + ExtForce = 6, + #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + ExtSync = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ForceSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ForceSel { + type Ux = u8; +} +impl crate::IsEnum for ForceSel {} +#[doc = "Field `FORCE_SEL` reader - Force Select"] +pub type ForceSelR = crate::FieldReader; +impl ForceSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ForceSel { + match self.bits { + 0 => ForceSel::Local, + 1 => ForceSel::Master, + 2 => ForceSel::LocalReload, + 3 => ForceSel::MasterReload, + 4 => ForceSel::LocalSync, + 5 => ForceSel::MasterSync, + 6 => ForceSel::ExtForce, + 7 => ForceSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ForceSel::Local + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ForceSel::Master + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == ForceSel::LocalReload + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == ForceSel::MasterReload + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == ForceSel::LocalSync + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == ForceSel::MasterSync + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_force(&self) -> bool { + *self == ForceSel::ExtForce + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == ForceSel::ExtSync + } +} +#[doc = "Field `FORCE_SEL` writer - Force Select"] +pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; +impl<'a, REG> ForceSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ForceSel::Local) + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ForceSel::Master) + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalReload) + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterReload) + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalSync) + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterSync) + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_force(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtForce) + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtSync) + } +} +#[doc = "Field `FORCE` reader - Force Initialization"] +pub type ForceR = crate::BitReader; +#[doc = "Field `FORCE` writer - Force Initialization"] +pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Force Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frcen { + #[doc = "0: Initialization from a FORCE_OUT is disabled."] + Disabled = 0, + #[doc = "1: Initialization from a FORCE_OUT is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRCEN` reader - Force Enable"] +pub type FrcenR = crate::BitReader; +impl FrcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frcen { + match self.bits { + false => Frcen::Disabled, + true => Frcen::Enabled, + } + } + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Frcen::Disabled + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Frcen::Enabled + } +} +#[doc = "Field `FRCEN` writer - Force Enable"] +pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; +impl<'a, REG> FrcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Frcen::Disabled) + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Frcen::Enabled) + } +} +#[doc = "Initialization Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum InitSel { + #[doc = "0: Local sync (PWM_X) causes initialization."] + PwmX = 0, + #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + MasterReload = 1, + #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + MasterSync = 2, + #[doc = "3: EXT_SYNC causes initialization."] + ExtSync = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: InitSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for InitSel { + type Ux = u8; +} +impl crate::IsEnum for InitSel {} +#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] +pub type InitSelR = crate::FieldReader; +impl InitSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InitSel { + match self.bits { + 0 => InitSel::PwmX, + 1 => InitSel::MasterReload, + 2 => InitSel::MasterSync, + 3 => InitSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InitSel::PwmX + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == InitSel::MasterReload + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == InitSel::MasterSync + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == InitSel::ExtSync + } +} +#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] +pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; +impl<'a, REG> InitSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InitSel::PwmX) + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(InitSel::MasterReload) + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(InitSel::MasterSync) + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(InitSel::ExtSync) + } +} +#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] +pub type PwmxInitR = crate::BitReader; +#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] +pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] +pub type Pwm45InitR = crate::BitReader; +#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] +pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] +pub type Pwm23InitR = crate::BitReader; +#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] +pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Indep { + #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] + Complementary = 0, + #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] + Independent = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Indep) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] +pub type IndepR = crate::BitReader; +impl IndepR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Indep { + match self.bits { + false => Indep::Complementary, + true => Indep::Independent, + } + } + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn is_complementary(&self) -> bool { + *self == Indep::Complementary + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn is_independent(&self) -> bool { + *self == Indep::Independent + } +} +#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] +pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; +impl<'a, REG> IndepW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn complementary(self) -> &'a mut crate::W { + self.variant(Indep::Complementary) + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn independent(self) -> &'a mut crate::W { + self.variant(Indep::Independent) + } +} +#[doc = "Field `DBGEN` reader - Debug Enable"] +pub type DbgenR = crate::BitReader; +#[doc = "Field `DBGEN` writer - Debug Enable"] +pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&self) -> ClkSelR { + ClkSelR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&self) -> ReloadSelR { + ReloadSelR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&self) -> ForceSelR { + ForceSelR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&self) -> ForceR { + ForceR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&self) -> FrcenR { + FrcenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&self) -> InitSelR { + InitSelR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&self) -> PwmxInitR { + PwmxInitR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&self) -> Pwm45InitR { + Pwm45InitR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&self) -> Pwm23InitR { + Pwm23InitR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&self) -> IndepR { + IndepR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&self) -> DbgenR { + DbgenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&mut self) -> ClkSelW { + ClkSelW::new(self, 0) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&mut self) -> ReloadSelW { + ReloadSelW::new(self, 2) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&mut self) -> ForceSelW { + ForceSelW::new(self, 3) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&mut self) -> ForceW { + ForceW::new(self, 6) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&mut self) -> FrcenW { + FrcenW::new(self, 7) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&mut self) -> InitSelW { + InitSelW::new(self, 8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&mut self) -> PwmxInitW { + PwmxInitW::new(self, 10) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&mut self) -> Pwm45InitW { + Pwm45InitW::new(self, 11) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&mut self) -> Pwm23InitW { + Pwm23InitW::new(self, 12) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&mut self) -> IndepW { + IndepW::new(self, 13) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&mut self) -> DbgenW { + DbgenW::new(self, 15) + } +} +#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2ctrl2Spec; +impl crate::RegisterSpec for Sm2ctrl2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2ctrl2::R`](R) reader structure"] +impl crate::Readable for Sm2ctrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2ctrl2::W`](W) writer structure"] +impl crate::Writable for Sm2ctrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2CTRL2 to value 0"] +impl crate::Resettable for Sm2ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval0.rs b/mcxa276-pac/src/flexpwm0/sm2cval0.rs new file mode 100644 index 000000000..228743cfd --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2cval0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM2CVAL0` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] +pub type Captval0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 0"] + #[inline(always)] + pub fn captval0(&self) -> Captval0R { + Captval0R::new(self.bits) + } +} +#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2cval0Spec; +impl crate::RegisterSpec for Sm2cval0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2cval0::R`](R) reader structure"] +impl crate::Readable for Sm2cval0Spec {} +#[doc = "`reset()` method sets SM2CVAL0 to value 0"] +impl crate::Resettable for Sm2cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs new file mode 100644 index 000000000..1146b3fa2 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM2CVAL0CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] +pub type Cval0cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 0 Cycle"] + #[inline(always)] + pub fn cval0cyc(&self) -> Cval0cycR { + Cval0cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2cval0cycSpec; +impl crate::RegisterSpec for Sm2cval0cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2cval0cyc::R`](R) reader structure"] +impl crate::Readable for Sm2cval0cycSpec {} +#[doc = "`reset()` method sets SM2CVAL0CYC to value 0"] +impl crate::Resettable for Sm2cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval1.rs b/mcxa276-pac/src/flexpwm0/sm2cval1.rs new file mode 100644 index 000000000..9f667cdb7 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2cval1.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM2CVAL1` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] +pub type Captval1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 1"] + #[inline(always)] + pub fn captval1(&self) -> Captval1R { + Captval1R::new(self.bits) + } +} +#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2cval1Spec; +impl crate::RegisterSpec for Sm2cval1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2cval1::R`](R) reader structure"] +impl crate::Readable for Sm2cval1Spec {} +#[doc = "`reset()` method sets SM2CVAL1 to value 0"] +impl crate::Resettable for Sm2cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs new file mode 100644 index 000000000..d62b3e407 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM2CVAL1CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] +pub type Cval1cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 1 Cycle"] + #[inline(always)] + pub fn cval1cyc(&self) -> Cval1cycR { + Cval1cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2cval1cycSpec; +impl crate::RegisterSpec for Sm2cval1cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2cval1cyc::R`](R) reader structure"] +impl crate::Readable for Sm2cval1cycSpec {} +#[doc = "`reset()` method sets SM2CVAL1CYC to value 0"] +impl crate::Resettable for Sm2cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2dismap0.rs b/mcxa276-pac/src/flexpwm0/sm2dismap0.rs new file mode 100644 index 000000000..aa571c2d7 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2dismap0.rs @@ -0,0 +1,65 @@ +#[doc = "Register `SM2DISMAP0` reader"] +pub type R = crate::R; +#[doc = "Register `SM2DISMAP0` writer"] +pub type W = crate::W; +#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] +pub type Dis0aR = crate::FieldReader; +#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] +pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] +pub type Dis0bR = crate::FieldReader; +#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] +pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] +pub type Dis0xR = crate::FieldReader; +#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] +pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&self) -> Dis0aR { + Dis0aR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&self) -> Dis0bR { + Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&self) -> Dis0xR { + Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&mut self) -> Dis0aW { + Dis0aW::new(self, 0) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&mut self) -> Dis0bW { + Dis0bW::new(self, 4) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&mut self) -> Dis0xW { + Dis0xW::new(self, 8) + } +} +#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2dismap0Spec; +impl crate::RegisterSpec for Sm2dismap0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2dismap0::R`](R) reader structure"] +impl crate::Readable for Sm2dismap0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2dismap0::W`](W) writer structure"] +impl crate::Writable for Sm2dismap0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2DISMAP0 to value 0xffff"] +impl crate::Resettable for Sm2dismap0Spec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm2dmaen.rs b/mcxa276-pac/src/flexpwm0/sm2dmaen.rs new file mode 100644 index 000000000..750bf3156 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2dmaen.rs @@ -0,0 +1,271 @@ +#[doc = "Register `SM2DMAEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM2DMAEN` writer"] +pub type W = crate::W; +#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] +pub type Cx0deR = crate::BitReader; +#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] +pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] +pub type Cx1deR = crate::BitReader; +#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] +pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Captde { + #[doc = "0: Read DMA requests disabled."] + Disabled = 0, + #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + Exceedfifo = 1, + #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] + LocalSync = 2, + #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] + LocalReload = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Captde) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Captde { + type Ux = u8; +} +impl crate::IsEnum for Captde {} +#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] +pub type CaptdeR = crate::FieldReader; +impl CaptdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Captde { + match self.bits { + 0 => Captde::Disabled, + 1 => Captde::Exceedfifo, + 2 => Captde::LocalSync, + 3 => Captde::LocalReload, + _ => unreachable!(), + } + } + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Captde::Disabled + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn is_exceedfifo(&self) -> bool { + *self == Captde::Exceedfifo + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == Captde::LocalSync + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == Captde::LocalReload + } +} +#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] +pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; +impl<'a, REG> CaptdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Captde::Disabled) + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn exceedfifo(self) -> &'a mut crate::W { + self.variant(Captde::Exceedfifo) + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(Captde::LocalSync) + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(Captde::LocalReload) + } +} +#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fand { + #[doc = "0: Selected FIFO watermarks are OR'ed together."] + Or = 0, + #[doc = "1: Selected FIFO watermarks are AND'ed together."] + And = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fand) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] +pub type FandR = crate::BitReader; +impl FandR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fand { + match self.bits { + false => Fand::Or, + true => Fand::And, + } + } + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn is_or(&self) -> bool { + *self == Fand::Or + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn is_and(&self) -> bool { + *self == Fand::And + } +} +#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] +pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; +impl<'a, REG> FandW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn or(self) -> &'a mut crate::W { + self.variant(Fand::Or) + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn and(self) -> &'a mut crate::W { + self.variant(Fand::And) + } +} +#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Valde { + #[doc = "0: DMA write requests disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Valde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] +pub type ValdeR = crate::BitReader; +impl ValdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Valde { + match self.bits { + false => Valde::Disabled, + true => Valde::Enabled, + } + } + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Valde::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Valde::Enabled + } +} +#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] +pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; +impl<'a, REG> ValdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Valde::Disabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Valde::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&self) -> Cx0deR { + Cx0deR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&self) -> Cx1deR { + Cx1deR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&self) -> CaptdeR { + CaptdeR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&self) -> FandR { + FandR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&self) -> ValdeR { + ValdeR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&mut self) -> Cx0deW { + Cx0deW::new(self, 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&mut self) -> Cx1deW { + Cx1deW::new(self, 1) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&mut self) -> CaptdeW { + CaptdeW::new(self, 6) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&mut self) -> FandW { + FandW::new(self, 8) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&mut self) -> ValdeW { + ValdeW::new(self, 9) + } +} +#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2dmaenSpec; +impl crate::RegisterSpec for Sm2dmaenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2dmaen::R`](R) reader structure"] +impl crate::Readable for Sm2dmaenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2dmaen::W`](W) writer structure"] +impl crate::Writable for Sm2dmaenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2DMAEN to value 0"] +impl crate::Resettable for Sm2dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs new file mode 100644 index 000000000..b35817d79 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM2DTCNT0` reader"] +pub type R = crate::R; +#[doc = "Register `SM2DTCNT0` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] +pub type Dtcnt0R = crate::FieldReader; +#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] +pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&self) -> Dtcnt0R { + Dtcnt0R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&mut self) -> Dtcnt0W { + Dtcnt0W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2dtcnt0Spec; +impl crate::RegisterSpec for Sm2dtcnt0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2dtcnt0::R`](R) reader structure"] +impl crate::Readable for Sm2dtcnt0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2dtcnt0::W`](W) writer structure"] +impl crate::Writable for Sm2dtcnt0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2DTCNT0 to value 0x07ff"] +impl crate::Resettable for Sm2dtcnt0Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs new file mode 100644 index 000000000..ae1998374 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM2DTCNT1` reader"] +pub type R = crate::R; +#[doc = "Register `SM2DTCNT1` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] +pub type Dtcnt1R = crate::FieldReader; +#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] +pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&self) -> Dtcnt1R { + Dtcnt1R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&mut self) -> Dtcnt1W { + Dtcnt1W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2dtcnt1Spec; +impl crate::RegisterSpec for Sm2dtcnt1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2dtcnt1::R`](R) reader structure"] +impl crate::Readable for Sm2dtcnt1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2dtcnt1::W`](W) writer structure"] +impl crate::Writable for Sm2dtcnt1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2DTCNT1 to value 0x07ff"] +impl crate::Resettable for Sm2dtcnt1Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm2init.rs b/mcxa276-pac/src/flexpwm0/sm2init.rs new file mode 100644 index 000000000..40972e549 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2init.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2INIT` reader"] +pub type R = crate::R; +#[doc = "Register `SM2INIT` writer"] +pub type W = crate::W; +#[doc = "Field `INIT` reader - Initial Count Register Bits"] +pub type InitR = crate::FieldReader; +#[doc = "Field `INIT` writer - Initial Count Register Bits"] +pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&self) -> InitR { + InitR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&mut self) -> InitW { + InitW::new(self, 0) + } +} +#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2initSpec; +impl crate::RegisterSpec for Sm2initSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2init::R`](R) reader structure"] +impl crate::Readable for Sm2initSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2init::W`](W) writer structure"] +impl crate::Writable for Sm2initSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2INIT to value 0"] +impl crate::Resettable for Sm2initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2inten.rs b/mcxa276-pac/src/flexpwm0/sm2inten.rs new file mode 100644 index 000000000..8fb99fdd7 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2inten.rs @@ -0,0 +1,343 @@ +#[doc = "Register `SM2INTEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM2INTEN` writer"] +pub type W = crate::W; +#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpie { + #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + Disabled = 0, + #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + Enabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpie) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpie { + type Ux = u8; +} +impl crate::IsEnum for Cmpie {} +#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] +pub type CmpieR = crate::FieldReader; +impl CmpieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpie::Disabled), + 1 => Some(Cmpie::Enabled), + _ => None, + } + } + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmpie::Disabled + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmpie::Enabled + } +} +#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] +pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; +impl<'a, REG> CmpieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Disabled) + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Enabled) + } +} +#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx0ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx0ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] +pub type Cx0ieR = crate::BitReader; +impl Cx0ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx0ie { + match self.bits { + false => Cx0ie::Disabled, + true => Cx0ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx0ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx0ie::Enabled + } +} +#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] +pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; +impl<'a, REG> Cx0ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Enabled) + } +} +#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx1ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx1ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] +pub type Cx1ieR = crate::BitReader; +impl Cx1ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx1ie { + match self.bits { + false => Cx1ie::Disabled, + true => Cx1ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx1ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx1ie::Enabled + } +} +#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] +pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; +impl<'a, REG> Cx1ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Enabled) + } +} +#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rie { + #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RIE` reader - Reload Interrupt Enable"] +pub type RieR = crate::BitReader; +impl RieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rie { + match self.bits { + false => Rie::Disabled, + true => Rie::Enabled, + } + } + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rie::Disabled + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rie::Enabled + } +} +#[doc = "Field `RIE` writer - Reload Interrupt Enable"] +pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; +impl<'a, REG> RieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rie::Disabled) + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rie::Enabled) + } +} +#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reie { + #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] +pub type ReieR = crate::BitReader; +impl ReieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reie { + match self.bits { + false => Reie::Disabled, + true => Reie::Enabled, + } + } + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Reie::Disabled + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Reie::Enabled + } +} +#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] +pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; +impl<'a, REG> ReieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Reie::Disabled) + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Reie::Enabled) + } +} +impl R { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&self) -> CmpieR { + CmpieR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&self) -> Cx0ieR { + Cx0ieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&self) -> Cx1ieR { + Cx1ieR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RieR { + RieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&self) -> ReieR { + ReieR::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&mut self) -> CmpieW { + CmpieW::new(self, 0) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&mut self) -> Cx0ieW { + Cx0ieW::new(self, 6) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&mut self) -> Cx1ieW { + Cx1ieW::new(self, 7) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&mut self) -> RieW { + RieW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&mut self) -> ReieW { + ReieW::new(self, 13) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2intenSpec; +impl crate::RegisterSpec for Sm2intenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2inten::R`](R) reader structure"] +impl crate::Readable for Sm2intenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2inten::W`](W) writer structure"] +impl crate::Writable for Sm2intenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2INTEN to value 0"] +impl crate::Resettable for Sm2intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2octrl.rs b/mcxa276-pac/src/flexpwm0/sm2octrl.rs new file mode 100644 index 000000000..45f411730 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2octrl.rs @@ -0,0 +1,519 @@ +#[doc = "Register `SM2OCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM2OCTRL` writer"] +pub type W = crate::W; +#[doc = "PWM_X Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmxfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmxfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmxfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmxfs {} +#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] +pub type PwmxfsR = crate::FieldReader; +impl PwmxfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmxfs { + match self.bits { + 0 => Pwmxfs::Logic0, + 1 => Pwmxfs::Logic1, + 2 => Pwmxfs::Tristated2, + 3 => Pwmxfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmxfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmxfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmxfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmxfs::Tristated3 + } +} +#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] +pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; +impl<'a, REG> PwmxfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated3) + } +} +#[doc = "PWM_B Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmbfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmbfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmbfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmbfs {} +#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] +pub type PwmbfsR = crate::FieldReader; +impl PwmbfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmbfs { + match self.bits { + 0 => Pwmbfs::Logic0, + 1 => Pwmbfs::Logic1, + 2 => Pwmbfs::Tristated2, + 3 => Pwmbfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmbfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmbfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmbfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmbfs::Tristated3 + } +} +#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] +pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; +impl<'a, REG> PwmbfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated3) + } +} +#[doc = "PWM_A Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmafs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmafs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmafs { + type Ux = u8; +} +impl crate::IsEnum for Pwmafs {} +#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] +pub type PwmafsR = crate::FieldReader; +impl PwmafsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmafs { + match self.bits { + 0 => Pwmafs::Logic0, + 1 => Pwmafs::Logic1, + 2 => Pwmafs::Tristated2, + 3 => Pwmafs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmafs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmafs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmafs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmafs::Tristated3 + } +} +#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] +pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; +impl<'a, REG> PwmafsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated3) + } +} +#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polx { + #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLX` reader - PWM_X Output Polarity"] +pub type PolxR = crate::BitReader; +impl PolxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polx { + match self.bits { + false => Polx::NotInverted, + true => Polx::Inverted, + } + } + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polx::NotInverted + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polx::Inverted + } +} +#[doc = "Field `POLX` writer - PWM_X Output Polarity"] +pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; +impl<'a, REG> PolxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polx::NotInverted) + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polx::Inverted) + } +} +#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polb { + #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLB` reader - PWM_B Output Polarity"] +pub type PolbR = crate::BitReader; +impl PolbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polb { + match self.bits { + false => Polb::NotInverted, + true => Polb::Inverted, + } + } + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polb::NotInverted + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polb::Inverted + } +} +#[doc = "Field `POLB` writer - PWM_B Output Polarity"] +pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; +impl<'a, REG> PolbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polb::NotInverted) + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polb::Inverted) + } +} +#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pola { + #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pola) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLA` reader - PWM_A Output Polarity"] +pub type PolaR = crate::BitReader; +impl PolaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pola { + match self.bits { + false => Pola::NotInverted, + true => Pola::Inverted, + } + } + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Pola::NotInverted + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Pola::Inverted + } +} +#[doc = "Field `POLA` writer - PWM_A Output Polarity"] +pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; +impl<'a, REG> PolaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Pola::NotInverted) + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Pola::Inverted) + } +} +#[doc = "Field `PWMX_IN` reader - PWM_X Input"] +pub type PwmxInR = crate::BitReader; +#[doc = "Field `PWMB_IN` reader - PWM_B Input"] +pub type PwmbInR = crate::BitReader; +#[doc = "Field `PWMA_IN` reader - PWM_A Input"] +pub type PwmaInR = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&self) -> PwmxfsR { + PwmxfsR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&self) -> PwmbfsR { + PwmbfsR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&self) -> PwmafsR { + PwmafsR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&self) -> PolxR { + PolxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&self) -> PolbR { + PolbR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&self) -> PolaR { + PolaR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - PWM_X Input"] + #[inline(always)] + pub fn pwmx_in(&self) -> PwmxInR { + PwmxInR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PWM_B Input"] + #[inline(always)] + pub fn pwmb_in(&self) -> PwmbInR { + PwmbInR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - PWM_A Input"] + #[inline(always)] + pub fn pwma_in(&self) -> PwmaInR { + PwmaInR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&mut self) -> PwmxfsW { + PwmxfsW::new(self, 0) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&mut self) -> PwmbfsW { + PwmbfsW::new(self, 2) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&mut self) -> PwmafsW { + PwmafsW::new(self, 4) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&mut self) -> PolxW { + PolxW::new(self, 8) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&mut self) -> PolbW { + PolbW::new(self, 9) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&mut self) -> PolaW { + PolaW::new(self, 10) + } +} +#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2octrlSpec; +impl crate::RegisterSpec for Sm2octrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2octrl::R`](R) reader structure"] +impl crate::Readable for Sm2octrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2octrl::W`](W) writer structure"] +impl crate::Writable for Sm2octrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2OCTRL to value 0"] +impl crate::Resettable for Sm2octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2phasedly.rs b/mcxa276-pac/src/flexpwm0/sm2phasedly.rs new file mode 100644 index 000000000..429a1f3ce --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2phasedly.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2PHASEDLY` reader"] +pub type R = crate::R; +#[doc = "Register `SM2PHASEDLY` writer"] +pub type W = crate::W; +#[doc = "Field `PHASEDLY` reader - Initial Count Register Bits"] +pub type PhasedlyR = crate::FieldReader; +#[doc = "Field `PHASEDLY` writer - Initial Count Register Bits"] +pub type PhasedlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn phasedly(&self) -> PhasedlyR { + PhasedlyR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn phasedly(&mut self) -> PhasedlyW { + PhasedlyW::new(self, 0) + } +} +#[doc = "Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2phasedly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2phasedly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2phasedlySpec; +impl crate::RegisterSpec for Sm2phasedlySpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2phasedly::R`](R) reader structure"] +impl crate::Readable for Sm2phasedlySpec {} +#[doc = "`write(|w| ..)` method takes [`sm2phasedly::W`](W) writer structure"] +impl crate::Writable for Sm2phasedlySpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2PHASEDLY to value 0"] +impl crate::Resettable for Sm2phasedlySpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2sts.rs b/mcxa276-pac/src/flexpwm0/sm2sts.rs new file mode 100644 index 000000000..8700f66e1 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2sts.rs @@ -0,0 +1,287 @@ +#[doc = "Register `SM2STS` reader"] +pub type R = crate::R; +#[doc = "Register `SM2STS` writer"] +pub type W = crate::W; +#[doc = "Compare Flags\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpf { + #[doc = "0: No compare event has occurred for a particular VALx value."] + NoEvent = 0, + #[doc = "1: A compare event has occurred for a particular VALx value."] + Event = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpf { + type Ux = u8; +} +impl crate::IsEnum for Cmpf {} +#[doc = "Field `CMPF` reader - Compare Flags"] +pub type CmpfR = crate::FieldReader; +impl CmpfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpf::NoEvent), + 1 => Some(Cmpf::Event), + _ => None, + } + } + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_no_event(&self) -> bool { + *self == Cmpf::NoEvent + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == Cmpf::Event + } +} +#[doc = "Field `CMPF` writer - Compare Flags"] +pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; +impl<'a, REG> CmpfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn no_event(self) -> &'a mut crate::W { + self.variant(Cmpf::NoEvent) + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn event(self) -> &'a mut crate::W { + self.variant(Cmpf::Event) + } +} +#[doc = "Field `CFX0` reader - Capture Flag X0"] +pub type Cfx0R = crate::BitReader; +#[doc = "Field `CFX0` writer - Capture Flag X0"] +pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CFX1` reader - Capture Flag X1"] +pub type Cfx1R = crate::BitReader; +#[doc = "Field `CFX1` writer - Capture Flag X1"] +pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Reload Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rf { + #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] + NoFlag = 0, + #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RF` reader - Reload Flag"] +pub type RfR = crate::BitReader; +impl RfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rf { + match self.bits { + false => Rf::NoFlag, + true => Rf::Flag, + } + } + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Rf::NoFlag + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Rf::Flag + } +} +#[doc = "Field `RF` writer - Reload Flag"] +pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; +impl<'a, REG> RfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Rf::NoFlag) + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Rf::Flag) + } +} +#[doc = "Reload Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ref { + #[doc = "0: No reload error occurred."] + NoFlag = 0, + #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ref) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REF` reader - Reload Error Flag"] +pub type RefR = crate::BitReader; +impl RefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ref { + match self.bits { + false => Ref::NoFlag, + true => Ref::Flag, + } + } + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ref::NoFlag + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ref::Flag + } +} +#[doc = "Field `REF` writer - Reload Error Flag"] +pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; +impl<'a, REG> RefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Ref::NoFlag) + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Ref::Flag) + } +} +#[doc = "Registers Updated Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ruf { + #[doc = "0: No register update has occurred since last reload."] + NoFlag = 0, + #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ruf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RUF` reader - Registers Updated Flag"] +pub type RufR = crate::BitReader; +impl RufR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ruf { + match self.bits { + false => Ruf::NoFlag, + true => Ruf::Flag, + } + } + #[doc = "No register update has occurred since last reload."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ruf::NoFlag + } + #[doc = "At least one of the double buffered registers has been updated since the last reload."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ruf::Flag + } +} +impl R { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&self) -> CmpfR { + CmpfR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&self) -> Cfx0R { + Cfx0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&self) -> Cfx1R { + Cfx1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&self) -> RfR { + RfR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&self) -> RefR { + RefR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Registers Updated Flag"] + #[inline(always)] + pub fn ruf(&self) -> RufR { + RufR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&mut self) -> CmpfW { + CmpfW::new(self, 0) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&mut self) -> Cfx0W { + Cfx0W::new(self, 6) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&mut self) -> Cfx1W { + Cfx1W::new(self, 7) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&mut self) -> RfW { + RfW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&mut self) -> RefW { + RefW::new(self, 13) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2stsSpec; +impl crate::RegisterSpec for Sm2stsSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2sts::R`](R) reader structure"] +impl crate::Readable for Sm2stsSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2sts::W`](W) writer structure"] +impl crate::Writable for Sm2stsSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; +} +#[doc = "`reset()` method sets SM2STS to value 0"] +impl crate::Resettable for Sm2stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2tctrl.rs b/mcxa276-pac/src/flexpwm0/sm2tctrl.rs new file mode 100644 index 000000000..4ebb12b79 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2tctrl.rs @@ -0,0 +1,267 @@ +#[doc = "Register `SM2TCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM2TCTRL` writer"] +pub type W = crate::W; +#[doc = "Output Trigger Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OutTrigEn { + #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + Val0 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OutTrigEn) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OutTrigEn { + type Ux = u8; +} +impl crate::IsEnum for OutTrigEn {} +#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] +pub type OutTrigEnR = crate::FieldReader; +impl OutTrigEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(OutTrigEn::Val0), + _ => None, + } + } + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == OutTrigEn::Val0 + } +} +#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] +pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; +impl<'a, REG> OutTrigEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn val0(self) -> &'a mut crate::W { + self.variant(OutTrigEn::Val0) + } +} +#[doc = "Trigger Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trgfrq { + #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Everypwm = 0, + #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Finalpwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trgfrq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] +pub type TrgfrqR = crate::BitReader; +impl TrgfrqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgfrq { + match self.bits { + false => Trgfrq::Everypwm, + true => Trgfrq::Finalpwm, + } + } + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Trgfrq::Everypwm + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_finalpwm(&self) -> bool { + *self == Trgfrq::Finalpwm + } +} +#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] +pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; +impl<'a, REG> TrgfrqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Everypwm) + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn finalpwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Finalpwm) + } +} +#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwbot1 { + #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + PwmOutTrig1Signal = 0, + #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] + PwmbOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwbot1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] +pub type Pwbot1R = crate::BitReader; +impl Pwbot1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwbot1 { + match self.bits { + false => Pwbot1::PwmOutTrig1Signal, + true => Pwbot1::PwmbOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwm_out_trig1_signal(&self) -> bool { + *self == Pwbot1::PwmOutTrig1Signal + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwmb_output(&self) -> bool { + *self == Pwbot1::PwmbOutput + } +} +#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] +pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; +impl<'a, REG> Pwbot1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmOutTrig1Signal) + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwmb_output(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmbOutput) + } +} +#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwaot0 { + #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + PwmOutTrig0Signal = 0, + #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] + PwmaOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwaot0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] +pub type Pwaot0R = crate::BitReader; +impl Pwaot0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwaot0 { + match self.bits { + false => Pwaot0::PwmOutTrig0Signal, + true => Pwaot0::PwmaOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwm_out_trig0_signal(&self) -> bool { + *self == Pwaot0::PwmOutTrig0Signal + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwma_output(&self) -> bool { + *self == Pwaot0::PwmaOutput + } +} +#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] +pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; +impl<'a, REG> Pwaot0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmOutTrig0Signal) + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwma_output(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmaOutput) + } +} +impl R { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&self) -> OutTrigEnR { + OutTrigEnR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&self) -> TrgfrqR { + TrgfrqR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&self) -> Pwbot1R { + Pwbot1R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&self) -> Pwaot0R { + Pwaot0R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&mut self) -> OutTrigEnW { + OutTrigEnW::new(self, 0) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&mut self) -> TrgfrqW { + TrgfrqW::new(self, 12) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&mut self) -> Pwbot1W { + Pwbot1W::new(self, 14) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&mut self) -> Pwaot0W { + Pwaot0W::new(self, 15) + } +} +#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2tctrlSpec; +impl crate::RegisterSpec for Sm2tctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2tctrl::R`](R) reader structure"] +impl crate::Readable for Sm2tctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm2tctrl::W`](W) writer structure"] +impl crate::Writable for Sm2tctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2TCTRL to value 0"] +impl crate::Resettable for Sm2tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val0.rs b/mcxa276-pac/src/flexpwm0/sm2val0.rs new file mode 100644 index 000000000..c9e859833 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2val0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2VAL0` reader"] +pub type R = crate::R; +#[doc = "Register `SM2VAL0` writer"] +pub type W = crate::W; +#[doc = "Field `VAL0` reader - Value 0"] +pub type Val0R = crate::FieldReader; +#[doc = "Field `VAL0` writer - Value 0"] +pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&self) -> Val0R { + Val0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&mut self) -> Val0W { + Val0W::new(self, 0) + } +} +#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2val0Spec; +impl crate::RegisterSpec for Sm2val0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2val0::R`](R) reader structure"] +impl crate::Readable for Sm2val0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2val0::W`](W) writer structure"] +impl crate::Writable for Sm2val0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2VAL0 to value 0"] +impl crate::Resettable for Sm2val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val1.rs b/mcxa276-pac/src/flexpwm0/sm2val1.rs new file mode 100644 index 000000000..9f1031bdd --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2val1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2VAL1` reader"] +pub type R = crate::R; +#[doc = "Register `SM2VAL1` writer"] +pub type W = crate::W; +#[doc = "Field `VAL1` reader - Value 1"] +pub type Val1R = crate::FieldReader; +#[doc = "Field `VAL1` writer - Value 1"] +pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&self) -> Val1R { + Val1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&mut self) -> Val1W { + Val1W::new(self, 0) + } +} +#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2val1Spec; +impl crate::RegisterSpec for Sm2val1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2val1::R`](R) reader structure"] +impl crate::Readable for Sm2val1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2val1::W`](W) writer structure"] +impl crate::Writable for Sm2val1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2VAL1 to value 0"] +impl crate::Resettable for Sm2val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val2.rs b/mcxa276-pac/src/flexpwm0/sm2val2.rs new file mode 100644 index 000000000..1620ddd68 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2val2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2VAL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM2VAL2` writer"] +pub type W = crate::W; +#[doc = "Field `VAL2` reader - Value 2"] +pub type Val2R = crate::FieldReader; +#[doc = "Field `VAL2` writer - Value 2"] +pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&self) -> Val2R { + Val2R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&mut self) -> Val2W { + Val2W::new(self, 0) + } +} +#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2val2Spec; +impl crate::RegisterSpec for Sm2val2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2val2::R`](R) reader structure"] +impl crate::Readable for Sm2val2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2val2::W`](W) writer structure"] +impl crate::Writable for Sm2val2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2VAL2 to value 0"] +impl crate::Resettable for Sm2val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val3.rs b/mcxa276-pac/src/flexpwm0/sm2val3.rs new file mode 100644 index 000000000..4d0f2072d --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2val3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2VAL3` reader"] +pub type R = crate::R; +#[doc = "Register `SM2VAL3` writer"] +pub type W = crate::W; +#[doc = "Field `VAL3` reader - Value 3"] +pub type Val3R = crate::FieldReader; +#[doc = "Field `VAL3` writer - Value 3"] +pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&self) -> Val3R { + Val3R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&mut self) -> Val3W { + Val3W::new(self, 0) + } +} +#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2val3Spec; +impl crate::RegisterSpec for Sm2val3Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2val3::R`](R) reader structure"] +impl crate::Readable for Sm2val3Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2val3::W`](W) writer structure"] +impl crate::Writable for Sm2val3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2VAL3 to value 0"] +impl crate::Resettable for Sm2val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val4.rs b/mcxa276-pac/src/flexpwm0/sm2val4.rs new file mode 100644 index 000000000..35a962784 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2val4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2VAL4` reader"] +pub type R = crate::R; +#[doc = "Register `SM2VAL4` writer"] +pub type W = crate::W; +#[doc = "Field `VAL4` reader - Value 4"] +pub type Val4R = crate::FieldReader; +#[doc = "Field `VAL4` writer - Value 4"] +pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&self) -> Val4R { + Val4R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&mut self) -> Val4W { + Val4W::new(self, 0) + } +} +#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2val4Spec; +impl crate::RegisterSpec for Sm2val4Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2val4::R`](R) reader structure"] +impl crate::Readable for Sm2val4Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2val4::W`](W) writer structure"] +impl crate::Writable for Sm2val4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2VAL4 to value 0"] +impl crate::Resettable for Sm2val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val5.rs b/mcxa276-pac/src/flexpwm0/sm2val5.rs new file mode 100644 index 000000000..4f570009f --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm2val5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM2VAL5` reader"] +pub type R = crate::R; +#[doc = "Register `SM2VAL5` writer"] +pub type W = crate::W; +#[doc = "Field `VAL5` reader - Value 5"] +pub type Val5R = crate::FieldReader; +#[doc = "Field `VAL5` writer - Value 5"] +pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&self) -> Val5R { + Val5R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&mut self) -> Val5W { + Val5W::new(self, 0) + } +} +#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm2val5Spec; +impl crate::RegisterSpec for Sm2val5Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm2val5::R`](R) reader structure"] +impl crate::Readable for Sm2val5Spec {} +#[doc = "`write(|w| ..)` method takes [`sm2val5::W`](W) writer structure"] +impl crate::Writable for Sm2val5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM2VAL5 to value 0"] +impl crate::Resettable for Sm2val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3captcompx.rs b/mcxa276-pac/src/flexpwm0/sm3captcompx.rs new file mode 100644 index 000000000..62f88b8e0 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3captcompx.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SM3CAPTCOMPX` reader"] +pub type R = crate::R; +#[doc = "Register `SM3CAPTCOMPX` writer"] +pub type W = crate::W; +#[doc = "Field `EDGCMPX` reader - Edge Compare X"] +pub type EdgcmpxR = crate::FieldReader; +#[doc = "Field `EDGCMPX` writer - Edge Compare X"] +pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EDGCNTX` reader - Edge Counter X"] +pub type EdgcntxR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&self) -> EdgcmpxR { + EdgcmpxR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Edge Counter X"] + #[inline(always)] + pub fn edgcntx(&self) -> EdgcntxR { + EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Edge Compare X"] + #[inline(always)] + pub fn edgcmpx(&mut self) -> EdgcmpxW { + EdgcmpxW::new(self, 0) + } +} +#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3captcompxSpec; +impl crate::RegisterSpec for Sm3captcompxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3captcompx::R`](R) reader structure"] +impl crate::Readable for Sm3captcompxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3captcompx::W`](W) writer structure"] +impl crate::Writable for Sm3captcompxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3CAPTCOMPX to value 0"] +impl crate::Resettable for Sm3captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm3captctrlx.rs new file mode 100644 index 000000000..dc88b9521 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3captctrlx.rs @@ -0,0 +1,493 @@ +#[doc = "Register `SM3CAPTCTRLX` reader"] +pub type R = crate::R; +#[doc = "Register `SM3CAPTCTRLX` writer"] +pub type W = crate::W; +#[doc = "Arm X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Armx { + #[doc = "0: Input capture operation is disabled."] + Disabled = 0, + #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Armx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARMX` reader - Arm X"] +pub type ArmxR = crate::BitReader; +impl ArmxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Armx { + match self.bits { + false => Armx::Disabled, + true => Armx::Enabled, + } + } + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Armx::Disabled + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Armx::Enabled + } +} +#[doc = "Field `ARMX` writer - Arm X"] +pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; +impl<'a, REG> ArmxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input capture operation is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Armx::Disabled) + } + #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Armx::Enabled) + } +} +#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oneshotx { + #[doc = "0: Free Running"] + FreeRunning = 0, + #[doc = "1: One Shot"] + OneShot = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oneshotx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] +pub type OneshotxR = crate::BitReader; +impl OneshotxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oneshotx { + match self.bits { + false => Oneshotx::FreeRunning, + true => Oneshotx::OneShot, + } + } + #[doc = "Free Running"] + #[inline(always)] + pub fn is_free_running(&self) -> bool { + *self == Oneshotx::FreeRunning + } + #[doc = "One Shot"] + #[inline(always)] + pub fn is_one_shot(&self) -> bool { + *self == Oneshotx::OneShot + } +} +#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] +pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; +impl<'a, REG> OneshotxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Free Running"] + #[inline(always)] + pub fn free_running(self) -> &'a mut crate::W { + self.variant(Oneshotx::FreeRunning) + } + #[doc = "One Shot"] + #[inline(always)] + pub fn one_shot(self) -> &'a mut crate::W { + self.variant(Oneshotx::OneShot) + } +} +#[doc = "Edge X 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx0 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx0 { + type Ux = u8; +} +impl crate::IsEnum for Edgx0 {} +#[doc = "Field `EDGX0` reader - Edge X 0"] +pub type Edgx0R = crate::FieldReader; +impl Edgx0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx0 { + match self.bits { + 0 => Edgx0::Disabled, + 1 => Edgx0::FallingEdge, + 2 => Edgx0::RisingEdge, + 3 => Edgx0::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx0::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx0::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx0::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx0::AnyEdge + } +} +#[doc = "Field `EDGX0` writer - Edge X 0"] +pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; +impl<'a, REG> Edgx0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx0::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx0::AnyEdge) + } +} +#[doc = "Edge X 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Edgx1 { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Capture falling edges"] + FallingEdge = 1, + #[doc = "2: Capture rising edges"] + RisingEdge = 2, + #[doc = "3: Capture any edge"] + AnyEdge = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Edgx1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Edgx1 { + type Ux = u8; +} +impl crate::IsEnum for Edgx1 {} +#[doc = "Field `EDGX1` reader - Edge X 1"] +pub type Edgx1R = crate::FieldReader; +impl Edgx1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edgx1 { + match self.bits { + 0 => Edgx1::Disabled, + 1 => Edgx1::FallingEdge, + 2 => Edgx1::RisingEdge, + 3 => Edgx1::AnyEdge, + _ => unreachable!(), + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Edgx1::Disabled + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == Edgx1::FallingEdge + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == Edgx1::RisingEdge + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn is_any_edge(&self) -> bool { + *self == Edgx1::AnyEdge + } +} +#[doc = "Field `EDGX1` writer - Edge X 1"] +pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; +impl<'a, REG> Edgx1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Edgx1::Disabled) + } + #[doc = "Capture falling edges"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::FallingEdge) + } + #[doc = "Capture rising edges"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::RisingEdge) + } + #[doc = "Capture any edge"] + #[inline(always)] + pub fn any_edge(self) -> &'a mut crate::W { + self.variant(Edgx1::AnyEdge) + } +} +#[doc = "Input Select X\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum InpSelx { + #[doc = "0: Raw PWM_X input signal selected as source."] + PwmX = 0, + #[doc = "1: Edge Counter"] + EdgeCounter = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: InpSelx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INP_SELX` reader - Input Select X"] +pub type InpSelxR = crate::BitReader; +impl InpSelxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InpSelx { + match self.bits { + false => InpSelx::PwmX, + true => InpSelx::EdgeCounter, + } + } + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InpSelx::PwmX + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn is_edge_counter(&self) -> bool { + *self == InpSelx::EdgeCounter + } +} +#[doc = "Field `INP_SELX` writer - Input Select X"] +pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; +impl<'a, REG> InpSelxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Raw PWM_X input signal selected as source."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InpSelx::PwmX) + } + #[doc = "Edge Counter"] + #[inline(always)] + pub fn edge_counter(self) -> &'a mut crate::W { + self.variant(InpSelx::EdgeCounter) + } +} +#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EdgcntxEn { + #[doc = "0: Edge counter disabled and held in reset"] + Disabled = 0, + #[doc = "1: Edge counter enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EdgcntxEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] +pub type EdgcntxEnR = crate::BitReader; +impl EdgcntxEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EdgcntxEn { + match self.bits { + false => EdgcntxEn::Disabled, + true => EdgcntxEn::Enabled, + } + } + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == EdgcntxEn::Disabled + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == EdgcntxEn::Enabled + } +} +#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] +pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; +impl<'a, REG> EdgcntxEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Edge counter disabled and held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Disabled) + } + #[doc = "Edge counter enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(EdgcntxEn::Enabled) + } +} +#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] +pub type CfxwmR = crate::FieldReader; +#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] +pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] +pub type Cx0cntR = crate::FieldReader; +#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] +pub type Cx1cntR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&self) -> ArmxR { + ArmxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&self) -> OneshotxR { + OneshotxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&self) -> Edgx0R { + Edgx0R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&self) -> Edgx1R { + Edgx1R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&self) -> InpSelxR { + InpSelxR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&self) -> EdgcntxEnR { + EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&self) -> CfxwmR { + CfxwmR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] + #[inline(always)] + pub fn cx0cnt(&self) -> Cx0cntR { + Cx0cntR::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] + #[inline(always)] + pub fn cx1cnt(&self) -> Cx1cntR { + Cx1cntR::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Arm X"] + #[inline(always)] + pub fn armx(&mut self) -> ArmxW { + ArmxW::new(self, 0) + } + #[doc = "Bit 1 - One Shot Mode Aux"] + #[inline(always)] + pub fn oneshotx(&mut self) -> OneshotxW { + OneshotxW::new(self, 1) + } + #[doc = "Bits 2:3 - Edge X 0"] + #[inline(always)] + pub fn edgx0(&mut self) -> Edgx0W { + Edgx0W::new(self, 2) + } + #[doc = "Bits 4:5 - Edge X 1"] + #[inline(always)] + pub fn edgx1(&mut self) -> Edgx1W { + Edgx1W::new(self, 4) + } + #[doc = "Bit 6 - Input Select X"] + #[inline(always)] + pub fn inp_selx(&mut self) -> InpSelxW { + InpSelxW::new(self, 6) + } + #[doc = "Bit 7 - Edge Counter X Enable"] + #[inline(always)] + pub fn edgcntx_en(&mut self) -> EdgcntxEnW { + EdgcntxEnW::new(self, 7) + } + #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] + #[inline(always)] + pub fn cfxwm(&mut self) -> CfxwmW { + CfxwmW::new(self, 8) + } +} +#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3captctrlxSpec; +impl crate::RegisterSpec for Sm3captctrlxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3captctrlx::R`](R) reader structure"] +impl crate::Readable for Sm3captctrlxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3captctrlx::W`](W) writer structure"] +impl crate::Writable for Sm3captctrlxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3CAPTCTRLX to value 0"] +impl crate::Resettable for Sm3captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm3captfiltx.rs new file mode 100644 index 000000000..4cb5c4899 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3captfiltx.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SM3CAPTFILTX` reader"] +pub type R = crate::R; +#[doc = "Register `SM3CAPTFILTX` writer"] +pub type W = crate::W; +#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] +pub type CaptxFiltPerR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] +pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] +pub type CaptxFiltCntR = crate::FieldReader; +#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] +pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&self) -> CaptxFiltPerR { + CaptxFiltPerR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { + CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Input Capture Filter Period"] + #[inline(always)] + pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { + CaptxFiltPerW::new(self, 0) + } + #[doc = "Bits 8:10 - Input Capture Filter Count"] + #[inline(always)] + pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { + CaptxFiltCntW::new(self, 8) + } +} +#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3captfiltxSpec; +impl crate::RegisterSpec for Sm3captfiltxSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3captfiltx::R`](R) reader structure"] +impl crate::Readable for Sm3captfiltxSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3captfiltx::W`](W) writer structure"] +impl crate::Writable for Sm3captfiltxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3CAPTFILTX to value 0"] +impl crate::Resettable for Sm3captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cnt.rs b/mcxa276-pac/src/flexpwm0/sm3cnt.rs new file mode 100644 index 000000000..14c00cbf3 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3cnt.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM3CNT` reader"] +pub type R = crate::R; +#[doc = "Field `CNT` reader - Counter Register Bits"] +pub type CntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Counter Register Bits"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3cntSpec; +impl crate::RegisterSpec for Sm3cntSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3cnt::R`](R) reader structure"] +impl crate::Readable for Sm3cntSpec {} +#[doc = "`reset()` method sets SM3CNT to value 0"] +impl crate::Resettable for Sm3cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3ctrl.rs b/mcxa276-pac/src/flexpwm0/sm3ctrl.rs new file mode 100644 index 000000000..832674137 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3ctrl.rs @@ -0,0 +1,871 @@ +#[doc = "Register `SM3CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM3CTRL` writer"] +pub type W = crate::W; +#[doc = "Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblen { + #[doc = "0: Double switching disabled."] + Disabled = 0, + #[doc = "1: Double switching enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLEN` reader - Double Switching Enable"] +pub type DblenR = crate::BitReader; +impl DblenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblen { + match self.bits { + false => Dblen::Disabled, + true => Dblen::Enabled, + } + } + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblen::Disabled + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblen::Enabled + } +} +#[doc = "Field `DBLEN` writer - Double Switching Enable"] +pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; +impl<'a, REG> DblenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Double switching disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblen::Disabled) + } + #[doc = "Double switching enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblen::Enabled) + } +} +#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dblx { + #[doc = "0: PWM_X double pulse disabled."] + Disabled = 0, + #[doc = "1: PWM_X double pulse enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dblx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] +pub type DblxR = crate::BitReader; +impl DblxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dblx { + match self.bits { + false => Dblx::Disabled, + true => Dblx::Enabled, + } + } + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dblx::Disabled + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dblx::Enabled + } +} +#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] +pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; +impl<'a, REG> DblxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X double pulse disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dblx::Disabled) + } + #[doc = "PWM_X double pulse enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dblx::Enabled) + } +} +#[doc = "Load Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldmod { + #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + NextPwmReload = 0, + #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + MtctrlLdokSet = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldmod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDMOD` reader - Load Mode Select"] +pub type LdmodR = crate::BitReader; +impl LdmodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldmod { + match self.bits { + false => Ldmod::NextPwmReload, + true => Ldmod::MtctrlLdokSet, + } + } + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn is_next_pwm_reload(&self) -> bool { + *self == Ldmod::NextPwmReload + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn is_mtctrl_ldok_set(&self) -> bool { + *self == Ldmod::MtctrlLdokSet + } +} +#[doc = "Field `LDMOD` writer - Load Mode Select"] +pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; +impl<'a, REG> LdmodW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] + #[inline(always)] + pub fn next_pwm_reload(self) -> &'a mut crate::W { + self.variant(Ldmod::NextPwmReload) + } + #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] + #[inline(always)] + pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { + self.variant(Ldmod::MtctrlLdokSet) + } +} +#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Split { + #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + Disabled = 0, + #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Split) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitR = crate::BitReader; +impl SplitR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Split { + match self.bits { + false => Split::Disabled, + true => Split::Enabled, + } + } + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Split::Disabled + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Split::Enabled + } +} +#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] +pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; +impl<'a, REG> SplitW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Split::Disabled) + } + #[doc = "DBLPWM is split to PWM_A and PWM_B."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Split::Enabled) + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Prsc { + #[doc = "0: Prescaler 1"] + One = 0, + #[doc = "1: Prescaler 2"] + Two = 1, + #[doc = "2: Prescaler 4"] + Four = 2, + #[doc = "3: Prescaler 8"] + Eight = 3, + #[doc = "4: Prescaler 16"] + Sixteen = 4, + #[doc = "5: Prescaler 32"] + Thirtytwo = 5, + #[doc = "6: Prescaler 64"] + Sixtyfour = 6, + #[doc = "7: Prescaler 128"] + Hundredtwentyeight = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Prsc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Prsc { + type Ux = u8; +} +impl crate::IsEnum for Prsc {} +#[doc = "Field `PRSC` reader - Prescaler"] +pub type PrscR = crate::FieldReader; +impl PrscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prsc { + match self.bits { + 0 => Prsc::One, + 1 => Prsc::Two, + 2 => Prsc::Four, + 3 => Prsc::Eight, + 4 => Prsc::Sixteen, + 5 => Prsc::Thirtytwo, + 6 => Prsc::Sixtyfour, + 7 => Prsc::Hundredtwentyeight, + _ => unreachable!(), + } + } + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Prsc::One + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn is_two(&self) -> bool { + *self == Prsc::Two + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn is_four(&self) -> bool { + *self == Prsc::Four + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn is_eight(&self) -> bool { + *self == Prsc::Eight + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn is_sixteen(&self) -> bool { + *self == Prsc::Sixteen + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn is_thirtytwo(&self) -> bool { + *self == Prsc::Thirtytwo + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn is_sixtyfour(&self) -> bool { + *self == Prsc::Sixtyfour + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn is_hundredtwentyeight(&self) -> bool { + *self == Prsc::Hundredtwentyeight + } +} +#[doc = "Field `PRSC` writer - Prescaler"] +pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; +impl<'a, REG> PrscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Prescaler 1"] + #[inline(always)] + pub fn one(self) -> &'a mut crate::W { + self.variant(Prsc::One) + } + #[doc = "Prescaler 2"] + #[inline(always)] + pub fn two(self) -> &'a mut crate::W { + self.variant(Prsc::Two) + } + #[doc = "Prescaler 4"] + #[inline(always)] + pub fn four(self) -> &'a mut crate::W { + self.variant(Prsc::Four) + } + #[doc = "Prescaler 8"] + #[inline(always)] + pub fn eight(self) -> &'a mut crate::W { + self.variant(Prsc::Eight) + } + #[doc = "Prescaler 16"] + #[inline(always)] + pub fn sixteen(self) -> &'a mut crate::W { + self.variant(Prsc::Sixteen) + } + #[doc = "Prescaler 32"] + #[inline(always)] + pub fn thirtytwo(self) -> &'a mut crate::W { + self.variant(Prsc::Thirtytwo) + } + #[doc = "Prescaler 64"] + #[inline(always)] + pub fn sixtyfour(self) -> &'a mut crate::W { + self.variant(Prsc::Sixtyfour) + } + #[doc = "Prescaler 128"] + #[inline(always)] + pub fn hundredtwentyeight(self) -> &'a mut crate::W { + self.variant(Prsc::Hundredtwentyeight) + } +} +#[doc = "Compare Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Compmode { + #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + EqualTo = 0, + #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + EqualToOrGreaterThan = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Compmode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPMODE` reader - Compare Mode"] +pub type CompmodeR = crate::BitReader; +impl CompmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Compmode { + match self.bits { + false => Compmode::EqualTo, + true => Compmode::EqualToOrGreaterThan, + } + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn is_equal_to(&self) -> bool { + *self == Compmode::EqualTo + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn is_equal_to_or_greater_than(&self) -> bool { + *self == Compmode::EqualToOrGreaterThan + } +} +#[doc = "Field `COMPMODE` writer - Compare Mode"] +pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; +impl<'a, REG> CompmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] + #[inline(always)] + pub fn equal_to(self) -> &'a mut crate::W { + self.variant(Compmode::EqualTo) + } + #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] + #[inline(always)] + pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { + self.variant(Compmode::EqualToOrGreaterThan) + } +} +#[doc = "Field `DT` reader - Deadtime"] +pub type DtR = crate::FieldReader; +#[doc = "Full Cycle Reload\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Full { + #[doc = "0: Full-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Full-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FULL` reader - Full Cycle Reload"] +pub type FullR = crate::BitReader; +impl FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Full { + match self.bits { + false => Full::Disabled, + true => Full::Enabled, + } + } + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Full::Disabled + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Full::Enabled + } +} +#[doc = "Field `FULL` writer - Full Cycle Reload"] +pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; +impl<'a, REG> FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Full-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Full::Disabled) + } + #[doc = "Full-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Full::Enabled) + } +} +#[doc = "Half Cycle Reload\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Half { + #[doc = "0: Half-cycle reloads disabled."] + Disabled = 0, + #[doc = "1: Half-cycle reloads enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Half) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALF` reader - Half Cycle Reload"] +pub type HalfR = crate::BitReader; +impl HalfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Half { + match self.bits { + false => Half::Disabled, + true => Half::Enabled, + } + } + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Half::Disabled + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Half::Enabled + } +} +#[doc = "Field `HALF` writer - Half Cycle Reload"] +pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; +impl<'a, REG> HalfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Half-cycle reloads disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Half::Disabled) + } + #[doc = "Half-cycle reloads enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Half::Enabled) + } +} +#[doc = "Load Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ldfq { + #[doc = "0: Every PWM opportunity"] + Everypwm = 0, + #[doc = "1: Every 2 PWM opportunities"] + Every2pwm = 1, + #[doc = "2: Every 3 PWM opportunities"] + Every3pwm = 2, + #[doc = "3: Every 4 PWM opportunities"] + Every4pwm = 3, + #[doc = "4: Every 5 PWM opportunities"] + Every5pwm = 4, + #[doc = "5: Every 6 PWM opportunities"] + Every6pwm = 5, + #[doc = "6: Every 7 PWM opportunities"] + Every7pwm = 6, + #[doc = "7: Every 8 PWM opportunities"] + Every8pwm = 7, + #[doc = "8: Every 9 PWM opportunities"] + Every9pwm = 8, + #[doc = "9: Every 10 PWM opportunities"] + Every10pwm = 9, + #[doc = "10: Every 11 PWM opportunities"] + Every11pwm = 10, + #[doc = "11: Every 12 PWM opportunities"] + Every12pwm = 11, + #[doc = "12: Every 13 PWM opportunities"] + Every13pwm = 12, + #[doc = "13: Every 14 PWM opportunities"] + Every14pwm = 13, + #[doc = "14: Every 15 PWM opportunities"] + Every15pwm = 14, + #[doc = "15: Every 16 PWM opportunities"] + Every16pwm = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ldfq) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ldfq { + type Ux = u8; +} +impl crate::IsEnum for Ldfq {} +#[doc = "Field `LDFQ` reader - Load Frequency"] +pub type LdfqR = crate::FieldReader; +impl LdfqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldfq { + match self.bits { + 0 => Ldfq::Everypwm, + 1 => Ldfq::Every2pwm, + 2 => Ldfq::Every3pwm, + 3 => Ldfq::Every4pwm, + 4 => Ldfq::Every5pwm, + 5 => Ldfq::Every6pwm, + 6 => Ldfq::Every7pwm, + 7 => Ldfq::Every8pwm, + 8 => Ldfq::Every9pwm, + 9 => Ldfq::Every10pwm, + 10 => Ldfq::Every11pwm, + 11 => Ldfq::Every12pwm, + 12 => Ldfq::Every13pwm, + 13 => Ldfq::Every14pwm, + 14 => Ldfq::Every15pwm, + 15 => Ldfq::Every16pwm, + _ => unreachable!(), + } + } + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Ldfq::Everypwm + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn is_every2pwm(&self) -> bool { + *self == Ldfq::Every2pwm + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn is_every3pwm(&self) -> bool { + *self == Ldfq::Every3pwm + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn is_every4pwm(&self) -> bool { + *self == Ldfq::Every4pwm + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn is_every5pwm(&self) -> bool { + *self == Ldfq::Every5pwm + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn is_every6pwm(&self) -> bool { + *self == Ldfq::Every6pwm + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn is_every7pwm(&self) -> bool { + *self == Ldfq::Every7pwm + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn is_every8pwm(&self) -> bool { + *self == Ldfq::Every8pwm + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn is_every9pwm(&self) -> bool { + *self == Ldfq::Every9pwm + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn is_every10pwm(&self) -> bool { + *self == Ldfq::Every10pwm + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn is_every11pwm(&self) -> bool { + *self == Ldfq::Every11pwm + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn is_every12pwm(&self) -> bool { + *self == Ldfq::Every12pwm + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn is_every13pwm(&self) -> bool { + *self == Ldfq::Every13pwm + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn is_every14pwm(&self) -> bool { + *self == Ldfq::Every14pwm + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn is_every15pwm(&self) -> bool { + *self == Ldfq::Every15pwm + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn is_every16pwm(&self) -> bool { + *self == Ldfq::Every16pwm + } +} +#[doc = "Field `LDFQ` writer - Load Frequency"] +pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; +impl<'a, REG> LdfqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Every PWM opportunity"] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Everypwm) + } + #[doc = "Every 2 PWM opportunities"] + #[inline(always)] + pub fn every2pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every2pwm) + } + #[doc = "Every 3 PWM opportunities"] + #[inline(always)] + pub fn every3pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every3pwm) + } + #[doc = "Every 4 PWM opportunities"] + #[inline(always)] + pub fn every4pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every4pwm) + } + #[doc = "Every 5 PWM opportunities"] + #[inline(always)] + pub fn every5pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every5pwm) + } + #[doc = "Every 6 PWM opportunities"] + #[inline(always)] + pub fn every6pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every6pwm) + } + #[doc = "Every 7 PWM opportunities"] + #[inline(always)] + pub fn every7pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every7pwm) + } + #[doc = "Every 8 PWM opportunities"] + #[inline(always)] + pub fn every8pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every8pwm) + } + #[doc = "Every 9 PWM opportunities"] + #[inline(always)] + pub fn every9pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every9pwm) + } + #[doc = "Every 10 PWM opportunities"] + #[inline(always)] + pub fn every10pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every10pwm) + } + #[doc = "Every 11 PWM opportunities"] + #[inline(always)] + pub fn every11pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every11pwm) + } + #[doc = "Every 12 PWM opportunities"] + #[inline(always)] + pub fn every12pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every12pwm) + } + #[doc = "Every 13 PWM opportunities"] + #[inline(always)] + pub fn every13pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every13pwm) + } + #[doc = "Every 14 PWM opportunities"] + #[inline(always)] + pub fn every14pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every14pwm) + } + #[doc = "Every 15 PWM opportunities"] + #[inline(always)] + pub fn every15pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every15pwm) + } + #[doc = "Every 16 PWM opportunities"] + #[inline(always)] + pub fn every16pwm(self) -> &'a mut crate::W { + self.variant(Ldfq::Every16pwm) + } +} +impl R { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&self) -> DblenR { + DblenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&self) -> DblxR { + DblxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&self) -> LdmodR { + LdmodR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&self) -> SplitR { + SplitR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&self) -> PrscR { + PrscR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&self) -> CompmodeR { + CompmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Deadtime"] + #[inline(always)] + pub fn dt(&self) -> DtR { + DtR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&self) -> FullR { + FullR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&self) -> HalfR { + HalfR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&self) -> LdfqR { + LdfqR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Double Switching Enable"] + #[inline(always)] + pub fn dblen(&mut self) -> DblenW { + DblenW::new(self, 0) + } + #[doc = "Bit 1 - PWM_X Double Switching Enable"] + #[inline(always)] + pub fn dblx(&mut self) -> DblxW { + DblxW::new(self, 1) + } + #[doc = "Bit 2 - Load Mode Select"] + #[inline(always)] + pub fn ldmod(&mut self) -> LdmodW { + LdmodW::new(self, 2) + } + #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] + #[inline(always)] + pub fn split(&mut self) -> SplitW { + SplitW::new(self, 3) + } + #[doc = "Bits 4:6 - Prescaler"] + #[inline(always)] + pub fn prsc(&mut self) -> PrscW { + PrscW::new(self, 4) + } + #[doc = "Bit 7 - Compare Mode"] + #[inline(always)] + pub fn compmode(&mut self) -> CompmodeW { + CompmodeW::new(self, 7) + } + #[doc = "Bit 10 - Full Cycle Reload"] + #[inline(always)] + pub fn full(&mut self) -> FullW { + FullW::new(self, 10) + } + #[doc = "Bit 11 - Half Cycle Reload"] + #[inline(always)] + pub fn half(&mut self) -> HalfW { + HalfW::new(self, 11) + } + #[doc = "Bits 12:15 - Load Frequency"] + #[inline(always)] + pub fn ldfq(&mut self) -> LdfqW { + LdfqW::new(self, 12) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3ctrlSpec; +impl crate::RegisterSpec for Sm3ctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3ctrl::R`](R) reader structure"] +impl crate::Readable for Sm3ctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3ctrl::W`](W) writer structure"] +impl crate::Writable for Sm3ctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3CTRL to value 0x0400"] +impl crate::Resettable for Sm3ctrlSpec { + const RESET_VALUE: u16 = 0x0400; +} diff --git a/mcxa276-pac/src/flexpwm0/sm3ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm3ctrl2.rs new file mode 100644 index 000000000..22721e058 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3ctrl2.rs @@ -0,0 +1,607 @@ +#[doc = "Register `SM3CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM3CTRL2` writer"] +pub type W = crate::W; +#[doc = "Clock Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ClkSel { + #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] + Ipbus = 0, + #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] + ExtClk = 1, + #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + AuxClk = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ClkSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ClkSel { + type Ux = u8; +} +impl crate::IsEnum for ClkSel {} +#[doc = "Field `CLK_SEL` reader - Clock Source Select"] +pub type ClkSelR = crate::FieldReader; +impl ClkSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ClkSel::Ipbus), + 1 => Some(ClkSel::ExtClk), + 2 => Some(ClkSel::AuxClk), + _ => None, + } + } + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ipbus(&self) -> bool { + *self == ClkSel::Ipbus + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn is_ext_clk(&self) -> bool { + *self == ClkSel::ExtClk + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn is_aux_clk(&self) -> bool { + *self == ClkSel::AuxClk + } +} +#[doc = "Field `CLK_SEL` writer - Clock Source Select"] +pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; +impl<'a, REG> ClkSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ipbus(self) -> &'a mut crate::W { + self.variant(ClkSel::Ipbus) + } + #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] + #[inline(always)] + pub fn ext_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::ExtClk) + } + #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] + #[inline(always)] + pub fn aux_clk(self) -> &'a mut crate::W { + self.variant(ClkSel::AuxClk) + } +} +#[doc = "Reload Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ReloadSel { + #[doc = "0: The local RELOAD signal is used to reload registers."] + Local = 0, + #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + Master = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ReloadSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] +pub type ReloadSelR = crate::BitReader; +impl ReloadSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ReloadSel { + match self.bits { + false => ReloadSel::Local, + true => ReloadSel::Master, + } + } + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ReloadSel::Local + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ReloadSel::Master + } +} +#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] +pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; +impl<'a, REG> ReloadSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The local RELOAD signal is used to reload registers."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ReloadSel::Local) + } + #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ReloadSel::Master) + } +} +#[doc = "Force Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ForceSel { + #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + Local = 0, + #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + Master = 1, + #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + LocalReload = 2, + #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterReload = 3, + #[doc = "4: The local sync signal from this submodule is used to force updates."] + LocalSync = 4, + #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + MasterSync = 5, + #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + ExtForce = 6, + #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + ExtSync = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ForceSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ForceSel { + type Ux = u8; +} +impl crate::IsEnum for ForceSel {} +#[doc = "Field `FORCE_SEL` reader - Force Select"] +pub type ForceSelR = crate::FieldReader; +impl ForceSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ForceSel { + match self.bits { + 0 => ForceSel::Local, + 1 => ForceSel::Master, + 2 => ForceSel::LocalReload, + 3 => ForceSel::MasterReload, + 4 => ForceSel::LocalSync, + 5 => ForceSel::MasterSync, + 6 => ForceSel::ExtForce, + 7 => ForceSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local(&self) -> bool { + *self == ForceSel::Local + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == ForceSel::Master + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == ForceSel::LocalReload + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == ForceSel::MasterReload + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == ForceSel::LocalSync + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == ForceSel::MasterSync + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_force(&self) -> bool { + *self == ForceSel::ExtForce + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == ForceSel::ExtSync + } +} +#[doc = "Field `FORCE_SEL` writer - Force Select"] +pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; +impl<'a, REG> ForceSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] + #[inline(always)] + pub fn local(self) -> &'a mut crate::W { + self.variant(ForceSel::Local) + } + #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(ForceSel::Master) + } + #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalReload) + } + #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterReload) + } + #[doc = "The local sync signal from this submodule is used to force updates."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::LocalSync) + } + #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::MasterSync) + } + #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_force(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtForce) + } + #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(ForceSel::ExtSync) + } +} +#[doc = "Field `FORCE` reader - Force Initialization"] +pub type ForceR = crate::BitReader; +#[doc = "Field `FORCE` writer - Force Initialization"] +pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Force Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frcen { + #[doc = "0: Initialization from a FORCE_OUT is disabled."] + Disabled = 0, + #[doc = "1: Initialization from a FORCE_OUT is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRCEN` reader - Force Enable"] +pub type FrcenR = crate::BitReader; +impl FrcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frcen { + match self.bits { + false => Frcen::Disabled, + true => Frcen::Enabled, + } + } + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Frcen::Disabled + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Frcen::Enabled + } +} +#[doc = "Field `FRCEN` writer - Force Enable"] +pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; +impl<'a, REG> FrcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Initialization from a FORCE_OUT is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Frcen::Disabled) + } + #[doc = "Initialization from a FORCE_OUT is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Frcen::Enabled) + } +} +#[doc = "Initialization Control Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum InitSel { + #[doc = "0: Local sync (PWM_X) causes initialization."] + PwmX = 0, + #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + MasterReload = 1, + #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + MasterSync = 2, + #[doc = "3: EXT_SYNC causes initialization."] + ExtSync = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: InitSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for InitSel { + type Ux = u8; +} +impl crate::IsEnum for InitSel {} +#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] +pub type InitSelR = crate::FieldReader; +impl InitSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> InitSel { + match self.bits { + 0 => InitSel::PwmX, + 1 => InitSel::MasterReload, + 2 => InitSel::MasterSync, + 3 => InitSel::ExtSync, + _ => unreachable!(), + } + } + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn is_pwm_x(&self) -> bool { + *self == InitSel::PwmX + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn is_master_reload(&self) -> bool { + *self == InitSel::MasterReload + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn is_master_sync(&self) -> bool { + *self == InitSel::MasterSync + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn is_ext_sync(&self) -> bool { + *self == InitSel::ExtSync + } +} +#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] +pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; +impl<'a, REG> InitSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Local sync (PWM_X) causes initialization."] + #[inline(always)] + pub fn pwm_x(self) -> &'a mut crate::W { + self.variant(InitSel::PwmX) + } + #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] + #[inline(always)] + pub fn master_reload(self) -> &'a mut crate::W { + self.variant(InitSel::MasterReload) + } + #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] + #[inline(always)] + pub fn master_sync(self) -> &'a mut crate::W { + self.variant(InitSel::MasterSync) + } + #[doc = "EXT_SYNC causes initialization."] + #[inline(always)] + pub fn ext_sync(self) -> &'a mut crate::W { + self.variant(InitSel::ExtSync) + } +} +#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] +pub type PwmxInitR = crate::BitReader; +#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] +pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] +pub type Pwm45InitR = crate::BitReader; +#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] +pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] +pub type Pwm23InitR = crate::BitReader; +#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] +pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Indep { + #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] + Complementary = 0, + #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] + Independent = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Indep) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] +pub type IndepR = crate::BitReader; +impl IndepR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Indep { + match self.bits { + false => Indep::Complementary, + true => Indep::Independent, + } + } + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn is_complementary(&self) -> bool { + *self == Indep::Complementary + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn is_independent(&self) -> bool { + *self == Indep::Independent + } +} +#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] +pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; +impl<'a, REG> IndepW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A and PWM_B form a complementary PWM pair."] + #[inline(always)] + pub fn complementary(self) -> &'a mut crate::W { + self.variant(Indep::Complementary) + } + #[doc = "PWM_A and PWM_B outputs are independent PWMs."] + #[inline(always)] + pub fn independent(self) -> &'a mut crate::W { + self.variant(Indep::Independent) + } +} +#[doc = "Field `DBGEN` reader - Debug Enable"] +pub type DbgenR = crate::BitReader; +#[doc = "Field `DBGEN` writer - Debug Enable"] +pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&self) -> ClkSelR { + ClkSelR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&self) -> ReloadSelR { + ReloadSelR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&self) -> ForceSelR { + ForceSelR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&self) -> ForceR { + ForceR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&self) -> FrcenR { + FrcenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&self) -> InitSelR { + InitSelR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&self) -> PwmxInitR { + PwmxInitR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&self) -> Pwm45InitR { + Pwm45InitR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&self) -> Pwm23InitR { + Pwm23InitR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&self) -> IndepR { + IndepR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&self) -> DbgenR { + DbgenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Clock Source Select"] + #[inline(always)] + pub fn clk_sel(&mut self) -> ClkSelW { + ClkSelW::new(self, 0) + } + #[doc = "Bit 2 - Reload Source Select"] + #[inline(always)] + pub fn reload_sel(&mut self) -> ReloadSelW { + ReloadSelW::new(self, 2) + } + #[doc = "Bits 3:5 - Force Select"] + #[inline(always)] + pub fn force_sel(&mut self) -> ForceSelW { + ForceSelW::new(self, 3) + } + #[doc = "Bit 6 - Force Initialization"] + #[inline(always)] + pub fn force(&mut self) -> ForceW { + ForceW::new(self, 6) + } + #[doc = "Bit 7 - Force Enable"] + #[inline(always)] + pub fn frcen(&mut self) -> FrcenW { + FrcenW::new(self, 7) + } + #[doc = "Bits 8:9 - Initialization Control Select"] + #[inline(always)] + pub fn init_sel(&mut self) -> InitSelW { + InitSelW::new(self, 8) + } + #[doc = "Bit 10 - PWM_X Initial Value"] + #[inline(always)] + pub fn pwmx_init(&mut self) -> PwmxInitW { + PwmxInitW::new(self, 10) + } + #[doc = "Bit 11 - PWM45 Initial Value"] + #[inline(always)] + pub fn pwm45_init(&mut self) -> Pwm45InitW { + Pwm45InitW::new(self, 11) + } + #[doc = "Bit 12 - PWM23 Initial Value"] + #[inline(always)] + pub fn pwm23_init(&mut self) -> Pwm23InitW { + Pwm23InitW::new(self, 12) + } + #[doc = "Bit 13 - Independent or Complementary Pair Operation"] + #[inline(always)] + pub fn indep(&mut self) -> IndepW { + IndepW::new(self, 13) + } + #[doc = "Bit 15 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&mut self) -> DbgenW { + DbgenW::new(self, 15) + } +} +#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3ctrl2Spec; +impl crate::RegisterSpec for Sm3ctrl2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3ctrl2::R`](R) reader structure"] +impl crate::Readable for Sm3ctrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3ctrl2::W`](W) writer structure"] +impl crate::Writable for Sm3ctrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3CTRL2 to value 0"] +impl crate::Resettable for Sm3ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval0.rs b/mcxa276-pac/src/flexpwm0/sm3cval0.rs new file mode 100644 index 000000000..5a45fd69d --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3cval0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM3CVAL0` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] +pub type Captval0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 0"] + #[inline(always)] + pub fn captval0(&self) -> Captval0R { + Captval0R::new(self.bits) + } +} +#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3cval0Spec; +impl crate::RegisterSpec for Sm3cval0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3cval0::R`](R) reader structure"] +impl crate::Readable for Sm3cval0Spec {} +#[doc = "`reset()` method sets SM3CVAL0 to value 0"] +impl crate::Resettable for Sm3cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs new file mode 100644 index 000000000..ecfc79254 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM3CVAL0CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] +pub type Cval0cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 0 Cycle"] + #[inline(always)] + pub fn cval0cyc(&self) -> Cval0cycR { + Cval0cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3cval0cycSpec; +impl crate::RegisterSpec for Sm3cval0cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3cval0cyc::R`](R) reader structure"] +impl crate::Readable for Sm3cval0cycSpec {} +#[doc = "`reset()` method sets SM3CVAL0CYC to value 0"] +impl crate::Resettable for Sm3cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval1.rs b/mcxa276-pac/src/flexpwm0/sm3cval1.rs new file mode 100644 index 000000000..de6510093 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3cval1.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM3CVAL1` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] +pub type Captval1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Capture Value 1"] + #[inline(always)] + pub fn captval1(&self) -> Captval1R { + Captval1R::new(self.bits) + } +} +#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3cval1Spec; +impl crate::RegisterSpec for Sm3cval1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3cval1::R`](R) reader structure"] +impl crate::Readable for Sm3cval1Spec {} +#[doc = "`reset()` method sets SM3CVAL1 to value 0"] +impl crate::Resettable for Sm3cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs new file mode 100644 index 000000000..bf80ed837 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SM3CVAL1CYC` reader"] +pub type R = crate::R; +#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] +pub type Cval1cycR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Capture Value 1 Cycle"] + #[inline(always)] + pub fn cval1cyc(&self) -> Cval1cycR { + Cval1cycR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3cval1cycSpec; +impl crate::RegisterSpec for Sm3cval1cycSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3cval1cyc::R`](R) reader structure"] +impl crate::Readable for Sm3cval1cycSpec {} +#[doc = "`reset()` method sets SM3CVAL1CYC to value 0"] +impl crate::Resettable for Sm3cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3dismap0.rs b/mcxa276-pac/src/flexpwm0/sm3dismap0.rs new file mode 100644 index 000000000..e1553271f --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3dismap0.rs @@ -0,0 +1,65 @@ +#[doc = "Register `SM3DISMAP0` reader"] +pub type R = crate::R; +#[doc = "Register `SM3DISMAP0` writer"] +pub type W = crate::W; +#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] +pub type Dis0aR = crate::FieldReader; +#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] +pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] +pub type Dis0bR = crate::FieldReader; +#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] +pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] +pub type Dis0xR = crate::FieldReader; +#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] +pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&self) -> Dis0aR { + Dis0aR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&self) -> Dis0bR { + Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&self) -> Dis0xR { + Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0a(&mut self) -> Dis0aW { + Dis0aW::new(self, 0) + } + #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0b(&mut self) -> Dis0bW { + Dis0bW::new(self, 4) + } + #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] + #[inline(always)] + pub fn dis0x(&mut self) -> Dis0xW { + Dis0xW::new(self, 8) + } +} +#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3dismap0Spec; +impl crate::RegisterSpec for Sm3dismap0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3dismap0::R`](R) reader structure"] +impl crate::Readable for Sm3dismap0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3dismap0::W`](W) writer structure"] +impl crate::Writable for Sm3dismap0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3DISMAP0 to value 0xffff"] +impl crate::Resettable for Sm3dismap0Spec { + const RESET_VALUE: u16 = 0xffff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm3dmaen.rs b/mcxa276-pac/src/flexpwm0/sm3dmaen.rs new file mode 100644 index 000000000..b4f400b8f --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3dmaen.rs @@ -0,0 +1,271 @@ +#[doc = "Register `SM3DMAEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM3DMAEN` writer"] +pub type W = crate::W; +#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] +pub type Cx0deR = crate::BitReader; +#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] +pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] +pub type Cx1deR = crate::BitReader; +#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] +pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Captde { + #[doc = "0: Read DMA requests disabled."] + Disabled = 0, + #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + Exceedfifo = 1, + #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] + LocalSync = 2, + #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] + LocalReload = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Captde) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Captde { + type Ux = u8; +} +impl crate::IsEnum for Captde {} +#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] +pub type CaptdeR = crate::FieldReader; +impl CaptdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Captde { + match self.bits { + 0 => Captde::Disabled, + 1 => Captde::Exceedfifo, + 2 => Captde::LocalSync, + 3 => Captde::LocalReload, + _ => unreachable!(), + } + } + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Captde::Disabled + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn is_exceedfifo(&self) -> bool { + *self == Captde::Exceedfifo + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn is_local_sync(&self) -> bool { + *self == Captde::LocalSync + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn is_local_reload(&self) -> bool { + *self == Captde::LocalReload + } +} +#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] +pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; +impl<'a, REG> CaptdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Read DMA requests disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Captde::Disabled) + } + #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] + #[inline(always)] + pub fn exceedfifo(self) -> &'a mut crate::W { + self.variant(Captde::Exceedfifo) + } + #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] + #[inline(always)] + pub fn local_sync(self) -> &'a mut crate::W { + self.variant(Captde::LocalSync) + } + #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] + #[inline(always)] + pub fn local_reload(self) -> &'a mut crate::W { + self.variant(Captde::LocalReload) + } +} +#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fand { + #[doc = "0: Selected FIFO watermarks are OR'ed together."] + Or = 0, + #[doc = "1: Selected FIFO watermarks are AND'ed together."] + And = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fand) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] +pub type FandR = crate::BitReader; +impl FandR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fand { + match self.bits { + false => Fand::Or, + true => Fand::And, + } + } + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn is_or(&self) -> bool { + *self == Fand::Or + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn is_and(&self) -> bool { + *self == Fand::And + } +} +#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] +pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; +impl<'a, REG> FandW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Selected FIFO watermarks are OR'ed together."] + #[inline(always)] + pub fn or(self) -> &'a mut crate::W { + self.variant(Fand::Or) + } + #[doc = "Selected FIFO watermarks are AND'ed together."] + #[inline(always)] + pub fn and(self) -> &'a mut crate::W { + self.variant(Fand::And) + } +} +#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Valde { + #[doc = "0: DMA write requests disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Valde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] +pub type ValdeR = crate::BitReader; +impl ValdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Valde { + match self.bits { + false => Valde::Disabled, + true => Valde::Enabled, + } + } + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Valde::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Valde::Enabled + } +} +#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] +pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; +impl<'a, REG> ValdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DMA write requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Valde::Disabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Valde::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&self) -> Cx0deR { + Cx0deR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&self) -> Cx1deR { + Cx1deR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&self) -> CaptdeR { + CaptdeR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&self) -> FandR { + FandR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&self) -> ValdeR { + ValdeR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] + #[inline(always)] + pub fn cx0de(&mut self) -> Cx0deW { + Cx0deW::new(self, 0) + } + #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] + #[inline(always)] + pub fn cx1de(&mut self) -> Cx1deW { + Cx1deW::new(self, 1) + } + #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] + #[inline(always)] + pub fn captde(&mut self) -> CaptdeW { + CaptdeW::new(self, 6) + } + #[doc = "Bit 8 - FIFO Watermark AND Control"] + #[inline(always)] + pub fn fand(&mut self) -> FandW { + FandW::new(self, 8) + } + #[doc = "Bit 9 - Value Registers DMA Enable"] + #[inline(always)] + pub fn valde(&mut self) -> ValdeW { + ValdeW::new(self, 9) + } +} +#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3dmaenSpec; +impl crate::RegisterSpec for Sm3dmaenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3dmaen::R`](R) reader structure"] +impl crate::Readable for Sm3dmaenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3dmaen::W`](W) writer structure"] +impl crate::Writable for Sm3dmaenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3DMAEN to value 0"] +impl crate::Resettable for Sm3dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs new file mode 100644 index 000000000..80a4a13e8 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM3DTCNT0` reader"] +pub type R = crate::R; +#[doc = "Register `SM3DTCNT0` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] +pub type Dtcnt0R = crate::FieldReader; +#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] +pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&self) -> Dtcnt0R { + Dtcnt0R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 0"] + #[inline(always)] + pub fn dtcnt0(&mut self) -> Dtcnt0W { + Dtcnt0W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3dtcnt0Spec; +impl crate::RegisterSpec for Sm3dtcnt0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3dtcnt0::R`](R) reader structure"] +impl crate::Readable for Sm3dtcnt0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3dtcnt0::W`](W) writer structure"] +impl crate::Writable for Sm3dtcnt0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3DTCNT0 to value 0x07ff"] +impl crate::Resettable for Sm3dtcnt0Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs new file mode 100644 index 000000000..2d83230bc --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SM3DTCNT1` reader"] +pub type R = crate::R; +#[doc = "Register `SM3DTCNT1` writer"] +pub type W = crate::W; +#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] +pub type Dtcnt1R = crate::FieldReader; +#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] +pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&self) -> Dtcnt1R { + Dtcnt1R::new(self.bits & 0x07ff) + } +} +impl W { + #[doc = "Bits 0:10 - Deadtime Count Register 1"] + #[inline(always)] + pub fn dtcnt1(&mut self) -> Dtcnt1W { + Dtcnt1W::new(self, 0) + } +} +#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3dtcnt1Spec; +impl crate::RegisterSpec for Sm3dtcnt1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3dtcnt1::R`](R) reader structure"] +impl crate::Readable for Sm3dtcnt1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3dtcnt1::W`](W) writer structure"] +impl crate::Writable for Sm3dtcnt1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3DTCNT1 to value 0x07ff"] +impl crate::Resettable for Sm3dtcnt1Spec { + const RESET_VALUE: u16 = 0x07ff; +} diff --git a/mcxa276-pac/src/flexpwm0/sm3init.rs b/mcxa276-pac/src/flexpwm0/sm3init.rs new file mode 100644 index 000000000..e71f5609d --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3init.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3INIT` reader"] +pub type R = crate::R; +#[doc = "Register `SM3INIT` writer"] +pub type W = crate::W; +#[doc = "Field `INIT` reader - Initial Count Register Bits"] +pub type InitR = crate::FieldReader; +#[doc = "Field `INIT` writer - Initial Count Register Bits"] +pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&self) -> InitR { + InitR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn init(&mut self) -> InitW { + InitW::new(self, 0) + } +} +#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3initSpec; +impl crate::RegisterSpec for Sm3initSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3init::R`](R) reader structure"] +impl crate::Readable for Sm3initSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3init::W`](W) writer structure"] +impl crate::Writable for Sm3initSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3INIT to value 0"] +impl crate::Resettable for Sm3initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3inten.rs b/mcxa276-pac/src/flexpwm0/sm3inten.rs new file mode 100644 index 000000000..6dd4613d4 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3inten.rs @@ -0,0 +1,343 @@ +#[doc = "Register `SM3INTEN` reader"] +pub type R = crate::R; +#[doc = "Register `SM3INTEN` writer"] +pub type W = crate::W; +#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpie { + #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + Disabled = 0, + #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + Enabled = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpie) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpie { + type Ux = u8; +} +impl crate::IsEnum for Cmpie {} +#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] +pub type CmpieR = crate::FieldReader; +impl CmpieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpie::Disabled), + 1 => Some(Cmpie::Enabled), + _ => None, + } + } + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmpie::Disabled + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmpie::Enabled + } +} +#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] +pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; +impl<'a, REG> CmpieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Disabled) + } + #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmpie::Enabled) + } +} +#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx0ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx0ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] +pub type Cx0ieR = crate::BitReader; +impl Cx0ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx0ie { + match self.bits { + false => Cx0ie::Disabled, + true => Cx0ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx0ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx0ie::Enabled + } +} +#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] +pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; +impl<'a, REG> Cx0ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx0ie::Enabled) + } +} +#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cx1ie { + #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] + Disabled = 0, + #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cx1ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] +pub type Cx1ieR = crate::BitReader; +impl Cx1ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cx1ie { + match self.bits { + false => Cx1ie::Disabled, + true => Cx1ie::Enabled, + } + } + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cx1ie::Disabled + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cx1ie::Enabled + } +} +#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] +pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; +impl<'a, REG> Cx1ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Disabled) + } + #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cx1ie::Enabled) + } +} +#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rie { + #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RIE` reader - Reload Interrupt Enable"] +pub type RieR = crate::BitReader; +impl RieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rie { + match self.bits { + false => Rie::Disabled, + true => Rie::Enabled, + } + } + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rie::Disabled + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rie::Enabled + } +} +#[doc = "Field `RIE` writer - Reload Interrupt Enable"] +pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; +impl<'a, REG> RieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rie::Disabled) + } + #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rie::Enabled) + } +} +#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reie { + #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] + Disabled = 0, + #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] +pub type ReieR = crate::BitReader; +impl ReieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reie { + match self.bits { + false => Reie::Disabled, + true => Reie::Enabled, + } + } + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Reie::Disabled + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Reie::Enabled + } +} +#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] +pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; +impl<'a, REG> ReieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Reie::Disabled) + } + #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Reie::Enabled) + } +} +impl R { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&self) -> CmpieR { + CmpieR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&self) -> Cx0ieR { + Cx0ieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&self) -> Cx1ieR { + Cx1ieR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RieR { + RieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&self) -> ReieR { + ReieR::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Interrupt Enables"] + #[inline(always)] + pub fn cmpie(&mut self) -> CmpieW { + CmpieW::new(self, 0) + } + #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] + #[inline(always)] + pub fn cx0ie(&mut self) -> Cx0ieW { + Cx0ieW::new(self, 6) + } + #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] + #[inline(always)] + pub fn cx1ie(&mut self) -> Cx1ieW { + Cx1ieW::new(self, 7) + } + #[doc = "Bit 12 - Reload Interrupt Enable"] + #[inline(always)] + pub fn rie(&mut self) -> RieW { + RieW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&mut self) -> ReieW { + ReieW::new(self, 13) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3intenSpec; +impl crate::RegisterSpec for Sm3intenSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3inten::R`](R) reader structure"] +impl crate::Readable for Sm3intenSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3inten::W`](W) writer structure"] +impl crate::Writable for Sm3intenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3INTEN to value 0"] +impl crate::Resettable for Sm3intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3octrl.rs b/mcxa276-pac/src/flexpwm0/sm3octrl.rs new file mode 100644 index 000000000..a83bd4c8e --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3octrl.rs @@ -0,0 +1,519 @@ +#[doc = "Register `SM3OCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM3OCTRL` writer"] +pub type W = crate::W; +#[doc = "PWM_X Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmxfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmxfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmxfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmxfs {} +#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] +pub type PwmxfsR = crate::FieldReader; +impl PwmxfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmxfs { + match self.bits { + 0 => Pwmxfs::Logic0, + 1 => Pwmxfs::Logic1, + 2 => Pwmxfs::Tristated2, + 3 => Pwmxfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmxfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmxfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmxfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmxfs::Tristated3 + } +} +#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] +pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; +impl<'a, REG> PwmxfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmxfs::Tristated3) + } +} +#[doc = "PWM_B Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmbfs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmbfs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmbfs { + type Ux = u8; +} +impl crate::IsEnum for Pwmbfs {} +#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] +pub type PwmbfsR = crate::FieldReader; +impl PwmbfsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmbfs { + match self.bits { + 0 => Pwmbfs::Logic0, + 1 => Pwmbfs::Logic1, + 2 => Pwmbfs::Tristated2, + 3 => Pwmbfs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmbfs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmbfs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmbfs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmbfs::Tristated3 + } +} +#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] +pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; +impl<'a, REG> PwmbfsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmbfs::Tristated3) + } +} +#[doc = "PWM_A Fault State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pwmafs { + #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] + Logic0 = 0, + #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] + Logic1 = 1, + #[doc = "2: Output is put in a high-impedance state."] + Tristated2 = 2, + #[doc = "3: Output is put in a high-impedance state."] + Tristated3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pwmafs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pwmafs { + type Ux = u8; +} +impl crate::IsEnum for Pwmafs {} +#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] +pub type PwmafsR = crate::FieldReader; +impl PwmafsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmafs { + match self.bits { + 0 => Pwmafs::Logic0, + 1 => Pwmafs::Logic1, + 2 => Pwmafs::Tristated2, + 3 => Pwmafs::Tristated3, + _ => unreachable!(), + } + } + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Pwmafs::Logic0 + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Pwmafs::Logic1 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_2(&self) -> bool { + *self == Pwmafs::Tristated2 + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn is_tristated_3(&self) -> bool { + *self == Pwmafs::Tristated3 + } +} +#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] +pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; +impl<'a, REG> PwmafsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic0) + } + #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Pwmafs::Logic1) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_2(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated2) + } + #[doc = "Output is put in a high-impedance state."] + #[inline(always)] + pub fn tristated_3(self) -> &'a mut crate::W { + self.variant(Pwmafs::Tristated3) + } +} +#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polx { + #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLX` reader - PWM_X Output Polarity"] +pub type PolxR = crate::BitReader; +impl PolxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polx { + match self.bits { + false => Polx::NotInverted, + true => Polx::Inverted, + } + } + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polx::NotInverted + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polx::Inverted + } +} +#[doc = "Field `POLX` writer - PWM_X Output Polarity"] +pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; +impl<'a, REG> PolxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polx::NotInverted) + } + #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polx::Inverted) + } +} +#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Polb { + #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Polb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLB` reader - PWM_B Output Polarity"] +pub type PolbR = crate::BitReader; +impl PolbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Polb { + match self.bits { + false => Polb::NotInverted, + true => Polb::Inverted, + } + } + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Polb::NotInverted + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Polb::Inverted + } +} +#[doc = "Field `POLB` writer - PWM_B Output Polarity"] +pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; +impl<'a, REG> PolbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Polb::NotInverted) + } + #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Polb::Inverted) + } +} +#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pola { + #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + NotInverted = 0, + #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pola) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POLA` reader - PWM_A Output Polarity"] +pub type PolaR = crate::BitReader; +impl PolaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pola { + match self.bits { + false => Pola::NotInverted, + true => Pola::Inverted, + } + } + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Pola::NotInverted + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Pola::Inverted + } +} +#[doc = "Field `POLA` writer - PWM_A Output Polarity"] +pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; +impl<'a, REG> PolaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Pola::NotInverted) + } + #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Pola::Inverted) + } +} +#[doc = "Field `PWMX_IN` reader - PWM_X Input"] +pub type PwmxInR = crate::BitReader; +#[doc = "Field `PWMB_IN` reader - PWM_B Input"] +pub type PwmbInR = crate::BitReader; +#[doc = "Field `PWMA_IN` reader - PWM_A Input"] +pub type PwmaInR = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&self) -> PwmxfsR { + PwmxfsR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&self) -> PwmbfsR { + PwmbfsR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&self) -> PwmafsR { + PwmafsR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&self) -> PolxR { + PolxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&self) -> PolbR { + PolbR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&self) -> PolaR { + PolaR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - PWM_X Input"] + #[inline(always)] + pub fn pwmx_in(&self) -> PwmxInR { + PwmxInR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PWM_B Input"] + #[inline(always)] + pub fn pwmb_in(&self) -> PwmbInR { + PwmbInR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - PWM_A Input"] + #[inline(always)] + pub fn pwma_in(&self) -> PwmaInR { + PwmaInR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - PWM_X Fault State"] + #[inline(always)] + pub fn pwmxfs(&mut self) -> PwmxfsW { + PwmxfsW::new(self, 0) + } + #[doc = "Bits 2:3 - PWM_B Fault State"] + #[inline(always)] + pub fn pwmbfs(&mut self) -> PwmbfsW { + PwmbfsW::new(self, 2) + } + #[doc = "Bits 4:5 - PWM_A Fault State"] + #[inline(always)] + pub fn pwmafs(&mut self) -> PwmafsW { + PwmafsW::new(self, 4) + } + #[doc = "Bit 8 - PWM_X Output Polarity"] + #[inline(always)] + pub fn polx(&mut self) -> PolxW { + PolxW::new(self, 8) + } + #[doc = "Bit 9 - PWM_B Output Polarity"] + #[inline(always)] + pub fn polb(&mut self) -> PolbW { + PolbW::new(self, 9) + } + #[doc = "Bit 10 - PWM_A Output Polarity"] + #[inline(always)] + pub fn pola(&mut self) -> PolaW { + PolaW::new(self, 10) + } +} +#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3octrlSpec; +impl crate::RegisterSpec for Sm3octrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3octrl::R`](R) reader structure"] +impl crate::Readable for Sm3octrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3octrl::W`](W) writer structure"] +impl crate::Writable for Sm3octrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3OCTRL to value 0"] +impl crate::Resettable for Sm3octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3phasedly.rs b/mcxa276-pac/src/flexpwm0/sm3phasedly.rs new file mode 100644 index 000000000..ccaa095f9 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3phasedly.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3PHASEDLY` reader"] +pub type R = crate::R; +#[doc = "Register `SM3PHASEDLY` writer"] +pub type W = crate::W; +#[doc = "Field `PHASEDLY` reader - Initial Count Register Bits"] +pub type PhasedlyR = crate::FieldReader; +#[doc = "Field `PHASEDLY` writer - Initial Count Register Bits"] +pub type PhasedlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn phasedly(&self) -> PhasedlyR { + PhasedlyR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Initial Count Register Bits"] + #[inline(always)] + pub fn phasedly(&mut self) -> PhasedlyW { + PhasedlyW::new(self, 0) + } +} +#[doc = "Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3phasedly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3phasedly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3phasedlySpec; +impl crate::RegisterSpec for Sm3phasedlySpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3phasedly::R`](R) reader structure"] +impl crate::Readable for Sm3phasedlySpec {} +#[doc = "`write(|w| ..)` method takes [`sm3phasedly::W`](W) writer structure"] +impl crate::Writable for Sm3phasedlySpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3PHASEDLY to value 0"] +impl crate::Resettable for Sm3phasedlySpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3sts.rs b/mcxa276-pac/src/flexpwm0/sm3sts.rs new file mode 100644 index 000000000..5dd9c7723 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3sts.rs @@ -0,0 +1,287 @@ +#[doc = "Register `SM3STS` reader"] +pub type R = crate::R; +#[doc = "Register `SM3STS` writer"] +pub type W = crate::W; +#[doc = "Compare Flags\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmpf { + #[doc = "0: No compare event has occurred for a particular VALx value."] + NoEvent = 0, + #[doc = "1: A compare event has occurred for a particular VALx value."] + Event = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmpf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmpf { + type Ux = u8; +} +impl crate::IsEnum for Cmpf {} +#[doc = "Field `CMPF` reader - Compare Flags"] +pub type CmpfR = crate::FieldReader; +impl CmpfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmpf::NoEvent), + 1 => Some(Cmpf::Event), + _ => None, + } + } + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_no_event(&self) -> bool { + *self == Cmpf::NoEvent + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == Cmpf::Event + } +} +#[doc = "Field `CMPF` writer - Compare Flags"] +pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; +impl<'a, REG> CmpfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn no_event(self) -> &'a mut crate::W { + self.variant(Cmpf::NoEvent) + } + #[doc = "A compare event has occurred for a particular VALx value."] + #[inline(always)] + pub fn event(self) -> &'a mut crate::W { + self.variant(Cmpf::Event) + } +} +#[doc = "Field `CFX0` reader - Capture Flag X0"] +pub type Cfx0R = crate::BitReader; +#[doc = "Field `CFX0` writer - Capture Flag X0"] +pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CFX1` reader - Capture Flag X1"] +pub type Cfx1R = crate::BitReader; +#[doc = "Field `CFX1` writer - Capture Flag X1"] +pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Reload Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rf { + #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] + NoFlag = 0, + #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RF` reader - Reload Flag"] +pub type RfR = crate::BitReader; +impl RfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rf { + match self.bits { + false => Rf::NoFlag, + true => Rf::Flag, + } + } + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Rf::NoFlag + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Rf::Flag + } +} +#[doc = "Field `RF` writer - Reload Flag"] +pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; +impl<'a, REG> RfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Rf::NoFlag) + } + #[doc = "New reload cycle since last STS\\[RF\\] clearing"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Rf::Flag) + } +} +#[doc = "Reload Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ref { + #[doc = "0: No reload error occurred."] + NoFlag = 0, + #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ref) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REF` reader - Reload Error Flag"] +pub type RefR = crate::BitReader; +impl RefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ref { + match self.bits { + false => Ref::NoFlag, + true => Ref::Flag, + } + } + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ref::NoFlag + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ref::Flag + } +} +#[doc = "Field `REF` writer - Reload Error Flag"] +pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; +impl<'a, REG> RefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No reload error occurred."] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Ref::NoFlag) + } + #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Ref::Flag) + } +} +#[doc = "Registers Updated Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ruf { + #[doc = "0: No register update has occurred since last reload."] + NoFlag = 0, + #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ruf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RUF` reader - Registers Updated Flag"] +pub type RufR = crate::BitReader; +impl RufR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ruf { + match self.bits { + false => Ruf::NoFlag, + true => Ruf::Flag, + } + } + #[doc = "No register update has occurred since last reload."] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Ruf::NoFlag + } + #[doc = "At least one of the double buffered registers has been updated since the last reload."] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Ruf::Flag + } +} +impl R { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&self) -> CmpfR { + CmpfR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&self) -> Cfx0R { + Cfx0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&self) -> Cfx1R { + Cfx1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&self) -> RfR { + RfR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&self) -> RefR { + RefR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Registers Updated Flag"] + #[inline(always)] + pub fn ruf(&self) -> RufR { + RufR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Compare Flags"] + #[inline(always)] + pub fn cmpf(&mut self) -> CmpfW { + CmpfW::new(self, 0) + } + #[doc = "Bit 6 - Capture Flag X0"] + #[inline(always)] + pub fn cfx0(&mut self) -> Cfx0W { + Cfx0W::new(self, 6) + } + #[doc = "Bit 7 - Capture Flag X1"] + #[inline(always)] + pub fn cfx1(&mut self) -> Cfx1W { + Cfx1W::new(self, 7) + } + #[doc = "Bit 12 - Reload Flag"] + #[inline(always)] + pub fn rf(&mut self) -> RfW { + RfW::new(self, 12) + } + #[doc = "Bit 13 - Reload Error Flag"] + #[inline(always)] + pub fn ref_(&mut self) -> RefW { + RefW::new(self, 13) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3stsSpec; +impl crate::RegisterSpec for Sm3stsSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3sts::R`](R) reader structure"] +impl crate::Readable for Sm3stsSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3sts::W`](W) writer structure"] +impl crate::Writable for Sm3stsSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; +} +#[doc = "`reset()` method sets SM3STS to value 0"] +impl crate::Resettable for Sm3stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3tctrl.rs b/mcxa276-pac/src/flexpwm0/sm3tctrl.rs new file mode 100644 index 000000000..1cdc4fbc7 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3tctrl.rs @@ -0,0 +1,267 @@ +#[doc = "Register `SM3TCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM3TCTRL` writer"] +pub type W = crate::W; +#[doc = "Output Trigger Enables\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OutTrigEn { + #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + Val0 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OutTrigEn) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OutTrigEn { + type Ux = u8; +} +impl crate::IsEnum for OutTrigEn {} +#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] +pub type OutTrigEnR = crate::FieldReader; +impl OutTrigEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(OutTrigEn::Val0), + _ => None, + } + } + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == OutTrigEn::Val0 + } +} +#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] +pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; +impl<'a, REG> OutTrigEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] + #[inline(always)] + pub fn val0(self) -> &'a mut crate::W { + self.variant(OutTrigEn::Val0) + } +} +#[doc = "Trigger Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trgfrq { + #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Everypwm = 0, + #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + Finalpwm = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trgfrq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] +pub type TrgfrqR = crate::BitReader; +impl TrgfrqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgfrq { + match self.bits { + false => Trgfrq::Everypwm, + true => Trgfrq::Finalpwm, + } + } + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_everypwm(&self) -> bool { + *self == Trgfrq::Everypwm + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn is_finalpwm(&self) -> bool { + *self == Trgfrq::Finalpwm + } +} +#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] +pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; +impl<'a, REG> TrgfrqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn everypwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Everypwm) + } + #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] + #[inline(always)] + pub fn finalpwm(self) -> &'a mut crate::W { + self.variant(Trgfrq::Finalpwm) + } +} +#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwbot1 { + #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + PwmOutTrig1Signal = 0, + #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] + PwmbOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwbot1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] +pub type Pwbot1R = crate::BitReader; +impl Pwbot1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwbot1 { + match self.bits { + false => Pwbot1::PwmOutTrig1Signal, + true => Pwbot1::PwmbOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwm_out_trig1_signal(&self) -> bool { + *self == Pwbot1::PwmOutTrig1Signal + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn is_pwmb_output(&self) -> bool { + *self == Pwbot1::PwmbOutput + } +} +#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] +pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; +impl<'a, REG> Pwbot1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmOutTrig1Signal) + } + #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] + #[inline(always)] + pub fn pwmb_output(self) -> &'a mut crate::W { + self.variant(Pwbot1::PwmbOutput) + } +} +#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwaot0 { + #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + PwmOutTrig0Signal = 0, + #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] + PwmaOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwaot0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] +pub type Pwaot0R = crate::BitReader; +impl Pwaot0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwaot0 { + match self.bits { + false => Pwaot0::PwmOutTrig0Signal, + true => Pwaot0::PwmaOutput, + } + } + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwm_out_trig0_signal(&self) -> bool { + *self == Pwaot0::PwmOutTrig0Signal + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn is_pwma_output(&self) -> bool { + *self == Pwaot0::PwmaOutput + } +} +#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] +pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; +impl<'a, REG> Pwaot0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmOutTrig0Signal) + } + #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] + #[inline(always)] + pub fn pwma_output(self) -> &'a mut crate::W { + self.variant(Pwaot0::PwmaOutput) + } +} +impl R { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&self) -> OutTrigEnR { + OutTrigEnR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&self) -> TrgfrqR { + TrgfrqR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&self) -> Pwbot1R { + Pwbot1R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&self) -> Pwaot0R { + Pwaot0R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Output Trigger Enables"] + #[inline(always)] + pub fn out_trig_en(&mut self) -> OutTrigEnW { + OutTrigEnW::new(self, 0) + } + #[doc = "Bit 12 - Trigger Frequency"] + #[inline(always)] + pub fn trgfrq(&mut self) -> TrgfrqW { + TrgfrqW::new(self, 12) + } + #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] + #[inline(always)] + pub fn pwbot1(&mut self) -> Pwbot1W { + Pwbot1W::new(self, 14) + } + #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] + #[inline(always)] + pub fn pwaot0(&mut self) -> Pwaot0W { + Pwaot0W::new(self, 15) + } +} +#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3tctrlSpec; +impl crate::RegisterSpec for Sm3tctrlSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3tctrl::R`](R) reader structure"] +impl crate::Readable for Sm3tctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sm3tctrl::W`](W) writer structure"] +impl crate::Writable for Sm3tctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3TCTRL to value 0"] +impl crate::Resettable for Sm3tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val0.rs b/mcxa276-pac/src/flexpwm0/sm3val0.rs new file mode 100644 index 000000000..bce081cba --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3val0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3VAL0` reader"] +pub type R = crate::R; +#[doc = "Register `SM3VAL0` writer"] +pub type W = crate::W; +#[doc = "Field `VAL0` reader - Value 0"] +pub type Val0R = crate::FieldReader; +#[doc = "Field `VAL0` writer - Value 0"] +pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&self) -> Val0R { + Val0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 0"] + #[inline(always)] + pub fn val0(&mut self) -> Val0W { + Val0W::new(self, 0) + } +} +#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3val0Spec; +impl crate::RegisterSpec for Sm3val0Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3val0::R`](R) reader structure"] +impl crate::Readable for Sm3val0Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3val0::W`](W) writer structure"] +impl crate::Writable for Sm3val0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3VAL0 to value 0"] +impl crate::Resettable for Sm3val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val1.rs b/mcxa276-pac/src/flexpwm0/sm3val1.rs new file mode 100644 index 000000000..d54d73992 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3val1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3VAL1` reader"] +pub type R = crate::R; +#[doc = "Register `SM3VAL1` writer"] +pub type W = crate::W; +#[doc = "Field `VAL1` reader - Value 1"] +pub type Val1R = crate::FieldReader; +#[doc = "Field `VAL1` writer - Value 1"] +pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&self) -> Val1R { + Val1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 1"] + #[inline(always)] + pub fn val1(&mut self) -> Val1W { + Val1W::new(self, 0) + } +} +#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3val1Spec; +impl crate::RegisterSpec for Sm3val1Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3val1::R`](R) reader structure"] +impl crate::Readable for Sm3val1Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3val1::W`](W) writer structure"] +impl crate::Writable for Sm3val1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3VAL1 to value 0"] +impl crate::Resettable for Sm3val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val2.rs b/mcxa276-pac/src/flexpwm0/sm3val2.rs new file mode 100644 index 000000000..02c26ec2a --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3val2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3VAL2` reader"] +pub type R = crate::R; +#[doc = "Register `SM3VAL2` writer"] +pub type W = crate::W; +#[doc = "Field `VAL2` reader - Value 2"] +pub type Val2R = crate::FieldReader; +#[doc = "Field `VAL2` writer - Value 2"] +pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&self) -> Val2R { + Val2R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 2"] + #[inline(always)] + pub fn val2(&mut self) -> Val2W { + Val2W::new(self, 0) + } +} +#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3val2Spec; +impl crate::RegisterSpec for Sm3val2Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3val2::R`](R) reader structure"] +impl crate::Readable for Sm3val2Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3val2::W`](W) writer structure"] +impl crate::Writable for Sm3val2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3VAL2 to value 0"] +impl crate::Resettable for Sm3val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val3.rs b/mcxa276-pac/src/flexpwm0/sm3val3.rs new file mode 100644 index 000000000..443c3efc9 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3val3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3VAL3` reader"] +pub type R = crate::R; +#[doc = "Register `SM3VAL3` writer"] +pub type W = crate::W; +#[doc = "Field `VAL3` reader - Value 3"] +pub type Val3R = crate::FieldReader; +#[doc = "Field `VAL3` writer - Value 3"] +pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&self) -> Val3R { + Val3R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 3"] + #[inline(always)] + pub fn val3(&mut self) -> Val3W { + Val3W::new(self, 0) + } +} +#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3val3Spec; +impl crate::RegisterSpec for Sm3val3Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3val3::R`](R) reader structure"] +impl crate::Readable for Sm3val3Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3val3::W`](W) writer structure"] +impl crate::Writable for Sm3val3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3VAL3 to value 0"] +impl crate::Resettable for Sm3val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val4.rs b/mcxa276-pac/src/flexpwm0/sm3val4.rs new file mode 100644 index 000000000..6690c8284 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3val4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3VAL4` reader"] +pub type R = crate::R; +#[doc = "Register `SM3VAL4` writer"] +pub type W = crate::W; +#[doc = "Field `VAL4` reader - Value 4"] +pub type Val4R = crate::FieldReader; +#[doc = "Field `VAL4` writer - Value 4"] +pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&self) -> Val4R { + Val4R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 4"] + #[inline(always)] + pub fn val4(&mut self) -> Val4W { + Val4W::new(self, 0) + } +} +#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3val4Spec; +impl crate::RegisterSpec for Sm3val4Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3val4::R`](R) reader structure"] +impl crate::Readable for Sm3val4Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3val4::W`](W) writer structure"] +impl crate::Writable for Sm3val4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3VAL4 to value 0"] +impl crate::Resettable for Sm3val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val5.rs b/mcxa276-pac/src/flexpwm0/sm3val5.rs new file mode 100644 index 000000000..4b2b561f0 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/sm3val5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SM3VAL5` reader"] +pub type R = crate::R; +#[doc = "Register `SM3VAL5` writer"] +pub type W = crate::W; +#[doc = "Field `VAL5` reader - Value 5"] +pub type Val5R = crate::FieldReader; +#[doc = "Field `VAL5` writer - Value 5"] +pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&self) -> Val5R { + Val5R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Value 5"] + #[inline(always)] + pub fn val5(&mut self) -> Val5W { + Val5W::new(self, 0) + } +} +#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sm3val5Spec; +impl crate::RegisterSpec for Sm3val5Spec { + type Ux = u16; +} +#[doc = "`read()` method returns [`sm3val5::R`](R) reader structure"] +impl crate::Readable for Sm3val5Spec {} +#[doc = "`write(|w| ..)` method takes [`sm3val5::W`](W) writer structure"] +impl crate::Writable for Sm3val5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SM3VAL5 to value 0"] +impl crate::Resettable for Sm3val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/swcout.rs b/mcxa276-pac/src/flexpwm0/swcout.rs new file mode 100644 index 000000000..976f04130 --- /dev/null +++ b/mcxa276-pac/src/flexpwm0/swcout.rs @@ -0,0 +1,525 @@ +#[doc = "Register `SWCOUT` reader"] +pub type R = crate::R; +#[doc = "Register `SWCOUT` writer"] +pub type W = crate::W; +#[doc = "Submodule 0 Software Controlled Output 45\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm0out45 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm0out45) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM0OUT45` reader - Submodule 0 Software Controlled Output 45"] +pub type Sm0out45R = crate::BitReader; +impl Sm0out45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm0out45 { + match self.bits { + false => Sm0out45::Logic0, + true => Sm0out45::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm0out45::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm0out45::Logic1 + } +} +#[doc = "Field `SM0OUT45` writer - Submodule 0 Software Controlled Output 45"] +pub type Sm0out45W<'a, REG> = crate::BitWriter<'a, REG, Sm0out45>; +impl<'a, REG> Sm0out45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm0out45::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm0out45::Logic1) + } +} +#[doc = "Submodule 0 Software Controlled Output 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm0out23 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm0out23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM0OUT23` reader - Submodule 0 Software Controlled Output 23"] +pub type Sm0out23R = crate::BitReader; +impl Sm0out23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm0out23 { + match self.bits { + false => Sm0out23::Logic0, + true => Sm0out23::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm0out23::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm0out23::Logic1 + } +} +#[doc = "Field `SM0OUT23` writer - Submodule 0 Software Controlled Output 23"] +pub type Sm0out23W<'a, REG> = crate::BitWriter<'a, REG, Sm0out23>; +impl<'a, REG> Sm0out23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm0out23::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm0out23::Logic1) + } +} +#[doc = "Submodule 1 Software Controlled Output 45\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm1out45 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm1out45) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM1OUT45` reader - Submodule 1 Software Controlled Output 45"] +pub type Sm1out45R = crate::BitReader; +impl Sm1out45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm1out45 { + match self.bits { + false => Sm1out45::Logic0, + true => Sm1out45::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm1out45::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm1out45::Logic1 + } +} +#[doc = "Field `SM1OUT45` writer - Submodule 1 Software Controlled Output 45"] +pub type Sm1out45W<'a, REG> = crate::BitWriter<'a, REG, Sm1out45>; +impl<'a, REG> Sm1out45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm1out45::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm1out45::Logic1) + } +} +#[doc = "Submodule 1 Software Controlled Output 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm1out23 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm1out23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM1OUT23` reader - Submodule 1 Software Controlled Output 23"] +pub type Sm1out23R = crate::BitReader; +impl Sm1out23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm1out23 { + match self.bits { + false => Sm1out23::Logic0, + true => Sm1out23::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm1out23::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm1out23::Logic1 + } +} +#[doc = "Field `SM1OUT23` writer - Submodule 1 Software Controlled Output 23"] +pub type Sm1out23W<'a, REG> = crate::BitWriter<'a, REG, Sm1out23>; +impl<'a, REG> Sm1out23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm1out23::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm1out23::Logic1) + } +} +#[doc = "Submodule 2 Software Controlled Output 45\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm2out45 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm2out45) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM2OUT45` reader - Submodule 2 Software Controlled Output 45"] +pub type Sm2out45R = crate::BitReader; +impl Sm2out45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm2out45 { + match self.bits { + false => Sm2out45::Logic0, + true => Sm2out45::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm2out45::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm2out45::Logic1 + } +} +#[doc = "Field `SM2OUT45` writer - Submodule 2 Software Controlled Output 45"] +pub type Sm2out45W<'a, REG> = crate::BitWriter<'a, REG, Sm2out45>; +impl<'a, REG> Sm2out45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm2out45::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm2out45::Logic1) + } +} +#[doc = "Submodule 2 Software Controlled Output 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm2out23 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm2out23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM2OUT23` reader - Submodule 2 Software Controlled Output 23"] +pub type Sm2out23R = crate::BitReader; +impl Sm2out23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm2out23 { + match self.bits { + false => Sm2out23::Logic0, + true => Sm2out23::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm2out23::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm2out23::Logic1 + } +} +#[doc = "Field `SM2OUT23` writer - Submodule 2 Software Controlled Output 23"] +pub type Sm2out23W<'a, REG> = crate::BitWriter<'a, REG, Sm2out23>; +impl<'a, REG> Sm2out23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm2out23::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm2out23::Logic1) + } +} +#[doc = "Submodule 3 Software Controlled Output 45\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm3out45 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm3out45) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM3OUT45` reader - Submodule 3 Software Controlled Output 45"] +pub type Sm3out45R = crate::BitReader; +impl Sm3out45R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm3out45 { + match self.bits { + false => Sm3out45::Logic0, + true => Sm3out45::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm3out45::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm3out45::Logic1 + } +} +#[doc = "Field `SM3OUT45` writer - Submodule 3 Software Controlled Output 45"] +pub type Sm3out45W<'a, REG> = crate::BitWriter<'a, REG, Sm3out45>; +impl<'a, REG> Sm3out45W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm3out45::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm3out45::Logic1) + } +} +#[doc = "Submodule 3 Software Controlled Output 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sm3out23 { + #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."] + Logic0 = 0, + #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."] + Logic1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sm3out23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SM3OUT23` reader - Submodule 3 Software Controlled Output 23"] +pub type Sm3out23R = crate::BitReader; +impl Sm3out23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sm3out23 { + match self.bits { + false => Sm3out23::Logic0, + true => Sm3out23::Logic1, + } + } + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."] + #[inline(always)] + pub fn is_logic_0(&self) -> bool { + *self == Sm3out23::Logic0 + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."] + #[inline(always)] + pub fn is_logic_1(&self) -> bool { + *self == Sm3out23::Logic1 + } +} +#[doc = "Field `SM3OUT23` writer - Submodule 3 Software Controlled Output 23"] +pub type Sm3out23W<'a, REG> = crate::BitWriter<'a, REG, Sm3out23>; +impl<'a, REG> Sm3out23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."] + #[inline(always)] + pub fn logic_0(self) -> &'a mut crate::W { + self.variant(Sm3out23::Logic0) + } + #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."] + #[inline(always)] + pub fn logic_1(self) -> &'a mut crate::W { + self.variant(Sm3out23::Logic1) + } +} +impl R { + #[doc = "Bit 0 - Submodule 0 Software Controlled Output 45"] + #[inline(always)] + pub fn sm0out45(&self) -> Sm0out45R { + Sm0out45R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Submodule 0 Software Controlled Output 23"] + #[inline(always)] + pub fn sm0out23(&self) -> Sm0out23R { + Sm0out23R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Submodule 1 Software Controlled Output 45"] + #[inline(always)] + pub fn sm1out45(&self) -> Sm1out45R { + Sm1out45R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Submodule 1 Software Controlled Output 23"] + #[inline(always)] + pub fn sm1out23(&self) -> Sm1out23R { + Sm1out23R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Submodule 2 Software Controlled Output 45"] + #[inline(always)] + pub fn sm2out45(&self) -> Sm2out45R { + Sm2out45R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Submodule 2 Software Controlled Output 23"] + #[inline(always)] + pub fn sm2out23(&self) -> Sm2out23R { + Sm2out23R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Submodule 3 Software Controlled Output 45"] + #[inline(always)] + pub fn sm3out45(&self) -> Sm3out45R { + Sm3out45R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Submodule 3 Software Controlled Output 23"] + #[inline(always)] + pub fn sm3out23(&self) -> Sm3out23R { + Sm3out23R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Submodule 0 Software Controlled Output 45"] + #[inline(always)] + pub fn sm0out45(&mut self) -> Sm0out45W { + Sm0out45W::new(self, 0) + } + #[doc = "Bit 1 - Submodule 0 Software Controlled Output 23"] + #[inline(always)] + pub fn sm0out23(&mut self) -> Sm0out23W { + Sm0out23W::new(self, 1) + } + #[doc = "Bit 2 - Submodule 1 Software Controlled Output 45"] + #[inline(always)] + pub fn sm1out45(&mut self) -> Sm1out45W { + Sm1out45W::new(self, 2) + } + #[doc = "Bit 3 - Submodule 1 Software Controlled Output 23"] + #[inline(always)] + pub fn sm1out23(&mut self) -> Sm1out23W { + Sm1out23W::new(self, 3) + } + #[doc = "Bit 4 - Submodule 2 Software Controlled Output 45"] + #[inline(always)] + pub fn sm2out45(&mut self) -> Sm2out45W { + Sm2out45W::new(self, 4) + } + #[doc = "Bit 5 - Submodule 2 Software Controlled Output 23"] + #[inline(always)] + pub fn sm2out23(&mut self) -> Sm2out23W { + Sm2out23W::new(self, 5) + } + #[doc = "Bit 6 - Submodule 3 Software Controlled Output 45"] + #[inline(always)] + pub fn sm3out45(&mut self) -> Sm3out45W { + Sm3out45W::new(self, 6) + } + #[doc = "Bit 7 - Submodule 3 Software Controlled Output 23"] + #[inline(always)] + pub fn sm3out23(&mut self) -> Sm3out23W { + Sm3out23W::new(self, 7) + } +} +#[doc = "Software Controlled Output Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swcout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swcout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwcoutSpec; +impl crate::RegisterSpec for SwcoutSpec { + type Ux = u16; +} +#[doc = "`read()` method returns [`swcout::R`](R) reader structure"] +impl crate::Readable for SwcoutSpec {} +#[doc = "`write(|w| ..)` method takes [`swcout::W`](W) writer structure"] +impl crate::Writable for SwcoutSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWCOUT to value 0"] +impl crate::Resettable for SwcoutSpec {} diff --git a/mcxa276-pac/src/fmc0.rs b/mcxa276-pac/src/fmc0.rs new file mode 100644 index 000000000..aca9ec192 --- /dev/null +++ b/mcxa276-pac/src/fmc0.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x20], + remap: Remap, +} +impl RegisterBlock { + #[doc = "0x20 - Data Remap"] + #[inline(always)] + pub const fn remap(&self) -> &Remap { + &self.remap + } +} +#[doc = "REMAP (rw) register accessor: Data Remap\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap`] module"] +#[doc(alias = "REMAP")] +pub type Remap = crate::Reg; +#[doc = "Data Remap"] +pub mod remap; diff --git a/mcxa276-pac/src/fmc0/remap.rs b/mcxa276-pac/src/fmc0/remap.rs new file mode 100644 index 000000000..80438fc5f --- /dev/null +++ b/mcxa276-pac/src/fmc0/remap.rs @@ -0,0 +1,112 @@ +#[doc = "Register `REMAP` reader"] +pub type R = crate::R; +#[doc = "Register `REMAP` writer"] +pub type W = crate::W; +#[doc = "Remap Lock Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Remaplk { + #[doc = "0: Lock disabled: can write to REMAP"] + LockDisabled = 0, + #[doc = "1: Lock enabled: cannot write to REMAP"] + LockEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Remaplk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REMAPLK` reader - Remap Lock Enable"] +pub type RemaplkR = crate::BitReader; +impl RemaplkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Remaplk { + match self.bits { + false => Remaplk::LockDisabled, + true => Remaplk::LockEnabled, + } + } + #[doc = "Lock disabled: can write to REMAP"] + #[inline(always)] + pub fn is_lock_disabled(&self) -> bool { + *self == Remaplk::LockDisabled + } + #[doc = "Lock enabled: cannot write to REMAP"] + #[inline(always)] + pub fn is_lock_enabled(&self) -> bool { + *self == Remaplk::LockEnabled + } +} +#[doc = "Field `REMAPLK` writer - Remap Lock Enable"] +pub type RemaplkW<'a, REG> = crate::BitWriter<'a, REG, Remaplk>; +impl<'a, REG> RemaplkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Lock disabled: can write to REMAP"] + #[inline(always)] + pub fn lock_disabled(self) -> &'a mut crate::W { + self.variant(Remaplk::LockDisabled) + } + #[doc = "Lock enabled: cannot write to REMAP"] + #[inline(always)] + pub fn lock_enabled(self) -> &'a mut crate::W { + self.variant(Remaplk::LockEnabled) + } +} +#[doc = "Field `LIM` reader - LIM Remapping Address"] +pub type LimR = crate::FieldReader; +#[doc = "Field `LIM` writer - LIM Remapping Address"] +pub type LimW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LIMDP` reader - LIMDP Remapping Address"] +pub type LimdpR = crate::FieldReader; +#[doc = "Field `LIMDP` writer - LIMDP Remapping Address"] +pub type LimdpW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bit 0 - Remap Lock Enable"] + #[inline(always)] + pub fn remaplk(&self) -> RemaplkR { + RemaplkR::new((self.bits & 1) != 0) + } + #[doc = "Bits 16:22 - LIM Remapping Address"] + #[inline(always)] + pub fn lim(&self) -> LimR { + LimR::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - LIMDP Remapping Address"] + #[inline(always)] + pub fn limdp(&self) -> LimdpR { + LimdpR::new(((self.bits >> 24) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Remap Lock Enable"] + #[inline(always)] + pub fn remaplk(&mut self) -> RemaplkW { + RemaplkW::new(self, 0) + } + #[doc = "Bits 16:22 - LIM Remapping Address"] + #[inline(always)] + pub fn lim(&mut self) -> LimW { + LimW::new(self, 16) + } + #[doc = "Bits 24:30 - LIMDP Remapping Address"] + #[inline(always)] + pub fn limdp(&mut self) -> LimdpW { + LimdpW::new(self, 24) + } +} +#[doc = "Data Remap\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RemapSpec; +impl crate::RegisterSpec for RemapSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`remap::R`](R) reader structure"] +impl crate::Readable for RemapSpec {} +#[doc = "`write(|w| ..)` method takes [`remap::W`](W) writer structure"] +impl crate::Writable for RemapSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets REMAP to value 0"] +impl crate::Resettable for RemapSpec {} diff --git a/mcxa276-pac/src/fmu0.rs b/mcxa276-pac/src/fmu0.rs new file mode 100644 index 000000000..774fc87f3 --- /dev/null +++ b/mcxa276-pac/src/fmu0.rs @@ -0,0 +1,57 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + fstat: Fstat, + fcnfg: Fcnfg, + fctrl: Fctrl, + _reserved3: [u8; 0x04], + fccob: [Fccob; 8], +} +impl RegisterBlock { + #[doc = "0x00 - Flash Status Register"] + #[inline(always)] + pub const fn fstat(&self) -> &Fstat { + &self.fstat + } + #[doc = "0x04 - Flash Configuration Register"] + #[inline(always)] + pub const fn fcnfg(&self) -> &Fcnfg { + &self.fcnfg + } + #[doc = "0x08 - Flash Control Register"] + #[inline(always)] + pub const fn fctrl(&self) -> &Fctrl { + &self.fctrl + } + #[doc = "0x10..0x30 - Flash Common Command Object Registers"] + #[inline(always)] + pub const fn fccob(&self, n: usize) -> &Fccob { + &self.fccob[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x10..0x30 - Flash Common Command Object Registers"] + #[inline(always)] + pub fn fccob_iter(&self) -> impl Iterator { + self.fccob.iter() + } +} +#[doc = "FSTAT (rw) register accessor: Flash Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fstat`] module"] +#[doc(alias = "FSTAT")] +pub type Fstat = crate::Reg; +#[doc = "Flash Status Register"] +pub mod fstat; +#[doc = "FCNFG (rw) register accessor: Flash Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fcnfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcnfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcnfg`] module"] +#[doc(alias = "FCNFG")] +pub type Fcnfg = crate::Reg; +#[doc = "Flash Configuration Register"] +pub mod fcnfg; +#[doc = "FCTRL (rw) register accessor: Flash Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl`] module"] +#[doc(alias = "FCTRL")] +pub type Fctrl = crate::Reg; +#[doc = "Flash Control Register"] +pub mod fctrl; +#[doc = "FCCOB (rw) register accessor: Flash Common Command Object Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`fccob::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fccob::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fccob`] module"] +#[doc(alias = "FCCOB")] +pub type Fccob = crate::Reg; +#[doc = "Flash Common Command Object Registers"] +pub mod fccob; diff --git a/mcxa276-pac/src/fmu0/fccob.rs b/mcxa276-pac/src/fmu0/fccob.rs new file mode 100644 index 000000000..c515ff9c4 --- /dev/null +++ b/mcxa276-pac/src/fmu0/fccob.rs @@ -0,0 +1,35 @@ +#[doc = "Register `FCCOB%s` reader"] +pub type R = crate::R; +#[doc = "Register `FCCOB%s` writer"] +pub type W = crate::W; +#[doc = "Field `CCOBn` reader - CCOBn"] +pub type CcobnR = crate::FieldReader; +#[doc = "Field `CCOBn` writer - CCOBn"] +pub type CcobnW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - CCOBn"] + #[inline(always)] + pub fn ccobn(&self) -> CcobnR { + CcobnR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - CCOBn"] + #[inline(always)] + pub fn ccobn(&mut self) -> CcobnW { + CcobnW::new(self, 0) + } +} +#[doc = "Flash Common Command Object Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`fccob::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fccob::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FccobSpec; +impl crate::RegisterSpec for FccobSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fccob::R`](R) reader structure"] +impl crate::Readable for FccobSpec {} +#[doc = "`write(|w| ..)` method takes [`fccob::W`](W) writer structure"] +impl crate::Writable for FccobSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCCOB%s to value 0"] +impl crate::Resettable for FccobSpec {} diff --git a/mcxa276-pac/src/fmu0/fcnfg.rs b/mcxa276-pac/src/fmu0/fcnfg.rs new file mode 100644 index 000000000..b2add0044 --- /dev/null +++ b/mcxa276-pac/src/fmu0/fcnfg.rs @@ -0,0 +1,282 @@ +#[doc = "Register `FCNFG` reader"] +pub type R = crate::R; +#[doc = "Register `FCNFG` writer"] +pub type W = crate::W; +#[doc = "Command Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ccie { + #[doc = "0: Command complete interrupt disabled"] + Ccie0 = 0, + #[doc = "1: Command complete interrupt enabled"] + Ccie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ccie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CCIE` reader - Command Complete Interrupt Enable"] +pub type CcieR = crate::BitReader; +impl CcieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ccie { + match self.bits { + false => Ccie::Ccie0, + true => Ccie::Ccie1, + } + } + #[doc = "Command complete interrupt disabled"] + #[inline(always)] + pub fn is_ccie0(&self) -> bool { + *self == Ccie::Ccie0 + } + #[doc = "Command complete interrupt enabled"] + #[inline(always)] + pub fn is_ccie1(&self) -> bool { + *self == Ccie::Ccie1 + } +} +#[doc = "Field `CCIE` writer - Command Complete Interrupt Enable"] +pub type CcieW<'a, REG> = crate::BitWriter<'a, REG, Ccie>; +impl<'a, REG> CcieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Command complete interrupt disabled"] + #[inline(always)] + pub fn ccie0(self) -> &'a mut crate::W { + self.variant(Ccie::Ccie0) + } + #[doc = "Command complete interrupt enabled"] + #[inline(always)] + pub fn ccie1(self) -> &'a mut crate::W { + self.variant(Ccie::Ccie1) + } +} +#[doc = "Mass Erase Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ersreq { + #[doc = "0: No request or request complete"] + Ersreq0 = 0, + #[doc = "1: Request to run the Mass Erase operation"] + Ersreq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ersreq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERSREQ` reader - Mass Erase Request"] +pub type ErsreqR = crate::BitReader; +impl ErsreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ersreq { + match self.bits { + false => Ersreq::Ersreq0, + true => Ersreq::Ersreq1, + } + } + #[doc = "No request or request complete"] + #[inline(always)] + pub fn is_ersreq0(&self) -> bool { + *self == Ersreq::Ersreq0 + } + #[doc = "Request to run the Mass Erase operation"] + #[inline(always)] + pub fn is_ersreq1(&self) -> bool { + *self == Ersreq::Ersreq1 + } +} +#[doc = "Double Bit Fault Detect Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dfdie { + #[doc = "0: Double bit fault detect interrupt disabled"] + Dfdie0 = 0, + #[doc = "1: Double bit fault detect interrupt enabled"] + Dfdie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dfdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DFDIE` reader - Double Bit Fault Detect Interrupt Enable"] +pub type DfdieR = crate::BitReader; +impl DfdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dfdie { + match self.bits { + false => Dfdie::Dfdie0, + true => Dfdie::Dfdie1, + } + } + #[doc = "Double bit fault detect interrupt disabled"] + #[inline(always)] + pub fn is_dfdie0(&self) -> bool { + *self == Dfdie::Dfdie0 + } + #[doc = "Double bit fault detect interrupt enabled"] + #[inline(always)] + pub fn is_dfdie1(&self) -> bool { + *self == Dfdie::Dfdie1 + } +} +#[doc = "Field `DFDIE` writer - Double Bit Fault Detect Interrupt Enable"] +pub type DfdieW<'a, REG> = crate::BitWriter<'a, REG, Dfdie>; +impl<'a, REG> DfdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Double bit fault detect interrupt disabled"] + #[inline(always)] + pub fn dfdie0(self) -> &'a mut crate::W { + self.variant(Dfdie::Dfdie0) + } + #[doc = "Double bit fault detect interrupt enabled"] + #[inline(always)] + pub fn dfdie1(self) -> &'a mut crate::W { + self.variant(Dfdie::Dfdie1) + } +} +#[doc = "Erase IFR Sector Enable - Block 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ersien0 { + #[doc = "0: Block 0 IFR Sector X is protected from erase by ERSSCR command"] + Ersien00 = 0, + #[doc = "1: Block 0 IFR Sector X is not protected from erase by ERSSCR command"] + Ersien01 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ersien0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ersien0 { + type Ux = u8; +} +impl crate::IsEnum for Ersien0 {} +#[doc = "Field `ERSIEN0` reader - Erase IFR Sector Enable - Block 0"] +pub type Ersien0R = crate::FieldReader; +impl Ersien0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ersien0::Ersien00), + 1 => Some(Ersien0::Ersien01), + _ => None, + } + } + #[doc = "Block 0 IFR Sector X is protected from erase by ERSSCR command"] + #[inline(always)] + pub fn is_ersien00(&self) -> bool { + *self == Ersien0::Ersien00 + } + #[doc = "Block 0 IFR Sector X is not protected from erase by ERSSCR command"] + #[inline(always)] + pub fn is_ersien01(&self) -> bool { + *self == Ersien0::Ersien01 + } +} +#[doc = "Erase IFR Sector Enable - Block 1 (for dual block configs)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ersien1 { + #[doc = "0: Block 1 IFR Sector X is protected from erase by ERSSCR command"] + Ersien10 = 0, + #[doc = "1: Block 1 IFR Sector X is not protected from erase by ERSSCR command"] + Ersien11 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ersien1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ersien1 { + type Ux = u8; +} +impl crate::IsEnum for Ersien1 {} +#[doc = "Field `ERSIEN1` reader - Erase IFR Sector Enable - Block 1 (for dual block configs)"] +pub type Ersien1R = crate::FieldReader; +impl Ersien1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ersien1::Ersien10), + 1 => Some(Ersien1::Ersien11), + _ => None, + } + } + #[doc = "Block 1 IFR Sector X is protected from erase by ERSSCR command"] + #[inline(always)] + pub fn is_ersien10(&self) -> bool { + *self == Ersien1::Ersien10 + } + #[doc = "Block 1 IFR Sector X is not protected from erase by ERSSCR command"] + #[inline(always)] + pub fn is_ersien11(&self) -> bool { + *self == Ersien1::Ersien11 + } +} +impl R { + #[doc = "Bit 7 - Command Complete Interrupt Enable"] + #[inline(always)] + pub fn ccie(&self) -> CcieR { + CcieR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Mass Erase Request"] + #[inline(always)] + pub fn ersreq(&self) -> ErsreqR { + ErsreqR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Enable"] + #[inline(always)] + pub fn dfdie(&self) -> DfdieR { + DfdieR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 24:27 - Erase IFR Sector Enable - Block 0"] + #[inline(always)] + pub fn ersien0(&self) -> Ersien0R { + Ersien0R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Erase IFR Sector Enable - Block 1 (for dual block configs)"] + #[inline(always)] + pub fn ersien1(&self) -> Ersien1R { + Ersien1R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 7 - Command Complete Interrupt Enable"] + #[inline(always)] + pub fn ccie(&mut self) -> CcieW { + CcieW::new(self, 7) + } + #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Enable"] + #[inline(always)] + pub fn dfdie(&mut self) -> DfdieW { + DfdieW::new(self, 16) + } +} +#[doc = "Flash Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fcnfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcnfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FcnfgSpec; +impl crate::RegisterSpec for FcnfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fcnfg::R`](R) reader structure"] +impl crate::Readable for FcnfgSpec {} +#[doc = "`write(|w| ..)` method takes [`fcnfg::W`](W) writer structure"] +impl crate::Writable for FcnfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCNFG to value 0"] +impl crate::Resettable for FcnfgSpec {} diff --git a/mcxa276-pac/src/fmu0/fctrl.rs b/mcxa276-pac/src/fmu0/fctrl.rs new file mode 100644 index 000000000..8504ae006 --- /dev/null +++ b/mcxa276-pac/src/fmu0/fctrl.rs @@ -0,0 +1,226 @@ +#[doc = "Register `FCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `FCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `RWSC` reader - Read Wait-State Control"] +pub type RwscR = crate::FieldReader; +#[doc = "Field `RWSC` writer - Read Wait-State Control"] +pub type RwscW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Low speed active mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lsactive { + #[doc = "0: Full speed active mode requested"] + Lsactive0 = 0, + #[doc = "1: Low speed active mode requested"] + Lsactive1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lsactive) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LSACTIVE` reader - Low speed active mode"] +pub type LsactiveR = crate::BitReader; +impl LsactiveR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lsactive { + match self.bits { + false => Lsactive::Lsactive0, + true => Lsactive::Lsactive1, + } + } + #[doc = "Full speed active mode requested"] + #[inline(always)] + pub fn is_lsactive0(&self) -> bool { + *self == Lsactive::Lsactive0 + } + #[doc = "Low speed active mode requested"] + #[inline(always)] + pub fn is_lsactive1(&self) -> bool { + *self == Lsactive::Lsactive1 + } +} +#[doc = "Field `LSACTIVE` writer - Low speed active mode"] +pub type LsactiveW<'a, REG> = crate::BitWriter<'a, REG, Lsactive>; +impl<'a, REG> LsactiveW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Full speed active mode requested"] + #[inline(always)] + pub fn lsactive0(self) -> &'a mut crate::W { + self.variant(Lsactive::Lsactive0) + } + #[doc = "Low speed active mode requested"] + #[inline(always)] + pub fn lsactive1(self) -> &'a mut crate::W { + self.variant(Lsactive::Lsactive1) + } +} +#[doc = "Force Double Bit Fault Detect\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fdfd { + #[doc = "0: FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"] + Fdfd0 = 0, + #[doc = "1: FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."] + Fdfd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fdfd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FDFD` reader - Force Double Bit Fault Detect"] +pub type FdfdR = crate::BitReader; +impl FdfdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fdfd { + match self.bits { + false => Fdfd::Fdfd0, + true => Fdfd::Fdfd1, + } + } + #[doc = "FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"] + #[inline(always)] + pub fn is_fdfd0(&self) -> bool { + *self == Fdfd::Fdfd0 + } + #[doc = "FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."] + #[inline(always)] + pub fn is_fdfd1(&self) -> bool { + *self == Fdfd::Fdfd1 + } +} +#[doc = "Field `FDFD` writer - Force Double Bit Fault Detect"] +pub type FdfdW<'a, REG> = crate::BitWriter<'a, REG, Fdfd>; +impl<'a, REG> FdfdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"] + #[inline(always)] + pub fn fdfd0(self) -> &'a mut crate::W { + self.variant(Fdfd::Fdfd0) + } + #[doc = "FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."] + #[inline(always)] + pub fn fdfd1(self) -> &'a mut crate::W { + self.variant(Fdfd::Fdfd1) + } +} +#[doc = "Abort Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Abtreq { + #[doc = "0: No request to abort a command write sequence"] + Abtreq0 = 0, + #[doc = "1: Request to abort a command write sequence"] + Abtreq1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Abtreq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABTREQ` reader - Abort Request"] +pub type AbtreqR = crate::BitReader; +impl AbtreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Abtreq { + match self.bits { + false => Abtreq::Abtreq0, + true => Abtreq::Abtreq1, + } + } + #[doc = "No request to abort a command write sequence"] + #[inline(always)] + pub fn is_abtreq0(&self) -> bool { + *self == Abtreq::Abtreq0 + } + #[doc = "Request to abort a command write sequence"] + #[inline(always)] + pub fn is_abtreq1(&self) -> bool { + *self == Abtreq::Abtreq1 + } +} +#[doc = "Field `ABTREQ` writer - Abort Request"] +pub type AbtreqW<'a, REG> = crate::BitWriter<'a, REG, Abtreq>; +impl<'a, REG> AbtreqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No request to abort a command write sequence"] + #[inline(always)] + pub fn abtreq0(self) -> &'a mut crate::W { + self.variant(Abtreq::Abtreq0) + } + #[doc = "Request to abort a command write sequence"] + #[inline(always)] + pub fn abtreq1(self) -> &'a mut crate::W { + self.variant(Abtreq::Abtreq1) + } +} +impl R { + #[doc = "Bits 0:3 - Read Wait-State Control"] + #[inline(always)] + pub fn rwsc(&self) -> RwscR { + RwscR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Low speed active mode"] + #[inline(always)] + pub fn lsactive(&self) -> LsactiveR { + LsactiveR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Force Double Bit Fault Detect"] + #[inline(always)] + pub fn fdfd(&self) -> FdfdR { + FdfdR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 24 - Abort Request"] + #[inline(always)] + pub fn abtreq(&self) -> AbtreqR { + AbtreqR::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Read Wait-State Control"] + #[inline(always)] + pub fn rwsc(&mut self) -> RwscW { + RwscW::new(self, 0) + } + #[doc = "Bit 8 - Low speed active mode"] + #[inline(always)] + pub fn lsactive(&mut self) -> LsactiveW { + LsactiveW::new(self, 8) + } + #[doc = "Bit 16 - Force Double Bit Fault Detect"] + #[inline(always)] + pub fn fdfd(&mut self) -> FdfdW { + FdfdW::new(self, 16) + } + #[doc = "Bit 24 - Abort Request"] + #[inline(always)] + pub fn abtreq(&mut self) -> AbtreqW { + AbtreqW::new(self, 24) + } +} +#[doc = "Flash Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FctrlSpec; +impl crate::RegisterSpec for FctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fctrl::R`](R) reader structure"] +impl crate::Readable for FctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`fctrl::W`](W) writer structure"] +impl crate::Writable for FctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCTRL to value 0x0100"] +impl crate::Resettable for FctrlSpec { + const RESET_VALUE: u32 = 0x0100; +} diff --git a/mcxa276-pac/src/fmu0/fstat.rs b/mcxa276-pac/src/fmu0/fstat.rs new file mode 100644 index 000000000..7dc1014d4 --- /dev/null +++ b/mcxa276-pac/src/fmu0/fstat.rs @@ -0,0 +1,713 @@ +#[doc = "Register `FSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `FSTAT` writer"] +pub type W = crate::W; +#[doc = "Command Fail Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fail { + #[doc = "0: Error not detected"] + Fail0 = 0, + #[doc = "1: Error detected"] + Fail1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fail) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FAIL` reader - Command Fail Flag"] +pub type FailR = crate::BitReader; +impl FailR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fail { + match self.bits { + false => Fail::Fail0, + true => Fail::Fail1, + } + } + #[doc = "Error not detected"] + #[inline(always)] + pub fn is_fail0(&self) -> bool { + *self == Fail::Fail0 + } + #[doc = "Error detected"] + #[inline(always)] + pub fn is_fail1(&self) -> bool { + *self == Fail::Fail1 + } +} +#[doc = "Command Abort Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmdabt { + #[doc = "0: No command abort detected"] + Cmdabt0 = 0, + #[doc = "1: Command abort detected"] + Cmdabt1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmdabt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMDABT` reader - Command Abort Flag"] +pub type CmdabtR = crate::BitReader; +impl CmdabtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmdabt { + match self.bits { + false => Cmdabt::Cmdabt0, + true => Cmdabt::Cmdabt1, + } + } + #[doc = "No command abort detected"] + #[inline(always)] + pub fn is_cmdabt0(&self) -> bool { + *self == Cmdabt::Cmdabt0 + } + #[doc = "Command abort detected"] + #[inline(always)] + pub fn is_cmdabt1(&self) -> bool { + *self == Cmdabt::Cmdabt1 + } +} +#[doc = "Field `CMDABT` writer - Command Abort Flag"] +pub type CmdabtW<'a, REG> = crate::BitWriter1C<'a, REG, Cmdabt>; +impl<'a, REG> CmdabtW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No command abort detected"] + #[inline(always)] + pub fn cmdabt0(self) -> &'a mut crate::W { + self.variant(Cmdabt::Cmdabt0) + } + #[doc = "Command abort detected"] + #[inline(always)] + pub fn cmdabt1(self) -> &'a mut crate::W { + self.variant(Cmdabt::Cmdabt1) + } +} +#[doc = "Command Protection Violation Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pviol { + #[doc = "0: No protection violation detected"] + Pviol0 = 0, + #[doc = "1: Protection violation detected"] + Pviol1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pviol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PVIOL` reader - Command Protection Violation Flag"] +pub type PviolR = crate::BitReader; +impl PviolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pviol { + match self.bits { + false => Pviol::Pviol0, + true => Pviol::Pviol1, + } + } + #[doc = "No protection violation detected"] + #[inline(always)] + pub fn is_pviol0(&self) -> bool { + *self == Pviol::Pviol0 + } + #[doc = "Protection violation detected"] + #[inline(always)] + pub fn is_pviol1(&self) -> bool { + *self == Pviol::Pviol1 + } +} +#[doc = "Field `PVIOL` writer - Command Protection Violation Flag"] +pub type PviolW<'a, REG> = crate::BitWriter1C<'a, REG, Pviol>; +impl<'a, REG> PviolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No protection violation detected"] + #[inline(always)] + pub fn pviol0(self) -> &'a mut crate::W { + self.variant(Pviol::Pviol0) + } + #[doc = "Protection violation detected"] + #[inline(always)] + pub fn pviol1(self) -> &'a mut crate::W { + self.variant(Pviol::Pviol1) + } +} +#[doc = "Command Access Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Accerr { + #[doc = "0: No access error detected"] + Accerr0 = 0, + #[doc = "1: Access error detected"] + Accerr1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Accerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACCERR` reader - Command Access Error Flag"] +pub type AccerrR = crate::BitReader; +impl AccerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Accerr { + match self.bits { + false => Accerr::Accerr0, + true => Accerr::Accerr1, + } + } + #[doc = "No access error detected"] + #[inline(always)] + pub fn is_accerr0(&self) -> bool { + *self == Accerr::Accerr0 + } + #[doc = "Access error detected"] + #[inline(always)] + pub fn is_accerr1(&self) -> bool { + *self == Accerr::Accerr1 + } +} +#[doc = "Field `ACCERR` writer - Command Access Error Flag"] +pub type AccerrW<'a, REG> = crate::BitWriter1C<'a, REG, Accerr>; +impl<'a, REG> AccerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No access error detected"] + #[inline(always)] + pub fn accerr0(self) -> &'a mut crate::W { + self.variant(Accerr::Accerr0) + } + #[doc = "Access error detected"] + #[inline(always)] + pub fn accerr1(self) -> &'a mut crate::W { + self.variant(Accerr::Accerr1) + } +} +#[doc = "Command Write Sequence Abort Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cwsabt { + #[doc = "0: Command write sequence not aborted"] + Cwsabt0 = 0, + #[doc = "1: Command write sequence aborted"] + Cwsabt1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cwsabt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CWSABT` reader - Command Write Sequence Abort Flag"] +pub type CwsabtR = crate::BitReader; +impl CwsabtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cwsabt { + match self.bits { + false => Cwsabt::Cwsabt0, + true => Cwsabt::Cwsabt1, + } + } + #[doc = "Command write sequence not aborted"] + #[inline(always)] + pub fn is_cwsabt0(&self) -> bool { + *self == Cwsabt::Cwsabt0 + } + #[doc = "Command write sequence aborted"] + #[inline(always)] + pub fn is_cwsabt1(&self) -> bool { + *self == Cwsabt::Cwsabt1 + } +} +#[doc = "Field `CWSABT` writer - Command Write Sequence Abort Flag"] +pub type CwsabtW<'a, REG> = crate::BitWriter1C<'a, REG, Cwsabt>; +impl<'a, REG> CwsabtW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Command write sequence not aborted"] + #[inline(always)] + pub fn cwsabt0(self) -> &'a mut crate::W { + self.variant(Cwsabt::Cwsabt0) + } + #[doc = "Command write sequence aborted"] + #[inline(always)] + pub fn cwsabt1(self) -> &'a mut crate::W { + self.variant(Cwsabt::Cwsabt1) + } +} +#[doc = "Command Complete Interrupt Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ccif { + #[doc = "0: Flash command, initialization, or power mode recovery in progress"] + Ccif0 = 0, + #[doc = "1: Flash command, initialization, or power mode recovery has completed"] + Ccif1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ccif) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CCIF` reader - Command Complete Interrupt Flag"] +pub type CcifR = crate::BitReader; +impl CcifR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ccif { + match self.bits { + false => Ccif::Ccif0, + true => Ccif::Ccif1, + } + } + #[doc = "Flash command, initialization, or power mode recovery in progress"] + #[inline(always)] + pub fn is_ccif0(&self) -> bool { + *self == Ccif::Ccif0 + } + #[doc = "Flash command, initialization, or power mode recovery has completed"] + #[inline(always)] + pub fn is_ccif1(&self) -> bool { + *self == Ccif::Ccif1 + } +} +#[doc = "Field `CCIF` writer - Command Complete Interrupt Flag"] +pub type CcifW<'a, REG> = crate::BitWriter1C<'a, REG, Ccif>; +impl<'a, REG> CcifW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Flash command, initialization, or power mode recovery in progress"] + #[inline(always)] + pub fn ccif0(self) -> &'a mut crate::W { + self.variant(Ccif::Ccif0) + } + #[doc = "Flash command, initialization, or power mode recovery has completed"] + #[inline(always)] + pub fn ccif1(self) -> &'a mut crate::W { + self.variant(Ccif::Ccif1) + } +} +#[doc = "Command protection level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmdprt { + #[doc = "0: Secure, normal access"] + Cmdprt00 = 0, + #[doc = "1: Secure, privileged access"] + Cmdprt01 = 1, + #[doc = "2: Nonsecure, normal access"] + Cmdprt10 = 2, + #[doc = "3: Nonsecure, privileged access"] + Cmdprt11 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmdprt) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmdprt { + type Ux = u8; +} +impl crate::IsEnum for Cmdprt {} +#[doc = "Field `CMDPRT` reader - Command protection level"] +pub type CmdprtR = crate::FieldReader; +impl CmdprtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmdprt { + match self.bits { + 0 => Cmdprt::Cmdprt00, + 1 => Cmdprt::Cmdprt01, + 2 => Cmdprt::Cmdprt10, + 3 => Cmdprt::Cmdprt11, + _ => unreachable!(), + } + } + #[doc = "Secure, normal access"] + #[inline(always)] + pub fn is_cmdprt00(&self) -> bool { + *self == Cmdprt::Cmdprt00 + } + #[doc = "Secure, privileged access"] + #[inline(always)] + pub fn is_cmdprt01(&self) -> bool { + *self == Cmdprt::Cmdprt01 + } + #[doc = "Nonsecure, normal access"] + #[inline(always)] + pub fn is_cmdprt10(&self) -> bool { + *self == Cmdprt::Cmdprt10 + } + #[doc = "Nonsecure, privileged access"] + #[inline(always)] + pub fn is_cmdprt11(&self) -> bool { + *self == Cmdprt::Cmdprt11 + } +} +#[doc = "Command protection status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmdp { + #[doc = "0: Command protection level and domain ID are stale"] + Cmdp0 = 0, + #[doc = "1: Command protection level (CMDPRT) and domain ID (CMDDID) are set"] + Cmdp1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmdp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMDP` reader - Command protection status flag"] +pub type CmdpR = crate::BitReader; +impl CmdpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmdp { + match self.bits { + false => Cmdp::Cmdp0, + true => Cmdp::Cmdp1, + } + } + #[doc = "Command protection level and domain ID are stale"] + #[inline(always)] + pub fn is_cmdp0(&self) -> bool { + *self == Cmdp::Cmdp0 + } + #[doc = "Command protection level (CMDPRT) and domain ID (CMDDID) are set"] + #[inline(always)] + pub fn is_cmdp1(&self) -> bool { + *self == Cmdp::Cmdp1 + } +} +#[doc = "Field `CMDDID` reader - Command domain ID"] +pub type CmddidR = crate::FieldReader; +#[doc = "Double Bit Fault Detect Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dfdif { + #[doc = "0: Double bit fault not detected during a valid flash read access"] + Dfdif0 = 0, + #[doc = "1: Double bit fault detected (or FCTRL\\[FDFD\\] is set) during a valid flash read access"] + Dfdif1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dfdif) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DFDIF` reader - Double Bit Fault Detect Interrupt Flag"] +pub type DfdifR = crate::BitReader; +impl DfdifR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dfdif { + match self.bits { + false => Dfdif::Dfdif0, + true => Dfdif::Dfdif1, + } + } + #[doc = "Double bit fault not detected during a valid flash read access"] + #[inline(always)] + pub fn is_dfdif0(&self) -> bool { + *self == Dfdif::Dfdif0 + } + #[doc = "Double bit fault detected (or FCTRL\\[FDFD\\] is set) during a valid flash read access"] + #[inline(always)] + pub fn is_dfdif1(&self) -> bool { + *self == Dfdif::Dfdif1 + } +} +#[doc = "Field `DFDIF` writer - Double Bit Fault Detect Interrupt Flag"] +pub type DfdifW<'a, REG> = crate::BitWriter1C<'a, REG, Dfdif>; +impl<'a, REG> DfdifW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Double bit fault not detected during a valid flash read access"] + #[inline(always)] + pub fn dfdif0(self) -> &'a mut crate::W { + self.variant(Dfdif::Dfdif0) + } + #[doc = "Double bit fault detected (or FCTRL\\[FDFD\\] is set) during a valid flash read access"] + #[inline(always)] + pub fn dfdif1(self) -> &'a mut crate::W { + self.variant(Dfdif::Dfdif1) + } +} +#[doc = "Salvage Used for Erase operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SalvUsed { + #[doc = "0: Salvage not used during last operation"] + SalvUsed0 = 0, + #[doc = "1: Salvage used during the last erase operation"] + SalvUsed1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SalvUsed) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SALV_USED` reader - Salvage Used for Erase operation"] +pub type SalvUsedR = crate::BitReader; +impl SalvUsedR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SalvUsed { + match self.bits { + false => SalvUsed::SalvUsed0, + true => SalvUsed::SalvUsed1, + } + } + #[doc = "Salvage not used during last operation"] + #[inline(always)] + pub fn is_salv_used0(&self) -> bool { + *self == SalvUsed::SalvUsed0 + } + #[doc = "Salvage used during the last erase operation"] + #[inline(always)] + pub fn is_salv_used1(&self) -> bool { + *self == SalvUsed::SalvUsed1 + } +} +#[doc = "Program-Erase Write Enable Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pewen { + #[doc = "0: Writes are not enabled"] + Pewen00 = 0, + #[doc = "1: Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)"] + Pewen01 = 1, + #[doc = "2: Writes are enabled for one flash or IFR page (page programming)"] + Pewen10 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pewen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pewen { + type Ux = u8; +} +impl crate::IsEnum for Pewen {} +#[doc = "Field `PEWEN` reader - Program-Erase Write Enable Control"] +pub type PewenR = crate::FieldReader; +impl PewenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Pewen::Pewen00), + 1 => Some(Pewen::Pewen01), + 2 => Some(Pewen::Pewen10), + _ => None, + } + } + #[doc = "Writes are not enabled"] + #[inline(always)] + pub fn is_pewen00(&self) -> bool { + *self == Pewen::Pewen00 + } + #[doc = "Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)"] + #[inline(always)] + pub fn is_pewen01(&self) -> bool { + *self == Pewen::Pewen01 + } + #[doc = "Writes are enabled for one flash or IFR page (page programming)"] + #[inline(always)] + pub fn is_pewen10(&self) -> bool { + *self == Pewen::Pewen10 + } +} +#[doc = "Program-Erase Ready Control/Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Perdy { + #[doc = "0: Program or sector erase command operation not stalled"] + Perdy0 = 0, + #[doc = "1: Program or sector erase command operation ready to execute"] + Perdy1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Perdy) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PERDY` reader - Program-Erase Ready Control/Status Flag"] +pub type PerdyR = crate::BitReader; +impl PerdyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Perdy { + match self.bits { + false => Perdy::Perdy0, + true => Perdy::Perdy1, + } + } + #[doc = "Program or sector erase command operation not stalled"] + #[inline(always)] + pub fn is_perdy0(&self) -> bool { + *self == Perdy::Perdy0 + } + #[doc = "Program or sector erase command operation ready to execute"] + #[inline(always)] + pub fn is_perdy1(&self) -> bool { + *self == Perdy::Perdy1 + } +} +#[doc = "Field `PERDY` writer - Program-Erase Ready Control/Status Flag"] +pub type PerdyW<'a, REG> = crate::BitWriter1C<'a, REG, Perdy>; +impl<'a, REG> PerdyW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Program or sector erase command operation not stalled"] + #[inline(always)] + pub fn perdy0(self) -> &'a mut crate::W { + self.variant(Perdy::Perdy0) + } + #[doc = "Program or sector erase command operation ready to execute"] + #[inline(always)] + pub fn perdy1(self) -> &'a mut crate::W { + self.variant(Perdy::Perdy1) + } +} +impl R { + #[doc = "Bit 0 - Command Fail Flag"] + #[inline(always)] + pub fn fail(&self) -> FailR { + FailR::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - Command Abort Flag"] + #[inline(always)] + pub fn cmdabt(&self) -> CmdabtR { + CmdabtR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Command Protection Violation Flag"] + #[inline(always)] + pub fn pviol(&self) -> PviolR { + PviolR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Command Access Error Flag"] + #[inline(always)] + pub fn accerr(&self) -> AccerrR { + AccerrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Command Write Sequence Abort Flag"] + #[inline(always)] + pub fn cwsabt(&self) -> CwsabtR { + CwsabtR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Command Complete Interrupt Flag"] + #[inline(always)] + pub fn ccif(&self) -> CcifR { + CcifR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Command protection level"] + #[inline(always)] + pub fn cmdprt(&self) -> CmdprtR { + CmdprtR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 11 - Command protection status flag"] + #[inline(always)] + pub fn cmdp(&self) -> CmdpR { + CmdpR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - Command domain ID"] + #[inline(always)] + pub fn cmddid(&self) -> CmddidR { + CmddidR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Flag"] + #[inline(always)] + pub fn dfdif(&self) -> DfdifR { + DfdifR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Salvage Used for Erase operation"] + #[inline(always)] + pub fn salv_used(&self) -> SalvUsedR { + SalvUsedR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 24:25 - Program-Erase Write Enable Control"] + #[inline(always)] + pub fn pewen(&self) -> PewenR { + PewenR::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 31 - Program-Erase Ready Control/Status Flag"] + #[inline(always)] + pub fn perdy(&self) -> PerdyR { + PerdyR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Command Abort Flag"] + #[inline(always)] + pub fn cmdabt(&mut self) -> CmdabtW { + CmdabtW::new(self, 2) + } + #[doc = "Bit 4 - Command Protection Violation Flag"] + #[inline(always)] + pub fn pviol(&mut self) -> PviolW { + PviolW::new(self, 4) + } + #[doc = "Bit 5 - Command Access Error Flag"] + #[inline(always)] + pub fn accerr(&mut self) -> AccerrW { + AccerrW::new(self, 5) + } + #[doc = "Bit 6 - Command Write Sequence Abort Flag"] + #[inline(always)] + pub fn cwsabt(&mut self) -> CwsabtW { + CwsabtW::new(self, 6) + } + #[doc = "Bit 7 - Command Complete Interrupt Flag"] + #[inline(always)] + pub fn ccif(&mut self) -> CcifW { + CcifW::new(self, 7) + } + #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Flag"] + #[inline(always)] + pub fn dfdif(&mut self) -> DfdifW { + DfdifW::new(self, 16) + } + #[doc = "Bit 31 - Program-Erase Ready Control/Status Flag"] + #[inline(always)] + pub fn perdy(&mut self) -> PerdyW { + PerdyW::new(self, 31) + } +} +#[doc = "Flash Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FstatSpec; +impl crate::RegisterSpec for FstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fstat::R`](R) reader structure"] +impl crate::Readable for FstatSpec {} +#[doc = "`write(|w| ..)` method takes [`fstat::W`](W) writer structure"] +impl crate::Writable for FstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8001_00f4; +} +#[doc = "`reset()` method sets FSTAT to value 0x80"] +impl crate::Resettable for FstatSpec { + const RESET_VALUE: u32 = 0x80; +} diff --git a/mcxa276-pac/src/freqme0.rs b/mcxa276-pac/src/freqme0.rs new file mode 100644 index 000000000..4f6ccd5be --- /dev/null +++ b/mcxa276-pac/src/freqme0.rs @@ -0,0 +1,60 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved_0_read_mode_ctrl_r: [u8; 0x04], + ctrlstat: Ctrlstat, + min: Min, + max: Max, +} +impl RegisterBlock { + #[doc = "0x00 - Control (in Write mode)"] + #[inline(always)] + pub const fn write_mode_ctrl_w(&self) -> &WriteModeCtrlW { + unsafe { &*core::ptr::from_ref(self).cast::().cast() } + } + #[doc = "0x00 - Control (in Read mode)"] + #[inline(always)] + pub const fn read_mode_ctrl_r(&self) -> &ReadModeCtrlR { + unsafe { &*core::ptr::from_ref(self).cast::().cast() } + } + #[doc = "0x04 - Control Status"] + #[inline(always)] + pub const fn ctrlstat(&self) -> &Ctrlstat { + &self.ctrlstat + } + #[doc = "0x08 - Minimum"] + #[inline(always)] + pub const fn min(&self) -> &Min { + &self.min + } + #[doc = "0x0c - Maximum"] + #[inline(always)] + pub const fn max(&self) -> &Max { + &self.max + } +} +#[doc = "READ_MODE_CTRL_R (r) register accessor: Control (in Read mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`read_mode_ctrl_r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read_mode_ctrl_r`] module"] +#[doc(alias = "READ_MODE_CTRL_R")] +pub type ReadModeCtrlR = crate::Reg; +#[doc = "Control (in Read mode)"] +pub mod read_mode_ctrl_r; +#[doc = "WRITE_MODE_CTRL_W (w) register accessor: Control (in Write mode)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_mode_ctrl_w::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@write_mode_ctrl_w`] module"] +#[doc(alias = "WRITE_MODE_CTRL_W")] +pub type WriteModeCtrlW = crate::Reg; +#[doc = "Control (in Write mode)"] +pub mod write_mode_ctrl_w; +#[doc = "CTRLSTAT (rw) register accessor: Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrlstat`] module"] +#[doc(alias = "CTRLSTAT")] +pub type Ctrlstat = crate::Reg; +#[doc = "Control Status"] +pub mod ctrlstat; +#[doc = "MIN (rw) register accessor: Minimum\n\nYou can [`read`](crate::Reg::read) this register and get [`min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@min`] module"] +#[doc(alias = "MIN")] +pub type Min = crate::Reg; +#[doc = "Minimum"] +pub mod min; +#[doc = "MAX (rw) register accessor: Maximum\n\nYou can [`read`](crate::Reg::read) this register and get [`max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max`] module"] +#[doc(alias = "MAX")] +pub type Max = crate::Reg; +#[doc = "Maximum"] +pub mod max; diff --git a/mcxa276-pac/src/freqme0/ctrlstat.rs b/mcxa276-pac/src/freqme0/ctrlstat.rs new file mode 100644 index 000000000..2e3bb461d --- /dev/null +++ b/mcxa276-pac/src/freqme0/ctrlstat.rs @@ -0,0 +1,505 @@ +#[doc = "Register `CTRLSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `CTRLSTAT` writer"] +pub type W = crate::W; +#[doc = "Field `REF_SCALE` reader - Reference Scale"] +pub type RefScaleR = crate::FieldReader; +#[doc = "Pulse Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PulseMode { + #[doc = "0: Frequency Measurement mode"] + Freq = 0, + #[doc = "1: Pulse Width Measurement mode"] + Pulse = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PulseMode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PULSE_MODE` reader - Pulse Mode"] +pub type PulseModeR = crate::BitReader; +impl PulseModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PulseMode { + match self.bits { + false => PulseMode::Freq, + true => PulseMode::Pulse, + } + } + #[doc = "Frequency Measurement mode"] + #[inline(always)] + pub fn is_freq(&self) -> bool { + *self == PulseMode::Freq + } + #[doc = "Pulse Width Measurement mode"] + #[inline(always)] + pub fn is_pulse(&self) -> bool { + *self == PulseMode::Pulse + } +} +#[doc = "Pulse Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PulsePol { + #[doc = "0: High period"] + High = 0, + #[doc = "1: Low period"] + Low = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PulsePol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PULSE_POL` reader - Pulse Polarity"] +pub type PulsePolR = crate::BitReader; +impl PulsePolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PulsePol { + match self.bits { + false => PulsePol::High, + true => PulsePol::Low, + } + } + #[doc = "High period"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == PulsePol::High + } + #[doc = "Low period"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == PulsePol::Low + } +} +#[doc = "Less Than Minimum Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LtMinIntEn { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LtMinIntEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LT_MIN_INT_EN` reader - Less Than Minimum Interrupt Enable"] +pub type LtMinIntEnR = crate::BitReader; +impl LtMinIntEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LtMinIntEn { + match self.bits { + false => LtMinIntEn::Disabled, + true => LtMinIntEn::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == LtMinIntEn::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == LtMinIntEn::Enabled + } +} +#[doc = "Greater Than Maximum Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GtMaxIntEn { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GtMaxIntEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GT_MAX_INT_EN` reader - Greater Than Maximum Interrupt Enable"] +pub type GtMaxIntEnR = crate::BitReader; +impl GtMaxIntEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> GtMaxIntEn { + match self.bits { + false => GtMaxIntEn::Disabled, + true => GtMaxIntEn::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == GtMaxIntEn::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == GtMaxIntEn::Enabled + } +} +#[doc = "Result Ready Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ResultReadyIntEn { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ResultReadyIntEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESULT_READY_INT_EN` reader - Result Ready Interrupt Enable"] +pub type ResultReadyIntEnR = crate::BitReader; +impl ResultReadyIntEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ResultReadyIntEn { + match self.bits { + false => ResultReadyIntEn::Disabled, + true => ResultReadyIntEn::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ResultReadyIntEn::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ResultReadyIntEn::Enabled + } +} +#[doc = "Less Than Minimum Results Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LtMinStat { + #[doc = "0: Greater than MIN\\[MIN_VALUE\\]"] + InRange = 0, + #[doc = "1: Less than MIN\\[MIN_VALUE\\]"] + LtMin = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LtMinStat) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LT_MIN_STAT` reader - Less Than Minimum Results Status"] +pub type LtMinStatR = crate::BitReader; +impl LtMinStatR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LtMinStat { + match self.bits { + false => LtMinStat::InRange, + true => LtMinStat::LtMin, + } + } + #[doc = "Greater than MIN\\[MIN_VALUE\\]"] + #[inline(always)] + pub fn is_in_range(&self) -> bool { + *self == LtMinStat::InRange + } + #[doc = "Less than MIN\\[MIN_VALUE\\]"] + #[inline(always)] + pub fn is_lt_min(&self) -> bool { + *self == LtMinStat::LtMin + } +} +#[doc = "Field `LT_MIN_STAT` writer - Less Than Minimum Results Status"] +pub type LtMinStatW<'a, REG> = crate::BitWriter1C<'a, REG, LtMinStat>; +impl<'a, REG> LtMinStatW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Greater than MIN\\[MIN_VALUE\\]"] + #[inline(always)] + pub fn in_range(self) -> &'a mut crate::W { + self.variant(LtMinStat::InRange) + } + #[doc = "Less than MIN\\[MIN_VALUE\\]"] + #[inline(always)] + pub fn lt_min(self) -> &'a mut crate::W { + self.variant(LtMinStat::LtMin) + } +} +#[doc = "Greater Than Maximum Result Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GtMaxStat { + #[doc = "0: Less than MAX\\[MAX_VALUE\\]"] + InRange = 0, + #[doc = "1: Greater than MAX\\[MAX_VALUE\\]"] + GtMax = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GtMaxStat) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GT_MAX_STAT` reader - Greater Than Maximum Result Status"] +pub type GtMaxStatR = crate::BitReader; +impl GtMaxStatR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> GtMaxStat { + match self.bits { + false => GtMaxStat::InRange, + true => GtMaxStat::GtMax, + } + } + #[doc = "Less than MAX\\[MAX_VALUE\\]"] + #[inline(always)] + pub fn is_in_range(&self) -> bool { + *self == GtMaxStat::InRange + } + #[doc = "Greater than MAX\\[MAX_VALUE\\]"] + #[inline(always)] + pub fn is_gt_max(&self) -> bool { + *self == GtMaxStat::GtMax + } +} +#[doc = "Field `GT_MAX_STAT` writer - Greater Than Maximum Result Status"] +pub type GtMaxStatW<'a, REG> = crate::BitWriter1C<'a, REG, GtMaxStat>; +impl<'a, REG> GtMaxStatW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Less than MAX\\[MAX_VALUE\\]"] + #[inline(always)] + pub fn in_range(self) -> &'a mut crate::W { + self.variant(GtMaxStat::InRange) + } + #[doc = "Greater than MAX\\[MAX_VALUE\\]"] + #[inline(always)] + pub fn gt_max(self) -> &'a mut crate::W { + self.variant(GtMaxStat::GtMax) + } +} +#[doc = "Result Ready Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ResultReadyStat { + #[doc = "0: Not complete"] + NotComplete = 0, + #[doc = "1: Complete"] + Complete = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ResultReadyStat) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESULT_READY_STAT` reader - Result Ready Status"] +pub type ResultReadyStatR = crate::BitReader; +impl ResultReadyStatR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ResultReadyStat { + match self.bits { + false => ResultReadyStat::NotComplete, + true => ResultReadyStat::Complete, + } + } + #[doc = "Not complete"] + #[inline(always)] + pub fn is_not_complete(&self) -> bool { + *self == ResultReadyStat::NotComplete + } + #[doc = "Complete"] + #[inline(always)] + pub fn is_complete(&self) -> bool { + *self == ResultReadyStat::Complete + } +} +#[doc = "Field `RESULT_READY_STAT` writer - Result Ready Status"] +pub type ResultReadyStatW<'a, REG> = crate::BitWriter1C<'a, REG, ResultReadyStat>; +impl<'a, REG> ResultReadyStatW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not complete"] + #[inline(always)] + pub fn not_complete(self) -> &'a mut crate::W { + self.variant(ResultReadyStat::NotComplete) + } + #[doc = "Complete"] + #[inline(always)] + pub fn complete(self) -> &'a mut crate::W { + self.variant(ResultReadyStat::Complete) + } +} +#[doc = "Continuous Mode Enable Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ContinuousModeEn { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ContinuousModeEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CONTINUOUS_MODE_EN` reader - Continuous Mode Enable Status"] +pub type ContinuousModeEnR = crate::BitReader; +impl ContinuousModeEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ContinuousModeEn { + match self.bits { + false => ContinuousModeEn::Disabled, + true => ContinuousModeEn::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ContinuousModeEn::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ContinuousModeEn::Enabled + } +} +#[doc = "Measurement in Progress Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MeasureInProgress { + #[doc = "0: Not in progress"] + Idle = 0, + #[doc = "1: In progress"] + Ongoing = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MeasureInProgress) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MEASURE_IN_PROGRESS` reader - Measurement in Progress Status"] +pub type MeasureInProgressR = crate::BitReader; +impl MeasureInProgressR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MeasureInProgress { + match self.bits { + false => MeasureInProgress::Idle, + true => MeasureInProgress::Ongoing, + } + } + #[doc = "Not in progress"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == MeasureInProgress::Idle + } + #[doc = "In progress"] + #[inline(always)] + pub fn is_ongoing(&self) -> bool { + *self == MeasureInProgress::Ongoing + } +} +impl R { + #[doc = "Bits 0:4 - Reference Scale"] + #[inline(always)] + pub fn ref_scale(&self) -> RefScaleR { + RefScaleR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 8 - Pulse Mode"] + #[inline(always)] + pub fn pulse_mode(&self) -> PulseModeR { + PulseModeR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pulse Polarity"] + #[inline(always)] + pub fn pulse_pol(&self) -> PulsePolR { + PulsePolR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Less Than Minimum Interrupt Enable"] + #[inline(always)] + pub fn lt_min_int_en(&self) -> LtMinIntEnR { + LtMinIntEnR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Greater Than Maximum Interrupt Enable"] + #[inline(always)] + pub fn gt_max_int_en(&self) -> GtMaxIntEnR { + GtMaxIntEnR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn result_ready_int_en(&self) -> ResultReadyIntEnR { + ResultReadyIntEnR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 24 - Less Than Minimum Results Status"] + #[inline(always)] + pub fn lt_min_stat(&self) -> LtMinStatR { + LtMinStatR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Greater Than Maximum Result Status"] + #[inline(always)] + pub fn gt_max_stat(&self) -> GtMaxStatR { + GtMaxStatR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Result Ready Status"] + #[inline(always)] + pub fn result_ready_stat(&self) -> ResultReadyStatR { + ResultReadyStatR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - Continuous Mode Enable Status"] + #[inline(always)] + pub fn continuous_mode_en(&self) -> ContinuousModeEnR { + ContinuousModeEnR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Measurement in Progress Status"] + #[inline(always)] + pub fn measure_in_progress(&self) -> MeasureInProgressR { + MeasureInProgressR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 24 - Less Than Minimum Results Status"] + #[inline(always)] + pub fn lt_min_stat(&mut self) -> LtMinStatW { + LtMinStatW::new(self, 24) + } + #[doc = "Bit 25 - Greater Than Maximum Result Status"] + #[inline(always)] + pub fn gt_max_stat(&mut self) -> GtMaxStatW { + GtMaxStatW::new(self, 25) + } + #[doc = "Bit 26 - Result Ready Status"] + #[inline(always)] + pub fn result_ready_stat(&mut self) -> ResultReadyStatW { + ResultReadyStatW::new(self, 26) + } +} +#[doc = "Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlstatSpec; +impl crate::RegisterSpec for CtrlstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrlstat::R`](R) reader structure"] +impl crate::Readable for CtrlstatSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrlstat::W`](W) writer structure"] +impl crate::Writable for CtrlstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0700_0000; +} +#[doc = "`reset()` method sets CTRLSTAT to value 0"] +impl crate::Resettable for CtrlstatSpec {} diff --git a/mcxa276-pac/src/freqme0/max.rs b/mcxa276-pac/src/freqme0/max.rs new file mode 100644 index 000000000..ed470581a --- /dev/null +++ b/mcxa276-pac/src/freqme0/max.rs @@ -0,0 +1,37 @@ +#[doc = "Register `MAX` reader"] +pub type R = crate::R; +#[doc = "Register `MAX` writer"] +pub type W = crate::W; +#[doc = "Field `MAX_VALUE` reader - Maximum Value"] +pub type MaxValueR = crate::FieldReader; +#[doc = "Field `MAX_VALUE` writer - Maximum Value"] +pub type MaxValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +impl R { + #[doc = "Bits 0:30 - Maximum Value"] + #[inline(always)] + pub fn max_value(&self) -> MaxValueR { + MaxValueR::new(self.bits & 0x7fff_ffff) + } +} +impl W { + #[doc = "Bits 0:30 - Maximum Value"] + #[inline(always)] + pub fn max_value(&mut self) -> MaxValueW { + MaxValueW::new(self, 0) + } +} +#[doc = "Maximum\n\nYou can [`read`](crate::Reg::read) this register and get [`max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MaxSpec; +impl crate::RegisterSpec for MaxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`max::R`](R) reader structure"] +impl crate::Readable for MaxSpec {} +#[doc = "`write(|w| ..)` method takes [`max::W`](W) writer structure"] +impl crate::Writable for MaxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAX to value 0x7fff_ffff"] +impl crate::Resettable for MaxSpec { + const RESET_VALUE: u32 = 0x7fff_ffff; +} diff --git a/mcxa276-pac/src/freqme0/min.rs b/mcxa276-pac/src/freqme0/min.rs new file mode 100644 index 000000000..622bd623b --- /dev/null +++ b/mcxa276-pac/src/freqme0/min.rs @@ -0,0 +1,35 @@ +#[doc = "Register `MIN` reader"] +pub type R = crate::R; +#[doc = "Register `MIN` writer"] +pub type W = crate::W; +#[doc = "Field `MIN_VALUE` reader - Minimum Value"] +pub type MinValueR = crate::FieldReader; +#[doc = "Field `MIN_VALUE` writer - Minimum Value"] +pub type MinValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +impl R { + #[doc = "Bits 0:30 - Minimum Value"] + #[inline(always)] + pub fn min_value(&self) -> MinValueR { + MinValueR::new(self.bits & 0x7fff_ffff) + } +} +impl W { + #[doc = "Bits 0:30 - Minimum Value"] + #[inline(always)] + pub fn min_value(&mut self) -> MinValueW { + MinValueW::new(self, 0) + } +} +#[doc = "Minimum\n\nYou can [`read`](crate::Reg::read) this register and get [`min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MinSpec; +impl crate::RegisterSpec for MinSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`min::R`](R) reader structure"] +impl crate::Readable for MinSpec {} +#[doc = "`write(|w| ..)` method takes [`min::W`](W) writer structure"] +impl crate::Writable for MinSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MIN to value 0"] +impl crate::Resettable for MinSpec {} diff --git a/mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs b/mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs new file mode 100644 index 000000000..b70744109 --- /dev/null +++ b/mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs @@ -0,0 +1,61 @@ +#[doc = "Register `CTRL_R` reader"] +pub type R = crate::R; +#[doc = "Field `RESULT` reader - Indicates the measurement result-either the target clock counter value (for Frequency Measurement mode) or pulse width measurement (for Pulse Width Measurement mode)"] +pub type ResultR = crate::FieldReader; +#[doc = "Measurement In Progress\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MeasureInProgress { + #[doc = "0: Complete"] + CycleDone = 0, + #[doc = "1: In progress"] + InProgress = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MeasureInProgress) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MEASURE_IN_PROGRESS` reader - Measurement In Progress"] +pub type MeasureInProgressR = crate::BitReader; +impl MeasureInProgressR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MeasureInProgress { + match self.bits { + false => MeasureInProgress::CycleDone, + true => MeasureInProgress::InProgress, + } + } + #[doc = "Complete"] + #[inline(always)] + pub fn is_cycle_done(&self) -> bool { + *self == MeasureInProgress::CycleDone + } + #[doc = "In progress"] + #[inline(always)] + pub fn is_in_progress(&self) -> bool { + *self == MeasureInProgress::InProgress + } +} +impl R { + #[doc = "Bits 0:30 - Indicates the measurement result-either the target clock counter value (for Frequency Measurement mode) or pulse width measurement (for Pulse Width Measurement mode)"] + #[inline(always)] + pub fn result(&self) -> ResultR { + ResultR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Measurement In Progress"] + #[inline(always)] + pub fn measure_in_progress(&self) -> MeasureInProgressR { + MeasureInProgressR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Control (in Read mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`read_mode_ctrl_r::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ReadModeCtrlRSpec; +impl crate::RegisterSpec for ReadModeCtrlRSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`read_mode_ctrl_r::R`](R) reader structure"] +impl crate::Readable for ReadModeCtrlRSpec {} +#[doc = "`reset()` method sets CTRL_R to value 0"] +impl crate::Resettable for ReadModeCtrlRSpec {} diff --git a/mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs b/mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs new file mode 100644 index 000000000..a9278342b --- /dev/null +++ b/mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs @@ -0,0 +1,274 @@ +#[doc = "Register `CTRL_W` writer"] +pub type W = crate::W; +#[doc = "Field `REF_SCALE` writer - Reference Clock Scaling Factor"] +pub type RefScaleW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Pulse Width Measurement Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PulseMode { + #[doc = "0: Frequency Measurement mode"] + FreqMeMode = 0, + #[doc = "1: Pulse Width Measurement mode"] + PulseMeMode = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PulseMode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PULSE_MODE` writer - Pulse Width Measurement Mode Select"] +pub type PulseModeW<'a, REG> = crate::BitWriter<'a, REG, PulseMode>; +impl<'a, REG> PulseModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Frequency Measurement mode"] + #[inline(always)] + pub fn freq_me_mode(self) -> &'a mut crate::W { + self.variant(PulseMode::FreqMeMode) + } + #[doc = "Pulse Width Measurement mode"] + #[inline(always)] + pub fn pulse_me_mode(self) -> &'a mut crate::W { + self.variant(PulseMode::PulseMeMode) + } +} +#[doc = "Pulse Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PulsePol { + #[doc = "0: High period"] + HighPeriod = 0, + #[doc = "1: Low period"] + LowPeriod = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PulsePol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PULSE_POL` writer - Pulse Polarity"] +pub type PulsePolW<'a, REG> = crate::BitWriter<'a, REG, PulsePol>; +impl<'a, REG> PulsePolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "High period"] + #[inline(always)] + pub fn high_period(self) -> &'a mut crate::W { + self.variant(PulsePol::HighPeriod) + } + #[doc = "Low period"] + #[inline(always)] + pub fn low_period(self) -> &'a mut crate::W { + self.variant(PulsePol::LowPeriod) + } +} +#[doc = "Less Than Minimum Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LtMinIntEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LtMinIntEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LT_MIN_INT_EN` writer - Less Than Minimum Interrupt Enable"] +pub type LtMinIntEnW<'a, REG> = crate::BitWriter<'a, REG, LtMinIntEn>; +impl<'a, REG> LtMinIntEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(LtMinIntEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(LtMinIntEn::Enable) + } +} +#[doc = "Greater Than Maximum Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GtMaxIntEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GtMaxIntEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GT_MAX_INT_EN` writer - Greater Than Maximum Interrupt Enable"] +pub type GtMaxIntEnW<'a, REG> = crate::BitWriter<'a, REG, GtMaxIntEn>; +impl<'a, REG> GtMaxIntEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(GtMaxIntEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(GtMaxIntEn::Enable) + } +} +#[doc = "Result Ready Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ResultReadyIntEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ResultReadyIntEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESULT_READY_INT_EN` writer - Result Ready Interrupt Enable"] +pub type ResultReadyIntEnW<'a, REG> = crate::BitWriter<'a, REG, ResultReadyIntEn>; +impl<'a, REG> ResultReadyIntEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ResultReadyIntEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ResultReadyIntEn::Enable) + } +} +#[doc = "Continuous Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ContinuousModeEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ContinuousModeEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CONTINUOUS_MODE_EN` writer - Continuous Mode Enable"] +pub type ContinuousModeEnW<'a, REG> = crate::BitWriter<'a, REG, ContinuousModeEn>; +impl<'a, REG> ContinuousModeEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ContinuousModeEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ContinuousModeEn::Enable) + } +} +#[doc = "Measurement In Progress\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MeasureInProgress { + #[doc = "0: Terminates measurement"] + ForceTerminate = 0, + #[doc = "1: Initiates measurement"] + InitiateAFreqmeCycle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MeasureInProgress) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MEASURE_IN_PROGRESS` writer - Measurement In Progress"] +pub type MeasureInProgressW<'a, REG> = crate::BitWriter<'a, REG, MeasureInProgress>; +impl<'a, REG> MeasureInProgressW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Terminates measurement"] + #[inline(always)] + pub fn force_terminate(self) -> &'a mut crate::W { + self.variant(MeasureInProgress::ForceTerminate) + } + #[doc = "Initiates measurement"] + #[inline(always)] + pub fn initiate_a_freqme_cycle(self) -> &'a mut crate::W { + self.variant(MeasureInProgress::InitiateAFreqmeCycle) + } +} +impl W { + #[doc = "Bits 0:4 - Reference Clock Scaling Factor"] + #[inline(always)] + pub fn ref_scale(&mut self) -> RefScaleW { + RefScaleW::new(self, 0) + } + #[doc = "Bit 8 - Pulse Width Measurement Mode Select"] + #[inline(always)] + pub fn pulse_mode(&mut self) -> PulseModeW { + PulseModeW::new(self, 8) + } + #[doc = "Bit 9 - Pulse Polarity"] + #[inline(always)] + pub fn pulse_pol(&mut self) -> PulsePolW { + PulsePolW::new(self, 9) + } + #[doc = "Bit 12 - Less Than Minimum Interrupt Enable"] + #[inline(always)] + pub fn lt_min_int_en(&mut self) -> LtMinIntEnW { + LtMinIntEnW::new(self, 12) + } + #[doc = "Bit 13 - Greater Than Maximum Interrupt Enable"] + #[inline(always)] + pub fn gt_max_int_en(&mut self) -> GtMaxIntEnW { + GtMaxIntEnW::new(self, 13) + } + #[doc = "Bit 14 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn result_ready_int_en(&mut self) -> ResultReadyIntEnW { + ResultReadyIntEnW::new(self, 14) + } + #[doc = "Bit 30 - Continuous Mode Enable"] + #[inline(always)] + pub fn continuous_mode_en(&mut self) -> ContinuousModeEnW { + ContinuousModeEnW::new(self, 30) + } + #[doc = "Bit 31 - Measurement In Progress"] + #[inline(always)] + pub fn measure_in_progress(&mut self) -> MeasureInProgressW { + MeasureInProgressW::new(self, 31) + } +} +#[doc = "Control (in Write mode)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_mode_ctrl_w::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WriteModeCtrlWSpec; +impl crate::RegisterSpec for WriteModeCtrlWSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`write_mode_ctrl_w::W`](W) writer structure"] +impl crate::Writable for WriteModeCtrlWSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL_W to value 0"] +impl crate::Resettable for WriteModeCtrlWSpec {} diff --git a/mcxa276-pac/src/generic.rs b/mcxa276-pac/src/generic.rs new file mode 100644 index 000000000..1bb995a4e --- /dev/null +++ b/mcxa276-pac/src/generic.rs @@ -0,0 +1,768 @@ +use core::marker; +#[doc = " Generic peripheral accessor"] +pub struct Periph { + _marker: marker::PhantomData, +} +unsafe impl Send for Periph {} +impl Periph { + #[doc = "Pointer to the register block"] + pub const PTR: *const RB = A as *const _; + #[doc = "Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const RB { + Self::PTR + } + #[doc = " Steal an instance of this peripheral"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = " that may race with any existing instances, for example by only"] + #[doc = " accessing read-only or write-only registers, or by consuming the"] + #[doc = " original peripheral and using critical sections to coordinate"] + #[doc = " access between multiple new instances."] + #[doc = ""] + #[doc = " Additionally, other software such as HALs may rely on only one"] + #[doc = " peripheral instance existing to ensure memory safety; ensure"] + #[doc = " no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: marker::PhantomData, + } + } +} +impl core::ops::Deref for Periph { + type Target = RB; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " `0`"] + const ZERO: Self; + #[doc = " `1`"] + const ONE: Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + const ZERO: Self = 0; + const ONE: Self = 1; + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + impl FieldSpec for $U { + type Ux = $U; + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + core::fmt::Debug + PartialEq + From; +} +#[doc = " Marker for fields with fixed values"] +pub trait IsEnum: FieldSpec {} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec {} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Is it safe to write any bits to register"] + type Safety; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux = Self::Ux::ZERO; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc(hidden)] +pub mod raw; +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub type R = raw::R; +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub const fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub type W = raw::W; +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +impl W +where + REG: Writable, +{ + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub fn set(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = raw::FieldReader; +#[doc = " Bit-wise field reader"] +pub type BitReader = raw::BitReader; +impl FieldReader { + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub const fn bits(&self) -> FI::Ux { + self.bits + } +} +impl core::fmt::Debug for FieldReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +impl PartialEq for FieldReader +where + FI: FieldSpec + Copy, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&FI::Ux::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub const fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub const fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub const fn bit_is_set(&self) -> bool { + self.bit() + } +} +impl core::fmt::Debug for BitReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +#[doc = " Marker for register/field writers which can take any value of specified width"] +pub struct Safe; +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] +pub struct Unsafe; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct Range; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeFrom; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeTo; +#[doc = " Write field Proxy"] +pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = + raw::FieldWriter<'a, REG, WI, FI, Safety>; +impl FieldWriter<'_, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } +} +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> + FieldWriter<'a, REG, WI, FI, Range> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN && value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: IsEnum, + REG::Ux: From, +{ + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, REG, FI> BitWriter<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) -> REG::Ux + where + F: FnOnce(&mut W) -> &mut W, + { + let value = f(&mut W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }) + .bits; + self.register.set(value); + value + } + #[doc = " Writes bits to a `Writable` register and produce a value."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| {"] + #[doc = " w.field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[doc = ""] + #[doc = " Values can be returned from the closure:"] + #[doc = " ```ignore"] + #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"] + #[doc = " ```"] + #[inline(always)] + pub fn from_write(&self, f: F) -> T + where + F: FnOnce(&mut W) -> T, + { + let mut writer = W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }; + let result = f(&mut writer); + self.register.set(writer.bits); + result + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) -> REG::Ux + where + F: FnOnce(&mut W) -> &mut W, + { + let value = f(&mut W { + bits: REG::Ux::ZERO, + _reg: marker::PhantomData, + }) + .bits; + self.register.set(value); + value + } + #[doc = " Writes 0 to a `Writable` register and produces a value."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn from_write_with_zero(&self, f: F) -> T + where + F: FnOnce(&mut W) -> T, + { + let mut writer = W { + bits: REG::Ux::ZERO, + _reg: marker::PhantomData, + }; + let result = f(&mut writer); + self.register.set(writer.bits); + result + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) -> REG::Ux + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + let value = f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }, + ) + .bits; + self.register.set(value); + value + } + #[doc = " Modifies the contents of the register by reading and then writing it"] + #[doc = " and produces a value."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.modify(|r, w| {"] + #[doc = " let new_bits = r.bits() | 3;"] + #[doc = " unsafe {"] + #[doc = " w.bits(new_bits);"] + #[doc = " }"] + #[doc = ""] + #[doc = " new_bits"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn from_modify(&self, f: F) -> T + where + for<'w> F: FnOnce(&R, &'w mut W) -> T, + { + let bits = self.register.get(); + let mut writer = W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }; + let result = f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut writer, + ); + self.register.set(writer.bits); + result + } +} +impl core::fmt::Debug for crate::generic::Reg +where + R: core::fmt::Debug, +{ + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} diff --git a/mcxa276-pac/src/generic/raw.rs b/mcxa276-pac/src/generic/raw.rs new file mode 100644 index 000000000..d60a23a7c --- /dev/null +++ b/mcxa276-pac/src/generic/raw.rs @@ -0,0 +1,95 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[must_use = "after creating `FieldWriter` you need to call field value setting method"] +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +#[must_use = "after creating `BitWriter` you need to call bit setting method"] +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/mcxa276-pac/src/glikey0.rs b/mcxa276-pac/src/glikey0.rs new file mode 100644 index 000000000..02c444c32 --- /dev/null +++ b/mcxa276-pac/src/glikey0.rs @@ -0,0 +1,62 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl_0: Ctrl0, + ctrl_1: Ctrl1, + intr_ctrl: IntrCtrl, + status: Status, + _reserved4: [u8; 0xec], + version: Version, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register 0 SFR"] + #[inline(always)] + pub const fn ctrl_0(&self) -> &Ctrl0 { + &self.ctrl_0 + } + #[doc = "0x04 - Control Register 1 SFR"] + #[inline(always)] + pub const fn ctrl_1(&self) -> &Ctrl1 { + &self.ctrl_1 + } + #[doc = "0x08 - Interrupt Control"] + #[inline(always)] + pub const fn intr_ctrl(&self) -> &IntrCtrl { + &self.intr_ctrl + } + #[doc = "0x0c - Status"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0xfc - IP Version"] + #[inline(always)] + pub const fn version(&self) -> &Version { + &self.version + } +} +#[doc = "CTRL_0 (rw) register accessor: Control Register 0 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_0`] module"] +#[doc(alias = "CTRL_0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Control Register 0 SFR"] +pub mod ctrl_0; +#[doc = "CTRL_1 (rw) register accessor: Control Register 1 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_1`] module"] +#[doc(alias = "CTRL_1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Control Register 1 SFR"] +pub mod ctrl_1; +#[doc = "INTR_CTRL (rw) register accessor: Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_ctrl`] module"] +#[doc(alias = "INTR_CTRL")] +pub type IntrCtrl = crate::Reg; +#[doc = "Interrupt Control"] +pub mod intr_ctrl; +#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "VERSION (r) register accessor: IP Version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +#[doc(alias = "VERSION")] +pub type Version = crate::Reg; +#[doc = "IP Version"] +pub mod version; diff --git a/mcxa276-pac/src/glikey0/ctrl_0.rs b/mcxa276-pac/src/glikey0/ctrl_0.rs new file mode 100644 index 000000000..775c9c7cd --- /dev/null +++ b/mcxa276-pac/src/glikey0/ctrl_0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CTRL_0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL_0` writer"] +pub type W = crate::W; +#[doc = "Field `WRITE_INDEX` reader - Write Index"] +pub type WriteIndexR = crate::FieldReader; +#[doc = "Field `WRITE_INDEX` writer - Write Index"] +pub type WriteIndexW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RESERVED15` reader - Reserved for Future Use"] +pub type Reserved15R = crate::FieldReader; +#[doc = "Field `WR_EN_0` reader - Write Enable 0"] +pub type WrEn0R = crate::FieldReader; +#[doc = "Field `WR_EN_0` writer - Write Enable 0"] +pub type WrEn0W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SftRst { + #[doc = "0: No effect"] + Disable = 0, + #[doc = "1: Triggers the soft reset"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SftRst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SFT_RST` reader - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] +pub type SftRstR = crate::BitReader; +impl SftRstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SftRst { + match self.bits { + false => SftRst::Disable, + true => SftRst::Enable, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SftRst::Disable + } + #[doc = "Triggers the soft reset"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SftRst::Enable + } +} +#[doc = "Field `SFT_RST` writer - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] +pub type SftRstW<'a, REG> = crate::BitWriter<'a, REG, SftRst>; +impl<'a, REG> SftRstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SftRst::Disable) + } + #[doc = "Triggers the soft reset"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SftRst::Enable) + } +} +#[doc = "Field `RESERVED31` reader - Reserved for Future Use"] +pub type Reserved31R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Write Index"] + #[inline(always)] + pub fn write_index(&self) -> WriteIndexR { + WriteIndexR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved for Future Use"] + #[inline(always)] + pub fn reserved15(&self) -> Reserved15R { + Reserved15R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:17 - Write Enable 0"] + #[inline(always)] + pub fn wr_en_0(&self) -> WrEn0R { + WrEn0R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] + #[inline(always)] + pub fn sft_rst(&self) -> SftRstR { + SftRstR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:31 - Reserved for Future Use"] + #[inline(always)] + pub fn reserved31(&self) -> Reserved31R { + Reserved31R::new(((self.bits >> 19) & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:7 - Write Index"] + #[inline(always)] + pub fn write_index(&mut self) -> WriteIndexW { + WriteIndexW::new(self, 0) + } + #[doc = "Bits 16:17 - Write Enable 0"] + #[inline(always)] + pub fn wr_en_0(&mut self) -> WrEn0W { + WrEn0W::new(self, 16) + } + #[doc = "Bit 18 - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] + #[inline(always)] + pub fn sft_rst(&mut self) -> SftRstW { + SftRstW::new(self, 18) + } +} +#[doc = "Control Register 0 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl_0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl_0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL_0 to value 0x0002_0000"] +impl crate::Resettable for Ctrl0Spec { + const RESET_VALUE: u32 = 0x0002_0000; +} diff --git a/mcxa276-pac/src/glikey0/ctrl_1.rs b/mcxa276-pac/src/glikey0/ctrl_1.rs new file mode 100644 index 000000000..ad8c97531 --- /dev/null +++ b/mcxa276-pac/src/glikey0/ctrl_1.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CTRL_1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL_1` writer"] +pub type W = crate::W; +#[doc = "Field `READ_INDEX` reader - Index status, Writing an index value to this register will request the block to return the lock status of this index."] +pub type ReadIndexR = crate::FieldReader; +#[doc = "Field `READ_INDEX` writer - Index status, Writing an index value to this register will request the block to return the lock status of this index."] +pub type ReadIndexW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RESERVED15` reader - Reserved for Future Use"] +pub type Reserved15R = crate::FieldReader; +#[doc = "Field `WR_EN_1` reader - Write Enable One"] +pub type WrEn1R = crate::FieldReader; +#[doc = "Field `WR_EN_1` writer - Write Enable One"] +pub type WrEn1W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SFR_LOCK` reader - LOCK register for GLIKEY"] +pub type SfrLockR = crate::FieldReader; +#[doc = "Field `SFR_LOCK` writer - LOCK register for GLIKEY"] +pub type SfrLockW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RESERVED31` reader - Reserved for Future Use"] +pub type Reserved31R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Index status, Writing an index value to this register will request the block to return the lock status of this index."] + #[inline(always)] + pub fn read_index(&self) -> ReadIndexR { + ReadIndexR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved for Future Use"] + #[inline(always)] + pub fn reserved15(&self) -> Reserved15R { + Reserved15R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:17 - Write Enable One"] + #[inline(always)] + pub fn wr_en_1(&self) -> WrEn1R { + WrEn1R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:21 - LOCK register for GLIKEY"] + #[inline(always)] + pub fn sfr_lock(&self) -> SfrLockR { + SfrLockR::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 22:31 - Reserved for Future Use"] + #[inline(always)] + pub fn reserved31(&self) -> Reserved31R { + Reserved31R::new(((self.bits >> 22) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:7 - Index status, Writing an index value to this register will request the block to return the lock status of this index."] + #[inline(always)] + pub fn read_index(&mut self) -> ReadIndexW { + ReadIndexW::new(self, 0) + } + #[doc = "Bits 16:17 - Write Enable One"] + #[inline(always)] + pub fn wr_en_1(&mut self) -> WrEn1W { + WrEn1W::new(self, 16) + } + #[doc = "Bits 18:21 - LOCK register for GLIKEY"] + #[inline(always)] + pub fn sfr_lock(&mut self) -> SfrLockW { + SfrLockW::new(self, 18) + } +} +#[doc = "Control Register 1 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl_1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl_1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL_1 to value 0x0028_0000"] +impl crate::Resettable for Ctrl1Spec { + const RESET_VALUE: u32 = 0x0028_0000; +} diff --git a/mcxa276-pac/src/glikey0/intr_ctrl.rs b/mcxa276-pac/src/glikey0/intr_ctrl.rs new file mode 100644 index 000000000..e9648235c --- /dev/null +++ b/mcxa276-pac/src/glikey0/intr_ctrl.rs @@ -0,0 +1,119 @@ +#[doc = "Register `INTR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `INTR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `INT_EN` reader - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] +pub type IntEnR = crate::BitReader; +#[doc = "Field `INT_EN` writer - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] +pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INT_CLR` reader - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] +pub type IntClrR = crate::BitReader; +#[doc = "Field `INT_CLR` writer - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] +pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IntSet { + #[doc = "0: No effect"] + Disable = 0, + #[doc = "1: Triggers interrupt"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IntSet) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT_SET` reader - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] +pub type IntSetR = crate::BitReader; +impl IntSetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IntSet { + match self.bits { + false => IntSet::Disable, + true => IntSet::Enable, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IntSet::Disable + } + #[doc = "Triggers interrupt"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IntSet::Enable + } +} +#[doc = "Field `INT_SET` writer - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] +pub type IntSetW<'a, REG> = crate::BitWriter<'a, REG, IntSet>; +impl<'a, REG> IntSetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(IntSet::Disable) + } + #[doc = "Triggers interrupt"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(IntSet::Enable) + } +} +#[doc = "Field `RESERVED31` reader - Reserved for Future Use"] +pub type Reserved31R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] + #[inline(always)] + pub fn int_en(&self) -> IntEnR { + IntEnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] + #[inline(always)] + pub fn int_clr(&self) -> IntClrR { + IntClrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] + #[inline(always)] + pub fn int_set(&self) -> IntSetR { + IntSetR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:31 - Reserved for Future Use"] + #[inline(always)] + pub fn reserved31(&self) -> Reserved31R { + Reserved31R::new((self.bits >> 3) & 0x1fff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] + #[inline(always)] + pub fn int_en(&mut self) -> IntEnW { + IntEnW::new(self, 0) + } + #[doc = "Bit 1 - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] + #[inline(always)] + pub fn int_clr(&mut self) -> IntClrW { + IntClrW::new(self, 1) + } + #[doc = "Bit 2 - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] + #[inline(always)] + pub fn int_set(&mut self) -> IntSetW { + IntSetW::new(self, 2) + } +} +#[doc = "Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntrCtrlSpec; +impl crate::RegisterSpec for IntrCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_ctrl::R`](R) reader structure"] +impl crate::Readable for IntrCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`intr_ctrl::W`](W) writer structure"] +impl crate::Writable for IntrCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets INTR_CTRL to value 0"] +impl crate::Resettable for IntrCtrlSpec {} diff --git a/mcxa276-pac/src/glikey0/status.rs b/mcxa276-pac/src/glikey0/status.rs new file mode 100644 index 000000000..eae5bd127 --- /dev/null +++ b/mcxa276-pac/src/glikey0/status.rs @@ -0,0 +1,198 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Interrupt Status.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IntStatus { + #[doc = "0: No effect"] + Disable = 0, + #[doc = "1: Triggers interrupt"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IntStatus) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT_STATUS` reader - Interrupt Status."] +pub type IntStatusR = crate::BitReader; +impl IntStatusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IntStatus { + match self.bits { + false => IntStatus::Disable, + true => IntStatus::Enable, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IntStatus::Disable + } + #[doc = "Triggers interrupt"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IntStatus::Enable + } +} +#[doc = "Provides the current lock status of indexes.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LockStatus { + #[doc = "0: Current read index is not locked"] + Lock0 = 0, + #[doc = "1: Current read index is locked"] + Lock1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LockStatus) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK_STATUS` reader - Provides the current lock status of indexes."] +pub type LockStatusR = crate::BitReader; +impl LockStatusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LockStatus { + match self.bits { + false => LockStatus::Lock0, + true => LockStatus::Lock1, + } + } + #[doc = "Current read index is not locked"] + #[inline(always)] + pub fn is_lock0(&self) -> bool { + *self == LockStatus::Lock0 + } + #[doc = "Current read index is locked"] + #[inline(always)] + pub fn is_lock1(&self) -> bool { + *self == LockStatus::Lock1 + } +} +#[doc = "Status of the Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ErrorStatus { + #[doc = "0: No error"] + Stat0 = 0, + #[doc = "1: FSM error has occurred"] + Stat1 = 1, + #[doc = "2: Write index out of the bound (OOB) error"] + Stat2 = 2, + #[doc = "3: Write index OOB and FSM error"] + Stat3 = 3, + #[doc = "4: Read index OOB error"] + Stat4 = 4, + #[doc = "6: Write index and read index OOB error"] + Stat5 = 6, + #[doc = "7: Read index OOB, write index OOB, and FSM error"] + Stat6 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ErrorStatus) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ErrorStatus { + type Ux = u8; +} +impl crate::IsEnum for ErrorStatus {} +#[doc = "Field `ERROR_STATUS` reader - Status of the Error"] +pub type ErrorStatusR = crate::FieldReader; +impl ErrorStatusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ErrorStatus::Stat0), + 1 => Some(ErrorStatus::Stat1), + 2 => Some(ErrorStatus::Stat2), + 3 => Some(ErrorStatus::Stat3), + 4 => Some(ErrorStatus::Stat4), + 6 => Some(ErrorStatus::Stat5), + 7 => Some(ErrorStatus::Stat6), + _ => None, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_stat0(&self) -> bool { + *self == ErrorStatus::Stat0 + } + #[doc = "FSM error has occurred"] + #[inline(always)] + pub fn is_stat1(&self) -> bool { + *self == ErrorStatus::Stat1 + } + #[doc = "Write index out of the bound (OOB) error"] + #[inline(always)] + pub fn is_stat2(&self) -> bool { + *self == ErrorStatus::Stat2 + } + #[doc = "Write index OOB and FSM error"] + #[inline(always)] + pub fn is_stat3(&self) -> bool { + *self == ErrorStatus::Stat3 + } + #[doc = "Read index OOB error"] + #[inline(always)] + pub fn is_stat4(&self) -> bool { + *self == ErrorStatus::Stat4 + } + #[doc = "Write index and read index OOB error"] + #[inline(always)] + pub fn is_stat5(&self) -> bool { + *self == ErrorStatus::Stat5 + } + #[doc = "Read index OOB, write index OOB, and FSM error"] + #[inline(always)] + pub fn is_stat6(&self) -> bool { + *self == ErrorStatus::Stat6 + } +} +#[doc = "Field `RESERVED18` reader - Reserved for Future Use"] +pub type Reserved18R = crate::FieldReader; +#[doc = "Field `FSM_STATE` reader - Status of FSM"] +pub type FsmStateR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Interrupt Status."] + #[inline(always)] + pub fn int_status(&self) -> IntStatusR { + IntStatusR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Provides the current lock status of indexes."] + #[inline(always)] + pub fn lock_status(&self) -> LockStatusR { + LockStatusR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Status of the Error"] + #[inline(always)] + pub fn error_status(&self) -> ErrorStatusR { + ErrorStatusR::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bits 5:18 - Reserved for Future Use"] + #[inline(always)] + pub fn reserved18(&self) -> Reserved18R { + Reserved18R::new(((self.bits >> 5) & 0x3fff) as u16) + } + #[doc = "Bits 19:31 - Status of FSM"] + #[inline(always)] + pub fn fsm_state(&self) -> FsmStateR { + FsmStateR::new(((self.bits >> 19) & 0x1fff) as u16) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0x00b0_0000"] +impl crate::Resettable for StatusSpec { + const RESET_VALUE: u32 = 0x00b0_0000; +} diff --git a/mcxa276-pac/src/glikey0/version.rs b/mcxa276-pac/src/glikey0/version.rs new file mode 100644 index 000000000..a8c02d94a --- /dev/null +++ b/mcxa276-pac/src/glikey0/version.rs @@ -0,0 +1,71 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Field `Reserved3` reader - Reserved"] +pub type Reserved3R = crate::FieldReader; +#[doc = "Field `Reserved7` reader - Reserved"] +pub type Reserved7R = crate::FieldReader; +#[doc = "Field `Reserved11` reader - Reserved"] +pub type Reserved11R = crate::FieldReader; +#[doc = "Field `Reserved15` reader - Reserved"] +pub type Reserved15R = crate::FieldReader; +#[doc = "Field `MILESTONE` reader - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] +pub type MilestoneR = crate::FieldReader; +#[doc = "Field `FSM_CONFIG` reader - 0:4 step, 1:8 step"] +pub type FsmConfigR = crate::BitReader; +#[doc = "Field `INDEX_CONFIG` reader - Configured number of addressable indexes"] +pub type IndexConfigR = crate::FieldReader; +#[doc = "Field `Reserved31` reader - Reserved for Future Use"] +pub type Reserved31R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Reserved"] + #[inline(always)] + pub fn reserved3(&self) -> Reserved3R { + Reserved3R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Reserved"] + #[inline(always)] + pub fn reserved7(&self) -> Reserved7R { + Reserved7R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Reserved"] + #[inline(always)] + pub fn reserved11(&self) -> Reserved11R { + Reserved11R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Reserved"] + #[inline(always)] + pub fn reserved15(&self) -> Reserved15R { + Reserved15R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:17 - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] + #[inline(always)] + pub fn milestone(&self) -> MilestoneR { + MilestoneR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - 0:4 step, 1:8 step"] + #[inline(always)] + pub fn fsm_config(&self) -> FsmConfigR { + FsmConfigR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:26 - Configured number of addressable indexes"] + #[inline(always)] + pub fn index_config(&self) -> IndexConfigR { + IndexConfigR::new(((self.bits >> 19) & 0xff) as u8) + } + #[doc = "Bits 27:31 - Reserved for Future Use"] + #[inline(always)] + pub fn reserved31(&self) -> Reserved31R { + Reserved31R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[doc = "IP Version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VersionSpec; +impl crate::RegisterSpec for VersionSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VersionSpec {} +#[doc = "`reset()` method sets VERSION to value 0x007b_0100"] +impl crate::Resettable for VersionSpec { + const RESET_VALUE: u32 = 0x007b_0100; +} diff --git a/mcxa276-pac/src/gpio0.rs b/mcxa276-pac/src/gpio0.rs new file mode 100644 index 000000000..f42ec291b --- /dev/null +++ b/mcxa276-pac/src/gpio0.rs @@ -0,0 +1,175 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + _reserved2: [u8; 0x38], + pdor: Pdor, + psor: Psor, + pcor: Pcor, + ptor: Ptor, + pdir: Pdir, + pddr: Pddr, + pidr: Pidr, + _reserved9: [u8; 0x04], + pdr: [Pdr; 32], + icr: [Icr; 32], + giclr: Giclr, + gichr: Gichr, + _reserved13: [u8; 0x18], + isfr0: Isfr0, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x40 - Port Data Output"] + #[inline(always)] + pub const fn pdor(&self) -> &Pdor { + &self.pdor + } + #[doc = "0x44 - Port Set Output"] + #[inline(always)] + pub const fn psor(&self) -> &Psor { + &self.psor + } + #[doc = "0x48 - Port Clear Output"] + #[inline(always)] + pub const fn pcor(&self) -> &Pcor { + &self.pcor + } + #[doc = "0x4c - Port Toggle Output"] + #[inline(always)] + pub const fn ptor(&self) -> &Ptor { + &self.ptor + } + #[doc = "0x50 - Port Data Input"] + #[inline(always)] + pub const fn pdir(&self) -> &Pdir { + &self.pdir + } + #[doc = "0x54 - Port Data Direction"] + #[inline(always)] + pub const fn pddr(&self) -> &Pddr { + &self.pddr + } + #[doc = "0x58 - Port Input Disable"] + #[inline(always)] + pub const fn pidr(&self) -> &Pidr { + &self.pidr + } + #[doc = "0x60..0x80 - Pin Data"] + #[inline(always)] + pub const fn pdr(&self, n: usize) -> &Pdr { + &self.pdr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x60..0x80 - Pin Data"] + #[inline(always)] + pub fn pdr_iter(&self) -> impl Iterator { + self.pdr.iter() + } + #[doc = "0x80..0x100 - Interrupt Control index"] + #[inline(always)] + pub const fn icr(&self, n: usize) -> &Icr { + &self.icr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0x100 - Interrupt Control index"] + #[inline(always)] + pub fn icr_iter(&self) -> impl Iterator { + self.icr.iter() + } + #[doc = "0x100 - Global Interrupt Control Low"] + #[inline(always)] + pub const fn giclr(&self) -> &Giclr { + &self.giclr + } + #[doc = "0x104 - Global Interrupt Control High"] + #[inline(always)] + pub const fn gichr(&self) -> &Gichr { + &self.gichr + } + #[doc = "0x120 - Interrupt Status Flag"] + #[inline(always)] + pub const fn isfr0(&self) -> &Isfr0 { + &self.isfr0 + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "PDOR (rw) register accessor: Port Data Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pdor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdor`] module"] +#[doc(alias = "PDOR")] +pub type Pdor = crate::Reg; +#[doc = "Port Data Output"] +pub mod pdor; +#[doc = "PSOR (rw) register accessor: Port Set Output\n\nYou can [`read`](crate::Reg::read) this register and get [`psor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psor`] module"] +#[doc(alias = "PSOR")] +pub type Psor = crate::Reg; +#[doc = "Port Set Output"] +pub mod psor; +#[doc = "PCOR (rw) register accessor: Port Clear Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pcor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcor`] module"] +#[doc(alias = "PCOR")] +pub type Pcor = crate::Reg; +#[doc = "Port Clear Output"] +pub mod pcor; +#[doc = "PTOR (rw) register accessor: Port Toggle Output\n\nYou can [`read`](crate::Reg::read) this register and get [`ptor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ptor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ptor`] module"] +#[doc(alias = "PTOR")] +pub type Ptor = crate::Reg; +#[doc = "Port Toggle Output"] +pub mod ptor; +#[doc = "PDIR (r) register accessor: Port Data Input\n\nYou can [`read`](crate::Reg::read) this register and get [`pdir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdir`] module"] +#[doc(alias = "PDIR")] +pub type Pdir = crate::Reg; +#[doc = "Port Data Input"] +pub mod pdir; +#[doc = "PDDR (rw) register accessor: Port Data Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`pddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pddr`] module"] +#[doc(alias = "PDDR")] +pub type Pddr = crate::Reg; +#[doc = "Port Data Direction"] +pub mod pddr; +#[doc = "PIDR (rw) register accessor: Port Input Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pidr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pidr`] module"] +#[doc(alias = "PIDR")] +pub type Pidr = crate::Reg; +#[doc = "Port Input Disable"] +pub mod pidr; +#[doc = "PDR (rw) register accessor: Pin Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdr`] module"] +#[doc(alias = "PDR")] +pub type Pdr = crate::Reg; +#[doc = "Pin Data"] +pub mod pdr; +#[doc = "ICR (rw) register accessor: Interrupt Control index\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] module"] +#[doc(alias = "ICR")] +pub type Icr = crate::Reg; +#[doc = "Interrupt Control index"] +pub mod icr; +#[doc = "GICLR (rw) register accessor: Global Interrupt Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`giclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giclr`] module"] +#[doc(alias = "GICLR")] +pub type Giclr = crate::Reg; +#[doc = "Global Interrupt Control Low"] +pub mod giclr; +#[doc = "GICHR (rw) register accessor: Global Interrupt Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gichr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gichr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gichr`] module"] +#[doc(alias = "GICHR")] +pub type Gichr = crate::Reg; +#[doc = "Global Interrupt Control High"] +pub mod gichr; +#[doc = "ISFR0 (rw) register accessor: Interrupt Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`isfr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isfr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isfr0`] module"] +#[doc(alias = "ISFR0")] +pub type Isfr0 = crate::Reg; +#[doc = "Interrupt Status Flag"] +pub mod isfr0; diff --git a/mcxa276-pac/src/gpio0/gichr.rs b/mcxa276-pac/src/gpio0/gichr.rs new file mode 100644 index 000000000..4d2d773d7 --- /dev/null +++ b/mcxa276-pac/src/gpio0/gichr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GICHR` reader"] +pub type R = crate::R; +#[doc = "Register `GICHR` writer"] +pub type W = crate::W; +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe16 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE16` reader - Global Interrupt Write Enable"] +pub type Giwe16R = crate::BitReader; +impl Giwe16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe16 { + match self.bits { + false => Giwe16::Giwe0, + true => Giwe16::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe16::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe16::Giwe1 + } +} +#[doc = "Field `GIWE16` writer - Global Interrupt Write Enable"] +pub type Giwe16W<'a, REG> = crate::BitWriter<'a, REG, Giwe16>; +impl<'a, REG> Giwe16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe16::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe16::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe17 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE17` reader - Global Interrupt Write Enable"] +pub type Giwe17R = crate::BitReader; +impl Giwe17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe17 { + match self.bits { + false => Giwe17::Giwe0, + true => Giwe17::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe17::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe17::Giwe1 + } +} +#[doc = "Field `GIWE17` writer - Global Interrupt Write Enable"] +pub type Giwe17W<'a, REG> = crate::BitWriter<'a, REG, Giwe17>; +impl<'a, REG> Giwe17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe17::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe17::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe18 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE18` reader - Global Interrupt Write Enable"] +pub type Giwe18R = crate::BitReader; +impl Giwe18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe18 { + match self.bits { + false => Giwe18::Giwe0, + true => Giwe18::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe18::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe18::Giwe1 + } +} +#[doc = "Field `GIWE18` writer - Global Interrupt Write Enable"] +pub type Giwe18W<'a, REG> = crate::BitWriter<'a, REG, Giwe18>; +impl<'a, REG> Giwe18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe18::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe18::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe19 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE19` reader - Global Interrupt Write Enable"] +pub type Giwe19R = crate::BitReader; +impl Giwe19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe19 { + match self.bits { + false => Giwe19::Giwe0, + true => Giwe19::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe19::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe19::Giwe1 + } +} +#[doc = "Field `GIWE19` writer - Global Interrupt Write Enable"] +pub type Giwe19W<'a, REG> = crate::BitWriter<'a, REG, Giwe19>; +impl<'a, REG> Giwe19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe19::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe19::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe20 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE20` reader - Global Interrupt Write Enable"] +pub type Giwe20R = crate::BitReader; +impl Giwe20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe20 { + match self.bits { + false => Giwe20::Giwe0, + true => Giwe20::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe20::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe20::Giwe1 + } +} +#[doc = "Field `GIWE20` writer - Global Interrupt Write Enable"] +pub type Giwe20W<'a, REG> = crate::BitWriter<'a, REG, Giwe20>; +impl<'a, REG> Giwe20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe20::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe20::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe21 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE21` reader - Global Interrupt Write Enable"] +pub type Giwe21R = crate::BitReader; +impl Giwe21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe21 { + match self.bits { + false => Giwe21::Giwe0, + true => Giwe21::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe21::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe21::Giwe1 + } +} +#[doc = "Field `GIWE21` writer - Global Interrupt Write Enable"] +pub type Giwe21W<'a, REG> = crate::BitWriter<'a, REG, Giwe21>; +impl<'a, REG> Giwe21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe21::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe21::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe22 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE22` reader - Global Interrupt Write Enable"] +pub type Giwe22R = crate::BitReader; +impl Giwe22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe22 { + match self.bits { + false => Giwe22::Giwe0, + true => Giwe22::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe22::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe22::Giwe1 + } +} +#[doc = "Field `GIWE22` writer - Global Interrupt Write Enable"] +pub type Giwe22W<'a, REG> = crate::BitWriter<'a, REG, Giwe22>; +impl<'a, REG> Giwe22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe22::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe22::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe23 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE23` reader - Global Interrupt Write Enable"] +pub type Giwe23R = crate::BitReader; +impl Giwe23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe23 { + match self.bits { + false => Giwe23::Giwe0, + true => Giwe23::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe23::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe23::Giwe1 + } +} +#[doc = "Field `GIWE23` writer - Global Interrupt Write Enable"] +pub type Giwe23W<'a, REG> = crate::BitWriter<'a, REG, Giwe23>; +impl<'a, REG> Giwe23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe23::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe23::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe24 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE24` reader - Global Interrupt Write Enable"] +pub type Giwe24R = crate::BitReader; +impl Giwe24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe24 { + match self.bits { + false => Giwe24::Giwe0, + true => Giwe24::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe24::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe24::Giwe1 + } +} +#[doc = "Field `GIWE24` writer - Global Interrupt Write Enable"] +pub type Giwe24W<'a, REG> = crate::BitWriter<'a, REG, Giwe24>; +impl<'a, REG> Giwe24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe24::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe24::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe25 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE25` reader - Global Interrupt Write Enable"] +pub type Giwe25R = crate::BitReader; +impl Giwe25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe25 { + match self.bits { + false => Giwe25::Giwe0, + true => Giwe25::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe25::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe25::Giwe1 + } +} +#[doc = "Field `GIWE25` writer - Global Interrupt Write Enable"] +pub type Giwe25W<'a, REG> = crate::BitWriter<'a, REG, Giwe25>; +impl<'a, REG> Giwe25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe25::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe25::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe26 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE26` reader - Global Interrupt Write Enable"] +pub type Giwe26R = crate::BitReader; +impl Giwe26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe26 { + match self.bits { + false => Giwe26::Giwe0, + true => Giwe26::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe26::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe26::Giwe1 + } +} +#[doc = "Field `GIWE26` writer - Global Interrupt Write Enable"] +pub type Giwe26W<'a, REG> = crate::BitWriter<'a, REG, Giwe26>; +impl<'a, REG> Giwe26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe26::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe26::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe27 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE27` reader - Global Interrupt Write Enable"] +pub type Giwe27R = crate::BitReader; +impl Giwe27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe27 { + match self.bits { + false => Giwe27::Giwe0, + true => Giwe27::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe27::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe27::Giwe1 + } +} +#[doc = "Field `GIWE27` writer - Global Interrupt Write Enable"] +pub type Giwe27W<'a, REG> = crate::BitWriter<'a, REG, Giwe27>; +impl<'a, REG> Giwe27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe27::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe27::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe28 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE28` reader - Global Interrupt Write Enable"] +pub type Giwe28R = crate::BitReader; +impl Giwe28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe28 { + match self.bits { + false => Giwe28::Giwe0, + true => Giwe28::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe28::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe28::Giwe1 + } +} +#[doc = "Field `GIWE28` writer - Global Interrupt Write Enable"] +pub type Giwe28W<'a, REG> = crate::BitWriter<'a, REG, Giwe28>; +impl<'a, REG> Giwe28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe28::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe28::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe29 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE29` reader - Global Interrupt Write Enable"] +pub type Giwe29R = crate::BitReader; +impl Giwe29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe29 { + match self.bits { + false => Giwe29::Giwe0, + true => Giwe29::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe29::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe29::Giwe1 + } +} +#[doc = "Field `GIWE29` writer - Global Interrupt Write Enable"] +pub type Giwe29W<'a, REG> = crate::BitWriter<'a, REG, Giwe29>; +impl<'a, REG> Giwe29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe29::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe29::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe30 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE30` reader - Global Interrupt Write Enable"] +pub type Giwe30R = crate::BitReader; +impl Giwe30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe30 { + match self.bits { + false => Giwe30::Giwe0, + true => Giwe30::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe30::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe30::Giwe1 + } +} +#[doc = "Field `GIWE30` writer - Global Interrupt Write Enable"] +pub type Giwe30W<'a, REG> = crate::BitWriter<'a, REG, Giwe30>; +impl<'a, REG> Giwe30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe30::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe30::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe31 { + #[doc = "0: Not updated."] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE31` reader - Global Interrupt Write Enable"] +pub type Giwe31R = crate::BitReader; +impl Giwe31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe31 { + match self.bits { + false => Giwe31::Giwe0, + true => Giwe31::Giwe1, + } + } + #[doc = "Not updated."] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe31::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe31::Giwe1 + } +} +#[doc = "Field `GIWE31` writer - Global Interrupt Write Enable"] +pub type Giwe31W<'a, REG> = crate::BitWriter<'a, REG, Giwe31>; +impl<'a, REG> Giwe31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated."] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe31::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe31::Giwe1) + } +} +#[doc = "Field `GIWD` reader - Global Interrupt Write Data"] +pub type GiwdR = crate::FieldReader; +#[doc = "Field `GIWD` writer - Global Interrupt Write Data"] +pub type GiwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe16(&self) -> Giwe16R { + Giwe16R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe17(&self) -> Giwe17R { + Giwe17R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe18(&self) -> Giwe18R { + Giwe18R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe19(&self) -> Giwe19R { + Giwe19R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe20(&self) -> Giwe20R { + Giwe20R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe21(&self) -> Giwe21R { + Giwe21R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe22(&self) -> Giwe22R { + Giwe22R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe23(&self) -> Giwe23R { + Giwe23R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe24(&self) -> Giwe24R { + Giwe24R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe25(&self) -> Giwe25R { + Giwe25R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe26(&self) -> Giwe26R { + Giwe26R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe27(&self) -> Giwe27R { + Giwe27R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe28(&self) -> Giwe28R { + Giwe28R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe29(&self) -> Giwe29R { + Giwe29R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe30(&self) -> Giwe30R { + Giwe30R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe31(&self) -> Giwe31R { + Giwe31R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - Global Interrupt Write Data"] + #[inline(always)] + pub fn giwd(&self) -> GiwdR { + GiwdR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe16(&mut self) -> Giwe16W { + Giwe16W::new(self, 0) + } + #[doc = "Bit 1 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe17(&mut self) -> Giwe17W { + Giwe17W::new(self, 1) + } + #[doc = "Bit 2 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe18(&mut self) -> Giwe18W { + Giwe18W::new(self, 2) + } + #[doc = "Bit 3 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe19(&mut self) -> Giwe19W { + Giwe19W::new(self, 3) + } + #[doc = "Bit 4 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe20(&mut self) -> Giwe20W { + Giwe20W::new(self, 4) + } + #[doc = "Bit 5 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe21(&mut self) -> Giwe21W { + Giwe21W::new(self, 5) + } + #[doc = "Bit 6 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe22(&mut self) -> Giwe22W { + Giwe22W::new(self, 6) + } + #[doc = "Bit 7 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe23(&mut self) -> Giwe23W { + Giwe23W::new(self, 7) + } + #[doc = "Bit 8 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe24(&mut self) -> Giwe24W { + Giwe24W::new(self, 8) + } + #[doc = "Bit 9 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe25(&mut self) -> Giwe25W { + Giwe25W::new(self, 9) + } + #[doc = "Bit 10 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe26(&mut self) -> Giwe26W { + Giwe26W::new(self, 10) + } + #[doc = "Bit 11 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe27(&mut self) -> Giwe27W { + Giwe27W::new(self, 11) + } + #[doc = "Bit 12 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe28(&mut self) -> Giwe28W { + Giwe28W::new(self, 12) + } + #[doc = "Bit 13 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe29(&mut self) -> Giwe29W { + Giwe29W::new(self, 13) + } + #[doc = "Bit 14 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe30(&mut self) -> Giwe30W { + Giwe30W::new(self, 14) + } + #[doc = "Bit 15 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe31(&mut self) -> Giwe31W { + Giwe31W::new(self, 15) + } + #[doc = "Bits 16:31 - Global Interrupt Write Data"] + #[inline(always)] + pub fn giwd(&mut self) -> GiwdW { + GiwdW::new(self, 16) + } +} +#[doc = "Global Interrupt Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gichr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gichr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GichrSpec; +impl crate::RegisterSpec for GichrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gichr::R`](R) reader structure"] +impl crate::Readable for GichrSpec {} +#[doc = "`write(|w| ..)` method takes [`gichr::W`](W) writer structure"] +impl crate::Writable for GichrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GICHR to value 0"] +impl crate::Resettable for GichrSpec {} diff --git a/mcxa276-pac/src/gpio0/giclr.rs b/mcxa276-pac/src/gpio0/giclr.rs new file mode 100644 index 000000000..239b49ca1 --- /dev/null +++ b/mcxa276-pac/src/gpio0/giclr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GICLR` reader"] +pub type R = crate::R; +#[doc = "Register `GICLR` writer"] +pub type W = crate::W; +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe0 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE0` reader - Global Interrupt Write Enable"] +pub type Giwe0R = crate::BitReader; +impl Giwe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe0 { + match self.bits { + false => Giwe0::Giwe0, + true => Giwe0::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe0::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe0::Giwe1 + } +} +#[doc = "Field `GIWE0` writer - Global Interrupt Write Enable"] +pub type Giwe0W<'a, REG> = crate::BitWriter<'a, REG, Giwe0>; +impl<'a, REG> Giwe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe0::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe0::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe1 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE1` reader - Global Interrupt Write Enable"] +pub type Giwe1R = crate::BitReader; +impl Giwe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe1 { + match self.bits { + false => Giwe1::Giwe0, + true => Giwe1::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe1::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe1::Giwe1 + } +} +#[doc = "Field `GIWE1` writer - Global Interrupt Write Enable"] +pub type Giwe1W<'a, REG> = crate::BitWriter<'a, REG, Giwe1>; +impl<'a, REG> Giwe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe1::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe1::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe2 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE2` reader - Global Interrupt Write Enable"] +pub type Giwe2R = crate::BitReader; +impl Giwe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe2 { + match self.bits { + false => Giwe2::Giwe0, + true => Giwe2::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe2::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe2::Giwe1 + } +} +#[doc = "Field `GIWE2` writer - Global Interrupt Write Enable"] +pub type Giwe2W<'a, REG> = crate::BitWriter<'a, REG, Giwe2>; +impl<'a, REG> Giwe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe2::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe2::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe3 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE3` reader - Global Interrupt Write Enable"] +pub type Giwe3R = crate::BitReader; +impl Giwe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe3 { + match self.bits { + false => Giwe3::Giwe0, + true => Giwe3::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe3::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe3::Giwe1 + } +} +#[doc = "Field `GIWE3` writer - Global Interrupt Write Enable"] +pub type Giwe3W<'a, REG> = crate::BitWriter<'a, REG, Giwe3>; +impl<'a, REG> Giwe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe3::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe3::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe4 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE4` reader - Global Interrupt Write Enable"] +pub type Giwe4R = crate::BitReader; +impl Giwe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe4 { + match self.bits { + false => Giwe4::Giwe0, + true => Giwe4::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe4::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe4::Giwe1 + } +} +#[doc = "Field `GIWE4` writer - Global Interrupt Write Enable"] +pub type Giwe4W<'a, REG> = crate::BitWriter<'a, REG, Giwe4>; +impl<'a, REG> Giwe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe4::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe4::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe5 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE5` reader - Global Interrupt Write Enable"] +pub type Giwe5R = crate::BitReader; +impl Giwe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe5 { + match self.bits { + false => Giwe5::Giwe0, + true => Giwe5::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe5::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe5::Giwe1 + } +} +#[doc = "Field `GIWE5` writer - Global Interrupt Write Enable"] +pub type Giwe5W<'a, REG> = crate::BitWriter<'a, REG, Giwe5>; +impl<'a, REG> Giwe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe5::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe5::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe6 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE6` reader - Global Interrupt Write Enable"] +pub type Giwe6R = crate::BitReader; +impl Giwe6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe6 { + match self.bits { + false => Giwe6::Giwe0, + true => Giwe6::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe6::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe6::Giwe1 + } +} +#[doc = "Field `GIWE6` writer - Global Interrupt Write Enable"] +pub type Giwe6W<'a, REG> = crate::BitWriter<'a, REG, Giwe6>; +impl<'a, REG> Giwe6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe6::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe6::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe7 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE7` reader - Global Interrupt Write Enable"] +pub type Giwe7R = crate::BitReader; +impl Giwe7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe7 { + match self.bits { + false => Giwe7::Giwe0, + true => Giwe7::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe7::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe7::Giwe1 + } +} +#[doc = "Field `GIWE7` writer - Global Interrupt Write Enable"] +pub type Giwe7W<'a, REG> = crate::BitWriter<'a, REG, Giwe7>; +impl<'a, REG> Giwe7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe7::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe7::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe8 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE8` reader - Global Interrupt Write Enable"] +pub type Giwe8R = crate::BitReader; +impl Giwe8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe8 { + match self.bits { + false => Giwe8::Giwe0, + true => Giwe8::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe8::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe8::Giwe1 + } +} +#[doc = "Field `GIWE8` writer - Global Interrupt Write Enable"] +pub type Giwe8W<'a, REG> = crate::BitWriter<'a, REG, Giwe8>; +impl<'a, REG> Giwe8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe8::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe8::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe9 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE9` reader - Global Interrupt Write Enable"] +pub type Giwe9R = crate::BitReader; +impl Giwe9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe9 { + match self.bits { + false => Giwe9::Giwe0, + true => Giwe9::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe9::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe9::Giwe1 + } +} +#[doc = "Field `GIWE9` writer - Global Interrupt Write Enable"] +pub type Giwe9W<'a, REG> = crate::BitWriter<'a, REG, Giwe9>; +impl<'a, REG> Giwe9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe9::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe9::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe10 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE10` reader - Global Interrupt Write Enable"] +pub type Giwe10R = crate::BitReader; +impl Giwe10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe10 { + match self.bits { + false => Giwe10::Giwe0, + true => Giwe10::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe10::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe10::Giwe1 + } +} +#[doc = "Field `GIWE10` writer - Global Interrupt Write Enable"] +pub type Giwe10W<'a, REG> = crate::BitWriter<'a, REG, Giwe10>; +impl<'a, REG> Giwe10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe10::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe10::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe11 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE11` reader - Global Interrupt Write Enable"] +pub type Giwe11R = crate::BitReader; +impl Giwe11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe11 { + match self.bits { + false => Giwe11::Giwe0, + true => Giwe11::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe11::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe11::Giwe1 + } +} +#[doc = "Field `GIWE11` writer - Global Interrupt Write Enable"] +pub type Giwe11W<'a, REG> = crate::BitWriter<'a, REG, Giwe11>; +impl<'a, REG> Giwe11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe11::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe11::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe12 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE12` reader - Global Interrupt Write Enable"] +pub type Giwe12R = crate::BitReader; +impl Giwe12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe12 { + match self.bits { + false => Giwe12::Giwe0, + true => Giwe12::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe12::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe12::Giwe1 + } +} +#[doc = "Field `GIWE12` writer - Global Interrupt Write Enable"] +pub type Giwe12W<'a, REG> = crate::BitWriter<'a, REG, Giwe12>; +impl<'a, REG> Giwe12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe12::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe12::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe13 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE13` reader - Global Interrupt Write Enable"] +pub type Giwe13R = crate::BitReader; +impl Giwe13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe13 { + match self.bits { + false => Giwe13::Giwe0, + true => Giwe13::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe13::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe13::Giwe1 + } +} +#[doc = "Field `GIWE13` writer - Global Interrupt Write Enable"] +pub type Giwe13W<'a, REG> = crate::BitWriter<'a, REG, Giwe13>; +impl<'a, REG> Giwe13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe13::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe13::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe14 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE14` reader - Global Interrupt Write Enable"] +pub type Giwe14R = crate::BitReader; +impl Giwe14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe14 { + match self.bits { + false => Giwe14::Giwe0, + true => Giwe14::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe14::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe14::Giwe1 + } +} +#[doc = "Field `GIWE14` writer - Global Interrupt Write Enable"] +pub type Giwe14W<'a, REG> = crate::BitWriter<'a, REG, Giwe14>; +impl<'a, REG> Giwe14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe14::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe14::Giwe1) + } +} +#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Giwe15 { + #[doc = "0: Not updated"] + Giwe0 = 0, + #[doc = "1: Updated"] + Giwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Giwe15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GIWE15` reader - Global Interrupt Write Enable"] +pub type Giwe15R = crate::BitReader; +impl Giwe15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Giwe15 { + match self.bits { + false => Giwe15::Giwe0, + true => Giwe15::Giwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_giwe0(&self) -> bool { + *self == Giwe15::Giwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_giwe1(&self) -> bool { + *self == Giwe15::Giwe1 + } +} +#[doc = "Field `GIWE15` writer - Global Interrupt Write Enable"] +pub type Giwe15W<'a, REG> = crate::BitWriter<'a, REG, Giwe15>; +impl<'a, REG> Giwe15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn giwe0(self) -> &'a mut crate::W { + self.variant(Giwe15::Giwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn giwe1(self) -> &'a mut crate::W { + self.variant(Giwe15::Giwe1) + } +} +#[doc = "Field `GIWD` reader - Global Interrupt Write Data"] +pub type GiwdR = crate::FieldReader; +#[doc = "Field `GIWD` writer - Global Interrupt Write Data"] +pub type GiwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe0(&self) -> Giwe0R { + Giwe0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe1(&self) -> Giwe1R { + Giwe1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe2(&self) -> Giwe2R { + Giwe2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe3(&self) -> Giwe3R { + Giwe3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe4(&self) -> Giwe4R { + Giwe4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe5(&self) -> Giwe5R { + Giwe5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe6(&self) -> Giwe6R { + Giwe6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe7(&self) -> Giwe7R { + Giwe7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe8(&self) -> Giwe8R { + Giwe8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe9(&self) -> Giwe9R { + Giwe9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe10(&self) -> Giwe10R { + Giwe10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe11(&self) -> Giwe11R { + Giwe11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe12(&self) -> Giwe12R { + Giwe12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe13(&self) -> Giwe13R { + Giwe13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe14(&self) -> Giwe14R { + Giwe14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe15(&self) -> Giwe15R { + Giwe15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - Global Interrupt Write Data"] + #[inline(always)] + pub fn giwd(&self) -> GiwdR { + GiwdR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe0(&mut self) -> Giwe0W { + Giwe0W::new(self, 0) + } + #[doc = "Bit 1 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe1(&mut self) -> Giwe1W { + Giwe1W::new(self, 1) + } + #[doc = "Bit 2 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe2(&mut self) -> Giwe2W { + Giwe2W::new(self, 2) + } + #[doc = "Bit 3 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe3(&mut self) -> Giwe3W { + Giwe3W::new(self, 3) + } + #[doc = "Bit 4 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe4(&mut self) -> Giwe4W { + Giwe4W::new(self, 4) + } + #[doc = "Bit 5 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe5(&mut self) -> Giwe5W { + Giwe5W::new(self, 5) + } + #[doc = "Bit 6 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe6(&mut self) -> Giwe6W { + Giwe6W::new(self, 6) + } + #[doc = "Bit 7 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe7(&mut self) -> Giwe7W { + Giwe7W::new(self, 7) + } + #[doc = "Bit 8 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe8(&mut self) -> Giwe8W { + Giwe8W::new(self, 8) + } + #[doc = "Bit 9 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe9(&mut self) -> Giwe9W { + Giwe9W::new(self, 9) + } + #[doc = "Bit 10 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe10(&mut self) -> Giwe10W { + Giwe10W::new(self, 10) + } + #[doc = "Bit 11 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe11(&mut self) -> Giwe11W { + Giwe11W::new(self, 11) + } + #[doc = "Bit 12 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe12(&mut self) -> Giwe12W { + Giwe12W::new(self, 12) + } + #[doc = "Bit 13 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe13(&mut self) -> Giwe13W { + Giwe13W::new(self, 13) + } + #[doc = "Bit 14 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe14(&mut self) -> Giwe14W { + Giwe14W::new(self, 14) + } + #[doc = "Bit 15 - Global Interrupt Write Enable"] + #[inline(always)] + pub fn giwe15(&mut self) -> Giwe15W { + Giwe15W::new(self, 15) + } + #[doc = "Bits 16:31 - Global Interrupt Write Data"] + #[inline(always)] + pub fn giwd(&mut self) -> GiwdW { + GiwdW::new(self, 16) + } +} +#[doc = "Global Interrupt Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`giclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GiclrSpec; +impl crate::RegisterSpec for GiclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`giclr::R`](R) reader structure"] +impl crate::Readable for GiclrSpec {} +#[doc = "`write(|w| ..)` method takes [`giclr::W`](W) writer structure"] +impl crate::Writable for GiclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GICLR to value 0"] +impl crate::Resettable for GiclrSpec {} diff --git a/mcxa276-pac/src/gpio0/icr.rs b/mcxa276-pac/src/gpio0/icr.rs new file mode 100644 index 000000000..5cdb64489 --- /dev/null +++ b/mcxa276-pac/src/gpio0/icr.rs @@ -0,0 +1,311 @@ +#[doc = "Register `ICR[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `ICR[%s]` writer"] +pub type W = crate::W; +#[doc = "Interrupt Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Irqc { + #[doc = "0: ISF is disabled"] + Irqc0 = 0, + #[doc = "1: ISF and DMA request on rising edge"] + Irqc1 = 1, + #[doc = "2: ISF and DMA request on falling edge"] + Irqc2 = 2, + #[doc = "3: ISF and DMA request on either edge"] + Irqc3 = 3, + #[doc = "5: ISF sets on rising edge"] + Irqc5 = 5, + #[doc = "6: ISF sets on falling edge"] + Irqc6 = 6, + #[doc = "7: ISF sets on either edge"] + Irqc7 = 7, + #[doc = "8: ISF and interrupt when logic 0"] + Irqc8 = 8, + #[doc = "9: ISF and interrupt on rising edge"] + Irqc9 = 9, + #[doc = "10: ISF and interrupt on falling edge"] + Irqc10 = 10, + #[doc = "11: ISF and Interrupt on either edge"] + Irqc11 = 11, + #[doc = "12: ISF and interrupt when logic 1"] + Irqc12 = 12, + #[doc = "13: Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] + Irqc13 = 13, + #[doc = "14: Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] + Irqc14 = 14, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Irqc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Irqc { + type Ux = u8; +} +impl crate::IsEnum for Irqc {} +#[doc = "Field `IRQC` reader - Interrupt Configuration"] +pub type IrqcR = crate::FieldReader; +impl IrqcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Irqc::Irqc0), + 1 => Some(Irqc::Irqc1), + 2 => Some(Irqc::Irqc2), + 3 => Some(Irqc::Irqc3), + 5 => Some(Irqc::Irqc5), + 6 => Some(Irqc::Irqc6), + 7 => Some(Irqc::Irqc7), + 8 => Some(Irqc::Irqc8), + 9 => Some(Irqc::Irqc9), + 10 => Some(Irqc::Irqc10), + 11 => Some(Irqc::Irqc11), + 12 => Some(Irqc::Irqc12), + 13 => Some(Irqc::Irqc13), + 14 => Some(Irqc::Irqc14), + _ => None, + } + } + #[doc = "ISF is disabled"] + #[inline(always)] + pub fn is_irqc0(&self) -> bool { + *self == Irqc::Irqc0 + } + #[doc = "ISF and DMA request on rising edge"] + #[inline(always)] + pub fn is_irqc1(&self) -> bool { + *self == Irqc::Irqc1 + } + #[doc = "ISF and DMA request on falling edge"] + #[inline(always)] + pub fn is_irqc2(&self) -> bool { + *self == Irqc::Irqc2 + } + #[doc = "ISF and DMA request on either edge"] + #[inline(always)] + pub fn is_irqc3(&self) -> bool { + *self == Irqc::Irqc3 + } + #[doc = "ISF sets on rising edge"] + #[inline(always)] + pub fn is_irqc5(&self) -> bool { + *self == Irqc::Irqc5 + } + #[doc = "ISF sets on falling edge"] + #[inline(always)] + pub fn is_irqc6(&self) -> bool { + *self == Irqc::Irqc6 + } + #[doc = "ISF sets on either edge"] + #[inline(always)] + pub fn is_irqc7(&self) -> bool { + *self == Irqc::Irqc7 + } + #[doc = "ISF and interrupt when logic 0"] + #[inline(always)] + pub fn is_irqc8(&self) -> bool { + *self == Irqc::Irqc8 + } + #[doc = "ISF and interrupt on rising edge"] + #[inline(always)] + pub fn is_irqc9(&self) -> bool { + *self == Irqc::Irqc9 + } + #[doc = "ISF and interrupt on falling edge"] + #[inline(always)] + pub fn is_irqc10(&self) -> bool { + *self == Irqc::Irqc10 + } + #[doc = "ISF and Interrupt on either edge"] + #[inline(always)] + pub fn is_irqc11(&self) -> bool { + *self == Irqc::Irqc11 + } + #[doc = "ISF and interrupt when logic 1"] + #[inline(always)] + pub fn is_irqc12(&self) -> bool { + *self == Irqc::Irqc12 + } + #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] + #[inline(always)] + pub fn is_irqc13(&self) -> bool { + *self == Irqc::Irqc13 + } + #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] + #[inline(always)] + pub fn is_irqc14(&self) -> bool { + *self == Irqc::Irqc14 + } +} +#[doc = "Field `IRQC` writer - Interrupt Configuration"] +pub type IrqcW<'a, REG> = crate::FieldWriter<'a, REG, 4, Irqc>; +impl<'a, REG> IrqcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ISF is disabled"] + #[inline(always)] + pub fn irqc0(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc0) + } + #[doc = "ISF and DMA request on rising edge"] + #[inline(always)] + pub fn irqc1(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc1) + } + #[doc = "ISF and DMA request on falling edge"] + #[inline(always)] + pub fn irqc2(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc2) + } + #[doc = "ISF and DMA request on either edge"] + #[inline(always)] + pub fn irqc3(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc3) + } + #[doc = "ISF sets on rising edge"] + #[inline(always)] + pub fn irqc5(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc5) + } + #[doc = "ISF sets on falling edge"] + #[inline(always)] + pub fn irqc6(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc6) + } + #[doc = "ISF sets on either edge"] + #[inline(always)] + pub fn irqc7(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc7) + } + #[doc = "ISF and interrupt when logic 0"] + #[inline(always)] + pub fn irqc8(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc8) + } + #[doc = "ISF and interrupt on rising edge"] + #[inline(always)] + pub fn irqc9(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc9) + } + #[doc = "ISF and interrupt on falling edge"] + #[inline(always)] + pub fn irqc10(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc10) + } + #[doc = "ISF and Interrupt on either edge"] + #[inline(always)] + pub fn irqc11(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc11) + } + #[doc = "ISF and interrupt when logic 1"] + #[inline(always)] + pub fn irqc12(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc12) + } + #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] + #[inline(always)] + pub fn irqc13(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc13) + } + #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] + #[inline(always)] + pub fn irqc14(self) -> &'a mut crate::W { + self.variant(Irqc::Irqc14) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF` reader - Interrupt Status Flag"] +pub type IsfR = crate::BitReader; +impl IsfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf { + match self.bits { + false => Isf::Isf0, + true => Isf::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf::Isf1 + } +} +#[doc = "Field `ISF` writer - Interrupt Status Flag"] +pub type IsfW<'a, REG> = crate::BitWriter1C<'a, REG, Isf>; +impl<'a, REG> IsfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf::Isf1) + } +} +impl R { + #[doc = "Bits 16:19 - Interrupt Configuration"] + #[inline(always)] + pub fn irqc(&self) -> IrqcR { + IrqcR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 24 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf(&self) -> IsfR { + IsfR::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bits 16:19 - Interrupt Configuration"] + #[inline(always)] + pub fn irqc(&mut self) -> IrqcW { + IrqcW::new(self, 16) + } + #[doc = "Bit 24 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf(&mut self) -> IsfW { + IsfW::new(self, 24) + } +} +#[doc = "Interrupt Control index\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IcrSpec; +impl crate::RegisterSpec for IcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`icr::R`](R) reader structure"] +impl crate::Readable for IcrSpec {} +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] +impl crate::Writable for IcrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0100_0000; +} +#[doc = "`reset()` method sets ICR[%s] to value 0"] +impl crate::Resettable for IcrSpec {} diff --git a/mcxa276-pac/src/gpio0/isfr0.rs b/mcxa276-pac/src/gpio0/isfr0.rs new file mode 100644 index 000000000..aff3f0b1b --- /dev/null +++ b/mcxa276-pac/src/gpio0/isfr0.rs @@ -0,0 +1,2038 @@ +#[doc = "Register `ISFR0` reader"] +pub type R = crate::R; +#[doc = "Register `ISFR0` writer"] +pub type W = crate::W; +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf0 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF0` reader - Interrupt Status Flag"] +pub type Isf0R = crate::BitReader; +impl Isf0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf0 { + match self.bits { + false => Isf0::Isf0, + true => Isf0::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf0::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf0::Isf1 + } +} +#[doc = "Field `ISF0` writer - Interrupt Status Flag"] +pub type Isf0W<'a, REG> = crate::BitWriter1C<'a, REG, Isf0>; +impl<'a, REG> Isf0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf0::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf0::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf1 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF1` reader - Interrupt Status Flag"] +pub type Isf1R = crate::BitReader; +impl Isf1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf1 { + match self.bits { + false => Isf1::Isf0, + true => Isf1::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf1::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf1::Isf1 + } +} +#[doc = "Field `ISF1` writer - Interrupt Status Flag"] +pub type Isf1W<'a, REG> = crate::BitWriter1C<'a, REG, Isf1>; +impl<'a, REG> Isf1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf1::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf1::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf2 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF2` reader - Interrupt Status Flag"] +pub type Isf2R = crate::BitReader; +impl Isf2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf2 { + match self.bits { + false => Isf2::Isf0, + true => Isf2::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf2::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf2::Isf1 + } +} +#[doc = "Field `ISF2` writer - Interrupt Status Flag"] +pub type Isf2W<'a, REG> = crate::BitWriter1C<'a, REG, Isf2>; +impl<'a, REG> Isf2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf2::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf2::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf3 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF3` reader - Interrupt Status Flag"] +pub type Isf3R = crate::BitReader; +impl Isf3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf3 { + match self.bits { + false => Isf3::Isf0, + true => Isf3::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf3::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf3::Isf1 + } +} +#[doc = "Field `ISF3` writer - Interrupt Status Flag"] +pub type Isf3W<'a, REG> = crate::BitWriter1C<'a, REG, Isf3>; +impl<'a, REG> Isf3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf3::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf3::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf4 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF4` reader - Interrupt Status Flag"] +pub type Isf4R = crate::BitReader; +impl Isf4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf4 { + match self.bits { + false => Isf4::Isf0, + true => Isf4::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf4::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf4::Isf1 + } +} +#[doc = "Field `ISF4` writer - Interrupt Status Flag"] +pub type Isf4W<'a, REG> = crate::BitWriter1C<'a, REG, Isf4>; +impl<'a, REG> Isf4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf4::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf4::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf5 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF5` reader - Interrupt Status Flag"] +pub type Isf5R = crate::BitReader; +impl Isf5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf5 { + match self.bits { + false => Isf5::Isf0, + true => Isf5::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf5::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf5::Isf1 + } +} +#[doc = "Field `ISF5` writer - Interrupt Status Flag"] +pub type Isf5W<'a, REG> = crate::BitWriter1C<'a, REG, Isf5>; +impl<'a, REG> Isf5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf5::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf5::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf6 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF6` reader - Interrupt Status Flag"] +pub type Isf6R = crate::BitReader; +impl Isf6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf6 { + match self.bits { + false => Isf6::Isf0, + true => Isf6::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf6::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf6::Isf1 + } +} +#[doc = "Field `ISF6` writer - Interrupt Status Flag"] +pub type Isf6W<'a, REG> = crate::BitWriter1C<'a, REG, Isf6>; +impl<'a, REG> Isf6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf6::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf6::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf7 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF7` reader - Interrupt Status Flag"] +pub type Isf7R = crate::BitReader; +impl Isf7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf7 { + match self.bits { + false => Isf7::Isf0, + true => Isf7::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf7::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf7::Isf1 + } +} +#[doc = "Field `ISF7` writer - Interrupt Status Flag"] +pub type Isf7W<'a, REG> = crate::BitWriter1C<'a, REG, Isf7>; +impl<'a, REG> Isf7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf7::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf7::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf8 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF8` reader - Interrupt Status Flag"] +pub type Isf8R = crate::BitReader; +impl Isf8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf8 { + match self.bits { + false => Isf8::Isf0, + true => Isf8::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf8::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf8::Isf1 + } +} +#[doc = "Field `ISF8` writer - Interrupt Status Flag"] +pub type Isf8W<'a, REG> = crate::BitWriter1C<'a, REG, Isf8>; +impl<'a, REG> Isf8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf8::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf8::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf9 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF9` reader - Interrupt Status Flag"] +pub type Isf9R = crate::BitReader; +impl Isf9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf9 { + match self.bits { + false => Isf9::Isf0, + true => Isf9::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf9::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf9::Isf1 + } +} +#[doc = "Field `ISF9` writer - Interrupt Status Flag"] +pub type Isf9W<'a, REG> = crate::BitWriter1C<'a, REG, Isf9>; +impl<'a, REG> Isf9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf9::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf9::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf10 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF10` reader - Interrupt Status Flag"] +pub type Isf10R = crate::BitReader; +impl Isf10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf10 { + match self.bits { + false => Isf10::Isf0, + true => Isf10::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf10::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf10::Isf1 + } +} +#[doc = "Field `ISF10` writer - Interrupt Status Flag"] +pub type Isf10W<'a, REG> = crate::BitWriter1C<'a, REG, Isf10>; +impl<'a, REG> Isf10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf10::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf10::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf11 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF11` reader - Interrupt Status Flag"] +pub type Isf11R = crate::BitReader; +impl Isf11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf11 { + match self.bits { + false => Isf11::Isf0, + true => Isf11::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf11::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf11::Isf1 + } +} +#[doc = "Field `ISF11` writer - Interrupt Status Flag"] +pub type Isf11W<'a, REG> = crate::BitWriter1C<'a, REG, Isf11>; +impl<'a, REG> Isf11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf11::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf11::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf12 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF12` reader - Interrupt Status Flag"] +pub type Isf12R = crate::BitReader; +impl Isf12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf12 { + match self.bits { + false => Isf12::Isf0, + true => Isf12::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf12::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf12::Isf1 + } +} +#[doc = "Field `ISF12` writer - Interrupt Status Flag"] +pub type Isf12W<'a, REG> = crate::BitWriter1C<'a, REG, Isf12>; +impl<'a, REG> Isf12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf12::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf12::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf13 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF13` reader - Interrupt Status Flag"] +pub type Isf13R = crate::BitReader; +impl Isf13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf13 { + match self.bits { + false => Isf13::Isf0, + true => Isf13::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf13::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf13::Isf1 + } +} +#[doc = "Field `ISF13` writer - Interrupt Status Flag"] +pub type Isf13W<'a, REG> = crate::BitWriter1C<'a, REG, Isf13>; +impl<'a, REG> Isf13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf13::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf13::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf14 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF14` reader - Interrupt Status Flag"] +pub type Isf14R = crate::BitReader; +impl Isf14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf14 { + match self.bits { + false => Isf14::Isf0, + true => Isf14::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf14::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf14::Isf1 + } +} +#[doc = "Field `ISF14` writer - Interrupt Status Flag"] +pub type Isf14W<'a, REG> = crate::BitWriter1C<'a, REG, Isf14>; +impl<'a, REG> Isf14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf14::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf14::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf15 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF15` reader - Interrupt Status Flag"] +pub type Isf15R = crate::BitReader; +impl Isf15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf15 { + match self.bits { + false => Isf15::Isf0, + true => Isf15::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf15::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf15::Isf1 + } +} +#[doc = "Field `ISF15` writer - Interrupt Status Flag"] +pub type Isf15W<'a, REG> = crate::BitWriter1C<'a, REG, Isf15>; +impl<'a, REG> Isf15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf15::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf15::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf16 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF16` reader - Interrupt Status Flag"] +pub type Isf16R = crate::BitReader; +impl Isf16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf16 { + match self.bits { + false => Isf16::Isf0, + true => Isf16::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf16::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf16::Isf1 + } +} +#[doc = "Field `ISF16` writer - Interrupt Status Flag"] +pub type Isf16W<'a, REG> = crate::BitWriter1C<'a, REG, Isf16>; +impl<'a, REG> Isf16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf16::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf16::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf17 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF17` reader - Interrupt Status Flag"] +pub type Isf17R = crate::BitReader; +impl Isf17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf17 { + match self.bits { + false => Isf17::Isf0, + true => Isf17::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf17::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf17::Isf1 + } +} +#[doc = "Field `ISF17` writer - Interrupt Status Flag"] +pub type Isf17W<'a, REG> = crate::BitWriter1C<'a, REG, Isf17>; +impl<'a, REG> Isf17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf17::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf17::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf18 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF18` reader - Interrupt Status Flag"] +pub type Isf18R = crate::BitReader; +impl Isf18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf18 { + match self.bits { + false => Isf18::Isf0, + true => Isf18::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf18::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf18::Isf1 + } +} +#[doc = "Field `ISF18` writer - Interrupt Status Flag"] +pub type Isf18W<'a, REG> = crate::BitWriter1C<'a, REG, Isf18>; +impl<'a, REG> Isf18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf18::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf18::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf19 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF19` reader - Interrupt Status Flag"] +pub type Isf19R = crate::BitReader; +impl Isf19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf19 { + match self.bits { + false => Isf19::Isf0, + true => Isf19::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf19::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf19::Isf1 + } +} +#[doc = "Field `ISF19` writer - Interrupt Status Flag"] +pub type Isf19W<'a, REG> = crate::BitWriter1C<'a, REG, Isf19>; +impl<'a, REG> Isf19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf19::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf19::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf20 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF20` reader - Interrupt Status Flag"] +pub type Isf20R = crate::BitReader; +impl Isf20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf20 { + match self.bits { + false => Isf20::Isf0, + true => Isf20::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf20::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf20::Isf1 + } +} +#[doc = "Field `ISF20` writer - Interrupt Status Flag"] +pub type Isf20W<'a, REG> = crate::BitWriter1C<'a, REG, Isf20>; +impl<'a, REG> Isf20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf20::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf20::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf21 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF21` reader - Interrupt Status Flag"] +pub type Isf21R = crate::BitReader; +impl Isf21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf21 { + match self.bits { + false => Isf21::Isf0, + true => Isf21::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf21::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf21::Isf1 + } +} +#[doc = "Field `ISF21` writer - Interrupt Status Flag"] +pub type Isf21W<'a, REG> = crate::BitWriter1C<'a, REG, Isf21>; +impl<'a, REG> Isf21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf21::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf21::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf22 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF22` reader - Interrupt Status Flag"] +pub type Isf22R = crate::BitReader; +impl Isf22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf22 { + match self.bits { + false => Isf22::Isf0, + true => Isf22::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf22::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf22::Isf1 + } +} +#[doc = "Field `ISF22` writer - Interrupt Status Flag"] +pub type Isf22W<'a, REG> = crate::BitWriter1C<'a, REG, Isf22>; +impl<'a, REG> Isf22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf22::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf22::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf23 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF23` reader - Interrupt Status Flag"] +pub type Isf23R = crate::BitReader; +impl Isf23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf23 { + match self.bits { + false => Isf23::Isf0, + true => Isf23::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf23::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf23::Isf1 + } +} +#[doc = "Field `ISF23` writer - Interrupt Status Flag"] +pub type Isf23W<'a, REG> = crate::BitWriter1C<'a, REG, Isf23>; +impl<'a, REG> Isf23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf23::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf23::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf24 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF24` reader - Interrupt Status Flag"] +pub type Isf24R = crate::BitReader; +impl Isf24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf24 { + match self.bits { + false => Isf24::Isf0, + true => Isf24::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf24::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf24::Isf1 + } +} +#[doc = "Field `ISF24` writer - Interrupt Status Flag"] +pub type Isf24W<'a, REG> = crate::BitWriter1C<'a, REG, Isf24>; +impl<'a, REG> Isf24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf24::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf24::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf25 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF25` reader - Interrupt Status Flag"] +pub type Isf25R = crate::BitReader; +impl Isf25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf25 { + match self.bits { + false => Isf25::Isf0, + true => Isf25::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf25::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf25::Isf1 + } +} +#[doc = "Field `ISF25` writer - Interrupt Status Flag"] +pub type Isf25W<'a, REG> = crate::BitWriter1C<'a, REG, Isf25>; +impl<'a, REG> Isf25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf25::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf25::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf26 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF26` reader - Interrupt Status Flag"] +pub type Isf26R = crate::BitReader; +impl Isf26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf26 { + match self.bits { + false => Isf26::Isf0, + true => Isf26::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf26::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf26::Isf1 + } +} +#[doc = "Field `ISF26` writer - Interrupt Status Flag"] +pub type Isf26W<'a, REG> = crate::BitWriter1C<'a, REG, Isf26>; +impl<'a, REG> Isf26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf26::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf26::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf27 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF27` reader - Interrupt Status Flag"] +pub type Isf27R = crate::BitReader; +impl Isf27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf27 { + match self.bits { + false => Isf27::Isf0, + true => Isf27::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf27::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf27::Isf1 + } +} +#[doc = "Field `ISF27` writer - Interrupt Status Flag"] +pub type Isf27W<'a, REG> = crate::BitWriter1C<'a, REG, Isf27>; +impl<'a, REG> Isf27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf27::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf27::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf28 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF28` reader - Interrupt Status Flag"] +pub type Isf28R = crate::BitReader; +impl Isf28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf28 { + match self.bits { + false => Isf28::Isf0, + true => Isf28::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf28::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf28::Isf1 + } +} +#[doc = "Field `ISF28` writer - Interrupt Status Flag"] +pub type Isf28W<'a, REG> = crate::BitWriter1C<'a, REG, Isf28>; +impl<'a, REG> Isf28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf28::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf28::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf29 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF29` reader - Interrupt Status Flag"] +pub type Isf29R = crate::BitReader; +impl Isf29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf29 { + match self.bits { + false => Isf29::Isf0, + true => Isf29::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf29::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf29::Isf1 + } +} +#[doc = "Field `ISF29` writer - Interrupt Status Flag"] +pub type Isf29W<'a, REG> = crate::BitWriter1C<'a, REG, Isf29>; +impl<'a, REG> Isf29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf29::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf29::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf30 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF30` reader - Interrupt Status Flag"] +pub type Isf30R = crate::BitReader; +impl Isf30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf30 { + match self.bits { + false => Isf30::Isf0, + true => Isf30::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf30::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf30::Isf1 + } +} +#[doc = "Field `ISF30` writer - Interrupt Status Flag"] +pub type Isf30W<'a, REG> = crate::BitWriter1C<'a, REG, Isf30>; +impl<'a, REG> Isf30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf30::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf30::Isf1) + } +} +#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Isf31 { + #[doc = "0: Not detected"] + Isf0 = 0, + #[doc = "1: Detected"] + Isf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Isf31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ISF31` reader - Interrupt Status Flag"] +pub type Isf31R = crate::BitReader; +impl Isf31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Isf31 { + match self.bits { + false => Isf31::Isf0, + true => Isf31::Isf1, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_isf0(&self) -> bool { + *self == Isf31::Isf0 + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_isf1(&self) -> bool { + *self == Isf31::Isf1 + } +} +#[doc = "Field `ISF31` writer - Interrupt Status Flag"] +pub type Isf31W<'a, REG> = crate::BitWriter1C<'a, REG, Isf31>; +impl<'a, REG> Isf31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn isf0(self) -> &'a mut crate::W { + self.variant(Isf31::Isf0) + } + #[doc = "Detected"] + #[inline(always)] + pub fn isf1(self) -> &'a mut crate::W { + self.variant(Isf31::Isf1) + } +} +impl R { + #[doc = "Bit 0 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf0(&self) -> Isf0R { + Isf0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf1(&self) -> Isf1R { + Isf1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf2(&self) -> Isf2R { + Isf2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf3(&self) -> Isf3R { + Isf3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf4(&self) -> Isf4R { + Isf4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf5(&self) -> Isf5R { + Isf5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf6(&self) -> Isf6R { + Isf6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf7(&self) -> Isf7R { + Isf7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf8(&self) -> Isf8R { + Isf8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf9(&self) -> Isf9R { + Isf9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf10(&self) -> Isf10R { + Isf10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf11(&self) -> Isf11R { + Isf11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf12(&self) -> Isf12R { + Isf12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf13(&self) -> Isf13R { + Isf13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf14(&self) -> Isf14R { + Isf14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf15(&self) -> Isf15R { + Isf15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf16(&self) -> Isf16R { + Isf16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf17(&self) -> Isf17R { + Isf17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf18(&self) -> Isf18R { + Isf18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf19(&self) -> Isf19R { + Isf19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf20(&self) -> Isf20R { + Isf20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf21(&self) -> Isf21R { + Isf21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf22(&self) -> Isf22R { + Isf22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf23(&self) -> Isf23R { + Isf23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf24(&self) -> Isf24R { + Isf24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf25(&self) -> Isf25R { + Isf25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf26(&self) -> Isf26R { + Isf26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf27(&self) -> Isf27R { + Isf27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf28(&self) -> Isf28R { + Isf28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf29(&self) -> Isf29R { + Isf29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf30(&self) -> Isf30R { + Isf30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf31(&self) -> Isf31R { + Isf31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf0(&mut self) -> Isf0W { + Isf0W::new(self, 0) + } + #[doc = "Bit 1 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf1(&mut self) -> Isf1W { + Isf1W::new(self, 1) + } + #[doc = "Bit 2 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf2(&mut self) -> Isf2W { + Isf2W::new(self, 2) + } + #[doc = "Bit 3 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf3(&mut self) -> Isf3W { + Isf3W::new(self, 3) + } + #[doc = "Bit 4 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf4(&mut self) -> Isf4W { + Isf4W::new(self, 4) + } + #[doc = "Bit 5 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf5(&mut self) -> Isf5W { + Isf5W::new(self, 5) + } + #[doc = "Bit 6 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf6(&mut self) -> Isf6W { + Isf6W::new(self, 6) + } + #[doc = "Bit 7 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf7(&mut self) -> Isf7W { + Isf7W::new(self, 7) + } + #[doc = "Bit 8 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf8(&mut self) -> Isf8W { + Isf8W::new(self, 8) + } + #[doc = "Bit 9 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf9(&mut self) -> Isf9W { + Isf9W::new(self, 9) + } + #[doc = "Bit 10 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf10(&mut self) -> Isf10W { + Isf10W::new(self, 10) + } + #[doc = "Bit 11 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf11(&mut self) -> Isf11W { + Isf11W::new(self, 11) + } + #[doc = "Bit 12 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf12(&mut self) -> Isf12W { + Isf12W::new(self, 12) + } + #[doc = "Bit 13 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf13(&mut self) -> Isf13W { + Isf13W::new(self, 13) + } + #[doc = "Bit 14 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf14(&mut self) -> Isf14W { + Isf14W::new(self, 14) + } + #[doc = "Bit 15 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf15(&mut self) -> Isf15W { + Isf15W::new(self, 15) + } + #[doc = "Bit 16 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf16(&mut self) -> Isf16W { + Isf16W::new(self, 16) + } + #[doc = "Bit 17 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf17(&mut self) -> Isf17W { + Isf17W::new(self, 17) + } + #[doc = "Bit 18 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf18(&mut self) -> Isf18W { + Isf18W::new(self, 18) + } + #[doc = "Bit 19 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf19(&mut self) -> Isf19W { + Isf19W::new(self, 19) + } + #[doc = "Bit 20 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf20(&mut self) -> Isf20W { + Isf20W::new(self, 20) + } + #[doc = "Bit 21 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf21(&mut self) -> Isf21W { + Isf21W::new(self, 21) + } + #[doc = "Bit 22 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf22(&mut self) -> Isf22W { + Isf22W::new(self, 22) + } + #[doc = "Bit 23 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf23(&mut self) -> Isf23W { + Isf23W::new(self, 23) + } + #[doc = "Bit 24 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf24(&mut self) -> Isf24W { + Isf24W::new(self, 24) + } + #[doc = "Bit 25 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf25(&mut self) -> Isf25W { + Isf25W::new(self, 25) + } + #[doc = "Bit 26 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf26(&mut self) -> Isf26W { + Isf26W::new(self, 26) + } + #[doc = "Bit 27 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf27(&mut self) -> Isf27W { + Isf27W::new(self, 27) + } + #[doc = "Bit 28 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf28(&mut self) -> Isf28W { + Isf28W::new(self, 28) + } + #[doc = "Bit 29 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf29(&mut self) -> Isf29W { + Isf29W::new(self, 29) + } + #[doc = "Bit 30 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf30(&mut self) -> Isf30W { + Isf30W::new(self, 30) + } + #[doc = "Bit 31 - Interrupt Status Flag"] + #[inline(always)] + pub fn isf31(&mut self) -> Isf31W { + Isf31W::new(self, 31) + } +} +#[doc = "Interrupt Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`isfr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isfr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Isfr0Spec; +impl crate::RegisterSpec for Isfr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`isfr0::R`](R) reader structure"] +impl crate::Readable for Isfr0Spec {} +#[doc = "`write(|w| ..)` method takes [`isfr0::W`](W) writer structure"] +impl crate::Writable for Isfr0Spec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets ISFR0 to value 0"] +impl crate::Resettable for Isfr0Spec {} diff --git a/mcxa276-pac/src/gpio0/param.rs b/mcxa276-pac/src/gpio0/param.rs new file mode 100644 index 000000000..8544fc60e --- /dev/null +++ b/mcxa276-pac/src/gpio0/param.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "Field `IRQNUM` reader - Interrupt Number"] +pub type IrqnumR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Interrupt Number"] + #[inline(always)] + pub fn irqnum(&self) -> IrqnumR { + IrqnumR::new((self.bits & 0x0f) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x01"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/gpio0/pcor.rs b/mcxa276-pac/src/gpio0/pcor.rs new file mode 100644 index 000000000..705ec181b --- /dev/null +++ b/mcxa276-pac/src/gpio0/pcor.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `PCOR` reader"] +pub type R = crate::R; +#[doc = "Register `PCOR` writer"] +pub type W = crate::W; +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco0 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO0` reader - Port Clear Output"] +pub type Ptco0R = crate::BitReader; +impl Ptco0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco0 { + match self.bits { + false => Ptco0::Ptco0, + true => Ptco0::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco0::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco0::Ptco1 + } +} +#[doc = "Field `PTCO0` writer - Port Clear Output"] +pub type Ptco0W<'a, REG> = crate::BitWriter<'a, REG, Ptco0>; +impl<'a, REG> Ptco0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco0::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco0::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco1 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO1` reader - Port Clear Output"] +pub type Ptco1R = crate::BitReader; +impl Ptco1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco1 { + match self.bits { + false => Ptco1::Ptco0, + true => Ptco1::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco1::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco1::Ptco1 + } +} +#[doc = "Field `PTCO1` writer - Port Clear Output"] +pub type Ptco1W<'a, REG> = crate::BitWriter<'a, REG, Ptco1>; +impl<'a, REG> Ptco1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco1::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco1::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco2 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO2` reader - Port Clear Output"] +pub type Ptco2R = crate::BitReader; +impl Ptco2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco2 { + match self.bits { + false => Ptco2::Ptco0, + true => Ptco2::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco2::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco2::Ptco1 + } +} +#[doc = "Field `PTCO2` writer - Port Clear Output"] +pub type Ptco2W<'a, REG> = crate::BitWriter<'a, REG, Ptco2>; +impl<'a, REG> Ptco2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco2::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco2::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco3 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO3` reader - Port Clear Output"] +pub type Ptco3R = crate::BitReader; +impl Ptco3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco3 { + match self.bits { + false => Ptco3::Ptco0, + true => Ptco3::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco3::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco3::Ptco1 + } +} +#[doc = "Field `PTCO3` writer - Port Clear Output"] +pub type Ptco3W<'a, REG> = crate::BitWriter<'a, REG, Ptco3>; +impl<'a, REG> Ptco3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco3::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco3::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco4 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO4` reader - Port Clear Output"] +pub type Ptco4R = crate::BitReader; +impl Ptco4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco4 { + match self.bits { + false => Ptco4::Ptco0, + true => Ptco4::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco4::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco4::Ptco1 + } +} +#[doc = "Field `PTCO4` writer - Port Clear Output"] +pub type Ptco4W<'a, REG> = crate::BitWriter<'a, REG, Ptco4>; +impl<'a, REG> Ptco4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco4::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco4::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco5 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO5` reader - Port Clear Output"] +pub type Ptco5R = crate::BitReader; +impl Ptco5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco5 { + match self.bits { + false => Ptco5::Ptco0, + true => Ptco5::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco5::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco5::Ptco1 + } +} +#[doc = "Field `PTCO5` writer - Port Clear Output"] +pub type Ptco5W<'a, REG> = crate::BitWriter<'a, REG, Ptco5>; +impl<'a, REG> Ptco5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco5::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco5::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco6 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO6` reader - Port Clear Output"] +pub type Ptco6R = crate::BitReader; +impl Ptco6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco6 { + match self.bits { + false => Ptco6::Ptco0, + true => Ptco6::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco6::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco6::Ptco1 + } +} +#[doc = "Field `PTCO6` writer - Port Clear Output"] +pub type Ptco6W<'a, REG> = crate::BitWriter<'a, REG, Ptco6>; +impl<'a, REG> Ptco6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco6::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco6::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco7 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO7` reader - Port Clear Output"] +pub type Ptco7R = crate::BitReader; +impl Ptco7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco7 { + match self.bits { + false => Ptco7::Ptco0, + true => Ptco7::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco7::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco7::Ptco1 + } +} +#[doc = "Field `PTCO7` writer - Port Clear Output"] +pub type Ptco7W<'a, REG> = crate::BitWriter<'a, REG, Ptco7>; +impl<'a, REG> Ptco7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco7::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco7::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco8 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO8` reader - Port Clear Output"] +pub type Ptco8R = crate::BitReader; +impl Ptco8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco8 { + match self.bits { + false => Ptco8::Ptco0, + true => Ptco8::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco8::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco8::Ptco1 + } +} +#[doc = "Field `PTCO8` writer - Port Clear Output"] +pub type Ptco8W<'a, REG> = crate::BitWriter<'a, REG, Ptco8>; +impl<'a, REG> Ptco8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco8::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco8::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco9 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO9` reader - Port Clear Output"] +pub type Ptco9R = crate::BitReader; +impl Ptco9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco9 { + match self.bits { + false => Ptco9::Ptco0, + true => Ptco9::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco9::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco9::Ptco1 + } +} +#[doc = "Field `PTCO9` writer - Port Clear Output"] +pub type Ptco9W<'a, REG> = crate::BitWriter<'a, REG, Ptco9>; +impl<'a, REG> Ptco9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco9::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco9::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco10 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO10` reader - Port Clear Output"] +pub type Ptco10R = crate::BitReader; +impl Ptco10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco10 { + match self.bits { + false => Ptco10::Ptco0, + true => Ptco10::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco10::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco10::Ptco1 + } +} +#[doc = "Field `PTCO10` writer - Port Clear Output"] +pub type Ptco10W<'a, REG> = crate::BitWriter<'a, REG, Ptco10>; +impl<'a, REG> Ptco10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco10::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco10::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco11 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO11` reader - Port Clear Output"] +pub type Ptco11R = crate::BitReader; +impl Ptco11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco11 { + match self.bits { + false => Ptco11::Ptco0, + true => Ptco11::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco11::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco11::Ptco1 + } +} +#[doc = "Field `PTCO11` writer - Port Clear Output"] +pub type Ptco11W<'a, REG> = crate::BitWriter<'a, REG, Ptco11>; +impl<'a, REG> Ptco11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco11::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco11::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco12 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO12` reader - Port Clear Output"] +pub type Ptco12R = crate::BitReader; +impl Ptco12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco12 { + match self.bits { + false => Ptco12::Ptco0, + true => Ptco12::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco12::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco12::Ptco1 + } +} +#[doc = "Field `PTCO12` writer - Port Clear Output"] +pub type Ptco12W<'a, REG> = crate::BitWriter<'a, REG, Ptco12>; +impl<'a, REG> Ptco12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco12::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco12::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco13 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO13` reader - Port Clear Output"] +pub type Ptco13R = crate::BitReader; +impl Ptco13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco13 { + match self.bits { + false => Ptco13::Ptco0, + true => Ptco13::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco13::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco13::Ptco1 + } +} +#[doc = "Field `PTCO13` writer - Port Clear Output"] +pub type Ptco13W<'a, REG> = crate::BitWriter<'a, REG, Ptco13>; +impl<'a, REG> Ptco13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco13::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco13::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco14 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO14` reader - Port Clear Output"] +pub type Ptco14R = crate::BitReader; +impl Ptco14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco14 { + match self.bits { + false => Ptco14::Ptco0, + true => Ptco14::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco14::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco14::Ptco1 + } +} +#[doc = "Field `PTCO14` writer - Port Clear Output"] +pub type Ptco14W<'a, REG> = crate::BitWriter<'a, REG, Ptco14>; +impl<'a, REG> Ptco14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco14::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco14::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco15 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO15` reader - Port Clear Output"] +pub type Ptco15R = crate::BitReader; +impl Ptco15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco15 { + match self.bits { + false => Ptco15::Ptco0, + true => Ptco15::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco15::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco15::Ptco1 + } +} +#[doc = "Field `PTCO15` writer - Port Clear Output"] +pub type Ptco15W<'a, REG> = crate::BitWriter<'a, REG, Ptco15>; +impl<'a, REG> Ptco15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco15::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco15::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco16 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO16` reader - Port Clear Output"] +pub type Ptco16R = crate::BitReader; +impl Ptco16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco16 { + match self.bits { + false => Ptco16::Ptco0, + true => Ptco16::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco16::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco16::Ptco1 + } +} +#[doc = "Field `PTCO16` writer - Port Clear Output"] +pub type Ptco16W<'a, REG> = crate::BitWriter<'a, REG, Ptco16>; +impl<'a, REG> Ptco16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco16::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco16::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco17 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO17` reader - Port Clear Output"] +pub type Ptco17R = crate::BitReader; +impl Ptco17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco17 { + match self.bits { + false => Ptco17::Ptco0, + true => Ptco17::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco17::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco17::Ptco1 + } +} +#[doc = "Field `PTCO17` writer - Port Clear Output"] +pub type Ptco17W<'a, REG> = crate::BitWriter<'a, REG, Ptco17>; +impl<'a, REG> Ptco17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco17::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco17::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco18 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO18` reader - Port Clear Output"] +pub type Ptco18R = crate::BitReader; +impl Ptco18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco18 { + match self.bits { + false => Ptco18::Ptco0, + true => Ptco18::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco18::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco18::Ptco1 + } +} +#[doc = "Field `PTCO18` writer - Port Clear Output"] +pub type Ptco18W<'a, REG> = crate::BitWriter<'a, REG, Ptco18>; +impl<'a, REG> Ptco18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco18::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco18::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco19 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO19` reader - Port Clear Output"] +pub type Ptco19R = crate::BitReader; +impl Ptco19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco19 { + match self.bits { + false => Ptco19::Ptco0, + true => Ptco19::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco19::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco19::Ptco1 + } +} +#[doc = "Field `PTCO19` writer - Port Clear Output"] +pub type Ptco19W<'a, REG> = crate::BitWriter<'a, REG, Ptco19>; +impl<'a, REG> Ptco19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco19::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco19::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco20 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO20` reader - Port Clear Output"] +pub type Ptco20R = crate::BitReader; +impl Ptco20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco20 { + match self.bits { + false => Ptco20::Ptco0, + true => Ptco20::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco20::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco20::Ptco1 + } +} +#[doc = "Field `PTCO20` writer - Port Clear Output"] +pub type Ptco20W<'a, REG> = crate::BitWriter<'a, REG, Ptco20>; +impl<'a, REG> Ptco20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco20::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco20::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco21 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO21` reader - Port Clear Output"] +pub type Ptco21R = crate::BitReader; +impl Ptco21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco21 { + match self.bits { + false => Ptco21::Ptco0, + true => Ptco21::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco21::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco21::Ptco1 + } +} +#[doc = "Field `PTCO21` writer - Port Clear Output"] +pub type Ptco21W<'a, REG> = crate::BitWriter<'a, REG, Ptco21>; +impl<'a, REG> Ptco21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco21::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco21::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco22 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO22` reader - Port Clear Output"] +pub type Ptco22R = crate::BitReader; +impl Ptco22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco22 { + match self.bits { + false => Ptco22::Ptco0, + true => Ptco22::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco22::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco22::Ptco1 + } +} +#[doc = "Field `PTCO22` writer - Port Clear Output"] +pub type Ptco22W<'a, REG> = crate::BitWriter<'a, REG, Ptco22>; +impl<'a, REG> Ptco22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco22::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco22::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco23 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO23` reader - Port Clear Output"] +pub type Ptco23R = crate::BitReader; +impl Ptco23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco23 { + match self.bits { + false => Ptco23::Ptco0, + true => Ptco23::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco23::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco23::Ptco1 + } +} +#[doc = "Field `PTCO23` writer - Port Clear Output"] +pub type Ptco23W<'a, REG> = crate::BitWriter<'a, REG, Ptco23>; +impl<'a, REG> Ptco23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco23::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco23::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco24 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO24` reader - Port Clear Output"] +pub type Ptco24R = crate::BitReader; +impl Ptco24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco24 { + match self.bits { + false => Ptco24::Ptco0, + true => Ptco24::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco24::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco24::Ptco1 + } +} +#[doc = "Field `PTCO24` writer - Port Clear Output"] +pub type Ptco24W<'a, REG> = crate::BitWriter<'a, REG, Ptco24>; +impl<'a, REG> Ptco24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco24::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco24::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco25 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO25` reader - Port Clear Output"] +pub type Ptco25R = crate::BitReader; +impl Ptco25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco25 { + match self.bits { + false => Ptco25::Ptco0, + true => Ptco25::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco25::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco25::Ptco1 + } +} +#[doc = "Field `PTCO25` writer - Port Clear Output"] +pub type Ptco25W<'a, REG> = crate::BitWriter<'a, REG, Ptco25>; +impl<'a, REG> Ptco25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco25::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco25::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco26 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO26` reader - Port Clear Output"] +pub type Ptco26R = crate::BitReader; +impl Ptco26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco26 { + match self.bits { + false => Ptco26::Ptco0, + true => Ptco26::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco26::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco26::Ptco1 + } +} +#[doc = "Field `PTCO26` writer - Port Clear Output"] +pub type Ptco26W<'a, REG> = crate::BitWriter<'a, REG, Ptco26>; +impl<'a, REG> Ptco26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco26::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco26::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco27 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO27` reader - Port Clear Output"] +pub type Ptco27R = crate::BitReader; +impl Ptco27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco27 { + match self.bits { + false => Ptco27::Ptco0, + true => Ptco27::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco27::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco27::Ptco1 + } +} +#[doc = "Field `PTCO27` writer - Port Clear Output"] +pub type Ptco27W<'a, REG> = crate::BitWriter<'a, REG, Ptco27>; +impl<'a, REG> Ptco27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco27::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco27::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco28 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO28` reader - Port Clear Output"] +pub type Ptco28R = crate::BitReader; +impl Ptco28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco28 { + match self.bits { + false => Ptco28::Ptco0, + true => Ptco28::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco28::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco28::Ptco1 + } +} +#[doc = "Field `PTCO28` writer - Port Clear Output"] +pub type Ptco28W<'a, REG> = crate::BitWriter<'a, REG, Ptco28>; +impl<'a, REG> Ptco28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco28::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco28::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco29 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO29` reader - Port Clear Output"] +pub type Ptco29R = crate::BitReader; +impl Ptco29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco29 { + match self.bits { + false => Ptco29::Ptco0, + true => Ptco29::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco29::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco29::Ptco1 + } +} +#[doc = "Field `PTCO29` writer - Port Clear Output"] +pub type Ptco29W<'a, REG> = crate::BitWriter<'a, REG, Ptco29>; +impl<'a, REG> Ptco29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco29::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco29::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco30 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO30` reader - Port Clear Output"] +pub type Ptco30R = crate::BitReader; +impl Ptco30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco30 { + match self.bits { + false => Ptco30::Ptco0, + true => Ptco30::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco30::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco30::Ptco1 + } +} +#[doc = "Field `PTCO30` writer - Port Clear Output"] +pub type Ptco30W<'a, REG> = crate::BitWriter<'a, REG, Ptco30>; +impl<'a, REG> Ptco30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco30::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco30::Ptco1) + } +} +#[doc = "Port Clear Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptco31 { + #[doc = "0: No change"] + Ptco0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 0"] + Ptco1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptco31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTCO31` reader - Port Clear Output"] +pub type Ptco31R = crate::BitReader; +impl Ptco31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptco31 { + match self.bits { + false => Ptco31::Ptco0, + true => Ptco31::Ptco1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptco0(&self) -> bool { + *self == Ptco31::Ptco0 + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn is_ptco1(&self) -> bool { + *self == Ptco31::Ptco1 + } +} +#[doc = "Field `PTCO31` writer - Port Clear Output"] +pub type Ptco31W<'a, REG> = crate::BitWriter<'a, REG, Ptco31>; +impl<'a, REG> Ptco31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptco0(self) -> &'a mut crate::W { + self.variant(Ptco31::Ptco0) + } + #[doc = "Corresponding field in PDOR becomes 0"] + #[inline(always)] + pub fn ptco1(self) -> &'a mut crate::W { + self.variant(Ptco31::Ptco1) + } +} +impl R { + #[doc = "Bit 0 - Port Clear Output"] + #[inline(always)] + pub fn ptco0(&self) -> Ptco0R { + Ptco0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port Clear Output"] + #[inline(always)] + pub fn ptco1(&self) -> Ptco1R { + Ptco1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port Clear Output"] + #[inline(always)] + pub fn ptco2(&self) -> Ptco2R { + Ptco2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port Clear Output"] + #[inline(always)] + pub fn ptco3(&self) -> Ptco3R { + Ptco3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port Clear Output"] + #[inline(always)] + pub fn ptco4(&self) -> Ptco4R { + Ptco4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port Clear Output"] + #[inline(always)] + pub fn ptco5(&self) -> Ptco5R { + Ptco5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port Clear Output"] + #[inline(always)] + pub fn ptco6(&self) -> Ptco6R { + Ptco6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port Clear Output"] + #[inline(always)] + pub fn ptco7(&self) -> Ptco7R { + Ptco7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port Clear Output"] + #[inline(always)] + pub fn ptco8(&self) -> Ptco8R { + Ptco8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Port Clear Output"] + #[inline(always)] + pub fn ptco9(&self) -> Ptco9R { + Ptco9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Port Clear Output"] + #[inline(always)] + pub fn ptco10(&self) -> Ptco10R { + Ptco10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Port Clear Output"] + #[inline(always)] + pub fn ptco11(&self) -> Ptco11R { + Ptco11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Port Clear Output"] + #[inline(always)] + pub fn ptco12(&self) -> Ptco12R { + Ptco12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Port Clear Output"] + #[inline(always)] + pub fn ptco13(&self) -> Ptco13R { + Ptco13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Port Clear Output"] + #[inline(always)] + pub fn ptco14(&self) -> Ptco14R { + Ptco14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Clear Output"] + #[inline(always)] + pub fn ptco15(&self) -> Ptco15R { + Ptco15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Port Clear Output"] + #[inline(always)] + pub fn ptco16(&self) -> Ptco16R { + Ptco16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Port Clear Output"] + #[inline(always)] + pub fn ptco17(&self) -> Ptco17R { + Ptco17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Port Clear Output"] + #[inline(always)] + pub fn ptco18(&self) -> Ptco18R { + Ptco18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Port Clear Output"] + #[inline(always)] + pub fn ptco19(&self) -> Ptco19R { + Ptco19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Port Clear Output"] + #[inline(always)] + pub fn ptco20(&self) -> Ptco20R { + Ptco20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Port Clear Output"] + #[inline(always)] + pub fn ptco21(&self) -> Ptco21R { + Ptco21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Port Clear Output"] + #[inline(always)] + pub fn ptco22(&self) -> Ptco22R { + Ptco22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Port Clear Output"] + #[inline(always)] + pub fn ptco23(&self) -> Ptco23R { + Ptco23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Port Clear Output"] + #[inline(always)] + pub fn ptco24(&self) -> Ptco24R { + Ptco24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Port Clear Output"] + #[inline(always)] + pub fn ptco25(&self) -> Ptco25R { + Ptco25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Port Clear Output"] + #[inline(always)] + pub fn ptco26(&self) -> Ptco26R { + Ptco26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Port Clear Output"] + #[inline(always)] + pub fn ptco27(&self) -> Ptco27R { + Ptco27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Port Clear Output"] + #[inline(always)] + pub fn ptco28(&self) -> Ptco28R { + Ptco28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Port Clear Output"] + #[inline(always)] + pub fn ptco29(&self) -> Ptco29R { + Ptco29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Port Clear Output"] + #[inline(always)] + pub fn ptco30(&self) -> Ptco30R { + Ptco30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Port Clear Output"] + #[inline(always)] + pub fn ptco31(&self) -> Ptco31R { + Ptco31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Clear Output"] + #[inline(always)] + pub fn ptco0(&mut self) -> Ptco0W { + Ptco0W::new(self, 0) + } + #[doc = "Bit 1 - Port Clear Output"] + #[inline(always)] + pub fn ptco1(&mut self) -> Ptco1W { + Ptco1W::new(self, 1) + } + #[doc = "Bit 2 - Port Clear Output"] + #[inline(always)] + pub fn ptco2(&mut self) -> Ptco2W { + Ptco2W::new(self, 2) + } + #[doc = "Bit 3 - Port Clear Output"] + #[inline(always)] + pub fn ptco3(&mut self) -> Ptco3W { + Ptco3W::new(self, 3) + } + #[doc = "Bit 4 - Port Clear Output"] + #[inline(always)] + pub fn ptco4(&mut self) -> Ptco4W { + Ptco4W::new(self, 4) + } + #[doc = "Bit 5 - Port Clear Output"] + #[inline(always)] + pub fn ptco5(&mut self) -> Ptco5W { + Ptco5W::new(self, 5) + } + #[doc = "Bit 6 - Port Clear Output"] + #[inline(always)] + pub fn ptco6(&mut self) -> Ptco6W { + Ptco6W::new(self, 6) + } + #[doc = "Bit 7 - Port Clear Output"] + #[inline(always)] + pub fn ptco7(&mut self) -> Ptco7W { + Ptco7W::new(self, 7) + } + #[doc = "Bit 8 - Port Clear Output"] + #[inline(always)] + pub fn ptco8(&mut self) -> Ptco8W { + Ptco8W::new(self, 8) + } + #[doc = "Bit 9 - Port Clear Output"] + #[inline(always)] + pub fn ptco9(&mut self) -> Ptco9W { + Ptco9W::new(self, 9) + } + #[doc = "Bit 10 - Port Clear Output"] + #[inline(always)] + pub fn ptco10(&mut self) -> Ptco10W { + Ptco10W::new(self, 10) + } + #[doc = "Bit 11 - Port Clear Output"] + #[inline(always)] + pub fn ptco11(&mut self) -> Ptco11W { + Ptco11W::new(self, 11) + } + #[doc = "Bit 12 - Port Clear Output"] + #[inline(always)] + pub fn ptco12(&mut self) -> Ptco12W { + Ptco12W::new(self, 12) + } + #[doc = "Bit 13 - Port Clear Output"] + #[inline(always)] + pub fn ptco13(&mut self) -> Ptco13W { + Ptco13W::new(self, 13) + } + #[doc = "Bit 14 - Port Clear Output"] + #[inline(always)] + pub fn ptco14(&mut self) -> Ptco14W { + Ptco14W::new(self, 14) + } + #[doc = "Bit 15 - Port Clear Output"] + #[inline(always)] + pub fn ptco15(&mut self) -> Ptco15W { + Ptco15W::new(self, 15) + } + #[doc = "Bit 16 - Port Clear Output"] + #[inline(always)] + pub fn ptco16(&mut self) -> Ptco16W { + Ptco16W::new(self, 16) + } + #[doc = "Bit 17 - Port Clear Output"] + #[inline(always)] + pub fn ptco17(&mut self) -> Ptco17W { + Ptco17W::new(self, 17) + } + #[doc = "Bit 18 - Port Clear Output"] + #[inline(always)] + pub fn ptco18(&mut self) -> Ptco18W { + Ptco18W::new(self, 18) + } + #[doc = "Bit 19 - Port Clear Output"] + #[inline(always)] + pub fn ptco19(&mut self) -> Ptco19W { + Ptco19W::new(self, 19) + } + #[doc = "Bit 20 - Port Clear Output"] + #[inline(always)] + pub fn ptco20(&mut self) -> Ptco20W { + Ptco20W::new(self, 20) + } + #[doc = "Bit 21 - Port Clear Output"] + #[inline(always)] + pub fn ptco21(&mut self) -> Ptco21W { + Ptco21W::new(self, 21) + } + #[doc = "Bit 22 - Port Clear Output"] + #[inline(always)] + pub fn ptco22(&mut self) -> Ptco22W { + Ptco22W::new(self, 22) + } + #[doc = "Bit 23 - Port Clear Output"] + #[inline(always)] + pub fn ptco23(&mut self) -> Ptco23W { + Ptco23W::new(self, 23) + } + #[doc = "Bit 24 - Port Clear Output"] + #[inline(always)] + pub fn ptco24(&mut self) -> Ptco24W { + Ptco24W::new(self, 24) + } + #[doc = "Bit 25 - Port Clear Output"] + #[inline(always)] + pub fn ptco25(&mut self) -> Ptco25W { + Ptco25W::new(self, 25) + } + #[doc = "Bit 26 - Port Clear Output"] + #[inline(always)] + pub fn ptco26(&mut self) -> Ptco26W { + Ptco26W::new(self, 26) + } + #[doc = "Bit 27 - Port Clear Output"] + #[inline(always)] + pub fn ptco27(&mut self) -> Ptco27W { + Ptco27W::new(self, 27) + } + #[doc = "Bit 28 - Port Clear Output"] + #[inline(always)] + pub fn ptco28(&mut self) -> Ptco28W { + Ptco28W::new(self, 28) + } + #[doc = "Bit 29 - Port Clear Output"] + #[inline(always)] + pub fn ptco29(&mut self) -> Ptco29W { + Ptco29W::new(self, 29) + } + #[doc = "Bit 30 - Port Clear Output"] + #[inline(always)] + pub fn ptco30(&mut self) -> Ptco30W { + Ptco30W::new(self, 30) + } + #[doc = "Bit 31 - Port Clear Output"] + #[inline(always)] + pub fn ptco31(&mut self) -> Ptco31W { + Ptco31W::new(self, 31) + } +} +#[doc = "Port Clear Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pcor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PcorSpec; +impl crate::RegisterSpec for PcorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcor::R`](R) reader structure"] +impl crate::Readable for PcorSpec {} +#[doc = "`write(|w| ..)` method takes [`pcor::W`](W) writer structure"] +impl crate::Writable for PcorSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCOR to value 0"] +impl crate::Resettable for PcorSpec {} diff --git a/mcxa276-pac/src/gpio0/pddr.rs b/mcxa276-pac/src/gpio0/pddr.rs new file mode 100644 index 000000000..66008cdc6 --- /dev/null +++ b/mcxa276-pac/src/gpio0/pddr.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `PDDR` reader"] +pub type R = crate::R; +#[doc = "Register `PDDR` writer"] +pub type W = crate::W; +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd0 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD0` reader - Port Data Direction"] +pub type Pdd0R = crate::BitReader; +impl Pdd0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd0 { + match self.bits { + false => Pdd0::Pdd0, + true => Pdd0::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd0::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd0::Pdd1 + } +} +#[doc = "Field `PDD0` writer - Port Data Direction"] +pub type Pdd0W<'a, REG> = crate::BitWriter<'a, REG, Pdd0>; +impl<'a, REG> Pdd0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd0::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd0::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd1 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD1` reader - Port Data Direction"] +pub type Pdd1R = crate::BitReader; +impl Pdd1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd1 { + match self.bits { + false => Pdd1::Pdd0, + true => Pdd1::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd1::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd1::Pdd1 + } +} +#[doc = "Field `PDD1` writer - Port Data Direction"] +pub type Pdd1W<'a, REG> = crate::BitWriter<'a, REG, Pdd1>; +impl<'a, REG> Pdd1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd1::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd1::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd2 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD2` reader - Port Data Direction"] +pub type Pdd2R = crate::BitReader; +impl Pdd2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd2 { + match self.bits { + false => Pdd2::Pdd0, + true => Pdd2::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd2::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd2::Pdd1 + } +} +#[doc = "Field `PDD2` writer - Port Data Direction"] +pub type Pdd2W<'a, REG> = crate::BitWriter<'a, REG, Pdd2>; +impl<'a, REG> Pdd2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd2::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd2::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd3 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD3` reader - Port Data Direction"] +pub type Pdd3R = crate::BitReader; +impl Pdd3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd3 { + match self.bits { + false => Pdd3::Pdd0, + true => Pdd3::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd3::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd3::Pdd1 + } +} +#[doc = "Field `PDD3` writer - Port Data Direction"] +pub type Pdd3W<'a, REG> = crate::BitWriter<'a, REG, Pdd3>; +impl<'a, REG> Pdd3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd3::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd3::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd4 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD4` reader - Port Data Direction"] +pub type Pdd4R = crate::BitReader; +impl Pdd4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd4 { + match self.bits { + false => Pdd4::Pdd0, + true => Pdd4::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd4::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd4::Pdd1 + } +} +#[doc = "Field `PDD4` writer - Port Data Direction"] +pub type Pdd4W<'a, REG> = crate::BitWriter<'a, REG, Pdd4>; +impl<'a, REG> Pdd4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd4::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd4::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd5 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD5` reader - Port Data Direction"] +pub type Pdd5R = crate::BitReader; +impl Pdd5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd5 { + match self.bits { + false => Pdd5::Pdd0, + true => Pdd5::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd5::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd5::Pdd1 + } +} +#[doc = "Field `PDD5` writer - Port Data Direction"] +pub type Pdd5W<'a, REG> = crate::BitWriter<'a, REG, Pdd5>; +impl<'a, REG> Pdd5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd5::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd5::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd6 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD6` reader - Port Data Direction"] +pub type Pdd6R = crate::BitReader; +impl Pdd6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd6 { + match self.bits { + false => Pdd6::Pdd0, + true => Pdd6::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd6::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd6::Pdd1 + } +} +#[doc = "Field `PDD6` writer - Port Data Direction"] +pub type Pdd6W<'a, REG> = crate::BitWriter<'a, REG, Pdd6>; +impl<'a, REG> Pdd6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd6::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd6::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd7 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD7` reader - Port Data Direction"] +pub type Pdd7R = crate::BitReader; +impl Pdd7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd7 { + match self.bits { + false => Pdd7::Pdd0, + true => Pdd7::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd7::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd7::Pdd1 + } +} +#[doc = "Field `PDD7` writer - Port Data Direction"] +pub type Pdd7W<'a, REG> = crate::BitWriter<'a, REG, Pdd7>; +impl<'a, REG> Pdd7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd7::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd7::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd8 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD8` reader - Port Data Direction"] +pub type Pdd8R = crate::BitReader; +impl Pdd8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd8 { + match self.bits { + false => Pdd8::Pdd0, + true => Pdd8::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd8::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd8::Pdd1 + } +} +#[doc = "Field `PDD8` writer - Port Data Direction"] +pub type Pdd8W<'a, REG> = crate::BitWriter<'a, REG, Pdd8>; +impl<'a, REG> Pdd8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd8::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd8::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd9 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD9` reader - Port Data Direction"] +pub type Pdd9R = crate::BitReader; +impl Pdd9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd9 { + match self.bits { + false => Pdd9::Pdd0, + true => Pdd9::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd9::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd9::Pdd1 + } +} +#[doc = "Field `PDD9` writer - Port Data Direction"] +pub type Pdd9W<'a, REG> = crate::BitWriter<'a, REG, Pdd9>; +impl<'a, REG> Pdd9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd9::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd9::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd10 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD10` reader - Port Data Direction"] +pub type Pdd10R = crate::BitReader; +impl Pdd10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd10 { + match self.bits { + false => Pdd10::Pdd0, + true => Pdd10::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd10::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd10::Pdd1 + } +} +#[doc = "Field `PDD10` writer - Port Data Direction"] +pub type Pdd10W<'a, REG> = crate::BitWriter<'a, REG, Pdd10>; +impl<'a, REG> Pdd10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd10::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd10::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd11 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD11` reader - Port Data Direction"] +pub type Pdd11R = crate::BitReader; +impl Pdd11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd11 { + match self.bits { + false => Pdd11::Pdd0, + true => Pdd11::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd11::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd11::Pdd1 + } +} +#[doc = "Field `PDD11` writer - Port Data Direction"] +pub type Pdd11W<'a, REG> = crate::BitWriter<'a, REG, Pdd11>; +impl<'a, REG> Pdd11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd11::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd11::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd12 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD12` reader - Port Data Direction"] +pub type Pdd12R = crate::BitReader; +impl Pdd12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd12 { + match self.bits { + false => Pdd12::Pdd0, + true => Pdd12::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd12::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd12::Pdd1 + } +} +#[doc = "Field `PDD12` writer - Port Data Direction"] +pub type Pdd12W<'a, REG> = crate::BitWriter<'a, REG, Pdd12>; +impl<'a, REG> Pdd12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd12::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd12::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd13 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD13` reader - Port Data Direction"] +pub type Pdd13R = crate::BitReader; +impl Pdd13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd13 { + match self.bits { + false => Pdd13::Pdd0, + true => Pdd13::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd13::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd13::Pdd1 + } +} +#[doc = "Field `PDD13` writer - Port Data Direction"] +pub type Pdd13W<'a, REG> = crate::BitWriter<'a, REG, Pdd13>; +impl<'a, REG> Pdd13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd13::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd13::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd14 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD14` reader - Port Data Direction"] +pub type Pdd14R = crate::BitReader; +impl Pdd14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd14 { + match self.bits { + false => Pdd14::Pdd0, + true => Pdd14::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd14::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd14::Pdd1 + } +} +#[doc = "Field `PDD14` writer - Port Data Direction"] +pub type Pdd14W<'a, REG> = crate::BitWriter<'a, REG, Pdd14>; +impl<'a, REG> Pdd14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd14::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd14::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd15 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD15` reader - Port Data Direction"] +pub type Pdd15R = crate::BitReader; +impl Pdd15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd15 { + match self.bits { + false => Pdd15::Pdd0, + true => Pdd15::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd15::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd15::Pdd1 + } +} +#[doc = "Field `PDD15` writer - Port Data Direction"] +pub type Pdd15W<'a, REG> = crate::BitWriter<'a, REG, Pdd15>; +impl<'a, REG> Pdd15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd15::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd15::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd16 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD16` reader - Port Data Direction"] +pub type Pdd16R = crate::BitReader; +impl Pdd16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd16 { + match self.bits { + false => Pdd16::Pdd0, + true => Pdd16::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd16::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd16::Pdd1 + } +} +#[doc = "Field `PDD16` writer - Port Data Direction"] +pub type Pdd16W<'a, REG> = crate::BitWriter<'a, REG, Pdd16>; +impl<'a, REG> Pdd16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd16::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd16::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd17 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD17` reader - Port Data Direction"] +pub type Pdd17R = crate::BitReader; +impl Pdd17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd17 { + match self.bits { + false => Pdd17::Pdd0, + true => Pdd17::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd17::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd17::Pdd1 + } +} +#[doc = "Field `PDD17` writer - Port Data Direction"] +pub type Pdd17W<'a, REG> = crate::BitWriter<'a, REG, Pdd17>; +impl<'a, REG> Pdd17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd17::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd17::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd18 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD18` reader - Port Data Direction"] +pub type Pdd18R = crate::BitReader; +impl Pdd18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd18 { + match self.bits { + false => Pdd18::Pdd0, + true => Pdd18::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd18::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd18::Pdd1 + } +} +#[doc = "Field `PDD18` writer - Port Data Direction"] +pub type Pdd18W<'a, REG> = crate::BitWriter<'a, REG, Pdd18>; +impl<'a, REG> Pdd18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd18::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd18::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd19 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD19` reader - Port Data Direction"] +pub type Pdd19R = crate::BitReader; +impl Pdd19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd19 { + match self.bits { + false => Pdd19::Pdd0, + true => Pdd19::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd19::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd19::Pdd1 + } +} +#[doc = "Field `PDD19` writer - Port Data Direction"] +pub type Pdd19W<'a, REG> = crate::BitWriter<'a, REG, Pdd19>; +impl<'a, REG> Pdd19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd19::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd19::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd20 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD20` reader - Port Data Direction"] +pub type Pdd20R = crate::BitReader; +impl Pdd20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd20 { + match self.bits { + false => Pdd20::Pdd0, + true => Pdd20::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd20::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd20::Pdd1 + } +} +#[doc = "Field `PDD20` writer - Port Data Direction"] +pub type Pdd20W<'a, REG> = crate::BitWriter<'a, REG, Pdd20>; +impl<'a, REG> Pdd20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd20::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd20::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd21 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD21` reader - Port Data Direction"] +pub type Pdd21R = crate::BitReader; +impl Pdd21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd21 { + match self.bits { + false => Pdd21::Pdd0, + true => Pdd21::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd21::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd21::Pdd1 + } +} +#[doc = "Field `PDD21` writer - Port Data Direction"] +pub type Pdd21W<'a, REG> = crate::BitWriter<'a, REG, Pdd21>; +impl<'a, REG> Pdd21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd21::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd21::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd22 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD22` reader - Port Data Direction"] +pub type Pdd22R = crate::BitReader; +impl Pdd22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd22 { + match self.bits { + false => Pdd22::Pdd0, + true => Pdd22::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd22::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd22::Pdd1 + } +} +#[doc = "Field `PDD22` writer - Port Data Direction"] +pub type Pdd22W<'a, REG> = crate::BitWriter<'a, REG, Pdd22>; +impl<'a, REG> Pdd22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd22::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd22::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd23 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD23` reader - Port Data Direction"] +pub type Pdd23R = crate::BitReader; +impl Pdd23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd23 { + match self.bits { + false => Pdd23::Pdd0, + true => Pdd23::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd23::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd23::Pdd1 + } +} +#[doc = "Field `PDD23` writer - Port Data Direction"] +pub type Pdd23W<'a, REG> = crate::BitWriter<'a, REG, Pdd23>; +impl<'a, REG> Pdd23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd23::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd23::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd24 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD24` reader - Port Data Direction"] +pub type Pdd24R = crate::BitReader; +impl Pdd24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd24 { + match self.bits { + false => Pdd24::Pdd0, + true => Pdd24::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd24::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd24::Pdd1 + } +} +#[doc = "Field `PDD24` writer - Port Data Direction"] +pub type Pdd24W<'a, REG> = crate::BitWriter<'a, REG, Pdd24>; +impl<'a, REG> Pdd24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd24::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd24::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd25 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD25` reader - Port Data Direction"] +pub type Pdd25R = crate::BitReader; +impl Pdd25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd25 { + match self.bits { + false => Pdd25::Pdd0, + true => Pdd25::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd25::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd25::Pdd1 + } +} +#[doc = "Field `PDD25` writer - Port Data Direction"] +pub type Pdd25W<'a, REG> = crate::BitWriter<'a, REG, Pdd25>; +impl<'a, REG> Pdd25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd25::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd25::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd26 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD26` reader - Port Data Direction"] +pub type Pdd26R = crate::BitReader; +impl Pdd26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd26 { + match self.bits { + false => Pdd26::Pdd0, + true => Pdd26::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd26::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd26::Pdd1 + } +} +#[doc = "Field `PDD26` writer - Port Data Direction"] +pub type Pdd26W<'a, REG> = crate::BitWriter<'a, REG, Pdd26>; +impl<'a, REG> Pdd26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd26::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd26::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd27 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD27` reader - Port Data Direction"] +pub type Pdd27R = crate::BitReader; +impl Pdd27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd27 { + match self.bits { + false => Pdd27::Pdd0, + true => Pdd27::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd27::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd27::Pdd1 + } +} +#[doc = "Field `PDD27` writer - Port Data Direction"] +pub type Pdd27W<'a, REG> = crate::BitWriter<'a, REG, Pdd27>; +impl<'a, REG> Pdd27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd27::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd27::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd28 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD28` reader - Port Data Direction"] +pub type Pdd28R = crate::BitReader; +impl Pdd28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd28 { + match self.bits { + false => Pdd28::Pdd0, + true => Pdd28::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd28::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd28::Pdd1 + } +} +#[doc = "Field `PDD28` writer - Port Data Direction"] +pub type Pdd28W<'a, REG> = crate::BitWriter<'a, REG, Pdd28>; +impl<'a, REG> Pdd28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd28::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd28::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd29 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD29` reader - Port Data Direction"] +pub type Pdd29R = crate::BitReader; +impl Pdd29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd29 { + match self.bits { + false => Pdd29::Pdd0, + true => Pdd29::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd29::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd29::Pdd1 + } +} +#[doc = "Field `PDD29` writer - Port Data Direction"] +pub type Pdd29W<'a, REG> = crate::BitWriter<'a, REG, Pdd29>; +impl<'a, REG> Pdd29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd29::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd29::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd30 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD30` reader - Port Data Direction"] +pub type Pdd30R = crate::BitReader; +impl Pdd30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd30 { + match self.bits { + false => Pdd30::Pdd0, + true => Pdd30::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd30::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd30::Pdd1 + } +} +#[doc = "Field `PDD30` writer - Port Data Direction"] +pub type Pdd30W<'a, REG> = crate::BitWriter<'a, REG, Pdd30>; +impl<'a, REG> Pdd30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd30::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd30::Pdd1) + } +} +#[doc = "Port Data Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdd31 { + #[doc = "0: Input"] + Pdd0 = 0, + #[doc = "1: Output"] + Pdd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdd31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDD31` reader - Port Data Direction"] +pub type Pdd31R = crate::BitReader; +impl Pdd31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdd31 { + match self.bits { + false => Pdd31::Pdd0, + true => Pdd31::Pdd1, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_pdd0(&self) -> bool { + *self == Pdd31::Pdd0 + } + #[doc = "Output"] + #[inline(always)] + pub fn is_pdd1(&self) -> bool { + *self == Pdd31::Pdd1 + } +} +#[doc = "Field `PDD31` writer - Port Data Direction"] +pub type Pdd31W<'a, REG> = crate::BitWriter<'a, REG, Pdd31>; +impl<'a, REG> Pdd31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn pdd0(self) -> &'a mut crate::W { + self.variant(Pdd31::Pdd0) + } + #[doc = "Output"] + #[inline(always)] + pub fn pdd1(self) -> &'a mut crate::W { + self.variant(Pdd31::Pdd1) + } +} +impl R { + #[doc = "Bit 0 - Port Data Direction"] + #[inline(always)] + pub fn pdd0(&self) -> Pdd0R { + Pdd0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port Data Direction"] + #[inline(always)] + pub fn pdd1(&self) -> Pdd1R { + Pdd1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port Data Direction"] + #[inline(always)] + pub fn pdd2(&self) -> Pdd2R { + Pdd2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port Data Direction"] + #[inline(always)] + pub fn pdd3(&self) -> Pdd3R { + Pdd3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port Data Direction"] + #[inline(always)] + pub fn pdd4(&self) -> Pdd4R { + Pdd4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port Data Direction"] + #[inline(always)] + pub fn pdd5(&self) -> Pdd5R { + Pdd5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port Data Direction"] + #[inline(always)] + pub fn pdd6(&self) -> Pdd6R { + Pdd6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port Data Direction"] + #[inline(always)] + pub fn pdd7(&self) -> Pdd7R { + Pdd7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port Data Direction"] + #[inline(always)] + pub fn pdd8(&self) -> Pdd8R { + Pdd8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Port Data Direction"] + #[inline(always)] + pub fn pdd9(&self) -> Pdd9R { + Pdd9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Port Data Direction"] + #[inline(always)] + pub fn pdd10(&self) -> Pdd10R { + Pdd10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Port Data Direction"] + #[inline(always)] + pub fn pdd11(&self) -> Pdd11R { + Pdd11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Port Data Direction"] + #[inline(always)] + pub fn pdd12(&self) -> Pdd12R { + Pdd12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Port Data Direction"] + #[inline(always)] + pub fn pdd13(&self) -> Pdd13R { + Pdd13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Port Data Direction"] + #[inline(always)] + pub fn pdd14(&self) -> Pdd14R { + Pdd14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Data Direction"] + #[inline(always)] + pub fn pdd15(&self) -> Pdd15R { + Pdd15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Port Data Direction"] + #[inline(always)] + pub fn pdd16(&self) -> Pdd16R { + Pdd16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Port Data Direction"] + #[inline(always)] + pub fn pdd17(&self) -> Pdd17R { + Pdd17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Port Data Direction"] + #[inline(always)] + pub fn pdd18(&self) -> Pdd18R { + Pdd18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Port Data Direction"] + #[inline(always)] + pub fn pdd19(&self) -> Pdd19R { + Pdd19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Port Data Direction"] + #[inline(always)] + pub fn pdd20(&self) -> Pdd20R { + Pdd20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Port Data Direction"] + #[inline(always)] + pub fn pdd21(&self) -> Pdd21R { + Pdd21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Port Data Direction"] + #[inline(always)] + pub fn pdd22(&self) -> Pdd22R { + Pdd22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Port Data Direction"] + #[inline(always)] + pub fn pdd23(&self) -> Pdd23R { + Pdd23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Port Data Direction"] + #[inline(always)] + pub fn pdd24(&self) -> Pdd24R { + Pdd24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Port Data Direction"] + #[inline(always)] + pub fn pdd25(&self) -> Pdd25R { + Pdd25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Port Data Direction"] + #[inline(always)] + pub fn pdd26(&self) -> Pdd26R { + Pdd26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Port Data Direction"] + #[inline(always)] + pub fn pdd27(&self) -> Pdd27R { + Pdd27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Port Data Direction"] + #[inline(always)] + pub fn pdd28(&self) -> Pdd28R { + Pdd28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Port Data Direction"] + #[inline(always)] + pub fn pdd29(&self) -> Pdd29R { + Pdd29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Port Data Direction"] + #[inline(always)] + pub fn pdd30(&self) -> Pdd30R { + Pdd30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Port Data Direction"] + #[inline(always)] + pub fn pdd31(&self) -> Pdd31R { + Pdd31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Data Direction"] + #[inline(always)] + pub fn pdd0(&mut self) -> Pdd0W { + Pdd0W::new(self, 0) + } + #[doc = "Bit 1 - Port Data Direction"] + #[inline(always)] + pub fn pdd1(&mut self) -> Pdd1W { + Pdd1W::new(self, 1) + } + #[doc = "Bit 2 - Port Data Direction"] + #[inline(always)] + pub fn pdd2(&mut self) -> Pdd2W { + Pdd2W::new(self, 2) + } + #[doc = "Bit 3 - Port Data Direction"] + #[inline(always)] + pub fn pdd3(&mut self) -> Pdd3W { + Pdd3W::new(self, 3) + } + #[doc = "Bit 4 - Port Data Direction"] + #[inline(always)] + pub fn pdd4(&mut self) -> Pdd4W { + Pdd4W::new(self, 4) + } + #[doc = "Bit 5 - Port Data Direction"] + #[inline(always)] + pub fn pdd5(&mut self) -> Pdd5W { + Pdd5W::new(self, 5) + } + #[doc = "Bit 6 - Port Data Direction"] + #[inline(always)] + pub fn pdd6(&mut self) -> Pdd6W { + Pdd6W::new(self, 6) + } + #[doc = "Bit 7 - Port Data Direction"] + #[inline(always)] + pub fn pdd7(&mut self) -> Pdd7W { + Pdd7W::new(self, 7) + } + #[doc = "Bit 8 - Port Data Direction"] + #[inline(always)] + pub fn pdd8(&mut self) -> Pdd8W { + Pdd8W::new(self, 8) + } + #[doc = "Bit 9 - Port Data Direction"] + #[inline(always)] + pub fn pdd9(&mut self) -> Pdd9W { + Pdd9W::new(self, 9) + } + #[doc = "Bit 10 - Port Data Direction"] + #[inline(always)] + pub fn pdd10(&mut self) -> Pdd10W { + Pdd10W::new(self, 10) + } + #[doc = "Bit 11 - Port Data Direction"] + #[inline(always)] + pub fn pdd11(&mut self) -> Pdd11W { + Pdd11W::new(self, 11) + } + #[doc = "Bit 12 - Port Data Direction"] + #[inline(always)] + pub fn pdd12(&mut self) -> Pdd12W { + Pdd12W::new(self, 12) + } + #[doc = "Bit 13 - Port Data Direction"] + #[inline(always)] + pub fn pdd13(&mut self) -> Pdd13W { + Pdd13W::new(self, 13) + } + #[doc = "Bit 14 - Port Data Direction"] + #[inline(always)] + pub fn pdd14(&mut self) -> Pdd14W { + Pdd14W::new(self, 14) + } + #[doc = "Bit 15 - Port Data Direction"] + #[inline(always)] + pub fn pdd15(&mut self) -> Pdd15W { + Pdd15W::new(self, 15) + } + #[doc = "Bit 16 - Port Data Direction"] + #[inline(always)] + pub fn pdd16(&mut self) -> Pdd16W { + Pdd16W::new(self, 16) + } + #[doc = "Bit 17 - Port Data Direction"] + #[inline(always)] + pub fn pdd17(&mut self) -> Pdd17W { + Pdd17W::new(self, 17) + } + #[doc = "Bit 18 - Port Data Direction"] + #[inline(always)] + pub fn pdd18(&mut self) -> Pdd18W { + Pdd18W::new(self, 18) + } + #[doc = "Bit 19 - Port Data Direction"] + #[inline(always)] + pub fn pdd19(&mut self) -> Pdd19W { + Pdd19W::new(self, 19) + } + #[doc = "Bit 20 - Port Data Direction"] + #[inline(always)] + pub fn pdd20(&mut self) -> Pdd20W { + Pdd20W::new(self, 20) + } + #[doc = "Bit 21 - Port Data Direction"] + #[inline(always)] + pub fn pdd21(&mut self) -> Pdd21W { + Pdd21W::new(self, 21) + } + #[doc = "Bit 22 - Port Data Direction"] + #[inline(always)] + pub fn pdd22(&mut self) -> Pdd22W { + Pdd22W::new(self, 22) + } + #[doc = "Bit 23 - Port Data Direction"] + #[inline(always)] + pub fn pdd23(&mut self) -> Pdd23W { + Pdd23W::new(self, 23) + } + #[doc = "Bit 24 - Port Data Direction"] + #[inline(always)] + pub fn pdd24(&mut self) -> Pdd24W { + Pdd24W::new(self, 24) + } + #[doc = "Bit 25 - Port Data Direction"] + #[inline(always)] + pub fn pdd25(&mut self) -> Pdd25W { + Pdd25W::new(self, 25) + } + #[doc = "Bit 26 - Port Data Direction"] + #[inline(always)] + pub fn pdd26(&mut self) -> Pdd26W { + Pdd26W::new(self, 26) + } + #[doc = "Bit 27 - Port Data Direction"] + #[inline(always)] + pub fn pdd27(&mut self) -> Pdd27W { + Pdd27W::new(self, 27) + } + #[doc = "Bit 28 - Port Data Direction"] + #[inline(always)] + pub fn pdd28(&mut self) -> Pdd28W { + Pdd28W::new(self, 28) + } + #[doc = "Bit 29 - Port Data Direction"] + #[inline(always)] + pub fn pdd29(&mut self) -> Pdd29W { + Pdd29W::new(self, 29) + } + #[doc = "Bit 30 - Port Data Direction"] + #[inline(always)] + pub fn pdd30(&mut self) -> Pdd30W { + Pdd30W::new(self, 30) + } + #[doc = "Bit 31 - Port Data Direction"] + #[inline(always)] + pub fn pdd31(&mut self) -> Pdd31W { + Pdd31W::new(self, 31) + } +} +#[doc = "Port Data Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`pddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PddrSpec; +impl crate::RegisterSpec for PddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pddr::R`](R) reader structure"] +impl crate::Readable for PddrSpec {} +#[doc = "`write(|w| ..)` method takes [`pddr::W`](W) writer structure"] +impl crate::Writable for PddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PDDR to value 0"] +impl crate::Resettable for PddrSpec {} diff --git a/mcxa276-pac/src/gpio0/pdir.rs b/mcxa276-pac/src/gpio0/pdir.rs new file mode 100644 index 000000000..6064118c9 --- /dev/null +++ b/mcxa276-pac/src/gpio0/pdir.rs @@ -0,0 +1,1325 @@ +#[doc = "Register `PDIR` reader"] +pub type R = crate::R; +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi0 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI0` reader - Port Data Input"] +pub type Pdi0R = crate::BitReader; +impl Pdi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi0 { + match self.bits { + false => Pdi0::Pdi0, + true => Pdi0::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi0::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi0::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi1 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI1` reader - Port Data Input"] +pub type Pdi1R = crate::BitReader; +impl Pdi1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi1 { + match self.bits { + false => Pdi1::Pdi0, + true => Pdi1::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi1::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi1::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi2 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI2` reader - Port Data Input"] +pub type Pdi2R = crate::BitReader; +impl Pdi2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi2 { + match self.bits { + false => Pdi2::Pdi0, + true => Pdi2::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi2::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi2::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi3 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI3` reader - Port Data Input"] +pub type Pdi3R = crate::BitReader; +impl Pdi3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi3 { + match self.bits { + false => Pdi3::Pdi0, + true => Pdi3::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi3::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi3::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi4 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI4` reader - Port Data Input"] +pub type Pdi4R = crate::BitReader; +impl Pdi4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi4 { + match self.bits { + false => Pdi4::Pdi0, + true => Pdi4::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi4::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi4::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi5 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI5` reader - Port Data Input"] +pub type Pdi5R = crate::BitReader; +impl Pdi5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi5 { + match self.bits { + false => Pdi5::Pdi0, + true => Pdi5::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi5::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi5::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi6 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI6` reader - Port Data Input"] +pub type Pdi6R = crate::BitReader; +impl Pdi6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi6 { + match self.bits { + false => Pdi6::Pdi0, + true => Pdi6::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi6::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi6::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi7 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI7` reader - Port Data Input"] +pub type Pdi7R = crate::BitReader; +impl Pdi7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi7 { + match self.bits { + false => Pdi7::Pdi0, + true => Pdi7::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi7::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi7::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi8 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI8` reader - Port Data Input"] +pub type Pdi8R = crate::BitReader; +impl Pdi8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi8 { + match self.bits { + false => Pdi8::Pdi0, + true => Pdi8::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi8::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi8::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi9 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI9` reader - Port Data Input"] +pub type Pdi9R = crate::BitReader; +impl Pdi9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi9 { + match self.bits { + false => Pdi9::Pdi0, + true => Pdi9::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi9::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi9::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi10 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI10` reader - Port Data Input"] +pub type Pdi10R = crate::BitReader; +impl Pdi10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi10 { + match self.bits { + false => Pdi10::Pdi0, + true => Pdi10::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi10::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi10::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi11 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI11` reader - Port Data Input"] +pub type Pdi11R = crate::BitReader; +impl Pdi11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi11 { + match self.bits { + false => Pdi11::Pdi0, + true => Pdi11::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi11::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi11::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi12 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI12` reader - Port Data Input"] +pub type Pdi12R = crate::BitReader; +impl Pdi12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi12 { + match self.bits { + false => Pdi12::Pdi0, + true => Pdi12::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi12::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi12::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi13 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI13` reader - Port Data Input"] +pub type Pdi13R = crate::BitReader; +impl Pdi13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi13 { + match self.bits { + false => Pdi13::Pdi0, + true => Pdi13::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi13::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi13::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi14 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI14` reader - Port Data Input"] +pub type Pdi14R = crate::BitReader; +impl Pdi14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi14 { + match self.bits { + false => Pdi14::Pdi0, + true => Pdi14::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi14::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi14::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi15 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI15` reader - Port Data Input"] +pub type Pdi15R = crate::BitReader; +impl Pdi15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi15 { + match self.bits { + false => Pdi15::Pdi0, + true => Pdi15::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi15::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi15::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi16 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI16` reader - Port Data Input"] +pub type Pdi16R = crate::BitReader; +impl Pdi16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi16 { + match self.bits { + false => Pdi16::Pdi0, + true => Pdi16::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi16::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi16::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi17 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI17` reader - Port Data Input"] +pub type Pdi17R = crate::BitReader; +impl Pdi17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi17 { + match self.bits { + false => Pdi17::Pdi0, + true => Pdi17::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi17::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi17::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi18 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI18` reader - Port Data Input"] +pub type Pdi18R = crate::BitReader; +impl Pdi18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi18 { + match self.bits { + false => Pdi18::Pdi0, + true => Pdi18::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi18::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi18::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi19 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI19` reader - Port Data Input"] +pub type Pdi19R = crate::BitReader; +impl Pdi19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi19 { + match self.bits { + false => Pdi19::Pdi0, + true => Pdi19::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi19::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi19::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi20 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI20` reader - Port Data Input"] +pub type Pdi20R = crate::BitReader; +impl Pdi20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi20 { + match self.bits { + false => Pdi20::Pdi0, + true => Pdi20::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi20::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi20::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi21 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI21` reader - Port Data Input"] +pub type Pdi21R = crate::BitReader; +impl Pdi21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi21 { + match self.bits { + false => Pdi21::Pdi0, + true => Pdi21::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi21::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi21::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi22 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI22` reader - Port Data Input"] +pub type Pdi22R = crate::BitReader; +impl Pdi22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi22 { + match self.bits { + false => Pdi22::Pdi0, + true => Pdi22::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi22::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi22::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi23 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI23` reader - Port Data Input"] +pub type Pdi23R = crate::BitReader; +impl Pdi23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi23 { + match self.bits { + false => Pdi23::Pdi0, + true => Pdi23::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi23::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi23::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi24 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI24` reader - Port Data Input"] +pub type Pdi24R = crate::BitReader; +impl Pdi24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi24 { + match self.bits { + false => Pdi24::Pdi0, + true => Pdi24::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi24::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi24::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi25 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI25` reader - Port Data Input"] +pub type Pdi25R = crate::BitReader; +impl Pdi25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi25 { + match self.bits { + false => Pdi25::Pdi0, + true => Pdi25::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi25::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi25::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi26 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI26` reader - Port Data Input"] +pub type Pdi26R = crate::BitReader; +impl Pdi26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi26 { + match self.bits { + false => Pdi26::Pdi0, + true => Pdi26::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi26::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi26::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi27 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI27` reader - Port Data Input"] +pub type Pdi27R = crate::BitReader; +impl Pdi27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi27 { + match self.bits { + false => Pdi27::Pdi0, + true => Pdi27::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi27::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi27::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi28 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI28` reader - Port Data Input"] +pub type Pdi28R = crate::BitReader; +impl Pdi28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi28 { + match self.bits { + false => Pdi28::Pdi0, + true => Pdi28::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi28::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi28::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi29 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI29` reader - Port Data Input"] +pub type Pdi29R = crate::BitReader; +impl Pdi29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi29 { + match self.bits { + false => Pdi29::Pdi0, + true => Pdi29::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi29::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi29::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi30 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI30` reader - Port Data Input"] +pub type Pdi30R = crate::BitReader; +impl Pdi30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi30 { + match self.bits { + false => Pdi30::Pdi0, + true => Pdi30::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi30::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi30::Pdi1 + } +} +#[doc = "Port Data Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdi31 { + #[doc = "0: Logic 0"] + Pdi0 = 0, + #[doc = "1: Logic 1"] + Pdi1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdi31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDI31` reader - Port Data Input"] +pub type Pdi31R = crate::BitReader; +impl Pdi31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdi31 { + match self.bits { + false => Pdi31::Pdi0, + true => Pdi31::Pdi1, + } + } + #[doc = "Logic 0"] + #[inline(always)] + pub fn is_pdi0(&self) -> bool { + *self == Pdi31::Pdi0 + } + #[doc = "Logic 1"] + #[inline(always)] + pub fn is_pdi1(&self) -> bool { + *self == Pdi31::Pdi1 + } +} +impl R { + #[doc = "Bit 0 - Port Data Input"] + #[inline(always)] + pub fn pdi0(&self) -> Pdi0R { + Pdi0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port Data Input"] + #[inline(always)] + pub fn pdi1(&self) -> Pdi1R { + Pdi1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port Data Input"] + #[inline(always)] + pub fn pdi2(&self) -> Pdi2R { + Pdi2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port Data Input"] + #[inline(always)] + pub fn pdi3(&self) -> Pdi3R { + Pdi3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port Data Input"] + #[inline(always)] + pub fn pdi4(&self) -> Pdi4R { + Pdi4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port Data Input"] + #[inline(always)] + pub fn pdi5(&self) -> Pdi5R { + Pdi5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port Data Input"] + #[inline(always)] + pub fn pdi6(&self) -> Pdi6R { + Pdi6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port Data Input"] + #[inline(always)] + pub fn pdi7(&self) -> Pdi7R { + Pdi7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port Data Input"] + #[inline(always)] + pub fn pdi8(&self) -> Pdi8R { + Pdi8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Port Data Input"] + #[inline(always)] + pub fn pdi9(&self) -> Pdi9R { + Pdi9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Port Data Input"] + #[inline(always)] + pub fn pdi10(&self) -> Pdi10R { + Pdi10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Port Data Input"] + #[inline(always)] + pub fn pdi11(&self) -> Pdi11R { + Pdi11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Port Data Input"] + #[inline(always)] + pub fn pdi12(&self) -> Pdi12R { + Pdi12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Port Data Input"] + #[inline(always)] + pub fn pdi13(&self) -> Pdi13R { + Pdi13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Port Data Input"] + #[inline(always)] + pub fn pdi14(&self) -> Pdi14R { + Pdi14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Data Input"] + #[inline(always)] + pub fn pdi15(&self) -> Pdi15R { + Pdi15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Port Data Input"] + #[inline(always)] + pub fn pdi16(&self) -> Pdi16R { + Pdi16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Port Data Input"] + #[inline(always)] + pub fn pdi17(&self) -> Pdi17R { + Pdi17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Port Data Input"] + #[inline(always)] + pub fn pdi18(&self) -> Pdi18R { + Pdi18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Port Data Input"] + #[inline(always)] + pub fn pdi19(&self) -> Pdi19R { + Pdi19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Port Data Input"] + #[inline(always)] + pub fn pdi20(&self) -> Pdi20R { + Pdi20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Port Data Input"] + #[inline(always)] + pub fn pdi21(&self) -> Pdi21R { + Pdi21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Port Data Input"] + #[inline(always)] + pub fn pdi22(&self) -> Pdi22R { + Pdi22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Port Data Input"] + #[inline(always)] + pub fn pdi23(&self) -> Pdi23R { + Pdi23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Port Data Input"] + #[inline(always)] + pub fn pdi24(&self) -> Pdi24R { + Pdi24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Port Data Input"] + #[inline(always)] + pub fn pdi25(&self) -> Pdi25R { + Pdi25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Port Data Input"] + #[inline(always)] + pub fn pdi26(&self) -> Pdi26R { + Pdi26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Port Data Input"] + #[inline(always)] + pub fn pdi27(&self) -> Pdi27R { + Pdi27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Port Data Input"] + #[inline(always)] + pub fn pdi28(&self) -> Pdi28R { + Pdi28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Port Data Input"] + #[inline(always)] + pub fn pdi29(&self) -> Pdi29R { + Pdi29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Port Data Input"] + #[inline(always)] + pub fn pdi30(&self) -> Pdi30R { + Pdi30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Port Data Input"] + #[inline(always)] + pub fn pdi31(&self) -> Pdi31R { + Pdi31R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Port Data Input\n\nYou can [`read`](crate::Reg::read) this register and get [`pdir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PdirSpec; +impl crate::RegisterSpec for PdirSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdir::R`](R) reader structure"] +impl crate::Readable for PdirSpec {} +#[doc = "`reset()` method sets PDIR to value 0"] +impl crate::Resettable for PdirSpec {} diff --git a/mcxa276-pac/src/gpio0/pdor.rs b/mcxa276-pac/src/gpio0/pdor.rs new file mode 100644 index 000000000..c1aa0b516 --- /dev/null +++ b/mcxa276-pac/src/gpio0/pdor.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `PDOR` reader"] +pub type R = crate::R; +#[doc = "Register `PDOR` writer"] +pub type W = crate::W; +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo0 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO0` reader - Port Data Output"] +pub type Pdo0R = crate::BitReader; +impl Pdo0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo0 { + match self.bits { + false => Pdo0::Pdo0, + true => Pdo0::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo0::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo0::Pdo1 + } +} +#[doc = "Field `PDO0` writer - Port Data Output"] +pub type Pdo0W<'a, REG> = crate::BitWriter<'a, REG, Pdo0>; +impl<'a, REG> Pdo0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo0::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo0::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo1 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO1` reader - Port Data Output"] +pub type Pdo1R = crate::BitReader; +impl Pdo1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo1 { + match self.bits { + false => Pdo1::Pdo0, + true => Pdo1::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo1::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo1::Pdo1 + } +} +#[doc = "Field `PDO1` writer - Port Data Output"] +pub type Pdo1W<'a, REG> = crate::BitWriter<'a, REG, Pdo1>; +impl<'a, REG> Pdo1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo1::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo1::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo2 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO2` reader - Port Data Output"] +pub type Pdo2R = crate::BitReader; +impl Pdo2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo2 { + match self.bits { + false => Pdo2::Pdo0, + true => Pdo2::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo2::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo2::Pdo1 + } +} +#[doc = "Field `PDO2` writer - Port Data Output"] +pub type Pdo2W<'a, REG> = crate::BitWriter<'a, REG, Pdo2>; +impl<'a, REG> Pdo2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo2::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo2::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo3 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO3` reader - Port Data Output"] +pub type Pdo3R = crate::BitReader; +impl Pdo3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo3 { + match self.bits { + false => Pdo3::Pdo0, + true => Pdo3::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo3::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo3::Pdo1 + } +} +#[doc = "Field `PDO3` writer - Port Data Output"] +pub type Pdo3W<'a, REG> = crate::BitWriter<'a, REG, Pdo3>; +impl<'a, REG> Pdo3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo3::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo3::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo4 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO4` reader - Port Data Output"] +pub type Pdo4R = crate::BitReader; +impl Pdo4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo4 { + match self.bits { + false => Pdo4::Pdo0, + true => Pdo4::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo4::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo4::Pdo1 + } +} +#[doc = "Field `PDO4` writer - Port Data Output"] +pub type Pdo4W<'a, REG> = crate::BitWriter<'a, REG, Pdo4>; +impl<'a, REG> Pdo4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo4::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo4::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo5 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO5` reader - Port Data Output"] +pub type Pdo5R = crate::BitReader; +impl Pdo5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo5 { + match self.bits { + false => Pdo5::Pdo0, + true => Pdo5::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo5::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo5::Pdo1 + } +} +#[doc = "Field `PDO5` writer - Port Data Output"] +pub type Pdo5W<'a, REG> = crate::BitWriter<'a, REG, Pdo5>; +impl<'a, REG> Pdo5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo5::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo5::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo6 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO6` reader - Port Data Output"] +pub type Pdo6R = crate::BitReader; +impl Pdo6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo6 { + match self.bits { + false => Pdo6::Pdo0, + true => Pdo6::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo6::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo6::Pdo1 + } +} +#[doc = "Field `PDO6` writer - Port Data Output"] +pub type Pdo6W<'a, REG> = crate::BitWriter<'a, REG, Pdo6>; +impl<'a, REG> Pdo6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo6::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo6::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo7 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO7` reader - Port Data Output"] +pub type Pdo7R = crate::BitReader; +impl Pdo7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo7 { + match self.bits { + false => Pdo7::Pdo0, + true => Pdo7::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo7::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo7::Pdo1 + } +} +#[doc = "Field `PDO7` writer - Port Data Output"] +pub type Pdo7W<'a, REG> = crate::BitWriter<'a, REG, Pdo7>; +impl<'a, REG> Pdo7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo7::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo7::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo8 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO8` reader - Port Data Output"] +pub type Pdo8R = crate::BitReader; +impl Pdo8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo8 { + match self.bits { + false => Pdo8::Pdo0, + true => Pdo8::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo8::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo8::Pdo1 + } +} +#[doc = "Field `PDO8` writer - Port Data Output"] +pub type Pdo8W<'a, REG> = crate::BitWriter<'a, REG, Pdo8>; +impl<'a, REG> Pdo8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo8::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo8::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo9 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO9` reader - Port Data Output"] +pub type Pdo9R = crate::BitReader; +impl Pdo9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo9 { + match self.bits { + false => Pdo9::Pdo0, + true => Pdo9::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo9::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo9::Pdo1 + } +} +#[doc = "Field `PDO9` writer - Port Data Output"] +pub type Pdo9W<'a, REG> = crate::BitWriter<'a, REG, Pdo9>; +impl<'a, REG> Pdo9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo9::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo9::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo10 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO10` reader - Port Data Output"] +pub type Pdo10R = crate::BitReader; +impl Pdo10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo10 { + match self.bits { + false => Pdo10::Pdo0, + true => Pdo10::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo10::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo10::Pdo1 + } +} +#[doc = "Field `PDO10` writer - Port Data Output"] +pub type Pdo10W<'a, REG> = crate::BitWriter<'a, REG, Pdo10>; +impl<'a, REG> Pdo10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo10::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo10::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo11 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO11` reader - Port Data Output"] +pub type Pdo11R = crate::BitReader; +impl Pdo11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo11 { + match self.bits { + false => Pdo11::Pdo0, + true => Pdo11::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo11::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo11::Pdo1 + } +} +#[doc = "Field `PDO11` writer - Port Data Output"] +pub type Pdo11W<'a, REG> = crate::BitWriter<'a, REG, Pdo11>; +impl<'a, REG> Pdo11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo11::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo11::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo12 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO12` reader - Port Data Output"] +pub type Pdo12R = crate::BitReader; +impl Pdo12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo12 { + match self.bits { + false => Pdo12::Pdo0, + true => Pdo12::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo12::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo12::Pdo1 + } +} +#[doc = "Field `PDO12` writer - Port Data Output"] +pub type Pdo12W<'a, REG> = crate::BitWriter<'a, REG, Pdo12>; +impl<'a, REG> Pdo12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo12::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo12::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo13 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO13` reader - Port Data Output"] +pub type Pdo13R = crate::BitReader; +impl Pdo13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo13 { + match self.bits { + false => Pdo13::Pdo0, + true => Pdo13::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo13::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo13::Pdo1 + } +} +#[doc = "Field `PDO13` writer - Port Data Output"] +pub type Pdo13W<'a, REG> = crate::BitWriter<'a, REG, Pdo13>; +impl<'a, REG> Pdo13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo13::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo13::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo14 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO14` reader - Port Data Output"] +pub type Pdo14R = crate::BitReader; +impl Pdo14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo14 { + match self.bits { + false => Pdo14::Pdo0, + true => Pdo14::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo14::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo14::Pdo1 + } +} +#[doc = "Field `PDO14` writer - Port Data Output"] +pub type Pdo14W<'a, REG> = crate::BitWriter<'a, REG, Pdo14>; +impl<'a, REG> Pdo14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo14::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo14::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo15 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO15` reader - Port Data Output"] +pub type Pdo15R = crate::BitReader; +impl Pdo15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo15 { + match self.bits { + false => Pdo15::Pdo0, + true => Pdo15::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo15::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo15::Pdo1 + } +} +#[doc = "Field `PDO15` writer - Port Data Output"] +pub type Pdo15W<'a, REG> = crate::BitWriter<'a, REG, Pdo15>; +impl<'a, REG> Pdo15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo15::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo15::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo16 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO16` reader - Port Data Output"] +pub type Pdo16R = crate::BitReader; +impl Pdo16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo16 { + match self.bits { + false => Pdo16::Pdo0, + true => Pdo16::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo16::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo16::Pdo1 + } +} +#[doc = "Field `PDO16` writer - Port Data Output"] +pub type Pdo16W<'a, REG> = crate::BitWriter<'a, REG, Pdo16>; +impl<'a, REG> Pdo16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo16::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo16::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo17 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO17` reader - Port Data Output"] +pub type Pdo17R = crate::BitReader; +impl Pdo17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo17 { + match self.bits { + false => Pdo17::Pdo0, + true => Pdo17::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo17::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo17::Pdo1 + } +} +#[doc = "Field `PDO17` writer - Port Data Output"] +pub type Pdo17W<'a, REG> = crate::BitWriter<'a, REG, Pdo17>; +impl<'a, REG> Pdo17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo17::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo17::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo18 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO18` reader - Port Data Output"] +pub type Pdo18R = crate::BitReader; +impl Pdo18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo18 { + match self.bits { + false => Pdo18::Pdo0, + true => Pdo18::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo18::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo18::Pdo1 + } +} +#[doc = "Field `PDO18` writer - Port Data Output"] +pub type Pdo18W<'a, REG> = crate::BitWriter<'a, REG, Pdo18>; +impl<'a, REG> Pdo18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo18::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo18::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo19 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO19` reader - Port Data Output"] +pub type Pdo19R = crate::BitReader; +impl Pdo19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo19 { + match self.bits { + false => Pdo19::Pdo0, + true => Pdo19::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo19::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo19::Pdo1 + } +} +#[doc = "Field `PDO19` writer - Port Data Output"] +pub type Pdo19W<'a, REG> = crate::BitWriter<'a, REG, Pdo19>; +impl<'a, REG> Pdo19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo19::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo19::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo20 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO20` reader - Port Data Output"] +pub type Pdo20R = crate::BitReader; +impl Pdo20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo20 { + match self.bits { + false => Pdo20::Pdo0, + true => Pdo20::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo20::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo20::Pdo1 + } +} +#[doc = "Field `PDO20` writer - Port Data Output"] +pub type Pdo20W<'a, REG> = crate::BitWriter<'a, REG, Pdo20>; +impl<'a, REG> Pdo20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo20::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo20::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo21 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO21` reader - Port Data Output"] +pub type Pdo21R = crate::BitReader; +impl Pdo21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo21 { + match self.bits { + false => Pdo21::Pdo0, + true => Pdo21::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo21::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo21::Pdo1 + } +} +#[doc = "Field `PDO21` writer - Port Data Output"] +pub type Pdo21W<'a, REG> = crate::BitWriter<'a, REG, Pdo21>; +impl<'a, REG> Pdo21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo21::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo21::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo22 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO22` reader - Port Data Output"] +pub type Pdo22R = crate::BitReader; +impl Pdo22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo22 { + match self.bits { + false => Pdo22::Pdo0, + true => Pdo22::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo22::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo22::Pdo1 + } +} +#[doc = "Field `PDO22` writer - Port Data Output"] +pub type Pdo22W<'a, REG> = crate::BitWriter<'a, REG, Pdo22>; +impl<'a, REG> Pdo22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo22::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo22::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo23 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO23` reader - Port Data Output"] +pub type Pdo23R = crate::BitReader; +impl Pdo23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo23 { + match self.bits { + false => Pdo23::Pdo0, + true => Pdo23::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo23::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo23::Pdo1 + } +} +#[doc = "Field `PDO23` writer - Port Data Output"] +pub type Pdo23W<'a, REG> = crate::BitWriter<'a, REG, Pdo23>; +impl<'a, REG> Pdo23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo23::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo23::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo24 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO24` reader - Port Data Output"] +pub type Pdo24R = crate::BitReader; +impl Pdo24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo24 { + match self.bits { + false => Pdo24::Pdo0, + true => Pdo24::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo24::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo24::Pdo1 + } +} +#[doc = "Field `PDO24` writer - Port Data Output"] +pub type Pdo24W<'a, REG> = crate::BitWriter<'a, REG, Pdo24>; +impl<'a, REG> Pdo24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo24::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo24::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo25 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO25` reader - Port Data Output"] +pub type Pdo25R = crate::BitReader; +impl Pdo25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo25 { + match self.bits { + false => Pdo25::Pdo0, + true => Pdo25::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo25::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo25::Pdo1 + } +} +#[doc = "Field `PDO25` writer - Port Data Output"] +pub type Pdo25W<'a, REG> = crate::BitWriter<'a, REG, Pdo25>; +impl<'a, REG> Pdo25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo25::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo25::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo26 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO26` reader - Port Data Output"] +pub type Pdo26R = crate::BitReader; +impl Pdo26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo26 { + match self.bits { + false => Pdo26::Pdo0, + true => Pdo26::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo26::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo26::Pdo1 + } +} +#[doc = "Field `PDO26` writer - Port Data Output"] +pub type Pdo26W<'a, REG> = crate::BitWriter<'a, REG, Pdo26>; +impl<'a, REG> Pdo26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo26::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo26::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo27 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO27` reader - Port Data Output"] +pub type Pdo27R = crate::BitReader; +impl Pdo27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo27 { + match self.bits { + false => Pdo27::Pdo0, + true => Pdo27::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo27::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo27::Pdo1 + } +} +#[doc = "Field `PDO27` writer - Port Data Output"] +pub type Pdo27W<'a, REG> = crate::BitWriter<'a, REG, Pdo27>; +impl<'a, REG> Pdo27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo27::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo27::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo28 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO28` reader - Port Data Output"] +pub type Pdo28R = crate::BitReader; +impl Pdo28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo28 { + match self.bits { + false => Pdo28::Pdo0, + true => Pdo28::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo28::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo28::Pdo1 + } +} +#[doc = "Field `PDO28` writer - Port Data Output"] +pub type Pdo28W<'a, REG> = crate::BitWriter<'a, REG, Pdo28>; +impl<'a, REG> Pdo28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo28::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo28::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo29 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO29` reader - Port Data Output"] +pub type Pdo29R = crate::BitReader; +impl Pdo29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo29 { + match self.bits { + false => Pdo29::Pdo0, + true => Pdo29::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo29::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo29::Pdo1 + } +} +#[doc = "Field `PDO29` writer - Port Data Output"] +pub type Pdo29W<'a, REG> = crate::BitWriter<'a, REG, Pdo29>; +impl<'a, REG> Pdo29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo29::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo29::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo30 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO30` reader - Port Data Output"] +pub type Pdo30R = crate::BitReader; +impl Pdo30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo30 { + match self.bits { + false => Pdo30::Pdo0, + true => Pdo30::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo30::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo30::Pdo1 + } +} +#[doc = "Field `PDO30` writer - Port Data Output"] +pub type Pdo30W<'a, REG> = crate::BitWriter<'a, REG, Pdo30>; +impl<'a, REG> Pdo30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo30::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo30::Pdo1) + } +} +#[doc = "Port Data Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdo31 { + #[doc = "0: Logic level 0"] + Pdo0 = 0, + #[doc = "1: Logic level 1"] + Pdo1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdo31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDO31` reader - Port Data Output"] +pub type Pdo31R = crate::BitReader; +impl Pdo31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdo31 { + match self.bits { + false => Pdo31::Pdo0, + true => Pdo31::Pdo1, + } + } + #[doc = "Logic level 0"] + #[inline(always)] + pub fn is_pdo0(&self) -> bool { + *self == Pdo31::Pdo0 + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn is_pdo1(&self) -> bool { + *self == Pdo31::Pdo1 + } +} +#[doc = "Field `PDO31` writer - Port Data Output"] +pub type Pdo31W<'a, REG> = crate::BitWriter<'a, REG, Pdo31>; +impl<'a, REG> Pdo31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic level 0"] + #[inline(always)] + pub fn pdo0(self) -> &'a mut crate::W { + self.variant(Pdo31::Pdo0) + } + #[doc = "Logic level 1"] + #[inline(always)] + pub fn pdo1(self) -> &'a mut crate::W { + self.variant(Pdo31::Pdo1) + } +} +impl R { + #[doc = "Bit 0 - Port Data Output"] + #[inline(always)] + pub fn pdo0(&self) -> Pdo0R { + Pdo0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port Data Output"] + #[inline(always)] + pub fn pdo1(&self) -> Pdo1R { + Pdo1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port Data Output"] + #[inline(always)] + pub fn pdo2(&self) -> Pdo2R { + Pdo2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port Data Output"] + #[inline(always)] + pub fn pdo3(&self) -> Pdo3R { + Pdo3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port Data Output"] + #[inline(always)] + pub fn pdo4(&self) -> Pdo4R { + Pdo4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port Data Output"] + #[inline(always)] + pub fn pdo5(&self) -> Pdo5R { + Pdo5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port Data Output"] + #[inline(always)] + pub fn pdo6(&self) -> Pdo6R { + Pdo6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port Data Output"] + #[inline(always)] + pub fn pdo7(&self) -> Pdo7R { + Pdo7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port Data Output"] + #[inline(always)] + pub fn pdo8(&self) -> Pdo8R { + Pdo8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Port Data Output"] + #[inline(always)] + pub fn pdo9(&self) -> Pdo9R { + Pdo9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Port Data Output"] + #[inline(always)] + pub fn pdo10(&self) -> Pdo10R { + Pdo10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Port Data Output"] + #[inline(always)] + pub fn pdo11(&self) -> Pdo11R { + Pdo11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Port Data Output"] + #[inline(always)] + pub fn pdo12(&self) -> Pdo12R { + Pdo12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Port Data Output"] + #[inline(always)] + pub fn pdo13(&self) -> Pdo13R { + Pdo13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Port Data Output"] + #[inline(always)] + pub fn pdo14(&self) -> Pdo14R { + Pdo14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Data Output"] + #[inline(always)] + pub fn pdo15(&self) -> Pdo15R { + Pdo15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Port Data Output"] + #[inline(always)] + pub fn pdo16(&self) -> Pdo16R { + Pdo16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Port Data Output"] + #[inline(always)] + pub fn pdo17(&self) -> Pdo17R { + Pdo17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Port Data Output"] + #[inline(always)] + pub fn pdo18(&self) -> Pdo18R { + Pdo18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Port Data Output"] + #[inline(always)] + pub fn pdo19(&self) -> Pdo19R { + Pdo19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Port Data Output"] + #[inline(always)] + pub fn pdo20(&self) -> Pdo20R { + Pdo20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Port Data Output"] + #[inline(always)] + pub fn pdo21(&self) -> Pdo21R { + Pdo21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Port Data Output"] + #[inline(always)] + pub fn pdo22(&self) -> Pdo22R { + Pdo22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Port Data Output"] + #[inline(always)] + pub fn pdo23(&self) -> Pdo23R { + Pdo23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Port Data Output"] + #[inline(always)] + pub fn pdo24(&self) -> Pdo24R { + Pdo24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Port Data Output"] + #[inline(always)] + pub fn pdo25(&self) -> Pdo25R { + Pdo25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Port Data Output"] + #[inline(always)] + pub fn pdo26(&self) -> Pdo26R { + Pdo26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Port Data Output"] + #[inline(always)] + pub fn pdo27(&self) -> Pdo27R { + Pdo27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Port Data Output"] + #[inline(always)] + pub fn pdo28(&self) -> Pdo28R { + Pdo28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Port Data Output"] + #[inline(always)] + pub fn pdo29(&self) -> Pdo29R { + Pdo29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Port Data Output"] + #[inline(always)] + pub fn pdo30(&self) -> Pdo30R { + Pdo30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Port Data Output"] + #[inline(always)] + pub fn pdo31(&self) -> Pdo31R { + Pdo31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Data Output"] + #[inline(always)] + pub fn pdo0(&mut self) -> Pdo0W { + Pdo0W::new(self, 0) + } + #[doc = "Bit 1 - Port Data Output"] + #[inline(always)] + pub fn pdo1(&mut self) -> Pdo1W { + Pdo1W::new(self, 1) + } + #[doc = "Bit 2 - Port Data Output"] + #[inline(always)] + pub fn pdo2(&mut self) -> Pdo2W { + Pdo2W::new(self, 2) + } + #[doc = "Bit 3 - Port Data Output"] + #[inline(always)] + pub fn pdo3(&mut self) -> Pdo3W { + Pdo3W::new(self, 3) + } + #[doc = "Bit 4 - Port Data Output"] + #[inline(always)] + pub fn pdo4(&mut self) -> Pdo4W { + Pdo4W::new(self, 4) + } + #[doc = "Bit 5 - Port Data Output"] + #[inline(always)] + pub fn pdo5(&mut self) -> Pdo5W { + Pdo5W::new(self, 5) + } + #[doc = "Bit 6 - Port Data Output"] + #[inline(always)] + pub fn pdo6(&mut self) -> Pdo6W { + Pdo6W::new(self, 6) + } + #[doc = "Bit 7 - Port Data Output"] + #[inline(always)] + pub fn pdo7(&mut self) -> Pdo7W { + Pdo7W::new(self, 7) + } + #[doc = "Bit 8 - Port Data Output"] + #[inline(always)] + pub fn pdo8(&mut self) -> Pdo8W { + Pdo8W::new(self, 8) + } + #[doc = "Bit 9 - Port Data Output"] + #[inline(always)] + pub fn pdo9(&mut self) -> Pdo9W { + Pdo9W::new(self, 9) + } + #[doc = "Bit 10 - Port Data Output"] + #[inline(always)] + pub fn pdo10(&mut self) -> Pdo10W { + Pdo10W::new(self, 10) + } + #[doc = "Bit 11 - Port Data Output"] + #[inline(always)] + pub fn pdo11(&mut self) -> Pdo11W { + Pdo11W::new(self, 11) + } + #[doc = "Bit 12 - Port Data Output"] + #[inline(always)] + pub fn pdo12(&mut self) -> Pdo12W { + Pdo12W::new(self, 12) + } + #[doc = "Bit 13 - Port Data Output"] + #[inline(always)] + pub fn pdo13(&mut self) -> Pdo13W { + Pdo13W::new(self, 13) + } + #[doc = "Bit 14 - Port Data Output"] + #[inline(always)] + pub fn pdo14(&mut self) -> Pdo14W { + Pdo14W::new(self, 14) + } + #[doc = "Bit 15 - Port Data Output"] + #[inline(always)] + pub fn pdo15(&mut self) -> Pdo15W { + Pdo15W::new(self, 15) + } + #[doc = "Bit 16 - Port Data Output"] + #[inline(always)] + pub fn pdo16(&mut self) -> Pdo16W { + Pdo16W::new(self, 16) + } + #[doc = "Bit 17 - Port Data Output"] + #[inline(always)] + pub fn pdo17(&mut self) -> Pdo17W { + Pdo17W::new(self, 17) + } + #[doc = "Bit 18 - Port Data Output"] + #[inline(always)] + pub fn pdo18(&mut self) -> Pdo18W { + Pdo18W::new(self, 18) + } + #[doc = "Bit 19 - Port Data Output"] + #[inline(always)] + pub fn pdo19(&mut self) -> Pdo19W { + Pdo19W::new(self, 19) + } + #[doc = "Bit 20 - Port Data Output"] + #[inline(always)] + pub fn pdo20(&mut self) -> Pdo20W { + Pdo20W::new(self, 20) + } + #[doc = "Bit 21 - Port Data Output"] + #[inline(always)] + pub fn pdo21(&mut self) -> Pdo21W { + Pdo21W::new(self, 21) + } + #[doc = "Bit 22 - Port Data Output"] + #[inline(always)] + pub fn pdo22(&mut self) -> Pdo22W { + Pdo22W::new(self, 22) + } + #[doc = "Bit 23 - Port Data Output"] + #[inline(always)] + pub fn pdo23(&mut self) -> Pdo23W { + Pdo23W::new(self, 23) + } + #[doc = "Bit 24 - Port Data Output"] + #[inline(always)] + pub fn pdo24(&mut self) -> Pdo24W { + Pdo24W::new(self, 24) + } + #[doc = "Bit 25 - Port Data Output"] + #[inline(always)] + pub fn pdo25(&mut self) -> Pdo25W { + Pdo25W::new(self, 25) + } + #[doc = "Bit 26 - Port Data Output"] + #[inline(always)] + pub fn pdo26(&mut self) -> Pdo26W { + Pdo26W::new(self, 26) + } + #[doc = "Bit 27 - Port Data Output"] + #[inline(always)] + pub fn pdo27(&mut self) -> Pdo27W { + Pdo27W::new(self, 27) + } + #[doc = "Bit 28 - Port Data Output"] + #[inline(always)] + pub fn pdo28(&mut self) -> Pdo28W { + Pdo28W::new(self, 28) + } + #[doc = "Bit 29 - Port Data Output"] + #[inline(always)] + pub fn pdo29(&mut self) -> Pdo29W { + Pdo29W::new(self, 29) + } + #[doc = "Bit 30 - Port Data Output"] + #[inline(always)] + pub fn pdo30(&mut self) -> Pdo30W { + Pdo30W::new(self, 30) + } + #[doc = "Bit 31 - Port Data Output"] + #[inline(always)] + pub fn pdo31(&mut self) -> Pdo31W { + Pdo31W::new(self, 31) + } +} +#[doc = "Port Data Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pdor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PdorSpec; +impl crate::RegisterSpec for PdorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdor::R`](R) reader structure"] +impl crate::Readable for PdorSpec {} +#[doc = "`write(|w| ..)` method takes [`pdor::W`](W) writer structure"] +impl crate::Writable for PdorSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PDOR to value 0"] +impl crate::Resettable for PdorSpec {} diff --git a/mcxa276-pac/src/gpio0/pdr.rs b/mcxa276-pac/src/gpio0/pdr.rs new file mode 100644 index 000000000..f37f80c6d --- /dev/null +++ b/mcxa276-pac/src/gpio0/pdr.rs @@ -0,0 +1,84 @@ +#[doc = "Register `PDR[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `PDR[%s]` writer"] +pub type W = crate::W; +#[doc = "Pin Data (I/O)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pd { + #[doc = "0: Logic zero"] + Pd0 = 0, + #[doc = "1: Logic one"] + Pd1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PD` reader - Pin Data (I/O)"] +pub type PdR = crate::BitReader; +impl PdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pd { + match self.bits { + false => Pd::Pd0, + true => Pd::Pd1, + } + } + #[doc = "Logic zero"] + #[inline(always)] + pub fn is_pd0(&self) -> bool { + *self == Pd::Pd0 + } + #[doc = "Logic one"] + #[inline(always)] + pub fn is_pd1(&self) -> bool { + *self == Pd::Pd1 + } +} +#[doc = "Field `PD` writer - Pin Data (I/O)"] +pub type PdW<'a, REG> = crate::BitWriter<'a, REG, Pd>; +impl<'a, REG> PdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Logic zero"] + #[inline(always)] + pub fn pd0(self) -> &'a mut crate::W { + self.variant(Pd::Pd0) + } + #[doc = "Logic one"] + #[inline(always)] + pub fn pd1(self) -> &'a mut crate::W { + self.variant(Pd::Pd1) + } +} +impl R { + #[doc = "Bit 0 - Pin Data (I/O)"] + #[inline(always)] + pub fn pd(&self) -> PdR { + PdR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pin Data (I/O)"] + #[inline(always)] + pub fn pd(&mut self) -> PdW { + PdW::new(self, 0) + } +} +#[doc = "Pin Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PdrSpec; +impl crate::RegisterSpec for PdrSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`pdr::R`](R) reader structure"] +impl crate::Readable for PdrSpec {} +#[doc = "`write(|w| ..)` method takes [`pdr::W`](W) writer structure"] +impl crate::Writable for PdrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PDR[%s] to value 0"] +impl crate::Resettable for PdrSpec {} diff --git a/mcxa276-pac/src/gpio0/pidr.rs b/mcxa276-pac/src/gpio0/pidr.rs new file mode 100644 index 000000000..619c9b97b --- /dev/null +++ b/mcxa276-pac/src/gpio0/pidr.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `PIDR` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR` writer"] +pub type W = crate::W; +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid0 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID0` reader - Port Input Disable"] +pub type Pid0R = crate::BitReader; +impl Pid0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid0 { + match self.bits { + false => Pid0::Pid0, + true => Pid0::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid0::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid0::Pid1 + } +} +#[doc = "Field `PID0` writer - Port Input Disable"] +pub type Pid0W<'a, REG> = crate::BitWriter<'a, REG, Pid0>; +impl<'a, REG> Pid0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid0::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid0::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid1 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID1` reader - Port Input Disable"] +pub type Pid1R = crate::BitReader; +impl Pid1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid1 { + match self.bits { + false => Pid1::Pid0, + true => Pid1::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid1::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid1::Pid1 + } +} +#[doc = "Field `PID1` writer - Port Input Disable"] +pub type Pid1W<'a, REG> = crate::BitWriter<'a, REG, Pid1>; +impl<'a, REG> Pid1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid1::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid1::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid2 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID2` reader - Port Input Disable"] +pub type Pid2R = crate::BitReader; +impl Pid2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid2 { + match self.bits { + false => Pid2::Pid0, + true => Pid2::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid2::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid2::Pid1 + } +} +#[doc = "Field `PID2` writer - Port Input Disable"] +pub type Pid2W<'a, REG> = crate::BitWriter<'a, REG, Pid2>; +impl<'a, REG> Pid2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid2::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid2::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid3 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID3` reader - Port Input Disable"] +pub type Pid3R = crate::BitReader; +impl Pid3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid3 { + match self.bits { + false => Pid3::Pid0, + true => Pid3::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid3::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid3::Pid1 + } +} +#[doc = "Field `PID3` writer - Port Input Disable"] +pub type Pid3W<'a, REG> = crate::BitWriter<'a, REG, Pid3>; +impl<'a, REG> Pid3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid3::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid3::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid4 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID4` reader - Port Input Disable"] +pub type Pid4R = crate::BitReader; +impl Pid4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid4 { + match self.bits { + false => Pid4::Pid0, + true => Pid4::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid4::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid4::Pid1 + } +} +#[doc = "Field `PID4` writer - Port Input Disable"] +pub type Pid4W<'a, REG> = crate::BitWriter<'a, REG, Pid4>; +impl<'a, REG> Pid4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid4::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid4::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid5 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID5` reader - Port Input Disable"] +pub type Pid5R = crate::BitReader; +impl Pid5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid5 { + match self.bits { + false => Pid5::Pid0, + true => Pid5::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid5::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid5::Pid1 + } +} +#[doc = "Field `PID5` writer - Port Input Disable"] +pub type Pid5W<'a, REG> = crate::BitWriter<'a, REG, Pid5>; +impl<'a, REG> Pid5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid5::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid5::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid6 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID6` reader - Port Input Disable"] +pub type Pid6R = crate::BitReader; +impl Pid6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid6 { + match self.bits { + false => Pid6::Pid0, + true => Pid6::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid6::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid6::Pid1 + } +} +#[doc = "Field `PID6` writer - Port Input Disable"] +pub type Pid6W<'a, REG> = crate::BitWriter<'a, REG, Pid6>; +impl<'a, REG> Pid6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid6::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid6::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid7 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID7` reader - Port Input Disable"] +pub type Pid7R = crate::BitReader; +impl Pid7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid7 { + match self.bits { + false => Pid7::Pid0, + true => Pid7::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid7::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid7::Pid1 + } +} +#[doc = "Field `PID7` writer - Port Input Disable"] +pub type Pid7W<'a, REG> = crate::BitWriter<'a, REG, Pid7>; +impl<'a, REG> Pid7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid7::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid7::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid8 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID8` reader - Port Input Disable"] +pub type Pid8R = crate::BitReader; +impl Pid8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid8 { + match self.bits { + false => Pid8::Pid0, + true => Pid8::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid8::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid8::Pid1 + } +} +#[doc = "Field `PID8` writer - Port Input Disable"] +pub type Pid8W<'a, REG> = crate::BitWriter<'a, REG, Pid8>; +impl<'a, REG> Pid8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid8::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid8::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid9 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID9` reader - Port Input Disable"] +pub type Pid9R = crate::BitReader; +impl Pid9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid9 { + match self.bits { + false => Pid9::Pid0, + true => Pid9::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid9::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid9::Pid1 + } +} +#[doc = "Field `PID9` writer - Port Input Disable"] +pub type Pid9W<'a, REG> = crate::BitWriter<'a, REG, Pid9>; +impl<'a, REG> Pid9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid9::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid9::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid10 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID10` reader - Port Input Disable"] +pub type Pid10R = crate::BitReader; +impl Pid10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid10 { + match self.bits { + false => Pid10::Pid0, + true => Pid10::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid10::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid10::Pid1 + } +} +#[doc = "Field `PID10` writer - Port Input Disable"] +pub type Pid10W<'a, REG> = crate::BitWriter<'a, REG, Pid10>; +impl<'a, REG> Pid10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid10::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid10::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid11 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID11` reader - Port Input Disable"] +pub type Pid11R = crate::BitReader; +impl Pid11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid11 { + match self.bits { + false => Pid11::Pid0, + true => Pid11::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid11::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid11::Pid1 + } +} +#[doc = "Field `PID11` writer - Port Input Disable"] +pub type Pid11W<'a, REG> = crate::BitWriter<'a, REG, Pid11>; +impl<'a, REG> Pid11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid11::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid11::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid12 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID12` reader - Port Input Disable"] +pub type Pid12R = crate::BitReader; +impl Pid12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid12 { + match self.bits { + false => Pid12::Pid0, + true => Pid12::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid12::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid12::Pid1 + } +} +#[doc = "Field `PID12` writer - Port Input Disable"] +pub type Pid12W<'a, REG> = crate::BitWriter<'a, REG, Pid12>; +impl<'a, REG> Pid12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid12::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid12::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid13 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID13` reader - Port Input Disable"] +pub type Pid13R = crate::BitReader; +impl Pid13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid13 { + match self.bits { + false => Pid13::Pid0, + true => Pid13::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid13::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid13::Pid1 + } +} +#[doc = "Field `PID13` writer - Port Input Disable"] +pub type Pid13W<'a, REG> = crate::BitWriter<'a, REG, Pid13>; +impl<'a, REG> Pid13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid13::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid13::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid14 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID14` reader - Port Input Disable"] +pub type Pid14R = crate::BitReader; +impl Pid14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid14 { + match self.bits { + false => Pid14::Pid0, + true => Pid14::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid14::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid14::Pid1 + } +} +#[doc = "Field `PID14` writer - Port Input Disable"] +pub type Pid14W<'a, REG> = crate::BitWriter<'a, REG, Pid14>; +impl<'a, REG> Pid14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid14::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid14::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid15 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID15` reader - Port Input Disable"] +pub type Pid15R = crate::BitReader; +impl Pid15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid15 { + match self.bits { + false => Pid15::Pid0, + true => Pid15::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid15::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid15::Pid1 + } +} +#[doc = "Field `PID15` writer - Port Input Disable"] +pub type Pid15W<'a, REG> = crate::BitWriter<'a, REG, Pid15>; +impl<'a, REG> Pid15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid15::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid15::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid16 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID16` reader - Port Input Disable"] +pub type Pid16R = crate::BitReader; +impl Pid16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid16 { + match self.bits { + false => Pid16::Pid0, + true => Pid16::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid16::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid16::Pid1 + } +} +#[doc = "Field `PID16` writer - Port Input Disable"] +pub type Pid16W<'a, REG> = crate::BitWriter<'a, REG, Pid16>; +impl<'a, REG> Pid16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid16::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid16::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid17 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID17` reader - Port Input Disable"] +pub type Pid17R = crate::BitReader; +impl Pid17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid17 { + match self.bits { + false => Pid17::Pid0, + true => Pid17::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid17::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid17::Pid1 + } +} +#[doc = "Field `PID17` writer - Port Input Disable"] +pub type Pid17W<'a, REG> = crate::BitWriter<'a, REG, Pid17>; +impl<'a, REG> Pid17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid17::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid17::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid18 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID18` reader - Port Input Disable"] +pub type Pid18R = crate::BitReader; +impl Pid18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid18 { + match self.bits { + false => Pid18::Pid0, + true => Pid18::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid18::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid18::Pid1 + } +} +#[doc = "Field `PID18` writer - Port Input Disable"] +pub type Pid18W<'a, REG> = crate::BitWriter<'a, REG, Pid18>; +impl<'a, REG> Pid18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid18::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid18::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid19 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID19` reader - Port Input Disable"] +pub type Pid19R = crate::BitReader; +impl Pid19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid19 { + match self.bits { + false => Pid19::Pid0, + true => Pid19::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid19::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid19::Pid1 + } +} +#[doc = "Field `PID19` writer - Port Input Disable"] +pub type Pid19W<'a, REG> = crate::BitWriter<'a, REG, Pid19>; +impl<'a, REG> Pid19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid19::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid19::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid20 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID20` reader - Port Input Disable"] +pub type Pid20R = crate::BitReader; +impl Pid20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid20 { + match self.bits { + false => Pid20::Pid0, + true => Pid20::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid20::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid20::Pid1 + } +} +#[doc = "Field `PID20` writer - Port Input Disable"] +pub type Pid20W<'a, REG> = crate::BitWriter<'a, REG, Pid20>; +impl<'a, REG> Pid20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid20::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid20::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid21 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID21` reader - Port Input Disable"] +pub type Pid21R = crate::BitReader; +impl Pid21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid21 { + match self.bits { + false => Pid21::Pid0, + true => Pid21::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid21::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid21::Pid1 + } +} +#[doc = "Field `PID21` writer - Port Input Disable"] +pub type Pid21W<'a, REG> = crate::BitWriter<'a, REG, Pid21>; +impl<'a, REG> Pid21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid21::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid21::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid22 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID22` reader - Port Input Disable"] +pub type Pid22R = crate::BitReader; +impl Pid22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid22 { + match self.bits { + false => Pid22::Pid0, + true => Pid22::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid22::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid22::Pid1 + } +} +#[doc = "Field `PID22` writer - Port Input Disable"] +pub type Pid22W<'a, REG> = crate::BitWriter<'a, REG, Pid22>; +impl<'a, REG> Pid22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid22::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid22::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid23 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID23` reader - Port Input Disable"] +pub type Pid23R = crate::BitReader; +impl Pid23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid23 { + match self.bits { + false => Pid23::Pid0, + true => Pid23::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid23::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid23::Pid1 + } +} +#[doc = "Field `PID23` writer - Port Input Disable"] +pub type Pid23W<'a, REG> = crate::BitWriter<'a, REG, Pid23>; +impl<'a, REG> Pid23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid23::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid23::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid24 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID24` reader - Port Input Disable"] +pub type Pid24R = crate::BitReader; +impl Pid24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid24 { + match self.bits { + false => Pid24::Pid0, + true => Pid24::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid24::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid24::Pid1 + } +} +#[doc = "Field `PID24` writer - Port Input Disable"] +pub type Pid24W<'a, REG> = crate::BitWriter<'a, REG, Pid24>; +impl<'a, REG> Pid24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid24::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid24::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid25 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID25` reader - Port Input Disable"] +pub type Pid25R = crate::BitReader; +impl Pid25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid25 { + match self.bits { + false => Pid25::Pid0, + true => Pid25::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid25::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid25::Pid1 + } +} +#[doc = "Field `PID25` writer - Port Input Disable"] +pub type Pid25W<'a, REG> = crate::BitWriter<'a, REG, Pid25>; +impl<'a, REG> Pid25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid25::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid25::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid26 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID26` reader - Port Input Disable"] +pub type Pid26R = crate::BitReader; +impl Pid26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid26 { + match self.bits { + false => Pid26::Pid0, + true => Pid26::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid26::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid26::Pid1 + } +} +#[doc = "Field `PID26` writer - Port Input Disable"] +pub type Pid26W<'a, REG> = crate::BitWriter<'a, REG, Pid26>; +impl<'a, REG> Pid26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid26::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid26::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid27 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID27` reader - Port Input Disable"] +pub type Pid27R = crate::BitReader; +impl Pid27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid27 { + match self.bits { + false => Pid27::Pid0, + true => Pid27::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid27::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid27::Pid1 + } +} +#[doc = "Field `PID27` writer - Port Input Disable"] +pub type Pid27W<'a, REG> = crate::BitWriter<'a, REG, Pid27>; +impl<'a, REG> Pid27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid27::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid27::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid28 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID28` reader - Port Input Disable"] +pub type Pid28R = crate::BitReader; +impl Pid28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid28 { + match self.bits { + false => Pid28::Pid0, + true => Pid28::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid28::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid28::Pid1 + } +} +#[doc = "Field `PID28` writer - Port Input Disable"] +pub type Pid28W<'a, REG> = crate::BitWriter<'a, REG, Pid28>; +impl<'a, REG> Pid28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid28::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid28::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid29 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID29` reader - Port Input Disable"] +pub type Pid29R = crate::BitReader; +impl Pid29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid29 { + match self.bits { + false => Pid29::Pid0, + true => Pid29::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid29::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid29::Pid1 + } +} +#[doc = "Field `PID29` writer - Port Input Disable"] +pub type Pid29W<'a, REG> = crate::BitWriter<'a, REG, Pid29>; +impl<'a, REG> Pid29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid29::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid29::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid30 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID30` reader - Port Input Disable"] +pub type Pid30R = crate::BitReader; +impl Pid30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid30 { + match self.bits { + false => Pid30::Pid0, + true => Pid30::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid30::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid30::Pid1 + } +} +#[doc = "Field `PID30` writer - Port Input Disable"] +pub type Pid30W<'a, REG> = crate::BitWriter<'a, REG, Pid30>; +impl<'a, REG> Pid30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid30::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid30::Pid1) + } +} +#[doc = "Port Input Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pid31 { + #[doc = "0: Configured for general-purpose input"] + Pid0 = 0, + #[doc = "1: Disabled for general-purpose input"] + Pid1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pid31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PID31` reader - Port Input Disable"] +pub type Pid31R = crate::BitReader; +impl Pid31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pid31 { + match self.bits { + false => Pid31::Pid0, + true => Pid31::Pid1, + } + } + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn is_pid0(&self) -> bool { + *self == Pid31::Pid0 + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn is_pid1(&self) -> bool { + *self == Pid31::Pid1 + } +} +#[doc = "Field `PID31` writer - Port Input Disable"] +pub type Pid31W<'a, REG> = crate::BitWriter<'a, REG, Pid31>; +impl<'a, REG> Pid31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configured for general-purpose input"] + #[inline(always)] + pub fn pid0(self) -> &'a mut crate::W { + self.variant(Pid31::Pid0) + } + #[doc = "Disabled for general-purpose input"] + #[inline(always)] + pub fn pid1(self) -> &'a mut crate::W { + self.variant(Pid31::Pid1) + } +} +impl R { + #[doc = "Bit 0 - Port Input Disable"] + #[inline(always)] + pub fn pid0(&self) -> Pid0R { + Pid0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port Input Disable"] + #[inline(always)] + pub fn pid1(&self) -> Pid1R { + Pid1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port Input Disable"] + #[inline(always)] + pub fn pid2(&self) -> Pid2R { + Pid2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port Input Disable"] + #[inline(always)] + pub fn pid3(&self) -> Pid3R { + Pid3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port Input Disable"] + #[inline(always)] + pub fn pid4(&self) -> Pid4R { + Pid4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port Input Disable"] + #[inline(always)] + pub fn pid5(&self) -> Pid5R { + Pid5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port Input Disable"] + #[inline(always)] + pub fn pid6(&self) -> Pid6R { + Pid6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port Input Disable"] + #[inline(always)] + pub fn pid7(&self) -> Pid7R { + Pid7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port Input Disable"] + #[inline(always)] + pub fn pid8(&self) -> Pid8R { + Pid8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Port Input Disable"] + #[inline(always)] + pub fn pid9(&self) -> Pid9R { + Pid9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Port Input Disable"] + #[inline(always)] + pub fn pid10(&self) -> Pid10R { + Pid10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Port Input Disable"] + #[inline(always)] + pub fn pid11(&self) -> Pid11R { + Pid11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Port Input Disable"] + #[inline(always)] + pub fn pid12(&self) -> Pid12R { + Pid12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Port Input Disable"] + #[inline(always)] + pub fn pid13(&self) -> Pid13R { + Pid13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Port Input Disable"] + #[inline(always)] + pub fn pid14(&self) -> Pid14R { + Pid14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Input Disable"] + #[inline(always)] + pub fn pid15(&self) -> Pid15R { + Pid15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Port Input Disable"] + #[inline(always)] + pub fn pid16(&self) -> Pid16R { + Pid16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Port Input Disable"] + #[inline(always)] + pub fn pid17(&self) -> Pid17R { + Pid17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Port Input Disable"] + #[inline(always)] + pub fn pid18(&self) -> Pid18R { + Pid18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Port Input Disable"] + #[inline(always)] + pub fn pid19(&self) -> Pid19R { + Pid19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Port Input Disable"] + #[inline(always)] + pub fn pid20(&self) -> Pid20R { + Pid20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Port Input Disable"] + #[inline(always)] + pub fn pid21(&self) -> Pid21R { + Pid21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Port Input Disable"] + #[inline(always)] + pub fn pid22(&self) -> Pid22R { + Pid22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Port Input Disable"] + #[inline(always)] + pub fn pid23(&self) -> Pid23R { + Pid23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Port Input Disable"] + #[inline(always)] + pub fn pid24(&self) -> Pid24R { + Pid24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Port Input Disable"] + #[inline(always)] + pub fn pid25(&self) -> Pid25R { + Pid25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Port Input Disable"] + #[inline(always)] + pub fn pid26(&self) -> Pid26R { + Pid26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Port Input Disable"] + #[inline(always)] + pub fn pid27(&self) -> Pid27R { + Pid27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Port Input Disable"] + #[inline(always)] + pub fn pid28(&self) -> Pid28R { + Pid28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Port Input Disable"] + #[inline(always)] + pub fn pid29(&self) -> Pid29R { + Pid29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Port Input Disable"] + #[inline(always)] + pub fn pid30(&self) -> Pid30R { + Pid30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Port Input Disable"] + #[inline(always)] + pub fn pid31(&self) -> Pid31R { + Pid31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Input Disable"] + #[inline(always)] + pub fn pid0(&mut self) -> Pid0W { + Pid0W::new(self, 0) + } + #[doc = "Bit 1 - Port Input Disable"] + #[inline(always)] + pub fn pid1(&mut self) -> Pid1W { + Pid1W::new(self, 1) + } + #[doc = "Bit 2 - Port Input Disable"] + #[inline(always)] + pub fn pid2(&mut self) -> Pid2W { + Pid2W::new(self, 2) + } + #[doc = "Bit 3 - Port Input Disable"] + #[inline(always)] + pub fn pid3(&mut self) -> Pid3W { + Pid3W::new(self, 3) + } + #[doc = "Bit 4 - Port Input Disable"] + #[inline(always)] + pub fn pid4(&mut self) -> Pid4W { + Pid4W::new(self, 4) + } + #[doc = "Bit 5 - Port Input Disable"] + #[inline(always)] + pub fn pid5(&mut self) -> Pid5W { + Pid5W::new(self, 5) + } + #[doc = "Bit 6 - Port Input Disable"] + #[inline(always)] + pub fn pid6(&mut self) -> Pid6W { + Pid6W::new(self, 6) + } + #[doc = "Bit 7 - Port Input Disable"] + #[inline(always)] + pub fn pid7(&mut self) -> Pid7W { + Pid7W::new(self, 7) + } + #[doc = "Bit 8 - Port Input Disable"] + #[inline(always)] + pub fn pid8(&mut self) -> Pid8W { + Pid8W::new(self, 8) + } + #[doc = "Bit 9 - Port Input Disable"] + #[inline(always)] + pub fn pid9(&mut self) -> Pid9W { + Pid9W::new(self, 9) + } + #[doc = "Bit 10 - Port Input Disable"] + #[inline(always)] + pub fn pid10(&mut self) -> Pid10W { + Pid10W::new(self, 10) + } + #[doc = "Bit 11 - Port Input Disable"] + #[inline(always)] + pub fn pid11(&mut self) -> Pid11W { + Pid11W::new(self, 11) + } + #[doc = "Bit 12 - Port Input Disable"] + #[inline(always)] + pub fn pid12(&mut self) -> Pid12W { + Pid12W::new(self, 12) + } + #[doc = "Bit 13 - Port Input Disable"] + #[inline(always)] + pub fn pid13(&mut self) -> Pid13W { + Pid13W::new(self, 13) + } + #[doc = "Bit 14 - Port Input Disable"] + #[inline(always)] + pub fn pid14(&mut self) -> Pid14W { + Pid14W::new(self, 14) + } + #[doc = "Bit 15 - Port Input Disable"] + #[inline(always)] + pub fn pid15(&mut self) -> Pid15W { + Pid15W::new(self, 15) + } + #[doc = "Bit 16 - Port Input Disable"] + #[inline(always)] + pub fn pid16(&mut self) -> Pid16W { + Pid16W::new(self, 16) + } + #[doc = "Bit 17 - Port Input Disable"] + #[inline(always)] + pub fn pid17(&mut self) -> Pid17W { + Pid17W::new(self, 17) + } + #[doc = "Bit 18 - Port Input Disable"] + #[inline(always)] + pub fn pid18(&mut self) -> Pid18W { + Pid18W::new(self, 18) + } + #[doc = "Bit 19 - Port Input Disable"] + #[inline(always)] + pub fn pid19(&mut self) -> Pid19W { + Pid19W::new(self, 19) + } + #[doc = "Bit 20 - Port Input Disable"] + #[inline(always)] + pub fn pid20(&mut self) -> Pid20W { + Pid20W::new(self, 20) + } + #[doc = "Bit 21 - Port Input Disable"] + #[inline(always)] + pub fn pid21(&mut self) -> Pid21W { + Pid21W::new(self, 21) + } + #[doc = "Bit 22 - Port Input Disable"] + #[inline(always)] + pub fn pid22(&mut self) -> Pid22W { + Pid22W::new(self, 22) + } + #[doc = "Bit 23 - Port Input Disable"] + #[inline(always)] + pub fn pid23(&mut self) -> Pid23W { + Pid23W::new(self, 23) + } + #[doc = "Bit 24 - Port Input Disable"] + #[inline(always)] + pub fn pid24(&mut self) -> Pid24W { + Pid24W::new(self, 24) + } + #[doc = "Bit 25 - Port Input Disable"] + #[inline(always)] + pub fn pid25(&mut self) -> Pid25W { + Pid25W::new(self, 25) + } + #[doc = "Bit 26 - Port Input Disable"] + #[inline(always)] + pub fn pid26(&mut self) -> Pid26W { + Pid26W::new(self, 26) + } + #[doc = "Bit 27 - Port Input Disable"] + #[inline(always)] + pub fn pid27(&mut self) -> Pid27W { + Pid27W::new(self, 27) + } + #[doc = "Bit 28 - Port Input Disable"] + #[inline(always)] + pub fn pid28(&mut self) -> Pid28W { + Pid28W::new(self, 28) + } + #[doc = "Bit 29 - Port Input Disable"] + #[inline(always)] + pub fn pid29(&mut self) -> Pid29W { + Pid29W::new(self, 29) + } + #[doc = "Bit 30 - Port Input Disable"] + #[inline(always)] + pub fn pid30(&mut self) -> Pid30W { + Pid30W::new(self, 30) + } + #[doc = "Bit 31 - Port Input Disable"] + #[inline(always)] + pub fn pid31(&mut self) -> Pid31W { + Pid31W::new(self, 31) + } +} +#[doc = "Port Input Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pidr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PidrSpec; +impl crate::RegisterSpec for PidrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr::R`](R) reader structure"] +impl crate::Readable for PidrSpec {} +#[doc = "`write(|w| ..)` method takes [`pidr::W`](W) writer structure"] +impl crate::Writable for PidrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PIDR to value 0"] +impl crate::Resettable for PidrSpec {} diff --git a/mcxa276-pac/src/gpio0/psor.rs b/mcxa276-pac/src/gpio0/psor.rs new file mode 100644 index 000000000..e0cea51f1 --- /dev/null +++ b/mcxa276-pac/src/gpio0/psor.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `PSOR` reader"] +pub type R = crate::R; +#[doc = "Register `PSOR` writer"] +pub type W = crate::W; +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso0 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO0` reader - Port Set Output"] +pub type Ptso0R = crate::BitReader; +impl Ptso0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso0 { + match self.bits { + false => Ptso0::Ptso0, + true => Ptso0::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso0::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso0::Ptso1 + } +} +#[doc = "Field `PTSO0` writer - Port Set Output"] +pub type Ptso0W<'a, REG> = crate::BitWriter<'a, REG, Ptso0>; +impl<'a, REG> Ptso0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso0::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso0::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso1 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO1` reader - Port Set Output"] +pub type Ptso1R = crate::BitReader; +impl Ptso1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso1 { + match self.bits { + false => Ptso1::Ptso0, + true => Ptso1::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso1::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso1::Ptso1 + } +} +#[doc = "Field `PTSO1` writer - Port Set Output"] +pub type Ptso1W<'a, REG> = crate::BitWriter<'a, REG, Ptso1>; +impl<'a, REG> Ptso1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso1::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso1::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso2 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO2` reader - Port Set Output"] +pub type Ptso2R = crate::BitReader; +impl Ptso2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso2 { + match self.bits { + false => Ptso2::Ptso0, + true => Ptso2::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso2::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso2::Ptso1 + } +} +#[doc = "Field `PTSO2` writer - Port Set Output"] +pub type Ptso2W<'a, REG> = crate::BitWriter<'a, REG, Ptso2>; +impl<'a, REG> Ptso2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso2::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso2::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso3 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO3` reader - Port Set Output"] +pub type Ptso3R = crate::BitReader; +impl Ptso3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso3 { + match self.bits { + false => Ptso3::Ptso0, + true => Ptso3::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso3::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso3::Ptso1 + } +} +#[doc = "Field `PTSO3` writer - Port Set Output"] +pub type Ptso3W<'a, REG> = crate::BitWriter<'a, REG, Ptso3>; +impl<'a, REG> Ptso3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso3::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso3::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso4 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO4` reader - Port Set Output"] +pub type Ptso4R = crate::BitReader; +impl Ptso4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso4 { + match self.bits { + false => Ptso4::Ptso0, + true => Ptso4::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso4::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso4::Ptso1 + } +} +#[doc = "Field `PTSO4` writer - Port Set Output"] +pub type Ptso4W<'a, REG> = crate::BitWriter<'a, REG, Ptso4>; +impl<'a, REG> Ptso4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso4::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso4::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso5 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO5` reader - Port Set Output"] +pub type Ptso5R = crate::BitReader; +impl Ptso5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso5 { + match self.bits { + false => Ptso5::Ptso0, + true => Ptso5::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso5::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso5::Ptso1 + } +} +#[doc = "Field `PTSO5` writer - Port Set Output"] +pub type Ptso5W<'a, REG> = crate::BitWriter<'a, REG, Ptso5>; +impl<'a, REG> Ptso5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso5::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso5::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso6 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO6` reader - Port Set Output"] +pub type Ptso6R = crate::BitReader; +impl Ptso6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso6 { + match self.bits { + false => Ptso6::Ptso0, + true => Ptso6::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso6::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso6::Ptso1 + } +} +#[doc = "Field `PTSO6` writer - Port Set Output"] +pub type Ptso6W<'a, REG> = crate::BitWriter<'a, REG, Ptso6>; +impl<'a, REG> Ptso6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso6::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso6::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso7 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO7` reader - Port Set Output"] +pub type Ptso7R = crate::BitReader; +impl Ptso7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso7 { + match self.bits { + false => Ptso7::Ptso0, + true => Ptso7::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso7::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso7::Ptso1 + } +} +#[doc = "Field `PTSO7` writer - Port Set Output"] +pub type Ptso7W<'a, REG> = crate::BitWriter<'a, REG, Ptso7>; +impl<'a, REG> Ptso7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso7::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso7::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso8 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO8` reader - Port Set Output"] +pub type Ptso8R = crate::BitReader; +impl Ptso8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso8 { + match self.bits { + false => Ptso8::Ptso0, + true => Ptso8::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso8::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso8::Ptso1 + } +} +#[doc = "Field `PTSO8` writer - Port Set Output"] +pub type Ptso8W<'a, REG> = crate::BitWriter<'a, REG, Ptso8>; +impl<'a, REG> Ptso8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso8::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso8::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso9 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO9` reader - Port Set Output"] +pub type Ptso9R = crate::BitReader; +impl Ptso9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso9 { + match self.bits { + false => Ptso9::Ptso0, + true => Ptso9::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso9::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso9::Ptso1 + } +} +#[doc = "Field `PTSO9` writer - Port Set Output"] +pub type Ptso9W<'a, REG> = crate::BitWriter<'a, REG, Ptso9>; +impl<'a, REG> Ptso9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso9::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso9::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso10 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO10` reader - Port Set Output"] +pub type Ptso10R = crate::BitReader; +impl Ptso10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso10 { + match self.bits { + false => Ptso10::Ptso0, + true => Ptso10::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso10::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso10::Ptso1 + } +} +#[doc = "Field `PTSO10` writer - Port Set Output"] +pub type Ptso10W<'a, REG> = crate::BitWriter<'a, REG, Ptso10>; +impl<'a, REG> Ptso10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso10::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso10::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso11 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO11` reader - Port Set Output"] +pub type Ptso11R = crate::BitReader; +impl Ptso11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso11 { + match self.bits { + false => Ptso11::Ptso0, + true => Ptso11::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso11::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso11::Ptso1 + } +} +#[doc = "Field `PTSO11` writer - Port Set Output"] +pub type Ptso11W<'a, REG> = crate::BitWriter<'a, REG, Ptso11>; +impl<'a, REG> Ptso11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso11::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso11::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso12 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO12` reader - Port Set Output"] +pub type Ptso12R = crate::BitReader; +impl Ptso12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso12 { + match self.bits { + false => Ptso12::Ptso0, + true => Ptso12::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso12::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso12::Ptso1 + } +} +#[doc = "Field `PTSO12` writer - Port Set Output"] +pub type Ptso12W<'a, REG> = crate::BitWriter<'a, REG, Ptso12>; +impl<'a, REG> Ptso12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso12::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso12::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso13 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO13` reader - Port Set Output"] +pub type Ptso13R = crate::BitReader; +impl Ptso13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso13 { + match self.bits { + false => Ptso13::Ptso0, + true => Ptso13::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso13::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso13::Ptso1 + } +} +#[doc = "Field `PTSO13` writer - Port Set Output"] +pub type Ptso13W<'a, REG> = crate::BitWriter<'a, REG, Ptso13>; +impl<'a, REG> Ptso13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso13::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso13::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso14 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO14` reader - Port Set Output"] +pub type Ptso14R = crate::BitReader; +impl Ptso14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso14 { + match self.bits { + false => Ptso14::Ptso0, + true => Ptso14::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso14::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso14::Ptso1 + } +} +#[doc = "Field `PTSO14` writer - Port Set Output"] +pub type Ptso14W<'a, REG> = crate::BitWriter<'a, REG, Ptso14>; +impl<'a, REG> Ptso14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso14::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso14::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso15 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO15` reader - Port Set Output"] +pub type Ptso15R = crate::BitReader; +impl Ptso15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso15 { + match self.bits { + false => Ptso15::Ptso0, + true => Ptso15::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso15::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso15::Ptso1 + } +} +#[doc = "Field `PTSO15` writer - Port Set Output"] +pub type Ptso15W<'a, REG> = crate::BitWriter<'a, REG, Ptso15>; +impl<'a, REG> Ptso15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso15::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso15::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso16 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO16` reader - Port Set Output"] +pub type Ptso16R = crate::BitReader; +impl Ptso16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso16 { + match self.bits { + false => Ptso16::Ptso0, + true => Ptso16::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso16::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso16::Ptso1 + } +} +#[doc = "Field `PTSO16` writer - Port Set Output"] +pub type Ptso16W<'a, REG> = crate::BitWriter<'a, REG, Ptso16>; +impl<'a, REG> Ptso16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso16::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso16::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso17 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO17` reader - Port Set Output"] +pub type Ptso17R = crate::BitReader; +impl Ptso17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso17 { + match self.bits { + false => Ptso17::Ptso0, + true => Ptso17::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso17::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso17::Ptso1 + } +} +#[doc = "Field `PTSO17` writer - Port Set Output"] +pub type Ptso17W<'a, REG> = crate::BitWriter<'a, REG, Ptso17>; +impl<'a, REG> Ptso17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso17::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso17::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso18 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO18` reader - Port Set Output"] +pub type Ptso18R = crate::BitReader; +impl Ptso18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso18 { + match self.bits { + false => Ptso18::Ptso0, + true => Ptso18::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso18::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso18::Ptso1 + } +} +#[doc = "Field `PTSO18` writer - Port Set Output"] +pub type Ptso18W<'a, REG> = crate::BitWriter<'a, REG, Ptso18>; +impl<'a, REG> Ptso18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso18::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso18::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso19 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO19` reader - Port Set Output"] +pub type Ptso19R = crate::BitReader; +impl Ptso19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso19 { + match self.bits { + false => Ptso19::Ptso0, + true => Ptso19::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso19::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso19::Ptso1 + } +} +#[doc = "Field `PTSO19` writer - Port Set Output"] +pub type Ptso19W<'a, REG> = crate::BitWriter<'a, REG, Ptso19>; +impl<'a, REG> Ptso19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso19::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso19::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso20 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO20` reader - Port Set Output"] +pub type Ptso20R = crate::BitReader; +impl Ptso20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso20 { + match self.bits { + false => Ptso20::Ptso0, + true => Ptso20::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso20::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso20::Ptso1 + } +} +#[doc = "Field `PTSO20` writer - Port Set Output"] +pub type Ptso20W<'a, REG> = crate::BitWriter<'a, REG, Ptso20>; +impl<'a, REG> Ptso20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso20::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso20::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso21 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO21` reader - Port Set Output"] +pub type Ptso21R = crate::BitReader; +impl Ptso21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso21 { + match self.bits { + false => Ptso21::Ptso0, + true => Ptso21::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso21::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso21::Ptso1 + } +} +#[doc = "Field `PTSO21` writer - Port Set Output"] +pub type Ptso21W<'a, REG> = crate::BitWriter<'a, REG, Ptso21>; +impl<'a, REG> Ptso21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso21::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso21::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso22 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO22` reader - Port Set Output"] +pub type Ptso22R = crate::BitReader; +impl Ptso22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso22 { + match self.bits { + false => Ptso22::Ptso0, + true => Ptso22::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso22::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso22::Ptso1 + } +} +#[doc = "Field `PTSO22` writer - Port Set Output"] +pub type Ptso22W<'a, REG> = crate::BitWriter<'a, REG, Ptso22>; +impl<'a, REG> Ptso22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso22::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso22::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso23 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO23` reader - Port Set Output"] +pub type Ptso23R = crate::BitReader; +impl Ptso23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso23 { + match self.bits { + false => Ptso23::Ptso0, + true => Ptso23::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso23::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso23::Ptso1 + } +} +#[doc = "Field `PTSO23` writer - Port Set Output"] +pub type Ptso23W<'a, REG> = crate::BitWriter<'a, REG, Ptso23>; +impl<'a, REG> Ptso23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso23::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso23::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso24 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO24` reader - Port Set Output"] +pub type Ptso24R = crate::BitReader; +impl Ptso24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso24 { + match self.bits { + false => Ptso24::Ptso0, + true => Ptso24::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso24::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso24::Ptso1 + } +} +#[doc = "Field `PTSO24` writer - Port Set Output"] +pub type Ptso24W<'a, REG> = crate::BitWriter<'a, REG, Ptso24>; +impl<'a, REG> Ptso24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso24::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso24::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso25 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO25` reader - Port Set Output"] +pub type Ptso25R = crate::BitReader; +impl Ptso25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso25 { + match self.bits { + false => Ptso25::Ptso0, + true => Ptso25::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso25::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso25::Ptso1 + } +} +#[doc = "Field `PTSO25` writer - Port Set Output"] +pub type Ptso25W<'a, REG> = crate::BitWriter<'a, REG, Ptso25>; +impl<'a, REG> Ptso25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso25::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso25::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso26 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO26` reader - Port Set Output"] +pub type Ptso26R = crate::BitReader; +impl Ptso26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso26 { + match self.bits { + false => Ptso26::Ptso0, + true => Ptso26::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso26::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso26::Ptso1 + } +} +#[doc = "Field `PTSO26` writer - Port Set Output"] +pub type Ptso26W<'a, REG> = crate::BitWriter<'a, REG, Ptso26>; +impl<'a, REG> Ptso26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso26::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso26::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso27 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO27` reader - Port Set Output"] +pub type Ptso27R = crate::BitReader; +impl Ptso27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso27 { + match self.bits { + false => Ptso27::Ptso0, + true => Ptso27::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso27::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso27::Ptso1 + } +} +#[doc = "Field `PTSO27` writer - Port Set Output"] +pub type Ptso27W<'a, REG> = crate::BitWriter<'a, REG, Ptso27>; +impl<'a, REG> Ptso27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso27::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso27::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso28 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO28` reader - Port Set Output"] +pub type Ptso28R = crate::BitReader; +impl Ptso28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso28 { + match self.bits { + false => Ptso28::Ptso0, + true => Ptso28::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso28::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso28::Ptso1 + } +} +#[doc = "Field `PTSO28` writer - Port Set Output"] +pub type Ptso28W<'a, REG> = crate::BitWriter<'a, REG, Ptso28>; +impl<'a, REG> Ptso28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso28::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso28::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso29 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO29` reader - Port Set Output"] +pub type Ptso29R = crate::BitReader; +impl Ptso29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso29 { + match self.bits { + false => Ptso29::Ptso0, + true => Ptso29::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso29::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso29::Ptso1 + } +} +#[doc = "Field `PTSO29` writer - Port Set Output"] +pub type Ptso29W<'a, REG> = crate::BitWriter<'a, REG, Ptso29>; +impl<'a, REG> Ptso29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso29::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso29::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso30 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO30` reader - Port Set Output"] +pub type Ptso30R = crate::BitReader; +impl Ptso30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso30 { + match self.bits { + false => Ptso30::Ptso0, + true => Ptso30::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso30::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso30::Ptso1 + } +} +#[doc = "Field `PTSO30` writer - Port Set Output"] +pub type Ptso30W<'a, REG> = crate::BitWriter<'a, REG, Ptso30>; +impl<'a, REG> Ptso30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso30::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso30::Ptso1) + } +} +#[doc = "Port Set Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptso31 { + #[doc = "0: No change"] + Ptso0 = 0, + #[doc = "1: Corresponding field in PDOR becomes 1"] + Ptso1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptso31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTSO31` reader - Port Set Output"] +pub type Ptso31R = crate::BitReader; +impl Ptso31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptso31 { + match self.bits { + false => Ptso31::Ptso0, + true => Ptso31::Ptso1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptso0(&self) -> bool { + *self == Ptso31::Ptso0 + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn is_ptso1(&self) -> bool { + *self == Ptso31::Ptso1 + } +} +#[doc = "Field `PTSO31` writer - Port Set Output"] +pub type Ptso31W<'a, REG> = crate::BitWriter<'a, REG, Ptso31>; +impl<'a, REG> Ptso31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptso0(self) -> &'a mut crate::W { + self.variant(Ptso31::Ptso0) + } + #[doc = "Corresponding field in PDOR becomes 1"] + #[inline(always)] + pub fn ptso1(self) -> &'a mut crate::W { + self.variant(Ptso31::Ptso1) + } +} +impl R { + #[doc = "Bit 0 - Port Set Output"] + #[inline(always)] + pub fn ptso0(&self) -> Ptso0R { + Ptso0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port Set Output"] + #[inline(always)] + pub fn ptso1(&self) -> Ptso1R { + Ptso1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port Set Output"] + #[inline(always)] + pub fn ptso2(&self) -> Ptso2R { + Ptso2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port Set Output"] + #[inline(always)] + pub fn ptso3(&self) -> Ptso3R { + Ptso3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port Set Output"] + #[inline(always)] + pub fn ptso4(&self) -> Ptso4R { + Ptso4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port Set Output"] + #[inline(always)] + pub fn ptso5(&self) -> Ptso5R { + Ptso5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port Set Output"] + #[inline(always)] + pub fn ptso6(&self) -> Ptso6R { + Ptso6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port Set Output"] + #[inline(always)] + pub fn ptso7(&self) -> Ptso7R { + Ptso7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port Set Output"] + #[inline(always)] + pub fn ptso8(&self) -> Ptso8R { + Ptso8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Port Set Output"] + #[inline(always)] + pub fn ptso9(&self) -> Ptso9R { + Ptso9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Port Set Output"] + #[inline(always)] + pub fn ptso10(&self) -> Ptso10R { + Ptso10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Port Set Output"] + #[inline(always)] + pub fn ptso11(&self) -> Ptso11R { + Ptso11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Port Set Output"] + #[inline(always)] + pub fn ptso12(&self) -> Ptso12R { + Ptso12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Port Set Output"] + #[inline(always)] + pub fn ptso13(&self) -> Ptso13R { + Ptso13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Port Set Output"] + #[inline(always)] + pub fn ptso14(&self) -> Ptso14R { + Ptso14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Set Output"] + #[inline(always)] + pub fn ptso15(&self) -> Ptso15R { + Ptso15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Port Set Output"] + #[inline(always)] + pub fn ptso16(&self) -> Ptso16R { + Ptso16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Port Set Output"] + #[inline(always)] + pub fn ptso17(&self) -> Ptso17R { + Ptso17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Port Set Output"] + #[inline(always)] + pub fn ptso18(&self) -> Ptso18R { + Ptso18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Port Set Output"] + #[inline(always)] + pub fn ptso19(&self) -> Ptso19R { + Ptso19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Port Set Output"] + #[inline(always)] + pub fn ptso20(&self) -> Ptso20R { + Ptso20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Port Set Output"] + #[inline(always)] + pub fn ptso21(&self) -> Ptso21R { + Ptso21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Port Set Output"] + #[inline(always)] + pub fn ptso22(&self) -> Ptso22R { + Ptso22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Port Set Output"] + #[inline(always)] + pub fn ptso23(&self) -> Ptso23R { + Ptso23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Port Set Output"] + #[inline(always)] + pub fn ptso24(&self) -> Ptso24R { + Ptso24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Port Set Output"] + #[inline(always)] + pub fn ptso25(&self) -> Ptso25R { + Ptso25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Port Set Output"] + #[inline(always)] + pub fn ptso26(&self) -> Ptso26R { + Ptso26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Port Set Output"] + #[inline(always)] + pub fn ptso27(&self) -> Ptso27R { + Ptso27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Port Set Output"] + #[inline(always)] + pub fn ptso28(&self) -> Ptso28R { + Ptso28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Port Set Output"] + #[inline(always)] + pub fn ptso29(&self) -> Ptso29R { + Ptso29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Port Set Output"] + #[inline(always)] + pub fn ptso30(&self) -> Ptso30R { + Ptso30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Port Set Output"] + #[inline(always)] + pub fn ptso31(&self) -> Ptso31R { + Ptso31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Set Output"] + #[inline(always)] + pub fn ptso0(&mut self) -> Ptso0W { + Ptso0W::new(self, 0) + } + #[doc = "Bit 1 - Port Set Output"] + #[inline(always)] + pub fn ptso1(&mut self) -> Ptso1W { + Ptso1W::new(self, 1) + } + #[doc = "Bit 2 - Port Set Output"] + #[inline(always)] + pub fn ptso2(&mut self) -> Ptso2W { + Ptso2W::new(self, 2) + } + #[doc = "Bit 3 - Port Set Output"] + #[inline(always)] + pub fn ptso3(&mut self) -> Ptso3W { + Ptso3W::new(self, 3) + } + #[doc = "Bit 4 - Port Set Output"] + #[inline(always)] + pub fn ptso4(&mut self) -> Ptso4W { + Ptso4W::new(self, 4) + } + #[doc = "Bit 5 - Port Set Output"] + #[inline(always)] + pub fn ptso5(&mut self) -> Ptso5W { + Ptso5W::new(self, 5) + } + #[doc = "Bit 6 - Port Set Output"] + #[inline(always)] + pub fn ptso6(&mut self) -> Ptso6W { + Ptso6W::new(self, 6) + } + #[doc = "Bit 7 - Port Set Output"] + #[inline(always)] + pub fn ptso7(&mut self) -> Ptso7W { + Ptso7W::new(self, 7) + } + #[doc = "Bit 8 - Port Set Output"] + #[inline(always)] + pub fn ptso8(&mut self) -> Ptso8W { + Ptso8W::new(self, 8) + } + #[doc = "Bit 9 - Port Set Output"] + #[inline(always)] + pub fn ptso9(&mut self) -> Ptso9W { + Ptso9W::new(self, 9) + } + #[doc = "Bit 10 - Port Set Output"] + #[inline(always)] + pub fn ptso10(&mut self) -> Ptso10W { + Ptso10W::new(self, 10) + } + #[doc = "Bit 11 - Port Set Output"] + #[inline(always)] + pub fn ptso11(&mut self) -> Ptso11W { + Ptso11W::new(self, 11) + } + #[doc = "Bit 12 - Port Set Output"] + #[inline(always)] + pub fn ptso12(&mut self) -> Ptso12W { + Ptso12W::new(self, 12) + } + #[doc = "Bit 13 - Port Set Output"] + #[inline(always)] + pub fn ptso13(&mut self) -> Ptso13W { + Ptso13W::new(self, 13) + } + #[doc = "Bit 14 - Port Set Output"] + #[inline(always)] + pub fn ptso14(&mut self) -> Ptso14W { + Ptso14W::new(self, 14) + } + #[doc = "Bit 15 - Port Set Output"] + #[inline(always)] + pub fn ptso15(&mut self) -> Ptso15W { + Ptso15W::new(self, 15) + } + #[doc = "Bit 16 - Port Set Output"] + #[inline(always)] + pub fn ptso16(&mut self) -> Ptso16W { + Ptso16W::new(self, 16) + } + #[doc = "Bit 17 - Port Set Output"] + #[inline(always)] + pub fn ptso17(&mut self) -> Ptso17W { + Ptso17W::new(self, 17) + } + #[doc = "Bit 18 - Port Set Output"] + #[inline(always)] + pub fn ptso18(&mut self) -> Ptso18W { + Ptso18W::new(self, 18) + } + #[doc = "Bit 19 - Port Set Output"] + #[inline(always)] + pub fn ptso19(&mut self) -> Ptso19W { + Ptso19W::new(self, 19) + } + #[doc = "Bit 20 - Port Set Output"] + #[inline(always)] + pub fn ptso20(&mut self) -> Ptso20W { + Ptso20W::new(self, 20) + } + #[doc = "Bit 21 - Port Set Output"] + #[inline(always)] + pub fn ptso21(&mut self) -> Ptso21W { + Ptso21W::new(self, 21) + } + #[doc = "Bit 22 - Port Set Output"] + #[inline(always)] + pub fn ptso22(&mut self) -> Ptso22W { + Ptso22W::new(self, 22) + } + #[doc = "Bit 23 - Port Set Output"] + #[inline(always)] + pub fn ptso23(&mut self) -> Ptso23W { + Ptso23W::new(self, 23) + } + #[doc = "Bit 24 - Port Set Output"] + #[inline(always)] + pub fn ptso24(&mut self) -> Ptso24W { + Ptso24W::new(self, 24) + } + #[doc = "Bit 25 - Port Set Output"] + #[inline(always)] + pub fn ptso25(&mut self) -> Ptso25W { + Ptso25W::new(self, 25) + } + #[doc = "Bit 26 - Port Set Output"] + #[inline(always)] + pub fn ptso26(&mut self) -> Ptso26W { + Ptso26W::new(self, 26) + } + #[doc = "Bit 27 - Port Set Output"] + #[inline(always)] + pub fn ptso27(&mut self) -> Ptso27W { + Ptso27W::new(self, 27) + } + #[doc = "Bit 28 - Port Set Output"] + #[inline(always)] + pub fn ptso28(&mut self) -> Ptso28W { + Ptso28W::new(self, 28) + } + #[doc = "Bit 29 - Port Set Output"] + #[inline(always)] + pub fn ptso29(&mut self) -> Ptso29W { + Ptso29W::new(self, 29) + } + #[doc = "Bit 30 - Port Set Output"] + #[inline(always)] + pub fn ptso30(&mut self) -> Ptso30W { + Ptso30W::new(self, 30) + } + #[doc = "Bit 31 - Port Set Output"] + #[inline(always)] + pub fn ptso31(&mut self) -> Ptso31W { + Ptso31W::new(self, 31) + } +} +#[doc = "Port Set Output\n\nYou can [`read`](crate::Reg::read) this register and get [`psor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PsorSpec; +impl crate::RegisterSpec for PsorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`psor::R`](R) reader structure"] +impl crate::Readable for PsorSpec {} +#[doc = "`write(|w| ..)` method takes [`psor::W`](W) writer structure"] +impl crate::Writable for PsorSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PSOR to value 0"] +impl crate::Resettable for PsorSpec {} diff --git a/mcxa276-pac/src/gpio0/ptor.rs b/mcxa276-pac/src/gpio0/ptor.rs new file mode 100644 index 000000000..fda81c765 --- /dev/null +++ b/mcxa276-pac/src/gpio0/ptor.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `PTOR` reader"] +pub type R = crate::R; +#[doc = "Register `PTOR` writer"] +pub type W = crate::W; +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto0 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO0` reader - Port Toggle Output"] +pub type Ptto0R = crate::BitReader; +impl Ptto0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto0 { + match self.bits { + false => Ptto0::Ptto0, + true => Ptto0::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto0::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto0::Ptto1 + } +} +#[doc = "Field `PTTO0` writer - Port Toggle Output"] +pub type Ptto0W<'a, REG> = crate::BitWriter<'a, REG, Ptto0>; +impl<'a, REG> Ptto0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto0::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto0::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto1 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO1` reader - Port Toggle Output"] +pub type Ptto1R = crate::BitReader; +impl Ptto1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto1 { + match self.bits { + false => Ptto1::Ptto0, + true => Ptto1::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto1::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto1::Ptto1 + } +} +#[doc = "Field `PTTO1` writer - Port Toggle Output"] +pub type Ptto1W<'a, REG> = crate::BitWriter<'a, REG, Ptto1>; +impl<'a, REG> Ptto1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto1::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto1::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto2 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO2` reader - Port Toggle Output"] +pub type Ptto2R = crate::BitReader; +impl Ptto2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto2 { + match self.bits { + false => Ptto2::Ptto0, + true => Ptto2::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto2::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto2::Ptto1 + } +} +#[doc = "Field `PTTO2` writer - Port Toggle Output"] +pub type Ptto2W<'a, REG> = crate::BitWriter<'a, REG, Ptto2>; +impl<'a, REG> Ptto2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto2::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto2::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto3 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO3` reader - Port Toggle Output"] +pub type Ptto3R = crate::BitReader; +impl Ptto3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto3 { + match self.bits { + false => Ptto3::Ptto0, + true => Ptto3::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto3::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto3::Ptto1 + } +} +#[doc = "Field `PTTO3` writer - Port Toggle Output"] +pub type Ptto3W<'a, REG> = crate::BitWriter<'a, REG, Ptto3>; +impl<'a, REG> Ptto3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto3::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto3::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto4 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO4` reader - Port Toggle Output"] +pub type Ptto4R = crate::BitReader; +impl Ptto4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto4 { + match self.bits { + false => Ptto4::Ptto0, + true => Ptto4::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto4::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto4::Ptto1 + } +} +#[doc = "Field `PTTO4` writer - Port Toggle Output"] +pub type Ptto4W<'a, REG> = crate::BitWriter<'a, REG, Ptto4>; +impl<'a, REG> Ptto4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto4::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto4::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto5 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO5` reader - Port Toggle Output"] +pub type Ptto5R = crate::BitReader; +impl Ptto5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto5 { + match self.bits { + false => Ptto5::Ptto0, + true => Ptto5::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto5::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto5::Ptto1 + } +} +#[doc = "Field `PTTO5` writer - Port Toggle Output"] +pub type Ptto5W<'a, REG> = crate::BitWriter<'a, REG, Ptto5>; +impl<'a, REG> Ptto5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto5::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto5::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto6 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO6` reader - Port Toggle Output"] +pub type Ptto6R = crate::BitReader; +impl Ptto6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto6 { + match self.bits { + false => Ptto6::Ptto0, + true => Ptto6::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto6::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto6::Ptto1 + } +} +#[doc = "Field `PTTO6` writer - Port Toggle Output"] +pub type Ptto6W<'a, REG> = crate::BitWriter<'a, REG, Ptto6>; +impl<'a, REG> Ptto6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto6::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto6::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto7 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO7` reader - Port Toggle Output"] +pub type Ptto7R = crate::BitReader; +impl Ptto7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto7 { + match self.bits { + false => Ptto7::Ptto0, + true => Ptto7::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto7::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto7::Ptto1 + } +} +#[doc = "Field `PTTO7` writer - Port Toggle Output"] +pub type Ptto7W<'a, REG> = crate::BitWriter<'a, REG, Ptto7>; +impl<'a, REG> Ptto7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto7::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto7::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto8 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO8` reader - Port Toggle Output"] +pub type Ptto8R = crate::BitReader; +impl Ptto8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto8 { + match self.bits { + false => Ptto8::Ptto0, + true => Ptto8::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto8::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto8::Ptto1 + } +} +#[doc = "Field `PTTO8` writer - Port Toggle Output"] +pub type Ptto8W<'a, REG> = crate::BitWriter<'a, REG, Ptto8>; +impl<'a, REG> Ptto8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto8::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto8::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto9 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO9` reader - Port Toggle Output"] +pub type Ptto9R = crate::BitReader; +impl Ptto9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto9 { + match self.bits { + false => Ptto9::Ptto0, + true => Ptto9::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto9::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto9::Ptto1 + } +} +#[doc = "Field `PTTO9` writer - Port Toggle Output"] +pub type Ptto9W<'a, REG> = crate::BitWriter<'a, REG, Ptto9>; +impl<'a, REG> Ptto9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto9::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto9::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto10 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO10` reader - Port Toggle Output"] +pub type Ptto10R = crate::BitReader; +impl Ptto10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto10 { + match self.bits { + false => Ptto10::Ptto0, + true => Ptto10::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto10::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto10::Ptto1 + } +} +#[doc = "Field `PTTO10` writer - Port Toggle Output"] +pub type Ptto10W<'a, REG> = crate::BitWriter<'a, REG, Ptto10>; +impl<'a, REG> Ptto10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto10::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto10::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto11 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO11` reader - Port Toggle Output"] +pub type Ptto11R = crate::BitReader; +impl Ptto11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto11 { + match self.bits { + false => Ptto11::Ptto0, + true => Ptto11::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto11::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto11::Ptto1 + } +} +#[doc = "Field `PTTO11` writer - Port Toggle Output"] +pub type Ptto11W<'a, REG> = crate::BitWriter<'a, REG, Ptto11>; +impl<'a, REG> Ptto11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto11::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto11::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto12 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO12` reader - Port Toggle Output"] +pub type Ptto12R = crate::BitReader; +impl Ptto12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto12 { + match self.bits { + false => Ptto12::Ptto0, + true => Ptto12::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto12::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto12::Ptto1 + } +} +#[doc = "Field `PTTO12` writer - Port Toggle Output"] +pub type Ptto12W<'a, REG> = crate::BitWriter<'a, REG, Ptto12>; +impl<'a, REG> Ptto12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto12::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto12::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto13 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO13` reader - Port Toggle Output"] +pub type Ptto13R = crate::BitReader; +impl Ptto13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto13 { + match self.bits { + false => Ptto13::Ptto0, + true => Ptto13::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto13::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto13::Ptto1 + } +} +#[doc = "Field `PTTO13` writer - Port Toggle Output"] +pub type Ptto13W<'a, REG> = crate::BitWriter<'a, REG, Ptto13>; +impl<'a, REG> Ptto13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto13::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto13::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto14 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO14` reader - Port Toggle Output"] +pub type Ptto14R = crate::BitReader; +impl Ptto14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto14 { + match self.bits { + false => Ptto14::Ptto0, + true => Ptto14::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto14::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto14::Ptto1 + } +} +#[doc = "Field `PTTO14` writer - Port Toggle Output"] +pub type Ptto14W<'a, REG> = crate::BitWriter<'a, REG, Ptto14>; +impl<'a, REG> Ptto14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto14::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto14::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto15 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO15` reader - Port Toggle Output"] +pub type Ptto15R = crate::BitReader; +impl Ptto15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto15 { + match self.bits { + false => Ptto15::Ptto0, + true => Ptto15::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto15::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto15::Ptto1 + } +} +#[doc = "Field `PTTO15` writer - Port Toggle Output"] +pub type Ptto15W<'a, REG> = crate::BitWriter<'a, REG, Ptto15>; +impl<'a, REG> Ptto15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto15::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto15::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto16 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO16` reader - Port Toggle Output"] +pub type Ptto16R = crate::BitReader; +impl Ptto16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto16 { + match self.bits { + false => Ptto16::Ptto0, + true => Ptto16::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto16::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto16::Ptto1 + } +} +#[doc = "Field `PTTO16` writer - Port Toggle Output"] +pub type Ptto16W<'a, REG> = crate::BitWriter<'a, REG, Ptto16>; +impl<'a, REG> Ptto16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto16::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto16::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto17 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO17` reader - Port Toggle Output"] +pub type Ptto17R = crate::BitReader; +impl Ptto17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto17 { + match self.bits { + false => Ptto17::Ptto0, + true => Ptto17::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto17::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto17::Ptto1 + } +} +#[doc = "Field `PTTO17` writer - Port Toggle Output"] +pub type Ptto17W<'a, REG> = crate::BitWriter<'a, REG, Ptto17>; +impl<'a, REG> Ptto17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto17::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto17::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto18 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO18` reader - Port Toggle Output"] +pub type Ptto18R = crate::BitReader; +impl Ptto18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto18 { + match self.bits { + false => Ptto18::Ptto0, + true => Ptto18::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto18::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto18::Ptto1 + } +} +#[doc = "Field `PTTO18` writer - Port Toggle Output"] +pub type Ptto18W<'a, REG> = crate::BitWriter<'a, REG, Ptto18>; +impl<'a, REG> Ptto18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto18::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto18::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto19 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO19` reader - Port Toggle Output"] +pub type Ptto19R = crate::BitReader; +impl Ptto19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto19 { + match self.bits { + false => Ptto19::Ptto0, + true => Ptto19::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto19::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto19::Ptto1 + } +} +#[doc = "Field `PTTO19` writer - Port Toggle Output"] +pub type Ptto19W<'a, REG> = crate::BitWriter<'a, REG, Ptto19>; +impl<'a, REG> Ptto19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto19::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto19::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto20 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO20` reader - Port Toggle Output"] +pub type Ptto20R = crate::BitReader; +impl Ptto20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto20 { + match self.bits { + false => Ptto20::Ptto0, + true => Ptto20::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto20::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto20::Ptto1 + } +} +#[doc = "Field `PTTO20` writer - Port Toggle Output"] +pub type Ptto20W<'a, REG> = crate::BitWriter<'a, REG, Ptto20>; +impl<'a, REG> Ptto20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto20::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto20::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto21 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO21` reader - Port Toggle Output"] +pub type Ptto21R = crate::BitReader; +impl Ptto21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto21 { + match self.bits { + false => Ptto21::Ptto0, + true => Ptto21::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto21::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto21::Ptto1 + } +} +#[doc = "Field `PTTO21` writer - Port Toggle Output"] +pub type Ptto21W<'a, REG> = crate::BitWriter<'a, REG, Ptto21>; +impl<'a, REG> Ptto21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto21::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto21::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto22 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO22` reader - Port Toggle Output"] +pub type Ptto22R = crate::BitReader; +impl Ptto22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto22 { + match self.bits { + false => Ptto22::Ptto0, + true => Ptto22::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto22::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto22::Ptto1 + } +} +#[doc = "Field `PTTO22` writer - Port Toggle Output"] +pub type Ptto22W<'a, REG> = crate::BitWriter<'a, REG, Ptto22>; +impl<'a, REG> Ptto22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto22::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto22::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto23 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO23` reader - Port Toggle Output"] +pub type Ptto23R = crate::BitReader; +impl Ptto23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto23 { + match self.bits { + false => Ptto23::Ptto0, + true => Ptto23::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto23::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto23::Ptto1 + } +} +#[doc = "Field `PTTO23` writer - Port Toggle Output"] +pub type Ptto23W<'a, REG> = crate::BitWriter<'a, REG, Ptto23>; +impl<'a, REG> Ptto23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto23::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto23::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto24 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO24` reader - Port Toggle Output"] +pub type Ptto24R = crate::BitReader; +impl Ptto24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto24 { + match self.bits { + false => Ptto24::Ptto0, + true => Ptto24::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto24::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto24::Ptto1 + } +} +#[doc = "Field `PTTO24` writer - Port Toggle Output"] +pub type Ptto24W<'a, REG> = crate::BitWriter<'a, REG, Ptto24>; +impl<'a, REG> Ptto24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto24::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto24::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto25 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO25` reader - Port Toggle Output"] +pub type Ptto25R = crate::BitReader; +impl Ptto25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto25 { + match self.bits { + false => Ptto25::Ptto0, + true => Ptto25::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto25::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto25::Ptto1 + } +} +#[doc = "Field `PTTO25` writer - Port Toggle Output"] +pub type Ptto25W<'a, REG> = crate::BitWriter<'a, REG, Ptto25>; +impl<'a, REG> Ptto25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto25::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto25::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto26 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO26` reader - Port Toggle Output"] +pub type Ptto26R = crate::BitReader; +impl Ptto26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto26 { + match self.bits { + false => Ptto26::Ptto0, + true => Ptto26::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto26::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto26::Ptto1 + } +} +#[doc = "Field `PTTO26` writer - Port Toggle Output"] +pub type Ptto26W<'a, REG> = crate::BitWriter<'a, REG, Ptto26>; +impl<'a, REG> Ptto26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto26::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto26::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto27 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO27` reader - Port Toggle Output"] +pub type Ptto27R = crate::BitReader; +impl Ptto27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto27 { + match self.bits { + false => Ptto27::Ptto0, + true => Ptto27::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto27::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto27::Ptto1 + } +} +#[doc = "Field `PTTO27` writer - Port Toggle Output"] +pub type Ptto27W<'a, REG> = crate::BitWriter<'a, REG, Ptto27>; +impl<'a, REG> Ptto27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto27::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto27::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto28 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO28` reader - Port Toggle Output"] +pub type Ptto28R = crate::BitReader; +impl Ptto28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto28 { + match self.bits { + false => Ptto28::Ptto0, + true => Ptto28::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto28::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto28::Ptto1 + } +} +#[doc = "Field `PTTO28` writer - Port Toggle Output"] +pub type Ptto28W<'a, REG> = crate::BitWriter<'a, REG, Ptto28>; +impl<'a, REG> Ptto28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto28::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto28::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto29 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO29` reader - Port Toggle Output"] +pub type Ptto29R = crate::BitReader; +impl Ptto29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto29 { + match self.bits { + false => Ptto29::Ptto0, + true => Ptto29::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto29::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto29::Ptto1 + } +} +#[doc = "Field `PTTO29` writer - Port Toggle Output"] +pub type Ptto29W<'a, REG> = crate::BitWriter<'a, REG, Ptto29>; +impl<'a, REG> Ptto29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto29::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto29::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto30 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO30` reader - Port Toggle Output"] +pub type Ptto30R = crate::BitReader; +impl Ptto30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto30 { + match self.bits { + false => Ptto30::Ptto0, + true => Ptto30::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto30::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto30::Ptto1 + } +} +#[doc = "Field `PTTO30` writer - Port Toggle Output"] +pub type Ptto30W<'a, REG> = crate::BitWriter<'a, REG, Ptto30>; +impl<'a, REG> Ptto30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto30::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto30::Ptto1) + } +} +#[doc = "Port Toggle Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ptto31 { + #[doc = "0: No change"] + Ptto0 = 0, + #[doc = "1: Set to the inverse of its current logic state"] + Ptto1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ptto31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PTTO31` reader - Port Toggle Output"] +pub type Ptto31R = crate::BitReader; +impl Ptto31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ptto31 { + match self.bits { + false => Ptto31::Ptto0, + true => Ptto31::Ptto1, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_ptto0(&self) -> bool { + *self == Ptto31::Ptto0 + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn is_ptto1(&self) -> bool { + *self == Ptto31::Ptto1 + } +} +#[doc = "Field `PTTO31` writer - Port Toggle Output"] +pub type Ptto31W<'a, REG> = crate::BitWriter<'a, REG, Ptto31>; +impl<'a, REG> Ptto31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn ptto0(self) -> &'a mut crate::W { + self.variant(Ptto31::Ptto0) + } + #[doc = "Set to the inverse of its current logic state"] + #[inline(always)] + pub fn ptto1(self) -> &'a mut crate::W { + self.variant(Ptto31::Ptto1) + } +} +impl R { + #[doc = "Bit 0 - Port Toggle Output"] + #[inline(always)] + pub fn ptto0(&self) -> Ptto0R { + Ptto0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port Toggle Output"] + #[inline(always)] + pub fn ptto1(&self) -> Ptto1R { + Ptto1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port Toggle Output"] + #[inline(always)] + pub fn ptto2(&self) -> Ptto2R { + Ptto2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port Toggle Output"] + #[inline(always)] + pub fn ptto3(&self) -> Ptto3R { + Ptto3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port Toggle Output"] + #[inline(always)] + pub fn ptto4(&self) -> Ptto4R { + Ptto4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port Toggle Output"] + #[inline(always)] + pub fn ptto5(&self) -> Ptto5R { + Ptto5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port Toggle Output"] + #[inline(always)] + pub fn ptto6(&self) -> Ptto6R { + Ptto6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port Toggle Output"] + #[inline(always)] + pub fn ptto7(&self) -> Ptto7R { + Ptto7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port Toggle Output"] + #[inline(always)] + pub fn ptto8(&self) -> Ptto8R { + Ptto8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Port Toggle Output"] + #[inline(always)] + pub fn ptto9(&self) -> Ptto9R { + Ptto9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Port Toggle Output"] + #[inline(always)] + pub fn ptto10(&self) -> Ptto10R { + Ptto10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Port Toggle Output"] + #[inline(always)] + pub fn ptto11(&self) -> Ptto11R { + Ptto11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Port Toggle Output"] + #[inline(always)] + pub fn ptto12(&self) -> Ptto12R { + Ptto12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Port Toggle Output"] + #[inline(always)] + pub fn ptto13(&self) -> Ptto13R { + Ptto13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Port Toggle Output"] + #[inline(always)] + pub fn ptto14(&self) -> Ptto14R { + Ptto14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Toggle Output"] + #[inline(always)] + pub fn ptto15(&self) -> Ptto15R { + Ptto15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Port Toggle Output"] + #[inline(always)] + pub fn ptto16(&self) -> Ptto16R { + Ptto16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Port Toggle Output"] + #[inline(always)] + pub fn ptto17(&self) -> Ptto17R { + Ptto17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Port Toggle Output"] + #[inline(always)] + pub fn ptto18(&self) -> Ptto18R { + Ptto18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Port Toggle Output"] + #[inline(always)] + pub fn ptto19(&self) -> Ptto19R { + Ptto19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Port Toggle Output"] + #[inline(always)] + pub fn ptto20(&self) -> Ptto20R { + Ptto20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Port Toggle Output"] + #[inline(always)] + pub fn ptto21(&self) -> Ptto21R { + Ptto21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Port Toggle Output"] + #[inline(always)] + pub fn ptto22(&self) -> Ptto22R { + Ptto22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Port Toggle Output"] + #[inline(always)] + pub fn ptto23(&self) -> Ptto23R { + Ptto23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Port Toggle Output"] + #[inline(always)] + pub fn ptto24(&self) -> Ptto24R { + Ptto24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Port Toggle Output"] + #[inline(always)] + pub fn ptto25(&self) -> Ptto25R { + Ptto25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Port Toggle Output"] + #[inline(always)] + pub fn ptto26(&self) -> Ptto26R { + Ptto26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Port Toggle Output"] + #[inline(always)] + pub fn ptto27(&self) -> Ptto27R { + Ptto27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Port Toggle Output"] + #[inline(always)] + pub fn ptto28(&self) -> Ptto28R { + Ptto28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Port Toggle Output"] + #[inline(always)] + pub fn ptto29(&self) -> Ptto29R { + Ptto29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Port Toggle Output"] + #[inline(always)] + pub fn ptto30(&self) -> Ptto30R { + Ptto30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Port Toggle Output"] + #[inline(always)] + pub fn ptto31(&self) -> Ptto31R { + Ptto31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Toggle Output"] + #[inline(always)] + pub fn ptto0(&mut self) -> Ptto0W { + Ptto0W::new(self, 0) + } + #[doc = "Bit 1 - Port Toggle Output"] + #[inline(always)] + pub fn ptto1(&mut self) -> Ptto1W { + Ptto1W::new(self, 1) + } + #[doc = "Bit 2 - Port Toggle Output"] + #[inline(always)] + pub fn ptto2(&mut self) -> Ptto2W { + Ptto2W::new(self, 2) + } + #[doc = "Bit 3 - Port Toggle Output"] + #[inline(always)] + pub fn ptto3(&mut self) -> Ptto3W { + Ptto3W::new(self, 3) + } + #[doc = "Bit 4 - Port Toggle Output"] + #[inline(always)] + pub fn ptto4(&mut self) -> Ptto4W { + Ptto4W::new(self, 4) + } + #[doc = "Bit 5 - Port Toggle Output"] + #[inline(always)] + pub fn ptto5(&mut self) -> Ptto5W { + Ptto5W::new(self, 5) + } + #[doc = "Bit 6 - Port Toggle Output"] + #[inline(always)] + pub fn ptto6(&mut self) -> Ptto6W { + Ptto6W::new(self, 6) + } + #[doc = "Bit 7 - Port Toggle Output"] + #[inline(always)] + pub fn ptto7(&mut self) -> Ptto7W { + Ptto7W::new(self, 7) + } + #[doc = "Bit 8 - Port Toggle Output"] + #[inline(always)] + pub fn ptto8(&mut self) -> Ptto8W { + Ptto8W::new(self, 8) + } + #[doc = "Bit 9 - Port Toggle Output"] + #[inline(always)] + pub fn ptto9(&mut self) -> Ptto9W { + Ptto9W::new(self, 9) + } + #[doc = "Bit 10 - Port Toggle Output"] + #[inline(always)] + pub fn ptto10(&mut self) -> Ptto10W { + Ptto10W::new(self, 10) + } + #[doc = "Bit 11 - Port Toggle Output"] + #[inline(always)] + pub fn ptto11(&mut self) -> Ptto11W { + Ptto11W::new(self, 11) + } + #[doc = "Bit 12 - Port Toggle Output"] + #[inline(always)] + pub fn ptto12(&mut self) -> Ptto12W { + Ptto12W::new(self, 12) + } + #[doc = "Bit 13 - Port Toggle Output"] + #[inline(always)] + pub fn ptto13(&mut self) -> Ptto13W { + Ptto13W::new(self, 13) + } + #[doc = "Bit 14 - Port Toggle Output"] + #[inline(always)] + pub fn ptto14(&mut self) -> Ptto14W { + Ptto14W::new(self, 14) + } + #[doc = "Bit 15 - Port Toggle Output"] + #[inline(always)] + pub fn ptto15(&mut self) -> Ptto15W { + Ptto15W::new(self, 15) + } + #[doc = "Bit 16 - Port Toggle Output"] + #[inline(always)] + pub fn ptto16(&mut self) -> Ptto16W { + Ptto16W::new(self, 16) + } + #[doc = "Bit 17 - Port Toggle Output"] + #[inline(always)] + pub fn ptto17(&mut self) -> Ptto17W { + Ptto17W::new(self, 17) + } + #[doc = "Bit 18 - Port Toggle Output"] + #[inline(always)] + pub fn ptto18(&mut self) -> Ptto18W { + Ptto18W::new(self, 18) + } + #[doc = "Bit 19 - Port Toggle Output"] + #[inline(always)] + pub fn ptto19(&mut self) -> Ptto19W { + Ptto19W::new(self, 19) + } + #[doc = "Bit 20 - Port Toggle Output"] + #[inline(always)] + pub fn ptto20(&mut self) -> Ptto20W { + Ptto20W::new(self, 20) + } + #[doc = "Bit 21 - Port Toggle Output"] + #[inline(always)] + pub fn ptto21(&mut self) -> Ptto21W { + Ptto21W::new(self, 21) + } + #[doc = "Bit 22 - Port Toggle Output"] + #[inline(always)] + pub fn ptto22(&mut self) -> Ptto22W { + Ptto22W::new(self, 22) + } + #[doc = "Bit 23 - Port Toggle Output"] + #[inline(always)] + pub fn ptto23(&mut self) -> Ptto23W { + Ptto23W::new(self, 23) + } + #[doc = "Bit 24 - Port Toggle Output"] + #[inline(always)] + pub fn ptto24(&mut self) -> Ptto24W { + Ptto24W::new(self, 24) + } + #[doc = "Bit 25 - Port Toggle Output"] + #[inline(always)] + pub fn ptto25(&mut self) -> Ptto25W { + Ptto25W::new(self, 25) + } + #[doc = "Bit 26 - Port Toggle Output"] + #[inline(always)] + pub fn ptto26(&mut self) -> Ptto26W { + Ptto26W::new(self, 26) + } + #[doc = "Bit 27 - Port Toggle Output"] + #[inline(always)] + pub fn ptto27(&mut self) -> Ptto27W { + Ptto27W::new(self, 27) + } + #[doc = "Bit 28 - Port Toggle Output"] + #[inline(always)] + pub fn ptto28(&mut self) -> Ptto28W { + Ptto28W::new(self, 28) + } + #[doc = "Bit 29 - Port Toggle Output"] + #[inline(always)] + pub fn ptto29(&mut self) -> Ptto29W { + Ptto29W::new(self, 29) + } + #[doc = "Bit 30 - Port Toggle Output"] + #[inline(always)] + pub fn ptto30(&mut self) -> Ptto30W { + Ptto30W::new(self, 30) + } + #[doc = "Bit 31 - Port Toggle Output"] + #[inline(always)] + pub fn ptto31(&mut self) -> Ptto31W { + Ptto31W::new(self, 31) + } +} +#[doc = "Port Toggle Output\n\nYou can [`read`](crate::Reg::read) this register and get [`ptor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ptor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PtorSpec; +impl crate::RegisterSpec for PtorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ptor::R`](R) reader structure"] +impl crate::Readable for PtorSpec {} +#[doc = "`write(|w| ..)` method takes [`ptor::W`](W) writer structure"] +impl crate::Writable for PtorSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PTOR to value 0"] +impl crate::Resettable for PtorSpec {} diff --git a/mcxa276-pac/src/gpio0/verid.rs b/mcxa276-pac/src/gpio0/verid.rs new file mode 100644 index 000000000..76e8a3874 --- /dev/null +++ b/mcxa276-pac/src/gpio0/verid.rs @@ -0,0 +1,76 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Basic implementation"] + Feature0 = 0, + #[doc = "1: Protection registers implemented"] + Feature1 = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Feature0), + 1 => Some(Feature::Feature1), + _ => None, + } + } + #[doc = "Basic implementation"] + #[inline(always)] + pub fn is_feature0(&self) -> bool { + *self == Feature::Feature0 + } + #[doc = "Protection registers implemented"] + #[inline(always)] + pub fn is_feature1(&self) -> bool { + *self == Feature::Feature1 + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0201_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0201_0000; +} diff --git a/mcxa276-pac/src/i3c0.rs b/mcxa276-pac/src/i3c0.rs new file mode 100644 index 000000000..31bb9d14b --- /dev/null +++ b/mcxa276-pac/src/i3c0.rs @@ -0,0 +1,639 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mconfig: Mconfig, + sconfig: Sconfig, + sstatus: Sstatus, + sctrl: Sctrl, + sintset: Sintset, + sintclr: Sintclr, + sintmasked: Sintmasked, + serrwarn: Serrwarn, + sdmactrl: Sdmactrl, + _reserved9: [u8; 0x08], + sdatactrl: Sdatactrl, + swdatab: Swdatab, + swdatabe: Swdatabe, + swdatah: Swdatah, + swdatahe: Swdatahe, + srdatab: Srdatab, + _reserved15: [u8; 0x04], + srdatah: Srdatah, + _reserved16: [u8; 0x08], + _reserved_16_byte_swdatab1: [u8; 0x04], + _reserved17: [u8; 0x04], + scapabilities2: Scapabilities2, + scapabilities: Scapabilities, + sdynaddr: Sdynaddr, + smaxlimits: Smaxlimits, + sidpartno: Sidpartno, + sidext: Sidext, + svendorid: Svendorid, + stcclock: Stcclock, + smsgmapaddr: Smsgmapaddr, + mconfig_ext: MconfigExt, + mctrl: Mctrl, + mstatus: Mstatus, + mibirules: Mibirules, + mintset: Mintset, + mintclr: Mintclr, + mintmasked: Mintmasked, + merrwarn: Merrwarn, + mdmactrl: Mdmactrl, + _reserved35: [u8; 0x08], + mdatactrl: Mdatactrl, + mwdatab: Mwdatab, + mwdatabe: Mwdatabe, + mwdatah: Mwdatah, + mwdatahe: Mwdatahe, + mrdatab: Mrdatab, + _reserved41: [u8; 0x04], + mrdatah: Mrdatah, + _reserved_42_byte_mwdatab1: [u8; 0x04], + _reserved_43_data_mwmsg_sdr_data: [u8; 0x04], + mrmsg_sdr: MrmsgSdr, + _reserved_45_data_mwmsg_ddr_data: [u8; 0x04], + mrmsg_ddr: MrmsgDdr, + _reserved47: [u8; 0x04], + mdynaddr: Mdynaddr, + _reserved48: [u8; 0x34], + smapctrl0: Smapctrl0, + _reserved49: [u8; 0x20], + ibiext1: Ibiext1, + ibiext2: Ibiext2, + _reserved51: [u8; 0x0eb4], + sid: Sid, +} +impl RegisterBlock { + #[doc = "0x00 - Controller Configuration"] + #[inline(always)] + pub const fn mconfig(&self) -> &Mconfig { + &self.mconfig + } + #[doc = "0x04 - Target Configuration"] + #[inline(always)] + pub const fn sconfig(&self) -> &Sconfig { + &self.sconfig + } + #[doc = "0x08 - Target Status"] + #[inline(always)] + pub const fn sstatus(&self) -> &Sstatus { + &self.sstatus + } + #[doc = "0x0c - Target Control"] + #[inline(always)] + pub const fn sctrl(&self) -> &Sctrl { + &self.sctrl + } + #[doc = "0x10 - Target Interrupt Set"] + #[inline(always)] + pub const fn sintset(&self) -> &Sintset { + &self.sintset + } + #[doc = "0x14 - Target Interrupt Clear"] + #[inline(always)] + pub const fn sintclr(&self) -> &Sintclr { + &self.sintclr + } + #[doc = "0x18 - Target Interrupt Mask"] + #[inline(always)] + pub const fn sintmasked(&self) -> &Sintmasked { + &self.sintmasked + } + #[doc = "0x1c - Target Errors and Warnings"] + #[inline(always)] + pub const fn serrwarn(&self) -> &Serrwarn { + &self.serrwarn + } + #[doc = "0x20 - Target DMA Control"] + #[inline(always)] + pub const fn sdmactrl(&self) -> &Sdmactrl { + &self.sdmactrl + } + #[doc = "0x2c - Target Data Control"] + #[inline(always)] + pub const fn sdatactrl(&self) -> &Sdatactrl { + &self.sdatactrl + } + #[doc = "0x30 - Target Write Data Byte"] + #[inline(always)] + pub const fn swdatab(&self) -> &Swdatab { + &self.swdatab + } + #[doc = "0x34 - Target Write Data Byte End"] + #[inline(always)] + pub const fn swdatabe(&self) -> &Swdatabe { + &self.swdatabe + } + #[doc = "0x38 - Target Write Data Halfword"] + #[inline(always)] + pub const fn swdatah(&self) -> &Swdatah { + &self.swdatah + } + #[doc = "0x3c - Target Write Data Halfword End"] + #[inline(always)] + pub const fn swdatahe(&self) -> &Swdatahe { + &self.swdatahe + } + #[doc = "0x40 - Target Read Data Byte"] + #[inline(always)] + pub const fn srdatab(&self) -> &Srdatab { + &self.srdatab + } + #[doc = "0x48 - Target Read Data Halfword"] + #[inline(always)] + pub const fn srdatah(&self) -> &Srdatah { + &self.srdatah + } + #[doc = "0x54 - Target Write Data Halfword"] + #[inline(always)] + pub const fn halfword_swdatah1(&self) -> &HalfwordSwdatah1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(84).cast() } + } + #[doc = "0x54 - Target Write Data Byte"] + #[inline(always)] + pub const fn byte_swdatab1(&self) -> &ByteSwdatab1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(84).cast() } + } + #[doc = "0x5c - Target Capabilities 2"] + #[inline(always)] + pub const fn scapabilities2(&self) -> &Scapabilities2 { + &self.scapabilities2 + } + #[doc = "0x60 - Target Capabilities"] + #[inline(always)] + pub const fn scapabilities(&self) -> &Scapabilities { + &self.scapabilities + } + #[doc = "0x64 - Target Dynamic Address"] + #[inline(always)] + pub const fn sdynaddr(&self) -> &Sdynaddr { + &self.sdynaddr + } + #[doc = "0x68 - Target Maximum Limits"] + #[inline(always)] + pub const fn smaxlimits(&self) -> &Smaxlimits { + &self.smaxlimits + } + #[doc = "0x6c - Target ID Part Number"] + #[inline(always)] + pub const fn sidpartno(&self) -> &Sidpartno { + &self.sidpartno + } + #[doc = "0x70 - Target ID Extension"] + #[inline(always)] + pub const fn sidext(&self) -> &Sidext { + &self.sidext + } + #[doc = "0x74 - Target Vendor ID"] + #[inline(always)] + pub const fn svendorid(&self) -> &Svendorid { + &self.svendorid + } + #[doc = "0x78 - Target Time Control Clock"] + #[inline(always)] + pub const fn stcclock(&self) -> &Stcclock { + &self.stcclock + } + #[doc = "0x7c - Target Message Map Address"] + #[inline(always)] + pub const fn smsgmapaddr(&self) -> &Smsgmapaddr { + &self.smsgmapaddr + } + #[doc = "0x80 - Controller Extended Configuration"] + #[inline(always)] + pub const fn mconfig_ext(&self) -> &MconfigExt { + &self.mconfig_ext + } + #[doc = "0x84 - Controller Control"] + #[inline(always)] + pub const fn mctrl(&self) -> &Mctrl { + &self.mctrl + } + #[doc = "0x88 - Controller Status"] + #[inline(always)] + pub const fn mstatus(&self) -> &Mstatus { + &self.mstatus + } + #[doc = "0x8c - Controller In-band Interrupt Registry and Rules"] + #[inline(always)] + pub const fn mibirules(&self) -> &Mibirules { + &self.mibirules + } + #[doc = "0x90 - Controller Interrupt Set"] + #[inline(always)] + pub const fn mintset(&self) -> &Mintset { + &self.mintset + } + #[doc = "0x94 - Controller Interrupt Clear"] + #[inline(always)] + pub const fn mintclr(&self) -> &Mintclr { + &self.mintclr + } + #[doc = "0x98 - Controller Interrupt Mask"] + #[inline(always)] + pub const fn mintmasked(&self) -> &Mintmasked { + &self.mintmasked + } + #[doc = "0x9c - Controller Errors and Warnings"] + #[inline(always)] + pub const fn merrwarn(&self) -> &Merrwarn { + &self.merrwarn + } + #[doc = "0xa0 - Controller DMA Control"] + #[inline(always)] + pub const fn mdmactrl(&self) -> &Mdmactrl { + &self.mdmactrl + } + #[doc = "0xac - Controller Data Control"] + #[inline(always)] + pub const fn mdatactrl(&self) -> &Mdatactrl { + &self.mdatactrl + } + #[doc = "0xb0 - Controller Write Data Byte"] + #[inline(always)] + pub const fn mwdatab(&self) -> &Mwdatab { + &self.mwdatab + } + #[doc = "0xb4 - Controller Write Data Byte End"] + #[inline(always)] + pub const fn mwdatabe(&self) -> &Mwdatabe { + &self.mwdatabe + } + #[doc = "0xb8 - Controller Write Data Halfword"] + #[inline(always)] + pub const fn mwdatah(&self) -> &Mwdatah { + &self.mwdatah + } + #[doc = "0xbc - Controller Write Data Halfword End"] + #[inline(always)] + pub const fn mwdatahe(&self) -> &Mwdatahe { + &self.mwdatahe + } + #[doc = "0xc0 - Controller Read Data Byte"] + #[inline(always)] + pub const fn mrdatab(&self) -> &Mrdatab { + &self.mrdatab + } + #[doc = "0xc8 - Controller Read Data Halfword"] + #[inline(always)] + pub const fn mrdatah(&self) -> &Mrdatah { + &self.mrdatah + } + #[doc = "0xcc - Controller Write Halfword Data (to Bus)"] + #[inline(always)] + pub const fn halfword_mwdatah1(&self) -> &HalfwordMwdatah1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } + } + #[doc = "0xcc - Controller Write Byte Data 1 (to Bus)"] + #[inline(always)] + pub const fn byte_mwdatab1(&self) -> &ByteMwdatab1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } + } + #[doc = "0xd0 - Controller Write Message Data in SDR mode"] + #[inline(always)] + pub const fn data_mwmsg_sdr_data(&self) -> &DataMwmsgSdrData { + unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } + } + #[doc = "0xd0 - Controller Write Message Control in SDR mode"] + #[inline(always)] + pub const fn control_mwmsg_sdr_control(&self) -> &ControlMwmsgSdrControl { + unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } + } + #[doc = "0xd4 - Controller Read Message in SDR mode"] + #[inline(always)] + pub const fn mrmsg_sdr(&self) -> &MrmsgSdr { + &self.mrmsg_sdr + } + #[doc = "0xd8 - Controller Write Message Data in DDR mode"] + #[inline(always)] + pub const fn data_mwmsg_ddr_data(&self) -> &DataMwmsgDdrData { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xd8 - Controller Write Message in DDR Mode Control 2"] + #[inline(always)] + pub const fn control2_mwmsg_ddr_control2(&self) -> &Control2MwmsgDdrControl2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xd8 - Controller Write Message in DDR mode: First Control Word"] + #[inline(always)] + pub const fn control_mwmsg_ddr_control(&self) -> &ControlMwmsgDdrControl { + unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } + } + #[doc = "0xdc - Controller Read Message in DDR mode"] + #[inline(always)] + pub const fn mrmsg_ddr(&self) -> &MrmsgDdr { + &self.mrmsg_ddr + } + #[doc = "0xe4 - Controller Dynamic Address"] + #[inline(always)] + pub const fn mdynaddr(&self) -> &Mdynaddr { + &self.mdynaddr + } + #[doc = "0x11c - Map Feature Control 0"] + #[inline(always)] + pub const fn smapctrl0(&self) -> &Smapctrl0 { + &self.smapctrl0 + } + #[doc = "0x140 - Extended IBI Data 1"] + #[inline(always)] + pub const fn ibiext1(&self) -> &Ibiext1 { + &self.ibiext1 + } + #[doc = "0x144 - Extended IBI Data 2"] + #[inline(always)] + pub const fn ibiext2(&self) -> &Ibiext2 { + &self.ibiext2 + } + #[doc = "0xffc - Target Module ID"] + #[inline(always)] + pub const fn sid(&self) -> &Sid { + &self.sid + } +} +#[doc = "MCONFIG (rw) register accessor: Controller Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mconfig`] module"] +#[doc(alias = "MCONFIG")] +pub type Mconfig = crate::Reg; +#[doc = "Controller Configuration"] +pub mod mconfig; +#[doc = "SCONFIG (rw) register accessor: Target Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`sconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sconfig`] module"] +#[doc(alias = "SCONFIG")] +pub type Sconfig = crate::Reg; +#[doc = "Target Configuration"] +pub mod sconfig; +#[doc = "SSTATUS (rw) register accessor: Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sstatus`] module"] +#[doc(alias = "SSTATUS")] +pub type Sstatus = crate::Reg; +#[doc = "Target Status"] +pub mod sstatus; +#[doc = "SCTRL (rw) register accessor: Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sctrl`] module"] +#[doc(alias = "SCTRL")] +pub type Sctrl = crate::Reg; +#[doc = "Target Control"] +pub mod sctrl; +#[doc = "SINTSET (rw) register accessor: Target Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`sintset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sintset`] module"] +#[doc(alias = "SINTSET")] +pub type Sintset = crate::Reg; +#[doc = "Target Interrupt Set"] +pub mod sintset; +#[doc = "SINTCLR (rw) register accessor: Target Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sintclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sintclr`] module"] +#[doc(alias = "SINTCLR")] +pub type Sintclr = crate::Reg; +#[doc = "Target Interrupt Clear"] +pub mod sintclr; +#[doc = "SINTMASKED (r) register accessor: Target Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`sintmasked::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sintmasked`] module"] +#[doc(alias = "SINTMASKED")] +pub type Sintmasked = crate::Reg; +#[doc = "Target Interrupt Mask"] +pub mod sintmasked; +#[doc = "SERRWARN (rw) register accessor: Target Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`serrwarn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serrwarn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@serrwarn`] module"] +#[doc(alias = "SERRWARN")] +pub type Serrwarn = crate::Reg; +#[doc = "Target Errors and Warnings"] +pub mod serrwarn; +#[doc = "SDMACTRL (rw) register accessor: Target DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdmactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdmactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmactrl`] module"] +#[doc(alias = "SDMACTRL")] +pub type Sdmactrl = crate::Reg; +#[doc = "Target DMA Control"] +pub mod sdmactrl; +#[doc = "SDATACTRL (rw) register accessor: Target Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdatactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdatactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdatactrl`] module"] +#[doc(alias = "SDATACTRL")] +pub type Sdatactrl = crate::Reg; +#[doc = "Target Data Control"] +pub mod sdatactrl; +#[doc = "SWDATAB (w) register accessor: Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatab::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatab`] module"] +#[doc(alias = "SWDATAB")] +pub type Swdatab = crate::Reg; +#[doc = "Target Write Data Byte"] +pub mod swdatab; +#[doc = "SWDATABE (w) register accessor: Target Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatabe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatabe`] module"] +#[doc(alias = "SWDATABE")] +pub type Swdatabe = crate::Reg; +#[doc = "Target Write Data Byte End"] +pub mod swdatabe; +#[doc = "SWDATAH (w) register accessor: Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatah::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatah`] module"] +#[doc(alias = "SWDATAH")] +pub type Swdatah = crate::Reg; +#[doc = "Target Write Data Halfword"] +pub mod swdatah; +#[doc = "SWDATAHE (w) register accessor: Target Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatahe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatahe`] module"] +#[doc(alias = "SWDATAHE")] +pub type Swdatahe = crate::Reg; +#[doc = "Target Write Data Halfword End"] +pub mod swdatahe; +#[doc = "SRDATAB (r) register accessor: Target Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatab::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdatab`] module"] +#[doc(alias = "SRDATAB")] +pub type Srdatab = crate::Reg; +#[doc = "Target Read Data Byte"] +pub mod srdatab; +#[doc = "SRDATAH (r) register accessor: Target Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatah::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdatah`] module"] +#[doc(alias = "SRDATAH")] +pub type Srdatah = crate::Reg; +#[doc = "Target Read Data Halfword"] +pub mod srdatah; +#[doc = "Byte_SWDATAB1 (w) register accessor: Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_swdatab1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@byte_swdatab1`] module"] +#[doc(alias = "Byte_SWDATAB1")] +pub type ByteSwdatab1 = crate::Reg; +#[doc = "Target Write Data Byte"] +pub mod byte_swdatab1; +#[doc = "Halfword_SWDATAH1 (w) register accessor: Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_swdatah1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halfword_swdatah1`] module"] +#[doc(alias = "Halfword_SWDATAH1")] +pub type HalfwordSwdatah1 = crate::Reg; +#[doc = "Target Write Data Halfword"] +pub mod halfword_swdatah1; +#[doc = "SCAPABILITIES2 (r) register accessor: Target Capabilities 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scapabilities2`] module"] +#[doc(alias = "SCAPABILITIES2")] +pub type Scapabilities2 = crate::Reg; +#[doc = "Target Capabilities 2"] +pub mod scapabilities2; +#[doc = "SCAPABILITIES (r) register accessor: Target Capabilities\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scapabilities`] module"] +#[doc(alias = "SCAPABILITIES")] +pub type Scapabilities = crate::Reg; +#[doc = "Target Capabilities"] +pub mod scapabilities; +#[doc = "SDYNADDR (rw) register accessor: Target Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sdynaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdynaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdynaddr`] module"] +#[doc(alias = "SDYNADDR")] +pub type Sdynaddr = crate::Reg; +#[doc = "Target Dynamic Address"] +pub mod sdynaddr; +#[doc = "SMAXLIMITS (rw) register accessor: Target Maximum Limits\n\nYou can [`read`](crate::Reg::read) this register and get [`smaxlimits::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smaxlimits::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smaxlimits`] module"] +#[doc(alias = "SMAXLIMITS")] +pub type Smaxlimits = crate::Reg; +#[doc = "Target Maximum Limits"] +pub mod smaxlimits; +#[doc = "SIDPARTNO (rw) register accessor: Target ID Part Number\n\nYou can [`read`](crate::Reg::read) this register and get [`sidpartno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidpartno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sidpartno`] module"] +#[doc(alias = "SIDPARTNO")] +pub type Sidpartno = crate::Reg; +#[doc = "Target ID Part Number"] +pub mod sidpartno; +#[doc = "SIDEXT (rw) register accessor: Target ID Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`sidext::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidext::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sidext`] module"] +#[doc(alias = "SIDEXT")] +pub type Sidext = crate::Reg; +#[doc = "Target ID Extension"] +pub mod sidext; +#[doc = "SVENDORID (rw) register accessor: Target Vendor ID\n\nYou can [`read`](crate::Reg::read) this register and get [`svendorid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`svendorid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@svendorid`] module"] +#[doc(alias = "SVENDORID")] +pub type Svendorid = crate::Reg; +#[doc = "Target Vendor ID"] +pub mod svendorid; +#[doc = "STCCLOCK (rw) register accessor: Target Time Control Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`stcclock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stcclock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stcclock`] module"] +#[doc(alias = "STCCLOCK")] +pub type Stcclock = crate::Reg; +#[doc = "Target Time Control Clock"] +pub mod stcclock; +#[doc = "SMSGMAPADDR (r) register accessor: Target Message Map Address\n\nYou can [`read`](crate::Reg::read) this register and get [`smsgmapaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smsgmapaddr`] module"] +#[doc(alias = "SMSGMAPADDR")] +pub type Smsgmapaddr = crate::Reg; +#[doc = "Target Message Map Address"] +pub mod smsgmapaddr; +#[doc = "MCONFIG_EXT (rw) register accessor: Controller Extended Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig_ext::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig_ext::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mconfig_ext`] module"] +#[doc(alias = "MCONFIG_EXT")] +pub type MconfigExt = crate::Reg; +#[doc = "Controller Extended Configuration"] +pub mod mconfig_ext; +#[doc = "MCTRL (rw) register accessor: Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctrl`] module"] +#[doc(alias = "MCTRL")] +pub type Mctrl = crate::Reg; +#[doc = "Controller Control"] +pub mod mctrl; +#[doc = "MSTATUS (rw) register accessor: Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mstatus`] module"] +#[doc(alias = "MSTATUS")] +pub type Mstatus = crate::Reg; +#[doc = "Controller Status"] +pub mod mstatus; +#[doc = "MIBIRULES (rw) register accessor: Controller In-band Interrupt Registry and Rules\n\nYou can [`read`](crate::Reg::read) this register and get [`mibirules::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mibirules::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mibirules`] module"] +#[doc(alias = "MIBIRULES")] +pub type Mibirules = crate::Reg; +#[doc = "Controller In-band Interrupt Registry and Rules"] +pub mod mibirules; +#[doc = "MINTSET (rw) register accessor: Controller Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`mintset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintset`] module"] +#[doc(alias = "MINTSET")] +pub type Mintset = crate::Reg; +#[doc = "Controller Interrupt Set"] +pub mod mintset; +#[doc = "MINTCLR (rw) register accessor: Controller Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`mintclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintclr`] module"] +#[doc(alias = "MINTCLR")] +pub type Mintclr = crate::Reg; +#[doc = "Controller Interrupt Clear"] +pub mod mintclr; +#[doc = "MINTMASKED (r) register accessor: Controller Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mintmasked::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintmasked`] module"] +#[doc(alias = "MINTMASKED")] +pub type Mintmasked = crate::Reg; +#[doc = "Controller Interrupt Mask"] +pub mod mintmasked; +#[doc = "MERRWARN (rw) register accessor: Controller Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`merrwarn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`merrwarn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@merrwarn`] module"] +#[doc(alias = "MERRWARN")] +pub type Merrwarn = crate::Reg; +#[doc = "Controller Errors and Warnings"] +pub mod merrwarn; +#[doc = "MDMACTRL (rw) register accessor: Controller DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdmactrl`] module"] +#[doc(alias = "MDMACTRL")] +pub type Mdmactrl = crate::Reg; +#[doc = "Controller DMA Control"] +pub mod mdmactrl; +#[doc = "MDATACTRL (rw) register accessor: Controller Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdatactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdatactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdatactrl`] module"] +#[doc(alias = "MDATACTRL")] +pub type Mdatactrl = crate::Reg; +#[doc = "Controller Data Control"] +pub mod mdatactrl; +#[doc = "MWDATAB (w) register accessor: Controller Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatab::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatab`] module"] +#[doc(alias = "MWDATAB")] +pub type Mwdatab = crate::Reg; +#[doc = "Controller Write Data Byte"] +pub mod mwdatab; +#[doc = "MWDATABE (w) register accessor: Controller Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatabe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatabe`] module"] +#[doc(alias = "MWDATABE")] +pub type Mwdatabe = crate::Reg; +#[doc = "Controller Write Data Byte End"] +pub mod mwdatabe; +#[doc = "MWDATAH (w) register accessor: Controller Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatah::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatah`] module"] +#[doc(alias = "MWDATAH")] +pub type Mwdatah = crate::Reg; +#[doc = "Controller Write Data Halfword"] +pub mod mwdatah; +#[doc = "MWDATAHE (w) register accessor: Controller Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatahe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatahe`] module"] +#[doc(alias = "MWDATAHE")] +pub type Mwdatahe = crate::Reg; +#[doc = "Controller Write Data Halfword End"] +pub mod mwdatahe; +#[doc = "MRDATAB (r) register accessor: Controller Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatab::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdatab`] module"] +#[doc(alias = "MRDATAB")] +pub type Mrdatab = crate::Reg; +#[doc = "Controller Read Data Byte"] +pub mod mrdatab; +#[doc = "MRDATAH (r) register accessor: Controller Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatah::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdatah`] module"] +#[doc(alias = "MRDATAH")] +pub type Mrdatah = crate::Reg; +#[doc = "Controller Read Data Halfword"] +pub mod mrdatah; +#[doc = "BYTE_MWDATAB1 (w) register accessor: Controller Write Byte Data 1 (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_mwdatab1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@byte_mwdatab1`] module"] +#[doc(alias = "BYTE_MWDATAB1")] +pub type ByteMwdatab1 = crate::Reg; +#[doc = "Controller Write Byte Data 1 (to Bus)"] +pub mod byte_mwdatab1; +#[doc = "HALFWORD_MWDATAH1 (w) register accessor: Controller Write Halfword Data (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_mwdatah1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halfword_mwdatah1`] module"] +#[doc(alias = "HALFWORD_MWDATAH1")] +pub type HalfwordMwdatah1 = crate::Reg; +#[doc = "Controller Write Halfword Data (to Bus)"] +pub mod halfword_mwdatah1; +#[doc = "CONTROL_MWMSG_SDR_CONTROL (w) register accessor: Controller Write Message Control in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_sdr_control::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control_mwmsg_sdr_control`] module"] +#[doc(alias = "CONTROL_MWMSG_SDR_CONTROL")] +pub type ControlMwmsgSdrControl = crate::Reg; +#[doc = "Controller Write Message Control in SDR mode"] +pub mod control_mwmsg_sdr_control; +#[doc = "DATA_MWMSG_SDR_DATA (w) register accessor: Controller Write Message Data in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_sdr_data::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_mwmsg_sdr_data`] module"] +#[doc(alias = "DATA_MWMSG_SDR_DATA")] +pub type DataMwmsgSdrData = crate::Reg; +#[doc = "Controller Write Message Data in SDR mode"] +pub mod data_mwmsg_sdr_data; +#[doc = "MRMSG_SDR (r) register accessor: Controller Read Message in SDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_sdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrmsg_sdr`] module"] +#[doc(alias = "MRMSG_SDR")] +pub type MrmsgSdr = crate::Reg; +#[doc = "Controller Read Message in SDR mode"] +pub mod mrmsg_sdr; +#[doc = "CONTROL_MWMSG_DDR_CONTROL (w) register accessor: Controller Write Message in DDR mode: First Control Word\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_ddr_control::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control_mwmsg_ddr_control`] module"] +#[doc(alias = "CONTROL_MWMSG_DDR_CONTROL")] +pub type ControlMwmsgDdrControl = crate::Reg; +#[doc = "Controller Write Message in DDR mode: First Control Word"] +pub mod control_mwmsg_ddr_control; +#[doc = "CONTROL2_MWMSG_DDR_CONTROL2 (w) register accessor: Controller Write Message in DDR Mode Control 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control2_mwmsg_ddr_control2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control2_mwmsg_ddr_control2`] module"] +#[doc(alias = "CONTROL2_MWMSG_DDR_CONTROL2")] +pub type Control2MwmsgDdrControl2 = + crate::Reg; +#[doc = "Controller Write Message in DDR Mode Control 2"] +pub mod control2_mwmsg_ddr_control2; +#[doc = "DATA_MWMSG_DDR_DATA (w) register accessor: Controller Write Message Data in DDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_ddr_data::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_mwmsg_ddr_data`] module"] +#[doc(alias = "DATA_MWMSG_DDR_DATA")] +pub type DataMwmsgDdrData = crate::Reg; +#[doc = "Controller Write Message Data in DDR mode"] +pub mod data_mwmsg_ddr_data; +#[doc = "MRMSG_DDR (r) register accessor: Controller Read Message in DDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_ddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrmsg_ddr`] module"] +#[doc(alias = "MRMSG_DDR")] +pub type MrmsgDdr = crate::Reg; +#[doc = "Controller Read Message in DDR mode"] +pub mod mrmsg_ddr; +#[doc = "MDYNADDR (rw) register accessor: Controller Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mdynaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdynaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdynaddr`] module"] +#[doc(alias = "MDYNADDR")] +pub type Mdynaddr = crate::Reg; +#[doc = "Controller Dynamic Address"] +pub mod mdynaddr; +#[doc = "SMAPCTRL0 (r) register accessor: Map Feature Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`smapctrl0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smapctrl0`] module"] +#[doc(alias = "SMAPCTRL0")] +pub type Smapctrl0 = crate::Reg; +#[doc = "Map Feature Control 0"] +pub mod smapctrl0; +#[doc = "IBIEXT1 (rw) register accessor: Extended IBI Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibiext1`] module"] +#[doc(alias = "IBIEXT1")] +pub type Ibiext1 = crate::Reg; +#[doc = "Extended IBI Data 1"] +pub mod ibiext1; +#[doc = "IBIEXT2 (rw) register accessor: Extended IBI Data 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibiext2`] module"] +#[doc(alias = "IBIEXT2")] +pub type Ibiext2 = crate::Reg; +#[doc = "Extended IBI Data 2"] +pub mod ibiext2; +#[doc = "SID (r) register accessor: Target Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sid`] module"] +#[doc(alias = "SID")] +pub type Sid = crate::Reg; +#[doc = "Target Module ID"] +pub mod sid; diff --git a/mcxa276-pac/src/i3c0/byte_mwdatab1.rs b/mcxa276-pac/src/i3c0/byte_mwdatab1.rs new file mode 100644 index 000000000..e32cde5d1 --- /dev/null +++ b/mcxa276-pac/src/i3c0/byte_mwdatab1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MWDATAB1` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` writer - Value"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Value"] + #[inline(always)] + pub fn value(&mut self) -> ValueW { + ValueW::new(self, 0) + } +} +#[doc = "Controller Write Byte Data 1 (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_mwdatab1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ByteMwdatab1Spec; +impl crate::RegisterSpec for ByteMwdatab1Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`byte_mwdatab1::W`](W) writer structure"] +impl crate::Writable for ByteMwdatab1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWDATAB1 to value 0"] +impl crate::Resettable for ByteMwdatab1Spec {} diff --git a/mcxa276-pac/src/i3c0/byte_swdatab1.rs b/mcxa276-pac/src/i3c0/byte_swdatab1.rs new file mode 100644 index 000000000..1e3015ee5 --- /dev/null +++ b/mcxa276-pac/src/i3c0/byte_swdatab1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SWDATAB1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_swdatab1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ByteSwdatab1Spec; +impl crate::RegisterSpec for ByteSwdatab1Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`byte_swdatab1::W`](W) writer structure"] +impl crate::Writable for ByteSwdatab1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWDATAB1 to value 0"] +impl crate::Resettable for ByteSwdatab1Spec {} diff --git a/mcxa276-pac/src/i3c0/control2_mwmsg_ddr_control2.rs b/mcxa276-pac/src/i3c0/control2_mwmsg_ddr_control2.rs new file mode 100644 index 000000000..0f7963eae --- /dev/null +++ b/mcxa276-pac/src/i3c0/control2_mwmsg_ddr_control2.rs @@ -0,0 +1,58 @@ +#[doc = "Register `MWMSG_DDR_CONTROL2` writer"] +pub type W = crate::W; +#[doc = "Field `LEN` writer - Length of Message"] +pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "End of Message\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum End { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: End) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - End of Message"] +pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; +impl<'a, REG> EndW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(End::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(End::End) + } +} +impl W { + #[doc = "Bits 0:9 - Length of Message"] + #[inline(always)] + pub fn len(&mut self) -> LenW { + LenW::new(self, 0) + } + #[doc = "Bit 14 - End of Message"] + #[inline(always)] + pub fn end(&mut self) -> EndW { + EndW::new(self, 14) + } +} +#[doc = "Controller Write Message in DDR Mode Control 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control2_mwmsg_ddr_control2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Control2MwmsgDdrControl2Spec; +impl crate::RegisterSpec for Control2MwmsgDdrControl2Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`control2_mwmsg_ddr_control2::W`](W) writer structure"] +impl crate::Writable for Control2MwmsgDdrControl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWMSG_DDR_CONTROL2 to value 0"] +impl crate::Resettable for Control2MwmsgDdrControl2Spec {} diff --git a/mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs b/mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs new file mode 100644 index 000000000..155c85e33 --- /dev/null +++ b/mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MWMSG_DDR_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRCMD` writer - Address Command"] +pub type AddrcmdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - Address Command"] + #[inline(always)] + pub fn addrcmd(&mut self) -> AddrcmdW { + AddrcmdW::new(self, 0) + } +} +#[doc = "Controller Write Message in DDR mode: First Control Word\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_ddr_control::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ControlMwmsgDdrControlSpec; +impl crate::RegisterSpec for ControlMwmsgDdrControlSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`control_mwmsg_ddr_control::W`](W) writer structure"] +impl crate::Writable for ControlMwmsgDdrControlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWMSG_DDR_CONTROL to value 0"] +impl crate::Resettable for ControlMwmsgDdrControlSpec {} diff --git a/mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs b/mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs new file mode 100644 index 000000000..511e4049b --- /dev/null +++ b/mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs @@ -0,0 +1,137 @@ +#[doc = "Register `MWMSG_SDR_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dir { + #[doc = "0: Write"] + Write = 0, + #[doc = "1: Read"] + Read = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dir) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIR` writer - Direction"] +pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>; +impl<'a, REG> DirW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write"] + #[inline(always)] + pub fn write(self) -> &'a mut crate::W { + self.variant(Dir::Write) + } + #[doc = "Read"] + #[inline(always)] + pub fn read(self) -> &'a mut crate::W { + self.variant(Dir::Read) + } +} +#[doc = "Field `ADDR` writer - Address"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "End of SDR Message\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum End { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: End) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - End of SDR Message"] +pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; +impl<'a, REG> EndW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(End::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(End::End) + } +} +#[doc = "I2C\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I2c { + #[doc = "0: I3C message"] + I3cmessage = 0, + #[doc = "1: I2C message"] + I2cmessage = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I2c) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I2C` writer - I2C"] +pub type I2cW<'a, REG> = crate::BitWriter<'a, REG, I2c>; +impl<'a, REG> I2cW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "I3C message"] + #[inline(always)] + pub fn i3cmessage(self) -> &'a mut crate::W { + self.variant(I2c::I3cmessage) + } + #[doc = "I2C message"] + #[inline(always)] + pub fn i2cmessage(self) -> &'a mut crate::W { + self.variant(I2c::I2cmessage) + } +} +#[doc = "Field `LEN` writer - Length"] +pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl W { + #[doc = "Bit 0 - Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DirW { + DirW::new(self, 0) + } + #[doc = "Bits 1:7 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 1) + } + #[doc = "Bit 8 - End of SDR Message"] + #[inline(always)] + pub fn end(&mut self) -> EndW { + EndW::new(self, 8) + } + #[doc = "Bit 10 - I2C"] + #[inline(always)] + pub fn i2c(&mut self) -> I2cW { + I2cW::new(self, 10) + } + #[doc = "Bits 11:15 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LenW { + LenW::new(self, 11) + } +} +#[doc = "Controller Write Message Control in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_sdr_control::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ControlMwmsgSdrControlSpec; +impl crate::RegisterSpec for ControlMwmsgSdrControlSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`control_mwmsg_sdr_control::W`](W) writer structure"] +impl crate::Writable for ControlMwmsgSdrControlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWMSG_SDR_CONTROL to value 0"] +impl crate::Resettable for ControlMwmsgSdrControlSpec {} diff --git a/mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs b/mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs new file mode 100644 index 000000000..c747baf48 --- /dev/null +++ b/mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MWMSG_DDR_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DATA16B` writer - Data"] +pub type Data16bW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - Data"] + #[inline(always)] + pub fn data16b(&mut self) -> Data16bW { + Data16bW::new(self, 0) + } +} +#[doc = "Controller Write Message Data in DDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_ddr_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataMwmsgDdrDataSpec; +impl crate::RegisterSpec for DataMwmsgDdrDataSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`data_mwmsg_ddr_data::W`](W) writer structure"] +impl crate::Writable for DataMwmsgDdrDataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWMSG_DDR_DATA to value 0"] +impl crate::Resettable for DataMwmsgDdrDataSpec {} diff --git a/mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs b/mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs new file mode 100644 index 000000000..0ffebbf4d --- /dev/null +++ b/mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MWMSG_SDR_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DATA16B` writer - Data"] +pub type Data16bW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - Data"] + #[inline(always)] + pub fn data16b(&mut self) -> Data16bW { + Data16bW::new(self, 0) + } +} +#[doc = "Controller Write Message Data in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_sdr_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataMwmsgSdrDataSpec; +impl crate::RegisterSpec for DataMwmsgSdrDataSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`data_mwmsg_sdr_data::W`](W) writer structure"] +impl crate::Writable for DataMwmsgSdrDataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWMSG_SDR_DATA to value 0"] +impl crate::Resettable for DataMwmsgSdrDataSpec {} diff --git a/mcxa276-pac/src/i3c0/halfword_mwdatah1.rs b/mcxa276-pac/src/i3c0/halfword_mwdatah1.rs new file mode 100644 index 000000000..c7ed2ed65 --- /dev/null +++ b/mcxa276-pac/src/i3c0/halfword_mwdatah1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MWDATAH1` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` writer - Value"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - Value"] + #[inline(always)] + pub fn value(&mut self) -> ValueW { + ValueW::new(self, 0) + } +} +#[doc = "Controller Write Halfword Data (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_mwdatah1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HalfwordMwdatah1Spec; +impl crate::RegisterSpec for HalfwordMwdatah1Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`halfword_mwdatah1::W`](W) writer structure"] +impl crate::Writable for HalfwordMwdatah1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWDATAH1 to value 0"] +impl crate::Resettable for HalfwordMwdatah1Spec {} diff --git a/mcxa276-pac/src/i3c0/halfword_swdatah1.rs b/mcxa276-pac/src/i3c0/halfword_swdatah1.rs new file mode 100644 index 000000000..1e409f566 --- /dev/null +++ b/mcxa276-pac/src/i3c0/halfword_swdatah1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SWDATAH1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_swdatah1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HalfwordSwdatah1Spec; +impl crate::RegisterSpec for HalfwordSwdatah1Spec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`halfword_swdatah1::W`](W) writer structure"] +impl crate::Writable for HalfwordSwdatah1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWDATAH1 to value 0"] +impl crate::Resettable for HalfwordSwdatah1Spec {} diff --git a/mcxa276-pac/src/i3c0/ibiext1.rs b/mcxa276-pac/src/i3c0/ibiext1.rs new file mode 100644 index 000000000..86a545869 --- /dev/null +++ b/mcxa276-pac/src/i3c0/ibiext1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `IBIEXT1` reader"] +pub type R = crate::R; +#[doc = "Register `IBIEXT1` writer"] +pub type W = crate::W; +#[doc = "Field `CNT` reader - Count"] +pub type CntR = crate::FieldReader; +#[doc = "Field `CNT` writer - Count"] +pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MAX` reader - Maximum"] +pub type MaxR = crate::FieldReader; +#[doc = "Field `EXT1` reader - Extra Byte 1"] +pub type Ext1R = crate::FieldReader; +#[doc = "Field `EXT1` writer - Extra Byte 1"] +pub type Ext1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EXT2` reader - Extra Byte 2"] +pub type Ext2R = crate::FieldReader; +#[doc = "Field `EXT2` writer - Extra Byte 2"] +pub type Ext2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EXT3` reader - Extra Byte 3"] +pub type Ext3R = crate::FieldReader; +#[doc = "Field `EXT3` writer - Extra Byte 3"] +pub type Ext3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:2 - Count"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:6 - Maximum"] + #[inline(always)] + pub fn max(&self) -> MaxR { + MaxR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bits 8:15 - Extra Byte 1"] + #[inline(always)] + pub fn ext1(&self) -> Ext1R { + Ext1R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Extra Byte 2"] + #[inline(always)] + pub fn ext2(&self) -> Ext2R { + Ext2R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Extra Byte 3"] + #[inline(always)] + pub fn ext3(&self) -> Ext3R { + Ext3R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Count"] + #[inline(always)] + pub fn cnt(&mut self) -> CntW { + CntW::new(self, 0) + } + #[doc = "Bits 8:15 - Extra Byte 1"] + #[inline(always)] + pub fn ext1(&mut self) -> Ext1W { + Ext1W::new(self, 8) + } + #[doc = "Bits 16:23 - Extra Byte 2"] + #[inline(always)] + pub fn ext2(&mut self) -> Ext2W { + Ext2W::new(self, 16) + } + #[doc = "Bits 24:31 - Extra Byte 3"] + #[inline(always)] + pub fn ext3(&mut self) -> Ext3W { + Ext3W::new(self, 24) + } +} +#[doc = "Extended IBI Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ibiext1Spec; +impl crate::RegisterSpec for Ibiext1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibiext1::R`](R) reader structure"] +impl crate::Readable for Ibiext1Spec {} +#[doc = "`write(|w| ..)` method takes [`ibiext1::W`](W) writer structure"] +impl crate::Writable for Ibiext1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IBIEXT1 to value 0x70"] +impl crate::Resettable for Ibiext1Spec { + const RESET_VALUE: u32 = 0x70; +} diff --git a/mcxa276-pac/src/i3c0/ibiext2.rs b/mcxa276-pac/src/i3c0/ibiext2.rs new file mode 100644 index 000000000..163a8f0da --- /dev/null +++ b/mcxa276-pac/src/i3c0/ibiext2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IBIEXT2` reader"] +pub type R = crate::R; +#[doc = "Register `IBIEXT2` writer"] +pub type W = crate::W; +#[doc = "Field `EXT4` reader - Extra Byte 4"] +pub type Ext4R = crate::FieldReader; +#[doc = "Field `EXT4` writer - Extra Byte 4"] +pub type Ext4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EXT5` reader - Extra Byte 5"] +pub type Ext5R = crate::FieldReader; +#[doc = "Field `EXT5` writer - Extra Byte 5"] +pub type Ext5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EXT6` reader - Extra Byte 6"] +pub type Ext6R = crate::FieldReader; +#[doc = "Field `EXT6` writer - Extra Byte 6"] +pub type Ext6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EXT7` reader - Extra Byte 7"] +pub type Ext7R = crate::FieldReader; +#[doc = "Field `EXT7` writer - Extra Byte 7"] +pub type Ext7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Extra Byte 4"] + #[inline(always)] + pub fn ext4(&self) -> Ext4R { + Ext4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Extra Byte 5"] + #[inline(always)] + pub fn ext5(&self) -> Ext5R { + Ext5R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Extra Byte 6"] + #[inline(always)] + pub fn ext6(&self) -> Ext6R { + Ext6R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Extra Byte 7"] + #[inline(always)] + pub fn ext7(&self) -> Ext7R { + Ext7R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Extra Byte 4"] + #[inline(always)] + pub fn ext4(&mut self) -> Ext4W { + Ext4W::new(self, 0) + } + #[doc = "Bits 8:15 - Extra Byte 5"] + #[inline(always)] + pub fn ext5(&mut self) -> Ext5W { + Ext5W::new(self, 8) + } + #[doc = "Bits 16:23 - Extra Byte 6"] + #[inline(always)] + pub fn ext6(&mut self) -> Ext6W { + Ext6W::new(self, 16) + } + #[doc = "Bits 24:31 - Extra Byte 7"] + #[inline(always)] + pub fn ext7(&mut self) -> Ext7W { + Ext7W::new(self, 24) + } +} +#[doc = "Extended IBI Data 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ibiext2Spec; +impl crate::RegisterSpec for Ibiext2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibiext2::R`](R) reader structure"] +impl crate::Readable for Ibiext2Spec {} +#[doc = "`write(|w| ..)` method takes [`ibiext2::W`](W) writer structure"] +impl crate::Writable for Ibiext2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IBIEXT2 to value 0"] +impl crate::Resettable for Ibiext2Spec {} diff --git a/mcxa276-pac/src/i3c0/mconfig.rs b/mcxa276-pac/src/i3c0/mconfig.rs new file mode 100644 index 000000000..d69d1d395 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mconfig.rs @@ -0,0 +1,472 @@ +#[doc = "Register `MCONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `MCONFIG` writer"] +pub type W = crate::W; +#[doc = "Controller Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mstena { + #[doc = "0: CONTROLLER_OFF"] + MasterOff = 0, + #[doc = "1: CONTROLLER_ON"] + MasterOn = 1, + #[doc = "2: CONTROLLER_CAPABLE"] + MasterCapable = 2, + #[doc = "3: I2C_CONTROLLER_MODE"] + I2cMasterMode = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mstena) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mstena { + type Ux = u8; +} +impl crate::IsEnum for Mstena {} +#[doc = "Field `MSTENA` reader - Controller Enable"] +pub type MstenaR = crate::FieldReader; +impl MstenaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mstena { + match self.bits { + 0 => Mstena::MasterOff, + 1 => Mstena::MasterOn, + 2 => Mstena::MasterCapable, + 3 => Mstena::I2cMasterMode, + _ => unreachable!(), + } + } + #[doc = "CONTROLLER_OFF"] + #[inline(always)] + pub fn is_master_off(&self) -> bool { + *self == Mstena::MasterOff + } + #[doc = "CONTROLLER_ON"] + #[inline(always)] + pub fn is_master_on(&self) -> bool { + *self == Mstena::MasterOn + } + #[doc = "CONTROLLER_CAPABLE"] + #[inline(always)] + pub fn is_master_capable(&self) -> bool { + *self == Mstena::MasterCapable + } + #[doc = "I2C_CONTROLLER_MODE"] + #[inline(always)] + pub fn is_i2c_master_mode(&self) -> bool { + *self == Mstena::I2cMasterMode + } +} +#[doc = "Field `MSTENA` writer - Controller Enable"] +pub type MstenaW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mstena, crate::Safe>; +impl<'a, REG> MstenaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CONTROLLER_OFF"] + #[inline(always)] + pub fn master_off(self) -> &'a mut crate::W { + self.variant(Mstena::MasterOff) + } + #[doc = "CONTROLLER_ON"] + #[inline(always)] + pub fn master_on(self) -> &'a mut crate::W { + self.variant(Mstena::MasterOn) + } + #[doc = "CONTROLLER_CAPABLE"] + #[inline(always)] + pub fn master_capable(self) -> &'a mut crate::W { + self.variant(Mstena::MasterCapable) + } + #[doc = "I2C_CONTROLLER_MODE"] + #[inline(always)] + pub fn i2c_master_mode(self) -> &'a mut crate::W { + self.variant(Mstena::I2cMasterMode) + } +} +#[doc = "Disable Timeout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Disto { + #[doc = "0: Enabled"] + Enable = 0, + #[doc = "1: Disabled, if configured"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Disto) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DISTO` reader - Disable Timeout"] +pub type DistoR = crate::BitReader; +impl DistoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Disto { + match self.bits { + false => Disto::Enable, + true => Disto::Disable, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Disto::Enable + } + #[doc = "Disabled, if configured"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Disto::Disable + } +} +#[doc = "Field `DISTO` writer - Disable Timeout"] +pub type DistoW<'a, REG> = crate::BitWriter<'a, REG, Disto>; +impl<'a, REG> DistoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Disto::Enable) + } + #[doc = "Disabled, if configured"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Disto::Disable) + } +} +#[doc = "High-Keeper\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Hkeep { + #[doc = "0: None"] + None = 0, + #[doc = "1: WIRED_IN"] + WiredIn = 1, + #[doc = "2: PASSIVE_SDA (I2C mode, no clock stretches mode)"] + PassiveSda = 2, + #[doc = "3: PASSIVE_ON_SDA_SCL"] + PassiveOnSdaScl = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Hkeep) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Hkeep { + type Ux = u8; +} +impl crate::IsEnum for Hkeep {} +#[doc = "Field `HKEEP` reader - High-Keeper"] +pub type HkeepR = crate::FieldReader; +impl HkeepR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hkeep { + match self.bits { + 0 => Hkeep::None, + 1 => Hkeep::WiredIn, + 2 => Hkeep::PassiveSda, + 3 => Hkeep::PassiveOnSdaScl, + _ => unreachable!(), + } + } + #[doc = "None"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Hkeep::None + } + #[doc = "WIRED_IN"] + #[inline(always)] + pub fn is_wired_in(&self) -> bool { + *self == Hkeep::WiredIn + } + #[doc = "PASSIVE_SDA (I2C mode, no clock stretches mode)"] + #[inline(always)] + pub fn is_passive_sda(&self) -> bool { + *self == Hkeep::PassiveSda + } + #[doc = "PASSIVE_ON_SDA_SCL"] + #[inline(always)] + pub fn is_passive_on_sda_scl(&self) -> bool { + *self == Hkeep::PassiveOnSdaScl + } +} +#[doc = "Field `HKEEP` writer - High-Keeper"] +pub type HkeepW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hkeep, crate::Safe>; +impl<'a, REG> HkeepW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "None"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Hkeep::None) + } + #[doc = "WIRED_IN"] + #[inline(always)] + pub fn wired_in(self) -> &'a mut crate::W { + self.variant(Hkeep::WiredIn) + } + #[doc = "PASSIVE_SDA (I2C mode, no clock stretches mode)"] + #[inline(always)] + pub fn passive_sda(self) -> &'a mut crate::W { + self.variant(Hkeep::PassiveSda) + } + #[doc = "PASSIVE_ON_SDA_SCL"] + #[inline(always)] + pub fn passive_on_sda_scl(self) -> &'a mut crate::W { + self.variant(Hkeep::PassiveOnSdaScl) + } +} +#[doc = "Open-drain Stop\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Odstop { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Odstop) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODSTOP` reader - Open-drain Stop"] +pub type OdstopR = crate::BitReader; +impl OdstopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Odstop { + match self.bits { + false => Odstop::Disable, + true => Odstop::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Odstop::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Odstop::Enable + } +} +#[doc = "Field `ODSTOP` writer - Open-drain Stop"] +pub type OdstopW<'a, REG> = crate::BitWriter<'a, REG, Odstop>; +impl<'a, REG> OdstopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Odstop::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Odstop::Enable) + } +} +#[doc = "Field `PPBAUD` reader - Push-Pull Baud Rate"] +pub type PpbaudR = crate::FieldReader; +#[doc = "Field `PPBAUD` writer - Push-Pull Baud Rate"] +pub type PpbaudW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PPLOW` reader - Push-Pull Low"] +pub type PplowR = crate::FieldReader; +#[doc = "Field `PPLOW` writer - Push-Pull Low"] +pub type PplowW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ODBAUD` reader - Open-drain Baud Rate"] +pub type OdbaudR = crate::FieldReader; +#[doc = "Field `ODBAUD` writer - Open-drain Baud Rate"] +pub type OdbaudW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Open-drain High Push-Pull\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Odhpp { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Odhpp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODHPP` reader - Open-drain High Push-Pull"] +pub type OdhppR = crate::BitReader; +impl OdhppR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Odhpp { + match self.bits { + false => Odhpp::Disable, + true => Odhpp::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Odhpp::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Odhpp::Enable + } +} +#[doc = "Field `ODHPP` writer - Open-drain High Push-Pull"] +pub type OdhppW<'a, REG> = crate::BitWriter<'a, REG, Odhpp>; +impl<'a, REG> OdhppW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Odhpp::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Odhpp::Enable) + } +} +#[doc = "Field `SKEW` reader - Skew"] +pub type SkewR = crate::FieldReader; +#[doc = "Field `SKEW` writer - Skew"] +pub type SkewW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `I2CBAUD` reader - I2C Baud Rate"] +pub type I2cbaudR = crate::FieldReader; +#[doc = "Field `I2CBAUD` writer - I2C Baud Rate"] +pub type I2cbaudW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:1 - Controller Enable"] + #[inline(always)] + pub fn mstena(&self) -> MstenaR { + MstenaR::new((self.bits & 3) as u8) + } + #[doc = "Bit 3 - Disable Timeout"] + #[inline(always)] + pub fn disto(&self) -> DistoR { + DistoR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - High-Keeper"] + #[inline(always)] + pub fn hkeep(&self) -> HkeepR { + HkeepR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Open-drain Stop"] + #[inline(always)] + pub fn odstop(&self) -> OdstopR { + OdstopR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Push-Pull Baud Rate"] + #[inline(always)] + pub fn ppbaud(&self) -> PpbaudR { + PpbaudR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Push-Pull Low"] + #[inline(always)] + pub fn pplow(&self) -> PplowR { + PplowR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:23 - Open-drain Baud Rate"] + #[inline(always)] + pub fn odbaud(&self) -> OdbaudR { + OdbaudR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - Open-drain High Push-Pull"] + #[inline(always)] + pub fn odhpp(&self) -> OdhppR { + OdhppR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - Skew"] + #[inline(always)] + pub fn skew(&self) -> SkewR { + SkewR::new(((self.bits >> 25) & 7) as u8) + } + #[doc = "Bits 28:31 - I2C Baud Rate"] + #[inline(always)] + pub fn i2cbaud(&self) -> I2cbaudR { + I2cbaudR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Controller Enable"] + #[inline(always)] + pub fn mstena(&mut self) -> MstenaW { + MstenaW::new(self, 0) + } + #[doc = "Bit 3 - Disable Timeout"] + #[inline(always)] + pub fn disto(&mut self) -> DistoW { + DistoW::new(self, 3) + } + #[doc = "Bits 4:5 - High-Keeper"] + #[inline(always)] + pub fn hkeep(&mut self) -> HkeepW { + HkeepW::new(self, 4) + } + #[doc = "Bit 6 - Open-drain Stop"] + #[inline(always)] + pub fn odstop(&mut self) -> OdstopW { + OdstopW::new(self, 6) + } + #[doc = "Bits 8:11 - Push-Pull Baud Rate"] + #[inline(always)] + pub fn ppbaud(&mut self) -> PpbaudW { + PpbaudW::new(self, 8) + } + #[doc = "Bits 12:15 - Push-Pull Low"] + #[inline(always)] + pub fn pplow(&mut self) -> PplowW { + PplowW::new(self, 12) + } + #[doc = "Bits 16:23 - Open-drain Baud Rate"] + #[inline(always)] + pub fn odbaud(&mut self) -> OdbaudW { + OdbaudW::new(self, 16) + } + #[doc = "Bit 24 - Open-drain High Push-Pull"] + #[inline(always)] + pub fn odhpp(&mut self) -> OdhppW { + OdhppW::new(self, 24) + } + #[doc = "Bits 25:27 - Skew"] + #[inline(always)] + pub fn skew(&mut self) -> SkewW { + SkewW::new(self, 25) + } + #[doc = "Bits 28:31 - I2C Baud Rate"] + #[inline(always)] + pub fn i2cbaud(&mut self) -> I2cbaudW { + I2cbaudW::new(self, 28) + } +} +#[doc = "Controller Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MconfigSpec; +impl crate::RegisterSpec for MconfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mconfig::R`](R) reader structure"] +impl crate::Readable for MconfigSpec {} +#[doc = "`write(|w| ..)` method takes [`mconfig::W`](W) writer structure"] +impl crate::Writable for MconfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCONFIG to value 0"] +impl crate::Resettable for MconfigSpec {} diff --git a/mcxa276-pac/src/i3c0/mconfig_ext.rs b/mcxa276-pac/src/i3c0/mconfig_ext.rs new file mode 100644 index 000000000..4b4c2d9b6 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mconfig_ext.rs @@ -0,0 +1,213 @@ +#[doc = "Register `MCONFIG_EXT` reader"] +pub type R = crate::R; +#[doc = "Register `MCONFIG_EXT` writer"] +pub type W = crate::W; +#[doc = "I3C CAS Delay After START\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum I3cCasDel { + #[doc = "0: No delay"] + NoDelay = 0, + #[doc = "1: Increases SCL clock period by 1/2"] + OneHalfClk = 1, + #[doc = "2: Increases SCL clock period by 1"] + OneClk = 2, + #[doc = "3: Increases SCL clock period by 3/2"] + OneAndOneHalfClk = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: I3cCasDel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for I3cCasDel { + type Ux = u8; +} +impl crate::IsEnum for I3cCasDel {} +#[doc = "Field `I3C_CAS_DEL` reader - I3C CAS Delay After START"] +pub type I3cCasDelR = crate::FieldReader; +impl I3cCasDelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I3cCasDel { + match self.bits { + 0 => I3cCasDel::NoDelay, + 1 => I3cCasDel::OneHalfClk, + 2 => I3cCasDel::OneClk, + 3 => I3cCasDel::OneAndOneHalfClk, + _ => unreachable!(), + } + } + #[doc = "No delay"] + #[inline(always)] + pub fn is_no_delay(&self) -> bool { + *self == I3cCasDel::NoDelay + } + #[doc = "Increases SCL clock period by 1/2"] + #[inline(always)] + pub fn is_one_half_clk(&self) -> bool { + *self == I3cCasDel::OneHalfClk + } + #[doc = "Increases SCL clock period by 1"] + #[inline(always)] + pub fn is_one_clk(&self) -> bool { + *self == I3cCasDel::OneClk + } + #[doc = "Increases SCL clock period by 3/2"] + #[inline(always)] + pub fn is_one_and_one_half_clk(&self) -> bool { + *self == I3cCasDel::OneAndOneHalfClk + } +} +#[doc = "Field `I3C_CAS_DEL` writer - I3C CAS Delay After START"] +pub type I3cCasDelW<'a, REG> = crate::FieldWriter<'a, REG, 2, I3cCasDel, crate::Safe>; +impl<'a, REG> I3cCasDelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No delay"] + #[inline(always)] + pub fn no_delay(self) -> &'a mut crate::W { + self.variant(I3cCasDel::NoDelay) + } + #[doc = "Increases SCL clock period by 1/2"] + #[inline(always)] + pub fn one_half_clk(self) -> &'a mut crate::W { + self.variant(I3cCasDel::OneHalfClk) + } + #[doc = "Increases SCL clock period by 1"] + #[inline(always)] + pub fn one_clk(self) -> &'a mut crate::W { + self.variant(I3cCasDel::OneClk) + } + #[doc = "Increases SCL clock period by 3/2"] + #[inline(always)] + pub fn one_and_one_half_clk(self) -> &'a mut crate::W { + self.variant(I3cCasDel::OneAndOneHalfClk) + } +} +#[doc = "I3C CAS Delay After Repeated START\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum I3cCasrDel { + #[doc = "0: No delay"] + NoDelay = 0, + #[doc = "1: Increases SCL clock period by 1/2"] + OneHalfClk = 1, + #[doc = "2: Increases SCL clock period by 1"] + OneClk = 2, + #[doc = "3: Increases SCL clock period by 1 1/2"] + OneAndOneHalfClk = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: I3cCasrDel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for I3cCasrDel { + type Ux = u8; +} +impl crate::IsEnum for I3cCasrDel {} +#[doc = "Field `I3C_CASR_DEL` reader - I3C CAS Delay After Repeated START"] +pub type I3cCasrDelR = crate::FieldReader; +impl I3cCasrDelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I3cCasrDel { + match self.bits { + 0 => I3cCasrDel::NoDelay, + 1 => I3cCasrDel::OneHalfClk, + 2 => I3cCasrDel::OneClk, + 3 => I3cCasrDel::OneAndOneHalfClk, + _ => unreachable!(), + } + } + #[doc = "No delay"] + #[inline(always)] + pub fn is_no_delay(&self) -> bool { + *self == I3cCasrDel::NoDelay + } + #[doc = "Increases SCL clock period by 1/2"] + #[inline(always)] + pub fn is_one_half_clk(&self) -> bool { + *self == I3cCasrDel::OneHalfClk + } + #[doc = "Increases SCL clock period by 1"] + #[inline(always)] + pub fn is_one_clk(&self) -> bool { + *self == I3cCasrDel::OneClk + } + #[doc = "Increases SCL clock period by 1 1/2"] + #[inline(always)] + pub fn is_one_and_one_half_clk(&self) -> bool { + *self == I3cCasrDel::OneAndOneHalfClk + } +} +#[doc = "Field `I3C_CASR_DEL` writer - I3C CAS Delay After Repeated START"] +pub type I3cCasrDelW<'a, REG> = crate::FieldWriter<'a, REG, 2, I3cCasrDel, crate::Safe>; +impl<'a, REG> I3cCasrDelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No delay"] + #[inline(always)] + pub fn no_delay(self) -> &'a mut crate::W { + self.variant(I3cCasrDel::NoDelay) + } + #[doc = "Increases SCL clock period by 1/2"] + #[inline(always)] + pub fn one_half_clk(self) -> &'a mut crate::W { + self.variant(I3cCasrDel::OneHalfClk) + } + #[doc = "Increases SCL clock period by 1"] + #[inline(always)] + pub fn one_clk(self) -> &'a mut crate::W { + self.variant(I3cCasrDel::OneClk) + } + #[doc = "Increases SCL clock period by 1 1/2"] + #[inline(always)] + pub fn one_and_one_half_clk(self) -> &'a mut crate::W { + self.variant(I3cCasrDel::OneAndOneHalfClk) + } +} +impl R { + #[doc = "Bits 16:17 - I3C CAS Delay After START"] + #[inline(always)] + pub fn i3c_cas_del(&self) -> I3cCasDelR { + I3cCasDelR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - I3C CAS Delay After Repeated START"] + #[inline(always)] + pub fn i3c_casr_del(&self) -> I3cCasrDelR { + I3cCasrDelR::new(((self.bits >> 18) & 3) as u8) + } +} +impl W { + #[doc = "Bits 16:17 - I3C CAS Delay After START"] + #[inline(always)] + pub fn i3c_cas_del(&mut self) -> I3cCasDelW { + I3cCasDelW::new(self, 16) + } + #[doc = "Bits 18:19 - I3C CAS Delay After Repeated START"] + #[inline(always)] + pub fn i3c_casr_del(&mut self) -> I3cCasrDelW { + I3cCasrDelW::new(self, 18) + } +} +#[doc = "Controller Extended Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig_ext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig_ext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MconfigExtSpec; +impl crate::RegisterSpec for MconfigExtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mconfig_ext::R`](R) reader structure"] +impl crate::Readable for MconfigExtSpec {} +#[doc = "`write(|w| ..)` method takes [`mconfig_ext::W`](W) writer structure"] +impl crate::Writable for MconfigExtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCONFIG_EXT to value 0"] +impl crate::Resettable for MconfigExtSpec {} diff --git a/mcxa276-pac/src/i3c0/mctrl.rs b/mcxa276-pac/src/i3c0/mctrl.rs new file mode 100644 index 000000000..58c9b7105 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mctrl.rs @@ -0,0 +1,426 @@ +#[doc = "Register `MCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MCTRL` writer"] +pub type W = crate::W; +#[doc = "Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Request { + #[doc = "0: NONE"] + None = 0, + #[doc = "1: EMITSTARTADDR"] + Emitstartaddr = 1, + #[doc = "2: EMITSTOP"] + Emitstop = 2, + #[doc = "3: IBIACKNACK"] + Ibiacknack = 3, + #[doc = "4: PROCESSDAA"] + Processdaa = 4, + #[doc = "6: Force Exit and Target Reset"] + Forceexit = 6, + #[doc = "7: AUTOIBI"] + Autoibi = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Request) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Request { + type Ux = u8; +} +impl crate::IsEnum for Request {} +#[doc = "Field `REQUEST` reader - Request"] +pub type RequestR = crate::FieldReader; +impl RequestR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Request::None), + 1 => Some(Request::Emitstartaddr), + 2 => Some(Request::Emitstop), + 3 => Some(Request::Ibiacknack), + 4 => Some(Request::Processdaa), + 6 => Some(Request::Forceexit), + 7 => Some(Request::Autoibi), + _ => None, + } + } + #[doc = "NONE"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Request::None + } + #[doc = "EMITSTARTADDR"] + #[inline(always)] + pub fn is_emitstartaddr(&self) -> bool { + *self == Request::Emitstartaddr + } + #[doc = "EMITSTOP"] + #[inline(always)] + pub fn is_emitstop(&self) -> bool { + *self == Request::Emitstop + } + #[doc = "IBIACKNACK"] + #[inline(always)] + pub fn is_ibiacknack(&self) -> bool { + *self == Request::Ibiacknack + } + #[doc = "PROCESSDAA"] + #[inline(always)] + pub fn is_processdaa(&self) -> bool { + *self == Request::Processdaa + } + #[doc = "Force Exit and Target Reset"] + #[inline(always)] + pub fn is_forceexit(&self) -> bool { + *self == Request::Forceexit + } + #[doc = "AUTOIBI"] + #[inline(always)] + pub fn is_autoibi(&self) -> bool { + *self == Request::Autoibi + } +} +#[doc = "Field `REQUEST` writer - Request"] +pub type RequestW<'a, REG> = crate::FieldWriter<'a, REG, 3, Request>; +impl<'a, REG> RequestW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "NONE"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Request::None) + } + #[doc = "EMITSTARTADDR"] + #[inline(always)] + pub fn emitstartaddr(self) -> &'a mut crate::W { + self.variant(Request::Emitstartaddr) + } + #[doc = "EMITSTOP"] + #[inline(always)] + pub fn emitstop(self) -> &'a mut crate::W { + self.variant(Request::Emitstop) + } + #[doc = "IBIACKNACK"] + #[inline(always)] + pub fn ibiacknack(self) -> &'a mut crate::W { + self.variant(Request::Ibiacknack) + } + #[doc = "PROCESSDAA"] + #[inline(always)] + pub fn processdaa(self) -> &'a mut crate::W { + self.variant(Request::Processdaa) + } + #[doc = "Force Exit and Target Reset"] + #[inline(always)] + pub fn forceexit(self) -> &'a mut crate::W { + self.variant(Request::Forceexit) + } + #[doc = "AUTOIBI"] + #[inline(always)] + pub fn autoibi(self) -> &'a mut crate::W { + self.variant(Request::Autoibi) + } +} +#[doc = "Bus Type with EmitStartAddr\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Type { + #[doc = "0: I3C"] + I3c = 0, + #[doc = "1: I2C"] + I2c = 1, + #[doc = "2: DDR"] + Ddr = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Type) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Type { + type Ux = u8; +} +impl crate::IsEnum for Type {} +#[doc = "Field `TYPE` reader - Bus Type with EmitStartAddr"] +pub type TypeR = crate::FieldReader; +impl TypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Type::I3c), + 1 => Some(Type::I2c), + 2 => Some(Type::Ddr), + _ => None, + } + } + #[doc = "I3C"] + #[inline(always)] + pub fn is_i3c(&self) -> bool { + *self == Type::I3c + } + #[doc = "I2C"] + #[inline(always)] + pub fn is_i2c(&self) -> bool { + *self == Type::I2c + } + #[doc = "DDR"] + #[inline(always)] + pub fn is_ddr(&self) -> bool { + *self == Type::Ddr + } +} +#[doc = "Field `TYPE` writer - Bus Type with EmitStartAddr"] +pub type TypeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Type>; +impl<'a, REG> TypeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "I3C"] + #[inline(always)] + pub fn i3c(self) -> &'a mut crate::W { + self.variant(Type::I3c) + } + #[doc = "I2C"] + #[inline(always)] + pub fn i2c(self) -> &'a mut crate::W { + self.variant(Type::I2c) + } + #[doc = "DDR"] + #[inline(always)] + pub fn ddr(self) -> &'a mut crate::W { + self.variant(Type::Ddr) + } +} +#[doc = "In-Band Interrupt Response\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ibiresp { + #[doc = "0: ACK (acknowledge)"] + Ack = 0, + #[doc = "1: NACK (reject)"] + Nack = 1, + #[doc = "2: Acknowledge with mandatory byte"] + AckWithMandatory = 2, + #[doc = "3: Manual"] + Manual = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ibiresp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ibiresp { + type Ux = u8; +} +impl crate::IsEnum for Ibiresp {} +#[doc = "Field `IBIRESP` reader - In-Band Interrupt Response"] +pub type IbirespR = crate::FieldReader; +impl IbirespR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibiresp { + match self.bits { + 0 => Ibiresp::Ack, + 1 => Ibiresp::Nack, + 2 => Ibiresp::AckWithMandatory, + 3 => Ibiresp::Manual, + _ => unreachable!(), + } + } + #[doc = "ACK (acknowledge)"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + *self == Ibiresp::Ack + } + #[doc = "NACK (reject)"] + #[inline(always)] + pub fn is_nack(&self) -> bool { + *self == Ibiresp::Nack + } + #[doc = "Acknowledge with mandatory byte"] + #[inline(always)] + pub fn is_ack_with_mandatory(&self) -> bool { + *self == Ibiresp::AckWithMandatory + } + #[doc = "Manual"] + #[inline(always)] + pub fn is_manual(&self) -> bool { + *self == Ibiresp::Manual + } +} +#[doc = "Field `IBIRESP` writer - In-Band Interrupt Response"] +pub type IbirespW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ibiresp, crate::Safe>; +impl<'a, REG> IbirespW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ACK (acknowledge)"] + #[inline(always)] + pub fn ack(self) -> &'a mut crate::W { + self.variant(Ibiresp::Ack) + } + #[doc = "NACK (reject)"] + #[inline(always)] + pub fn nack(self) -> &'a mut crate::W { + self.variant(Ibiresp::Nack) + } + #[doc = "Acknowledge with mandatory byte"] + #[inline(always)] + pub fn ack_with_mandatory(self) -> &'a mut crate::W { + self.variant(Ibiresp::AckWithMandatory) + } + #[doc = "Manual"] + #[inline(always)] + pub fn manual(self) -> &'a mut crate::W { + self.variant(Ibiresp::Manual) + } +} +#[doc = "Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dir { + #[doc = "0: Write"] + Dirwrite = 0, + #[doc = "1: Read"] + Dirread = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dir) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIR` reader - Direction"] +pub type DirR = crate::BitReader; +impl DirR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dir { + match self.bits { + false => Dir::Dirwrite, + true => Dir::Dirread, + } + } + #[doc = "Write"] + #[inline(always)] + pub fn is_dirwrite(&self) -> bool { + *self == Dir::Dirwrite + } + #[doc = "Read"] + #[inline(always)] + pub fn is_dirread(&self) -> bool { + *self == Dir::Dirread + } +} +#[doc = "Field `DIR` writer - Direction"] +pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>; +impl<'a, REG> DirW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write"] + #[inline(always)] + pub fn dirwrite(self) -> &'a mut crate::W { + self.variant(Dir::Dirwrite) + } + #[doc = "Read"] + #[inline(always)] + pub fn dirread(self) -> &'a mut crate::W { + self.variant(Dir::Dirread) + } +} +#[doc = "Field `ADDR` reader - Address"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `RDTERM` reader - Read Terminate Counter"] +pub type RdtermR = crate::FieldReader; +#[doc = "Field `RDTERM` writer - Read Terminate Counter"] +pub type RdtermW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:2 - Request"] + #[inline(always)] + pub fn request(&self) -> RequestR { + RequestR::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:5 - Bus Type with EmitStartAddr"] + #[inline(always)] + pub fn type_(&self) -> TypeR { + TypeR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - In-Band Interrupt Response"] + #[inline(always)] + pub fn ibiresp(&self) -> IbirespR { + IbirespR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - Direction"] + #[inline(always)] + pub fn dir(&self) -> DirR { + DirR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:15 - Address"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new(((self.bits >> 9) & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Read Terminate Counter"] + #[inline(always)] + pub fn rdterm(&self) -> RdtermR { + RdtermR::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Request"] + #[inline(always)] + pub fn request(&mut self) -> RequestW { + RequestW::new(self, 0) + } + #[doc = "Bits 4:5 - Bus Type with EmitStartAddr"] + #[inline(always)] + pub fn type_(&mut self) -> TypeW { + TypeW::new(self, 4) + } + #[doc = "Bits 6:7 - In-Band Interrupt Response"] + #[inline(always)] + pub fn ibiresp(&mut self) -> IbirespW { + IbirespW::new(self, 6) + } + #[doc = "Bit 8 - Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DirW { + DirW::new(self, 8) + } + #[doc = "Bits 9:15 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 9) + } + #[doc = "Bits 16:23 - Read Terminate Counter"] + #[inline(always)] + pub fn rdterm(&mut self) -> RdtermW { + RdtermW::new(self, 16) + } +} +#[doc = "Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MctrlSpec; +impl crate::RegisterSpec for MctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mctrl::R`](R) reader structure"] +impl crate::Readable for MctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mctrl::W`](W) writer structure"] +impl crate::Writable for MctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCTRL to value 0"] +impl crate::Resettable for MctrlSpec {} diff --git a/mcxa276-pac/src/i3c0/mdatactrl.rs b/mcxa276-pac/src/i3c0/mdatactrl.rs new file mode 100644 index 000000000..4b4e39a58 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mdatactrl.rs @@ -0,0 +1,419 @@ +#[doc = "Register `MDATACTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MDATACTRL` writer"] +pub type W = crate::W; +#[doc = "Flush To-Bus Buffer or FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flushtb { + #[doc = "0: No action"] + NoAction = 0, + #[doc = "1: Flush the buffer"] + Flush = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flushtb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLUSHTB` writer - Flush To-Bus Buffer or FIFO"] +pub type FlushtbW<'a, REG> = crate::BitWriter<'a, REG, Flushtb>; +impl<'a, REG> FlushtbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No action"] + #[inline(always)] + pub fn no_action(self) -> &'a mut crate::W { + self.variant(Flushtb::NoAction) + } + #[doc = "Flush the buffer"] + #[inline(always)] + pub fn flush(self) -> &'a mut crate::W { + self.variant(Flushtb::Flush) + } +} +#[doc = "Flush From-Bus Buffer or FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flushfb { + #[doc = "0: No action"] + NoAction = 0, + #[doc = "1: Flush the buffer"] + Flush = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flushfb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLUSHFB` writer - Flush From-Bus Buffer or FIFO"] +pub type FlushfbW<'a, REG> = crate::BitWriter<'a, REG, Flushfb>; +impl<'a, REG> FlushfbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No action"] + #[inline(always)] + pub fn no_action(self) -> &'a mut crate::W { + self.variant(Flushfb::NoAction) + } + #[doc = "Flush the buffer"] + #[inline(always)] + pub fn flush(self) -> &'a mut crate::W { + self.variant(Flushfb::Flush) + } +} +#[doc = "Unlock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unlock { + #[doc = "0: Locked"] + Disabled = 0, + #[doc = "1: Unlocked"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unlock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNLOCK` writer - Unlock"] +pub type UnlockW<'a, REG> = crate::BitWriter<'a, REG, Unlock>; +impl<'a, REG> UnlockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Unlock::Disabled) + } + #[doc = "Unlocked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Unlock::Enabled) + } +} +#[doc = "Transmit Trigger Level\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Txtrig { + #[doc = "0: Trigger when empty"] + Empty = 0, + #[doc = "1: Trigger when 1/4 full or less"] + QuarterOrLess = 1, + #[doc = "2: Trigger when 1/2 full or less"] + HalfOrLess = 2, + #[doc = "3: Trigger when 1 less than full or less (default)"] + FullOrLess = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Txtrig) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Txtrig { + type Ux = u8; +} +impl crate::IsEnum for Txtrig {} +#[doc = "Field `TXTRIG` reader - Transmit Trigger Level"] +pub type TxtrigR = crate::FieldReader; +impl TxtrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txtrig { + match self.bits { + 0 => Txtrig::Empty, + 1 => Txtrig::QuarterOrLess, + 2 => Txtrig::HalfOrLess, + 3 => Txtrig::FullOrLess, + _ => unreachable!(), + } + } + #[doc = "Trigger when empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Txtrig::Empty + } + #[doc = "Trigger when 1/4 full or less"] + #[inline(always)] + pub fn is_quarter_or_less(&self) -> bool { + *self == Txtrig::QuarterOrLess + } + #[doc = "Trigger when 1/2 full or less"] + #[inline(always)] + pub fn is_half_or_less(&self) -> bool { + *self == Txtrig::HalfOrLess + } + #[doc = "Trigger when 1 less than full or less (default)"] + #[inline(always)] + pub fn is_full_or_less(&self) -> bool { + *self == Txtrig::FullOrLess + } +} +#[doc = "Field `TXTRIG` writer - Transmit Trigger Level"] +pub type TxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txtrig, crate::Safe>; +impl<'a, REG> TxtrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Trigger when empty"] + #[inline(always)] + pub fn empty(self) -> &'a mut crate::W { + self.variant(Txtrig::Empty) + } + #[doc = "Trigger when 1/4 full or less"] + #[inline(always)] + pub fn quarter_or_less(self) -> &'a mut crate::W { + self.variant(Txtrig::QuarterOrLess) + } + #[doc = "Trigger when 1/2 full or less"] + #[inline(always)] + pub fn half_or_less(self) -> &'a mut crate::W { + self.variant(Txtrig::HalfOrLess) + } + #[doc = "Trigger when 1 less than full or less (default)"] + #[inline(always)] + pub fn full_or_less(self) -> &'a mut crate::W { + self.variant(Txtrig::FullOrLess) + } +} +#[doc = "Receive Trigger Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Rxtrig { + #[doc = "0: Trigger when not empty (default)"] + NotEmpty = 0, + #[doc = "1: Trigger when 1/4 full or more"] + QuarterOrMore = 1, + #[doc = "2: Trigger when 1/2 full or more"] + HalfOrMore = 2, + #[doc = "3: Trigger when 3/4 full or more"] + ThreeQuarterOrMore = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Rxtrig) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Rxtrig { + type Ux = u8; +} +impl crate::IsEnum for Rxtrig {} +#[doc = "Field `RXTRIG` reader - Receive Trigger Level"] +pub type RxtrigR = crate::FieldReader; +impl RxtrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxtrig { + match self.bits { + 0 => Rxtrig::NotEmpty, + 1 => Rxtrig::QuarterOrMore, + 2 => Rxtrig::HalfOrMore, + 3 => Rxtrig::ThreeQuarterOrMore, + _ => unreachable!(), + } + } + #[doc = "Trigger when not empty (default)"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxtrig::NotEmpty + } + #[doc = "Trigger when 1/4 full or more"] + #[inline(always)] + pub fn is_quarter_or_more(&self) -> bool { + *self == Rxtrig::QuarterOrMore + } + #[doc = "Trigger when 1/2 full or more"] + #[inline(always)] + pub fn is_half_or_more(&self) -> bool { + *self == Rxtrig::HalfOrMore + } + #[doc = "Trigger when 3/4 full or more"] + #[inline(always)] + pub fn is_three_quarter_or_more(&self) -> bool { + *self == Rxtrig::ThreeQuarterOrMore + } +} +#[doc = "Field `RXTRIG` writer - Receive Trigger Level"] +pub type RxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxtrig, crate::Safe>; +impl<'a, REG> RxtrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Trigger when not empty (default)"] + #[inline(always)] + pub fn not_empty(self) -> &'a mut crate::W { + self.variant(Rxtrig::NotEmpty) + } + #[doc = "Trigger when 1/4 full or more"] + #[inline(always)] + pub fn quarter_or_more(self) -> &'a mut crate::W { + self.variant(Rxtrig::QuarterOrMore) + } + #[doc = "Trigger when 1/2 full or more"] + #[inline(always)] + pub fn half_or_more(self) -> &'a mut crate::W { + self.variant(Rxtrig::HalfOrMore) + } + #[doc = "Trigger when 3/4 full or more"] + #[inline(always)] + pub fn three_quarter_or_more(self) -> &'a mut crate::W { + self.variant(Rxtrig::ThreeQuarterOrMore) + } +} +#[doc = "Field `TXCOUNT` reader - Transmit Entry Count"] +pub type TxcountR = crate::FieldReader; +#[doc = "Field `RXCOUNT` reader - Receive Entry Count"] +pub type RxcountR = crate::FieldReader; +#[doc = "Transmit is Full\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txfull { + #[doc = "0: Not full"] + NotFull = 0, + #[doc = "1: Full"] + Full = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txfull) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXFULL` reader - Transmit is Full"] +pub type TxfullR = crate::BitReader; +impl TxfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txfull { + match self.bits { + false => Txfull::NotFull, + true => Txfull::Full, + } + } + #[doc = "Not full"] + #[inline(always)] + pub fn is_not_full(&self) -> bool { + *self == Txfull::NotFull + } + #[doc = "Full"] + #[inline(always)] + pub fn is_full(&self) -> bool { + *self == Txfull::Full + } +} +#[doc = "Receive is Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempty { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPTY` reader - Receive is Empty"] +pub type RxemptyR = crate::BitReader; +impl RxemptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempty { + match self.bits { + false => Rxempty::NotEmpty, + true => Rxempty::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempty::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempty::Empty + } +} +impl R { + #[doc = "Bits 4:5 - Transmit Trigger Level"] + #[inline(always)] + pub fn txtrig(&self) -> TxtrigR { + TxtrigR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Receive Trigger Level"] + #[inline(always)] + pub fn rxtrig(&self) -> RxtrigR { + RxtrigR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 16:20 - Transmit Entry Count"] + #[inline(always)] + pub fn txcount(&self) -> TxcountR { + TxcountR::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - Receive Entry Count"] + #[inline(always)] + pub fn rxcount(&self) -> RxcountR { + RxcountR::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 30 - Transmit is Full"] + #[inline(always)] + pub fn txfull(&self) -> TxfullR { + TxfullR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Receive is Empty"] + #[inline(always)] + pub fn rxempty(&self) -> RxemptyR { + RxemptyR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush To-Bus Buffer or FIFO"] + #[inline(always)] + pub fn flushtb(&mut self) -> FlushtbW { + FlushtbW::new(self, 0) + } + #[doc = "Bit 1 - Flush From-Bus Buffer or FIFO"] + #[inline(always)] + pub fn flushfb(&mut self) -> FlushfbW { + FlushfbW::new(self, 1) + } + #[doc = "Bit 3 - Unlock"] + #[inline(always)] + pub fn unlock(&mut self) -> UnlockW { + UnlockW::new(self, 3) + } + #[doc = "Bits 4:5 - Transmit Trigger Level"] + #[inline(always)] + pub fn txtrig(&mut self) -> TxtrigW { + TxtrigW::new(self, 4) + } + #[doc = "Bits 6:7 - Receive Trigger Level"] + #[inline(always)] + pub fn rxtrig(&mut self) -> RxtrigW { + RxtrigW::new(self, 6) + } +} +#[doc = "Controller Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdatactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdatactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MdatactrlSpec; +impl crate::RegisterSpec for MdatactrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mdatactrl::R`](R) reader structure"] +impl crate::Readable for MdatactrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mdatactrl::W`](W) writer structure"] +impl crate::Writable for MdatactrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MDATACTRL to value 0x8000_0030"] +impl crate::Resettable for MdatactrlSpec { + const RESET_VALUE: u32 = 0x8000_0030; +} diff --git a/mcxa276-pac/src/i3c0/mdmactrl.rs b/mcxa276-pac/src/i3c0/mdmactrl.rs new file mode 100644 index 000000000..6c21d00f2 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mdmactrl.rs @@ -0,0 +1,272 @@ +#[doc = "Register `MDMACTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MDMACTRL` writer"] +pub type W = crate::W; +#[doc = "DMA from Bus\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dmafb { + #[doc = "0: DMA not used"] + NotUsed = 0, + #[doc = "1: Enable DMA for one frame"] + EnableOneFrame = 1, + #[doc = "2: Enable DMA until DMA is turned off"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dmafb) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dmafb { + type Ux = u8; +} +impl crate::IsEnum for Dmafb {} +#[doc = "Field `DMAFB` reader - DMA from Bus"] +pub type DmafbR = crate::FieldReader; +impl DmafbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dmafb::NotUsed), + 1 => Some(Dmafb::EnableOneFrame), + 2 => Some(Dmafb::Enable), + _ => None, + } + } + #[doc = "DMA not used"] + #[inline(always)] + pub fn is_not_used(&self) -> bool { + *self == Dmafb::NotUsed + } + #[doc = "Enable DMA for one frame"] + #[inline(always)] + pub fn is_enable_one_frame(&self) -> bool { + *self == Dmafb::EnableOneFrame + } + #[doc = "Enable DMA until DMA is turned off"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dmafb::Enable + } +} +#[doc = "Field `DMAFB` writer - DMA from Bus"] +pub type DmafbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmafb>; +impl<'a, REG> DmafbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "DMA not used"] + #[inline(always)] + pub fn not_used(self) -> &'a mut crate::W { + self.variant(Dmafb::NotUsed) + } + #[doc = "Enable DMA for one frame"] + #[inline(always)] + pub fn enable_one_frame(self) -> &'a mut crate::W { + self.variant(Dmafb::EnableOneFrame) + } + #[doc = "Enable DMA until DMA is turned off"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dmafb::Enable) + } +} +#[doc = "DMA to Bus\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dmatb { + #[doc = "0: DMA not used"] + NotUsed = 0, + #[doc = "1: Enable DMA for one frame (ended by DMA or terminated)"] + EnableOneFrame = 1, + #[doc = "2: Enable DMA until DMA is turned off"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dmatb) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dmatb { + type Ux = u8; +} +impl crate::IsEnum for Dmatb {} +#[doc = "Field `DMATB` reader - DMA to Bus"] +pub type DmatbR = crate::FieldReader; +impl DmatbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dmatb::NotUsed), + 1 => Some(Dmatb::EnableOneFrame), + 2 => Some(Dmatb::Enable), + _ => None, + } + } + #[doc = "DMA not used"] + #[inline(always)] + pub fn is_not_used(&self) -> bool { + *self == Dmatb::NotUsed + } + #[doc = "Enable DMA for one frame (ended by DMA or terminated)"] + #[inline(always)] + pub fn is_enable_one_frame(&self) -> bool { + *self == Dmatb::EnableOneFrame + } + #[doc = "Enable DMA until DMA is turned off"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dmatb::Enable + } +} +#[doc = "Field `DMATB` writer - DMA to Bus"] +pub type DmatbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmatb>; +impl<'a, REG> DmatbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "DMA not used"] + #[inline(always)] + pub fn not_used(self) -> &'a mut crate::W { + self.variant(Dmatb::NotUsed) + } + #[doc = "Enable DMA for one frame (ended by DMA or terminated)"] + #[inline(always)] + pub fn enable_one_frame(self) -> &'a mut crate::W { + self.variant(Dmatb::EnableOneFrame) + } + #[doc = "Enable DMA until DMA is turned off"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dmatb::Enable) + } +} +#[doc = "DMA Width\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dmawidth { + #[doc = "0: Byte"] + Byte0 = 0, + #[doc = "1: Byte"] + Byte1 = 1, + #[doc = "2: Halfword (16 bits)"] + HalfWord = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dmawidth) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dmawidth { + type Ux = u8; +} +impl crate::IsEnum for Dmawidth {} +#[doc = "Field `DMAWIDTH` reader - DMA Width"] +pub type DmawidthR = crate::FieldReader; +impl DmawidthR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dmawidth::Byte0), + 1 => Some(Dmawidth::Byte1), + 2 => Some(Dmawidth::HalfWord), + _ => None, + } + } + #[doc = "Byte"] + #[inline(always)] + pub fn is_byte_0(&self) -> bool { + *self == Dmawidth::Byte0 + } + #[doc = "Byte"] + #[inline(always)] + pub fn is_byte_1(&self) -> bool { + *self == Dmawidth::Byte1 + } + #[doc = "Halfword (16 bits)"] + #[inline(always)] + pub fn is_half_word(&self) -> bool { + *self == Dmawidth::HalfWord + } +} +#[doc = "Field `DMAWIDTH` writer - DMA Width"] +pub type DmawidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmawidth>; +impl<'a, REG> DmawidthW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Byte"] + #[inline(always)] + pub fn byte_0(self) -> &'a mut crate::W { + self.variant(Dmawidth::Byte0) + } + #[doc = "Byte"] + #[inline(always)] + pub fn byte_1(self) -> &'a mut crate::W { + self.variant(Dmawidth::Byte1) + } + #[doc = "Halfword (16 bits)"] + #[inline(always)] + pub fn half_word(self) -> &'a mut crate::W { + self.variant(Dmawidth::HalfWord) + } +} +impl R { + #[doc = "Bits 0:1 - DMA from Bus"] + #[inline(always)] + pub fn dmafb(&self) -> DmafbR { + DmafbR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - DMA to Bus"] + #[inline(always)] + pub fn dmatb(&self) -> DmatbR { + DmatbR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - DMA Width"] + #[inline(always)] + pub fn dmawidth(&self) -> DmawidthR { + DmawidthR::new(((self.bits >> 4) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - DMA from Bus"] + #[inline(always)] + pub fn dmafb(&mut self) -> DmafbW { + DmafbW::new(self, 0) + } + #[doc = "Bits 2:3 - DMA to Bus"] + #[inline(always)] + pub fn dmatb(&mut self) -> DmatbW { + DmatbW::new(self, 2) + } + #[doc = "Bits 4:5 - DMA Width"] + #[inline(always)] + pub fn dmawidth(&mut self) -> DmawidthW { + DmawidthW::new(self, 4) + } +} +#[doc = "Controller DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MdmactrlSpec; +impl crate::RegisterSpec for MdmactrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mdmactrl::R`](R) reader structure"] +impl crate::Readable for MdmactrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mdmactrl::W`](W) writer structure"] +impl crate::Writable for MdmactrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MDMACTRL to value 0x10"] +impl crate::Resettable for MdmactrlSpec { + const RESET_VALUE: u32 = 0x10; +} diff --git a/mcxa276-pac/src/i3c0/mdynaddr.rs b/mcxa276-pac/src/i3c0/mdynaddr.rs new file mode 100644 index 000000000..0381838ee --- /dev/null +++ b/mcxa276-pac/src/i3c0/mdynaddr.rs @@ -0,0 +1,98 @@ +#[doc = "Register `MDYNADDR` reader"] +pub type R = crate::R; +#[doc = "Register `MDYNADDR` writer"] +pub type W = crate::W; +#[doc = "Dynamic Address Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Davalid { + #[doc = "0: No valid DA assigned"] + NoValid = 0, + #[doc = "1: Valid DA assigned"] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Davalid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAVALID` reader - Dynamic Address Valid"] +pub type DavalidR = crate::BitReader; +impl DavalidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Davalid { + match self.bits { + false => Davalid::NoValid, + true => Davalid::Valid, + } + } + #[doc = "No valid DA assigned"] + #[inline(always)] + pub fn is_no_valid(&self) -> bool { + *self == Davalid::NoValid + } + #[doc = "Valid DA assigned"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Davalid::Valid + } +} +#[doc = "Field `DAVALID` writer - Dynamic Address Valid"] +pub type DavalidW<'a, REG> = crate::BitWriter<'a, REG, Davalid>; +impl<'a, REG> DavalidW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No valid DA assigned"] + #[inline(always)] + pub fn no_valid(self) -> &'a mut crate::W { + self.variant(Davalid::NoValid) + } + #[doc = "Valid DA assigned"] + #[inline(always)] + pub fn valid(self) -> &'a mut crate::W { + self.variant(Davalid::Valid) + } +} +#[doc = "Field `DADDR` reader - Dynamic Address"] +pub type DaddrR = crate::FieldReader; +#[doc = "Field `DADDR` writer - Dynamic Address"] +pub type DaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bit 0 - Dynamic Address Valid"] + #[inline(always)] + pub fn davalid(&self) -> DavalidR { + DavalidR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:7 - Dynamic Address"] + #[inline(always)] + pub fn daddr(&self) -> DaddrR { + DaddrR::new(((self.bits >> 1) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Dynamic Address Valid"] + #[inline(always)] + pub fn davalid(&mut self) -> DavalidW { + DavalidW::new(self, 0) + } + #[doc = "Bits 1:7 - Dynamic Address"] + #[inline(always)] + pub fn daddr(&mut self) -> DaddrW { + DaddrW::new(self, 1) + } +} +#[doc = "Controller Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mdynaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdynaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MdynaddrSpec; +impl crate::RegisterSpec for MdynaddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mdynaddr::R`](R) reader structure"] +impl crate::Readable for MdynaddrSpec {} +#[doc = "`write(|w| ..)` method takes [`mdynaddr::W`](W) writer structure"] +impl crate::Writable for MdynaddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MDYNADDR to value 0"] +impl crate::Resettable for MdynaddrSpec {} diff --git a/mcxa276-pac/src/i3c0/merrwarn.rs b/mcxa276-pac/src/i3c0/merrwarn.rs new file mode 100644 index 000000000..e73710666 --- /dev/null +++ b/mcxa276-pac/src/i3c0/merrwarn.rs @@ -0,0 +1,715 @@ +#[doc = "Register `MERRWARN` reader"] +pub type R = crate::R; +#[doc = "Register `MERRWARN` writer"] +pub type W = crate::W; +#[doc = "Underrun Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Urun { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Urun) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `URUN` reader - Underrun Error Flag"] +pub type UrunR = crate::BitReader; +impl UrunR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Urun { + match self.bits { + false => Urun::NoError, + true => Urun::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Urun::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Urun::Error + } +} +#[doc = "Field `URUN` writer - Underrun Error Flag"] +pub type UrunW<'a, REG> = crate::BitWriter1C<'a, REG, Urun>; +impl<'a, REG> UrunW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Urun::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Urun::Error) + } +} +#[doc = "Not Acknowledge Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nack { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NACK` reader - Not Acknowledge Error Flag"] +pub type NackR = crate::BitReader; +impl NackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nack { + match self.bits { + false => Nack::NoError, + true => Nack::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Nack::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Nack::Error + } +} +#[doc = "Field `NACK` writer - Not Acknowledge Error Flag"] +pub type NackW<'a, REG> = crate::BitWriter1C<'a, REG, Nack>; +impl<'a, REG> NackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Nack::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Nack::Error) + } +} +#[doc = "Write Abort Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wrabt { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wrabt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WRABT` reader - Write Abort Error Flag"] +pub type WrabtR = crate::BitReader; +impl WrabtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wrabt { + match self.bits { + false => Wrabt::NoError, + true => Wrabt::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Wrabt::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Wrabt::Error + } +} +#[doc = "Field `WRABT` writer - Write Abort Error Flag"] +pub type WrabtW<'a, REG> = crate::BitWriter1C<'a, REG, Wrabt>; +impl<'a, REG> WrabtW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Wrabt::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Wrabt::Error) + } +} +#[doc = "Terminate Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Term { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Term) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TERM` reader - Terminate Error Flag"] +pub type TermR = crate::BitReader; +impl TermR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Term { + match self.bits { + false => Term::NoError, + true => Term::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Term::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Term::Error + } +} +#[doc = "Field `TERM` writer - Terminate Error Flag"] +pub type TermW<'a, REG> = crate::BitWriter1C<'a, REG, Term>; +impl<'a, REG> TermW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Term::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Term::Error) + } +} +#[doc = "High Data Rate Parity Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hpar { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hpar) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HPAR` reader - High Data Rate Parity Flag"] +pub type HparR = crate::BitReader; +impl HparR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hpar { + match self.bits { + false => Hpar::NoError, + true => Hpar::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Hpar::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Hpar::Error + } +} +#[doc = "Field `HPAR` writer - High Data Rate Parity Flag"] +pub type HparW<'a, REG> = crate::BitWriter1C<'a, REG, Hpar>; +impl<'a, REG> HparW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Hpar::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Hpar::Error) + } +} +#[doc = "High Data Rate CRC Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hcrc { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hcrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HCRC` reader - High Data Rate CRC Error Flag"] +pub type HcrcR = crate::BitReader; +impl HcrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hcrc { + match self.bits { + false => Hcrc::NoError, + true => Hcrc::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Hcrc::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Hcrc::Error + } +} +#[doc = "Field `HCRC` writer - High Data Rate CRC Error Flag"] +pub type HcrcW<'a, REG> = crate::BitWriter1C<'a, REG, Hcrc>; +impl<'a, REG> HcrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Hcrc::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Hcrc::Error) + } +} +#[doc = "Overread Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oread { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oread) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OREAD` reader - Overread Error Flag"] +pub type OreadR = crate::BitReader; +impl OreadR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oread { + match self.bits { + false => Oread::NoError, + true => Oread::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Oread::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Oread::Error + } +} +#[doc = "Field `OREAD` writer - Overread Error Flag"] +pub type OreadW<'a, REG> = crate::BitWriter1C<'a, REG, Oread>; +impl<'a, REG> OreadW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Oread::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Oread::Error) + } +} +#[doc = "Overwrite Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Owrite { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Owrite) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OWRITE` reader - Overwrite Error Flag"] +pub type OwriteR = crate::BitReader; +impl OwriteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Owrite { + match self.bits { + false => Owrite::NoError, + true => Owrite::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Owrite::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Owrite::Error + } +} +#[doc = "Field `OWRITE` writer - Overwrite Error Flag"] +pub type OwriteW<'a, REG> = crate::BitWriter1C<'a, REG, Owrite>; +impl<'a, REG> OwriteW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Owrite::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Owrite::Error) + } +} +#[doc = "Message Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Msgerr { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Msgerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MSGERR` reader - Message Error Flag"] +pub type MsgerrR = crate::BitReader; +impl MsgerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Msgerr { + match self.bits { + false => Msgerr::NoError, + true => Msgerr::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Msgerr::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Msgerr::Error + } +} +#[doc = "Field `MSGERR` writer - Message Error Flag"] +pub type MsgerrW<'a, REG> = crate::BitWriter1C<'a, REG, Msgerr>; +impl<'a, REG> MsgerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Msgerr::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Msgerr::Error) + } +} +#[doc = "Invalid Request Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Invreq { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Invreq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INVREQ` reader - Invalid Request Error Flag"] +pub type InvreqR = crate::BitReader; +impl InvreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Invreq { + match self.bits { + false => Invreq::NoError, + true => Invreq::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Invreq::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Invreq::Error + } +} +#[doc = "Field `INVREQ` writer - Invalid Request Error Flag"] +pub type InvreqW<'a, REG> = crate::BitWriter1C<'a, REG, Invreq>; +impl<'a, REG> InvreqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Invreq::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Invreq::Error) + } +} +#[doc = "Timeout Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Timeout { + #[doc = "0: No error"] + NoError = 0, + #[doc = "1: Error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Timeout) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIMEOUT` reader - Timeout Error Flag"] +pub type TimeoutR = crate::BitReader; +impl TimeoutR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timeout { + match self.bits { + false => Timeout::NoError, + true => Timeout::Error, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Timeout::NoError + } + #[doc = "Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Timeout::Error + } +} +#[doc = "Field `TIMEOUT` writer - Timeout Error Flag"] +pub type TimeoutW<'a, REG> = crate::BitWriter1C<'a, REG, Timeout>; +impl<'a, REG> TimeoutW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Timeout::NoError) + } + #[doc = "Error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Timeout::Error) + } +} +impl R { + #[doc = "Bit 1 - Underrun Error Flag"] + #[inline(always)] + pub fn urun(&self) -> UrunR { + UrunR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Not Acknowledge Error Flag"] + #[inline(always)] + pub fn nack(&self) -> NackR { + NackR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write Abort Error Flag"] + #[inline(always)] + pub fn wrabt(&self) -> WrabtR { + WrabtR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Terminate Error Flag"] + #[inline(always)] + pub fn term(&self) -> TermR { + TermR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 9 - High Data Rate Parity Flag"] + #[inline(always)] + pub fn hpar(&self) -> HparR { + HparR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High Data Rate CRC Error Flag"] + #[inline(always)] + pub fn hcrc(&self) -> HcrcR { + HcrcR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 16 - Overread Error Flag"] + #[inline(always)] + pub fn oread(&self) -> OreadR { + OreadR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Overwrite Error Flag"] + #[inline(always)] + pub fn owrite(&self) -> OwriteR { + OwriteR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Message Error Flag"] + #[inline(always)] + pub fn msgerr(&self) -> MsgerrR { + MsgerrR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Invalid Request Error Flag"] + #[inline(always)] + pub fn invreq(&self) -> InvreqR { + InvreqR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Timeout Error Flag"] + #[inline(always)] + pub fn timeout(&self) -> TimeoutR { + TimeoutR::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Underrun Error Flag"] + #[inline(always)] + pub fn urun(&mut self) -> UrunW { + UrunW::new(self, 1) + } + #[doc = "Bit 2 - Not Acknowledge Error Flag"] + #[inline(always)] + pub fn nack(&mut self) -> NackW { + NackW::new(self, 2) + } + #[doc = "Bit 3 - Write Abort Error Flag"] + #[inline(always)] + pub fn wrabt(&mut self) -> WrabtW { + WrabtW::new(self, 3) + } + #[doc = "Bit 4 - Terminate Error Flag"] + #[inline(always)] + pub fn term(&mut self) -> TermW { + TermW::new(self, 4) + } + #[doc = "Bit 9 - High Data Rate Parity Flag"] + #[inline(always)] + pub fn hpar(&mut self) -> HparW { + HparW::new(self, 9) + } + #[doc = "Bit 10 - High Data Rate CRC Error Flag"] + #[inline(always)] + pub fn hcrc(&mut self) -> HcrcW { + HcrcW::new(self, 10) + } + #[doc = "Bit 16 - Overread Error Flag"] + #[inline(always)] + pub fn oread(&mut self) -> OreadW { + OreadW::new(self, 16) + } + #[doc = "Bit 17 - Overwrite Error Flag"] + #[inline(always)] + pub fn owrite(&mut self) -> OwriteW { + OwriteW::new(self, 17) + } + #[doc = "Bit 18 - Message Error Flag"] + #[inline(always)] + pub fn msgerr(&mut self) -> MsgerrW { + MsgerrW::new(self, 18) + } + #[doc = "Bit 19 - Invalid Request Error Flag"] + #[inline(always)] + pub fn invreq(&mut self) -> InvreqW { + InvreqW::new(self, 19) + } + #[doc = "Bit 20 - Timeout Error Flag"] + #[inline(always)] + pub fn timeout(&mut self) -> TimeoutW { + TimeoutW::new(self, 20) + } +} +#[doc = "Controller Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`merrwarn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`merrwarn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MerrwarnSpec; +impl crate::RegisterSpec for MerrwarnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`merrwarn::R`](R) reader structure"] +impl crate::Readable for MerrwarnSpec {} +#[doc = "`write(|w| ..)` method takes [`merrwarn::W`](W) writer structure"] +impl crate::Writable for MerrwarnSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_061e; +} +#[doc = "`reset()` method sets MERRWARN to value 0"] +impl crate::Resettable for MerrwarnSpec {} diff --git a/mcxa276-pac/src/i3c0/mibirules.rs b/mcxa276-pac/src/i3c0/mibirules.rs new file mode 100644 index 000000000..256a57ccd --- /dev/null +++ b/mcxa276-pac/src/i3c0/mibirules.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MIBIRULES` reader"] +pub type R = crate::R; +#[doc = "Register `MIBIRULES` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR0` reader - ADDR0"] +pub type Addr0R = crate::FieldReader; +#[doc = "Field `ADDR0` writer - ADDR0"] +pub type Addr0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ADDR1` reader - ADDR1"] +pub type Addr1R = crate::FieldReader; +#[doc = "Field `ADDR1` writer - ADDR1"] +pub type Addr1W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ADDR2` reader - ADDR2"] +pub type Addr2R = crate::FieldReader; +#[doc = "Field `ADDR2` writer - ADDR2"] +pub type Addr2W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ADDR3` reader - ADDR3"] +pub type Addr3R = crate::FieldReader; +#[doc = "Field `ADDR3` writer - ADDR3"] +pub type Addr3W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ADDR4` reader - ADDR4"] +pub type Addr4R = crate::FieldReader; +#[doc = "Field `ADDR4` writer - ADDR4"] +pub type Addr4W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Most Significant Address Bit is 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Msb0 { + #[doc = "0: MSB is not 0"] + Disable = 0, + #[doc = "1: MSB is 0"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Msb0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MSB0` reader - Most Significant Address Bit is 0"] +pub type Msb0R = crate::BitReader; +impl Msb0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Msb0 { + match self.bits { + false => Msb0::Disable, + true => Msb0::Enable, + } + } + #[doc = "MSB is not 0"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Msb0::Disable + } + #[doc = "MSB is 0"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Msb0::Enable + } +} +#[doc = "Field `MSB0` writer - Most Significant Address Bit is 0"] +pub type Msb0W<'a, REG> = crate::BitWriter<'a, REG, Msb0>; +impl<'a, REG> Msb0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "MSB is not 0"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Msb0::Disable) + } + #[doc = "MSB is 0"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Msb0::Enable) + } +} +#[doc = "No IBI byte\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nobyte { + #[doc = "0: With mandatory IBI byte"] + Ibibyte = 0, + #[doc = "1: Without mandatory IBI byte"] + NoIbibyte = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nobyte) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOBYTE` reader - No IBI byte"] +pub type NobyteR = crate::BitReader; +impl NobyteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nobyte { + match self.bits { + false => Nobyte::Ibibyte, + true => Nobyte::NoIbibyte, + } + } + #[doc = "With mandatory IBI byte"] + #[inline(always)] + pub fn is_ibibyte(&self) -> bool { + *self == Nobyte::Ibibyte + } + #[doc = "Without mandatory IBI byte"] + #[inline(always)] + pub fn is_no_ibibyte(&self) -> bool { + *self == Nobyte::NoIbibyte + } +} +#[doc = "Field `NOBYTE` writer - No IBI byte"] +pub type NobyteW<'a, REG> = crate::BitWriter<'a, REG, Nobyte>; +impl<'a, REG> NobyteW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "With mandatory IBI byte"] + #[inline(always)] + pub fn ibibyte(self) -> &'a mut crate::W { + self.variant(Nobyte::Ibibyte) + } + #[doc = "Without mandatory IBI byte"] + #[inline(always)] + pub fn no_ibibyte(self) -> &'a mut crate::W { + self.variant(Nobyte::NoIbibyte) + } +} +impl R { + #[doc = "Bits 0:5 - ADDR0"] + #[inline(always)] + pub fn addr0(&self) -> Addr0R { + Addr0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - ADDR1"] + #[inline(always)] + pub fn addr1(&self) -> Addr1R { + Addr1R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:17 - ADDR2"] + #[inline(always)] + pub fn addr2(&self) -> Addr2R { + Addr2R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:23 - ADDR3"] + #[inline(always)] + pub fn addr3(&self) -> Addr3R { + Addr3R::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - ADDR4"] + #[inline(always)] + pub fn addr4(&self) -> Addr4R { + Addr4R::new(((self.bits >> 24) & 0x3f) as u8) + } + #[doc = "Bit 30 - Most Significant Address Bit is 0"] + #[inline(always)] + pub fn msb0(&self) -> Msb0R { + Msb0R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - No IBI byte"] + #[inline(always)] + pub fn nobyte(&self) -> NobyteR { + NobyteR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - ADDR0"] + #[inline(always)] + pub fn addr0(&mut self) -> Addr0W { + Addr0W::new(self, 0) + } + #[doc = "Bits 6:11 - ADDR1"] + #[inline(always)] + pub fn addr1(&mut self) -> Addr1W { + Addr1W::new(self, 6) + } + #[doc = "Bits 12:17 - ADDR2"] + #[inline(always)] + pub fn addr2(&mut self) -> Addr2W { + Addr2W::new(self, 12) + } + #[doc = "Bits 18:23 - ADDR3"] + #[inline(always)] + pub fn addr3(&mut self) -> Addr3W { + Addr3W::new(self, 18) + } + #[doc = "Bits 24:29 - ADDR4"] + #[inline(always)] + pub fn addr4(&mut self) -> Addr4W { + Addr4W::new(self, 24) + } + #[doc = "Bit 30 - Most Significant Address Bit is 0"] + #[inline(always)] + pub fn msb0(&mut self) -> Msb0W { + Msb0W::new(self, 30) + } + #[doc = "Bit 31 - No IBI byte"] + #[inline(always)] + pub fn nobyte(&mut self) -> NobyteW { + NobyteW::new(self, 31) + } +} +#[doc = "Controller In-band Interrupt Registry and Rules\n\nYou can [`read`](crate::Reg::read) this register and get [`mibirules::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mibirules::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MibirulesSpec; +impl crate::RegisterSpec for MibirulesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mibirules::R`](R) reader structure"] +impl crate::Readable for MibirulesSpec {} +#[doc = "`write(|w| ..)` method takes [`mibirules::W`](W) writer structure"] +impl crate::Writable for MibirulesSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MIBIRULES to value 0"] +impl crate::Resettable for MibirulesSpec {} diff --git a/mcxa276-pac/src/i3c0/mintclr.rs b/mcxa276-pac/src/i3c0/mintclr.rs new file mode 100644 index 000000000..21aea1fdf --- /dev/null +++ b/mcxa276-pac/src/i3c0/mintclr.rs @@ -0,0 +1,526 @@ +#[doc = "Register `MINTCLR` reader"] +pub type R = crate::R; +#[doc = "Register `MINTCLR` writer"] +pub type W = crate::W; +#[doc = "SLVSTART Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slvstart { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slvstart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLVSTART` reader - SLVSTART Interrupt Enable Clear Flag"] +pub type SlvstartR = crate::BitReader; +impl SlvstartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slvstart { + match self.bits { + false => Slvstart::None, + true => Slvstart::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Slvstart::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Slvstart::Clear + } +} +#[doc = "Field `SLVSTART` writer - SLVSTART Interrupt Enable Clear Flag"] +pub type SlvstartW<'a, REG> = crate::BitWriter1C<'a, REG, Slvstart>; +impl<'a, REG> SlvstartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Slvstart::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Slvstart::Clear) + } +} +#[doc = "MCTRLDONE Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mctrldone { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mctrldone) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MCTRLDONE` reader - MCTRLDONE Interrupt Enable Clear Flag"] +pub type MctrldoneR = crate::BitReader; +impl MctrldoneR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mctrldone { + match self.bits { + false => Mctrldone::None, + true => Mctrldone::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Mctrldone::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Mctrldone::Clear + } +} +#[doc = "Field `MCTRLDONE` writer - MCTRLDONE Interrupt Enable Clear Flag"] +pub type MctrldoneW<'a, REG> = crate::BitWriter1C<'a, REG, Mctrldone>; +impl<'a, REG> MctrldoneW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Mctrldone::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Mctrldone::Clear) + } +} +#[doc = "COMPLETE Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Complete { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Complete) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPLETE` reader - COMPLETE Interrupt Enable Clear Flag"] +pub type CompleteR = crate::BitReader; +impl CompleteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Complete { + match self.bits { + false => Complete::None, + true => Complete::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Complete::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Complete::Clear + } +} +#[doc = "Field `COMPLETE` writer - COMPLETE Interrupt Enable Clear Flag"] +pub type CompleteW<'a, REG> = crate::BitWriter1C<'a, REG, Complete>; +impl<'a, REG> CompleteW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Complete::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Complete::Clear) + } +} +#[doc = "RXPEND Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxpend { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxpend) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXPEND` reader - RXPEND Interrupt Enable Clear Flag"] +pub type RxpendR = crate::BitReader; +impl RxpendR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxpend { + match self.bits { + false => Rxpend::None, + true => Rxpend::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Rxpend::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Rxpend::Clear + } +} +#[doc = "Field `RXPEND` writer - RXPEND Interrupt Enable Clear Flag"] +pub type RxpendW<'a, REG> = crate::BitWriter1C<'a, REG, Rxpend>; +impl<'a, REG> RxpendW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Rxpend::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Rxpend::Clear) + } +} +#[doc = "TXNOTFULL Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txnotfull { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txnotfull) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXNOTFULL` reader - TXNOTFULL Interrupt Enable Clear Flag"] +pub type TxnotfullR = crate::BitReader; +impl TxnotfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txnotfull { + match self.bits { + false => Txnotfull::None, + true => Txnotfull::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Txnotfull::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Txnotfull::Clear + } +} +#[doc = "Field `TXNOTFULL` writer - TXNOTFULL Interrupt Enable Clear Flag"] +pub type TxnotfullW<'a, REG> = crate::BitWriter1C<'a, REG, Txnotfull>; +impl<'a, REG> TxnotfullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Txnotfull::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Txnotfull::Clear) + } +} +#[doc = "IBIWON Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibiwon { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibiwon) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBIWON` reader - IBIWON Interrupt Enable Clear Flag"] +pub type IbiwonR = crate::BitReader; +impl IbiwonR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibiwon { + match self.bits { + false => Ibiwon::None, + true => Ibiwon::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Ibiwon::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Ibiwon::Clear + } +} +#[doc = "Field `IBIWON` writer - IBIWON Interrupt Enable Clear Flag"] +pub type IbiwonW<'a, REG> = crate::BitWriter1C<'a, REG, Ibiwon>; +impl<'a, REG> IbiwonW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Ibiwon::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Ibiwon::Clear) + } +} +#[doc = "ERRWARN Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errwarn { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errwarn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Enable Clear Flag"] +pub type ErrwarnR = crate::BitReader; +impl ErrwarnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errwarn { + match self.bits { + false => Errwarn::None, + true => Errwarn::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Errwarn::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Errwarn::Clear + } +} +#[doc = "Field `ERRWARN` writer - ERRWARN Interrupt Enable Clear Flag"] +pub type ErrwarnW<'a, REG> = crate::BitWriter1C<'a, REG, Errwarn>; +impl<'a, REG> ErrwarnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Errwarn::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Errwarn::Clear) + } +} +#[doc = "NOWCONTROLLER Interrupt Enable Clear Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nowmaster { + #[doc = "0: No effect"] + None = 0, + #[doc = "1: Interrupt enable cleared"] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nowmaster) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOWMASTER` reader - NOWCONTROLLER Interrupt Enable Clear Flag"] +pub type NowmasterR = crate::BitReader; +impl NowmasterR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nowmaster { + match self.bits { + false => Nowmaster::None, + true => Nowmaster::Clear, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Nowmaster::None + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Nowmaster::Clear + } +} +#[doc = "Field `NOWMASTER` writer - NOWCONTROLLER Interrupt Enable Clear Flag"] +pub type NowmasterW<'a, REG> = crate::BitWriter1C<'a, REG, Nowmaster>; +impl<'a, REG> NowmasterW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(Nowmaster::None) + } + #[doc = "Interrupt enable cleared"] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Nowmaster::Clear) + } +} +impl R { + #[doc = "Bit 8 - SLVSTART Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn slvstart(&self) -> SlvstartR { + SlvstartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MCTRLDONE Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn mctrldone(&self) -> MctrldoneR { + MctrldoneR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - COMPLETE Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn complete(&self) -> CompleteR { + CompleteR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn rxpend(&self) -> RxpendR { + RxpendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TXNOTFULL Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn txnotfull(&self) -> TxnotfullR { + TxnotfullR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - IBIWON Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn ibiwon(&self) -> IbiwonR { + IbiwonR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 19 - NOWCONTROLLER Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn nowmaster(&self) -> NowmasterR { + NowmasterR::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - SLVSTART Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn slvstart(&mut self) -> SlvstartW { + SlvstartW::new(self, 8) + } + #[doc = "Bit 9 - MCTRLDONE Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn mctrldone(&mut self) -> MctrldoneW { + MctrldoneW::new(self, 9) + } + #[doc = "Bit 10 - COMPLETE Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn complete(&mut self) -> CompleteW { + CompleteW::new(self, 10) + } + #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn rxpend(&mut self) -> RxpendW { + RxpendW::new(self, 11) + } + #[doc = "Bit 12 - TXNOTFULL Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn txnotfull(&mut self) -> TxnotfullW { + TxnotfullW::new(self, 12) + } + #[doc = "Bit 13 - IBIWON Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn ibiwon(&mut self) -> IbiwonW { + IbiwonW::new(self, 13) + } + #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn errwarn(&mut self) -> ErrwarnW { + ErrwarnW::new(self, 15) + } + #[doc = "Bit 19 - NOWCONTROLLER Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn nowmaster(&mut self) -> NowmasterW { + NowmasterW::new(self, 19) + } +} +#[doc = "Controller Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`mintclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MintclrSpec; +impl crate::RegisterSpec for MintclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mintclr::R`](R) reader structure"] +impl crate::Readable for MintclrSpec {} +#[doc = "`write(|w| ..)` method takes [`mintclr::W`](W) writer structure"] +impl crate::Writable for MintclrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0008_bf00; +} +#[doc = "`reset()` method sets MINTCLR to value 0"] +impl crate::Resettable for MintclrSpec {} diff --git a/mcxa276-pac/src/i3c0/mintmasked.rs b/mcxa276-pac/src/i3c0/mintmasked.rs new file mode 100644 index 000000000..eb4e620b5 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mintmasked.rs @@ -0,0 +1,307 @@ +#[doc = "Register `MINTMASKED` reader"] +pub type R = crate::R; +#[doc = "SLVSTART Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slvstart { + #[doc = "0: Disabled"] + NotEnabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slvstart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLVSTART` reader - SLVSTART Interrupt Mask"] +pub type SlvstartR = crate::BitReader; +impl SlvstartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slvstart { + match self.bits { + false => Slvstart::NotEnabled, + true => Slvstart::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_not_enabled(&self) -> bool { + *self == Slvstart::NotEnabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Slvstart::Enabled + } +} +#[doc = "MCTRLDONE Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mctrldone { + #[doc = "0: Disabled"] + NotEnabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mctrldone) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MCTRLDONE` reader - MCTRLDONE Interrupt Mask"] +pub type MctrldoneR = crate::BitReader; +impl MctrldoneR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mctrldone { + match self.bits { + false => Mctrldone::NotEnabled, + true => Mctrldone::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_not_enabled(&self) -> bool { + *self == Mctrldone::NotEnabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mctrldone::Enabled + } +} +#[doc = "COMPLETE Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Complete { + #[doc = "0: Disabled"] + NotEnabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Complete) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPLETE` reader - COMPLETE Interrupt Mask"] +pub type CompleteR = crate::BitReader; +impl CompleteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Complete { + match self.bits { + false => Complete::NotEnabled, + true => Complete::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_not_enabled(&self) -> bool { + *self == Complete::NotEnabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Complete::Enabled + } +} +#[doc = "Field `RXPEND` reader - RXPEND Interrupt Mask"] +pub type RxpendR = crate::BitReader; +#[doc = "TXNOTFULL Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txnotfull { + #[doc = "0: Disabled"] + NotEnabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txnotfull) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXNOTFULL` reader - TXNOTFULL Interrupt Mask"] +pub type TxnotfullR = crate::BitReader; +impl TxnotfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txnotfull { + match self.bits { + false => Txnotfull::NotEnabled, + true => Txnotfull::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_not_enabled(&self) -> bool { + *self == Txnotfull::NotEnabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Txnotfull::Enabled + } +} +#[doc = "IBIWON Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibiwon { + #[doc = "0: Disabled"] + NotEnabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibiwon) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBIWON` reader - IBIWON Interrupt Mask"] +pub type IbiwonR = crate::BitReader; +impl IbiwonR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibiwon { + match self.bits { + false => Ibiwon::NotEnabled, + true => Ibiwon::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_not_enabled(&self) -> bool { + *self == Ibiwon::NotEnabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ibiwon::Enabled + } +} +#[doc = "ERRWARN Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errwarn { + #[doc = "0: Disabled"] + NotEnabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errwarn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Mask"] +pub type ErrwarnR = crate::BitReader; +impl ErrwarnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errwarn { + match self.bits { + false => Errwarn::NotEnabled, + true => Errwarn::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_not_enabled(&self) -> bool { + *self == Errwarn::NotEnabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Errwarn::Enabled + } +} +#[doc = "NOWCONTROLLER Interrupt Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nowmaster { + #[doc = "0: Disabled"] + NotEnabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nowmaster) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOWMASTER` reader - NOWCONTROLLER Interrupt Mask"] +pub type NowmasterR = crate::BitReader; +impl NowmasterR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nowmaster { + match self.bits { + false => Nowmaster::NotEnabled, + true => Nowmaster::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_not_enabled(&self) -> bool { + *self == Nowmaster::NotEnabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Nowmaster::Enabled + } +} +impl R { + #[doc = "Bit 8 - SLVSTART Interrupt Mask"] + #[inline(always)] + pub fn slvstart(&self) -> SlvstartR { + SlvstartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MCTRLDONE Interrupt Mask"] + #[inline(always)] + pub fn mctrldone(&self) -> MctrldoneR { + MctrldoneR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - COMPLETE Interrupt Mask"] + #[inline(always)] + pub fn complete(&self) -> CompleteR { + CompleteR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RXPEND Interrupt Mask"] + #[inline(always)] + pub fn rxpend(&self) -> RxpendR { + RxpendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TXNOTFULL Interrupt Mask"] + #[inline(always)] + pub fn txnotfull(&self) -> TxnotfullR { + TxnotfullR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - IBIWON Interrupt Mask"] + #[inline(always)] + pub fn ibiwon(&self) -> IbiwonR { + IbiwonR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - ERRWARN Interrupt Mask"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 19 - NOWCONTROLLER Interrupt Mask"] + #[inline(always)] + pub fn nowmaster(&self) -> NowmasterR { + NowmasterR::new(((self.bits >> 19) & 1) != 0) + } +} +#[doc = "Controller Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mintmasked::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MintmaskedSpec; +impl crate::RegisterSpec for MintmaskedSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mintmasked::R`](R) reader structure"] +impl crate::Readable for MintmaskedSpec {} +#[doc = "`reset()` method sets MINTMASKED to value 0"] +impl crate::Resettable for MintmaskedSpec {} diff --git a/mcxa276-pac/src/i3c0/mintset.rs b/mcxa276-pac/src/i3c0/mintset.rs new file mode 100644 index 000000000..3235bf681 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mintset.rs @@ -0,0 +1,477 @@ +#[doc = "Register `MINTSET` reader"] +pub type R = crate::R; +#[doc = "Register `MINTSET` writer"] +pub type W = crate::W; +#[doc = "Target Start Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slvstart { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slvstart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLVSTART` reader - Target Start Interrupt Enable"] +pub type SlvstartR = crate::BitReader; +impl SlvstartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slvstart { + match self.bits { + false => Slvstart::Disable, + true => Slvstart::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Slvstart::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Slvstart::Enable + } +} +#[doc = "Field `SLVSTART` writer - Target Start Interrupt Enable"] +pub type SlvstartW<'a, REG> = crate::BitWriter1S<'a, REG, Slvstart>; +impl<'a, REG> SlvstartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Slvstart::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Slvstart::Enable) + } +} +#[doc = "Controller Control Done Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mctrldone { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mctrldone) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MCTRLDONE` reader - Controller Control Done Interrupt Enable"] +pub type MctrldoneR = crate::BitReader; +impl MctrldoneR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mctrldone { + match self.bits { + false => Mctrldone::Disable, + true => Mctrldone::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Mctrldone::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Mctrldone::Enable + } +} +#[doc = "Field `MCTRLDONE` writer - Controller Control Done Interrupt Enable"] +pub type MctrldoneW<'a, REG> = crate::BitWriter1S<'a, REG, Mctrldone>; +impl<'a, REG> MctrldoneW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Mctrldone::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Mctrldone::Enable) + } +} +#[doc = "Completed Message Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Complete { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Complete) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPLETE` reader - Completed Message Interrupt Enable"] +pub type CompleteR = crate::BitReader; +impl CompleteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Complete { + match self.bits { + false => Complete::Disable, + true => Complete::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Complete::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Complete::Enable + } +} +#[doc = "Field `COMPLETE` writer - Completed Message Interrupt Enable"] +pub type CompleteW<'a, REG> = crate::BitWriter1S<'a, REG, Complete>; +impl<'a, REG> CompleteW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Complete::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Complete::Enable) + } +} +#[doc = "Field `RXPEND` reader - Receive Pending Interrupt Enable"] +pub type RxpendR = crate::BitReader; +#[doc = "Field `RXPEND` writer - Receive Pending Interrupt Enable"] +pub type RxpendW<'a, REG> = crate::BitWriter1S<'a, REG>; +#[doc = "Transmit Buffer/FIFO Not Full Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txnotfull { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txnotfull) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXNOTFULL` reader - Transmit Buffer/FIFO Not Full Interrupt Enable"] +pub type TxnotfullR = crate::BitReader; +impl TxnotfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txnotfull { + match self.bits { + false => Txnotfull::Disable, + true => Txnotfull::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Txnotfull::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Txnotfull::Enable + } +} +#[doc = "Field `TXNOTFULL` writer - Transmit Buffer/FIFO Not Full Interrupt Enable"] +pub type TxnotfullW<'a, REG> = crate::BitWriter1S<'a, REG, Txnotfull>; +impl<'a, REG> TxnotfullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Txnotfull::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Txnotfull::Enable) + } +} +#[doc = "IBI Won Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibiwon { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibiwon) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBIWON` reader - IBI Won Interrupt Enable"] +pub type IbiwonR = crate::BitReader; +impl IbiwonR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibiwon { + match self.bits { + false => Ibiwon::Disable, + true => Ibiwon::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ibiwon::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ibiwon::Enable + } +} +#[doc = "Field `IBIWON` writer - IBI Won Interrupt Enable"] +pub type IbiwonW<'a, REG> = crate::BitWriter1S<'a, REG, Ibiwon>; +impl<'a, REG> IbiwonW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ibiwon::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ibiwon::Enable) + } +} +#[doc = "Error or Warning (ERRWARN) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errwarn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errwarn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRWARN` reader - Error or Warning (ERRWARN) Interrupt Enable"] +pub type ErrwarnR = crate::BitReader; +impl ErrwarnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errwarn { + match self.bits { + false => Errwarn::Disable, + true => Errwarn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Errwarn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Errwarn::Enable + } +} +#[doc = "Field `ERRWARN` writer - Error or Warning (ERRWARN) Interrupt Enable"] +pub type ErrwarnW<'a, REG> = crate::BitWriter1S<'a, REG, Errwarn>; +impl<'a, REG> ErrwarnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Errwarn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Errwarn::Enable) + } +} +#[doc = "Now Controller Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nowmaster { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nowmaster) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOWMASTER` reader - Now Controller Interrupt Enable"] +pub type NowmasterR = crate::BitReader; +impl NowmasterR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nowmaster { + match self.bits { + false => Nowmaster::Disable, + true => Nowmaster::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Nowmaster::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Nowmaster::Enable + } +} +#[doc = "Field `NOWMASTER` writer - Now Controller Interrupt Enable"] +pub type NowmasterW<'a, REG> = crate::BitWriter1S<'a, REG, Nowmaster>; +impl<'a, REG> NowmasterW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Nowmaster::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Nowmaster::Enable) + } +} +impl R { + #[doc = "Bit 8 - Target Start Interrupt Enable"] + #[inline(always)] + pub fn slvstart(&self) -> SlvstartR { + SlvstartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Controller Control Done Interrupt Enable"] + #[inline(always)] + pub fn mctrldone(&self) -> MctrldoneR { + MctrldoneR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Completed Message Interrupt Enable"] + #[inline(always)] + pub fn complete(&self) -> CompleteR { + CompleteR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Receive Pending Interrupt Enable"] + #[inline(always)] + pub fn rxpend(&self) -> RxpendR { + RxpendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Transmit Buffer/FIFO Not Full Interrupt Enable"] + #[inline(always)] + pub fn txnotfull(&self) -> TxnotfullR { + TxnotfullR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - IBI Won Interrupt Enable"] + #[inline(always)] + pub fn ibiwon(&self) -> IbiwonR { + IbiwonR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Error or Warning (ERRWARN) Interrupt Enable"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 19 - Now Controller Interrupt Enable"] + #[inline(always)] + pub fn nowmaster(&self) -> NowmasterR { + NowmasterR::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Target Start Interrupt Enable"] + #[inline(always)] + pub fn slvstart(&mut self) -> SlvstartW { + SlvstartW::new(self, 8) + } + #[doc = "Bit 9 - Controller Control Done Interrupt Enable"] + #[inline(always)] + pub fn mctrldone(&mut self) -> MctrldoneW { + MctrldoneW::new(self, 9) + } + #[doc = "Bit 10 - Completed Message Interrupt Enable"] + #[inline(always)] + pub fn complete(&mut self) -> CompleteW { + CompleteW::new(self, 10) + } + #[doc = "Bit 11 - Receive Pending Interrupt Enable"] + #[inline(always)] + pub fn rxpend(&mut self) -> RxpendW { + RxpendW::new(self, 11) + } + #[doc = "Bit 12 - Transmit Buffer/FIFO Not Full Interrupt Enable"] + #[inline(always)] + pub fn txnotfull(&mut self) -> TxnotfullW { + TxnotfullW::new(self, 12) + } + #[doc = "Bit 13 - IBI Won Interrupt Enable"] + #[inline(always)] + pub fn ibiwon(&mut self) -> IbiwonW { + IbiwonW::new(self, 13) + } + #[doc = "Bit 15 - Error or Warning (ERRWARN) Interrupt Enable"] + #[inline(always)] + pub fn errwarn(&mut self) -> ErrwarnW { + ErrwarnW::new(self, 15) + } + #[doc = "Bit 19 - Now Controller Interrupt Enable"] + #[inline(always)] + pub fn nowmaster(&mut self) -> NowmasterW { + NowmasterW::new(self, 19) + } +} +#[doc = "Controller Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`mintset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MintsetSpec; +impl crate::RegisterSpec for MintsetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mintset::R`](R) reader structure"] +impl crate::Readable for MintsetSpec {} +#[doc = "`write(|w| ..)` method takes [`mintset::W`](W) writer structure"] +impl crate::Writable for MintsetSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0008_bf00; +} +#[doc = "`reset()` method sets MINTSET to value 0"] +impl crate::Resettable for MintsetSpec {} diff --git a/mcxa276-pac/src/i3c0/mrdatab.rs b/mcxa276-pac/src/i3c0/mrdatab.rs new file mode 100644 index 000000000..25437af63 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mrdatab.rs @@ -0,0 +1,20 @@ +#[doc = "Register `MRDATAB` reader"] +pub type R = crate::R; +#[doc = "Field `VALUE` reader - Value"] +pub type ValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Controller Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatab::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrdatabSpec; +impl crate::RegisterSpec for MrdatabSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrdatab::R`](R) reader structure"] +impl crate::Readable for MrdatabSpec {} +#[doc = "`reset()` method sets MRDATAB to value 0"] +impl crate::Resettable for MrdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/mrdatah.rs b/mcxa276-pac/src/i3c0/mrdatah.rs new file mode 100644 index 000000000..4de10af62 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mrdatah.rs @@ -0,0 +1,27 @@ +#[doc = "Register `MRDATAH` reader"] +pub type R = crate::R; +#[doc = "Field `LSB` reader - Low Byte"] +pub type LsbR = crate::FieldReader; +#[doc = "Field `MSB` reader - High Byte"] +pub type MsbR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Low Byte"] + #[inline(always)] + pub fn lsb(&self) -> LsbR { + LsbR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - High Byte"] + #[inline(always)] + pub fn msb(&self) -> MsbR { + MsbR::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[doc = "Controller Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatah::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrdatahSpec; +impl crate::RegisterSpec for MrdatahSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrdatah::R`](R) reader structure"] +impl crate::Readable for MrdatahSpec {} +#[doc = "`reset()` method sets MRDATAH to value 0"] +impl crate::Resettable for MrdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/mrmsg_ddr.rs b/mcxa276-pac/src/i3c0/mrmsg_ddr.rs new file mode 100644 index 000000000..611d4d5e7 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mrmsg_ddr.rs @@ -0,0 +1,20 @@ +#[doc = "Register `MRMSG_DDR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Data"] +pub type DataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Controller Read Message in DDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_ddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrmsgDdrSpec; +impl crate::RegisterSpec for MrmsgDdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrmsg_ddr::R`](R) reader structure"] +impl crate::Readable for MrmsgDdrSpec {} +#[doc = "`reset()` method sets MRMSG_DDR to value 0"] +impl crate::Resettable for MrmsgDdrSpec {} diff --git a/mcxa276-pac/src/i3c0/mrmsg_sdr.rs b/mcxa276-pac/src/i3c0/mrmsg_sdr.rs new file mode 100644 index 000000000..b867262f4 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mrmsg_sdr.rs @@ -0,0 +1,20 @@ +#[doc = "Register `MRMSG_SDR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Data"] +pub type DataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Controller Read Message in SDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_sdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrmsgSdrSpec; +impl crate::RegisterSpec for MrmsgSdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrmsg_sdr::R`](R) reader structure"] +impl crate::Readable for MrmsgSdrSpec {} +#[doc = "`reset()` method sets MRMSG_SDR to value 0"] +impl crate::Resettable for MrmsgSdrSpec {} diff --git a/mcxa276-pac/src/i3c0/mstatus.rs b/mcxa276-pac/src/i3c0/mstatus.rs new file mode 100644 index 000000000..20d7cf0b1 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mstatus.rs @@ -0,0 +1,709 @@ +#[doc = "Register `MSTATUS` reader"] +pub type R = crate::R; +#[doc = "Register `MSTATUS` writer"] +pub type W = crate::W; +#[doc = "State of the Controller\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum State { + #[doc = "0: IDLE (bus has stopped)"] + Idle = 0, + #[doc = "1: SLVREQ (target request)"] + Slvreq = 1, + #[doc = "2: MSGSDR"] + Msgsdr = 2, + #[doc = "3: NORMACT"] + Normact = 3, + #[doc = "4: MSGDDR"] + Ddr = 4, + #[doc = "5: DAA"] + Daa = 5, + #[doc = "6: IBIACK"] + Ibiack = 6, + #[doc = "7: IBIRCV"] + Ibircv = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: State) -> Self { + variant as _ + } +} +impl crate::FieldSpec for State { + type Ux = u8; +} +impl crate::IsEnum for State {} +#[doc = "Field `STATE` reader - State of the Controller"] +pub type StateR = crate::FieldReader; +impl StateR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> State { + match self.bits { + 0 => State::Idle, + 1 => State::Slvreq, + 2 => State::Msgsdr, + 3 => State::Normact, + 4 => State::Ddr, + 5 => State::Daa, + 6 => State::Ibiack, + 7 => State::Ibircv, + _ => unreachable!(), + } + } + #[doc = "IDLE (bus has stopped)"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == State::Idle + } + #[doc = "SLVREQ (target request)"] + #[inline(always)] + pub fn is_slvreq(&self) -> bool { + *self == State::Slvreq + } + #[doc = "MSGSDR"] + #[inline(always)] + pub fn is_msgsdr(&self) -> bool { + *self == State::Msgsdr + } + #[doc = "NORMACT"] + #[inline(always)] + pub fn is_normact(&self) -> bool { + *self == State::Normact + } + #[doc = "MSGDDR"] + #[inline(always)] + pub fn is_ddr(&self) -> bool { + *self == State::Ddr + } + #[doc = "DAA"] + #[inline(always)] + pub fn is_daa(&self) -> bool { + *self == State::Daa + } + #[doc = "IBIACK"] + #[inline(always)] + pub fn is_ibiack(&self) -> bool { + *self == State::Ibiack + } + #[doc = "IBIRCV"] + #[inline(always)] + pub fn is_ibircv(&self) -> bool { + *self == State::Ibircv + } +} +#[doc = "Between\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Between { + #[doc = "0: Inactive (for other cases)"] + Inactive = 0, + #[doc = "1: Active"] + Active = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Between) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BETWEEN` reader - Between"] +pub type BetweenR = crate::BitReader; +impl BetweenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Between { + match self.bits { + false => Between::Inactive, + true => Between::Active, + } + } + #[doc = "Inactive (for other cases)"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == Between::Inactive + } + #[doc = "Active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == Between::Active + } +} +#[doc = "Not Acknowledged\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nacked { + #[doc = "0: Not NACKed"] + NotNacked = 0, + #[doc = "1: NACKed (not acknowledged)"] + Nacked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nacked) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NACKED` reader - Not Acknowledged"] +pub type NackedR = crate::BitReader; +impl NackedR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nacked { + match self.bits { + false => Nacked::NotNacked, + true => Nacked::Nacked, + } + } + #[doc = "Not NACKed"] + #[inline(always)] + pub fn is_not_nacked(&self) -> bool { + *self == Nacked::NotNacked + } + #[doc = "NACKed (not acknowledged)"] + #[inline(always)] + pub fn is_nacked(&self) -> bool { + *self == Nacked::Nacked + } +} +#[doc = "In-Band Interrupt (IBI) Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ibitype { + #[doc = "0: NONE (no IBI: this status occurs when MSTATUS\\[IBIWON\\] becomes 0)"] + None = 0, + #[doc = "1: IBI"] + Ibi = 1, + #[doc = "2: CR"] + Mr = 2, + #[doc = "3: HJ"] + Hj = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ibitype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ibitype { + type Ux = u8; +} +impl crate::IsEnum for Ibitype {} +#[doc = "Field `IBITYPE` reader - In-Band Interrupt (IBI) Type"] +pub type IbitypeR = crate::FieldReader; +impl IbitypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibitype { + match self.bits { + 0 => Ibitype::None, + 1 => Ibitype::Ibi, + 2 => Ibitype::Mr, + 3 => Ibitype::Hj, + _ => unreachable!(), + } + } + #[doc = "NONE (no IBI: this status occurs when MSTATUS\\[IBIWON\\] becomes 0)"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Ibitype::None + } + #[doc = "IBI"] + #[inline(always)] + pub fn is_ibi(&self) -> bool { + *self == Ibitype::Ibi + } + #[doc = "CR"] + #[inline(always)] + pub fn is_mr(&self) -> bool { + *self == Ibitype::Mr + } + #[doc = "HJ"] + #[inline(always)] + pub fn is_hj(&self) -> bool { + *self == Ibitype::Hj + } +} +#[doc = "Target Start Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slvstart { + #[doc = "0: Target not requesting START"] + NotStart = 0, + #[doc = "1: Target requesting START"] + Start = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slvstart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLVSTART` reader - Target Start Flag"] +pub type SlvstartR = crate::BitReader; +impl SlvstartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slvstart { + match self.bits { + false => Slvstart::NotStart, + true => Slvstart::Start, + } + } + #[doc = "Target not requesting START"] + #[inline(always)] + pub fn is_not_start(&self) -> bool { + *self == Slvstart::NotStart + } + #[doc = "Target requesting START"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == Slvstart::Start + } +} +#[doc = "Field `SLVSTART` writer - Target Start Flag"] +pub type SlvstartW<'a, REG> = crate::BitWriter1C<'a, REG, Slvstart>; +impl<'a, REG> SlvstartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Target not requesting START"] + #[inline(always)] + pub fn not_start(self) -> &'a mut crate::W { + self.variant(Slvstart::NotStart) + } + #[doc = "Target requesting START"] + #[inline(always)] + pub fn start(self) -> &'a mut crate::W { + self.variant(Slvstart::Start) + } +} +#[doc = "Controller Control Done Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mctrldone { + #[doc = "0: Not done"] + NotDone = 0, + #[doc = "1: Done"] + Done = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mctrldone) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MCTRLDONE` reader - Controller Control Done Flag"] +pub type MctrldoneR = crate::BitReader; +impl MctrldoneR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mctrldone { + match self.bits { + false => Mctrldone::NotDone, + true => Mctrldone::Done, + } + } + #[doc = "Not done"] + #[inline(always)] + pub fn is_not_done(&self) -> bool { + *self == Mctrldone::NotDone + } + #[doc = "Done"] + #[inline(always)] + pub fn is_done(&self) -> bool { + *self == Mctrldone::Done + } +} +#[doc = "Field `MCTRLDONE` writer - Controller Control Done Flag"] +pub type MctrldoneW<'a, REG> = crate::BitWriter1C<'a, REG, Mctrldone>; +impl<'a, REG> MctrldoneW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not done"] + #[inline(always)] + pub fn not_done(self) -> &'a mut crate::W { + self.variant(Mctrldone::NotDone) + } + #[doc = "Done"] + #[inline(always)] + pub fn done(self) -> &'a mut crate::W { + self.variant(Mctrldone::Done) + } +} +#[doc = "Complete Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Complete { + #[doc = "0: Not complete"] + NotComplete = 0, + #[doc = "1: Complete"] + Complete = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Complete) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COMPLETE` reader - Complete Flag"] +pub type CompleteR = crate::BitReader; +impl CompleteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Complete { + match self.bits { + false => Complete::NotComplete, + true => Complete::Complete, + } + } + #[doc = "Not complete"] + #[inline(always)] + pub fn is_not_complete(&self) -> bool { + *self == Complete::NotComplete + } + #[doc = "Complete"] + #[inline(always)] + pub fn is_complete(&self) -> bool { + *self == Complete::Complete + } +} +#[doc = "Field `COMPLETE` writer - Complete Flag"] +pub type CompleteW<'a, REG> = crate::BitWriter1C<'a, REG, Complete>; +impl<'a, REG> CompleteW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not complete"] + #[inline(always)] + pub fn not_complete(self) -> &'a mut crate::W { + self.variant(Complete::NotComplete) + } + #[doc = "Complete"] + #[inline(always)] + pub fn complete(self) -> &'a mut crate::W { + self.variant(Complete::Complete) + } +} +#[doc = "RXPEND\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxpend { + #[doc = "0: No receive message pending"] + Idle = 0, + #[doc = "1: Receive message pending"] + Pending = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxpend) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXPEND` reader - RXPEND"] +pub type RxpendR = crate::BitReader; +impl RxpendR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxpend { + match self.bits { + false => Rxpend::Idle, + true => Rxpend::Pending, + } + } + #[doc = "No receive message pending"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Rxpend::Idle + } + #[doc = "Receive message pending"] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == Rxpend::Pending + } +} +#[doc = "TX Buffer or FIFO Not Full\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txnotfull { + #[doc = "0: Receive buffer or FIFO full"] + Full = 0, + #[doc = "1: Receive buffer or FIFO not full"] + Notfull = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txnotfull) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXNOTFULL` reader - TX Buffer or FIFO Not Full"] +pub type TxnotfullR = crate::BitReader; +impl TxnotfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txnotfull { + match self.bits { + false => Txnotfull::Full, + true => Txnotfull::Notfull, + } + } + #[doc = "Receive buffer or FIFO full"] + #[inline(always)] + pub fn is_full(&self) -> bool { + *self == Txnotfull::Full + } + #[doc = "Receive buffer or FIFO not full"] + #[inline(always)] + pub fn is_notfull(&self) -> bool { + *self == Txnotfull::Notfull + } +} +#[doc = "In-Band Interrupt (IBI) Won Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibiwon { + #[doc = "0: No IBI arbitration won"] + NotWon = 0, + #[doc = "1: IBI arbitration won"] + Won = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibiwon) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBIWON` reader - In-Band Interrupt (IBI) Won Flag"] +pub type IbiwonR = crate::BitReader; +impl IbiwonR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibiwon { + match self.bits { + false => Ibiwon::NotWon, + true => Ibiwon::Won, + } + } + #[doc = "No IBI arbitration won"] + #[inline(always)] + pub fn is_not_won(&self) -> bool { + *self == Ibiwon::NotWon + } + #[doc = "IBI arbitration won"] + #[inline(always)] + pub fn is_won(&self) -> bool { + *self == Ibiwon::Won + } +} +#[doc = "Field `IBIWON` writer - In-Band Interrupt (IBI) Won Flag"] +pub type IbiwonW<'a, REG> = crate::BitWriter1C<'a, REG, Ibiwon>; +impl<'a, REG> IbiwonW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No IBI arbitration won"] + #[inline(always)] + pub fn not_won(self) -> &'a mut crate::W { + self.variant(Ibiwon::NotWon) + } + #[doc = "IBI arbitration won"] + #[inline(always)] + pub fn won(self) -> &'a mut crate::W { + self.variant(Ibiwon::Won) + } +} +#[doc = "Error or Warning\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errwarn { + #[doc = "0: No error or warning"] + NoError = 0, + #[doc = "1: Error or warning"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errwarn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRWARN` reader - Error or Warning"] +pub type ErrwarnR = crate::BitReader; +impl ErrwarnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errwarn { + match self.bits { + false => Errwarn::NoError, + true => Errwarn::Error, + } + } + #[doc = "No error or warning"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Errwarn::NoError + } + #[doc = "Error or warning"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Errwarn::Error + } +} +#[doc = "Module is now Controller Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nowmaster { + #[doc = "0: Not a controller"] + NotMaster = 0, + #[doc = "1: Controller"] + Master = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nowmaster) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOWMASTER` reader - Module is now Controller Flag"] +pub type NowmasterR = crate::BitReader; +impl NowmasterR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nowmaster { + match self.bits { + false => Nowmaster::NotMaster, + true => Nowmaster::Master, + } + } + #[doc = "Not a controller"] + #[inline(always)] + pub fn is_not_master(&self) -> bool { + *self == Nowmaster::NotMaster + } + #[doc = "Controller"] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == Nowmaster::Master + } +} +#[doc = "Field `NOWMASTER` writer - Module is now Controller Flag"] +pub type NowmasterW<'a, REG> = crate::BitWriter1C<'a, REG, Nowmaster>; +impl<'a, REG> NowmasterW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not a controller"] + #[inline(always)] + pub fn not_master(self) -> &'a mut crate::W { + self.variant(Nowmaster::NotMaster) + } + #[doc = "Controller"] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(Nowmaster::Master) + } +} +#[doc = "Field `IBIADDR` reader - IBI Address"] +pub type IbiaddrR = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - State of the Controller"] + #[inline(always)] + pub fn state(&self) -> StateR { + StateR::new((self.bits & 7) as u8) + } + #[doc = "Bit 4 - Between"] + #[inline(always)] + pub fn between(&self) -> BetweenR { + BetweenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Not Acknowledged"] + #[inline(always)] + pub fn nacked(&self) -> NackedR { + NackedR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - In-Band Interrupt (IBI) Type"] + #[inline(always)] + pub fn ibitype(&self) -> IbitypeR { + IbitypeR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - Target Start Flag"] + #[inline(always)] + pub fn slvstart(&self) -> SlvstartR { + SlvstartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Controller Control Done Flag"] + #[inline(always)] + pub fn mctrldone(&self) -> MctrldoneR { + MctrldoneR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Complete Flag"] + #[inline(always)] + pub fn complete(&self) -> CompleteR { + CompleteR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RXPEND"] + #[inline(always)] + pub fn rxpend(&self) -> RxpendR { + RxpendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX Buffer or FIFO Not Full"] + #[inline(always)] + pub fn txnotfull(&self) -> TxnotfullR { + TxnotfullR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - In-Band Interrupt (IBI) Won Flag"] + #[inline(always)] + pub fn ibiwon(&self) -> IbiwonR { + IbiwonR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Error or Warning"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 19 - Module is now Controller Flag"] + #[inline(always)] + pub fn nowmaster(&self) -> NowmasterR { + NowmasterR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 24:30 - IBI Address"] + #[inline(always)] + pub fn ibiaddr(&self) -> IbiaddrR { + IbiaddrR::new(((self.bits >> 24) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 8 - Target Start Flag"] + #[inline(always)] + pub fn slvstart(&mut self) -> SlvstartW { + SlvstartW::new(self, 8) + } + #[doc = "Bit 9 - Controller Control Done Flag"] + #[inline(always)] + pub fn mctrldone(&mut self) -> MctrldoneW { + MctrldoneW::new(self, 9) + } + #[doc = "Bit 10 - Complete Flag"] + #[inline(always)] + pub fn complete(&mut self) -> CompleteW { + CompleteW::new(self, 10) + } + #[doc = "Bit 13 - In-Band Interrupt (IBI) Won Flag"] + #[inline(always)] + pub fn ibiwon(&mut self) -> IbiwonW { + IbiwonW::new(self, 13) + } + #[doc = "Bit 19 - Module is now Controller Flag"] + #[inline(always)] + pub fn nowmaster(&mut self) -> NowmasterW { + NowmasterW::new(self, 19) + } +} +#[doc = "Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MstatusSpec; +impl crate::RegisterSpec for MstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mstatus::R`](R) reader structure"] +impl crate::Readable for MstatusSpec {} +#[doc = "`write(|w| ..)` method takes [`mstatus::W`](W) writer structure"] +impl crate::Writable for MstatusSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0008_2700; +} +#[doc = "`reset()` method sets MSTATUS to value 0x1000"] +impl crate::Resettable for MstatusSpec { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/mcxa276-pac/src/i3c0/mwdatab.rs b/mcxa276-pac/src/i3c0/mwdatab.rs new file mode 100644 index 000000000..ef418e75a --- /dev/null +++ b/mcxa276-pac/src/i3c0/mwdatab.rs @@ -0,0 +1,94 @@ +#[doc = "Register `MWDATAB` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` writer - Data Byte"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "End of Message\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum End { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: End) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - End of Message"] +pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; +impl<'a, REG> EndW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(End::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(End::End) + } +} +#[doc = "End of Message ALSO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EndAlso { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EndAlso) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END_ALSO` writer - End of Message ALSO"] +pub type EndAlsoW<'a, REG> = crate::BitWriter<'a, REG, EndAlso>; +impl<'a, REG> EndAlsoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(EndAlso::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(EndAlso::End) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte"] + #[inline(always)] + pub fn value(&mut self) -> ValueW { + ValueW::new(self, 0) + } + #[doc = "Bit 8 - End of Message"] + #[inline(always)] + pub fn end(&mut self) -> EndW { + EndW::new(self, 8) + } + #[doc = "Bit 16 - End of Message ALSO"] + #[inline(always)] + pub fn end_also(&mut self) -> EndAlsoW { + EndAlsoW::new(self, 16) + } +} +#[doc = "Controller Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatab::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MwdatabSpec; +impl crate::RegisterSpec for MwdatabSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mwdatab::W`](W) writer structure"] +impl crate::Writable for MwdatabSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWDATAB to value 0"] +impl crate::Resettable for MwdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/mwdatabe.rs b/mcxa276-pac/src/i3c0/mwdatabe.rs new file mode 100644 index 000000000..6ba1ff920 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mwdatabe.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MWDATABE` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` writer - Data"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn value(&mut self) -> ValueW { + ValueW::new(self, 0) + } +} +#[doc = "Controller Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatabe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MwdatabeSpec; +impl crate::RegisterSpec for MwdatabeSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mwdatabe::W`](W) writer structure"] +impl crate::Writable for MwdatabeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWDATABE to value 0"] +impl crate::Resettable for MwdatabeSpec {} diff --git a/mcxa276-pac/src/i3c0/mwdatah.rs b/mcxa276-pac/src/i3c0/mwdatah.rs new file mode 100644 index 000000000..a96e018c7 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mwdatah.rs @@ -0,0 +1,65 @@ +#[doc = "Register `MWDATAH` writer"] +pub type W = crate::W; +#[doc = "Field `DATA0` writer - Data Byte 0"] +pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA1` writer - Data Byte 1"] +pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "End of Message\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum End { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: End) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - End of Message"] +pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; +impl<'a, REG> EndW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(End::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(End::End) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 0"] + #[inline(always)] + pub fn data0(&mut self) -> Data0W { + Data0W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn data1(&mut self) -> Data1W { + Data1W::new(self, 8) + } + #[doc = "Bit 16 - End of Message"] + #[inline(always)] + pub fn end(&mut self) -> EndW { + EndW::new(self, 16) + } +} +#[doc = "Controller Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatah::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MwdatahSpec; +impl crate::RegisterSpec for MwdatahSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mwdatah::W`](W) writer structure"] +impl crate::Writable for MwdatahSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWDATAH to value 0"] +impl crate::Resettable for MwdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/mwdatahe.rs b/mcxa276-pac/src/i3c0/mwdatahe.rs new file mode 100644 index 000000000..e37e91b52 --- /dev/null +++ b/mcxa276-pac/src/i3c0/mwdatahe.rs @@ -0,0 +1,29 @@ +#[doc = "Register `MWDATAHE` writer"] +pub type W = crate::W; +#[doc = "Field `DATA0` writer - Data Byte 0"] +pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA1` writer - Data Byte 1"] +pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Data Byte 0"] + #[inline(always)] + pub fn data0(&mut self) -> Data0W { + Data0W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn data1(&mut self) -> Data1W { + Data1W::new(self, 8) + } +} +#[doc = "Controller Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatahe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MwdataheSpec; +impl crate::RegisterSpec for MwdataheSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mwdatahe::W`](W) writer structure"] +impl crate::Writable for MwdataheSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MWDATAHE to value 0"] +impl crate::Resettable for MwdataheSpec {} diff --git a/mcxa276-pac/src/i3c0/scapabilities.rs b/mcxa276-pac/src/i3c0/scapabilities.rs new file mode 100644 index 000000000..18c174154 --- /dev/null +++ b/mcxa276-pac/src/i3c0/scapabilities.rs @@ -0,0 +1,674 @@ +#[doc = "Register `SCAPABILITIES` reader"] +pub type R = crate::R; +#[doc = "ID 48b Handler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Idena { + #[doc = "0: Application"] + Application = 0, + #[doc = "1: Hardware"] + Hw = 1, + #[doc = "2: Hardware, but the I3C module instance handles ID 48b"] + HwBut = 2, + #[doc = "3: A part number register (PARTNO)"] + Partno = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Idena) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Idena { + type Ux = u8; +} +impl crate::IsEnum for Idena {} +#[doc = "Field `IDENA` reader - ID 48b Handler"] +pub type IdenaR = crate::FieldReader; +impl IdenaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Idena { + match self.bits { + 0 => Idena::Application, + 1 => Idena::Hw, + 2 => Idena::HwBut, + 3 => Idena::Partno, + _ => unreachable!(), + } + } + #[doc = "Application"] + #[inline(always)] + pub fn is_application(&self) -> bool { + *self == Idena::Application + } + #[doc = "Hardware"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + *self == Idena::Hw + } + #[doc = "Hardware, but the I3C module instance handles ID 48b"] + #[inline(always)] + pub fn is_hw_but(&self) -> bool { + *self == Idena::HwBut + } + #[doc = "A part number register (PARTNO)"] + #[inline(always)] + pub fn is_partno(&self) -> bool { + *self == Idena::Partno + } +} +#[doc = "ID Register\n\nValue on reset: 12"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Idreg { + #[doc = "0: All ID register features disabled"] + AllDisabled = 0, + #[doc = "1: ID Instance is a register; used if there is no PARTNO register"] + IdInstance = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Idreg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Idreg { + type Ux = u8; +} +impl crate::IsEnum for Idreg {} +#[doc = "Field `IDREG` reader - ID Register"] +pub type IdregR = crate::FieldReader; +impl IdregR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Idreg::AllDisabled), + 1 => Some(Idreg::IdInstance), + _ => None, + } + } + #[doc = "All ID register features disabled"] + #[inline(always)] + pub fn is_all_disabled(&self) -> bool { + *self == Idreg::AllDisabled + } + #[doc = "ID Instance is a register; used if there is no PARTNO register"] + #[inline(always)] + pub fn is_id_instance(&self) -> bool { + *self == Idreg::IdInstance + } +} +#[doc = "High Data Rate Support\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Hdrsupp { + #[doc = "0: No HDR modes supported"] + NoHdr = 0, + #[doc = "1: DDR mode supported"] + Ddr = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Hdrsupp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Hdrsupp { + type Ux = u8; +} +impl crate::IsEnum for Hdrsupp {} +#[doc = "Field `HDRSUPP` reader - High Data Rate Support"] +pub type HdrsuppR = crate::FieldReader; +impl HdrsuppR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Hdrsupp::NoHdr), + 1 => Some(Hdrsupp::Ddr), + _ => None, + } + } + #[doc = "No HDR modes supported"] + #[inline(always)] + pub fn is_no_hdr(&self) -> bool { + *self == Hdrsupp::NoHdr + } + #[doc = "DDR mode supported"] + #[inline(always)] + pub fn is_ddr(&self) -> bool { + *self == Hdrsupp::Ddr + } +} +#[doc = "Controller\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Master { + #[doc = "0: Not supported"] + Masternotsupported = 0, + #[doc = "1: Supported"] + Mastersupported = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Master) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MASTER` reader - Controller"] +pub type MasterR = crate::BitReader; +impl MasterR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Master { + match self.bits { + false => Master::Masternotsupported, + true => Master::Mastersupported, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_masternotsupported(&self) -> bool { + *self == Master::Masternotsupported + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_mastersupported(&self) -> bool { + *self == Master::Mastersupported + } +} +#[doc = "Static Address\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Saddr { + #[doc = "0: No static address"] + NoStatic = 0, + #[doc = "1: Static address is fixed in hardware"] + Static = 1, + #[doc = "2: Hardware controls the static address dynamically (for example, from the pin strap)"] + HwControl = 2, + #[doc = "3: SCONFIG register supplies the static address"] + Config = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Saddr) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Saddr { + type Ux = u8; +} +impl crate::IsEnum for Saddr {} +#[doc = "Field `SADDR` reader - Static Address"] +pub type SaddrR = crate::FieldReader; +impl SaddrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Saddr { + match self.bits { + 0 => Saddr::NoStatic, + 1 => Saddr::Static, + 2 => Saddr::HwControl, + 3 => Saddr::Config, + _ => unreachable!(), + } + } + #[doc = "No static address"] + #[inline(always)] + pub fn is_no_static(&self) -> bool { + *self == Saddr::NoStatic + } + #[doc = "Static address is fixed in hardware"] + #[inline(always)] + pub fn is_static(&self) -> bool { + *self == Saddr::Static + } + #[doc = "Hardware controls the static address dynamically (for example, from the pin strap)"] + #[inline(always)] + pub fn is_hw_control(&self) -> bool { + *self == Saddr::HwControl + } + #[doc = "SCONFIG register supplies the static address"] + #[inline(always)] + pub fn is_config(&self) -> bool { + *self == Saddr::Config + } +} +#[doc = "Common Command Codes Handling\n\nValue on reset: 15"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ccchandle { + #[doc = "0: All handling features disabled"] + AllDisabled = 0, + #[doc = "1: The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items"] + BlockHandle = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ccchandle) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ccchandle { + type Ux = u8; +} +impl crate::IsEnum for Ccchandle {} +#[doc = "Field `CCCHANDLE` reader - Common Command Codes Handling"] +pub type CcchandleR = crate::FieldReader; +impl CcchandleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ccchandle::AllDisabled), + 1 => Some(Ccchandle::BlockHandle), + _ => None, + } + } + #[doc = "All handling features disabled"] + #[inline(always)] + pub fn is_all_disabled(&self) -> bool { + *self == Ccchandle::AllDisabled + } + #[doc = "The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items"] + #[inline(always)] + pub fn is_block_handle(&self) -> bool { + *self == Ccchandle::BlockHandle + } +} +#[doc = "In-Band Interrupts, Controller Requests, Hot-Join Events\n\nValue on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IbiMrHj { + #[doc = "0: Application cannot generate IBI, CR, or HJ"] + AllDisabled = 0, + #[doc = "1: Application can generate an IBI"] + Ibi = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IbiMrHj) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IbiMrHj { + type Ux = u8; +} +impl crate::IsEnum for IbiMrHj {} +#[doc = "Field `IBI_MR_HJ` reader - In-Band Interrupts, Controller Requests, Hot-Join Events"] +pub type IbiMrHjR = crate::FieldReader; +impl IbiMrHjR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(IbiMrHj::AllDisabled), + 1 => Some(IbiMrHj::Ibi), + _ => None, + } + } + #[doc = "Application cannot generate IBI, CR, or HJ"] + #[inline(always)] + pub fn is_all_disabled(&self) -> bool { + *self == IbiMrHj::AllDisabled + } + #[doc = "Application can generate an IBI"] + #[inline(always)] + pub fn is_ibi(&self) -> bool { + *self == IbiMrHj::Ibi + } +} +#[doc = "Time Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Timectrl { + #[doc = "0: No time control supported"] + NoTimeControlType = 0, + #[doc = "1: At least one time-control type supported"] + Atleast1TimeControl = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Timectrl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIMECTRL` reader - Time Control"] +pub type TimectrlR = crate::BitReader; +impl TimectrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timectrl { + match self.bits { + false => Timectrl::NoTimeControlType, + true => Timectrl::Atleast1TimeControl, + } + } + #[doc = "No time control supported"] + #[inline(always)] + pub fn is_no_time_control_type(&self) -> bool { + *self == Timectrl::NoTimeControlType + } + #[doc = "At least one time-control type supported"] + #[inline(always)] + pub fn is_atleast1_time_control(&self) -> bool { + *self == Timectrl::Atleast1TimeControl + } +} +#[doc = "External FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Extfifo { + #[doc = "0: No external FIFO available"] + NoExtFifo = 0, + #[doc = "1: Standard available or free external FIFO"] + StdExtFifo = 1, + #[doc = "2: Request track external FIFO"] + RequestExtFifo = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Extfifo) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Extfifo { + type Ux = u8; +} +impl crate::IsEnum for Extfifo {} +#[doc = "Field `EXTFIFO` reader - External FIFO"] +pub type ExtfifoR = crate::FieldReader; +impl ExtfifoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Extfifo::NoExtFifo), + 1 => Some(Extfifo::StdExtFifo), + 2 => Some(Extfifo::RequestExtFifo), + _ => None, + } + } + #[doc = "No external FIFO available"] + #[inline(always)] + pub fn is_no_ext_fifo(&self) -> bool { + *self == Extfifo::NoExtFifo + } + #[doc = "Standard available or free external FIFO"] + #[inline(always)] + pub fn is_std_ext_fifo(&self) -> bool { + *self == Extfifo::StdExtFifo + } + #[doc = "Request track external FIFO"] + #[inline(always)] + pub fn is_request_ext_fifo(&self) -> bool { + *self == Extfifo::RequestExtFifo + } +} +#[doc = "FIFO Transmit\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fifotx { + #[doc = "0: Two"] + Fifo2byte = 0, + #[doc = "1: Four"] + Fifo4byte = 1, + #[doc = "2: Eight"] + Fifo8byte = 2, + #[doc = "3: 16 or larger"] + Fifo16byte = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fifotx) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fifotx { + type Ux = u8; +} +impl crate::IsEnum for Fifotx {} +#[doc = "Field `FIFOTX` reader - FIFO Transmit"] +pub type FifotxR = crate::FieldReader; +impl FifotxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fifotx { + match self.bits { + 0 => Fifotx::Fifo2byte, + 1 => Fifotx::Fifo4byte, + 2 => Fifotx::Fifo8byte, + 3 => Fifotx::Fifo16byte, + _ => unreachable!(), + } + } + #[doc = "Two"] + #[inline(always)] + pub fn is_fifo_2byte(&self) -> bool { + *self == Fifotx::Fifo2byte + } + #[doc = "Four"] + #[inline(always)] + pub fn is_fifo_4byte(&self) -> bool { + *self == Fifotx::Fifo4byte + } + #[doc = "Eight"] + #[inline(always)] + pub fn is_fifo_8byte(&self) -> bool { + *self == Fifotx::Fifo8byte + } + #[doc = "16 or larger"] + #[inline(always)] + pub fn is_fifo_16byte(&self) -> bool { + *self == Fifotx::Fifo16byte + } +} +#[doc = "FIFO Receive\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fiforx { + #[doc = "0: Two or three"] + Fifo2byte = 0, + #[doc = "1: Four"] + Fifo4byte = 1, + #[doc = "2: Eight"] + Fifo8byte = 2, + #[doc = "3: 16 or larger"] + Fifo16byte = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fiforx) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fiforx { + type Ux = u8; +} +impl crate::IsEnum for Fiforx {} +#[doc = "Field `FIFORX` reader - FIFO Receive"] +pub type FiforxR = crate::FieldReader; +impl FiforxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fiforx { + match self.bits { + 0 => Fiforx::Fifo2byte, + 1 => Fiforx::Fifo4byte, + 2 => Fiforx::Fifo8byte, + 3 => Fiforx::Fifo16byte, + _ => unreachable!(), + } + } + #[doc = "Two or three"] + #[inline(always)] + pub fn is_fifo_2byte(&self) -> bool { + *self == Fiforx::Fifo2byte + } + #[doc = "Four"] + #[inline(always)] + pub fn is_fifo_4byte(&self) -> bool { + *self == Fiforx::Fifo4byte + } + #[doc = "Eight"] + #[inline(always)] + pub fn is_fifo_8byte(&self) -> bool { + *self == Fiforx::Fifo8byte + } + #[doc = "16 or larger"] + #[inline(always)] + pub fn is_fifo_16byte(&self) -> bool { + *self == Fiforx::Fifo16byte + } +} +#[doc = "Interrupts\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int { + #[doc = "0: Not supported"] + Interruptsno = 0, + #[doc = "1: Supported"] + Interruptsyes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT` reader - Interrupts"] +pub type IntR = crate::BitReader; +impl IntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int { + match self.bits { + false => Int::Interruptsno, + true => Int::Interruptsyes, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_interruptsno(&self) -> bool { + *self == Int::Interruptsno + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_interruptsyes(&self) -> bool { + *self == Int::Interruptsyes + } +} +#[doc = "Direct Memory Access\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dma { + #[doc = "0: Not supported"] + Dmano = 0, + #[doc = "1: Supported"] + Dmayes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dma) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA` reader - Direct Memory Access"] +pub type DmaR = crate::BitReader; +impl DmaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dma { + match self.bits { + false => Dma::Dmano, + true => Dma::Dmayes, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_dmano(&self) -> bool { + *self == Dma::Dmano + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_dmayes(&self) -> bool { + *self == Dma::Dmayes + } +} +impl R { + #[doc = "Bits 0:1 - ID 48b Handler"] + #[inline(always)] + pub fn idena(&self) -> IdenaR { + IdenaR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:5 - ID Register"] + #[inline(always)] + pub fn idreg(&self) -> IdregR { + IdregR::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bits 6:7 - High Data Rate Support"] + #[inline(always)] + pub fn hdrsupp(&self) -> HdrsuppR { + HdrsuppR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 9 - Controller"] + #[inline(always)] + pub fn master(&self) -> MasterR { + MasterR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - Static Address"] + #[inline(always)] + pub fn saddr(&self) -> SaddrR { + SaddrR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:15 - Common Command Codes Handling"] + #[inline(always)] + pub fn ccchandle(&self) -> CcchandleR { + CcchandleR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:20 - In-Band Interrupts, Controller Requests, Hot-Join Events"] + #[inline(always)] + pub fn ibi_mr_hj(&self) -> IbiMrHjR { + IbiMrHjR::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 21 - Time Control"] + #[inline(always)] + pub fn timectrl(&self) -> TimectrlR { + TimectrlR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 23:25 - External FIFO"] + #[inline(always)] + pub fn extfifo(&self) -> ExtfifoR { + ExtfifoR::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bits 26:27 - FIFO Transmit"] + #[inline(always)] + pub fn fifotx(&self) -> FifotxR { + FifotxR::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - FIFO Receive"] + #[inline(always)] + pub fn fiforx(&self) -> FiforxR { + FiforxR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - Interrupts"] + #[inline(always)] + pub fn int(&self) -> IntR { + IntR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Direct Memory Access"] + #[inline(always)] + pub fn dma(&self) -> DmaR { + DmaR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Target Capabilities\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScapabilitiesSpec; +impl crate::RegisterSpec for ScapabilitiesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scapabilities::R`](R) reader structure"] +impl crate::Readable for ScapabilitiesSpec {} +#[doc = "`reset()` method sets SCAPABILITIES to value 0xe83f_fe70"] +impl crate::Resettable for ScapabilitiesSpec { + const RESET_VALUE: u32 = 0xe83f_fe70; +} diff --git a/mcxa276-pac/src/i3c0/scapabilities2.rs b/mcxa276-pac/src/i3c0/scapabilities2.rs new file mode 100644 index 000000000..a2339be0f --- /dev/null +++ b/mcxa276-pac/src/i3c0/scapabilities2.rs @@ -0,0 +1,413 @@ +#[doc = "Register `SCAPABILITIES2` reader"] +pub type R = crate::R; +#[doc = "Field `MAPCNT` reader - Map Count"] +pub type MapcntR = crate::FieldReader; +#[doc = "I2C 10-bit Address\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I2c10b { + #[doc = "0: Not supported"] + Disable = 0, + #[doc = "1: Supported"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I2c10b) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I2C10B` reader - I2C 10-bit Address"] +pub type I2c10bR = crate::BitReader; +impl I2c10bR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I2c10b { + match self.bits { + false => I2c10b::Disable, + true => I2c10b::Enable, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == I2c10b::Disable + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == I2c10b::Enable + } +} +#[doc = "I2C Device ID\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I2cdevid { + #[doc = "0: Not supported"] + Disable = 0, + #[doc = "1: Supported"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I2cdevid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I2CDEVID` reader - I2C Device ID"] +pub type I2cdevidR = crate::BitReader; +impl I2cdevidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I2cdevid { + match self.bits { + false => I2cdevid::Disable, + true => I2cdevid::Enable, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == I2cdevid::Disable + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == I2cdevid::Enable + } +} +#[doc = "In-Band Interrupt EXTDATA\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibiext { + #[doc = "0: Not supported"] + Disable = 0, + #[doc = "1: Supported"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibiext) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBIEXT` reader - In-Band Interrupt EXTDATA"] +pub type IbiextR = crate::BitReader; +impl IbiextR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibiext { + match self.bits { + false => Ibiext::Disable, + true => Ibiext::Enable, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ibiext::Disable + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ibiext::Enable + } +} +#[doc = "In-Band Interrupt Extended Register\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibixreg { + #[doc = "0: Not supported"] + Disable = 0, + #[doc = "1: Supported"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibixreg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBIXREG` reader - In-Band Interrupt Extended Register"] +pub type IbixregR = crate::BitReader; +impl IbixregR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibixreg { + match self.bits { + false => Ibixreg::Disable, + true => Ibixreg::Enable, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ibixreg::Disable + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ibixreg::Enable + } +} +#[doc = "Target Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slvrst { + #[doc = "0: Not supported"] + Disable = 0, + #[doc = "1: Supported"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slvrst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLVRST` reader - Target Reset"] +pub type SlvrstR = crate::BitReader; +impl SlvrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slvrst { + match self.bits { + false => Slvrst::Disable, + true => Slvrst::Enable, + } + } + #[doc = "Not supported"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Slvrst::Disable + } + #[doc = "Supported"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Slvrst::Enable + } +} +#[doc = "Group\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Group { + #[doc = "0: v1.1 group addressing not supported"] + Notsupported = 0, + #[doc = "1: One group supported"] + One = 1, + #[doc = "2: Two groups supported"] + Two = 2, + #[doc = "3: Three groups supported"] + Three = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Group) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Group { + type Ux = u8; +} +impl crate::IsEnum for Group {} +#[doc = "Field `GROUP` reader - Group"] +pub type GroupR = crate::FieldReader; +impl GroupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Group { + match self.bits { + 0 => Group::Notsupported, + 1 => Group::One, + 2 => Group::Two, + 3 => Group::Three, + _ => unreachable!(), + } + } + #[doc = "v1.1 group addressing not supported"] + #[inline(always)] + pub fn is_notsupported(&self) -> bool { + *self == Group::Notsupported + } + #[doc = "One group supported"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Group::One + } + #[doc = "Two groups supported"] + #[inline(always)] + pub fn is_two(&self) -> bool { + *self == Group::Two + } + #[doc = "Three groups supported"] + #[inline(always)] + pub fn is_three(&self) -> bool { + *self == Group::Three + } +} +#[doc = "SETAASA\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aasa { + #[doc = "0: SETAASA not supported"] + Notsupported = 0, + #[doc = "1: SETAASA supported"] + Supported = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aasa) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AASA` reader - SETAASA"] +pub type AasaR = crate::BitReader; +impl AasaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aasa { + match self.bits { + false => Aasa::Notsupported, + true => Aasa::Supported, + } + } + #[doc = "SETAASA not supported"] + #[inline(always)] + pub fn is_notsupported(&self) -> bool { + *self == Aasa::Notsupported + } + #[doc = "SETAASA supported"] + #[inline(always)] + pub fn is_supported(&self) -> bool { + *self == Aasa::Supported + } +} +#[doc = "Target-Target(s)-Tunnel Subscriber Capable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sstsub { + #[doc = "0: Not subscriber capable"] + Notsupported = 0, + #[doc = "1: Subscriber capable"] + Supported = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sstsub) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSTSUB` reader - Target-Target(s)-Tunnel Subscriber Capable"] +pub type SstsubR = crate::BitReader; +impl SstsubR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sstsub { + match self.bits { + false => Sstsub::Notsupported, + true => Sstsub::Supported, + } + } + #[doc = "Not subscriber capable"] + #[inline(always)] + pub fn is_notsupported(&self) -> bool { + *self == Sstsub::Notsupported + } + #[doc = "Subscriber capable"] + #[inline(always)] + pub fn is_supported(&self) -> bool { + *self == Sstsub::Supported + } +} +#[doc = "Target-Target(s)-Tunnel Write Capable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sstwr { + #[doc = "0: Not write capable"] + Notsupported = 0, + #[doc = "1: Write capable"] + Supported = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sstwr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSTWR` reader - Target-Target(s)-Tunnel Write Capable"] +pub type SstwrR = crate::BitReader; +impl SstwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sstwr { + match self.bits { + false => Sstwr::Notsupported, + true => Sstwr::Supported, + } + } + #[doc = "Not write capable"] + #[inline(always)] + pub fn is_notsupported(&self) -> bool { + *self == Sstwr::Notsupported + } + #[doc = "Write capable"] + #[inline(always)] + pub fn is_supported(&self) -> bool { + *self == Sstwr::Supported + } +} +impl R { + #[doc = "Bits 0:3 - Map Count"] + #[inline(always)] + pub fn mapcnt(&self) -> MapcntR { + MapcntR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - I2C 10-bit Address"] + #[inline(always)] + pub fn i2c10b(&self) -> I2c10bR { + I2c10bR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - I2C Device ID"] + #[inline(always)] + pub fn i2cdevid(&self) -> I2cdevidR { + I2cdevidR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - In-Band Interrupt EXTDATA"] + #[inline(always)] + pub fn ibiext(&self) -> IbiextR { + IbiextR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - In-Band Interrupt Extended Register"] + #[inline(always)] + pub fn ibixreg(&self) -> IbixregR { + IbixregR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 17 - Target Reset"] + #[inline(always)] + pub fn slvrst(&self) -> SlvrstR { + SlvrstR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Group"] + #[inline(always)] + pub fn group(&self) -> GroupR { + GroupR::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 21 - SETAASA"] + #[inline(always)] + pub fn aasa(&self) -> AasaR { + AasaR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Target-Target(s)-Tunnel Subscriber Capable"] + #[inline(always)] + pub fn sstsub(&self) -> SstsubR { + SstsubR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Target-Target(s)-Tunnel Write Capable"] + #[inline(always)] + pub fn sstwr(&self) -> SstwrR { + SstwrR::new(((self.bits >> 23) & 1) != 0) + } +} +#[doc = "Target Capabilities 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scapabilities2Spec; +impl crate::RegisterSpec for Scapabilities2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scapabilities2::R`](R) reader structure"] +impl crate::Readable for Scapabilities2Spec {} +#[doc = "`reset()` method sets SCAPABILITIES2 to value 0x0300"] +impl crate::Resettable for Scapabilities2Spec { + const RESET_VALUE: u32 = 0x0300; +} diff --git a/mcxa276-pac/src/i3c0/sconfig.rs b/mcxa276-pac/src/i3c0/sconfig.rs new file mode 100644 index 000000000..d364ddc66 --- /dev/null +++ b/mcxa276-pac/src/i3c0/sconfig.rs @@ -0,0 +1,429 @@ +#[doc = "Register `SCONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `SCONFIG` writer"] +pub type W = crate::W; +#[doc = "Target Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slvena { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slvena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLVENA` reader - Target Enable"] +pub type SlvenaR = crate::BitReader; +impl SlvenaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slvena { + match self.bits { + false => Slvena::Disable, + true => Slvena::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Slvena::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Slvena::Enable + } +} +#[doc = "Field `SLVENA` writer - Target Enable"] +pub type SlvenaW<'a, REG> = crate::BitWriter<'a, REG, Slvena>; +impl<'a, REG> SlvenaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Slvena::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Slvena::Enable) + } +} +#[doc = "Not Acknowledge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nack { + #[doc = "0: Always disable NACK mode"] + Disable = 0, + #[doc = "1: Always enable NACK mode (works normally)"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NACK` reader - Not Acknowledge"] +pub type NackR = crate::BitReader; +impl NackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nack { + match self.bits { + false => Nack::Disable, + true => Nack::Enable, + } + } + #[doc = "Always disable NACK mode"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Nack::Disable + } + #[doc = "Always enable NACK mode (works normally)"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Nack::Enable + } +} +#[doc = "Field `NACK` writer - Not Acknowledge"] +pub type NackW<'a, REG> = crate::BitWriter<'a, REG, Nack>; +impl<'a, REG> NackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Always disable NACK mode"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Nack::Disable) + } + #[doc = "Always enable NACK mode (works normally)"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Nack::Enable) + } +} +#[doc = "Match Start or Stop\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Matchss { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Matchss) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MATCHSS` reader - Match Start or Stop"] +pub type MatchssR = crate::BitReader; +impl MatchssR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Matchss { + match self.bits { + false => Matchss::Disable, + true => Matchss::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Matchss::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Matchss::Enable + } +} +#[doc = "Field `MATCHSS` writer - Match Start or Stop"] +pub type MatchssW<'a, REG> = crate::BitWriter<'a, REG, Matchss>; +impl<'a, REG> MatchssW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Matchss::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Matchss::Enable) + } +} +#[doc = "Ignore TE0 or TE1 Errors\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum S0ignore { + #[doc = "0: Do not ignore TE0 or TE1 errors"] + Disable = 0, + #[doc = "1: Ignore TE0 or TE1 errors"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0ignore) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S0IGNORE` reader - Ignore TE0 or TE1 Errors"] +pub type S0ignoreR = crate::BitReader; +impl S0ignoreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> S0ignore { + match self.bits { + false => S0ignore::Disable, + true => S0ignore::Enable, + } + } + #[doc = "Do not ignore TE0 or TE1 errors"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == S0ignore::Disable + } + #[doc = "Ignore TE0 or TE1 errors"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == S0ignore::Enable + } +} +#[doc = "Field `S0IGNORE` writer - Ignore TE0 or TE1 Errors"] +pub type S0ignoreW<'a, REG> = crate::BitWriter<'a, REG, S0ignore>; +impl<'a, REG> S0ignoreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Do not ignore TE0 or TE1 errors"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(S0ignore::Disable) + } + #[doc = "Ignore TE0 or TE1 errors"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(S0ignore::Enable) + } +} +#[doc = "HDR OK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hdrok { + #[doc = "0: Disable HDR OK"] + Disable = 0, + #[doc = "1: Enable HDR OK"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hdrok) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HDROK` reader - HDR OK"] +pub type HdrokR = crate::BitReader; +impl HdrokR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hdrok { + match self.bits { + false => Hdrok::Disable, + true => Hdrok::Enable, + } + } + #[doc = "Disable HDR OK"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Hdrok::Disable + } + #[doc = "Enable HDR OK"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Hdrok::Enable + } +} +#[doc = "Field `HDROK` writer - HDR OK"] +pub type HdrokW<'a, REG> = crate::BitWriter<'a, REG, Hdrok>; +impl<'a, REG> HdrokW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable HDR OK"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Hdrok::Disable) + } + #[doc = "Enable HDR OK"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Hdrok::Enable) + } +} +#[doc = "Offline\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Offline { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Offline) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OFFLINE` reader - Offline"] +pub type OfflineR = crate::BitReader; +impl OfflineR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Offline { + match self.bits { + false => Offline::Disable, + true => Offline::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Offline::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Offline::Enable + } +} +#[doc = "Field `OFFLINE` writer - Offline"] +pub type OfflineW<'a, REG> = crate::BitWriter<'a, REG, Offline>; +impl<'a, REG> OfflineW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Offline::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Offline::Enable) + } +} +#[doc = "Field `BAMATCH` reader - Bus Available Match"] +pub type BamatchR = crate::FieldReader; +#[doc = "Field `BAMATCH` writer - Bus Available Match"] +pub type BamatchW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SADDR` reader - Static Address"] +pub type SaddrR = crate::FieldReader; +#[doc = "Field `SADDR` writer - Static Address"] +pub type SaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bit 0 - Target Enable"] + #[inline(always)] + pub fn slvena(&self) -> SlvenaR { + SlvenaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Not Acknowledge"] + #[inline(always)] + pub fn nack(&self) -> NackR { + NackR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Match Start or Stop"] + #[inline(always)] + pub fn matchss(&self) -> MatchssR { + MatchssR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Ignore TE0 or TE1 Errors"] + #[inline(always)] + pub fn s0ignore(&self) -> S0ignoreR { + S0ignoreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - HDR OK"] + #[inline(always)] + pub fn hdrok(&self) -> HdrokR { + HdrokR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 9 - Offline"] + #[inline(always)] + pub fn offline(&self) -> OfflineR { + OfflineR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:21 - Bus Available Match"] + #[inline(always)] + pub fn bamatch(&self) -> BamatchR { + BamatchR::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 25:31 - Static Address"] + #[inline(always)] + pub fn saddr(&self) -> SaddrR { + SaddrR::new(((self.bits >> 25) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Target Enable"] + #[inline(always)] + pub fn slvena(&mut self) -> SlvenaW { + SlvenaW::new(self, 0) + } + #[doc = "Bit 1 - Not Acknowledge"] + #[inline(always)] + pub fn nack(&mut self) -> NackW { + NackW::new(self, 1) + } + #[doc = "Bit 2 - Match Start or Stop"] + #[inline(always)] + pub fn matchss(&mut self) -> MatchssW { + MatchssW::new(self, 2) + } + #[doc = "Bit 3 - Ignore TE0 or TE1 Errors"] + #[inline(always)] + pub fn s0ignore(&mut self) -> S0ignoreW { + S0ignoreW::new(self, 3) + } + #[doc = "Bit 4 - HDR OK"] + #[inline(always)] + pub fn hdrok(&mut self) -> HdrokW { + HdrokW::new(self, 4) + } + #[doc = "Bit 9 - Offline"] + #[inline(always)] + pub fn offline(&mut self) -> OfflineW { + OfflineW::new(self, 9) + } + #[doc = "Bits 16:21 - Bus Available Match"] + #[inline(always)] + pub fn bamatch(&mut self) -> BamatchW { + BamatchW::new(self, 16) + } + #[doc = "Bits 25:31 - Static Address"] + #[inline(always)] + pub fn saddr(&mut self) -> SaddrW { + SaddrW::new(self, 25) + } +} +#[doc = "Target Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`sconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SconfigSpec; +impl crate::RegisterSpec for SconfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sconfig::R`](R) reader structure"] +impl crate::Readable for SconfigSpec {} +#[doc = "`write(|w| ..)` method takes [`sconfig::W`](W) writer structure"] +impl crate::Writable for SconfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCONFIG to value 0x0017_0000"] +impl crate::Resettable for SconfigSpec { + const RESET_VALUE: u32 = 0x0017_0000; +} diff --git a/mcxa276-pac/src/i3c0/sctrl.rs b/mcxa276-pac/src/i3c0/sctrl.rs new file mode 100644 index 000000000..565ed5a51 --- /dev/null +++ b/mcxa276-pac/src/i3c0/sctrl.rs @@ -0,0 +1,236 @@ +#[doc = "Register `SCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SCTRL` writer"] +pub type W = crate::W; +#[doc = "Event\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Event { + #[doc = "0: NORMAL_MODE"] + NormalMode = 0, + #[doc = "1: IBI"] + Ibi = 1, + #[doc = "2: CONTROLLER_REQUEST"] + MasterRequest = 2, + #[doc = "3: HOT_JOIN_REQUEST"] + HotJoinRequest = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Event) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Event { + type Ux = u8; +} +impl crate::IsEnum for Event {} +#[doc = "Field `EVENT` reader - Event"] +pub type EventR = crate::FieldReader; +impl EventR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Event { + match self.bits { + 0 => Event::NormalMode, + 1 => Event::Ibi, + 2 => Event::MasterRequest, + 3 => Event::HotJoinRequest, + _ => unreachable!(), + } + } + #[doc = "NORMAL_MODE"] + #[inline(always)] + pub fn is_normal_mode(&self) -> bool { + *self == Event::NormalMode + } + #[doc = "IBI"] + #[inline(always)] + pub fn is_ibi(&self) -> bool { + *self == Event::Ibi + } + #[doc = "CONTROLLER_REQUEST"] + #[inline(always)] + pub fn is_master_request(&self) -> bool { + *self == Event::MasterRequest + } + #[doc = "HOT_JOIN_REQUEST"] + #[inline(always)] + pub fn is_hot_join_request(&self) -> bool { + *self == Event::HotJoinRequest + } +} +#[doc = "Field `EVENT` writer - Event"] +pub type EventW<'a, REG> = crate::FieldWriter<'a, REG, 2, Event, crate::Safe>; +impl<'a, REG> EventW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "NORMAL_MODE"] + #[inline(always)] + pub fn normal_mode(self) -> &'a mut crate::W { + self.variant(Event::NormalMode) + } + #[doc = "IBI"] + #[inline(always)] + pub fn ibi(self) -> &'a mut crate::W { + self.variant(Event::Ibi) + } + #[doc = "CONTROLLER_REQUEST"] + #[inline(always)] + pub fn master_request(self) -> &'a mut crate::W { + self.variant(Event::MasterRequest) + } + #[doc = "HOT_JOIN_REQUEST"] + #[inline(always)] + pub fn hot_join_request(self) -> &'a mut crate::W { + self.variant(Event::HotJoinRequest) + } +} +#[doc = "Extended Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Extdata { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Extdata) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EXTDATA` reader - Extended Data"] +pub type ExtdataR = crate::BitReader; +impl ExtdataR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Extdata { + match self.bits { + false => Extdata::Disable, + true => Extdata::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Extdata::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Extdata::Enable + } +} +#[doc = "Field `EXTDATA` writer - Extended Data"] +pub type ExtdataW<'a, REG> = crate::BitWriter<'a, REG, Extdata>; +impl<'a, REG> ExtdataW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Extdata::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Extdata::Enable) + } +} +#[doc = "Field `IBIDATA` reader - In-Band Interrupt Data"] +pub type IbidataR = crate::FieldReader; +#[doc = "Field `IBIDATA` writer - In-Band Interrupt Data"] +pub type IbidataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PENDINT` reader - Pending Interrupt"] +pub type PendintR = crate::FieldReader; +#[doc = "Field `PENDINT` writer - Pending Interrupt"] +pub type PendintW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ACTSTATE` reader - Activity State of Target"] +pub type ActstateR = crate::FieldReader; +#[doc = "Field `ACTSTATE` writer - Activity State of Target"] +pub type ActstateW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `VENDINFO` reader - Vendor Information"] +pub type VendinfoR = crate::FieldReader; +#[doc = "Field `VENDINFO` writer - Vendor Information"] +pub type VendinfoW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:1 - Event"] + #[inline(always)] + pub fn event(&self) -> EventR { + EventR::new((self.bits & 3) as u8) + } + #[doc = "Bit 3 - Extended Data"] + #[inline(always)] + pub fn extdata(&self) -> ExtdataR { + ExtdataR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 8:15 - In-Band Interrupt Data"] + #[inline(always)] + pub fn ibidata(&self) -> IbidataR { + IbidataR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:19 - Pending Interrupt"] + #[inline(always)] + pub fn pendint(&self) -> PendintR { + PendintR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:21 - Activity State of Target"] + #[inline(always)] + pub fn actstate(&self) -> ActstateR { + ActstateR::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 24:31 - Vendor Information"] + #[inline(always)] + pub fn vendinfo(&self) -> VendinfoR { + VendinfoR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Event"] + #[inline(always)] + pub fn event(&mut self) -> EventW { + EventW::new(self, 0) + } + #[doc = "Bit 3 - Extended Data"] + #[inline(always)] + pub fn extdata(&mut self) -> ExtdataW { + ExtdataW::new(self, 3) + } + #[doc = "Bits 8:15 - In-Band Interrupt Data"] + #[inline(always)] + pub fn ibidata(&mut self) -> IbidataW { + IbidataW::new(self, 8) + } + #[doc = "Bits 16:19 - Pending Interrupt"] + #[inline(always)] + pub fn pendint(&mut self) -> PendintW { + PendintW::new(self, 16) + } + #[doc = "Bits 20:21 - Activity State of Target"] + #[inline(always)] + pub fn actstate(&mut self) -> ActstateW { + ActstateW::new(self, 20) + } + #[doc = "Bits 24:31 - Vendor Information"] + #[inline(always)] + pub fn vendinfo(&mut self) -> VendinfoW { + VendinfoW::new(self, 24) + } +} +#[doc = "Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SctrlSpec; +impl crate::RegisterSpec for SctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sctrl::R`](R) reader structure"] +impl crate::Readable for SctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sctrl::W`](W) writer structure"] +impl crate::Writable for SctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCTRL to value 0"] +impl crate::Resettable for SctrlSpec {} diff --git a/mcxa276-pac/src/i3c0/sdatactrl.rs b/mcxa276-pac/src/i3c0/sdatactrl.rs new file mode 100644 index 000000000..4e9e5ba1d --- /dev/null +++ b/mcxa276-pac/src/i3c0/sdatactrl.rs @@ -0,0 +1,419 @@ +#[doc = "Register `SDATACTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SDATACTRL` writer"] +pub type W = crate::W; +#[doc = "Flush To-Bus Buffer or FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flushtb { + #[doc = "0: No action"] + NoAction = 0, + #[doc = "1: Flush the buffer"] + Flush = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flushtb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLUSHTB` writer - Flush To-Bus Buffer or FIFO"] +pub type FlushtbW<'a, REG> = crate::BitWriter<'a, REG, Flushtb>; +impl<'a, REG> FlushtbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No action"] + #[inline(always)] + pub fn no_action(self) -> &'a mut crate::W { + self.variant(Flushtb::NoAction) + } + #[doc = "Flush the buffer"] + #[inline(always)] + pub fn flush(self) -> &'a mut crate::W { + self.variant(Flushtb::Flush) + } +} +#[doc = "Flush From-Bus Buffer or FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flushfb { + #[doc = "0: No action"] + NoAction = 0, + #[doc = "1: Flush the buffer"] + Flush = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flushfb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLUSHFB` writer - Flush From-Bus Buffer or FIFO"] +pub type FlushfbW<'a, REG> = crate::BitWriter<'a, REG, Flushfb>; +impl<'a, REG> FlushfbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No action"] + #[inline(always)] + pub fn no_action(self) -> &'a mut crate::W { + self.variant(Flushfb::NoAction) + } + #[doc = "Flush the buffer"] + #[inline(always)] + pub fn flush(self) -> &'a mut crate::W { + self.variant(Flushfb::Flush) + } +} +#[doc = "Unlock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unlock { + #[doc = "0: Cannot be changed"] + Disabled = 0, + #[doc = "1: Can be changed"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unlock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNLOCK` writer - Unlock"] +pub type UnlockW<'a, REG> = crate::BitWriter<'a, REG, Unlock>; +impl<'a, REG> UnlockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Cannot be changed"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Unlock::Disabled) + } + #[doc = "Can be changed"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Unlock::Enabled) + } +} +#[doc = "Transmit Trigger Level\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Txtrig { + #[doc = "0: Trigger when empty"] + Triggrempty = 0, + #[doc = "1: Trigger when 1/4 full or less"] + Triggronefourth = 1, + #[doc = "2: Trigger when 1/2 full or less"] + Triggronehalf = 2, + #[doc = "3: Default (trigger when 1 less than full or less)"] + Triggroneless = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Txtrig) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Txtrig { + type Ux = u8; +} +impl crate::IsEnum for Txtrig {} +#[doc = "Field `TXTRIG` reader - Transmit Trigger Level"] +pub type TxtrigR = crate::FieldReader; +impl TxtrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txtrig { + match self.bits { + 0 => Txtrig::Triggrempty, + 1 => Txtrig::Triggronefourth, + 2 => Txtrig::Triggronehalf, + 3 => Txtrig::Triggroneless, + _ => unreachable!(), + } + } + #[doc = "Trigger when empty"] + #[inline(always)] + pub fn is_triggrempty(&self) -> bool { + *self == Txtrig::Triggrempty + } + #[doc = "Trigger when 1/4 full or less"] + #[inline(always)] + pub fn is_triggronefourth(&self) -> bool { + *self == Txtrig::Triggronefourth + } + #[doc = "Trigger when 1/2 full or less"] + #[inline(always)] + pub fn is_triggronehalf(&self) -> bool { + *self == Txtrig::Triggronehalf + } + #[doc = "Default (trigger when 1 less than full or less)"] + #[inline(always)] + pub fn is_triggroneless(&self) -> bool { + *self == Txtrig::Triggroneless + } +} +#[doc = "Field `TXTRIG` writer - Transmit Trigger Level"] +pub type TxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txtrig, crate::Safe>; +impl<'a, REG> TxtrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Trigger when empty"] + #[inline(always)] + pub fn triggrempty(self) -> &'a mut crate::W { + self.variant(Txtrig::Triggrempty) + } + #[doc = "Trigger when 1/4 full or less"] + #[inline(always)] + pub fn triggronefourth(self) -> &'a mut crate::W { + self.variant(Txtrig::Triggronefourth) + } + #[doc = "Trigger when 1/2 full or less"] + #[inline(always)] + pub fn triggronehalf(self) -> &'a mut crate::W { + self.variant(Txtrig::Triggronehalf) + } + #[doc = "Default (trigger when 1 less than full or less)"] + #[inline(always)] + pub fn triggroneless(self) -> &'a mut crate::W { + self.variant(Txtrig::Triggroneless) + } +} +#[doc = "Receive Trigger Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Rxtrig { + #[doc = "0: Trigger when not empty (default)"] + Triggrnotempty = 0, + #[doc = "1: Trigger when 1/4 or more full"] + Triggronefourth = 1, + #[doc = "2: Trigger when 1/2 or more full"] + Triggronehalf = 2, + #[doc = "3: Trigger when 3/4 or more full"] + Triggrthreefourths = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Rxtrig) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Rxtrig { + type Ux = u8; +} +impl crate::IsEnum for Rxtrig {} +#[doc = "Field `RXTRIG` reader - Receive Trigger Level"] +pub type RxtrigR = crate::FieldReader; +impl RxtrigR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxtrig { + match self.bits { + 0 => Rxtrig::Triggrnotempty, + 1 => Rxtrig::Triggronefourth, + 2 => Rxtrig::Triggronehalf, + 3 => Rxtrig::Triggrthreefourths, + _ => unreachable!(), + } + } + #[doc = "Trigger when not empty (default)"] + #[inline(always)] + pub fn is_triggrnotempty(&self) -> bool { + *self == Rxtrig::Triggrnotempty + } + #[doc = "Trigger when 1/4 or more full"] + #[inline(always)] + pub fn is_triggronefourth(&self) -> bool { + *self == Rxtrig::Triggronefourth + } + #[doc = "Trigger when 1/2 or more full"] + #[inline(always)] + pub fn is_triggronehalf(&self) -> bool { + *self == Rxtrig::Triggronehalf + } + #[doc = "Trigger when 3/4 or more full"] + #[inline(always)] + pub fn is_triggrthreefourths(&self) -> bool { + *self == Rxtrig::Triggrthreefourths + } +} +#[doc = "Field `RXTRIG` writer - Receive Trigger Level"] +pub type RxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxtrig, crate::Safe>; +impl<'a, REG> RxtrigW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Trigger when not empty (default)"] + #[inline(always)] + pub fn triggrnotempty(self) -> &'a mut crate::W { + self.variant(Rxtrig::Triggrnotempty) + } + #[doc = "Trigger when 1/4 or more full"] + #[inline(always)] + pub fn triggronefourth(self) -> &'a mut crate::W { + self.variant(Rxtrig::Triggronefourth) + } + #[doc = "Trigger when 1/2 or more full"] + #[inline(always)] + pub fn triggronehalf(self) -> &'a mut crate::W { + self.variant(Rxtrig::Triggronehalf) + } + #[doc = "Trigger when 3/4 or more full"] + #[inline(always)] + pub fn triggrthreefourths(self) -> &'a mut crate::W { + self.variant(Rxtrig::Triggrthreefourths) + } +} +#[doc = "Field `TXCOUNT` reader - Count of Entries in Transmit"] +pub type TxcountR = crate::FieldReader; +#[doc = "Field `RXCOUNT` reader - Count of Entries in Receive"] +pub type RxcountR = crate::FieldReader; +#[doc = "Transmit is Full\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txfull { + #[doc = "0: Not full"] + Txisnotfull = 0, + #[doc = "1: Full"] + Txisfull = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txfull) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXFULL` reader - Transmit is Full"] +pub type TxfullR = crate::BitReader; +impl TxfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txfull { + match self.bits { + false => Txfull::Txisnotfull, + true => Txfull::Txisfull, + } + } + #[doc = "Not full"] + #[inline(always)] + pub fn is_txisnotfull(&self) -> bool { + *self == Txfull::Txisnotfull + } + #[doc = "Full"] + #[inline(always)] + pub fn is_txisfull(&self) -> bool { + *self == Txfull::Txisfull + } +} +#[doc = "Receive is Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempty { + #[doc = "0: Not empty"] + Rxisnotempty = 0, + #[doc = "1: Empty"] + Rxisempty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPTY` reader - Receive is Empty"] +pub type RxemptyR = crate::BitReader; +impl RxemptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempty { + match self.bits { + false => Rxempty::Rxisnotempty, + true => Rxempty::Rxisempty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_rxisnotempty(&self) -> bool { + *self == Rxempty::Rxisnotempty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_rxisempty(&self) -> bool { + *self == Rxempty::Rxisempty + } +} +impl R { + #[doc = "Bits 4:5 - Transmit Trigger Level"] + #[inline(always)] + pub fn txtrig(&self) -> TxtrigR { + TxtrigR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Receive Trigger Level"] + #[inline(always)] + pub fn rxtrig(&self) -> RxtrigR { + RxtrigR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 16:20 - Count of Entries in Transmit"] + #[inline(always)] + pub fn txcount(&self) -> TxcountR { + TxcountR::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - Count of Entries in Receive"] + #[inline(always)] + pub fn rxcount(&self) -> RxcountR { + RxcountR::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 30 - Transmit is Full"] + #[inline(always)] + pub fn txfull(&self) -> TxfullR { + TxfullR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Receive is Empty"] + #[inline(always)] + pub fn rxempty(&self) -> RxemptyR { + RxemptyR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush To-Bus Buffer or FIFO"] + #[inline(always)] + pub fn flushtb(&mut self) -> FlushtbW { + FlushtbW::new(self, 0) + } + #[doc = "Bit 1 - Flush From-Bus Buffer or FIFO"] + #[inline(always)] + pub fn flushfb(&mut self) -> FlushfbW { + FlushfbW::new(self, 1) + } + #[doc = "Bit 3 - Unlock"] + #[inline(always)] + pub fn unlock(&mut self) -> UnlockW { + UnlockW::new(self, 3) + } + #[doc = "Bits 4:5 - Transmit Trigger Level"] + #[inline(always)] + pub fn txtrig(&mut self) -> TxtrigW { + TxtrigW::new(self, 4) + } + #[doc = "Bits 6:7 - Receive Trigger Level"] + #[inline(always)] + pub fn rxtrig(&mut self) -> RxtrigW { + RxtrigW::new(self, 6) + } +} +#[doc = "Target Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdatactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdatactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SdatactrlSpec; +impl crate::RegisterSpec for SdatactrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdatactrl::R`](R) reader structure"] +impl crate::Readable for SdatactrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sdatactrl::W`](W) writer structure"] +impl crate::Writable for SdatactrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SDATACTRL to value 0x8000_0030"] +impl crate::Resettable for SdatactrlSpec { + const RESET_VALUE: u32 = 0x8000_0030; +} diff --git a/mcxa276-pac/src/i3c0/sdmactrl.rs b/mcxa276-pac/src/i3c0/sdmactrl.rs new file mode 100644 index 000000000..251a989bc --- /dev/null +++ b/mcxa276-pac/src/i3c0/sdmactrl.rs @@ -0,0 +1,272 @@ +#[doc = "Register `SDMACTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SDMACTRL` writer"] +pub type W = crate::W; +#[doc = "DMA Read (From-Bus) Trigger\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dmafb { + #[doc = "0: DMA not used"] + NotUsed = 0, + #[doc = "1: DMA enabled for one frame"] + EnableOneFrame = 1, + #[doc = "2: DMA enabled until turned off"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dmafb) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dmafb { + type Ux = u8; +} +impl crate::IsEnum for Dmafb {} +#[doc = "Field `DMAFB` reader - DMA Read (From-Bus) Trigger"] +pub type DmafbR = crate::FieldReader; +impl DmafbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dmafb::NotUsed), + 1 => Some(Dmafb::EnableOneFrame), + 2 => Some(Dmafb::Enable), + _ => None, + } + } + #[doc = "DMA not used"] + #[inline(always)] + pub fn is_not_used(&self) -> bool { + *self == Dmafb::NotUsed + } + #[doc = "DMA enabled for one frame"] + #[inline(always)] + pub fn is_enable_one_frame(&self) -> bool { + *self == Dmafb::EnableOneFrame + } + #[doc = "DMA enabled until turned off"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dmafb::Enable + } +} +#[doc = "Field `DMAFB` writer - DMA Read (From-Bus) Trigger"] +pub type DmafbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmafb>; +impl<'a, REG> DmafbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "DMA not used"] + #[inline(always)] + pub fn not_used(self) -> &'a mut crate::W { + self.variant(Dmafb::NotUsed) + } + #[doc = "DMA enabled for one frame"] + #[inline(always)] + pub fn enable_one_frame(self) -> &'a mut crate::W { + self.variant(Dmafb::EnableOneFrame) + } + #[doc = "DMA enabled until turned off"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dmafb::Enable) + } +} +#[doc = "DMA Write (To-Bus) Trigger\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dmatb { + #[doc = "0: DMA not used"] + NotUsed = 0, + #[doc = "1: DMA enabled for one frame"] + EnableOneFrame = 1, + #[doc = "2: DMA enabled until turned off"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dmatb) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dmatb { + type Ux = u8; +} +impl crate::IsEnum for Dmatb {} +#[doc = "Field `DMATB` reader - DMA Write (To-Bus) Trigger"] +pub type DmatbR = crate::FieldReader; +impl DmatbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dmatb::NotUsed), + 1 => Some(Dmatb::EnableOneFrame), + 2 => Some(Dmatb::Enable), + _ => None, + } + } + #[doc = "DMA not used"] + #[inline(always)] + pub fn is_not_used(&self) -> bool { + *self == Dmatb::NotUsed + } + #[doc = "DMA enabled for one frame"] + #[inline(always)] + pub fn is_enable_one_frame(&self) -> bool { + *self == Dmatb::EnableOneFrame + } + #[doc = "DMA enabled until turned off"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dmatb::Enable + } +} +#[doc = "Field `DMATB` writer - DMA Write (To-Bus) Trigger"] +pub type DmatbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmatb>; +impl<'a, REG> DmatbW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "DMA not used"] + #[inline(always)] + pub fn not_used(self) -> &'a mut crate::W { + self.variant(Dmatb::NotUsed) + } + #[doc = "DMA enabled for one frame"] + #[inline(always)] + pub fn enable_one_frame(self) -> &'a mut crate::W { + self.variant(Dmatb::EnableOneFrame) + } + #[doc = "DMA enabled until turned off"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dmatb::Enable) + } +} +#[doc = "Width of DMA Operations\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dmawidth { + #[doc = "0: Byte"] + Byte0 = 0, + #[doc = "1: Byte"] + Byte1 = 1, + #[doc = "2: Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)"] + HalfWord = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dmawidth) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dmawidth { + type Ux = u8; +} +impl crate::IsEnum for Dmawidth {} +#[doc = "Field `DMAWIDTH` reader - Width of DMA Operations"] +pub type DmawidthR = crate::FieldReader; +impl DmawidthR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dmawidth::Byte0), + 1 => Some(Dmawidth::Byte1), + 2 => Some(Dmawidth::HalfWord), + _ => None, + } + } + #[doc = "Byte"] + #[inline(always)] + pub fn is_byte_0(&self) -> bool { + *self == Dmawidth::Byte0 + } + #[doc = "Byte"] + #[inline(always)] + pub fn is_byte_1(&self) -> bool { + *self == Dmawidth::Byte1 + } + #[doc = "Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)"] + #[inline(always)] + pub fn is_half_word(&self) -> bool { + *self == Dmawidth::HalfWord + } +} +#[doc = "Field `DMAWIDTH` writer - Width of DMA Operations"] +pub type DmawidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmawidth>; +impl<'a, REG> DmawidthW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Byte"] + #[inline(always)] + pub fn byte_0(self) -> &'a mut crate::W { + self.variant(Dmawidth::Byte0) + } + #[doc = "Byte"] + #[inline(always)] + pub fn byte_1(self) -> &'a mut crate::W { + self.variant(Dmawidth::Byte1) + } + #[doc = "Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)"] + #[inline(always)] + pub fn half_word(self) -> &'a mut crate::W { + self.variant(Dmawidth::HalfWord) + } +} +impl R { + #[doc = "Bits 0:1 - DMA Read (From-Bus) Trigger"] + #[inline(always)] + pub fn dmafb(&self) -> DmafbR { + DmafbR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - DMA Write (To-Bus) Trigger"] + #[inline(always)] + pub fn dmatb(&self) -> DmatbR { + DmatbR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Width of DMA Operations"] + #[inline(always)] + pub fn dmawidth(&self) -> DmawidthR { + DmawidthR::new(((self.bits >> 4) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - DMA Read (From-Bus) Trigger"] + #[inline(always)] + pub fn dmafb(&mut self) -> DmafbW { + DmafbW::new(self, 0) + } + #[doc = "Bits 2:3 - DMA Write (To-Bus) Trigger"] + #[inline(always)] + pub fn dmatb(&mut self) -> DmatbW { + DmatbW::new(self, 2) + } + #[doc = "Bits 4:5 - Width of DMA Operations"] + #[inline(always)] + pub fn dmawidth(&mut self) -> DmawidthW { + DmawidthW::new(self, 4) + } +} +#[doc = "Target DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdmactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdmactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SdmactrlSpec; +impl crate::RegisterSpec for SdmactrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdmactrl::R`](R) reader structure"] +impl crate::Readable for SdmactrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sdmactrl::W`](W) writer structure"] +impl crate::Writable for SdmactrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SDMACTRL to value 0x10"] +impl crate::Resettable for SdmactrlSpec { + const RESET_VALUE: u32 = 0x10; +} diff --git a/mcxa276-pac/src/i3c0/sdynaddr.rs b/mcxa276-pac/src/i3c0/sdynaddr.rs new file mode 100644 index 000000000..2c82a449b --- /dev/null +++ b/mcxa276-pac/src/i3c0/sdynaddr.rs @@ -0,0 +1,126 @@ +#[doc = "Register `SDYNADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SDYNADDR` writer"] +pub type W = crate::W; +#[doc = "Dynamic Address Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Davalid { + #[doc = "0: DANOTASSIGNED: a dynamic address is not assigned"] + Danotassigned = 0, + #[doc = "1: DAASSIGNED: a dynamic address is assigned"] + Daassigned = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Davalid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAVALID` reader - Dynamic Address Valid"] +pub type DavalidR = crate::BitReader; +impl DavalidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Davalid { + match self.bits { + false => Davalid::Danotassigned, + true => Davalid::Daassigned, + } + } + #[doc = "DANOTASSIGNED: a dynamic address is not assigned"] + #[inline(always)] + pub fn is_danotassigned(&self) -> bool { + *self == Davalid::Danotassigned + } + #[doc = "DAASSIGNED: a dynamic address is assigned"] + #[inline(always)] + pub fn is_daassigned(&self) -> bool { + *self == Davalid::Daassigned + } +} +#[doc = "Field `DAVALID` writer - Dynamic Address Valid"] +pub type DavalidW<'a, REG> = crate::BitWriter<'a, REG, Davalid>; +impl<'a, REG> DavalidW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "DANOTASSIGNED: a dynamic address is not assigned"] + #[inline(always)] + pub fn danotassigned(self) -> &'a mut crate::W { + self.variant(Davalid::Danotassigned) + } + #[doc = "DAASSIGNED: a dynamic address is assigned"] + #[inline(always)] + pub fn daassigned(self) -> &'a mut crate::W { + self.variant(Davalid::Daassigned) + } +} +#[doc = "Field `DADDR` reader - Dynamic Address"] +pub type DaddrR = crate::FieldReader; +#[doc = "Field `DADDR` writer - Dynamic Address"] +pub type DaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `MAPSA` writer - Map a Static Address"] +pub type MapsaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SA10B` writer - 10-Bit Static Address"] +pub type Sa10bW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `KEY` reader - Key"] +pub type KeyR = crate::FieldReader; +#[doc = "Field `KEY` writer - Key"] +pub type KeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Dynamic Address Valid"] + #[inline(always)] + pub fn davalid(&self) -> DavalidR { + DavalidR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:7 - Dynamic Address"] + #[inline(always)] + pub fn daddr(&self) -> DaddrR { + DaddrR::new(((self.bits >> 1) & 0x7f) as u8) + } + #[doc = "Bits 16:31 - Key"] + #[inline(always)] + pub fn key(&self) -> KeyR { + KeyR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Dynamic Address Valid"] + #[inline(always)] + pub fn davalid(&mut self) -> DavalidW { + DavalidW::new(self, 0) + } + #[doc = "Bits 1:7 - Dynamic Address"] + #[inline(always)] + pub fn daddr(&mut self) -> DaddrW { + DaddrW::new(self, 1) + } + #[doc = "Bit 12 - Map a Static Address"] + #[inline(always)] + pub fn mapsa(&mut self) -> MapsaW { + MapsaW::new(self, 12) + } + #[doc = "Bits 13:15 - 10-Bit Static Address"] + #[inline(always)] + pub fn sa10b(&mut self) -> Sa10bW { + Sa10bW::new(self, 13) + } + #[doc = "Bits 16:31 - Key"] + #[inline(always)] + pub fn key(&mut self) -> KeyW { + KeyW::new(self, 16) + } +} +#[doc = "Target Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sdynaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdynaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SdynaddrSpec; +impl crate::RegisterSpec for SdynaddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdynaddr::R`](R) reader structure"] +impl crate::Readable for SdynaddrSpec {} +#[doc = "`write(|w| ..)` method takes [`sdynaddr::W`](W) writer structure"] +impl crate::Writable for SdynaddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SDYNADDR to value 0"] +impl crate::Resettable for SdynaddrSpec {} diff --git a/mcxa276-pac/src/i3c0/serrwarn.rs b/mcxa276-pac/src/i3c0/serrwarn.rs new file mode 100644 index 000000000..811c2a11e --- /dev/null +++ b/mcxa276-pac/src/i3c0/serrwarn.rs @@ -0,0 +1,715 @@ +#[doc = "Register `SERRWARN` reader"] +pub type R = crate::R; +#[doc = "Register `SERRWARN` writer"] +pub type W = crate::W; +#[doc = "Overrun Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Orun { + #[doc = "0: No overrun error"] + NoError = 0, + #[doc = "1: Overrun error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Orun) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ORUN` reader - Overrun Error Flag"] +pub type OrunR = crate::BitReader; +impl OrunR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Orun { + match self.bits { + false => Orun::NoError, + true => Orun::Error, + } + } + #[doc = "No overrun error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Orun::NoError + } + #[doc = "Overrun error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Orun::Error + } +} +#[doc = "Field `ORUN` writer - Overrun Error Flag"] +pub type OrunW<'a, REG> = crate::BitWriter1C<'a, REG, Orun>; +impl<'a, REG> OrunW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overrun error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Orun::NoError) + } + #[doc = "Overrun error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Orun::Error) + } +} +#[doc = "Underrun Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Urun { + #[doc = "0: No underrun error"] + NoError = 0, + #[doc = "1: Underrun error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Urun) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `URUN` reader - Underrun Error Flag"] +pub type UrunR = crate::BitReader; +impl UrunR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Urun { + match self.bits { + false => Urun::NoError, + true => Urun::Error, + } + } + #[doc = "No underrun error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Urun::NoError + } + #[doc = "Underrun error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Urun::Error + } +} +#[doc = "Field `URUN` writer - Underrun Error Flag"] +pub type UrunW<'a, REG> = crate::BitWriter1C<'a, REG, Urun>; +impl<'a, REG> UrunW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No underrun error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Urun::NoError) + } + #[doc = "Underrun error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Urun::Error) + } +} +#[doc = "Underrun and Not Acknowledged (NACKed) Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Urunnack { + #[doc = "0: No underrun; not acknowledged error"] + NoError = 0, + #[doc = "1: Underrun; not acknowledged error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Urunnack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `URUNNACK` reader - Underrun and Not Acknowledged (NACKed) Error Flag"] +pub type UrunnackR = crate::BitReader; +impl UrunnackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Urunnack { + match self.bits { + false => Urunnack::NoError, + true => Urunnack::Error, + } + } + #[doc = "No underrun; not acknowledged error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Urunnack::NoError + } + #[doc = "Underrun; not acknowledged error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Urunnack::Error + } +} +#[doc = "Field `URUNNACK` writer - Underrun and Not Acknowledged (NACKed) Error Flag"] +pub type UrunnackW<'a, REG> = crate::BitWriter1C<'a, REG, Urunnack>; +impl<'a, REG> UrunnackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No underrun; not acknowledged error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Urunnack::NoError) + } + #[doc = "Underrun; not acknowledged error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Urunnack::Error) + } +} +#[doc = "Terminated Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Term { + #[doc = "0: No terminated error"] + NoError = 0, + #[doc = "1: Terminated error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Term) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TERM` reader - Terminated Error Flag"] +pub type TermR = crate::BitReader; +impl TermR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Term { + match self.bits { + false => Term::NoError, + true => Term::Error, + } + } + #[doc = "No terminated error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Term::NoError + } + #[doc = "Terminated error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Term::Error + } +} +#[doc = "Field `TERM` writer - Terminated Error Flag"] +pub type TermW<'a, REG> = crate::BitWriter1C<'a, REG, Term>; +impl<'a, REG> TermW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No terminated error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Term::NoError) + } + #[doc = "Terminated error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Term::Error) + } +} +#[doc = "Invalid Start Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Invstart { + #[doc = "0: No invalid start error"] + NoError = 0, + #[doc = "1: Invalid start error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Invstart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INVSTART` reader - Invalid Start Error Flag"] +pub type InvstartR = crate::BitReader; +impl InvstartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Invstart { + match self.bits { + false => Invstart::NoError, + true => Invstart::Error, + } + } + #[doc = "No invalid start error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Invstart::NoError + } + #[doc = "Invalid start error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Invstart::Error + } +} +#[doc = "Field `INVSTART` writer - Invalid Start Error Flag"] +pub type InvstartW<'a, REG> = crate::BitWriter1C<'a, REG, Invstart>; +impl<'a, REG> InvstartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No invalid start error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Invstart::NoError) + } + #[doc = "Invalid start error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Invstart::Error) + } +} +#[doc = "SDR Parity Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spar { + #[doc = "0: No SDR parity error"] + NoError = 0, + #[doc = "1: SDR parity error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spar) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPAR` reader - SDR Parity Error Flag"] +pub type SparR = crate::BitReader; +impl SparR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spar { + match self.bits { + false => Spar::NoError, + true => Spar::Error, + } + } + #[doc = "No SDR parity error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Spar::NoError + } + #[doc = "SDR parity error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Spar::Error + } +} +#[doc = "Field `SPAR` writer - SDR Parity Error Flag"] +pub type SparW<'a, REG> = crate::BitWriter1C<'a, REG, Spar>; +impl<'a, REG> SparW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No SDR parity error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Spar::NoError) + } + #[doc = "SDR parity error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Spar::Error) + } +} +#[doc = "HDR Parity Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hpar { + #[doc = "0: No HDR parity error"] + NoError = 0, + #[doc = "1: HDR parity error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hpar) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HPAR` reader - HDR Parity Error Flag"] +pub type HparR = crate::BitReader; +impl HparR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hpar { + match self.bits { + false => Hpar::NoError, + true => Hpar::Error, + } + } + #[doc = "No HDR parity error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Hpar::NoError + } + #[doc = "HDR parity error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Hpar::Error + } +} +#[doc = "Field `HPAR` writer - HDR Parity Error Flag"] +pub type HparW<'a, REG> = crate::BitWriter1C<'a, REG, Hpar>; +impl<'a, REG> HparW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No HDR parity error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Hpar::NoError) + } + #[doc = "HDR parity error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Hpar::Error) + } +} +#[doc = "HDR-DDR CRC Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hcrc { + #[doc = "0: No HDR-DDR CRC error occurred"] + NoError = 0, + #[doc = "1: HDR-DDR CRC error occurred"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hcrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HCRC` reader - HDR-DDR CRC Error Flag"] +pub type HcrcR = crate::BitReader; +impl HcrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hcrc { + match self.bits { + false => Hcrc::NoError, + true => Hcrc::Error, + } + } + #[doc = "No HDR-DDR CRC error occurred"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Hcrc::NoError + } + #[doc = "HDR-DDR CRC error occurred"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Hcrc::Error + } +} +#[doc = "Field `HCRC` writer - HDR-DDR CRC Error Flag"] +pub type HcrcW<'a, REG> = crate::BitWriter1C<'a, REG, Hcrc>; +impl<'a, REG> HcrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No HDR-DDR CRC error occurred"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Hcrc::NoError) + } + #[doc = "HDR-DDR CRC error occurred"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Hcrc::Error) + } +} +#[doc = "TE0 or TE1 Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum S0s1 { + #[doc = "0: No TE0 or TE1 error occurred"] + NoError = 0, + #[doc = "1: TE0 or TE1 error occurred"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: S0s1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `S0S1` reader - TE0 or TE1 Error Flag"] +pub type S0s1R = crate::BitReader; +impl S0s1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> S0s1 { + match self.bits { + false => S0s1::NoError, + true => S0s1::Error, + } + } + #[doc = "No TE0 or TE1 error occurred"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == S0s1::NoError + } + #[doc = "TE0 or TE1 error occurred"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == S0s1::Error + } +} +#[doc = "Field `S0S1` writer - TE0 or TE1 Error Flag"] +pub type S0s1W<'a, REG> = crate::BitWriter1C<'a, REG, S0s1>; +impl<'a, REG> S0s1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No TE0 or TE1 error occurred"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(S0s1::NoError) + } + #[doc = "TE0 or TE1 error occurred"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(S0s1::Error) + } +} +#[doc = "Over-Read Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oread { + #[doc = "0: No over-read error"] + NoError = 0, + #[doc = "1: Over-read error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oread) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OREAD` reader - Over-Read Error Flag"] +pub type OreadR = crate::BitReader; +impl OreadR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oread { + match self.bits { + false => Oread::NoError, + true => Oread::Error, + } + } + #[doc = "No over-read error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Oread::NoError + } + #[doc = "Over-read error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Oread::Error + } +} +#[doc = "Field `OREAD` writer - Over-Read Error Flag"] +pub type OreadW<'a, REG> = crate::BitWriter1C<'a, REG, Oread>; +impl<'a, REG> OreadW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No over-read error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Oread::NoError) + } + #[doc = "Over-read error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Oread::Error) + } +} +#[doc = "Over-Write Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Owrite { + #[doc = "0: No overwrite error"] + NoError = 0, + #[doc = "1: Overwrite error"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Owrite) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OWRITE` reader - Over-Write Error Flag"] +pub type OwriteR = crate::BitReader; +impl OwriteR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Owrite { + match self.bits { + false => Owrite::NoError, + true => Owrite::Error, + } + } + #[doc = "No overwrite error"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Owrite::NoError + } + #[doc = "Overwrite error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Owrite::Error + } +} +#[doc = "Field `OWRITE` writer - Over-Write Error Flag"] +pub type OwriteW<'a, REG> = crate::BitWriter1C<'a, REG, Owrite>; +impl<'a, REG> OwriteW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overwrite error"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Owrite::NoError) + } + #[doc = "Overwrite error"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Owrite::Error) + } +} +impl R { + #[doc = "Bit 0 - Overrun Error Flag"] + #[inline(always)] + pub fn orun(&self) -> OrunR { + OrunR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Underrun Error Flag"] + #[inline(always)] + pub fn urun(&self) -> UrunR { + UrunR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Underrun and Not Acknowledged (NACKed) Error Flag"] + #[inline(always)] + pub fn urunnack(&self) -> UrunnackR { + UrunnackR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Terminated Error Flag"] + #[inline(always)] + pub fn term(&self) -> TermR { + TermR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Invalid Start Error Flag"] + #[inline(always)] + pub fn invstart(&self) -> InvstartR { + InvstartR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - SDR Parity Error Flag"] + #[inline(always)] + pub fn spar(&self) -> SparR { + SparR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDR Parity Error Flag"] + #[inline(always)] + pub fn hpar(&self) -> HparR { + HparR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - HDR-DDR CRC Error Flag"] + #[inline(always)] + pub fn hcrc(&self) -> HcrcR { + HcrcR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TE0 or TE1 Error Flag"] + #[inline(always)] + pub fn s0s1(&self) -> S0s1R { + S0s1R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Over-Read Error Flag"] + #[inline(always)] + pub fn oread(&self) -> OreadR { + OreadR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Over-Write Error Flag"] + #[inline(always)] + pub fn owrite(&self) -> OwriteR { + OwriteR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overrun Error Flag"] + #[inline(always)] + pub fn orun(&mut self) -> OrunW { + OrunW::new(self, 0) + } + #[doc = "Bit 1 - Underrun Error Flag"] + #[inline(always)] + pub fn urun(&mut self) -> UrunW { + UrunW::new(self, 1) + } + #[doc = "Bit 2 - Underrun and Not Acknowledged (NACKed) Error Flag"] + #[inline(always)] + pub fn urunnack(&mut self) -> UrunnackW { + UrunnackW::new(self, 2) + } + #[doc = "Bit 3 - Terminated Error Flag"] + #[inline(always)] + pub fn term(&mut self) -> TermW { + TermW::new(self, 3) + } + #[doc = "Bit 4 - Invalid Start Error Flag"] + #[inline(always)] + pub fn invstart(&mut self) -> InvstartW { + InvstartW::new(self, 4) + } + #[doc = "Bit 8 - SDR Parity Error Flag"] + #[inline(always)] + pub fn spar(&mut self) -> SparW { + SparW::new(self, 8) + } + #[doc = "Bit 9 - HDR Parity Error Flag"] + #[inline(always)] + pub fn hpar(&mut self) -> HparW { + HparW::new(self, 9) + } + #[doc = "Bit 10 - HDR-DDR CRC Error Flag"] + #[inline(always)] + pub fn hcrc(&mut self) -> HcrcW { + HcrcW::new(self, 10) + } + #[doc = "Bit 11 - TE0 or TE1 Error Flag"] + #[inline(always)] + pub fn s0s1(&mut self) -> S0s1W { + S0s1W::new(self, 11) + } + #[doc = "Bit 16 - Over-Read Error Flag"] + #[inline(always)] + pub fn oread(&mut self) -> OreadW { + OreadW::new(self, 16) + } + #[doc = "Bit 17 - Over-Write Error Flag"] + #[inline(always)] + pub fn owrite(&mut self) -> OwriteW { + OwriteW::new(self, 17) + } +} +#[doc = "Target Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`serrwarn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serrwarn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SerrwarnSpec; +impl crate::RegisterSpec for SerrwarnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`serrwarn::R`](R) reader structure"] +impl crate::Readable for SerrwarnSpec {} +#[doc = "`write(|w| ..)` method takes [`serrwarn::W`](W) writer structure"] +impl crate::Writable for SerrwarnSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0003_0f1f; +} +#[doc = "`reset()` method sets SERRWARN to value 0"] +impl crate::Resettable for SerrwarnSpec {} diff --git a/mcxa276-pac/src/i3c0/sid.rs b/mcxa276-pac/src/i3c0/sid.rs new file mode 100644 index 000000000..169c84886 --- /dev/null +++ b/mcxa276-pac/src/i3c0/sid.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SID` reader"] +pub type R = crate::R; +#[doc = "Field `ID` reader - ID"] +pub type IdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - ID"] + #[inline(always)] + pub fn id(&self) -> IdR { + IdR::new(self.bits) + } +} +#[doc = "Target Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SidSpec; +impl crate::RegisterSpec for SidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sid::R`](R) reader structure"] +impl crate::Readable for SidSpec {} +#[doc = "`reset()` method sets SID to value 0xedcb_0100"] +impl crate::Resettable for SidSpec { + const RESET_VALUE: u32 = 0xedcb_0100; +} diff --git a/mcxa276-pac/src/i3c0/sidext.rs b/mcxa276-pac/src/i3c0/sidext.rs new file mode 100644 index 000000000..bb25a3385 --- /dev/null +++ b/mcxa276-pac/src/i3c0/sidext.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SIDEXT` reader"] +pub type R = crate::R; +#[doc = "Register `SIDEXT` writer"] +pub type W = crate::W; +#[doc = "Field `DCR` reader - Device Characteristic Register"] +pub type DcrR = crate::FieldReader; +#[doc = "Field `DCR` writer - Device Characteristic Register"] +pub type DcrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BCR` reader - Bus Characteristics Register"] +pub type BcrR = crate::FieldReader; +#[doc = "Field `BCR` writer - Bus Characteristics Register"] +pub type BcrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 8:15 - Device Characteristic Register"] + #[inline(always)] + pub fn dcr(&self) -> DcrR { + DcrR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Bus Characteristics Register"] + #[inline(always)] + pub fn bcr(&self) -> BcrR { + BcrR::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Device Characteristic Register"] + #[inline(always)] + pub fn dcr(&mut self) -> DcrW { + DcrW::new(self, 8) + } + #[doc = "Bits 16:23 - Bus Characteristics Register"] + #[inline(always)] + pub fn bcr(&mut self) -> BcrW { + BcrW::new(self, 16) + } +} +#[doc = "Target ID Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`sidext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SidextSpec; +impl crate::RegisterSpec for SidextSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sidext::R`](R) reader structure"] +impl crate::Readable for SidextSpec {} +#[doc = "`write(|w| ..)` method takes [`sidext::W`](W) writer structure"] +impl crate::Writable for SidextSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SIDEXT to value 0x0066_ef00"] +impl crate::Resettable for SidextSpec { + const RESET_VALUE: u32 = 0x0066_ef00; +} diff --git a/mcxa276-pac/src/i3c0/sidpartno.rs b/mcxa276-pac/src/i3c0/sidpartno.rs new file mode 100644 index 000000000..ce972d60d --- /dev/null +++ b/mcxa276-pac/src/i3c0/sidpartno.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SIDPARTNO` reader"] +pub type R = crate::R; +#[doc = "Register `SIDPARTNO` writer"] +pub type W = crate::W; +#[doc = "Field `PARTNO` reader - Part Number"] +pub type PartnoR = crate::FieldReader; +#[doc = "Field `PARTNO` writer - Part Number"] +pub type PartnoW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Part Number"] + #[inline(always)] + pub fn partno(&self) -> PartnoR { + PartnoR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Part Number"] + #[inline(always)] + pub fn partno(&mut self) -> PartnoW { + PartnoW::new(self, 0) + } +} +#[doc = "Target ID Part Number\n\nYou can [`read`](crate::Reg::read) this register and get [`sidpartno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidpartno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SidpartnoSpec; +impl crate::RegisterSpec for SidpartnoSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sidpartno::R`](R) reader structure"] +impl crate::Readable for SidpartnoSpec {} +#[doc = "`write(|w| ..)` method takes [`sidpartno::W`](W) writer structure"] +impl crate::Writable for SidpartnoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SIDPARTNO to value 0x3000_0000"] +impl crate::Resettable for SidpartnoSpec { + const RESET_VALUE: u32 = 0x3000_0000; +} diff --git a/mcxa276-pac/src/i3c0/sintclr.rs b/mcxa276-pac/src/i3c0/sintclr.rs new file mode 100644 index 000000000..090fce885 --- /dev/null +++ b/mcxa276-pac/src/i3c0/sintclr.rs @@ -0,0 +1,176 @@ +#[doc = "Register `SINTCLR` reader"] +pub type R = crate::R; +#[doc = "Register `SINTCLR` writer"] +pub type W = crate::W; +#[doc = "Field `START` reader - START Interrupt Enable Clear Flag"] +pub type StartR = crate::BitReader; +#[doc = "Field `START` writer - START Interrupt Enable Clear Flag"] +pub type StartW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `MATCHED` reader - Matched Interrupt Enable Clear Flag"] +pub type MatchedR = crate::BitReader; +#[doc = "Field `MATCHED` writer - Matched Interrupt Enable Clear Flag"] +pub type MatchedW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `STOP` reader - STOP Interrupt Enable Clear Flag"] +pub type StopR = crate::BitReader; +#[doc = "Field `STOP` writer - STOP Interrupt Enable Clear Flag"] +pub type StopW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXPEND` reader - RXPEND Interrupt Enable Clear Flag"] +pub type RxpendR = crate::BitReader; +#[doc = "Field `RXPEND` writer - RXPEND Interrupt Enable Clear Flag"] +pub type RxpendW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TXSEND` reader - TXSEND Interrupt Enable Clear Flag"] +pub type TxsendR = crate::BitReader; +#[doc = "Field `TXSEND` writer - TXSEND Interrupt Enable Clear Flag"] +pub type TxsendW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DACHG` reader - DACHG Interrupt Enable Clear Flag"] +pub type DachgR = crate::BitReader; +#[doc = "Field `DACHG` writer - DACHG Interrupt Enable Clear Flag"] +pub type DachgW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CCC` reader - CCC Interrupt Enable Clear Flag"] +pub type CccR = crate::BitReader; +#[doc = "Field `CCC` writer - CCC Interrupt Enable Clear Flag"] +pub type CccW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Enable Clear Flag"] +pub type ErrwarnR = crate::BitReader; +#[doc = "Field `ERRWARN` writer - ERRWARN Interrupt Enable Clear Flag"] +pub type ErrwarnW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DDRMATCHED` reader - DDRMATCHED Interrupt Enable Clear Flag"] +pub type DdrmatchedR = crate::BitReader; +#[doc = "Field `DDRMATCHED` writer - DDRMATCHED Interrupt Enable Clear Flag"] +pub type DdrmatchedW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CHANDLED` reader - CHANDLED Interrupt Enable Clear Flag"] +pub type ChandledR = crate::BitReader; +#[doc = "Field `CHANDLED` writer - CHANDLED Interrupt Enable Clear Flag"] +pub type ChandledW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EVENT` reader - EVENT Interrupt Enable Clear Flag"] +pub type EventR = crate::BitReader; +#[doc = "Field `EVENT` writer - EVENT Interrupt Enable Clear Flag"] +pub type EventW<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 8 - START Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Matched Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn matched(&self) -> MatchedR { + MatchedR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - STOP Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn stop(&self) -> StopR { + StopR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn rxpend(&self) -> RxpendR { + RxpendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TXSEND Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn txsend(&self) -> TxsendR { + TxsendR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - DACHG Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn dachg(&self) -> DachgR { + DachgR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - CCC Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn ccc(&self) -> CccR { + CccR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DDRMATCHED Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn ddrmatched(&self) -> DdrmatchedR { + DdrmatchedR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - CHANDLED Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn chandled(&self) -> ChandledR { + ChandledR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - EVENT Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn event(&self) -> EventR { + EventR::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - START Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn start(&mut self) -> StartW { + StartW::new(self, 8) + } + #[doc = "Bit 9 - Matched Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn matched(&mut self) -> MatchedW { + MatchedW::new(self, 9) + } + #[doc = "Bit 10 - STOP Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn stop(&mut self) -> StopW { + StopW::new(self, 10) + } + #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn rxpend(&mut self) -> RxpendW { + RxpendW::new(self, 11) + } + #[doc = "Bit 12 - TXSEND Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn txsend(&mut self) -> TxsendW { + TxsendW::new(self, 12) + } + #[doc = "Bit 13 - DACHG Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn dachg(&mut self) -> DachgW { + DachgW::new(self, 13) + } + #[doc = "Bit 14 - CCC Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn ccc(&mut self) -> CccW { + CccW::new(self, 14) + } + #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn errwarn(&mut self) -> ErrwarnW { + ErrwarnW::new(self, 15) + } + #[doc = "Bit 16 - DDRMATCHED Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn ddrmatched(&mut self) -> DdrmatchedW { + DdrmatchedW::new(self, 16) + } + #[doc = "Bit 17 - CHANDLED Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn chandled(&mut self) -> ChandledW { + ChandledW::new(self, 17) + } + #[doc = "Bit 18 - EVENT Interrupt Enable Clear Flag"] + #[inline(always)] + pub fn event(&mut self) -> EventW { + EventW::new(self, 18) + } +} +#[doc = "Target Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sintclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SintclrSpec; +impl crate::RegisterSpec for SintclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sintclr::R`](R) reader structure"] +impl crate::Readable for SintclrSpec {} +#[doc = "`write(|w| ..)` method takes [`sintclr::W`](W) writer structure"] +impl crate::Writable for SintclrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ff00; +} +#[doc = "`reset()` method sets SINTCLR to value 0"] +impl crate::Resettable for SintclrSpec {} diff --git a/mcxa276-pac/src/i3c0/sintmasked.rs b/mcxa276-pac/src/i3c0/sintmasked.rs new file mode 100644 index 000000000..dce9621a3 --- /dev/null +++ b/mcxa276-pac/src/i3c0/sintmasked.rs @@ -0,0 +1,90 @@ +#[doc = "Register `SINTMASKED` reader"] +pub type R = crate::R; +#[doc = "Field `START` reader - START Interrupt Mask"] +pub type StartR = crate::BitReader; +#[doc = "Field `MATCHED` reader - MATCHED Interrupt Mask"] +pub type MatchedR = crate::BitReader; +#[doc = "Field `STOP` reader - STOP Interrupt Mask"] +pub type StopR = crate::BitReader; +#[doc = "Field `RXPEND` reader - RXPEND Interrupt Mask"] +pub type RxpendR = crate::BitReader; +#[doc = "Field `TXSEND` reader - TXSEND Interrupt Mask"] +pub type TxsendR = crate::BitReader; +#[doc = "Field `DACHG` reader - DACHG Interrupt Mask"] +pub type DachgR = crate::BitReader; +#[doc = "Field `CCC` reader - CCC Interrupt Mask"] +pub type CccR = crate::BitReader; +#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Mask"] +pub type ErrwarnR = crate::BitReader; +#[doc = "Field `DDRMATCHED` reader - DDRMATCHED Interrupt Mask"] +pub type DdrmatchedR = crate::BitReader; +#[doc = "Field `CHANDLED` reader - CHANDLED Interrupt Mask"] +pub type ChandledR = crate::BitReader; +#[doc = "Field `EVENT` reader - EVENT Interrupt Mask"] +pub type EventR = crate::BitReader; +impl R { + #[doc = "Bit 8 - START Interrupt Mask"] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MATCHED Interrupt Mask"] + #[inline(always)] + pub fn matched(&self) -> MatchedR { + MatchedR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - STOP Interrupt Mask"] + #[inline(always)] + pub fn stop(&self) -> StopR { + StopR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RXPEND Interrupt Mask"] + #[inline(always)] + pub fn rxpend(&self) -> RxpendR { + RxpendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TXSEND Interrupt Mask"] + #[inline(always)] + pub fn txsend(&self) -> TxsendR { + TxsendR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - DACHG Interrupt Mask"] + #[inline(always)] + pub fn dachg(&self) -> DachgR { + DachgR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - CCC Interrupt Mask"] + #[inline(always)] + pub fn ccc(&self) -> CccR { + CccR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - ERRWARN Interrupt Mask"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DDRMATCHED Interrupt Mask"] + #[inline(always)] + pub fn ddrmatched(&self) -> DdrmatchedR { + DdrmatchedR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - CHANDLED Interrupt Mask"] + #[inline(always)] + pub fn chandled(&self) -> ChandledR { + ChandledR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - EVENT Interrupt Mask"] + #[inline(always)] + pub fn event(&self) -> EventR { + EventR::new(((self.bits >> 18) & 1) != 0) + } +} +#[doc = "Target Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`sintmasked::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SintmaskedSpec; +impl crate::RegisterSpec for SintmaskedSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sintmasked::R`](R) reader structure"] +impl crate::Readable for SintmaskedSpec {} +#[doc = "`reset()` method sets SINTMASKED to value 0"] +impl crate::Resettable for SintmaskedSpec {} diff --git a/mcxa276-pac/src/i3c0/sintset.rs b/mcxa276-pac/src/i3c0/sintset.rs new file mode 100644 index 000000000..766634744 --- /dev/null +++ b/mcxa276-pac/src/i3c0/sintset.rs @@ -0,0 +1,715 @@ +#[doc = "Register `SINTSET` reader"] +pub type R = crate::R; +#[doc = "Register `SINTSET` writer"] +pub type W = crate::W; +#[doc = "Start Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Start { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Start) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `START` reader - Start Interrupt Enable"] +pub type StartR = crate::BitReader; +impl StartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Start { + match self.bits { + false => Start::Disable, + true => Start::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Start::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Start::Enable + } +} +#[doc = "Field `START` writer - Start Interrupt Enable"] +pub type StartW<'a, REG> = crate::BitWriter1S<'a, REG, Start>; +impl<'a, REG> StartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Start::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Start::Enable) + } +} +#[doc = "Match Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Matched { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Matched) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MATCHED` reader - Match Interrupt Enable"] +pub type MatchedR = crate::BitReader; +impl MatchedR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Matched { + match self.bits { + false => Matched::Disable, + true => Matched::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Matched::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Matched::Enable + } +} +#[doc = "Field `MATCHED` writer - Match Interrupt Enable"] +pub type MatchedW<'a, REG> = crate::BitWriter1S<'a, REG, Matched>; +impl<'a, REG> MatchedW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Matched::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Matched::Enable) + } +} +#[doc = "Stop Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stop { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stop) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOP` reader - Stop Interrupt Enable"] +pub type StopR = crate::BitReader; +impl StopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stop { + match self.bits { + false => Stop::Disable, + true => Stop::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Stop::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Stop::Enable + } +} +#[doc = "Field `STOP` writer - Stop Interrupt Enable"] +pub type StopW<'a, REG> = crate::BitWriter1S<'a, REG, Stop>; +impl<'a, REG> StopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Stop::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Stop::Enable) + } +} +#[doc = "Receive Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxpend { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxpend) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXPEND` reader - Receive Interrupt Enable"] +pub type RxpendR = crate::BitReader; +impl RxpendR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxpend { + match self.bits { + false => Rxpend::Disable, + true => Rxpend::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rxpend::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rxpend::Enable + } +} +#[doc = "Field `RXPEND` writer - Receive Interrupt Enable"] +pub type RxpendW<'a, REG> = crate::BitWriter1S<'a, REG, Rxpend>; +impl<'a, REG> RxpendW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Rxpend::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Rxpend::Enable) + } +} +#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txsend { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txsend) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXSEND` reader - Transmit Interrupt Enable"] +pub type TxsendR = crate::BitReader; +impl TxsendR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txsend { + match self.bits { + false => Txsend::Disable, + true => Txsend::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Txsend::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Txsend::Enable + } +} +#[doc = "Field `TXSEND` writer - Transmit Interrupt Enable"] +pub type TxsendW<'a, REG> = crate::BitWriter1S<'a, REG, Txsend>; +impl<'a, REG> TxsendW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Txsend::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Txsend::Enable) + } +} +#[doc = "Dynamic Address Change Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dachg { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dachg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DACHG` reader - Dynamic Address Change Interrupt Enable"] +pub type DachgR = crate::BitReader; +impl DachgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dachg { + match self.bits { + false => Dachg::Disable, + true => Dachg::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Dachg::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dachg::Enable + } +} +#[doc = "Field `DACHG` writer - Dynamic Address Change Interrupt Enable"] +pub type DachgW<'a, REG> = crate::BitWriter1S<'a, REG, Dachg>; +impl<'a, REG> DachgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Dachg::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dachg::Enable) + } +} +#[doc = "Common Command Code (CCC) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ccc { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ccc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CCC` reader - Common Command Code (CCC) Interrupt Enable"] +pub type CccR = crate::BitReader; +impl CccR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ccc { + match self.bits { + false => Ccc::Disable, + true => Ccc::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ccc::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ccc::Enable + } +} +#[doc = "Field `CCC` writer - Common Command Code (CCC) Interrupt Enable"] +pub type CccW<'a, REG> = crate::BitWriter1S<'a, REG, Ccc>; +impl<'a, REG> CccW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ccc::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ccc::Enable) + } +} +#[doc = "Error or Warning Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Errwarn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Errwarn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERRWARN` reader - Error or Warning Interrupt Enable"] +pub type ErrwarnR = crate::BitReader; +impl ErrwarnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Errwarn { + match self.bits { + false => Errwarn::Disable, + true => Errwarn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Errwarn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Errwarn::Enable + } +} +#[doc = "Field `ERRWARN` writer - Error or Warning Interrupt Enable"] +pub type ErrwarnW<'a, REG> = crate::BitWriter1S<'a, REG, Errwarn>; +impl<'a, REG> ErrwarnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Errwarn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Errwarn::Enable) + } +} +#[doc = "Double Data Rate Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ddrmatched { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ddrmatched) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DDRMATCHED` reader - Double Data Rate Interrupt Enable"] +pub type DdrmatchedR = crate::BitReader; +impl DdrmatchedR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ddrmatched { + match self.bits { + false => Ddrmatched::Disable, + true => Ddrmatched::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ddrmatched::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ddrmatched::Enable + } +} +#[doc = "Field `DDRMATCHED` writer - Double Data Rate Interrupt Enable"] +pub type DdrmatchedW<'a, REG> = crate::BitWriter1S<'a, REG, Ddrmatched>; +impl<'a, REG> DdrmatchedW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ddrmatched::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ddrmatched::Enable) + } +} +#[doc = "Common Command Code (CCC) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Chandled { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Chandled) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CHANDLED` reader - Common Command Code (CCC) Interrupt Enable"] +pub type ChandledR = crate::BitReader; +impl ChandledR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Chandled { + match self.bits { + false => Chandled::Disable, + true => Chandled::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Chandled::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Chandled::Enable + } +} +#[doc = "Field `CHANDLED` writer - Common Command Code (CCC) Interrupt Enable"] +pub type ChandledW<'a, REG> = crate::BitWriter1S<'a, REG, Chandled>; +impl<'a, REG> ChandledW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Chandled::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Chandled::Enable) + } +} +#[doc = "Event Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Event { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Event) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EVENT` reader - Event Interrupt Enable"] +pub type EventR = crate::BitReader; +impl EventR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Event { + match self.bits { + false => Event::Disable, + true => Event::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Event::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Event::Enable + } +} +#[doc = "Field `EVENT` writer - Event Interrupt Enable"] +pub type EventW<'a, REG> = crate::BitWriter1S<'a, REG, Event>; +impl<'a, REG> EventW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Event::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Event::Enable) + } +} +impl R { + #[doc = "Bit 8 - Start Interrupt Enable"] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Match Interrupt Enable"] + #[inline(always)] + pub fn matched(&self) -> MatchedR { + MatchedR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Stop Interrupt Enable"] + #[inline(always)] + pub fn stop(&self) -> StopR { + StopR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Receive Interrupt Enable"] + #[inline(always)] + pub fn rxpend(&self) -> RxpendR { + RxpendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn txsend(&self) -> TxsendR { + TxsendR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Dynamic Address Change Interrupt Enable"] + #[inline(always)] + pub fn dachg(&self) -> DachgR { + DachgR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Common Command Code (CCC) Interrupt Enable"] + #[inline(always)] + pub fn ccc(&self) -> CccR { + CccR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Error or Warning Interrupt Enable"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Double Data Rate Interrupt Enable"] + #[inline(always)] + pub fn ddrmatched(&self) -> DdrmatchedR { + DdrmatchedR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Common Command Code (CCC) Interrupt Enable"] + #[inline(always)] + pub fn chandled(&self) -> ChandledR { + ChandledR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event Interrupt Enable"] + #[inline(always)] + pub fn event(&self) -> EventR { + EventR::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Start Interrupt Enable"] + #[inline(always)] + pub fn start(&mut self) -> StartW { + StartW::new(self, 8) + } + #[doc = "Bit 9 - Match Interrupt Enable"] + #[inline(always)] + pub fn matched(&mut self) -> MatchedW { + MatchedW::new(self, 9) + } + #[doc = "Bit 10 - Stop Interrupt Enable"] + #[inline(always)] + pub fn stop(&mut self) -> StopW { + StopW::new(self, 10) + } + #[doc = "Bit 11 - Receive Interrupt Enable"] + #[inline(always)] + pub fn rxpend(&mut self) -> RxpendW { + RxpendW::new(self, 11) + } + #[doc = "Bit 12 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn txsend(&mut self) -> TxsendW { + TxsendW::new(self, 12) + } + #[doc = "Bit 13 - Dynamic Address Change Interrupt Enable"] + #[inline(always)] + pub fn dachg(&mut self) -> DachgW { + DachgW::new(self, 13) + } + #[doc = "Bit 14 - Common Command Code (CCC) Interrupt Enable"] + #[inline(always)] + pub fn ccc(&mut self) -> CccW { + CccW::new(self, 14) + } + #[doc = "Bit 15 - Error or Warning Interrupt Enable"] + #[inline(always)] + pub fn errwarn(&mut self) -> ErrwarnW { + ErrwarnW::new(self, 15) + } + #[doc = "Bit 16 - Double Data Rate Interrupt Enable"] + #[inline(always)] + pub fn ddrmatched(&mut self) -> DdrmatchedW { + DdrmatchedW::new(self, 16) + } + #[doc = "Bit 17 - Common Command Code (CCC) Interrupt Enable"] + #[inline(always)] + pub fn chandled(&mut self) -> ChandledW { + ChandledW::new(self, 17) + } + #[doc = "Bit 18 - Event Interrupt Enable"] + #[inline(always)] + pub fn event(&mut self) -> EventW { + EventW::new(self, 18) + } +} +#[doc = "Target Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`sintset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SintsetSpec; +impl crate::RegisterSpec for SintsetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sintset::R`](R) reader structure"] +impl crate::Readable for SintsetSpec {} +#[doc = "`write(|w| ..)` method takes [`sintset::W`](W) writer structure"] +impl crate::Writable for SintsetSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ff00; +} +#[doc = "`reset()` method sets SINTSET to value 0"] +impl crate::Resettable for SintsetSpec {} diff --git a/mcxa276-pac/src/i3c0/smapctrl0.rs b/mcxa276-pac/src/i3c0/smapctrl0.rs new file mode 100644 index 000000000..7d1bad73b --- /dev/null +++ b/mcxa276-pac/src/i3c0/smapctrl0.rs @@ -0,0 +1,132 @@ +#[doc = "Register `SMAPCTRL0` reader"] +pub type R = crate::R; +#[doc = "Enable Primary Dynamic Address\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ena { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENA` reader - Enable Primary Dynamic Address"] +pub type EnaR = crate::BitReader; +impl EnaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ena { + match self.bits { + false => Ena::Disable, + true => Ena::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ena::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ena::Enable + } +} +#[doc = "Field `DA` reader - Dynamic Address"] +pub type DaR = crate::FieldReader; +#[doc = "Cause\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cause { + #[doc = "0: No information (this value occurs when not configured to write DA)"] + None = 0, + #[doc = "1: Set using ENTDAA"] + Entdaa = 1, + #[doc = "2: Set using SETDASA, SETAASA, or SETNEWDA"] + Setdasa = 2, + #[doc = "3: Cleared using RSTDAA"] + Rstdaa = 3, + #[doc = "4: Auto MAP change happened last"] + Automap = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cause) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cause { + type Ux = u8; +} +impl crate::IsEnum for Cause {} +#[doc = "Field `CAUSE` reader - Cause"] +pub type CauseR = crate::FieldReader; +impl CauseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cause::None), + 1 => Some(Cause::Entdaa), + 2 => Some(Cause::Setdasa), + 3 => Some(Cause::Rstdaa), + 4 => Some(Cause::Automap), + _ => None, + } + } + #[doc = "No information (this value occurs when not configured to write DA)"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Cause::None + } + #[doc = "Set using ENTDAA"] + #[inline(always)] + pub fn is_entdaa(&self) -> bool { + *self == Cause::Entdaa + } + #[doc = "Set using SETDASA, SETAASA, or SETNEWDA"] + #[inline(always)] + pub fn is_setdasa(&self) -> bool { + *self == Cause::Setdasa + } + #[doc = "Cleared using RSTDAA"] + #[inline(always)] + pub fn is_rstdaa(&self) -> bool { + *self == Cause::Rstdaa + } + #[doc = "Auto MAP change happened last"] + #[inline(always)] + pub fn is_automap(&self) -> bool { + *self == Cause::Automap + } +} +impl R { + #[doc = "Bit 0 - Enable Primary Dynamic Address"] + #[inline(always)] + pub fn ena(&self) -> EnaR { + EnaR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:7 - Dynamic Address"] + #[inline(always)] + pub fn da(&self) -> DaR { + DaR::new(((self.bits >> 1) & 0x7f) as u8) + } + #[doc = "Bits 8:10 - Cause"] + #[inline(always)] + pub fn cause(&self) -> CauseR { + CauseR::new(((self.bits >> 8) & 7) as u8) + } +} +#[doc = "Map Feature Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`smapctrl0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Smapctrl0Spec; +impl crate::RegisterSpec for Smapctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`smapctrl0::R`](R) reader structure"] +impl crate::Readable for Smapctrl0Spec {} +#[doc = "`reset()` method sets SMAPCTRL0 to value 0"] +impl crate::Resettable for Smapctrl0Spec {} diff --git a/mcxa276-pac/src/i3c0/smaxlimits.rs b/mcxa276-pac/src/i3c0/smaxlimits.rs new file mode 100644 index 000000000..646940296 --- /dev/null +++ b/mcxa276-pac/src/i3c0/smaxlimits.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SMAXLIMITS` reader"] +pub type R = crate::R; +#[doc = "Register `SMAXLIMITS` writer"] +pub type W = crate::W; +#[doc = "Field `MAXRD` reader - Maximum Read Length"] +pub type MaxrdR = crate::FieldReader; +#[doc = "Field `MAXRD` writer - Maximum Read Length"] +pub type MaxrdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `MAXWR` reader - Maximum Write Length"] +pub type MaxwrR = crate::FieldReader; +#[doc = "Field `MAXWR` writer - Maximum Write Length"] +pub type MaxwrW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - Maximum Read Length"] + #[inline(always)] + pub fn maxrd(&self) -> MaxrdR { + MaxrdR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - Maximum Write Length"] + #[inline(always)] + pub fn maxwr(&self) -> MaxwrR { + MaxwrR::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Maximum Read Length"] + #[inline(always)] + pub fn maxrd(&mut self) -> MaxrdW { + MaxrdW::new(self, 0) + } + #[doc = "Bits 16:27 - Maximum Write Length"] + #[inline(always)] + pub fn maxwr(&mut self) -> MaxwrW { + MaxwrW::new(self, 16) + } +} +#[doc = "Target Maximum Limits\n\nYou can [`read`](crate::Reg::read) this register and get [`smaxlimits::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smaxlimits::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SmaxlimitsSpec; +impl crate::RegisterSpec for SmaxlimitsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`smaxlimits::R`](R) reader structure"] +impl crate::Readable for SmaxlimitsSpec {} +#[doc = "`write(|w| ..)` method takes [`smaxlimits::W`](W) writer structure"] +impl crate::Writable for SmaxlimitsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SMAXLIMITS to value 0"] +impl crate::Resettable for SmaxlimitsSpec {} diff --git a/mcxa276-pac/src/i3c0/smsgmapaddr.rs b/mcxa276-pac/src/i3c0/smsgmapaddr.rs new file mode 100644 index 000000000..c853cd7e3 --- /dev/null +++ b/mcxa276-pac/src/i3c0/smsgmapaddr.rs @@ -0,0 +1,75 @@ +#[doc = "Register `SMSGMAPADDR` reader"] +pub type R = crate::R; +#[doc = "Field `MAPLAST` reader - Matched Address Index"] +pub type MaplastR = crate::FieldReader; +#[doc = "Last Static Address Matched\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Laststatic { + #[doc = "0: I3C dynamic address"] + I3c = 0, + #[doc = "1: I2C static address"] + I2c = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Laststatic) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LASTSTATIC` reader - Last Static Address Matched"] +pub type LaststaticR = crate::BitReader; +impl LaststaticR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Laststatic { + match self.bits { + false => Laststatic::I3c, + true => Laststatic::I2c, + } + } + #[doc = "I3C dynamic address"] + #[inline(always)] + pub fn is_i3c(&self) -> bool { + *self == Laststatic::I3c + } + #[doc = "I2C static address"] + #[inline(always)] + pub fn is_i2c(&self) -> bool { + *self == Laststatic::I2c + } +} +#[doc = "Field `MAPLASTM1` reader - Matched Previous Address Index 1"] +pub type Maplastm1R = crate::FieldReader; +#[doc = "Field `MAPLASTM2` reader - Matched Previous Index 2"] +pub type Maplastm2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Matched Address Index"] + #[inline(always)] + pub fn maplast(&self) -> MaplastR { + MaplastR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - Last Static Address Matched"] + #[inline(always)] + pub fn laststatic(&self) -> LaststaticR { + LaststaticR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:11 - Matched Previous Address Index 1"] + #[inline(always)] + pub fn maplastm1(&self) -> Maplastm1R { + Maplastm1R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Matched Previous Index 2"] + #[inline(always)] + pub fn maplastm2(&self) -> Maplastm2R { + Maplastm2R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +#[doc = "Target Message Map Address\n\nYou can [`read`](crate::Reg::read) this register and get [`smsgmapaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SmsgmapaddrSpec; +impl crate::RegisterSpec for SmsgmapaddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`smsgmapaddr::R`](R) reader structure"] +impl crate::Readable for SmsgmapaddrSpec {} +#[doc = "`reset()` method sets SMSGMAPADDR to value 0"] +impl crate::Resettable for SmsgmapaddrSpec {} diff --git a/mcxa276-pac/src/i3c0/srdatab.rs b/mcxa276-pac/src/i3c0/srdatab.rs new file mode 100644 index 000000000..1d3b85a8d --- /dev/null +++ b/mcxa276-pac/src/i3c0/srdatab.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SRDATAB` reader"] +pub type R = crate::R; +#[doc = "Field `DATA0` reader - Data 0"] +pub type Data0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Data 0"] + #[inline(always)] + pub fn data0(&self) -> Data0R { + Data0R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Target Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatab::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrdatabSpec; +impl crate::RegisterSpec for SrdatabSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`srdatab::R`](R) reader structure"] +impl crate::Readable for SrdatabSpec {} +#[doc = "`reset()` method sets SRDATAB to value 0"] +impl crate::Resettable for SrdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/srdatah.rs b/mcxa276-pac/src/i3c0/srdatah.rs new file mode 100644 index 000000000..e25167f76 --- /dev/null +++ b/mcxa276-pac/src/i3c0/srdatah.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SRDATAH` reader"] +pub type R = crate::R; +#[doc = "Field `LSB` reader - Low Byte"] +pub type LsbR = crate::FieldReader; +#[doc = "Field `MSB` reader - High Byte"] +pub type MsbR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Low Byte"] + #[inline(always)] + pub fn lsb(&self) -> LsbR { + LsbR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - High Byte"] + #[inline(always)] + pub fn msb(&self) -> MsbR { + MsbR::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[doc = "Target Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatah::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrdatahSpec; +impl crate::RegisterSpec for SrdatahSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`srdatah::R`](R) reader structure"] +impl crate::Readable for SrdatahSpec {} +#[doc = "`reset()` method sets SRDATAH to value 0"] +impl crate::Resettable for SrdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/sstatus.rs b/mcxa276-pac/src/i3c0/sstatus.rs new file mode 100644 index 000000000..d02f9d08a --- /dev/null +++ b/mcxa276-pac/src/i3c0/sstatus.rs @@ -0,0 +1,1216 @@ +#[doc = "Register `SSTATUS` reader"] +pub type R = crate::R; +#[doc = "Register `SSTATUS` writer"] +pub type W = crate::W; +#[doc = "Status not Stop\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stnotstop { + #[doc = "0: In STOP condition"] + Stopped = 0, + #[doc = "1: Busy"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stnotstop) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STNOTSTOP` reader - Status not Stop"] +pub type StnotstopR = crate::BitReader; +impl StnotstopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stnotstop { + match self.bits { + false => Stnotstop::Stopped, + true => Stnotstop::Busy, + } + } + #[doc = "In STOP condition"] + #[inline(always)] + pub fn is_stopped(&self) -> bool { + *self == Stnotstop::Stopped + } + #[doc = "Busy"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Stnotstop::Busy + } +} +#[doc = "Status Message\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stmsg { + #[doc = "0: Idle"] + Idle = 0, + #[doc = "1: Busy"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stmsg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STMSG` reader - Status Message"] +pub type StmsgR = crate::BitReader; +impl StmsgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stmsg { + match self.bits { + false => Stmsg::Idle, + true => Stmsg::Busy, + } + } + #[doc = "Idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Stmsg::Idle + } + #[doc = "Busy"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Stmsg::Busy + } +} +#[doc = "Status Common Command Code Handler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stccch { + #[doc = "0: No CCC message handled"] + Idle = 0, + #[doc = "1: Handled automatically"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stccch) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STCCCH` reader - Status Common Command Code Handler"] +pub type StccchR = crate::BitReader; +impl StccchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stccch { + match self.bits { + false => Stccch::Idle, + true => Stccch::Busy, + } + } + #[doc = "No CCC message handled"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Stccch::Idle + } + #[doc = "Handled automatically"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Stccch::Busy + } +} +#[doc = "Status Request Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Streqrd { + #[doc = "0: Not an SDR read"] + Idle = 0, + #[doc = "1: SDR read from this target or an IBI is being pushed out"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Streqrd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STREQRD` reader - Status Request Read"] +pub type StreqrdR = crate::BitReader; +impl StreqrdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Streqrd { + match self.bits { + false => Streqrd::Idle, + true => Streqrd::Busy, + } + } + #[doc = "Not an SDR read"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Streqrd::Idle + } + #[doc = "SDR read from this target or an IBI is being pushed out"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Streqrd::Busy + } +} +#[doc = "Status Request Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Streqwr { + #[doc = "0: Not an SDR write"] + Idle = 0, + #[doc = "1: SDR write data from the controller, but not in ENTDAA mode"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Streqwr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STREQWR` reader - Status Request Write"] +pub type StreqwrR = crate::BitReader; +impl StreqwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Streqwr { + match self.bits { + false => Streqwr::Idle, + true => Streqwr::Busy, + } + } + #[doc = "Not an SDR write"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Streqwr::Idle + } + #[doc = "SDR write data from the controller, but not in ENTDAA mode"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Streqwr::Busy + } +} +#[doc = "Status Dynamic Address Assignment\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stdaa { + #[doc = "0: Not in ENTDAA mode"] + NotInEntdaa = 0, + #[doc = "1: In ENTDAA mode"] + InEntdaa = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stdaa) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STDAA` reader - Status Dynamic Address Assignment"] +pub type StdaaR = crate::BitReader; +impl StdaaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stdaa { + match self.bits { + false => Stdaa::NotInEntdaa, + true => Stdaa::InEntdaa, + } + } + #[doc = "Not in ENTDAA mode"] + #[inline(always)] + pub fn is_not_in_entdaa(&self) -> bool { + *self == Stdaa::NotInEntdaa + } + #[doc = "In ENTDAA mode"] + #[inline(always)] + pub fn is_in_entdaa(&self) -> bool { + *self == Stdaa::InEntdaa + } +} +#[doc = "Status High Data Rate\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sthdr { + #[doc = "0: I3C bus not in HDR-DDR mode"] + NotInHdrDdr = 0, + #[doc = "1: I3C bus in HDR-DDR mode"] + InHdrDdr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sthdr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STHDR` reader - Status High Data Rate"] +pub type SthdrR = crate::BitReader; +impl SthdrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sthdr { + match self.bits { + false => Sthdr::NotInHdrDdr, + true => Sthdr::InHdrDdr, + } + } + #[doc = "I3C bus not in HDR-DDR mode"] + #[inline(always)] + pub fn is_not_in_hdr_ddr(&self) -> bool { + *self == Sthdr::NotInHdrDdr + } + #[doc = "I3C bus in HDR-DDR mode"] + #[inline(always)] + pub fn is_in_hdr_ddr(&self) -> bool { + *self == Sthdr::InHdrDdr + } +} +#[doc = "Start Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Start { + #[doc = "0: Not detected"] + StartNotDetected = 0, + #[doc = "1: Detected"] + StartDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Start) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `START` reader - Start Flag"] +pub type StartR = crate::BitReader; +impl StartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Start { + match self.bits { + false => Start::StartNotDetected, + true => Start::StartDetected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_start_not_detected(&self) -> bool { + *self == Start::StartNotDetected + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_start_detected(&self) -> bool { + *self == Start::StartDetected + } +} +#[doc = "Field `START` writer - Start Flag"] +pub type StartW<'a, REG> = crate::BitWriter1C<'a, REG, Start>; +impl<'a, REG> StartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn start_not_detected(self) -> &'a mut crate::W { + self.variant(Start::StartNotDetected) + } + #[doc = "Detected"] + #[inline(always)] + pub fn start_detected(self) -> &'a mut crate::W { + self.variant(Start::StartDetected) + } +} +#[doc = "Matched Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Matched { + #[doc = "0: Header not matched"] + NotMatched = 0, + #[doc = "1: Header matched"] + Matched = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Matched) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MATCHED` reader - Matched Flag"] +pub type MatchedR = crate::BitReader; +impl MatchedR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Matched { + match self.bits { + false => Matched::NotMatched, + true => Matched::Matched, + } + } + #[doc = "Header not matched"] + #[inline(always)] + pub fn is_not_matched(&self) -> bool { + *self == Matched::NotMatched + } + #[doc = "Header matched"] + #[inline(always)] + pub fn is_matched(&self) -> bool { + *self == Matched::Matched + } +} +#[doc = "Field `MATCHED` writer - Matched Flag"] +pub type MatchedW<'a, REG> = crate::BitWriter1C<'a, REG, Matched>; +impl<'a, REG> MatchedW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Header not matched"] + #[inline(always)] + pub fn not_matched(self) -> &'a mut crate::W { + self.variant(Matched::NotMatched) + } + #[doc = "Header matched"] + #[inline(always)] + pub fn matched(self) -> &'a mut crate::W { + self.variant(Matched::Matched) + } +} +#[doc = "Stop Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stop { + #[doc = "0: No Stopped state detected"] + NoStopDetected = 0, + #[doc = "1: Stopped state detected"] + StopDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stop) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOP` reader - Stop Flag"] +pub type StopR = crate::BitReader; +impl StopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stop { + match self.bits { + false => Stop::NoStopDetected, + true => Stop::StopDetected, + } + } + #[doc = "No Stopped state detected"] + #[inline(always)] + pub fn is_no_stop_detected(&self) -> bool { + *self == Stop::NoStopDetected + } + #[doc = "Stopped state detected"] + #[inline(always)] + pub fn is_stop_detected(&self) -> bool { + *self == Stop::StopDetected + } +} +#[doc = "Field `STOP` writer - Stop Flag"] +pub type StopW<'a, REG> = crate::BitWriter1C<'a, REG, Stop>; +impl<'a, REG> StopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No Stopped state detected"] + #[inline(always)] + pub fn no_stop_detected(self) -> &'a mut crate::W { + self.variant(Stop::NoStopDetected) + } + #[doc = "Stopped state detected"] + #[inline(always)] + pub fn stop_detected(self) -> &'a mut crate::W { + self.variant(Stop::StopDetected) + } +} +#[doc = "Received Message Pending\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RxPend { + #[doc = "0: No received message pending"] + NoMsgPending = 0, + #[doc = "1: Received message pending"] + MsgPending = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RxPend) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RX_PEND` reader - Received Message Pending"] +pub type RxPendR = crate::BitReader; +impl RxPendR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RxPend { + match self.bits { + false => RxPend::NoMsgPending, + true => RxPend::MsgPending, + } + } + #[doc = "No received message pending"] + #[inline(always)] + pub fn is_no_msg_pending(&self) -> bool { + *self == RxPend::NoMsgPending + } + #[doc = "Received message pending"] + #[inline(always)] + pub fn is_msg_pending(&self) -> bool { + *self == RxPend::MsgPending + } +} +#[doc = "Transmit Buffer Not Full\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txnotfull { + #[doc = "0: Transmit buffer full"] + Full = 0, + #[doc = "1: Transmit buffer not full"] + NotFull = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txnotfull) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXNOTFULL` reader - Transmit Buffer Not Full"] +pub type TxnotfullR = crate::BitReader; +impl TxnotfullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txnotfull { + match self.bits { + false => Txnotfull::Full, + true => Txnotfull::NotFull, + } + } + #[doc = "Transmit buffer full"] + #[inline(always)] + pub fn is_full(&self) -> bool { + *self == Txnotfull::Full + } + #[doc = "Transmit buffer not full"] + #[inline(always)] + pub fn is_not_full(&self) -> bool { + *self == Txnotfull::NotFull + } +} +#[doc = "Dynamic Address Change Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dachg { + #[doc = "0: No DA change detected"] + NoChangeDetected = 0, + #[doc = "1: DA change detected"] + ChangeDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dachg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DACHG` reader - Dynamic Address Change Flag"] +pub type DachgR = crate::BitReader; +impl DachgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dachg { + match self.bits { + false => Dachg::NoChangeDetected, + true => Dachg::ChangeDetected, + } + } + #[doc = "No DA change detected"] + #[inline(always)] + pub fn is_no_change_detected(&self) -> bool { + *self == Dachg::NoChangeDetected + } + #[doc = "DA change detected"] + #[inline(always)] + pub fn is_change_detected(&self) -> bool { + *self == Dachg::ChangeDetected + } +} +#[doc = "Field `DACHG` writer - Dynamic Address Change Flag"] +pub type DachgW<'a, REG> = crate::BitWriter1C<'a, REG, Dachg>; +impl<'a, REG> DachgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No DA change detected"] + #[inline(always)] + pub fn no_change_detected(self) -> &'a mut crate::W { + self.variant(Dachg::NoChangeDetected) + } + #[doc = "DA change detected"] + #[inline(always)] + pub fn change_detected(self) -> &'a mut crate::W { + self.variant(Dachg::ChangeDetected) + } +} +#[doc = "Common Command Code Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ccc { + #[doc = "0: CCC not received"] + NoCccReceived = 0, + #[doc = "1: CCC received"] + CccReceived = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ccc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CCC` reader - Common Command Code Flag"] +pub type CccR = crate::BitReader; +impl CccR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ccc { + match self.bits { + false => Ccc::NoCccReceived, + true => Ccc::CccReceived, + } + } + #[doc = "CCC not received"] + #[inline(always)] + pub fn is_no_ccc_received(&self) -> bool { + *self == Ccc::NoCccReceived + } + #[doc = "CCC received"] + #[inline(always)] + pub fn is_ccc_received(&self) -> bool { + *self == Ccc::CccReceived + } +} +#[doc = "Field `CCC` writer - Common Command Code Flag"] +pub type CccW<'a, REG> = crate::BitWriter1C<'a, REG, Ccc>; +impl<'a, REG> CccW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CCC not received"] + #[inline(always)] + pub fn no_ccc_received(self) -> &'a mut crate::W { + self.variant(Ccc::NoCccReceived) + } + #[doc = "CCC received"] + #[inline(always)] + pub fn ccc_received(self) -> &'a mut crate::W { + self.variant(Ccc::CccReceived) + } +} +#[doc = "Field `ERRWARN` reader - Error Warning"] +pub type ErrwarnR = crate::BitReader; +#[doc = "High Data Rate Command Match Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hdrmatch { + #[doc = "0: Did not match"] + NoMatch = 0, + #[doc = "1: Matched the I3C dynamic address"] + Match = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hdrmatch) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HDRMATCH` reader - High Data Rate Command Match Flag"] +pub type HdrmatchR = crate::BitReader; +impl HdrmatchR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hdrmatch { + match self.bits { + false => Hdrmatch::NoMatch, + true => Hdrmatch::Match, + } + } + #[doc = "Did not match"] + #[inline(always)] + pub fn is_no_match(&self) -> bool { + *self == Hdrmatch::NoMatch + } + #[doc = "Matched the I3C dynamic address"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Hdrmatch::Match + } +} +#[doc = "Field `HDRMATCH` writer - High Data Rate Command Match Flag"] +pub type HdrmatchW<'a, REG> = crate::BitWriter1C<'a, REG, Hdrmatch>; +impl<'a, REG> HdrmatchW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Did not match"] + #[inline(always)] + pub fn no_match(self) -> &'a mut crate::W { + self.variant(Hdrmatch::NoMatch) + } + #[doc = "Matched the I3C dynamic address"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Hdrmatch::Match) + } +} +#[doc = "Common Command Code Handled Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Chandled { + #[doc = "0: CCC handling not in progress"] + NotHandled = 0, + #[doc = "1: CCC handling in progress"] + Handled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Chandled) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CHANDLED` reader - Common Command Code Handled Flag"] +pub type ChandledR = crate::BitReader; +impl ChandledR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Chandled { + match self.bits { + false => Chandled::NotHandled, + true => Chandled::Handled, + } + } + #[doc = "CCC handling not in progress"] + #[inline(always)] + pub fn is_not_handled(&self) -> bool { + *self == Chandled::NotHandled + } + #[doc = "CCC handling in progress"] + #[inline(always)] + pub fn is_handled(&self) -> bool { + *self == Chandled::Handled + } +} +#[doc = "Field `CHANDLED` writer - Common Command Code Handled Flag"] +pub type ChandledW<'a, REG> = crate::BitWriter1C<'a, REG, Chandled>; +impl<'a, REG> ChandledW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CCC handling not in progress"] + #[inline(always)] + pub fn not_handled(self) -> &'a mut crate::W { + self.variant(Chandled::NotHandled) + } + #[doc = "CCC handling in progress"] + #[inline(always)] + pub fn handled(self) -> &'a mut crate::W { + self.variant(Chandled::Handled) + } +} +#[doc = "Event Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Event { + #[doc = "0: No event occurred"] + NoEvent = 0, + #[doc = "1: IBI, CR, or HJ occurred"] + Event = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Event) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EVENT` reader - Event Flag"] +pub type EventR = crate::BitReader; +impl EventR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Event { + match self.bits { + false => Event::NoEvent, + true => Event::Event, + } + } + #[doc = "No event occurred"] + #[inline(always)] + pub fn is_no_event(&self) -> bool { + *self == Event::NoEvent + } + #[doc = "IBI, CR, or HJ occurred"] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == Event::Event + } +} +#[doc = "Field `EVENT` writer - Event Flag"] +pub type EventW<'a, REG> = crate::BitWriter1C<'a, REG, Event>; +impl<'a, REG> EventW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No event occurred"] + #[inline(always)] + pub fn no_event(self) -> &'a mut crate::W { + self.variant(Event::NoEvent) + } + #[doc = "IBI, CR, or HJ occurred"] + #[inline(always)] + pub fn event(self) -> &'a mut crate::W { + self.variant(Event::Event) + } +} +#[doc = "Event Details\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Evdet { + #[doc = "0: NONE (no event or no pending event)"] + None = 0, + #[doc = "1: NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))"] + NoRequest = 1, + #[doc = "2: NACKed (not acknowledged, request sent and rejected); I3C tries again"] + Nacked = 2, + #[doc = "3: ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)"] + Acked = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Evdet) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Evdet { + type Ux = u8; +} +impl crate::IsEnum for Evdet {} +#[doc = "Field `EVDET` reader - Event Details"] +pub type EvdetR = crate::FieldReader; +impl EvdetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Evdet { + match self.bits { + 0 => Evdet::None, + 1 => Evdet::NoRequest, + 2 => Evdet::Nacked, + 3 => Evdet::Acked, + _ => unreachable!(), + } + } + #[doc = "NONE (no event or no pending event)"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == Evdet::None + } + #[doc = "NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))"] + #[inline(always)] + pub fn is_no_request(&self) -> bool { + *self == Evdet::NoRequest + } + #[doc = "NACKed (not acknowledged, request sent and rejected); I3C tries again"] + #[inline(always)] + pub fn is_nacked(&self) -> bool { + *self == Evdet::Nacked + } + #[doc = "ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)"] + #[inline(always)] + pub fn is_acked(&self) -> bool { + *self == Evdet::Acked + } +} +#[doc = "In-Band Interrupts Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibidis { + #[doc = "0: Enabled"] + InterruptsEnabled = 0, + #[doc = "1: Disabled"] + InterruptsDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibidis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBIDIS` reader - In-Band Interrupts Disable"] +pub type IbidisR = crate::BitReader; +impl IbidisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibidis { + match self.bits { + false => Ibidis::InterruptsEnabled, + true => Ibidis::InterruptsDisabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_interrupts_enabled(&self) -> bool { + *self == Ibidis::InterruptsEnabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_interrupts_disabled(&self) -> bool { + *self == Ibidis::InterruptsDisabled + } +} +#[doc = "Controller Requests Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mrdis { + #[doc = "0: Enabled"] + MrEnabled = 0, + #[doc = "1: Disabled"] + MrDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mrdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MRDIS` reader - Controller Requests Disable"] +pub type MrdisR = crate::BitReader; +impl MrdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mrdis { + match self.bits { + false => Mrdis::MrEnabled, + true => Mrdis::MrDisabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_mr_enabled(&self) -> bool { + *self == Mrdis::MrEnabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_mr_disabled(&self) -> bool { + *self == Mrdis::MrDisabled + } +} +#[doc = "Hot-Join Disabled\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hjdis { + #[doc = "0: Enabled"] + MrEnabled = 0, + #[doc = "1: Disabled"] + MrDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hjdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HJDIS` reader - Hot-Join Disabled"] +pub type HjdisR = crate::BitReader; +impl HjdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hjdis { + match self.bits { + false => Hjdis::MrEnabled, + true => Hjdis::MrDisabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_mr_enabled(&self) -> bool { + *self == Hjdis::MrEnabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_mr_disabled(&self) -> bool { + *self == Hjdis::MrDisabled + } +} +#[doc = "Activity State from Common Command Codes (CCC)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Actstate { + #[doc = "0: NO_LATENCY (normal bus operations)"] + NoLatency = 0, + #[doc = "1: LATENCY_1MS (1 ms of latency)"] + Latency1ms = 1, + #[doc = "2: LATENCY_100MS (100 ms of latency)"] + Latency100ms = 2, + #[doc = "3: LATENCY_10S (10 seconds of latency)"] + Latency10s = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Actstate) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Actstate { + type Ux = u8; +} +impl crate::IsEnum for Actstate {} +#[doc = "Field `ACTSTATE` reader - Activity State from Common Command Codes (CCC)"] +pub type ActstateR = crate::FieldReader; +impl ActstateR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Actstate { + match self.bits { + 0 => Actstate::NoLatency, + 1 => Actstate::Latency1ms, + 2 => Actstate::Latency100ms, + 3 => Actstate::Latency10s, + _ => unreachable!(), + } + } + #[doc = "NO_LATENCY (normal bus operations)"] + #[inline(always)] + pub fn is_no_latency(&self) -> bool { + *self == Actstate::NoLatency + } + #[doc = "LATENCY_1MS (1 ms of latency)"] + #[inline(always)] + pub fn is_latency_1ms(&self) -> bool { + *self == Actstate::Latency1ms + } + #[doc = "LATENCY_100MS (100 ms of latency)"] + #[inline(always)] + pub fn is_latency_100ms(&self) -> bool { + *self == Actstate::Latency100ms + } + #[doc = "LATENCY_10S (10 seconds of latency)"] + #[inline(always)] + pub fn is_latency_10s(&self) -> bool { + *self == Actstate::Latency10s + } +} +#[doc = "Time Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Timectrl { + #[doc = "0: NO_TIME_CONTROL (no time control is enabled)"] + NoTimeControl = 0, + #[doc = "1: SYNC_MODE (Synchronous mode is enabled)"] + Sync = 1, + #[doc = "2: ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)"] + AsyncMode = 2, + #[doc = "3: BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)"] + Bothsyncasync = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Timectrl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Timectrl { + type Ux = u8; +} +impl crate::IsEnum for Timectrl {} +#[doc = "Field `TIMECTRL` reader - Time Control"] +pub type TimectrlR = crate::FieldReader; +impl TimectrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timectrl { + match self.bits { + 0 => Timectrl::NoTimeControl, + 1 => Timectrl::Sync, + 2 => Timectrl::AsyncMode, + 3 => Timectrl::Bothsyncasync, + _ => unreachable!(), + } + } + #[doc = "NO_TIME_CONTROL (no time control is enabled)"] + #[inline(always)] + pub fn is_no_time_control(&self) -> bool { + *self == Timectrl::NoTimeControl + } + #[doc = "SYNC_MODE (Synchronous mode is enabled)"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + *self == Timectrl::Sync + } + #[doc = "ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)"] + #[inline(always)] + pub fn is_async_mode(&self) -> bool { + *self == Timectrl::AsyncMode + } + #[doc = "BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)"] + #[inline(always)] + pub fn is_bothsyncasync(&self) -> bool { + *self == Timectrl::Bothsyncasync + } +} +impl R { + #[doc = "Bit 0 - Status not Stop"] + #[inline(always)] + pub fn stnotstop(&self) -> StnotstopR { + StnotstopR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Status Message"] + #[inline(always)] + pub fn stmsg(&self) -> StmsgR { + StmsgR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Status Common Command Code Handler"] + #[inline(always)] + pub fn stccch(&self) -> StccchR { + StccchR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Status Request Read"] + #[inline(always)] + pub fn streqrd(&self) -> StreqrdR { + StreqrdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Status Request Write"] + #[inline(always)] + pub fn streqwr(&self) -> StreqwrR { + StreqwrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Status Dynamic Address Assignment"] + #[inline(always)] + pub fn stdaa(&self) -> StdaaR { + StdaaR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Status High Data Rate"] + #[inline(always)] + pub fn sthdr(&self) -> SthdrR { + SthdrR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Start Flag"] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Matched Flag"] + #[inline(always)] + pub fn matched(&self) -> MatchedR { + MatchedR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Stop Flag"] + #[inline(always)] + pub fn stop(&self) -> StopR { + StopR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Received Message Pending"] + #[inline(always)] + pub fn rx_pend(&self) -> RxPendR { + RxPendR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Transmit Buffer Not Full"] + #[inline(always)] + pub fn txnotfull(&self) -> TxnotfullR { + TxnotfullR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Dynamic Address Change Flag"] + #[inline(always)] + pub fn dachg(&self) -> DachgR { + DachgR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Common Command Code Flag"] + #[inline(always)] + pub fn ccc(&self) -> CccR { + CccR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Error Warning"] + #[inline(always)] + pub fn errwarn(&self) -> ErrwarnR { + ErrwarnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - High Data Rate Command Match Flag"] + #[inline(always)] + pub fn hdrmatch(&self) -> HdrmatchR { + HdrmatchR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Common Command Code Handled Flag"] + #[inline(always)] + pub fn chandled(&self) -> ChandledR { + ChandledR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event Flag"] + #[inline(always)] + pub fn event(&self) -> EventR { + EventR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 20:21 - Event Details"] + #[inline(always)] + pub fn evdet(&self) -> EvdetR { + EvdetR::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 24 - In-Band Interrupts Disable"] + #[inline(always)] + pub fn ibidis(&self) -> IbidisR { + IbidisR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Controller Requests Disable"] + #[inline(always)] + pub fn mrdis(&self) -> MrdisR { + MrdisR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Hot-Join Disabled"] + #[inline(always)] + pub fn hjdis(&self) -> HjdisR { + HjdisR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - Activity State from Common Command Codes (CCC)"] + #[inline(always)] + pub fn actstate(&self) -> ActstateR { + ActstateR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Time Control"] + #[inline(always)] + pub fn timectrl(&self) -> TimectrlR { + TimectrlR::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bit 8 - Start Flag"] + #[inline(always)] + pub fn start(&mut self) -> StartW { + StartW::new(self, 8) + } + #[doc = "Bit 9 - Matched Flag"] + #[inline(always)] + pub fn matched(&mut self) -> MatchedW { + MatchedW::new(self, 9) + } + #[doc = "Bit 10 - Stop Flag"] + #[inline(always)] + pub fn stop(&mut self) -> StopW { + StopW::new(self, 10) + } + #[doc = "Bit 13 - Dynamic Address Change Flag"] + #[inline(always)] + pub fn dachg(&mut self) -> DachgW { + DachgW::new(self, 13) + } + #[doc = "Bit 14 - Common Command Code Flag"] + #[inline(always)] + pub fn ccc(&mut self) -> CccW { + CccW::new(self, 14) + } + #[doc = "Bit 16 - High Data Rate Command Match Flag"] + #[inline(always)] + pub fn hdrmatch(&mut self) -> HdrmatchW { + HdrmatchW::new(self, 16) + } + #[doc = "Bit 17 - Common Command Code Handled Flag"] + #[inline(always)] + pub fn chandled(&mut self) -> ChandledW { + ChandledW::new(self, 17) + } + #[doc = "Bit 18 - Event Flag"] + #[inline(always)] + pub fn event(&mut self) -> EventW { + EventW::new(self, 18) + } +} +#[doc = "Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SstatusSpec; +impl crate::RegisterSpec for SstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sstatus::R`](R) reader structure"] +impl crate::Readable for SstatusSpec {} +#[doc = "`write(|w| ..)` method takes [`sstatus::W`](W) writer structure"] +impl crate::Writable for SstatusSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_6700; +} +#[doc = "`reset()` method sets SSTATUS to value 0x1400"] +impl crate::Resettable for SstatusSpec { + const RESET_VALUE: u32 = 0x1400; +} diff --git a/mcxa276-pac/src/i3c0/stcclock.rs b/mcxa276-pac/src/i3c0/stcclock.rs new file mode 100644 index 000000000..3dc6e039c --- /dev/null +++ b/mcxa276-pac/src/i3c0/stcclock.rs @@ -0,0 +1,51 @@ +#[doc = "Register `STCCLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `STCCLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `ACCURACY` reader - Clock Accuracy"] +pub type AccuracyR = crate::FieldReader; +#[doc = "Field `ACCURACY` writer - Clock Accuracy"] +pub type AccuracyW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `FREQ` reader - Clock Frequency"] +pub type FreqR = crate::FieldReader; +#[doc = "Field `FREQ` writer - Clock Frequency"] +pub type FreqW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Clock Accuracy"] + #[inline(always)] + pub fn accuracy(&self) -> AccuracyR { + AccuracyR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Clock Frequency"] + #[inline(always)] + pub fn freq(&self) -> FreqR { + FreqR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock Accuracy"] + #[inline(always)] + pub fn accuracy(&mut self) -> AccuracyW { + AccuracyW::new(self, 0) + } + #[doc = "Bits 8:15 - Clock Frequency"] + #[inline(always)] + pub fn freq(&mut self) -> FreqW { + FreqW::new(self, 8) + } +} +#[doc = "Target Time Control Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`stcclock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stcclock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StcclockSpec; +impl crate::RegisterSpec for StcclockSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stcclock::R`](R) reader structure"] +impl crate::Readable for StcclockSpec {} +#[doc = "`write(|w| ..)` method takes [`stcclock::W`](W) writer structure"] +impl crate::Writable for StcclockSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STCCLOCK to value 0x3014"] +impl crate::Resettable for StcclockSpec { + const RESET_VALUE: u32 = 0x3014; +} diff --git a/mcxa276-pac/src/i3c0/svendorid.rs b/mcxa276-pac/src/i3c0/svendorid.rs new file mode 100644 index 000000000..3baa73692 --- /dev/null +++ b/mcxa276-pac/src/i3c0/svendorid.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SVENDORID` reader"] +pub type R = crate::R; +#[doc = "Register `SVENDORID` writer"] +pub type W = crate::W; +#[doc = "Field `VID` reader - Vendor ID"] +pub type VidR = crate::FieldReader; +#[doc = "Field `VID` writer - Vendor ID"] +pub type VidW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - Vendor ID"] + #[inline(always)] + pub fn vid(&self) -> VidR { + VidR::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bits 0:14 - Vendor ID"] + #[inline(always)] + pub fn vid(&mut self) -> VidW { + VidW::new(self, 0) + } +} +#[doc = "Target Vendor ID\n\nYou can [`read`](crate::Reg::read) this register and get [`svendorid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`svendorid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SvendoridSpec; +impl crate::RegisterSpec for SvendoridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`svendorid::R`](R) reader structure"] +impl crate::Readable for SvendoridSpec {} +#[doc = "`write(|w| ..)` method takes [`svendorid::W`](W) writer structure"] +impl crate::Writable for SvendoridSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SVENDORID to value 0x011b"] +impl crate::Resettable for SvendoridSpec { + const RESET_VALUE: u32 = 0x011b; +} diff --git a/mcxa276-pac/src/i3c0/swdatab.rs b/mcxa276-pac/src/i3c0/swdatab.rs new file mode 100644 index 000000000..1455e1c40 --- /dev/null +++ b/mcxa276-pac/src/i3c0/swdatab.rs @@ -0,0 +1,94 @@ +#[doc = "Register `SWDATAB` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "End\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum End { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: End) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - End"] +pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; +impl<'a, REG> EndW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(End::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(End::End) + } +} +#[doc = "End Also\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EndAlso { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EndAlso) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END_ALSO` writer - End Also"] +pub type EndAlsoW<'a, REG> = crate::BitWriter<'a, REG, EndAlso>; +impl<'a, REG> EndAlsoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(EndAlso::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(EndAlso::End) + } +} +impl W { + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } + #[doc = "Bit 8 - End"] + #[inline(always)] + pub fn end(&mut self) -> EndW { + EndW::new(self, 8) + } + #[doc = "Bit 16 - End Also"] + #[inline(always)] + pub fn end_also(&mut self) -> EndAlsoW { + EndAlsoW::new(self, 16) + } +} +#[doc = "Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatab::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwdatabSpec; +impl crate::RegisterSpec for SwdatabSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`swdatab::W`](W) writer structure"] +impl crate::Writable for SwdatabSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWDATAB to value 0"] +impl crate::Resettable for SwdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/swdatabe.rs b/mcxa276-pac/src/i3c0/swdatabe.rs new file mode 100644 index 000000000..e72d0bf90 --- /dev/null +++ b/mcxa276-pac/src/i3c0/swdatabe.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SWDATABE` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Target Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatabe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwdatabeSpec; +impl crate::RegisterSpec for SwdatabeSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`swdatabe::W`](W) writer structure"] +impl crate::Writable for SwdatabeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWDATABE to value 0"] +impl crate::Resettable for SwdatabeSpec {} diff --git a/mcxa276-pac/src/i3c0/swdatah.rs b/mcxa276-pac/src/i3c0/swdatah.rs new file mode 100644 index 000000000..2c2f2af44 --- /dev/null +++ b/mcxa276-pac/src/i3c0/swdatah.rs @@ -0,0 +1,65 @@ +#[doc = "Register `SWDATAH` writer"] +pub type W = crate::W; +#[doc = "Field `DATA0` writer - Data 0"] +pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA1` writer - Data 1"] +pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "End of Message\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum End { + #[doc = "0: Not the end"] + NotEnd = 0, + #[doc = "1: End"] + End = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: End) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `END` writer - End of Message"] +pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; +impl<'a, REG> EndW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not the end"] + #[inline(always)] + pub fn not_end(self) -> &'a mut crate::W { + self.variant(End::NotEnd) + } + #[doc = "End"] + #[inline(always)] + pub fn end(self) -> &'a mut crate::W { + self.variant(End::End) + } +} +impl W { + #[doc = "Bits 0:7 - Data 0"] + #[inline(always)] + pub fn data0(&mut self) -> Data0W { + Data0W::new(self, 0) + } + #[doc = "Bits 8:15 - Data 1"] + #[inline(always)] + pub fn data1(&mut self) -> Data1W { + Data1W::new(self, 8) + } + #[doc = "Bit 16 - End of Message"] + #[inline(always)] + pub fn end(&mut self) -> EndW { + EndW::new(self, 16) + } +} +#[doc = "Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatah::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwdatahSpec; +impl crate::RegisterSpec for SwdatahSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`swdatah::W`](W) writer structure"] +impl crate::Writable for SwdatahSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWDATAH to value 0"] +impl crate::Resettable for SwdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/swdatahe.rs b/mcxa276-pac/src/i3c0/swdatahe.rs new file mode 100644 index 000000000..c54041f54 --- /dev/null +++ b/mcxa276-pac/src/i3c0/swdatahe.rs @@ -0,0 +1,29 @@ +#[doc = "Register `SWDATAHE` writer"] +pub type W = crate::W; +#[doc = "Field `DATA0` writer - Data 0"] +pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA1` writer - Data 1"] +pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Data 0"] + #[inline(always)] + pub fn data0(&mut self) -> Data0W { + Data0W::new(self, 0) + } + #[doc = "Bits 8:15 - Data 1"] + #[inline(always)] + pub fn data1(&mut self) -> Data1W { + Data1W::new(self, 8) + } +} +#[doc = "Target Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatahe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwdataheSpec; +impl crate::RegisterSpec for SwdataheSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`swdatahe::W`](W) writer structure"] +impl crate::Writable for SwdataheSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWDATAHE to value 0"] +impl crate::Resettable for SwdataheSpec {} diff --git a/mcxa276-pac/src/inputmux0.rs b/mcxa276-pac/src/inputmux0.rs new file mode 100644 index 000000000..9faa6aeb0 --- /dev/null +++ b/mcxa276-pac/src/inputmux0.rs @@ -0,0 +1,1012 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x20], + ctimer0cap: [Ctimer0cap; 4], + timer0trig: Timer0trig, + _reserved2: [u8; 0x0c], + ctimer1cap: [Ctimer1cap; 4], + timer1trig: Timer1trig, + _reserved4: [u8; 0x0c], + ctimer2cap: [Ctimer2cap; 4], + timer2trig: Timer2trig, + _reserved6: [u8; 0x2c], + smart_dma_trig: [SmartDmaTrig; 8], + _reserved7: [u8; 0xc0], + freqmeas_ref: FreqmeasRef, + freqmeas_tar: FreqmeasTar, + _reserved9: [u8; 0x18], + ctimer3cap: [Ctimer3cap; 4], + timer3trig: Timer3trig, + _reserved11: [u8; 0x0c], + ctimer4cap: [Ctimer4cap; 4], + timer4trig: Timer4trig, + _reserved13: [u8; 0x2c], + aoi1_input: [Aoi1Input; 16], + _reserved14: [u8; 0x20], + cmp0_trig: Cmp0Trig, + _reserved15: [u8; 0x1c], + adc0_trig: [Adc0Trig; 4], + _reserved16: [u8; 0x10], + adc2_trig: [Adc2Trig; 4], + _reserved17: [u8; 0x10], + adc1_trig: [Adc1Trig; 4], + _reserved18: [u8; 0x10], + adc3_trig: [Adc3Trig; 4], + _reserved19: [u8; 0x10], + dac0_trig: Dac0Trig, + _reserved20: [u8; 0x5c], + qdc0_trig: Qdc0Trig, + qdc0_home: Qdc0Home, + qdc0_index: Qdc0Index, + qdc0_phaseb: Qdc0Phaseb, + qdc0_phasea: Qdc0Phasea, + qdc0_icap1: Qdc0Icap1, + qdc0_icap2: Qdc0Icap2, + qdc0_icap3: Qdc0Icap3, + qdc1_trig: Qdc1Trig, + qdc1_home: Qdc1Home, + qdc1_index: Qdc1Index, + qdc1_phaseb: Qdc1Phaseb, + qdc1_phasea: Qdc1Phasea, + qdc1_icap1: Qdc1Icap1, + qdc1_icap2: Qdc1Icap2, + qdc1_icap3: Qdc1Icap3, + flex_pwm0_sm0_exta0: FlexPwm0Sm0Exta0, + flex_pwm0_sm0_extsync: FlexPwm0Sm0Extsync, + flex_pwm0_sm1_exta: FlexPwm0Sm1Exta, + flex_pwm0_sm1_extsync: FlexPwm0Sm1Extsync, + flex_pwm0_sm2_exta: FlexPwm0Sm2Exta, + flex_pwm0_sm2_extsync: FlexPwm0Sm2Extsync, + flex_pwm0_sm3_exta0: FlexPwm0Sm3Exta0, + flex_pwm0_sm3_extsync: FlexPwm0Sm3Extsync, + flex_pwm0_fault: [FlexPwm0Fault; 4], + flex_pwm0_force: FlexPwm0Force, + _reserved46: [u8; 0x0c], + flex_pwm1_sm0_exta0: FlexPwm1Sm0Exta0, + flex_pwm1_sm0_extsync: FlexPwm1Sm0Extsync, + flex_pwm1_sm1_exta: FlexPwm1Sm1Exta, + flex_pwm1_sm1_extsync: FlexPwm1Sm1Extsync, + flex_pwm1_sm2_exta: FlexPwm1Sm2Exta, + flex_pwm1_sm2_extsync: FlexPwm1Sm2Extsync, + flex_pwm1_sm3_exta0: FlexPwm1Sm3Exta0, + flex_pwm1_sm3_extsync: FlexPwm1Sm3Extsync, + flex_pwm1_fault: [FlexPwm1Fault; 4], + flex_pwm1_force: FlexPwm1Force, + _reserved56: [u8; 0x0c], + pwm0_ext_clk: Pwm0ExtClk, + pwm1_ext_clk: Pwm1ExtClk, + _reserved58: [u8; 0x18], + aoi0_input: [Aoi0Input; 16], + usbfs_trig: UsbfsTrig, + _reserved60: [u8; 0x3c], + ext_trig: [ExtTrig; 8], + cmp1_trig: Cmp1Trig, + _reserved62: [u8; 0x1c], + cmp2_trig: Cmp2Trig, + _reserved63: [u8; 0x3c], + lpi2c2_trig: Lpi2c2Trig, + _reserved64: [u8; 0x1c], + lpi2c3_trig: Lpi2c3Trig, + _reserved65: [u8; 0x3c], + lpi2c0_trig: Lpi2c0Trig, + _reserved66: [u8; 0x1c], + lpi2c1_trig: Lpi2c1Trig, + _reserved67: [u8; 0x1c], + lpspi0_trig: Lpspi0Trig, + _reserved68: [u8; 0x1c], + lpspi1_trig: Lpspi1Trig, + _reserved69: [u8; 0x1c], + lpuart0: Lpuart0, + _reserved70: [u8; 0x1c], + lpuart1: Lpuart1, + _reserved71: [u8; 0x1c], + lpuart2: Lpuart2, + _reserved72: [u8; 0x1c], + lpuart3: Lpuart3, + _reserved73: [u8; 0x1c], + lpuart4: Lpuart4, + _reserved74: [u8; 0x1c], + lpuart5: Lpuart5, + _reserved75: [u8; 0x1c], + flexio_trig: [FlexioTrig; 4], + _reserved76: [u8; 0x0310], + trigfil_prsc: TrigfilPrsc, + trigfil_stat0: TrigfilStat0, + _reserved78: [u8; 0x08], + trigfil: [Trigfil; 12], +} +impl RegisterBlock { + #[doc = "0x20..0x30 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub const fn ctimer0cap(&self, n: usize) -> &Ctimer0cap { + &self.ctimer0cap[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x20..0x30 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub fn ctimer0cap_iter(&self) -> impl Iterator { + self.ctimer0cap.iter() + } + #[doc = "0x30 - Trigger register for TIMER0"] + #[inline(always)] + pub const fn timer0trig(&self) -> &Timer0trig { + &self.timer0trig + } + #[doc = "0x40..0x50 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub const fn ctimer1cap(&self, n: usize) -> &Ctimer1cap { + &self.ctimer1cap[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x40..0x50 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub fn ctimer1cap_iter(&self) -> impl Iterator { + self.ctimer1cap.iter() + } + #[doc = "0x50 - Trigger register for TIMER1"] + #[inline(always)] + pub const fn timer1trig(&self) -> &Timer1trig { + &self.timer1trig + } + #[doc = "0x60..0x70 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub const fn ctimer2cap(&self, n: usize) -> &Ctimer2cap { + &self.ctimer2cap[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x60..0x70 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub fn ctimer2cap_iter(&self) -> impl Iterator { + self.ctimer2cap.iter() + } + #[doc = "0x70 - Trigger register for TIMER2 inputs"] + #[inline(always)] + pub const fn timer2trig(&self) -> &Timer2trig { + &self.timer2trig + } + #[doc = "0xa0..0xc0 - SmartDMA Trigger Input Connections"] + #[inline(always)] + pub const fn smart_dma_trig(&self, n: usize) -> &SmartDmaTrig { + &self.smart_dma_trig[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xa0..0xc0 - SmartDMA Trigger Input Connections"] + #[inline(always)] + pub fn smart_dma_trig_iter(&self) -> impl Iterator { + self.smart_dma_trig.iter() + } + #[doc = "0x180 - Selection for frequency measurement reference clock"] + #[inline(always)] + pub const fn freqmeas_ref(&self) -> &FreqmeasRef { + &self.freqmeas_ref + } + #[doc = "0x184 - Selection for frequency measurement reference clock"] + #[inline(always)] + pub const fn freqmeas_tar(&self) -> &FreqmeasTar { + &self.freqmeas_tar + } + #[doc = "0x1a0..0x1b0 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub const fn ctimer3cap(&self, n: usize) -> &Ctimer3cap { + &self.ctimer3cap[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x1a0..0x1b0 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub fn ctimer3cap_iter(&self) -> impl Iterator { + self.ctimer3cap.iter() + } + #[doc = "0x1b0 - Trigger register for TIMER3"] + #[inline(always)] + pub const fn timer3trig(&self) -> &Timer3trig { + &self.timer3trig + } + #[doc = "0x1c0..0x1d0 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub const fn ctimer4cap(&self, n: usize) -> &Ctimer4cap { + &self.ctimer4cap[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x1c0..0x1d0 - Capture select register for CTIMER inputs"] + #[inline(always)] + pub fn ctimer4cap_iter(&self) -> impl Iterator { + self.ctimer4cap.iter() + } + #[doc = "0x1d0 - Trigger register for TIMER4"] + #[inline(always)] + pub const fn timer4trig(&self) -> &Timer4trig { + &self.timer4trig + } + #[doc = "0x200..0x240 - AOI1 trigger input connections 0"] + #[inline(always)] + pub const fn aoi1_input(&self, n: usize) -> &Aoi1Input { + &self.aoi1_input[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x200..0x240 - AOI1 trigger input connections 0"] + #[inline(always)] + pub fn aoi1_input_iter(&self) -> impl Iterator { + self.aoi1_input.iter() + } + #[doc = "0x260 - CMP0 input connections"] + #[inline(always)] + pub const fn cmp0_trig(&self) -> &Cmp0Trig { + &self.cmp0_trig + } + #[doc = "0x280..0x290 - ADC Trigger input connections"] + #[inline(always)] + pub const fn adc0_trig(&self, n: usize) -> &Adc0Trig { + &self.adc0_trig[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x280..0x290 - ADC Trigger input connections"] + #[inline(always)] + pub fn adc0_trig_iter(&self) -> impl Iterator { + self.adc0_trig.iter() + } + #[doc = "0x2a0..0x2b0 - ADC Trigger input connections"] + #[inline(always)] + pub const fn adc2_trig(&self, n: usize) -> &Adc2Trig { + &self.adc2_trig[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2a0..0x2b0 - ADC Trigger input connections"] + #[inline(always)] + pub fn adc2_trig_iter(&self) -> impl Iterator { + self.adc2_trig.iter() + } + #[doc = "0x2c0..0x2d0 - ADC Trigger input connections"] + #[inline(always)] + pub const fn adc1_trig(&self, n: usize) -> &Adc1Trig { + &self.adc1_trig[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c0..0x2d0 - ADC Trigger input connections"] + #[inline(always)] + pub fn adc1_trig_iter(&self) -> impl Iterator { + self.adc1_trig.iter() + } + #[doc = "0x2e0..0x2f0 - ADC Trigger input connections"] + #[inline(always)] + pub const fn adc3_trig(&self, n: usize) -> &Adc3Trig { + &self.adc3_trig[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2e0..0x2f0 - ADC Trigger input connections"] + #[inline(always)] + pub fn adc3_trig_iter(&self) -> impl Iterator { + self.adc3_trig.iter() + } + #[doc = "0x300 - DAC0 Trigger input connections."] + #[inline(always)] + pub const fn dac0_trig(&self) -> &Dac0Trig { + &self.dac0_trig + } + #[doc = "0x360 - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_trig(&self) -> &Qdc0Trig { + &self.qdc0_trig + } + #[doc = "0x364 - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_home(&self) -> &Qdc0Home { + &self.qdc0_home + } + #[doc = "0x368 - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_index(&self) -> &Qdc0Index { + &self.qdc0_index + } + #[doc = "0x36c - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_phaseb(&self) -> &Qdc0Phaseb { + &self.qdc0_phaseb + } + #[doc = "0x370 - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_phasea(&self) -> &Qdc0Phasea { + &self.qdc0_phasea + } + #[doc = "0x374 - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_icap1(&self) -> &Qdc0Icap1 { + &self.qdc0_icap1 + } + #[doc = "0x378 - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_icap2(&self) -> &Qdc0Icap2 { + &self.qdc0_icap2 + } + #[doc = "0x37c - QDC0 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc0_icap3(&self) -> &Qdc0Icap3 { + &self.qdc0_icap3 + } + #[doc = "0x380 - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_trig(&self) -> &Qdc1Trig { + &self.qdc1_trig + } + #[doc = "0x384 - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_home(&self) -> &Qdc1Home { + &self.qdc1_home + } + #[doc = "0x388 - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_index(&self) -> &Qdc1Index { + &self.qdc1_index + } + #[doc = "0x38c - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_phaseb(&self) -> &Qdc1Phaseb { + &self.qdc1_phaseb + } + #[doc = "0x390 - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_phasea(&self) -> &Qdc1Phasea { + &self.qdc1_phasea + } + #[doc = "0x394 - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_icap1(&self) -> &Qdc1Icap1 { + &self.qdc1_icap1 + } + #[doc = "0x398 - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_icap2(&self) -> &Qdc1Icap2 { + &self.qdc1_icap2 + } + #[doc = "0x39c - QDC1 Trigger Input Connections"] + #[inline(always)] + pub const fn qdc1_icap3(&self) -> &Qdc1Icap3 { + &self.qdc1_icap3 + } + #[doc = "0x3a0 - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm0_exta0(&self) -> &FlexPwm0Sm0Exta0 { + &self.flex_pwm0_sm0_exta0 + } + #[doc = "0x3a4 - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm0_extsync(&self) -> &FlexPwm0Sm0Extsync { + &self.flex_pwm0_sm0_extsync + } + #[doc = "0x3a8 - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm1_exta(&self) -> &FlexPwm0Sm1Exta { + &self.flex_pwm0_sm1_exta + } + #[doc = "0x3ac - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm1_extsync(&self) -> &FlexPwm0Sm1Extsync { + &self.flex_pwm0_sm1_extsync + } + #[doc = "0x3b0 - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm2_exta(&self) -> &FlexPwm0Sm2Exta { + &self.flex_pwm0_sm2_exta + } + #[doc = "0x3b4 - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm2_extsync(&self) -> &FlexPwm0Sm2Extsync { + &self.flex_pwm0_sm2_extsync + } + #[doc = "0x3b8 - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm3_exta0(&self) -> &FlexPwm0Sm3Exta0 { + &self.flex_pwm0_sm3_exta0 + } + #[doc = "0x3bc - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_sm3_extsync(&self) -> &FlexPwm0Sm3Extsync { + &self.flex_pwm0_sm3_extsync + } + #[doc = "0x3c0..0x3d0 - PWM0 Fault Input Trigger Connections"] + #[inline(always)] + pub const fn flex_pwm0_fault(&self, n: usize) -> &FlexPwm0Fault { + &self.flex_pwm0_fault[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x3c0..0x3d0 - PWM0 Fault Input Trigger Connections"] + #[inline(always)] + pub fn flex_pwm0_fault_iter(&self) -> impl Iterator { + self.flex_pwm0_fault.iter() + } + #[doc = "0x3d0 - PWM0 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm0_force(&self) -> &FlexPwm0Force { + &self.flex_pwm0_force + } + #[doc = "0x3e0 - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm0_exta0(&self) -> &FlexPwm1Sm0Exta0 { + &self.flex_pwm1_sm0_exta0 + } + #[doc = "0x3e4 - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm0_extsync(&self) -> &FlexPwm1Sm0Extsync { + &self.flex_pwm1_sm0_extsync + } + #[doc = "0x3e8 - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm1_exta(&self) -> &FlexPwm1Sm1Exta { + &self.flex_pwm1_sm1_exta + } + #[doc = "0x3ec - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm1_extsync(&self) -> &FlexPwm1Sm1Extsync { + &self.flex_pwm1_sm1_extsync + } + #[doc = "0x3f0 - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm2_exta(&self) -> &FlexPwm1Sm2Exta { + &self.flex_pwm1_sm2_exta + } + #[doc = "0x3f4 - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm2_extsync(&self) -> &FlexPwm1Sm2Extsync { + &self.flex_pwm1_sm2_extsync + } + #[doc = "0x3f8 - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm3_exta0(&self) -> &FlexPwm1Sm3Exta0 { + &self.flex_pwm1_sm3_exta0 + } + #[doc = "0x3fc - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_sm3_extsync(&self) -> &FlexPwm1Sm3Extsync { + &self.flex_pwm1_sm3_extsync + } + #[doc = "0x400..0x410 - PWM1 Fault Input Trigger Connections"] + #[inline(always)] + pub const fn flex_pwm1_fault(&self, n: usize) -> &FlexPwm1Fault { + &self.flex_pwm1_fault[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x400..0x410 - PWM1 Fault Input Trigger Connections"] + #[inline(always)] + pub fn flex_pwm1_fault_iter(&self) -> impl Iterator { + self.flex_pwm1_fault.iter() + } + #[doc = "0x410 - PWM1 input trigger connections"] + #[inline(always)] + pub const fn flex_pwm1_force(&self) -> &FlexPwm1Force { + &self.flex_pwm1_force + } + #[doc = "0x420 - PWM0 external clock trigger"] + #[inline(always)] + pub const fn pwm0_ext_clk(&self) -> &Pwm0ExtClk { + &self.pwm0_ext_clk + } + #[doc = "0x424 - PWM1 external clock trigger"] + #[inline(always)] + pub const fn pwm1_ext_clk(&self) -> &Pwm1ExtClk { + &self.pwm1_ext_clk + } + #[doc = "0x440..0x480 - AOI0 trigger input connections 0"] + #[inline(always)] + pub const fn aoi0_input(&self, n: usize) -> &Aoi0Input { + &self.aoi0_input[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x440..0x480 - AOI0 trigger input connections 0"] + #[inline(always)] + pub fn aoi0_input_iter(&self) -> impl Iterator { + self.aoi0_input.iter() + } + #[doc = "0x480 - USB-FS trigger input connections"] + #[inline(always)] + pub const fn usbfs_trig(&self) -> &UsbfsTrig { + &self.usbfs_trig + } + #[doc = "0x4c0..0x4e0 - EXT trigger connections"] + #[inline(always)] + pub const fn ext_trig(&self, n: usize) -> &ExtTrig { + &self.ext_trig[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x4c0..0x4e0 - EXT trigger connections"] + #[inline(always)] + pub fn ext_trig_iter(&self) -> impl Iterator { + self.ext_trig.iter() + } + #[doc = "0x4e0 - CMP1 input connections"] + #[inline(always)] + pub const fn cmp1_trig(&self) -> &Cmp1Trig { + &self.cmp1_trig + } + #[doc = "0x500 - CMP2 input connections"] + #[inline(always)] + pub const fn cmp2_trig(&self) -> &Cmp2Trig { + &self.cmp2_trig + } + #[doc = "0x540 - LPI2C2 trigger input connections"] + #[inline(always)] + pub const fn lpi2c2_trig(&self) -> &Lpi2c2Trig { + &self.lpi2c2_trig + } + #[doc = "0x560 - LPI2C3 trigger input connections"] + #[inline(always)] + pub const fn lpi2c3_trig(&self) -> &Lpi2c3Trig { + &self.lpi2c3_trig + } + #[doc = "0x5a0 - LPI2C0 trigger input connections"] + #[inline(always)] + pub const fn lpi2c0_trig(&self) -> &Lpi2c0Trig { + &self.lpi2c0_trig + } + #[doc = "0x5c0 - LPI2C1 trigger input connections"] + #[inline(always)] + pub const fn lpi2c1_trig(&self) -> &Lpi2c1Trig { + &self.lpi2c1_trig + } + #[doc = "0x5e0 - LPSPI0 trigger input connections"] + #[inline(always)] + pub const fn lpspi0_trig(&self) -> &Lpspi0Trig { + &self.lpspi0_trig + } + #[doc = "0x600 - LPSPI1 trigger input connections"] + #[inline(always)] + pub const fn lpspi1_trig(&self) -> &Lpspi1Trig { + &self.lpspi1_trig + } + #[doc = "0x620 - LPUART0 trigger input connections"] + #[inline(always)] + pub const fn lpuart0(&self) -> &Lpuart0 { + &self.lpuart0 + } + #[doc = "0x640 - LPUART1 trigger input connections"] + #[inline(always)] + pub const fn lpuart1(&self) -> &Lpuart1 { + &self.lpuart1 + } + #[doc = "0x660 - LPUART2 trigger input connections"] + #[inline(always)] + pub const fn lpuart2(&self) -> &Lpuart2 { + &self.lpuart2 + } + #[doc = "0x680 - LPUART3 trigger input connections"] + #[inline(always)] + pub const fn lpuart3(&self) -> &Lpuart3 { + &self.lpuart3 + } + #[doc = "0x6a0 - LPUART4 trigger input connections"] + #[inline(always)] + pub const fn lpuart4(&self) -> &Lpuart4 { + &self.lpuart4 + } + #[doc = "0x6c0 - LPUART5 trigger input connections"] + #[inline(always)] + pub const fn lpuart5(&self) -> &Lpuart5 { + &self.lpuart5 + } + #[doc = "0x6e0..0x6f0 - FlexIO Trigger Input Connections"] + #[inline(always)] + pub const fn flexio_trig(&self, n: usize) -> &FlexioTrig { + &self.flexio_trig[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x6e0..0x6f0 - FlexIO Trigger Input Connections"] + #[inline(always)] + pub fn flexio_trig_iter(&self) -> impl Iterator { + self.flexio_trig.iter() + } + #[doc = "0xa00 - Trigger filter prescaller"] + #[inline(always)] + pub const fn trigfil_prsc(&self) -> &TrigfilPrsc { + &self.trigfil_prsc + } + #[doc = "0xa04 - Trigger filter stat"] + #[inline(always)] + pub const fn trigfil_stat0(&self) -> &TrigfilStat0 { + &self.trigfil_stat0 + } + #[doc = "0xa10..0xa40 - TRIGFIL control"] + #[inline(always)] + pub const fn trigfil(&self, n: usize) -> &Trigfil { + &self.trigfil[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xa10..0xa40 - TRIGFIL control"] + #[inline(always)] + pub fn trigfil_iter(&self) -> impl Iterator { + self.trigfil.iter() + } +} +#[doc = "CTIMER0CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer0cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer0cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer0cap`] module"] +#[doc(alias = "CTIMER0CAP")] +pub type Ctimer0cap = crate::Reg; +#[doc = "Capture select register for CTIMER inputs"] +pub mod ctimer0cap; +#[doc = "TIMER0TRIG (rw) register accessor: Trigger register for TIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`timer0trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer0trig`] module"] +#[doc(alias = "TIMER0TRIG")] +pub type Timer0trig = crate::Reg; +#[doc = "Trigger register for TIMER0"] +pub mod timer0trig; +#[doc = "CTIMER1CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer1cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer1cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer1cap`] module"] +#[doc(alias = "CTIMER1CAP")] +pub type Ctimer1cap = crate::Reg; +#[doc = "Capture select register for CTIMER inputs"] +pub mod ctimer1cap; +#[doc = "TIMER1TRIG (rw) register accessor: Trigger register for TIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1trig`] module"] +#[doc(alias = "TIMER1TRIG")] +pub type Timer1trig = crate::Reg; +#[doc = "Trigger register for TIMER1"] +pub mod timer1trig; +#[doc = "CTIMER2CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer2cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer2cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer2cap`] module"] +#[doc(alias = "CTIMER2CAP")] +pub type Ctimer2cap = crate::Reg; +#[doc = "Capture select register for CTIMER inputs"] +pub mod ctimer2cap; +#[doc = "TIMER2TRIG (rw) register accessor: Trigger register for TIMER2 inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2trig`] module"] +#[doc(alias = "TIMER2TRIG")] +pub type Timer2trig = crate::Reg; +#[doc = "Trigger register for TIMER2 inputs"] +pub mod timer2trig; +#[doc = "SmartDMA_TRIG (rw) register accessor: SmartDMA Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dma_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dma_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smart_dma_trig`] module"] +#[doc(alias = "SmartDMA_TRIG")] +pub type SmartDmaTrig = crate::Reg; +#[doc = "SmartDMA Trigger Input Connections"] +pub mod smart_dma_trig; +#[doc = "FREQMEAS_REF (rw) register accessor: Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_ref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_ref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@freqmeas_ref`] module"] +#[doc(alias = "FREQMEAS_REF")] +pub type FreqmeasRef = crate::Reg; +#[doc = "Selection for frequency measurement reference clock"] +pub mod freqmeas_ref; +#[doc = "FREQMEAS_TAR (rw) register accessor: Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@freqmeas_tar`] module"] +#[doc(alias = "FREQMEAS_TAR")] +pub type FreqmeasTar = crate::Reg; +#[doc = "Selection for frequency measurement reference clock"] +pub mod freqmeas_tar; +#[doc = "CTIMER3CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer3cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer3cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer3cap`] module"] +#[doc(alias = "CTIMER3CAP")] +pub type Ctimer3cap = crate::Reg; +#[doc = "Capture select register for CTIMER inputs"] +pub mod ctimer3cap; +#[doc = "TIMER3TRIG (rw) register accessor: Trigger register for TIMER3\n\nYou can [`read`](crate::Reg::read) this register and get [`timer3trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer3trig`] module"] +#[doc(alias = "TIMER3TRIG")] +pub type Timer3trig = crate::Reg; +#[doc = "Trigger register for TIMER3"] +pub mod timer3trig; +#[doc = "CTIMER4CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer4cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer4cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer4cap`] module"] +#[doc(alias = "CTIMER4CAP")] +pub type Ctimer4cap = crate::Reg; +#[doc = "Capture select register for CTIMER inputs"] +pub mod ctimer4cap; +#[doc = "TIMER4TRIG (rw) register accessor: Trigger register for TIMER4\n\nYou can [`read`](crate::Reg::read) this register and get [`timer4trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer4trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer4trig`] module"] +#[doc(alias = "TIMER4TRIG")] +pub type Timer4trig = crate::Reg; +#[doc = "Trigger register for TIMER4"] +pub mod timer4trig; +#[doc = "AOI1_INPUT (rw) register accessor: AOI1 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoi1_input`] module"] +#[doc(alias = "AOI1_INPUT")] +pub type Aoi1Input = crate::Reg; +#[doc = "AOI1 trigger input connections 0"] +pub mod aoi1_input; +#[doc = "CMP0_TRIG (rw) register accessor: CMP0 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp0_trig`] module"] +#[doc(alias = "CMP0_TRIG")] +pub type Cmp0Trig = crate::Reg; +#[doc = "CMP0 input connections"] +pub mod cmp0_trig; +#[doc = "ADC0_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc0_trig`] module"] +#[doc(alias = "ADC0_TRIG")] +pub type Adc0Trig = crate::Reg; +#[doc = "ADC Trigger input connections"] +pub mod adc0_trig; +#[doc = "ADC2_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc2_trig`] module"] +#[doc(alias = "ADC2_TRIG")] +pub type Adc2Trig = crate::Reg; +#[doc = "ADC Trigger input connections"] +pub mod adc2_trig; +#[doc = "ADC1_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc1_trig`] module"] +#[doc(alias = "ADC1_TRIG")] +pub type Adc1Trig = crate::Reg; +#[doc = "ADC Trigger input connections"] +pub mod adc1_trig; +#[doc = "ADC3_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc3_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc3_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc3_trig`] module"] +#[doc(alias = "ADC3_TRIG")] +pub type Adc3Trig = crate::Reg; +#[doc = "ADC Trigger input connections"] +pub mod adc3_trig; +#[doc = "DAC0_TRIG (rw) register accessor: DAC0 Trigger input connections.\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dac0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac0_trig`] module"] +#[doc(alias = "DAC0_TRIG")] +pub type Dac0Trig = crate::Reg; +#[doc = "DAC0 Trigger input connections."] +pub mod dac0_trig; +#[doc = "QDC0_TRIG (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_trig`] module"] +#[doc(alias = "QDC0_TRIG")] +pub type Qdc0Trig = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_trig; +#[doc = "QDC0_HOME (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_home::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_home::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_home`] module"] +#[doc(alias = "QDC0_HOME")] +pub type Qdc0Home = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_home; +#[doc = "QDC0_INDEX (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_index`] module"] +#[doc(alias = "QDC0_INDEX")] +pub type Qdc0Index = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_index; +#[doc = "QDC0_PHASEB (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phaseb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phaseb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_phaseb`] module"] +#[doc(alias = "QDC0_PHASEB")] +pub type Qdc0Phaseb = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_phaseb; +#[doc = "QDC0_PHASEA (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phasea::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phasea::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_phasea`] module"] +#[doc(alias = "QDC0_PHASEA")] +pub type Qdc0Phasea = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_phasea; +#[doc = "QDC0_ICAP1 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap1`] module"] +#[doc(alias = "QDC0_ICAP1")] +pub type Qdc0Icap1 = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_icap1; +#[doc = "QDC0_ICAP2 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap2`] module"] +#[doc(alias = "QDC0_ICAP2")] +pub type Qdc0Icap2 = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_icap2; +#[doc = "QDC0_ICAP3 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap3`] module"] +#[doc(alias = "QDC0_ICAP3")] +pub type Qdc0Icap3 = crate::Reg; +#[doc = "QDC0 Trigger Input Connections"] +pub mod qdc0_icap3; +#[doc = "QDC1_TRIG (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_trig`] module"] +#[doc(alias = "QDC1_TRIG")] +pub type Qdc1Trig = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_trig; +#[doc = "QDC1_HOME (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_home::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_home::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_home`] module"] +#[doc(alias = "QDC1_HOME")] +pub type Qdc1Home = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_home; +#[doc = "QDC1_INDEX (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_index`] module"] +#[doc(alias = "QDC1_INDEX")] +pub type Qdc1Index = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_index; +#[doc = "QDC1_PHASEB (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phaseb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phaseb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_phaseb`] module"] +#[doc(alias = "QDC1_PHASEB")] +pub type Qdc1Phaseb = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_phaseb; +#[doc = "QDC1_PHASEA (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phasea::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phasea::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_phasea`] module"] +#[doc(alias = "QDC1_PHASEA")] +pub type Qdc1Phasea = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_phasea; +#[doc = "QDC1_ICAP1 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap1`] module"] +#[doc(alias = "QDC1_ICAP1")] +pub type Qdc1Icap1 = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_icap1; +#[doc = "QDC1_ICAP2 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap2`] module"] +#[doc(alias = "QDC1_ICAP2")] +pub type Qdc1Icap2 = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_icap2; +#[doc = "QDC1_ICAP3 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap3`] module"] +#[doc(alias = "QDC1_ICAP3")] +pub type Qdc1Icap3 = crate::Reg; +#[doc = "QDC1 Trigger Input Connections"] +pub mod qdc1_icap3; +#[doc = "FlexPWM0_SM0_EXTA0 (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm0_exta0`] module"] +#[doc(alias = "FlexPWM0_SM0_EXTA0")] +pub type FlexPwm0Sm0Exta0 = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm0_exta0; +#[doc = "FlexPWM0_SM0_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm0_extsync`] module"] +#[doc(alias = "FlexPWM0_SM0_EXTSYNC")] +pub type FlexPwm0Sm0Extsync = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm0_extsync; +#[doc = "FlexPWM0_SM1_EXTA (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm1_exta`] module"] +#[doc(alias = "FlexPWM0_SM1_EXTA")] +pub type FlexPwm0Sm1Exta = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm1_exta; +#[doc = "FlexPWM0_SM1_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm1_extsync`] module"] +#[doc(alias = "FlexPWM0_SM1_EXTSYNC")] +pub type FlexPwm0Sm1Extsync = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm1_extsync; +#[doc = "FlexPWM0_SM2_EXTA (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm2_exta`] module"] +#[doc(alias = "FlexPWM0_SM2_EXTA")] +pub type FlexPwm0Sm2Exta = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm2_exta; +#[doc = "FlexPWM0_SM2_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm2_extsync`] module"] +#[doc(alias = "FlexPWM0_SM2_EXTSYNC")] +pub type FlexPwm0Sm2Extsync = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm2_extsync; +#[doc = "FlexPWM0_SM3_EXTA0 (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm3_exta0`] module"] +#[doc(alias = "FlexPWM0_SM3_EXTA0")] +pub type FlexPwm0Sm3Exta0 = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm3_exta0; +#[doc = "FlexPWM0_SM3_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm3_extsync`] module"] +#[doc(alias = "FlexPWM0_SM3_EXTSYNC")] +pub type FlexPwm0Sm3Extsync = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_sm3_extsync; +#[doc = "FlexPWM0_FAULT (rw) register accessor: PWM0 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_fault::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_fault::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_fault`] module"] +#[doc(alias = "FlexPWM0_FAULT")] +pub type FlexPwm0Fault = crate::Reg; +#[doc = "PWM0 Fault Input Trigger Connections"] +pub mod flex_pwm0_fault; +#[doc = "FlexPWM0_FORCE (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_force`] module"] +#[doc(alias = "FlexPWM0_FORCE")] +pub type FlexPwm0Force = crate::Reg; +#[doc = "PWM0 input trigger connections"] +pub mod flex_pwm0_force; +#[doc = "FlexPWM1_SM0_EXTA0 (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm0_exta0`] module"] +#[doc(alias = "FlexPWM1_SM0_EXTA0")] +pub type FlexPwm1Sm0Exta0 = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm0_exta0; +#[doc = "FlexPWM1_SM0_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm0_extsync`] module"] +#[doc(alias = "FlexPWM1_SM0_EXTSYNC")] +pub type FlexPwm1Sm0Extsync = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm0_extsync; +#[doc = "FlexPWM1_SM1_EXTA (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm1_exta`] module"] +#[doc(alias = "FlexPWM1_SM1_EXTA")] +pub type FlexPwm1Sm1Exta = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm1_exta; +#[doc = "FlexPWM1_SM1_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm1_extsync`] module"] +#[doc(alias = "FlexPWM1_SM1_EXTSYNC")] +pub type FlexPwm1Sm1Extsync = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm1_extsync; +#[doc = "FlexPWM1_SM2_EXTA (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm2_exta`] module"] +#[doc(alias = "FlexPWM1_SM2_EXTA")] +pub type FlexPwm1Sm2Exta = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm2_exta; +#[doc = "FlexPWM1_SM2_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm2_extsync`] module"] +#[doc(alias = "FlexPWM1_SM2_EXTSYNC")] +pub type FlexPwm1Sm2Extsync = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm2_extsync; +#[doc = "FlexPWM1_SM3_EXTA0 (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm3_exta0`] module"] +#[doc(alias = "FlexPWM1_SM3_EXTA0")] +pub type FlexPwm1Sm3Exta0 = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm3_exta0; +#[doc = "FlexPWM1_SM3_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm3_extsync`] module"] +#[doc(alias = "FlexPWM1_SM3_EXTSYNC")] +pub type FlexPwm1Sm3Extsync = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_sm3_extsync; +#[doc = "FlexPWM1_FAULT (rw) register accessor: PWM1 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_fault::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_fault::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_fault`] module"] +#[doc(alias = "FlexPWM1_FAULT")] +pub type FlexPwm1Fault = crate::Reg; +#[doc = "PWM1 Fault Input Trigger Connections"] +pub mod flex_pwm1_fault; +#[doc = "FlexPWM1_FORCE (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_force`] module"] +#[doc(alias = "FlexPWM1_FORCE")] +pub type FlexPwm1Force = crate::Reg; +#[doc = "PWM1 input trigger connections"] +pub mod flex_pwm1_force; +#[doc = "PWM0_EXT_CLK (rw) register accessor: PWM0 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0_ext_clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0_ext_clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0_ext_clk`] module"] +#[doc(alias = "PWM0_EXT_CLK")] +pub type Pwm0ExtClk = crate::Reg; +#[doc = "PWM0 external clock trigger"] +pub mod pwm0_ext_clk; +#[doc = "PWM1_EXT_CLK (rw) register accessor: PWM1 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1_ext_clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1_ext_clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1_ext_clk`] module"] +#[doc(alias = "PWM1_EXT_CLK")] +pub type Pwm1ExtClk = crate::Reg; +#[doc = "PWM1 external clock trigger"] +pub mod pwm1_ext_clk; +#[doc = "AOI0_INPUT (rw) register accessor: AOI0 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi0_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi0_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoi0_input`] module"] +#[doc(alias = "AOI0_INPUT")] +pub type Aoi0Input = crate::Reg; +#[doc = "AOI0 trigger input connections 0"] +pub mod aoi0_input; +#[doc = "USBFS_TRIG (rw) register accessor: USB-FS trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfs_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfs_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbfs_trig`] module"] +#[doc(alias = "USBFS_TRIG")] +pub type UsbfsTrig = crate::Reg; +#[doc = "USB-FS trigger input connections"] +pub mod usbfs_trig; +#[doc = "EXT_TRIG (rw) register accessor: EXT trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_trig`] module"] +#[doc(alias = "EXT_TRIG")] +pub type ExtTrig = crate::Reg; +#[doc = "EXT trigger connections"] +pub mod ext_trig; +#[doc = "CMP1_TRIG (rw) register accessor: CMP1 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp1_trig`] module"] +#[doc(alias = "CMP1_TRIG")] +pub type Cmp1Trig = crate::Reg; +#[doc = "CMP1 input connections"] +pub mod cmp1_trig; +#[doc = "CMP2_TRIG (rw) register accessor: CMP2 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp2_trig`] module"] +#[doc(alias = "CMP2_TRIG")] +pub type Cmp2Trig = crate::Reg; +#[doc = "CMP2 input connections"] +pub mod cmp2_trig; +#[doc = "LPI2C2_TRIG (rw) register accessor: LPI2C2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c2_trig`] module"] +#[doc(alias = "LPI2C2_TRIG")] +pub type Lpi2c2Trig = crate::Reg; +#[doc = "LPI2C2 trigger input connections"] +pub mod lpi2c2_trig; +#[doc = "LPI2C3_TRIG (rw) register accessor: LPI2C3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c3_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c3_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c3_trig`] module"] +#[doc(alias = "LPI2C3_TRIG")] +pub type Lpi2c3Trig = crate::Reg; +#[doc = "LPI2C3 trigger input connections"] +pub mod lpi2c3_trig; +#[doc = "LPI2C0_TRIG (rw) register accessor: LPI2C0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c0_trig`] module"] +#[doc(alias = "LPI2C0_TRIG")] +pub type Lpi2c0Trig = crate::Reg; +#[doc = "LPI2C0 trigger input connections"] +pub mod lpi2c0_trig; +#[doc = "LPI2C1_TRIG (rw) register accessor: LPI2C1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c1_trig`] module"] +#[doc(alias = "LPI2C1_TRIG")] +pub type Lpi2c1Trig = crate::Reg; +#[doc = "LPI2C1 trigger input connections"] +pub mod lpi2c1_trig; +#[doc = "LPSPI0_TRIG (rw) register accessor: LPSPI0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpspi0_trig`] module"] +#[doc(alias = "LPSPI0_TRIG")] +pub type Lpspi0Trig = crate::Reg; +#[doc = "LPSPI0 trigger input connections"] +pub mod lpspi0_trig; +#[doc = "LPSPI1_TRIG (rw) register accessor: LPSPI1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpspi1_trig`] module"] +#[doc(alias = "LPSPI1_TRIG")] +pub type Lpspi1Trig = crate::Reg; +#[doc = "LPSPI1 trigger input connections"] +pub mod lpspi1_trig; +#[doc = "LPUART0 (rw) register accessor: LPUART0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart0`] module"] +#[doc(alias = "LPUART0")] +pub type Lpuart0 = crate::Reg; +#[doc = "LPUART0 trigger input connections"] +pub mod lpuart0; +#[doc = "LPUART1 (rw) register accessor: LPUART1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart1`] module"] +#[doc(alias = "LPUART1")] +pub type Lpuart1 = crate::Reg; +#[doc = "LPUART1 trigger input connections"] +pub mod lpuart1; +#[doc = "LPUART2 (rw) register accessor: LPUART2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart2`] module"] +#[doc(alias = "LPUART2")] +pub type Lpuart2 = crate::Reg; +#[doc = "LPUART2 trigger input connections"] +pub mod lpuart2; +#[doc = "LPUART3 (rw) register accessor: LPUART3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart3`] module"] +#[doc(alias = "LPUART3")] +pub type Lpuart3 = crate::Reg; +#[doc = "LPUART3 trigger input connections"] +pub mod lpuart3; +#[doc = "LPUART4 (rw) register accessor: LPUART4 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart4`] module"] +#[doc(alias = "LPUART4")] +pub type Lpuart4 = crate::Reg; +#[doc = "LPUART4 trigger input connections"] +pub mod lpuart4; +#[doc = "LPUART5 (rw) register accessor: LPUART5 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart5`] module"] +#[doc(alias = "LPUART5")] +pub type Lpuart5 = crate::Reg; +#[doc = "LPUART5 trigger input connections"] +pub mod lpuart5; +#[doc = "FLEXIO_TRIG (rw) register accessor: FlexIO Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flexio_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexio_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexio_trig`] module"] +#[doc(alias = "FLEXIO_TRIG")] +pub type FlexioTrig = crate::Reg; +#[doc = "FlexIO Trigger Input Connections"] +pub mod flexio_trig; +#[doc = "TRIGFIL_PRSC (rw) register accessor: Trigger filter prescaller\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_prsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil_prsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil_prsc`] module"] +#[doc(alias = "TRIGFIL_PRSC")] +pub type TrigfilPrsc = crate::Reg; +#[doc = "Trigger filter prescaller"] +pub mod trigfil_prsc; +#[doc = "TRIGFIL_STAT0 (r) register accessor: Trigger filter stat\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_stat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil_stat0`] module"] +#[doc(alias = "TRIGFIL_STAT0")] +pub type TrigfilStat0 = crate::Reg; +#[doc = "Trigger filter stat"] +pub mod trigfil_stat0; +#[doc = "TRIGFIL (rw) register accessor: TRIGFIL control\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil`] module"] +#[doc(alias = "TRIGFIL")] +pub type Trigfil = crate::Reg; +#[doc = "TRIGFIL control"] +pub mod trigfil; diff --git a/mcxa276-pac/src/inputmux0/adc0_trig.rs b/mcxa276-pac/src/inputmux0/adc0_trig.rs new file mode 100644 index 000000000..c306806ee --- /dev/null +++ b/mcxa276-pac/src/inputmux0/adc0_trig.rs @@ -0,0 +1,782 @@ +#[doc = "Register `ADC0_TRIG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `ADC0_TRIG[%s]` writer"] +pub type W = crate::W; +#[doc = "ADC0 trigger inputs\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: QDC0_POS_MATCH0 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] + Val24 = 24, + #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] + Val25 = 25, + #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: WUU"] + Val31 = 31, + #[doc = "33: AOI1_OUT0 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT1 input is selected"] + Val34 = 34, + #[doc = "35: AOI1_OUT2 input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT3 input is selected"] + Val36 = 36, + #[doc = "37: ADC1_tcomp\\[0\\] input is selected"] + Val37 = 37, + #[doc = "38: ADC1_tcomp\\[1\\] input is selected"] + Val38 = 38, + #[doc = "39: ADC1_tcomp\\[2\\] input is selected"] + Val39 = 39, + #[doc = "40: ADC1_tcomp\\[3\\] input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer3_MAT1 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT0 input is selected"] + Val43 = 43, + #[doc = "44: CTimer4_MAT1 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH0 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH1 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH2 input is selected"] + Val47 = 47, + #[doc = "48: FlexIO CH3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_POS_MATCH0 input is selected"] + Val49 = 49, + #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] + Val57 = 57, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - ADC0 trigger inputs"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 43 => Some(Trigin::Val43), + 44 => Some(Trigin::Val44), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "WUU"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Trigin::Val43 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Trigin::Val44 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } +} +#[doc = "Field `TRIGIN` writer - ADC0 trigger inputs"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "WUU"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Trigin::Val43) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Trigin::Val44) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } +} +impl R { + #[doc = "Bits 0:5 - ADC0 trigger inputs"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - ADC0 trigger inputs"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Adc0TrigSpec; +impl crate::RegisterSpec for Adc0TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc0_trig::R`](R) reader structure"] +impl crate::Readable for Adc0TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`adc0_trig::W`](W) writer structure"] +impl crate::Writable for Adc0TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADC0_TRIG[%s] to value 0x3f"] +impl crate::Resettable for Adc0TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/adc1_trig.rs b/mcxa276-pac/src/inputmux0/adc1_trig.rs new file mode 100644 index 000000000..ca42768f9 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/adc1_trig.rs @@ -0,0 +1,782 @@ +#[doc = "Register `ADC1_TRIG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `ADC1_TRIG[%s]` writer"] +pub type W = crate::W; +#[doc = "ADC1 trigger inputs\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: QDC0_POS_MATCH0 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] + Val24 = 24, + #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] + Val25 = 25, + #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: WUU"] + Val31 = 31, + #[doc = "33: AOI1_OUT0 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT1 input is selected"] + Val34 = 34, + #[doc = "35: AOI1_OUT2 input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT3 input is selected"] + Val36 = 36, + #[doc = "37: ADC0_tcomp\\[0\\] input is selected"] + Val37 = 37, + #[doc = "38: ADC0_tcomp\\[1\\] input is selected"] + Val38 = 38, + #[doc = "39: ADC0_tcomp\\[2\\] input is selected"] + Val39 = 39, + #[doc = "40: ADC0_tcomp\\[3\\] input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer3_MAT1 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT0 input is selected"] + Val43 = 43, + #[doc = "44: CTimer4_MAT1 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH0 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH1 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH2 input is selected"] + Val47 = 47, + #[doc = "48: FlexIO CH3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_POS_MATCH0 input is selected"] + Val49 = 49, + #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] + Val57 = 57, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - ADC1 trigger inputs"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 43 => Some(Trigin::Val43), + 44 => Some(Trigin::Val44), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "WUU"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Trigin::Val43 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Trigin::Val44 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } +} +#[doc = "Field `TRIGIN` writer - ADC1 trigger inputs"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "WUU"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Trigin::Val43) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Trigin::Val44) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } +} +impl R { + #[doc = "Bits 0:5 - ADC1 trigger inputs"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - ADC1 trigger inputs"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Adc1TrigSpec; +impl crate::RegisterSpec for Adc1TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc1_trig::R`](R) reader structure"] +impl crate::Readable for Adc1TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`adc1_trig::W`](W) writer structure"] +impl crate::Writable for Adc1TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADC1_TRIG[%s] to value 0x3f"] +impl crate::Resettable for Adc1TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/adc2_trig.rs b/mcxa276-pac/src/inputmux0/adc2_trig.rs new file mode 100644 index 000000000..d49743efa --- /dev/null +++ b/mcxa276-pac/src/inputmux0/adc2_trig.rs @@ -0,0 +1,782 @@ +#[doc = "Register `ADC2_TRIG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `ADC2_TRIG[%s]` writer"] +pub type W = crate::W; +#[doc = "ADC2 trigger inputs\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: QDC0_POS_MATCH0 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] + Val24 = 24, + #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] + Val25 = 25, + #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: WUU"] + Val31 = 31, + #[doc = "33: AOI1_OUT0 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT1 input is selected"] + Val34 = 34, + #[doc = "35: AOI1_OUT2 input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT3 input is selected"] + Val36 = 36, + #[doc = "37: ADC3_tcomp\\[0\\] input is selected"] + Val37 = 37, + #[doc = "38: ADC3_tcomp\\[1\\] input is selected"] + Val38 = 38, + #[doc = "39: ADC3_tcomp\\[2\\] input is selected"] + Val39 = 39, + #[doc = "40: ADC3_tcomp\\[3\\] input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer3_MAT1 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT0 input is selected"] + Val43 = 43, + #[doc = "44: CTimer4_MAT1 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH0 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH1 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH2 input is selected"] + Val47 = 47, + #[doc = "48: FlexIO CH3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_POS_MATCH0 input is selected"] + Val49 = 49, + #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] + Val57 = 57, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - ADC2 trigger inputs"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 43 => Some(Trigin::Val43), + 44 => Some(Trigin::Val44), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "WUU"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Trigin::Val43 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Trigin::Val44 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } +} +#[doc = "Field `TRIGIN` writer - ADC2 trigger inputs"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "WUU"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Trigin::Val43) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Trigin::Val44) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } +} +impl R { + #[doc = "Bits 0:5 - ADC2 trigger inputs"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - ADC2 trigger inputs"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc2_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc2_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Adc2TrigSpec; +impl crate::RegisterSpec for Adc2TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc2_trig::R`](R) reader structure"] +impl crate::Readable for Adc2TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`adc2_trig::W`](W) writer structure"] +impl crate::Writable for Adc2TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADC2_TRIG[%s] to value 0x3f"] +impl crate::Resettable for Adc2TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/adc3_trig.rs b/mcxa276-pac/src/inputmux0/adc3_trig.rs new file mode 100644 index 000000000..e2fb33988 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/adc3_trig.rs @@ -0,0 +1,782 @@ +#[doc = "Register `ADC3_TRIG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `ADC3_TRIG[%s]` writer"] +pub type W = crate::W; +#[doc = "ADC3 trigger inputs\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: QDC0_POS_MATCH0 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] + Val24 = 24, + #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] + Val25 = 25, + #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: WUU"] + Val31 = 31, + #[doc = "33: AOI1_OUT0 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT1 input is selected"] + Val34 = 34, + #[doc = "35: AOI1_OUT2 input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT3 input is selected"] + Val36 = 36, + #[doc = "37: ADC2_tcomp\\[0\\] input is selected"] + Val37 = 37, + #[doc = "38: ADC2_tcomp\\[1\\] input is selected"] + Val38 = 38, + #[doc = "39: ADC2_tcomp\\[2\\] input is selected"] + Val39 = 39, + #[doc = "40: ADC2_tcomp\\[3\\] input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer3_MAT1 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT0 input is selected"] + Val43 = 43, + #[doc = "44: CTimer4_MAT1 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH0 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH1 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH2 input is selected"] + Val47 = 47, + #[doc = "48: FlexIO CH3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_POS_MATCH0 input is selected"] + Val49 = 49, + #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] + Val57 = 57, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - ADC3 trigger inputs"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 43 => Some(Trigin::Val43), + 44 => Some(Trigin::Val44), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "WUU"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Trigin::Val43 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Trigin::Val44 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } +} +#[doc = "Field `TRIGIN` writer - ADC3 trigger inputs"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "WUU"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Trigin::Val43) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Trigin::Val44) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } +} +impl R { + #[doc = "Bits 0:5 - ADC3 trigger inputs"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - ADC3 trigger inputs"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc3_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc3_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Adc3TrigSpec; +impl crate::RegisterSpec for Adc3TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc3_trig::R`](R) reader structure"] +impl crate::Readable for Adc3TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`adc3_trig::W`](W) writer structure"] +impl crate::Writable for Adc3TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADC3_TRIG[%s] to value 0x3f"] +impl crate::Resettable for Adc3TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/aoi0_input.rs b/mcxa276-pac/src/inputmux0/aoi0_input.rs new file mode 100644 index 000000000..7eb6d0d35 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/aoi0_input.rs @@ -0,0 +1,1302 @@ +#[doc = "Register `AOI0_INPUT[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `AOI0_INPUT[%s]` writer"] +pub type W = crate::W; +#[doc = "AOI0 trigger input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ADC0_tcomp\\[0\\] input is selected"] + Val1 = 1, + #[doc = "2: ADC0_tcomp\\[1\\] input is selected"] + Val2 = 2, + #[doc = "3: ADC0_tcomp\\[2\\] input is selected"] + Val3 = 3, + #[doc = "4: ADC0_tcomp\\[3\\] input is selected"] + Val4 = 4, + #[doc = "5: CMP0_OUT input is selected"] + Val5 = 5, + #[doc = "6: CMP1_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP2_OUT input is selected"] + Val7 = 7, + #[doc = "8: CTimer0_MAT0 input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT1 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT2 input is selected"] + Val10 = 10, + #[doc = "11: CTimer0_MAT3 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT0 input is selected"] + Val12 = 12, + #[doc = "13: CTimer1_MAT1 input is selected"] + Val13 = 13, + #[doc = "14: CTimer1_MAT2 input is selected"] + Val14 = 14, + #[doc = "15: CTimer1_MAT3 input is selected"] + Val15 = 15, + #[doc = "16: CTimer2_MAT0 input is selected"] + Val16 = 16, + #[doc = "17: CTimer2_MAT1 input is selected"] + Val17 = 17, + #[doc = "18: CTimer2_MAT2 input is selected"] + Val18 = 18, + #[doc = "19: CTimer2_MAT3 input is selected"] + Val19 = 19, + #[doc = "20: LPTMR0 input is selected"] + Val20 = 20, + #[doc = "22: QDC0_CMP_FLAG0 input is selected"] + Val22 = 22, + #[doc = "23: QDC0_CMP_FLAG1 input is selected"] + Val23 = 23, + #[doc = "24: QDC0_CMP_FLAG2 input is selected"] + Val24 = 24, + #[doc = "25: QDC0_CMP_FLAG3 input is selected"] + Val25 = 25, + #[doc = "26: QDC0_POS_MATCH0 input is selected"] + Val26 = 26, + #[doc = "27: PWM0_SM0_MUX_TRIG0 0 input is selected"] + Val27 = 27, + #[doc = "28: PWM0_SM0_MUX_TRIG1 input is selected"] + Val28 = 28, + #[doc = "29: PWM0_SM1_MUX_TRIG0 input is selected"] + Val29 = 29, + #[doc = "30: PWM0_SM1_MUX_TRIG1 input is selected"] + Val30 = 30, + #[doc = "31: PWM0_SM2_MUX_TRIG0 input is selected"] + Val31 = 31, + #[doc = "32: PWM0_SM2_MUX_TRIG1 input is selected"] + Val32 = 32, + #[doc = "33: PWM0_SM3_MUX_TRIG0 input is selected"] + Val33 = 33, + #[doc = "34: PWM0_SM3_MUX_TRIG1 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN0 input is selected"] + Val35 = 35, + #[doc = "36: TRIG_IN1 input is selected"] + Val36 = 36, + #[doc = "37: TRIG_IN2 input is selected"] + Val37 = 37, + #[doc = "38: TRIG_IN3 input is selected"] + Val38 = 38, + #[doc = "39: TRIG_IN4 input is selected"] + Val39 = 39, + #[doc = "40: TRIG_IN5 input is selected"] + Val40 = 40, + #[doc = "41: TRIG_IN6 input is selected"] + Val41 = 41, + #[doc = "42: TRIG_IN7 input is selected"] + Val42 = 42, + #[doc = "43: TRIG_IN8 input is selected"] + Val43 = 43, + #[doc = "44: TRIG_IN9 input is selected"] + Val44 = 44, + #[doc = "45: TRIG_IN10 input is selected"] + Val45 = 45, + #[doc = "46: TRIG_IN11 input is selected"] + Val46 = 46, + #[doc = "47: GPIO0 Pin Event Trig 0 input is selected"] + Val47 = 47, + #[doc = "48: GPIO1 Pin Event Trig 0 input is selected"] + Val48 = 48, + #[doc = "49: GPIO2 Pin Event Trig 0 input is selected"] + Val49 = 49, + #[doc = "50: GPIO3 Pin Event Trig 0 input is selected"] + Val50 = 50, + #[doc = "51: GPIO4 Pin Event Trig 0 input is selected"] + Val51 = 51, + #[doc = "52: ADC1_tcomp\\[0\\] input is selected"] + Val52 = 52, + #[doc = "53: ADC1_tcomp\\[1\\] input is selected"] + Val53 = 53, + #[doc = "54: ADC1_tcomp\\[2\\] input is selected"] + Val54 = 54, + #[doc = "55: ADC1_tcomp\\[3\\] input is selected"] + Val55 = 55, + #[doc = "56: CTimer3_MAT0 input is selected"] + Val56 = 56, + #[doc = "57: CTimer3_MAT1 input is selected"] + Val57 = 57, + #[doc = "58: CTimer3_MAT2 input is selected"] + Val58 = 58, + #[doc = "59: CTimer3_MAT3 input is selected"] + Val59 = 59, + #[doc = "60: CTimer4_MAT0 input is selected"] + Val60 = 60, + #[doc = "61: CTimer4_MAT1 input is selected"] + Val61 = 61, + #[doc = "62: CTimer4_MAT2 input is selected"] + Val62 = 62, + #[doc = "63: CTimer4_MAT3 input is selected"] + Val63 = 63, + #[doc = "64: FlexIO CH0 input is selected"] + Val64 = 64, + #[doc = "65: FlexIO CH1 input is selected"] + Val65 = 65, + #[doc = "66: FlexIO CH2 input is selected"] + Val66 = 66, + #[doc = "67: FlexIO CH3 input is selected"] + Val67 = 67, + #[doc = "68: QDC1_CMP_FLAG0 input is selected"] + Val68 = 68, + #[doc = "69: QDC1_CMP_FLAG1 input is selected"] + Val69 = 69, + #[doc = "70: QDC1_CMP_FLAG2 input is selected"] + Val70 = 70, + #[doc = "71: QDC1_CMP_FLAG3 input is selected"] + Val71 = 71, + #[doc = "72: QDC1_POS_MATCH0 input is selected"] + Val72 = 72, + #[doc = "73: PWM1_SM0_MUX_TRIG0 input is selected"] + Val73 = 73, + #[doc = "74: PWM1_SM0_MUX_TRIG1 input is selected"] + Val74 = 74, + #[doc = "75: PWM1_SM1_MUX_TRIG0 input is selected"] + Val75 = 75, + #[doc = "76: PWM1_SM1_MUX_TRIG1 input is selected"] + Val76 = 76, + #[doc = "77: PWM1_SM2_MUX_TRIG0 input is selected"] + Val77 = 77, + #[doc = "78: PWM1_SM2_MUX_TRIG1 input is selected"] + Val78 = 78, + #[doc = "79: PWM1_SM3_MUX_TRIG0 input is selected"] + Val79 = 79, + #[doc = "80: PWM1_SM3_MUX_TRIG1 input is selected"] + Val80 = 80, + #[doc = "81: PWM0_SM0_A_Output"] + Val81 = 81, + #[doc = "82: PWM0_SM0_B_Output"] + Val82 = 82, + #[doc = "83: PWM0_SM1_A_Output"] + Val83 = 83, + #[doc = "84: PWM0_SM1_B_Output"] + Val84 = 84, + #[doc = "85: PWM0_SM2_A_Output"] + Val85 = 85, + #[doc = "86: PWM0_SM2_B_Output"] + Val86 = 86, + #[doc = "87: PWM0_SM3_A_Output"] + Val87 = 87, + #[doc = "88: PWM0_SM3_B_Output"] + Val88 = 88, + #[doc = "89: ADC2_tcomp\\[0\\] input is selected"] + Val89 = 89, + #[doc = "90: ADC2_tcomp\\[1\\] input is selected"] + Val90 = 90, + #[doc = "91: ADC2_tcomp\\[2\\] input is selected"] + Val91 = 91, + #[doc = "92: ADC2_tcomp\\[3\\] input is selected"] + Val92 = 92, + #[doc = "93: ADC3_tcomp\\[0\\] input is selected"] + Val93 = 93, + #[doc = "94: ADC3_tcomp\\[1\\] input is selected"] + Val94 = 94, + #[doc = "95: ADC3_tcomp\\[2\\] input is selected"] + Val95 = 95, + #[doc = "96: ADC3_tcomp\\[3\\] input is selected"] + Val96 = 96, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - AOI0 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + _ => None, + } + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "PWM0_SM0_MUX_TRIG0 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "PWM0_SM0_A_Output"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "PWM0_SM0_B_Output"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "PWM0_SM1_A_Output"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "PWM0_SM1_B_Output"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "PWM0_SM2_A_Output"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "PWM0_SM2_B_Output"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "PWM0_SM3_A_Output"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "PWM0_SM3_B_Output"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } +} +#[doc = "Field `INP` writer - AOI0 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "PWM0_SM0_MUX_TRIG0 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "PWM0_SM0_A_Output"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "PWM0_SM0_B_Output"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "PWM0_SM1_A_Output"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "PWM0_SM1_B_Output"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "PWM0_SM2_A_Output"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "PWM0_SM2_B_Output"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "PWM0_SM3_A_Output"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "PWM0_SM3_B_Output"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } +} +impl R { + #[doc = "Bits 0:6 - AOI0 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - AOI0 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "AOI0 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi0_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi0_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Aoi0InputSpec; +impl crate::RegisterSpec for Aoi0InputSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`aoi0_input::R`](R) reader structure"] +impl crate::Readable for Aoi0InputSpec {} +#[doc = "`write(|w| ..)` method takes [`aoi0_input::W`](W) writer structure"] +impl crate::Writable for Aoi0InputSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets AOI0_INPUT[%s] to value 0x7f"] +impl crate::Resettable for Aoi0InputSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/aoi1_input.rs b/mcxa276-pac/src/inputmux0/aoi1_input.rs new file mode 100644 index 000000000..721b0aba0 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/aoi1_input.rs @@ -0,0 +1,1302 @@ +#[doc = "Register `AOI1_INPUT[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `AOI1_INPUT[%s]` writer"] +pub type W = crate::W; +#[doc = "AOI0 trigger input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ADC0_tcomp\\[0\\] input is selected"] + Val1 = 1, + #[doc = "2: ADC0_tcomp\\[1\\] input is selected"] + Val2 = 2, + #[doc = "3: ADC0_tcomp\\[2\\] input is selected"] + Val3 = 3, + #[doc = "4: ADC0_tcomp\\[3\\] input is selected"] + Val4 = 4, + #[doc = "5: CMP0_OUT input is selected"] + Val5 = 5, + #[doc = "6: CMP1_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP2_OUT input is selected"] + Val7 = 7, + #[doc = "8: CTimer0_MAT0 input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT1 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT2 input is selected"] + Val10 = 10, + #[doc = "11: CTimer0_MAT3 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT0"] + Val12 = 12, + #[doc = "13: CTimer1_MAT1 input is selected"] + Val13 = 13, + #[doc = "14: CTimer1_MAT2 input is selected"] + Val14 = 14, + #[doc = "15: CTimer1_MAT3 input is selected"] + Val15 = 15, + #[doc = "16: CTimer2_MAT0 input is selected"] + Val16 = 16, + #[doc = "17: CTimer2_MAT1 input is selected"] + Val17 = 17, + #[doc = "18: CTimer2_MAT2 input is selected"] + Val18 = 18, + #[doc = "19: CTimer2_MAT3 input is selected"] + Val19 = 19, + #[doc = "20: LPTMR0 input is selected"] + Val20 = 20, + #[doc = "22: QDC0_CMP_FLAG0 input is selected"] + Val22 = 22, + #[doc = "23: QDC0_CMP_FLAG1 input is selected"] + Val23 = 23, + #[doc = "24: QDC0_CMP_FLAG2 input is selected"] + Val24 = 24, + #[doc = "25: QDC0_CMP_FLAG3 input is selected"] + Val25 = 25, + #[doc = "26: QDC0_POS_MATCH0 input is selected"] + Val26 = 26, + #[doc = "27: PWM0_SM0_MUX_TRIG0 input is selected"] + Val27 = 27, + #[doc = "28: PWM0_SM0_MUX_TRIG1 input is selected"] + Val28 = 28, + #[doc = "29: PWM0_SM1_MUX_TRIG0 input is selected"] + Val29 = 29, + #[doc = "30: PWM0_SM1_MUX_TRIG1 input is selected"] + Val30 = 30, + #[doc = "31: PWM0_SM2_MUX_TRIG0 input is selected"] + Val31 = 31, + #[doc = "32: PWM0_SM2_MUX_TRIG1 input is selected"] + Val32 = 32, + #[doc = "33: PWM0_SM3_MUX_TRIG0 input is selected"] + Val33 = 33, + #[doc = "34: PWM0_SM3_MUX_TRIG1 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN0 input is selected"] + Val35 = 35, + #[doc = "36: TRIG_IN1 input is selected"] + Val36 = 36, + #[doc = "37: TRIG_IN2 input is selected"] + Val37 = 37, + #[doc = "38: TRIG_IN3 input is selected"] + Val38 = 38, + #[doc = "39: TRIG_IN4 input is selected"] + Val39 = 39, + #[doc = "40: TRIG_IN5 input is selected"] + Val40 = 40, + #[doc = "41: TRIG_IN6 input is selected"] + Val41 = 41, + #[doc = "42: TRIG_IN7 input is selected"] + Val42 = 42, + #[doc = "43: TRIG_IN8 input is selected"] + Val43 = 43, + #[doc = "44: TRIG_IN9 input is selected"] + Val44 = 44, + #[doc = "45: TRIG_IN10 input is selected"] + Val45 = 45, + #[doc = "46: TRIG_IN11 input is selected"] + Val46 = 46, + #[doc = "47: GPIO0 Pin Event Trig 0 input is selected"] + Val47 = 47, + #[doc = "48: GPIO1 Pin Event Trig 0 input is selected"] + Val48 = 48, + #[doc = "49: GPIO2 Pin Event Trig 0 input is selected"] + Val49 = 49, + #[doc = "50: GPIO3 Pin Event Trig 0 input is selected"] + Val50 = 50, + #[doc = "51: GPIO4 Pin Event Trig 0 input is selected"] + Val51 = 51, + #[doc = "52: ADC1_tcomp\\[0\\] input is selected"] + Val52 = 52, + #[doc = "53: ADC1_tcomp\\[1\\] input is selected"] + Val53 = 53, + #[doc = "54: ADC1_tcomp\\[2\\] input is selected"] + Val54 = 54, + #[doc = "55: ADC1_tcomp\\[3\\] input is selected"] + Val55 = 55, + #[doc = "56: CTimer3_MAT0 input is selected"] + Val56 = 56, + #[doc = "57: CTimer3_MAT1 input is selected"] + Val57 = 57, + #[doc = "58: CTimer3_MAT2 input is selected"] + Val58 = 58, + #[doc = "59: CTimer3_MAT3 input is selected"] + Val59 = 59, + #[doc = "60: CTimer4_MAT0 input is selected"] + Val60 = 60, + #[doc = "61: CTimer4_MAT1 input is selected"] + Val61 = 61, + #[doc = "62: CTimer4_MAT2 input is selected"] + Val62 = 62, + #[doc = "63: CTimer4_MAT3 input is selected"] + Val63 = 63, + #[doc = "64: FlexIO CH0 input is selected"] + Val64 = 64, + #[doc = "65: FlexIO CH1 input is selected"] + Val65 = 65, + #[doc = "66: FlexIO CH2 input is selected"] + Val66 = 66, + #[doc = "67: FlexIO CH3 input is selected"] + Val67 = 67, + #[doc = "68: QDC1_CMP_FLAG0 input is selected"] + Val68 = 68, + #[doc = "69: QDC1_CMP_FLAG1 input is selected"] + Val69 = 69, + #[doc = "70: QDC1_CMP_FLAG2 input is selected"] + Val70 = 70, + #[doc = "71: QDC1_CMP_FLAG3 input is selected"] + Val71 = 71, + #[doc = "72: QDC1_POS_MATCH0 input is selected"] + Val72 = 72, + #[doc = "73: PWM1_SM0_MUX_TRIG0 input is selected"] + Val73 = 73, + #[doc = "74: PWM1_SM0_MUX_TRIG1 input is selected"] + Val74 = 74, + #[doc = "75: PWM1_SM1_MUX_TRIG0 input is selected"] + Val75 = 75, + #[doc = "76: PWM1_SM1_MUX_TRIG1 input is selected"] + Val76 = 76, + #[doc = "77: PWM1_SM2_MUX_TRIG0 input is selected"] + Val77 = 77, + #[doc = "78: PWM1_SM2_MUX_TRIG1 input is selected"] + Val78 = 78, + #[doc = "79: PWM1_SM3_MUX_TRIG0 input is selected"] + Val79 = 79, + #[doc = "80: PWM1_SM3_MUX_TRIG1 input is selected"] + Val80 = 80, + #[doc = "81: PWM0_SM0_A_Output"] + Val81 = 81, + #[doc = "82: PWM0_SM0_B_Output"] + Val82 = 82, + #[doc = "83: PWM0_SM1_A_Output"] + Val83 = 83, + #[doc = "84: PWM0_SM1_B_Output"] + Val84 = 84, + #[doc = "85: PWM0_SM2_A_Output"] + Val85 = 85, + #[doc = "86: PWM0_SM2_B_Output"] + Val86 = 86, + #[doc = "87: PWM0_SM3_A_Output"] + Val87 = 87, + #[doc = "88: PWM0_SM3_B_Output"] + Val88 = 88, + #[doc = "89: ADC2_tcomp\\[0\\] input is selected"] + Val89 = 89, + #[doc = "90: ADC2_tcomp\\[1\\] input is selected"] + Val90 = 90, + #[doc = "91: ADC2_tcomp\\[2\\] input is selected"] + Val91 = 91, + #[doc = "92: ADC2_tcomp\\[3\\] input is selected"] + Val92 = 92, + #[doc = "93: ADC3_tcomp\\[0\\] input is selected"] + Val93 = 93, + #[doc = "94: ADC3_tcomp\\[1\\] input is selected"] + Val94 = 94, + #[doc = "95: ADC3_tcomp\\[2\\] input is selected"] + Val95 = 95, + #[doc = "96: ADC3_tcomp\\[3\\] input is selected"] + Val96 = 96, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - AOI0 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + _ => None, + } + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "PWM0_SM0_A_Output"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "PWM0_SM0_B_Output"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "PWM0_SM1_A_Output"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "PWM0_SM1_B_Output"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "PWM0_SM2_A_Output"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "PWM0_SM2_B_Output"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "PWM0_SM3_A_Output"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "PWM0_SM3_B_Output"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } +} +#[doc = "Field `INP` writer - AOI0 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "PWM0_SM0_A_Output"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "PWM0_SM0_B_Output"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "PWM0_SM1_A_Output"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "PWM0_SM1_B_Output"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "PWM0_SM2_A_Output"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "PWM0_SM2_B_Output"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "PWM0_SM3_A_Output"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "PWM0_SM3_B_Output"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } +} +impl R { + #[doc = "Bits 0:6 - AOI0 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - AOI0 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "AOI1 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi1_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi1_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Aoi1InputSpec; +impl crate::RegisterSpec for Aoi1InputSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`aoi1_input::R`](R) reader structure"] +impl crate::Readable for Aoi1InputSpec {} +#[doc = "`write(|w| ..)` method takes [`aoi1_input::W`](W) writer structure"] +impl crate::Writable for Aoi1InputSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets AOI1_INPUT[%s] to value 0x7f"] +impl crate::Resettable for Aoi1InputSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/cmp0_trig.rs b/mcxa276-pac/src/inputmux0/cmp0_trig.rs new file mode 100644 index 000000000..5c5fd4337 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/cmp0_trig.rs @@ -0,0 +1,652 @@ +#[doc = "Register `CMP0_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `CMP0_TRIG` writer"] +pub type W = crate::W; +#[doc = "CMP0 input trigger\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP1_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP2_OUT input is selected"] + Val7 = 7, + #[doc = "8: CTimer0_MAT0 input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer1_MAT0"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer2_MAT0 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: LPTMR0 input is selected"] + Val14 = 14, + #[doc = "16: QDC0_POS_MATCH0"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG0 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM0_MUX_TRIG1 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG0 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_MUX_TRIG1 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG0 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_MUX_TRIG1 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] + Val23 = 23, + #[doc = "24: PWM0_SM3_MUX_TRIG1 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "39: CTimer3_MAT0"] + Val39 = 39, + #[doc = "40: CTimer3_MAT1"] + Val40 = 40, + #[doc = "41: CTimer4_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT1 input is selected"] + Val42 = 42, + #[doc = "47: QDC1_POS_MATCH0 input is selected"] + Val47 = 47, + #[doc = "48: PWM1_SM0_MUX_TRIG0 input is selected"] + Val48 = 48, + #[doc = "49: PWM1_SM0_MUX_TRIG1 input is selected"] + Val49 = 49, + #[doc = "50: PWM1_SM1_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM1_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM2_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM2_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM3_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] + Val55 = 55, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - CMP0 input trigger"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_POS_MATCH0"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "CTimer3_MAT0"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "CTimer3_MAT1"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } +} +#[doc = "Field `TRIGIN` writer - CMP0 input trigger"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_POS_MATCH0"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "CTimer3_MAT0"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "CTimer3_MAT1"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } +} +impl R { + #[doc = "Bits 0:5 - CMP0 input trigger"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - CMP0 input trigger"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "CMP0 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmp0TrigSpec; +impl crate::RegisterSpec for Cmp0TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmp0_trig::R`](R) reader structure"] +impl crate::Readable for Cmp0TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`cmp0_trig::W`](W) writer structure"] +impl crate::Writable for Cmp0TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMP0_TRIG to value 0x3f"] +impl crate::Resettable for Cmp0TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/cmp1_trig.rs b/mcxa276-pac/src/inputmux0/cmp1_trig.rs new file mode 100644 index 000000000..a96b98418 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/cmp1_trig.rs @@ -0,0 +1,652 @@ +#[doc = "Register `CMP1_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `CMP1_TRIG` writer"] +pub type W = crate::W; +#[doc = "CMP1 input trigger\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP2_OUT input is selected"] + Val7 = 7, + #[doc = "8: CTimer0_MAT0 input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer1_MAT0"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer2_MAT0 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: LPTMR0 input is selected"] + Val14 = 14, + #[doc = "16: QDC0_POS_MATCH0"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG0 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM0_MUX_TRIG1 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG0 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_MUX_TRIG1 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG0 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_MUX_TRIG1 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] + Val23 = 23, + #[doc = "24: PWM0_SM3_MUX_TRIG1 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "39: CTimer3_MAT0"] + Val39 = 39, + #[doc = "40: CTimer3_MAT1"] + Val40 = 40, + #[doc = "41: CTimer4_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT1 input is selected"] + Val42 = 42, + #[doc = "47: QDC1_POS_MATCH0 input is selected"] + Val47 = 47, + #[doc = "48: PWM1_SM0_MUX_TRIG0 input is selected"] + Val48 = 48, + #[doc = "49: PWM1_SM0_MUX_TRIG1 input is selected"] + Val49 = 49, + #[doc = "50: PWM1_SM1_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM1_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM2_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM2_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM3_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] + Val55 = 55, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - CMP1 input trigger"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_POS_MATCH0"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "CTimer3_MAT0"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "CTimer3_MAT1"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } +} +#[doc = "Field `TRIGIN` writer - CMP1 input trigger"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_POS_MATCH0"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "CTimer3_MAT0"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "CTimer3_MAT1"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } +} +impl R { + #[doc = "Bits 0:5 - CMP1 input trigger"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - CMP1 input trigger"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "CMP1 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmp1TrigSpec; +impl crate::RegisterSpec for Cmp1TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmp1_trig::R`](R) reader structure"] +impl crate::Readable for Cmp1TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`cmp1_trig::W`](W) writer structure"] +impl crate::Writable for Cmp1TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMP1_TRIG to value 0x3f"] +impl crate::Resettable for Cmp1TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/cmp2_trig.rs b/mcxa276-pac/src/inputmux0/cmp2_trig.rs new file mode 100644 index 000000000..b8988a4de --- /dev/null +++ b/mcxa276-pac/src/inputmux0/cmp2_trig.rs @@ -0,0 +1,652 @@ +#[doc = "Register `CMP2_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `CMP2_TRIG` writer"] +pub type W = crate::W; +#[doc = "CMP2 input trigger\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CTimer0_MAT0 input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer1_MAT0"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer2_MAT0 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: LPTMR0 input is selected"] + Val14 = 14, + #[doc = "16: QDC0_POS_MATCH0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG0 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM0_MUX_TRIG1 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG0 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_MUX_TRIG1 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG0 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_MUX_TRIG1 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] + Val23 = 23, + #[doc = "24: PWM0_SM3_MUX_TRIG1 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "39: CTimer3_MAT0"] + Val39 = 39, + #[doc = "40: CTimer3_MAT1"] + Val40 = 40, + #[doc = "41: CTimer4_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT1 input is selected"] + Val42 = 42, + #[doc = "47: QDC1_POS_MATCH0 input is selected"] + Val47 = 47, + #[doc = "48: PWM1_SM0_MUX_TRIG0 input is selected"] + Val48 = 48, + #[doc = "49: PWM1_SM0_MUX_TRIG1 input is selected"] + Val49 = 49, + #[doc = "50: PWM1_SM1_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM1_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM2_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM2_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM3_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] + Val55 = 55, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - CMP2 input trigger"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "CTimer3_MAT0"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "CTimer3_MAT1"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } +} +#[doc = "Field `TRIGIN` writer - CMP2 input trigger"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer1_MAT0"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "CTimer3_MAT0"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "CTimer3_MAT1"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } +} +impl R { + #[doc = "Bits 0:5 - CMP2 input trigger"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - CMP2 input trigger"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "CMP2 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp2_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp2_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cmp2TrigSpec; +impl crate::RegisterSpec for Cmp2TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmp2_trig::R`](R) reader structure"] +impl crate::Readable for Cmp2TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`cmp2_trig::W`](W) writer structure"] +impl crate::Writable for Cmp2TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMP2_TRIG to value 0x3f"] +impl crate::Resettable for Cmp2TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/ctimer0cap.rs b/mcxa276-pac/src/inputmux0/ctimer0cap.rs new file mode 100644 index 000000000..892ab6d6f --- /dev/null +++ b/mcxa276-pac/src/inputmux0/ctimer0cap.rs @@ -0,0 +1,1471 @@ +#[doc = "Register `CTIMER0CAP[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `CTIMER0CAP[%s]` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER0\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer1_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer1_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer1_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer2_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer2_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer2_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer3_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer3_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer3_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM3_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER0"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER0"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER0"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER0"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer0cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer0cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctimer0capSpec; +impl crate::RegisterSpec for Ctimer0capSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctimer0cap::R`](R) reader structure"] +impl crate::Readable for Ctimer0capSpec {} +#[doc = "`write(|w| ..)` method takes [`ctimer0cap::W`](W) writer structure"] +impl crate::Writable for Ctimer0capSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTIMER0CAP[%s] to value 0x7f"] +impl crate::Resettable for Ctimer0capSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/ctimer1cap.rs b/mcxa276-pac/src/inputmux0/ctimer1cap.rs new file mode 100644 index 000000000..1752e1cb3 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/ctimer1cap.rs @@ -0,0 +1,1471 @@ +#[doc = "Register `CTIMER1CAP[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `CTIMER1CAP[%s]` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER1\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer2_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer2_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer2_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer3_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer3_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer3_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER1"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER1"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER1"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER1"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer1cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer1cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctimer1capSpec; +impl crate::RegisterSpec for Ctimer1capSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctimer1cap::R`](R) reader structure"] +impl crate::Readable for Ctimer1capSpec {} +#[doc = "`write(|w| ..)` method takes [`ctimer1cap::W`](W) writer structure"] +impl crate::Writable for Ctimer1capSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTIMER1CAP[%s] to value 0x7f"] +impl crate::Resettable for Ctimer1capSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/ctimer2cap.rs b/mcxa276-pac/src/inputmux0/ctimer2cap.rs new file mode 100644 index 000000000..14ba36d74 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/ctimer2cap.rs @@ -0,0 +1,1471 @@ +#[doc = "Register `CTIMER2CAP[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `CTIMER2CAP[%s]` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER2\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer1_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer1_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer1_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer3_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer3_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer3_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER2"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER2"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER2"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER2"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer2cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer2cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctimer2capSpec; +impl crate::RegisterSpec for Ctimer2capSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctimer2cap::R`](R) reader structure"] +impl crate::Readable for Ctimer2capSpec {} +#[doc = "`write(|w| ..)` method takes [`ctimer2cap::W`](W) writer structure"] +impl crate::Writable for Ctimer2capSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTIMER2CAP[%s] to value 0x7f"] +impl crate::Resettable for Ctimer2capSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/ctimer3cap.rs b/mcxa276-pac/src/inputmux0/ctimer3cap.rs new file mode 100644 index 000000000..6fe3703ec --- /dev/null +++ b/mcxa276-pac/src/inputmux0/ctimer3cap.rs @@ -0,0 +1,1627 @@ +#[doc = "Register `CTIMER3CAP[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `CTIMER3CAP[%s]` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER3\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer1_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer1_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer1_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer2_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer2_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer2_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, + #[doc = "113: TRIG_IN0 input is selected"] + Val113 = 113, + #[doc = "114: TRIG_IN1 input is selected"] + Val114 = 114, + #[doc = "115: TRIG_IN2 input is selected"] + Val115 = 115, + #[doc = "116: TRIG_IN3 input is selected"] + Val116 = 116, + #[doc = "117: TRIG_IN4 input is selected"] + Val117 = 117, + #[doc = "118: TRIG_IN5 input is selected"] + Val118 = 118, + #[doc = "119: TRIG_IN6 input is selected"] + Val119 = 119, + #[doc = "120: TRIG_IN7 input is selected"] + Val120 = 120, + #[doc = "121: TRIG_IN8 input is selected"] + Val121 = 121, + #[doc = "122: TRIG_IN9 input is selected"] + Val122 = 122, + #[doc = "123: TRIG_IN10 input is selected"] + Val123 = 123, + #[doc = "124: TRIG_IN11 input is selected"] + Val124 = 124, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER3"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + 113 => Some(Inp::Val113), + 114 => Some(Inp::Val114), + 115 => Some(Inp::Val115), + 116 => Some(Inp::Val116), + 117 => Some(Inp::Val117), + 118 => Some(Inp::Val118), + 119 => Some(Inp::Val119), + 120 => Some(Inp::Val120), + 121 => Some(Inp::Val121), + 122 => Some(Inp::Val122), + 123 => Some(Inp::Val123), + 124 => Some(Inp::Val124), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val113(&self) -> bool { + *self == Inp::Val113 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val114(&self) -> bool { + *self == Inp::Val114 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val115(&self) -> bool { + *self == Inp::Val115 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val116(&self) -> bool { + *self == Inp::Val116 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val117(&self) -> bool { + *self == Inp::Val117 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val118(&self) -> bool { + *self == Inp::Val118 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val119(&self) -> bool { + *self == Inp::Val119 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val120(&self) -> bool { + *self == Inp::Val120 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val121(&self) -> bool { + *self == Inp::Val121 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val122(&self) -> bool { + *self == Inp::Val122 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val123(&self) -> bool { + *self == Inp::Val123 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val124(&self) -> bool { + *self == Inp::Val124 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER3"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val113(self) -> &'a mut crate::W { + self.variant(Inp::Val113) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val114(self) -> &'a mut crate::W { + self.variant(Inp::Val114) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val115(self) -> &'a mut crate::W { + self.variant(Inp::Val115) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val116(self) -> &'a mut crate::W { + self.variant(Inp::Val116) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val117(self) -> &'a mut crate::W { + self.variant(Inp::Val117) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val118(self) -> &'a mut crate::W { + self.variant(Inp::Val118) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val119(self) -> &'a mut crate::W { + self.variant(Inp::Val119) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val120(self) -> &'a mut crate::W { + self.variant(Inp::Val120) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val121(self) -> &'a mut crate::W { + self.variant(Inp::Val121) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val122(self) -> &'a mut crate::W { + self.variant(Inp::Val122) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val123(self) -> &'a mut crate::W { + self.variant(Inp::Val123) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val124(self) -> &'a mut crate::W { + self.variant(Inp::Val124) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER3"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER3"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer3cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer3cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctimer3capSpec; +impl crate::RegisterSpec for Ctimer3capSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctimer3cap::R`](R) reader structure"] +impl crate::Readable for Ctimer3capSpec {} +#[doc = "`write(|w| ..)` method takes [`ctimer3cap::W`](W) writer structure"] +impl crate::Writable for Ctimer3capSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTIMER3CAP[%s] to value 0x7f"] +impl crate::Resettable for Ctimer3capSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/ctimer4cap.rs b/mcxa276-pac/src/inputmux0/ctimer4cap.rs new file mode 100644 index 000000000..e5fa7f6e4 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/ctimer4cap.rs @@ -0,0 +1,1627 @@ +#[doc = "Register `CTIMER4CAP[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `CTIMER4CAP[%s]` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER4\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer1_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer1_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer1_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer2_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer2_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer2_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer3_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer3_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer3_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, + #[doc = "113: TRIG_IN0 input is selected"] + Val113 = 113, + #[doc = "114: TRIG_IN1 input is selected"] + Val114 = 114, + #[doc = "115: TRIG_IN2 input is selected"] + Val115 = 115, + #[doc = "116: TRIG_IN3 input is selected"] + Val116 = 116, + #[doc = "117: TRIG_IN4 input is selected"] + Val117 = 117, + #[doc = "118: TRIG_IN5 input is selected"] + Val118 = 118, + #[doc = "119: TRIG_IN6 input is selected"] + Val119 = 119, + #[doc = "120: TRIG_IN7 input is selected"] + Val120 = 120, + #[doc = "121: TRIG_IN8 input is selected"] + Val121 = 121, + #[doc = "122: TRIG_IN9 input is selected"] + Val122 = 122, + #[doc = "123: TRIG_IN10 input is selected"] + Val123 = 123, + #[doc = "124: TRIG_IN11 input is selected"] + Val124 = 124, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER4"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + 113 => Some(Inp::Val113), + 114 => Some(Inp::Val114), + 115 => Some(Inp::Val115), + 116 => Some(Inp::Val116), + 117 => Some(Inp::Val117), + 118 => Some(Inp::Val118), + 119 => Some(Inp::Val119), + 120 => Some(Inp::Val120), + 121 => Some(Inp::Val121), + 122 => Some(Inp::Val122), + 123 => Some(Inp::Val123), + 124 => Some(Inp::Val124), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val113(&self) -> bool { + *self == Inp::Val113 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val114(&self) -> bool { + *self == Inp::Val114 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val115(&self) -> bool { + *self == Inp::Val115 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val116(&self) -> bool { + *self == Inp::Val116 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val117(&self) -> bool { + *self == Inp::Val117 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val118(&self) -> bool { + *self == Inp::Val118 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val119(&self) -> bool { + *self == Inp::Val119 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val120(&self) -> bool { + *self == Inp::Val120 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val121(&self) -> bool { + *self == Inp::Val121 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val122(&self) -> bool { + *self == Inp::Val122 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val123(&self) -> bool { + *self == Inp::Val123 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val124(&self) -> bool { + *self == Inp::Val124 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER4"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val113(self) -> &'a mut crate::W { + self.variant(Inp::Val113) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val114(self) -> &'a mut crate::W { + self.variant(Inp::Val114) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val115(self) -> &'a mut crate::W { + self.variant(Inp::Val115) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val116(self) -> &'a mut crate::W { + self.variant(Inp::Val116) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val117(self) -> &'a mut crate::W { + self.variant(Inp::Val117) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val118(self) -> &'a mut crate::W { + self.variant(Inp::Val118) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val119(self) -> &'a mut crate::W { + self.variant(Inp::Val119) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val120(self) -> &'a mut crate::W { + self.variant(Inp::Val120) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val121(self) -> &'a mut crate::W { + self.variant(Inp::Val121) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val122(self) -> &'a mut crate::W { + self.variant(Inp::Val122) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val123(self) -> &'a mut crate::W { + self.variant(Inp::Val123) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val124(self) -> &'a mut crate::W { + self.variant(Inp::Val124) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER4"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER4"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer4cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer4cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctimer4capSpec; +impl crate::RegisterSpec for Ctimer4capSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctimer4cap::R`](R) reader structure"] +impl crate::Readable for Ctimer4capSpec {} +#[doc = "`write(|w| ..)` method takes [`ctimer4cap::W`](W) writer structure"] +impl crate::Writable for Ctimer4capSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTIMER4CAP[%s] to value 0x7f"] +impl crate::Resettable for Ctimer4capSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/dac0_trig.rs b/mcxa276-pac/src/inputmux0/dac0_trig.rs new file mode 100644 index 000000000..e2869025c --- /dev/null +++ b/mcxa276-pac/src/inputmux0/dac0_trig.rs @@ -0,0 +1,652 @@ +#[doc = "Register `DAC0_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `DAC0_TRIG` writer"] +pub type W = crate::W; +#[doc = "DAC0 trigger input\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "18: PWM0_SM0_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM0_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM1_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM1_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: WUU input is selected"] + Val31 = 31, + #[doc = "33: AOI1_OUT0 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT1 input is selected"] + Val34 = 34, + #[doc = "35: AOI1_OUT2 input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT3 input is selected"] + Val36 = 36, + #[doc = "37: ADC0_tcomp\\[0\\] input is selected"] + Val37 = 37, + #[doc = "38: ADC0_tcomp\\[1\\] input is selected"] + Val38 = 38, + #[doc = "39: ADC1_tcomp\\[0\\] input is selected"] + Val39 = 39, + #[doc = "40: ADC1_tcomp\\[1\\] input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT0 input is selected"] + Val41 = 41, + #[doc = "42: CTimer3_MAT1 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT0 input is selected"] + Val43 = 43, + #[doc = "44: CTimer4_MAT1 input is selected"] + Val44 = 44, + #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] + Val50 = 50, + #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] + Val51 = 51, + #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] + Val52 = 52, + #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] + Val53 = 53, + #[doc = "58: ADC2_tcomp\\[0\\] input is selected"] + Val58 = 58, + #[doc = "59: ADC2_tcomp\\[1\\] input is selected"] + Val59 = 59, + #[doc = "60: ADC3_tcomp\\[0\\] input is selected"] + Val60 = 60, + #[doc = "61: ADC3_tcomp\\[1\\] input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - DAC0 trigger input"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 41 => Some(Trigin::Val41), + 42 => Some(Trigin::Val42), + 43 => Some(Trigin::Val43), + 44 => Some(Trigin::Val44), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Trigin::Val41 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Trigin::Val42 + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Trigin::Val43 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Trigin::Val44 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - DAC0 trigger input"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Trigin::Val41) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Trigin::Val42) + } + #[doc = "CTimer4_MAT0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Trigin::Val43) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Trigin::Val44) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - DAC0 trigger input"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - DAC0 trigger input"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "DAC0 Trigger input connections.\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dac0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dac0TrigSpec; +impl crate::RegisterSpec for Dac0TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dac0_trig::R`](R) reader structure"] +impl crate::Readable for Dac0TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`dac0_trig::W`](W) writer structure"] +impl crate::Writable for Dac0TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DAC0_TRIG to value 0x3f"] +impl crate::Resettable for Dac0TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/ext_trig.rs b/mcxa276-pac/src/inputmux0/ext_trig.rs new file mode 100644 index 000000000..28a3c7cfb --- /dev/null +++ b/mcxa276-pac/src/inputmux0/ext_trig.rs @@ -0,0 +1,288 @@ +#[doc = "Register `EXT_TRIG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_TRIG[%s]` writer"] +pub type W = crate::W; +#[doc = "EXT trigger input connections\n\nValue on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: LPUART0 ipp_do_lpuart_txd input is selected"] + Val9 = 9, + #[doc = "10: LPUART1 ipp_do_lpuart_txd input is selected"] + Val10 = 10, + #[doc = "11: LPUART2 ipp_do_lpuart_txd input is selected"] + Val11 = 11, + #[doc = "12: LPUART3 ipp_do_lpuart_txd input is selected"] + Val12 = 12, + #[doc = "13: LPUART4 ipp_do_lpuart_txd input is selected"] + Val13 = 13, + #[doc = "14: AOI1_OUT0 input is selected"] + Val14 = 14, + #[doc = "15: AOI1_OUT1 input is selected"] + Val15 = 15, + #[doc = "16: AOI1_OUT2 input is selected"] + Val16 = 16, + #[doc = "17: RTC_1Hz_CLK input is selected"] + Val17 = 17, + #[doc = "18: LPUART5 ipp_do_lpuart_txd input is selected"] + Val18 = 18, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - EXT trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "LPUART0 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "LPUART1 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "LPUART2 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "LPUART3 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "LPUART4 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "RTC_1Hz_CLK input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "LPUART5 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } +} +#[doc = "Field `INP` writer - EXT trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 5, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "LPUART0 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "LPUART1 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "LPUART2 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "LPUART3 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "LPUART4 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "RTC_1Hz_CLK input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "LPUART5 ipp_do_lpuart_txd input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } +} +impl R { + #[doc = "Bits 0:4 - EXT trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - EXT trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "EXT trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ExtTrigSpec; +impl crate::RegisterSpec for ExtTrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_trig::R`](R) reader structure"] +impl crate::Readable for ExtTrigSpec {} +#[doc = "`write(|w| ..)` method takes [`ext_trig::W`](W) writer structure"] +impl crate::Writable for ExtTrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EXT_TRIG[%s] to value 0x1f"] +impl crate::Resettable for ExtTrigSpec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs new file mode 100644 index 000000000..0276feac7 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_FAULT[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_FAULT[%s]` writer"] +pub type W = crate::W; +#[doc = "FAULT input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - FAULT input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - FAULT input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - FAULT input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - FAULT input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_fault::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_fault::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0FaultSpec; +impl crate::RegisterSpec for FlexPwm0FaultSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_fault::R`](R) reader structure"] +impl crate::Readable for FlexPwm0FaultSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_fault::W`](W) writer structure"] +impl crate::Writable for FlexPwm0FaultSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_FAULT[%s] to value 0x3f"] +impl crate::Resettable for FlexPwm0FaultSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_force.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_force.rs new file mode 100644 index 000000000..8f8e675ef --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_force.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_FORCE` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_FORCE` writer"] +pub type W = crate::W; +#[doc = "Trigger input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - Trigger input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Trigger input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_force::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_force::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0ForceSpec; +impl crate::RegisterSpec for FlexPwm0ForceSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_force::R`](R) reader structure"] +impl crate::Readable for FlexPwm0ForceSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_force::W`](W) writer structure"] +impl crate::Writable for FlexPwm0ForceSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_FORCE to value 0x3f"] +impl crate::Resettable for FlexPwm0ForceSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs new file mode 100644 index 000000000..aa291e59a --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM0_EXTA0` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM0_EXTA0` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm0Exta0Spec; +impl crate::RegisterSpec for FlexPwm0Sm0Exta0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm0_exta0::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm0Exta0Spec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm0_exta0::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm0Exta0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM0_EXTA0 to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm0Exta0Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs new file mode 100644 index 000000000..5f7151478 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM0_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM0_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm0ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm0Sm0ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm0_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm0ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm0_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm0ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM0_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm0ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs new file mode 100644 index 000000000..4100e5e16 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM1_EXTA` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM1_EXTA` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm1ExtaSpec; +impl crate::RegisterSpec for FlexPwm0Sm1ExtaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm1_exta::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm1ExtaSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm1_exta::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm1ExtaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM1_EXTA to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm1ExtaSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs new file mode 100644 index 000000000..2d0d0474f --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM1_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM1_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm1ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm0Sm1ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm1_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm1ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm1_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm1ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM1_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm1ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs new file mode 100644 index 000000000..19fe1f3d0 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM2_EXTA` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM2_EXTA` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm2ExtaSpec; +impl crate::RegisterSpec for FlexPwm0Sm2ExtaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm2_exta::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm2ExtaSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm2_exta::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm2ExtaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM2_EXTA to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm2ExtaSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs new file mode 100644 index 000000000..dff963e90 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM2_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM2_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm2ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm0Sm2ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm2_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm2ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm2_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm2ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM2_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm2ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs new file mode 100644 index 000000000..5c0c50075 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM3_EXTA0` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM3_EXTA0` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm3Exta0Spec; +impl crate::RegisterSpec for FlexPwm0Sm3Exta0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm3_exta0::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm3Exta0Spec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm3_exta0::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm3Exta0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM3_EXTA0 to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm3Exta0Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs new file mode 100644 index 000000000..4799815bd --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM0_SM3_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM0_SM3_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm0Sm3ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm0Sm3ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm0_sm3_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm0Sm3ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm3_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm0Sm3ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM0_SM3_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm0Sm3ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs new file mode 100644 index 000000000..bc1379279 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_FAULT[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_FAULT[%s]` writer"] +pub type W = crate::W; +#[doc = "FAULT input connections for PWM1\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - FAULT input connections for PWM1"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - FAULT input connections for PWM1"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - FAULT input connections for PWM1"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - FAULT input connections for PWM1"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_fault::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_fault::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1FaultSpec; +impl crate::RegisterSpec for FlexPwm1FaultSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_fault::R`](R) reader structure"] +impl crate::Readable for FlexPwm1FaultSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_fault::W`](W) writer structure"] +impl crate::Writable for FlexPwm1FaultSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_FAULT[%s] to value 0x3f"] +impl crate::Resettable for FlexPwm1FaultSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_force.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_force.rs new file mode 100644 index 000000000..cafcc6a3e --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_force.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_FORCE` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_FORCE` writer"] +pub type W = crate::W; +#[doc = "Trigger input connections for PWM1\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM1"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM1"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - Trigger input connections for PWM1"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Trigger input connections for PWM1"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_force::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_force::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1ForceSpec; +impl crate::RegisterSpec for FlexPwm1ForceSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_force::R`](R) reader structure"] +impl crate::Readable for FlexPwm1ForceSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_force::W`](W) writer structure"] +impl crate::Writable for FlexPwm1ForceSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_FORCE to value 0x3f"] +impl crate::Resettable for FlexPwm1ForceSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs new file mode 100644 index 000000000..40b9d8785 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM0_EXTA0` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM0_EXTA0` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm0Exta0Spec; +impl crate::RegisterSpec for FlexPwm1Sm0Exta0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm0_exta0::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm0Exta0Spec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm0_exta0::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm0Exta0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM0_EXTA0 to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm0Exta0Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs new file mode 100644 index 000000000..f1aa07af4 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM0_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM0_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm0ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm1Sm0ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm0_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm0ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm0_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm0ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM0_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm0ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs new file mode 100644 index 000000000..0e1937dba --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM1_EXTA` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM1_EXTA` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm1ExtaSpec; +impl crate::RegisterSpec for FlexPwm1Sm1ExtaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm1_exta::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm1ExtaSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm1_exta::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm1ExtaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM1_EXTA to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm1ExtaSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs new file mode 100644 index 000000000..112ec4965 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM1_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM1_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm1ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm1Sm1ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm1_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm1ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm1_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm1ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM1_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm1ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs new file mode 100644 index 000000000..f2e03e309 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM2_EXTA` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM2_EXTA` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm2ExtaSpec; +impl crate::RegisterSpec for FlexPwm1Sm2ExtaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm2_exta::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm2ExtaSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm2_exta::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm2ExtaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM2_EXTA to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm2ExtaSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs new file mode 100644 index 000000000..d11de8a73 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM2_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM2_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm2ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm1Sm2ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm2_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm2ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm2_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm2ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM2_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm2ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs new file mode 100644 index 000000000..7b3ba661e --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM3_EXTA0` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM3_EXTA0` writer"] +pub type W = crate::W; +#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTA input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm3Exta0Spec; +impl crate::RegisterSpec for FlexPwm1Sm3Exta0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm3_exta0::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm3Exta0Spec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm3_exta0::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm3Exta0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM3_EXTA0 to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm3Exta0Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs new file mode 100644 index 000000000..45f16c66c --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs @@ -0,0 +1,808 @@ +#[doc = "Register `FlexPWM1_SM3_EXTSYNC` reader"] +pub type R = crate::R; +#[doc = "Register `FlexPWM1_SM3_EXTSYNC` writer"] +pub type W = crate::W; +#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: QDC0_CMP_FLAG0 input is selected"] + Val15 = 15, + #[doc = "16: QDC0_CMP_FLAG1 input is selected"] + Val16 = 16, + #[doc = "17: QDC0_CMP_FLAG2 input is selected"] + Val17 = 17, + #[doc = "18: QDC0_CMP_FLAG3 input is selected"] + Val18 = 18, + #[doc = "19: QDC0_POS_MATCH0 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN0 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN1 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN2 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN3 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN4 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN5 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN6 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN7 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN8 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN9 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN10 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN11 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT0 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT1 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT2 input is selected"] + Val39 = 39, + #[doc = "40: AOI1_OUT3 input is selected"] + Val40 = 40, + #[doc = "45: CTimer3_MAT2 input is selected"] + Val45 = 45, + #[doc = "46: CTimer3_MAT3 input is selected"] + Val46 = 46, + #[doc = "47: CTimer4_MAT2 input is selected"] + Val47 = 47, + #[doc = "48: CTimer4_MAT3 input is selected"] + Val48 = 48, + #[doc = "49: QDC1_CMP_FLAG0 input is selected"] + Val49 = 49, + #[doc = "50: QDC1_CMP_FLAG1 input is selected"] + Val50 = 50, + #[doc = "51: QDC1_CMP_FLAG2 input is selected"] + Val51 = 51, + #[doc = "52: QDC1_CMP_FLAG3 input is selected"] + Val52 = 52, + #[doc = "53: QDC1_POS_MATCH0 input is selected"] + Val53 = 53, + #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] + Val54 = 54, + #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] + Val55 = 55, + #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] + Val56 = 56, + #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] + Val57 = 57, + #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] + Val58 = 58, + #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] + Val59 = 59, + #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] + Val60 = 60, + #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] + Val61 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + 9 => Some(Trigin::Val9), + 10 => Some(Trigin::Val10), + 11 => Some(Trigin::Val11), + 12 => Some(Trigin::Val12), + 13 => Some(Trigin::Val13), + 14 => Some(Trigin::Val14), + 15 => Some(Trigin::Val15), + 16 => Some(Trigin::Val16), + 17 => Some(Trigin::Val17), + 18 => Some(Trigin::Val18), + 19 => Some(Trigin::Val19), + 20 => Some(Trigin::Val20), + 21 => Some(Trigin::Val21), + 22 => Some(Trigin::Val22), + 23 => Some(Trigin::Val23), + 24 => Some(Trigin::Val24), + 25 => Some(Trigin::Val25), + 26 => Some(Trigin::Val26), + 27 => Some(Trigin::Val27), + 28 => Some(Trigin::Val28), + 29 => Some(Trigin::Val29), + 30 => Some(Trigin::Val30), + 31 => Some(Trigin::Val31), + 32 => Some(Trigin::Val32), + 33 => Some(Trigin::Val33), + 34 => Some(Trigin::Val34), + 35 => Some(Trigin::Val35), + 36 => Some(Trigin::Val36), + 37 => Some(Trigin::Val37), + 38 => Some(Trigin::Val38), + 39 => Some(Trigin::Val39), + 40 => Some(Trigin::Val40), + 45 => Some(Trigin::Val45), + 46 => Some(Trigin::Val46), + 47 => Some(Trigin::Val47), + 48 => Some(Trigin::Val48), + 49 => Some(Trigin::Val49), + 50 => Some(Trigin::Val50), + 51 => Some(Trigin::Val51), + 52 => Some(Trigin::Val52), + 53 => Some(Trigin::Val53), + 54 => Some(Trigin::Val54), + 55 => Some(Trigin::Val55), + 56 => Some(Trigin::Val56), + 57 => Some(Trigin::Val57), + 58 => Some(Trigin::Val58), + 59 => Some(Trigin::Val59), + 60 => Some(Trigin::Val60), + 61 => Some(Trigin::Val61), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Trigin::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Trigin::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Trigin::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Trigin::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Trigin::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Trigin::Val14 + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Trigin::Val15 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Trigin::Val16 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Trigin::Val17 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Trigin::Val18 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Trigin::Val19 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Trigin::Val20 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Trigin::Val21 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Trigin::Val22 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Trigin::Val23 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Trigin::Val24 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Trigin::Val25 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Trigin::Val26 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Trigin::Val27 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Trigin::Val28 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Trigin::Val29 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Trigin::Val30 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Trigin::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Trigin::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Trigin::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Trigin::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Trigin::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Trigin::Val36 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Trigin::Val37 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Trigin::Val38 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Trigin::Val39 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Trigin::Val40 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Trigin::Val45 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Trigin::Val46 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Trigin::Val47 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Trigin::Val48 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Trigin::Val49 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Trigin::Val50 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Trigin::Val51 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Trigin::Val52 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Trigin::Val53 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Trigin::Val54 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Trigin::Val55 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Trigin::Val56 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Trigin::Val57 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Trigin::Val58 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Trigin::Val59 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Trigin::Val60 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Trigin::Val61 + } +} +#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Trigin::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Trigin::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Trigin::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Trigin::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Trigin::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Trigin::Val14) + } + #[doc = "QDC0_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Trigin::Val15) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Trigin::Val16) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Trigin::Val17) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Trigin::Val18) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Trigin::Val19) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Trigin::Val20) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Trigin::Val21) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Trigin::Val22) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Trigin::Val23) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Trigin::Val24) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Trigin::Val25) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Trigin::Val26) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Trigin::Val27) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Trigin::Val28) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Trigin::Val29) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Trigin::Val30) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Trigin::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Trigin::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Trigin::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Trigin::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Trigin::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Trigin::Val36) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Trigin::Val37) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Trigin::Val38) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Trigin::Val39) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Trigin::Val40) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Trigin::Val45) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Trigin::Val46) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Trigin::Val47) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Trigin::Val48) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Trigin::Val49) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Trigin::Val50) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Trigin::Val51) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Trigin::Val52) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Trigin::Val53) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Trigin::Val54) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Trigin::Val55) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Trigin::Val56) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Trigin::Val57) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Trigin::Val58) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Trigin::Val59) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Trigin::Val60) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Trigin::Val61) + } +} +impl R { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexPwm1Sm3ExtsyncSpec; +impl crate::RegisterSpec for FlexPwm1Sm3ExtsyncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flex_pwm1_sm3_extsync::R`](R) reader structure"] +impl crate::Readable for FlexPwm1Sm3ExtsyncSpec {} +#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm3_extsync::W`](W) writer structure"] +impl crate::Writable for FlexPwm1Sm3ExtsyncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FlexPWM1_SM3_EXTSYNC to value 0x3f"] +impl crate::Resettable for FlexPwm1Sm3ExtsyncSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/flexio_trig.rs b/mcxa276-pac/src/inputmux0/flexio_trig.rs new file mode 100644 index 000000000..dc777d350 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/flexio_trig.rs @@ -0,0 +1,1094 @@ +#[doc = "Register `FLEXIO_TRIG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `FLEXIO_TRIG[%s]` writer"] +pub type W = crate::W; +#[doc = "Input number for FlexIO0.\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: AOI0_OUT0 input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT1 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT2 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT3 input is selected"] + Val4 = 4, + #[doc = "5: ADC0_tcomp\\[0\\] input is selected"] + Val5 = 5, + #[doc = "6: ADC0_tcomp\\[1\\] input is selected"] + Val6 = 6, + #[doc = "7: ADC0_tcomp\\[2\\] input is selected"] + Val7 = 7, + #[doc = "8: ADC0_tcomp\\[3\\] input is selected"] + Val8 = 8, + #[doc = "9: CMP0_OUT input is selected"] + Val9 = 9, + #[doc = "10: CMP1_OUT input is selected"] + Val10 = 10, + #[doc = "11: CMP2_OUT input is selected"] + Val11 = 11, + #[doc = "12: CTimer0_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer0_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer1_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: CTimer1_MAT2 input is selected"] + Val15 = 15, + #[doc = "16: CTimer2_MAT1 input is selected"] + Val16 = 16, + #[doc = "17: CTimer2_MAT2 input is selected"] + Val17 = 17, + #[doc = "18: LPTMR0 input is selected"] + Val18 = 18, + #[doc = "20: PWM0_SM0_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM1_MUX_TRIG0 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM2_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] + Val34 = 34, + #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] + Val35 = 35, + #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] + Val36 = 36, + #[doc = "37: WUU input is selected"] + Val37 = 37, + #[doc = "38: LPI2C0 Master End of Packet"] + Val38 = 38, + #[doc = "39: LPI2C0 Slave End of Packet"] + Val39 = 39, + #[doc = "40: LPI2C1 Master End of Packet"] + Val40 = 40, + #[doc = "41: LPI2C1 Slave End of Packet"] + Val41 = 41, + #[doc = "42: LPSPI0 End of Frame"] + Val42 = 42, + #[doc = "43: LPSPI0 Received Data Word"] + Val43 = 43, + #[doc = "44: LPSPI1 End of Frame"] + Val44 = 44, + #[doc = "45: LPSPI1 Received Data Word"] + Val45 = 45, + #[doc = "46: LPUART0 Received Data Word"] + Val46 = 46, + #[doc = "47: LPUART0 Transmitted Data Word"] + Val47 = 47, + #[doc = "48: LPUART0 Receive Line Idle"] + Val48 = 48, + #[doc = "49: LPUART1 Received Data Word"] + Val49 = 49, + #[doc = "50: LPUART1 Transmitted Data Word"] + Val50 = 50, + #[doc = "51: LPUART1 Receive Line Idle"] + Val51 = 51, + #[doc = "52: LPUART2 Received Data Word"] + Val52 = 52, + #[doc = "53: LPUART2 Transmitted Data Word"] + Val53 = 53, + #[doc = "54: LPUART2 Receive Line Idle"] + Val54 = 54, + #[doc = "55: LPUART3 Received Data Word"] + Val55 = 55, + #[doc = "56: LPUART3 Transmitted Data Word"] + Val56 = 56, + #[doc = "57: LPUART3 Receive Line Idle"] + Val57 = 57, + #[doc = "58: LPUART4 Received Data Word"] + Val58 = 58, + #[doc = "59: LPUART4 Transmitted Data Word"] + Val59 = 59, + #[doc = "60: LPUART4 Receive Line Idle"] + Val60 = 60, + #[doc = "61: AOI1_OUT0 input is selected"] + Val61 = 61, + #[doc = "62: AOI1_OUT1 input is selected"] + Val62 = 62, + #[doc = "63: AOI1_OUT2 input is selected"] + Val63 = 63, + #[doc = "64: AOI1_OUT3 input is selected"] + Val64 = 64, + #[doc = "65: ADC1_tcomp\\[0\\] input is selected"] + Val65 = 65, + #[doc = "66: ADC1_tcomp\\[1\\] input is selected"] + Val66 = 66, + #[doc = "67: ADC1_tcomp\\[2\\] input is selected"] + Val67 = 67, + #[doc = "68: ADC1_tcomp\\[3\\] input is selected"] + Val68 = 68, + #[doc = "69: CTimer3_MAT2 input is selected"] + Val69 = 69, + #[doc = "70: CTimer3_MAT3 input is selected"] + Val70 = 70, + #[doc = "71: CTimer4_MAT2 input is selected"] + Val71 = 71, + #[doc = "72: CTimer4_MAT3 input is selected"] + Val72 = 72, + #[doc = "73: PWM1_SM0_MUX_TRIG0 input is selected"] + Val73 = 73, + #[doc = "74: PWM1_SM1_MUX_TRIG0 input is selected"] + Val74 = 74, + #[doc = "75: PWM1_SM2_MUX_TRIG0 input is selected"] + Val75 = 75, + #[doc = "76: PWM1_SM3_MUX_TRIG0 input is selected"] + Val76 = 76, + #[doc = "77: LPI2C2 Master End of Packet"] + Val77 = 77, + #[doc = "78: LPI2C2 Slave End of Packet"] + Val78 = 78, + #[doc = "79: LPI2C3 Master End of Packet"] + Val79 = 79, + #[doc = "80: LPI2C3 Slave End of Packet"] + Val80 = 80, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for FlexIO0."] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "LPI2C0 Master End of Packet"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "LPI2C0 Slave End of Packet"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "LPI2C1 Master End of Packet"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "LPI2C1 Slave End of Packet"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "LPSPI0 End of Frame"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "LPSPI0 Received Data Word"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "LPSPI1 End of Frame"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "LPSPI1 Received Data Word"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "LPUART0 Received Data Word"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "LPUART0 Transmitted Data Word"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPUART0 Receive Line Idle"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPUART1 Received Data Word"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPUART1 Transmitted Data Word"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPUART1 Receive Line Idle"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPUART2 Received Data Word"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPUART2 Transmitted Data Word"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPUART2 Receive Line Idle"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPUART3 Received Data Word"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART3 Transmitted Data Word"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART3 Receive Line Idle"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART4 Received Data Word"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART4 Transmitted Data Word"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART4 Receive Line Idle"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "LPI2C2 Master End of Packet"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "LPI2C2 Slave End of Packet"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "LPI2C3 Master End of Packet"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "LPI2C3 Slave End of Packet"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } +} +#[doc = "Field `INP` writer - Input number for FlexIO0."] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "ADC0_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "ADC0_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "ADC0_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "LPI2C0 Master End of Packet"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "LPI2C0 Slave End of Packet"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "LPI2C1 Master End of Packet"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "LPI2C1 Slave End of Packet"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "LPSPI0 End of Frame"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "LPSPI0 Received Data Word"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "LPSPI1 End of Frame"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "LPSPI1 Received Data Word"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "LPUART0 Received Data Word"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "LPUART0 Transmitted Data Word"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPUART0 Receive Line Idle"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPUART1 Received Data Word"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPUART1 Transmitted Data Word"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPUART1 Receive Line Idle"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPUART2 Received Data Word"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPUART2 Transmitted Data Word"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPUART2 Receive Line Idle"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPUART3 Received Data Word"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART3 Transmitted Data Word"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART3 Receive Line Idle"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART4 Received Data Word"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART4 Transmitted Data Word"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART4 Receive Line Idle"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "LPI2C2 Master End of Packet"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "LPI2C2 Slave End of Packet"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "LPI2C3 Master End of Packet"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "LPI2C3 Slave End of Packet"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for FlexIO0."] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for FlexIO0."] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "FlexIO Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flexio_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexio_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlexioTrigSpec; +impl crate::RegisterSpec for FlexioTrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flexio_trig::R`](R) reader structure"] +impl crate::Readable for FlexioTrigSpec {} +#[doc = "`write(|w| ..)` method takes [`flexio_trig::W`](W) writer structure"] +impl crate::Writable for FlexioTrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FLEXIO_TRIG[%s] to value 0x7f"] +impl crate::Resettable for FlexioTrigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/freqmeas_ref.rs b/mcxa276-pac/src/inputmux0/freqmeas_ref.rs new file mode 100644 index 000000000..709671340 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/freqmeas_ref.rs @@ -0,0 +1,418 @@ +#[doc = "Register `FREQMEAS_REF` reader"] +pub type R = crate::R; +#[doc = "Register `FREQMEAS_REF` writer"] +pub type W = crate::W; +#[doc = "Clock source number (binary value) for frequency measure function target clock.\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: clk_in input is selected"] + Val1 = 1, + #[doc = "2: FRO_OSC_12M input is selected"] + Val2 = 2, + #[doc = "3: fro_hf_div input is selected"] + Val3 = 3, + #[doc = "5: clk_16k\\[1\\] input is selected"] + Val5 = 5, + #[doc = "6: SLOW_CLK input is selected"] + Val6 = 6, + #[doc = "7: FREQME_CLK_IN0 input is selected"] + Val7 = 7, + #[doc = "8: FREQME_CLK_IN1 input is selected input is selected"] + Val8 = 8, + #[doc = "9: AOI0_OUT0 input is selected"] + Val9 = 9, + #[doc = "10: AOI0_OUT1"] + Val10 = 10, + #[doc = "11: PWM0_SM0_MUX_TRIG0"] + Val11 = 11, + #[doc = "12: PWM0_SM0_MUX_TRIG1"] + Val12 = 12, + #[doc = "13: PWM0_SM1_MUX_TRIG0"] + Val13 = 13, + #[doc = "14: PWM0_SM1_MUX_TRIG1"] + Val14 = 14, + #[doc = "15: PWM0_SM2_MUX_TRIG0"] + Val15 = 15, + #[doc = "16: PWM0_SM2_MUX_TRIG1"] + Val16 = 16, + #[doc = "17: PWM0_SM3_MUX_TRIG0"] + Val17 = 17, + #[doc = "18: PWM0_SM3_MUX_TRIG1"] + Val18 = 18, + #[doc = "32: AOI1_OUT0 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT1 input is selected"] + Val33 = 33, + #[doc = "34: PWM1_SM0_MUX_TRIG0 input is selected"] + Val34 = 34, + #[doc = "35: PWM1_SM0_MUX_TRIG1 input is selected"] + Val35 = 35, + #[doc = "36: PWM1_SM1_MUX_TRIG0 input is selected"] + Val36 = 36, + #[doc = "37: PWM1_SM1_MUX_TRIG1 input is selected"] + Val37 = 37, + #[doc = "38: PWM1_SM2_MUX_TRIG0 input is selected"] + Val38 = 38, + #[doc = "39: PWM1_SM2_MUX_TRIG1 input is selected"] + Val39 = 39, + #[doc = "40: PWM1_SM3_MUX_TRIG0 input is selected"] + Val40 = 40, + #[doc = "41: PWM1_SM3_MUX_TRIG1 input is selected"] + Val41 = 41, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Clock source number (binary value) for frequency measure function target clock."] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + _ => None, + } + } + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "FRO_OSC_12M input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "fro_hf_div input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "SLOW_CLK input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "FREQME_CLK_IN0 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "FREQME_CLK_IN1 input is selected input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "AOI0_OUT1"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "PWM0_SM0_MUX_TRIG0"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "PWM0_SM0_MUX_TRIG1"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "PWM0_SM1_MUX_TRIG0"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "PWM0_SM1_MUX_TRIG1"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM2_MUX_TRIG0"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "PWM0_SM2_MUX_TRIG1"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM3_MUX_TRIG0"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM3_MUX_TRIG1"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } +} +#[doc = "Field `INP` writer - Clock source number (binary value) for frequency measure function target clock."] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "FRO_OSC_12M input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "fro_hf_div input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "SLOW_CLK input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "FREQME_CLK_IN0 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "FREQME_CLK_IN1 input is selected input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "AOI0_OUT1"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "PWM0_SM0_MUX_TRIG0"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "PWM0_SM0_MUX_TRIG1"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "PWM0_SM1_MUX_TRIG0"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "PWM0_SM1_MUX_TRIG1"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM2_MUX_TRIG0"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "PWM0_SM2_MUX_TRIG1"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM3_MUX_TRIG0"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM3_MUX_TRIG1"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } +} +impl R { + #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_ref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_ref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FreqmeasRefSpec; +impl crate::RegisterSpec for FreqmeasRefSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`freqmeas_ref::R`](R) reader structure"] +impl crate::Readable for FreqmeasRefSpec {} +#[doc = "`write(|w| ..)` method takes [`freqmeas_ref::W`](W) writer structure"] +impl crate::Writable for FreqmeasRefSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FREQMEAS_REF to value 0x3f"] +impl crate::Resettable for FreqmeasRefSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/freqmeas_tar.rs b/mcxa276-pac/src/inputmux0/freqmeas_tar.rs new file mode 100644 index 000000000..38638c330 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/freqmeas_tar.rs @@ -0,0 +1,418 @@ +#[doc = "Register `FREQMEAS_TAR` reader"] +pub type R = crate::R; +#[doc = "Register `FREQMEAS_TAR` writer"] +pub type W = crate::W; +#[doc = "Clock source number (binary value) for frequency measure function target clock.\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: clk_in input is selected"] + Val1 = 1, + #[doc = "2: FRO_OSC_12M input is selected"] + Val2 = 2, + #[doc = "3: fro_hf_div input is selected"] + Val3 = 3, + #[doc = "5: clk_16k\\[1\\] input is selected"] + Val5 = 5, + #[doc = "6: SLOW_CLK input is selected"] + Val6 = 6, + #[doc = "7: FREQME_CLK_IN0 input is selected"] + Val7 = 7, + #[doc = "8: FREQME_CLK_IN1 input is selected input is selected"] + Val8 = 8, + #[doc = "9: AOI0_OUT0 input is selected"] + Val9 = 9, + #[doc = "10: AOI0_OUT1"] + Val10 = 10, + #[doc = "11: PWM0_SM0_MUX_TRIG0"] + Val11 = 11, + #[doc = "12: PWM0_SM0_MUX_TRIG1"] + Val12 = 12, + #[doc = "13: PWM0_SM1_MUX_TRIG0"] + Val13 = 13, + #[doc = "14: PWM0_SM1_MUX_TRIG1"] + Val14 = 14, + #[doc = "15: PWM0_SM2_MUX_TRIG0"] + Val15 = 15, + #[doc = "16: PWM0_SM2_MUX_TRIG1"] + Val16 = 16, + #[doc = "17: PWM0_SM3_MUX_TRIG0"] + Val17 = 17, + #[doc = "18: PWM0_SM3_MUX_TRIG1"] + Val18 = 18, + #[doc = "32: AOI1_OUT0 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT1 input is selected"] + Val33 = 33, + #[doc = "34: PWM1_SM0_MUX_TRIG0 input is selected"] + Val34 = 34, + #[doc = "35: PWM1_SM0_MUX_TRIG1 input is selected"] + Val35 = 35, + #[doc = "36: PWM1_SM1_MUX_TRIG0 input is selected"] + Val36 = 36, + #[doc = "37: PWM1_SM1_MUX_TRIG1 input is selected"] + Val37 = 37, + #[doc = "38: PWM1_SM2_MUX_TRIG0 input is selected"] + Val38 = 38, + #[doc = "39: PWM1_SM2_MUX_TRIG1 input is selected"] + Val39 = 39, + #[doc = "40: PWM1_SM3_MUX_TRIG0 input is selected"] + Val40 = 40, + #[doc = "41: PWM1_SM3_MUX_TRIG1 input is selected"] + Val41 = 41, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Clock source number (binary value) for frequency measure function target clock."] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + _ => None, + } + } + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "FRO_OSC_12M input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "fro_hf_div input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "SLOW_CLK input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "FREQME_CLK_IN0 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "FREQME_CLK_IN1 input is selected input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "AOI0_OUT1"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "PWM0_SM0_MUX_TRIG0"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "PWM0_SM0_MUX_TRIG1"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "PWM0_SM1_MUX_TRIG0"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "PWM0_SM1_MUX_TRIG1"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM2_MUX_TRIG0"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "PWM0_SM2_MUX_TRIG1"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM3_MUX_TRIG0"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM3_MUX_TRIG1"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } +} +#[doc = "Field `INP` writer - Clock source number (binary value) for frequency measure function target clock."] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "FRO_OSC_12M input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "fro_hf_div input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "SLOW_CLK input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "FREQME_CLK_IN0 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "FREQME_CLK_IN1 input is selected input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "AOI0_OUT1"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "PWM0_SM0_MUX_TRIG0"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "PWM0_SM0_MUX_TRIG1"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "PWM0_SM1_MUX_TRIG0"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "PWM0_SM1_MUX_TRIG1"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM2_MUX_TRIG0"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "PWM0_SM2_MUX_TRIG1"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM3_MUX_TRIG0"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM3_MUX_TRIG1"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } +} +impl R { + #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FreqmeasTarSpec; +impl crate::RegisterSpec for FreqmeasTarSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`freqmeas_tar::R`](R) reader structure"] +impl crate::Readable for FreqmeasTarSpec {} +#[doc = "`write(|w| ..)` method takes [`freqmeas_tar::W`](W) writer structure"] +impl crate::Writable for FreqmeasTarSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FREQMEAS_TAR to value 0x3f"] +impl crate::Resettable for FreqmeasTarSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpi2c0_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c0_trig.rs new file mode 100644 index 000000000..a2e9bf3c7 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpi2c0_trig.rs @@ -0,0 +1,587 @@ +#[doc = "Register `LPI2C0_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `LPI2C0_TRIG` writer"] +pub type W = crate::W; +#[doc = "LPI2C0 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "35: CTimer3_MAT2 input is selected"] + Val35 = 35, + #[doc = "36: CTimer3_MAT3 input is selected"] + Val36 = 36, + #[doc = "37: CTimer4_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer4_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: FlexIO CH0 input is selected"] + Val39 = 39, + #[doc = "40: FlexIO CH1 input is selected"] + Val40 = 40, + #[doc = "41: FlexIO CH2 input is selected"] + Val41 = 41, + #[doc = "42: FlexIO CH3 input is selected"] + Val42 = 42, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPI2C0 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } +} +#[doc = "Field `INP` writer - LPI2C0 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } +} +impl R { + #[doc = "Bits 0:5 - LPI2C0 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPI2C0 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPI2C0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpi2c0TrigSpec; +impl crate::RegisterSpec for Lpi2c0TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpi2c0_trig::R`](R) reader structure"] +impl crate::Readable for Lpi2c0TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`lpi2c0_trig::W`](W) writer structure"] +impl crate::Writable for Lpi2c0TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPI2C0_TRIG to value 0x3f"] +impl crate::Resettable for Lpi2c0TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpi2c1_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c1_trig.rs new file mode 100644 index 000000000..f095c6b5d --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpi2c1_trig.rs @@ -0,0 +1,587 @@ +#[doc = "Register `LPI2C1_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `LPI2C1_TRIG` writer"] +pub type W = crate::W; +#[doc = "LPI2C1 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "35: CTimer3_MAT2 input is selected"] + Val35 = 35, + #[doc = "36: CTimer3_MAT3 input is selected"] + Val36 = 36, + #[doc = "37: CTimer4_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer4_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: FlexIO CH0 input is selected"] + Val39 = 39, + #[doc = "40: FlexIO CH1 input is selected"] + Val40 = 40, + #[doc = "41: FlexIO CH2 input is selected"] + Val41 = 41, + #[doc = "42: FlexIO CH3 input is selected"] + Val42 = 42, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPI2C1 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } +} +#[doc = "Field `INP` writer - LPI2C1 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } +} +impl R { + #[doc = "Bits 0:5 - LPI2C1 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPI2C1 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPI2C1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpi2c1TrigSpec; +impl crate::RegisterSpec for Lpi2c1TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpi2c1_trig::R`](R) reader structure"] +impl crate::Readable for Lpi2c1TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`lpi2c1_trig::W`](W) writer structure"] +impl crate::Writable for Lpi2c1TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPI2C1_TRIG to value 0x3f"] +impl crate::Resettable for Lpi2c1TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpi2c2_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c2_trig.rs new file mode 100644 index 000000000..5e402bcc8 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpi2c2_trig.rs @@ -0,0 +1,587 @@ +#[doc = "Register `LPI2C2_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `LPI2C2_TRIG` writer"] +pub type W = crate::W; +#[doc = "LPI2C2 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "35: CTimer3_MAT2 input is selected"] + Val35 = 35, + #[doc = "36: CTimer3_MAT3 input is selected"] + Val36 = 36, + #[doc = "37: CTimer4_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer4_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: FlexIO CH0 input is selected"] + Val39 = 39, + #[doc = "40: FlexIO CH1 input is selected"] + Val40 = 40, + #[doc = "41: FlexIO CH2 input is selected"] + Val41 = 41, + #[doc = "42: FlexIO CH3 input is selected"] + Val42 = 42, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPI2C2 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } +} +#[doc = "Field `INP` writer - LPI2C2 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } +} +impl R { + #[doc = "Bits 0:5 - LPI2C2 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPI2C2 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPI2C2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c2_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c2_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpi2c2TrigSpec; +impl crate::RegisterSpec for Lpi2c2TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpi2c2_trig::R`](R) reader structure"] +impl crate::Readable for Lpi2c2TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`lpi2c2_trig::W`](W) writer structure"] +impl crate::Writable for Lpi2c2TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPI2C2_TRIG to value 0x3f"] +impl crate::Resettable for Lpi2c2TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpi2c3_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c3_trig.rs new file mode 100644 index 000000000..e674d2cc2 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpi2c3_trig.rs @@ -0,0 +1,587 @@ +#[doc = "Register `LPI2C3_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `LPI2C3_TRIG` writer"] +pub type W = crate::W; +#[doc = "LPI2C3 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT0 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT1 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT0 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT1 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT0 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT1 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "35: CTimer3_MAT2 input is selected"] + Val35 = 35, + #[doc = "36: CTimer3_MAT3 input is selected"] + Val36 = 36, + #[doc = "37: CTimer4_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer4_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: FlexIO CH0 input is selected"] + Val39 = 39, + #[doc = "40: FlexIO CH1 input is selected"] + Val40 = 40, + #[doc = "41: FlexIO CH2 input is selected"] + Val41 = 41, + #[doc = "42: FlexIO CH3 input is selected"] + Val42 = 42, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPI2C3 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } +} +#[doc = "Field `INP` writer - LPI2C3 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT0 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT0 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } +} +impl R { + #[doc = "Bits 0:5 - LPI2C3 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPI2C3 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPI2C3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c3_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c3_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpi2c3TrigSpec; +impl crate::RegisterSpec for Lpi2c3TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpi2c3_trig::R`](R) reader structure"] +impl crate::Readable for Lpi2c3TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`lpi2c3_trig::W`](W) writer structure"] +impl crate::Writable for Lpi2c3TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPI2C3_TRIG to value 0x3f"] +impl crate::Resettable for Lpi2c3TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpspi0_trig.rs b/mcxa276-pac/src/inputmux0/lpspi0_trig.rs new file mode 100644 index 000000000..b40704410 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpspi0_trig.rs @@ -0,0 +1,587 @@ +#[doc = "Register `LPSPI0_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `LPSPI0_TRIG` writer"] +pub type W = crate::W; +#[doc = "LPSPI0 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT1 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT2 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT1 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT2 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT1 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT2 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "35: CTimer3_MAT2 input is selected"] + Val35 = 35, + #[doc = "36: CTimer3_MAT3 input is selected"] + Val36 = 36, + #[doc = "37: CTimer4_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer4_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: FlexIO CH0 input is selected"] + Val39 = 39, + #[doc = "40: FlexIO CH1 input is selected"] + Val40 = 40, + #[doc = "41: FlexIO CH2 input is selected"] + Val41 = 41, + #[doc = "42: FlexIO CH3 input is selected"] + Val42 = 42, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPSPI0 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } +} +#[doc = "Field `INP` writer - LPSPI0 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } +} +impl R { + #[doc = "Bits 0:5 - LPSPI0 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPSPI0 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPSPI0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpspi0TrigSpec; +impl crate::RegisterSpec for Lpspi0TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpspi0_trig::R`](R) reader structure"] +impl crate::Readable for Lpspi0TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`lpspi0_trig::W`](W) writer structure"] +impl crate::Writable for Lpspi0TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPSPI0_TRIG to value 0x3f"] +impl crate::Resettable for Lpspi0TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpspi1_trig.rs b/mcxa276-pac/src/inputmux0/lpspi1_trig.rs new file mode 100644 index 000000000..39708509c --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpspi1_trig.rs @@ -0,0 +1,587 @@ +#[doc = "Register `LPSPI1_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `LPSPI1_TRIG` writer"] +pub type W = crate::W; +#[doc = "LPSPI1 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT1 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT2 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT1 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT2 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT1 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT2 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] + Val25 = 25, + #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] + Val26 = 26, + #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] + Val27 = 27, + #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] + Val28 = 28, + #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: WUU input is selected"] + Val30 = 30, + #[doc = "31: AOI1_OUT0 input is selected"] + Val31 = 31, + #[doc = "32: AOI1_OUT1 input is selected"] + Val32 = 32, + #[doc = "33: AOI1_OUT2 input is selected"] + Val33 = 33, + #[doc = "34: AOI1_OUT3 input is selected"] + Val34 = 34, + #[doc = "35: CTimer3_MAT2 input is selected"] + Val35 = 35, + #[doc = "36: CTimer3_MAT3 input is selected"] + Val36 = 36, + #[doc = "37: CTimer4_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer4_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: FlexIO CH0 input is selected"] + Val39 = 39, + #[doc = "40: FlexIO CH1 input is selected"] + Val40 = 40, + #[doc = "41: FlexIO CH2 input is selected"] + Val41 = 41, + #[doc = "42: FlexIO CH3 input is selected"] + Val42 = 42, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPSPI1 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } +} +#[doc = "Field `INP` writer - LPSPI1 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "WUU input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } +} +impl R { + #[doc = "Bits 0:5 - LPSPI1 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPSPI1 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPSPI1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpspi1TrigSpec; +impl crate::RegisterSpec for Lpspi1TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpspi1_trig::R`](R) reader structure"] +impl crate::Readable for Lpspi1TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`lpspi1_trig::W`](W) writer structure"] +impl crate::Writable for Lpspi1TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPSPI1_TRIG to value 0x3f"] +impl crate::Resettable for Lpspi1TrigSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpuart0.rs b/mcxa276-pac/src/inputmux0/lpuart0.rs new file mode 100644 index 000000000..19d441388 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpuart0.rs @@ -0,0 +1,652 @@ +#[doc = "Register `LPUART0` reader"] +pub type R = crate::R; +#[doc = "Register `LPUART0` writer"] +pub type W = crate::W; +#[doc = "LPUART0 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN8 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN9 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN10 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN11 input is selected"] + Val28 = 28, + #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] + Val31 = 31, + #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: WUU selected"] + Val34 = 34, + #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT1 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT2 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT3 input is selected"] + Val39 = 39, + #[doc = "40: CTimer3_MAT2 input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT3 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT2 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT3 input is selected"] + Val43 = 43, + #[doc = "44: FlexIO CH0 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH1 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH2 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH3 input is selected"] + Val47 = 47, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPUART0 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } +} +#[doc = "Field `INP` writer - LPUART0 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } +} +impl R { + #[doc = "Bits 0:5 - LPUART0 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPUART0 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPUART0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpuart0Spec; +impl crate::RegisterSpec for Lpuart0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpuart0::R`](R) reader structure"] +impl crate::Readable for Lpuart0Spec {} +#[doc = "`write(|w| ..)` method takes [`lpuart0::W`](W) writer structure"] +impl crate::Writable for Lpuart0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPUART0 to value 0x3f"] +impl crate::Resettable for Lpuart0Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpuart1.rs b/mcxa276-pac/src/inputmux0/lpuart1.rs new file mode 100644 index 000000000..1564d3534 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpuart1.rs @@ -0,0 +1,652 @@ +#[doc = "Register `LPUART1` reader"] +pub type R = crate::R; +#[doc = "Register `LPUART1` writer"] +pub type W = crate::W; +#[doc = "LPUART1 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN8 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN9 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN10 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN11 input is selected"] + Val28 = 28, + #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] + Val31 = 31, + #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: WUU selected"] + Val34 = 34, + #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT1 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT2 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT3 input is selected"] + Val39 = 39, + #[doc = "40: CTimer3_MAT2 input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT3 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT2 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT3 input is selected"] + Val43 = 43, + #[doc = "44: FlexIO CH0 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH1 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH2 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH3 input is selected"] + Val47 = 47, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPUART1 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } +} +#[doc = "Field `INP` writer - LPUART1 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } +} +impl R { + #[doc = "Bits 0:5 - LPUART1 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPUART1 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPUART1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpuart1Spec; +impl crate::RegisterSpec for Lpuart1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpuart1::R`](R) reader structure"] +impl crate::Readable for Lpuart1Spec {} +#[doc = "`write(|w| ..)` method takes [`lpuart1::W`](W) writer structure"] +impl crate::Writable for Lpuart1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPUART1 to value 0x3f"] +impl crate::Resettable for Lpuart1Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpuart2.rs b/mcxa276-pac/src/inputmux0/lpuart2.rs new file mode 100644 index 000000000..b4421f6e3 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpuart2.rs @@ -0,0 +1,652 @@ +#[doc = "Register `LPUART2` reader"] +pub type R = crate::R; +#[doc = "Register `LPUART2` writer"] +pub type W = crate::W; +#[doc = "LPUART2 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN8 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN9 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN10 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN11 input is selected"] + Val28 = 28, + #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] + Val31 = 31, + #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: WUU selected"] + Val34 = 34, + #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT1 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT2 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT3 input is selected"] + Val39 = 39, + #[doc = "40: CTimer3_MAT2 input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT3 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT2 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT3 input is selected"] + Val43 = 43, + #[doc = "44: FlexIO CH0 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH1 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH2 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH3 input is selected"] + Val47 = 47, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPUART2 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } +} +#[doc = "Field `INP` writer - LPUART2 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } +} +impl R { + #[doc = "Bits 0:5 - LPUART2 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPUART2 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPUART2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpuart2Spec; +impl crate::RegisterSpec for Lpuart2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpuart2::R`](R) reader structure"] +impl crate::Readable for Lpuart2Spec {} +#[doc = "`write(|w| ..)` method takes [`lpuart2::W`](W) writer structure"] +impl crate::Writable for Lpuart2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPUART2 to value 0x3f"] +impl crate::Resettable for Lpuart2Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpuart3.rs b/mcxa276-pac/src/inputmux0/lpuart3.rs new file mode 100644 index 000000000..e42bf4d44 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpuart3.rs @@ -0,0 +1,652 @@ +#[doc = "Register `LPUART3` reader"] +pub type R = crate::R; +#[doc = "Register `LPUART3` writer"] +pub type W = crate::W; +#[doc = "LPUART3 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN8 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN9 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN10 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN11 input is selected"] + Val28 = 28, + #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] + Val31 = 31, + #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: WUU selected"] + Val34 = 34, + #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT1 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT2 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT3 input is selected"] + Val39 = 39, + #[doc = "40: CTimer3_MAT2 input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT3 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT2 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT3 input is selected"] + Val43 = 43, + #[doc = "44: FlexIO CH0 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH1 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH2 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH3 input is selected"] + Val47 = 47, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPUART3 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } +} +#[doc = "Field `INP` writer - LPUART3 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } +} +impl R { + #[doc = "Bits 0:5 - LPUART3 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPUART3 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPUART3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpuart3Spec; +impl crate::RegisterSpec for Lpuart3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpuart3::R`](R) reader structure"] +impl crate::Readable for Lpuart3Spec {} +#[doc = "`write(|w| ..)` method takes [`lpuart3::W`](W) writer structure"] +impl crate::Writable for Lpuart3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPUART3 to value 0x3f"] +impl crate::Resettable for Lpuart3Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpuart4.rs b/mcxa276-pac/src/inputmux0/lpuart4.rs new file mode 100644 index 000000000..5c8e0862e --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpuart4.rs @@ -0,0 +1,652 @@ +#[doc = "Register `LPUART4` reader"] +pub type R = crate::R; +#[doc = "Register `LPUART4` writer"] +pub type W = crate::W; +#[doc = "LPUART4 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN8 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN9 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN10 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN11 input is selected"] + Val28 = 28, + #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] + Val31 = 31, + #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: WUU selected"] + Val34 = 34, + #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT1 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT2 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT3 input is selected"] + Val39 = 39, + #[doc = "40: CTimer3_MAT2 input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT3 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT2 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT3 input is selected"] + Val43 = 43, + #[doc = "44: FlexIO CH0 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH1 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH2 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH3 input is selected"] + Val47 = 47, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPUART4 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } +} +#[doc = "Field `INP` writer - LPUART4 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } +} +impl R { + #[doc = "Bits 0:5 - LPUART4 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPUART4 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPUART4 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpuart4Spec; +impl crate::RegisterSpec for Lpuart4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpuart4::R`](R) reader structure"] +impl crate::Readable for Lpuart4Spec {} +#[doc = "`write(|w| ..)` method takes [`lpuart4::W`](W) writer structure"] +impl crate::Writable for Lpuart4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPUART4 to value 0x3f"] +impl crate::Resettable for Lpuart4Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/lpuart5.rs b/mcxa276-pac/src/inputmux0/lpuart5.rs new file mode 100644 index 000000000..92023be2d --- /dev/null +++ b/mcxa276-pac/src/inputmux0/lpuart5.rs @@ -0,0 +1,652 @@ +#[doc = "Register `LPUART5` reader"] +pub type R = crate::R; +#[doc = "Register `LPUART5` writer"] +pub type W = crate::W; +#[doc = "LPUART5 trigger input connections\n\nValue on reset: 63"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3 input is selected"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "15: LPTMR0 input is selected"] + Val15 = 15, + #[doc = "17: TRIG_IN0 input is selected"] + Val17 = 17, + #[doc = "18: TRIG_IN1 input is selected"] + Val18 = 18, + #[doc = "19: TRIG_IN2 input is selected"] + Val19 = 19, + #[doc = "20: TRIG_IN3 input is selected"] + Val20 = 20, + #[doc = "21: TRIG_IN4 input is selected"] + Val21 = 21, + #[doc = "22: TRIG_IN5 input is selected"] + Val22 = 22, + #[doc = "23: TRIG_IN6 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN7 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN8 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN9 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN10 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN11 input is selected"] + Val28 = 28, + #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] + Val29 = 29, + #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] + Val30 = 30, + #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] + Val31 = 31, + #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] + Val32 = 32, + #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] + Val33 = 33, + #[doc = "34: WUU selected"] + Val34 = 34, + #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] + Val35 = 35, + #[doc = "36: AOI1_OUT0 input is selected"] + Val36 = 36, + #[doc = "37: AOI1_OUT1 input is selected"] + Val37 = 37, + #[doc = "38: AOI1_OUT2 input is selected"] + Val38 = 38, + #[doc = "39: AOI1_OUT3 input is selected"] + Val39 = 39, + #[doc = "40: CTimer3_MAT2 input is selected"] + Val40 = 40, + #[doc = "41: CTimer3_MAT3 input is selected"] + Val41 = 41, + #[doc = "42: CTimer4_MAT2 input is selected"] + Val42 = 42, + #[doc = "43: CTimer4_MAT3 input is selected"] + Val43 = 43, + #[doc = "44: FlexIO CH0 input is selected"] + Val44 = 44, + #[doc = "45: FlexIO CH1 input is selected"] + Val45 = 45, + #[doc = "46: FlexIO CH2 input is selected"] + Val46 = 46, + #[doc = "47: FlexIO CH3 input is selected"] + Val47 = 47, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - LPUART5 trigger input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + _ => None, + } + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } +} +#[doc = "Field `INP` writer - LPUART5 trigger input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "LPTMR0 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "GPIO0 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "WUU selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "FlexIO CH0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "FlexIO CH1 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "FlexIO CH2 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "FlexIO CH3 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } +} +impl R { + #[doc = "Bits 0:5 - LPUART5 trigger input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - LPUART5 trigger input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "LPUART5 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Lpuart5Spec; +impl crate::RegisterSpec for Lpuart5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpuart5::R`](R) reader structure"] +impl crate::Readable for Lpuart5Spec {} +#[doc = "`write(|w| ..)` method takes [`lpuart5::W`](W) writer structure"] +impl crate::Writable for Lpuart5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPUART5 to value 0x3f"] +impl crate::Resettable for Lpuart5Spec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs b/mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs new file mode 100644 index 000000000..fd9d8b6ea --- /dev/null +++ b/mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs @@ -0,0 +1,171 @@ +#[doc = "Register `PWM0_EXT_CLK` reader"] +pub type R = crate::R; +#[doc = "Register `PWM0_EXT_CLK` writer"] +pub type W = crate::W; +#[doc = "Trigger input connections for PWM\n\nValue on reset: 15"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: clk_16k\\[1\\] input is selected"] + Val1 = 1, + #[doc = "2: clk_in input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT0 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT1 input is selected"] + Val4 = 4, + #[doc = "5: EXTTRIG_IN0 input is selected"] + Val5 = 5, + #[doc = "6: EXTTRIG_IN7 input is selected"] + Val6 = 6, + #[doc = "7: AOI1_OUT0 input is selected"] + Val7 = 7, + #[doc = "8: AOI1_OUT1 input is selected"] + Val8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + _ => None, + } + } + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "EXTTRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "EXTTRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } +} +#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 4, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "EXTTRIG_IN0 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "EXTTRIG_IN7 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } +} +impl R { + #[doc = "Bits 0:3 - Trigger input connections for PWM"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Trigger input connections for PWM"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM0 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0_ext_clk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0_ext_clk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pwm0ExtClkSpec; +impl crate::RegisterSpec for Pwm0ExtClkSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm0_ext_clk::R`](R) reader structure"] +impl crate::Readable for Pwm0ExtClkSpec {} +#[doc = "`write(|w| ..)` method takes [`pwm0_ext_clk::W`](W) writer structure"] +impl crate::Writable for Pwm0ExtClkSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWM0_EXT_CLK to value 0x0f"] +impl crate::Resettable for Pwm0ExtClkSpec { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs b/mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs new file mode 100644 index 000000000..5c827f56b --- /dev/null +++ b/mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs @@ -0,0 +1,171 @@ +#[doc = "Register `PWM1_EXT_CLK` reader"] +pub type R = crate::R; +#[doc = "Register `PWM1_EXT_CLK` writer"] +pub type W = crate::W; +#[doc = "Trigger input connections for PWM\n\nValue on reset: 15"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trigin { + #[doc = "1: clk_16k\\[1\\] input is selected"] + Val1 = 1, + #[doc = "2: clk_in input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT0 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT1 input is selected"] + Val4 = 4, + #[doc = "5: EXTTRIG_IN0 input is selected"] + Val5 = 5, + #[doc = "6: EXTTRIG_IN7 input is selected"] + Val6 = 6, + #[doc = "7: AOI1_OUT0 input is selected"] + Val7 = 7, + #[doc = "8: AOI1_OUT1 input is selected"] + Val8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trigin) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trigin { + type Ux = u8; +} +impl crate::IsEnum for Trigin {} +#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM"] +pub type TriginR = crate::FieldReader; +impl TriginR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Trigin::Val1), + 2 => Some(Trigin::Val2), + 3 => Some(Trigin::Val3), + 4 => Some(Trigin::Val4), + 5 => Some(Trigin::Val5), + 6 => Some(Trigin::Val6), + 7 => Some(Trigin::Val7), + 8 => Some(Trigin::Val8), + _ => None, + } + } + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Trigin::Val1 + } + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Trigin::Val2 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Trigin::Val3 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Trigin::Val4 + } + #[doc = "EXTTRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Trigin::Val5 + } + #[doc = "EXTTRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Trigin::Val6 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Trigin::Val7 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Trigin::Val8 + } +} +#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM"] +pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 4, Trigin>; +impl<'a, REG> TriginW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "clk_16k\\[1\\] input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Trigin::Val1) + } + #[doc = "clk_in input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Trigin::Val2) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Trigin::Val3) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Trigin::Val4) + } + #[doc = "EXTTRIG_IN0 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Trigin::Val5) + } + #[doc = "EXTTRIG_IN7 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Trigin::Val6) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Trigin::Val7) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Trigin::Val8) + } +} +impl R { + #[doc = "Bits 0:3 - Trigger input connections for PWM"] + #[inline(always)] + pub fn trigin(&self) -> TriginR { + TriginR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Trigger input connections for PWM"] + #[inline(always)] + pub fn trigin(&mut self) -> TriginW { + TriginW::new(self, 0) + } +} +#[doc = "PWM1 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1_ext_clk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1_ext_clk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pwm1ExtClkSpec; +impl crate::RegisterSpec for Pwm1ExtClkSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm1_ext_clk::R`](R) reader structure"] +impl crate::Readable for Pwm1ExtClkSpec {} +#[doc = "`write(|w| ..)` method takes [`pwm1_ext_clk::W`](W) writer structure"] +impl crate::Writable for Pwm1ExtClkSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWM1_EXT_CLK to value 0x0f"] +impl crate::Resettable for Pwm1ExtClkSpec { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_home.rs b/mcxa276-pac/src/inputmux0/qdc0_home.rs new file mode 100644 index 000000000..a515f2e8f --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_home.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC0_HOME` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_HOME` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_home::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_home::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0HomeSpec; +impl crate::RegisterSpec for Qdc0HomeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_home::R`](R) reader structure"] +impl crate::Readable for Qdc0HomeSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_home::W`](W) writer structure"] +impl crate::Writable for Qdc0HomeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_HOME to value 0x7f"] +impl crate::Resettable for Qdc0HomeSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_icap1.rs b/mcxa276-pac/src/inputmux0/qdc0_icap1.rs new file mode 100644 index 000000000..4ecbe2876 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_icap1.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC0_ICAP1` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_ICAP1` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0Icap1Spec; +impl crate::RegisterSpec for Qdc0Icap1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_icap1::R`](R) reader structure"] +impl crate::Readable for Qdc0Icap1Spec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_icap1::W`](W) writer structure"] +impl crate::Writable for Qdc0Icap1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_ICAP1 to value 0x7f"] +impl crate::Resettable for Qdc0Icap1Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_icap2.rs b/mcxa276-pac/src/inputmux0/qdc0_icap2.rs new file mode 100644 index 000000000..5f3a3ea83 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_icap2.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC0_ICAP2` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_ICAP2` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0Icap2Spec; +impl crate::RegisterSpec for Qdc0Icap2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_icap2::R`](R) reader structure"] +impl crate::Readable for Qdc0Icap2Spec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_icap2::W`](W) writer structure"] +impl crate::Writable for Qdc0Icap2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_ICAP2 to value 0x7f"] +impl crate::Resettable for Qdc0Icap2Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_icap3.rs b/mcxa276-pac/src/inputmux0/qdc0_icap3.rs new file mode 100644 index 000000000..19111f161 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_icap3.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC0_ICAP3` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_ICAP3` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM0_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0Icap3Spec; +impl crate::RegisterSpec for Qdc0Icap3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_icap3::R`](R) reader structure"] +impl crate::Readable for Qdc0Icap3Spec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_icap3::W`](W) writer structure"] +impl crate::Writable for Qdc0Icap3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_ICAP3 to value 0x7f"] +impl crate::Resettable for Qdc0Icap3Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_index.rs b/mcxa276-pac/src/inputmux0/qdc0_index.rs new file mode 100644 index 000000000..dbc856a33 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_index.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC0_INDEX` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_INDEX` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0IndexSpec; +impl crate::RegisterSpec for Qdc0IndexSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_index::R`](R) reader structure"] +impl crate::Readable for Qdc0IndexSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_index::W`](W) writer structure"] +impl crate::Writable for Qdc0IndexSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_INDEX to value 0x7f"] +impl crate::Resettable for Qdc0IndexSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_phasea.rs b/mcxa276-pac/src/inputmux0/qdc0_phasea.rs new file mode 100644 index 000000000..de4028f34 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_phasea.rs @@ -0,0 +1,756 @@ +#[doc = "Register `QDC0_PHASEA` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_PHASEA` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phasea::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phasea::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0PhaseaSpec; +impl crate::RegisterSpec for Qdc0PhaseaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_phasea::R`](R) reader structure"] +impl crate::Readable for Qdc0PhaseaSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_phasea::W`](W) writer structure"] +impl crate::Writable for Qdc0PhaseaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_PHASEA to value 0x7f"] +impl crate::Resettable for Qdc0PhaseaSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_phaseb.rs b/mcxa276-pac/src/inputmux0/qdc0_phaseb.rs new file mode 100644 index 000000000..204fadc21 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_phaseb.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC0_PHASEB` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_PHASEB` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phaseb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phaseb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0PhasebSpec; +impl crate::RegisterSpec for Qdc0PhasebSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_phaseb::R`](R) reader structure"] +impl crate::Readable for Qdc0PhasebSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_phaseb::W`](W) writer structure"] +impl crate::Writable for Qdc0PhasebSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_PHASEB to value 0x7f"] +impl crate::Resettable for Qdc0PhasebSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc0_trig.rs b/mcxa276-pac/src/inputmux0/qdc0_trig.rs new file mode 100644 index 000000000..f2c422b39 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc0_trig.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC0_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `QDC0_TRIG` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc0TrigSpec; +impl crate::RegisterSpec for Qdc0TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc0_trig::R`](R) reader structure"] +impl crate::Readable for Qdc0TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc0_trig::W`](W) writer structure"] +impl crate::Writable for Qdc0TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC0_TRIG to value 0x7f"] +impl crate::Resettable for Qdc0TrigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_home.rs b/mcxa276-pac/src/inputmux0/qdc1_home.rs new file mode 100644 index 000000000..90f9f9c40 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_home.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_HOME` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_HOME` writer"] +pub type W = crate::W; +#[doc = "QDC1 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC1 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC1 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_home::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_home::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1HomeSpec; +impl crate::RegisterSpec for Qdc1HomeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_home::R`](R) reader structure"] +impl crate::Readable for Qdc1HomeSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_home::W`](W) writer structure"] +impl crate::Writable for Qdc1HomeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_HOME to value 0x7f"] +impl crate::Resettable for Qdc1HomeSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_icap1.rs b/mcxa276-pac/src/inputmux0/qdc1_icap1.rs new file mode 100644 index 000000000..689321615 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_icap1.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_ICAP1` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_ICAP1` writer"] +pub type W = crate::W; +#[doc = "QDC1 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC1 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC1 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1Icap1Spec; +impl crate::RegisterSpec for Qdc1Icap1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_icap1::R`](R) reader structure"] +impl crate::Readable for Qdc1Icap1Spec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_icap1::W`](W) writer structure"] +impl crate::Writable for Qdc1Icap1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_ICAP1 to value 0x7f"] +impl crate::Resettable for Qdc1Icap1Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_icap2.rs b/mcxa276-pac/src/inputmux0/qdc1_icap2.rs new file mode 100644 index 000000000..07c2bd08e --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_icap2.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_ICAP2` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_ICAP2` writer"] +pub type W = crate::W; +#[doc = "QDC1 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC1 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC1 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1Icap2Spec; +impl crate::RegisterSpec for Qdc1Icap2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_icap2::R`](R) reader structure"] +impl crate::Readable for Qdc1Icap2Spec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_icap2::W`](W) writer structure"] +impl crate::Writable for Qdc1Icap2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_ICAP2 to value 0x7f"] +impl crate::Resettable for Qdc1Icap2Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_icap3.rs b/mcxa276-pac/src/inputmux0/qdc1_icap3.rs new file mode 100644 index 000000000..84e312a0f --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_icap3.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_ICAP3` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_ICAP3` writer"] +pub type W = crate::W; +#[doc = "QDC1 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC1 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC1 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1Icap3Spec; +impl crate::RegisterSpec for Qdc1Icap3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_icap3::R`](R) reader structure"] +impl crate::Readable for Qdc1Icap3Spec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_icap3::W`](W) writer structure"] +impl crate::Writable for Qdc1Icap3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_ICAP3 to value 0x7f"] +impl crate::Resettable for Qdc1Icap3Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_index.rs b/mcxa276-pac/src/inputmux0/qdc1_index.rs new file mode 100644 index 000000000..5dc5a96a8 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_index.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_INDEX` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_INDEX` writer"] +pub type W = crate::W; +#[doc = "QDC1 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: >CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC1 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = ">CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC1 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = ">CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1IndexSpec; +impl crate::RegisterSpec for Qdc1IndexSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_index::R`](R) reader structure"] +impl crate::Readable for Qdc1IndexSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_index::W`](W) writer structure"] +impl crate::Writable for Qdc1IndexSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_INDEX to value 0x7f"] +impl crate::Resettable for Qdc1IndexSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_phasea.rs b/mcxa276-pac/src/inputmux0/qdc1_phasea.rs new file mode 100644 index 000000000..e95cf7945 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_phasea.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_PHASEA` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_PHASEA` writer"] +pub type W = crate::W; +#[doc = "QDC0 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC0 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC0 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC0 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phasea::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phasea::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1PhaseaSpec; +impl crate::RegisterSpec for Qdc1PhaseaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_phasea::R`](R) reader structure"] +impl crate::Readable for Qdc1PhaseaSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_phasea::W`](W) writer structure"] +impl crate::Writable for Qdc1PhaseaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_PHASEA to value 0x7f"] +impl crate::Resettable for Qdc1PhaseaSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_phaseb.rs b/mcxa276-pac/src/inputmux0/qdc1_phaseb.rs new file mode 100644 index 000000000..76a0e7a9a --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_phaseb.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_PHASEB` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_PHASEB` writer"] +pub type W = crate::W; +#[doc = "QDC1 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 inout is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC1 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 inout is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC1 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 inout is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phaseb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phaseb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1PhasebSpec; +impl crate::RegisterSpec for Qdc1PhasebSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_phaseb::R`](R) reader structure"] +impl crate::Readable for Qdc1PhasebSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_phaseb::W`](W) writer structure"] +impl crate::Writable for Qdc1PhasebSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_PHASEB to value 0x7f"] +impl crate::Resettable for Qdc1PhasebSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/qdc1_trig.rs b/mcxa276-pac/src/inputmux0/qdc1_trig.rs new file mode 100644 index 000000000..392b5ce50 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/qdc1_trig.rs @@ -0,0 +1,782 @@ +#[doc = "Register `QDC1_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `QDC1_TRIG` writer"] +pub type W = crate::W; +#[doc = "QDC1 input connections\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: ARM_TXEV input is selected"] + Val1 = 1, + #[doc = "2: AOI0_OUT0 input is selected"] + Val2 = 2, + #[doc = "3: AOI0_OUT1 input is selected"] + Val3 = 3, + #[doc = "4: AOI0_OUT2 input is selected"] + Val4 = 4, + #[doc = "5: AOI0_OUT3 input is selected"] + Val5 = 5, + #[doc = "6: CMP0_OUT input is selected"] + Val6 = 6, + #[doc = "7: CMP1_OUT input is selected"] + Val7 = 7, + #[doc = "8: CMP2_OUT input is selected"] + Val8 = 8, + #[doc = "9: CTimer0_MAT2 input is selected"] + Val9 = 9, + #[doc = "10: CTimer0_MAT3"] + Val10 = 10, + #[doc = "11: CTimer1_MAT2 input is selected"] + Val11 = 11, + #[doc = "12: CTimer1_MAT3 input is selected"] + Val12 = 12, + #[doc = "13: CTimer2_MAT2 input is selected"] + Val13 = 13, + #[doc = "14: CTimer2_MAT3 input is selected"] + Val14 = 14, + #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] + Val16 = 16, + #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] + Val17 = 17, + #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] + Val18 = 18, + #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] + Val19 = 19, + #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] + Val20 = 20, + #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] + Val21 = 21, + #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] + Val22 = 22, + #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] + Val23 = 23, + #[doc = "24: TRIG_IN0 input is selected"] + Val24 = 24, + #[doc = "25: TRIG_IN1 input is selected"] + Val25 = 25, + #[doc = "26: TRIG_IN2 input is selected"] + Val26 = 26, + #[doc = "27: TRIG_IN3 input is selected"] + Val27 = 27, + #[doc = "28: TRIG_IN4 input is selected"] + Val28 = 28, + #[doc = "29: TRIG_IN5 input is selected"] + Val29 = 29, + #[doc = "30: TRIG_IN6 input is selected"] + Val30 = 30, + #[doc = "31: TRIG_IN7 input is selected"] + Val31 = 31, + #[doc = "32: TRIG_IN8 input is selected"] + Val32 = 32, + #[doc = "33: TRIG_IN9 input is selected"] + Val33 = 33, + #[doc = "34: TRIG_IN10 input is selected"] + Val34 = 34, + #[doc = "35: TRIG_IN11 input is selected"] + Val35 = 35, + #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] + Val36 = 36, + #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] + Val37 = 37, + #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] + Val38 = 38, + #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] + Val39 = 39, + #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] + Val40 = 40, + #[doc = "41: AOI1_OUT0 input is selected"] + Val41 = 41, + #[doc = "42: AOI1_OUT1 input is selected"] + Val42 = 42, + #[doc = "43: AOI1_OUT2 input is selected"] + Val43 = 43, + #[doc = "44: AOI1_OUT3 input is selected"] + Val44 = 44, + #[doc = "49: CTimer3_MAT2 input is selected"] + Val49 = 49, + #[doc = "50: CTimer3_MAT3 input is selected"] + Val50 = 50, + #[doc = "51: CTimer4_MAT2 input is selected"] + Val51 = 51, + #[doc = "52: CTimer4_MAT3 input is selected"] + Val52 = 52, + #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] + Val62 = 62, + #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] + Val63 = 63, + #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] + Val64 = 64, + #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] + Val65 = 65, + #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] + Val66 = 66, + #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] + Val67 = 67, + #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] + Val68 = 68, + #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] + Val69 = 69, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - QDC1 input connections"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + _ => None, + } + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } +} +#[doc = "Field `INP` writer - QDC1 input connections"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CTimer0_MAT3"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "GPIO0 Pin Event Trig 0 is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "GPIO1 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "GPIO2 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "GPIO3 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "GPIO4 Pin Event Trig 0 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } +} +impl R { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - QDC1 input connections"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Qdc1TrigSpec; +impl crate::RegisterSpec for Qdc1TrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`qdc1_trig::R`](R) reader structure"] +impl crate::Readable for Qdc1TrigSpec {} +#[doc = "`write(|w| ..)` method takes [`qdc1_trig::W`](W) writer structure"] +impl crate::Writable for Qdc1TrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets QDC1_TRIG to value 0x7f"] +impl crate::Resettable for Qdc1TrigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/smart_dma_trig.rs b/mcxa276-pac/src/inputmux0/smart_dma_trig.rs new file mode 100644 index 000000000..535a029bc --- /dev/null +++ b/mcxa276-pac/src/inputmux0/smart_dma_trig.rs @@ -0,0 +1,1081 @@ +#[doc = "Register `SmartDMA_TRIG[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `SmartDMA_TRIG[%s]` writer"] +pub type W = crate::W; +#[doc = "Input number for SmartDMA.\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: GPIO P0_16 input is selected"] + Val1 = 1, + #[doc = "2: GPIO P0_17 input is selected"] + Val2 = 2, + #[doc = "3: GPIO P1_8 input is selected"] + Val3 = 3, + #[doc = "4: GPIO P1_9 input is selected"] + Val4 = 4, + #[doc = "5: GPIO P1_10 input is selected"] + Val5 = 5, + #[doc = "6: GPIO P1_11 input is selected"] + Val6 = 6, + #[doc = "7: GPIO P1_12 input is selected"] + Val7 = 7, + #[doc = "8: GPIO P1_13 input is selected"] + Val8 = 8, + #[doc = "9: GPIO P2_0 input is selected"] + Val9 = 9, + #[doc = "10: GPIO P2_1 input is selected"] + Val10 = 10, + #[doc = "11: GPIO P2_2 input is selected"] + Val11 = 11, + #[doc = "12: GPIO P2_3 input is selected"] + Val12 = 12, + #[doc = "13: GPIO P2_6 input is selected"] + Val13 = 13, + #[doc = "14: GPIO P3_8 input is selected"] + Val14 = 14, + #[doc = "15: GPIO P3_9 input is selected"] + Val15 = 15, + #[doc = "16: GPIO P3_10 input is selected"] + Val16 = 16, + #[doc = "17: GPIO P3_11 input is selected"] + Val17 = 17, + #[doc = "18: GPIO P3_12 input is seclected"] + Val18 = 18, + #[doc = "19: GPIO0 Pin Event Trig input is selected"] + Val19 = 19, + #[doc = "20: GPIO1 Pin Event Trig input is selected"] + Val20 = 20, + #[doc = "21: GPIO2 Pin Event Trig input is selected"] + Val21 = 21, + #[doc = "22: GPIO3 Pin Event Trig input is selected"] + Val22 = 22, + #[doc = "23: GPIO4 Pin Event Trig input is selected"] + Val23 = 23, + #[doc = "24: ARM_TXEV input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT0 input is selected"] + Val25 = 25, + #[doc = "26: AOI1_OUT1 input is selected"] + Val26 = 26, + #[doc = "27: DMA_IRQ input is selected"] + Val27 = 27, + #[doc = "28: MAU_IRQ input is selected"] + Val28 = 28, + #[doc = "29: WUU_IRQ input is selected"] + Val29 = 29, + #[doc = "30: CTimer0_MAT2 input is selected"] + Val30 = 30, + #[doc = "31: CTimer0_MAT3 input is selected"] + Val31 = 31, + #[doc = "32: CTimer1_MAT2 input is selected"] + Val32 = 32, + #[doc = "33: CTimer1_MAT3 input is selected"] + Val33 = 33, + #[doc = "34: CTimer2_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer2_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer3_MAT2 input is selected"] + Val36 = 36, + #[doc = "37: CTimer3_MAT3 input is selected"] + Val37 = 37, + #[doc = "38: CTimer4_MAT2 input is selected"] + Val38 = 38, + #[doc = "39: CTimer4_MAT3 input is selected"] + Val39 = 39, + #[doc = "40: OSTIMER_IRQ input is selected"] + Val40 = 40, + #[doc = "41: PWM0_IRQ input is selected"] + Val41 = 41, + #[doc = "42: PWM1_IRQ input is selected"] + Val42 = 42, + #[doc = "43: QDC0_IRQ input is selected"] + Val43 = 43, + #[doc = "44: QDC1_IRQ input is selected"] + Val44 = 44, + #[doc = "45: RTC_Alarm_IRQ input is selected"] + Val45 = 45, + #[doc = "46: RTC_1Hz_IRQ input is selected"] + Val46 = 46, + #[doc = "47: uTICK_IRQ input is selected"] + Val47 = 47, + #[doc = "48: WDT_IRQ input is selected"] + Val48 = 48, + #[doc = "49: Wakeup_Timer_IRQ input is selected"] + Val49 = 49, + #[doc = "50: CAN0_IRQ input is selected"] + Val50 = 50, + #[doc = "51: CAN1_IRQ input is selected"] + Val51 = 51, + #[doc = "52: FlexIO_IRQ input is selected"] + Val52 = 52, + #[doc = "53: FlexIO_Shifer0_DMA_Req input is selected"] + Val53 = 53, + #[doc = "54: FlexIO_Shifer1_DMA_Req input is selected"] + Val54 = 54, + #[doc = "55: FlexIO_Shifer2_DMA_Req input is selected"] + Val55 = 55, + #[doc = "56: FlexIO_Shifer3_DMA_Req input is selected"] + Val56 = 56, + #[doc = "57: I3C0_IRQ input is selected"] + Val57 = 57, + #[doc = "58: LPI2C0_IRQ input is selected"] + Val58 = 58, + #[doc = "59: LPI2C1_IRQ input is selected"] + Val59 = 59, + #[doc = "60: LPSPI0_IRQ input is selected"] + Val60 = 60, + #[doc = "61: LPSPI1_IRQ input is selected"] + Val61 = 61, + #[doc = "62: LPUART0_IRQ input is selected"] + Val62 = 62, + #[doc = "63: LPUART1_IRQ input is selected"] + Val63 = 63, + #[doc = "64: LPUART2_IRQ input is selected"] + Val64 = 64, + #[doc = "65: LPUART3_IRQ input is selected"] + Val65 = 65, + #[doc = "66: USB0_SOF input is selected"] + Val66 = 66, + #[doc = "68: ADC0_IRQ input is selected"] + Val68 = 68, + #[doc = "69: ADC1_IRQ input is selected"] + Val69 = 69, + #[doc = "70: ADC2_IRQ input is selected"] + Val70 = 70, + #[doc = "71: ADC3_IRQ input is selected"] + Val71 = 71, + #[doc = "72: CMP0_IRQ input is selected"] + Val72 = 72, + #[doc = "73: CMP1_IRQ input is selected"] + Val73 = 73, + #[doc = "74: CMP2_IRQ input is selected"] + Val74 = 74, + #[doc = "75: CMP0_OUT input is selected"] + Val75 = 75, + #[doc = "76: CMP1_OUT input is selected"] + Val76 = 76, + #[doc = "77: CMP2_OUT input is selected"] + Val77 = 77, + #[doc = "78: DAC0_IRQ input is selected"] + Val78 = 78, + #[doc = "79: SLCD_IRQ input is selected"] + Val79 = 79, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for SmartDMA."] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + _ => None, + } + } + #[doc = "GPIO P0_16 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "GPIO P0_17 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "GPIO P1_8 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "GPIO P1_9 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "GPIO P1_10 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "GPIO P1_11 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "GPIO P1_12 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "GPIO P1_13 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "GPIO P2_0 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "GPIO P2_1 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "GPIO P2_2 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "GPIO P2_3 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "GPIO P2_6 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "GPIO P3_8 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "GPIO P3_9 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "GPIO P3_10 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "GPIO P3_11 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "GPIO P3_12 input is seclected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "GPIO0 Pin Event Trig input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "GPIO1 Pin Event Trig input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "GPIO2 Pin Event Trig input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "GPIO3 Pin Event Trig input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "GPIO4 Pin Event Trig input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "DMA_IRQ input is selected"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "MAU_IRQ input is selected"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "WUU_IRQ input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "OSTIMER_IRQ input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "PWM0_IRQ input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "PWM1_IRQ input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_IRQ input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "QDC1_IRQ input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "RTC_Alarm_IRQ input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "RTC_1Hz_IRQ input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "uTICK_IRQ input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "WDT_IRQ input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "Wakeup_Timer_IRQ input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "CAN0_IRQ input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "CAN1_IRQ input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "FlexIO_IRQ input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "FlexIO_Shifer0_DMA_Req input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "FlexIO_Shifer1_DMA_Req input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "FlexIO_Shifer2_DMA_Req input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "FlexIO_Shifer3_DMA_Req input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "I3C0_IRQ input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPI2C0_IRQ input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPI2C1_IRQ input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPSPI0_IRQ input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPSPI1_IRQ input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART0_IRQ input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART1_IRQ input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2_IRQ input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3_IRQ input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "USB0_SOF input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "ADC0_IRQ input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "ADC1_IRQ input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "ADC2_IRQ input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "ADC3_IRQ input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "CMP0_IRQ input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "CMP1_IRQ input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "CMP2_IRQ input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "DAC0_IRQ input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "SLCD_IRQ input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } +} +#[doc = "Field `INP` writer - Input number for SmartDMA."] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "GPIO P0_16 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "GPIO P0_17 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "GPIO P1_8 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "GPIO P1_9 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "GPIO P1_10 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "GPIO P1_11 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "GPIO P1_12 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "GPIO P1_13 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "GPIO P2_0 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "GPIO P2_1 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "GPIO P2_2 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "GPIO P2_3 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "GPIO P2_6 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "GPIO P3_8 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "GPIO P3_9 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "GPIO P3_10 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "GPIO P3_11 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "GPIO P3_12 input is seclected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "GPIO0 Pin Event Trig input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "GPIO1 Pin Event Trig input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "GPIO2 Pin Event Trig input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "GPIO3 Pin Event Trig input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "GPIO4 Pin Event Trig input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "ARM_TXEV input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "DMA_IRQ input is selected"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "MAU_IRQ input is selected"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "WUU_IRQ input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "OSTIMER_IRQ input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "PWM0_IRQ input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "PWM1_IRQ input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_IRQ input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "QDC1_IRQ input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "RTC_Alarm_IRQ input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "RTC_1Hz_IRQ input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "uTICK_IRQ input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "WDT_IRQ input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "Wakeup_Timer_IRQ input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "CAN0_IRQ input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "CAN1_IRQ input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "FlexIO_IRQ input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "FlexIO_Shifer0_DMA_Req input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "FlexIO_Shifer1_DMA_Req input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "FlexIO_Shifer2_DMA_Req input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "FlexIO_Shifer3_DMA_Req input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "I3C0_IRQ input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPI2C0_IRQ input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPI2C1_IRQ input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPSPI0_IRQ input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPSPI1_IRQ input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART0_IRQ input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART1_IRQ input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2_IRQ input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3_IRQ input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "USB0_SOF input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "ADC0_IRQ input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "ADC1_IRQ input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "ADC2_IRQ input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "ADC3_IRQ input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "CMP0_IRQ input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "CMP1_IRQ input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "CMP2_IRQ input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "CMP0_OUT input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "CMP1_OUT input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "CMP2_OUT input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "DAC0_IRQ input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "SLCD_IRQ input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for SmartDMA."] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for SmartDMA."] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "SmartDMA Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dma_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dma_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SmartDmaTrigSpec; +impl crate::RegisterSpec for SmartDmaTrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`smart_dma_trig::R`](R) reader structure"] +impl crate::Readable for SmartDmaTrigSpec {} +#[doc = "`write(|w| ..)` method takes [`smart_dma_trig::W`](W) writer structure"] +impl crate::Writable for SmartDmaTrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SmartDMA_TRIG[%s] to value 0x7f"] +impl crate::Resettable for SmartDmaTrigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/timer0trig.rs b/mcxa276-pac/src/inputmux0/timer0trig.rs new file mode 100644 index 000000000..fb53737c9 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/timer0trig.rs @@ -0,0 +1,1471 @@ +#[doc = "Register `TIMER0TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER0TRIG` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER0\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer1_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer1_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer1_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer2_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer2_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer2_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer3_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer3_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer3_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER0"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER0"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER0"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER0"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Trigger register for TIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`timer0trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Timer0trigSpec; +impl crate::RegisterSpec for Timer0trigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer0trig::R`](R) reader structure"] +impl crate::Readable for Timer0trigSpec {} +#[doc = "`write(|w| ..)` method takes [`timer0trig::W`](W) writer structure"] +impl crate::Writable for Timer0trigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMER0TRIG to value 0x7f"] +impl crate::Resettable for Timer0trigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/timer1trig.rs b/mcxa276-pac/src/inputmux0/timer1trig.rs new file mode 100644 index 000000000..3b95505c2 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/timer1trig.rs @@ -0,0 +1,1471 @@ +#[doc = "Register `TIMER1TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER1TRIG` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER1\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer2_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer2_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer2_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer3_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer3_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer3_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER1"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER1"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER1"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER1"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Trigger register for TIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Timer1trigSpec; +impl crate::RegisterSpec for Timer1trigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer1trig::R`](R) reader structure"] +impl crate::Readable for Timer1trigSpec {} +#[doc = "`write(|w| ..)` method takes [`timer1trig::W`](W) writer structure"] +impl crate::Writable for Timer1trigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMER1TRIG to value 0x7f"] +impl crate::Resettable for Timer1trigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/timer2trig.rs b/mcxa276-pac/src/inputmux0/timer2trig.rs new file mode 100644 index 000000000..4df66adc8 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/timer2trig.rs @@ -0,0 +1,1471 @@ +#[doc = "Register `TIMER2TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER2TRIG` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER2\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer1_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer1_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer1_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer3_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer3_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer3_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER2"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER2"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER2"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER2"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Trigger register for TIMER2 inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Timer2trigSpec; +impl crate::RegisterSpec for Timer2trigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer2trig::R`](R) reader structure"] +impl crate::Readable for Timer2trigSpec {} +#[doc = "`write(|w| ..)` method takes [`timer2trig::W`](W) writer structure"] +impl crate::Writable for Timer2trigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMER2TRIG to value 0x7f"] +impl crate::Resettable for Timer2trigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/timer3trig.rs b/mcxa276-pac/src/inputmux0/timer3trig.rs new file mode 100644 index 000000000..46fe97bf5 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/timer3trig.rs @@ -0,0 +1,1627 @@ +#[doc = "Register `TIMER3TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER3TRIG` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER3\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer1_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer1_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer1_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer2_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer2_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer2_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer4_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer4_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer4_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, + #[doc = "113: TRIG_IN0 input is selected"] + Val113 = 113, + #[doc = "114: TRIG_IN1 input is selected"] + Val114 = 114, + #[doc = "115: TRIG_IN2 input is selected"] + Val115 = 115, + #[doc = "116: TRIG_IN3 input is selected"] + Val116 = 116, + #[doc = "117: TRIG_IN4 input is selected"] + Val117 = 117, + #[doc = "118: TRIG_IN5 input is selected"] + Val118 = 118, + #[doc = "119: TRIG_IN6 input is selected"] + Val119 = 119, + #[doc = "120: TRIG_IN7 input is selected"] + Val120 = 120, + #[doc = "121: TRIG_IN8 input is selected"] + Val121 = 121, + #[doc = "122: TRIG_IN9 input is selected"] + Val122 = 122, + #[doc = "123: TRIG_IN10 input is selected"] + Val123 = 123, + #[doc = "124: TRIG_IN11 input is selected"] + Val124 = 124, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER3"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + 113 => Some(Inp::Val113), + 114 => Some(Inp::Val114), + 115 => Some(Inp::Val115), + 116 => Some(Inp::Val116), + 117 => Some(Inp::Val117), + 118 => Some(Inp::Val118), + 119 => Some(Inp::Val119), + 120 => Some(Inp::Val120), + 121 => Some(Inp::Val121), + 122 => Some(Inp::Val122), + 123 => Some(Inp::Val123), + 124 => Some(Inp::Val124), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val113(&self) -> bool { + *self == Inp::Val113 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val114(&self) -> bool { + *self == Inp::Val114 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val115(&self) -> bool { + *self == Inp::Val115 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val116(&self) -> bool { + *self == Inp::Val116 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val117(&self) -> bool { + *self == Inp::Val117 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val118(&self) -> bool { + *self == Inp::Val118 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val119(&self) -> bool { + *self == Inp::Val119 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val120(&self) -> bool { + *self == Inp::Val120 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val121(&self) -> bool { + *self == Inp::Val121 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val122(&self) -> bool { + *self == Inp::Val122 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val123(&self) -> bool { + *self == Inp::Val123 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val124(&self) -> bool { + *self == Inp::Val124 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER3"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer4_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer4_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer4_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val113(self) -> &'a mut crate::W { + self.variant(Inp::Val113) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val114(self) -> &'a mut crate::W { + self.variant(Inp::Val114) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val115(self) -> &'a mut crate::W { + self.variant(Inp::Val115) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val116(self) -> &'a mut crate::W { + self.variant(Inp::Val116) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val117(self) -> &'a mut crate::W { + self.variant(Inp::Val117) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val118(self) -> &'a mut crate::W { + self.variant(Inp::Val118) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val119(self) -> &'a mut crate::W { + self.variant(Inp::Val119) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val120(self) -> &'a mut crate::W { + self.variant(Inp::Val120) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val121(self) -> &'a mut crate::W { + self.variant(Inp::Val121) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val122(self) -> &'a mut crate::W { + self.variant(Inp::Val122) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val123(self) -> &'a mut crate::W { + self.variant(Inp::Val123) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val124(self) -> &'a mut crate::W { + self.variant(Inp::Val124) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER3"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER3"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Trigger register for TIMER3\n\nYou can [`read`](crate::Reg::read) this register and get [`timer3trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Timer3trigSpec; +impl crate::RegisterSpec for Timer3trigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer3trig::R`](R) reader structure"] +impl crate::Readable for Timer3trigSpec {} +#[doc = "`write(|w| ..)` method takes [`timer3trig::W`](W) writer structure"] +impl crate::Writable for Timer3trigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMER3TRIG to value 0x7f"] +impl crate::Resettable for Timer3trigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/timer4trig.rs b/mcxa276-pac/src/inputmux0/timer4trig.rs new file mode 100644 index 000000000..d86e8e10b --- /dev/null +++ b/mcxa276-pac/src/inputmux0/timer4trig.rs @@ -0,0 +1,1627 @@ +#[doc = "Register `TIMER4TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER4TRIG` writer"] +pub type W = crate::W; +#[doc = "Input number for CTIMER4\n\nValue on reset: 127"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: CT_INP0 input is selected"] + Val1 = 1, + #[doc = "2: CT_INP1 input is selected"] + Val2 = 2, + #[doc = "3: CT_INP2 input is selected"] + Val3 = 3, + #[doc = "4: CT_INP3 input is selected"] + Val4 = 4, + #[doc = "5: CT_INP4 input is selected"] + Val5 = 5, + #[doc = "6: CT_INP5 input is selected"] + Val6 = 6, + #[doc = "7: CT_INP6 input is selected"] + Val7 = 7, + #[doc = "8: CT_INP7 input is selected"] + Val8 = 8, + #[doc = "9: CT_INP8 input is selected"] + Val9 = 9, + #[doc = "10: CT_INP9 input is selected"] + Val10 = 10, + #[doc = "11: CT_INP10 input is selected"] + Val11 = 11, + #[doc = "12: CT_INP11 input is selected"] + Val12 = 12, + #[doc = "13: CT_INP12 input is selected"] + Val13 = 13, + #[doc = "14: CT_INP13 input is selected"] + Val14 = 14, + #[doc = "15: CT_INP14 input is selected"] + Val15 = 15, + #[doc = "16: CT_INP15 input is selected"] + Val16 = 16, + #[doc = "17: CT_INP16 input is selected"] + Val17 = 17, + #[doc = "18: CT_INP17 input is selected"] + Val18 = 18, + #[doc = "19: CT_INP18 input is selected"] + Val19 = 19, + #[doc = "20: CT_INP19 input is selected"] + Val20 = 20, + #[doc = "21: USB0 usb0 start of frame input is selected"] + Val21 = 21, + #[doc = "22: AOI0_OUT0 input is selected"] + Val22 = 22, + #[doc = "23: AOI0_OUT1 input is selected"] + Val23 = 23, + #[doc = "24: AOI0_OUT2 input is selected"] + Val24 = 24, + #[doc = "25: AOI0_OUT3 input is selected"] + Val25 = 25, + #[doc = "26: ADC0_tcomp\\[0\\]"] + Val26 = 26, + #[doc = "27: ADC0_tcomp\\[1\\]"] + Val27 = 27, + #[doc = "28: ADC0_tcomp\\[2\\]"] + Val28 = 28, + #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] + Val29 = 29, + #[doc = "30: CMP0_OUT is selected"] + Val30 = 30, + #[doc = "31: CMP1_OUT is selected"] + Val31 = 31, + #[doc = "32: CMP2_OUT is selected"] + Val32 = 32, + #[doc = "33: CTimer0_MAT1 input is selected"] + Val33 = 33, + #[doc = "34: CTimer0_MAT2 input is selected"] + Val34 = 34, + #[doc = "35: CTimer0_MAT3 input is selected"] + Val35 = 35, + #[doc = "36: CTimer1_MAT1 input is selected"] + Val36 = 36, + #[doc = "37: CTimer1_MAT2 input is selected"] + Val37 = 37, + #[doc = "38: CTimer1_MAT3 input is selected"] + Val38 = 38, + #[doc = "39: QDC0_CMP_FLAG0 is selected"] + Val39 = 39, + #[doc = "40: QDC0_CMP_FLAG1 input is selected"] + Val40 = 40, + #[doc = "41: QDC0_CMP_FLAG2 input is selected"] + Val41 = 41, + #[doc = "42: QDC0_CMP_FLAG3 input is selected"] + Val42 = 42, + #[doc = "43: QDC0_POS_MATCH0 input is selected"] + Val43 = 43, + #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] + Val44 = 44, + #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] + Val45 = 45, + #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] + Val46 = 46, + #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] + Val47 = 47, + #[doc = "48: LPI2C0 Master End of Packet input is selected"] + Val48 = 48, + #[doc = "49: LPI2C0 Slave End of Packet input is selected"] + Val49 = 49, + #[doc = "50: LPI2C1 Master End of Packet input is selected"] + Val50 = 50, + #[doc = "51: LPI2C1 Slave End of Packet input is selected"] + Val51 = 51, + #[doc = "52: LPSPI0 End of Frame input is selected"] + Val52 = 52, + #[doc = "53: LPSPI0 Received Data Word input is selected"] + Val53 = 53, + #[doc = "54: LPSPI1 End of Frame input is selected"] + Val54 = 54, + #[doc = "55: LPSPI1 Received Data Word input is selected"] + Val55 = 55, + #[doc = "56: LPUART0 Received Data Word input is selected"] + Val56 = 56, + #[doc = "57: LPUART0 Transmitted Data Word input is selected"] + Val57 = 57, + #[doc = "58: LPUART0 Receive Line Idle input is selected"] + Val58 = 58, + #[doc = "59: LPUART1 Received Data Word input is selected"] + Val59 = 59, + #[doc = "60: LPUART1 Transmitted Data Word input is selected"] + Val60 = 60, + #[doc = "61: LPUART1 Receive Line Idle input is selected"] + Val61 = 61, + #[doc = "62: LPUART2 Received Data Word input is selected"] + Val62 = 62, + #[doc = "63: LPUART2 Transmitted Data Word input is selected"] + Val63 = 63, + #[doc = "64: LPUART2 Receive Line Idle input is selected"] + Val64 = 64, + #[doc = "65: LPUART3 Received Data Word input is selected"] + Val65 = 65, + #[doc = "66: LPUART3 Transmitted Data Word input is selected"] + Val66 = 66, + #[doc = "67: LPUART3 Receive Line Idle input is selected"] + Val67 = 67, + #[doc = "68: LPUART4 Received Data Word input is selected"] + Val68 = 68, + #[doc = "69: LPUART4 Transmitted Data Word input is selected"] + Val69 = 69, + #[doc = "70: LPUART4 Receive Line Idle input is selected"] + Val70 = 70, + #[doc = "71: AOI1_OUT0 input is selected"] + Val71 = 71, + #[doc = "72: AOI1_OUT1 input is selected"] + Val72 = 72, + #[doc = "73: AOI1_OUT2 input is selected"] + Val73 = 73, + #[doc = "74: AOI1_OUT3 input is selected"] + Val74 = 74, + #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] + Val75 = 75, + #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] + Val76 = 76, + #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] + Val77 = 77, + #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] + Val78 = 78, + #[doc = "79: CTimer2_MAT1 input is selected"] + Val79 = 79, + #[doc = "80: CTimer2_MAT2 input is selected"] + Val80 = 80, + #[doc = "81: CTimer2_MAT3 input is selected"] + Val81 = 81, + #[doc = "82: CTimer3_MAT1 input is selected"] + Val82 = 82, + #[doc = "83: CTimer3_MAT2 input is selected"] + Val83 = 83, + #[doc = "84: CTimer3_MAT3 input is selected"] + Val84 = 84, + #[doc = "85: QDC1_CMP_FLAG0 input is selected"] + Val85 = 85, + #[doc = "86: QDC1_CMP_FLAG1 input is selected"] + Val86 = 86, + #[doc = "87: QDC1_CMP_FLAG2 input is selected"] + Val87 = 87, + #[doc = "88: QDC1_CMP_FLAG3 input is selected"] + Val88 = 88, + #[doc = "89: QDC1_POS_MATCH0 input is selected"] + Val89 = 89, + #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] + Val90 = 90, + #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] + Val91 = 91, + #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] + Val92 = 92, + #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] + Val93 = 93, + #[doc = "94: LPI2C2 Master End of Packet input is selected"] + Val94 = 94, + #[doc = "95: LPI2C2 Slave End of Packet input is selected"] + Val95 = 95, + #[doc = "96: LPI2C3 Master End of Packet input is selected"] + Val96 = 96, + #[doc = "97: LPI2C3 Slave End of Packet input is selected"] + Val97 = 97, + #[doc = "98: LPUART5 Received Data Word input is selected"] + Val98 = 98, + #[doc = "99: LPUART5 Transmitted Data Word input is selected"] + Val99 = 99, + #[doc = "100: LPUART5 Receive Line Idle input is selected"] + Val100 = 100, + #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] + Val105 = 105, + #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] + Val106 = 106, + #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] + Val107 = 107, + #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] + Val108 = 108, + #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] + Val109 = 109, + #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] + Val110 = 110, + #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] + Val111 = 111, + #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] + Val112 = 112, + #[doc = "113: TRIG_IN0 input is selected"] + Val113 = 113, + #[doc = "114: TRIG_IN1 input is selected"] + Val114 = 114, + #[doc = "115: TRIG_IN2 input is selected"] + Val115 = 115, + #[doc = "116: TRIG_IN3 input is selected"] + Val116 = 116, + #[doc = "117: TRIG_IN4 input is selected"] + Val117 = 117, + #[doc = "118: TRIG_IN5 input is selected"] + Val118 = 118, + #[doc = "119: TRIG_IN6 input is selected"] + Val119 = 119, + #[doc = "120: TRIG_IN7 input is selected"] + Val120 = 120, + #[doc = "121: TRIG_IN8 input is selected"] + Val121 = 121, + #[doc = "122: TRIG_IN9 input is selected"] + Val122 = 122, + #[doc = "123: TRIG_IN10 input is selected"] + Val123 = 123, + #[doc = "124: TRIG_IN11 input is selected"] + Val124 = 124, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - Input number for CTIMER4"] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + 7 => Some(Inp::Val7), + 8 => Some(Inp::Val8), + 9 => Some(Inp::Val9), + 10 => Some(Inp::Val10), + 11 => Some(Inp::Val11), + 12 => Some(Inp::Val12), + 13 => Some(Inp::Val13), + 14 => Some(Inp::Val14), + 15 => Some(Inp::Val15), + 16 => Some(Inp::Val16), + 17 => Some(Inp::Val17), + 18 => Some(Inp::Val18), + 19 => Some(Inp::Val19), + 20 => Some(Inp::Val20), + 21 => Some(Inp::Val21), + 22 => Some(Inp::Val22), + 23 => Some(Inp::Val23), + 24 => Some(Inp::Val24), + 25 => Some(Inp::Val25), + 26 => Some(Inp::Val26), + 27 => Some(Inp::Val27), + 28 => Some(Inp::Val28), + 29 => Some(Inp::Val29), + 30 => Some(Inp::Val30), + 31 => Some(Inp::Val31), + 32 => Some(Inp::Val32), + 33 => Some(Inp::Val33), + 34 => Some(Inp::Val34), + 35 => Some(Inp::Val35), + 36 => Some(Inp::Val36), + 37 => Some(Inp::Val37), + 38 => Some(Inp::Val38), + 39 => Some(Inp::Val39), + 40 => Some(Inp::Val40), + 41 => Some(Inp::Val41), + 42 => Some(Inp::Val42), + 43 => Some(Inp::Val43), + 44 => Some(Inp::Val44), + 45 => Some(Inp::Val45), + 46 => Some(Inp::Val46), + 47 => Some(Inp::Val47), + 48 => Some(Inp::Val48), + 49 => Some(Inp::Val49), + 50 => Some(Inp::Val50), + 51 => Some(Inp::Val51), + 52 => Some(Inp::Val52), + 53 => Some(Inp::Val53), + 54 => Some(Inp::Val54), + 55 => Some(Inp::Val55), + 56 => Some(Inp::Val56), + 57 => Some(Inp::Val57), + 58 => Some(Inp::Val58), + 59 => Some(Inp::Val59), + 60 => Some(Inp::Val60), + 61 => Some(Inp::Val61), + 62 => Some(Inp::Val62), + 63 => Some(Inp::Val63), + 64 => Some(Inp::Val64), + 65 => Some(Inp::Val65), + 66 => Some(Inp::Val66), + 67 => Some(Inp::Val67), + 68 => Some(Inp::Val68), + 69 => Some(Inp::Val69), + 70 => Some(Inp::Val70), + 71 => Some(Inp::Val71), + 72 => Some(Inp::Val72), + 73 => Some(Inp::Val73), + 74 => Some(Inp::Val74), + 75 => Some(Inp::Val75), + 76 => Some(Inp::Val76), + 77 => Some(Inp::Val77), + 78 => Some(Inp::Val78), + 79 => Some(Inp::Val79), + 80 => Some(Inp::Val80), + 81 => Some(Inp::Val81), + 82 => Some(Inp::Val82), + 83 => Some(Inp::Val83), + 84 => Some(Inp::Val84), + 85 => Some(Inp::Val85), + 86 => Some(Inp::Val86), + 87 => Some(Inp::Val87), + 88 => Some(Inp::Val88), + 89 => Some(Inp::Val89), + 90 => Some(Inp::Val90), + 91 => Some(Inp::Val91), + 92 => Some(Inp::Val92), + 93 => Some(Inp::Val93), + 94 => Some(Inp::Val94), + 95 => Some(Inp::Val95), + 96 => Some(Inp::Val96), + 97 => Some(Inp::Val97), + 98 => Some(Inp::Val98), + 99 => Some(Inp::Val99), + 100 => Some(Inp::Val100), + 105 => Some(Inp::Val105), + 106 => Some(Inp::Val106), + 107 => Some(Inp::Val107), + 108 => Some(Inp::Val108), + 109 => Some(Inp::Val109), + 110 => Some(Inp::Val110), + 111 => Some(Inp::Val111), + 112 => Some(Inp::Val112), + 113 => Some(Inp::Val113), + 114 => Some(Inp::Val114), + 115 => Some(Inp::Val115), + 116 => Some(Inp::Val116), + 117 => Some(Inp::Val117), + 118 => Some(Inp::Val118), + 119 => Some(Inp::Val119), + 120 => Some(Inp::Val120), + 121 => Some(Inp::Val121), + 122 => Some(Inp::Val122), + 123 => Some(Inp::Val123), + 124 => Some(Inp::Val124), + _ => None, + } + } + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn is_val7(&self) -> bool { + *self == Inp::Val7 + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn is_val8(&self) -> bool { + *self == Inp::Val8 + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn is_val9(&self) -> bool { + *self == Inp::Val9 + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn is_val10(&self) -> bool { + *self == Inp::Val10 + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn is_val11(&self) -> bool { + *self == Inp::Val11 + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn is_val12(&self) -> bool { + *self == Inp::Val12 + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn is_val13(&self) -> bool { + *self == Inp::Val13 + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn is_val14(&self) -> bool { + *self == Inp::Val14 + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn is_val15(&self) -> bool { + *self == Inp::Val15 + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn is_val16(&self) -> bool { + *self == Inp::Val16 + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn is_val17(&self) -> bool { + *self == Inp::Val17 + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn is_val18(&self) -> bool { + *self == Inp::Val18 + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn is_val19(&self) -> bool { + *self == Inp::Val19 + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn is_val20(&self) -> bool { + *self == Inp::Val20 + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn is_val21(&self) -> bool { + *self == Inp::Val21 + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn is_val22(&self) -> bool { + *self == Inp::Val22 + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn is_val23(&self) -> bool { + *self == Inp::Val23 + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn is_val24(&self) -> bool { + *self == Inp::Val24 + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn is_val25(&self) -> bool { + *self == Inp::Val25 + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn is_val26(&self) -> bool { + *self == Inp::Val26 + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn is_val27(&self) -> bool { + *self == Inp::Val27 + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn is_val28(&self) -> bool { + *self == Inp::Val28 + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val29(&self) -> bool { + *self == Inp::Val29 + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn is_val30(&self) -> bool { + *self == Inp::Val30 + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn is_val31(&self) -> bool { + *self == Inp::Val31 + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn is_val32(&self) -> bool { + *self == Inp::Val32 + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn is_val33(&self) -> bool { + *self == Inp::Val33 + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn is_val34(&self) -> bool { + *self == Inp::Val34 + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn is_val35(&self) -> bool { + *self == Inp::Val35 + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn is_val36(&self) -> bool { + *self == Inp::Val36 + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn is_val37(&self) -> bool { + *self == Inp::Val37 + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn is_val38(&self) -> bool { + *self == Inp::Val38 + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn is_val39(&self) -> bool { + *self == Inp::Val39 + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val40(&self) -> bool { + *self == Inp::Val40 + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val41(&self) -> bool { + *self == Inp::Val41 + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val42(&self) -> bool { + *self == Inp::Val42 + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val43(&self) -> bool { + *self == Inp::Val43 + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val44(&self) -> bool { + *self == Inp::Val44 + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val45(&self) -> bool { + *self == Inp::Val45 + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val46(&self) -> bool { + *self == Inp::Val46 + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val47(&self) -> bool { + *self == Inp::Val47 + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val48(&self) -> bool { + *self == Inp::Val48 + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val49(&self) -> bool { + *self == Inp::Val49 + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val50(&self) -> bool { + *self == Inp::Val50 + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val51(&self) -> bool { + *self == Inp::Val51 + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn is_val52(&self) -> bool { + *self == Inp::Val52 + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val53(&self) -> bool { + *self == Inp::Val53 + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn is_val54(&self) -> bool { + *self == Inp::Val54 + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val55(&self) -> bool { + *self == Inp::Val55 + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val56(&self) -> bool { + *self == Inp::Val56 + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val57(&self) -> bool { + *self == Inp::Val57 + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val58(&self) -> bool { + *self == Inp::Val58 + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val59(&self) -> bool { + *self == Inp::Val59 + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val60(&self) -> bool { + *self == Inp::Val60 + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val61(&self) -> bool { + *self == Inp::Val61 + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val62(&self) -> bool { + *self == Inp::Val62 + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val63(&self) -> bool { + *self == Inp::Val63 + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val64(&self) -> bool { + *self == Inp::Val64 + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val65(&self) -> bool { + *self == Inp::Val65 + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val66(&self) -> bool { + *self == Inp::Val66 + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val67(&self) -> bool { + *self == Inp::Val67 + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val68(&self) -> bool { + *self == Inp::Val68 + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val69(&self) -> bool { + *self == Inp::Val69 + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val70(&self) -> bool { + *self == Inp::Val70 + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn is_val71(&self) -> bool { + *self == Inp::Val71 + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn is_val72(&self) -> bool { + *self == Inp::Val72 + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn is_val73(&self) -> bool { + *self == Inp::Val73 + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn is_val74(&self) -> bool { + *self == Inp::Val74 + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val75(&self) -> bool { + *self == Inp::Val75 + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val76(&self) -> bool { + *self == Inp::Val76 + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val77(&self) -> bool { + *self == Inp::Val77 + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val78(&self) -> bool { + *self == Inp::Val78 + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn is_val79(&self) -> bool { + *self == Inp::Val79 + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn is_val80(&self) -> bool { + *self == Inp::Val80 + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn is_val81(&self) -> bool { + *self == Inp::Val81 + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn is_val82(&self) -> bool { + *self == Inp::Val82 + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn is_val83(&self) -> bool { + *self == Inp::Val83 + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn is_val84(&self) -> bool { + *self == Inp::Val84 + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn is_val85(&self) -> bool { + *self == Inp::Val85 + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn is_val86(&self) -> bool { + *self == Inp::Val86 + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn is_val87(&self) -> bool { + *self == Inp::Val87 + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn is_val88(&self) -> bool { + *self == Inp::Val88 + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn is_val89(&self) -> bool { + *self == Inp::Val89 + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val90(&self) -> bool { + *self == Inp::Val90 + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val91(&self) -> bool { + *self == Inp::Val91 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val92(&self) -> bool { + *self == Inp::Val92 + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn is_val93(&self) -> bool { + *self == Inp::Val93 + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val94(&self) -> bool { + *self == Inp::Val94 + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val95(&self) -> bool { + *self == Inp::Val95 + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn is_val96(&self) -> bool { + *self == Inp::Val96 + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn is_val97(&self) -> bool { + *self == Inp::Val97 + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn is_val98(&self) -> bool { + *self == Inp::Val98 + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn is_val99(&self) -> bool { + *self == Inp::Val99 + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn is_val100(&self) -> bool { + *self == Inp::Val100 + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val105(&self) -> bool { + *self == Inp::Val105 + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val106(&self) -> bool { + *self == Inp::Val106 + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val107(&self) -> bool { + *self == Inp::Val107 + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val108(&self) -> bool { + *self == Inp::Val108 + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn is_val109(&self) -> bool { + *self == Inp::Val109 + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn is_val110(&self) -> bool { + *self == Inp::Val110 + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn is_val111(&self) -> bool { + *self == Inp::Val111 + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn is_val112(&self) -> bool { + *self == Inp::Val112 + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn is_val113(&self) -> bool { + *self == Inp::Val113 + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn is_val114(&self) -> bool { + *self == Inp::Val114 + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn is_val115(&self) -> bool { + *self == Inp::Val115 + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn is_val116(&self) -> bool { + *self == Inp::Val116 + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn is_val117(&self) -> bool { + *self == Inp::Val117 + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn is_val118(&self) -> bool { + *self == Inp::Val118 + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn is_val119(&self) -> bool { + *self == Inp::Val119 + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn is_val120(&self) -> bool { + *self == Inp::Val120 + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn is_val121(&self) -> bool { + *self == Inp::Val121 + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn is_val122(&self) -> bool { + *self == Inp::Val122 + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn is_val123(&self) -> bool { + *self == Inp::Val123 + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn is_val124(&self) -> bool { + *self == Inp::Val124 + } +} +#[doc = "Field `INP` writer - Input number for CTIMER4"] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT_INP0 input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "CT_INP1 input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "CT_INP2 input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "CT_INP3 input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "CT_INP4 input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "CT_INP5 input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } + #[doc = "CT_INP6 input is selected"] + #[inline(always)] + pub fn val7(self) -> &'a mut crate::W { + self.variant(Inp::Val7) + } + #[doc = "CT_INP7 input is selected"] + #[inline(always)] + pub fn val8(self) -> &'a mut crate::W { + self.variant(Inp::Val8) + } + #[doc = "CT_INP8 input is selected"] + #[inline(always)] + pub fn val9(self) -> &'a mut crate::W { + self.variant(Inp::Val9) + } + #[doc = "CT_INP9 input is selected"] + #[inline(always)] + pub fn val10(self) -> &'a mut crate::W { + self.variant(Inp::Val10) + } + #[doc = "CT_INP10 input is selected"] + #[inline(always)] + pub fn val11(self) -> &'a mut crate::W { + self.variant(Inp::Val11) + } + #[doc = "CT_INP11 input is selected"] + #[inline(always)] + pub fn val12(self) -> &'a mut crate::W { + self.variant(Inp::Val12) + } + #[doc = "CT_INP12 input is selected"] + #[inline(always)] + pub fn val13(self) -> &'a mut crate::W { + self.variant(Inp::Val13) + } + #[doc = "CT_INP13 input is selected"] + #[inline(always)] + pub fn val14(self) -> &'a mut crate::W { + self.variant(Inp::Val14) + } + #[doc = "CT_INP14 input is selected"] + #[inline(always)] + pub fn val15(self) -> &'a mut crate::W { + self.variant(Inp::Val15) + } + #[doc = "CT_INP15 input is selected"] + #[inline(always)] + pub fn val16(self) -> &'a mut crate::W { + self.variant(Inp::Val16) + } + #[doc = "CT_INP16 input is selected"] + #[inline(always)] + pub fn val17(self) -> &'a mut crate::W { + self.variant(Inp::Val17) + } + #[doc = "CT_INP17 input is selected"] + #[inline(always)] + pub fn val18(self) -> &'a mut crate::W { + self.variant(Inp::Val18) + } + #[doc = "CT_INP18 input is selected"] + #[inline(always)] + pub fn val19(self) -> &'a mut crate::W { + self.variant(Inp::Val19) + } + #[doc = "CT_INP19 input is selected"] + #[inline(always)] + pub fn val20(self) -> &'a mut crate::W { + self.variant(Inp::Val20) + } + #[doc = "USB0 usb0 start of frame input is selected"] + #[inline(always)] + pub fn val21(self) -> &'a mut crate::W { + self.variant(Inp::Val21) + } + #[doc = "AOI0_OUT0 input is selected"] + #[inline(always)] + pub fn val22(self) -> &'a mut crate::W { + self.variant(Inp::Val22) + } + #[doc = "AOI0_OUT1 input is selected"] + #[inline(always)] + pub fn val23(self) -> &'a mut crate::W { + self.variant(Inp::Val23) + } + #[doc = "AOI0_OUT2 input is selected"] + #[inline(always)] + pub fn val24(self) -> &'a mut crate::W { + self.variant(Inp::Val24) + } + #[doc = "AOI0_OUT3 input is selected"] + #[inline(always)] + pub fn val25(self) -> &'a mut crate::W { + self.variant(Inp::Val25) + } + #[doc = "ADC0_tcomp\\[0\\]"] + #[inline(always)] + pub fn val26(self) -> &'a mut crate::W { + self.variant(Inp::Val26) + } + #[doc = "ADC0_tcomp\\[1\\]"] + #[inline(always)] + pub fn val27(self) -> &'a mut crate::W { + self.variant(Inp::Val27) + } + #[doc = "ADC0_tcomp\\[2\\]"] + #[inline(always)] + pub fn val28(self) -> &'a mut crate::W { + self.variant(Inp::Val28) + } + #[doc = "ADC0_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val29(self) -> &'a mut crate::W { + self.variant(Inp::Val29) + } + #[doc = "CMP0_OUT is selected"] + #[inline(always)] + pub fn val30(self) -> &'a mut crate::W { + self.variant(Inp::Val30) + } + #[doc = "CMP1_OUT is selected"] + #[inline(always)] + pub fn val31(self) -> &'a mut crate::W { + self.variant(Inp::Val31) + } + #[doc = "CMP2_OUT is selected"] + #[inline(always)] + pub fn val32(self) -> &'a mut crate::W { + self.variant(Inp::Val32) + } + #[doc = "CTimer0_MAT1 input is selected"] + #[inline(always)] + pub fn val33(self) -> &'a mut crate::W { + self.variant(Inp::Val33) + } + #[doc = "CTimer0_MAT2 input is selected"] + #[inline(always)] + pub fn val34(self) -> &'a mut crate::W { + self.variant(Inp::Val34) + } + #[doc = "CTimer0_MAT3 input is selected"] + #[inline(always)] + pub fn val35(self) -> &'a mut crate::W { + self.variant(Inp::Val35) + } + #[doc = "CTimer1_MAT1 input is selected"] + #[inline(always)] + pub fn val36(self) -> &'a mut crate::W { + self.variant(Inp::Val36) + } + #[doc = "CTimer1_MAT2 input is selected"] + #[inline(always)] + pub fn val37(self) -> &'a mut crate::W { + self.variant(Inp::Val37) + } + #[doc = "CTimer1_MAT3 input is selected"] + #[inline(always)] + pub fn val38(self) -> &'a mut crate::W { + self.variant(Inp::Val38) + } + #[doc = "QDC0_CMP_FLAG0 is selected"] + #[inline(always)] + pub fn val39(self) -> &'a mut crate::W { + self.variant(Inp::Val39) + } + #[doc = "QDC0_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val40(self) -> &'a mut crate::W { + self.variant(Inp::Val40) + } + #[doc = "QDC0_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val41(self) -> &'a mut crate::W { + self.variant(Inp::Val41) + } + #[doc = "QDC0_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val42(self) -> &'a mut crate::W { + self.variant(Inp::Val42) + } + #[doc = "QDC0_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val43(self) -> &'a mut crate::W { + self.variant(Inp::Val43) + } + #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val44(self) -> &'a mut crate::W { + self.variant(Inp::Val44) + } + #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val45(self) -> &'a mut crate::W { + self.variant(Inp::Val45) + } + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val46(self) -> &'a mut crate::W { + self.variant(Inp::Val46) + } + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val47(self) -> &'a mut crate::W { + self.variant(Inp::Val47) + } + #[doc = "LPI2C0 Master End of Packet input is selected"] + #[inline(always)] + pub fn val48(self) -> &'a mut crate::W { + self.variant(Inp::Val48) + } + #[doc = "LPI2C0 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val49(self) -> &'a mut crate::W { + self.variant(Inp::Val49) + } + #[doc = "LPI2C1 Master End of Packet input is selected"] + #[inline(always)] + pub fn val50(self) -> &'a mut crate::W { + self.variant(Inp::Val50) + } + #[doc = "LPI2C1 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val51(self) -> &'a mut crate::W { + self.variant(Inp::Val51) + } + #[doc = "LPSPI0 End of Frame input is selected"] + #[inline(always)] + pub fn val52(self) -> &'a mut crate::W { + self.variant(Inp::Val52) + } + #[doc = "LPSPI0 Received Data Word input is selected"] + #[inline(always)] + pub fn val53(self) -> &'a mut crate::W { + self.variant(Inp::Val53) + } + #[doc = "LPSPI1 End of Frame input is selected"] + #[inline(always)] + pub fn val54(self) -> &'a mut crate::W { + self.variant(Inp::Val54) + } + #[doc = "LPSPI1 Received Data Word input is selected"] + #[inline(always)] + pub fn val55(self) -> &'a mut crate::W { + self.variant(Inp::Val55) + } + #[doc = "LPUART0 Received Data Word input is selected"] + #[inline(always)] + pub fn val56(self) -> &'a mut crate::W { + self.variant(Inp::Val56) + } + #[doc = "LPUART0 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val57(self) -> &'a mut crate::W { + self.variant(Inp::Val57) + } + #[doc = "LPUART0 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val58(self) -> &'a mut crate::W { + self.variant(Inp::Val58) + } + #[doc = "LPUART1 Received Data Word input is selected"] + #[inline(always)] + pub fn val59(self) -> &'a mut crate::W { + self.variant(Inp::Val59) + } + #[doc = "LPUART1 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val60(self) -> &'a mut crate::W { + self.variant(Inp::Val60) + } + #[doc = "LPUART1 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val61(self) -> &'a mut crate::W { + self.variant(Inp::Val61) + } + #[doc = "LPUART2 Received Data Word input is selected"] + #[inline(always)] + pub fn val62(self) -> &'a mut crate::W { + self.variant(Inp::Val62) + } + #[doc = "LPUART2 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val63(self) -> &'a mut crate::W { + self.variant(Inp::Val63) + } + #[doc = "LPUART2 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val64(self) -> &'a mut crate::W { + self.variant(Inp::Val64) + } + #[doc = "LPUART3 Received Data Word input is selected"] + #[inline(always)] + pub fn val65(self) -> &'a mut crate::W { + self.variant(Inp::Val65) + } + #[doc = "LPUART3 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val66(self) -> &'a mut crate::W { + self.variant(Inp::Val66) + } + #[doc = "LPUART3 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val67(self) -> &'a mut crate::W { + self.variant(Inp::Val67) + } + #[doc = "LPUART4 Received Data Word input is selected"] + #[inline(always)] + pub fn val68(self) -> &'a mut crate::W { + self.variant(Inp::Val68) + } + #[doc = "LPUART4 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val69(self) -> &'a mut crate::W { + self.variant(Inp::Val69) + } + #[doc = "LPUART4 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val70(self) -> &'a mut crate::W { + self.variant(Inp::Val70) + } + #[doc = "AOI1_OUT0 input is selected"] + #[inline(always)] + pub fn val71(self) -> &'a mut crate::W { + self.variant(Inp::Val71) + } + #[doc = "AOI1_OUT1 input is selected"] + #[inline(always)] + pub fn val72(self) -> &'a mut crate::W { + self.variant(Inp::Val72) + } + #[doc = "AOI1_OUT2 input is selected"] + #[inline(always)] + pub fn val73(self) -> &'a mut crate::W { + self.variant(Inp::Val73) + } + #[doc = "AOI1_OUT3 input is selected"] + #[inline(always)] + pub fn val74(self) -> &'a mut crate::W { + self.variant(Inp::Val74) + } + #[doc = "ADC1_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val75(self) -> &'a mut crate::W { + self.variant(Inp::Val75) + } + #[doc = "ADC1_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val76(self) -> &'a mut crate::W { + self.variant(Inp::Val76) + } + #[doc = "ADC1_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val77(self) -> &'a mut crate::W { + self.variant(Inp::Val77) + } + #[doc = "ADC1_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val78(self) -> &'a mut crate::W { + self.variant(Inp::Val78) + } + #[doc = "CTimer2_MAT1 input is selected"] + #[inline(always)] + pub fn val79(self) -> &'a mut crate::W { + self.variant(Inp::Val79) + } + #[doc = "CTimer2_MAT2 input is selected"] + #[inline(always)] + pub fn val80(self) -> &'a mut crate::W { + self.variant(Inp::Val80) + } + #[doc = "CTimer2_MAT3 input is selected"] + #[inline(always)] + pub fn val81(self) -> &'a mut crate::W { + self.variant(Inp::Val81) + } + #[doc = "CTimer3_MAT1 input is selected"] + #[inline(always)] + pub fn val82(self) -> &'a mut crate::W { + self.variant(Inp::Val82) + } + #[doc = "CTimer3_MAT2 input is selected"] + #[inline(always)] + pub fn val83(self) -> &'a mut crate::W { + self.variant(Inp::Val83) + } + #[doc = "CTimer3_MAT3 input is selected"] + #[inline(always)] + pub fn val84(self) -> &'a mut crate::W { + self.variant(Inp::Val84) + } + #[doc = "QDC1_CMP_FLAG0 input is selected"] + #[inline(always)] + pub fn val85(self) -> &'a mut crate::W { + self.variant(Inp::Val85) + } + #[doc = "QDC1_CMP_FLAG1 input is selected"] + #[inline(always)] + pub fn val86(self) -> &'a mut crate::W { + self.variant(Inp::Val86) + } + #[doc = "QDC1_CMP_FLAG2 input is selected"] + #[inline(always)] + pub fn val87(self) -> &'a mut crate::W { + self.variant(Inp::Val87) + } + #[doc = "QDC1_CMP_FLAG3 input is selected"] + #[inline(always)] + pub fn val88(self) -> &'a mut crate::W { + self.variant(Inp::Val88) + } + #[doc = "QDC1_POS_MATCH0 input is selected"] + #[inline(always)] + pub fn val89(self) -> &'a mut crate::W { + self.variant(Inp::Val89) + } + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val90(self) -> &'a mut crate::W { + self.variant(Inp::Val90) + } + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val91(self) -> &'a mut crate::W { + self.variant(Inp::Val91) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val92(self) -> &'a mut crate::W { + self.variant(Inp::Val92) + } + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] + #[inline(always)] + pub fn val93(self) -> &'a mut crate::W { + self.variant(Inp::Val93) + } + #[doc = "LPI2C2 Master End of Packet input is selected"] + #[inline(always)] + pub fn val94(self) -> &'a mut crate::W { + self.variant(Inp::Val94) + } + #[doc = "LPI2C2 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val95(self) -> &'a mut crate::W { + self.variant(Inp::Val95) + } + #[doc = "LPI2C3 Master End of Packet input is selected"] + #[inline(always)] + pub fn val96(self) -> &'a mut crate::W { + self.variant(Inp::Val96) + } + #[doc = "LPI2C3 Slave End of Packet input is selected"] + #[inline(always)] + pub fn val97(self) -> &'a mut crate::W { + self.variant(Inp::Val97) + } + #[doc = "LPUART5 Received Data Word input is selected"] + #[inline(always)] + pub fn val98(self) -> &'a mut crate::W { + self.variant(Inp::Val98) + } + #[doc = "LPUART5 Transmitted Data Word input is selected"] + #[inline(always)] + pub fn val99(self) -> &'a mut crate::W { + self.variant(Inp::Val99) + } + #[doc = "LPUART5 Receive Line Idle input is selected"] + #[inline(always)] + pub fn val100(self) -> &'a mut crate::W { + self.variant(Inp::Val100) + } + #[doc = "ADC2_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val105(self) -> &'a mut crate::W { + self.variant(Inp::Val105) + } + #[doc = "ADC2_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val106(self) -> &'a mut crate::W { + self.variant(Inp::Val106) + } + #[doc = "ADC2_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val107(self) -> &'a mut crate::W { + self.variant(Inp::Val107) + } + #[doc = "ADC2_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val108(self) -> &'a mut crate::W { + self.variant(Inp::Val108) + } + #[doc = "ADC3_tcomp\\[0\\] input is selected"] + #[inline(always)] + pub fn val109(self) -> &'a mut crate::W { + self.variant(Inp::Val109) + } + #[doc = "ADC3_tcomp\\[1\\] input is selected"] + #[inline(always)] + pub fn val110(self) -> &'a mut crate::W { + self.variant(Inp::Val110) + } + #[doc = "ADC3_tcomp\\[2\\] input is selected"] + #[inline(always)] + pub fn val111(self) -> &'a mut crate::W { + self.variant(Inp::Val111) + } + #[doc = "ADC3_tcomp\\[3\\] input is selected"] + #[inline(always)] + pub fn val112(self) -> &'a mut crate::W { + self.variant(Inp::Val112) + } + #[doc = "TRIG_IN0 input is selected"] + #[inline(always)] + pub fn val113(self) -> &'a mut crate::W { + self.variant(Inp::Val113) + } + #[doc = "TRIG_IN1 input is selected"] + #[inline(always)] + pub fn val114(self) -> &'a mut crate::W { + self.variant(Inp::Val114) + } + #[doc = "TRIG_IN2 input is selected"] + #[inline(always)] + pub fn val115(self) -> &'a mut crate::W { + self.variant(Inp::Val115) + } + #[doc = "TRIG_IN3 input is selected"] + #[inline(always)] + pub fn val116(self) -> &'a mut crate::W { + self.variant(Inp::Val116) + } + #[doc = "TRIG_IN4 input is selected"] + #[inline(always)] + pub fn val117(self) -> &'a mut crate::W { + self.variant(Inp::Val117) + } + #[doc = "TRIG_IN5 input is selected"] + #[inline(always)] + pub fn val118(self) -> &'a mut crate::W { + self.variant(Inp::Val118) + } + #[doc = "TRIG_IN6 input is selected"] + #[inline(always)] + pub fn val119(self) -> &'a mut crate::W { + self.variant(Inp::Val119) + } + #[doc = "TRIG_IN7 input is selected"] + #[inline(always)] + pub fn val120(self) -> &'a mut crate::W { + self.variant(Inp::Val120) + } + #[doc = "TRIG_IN8 input is selected"] + #[inline(always)] + pub fn val121(self) -> &'a mut crate::W { + self.variant(Inp::Val121) + } + #[doc = "TRIG_IN9 input is selected"] + #[inline(always)] + pub fn val122(self) -> &'a mut crate::W { + self.variant(Inp::Val122) + } + #[doc = "TRIG_IN10 input is selected"] + #[inline(always)] + pub fn val123(self) -> &'a mut crate::W { + self.variant(Inp::Val123) + } + #[doc = "TRIG_IN11 input is selected"] + #[inline(always)] + pub fn val124(self) -> &'a mut crate::W { + self.variant(Inp::Val124) + } +} +impl R { + #[doc = "Bits 0:6 - Input number for CTIMER4"] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Input number for CTIMER4"] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "Trigger register for TIMER4\n\nYou can [`read`](crate::Reg::read) this register and get [`timer4trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer4trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Timer4trigSpec; +impl crate::RegisterSpec for Timer4trigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer4trig::R`](R) reader structure"] +impl crate::Readable for Timer4trigSpec {} +#[doc = "`write(|w| ..)` method takes [`timer4trig::W`](W) writer structure"] +impl crate::Writable for Timer4trigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMER4TRIG to value 0x7f"] +impl crate::Resettable for Timer4trigSpec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/mcxa276-pac/src/inputmux0/trigfil.rs b/mcxa276-pac/src/inputmux0/trigfil.rs new file mode 100644 index 000000000..be56269fa --- /dev/null +++ b/mcxa276-pac/src/inputmux0/trigfil.rs @@ -0,0 +1,49 @@ +#[doc = "Register `TRIGFIL[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `TRIGFIL[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `FILT_PER` reader - Input Filter Sample Period"] +pub type FiltPerR = crate::FieldReader; +#[doc = "Field `FILT_PER` writer - Input Filter Sample Period"] +pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `FILT_CNT` reader - Input Filter Sample Count"] +pub type FiltCntR = crate::FieldReader; +#[doc = "Field `FILT_CNT` writer - Input Filter Sample Count"] +pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:7 - Input Filter Sample Period"] + #[inline(always)] + pub fn filt_per(&self) -> FiltPerR { + FiltPerR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Input Filter Sample Count"] + #[inline(always)] + pub fn filt_cnt(&self) -> FiltCntR { + FiltCntR::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Input Filter Sample Period"] + #[inline(always)] + pub fn filt_per(&mut self) -> FiltPerW { + FiltPerW::new(self, 0) + } + #[doc = "Bits 8:10 - Input Filter Sample Count"] + #[inline(always)] + pub fn filt_cnt(&mut self) -> FiltCntW { + FiltCntW::new(self, 8) + } +} +#[doc = "TRIGFIL control\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TrigfilSpec; +impl crate::RegisterSpec for TrigfilSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`trigfil::R`](R) reader structure"] +impl crate::Readable for TrigfilSpec {} +#[doc = "`write(|w| ..)` method takes [`trigfil::W`](W) writer structure"] +impl crate::Writable for TrigfilSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TRIGFIL[%s] to value 0"] +impl crate::Resettable for TrigfilSpec {} diff --git a/mcxa276-pac/src/inputmux0/trigfil_prsc.rs b/mcxa276-pac/src/inputmux0/trigfil_prsc.rs new file mode 100644 index 000000000..01ca959ae --- /dev/null +++ b/mcxa276-pac/src/inputmux0/trigfil_prsc.rs @@ -0,0 +1,180 @@ +#[doc = "Register `TRIGFIL_PRSC` reader"] +pub type R = crate::R; +#[doc = "Register `TRIGFIL_PRSC` writer"] +pub type W = crate::W; +#[doc = "Filter Prescaller Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FiltScaleVal { + #[doc = "0: Bypass the clock"] + Val0 = 0, + #[doc = "1: Divide 2"] + Val1 = 1, + #[doc = "2: Divide 4"] + Val2 = 2, + #[doc = "3: Divide 8"] + Val3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FiltScaleVal) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FiltScaleVal { + type Ux = u8; +} +impl crate::IsEnum for FiltScaleVal {} +#[doc = "Field `FILT_SCALE_VAL` reader - Filter Prescaller Value"] +pub type FiltScaleValR = crate::FieldReader; +impl FiltScaleValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FiltScaleVal { + match self.bits { + 0 => FiltScaleVal::Val0, + 1 => FiltScaleVal::Val1, + 2 => FiltScaleVal::Val2, + 3 => FiltScaleVal::Val3, + _ => unreachable!(), + } + } + #[doc = "Bypass the clock"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == FiltScaleVal::Val0 + } + #[doc = "Divide 2"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == FiltScaleVal::Val1 + } + #[doc = "Divide 4"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == FiltScaleVal::Val2 + } + #[doc = "Divide 8"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == FiltScaleVal::Val3 + } +} +#[doc = "Field `FILT_SCALE_VAL` writer - Filter Prescaller Value"] +pub type FiltScaleValW<'a, REG> = crate::FieldWriter<'a, REG, 2, FiltScaleVal, crate::Safe>; +impl<'a, REG> FiltScaleValW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Bypass the clock"] + #[inline(always)] + pub fn val0(self) -> &'a mut crate::W { + self.variant(FiltScaleVal::Val0) + } + #[doc = "Divide 2"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(FiltScaleVal::Val1) + } + #[doc = "Divide 4"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(FiltScaleVal::Val2) + } + #[doc = "Divide 8"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(FiltScaleVal::Val3) + } +} +#[doc = "Enable trigger filter prescaller\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FiltScaleEn { + #[doc = "0: Disable prescaller"] + Val2 = 0, + #[doc = "1: Enabled prescaller"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FiltScaleEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILT_SCALE_EN` reader - Enable trigger filter prescaller"] +pub type FiltScaleEnR = crate::BitReader; +impl FiltScaleEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FiltScaleEn { + match self.bits { + false => FiltScaleEn::Val2, + true => FiltScaleEn::Val1, + } + } + #[doc = "Disable prescaller"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == FiltScaleEn::Val2 + } + #[doc = "Enabled prescaller"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == FiltScaleEn::Val1 + } +} +#[doc = "Field `FILT_SCALE_EN` writer - Enable trigger filter prescaller"] +pub type FiltScaleEnW<'a, REG> = crate::BitWriter<'a, REG, FiltScaleEn>; +impl<'a, REG> FiltScaleEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable prescaller"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(FiltScaleEn::Val2) + } + #[doc = "Enabled prescaller"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(FiltScaleEn::Val1) + } +} +impl R { + #[doc = "Bits 0:1 - Filter Prescaller Value"] + #[inline(always)] + pub fn filt_scale_val(&self) -> FiltScaleValR { + FiltScaleValR::new((self.bits & 3) as u8) + } + #[doc = "Bit 31 - Enable trigger filter prescaller"] + #[inline(always)] + pub fn filt_scale_en(&self) -> FiltScaleEnR { + FiltScaleEnR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Filter Prescaller Value"] + #[inline(always)] + pub fn filt_scale_val(&mut self) -> FiltScaleValW { + FiltScaleValW::new(self, 0) + } + #[doc = "Bit 31 - Enable trigger filter prescaller"] + #[inline(always)] + pub fn filt_scale_en(&mut self) -> FiltScaleEnW { + FiltScaleEnW::new(self, 31) + } +} +#[doc = "Trigger filter prescaller\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_prsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil_prsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TrigfilPrscSpec; +impl crate::RegisterSpec for TrigfilPrscSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`trigfil_prsc::R`](R) reader structure"] +impl crate::Readable for TrigfilPrscSpec {} +#[doc = "`write(|w| ..)` method takes [`trigfil_prsc::W`](W) writer structure"] +impl crate::Writable for TrigfilPrscSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TRIGFIL_PRSC to value 0"] +impl crate::Resettable for TrigfilPrscSpec {} diff --git a/mcxa276-pac/src/inputmux0/trigfil_stat0.rs b/mcxa276-pac/src/inputmux0/trigfil_stat0.rs new file mode 100644 index 000000000..0474124c9 --- /dev/null +++ b/mcxa276-pac/src/inputmux0/trigfil_stat0.rs @@ -0,0 +1,505 @@ +#[doc = "Register `TRIGFIL_STAT0` reader"] +pub type R = crate::R; +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn0Val { + #[doc = "0: TRIG_IN0 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN0 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn0Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN0_VAL` reader - TRIG_IN value"] +pub type TrigIn0ValR = crate::BitReader; +impl TrigIn0ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn0Val { + match self.bits { + false => TrigIn0Val::Val0, + true => TrigIn0Val::Val1, + } + } + #[doc = "TRIG_IN0 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn0Val::Val0 + } + #[doc = "TRIG_IN0 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn0Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn1Val { + #[doc = "0: TRIG_IN1 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN1 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn1Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN1_VAL` reader - TRIG_IN value"] +pub type TrigIn1ValR = crate::BitReader; +impl TrigIn1ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn1Val { + match self.bits { + false => TrigIn1Val::Val0, + true => TrigIn1Val::Val1, + } + } + #[doc = "TRIG_IN1 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn1Val::Val0 + } + #[doc = "TRIG_IN1 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn1Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn2Val { + #[doc = "0: TRIG_IN2 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN2 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn2Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN2_VAL` reader - TRIG_IN value"] +pub type TrigIn2ValR = crate::BitReader; +impl TrigIn2ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn2Val { + match self.bits { + false => TrigIn2Val::Val0, + true => TrigIn2Val::Val1, + } + } + #[doc = "TRIG_IN2 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn2Val::Val0 + } + #[doc = "TRIG_IN2 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn2Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn3Val { + #[doc = "0: TRIG_IN3 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN3 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn3Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN3_VAL` reader - TRIG_IN value"] +pub type TrigIn3ValR = crate::BitReader; +impl TrigIn3ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn3Val { + match self.bits { + false => TrigIn3Val::Val0, + true => TrigIn3Val::Val1, + } + } + #[doc = "TRIG_IN3 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn3Val::Val0 + } + #[doc = "TRIG_IN3 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn3Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn4Val { + #[doc = "0: TRIG_IN4 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN4 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn4Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN4_VAL` reader - TRIG_IN value"] +pub type TrigIn4ValR = crate::BitReader; +impl TrigIn4ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn4Val { + match self.bits { + false => TrigIn4Val::Val0, + true => TrigIn4Val::Val1, + } + } + #[doc = "TRIG_IN4 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn4Val::Val0 + } + #[doc = "TRIG_IN4 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn4Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn5Val { + #[doc = "0: TRIG_IN5 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN5 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn5Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN5_VAL` reader - TRIG_IN value"] +pub type TrigIn5ValR = crate::BitReader; +impl TrigIn5ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn5Val { + match self.bits { + false => TrigIn5Val::Val0, + true => TrigIn5Val::Val1, + } + } + #[doc = "TRIG_IN5 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn5Val::Val0 + } + #[doc = "TRIG_IN5 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn5Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn6Val { + #[doc = "0: TRIG_IN6 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN6 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn6Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN6_VAL` reader - TRIG_IN value"] +pub type TrigIn6ValR = crate::BitReader; +impl TrigIn6ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn6Val { + match self.bits { + false => TrigIn6Val::Val0, + true => TrigIn6Val::Val1, + } + } + #[doc = "TRIG_IN6 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn6Val::Val0 + } + #[doc = "TRIG_IN6 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn6Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn7Val { + #[doc = "0: TRIG_IN7 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN7 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn7Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN7_VAL` reader - TRIG_IN value"] +pub type TrigIn7ValR = crate::BitReader; +impl TrigIn7ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn7Val { + match self.bits { + false => TrigIn7Val::Val0, + true => TrigIn7Val::Val1, + } + } + #[doc = "TRIG_IN7 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn7Val::Val0 + } + #[doc = "TRIG_IN7 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn7Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn8Val { + #[doc = "0: TRIG_IN8 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN8 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn8Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN8_VAL` reader - TRIG_IN value"] +pub type TrigIn8ValR = crate::BitReader; +impl TrigIn8ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn8Val { + match self.bits { + false => TrigIn8Val::Val0, + true => TrigIn8Val::Val1, + } + } + #[doc = "TRIG_IN8 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn8Val::Val0 + } + #[doc = "TRIG_IN8 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn8Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn9Val { + #[doc = "0: TRIG_IN9 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN9 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn9Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN9_VAL` reader - TRIG_IN value"] +pub type TrigIn9ValR = crate::BitReader; +impl TrigIn9ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn9Val { + match self.bits { + false => TrigIn9Val::Val0, + true => TrigIn9Val::Val1, + } + } + #[doc = "TRIG_IN9 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn9Val::Val0 + } + #[doc = "TRIG_IN9 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn9Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn10Val { + #[doc = "0: TRIG_IN10 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN10 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn10Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN10_VAL` reader - TRIG_IN value"] +pub type TrigIn10ValR = crate::BitReader; +impl TrigIn10ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn10Val { + match self.bits { + false => TrigIn10Val::Val0, + true => TrigIn10Val::Val1, + } + } + #[doc = "TRIG_IN10 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn10Val::Val0 + } + #[doc = "TRIG_IN10 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn10Val::Val1 + } +} +#[doc = "TRIG_IN value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrigIn11Val { + #[doc = "0: TRIG_IN11 is 0"] + Val0 = 0, + #[doc = "1: TRIG_IN11 is 1"] + Val1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrigIn11Val) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIG_IN11_VAL` reader - TRIG_IN value"] +pub type TrigIn11ValR = crate::BitReader; +impl TrigIn11ValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrigIn11Val { + match self.bits { + false => TrigIn11Val::Val0, + true => TrigIn11Val::Val1, + } + } + #[doc = "TRIG_IN11 is 0"] + #[inline(always)] + pub fn is_val0(&self) -> bool { + *self == TrigIn11Val::Val0 + } + #[doc = "TRIG_IN11 is 1"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == TrigIn11Val::Val1 + } +} +impl R { + #[doc = "Bit 0 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in0_val(&self) -> TrigIn0ValR { + TrigIn0ValR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in1_val(&self) -> TrigIn1ValR { + TrigIn1ValR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in2_val(&self) -> TrigIn2ValR { + TrigIn2ValR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in3_val(&self) -> TrigIn3ValR { + TrigIn3ValR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in4_val(&self) -> TrigIn4ValR { + TrigIn4ValR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in5_val(&self) -> TrigIn5ValR { + TrigIn5ValR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in6_val(&self) -> TrigIn6ValR { + TrigIn6ValR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in7_val(&self) -> TrigIn7ValR { + TrigIn7ValR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in8_val(&self) -> TrigIn8ValR { + TrigIn8ValR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in9_val(&self) -> TrigIn9ValR { + TrigIn9ValR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in10_val(&self) -> TrigIn10ValR { + TrigIn10ValR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TRIG_IN value"] + #[inline(always)] + pub fn trig_in11_val(&self) -> TrigIn11ValR { + TrigIn11ValR::new(((self.bits >> 11) & 1) != 0) + } +} +#[doc = "Trigger filter stat\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_stat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TrigfilStat0Spec; +impl crate::RegisterSpec for TrigfilStat0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`trigfil_stat0::R`](R) reader structure"] +impl crate::Readable for TrigfilStat0Spec {} +#[doc = "`reset()` method sets TRIGFIL_STAT0 to value 0"] +impl crate::Resettable for TrigfilStat0Spec {} diff --git a/mcxa276-pac/src/inputmux0/usbfs_trig.rs b/mcxa276-pac/src/inputmux0/usbfs_trig.rs new file mode 100644 index 000000000..ee5babf7b --- /dev/null +++ b/mcxa276-pac/src/inputmux0/usbfs_trig.rs @@ -0,0 +1,145 @@ +#[doc = "Register `USBFS_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `USBFS_TRIG` writer"] +pub type W = crate::W; +#[doc = "USB-FS trigger input connections.\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Inp { + #[doc = "1: LPUART0 lpuart_trg_txdata input is selected"] + Val1 = 1, + #[doc = "2: LPUART1 lpuart_trg_txdata input is selected"] + Val2 = 2, + #[doc = "3: LPUART2 lpuart_trg_txdata input is selected"] + Val3 = 3, + #[doc = "4: LPUART3 lpuart_trg_txdata input is selected"] + Val4 = 4, + #[doc = "5: LPUART4 lpuart_trg_txdata input is selected"] + Val5 = 5, + #[doc = "6: LPUART5 lpuart_trg_txdata input is selected"] + Val6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Inp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Inp { + type Ux = u8; +} +impl crate::IsEnum for Inp {} +#[doc = "Field `INP` reader - USB-FS trigger input connections."] +pub type InpR = crate::FieldReader; +impl InpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Inp::Val1), + 2 => Some(Inp::Val2), + 3 => Some(Inp::Val3), + 4 => Some(Inp::Val4), + 5 => Some(Inp::Val5), + 6 => Some(Inp::Val6), + _ => None, + } + } + #[doc = "LPUART0 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn is_val1(&self) -> bool { + *self == Inp::Val1 + } + #[doc = "LPUART1 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn is_val2(&self) -> bool { + *self == Inp::Val2 + } + #[doc = "LPUART2 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn is_val3(&self) -> bool { + *self == Inp::Val3 + } + #[doc = "LPUART3 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn is_val4(&self) -> bool { + *self == Inp::Val4 + } + #[doc = "LPUART4 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn is_val5(&self) -> bool { + *self == Inp::Val5 + } + #[doc = "LPUART5 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn is_val6(&self) -> bool { + *self == Inp::Val6 + } +} +#[doc = "Field `INP` writer - USB-FS trigger input connections."] +pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 4, Inp>; +impl<'a, REG> InpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "LPUART0 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn val1(self) -> &'a mut crate::W { + self.variant(Inp::Val1) + } + #[doc = "LPUART1 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn val2(self) -> &'a mut crate::W { + self.variant(Inp::Val2) + } + #[doc = "LPUART2 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn val3(self) -> &'a mut crate::W { + self.variant(Inp::Val3) + } + #[doc = "LPUART3 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn val4(self) -> &'a mut crate::W { + self.variant(Inp::Val4) + } + #[doc = "LPUART4 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn val5(self) -> &'a mut crate::W { + self.variant(Inp::Val5) + } + #[doc = "LPUART5 lpuart_trg_txdata input is selected"] + #[inline(always)] + pub fn val6(self) -> &'a mut crate::W { + self.variant(Inp::Val6) + } +} +impl R { + #[doc = "Bits 0:3 - USB-FS trigger input connections."] + #[inline(always)] + pub fn inp(&self) -> InpR { + InpR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - USB-FS trigger input connections."] + #[inline(always)] + pub fn inp(&mut self) -> InpW { + InpW::new(self, 0) + } +} +#[doc = "USB-FS trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfs_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfs_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UsbfsTrigSpec; +impl crate::RegisterSpec for UsbfsTrigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbfs_trig::R`](R) reader structure"] +impl crate::Readable for UsbfsTrigSpec {} +#[doc = "`write(|w| ..)` method takes [`usbfs_trig::W`](W) writer structure"] +impl crate::Writable for UsbfsTrigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets USBFS_TRIG to value 0x07"] +impl crate::Resettable for UsbfsTrigSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/lib.rs b/mcxa276-pac/src/lib.rs new file mode 100644 index 000000000..18a85f052 --- /dev/null +++ b/mcxa276-pac/src/lib.rs @@ -0,0 +1,1555 @@ +#![doc = "Peripheral access API for MCXA276 microcontrollers (generated using svd2rust v0.36.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +#![allow(elided_lifetimes_in_paths)] +#![allow(warnings)] + + +#![cfg_attr(docsrs, feature(doc_auto_cfg))] +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 3; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn Reserved16(); + fn CMC(); + fn DMA_CH0(); + fn DMA_CH1(); + fn DMA_CH2(); + fn DMA_CH3(); + fn DMA_CH4(); + fn DMA_CH5(); + fn DMA_CH6(); + fn DMA_CH7(); + fn ERM0_SINGLE_BIT(); + fn ERM0_MULTI_BIT(); + fn FMU0(); + fn GLIKEY0(); + fn MBC0(); + fn SCG0(); + fn SPC0(); + fn TDET(); + fn WUU0(); + fn CAN0(); + fn CAN1(); + fn FLEXIO(); + fn I3C0(); + fn LPI2C0(); + fn LPI2C1(); + fn LPSPI0(); + fn LPSPI1(); + fn LPUART0(); + fn LPUART1(); + fn LPUART2(); + fn LPUART3(); + fn LPUART4(); + fn USB0(); + fn CDOG0(); + fn CTIMER0(); + fn CTIMER1(); + fn CTIMER2(); + fn CTIMER3(); + fn CTIMER4(); + fn FLEXPWM0_RELOAD_ERROR(); + fn FLEXPWM0_FAULT(); + fn FLEXPWM0_SUBMODULE0(); + fn FLEXPWM0_SUBMODULE1(); + fn FLEXPWM0_SUBMODULE2(); + fn FLEXPWM0_SUBMODULE3(); + fn EQDC0_COMPARE(); + fn EQDC0_HOME(); + fn EQDC0_WATCHDOG(); + fn EQDC0_INDEX(); + fn FREQME0(); + fn LPTMR0(); + fn OS_EVENT(); + fn WAKETIMER0(); + fn UTICK0(); + fn WWDT0(); + fn ADC0(); + fn ADC1(); + fn CMP0(); + fn CMP1(); + fn CMP2(); + fn DAC0(); + fn GPIO0(); + fn GPIO1(); + fn GPIO2(); + fn GPIO3(); + fn GPIO4(); + fn LPI2C2(); + fn LPI2C3(); + fn FLEXPWM1_RELOAD_ERROR(); + fn FLEXPWM1_FAULT(); + fn FLEXPWM1_SUBMODULE0(); + fn FLEXPWM1_SUBMODULE1(); + fn FLEXPWM1_SUBMODULE2(); + fn FLEXPWM1_SUBMODULE3(); + fn EQDC1_COMPARE(); + fn EQDC1_HOME(); + fn EQDC1_WATCHDOG(); + fn EQDC1_INDEX(); + fn LPUART5(); + fn MAU(); + fn SMARTDMA(); + fn CDOG1(); + fn PKC(); + fn SGI(); + fn TRNG0(); + fn ADC2(); + fn ADC3(); + fn RTC(); + fn RTC_1HZ(); + fn SLCD(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 122] = [ + Vector { + _handler: Reserved16, + }, + Vector { _handler: CMC }, + Vector { _handler: DMA_CH0 }, + Vector { _handler: DMA_CH1 }, + Vector { _handler: DMA_CH2 }, + Vector { _handler: DMA_CH3 }, + Vector { _handler: DMA_CH4 }, + Vector { _handler: DMA_CH5 }, + Vector { _handler: DMA_CH6 }, + Vector { _handler: DMA_CH7 }, + Vector { + _handler: ERM0_SINGLE_BIT, + }, + Vector { + _handler: ERM0_MULTI_BIT, + }, + Vector { _handler: FMU0 }, + Vector { _handler: GLIKEY0 }, + Vector { _handler: MBC0 }, + Vector { _handler: SCG0 }, + Vector { _handler: SPC0 }, + Vector { _handler: TDET }, + Vector { _handler: WUU0 }, + Vector { _handler: CAN0 }, + Vector { _handler: CAN1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FLEXIO }, + Vector { _handler: I3C0 }, + Vector { _reserved: 0 }, + Vector { _handler: LPI2C0 }, + Vector { _handler: LPI2C1 }, + Vector { _handler: LPSPI0 }, + Vector { _handler: LPSPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: LPUART0 }, + Vector { _handler: LPUART1 }, + Vector { _handler: LPUART2 }, + Vector { _handler: LPUART3 }, + Vector { _handler: LPUART4 }, + Vector { _handler: USB0 }, + Vector { _reserved: 0 }, + Vector { _handler: CDOG0 }, + Vector { _handler: CTIMER0 }, + Vector { _handler: CTIMER1 }, + Vector { _handler: CTIMER2 }, + Vector { _handler: CTIMER3 }, + Vector { _handler: CTIMER4 }, + Vector { + _handler: FLEXPWM0_RELOAD_ERROR, + }, + Vector { + _handler: FLEXPWM0_FAULT, + }, + Vector { + _handler: FLEXPWM0_SUBMODULE0, + }, + Vector { + _handler: FLEXPWM0_SUBMODULE1, + }, + Vector { + _handler: FLEXPWM0_SUBMODULE2, + }, + Vector { + _handler: FLEXPWM0_SUBMODULE3, + }, + Vector { + _handler: EQDC0_COMPARE, + }, + Vector { + _handler: EQDC0_HOME, + }, + Vector { + _handler: EQDC0_WATCHDOG, + }, + Vector { + _handler: EQDC0_INDEX, + }, + Vector { _handler: FREQME0 }, + Vector { _handler: LPTMR0 }, + Vector { _reserved: 0 }, + Vector { _handler: OS_EVENT }, + Vector { + _handler: WAKETIMER0, + }, + Vector { _handler: UTICK0 }, + Vector { _handler: WWDT0 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC0 }, + Vector { _handler: ADC1 }, + Vector { _handler: CMP0 }, + Vector { _handler: CMP1 }, + Vector { _handler: CMP2 }, + Vector { _handler: DAC0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GPIO0 }, + Vector { _handler: GPIO1 }, + Vector { _handler: GPIO2 }, + Vector { _handler: GPIO3 }, + Vector { _handler: GPIO4 }, + Vector { _reserved: 0 }, + Vector { _handler: LPI2C2 }, + Vector { _handler: LPI2C3 }, + Vector { + _handler: FLEXPWM1_RELOAD_ERROR, + }, + Vector { + _handler: FLEXPWM1_FAULT, + }, + Vector { + _handler: FLEXPWM1_SUBMODULE0, + }, + Vector { + _handler: FLEXPWM1_SUBMODULE1, + }, + Vector { + _handler: FLEXPWM1_SUBMODULE2, + }, + Vector { + _handler: FLEXPWM1_SUBMODULE3, + }, + Vector { + _handler: EQDC1_COMPARE, + }, + Vector { + _handler: EQDC1_HOME, + }, + Vector { + _handler: EQDC1_WATCHDOG, + }, + Vector { + _handler: EQDC1_INDEX, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: LPUART5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: MAU }, + Vector { _handler: SMARTDMA }, + Vector { _handler: CDOG1 }, + Vector { _handler: PKC }, + Vector { _handler: SGI }, + Vector { _reserved: 0 }, + Vector { _handler: TRNG0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { _handler: RTC }, + Vector { _handler: RTC_1HZ }, + Vector { _handler: SLCD }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - Reserved16"] + Reserved16 = 0, + #[doc = "1 - CMC"] + CMC = 1, + #[doc = "2 - DMA_CH0"] + DMA_CH0 = 2, + #[doc = "3 - DMA_CH1"] + DMA_CH1 = 3, + #[doc = "4 - DMA_CH2"] + DMA_CH2 = 4, + #[doc = "5 - DMA_CH3"] + DMA_CH3 = 5, + #[doc = "6 - DMA_CH4"] + DMA_CH4 = 6, + #[doc = "7 - DMA_CH5"] + DMA_CH5 = 7, + #[doc = "8 - DMA_CH6"] + DMA_CH6 = 8, + #[doc = "9 - DMA_CH7"] + DMA_CH7 = 9, + #[doc = "10 - ERM0_SINGLE_BIT"] + ERM0_SINGLE_BIT = 10, + #[doc = "11 - ERM0_MULTI_BIT"] + ERM0_MULTI_BIT = 11, + #[doc = "12 - FMU0"] + FMU0 = 12, + #[doc = "13 - GLIKEY0"] + GLIKEY0 = 13, + #[doc = "14 - MBC0"] + MBC0 = 14, + #[doc = "15 - SCG0"] + SCG0 = 15, + #[doc = "16 - SPC0"] + SPC0 = 16, + #[doc = "17 - TDET"] + TDET = 17, + #[doc = "18 - WUU0"] + WUU0 = 18, + #[doc = "19 - CAN0"] + CAN0 = 19, + #[doc = "20 - CAN1"] + CAN1 = 20, + #[doc = "23 - FLEXIO"] + FLEXIO = 23, + #[doc = "24 - I3C0"] + I3C0 = 24, + #[doc = "26 - LPI2C0"] + LPI2C0 = 26, + #[doc = "27 - LPI2C1"] + LPI2C1 = 27, + #[doc = "28 - LPSPI0"] + LPSPI0 = 28, + #[doc = "29 - LPSPI1"] + LPSPI1 = 29, + #[doc = "31 - LPUART0"] + LPUART0 = 31, + #[doc = "32 - LPUART1"] + LPUART1 = 32, + #[doc = "33 - LPUART2"] + LPUART2 = 33, + #[doc = "34 - LPUART3"] + LPUART3 = 34, + #[doc = "35 - LPUART4"] + LPUART4 = 35, + #[doc = "36 - USB0"] + USB0 = 36, + #[doc = "38 - CDOG0"] + CDOG0 = 38, + #[doc = "39 - CTIMER0"] + CTIMER0 = 39, + #[doc = "40 - CTIMER1"] + CTIMER1 = 40, + #[doc = "41 - CTIMER2"] + CTIMER2 = 41, + #[doc = "42 - CTIMER3"] + CTIMER3 = 42, + #[doc = "43 - CTIMER4"] + CTIMER4 = 43, + #[doc = "44 - FLEXPWM0_RELOAD_ERROR"] + FLEXPWM0_RELOAD_ERROR = 44, + #[doc = "45 - FLEXPWM0_FAULT"] + FLEXPWM0_FAULT = 45, + #[doc = "46 - FLEXPWM0_SUBMODULE0"] + FLEXPWM0_SUBMODULE0 = 46, + #[doc = "47 - FLEXPWM0_SUBMODULE1"] + FLEXPWM0_SUBMODULE1 = 47, + #[doc = "48 - FLEXPWM0_SUBMODULE2"] + FLEXPWM0_SUBMODULE2 = 48, + #[doc = "49 - FLEXPWM0_SUBMODULE3"] + FLEXPWM0_SUBMODULE3 = 49, + #[doc = "50 - EQDC0_COMPARE"] + EQDC0_COMPARE = 50, + #[doc = "51 - EQDC0_HOME"] + EQDC0_HOME = 51, + #[doc = "52 - EQDC0_WATCHDOG"] + EQDC0_WATCHDOG = 52, + #[doc = "53 - EQDC0_INDEX"] + EQDC0_INDEX = 53, + #[doc = "54 - FREQME0"] + FREQME0 = 54, + #[doc = "55 - LPTMR0"] + LPTMR0 = 55, + #[doc = "57 - OS_EVENT"] + OS_EVENT = 57, + #[doc = "58 - WAKETIMER0"] + WAKETIMER0 = 58, + #[doc = "59 - UTICK0"] + UTICK0 = 59, + #[doc = "60 - WWDT0"] + WWDT0 = 60, + #[doc = "62 - ADC0"] + ADC0 = 62, + #[doc = "63 - ADC1"] + ADC1 = 63, + #[doc = "64 - CMP0"] + CMP0 = 64, + #[doc = "65 - CMP1"] + CMP1 = 65, + #[doc = "66 - CMP2"] + CMP2 = 66, + #[doc = "67 - DAC0"] + DAC0 = 67, + #[doc = "71 - GPIO0"] + GPIO0 = 71, + #[doc = "72 - GPIO1"] + GPIO1 = 72, + #[doc = "73 - GPIO2"] + GPIO2 = 73, + #[doc = "74 - GPIO3"] + GPIO3 = 74, + #[doc = "75 - GPIO4"] + GPIO4 = 75, + #[doc = "77 - LPI2C2"] + LPI2C2 = 77, + #[doc = "78 - LPI2C3"] + LPI2C3 = 78, + #[doc = "79 - FLEXPWM1_RELOAD_ERROR"] + FLEXPWM1_RELOAD_ERROR = 79, + #[doc = "80 - FLEXPWM1_FAULT"] + FLEXPWM1_FAULT = 80, + #[doc = "81 - FLEXPWM1_SUBMODULE0"] + FLEXPWM1_SUBMODULE0 = 81, + #[doc = "82 - FLEXPWM1_SUBMODULE1"] + FLEXPWM1_SUBMODULE1 = 82, + #[doc = "83 - FLEXPWM1_SUBMODULE2"] + FLEXPWM1_SUBMODULE2 = 83, + #[doc = "84 - FLEXPWM1_SUBMODULE3"] + FLEXPWM1_SUBMODULE3 = 84, + #[doc = "85 - EQDC1_COMPARE"] + EQDC1_COMPARE = 85, + #[doc = "86 - EQDC1_HOME"] + EQDC1_HOME = 86, + #[doc = "87 - EQDC1_WATCHDOG"] + EQDC1_WATCHDOG = 87, + #[doc = "88 - EQDC1_INDEX"] + EQDC1_INDEX = 88, + #[doc = "95 - LPUART5"] + LPUART5 = 95, + #[doc = "107 - MAU"] + MAU = 107, + #[doc = "108 - SMARTDMA"] + SMARTDMA = 108, + #[doc = "109 - CDOG1"] + CDOG1 = 109, + #[doc = "110 - PKC"] + PKC = 110, + #[doc = "111 - SGI"] + SGI = 111, + #[doc = "113 - TRNG0"] + TRNG0 = 113, + #[doc = "116 - ADC2"] + ADC2 = 116, + #[doc = "117 - ADC3"] + ADC3 = 117, + #[doc = "119 - RTC"] + RTC = 119, + #[doc = "120 - RTC_1HZ"] + RTC_1HZ = 120, + #[doc = "121 - SLCD"] + SLCD = 121, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "INPUTMUX"] +pub type Inputmux0 = crate::Periph; +impl core::fmt::Debug for Inputmux0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Inputmux0").finish() + } +} +#[doc = "INPUTMUX"] +pub mod inputmux0; +#[doc = "Improved Inter-Integrated Circuit"] +pub type I3c0 = crate::Periph; +impl core::fmt::Debug for I3c0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3c0").finish() + } +} +#[doc = "Improved Inter-Integrated Circuit"] +pub mod i3c0; +#[doc = "Standard Counter or Timer"] +pub type Ctimer0 = crate::Periph; +impl core::fmt::Debug for Ctimer0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ctimer0").finish() + } +} +#[doc = "Standard Counter or Timer"] +pub mod ctimer0; +#[doc = "Standard Counter or Timer"] +pub type Ctimer1 = crate::Periph; +impl core::fmt::Debug for Ctimer1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ctimer1").finish() + } +} +#[doc = "Standard Counter or Timer"] +pub use self::ctimer0 as ctimer1; +#[doc = "Standard Counter or Timer"] +pub type Ctimer2 = crate::Periph; +impl core::fmt::Debug for Ctimer2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ctimer2").finish() + } +} +#[doc = "Standard Counter or Timer"] +pub use self::ctimer0 as ctimer2; +#[doc = "Standard Counter or Timer"] +pub type Ctimer3 = crate::Periph; +impl core::fmt::Debug for Ctimer3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ctimer3").finish() + } +} +#[doc = "Standard Counter or Timer"] +pub use self::ctimer0 as ctimer3; +#[doc = "Standard Counter or Timer"] +pub type Ctimer4 = crate::Periph; +impl core::fmt::Debug for Ctimer4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ctimer4").finish() + } +} +#[doc = "Standard Counter or Timer"] +pub use self::ctimer0 as ctimer4; +#[doc = "FREQME"] +pub type Freqme0 = crate::Periph; +impl core::fmt::Debug for Freqme0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Freqme0").finish() + } +} +#[doc = "FREQME"] +pub mod freqme0; +#[doc = "UTICK"] +pub type Utick0 = crate::Periph; +impl core::fmt::Debug for Utick0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Utick0").finish() + } +} +#[doc = "UTICK"] +pub mod utick0; +#[doc = "WWDT"] +pub type Wwdt0 = crate::Periph; +impl core::fmt::Debug for Wwdt0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Wwdt0").finish() + } +} +#[doc = "WWDT"] +pub mod wwdt0; +#[doc = "Smart DMA Controller"] +pub type Smartdma0 = crate::Periph; +impl core::fmt::Debug for Smartdma0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Smartdma0").finish() + } +} +#[doc = "Smart DMA Controller"] +pub mod smartdma0; +#[doc = "DMA MP"] +pub type Dma0 = crate::Periph; +impl core::fmt::Debug for Dma0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dma0").finish() + } +} +#[doc = "DMA MP"] +pub mod dma0; +#[doc = "DMA TCD"] +pub type Edma0Tcd0 = crate::Periph; +impl core::fmt::Debug for Edma0Tcd0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Edma0Tcd0").finish() + } +} +#[doc = "DMA TCD"] +pub mod edma_0_tcd0; +#[doc = "AOI"] +pub type Aoi0 = crate::Periph; +impl core::fmt::Debug for Aoi0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Aoi0").finish() + } +} +#[doc = "AOI"] +pub mod aoi0; +#[doc = "AOI"] +pub type Aoi1 = crate::Periph; +impl core::fmt::Debug for Aoi1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Aoi1").finish() + } +} +#[doc = "AOI"] +pub use self::aoi0 as aoi1; +#[doc = "CRC"] +pub type Crc0 = crate::Periph; +impl core::fmt::Debug for Crc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Crc0").finish() + } +} +#[doc = "CRC"] +pub mod crc0; +#[doc = "CMC"] +pub type Cmc = crate::Periph; +impl core::fmt::Debug for Cmc { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Cmc").finish() + } +} +#[doc = "CMC"] +pub mod cmc; +#[doc = "Error Injection Module"] +pub type Eim0 = crate::Periph; +impl core::fmt::Debug for Eim0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Eim0").finish() + } +} +#[doc = "Error Injection Module"] +pub mod eim0; +#[doc = "Error Reporting Module"] +pub type Erm0 = crate::Periph; +impl core::fmt::Debug for Erm0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Erm0").finish() + } +} +#[doc = "Error Reporting Module"] +pub mod erm0; +#[doc = "TRDC"] +pub type Mbc0 = crate::Periph; +impl core::fmt::Debug for Mbc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Mbc0").finish() + } +} +#[doc = "TRDC"] +pub mod mbc0; +#[doc = "System Clock Generator"] +pub type Scg0 = crate::Periph; +impl core::fmt::Debug for Scg0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Scg0").finish() + } +} +#[doc = "System Clock Generator"] +pub mod scg0; +#[doc = "SPC"] +pub type Spc0 = crate::Periph; +impl core::fmt::Debug for Spc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spc0").finish() + } +} +#[doc = "SPC"] +pub mod spc0; +#[doc = "MRCC"] +pub type Mrcc0 = crate::Periph; +impl core::fmt::Debug for Mrcc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Mrcc0").finish() + } +} +#[doc = "MRCC"] +pub mod mrcc0; +#[doc = "SYSCON"] +pub type Syscon = crate::Periph; +impl core::fmt::Debug for Syscon { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Syscon").finish() + } +} +#[doc = "SYSCON"] +pub mod syscon; +#[doc = "GLIKEY"] +pub type Glikey0 = crate::Periph; +impl core::fmt::Debug for Glikey0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Glikey0").finish() + } +} +#[doc = "GLIKEY"] +pub mod glikey0; +#[doc = "Low-Leakage Wakeup Unit"] +pub type Wuu0 = crate::Periph; +impl core::fmt::Debug for Wuu0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Wuu0").finish() + } +} +#[doc = "Low-Leakage Wakeup Unit"] +pub mod wuu0; +#[doc = "VBAT"] +pub type Vbat0 = crate::Periph; +impl core::fmt::Debug for Vbat0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Vbat0").finish() + } +} +#[doc = "VBAT"] +pub mod vbat0; +#[doc = "NPX"] +pub type Fmc0 = crate::Periph; +impl core::fmt::Debug for Fmc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Fmc0").finish() + } +} +#[doc = "NPX"] +pub mod fmc0; +#[doc = "Flash"] +pub type Fmu0 = crate::Periph; +impl core::fmt::Debug for Fmu0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Fmu0").finish() + } +} +#[doc = "Flash"] +pub mod fmu0; +#[doc = "Flexible I/O"] +pub type Flexio0 = crate::Periph; +impl core::fmt::Debug for Flexio0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Flexio0").finish() + } +} +#[doc = "Flexible I/O"] +pub mod flexio0; +#[doc = "Low-Power Inter-Integrated Circuit"] +pub type Lpi2c0 = crate::Periph; +impl core::fmt::Debug for Lpi2c0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpi2c0").finish() + } +} +#[doc = "Low-Power Inter-Integrated Circuit"] +pub mod lpi2c0; +#[doc = "Low-Power Inter-Integrated Circuit"] +pub type Lpi2c1 = crate::Periph; +impl core::fmt::Debug for Lpi2c1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpi2c1").finish() + } +} +#[doc = "Low-Power Inter-Integrated Circuit"] +pub use self::lpi2c0 as lpi2c1; +#[doc = "Low-Power Inter-Integrated Circuit"] +pub type Lpi2c2 = crate::Periph; +impl core::fmt::Debug for Lpi2c2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpi2c2").finish() + } +} +#[doc = "Low-Power Inter-Integrated Circuit"] +pub use self::lpi2c0 as lpi2c2; +#[doc = "Low-Power Inter-Integrated Circuit"] +pub type Lpi2c3 = crate::Periph; +impl core::fmt::Debug for Lpi2c3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpi2c3").finish() + } +} +#[doc = "Low-Power Inter-Integrated Circuit"] +pub use self::lpi2c0 as lpi2c3; +#[doc = "Low-Power Serial Peripheral Interface"] +pub type Lpspi0 = crate::Periph; +impl core::fmt::Debug for Lpspi0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpspi0").finish() + } +} +#[doc = "Low-Power Serial Peripheral Interface"] +pub mod lpspi0; +#[doc = "Low-Power Serial Peripheral Interface"] +pub type Lpspi1 = crate::Periph; +impl core::fmt::Debug for Lpspi1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpspi1").finish() + } +} +#[doc = "Low-Power Serial Peripheral Interface"] +pub use self::lpspi0 as lpspi1; +#[doc = "LPUART"] +pub type Lpuart0 = crate::Periph; +impl core::fmt::Debug for Lpuart0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpuart0").finish() + } +} +#[doc = "LPUART"] +pub mod lpuart0; +#[doc = "LPUART"] +pub type Lpuart1 = crate::Periph; +impl core::fmt::Debug for Lpuart1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpuart1").finish() + } +} +#[doc = "LPUART"] +pub use self::lpuart0 as lpuart1; +#[doc = "LPUART"] +pub type Lpuart2 = crate::Periph; +impl core::fmt::Debug for Lpuart2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpuart2").finish() + } +} +#[doc = "LPUART"] +pub use self::lpuart0 as lpuart2; +#[doc = "LPUART"] +pub type Lpuart3 = crate::Periph; +impl core::fmt::Debug for Lpuart3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpuart3").finish() + } +} +#[doc = "LPUART"] +pub use self::lpuart0 as lpuart3; +#[doc = "LPUART"] +pub type Lpuart4 = crate::Periph; +impl core::fmt::Debug for Lpuart4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpuart4").finish() + } +} +#[doc = "LPUART"] +pub use self::lpuart0 as lpuart4; +#[doc = "LPUART"] +pub type Lpuart5 = crate::Periph; +impl core::fmt::Debug for Lpuart5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpuart5").finish() + } +} +#[doc = "LPUART"] +pub use self::lpuart0 as lpuart5; +#[doc = "USBFS"] +pub type Usb0 = crate::Periph; +impl core::fmt::Debug for Usb0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Usb0").finish() + } +} +#[doc = "USBFS"] +pub mod usb0; +#[doc = "Quadrature_Decoder"] +pub type Eqdc0 = crate::Periph; +impl core::fmt::Debug for Eqdc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Eqdc0").finish() + } +} +#[doc = "Quadrature_Decoder"] +pub mod eqdc0; +#[doc = "Quadrature_Decoder"] +pub type Eqdc1 = crate::Periph; +impl core::fmt::Debug for Eqdc1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Eqdc1").finish() + } +} +#[doc = "Quadrature_Decoder"] +pub use self::eqdc0 as eqdc1; +#[doc = "PWM"] +pub type Flexpwm0 = crate::Periph; +impl core::fmt::Debug for Flexpwm0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Flexpwm0").finish() + } +} +#[doc = "PWM"] +pub mod flexpwm0; +#[doc = "PWM"] +pub type Flexpwm1 = crate::Periph; +impl core::fmt::Debug for Flexpwm1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Flexpwm1").finish() + } +} +#[doc = "PWM"] +pub use self::flexpwm0 as flexpwm1; +#[doc = "LPTMR"] +pub type Lptmr0 = crate::Periph; +impl core::fmt::Debug for Lptmr0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lptmr0").finish() + } +} +#[doc = "LPTMR"] +pub mod lptmr0; +#[doc = "OSTIMER"] +pub type Ostimer0 = crate::Periph; +impl core::fmt::Debug for Ostimer0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ostimer0").finish() + } +} +#[doc = "OSTIMER"] +pub mod ostimer0; +#[doc = "WAKE_TIMER"] +pub type Waketimer0 = crate::Periph; +impl core::fmt::Debug for Waketimer0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Waketimer0").finish() + } +} +#[doc = "WAKE_TIMER"] +pub mod waketimer0; +#[doc = "ADC"] +pub type Adc0 = crate::Periph; +impl core::fmt::Debug for Adc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Adc0").finish() + } +} +#[doc = "ADC"] +pub mod adc0; +#[doc = "ADC"] +pub type Adc1 = crate::Periph; +impl core::fmt::Debug for Adc1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Adc1").finish() + } +} +#[doc = "ADC"] +pub use self::adc0 as adc1; +#[doc = "ADC"] +pub type Adc2 = crate::Periph; +impl core::fmt::Debug for Adc2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Adc2").finish() + } +} +#[doc = "ADC"] +pub use self::adc0 as adc2; +#[doc = "ADC"] +pub type Adc3 = crate::Periph; +impl core::fmt::Debug for Adc3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Adc3").finish() + } +} +#[doc = "ADC"] +pub use self::adc0 as adc3; +#[doc = "LPCMP"] +pub type Cmp0 = crate::Periph; +impl core::fmt::Debug for Cmp0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Cmp0").finish() + } +} +#[doc = "LPCMP"] +pub mod cmp0; +#[doc = "LPCMP"] +pub type Cmp1 = crate::Periph; +impl core::fmt::Debug for Cmp1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Cmp1").finish() + } +} +#[doc = "LPCMP"] +pub use self::cmp0 as cmp1; +#[doc = "LPCMP"] +pub type Cmp2 = crate::Periph; +impl core::fmt::Debug for Cmp2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Cmp2").finish() + } +} +#[doc = "LPCMP"] +pub use self::cmp0 as cmp2; +#[doc = "12-bit DAC"] +pub type Dac0 = crate::Periph; +impl core::fmt::Debug for Dac0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dac0").finish() + } +} +#[doc = "12-bit DAC"] +pub mod dac0; +#[doc = "OPAMP"] +pub type Opamp0 = crate::Periph; +impl core::fmt::Debug for Opamp0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Opamp0").finish() + } +} +#[doc = "OPAMP"] +pub mod opamp0; +#[doc = "OPAMP"] +pub type Opamp1 = crate::Periph; +impl core::fmt::Debug for Opamp1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Opamp1").finish() + } +} +#[doc = "OPAMP"] +pub use self::opamp0 as opamp1; +#[doc = "OPAMP"] +pub type Opamp2 = crate::Periph; +impl core::fmt::Debug for Opamp2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Opamp2").finish() + } +} +#[doc = "OPAMP"] +pub use self::opamp0 as opamp2; +#[doc = "OPAMP"] +pub type Opamp3 = crate::Periph; +impl core::fmt::Debug for Opamp3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Opamp3").finish() + } +} +#[doc = "OPAMP"] +pub use self::opamp0 as opamp3; +#[doc = "PORT"] +pub type Port0 = crate::Periph; +impl core::fmt::Debug for Port0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Port0").finish() + } +} +#[doc = "PORT"] +pub mod port0; +#[doc = "PORT"] +pub type Port1 = crate::Periph; +impl core::fmt::Debug for Port1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Port1").finish() + } +} +#[doc = "PORT"] +pub mod port1; +#[doc = "PORT"] +pub type Port2 = crate::Periph; +impl core::fmt::Debug for Port2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Port2").finish() + } +} +#[doc = "PORT"] +pub mod port2; +#[doc = "PORT"] +pub type Port3 = crate::Periph; +impl core::fmt::Debug for Port3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Port3").finish() + } +} +#[doc = "PORT"] +pub mod port3; +#[doc = "PORT"] +pub type Port4 = crate::Periph; +impl core::fmt::Debug for Port4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Port4").finish() + } +} +#[doc = "PORT"] +pub mod port4; +#[doc = "SLCD"] +pub type Slcd0 = crate::Periph; +impl core::fmt::Debug for Slcd0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Slcd0").finish() + } +} +#[doc = "SLCD"] +pub mod slcd0; +#[doc = "CAN"] +pub type Can0 = crate::Periph; +impl core::fmt::Debug for Can0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Can0").finish() + } +} +#[doc = "CAN"] +pub mod can0; +#[doc = "CAN"] +pub type Can1 = crate::Periph; +impl core::fmt::Debug for Can1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Can1").finish() + } +} +#[doc = "CAN"] +pub use self::can0 as can1; +#[doc = "TDET"] +pub type Tdet0 = crate::Periph; +impl core::fmt::Debug for Tdet0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tdet0").finish() + } +} +#[doc = "TDET"] +pub mod tdet0; +#[doc = "no description available"] +pub type Pkc0 = crate::Periph; +impl core::fmt::Debug for Pkc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Pkc0").finish() + } +} +#[doc = "no description available"] +pub mod pkc0; +#[doc = "no description available"] +pub type Sgi0 = crate::Periph; +impl core::fmt::Debug for Sgi0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sgi0").finish() + } +} +#[doc = "no description available"] +pub mod sgi0; +#[doc = "pd_main.trng0"] +pub type Trng0 = crate::Periph; +impl core::fmt::Debug for Trng0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Trng0").finish() + } +} +#[doc = "pd_main.trng0"] +pub mod trng0; +#[doc = "no description available"] +pub type Udf0 = crate::Periph; +impl core::fmt::Debug for Udf0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Udf0").finish() + } +} +#[doc = "no description available"] +pub mod udf0; +#[doc = "RTC"] +pub type Rtc0 = crate::Periph; +impl core::fmt::Debug for Rtc0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Rtc0").finish() + } +} +#[doc = "RTC"] +pub mod rtc0; +#[doc = "CDOG"] +pub type Cdog0 = crate::Periph; +impl core::fmt::Debug for Cdog0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Cdog0").finish() + } +} +#[doc = "CDOG"] +pub mod cdog0; +#[doc = "CDOG"] +pub type Cdog1 = crate::Periph; +impl core::fmt::Debug for Cdog1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Cdog1").finish() + } +} +#[doc = "CDOG"] +pub use self::cdog0 as cdog1; +#[doc = "DBGMB"] +pub type Dbgmailbox = crate::Periph; +impl core::fmt::Debug for Dbgmailbox { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dbgmailbox").finish() + } +} +#[doc = "DBGMB"] +pub mod dbgmailbox; +#[doc = "GPIO"] +pub type Gpio0 = crate::Periph; +impl core::fmt::Debug for Gpio0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio0").finish() + } +} +#[doc = "GPIO"] +pub mod gpio0; +#[doc = "GPIO"] +pub type Gpio1 = crate::Periph; +impl core::fmt::Debug for Gpio1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio1").finish() + } +} +#[doc = "GPIO"] +pub use self::gpio0 as gpio1; +#[doc = "GPIO"] +pub type Gpio2 = crate::Periph; +impl core::fmt::Debug for Gpio2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio2").finish() + } +} +#[doc = "GPIO"] +pub use self::gpio0 as gpio2; +#[doc = "GPIO"] +pub type Gpio3 = crate::Periph; +impl core::fmt::Debug for Gpio3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio3").finish() + } +} +#[doc = "GPIO"] +pub use self::gpio0 as gpio3; +#[doc = "GPIO"] +pub type Gpio4 = crate::Periph; +impl core::fmt::Debug for Gpio4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio4").finish() + } +} +#[doc = "GPIO"] +pub use self::gpio0 as gpio4; +#[doc = "MAUWRAP"] +pub type Mau0 = crate::Periph; +impl core::fmt::Debug for Mau0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Mau0").finish() + } +} +#[doc = "MAUWRAP"] +pub mod mau0; +#[doc = "System Control not in System Control Block"] +pub type ScnScb = crate::Periph; +impl core::fmt::Debug for ScnScb { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ScnScb").finish() + } +} +#[doc = "System Control not in System Control Block"] +pub mod scn_scb; +#[doc = "Security Attribution Unit"] +pub type Sau = crate::Periph; +impl core::fmt::Debug for Sau { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sau").finish() + } +} +#[doc = "Security Attribution Unit"] +pub mod sau; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "INPUTMUX0"] + pub inputmux0: Inputmux0, + #[doc = "I3C0"] + pub i3c0: I3c0, + #[doc = "CTIMER0"] + pub ctimer0: Ctimer0, + #[doc = "CTIMER1"] + pub ctimer1: Ctimer1, + #[doc = "CTIMER2"] + pub ctimer2: Ctimer2, + #[doc = "CTIMER3"] + pub ctimer3: Ctimer3, + #[doc = "CTIMER4"] + pub ctimer4: Ctimer4, + #[doc = "FREQME0"] + pub freqme0: Freqme0, + #[doc = "UTICK0"] + pub utick0: Utick0, + #[doc = "WWDT0"] + pub wwdt0: Wwdt0, + #[doc = "SMARTDMA0"] + pub smartdma0: Smartdma0, + #[doc = "DMA0"] + pub dma0: Dma0, + #[doc = "EDMA_0_TCD0"] + pub edma_0_tcd0: Edma0Tcd0, + #[doc = "AOI0"] + pub aoi0: Aoi0, + #[doc = "AOI1"] + pub aoi1: Aoi1, + #[doc = "CRC0"] + pub crc0: Crc0, + #[doc = "CMC"] + pub cmc: Cmc, + #[doc = "EIM0"] + pub eim0: Eim0, + #[doc = "ERM0"] + pub erm0: Erm0, + #[doc = "MBC0"] + pub mbc0: Mbc0, + #[doc = "SCG0"] + pub scg0: Scg0, + #[doc = "SPC0"] + pub spc0: Spc0, + #[doc = "MRCC0"] + pub mrcc0: Mrcc0, + #[doc = "SYSCON"] + pub syscon: Syscon, + #[doc = "GLIKEY0"] + pub glikey0: Glikey0, + #[doc = "WUU0"] + pub wuu0: Wuu0, + #[doc = "VBAT0"] + pub vbat0: Vbat0, + #[doc = "FMC0"] + pub fmc0: Fmc0, + #[doc = "FMU0"] + pub fmu0: Fmu0, + #[doc = "FLEXIO0"] + pub flexio0: Flexio0, + #[doc = "LPI2C0"] + pub lpi2c0: Lpi2c0, + #[doc = "LPI2C1"] + pub lpi2c1: Lpi2c1, + #[doc = "LPI2C2"] + pub lpi2c2: Lpi2c2, + #[doc = "LPI2C3"] + pub lpi2c3: Lpi2c3, + #[doc = "LPSPI0"] + pub lpspi0: Lpspi0, + #[doc = "LPSPI1"] + pub lpspi1: Lpspi1, + #[doc = "LPUART0"] + pub lpuart0: Lpuart0, + #[doc = "LPUART1"] + pub lpuart1: Lpuart1, + #[doc = "LPUART2"] + pub lpuart2: Lpuart2, + #[doc = "LPUART3"] + pub lpuart3: Lpuart3, + #[doc = "LPUART4"] + pub lpuart4: Lpuart4, + #[doc = "LPUART5"] + pub lpuart5: Lpuart5, + #[doc = "USB0"] + pub usb0: Usb0, + #[doc = "EQDC0"] + pub eqdc0: Eqdc0, + #[doc = "EQDC1"] + pub eqdc1: Eqdc1, + #[doc = "FLEXPWM0"] + pub flexpwm0: Flexpwm0, + #[doc = "FLEXPWM1"] + pub flexpwm1: Flexpwm1, + #[doc = "LPTMR0"] + pub lptmr0: Lptmr0, + #[doc = "OSTIMER0"] + pub ostimer0: Ostimer0, + #[doc = "WAKE_TIMER"] + pub waketimer0: Waketimer0, + #[doc = "ADC0"] + pub adc0: Adc0, + #[doc = "ADC1"] + pub adc1: Adc1, + #[doc = "ADC2"] + pub adc2: Adc2, + #[doc = "ADC3"] + pub adc3: Adc3, + #[doc = "CMP0"] + pub cmp0: Cmp0, + #[doc = "CMP1"] + pub cmp1: Cmp1, + #[doc = "CMP2"] + pub cmp2: Cmp2, + #[doc = "DAC0"] + pub dac0: Dac0, + #[doc = "OPAMP0"] + pub opamp0: Opamp0, + #[doc = "OPAMP1"] + pub opamp1: Opamp1, + #[doc = "OPAMP2"] + pub opamp2: Opamp2, + #[doc = "OPAMP3"] + pub opamp3: Opamp3, + #[doc = "PORT0"] + pub port0: Port0, + #[doc = "PORT1"] + pub port1: Port1, + #[doc = "PORT2"] + pub port2: Port2, + #[doc = "PORT3"] + pub port3: Port3, + #[doc = "PORT4"] + pub port4: Port4, + #[doc = "SLCD0"] + pub slcd0: Slcd0, + #[doc = "CAN0"] + pub can0: Can0, + #[doc = "CAN1"] + pub can1: Can1, + #[doc = "TDET0"] + pub tdet0: Tdet0, + #[doc = "PKC0"] + pub pkc0: Pkc0, + #[doc = "SGI0"] + pub sgi0: Sgi0, + #[doc = "TRNG0"] + pub trng0: Trng0, + #[doc = "UDF0"] + pub udf0: Udf0, + #[doc = "RTC0"] + pub rtc0: Rtc0, + #[doc = "CDOG0"] + pub cdog0: Cdog0, + #[doc = "CDOG1"] + pub cdog1: Cdog1, + #[doc = "DBGMAILBOX"] + pub dbgmailbox: Dbgmailbox, + #[doc = "GPIO0"] + pub gpio0: Gpio0, + #[doc = "GPIO1"] + pub gpio1: Gpio1, + #[doc = "GPIO2"] + pub gpio2: Gpio2, + #[doc = "GPIO3"] + pub gpio3: Gpio3, + #[doc = "GPIO4"] + pub gpio4: Gpio4, + #[doc = "MAU0"] + pub mau0: Mau0, + #[doc = "SCnSCB"] + pub scn_scb: ScnScb, + #[doc = "SAU"] + pub sau: Sau, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + inputmux0: Inputmux0::steal(), + i3c0: I3c0::steal(), + ctimer0: Ctimer0::steal(), + ctimer1: Ctimer1::steal(), + ctimer2: Ctimer2::steal(), + ctimer3: Ctimer3::steal(), + ctimer4: Ctimer4::steal(), + freqme0: Freqme0::steal(), + utick0: Utick0::steal(), + wwdt0: Wwdt0::steal(), + smartdma0: Smartdma0::steal(), + dma0: Dma0::steal(), + edma_0_tcd0: Edma0Tcd0::steal(), + aoi0: Aoi0::steal(), + aoi1: Aoi1::steal(), + crc0: Crc0::steal(), + cmc: Cmc::steal(), + eim0: Eim0::steal(), + erm0: Erm0::steal(), + mbc0: Mbc0::steal(), + scg0: Scg0::steal(), + spc0: Spc0::steal(), + mrcc0: Mrcc0::steal(), + syscon: Syscon::steal(), + glikey0: Glikey0::steal(), + wuu0: Wuu0::steal(), + vbat0: Vbat0::steal(), + fmc0: Fmc0::steal(), + fmu0: Fmu0::steal(), + flexio0: Flexio0::steal(), + lpi2c0: Lpi2c0::steal(), + lpi2c1: Lpi2c1::steal(), + lpi2c2: Lpi2c2::steal(), + lpi2c3: Lpi2c3::steal(), + lpspi0: Lpspi0::steal(), + lpspi1: Lpspi1::steal(), + lpuart0: Lpuart0::steal(), + lpuart1: Lpuart1::steal(), + lpuart2: Lpuart2::steal(), + lpuart3: Lpuart3::steal(), + lpuart4: Lpuart4::steal(), + lpuart5: Lpuart5::steal(), + usb0: Usb0::steal(), + eqdc0: Eqdc0::steal(), + eqdc1: Eqdc1::steal(), + flexpwm0: Flexpwm0::steal(), + flexpwm1: Flexpwm1::steal(), + lptmr0: Lptmr0::steal(), + ostimer0: Ostimer0::steal(), + waketimer0: Waketimer0::steal(), + adc0: Adc0::steal(), + adc1: Adc1::steal(), + adc2: Adc2::steal(), + adc3: Adc3::steal(), + cmp0: Cmp0::steal(), + cmp1: Cmp1::steal(), + cmp2: Cmp2::steal(), + dac0: Dac0::steal(), + opamp0: Opamp0::steal(), + opamp1: Opamp1::steal(), + opamp2: Opamp2::steal(), + opamp3: Opamp3::steal(), + port0: Port0::steal(), + port1: Port1::steal(), + port2: Port2::steal(), + port3: Port3::steal(), + port4: Port4::steal(), + slcd0: Slcd0::steal(), + can0: Can0::steal(), + can1: Can1::steal(), + tdet0: Tdet0::steal(), + pkc0: Pkc0::steal(), + sgi0: Sgi0::steal(), + trng0: Trng0::steal(), + udf0: Udf0::steal(), + rtc0: Rtc0::steal(), + cdog0: Cdog0::steal(), + cdog1: Cdog1::steal(), + dbgmailbox: Dbgmailbox::steal(), + gpio0: Gpio0::steal(), + gpio1: Gpio1::steal(), + gpio2: Gpio2::steal(), + gpio3: Gpio3::steal(), + gpio4: Gpio4::steal(), + mau0: Mau0::steal(), + scn_scb: ScnScb::steal(), + sau: Sau::steal(), + } + } +} diff --git a/mcxa276-pac/src/lpi2c0.rs b/mcxa276-pac/src/lpi2c0.rs new file mode 100644 index 000000000..1cbc714e9 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0.rs @@ -0,0 +1,360 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + _reserved2: [u8; 0x08], + mcr: Mcr, + msr: Msr, + mier: Mier, + mder: Mder, + mcfgr0: Mcfgr0, + mcfgr1: Mcfgr1, + mcfgr2: Mcfgr2, + mcfgr3: Mcfgr3, + _reserved10: [u8; 0x10], + mdmr: Mdmr, + _reserved11: [u8; 0x04], + mccr0: Mccr0, + _reserved12: [u8; 0x04], + mccr1: Mccr1, + _reserved13: [u8; 0x04], + mfcr: Mfcr, + mfsr: Mfsr, + mtdr: Mtdr, + _reserved16: [u8; 0x0c], + mrdr: Mrdr, + _reserved17: [u8; 0x04], + mrdror: Mrdror, + _reserved18: [u8; 0x94], + scr: Scr, + ssr: Ssr, + sier: Sier, + sder: Sder, + scfgr0: Scfgr0, + scfgr1: Scfgr1, + scfgr2: Scfgr2, + _reserved25: [u8; 0x14], + samr: Samr, + _reserved26: [u8; 0x0c], + sasr: Sasr, + star: Star, + _reserved28: [u8; 0x08], + stdr: Stdr, + _reserved29: [u8; 0x0c], + srdr: Srdr, + _reserved30: [u8; 0x04], + srdror: Srdror, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x10 - Controller Control"] + #[inline(always)] + pub const fn mcr(&self) -> &Mcr { + &self.mcr + } + #[doc = "0x14 - Controller Status"] + #[inline(always)] + pub const fn msr(&self) -> &Msr { + &self.msr + } + #[doc = "0x18 - Controller Interrupt Enable"] + #[inline(always)] + pub const fn mier(&self) -> &Mier { + &self.mier + } + #[doc = "0x1c - Controller DMA Enable"] + #[inline(always)] + pub const fn mder(&self) -> &Mder { + &self.mder + } + #[doc = "0x20 - Controller Configuration 0"] + #[inline(always)] + pub const fn mcfgr0(&self) -> &Mcfgr0 { + &self.mcfgr0 + } + #[doc = "0x24 - Controller Configuration 1"] + #[inline(always)] + pub const fn mcfgr1(&self) -> &Mcfgr1 { + &self.mcfgr1 + } + #[doc = "0x28 - Controller Configuration 2"] + #[inline(always)] + pub const fn mcfgr2(&self) -> &Mcfgr2 { + &self.mcfgr2 + } + #[doc = "0x2c - Controller Configuration 3"] + #[inline(always)] + pub const fn mcfgr3(&self) -> &Mcfgr3 { + &self.mcfgr3 + } + #[doc = "0x40 - Controller Data Match"] + #[inline(always)] + pub const fn mdmr(&self) -> &Mdmr { + &self.mdmr + } + #[doc = "0x48 - Controller Clock Configuration 0"] + #[inline(always)] + pub const fn mccr0(&self) -> &Mccr0 { + &self.mccr0 + } + #[doc = "0x50 - Controller Clock Configuration 1"] + #[inline(always)] + pub const fn mccr1(&self) -> &Mccr1 { + &self.mccr1 + } + #[doc = "0x58 - Controller FIFO Control"] + #[inline(always)] + pub const fn mfcr(&self) -> &Mfcr { + &self.mfcr + } + #[doc = "0x5c - Controller FIFO Status"] + #[inline(always)] + pub const fn mfsr(&self) -> &Mfsr { + &self.mfsr + } + #[doc = "0x60 - Controller Transmit Data"] + #[inline(always)] + pub const fn mtdr(&self) -> &Mtdr { + &self.mtdr + } + #[doc = "0x70 - Controller Receive Data"] + #[inline(always)] + pub const fn mrdr(&self) -> &Mrdr { + &self.mrdr + } + #[doc = "0x78 - Controller Receive Data Read Only"] + #[inline(always)] + pub const fn mrdror(&self) -> &Mrdror { + &self.mrdror + } + #[doc = "0x110 - Target Control"] + #[inline(always)] + pub const fn scr(&self) -> &Scr { + &self.scr + } + #[doc = "0x114 - Target Status"] + #[inline(always)] + pub const fn ssr(&self) -> &Ssr { + &self.ssr + } + #[doc = "0x118 - Target Interrupt Enable"] + #[inline(always)] + pub const fn sier(&self) -> &Sier { + &self.sier + } + #[doc = "0x11c - Target DMA Enable"] + #[inline(always)] + pub const fn sder(&self) -> &Sder { + &self.sder + } + #[doc = "0x120 - Target Configuration 0"] + #[inline(always)] + pub const fn scfgr0(&self) -> &Scfgr0 { + &self.scfgr0 + } + #[doc = "0x124 - Target Configuration 1"] + #[inline(always)] + pub const fn scfgr1(&self) -> &Scfgr1 { + &self.scfgr1 + } + #[doc = "0x128 - Target Configuration 2"] + #[inline(always)] + pub const fn scfgr2(&self) -> &Scfgr2 { + &self.scfgr2 + } + #[doc = "0x140 - Target Address Match"] + #[inline(always)] + pub const fn samr(&self) -> &Samr { + &self.samr + } + #[doc = "0x150 - Target Address Status"] + #[inline(always)] + pub const fn sasr(&self) -> &Sasr { + &self.sasr + } + #[doc = "0x154 - Target Transmit ACK"] + #[inline(always)] + pub const fn star(&self) -> &Star { + &self.star + } + #[doc = "0x160 - Target Transmit Data"] + #[inline(always)] + pub const fn stdr(&self) -> &Stdr { + &self.stdr + } + #[doc = "0x170 - Target Receive Data"] + #[inline(always)] + pub const fn srdr(&self) -> &Srdr { + &self.srdr + } + #[doc = "0x178 - Target Receive Data Read Only"] + #[inline(always)] + pub const fn srdror(&self) -> &Srdror { + &self.srdror + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "MCR (rw) register accessor: Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] +#[doc(alias = "MCR")] +pub type Mcr = crate::Reg; +#[doc = "Controller Control"] +pub mod mcr; +#[doc = "MSR (rw) register accessor: Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] +#[doc(alias = "MSR")] +pub type Msr = crate::Reg; +#[doc = "Controller Status"] +pub mod msr; +#[doc = "MIER (rw) register accessor: Controller Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mier`] module"] +#[doc(alias = "MIER")] +pub type Mier = crate::Reg; +#[doc = "Controller Interrupt Enable"] +pub mod mier; +#[doc = "MDER (rw) register accessor: Controller DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mder::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mder::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mder`] module"] +#[doc(alias = "MDER")] +pub type Mder = crate::Reg; +#[doc = "Controller DMA Enable"] +pub mod mder; +#[doc = "MCFGR0 (rw) register accessor: Controller Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr0`] module"] +#[doc(alias = "MCFGR0")] +pub type Mcfgr0 = crate::Reg; +#[doc = "Controller Configuration 0"] +pub mod mcfgr0; +#[doc = "MCFGR1 (rw) register accessor: Controller Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr1`] module"] +#[doc(alias = "MCFGR1")] +pub type Mcfgr1 = crate::Reg; +#[doc = "Controller Configuration 1"] +pub mod mcfgr1; +#[doc = "MCFGR2 (rw) register accessor: Controller Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr2`] module"] +#[doc(alias = "MCFGR2")] +pub type Mcfgr2 = crate::Reg; +#[doc = "Controller Configuration 2"] +pub mod mcfgr2; +#[doc = "MCFGR3 (rw) register accessor: Controller Configuration 3\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr3`] module"] +#[doc(alias = "MCFGR3")] +pub type Mcfgr3 = crate::Reg; +#[doc = "Controller Configuration 3"] +pub mod mcfgr3; +#[doc = "MDMR (rw) register accessor: Controller Data Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdmr`] module"] +#[doc(alias = "MDMR")] +pub type Mdmr = crate::Reg; +#[doc = "Controller Data Match"] +pub mod mdmr; +#[doc = "MCCR0 (rw) register accessor: Controller Clock Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mccr0`] module"] +#[doc(alias = "MCCR0")] +pub type Mccr0 = crate::Reg; +#[doc = "Controller Clock Configuration 0"] +pub mod mccr0; +#[doc = "MCCR1 (rw) register accessor: Controller Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mccr1`] module"] +#[doc(alias = "MCCR1")] +pub type Mccr1 = crate::Reg; +#[doc = "Controller Clock Configuration 1"] +pub mod mccr1; +#[doc = "MFCR (rw) register accessor: Controller FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mfcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mfcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfcr`] module"] +#[doc(alias = "MFCR")] +pub type Mfcr = crate::Reg; +#[doc = "Controller FIFO Control"] +pub mod mfcr; +#[doc = "MFSR (r) register accessor: Controller FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mfsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfsr`] module"] +#[doc(alias = "MFSR")] +pub type Mfsr = crate::Reg; +#[doc = "Controller FIFO Status"] +pub mod mfsr; +#[doc = "MTDR (w) register accessor: Controller Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtdr`] module"] +#[doc(alias = "MTDR")] +pub type Mtdr = crate::Reg; +#[doc = "Controller Transmit Data"] +pub mod mtdr; +#[doc = "MRDR (r) register accessor: Controller Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdr`] module"] +#[doc(alias = "MRDR")] +pub type Mrdr = crate::Reg; +#[doc = "Controller Receive Data"] +pub mod mrdr; +#[doc = "MRDROR (r) register accessor: Controller Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdror`] module"] +#[doc(alias = "MRDROR")] +pub type Mrdror = crate::Reg; +#[doc = "Controller Receive Data Read Only"] +pub mod mrdror; +#[doc = "SCR (rw) register accessor: Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] +#[doc(alias = "SCR")] +pub type Scr = crate::Reg; +#[doc = "Target Control"] +pub mod scr; +#[doc = "SSR (rw) register accessor: Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssr`] module"] +#[doc(alias = "SSR")] +pub type Ssr = crate::Reg; +#[doc = "Target Status"] +pub mod ssr; +#[doc = "SIER (rw) register accessor: Target Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sier`] module"] +#[doc(alias = "SIER")] +pub type Sier = crate::Reg; +#[doc = "Target Interrupt Enable"] +pub mod sier; +#[doc = "SDER (rw) register accessor: Target DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sder::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sder::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sder`] module"] +#[doc(alias = "SDER")] +pub type Sder = crate::Reg; +#[doc = "Target DMA Enable"] +pub mod sder; +#[doc = "SCFGR0 (rw) register accessor: Target Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scfgr0`] module"] +#[doc(alias = "SCFGR0")] +pub type Scfgr0 = crate::Reg; +#[doc = "Target Configuration 0"] +pub mod scfgr0; +#[doc = "SCFGR1 (rw) register accessor: Target Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scfgr1`] module"] +#[doc(alias = "SCFGR1")] +pub type Scfgr1 = crate::Reg; +#[doc = "Target Configuration 1"] +pub mod scfgr1; +#[doc = "SCFGR2 (rw) register accessor: Target Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scfgr2`] module"] +#[doc(alias = "SCFGR2")] +pub type Scfgr2 = crate::Reg; +#[doc = "Target Configuration 2"] +pub mod scfgr2; +#[doc = "SAMR (rw) register accessor: Target Address Match\n\nYou can [`read`](crate::Reg::read) this register and get [`samr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`samr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@samr`] module"] +#[doc(alias = "SAMR")] +pub type Samr = crate::Reg; +#[doc = "Target Address Match"] +pub mod samr; +#[doc = "SASR (r) register accessor: Target Address Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sasr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasr`] module"] +#[doc(alias = "SASR")] +pub type Sasr = crate::Reg; +#[doc = "Target Address Status"] +pub mod sasr; +#[doc = "STAR (rw) register accessor: Target Transmit ACK\n\nYou can [`read`](crate::Reg::read) this register and get [`star::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`star::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@star`] module"] +#[doc(alias = "STAR")] +pub type Star = crate::Reg; +#[doc = "Target Transmit ACK"] +pub mod star; +#[doc = "STDR (w) register accessor: Target Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stdr`] module"] +#[doc(alias = "STDR")] +pub type Stdr = crate::Reg; +#[doc = "Target Transmit Data"] +pub mod stdr; +#[doc = "SRDR (r) register accessor: Target Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`srdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdr`] module"] +#[doc(alias = "SRDR")] +pub type Srdr = crate::Reg; +#[doc = "Target Receive Data"] +pub mod srdr; +#[doc = "SRDROR (r) register accessor: Target Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`srdror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdror`] module"] +#[doc(alias = "SRDROR")] +pub type Srdror = crate::Reg; +#[doc = "Target Receive Data Read Only"] +pub mod srdror; diff --git a/mcxa276-pac/src/lpi2c0/mccr0.rs b/mcxa276-pac/src/lpi2c0/mccr0.rs new file mode 100644 index 000000000..bb89863ac --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mccr0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MCCR0` reader"] +pub type R = crate::R; +#[doc = "Register `MCCR0` writer"] +pub type W = crate::W; +#[doc = "Field `CLKLO` reader - Clock Low Period"] +pub type ClkloR = crate::FieldReader; +#[doc = "Field `CLKLO` writer - Clock Low Period"] +pub type ClkloW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CLKHI` reader - Clock High Period"] +pub type ClkhiR = crate::FieldReader; +#[doc = "Field `CLKHI` writer - Clock High Period"] +pub type ClkhiW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SETHOLD` reader - Setup Hold Delay"] +pub type SetholdR = crate::FieldReader; +#[doc = "Field `SETHOLD` writer - Setup Hold Delay"] +pub type SetholdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DATAVD` reader - Data Valid Delay"] +pub type DatavdR = crate::FieldReader; +#[doc = "Field `DATAVD` writer - Data Valid Delay"] +pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Clock Low Period"] + #[inline(always)] + pub fn clklo(&self) -> ClkloR { + ClkloR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - Clock High Period"] + #[inline(always)] + pub fn clkhi(&self) -> ClkhiR { + ClkhiR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Setup Hold Delay"] + #[inline(always)] + pub fn sethold(&self) -> SetholdR { + SetholdR::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Data Valid Delay"] + #[inline(always)] + pub fn datavd(&self) -> DatavdR { + DatavdR::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Clock Low Period"] + #[inline(always)] + pub fn clklo(&mut self) -> ClkloW { + ClkloW::new(self, 0) + } + #[doc = "Bits 8:13 - Clock High Period"] + #[inline(always)] + pub fn clkhi(&mut self) -> ClkhiW { + ClkhiW::new(self, 8) + } + #[doc = "Bits 16:21 - Setup Hold Delay"] + #[inline(always)] + pub fn sethold(&mut self) -> SetholdW { + SetholdW::new(self, 16) + } + #[doc = "Bits 24:29 - Data Valid Delay"] + #[inline(always)] + pub fn datavd(&mut self) -> DatavdW { + DatavdW::new(self, 24) + } +} +#[doc = "Controller Clock Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mccr0Spec; +impl crate::RegisterSpec for Mccr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mccr0::R`](R) reader structure"] +impl crate::Readable for Mccr0Spec {} +#[doc = "`write(|w| ..)` method takes [`mccr0::W`](W) writer structure"] +impl crate::Writable for Mccr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCCR0 to value 0"] +impl crate::Resettable for Mccr0Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mccr1.rs b/mcxa276-pac/src/lpi2c0/mccr1.rs new file mode 100644 index 000000000..5d1ec7c5b --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mccr1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MCCR1` reader"] +pub type R = crate::R; +#[doc = "Register `MCCR1` writer"] +pub type W = crate::W; +#[doc = "Field `CLKLO` reader - Clock Low Period"] +pub type ClkloR = crate::FieldReader; +#[doc = "Field `CLKLO` writer - Clock Low Period"] +pub type ClkloW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CLKHI` reader - Clock High Period"] +pub type ClkhiR = crate::FieldReader; +#[doc = "Field `CLKHI` writer - Clock High Period"] +pub type ClkhiW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SETHOLD` reader - Setup Hold Delay"] +pub type SetholdR = crate::FieldReader; +#[doc = "Field `SETHOLD` writer - Setup Hold Delay"] +pub type SetholdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DATAVD` reader - Data Valid Delay"] +pub type DatavdR = crate::FieldReader; +#[doc = "Field `DATAVD` writer - Data Valid Delay"] +pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Clock Low Period"] + #[inline(always)] + pub fn clklo(&self) -> ClkloR { + ClkloR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - Clock High Period"] + #[inline(always)] + pub fn clkhi(&self) -> ClkhiR { + ClkhiR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Setup Hold Delay"] + #[inline(always)] + pub fn sethold(&self) -> SetholdR { + SetholdR::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Data Valid Delay"] + #[inline(always)] + pub fn datavd(&self) -> DatavdR { + DatavdR::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Clock Low Period"] + #[inline(always)] + pub fn clklo(&mut self) -> ClkloW { + ClkloW::new(self, 0) + } + #[doc = "Bits 8:13 - Clock High Period"] + #[inline(always)] + pub fn clkhi(&mut self) -> ClkhiW { + ClkhiW::new(self, 8) + } + #[doc = "Bits 16:21 - Setup Hold Delay"] + #[inline(always)] + pub fn sethold(&mut self) -> SetholdW { + SetholdW::new(self, 16) + } + #[doc = "Bits 24:29 - Data Valid Delay"] + #[inline(always)] + pub fn datavd(&mut self) -> DatavdW { + DatavdW::new(self, 24) + } +} +#[doc = "Controller Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mccr1Spec; +impl crate::RegisterSpec for Mccr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mccr1::R`](R) reader structure"] +impl crate::Readable for Mccr1Spec {} +#[doc = "`write(|w| ..)` method takes [`mccr1::W`](W) writer structure"] +impl crate::Writable for Mccr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCCR1 to value 0"] +impl crate::Resettable for Mccr1Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr0.rs b/mcxa276-pac/src/lpi2c0/mcfgr0.rs new file mode 100644 index 000000000..ce252d81f --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mcfgr0.rs @@ -0,0 +1,525 @@ +#[doc = "Register `MCFGR0` reader"] +pub type R = crate::R; +#[doc = "Register `MCFGR0` writer"] +pub type W = crate::W; +#[doc = "Host Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hren { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HREN` reader - Host Request Enable"] +pub type HrenR = crate::BitReader; +impl HrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hren { + match self.bits { + false => Hren::Disabled, + true => Hren::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Hren::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Hren::Enabled + } +} +#[doc = "Field `HREN` writer - Host Request Enable"] +pub type HrenW<'a, REG> = crate::BitWriter<'a, REG, Hren>; +impl<'a, REG> HrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Hren::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Hren::Enabled) + } +} +#[doc = "Host Request Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hrpol { + #[doc = "0: Active low"] + ActiveLow = 0, + #[doc = "1: Active high"] + ActiveHigh = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hrpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HRPOL` reader - Host Request Polarity"] +pub type HrpolR = crate::BitReader; +impl HrpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hrpol { + match self.bits { + false => Hrpol::ActiveLow, + true => Hrpol::ActiveHigh, + } + } + #[doc = "Active low"] + #[inline(always)] + pub fn is_active_low(&self) -> bool { + *self == Hrpol::ActiveLow + } + #[doc = "Active high"] + #[inline(always)] + pub fn is_active_high(&self) -> bool { + *self == Hrpol::ActiveHigh + } +} +#[doc = "Field `HRPOL` writer - Host Request Polarity"] +pub type HrpolW<'a, REG> = crate::BitWriter<'a, REG, Hrpol>; +impl<'a, REG> HrpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active low"] + #[inline(always)] + pub fn active_low(self) -> &'a mut crate::W { + self.variant(Hrpol::ActiveLow) + } + #[doc = "Active high"] + #[inline(always)] + pub fn active_high(self) -> &'a mut crate::W { + self.variant(Hrpol::ActiveHigh) + } +} +#[doc = "Host Request Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hrsel { + #[doc = "0: Host request input is pin HREQ"] + Disabled = 0, + #[doc = "1: Host request input is input trigger"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hrsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HRSEL` reader - Host Request Select"] +pub type HrselR = crate::BitReader; +impl HrselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hrsel { + match self.bits { + false => Hrsel::Disabled, + true => Hrsel::Enabled, + } + } + #[doc = "Host request input is pin HREQ"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Hrsel::Disabled + } + #[doc = "Host request input is input trigger"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Hrsel::Enabled + } +} +#[doc = "Field `HRSEL` writer - Host Request Select"] +pub type HrselW<'a, REG> = crate::BitWriter<'a, REG, Hrsel>; +impl<'a, REG> HrselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Host request input is pin HREQ"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Hrsel::Disabled) + } + #[doc = "Host request input is input trigger"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Hrsel::Enabled) + } +} +#[doc = "Host Request Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hrdir { + #[doc = "0: HREQ pin is input (for LPI2C controller)"] + Input = 0, + #[doc = "1: HREQ pin is output (for LPI2C target)"] + Output = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hrdir) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HRDIR` reader - Host Request Direction"] +pub type HrdirR = crate::BitReader; +impl HrdirR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hrdir { + match self.bits { + false => Hrdir::Input, + true => Hrdir::Output, + } + } + #[doc = "HREQ pin is input (for LPI2C controller)"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == Hrdir::Input + } + #[doc = "HREQ pin is output (for LPI2C target)"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == Hrdir::Output + } +} +#[doc = "Field `HRDIR` writer - Host Request Direction"] +pub type HrdirW<'a, REG> = crate::BitWriter<'a, REG, Hrdir>; +impl<'a, REG> HrdirW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "HREQ pin is input (for LPI2C controller)"] + #[inline(always)] + pub fn input(self) -> &'a mut crate::W { + self.variant(Hrdir::Input) + } + #[doc = "HREQ pin is output (for LPI2C target)"] + #[inline(always)] + pub fn output(self) -> &'a mut crate::W { + self.variant(Hrdir::Output) + } +} +#[doc = "Circular FIFO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cirfifo { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cirfifo) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CIRFIFO` reader - Circular FIFO Enable"] +pub type CirfifoR = crate::BitReader; +impl CirfifoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cirfifo { + match self.bits { + false => Cirfifo::Disabled, + true => Cirfifo::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cirfifo::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cirfifo::Enabled + } +} +#[doc = "Field `CIRFIFO` writer - Circular FIFO Enable"] +pub type CirfifoW<'a, REG> = crate::BitWriter<'a, REG, Cirfifo>; +impl<'a, REG> CirfifoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cirfifo::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cirfifo::Enabled) + } +} +#[doc = "Receive Data Match Only\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdmo { + #[doc = "0: Received data is stored in the receive FIFO"] + Disabled = 0, + #[doc = "1: Received data is discarded unless MSR\\[DMF\\] is set"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdmo) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDMO` reader - Receive Data Match Only"] +pub type RdmoR = crate::BitReader; +impl RdmoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdmo { + match self.bits { + false => Rdmo::Disabled, + true => Rdmo::Enabled, + } + } + #[doc = "Received data is stored in the receive FIFO"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdmo::Disabled + } + #[doc = "Received data is discarded unless MSR\\[DMF\\] is set"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdmo::Enabled + } +} +#[doc = "Field `RDMO` writer - Receive Data Match Only"] +pub type RdmoW<'a, REG> = crate::BitWriter<'a, REG, Rdmo>; +impl<'a, REG> RdmoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Received data is stored in the receive FIFO"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rdmo::Disabled) + } + #[doc = "Received data is discarded unless MSR\\[DMF\\] is set"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rdmo::Enabled) + } +} +#[doc = "Relaxed Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Relax { + #[doc = "0: Normal transfer"] + NormalTransfer = 0, + #[doc = "1: Relaxed transfer"] + RelaxedTransfer = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Relax) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RELAX` reader - Relaxed Mode"] +pub type RelaxR = crate::BitReader; +impl RelaxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Relax { + match self.bits { + false => Relax::NormalTransfer, + true => Relax::RelaxedTransfer, + } + } + #[doc = "Normal transfer"] + #[inline(always)] + pub fn is_normal_transfer(&self) -> bool { + *self == Relax::NormalTransfer + } + #[doc = "Relaxed transfer"] + #[inline(always)] + pub fn is_relaxed_transfer(&self) -> bool { + *self == Relax::RelaxedTransfer + } +} +#[doc = "Field `RELAX` writer - Relaxed Mode"] +pub type RelaxW<'a, REG> = crate::BitWriter<'a, REG, Relax>; +impl<'a, REG> RelaxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal transfer"] + #[inline(always)] + pub fn normal_transfer(self) -> &'a mut crate::W { + self.variant(Relax::NormalTransfer) + } + #[doc = "Relaxed transfer"] + #[inline(always)] + pub fn relaxed_transfer(self) -> &'a mut crate::W { + self.variant(Relax::RelaxedTransfer) + } +} +#[doc = "Abort Transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Abort { + #[doc = "0: Normal transfer"] + Disabled = 0, + #[doc = "1: Abort existing transfer and do not start a new one"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Abort) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABORT` reader - Abort Transfer"] +pub type AbortR = crate::BitReader; +impl AbortR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Abort { + match self.bits { + false => Abort::Disabled, + true => Abort::Enabled, + } + } + #[doc = "Normal transfer"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Abort::Disabled + } + #[doc = "Abort existing transfer and do not start a new one"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Abort::Enabled + } +} +#[doc = "Field `ABORT` writer - Abort Transfer"] +pub type AbortW<'a, REG> = crate::BitWriter<'a, REG, Abort>; +impl<'a, REG> AbortW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal transfer"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Abort::Disabled) + } + #[doc = "Abort existing transfer and do not start a new one"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Abort::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Host Request Enable"] + #[inline(always)] + pub fn hren(&self) -> HrenR { + HrenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Host Request Polarity"] + #[inline(always)] + pub fn hrpol(&self) -> HrpolR { + HrpolR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host Request Select"] + #[inline(always)] + pub fn hrsel(&self) -> HrselR { + HrselR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Host Request Direction"] + #[inline(always)] + pub fn hrdir(&self) -> HrdirR { + HrdirR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Circular FIFO Enable"] + #[inline(always)] + pub fn cirfifo(&self) -> CirfifoR { + CirfifoR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Receive Data Match Only"] + #[inline(always)] + pub fn rdmo(&self) -> RdmoR { + RdmoR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 16 - Relaxed Mode"] + #[inline(always)] + pub fn relax(&self) -> RelaxR { + RelaxR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Abort Transfer"] + #[inline(always)] + pub fn abort(&self) -> AbortR { + AbortR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Host Request Enable"] + #[inline(always)] + pub fn hren(&mut self) -> HrenW { + HrenW::new(self, 0) + } + #[doc = "Bit 1 - Host Request Polarity"] + #[inline(always)] + pub fn hrpol(&mut self) -> HrpolW { + HrpolW::new(self, 1) + } + #[doc = "Bit 2 - Host Request Select"] + #[inline(always)] + pub fn hrsel(&mut self) -> HrselW { + HrselW::new(self, 2) + } + #[doc = "Bit 3 - Host Request Direction"] + #[inline(always)] + pub fn hrdir(&mut self) -> HrdirW { + HrdirW::new(self, 3) + } + #[doc = "Bit 8 - Circular FIFO Enable"] + #[inline(always)] + pub fn cirfifo(&mut self) -> CirfifoW { + CirfifoW::new(self, 8) + } + #[doc = "Bit 9 - Receive Data Match Only"] + #[inline(always)] + pub fn rdmo(&mut self) -> RdmoW { + RdmoW::new(self, 9) + } + #[doc = "Bit 16 - Relaxed Mode"] + #[inline(always)] + pub fn relax(&mut self) -> RelaxW { + RelaxW::new(self, 16) + } + #[doc = "Bit 17 - Abort Transfer"] + #[inline(always)] + pub fn abort(&mut self) -> AbortW { + AbortW::new(self, 17) + } +} +#[doc = "Controller Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mcfgr0Spec; +impl crate::RegisterSpec for Mcfgr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcfgr0::R`](R) reader structure"] +impl crate::Readable for Mcfgr0Spec {} +#[doc = "`write(|w| ..)` method takes [`mcfgr0::W`](W) writer structure"] +impl crate::Writable for Mcfgr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCFGR0 to value 0"] +impl crate::Resettable for Mcfgr0Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr1.rs b/mcxa276-pac/src/lpi2c0/mcfgr1.rs new file mode 100644 index 000000000..885d571eb --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mcfgr1.rs @@ -0,0 +1,767 @@ +#[doc = "Register `MCFGR1` reader"] +pub type R = crate::R; +#[doc = "Register `MCFGR1` writer"] +pub type W = crate::W; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Prescale { + #[doc = "0: Divide by 1"] + DivideBy1 = 0, + #[doc = "1: Divide by 2"] + DivideBy2 = 1, + #[doc = "2: Divide by 4"] + DivideBy4 = 2, + #[doc = "3: Divide by 8"] + DivideBy8 = 3, + #[doc = "4: Divide by 16"] + DivideBy16 = 4, + #[doc = "5: Divide by 32"] + DivideBy32 = 5, + #[doc = "6: Divide by 64"] + DivideBy64 = 6, + #[doc = "7: Divide by 128"] + DivideBy128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Prescale) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Prescale { + type Ux = u8; +} +impl crate::IsEnum for Prescale {} +#[doc = "Field `PRESCALE` reader - Prescaler"] +pub type PrescaleR = crate::FieldReader; +impl PrescaleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prescale { + match self.bits { + 0 => Prescale::DivideBy1, + 1 => Prescale::DivideBy2, + 2 => Prescale::DivideBy4, + 3 => Prescale::DivideBy8, + 4 => Prescale::DivideBy16, + 5 => Prescale::DivideBy32, + 6 => Prescale::DivideBy64, + 7 => Prescale::DivideBy128, + _ => unreachable!(), + } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn is_divide_by_1(&self) -> bool { + *self == Prescale::DivideBy1 + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn is_divide_by_2(&self) -> bool { + *self == Prescale::DivideBy2 + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn is_divide_by_4(&self) -> bool { + *self == Prescale::DivideBy4 + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn is_divide_by_8(&self) -> bool { + *self == Prescale::DivideBy8 + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn is_divide_by_16(&self) -> bool { + *self == Prescale::DivideBy16 + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn is_divide_by_32(&self) -> bool { + *self == Prescale::DivideBy32 + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn is_divide_by_64(&self) -> bool { + *self == Prescale::DivideBy64 + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn is_divide_by_128(&self) -> bool { + *self == Prescale::DivideBy128 + } +} +#[doc = "Field `PRESCALE` writer - Prescaler"] +pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescale, crate::Safe>; +impl<'a, REG> PrescaleW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Divide by 1"] + #[inline(always)] + pub fn divide_by_1(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn divide_by_2(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn divide_by_4(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn divide_by_8(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn divide_by_16(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn divide_by_32(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn divide_by_64(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn divide_by_128(self) -> &'a mut crate::W { + self.variant(Prescale::DivideBy128) + } +} +#[doc = "Automatic Stop Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Autostop { + #[doc = "0: No effect"] + Disabled = 0, + #[doc = "1: Stop automatically generated"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Autostop) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AUTOSTOP` reader - Automatic Stop Generation"] +pub type AutostopR = crate::BitReader; +impl AutostopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Autostop { + match self.bits { + false => Autostop::Disabled, + true => Autostop::Enabled, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Autostop::Disabled + } + #[doc = "Stop automatically generated"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Autostop::Enabled + } +} +#[doc = "Field `AUTOSTOP` writer - Automatic Stop Generation"] +pub type AutostopW<'a, REG> = crate::BitWriter<'a, REG, Autostop>; +impl<'a, REG> AutostopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Autostop::Disabled) + } + #[doc = "Stop automatically generated"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Autostop::Enabled) + } +} +#[doc = "Ignore NACK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ignack { + #[doc = "0: No effect"] + Disabled = 0, + #[doc = "1: Treat a received NACK as an ACK"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ignack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IGNACK` reader - Ignore NACK"] +pub type IgnackR = crate::BitReader; +impl IgnackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ignack { + match self.bits { + false => Ignack::Disabled, + true => Ignack::Enabled, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ignack::Disabled + } + #[doc = "Treat a received NACK as an ACK"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ignack::Enabled + } +} +#[doc = "Field `IGNACK` writer - Ignore NACK"] +pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG, Ignack>; +impl<'a, REG> IgnackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ignack::Disabled) + } + #[doc = "Treat a received NACK as an ACK"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ignack::Enabled) + } +} +#[doc = "Timeout Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Timecfg { + #[doc = "0: SCL"] + IfSclLow = 0, + #[doc = "1: SCL or SDA"] + IfSclOrSdaLow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Timecfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIMECFG` reader - Timeout Configuration"] +pub type TimecfgR = crate::BitReader; +impl TimecfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Timecfg { + match self.bits { + false => Timecfg::IfSclLow, + true => Timecfg::IfSclOrSdaLow, + } + } + #[doc = "SCL"] + #[inline(always)] + pub fn is_if_scl_low(&self) -> bool { + *self == Timecfg::IfSclLow + } + #[doc = "SCL or SDA"] + #[inline(always)] + pub fn is_if_scl_or_sda_low(&self) -> bool { + *self == Timecfg::IfSclOrSdaLow + } +} +#[doc = "Field `TIMECFG` writer - Timeout Configuration"] +pub type TimecfgW<'a, REG> = crate::BitWriter<'a, REG, Timecfg>; +impl<'a, REG> TimecfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SCL"] + #[inline(always)] + pub fn if_scl_low(self) -> &'a mut crate::W { + self.variant(Timecfg::IfSclLow) + } + #[doc = "SCL or SDA"] + #[inline(always)] + pub fn if_scl_or_sda_low(self) -> &'a mut crate::W { + self.variant(Timecfg::IfSclOrSdaLow) + } +} +#[doc = "Stop Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stopcfg { + #[doc = "0: Any Stop condition"] + AnyStop = 0, + #[doc = "1: Last Stop condition"] + LastStop = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stopcfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOPCFG` reader - Stop Configuration"] +pub type StopcfgR = crate::BitReader; +impl StopcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stopcfg { + match self.bits { + false => Stopcfg::AnyStop, + true => Stopcfg::LastStop, + } + } + #[doc = "Any Stop condition"] + #[inline(always)] + pub fn is_any_stop(&self) -> bool { + *self == Stopcfg::AnyStop + } + #[doc = "Last Stop condition"] + #[inline(always)] + pub fn is_last_stop(&self) -> bool { + *self == Stopcfg::LastStop + } +} +#[doc = "Field `STOPCFG` writer - Stop Configuration"] +pub type StopcfgW<'a, REG> = crate::BitWriter<'a, REG, Stopcfg>; +impl<'a, REG> StopcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Any Stop condition"] + #[inline(always)] + pub fn any_stop(self) -> &'a mut crate::W { + self.variant(Stopcfg::AnyStop) + } + #[doc = "Last Stop condition"] + #[inline(always)] + pub fn last_stop(self) -> &'a mut crate::W { + self.variant(Stopcfg::LastStop) + } +} +#[doc = "Start Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Startcfg { + #[doc = "0: Sets when both I2C bus and LPI2C controller are idle"] + BothI2cAndLpi2cIdle = 0, + #[doc = "1: Sets when I2C bus is idle"] + I2cIdle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Startcfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STARTCFG` reader - Start Configuration"] +pub type StartcfgR = crate::BitReader; +impl StartcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Startcfg { + match self.bits { + false => Startcfg::BothI2cAndLpi2cIdle, + true => Startcfg::I2cIdle, + } + } + #[doc = "Sets when both I2C bus and LPI2C controller are idle"] + #[inline(always)] + pub fn is_both_i2c_and_lpi2c_idle(&self) -> bool { + *self == Startcfg::BothI2cAndLpi2cIdle + } + #[doc = "Sets when I2C bus is idle"] + #[inline(always)] + pub fn is_i2c_idle(&self) -> bool { + *self == Startcfg::I2cIdle + } +} +#[doc = "Field `STARTCFG` writer - Start Configuration"] +pub type StartcfgW<'a, REG> = crate::BitWriter<'a, REG, Startcfg>; +impl<'a, REG> StartcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Sets when both I2C bus and LPI2C controller are idle"] + #[inline(always)] + pub fn both_i2c_and_lpi2c_idle(self) -> &'a mut crate::W { + self.variant(Startcfg::BothI2cAndLpi2cIdle) + } + #[doc = "Sets when I2C bus is idle"] + #[inline(always)] + pub fn i2c_idle(self) -> &'a mut crate::W { + self.variant(Startcfg::I2cIdle) + } +} +#[doc = "Match Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Matcfg { + #[doc = "0: Match is disabled"] + Disabled = 0, + #[doc = "2: Match is enabled: first data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] + FirstDataWordEqualsMatch0OrMatch1 = 2, + #[doc = "3: Match is enabled: any data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] + AnyDataWordEqualsMatch0OrMatch1 = 3, + #[doc = "4: Match is enabled: (first data word equals MDMR\\[MATCH0\\]) AND (second data word equals MDMR\\[MATCH1)"] + FirstDataWordMatch0AndSecondDataWordMatch1 = 4, + #[doc = "5: Match is enabled: (any data word equals MDMR\\[MATCH0\\]) AND (next data word equals MDMR\\[MATCH1)"] + AnyDataWordMatch0NextDataWordMatch1 = 5, + #[doc = "6: Match is enabled: (first data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] + FirstDataWordAndMatch1EqualsMatch0AndMatch1 = 6, + #[doc = "7: Match is enabled: (any data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] + AnyDataWordAndMatch1EqualsMatch0AndMatch1 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Matcfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Matcfg { + type Ux = u8; +} +impl crate::IsEnum for Matcfg {} +#[doc = "Field `MATCFG` reader - Match Configuration"] +pub type MatcfgR = crate::FieldReader; +impl MatcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Matcfg::Disabled), + 2 => Some(Matcfg::FirstDataWordEqualsMatch0OrMatch1), + 3 => Some(Matcfg::AnyDataWordEqualsMatch0OrMatch1), + 4 => Some(Matcfg::FirstDataWordMatch0AndSecondDataWordMatch1), + 5 => Some(Matcfg::AnyDataWordMatch0NextDataWordMatch1), + 6 => Some(Matcfg::FirstDataWordAndMatch1EqualsMatch0AndMatch1), + 7 => Some(Matcfg::AnyDataWordAndMatch1EqualsMatch0AndMatch1), + _ => None, + } + } + #[doc = "Match is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Matcfg::Disabled + } + #[doc = "Match is enabled: first data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] + #[inline(always)] + pub fn is_first_data_word_equals_match0_or_match1(&self) -> bool { + *self == Matcfg::FirstDataWordEqualsMatch0OrMatch1 + } + #[doc = "Match is enabled: any data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] + #[inline(always)] + pub fn is_any_data_word_equals_match0_or_match1(&self) -> bool { + *self == Matcfg::AnyDataWordEqualsMatch0OrMatch1 + } + #[doc = "Match is enabled: (first data word equals MDMR\\[MATCH0\\]) AND (second data word equals MDMR\\[MATCH1)"] + #[inline(always)] + pub fn is_first_data_word_match0_and_second_data_word_match1(&self) -> bool { + *self == Matcfg::FirstDataWordMatch0AndSecondDataWordMatch1 + } + #[doc = "Match is enabled: (any data word equals MDMR\\[MATCH0\\]) AND (next data word equals MDMR\\[MATCH1)"] + #[inline(always)] + pub fn is_any_data_word_match0_next_data_word_match1(&self) -> bool { + *self == Matcfg::AnyDataWordMatch0NextDataWordMatch1 + } + #[doc = "Match is enabled: (first data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] + #[inline(always)] + pub fn is_first_data_word_and_match1_equals_match0_and_match1(&self) -> bool { + *self == Matcfg::FirstDataWordAndMatch1EqualsMatch0AndMatch1 + } + #[doc = "Match is enabled: (any data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] + #[inline(always)] + pub fn is_any_data_word_and_match1_equals_match0_and_match1(&self) -> bool { + *self == Matcfg::AnyDataWordAndMatch1EqualsMatch0AndMatch1 + } +} +#[doc = "Field `MATCFG` writer - Match Configuration"] +pub type MatcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Matcfg>; +impl<'a, REG> MatcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Match is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Matcfg::Disabled) + } + #[doc = "Match is enabled: first data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] + #[inline(always)] + pub fn first_data_word_equals_match0_or_match1(self) -> &'a mut crate::W { + self.variant(Matcfg::FirstDataWordEqualsMatch0OrMatch1) + } + #[doc = "Match is enabled: any data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] + #[inline(always)] + pub fn any_data_word_equals_match0_or_match1(self) -> &'a mut crate::W { + self.variant(Matcfg::AnyDataWordEqualsMatch0OrMatch1) + } + #[doc = "Match is enabled: (first data word equals MDMR\\[MATCH0\\]) AND (second data word equals MDMR\\[MATCH1)"] + #[inline(always)] + pub fn first_data_word_match0_and_second_data_word_match1(self) -> &'a mut crate::W { + self.variant(Matcfg::FirstDataWordMatch0AndSecondDataWordMatch1) + } + #[doc = "Match is enabled: (any data word equals MDMR\\[MATCH0\\]) AND (next data word equals MDMR\\[MATCH1)"] + #[inline(always)] + pub fn any_data_word_match0_next_data_word_match1(self) -> &'a mut crate::W { + self.variant(Matcfg::AnyDataWordMatch0NextDataWordMatch1) + } + #[doc = "Match is enabled: (first data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] + #[inline(always)] + pub fn first_data_word_and_match1_equals_match0_and_match1(self) -> &'a mut crate::W { + self.variant(Matcfg::FirstDataWordAndMatch1EqualsMatch0AndMatch1) + } + #[doc = "Match is enabled: (any data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] + #[inline(always)] + pub fn any_data_word_and_match1_equals_match0_and_match1(self) -> &'a mut crate::W { + self.variant(Matcfg::AnyDataWordAndMatch1EqualsMatch0AndMatch1) + } +} +#[doc = "Pin Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pincfg { + #[doc = "0: Two-pin open drain mode"] + OpenDrain2Pin = 0, + #[doc = "1: Two-pin output only mode (Ultra-Fast mode)"] + Output2PinOnly = 1, + #[doc = "2: Two-pin push-pull mode"] + PushPull2Pin = 2, + #[doc = "3: Four-pin push-pull mode"] + PushPull4Pin = 3, + #[doc = "4: Two-pin open-drain mode with separate LPI2C target"] + OpenDrain2PinWLpi2cSlave = 4, + #[doc = "5: Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target"] + Output2PinOnlyWLpi2cSlave = 5, + #[doc = "6: Two-pin push-pull mode with separate LPI2C target"] + PushPull2PinWLpi2cSlave = 6, + #[doc = "7: Four-pin push-pull mode (inverted outputs)"] + PushPull4PinWLpi2cSlave = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pincfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pincfg { + type Ux = u8; +} +impl crate::IsEnum for Pincfg {} +#[doc = "Field `PINCFG` reader - Pin Configuration"] +pub type PincfgR = crate::FieldReader; +impl PincfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pincfg { + match self.bits { + 0 => Pincfg::OpenDrain2Pin, + 1 => Pincfg::Output2PinOnly, + 2 => Pincfg::PushPull2Pin, + 3 => Pincfg::PushPull4Pin, + 4 => Pincfg::OpenDrain2PinWLpi2cSlave, + 5 => Pincfg::Output2PinOnlyWLpi2cSlave, + 6 => Pincfg::PushPull2PinWLpi2cSlave, + 7 => Pincfg::PushPull4PinWLpi2cSlave, + _ => unreachable!(), + } + } + #[doc = "Two-pin open drain mode"] + #[inline(always)] + pub fn is_open_drain_2_pin(&self) -> bool { + *self == Pincfg::OpenDrain2Pin + } + #[doc = "Two-pin output only mode (Ultra-Fast mode)"] + #[inline(always)] + pub fn is_output_2_pin_only(&self) -> bool { + *self == Pincfg::Output2PinOnly + } + #[doc = "Two-pin push-pull mode"] + #[inline(always)] + pub fn is_push_pull_2_pin(&self) -> bool { + *self == Pincfg::PushPull2Pin + } + #[doc = "Four-pin push-pull mode"] + #[inline(always)] + pub fn is_push_pull_4_pin(&self) -> bool { + *self == Pincfg::PushPull4Pin + } + #[doc = "Two-pin open-drain mode with separate LPI2C target"] + #[inline(always)] + pub fn is_open_drain_2_pin_w_lpi2c_slave(&self) -> bool { + *self == Pincfg::OpenDrain2PinWLpi2cSlave + } + #[doc = "Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target"] + #[inline(always)] + pub fn is_output_2_pin_only_w_lpi2c_slave(&self) -> bool { + *self == Pincfg::Output2PinOnlyWLpi2cSlave + } + #[doc = "Two-pin push-pull mode with separate LPI2C target"] + #[inline(always)] + pub fn is_push_pull_2_pin_w_lpi2c_slave(&self) -> bool { + *self == Pincfg::PushPull2PinWLpi2cSlave + } + #[doc = "Four-pin push-pull mode (inverted outputs)"] + #[inline(always)] + pub fn is_push_pull_4_pin_w_lpi2c_slave(&self) -> bool { + *self == Pincfg::PushPull4PinWLpi2cSlave + } +} +#[doc = "Field `PINCFG` writer - Pin Configuration"] +pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Pincfg, crate::Safe>; +impl<'a, REG> PincfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Two-pin open drain mode"] + #[inline(always)] + pub fn open_drain_2_pin(self) -> &'a mut crate::W { + self.variant(Pincfg::OpenDrain2Pin) + } + #[doc = "Two-pin output only mode (Ultra-Fast mode)"] + #[inline(always)] + pub fn output_2_pin_only(self) -> &'a mut crate::W { + self.variant(Pincfg::Output2PinOnly) + } + #[doc = "Two-pin push-pull mode"] + #[inline(always)] + pub fn push_pull_2_pin(self) -> &'a mut crate::W { + self.variant(Pincfg::PushPull2Pin) + } + #[doc = "Four-pin push-pull mode"] + #[inline(always)] + pub fn push_pull_4_pin(self) -> &'a mut crate::W { + self.variant(Pincfg::PushPull4Pin) + } + #[doc = "Two-pin open-drain mode with separate LPI2C target"] + #[inline(always)] + pub fn open_drain_2_pin_w_lpi2c_slave(self) -> &'a mut crate::W { + self.variant(Pincfg::OpenDrain2PinWLpi2cSlave) + } + #[doc = "Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target"] + #[inline(always)] + pub fn output_2_pin_only_w_lpi2c_slave(self) -> &'a mut crate::W { + self.variant(Pincfg::Output2PinOnlyWLpi2cSlave) + } + #[doc = "Two-pin push-pull mode with separate LPI2C target"] + #[inline(always)] + pub fn push_pull_2_pin_w_lpi2c_slave(self) -> &'a mut crate::W { + self.variant(Pincfg::PushPull2PinWLpi2cSlave) + } + #[doc = "Four-pin push-pull mode (inverted outputs)"] + #[inline(always)] + pub fn push_pull_4_pin_w_lpi2c_slave(self) -> &'a mut crate::W { + self.variant(Pincfg::PushPull4PinWLpi2cSlave) + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler"] + #[inline(always)] + pub fn prescale(&self) -> PrescaleR { + PrescaleR::new((self.bits & 7) as u8) + } + #[doc = "Bit 8 - Automatic Stop Generation"] + #[inline(always)] + pub fn autostop(&self) -> AutostopR { + AutostopR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Ignore NACK"] + #[inline(always)] + pub fn ignack(&self) -> IgnackR { + IgnackR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Timeout Configuration"] + #[inline(always)] + pub fn timecfg(&self) -> TimecfgR { + TimecfgR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Stop Configuration"] + #[inline(always)] + pub fn stopcfg(&self) -> StopcfgR { + StopcfgR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Start Configuration"] + #[inline(always)] + pub fn startcfg(&self) -> StartcfgR { + StartcfgR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:18 - Match Configuration"] + #[inline(always)] + pub fn matcfg(&self) -> MatcfgR { + MatcfgR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 24:26 - Pin Configuration"] + #[inline(always)] + pub fn pincfg(&self) -> PincfgR { + PincfgR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler"] + #[inline(always)] + pub fn prescale(&mut self) -> PrescaleW { + PrescaleW::new(self, 0) + } + #[doc = "Bit 8 - Automatic Stop Generation"] + #[inline(always)] + pub fn autostop(&mut self) -> AutostopW { + AutostopW::new(self, 8) + } + #[doc = "Bit 9 - Ignore NACK"] + #[inline(always)] + pub fn ignack(&mut self) -> IgnackW { + IgnackW::new(self, 9) + } + #[doc = "Bit 10 - Timeout Configuration"] + #[inline(always)] + pub fn timecfg(&mut self) -> TimecfgW { + TimecfgW::new(self, 10) + } + #[doc = "Bit 11 - Stop Configuration"] + #[inline(always)] + pub fn stopcfg(&mut self) -> StopcfgW { + StopcfgW::new(self, 11) + } + #[doc = "Bit 12 - Start Configuration"] + #[inline(always)] + pub fn startcfg(&mut self) -> StartcfgW { + StartcfgW::new(self, 12) + } + #[doc = "Bits 16:18 - Match Configuration"] + #[inline(always)] + pub fn matcfg(&mut self) -> MatcfgW { + MatcfgW::new(self, 16) + } + #[doc = "Bits 24:26 - Pin Configuration"] + #[inline(always)] + pub fn pincfg(&mut self) -> PincfgW { + PincfgW::new(self, 24) + } +} +#[doc = "Controller Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mcfgr1Spec; +impl crate::RegisterSpec for Mcfgr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcfgr1::R`](R) reader structure"] +impl crate::Readable for Mcfgr1Spec {} +#[doc = "`write(|w| ..)` method takes [`mcfgr1::W`](W) writer structure"] +impl crate::Writable for Mcfgr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCFGR1 to value 0"] +impl crate::Resettable for Mcfgr1Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr2.rs b/mcxa276-pac/src/lpi2c0/mcfgr2.rs new file mode 100644 index 000000000..7b76a8991 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mcfgr2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MCFGR2` reader"] +pub type R = crate::R; +#[doc = "Register `MCFGR2` writer"] +pub type W = crate::W; +#[doc = "Field `BUSIDLE` reader - Bus Idle Timeout"] +pub type BusidleR = crate::FieldReader; +#[doc = "Field `BUSIDLE` writer - Bus Idle Timeout"] +pub type BusidleW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `FILTSCL` reader - Glitch Filter SCL"] +pub type FiltsclR = crate::FieldReader; +#[doc = "Field `FILTSCL` writer - Glitch Filter SCL"] +pub type FiltsclW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `FILTSDA` reader - Glitch Filter SDA"] +pub type FiltsdaR = crate::FieldReader; +#[doc = "Field `FILTSDA` writer - Glitch Filter SDA"] +pub type FiltsdaW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:11 - Bus Idle Timeout"] + #[inline(always)] + pub fn busidle(&self) -> BusidleR { + BusidleR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Glitch Filter SCL"] + #[inline(always)] + pub fn filtscl(&self) -> FiltsclR { + FiltsclR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Glitch Filter SDA"] + #[inline(always)] + pub fn filtsda(&self) -> FiltsdaR { + FiltsdaR::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Bus Idle Timeout"] + #[inline(always)] + pub fn busidle(&mut self) -> BusidleW { + BusidleW::new(self, 0) + } + #[doc = "Bits 16:19 - Glitch Filter SCL"] + #[inline(always)] + pub fn filtscl(&mut self) -> FiltsclW { + FiltsclW::new(self, 16) + } + #[doc = "Bits 24:27 - Glitch Filter SDA"] + #[inline(always)] + pub fn filtsda(&mut self) -> FiltsdaW { + FiltsdaW::new(self, 24) + } +} +#[doc = "Controller Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mcfgr2Spec; +impl crate::RegisterSpec for Mcfgr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcfgr2::R`](R) reader structure"] +impl crate::Readable for Mcfgr2Spec {} +#[doc = "`write(|w| ..)` method takes [`mcfgr2::W`](W) writer structure"] +impl crate::Writable for Mcfgr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCFGR2 to value 0"] +impl crate::Resettable for Mcfgr2Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr3.rs b/mcxa276-pac/src/lpi2c0/mcfgr3.rs new file mode 100644 index 000000000..909e2a0a5 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mcfgr3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `MCFGR3` reader"] +pub type R = crate::R; +#[doc = "Register `MCFGR3` writer"] +pub type W = crate::W; +#[doc = "Field `PINLOW` reader - Pin Low Timeout"] +pub type PinlowR = crate::FieldReader; +#[doc = "Field `PINLOW` writer - Pin Low Timeout"] +pub type PinlowW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 8:19 - Pin Low Timeout"] + #[inline(always)] + pub fn pinlow(&self) -> PinlowR { + PinlowR::new(((self.bits >> 8) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 8:19 - Pin Low Timeout"] + #[inline(always)] + pub fn pinlow(&mut self) -> PinlowW { + PinlowW::new(self, 8) + } +} +#[doc = "Controller Configuration 3\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mcfgr3Spec; +impl crate::RegisterSpec for Mcfgr3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcfgr3::R`](R) reader structure"] +impl crate::Readable for Mcfgr3Spec {} +#[doc = "`write(|w| ..)` method takes [`mcfgr3::W`](W) writer structure"] +impl crate::Writable for Mcfgr3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCFGR3 to value 0"] +impl crate::Resettable for Mcfgr3Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcr.rs b/mcxa276-pac/src/lpi2c0/mcr.rs new file mode 100644 index 000000000..19f2a4eab --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mcr.rs @@ -0,0 +1,399 @@ +#[doc = "Register `MCR` reader"] +pub type R = crate::R; +#[doc = "Register `MCR` writer"] +pub type W = crate::W; +#[doc = "Controller Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Men { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Men) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MEN` reader - Controller Enable"] +pub type MenR = crate::BitReader; +impl MenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Men { + match self.bits { + false => Men::Disabled, + true => Men::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Men::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Men::Enabled + } +} +#[doc = "Field `MEN` writer - Controller Enable"] +pub type MenW<'a, REG> = crate::BitWriter<'a, REG, Men>; +impl<'a, REG> MenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Men::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Men::Enabled) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rst { + #[doc = "0: No effect"] + NotReset = 0, + #[doc = "1: Reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RST` reader - Software Reset"] +pub type RstR = crate::BitReader; +impl RstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rst { + match self.bits { + false => Rst::NotReset, + true => Rst::Reset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_not_reset(&self) -> bool { + *self == Rst::NotReset + } + #[doc = "Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Rst::Reset + } +} +#[doc = "Field `RST` writer - Software Reset"] +pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; +impl<'a, REG> RstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn not_reset(self) -> &'a mut crate::W { + self.variant(Rst::NotReset) + } + #[doc = "Reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Rst::Reset) + } +} +#[doc = "Doze Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dozen { + #[doc = "0: Enable"] + Enabled = 0, + #[doc = "1: Disable"] + Disabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dozen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DOZEN` reader - Doze Mode Enable"] +pub type DozenR = crate::BitReader; +impl DozenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dozen { + match self.bits { + false => Dozen::Enabled, + true => Dozen::Disabled, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dozen::Enabled + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dozen::Disabled + } +} +#[doc = "Field `DOZEN` writer - Doze Mode Enable"] +pub type DozenW<'a, REG> = crate::BitWriter<'a, REG, Dozen>; +impl<'a, REG> DozenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dozen::Enabled) + } + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dozen::Disabled) + } +} +#[doc = "Debug Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dbgen { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dbgen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBGEN` reader - Debug Enable"] +pub type DbgenR = crate::BitReader; +impl DbgenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dbgen { + match self.bits { + false => Dbgen::Disabled, + true => Dbgen::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dbgen::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dbgen::Enabled + } +} +#[doc = "Field `DBGEN` writer - Debug Enable"] +pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG, Dbgen>; +impl<'a, REG> DbgenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dbgen::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dbgen::Enabled) + } +} +#[doc = "Reset Transmit FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rtf { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Reset transmit FIFO"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rtf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RTF` reader - Reset Transmit FIFO"] +pub type RtfR = crate::BitReader; +impl RtfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rtf { + match self.bits { + false => Rtf::NoEffect, + true => Rtf::Reset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rtf::NoEffect + } + #[doc = "Reset transmit FIFO"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Rtf::Reset + } +} +#[doc = "Field `RTF` writer - Reset Transmit FIFO"] +pub type RtfW<'a, REG> = crate::BitWriter<'a, REG, Rtf>; +impl<'a, REG> RtfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rtf::NoEffect) + } + #[doc = "Reset transmit FIFO"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Rtf::Reset) + } +} +#[doc = "Reset Receive FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rrf { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Reset receive FIFO"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rrf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRF` reader - Reset Receive FIFO"] +pub type RrfR = crate::BitReader; +impl RrfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rrf { + match self.bits { + false => Rrf::NoEffect, + true => Rrf::Reset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rrf::NoEffect + } + #[doc = "Reset receive FIFO"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Rrf::Reset + } +} +#[doc = "Field `RRF` writer - Reset Receive FIFO"] +pub type RrfW<'a, REG> = crate::BitWriter<'a, REG, Rrf>; +impl<'a, REG> RrfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rrf::NoEffect) + } + #[doc = "Reset receive FIFO"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Rrf::Reset) + } +} +impl R { + #[doc = "Bit 0 - Controller Enable"] + #[inline(always)] + pub fn men(&self) -> MenR { + MenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&self) -> RstR { + RstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doze Mode Enable"] + #[inline(always)] + pub fn dozen(&self) -> DozenR { + DozenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&self) -> DbgenR { + DbgenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Reset Transmit FIFO"] + #[inline(always)] + pub fn rtf(&self) -> RtfR { + RtfR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reset Receive FIFO"] + #[inline(always)] + pub fn rrf(&self) -> RrfR { + RrfR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controller Enable"] + #[inline(always)] + pub fn men(&mut self) -> MenW { + MenW::new(self, 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RstW { + RstW::new(self, 1) + } + #[doc = "Bit 2 - Doze Mode Enable"] + #[inline(always)] + pub fn dozen(&mut self) -> DozenW { + DozenW::new(self, 2) + } + #[doc = "Bit 3 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&mut self) -> DbgenW { + DbgenW::new(self, 3) + } + #[doc = "Bit 8 - Reset Transmit FIFO"] + #[inline(always)] + pub fn rtf(&mut self) -> RtfW { + RtfW::new(self, 8) + } + #[doc = "Bit 9 - Reset Receive FIFO"] + #[inline(always)] + pub fn rrf(&mut self) -> RrfW { + RrfW::new(self, 9) + } +} +#[doc = "Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct McrSpec; +impl crate::RegisterSpec for McrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for McrSpec {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] +impl crate::Writable for McrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for McrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mder.rs b/mcxa276-pac/src/lpi2c0/mder.rs new file mode 100644 index 000000000..84debc732 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mder.rs @@ -0,0 +1,147 @@ +#[doc = "Register `MDER` reader"] +pub type R = crate::R; +#[doc = "Register `MDER` writer"] +pub type W = crate::W; +#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdde { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"] +pub type TddeR = crate::BitReader; +impl TddeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdde { + match self.bits { + false => Tdde::Disabled, + true => Tdde::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tdde::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tdde::Enabled + } +} +#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"] +pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>; +impl<'a, REG> TddeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tdde::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tdde::Enabled) + } +} +#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdde { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDDE` reader - Receive Data DMA Enable"] +pub type RddeR = crate::BitReader; +impl RddeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdde { + match self.bits { + false => Rdde::Disabled, + true => Rdde::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdde::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdde::Enabled + } +} +#[doc = "Field `RDDE` writer - Receive Data DMA Enable"] +pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>; +impl<'a, REG> RddeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rdde::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rdde::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Transmit Data DMA Enable"] + #[inline(always)] + pub fn tdde(&self) -> TddeR { + TddeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data DMA Enable"] + #[inline(always)] + pub fn rdde(&self) -> RddeR { + RddeR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Data DMA Enable"] + #[inline(always)] + pub fn tdde(&mut self) -> TddeW { + TddeW::new(self, 0) + } + #[doc = "Bit 1 - Receive Data DMA Enable"] + #[inline(always)] + pub fn rdde(&mut self) -> RddeW { + RddeW::new(self, 1) + } +} +#[doc = "Controller DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mder::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mder::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MderSpec; +impl crate::RegisterSpec for MderSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mder::R`](R) reader structure"] +impl crate::Readable for MderSpec {} +#[doc = "`write(|w| ..)` method takes [`mder::W`](W) writer structure"] +impl crate::Writable for MderSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MDER to value 0"] +impl crate::Resettable for MderSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mdmr.rs b/mcxa276-pac/src/lpi2c0/mdmr.rs new file mode 100644 index 000000000..84d8fd1d0 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mdmr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `MDMR` reader"] +pub type R = crate::R; +#[doc = "Register `MDMR` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH0` reader - Match 0 Value"] +pub type Match0R = crate::FieldReader; +#[doc = "Field `MATCH0` writer - Match 0 Value"] +pub type Match0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MATCH1` reader - Match 1 Value"] +pub type Match1R = crate::FieldReader; +#[doc = "Field `MATCH1` writer - Match 1 Value"] +pub type Match1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Match 0 Value"] + #[inline(always)] + pub fn match0(&self) -> Match0R { + Match0R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Match 1 Value"] + #[inline(always)] + pub fn match1(&self) -> Match1R { + Match1R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Match 0 Value"] + #[inline(always)] + pub fn match0(&mut self) -> Match0W { + Match0W::new(self, 0) + } + #[doc = "Bits 16:23 - Match 1 Value"] + #[inline(always)] + pub fn match1(&mut self) -> Match1W { + Match1W::new(self, 16) + } +} +#[doc = "Controller Data Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MdmrSpec; +impl crate::RegisterSpec for MdmrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mdmr::R`](R) reader structure"] +impl crate::Readable for MdmrSpec {} +#[doc = "`write(|w| ..)` method takes [`mdmr::W`](W) writer structure"] +impl crate::Writable for MdmrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MDMR to value 0"] +impl crate::Resettable for MdmrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mfcr.rs b/mcxa276-pac/src/lpi2c0/mfcr.rs new file mode 100644 index 000000000..8e7c44de7 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mfcr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `MFCR` reader"] +pub type R = crate::R; +#[doc = "Register `MFCR` writer"] +pub type W = crate::W; +#[doc = "Field `TXWATER` reader - Transmit FIFO Watermark"] +pub type TxwaterR = crate::FieldReader; +#[doc = "Field `TXWATER` writer - Transmit FIFO Watermark"] +pub type TxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RXWATER` reader - Receive FIFO Watermark"] +pub type RxwaterR = crate::FieldReader; +#[doc = "Field `RXWATER` writer - Receive FIFO Watermark"] +pub type RxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Transmit FIFO Watermark"] + #[inline(always)] + pub fn txwater(&self) -> TxwaterR { + TxwaterR::new((self.bits & 3) as u8) + } + #[doc = "Bits 16:17 - Receive FIFO Watermark"] + #[inline(always)] + pub fn rxwater(&self) -> RxwaterR { + RxwaterR::new(((self.bits >> 16) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Transmit FIFO Watermark"] + #[inline(always)] + pub fn txwater(&mut self) -> TxwaterW { + TxwaterW::new(self, 0) + } + #[doc = "Bits 16:17 - Receive FIFO Watermark"] + #[inline(always)] + pub fn rxwater(&mut self) -> RxwaterW { + RxwaterW::new(self, 16) + } +} +#[doc = "Controller FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mfcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mfcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MfcrSpec; +impl crate::RegisterSpec for MfcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mfcr::R`](R) reader structure"] +impl crate::Readable for MfcrSpec {} +#[doc = "`write(|w| ..)` method takes [`mfcr::W`](W) writer structure"] +impl crate::Writable for MfcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MFCR to value 0"] +impl crate::Resettable for MfcrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mfsr.rs b/mcxa276-pac/src/lpi2c0/mfsr.rs new file mode 100644 index 000000000..43ef0da61 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mfsr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `MFSR` reader"] +pub type R = crate::R; +#[doc = "Field `TXCOUNT` reader - Transmit FIFO Count"] +pub type TxcountR = crate::FieldReader; +#[doc = "Field `RXCOUNT` reader - Receive FIFO Count"] +pub type RxcountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Transmit FIFO Count"] + #[inline(always)] + pub fn txcount(&self) -> TxcountR { + TxcountR::new((self.bits & 7) as u8) + } + #[doc = "Bits 16:18 - Receive FIFO Count"] + #[inline(always)] + pub fn rxcount(&self) -> RxcountR { + RxcountR::new(((self.bits >> 16) & 7) as u8) + } +} +#[doc = "Controller FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mfsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MfsrSpec; +impl crate::RegisterSpec for MfsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mfsr::R`](R) reader structure"] +impl crate::Readable for MfsrSpec {} +#[doc = "`reset()` method sets MFSR to value 0"] +impl crate::Resettable for MfsrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mier.rs b/mcxa276-pac/src/lpi2c0/mier.rs new file mode 100644 index 000000000..d2296722b --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mier.rs @@ -0,0 +1,651 @@ +#[doc = "Register `MIER` reader"] +pub type R = crate::R; +#[doc = "Register `MIER` writer"] +pub type W = crate::W; +#[doc = "Transmit Data Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDIE` reader - Transmit Data Interrupt Enable"] +pub type TdieR = crate::BitReader; +impl TdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdie { + match self.bits { + false => Tdie::Disabled, + true => Tdie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tdie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tdie::Enabled + } +} +#[doc = "Field `TDIE` writer - Transmit Data Interrupt Enable"] +pub type TdieW<'a, REG> = crate::BitWriter<'a, REG, Tdie>; +impl<'a, REG> TdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tdie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tdie::Enabled) + } +} +#[doc = "Receive Data Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDIE` reader - Receive Data Interrupt Enable"] +pub type RdieR = crate::BitReader; +impl RdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdie { + match self.bits { + false => Rdie::Disabled, + true => Rdie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdie::Enabled + } +} +#[doc = "Field `RDIE` writer - Receive Data Interrupt Enable"] +pub type RdieW<'a, REG> = crate::BitWriter<'a, REG, Rdie>; +impl<'a, REG> RdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rdie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rdie::Enabled) + } +} +#[doc = "End Packet Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Epie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Epie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EPIE` reader - End Packet Interrupt Enable"] +pub type EpieR = crate::BitReader; +impl EpieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Epie { + match self.bits { + false => Epie::Disabled, + true => Epie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Epie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Epie::Enabled + } +} +#[doc = "Field `EPIE` writer - End Packet Interrupt Enable"] +pub type EpieW<'a, REG> = crate::BitWriter<'a, REG, Epie>; +impl<'a, REG> EpieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Epie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Epie::Enabled) + } +} +#[doc = "Stop Detect Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sdie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SDIE` reader - Stop Detect Interrupt Enable"] +pub type SdieR = crate::BitReader; +impl SdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sdie { + match self.bits { + false => Sdie::Disabled, + true => Sdie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sdie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sdie::Enabled + } +} +#[doc = "Field `SDIE` writer - Stop Detect Interrupt Enable"] +pub type SdieW<'a, REG> = crate::BitWriter<'a, REG, Sdie>; +impl<'a, REG> SdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sdie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sdie::Enabled) + } +} +#[doc = "NACK Detect Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ndie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ndie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NDIE` reader - NACK Detect Interrupt Enable"] +pub type NdieR = crate::BitReader; +impl NdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ndie { + match self.bits { + false => Ndie::Disabled, + true => Ndie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ndie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ndie::Enabled + } +} +#[doc = "Field `NDIE` writer - NACK Detect Interrupt Enable"] +pub type NdieW<'a, REG> = crate::BitWriter<'a, REG, Ndie>; +impl<'a, REG> NdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ndie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ndie::Enabled) + } +} +#[doc = "Arbitration Lost Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Alie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Alie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ALIE` reader - Arbitration Lost Interrupt Enable"] +pub type AlieR = crate::BitReader; +impl AlieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Alie { + match self.bits { + false => Alie::Disabled, + true => Alie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Alie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Alie::Enabled + } +} +#[doc = "Field `ALIE` writer - Arbitration Lost Interrupt Enable"] +pub type AlieW<'a, REG> = crate::BitWriter<'a, REG, Alie>; +impl<'a, REG> AlieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Alie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Alie::Enabled) + } +} +#[doc = "FIFO Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Feie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Feie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FEIE` reader - FIFO Error Interrupt Enable"] +pub type FeieR = crate::BitReader; +impl FeieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Feie { + match self.bits { + false => Feie::Disabled, + true => Feie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Feie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Feie::Enabled + } +} +#[doc = "Field `FEIE` writer - FIFO Error Interrupt Enable"] +pub type FeieW<'a, REG> = crate::BitWriter<'a, REG, Feie>; +impl<'a, REG> FeieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Feie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Feie::Enabled) + } +} +#[doc = "Pin Low Timeout Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pltie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pltie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PLTIE` reader - Pin Low Timeout Interrupt Enable"] +pub type PltieR = crate::BitReader; +impl PltieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pltie { + match self.bits { + false => Pltie::Disabled, + true => Pltie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pltie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pltie::Enabled + } +} +#[doc = "Field `PLTIE` writer - Pin Low Timeout Interrupt Enable"] +pub type PltieW<'a, REG> = crate::BitWriter<'a, REG, Pltie>; +impl<'a, REG> PltieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pltie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pltie::Enabled) + } +} +#[doc = "Data Match Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMIE` reader - Data Match Interrupt Enable"] +pub type DmieR = crate::BitReader; +impl DmieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmie { + match self.bits { + false => Dmie::Disabled, + true => Dmie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dmie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dmie::Enabled + } +} +#[doc = "Field `DMIE` writer - Data Match Interrupt Enable"] +pub type DmieW<'a, REG> = crate::BitWriter<'a, REG, Dmie>; +impl<'a, REG> DmieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dmie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dmie::Enabled) + } +} +#[doc = "Start Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STIE` reader - Start Interrupt Enable"] +pub type StieR = crate::BitReader; +impl StieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stie { + match self.bits { + false => Stie::Disabled, + true => Stie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Stie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Stie::Enabled + } +} +#[doc = "Field `STIE` writer - Start Interrupt Enable"] +pub type StieW<'a, REG> = crate::BitWriter<'a, REG, Stie>; +impl<'a, REG> StieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Stie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Stie::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Transmit Data Interrupt Enable"] + #[inline(always)] + pub fn tdie(&self) -> TdieR { + TdieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data Interrupt Enable"] + #[inline(always)] + pub fn rdie(&self) -> RdieR { + RdieR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - End Packet Interrupt Enable"] + #[inline(always)] + pub fn epie(&self) -> EpieR { + EpieR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Detect Interrupt Enable"] + #[inline(always)] + pub fn sdie(&self) -> SdieR { + SdieR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NACK Detect Interrupt Enable"] + #[inline(always)] + pub fn ndie(&self) -> NdieR { + NdieR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Arbitration Lost Interrupt Enable"] + #[inline(always)] + pub fn alie(&self) -> AlieR { + AlieR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - FIFO Error Interrupt Enable"] + #[inline(always)] + pub fn feie(&self) -> FeieR { + FeieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pin Low Timeout Interrupt Enable"] + #[inline(always)] + pub fn pltie(&self) -> PltieR { + PltieR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Data Match Interrupt Enable"] + #[inline(always)] + pub fn dmie(&self) -> DmieR { + DmieR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Start Interrupt Enable"] + #[inline(always)] + pub fn stie(&self) -> StieR { + StieR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Data Interrupt Enable"] + #[inline(always)] + pub fn tdie(&mut self) -> TdieW { + TdieW::new(self, 0) + } + #[doc = "Bit 1 - Receive Data Interrupt Enable"] + #[inline(always)] + pub fn rdie(&mut self) -> RdieW { + RdieW::new(self, 1) + } + #[doc = "Bit 8 - End Packet Interrupt Enable"] + #[inline(always)] + pub fn epie(&mut self) -> EpieW { + EpieW::new(self, 8) + } + #[doc = "Bit 9 - Stop Detect Interrupt Enable"] + #[inline(always)] + pub fn sdie(&mut self) -> SdieW { + SdieW::new(self, 9) + } + #[doc = "Bit 10 - NACK Detect Interrupt Enable"] + #[inline(always)] + pub fn ndie(&mut self) -> NdieW { + NdieW::new(self, 10) + } + #[doc = "Bit 11 - Arbitration Lost Interrupt Enable"] + #[inline(always)] + pub fn alie(&mut self) -> AlieW { + AlieW::new(self, 11) + } + #[doc = "Bit 12 - FIFO Error Interrupt Enable"] + #[inline(always)] + pub fn feie(&mut self) -> FeieW { + FeieW::new(self, 12) + } + #[doc = "Bit 13 - Pin Low Timeout Interrupt Enable"] + #[inline(always)] + pub fn pltie(&mut self) -> PltieW { + PltieW::new(self, 13) + } + #[doc = "Bit 14 - Data Match Interrupt Enable"] + #[inline(always)] + pub fn dmie(&mut self) -> DmieW { + DmieW::new(self, 14) + } + #[doc = "Bit 15 - Start Interrupt Enable"] + #[inline(always)] + pub fn stie(&mut self) -> StieW { + StieW::new(self, 15) + } +} +#[doc = "Controller Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MierSpec; +impl crate::RegisterSpec for MierSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mier::R`](R) reader structure"] +impl crate::Readable for MierSpec {} +#[doc = "`write(|w| ..)` method takes [`mier::W`](W) writer structure"] +impl crate::Writable for MierSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MIER to value 0"] +impl crate::Resettable for MierSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mrdr.rs b/mcxa276-pac/src/lpi2c0/mrdr.rs new file mode 100644 index 000000000..77317eaa7 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mrdr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MRDR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Receive Data"] +pub type DataR = crate::FieldReader; +#[doc = "Receive Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempty { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPTY` reader - Receive Empty"] +pub type RxemptyR = crate::BitReader; +impl RxemptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempty { + match self.bits { + false => Rxempty::NotEmpty, + true => Rxempty::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempty::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempty::Empty + } +} +impl R { + #[doc = "Bits 0:7 - Receive Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 14 - Receive Empty"] + #[inline(always)] + pub fn rxempty(&self) -> RxemptyR { + RxemptyR::new(((self.bits >> 14) & 1) != 0) + } +} +#[doc = "Controller Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrdrSpec; +impl crate::RegisterSpec for MrdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrdr::R`](R) reader structure"] +impl crate::Readable for MrdrSpec {} +#[doc = "`reset()` method sets MRDR to value 0x4000"] +impl crate::Resettable for MrdrSpec { + const RESET_VALUE: u32 = 0x4000; +} diff --git a/mcxa276-pac/src/lpi2c0/mrdror.rs b/mcxa276-pac/src/lpi2c0/mrdror.rs new file mode 100644 index 000000000..2b70be11a --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mrdror.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MRDROR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Receive Data"] +pub type DataR = crate::FieldReader; +#[doc = "RX Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempty { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPTY` reader - RX Empty"] +pub type RxemptyR = crate::BitReader; +impl RxemptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempty { + match self.bits { + false => Rxempty::NotEmpty, + true => Rxempty::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempty::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempty::Empty + } +} +impl R { + #[doc = "Bits 0:7 - Receive Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 14 - RX Empty"] + #[inline(always)] + pub fn rxempty(&self) -> RxemptyR { + RxemptyR::new(((self.bits >> 14) & 1) != 0) + } +} +#[doc = "Controller Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrdrorSpec; +impl crate::RegisterSpec for MrdrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrdror::R`](R) reader structure"] +impl crate::Readable for MrdrorSpec {} +#[doc = "`reset()` method sets MRDROR to value 0x4000"] +impl crate::Resettable for MrdrorSpec { + const RESET_VALUE: u32 = 0x4000; +} diff --git a/mcxa276-pac/src/lpi2c0/msr.rs b/mcxa276-pac/src/lpi2c0/msr.rs new file mode 100644 index 000000000..fef810d46 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/msr.rs @@ -0,0 +1,692 @@ +#[doc = "Register `MSR` reader"] +pub type R = crate::R; +#[doc = "Register `MSR` writer"] +pub type W = crate::W; +#[doc = "Transmit Data Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdf { + #[doc = "0: Transmit data not requested"] + Disabled = 0, + #[doc = "1: Transmit data requested"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDF` reader - Transmit Data Flag"] +pub type TdfR = crate::BitReader; +impl TdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdf { + match self.bits { + false => Tdf::Disabled, + true => Tdf::Enabled, + } + } + #[doc = "Transmit data not requested"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tdf::Disabled + } + #[doc = "Transmit data requested"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tdf::Enabled + } +} +#[doc = "Receive Data Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdf { + #[doc = "0: Receive data not ready"] + Disabled = 0, + #[doc = "1: Receive data ready"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDF` reader - Receive Data Flag"] +pub type RdfR = crate::BitReader; +impl RdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdf { + match self.bits { + false => Rdf::Disabled, + true => Rdf::Enabled, + } + } + #[doc = "Receive data not ready"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdf::Disabled + } + #[doc = "Receive data ready"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdf::Enabled + } +} +#[doc = "End Packet Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Epf { + #[doc = "0: No Stop or repeated Start generated"] + IntNo = 0, + #[doc = "1: Stop or repeated Start generated"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Epf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EPF` reader - End Packet Flag"] +pub type EpfR = crate::BitReader; +impl EpfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Epf { + match self.bits { + false => Epf::IntNo, + true => Epf::IntYes, + } + } + #[doc = "No Stop or repeated Start generated"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Epf::IntNo + } + #[doc = "Stop or repeated Start generated"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Epf::IntYes + } +} +#[doc = "Field `EPF` writer - End Packet Flag"] +pub type EpfW<'a, REG> = crate::BitWriter1C<'a, REG, Epf>; +impl<'a, REG> EpfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No Stop or repeated Start generated"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Epf::IntNo) + } + #[doc = "Stop or repeated Start generated"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Epf::IntYes) + } +} +#[doc = "Stop Detect Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sdf { + #[doc = "0: No Stop condition generated"] + IntNo = 0, + #[doc = "1: Stop condition generated"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SDF` reader - Stop Detect Flag"] +pub type SdfR = crate::BitReader; +impl SdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sdf { + match self.bits { + false => Sdf::IntNo, + true => Sdf::IntYes, + } + } + #[doc = "No Stop condition generated"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Sdf::IntNo + } + #[doc = "Stop condition generated"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Sdf::IntYes + } +} +#[doc = "Field `SDF` writer - Stop Detect Flag"] +pub type SdfW<'a, REG> = crate::BitWriter1C<'a, REG, Sdf>; +impl<'a, REG> SdfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No Stop condition generated"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Sdf::IntNo) + } + #[doc = "Stop condition generated"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Sdf::IntYes) + } +} +#[doc = "NACK Detect Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ndf { + #[doc = "0: No unexpected NACK detected"] + IntNo = 0, + #[doc = "1: Unexpected NACK detected"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ndf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NDF` reader - NACK Detect Flag"] +pub type NdfR = crate::BitReader; +impl NdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ndf { + match self.bits { + false => Ndf::IntNo, + true => Ndf::IntYes, + } + } + #[doc = "No unexpected NACK detected"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Ndf::IntNo + } + #[doc = "Unexpected NACK detected"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Ndf::IntYes + } +} +#[doc = "Field `NDF` writer - NACK Detect Flag"] +pub type NdfW<'a, REG> = crate::BitWriter1C<'a, REG, Ndf>; +impl<'a, REG> NdfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No unexpected NACK detected"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Ndf::IntNo) + } + #[doc = "Unexpected NACK detected"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Ndf::IntYes) + } +} +#[doc = "Arbitration Lost Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Alf { + #[doc = "0: Controller did not lose arbitration"] + IntNo = 0, + #[doc = "1: Controller lost arbitration"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Alf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ALF` reader - Arbitration Lost Flag"] +pub type AlfR = crate::BitReader; +impl AlfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Alf { + match self.bits { + false => Alf::IntNo, + true => Alf::IntYes, + } + } + #[doc = "Controller did not lose arbitration"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Alf::IntNo + } + #[doc = "Controller lost arbitration"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Alf::IntYes + } +} +#[doc = "Field `ALF` writer - Arbitration Lost Flag"] +pub type AlfW<'a, REG> = crate::BitWriter1C<'a, REG, Alf>; +impl<'a, REG> AlfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Controller did not lose arbitration"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Alf::IntNo) + } + #[doc = "Controller lost arbitration"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Alf::IntYes) + } +} +#[doc = "FIFO Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fef { + #[doc = "0: No FIFO error"] + IntNo = 0, + #[doc = "1: FIFO error"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fef) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FEF` reader - FIFO Error Flag"] +pub type FefR = crate::BitReader; +impl FefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fef { + match self.bits { + false => Fef::IntNo, + true => Fef::IntYes, + } + } + #[doc = "No FIFO error"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Fef::IntNo + } + #[doc = "FIFO error"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Fef::IntYes + } +} +#[doc = "Field `FEF` writer - FIFO Error Flag"] +pub type FefW<'a, REG> = crate::BitWriter1C<'a, REG, Fef>; +impl<'a, REG> FefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No FIFO error"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Fef::IntNo) + } + #[doc = "FIFO error"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Fef::IntYes) + } +} +#[doc = "Pin Low Timeout Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pltf { + #[doc = "0: Pin low timeout did not occur"] + IntNo = 0, + #[doc = "1: Pin low timeout occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pltf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PLTF` reader - Pin Low Timeout Flag"] +pub type PltfR = crate::BitReader; +impl PltfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pltf { + match self.bits { + false => Pltf::IntNo, + true => Pltf::IntYes, + } + } + #[doc = "Pin low timeout did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Pltf::IntNo + } + #[doc = "Pin low timeout occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Pltf::IntYes + } +} +#[doc = "Field `PLTF` writer - Pin Low Timeout Flag"] +pub type PltfW<'a, REG> = crate::BitWriter1C<'a, REG, Pltf>; +impl<'a, REG> PltfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin low timeout did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Pltf::IntNo) + } + #[doc = "Pin low timeout occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Pltf::IntYes) + } +} +#[doc = "Data Match Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmf { + #[doc = "0: Matching data not received"] + IntNo = 0, + #[doc = "1: Matching data received"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMF` reader - Data Match Flag"] +pub type DmfR = crate::BitReader; +impl DmfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmf { + match self.bits { + false => Dmf::IntNo, + true => Dmf::IntYes, + } + } + #[doc = "Matching data not received"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Dmf::IntNo + } + #[doc = "Matching data received"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Dmf::IntYes + } +} +#[doc = "Field `DMF` writer - Data Match Flag"] +pub type DmfW<'a, REG> = crate::BitWriter1C<'a, REG, Dmf>; +impl<'a, REG> DmfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Matching data not received"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Dmf::IntNo) + } + #[doc = "Matching data received"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Dmf::IntYes) + } +} +#[doc = "Start Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stf { + #[doc = "0: Start condition not detected"] + IntNo = 0, + #[doc = "1: Start condition detected"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STF` reader - Start Flag"] +pub type StfR = crate::BitReader; +impl StfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stf { + match self.bits { + false => Stf::IntNo, + true => Stf::IntYes, + } + } + #[doc = "Start condition not detected"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Stf::IntNo + } + #[doc = "Start condition detected"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Stf::IntYes + } +} +#[doc = "Field `STF` writer - Start Flag"] +pub type StfW<'a, REG> = crate::BitWriter1C<'a, REG, Stf>; +impl<'a, REG> StfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Start condition not detected"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Stf::IntNo) + } + #[doc = "Start condition detected"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Stf::IntYes) + } +} +#[doc = "Controller Busy Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mbf { + #[doc = "0: Idle"] + Idle = 0, + #[doc = "1: Busy"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MBF` reader - Controller Busy Flag"] +pub type MbfR = crate::BitReader; +impl MbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbf { + match self.bits { + false => Mbf::Idle, + true => Mbf::Busy, + } + } + #[doc = "Idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Mbf::Idle + } + #[doc = "Busy"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Mbf::Busy + } +} +#[doc = "Bus Busy Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bbf { + #[doc = "0: Idle"] + Idle = 0, + #[doc = "1: Busy"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BBF` reader - Bus Busy Flag"] +pub type BbfR = crate::BitReader; +impl BbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bbf { + match self.bits { + false => Bbf::Idle, + true => Bbf::Busy, + } + } + #[doc = "Idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Bbf::Idle + } + #[doc = "Busy"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Bbf::Busy + } +} +impl R { + #[doc = "Bit 0 - Transmit Data Flag"] + #[inline(always)] + pub fn tdf(&self) -> TdfR { + TdfR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data Flag"] + #[inline(always)] + pub fn rdf(&self) -> RdfR { + RdfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - End Packet Flag"] + #[inline(always)] + pub fn epf(&self) -> EpfR { + EpfR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Detect Flag"] + #[inline(always)] + pub fn sdf(&self) -> SdfR { + SdfR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NACK Detect Flag"] + #[inline(always)] + pub fn ndf(&self) -> NdfR { + NdfR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Arbitration Lost Flag"] + #[inline(always)] + pub fn alf(&self) -> AlfR { + AlfR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - FIFO Error Flag"] + #[inline(always)] + pub fn fef(&self) -> FefR { + FefR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pin Low Timeout Flag"] + #[inline(always)] + pub fn pltf(&self) -> PltfR { + PltfR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Data Match Flag"] + #[inline(always)] + pub fn dmf(&self) -> DmfR { + DmfR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Start Flag"] + #[inline(always)] + pub fn stf(&self) -> StfR { + StfR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 24 - Controller Busy Flag"] + #[inline(always)] + pub fn mbf(&self) -> MbfR { + MbfR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Bus Busy Flag"] + #[inline(always)] + pub fn bbf(&self) -> BbfR { + BbfR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - End Packet Flag"] + #[inline(always)] + pub fn epf(&mut self) -> EpfW { + EpfW::new(self, 8) + } + #[doc = "Bit 9 - Stop Detect Flag"] + #[inline(always)] + pub fn sdf(&mut self) -> SdfW { + SdfW::new(self, 9) + } + #[doc = "Bit 10 - NACK Detect Flag"] + #[inline(always)] + pub fn ndf(&mut self) -> NdfW { + NdfW::new(self, 10) + } + #[doc = "Bit 11 - Arbitration Lost Flag"] + #[inline(always)] + pub fn alf(&mut self) -> AlfW { + AlfW::new(self, 11) + } + #[doc = "Bit 12 - FIFO Error Flag"] + #[inline(always)] + pub fn fef(&mut self) -> FefW { + FefW::new(self, 12) + } + #[doc = "Bit 13 - Pin Low Timeout Flag"] + #[inline(always)] + pub fn pltf(&mut self) -> PltfW { + PltfW::new(self, 13) + } + #[doc = "Bit 14 - Data Match Flag"] + #[inline(always)] + pub fn dmf(&mut self) -> DmfW { + DmfW::new(self, 14) + } + #[doc = "Bit 15 - Start Flag"] + #[inline(always)] + pub fn stf(&mut self) -> StfW { + StfW::new(self, 15) + } +} +#[doc = "Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MsrSpec; +impl crate::RegisterSpec for MsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`msr::R`](R) reader structure"] +impl crate::Readable for MsrSpec {} +#[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"] +impl crate::Writable for MsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff00; +} +#[doc = "`reset()` method sets MSR to value 0x01"] +impl crate::Resettable for MsrSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/lpi2c0/mtdr.rs b/mcxa276-pac/src/lpi2c0/mtdr.rs new file mode 100644 index 000000000..385d0b4cc --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/mtdr.rs @@ -0,0 +1,114 @@ +#[doc = "Register `MTDR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Transmit Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Command Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmd { + #[doc = "0: Transmit the value in DATA\\[7:0\\]"] + TransmitData7Through0 = 0, + #[doc = "1: Receive (DATA\\[7:0\\] + 1) bytes"] + ReceiveData7Through0PlusOne = 1, + #[doc = "2: Generate Stop condition on I2C bus"] + GenerateStopCondition = 2, + #[doc = "3: Receive and discard (DATA\\[7:0\\] + 1) bytes"] + ReceiveAndDiscardData7Through0PlusOne = 3, + #[doc = "4: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\]"] + GenerateStartAndTransmitAddressInData7Through0 = 4, + #[doc = "5: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] (this transfer expects a NACK to be returned)"] + GenerateStartAndTransmitAddressInData7Through0ExpectNack = 5, + #[doc = "6: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode"] + GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedMode = 6, + #[doc = "7: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode (this transfer expects a NACK to be returned)"] + GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedModeExpectNack = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmd) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmd { + type Ux = u8; +} +impl crate::IsEnum for Cmd {} +#[doc = "Field `CMD` writer - Command Data"] +pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 3, Cmd, crate::Safe>; +impl<'a, REG> CmdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Transmit the value in DATA\\[7:0\\]"] + #[inline(always)] + pub fn transmit_data_7_through_0(self) -> &'a mut crate::W { + self.variant(Cmd::TransmitData7Through0) + } + #[doc = "Receive (DATA\\[7:0\\] + 1) bytes"] + #[inline(always)] + pub fn receive_data_7_through_0_plus_one(self) -> &'a mut crate::W { + self.variant(Cmd::ReceiveData7Through0PlusOne) + } + #[doc = "Generate Stop condition on I2C bus"] + #[inline(always)] + pub fn generate_stop_condition(self) -> &'a mut crate::W { + self.variant(Cmd::GenerateStopCondition) + } + #[doc = "Receive and discard (DATA\\[7:0\\] + 1) bytes"] + #[inline(always)] + pub fn receive_and_discard_data_7_through_0_plus_one(self) -> &'a mut crate::W { + self.variant(Cmd::ReceiveAndDiscardData7Through0PlusOne) + } + #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\]"] + #[inline(always)] + pub fn generate_start_and_transmit_address_in_data_7_through_0(self) -> &'a mut crate::W { + self.variant(Cmd::GenerateStartAndTransmitAddressInData7Through0) + } + #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] (this transfer expects a NACK to be returned)"] + #[inline(always)] + pub fn generate_start_and_transmit_address_in_data_7_through_0_expect_nack( + self, + ) -> &'a mut crate::W { + self.variant(Cmd::GenerateStartAndTransmitAddressInData7Through0ExpectNack) + } + #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode"] + #[inline(always)] + pub fn generate_start_and_transmit_address_in_data_7_through_0_using_high_speed_mode( + self, + ) -> &'a mut crate::W { + self.variant(Cmd::GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedMode) + } + #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode (this transfer expects a NACK to be returned)"] + #[inline(always)] + pub fn generate_start_and_transmit_address_in_data_7_through_0_using_high_speed_mode_expect_nack( + self, + ) -> &'a mut crate::W { + self.variant( + Cmd::GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedModeExpectNack, + ) + } +} +impl W { + #[doc = "Bits 0:7 - Transmit Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } + #[doc = "Bits 8:10 - Command Data"] + #[inline(always)] + pub fn cmd(&mut self) -> CmdW { + CmdW::new(self, 8) + } +} +#[doc = "Controller Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MtdrSpec; +impl crate::RegisterSpec for MtdrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mtdr::W`](W) writer structure"] +impl crate::Writable for MtdrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MTDR to value 0"] +impl crate::Resettable for MtdrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/param.rs b/mcxa276-pac/src/lpi2c0/param.rs new file mode 100644 index 000000000..ae15d2371 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/param.rs @@ -0,0 +1,29 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "Field `MTXFIFO` reader - Controller Transmit FIFO Size"] +pub type MtxfifoR = crate::FieldReader; +#[doc = "Field `MRXFIFO` reader - Controller Receive FIFO Size"] +pub type MrxfifoR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Controller Transmit FIFO Size"] + #[inline(always)] + pub fn mtxfifo(&self) -> MtxfifoR { + MtxfifoR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Controller Receive FIFO Size"] + #[inline(always)] + pub fn mrxfifo(&self) -> MrxfifoR { + MrxfifoR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x0202"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x0202; +} diff --git a/mcxa276-pac/src/lpi2c0/samr.rs b/mcxa276-pac/src/lpi2c0/samr.rs new file mode 100644 index 000000000..db89ce068 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/samr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SAMR` reader"] +pub type R = crate::R; +#[doc = "Register `SAMR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR0` reader - Address 0 Value"] +pub type Addr0R = crate::FieldReader; +#[doc = "Field `ADDR0` writer - Address 0 Value"] +pub type Addr0W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `ADDR1` reader - Address 1 Value"] +pub type Addr1R = crate::FieldReader; +#[doc = "Field `ADDR1` writer - Address 1 Value"] +pub type Addr1W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 1:10 - Address 0 Value"] + #[inline(always)] + pub fn addr0(&self) -> Addr0R { + Addr0R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bits 17:26 - Address 1 Value"] + #[inline(always)] + pub fn addr1(&self) -> Addr1R { + Addr1R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 1:10 - Address 0 Value"] + #[inline(always)] + pub fn addr0(&mut self) -> Addr0W { + Addr0W::new(self, 1) + } + #[doc = "Bits 17:26 - Address 1 Value"] + #[inline(always)] + pub fn addr1(&mut self) -> Addr1W { + Addr1W::new(self, 17) + } +} +#[doc = "Target Address Match\n\nYou can [`read`](crate::Reg::read) this register and get [`samr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`samr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SamrSpec; +impl crate::RegisterSpec for SamrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`samr::R`](R) reader structure"] +impl crate::Readable for SamrSpec {} +#[doc = "`write(|w| ..)` method takes [`samr::W`](W) writer structure"] +impl crate::Writable for SamrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SAMR to value 0"] +impl crate::Resettable for SamrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/sasr.rs b/mcxa276-pac/src/lpi2c0/sasr.rs new file mode 100644 index 000000000..c0dc0706c --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/sasr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SASR` reader"] +pub type R = crate::R; +#[doc = "Field `RADDR` reader - Received Address"] +pub type RaddrR = crate::FieldReader; +#[doc = "Address Not Valid\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Anv { + #[doc = "0: Valid"] + Valid = 0, + #[doc = "1: Not valid"] + NotValid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Anv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ANV` reader - Address Not Valid"] +pub type AnvR = crate::BitReader; +impl AnvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Anv { + match self.bits { + false => Anv::Valid, + true => Anv::NotValid, + } + } + #[doc = "Valid"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Anv::Valid + } + #[doc = "Not valid"] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Anv::NotValid + } +} +impl R { + #[doc = "Bits 0:10 - Received Address"] + #[inline(always)] + pub fn raddr(&self) -> RaddrR { + RaddrR::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 14 - Address Not Valid"] + #[inline(always)] + pub fn anv(&self) -> AnvR { + AnvR::new(((self.bits >> 14) & 1) != 0) + } +} +#[doc = "Target Address Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sasr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SasrSpec; +impl crate::RegisterSpec for SasrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sasr::R`](R) reader structure"] +impl crate::Readable for SasrSpec {} +#[doc = "`reset()` method sets SASR to value 0x4000"] +impl crate::Resettable for SasrSpec { + const RESET_VALUE: u32 = 0x4000; +} diff --git a/mcxa276-pac/src/lpi2c0/scfgr0.rs b/mcxa276-pac/src/lpi2c0/scfgr0.rs new file mode 100644 index 000000000..bff09fe01 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/scfgr0.rs @@ -0,0 +1,125 @@ +#[doc = "Register `SCFGR0` reader"] +pub type R = crate::R; +#[doc = "Register `SCFGR0` writer"] +pub type W = crate::W; +#[doc = "Read Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdreq { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdreq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDREQ` reader - Read Request"] +pub type RdreqR = crate::BitReader; +impl RdreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdreq { + match self.bits { + false => Rdreq::Disabled, + true => Rdreq::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdreq::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdreq::Enabled + } +} +#[doc = "Field `RDREQ` writer - Read Request"] +pub type RdreqW<'a, REG> = crate::BitWriter<'a, REG, Rdreq>; +impl<'a, REG> RdreqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rdreq::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rdreq::Enabled) + } +} +#[doc = "Read Acknowledge Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdack { + #[doc = "0: Read Request not acknowledged"] + NotAcknowledged = 0, + #[doc = "1: Read Request acknowledged"] + Acknowledged = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDACK` reader - Read Acknowledge Flag"] +pub type RdackR = crate::BitReader; +impl RdackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdack { + match self.bits { + false => Rdack::NotAcknowledged, + true => Rdack::Acknowledged, + } + } + #[doc = "Read Request not acknowledged"] + #[inline(always)] + pub fn is_not_acknowledged(&self) -> bool { + *self == Rdack::NotAcknowledged + } + #[doc = "Read Request acknowledged"] + #[inline(always)] + pub fn is_acknowledged(&self) -> bool { + *self == Rdack::Acknowledged + } +} +impl R { + #[doc = "Bit 0 - Read Request"] + #[inline(always)] + pub fn rdreq(&self) -> RdreqR { + RdreqR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read Acknowledge Flag"] + #[inline(always)] + pub fn rdack(&self) -> RdackR { + RdackR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read Request"] + #[inline(always)] + pub fn rdreq(&mut self) -> RdreqW { + RdreqW::new(self, 0) + } +} +#[doc = "Target Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scfgr0Spec; +impl crate::RegisterSpec for Scfgr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scfgr0::R`](R) reader structure"] +impl crate::Readable for Scfgr0Spec {} +#[doc = "`write(|w| ..)` method takes [`scfgr0::W`](W) writer structure"] +impl crate::Writable for Scfgr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCFGR0 to value 0"] +impl crate::Resettable for Scfgr0Spec {} diff --git a/mcxa276-pac/src/lpi2c0/scfgr1.rs b/mcxa276-pac/src/lpi2c0/scfgr1.rs new file mode 100644 index 000000000..e3a809032 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/scfgr1.rs @@ -0,0 +1,1057 @@ +#[doc = "Register `SCFGR1` reader"] +pub type R = crate::R; +#[doc = "Register `SCFGR1` writer"] +pub type W = crate::W; +#[doc = "Address SCL Stall\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adrstall { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adrstall) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADRSTALL` reader - Address SCL Stall"] +pub type AdrstallR = crate::BitReader; +impl AdrstallR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adrstall { + match self.bits { + false => Adrstall::Disabled, + true => Adrstall::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adrstall::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adrstall::Enabled + } +} +#[doc = "Field `ADRSTALL` writer - Address SCL Stall"] +pub type AdrstallW<'a, REG> = crate::BitWriter<'a, REG, Adrstall>; +impl<'a, REG> AdrstallW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adrstall::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adrstall::Enabled) + } +} +#[doc = "RX SCL Stall\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxstall { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxstall) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXSTALL` reader - RX SCL Stall"] +pub type RxstallR = crate::BitReader; +impl RxstallR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxstall { + match self.bits { + false => Rxstall::Disabled, + true => Rxstall::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rxstall::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rxstall::Enabled + } +} +#[doc = "Field `RXSTALL` writer - RX SCL Stall"] +pub type RxstallW<'a, REG> = crate::BitWriter<'a, REG, Rxstall>; +impl<'a, REG> RxstallW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rxstall::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rxstall::Enabled) + } +} +#[doc = "Transmit Data SCL Stall\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txdstall { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txdstall) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXDSTALL` reader - Transmit Data SCL Stall"] +pub type TxdstallR = crate::BitReader; +impl TxdstallR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txdstall { + match self.bits { + false => Txdstall::Disabled, + true => Txdstall::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Txdstall::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Txdstall::Enabled + } +} +#[doc = "Field `TXDSTALL` writer - Transmit Data SCL Stall"] +pub type TxdstallW<'a, REG> = crate::BitWriter<'a, REG, Txdstall>; +impl<'a, REG> TxdstallW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Txdstall::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Txdstall::Enabled) + } +} +#[doc = "ACK SCL Stall\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ackstall { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ackstall) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACKSTALL` reader - ACK SCL Stall"] +pub type AckstallR = crate::BitReader; +impl AckstallR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ackstall { + match self.bits { + false => Ackstall::Disabled, + true => Ackstall::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ackstall::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ackstall::Enabled + } +} +#[doc = "Field `ACKSTALL` writer - ACK SCL Stall"] +pub type AckstallW<'a, REG> = crate::BitWriter<'a, REG, Ackstall>; +impl<'a, REG> AckstallW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ackstall::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ackstall::Enabled) + } +} +#[doc = "Receive NACK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxnack { + #[doc = "0: ACK or NACK always determined by STAR\\[TXNACK\\]"] + SetByTxnack = 0, + #[doc = "1: NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"] + AlwaysGeneratedOnAddressOrReceiveDataOverrun = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxnack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXNACK` reader - Receive NACK"] +pub type RxnackR = crate::BitReader; +impl RxnackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxnack { + match self.bits { + false => Rxnack::SetByTxnack, + true => Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun, + } + } + #[doc = "ACK or NACK always determined by STAR\\[TXNACK\\]"] + #[inline(always)] + pub fn is_set_by_txnack(&self) -> bool { + *self == Rxnack::SetByTxnack + } + #[doc = "NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"] + #[inline(always)] + pub fn is_always_generated_on_address_or_receive_data_overrun(&self) -> bool { + *self == Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun + } +} +#[doc = "Field `RXNACK` writer - Receive NACK"] +pub type RxnackW<'a, REG> = crate::BitWriter<'a, REG, Rxnack>; +impl<'a, REG> RxnackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ACK or NACK always determined by STAR\\[TXNACK\\]"] + #[inline(always)] + pub fn set_by_txnack(self) -> &'a mut crate::W { + self.variant(Rxnack::SetByTxnack) + } + #[doc = "NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"] + #[inline(always)] + pub fn always_generated_on_address_or_receive_data_overrun(self) -> &'a mut crate::W { + self.variant(Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun) + } +} +#[doc = "General Call Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gcen { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gcen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GCEN` reader - General Call Enable"] +pub type GcenR = crate::BitReader; +impl GcenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gcen { + match self.bits { + false => Gcen::Disabled, + true => Gcen::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gcen::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gcen::Enabled + } +} +#[doc = "Field `GCEN` writer - General Call Enable"] +pub type GcenW<'a, REG> = crate::BitWriter<'a, REG, Gcen>; +impl<'a, REG> GcenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gcen::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gcen::Enabled) + } +} +#[doc = "SMBus Alert Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Saen { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Saen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SAEN` reader - SMBus Alert Enable"] +pub type SaenR = crate::BitReader; +impl SaenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Saen { + match self.bits { + false => Saen::Disable, + true => Saen::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Saen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Saen::Enable + } +} +#[doc = "Field `SAEN` writer - SMBus Alert Enable"] +pub type SaenW<'a, REG> = crate::BitWriter<'a, REG, Saen>; +impl<'a, REG> SaenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Saen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Saen::Enable) + } +} +#[doc = "Transmit Flag Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txcfg { + #[doc = "0: MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"] + AssertsDuringSlaveTransmitTransferWhenTxDataEmpty = 0, + #[doc = "1: MSR\\[TDF\\] is set whenever STDR is empty"] + AssertsWhenTxDataEmpty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txcfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXCFG` reader - Transmit Flag Configuration"] +pub type TxcfgR = crate::BitReader; +impl TxcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txcfg { + match self.bits { + false => Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty, + true => Txcfg::AssertsWhenTxDataEmpty, + } + } + #[doc = "MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"] + #[inline(always)] + pub fn is_asserts_during_slave_transmit_transfer_when_tx_data_empty(&self) -> bool { + *self == Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty + } + #[doc = "MSR\\[TDF\\] is set whenever STDR is empty"] + #[inline(always)] + pub fn is_asserts_when_tx_data_empty(&self) -> bool { + *self == Txcfg::AssertsWhenTxDataEmpty + } +} +#[doc = "Field `TXCFG` writer - Transmit Flag Configuration"] +pub type TxcfgW<'a, REG> = crate::BitWriter<'a, REG, Txcfg>; +impl<'a, REG> TxcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"] + #[inline(always)] + pub fn asserts_during_slave_transmit_transfer_when_tx_data_empty( + self, + ) -> &'a mut crate::W { + self.variant(Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty) + } + #[doc = "MSR\\[TDF\\] is set whenever STDR is empty"] + #[inline(always)] + pub fn asserts_when_tx_data_empty(self) -> &'a mut crate::W { + self.variant(Txcfg::AssertsWhenTxDataEmpty) + } +} +#[doc = "Receive Data Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxcfg { + #[doc = "0: Return received data, clear MSR\\[RDF\\]"] + ReturnsReceivedDataAndClearsRxDataFlag = 0, + #[doc = "1: Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"] + WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxcfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXCFG` reader - Receive Data Configuration"] +pub type RxcfgR = crate::BitReader; +impl RxcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxcfg { + match self.bits { + false => Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag, + true => Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag, + } + } + #[doc = "Return received data, clear MSR\\[RDF\\]"] + #[inline(always)] + pub fn is_returns_received_data_and_clears_rx_data_flag(&self) -> bool { + *self == Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag + } + #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"] + #[inline(always)] + pub fn is_when_address_valid_flag_set_returns_address_status_and_clears_address_valid_flag( + &self, + ) -> bool { + *self == Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag + } +} +#[doc = "Field `RXCFG` writer - Receive Data Configuration"] +pub type RxcfgW<'a, REG> = crate::BitWriter<'a, REG, Rxcfg>; +impl<'a, REG> RxcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Return received data, clear MSR\\[RDF\\]"] + #[inline(always)] + pub fn returns_received_data_and_clears_rx_data_flag(self) -> &'a mut crate::W { + self.variant(Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag) + } + #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"] + #[inline(always)] + pub fn when_address_valid_flag_set_returns_address_status_and_clears_address_valid_flag( + self, + ) -> &'a mut crate::W { + self.variant(Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag) + } +} +#[doc = "Ignore NACK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ignack { + #[doc = "0: End transfer on NACK"] + EndsTransferOnNack = 0, + #[doc = "1: Do not end transfer on NACK"] + DoesNotEndTransferOnNack = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ignack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IGNACK` reader - Ignore NACK"] +pub type IgnackR = crate::BitReader; +impl IgnackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ignack { + match self.bits { + false => Ignack::EndsTransferOnNack, + true => Ignack::DoesNotEndTransferOnNack, + } + } + #[doc = "End transfer on NACK"] + #[inline(always)] + pub fn is_ends_transfer_on_nack(&self) -> bool { + *self == Ignack::EndsTransferOnNack + } + #[doc = "Do not end transfer on NACK"] + #[inline(always)] + pub fn is_does_not_end_transfer_on_nack(&self) -> bool { + *self == Ignack::DoesNotEndTransferOnNack + } +} +#[doc = "Field `IGNACK` writer - Ignore NACK"] +pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG, Ignack>; +impl<'a, REG> IgnackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "End transfer on NACK"] + #[inline(always)] + pub fn ends_transfer_on_nack(self) -> &'a mut crate::W { + self.variant(Ignack::EndsTransferOnNack) + } + #[doc = "Do not end transfer on NACK"] + #[inline(always)] + pub fn does_not_end_transfer_on_nack(self) -> &'a mut crate::W { + self.variant(Ignack::DoesNotEndTransferOnNack) + } +} +#[doc = "HS Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hsmen { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hsmen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HSMEN` reader - HS Mode Enable"] +pub type HsmenR = crate::BitReader; +impl HsmenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hsmen { + match self.bits { + false => Hsmen::Disabled, + true => Hsmen::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Hsmen::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Hsmen::Enabled + } +} +#[doc = "Field `HSMEN` writer - HS Mode Enable"] +pub type HsmenW<'a, REG> = crate::BitWriter<'a, REG, Hsmen>; +impl<'a, REG> HsmenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Hsmen::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Hsmen::Enabled) + } +} +#[doc = "Address Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Addrcfg { + #[doc = "0: Address match 0 (7-bit)"] + AddressMatch0_7Bit = 0, + #[doc = "1: Address match 0 (10-bit)"] + AddressMatch0_10Bit = 1, + #[doc = "2: Address match 0 (7-bit) or address match 1 (7-bit)"] + AddressMatch0_7BitOrAddressMatch1_7Bit = 2, + #[doc = "3: Address match 0 (10-bit) or address match 1 (10-bit)"] + AddressMatch0_10BitOrAddressMatch1_10Bit = 3, + #[doc = "4: Address match 0 (7-bit) or address match 1 (10-bit)"] + AddressMatch0_7BitOrAddressMatch1_10Bit = 4, + #[doc = "5: Address match 0 (10-bit) or address match 1 (7-bit)"] + AddressMatch0_10BitOrAddressMatch1_7Bit = 5, + #[doc = "6: From address match 0 (7-bit) to address match 1 (7-bit)"] + FromAddressMatch0_7BitToAddressMatch1_7Bit = 6, + #[doc = "7: From address match 0 (10-bit) to address match 1 (10-bit)"] + FromAddressMatch0_10BitToAddressMatch1_10Bit = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Addrcfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Addrcfg { + type Ux = u8; +} +impl crate::IsEnum for Addrcfg {} +#[doc = "Field `ADDRCFG` reader - Address Configuration"] +pub type AddrcfgR = crate::FieldReader; +impl AddrcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Addrcfg { + match self.bits { + 0 => Addrcfg::AddressMatch0_7Bit, + 1 => Addrcfg::AddressMatch0_10Bit, + 2 => Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit, + 3 => Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit, + 4 => Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit, + 5 => Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit, + 6 => Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit, + 7 => Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit, + _ => unreachable!(), + } + } + #[doc = "Address match 0 (7-bit)"] + #[inline(always)] + pub fn is_address_match0_7_bit(&self) -> bool { + *self == Addrcfg::AddressMatch0_7Bit + } + #[doc = "Address match 0 (10-bit)"] + #[inline(always)] + pub fn is_address_match0_10_bit(&self) -> bool { + *self == Addrcfg::AddressMatch0_10Bit + } + #[doc = "Address match 0 (7-bit) or address match 1 (7-bit)"] + #[inline(always)] + pub fn is_address_match0_7_bit_or_address_match1_7_bit(&self) -> bool { + *self == Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit + } + #[doc = "Address match 0 (10-bit) or address match 1 (10-bit)"] + #[inline(always)] + pub fn is_address_match0_10_bit_or_address_match1_10_bit(&self) -> bool { + *self == Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit + } + #[doc = "Address match 0 (7-bit) or address match 1 (10-bit)"] + #[inline(always)] + pub fn is_address_match0_7_bit_or_address_match1_10_bit(&self) -> bool { + *self == Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit + } + #[doc = "Address match 0 (10-bit) or address match 1 (7-bit)"] + #[inline(always)] + pub fn is_address_match0_10_bit_or_address_match1_7_bit(&self) -> bool { + *self == Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit + } + #[doc = "From address match 0 (7-bit) to address match 1 (7-bit)"] + #[inline(always)] + pub fn is_from_address_match0_7_bit_to_address_match1_7_bit(&self) -> bool { + *self == Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit + } + #[doc = "From address match 0 (10-bit) to address match 1 (10-bit)"] + #[inline(always)] + pub fn is_from_address_match0_10_bit_to_address_match1_10_bit(&self) -> bool { + *self == Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit + } +} +#[doc = "Field `ADDRCFG` writer - Address Configuration"] +pub type AddrcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Addrcfg, crate::Safe>; +impl<'a, REG> AddrcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Address match 0 (7-bit)"] + #[inline(always)] + pub fn address_match0_7_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::AddressMatch0_7Bit) + } + #[doc = "Address match 0 (10-bit)"] + #[inline(always)] + pub fn address_match0_10_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::AddressMatch0_10Bit) + } + #[doc = "Address match 0 (7-bit) or address match 1 (7-bit)"] + #[inline(always)] + pub fn address_match0_7_bit_or_address_match1_7_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit) + } + #[doc = "Address match 0 (10-bit) or address match 1 (10-bit)"] + #[inline(always)] + pub fn address_match0_10_bit_or_address_match1_10_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit) + } + #[doc = "Address match 0 (7-bit) or address match 1 (10-bit)"] + #[inline(always)] + pub fn address_match0_7_bit_or_address_match1_10_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit) + } + #[doc = "Address match 0 (10-bit) or address match 1 (7-bit)"] + #[inline(always)] + pub fn address_match0_10_bit_or_address_match1_7_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit) + } + #[doc = "From address match 0 (7-bit) to address match 1 (7-bit)"] + #[inline(always)] + pub fn from_address_match0_7_bit_to_address_match1_7_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit) + } + #[doc = "From address match 0 (10-bit) to address match 1 (10-bit)"] + #[inline(always)] + pub fn from_address_match0_10_bit_to_address_match1_10_bit(self) -> &'a mut crate::W { + self.variant(Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit) + } +} +#[doc = "Receive All\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxall { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxall) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXALL` reader - Receive All"] +pub type RxallR = crate::BitReader; +impl RxallR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxall { + match self.bits { + false => Rxall::Disabled, + true => Rxall::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rxall::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rxall::Enabled + } +} +#[doc = "Field `RXALL` writer - Receive All"] +pub type RxallW<'a, REG> = crate::BitWriter<'a, REG, Rxall>; +impl<'a, REG> RxallW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rxall::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rxall::Enabled) + } +} +#[doc = "Repeated Start Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rscfg { + #[doc = "0: Any repeated Start condition following an address match"] + AnyRepeatedStartAfterAddressMatch = 0, + #[doc = "1: Any repeated Start condition"] + AnyRepeatedStart = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rscfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSCFG` reader - Repeated Start Configuration"] +pub type RscfgR = crate::BitReader; +impl RscfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rscfg { + match self.bits { + false => Rscfg::AnyRepeatedStartAfterAddressMatch, + true => Rscfg::AnyRepeatedStart, + } + } + #[doc = "Any repeated Start condition following an address match"] + #[inline(always)] + pub fn is_any_repeated_start_after_address_match(&self) -> bool { + *self == Rscfg::AnyRepeatedStartAfterAddressMatch + } + #[doc = "Any repeated Start condition"] + #[inline(always)] + pub fn is_any_repeated_start(&self) -> bool { + *self == Rscfg::AnyRepeatedStart + } +} +#[doc = "Field `RSCFG` writer - Repeated Start Configuration"] +pub type RscfgW<'a, REG> = crate::BitWriter<'a, REG, Rscfg>; +impl<'a, REG> RscfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Any repeated Start condition following an address match"] + #[inline(always)] + pub fn any_repeated_start_after_address_match(self) -> &'a mut crate::W { + self.variant(Rscfg::AnyRepeatedStartAfterAddressMatch) + } + #[doc = "Any repeated Start condition"] + #[inline(always)] + pub fn any_repeated_start(self) -> &'a mut crate::W { + self.variant(Rscfg::AnyRepeatedStart) + } +} +#[doc = "Stop Detect Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sdcfg { + #[doc = "0: Any Stop condition following an address match"] + AnyStopAfterAddressMatch = 0, + #[doc = "1: Any Stop condition"] + AnyStop = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sdcfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SDCFG` reader - Stop Detect Configuration"] +pub type SdcfgR = crate::BitReader; +impl SdcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sdcfg { + match self.bits { + false => Sdcfg::AnyStopAfterAddressMatch, + true => Sdcfg::AnyStop, + } + } + #[doc = "Any Stop condition following an address match"] + #[inline(always)] + pub fn is_any_stop_after_address_match(&self) -> bool { + *self == Sdcfg::AnyStopAfterAddressMatch + } + #[doc = "Any Stop condition"] + #[inline(always)] + pub fn is_any_stop(&self) -> bool { + *self == Sdcfg::AnyStop + } +} +#[doc = "Field `SDCFG` writer - Stop Detect Configuration"] +pub type SdcfgW<'a, REG> = crate::BitWriter<'a, REG, Sdcfg>; +impl<'a, REG> SdcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Any Stop condition following an address match"] + #[inline(always)] + pub fn any_stop_after_address_match(self) -> &'a mut crate::W { + self.variant(Sdcfg::AnyStopAfterAddressMatch) + } + #[doc = "Any Stop condition"] + #[inline(always)] + pub fn any_stop(self) -> &'a mut crate::W { + self.variant(Sdcfg::AnyStop) + } +} +impl R { + #[doc = "Bit 0 - Address SCL Stall"] + #[inline(always)] + pub fn adrstall(&self) -> AdrstallR { + AdrstallR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX SCL Stall"] + #[inline(always)] + pub fn rxstall(&self) -> RxstallR { + RxstallR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit Data SCL Stall"] + #[inline(always)] + pub fn txdstall(&self) -> TxdstallR { + TxdstallR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ACK SCL Stall"] + #[inline(always)] + pub fn ackstall(&self) -> AckstallR { + AckstallR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive NACK"] + #[inline(always)] + pub fn rxnack(&self) -> RxnackR { + RxnackR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - General Call Enable"] + #[inline(always)] + pub fn gcen(&self) -> GcenR { + GcenR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SMBus Alert Enable"] + #[inline(always)] + pub fn saen(&self) -> SaenR { + SaenR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Transmit Flag Configuration"] + #[inline(always)] + pub fn txcfg(&self) -> TxcfgR { + TxcfgR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Receive Data Configuration"] + #[inline(always)] + pub fn rxcfg(&self) -> RxcfgR { + RxcfgR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Ignore NACK"] + #[inline(always)] + pub fn ignack(&self) -> IgnackR { + IgnackR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - HS Mode Enable"] + #[inline(always)] + pub fn hsmen(&self) -> HsmenR { + HsmenR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 16:18 - Address Configuration"] + #[inline(always)] + pub fn addrcfg(&self) -> AddrcfgR { + AddrcfgR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 24 - Receive All"] + #[inline(always)] + pub fn rxall(&self) -> RxallR { + RxallR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Repeated Start Configuration"] + #[inline(always)] + pub fn rscfg(&self) -> RscfgR { + RscfgR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Stop Detect Configuration"] + #[inline(always)] + pub fn sdcfg(&self) -> SdcfgR { + SdcfgR::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Address SCL Stall"] + #[inline(always)] + pub fn adrstall(&mut self) -> AdrstallW { + AdrstallW::new(self, 0) + } + #[doc = "Bit 1 - RX SCL Stall"] + #[inline(always)] + pub fn rxstall(&mut self) -> RxstallW { + RxstallW::new(self, 1) + } + #[doc = "Bit 2 - Transmit Data SCL Stall"] + #[inline(always)] + pub fn txdstall(&mut self) -> TxdstallW { + TxdstallW::new(self, 2) + } + #[doc = "Bit 3 - ACK SCL Stall"] + #[inline(always)] + pub fn ackstall(&mut self) -> AckstallW { + AckstallW::new(self, 3) + } + #[doc = "Bit 4 - Receive NACK"] + #[inline(always)] + pub fn rxnack(&mut self) -> RxnackW { + RxnackW::new(self, 4) + } + #[doc = "Bit 8 - General Call Enable"] + #[inline(always)] + pub fn gcen(&mut self) -> GcenW { + GcenW::new(self, 8) + } + #[doc = "Bit 9 - SMBus Alert Enable"] + #[inline(always)] + pub fn saen(&mut self) -> SaenW { + SaenW::new(self, 9) + } + #[doc = "Bit 10 - Transmit Flag Configuration"] + #[inline(always)] + pub fn txcfg(&mut self) -> TxcfgW { + TxcfgW::new(self, 10) + } + #[doc = "Bit 11 - Receive Data Configuration"] + #[inline(always)] + pub fn rxcfg(&mut self) -> RxcfgW { + RxcfgW::new(self, 11) + } + #[doc = "Bit 12 - Ignore NACK"] + #[inline(always)] + pub fn ignack(&mut self) -> IgnackW { + IgnackW::new(self, 12) + } + #[doc = "Bit 13 - HS Mode Enable"] + #[inline(always)] + pub fn hsmen(&mut self) -> HsmenW { + HsmenW::new(self, 13) + } + #[doc = "Bits 16:18 - Address Configuration"] + #[inline(always)] + pub fn addrcfg(&mut self) -> AddrcfgW { + AddrcfgW::new(self, 16) + } + #[doc = "Bit 24 - Receive All"] + #[inline(always)] + pub fn rxall(&mut self) -> RxallW { + RxallW::new(self, 24) + } + #[doc = "Bit 25 - Repeated Start Configuration"] + #[inline(always)] + pub fn rscfg(&mut self) -> RscfgW { + RscfgW::new(self, 25) + } + #[doc = "Bit 26 - Stop Detect Configuration"] + #[inline(always)] + pub fn sdcfg(&mut self) -> SdcfgW { + SdcfgW::new(self, 26) + } +} +#[doc = "Target Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scfgr1Spec; +impl crate::RegisterSpec for Scfgr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scfgr1::R`](R) reader structure"] +impl crate::Readable for Scfgr1Spec {} +#[doc = "`write(|w| ..)` method takes [`scfgr1::W`](W) writer structure"] +impl crate::Writable for Scfgr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCFGR1 to value 0"] +impl crate::Resettable for Scfgr1Spec {} diff --git a/mcxa276-pac/src/lpi2c0/scfgr2.rs b/mcxa276-pac/src/lpi2c0/scfgr2.rs new file mode 100644 index 000000000..2dbc8ab11 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/scfgr2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `SCFGR2` reader"] +pub type R = crate::R; +#[doc = "Register `SCFGR2` writer"] +pub type W = crate::W; +#[doc = "Field `CLKHOLD` reader - Clock Hold Time"] +pub type ClkholdR = crate::FieldReader; +#[doc = "Field `CLKHOLD` writer - Clock Hold Time"] +pub type ClkholdW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DATAVD` reader - Data Valid Delay"] +pub type DatavdR = crate::FieldReader; +#[doc = "Field `DATAVD` writer - Data Valid Delay"] +pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FILTSCL` reader - Glitch Filter SCL"] +pub type FiltsclR = crate::FieldReader; +#[doc = "Field `FILTSCL` writer - Glitch Filter SCL"] +pub type FiltsclW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `FILTSDA` reader - Glitch Filter SDA"] +pub type FiltsdaR = crate::FieldReader; +#[doc = "Field `FILTSDA` writer - Glitch Filter SDA"] +pub type FiltsdaW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Clock Hold Time"] + #[inline(always)] + pub fn clkhold(&self) -> ClkholdR { + ClkholdR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:13 - Data Valid Delay"] + #[inline(always)] + pub fn datavd(&self) -> DatavdR { + DatavdR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:19 - Glitch Filter SCL"] + #[inline(always)] + pub fn filtscl(&self) -> FiltsclR { + FiltsclR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Glitch Filter SDA"] + #[inline(always)] + pub fn filtsda(&self) -> FiltsdaR { + FiltsdaR::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Clock Hold Time"] + #[inline(always)] + pub fn clkhold(&mut self) -> ClkholdW { + ClkholdW::new(self, 0) + } + #[doc = "Bits 8:13 - Data Valid Delay"] + #[inline(always)] + pub fn datavd(&mut self) -> DatavdW { + DatavdW::new(self, 8) + } + #[doc = "Bits 16:19 - Glitch Filter SCL"] + #[inline(always)] + pub fn filtscl(&mut self) -> FiltsclW { + FiltsclW::new(self, 16) + } + #[doc = "Bits 24:27 - Glitch Filter SDA"] + #[inline(always)] + pub fn filtsda(&mut self) -> FiltsdaW { + FiltsdaW::new(self, 24) + } +} +#[doc = "Target Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scfgr2Spec; +impl crate::RegisterSpec for Scfgr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scfgr2::R`](R) reader structure"] +impl crate::Readable for Scfgr2Spec {} +#[doc = "`write(|w| ..)` method takes [`scfgr2::W`](W) writer structure"] +impl crate::Writable for Scfgr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCFGR2 to value 0"] +impl crate::Resettable for Scfgr2Spec {} diff --git a/mcxa276-pac/src/lpi2c0/scr.rs b/mcxa276-pac/src/lpi2c0/scr.rs new file mode 100644 index 000000000..0af92e8e2 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/scr.rs @@ -0,0 +1,399 @@ +#[doc = "Register `SCR` reader"] +pub type R = crate::R; +#[doc = "Register `SCR` writer"] +pub type W = crate::W; +#[doc = "Target Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sen { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEN` reader - Target Enable"] +pub type SenR = crate::BitReader; +impl SenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sen { + match self.bits { + false => Sen::Disabled, + true => Sen::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sen::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sen::Enabled + } +} +#[doc = "Field `SEN` writer - Target Enable"] +pub type SenW<'a, REG> = crate::BitWriter<'a, REG, Sen>; +impl<'a, REG> SenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sen::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sen::Enabled) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rst { + #[doc = "0: Not reset"] + NotReset = 0, + #[doc = "1: Reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RST` reader - Software Reset"] +pub type RstR = crate::BitReader; +impl RstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rst { + match self.bits { + false => Rst::NotReset, + true => Rst::Reset, + } + } + #[doc = "Not reset"] + #[inline(always)] + pub fn is_not_reset(&self) -> bool { + *self == Rst::NotReset + } + #[doc = "Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Rst::Reset + } +} +#[doc = "Field `RST` writer - Software Reset"] +pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; +impl<'a, REG> RstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not reset"] + #[inline(always)] + pub fn not_reset(self) -> &'a mut crate::W { + self.variant(Rst::NotReset) + } + #[doc = "Reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Rst::Reset) + } +} +#[doc = "Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Filten { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Filten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILTEN` reader - Filter Enable"] +pub type FiltenR = crate::BitReader; +impl FiltenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filten { + match self.bits { + false => Filten::Disable, + true => Filten::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Filten::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Filten::Enable + } +} +#[doc = "Field `FILTEN` writer - Filter Enable"] +pub type FiltenW<'a, REG> = crate::BitWriter<'a, REG, Filten>; +impl<'a, REG> FiltenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Filten::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Filten::Enable) + } +} +#[doc = "Filter Doze Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Filtdz { + #[doc = "0: Enable"] + FilterEnabled = 0, + #[doc = "1: Disable"] + FilterDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Filtdz) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILTDZ` reader - Filter Doze Enable"] +pub type FiltdzR = crate::BitReader; +impl FiltdzR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filtdz { + match self.bits { + false => Filtdz::FilterEnabled, + true => Filtdz::FilterDisabled, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_filter_enabled(&self) -> bool { + *self == Filtdz::FilterEnabled + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_filter_disabled(&self) -> bool { + *self == Filtdz::FilterDisabled + } +} +#[doc = "Field `FILTDZ` writer - Filter Doze Enable"] +pub type FiltdzW<'a, REG> = crate::BitWriter<'a, REG, Filtdz>; +impl<'a, REG> FiltdzW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn filter_enabled(self) -> &'a mut crate::W { + self.variant(Filtdz::FilterEnabled) + } + #[doc = "Disable"] + #[inline(always)] + pub fn filter_disabled(self) -> &'a mut crate::W { + self.variant(Filtdz::FilterDisabled) + } +} +#[doc = "Reset Transmit FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rtf { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: STDR is now empty"] + NowEmpty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rtf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RTF` reader - Reset Transmit FIFO"] +pub type RtfR = crate::BitReader; +impl RtfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rtf { + match self.bits { + false => Rtf::NoEffect, + true => Rtf::NowEmpty, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rtf::NoEffect + } + #[doc = "STDR is now empty"] + #[inline(always)] + pub fn is_now_empty(&self) -> bool { + *self == Rtf::NowEmpty + } +} +#[doc = "Field `RTF` writer - Reset Transmit FIFO"] +pub type RtfW<'a, REG> = crate::BitWriter<'a, REG, Rtf>; +impl<'a, REG> RtfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rtf::NoEffect) + } + #[doc = "STDR is now empty"] + #[inline(always)] + pub fn now_empty(self) -> &'a mut crate::W { + self.variant(Rtf::NowEmpty) + } +} +#[doc = "Reset Receive FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rrf { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: SRDR is now empty"] + NowEmpty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rrf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRF` reader - Reset Receive FIFO"] +pub type RrfR = crate::BitReader; +impl RrfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rrf { + match self.bits { + false => Rrf::NoEffect, + true => Rrf::NowEmpty, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rrf::NoEffect + } + #[doc = "SRDR is now empty"] + #[inline(always)] + pub fn is_now_empty(&self) -> bool { + *self == Rrf::NowEmpty + } +} +#[doc = "Field `RRF` writer - Reset Receive FIFO"] +pub type RrfW<'a, REG> = crate::BitWriter<'a, REG, Rrf>; +impl<'a, REG> RrfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rrf::NoEffect) + } + #[doc = "SRDR is now empty"] + #[inline(always)] + pub fn now_empty(self) -> &'a mut crate::W { + self.variant(Rrf::NowEmpty) + } +} +impl R { + #[doc = "Bit 0 - Target Enable"] + #[inline(always)] + pub fn sen(&self) -> SenR { + SenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&self) -> RstR { + RstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Filter Enable"] + #[inline(always)] + pub fn filten(&self) -> FiltenR { + FiltenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Filter Doze Enable"] + #[inline(always)] + pub fn filtdz(&self) -> FiltdzR { + FiltdzR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Reset Transmit FIFO"] + #[inline(always)] + pub fn rtf(&self) -> RtfR { + RtfR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reset Receive FIFO"] + #[inline(always)] + pub fn rrf(&self) -> RrfR { + RrfR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Target Enable"] + #[inline(always)] + pub fn sen(&mut self) -> SenW { + SenW::new(self, 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RstW { + RstW::new(self, 1) + } + #[doc = "Bit 4 - Filter Enable"] + #[inline(always)] + pub fn filten(&mut self) -> FiltenW { + FiltenW::new(self, 4) + } + #[doc = "Bit 5 - Filter Doze Enable"] + #[inline(always)] + pub fn filtdz(&mut self) -> FiltdzW { + FiltdzW::new(self, 5) + } + #[doc = "Bit 8 - Reset Transmit FIFO"] + #[inline(always)] + pub fn rtf(&mut self) -> RtfW { + RtfW::new(self, 8) + } + #[doc = "Bit 9 - Reset Receive FIFO"] + #[inline(always)] + pub fn rrf(&mut self) -> RrfW { + RrfW::new(self, 9) + } +} +#[doc = "Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScrSpec; +impl crate::RegisterSpec for ScrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr::R`](R) reader structure"] +impl crate::Readable for ScrSpec {} +#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] +impl crate::Writable for ScrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for ScrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/sder.rs b/mcxa276-pac/src/lpi2c0/sder.rs new file mode 100644 index 000000000..0be9d6102 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/sder.rs @@ -0,0 +1,336 @@ +#[doc = "Register `SDER` reader"] +pub type R = crate::R; +#[doc = "Register `SDER` writer"] +pub type W = crate::W; +#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdde { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"] +pub type TddeR = crate::BitReader; +impl TddeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdde { + match self.bits { + false => Tdde::Disabled, + true => Tdde::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tdde::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tdde::Enabled + } +} +#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"] +pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>; +impl<'a, REG> TddeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tdde::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tdde::Enabled) + } +} +#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdde { + #[doc = "0: Disable DMA request"] + Disabled = 0, + #[doc = "1: Enable DMA request"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDDE` reader - Receive Data DMA Enable"] +pub type RddeR = crate::BitReader; +impl RddeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdde { + match self.bits { + false => Rdde::Disabled, + true => Rdde::Enabled, + } + } + #[doc = "Disable DMA request"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdde::Disabled + } + #[doc = "Enable DMA request"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdde::Enabled + } +} +#[doc = "Field `RDDE` writer - Receive Data DMA Enable"] +pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>; +impl<'a, REG> RddeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable DMA request"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rdde::Disabled) + } + #[doc = "Enable DMA request"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rdde::Enabled) + } +} +#[doc = "Address Valid DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Avde { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Avde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AVDE` reader - Address Valid DMA Enable"] +pub type AvdeR = crate::BitReader; +impl AvdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Avde { + match self.bits { + false => Avde::Disabled, + true => Avde::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Avde::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Avde::Enabled + } +} +#[doc = "Field `AVDE` writer - Address Valid DMA Enable"] +pub type AvdeW<'a, REG> = crate::BitWriter<'a, REG, Avde>; +impl<'a, REG> AvdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Avde::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Avde::Enabled) + } +} +#[doc = "Repeated Start DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rsde { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rsde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSDE` reader - Repeated Start DMA Enable"] +pub type RsdeR = crate::BitReader; +impl RsdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rsde { + match self.bits { + false => Rsde::Disabled, + true => Rsde::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rsde::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rsde::Enabled + } +} +#[doc = "Field `RSDE` writer - Repeated Start DMA Enable"] +pub type RsdeW<'a, REG> = crate::BitWriter<'a, REG, Rsde>; +impl<'a, REG> RsdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rsde::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rsde::Enabled) + } +} +#[doc = "Stop Detect DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sdde { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sdde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SDDE` reader - Stop Detect DMA Enable"] +pub type SddeR = crate::BitReader; +impl SddeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sdde { + match self.bits { + false => Sdde::Disabled, + true => Sdde::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sdde::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sdde::Enabled + } +} +#[doc = "Field `SDDE` writer - Stop Detect DMA Enable"] +pub type SddeW<'a, REG> = crate::BitWriter<'a, REG, Sdde>; +impl<'a, REG> SddeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sdde::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sdde::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Transmit Data DMA Enable"] + #[inline(always)] + pub fn tdde(&self) -> TddeR { + TddeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data DMA Enable"] + #[inline(always)] + pub fn rdde(&self) -> RddeR { + RddeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Address Valid DMA Enable"] + #[inline(always)] + pub fn avde(&self) -> AvdeR { + AvdeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Repeated Start DMA Enable"] + #[inline(always)] + pub fn rsde(&self) -> RsdeR { + RsdeR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Detect DMA Enable"] + #[inline(always)] + pub fn sdde(&self) -> SddeR { + SddeR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Data DMA Enable"] + #[inline(always)] + pub fn tdde(&mut self) -> TddeW { + TddeW::new(self, 0) + } + #[doc = "Bit 1 - Receive Data DMA Enable"] + #[inline(always)] + pub fn rdde(&mut self) -> RddeW { + RddeW::new(self, 1) + } + #[doc = "Bit 2 - Address Valid DMA Enable"] + #[inline(always)] + pub fn avde(&mut self) -> AvdeW { + AvdeW::new(self, 2) + } + #[doc = "Bit 8 - Repeated Start DMA Enable"] + #[inline(always)] + pub fn rsde(&mut self) -> RsdeW { + RsdeW::new(self, 8) + } + #[doc = "Bit 9 - Stop Detect DMA Enable"] + #[inline(always)] + pub fn sdde(&mut self) -> SddeW { + SddeW::new(self, 9) + } +} +#[doc = "Target DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sder::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sder::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SderSpec; +impl crate::RegisterSpec for SderSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sder::R`](R) reader structure"] +impl crate::Readable for SderSpec {} +#[doc = "`write(|w| ..)` method takes [`sder::W`](W) writer structure"] +impl crate::Writable for SderSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SDER to value 0"] +impl crate::Resettable for SderSpec {} diff --git a/mcxa276-pac/src/lpi2c0/sier.rs b/mcxa276-pac/src/lpi2c0/sier.rs new file mode 100644 index 000000000..3e80516cf --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/sier.rs @@ -0,0 +1,777 @@ +#[doc = "Register `SIER` reader"] +pub type R = crate::R; +#[doc = "Register `SIER` writer"] +pub type W = crate::W; +#[doc = "Transmit Data Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDIE` reader - Transmit Data Interrupt Enable"] +pub type TdieR = crate::BitReader; +impl TdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdie { + match self.bits { + false => Tdie::Disabled, + true => Tdie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tdie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tdie::Enabled + } +} +#[doc = "Field `TDIE` writer - Transmit Data Interrupt Enable"] +pub type TdieW<'a, REG> = crate::BitWriter<'a, REG, Tdie>; +impl<'a, REG> TdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tdie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tdie::Enabled) + } +} +#[doc = "Receive Data Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDIE` reader - Receive Data Interrupt Enable"] +pub type RdieR = crate::BitReader; +impl RdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdie { + match self.bits { + false => Rdie::Disabled, + true => Rdie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdie::Enabled + } +} +#[doc = "Field `RDIE` writer - Receive Data Interrupt Enable"] +pub type RdieW<'a, REG> = crate::BitWriter<'a, REG, Rdie>; +impl<'a, REG> RdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rdie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rdie::Enabled) + } +} +#[doc = "Address Valid Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Avie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Avie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AVIE` reader - Address Valid Interrupt Enable"] +pub type AvieR = crate::BitReader; +impl AvieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Avie { + match self.bits { + false => Avie::Disabled, + true => Avie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Avie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Avie::Enabled + } +} +#[doc = "Field `AVIE` writer - Address Valid Interrupt Enable"] +pub type AvieW<'a, REG> = crate::BitWriter<'a, REG, Avie>; +impl<'a, REG> AvieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Avie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Avie::Enabled) + } +} +#[doc = "Transmit ACK Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Taie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Taie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TAIE` reader - Transmit ACK Interrupt Enable"] +pub type TaieR = crate::BitReader; +impl TaieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Taie { + match self.bits { + false => Taie::Disabled, + true => Taie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Taie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Taie::Enabled + } +} +#[doc = "Field `TAIE` writer - Transmit ACK Interrupt Enable"] +pub type TaieW<'a, REG> = crate::BitWriter<'a, REG, Taie>; +impl<'a, REG> TaieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Taie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Taie::Enabled) + } +} +#[doc = "Repeated Start Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rsie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rsie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSIE` reader - Repeated Start Interrupt Enable"] +pub type RsieR = crate::BitReader; +impl RsieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rsie { + match self.bits { + false => Rsie::Disabled, + true => Rsie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rsie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rsie::Enabled + } +} +#[doc = "Field `RSIE` writer - Repeated Start Interrupt Enable"] +pub type RsieW<'a, REG> = crate::BitWriter<'a, REG, Rsie>; +impl<'a, REG> RsieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rsie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rsie::Enabled) + } +} +#[doc = "Stop Detect Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sdie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SDIE` reader - Stop Detect Interrupt Enable"] +pub type SdieR = crate::BitReader; +impl SdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sdie { + match self.bits { + false => Sdie::Disabled, + true => Sdie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sdie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sdie::Enabled + } +} +#[doc = "Field `SDIE` writer - Stop Detect Interrupt Enable"] +pub type SdieW<'a, REG> = crate::BitWriter<'a, REG, Sdie>; +impl<'a, REG> SdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sdie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sdie::Enabled) + } +} +#[doc = "Bit Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Beie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Beie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BEIE` reader - Bit Error Interrupt Enable"] +pub type BeieR = crate::BitReader; +impl BeieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Beie { + match self.bits { + false => Beie::Disabled, + true => Beie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Beie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Beie::Enabled + } +} +#[doc = "Field `BEIE` writer - Bit Error Interrupt Enable"] +pub type BeieW<'a, REG> = crate::BitWriter<'a, REG, Beie>; +impl<'a, REG> BeieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Beie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Beie::Enabled) + } +} +#[doc = "FIFO Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Feie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Feie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FEIE` reader - FIFO Error Interrupt Enable"] +pub type FeieR = crate::BitReader; +impl FeieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Feie { + match self.bits { + false => Feie::Disabled, + true => Feie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Feie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Feie::Enabled + } +} +#[doc = "Field `FEIE` writer - FIFO Error Interrupt Enable"] +pub type FeieW<'a, REG> = crate::BitWriter<'a, REG, Feie>; +impl<'a, REG> FeieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Feie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Feie::Enabled) + } +} +#[doc = "Address Match 0 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Am0ie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Am0ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AM0IE` reader - Address Match 0 Interrupt Enable"] +pub type Am0ieR = crate::BitReader; +impl Am0ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Am0ie { + match self.bits { + false => Am0ie::Disabled, + true => Am0ie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Am0ie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Am0ie::Enabled + } +} +#[doc = "Field `AM0IE` writer - Address Match 0 Interrupt Enable"] +pub type Am0ieW<'a, REG> = crate::BitWriter<'a, REG, Am0ie>; +impl<'a, REG> Am0ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Am0ie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Am0ie::Enabled) + } +} +#[doc = "Address Match 1 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Am1ie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Am1ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AM1IE` reader - Address Match 1 Interrupt Enable"] +pub type Am1ieR = crate::BitReader; +impl Am1ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Am1ie { + match self.bits { + false => Am1ie::Disabled, + true => Am1ie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Am1ie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Am1ie::Enabled + } +} +#[doc = "Field `AM1IE` writer - Address Match 1 Interrupt Enable"] +pub type Am1ieW<'a, REG> = crate::BitWriter<'a, REG, Am1ie>; +impl<'a, REG> Am1ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Am1ie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Am1ie::Enabled) + } +} +#[doc = "General Call Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gcie { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gcie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GCIE` reader - General Call Interrupt Enable"] +pub type GcieR = crate::BitReader; +impl GcieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gcie { + match self.bits { + false => Gcie::Disabled, + true => Gcie::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gcie::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gcie::Enabled + } +} +#[doc = "Field `GCIE` writer - General Call Interrupt Enable"] +pub type GcieW<'a, REG> = crate::BitWriter<'a, REG, Gcie>; +impl<'a, REG> GcieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gcie::Disabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gcie::Enabled) + } +} +#[doc = "SMBus Alert Response Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sarie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sarie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SARIE` reader - SMBus Alert Response Interrupt Enable"] +pub type SarieR = crate::BitReader; +impl SarieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sarie { + match self.bits { + false => Sarie::Disabled, + true => Sarie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sarie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sarie::Enabled + } +} +#[doc = "Field `SARIE` writer - SMBus Alert Response Interrupt Enable"] +pub type SarieW<'a, REG> = crate::BitWriter<'a, REG, Sarie>; +impl<'a, REG> SarieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sarie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sarie::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Transmit Data Interrupt Enable"] + #[inline(always)] + pub fn tdie(&self) -> TdieR { + TdieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data Interrupt Enable"] + #[inline(always)] + pub fn rdie(&self) -> RdieR { + RdieR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Address Valid Interrupt Enable"] + #[inline(always)] + pub fn avie(&self) -> AvieR { + AvieR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit ACK Interrupt Enable"] + #[inline(always)] + pub fn taie(&self) -> TaieR { + TaieR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Repeated Start Interrupt Enable"] + #[inline(always)] + pub fn rsie(&self) -> RsieR { + RsieR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Detect Interrupt Enable"] + #[inline(always)] + pub fn sdie(&self) -> SdieR { + SdieR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Bit Error Interrupt Enable"] + #[inline(always)] + pub fn beie(&self) -> BeieR { + BeieR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - FIFO Error Interrupt Enable"] + #[inline(always)] + pub fn feie(&self) -> FeieR { + FeieR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Address Match 0 Interrupt Enable"] + #[inline(always)] + pub fn am0ie(&self) -> Am0ieR { + Am0ieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Address Match 1 Interrupt Enable"] + #[inline(always)] + pub fn am1ie(&self) -> Am1ieR { + Am1ieR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - General Call Interrupt Enable"] + #[inline(always)] + pub fn gcie(&self) -> GcieR { + GcieR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - SMBus Alert Response Interrupt Enable"] + #[inline(always)] + pub fn sarie(&self) -> SarieR { + SarieR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Data Interrupt Enable"] + #[inline(always)] + pub fn tdie(&mut self) -> TdieW { + TdieW::new(self, 0) + } + #[doc = "Bit 1 - Receive Data Interrupt Enable"] + #[inline(always)] + pub fn rdie(&mut self) -> RdieW { + RdieW::new(self, 1) + } + #[doc = "Bit 2 - Address Valid Interrupt Enable"] + #[inline(always)] + pub fn avie(&mut self) -> AvieW { + AvieW::new(self, 2) + } + #[doc = "Bit 3 - Transmit ACK Interrupt Enable"] + #[inline(always)] + pub fn taie(&mut self) -> TaieW { + TaieW::new(self, 3) + } + #[doc = "Bit 8 - Repeated Start Interrupt Enable"] + #[inline(always)] + pub fn rsie(&mut self) -> RsieW { + RsieW::new(self, 8) + } + #[doc = "Bit 9 - Stop Detect Interrupt Enable"] + #[inline(always)] + pub fn sdie(&mut self) -> SdieW { + SdieW::new(self, 9) + } + #[doc = "Bit 10 - Bit Error Interrupt Enable"] + #[inline(always)] + pub fn beie(&mut self) -> BeieW { + BeieW::new(self, 10) + } + #[doc = "Bit 11 - FIFO Error Interrupt Enable"] + #[inline(always)] + pub fn feie(&mut self) -> FeieW { + FeieW::new(self, 11) + } + #[doc = "Bit 12 - Address Match 0 Interrupt Enable"] + #[inline(always)] + pub fn am0ie(&mut self) -> Am0ieW { + Am0ieW::new(self, 12) + } + #[doc = "Bit 13 - Address Match 1 Interrupt Enable"] + #[inline(always)] + pub fn am1ie(&mut self) -> Am1ieW { + Am1ieW::new(self, 13) + } + #[doc = "Bit 14 - General Call Interrupt Enable"] + #[inline(always)] + pub fn gcie(&mut self) -> GcieW { + GcieW::new(self, 14) + } + #[doc = "Bit 15 - SMBus Alert Response Interrupt Enable"] + #[inline(always)] + pub fn sarie(&mut self) -> SarieW { + SarieW::new(self, 15) + } +} +#[doc = "Target Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SierSpec; +impl crate::RegisterSpec for SierSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sier::R`](R) reader structure"] +impl crate::Readable for SierSpec {} +#[doc = "`write(|w| ..)` method takes [`sier::W`](W) writer structure"] +impl crate::Writable for SierSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SIER to value 0"] +impl crate::Resettable for SierSpec {} diff --git a/mcxa276-pac/src/lpi2c0/srdr.rs b/mcxa276-pac/src/lpi2c0/srdr.rs new file mode 100644 index 000000000..0f4803b5d --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/srdr.rs @@ -0,0 +1,111 @@ +#[doc = "Register `SRDR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Received Data"] +pub type DataR = crate::FieldReader; +#[doc = "Field `RADDR` reader - Received Address"] +pub type RaddrR = crate::FieldReader; +#[doc = "Receive Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempty { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPTY` reader - Receive Empty"] +pub type RxemptyR = crate::BitReader; +impl RxemptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempty { + match self.bits { + false => Rxempty::NotEmpty, + true => Rxempty::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempty::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempty::Empty + } +} +#[doc = "Start of Frame\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sof { + #[doc = "0: Not first"] + NotFirstDataWord = 0, + #[doc = "1: First"] + FirstDataWord = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOF` reader - Start of Frame"] +pub type SofR = crate::BitReader; +impl SofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sof { + match self.bits { + false => Sof::NotFirstDataWord, + true => Sof::FirstDataWord, + } + } + #[doc = "Not first"] + #[inline(always)] + pub fn is_not_first_data_word(&self) -> bool { + *self == Sof::NotFirstDataWord + } + #[doc = "First"] + #[inline(always)] + pub fn is_first_data_word(&self) -> bool { + *self == Sof::FirstDataWord + } +} +impl R { + #[doc = "Bits 0:7 - Received Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Received Address"] + #[inline(always)] + pub fn raddr(&self) -> RaddrR { + RaddrR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 14 - Receive Empty"] + #[inline(always)] + pub fn rxempty(&self) -> RxemptyR { + RxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Start of Frame"] + #[inline(always)] + pub fn sof(&self) -> SofR { + SofR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Target Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`srdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrdrSpec; +impl crate::RegisterSpec for SrdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`srdr::R`](R) reader structure"] +impl crate::Readable for SrdrSpec {} +#[doc = "`reset()` method sets SRDR to value 0x4000"] +impl crate::Resettable for SrdrSpec { + const RESET_VALUE: u32 = 0x4000; +} diff --git a/mcxa276-pac/src/lpi2c0/srdror.rs b/mcxa276-pac/src/lpi2c0/srdror.rs new file mode 100644 index 000000000..cb0b415c3 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/srdror.rs @@ -0,0 +1,111 @@ +#[doc = "Register `SRDROR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Receive Data"] +pub type DataR = crate::FieldReader; +#[doc = "Field `RADDR` reader - Received Address"] +pub type RaddrR = crate::FieldReader; +#[doc = "Receive Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempty { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPTY` reader - Receive Empty"] +pub type RxemptyR = crate::BitReader; +impl RxemptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempty { + match self.bits { + false => Rxempty::NotEmpty, + true => Rxempty::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempty::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempty::Empty + } +} +#[doc = "Start of Frame\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sof { + #[doc = "0: Not the first"] + NotFirstDataWord = 0, + #[doc = "1: First"] + FirstDataWord = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOF` reader - Start of Frame"] +pub type SofR = crate::BitReader; +impl SofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sof { + match self.bits { + false => Sof::NotFirstDataWord, + true => Sof::FirstDataWord, + } + } + #[doc = "Not the first"] + #[inline(always)] + pub fn is_not_first_data_word(&self) -> bool { + *self == Sof::NotFirstDataWord + } + #[doc = "First"] + #[inline(always)] + pub fn is_first_data_word(&self) -> bool { + *self == Sof::FirstDataWord + } +} +impl R { + #[doc = "Bits 0:7 - Receive Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Received Address"] + #[inline(always)] + pub fn raddr(&self) -> RaddrR { + RaddrR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 14 - Receive Empty"] + #[inline(always)] + pub fn rxempty(&self) -> RxemptyR { + RxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Start of Frame"] + #[inline(always)] + pub fn sof(&self) -> SofR { + SofR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Target Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`srdror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrdrorSpec; +impl crate::RegisterSpec for SrdrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`srdror::R`](R) reader structure"] +impl crate::Readable for SrdrorSpec {} +#[doc = "`reset()` method sets SRDROR to value 0x4000"] +impl crate::Resettable for SrdrorSpec { + const RESET_VALUE: u32 = 0x4000; +} diff --git a/mcxa276-pac/src/lpi2c0/ssr.rs b/mcxa276-pac/src/lpi2c0/ssr.rs new file mode 100644 index 000000000..a4c0b8b47 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/ssr.rs @@ -0,0 +1,684 @@ +#[doc = "Register `SSR` reader"] +pub type R = crate::R; +#[doc = "Register `SSR` writer"] +pub type W = crate::W; +#[doc = "Transmit Data Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdf { + #[doc = "0: Transmit data not requested"] + NoFlag = 0, + #[doc = "1: Transmit data is requested"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDF` reader - Transmit Data Flag"] +pub type TdfR = crate::BitReader; +impl TdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdf { + match self.bits { + false => Tdf::NoFlag, + true => Tdf::Flag, + } + } + #[doc = "Transmit data not requested"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Tdf::NoFlag + } + #[doc = "Transmit data is requested"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Tdf::Flag + } +} +#[doc = "Receive Data Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdf { + #[doc = "0: Not ready"] + NotReady = 0, + #[doc = "1: Ready"] + Ready = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDF` reader - Receive Data Flag"] +pub type RdfR = crate::BitReader; +impl RdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdf { + match self.bits { + false => Rdf::NotReady, + true => Rdf::Ready, + } + } + #[doc = "Not ready"] + #[inline(always)] + pub fn is_not_ready(&self) -> bool { + *self == Rdf::NotReady + } + #[doc = "Ready"] + #[inline(always)] + pub fn is_ready(&self) -> bool { + *self == Rdf::Ready + } +} +#[doc = "Address Valid Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Avf { + #[doc = "0: Not valid"] + NotValid = 0, + #[doc = "1: Valid"] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Avf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AVF` reader - Address Valid Flag"] +pub type AvfR = crate::BitReader; +impl AvfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Avf { + match self.bits { + false => Avf::NotValid, + true => Avf::Valid, + } + } + #[doc = "Not valid"] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Avf::NotValid + } + #[doc = "Valid"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Avf::Valid + } +} +#[doc = "Transmit ACK Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Taf { + #[doc = "0: Not required"] + NotRequired = 0, + #[doc = "1: Required"] + Required = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Taf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TAF` reader - Transmit ACK Flag"] +pub type TafR = crate::BitReader; +impl TafR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Taf { + match self.bits { + false => Taf::NotRequired, + true => Taf::Required, + } + } + #[doc = "Not required"] + #[inline(always)] + pub fn is_not_required(&self) -> bool { + *self == Taf::NotRequired + } + #[doc = "Required"] + #[inline(always)] + pub fn is_required(&self) -> bool { + *self == Taf::Required + } +} +#[doc = "Repeated Start Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rsf { + #[doc = "0: No repeated Start detected"] + IntNo = 0, + #[doc = "1: Repeated Start detected"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rsf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSF` reader - Repeated Start Flag"] +pub type RsfR = crate::BitReader; +impl RsfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rsf { + match self.bits { + false => Rsf::IntNo, + true => Rsf::IntYes, + } + } + #[doc = "No repeated Start detected"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Rsf::IntNo + } + #[doc = "Repeated Start detected"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Rsf::IntYes + } +} +#[doc = "Field `RSF` writer - Repeated Start Flag"] +pub type RsfW<'a, REG> = crate::BitWriter1C<'a, REG, Rsf>; +impl<'a, REG> RsfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No repeated Start detected"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Rsf::IntNo) + } + #[doc = "Repeated Start detected"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Rsf::IntYes) + } +} +#[doc = "Stop Detect Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sdf { + #[doc = "0: No Stop detected"] + IntNo = 0, + #[doc = "1: Stop detected"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SDF` reader - Stop Detect Flag"] +pub type SdfR = crate::BitReader; +impl SdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sdf { + match self.bits { + false => Sdf::IntNo, + true => Sdf::IntYes, + } + } + #[doc = "No Stop detected"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Sdf::IntNo + } + #[doc = "Stop detected"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Sdf::IntYes + } +} +#[doc = "Field `SDF` writer - Stop Detect Flag"] +pub type SdfW<'a, REG> = crate::BitWriter1C<'a, REG, Sdf>; +impl<'a, REG> SdfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No Stop detected"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Sdf::IntNo) + } + #[doc = "Stop detected"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Sdf::IntYes) + } +} +#[doc = "Bit Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bef { + #[doc = "0: No bit error occurred"] + IntNo = 0, + #[doc = "1: Bit error occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bef) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BEF` reader - Bit Error Flag"] +pub type BefR = crate::BitReader; +impl BefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bef { + match self.bits { + false => Bef::IntNo, + true => Bef::IntYes, + } + } + #[doc = "No bit error occurred"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Bef::IntNo + } + #[doc = "Bit error occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Bef::IntYes + } +} +#[doc = "Field `BEF` writer - Bit Error Flag"] +pub type BefW<'a, REG> = crate::BitWriter1C<'a, REG, Bef>; +impl<'a, REG> BefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No bit error occurred"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Bef::IntNo) + } + #[doc = "Bit error occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Bef::IntYes) + } +} +#[doc = "FIFO Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fef { + #[doc = "0: No FIFO error"] + IntNo = 0, + #[doc = "1: FIFO error"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fef) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FEF` reader - FIFO Error Flag"] +pub type FefR = crate::BitReader; +impl FefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fef { + match self.bits { + false => Fef::IntNo, + true => Fef::IntYes, + } + } + #[doc = "No FIFO error"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Fef::IntNo + } + #[doc = "FIFO error"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Fef::IntYes + } +} +#[doc = "Field `FEF` writer - FIFO Error Flag"] +pub type FefW<'a, REG> = crate::BitWriter1C<'a, REG, Fef>; +impl<'a, REG> FefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No FIFO error"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Fef::IntNo) + } + #[doc = "FIFO error"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Fef::IntYes) + } +} +#[doc = "Address Match 0 Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Am0f { + #[doc = "0: ADDR0 matching address not received"] + NoFlag = 0, + #[doc = "1: ADDR0 matching address received"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Am0f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AM0F` reader - Address Match 0 Flag"] +pub type Am0fR = crate::BitReader; +impl Am0fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Am0f { + match self.bits { + false => Am0f::NoFlag, + true => Am0f::Flag, + } + } + #[doc = "ADDR0 matching address not received"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Am0f::NoFlag + } + #[doc = "ADDR0 matching address received"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Am0f::Flag + } +} +#[doc = "Address Match 1 Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Am1f { + #[doc = "0: Matching address not received"] + NoFlag = 0, + #[doc = "1: Matching address received"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Am1f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AM1F` reader - Address Match 1 Flag"] +pub type Am1fR = crate::BitReader; +impl Am1fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Am1f { + match self.bits { + false => Am1f::NoFlag, + true => Am1f::Flag, + } + } + #[doc = "Matching address not received"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Am1f::NoFlag + } + #[doc = "Matching address received"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Am1f::Flag + } +} +#[doc = "General Call Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gcf { + #[doc = "0: General call address disabled or not detected"] + NoFlag = 0, + #[doc = "1: General call address detected"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gcf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GCF` reader - General Call Flag"] +pub type GcfR = crate::BitReader; +impl GcfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gcf { + match self.bits { + false => Gcf::NoFlag, + true => Gcf::Flag, + } + } + #[doc = "General call address disabled or not detected"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Gcf::NoFlag + } + #[doc = "General call address detected"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Gcf::Flag + } +} +#[doc = "SMBus Alert Response Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sarf { + #[doc = "0: Disabled or not detected"] + NoFlag = 0, + #[doc = "1: Enabled and detected"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sarf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SARF` reader - SMBus Alert Response Flag"] +pub type SarfR = crate::BitReader; +impl SarfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sarf { + match self.bits { + false => Sarf::NoFlag, + true => Sarf::Flag, + } + } + #[doc = "Disabled or not detected"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Sarf::NoFlag + } + #[doc = "Enabled and detected"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Sarf::Flag + } +} +#[doc = "Target Busy Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbf { + #[doc = "0: Idle"] + Idle = 0, + #[doc = "1: Busy"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBF` reader - Target Busy Flag"] +pub type SbfR = crate::BitReader; +impl SbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbf { + match self.bits { + false => Sbf::Idle, + true => Sbf::Busy, + } + } + #[doc = "Idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Sbf::Idle + } + #[doc = "Busy"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Sbf::Busy + } +} +#[doc = "Bus Busy Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bbf { + #[doc = "0: Idle"] + Idle = 0, + #[doc = "1: Busy"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BBF` reader - Bus Busy Flag"] +pub type BbfR = crate::BitReader; +impl BbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bbf { + match self.bits { + false => Bbf::Idle, + true => Bbf::Busy, + } + } + #[doc = "Idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Bbf::Idle + } + #[doc = "Busy"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Bbf::Busy + } +} +impl R { + #[doc = "Bit 0 - Transmit Data Flag"] + #[inline(always)] + pub fn tdf(&self) -> TdfR { + TdfR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data Flag"] + #[inline(always)] + pub fn rdf(&self) -> RdfR { + RdfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Address Valid Flag"] + #[inline(always)] + pub fn avf(&self) -> AvfR { + AvfR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit ACK Flag"] + #[inline(always)] + pub fn taf(&self) -> TafR { + TafR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Repeated Start Flag"] + #[inline(always)] + pub fn rsf(&self) -> RsfR { + RsfR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Detect Flag"] + #[inline(always)] + pub fn sdf(&self) -> SdfR { + SdfR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Bit Error Flag"] + #[inline(always)] + pub fn bef(&self) -> BefR { + BefR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - FIFO Error Flag"] + #[inline(always)] + pub fn fef(&self) -> FefR { + FefR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Address Match 0 Flag"] + #[inline(always)] + pub fn am0f(&self) -> Am0fR { + Am0fR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Address Match 1 Flag"] + #[inline(always)] + pub fn am1f(&self) -> Am1fR { + Am1fR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - General Call Flag"] + #[inline(always)] + pub fn gcf(&self) -> GcfR { + GcfR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - SMBus Alert Response Flag"] + #[inline(always)] + pub fn sarf(&self) -> SarfR { + SarfR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 24 - Target Busy Flag"] + #[inline(always)] + pub fn sbf(&self) -> SbfR { + SbfR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Bus Busy Flag"] + #[inline(always)] + pub fn bbf(&self) -> BbfR { + BbfR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Repeated Start Flag"] + #[inline(always)] + pub fn rsf(&mut self) -> RsfW { + RsfW::new(self, 8) + } + #[doc = "Bit 9 - Stop Detect Flag"] + #[inline(always)] + pub fn sdf(&mut self) -> SdfW { + SdfW::new(self, 9) + } + #[doc = "Bit 10 - Bit Error Flag"] + #[inline(always)] + pub fn bef(&mut self) -> BefW { + BefW::new(self, 10) + } + #[doc = "Bit 11 - FIFO Error Flag"] + #[inline(always)] + pub fn fef(&mut self) -> FefW { + FefW::new(self, 11) + } +} +#[doc = "Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SsrSpec; +impl crate::RegisterSpec for SsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssr::R`](R) reader structure"] +impl crate::Readable for SsrSpec {} +#[doc = "`write(|w| ..)` method takes [`ssr::W`](W) writer structure"] +impl crate::Writable for SsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f00; +} +#[doc = "`reset()` method sets SSR to value 0"] +impl crate::Resettable for SsrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/star.rs b/mcxa276-pac/src/lpi2c0/star.rs new file mode 100644 index 000000000..87c4393d9 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/star.rs @@ -0,0 +1,84 @@ +#[doc = "Register `STAR` reader"] +pub type R = crate::R; +#[doc = "Register `STAR` writer"] +pub type W = crate::W; +#[doc = "Transmit NACK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txnack { + #[doc = "0: Transmit ACK"] + TransmitAck = 0, + #[doc = "1: Transmit NACK"] + TransmitNack = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txnack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXNACK` reader - Transmit NACK"] +pub type TxnackR = crate::BitReader; +impl TxnackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txnack { + match self.bits { + false => Txnack::TransmitAck, + true => Txnack::TransmitNack, + } + } + #[doc = "Transmit ACK"] + #[inline(always)] + pub fn is_transmit_ack(&self) -> bool { + *self == Txnack::TransmitAck + } + #[doc = "Transmit NACK"] + #[inline(always)] + pub fn is_transmit_nack(&self) -> bool { + *self == Txnack::TransmitNack + } +} +#[doc = "Field `TXNACK` writer - Transmit NACK"] +pub type TxnackW<'a, REG> = crate::BitWriter<'a, REG, Txnack>; +impl<'a, REG> TxnackW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Transmit ACK"] + #[inline(always)] + pub fn transmit_ack(self) -> &'a mut crate::W { + self.variant(Txnack::TransmitAck) + } + #[doc = "Transmit NACK"] + #[inline(always)] + pub fn transmit_nack(self) -> &'a mut crate::W { + self.variant(Txnack::TransmitNack) + } +} +impl R { + #[doc = "Bit 0 - Transmit NACK"] + #[inline(always)] + pub fn txnack(&self) -> TxnackR { + TxnackR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit NACK"] + #[inline(always)] + pub fn txnack(&mut self) -> TxnackW { + TxnackW::new(self, 0) + } +} +#[doc = "Target Transmit ACK\n\nYou can [`read`](crate::Reg::read) this register and get [`star::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`star::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StarSpec; +impl crate::RegisterSpec for StarSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`star::R`](R) reader structure"] +impl crate::Readable for StarSpec {} +#[doc = "`write(|w| ..)` method takes [`star::W`](W) writer structure"] +impl crate::Writable for StarSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STAR to value 0"] +impl crate::Resettable for StarSpec {} diff --git a/mcxa276-pac/src/lpi2c0/stdr.rs b/mcxa276-pac/src/lpi2c0/stdr.rs new file mode 100644 index 000000000..588a17440 --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/stdr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `STDR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Transmit Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Transmit Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Target Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StdrSpec; +impl crate::RegisterSpec for StdrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`stdr::W`](W) writer structure"] +impl crate::Writable for StdrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STDR to value 0"] +impl crate::Resettable for StdrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/verid.rs b/mcxa276-pac/src/lpi2c0/verid.rs new file mode 100644 index 000000000..53c7bef0d --- /dev/null +++ b/mcxa276-pac/src/lpi2c0/verid.rs @@ -0,0 +1,76 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "2: Controller only, with standard feature set"] + MasterOnly = 2, + #[doc = "3: Controller and target, with standard feature set"] + MasterAndSlave = 3, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Feature::MasterOnly), + 3 => Some(Feature::MasterAndSlave), + _ => None, + } + } + #[doc = "Controller only, with standard feature set"] + #[inline(always)] + pub fn is_master_only(&self) -> bool { + *self == Feature::MasterOnly + } + #[doc = "Controller and target, with standard feature set"] + #[inline(always)] + pub fn is_master_and_slave(&self) -> bool { + *self == Feature::MasterAndSlave + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0103_0003"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0103_0003; +} diff --git a/mcxa276-pac/src/lpspi0.rs b/mcxa276-pac/src/lpspi0.rs new file mode 100644 index 000000000..43c548584 --- /dev/null +++ b/mcxa276-pac/src/lpspi0.rs @@ -0,0 +1,266 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + _reserved2: [u8; 0x08], + cr: Cr, + sr: Sr, + ier: Ier, + der: Der, + cfgr0: Cfgr0, + cfgr1: Cfgr1, + _reserved8: [u8; 0x08], + dmr0: Dmr0, + dmr1: Dmr1, + _reserved10: [u8; 0x08], + ccr: Ccr, + ccr1: Ccr1, + _reserved12: [u8; 0x10], + fcr: Fcr, + fsr: Fsr, + tcr: Tcr, + tdr: Tdr, + _reserved16: [u8; 0x08], + rsr: Rsr, + rdr: Rdr, + rdror: Rdror, + _reserved19: [u8; 0x0380], + tcbr: Tcbr, + tdbr: [Tdbr; 128], + rdbr: [Rdbr; 128], +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x10 - Control"] + #[inline(always)] + pub const fn cr(&self) -> &Cr { + &self.cr + } + #[doc = "0x14 - Status"] + #[inline(always)] + pub const fn sr(&self) -> &Sr { + &self.sr + } + #[doc = "0x18 - Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &Ier { + &self.ier + } + #[doc = "0x1c - DMA Enable"] + #[inline(always)] + pub const fn der(&self) -> &Der { + &self.der + } + #[doc = "0x20 - Configuration 0"] + #[inline(always)] + pub const fn cfgr0(&self) -> &Cfgr0 { + &self.cfgr0 + } + #[doc = "0x24 - Configuration 1"] + #[inline(always)] + pub const fn cfgr1(&self) -> &Cfgr1 { + &self.cfgr1 + } + #[doc = "0x30 - Data Match 0"] + #[inline(always)] + pub const fn dmr0(&self) -> &Dmr0 { + &self.dmr0 + } + #[doc = "0x34 - Data Match 1"] + #[inline(always)] + pub const fn dmr1(&self) -> &Dmr1 { + &self.dmr1 + } + #[doc = "0x40 - Clock Configuration"] + #[inline(always)] + pub const fn ccr(&self) -> &Ccr { + &self.ccr + } + #[doc = "0x44 - Clock Configuration 1"] + #[inline(always)] + pub const fn ccr1(&self) -> &Ccr1 { + &self.ccr1 + } + #[doc = "0x58 - FIFO Control"] + #[inline(always)] + pub const fn fcr(&self) -> &Fcr { + &self.fcr + } + #[doc = "0x5c - FIFO Status"] + #[inline(always)] + pub const fn fsr(&self) -> &Fsr { + &self.fsr + } + #[doc = "0x60 - Transmit Command"] + #[inline(always)] + pub const fn tcr(&self) -> &Tcr { + &self.tcr + } + #[doc = "0x64 - Transmit Data"] + #[inline(always)] + pub const fn tdr(&self) -> &Tdr { + &self.tdr + } + #[doc = "0x70 - Receive Status"] + #[inline(always)] + pub const fn rsr(&self) -> &Rsr { + &self.rsr + } + #[doc = "0x74 - Receive Data"] + #[inline(always)] + pub const fn rdr(&self) -> &Rdr { + &self.rdr + } + #[doc = "0x78 - Receive Data Read Only"] + #[inline(always)] + pub const fn rdror(&self) -> &Rdror { + &self.rdror + } + #[doc = "0x3fc - Transmit Command Burst"] + #[inline(always)] + pub const fn tcbr(&self) -> &Tcbr { + &self.tcbr + } + #[doc = "0x400..0x600 - Transmit Data Burst"] + #[inline(always)] + pub const fn tdbr(&self, n: usize) -> &Tdbr { + &self.tdbr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x400..0x600 - Transmit Data Burst"] + #[inline(always)] + pub fn tdbr_iter(&self) -> impl Iterator { + self.tdbr.iter() + } + #[doc = "0x600..0x800 - Receive Data Burst"] + #[inline(always)] + pub const fn rdbr(&self, n: usize) -> &Rdbr { + &self.rdbr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x600..0x800 - Receive Data Burst"] + #[inline(always)] + pub fn rdbr_iter(&self) -> impl Iterator { + self.rdbr.iter() + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "CR (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] +#[doc(alias = "CR")] +pub type Cr = crate::Reg; +#[doc = "Control"] +pub mod cr; +#[doc = "SR (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] +#[doc(alias = "SR")] +pub type Sr = crate::Reg; +#[doc = "Status"] +pub mod sr; +#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] +#[doc(alias = "IER")] +pub type Ier = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ier; +#[doc = "DER (rw) register accessor: DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@der`] module"] +#[doc(alias = "DER")] +pub type Der = crate::Reg; +#[doc = "DMA Enable"] +pub mod der; +#[doc = "CFGR0 (rw) register accessor: Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr0`] module"] +#[doc(alias = "CFGR0")] +pub type Cfgr0 = crate::Reg; +#[doc = "Configuration 0"] +pub mod cfgr0; +#[doc = "CFGR1 (rw) register accessor: Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr1`] module"] +#[doc(alias = "CFGR1")] +pub type Cfgr1 = crate::Reg; +#[doc = "Configuration 1"] +pub mod cfgr1; +#[doc = "DMR0 (rw) register accessor: Data Match 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmr0`] module"] +#[doc(alias = "DMR0")] +pub type Dmr0 = crate::Reg; +#[doc = "Data Match 0"] +pub mod dmr0; +#[doc = "DMR1 (rw) register accessor: Data Match 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmr1`] module"] +#[doc(alias = "DMR1")] +pub type Dmr1 = crate::Reg; +#[doc = "Data Match 1"] +pub mod dmr1; +#[doc = "CCR (rw) register accessor: Clock Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`] module"] +#[doc(alias = "CCR")] +pub type Ccr = crate::Reg; +#[doc = "Clock Configuration"] +pub mod ccr; +#[doc = "CCR1 (rw) register accessor: Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`] module"] +#[doc(alias = "CCR1")] +pub type Ccr1 = crate::Reg; +#[doc = "Clock Configuration 1"] +pub mod ccr1; +#[doc = "FCR (rw) register accessor: FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] +#[doc(alias = "FCR")] +pub type Fcr = crate::Reg; +#[doc = "FIFO Control"] +pub mod fcr; +#[doc = "FSR (r) register accessor: FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsr`] module"] +#[doc(alias = "FSR")] +pub type Fsr = crate::Reg; +#[doc = "FIFO Status"] +pub mod fsr; +#[doc = "TCR (rw) register accessor: Transmit Command\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] +#[doc(alias = "TCR")] +pub type Tcr = crate::Reg; +#[doc = "Transmit Command"] +pub mod tcr; +#[doc = "TDR (w) register accessor: Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`] module"] +#[doc(alias = "TDR")] +pub type Tdr = crate::Reg; +#[doc = "Transmit Data"] +pub mod tdr; +#[doc = "RSR (r) register accessor: Receive Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsr`] module"] +#[doc(alias = "RSR")] +pub type Rsr = crate::Reg; +#[doc = "Receive Status"] +pub mod rsr; +#[doc = "RDR (r) register accessor: Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`rdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdr`] module"] +#[doc(alias = "RDR")] +pub type Rdr = crate::Reg; +#[doc = "Receive Data"] +pub mod rdr; +#[doc = "RDROR (r) register accessor: Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`rdror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdror`] module"] +#[doc(alias = "RDROR")] +pub type Rdror = crate::Reg; +#[doc = "Receive Data Read Only"] +pub mod rdror; +#[doc = "TCBR (w) register accessor: Transmit Command Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcbr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcbr`] module"] +#[doc(alias = "TCBR")] +pub type Tcbr = crate::Reg; +#[doc = "Transmit Command Burst"] +pub mod tcbr; +#[doc = "TDBR (w) register accessor: Transmit Data Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdbr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdbr`] module"] +#[doc(alias = "TDBR")] +pub type Tdbr = crate::Reg; +#[doc = "Transmit Data Burst"] +pub mod tdbr; +#[doc = "RDBR (r) register accessor: Receive Data Burst\n\nYou can [`read`](crate::Reg::read) this register and get [`rdbr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdbr`] module"] +#[doc(alias = "RDBR")] +pub type Rdbr = crate::Reg; +#[doc = "Receive Data Burst"] +pub mod rdbr; diff --git a/mcxa276-pac/src/lpspi0/ccr.rs b/mcxa276-pac/src/lpspi0/ccr.rs new file mode 100644 index 000000000..16490c8af --- /dev/null +++ b/mcxa276-pac/src/lpspi0/ccr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CCR` reader"] +pub type R = crate::R; +#[doc = "Register `CCR` writer"] +pub type W = crate::W; +#[doc = "Field `SCKDIV` reader - SCK Divider"] +pub type SckdivR = crate::FieldReader; +#[doc = "Field `SCKDIV` writer - SCK Divider"] +pub type SckdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DBT` reader - Delay Between Transfers"] +pub type DbtR = crate::FieldReader; +#[doc = "Field `DBT` writer - Delay Between Transfers"] +pub type DbtW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PCSSCK` reader - PCS-to-SCK Delay"] +pub type PcssckR = crate::FieldReader; +#[doc = "Field `PCSSCK` writer - PCS-to-SCK Delay"] +pub type PcssckW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCKPCS` reader - SCK-to-PCS Delay"] +pub type SckpcsR = crate::FieldReader; +#[doc = "Field `SCKPCS` writer - SCK-to-PCS Delay"] +pub type SckpcsW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - SCK Divider"] + #[inline(always)] + pub fn sckdiv(&self) -> SckdivR { + SckdivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Delay Between Transfers"] + #[inline(always)] + pub fn dbt(&self) -> DbtR { + DbtR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - PCS-to-SCK Delay"] + #[inline(always)] + pub fn pcssck(&self) -> PcssckR { + PcssckR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - SCK-to-PCS Delay"] + #[inline(always)] + pub fn sckpcs(&self) -> SckpcsR { + SckpcsR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SCK Divider"] + #[inline(always)] + pub fn sckdiv(&mut self) -> SckdivW { + SckdivW::new(self, 0) + } + #[doc = "Bits 8:15 - Delay Between Transfers"] + #[inline(always)] + pub fn dbt(&mut self) -> DbtW { + DbtW::new(self, 8) + } + #[doc = "Bits 16:23 - PCS-to-SCK Delay"] + #[inline(always)] + pub fn pcssck(&mut self) -> PcssckW { + PcssckW::new(self, 16) + } + #[doc = "Bits 24:31 - SCK-to-PCS Delay"] + #[inline(always)] + pub fn sckpcs(&mut self) -> SckpcsW { + SckpcsW::new(self, 24) + } +} +#[doc = "Clock Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CcrSpec; +impl crate::RegisterSpec for CcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] +impl crate::Readable for CcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] +impl crate::Writable for CcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CCR to value 0"] +impl crate::Resettable for CcrSpec {} diff --git a/mcxa276-pac/src/lpspi0/ccr1.rs b/mcxa276-pac/src/lpspi0/ccr1.rs new file mode 100644 index 000000000..f56d82e74 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/ccr1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CCR1` reader"] +pub type R = crate::R; +#[doc = "Register `CCR1` writer"] +pub type W = crate::W; +#[doc = "Field `SCKSET` reader - SCK Setup"] +pub type ScksetR = crate::FieldReader; +#[doc = "Field `SCKSET` writer - SCK Setup"] +pub type ScksetW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCKHLD` reader - SCK Hold"] +pub type SckhldR = crate::FieldReader; +#[doc = "Field `SCKHLD` writer - SCK Hold"] +pub type SckhldW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PCSPCS` reader - PCS to PCS Delay"] +pub type PcspcsR = crate::FieldReader; +#[doc = "Field `PCSPCS` writer - PCS to PCS Delay"] +pub type PcspcsW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCKSCK` reader - SCK Inter-Frame Delay"] +pub type ScksckR = crate::FieldReader; +#[doc = "Field `SCKSCK` writer - SCK Inter-Frame Delay"] +pub type ScksckW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - SCK Setup"] + #[inline(always)] + pub fn sckset(&self) -> ScksetR { + ScksetR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - SCK Hold"] + #[inline(always)] + pub fn sckhld(&self) -> SckhldR { + SckhldR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - PCS to PCS Delay"] + #[inline(always)] + pub fn pcspcs(&self) -> PcspcsR { + PcspcsR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - SCK Inter-Frame Delay"] + #[inline(always)] + pub fn scksck(&self) -> ScksckR { + ScksckR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SCK Setup"] + #[inline(always)] + pub fn sckset(&mut self) -> ScksetW { + ScksetW::new(self, 0) + } + #[doc = "Bits 8:15 - SCK Hold"] + #[inline(always)] + pub fn sckhld(&mut self) -> SckhldW { + SckhldW::new(self, 8) + } + #[doc = "Bits 16:23 - PCS to PCS Delay"] + #[inline(always)] + pub fn pcspcs(&mut self) -> PcspcsW { + PcspcsW::new(self, 16) + } + #[doc = "Bits 24:31 - SCK Inter-Frame Delay"] + #[inline(always)] + pub fn scksck(&mut self) -> ScksckW { + ScksckW::new(self, 24) + } +} +#[doc = "Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ccr1Spec; +impl crate::RegisterSpec for Ccr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"] +impl crate::Readable for Ccr1Spec {} +#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"] +impl crate::Writable for Ccr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CCR1 to value 0"] +impl crate::Resettable for Ccr1Spec {} diff --git a/mcxa276-pac/src/lpspi0/cfgr0.rs b/mcxa276-pac/src/lpspi0/cfgr0.rs new file mode 100644 index 000000000..8be5e6102 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/cfgr0.rs @@ -0,0 +1,399 @@ +#[doc = "Register `CFGR0` reader"] +pub type R = crate::R; +#[doc = "Register `CFGR0` writer"] +pub type W = crate::W; +#[doc = "Host Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hren { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HREN` reader - Host Request Enable"] +pub type HrenR = crate::BitReader; +impl HrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hren { + match self.bits { + false => Hren::Disable, + true => Hren::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Hren::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Hren::Enable + } +} +#[doc = "Field `HREN` writer - Host Request Enable"] +pub type HrenW<'a, REG> = crate::BitWriter<'a, REG, Hren>; +impl<'a, REG> HrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Hren::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Hren::Enable) + } +} +#[doc = "Host Request Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hrpol { + #[doc = "0: Active high"] + Disabled = 0, + #[doc = "1: Active low"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hrpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HRPOL` reader - Host Request Polarity"] +pub type HrpolR = crate::BitReader; +impl HrpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hrpol { + match self.bits { + false => Hrpol::Disabled, + true => Hrpol::Enabled, + } + } + #[doc = "Active high"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Hrpol::Disabled + } + #[doc = "Active low"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Hrpol::Enabled + } +} +#[doc = "Field `HRPOL` writer - Host Request Polarity"] +pub type HrpolW<'a, REG> = crate::BitWriter<'a, REG, Hrpol>; +impl<'a, REG> HrpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active high"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Hrpol::Disabled) + } + #[doc = "Active low"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Hrpol::Enabled) + } +} +#[doc = "Host Request Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hrsel { + #[doc = "0: HREQ pin"] + Hreqpin = 0, + #[doc = "1: Input trigger"] + InputTrigger = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hrsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HRSEL` reader - Host Request Select"] +pub type HrselR = crate::BitReader; +impl HrselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hrsel { + match self.bits { + false => Hrsel::Hreqpin, + true => Hrsel::InputTrigger, + } + } + #[doc = "HREQ pin"] + #[inline(always)] + pub fn is_hreqpin(&self) -> bool { + *self == Hrsel::Hreqpin + } + #[doc = "Input trigger"] + #[inline(always)] + pub fn is_input_trigger(&self) -> bool { + *self == Hrsel::InputTrigger + } +} +#[doc = "Field `HRSEL` writer - Host Request Select"] +pub type HrselW<'a, REG> = crate::BitWriter<'a, REG, Hrsel>; +impl<'a, REG> HrselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "HREQ pin"] + #[inline(always)] + pub fn hreqpin(self) -> &'a mut crate::W { + self.variant(Hrsel::Hreqpin) + } + #[doc = "Input trigger"] + #[inline(always)] + pub fn input_trigger(self) -> &'a mut crate::W { + self.variant(Hrsel::InputTrigger) + } +} +#[doc = "Host Request Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hrdir { + #[doc = "0: Input"] + Input = 0, + #[doc = "1: Output"] + Output = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hrdir) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HRDIR` reader - Host Request Direction"] +pub type HrdirR = crate::BitReader; +impl HrdirR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hrdir { + match self.bits { + false => Hrdir::Input, + true => Hrdir::Output, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == Hrdir::Input + } + #[doc = "Output"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == Hrdir::Output + } +} +#[doc = "Field `HRDIR` writer - Host Request Direction"] +pub type HrdirW<'a, REG> = crate::BitWriter<'a, REG, Hrdir>; +impl<'a, REG> HrdirW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn input(self) -> &'a mut crate::W { + self.variant(Hrdir::Input) + } + #[doc = "Output"] + #[inline(always)] + pub fn output(self) -> &'a mut crate::W { + self.variant(Hrdir::Output) + } +} +#[doc = "Circular FIFO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cirfifo { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cirfifo) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CIRFIFO` reader - Circular FIFO Enable"] +pub type CirfifoR = crate::BitReader; +impl CirfifoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cirfifo { + match self.bits { + false => Cirfifo::Disable, + true => Cirfifo::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Cirfifo::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Cirfifo::Enable + } +} +#[doc = "Field `CIRFIFO` writer - Circular FIFO Enable"] +pub type CirfifoW<'a, REG> = crate::BitWriter<'a, REG, Cirfifo>; +impl<'a, REG> CirfifoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Cirfifo::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Cirfifo::Enable) + } +} +#[doc = "Receive Data Match Only\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdmo { + #[doc = "0: Disable"] + Stored = 0, + #[doc = "1: Enable"] + Discarded = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdmo) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDMO` reader - Receive Data Match Only"] +pub type RdmoR = crate::BitReader; +impl RdmoR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdmo { + match self.bits { + false => Rdmo::Stored, + true => Rdmo::Discarded, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_stored(&self) -> bool { + *self == Rdmo::Stored + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_discarded(&self) -> bool { + *self == Rdmo::Discarded + } +} +#[doc = "Field `RDMO` writer - Receive Data Match Only"] +pub type RdmoW<'a, REG> = crate::BitWriter<'a, REG, Rdmo>; +impl<'a, REG> RdmoW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn stored(self) -> &'a mut crate::W { + self.variant(Rdmo::Stored) + } + #[doc = "Enable"] + #[inline(always)] + pub fn discarded(self) -> &'a mut crate::W { + self.variant(Rdmo::Discarded) + } +} +impl R { + #[doc = "Bit 0 - Host Request Enable"] + #[inline(always)] + pub fn hren(&self) -> HrenR { + HrenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Host Request Polarity"] + #[inline(always)] + pub fn hrpol(&self) -> HrpolR { + HrpolR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host Request Select"] + #[inline(always)] + pub fn hrsel(&self) -> HrselR { + HrselR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Host Request Direction"] + #[inline(always)] + pub fn hrdir(&self) -> HrdirR { + HrdirR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Circular FIFO Enable"] + #[inline(always)] + pub fn cirfifo(&self) -> CirfifoR { + CirfifoR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Receive Data Match Only"] + #[inline(always)] + pub fn rdmo(&self) -> RdmoR { + RdmoR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Host Request Enable"] + #[inline(always)] + pub fn hren(&mut self) -> HrenW { + HrenW::new(self, 0) + } + #[doc = "Bit 1 - Host Request Polarity"] + #[inline(always)] + pub fn hrpol(&mut self) -> HrpolW { + HrpolW::new(self, 1) + } + #[doc = "Bit 2 - Host Request Select"] + #[inline(always)] + pub fn hrsel(&mut self) -> HrselW { + HrselW::new(self, 2) + } + #[doc = "Bit 3 - Host Request Direction"] + #[inline(always)] + pub fn hrdir(&mut self) -> HrdirW { + HrdirW::new(self, 3) + } + #[doc = "Bit 8 - Circular FIFO Enable"] + #[inline(always)] + pub fn cirfifo(&mut self) -> CirfifoW { + CirfifoW::new(self, 8) + } + #[doc = "Bit 9 - Receive Data Match Only"] + #[inline(always)] + pub fn rdmo(&mut self) -> RdmoW { + RdmoW::new(self, 9) + } +} +#[doc = "Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cfgr0Spec; +impl crate::RegisterSpec for Cfgr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfgr0::R`](R) reader structure"] +impl crate::Readable for Cfgr0Spec {} +#[doc = "`write(|w| ..)` method takes [`cfgr0::W`](W) writer structure"] +impl crate::Writable for Cfgr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CFGR0 to value 0"] +impl crate::Resettable for Cfgr0Spec {} diff --git a/mcxa276-pac/src/lpspi0/cfgr1.rs b/mcxa276-pac/src/lpspi0/cfgr1.rs new file mode 100644 index 000000000..c3a2bc79f --- /dev/null +++ b/mcxa276-pac/src/lpspi0/cfgr1.rs @@ -0,0 +1,763 @@ +#[doc = "Register `CFGR1` reader"] +pub type R = crate::R; +#[doc = "Register `CFGR1` writer"] +pub type W = crate::W; +#[doc = "Controller Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Master { + #[doc = "0: Peripheral mode"] + SlaveMode = 0, + #[doc = "1: Controller mode"] + MasterMode = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Master) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MASTER` reader - Controller Mode"] +pub type MasterR = crate::BitReader; +impl MasterR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Master { + match self.bits { + false => Master::SlaveMode, + true => Master::MasterMode, + } + } + #[doc = "Peripheral mode"] + #[inline(always)] + pub fn is_slave_mode(&self) -> bool { + *self == Master::SlaveMode + } + #[doc = "Controller mode"] + #[inline(always)] + pub fn is_master_mode(&self) -> bool { + *self == Master::MasterMode + } +} +#[doc = "Field `MASTER` writer - Controller Mode"] +pub type MasterW<'a, REG> = crate::BitWriter<'a, REG, Master>; +impl<'a, REG> MasterW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral mode"] + #[inline(always)] + pub fn slave_mode(self) -> &'a mut crate::W { + self.variant(Master::SlaveMode) + } + #[doc = "Controller mode"] + #[inline(always)] + pub fn master_mode(self) -> &'a mut crate::W { + self.variant(Master::MasterMode) + } +} +#[doc = "Sample Point\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sample { + #[doc = "0: SCK edge"] + OnSckEdge = 0, + #[doc = "1: Delayed SCK edge"] + OnDelayedSckEdge = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sample) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SAMPLE` reader - Sample Point"] +pub type SampleR = crate::BitReader; +impl SampleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sample { + match self.bits { + false => Sample::OnSckEdge, + true => Sample::OnDelayedSckEdge, + } + } + #[doc = "SCK edge"] + #[inline(always)] + pub fn is_on_sck_edge(&self) -> bool { + *self == Sample::OnSckEdge + } + #[doc = "Delayed SCK edge"] + #[inline(always)] + pub fn is_on_delayed_sck_edge(&self) -> bool { + *self == Sample::OnDelayedSckEdge + } +} +#[doc = "Field `SAMPLE` writer - Sample Point"] +pub type SampleW<'a, REG> = crate::BitWriter<'a, REG, Sample>; +impl<'a, REG> SampleW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SCK edge"] + #[inline(always)] + pub fn on_sck_edge(self) -> &'a mut crate::W { + self.variant(Sample::OnSckEdge) + } + #[doc = "Delayed SCK edge"] + #[inline(always)] + pub fn on_delayed_sck_edge(self) -> &'a mut crate::W { + self.variant(Sample::OnDelayedSckEdge) + } +} +#[doc = "Automatic PCS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Autopcs { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Autopcs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AUTOPCS` reader - Automatic PCS"] +pub type AutopcsR = crate::BitReader; +impl AutopcsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Autopcs { + match self.bits { + false => Autopcs::Disabled, + true => Autopcs::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Autopcs::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Autopcs::Enabled + } +} +#[doc = "Field `AUTOPCS` writer - Automatic PCS"] +pub type AutopcsW<'a, REG> = crate::BitWriter<'a, REG, Autopcs>; +impl<'a, REG> AutopcsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Autopcs::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Autopcs::Enabled) + } +} +#[doc = "No Stall\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nostall { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nostall) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOSTALL` reader - No Stall"] +pub type NostallR = crate::BitReader; +impl NostallR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nostall { + match self.bits { + false => Nostall::Disable, + true => Nostall::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Nostall::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Nostall::Enable + } +} +#[doc = "Field `NOSTALL` writer - No Stall"] +pub type NostallW<'a, REG> = crate::BitWriter<'a, REG, Nostall>; +impl<'a, REG> NostallW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Nostall::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Nostall::Enable) + } +} +#[doc = "Partial Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Partial { + #[doc = "0: Discard"] + Discarded = 0, + #[doc = "1: Store"] + Stored = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Partial) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PARTIAL` reader - Partial Enable"] +pub type PartialR = crate::BitReader; +impl PartialR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Partial { + match self.bits { + false => Partial::Discarded, + true => Partial::Stored, + } + } + #[doc = "Discard"] + #[inline(always)] + pub fn is_discarded(&self) -> bool { + *self == Partial::Discarded + } + #[doc = "Store"] + #[inline(always)] + pub fn is_stored(&self) -> bool { + *self == Partial::Stored + } +} +#[doc = "Field `PARTIAL` writer - Partial Enable"] +pub type PartialW<'a, REG> = crate::BitWriter<'a, REG, Partial>; +impl<'a, REG> PartialW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Discard"] + #[inline(always)] + pub fn discarded(self) -> &'a mut crate::W { + self.variant(Partial::Discarded) + } + #[doc = "Store"] + #[inline(always)] + pub fn stored(self) -> &'a mut crate::W { + self.variant(Partial::Stored) + } +} +#[doc = "Peripheral Chip Select Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pcspol { + #[doc = "0: Active low"] + Discarded = 0, + #[doc = "1: Active high"] + Stored = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pcspol) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pcspol { + type Ux = u8; +} +impl crate::IsEnum for Pcspol {} +#[doc = "Field `PCSPOL` reader - Peripheral Chip Select Polarity"] +pub type PcspolR = crate::FieldReader; +impl PcspolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Pcspol::Discarded), + 1 => Some(Pcspol::Stored), + _ => None, + } + } + #[doc = "Active low"] + #[inline(always)] + pub fn is_discarded(&self) -> bool { + *self == Pcspol::Discarded + } + #[doc = "Active high"] + #[inline(always)] + pub fn is_stored(&self) -> bool { + *self == Pcspol::Stored + } +} +#[doc = "Field `PCSPOL` writer - Peripheral Chip Select Polarity"] +pub type PcspolW<'a, REG> = crate::FieldWriter<'a, REG, 4, Pcspol>; +impl<'a, REG> PcspolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Active low"] + #[inline(always)] + pub fn discarded(self) -> &'a mut crate::W { + self.variant(Pcspol::Discarded) + } + #[doc = "Active high"] + #[inline(always)] + pub fn stored(self) -> &'a mut crate::W { + self.variant(Pcspol::Stored) + } +} +#[doc = "Match Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Matcfg { + #[doc = "0: Match is disabled"] + Disabled = 0, + #[doc = "2: Match first data word with compare word"] + EnabledFirstdatamatch = 2, + #[doc = "3: Match any data word with compare word"] + EnabledAnydatamatch = 3, + #[doc = "4: Sequential match, first data word"] + EnabledDatamatch100 = 4, + #[doc = "5: Sequential match, any data word"] + EnabledDatamatch101 = 5, + #[doc = "6: Match first data word (masked) with compare word (masked)"] + EnabledDatamatch110 = 6, + #[doc = "7: Match any data word (masked) with compare word (masked)"] + EnabledDatamatch111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Matcfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Matcfg { + type Ux = u8; +} +impl crate::IsEnum for Matcfg {} +#[doc = "Field `MATCFG` reader - Match Configuration"] +pub type MatcfgR = crate::FieldReader; +impl MatcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Matcfg::Disabled), + 2 => Some(Matcfg::EnabledFirstdatamatch), + 3 => Some(Matcfg::EnabledAnydatamatch), + 4 => Some(Matcfg::EnabledDatamatch100), + 5 => Some(Matcfg::EnabledDatamatch101), + 6 => Some(Matcfg::EnabledDatamatch110), + 7 => Some(Matcfg::EnabledDatamatch111), + _ => None, + } + } + #[doc = "Match is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Matcfg::Disabled + } + #[doc = "Match first data word with compare word"] + #[inline(always)] + pub fn is_enabled_firstdatamatch(&self) -> bool { + *self == Matcfg::EnabledFirstdatamatch + } + #[doc = "Match any data word with compare word"] + #[inline(always)] + pub fn is_enabled_anydatamatch(&self) -> bool { + *self == Matcfg::EnabledAnydatamatch + } + #[doc = "Sequential match, first data word"] + #[inline(always)] + pub fn is_enabled_datamatch_100(&self) -> bool { + *self == Matcfg::EnabledDatamatch100 + } + #[doc = "Sequential match, any data word"] + #[inline(always)] + pub fn is_enabled_datamatch_101(&self) -> bool { + *self == Matcfg::EnabledDatamatch101 + } + #[doc = "Match first data word (masked) with compare word (masked)"] + #[inline(always)] + pub fn is_enabled_datamatch_110(&self) -> bool { + *self == Matcfg::EnabledDatamatch110 + } + #[doc = "Match any data word (masked) with compare word (masked)"] + #[inline(always)] + pub fn is_enabled_datamatch_111(&self) -> bool { + *self == Matcfg::EnabledDatamatch111 + } +} +#[doc = "Field `MATCFG` writer - Match Configuration"] +pub type MatcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Matcfg>; +impl<'a, REG> MatcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Match is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Matcfg::Disabled) + } + #[doc = "Match first data word with compare word"] + #[inline(always)] + pub fn enabled_firstdatamatch(self) -> &'a mut crate::W { + self.variant(Matcfg::EnabledFirstdatamatch) + } + #[doc = "Match any data word with compare word"] + #[inline(always)] + pub fn enabled_anydatamatch(self) -> &'a mut crate::W { + self.variant(Matcfg::EnabledAnydatamatch) + } + #[doc = "Sequential match, first data word"] + #[inline(always)] + pub fn enabled_datamatch_100(self) -> &'a mut crate::W { + self.variant(Matcfg::EnabledDatamatch100) + } + #[doc = "Sequential match, any data word"] + #[inline(always)] + pub fn enabled_datamatch_101(self) -> &'a mut crate::W { + self.variant(Matcfg::EnabledDatamatch101) + } + #[doc = "Match first data word (masked) with compare word (masked)"] + #[inline(always)] + pub fn enabled_datamatch_110(self) -> &'a mut crate::W { + self.variant(Matcfg::EnabledDatamatch110) + } + #[doc = "Match any data word (masked) with compare word (masked)"] + #[inline(always)] + pub fn enabled_datamatch_111(self) -> &'a mut crate::W { + self.variant(Matcfg::EnabledDatamatch111) + } +} +#[doc = "Pin Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pincfg { + #[doc = "0: SIN is used for input data; SOUT is used for output data"] + SinInSoutOut = 0, + #[doc = "1: SIN is used for both input and output data; only half-duplex serial transfers are supported"] + SinBothInOut = 1, + #[doc = "2: SOUT is used for both input and output data; only half-duplex serial transfers are supported"] + SoutBothInOut = 2, + #[doc = "3: SOUT is used for input data; SIN is used for output data"] + SoutInSinOut = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pincfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pincfg { + type Ux = u8; +} +impl crate::IsEnum for Pincfg {} +#[doc = "Field `PINCFG` reader - Pin Configuration"] +pub type PincfgR = crate::FieldReader; +impl PincfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pincfg { + match self.bits { + 0 => Pincfg::SinInSoutOut, + 1 => Pincfg::SinBothInOut, + 2 => Pincfg::SoutBothInOut, + 3 => Pincfg::SoutInSinOut, + _ => unreachable!(), + } + } + #[doc = "SIN is used for input data; SOUT is used for output data"] + #[inline(always)] + pub fn is_sin_in_sout_out(&self) -> bool { + *self == Pincfg::SinInSoutOut + } + #[doc = "SIN is used for both input and output data; only half-duplex serial transfers are supported"] + #[inline(always)] + pub fn is_sin_both_in_out(&self) -> bool { + *self == Pincfg::SinBothInOut + } + #[doc = "SOUT is used for both input and output data; only half-duplex serial transfers are supported"] + #[inline(always)] + pub fn is_sout_both_in_out(&self) -> bool { + *self == Pincfg::SoutBothInOut + } + #[doc = "SOUT is used for input data; SIN is used for output data"] + #[inline(always)] + pub fn is_sout_in_sin_out(&self) -> bool { + *self == Pincfg::SoutInSinOut + } +} +#[doc = "Field `PINCFG` writer - Pin Configuration"] +pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pincfg, crate::Safe>; +impl<'a, REG> PincfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "SIN is used for input data; SOUT is used for output data"] + #[inline(always)] + pub fn sin_in_sout_out(self) -> &'a mut crate::W { + self.variant(Pincfg::SinInSoutOut) + } + #[doc = "SIN is used for both input and output data; only half-duplex serial transfers are supported"] + #[inline(always)] + pub fn sin_both_in_out(self) -> &'a mut crate::W { + self.variant(Pincfg::SinBothInOut) + } + #[doc = "SOUT is used for both input and output data; only half-duplex serial transfers are supported"] + #[inline(always)] + pub fn sout_both_in_out(self) -> &'a mut crate::W { + self.variant(Pincfg::SoutBothInOut) + } + #[doc = "SOUT is used for input data; SIN is used for output data"] + #[inline(always)] + pub fn sout_in_sin_out(self) -> &'a mut crate::W { + self.variant(Pincfg::SoutInSinOut) + } +} +#[doc = "Output Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Outcfg { + #[doc = "0: Retain last value"] + RetainLastvalue = 0, + #[doc = "1: 3-stated"] + Tristated = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Outcfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OUTCFG` reader - Output Configuration"] +pub type OutcfgR = crate::BitReader; +impl OutcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Outcfg { + match self.bits { + false => Outcfg::RetainLastvalue, + true => Outcfg::Tristated, + } + } + #[doc = "Retain last value"] + #[inline(always)] + pub fn is_retain_lastvalue(&self) -> bool { + *self == Outcfg::RetainLastvalue + } + #[doc = "3-stated"] + #[inline(always)] + pub fn is_tristated(&self) -> bool { + *self == Outcfg::Tristated + } +} +#[doc = "Field `OUTCFG` writer - Output Configuration"] +pub type OutcfgW<'a, REG> = crate::BitWriter<'a, REG, Outcfg>; +impl<'a, REG> OutcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Retain last value"] + #[inline(always)] + pub fn retain_lastvalue(self) -> &'a mut crate::W { + self.variant(Outcfg::RetainLastvalue) + } + #[doc = "3-stated"] + #[inline(always)] + pub fn tristated(self) -> &'a mut crate::W { + self.variant(Outcfg::Tristated) + } +} +#[doc = "Peripheral Chip Select Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pcscfg { + #[doc = "0: PCS\\[3:2\\] configured for chip select function"] + ChipSelect = 0, + #[doc = "1: PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"] + Halfduplex4bit = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pcscfg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PCSCFG` reader - Peripheral Chip Select Configuration"] +pub type PcscfgR = crate::BitReader; +impl PcscfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pcscfg { + match self.bits { + false => Pcscfg::ChipSelect, + true => Pcscfg::Halfduplex4bit, + } + } + #[doc = "PCS\\[3:2\\] configured for chip select function"] + #[inline(always)] + pub fn is_chip_select(&self) -> bool { + *self == Pcscfg::ChipSelect + } + #[doc = "PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"] + #[inline(always)] + pub fn is_halfduplex4bit(&self) -> bool { + *self == Pcscfg::Halfduplex4bit + } +} +#[doc = "Field `PCSCFG` writer - Peripheral Chip Select Configuration"] +pub type PcscfgW<'a, REG> = crate::BitWriter<'a, REG, Pcscfg>; +impl<'a, REG> PcscfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "PCS\\[3:2\\] configured for chip select function"] + #[inline(always)] + pub fn chip_select(self) -> &'a mut crate::W { + self.variant(Pcscfg::ChipSelect) + } + #[doc = "PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"] + #[inline(always)] + pub fn halfduplex4bit(self) -> &'a mut crate::W { + self.variant(Pcscfg::Halfduplex4bit) + } +} +impl R { + #[doc = "Bit 0 - Controller Mode"] + #[inline(always)] + pub fn master(&self) -> MasterR { + MasterR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Sample Point"] + #[inline(always)] + pub fn sample(&self) -> SampleR { + SampleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Automatic PCS"] + #[inline(always)] + pub fn autopcs(&self) -> AutopcsR { + AutopcsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - No Stall"] + #[inline(always)] + pub fn nostall(&self) -> NostallR { + NostallR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Partial Enable"] + #[inline(always)] + pub fn partial(&self) -> PartialR { + PartialR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"] + #[inline(always)] + pub fn pcspol(&self) -> PcspolR { + PcspolR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:18 - Match Configuration"] + #[inline(always)] + pub fn matcfg(&self) -> MatcfgR { + MatcfgR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 24:25 - Pin Configuration"] + #[inline(always)] + pub fn pincfg(&self) -> PincfgR { + PincfgR::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Output Configuration"] + #[inline(always)] + pub fn outcfg(&self) -> OutcfgR { + OutcfgR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Peripheral Chip Select Configuration"] + #[inline(always)] + pub fn pcscfg(&self) -> PcscfgR { + PcscfgR::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controller Mode"] + #[inline(always)] + pub fn master(&mut self) -> MasterW { + MasterW::new(self, 0) + } + #[doc = "Bit 1 - Sample Point"] + #[inline(always)] + pub fn sample(&mut self) -> SampleW { + SampleW::new(self, 1) + } + #[doc = "Bit 2 - Automatic PCS"] + #[inline(always)] + pub fn autopcs(&mut self) -> AutopcsW { + AutopcsW::new(self, 2) + } + #[doc = "Bit 3 - No Stall"] + #[inline(always)] + pub fn nostall(&mut self) -> NostallW { + NostallW::new(self, 3) + } + #[doc = "Bit 4 - Partial Enable"] + #[inline(always)] + pub fn partial(&mut self) -> PartialW { + PartialW::new(self, 4) + } + #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"] + #[inline(always)] + pub fn pcspol(&mut self) -> PcspolW { + PcspolW::new(self, 8) + } + #[doc = "Bits 16:18 - Match Configuration"] + #[inline(always)] + pub fn matcfg(&mut self) -> MatcfgW { + MatcfgW::new(self, 16) + } + #[doc = "Bits 24:25 - Pin Configuration"] + #[inline(always)] + pub fn pincfg(&mut self) -> PincfgW { + PincfgW::new(self, 24) + } + #[doc = "Bit 26 - Output Configuration"] + #[inline(always)] + pub fn outcfg(&mut self) -> OutcfgW { + OutcfgW::new(self, 26) + } + #[doc = "Bit 27 - Peripheral Chip Select Configuration"] + #[inline(always)] + pub fn pcscfg(&mut self) -> PcscfgW { + PcscfgW::new(self, 27) + } +} +#[doc = "Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cfgr1Spec; +impl crate::RegisterSpec for Cfgr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfgr1::R`](R) reader structure"] +impl crate::Readable for Cfgr1Spec {} +#[doc = "`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure"] +impl crate::Writable for Cfgr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CFGR1 to value 0"] +impl crate::Resettable for Cfgr1Spec {} diff --git a/mcxa276-pac/src/lpspi0/cr.rs b/mcxa276-pac/src/lpspi0/cr.rs new file mode 100644 index 000000000..fc2a9997b --- /dev/null +++ b/mcxa276-pac/src/lpspi0/cr.rs @@ -0,0 +1,282 @@ +#[doc = "Register `CR` reader"] +pub type R = crate::R; +#[doc = "Register `CR` writer"] +pub type W = crate::W; +#[doc = "Module Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Men { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Men) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MEN` reader - Module Enable"] +pub type MenR = crate::BitReader; +impl MenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Men { + match self.bits { + false => Men::Disabled, + true => Men::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Men::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Men::Enabled + } +} +#[doc = "Field `MEN` writer - Module Enable"] +pub type MenW<'a, REG> = crate::BitWriter<'a, REG, Men>; +impl<'a, REG> MenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Men::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Men::Enabled) + } +} +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rst { + #[doc = "0: Not reset"] + NotReset = 0, + #[doc = "1: Reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RST` reader - Software Reset"] +pub type RstR = crate::BitReader; +impl RstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rst { + match self.bits { + false => Rst::NotReset, + true => Rst::Reset, + } + } + #[doc = "Not reset"] + #[inline(always)] + pub fn is_not_reset(&self) -> bool { + *self == Rst::NotReset + } + #[doc = "Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Rst::Reset + } +} +#[doc = "Field `RST` writer - Software Reset"] +pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; +impl<'a, REG> RstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not reset"] + #[inline(always)] + pub fn not_reset(self) -> &'a mut crate::W { + self.variant(Rst::NotReset) + } + #[doc = "Reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Rst::Reset) + } +} +#[doc = "Debug Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dbgen { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dbgen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DBGEN` reader - Debug Enable"] +pub type DbgenR = crate::BitReader; +impl DbgenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dbgen { + match self.bits { + false => Dbgen::Disabled, + true => Dbgen::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dbgen::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dbgen::Enabled + } +} +#[doc = "Field `DBGEN` writer - Debug Enable"] +pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG, Dbgen>; +impl<'a, REG> DbgenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dbgen::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dbgen::Enabled) + } +} +#[doc = "Reset Transmit FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rtf { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Reset"] + TxfifoRst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rtf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RTF` writer - Reset Transmit FIFO"] +pub type RtfW<'a, REG> = crate::BitWriter<'a, REG, Rtf>; +impl<'a, REG> RtfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rtf::NoEffect) + } + #[doc = "Reset"] + #[inline(always)] + pub fn txfifo_rst(self) -> &'a mut crate::W { + self.variant(Rtf::TxfifoRst) + } +} +#[doc = "Reset Receive FIFO\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rrf { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Reset"] + RxfifoRst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rrf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRF` writer - Reset Receive FIFO"] +pub type RrfW<'a, REG> = crate::BitWriter<'a, REG, Rrf>; +impl<'a, REG> RrfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rrf::NoEffect) + } + #[doc = "Reset"] + #[inline(always)] + pub fn rxfifo_rst(self) -> &'a mut crate::W { + self.variant(Rrf::RxfifoRst) + } +} +impl R { + #[doc = "Bit 0 - Module Enable"] + #[inline(always)] + pub fn men(&self) -> MenR { + MenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&self) -> RstR { + RstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&self) -> DbgenR { + DbgenR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Module Enable"] + #[inline(always)] + pub fn men(&mut self) -> MenW { + MenW::new(self, 0) + } + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RstW { + RstW::new(self, 1) + } + #[doc = "Bit 3 - Debug Enable"] + #[inline(always)] + pub fn dbgen(&mut self) -> DbgenW { + DbgenW::new(self, 3) + } + #[doc = "Bit 8 - Reset Transmit FIFO"] + #[inline(always)] + pub fn rtf(&mut self) -> RtfW { + RtfW::new(self, 8) + } + #[doc = "Bit 9 - Reset Receive FIFO"] + #[inline(always)] + pub fn rrf(&mut self) -> RrfW { + RrfW::new(self, 9) + } +} +#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrSpec; +impl crate::RegisterSpec for CrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CrSpec {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] +impl crate::Writable for CrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CR to value 0"] +impl crate::Resettable for CrSpec {} diff --git a/mcxa276-pac/src/lpspi0/der.rs b/mcxa276-pac/src/lpspi0/der.rs new file mode 100644 index 000000000..caee3b120 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/der.rs @@ -0,0 +1,210 @@ +#[doc = "Register `DER` reader"] +pub type R = crate::R; +#[doc = "Register `DER` writer"] +pub type W = crate::W; +#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"] +pub type TddeR = crate::BitReader; +impl TddeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdde { + match self.bits { + false => Tdde::Disable, + true => Tdde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tdde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tdde::Enable + } +} +#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"] +pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>; +impl<'a, REG> TddeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tdde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tdde::Enable) + } +} +#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDDE` reader - Receive Data DMA Enable"] +pub type RddeR = crate::BitReader; +impl RddeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdde { + match self.bits { + false => Rdde::Disable, + true => Rdde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rdde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rdde::Enable + } +} +#[doc = "Field `RDDE` writer - Receive Data DMA Enable"] +pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>; +impl<'a, REG> RddeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Rdde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Rdde::Enable) + } +} +#[doc = "Frame Complete DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fcde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fcde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FCDE` reader - Frame Complete DMA Enable"] +pub type FcdeR = crate::BitReader; +impl FcdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fcde { + match self.bits { + false => Fcde::Disable, + true => Fcde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Fcde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Fcde::Enable + } +} +#[doc = "Field `FCDE` writer - Frame Complete DMA Enable"] +pub type FcdeW<'a, REG> = crate::BitWriter<'a, REG, Fcde>; +impl<'a, REG> FcdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Fcde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Fcde::Enable) + } +} +impl R { + #[doc = "Bit 0 - Transmit Data DMA Enable"] + #[inline(always)] + pub fn tdde(&self) -> TddeR { + TddeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data DMA Enable"] + #[inline(always)] + pub fn rdde(&self) -> RddeR { + RddeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - Frame Complete DMA Enable"] + #[inline(always)] + pub fn fcde(&self) -> FcdeR { + FcdeR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Data DMA Enable"] + #[inline(always)] + pub fn tdde(&mut self) -> TddeW { + TddeW::new(self, 0) + } + #[doc = "Bit 1 - Receive Data DMA Enable"] + #[inline(always)] + pub fn rdde(&mut self) -> RddeW { + RddeW::new(self, 1) + } + #[doc = "Bit 9 - Frame Complete DMA Enable"] + #[inline(always)] + pub fn fcde(&mut self) -> FcdeW { + FcdeW::new(self, 9) + } +} +#[doc = "DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DerSpec; +impl crate::RegisterSpec for DerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`der::R`](R) reader structure"] +impl crate::Readable for DerSpec {} +#[doc = "`write(|w| ..)` method takes [`der::W`](W) writer structure"] +impl crate::Writable for DerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DER to value 0"] +impl crate::Resettable for DerSpec {} diff --git a/mcxa276-pac/src/lpspi0/dmr0.rs b/mcxa276-pac/src/lpspi0/dmr0.rs new file mode 100644 index 000000000..3f76b6ee1 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/dmr0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMR0` reader"] +pub type R = crate::R; +#[doc = "Register `DMR0` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH0` reader - Match 0 Value"] +pub type Match0R = crate::FieldReader; +#[doc = "Field `MATCH0` writer - Match 0 Value"] +pub type Match0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Match 0 Value"] + #[inline(always)] + pub fn match0(&self) -> Match0R { + Match0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Match 0 Value"] + #[inline(always)] + pub fn match0(&mut self) -> Match0W { + Match0W::new(self, 0) + } +} +#[doc = "Data Match 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmr0Spec; +impl crate::RegisterSpec for Dmr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmr0::R`](R) reader structure"] +impl crate::Readable for Dmr0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmr0::W`](W) writer structure"] +impl crate::Writable for Dmr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMR0 to value 0"] +impl crate::Resettable for Dmr0Spec {} diff --git a/mcxa276-pac/src/lpspi0/dmr1.rs b/mcxa276-pac/src/lpspi0/dmr1.rs new file mode 100644 index 000000000..31b4aca39 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/dmr1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMR1` reader"] +pub type R = crate::R; +#[doc = "Register `DMR1` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH1` reader - Match 1 Value"] +pub type Match1R = crate::FieldReader; +#[doc = "Field `MATCH1` writer - Match 1 Value"] +pub type Match1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Match 1 Value"] + #[inline(always)] + pub fn match1(&self) -> Match1R { + Match1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Match 1 Value"] + #[inline(always)] + pub fn match1(&mut self) -> Match1W { + Match1W::new(self, 0) + } +} +#[doc = "Data Match 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmr1Spec; +impl crate::RegisterSpec for Dmr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmr1::R`](R) reader structure"] +impl crate::Readable for Dmr1Spec {} +#[doc = "`write(|w| ..)` method takes [`dmr1::W`](W) writer structure"] +impl crate::Writable for Dmr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMR1 to value 0"] +impl crate::Resettable for Dmr1Spec {} diff --git a/mcxa276-pac/src/lpspi0/fcr.rs b/mcxa276-pac/src/lpspi0/fcr.rs new file mode 100644 index 000000000..fd2f3299e --- /dev/null +++ b/mcxa276-pac/src/lpspi0/fcr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `FCR` reader"] +pub type R = crate::R; +#[doc = "Register `FCR` writer"] +pub type W = crate::W; +#[doc = "Field `TXWATER` reader - Transmit FIFO Watermark"] +pub type TxwaterR = crate::FieldReader; +#[doc = "Field `TXWATER` writer - Transmit FIFO Watermark"] +pub type TxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RXWATER` reader - Receive FIFO Watermark"] +pub type RxwaterR = crate::FieldReader; +#[doc = "Field `RXWATER` writer - Receive FIFO Watermark"] +pub type RxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Transmit FIFO Watermark"] + #[inline(always)] + pub fn txwater(&self) -> TxwaterR { + TxwaterR::new((self.bits & 3) as u8) + } + #[doc = "Bits 16:17 - Receive FIFO Watermark"] + #[inline(always)] + pub fn rxwater(&self) -> RxwaterR { + RxwaterR::new(((self.bits >> 16) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Transmit FIFO Watermark"] + #[inline(always)] + pub fn txwater(&mut self) -> TxwaterW { + TxwaterW::new(self, 0) + } + #[doc = "Bits 16:17 - Receive FIFO Watermark"] + #[inline(always)] + pub fn rxwater(&mut self) -> RxwaterW { + RxwaterW::new(self, 16) + } +} +#[doc = "FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FcrSpec; +impl crate::RegisterSpec for FcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fcr::R`](R) reader structure"] +impl crate::Readable for FcrSpec {} +#[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] +impl crate::Writable for FcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FCR to value 0"] +impl crate::Resettable for FcrSpec {} diff --git a/mcxa276-pac/src/lpspi0/fsr.rs b/mcxa276-pac/src/lpspi0/fsr.rs new file mode 100644 index 000000000..06ed61d5b --- /dev/null +++ b/mcxa276-pac/src/lpspi0/fsr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `FSR` reader"] +pub type R = crate::R; +#[doc = "Field `TXCOUNT` reader - Transmit FIFO Count"] +pub type TxcountR = crate::FieldReader; +#[doc = "Field `RXCOUNT` reader - Receive FIFO Count"] +pub type RxcountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Transmit FIFO Count"] + #[inline(always)] + pub fn txcount(&self) -> TxcountR { + TxcountR::new((self.bits & 7) as u8) + } + #[doc = "Bits 16:18 - Receive FIFO Count"] + #[inline(always)] + pub fn rxcount(&self) -> RxcountR { + RxcountR::new(((self.bits >> 16) & 7) as u8) + } +} +#[doc = "FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FsrSpec; +impl crate::RegisterSpec for FsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fsr::R`](R) reader structure"] +impl crate::Readable for FsrSpec {} +#[doc = "`reset()` method sets FSR to value 0"] +impl crate::Resettable for FsrSpec {} diff --git a/mcxa276-pac/src/lpspi0/ier.rs b/mcxa276-pac/src/lpspi0/ier.rs new file mode 100644 index 000000000..2ce7aedfd --- /dev/null +++ b/mcxa276-pac/src/lpspi0/ier.rs @@ -0,0 +1,525 @@ +#[doc = "Register `IER` reader"] +pub type R = crate::R; +#[doc = "Register `IER` writer"] +pub type W = crate::W; +#[doc = "Transmit Data Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDIE` reader - Transmit Data Interrupt Enable"] +pub type TdieR = crate::BitReader; +impl TdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdie { + match self.bits { + false => Tdie::Disable, + true => Tdie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tdie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tdie::Enable + } +} +#[doc = "Field `TDIE` writer - Transmit Data Interrupt Enable"] +pub type TdieW<'a, REG> = crate::BitWriter<'a, REG, Tdie>; +impl<'a, REG> TdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tdie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tdie::Enable) + } +} +#[doc = "Receive Data Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDIE` reader - Receive Data Interrupt Enable"] +pub type RdieR = crate::BitReader; +impl RdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdie { + match self.bits { + false => Rdie::Disable, + true => Rdie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rdie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rdie::Enable + } +} +#[doc = "Field `RDIE` writer - Receive Data Interrupt Enable"] +pub type RdieW<'a, REG> = crate::BitWriter<'a, REG, Rdie>; +impl<'a, REG> RdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Rdie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Rdie::Enable) + } +} +#[doc = "Word Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wcie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wcie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WCIE` reader - Word Complete Interrupt Enable"] +pub type WcieR = crate::BitReader; +impl WcieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wcie { + match self.bits { + false => Wcie::Disable, + true => Wcie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wcie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wcie::Enable + } +} +#[doc = "Field `WCIE` writer - Word Complete Interrupt Enable"] +pub type WcieW<'a, REG> = crate::BitWriter<'a, REG, Wcie>; +impl<'a, REG> WcieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wcie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wcie::Enable) + } +} +#[doc = "Frame Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fcie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fcie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FCIE` reader - Frame Complete Interrupt Enable"] +pub type FcieR = crate::BitReader; +impl FcieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fcie { + match self.bits { + false => Fcie::Disable, + true => Fcie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Fcie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Fcie::Enable + } +} +#[doc = "Field `FCIE` writer - Frame Complete Interrupt Enable"] +pub type FcieW<'a, REG> = crate::BitWriter<'a, REG, Fcie>; +impl<'a, REG> FcieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Fcie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Fcie::Enable) + } +} +#[doc = "Transfer Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tcie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tcie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCIE` reader - Transfer Complete Interrupt Enable"] +pub type TcieR = crate::BitReader; +impl TcieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcie { + match self.bits { + false => Tcie::Disable, + true => Tcie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tcie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tcie::Enable + } +} +#[doc = "Field `TCIE` writer - Transfer Complete Interrupt Enable"] +pub type TcieW<'a, REG> = crate::BitWriter<'a, REG, Tcie>; +impl<'a, REG> TcieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tcie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tcie::Enable) + } +} +#[doc = "Transmit Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Teie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Teie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEIE` reader - Transmit Error Interrupt Enable"] +pub type TeieR = crate::BitReader; +impl TeieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Teie { + match self.bits { + false => Teie::Disable, + true => Teie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Teie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Teie::Enable + } +} +#[doc = "Field `TEIE` writer - Transmit Error Interrupt Enable"] +pub type TeieW<'a, REG> = crate::BitWriter<'a, REG, Teie>; +impl<'a, REG> TeieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Teie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Teie::Enable) + } +} +#[doc = "Receive Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REIE` reader - Receive Error Interrupt Enable"] +pub type ReieR = crate::BitReader; +impl ReieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reie { + match self.bits { + false => Reie::Disable, + true => Reie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Reie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Reie::Enable + } +} +#[doc = "Field `REIE` writer - Receive Error Interrupt Enable"] +pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; +impl<'a, REG> ReieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Reie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Reie::Enable) + } +} +#[doc = "Data Match Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMIE` reader - Data Match Interrupt Enable"] +pub type DmieR = crate::BitReader; +impl DmieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmie { + match self.bits { + false => Dmie::Disable, + true => Dmie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Dmie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dmie::Enable + } +} +#[doc = "Field `DMIE` writer - Data Match Interrupt Enable"] +pub type DmieW<'a, REG> = crate::BitWriter<'a, REG, Dmie>; +impl<'a, REG> DmieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Dmie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dmie::Enable) + } +} +impl R { + #[doc = "Bit 0 - Transmit Data Interrupt Enable"] + #[inline(always)] + pub fn tdie(&self) -> TdieR { + TdieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data Interrupt Enable"] + #[inline(always)] + pub fn rdie(&self) -> RdieR { + RdieR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Word Complete Interrupt Enable"] + #[inline(always)] + pub fn wcie(&self) -> WcieR { + WcieR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame Complete Interrupt Enable"] + #[inline(always)] + pub fn fcie(&self) -> FcieR { + FcieR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcie(&self) -> TcieR { + TcieR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transmit Error Interrupt Enable"] + #[inline(always)] + pub fn teie(&self) -> TeieR { + TeieR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Receive Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&self) -> ReieR { + ReieR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Data Match Interrupt Enable"] + #[inline(always)] + pub fn dmie(&self) -> DmieR { + DmieR::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Data Interrupt Enable"] + #[inline(always)] + pub fn tdie(&mut self) -> TdieW { + TdieW::new(self, 0) + } + #[doc = "Bit 1 - Receive Data Interrupt Enable"] + #[inline(always)] + pub fn rdie(&mut self) -> RdieW { + RdieW::new(self, 1) + } + #[doc = "Bit 8 - Word Complete Interrupt Enable"] + #[inline(always)] + pub fn wcie(&mut self) -> WcieW { + WcieW::new(self, 8) + } + #[doc = "Bit 9 - Frame Complete Interrupt Enable"] + #[inline(always)] + pub fn fcie(&mut self) -> FcieW { + FcieW::new(self, 9) + } + #[doc = "Bit 10 - Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcie(&mut self) -> TcieW { + TcieW::new(self, 10) + } + #[doc = "Bit 11 - Transmit Error Interrupt Enable"] + #[inline(always)] + pub fn teie(&mut self) -> TeieW { + TeieW::new(self, 11) + } + #[doc = "Bit 12 - Receive Error Interrupt Enable"] + #[inline(always)] + pub fn reie(&mut self) -> ReieW { + ReieW::new(self, 12) + } + #[doc = "Bit 13 - Data Match Interrupt Enable"] + #[inline(always)] + pub fn dmie(&mut self) -> DmieW { + DmieW::new(self, 13) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IerSpec; +impl crate::RegisterSpec for IerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IerSpec {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] +impl crate::Writable for IerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/lpspi0/param.rs b/mcxa276-pac/src/lpspi0/param.rs new file mode 100644 index 000000000..28e74a31b --- /dev/null +++ b/mcxa276-pac/src/lpspi0/param.rs @@ -0,0 +1,36 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "Field `TXFIFO` reader - Transmit FIFO Size"] +pub type TxfifoR = crate::FieldReader; +#[doc = "Field `RXFIFO` reader - Receive FIFO Size"] +pub type RxfifoR = crate::FieldReader; +#[doc = "Field `PCSNUM` reader - PCS Number"] +pub type PcsnumR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Transmit FIFO Size"] + #[inline(always)] + pub fn txfifo(&self) -> TxfifoR { + TxfifoR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Receive FIFO Size"] + #[inline(always)] + pub fn rxfifo(&self) -> RxfifoR { + RxfifoR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - PCS Number"] + #[inline(always)] + pub fn pcsnum(&self) -> PcsnumR { + PcsnumR::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x0004_0202"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x0004_0202; +} diff --git a/mcxa276-pac/src/lpspi0/rdbr.rs b/mcxa276-pac/src/lpspi0/rdbr.rs new file mode 100644 index 000000000..f36c625ee --- /dev/null +++ b/mcxa276-pac/src/lpspi0/rdbr.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RDBR[%s]` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Data"] +pub type DataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new(self.bits) + } +} +#[doc = "Receive Data Burst\n\nYou can [`read`](crate::Reg::read) this register and get [`rdbr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RdbrSpec; +impl crate::RegisterSpec for RdbrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdbr::R`](R) reader structure"] +impl crate::Readable for RdbrSpec {} +#[doc = "`reset()` method sets RDBR[%s] to value 0"] +impl crate::Resettable for RdbrSpec {} diff --git a/mcxa276-pac/src/lpspi0/rdr.rs b/mcxa276-pac/src/lpspi0/rdr.rs new file mode 100644 index 000000000..e0a814a20 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/rdr.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RDR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Receive Data"] +pub type DataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Receive Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new(self.bits) + } +} +#[doc = "Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`rdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RdrSpec; +impl crate::RegisterSpec for RdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdr::R`](R) reader structure"] +impl crate::Readable for RdrSpec {} +#[doc = "`reset()` method sets RDR to value 0"] +impl crate::Resettable for RdrSpec {} diff --git a/mcxa276-pac/src/lpspi0/rdror.rs b/mcxa276-pac/src/lpspi0/rdror.rs new file mode 100644 index 000000000..c25fcd4de --- /dev/null +++ b/mcxa276-pac/src/lpspi0/rdror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RDROR` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Receive Data"] +pub type DataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Receive Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new(self.bits) + } +} +#[doc = "Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`rdror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RdrorSpec; +impl crate::RegisterSpec for RdrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdror::R`](R) reader structure"] +impl crate::Readable for RdrorSpec {} +#[doc = "`reset()` method sets RDROR to value 0"] +impl crate::Resettable for RdrorSpec {} diff --git a/mcxa276-pac/src/lpspi0/rsr.rs b/mcxa276-pac/src/lpspi0/rsr.rs new file mode 100644 index 000000000..31a9f05cd --- /dev/null +++ b/mcxa276-pac/src/lpspi0/rsr.rs @@ -0,0 +1,97 @@ +#[doc = "Register `RSR` reader"] +pub type R = crate::R; +#[doc = "Start of Frame\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sof { + #[doc = "0: Subsequent data word or RX FIFO is empty (RXEMPTY=1)."] + NextDataword = 0, + #[doc = "1: First data word"] + FirstDataword = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOF` reader - Start of Frame"] +pub type SofR = crate::BitReader; +impl SofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sof { + match self.bits { + false => Sof::NextDataword, + true => Sof::FirstDataword, + } + } + #[doc = "Subsequent data word or RX FIFO is empty (RXEMPTY=1)."] + #[inline(always)] + pub fn is_next_dataword(&self) -> bool { + *self == Sof::NextDataword + } + #[doc = "First data word"] + #[inline(always)] + pub fn is_first_dataword(&self) -> bool { + *self == Sof::FirstDataword + } +} +#[doc = "RX FIFO Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempty { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempty) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPTY` reader - RX FIFO Empty"] +pub type RxemptyR = crate::BitReader; +impl RxemptyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempty { + match self.bits { + false => Rxempty::NotEmpty, + true => Rxempty::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempty::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempty::Empty + } +} +impl R { + #[doc = "Bit 0 - Start of Frame"] + #[inline(always)] + pub fn sof(&self) -> SofR { + SofR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX FIFO Empty"] + #[inline(always)] + pub fn rxempty(&self) -> RxemptyR { + RxemptyR::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "Receive Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RsrSpec; +impl crate::RegisterSpec for RsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rsr::R`](R) reader structure"] +impl crate::Readable for RsrSpec {} +#[doc = "`reset()` method sets RSR to value 0x02"] +impl crate::Resettable for RsrSpec { + const RESET_VALUE: u32 = 0x02; +} diff --git a/mcxa276-pac/src/lpspi0/sr.rs b/mcxa276-pac/src/lpspi0/sr.rs new file mode 100644 index 000000000..db8ad1012 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/sr.rs @@ -0,0 +1,525 @@ +#[doc = "Register `SR` reader"] +pub type R = crate::R; +#[doc = "Register `SR` writer"] +pub type W = crate::W; +#[doc = "Transmit Data Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdf { + #[doc = "0: Transmit data not requested"] + TxdataNotReqst = 0, + #[doc = "1: Transmit data requested"] + TxdataReqst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDF` reader - Transmit Data Flag"] +pub type TdfR = crate::BitReader; +impl TdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdf { + match self.bits { + false => Tdf::TxdataNotReqst, + true => Tdf::TxdataReqst, + } + } + #[doc = "Transmit data not requested"] + #[inline(always)] + pub fn is_txdata_not_reqst(&self) -> bool { + *self == Tdf::TxdataNotReqst + } + #[doc = "Transmit data requested"] + #[inline(always)] + pub fn is_txdata_reqst(&self) -> bool { + *self == Tdf::TxdataReqst + } +} +#[doc = "Receive Data Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdf { + #[doc = "0: Receive data not ready"] + Notready = 0, + #[doc = "1: Receive data ready"] + Ready = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDF` reader - Receive Data Flag"] +pub type RdfR = crate::BitReader; +impl RdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdf { + match self.bits { + false => Rdf::Notready, + true => Rdf::Ready, + } + } + #[doc = "Receive data not ready"] + #[inline(always)] + pub fn is_notready(&self) -> bool { + *self == Rdf::Notready + } + #[doc = "Receive data ready"] + #[inline(always)] + pub fn is_ready(&self) -> bool { + *self == Rdf::Ready + } +} +#[doc = "Word Complete Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wcf { + #[doc = "0: Not complete"] + NotCompleted = 0, + #[doc = "1: Complete"] + Completed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wcf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WCF` reader - Word Complete Flag"] +pub type WcfR = crate::BitReader; +impl WcfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wcf { + match self.bits { + false => Wcf::NotCompleted, + true => Wcf::Completed, + } + } + #[doc = "Not complete"] + #[inline(always)] + pub fn is_not_completed(&self) -> bool { + *self == Wcf::NotCompleted + } + #[doc = "Complete"] + #[inline(always)] + pub fn is_completed(&self) -> bool { + *self == Wcf::Completed + } +} +#[doc = "Field `WCF` writer - Word Complete Flag"] +pub type WcfW<'a, REG> = crate::BitWriter1C<'a, REG, Wcf>; +impl<'a, REG> WcfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not complete"] + #[inline(always)] + pub fn not_completed(self) -> &'a mut crate::W { + self.variant(Wcf::NotCompleted) + } + #[doc = "Complete"] + #[inline(always)] + pub fn completed(self) -> &'a mut crate::W { + self.variant(Wcf::Completed) + } +} +#[doc = "Frame Complete Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fcf { + #[doc = "0: Not complete"] + NotCompleted = 0, + #[doc = "1: Complete"] + Completed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fcf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FCF` reader - Frame Complete Flag"] +pub type FcfR = crate::BitReader; +impl FcfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fcf { + match self.bits { + false => Fcf::NotCompleted, + true => Fcf::Completed, + } + } + #[doc = "Not complete"] + #[inline(always)] + pub fn is_not_completed(&self) -> bool { + *self == Fcf::NotCompleted + } + #[doc = "Complete"] + #[inline(always)] + pub fn is_completed(&self) -> bool { + *self == Fcf::Completed + } +} +#[doc = "Field `FCF` writer - Frame Complete Flag"] +pub type FcfW<'a, REG> = crate::BitWriter1C<'a, REG, Fcf>; +impl<'a, REG> FcfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not complete"] + #[inline(always)] + pub fn not_completed(self) -> &'a mut crate::W { + self.variant(Fcf::NotCompleted) + } + #[doc = "Complete"] + #[inline(always)] + pub fn completed(self) -> &'a mut crate::W { + self.variant(Fcf::Completed) + } +} +#[doc = "Transfer Complete Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tcf { + #[doc = "0: Not complete"] + NotCompleted = 0, + #[doc = "1: Complete"] + Completed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tcf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCF` reader - Transfer Complete Flag"] +pub type TcfR = crate::BitReader; +impl TcfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcf { + match self.bits { + false => Tcf::NotCompleted, + true => Tcf::Completed, + } + } + #[doc = "Not complete"] + #[inline(always)] + pub fn is_not_completed(&self) -> bool { + *self == Tcf::NotCompleted + } + #[doc = "Complete"] + #[inline(always)] + pub fn is_completed(&self) -> bool { + *self == Tcf::Completed + } +} +#[doc = "Field `TCF` writer - Transfer Complete Flag"] +pub type TcfW<'a, REG> = crate::BitWriter1C<'a, REG, Tcf>; +impl<'a, REG> TcfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not complete"] + #[inline(always)] + pub fn not_completed(self) -> &'a mut crate::W { + self.variant(Tcf::NotCompleted) + } + #[doc = "Complete"] + #[inline(always)] + pub fn completed(self) -> &'a mut crate::W { + self.variant(Tcf::Completed) + } +} +#[doc = "Transmit Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tef { + #[doc = "0: No underrun"] + NoUnderrun = 0, + #[doc = "1: Underrun"] + Underrun = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tef) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEF` reader - Transmit Error Flag"] +pub type TefR = crate::BitReader; +impl TefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tef { + match self.bits { + false => Tef::NoUnderrun, + true => Tef::Underrun, + } + } + #[doc = "No underrun"] + #[inline(always)] + pub fn is_no_underrun(&self) -> bool { + *self == Tef::NoUnderrun + } + #[doc = "Underrun"] + #[inline(always)] + pub fn is_underrun(&self) -> bool { + *self == Tef::Underrun + } +} +#[doc = "Field `TEF` writer - Transmit Error Flag"] +pub type TefW<'a, REG> = crate::BitWriter1C<'a, REG, Tef>; +impl<'a, REG> TefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No underrun"] + #[inline(always)] + pub fn no_underrun(self) -> &'a mut crate::W { + self.variant(Tef::NoUnderrun) + } + #[doc = "Underrun"] + #[inline(always)] + pub fn underrun(self) -> &'a mut crate::W { + self.variant(Tef::Underrun) + } +} +#[doc = "Receive Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ref { + #[doc = "0: No overflow"] + NotOverflowed = 0, + #[doc = "1: Overflow"] + Overflowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ref) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REF` reader - Receive Error Flag"] +pub type RefR = crate::BitReader; +impl RefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ref { + match self.bits { + false => Ref::NotOverflowed, + true => Ref::Overflowed, + } + } + #[doc = "No overflow"] + #[inline(always)] + pub fn is_not_overflowed(&self) -> bool { + *self == Ref::NotOverflowed + } + #[doc = "Overflow"] + #[inline(always)] + pub fn is_overflowed(&self) -> bool { + *self == Ref::Overflowed + } +} +#[doc = "Field `REF` writer - Receive Error Flag"] +pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; +impl<'a, REG> RefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overflow"] + #[inline(always)] + pub fn not_overflowed(self) -> &'a mut crate::W { + self.variant(Ref::NotOverflowed) + } + #[doc = "Overflow"] + #[inline(always)] + pub fn overflowed(self) -> &'a mut crate::W { + self.variant(Ref::Overflowed) + } +} +#[doc = "Data Match Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmf { + #[doc = "0: No match"] + NoMatch = 0, + #[doc = "1: Match"] + Match = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMF` reader - Data Match Flag"] +pub type DmfR = crate::BitReader; +impl DmfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmf { + match self.bits { + false => Dmf::NoMatch, + true => Dmf::Match, + } + } + #[doc = "No match"] + #[inline(always)] + pub fn is_no_match(&self) -> bool { + *self == Dmf::NoMatch + } + #[doc = "Match"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Dmf::Match + } +} +#[doc = "Field `DMF` writer - Data Match Flag"] +pub type DmfW<'a, REG> = crate::BitWriter1C<'a, REG, Dmf>; +impl<'a, REG> DmfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No match"] + #[inline(always)] + pub fn no_match(self) -> &'a mut crate::W { + self.variant(Dmf::NoMatch) + } + #[doc = "Match"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Dmf::Match) + } +} +#[doc = "Module Busy Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mbf { + #[doc = "0: LPSPI is idle"] + Idle = 0, + #[doc = "1: LPSPI is busy"] + Busy = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MBF` reader - Module Busy Flag"] +pub type MbfR = crate::BitReader; +impl MbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbf { + match self.bits { + false => Mbf::Idle, + true => Mbf::Busy, + } + } + #[doc = "LPSPI is idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Mbf::Idle + } + #[doc = "LPSPI is busy"] + #[inline(always)] + pub fn is_busy(&self) -> bool { + *self == Mbf::Busy + } +} +impl R { + #[doc = "Bit 0 - Transmit Data Flag"] + #[inline(always)] + pub fn tdf(&self) -> TdfR { + TdfR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Data Flag"] + #[inline(always)] + pub fn rdf(&self) -> RdfR { + RdfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Word Complete Flag"] + #[inline(always)] + pub fn wcf(&self) -> WcfR { + WcfR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame Complete Flag"] + #[inline(always)] + pub fn fcf(&self) -> FcfR { + FcfR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Transfer Complete Flag"] + #[inline(always)] + pub fn tcf(&self) -> TcfR { + TcfR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transmit Error Flag"] + #[inline(always)] + pub fn tef(&self) -> TefR { + TefR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Receive Error Flag"] + #[inline(always)] + pub fn ref_(&self) -> RefR { + RefR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Data Match Flag"] + #[inline(always)] + pub fn dmf(&self) -> DmfR { + DmfR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 24 - Module Busy Flag"] + #[inline(always)] + pub fn mbf(&self) -> MbfR { + MbfR::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Word Complete Flag"] + #[inline(always)] + pub fn wcf(&mut self) -> WcfW { + WcfW::new(self, 8) + } + #[doc = "Bit 9 - Frame Complete Flag"] + #[inline(always)] + pub fn fcf(&mut self) -> FcfW { + FcfW::new(self, 9) + } + #[doc = "Bit 10 - Transfer Complete Flag"] + #[inline(always)] + pub fn tcf(&mut self) -> TcfW { + TcfW::new(self, 10) + } + #[doc = "Bit 11 - Transmit Error Flag"] + #[inline(always)] + pub fn tef(&mut self) -> TefW { + TefW::new(self, 11) + } + #[doc = "Bit 12 - Receive Error Flag"] + #[inline(always)] + pub fn ref_(&mut self) -> RefW { + RefW::new(self, 12) + } + #[doc = "Bit 13 - Data Match Flag"] + #[inline(always)] + pub fn dmf(&mut self) -> DmfW { + DmfW::new(self, 13) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrSpec; +impl crate::RegisterSpec for SrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SrSpec {} +#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] +impl crate::Writable for SrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f00; +} +#[doc = "`reset()` method sets SR to value 0x01"] +impl crate::Resettable for SrSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/lpspi0/tcbr.rs b/mcxa276-pac/src/lpspi0/tcbr.rs new file mode 100644 index 000000000..37c7abd61 --- /dev/null +++ b/mcxa276-pac/src/lpspi0/tcbr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TCBR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Command Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Command Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Transmit Command Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcbr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcbrSpec; +impl crate::RegisterSpec for TcbrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`tcbr::W`](W) writer structure"] +impl crate::Writable for TcbrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCBR to value 0"] +impl crate::Resettable for TcbrSpec {} diff --git a/mcxa276-pac/src/lpspi0/tcr.rs b/mcxa276-pac/src/lpspi0/tcr.rs new file mode 100644 index 000000000..6ca094c2f --- /dev/null +++ b/mcxa276-pac/src/lpspi0/tcr.rs @@ -0,0 +1,868 @@ +#[doc = "Register `TCR` reader"] +pub type R = crate::R; +#[doc = "Register `TCR` writer"] +pub type W = crate::W; +#[doc = "Field `FRAMESZ` reader - Frame Size"] +pub type FrameszR = crate::FieldReader; +#[doc = "Field `FRAMESZ` writer - Frame Size"] +pub type FrameszW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Transfer Width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Width { + #[doc = "0: 1-bit transfer"] + Onebit = 0, + #[doc = "1: 2-bit transfer"] + Twobit = 1, + #[doc = "2: 4-bit transfer"] + Fourbit = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Width) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Width { + type Ux = u8; +} +impl crate::IsEnum for Width {} +#[doc = "Field `WIDTH` reader - Transfer Width"] +pub type WidthR = crate::FieldReader; +impl WidthR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Width::Onebit), + 1 => Some(Width::Twobit), + 2 => Some(Width::Fourbit), + _ => None, + } + } + #[doc = "1-bit transfer"] + #[inline(always)] + pub fn is_onebit(&self) -> bool { + *self == Width::Onebit + } + #[doc = "2-bit transfer"] + #[inline(always)] + pub fn is_twobit(&self) -> bool { + *self == Width::Twobit + } + #[doc = "4-bit transfer"] + #[inline(always)] + pub fn is_fourbit(&self) -> bool { + *self == Width::Fourbit + } +} +#[doc = "Field `WIDTH` writer - Transfer Width"] +pub type WidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Width>; +impl<'a, REG> WidthW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1-bit transfer"] + #[inline(always)] + pub fn onebit(self) -> &'a mut crate::W { + self.variant(Width::Onebit) + } + #[doc = "2-bit transfer"] + #[inline(always)] + pub fn twobit(self) -> &'a mut crate::W { + self.variant(Width::Twobit) + } + #[doc = "4-bit transfer"] + #[inline(always)] + pub fn fourbit(self) -> &'a mut crate::W { + self.variant(Width::Fourbit) + } +} +#[doc = "Transmit Data Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txmsk { + #[doc = "0: Normal transfer"] + Normal = 0, + #[doc = "1: Mask transmit data"] + Mask = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txmsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXMSK` reader - Transmit Data Mask"] +pub type TxmskR = crate::BitReader; +impl TxmskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txmsk { + match self.bits { + false => Txmsk::Normal, + true => Txmsk::Mask, + } + } + #[doc = "Normal transfer"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == Txmsk::Normal + } + #[doc = "Mask transmit data"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + *self == Txmsk::Mask + } +} +#[doc = "Field `TXMSK` writer - Transmit Data Mask"] +pub type TxmskW<'a, REG> = crate::BitWriter<'a, REG, Txmsk>; +impl<'a, REG> TxmskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal transfer"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(Txmsk::Normal) + } + #[doc = "Mask transmit data"] + #[inline(always)] + pub fn mask(self) -> &'a mut crate::W { + self.variant(Txmsk::Mask) + } +} +#[doc = "Receive Data Mask\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxmsk { + #[doc = "0: Normal transfer"] + Normal = 0, + #[doc = "1: Mask receive data"] + Mask = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxmsk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXMSK` reader - Receive Data Mask"] +pub type RxmskR = crate::BitReader; +impl RxmskR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxmsk { + match self.bits { + false => Rxmsk::Normal, + true => Rxmsk::Mask, + } + } + #[doc = "Normal transfer"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == Rxmsk::Normal + } + #[doc = "Mask receive data"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + *self == Rxmsk::Mask + } +} +#[doc = "Field `RXMSK` writer - Receive Data Mask"] +pub type RxmskW<'a, REG> = crate::BitWriter<'a, REG, Rxmsk>; +impl<'a, REG> RxmskW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal transfer"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(Rxmsk::Normal) + } + #[doc = "Mask receive data"] + #[inline(always)] + pub fn mask(self) -> &'a mut crate::W { + self.variant(Rxmsk::Mask) + } +} +#[doc = "Continuing Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Contc { + #[doc = "0: Command word for start of new transfer"] + Start = 0, + #[doc = "1: Command word for continuing transfer"] + Continue = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Contc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CONTC` reader - Continuing Command"] +pub type ContcR = crate::BitReader; +impl ContcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Contc { + match self.bits { + false => Contc::Start, + true => Contc::Continue, + } + } + #[doc = "Command word for start of new transfer"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == Contc::Start + } + #[doc = "Command word for continuing transfer"] + #[inline(always)] + pub fn is_continue(&self) -> bool { + *self == Contc::Continue + } +} +#[doc = "Field `CONTC` writer - Continuing Command"] +pub type ContcW<'a, REG> = crate::BitWriter<'a, REG, Contc>; +impl<'a, REG> ContcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Command word for start of new transfer"] + #[inline(always)] + pub fn start(self) -> &'a mut crate::W { + self.variant(Contc::Start) + } + #[doc = "Command word for continuing transfer"] + #[inline(always)] + pub fn continue_(self) -> &'a mut crate::W { + self.variant(Contc::Continue) + } +} +#[doc = "Continuous Transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cont { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cont) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CONT` reader - Continuous Transfer"] +pub type ContR = crate::BitReader; +impl ContR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cont { + match self.bits { + false => Cont::Disabled, + true => Cont::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cont::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cont::Enabled + } +} +#[doc = "Field `CONT` writer - Continuous Transfer"] +pub type ContW<'a, REG> = crate::BitWriter<'a, REG, Cont>; +impl<'a, REG> ContW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cont::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cont::Enabled) + } +} +#[doc = "Byte Swap\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bysw { + #[doc = "0: Disable byte swap"] + Disabled = 0, + #[doc = "1: Enable byte swap"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bysw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BYSW` reader - Byte Swap"] +pub type ByswR = crate::BitReader; +impl ByswR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bysw { + match self.bits { + false => Bysw::Disabled, + true => Bysw::Enabled, + } + } + #[doc = "Disable byte swap"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Bysw::Disabled + } + #[doc = "Enable byte swap"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Bysw::Enabled + } +} +#[doc = "Field `BYSW` writer - Byte Swap"] +pub type ByswW<'a, REG> = crate::BitWriter<'a, REG, Bysw>; +impl<'a, REG> ByswW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable byte swap"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Bysw::Disabled) + } + #[doc = "Enable byte swap"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Bysw::Enabled) + } +} +#[doc = "LSB First\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lsbf { + #[doc = "0: MSB first"] + MsbFirst = 0, + #[doc = "1: LSB first"] + LsbFirst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lsbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LSBF` reader - LSB First"] +pub type LsbfR = crate::BitReader; +impl LsbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lsbf { + match self.bits { + false => Lsbf::MsbFirst, + true => Lsbf::LsbFirst, + } + } + #[doc = "MSB first"] + #[inline(always)] + pub fn is_msb_first(&self) -> bool { + *self == Lsbf::MsbFirst + } + #[doc = "LSB first"] + #[inline(always)] + pub fn is_lsb_first(&self) -> bool { + *self == Lsbf::LsbFirst + } +} +#[doc = "Field `LSBF` writer - LSB First"] +pub type LsbfW<'a, REG> = crate::BitWriter<'a, REG, Lsbf>; +impl<'a, REG> LsbfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "MSB first"] + #[inline(always)] + pub fn msb_first(self) -> &'a mut crate::W { + self.variant(Lsbf::MsbFirst) + } + #[doc = "LSB first"] + #[inline(always)] + pub fn lsb_first(self) -> &'a mut crate::W { + self.variant(Lsbf::LsbFirst) + } +} +#[doc = "Peripheral Chip Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pcs { + #[doc = "0: Transfer using PCS\\[0\\]"] + TxPcs0 = 0, + #[doc = "1: Transfer using PCS\\[1\\]"] + TxPcs1 = 1, + #[doc = "2: Transfer using PCS\\[2\\]"] + TxPcs2 = 2, + #[doc = "3: Transfer using PCS\\[3\\]"] + TxPcs3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pcs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pcs { + type Ux = u8; +} +impl crate::IsEnum for Pcs {} +#[doc = "Field `PCS` reader - Peripheral Chip Select"] +pub type PcsR = crate::FieldReader; +impl PcsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pcs { + match self.bits { + 0 => Pcs::TxPcs0, + 1 => Pcs::TxPcs1, + 2 => Pcs::TxPcs2, + 3 => Pcs::TxPcs3, + _ => unreachable!(), + } + } + #[doc = "Transfer using PCS\\[0\\]"] + #[inline(always)] + pub fn is_tx_pcs0(&self) -> bool { + *self == Pcs::TxPcs0 + } + #[doc = "Transfer using PCS\\[1\\]"] + #[inline(always)] + pub fn is_tx_pcs1(&self) -> bool { + *self == Pcs::TxPcs1 + } + #[doc = "Transfer using PCS\\[2\\]"] + #[inline(always)] + pub fn is_tx_pcs2(&self) -> bool { + *self == Pcs::TxPcs2 + } + #[doc = "Transfer using PCS\\[3\\]"] + #[inline(always)] + pub fn is_tx_pcs3(&self) -> bool { + *self == Pcs::TxPcs3 + } +} +#[doc = "Field `PCS` writer - Peripheral Chip Select"] +pub type PcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pcs, crate::Safe>; +impl<'a, REG> PcsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Transfer using PCS\\[0\\]"] + #[inline(always)] + pub fn tx_pcs0(self) -> &'a mut crate::W { + self.variant(Pcs::TxPcs0) + } + #[doc = "Transfer using PCS\\[1\\]"] + #[inline(always)] + pub fn tx_pcs1(self) -> &'a mut crate::W { + self.variant(Pcs::TxPcs1) + } + #[doc = "Transfer using PCS\\[2\\]"] + #[inline(always)] + pub fn tx_pcs2(self) -> &'a mut crate::W { + self.variant(Pcs::TxPcs2) + } + #[doc = "Transfer using PCS\\[3\\]"] + #[inline(always)] + pub fn tx_pcs3(self) -> &'a mut crate::W { + self.variant(Pcs::TxPcs3) + } +} +#[doc = "Prescaler Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Prescale { + #[doc = "0: Divide by 1"] + Divideby1 = 0, + #[doc = "1: Divide by 2"] + Divideby2 = 1, + #[doc = "2: Divide by 4"] + Divideby4 = 2, + #[doc = "3: Divide by 8"] + Divideby8 = 3, + #[doc = "4: Divide by 16"] + Divideby16 = 4, + #[doc = "5: Divide by 32"] + Divideby32 = 5, + #[doc = "6: Divide by 64"] + Divideby64 = 6, + #[doc = "7: Divide by 128"] + Divideby128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Prescale) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Prescale { + type Ux = u8; +} +impl crate::IsEnum for Prescale {} +#[doc = "Field `PRESCALE` reader - Prescaler Value"] +pub type PrescaleR = crate::FieldReader; +impl PrescaleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prescale { + match self.bits { + 0 => Prescale::Divideby1, + 1 => Prescale::Divideby2, + 2 => Prescale::Divideby4, + 3 => Prescale::Divideby8, + 4 => Prescale::Divideby16, + 5 => Prescale::Divideby32, + 6 => Prescale::Divideby64, + 7 => Prescale::Divideby128, + _ => unreachable!(), + } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn is_divideby1(&self) -> bool { + *self == Prescale::Divideby1 + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn is_divideby2(&self) -> bool { + *self == Prescale::Divideby2 + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn is_divideby4(&self) -> bool { + *self == Prescale::Divideby4 + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn is_divideby8(&self) -> bool { + *self == Prescale::Divideby8 + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn is_divideby16(&self) -> bool { + *self == Prescale::Divideby16 + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn is_divideby32(&self) -> bool { + *self == Prescale::Divideby32 + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn is_divideby64(&self) -> bool { + *self == Prescale::Divideby64 + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn is_divideby128(&self) -> bool { + *self == Prescale::Divideby128 + } +} +#[doc = "Field `PRESCALE` writer - Prescaler Value"] +pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescale, crate::Safe>; +impl<'a, REG> PrescaleW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Divide by 1"] + #[inline(always)] + pub fn divideby1(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn divideby2(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn divideby4(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn divideby8(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn divideby16(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn divideby32(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn divideby64(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn divideby128(self) -> &'a mut crate::W { + self.variant(Prescale::Divideby128) + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cpha { + #[doc = "0: Captured"] + Captured = 0, + #[doc = "1: Changed"] + Changed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cpha) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub type CphaR = crate::BitReader; +impl CphaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpha { + match self.bits { + false => Cpha::Captured, + true => Cpha::Changed, + } + } + #[doc = "Captured"] + #[inline(always)] + pub fn is_captured(&self) -> bool { + *self == Cpha::Captured + } + #[doc = "Changed"] + #[inline(always)] + pub fn is_changed(&self) -> bool { + *self == Cpha::Changed + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub type CphaW<'a, REG> = crate::BitWriter<'a, REG, Cpha>; +impl<'a, REG> CphaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Captured"] + #[inline(always)] + pub fn captured(self) -> &'a mut crate::W { + self.variant(Cpha::Captured) + } + #[doc = "Changed"] + #[inline(always)] + pub fn changed(self) -> &'a mut crate::W { + self.variant(Cpha::Changed) + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cpol { + #[doc = "0: Inactive low"] + InactiveLow = 0, + #[doc = "1: Inactive high"] + InactiveHigh = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub type CpolR = crate::BitReader; +impl CpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpol { + match self.bits { + false => Cpol::InactiveLow, + true => Cpol::InactiveHigh, + } + } + #[doc = "Inactive low"] + #[inline(always)] + pub fn is_inactive_low(&self) -> bool { + *self == Cpol::InactiveLow + } + #[doc = "Inactive high"] + #[inline(always)] + pub fn is_inactive_high(&self) -> bool { + *self == Cpol::InactiveHigh + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub type CpolW<'a, REG> = crate::BitWriter<'a, REG, Cpol>; +impl<'a, REG> CpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Inactive low"] + #[inline(always)] + pub fn inactive_low(self) -> &'a mut crate::W { + self.variant(Cpol::InactiveLow) + } + #[doc = "Inactive high"] + #[inline(always)] + pub fn inactive_high(self) -> &'a mut crate::W { + self.variant(Cpol::InactiveHigh) + } +} +impl R { + #[doc = "Bits 0:11 - Frame Size"] + #[inline(always)] + pub fn framesz(&self) -> FrameszR { + FrameszR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:17 - Transfer Width"] + #[inline(always)] + pub fn width(&self) -> WidthR { + WidthR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Transmit Data Mask"] + #[inline(always)] + pub fn txmsk(&self) -> TxmskR { + TxmskR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Receive Data Mask"] + #[inline(always)] + pub fn rxmsk(&self) -> RxmskR { + RxmskR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Continuing Command"] + #[inline(always)] + pub fn contc(&self) -> ContcR { + ContcR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Continuous Transfer"] + #[inline(always)] + pub fn cont(&self) -> ContR { + ContR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Byte Swap"] + #[inline(always)] + pub fn bysw(&self) -> ByswR { + ByswR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - LSB First"] + #[inline(always)] + pub fn lsbf(&self) -> LsbfR { + LsbfR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:25 - Peripheral Chip Select"] + #[inline(always)] + pub fn pcs(&self) -> PcsR { + PcsR::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 27:29 - Prescaler Value"] + #[inline(always)] + pub fn prescale(&self) -> PrescaleR { + PrescaleR::new(((self.bits >> 27) & 7) as u8) + } + #[doc = "Bit 30 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CphaR { + CphaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CpolR { + CpolR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:11 - Frame Size"] + #[inline(always)] + pub fn framesz(&mut self) -> FrameszW { + FrameszW::new(self, 0) + } + #[doc = "Bits 16:17 - Transfer Width"] + #[inline(always)] + pub fn width(&mut self) -> WidthW { + WidthW::new(self, 16) + } + #[doc = "Bit 18 - Transmit Data Mask"] + #[inline(always)] + pub fn txmsk(&mut self) -> TxmskW { + TxmskW::new(self, 18) + } + #[doc = "Bit 19 - Receive Data Mask"] + #[inline(always)] + pub fn rxmsk(&mut self) -> RxmskW { + RxmskW::new(self, 19) + } + #[doc = "Bit 20 - Continuing Command"] + #[inline(always)] + pub fn contc(&mut self) -> ContcW { + ContcW::new(self, 20) + } + #[doc = "Bit 21 - Continuous Transfer"] + #[inline(always)] + pub fn cont(&mut self) -> ContW { + ContW::new(self, 21) + } + #[doc = "Bit 22 - Byte Swap"] + #[inline(always)] + pub fn bysw(&mut self) -> ByswW { + ByswW::new(self, 22) + } + #[doc = "Bit 23 - LSB First"] + #[inline(always)] + pub fn lsbf(&mut self) -> LsbfW { + LsbfW::new(self, 23) + } + #[doc = "Bits 24:25 - Peripheral Chip Select"] + #[inline(always)] + pub fn pcs(&mut self) -> PcsW { + PcsW::new(self, 24) + } + #[doc = "Bits 27:29 - Prescaler Value"] + #[inline(always)] + pub fn prescale(&mut self) -> PrescaleW { + PrescaleW::new(self, 27) + } + #[doc = "Bit 30 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CphaW { + CphaW::new(self, 30) + } + #[doc = "Bit 31 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CpolW { + CpolW::new(self, 31) + } +} +#[doc = "Transmit Command\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcrSpec; +impl crate::RegisterSpec for TcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] +impl crate::Readable for TcrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] +impl crate::Writable for TcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCR to value 0x1f"] +impl crate::Resettable for TcrSpec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/mcxa276-pac/src/lpspi0/tdbr.rs b/mcxa276-pac/src/lpspi0/tdbr.rs new file mode 100644 index 000000000..de53f202e --- /dev/null +++ b/mcxa276-pac/src/lpspi0/tdbr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TDBR[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Transmit Data Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdbr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TdbrSpec; +impl crate::RegisterSpec for TdbrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`tdbr::W`](W) writer structure"] +impl crate::Writable for TdbrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TDBR[%s] to value 0"] +impl crate::Resettable for TdbrSpec {} diff --git a/mcxa276-pac/src/lpspi0/tdr.rs b/mcxa276-pac/src/lpspi0/tdr.rs new file mode 100644 index 000000000..a24e17c8e --- /dev/null +++ b/mcxa276-pac/src/lpspi0/tdr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TDR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Transmit Data"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Transmit Data"] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TdrSpec; +impl crate::RegisterSpec for TdrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"] +impl crate::Writable for TdrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TDR to value 0"] +impl crate::Resettable for TdrSpec {} diff --git a/mcxa276-pac/src/lpspi0/verid.rs b/mcxa276-pac/src/lpspi0/verid.rs new file mode 100644 index 000000000..2fff415ae --- /dev/null +++ b/mcxa276-pac/src/lpspi0/verid.rs @@ -0,0 +1,68 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Module Identification Number\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "4: Standard feature set supporting a 32-bit shift register."] + Standard = 4, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Module Identification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 4 => Some(Feature::Standard), + _ => None, + } + } + #[doc = "Standard feature set supporting a 32-bit shift register."] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == Feature::Standard + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Module Identification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0200_0004"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0200_0004; +} diff --git a/mcxa276-pac/src/lptmr0.rs b/mcxa276-pac/src/lptmr0.rs new file mode 100644 index 000000000..234310e3b --- /dev/null +++ b/mcxa276-pac/src/lptmr0.rs @@ -0,0 +1,50 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + csr: Csr, + psr: Psr, + cmr: Cmr, + cnr: Cnr, +} +impl RegisterBlock { + #[doc = "0x00 - Control Status"] + #[inline(always)] + pub const fn csr(&self) -> &Csr { + &self.csr + } + #[doc = "0x04 - Prescaler and Glitch Filter"] + #[inline(always)] + pub const fn psr(&self) -> &Psr { + &self.psr + } + #[doc = "0x08 - Compare"] + #[inline(always)] + pub const fn cmr(&self) -> &Cmr { + &self.cmr + } + #[doc = "0x0c - Counter"] + #[inline(always)] + pub const fn cnr(&self) -> &Cnr { + &self.cnr + } +} +#[doc = "CSR (rw) register accessor: Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`] module"] +#[doc(alias = "CSR")] +pub type Csr = crate::Reg; +#[doc = "Control Status"] +pub mod csr; +#[doc = "PSR (rw) register accessor: Prescaler and Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psr`] module"] +#[doc(alias = "PSR")] +pub type Psr = crate::Reg; +#[doc = "Prescaler and Glitch Filter"] +pub mod psr; +#[doc = "CMR (rw) register accessor: Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`cmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmr`] module"] +#[doc(alias = "CMR")] +pub type Cmr = crate::Reg; +#[doc = "Compare"] +pub mod cmr; +#[doc = "CNR (rw) register accessor: Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnr`] module"] +#[doc(alias = "CNR")] +pub type Cnr = crate::Reg; +#[doc = "Counter"] +pub mod cnr; diff --git a/mcxa276-pac/src/lptmr0/cmr.rs b/mcxa276-pac/src/lptmr0/cmr.rs new file mode 100644 index 000000000..c7bd5de9f --- /dev/null +++ b/mcxa276-pac/src/lptmr0/cmr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CMR` reader"] +pub type R = crate::R; +#[doc = "Register `CMR` writer"] +pub type W = crate::W; +#[doc = "Field `COMPARE` reader - Compare Value"] +pub type CompareR = crate::FieldReader; +#[doc = "Field `COMPARE` writer - Compare Value"] +pub type CompareW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn compare(&self) -> CompareR { + CompareR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn compare(&mut self) -> CompareW { + CompareW::new(self, 0) + } +} +#[doc = "Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`cmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CmrSpec; +impl crate::RegisterSpec for CmrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmr::R`](R) reader structure"] +impl crate::Readable for CmrSpec {} +#[doc = "`write(|w| ..)` method takes [`cmr::W`](W) writer structure"] +impl crate::Writable for CmrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMR to value 0"] +impl crate::Resettable for CmrSpec {} diff --git a/mcxa276-pac/src/lptmr0/cnr.rs b/mcxa276-pac/src/lptmr0/cnr.rs new file mode 100644 index 000000000..ea79ccf62 --- /dev/null +++ b/mcxa276-pac/src/lptmr0/cnr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CNR` reader"] +pub type R = crate::R; +#[doc = "Register `CNR` writer"] +pub type W = crate::W; +#[doc = "Field `COUNTER` reader - Counter Value"] +pub type CounterR = crate::FieldReader; +#[doc = "Field `COUNTER` writer - Counter Value"] +pub type CounterW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn counter(&self) -> CounterR { + CounterR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn counter(&mut self) -> CounterW { + CounterW::new(self, 0) + } +} +#[doc = "Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnrSpec; +impl crate::RegisterSpec for CnrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnr::R`](R) reader structure"] +impl crate::Readable for CnrSpec {} +#[doc = "`write(|w| ..)` method takes [`cnr::W`](W) writer structure"] +impl crate::Writable for CnrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNR to value 0"] +impl crate::Resettable for CnrSpec {} diff --git a/mcxa276-pac/src/lptmr0/csr.rs b/mcxa276-pac/src/lptmr0/csr.rs new file mode 100644 index 000000000..5f7b95786 --- /dev/null +++ b/mcxa276-pac/src/lptmr0/csr.rs @@ -0,0 +1,559 @@ +#[doc = "Register `CSR` reader"] +pub type R = crate::R; +#[doc = "Register `CSR` writer"] +pub type W = crate::W; +#[doc = "Timer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ten { + #[doc = "0: Disable"] + Ten0 = 0, + #[doc = "1: Enable"] + Ten1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEN` reader - Timer Enable"] +pub type TenR = crate::BitReader; +impl TenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ten { + match self.bits { + false => Ten::Ten0, + true => Ten::Ten1, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_ten0(&self) -> bool { + *self == Ten::Ten0 + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_ten1(&self) -> bool { + *self == Ten::Ten1 + } +} +#[doc = "Field `TEN` writer - Timer Enable"] +pub type TenW<'a, REG> = crate::BitWriter<'a, REG, Ten>; +impl<'a, REG> TenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn ten0(self) -> &'a mut crate::W { + self.variant(Ten::Ten0) + } + #[doc = "Enable"] + #[inline(always)] + pub fn ten1(self) -> &'a mut crate::W { + self.variant(Ten::Ten1) + } +} +#[doc = "Timer Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tms { + #[doc = "0: Time Counter"] + Tms0 = 0, + #[doc = "1: Pulse Counter"] + Tms1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tms) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TMS` reader - Timer Mode Select"] +pub type TmsR = crate::BitReader; +impl TmsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tms { + match self.bits { + false => Tms::Tms0, + true => Tms::Tms1, + } + } + #[doc = "Time Counter"] + #[inline(always)] + pub fn is_tms0(&self) -> bool { + *self == Tms::Tms0 + } + #[doc = "Pulse Counter"] + #[inline(always)] + pub fn is_tms1(&self) -> bool { + *self == Tms::Tms1 + } +} +#[doc = "Field `TMS` writer - Timer Mode Select"] +pub type TmsW<'a, REG> = crate::BitWriter<'a, REG, Tms>; +impl<'a, REG> TmsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Time Counter"] + #[inline(always)] + pub fn tms0(self) -> &'a mut crate::W { + self.variant(Tms::Tms0) + } + #[doc = "Pulse Counter"] + #[inline(always)] + pub fn tms1(self) -> &'a mut crate::W { + self.variant(Tms::Tms1) + } +} +#[doc = "Timer Free-Running Counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tfc { + #[doc = "0: Reset when TCF asserts"] + Tfc0 = 0, + #[doc = "1: Reset on overflow"] + Tfc1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tfc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFC` reader - Timer Free-Running Counter"] +pub type TfcR = crate::BitReader; +impl TfcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tfc { + match self.bits { + false => Tfc::Tfc0, + true => Tfc::Tfc1, + } + } + #[doc = "Reset when TCF asserts"] + #[inline(always)] + pub fn is_tfc0(&self) -> bool { + *self == Tfc::Tfc0 + } + #[doc = "Reset on overflow"] + #[inline(always)] + pub fn is_tfc1(&self) -> bool { + *self == Tfc::Tfc1 + } +} +#[doc = "Field `TFC` writer - Timer Free-Running Counter"] +pub type TfcW<'a, REG> = crate::BitWriter<'a, REG, Tfc>; +impl<'a, REG> TfcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reset when TCF asserts"] + #[inline(always)] + pub fn tfc0(self) -> &'a mut crate::W { + self.variant(Tfc::Tfc0) + } + #[doc = "Reset on overflow"] + #[inline(always)] + pub fn tfc1(self) -> &'a mut crate::W { + self.variant(Tfc::Tfc1) + } +} +#[doc = "Timer Pin Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpp { + #[doc = "0: Active-high"] + Tpp0 = 0, + #[doc = "1: Active-low"] + Tpp1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPP` reader - Timer Pin Polarity"] +pub type TppR = crate::BitReader; +impl TppR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpp { + match self.bits { + false => Tpp::Tpp0, + true => Tpp::Tpp1, + } + } + #[doc = "Active-high"] + #[inline(always)] + pub fn is_tpp0(&self) -> bool { + *self == Tpp::Tpp0 + } + #[doc = "Active-low"] + #[inline(always)] + pub fn is_tpp1(&self) -> bool { + *self == Tpp::Tpp1 + } +} +#[doc = "Field `TPP` writer - Timer Pin Polarity"] +pub type TppW<'a, REG> = crate::BitWriter<'a, REG, Tpp>; +impl<'a, REG> TppW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active-high"] + #[inline(always)] + pub fn tpp0(self) -> &'a mut crate::W { + self.variant(Tpp::Tpp0) + } + #[doc = "Active-low"] + #[inline(always)] + pub fn tpp1(self) -> &'a mut crate::W { + self.variant(Tpp::Tpp1) + } +} +#[doc = "Timer Pin Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tps { + #[doc = "0: Input 0"] + Tps00 = 0, + #[doc = "1: Input 1"] + Tps01 = 1, + #[doc = "2: Input 2"] + Tps10 = 2, + #[doc = "3: Input 3"] + Tps11 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tps) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tps { + type Ux = u8; +} +impl crate::IsEnum for Tps {} +#[doc = "Field `TPS` reader - Timer Pin Select"] +pub type TpsR = crate::FieldReader; +impl TpsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tps { + match self.bits { + 0 => Tps::Tps00, + 1 => Tps::Tps01, + 2 => Tps::Tps10, + 3 => Tps::Tps11, + _ => unreachable!(), + } + } + #[doc = "Input 0"] + #[inline(always)] + pub fn is_tps00(&self) -> bool { + *self == Tps::Tps00 + } + #[doc = "Input 1"] + #[inline(always)] + pub fn is_tps01(&self) -> bool { + *self == Tps::Tps01 + } + #[doc = "Input 2"] + #[inline(always)] + pub fn is_tps10(&self) -> bool { + *self == Tps::Tps10 + } + #[doc = "Input 3"] + #[inline(always)] + pub fn is_tps11(&self) -> bool { + *self == Tps::Tps11 + } +} +#[doc = "Field `TPS` writer - Timer Pin Select"] +pub type TpsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tps, crate::Safe>; +impl<'a, REG> TpsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Input 0"] + #[inline(always)] + pub fn tps00(self) -> &'a mut crate::W { + self.variant(Tps::Tps00) + } + #[doc = "Input 1"] + #[inline(always)] + pub fn tps01(self) -> &'a mut crate::W { + self.variant(Tps::Tps01) + } + #[doc = "Input 2"] + #[inline(always)] + pub fn tps10(self) -> &'a mut crate::W { + self.variant(Tps::Tps10) + } + #[doc = "Input 3"] + #[inline(always)] + pub fn tps11(self) -> &'a mut crate::W { + self.variant(Tps::Tps11) + } +} +#[doc = "Timer Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie { + #[doc = "0: Disable"] + Tie0 = 0, + #[doc = "1: Enable"] + Tie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE` reader - Timer Interrupt Enable"] +pub type TieR = crate::BitReader; +impl TieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie { + match self.bits { + false => Tie::Tie0, + true => Tie::Tie1, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_tie0(&self) -> bool { + *self == Tie::Tie0 + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_tie1(&self) -> bool { + *self == Tie::Tie1 + } +} +#[doc = "Field `TIE` writer - Timer Interrupt Enable"] +pub type TieW<'a, REG> = crate::BitWriter<'a, REG, Tie>; +impl<'a, REG> TieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn tie0(self) -> &'a mut crate::W { + self.variant(Tie::Tie0) + } + #[doc = "Enable"] + #[inline(always)] + pub fn tie1(self) -> &'a mut crate::W { + self.variant(Tie::Tie1) + } +} +#[doc = "Timer Compare Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tcf { + #[doc = "0: CNR != (CMR + 1)"] + Tcf0 = 0, + #[doc = "1: CNR = (CMR + 1)"] + Tcf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tcf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCF` reader - Timer Compare Flag"] +pub type TcfR = crate::BitReader; +impl TcfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcf { + match self.bits { + false => Tcf::Tcf0, + true => Tcf::Tcf1, + } + } + #[doc = "CNR != (CMR + 1)"] + #[inline(always)] + pub fn is_tcf0(&self) -> bool { + *self == Tcf::Tcf0 + } + #[doc = "CNR = (CMR + 1)"] + #[inline(always)] + pub fn is_tcf1(&self) -> bool { + *self == Tcf::Tcf1 + } +} +#[doc = "Field `TCF` writer - Timer Compare Flag"] +pub type TcfW<'a, REG> = crate::BitWriter1C<'a, REG, Tcf>; +impl<'a, REG> TcfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CNR != (CMR + 1)"] + #[inline(always)] + pub fn tcf0(self) -> &'a mut crate::W { + self.variant(Tcf::Tcf0) + } + #[doc = "CNR = (CMR + 1)"] + #[inline(always)] + pub fn tcf1(self) -> &'a mut crate::W { + self.variant(Tcf::Tcf1) + } +} +#[doc = "Timer DMA Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdre { + #[doc = "0: Disable"] + Trde0 = 0, + #[doc = "1: Enable"] + Trde1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDRE` reader - Timer DMA Request Enable"] +pub type TdreR = crate::BitReader; +impl TdreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdre { + match self.bits { + false => Tdre::Trde0, + true => Tdre::Trde1, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_trde0(&self) -> bool { + *self == Tdre::Trde0 + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_trde1(&self) -> bool { + *self == Tdre::Trde1 + } +} +#[doc = "Field `TDRE` writer - Timer DMA Request Enable"] +pub type TdreW<'a, REG> = crate::BitWriter<'a, REG, Tdre>; +impl<'a, REG> TdreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn trde0(self) -> &'a mut crate::W { + self.variant(Tdre::Trde0) + } + #[doc = "Enable"] + #[inline(always)] + pub fn trde1(self) -> &'a mut crate::W { + self.variant(Tdre::Trde1) + } +} +impl R { + #[doc = "Bit 0 - Timer Enable"] + #[inline(always)] + pub fn ten(&self) -> TenR { + TenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer Mode Select"] + #[inline(always)] + pub fn tms(&self) -> TmsR { + TmsR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer Free-Running Counter"] + #[inline(always)] + pub fn tfc(&self) -> TfcR { + TfcR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer Pin Polarity"] + #[inline(always)] + pub fn tpp(&self) -> TppR { + TppR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Timer Pin Select"] + #[inline(always)] + pub fn tps(&self) -> TpsR { + TpsR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Timer Interrupt Enable"] + #[inline(always)] + pub fn tie(&self) -> TieR { + TieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Timer Compare Flag"] + #[inline(always)] + pub fn tcf(&self) -> TcfR { + TcfR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Timer DMA Request Enable"] + #[inline(always)] + pub fn tdre(&self) -> TdreR { + TdreR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer Enable"] + #[inline(always)] + pub fn ten(&mut self) -> TenW { + TenW::new(self, 0) + } + #[doc = "Bit 1 - Timer Mode Select"] + #[inline(always)] + pub fn tms(&mut self) -> TmsW { + TmsW::new(self, 1) + } + #[doc = "Bit 2 - Timer Free-Running Counter"] + #[inline(always)] + pub fn tfc(&mut self) -> TfcW { + TfcW::new(self, 2) + } + #[doc = "Bit 3 - Timer Pin Polarity"] + #[inline(always)] + pub fn tpp(&mut self) -> TppW { + TppW::new(self, 3) + } + #[doc = "Bits 4:5 - Timer Pin Select"] + #[inline(always)] + pub fn tps(&mut self) -> TpsW { + TpsW::new(self, 4) + } + #[doc = "Bit 6 - Timer Interrupt Enable"] + #[inline(always)] + pub fn tie(&mut self) -> TieW { + TieW::new(self, 6) + } + #[doc = "Bit 7 - Timer Compare Flag"] + #[inline(always)] + pub fn tcf(&mut self) -> TcfW { + TcfW::new(self, 7) + } + #[doc = "Bit 8 - Timer DMA Request Enable"] + #[inline(always)] + pub fn tdre(&mut self) -> TdreW { + TdreW::new(self, 8) + } +} +#[doc = "Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CsrSpec; +impl crate::RegisterSpec for CsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CsrSpec {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] +impl crate::Writable for CsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x80; +} +#[doc = "`reset()` method sets CSR to value 0"] +impl crate::Resettable for CsrSpec {} diff --git a/mcxa276-pac/src/lptmr0/psr.rs b/mcxa276-pac/src/lptmr0/psr.rs new file mode 100644 index 000000000..2bfca7657 --- /dev/null +++ b/mcxa276-pac/src/lptmr0/psr.rs @@ -0,0 +1,432 @@ +#[doc = "Register `PSR` reader"] +pub type R = crate::R; +#[doc = "Register `PSR` writer"] +pub type W = crate::W; +#[doc = "Prescaler and Glitch Filter Clock Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pcs { + #[doc = "0: Clock 0"] + Pcs00 = 0, + #[doc = "1: Clock 1"] + Pcs01 = 1, + #[doc = "2: Clock 2"] + Pcs10 = 2, + #[doc = "3: Clock 3"] + Pcs11 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pcs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pcs { + type Ux = u8; +} +impl crate::IsEnum for Pcs {} +#[doc = "Field `PCS` reader - Prescaler and Glitch Filter Clock Select"] +pub type PcsR = crate::FieldReader; +impl PcsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pcs { + match self.bits { + 0 => Pcs::Pcs00, + 1 => Pcs::Pcs01, + 2 => Pcs::Pcs10, + 3 => Pcs::Pcs11, + _ => unreachable!(), + } + } + #[doc = "Clock 0"] + #[inline(always)] + pub fn is_pcs00(&self) -> bool { + *self == Pcs::Pcs00 + } + #[doc = "Clock 1"] + #[inline(always)] + pub fn is_pcs01(&self) -> bool { + *self == Pcs::Pcs01 + } + #[doc = "Clock 2"] + #[inline(always)] + pub fn is_pcs10(&self) -> bool { + *self == Pcs::Pcs10 + } + #[doc = "Clock 3"] + #[inline(always)] + pub fn is_pcs11(&self) -> bool { + *self == Pcs::Pcs11 + } +} +#[doc = "Field `PCS` writer - Prescaler and Glitch Filter Clock Select"] +pub type PcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pcs, crate::Safe>; +impl<'a, REG> PcsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Clock 0"] + #[inline(always)] + pub fn pcs00(self) -> &'a mut crate::W { + self.variant(Pcs::Pcs00) + } + #[doc = "Clock 1"] + #[inline(always)] + pub fn pcs01(self) -> &'a mut crate::W { + self.variant(Pcs::Pcs01) + } + #[doc = "Clock 2"] + #[inline(always)] + pub fn pcs10(self) -> &'a mut crate::W { + self.variant(Pcs::Pcs10) + } + #[doc = "Clock 3"] + #[inline(always)] + pub fn pcs11(self) -> &'a mut crate::W { + self.variant(Pcs::Pcs11) + } +} +#[doc = "Prescaler and Glitch Filter Bypass\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pbyp { + #[doc = "0: Prescaler and glitch filter enable"] + Pbyp0 = 0, + #[doc = "1: Prescaler and glitch filter bypass"] + Pbyp1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pbyp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PBYP` reader - Prescaler and Glitch Filter Bypass"] +pub type PbypR = crate::BitReader; +impl PbypR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pbyp { + match self.bits { + false => Pbyp::Pbyp0, + true => Pbyp::Pbyp1, + } + } + #[doc = "Prescaler and glitch filter enable"] + #[inline(always)] + pub fn is_pbyp0(&self) -> bool { + *self == Pbyp::Pbyp0 + } + #[doc = "Prescaler and glitch filter bypass"] + #[inline(always)] + pub fn is_pbyp1(&self) -> bool { + *self == Pbyp::Pbyp1 + } +} +#[doc = "Field `PBYP` writer - Prescaler and Glitch Filter Bypass"] +pub type PbypW<'a, REG> = crate::BitWriter<'a, REG, Pbyp>; +impl<'a, REG> PbypW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Prescaler and glitch filter enable"] + #[inline(always)] + pub fn pbyp0(self) -> &'a mut crate::W { + self.variant(Pbyp::Pbyp0) + } + #[doc = "Prescaler and glitch filter bypass"] + #[inline(always)] + pub fn pbyp1(self) -> &'a mut crate::W { + self.variant(Pbyp::Pbyp1) + } +} +#[doc = "Prescaler and Glitch Filter Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Prescale { + #[doc = "0: Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"] + Prescale0000 = 0, + #[doc = "1: Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"] + Prescale0001 = 1, + #[doc = "2: Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"] + Prescale0010 = 2, + #[doc = "3: Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"] + Prescale0011 = 3, + #[doc = "4: Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"] + Prescale0100 = 4, + #[doc = "5: Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"] + Prescale0101 = 5, + #[doc = "6: Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"] + Prescale0110 = 6, + #[doc = "7: Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"] + Prescale0111 = 7, + #[doc = "8: Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"] + Prescale1000 = 8, + #[doc = "9: Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"] + Prescale1001 = 9, + #[doc = "10: Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"] + Prescale1010 = 10, + #[doc = "11: Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"] + Prescale1011 = 11, + #[doc = "12: Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"] + Prescale1100 = 12, + #[doc = "13: Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"] + Prescale1101 = 13, + #[doc = "14: Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"] + Prescale1110 = 14, + #[doc = "15: Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"] + Prescale1111 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Prescale) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Prescale { + type Ux = u8; +} +impl crate::IsEnum for Prescale {} +#[doc = "Field `PRESCALE` reader - Prescaler and Glitch Filter Value"] +pub type PrescaleR = crate::FieldReader; +impl PrescaleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prescale { + match self.bits { + 0 => Prescale::Prescale0000, + 1 => Prescale::Prescale0001, + 2 => Prescale::Prescale0010, + 3 => Prescale::Prescale0011, + 4 => Prescale::Prescale0100, + 5 => Prescale::Prescale0101, + 6 => Prescale::Prescale0110, + 7 => Prescale::Prescale0111, + 8 => Prescale::Prescale1000, + 9 => Prescale::Prescale1001, + 10 => Prescale::Prescale1010, + 11 => Prescale::Prescale1011, + 12 => Prescale::Prescale1100, + 13 => Prescale::Prescale1101, + 14 => Prescale::Prescale1110, + 15 => Prescale::Prescale1111, + _ => unreachable!(), + } + } + #[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"] + #[inline(always)] + pub fn is_prescale0000(&self) -> bool { + *self == Prescale::Prescale0000 + } + #[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"] + #[inline(always)] + pub fn is_prescale0001(&self) -> bool { + *self == Prescale::Prescale0001 + } + #[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"] + #[inline(always)] + pub fn is_prescale0010(&self) -> bool { + *self == Prescale::Prescale0010 + } + #[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"] + #[inline(always)] + pub fn is_prescale0011(&self) -> bool { + *self == Prescale::Prescale0011 + } + #[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"] + #[inline(always)] + pub fn is_prescale0100(&self) -> bool { + *self == Prescale::Prescale0100 + } + #[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"] + #[inline(always)] + pub fn is_prescale0101(&self) -> bool { + *self == Prescale::Prescale0101 + } + #[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"] + #[inline(always)] + pub fn is_prescale0110(&self) -> bool { + *self == Prescale::Prescale0110 + } + #[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"] + #[inline(always)] + pub fn is_prescale0111(&self) -> bool { + *self == Prescale::Prescale0111 + } + #[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"] + #[inline(always)] + pub fn is_prescale1000(&self) -> bool { + *self == Prescale::Prescale1000 + } + #[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"] + #[inline(always)] + pub fn is_prescale1001(&self) -> bool { + *self == Prescale::Prescale1001 + } + #[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"] + #[inline(always)] + pub fn is_prescale1010(&self) -> bool { + *self == Prescale::Prescale1010 + } + #[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"] + #[inline(always)] + pub fn is_prescale1011(&self) -> bool { + *self == Prescale::Prescale1011 + } + #[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"] + #[inline(always)] + pub fn is_prescale1100(&self) -> bool { + *self == Prescale::Prescale1100 + } + #[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"] + #[inline(always)] + pub fn is_prescale1101(&self) -> bool { + *self == Prescale::Prescale1101 + } + #[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"] + #[inline(always)] + pub fn is_prescale1110(&self) -> bool { + *self == Prescale::Prescale1110 + } + #[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"] + #[inline(always)] + pub fn is_prescale1111(&self) -> bool { + *self == Prescale::Prescale1111 + } +} +#[doc = "Field `PRESCALE` writer - Prescaler and Glitch Filter Value"] +pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescale, crate::Safe>; +impl<'a, REG> PrescaleW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"] + #[inline(always)] + pub fn prescale0000(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0000) + } + #[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"] + #[inline(always)] + pub fn prescale0001(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0001) + } + #[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"] + #[inline(always)] + pub fn prescale0010(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0010) + } + #[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"] + #[inline(always)] + pub fn prescale0011(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0011) + } + #[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"] + #[inline(always)] + pub fn prescale0100(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0100) + } + #[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"] + #[inline(always)] + pub fn prescale0101(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0101) + } + #[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"] + #[inline(always)] + pub fn prescale0110(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0110) + } + #[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"] + #[inline(always)] + pub fn prescale0111(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale0111) + } + #[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"] + #[inline(always)] + pub fn prescale1000(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1000) + } + #[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"] + #[inline(always)] + pub fn prescale1001(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1001) + } + #[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"] + #[inline(always)] + pub fn prescale1010(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1010) + } + #[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"] + #[inline(always)] + pub fn prescale1011(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1011) + } + #[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"] + #[inline(always)] + pub fn prescale1100(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1100) + } + #[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"] + #[inline(always)] + pub fn prescale1101(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1101) + } + #[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"] + #[inline(always)] + pub fn prescale1110(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1110) + } + #[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"] + #[inline(always)] + pub fn prescale1111(self) -> &'a mut crate::W { + self.variant(Prescale::Prescale1111) + } +} +impl R { + #[doc = "Bits 0:1 - Prescaler and Glitch Filter Clock Select"] + #[inline(always)] + pub fn pcs(&self) -> PcsR { + PcsR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Prescaler and Glitch Filter Bypass"] + #[inline(always)] + pub fn pbyp(&self) -> PbypR { + PbypR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - Prescaler and Glitch Filter Value"] + #[inline(always)] + pub fn prescale(&self) -> PrescaleR { + PrescaleR::new(((self.bits >> 3) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Prescaler and Glitch Filter Clock Select"] + #[inline(always)] + pub fn pcs(&mut self) -> PcsW { + PcsW::new(self, 0) + } + #[doc = "Bit 2 - Prescaler and Glitch Filter Bypass"] + #[inline(always)] + pub fn pbyp(&mut self) -> PbypW { + PbypW::new(self, 2) + } + #[doc = "Bits 3:6 - Prescaler and Glitch Filter Value"] + #[inline(always)] + pub fn prescale(&mut self) -> PrescaleW { + PrescaleW::new(self, 3) + } +} +#[doc = "Prescaler and Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PsrSpec; +impl crate::RegisterSpec for PsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`psr::R`](R) reader structure"] +impl crate::Readable for PsrSpec {} +#[doc = "`write(|w| ..)` method takes [`psr::W`](W) writer structure"] +impl crate::Writable for PsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PSR to value 0"] +impl crate::Resettable for PsrSpec {} diff --git a/mcxa276-pac/src/lpuart0.rs b/mcxa276-pac/src/lpuart0.rs new file mode 100644 index 000000000..e27eba504 --- /dev/null +++ b/mcxa276-pac/src/lpuart0.rs @@ -0,0 +1,149 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + global: Global, + pincfg: Pincfg, + baud: Baud, + stat: Stat, + ctrl: Ctrl, + data: Data, + match_: Match, + modir: Modir, + fifo: Fifo, + water: Water, + dataro: Dataro, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x08 - Global"] + #[inline(always)] + pub const fn global(&self) -> &Global { + &self.global + } + #[doc = "0x0c - Pin Configuration"] + #[inline(always)] + pub const fn pincfg(&self) -> &Pincfg { + &self.pincfg + } + #[doc = "0x10 - Baud Rate"] + #[inline(always)] + pub const fn baud(&self) -> &Baud { + &self.baud + } + #[doc = "0x14 - Status"] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } + #[doc = "0x18 - Control"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x1c - Data"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x20 - Match Address"] + #[inline(always)] + pub const fn match_(&self) -> &Match { + &self.match_ + } + #[doc = "0x24 - MODEM IrDA"] + #[inline(always)] + pub const fn modir(&self) -> &Modir { + &self.modir + } + #[doc = "0x28 - FIFO"] + #[inline(always)] + pub const fn fifo(&self) -> &Fifo { + &self.fifo + } + #[doc = "0x2c - Watermark"] + #[inline(always)] + pub const fn water(&self) -> &Water { + &self.water + } + #[doc = "0x30 - Data Read-Only"] + #[inline(always)] + pub const fn dataro(&self) -> &Dataro { + &self.dataro + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "GLOBAL (rw) register accessor: Global\n\nYou can [`read`](crate::Reg::read) this register and get [`global::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@global`] module"] +#[doc(alias = "GLOBAL")] +pub type Global = crate::Reg; +#[doc = "Global"] +pub mod global; +#[doc = "PINCFG (rw) register accessor: Pin Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pincfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pincfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pincfg`] module"] +#[doc(alias = "PINCFG")] +pub type Pincfg = crate::Reg; +#[doc = "Pin Configuration"] +pub mod pincfg; +#[doc = "BAUD (rw) register accessor: Baud Rate\n\nYou can [`read`](crate::Reg::read) this register and get [`baud::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud`] module"] +#[doc(alias = "BAUD")] +pub type Baud = crate::Reg; +#[doc = "Baud Rate"] +pub mod baud; +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "DATA (rw) register accessor: Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "MATCH (rw) register accessor: Match Address\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_`] module"] +#[doc(alias = "MATCH")] +pub type Match = crate::Reg; +#[doc = "Match Address"] +pub mod match_; +#[doc = "MODIR (rw) register accessor: MODEM IrDA\n\nYou can [`read`](crate::Reg::read) this register and get [`modir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modir`] module"] +#[doc(alias = "MODIR")] +pub type Modir = crate::Reg; +#[doc = "MODEM IrDA"] +pub mod modir; +#[doc = "FIFO (rw) register accessor: FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] module"] +#[doc(alias = "FIFO")] +pub type Fifo = crate::Reg; +#[doc = "FIFO"] +pub mod fifo; +#[doc = "WATER (rw) register accessor: Watermark\n\nYou can [`read`](crate::Reg::read) this register and get [`water::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`water::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@water`] module"] +#[doc(alias = "WATER")] +pub type Water = crate::Reg; +#[doc = "Watermark"] +pub mod water; +#[doc = "DATARO (r) register accessor: Data Read-Only\n\nYou can [`read`](crate::Reg::read) this register and get [`dataro::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataro`] module"] +#[doc(alias = "DATARO")] +pub type Dataro = crate::Reg; +#[doc = "Data Read-Only"] +pub mod dataro; diff --git a/mcxa276-pac/src/lpuart0/baud.rs b/mcxa276-pac/src/lpuart0/baud.rs new file mode 100644 index 000000000..6329f14dd --- /dev/null +++ b/mcxa276-pac/src/lpuart0/baud.rs @@ -0,0 +1,1260 @@ +#[doc = "Register `BAUD` reader"] +pub type R = crate::R; +#[doc = "Register `BAUD` writer"] +pub type W = crate::W; +#[doc = "Field `SBR` reader - Baud Rate Modulo Divisor"] +pub type SbrR = crate::FieldReader; +#[doc = "Field `SBR` writer - Baud Rate Modulo Divisor"] +pub type SbrW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Stop Bit Number Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbns { + #[doc = "0: One stop bit"] + One = 0, + #[doc = "1: Two stop bits"] + Two = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbns) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBNS` reader - Stop Bit Number Select"] +pub type SbnsR = crate::BitReader; +impl SbnsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbns { + match self.bits { + false => Sbns::One, + true => Sbns::Two, + } + } + #[doc = "One stop bit"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Sbns::One + } + #[doc = "Two stop bits"] + #[inline(always)] + pub fn is_two(&self) -> bool { + *self == Sbns::Two + } +} +#[doc = "Field `SBNS` writer - Stop Bit Number Select"] +pub type SbnsW<'a, REG> = crate::BitWriter<'a, REG, Sbns>; +impl<'a, REG> SbnsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "One stop bit"] + #[inline(always)] + pub fn one(self) -> &'a mut crate::W { + self.variant(Sbns::One) + } + #[doc = "Two stop bits"] + #[inline(always)] + pub fn two(self) -> &'a mut crate::W { + self.variant(Sbns::Two) + } +} +#[doc = "RX Input Active Edge Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxedgie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxedgie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEDGIE` reader - RX Input Active Edge Interrupt Enable"] +pub type RxedgieR = crate::BitReader; +impl RxedgieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxedgie { + match self.bits { + false => Rxedgie::Disable, + true => Rxedgie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rxedgie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rxedgie::Enable + } +} +#[doc = "Field `RXEDGIE` writer - RX Input Active Edge Interrupt Enable"] +pub type RxedgieW<'a, REG> = crate::BitWriter<'a, REG, Rxedgie>; +impl<'a, REG> RxedgieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Rxedgie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Rxedgie::Enable) + } +} +#[doc = "LIN Break Detect Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lbkdie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lbkdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LBKDIE` reader - LIN Break Detect Interrupt Enable"] +pub type LbkdieR = crate::BitReader; +impl LbkdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lbkdie { + match self.bits { + false => Lbkdie::Disable, + true => Lbkdie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lbkdie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lbkdie::Enable + } +} +#[doc = "Field `LBKDIE` writer - LIN Break Detect Interrupt Enable"] +pub type LbkdieW<'a, REG> = crate::BitWriter<'a, REG, Lbkdie>; +impl<'a, REG> LbkdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lbkdie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lbkdie::Enable) + } +} +#[doc = "Resynchronization Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Resyncdis { + #[doc = "0: Enable"] + Resync = 0, + #[doc = "1: Disable"] + NoResync = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Resyncdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESYNCDIS` reader - Resynchronization Disable"] +pub type ResyncdisR = crate::BitReader; +impl ResyncdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Resyncdis { + match self.bits { + false => Resyncdis::Resync, + true => Resyncdis::NoResync, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + *self == Resyncdis::Resync + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_no_resync(&self) -> bool { + *self == Resyncdis::NoResync + } +} +#[doc = "Field `RESYNCDIS` writer - Resynchronization Disable"] +pub type ResyncdisW<'a, REG> = crate::BitWriter<'a, REG, Resyncdis>; +impl<'a, REG> ResyncdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn resync(self) -> &'a mut crate::W { + self.variant(Resyncdis::Resync) + } + #[doc = "Disable"] + #[inline(always)] + pub fn no_resync(self) -> &'a mut crate::W { + self.variant(Resyncdis::NoResync) + } +} +#[doc = "Both Edge Sampling\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bothedge { + #[doc = "0: Rising edge"] + Disabled = 0, + #[doc = "1: Both rising and falling edges"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bothedge) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOTHEDGE` reader - Both Edge Sampling"] +pub type BothedgeR = crate::BitReader; +impl BothedgeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bothedge { + match self.bits { + false => Bothedge::Disabled, + true => Bothedge::Enabled, + } + } + #[doc = "Rising edge"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Bothedge::Disabled + } + #[doc = "Both rising and falling edges"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Bothedge::Enabled + } +} +#[doc = "Field `BOTHEDGE` writer - Both Edge Sampling"] +pub type BothedgeW<'a, REG> = crate::BitWriter<'a, REG, Bothedge>; +impl<'a, REG> BothedgeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Rising edge"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Bothedge::Disabled) + } + #[doc = "Both rising and falling edges"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Bothedge::Enabled) + } +} +#[doc = "Match Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Matcfg { + #[doc = "0: Address match wake-up"] + AddrMatch = 0, + #[doc = "1: Idle match wake-up"] + IdleMatch = 1, + #[doc = "2: Match on and match off"] + OnoffMatch = 2, + #[doc = "3: Enables RWU on data match and match on or off for the transmitter CTS input"] + RwuMatch = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Matcfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Matcfg { + type Ux = u8; +} +impl crate::IsEnum for Matcfg {} +#[doc = "Field `MATCFG` reader - Match Configuration"] +pub type MatcfgR = crate::FieldReader; +impl MatcfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Matcfg { + match self.bits { + 0 => Matcfg::AddrMatch, + 1 => Matcfg::IdleMatch, + 2 => Matcfg::OnoffMatch, + 3 => Matcfg::RwuMatch, + _ => unreachable!(), + } + } + #[doc = "Address match wake-up"] + #[inline(always)] + pub fn is_addr_match(&self) -> bool { + *self == Matcfg::AddrMatch + } + #[doc = "Idle match wake-up"] + #[inline(always)] + pub fn is_idle_match(&self) -> bool { + *self == Matcfg::IdleMatch + } + #[doc = "Match on and match off"] + #[inline(always)] + pub fn is_onoff_match(&self) -> bool { + *self == Matcfg::OnoffMatch + } + #[doc = "Enables RWU on data match and match on or off for the transmitter CTS input"] + #[inline(always)] + pub fn is_rwu_match(&self) -> bool { + *self == Matcfg::RwuMatch + } +} +#[doc = "Field `MATCFG` writer - Match Configuration"] +pub type MatcfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Matcfg, crate::Safe>; +impl<'a, REG> MatcfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Address match wake-up"] + #[inline(always)] + pub fn addr_match(self) -> &'a mut crate::W { + self.variant(Matcfg::AddrMatch) + } + #[doc = "Idle match wake-up"] + #[inline(always)] + pub fn idle_match(self) -> &'a mut crate::W { + self.variant(Matcfg::IdleMatch) + } + #[doc = "Match on and match off"] + #[inline(always)] + pub fn onoff_match(self) -> &'a mut crate::W { + self.variant(Matcfg::OnoffMatch) + } + #[doc = "Enables RWU on data match and match on or off for the transmitter CTS input"] + #[inline(always)] + pub fn rwu_match(self) -> &'a mut crate::W { + self.variant(Matcfg::RwuMatch) + } +} +#[doc = "Receiver Idle DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ridmae { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ridmae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RIDMAE` reader - Receiver Idle DMA Enable"] +pub type RidmaeR = crate::BitReader; +impl RidmaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ridmae { + match self.bits { + false => Ridmae::Disabled, + true => Ridmae::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ridmae::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ridmae::Enabled + } +} +#[doc = "Field `RIDMAE` writer - Receiver Idle DMA Enable"] +pub type RidmaeW<'a, REG> = crate::BitWriter<'a, REG, Ridmae>; +impl<'a, REG> RidmaeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ridmae::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ridmae::Enabled) + } +} +#[doc = "Receiver Full DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdmae { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdmae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDMAE` reader - Receiver Full DMA Enable"] +pub type RdmaeR = crate::BitReader; +impl RdmaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdmae { + match self.bits { + false => Rdmae::Disabled, + true => Rdmae::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rdmae::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rdmae::Enabled + } +} +#[doc = "Field `RDMAE` writer - Receiver Full DMA Enable"] +pub type RdmaeW<'a, REG> = crate::BitWriter<'a, REG, Rdmae>; +impl<'a, REG> RdmaeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rdmae::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rdmae::Enabled) + } +} +#[doc = "Transmitter DMA Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdmae { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdmae) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDMAE` reader - Transmitter DMA Enable"] +pub type TdmaeR = crate::BitReader; +impl TdmaeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdmae { + match self.bits { + false => Tdmae::Disabled, + true => Tdmae::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tdmae::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tdmae::Enabled + } +} +#[doc = "Field `TDMAE` writer - Transmitter DMA Enable"] +pub type TdmaeW<'a, REG> = crate::BitWriter<'a, REG, Tdmae>; +impl<'a, REG> TdmaeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tdmae::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tdmae::Enabled) + } +} +#[doc = "Oversampling Ratio\n\nValue on reset: 15"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Osr { + #[doc = "0: Results in an OSR of 16"] + Default = 0, + #[doc = "3: Results in an OSR of 4 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + Osr4 = 3, + #[doc = "4: Results in an OSR of 5 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + Osr5 = 4, + #[doc = "5: Results in an OSR of 6 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + Osr6 = 5, + #[doc = "6: Results in an OSR of 7 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + Osr7 = 6, + #[doc = "7: Results in an OSR of 8"] + Osr8 = 7, + #[doc = "8: Results in an OSR of 9"] + Osr9 = 8, + #[doc = "9: Results in an OSR of 10"] + Osr10 = 9, + #[doc = "10: Results in an OSR of 11"] + Osr11 = 10, + #[doc = "11: Results in an OSR of 12"] + Osr12 = 11, + #[doc = "12: Results in an OSR of 13"] + Osr13 = 12, + #[doc = "13: Results in an OSR of 14"] + Osr14 = 13, + #[doc = "14: Results in an OSR of 15"] + Osr15 = 14, + #[doc = "15: Results in an OSR of 16"] + Osr16 = 15, + #[doc = "16: Results in an OSR of 17"] + Osr17 = 16, + #[doc = "17: Results in an OSR of 18"] + Osr18 = 17, + #[doc = "18: Results in an OSR of 19"] + Osr19 = 18, + #[doc = "19: Results in an OSR of 20"] + Osr20 = 19, + #[doc = "20: Results in an OSR of 21"] + Osr21 = 20, + #[doc = "21: Results in an OSR of 22"] + Osr22 = 21, + #[doc = "22: Results in an OSR of 23"] + Osr23 = 22, + #[doc = "23: Results in an OSR of 24"] + Osr24 = 23, + #[doc = "24: Results in an OSR of 25"] + Osr25 = 24, + #[doc = "25: Results in an OSR of 26"] + Osr26 = 25, + #[doc = "26: Results in an OSR of 27"] + Osr27 = 26, + #[doc = "27: Results in an OSR of 28"] + Osr28 = 27, + #[doc = "28: Results in an OSR of 29"] + Osr29 = 28, + #[doc = "29: Results in an OSR of 30"] + Osr30 = 29, + #[doc = "30: Results in an OSR of 31"] + Osr31 = 30, + #[doc = "31: Results in an OSR of 32"] + Osr32 = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Osr) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Osr { + type Ux = u8; +} +impl crate::IsEnum for Osr {} +#[doc = "Field `OSR` reader - Oversampling Ratio"] +pub type OsrR = crate::FieldReader; +impl OsrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Osr::Default), + 3 => Some(Osr::Osr4), + 4 => Some(Osr::Osr5), + 5 => Some(Osr::Osr6), + 6 => Some(Osr::Osr7), + 7 => Some(Osr::Osr8), + 8 => Some(Osr::Osr9), + 9 => Some(Osr::Osr10), + 10 => Some(Osr::Osr11), + 11 => Some(Osr::Osr12), + 12 => Some(Osr::Osr13), + 13 => Some(Osr::Osr14), + 14 => Some(Osr::Osr15), + 15 => Some(Osr::Osr16), + 16 => Some(Osr::Osr17), + 17 => Some(Osr::Osr18), + 18 => Some(Osr::Osr19), + 19 => Some(Osr::Osr20), + 20 => Some(Osr::Osr21), + 21 => Some(Osr::Osr22), + 22 => Some(Osr::Osr23), + 23 => Some(Osr::Osr24), + 24 => Some(Osr::Osr25), + 25 => Some(Osr::Osr26), + 26 => Some(Osr::Osr27), + 27 => Some(Osr::Osr28), + 28 => Some(Osr::Osr29), + 29 => Some(Osr::Osr30), + 30 => Some(Osr::Osr31), + 31 => Some(Osr::Osr32), + _ => None, + } + } + #[doc = "Results in an OSR of 16"] + #[inline(always)] + pub fn is_default(&self) -> bool { + *self == Osr::Default + } + #[doc = "Results in an OSR of 4 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn is_osr_4(&self) -> bool { + *self == Osr::Osr4 + } + #[doc = "Results in an OSR of 5 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn is_osr_5(&self) -> bool { + *self == Osr::Osr5 + } + #[doc = "Results in an OSR of 6 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn is_osr_6(&self) -> bool { + *self == Osr::Osr6 + } + #[doc = "Results in an OSR of 7 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn is_osr_7(&self) -> bool { + *self == Osr::Osr7 + } + #[doc = "Results in an OSR of 8"] + #[inline(always)] + pub fn is_osr_8(&self) -> bool { + *self == Osr::Osr8 + } + #[doc = "Results in an OSR of 9"] + #[inline(always)] + pub fn is_osr_9(&self) -> bool { + *self == Osr::Osr9 + } + #[doc = "Results in an OSR of 10"] + #[inline(always)] + pub fn is_osr_10(&self) -> bool { + *self == Osr::Osr10 + } + #[doc = "Results in an OSR of 11"] + #[inline(always)] + pub fn is_osr_11(&self) -> bool { + *self == Osr::Osr11 + } + #[doc = "Results in an OSR of 12"] + #[inline(always)] + pub fn is_osr_12(&self) -> bool { + *self == Osr::Osr12 + } + #[doc = "Results in an OSR of 13"] + #[inline(always)] + pub fn is_osr_13(&self) -> bool { + *self == Osr::Osr13 + } + #[doc = "Results in an OSR of 14"] + #[inline(always)] + pub fn is_osr_14(&self) -> bool { + *self == Osr::Osr14 + } + #[doc = "Results in an OSR of 15"] + #[inline(always)] + pub fn is_osr_15(&self) -> bool { + *self == Osr::Osr15 + } + #[doc = "Results in an OSR of 16"] + #[inline(always)] + pub fn is_osr_16(&self) -> bool { + *self == Osr::Osr16 + } + #[doc = "Results in an OSR of 17"] + #[inline(always)] + pub fn is_osr_17(&self) -> bool { + *self == Osr::Osr17 + } + #[doc = "Results in an OSR of 18"] + #[inline(always)] + pub fn is_osr_18(&self) -> bool { + *self == Osr::Osr18 + } + #[doc = "Results in an OSR of 19"] + #[inline(always)] + pub fn is_osr_19(&self) -> bool { + *self == Osr::Osr19 + } + #[doc = "Results in an OSR of 20"] + #[inline(always)] + pub fn is_osr_20(&self) -> bool { + *self == Osr::Osr20 + } + #[doc = "Results in an OSR of 21"] + #[inline(always)] + pub fn is_osr_21(&self) -> bool { + *self == Osr::Osr21 + } + #[doc = "Results in an OSR of 22"] + #[inline(always)] + pub fn is_osr_22(&self) -> bool { + *self == Osr::Osr22 + } + #[doc = "Results in an OSR of 23"] + #[inline(always)] + pub fn is_osr_23(&self) -> bool { + *self == Osr::Osr23 + } + #[doc = "Results in an OSR of 24"] + #[inline(always)] + pub fn is_osr_24(&self) -> bool { + *self == Osr::Osr24 + } + #[doc = "Results in an OSR of 25"] + #[inline(always)] + pub fn is_osr_25(&self) -> bool { + *self == Osr::Osr25 + } + #[doc = "Results in an OSR of 26"] + #[inline(always)] + pub fn is_osr_26(&self) -> bool { + *self == Osr::Osr26 + } + #[doc = "Results in an OSR of 27"] + #[inline(always)] + pub fn is_osr_27(&self) -> bool { + *self == Osr::Osr27 + } + #[doc = "Results in an OSR of 28"] + #[inline(always)] + pub fn is_osr_28(&self) -> bool { + *self == Osr::Osr28 + } + #[doc = "Results in an OSR of 29"] + #[inline(always)] + pub fn is_osr_29(&self) -> bool { + *self == Osr::Osr29 + } + #[doc = "Results in an OSR of 30"] + #[inline(always)] + pub fn is_osr_30(&self) -> bool { + *self == Osr::Osr30 + } + #[doc = "Results in an OSR of 31"] + #[inline(always)] + pub fn is_osr_31(&self) -> bool { + *self == Osr::Osr31 + } + #[doc = "Results in an OSR of 32"] + #[inline(always)] + pub fn is_osr_32(&self) -> bool { + *self == Osr::Osr32 + } +} +#[doc = "Field `OSR` writer - Oversampling Ratio"] +pub type OsrW<'a, REG> = crate::FieldWriter<'a, REG, 5, Osr>; +impl<'a, REG> OsrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Results in an OSR of 16"] + #[inline(always)] + pub fn default(self) -> &'a mut crate::W { + self.variant(Osr::Default) + } + #[doc = "Results in an OSR of 4 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn osr_4(self) -> &'a mut crate::W { + self.variant(Osr::Osr4) + } + #[doc = "Results in an OSR of 5 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn osr_5(self) -> &'a mut crate::W { + self.variant(Osr::Osr5) + } + #[doc = "Results in an OSR of 6 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn osr_6(self) -> &'a mut crate::W { + self.variant(Osr::Osr6) + } + #[doc = "Results in an OSR of 7 (requires BAUD\\[BOTHEDGE\\] to be 1)"] + #[inline(always)] + pub fn osr_7(self) -> &'a mut crate::W { + self.variant(Osr::Osr7) + } + #[doc = "Results in an OSR of 8"] + #[inline(always)] + pub fn osr_8(self) -> &'a mut crate::W { + self.variant(Osr::Osr8) + } + #[doc = "Results in an OSR of 9"] + #[inline(always)] + pub fn osr_9(self) -> &'a mut crate::W { + self.variant(Osr::Osr9) + } + #[doc = "Results in an OSR of 10"] + #[inline(always)] + pub fn osr_10(self) -> &'a mut crate::W { + self.variant(Osr::Osr10) + } + #[doc = "Results in an OSR of 11"] + #[inline(always)] + pub fn osr_11(self) -> &'a mut crate::W { + self.variant(Osr::Osr11) + } + #[doc = "Results in an OSR of 12"] + #[inline(always)] + pub fn osr_12(self) -> &'a mut crate::W { + self.variant(Osr::Osr12) + } + #[doc = "Results in an OSR of 13"] + #[inline(always)] + pub fn osr_13(self) -> &'a mut crate::W { + self.variant(Osr::Osr13) + } + #[doc = "Results in an OSR of 14"] + #[inline(always)] + pub fn osr_14(self) -> &'a mut crate::W { + self.variant(Osr::Osr14) + } + #[doc = "Results in an OSR of 15"] + #[inline(always)] + pub fn osr_15(self) -> &'a mut crate::W { + self.variant(Osr::Osr15) + } + #[doc = "Results in an OSR of 16"] + #[inline(always)] + pub fn osr_16(self) -> &'a mut crate::W { + self.variant(Osr::Osr16) + } + #[doc = "Results in an OSR of 17"] + #[inline(always)] + pub fn osr_17(self) -> &'a mut crate::W { + self.variant(Osr::Osr17) + } + #[doc = "Results in an OSR of 18"] + #[inline(always)] + pub fn osr_18(self) -> &'a mut crate::W { + self.variant(Osr::Osr18) + } + #[doc = "Results in an OSR of 19"] + #[inline(always)] + pub fn osr_19(self) -> &'a mut crate::W { + self.variant(Osr::Osr19) + } + #[doc = "Results in an OSR of 20"] + #[inline(always)] + pub fn osr_20(self) -> &'a mut crate::W { + self.variant(Osr::Osr20) + } + #[doc = "Results in an OSR of 21"] + #[inline(always)] + pub fn osr_21(self) -> &'a mut crate::W { + self.variant(Osr::Osr21) + } + #[doc = "Results in an OSR of 22"] + #[inline(always)] + pub fn osr_22(self) -> &'a mut crate::W { + self.variant(Osr::Osr22) + } + #[doc = "Results in an OSR of 23"] + #[inline(always)] + pub fn osr_23(self) -> &'a mut crate::W { + self.variant(Osr::Osr23) + } + #[doc = "Results in an OSR of 24"] + #[inline(always)] + pub fn osr_24(self) -> &'a mut crate::W { + self.variant(Osr::Osr24) + } + #[doc = "Results in an OSR of 25"] + #[inline(always)] + pub fn osr_25(self) -> &'a mut crate::W { + self.variant(Osr::Osr25) + } + #[doc = "Results in an OSR of 26"] + #[inline(always)] + pub fn osr_26(self) -> &'a mut crate::W { + self.variant(Osr::Osr26) + } + #[doc = "Results in an OSR of 27"] + #[inline(always)] + pub fn osr_27(self) -> &'a mut crate::W { + self.variant(Osr::Osr27) + } + #[doc = "Results in an OSR of 28"] + #[inline(always)] + pub fn osr_28(self) -> &'a mut crate::W { + self.variant(Osr::Osr28) + } + #[doc = "Results in an OSR of 29"] + #[inline(always)] + pub fn osr_29(self) -> &'a mut crate::W { + self.variant(Osr::Osr29) + } + #[doc = "Results in an OSR of 30"] + #[inline(always)] + pub fn osr_30(self) -> &'a mut crate::W { + self.variant(Osr::Osr30) + } + #[doc = "Results in an OSR of 31"] + #[inline(always)] + pub fn osr_31(self) -> &'a mut crate::W { + self.variant(Osr::Osr31) + } + #[doc = "Results in an OSR of 32"] + #[inline(always)] + pub fn osr_32(self) -> &'a mut crate::W { + self.variant(Osr::Osr32) + } +} +#[doc = "10-Bit Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M10 { + #[doc = "0: Receiver and transmitter use 7-bit to 9-bit data characters"] + Disabled = 0, + #[doc = "1: Receiver and transmitter use 10-bit data characters"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M10` reader - 10-Bit Mode Select"] +pub type M10R = crate::BitReader; +impl M10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M10 { + match self.bits { + false => M10::Disabled, + true => M10::Enabled, + } + } + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M10::Disabled + } + #[doc = "Receiver and transmitter use 10-bit data characters"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M10::Enabled + } +} +#[doc = "Field `M10` writer - 10-Bit Mode Select"] +pub type M10W<'a, REG> = crate::BitWriter<'a, REG, M10>; +impl<'a, REG> M10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M10::Disabled) + } + #[doc = "Receiver and transmitter use 10-bit data characters"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M10::Enabled) + } +} +#[doc = "Match Address Mode Enable 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Maen2 { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Maen2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MAEN2` reader - Match Address Mode Enable 2"] +pub type Maen2R = crate::BitReader; +impl Maen2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Maen2 { + match self.bits { + false => Maen2::Disabled, + true => Maen2::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Maen2::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Maen2::Enabled + } +} +#[doc = "Field `MAEN2` writer - Match Address Mode Enable 2"] +pub type Maen2W<'a, REG> = crate::BitWriter<'a, REG, Maen2>; +impl<'a, REG> Maen2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Maen2::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Maen2::Enabled) + } +} +#[doc = "Match Address Mode Enable 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Maen1 { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Maen1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MAEN1` reader - Match Address Mode Enable 1"] +pub type Maen1R = crate::BitReader; +impl Maen1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Maen1 { + match self.bits { + false => Maen1::Disabled, + true => Maen1::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Maen1::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Maen1::Enabled + } +} +#[doc = "Field `MAEN1` writer - Match Address Mode Enable 1"] +pub type Maen1W<'a, REG> = crate::BitWriter<'a, REG, Maen1>; +impl<'a, REG> Maen1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Maen1::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Maen1::Enabled) + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Modulo Divisor"] + #[inline(always)] + pub fn sbr(&self) -> SbrR { + SbrR::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bit 13 - Stop Bit Number Select"] + #[inline(always)] + pub fn sbns(&self) -> SbnsR { + SbnsR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - RX Input Active Edge Interrupt Enable"] + #[inline(always)] + pub fn rxedgie(&self) -> RxedgieR { + RxedgieR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - LIN Break Detect Interrupt Enable"] + #[inline(always)] + pub fn lbkdie(&self) -> LbkdieR { + LbkdieR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Resynchronization Disable"] + #[inline(always)] + pub fn resyncdis(&self) -> ResyncdisR { + ResyncdisR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Both Edge Sampling"] + #[inline(always)] + pub fn bothedge(&self) -> BothedgeR { + BothedgeR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Match Configuration"] + #[inline(always)] + pub fn matcfg(&self) -> MatcfgR { + MatcfgR::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Receiver Idle DMA Enable"] + #[inline(always)] + pub fn ridmae(&self) -> RidmaeR { + RidmaeR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Receiver Full DMA Enable"] + #[inline(always)] + pub fn rdmae(&self) -> RdmaeR { + RdmaeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Transmitter DMA Enable"] + #[inline(always)] + pub fn tdmae(&self) -> TdmaeR { + TdmaeR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:28 - Oversampling Ratio"] + #[inline(always)] + pub fn osr(&self) -> OsrR { + OsrR::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 29 - 10-Bit Mode Select"] + #[inline(always)] + pub fn m10(&self) -> M10R { + M10R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Match Address Mode Enable 2"] + #[inline(always)] + pub fn maen2(&self) -> Maen2R { + Maen2R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Match Address Mode Enable 1"] + #[inline(always)] + pub fn maen1(&self) -> Maen1R { + Maen1R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Modulo Divisor"] + #[inline(always)] + pub fn sbr(&mut self) -> SbrW { + SbrW::new(self, 0) + } + #[doc = "Bit 13 - Stop Bit Number Select"] + #[inline(always)] + pub fn sbns(&mut self) -> SbnsW { + SbnsW::new(self, 13) + } + #[doc = "Bit 14 - RX Input Active Edge Interrupt Enable"] + #[inline(always)] + pub fn rxedgie(&mut self) -> RxedgieW { + RxedgieW::new(self, 14) + } + #[doc = "Bit 15 - LIN Break Detect Interrupt Enable"] + #[inline(always)] + pub fn lbkdie(&mut self) -> LbkdieW { + LbkdieW::new(self, 15) + } + #[doc = "Bit 16 - Resynchronization Disable"] + #[inline(always)] + pub fn resyncdis(&mut self) -> ResyncdisW { + ResyncdisW::new(self, 16) + } + #[doc = "Bit 17 - Both Edge Sampling"] + #[inline(always)] + pub fn bothedge(&mut self) -> BothedgeW { + BothedgeW::new(self, 17) + } + #[doc = "Bits 18:19 - Match Configuration"] + #[inline(always)] + pub fn matcfg(&mut self) -> MatcfgW { + MatcfgW::new(self, 18) + } + #[doc = "Bit 20 - Receiver Idle DMA Enable"] + #[inline(always)] + pub fn ridmae(&mut self) -> RidmaeW { + RidmaeW::new(self, 20) + } + #[doc = "Bit 21 - Receiver Full DMA Enable"] + #[inline(always)] + pub fn rdmae(&mut self) -> RdmaeW { + RdmaeW::new(self, 21) + } + #[doc = "Bit 23 - Transmitter DMA Enable"] + #[inline(always)] + pub fn tdmae(&mut self) -> TdmaeW { + TdmaeW::new(self, 23) + } + #[doc = "Bits 24:28 - Oversampling Ratio"] + #[inline(always)] + pub fn osr(&mut self) -> OsrW { + OsrW::new(self, 24) + } + #[doc = "Bit 29 - 10-Bit Mode Select"] + #[inline(always)] + pub fn m10(&mut self) -> M10W { + M10W::new(self, 29) + } + #[doc = "Bit 30 - Match Address Mode Enable 2"] + #[inline(always)] + pub fn maen2(&mut self) -> Maen2W { + Maen2W::new(self, 30) + } + #[doc = "Bit 31 - Match Address Mode Enable 1"] + #[inline(always)] + pub fn maen1(&mut self) -> Maen1W { + Maen1W::new(self, 31) + } +} +#[doc = "Baud Rate\n\nYou can [`read`](crate::Reg::read) this register and get [`baud::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BaudSpec; +impl crate::RegisterSpec for BaudSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`baud::R`](R) reader structure"] +impl crate::Readable for BaudSpec {} +#[doc = "`write(|w| ..)` method takes [`baud::W`](W) writer structure"] +impl crate::Writable for BaudSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BAUD to value 0x0f00_0004"] +impl crate::Resettable for BaudSpec { + const RESET_VALUE: u32 = 0x0f00_0004; +} diff --git a/mcxa276-pac/src/lpuart0/ctrl.rs b/mcxa276-pac/src/lpuart0/ctrl.rs new file mode 100644 index 000000000..0154d1537 --- /dev/null +++ b/mcxa276-pac/src/lpuart0/ctrl.rs @@ -0,0 +1,1835 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Parity Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pt { + #[doc = "0: Even parity"] + Even = 0, + #[doc = "1: Odd parity"] + Odd = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PT` reader - Parity Type"] +pub type PtR = crate::BitReader; +impl PtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pt { + match self.bits { + false => Pt::Even, + true => Pt::Odd, + } + } + #[doc = "Even parity"] + #[inline(always)] + pub fn is_even(&self) -> bool { + *self == Pt::Even + } + #[doc = "Odd parity"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + *self == Pt::Odd + } +} +#[doc = "Field `PT` writer - Parity Type"] +pub type PtW<'a, REG> = crate::BitWriter<'a, REG, Pt>; +impl<'a, REG> PtW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Even parity"] + #[inline(always)] + pub fn even(self) -> &'a mut crate::W { + self.variant(Pt::Even) + } + #[doc = "Odd parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut crate::W { + self.variant(Pt::Odd) + } +} +#[doc = "Parity Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Parity Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Disabled, + true => Pe::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pe::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pe::Enabled + } +} +#[doc = "Field `PE` writer - Parity Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pe::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pe::Enabled) + } +} +#[doc = "Idle Line Type Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ilt { + #[doc = "0: After the start bit"] + FromStart = 0, + #[doc = "1: After the stop bit"] + FromStop = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ilt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ILT` reader - Idle Line Type Select"] +pub type IltR = crate::BitReader; +impl IltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ilt { + match self.bits { + false => Ilt::FromStart, + true => Ilt::FromStop, + } + } + #[doc = "After the start bit"] + #[inline(always)] + pub fn is_from_start(&self) -> bool { + *self == Ilt::FromStart + } + #[doc = "After the stop bit"] + #[inline(always)] + pub fn is_from_stop(&self) -> bool { + *self == Ilt::FromStop + } +} +#[doc = "Field `ILT` writer - Idle Line Type Select"] +pub type IltW<'a, REG> = crate::BitWriter<'a, REG, Ilt>; +impl<'a, REG> IltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "After the start bit"] + #[inline(always)] + pub fn from_start(self) -> &'a mut crate::W { + self.variant(Ilt::FromStart) + } + #[doc = "After the stop bit"] + #[inline(always)] + pub fn from_stop(self) -> &'a mut crate::W { + self.variant(Ilt::FromStop) + } +} +#[doc = "Receiver Wake-Up Method Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wake { + #[doc = "0: Idle"] + Idle = 0, + #[doc = "1: Mark"] + Mark = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wake) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKE` reader - Receiver Wake-Up Method Select"] +pub type WakeR = crate::BitReader; +impl WakeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wake { + match self.bits { + false => Wake::Idle, + true => Wake::Mark, + } + } + #[doc = "Idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Wake::Idle + } + #[doc = "Mark"] + #[inline(always)] + pub fn is_mark(&self) -> bool { + *self == Wake::Mark + } +} +#[doc = "Field `WAKE` writer - Receiver Wake-Up Method Select"] +pub type WakeW<'a, REG> = crate::BitWriter<'a, REG, Wake>; +impl<'a, REG> WakeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Idle"] + #[inline(always)] + pub fn idle(self) -> &'a mut crate::W { + self.variant(Wake::Idle) + } + #[doc = "Mark"] + #[inline(always)] + pub fn mark(self) -> &'a mut crate::W { + self.variant(Wake::Mark) + } +} +#[doc = "9-Bit Or 8-Bit Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M { + #[doc = "0: 8-bit"] + Data8 = 0, + #[doc = "1: 9-bit"] + Data9 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M` reader - 9-Bit Or 8-Bit Mode Select"] +pub type MR = crate::BitReader; +impl MR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M { + match self.bits { + false => M::Data8, + true => M::Data9, + } + } + #[doc = "8-bit"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + *self == M::Data8 + } + #[doc = "9-bit"] + #[inline(always)] + pub fn is_data9(&self) -> bool { + *self == M::Data9 + } +} +#[doc = "Field `M` writer - 9-Bit Or 8-Bit Mode Select"] +pub type MW<'a, REG> = crate::BitWriter<'a, REG, M>; +impl<'a, REG> MW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "8-bit"] + #[inline(always)] + pub fn data8(self) -> &'a mut crate::W { + self.variant(M::Data8) + } + #[doc = "9-bit"] + #[inline(always)] + pub fn data9(self) -> &'a mut crate::W { + self.variant(M::Data9) + } +} +#[doc = "Receiver Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rsrc { + #[doc = "0: Internal Loopback mode"] + NoEffect = 0, + #[doc = "1: Single-wire mode"] + Onewire = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rsrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RSRC` reader - Receiver Source Select"] +pub type RsrcR = crate::BitReader; +impl RsrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rsrc { + match self.bits { + false => Rsrc::NoEffect, + true => Rsrc::Onewire, + } + } + #[doc = "Internal Loopback mode"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rsrc::NoEffect + } + #[doc = "Single-wire mode"] + #[inline(always)] + pub fn is_onewire(&self) -> bool { + *self == Rsrc::Onewire + } +} +#[doc = "Field `RSRC` writer - Receiver Source Select"] +pub type RsrcW<'a, REG> = crate::BitWriter<'a, REG, Rsrc>; +impl<'a, REG> RsrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Internal Loopback mode"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rsrc::NoEffect) + } + #[doc = "Single-wire mode"] + #[inline(always)] + pub fn onewire(self) -> &'a mut crate::W { + self.variant(Rsrc::Onewire) + } +} +#[doc = "Doze Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dozeen { + #[doc = "0: Enable"] + Enabled = 0, + #[doc = "1: Disable"] + Disabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dozeen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DOZEEN` reader - Doze Mode"] +pub type DozeenR = crate::BitReader; +impl DozeenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dozeen { + match self.bits { + false => Dozeen::Enabled, + true => Dozeen::Disabled, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dozeen::Enabled + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dozeen::Disabled + } +} +#[doc = "Field `DOZEEN` writer - Doze Mode"] +pub type DozeenW<'a, REG> = crate::BitWriter<'a, REG, Dozeen>; +impl<'a, REG> DozeenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dozeen::Enabled) + } + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dozeen::Disabled) + } +} +#[doc = "Loop Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Loops { + #[doc = "0: Normal operation: RXD and TXD use separate pins"] + Noffect = 0, + #[doc = "1: Loop mode or Single-Wire mode"] + Loopback = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Loops) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOOPS` reader - Loop Mode Select"] +pub type LoopsR = crate::BitReader; +impl LoopsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Loops { + match self.bits { + false => Loops::Noffect, + true => Loops::Loopback, + } + } + #[doc = "Normal operation: RXD and TXD use separate pins"] + #[inline(always)] + pub fn is_noffect(&self) -> bool { + *self == Loops::Noffect + } + #[doc = "Loop mode or Single-Wire mode"] + #[inline(always)] + pub fn is_loopback(&self) -> bool { + *self == Loops::Loopback + } +} +#[doc = "Field `LOOPS` writer - Loop Mode Select"] +pub type LoopsW<'a, REG> = crate::BitWriter<'a, REG, Loops>; +impl<'a, REG> LoopsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal operation: RXD and TXD use separate pins"] + #[inline(always)] + pub fn noffect(self) -> &'a mut crate::W { + self.variant(Loops::Noffect) + } + #[doc = "Loop mode or Single-Wire mode"] + #[inline(always)] + pub fn loopback(self) -> &'a mut crate::W { + self.variant(Loops::Loopback) + } +} +#[doc = "Idle Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Idlecfg { + #[doc = "0: 1"] + Idle1 = 0, + #[doc = "1: 2"] + Idle2 = 1, + #[doc = "2: 4"] + Idle4 = 2, + #[doc = "3: 8"] + Idle8 = 3, + #[doc = "4: 16"] + Idle16 = 4, + #[doc = "5: 32"] + Idle32 = 5, + #[doc = "6: 64"] + Idle64 = 6, + #[doc = "7: 128"] + Idle128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Idlecfg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Idlecfg { + type Ux = u8; +} +impl crate::IsEnum for Idlecfg {} +#[doc = "Field `IDLECFG` reader - Idle Configuration"] +pub type IdlecfgR = crate::FieldReader; +impl IdlecfgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Idlecfg { + match self.bits { + 0 => Idlecfg::Idle1, + 1 => Idlecfg::Idle2, + 2 => Idlecfg::Idle4, + 3 => Idlecfg::Idle8, + 4 => Idlecfg::Idle16, + 5 => Idlecfg::Idle32, + 6 => Idlecfg::Idle64, + 7 => Idlecfg::Idle128, + _ => unreachable!(), + } + } + #[doc = "1"] + #[inline(always)] + pub fn is_idle_1(&self) -> bool { + *self == Idlecfg::Idle1 + } + #[doc = "2"] + #[inline(always)] + pub fn is_idle_2(&self) -> bool { + *self == Idlecfg::Idle2 + } + #[doc = "4"] + #[inline(always)] + pub fn is_idle_4(&self) -> bool { + *self == Idlecfg::Idle4 + } + #[doc = "8"] + #[inline(always)] + pub fn is_idle_8(&self) -> bool { + *self == Idlecfg::Idle8 + } + #[doc = "16"] + #[inline(always)] + pub fn is_idle_16(&self) -> bool { + *self == Idlecfg::Idle16 + } + #[doc = "32"] + #[inline(always)] + pub fn is_idle_32(&self) -> bool { + *self == Idlecfg::Idle32 + } + #[doc = "64"] + #[inline(always)] + pub fn is_idle_64(&self) -> bool { + *self == Idlecfg::Idle64 + } + #[doc = "128"] + #[inline(always)] + pub fn is_idle_128(&self) -> bool { + *self == Idlecfg::Idle128 + } +} +#[doc = "Field `IDLECFG` writer - Idle Configuration"] +pub type IdlecfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Idlecfg, crate::Safe>; +impl<'a, REG> IdlecfgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1"] + #[inline(always)] + pub fn idle_1(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle1) + } + #[doc = "2"] + #[inline(always)] + pub fn idle_2(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle2) + } + #[doc = "4"] + #[inline(always)] + pub fn idle_4(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle4) + } + #[doc = "8"] + #[inline(always)] + pub fn idle_8(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle8) + } + #[doc = "16"] + #[inline(always)] + pub fn idle_16(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle16) + } + #[doc = "32"] + #[inline(always)] + pub fn idle_32(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle32) + } + #[doc = "64"] + #[inline(always)] + pub fn idle_64(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle64) + } + #[doc = "128"] + #[inline(always)] + pub fn idle_128(self) -> &'a mut crate::W { + self.variant(Idlecfg::Idle128) + } +} +#[doc = "7-Bit Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M7 { + #[doc = "0: 8-bit to 10-bit"] + NoEffect = 0, + #[doc = "1: 7-bit"] + Data7 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M7` reader - 7-Bit Mode Select"] +pub type M7R = crate::BitReader; +impl M7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M7 { + match self.bits { + false => M7::NoEffect, + true => M7::Data7, + } + } + #[doc = "8-bit to 10-bit"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == M7::NoEffect + } + #[doc = "7-bit"] + #[inline(always)] + pub fn is_data7(&self) -> bool { + *self == M7::Data7 + } +} +#[doc = "Field `M7` writer - 7-Bit Mode Select"] +pub type M7W<'a, REG> = crate::BitWriter<'a, REG, M7>; +impl<'a, REG> M7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "8-bit to 10-bit"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(M7::NoEffect) + } + #[doc = "7-bit"] + #[inline(always)] + pub fn data7(self) -> &'a mut crate::W { + self.variant(M7::Data7) + } +} +#[doc = "TXD and RXD Pin Swap\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swap { + #[doc = "0: Use the standard way"] + Standard = 0, + #[doc = "1: Swap"] + Swap = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swap) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWAP` reader - TXD and RXD Pin Swap"] +pub type SwapR = crate::BitReader; +impl SwapR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swap { + match self.bits { + false => Swap::Standard, + true => Swap::Swap, + } + } + #[doc = "Use the standard way"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == Swap::Standard + } + #[doc = "Swap"] + #[inline(always)] + pub fn is_swap(&self) -> bool { + *self == Swap::Swap + } +} +#[doc = "Field `SWAP` writer - TXD and RXD Pin Swap"] +pub type SwapW<'a, REG> = crate::BitWriter<'a, REG, Swap>; +impl<'a, REG> SwapW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Use the standard way"] + #[inline(always)] + pub fn standard(self) -> &'a mut crate::W { + self.variant(Swap::Standard) + } + #[doc = "Swap"] + #[inline(always)] + pub fn swap(self) -> &'a mut crate::W { + self.variant(Swap::Swap) + } +} +#[doc = "Match 2 (MA2F) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ma2ie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ma2ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MA2IE` reader - Match 2 (MA2F) Interrupt Enable"] +pub type Ma2ieR = crate::BitReader; +impl Ma2ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ma2ie { + match self.bits { + false => Ma2ie::Disabled, + true => Ma2ie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ma2ie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ma2ie::Enabled + } +} +#[doc = "Field `MA2IE` writer - Match 2 (MA2F) Interrupt Enable"] +pub type Ma2ieW<'a, REG> = crate::BitWriter<'a, REG, Ma2ie>; +impl<'a, REG> Ma2ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ma2ie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ma2ie::Enabled) + } +} +#[doc = "Match 1 (MA1F) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ma1ie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ma1ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MA1IE` reader - Match 1 (MA1F) Interrupt Enable"] +pub type Ma1ieR = crate::BitReader; +impl Ma1ieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ma1ie { + match self.bits { + false => Ma1ie::Disabled, + true => Ma1ie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ma1ie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ma1ie::Enabled + } +} +#[doc = "Field `MA1IE` writer - Match 1 (MA1F) Interrupt Enable"] +pub type Ma1ieW<'a, REG> = crate::BitWriter<'a, REG, Ma1ie>; +impl<'a, REG> Ma1ieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ma1ie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ma1ie::Enabled) + } +} +#[doc = "Send Break\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbk { + #[doc = "0: Normal transmitter operation"] + NoEffect = 0, + #[doc = "1: Queue break character(s) to be sent"] + TxBreak = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBK` reader - Send Break"] +pub type SbkR = crate::BitReader; +impl SbkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbk { + match self.bits { + false => Sbk::NoEffect, + true => Sbk::TxBreak, + } + } + #[doc = "Normal transmitter operation"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Sbk::NoEffect + } + #[doc = "Queue break character(s) to be sent"] + #[inline(always)] + pub fn is_tx_break(&self) -> bool { + *self == Sbk::TxBreak + } +} +#[doc = "Field `SBK` writer - Send Break"] +pub type SbkW<'a, REG> = crate::BitWriter<'a, REG, Sbk>; +impl<'a, REG> SbkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal transmitter operation"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Sbk::NoEffect) + } + #[doc = "Queue break character(s) to be sent"] + #[inline(always)] + pub fn tx_break(self) -> &'a mut crate::W { + self.variant(Sbk::TxBreak) + } +} +#[doc = "Receiver Wake-Up Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rwu { + #[doc = "0: Normal receiver operation"] + NoEffect = 0, + #[doc = "1: LPUART receiver in standby, waiting for a wake-up condition"] + RxWakeup = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rwu) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RWU` reader - Receiver Wake-Up Control"] +pub type RwuR = crate::BitReader; +impl RwuR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rwu { + match self.bits { + false => Rwu::NoEffect, + true => Rwu::RxWakeup, + } + } + #[doc = "Normal receiver operation"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rwu::NoEffect + } + #[doc = "LPUART receiver in standby, waiting for a wake-up condition"] + #[inline(always)] + pub fn is_rx_wakeup(&self) -> bool { + *self == Rwu::RxWakeup + } +} +#[doc = "Field `RWU` writer - Receiver Wake-Up Control"] +pub type RwuW<'a, REG> = crate::BitWriter<'a, REG, Rwu>; +impl<'a, REG> RwuW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal receiver operation"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rwu::NoEffect) + } + #[doc = "LPUART receiver in standby, waiting for a wake-up condition"] + #[inline(always)] + pub fn rx_wakeup(self) -> &'a mut crate::W { + self.variant(Rwu::RxWakeup) + } +} +#[doc = "Receiver Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Re { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RE` reader - Receiver Enable"] +pub type ReR = crate::BitReader; +impl ReR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Re { + match self.bits { + false => Re::Disabled, + true => Re::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Re::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Re::Enabled + } +} +#[doc = "Field `RE` writer - Receiver Enable"] +pub type ReW<'a, REG> = crate::BitWriter<'a, REG, Re>; +impl<'a, REG> ReW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Re::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Re::Enabled) + } +} +#[doc = "Transmitter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Te { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Te) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TE` reader - Transmitter Enable"] +pub type TeR = crate::BitReader; +impl TeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Te { + match self.bits { + false => Te::Disabled, + true => Te::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Te::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Te::Enabled + } +} +#[doc = "Field `TE` writer - Transmitter Enable"] +pub type TeW<'a, REG> = crate::BitWriter<'a, REG, Te>; +impl<'a, REG> TeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Te::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Te::Enabled) + } +} +#[doc = "Idle Line Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ilie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ilie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ILIE` reader - Idle Line Interrupt Enable"] +pub type IlieR = crate::BitReader; +impl IlieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ilie { + match self.bits { + false => Ilie::Disabled, + true => Ilie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ilie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ilie::Enabled + } +} +#[doc = "Field `ILIE` writer - Idle Line Interrupt Enable"] +pub type IlieW<'a, REG> = crate::BitWriter<'a, REG, Ilie>; +impl<'a, REG> IlieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ilie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ilie::Enabled) + } +} +#[doc = "Receiver Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RIE` reader - Receiver Interrupt Enable"] +pub type RieR = crate::BitReader; +impl RieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rie { + match self.bits { + false => Rie::Disabled, + true => Rie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rie::Enabled + } +} +#[doc = "Field `RIE` writer - Receiver Interrupt Enable"] +pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; +impl<'a, REG> RieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rie::Enabled) + } +} +#[doc = "Transmission Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tcie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tcie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCIE` reader - Transmission Complete Interrupt Enable"] +pub type TcieR = crate::BitReader; +impl TcieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcie { + match self.bits { + false => Tcie::Disabled, + true => Tcie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tcie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tcie::Enabled + } +} +#[doc = "Field `TCIE` writer - Transmission Complete Interrupt Enable"] +pub type TcieW<'a, REG> = crate::BitWriter<'a, REG, Tcie>; +impl<'a, REG> TcieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tcie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tcie::Enabled) + } +} +#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE` reader - Transmit Interrupt Enable"] +pub type TieR = crate::BitReader; +impl TieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie { + match self.bits { + false => Tie::Disabled, + true => Tie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tie::Enabled + } +} +#[doc = "Field `TIE` writer - Transmit Interrupt Enable"] +pub type TieW<'a, REG> = crate::BitWriter<'a, REG, Tie>; +impl<'a, REG> TieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tie::Enabled) + } +} +#[doc = "Parity Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Peie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Peie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PEIE` reader - Parity Error Interrupt Enable"] +pub type PeieR = crate::BitReader; +impl PeieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Peie { + match self.bits { + false => Peie::Disabled, + true => Peie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Peie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Peie::Enabled + } +} +#[doc = "Field `PEIE` writer - Parity Error Interrupt Enable"] +pub type PeieW<'a, REG> = crate::BitWriter<'a, REG, Peie>; +impl<'a, REG> PeieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Peie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Peie::Enabled) + } +} +#[doc = "Framing Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Feie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Feie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FEIE` reader - Framing Error Interrupt Enable"] +pub type FeieR = crate::BitReader; +impl FeieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Feie { + match self.bits { + false => Feie::Disabled, + true => Feie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Feie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Feie::Enabled + } +} +#[doc = "Field `FEIE` writer - Framing Error Interrupt Enable"] +pub type FeieW<'a, REG> = crate::BitWriter<'a, REG, Feie>; +impl<'a, REG> FeieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Feie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Feie::Enabled) + } +} +#[doc = "Noise Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Neie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Neie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NEIE` reader - Noise Error Interrupt Enable"] +pub type NeieR = crate::BitReader; +impl NeieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Neie { + match self.bits { + false => Neie::Disabled, + true => Neie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Neie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Neie::Enabled + } +} +#[doc = "Field `NEIE` writer - Noise Error Interrupt Enable"] +pub type NeieW<'a, REG> = crate::BitWriter<'a, REG, Neie>; +impl<'a, REG> NeieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Neie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Neie::Enabled) + } +} +#[doc = "Overrun Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Orie { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Orie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ORIE` reader - Overrun Interrupt Enable"] +pub type OrieR = crate::BitReader; +impl OrieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Orie { + match self.bits { + false => Orie::Disabled, + true => Orie::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Orie::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Orie::Enabled + } +} +#[doc = "Field `ORIE` writer - Overrun Interrupt Enable"] +pub type OrieW<'a, REG> = crate::BitWriter<'a, REG, Orie>; +impl<'a, REG> OrieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Orie::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Orie::Enabled) + } +} +#[doc = "Transmit Data Inversion\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txinv { + #[doc = "0: Not inverted"] + NotInverted = 0, + #[doc = "1: Inverted"] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txinv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXINV` reader - Transmit Data Inversion"] +pub type TxinvR = crate::BitReader; +impl TxinvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txinv { + match self.bits { + false => Txinv::NotInverted, + true => Txinv::Inverted, + } + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Txinv::NotInverted + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Txinv::Inverted + } +} +#[doc = "Field `TXINV` writer - Transmit Data Inversion"] +pub type TxinvW<'a, REG> = crate::BitWriter<'a, REG, Txinv>; +impl<'a, REG> TxinvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not inverted"] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Txinv::NotInverted) + } + #[doc = "Inverted"] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Txinv::Inverted) + } +} +#[doc = "TXD Pin Direction in Single-Wire Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txdir { + #[doc = "0: Input"] + TxInput = 0, + #[doc = "1: Output"] + TxOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txdir) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXDIR` reader - TXD Pin Direction in Single-Wire Mode"] +pub type TxdirR = crate::BitReader; +impl TxdirR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txdir { + match self.bits { + false => Txdir::TxInput, + true => Txdir::TxOutput, + } + } + #[doc = "Input"] + #[inline(always)] + pub fn is_tx_input(&self) -> bool { + *self == Txdir::TxInput + } + #[doc = "Output"] + #[inline(always)] + pub fn is_tx_output(&self) -> bool { + *self == Txdir::TxOutput + } +} +#[doc = "Field `TXDIR` writer - TXD Pin Direction in Single-Wire Mode"] +pub type TxdirW<'a, REG> = crate::BitWriter<'a, REG, Txdir>; +impl<'a, REG> TxdirW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Input"] + #[inline(always)] + pub fn tx_input(self) -> &'a mut crate::W { + self.variant(Txdir::TxInput) + } + #[doc = "Output"] + #[inline(always)] + pub fn tx_output(self) -> &'a mut crate::W { + self.variant(Txdir::TxOutput) + } +} +#[doc = "Field `R9T8` reader - Receive Bit 9 Transmit Bit 8"] +pub type R9t8R = crate::BitReader; +#[doc = "Field `R9T8` writer - Receive Bit 9 Transmit Bit 8"] +pub type R9t8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R8T9` reader - Receive Bit 8 Transmit Bit 9"] +pub type R8t9R = crate::BitReader; +#[doc = "Field `R8T9` writer - Receive Bit 8 Transmit Bit 9"] +pub type R8t9W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Parity Type"] + #[inline(always)] + pub fn pt(&self) -> PtR { + PtR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Parity Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Idle Line Type Select"] + #[inline(always)] + pub fn ilt(&self) -> IltR { + IltR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receiver Wake-Up Method Select"] + #[inline(always)] + pub fn wake(&self) -> WakeR { + WakeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 9-Bit Or 8-Bit Mode Select"] + #[inline(always)] + pub fn m(&self) -> MR { + MR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Receiver Source Select"] + #[inline(always)] + pub fn rsrc(&self) -> RsrcR { + RsrcR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Doze Mode"] + #[inline(always)] + pub fn dozeen(&self) -> DozeenR { + DozeenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Loop Mode Select"] + #[inline(always)] + pub fn loops(&self) -> LoopsR { + LoopsR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Idle Configuration"] + #[inline(always)] + pub fn idlecfg(&self) -> IdlecfgR { + IdlecfgR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - 7-Bit Mode Select"] + #[inline(always)] + pub fn m7(&self) -> M7R { + M7R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TXD and RXD Pin Swap"] + #[inline(always)] + pub fn swap(&self) -> SwapR { + SwapR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - Match 2 (MA2F) Interrupt Enable"] + #[inline(always)] + pub fn ma2ie(&self) -> Ma2ieR { + Ma2ieR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Match 1 (MA1F) Interrupt Enable"] + #[inline(always)] + pub fn ma1ie(&self) -> Ma1ieR { + Ma1ieR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Send Break"] + #[inline(always)] + pub fn sbk(&self) -> SbkR { + SbkR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Receiver Wake-Up Control"] + #[inline(always)] + pub fn rwu(&self) -> RwuR { + RwuR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Receiver Enable"] + #[inline(always)] + pub fn re(&self) -> ReR { + ReR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Transmitter Enable"] + #[inline(always)] + pub fn te(&self) -> TeR { + TeR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Idle Line Interrupt Enable"] + #[inline(always)] + pub fn ilie(&self) -> IlieR { + IlieR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Receiver Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RieR { + RieR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Transmission Complete Interrupt Enable"] + #[inline(always)] + pub fn tcie(&self) -> TcieR { + TcieR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn tie(&self) -> TieR { + TieR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Parity Error Interrupt Enable"] + #[inline(always)] + pub fn peie(&self) -> PeieR { + PeieR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Framing Error Interrupt Enable"] + #[inline(always)] + pub fn feie(&self) -> FeieR { + FeieR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Noise Error Interrupt Enable"] + #[inline(always)] + pub fn neie(&self) -> NeieR { + NeieR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn orie(&self) -> OrieR { + OrieR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Transmit Data Inversion"] + #[inline(always)] + pub fn txinv(&self) -> TxinvR { + TxinvR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"] + #[inline(always)] + pub fn txdir(&self) -> TxdirR { + TxdirR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Receive Bit 9 Transmit Bit 8"] + #[inline(always)] + pub fn r9t8(&self) -> R9t8R { + R9t8R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Receive Bit 8 Transmit Bit 9"] + #[inline(always)] + pub fn r8t9(&self) -> R8t9R { + R8t9R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Type"] + #[inline(always)] + pub fn pt(&mut self) -> PtW { + PtW::new(self, 0) + } + #[doc = "Bit 1 - Parity Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Idle Line Type Select"] + #[inline(always)] + pub fn ilt(&mut self) -> IltW { + IltW::new(self, 2) + } + #[doc = "Bit 3 - Receiver Wake-Up Method Select"] + #[inline(always)] + pub fn wake(&mut self) -> WakeW { + WakeW::new(self, 3) + } + #[doc = "Bit 4 - 9-Bit Or 8-Bit Mode Select"] + #[inline(always)] + pub fn m(&mut self) -> MW { + MW::new(self, 4) + } + #[doc = "Bit 5 - Receiver Source Select"] + #[inline(always)] + pub fn rsrc(&mut self) -> RsrcW { + RsrcW::new(self, 5) + } + #[doc = "Bit 6 - Doze Mode"] + #[inline(always)] + pub fn dozeen(&mut self) -> DozeenW { + DozeenW::new(self, 6) + } + #[doc = "Bit 7 - Loop Mode Select"] + #[inline(always)] + pub fn loops(&mut self) -> LoopsW { + LoopsW::new(self, 7) + } + #[doc = "Bits 8:10 - Idle Configuration"] + #[inline(always)] + pub fn idlecfg(&mut self) -> IdlecfgW { + IdlecfgW::new(self, 8) + } + #[doc = "Bit 11 - 7-Bit Mode Select"] + #[inline(always)] + pub fn m7(&mut self) -> M7W { + M7W::new(self, 11) + } + #[doc = "Bit 12 - TXD and RXD Pin Swap"] + #[inline(always)] + pub fn swap(&mut self) -> SwapW { + SwapW::new(self, 12) + } + #[doc = "Bit 14 - Match 2 (MA2F) Interrupt Enable"] + #[inline(always)] + pub fn ma2ie(&mut self) -> Ma2ieW { + Ma2ieW::new(self, 14) + } + #[doc = "Bit 15 - Match 1 (MA1F) Interrupt Enable"] + #[inline(always)] + pub fn ma1ie(&mut self) -> Ma1ieW { + Ma1ieW::new(self, 15) + } + #[doc = "Bit 16 - Send Break"] + #[inline(always)] + pub fn sbk(&mut self) -> SbkW { + SbkW::new(self, 16) + } + #[doc = "Bit 17 - Receiver Wake-Up Control"] + #[inline(always)] + pub fn rwu(&mut self) -> RwuW { + RwuW::new(self, 17) + } + #[doc = "Bit 18 - Receiver Enable"] + #[inline(always)] + pub fn re(&mut self) -> ReW { + ReW::new(self, 18) + } + #[doc = "Bit 19 - Transmitter Enable"] + #[inline(always)] + pub fn te(&mut self) -> TeW { + TeW::new(self, 19) + } + #[doc = "Bit 20 - Idle Line Interrupt Enable"] + #[inline(always)] + pub fn ilie(&mut self) -> IlieW { + IlieW::new(self, 20) + } + #[doc = "Bit 21 - Receiver Interrupt Enable"] + #[inline(always)] + pub fn rie(&mut self) -> RieW { + RieW::new(self, 21) + } + #[doc = "Bit 22 - Transmission Complete Interrupt Enable"] + #[inline(always)] + pub fn tcie(&mut self) -> TcieW { + TcieW::new(self, 22) + } + #[doc = "Bit 23 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn tie(&mut self) -> TieW { + TieW::new(self, 23) + } + #[doc = "Bit 24 - Parity Error Interrupt Enable"] + #[inline(always)] + pub fn peie(&mut self) -> PeieW { + PeieW::new(self, 24) + } + #[doc = "Bit 25 - Framing Error Interrupt Enable"] + #[inline(always)] + pub fn feie(&mut self) -> FeieW { + FeieW::new(self, 25) + } + #[doc = "Bit 26 - Noise Error Interrupt Enable"] + #[inline(always)] + pub fn neie(&mut self) -> NeieW { + NeieW::new(self, 26) + } + #[doc = "Bit 27 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn orie(&mut self) -> OrieW { + OrieW::new(self, 27) + } + #[doc = "Bit 28 - Transmit Data Inversion"] + #[inline(always)] + pub fn txinv(&mut self) -> TxinvW { + TxinvW::new(self, 28) + } + #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"] + #[inline(always)] + pub fn txdir(&mut self) -> TxdirW { + TxdirW::new(self, 29) + } + #[doc = "Bit 30 - Receive Bit 9 Transmit Bit 8"] + #[inline(always)] + pub fn r9t8(&mut self) -> R9t8W { + R9t8W::new(self, 30) + } + #[doc = "Bit 31 - Receive Bit 8 Transmit Bit 9"] + #[inline(always)] + pub fn r8t9(&mut self) -> R8t9W { + R8t9W::new(self, 31) + } +} +#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/lpuart0/data.rs b/mcxa276-pac/src/lpuart0/data.rs new file mode 100644 index 000000000..f1712b21e --- /dev/null +++ b/mcxa276-pac/src/lpuart0/data.rs @@ -0,0 +1,431 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[doc = "Field `R0T0` reader - Read receive FIFO bit 0 or write transmit FIFO bit 0"] +pub type R0t0R = crate::BitReader; +#[doc = "Field `R0T0` writer - Read receive FIFO bit 0 or write transmit FIFO bit 0"] +pub type R0t0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R1T1` reader - Read receive FIFO bit 1 or write transmit FIFO bit 1"] +pub type R1t1R = crate::BitReader; +#[doc = "Field `R1T1` writer - Read receive FIFO bit 1 or write transmit FIFO bit 1"] +pub type R1t1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R2T2` reader - Read receive FIFO bit 2 or write transmit FIFO bit 2"] +pub type R2t2R = crate::BitReader; +#[doc = "Field `R2T2` writer - Read receive FIFO bit 2 or write transmit FIFO bit 2"] +pub type R2t2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R3T3` reader - Read receive FIFO bit 3 or write transmit FIFO bit 3"] +pub type R3t3R = crate::BitReader; +#[doc = "Field `R3T3` writer - Read receive FIFO bit 3 or write transmit FIFO bit 3"] +pub type R3t3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R4T4` reader - Read receive FIFO bit 4 or write transmit FIFO bit 4"] +pub type R4t4R = crate::BitReader; +#[doc = "Field `R4T4` writer - Read receive FIFO bit 4 or write transmit FIFO bit 4"] +pub type R4t4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R5T5` reader - Read receive FIFO bit 5 or write transmit FIFO bit 5"] +pub type R5t5R = crate::BitReader; +#[doc = "Field `R5T5` writer - Read receive FIFO bit 5 or write transmit FIFO bit 5"] +pub type R5t5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R6T6` reader - Read receive FIFO bit 6 or write transmit FIFO bit 6"] +pub type R6t6R = crate::BitReader; +#[doc = "Field `R6T6` writer - Read receive FIFO bit 6 or write transmit FIFO bit 6"] +pub type R6t6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R7T7` reader - Read receive FIFO bit 7 or write transmit FIFO bit 7"] +pub type R7t7R = crate::BitReader; +#[doc = "Field `R7T7` writer - Read receive FIFO bit 7 or write transmit FIFO bit 7"] +pub type R7t7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R8T8` reader - Read receive FIFO bit 8 or write transmit FIFO bit 8"] +pub type R8t8R = crate::BitReader; +#[doc = "Field `R8T8` writer - Read receive FIFO bit 8 or write transmit FIFO bit 8"] +pub type R8t8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `R9T9` reader - Read receive FIFO bit 9 or write transmit FIFO bit 9"] +pub type R9t9R = crate::BitReader; +#[doc = "Field `R9T9` writer - Read receive FIFO bit 9 or write transmit FIFO bit 9"] +pub type R9t9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "LIN Break\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Linbrk { + #[doc = "0: Not detected"] + NoBreak = 0, + #[doc = "1: Detected"] + Break = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Linbrk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LINBRK` reader - LIN Break"] +pub type LinbrkR = crate::BitReader; +impl LinbrkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Linbrk { + match self.bits { + false => Linbrk::NoBreak, + true => Linbrk::Break, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_no_break(&self) -> bool { + *self == Linbrk::NoBreak + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_break(&self) -> bool { + *self == Linbrk::Break + } +} +#[doc = "Idle Line\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Idline { + #[doc = "0: Not idle"] + NoIdle = 0, + #[doc = "1: Idle"] + Idle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Idline) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IDLINE` reader - Idle Line"] +pub type IdlineR = crate::BitReader; +impl IdlineR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Idline { + match self.bits { + false => Idline::NoIdle, + true => Idline::Idle, + } + } + #[doc = "Not idle"] + #[inline(always)] + pub fn is_no_idle(&self) -> bool { + *self == Idline::NoIdle + } + #[doc = "Idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Idline::Idle + } +} +#[doc = "Receive Buffer Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempt { + #[doc = "0: Valid data"] + NotEmpty = 0, + #[doc = "1: Invalid data and empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPT` reader - Receive Buffer Empty"] +pub type RxemptR = crate::BitReader; +impl RxemptR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempt { + match self.bits { + false => Rxempt::NotEmpty, + true => Rxempt::Empty, + } + } + #[doc = "Valid data"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempt::NotEmpty + } + #[doc = "Invalid data and empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempt::Empty + } +} +#[doc = "Frame Error Transmit Special Character\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fretsc { + #[doc = "0: Received without a frame error on reads or transmits a normal character on writes"] + NoError = 0, + #[doc = "1: Received with a frame error on reads or transmits an idle or break character on writes"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fretsc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRETSC` reader - Frame Error Transmit Special Character"] +pub type FretscR = crate::BitReader; +impl FretscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fretsc { + match self.bits { + false => Fretsc::NoError, + true => Fretsc::Error, + } + } + #[doc = "Received without a frame error on reads or transmits a normal character on writes"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Fretsc::NoError + } + #[doc = "Received with a frame error on reads or transmits an idle or break character on writes"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Fretsc::Error + } +} +#[doc = "Field `FRETSC` writer - Frame Error Transmit Special Character"] +pub type FretscW<'a, REG> = crate::BitWriter<'a, REG, Fretsc>; +impl<'a, REG> FretscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Received without a frame error on reads or transmits a normal character on writes"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Fretsc::NoError) + } + #[doc = "Received with a frame error on reads or transmits an idle or break character on writes"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Fretsc::Error) + } +} +#[doc = "Parity Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Paritye { + #[doc = "0: Received without a parity error"] + NoParity = 0, + #[doc = "1: Received with a parity error"] + Parity = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Paritye) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PARITYE` reader - Parity Error"] +pub type ParityeR = crate::BitReader; +impl ParityeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Paritye { + match self.bits { + false => Paritye::NoParity, + true => Paritye::Parity, + } + } + #[doc = "Received without a parity error"] + #[inline(always)] + pub fn is_no_parity(&self) -> bool { + *self == Paritye::NoParity + } + #[doc = "Received with a parity error"] + #[inline(always)] + pub fn is_parity(&self) -> bool { + *self == Paritye::Parity + } +} +#[doc = "Noisy Data Received\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Noisy { + #[doc = "0: Received without noise"] + NoNoise = 0, + #[doc = "1: Received with noise"] + Noise = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Noisy) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOISY` reader - Noisy Data Received"] +pub type NoisyR = crate::BitReader; +impl NoisyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Noisy { + match self.bits { + false => Noisy::NoNoise, + true => Noisy::Noise, + } + } + #[doc = "Received without noise"] + #[inline(always)] + pub fn is_no_noise(&self) -> bool { + *self == Noisy::NoNoise + } + #[doc = "Received with noise"] + #[inline(always)] + pub fn is_noise(&self) -> bool { + *self == Noisy::Noise + } +} +impl R { + #[doc = "Bit 0 - Read receive FIFO bit 0 or write transmit FIFO bit 0"] + #[inline(always)] + pub fn r0t0(&self) -> R0t0R { + R0t0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read receive FIFO bit 1 or write transmit FIFO bit 1"] + #[inline(always)] + pub fn r1t1(&self) -> R1t1R { + R1t1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Read receive FIFO bit 2 or write transmit FIFO bit 2"] + #[inline(always)] + pub fn r2t2(&self) -> R2t2R { + R2t2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Read receive FIFO bit 3 or write transmit FIFO bit 3"] + #[inline(always)] + pub fn r3t3(&self) -> R3t3R { + R3t3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Read receive FIFO bit 4 or write transmit FIFO bit 4"] + #[inline(always)] + pub fn r4t4(&self) -> R4t4R { + R4t4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Read receive FIFO bit 5 or write transmit FIFO bit 5"] + #[inline(always)] + pub fn r5t5(&self) -> R5t5R { + R5t5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Read receive FIFO bit 6 or write transmit FIFO bit 6"] + #[inline(always)] + pub fn r6t6(&self) -> R6t6R { + R6t6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Read receive FIFO bit 7 or write transmit FIFO bit 7"] + #[inline(always)] + pub fn r7t7(&self) -> R7t7R { + R7t7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Read receive FIFO bit 8 or write transmit FIFO bit 8"] + #[inline(always)] + pub fn r8t8(&self) -> R8t8R { + R8t8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Read receive FIFO bit 9 or write transmit FIFO bit 9"] + #[inline(always)] + pub fn r9t9(&self) -> R9t9R { + R9t9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - LIN Break"] + #[inline(always)] + pub fn linbrk(&self) -> LinbrkR { + LinbrkR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Idle Line"] + #[inline(always)] + pub fn idline(&self) -> IdlineR { + IdlineR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Receive Buffer Empty"] + #[inline(always)] + pub fn rxempt(&self) -> RxemptR { + RxemptR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Frame Error Transmit Special Character"] + #[inline(always)] + pub fn fretsc(&self) -> FretscR { + FretscR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Parity Error"] + #[inline(always)] + pub fn paritye(&self) -> ParityeR { + ParityeR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Noisy Data Received"] + #[inline(always)] + pub fn noisy(&self) -> NoisyR { + NoisyR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read receive FIFO bit 0 or write transmit FIFO bit 0"] + #[inline(always)] + pub fn r0t0(&mut self) -> R0t0W { + R0t0W::new(self, 0) + } + #[doc = "Bit 1 - Read receive FIFO bit 1 or write transmit FIFO bit 1"] + #[inline(always)] + pub fn r1t1(&mut self) -> R1t1W { + R1t1W::new(self, 1) + } + #[doc = "Bit 2 - Read receive FIFO bit 2 or write transmit FIFO bit 2"] + #[inline(always)] + pub fn r2t2(&mut self) -> R2t2W { + R2t2W::new(self, 2) + } + #[doc = "Bit 3 - Read receive FIFO bit 3 or write transmit FIFO bit 3"] + #[inline(always)] + pub fn r3t3(&mut self) -> R3t3W { + R3t3W::new(self, 3) + } + #[doc = "Bit 4 - Read receive FIFO bit 4 or write transmit FIFO bit 4"] + #[inline(always)] + pub fn r4t4(&mut self) -> R4t4W { + R4t4W::new(self, 4) + } + #[doc = "Bit 5 - Read receive FIFO bit 5 or write transmit FIFO bit 5"] + #[inline(always)] + pub fn r5t5(&mut self) -> R5t5W { + R5t5W::new(self, 5) + } + #[doc = "Bit 6 - Read receive FIFO bit 6 or write transmit FIFO bit 6"] + #[inline(always)] + pub fn r6t6(&mut self) -> R6t6W { + R6t6W::new(self, 6) + } + #[doc = "Bit 7 - Read receive FIFO bit 7 or write transmit FIFO bit 7"] + #[inline(always)] + pub fn r7t7(&mut self) -> R7t7W { + R7t7W::new(self, 7) + } + #[doc = "Bit 8 - Read receive FIFO bit 8 or write transmit FIFO bit 8"] + #[inline(always)] + pub fn r8t8(&mut self) -> R8t8W { + R8t8W::new(self, 8) + } + #[doc = "Bit 9 - Read receive FIFO bit 9 or write transmit FIFO bit 9"] + #[inline(always)] + pub fn r9t9(&mut self) -> R9t9W { + R9t9W::new(self, 9) + } + #[doc = "Bit 13 - Frame Error Transmit Special Character"] + #[inline(always)] + pub fn fretsc(&mut self) -> FretscW { + FretscW::new(self, 13) + } +} +#[doc = "Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0x1000"] +impl crate::Resettable for DataSpec { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/mcxa276-pac/src/lpuart0/dataro.rs b/mcxa276-pac/src/lpuart0/dataro.rs new file mode 100644 index 000000000..92daa4a7b --- /dev/null +++ b/mcxa276-pac/src/lpuart0/dataro.rs @@ -0,0 +1,22 @@ +#[doc = "Register `DATARO` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - Receive Data"] +pub type DataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Receive Data"] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Data Read-Only\n\nYou can [`read`](crate::Reg::read) this register and get [`dataro::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataroSpec; +impl crate::RegisterSpec for DataroSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dataro::R`](R) reader structure"] +impl crate::Readable for DataroSpec {} +#[doc = "`reset()` method sets DATARO to value 0x1000"] +impl crate::Resettable for DataroSpec { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/mcxa276-pac/src/lpuart0/fifo.rs b/mcxa276-pac/src/lpuart0/fifo.rs new file mode 100644 index 000000000..9a6765726 --- /dev/null +++ b/mcxa276-pac/src/lpuart0/fifo.rs @@ -0,0 +1,948 @@ +#[doc = "Register `FIFO` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO` writer"] +pub type W = crate::W; +#[doc = "Receive FIFO Buffer Depth\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Rxfifosize { + #[doc = "0: 1"] + Fifo1 = 0, + #[doc = "1: 4"] + Fifo4 = 1, + #[doc = "2: 8"] + Fifo8 = 2, + #[doc = "3: 16"] + Fifo16 = 3, + #[doc = "4: 32"] + Fifo32 = 4, + #[doc = "5: 64"] + Fifo64 = 5, + #[doc = "6: 128"] + Fifo128 = 6, + #[doc = "7: 256"] + Fifo256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Rxfifosize) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Rxfifosize { + type Ux = u8; +} +impl crate::IsEnum for Rxfifosize {} +#[doc = "Field `RXFIFOSIZE` reader - Receive FIFO Buffer Depth"] +pub type RxfifosizeR = crate::FieldReader; +impl RxfifosizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxfifosize { + match self.bits { + 0 => Rxfifosize::Fifo1, + 1 => Rxfifosize::Fifo4, + 2 => Rxfifosize::Fifo8, + 3 => Rxfifosize::Fifo16, + 4 => Rxfifosize::Fifo32, + 5 => Rxfifosize::Fifo64, + 6 => Rxfifosize::Fifo128, + 7 => Rxfifosize::Fifo256, + _ => unreachable!(), + } + } + #[doc = "1"] + #[inline(always)] + pub fn is_fifo_1(&self) -> bool { + *self == Rxfifosize::Fifo1 + } + #[doc = "4"] + #[inline(always)] + pub fn is_fifo_4(&self) -> bool { + *self == Rxfifosize::Fifo4 + } + #[doc = "8"] + #[inline(always)] + pub fn is_fifo_8(&self) -> bool { + *self == Rxfifosize::Fifo8 + } + #[doc = "16"] + #[inline(always)] + pub fn is_fifo_16(&self) -> bool { + *self == Rxfifosize::Fifo16 + } + #[doc = "32"] + #[inline(always)] + pub fn is_fifo_32(&self) -> bool { + *self == Rxfifosize::Fifo32 + } + #[doc = "64"] + #[inline(always)] + pub fn is_fifo_64(&self) -> bool { + *self == Rxfifosize::Fifo64 + } + #[doc = "128"] + #[inline(always)] + pub fn is_fifo_128(&self) -> bool { + *self == Rxfifosize::Fifo128 + } + #[doc = "256"] + #[inline(always)] + pub fn is_fifo_256(&self) -> bool { + *self == Rxfifosize::Fifo256 + } +} +#[doc = "Receive FIFO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxfe { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXFE` reader - Receive FIFO Enable"] +pub type RxfeR = crate::BitReader; +impl RxfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxfe { + match self.bits { + false => Rxfe::Disabled, + true => Rxfe::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rxfe::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rxfe::Enabled + } +} +#[doc = "Field `RXFE` writer - Receive FIFO Enable"] +pub type RxfeW<'a, REG> = crate::BitWriter<'a, REG, Rxfe>; +impl<'a, REG> RxfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rxfe::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rxfe::Enabled) + } +} +#[doc = "Transmit FIFO Buffer Depth\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Txfifosize { + #[doc = "0: 1"] + Fifo1 = 0, + #[doc = "1: 4"] + Fifo4 = 1, + #[doc = "2: 8"] + Fifo8 = 2, + #[doc = "3: 16"] + Fifo16 = 3, + #[doc = "4: 32"] + Fifo32 = 4, + #[doc = "5: 64"] + Fifo64 = 5, + #[doc = "6: 128"] + Fifo128 = 6, + #[doc = "7: 256"] + Fifo256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Txfifosize) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Txfifosize { + type Ux = u8; +} +impl crate::IsEnum for Txfifosize {} +#[doc = "Field `TXFIFOSIZE` reader - Transmit FIFO Buffer Depth"] +pub type TxfifosizeR = crate::FieldReader; +impl TxfifosizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txfifosize { + match self.bits { + 0 => Txfifosize::Fifo1, + 1 => Txfifosize::Fifo4, + 2 => Txfifosize::Fifo8, + 3 => Txfifosize::Fifo16, + 4 => Txfifosize::Fifo32, + 5 => Txfifosize::Fifo64, + 6 => Txfifosize::Fifo128, + 7 => Txfifosize::Fifo256, + _ => unreachable!(), + } + } + #[doc = "1"] + #[inline(always)] + pub fn is_fifo_1(&self) -> bool { + *self == Txfifosize::Fifo1 + } + #[doc = "4"] + #[inline(always)] + pub fn is_fifo_4(&self) -> bool { + *self == Txfifosize::Fifo4 + } + #[doc = "8"] + #[inline(always)] + pub fn is_fifo_8(&self) -> bool { + *self == Txfifosize::Fifo8 + } + #[doc = "16"] + #[inline(always)] + pub fn is_fifo_16(&self) -> bool { + *self == Txfifosize::Fifo16 + } + #[doc = "32"] + #[inline(always)] + pub fn is_fifo_32(&self) -> bool { + *self == Txfifosize::Fifo32 + } + #[doc = "64"] + #[inline(always)] + pub fn is_fifo_64(&self) -> bool { + *self == Txfifosize::Fifo64 + } + #[doc = "128"] + #[inline(always)] + pub fn is_fifo_128(&self) -> bool { + *self == Txfifosize::Fifo128 + } + #[doc = "256"] + #[inline(always)] + pub fn is_fifo_256(&self) -> bool { + *self == Txfifosize::Fifo256 + } +} +#[doc = "Transmit FIFO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txfe { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXFE` reader - Transmit FIFO Enable"] +pub type TxfeR = crate::BitReader; +impl TxfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txfe { + match self.bits { + false => Txfe::Disabled, + true => Txfe::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Txfe::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Txfe::Enabled + } +} +#[doc = "Field `TXFE` writer - Transmit FIFO Enable"] +pub type TxfeW<'a, REG> = crate::BitWriter<'a, REG, Txfe>; +impl<'a, REG> TxfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Txfe::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Txfe::Enabled) + } +} +#[doc = "Receive FIFO Underflow Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxufe { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxufe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXUFE` reader - Receive FIFO Underflow Interrupt Enable"] +pub type RxufeR = crate::BitReader; +impl RxufeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxufe { + match self.bits { + false => Rxufe::Disabled, + true => Rxufe::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rxufe::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rxufe::Enabled + } +} +#[doc = "Field `RXUFE` writer - Receive FIFO Underflow Interrupt Enable"] +pub type RxufeW<'a, REG> = crate::BitWriter<'a, REG, Rxufe>; +impl<'a, REG> RxufeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rxufe::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rxufe::Enabled) + } +} +#[doc = "Transmit FIFO Overflow Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txofe { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txofe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXOFE` reader - Transmit FIFO Overflow Interrupt Enable"] +pub type TxofeR = crate::BitReader; +impl TxofeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txofe { + match self.bits { + false => Txofe::Disabled, + true => Txofe::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Txofe::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Txofe::Enabled + } +} +#[doc = "Field `TXOFE` writer - Transmit FIFO Overflow Interrupt Enable"] +pub type TxofeW<'a, REG> = crate::BitWriter<'a, REG, Txofe>; +impl<'a, REG> TxofeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Txofe::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Txofe::Enabled) + } +} +#[doc = "Receiver Idle Empty Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Rxiden { + #[doc = "0: Disable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle"] + Disabled = 0, + #[doc = "1: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for one character"] + Idle1 = 1, + #[doc = "2: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for two characters"] + Idle2 = 2, + #[doc = "3: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for four characters"] + Idle4 = 3, + #[doc = "4: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for eight characters"] + Idle8 = 4, + #[doc = "5: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters"] + Idle16 = 5, + #[doc = "6: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters"] + Idle32 = 6, + #[doc = "7: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters"] + Idle64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Rxiden) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Rxiden { + type Ux = u8; +} +impl crate::IsEnum for Rxiden {} +#[doc = "Field `RXIDEN` reader - Receiver Idle Empty Enable"] +pub type RxidenR = crate::FieldReader; +impl RxidenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxiden { + match self.bits { + 0 => Rxiden::Disabled, + 1 => Rxiden::Idle1, + 2 => Rxiden::Idle2, + 3 => Rxiden::Idle4, + 4 => Rxiden::Idle8, + 5 => Rxiden::Idle16, + 6 => Rxiden::Idle32, + 7 => Rxiden::Idle64, + _ => unreachable!(), + } + } + #[doc = "Disable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rxiden::Disabled + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for one character"] + #[inline(always)] + pub fn is_idle_1(&self) -> bool { + *self == Rxiden::Idle1 + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for two characters"] + #[inline(always)] + pub fn is_idle_2(&self) -> bool { + *self == Rxiden::Idle2 + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for four characters"] + #[inline(always)] + pub fn is_idle_4(&self) -> bool { + *self == Rxiden::Idle4 + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for eight characters"] + #[inline(always)] + pub fn is_idle_8(&self) -> bool { + *self == Rxiden::Idle8 + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters"] + #[inline(always)] + pub fn is_idle_16(&self) -> bool { + *self == Rxiden::Idle16 + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters"] + #[inline(always)] + pub fn is_idle_32(&self) -> bool { + *self == Rxiden::Idle32 + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters"] + #[inline(always)] + pub fn is_idle_64(&self) -> bool { + *self == Rxiden::Idle64 + } +} +#[doc = "Field `RXIDEN` writer - Receiver Idle Empty Enable"] +pub type RxidenW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rxiden, crate::Safe>; +impl<'a, REG> RxidenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rxiden::Disabled) + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for one character"] + #[inline(always)] + pub fn idle_1(self) -> &'a mut crate::W { + self.variant(Rxiden::Idle1) + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for two characters"] + #[inline(always)] + pub fn idle_2(self) -> &'a mut crate::W { + self.variant(Rxiden::Idle2) + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for four characters"] + #[inline(always)] + pub fn idle_4(self) -> &'a mut crate::W { + self.variant(Rxiden::Idle4) + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for eight characters"] + #[inline(always)] + pub fn idle_8(self) -> &'a mut crate::W { + self.variant(Rxiden::Idle8) + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters"] + #[inline(always)] + pub fn idle_16(self) -> &'a mut crate::W { + self.variant(Rxiden::Idle16) + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters"] + #[inline(always)] + pub fn idle_32(self) -> &'a mut crate::W { + self.variant(Rxiden::Idle32) + } + #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters"] + #[inline(always)] + pub fn idle_64(self) -> &'a mut crate::W { + self.variant(Rxiden::Idle64) + } +} +#[doc = "Receive FIFO Flush\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxflush { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: All data flushed out"] + RxfifoRst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxflush) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXFLUSH` reader - Receive FIFO Flush"] +pub type RxflushR = crate::BitReader; +impl RxflushR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxflush { + match self.bits { + false => Rxflush::NoEffect, + true => Rxflush::RxfifoRst, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rxflush::NoEffect + } + #[doc = "All data flushed out"] + #[inline(always)] + pub fn is_rxfifo_rst(&self) -> bool { + *self == Rxflush::RxfifoRst + } +} +#[doc = "Field `RXFLUSH` writer - Receive FIFO Flush"] +pub type RxflushW<'a, REG> = crate::BitWriter<'a, REG, Rxflush>; +impl<'a, REG> RxflushW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rxflush::NoEffect) + } + #[doc = "All data flushed out"] + #[inline(always)] + pub fn rxfifo_rst(self) -> &'a mut crate::W { + self.variant(Rxflush::RxfifoRst) + } +} +#[doc = "Transmit FIFO Flush\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txflush { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: All data flushed out"] + TxfifoRst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txflush) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXFLUSH` reader - Transmit FIFO Flush"] +pub type TxflushR = crate::BitReader; +impl TxflushR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txflush { + match self.bits { + false => Txflush::NoEffect, + true => Txflush::TxfifoRst, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Txflush::NoEffect + } + #[doc = "All data flushed out"] + #[inline(always)] + pub fn is_txfifo_rst(&self) -> bool { + *self == Txflush::TxfifoRst + } +} +#[doc = "Field `TXFLUSH` writer - Transmit FIFO Flush"] +pub type TxflushW<'a, REG> = crate::BitWriter<'a, REG, Txflush>; +impl<'a, REG> TxflushW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Txflush::NoEffect) + } + #[doc = "All data flushed out"] + #[inline(always)] + pub fn txfifo_rst(self) -> &'a mut crate::W { + self.variant(Txflush::TxfifoRst) + } +} +#[doc = "Receiver FIFO Underflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxuf { + #[doc = "0: No underflow"] + NoUnderflow = 0, + #[doc = "1: Underflow"] + Underflow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxuf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXUF` reader - Receiver FIFO Underflow Flag"] +pub type RxufR = crate::BitReader; +impl RxufR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxuf { + match self.bits { + false => Rxuf::NoUnderflow, + true => Rxuf::Underflow, + } + } + #[doc = "No underflow"] + #[inline(always)] + pub fn is_no_underflow(&self) -> bool { + *self == Rxuf::NoUnderflow + } + #[doc = "Underflow"] + #[inline(always)] + pub fn is_underflow(&self) -> bool { + *self == Rxuf::Underflow + } +} +#[doc = "Field `RXUF` writer - Receiver FIFO Underflow Flag"] +pub type RxufW<'a, REG> = crate::BitWriter1C<'a, REG, Rxuf>; +impl<'a, REG> RxufW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No underflow"] + #[inline(always)] + pub fn no_underflow(self) -> &'a mut crate::W { + self.variant(Rxuf::NoUnderflow) + } + #[doc = "Underflow"] + #[inline(always)] + pub fn underflow(self) -> &'a mut crate::W { + self.variant(Rxuf::Underflow) + } +} +#[doc = "Transmitter FIFO Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txof { + #[doc = "0: No overflow"] + NoOverflow = 0, + #[doc = "1: Overflow"] + Overflow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXOF` reader - Transmitter FIFO Overflow Flag"] +pub type TxofR = crate::BitReader; +impl TxofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txof { + match self.bits { + false => Txof::NoOverflow, + true => Txof::Overflow, + } + } + #[doc = "No overflow"] + #[inline(always)] + pub fn is_no_overflow(&self) -> bool { + *self == Txof::NoOverflow + } + #[doc = "Overflow"] + #[inline(always)] + pub fn is_overflow(&self) -> bool { + *self == Txof::Overflow + } +} +#[doc = "Field `TXOF` writer - Transmitter FIFO Overflow Flag"] +pub type TxofW<'a, REG> = crate::BitWriter1C<'a, REG, Txof>; +impl<'a, REG> TxofW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overflow"] + #[inline(always)] + pub fn no_overflow(self) -> &'a mut crate::W { + self.variant(Txof::NoOverflow) + } + #[doc = "Overflow"] + #[inline(always)] + pub fn overflow(self) -> &'a mut crate::W { + self.variant(Txof::Overflow) + } +} +#[doc = "Receive FIFO Or Buffer Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxempt { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxempt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEMPT` reader - Receive FIFO Or Buffer Empty"] +pub type RxemptR = crate::BitReader; +impl RxemptR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxempt { + match self.bits { + false => Rxempt::NotEmpty, + true => Rxempt::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Rxempt::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Rxempt::Empty + } +} +#[doc = "Transmit FIFO Or Buffer Empty\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txempt { + #[doc = "0: Not empty"] + NotEmpty = 0, + #[doc = "1: Empty"] + Empty = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txempt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXEMPT` reader - Transmit FIFO Or Buffer Empty"] +pub type TxemptR = crate::BitReader; +impl TxemptR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txempt { + match self.bits { + false => Txempt::NotEmpty, + true => Txempt::Empty, + } + } + #[doc = "Not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == Txempt::NotEmpty + } + #[doc = "Empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == Txempt::Empty + } +} +impl R { + #[doc = "Bits 0:2 - Receive FIFO Buffer Depth"] + #[inline(always)] + pub fn rxfifosize(&self) -> RxfifosizeR { + RxfifosizeR::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Receive FIFO Enable"] + #[inline(always)] + pub fn rxfe(&self) -> RxfeR { + RxfeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Transmit FIFO Buffer Depth"] + #[inline(always)] + pub fn txfifosize(&self) -> TxfifosizeR { + TxfifosizeR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Transmit FIFO Enable"] + #[inline(always)] + pub fn txfe(&self) -> TxfeR { + TxfeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Receive FIFO Underflow Interrupt Enable"] + #[inline(always)] + pub fn rxufe(&self) -> RxufeR { + RxufeR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Transmit FIFO Overflow Interrupt Enable"] + #[inline(always)] + pub fn txofe(&self) -> TxofeR { + TxofeR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:12 - Receiver Idle Empty Enable"] + #[inline(always)] + pub fn rxiden(&self) -> RxidenR { + RxidenR::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bit 14 - Receive FIFO Flush"] + #[inline(always)] + pub fn rxflush(&self) -> RxflushR { + RxflushR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Transmit FIFO Flush"] + #[inline(always)] + pub fn txflush(&self) -> TxflushR { + TxflushR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Receiver FIFO Underflow Flag"] + #[inline(always)] + pub fn rxuf(&self) -> RxufR { + RxufR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Transmitter FIFO Overflow Flag"] + #[inline(always)] + pub fn txof(&self) -> TxofR { + TxofR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 22 - Receive FIFO Or Buffer Empty"] + #[inline(always)] + pub fn rxempt(&self) -> RxemptR { + RxemptR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Transmit FIFO Or Buffer Empty"] + #[inline(always)] + pub fn txempt(&self) -> TxemptR { + TxemptR::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Receive FIFO Enable"] + #[inline(always)] + pub fn rxfe(&mut self) -> RxfeW { + RxfeW::new(self, 3) + } + #[doc = "Bit 7 - Transmit FIFO Enable"] + #[inline(always)] + pub fn txfe(&mut self) -> TxfeW { + TxfeW::new(self, 7) + } + #[doc = "Bit 8 - Receive FIFO Underflow Interrupt Enable"] + #[inline(always)] + pub fn rxufe(&mut self) -> RxufeW { + RxufeW::new(self, 8) + } + #[doc = "Bit 9 - Transmit FIFO Overflow Interrupt Enable"] + #[inline(always)] + pub fn txofe(&mut self) -> TxofeW { + TxofeW::new(self, 9) + } + #[doc = "Bits 10:12 - Receiver Idle Empty Enable"] + #[inline(always)] + pub fn rxiden(&mut self) -> RxidenW { + RxidenW::new(self, 10) + } + #[doc = "Bit 14 - Receive FIFO Flush"] + #[inline(always)] + pub fn rxflush(&mut self) -> RxflushW { + RxflushW::new(self, 14) + } + #[doc = "Bit 15 - Transmit FIFO Flush"] + #[inline(always)] + pub fn txflush(&mut self) -> TxflushW { + TxflushW::new(self, 15) + } + #[doc = "Bit 16 - Receiver FIFO Underflow Flag"] + #[inline(always)] + pub fn rxuf(&mut self) -> RxufW { + RxufW::new(self, 16) + } + #[doc = "Bit 17 - Transmitter FIFO Overflow Flag"] + #[inline(always)] + pub fn txof(&mut self) -> TxofW { + TxofW::new(self, 17) + } +} +#[doc = "FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoSpec; +impl crate::RegisterSpec for FifoSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FifoSpec {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] +impl crate::Writable for FifoSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0003_0000; +} +#[doc = "`reset()` method sets FIFO to value 0x00c0_0011"] +impl crate::Resettable for FifoSpec { + const RESET_VALUE: u32 = 0x00c0_0011; +} diff --git a/mcxa276-pac/src/lpuart0/global.rs b/mcxa276-pac/src/lpuart0/global.rs new file mode 100644 index 000000000..d91df132d --- /dev/null +++ b/mcxa276-pac/src/lpuart0/global.rs @@ -0,0 +1,84 @@ +#[doc = "Register `GLOBAL` reader"] +pub type R = crate::R; +#[doc = "Register `GLOBAL` writer"] +pub type W = crate::W; +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rst { + #[doc = "0: Not reset"] + NoEffect = 0, + #[doc = "1: Reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RST` reader - Software Reset"] +pub type RstR = crate::BitReader; +impl RstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rst { + match self.bits { + false => Rst::NoEffect, + true => Rst::Reset, + } + } + #[doc = "Not reset"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Rst::NoEffect + } + #[doc = "Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Rst::Reset + } +} +#[doc = "Field `RST` writer - Software Reset"] +pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; +impl<'a, REG> RstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not reset"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Rst::NoEffect) + } + #[doc = "Reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Rst::Reset) + } +} +impl R { + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&self) -> RstR { + RstR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Software Reset"] + #[inline(always)] + pub fn rst(&mut self) -> RstW { + RstW::new(self, 1) + } +} +#[doc = "Global\n\nYou can [`read`](crate::Reg::read) this register and get [`global::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GlobalSpec; +impl crate::RegisterSpec for GlobalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`global::R`](R) reader structure"] +impl crate::Readable for GlobalSpec {} +#[doc = "`write(|w| ..)` method takes [`global::W`](W) writer structure"] +impl crate::Writable for GlobalSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GLOBAL to value 0"] +impl crate::Resettable for GlobalSpec {} diff --git a/mcxa276-pac/src/lpuart0/match_.rs b/mcxa276-pac/src/lpuart0/match_.rs new file mode 100644 index 000000000..50b748a7d --- /dev/null +++ b/mcxa276-pac/src/lpuart0/match_.rs @@ -0,0 +1,49 @@ +#[doc = "Register `MATCH` reader"] +pub type R = crate::R; +#[doc = "Register `MATCH` writer"] +pub type W = crate::W; +#[doc = "Field `MA1` reader - Match Address 1"] +pub type Ma1R = crate::FieldReader; +#[doc = "Field `MA1` writer - Match Address 1"] +pub type Ma1W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `MA2` reader - Match Address 2"] +pub type Ma2R = crate::FieldReader; +#[doc = "Field `MA2` writer - Match Address 2"] +pub type Ma2W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Match Address 1"] + #[inline(always)] + pub fn ma1(&self) -> Ma1R { + Ma1R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:25 - Match Address 2"] + #[inline(always)] + pub fn ma2(&self) -> Ma2R { + Ma2R::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Match Address 1"] + #[inline(always)] + pub fn ma1(&mut self) -> Ma1W { + Ma1W::new(self, 0) + } + #[doc = "Bits 16:25 - Match Address 2"] + #[inline(always)] + pub fn ma2(&mut self) -> Ma2W { + Ma2W::new(self, 16) + } +} +#[doc = "Match Address\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MatchSpec; +impl crate::RegisterSpec for MatchSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`match_::R`](R) reader structure"] +impl crate::Readable for MatchSpec {} +#[doc = "`write(|w| ..)` method takes [`match_::W`](W) writer structure"] +impl crate::Writable for MatchSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MATCH to value 0"] +impl crate::Resettable for MatchSpec {} diff --git a/mcxa276-pac/src/lpuart0/modir.rs b/mcxa276-pac/src/lpuart0/modir.rs new file mode 100644 index 000000000..90d5757c3 --- /dev/null +++ b/mcxa276-pac/src/lpuart0/modir.rs @@ -0,0 +1,572 @@ +#[doc = "Register `MODIR` reader"] +pub type R = crate::R; +#[doc = "Register `MODIR` writer"] +pub type W = crate::W; +#[doc = "Transmitter CTS Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txctse { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txctse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXCTSE` reader - Transmitter CTS Enable"] +pub type TxctseR = crate::BitReader; +impl TxctseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txctse { + match self.bits { + false => Txctse::Disabled, + true => Txctse::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Txctse::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Txctse::Enabled + } +} +#[doc = "Field `TXCTSE` writer - Transmitter CTS Enable"] +pub type TxctseW<'a, REG> = crate::BitWriter<'a, REG, Txctse>; +impl<'a, REG> TxctseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Txctse::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Txctse::Enabled) + } +} +#[doc = "Transmitter RTS Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txrtse { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txrtse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXRTSE` reader - Transmitter RTS Enable"] +pub type TxrtseR = crate::BitReader; +impl TxrtseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txrtse { + match self.bits { + false => Txrtse::Disabled, + true => Txrtse::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Txrtse::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Txrtse::Enabled + } +} +#[doc = "Field `TXRTSE` writer - Transmitter RTS Enable"] +pub type TxrtseW<'a, REG> = crate::BitWriter<'a, REG, Txrtse>; +impl<'a, REG> TxrtseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Txrtse::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Txrtse::Enabled) + } +} +#[doc = "Transmitter RTS Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txrtspol { + #[doc = "0: Active low"] + Low = 0, + #[doc = "1: Active high"] + High = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txrtspol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXRTSPOL` reader - Transmitter RTS Polarity"] +pub type TxrtspolR = crate::BitReader; +impl TxrtspolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txrtspol { + match self.bits { + false => Txrtspol::Low, + true => Txrtspol::High, + } + } + #[doc = "Active low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == Txrtspol::Low + } + #[doc = "Active high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == Txrtspol::High + } +} +#[doc = "Field `TXRTSPOL` writer - Transmitter RTS Polarity"] +pub type TxrtspolW<'a, REG> = crate::BitWriter<'a, REG, Txrtspol>; +impl<'a, REG> TxrtspolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(Txrtspol::Low) + } + #[doc = "Active high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(Txrtspol::High) + } +} +#[doc = "Receiver RTS Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxrtse { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxrtse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXRTSE` reader - Receiver RTS Enable"] +pub type RxrtseR = crate::BitReader; +impl RxrtseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxrtse { + match self.bits { + false => Rxrtse::Disabled, + true => Rxrtse::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rxrtse::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rxrtse::Enabled + } +} +#[doc = "Field `RXRTSE` writer - Receiver RTS Enable"] +pub type RxrtseW<'a, REG> = crate::BitWriter<'a, REG, Rxrtse>; +impl<'a, REG> RxrtseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rxrtse::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rxrtse::Enabled) + } +} +#[doc = "Transmit CTS Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txctsc { + #[doc = "0: Sampled at the start of each character"] + Start = 0, + #[doc = "1: Sampled when the transmitter is idle"] + Idle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txctsc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXCTSC` reader - Transmit CTS Configuration"] +pub type TxctscR = crate::BitReader; +impl TxctscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txctsc { + match self.bits { + false => Txctsc::Start, + true => Txctsc::Idle, + } + } + #[doc = "Sampled at the start of each character"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == Txctsc::Start + } + #[doc = "Sampled when the transmitter is idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Txctsc::Idle + } +} +#[doc = "Field `TXCTSC` writer - Transmit CTS Configuration"] +pub type TxctscW<'a, REG> = crate::BitWriter<'a, REG, Txctsc>; +impl<'a, REG> TxctscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Sampled at the start of each character"] + #[inline(always)] + pub fn start(self) -> &'a mut crate::W { + self.variant(Txctsc::Start) + } + #[doc = "Sampled when the transmitter is idle"] + #[inline(always)] + pub fn idle(self) -> &'a mut crate::W { + self.variant(Txctsc::Idle) + } +} +#[doc = "Transmit CTS Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txctssrc { + #[doc = "0: The CTS_B pin"] + Cts = 0, + #[doc = "1: An internal connection to the receiver address match result"] + Match = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txctssrc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXCTSSRC` reader - Transmit CTS Source"] +pub type TxctssrcR = crate::BitReader; +impl TxctssrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Txctssrc { + match self.bits { + false => Txctssrc::Cts, + true => Txctssrc::Match, + } + } + #[doc = "The CTS_B pin"] + #[inline(always)] + pub fn is_cts(&self) -> bool { + *self == Txctssrc::Cts + } + #[doc = "An internal connection to the receiver address match result"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Txctssrc::Match + } +} +#[doc = "Field `TXCTSSRC` writer - Transmit CTS Source"] +pub type TxctssrcW<'a, REG> = crate::BitWriter<'a, REG, Txctssrc>; +impl<'a, REG> TxctssrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The CTS_B pin"] + #[inline(always)] + pub fn cts(self) -> &'a mut crate::W { + self.variant(Txctssrc::Cts) + } + #[doc = "An internal connection to the receiver address match result"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Txctssrc::Match) + } +} +#[doc = "Field `RTSWATER` reader - Receive RTS Configuration"] +pub type RtswaterR = crate::FieldReader; +#[doc = "Field `RTSWATER` writer - Receive RTS Configuration"] +pub type RtswaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Transmitter Narrow Pulse\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tnp { + #[doc = "0: 1 / OSR"] + OneSample = 0, + #[doc = "1: 2 / OSR"] + TwoSample = 1, + #[doc = "2: 3 / OSR"] + ThreeSample = 2, + #[doc = "3: 4 / OSR"] + FourSample = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tnp) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tnp { + type Ux = u8; +} +impl crate::IsEnum for Tnp {} +#[doc = "Field `TNP` reader - Transmitter Narrow Pulse"] +pub type TnpR = crate::FieldReader; +impl TnpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tnp { + match self.bits { + 0 => Tnp::OneSample, + 1 => Tnp::TwoSample, + 2 => Tnp::ThreeSample, + 3 => Tnp::FourSample, + _ => unreachable!(), + } + } + #[doc = "1 / OSR"] + #[inline(always)] + pub fn is_one_sample(&self) -> bool { + *self == Tnp::OneSample + } + #[doc = "2 / OSR"] + #[inline(always)] + pub fn is_two_sample(&self) -> bool { + *self == Tnp::TwoSample + } + #[doc = "3 / OSR"] + #[inline(always)] + pub fn is_three_sample(&self) -> bool { + *self == Tnp::ThreeSample + } + #[doc = "4 / OSR"] + #[inline(always)] + pub fn is_four_sample(&self) -> bool { + *self == Tnp::FourSample + } +} +#[doc = "Field `TNP` writer - Transmitter Narrow Pulse"] +pub type TnpW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tnp, crate::Safe>; +impl<'a, REG> TnpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1 / OSR"] + #[inline(always)] + pub fn one_sample(self) -> &'a mut crate::W { + self.variant(Tnp::OneSample) + } + #[doc = "2 / OSR"] + #[inline(always)] + pub fn two_sample(self) -> &'a mut crate::W { + self.variant(Tnp::TwoSample) + } + #[doc = "3 / OSR"] + #[inline(always)] + pub fn three_sample(self) -> &'a mut crate::W { + self.variant(Tnp::ThreeSample) + } + #[doc = "4 / OSR"] + #[inline(always)] + pub fn four_sample(self) -> &'a mut crate::W { + self.variant(Tnp::FourSample) + } +} +#[doc = "IR Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Iren { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Iren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IREN` reader - IR Enable"] +pub type IrenR = crate::BitReader; +impl IrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Iren { + match self.bits { + false => Iren::Disabled, + true => Iren::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Iren::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Iren::Enabled + } +} +#[doc = "Field `IREN` writer - IR Enable"] +pub type IrenW<'a, REG> = crate::BitWriter<'a, REG, Iren>; +impl<'a, REG> IrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Iren::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Iren::Enabled) + } +} +impl R { + #[doc = "Bit 0 - Transmitter CTS Enable"] + #[inline(always)] + pub fn txctse(&self) -> TxctseR { + TxctseR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmitter RTS Enable"] + #[inline(always)] + pub fn txrtse(&self) -> TxrtseR { + TxrtseR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmitter RTS Polarity"] + #[inline(always)] + pub fn txrtspol(&self) -> TxrtspolR { + TxrtspolR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receiver RTS Enable"] + #[inline(always)] + pub fn rxrtse(&self) -> RxrtseR { + RxrtseR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Transmit CTS Configuration"] + #[inline(always)] + pub fn txctsc(&self) -> TxctscR { + TxctscR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit CTS Source"] + #[inline(always)] + pub fn txctssrc(&self) -> TxctssrcR { + TxctssrcR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 8:9 - Receive RTS Configuration"] + #[inline(always)] + pub fn rtswater(&self) -> RtswaterR { + RtswaterR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 16:17 - Transmitter Narrow Pulse"] + #[inline(always)] + pub fn tnp(&self) -> TnpR { + TnpR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - IR Enable"] + #[inline(always)] + pub fn iren(&self) -> IrenR { + IrenR::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmitter CTS Enable"] + #[inline(always)] + pub fn txctse(&mut self) -> TxctseW { + TxctseW::new(self, 0) + } + #[doc = "Bit 1 - Transmitter RTS Enable"] + #[inline(always)] + pub fn txrtse(&mut self) -> TxrtseW { + TxrtseW::new(self, 1) + } + #[doc = "Bit 2 - Transmitter RTS Polarity"] + #[inline(always)] + pub fn txrtspol(&mut self) -> TxrtspolW { + TxrtspolW::new(self, 2) + } + #[doc = "Bit 3 - Receiver RTS Enable"] + #[inline(always)] + pub fn rxrtse(&mut self) -> RxrtseW { + RxrtseW::new(self, 3) + } + #[doc = "Bit 4 - Transmit CTS Configuration"] + #[inline(always)] + pub fn txctsc(&mut self) -> TxctscW { + TxctscW::new(self, 4) + } + #[doc = "Bit 5 - Transmit CTS Source"] + #[inline(always)] + pub fn txctssrc(&mut self) -> TxctssrcW { + TxctssrcW::new(self, 5) + } + #[doc = "Bits 8:9 - Receive RTS Configuration"] + #[inline(always)] + pub fn rtswater(&mut self) -> RtswaterW { + RtswaterW::new(self, 8) + } + #[doc = "Bits 16:17 - Transmitter Narrow Pulse"] + #[inline(always)] + pub fn tnp(&mut self) -> TnpW { + TnpW::new(self, 16) + } + #[doc = "Bit 18 - IR Enable"] + #[inline(always)] + pub fn iren(&mut self) -> IrenW { + IrenW::new(self, 18) + } +} +#[doc = "MODEM IrDA\n\nYou can [`read`](crate::Reg::read) this register and get [`modir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ModirSpec; +impl crate::RegisterSpec for ModirSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`modir::R`](R) reader structure"] +impl crate::Readable for ModirSpec {} +#[doc = "`write(|w| ..)` method takes [`modir::W`](W) writer structure"] +impl crate::Writable for ModirSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MODIR to value 0"] +impl crate::Resettable for ModirSpec {} diff --git a/mcxa276-pac/src/lpuart0/param.rs b/mcxa276-pac/src/lpuart0/param.rs new file mode 100644 index 000000000..083fea641 --- /dev/null +++ b/mcxa276-pac/src/lpuart0/param.rs @@ -0,0 +1,29 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "Field `TXFIFO` reader - Transmit FIFO Size"] +pub type TxfifoR = crate::FieldReader; +#[doc = "Field `RXFIFO` reader - Receive FIFO Size"] +pub type RxfifoR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Transmit FIFO Size"] + #[inline(always)] + pub fn txfifo(&self) -> TxfifoR { + TxfifoR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Receive FIFO Size"] + #[inline(always)] + pub fn rxfifo(&self) -> RxfifoR { + RxfifoR::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x0202"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x0202; +} diff --git a/mcxa276-pac/src/lpuart0/pincfg.rs b/mcxa276-pac/src/lpuart0/pincfg.rs new file mode 100644 index 000000000..e83761535 --- /dev/null +++ b/mcxa276-pac/src/lpuart0/pincfg.rs @@ -0,0 +1,117 @@ +#[doc = "Register `PINCFG` reader"] +pub type R = crate::R; +#[doc = "Register `PINCFG` writer"] +pub type W = crate::W; +#[doc = "Trigger Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trgsel { + #[doc = "0: Input trigger disabled"] + Disabled = 0, + #[doc = "1: Input trigger used instead of the RXD pin input"] + TrgRxd = 1, + #[doc = "2: Input trigger used instead of the CTS_B pin input"] + TrgCts = 2, + #[doc = "3: Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"] + TrgTxd = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trgsel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trgsel { + type Ux = u8; +} +impl crate::IsEnum for Trgsel {} +#[doc = "Field `TRGSEL` reader - Trigger Select"] +pub type TrgselR = crate::FieldReader; +impl TrgselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trgsel { + match self.bits { + 0 => Trgsel::Disabled, + 1 => Trgsel::TrgRxd, + 2 => Trgsel::TrgCts, + 3 => Trgsel::TrgTxd, + _ => unreachable!(), + } + } + #[doc = "Input trigger disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Trgsel::Disabled + } + #[doc = "Input trigger used instead of the RXD pin input"] + #[inline(always)] + pub fn is_trg_rxd(&self) -> bool { + *self == Trgsel::TrgRxd + } + #[doc = "Input trigger used instead of the CTS_B pin input"] + #[inline(always)] + pub fn is_trg_cts(&self) -> bool { + *self == Trgsel::TrgCts + } + #[doc = "Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"] + #[inline(always)] + pub fn is_trg_txd(&self) -> bool { + *self == Trgsel::TrgTxd + } +} +#[doc = "Field `TRGSEL` writer - Trigger Select"] +pub type TrgselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trgsel, crate::Safe>; +impl<'a, REG> TrgselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Input trigger disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Trgsel::Disabled) + } + #[doc = "Input trigger used instead of the RXD pin input"] + #[inline(always)] + pub fn trg_rxd(self) -> &'a mut crate::W { + self.variant(Trgsel::TrgRxd) + } + #[doc = "Input trigger used instead of the CTS_B pin input"] + #[inline(always)] + pub fn trg_cts(self) -> &'a mut crate::W { + self.variant(Trgsel::TrgCts) + } + #[doc = "Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"] + #[inline(always)] + pub fn trg_txd(self) -> &'a mut crate::W { + self.variant(Trgsel::TrgTxd) + } +} +impl R { + #[doc = "Bits 0:1 - Trigger Select"] + #[inline(always)] + pub fn trgsel(&self) -> TrgselR { + TrgselR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Trigger Select"] + #[inline(always)] + pub fn trgsel(&mut self) -> TrgselW { + TrgselW::new(self, 0) + } +} +#[doc = "Pin Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pincfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pincfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PincfgSpec; +impl crate::RegisterSpec for PincfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pincfg::R`](R) reader structure"] +impl crate::Readable for PincfgSpec {} +#[doc = "`write(|w| ..)` method takes [`pincfg::W`](W) writer structure"] +impl crate::Writable for PincfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PINCFG to value 0"] +impl crate::Resettable for PincfgSpec {} diff --git a/mcxa276-pac/src/lpuart0/stat.rs b/mcxa276-pac/src/lpuart0/stat.rs new file mode 100644 index 000000000..ff07daf05 --- /dev/null +++ b/mcxa276-pac/src/lpuart0/stat.rs @@ -0,0 +1,1196 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Register `STAT` writer"] +pub type W = crate::W; +#[doc = "LIN Break Flag Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lbkfe { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lbkfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LBKFE` reader - LIN Break Flag Enable"] +pub type LbkfeR = crate::BitReader; +impl LbkfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lbkfe { + match self.bits { + false => Lbkfe::Disabled, + true => Lbkfe::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lbkfe::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lbkfe::Enabled + } +} +#[doc = "Field `LBKFE` writer - LIN Break Flag Enable"] +pub type LbkfeW<'a, REG> = crate::BitWriter<'a, REG, Lbkfe>; +impl<'a, REG> LbkfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lbkfe::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lbkfe::Enabled) + } +} +#[doc = "Address Mark Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ame { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ame) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AME` reader - Address Mark Enable"] +pub type AmeR = crate::BitReader; +impl AmeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ame { + match self.bits { + false => Ame::Disabled, + true => Ame::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ame::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ame::Enabled + } +} +#[doc = "Field `AME` writer - Address Mark Enable"] +pub type AmeW<'a, REG> = crate::BitWriter<'a, REG, Ame>; +impl<'a, REG> AmeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ame::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ame::Enabled) + } +} +#[doc = "Match 2 Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ma2f { + #[doc = "0: Not equal to MA2"] + Nomatch = 0, + #[doc = "1: Equal to MA2"] + Match = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ma2f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MA2F` reader - Match 2 Flag"] +pub type Ma2fR = crate::BitReader; +impl Ma2fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ma2f { + match self.bits { + false => Ma2f::Nomatch, + true => Ma2f::Match, + } + } + #[doc = "Not equal to MA2"] + #[inline(always)] + pub fn is_nomatch(&self) -> bool { + *self == Ma2f::Nomatch + } + #[doc = "Equal to MA2"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Ma2f::Match + } +} +#[doc = "Field `MA2F` writer - Match 2 Flag"] +pub type Ma2fW<'a, REG> = crate::BitWriter1C<'a, REG, Ma2f>; +impl<'a, REG> Ma2fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not equal to MA2"] + #[inline(always)] + pub fn nomatch(self) -> &'a mut crate::W { + self.variant(Ma2f::Nomatch) + } + #[doc = "Equal to MA2"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Ma2f::Match) + } +} +#[doc = "Match 1 Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ma1f { + #[doc = "0: Not equal to MA1"] + Nomatch = 0, + #[doc = "1: Equal to MA1"] + Match = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ma1f) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MA1F` reader - Match 1 Flag"] +pub type Ma1fR = crate::BitReader; +impl Ma1fR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ma1f { + match self.bits { + false => Ma1f::Nomatch, + true => Ma1f::Match, + } + } + #[doc = "Not equal to MA1"] + #[inline(always)] + pub fn is_nomatch(&self) -> bool { + *self == Ma1f::Nomatch + } + #[doc = "Equal to MA1"] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == Ma1f::Match + } +} +#[doc = "Field `MA1F` writer - Match 1 Flag"] +pub type Ma1fW<'a, REG> = crate::BitWriter1C<'a, REG, Ma1f>; +impl<'a, REG> Ma1fW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not equal to MA1"] + #[inline(always)] + pub fn nomatch(self) -> &'a mut crate::W { + self.variant(Ma1f::Nomatch) + } + #[doc = "Equal to MA1"] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(Ma1f::Match) + } +} +#[doc = "Parity Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pf { + #[doc = "0: No parity error detected"] + Noparity = 0, + #[doc = "1: Parity error detected"] + Parity = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PF` reader - Parity Error Flag"] +pub type PfR = crate::BitReader; +impl PfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pf { + match self.bits { + false => Pf::Noparity, + true => Pf::Parity, + } + } + #[doc = "No parity error detected"] + #[inline(always)] + pub fn is_noparity(&self) -> bool { + *self == Pf::Noparity + } + #[doc = "Parity error detected"] + #[inline(always)] + pub fn is_parity(&self) -> bool { + *self == Pf::Parity + } +} +#[doc = "Field `PF` writer - Parity Error Flag"] +pub type PfW<'a, REG> = crate::BitWriter1C<'a, REG, Pf>; +impl<'a, REG> PfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No parity error detected"] + #[inline(always)] + pub fn noparity(self) -> &'a mut crate::W { + self.variant(Pf::Noparity) + } + #[doc = "Parity error detected"] + #[inline(always)] + pub fn parity(self) -> &'a mut crate::W { + self.variant(Pf::Parity) + } +} +#[doc = "Framing Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fe { + #[doc = "0: No framing error detected (this does not guarantee that the framing is correct)"] + Noerror = 0, + #[doc = "1: Framing error detected"] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FE` reader - Framing Error Flag"] +pub type FeR = crate::BitReader; +impl FeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fe { + match self.bits { + false => Fe::Noerror, + true => Fe::Error, + } + } + #[doc = "No framing error detected (this does not guarantee that the framing is correct)"] + #[inline(always)] + pub fn is_noerror(&self) -> bool { + *self == Fe::Noerror + } + #[doc = "Framing error detected"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Fe::Error + } +} +#[doc = "Field `FE` writer - Framing Error Flag"] +pub type FeW<'a, REG> = crate::BitWriter1C<'a, REG, Fe>; +impl<'a, REG> FeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No framing error detected (this does not guarantee that the framing is correct)"] + #[inline(always)] + pub fn noerror(self) -> &'a mut crate::W { + self.variant(Fe::Noerror) + } + #[doc = "Framing error detected"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Fe::Error) + } +} +#[doc = "Noise Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nf { + #[doc = "0: No noise detected"] + Nonoise = 0, + #[doc = "1: Noise detected"] + Noise = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NF` reader - Noise Flag"] +pub type NfR = crate::BitReader; +impl NfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nf { + match self.bits { + false => Nf::Nonoise, + true => Nf::Noise, + } + } + #[doc = "No noise detected"] + #[inline(always)] + pub fn is_nonoise(&self) -> bool { + *self == Nf::Nonoise + } + #[doc = "Noise detected"] + #[inline(always)] + pub fn is_noise(&self) -> bool { + *self == Nf::Noise + } +} +#[doc = "Field `NF` writer - Noise Flag"] +pub type NfW<'a, REG> = crate::BitWriter1C<'a, REG, Nf>; +impl<'a, REG> NfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No noise detected"] + #[inline(always)] + pub fn nonoise(self) -> &'a mut crate::W { + self.variant(Nf::Nonoise) + } + #[doc = "Noise detected"] + #[inline(always)] + pub fn noise(self) -> &'a mut crate::W { + self.variant(Nf::Noise) + } +} +#[doc = "Receiver Overrun Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Or { + #[doc = "0: No overrun"] + NoOverrun = 0, + #[doc = "1: Receive overrun (new LPUART data is lost)"] + Overrun = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Or) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OR` reader - Receiver Overrun Flag"] +pub type OrR = crate::BitReader; +impl OrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Or { + match self.bits { + false => Or::NoOverrun, + true => Or::Overrun, + } + } + #[doc = "No overrun"] + #[inline(always)] + pub fn is_no_overrun(&self) -> bool { + *self == Or::NoOverrun + } + #[doc = "Receive overrun (new LPUART data is lost)"] + #[inline(always)] + pub fn is_overrun(&self) -> bool { + *self == Or::Overrun + } +} +#[doc = "Field `OR` writer - Receiver Overrun Flag"] +pub type OrW<'a, REG> = crate::BitWriter1C<'a, REG, Or>; +impl<'a, REG> OrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No overrun"] + #[inline(always)] + pub fn no_overrun(self) -> &'a mut crate::W { + self.variant(Or::NoOverrun) + } + #[doc = "Receive overrun (new LPUART data is lost)"] + #[inline(always)] + pub fn overrun(self) -> &'a mut crate::W { + self.variant(Or::Overrun) + } +} +#[doc = "Idle Line Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Idle { + #[doc = "0: Idle line detected"] + Noidle = 0, + #[doc = "1: Idle line not detected"] + Idle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Idle) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IDLE` reader - Idle Line Flag"] +pub type IdleR = crate::BitReader; +impl IdleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Idle { + match self.bits { + false => Idle::Noidle, + true => Idle::Idle, + } + } + #[doc = "Idle line detected"] + #[inline(always)] + pub fn is_noidle(&self) -> bool { + *self == Idle::Noidle + } + #[doc = "Idle line not detected"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Idle::Idle + } +} +#[doc = "Field `IDLE` writer - Idle Line Flag"] +pub type IdleW<'a, REG> = crate::BitWriter1C<'a, REG, Idle>; +impl<'a, REG> IdleW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Idle line detected"] + #[inline(always)] + pub fn noidle(self) -> &'a mut crate::W { + self.variant(Idle::Noidle) + } + #[doc = "Idle line not detected"] + #[inline(always)] + pub fn idle(self) -> &'a mut crate::W { + self.variant(Idle::Idle) + } +} +#[doc = "Receive Data Register Full Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdrf { + #[doc = "0: Equal to or less than watermark"] + NoRxdata = 0, + #[doc = "1: Greater than watermark"] + Rxdata = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdrf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDRF` reader - Receive Data Register Full Flag"] +pub type RdrfR = crate::BitReader; +impl RdrfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdrf { + match self.bits { + false => Rdrf::NoRxdata, + true => Rdrf::Rxdata, + } + } + #[doc = "Equal to or less than watermark"] + #[inline(always)] + pub fn is_no_rxdata(&self) -> bool { + *self == Rdrf::NoRxdata + } + #[doc = "Greater than watermark"] + #[inline(always)] + pub fn is_rxdata(&self) -> bool { + *self == Rdrf::Rxdata + } +} +#[doc = "Transmission Complete Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tc { + #[doc = "0: Transmitter active"] + Active = 0, + #[doc = "1: Transmitter idle"] + Complete = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TC` reader - Transmission Complete Flag"] +pub type TcR = crate::BitReader; +impl TcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tc { + match self.bits { + false => Tc::Active, + true => Tc::Complete, + } + } + #[doc = "Transmitter active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == Tc::Active + } + #[doc = "Transmitter idle"] + #[inline(always)] + pub fn is_complete(&self) -> bool { + *self == Tc::Complete + } +} +#[doc = "Transmit Data Register Empty Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdre { + #[doc = "0: Greater than watermark"] + Txdata = 0, + #[doc = "1: Equal to or less than watermark"] + NoTxdata = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDRE` reader - Transmit Data Register Empty Flag"] +pub type TdreR = crate::BitReader; +impl TdreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdre { + match self.bits { + false => Tdre::Txdata, + true => Tdre::NoTxdata, + } + } + #[doc = "Greater than watermark"] + #[inline(always)] + pub fn is_txdata(&self) -> bool { + *self == Tdre::Txdata + } + #[doc = "Equal to or less than watermark"] + #[inline(always)] + pub fn is_no_txdata(&self) -> bool { + *self == Tdre::NoTxdata + } +} +#[doc = "Receiver Active Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Raf { + #[doc = "0: Idle, waiting for a start bit"] + Idle = 0, + #[doc = "1: Receiver active (RXD pin input not idle)"] + Active = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Raf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAF` reader - Receiver Active Flag"] +pub type RafR = crate::BitReader; +impl RafR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Raf { + match self.bits { + false => Raf::Idle, + true => Raf::Active, + } + } + #[doc = "Idle, waiting for a start bit"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == Raf::Idle + } + #[doc = "Receiver active (RXD pin input not idle)"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == Raf::Active + } +} +#[doc = "LIN Break Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lbkde { + #[doc = "0: Disable"] + Disabled = 0, + #[doc = "1: Enable"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lbkde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LBKDE` reader - LIN Break Detection Enable"] +pub type LbkdeR = crate::BitReader; +impl LbkdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lbkde { + match self.bits { + false => Lbkde::Disabled, + true => Lbkde::Enabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lbkde::Disabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lbkde::Enabled + } +} +#[doc = "Field `LBKDE` writer - LIN Break Detection Enable"] +pub type LbkdeW<'a, REG> = crate::BitWriter<'a, REG, Lbkde>; +impl<'a, REG> LbkdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lbkde::Disabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lbkde::Enabled) + } +} +#[doc = "Break Character Generation Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Brk13 { + #[doc = "0: 9 to 13 bit times"] + Short = 0, + #[doc = "1: 12 to 15 bit times"] + Long = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Brk13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BRK13` reader - Break Character Generation Length"] +pub type Brk13R = crate::BitReader; +impl Brk13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Brk13 { + match self.bits { + false => Brk13::Short, + true => Brk13::Long, + } + } + #[doc = "9 to 13 bit times"] + #[inline(always)] + pub fn is_short(&self) -> bool { + *self == Brk13::Short + } + #[doc = "12 to 15 bit times"] + #[inline(always)] + pub fn is_long(&self) -> bool { + *self == Brk13::Long + } +} +#[doc = "Field `BRK13` writer - Break Character Generation Length"] +pub type Brk13W<'a, REG> = crate::BitWriter<'a, REG, Brk13>; +impl<'a, REG> Brk13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "9 to 13 bit times"] + #[inline(always)] + pub fn short(self) -> &'a mut crate::W { + self.variant(Brk13::Short) + } + #[doc = "12 to 15 bit times"] + #[inline(always)] + pub fn long(self) -> &'a mut crate::W { + self.variant(Brk13::Long) + } +} +#[doc = "Receive Wake Up Idle Detect\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rwuid { + #[doc = "0: STAT\\[IDLE\\] does not become 1"] + IdleNotset = 0, + #[doc = "1: STAT\\[IDLE\\] becomes 1"] + IdleSet = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rwuid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RWUID` reader - Receive Wake Up Idle Detect"] +pub type RwuidR = crate::BitReader; +impl RwuidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rwuid { + match self.bits { + false => Rwuid::IdleNotset, + true => Rwuid::IdleSet, + } + } + #[doc = "STAT\\[IDLE\\] does not become 1"] + #[inline(always)] + pub fn is_idle_notset(&self) -> bool { + *self == Rwuid::IdleNotset + } + #[doc = "STAT\\[IDLE\\] becomes 1"] + #[inline(always)] + pub fn is_idle_set(&self) -> bool { + *self == Rwuid::IdleSet + } +} +#[doc = "Field `RWUID` writer - Receive Wake Up Idle Detect"] +pub type RwuidW<'a, REG> = crate::BitWriter<'a, REG, Rwuid>; +impl<'a, REG> RwuidW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STAT\\[IDLE\\] does not become 1"] + #[inline(always)] + pub fn idle_notset(self) -> &'a mut crate::W { + self.variant(Rwuid::IdleNotset) + } + #[doc = "STAT\\[IDLE\\] becomes 1"] + #[inline(always)] + pub fn idle_set(self) -> &'a mut crate::W { + self.variant(Rwuid::IdleSet) + } +} +#[doc = "Receive Data Inversion\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxinv { + #[doc = "0: Inverted"] + NotInverted = 0, + #[doc = "1: Not inverted"] + Inverted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxinv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXINV` reader - Receive Data Inversion"] +pub type RxinvR = crate::BitReader; +impl RxinvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxinv { + match self.bits { + false => Rxinv::NotInverted, + true => Rxinv::Inverted, + } + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_not_inverted(&self) -> bool { + *self == Rxinv::NotInverted + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_inverted(&self) -> bool { + *self == Rxinv::Inverted + } +} +#[doc = "Field `RXINV` writer - Receive Data Inversion"] +pub type RxinvW<'a, REG> = crate::BitWriter<'a, REG, Rxinv>; +impl<'a, REG> RxinvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Inverted"] + #[inline(always)] + pub fn not_inverted(self) -> &'a mut crate::W { + self.variant(Rxinv::NotInverted) + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn inverted(self) -> &'a mut crate::W { + self.variant(Rxinv::Inverted) + } +} +#[doc = "MSB First\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Msbf { + #[doc = "0: LSB"] + LsbFirst = 0, + #[doc = "1: MSB"] + MsbFirst = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Msbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MSBF` reader - MSB First"] +pub type MsbfR = crate::BitReader; +impl MsbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Msbf { + match self.bits { + false => Msbf::LsbFirst, + true => Msbf::MsbFirst, + } + } + #[doc = "LSB"] + #[inline(always)] + pub fn is_lsb_first(&self) -> bool { + *self == Msbf::LsbFirst + } + #[doc = "MSB"] + #[inline(always)] + pub fn is_msb_first(&self) -> bool { + *self == Msbf::MsbFirst + } +} +#[doc = "Field `MSBF` writer - MSB First"] +pub type MsbfW<'a, REG> = crate::BitWriter<'a, REG, Msbf>; +impl<'a, REG> MsbfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "LSB"] + #[inline(always)] + pub fn lsb_first(self) -> &'a mut crate::W { + self.variant(Msbf::LsbFirst) + } + #[doc = "MSB"] + #[inline(always)] + pub fn msb_first(self) -> &'a mut crate::W { + self.variant(Msbf::MsbFirst) + } +} +#[doc = "RXD Pin Active Edge Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxedgif { + #[doc = "0: Not occurred"] + NoEdge = 0, + #[doc = "1: Occurred"] + Edge = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxedgif) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXEDGIF` reader - RXD Pin Active Edge Interrupt Flag"] +pub type RxedgifR = crate::BitReader; +impl RxedgifR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxedgif { + match self.bits { + false => Rxedgif::NoEdge, + true => Rxedgif::Edge, + } + } + #[doc = "Not occurred"] + #[inline(always)] + pub fn is_no_edge(&self) -> bool { + *self == Rxedgif::NoEdge + } + #[doc = "Occurred"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == Rxedgif::Edge + } +} +#[doc = "Field `RXEDGIF` writer - RXD Pin Active Edge Interrupt Flag"] +pub type RxedgifW<'a, REG> = crate::BitWriter1C<'a, REG, Rxedgif>; +impl<'a, REG> RxedgifW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not occurred"] + #[inline(always)] + pub fn no_edge(self) -> &'a mut crate::W { + self.variant(Rxedgif::NoEdge) + } + #[doc = "Occurred"] + #[inline(always)] + pub fn edge(self) -> &'a mut crate::W { + self.variant(Rxedgif::Edge) + } +} +#[doc = "LIN Break Detect Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lbkdif { + #[doc = "0: Not detected"] + NotDetected = 0, + #[doc = "1: Detected"] + Detected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lbkdif) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LBKDIF` reader - LIN Break Detect Interrupt Flag"] +pub type LbkdifR = crate::BitReader; +impl LbkdifR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lbkdif { + match self.bits { + false => Lbkdif::NotDetected, + true => Lbkdif::Detected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_not_detected(&self) -> bool { + *self == Lbkdif::NotDetected + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_detected(&self) -> bool { + *self == Lbkdif::Detected + } +} +#[doc = "Field `LBKDIF` writer - LIN Break Detect Interrupt Flag"] +pub type LbkdifW<'a, REG> = crate::BitWriter1C<'a, REG, Lbkdif>; +impl<'a, REG> LbkdifW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn not_detected(self) -> &'a mut crate::W { + self.variant(Lbkdif::NotDetected) + } + #[doc = "Detected"] + #[inline(always)] + pub fn detected(self) -> &'a mut crate::W { + self.variant(Lbkdif::Detected) + } +} +impl R { + #[doc = "Bit 0 - LIN Break Flag Enable"] + #[inline(always)] + pub fn lbkfe(&self) -> LbkfeR { + LbkfeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Address Mark Enable"] + #[inline(always)] + pub fn ame(&self) -> AmeR { + AmeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 14 - Match 2 Flag"] + #[inline(always)] + pub fn ma2f(&self) -> Ma2fR { + Ma2fR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Match 1 Flag"] + #[inline(always)] + pub fn ma1f(&self) -> Ma1fR { + Ma1fR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Parity Error Flag"] + #[inline(always)] + pub fn pf(&self) -> PfR { + PfR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Framing Error Flag"] + #[inline(always)] + pub fn fe(&self) -> FeR { + FeR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Noise Flag"] + #[inline(always)] + pub fn nf(&self) -> NfR { + NfR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Receiver Overrun Flag"] + #[inline(always)] + pub fn or(&self) -> OrR { + OrR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Idle Line Flag"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Receive Data Register Full Flag"] + #[inline(always)] + pub fn rdrf(&self) -> RdrfR { + RdrfR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Transmission Complete Flag"] + #[inline(always)] + pub fn tc(&self) -> TcR { + TcR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Transmit Data Register Empty Flag"] + #[inline(always)] + pub fn tdre(&self) -> TdreR { + TdreR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Receiver Active Flag"] + #[inline(always)] + pub fn raf(&self) -> RafR { + RafR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - LIN Break Detection Enable"] + #[inline(always)] + pub fn lbkde(&self) -> LbkdeR { + LbkdeR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Break Character Generation Length"] + #[inline(always)] + pub fn brk13(&self) -> Brk13R { + Brk13R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Receive Wake Up Idle Detect"] + #[inline(always)] + pub fn rwuid(&self) -> RwuidR { + RwuidR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Receive Data Inversion"] + #[inline(always)] + pub fn rxinv(&self) -> RxinvR { + RxinvR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - MSB First"] + #[inline(always)] + pub fn msbf(&self) -> MsbfR { + MsbfR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - RXD Pin Active Edge Interrupt Flag"] + #[inline(always)] + pub fn rxedgif(&self) -> RxedgifR { + RxedgifR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - LIN Break Detect Interrupt Flag"] + #[inline(always)] + pub fn lbkdif(&self) -> LbkdifR { + LbkdifR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LIN Break Flag Enable"] + #[inline(always)] + pub fn lbkfe(&mut self) -> LbkfeW { + LbkfeW::new(self, 0) + } + #[doc = "Bit 1 - Address Mark Enable"] + #[inline(always)] + pub fn ame(&mut self) -> AmeW { + AmeW::new(self, 1) + } + #[doc = "Bit 14 - Match 2 Flag"] + #[inline(always)] + pub fn ma2f(&mut self) -> Ma2fW { + Ma2fW::new(self, 14) + } + #[doc = "Bit 15 - Match 1 Flag"] + #[inline(always)] + pub fn ma1f(&mut self) -> Ma1fW { + Ma1fW::new(self, 15) + } + #[doc = "Bit 16 - Parity Error Flag"] + #[inline(always)] + pub fn pf(&mut self) -> PfW { + PfW::new(self, 16) + } + #[doc = "Bit 17 - Framing Error Flag"] + #[inline(always)] + pub fn fe(&mut self) -> FeW { + FeW::new(self, 17) + } + #[doc = "Bit 18 - Noise Flag"] + #[inline(always)] + pub fn nf(&mut self) -> NfW { + NfW::new(self, 18) + } + #[doc = "Bit 19 - Receiver Overrun Flag"] + #[inline(always)] + pub fn or(&mut self) -> OrW { + OrW::new(self, 19) + } + #[doc = "Bit 20 - Idle Line Flag"] + #[inline(always)] + pub fn idle(&mut self) -> IdleW { + IdleW::new(self, 20) + } + #[doc = "Bit 25 - LIN Break Detection Enable"] + #[inline(always)] + pub fn lbkde(&mut self) -> LbkdeW { + LbkdeW::new(self, 25) + } + #[doc = "Bit 26 - Break Character Generation Length"] + #[inline(always)] + pub fn brk13(&mut self) -> Brk13W { + Brk13W::new(self, 26) + } + #[doc = "Bit 27 - Receive Wake Up Idle Detect"] + #[inline(always)] + pub fn rwuid(&mut self) -> RwuidW { + RwuidW::new(self, 27) + } + #[doc = "Bit 28 - Receive Data Inversion"] + #[inline(always)] + pub fn rxinv(&mut self) -> RxinvW { + RxinvW::new(self, 28) + } + #[doc = "Bit 29 - MSB First"] + #[inline(always)] + pub fn msbf(&mut self) -> MsbfW { + MsbfW::new(self, 29) + } + #[doc = "Bit 30 - RXD Pin Active Edge Interrupt Flag"] + #[inline(always)] + pub fn rxedgif(&mut self) -> RxedgifW { + RxedgifW::new(self, 30) + } + #[doc = "Bit 31 - LIN Break Detect Interrupt Flag"] + #[inline(always)] + pub fn lbkdif(&mut self) -> LbkdifW { + LbkdifW::new(self, 31) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] +impl crate::Writable for StatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xc01f_c000; +} +#[doc = "`reset()` method sets STAT to value 0x00c0_0000"] +impl crate::Resettable for StatSpec { + const RESET_VALUE: u32 = 0x00c0_0000; +} diff --git a/mcxa276-pac/src/lpuart0/verid.rs b/mcxa276-pac/src/lpuart0/verid.rs new file mode 100644 index 000000000..eacb59d81 --- /dev/null +++ b/mcxa276-pac/src/lpuart0/verid.rs @@ -0,0 +1,76 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Identification Number\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "1: Standard feature set"] + Standard = 1, + #[doc = "3: Standard feature set with MODEM and IrDA support"] + Modem = 3, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Identification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Feature::Standard), + 3 => Some(Feature::Modem), + _ => None, + } + } + #[doc = "Standard feature set"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == Feature::Standard + } + #[doc = "Standard feature set with MODEM and IrDA support"] + #[inline(always)] + pub fn is_modem(&self) -> bool { + *self == Feature::Modem + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Identification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0405_0003"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0405_0003; +} diff --git a/mcxa276-pac/src/lpuart0/water.rs b/mcxa276-pac/src/lpuart0/water.rs new file mode 100644 index 000000000..1e868bfae --- /dev/null +++ b/mcxa276-pac/src/lpuart0/water.rs @@ -0,0 +1,63 @@ +#[doc = "Register `WATER` reader"] +pub type R = crate::R; +#[doc = "Register `WATER` writer"] +pub type W = crate::W; +#[doc = "Field `TXWATER` reader - Transmit Watermark"] +pub type TxwaterR = crate::FieldReader; +#[doc = "Field `TXWATER` writer - Transmit Watermark"] +pub type TxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TXCOUNT` reader - Transmit Counter"] +pub type TxcountR = crate::FieldReader; +#[doc = "Field `RXWATER` reader - Receive Watermark"] +pub type RxwaterR = crate::FieldReader; +#[doc = "Field `RXWATER` writer - Receive Watermark"] +pub type RxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RXCOUNT` reader - Receive Counter"] +pub type RxcountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Transmit Watermark"] + #[inline(always)] + pub fn txwater(&self) -> TxwaterR { + TxwaterR::new((self.bits & 3) as u8) + } + #[doc = "Bits 8:10 - Transmit Counter"] + #[inline(always)] + pub fn txcount(&self) -> TxcountR { + TxcountR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 16:17 - Receive Watermark"] + #[inline(always)] + pub fn rxwater(&self) -> RxwaterR { + RxwaterR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 24:26 - Receive Counter"] + #[inline(always)] + pub fn rxcount(&self) -> RxcountR { + RxcountR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Transmit Watermark"] + #[inline(always)] + pub fn txwater(&mut self) -> TxwaterW { + TxwaterW::new(self, 0) + } + #[doc = "Bits 16:17 - Receive Watermark"] + #[inline(always)] + pub fn rxwater(&mut self) -> RxwaterW { + RxwaterW::new(self, 16) + } +} +#[doc = "Watermark\n\nYou can [`read`](crate::Reg::read) this register and get [`water::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`water::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WaterSpec; +impl crate::RegisterSpec for WaterSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`water::R`](R) reader structure"] +impl crate::Readable for WaterSpec {} +#[doc = "`write(|w| ..)` method takes [`water::W`](W) writer structure"] +impl crate::Writable for WaterSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WATER to value 0"] +impl crate::Resettable for WaterSpec {} diff --git a/mcxa276-pac/src/mau0.rs b/mcxa276-pac/src/mau0.rs new file mode 100644 index 000000000..08b760472 --- /dev/null +++ b/mcxa276-pac/src/mau0.rs @@ -0,0 +1,119 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x10], + sys_ctlr: SysCtlr, + gexp_status_ie: GexpStatusIe, + gexp_status: GexpStatus, + _reserved3: [u8; 0x14], + op_ctrl: OpCtrl, + _reserved4: [u8; 0x04], + res_status_ie: ResStatusIe, + res_status: ResStatus, + res0: Res0, + res1: Res1, + res2: Res2, + res3: Res3, +} +impl RegisterBlock { + #[doc = "0x10 - System Control"] + #[inline(always)] + pub const fn sys_ctlr(&self) -> &SysCtlr { + &self.sys_ctlr + } + #[doc = "0x14 - General Exception Status Interrupt Enable"] + #[inline(always)] + pub const fn gexp_status_ie(&self) -> &GexpStatusIe { + &self.gexp_status_ie + } + #[doc = "0x18 - General Exception Status"] + #[inline(always)] + pub const fn gexp_status(&self) -> &GexpStatus { + &self.gexp_status + } + #[doc = "0x30 - Operation Control"] + #[inline(always)] + pub const fn op_ctrl(&self) -> &OpCtrl { + &self.op_ctrl + } + #[doc = "0x38 - Result Status Interrupt Enable"] + #[inline(always)] + pub const fn res_status_ie(&self) -> &ResStatusIe { + &self.res_status_ie + } + #[doc = "0x3c - Result Status"] + #[inline(always)] + pub const fn res_status(&self) -> &ResStatus { + &self.res_status + } + #[doc = "0x40 - Result Register 0"] + #[inline(always)] + pub const fn res0(&self) -> &Res0 { + &self.res0 + } + #[doc = "0x44 - Result Register 1"] + #[inline(always)] + pub const fn res1(&self) -> &Res1 { + &self.res1 + } + #[doc = "0x48 - Result Register 2"] + #[inline(always)] + pub const fn res2(&self) -> &Res2 { + &self.res2 + } + #[doc = "0x4c - Result Register 3"] + #[inline(always)] + pub const fn res3(&self) -> &Res3 { + &self.res3 + } +} +#[doc = "SYS_CTLR (rw) register accessor: System Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_ctlr`] module"] +#[doc(alias = "SYS_CTLR")] +pub type SysCtlr = crate::Reg; +#[doc = "System Control"] +pub mod sys_ctlr; +#[doc = "GEXP_STATUS_IE (rw) register accessor: General Exception Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status_ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status_ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gexp_status_ie`] module"] +#[doc(alias = "GEXP_STATUS_IE")] +pub type GexpStatusIe = crate::Reg; +#[doc = "General Exception Status Interrupt Enable"] +pub mod gexp_status_ie; +#[doc = "GEXP_STATUS (rw) register accessor: General Exception Status\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gexp_status`] module"] +#[doc(alias = "GEXP_STATUS")] +pub type GexpStatus = crate::Reg; +#[doc = "General Exception Status"] +pub mod gexp_status; +#[doc = "OP_CTRL (rw) register accessor: Operation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`op_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@op_ctrl`] module"] +#[doc(alias = "OP_CTRL")] +pub type OpCtrl = crate::Reg; +#[doc = "Operation Control"] +pub mod op_ctrl; +#[doc = "RES_STATUS_IE (rw) register accessor: Result Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status_ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status_ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res_status_ie`] module"] +#[doc(alias = "RES_STATUS_IE")] +pub type ResStatusIe = crate::Reg; +#[doc = "Result Status Interrupt Enable"] +pub mod res_status_ie; +#[doc = "RES_STATUS (rw) register accessor: Result Status\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res_status`] module"] +#[doc(alias = "RES_STATUS")] +pub type ResStatus = crate::Reg; +#[doc = "Result Status"] +pub mod res_status; +#[doc = "RES0 (rw) register accessor: Result Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`res0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res0`] module"] +#[doc(alias = "RES0")] +pub type Res0 = crate::Reg; +#[doc = "Result Register 0"] +pub mod res0; +#[doc = "RES1 (rw) register accessor: Result Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`res1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res1`] module"] +#[doc(alias = "RES1")] +pub type Res1 = crate::Reg; +#[doc = "Result Register 1"] +pub mod res1; +#[doc = "RES2 (rw) register accessor: Result Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`res2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res2`] module"] +#[doc(alias = "RES2")] +pub type Res2 = crate::Reg; +#[doc = "Result Register 2"] +pub mod res2; +#[doc = "RES3 (rw) register accessor: Result Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`res3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res3`] module"] +#[doc(alias = "RES3")] +pub type Res3 = crate::Reg; +#[doc = "Result Register 3"] +pub mod res3; diff --git a/mcxa276-pac/src/mau0/gexp_status.rs b/mcxa276-pac/src/mau0/gexp_status.rs new file mode 100644 index 000000000..4b3433bb2 --- /dev/null +++ b/mcxa276-pac/src/mau0/gexp_status.rs @@ -0,0 +1,84 @@ +#[doc = "Register `GEXP_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `GEXP_STATUS` writer"] +pub type W = crate::W; +#[doc = "Direct operation Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Error { + #[doc = "0: No error is generated."] + NoError = 0, + #[doc = "1: An error is generated."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Error) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` reader - Direct operation Error"] +pub type ErrorR = crate::BitReader; +impl ErrorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Error { + match self.bits { + false => Error::NoError, + true => Error::Error, + } + } + #[doc = "No error is generated."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Error::NoError + } + #[doc = "An error is generated."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Error::Error + } +} +#[doc = "Field `ERROR` writer - Direct operation Error"] +pub type ErrorW<'a, REG> = crate::BitWriter<'a, REG, Error>; +impl<'a, REG> ErrorW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error is generated."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Error::NoError) + } + #[doc = "An error is generated."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Error::Error) + } +} +impl R { + #[doc = "Bit 0 - Direct operation Error"] + #[inline(always)] + pub fn error(&self) -> ErrorR { + ErrorR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Direct operation Error"] + #[inline(always)] + pub fn error(&mut self) -> ErrorW { + ErrorW::new(self, 0) + } +} +#[doc = "General Exception Status\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GexpStatusSpec; +impl crate::RegisterSpec for GexpStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gexp_status::R`](R) reader structure"] +impl crate::Readable for GexpStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`gexp_status::W`](W) writer structure"] +impl crate::Writable for GexpStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GEXP_STATUS to value 0"] +impl crate::Resettable for GexpStatusSpec {} diff --git a/mcxa276-pac/src/mau0/gexp_status_ie.rs b/mcxa276-pac/src/mau0/gexp_status_ie.rs new file mode 100644 index 000000000..2250dad90 --- /dev/null +++ b/mcxa276-pac/src/mau0/gexp_status_ie.rs @@ -0,0 +1,84 @@ +#[doc = "Register `GEXP_STATUS_IE` reader"] +pub type R = crate::R; +#[doc = "Register `GEXP_STATUS_IE` writer"] +pub type W = crate::W; +#[doc = "Direct operation Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ErrorIe { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ErrorIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR_IE` reader - Direct operation Error Interrupt Enable"] +pub type ErrorIeR = crate::BitReader; +impl ErrorIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ErrorIe { + match self.bits { + false => ErrorIe::Disable, + true => ErrorIe::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == ErrorIe::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == ErrorIe::Enable + } +} +#[doc = "Field `ERROR_IE` writer - Direct operation Error Interrupt Enable"] +pub type ErrorIeW<'a, REG> = crate::BitWriter<'a, REG, ErrorIe>; +impl<'a, REG> ErrorIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ErrorIe::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ErrorIe::Enable) + } +} +impl R { + #[doc = "Bit 0 - Direct operation Error Interrupt Enable"] + #[inline(always)] + pub fn error_ie(&self) -> ErrorIeR { + ErrorIeR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Direct operation Error Interrupt Enable"] + #[inline(always)] + pub fn error_ie(&mut self) -> ErrorIeW { + ErrorIeW::new(self, 0) + } +} +#[doc = "General Exception Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status_ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status_ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GexpStatusIeSpec; +impl crate::RegisterSpec for GexpStatusIeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gexp_status_ie::R`](R) reader structure"] +impl crate::Readable for GexpStatusIeSpec {} +#[doc = "`write(|w| ..)` method takes [`gexp_status_ie::W`](W) writer structure"] +impl crate::Writable for GexpStatusIeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GEXP_STATUS_IE to value 0"] +impl crate::Resettable for GexpStatusIeSpec {} diff --git a/mcxa276-pac/src/mau0/op_ctrl.rs b/mcxa276-pac/src/mau0/op_ctrl.rs new file mode 100644 index 000000000..b3529d016 --- /dev/null +++ b/mcxa276-pac/src/mau0/op_ctrl.rs @@ -0,0 +1,657 @@ +#[doc = "Register `OP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `OP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Override RES0 Data Type Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OvdtEnRes0 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OvdtEnRes0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVDT_EN_RES0` reader - Override RES0 Data Type Enable"] +pub type OvdtEnRes0R = crate::BitReader; +impl OvdtEnRes0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtEnRes0 { + match self.bits { + false => OvdtEnRes0::Disable, + true => OvdtEnRes0::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OvdtEnRes0::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OvdtEnRes0::Enable + } +} +#[doc = "Field `OVDT_EN_RES0` writer - Override RES0 Data Type Enable"] +pub type OvdtEnRes0W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes0>; +impl<'a, REG> OvdtEnRes0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes0::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes0::Enable) + } +} +#[doc = "Override RES0 Data Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OvdtRes0 { + #[doc = "0: UINT"] + Uint = 0, + #[doc = "1: INT"] + Int = 1, + #[doc = "2: Q1.X"] + Q1X = 2, + #[doc = "3: FLOAT"] + Float = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OvdtRes0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OvdtRes0 { + type Ux = u8; +} +impl crate::IsEnum for OvdtRes0 {} +#[doc = "Field `OVDT_RES0` reader - Override RES0 Data Type"] +pub type OvdtRes0R = crate::FieldReader; +impl OvdtRes0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtRes0 { + match self.bits { + 0 => OvdtRes0::Uint, + 1 => OvdtRes0::Int, + 2 => OvdtRes0::Q1X, + 3 => OvdtRes0::Float, + _ => unreachable!(), + } + } + #[doc = "UINT"] + #[inline(always)] + pub fn is_uint(&self) -> bool { + *self == OvdtRes0::Uint + } + #[doc = "INT"] + #[inline(always)] + pub fn is_int(&self) -> bool { + *self == OvdtRes0::Int + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn is_q1_x(&self) -> bool { + *self == OvdtRes0::Q1X + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn is_float(&self) -> bool { + *self == OvdtRes0::Float + } +} +#[doc = "Field `OVDT_RES0` writer - Override RES0 Data Type"] +pub type OvdtRes0W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes0, crate::Safe>; +impl<'a, REG> OvdtRes0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "UINT"] + #[inline(always)] + pub fn uint(self) -> &'a mut crate::W { + self.variant(OvdtRes0::Uint) + } + #[doc = "INT"] + #[inline(always)] + pub fn int(self) -> &'a mut crate::W { + self.variant(OvdtRes0::Int) + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn q1_x(self) -> &'a mut crate::W { + self.variant(OvdtRes0::Q1X) + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn float(self) -> &'a mut crate::W { + self.variant(OvdtRes0::Float) + } +} +#[doc = "Override RES1 Data Type Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OvdtEnRes1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OvdtEnRes1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVDT_EN_RES1` reader - Override RES1 Data Type Enable"] +pub type OvdtEnRes1R = crate::BitReader; +impl OvdtEnRes1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtEnRes1 { + match self.bits { + false => OvdtEnRes1::Disable, + true => OvdtEnRes1::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OvdtEnRes1::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OvdtEnRes1::Enable + } +} +#[doc = "Field `OVDT_EN_RES1` writer - Override RES1 Data Type Enable"] +pub type OvdtEnRes1W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes1>; +impl<'a, REG> OvdtEnRes1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes1::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes1::Enable) + } +} +#[doc = "Override RES1 Data Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OvdtRes1 { + #[doc = "0: UINT"] + Uint = 0, + #[doc = "1: INT"] + Int = 1, + #[doc = "2: Q1.X"] + Q1X = 2, + #[doc = "3: FLOAT"] + Float = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OvdtRes1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OvdtRes1 { + type Ux = u8; +} +impl crate::IsEnum for OvdtRes1 {} +#[doc = "Field `OVDT_RES1` reader - Override RES1 Data Type"] +pub type OvdtRes1R = crate::FieldReader; +impl OvdtRes1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtRes1 { + match self.bits { + 0 => OvdtRes1::Uint, + 1 => OvdtRes1::Int, + 2 => OvdtRes1::Q1X, + 3 => OvdtRes1::Float, + _ => unreachable!(), + } + } + #[doc = "UINT"] + #[inline(always)] + pub fn is_uint(&self) -> bool { + *self == OvdtRes1::Uint + } + #[doc = "INT"] + #[inline(always)] + pub fn is_int(&self) -> bool { + *self == OvdtRes1::Int + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn is_q1_x(&self) -> bool { + *self == OvdtRes1::Q1X + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn is_float(&self) -> bool { + *self == OvdtRes1::Float + } +} +#[doc = "Field `OVDT_RES1` writer - Override RES1 Data Type"] +pub type OvdtRes1W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes1, crate::Safe>; +impl<'a, REG> OvdtRes1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "UINT"] + #[inline(always)] + pub fn uint(self) -> &'a mut crate::W { + self.variant(OvdtRes1::Uint) + } + #[doc = "INT"] + #[inline(always)] + pub fn int(self) -> &'a mut crate::W { + self.variant(OvdtRes1::Int) + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn q1_x(self) -> &'a mut crate::W { + self.variant(OvdtRes1::Q1X) + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn float(self) -> &'a mut crate::W { + self.variant(OvdtRes1::Float) + } +} +#[doc = "Override RES2 Data Type Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OvdtEnRes2 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OvdtEnRes2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVDT_EN_RES2` reader - Override RES2 Data Type Enable"] +pub type OvdtEnRes2R = crate::BitReader; +impl OvdtEnRes2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtEnRes2 { + match self.bits { + false => OvdtEnRes2::Disable, + true => OvdtEnRes2::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OvdtEnRes2::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OvdtEnRes2::Enable + } +} +#[doc = "Field `OVDT_EN_RES2` writer - Override RES2 Data Type Enable"] +pub type OvdtEnRes2W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes2>; +impl<'a, REG> OvdtEnRes2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes2::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes2::Enable) + } +} +#[doc = "Override RES2 Data Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OvdtRes2 { + #[doc = "0: UINT"] + Uint = 0, + #[doc = "1: INT"] + Int = 1, + #[doc = "2: Q1.X"] + Q1X = 2, + #[doc = "3: FLOAT"] + Float = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OvdtRes2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OvdtRes2 { + type Ux = u8; +} +impl crate::IsEnum for OvdtRes2 {} +#[doc = "Field `OVDT_RES2` reader - Override RES2 Data Type"] +pub type OvdtRes2R = crate::FieldReader; +impl OvdtRes2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtRes2 { + match self.bits { + 0 => OvdtRes2::Uint, + 1 => OvdtRes2::Int, + 2 => OvdtRes2::Q1X, + 3 => OvdtRes2::Float, + _ => unreachable!(), + } + } + #[doc = "UINT"] + #[inline(always)] + pub fn is_uint(&self) -> bool { + *self == OvdtRes2::Uint + } + #[doc = "INT"] + #[inline(always)] + pub fn is_int(&self) -> bool { + *self == OvdtRes2::Int + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn is_q1_x(&self) -> bool { + *self == OvdtRes2::Q1X + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn is_float(&self) -> bool { + *self == OvdtRes2::Float + } +} +#[doc = "Field `OVDT_RES2` writer - Override RES2 Data Type"] +pub type OvdtRes2W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes2, crate::Safe>; +impl<'a, REG> OvdtRes2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "UINT"] + #[inline(always)] + pub fn uint(self) -> &'a mut crate::W { + self.variant(OvdtRes2::Uint) + } + #[doc = "INT"] + #[inline(always)] + pub fn int(self) -> &'a mut crate::W { + self.variant(OvdtRes2::Int) + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn q1_x(self) -> &'a mut crate::W { + self.variant(OvdtRes2::Q1X) + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn float(self) -> &'a mut crate::W { + self.variant(OvdtRes2::Float) + } +} +#[doc = "Override RES3 Data Type Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OvdtEnRes3 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OvdtEnRes3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVDT_EN_RES3` reader - Override RES3 Data Type Enable"] +pub type OvdtEnRes3R = crate::BitReader; +impl OvdtEnRes3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtEnRes3 { + match self.bits { + false => OvdtEnRes3::Disable, + true => OvdtEnRes3::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OvdtEnRes3::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OvdtEnRes3::Enable + } +} +#[doc = "Field `OVDT_EN_RES3` writer - Override RES3 Data Type Enable"] +pub type OvdtEnRes3W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes3>; +impl<'a, REG> OvdtEnRes3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes3::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OvdtEnRes3::Enable) + } +} +#[doc = "Override RES3 Data Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OvdtRes3 { + #[doc = "0: UINT"] + Uint = 0, + #[doc = "1: INT"] + Int = 1, + #[doc = "2: Q1.X"] + Q1X = 2, + #[doc = "3: FLOAT"] + Float = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OvdtRes3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OvdtRes3 { + type Ux = u8; +} +impl crate::IsEnum for OvdtRes3 {} +#[doc = "Field `OVDT_RES3` reader - Override RES3 Data Type"] +pub type OvdtRes3R = crate::FieldReader; +impl OvdtRes3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvdtRes3 { + match self.bits { + 0 => OvdtRes3::Uint, + 1 => OvdtRes3::Int, + 2 => OvdtRes3::Q1X, + 3 => OvdtRes3::Float, + _ => unreachable!(), + } + } + #[doc = "UINT"] + #[inline(always)] + pub fn is_uint(&self) -> bool { + *self == OvdtRes3::Uint + } + #[doc = "INT"] + #[inline(always)] + pub fn is_int(&self) -> bool { + *self == OvdtRes3::Int + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn is_q1_x(&self) -> bool { + *self == OvdtRes3::Q1X + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn is_float(&self) -> bool { + *self == OvdtRes3::Float + } +} +#[doc = "Field `OVDT_RES3` writer - Override RES3 Data Type"] +pub type OvdtRes3W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes3, crate::Safe>; +impl<'a, REG> OvdtRes3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "UINT"] + #[inline(always)] + pub fn uint(self) -> &'a mut crate::W { + self.variant(OvdtRes3::Uint) + } + #[doc = "INT"] + #[inline(always)] + pub fn int(self) -> &'a mut crate::W { + self.variant(OvdtRes3::Int) + } + #[doc = "Q1.X"] + #[inline(always)] + pub fn q1_x(self) -> &'a mut crate::W { + self.variant(OvdtRes3::Q1X) + } + #[doc = "FLOAT"] + #[inline(always)] + pub fn float(self) -> &'a mut crate::W { + self.variant(OvdtRes3::Float) + } +} +impl R { + #[doc = "Bit 0 - Override RES0 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res0(&self) -> OvdtEnRes0R { + OvdtEnRes0R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Override RES0 Data Type"] + #[inline(always)] + pub fn ovdt_res0(&self) -> OvdtRes0R { + OvdtRes0R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 8 - Override RES1 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res1(&self) -> OvdtEnRes1R { + OvdtEnRes1R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:10 - Override RES1 Data Type"] + #[inline(always)] + pub fn ovdt_res1(&self) -> OvdtRes1R { + OvdtRes1R::new(((self.bits >> 9) & 3) as u8) + } + #[doc = "Bit 16 - Override RES2 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res2(&self) -> OvdtEnRes2R { + OvdtEnRes2R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:18 - Override RES2 Data Type"] + #[inline(always)] + pub fn ovdt_res2(&self) -> OvdtRes2R { + OvdtRes2R::new(((self.bits >> 17) & 3) as u8) + } + #[doc = "Bit 24 - Override RES3 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res3(&self) -> OvdtEnRes3R { + OvdtEnRes3R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:26 - Override RES3 Data Type"] + #[inline(always)] + pub fn ovdt_res3(&self) -> OvdtRes3R { + OvdtRes3R::new(((self.bits >> 25) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Override RES0 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res0(&mut self) -> OvdtEnRes0W { + OvdtEnRes0W::new(self, 0) + } + #[doc = "Bits 1:2 - Override RES0 Data Type"] + #[inline(always)] + pub fn ovdt_res0(&mut self) -> OvdtRes0W { + OvdtRes0W::new(self, 1) + } + #[doc = "Bit 8 - Override RES1 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res1(&mut self) -> OvdtEnRes1W { + OvdtEnRes1W::new(self, 8) + } + #[doc = "Bits 9:10 - Override RES1 Data Type"] + #[inline(always)] + pub fn ovdt_res1(&mut self) -> OvdtRes1W { + OvdtRes1W::new(self, 9) + } + #[doc = "Bit 16 - Override RES2 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res2(&mut self) -> OvdtEnRes2W { + OvdtEnRes2W::new(self, 16) + } + #[doc = "Bits 17:18 - Override RES2 Data Type"] + #[inline(always)] + pub fn ovdt_res2(&mut self) -> OvdtRes2W { + OvdtRes2W::new(self, 17) + } + #[doc = "Bit 24 - Override RES3 Data Type Enable"] + #[inline(always)] + pub fn ovdt_en_res3(&mut self) -> OvdtEnRes3W { + OvdtEnRes3W::new(self, 24) + } + #[doc = "Bits 25:26 - Override RES3 Data Type"] + #[inline(always)] + pub fn ovdt_res3(&mut self) -> OvdtRes3W { + OvdtRes3W::new(self, 25) + } +} +#[doc = "Operation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`op_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OpCtrlSpec; +impl crate::RegisterSpec for OpCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`op_ctrl::R`](R) reader structure"] +impl crate::Readable for OpCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`op_ctrl::W`](W) writer structure"] +impl crate::Writable for OpCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets OP_CTRL to value 0"] +impl crate::Resettable for OpCtrlSpec {} diff --git a/mcxa276-pac/src/mau0/res0.rs b/mcxa276-pac/src/mau0/res0.rs new file mode 100644 index 000000000..618913b87 --- /dev/null +++ b/mcxa276-pac/src/mau0/res0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RES0` reader"] +pub type R = crate::R; +#[doc = "Register `RES0` writer"] +pub type W = crate::W; +#[doc = "Field `MAU_RES0` reader - MAUWRAP Result Register 0"] +pub type MauRes0R = crate::FieldReader; +#[doc = "Field `MAU_RES0` writer - MAUWRAP Result Register 0"] +pub type MauRes0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - MAUWRAP Result Register 0"] + #[inline(always)] + pub fn mau_res0(&self) -> MauRes0R { + MauRes0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - MAUWRAP Result Register 0"] + #[inline(always)] + pub fn mau_res0(&mut self) -> MauRes0W { + MauRes0W::new(self, 0) + } +} +#[doc = "Result Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`res0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Res0Spec; +impl crate::RegisterSpec for Res0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`res0::R`](R) reader structure"] +impl crate::Readable for Res0Spec {} +#[doc = "`write(|w| ..)` method takes [`res0::W`](W) writer structure"] +impl crate::Writable for Res0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RES0 to value 0"] +impl crate::Resettable for Res0Spec {} diff --git a/mcxa276-pac/src/mau0/res1.rs b/mcxa276-pac/src/mau0/res1.rs new file mode 100644 index 000000000..9a240ef00 --- /dev/null +++ b/mcxa276-pac/src/mau0/res1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RES1` reader"] +pub type R = crate::R; +#[doc = "Register `RES1` writer"] +pub type W = crate::W; +#[doc = "Field `MAU_RES1` reader - MAUWRAP Result Register 1"] +pub type MauRes1R = crate::FieldReader; +#[doc = "Field `MAU_RES1` writer - MAUWRAP Result Register 1"] +pub type MauRes1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - MAUWRAP Result Register 1"] + #[inline(always)] + pub fn mau_res1(&self) -> MauRes1R { + MauRes1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - MAUWRAP Result Register 1"] + #[inline(always)] + pub fn mau_res1(&mut self) -> MauRes1W { + MauRes1W::new(self, 0) + } +} +#[doc = "Result Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`res1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Res1Spec; +impl crate::RegisterSpec for Res1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`res1::R`](R) reader structure"] +impl crate::Readable for Res1Spec {} +#[doc = "`write(|w| ..)` method takes [`res1::W`](W) writer structure"] +impl crate::Writable for Res1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RES1 to value 0"] +impl crate::Resettable for Res1Spec {} diff --git a/mcxa276-pac/src/mau0/res2.rs b/mcxa276-pac/src/mau0/res2.rs new file mode 100644 index 000000000..e7cea2e3c --- /dev/null +++ b/mcxa276-pac/src/mau0/res2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RES2` reader"] +pub type R = crate::R; +#[doc = "Register `RES2` writer"] +pub type W = crate::W; +#[doc = "Field `MAU_RES2` reader - MAUWRAP Result Register 2"] +pub type MauRes2R = crate::FieldReader; +#[doc = "Field `MAU_RES2` writer - MAUWRAP Result Register 2"] +pub type MauRes2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - MAUWRAP Result Register 2"] + #[inline(always)] + pub fn mau_res2(&self) -> MauRes2R { + MauRes2R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - MAUWRAP Result Register 2"] + #[inline(always)] + pub fn mau_res2(&mut self) -> MauRes2W { + MauRes2W::new(self, 0) + } +} +#[doc = "Result Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`res2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Res2Spec; +impl crate::RegisterSpec for Res2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`res2::R`](R) reader structure"] +impl crate::Readable for Res2Spec {} +#[doc = "`write(|w| ..)` method takes [`res2::W`](W) writer structure"] +impl crate::Writable for Res2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RES2 to value 0"] +impl crate::Resettable for Res2Spec {} diff --git a/mcxa276-pac/src/mau0/res3.rs b/mcxa276-pac/src/mau0/res3.rs new file mode 100644 index 000000000..900a97403 --- /dev/null +++ b/mcxa276-pac/src/mau0/res3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RES3` reader"] +pub type R = crate::R; +#[doc = "Register `RES3` writer"] +pub type W = crate::W; +#[doc = "Field `MAU_RES3` reader - MAUWRAP Result Register 3"] +pub type MauRes3R = crate::FieldReader; +#[doc = "Field `MAU_RES3` writer - MAUWRAP Result Register 3"] +pub type MauRes3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - MAUWRAP Result Register 3"] + #[inline(always)] + pub fn mau_res3(&self) -> MauRes3R { + MauRes3R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - MAUWRAP Result Register 3"] + #[inline(always)] + pub fn mau_res3(&mut self) -> MauRes3W { + MauRes3W::new(self, 0) + } +} +#[doc = "Result Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`res3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Res3Spec; +impl crate::RegisterSpec for Res3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`res3::R`](R) reader structure"] +impl crate::Readable for Res3Spec {} +#[doc = "`write(|w| ..)` method takes [`res3::W`](W) writer structure"] +impl crate::Writable for Res3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RES3 to value 0"] +impl crate::Resettable for Res3Spec {} diff --git a/mcxa276-pac/src/mau0/res_status.rs b/mcxa276-pac/src/mau0/res_status.rs new file mode 100644 index 000000000..29a47790c --- /dev/null +++ b/mcxa276-pac/src/mau0/res_status.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `RES_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `RES_STATUS` writer"] +pub type W = crate::W; +#[doc = "RES0 IEEE Inexact Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Nx { + #[doc = "0: The result is not rounded."] + Res0NxNo = 0, + #[doc = "1: The result is rounded, and as a result some digits lost."] + Res0NxYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Nx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_NX` reader - RES0 IEEE Inexact Flag"] +pub type Res0NxR = crate::BitReader; +impl Res0NxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Nx { + match self.bits { + false => Res0Nx::Res0NxNo, + true => Res0Nx::Res0NxYes, + } + } + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn is_res0_nx_no(&self) -> bool { + *self == Res0Nx::Res0NxNo + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn is_res0_nx_yes(&self) -> bool { + *self == Res0Nx::Res0NxYes + } +} +#[doc = "Field `RES0_NX` writer - RES0 IEEE Inexact Flag"] +pub type Res0NxW<'a, REG> = crate::BitWriter<'a, REG, Res0Nx>; +impl<'a, REG> Res0NxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn res0_nx_no(self) -> &'a mut crate::W { + self.variant(Res0Nx::Res0NxNo) + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn res0_nx_yes(self) -> &'a mut crate::W { + self.variant(Res0Nx::Res0NxYes) + } +} +#[doc = "RES0 IEEE Underflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Uf { + #[doc = "0: No tiny non-zero result is detected."] + Res0UfNo = 0, + #[doc = "1: A tiny non-zero result is detected."] + Res0UfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Uf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_UF` reader - RES0 IEEE Underflow Flag"] +pub type Res0UfR = crate::BitReader; +impl Res0UfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Uf { + match self.bits { + false => Res0Uf::Res0UfNo, + true => Res0Uf::Res0UfYes, + } + } + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res0_uf_no(&self) -> bool { + *self == Res0Uf::Res0UfNo + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res0_uf_yes(&self) -> bool { + *self == Res0Uf::Res0UfYes + } +} +#[doc = "Field `RES0_UF` writer - RES0 IEEE Underflow Flag"] +pub type Res0UfW<'a, REG> = crate::BitWriter<'a, REG, Res0Uf>; +impl<'a, REG> Res0UfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn res0_uf_no(self) -> &'a mut crate::W { + self.variant(Res0Uf::Res0UfNo) + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn res0_uf_yes(self) -> &'a mut crate::W { + self.variant(Res0Uf::Res0UfYes) + } +} +#[doc = "RES0 IEEE Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Of { + #[doc = "0: The result format's largest finite number is not exceeded."] + Res0OfNo = 0, + #[doc = "1: The result format's largest finite number is exceeded."] + Res0OfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Of) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_OF` reader - RES0 IEEE Overflow Flag"] +pub type Res0OfR = crate::BitReader; +impl Res0OfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Of { + match self.bits { + false => Res0Of::Res0OfNo, + true => Res0Of::Res0OfYes, + } + } + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn is_res0_of_no(&self) -> bool { + *self == Res0Of::Res0OfNo + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn is_res0_of_yes(&self) -> bool { + *self == Res0Of::Res0OfYes + } +} +#[doc = "Field `RES0_OF` writer - RES0 IEEE Overflow Flag"] +pub type Res0OfW<'a, REG> = crate::BitWriter<'a, REG, Res0Of>; +impl<'a, REG> Res0OfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn res0_of_no(self) -> &'a mut crate::W { + self.variant(Res0Of::Res0OfNo) + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn res0_of_yes(self) -> &'a mut crate::W { + self.variant(Res0Of::Res0OfYes) + } +} +#[doc = "RES0 IEEE Divide by Zero Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Dz { + #[doc = "0: No exact infinite result is defined for an operation on finite operands."] + Res0DzNo = 0, + #[doc = "1: An exact infinite result is defined for an operation on finite operands."] + Res0DzYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Dz) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_DZ` reader - RES0 IEEE Divide by Zero Flag"] +pub type Res0DzR = crate::BitReader; +impl Res0DzR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Dz { + match self.bits { + false => Res0Dz::Res0DzNo, + true => Res0Dz::Res0DzYes, + } + } + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res0_dz_no(&self) -> bool { + *self == Res0Dz::Res0DzNo + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res0_dz_yes(&self) -> bool { + *self == Res0Dz::Res0DzYes + } +} +#[doc = "Field `RES0_DZ` writer - RES0 IEEE Divide by Zero Flag"] +pub type Res0DzW<'a, REG> = crate::BitWriter<'a, REG, Res0Dz>; +impl<'a, REG> Res0DzW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res0_dz_no(self) -> &'a mut crate::W { + self.variant(Res0Dz::Res0DzNo) + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res0_dz_yes(self) -> &'a mut crate::W { + self.variant(Res0Dz::Res0DzYes) + } +} +#[doc = "RES0 IEEE Invalid Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Nv { + #[doc = "0: There is usefully definable result."] + Res0NvNo = 0, + #[doc = "1: There is no usefully definable result."] + Res0NvYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Nv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_NV` reader - RES0 IEEE Invalid Flag"] +pub type Res0NvR = crate::BitReader; +impl Res0NvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Nv { + match self.bits { + false => Res0Nv::Res0NvNo, + true => Res0Nv::Res0NvYes, + } + } + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn is_res0_nv_no(&self) -> bool { + *self == Res0Nv::Res0NvNo + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn is_res0_nv_yes(&self) -> bool { + *self == Res0Nv::Res0NvYes + } +} +#[doc = "Field `RES0_NV` writer - RES0 IEEE Invalid Flag"] +pub type Res0NvW<'a, REG> = crate::BitWriter<'a, REG, Res0Nv>; +impl<'a, REG> Res0NvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn res0_nv_no(self) -> &'a mut crate::W { + self.variant(Res0Nv::Res0NvNo) + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn res0_nv_yes(self) -> &'a mut crate::W { + self.variant(Res0Nv::Res0NvYes) + } +} +#[doc = "RES0 Indirect Operation Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Err { + #[doc = "0: No invalid indirect operation is detected."] + Res0ErrNo = 0, + #[doc = "1: An invalid indirect operation error is detected."] + Res0ErrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_ERR` reader - RES0 Indirect Operation Error Flag"] +pub type Res0ErrR = crate::BitReader; +impl Res0ErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Err { + match self.bits { + false => Res0Err::Res0ErrNo, + true => Res0Err::Res0ErrYes, + } + } + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn is_res0_err_no(&self) -> bool { + *self == Res0Err::Res0ErrNo + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn is_res0_err_yes(&self) -> bool { + *self == Res0Err::Res0ErrYes + } +} +#[doc = "Field `RES0_ERR` writer - RES0 Indirect Operation Error Flag"] +pub type Res0ErrW<'a, REG> = crate::BitWriter<'a, REG, Res0Err>; +impl<'a, REG> Res0ErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn res0_err_no(self) -> &'a mut crate::W { + self.variant(Res0Err::Res0ErrNo) + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn res0_err_yes(self) -> &'a mut crate::W { + self.variant(Res0Err::Res0ErrYes) + } +} +#[doc = "RES0 Overwrite Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Ovwr { + #[doc = "0: The value of RES0 has been read."] + Res0OvwrNo = 0, + #[doc = "1: The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result."] + Res0OvwrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Ovwr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_OVWR` reader - RES0 Overwrite Flag"] +pub type Res0OvwrR = crate::BitReader; +impl Res0OvwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Ovwr { + match self.bits { + false => Res0Ovwr::Res0OvwrNo, + true => Res0Ovwr::Res0OvwrYes, + } + } + #[doc = "The value of RES0 has been read."] + #[inline(always)] + pub fn is_res0_ovwr_no(&self) -> bool { + *self == Res0Ovwr::Res0OvwrNo + } + #[doc = "The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn is_res0_ovwr_yes(&self) -> bool { + *self == Res0Ovwr::Res0OvwrYes + } +} +#[doc = "Field `RES0_OVWR` writer - RES0 Overwrite Flag"] +pub type Res0OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res0Ovwr>; +impl<'a, REG> Res0OvwrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The value of RES0 has been read."] + #[inline(always)] + pub fn res0_ovwr_no(self) -> &'a mut crate::W { + self.variant(Res0Ovwr::Res0OvwrNo) + } + #[doc = "The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn res0_ovwr_yes(self) -> &'a mut crate::W { + self.variant(Res0Ovwr::Res0OvwrYes) + } +} +#[doc = "RES0 Full Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Full { + #[doc = "0: RES0 has not updated and cannot be read."] + Res0FullNo = 0, + #[doc = "1: RES0 has updated and can be read."] + Res0FullYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_FULL` reader - RES0 Full Flag"] +pub type Res0FullR = crate::BitReader; +impl Res0FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Full { + match self.bits { + false => Res0Full::Res0FullNo, + true => Res0Full::Res0FullYes, + } + } + #[doc = "RES0 has not updated and cannot be read."] + #[inline(always)] + pub fn is_res0_full_no(&self) -> bool { + *self == Res0Full::Res0FullNo + } + #[doc = "RES0 has updated and can be read."] + #[inline(always)] + pub fn is_res0_full_yes(&self) -> bool { + *self == Res0Full::Res0FullYes + } +} +#[doc = "Field `RES0_FULL` writer - RES0 Full Flag"] +pub type Res0FullW<'a, REG> = crate::BitWriter<'a, REG, Res0Full>; +impl<'a, REG> Res0FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RES0 has not updated and cannot be read."] + #[inline(always)] + pub fn res0_full_no(self) -> &'a mut crate::W { + self.variant(Res0Full::Res0FullNo) + } + #[doc = "RES0 has updated and can be read."] + #[inline(always)] + pub fn res0_full_yes(self) -> &'a mut crate::W { + self.variant(Res0Full::Res0FullYes) + } +} +#[doc = "RES1 IEEE Inexact Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Nx { + #[doc = "0: The result is not rounded."] + Res1NxNo = 0, + #[doc = "1: The result is rounded, and as a result some digits lost."] + Res1NxYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Nx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_NX` reader - RES1 IEEE Inexact Flag"] +pub type Res1NxR = crate::BitReader; +impl Res1NxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Nx { + match self.bits { + false => Res1Nx::Res1NxNo, + true => Res1Nx::Res1NxYes, + } + } + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn is_res1_nx_no(&self) -> bool { + *self == Res1Nx::Res1NxNo + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn is_res1_nx_yes(&self) -> bool { + *self == Res1Nx::Res1NxYes + } +} +#[doc = "Field `RES1_NX` writer - RES1 IEEE Inexact Flag"] +pub type Res1NxW<'a, REG> = crate::BitWriter<'a, REG, Res1Nx>; +impl<'a, REG> Res1NxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn res1_nx_no(self) -> &'a mut crate::W { + self.variant(Res1Nx::Res1NxNo) + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn res1_nx_yes(self) -> &'a mut crate::W { + self.variant(Res1Nx::Res1NxYes) + } +} +#[doc = "RES1 IEEE Underflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Uf { + #[doc = "0: No tiny non-zero result is detected."] + Res1UfNo = 0, + #[doc = "1: A tiny non-zero result is detected."] + Res1UfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Uf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_UF` reader - RES1 IEEE Underflow Flag"] +pub type Res1UfR = crate::BitReader; +impl Res1UfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Uf { + match self.bits { + false => Res1Uf::Res1UfNo, + true => Res1Uf::Res1UfYes, + } + } + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res1_uf_no(&self) -> bool { + *self == Res1Uf::Res1UfNo + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res1_uf_yes(&self) -> bool { + *self == Res1Uf::Res1UfYes + } +} +#[doc = "Field `RES1_UF` writer - RES1 IEEE Underflow Flag"] +pub type Res1UfW<'a, REG> = crate::BitWriter<'a, REG, Res1Uf>; +impl<'a, REG> Res1UfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn res1_uf_no(self) -> &'a mut crate::W { + self.variant(Res1Uf::Res1UfNo) + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn res1_uf_yes(self) -> &'a mut crate::W { + self.variant(Res1Uf::Res1UfYes) + } +} +#[doc = "RES1 IEEE Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Of { + #[doc = "0: The result format's largest finite number is not exceeded."] + Res1OfNo = 0, + #[doc = "1: The result format's largest finite number is exceeded."] + Res1OfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Of) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_OF` reader - RES1 IEEE Overflow Flag"] +pub type Res1OfR = crate::BitReader; +impl Res1OfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Of { + match self.bits { + false => Res1Of::Res1OfNo, + true => Res1Of::Res1OfYes, + } + } + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn is_res1_of_no(&self) -> bool { + *self == Res1Of::Res1OfNo + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn is_res1_of_yes(&self) -> bool { + *self == Res1Of::Res1OfYes + } +} +#[doc = "Field `RES1_OF` writer - RES1 IEEE Overflow Flag"] +pub type Res1OfW<'a, REG> = crate::BitWriter<'a, REG, Res1Of>; +impl<'a, REG> Res1OfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn res1_of_no(self) -> &'a mut crate::W { + self.variant(Res1Of::Res1OfNo) + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn res1_of_yes(self) -> &'a mut crate::W { + self.variant(Res1Of::Res1OfYes) + } +} +#[doc = "RES1 IEEE Divide by Zero Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Dz { + #[doc = "0: No exact infinite result is defined for an operation on finite operands."] + Res1DzNo = 0, + #[doc = "1: An exact infinite result is defined for an operation on finite operands."] + Res1DzYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Dz) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_DZ` reader - RES1 IEEE Divide by Zero Flag"] +pub type Res1DzR = crate::BitReader; +impl Res1DzR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Dz { + match self.bits { + false => Res1Dz::Res1DzNo, + true => Res1Dz::Res1DzYes, + } + } + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res1_dz_no(&self) -> bool { + *self == Res1Dz::Res1DzNo + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res1_dz_yes(&self) -> bool { + *self == Res1Dz::Res1DzYes + } +} +#[doc = "Field `RES1_DZ` writer - RES1 IEEE Divide by Zero Flag"] +pub type Res1DzW<'a, REG> = crate::BitWriter<'a, REG, Res1Dz>; +impl<'a, REG> Res1DzW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res1_dz_no(self) -> &'a mut crate::W { + self.variant(Res1Dz::Res1DzNo) + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res1_dz_yes(self) -> &'a mut crate::W { + self.variant(Res1Dz::Res1DzYes) + } +} +#[doc = "RES1 IEEE Invalid Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Nv { + #[doc = "0: There is usefully definable result."] + Res1NvNo = 0, + #[doc = "1: There is no usefully definable result."] + Res1NvYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Nv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_NV` reader - RES1 IEEE Invalid Flag"] +pub type Res1NvR = crate::BitReader; +impl Res1NvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Nv { + match self.bits { + false => Res1Nv::Res1NvNo, + true => Res1Nv::Res1NvYes, + } + } + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn is_res1_nv_no(&self) -> bool { + *self == Res1Nv::Res1NvNo + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn is_res1_nv_yes(&self) -> bool { + *self == Res1Nv::Res1NvYes + } +} +#[doc = "Field `RES1_NV` writer - RES1 IEEE Invalid Flag"] +pub type Res1NvW<'a, REG> = crate::BitWriter<'a, REG, Res1Nv>; +impl<'a, REG> Res1NvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn res1_nv_no(self) -> &'a mut crate::W { + self.variant(Res1Nv::Res1NvNo) + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn res1_nv_yes(self) -> &'a mut crate::W { + self.variant(Res1Nv::Res1NvYes) + } +} +#[doc = "RES1 Indirect Operation Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Err { + #[doc = "0: No invalid indirect operation is detected."] + Res1ErrNo = 0, + #[doc = "1: An invalid indirect operation error is detected."] + Res1ErrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_ERR` reader - RES1 Indirect Operation Error Flag"] +pub type Res1ErrR = crate::BitReader; +impl Res1ErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Err { + match self.bits { + false => Res1Err::Res1ErrNo, + true => Res1Err::Res1ErrYes, + } + } + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn is_res1_err_no(&self) -> bool { + *self == Res1Err::Res1ErrNo + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn is_res1_err_yes(&self) -> bool { + *self == Res1Err::Res1ErrYes + } +} +#[doc = "Field `RES1_ERR` writer - RES1 Indirect Operation Error Flag"] +pub type Res1ErrW<'a, REG> = crate::BitWriter<'a, REG, Res1Err>; +impl<'a, REG> Res1ErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn res1_err_no(self) -> &'a mut crate::W { + self.variant(Res1Err::Res1ErrNo) + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn res1_err_yes(self) -> &'a mut crate::W { + self.variant(Res1Err::Res1ErrYes) + } +} +#[doc = "RES1 Overwrite Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Ovwr { + #[doc = "0: The value of RES1 has been read."] + Res1OvwrNo = 0, + #[doc = "1: The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result."] + Res1OvwrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Ovwr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_OVWR` reader - RES1 Overwrite Flag"] +pub type Res1OvwrR = crate::BitReader; +impl Res1OvwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Ovwr { + match self.bits { + false => Res1Ovwr::Res1OvwrNo, + true => Res1Ovwr::Res1OvwrYes, + } + } + #[doc = "The value of RES1 has been read."] + #[inline(always)] + pub fn is_res1_ovwr_no(&self) -> bool { + *self == Res1Ovwr::Res1OvwrNo + } + #[doc = "The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn is_res1_ovwr_yes(&self) -> bool { + *self == Res1Ovwr::Res1OvwrYes + } +} +#[doc = "Field `RES1_OVWR` writer - RES1 Overwrite Flag"] +pub type Res1OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res1Ovwr>; +impl<'a, REG> Res1OvwrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The value of RES1 has been read."] + #[inline(always)] + pub fn res1_ovwr_no(self) -> &'a mut crate::W { + self.variant(Res1Ovwr::Res1OvwrNo) + } + #[doc = "The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn res1_ovwr_yes(self) -> &'a mut crate::W { + self.variant(Res1Ovwr::Res1OvwrYes) + } +} +#[doc = "RES1 Full Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Full { + #[doc = "0: RES1 has not updated and cannot be read."] + Res1FullNo = 0, + #[doc = "1: RES1 has updated and can be read."] + Res1FullYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_FULL` reader - RES1 Full Flag"] +pub type Res1FullR = crate::BitReader; +impl Res1FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Full { + match self.bits { + false => Res1Full::Res1FullNo, + true => Res1Full::Res1FullYes, + } + } + #[doc = "RES1 has not updated and cannot be read."] + #[inline(always)] + pub fn is_res1_full_no(&self) -> bool { + *self == Res1Full::Res1FullNo + } + #[doc = "RES1 has updated and can be read."] + #[inline(always)] + pub fn is_res1_full_yes(&self) -> bool { + *self == Res1Full::Res1FullYes + } +} +#[doc = "Field `RES1_FULL` writer - RES1 Full Flag"] +pub type Res1FullW<'a, REG> = crate::BitWriter<'a, REG, Res1Full>; +impl<'a, REG> Res1FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RES1 has not updated and cannot be read."] + #[inline(always)] + pub fn res1_full_no(self) -> &'a mut crate::W { + self.variant(Res1Full::Res1FullNo) + } + #[doc = "RES1 has updated and can be read."] + #[inline(always)] + pub fn res1_full_yes(self) -> &'a mut crate::W { + self.variant(Res1Full::Res1FullYes) + } +} +#[doc = "RES2 IEEE Inexact Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Nx { + #[doc = "0: The result is not rounded."] + Res2NxNo = 0, + #[doc = "1: The result is rounded, and as a result some digits lost."] + Res2NxYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Nx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_NX` reader - RES2 IEEE Inexact Flag"] +pub type Res2NxR = crate::BitReader; +impl Res2NxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Nx { + match self.bits { + false => Res2Nx::Res2NxNo, + true => Res2Nx::Res2NxYes, + } + } + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn is_res2_nx_no(&self) -> bool { + *self == Res2Nx::Res2NxNo + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn is_res2_nx_yes(&self) -> bool { + *self == Res2Nx::Res2NxYes + } +} +#[doc = "Field `RES2_NX` writer - RES2 IEEE Inexact Flag"] +pub type Res2NxW<'a, REG> = crate::BitWriter<'a, REG, Res2Nx>; +impl<'a, REG> Res2NxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn res2_nx_no(self) -> &'a mut crate::W { + self.variant(Res2Nx::Res2NxNo) + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn res2_nx_yes(self) -> &'a mut crate::W { + self.variant(Res2Nx::Res2NxYes) + } +} +#[doc = "RES2 IEEE Underflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Uf { + #[doc = "0: No tiny non-zero result is detected."] + Res2UfNo = 0, + #[doc = "1: A tiny non-zero result is detected."] + Res2UfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Uf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_UF` reader - RES2 IEEE Underflow Flag"] +pub type Res2UfR = crate::BitReader; +impl Res2UfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Uf { + match self.bits { + false => Res2Uf::Res2UfNo, + true => Res2Uf::Res2UfYes, + } + } + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res2_uf_no(&self) -> bool { + *self == Res2Uf::Res2UfNo + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res2_uf_yes(&self) -> bool { + *self == Res2Uf::Res2UfYes + } +} +#[doc = "Field `RES2_UF` writer - RES2 IEEE Underflow Flag"] +pub type Res2UfW<'a, REG> = crate::BitWriter<'a, REG, Res2Uf>; +impl<'a, REG> Res2UfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn res2_uf_no(self) -> &'a mut crate::W { + self.variant(Res2Uf::Res2UfNo) + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn res2_uf_yes(self) -> &'a mut crate::W { + self.variant(Res2Uf::Res2UfYes) + } +} +#[doc = "RES2 IEEE Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Of { + #[doc = "0: The result format's largest finite number is not exceeded."] + Res2OfNo = 0, + #[doc = "1: The result format's largest finite number is exceeded."] + Res2OfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Of) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_OF` reader - RES2 IEEE Overflow Flag"] +pub type Res2OfR = crate::BitReader; +impl Res2OfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Of { + match self.bits { + false => Res2Of::Res2OfNo, + true => Res2Of::Res2OfYes, + } + } + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn is_res2_of_no(&self) -> bool { + *self == Res2Of::Res2OfNo + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn is_res2_of_yes(&self) -> bool { + *self == Res2Of::Res2OfYes + } +} +#[doc = "Field `RES2_OF` writer - RES2 IEEE Overflow Flag"] +pub type Res2OfW<'a, REG> = crate::BitWriter<'a, REG, Res2Of>; +impl<'a, REG> Res2OfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn res2_of_no(self) -> &'a mut crate::W { + self.variant(Res2Of::Res2OfNo) + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn res2_of_yes(self) -> &'a mut crate::W { + self.variant(Res2Of::Res2OfYes) + } +} +#[doc = "RES2 IEEE Divide by Zero Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Dz { + #[doc = "0: No exact infinite result is defined for an operation on finite operands."] + Res2DzNo = 0, + #[doc = "1: An exact infinite result is defined for an operation on finite operands."] + Res2DzYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Dz) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_DZ` reader - RES2 IEEE Divide by Zero Flag"] +pub type Res2DzR = crate::BitReader; +impl Res2DzR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Dz { + match self.bits { + false => Res2Dz::Res2DzNo, + true => Res2Dz::Res2DzYes, + } + } + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res2_dz_no(&self) -> bool { + *self == Res2Dz::Res2DzNo + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res2_dz_yes(&self) -> bool { + *self == Res2Dz::Res2DzYes + } +} +#[doc = "Field `RES2_DZ` writer - RES2 IEEE Divide by Zero Flag"] +pub type Res2DzW<'a, REG> = crate::BitWriter<'a, REG, Res2Dz>; +impl<'a, REG> Res2DzW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res2_dz_no(self) -> &'a mut crate::W { + self.variant(Res2Dz::Res2DzNo) + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res2_dz_yes(self) -> &'a mut crate::W { + self.variant(Res2Dz::Res2DzYes) + } +} +#[doc = "RES2 IEEE Invalid Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Nv { + #[doc = "0: There is usefully definable result."] + Res2NvNo = 0, + #[doc = "1: There is no usefully definable result."] + Res2NvYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Nv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_NV` reader - RES2 IEEE Invalid Flag"] +pub type Res2NvR = crate::BitReader; +impl Res2NvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Nv { + match self.bits { + false => Res2Nv::Res2NvNo, + true => Res2Nv::Res2NvYes, + } + } + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn is_res2_nv_no(&self) -> bool { + *self == Res2Nv::Res2NvNo + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn is_res2_nv_yes(&self) -> bool { + *self == Res2Nv::Res2NvYes + } +} +#[doc = "Field `RES2_NV` writer - RES2 IEEE Invalid Flag"] +pub type Res2NvW<'a, REG> = crate::BitWriter<'a, REG, Res2Nv>; +impl<'a, REG> Res2NvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn res2_nv_no(self) -> &'a mut crate::W { + self.variant(Res2Nv::Res2NvNo) + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn res2_nv_yes(self) -> &'a mut crate::W { + self.variant(Res2Nv::Res2NvYes) + } +} +#[doc = "RES2 Indirect Operation Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Err { + #[doc = "0: No invalid indirect operation is detected."] + Res2ErrNo = 0, + #[doc = "1: An invalid indirect operation error is detected."] + Res2ErrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_ERR` reader - RES2 Indirect Operation Error Flag"] +pub type Res2ErrR = crate::BitReader; +impl Res2ErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Err { + match self.bits { + false => Res2Err::Res2ErrNo, + true => Res2Err::Res2ErrYes, + } + } + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn is_res2_err_no(&self) -> bool { + *self == Res2Err::Res2ErrNo + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn is_res2_err_yes(&self) -> bool { + *self == Res2Err::Res2ErrYes + } +} +#[doc = "Field `RES2_ERR` writer - RES2 Indirect Operation Error Flag"] +pub type Res2ErrW<'a, REG> = crate::BitWriter<'a, REG, Res2Err>; +impl<'a, REG> Res2ErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn res2_err_no(self) -> &'a mut crate::W { + self.variant(Res2Err::Res2ErrNo) + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn res2_err_yes(self) -> &'a mut crate::W { + self.variant(Res2Err::Res2ErrYes) + } +} +#[doc = "RES2 Overwrite Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Ovwr { + #[doc = "0: The value of RES2 has been read."] + Res2OvwrNo = 0, + #[doc = "1: The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result."] + Res2OvwrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Ovwr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_OVWR` reader - RES2 Overwrite Flag"] +pub type Res2OvwrR = crate::BitReader; +impl Res2OvwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Ovwr { + match self.bits { + false => Res2Ovwr::Res2OvwrNo, + true => Res2Ovwr::Res2OvwrYes, + } + } + #[doc = "The value of RES2 has been read."] + #[inline(always)] + pub fn is_res2_ovwr_no(&self) -> bool { + *self == Res2Ovwr::Res2OvwrNo + } + #[doc = "The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn is_res2_ovwr_yes(&self) -> bool { + *self == Res2Ovwr::Res2OvwrYes + } +} +#[doc = "Field `RES2_OVWR` writer - RES2 Overwrite Flag"] +pub type Res2OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res2Ovwr>; +impl<'a, REG> Res2OvwrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The value of RES2 has been read."] + #[inline(always)] + pub fn res2_ovwr_no(self) -> &'a mut crate::W { + self.variant(Res2Ovwr::Res2OvwrNo) + } + #[doc = "The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn res2_ovwr_yes(self) -> &'a mut crate::W { + self.variant(Res2Ovwr::Res2OvwrYes) + } +} +#[doc = "RES2 Full Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Full { + #[doc = "0: RES2 has not updated and cannot be read."] + Res2FullNo = 0, + #[doc = "1: RES2 has updated and can be read."] + Res2FullYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_FULL` reader - RES2 Full Flag"] +pub type Res2FullR = crate::BitReader; +impl Res2FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Full { + match self.bits { + false => Res2Full::Res2FullNo, + true => Res2Full::Res2FullYes, + } + } + #[doc = "RES2 has not updated and cannot be read."] + #[inline(always)] + pub fn is_res2_full_no(&self) -> bool { + *self == Res2Full::Res2FullNo + } + #[doc = "RES2 has updated and can be read."] + #[inline(always)] + pub fn is_res2_full_yes(&self) -> bool { + *self == Res2Full::Res2FullYes + } +} +#[doc = "Field `RES2_FULL` writer - RES2 Full Flag"] +pub type Res2FullW<'a, REG> = crate::BitWriter<'a, REG, Res2Full>; +impl<'a, REG> Res2FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RES2 has not updated and cannot be read."] + #[inline(always)] + pub fn res2_full_no(self) -> &'a mut crate::W { + self.variant(Res2Full::Res2FullNo) + } + #[doc = "RES2 has updated and can be read."] + #[inline(always)] + pub fn res2_full_yes(self) -> &'a mut crate::W { + self.variant(Res2Full::Res2FullYes) + } +} +#[doc = "RES3 IEEE Inexact Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Nx { + #[doc = "0: The result is not rounded."] + Res3NxNo = 0, + #[doc = "1: The result is rounded, and as a result some digits lost."] + Res3NxYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Nx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_NX` reader - RES3 IEEE Inexact Flag"] +pub type Res3NxR = crate::BitReader; +impl Res3NxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Nx { + match self.bits { + false => Res3Nx::Res3NxNo, + true => Res3Nx::Res3NxYes, + } + } + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn is_res3_nx_no(&self) -> bool { + *self == Res3Nx::Res3NxNo + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn is_res3_nx_yes(&self) -> bool { + *self == Res3Nx::Res3NxYes + } +} +#[doc = "Field `RES3_NX` writer - RES3 IEEE Inexact Flag"] +pub type Res3NxW<'a, REG> = crate::BitWriter<'a, REG, Res3Nx>; +impl<'a, REG> Res3NxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result is not rounded."] + #[inline(always)] + pub fn res3_nx_no(self) -> &'a mut crate::W { + self.variant(Res3Nx::Res3NxNo) + } + #[doc = "The result is rounded, and as a result some digits lost."] + #[inline(always)] + pub fn res3_nx_yes(self) -> &'a mut crate::W { + self.variant(Res3Nx::Res3NxYes) + } +} +#[doc = "RES3 IEEE Underflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Uf { + #[doc = "0: No tiny non-zero result is detected."] + Res3UfNo = 0, + #[doc = "1: A tiny non-zero result is detected."] + Res3UfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Uf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_UF` reader - RES3 IEEE Underflow Flag"] +pub type Res3UfR = crate::BitReader; +impl Res3UfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Uf { + match self.bits { + false => Res3Uf::Res3UfNo, + true => Res3Uf::Res3UfYes, + } + } + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res3_uf_no(&self) -> bool { + *self == Res3Uf::Res3UfNo + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn is_res3_uf_yes(&self) -> bool { + *self == Res3Uf::Res3UfYes + } +} +#[doc = "Field `RES3_UF` writer - RES3 IEEE Underflow Flag"] +pub type Res3UfW<'a, REG> = crate::BitWriter<'a, REG, Res3Uf>; +impl<'a, REG> Res3UfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No tiny non-zero result is detected."] + #[inline(always)] + pub fn res3_uf_no(self) -> &'a mut crate::W { + self.variant(Res3Uf::Res3UfNo) + } + #[doc = "A tiny non-zero result is detected."] + #[inline(always)] + pub fn res3_uf_yes(self) -> &'a mut crate::W { + self.variant(Res3Uf::Res3UfYes) + } +} +#[doc = "RES3 IEEE Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Of { + #[doc = "0: The result format's largest finite number is not exceeded."] + Res3OfNo = 0, + #[doc = "1: The result format's largest finite number is exceeded."] + Res3OfYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Of) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_OF` reader - RES3 IEEE Overflow Flag"] +pub type Res3OfR = crate::BitReader; +impl Res3OfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Of { + match self.bits { + false => Res3Of::Res3OfNo, + true => Res3Of::Res3OfYes, + } + } + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn is_res3_of_no(&self) -> bool { + *self == Res3Of::Res3OfNo + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn is_res3_of_yes(&self) -> bool { + *self == Res3Of::Res3OfYes + } +} +#[doc = "Field `RES3_OF` writer - RES3 IEEE Overflow Flag"] +pub type Res3OfW<'a, REG> = crate::BitWriter<'a, REG, Res3Of>; +impl<'a, REG> Res3OfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The result format's largest finite number is not exceeded."] + #[inline(always)] + pub fn res3_of_no(self) -> &'a mut crate::W { + self.variant(Res3Of::Res3OfNo) + } + #[doc = "The result format's largest finite number is exceeded."] + #[inline(always)] + pub fn res3_of_yes(self) -> &'a mut crate::W { + self.variant(Res3Of::Res3OfYes) + } +} +#[doc = "RES3 IEEE Divide by Zero Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Dz { + #[doc = "0: No exact infinite result is defined for an operation on finite operands."] + Res3DzNo = 0, + #[doc = "1: An exact infinite result is defined for an operation on finite operands."] + Res3DzYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Dz) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_DZ` reader - RES3 IEEE Divide by Zero Flag"] +pub type Res3DzR = crate::BitReader; +impl Res3DzR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Dz { + match self.bits { + false => Res3Dz::Res3DzNo, + true => Res3Dz::Res3DzYes, + } + } + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res3_dz_no(&self) -> bool { + *self == Res3Dz::Res3DzNo + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn is_res3_dz_yes(&self) -> bool { + *self == Res3Dz::Res3DzYes + } +} +#[doc = "Field `RES3_DZ` writer - RES3 IEEE Divide by Zero Flag"] +pub type Res3DzW<'a, REG> = crate::BitWriter<'a, REG, Res3Dz>; +impl<'a, REG> Res3DzW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res3_dz_no(self) -> &'a mut crate::W { + self.variant(Res3Dz::Res3DzNo) + } + #[doc = "An exact infinite result is defined for an operation on finite operands."] + #[inline(always)] + pub fn res3_dz_yes(self) -> &'a mut crate::W { + self.variant(Res3Dz::Res3DzYes) + } +} +#[doc = "RES3 IEEE Invalid Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Nv { + #[doc = "0: There is usefully definable result."] + Res3NvNo = 0, + #[doc = "1: There is no usefully definable result."] + Res3NvYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Nv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_NV` reader - RES3 IEEE Invalid Flag"] +pub type Res3NvR = crate::BitReader; +impl Res3NvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Nv { + match self.bits { + false => Res3Nv::Res3NvNo, + true => Res3Nv::Res3NvYes, + } + } + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn is_res3_nv_no(&self) -> bool { + *self == Res3Nv::Res3NvNo + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn is_res3_nv_yes(&self) -> bool { + *self == Res3Nv::Res3NvYes + } +} +#[doc = "Field `RES3_NV` writer - RES3 IEEE Invalid Flag"] +pub type Res3NvW<'a, REG> = crate::BitWriter<'a, REG, Res3Nv>; +impl<'a, REG> Res3NvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "There is usefully definable result."] + #[inline(always)] + pub fn res3_nv_no(self) -> &'a mut crate::W { + self.variant(Res3Nv::Res3NvNo) + } + #[doc = "There is no usefully definable result."] + #[inline(always)] + pub fn res3_nv_yes(self) -> &'a mut crate::W { + self.variant(Res3Nv::Res3NvYes) + } +} +#[doc = "RES3 Indirect Operation Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Err { + #[doc = "0: No invalid indirect operation is detected."] + Res3ErrNo = 0, + #[doc = "1: An invalid indirect operation error is detected."] + Res3ErrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_ERR` reader - RES3 Indirect Operation Error Flag"] +pub type Res3ErrR = crate::BitReader; +impl Res3ErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Err { + match self.bits { + false => Res3Err::Res3ErrNo, + true => Res3Err::Res3ErrYes, + } + } + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn is_res3_err_no(&self) -> bool { + *self == Res3Err::Res3ErrNo + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn is_res3_err_yes(&self) -> bool { + *self == Res3Err::Res3ErrYes + } +} +#[doc = "Field `RES3_ERR` writer - RES3 Indirect Operation Error Flag"] +pub type Res3ErrW<'a, REG> = crate::BitWriter<'a, REG, Res3Err>; +impl<'a, REG> Res3ErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No invalid indirect operation is detected."] + #[inline(always)] + pub fn res3_err_no(self) -> &'a mut crate::W { + self.variant(Res3Err::Res3ErrNo) + } + #[doc = "An invalid indirect operation error is detected."] + #[inline(always)] + pub fn res3_err_yes(self) -> &'a mut crate::W { + self.variant(Res3Err::Res3ErrYes) + } +} +#[doc = "RES3 Overwrite Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Ovwr { + #[doc = "0: The value of RES3 has been read."] + Res3OvwrNo = 0, + #[doc = "1: The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result."] + Res3OvwrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Ovwr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_OVWR` reader - RES3 Overwrite Flag"] +pub type Res3OvwrR = crate::BitReader; +impl Res3OvwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Ovwr { + match self.bits { + false => Res3Ovwr::Res3OvwrNo, + true => Res3Ovwr::Res3OvwrYes, + } + } + #[doc = "The value of RES3 has been read."] + #[inline(always)] + pub fn is_res3_ovwr_no(&self) -> bool { + *self == Res3Ovwr::Res3OvwrNo + } + #[doc = "The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn is_res3_ovwr_yes(&self) -> bool { + *self == Res3Ovwr::Res3OvwrYes + } +} +#[doc = "Field `RES3_OVWR` writer - RES3 Overwrite Flag"] +pub type Res3OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res3Ovwr>; +impl<'a, REG> Res3OvwrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The value of RES3 has been read."] + #[inline(always)] + pub fn res3_ovwr_no(self) -> &'a mut crate::W { + self.variant(Res3Ovwr::Res3OvwrNo) + } + #[doc = "The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result."] + #[inline(always)] + pub fn res3_ovwr_yes(self) -> &'a mut crate::W { + self.variant(Res3Ovwr::Res3OvwrYes) + } +} +#[doc = "RES3 Full Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Full { + #[doc = "0: RES3 has not updated and cannot be read."] + Res3FullNo = 0, + #[doc = "1: RES3 has updated and can be read."] + Res3FullYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Full) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_FULL` reader - RES3 Full Flag"] +pub type Res3FullR = crate::BitReader; +impl Res3FullR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Full { + match self.bits { + false => Res3Full::Res3FullNo, + true => Res3Full::Res3FullYes, + } + } + #[doc = "RES3 has not updated and cannot be read."] + #[inline(always)] + pub fn is_res3_full_no(&self) -> bool { + *self == Res3Full::Res3FullNo + } + #[doc = "RES3 has updated and can be read."] + #[inline(always)] + pub fn is_res3_full_yes(&self) -> bool { + *self == Res3Full::Res3FullYes + } +} +#[doc = "Field `RES3_FULL` writer - RES3 Full Flag"] +pub type Res3FullW<'a, REG> = crate::BitWriter<'a, REG, Res3Full>; +impl<'a, REG> Res3FullW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RES3 has not updated and cannot be read."] + #[inline(always)] + pub fn res3_full_no(self) -> &'a mut crate::W { + self.variant(Res3Full::Res3FullNo) + } + #[doc = "RES3 has updated and can be read."] + #[inline(always)] + pub fn res3_full_yes(self) -> &'a mut crate::W { + self.variant(Res3Full::Res3FullYes) + } +} +impl R { + #[doc = "Bit 0 - RES0 IEEE Inexact Flag"] + #[inline(always)] + pub fn res0_nx(&self) -> Res0NxR { + Res0NxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RES0 IEEE Underflow Flag"] + #[inline(always)] + pub fn res0_uf(&self) -> Res0UfR { + Res0UfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RES0 IEEE Overflow Flag"] + #[inline(always)] + pub fn res0_of(&self) -> Res0OfR { + Res0OfR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RES0 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res0_dz(&self) -> Res0DzR { + Res0DzR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RES0 IEEE Invalid Flag"] + #[inline(always)] + pub fn res0_nv(&self) -> Res0NvR { + Res0NvR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RES0 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res0_err(&self) -> Res0ErrR { + Res0ErrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RES0 Overwrite Flag"] + #[inline(always)] + pub fn res0_ovwr(&self) -> Res0OvwrR { + Res0OvwrR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - RES0 Full Flag"] + #[inline(always)] + pub fn res0_full(&self) -> Res0FullR { + Res0FullR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RES1 IEEE Inexact Flag"] + #[inline(always)] + pub fn res1_nx(&self) -> Res1NxR { + Res1NxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RES1 IEEE Underflow Flag"] + #[inline(always)] + pub fn res1_uf(&self) -> Res1UfR { + Res1UfR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - RES1 IEEE Overflow Flag"] + #[inline(always)] + pub fn res1_of(&self) -> Res1OfR { + Res1OfR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RES1 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res1_dz(&self) -> Res1DzR { + Res1DzR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - RES1 IEEE Invalid Flag"] + #[inline(always)] + pub fn res1_nv(&self) -> Res1NvR { + Res1NvR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - RES1 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res1_err(&self) -> Res1ErrR { + Res1ErrR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - RES1 Overwrite Flag"] + #[inline(always)] + pub fn res1_ovwr(&self) -> Res1OvwrR { + Res1OvwrR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - RES1 Full Flag"] + #[inline(always)] + pub fn res1_full(&self) -> Res1FullR { + Res1FullR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - RES2 IEEE Inexact Flag"] + #[inline(always)] + pub fn res2_nx(&self) -> Res2NxR { + Res2NxR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - RES2 IEEE Underflow Flag"] + #[inline(always)] + pub fn res2_uf(&self) -> Res2UfR { + Res2UfR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - RES2 IEEE Overflow Flag"] + #[inline(always)] + pub fn res2_of(&self) -> Res2OfR { + Res2OfR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - RES2 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res2_dz(&self) -> Res2DzR { + Res2DzR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - RES2 IEEE Invalid Flag"] + #[inline(always)] + pub fn res2_nv(&self) -> Res2NvR { + Res2NvR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - RES2 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res2_err(&self) -> Res2ErrR { + Res2ErrR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - RES2 Overwrite Flag"] + #[inline(always)] + pub fn res2_ovwr(&self) -> Res2OvwrR { + Res2OvwrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - RES2 Full Flag"] + #[inline(always)] + pub fn res2_full(&self) -> Res2FullR { + Res2FullR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - RES3 IEEE Inexact Flag"] + #[inline(always)] + pub fn res3_nx(&self) -> Res3NxR { + Res3NxR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - RES3 IEEE Underflow Flag"] + #[inline(always)] + pub fn res3_uf(&self) -> Res3UfR { + Res3UfR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - RES3 IEEE Overflow Flag"] + #[inline(always)] + pub fn res3_of(&self) -> Res3OfR { + Res3OfR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - RES3 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res3_dz(&self) -> Res3DzR { + Res3DzR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - RES3 IEEE Invalid Flag"] + #[inline(always)] + pub fn res3_nv(&self) -> Res3NvR { + Res3NvR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RES3 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res3_err(&self) -> Res3ErrR { + Res3ErrR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - RES3 Overwrite Flag"] + #[inline(always)] + pub fn res3_ovwr(&self) -> Res3OvwrR { + Res3OvwrR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - RES3 Full Flag"] + #[inline(always)] + pub fn res3_full(&self) -> Res3FullR { + Res3FullR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RES0 IEEE Inexact Flag"] + #[inline(always)] + pub fn res0_nx(&mut self) -> Res0NxW { + Res0NxW::new(self, 0) + } + #[doc = "Bit 1 - RES0 IEEE Underflow Flag"] + #[inline(always)] + pub fn res0_uf(&mut self) -> Res0UfW { + Res0UfW::new(self, 1) + } + #[doc = "Bit 2 - RES0 IEEE Overflow Flag"] + #[inline(always)] + pub fn res0_of(&mut self) -> Res0OfW { + Res0OfW::new(self, 2) + } + #[doc = "Bit 3 - RES0 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res0_dz(&mut self) -> Res0DzW { + Res0DzW::new(self, 3) + } + #[doc = "Bit 4 - RES0 IEEE Invalid Flag"] + #[inline(always)] + pub fn res0_nv(&mut self) -> Res0NvW { + Res0NvW::new(self, 4) + } + #[doc = "Bit 5 - RES0 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res0_err(&mut self) -> Res0ErrW { + Res0ErrW::new(self, 5) + } + #[doc = "Bit 6 - RES0 Overwrite Flag"] + #[inline(always)] + pub fn res0_ovwr(&mut self) -> Res0OvwrW { + Res0OvwrW::new(self, 6) + } + #[doc = "Bit 7 - RES0 Full Flag"] + #[inline(always)] + pub fn res0_full(&mut self) -> Res0FullW { + Res0FullW::new(self, 7) + } + #[doc = "Bit 8 - RES1 IEEE Inexact Flag"] + #[inline(always)] + pub fn res1_nx(&mut self) -> Res1NxW { + Res1NxW::new(self, 8) + } + #[doc = "Bit 9 - RES1 IEEE Underflow Flag"] + #[inline(always)] + pub fn res1_uf(&mut self) -> Res1UfW { + Res1UfW::new(self, 9) + } + #[doc = "Bit 10 - RES1 IEEE Overflow Flag"] + #[inline(always)] + pub fn res1_of(&mut self) -> Res1OfW { + Res1OfW::new(self, 10) + } + #[doc = "Bit 11 - RES1 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res1_dz(&mut self) -> Res1DzW { + Res1DzW::new(self, 11) + } + #[doc = "Bit 12 - RES1 IEEE Invalid Flag"] + #[inline(always)] + pub fn res1_nv(&mut self) -> Res1NvW { + Res1NvW::new(self, 12) + } + #[doc = "Bit 13 - RES1 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res1_err(&mut self) -> Res1ErrW { + Res1ErrW::new(self, 13) + } + #[doc = "Bit 14 - RES1 Overwrite Flag"] + #[inline(always)] + pub fn res1_ovwr(&mut self) -> Res1OvwrW { + Res1OvwrW::new(self, 14) + } + #[doc = "Bit 15 - RES1 Full Flag"] + #[inline(always)] + pub fn res1_full(&mut self) -> Res1FullW { + Res1FullW::new(self, 15) + } + #[doc = "Bit 16 - RES2 IEEE Inexact Flag"] + #[inline(always)] + pub fn res2_nx(&mut self) -> Res2NxW { + Res2NxW::new(self, 16) + } + #[doc = "Bit 17 - RES2 IEEE Underflow Flag"] + #[inline(always)] + pub fn res2_uf(&mut self) -> Res2UfW { + Res2UfW::new(self, 17) + } + #[doc = "Bit 18 - RES2 IEEE Overflow Flag"] + #[inline(always)] + pub fn res2_of(&mut self) -> Res2OfW { + Res2OfW::new(self, 18) + } + #[doc = "Bit 19 - RES2 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res2_dz(&mut self) -> Res2DzW { + Res2DzW::new(self, 19) + } + #[doc = "Bit 20 - RES2 IEEE Invalid Flag"] + #[inline(always)] + pub fn res2_nv(&mut self) -> Res2NvW { + Res2NvW::new(self, 20) + } + #[doc = "Bit 21 - RES2 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res2_err(&mut self) -> Res2ErrW { + Res2ErrW::new(self, 21) + } + #[doc = "Bit 22 - RES2 Overwrite Flag"] + #[inline(always)] + pub fn res2_ovwr(&mut self) -> Res2OvwrW { + Res2OvwrW::new(self, 22) + } + #[doc = "Bit 23 - RES2 Full Flag"] + #[inline(always)] + pub fn res2_full(&mut self) -> Res2FullW { + Res2FullW::new(self, 23) + } + #[doc = "Bit 24 - RES3 IEEE Inexact Flag"] + #[inline(always)] + pub fn res3_nx(&mut self) -> Res3NxW { + Res3NxW::new(self, 24) + } + #[doc = "Bit 25 - RES3 IEEE Underflow Flag"] + #[inline(always)] + pub fn res3_uf(&mut self) -> Res3UfW { + Res3UfW::new(self, 25) + } + #[doc = "Bit 26 - RES3 IEEE Overflow Flag"] + #[inline(always)] + pub fn res3_of(&mut self) -> Res3OfW { + Res3OfW::new(self, 26) + } + #[doc = "Bit 27 - RES3 IEEE Divide by Zero Flag"] + #[inline(always)] + pub fn res3_dz(&mut self) -> Res3DzW { + Res3DzW::new(self, 27) + } + #[doc = "Bit 28 - RES3 IEEE Invalid Flag"] + #[inline(always)] + pub fn res3_nv(&mut self) -> Res3NvW { + Res3NvW::new(self, 28) + } + #[doc = "Bit 29 - RES3 Indirect Operation Error Flag"] + #[inline(always)] + pub fn res3_err(&mut self) -> Res3ErrW { + Res3ErrW::new(self, 29) + } + #[doc = "Bit 30 - RES3 Overwrite Flag"] + #[inline(always)] + pub fn res3_ovwr(&mut self) -> Res3OvwrW { + Res3OvwrW::new(self, 30) + } + #[doc = "Bit 31 - RES3 Full Flag"] + #[inline(always)] + pub fn res3_full(&mut self) -> Res3FullW { + Res3FullW::new(self, 31) + } +} +#[doc = "Result Status\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ResStatusSpec; +impl crate::RegisterSpec for ResStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`res_status::R`](R) reader structure"] +impl crate::Readable for ResStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`res_status::W`](W) writer structure"] +impl crate::Writable for ResStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RES_STATUS to value 0"] +impl crate::Resettable for ResStatusSpec {} diff --git a/mcxa276-pac/src/mau0/res_status_ie.rs b/mcxa276-pac/src/mau0/res_status_ie.rs new file mode 100644 index 000000000..d05c45e0a --- /dev/null +++ b/mcxa276-pac/src/mau0/res_status_ie.rs @@ -0,0 +1,273 @@ +#[doc = "Register `RES_STATUS_IE` reader"] +pub type R = crate::R; +#[doc = "Register `RES_STATUS_IE` writer"] +pub type W = crate::W; +#[doc = "RES0 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res0Ie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res0Ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES0_IE` reader - RES0 Interrupt Enable"] +pub type Res0IeR = crate::BitReader; +impl Res0IeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res0Ie { + match self.bits { + false => Res0Ie::Disable, + true => Res0Ie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Res0Ie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Res0Ie::Enable + } +} +#[doc = "Field `RES0_IE` writer - RES0 Interrupt Enable"] +pub type Res0IeW<'a, REG> = crate::BitWriter<'a, REG, Res0Ie>; +impl<'a, REG> Res0IeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Res0Ie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Res0Ie::Enable) + } +} +#[doc = "RES1 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res1Ie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res1Ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES1_IE` reader - RES1 Interrupt Enable"] +pub type Res1IeR = crate::BitReader; +impl Res1IeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res1Ie { + match self.bits { + false => Res1Ie::Disable, + true => Res1Ie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Res1Ie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Res1Ie::Enable + } +} +#[doc = "Field `RES1_IE` writer - RES1 Interrupt Enable"] +pub type Res1IeW<'a, REG> = crate::BitWriter<'a, REG, Res1Ie>; +impl<'a, REG> Res1IeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Res1Ie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Res1Ie::Enable) + } +} +#[doc = "RES2 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res2Ie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res2Ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES2_IE` reader - RES2 Interrupt Enable"] +pub type Res2IeR = crate::BitReader; +impl Res2IeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res2Ie { + match self.bits { + false => Res2Ie::Disable, + true => Res2Ie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Res2Ie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Res2Ie::Enable + } +} +#[doc = "Field `RES2_IE` writer - RES2 Interrupt Enable"] +pub type Res2IeW<'a, REG> = crate::BitWriter<'a, REG, Res2Ie>; +impl<'a, REG> Res2IeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Res2Ie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Res2Ie::Enable) + } +} +#[doc = "RES3 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Res3Ie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Res3Ie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RES3_IE` reader - RES3 Interrupt Enable"] +pub type Res3IeR = crate::BitReader; +impl Res3IeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Res3Ie { + match self.bits { + false => Res3Ie::Disable, + true => Res3Ie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Res3Ie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Res3Ie::Enable + } +} +#[doc = "Field `RES3_IE` writer - RES3 Interrupt Enable"] +pub type Res3IeW<'a, REG> = crate::BitWriter<'a, REG, Res3Ie>; +impl<'a, REG> Res3IeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Res3Ie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Res3Ie::Enable) + } +} +impl R { + #[doc = "Bit 0 - RES0 Interrupt Enable"] + #[inline(always)] + pub fn res0_ie(&self) -> Res0IeR { + Res0IeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RES1 Interrupt Enable"] + #[inline(always)] + pub fn res1_ie(&self) -> Res1IeR { + Res1IeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RES2 Interrupt Enable"] + #[inline(always)] + pub fn res2_ie(&self) -> Res2IeR { + Res2IeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RES3 Interrupt Enable"] + #[inline(always)] + pub fn res3_ie(&self) -> Res3IeR { + Res3IeR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RES0 Interrupt Enable"] + #[inline(always)] + pub fn res0_ie(&mut self) -> Res0IeW { + Res0IeW::new(self, 0) + } + #[doc = "Bit 1 - RES1 Interrupt Enable"] + #[inline(always)] + pub fn res1_ie(&mut self) -> Res1IeW { + Res1IeW::new(self, 1) + } + #[doc = "Bit 2 - RES2 Interrupt Enable"] + #[inline(always)] + pub fn res2_ie(&mut self) -> Res2IeW { + Res2IeW::new(self, 2) + } + #[doc = "Bit 3 - RES3 Interrupt Enable"] + #[inline(always)] + pub fn res3_ie(&mut self) -> Res3IeW { + Res3IeW::new(self, 3) + } +} +#[doc = "Result Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status_ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status_ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ResStatusIeSpec; +impl crate::RegisterSpec for ResStatusIeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`res_status_ie::R`](R) reader structure"] +impl crate::Readable for ResStatusIeSpec {} +#[doc = "`write(|w| ..)` method takes [`res_status_ie::W`](W) writer structure"] +impl crate::Writable for ResStatusIeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RES_STATUS_IE to value 0"] +impl crate::Resettable for ResStatusIeSpec {} diff --git a/mcxa276-pac/src/mau0/sys_ctlr.rs b/mcxa276-pac/src/mau0/sys_ctlr.rs new file mode 100644 index 000000000..55c969788 --- /dev/null +++ b/mcxa276-pac/src/mau0/sys_ctlr.rs @@ -0,0 +1,86 @@ +#[doc = "Register `SYS_CTLR` reader"] +pub type R = crate::R; +#[doc = "Register `SYS_CTLR` writer"] +pub type W = crate::W; +#[doc = "Automatic Clock Gating Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum AcgEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: AcgEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACG_EN` reader - Automatic Clock Gating Enable"] +pub type AcgEnR = crate::BitReader; +impl AcgEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> AcgEn { + match self.bits { + false => AcgEn::Disable, + true => AcgEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == AcgEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == AcgEn::Enable + } +} +#[doc = "Field `ACG_EN` writer - Automatic Clock Gating Enable"] +pub type AcgEnW<'a, REG> = crate::BitWriter<'a, REG, AcgEn>; +impl<'a, REG> AcgEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(AcgEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(AcgEn::Enable) + } +} +impl R { + #[doc = "Bit 0 - Automatic Clock Gating Enable"] + #[inline(always)] + pub fn acg_en(&self) -> AcgEnR { + AcgEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Automatic Clock Gating Enable"] + #[inline(always)] + pub fn acg_en(&mut self) -> AcgEnW { + AcgEnW::new(self, 0) + } +} +#[doc = "System Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SysCtlrSpec; +impl crate::RegisterSpec for SysCtlrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys_ctlr::R`](R) reader structure"] +impl crate::Readable for SysCtlrSpec {} +#[doc = "`write(|w| ..)` method takes [`sys_ctlr::W`](W) writer structure"] +impl crate::Writable for SysCtlrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYS_CTLR to value 0x01"] +impl crate::Resettable for SysCtlrSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/mbc0.rs b/mcxa276-pac/src/mbc0.rs new file mode 100644 index 000000000..56b3c880b --- /dev/null +++ b/mcxa276-pac/src/mbc0.rs @@ -0,0 +1,350 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mbc0_mem0_glbcfg: Mbc0Mem0Glbcfg, + mbc0_mem1_glbcfg: Mbc0Mem1Glbcfg, + mbc0_mem2_glbcfg: Mbc0Mem2Glbcfg, + mbc0_mem3_glbcfg: Mbc0Mem3Glbcfg, + _reserved4: [u8; 0x10], + mbc0_memn_glbac0: Mbc0MemnGlbac0, + mbc0_memn_glbac1: Mbc0MemnGlbac1, + mbc0_memn_glbac2: Mbc0MemnGlbac2, + mbc0_memn_glbac3: Mbc0MemnGlbac3, + mbc0_memn_glbac4: Mbc0MemnGlbac4, + mbc0_memn_glbac5: Mbc0MemnGlbac5, + mbc0_memn_glbac6: Mbc0MemnGlbac6, + mbc0_memn_glbac7: Mbc0MemnGlbac7, + mbc0_dom0_mem0_blk_cfg_w0: Mbc0Dom0Mem0BlkCfgW0, + mbc0_dom0_mem0_blk_cfg_w1: Mbc0Dom0Mem0BlkCfgW1, + mbc0_dom0_mem0_blk_cfg_w2: Mbc0Dom0Mem0BlkCfgW2, + mbc0_dom0_mem0_blk_cfg_w3: Mbc0Dom0Mem0BlkCfgW3, + mbc0_dom0_mem0_blk_cfg_w4: Mbc0Dom0Mem0BlkCfgW4, + mbc0_dom0_mem0_blk_cfg_w5: Mbc0Dom0Mem0BlkCfgW5, + mbc0_dom0_mem0_blk_cfg_w6: Mbc0Dom0Mem0BlkCfgW6, + mbc0_dom0_mem0_blk_cfg_w7: Mbc0Dom0Mem0BlkCfgW7, + mbc0_dom0_mem0_blk_cfg_w8: Mbc0Dom0Mem0BlkCfgW8, + mbc0_dom0_mem0_blk_cfg_w9: Mbc0Dom0Mem0BlkCfgW9, + mbc0_dom0_mem0_blk_cfg_w10: Mbc0Dom0Mem0BlkCfgW10, + mbc0_dom0_mem0_blk_cfg_w11: Mbc0Dom0Mem0BlkCfgW11, + mbc0_dom0_mem0_blk_cfg_w12: Mbc0Dom0Mem0BlkCfgW12, + mbc0_dom0_mem0_blk_cfg_w13: Mbc0Dom0Mem0BlkCfgW13, + mbc0_dom0_mem0_blk_cfg_w14: Mbc0Dom0Mem0BlkCfgW14, + mbc0_dom0_mem0_blk_cfg_w15: Mbc0Dom0Mem0BlkCfgW15, + _reserved28: [u8; 0x0100], + mbc0_dom0_mem1_blk_cfg_w0: Mbc0Dom0Mem1BlkCfgW0, + mbc0_dom0_mem1_blk_cfg_w1: Mbc0Dom0Mem1BlkCfgW1, + _reserved30: [u8; 0x20], + mbc0_dom0_mem2_blk_cfg_w0: Mbc0Dom0Mem2BlkCfgW0, +} +impl RegisterBlock { + #[doc = "0x00 - MBC Global Configuration Register"] + #[inline(always)] + pub const fn mbc0_mem0_glbcfg(&self) -> &Mbc0Mem0Glbcfg { + &self.mbc0_mem0_glbcfg + } + #[doc = "0x04 - MBC Global Configuration Register"] + #[inline(always)] + pub const fn mbc0_mem1_glbcfg(&self) -> &Mbc0Mem1Glbcfg { + &self.mbc0_mem1_glbcfg + } + #[doc = "0x08 - MBC Global Configuration Register"] + #[inline(always)] + pub const fn mbc0_mem2_glbcfg(&self) -> &Mbc0Mem2Glbcfg { + &self.mbc0_mem2_glbcfg + } + #[doc = "0x0c - MBC Global Configuration Register"] + #[inline(always)] + pub const fn mbc0_mem3_glbcfg(&self) -> &Mbc0Mem3Glbcfg { + &self.mbc0_mem3_glbcfg + } + #[doc = "0x20 - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac0(&self) -> &Mbc0MemnGlbac0 { + &self.mbc0_memn_glbac0 + } + #[doc = "0x24 - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac1(&self) -> &Mbc0MemnGlbac1 { + &self.mbc0_memn_glbac1 + } + #[doc = "0x28 - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac2(&self) -> &Mbc0MemnGlbac2 { + &self.mbc0_memn_glbac2 + } + #[doc = "0x2c - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac3(&self) -> &Mbc0MemnGlbac3 { + &self.mbc0_memn_glbac3 + } + #[doc = "0x30 - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac4(&self) -> &Mbc0MemnGlbac4 { + &self.mbc0_memn_glbac4 + } + #[doc = "0x34 - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac5(&self) -> &Mbc0MemnGlbac5 { + &self.mbc0_memn_glbac5 + } + #[doc = "0x38 - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac6(&self) -> &Mbc0MemnGlbac6 { + &self.mbc0_memn_glbac6 + } + #[doc = "0x3c - MBC Global Access Control"] + #[inline(always)] + pub const fn mbc0_memn_glbac7(&self) -> &Mbc0MemnGlbac7 { + &self.mbc0_memn_glbac7 + } + #[doc = "0x40 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w0(&self) -> &Mbc0Dom0Mem0BlkCfgW0 { + &self.mbc0_dom0_mem0_blk_cfg_w0 + } + #[doc = "0x44 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w1(&self) -> &Mbc0Dom0Mem0BlkCfgW1 { + &self.mbc0_dom0_mem0_blk_cfg_w1 + } + #[doc = "0x48 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w2(&self) -> &Mbc0Dom0Mem0BlkCfgW2 { + &self.mbc0_dom0_mem0_blk_cfg_w2 + } + #[doc = "0x4c - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w3(&self) -> &Mbc0Dom0Mem0BlkCfgW3 { + &self.mbc0_dom0_mem0_blk_cfg_w3 + } + #[doc = "0x50 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w4(&self) -> &Mbc0Dom0Mem0BlkCfgW4 { + &self.mbc0_dom0_mem0_blk_cfg_w4 + } + #[doc = "0x54 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w5(&self) -> &Mbc0Dom0Mem0BlkCfgW5 { + &self.mbc0_dom0_mem0_blk_cfg_w5 + } + #[doc = "0x58 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w6(&self) -> &Mbc0Dom0Mem0BlkCfgW6 { + &self.mbc0_dom0_mem0_blk_cfg_w6 + } + #[doc = "0x5c - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w7(&self) -> &Mbc0Dom0Mem0BlkCfgW7 { + &self.mbc0_dom0_mem0_blk_cfg_w7 + } + #[doc = "0x60 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w8(&self) -> &Mbc0Dom0Mem0BlkCfgW8 { + &self.mbc0_dom0_mem0_blk_cfg_w8 + } + #[doc = "0x64 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w9(&self) -> &Mbc0Dom0Mem0BlkCfgW9 { + &self.mbc0_dom0_mem0_blk_cfg_w9 + } + #[doc = "0x68 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w10(&self) -> &Mbc0Dom0Mem0BlkCfgW10 { + &self.mbc0_dom0_mem0_blk_cfg_w10 + } + #[doc = "0x6c - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w11(&self) -> &Mbc0Dom0Mem0BlkCfgW11 { + &self.mbc0_dom0_mem0_blk_cfg_w11 + } + #[doc = "0x70 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w12(&self) -> &Mbc0Dom0Mem0BlkCfgW12 { + &self.mbc0_dom0_mem0_blk_cfg_w12 + } + #[doc = "0x74 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w13(&self) -> &Mbc0Dom0Mem0BlkCfgW13 { + &self.mbc0_dom0_mem0_blk_cfg_w13 + } + #[doc = "0x78 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w14(&self) -> &Mbc0Dom0Mem0BlkCfgW14 { + &self.mbc0_dom0_mem0_blk_cfg_w14 + } + #[doc = "0x7c - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem0_blk_cfg_w15(&self) -> &Mbc0Dom0Mem0BlkCfgW15 { + &self.mbc0_dom0_mem0_blk_cfg_w15 + } + #[doc = "0x180 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem1_blk_cfg_w0(&self) -> &Mbc0Dom0Mem1BlkCfgW0 { + &self.mbc0_dom0_mem1_blk_cfg_w0 + } + #[doc = "0x184 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem1_blk_cfg_w1(&self) -> &Mbc0Dom0Mem1BlkCfgW1 { + &self.mbc0_dom0_mem1_blk_cfg_w1 + } + #[doc = "0x1a8 - MBC Memory Block Configuration Word"] + #[inline(always)] + pub const fn mbc0_dom0_mem2_blk_cfg_w0(&self) -> &Mbc0Dom0Mem2BlkCfgW0 { + &self.mbc0_dom0_mem2_blk_cfg_w0 + } +} +#[doc = "MBC0_MEM0_GLBCFG (r) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem0_glbcfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem0_glbcfg`] module"] +#[doc(alias = "MBC0_MEM0_GLBCFG")] +pub type Mbc0Mem0Glbcfg = crate::Reg; +#[doc = "MBC Global Configuration Register"] +pub mod mbc0_mem0_glbcfg; +#[doc = "MBC0_MEM1_GLBCFG (r) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem1_glbcfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem1_glbcfg`] module"] +#[doc(alias = "MBC0_MEM1_GLBCFG")] +pub type Mbc0Mem1Glbcfg = crate::Reg; +#[doc = "MBC Global Configuration Register"] +pub mod mbc0_mem1_glbcfg; +#[doc = "MBC0_MEM2_GLBCFG (r) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem2_glbcfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem2_glbcfg`] module"] +#[doc(alias = "MBC0_MEM2_GLBCFG")] +pub type Mbc0Mem2Glbcfg = crate::Reg; +#[doc = "MBC Global Configuration Register"] +pub mod mbc0_mem2_glbcfg; +#[doc = "MBC0_MEM3_GLBCFG (rw) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem3_glbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_mem3_glbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem3_glbcfg`] module"] +#[doc(alias = "MBC0_MEM3_GLBCFG")] +pub type Mbc0Mem3Glbcfg = crate::Reg; +#[doc = "MBC Global Configuration Register"] +pub mod mbc0_mem3_glbcfg; +#[doc = "MBC0_MEMN_GLBAC0 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac0`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC0")] +pub type Mbc0MemnGlbac0 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac0; +#[doc = "MBC0_MEMN_GLBAC1 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac1`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC1")] +pub type Mbc0MemnGlbac1 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac1; +#[doc = "MBC0_MEMN_GLBAC2 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac2`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC2")] +pub type Mbc0MemnGlbac2 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac2; +#[doc = "MBC0_MEMN_GLBAC3 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac3`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC3")] +pub type Mbc0MemnGlbac3 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac3; +#[doc = "MBC0_MEMN_GLBAC4 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac4`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC4")] +pub type Mbc0MemnGlbac4 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac4; +#[doc = "MBC0_MEMN_GLBAC5 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac5`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC5")] +pub type Mbc0MemnGlbac5 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac5; +#[doc = "MBC0_MEMN_GLBAC6 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac6`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC6")] +pub type Mbc0MemnGlbac6 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac6; +#[doc = "MBC0_MEMN_GLBAC7 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac7`] module"] +#[doc(alias = "MBC0_MEMN_GLBAC7")] +pub type Mbc0MemnGlbac7 = crate::Reg; +#[doc = "MBC Global Access Control"] +pub mod mbc0_memn_glbac7; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W0 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w0`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W0")] +pub type Mbc0Dom0Mem0BlkCfgW0 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w0; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W1 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w1`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W1")] +pub type Mbc0Dom0Mem0BlkCfgW1 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w1; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W2 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w2`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W2")] +pub type Mbc0Dom0Mem0BlkCfgW2 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w2; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W3 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w3`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W3")] +pub type Mbc0Dom0Mem0BlkCfgW3 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w3; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W4 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w4`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W4")] +pub type Mbc0Dom0Mem0BlkCfgW4 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w4; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W5 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w5`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W5")] +pub type Mbc0Dom0Mem0BlkCfgW5 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w5; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W6 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w6`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W6")] +pub type Mbc0Dom0Mem0BlkCfgW6 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w6; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W7 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w7`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W7")] +pub type Mbc0Dom0Mem0BlkCfgW7 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w7; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W8 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w8`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W8")] +pub type Mbc0Dom0Mem0BlkCfgW8 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w8; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W9 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w9`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W9")] +pub type Mbc0Dom0Mem0BlkCfgW9 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w9; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W10 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w10`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W10")] +pub type Mbc0Dom0Mem0BlkCfgW10 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w10; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W11 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w11`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W11")] +pub type Mbc0Dom0Mem0BlkCfgW11 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w11; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W12 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w12`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W12")] +pub type Mbc0Dom0Mem0BlkCfgW12 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w12; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W13 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w13`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W13")] +pub type Mbc0Dom0Mem0BlkCfgW13 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w13; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W14 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w14`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W14")] +pub type Mbc0Dom0Mem0BlkCfgW14 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w14; +#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W15 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w15`] module"] +#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W15")] +pub type Mbc0Dom0Mem0BlkCfgW15 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem0_blk_cfg_w15; +#[doc = "MBC0_DOM0_MEM1_BLK_CFG_W0 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem1_blk_cfg_w0`] module"] +#[doc(alias = "MBC0_DOM0_MEM1_BLK_CFG_W0")] +pub type Mbc0Dom0Mem1BlkCfgW0 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem1_blk_cfg_w0; +#[doc = "MBC0_DOM0_MEM1_BLK_CFG_W1 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem1_blk_cfg_w1`] module"] +#[doc(alias = "MBC0_DOM0_MEM1_BLK_CFG_W1")] +pub type Mbc0Dom0Mem1BlkCfgW1 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem1_blk_cfg_w1; +#[doc = "MBC0_DOM0_MEM2_BLK_CFG_W0 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem2_blk_cfg_w0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem2_blk_cfg_w0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem2_blk_cfg_w0`] module"] +#[doc(alias = "MBC0_DOM0_MEM2_BLK_CFG_W0")] +pub type Mbc0Dom0Mem2BlkCfgW0 = crate::Reg; +#[doc = "MBC Memory Block Configuration Word"] +pub mod mbc0_dom0_mem2_blk_cfg_w0; diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs new file mode 100644 index 000000000..f46509afc --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W0` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W0` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW0Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w0::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW0Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w0::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W0 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW0Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs new file mode 100644 index 000000000..5e7da22b2 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W1` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W1` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW1Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w1::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW1Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w1::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W1 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW1Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs new file mode 100644 index 000000000..0149832d9 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W10` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W10` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW10Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w10::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW10Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w10::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W10 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW10Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs new file mode 100644 index 000000000..69f032e29 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W11` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W11` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW11Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w11::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW11Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w11::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W11 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW11Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs new file mode 100644 index 000000000..51035d48d --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W12` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W12` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW12Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w12::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW12Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w12::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W12 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW12Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs new file mode 100644 index 000000000..a326ab10a --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W13` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W13` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW13Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w13::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW13Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w13::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W13 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW13Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs new file mode 100644 index 000000000..85bf5a398 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W14` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W14` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW14Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w14::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW14Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w14::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W14 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW14Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs new file mode 100644 index 000000000..fa7bd6c31 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W15` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W15` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW15Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w15::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW15Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w15::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W15 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW15Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs new file mode 100644 index 000000000..3fa9b0b69 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W2` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W2` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW2Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w2::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW2Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w2::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W2 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW2Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs new file mode 100644 index 000000000..e000ae206 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W3` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W3` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW3Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w3::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW3Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w3::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W3 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW3Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs new file mode 100644 index 000000000..d69c63ba9 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W4` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W4` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW4Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w4::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW4Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w4::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W4 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW4Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs new file mode 100644 index 000000000..1b841299f --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W5` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W5` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW5Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w5::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW5Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w5::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W5 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW5Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs new file mode 100644 index 000000000..b574cb02e --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W6` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W6` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW6Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w6::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW6Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w6::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W6 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW6Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs new file mode 100644 index 000000000..e8f48713f --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W7` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W7` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW7Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w7::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW7Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w7::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W7 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW7Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs new file mode 100644 index 000000000..fa964fba7 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W8` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W8` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW8Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w8::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW8Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w8::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W8 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW8Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs new file mode 100644 index 000000000..f04f97145 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W9` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W9` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem0BlkCfgW9Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w9::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem0BlkCfgW9Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w9::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem0BlkCfgW9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W9 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW9Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs new file mode 100644 index 000000000..d764de3d4 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W0` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W0` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem1BlkCfgW0Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem1BlkCfgW0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem1_blk_cfg_w0::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem1BlkCfgW0Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem1_blk_cfg_w0::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem1BlkCfgW0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM1_BLK_CFG_W0 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem1BlkCfgW0Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs new file mode 100644 index 000000000..efd2bea14 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W1` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W1` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem1BlkCfgW1Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem1BlkCfgW1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem1_blk_cfg_w1::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem1BlkCfgW1Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem1_blk_cfg_w1::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem1BlkCfgW1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM1_BLK_CFG_W1 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem1BlkCfgW1Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs new file mode 100644 index 000000000..13d452400 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs @@ -0,0 +1,1709 @@ +#[doc = "Register `MBC0_DOM0_MEM2_BLK_CFG_W0` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_DOM0_MEM2_BLK_CFG_W0` writer"] +pub type W = crate::W; +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel0 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel0 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel0 {} +#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel0R = crate::FieldReader; +impl Mbacsel0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel0 { + match self.bits { + 0 => Mbacsel0::Glbac0, + 1 => Mbacsel0::Glbac1, + 2 => Mbacsel0::Glbac2, + 3 => Mbacsel0::Glbac3, + 4 => Mbacsel0::Glbac4, + 5 => Mbacsel0::Glbac5, + 6 => Mbacsel0::Glbac6, + 7 => Mbacsel0::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel0::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel0::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel0::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel0::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel0::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel0::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel0::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel0::Glbac7 + } +} +#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; +impl<'a, REG> Mbacsel0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel0::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse0 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] +pub type Nse0R = crate::BitReader; +impl Nse0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse0 { + match self.bits { + false => Nse0::Allowed, + true => Nse0::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse0::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse0::Notallowed + } +} +#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] +pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; +impl<'a, REG> Nse0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse0::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse0::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel1 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel1 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel1 {} +#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel1R = crate::FieldReader; +impl Mbacsel1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel1 { + match self.bits { + 0 => Mbacsel1::Glbac0, + 1 => Mbacsel1::Glbac1, + 2 => Mbacsel1::Glbac2, + 3 => Mbacsel1::Glbac3, + 4 => Mbacsel1::Glbac4, + 5 => Mbacsel1::Glbac5, + 6 => Mbacsel1::Glbac6, + 7 => Mbacsel1::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel1::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel1::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel1::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel1::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel1::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel1::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel1::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel1::Glbac7 + } +} +#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; +impl<'a, REG> Mbacsel1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel1::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse1 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] +pub type Nse1R = crate::BitReader; +impl Nse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse1 { + match self.bits { + false => Nse1::Allowed, + true => Nse1::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse1::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse1::Notallowed + } +} +#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] +pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; +impl<'a, REG> Nse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse1::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse1::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel2 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel2 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel2 {} +#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel2R = crate::FieldReader; +impl Mbacsel2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel2 { + match self.bits { + 0 => Mbacsel2::Glbac0, + 1 => Mbacsel2::Glbac1, + 2 => Mbacsel2::Glbac2, + 3 => Mbacsel2::Glbac3, + 4 => Mbacsel2::Glbac4, + 5 => Mbacsel2::Glbac5, + 6 => Mbacsel2::Glbac6, + 7 => Mbacsel2::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel2::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel2::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel2::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel2::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel2::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel2::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel2::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel2::Glbac7 + } +} +#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; +impl<'a, REG> Mbacsel2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel2::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse2 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] +pub type Nse2R = crate::BitReader; +impl Nse2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse2 { + match self.bits { + false => Nse2::Allowed, + true => Nse2::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse2::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse2::Notallowed + } +} +#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] +pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; +impl<'a, REG> Nse2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse2::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse2::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel3 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel3 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel3 {} +#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel3R = crate::FieldReader; +impl Mbacsel3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel3 { + match self.bits { + 0 => Mbacsel3::Glbac0, + 1 => Mbacsel3::Glbac1, + 2 => Mbacsel3::Glbac2, + 3 => Mbacsel3::Glbac3, + 4 => Mbacsel3::Glbac4, + 5 => Mbacsel3::Glbac5, + 6 => Mbacsel3::Glbac6, + 7 => Mbacsel3::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel3::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel3::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel3::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel3::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel3::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel3::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel3::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel3::Glbac7 + } +} +#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; +impl<'a, REG> Mbacsel3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel3::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse3 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] +pub type Nse3R = crate::BitReader; +impl Nse3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse3 { + match self.bits { + false => Nse3::Allowed, + true => Nse3::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse3::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse3::Notallowed + } +} +#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] +pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; +impl<'a, REG> Nse3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse3::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse3::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel4 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel4 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel4 {} +#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel4R = crate::FieldReader; +impl Mbacsel4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel4 { + match self.bits { + 0 => Mbacsel4::Glbac0, + 1 => Mbacsel4::Glbac1, + 2 => Mbacsel4::Glbac2, + 3 => Mbacsel4::Glbac3, + 4 => Mbacsel4::Glbac4, + 5 => Mbacsel4::Glbac5, + 6 => Mbacsel4::Glbac6, + 7 => Mbacsel4::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel4::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel4::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel4::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel4::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel4::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel4::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel4::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel4::Glbac7 + } +} +#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; +impl<'a, REG> Mbacsel4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel4::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse4 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] +pub type Nse4R = crate::BitReader; +impl Nse4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse4 { + match self.bits { + false => Nse4::Allowed, + true => Nse4::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse4::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse4::Notallowed + } +} +#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] +pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; +impl<'a, REG> Nse4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse4::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse4::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel5 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel5 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel5 {} +#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel5R = crate::FieldReader; +impl Mbacsel5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel5 { + match self.bits { + 0 => Mbacsel5::Glbac0, + 1 => Mbacsel5::Glbac1, + 2 => Mbacsel5::Glbac2, + 3 => Mbacsel5::Glbac3, + 4 => Mbacsel5::Glbac4, + 5 => Mbacsel5::Glbac5, + 6 => Mbacsel5::Glbac6, + 7 => Mbacsel5::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel5::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel5::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel5::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel5::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel5::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel5::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel5::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel5::Glbac7 + } +} +#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; +impl<'a, REG> Mbacsel5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel5::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse5 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] +pub type Nse5R = crate::BitReader; +impl Nse5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse5 { + match self.bits { + false => Nse5::Allowed, + true => Nse5::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse5::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse5::Notallowed + } +} +#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] +pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; +impl<'a, REG> Nse5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse5::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse5::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel6 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel6 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel6 {} +#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel6R = crate::FieldReader; +impl Mbacsel6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel6 { + match self.bits { + 0 => Mbacsel6::Glbac0, + 1 => Mbacsel6::Glbac1, + 2 => Mbacsel6::Glbac2, + 3 => Mbacsel6::Glbac3, + 4 => Mbacsel6::Glbac4, + 5 => Mbacsel6::Glbac5, + 6 => Mbacsel6::Glbac6, + 7 => Mbacsel6::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel6::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel6::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel6::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel6::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel6::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel6::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel6::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel6::Glbac7 + } +} +#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; +impl<'a, REG> Mbacsel6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel6::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse6 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] +pub type Nse6R = crate::BitReader; +impl Nse6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse6 { + match self.bits { + false => Nse6::Allowed, + true => Nse6::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse6::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse6::Notallowed + } +} +#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] +pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; +impl<'a, REG> Nse6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse6::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse6::Notallowed) + } +} +#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mbacsel7 { + #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] + Glbac0 = 0, + #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] + Glbac1 = 1, + #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] + Glbac2 = 2, + #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] + Glbac3 = 3, + #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] + Glbac4 = 4, + #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] + Glbac5 = 5, + #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] + Glbac6 = 6, + #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] + Glbac7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mbacsel7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mbacsel7 { + type Ux = u8; +} +impl crate::IsEnum for Mbacsel7 {} +#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] +pub type Mbacsel7R = crate::FieldReader; +impl Mbacsel7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mbacsel7 { + match self.bits { + 0 => Mbacsel7::Glbac0, + 1 => Mbacsel7::Glbac1, + 2 => Mbacsel7::Glbac2, + 3 => Mbacsel7::Glbac3, + 4 => Mbacsel7::Glbac4, + 5 => Mbacsel7::Glbac5, + 6 => Mbacsel7::Glbac6, + 7 => Mbacsel7::Glbac7, + _ => unreachable!(), + } + } + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn is_glbac0(&self) -> bool { + *self == Mbacsel7::Glbac0 + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn is_glbac1(&self) -> bool { + *self == Mbacsel7::Glbac1 + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn is_glbac2(&self) -> bool { + *self == Mbacsel7::Glbac2 + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn is_glbac3(&self) -> bool { + *self == Mbacsel7::Glbac3 + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn is_glbac4(&self) -> bool { + *self == Mbacsel7::Glbac4 + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn is_glbac5(&self) -> bool { + *self == Mbacsel7::Glbac5 + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn is_glbac6(&self) -> bool { + *self == Mbacsel7::Glbac6 + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn is_glbac7(&self) -> bool { + *self == Mbacsel7::Glbac7 + } +} +#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] +pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; +impl<'a, REG> Mbacsel7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] + #[inline(always)] + pub fn glbac0(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac0) + } + #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] + #[inline(always)] + pub fn glbac1(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac1) + } + #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] + #[inline(always)] + pub fn glbac2(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac2) + } + #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] + #[inline(always)] + pub fn glbac3(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac3) + } + #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] + #[inline(always)] + pub fn glbac4(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac4) + } + #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] + #[inline(always)] + pub fn glbac5(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac5) + } + #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] + #[inline(always)] + pub fn glbac6(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac6) + } + #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] + #[inline(always)] + pub fn glbac7(self) -> &'a mut crate::W { + self.variant(Mbacsel7::Glbac7) + } +} +#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nse7 { + #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + Allowed = 0, + #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + Notallowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nse7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] +pub type Nse7R = crate::BitReader; +impl Nse7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nse7 { + match self.bits { + false => Nse7::Allowed, + true => Nse7::Notallowed, + } + } + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nse7::Allowed + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nse7::Notallowed + } +} +#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] +pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; +impl<'a, REG> Nse7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nse7::Allowed) + } + #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nse7::Notallowed) + } +} +impl R { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&self) -> Mbacsel0R { + Mbacsel0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&self) -> Nse0R { + Nse0R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&self) -> Mbacsel1R { + Mbacsel1R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&self) -> Nse1R { + Nse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&self) -> Mbacsel2R { + Mbacsel2R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&self) -> Nse2R { + Nse2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&self) -> Mbacsel3R { + Mbacsel3R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&self) -> Nse3R { + Nse3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&self) -> Mbacsel4R { + Mbacsel4R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&self) -> Nse4R { + Nse4R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&self) -> Mbacsel5R { + Mbacsel5R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&self) -> Nse5R { + Nse5R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&self) -> Mbacsel6R { + Mbacsel6R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&self) -> Nse6R { + Nse6R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&self) -> Mbacsel7R { + Mbacsel7R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&self) -> Nse7R { + Nse7R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel0(&mut self) -> Mbacsel0W { + Mbacsel0W::new(self, 0) + } + #[doc = "Bit 3 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse0(&mut self) -> Nse0W { + Nse0W::new(self, 3) + } + #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel1(&mut self) -> Mbacsel1W { + Mbacsel1W::new(self, 4) + } + #[doc = "Bit 7 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse1(&mut self) -> Nse1W { + Nse1W::new(self, 7) + } + #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel2(&mut self) -> Mbacsel2W { + Mbacsel2W::new(self, 8) + } + #[doc = "Bit 11 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse2(&mut self) -> Nse2W { + Nse2W::new(self, 11) + } + #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel3(&mut self) -> Mbacsel3W { + Mbacsel3W::new(self, 12) + } + #[doc = "Bit 15 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse3(&mut self) -> Nse3W { + Nse3W::new(self, 15) + } + #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel4(&mut self) -> Mbacsel4W { + Mbacsel4W::new(self, 16) + } + #[doc = "Bit 19 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse4(&mut self) -> Nse4W { + Nse4W::new(self, 19) + } + #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel5(&mut self) -> Mbacsel5W { + Mbacsel5W::new(self, 20) + } + #[doc = "Bit 23 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse5(&mut self) -> Nse5W { + Nse5W::new(self, 23) + } + #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel6(&mut self) -> Mbacsel6W { + Mbacsel6W::new(self, 24) + } + #[doc = "Bit 27 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse6(&mut self) -> Nse6W { + Nse6W::new(self, 27) + } + #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] + #[inline(always)] + pub fn mbacsel7(&mut self) -> Mbacsel7W { + Mbacsel7W::new(self, 28) + } + #[doc = "Bit 31 - NonSecure Enable for block B"] + #[inline(always)] + pub fn nse7(&mut self) -> Nse7W { + Nse7W::new(self, 31) + } +} +#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem2_blk_cfg_w0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem2_blk_cfg_w0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Dom0Mem2BlkCfgW0Spec; +impl crate::RegisterSpec for Mbc0Dom0Mem2BlkCfgW0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_dom0_mem2_blk_cfg_w0::R`](R) reader structure"] +impl crate::Readable for Mbc0Dom0Mem2BlkCfgW0Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem2_blk_cfg_w0::W`](W) writer structure"] +impl crate::Writable for Mbc0Dom0Mem2BlkCfgW0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_DOM0_MEM2_BLK_CFG_W0 to value 0"] +impl crate::Resettable for Mbc0Dom0Mem2BlkCfgW0Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs new file mode 100644 index 000000000..a1e105c7b --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs @@ -0,0 +1,29 @@ +#[doc = "Register `MBC0_MEM0_GLBCFG` reader"] +pub type R = crate::R; +#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] +pub type NblksR = crate::FieldReader; +#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] +pub type SizeLog2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Number of blocks in this memory"] + #[inline(always)] + pub fn nblks(&self) -> NblksR { + NblksR::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:20 - Log2 size per block"] + #[inline(always)] + pub fn size_log2(&self) -> SizeLog2R { + SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) + } +} +#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem0_glbcfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Mem0GlbcfgSpec; +impl crate::RegisterSpec for Mbc0Mem0GlbcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_mem0_glbcfg::R`](R) reader structure"] +impl crate::Readable for Mbc0Mem0GlbcfgSpec {} +#[doc = "`reset()` method sets MBC0_MEM0_GLBCFG to value 0x000d_0080"] +impl crate::Resettable for Mbc0Mem0GlbcfgSpec { + const RESET_VALUE: u32 = 0x000d_0080; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs new file mode 100644 index 000000000..b36ca09ab --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs @@ -0,0 +1,29 @@ +#[doc = "Register `MBC0_MEM1_GLBCFG` reader"] +pub type R = crate::R; +#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] +pub type NblksR = crate::FieldReader; +#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] +pub type SizeLog2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Number of blocks in this memory"] + #[inline(always)] + pub fn nblks(&self) -> NblksR { + NblksR::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:20 - Log2 size per block"] + #[inline(always)] + pub fn size_log2(&self) -> SizeLog2R { + SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) + } +} +#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem1_glbcfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Mem1GlbcfgSpec; +impl crate::RegisterSpec for Mbc0Mem1GlbcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_mem1_glbcfg::R`](R) reader structure"] +impl crate::Readable for Mbc0Mem1GlbcfgSpec {} +#[doc = "`reset()` method sets MBC0_MEM1_GLBCFG to value 0x000b_0010"] +impl crate::Resettable for Mbc0Mem1GlbcfgSpec { + const RESET_VALUE: u32 = 0x000b_0010; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs new file mode 100644 index 000000000..c7f2b4f41 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs @@ -0,0 +1,29 @@ +#[doc = "Register `MBC0_MEM2_GLBCFG` reader"] +pub type R = crate::R; +#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] +pub type NblksR = crate::FieldReader; +#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] +pub type SizeLog2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Number of blocks in this memory"] + #[inline(always)] + pub fn nblks(&self) -> NblksR { + NblksR::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:20 - Log2 size per block"] + #[inline(always)] + pub fn size_log2(&self) -> SizeLog2R { + SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) + } +} +#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem2_glbcfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Mem2GlbcfgSpec; +impl crate::RegisterSpec for Mbc0Mem2GlbcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_mem2_glbcfg::R`](R) reader structure"] +impl crate::Readable for Mbc0Mem2GlbcfgSpec {} +#[doc = "`reset()` method sets MBC0_MEM2_GLBCFG to value 0x000b_0004"] +impl crate::Resettable for Mbc0Mem2GlbcfgSpec { + const RESET_VALUE: u32 = 0x000b_0004; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs new file mode 100644 index 000000000..c4ce138bc --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs @@ -0,0 +1,49 @@ +#[doc = "Register `MBC0_MEM3_GLBCFG` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEM3_GLBCFG` writer"] +pub type W = crate::W; +#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] +pub type NblksR = crate::FieldReader; +#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] +pub type SizeLog2R = crate::FieldReader; +#[doc = "Field `CLRE` reader - Clear Error"] +pub type ClreR = crate::FieldReader; +#[doc = "Field `CLRE` writer - Clear Error"] +pub type ClreW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:9 - Number of blocks in this memory"] + #[inline(always)] + pub fn nblks(&self) -> NblksR { + NblksR::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:20 - Log2 size per block"] + #[inline(always)] + pub fn size_log2(&self) -> SizeLog2R { + SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 30:31 - Clear Error"] + #[inline(always)] + pub fn clre(&self) -> ClreR { + ClreR::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 30:31 - Clear Error"] + #[inline(always)] + pub fn clre(&mut self) -> ClreW { + ClreW::new(self, 30) + } +} +#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem3_glbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_mem3_glbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0Mem3GlbcfgSpec; +impl crate::RegisterSpec for Mbc0Mem3GlbcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_mem3_glbcfg::R`](R) reader structure"] +impl crate::Readable for Mbc0Mem3GlbcfgSpec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_mem3_glbcfg::W`](W) writer structure"] +impl crate::Writable for Mbc0Mem3GlbcfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEM3_GLBCFG to value 0"] +impl crate::Resettable for Mbc0Mem3GlbcfgSpec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs new file mode 100644 index 000000000..8430ca1e6 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs @@ -0,0 +1,779 @@ +#[doc = "Register `MBC0_MEMN_GLBAC0` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC0` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac0Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac0::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac0Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac0::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC0 to value 0x6600"] +impl crate::Resettable for Mbc0MemnGlbac0Spec { + const RESET_VALUE: u32 = 0x6600; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs new file mode 100644 index 000000000..1c90b0421 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs @@ -0,0 +1,842 @@ +#[doc = "Register `MBC0_MEMN_GLBAC1` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC1` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +#[doc = "LOCK\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This register is not locked and can be altered."] + Unlocked = 0, + #[doc = "1: This register is locked and cannot be altered."] + Locked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - LOCK"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Unlocked, + true => Lk::Locked, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == Lk::Unlocked + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == Lk::Locked + } +} +#[doc = "Field `LK` writer - LOCK"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(Lk::Unlocked) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(Lk::Locked) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 31) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac1Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac1::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac1Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac1::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC1 to value 0x8000_6600"] +impl crate::Resettable for Mbc0MemnGlbac1Spec { + const RESET_VALUE: u32 = 0x8000_6600; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs new file mode 100644 index 000000000..1943900c8 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs @@ -0,0 +1,842 @@ +#[doc = "Register `MBC0_MEMN_GLBAC2` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC2` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +#[doc = "LOCK\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This register is not locked and can be altered."] + Unlocked = 0, + #[doc = "1: This register is locked and cannot be altered."] + Locked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - LOCK"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Unlocked, + true => Lk::Locked, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == Lk::Unlocked + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == Lk::Locked + } +} +#[doc = "Field `LK` writer - LOCK"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(Lk::Unlocked) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(Lk::Locked) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 31) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac2Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac2::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac2Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac2::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC2 to value 0x8000_5500"] +impl crate::Resettable for Mbc0MemnGlbac2Spec { + const RESET_VALUE: u32 = 0x8000_5500; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs new file mode 100644 index 000000000..e06076bfa --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs @@ -0,0 +1,842 @@ +#[doc = "Register `MBC0_MEMN_GLBAC3` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC3` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +#[doc = "LOCK\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This register is not locked and can be altered."] + Unlocked = 0, + #[doc = "1: This register is locked and cannot be altered."] + Locked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - LOCK"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Unlocked, + true => Lk::Locked, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == Lk::Unlocked + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == Lk::Locked + } +} +#[doc = "Field `LK` writer - LOCK"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(Lk::Unlocked) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(Lk::Locked) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 31) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac3Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac3::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac3Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac3::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC3 to value 0x8000_4400"] +impl crate::Resettable for Mbc0MemnGlbac3Spec { + const RESET_VALUE: u32 = 0x8000_4400; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs new file mode 100644 index 000000000..7c8e773ed --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs @@ -0,0 +1,842 @@ +#[doc = "Register `MBC0_MEMN_GLBAC4` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC4` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +#[doc = "LOCK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This register is not locked and can be altered."] + Unlocked = 0, + #[doc = "1: This register is locked and cannot be altered."] + Locked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - LOCK"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Unlocked, + true => Lk::Locked, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == Lk::Unlocked + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == Lk::Locked + } +} +#[doc = "Field `LK` writer - LOCK"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(Lk::Unlocked) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(Lk::Locked) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 31) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac4Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac4::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac4Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac4::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC4 to value 0x5500"] +impl crate::Resettable for Mbc0MemnGlbac4Spec { + const RESET_VALUE: u32 = 0x5500; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs new file mode 100644 index 000000000..9cf186a8b --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs @@ -0,0 +1,842 @@ +#[doc = "Register `MBC0_MEMN_GLBAC5` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC5` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +#[doc = "LOCK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This register is not locked and can be altered."] + Unlocked = 0, + #[doc = "1: This register is locked and cannot be altered."] + Locked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - LOCK"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Unlocked, + true => Lk::Locked, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == Lk::Unlocked + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == Lk::Locked + } +} +#[doc = "Field `LK` writer - LOCK"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(Lk::Unlocked) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(Lk::Locked) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 31) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac5Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac5::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac5Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac5::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC5 to value 0x1100"] +impl crate::Resettable for Mbc0MemnGlbac5Spec { + const RESET_VALUE: u32 = 0x1100; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs new file mode 100644 index 000000000..a06e436a9 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs @@ -0,0 +1,842 @@ +#[doc = "Register `MBC0_MEMN_GLBAC6` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC6` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +#[doc = "LOCK\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This register is not locked and can be altered."] + Unlocked = 0, + #[doc = "1: This register is locked and cannot be altered."] + Locked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - LOCK"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Unlocked, + true => Lk::Locked, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == Lk::Unlocked + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == Lk::Locked + } +} +#[doc = "Field `LK` writer - LOCK"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(Lk::Unlocked) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(Lk::Locked) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 31) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac6Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac6::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac6Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac6::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC6 to value 0x8000_1100"] +impl crate::Resettable for Mbc0MemnGlbac6Spec { + const RESET_VALUE: u32 = 0x8000_1100; +} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs new file mode 100644 index 000000000..7378d4533 --- /dev/null +++ b/mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs @@ -0,0 +1,842 @@ +#[doc = "Register `MBC0_MEMN_GLBAC7` reader"] +pub type R = crate::R; +#[doc = "Register `MBC0_MEMN_GLBAC7` writer"] +pub type W = crate::W; +#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nux { + #[doc = "0: Execute access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUX` reader - NonsecureUser Execute"] +pub type NuxR = crate::BitReader; +impl NuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nux { + match self.bits { + false => Nux::Notallowed, + true => Nux::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nux::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nux::Allowed + } +} +#[doc = "Field `NUX` writer - NonsecureUser Execute"] +pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; +impl<'a, REG> NuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nux::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nux::Allowed) + } +} +#[doc = "NonsecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nuw { + #[doc = "0: Write access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nuw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUW` reader - NonsecureUser Write"] +pub type NuwR = crate::BitReader; +impl NuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nuw { + match self.bits { + false => Nuw::Notallowed, + true => Nuw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nuw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nuw::Allowed + } +} +#[doc = "Field `NUW` writer - NonsecureUser Write"] +pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; +impl<'a, REG> NuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nuw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nuw::Allowed) + } +} +#[doc = "NonsecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nur { + #[doc = "0: Read access is not allowed in Nonsecure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NUR` reader - NonsecureUser Read"] +pub type NurR = crate::BitReader; +impl NurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nur { + match self.bits { + false => Nur::Notallowed, + true => Nur::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Nur::Notallowed + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Nur::Allowed + } +} +#[doc = "Field `NUR` writer - NonsecureUser Read"] +pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; +impl<'a, REG> NurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Nur::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Nur::Allowed) + } +} +#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npx { + #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPX` reader - NonsecurePriv Execute"] +pub type NpxR = crate::BitReader; +impl NpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npx { + match self.bits { + false => Npx::Notallowed, + true => Npx::Allowed, + } + } + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npx::Notallowed + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npx::Allowed + } +} +#[doc = "Field `NPX` writer - NonsecurePriv Execute"] +pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; +impl<'a, REG> NpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npx::Notallowed) + } + #[doc = "Execute access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npx::Allowed) + } +} +#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npw { + #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPW` reader - NonsecurePriv Write"] +pub type NpwR = crate::BitReader; +impl NpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npw { + match self.bits { + false => Npw::Notallowed, + true => Npw::Allowed, + } + } + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npw::Notallowed + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npw::Allowed + } +} +#[doc = "Field `NPW` writer - NonsecurePriv Write"] +pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; +impl<'a, REG> NpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npw::Notallowed) + } + #[doc = "Write access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npw::Allowed) + } +} +#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Npr { + #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Npr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NPR` reader - NonsecurePriv Read"] +pub type NprR = crate::BitReader; +impl NprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Npr { + match self.bits { + false => Npr::Notallowed, + true => Npr::Allowed, + } + } + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Npr::Notallowed + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Npr::Allowed + } +} +#[doc = "Field `NPR` writer - NonsecurePriv Read"] +pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; +impl<'a, REG> NprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Npr::Notallowed) + } + #[doc = "Read access is allowed in Nonsecure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Npr::Allowed) + } +} +#[doc = "SecureUser Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sux { + #[doc = "0: Execute access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sux) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUX` reader - SecureUser Execute"] +pub type SuxR = crate::BitReader; +impl SuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sux { + match self.bits { + false => Sux::Notallowed, + true => Sux::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sux::Notallowed + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sux::Allowed + } +} +#[doc = "Field `SUX` writer - SecureUser Execute"] +pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; +impl<'a, REG> SuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sux::Notallowed) + } + #[doc = "Execute access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sux::Allowed) + } +} +#[doc = "SecureUser Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Suw { + #[doc = "0: Write access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Suw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUW` reader - SecureUser Write"] +pub type SuwR = crate::BitReader; +impl SuwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Suw { + match self.bits { + false => Suw::Notallowed, + true => Suw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Suw::Notallowed + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Suw::Allowed + } +} +#[doc = "Field `SUW` writer - SecureUser Write"] +pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; +impl<'a, REG> SuwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Suw::Notallowed) + } + #[doc = "Write access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Suw::Allowed) + } +} +#[doc = "SecureUser Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sur { + #[doc = "0: Read access is not allowed in Secure User mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure User mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sur) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUR` reader - SecureUser Read"] +pub type SurR = crate::BitReader; +impl SurR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sur { + match self.bits { + false => Sur::Notallowed, + true => Sur::Allowed, + } + } + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Sur::Notallowed + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Sur::Allowed + } +} +#[doc = "Field `SUR` writer - SecureUser Read"] +pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; +impl<'a, REG> SurW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure User mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Sur::Notallowed) + } + #[doc = "Read access is allowed in Secure User mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Sur::Allowed) + } +} +#[doc = "SecurePriv Execute\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spx { + #[doc = "0: Execute access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Execute access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPX` reader - SecurePriv Execute"] +pub type SpxR = crate::BitReader; +impl SpxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spx { + match self.bits { + false => Spx::Notallowed, + true => Spx::Allowed, + } + } + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spx::Notallowed + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spx::Allowed + } +} +#[doc = "Field `SPX` writer - SecurePriv Execute"] +pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; +impl<'a, REG> SpxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spx::Notallowed) + } + #[doc = "Execute access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spx::Allowed) + } +} +#[doc = "SecurePriv Write\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spw { + #[doc = "0: Write access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Write access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spw) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPW` reader - SecurePriv Write"] +pub type SpwR = crate::BitReader; +impl SpwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spw { + match self.bits { + false => Spw::Notallowed, + true => Spw::Allowed, + } + } + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spw::Notallowed + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spw::Allowed + } +} +#[doc = "Field `SPW` writer - SecurePriv Write"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; +impl<'a, REG> SpwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spw::Notallowed) + } + #[doc = "Write access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spw::Allowed) + } +} +#[doc = "SecurePriv Read\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spr { + #[doc = "0: Read access is not allowed in Secure Privilege mode."] + Notallowed = 0, + #[doc = "1: Read access is allowed in Secure Privilege mode."] + Allowed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPR` reader - SecurePriv Read"] +pub type SprR = crate::BitReader; +impl SprR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spr { + match self.bits { + false => Spr::Notallowed, + true => Spr::Allowed, + } + } + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_notallowed(&self) -> bool { + *self == Spr::Notallowed + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn is_allowed(&self) -> bool { + *self == Spr::Allowed + } +} +#[doc = "Field `SPR` writer - SecurePriv Read"] +pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; +impl<'a, REG> SprW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read access is not allowed in Secure Privilege mode."] + #[inline(always)] + pub fn notallowed(self) -> &'a mut crate::W { + self.variant(Spr::Notallowed) + } + #[doc = "Read access is allowed in Secure Privilege mode."] + #[inline(always)] + pub fn allowed(self) -> &'a mut crate::W { + self.variant(Spr::Allowed) + } +} +#[doc = "LOCK\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This register is not locked and can be altered."] + Unlocked = 0, + #[doc = "1: This register is locked and cannot be altered."] + Locked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - LOCK"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Unlocked, + true => Lk::Locked, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_unlocked(&self) -> bool { + *self == Lk::Unlocked + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == Lk::Locked + } +} +#[doc = "Field `LK` writer - LOCK"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn unlocked(self) -> &'a mut crate::W { + self.variant(Lk::Unlocked) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(Lk::Locked) + } +} +impl R { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&self) -> NuxR { + NuxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&self) -> NuwR { + NuwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&self) -> NurR { + NurR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&self) -> NpxR { + NpxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&self) -> NpwR { + NpwR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&self) -> NprR { + NprR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&self) -> SuxR { + SuxR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&self) -> SuwR { + SuwR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&self) -> SurR { + SurR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&self) -> SpxR { + SpxR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&self) -> SprR { + SprR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NonsecureUser Execute"] + #[inline(always)] + pub fn nux(&mut self) -> NuxW { + NuxW::new(self, 0) + } + #[doc = "Bit 1 - NonsecureUser Write"] + #[inline(always)] + pub fn nuw(&mut self) -> NuwW { + NuwW::new(self, 1) + } + #[doc = "Bit 2 - NonsecureUser Read"] + #[inline(always)] + pub fn nur(&mut self) -> NurW { + NurW::new(self, 2) + } + #[doc = "Bit 4 - NonsecurePriv Execute"] + #[inline(always)] + pub fn npx(&mut self) -> NpxW { + NpxW::new(self, 4) + } + #[doc = "Bit 5 - NonsecurePriv Write"] + #[inline(always)] + pub fn npw(&mut self) -> NpwW { + NpwW::new(self, 5) + } + #[doc = "Bit 6 - NonsecurePriv Read"] + #[inline(always)] + pub fn npr(&mut self) -> NprW { + NprW::new(self, 6) + } + #[doc = "Bit 8 - SecureUser Execute"] + #[inline(always)] + pub fn sux(&mut self) -> SuxW { + SuxW::new(self, 8) + } + #[doc = "Bit 9 - SecureUser Write"] + #[inline(always)] + pub fn suw(&mut self) -> SuwW { + SuwW::new(self, 9) + } + #[doc = "Bit 10 - SecureUser Read"] + #[inline(always)] + pub fn sur(&mut self) -> SurW { + SurW::new(self, 10) + } + #[doc = "Bit 12 - SecurePriv Execute"] + #[inline(always)] + pub fn spx(&mut self) -> SpxW { + SpxW::new(self, 12) + } + #[doc = "Bit 13 - SecurePriv Write"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 13) + } + #[doc = "Bit 14 - SecurePriv Read"] + #[inline(always)] + pub fn spr(&mut self) -> SprW { + SprW::new(self, 14) + } + #[doc = "Bit 31 - LOCK"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 31) + } +} +#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mbc0MemnGlbac7Spec; +impl crate::RegisterSpec for Mbc0MemnGlbac7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mbc0_memn_glbac7::R`](R) reader structure"] +impl crate::Readable for Mbc0MemnGlbac7Spec {} +#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac7::W`](W) writer structure"] +impl crate::Writable for Mbc0MemnGlbac7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MBC0_MEMN_GLBAC7 to value 0x8000_0000"] +impl crate::Resettable for Mbc0MemnGlbac7Spec { + const RESET_VALUE: u32 = 0x8000_0000; +} diff --git a/mcxa276-pac/src/mrcc0.rs b/mcxa276-pac/src/mrcc0.rs new file mode 100644 index 000000000..654a7ffd6 --- /dev/null +++ b/mcxa276-pac/src/mrcc0.rs @@ -0,0 +1,986 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mrcc_glb_rst0: MrccGlbRst0, + mrcc_glb_rst0_set: MrccGlbRst0Set, + mrcc_glb_rst0_clr: MrccGlbRst0Clr, + _reserved3: [u8; 0x04], + mrcc_glb_rst1: MrccGlbRst1, + mrcc_glb_rst1_set: MrccGlbRst1Set, + mrcc_glb_rst1_clr: MrccGlbRst1Clr, + _reserved6: [u8; 0x04], + mrcc_glb_rst2: MrccGlbRst2, + mrcc_glb_rst2_set: MrccGlbRst2Set, + mrcc_glb_rst2_clr: MrccGlbRst2Clr, + _reserved9: [u8; 0x14], + mrcc_glb_cc0: MrccGlbCc0, + mrcc_glb_cc0_set: MrccGlbCc0Set, + mrcc_glb_cc0_clr: MrccGlbCc0Clr, + _reserved12: [u8; 0x04], + mrcc_glb_cc1: MrccGlbCc1, + mrcc_glb_cc1_set: MrccGlbCc1Set, + mrcc_glb_cc1_clr: MrccGlbCc1Clr, + _reserved15: [u8; 0x04], + mrcc_glb_cc2: MrccGlbCc2, + mrcc_glb_cc2_set: MrccGlbCc2Set, + mrcc_glb_cc2_clr: MrccGlbCc2Clr, + _reserved18: [u8; 0x14], + mrcc_glb_acc0: MrccGlbAcc0, + mrcc_glb_acc1: MrccGlbAcc1, + mrcc_glb_acc2: MrccGlbAcc2, + _reserved21: [u8; 0x14], + mrcc_i3c0_fclk_clksel: MrccI3c0FclkClksel, + mrcc_i3c0_fclk_clkdiv: MrccI3c0FclkClkdiv, + mrcc_ctimer0_clksel: MrccCtimer0Clksel, + mrcc_ctimer0_clkdiv: MrccCtimer0Clkdiv, + mrcc_ctimer1_clksel: MrccCtimer1Clksel, + mrcc_ctimer1_clkdiv: MrccCtimer1Clkdiv, + mrcc_ctimer2_clksel: MrccCtimer2Clksel, + mrcc_ctimer2_clkdiv: MrccCtimer2Clkdiv, + mrcc_ctimer3_clksel: MrccCtimer3Clksel, + mrcc_ctimer3_clkdiv: MrccCtimer3Clkdiv, + mrcc_ctimer4_clksel: MrccCtimer4Clksel, + mrcc_ctimer4_clkdiv: MrccCtimer4Clkdiv, + _reserved33: [u8; 0x04], + mrcc_wwdt0_clkdiv: MrccWwdt0Clkdiv, + mrcc_flexio0_clksel: MrccFlexio0Clksel, + mrcc_flexio0_clkdiv: MrccFlexio0Clkdiv, + mrcc_lpi2c0_clksel: MrccLpi2c0Clksel, + mrcc_lpi2c0_clkdiv: MrccLpi2c0Clkdiv, + mrcc_lpi2c1_clksel: MrccLpi2c1Clksel, + mrcc_lpi2c1_clkdiv: MrccLpi2c1Clkdiv, + mrcc_lpspi0_clksel: MrccLpspi0Clksel, + mrcc_lpspi0_clkdiv: MrccLpspi0Clkdiv, + mrcc_lpspi1_clksel: MrccLpspi1Clksel, + mrcc_lpspi1_clkdiv: MrccLpspi1Clkdiv, + mrcc_lpuart0_clksel: MrccLpuart0Clksel, + mrcc_lpuart0_clkdiv: MrccLpuart0Clkdiv, + mrcc_lpuart1_clksel: MrccLpuart1Clksel, + mrcc_lpuart1_clkdiv: MrccLpuart1Clkdiv, + mrcc_lpuart2_clksel: MrccLpuart2Clksel, + mrcc_lpuart2_clkdiv: MrccLpuart2Clkdiv, + mrcc_lpuart3_clksel: MrccLpuart3Clksel, + mrcc_lpuart3_clkdiv: MrccLpuart3Clkdiv, + mrcc_lpuart4_clksel: MrccLpuart4Clksel, + mrcc_lpuart4_clkdiv: MrccLpuart4Clkdiv, + mrcc_usb0_clksel: MrccUsb0Clksel, + mrcc_usb0_clkdiv: MrccUsb0Clkdiv, + mrcc_lptmr0_clksel: MrccLptmr0Clksel, + mrcc_lptmr0_clkdiv: MrccLptmr0Clkdiv, + mrcc_ostimer0_clksel: MrccOstimer0Clksel, + _reserved59: [u8; 0x04], + mrcc_adc_clksel: MrccAdcClksel, + mrcc_adc_clkdiv: MrccAdcClkdiv, + _reserved61: [u8; 0x04], + mrcc_cmp0_func_clkdiv: MrccCmp0FuncClkdiv, + mrcc_cmp0_rr_clksel: MrccCmp0RrClksel, + mrcc_cmp0_rr_clkdiv: MrccCmp0RrClkdiv, + _reserved64: [u8; 0x04], + mrcc_cmp1_func_clkdiv: MrccCmp1FuncClkdiv, + mrcc_cmp1_rr_clksel: MrccCmp1RrClksel, + mrcc_cmp1_rr_clkdiv: MrccCmp1RrClkdiv, + _reserved67: [u8; 0x04], + mrcc_cmp2_func_clkdiv: MrccCmp2FuncClkdiv, + mrcc_cmp2_rr_clksel: MrccCmp2RrClksel, + mrcc_cmp2_rr_clkdiv: MrccCmp2RrClkdiv, + mrcc_dac0_clksel: MrccDac0Clksel, + mrcc_dac0_clkdiv: MrccDac0Clkdiv, + mrcc_flexcan0_clksel: MrccFlexcan0Clksel, + mrcc_flexcan0_clkdiv: MrccFlexcan0Clkdiv, + mrcc_flexcan1_clksel: MrccFlexcan1Clksel, + mrcc_flexcan1_clkdiv: MrccFlexcan1Clkdiv, + mrcc_lpi2c2_clksel: MrccLpi2c2Clksel, + mrcc_lpi2c2_clkdiv: MrccLpi2c2Clkdiv, + mrcc_lpi2c3_clksel: MrccLpi2c3Clksel, + mrcc_lpi2c3_clkdiv: MrccLpi2c3Clkdiv, + mrcc_lpuart5_clksel: MrccLpuart5Clksel, + mrcc_lpuart5_clkdiv: MrccLpuart5Clkdiv, + mrcc_dbg_trace_clksel: MrccDbgTraceClksel, + mrcc_dbg_trace_clkdiv: MrccDbgTraceClkdiv, + mrcc_clkout_clksel: MrccClkoutClksel, + mrcc_clkout_clkdiv: MrccClkoutClkdiv, + mrcc_systick_clksel: MrccSystickClksel, + mrcc_systick_clkdiv: MrccSystickClkdiv, +} +impl RegisterBlock { + #[doc = "0x00 - Peripheral Reset Control 0"] + #[inline(always)] + pub const fn mrcc_glb_rst0(&self) -> &MrccGlbRst0 { + &self.mrcc_glb_rst0 + } + #[doc = "0x04 - Peripheral Reset Control Set 0"] + #[inline(always)] + pub const fn mrcc_glb_rst0_set(&self) -> &MrccGlbRst0Set { + &self.mrcc_glb_rst0_set + } + #[doc = "0x08 - Peripheral Reset Control Clear 0"] + #[inline(always)] + pub const fn mrcc_glb_rst0_clr(&self) -> &MrccGlbRst0Clr { + &self.mrcc_glb_rst0_clr + } + #[doc = "0x10 - Peripheral Reset Control 1"] + #[inline(always)] + pub const fn mrcc_glb_rst1(&self) -> &MrccGlbRst1 { + &self.mrcc_glb_rst1 + } + #[doc = "0x14 - Peripheral Reset Control Set 1"] + #[inline(always)] + pub const fn mrcc_glb_rst1_set(&self) -> &MrccGlbRst1Set { + &self.mrcc_glb_rst1_set + } + #[doc = "0x18 - Peripheral Reset Control Clear 1"] + #[inline(always)] + pub const fn mrcc_glb_rst1_clr(&self) -> &MrccGlbRst1Clr { + &self.mrcc_glb_rst1_clr + } + #[doc = "0x20 - Peripheral Reset Control 2"] + #[inline(always)] + pub const fn mrcc_glb_rst2(&self) -> &MrccGlbRst2 { + &self.mrcc_glb_rst2 + } + #[doc = "0x24 - Peripheral Reset Control Set 2"] + #[inline(always)] + pub const fn mrcc_glb_rst2_set(&self) -> &MrccGlbRst2Set { + &self.mrcc_glb_rst2_set + } + #[doc = "0x28 - Peripheral Reset Control Clear 2"] + #[inline(always)] + pub const fn mrcc_glb_rst2_clr(&self) -> &MrccGlbRst2Clr { + &self.mrcc_glb_rst2_clr + } + #[doc = "0x40 - AHB Clock Control 0"] + #[inline(always)] + pub const fn mrcc_glb_cc0(&self) -> &MrccGlbCc0 { + &self.mrcc_glb_cc0 + } + #[doc = "0x44 - AHB Clock Control Set 0"] + #[inline(always)] + pub const fn mrcc_glb_cc0_set(&self) -> &MrccGlbCc0Set { + &self.mrcc_glb_cc0_set + } + #[doc = "0x48 - AHB Clock Control Clear 0"] + #[inline(always)] + pub const fn mrcc_glb_cc0_clr(&self) -> &MrccGlbCc0Clr { + &self.mrcc_glb_cc0_clr + } + #[doc = "0x50 - AHB Clock Control 1"] + #[inline(always)] + pub const fn mrcc_glb_cc1(&self) -> &MrccGlbCc1 { + &self.mrcc_glb_cc1 + } + #[doc = "0x54 - AHB Clock Control Set 1"] + #[inline(always)] + pub const fn mrcc_glb_cc1_set(&self) -> &MrccGlbCc1Set { + &self.mrcc_glb_cc1_set + } + #[doc = "0x58 - AHB Clock Control Clear 1"] + #[inline(always)] + pub const fn mrcc_glb_cc1_clr(&self) -> &MrccGlbCc1Clr { + &self.mrcc_glb_cc1_clr + } + #[doc = "0x60 - AHB Clock Control 2"] + #[inline(always)] + pub const fn mrcc_glb_cc2(&self) -> &MrccGlbCc2 { + &self.mrcc_glb_cc2 + } + #[doc = "0x64 - AHB Clock Control Set 2"] + #[inline(always)] + pub const fn mrcc_glb_cc2_set(&self) -> &MrccGlbCc2Set { + &self.mrcc_glb_cc2_set + } + #[doc = "0x68 - AHB Clock Control Clear 2"] + #[inline(always)] + pub const fn mrcc_glb_cc2_clr(&self) -> &MrccGlbCc2Clr { + &self.mrcc_glb_cc2_clr + } + #[doc = "0x80 - Control Automatic Clock Gating 0"] + #[inline(always)] + pub const fn mrcc_glb_acc0(&self) -> &MrccGlbAcc0 { + &self.mrcc_glb_acc0 + } + #[doc = "0x84 - Control Automatic Clock Gating 1"] + #[inline(always)] + pub const fn mrcc_glb_acc1(&self) -> &MrccGlbAcc1 { + &self.mrcc_glb_acc1 + } + #[doc = "0x88 - Control Automatic Clock Gating 2"] + #[inline(always)] + pub const fn mrcc_glb_acc2(&self) -> &MrccGlbAcc2 { + &self.mrcc_glb_acc2 + } + #[doc = "0xa0 - I3C0_FCLK clock selection control"] + #[inline(always)] + pub const fn mrcc_i3c0_fclk_clksel(&self) -> &MrccI3c0FclkClksel { + &self.mrcc_i3c0_fclk_clksel + } + #[doc = "0xa4 - I3C0_FCLK clock divider control"] + #[inline(always)] + pub const fn mrcc_i3c0_fclk_clkdiv(&self) -> &MrccI3c0FclkClkdiv { + &self.mrcc_i3c0_fclk_clkdiv + } + #[doc = "0xa8 - CTIMER0 clock selection control"] + #[inline(always)] + pub const fn mrcc_ctimer0_clksel(&self) -> &MrccCtimer0Clksel { + &self.mrcc_ctimer0_clksel + } + #[doc = "0xac - CTIMER0 clock divider control"] + #[inline(always)] + pub const fn mrcc_ctimer0_clkdiv(&self) -> &MrccCtimer0Clkdiv { + &self.mrcc_ctimer0_clkdiv + } + #[doc = "0xb0 - CTIMER1 clock selection control"] + #[inline(always)] + pub const fn mrcc_ctimer1_clksel(&self) -> &MrccCtimer1Clksel { + &self.mrcc_ctimer1_clksel + } + #[doc = "0xb4 - CTIMER1 clock divider control"] + #[inline(always)] + pub const fn mrcc_ctimer1_clkdiv(&self) -> &MrccCtimer1Clkdiv { + &self.mrcc_ctimer1_clkdiv + } + #[doc = "0xb8 - CTIMER2 clock selection control"] + #[inline(always)] + pub const fn mrcc_ctimer2_clksel(&self) -> &MrccCtimer2Clksel { + &self.mrcc_ctimer2_clksel + } + #[doc = "0xbc - CTIMER2 clock divider control"] + #[inline(always)] + pub const fn mrcc_ctimer2_clkdiv(&self) -> &MrccCtimer2Clkdiv { + &self.mrcc_ctimer2_clkdiv + } + #[doc = "0xc0 - CTIMER3 clock selection control"] + #[inline(always)] + pub const fn mrcc_ctimer3_clksel(&self) -> &MrccCtimer3Clksel { + &self.mrcc_ctimer3_clksel + } + #[doc = "0xc4 - CTIMER3 clock divider control"] + #[inline(always)] + pub const fn mrcc_ctimer3_clkdiv(&self) -> &MrccCtimer3Clkdiv { + &self.mrcc_ctimer3_clkdiv + } + #[doc = "0xc8 - CTIMER4 clock selection control"] + #[inline(always)] + pub const fn mrcc_ctimer4_clksel(&self) -> &MrccCtimer4Clksel { + &self.mrcc_ctimer4_clksel + } + #[doc = "0xcc - CTIMER4 clock divider control"] + #[inline(always)] + pub const fn mrcc_ctimer4_clkdiv(&self) -> &MrccCtimer4Clkdiv { + &self.mrcc_ctimer4_clkdiv + } + #[doc = "0xd4 - WWDT0 clock divider control"] + #[inline(always)] + pub const fn mrcc_wwdt0_clkdiv(&self) -> &MrccWwdt0Clkdiv { + &self.mrcc_wwdt0_clkdiv + } + #[doc = "0xd8 - FLEXIO0 clock selection control"] + #[inline(always)] + pub const fn mrcc_flexio0_clksel(&self) -> &MrccFlexio0Clksel { + &self.mrcc_flexio0_clksel + } + #[doc = "0xdc - FLEXIO0 clock divider control"] + #[inline(always)] + pub const fn mrcc_flexio0_clkdiv(&self) -> &MrccFlexio0Clkdiv { + &self.mrcc_flexio0_clkdiv + } + #[doc = "0xe0 - LPI2C0 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpi2c0_clksel(&self) -> &MrccLpi2c0Clksel { + &self.mrcc_lpi2c0_clksel + } + #[doc = "0xe4 - LPI2C0 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpi2c0_clkdiv(&self) -> &MrccLpi2c0Clkdiv { + &self.mrcc_lpi2c0_clkdiv + } + #[doc = "0xe8 - LPI2C1 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpi2c1_clksel(&self) -> &MrccLpi2c1Clksel { + &self.mrcc_lpi2c1_clksel + } + #[doc = "0xec - LPI2C1 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpi2c1_clkdiv(&self) -> &MrccLpi2c1Clkdiv { + &self.mrcc_lpi2c1_clkdiv + } + #[doc = "0xf0 - LPSPI0 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpspi0_clksel(&self) -> &MrccLpspi0Clksel { + &self.mrcc_lpspi0_clksel + } + #[doc = "0xf4 - LPSPI0 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpspi0_clkdiv(&self) -> &MrccLpspi0Clkdiv { + &self.mrcc_lpspi0_clkdiv + } + #[doc = "0xf8 - LPSPI1 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpspi1_clksel(&self) -> &MrccLpspi1Clksel { + &self.mrcc_lpspi1_clksel + } + #[doc = "0xfc - LPSPI1 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpspi1_clkdiv(&self) -> &MrccLpspi1Clkdiv { + &self.mrcc_lpspi1_clkdiv + } + #[doc = "0x100 - LPUART0 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpuart0_clksel(&self) -> &MrccLpuart0Clksel { + &self.mrcc_lpuart0_clksel + } + #[doc = "0x104 - LPUART0 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpuart0_clkdiv(&self) -> &MrccLpuart0Clkdiv { + &self.mrcc_lpuart0_clkdiv + } + #[doc = "0x108 - LPUART1 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpuart1_clksel(&self) -> &MrccLpuart1Clksel { + &self.mrcc_lpuart1_clksel + } + #[doc = "0x10c - LPUART1 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpuart1_clkdiv(&self) -> &MrccLpuart1Clkdiv { + &self.mrcc_lpuart1_clkdiv + } + #[doc = "0x110 - LPUART2 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpuart2_clksel(&self) -> &MrccLpuart2Clksel { + &self.mrcc_lpuart2_clksel + } + #[doc = "0x114 - LPUART2 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpuart2_clkdiv(&self) -> &MrccLpuart2Clkdiv { + &self.mrcc_lpuart2_clkdiv + } + #[doc = "0x118 - LPUART3 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpuart3_clksel(&self) -> &MrccLpuart3Clksel { + &self.mrcc_lpuart3_clksel + } + #[doc = "0x11c - LPUART3 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpuart3_clkdiv(&self) -> &MrccLpuart3Clkdiv { + &self.mrcc_lpuart3_clkdiv + } + #[doc = "0x120 - LPUART4 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpuart4_clksel(&self) -> &MrccLpuart4Clksel { + &self.mrcc_lpuart4_clksel + } + #[doc = "0x124 - LPUART4 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpuart4_clkdiv(&self) -> &MrccLpuart4Clkdiv { + &self.mrcc_lpuart4_clkdiv + } + #[doc = "0x128 - USB0 clock selection control"] + #[inline(always)] + pub const fn mrcc_usb0_clksel(&self) -> &MrccUsb0Clksel { + &self.mrcc_usb0_clksel + } + #[doc = "0x12c - USB0 clock divider control"] + #[inline(always)] + pub const fn mrcc_usb0_clkdiv(&self) -> &MrccUsb0Clkdiv { + &self.mrcc_usb0_clkdiv + } + #[doc = "0x130 - LPTMR0 clock selection control"] + #[inline(always)] + pub const fn mrcc_lptmr0_clksel(&self) -> &MrccLptmr0Clksel { + &self.mrcc_lptmr0_clksel + } + #[doc = "0x134 - LPTMR0 clock divider control"] + #[inline(always)] + pub const fn mrcc_lptmr0_clkdiv(&self) -> &MrccLptmr0Clkdiv { + &self.mrcc_lptmr0_clkdiv + } + #[doc = "0x138 - OSTIMER0 clock selection control"] + #[inline(always)] + pub const fn mrcc_ostimer0_clksel(&self) -> &MrccOstimer0Clksel { + &self.mrcc_ostimer0_clksel + } + #[doc = "0x140 - ADCx clock selection control"] + #[inline(always)] + pub const fn mrcc_adc_clksel(&self) -> &MrccAdcClksel { + &self.mrcc_adc_clksel + } + #[doc = "0x144 - ADCx clock divider control"] + #[inline(always)] + pub const fn mrcc_adc_clkdiv(&self) -> &MrccAdcClkdiv { + &self.mrcc_adc_clkdiv + } + #[doc = "0x14c - CMP0_FUNC clock divider control"] + #[inline(always)] + pub const fn mrcc_cmp0_func_clkdiv(&self) -> &MrccCmp0FuncClkdiv { + &self.mrcc_cmp0_func_clkdiv + } + #[doc = "0x150 - CMP0_RR clock selection control"] + #[inline(always)] + pub const fn mrcc_cmp0_rr_clksel(&self) -> &MrccCmp0RrClksel { + &self.mrcc_cmp0_rr_clksel + } + #[doc = "0x154 - CMP0_RR clock divider control"] + #[inline(always)] + pub const fn mrcc_cmp0_rr_clkdiv(&self) -> &MrccCmp0RrClkdiv { + &self.mrcc_cmp0_rr_clkdiv + } + #[doc = "0x15c - CMP1_FUNC clock divider control"] + #[inline(always)] + pub const fn mrcc_cmp1_func_clkdiv(&self) -> &MrccCmp1FuncClkdiv { + &self.mrcc_cmp1_func_clkdiv + } + #[doc = "0x160 - CMP1_RR clock selection control"] + #[inline(always)] + pub const fn mrcc_cmp1_rr_clksel(&self) -> &MrccCmp1RrClksel { + &self.mrcc_cmp1_rr_clksel + } + #[doc = "0x164 - CMP1_RR clock divider control"] + #[inline(always)] + pub const fn mrcc_cmp1_rr_clkdiv(&self) -> &MrccCmp1RrClkdiv { + &self.mrcc_cmp1_rr_clkdiv + } + #[doc = "0x16c - CMP2_FUNC clock divider control"] + #[inline(always)] + pub const fn mrcc_cmp2_func_clkdiv(&self) -> &MrccCmp2FuncClkdiv { + &self.mrcc_cmp2_func_clkdiv + } + #[doc = "0x170 - CMP2_RR clock selection control"] + #[inline(always)] + pub const fn mrcc_cmp2_rr_clksel(&self) -> &MrccCmp2RrClksel { + &self.mrcc_cmp2_rr_clksel + } + #[doc = "0x174 - CMP2_RR clock divider control"] + #[inline(always)] + pub const fn mrcc_cmp2_rr_clkdiv(&self) -> &MrccCmp2RrClkdiv { + &self.mrcc_cmp2_rr_clkdiv + } + #[doc = "0x178 - DAC0 clock selection control"] + #[inline(always)] + pub const fn mrcc_dac0_clksel(&self) -> &MrccDac0Clksel { + &self.mrcc_dac0_clksel + } + #[doc = "0x17c - DAC0 clock divider control"] + #[inline(always)] + pub const fn mrcc_dac0_clkdiv(&self) -> &MrccDac0Clkdiv { + &self.mrcc_dac0_clkdiv + } + #[doc = "0x180 - FLEXCAN0 clock selection control"] + #[inline(always)] + pub const fn mrcc_flexcan0_clksel(&self) -> &MrccFlexcan0Clksel { + &self.mrcc_flexcan0_clksel + } + #[doc = "0x184 - FLEXCAN0 clock divider control"] + #[inline(always)] + pub const fn mrcc_flexcan0_clkdiv(&self) -> &MrccFlexcan0Clkdiv { + &self.mrcc_flexcan0_clkdiv + } + #[doc = "0x188 - FLEXCAN1 clock selection control"] + #[inline(always)] + pub const fn mrcc_flexcan1_clksel(&self) -> &MrccFlexcan1Clksel { + &self.mrcc_flexcan1_clksel + } + #[doc = "0x18c - FLEXCAN1 clock divider control"] + #[inline(always)] + pub const fn mrcc_flexcan1_clkdiv(&self) -> &MrccFlexcan1Clkdiv { + &self.mrcc_flexcan1_clkdiv + } + #[doc = "0x190 - LPI2C2 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpi2c2_clksel(&self) -> &MrccLpi2c2Clksel { + &self.mrcc_lpi2c2_clksel + } + #[doc = "0x194 - LPI2C2 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpi2c2_clkdiv(&self) -> &MrccLpi2c2Clkdiv { + &self.mrcc_lpi2c2_clkdiv + } + #[doc = "0x198 - LPI2C3 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpi2c3_clksel(&self) -> &MrccLpi2c3Clksel { + &self.mrcc_lpi2c3_clksel + } + #[doc = "0x19c - LPI2C3 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpi2c3_clkdiv(&self) -> &MrccLpi2c3Clkdiv { + &self.mrcc_lpi2c3_clkdiv + } + #[doc = "0x1a0 - LPUART5 clock selection control"] + #[inline(always)] + pub const fn mrcc_lpuart5_clksel(&self) -> &MrccLpuart5Clksel { + &self.mrcc_lpuart5_clksel + } + #[doc = "0x1a4 - LPUART5 clock divider control"] + #[inline(always)] + pub const fn mrcc_lpuart5_clkdiv(&self) -> &MrccLpuart5Clkdiv { + &self.mrcc_lpuart5_clkdiv + } + #[doc = "0x1a8 - DBG_TRACE clock selection control"] + #[inline(always)] + pub const fn mrcc_dbg_trace_clksel(&self) -> &MrccDbgTraceClksel { + &self.mrcc_dbg_trace_clksel + } + #[doc = "0x1ac - DBG_TRACE clock divider control"] + #[inline(always)] + pub const fn mrcc_dbg_trace_clkdiv(&self) -> &MrccDbgTraceClkdiv { + &self.mrcc_dbg_trace_clkdiv + } + #[doc = "0x1b0 - CLKOUT clock selection control"] + #[inline(always)] + pub const fn mrcc_clkout_clksel(&self) -> &MrccClkoutClksel { + &self.mrcc_clkout_clksel + } + #[doc = "0x1b4 - CLKOUT clock divider control"] + #[inline(always)] + pub const fn mrcc_clkout_clkdiv(&self) -> &MrccClkoutClkdiv { + &self.mrcc_clkout_clkdiv + } + #[doc = "0x1b8 - SYSTICK clock selection control"] + #[inline(always)] + pub const fn mrcc_systick_clksel(&self) -> &MrccSystickClksel { + &self.mrcc_systick_clksel + } + #[doc = "0x1bc - SYSTICK clock divider control"] + #[inline(always)] + pub const fn mrcc_systick_clkdiv(&self) -> &MrccSystickClkdiv { + &self.mrcc_systick_clkdiv + } +} +#[doc = "MRCC_GLB_RST0 (rw) register accessor: Peripheral Reset Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0`] module"] +#[doc(alias = "MRCC_GLB_RST0")] +pub type MrccGlbRst0 = crate::Reg; +#[doc = "Peripheral Reset Control 0"] +pub mod mrcc_glb_rst0; +#[doc = "MRCC_GLB_RST0_SET (w) register accessor: Peripheral Reset Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0_set`] module"] +#[doc(alias = "MRCC_GLB_RST0_SET")] +pub type MrccGlbRst0Set = crate::Reg; +#[doc = "Peripheral Reset Control Set 0"] +pub mod mrcc_glb_rst0_set; +#[doc = "MRCC_GLB_RST0_CLR (w) register accessor: Peripheral Reset Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0_clr`] module"] +#[doc(alias = "MRCC_GLB_RST0_CLR")] +pub type MrccGlbRst0Clr = crate::Reg; +#[doc = "Peripheral Reset Control Clear 0"] +pub mod mrcc_glb_rst0_clr; +#[doc = "MRCC_GLB_RST1 (rw) register accessor: Peripheral Reset Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1`] module"] +#[doc(alias = "MRCC_GLB_RST1")] +pub type MrccGlbRst1 = crate::Reg; +#[doc = "Peripheral Reset Control 1"] +pub mod mrcc_glb_rst1; +#[doc = "MRCC_GLB_RST1_SET (w) register accessor: Peripheral Reset Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1_set`] module"] +#[doc(alias = "MRCC_GLB_RST1_SET")] +pub type MrccGlbRst1Set = crate::Reg; +#[doc = "Peripheral Reset Control Set 1"] +pub mod mrcc_glb_rst1_set; +#[doc = "MRCC_GLB_RST1_CLR (w) register accessor: Peripheral Reset Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1_clr`] module"] +#[doc(alias = "MRCC_GLB_RST1_CLR")] +pub type MrccGlbRst1Clr = crate::Reg; +#[doc = "Peripheral Reset Control Clear 1"] +pub mod mrcc_glb_rst1_clr; +#[doc = "MRCC_GLB_RST2 (rw) register accessor: Peripheral Reset Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2`] module"] +#[doc(alias = "MRCC_GLB_RST2")] +pub type MrccGlbRst2 = crate::Reg; +#[doc = "Peripheral Reset Control 2"] +pub mod mrcc_glb_rst2; +#[doc = "MRCC_GLB_RST2_SET (w) register accessor: Peripheral Reset Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2_set`] module"] +#[doc(alias = "MRCC_GLB_RST2_SET")] +pub type MrccGlbRst2Set = crate::Reg; +#[doc = "Peripheral Reset Control Set 2"] +pub mod mrcc_glb_rst2_set; +#[doc = "MRCC_GLB_RST2_CLR (w) register accessor: Peripheral Reset Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2_clr`] module"] +#[doc(alias = "MRCC_GLB_RST2_CLR")] +pub type MrccGlbRst2Clr = crate::Reg; +#[doc = "Peripheral Reset Control Clear 2"] +pub mod mrcc_glb_rst2_clr; +#[doc = "MRCC_GLB_CC0 (rw) register accessor: AHB Clock Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0`] module"] +#[doc(alias = "MRCC_GLB_CC0")] +pub type MrccGlbCc0 = crate::Reg; +#[doc = "AHB Clock Control 0"] +pub mod mrcc_glb_cc0; +#[doc = "MRCC_GLB_CC0_SET (w) register accessor: AHB Clock Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0_set`] module"] +#[doc(alias = "MRCC_GLB_CC0_SET")] +pub type MrccGlbCc0Set = crate::Reg; +#[doc = "AHB Clock Control Set 0"] +pub mod mrcc_glb_cc0_set; +#[doc = "MRCC_GLB_CC0_CLR (w) register accessor: AHB Clock Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0_clr`] module"] +#[doc(alias = "MRCC_GLB_CC0_CLR")] +pub type MrccGlbCc0Clr = crate::Reg; +#[doc = "AHB Clock Control Clear 0"] +pub mod mrcc_glb_cc0_clr; +#[doc = "MRCC_GLB_CC1 (rw) register accessor: AHB Clock Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1`] module"] +#[doc(alias = "MRCC_GLB_CC1")] +pub type MrccGlbCc1 = crate::Reg; +#[doc = "AHB Clock Control 1"] +pub mod mrcc_glb_cc1; +#[doc = "MRCC_GLB_CC1_SET (w) register accessor: AHB Clock Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1_set`] module"] +#[doc(alias = "MRCC_GLB_CC1_SET")] +pub type MrccGlbCc1Set = crate::Reg; +#[doc = "AHB Clock Control Set 1"] +pub mod mrcc_glb_cc1_set; +#[doc = "MRCC_GLB_CC1_CLR (w) register accessor: AHB Clock Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1_clr`] module"] +#[doc(alias = "MRCC_GLB_CC1_CLR")] +pub type MrccGlbCc1Clr = crate::Reg; +#[doc = "AHB Clock Control Clear 1"] +pub mod mrcc_glb_cc1_clr; +#[doc = "MRCC_GLB_CC2 (rw) register accessor: AHB Clock Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2`] module"] +#[doc(alias = "MRCC_GLB_CC2")] +pub type MrccGlbCc2 = crate::Reg; +#[doc = "AHB Clock Control 2"] +pub mod mrcc_glb_cc2; +#[doc = "MRCC_GLB_CC2_SET (w) register accessor: AHB Clock Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2_set`] module"] +#[doc(alias = "MRCC_GLB_CC2_SET")] +pub type MrccGlbCc2Set = crate::Reg; +#[doc = "AHB Clock Control Set 2"] +pub mod mrcc_glb_cc2_set; +#[doc = "MRCC_GLB_CC2_CLR (w) register accessor: AHB Clock Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2_clr`] module"] +#[doc(alias = "MRCC_GLB_CC2_CLR")] +pub type MrccGlbCc2Clr = crate::Reg; +#[doc = "AHB Clock Control Clear 2"] +pub mod mrcc_glb_cc2_clr; +#[doc = "MRCC_GLB_ACC0 (rw) register accessor: Control Automatic Clock Gating 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc0`] module"] +#[doc(alias = "MRCC_GLB_ACC0")] +pub type MrccGlbAcc0 = crate::Reg; +#[doc = "Control Automatic Clock Gating 0"] +pub mod mrcc_glb_acc0; +#[doc = "MRCC_GLB_ACC1 (rw) register accessor: Control Automatic Clock Gating 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc1`] module"] +#[doc(alias = "MRCC_GLB_ACC1")] +pub type MrccGlbAcc1 = crate::Reg; +#[doc = "Control Automatic Clock Gating 1"] +pub mod mrcc_glb_acc1; +#[doc = "MRCC_GLB_ACC2 (rw) register accessor: Control Automatic Clock Gating 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc2`] module"] +#[doc(alias = "MRCC_GLB_ACC2")] +pub type MrccGlbAcc2 = crate::Reg; +#[doc = "Control Automatic Clock Gating 2"] +pub mod mrcc_glb_acc2; +#[doc = "MRCC_I3C0_FCLK_CLKSEL (rw) register accessor: I3C0_FCLK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_i3c0_fclk_clksel`] module"] +#[doc(alias = "MRCC_I3C0_FCLK_CLKSEL")] +pub type MrccI3c0FclkClksel = crate::Reg; +#[doc = "I3C0_FCLK clock selection control"] +pub mod mrcc_i3c0_fclk_clksel; +#[doc = "MRCC_I3C0_FCLK_CLKDIV (rw) register accessor: I3C0_FCLK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_i3c0_fclk_clkdiv`] module"] +#[doc(alias = "MRCC_I3C0_FCLK_CLKDIV")] +pub type MrccI3c0FclkClkdiv = crate::Reg; +#[doc = "I3C0_FCLK clock divider control"] +pub mod mrcc_i3c0_fclk_clkdiv; +#[doc = "MRCC_CTIMER0_CLKSEL (rw) register accessor: CTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer0_clksel`] module"] +#[doc(alias = "MRCC_CTIMER0_CLKSEL")] +pub type MrccCtimer0Clksel = crate::Reg; +#[doc = "CTIMER0 clock selection control"] +pub mod mrcc_ctimer0_clksel; +#[doc = "MRCC_CTIMER0_CLKDIV (rw) register accessor: CTIMER0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer0_clkdiv`] module"] +#[doc(alias = "MRCC_CTIMER0_CLKDIV")] +pub type MrccCtimer0Clkdiv = crate::Reg; +#[doc = "CTIMER0 clock divider control"] +pub mod mrcc_ctimer0_clkdiv; +#[doc = "MRCC_CTIMER1_CLKSEL (rw) register accessor: CTIMER1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer1_clksel`] module"] +#[doc(alias = "MRCC_CTIMER1_CLKSEL")] +pub type MrccCtimer1Clksel = crate::Reg; +#[doc = "CTIMER1 clock selection control"] +pub mod mrcc_ctimer1_clksel; +#[doc = "MRCC_CTIMER1_CLKDIV (rw) register accessor: CTIMER1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer1_clkdiv`] module"] +#[doc(alias = "MRCC_CTIMER1_CLKDIV")] +pub type MrccCtimer1Clkdiv = crate::Reg; +#[doc = "CTIMER1 clock divider control"] +pub mod mrcc_ctimer1_clkdiv; +#[doc = "MRCC_CTIMER2_CLKSEL (rw) register accessor: CTIMER2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer2_clksel`] module"] +#[doc(alias = "MRCC_CTIMER2_CLKSEL")] +pub type MrccCtimer2Clksel = crate::Reg; +#[doc = "CTIMER2 clock selection control"] +pub mod mrcc_ctimer2_clksel; +#[doc = "MRCC_CTIMER2_CLKDIV (rw) register accessor: CTIMER2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer2_clkdiv`] module"] +#[doc(alias = "MRCC_CTIMER2_CLKDIV")] +pub type MrccCtimer2Clkdiv = crate::Reg; +#[doc = "CTIMER2 clock divider control"] +pub mod mrcc_ctimer2_clkdiv; +#[doc = "MRCC_CTIMER3_CLKSEL (rw) register accessor: CTIMER3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer3_clksel`] module"] +#[doc(alias = "MRCC_CTIMER3_CLKSEL")] +pub type MrccCtimer3Clksel = crate::Reg; +#[doc = "CTIMER3 clock selection control"] +pub mod mrcc_ctimer3_clksel; +#[doc = "MRCC_CTIMER3_CLKDIV (rw) register accessor: CTIMER3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer3_clkdiv`] module"] +#[doc(alias = "MRCC_CTIMER3_CLKDIV")] +pub type MrccCtimer3Clkdiv = crate::Reg; +#[doc = "CTIMER3 clock divider control"] +pub mod mrcc_ctimer3_clkdiv; +#[doc = "MRCC_CTIMER4_CLKSEL (rw) register accessor: CTIMER4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer4_clksel`] module"] +#[doc(alias = "MRCC_CTIMER4_CLKSEL")] +pub type MrccCtimer4Clksel = crate::Reg; +#[doc = "CTIMER4 clock selection control"] +pub mod mrcc_ctimer4_clksel; +#[doc = "MRCC_CTIMER4_CLKDIV (rw) register accessor: CTIMER4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer4_clkdiv`] module"] +#[doc(alias = "MRCC_CTIMER4_CLKDIV")] +pub type MrccCtimer4Clkdiv = crate::Reg; +#[doc = "CTIMER4 clock divider control"] +pub mod mrcc_ctimer4_clkdiv; +#[doc = "MRCC_WWDT0_CLKDIV (rw) register accessor: WWDT0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_wwdt0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_wwdt0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_wwdt0_clkdiv`] module"] +#[doc(alias = "MRCC_WWDT0_CLKDIV")] +pub type MrccWwdt0Clkdiv = crate::Reg; +#[doc = "WWDT0 clock divider control"] +pub mod mrcc_wwdt0_clkdiv; +#[doc = "MRCC_FLEXIO0_CLKSEL (rw) register accessor: FLEXIO0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexio0_clksel`] module"] +#[doc(alias = "MRCC_FLEXIO0_CLKSEL")] +pub type MrccFlexio0Clksel = crate::Reg; +#[doc = "FLEXIO0 clock selection control"] +pub mod mrcc_flexio0_clksel; +#[doc = "MRCC_FLEXIO0_CLKDIV (rw) register accessor: FLEXIO0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexio0_clkdiv`] module"] +#[doc(alias = "MRCC_FLEXIO0_CLKDIV")] +pub type MrccFlexio0Clkdiv = crate::Reg; +#[doc = "FLEXIO0 clock divider control"] +pub mod mrcc_flexio0_clkdiv; +#[doc = "MRCC_LPI2C0_CLKSEL (rw) register accessor: LPI2C0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c0_clksel`] module"] +#[doc(alias = "MRCC_LPI2C0_CLKSEL")] +pub type MrccLpi2c0Clksel = crate::Reg; +#[doc = "LPI2C0 clock selection control"] +pub mod mrcc_lpi2c0_clksel; +#[doc = "MRCC_LPI2C0_CLKDIV (rw) register accessor: LPI2C0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c0_clkdiv`] module"] +#[doc(alias = "MRCC_LPI2C0_CLKDIV")] +pub type MrccLpi2c0Clkdiv = crate::Reg; +#[doc = "LPI2C0 clock divider control"] +pub mod mrcc_lpi2c0_clkdiv; +#[doc = "MRCC_LPI2C1_CLKSEL (rw) register accessor: LPI2C1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c1_clksel`] module"] +#[doc(alias = "MRCC_LPI2C1_CLKSEL")] +pub type MrccLpi2c1Clksel = crate::Reg; +#[doc = "LPI2C1 clock selection control"] +pub mod mrcc_lpi2c1_clksel; +#[doc = "MRCC_LPI2C1_CLKDIV (rw) register accessor: LPI2C1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c1_clkdiv`] module"] +#[doc(alias = "MRCC_LPI2C1_CLKDIV")] +pub type MrccLpi2c1Clkdiv = crate::Reg; +#[doc = "LPI2C1 clock divider control"] +pub mod mrcc_lpi2c1_clkdiv; +#[doc = "MRCC_LPSPI0_CLKSEL (rw) register accessor: LPSPI0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi0_clksel`] module"] +#[doc(alias = "MRCC_LPSPI0_CLKSEL")] +pub type MrccLpspi0Clksel = crate::Reg; +#[doc = "LPSPI0 clock selection control"] +pub mod mrcc_lpspi0_clksel; +#[doc = "MRCC_LPSPI0_CLKDIV (rw) register accessor: LPSPI0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi0_clkdiv`] module"] +#[doc(alias = "MRCC_LPSPI0_CLKDIV")] +pub type MrccLpspi0Clkdiv = crate::Reg; +#[doc = "LPSPI0 clock divider control"] +pub mod mrcc_lpspi0_clkdiv; +#[doc = "MRCC_LPSPI1_CLKSEL (rw) register accessor: LPSPI1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi1_clksel`] module"] +#[doc(alias = "MRCC_LPSPI1_CLKSEL")] +pub type MrccLpspi1Clksel = crate::Reg; +#[doc = "LPSPI1 clock selection control"] +pub mod mrcc_lpspi1_clksel; +#[doc = "MRCC_LPSPI1_CLKDIV (rw) register accessor: LPSPI1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi1_clkdiv`] module"] +#[doc(alias = "MRCC_LPSPI1_CLKDIV")] +pub type MrccLpspi1Clkdiv = crate::Reg; +#[doc = "LPSPI1 clock divider control"] +pub mod mrcc_lpspi1_clkdiv; +#[doc = "MRCC_LPUART0_CLKSEL (rw) register accessor: LPUART0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart0_clksel`] module"] +#[doc(alias = "MRCC_LPUART0_CLKSEL")] +pub type MrccLpuart0Clksel = crate::Reg; +#[doc = "LPUART0 clock selection control"] +pub mod mrcc_lpuart0_clksel; +#[doc = "MRCC_LPUART0_CLKDIV (rw) register accessor: LPUART0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart0_clkdiv`] module"] +#[doc(alias = "MRCC_LPUART0_CLKDIV")] +pub type MrccLpuart0Clkdiv = crate::Reg; +#[doc = "LPUART0 clock divider control"] +pub mod mrcc_lpuart0_clkdiv; +#[doc = "MRCC_LPUART1_CLKSEL (rw) register accessor: LPUART1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart1_clksel`] module"] +#[doc(alias = "MRCC_LPUART1_CLKSEL")] +pub type MrccLpuart1Clksel = crate::Reg; +#[doc = "LPUART1 clock selection control"] +pub mod mrcc_lpuart1_clksel; +#[doc = "MRCC_LPUART1_CLKDIV (rw) register accessor: LPUART1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart1_clkdiv`] module"] +#[doc(alias = "MRCC_LPUART1_CLKDIV")] +pub type MrccLpuart1Clkdiv = crate::Reg; +#[doc = "LPUART1 clock divider control"] +pub mod mrcc_lpuart1_clkdiv; +#[doc = "MRCC_LPUART2_CLKSEL (rw) register accessor: LPUART2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart2_clksel`] module"] +#[doc(alias = "MRCC_LPUART2_CLKSEL")] +pub type MrccLpuart2Clksel = crate::Reg; +#[doc = "LPUART2 clock selection control"] +pub mod mrcc_lpuart2_clksel; +#[doc = "MRCC_LPUART2_CLKDIV (rw) register accessor: LPUART2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart2_clkdiv`] module"] +#[doc(alias = "MRCC_LPUART2_CLKDIV")] +pub type MrccLpuart2Clkdiv = crate::Reg; +#[doc = "LPUART2 clock divider control"] +pub mod mrcc_lpuart2_clkdiv; +#[doc = "MRCC_LPUART3_CLKSEL (rw) register accessor: LPUART3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart3_clksel`] module"] +#[doc(alias = "MRCC_LPUART3_CLKSEL")] +pub type MrccLpuart3Clksel = crate::Reg; +#[doc = "LPUART3 clock selection control"] +pub mod mrcc_lpuart3_clksel; +#[doc = "MRCC_LPUART3_CLKDIV (rw) register accessor: LPUART3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart3_clkdiv`] module"] +#[doc(alias = "MRCC_LPUART3_CLKDIV")] +pub type MrccLpuart3Clkdiv = crate::Reg; +#[doc = "LPUART3 clock divider control"] +pub mod mrcc_lpuart3_clkdiv; +#[doc = "MRCC_LPUART4_CLKSEL (rw) register accessor: LPUART4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart4_clksel`] module"] +#[doc(alias = "MRCC_LPUART4_CLKSEL")] +pub type MrccLpuart4Clksel = crate::Reg; +#[doc = "LPUART4 clock selection control"] +pub mod mrcc_lpuart4_clksel; +#[doc = "MRCC_LPUART4_CLKDIV (rw) register accessor: LPUART4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart4_clkdiv`] module"] +#[doc(alias = "MRCC_LPUART4_CLKDIV")] +pub type MrccLpuart4Clkdiv = crate::Reg; +#[doc = "LPUART4 clock divider control"] +pub mod mrcc_lpuart4_clkdiv; +#[doc = "MRCC_USB0_CLKSEL (rw) register accessor: USB0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_usb0_clksel`] module"] +#[doc(alias = "MRCC_USB0_CLKSEL")] +pub type MrccUsb0Clksel = crate::Reg; +#[doc = "USB0 clock selection control"] +pub mod mrcc_usb0_clksel; +#[doc = "MRCC_USB0_CLKDIV (rw) register accessor: USB0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_usb0_clkdiv`] module"] +#[doc(alias = "MRCC_USB0_CLKDIV")] +pub type MrccUsb0Clkdiv = crate::Reg; +#[doc = "USB0 clock divider control"] +pub mod mrcc_usb0_clkdiv; +#[doc = "MRCC_LPTMR0_CLKSEL (rw) register accessor: LPTMR0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lptmr0_clksel`] module"] +#[doc(alias = "MRCC_LPTMR0_CLKSEL")] +pub type MrccLptmr0Clksel = crate::Reg; +#[doc = "LPTMR0 clock selection control"] +pub mod mrcc_lptmr0_clksel; +#[doc = "MRCC_LPTMR0_CLKDIV (rw) register accessor: LPTMR0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lptmr0_clkdiv`] module"] +#[doc(alias = "MRCC_LPTMR0_CLKDIV")] +pub type MrccLptmr0Clkdiv = crate::Reg; +#[doc = "LPTMR0 clock divider control"] +pub mod mrcc_lptmr0_clkdiv; +#[doc = "MRCC_OSTIMER0_CLKSEL (rw) register accessor: OSTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ostimer0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ostimer0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ostimer0_clksel`] module"] +#[doc(alias = "MRCC_OSTIMER0_CLKSEL")] +pub type MrccOstimer0Clksel = crate::Reg; +#[doc = "OSTIMER0 clock selection control"] +pub mod mrcc_ostimer0_clksel; +#[doc = "MRCC_ADC_CLKSEL (rw) register accessor: ADCx clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_adc_clksel`] module"] +#[doc(alias = "MRCC_ADC_CLKSEL")] +pub type MrccAdcClksel = crate::Reg; +#[doc = "ADCx clock selection control"] +pub mod mrcc_adc_clksel; +#[doc = "MRCC_ADC_CLKDIV (rw) register accessor: ADCx clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_adc_clkdiv`] module"] +#[doc(alias = "MRCC_ADC_CLKDIV")] +pub type MrccAdcClkdiv = crate::Reg; +#[doc = "ADCx clock divider control"] +pub mod mrcc_adc_clkdiv; +#[doc = "MRCC_CMP0_FUNC_CLKDIV (rw) register accessor: CMP0_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_func_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_func_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_func_clkdiv`] module"] +#[doc(alias = "MRCC_CMP0_FUNC_CLKDIV")] +pub type MrccCmp0FuncClkdiv = crate::Reg; +#[doc = "CMP0_FUNC clock divider control"] +pub mod mrcc_cmp0_func_clkdiv; +#[doc = "MRCC_CMP0_RR_CLKSEL (rw) register accessor: CMP0_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_rr_clksel`] module"] +#[doc(alias = "MRCC_CMP0_RR_CLKSEL")] +pub type MrccCmp0RrClksel = crate::Reg; +#[doc = "CMP0_RR clock selection control"] +pub mod mrcc_cmp0_rr_clksel; +#[doc = "MRCC_CMP0_RR_CLKDIV (rw) register accessor: CMP0_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_rr_clkdiv`] module"] +#[doc(alias = "MRCC_CMP0_RR_CLKDIV")] +pub type MrccCmp0RrClkdiv = crate::Reg; +#[doc = "CMP0_RR clock divider control"] +pub mod mrcc_cmp0_rr_clkdiv; +#[doc = "MRCC_CMP1_FUNC_CLKDIV (rw) register accessor: CMP1_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_func_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_func_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp1_func_clkdiv`] module"] +#[doc(alias = "MRCC_CMP1_FUNC_CLKDIV")] +pub type MrccCmp1FuncClkdiv = crate::Reg; +#[doc = "CMP1_FUNC clock divider control"] +pub mod mrcc_cmp1_func_clkdiv; +#[doc = "MRCC_CMP1_RR_CLKSEL (rw) register accessor: CMP1_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp1_rr_clksel`] module"] +#[doc(alias = "MRCC_CMP1_RR_CLKSEL")] +pub type MrccCmp1RrClksel = crate::Reg; +#[doc = "CMP1_RR clock selection control"] +pub mod mrcc_cmp1_rr_clksel; +#[doc = "MRCC_CMP1_RR_CLKDIV (rw) register accessor: CMP1_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp1_rr_clkdiv`] module"] +#[doc(alias = "MRCC_CMP1_RR_CLKDIV")] +pub type MrccCmp1RrClkdiv = crate::Reg; +#[doc = "CMP1_RR clock divider control"] +pub mod mrcc_cmp1_rr_clkdiv; +#[doc = "MRCC_CMP2_FUNC_CLKDIV (rw) register accessor: CMP2_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_func_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_func_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp2_func_clkdiv`] module"] +#[doc(alias = "MRCC_CMP2_FUNC_CLKDIV")] +pub type MrccCmp2FuncClkdiv = crate::Reg; +#[doc = "CMP2_FUNC clock divider control"] +pub mod mrcc_cmp2_func_clkdiv; +#[doc = "MRCC_CMP2_RR_CLKSEL (rw) register accessor: CMP2_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp2_rr_clksel`] module"] +#[doc(alias = "MRCC_CMP2_RR_CLKSEL")] +pub type MrccCmp2RrClksel = crate::Reg; +#[doc = "CMP2_RR clock selection control"] +pub mod mrcc_cmp2_rr_clksel; +#[doc = "MRCC_CMP2_RR_CLKDIV (rw) register accessor: CMP2_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp2_rr_clkdiv`] module"] +#[doc(alias = "MRCC_CMP2_RR_CLKDIV")] +pub type MrccCmp2RrClkdiv = crate::Reg; +#[doc = "CMP2_RR clock divider control"] +pub mod mrcc_cmp2_rr_clkdiv; +#[doc = "MRCC_DAC0_CLKSEL (rw) register accessor: DAC0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dac0_clksel`] module"] +#[doc(alias = "MRCC_DAC0_CLKSEL")] +pub type MrccDac0Clksel = crate::Reg; +#[doc = "DAC0 clock selection control"] +pub mod mrcc_dac0_clksel; +#[doc = "MRCC_DAC0_CLKDIV (rw) register accessor: DAC0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dac0_clkdiv`] module"] +#[doc(alias = "MRCC_DAC0_CLKDIV")] +pub type MrccDac0Clkdiv = crate::Reg; +#[doc = "DAC0 clock divider control"] +pub mod mrcc_dac0_clkdiv; +#[doc = "MRCC_FLEXCAN0_CLKSEL (rw) register accessor: FLEXCAN0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan0_clksel`] module"] +#[doc(alias = "MRCC_FLEXCAN0_CLKSEL")] +pub type MrccFlexcan0Clksel = crate::Reg; +#[doc = "FLEXCAN0 clock selection control"] +pub mod mrcc_flexcan0_clksel; +#[doc = "MRCC_FLEXCAN0_CLKDIV (rw) register accessor: FLEXCAN0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan0_clkdiv`] module"] +#[doc(alias = "MRCC_FLEXCAN0_CLKDIV")] +pub type MrccFlexcan0Clkdiv = crate::Reg; +#[doc = "FLEXCAN0 clock divider control"] +pub mod mrcc_flexcan0_clkdiv; +#[doc = "MRCC_FLEXCAN1_CLKSEL (rw) register accessor: FLEXCAN1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan1_clksel`] module"] +#[doc(alias = "MRCC_FLEXCAN1_CLKSEL")] +pub type MrccFlexcan1Clksel = crate::Reg; +#[doc = "FLEXCAN1 clock selection control"] +pub mod mrcc_flexcan1_clksel; +#[doc = "MRCC_FLEXCAN1_CLKDIV (rw) register accessor: FLEXCAN1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan1_clkdiv`] module"] +#[doc(alias = "MRCC_FLEXCAN1_CLKDIV")] +pub type MrccFlexcan1Clkdiv = crate::Reg; +#[doc = "FLEXCAN1 clock divider control"] +pub mod mrcc_flexcan1_clkdiv; +#[doc = "MRCC_LPI2C2_CLKSEL (rw) register accessor: LPI2C2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c2_clksel`] module"] +#[doc(alias = "MRCC_LPI2C2_CLKSEL")] +pub type MrccLpi2c2Clksel = crate::Reg; +#[doc = "LPI2C2 clock selection control"] +pub mod mrcc_lpi2c2_clksel; +#[doc = "MRCC_LPI2C2_CLKDIV (rw) register accessor: LPI2C2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c2_clkdiv`] module"] +#[doc(alias = "MRCC_LPI2C2_CLKDIV")] +pub type MrccLpi2c2Clkdiv = crate::Reg; +#[doc = "LPI2C2 clock divider control"] +pub mod mrcc_lpi2c2_clkdiv; +#[doc = "MRCC_LPI2C3_CLKSEL (rw) register accessor: LPI2C3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c3_clksel`] module"] +#[doc(alias = "MRCC_LPI2C3_CLKSEL")] +pub type MrccLpi2c3Clksel = crate::Reg; +#[doc = "LPI2C3 clock selection control"] +pub mod mrcc_lpi2c3_clksel; +#[doc = "MRCC_LPI2C3_CLKDIV (rw) register accessor: LPI2C3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c3_clkdiv`] module"] +#[doc(alias = "MRCC_LPI2C3_CLKDIV")] +pub type MrccLpi2c3Clkdiv = crate::Reg; +#[doc = "LPI2C3 clock divider control"] +pub mod mrcc_lpi2c3_clkdiv; +#[doc = "MRCC_LPUART5_CLKSEL (rw) register accessor: LPUART5 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart5_clksel`] module"] +#[doc(alias = "MRCC_LPUART5_CLKSEL")] +pub type MrccLpuart5Clksel = crate::Reg; +#[doc = "LPUART5 clock selection control"] +pub mod mrcc_lpuart5_clksel; +#[doc = "MRCC_LPUART5_CLKDIV (rw) register accessor: LPUART5 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart5_clkdiv`] module"] +#[doc(alias = "MRCC_LPUART5_CLKDIV")] +pub type MrccLpuart5Clkdiv = crate::Reg; +#[doc = "LPUART5 clock divider control"] +pub mod mrcc_lpuart5_clkdiv; +#[doc = "MRCC_DBG_TRACE_CLKSEL (rw) register accessor: DBG_TRACE clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dbg_trace_clksel`] module"] +#[doc(alias = "MRCC_DBG_TRACE_CLKSEL")] +pub type MrccDbgTraceClksel = crate::Reg; +#[doc = "DBG_TRACE clock selection control"] +pub mod mrcc_dbg_trace_clksel; +#[doc = "MRCC_DBG_TRACE_CLKDIV (rw) register accessor: DBG_TRACE clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dbg_trace_clkdiv`] module"] +#[doc(alias = "MRCC_DBG_TRACE_CLKDIV")] +pub type MrccDbgTraceClkdiv = crate::Reg; +#[doc = "DBG_TRACE clock divider control"] +pub mod mrcc_dbg_trace_clkdiv; +#[doc = "MRCC_CLKOUT_CLKSEL (rw) register accessor: CLKOUT clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_clkout_clksel`] module"] +#[doc(alias = "MRCC_CLKOUT_CLKSEL")] +pub type MrccClkoutClksel = crate::Reg; +#[doc = "CLKOUT clock selection control"] +pub mod mrcc_clkout_clksel; +#[doc = "MRCC_CLKOUT_CLKDIV (rw) register accessor: CLKOUT clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_clkout_clkdiv`] module"] +#[doc(alias = "MRCC_CLKOUT_CLKDIV")] +pub type MrccClkoutClkdiv = crate::Reg; +#[doc = "CLKOUT clock divider control"] +pub mod mrcc_clkout_clkdiv; +#[doc = "MRCC_SYSTICK_CLKSEL (rw) register accessor: SYSTICK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_systick_clksel`] module"] +#[doc(alias = "MRCC_SYSTICK_CLKSEL")] +pub type MrccSystickClksel = crate::Reg; +#[doc = "SYSTICK clock selection control"] +pub mod mrcc_systick_clksel; +#[doc = "MRCC_SYSTICK_CLKDIV (rw) register accessor: SYSTICK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_systick_clkdiv`] module"] +#[doc(alias = "MRCC_SYSTICK_CLKDIV")] +pub type MrccSystickClkdiv = crate::Reg; +#[doc = "SYSTICK clock divider control"] +pub mod mrcc_systick_clkdiv; diff --git a/mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs new file mode 100644 index 000000000..f32f236e8 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_ADC_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_ADC_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "ADCx clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccAdcClkdivSpec; +impl crate::RegisterSpec for MrccAdcClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_adc_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccAdcClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_adc_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccAdcClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_ADC_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccAdcClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs new file mode 100644 index 000000000..de251dec0 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_ADC_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_ADC_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "1: FRO_HF_GATED"] + ClkrootFunc1 = 1, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 1 => Some(Mux::ClkrootFunc1), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_func_1(&self) -> bool { + *self == Mux::ClkrootFunc1 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_func_1(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc1) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "ADCx clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccAdcClkselSpec; +impl crate::RegisterSpec for MrccAdcClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_adc_clksel::R`](R) reader structure"] +impl crate::Readable for MrccAdcClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_adc_clksel::W`](W) writer structure"] +impl crate::Writable for MrccAdcClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_ADC_CLKSEL to value 0x07"] +impl crate::Resettable for MrccAdcClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs new file mode 100644 index 000000000..d1e62fe47 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CLKOUT_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CLKOUT_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CLKOUT clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccClkoutClkdivSpec; +impl crate::RegisterSpec for MrccClkoutClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_clkout_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccClkoutClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_clkout_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccClkoutClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CLKOUT_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccClkoutClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs new file mode 100644 index 000000000..fcd600b66 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_CLKOUT_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CLKOUT_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_12M"] + Clkroot12m = 0, + #[doc = "1: FRO_HF_DIV"] + ClkrootFircDiv = 1, + #[doc = "2: CLK_IN"] + ClkrootSosc = 2, + #[doc = "3: CLK_16K"] + Clkroot16k = 3, + #[doc = "5: PLL1_CLK"] + ClkrootSpll = 5, + #[doc = "6: SLOW_CLK"] + ClkrootSlow = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Clkroot12m), + 1 => Some(Mux::ClkrootFircDiv), + 2 => Some(Mux::ClkrootSosc), + 3 => Some(Mux::Clkroot16k), + 5 => Some(Mux::ClkrootSpll), + 6 => Some(Mux::ClkrootSlow), + _ => None, + } + } + #[doc = "FRO_12M"] + #[inline(always)] + pub fn is_clkroot_12m(&self) -> bool { + *self == Mux::Clkroot12m + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_firc_div(&self) -> bool { + *self == Mux::ClkrootFircDiv + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_sosc(&self) -> bool { + *self == Mux::ClkrootSosc + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_16k(&self) -> bool { + *self == Mux::Clkroot16k + } + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn is_clkroot_spll(&self) -> bool { + *self == Mux::ClkrootSpll + } + #[doc = "SLOW_CLK"] + #[inline(always)] + pub fn is_clkroot_slow(&self) -> bool { + *self == Mux::ClkrootSlow + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_12M"] + #[inline(always)] + pub fn clkroot_12m(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot12m) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_firc_div(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFircDiv) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_sosc(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSosc) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_16k(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot16k) + } + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn clkroot_spll(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSpll) + } + #[doc = "SLOW_CLK"] + #[inline(always)] + pub fn clkroot_slow(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSlow) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CLKOUT clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccClkoutClkselSpec; +impl crate::RegisterSpec for MrccClkoutClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_clkout_clksel::R`](R) reader structure"] +impl crate::Readable for MrccClkoutClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_clkout_clksel::W`](W) writer structure"] +impl crate::Writable for MrccClkoutClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CLKOUT_CLKSEL to value 0x07"] +impl crate::Resettable for MrccClkoutClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs new file mode 100644 index 000000000..ed5fd5017 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CMP0_FUNC_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP0_FUNC_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CMP0_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_func_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_func_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp0FuncClkdivSpec; +impl crate::RegisterSpec for MrccCmp0FuncClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp0_func_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCmp0FuncClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp0_func_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCmp0FuncClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP0_FUNC_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCmp0FuncClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs new file mode 100644 index 000000000..d53e62ceb --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CMP0_RR_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP0_RR_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CMP0_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp0RrClkdivSpec; +impl crate::RegisterSpec for MrccCmp0RrClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp0_rr_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCmp0RrClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp0_rr_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCmp0RrClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP0_RR_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCmp0RrClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs new file mode 100644 index 000000000..13e3cf07e --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_CMP0_RR_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP0_RR_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CMP0_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp0RrClkselSpec; +impl crate::RegisterSpec for MrccCmp0RrClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp0_rr_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCmp0RrClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp0_rr_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCmp0RrClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP0_RR_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCmp0RrClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs new file mode 100644 index 000000000..e4d83dd8a --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CMP1_FUNC_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP1_FUNC_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CMP1_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_func_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_func_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp1FuncClkdivSpec; +impl crate::RegisterSpec for MrccCmp1FuncClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp1_func_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCmp1FuncClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp1_func_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCmp1FuncClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP1_FUNC_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCmp1FuncClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs new file mode 100644 index 000000000..2d505c912 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CMP1_RR_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP1_RR_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CMP1_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp1RrClkdivSpec; +impl crate::RegisterSpec for MrccCmp1RrClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp1_rr_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCmp1RrClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp1_rr_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCmp1RrClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP1_RR_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCmp1RrClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs new file mode 100644 index 000000000..e9d4863bf --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_CMP1_RR_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP1_RR_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CMP1_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp1RrClkselSpec; +impl crate::RegisterSpec for MrccCmp1RrClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp1_rr_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCmp1RrClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp1_rr_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCmp1RrClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP1_RR_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCmp1RrClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs new file mode 100644 index 000000000..867fb6e21 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CMP2_FUNC_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP2_FUNC_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CMP2_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_func_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_func_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp2FuncClkdivSpec; +impl crate::RegisterSpec for MrccCmp2FuncClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp2_func_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCmp2FuncClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp2_func_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCmp2FuncClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP2_FUNC_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCmp2FuncClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs new file mode 100644 index 000000000..3565ec288 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CMP2_RR_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP2_RR_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CMP2_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp2RrClkdivSpec; +impl crate::RegisterSpec for MrccCmp2RrClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp2_rr_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCmp2RrClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp2_rr_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCmp2RrClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP2_RR_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCmp2RrClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs new file mode 100644 index 000000000..7c383f9bf --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_CMP2_RR_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CMP2_RR_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CMP2_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCmp2RrClkselSpec; +impl crate::RegisterSpec for MrccCmp2RrClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_cmp2_rr_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCmp2RrClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_cmp2_rr_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCmp2RrClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CMP2_RR_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCmp2RrClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs new file mode 100644 index 000000000..f724e993c --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CTIMER0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CTIMER0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer0ClkdivSpec; +impl crate::RegisterSpec for MrccCtimer0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCtimer0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCtimer0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCtimer0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs new file mode 100644 index 000000000..6d7422443 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_CTIMER0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "1: FRO_HF_GATED"] + ClkrootFunc1 = 1, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 1 => Some(Mux::ClkrootFunc1), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_func_1(&self) -> bool { + *self == Mux::ClkrootFunc1 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_func_1(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc1) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer0ClkselSpec; +impl crate::RegisterSpec for MrccCtimer0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCtimer0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCtimer0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCtimer0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs new file mode 100644 index 000000000..d39a9161d --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CTIMER1_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER1_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CTIMER1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer1ClkdivSpec; +impl crate::RegisterSpec for MrccCtimer1ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer1_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCtimer1ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer1_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCtimer1ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER1_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCtimer1ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs new file mode 100644 index 000000000..0a27a24fd --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_CTIMER1_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER1_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "1: FRO_HF_GATED"] + ClkrootFunc1 = 1, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 1 => Some(Mux::ClkrootFunc1), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_func_1(&self) -> bool { + *self == Mux::ClkrootFunc1 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_func_1(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc1) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CTIMER1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer1ClkselSpec; +impl crate::RegisterSpec for MrccCtimer1ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer1_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCtimer1ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer1_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCtimer1ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER1_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCtimer1ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs new file mode 100644 index 000000000..4776a2584 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CTIMER2_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER2_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CTIMER2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer2ClkdivSpec; +impl crate::RegisterSpec for MrccCtimer2ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer2_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCtimer2ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer2_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCtimer2ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER2_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCtimer2ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs new file mode 100644 index 000000000..2fe5bf7cc --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_CTIMER2_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER2_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "1: FRO_HF_GATED"] + ClkrootFunc1 = 1, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 1 => Some(Mux::ClkrootFunc1), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_func_1(&self) -> bool { + *self == Mux::ClkrootFunc1 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_func_1(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc1) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CTIMER2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer2ClkselSpec; +impl crate::RegisterSpec for MrccCtimer2ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer2_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCtimer2ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer2_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCtimer2ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER2_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCtimer2ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs new file mode 100644 index 000000000..89aedb37f --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CTIMER3_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER3_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CTIMER3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer3ClkdivSpec; +impl crate::RegisterSpec for MrccCtimer3ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer3_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCtimer3ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer3_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCtimer3ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER3_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCtimer3ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs new file mode 100644 index 000000000..7263eb5b0 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_CTIMER3_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER3_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "1: FRO_HF_GATED"] + ClkrootFunc1 = 1, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 1 => Some(Mux::ClkrootFunc1), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_func_1(&self) -> bool { + *self == Mux::ClkrootFunc1 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_func_1(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc1) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CTIMER3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer3ClkselSpec; +impl crate::RegisterSpec for MrccCtimer3ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer3_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCtimer3ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer3_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCtimer3ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER3_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCtimer3ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs new file mode 100644 index 000000000..002dd7c66 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_CTIMER4_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER4_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "CTIMER4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer4ClkdivSpec; +impl crate::RegisterSpec for MrccCtimer4ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer4_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccCtimer4ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer4_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccCtimer4ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER4_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccCtimer4ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs new file mode 100644 index 000000000..88e8597d0 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_CTIMER4_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_CTIMER4_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "1: FRO_HF_GATED"] + ClkrootFunc1 = 1, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 1 => Some(Mux::ClkrootFunc1), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_func_1(&self) -> bool { + *self == Mux::ClkrootFunc1 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_func_1(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc1) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "CTIMER4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccCtimer4ClkselSpec; +impl crate::RegisterSpec for MrccCtimer4ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ctimer4_clksel::R`](R) reader structure"] +impl crate::Readable for MrccCtimer4ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer4_clksel::W`](W) writer structure"] +impl crate::Writable for MrccCtimer4ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_CTIMER4_CLKSEL to value 0x07"] +impl crate::Resettable for MrccCtimer4ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs new file mode 100644 index 000000000..2f8d3aaf2 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_DAC0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_DAC0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "DAC0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccDac0ClkdivSpec; +impl crate::RegisterSpec for MrccDac0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_dac0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccDac0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_dac0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccDac0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_DAC0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccDac0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs new file mode 100644 index 000000000..22b68ce18 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_DAC0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_DAC0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "DAC0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccDac0ClkselSpec; +impl crate::RegisterSpec for MrccDac0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_dac0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccDac0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_dac0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccDac0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_DAC0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccDac0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs new file mode 100644 index 000000000..0865d41c5 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs @@ -0,0 +1,175 @@ +#[doc = "Register `MRCC_DBG_TRACE_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_DBG_TRACE_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "DBG_TRACE clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccDbgTraceClkdivSpec; +impl crate::RegisterSpec for MrccDbgTraceClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_dbg_trace_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccDbgTraceClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_dbg_trace_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccDbgTraceClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_DBG_TRACE_CLKDIV to value 0"] +impl crate::Resettable for MrccDbgTraceClkdivSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs new file mode 100644 index 000000000..1fb3bbd69 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs @@ -0,0 +1,104 @@ +#[doc = "Register `MRCC_DBG_TRACE_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_DBG_TRACE_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: CPU_CLK"] + ClkrootCpu = 0, + #[doc = "1: CLK_1M"] + Clkroot1m = 1, + #[doc = "2: CLK_16K"] + Clkroot16k = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootCpu), + 1 => Some(Mux::Clkroot1m), + 2 => Some(Mux::Clkroot16k), + _ => None, + } + } + #[doc = "CPU_CLK"] + #[inline(always)] + pub fn is_clkroot_cpu(&self) -> bool { + *self == Mux::ClkrootCpu + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_1m(&self) -> bool { + *self == Mux::Clkroot1m + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_16k(&self) -> bool { + *self == Mux::Clkroot16k + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CPU_CLK"] + #[inline(always)] + pub fn clkroot_cpu(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootCpu) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_1m(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot1m) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_16k(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot16k) + } +} +impl R { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "DBG_TRACE clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccDbgTraceClkselSpec; +impl crate::RegisterSpec for MrccDbgTraceClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_dbg_trace_clksel::R`](R) reader structure"] +impl crate::Readable for MrccDbgTraceClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_dbg_trace_clksel::W`](W) writer structure"] +impl crate::Writable for MrccDbgTraceClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_DBG_TRACE_CLKSEL to value 0"] +impl crate::Resettable for MrccDbgTraceClkselSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs new file mode 100644 index 000000000..f431be88d --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_FLEXCAN0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_FLEXCAN0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "FLEXCAN0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccFlexcan0ClkdivSpec; +impl crate::RegisterSpec for MrccFlexcan0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_flexcan0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccFlexcan0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccFlexcan0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_FLEXCAN0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccFlexcan0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs new file mode 100644 index 000000000..ddc11f84b --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs @@ -0,0 +1,119 @@ +#[doc = "Register `MRCC_FLEXCAN0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_FLEXCAN0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "1: FRO_HF_GATED"] + ClkrootFircGated = 1, + #[doc = "2: FRO_HF_DIV"] + ClkrootFircDiv = 2, + #[doc = "3: CLK_IN"] + ClkrootSosc = 3, + #[doc = "6: PLL1_CLK"] + ClkrootSpll = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Mux::ClkrootFircGated), + 2 => Some(Mux::ClkrootFircDiv), + 3 => Some(Mux::ClkrootSosc), + 6 => Some(Mux::ClkrootSpll), + _ => None, + } + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_firc_gated(&self) -> bool { + *self == Mux::ClkrootFircGated + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_firc_div(&self) -> bool { + *self == Mux::ClkrootFircDiv + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_sosc(&self) -> bool { + *self == Mux::ClkrootSosc + } + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn is_clkroot_spll(&self) -> bool { + *self == Mux::ClkrootSpll + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_firc_gated(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFircGated) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_firc_div(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFircDiv) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_sosc(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSosc) + } + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn clkroot_spll(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSpll) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "FLEXCAN0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccFlexcan0ClkselSpec; +impl crate::RegisterSpec for MrccFlexcan0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_flexcan0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccFlexcan0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccFlexcan0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_FLEXCAN0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccFlexcan0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs new file mode 100644 index 000000000..e950f16ef --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_FLEXCAN1_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_FLEXCAN1_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "FLEXCAN1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccFlexcan1ClkdivSpec; +impl crate::RegisterSpec for MrccFlexcan1ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_flexcan1_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccFlexcan1ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan1_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccFlexcan1ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_FLEXCAN1_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccFlexcan1ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs new file mode 100644 index 000000000..328a4f461 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs @@ -0,0 +1,119 @@ +#[doc = "Register `MRCC_FLEXCAN1_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_FLEXCAN1_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "1: FRO_HF_GATED"] + ClkrootFircGated = 1, + #[doc = "2: FRO_HF_DIV"] + ClkrootFircDiv = 2, + #[doc = "3: CLK_IN"] + ClkrootSosc = 3, + #[doc = "6: PLL1_CLK"] + ClkrootSpll = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Mux::ClkrootFircGated), + 2 => Some(Mux::ClkrootFircDiv), + 3 => Some(Mux::ClkrootSosc), + 6 => Some(Mux::ClkrootSpll), + _ => None, + } + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_firc_gated(&self) -> bool { + *self == Mux::ClkrootFircGated + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_firc_div(&self) -> bool { + *self == Mux::ClkrootFircDiv + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_sosc(&self) -> bool { + *self == Mux::ClkrootSosc + } + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn is_clkroot_spll(&self) -> bool { + *self == Mux::ClkrootSpll + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_firc_gated(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFircGated) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_firc_div(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFircDiv) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_sosc(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSosc) + } + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn clkroot_spll(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSpll) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "FLEXCAN1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccFlexcan1ClkselSpec; +impl crate::RegisterSpec for MrccFlexcan1ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_flexcan1_clksel::R`](R) reader structure"] +impl crate::Readable for MrccFlexcan1ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan1_clksel::W`](W) writer structure"] +impl crate::Writable for MrccFlexcan1ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_FLEXCAN1_CLKSEL to value 0x07"] +impl crate::Resettable for MrccFlexcan1ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs new file mode 100644 index 000000000..2f6f94e48 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_FLEXIO0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_FLEXIO0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "FLEXIO0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccFlexio0ClkdivSpec; +impl crate::RegisterSpec for MrccFlexio0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_flexio0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccFlexio0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_flexio0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccFlexio0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_FLEXIO0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccFlexio0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs new file mode 100644 index 000000000..cd004d340 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_FLEXIO0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_FLEXIO0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "1: FRO_HF_GATED"] + ClkrootFunc1 = 1, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 1 => Some(Mux::ClkrootFunc1), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn is_clkroot_func_1(&self) -> bool { + *self == Mux::ClkrootFunc1 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_GATED"] + #[inline(always)] + pub fn clkroot_func_1(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc1) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "FLEXIO0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccFlexio0ClkselSpec; +impl crate::RegisterSpec for MrccFlexio0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_flexio0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccFlexio0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_flexio0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccFlexio0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_FLEXIO0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccFlexio0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs new file mode 100644 index 000000000..f991a2048 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs @@ -0,0 +1,2039 @@ +#[doc = "Register `MRCC_GLB_ACC0` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_ACC0` writer"] +pub type W = crate::W; +#[doc = "INPUTMUX0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inputmux0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inputmux0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INPUTMUX0` reader - INPUTMUX0"] +pub type Inputmux0R = crate::BitReader; +impl Inputmux0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inputmux0 { + match self.bits { + false => Inputmux0::Disabled, + true => Inputmux0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Inputmux0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Inputmux0::Enabled + } +} +#[doc = "Field `INPUTMUX0` writer - INPUTMUX0"] +pub type Inputmux0W<'a, REG> = crate::BitWriter<'a, REG, Inputmux0>; +impl<'a, REG> Inputmux0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Inputmux0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Inputmux0::Enabled) + } +} +#[doc = "I3C0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I3c0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I3c0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I3C0` reader - I3C0"] +pub type I3c0R = crate::BitReader; +impl I3c0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I3c0 { + match self.bits { + false => I3c0::Disabled, + true => I3c0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == I3c0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == I3c0::Enabled + } +} +#[doc = "Field `I3C0` writer - I3C0"] +pub type I3c0W<'a, REG> = crate::BitWriter<'a, REG, I3c0>; +impl<'a, REG> I3c0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(I3c0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(I3c0::Enabled) + } +} +#[doc = "CTIMER0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER0` reader - CTIMER0"] +pub type Ctimer0R = crate::BitReader; +impl Ctimer0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer0 { + match self.bits { + false => Ctimer0::Disabled, + true => Ctimer0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer0::Enabled + } +} +#[doc = "Field `CTIMER0` writer - CTIMER0"] +pub type Ctimer0W<'a, REG> = crate::BitWriter<'a, REG, Ctimer0>; +impl<'a, REG> Ctimer0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer0::Enabled) + } +} +#[doc = "CTIMER1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER1` reader - CTIMER1"] +pub type Ctimer1R = crate::BitReader; +impl Ctimer1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer1 { + match self.bits { + false => Ctimer1::Disabled, + true => Ctimer1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer1::Enabled + } +} +#[doc = "Field `CTIMER1` writer - CTIMER1"] +pub type Ctimer1W<'a, REG> = crate::BitWriter<'a, REG, Ctimer1>; +impl<'a, REG> Ctimer1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer1::Enabled) + } +} +#[doc = "CTIMER2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER2` reader - CTIMER2"] +pub type Ctimer2R = crate::BitReader; +impl Ctimer2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer2 { + match self.bits { + false => Ctimer2::Disabled, + true => Ctimer2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer2::Enabled + } +} +#[doc = "Field `CTIMER2` writer - CTIMER2"] +pub type Ctimer2W<'a, REG> = crate::BitWriter<'a, REG, Ctimer2>; +impl<'a, REG> Ctimer2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer2::Enabled) + } +} +#[doc = "CTIMER3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer3 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER3` reader - CTIMER3"] +pub type Ctimer3R = crate::BitReader; +impl Ctimer3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer3 { + match self.bits { + false => Ctimer3::Disabled, + true => Ctimer3::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer3::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer3::Enabled + } +} +#[doc = "Field `CTIMER3` writer - CTIMER3"] +pub type Ctimer3W<'a, REG> = crate::BitWriter<'a, REG, Ctimer3>; +impl<'a, REG> Ctimer3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer3::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer3::Enabled) + } +} +#[doc = "CTIMER4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer4 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER4` reader - CTIMER4"] +pub type Ctimer4R = crate::BitReader; +impl Ctimer4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer4 { + match self.bits { + false => Ctimer4::Disabled, + true => Ctimer4::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer4::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer4::Enabled + } +} +#[doc = "Field `CTIMER4` writer - CTIMER4"] +pub type Ctimer4W<'a, REG> = crate::BitWriter<'a, REG, Ctimer4>; +impl<'a, REG> Ctimer4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer4::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer4::Enabled) + } +} +#[doc = "FREQME\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Freqme { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Freqme) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FREQME` reader - FREQME"] +pub type FreqmeR = crate::BitReader; +impl FreqmeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Freqme { + match self.bits { + false => Freqme::Disabled, + true => Freqme::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Freqme::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Freqme::Enabled + } +} +#[doc = "Field `FREQME` writer - FREQME"] +pub type FreqmeW<'a, REG> = crate::BitWriter<'a, REG, Freqme>; +impl<'a, REG> FreqmeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Freqme::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Freqme::Enabled) + } +} +#[doc = "UTICK0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Utick0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Utick0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UTICK0` reader - UTICK0"] +pub type Utick0R = crate::BitReader; +impl Utick0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Utick0 { + match self.bits { + false => Utick0::Disabled, + true => Utick0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Utick0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Utick0::Enabled + } +} +#[doc = "Field `UTICK0` writer - UTICK0"] +pub type Utick0W<'a, REG> = crate::BitWriter<'a, REG, Utick0>; +impl<'a, REG> Utick0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Utick0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Utick0::Enabled) + } +} +#[doc = "WWDT0\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wwdt0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wwdt0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WWDT0` reader - WWDT0"] +pub type Wwdt0R = crate::BitReader; +impl Wwdt0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wwdt0 { + match self.bits { + false => Wwdt0::Disabled, + true => Wwdt0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wwdt0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wwdt0::Enabled + } +} +#[doc = "Field `WWDT0` writer - WWDT0"] +pub type Wwdt0W<'a, REG> = crate::BitWriter<'a, REG, Wwdt0>; +impl<'a, REG> Wwdt0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Enabled) + } +} +#[doc = "SMARTDMA0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Smartdma0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Smartdma0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SMARTDMA0` reader - SMARTDMA0"] +pub type Smartdma0R = crate::BitReader; +impl Smartdma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Smartdma0 { + match self.bits { + false => Smartdma0::Disabled, + true => Smartdma0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Smartdma0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Smartdma0::Enabled + } +} +#[doc = "Field `SMARTDMA0` writer - SMARTDMA0"] +pub type Smartdma0W<'a, REG> = crate::BitWriter<'a, REG, Smartdma0>; +impl<'a, REG> Smartdma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Smartdma0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Smartdma0::Enabled) + } +} +#[doc = "DMA0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dma0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dma0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA0` reader - DMA0"] +pub type Dma0R = crate::BitReader; +impl Dma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dma0 { + match self.bits { + false => Dma0::Disabled, + true => Dma0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dma0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dma0::Enabled + } +} +#[doc = "Field `DMA0` writer - DMA0"] +pub type Dma0W<'a, REG> = crate::BitWriter<'a, REG, Dma0>; +impl<'a, REG> Dma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dma0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dma0::Enabled) + } +} +#[doc = "AOI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aoi0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aoi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AOI0` reader - AOI0"] +pub type Aoi0R = crate::BitReader; +impl Aoi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aoi0 { + match self.bits { + false => Aoi0::Disabled, + true => Aoi0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Aoi0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Aoi0::Enabled + } +} +#[doc = "Field `AOI0` writer - AOI0"] +pub type Aoi0W<'a, REG> = crate::BitWriter<'a, REG, Aoi0>; +impl<'a, REG> Aoi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Aoi0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Aoi0::Enabled) + } +} +#[doc = "CRC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crc0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRC0` reader - CRC0"] +pub type Crc0R = crate::BitReader; +impl Crc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crc0 { + match self.bits { + false => Crc0::Disabled, + true => Crc0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Crc0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Crc0::Enabled + } +} +#[doc = "Field `CRC0` writer - CRC0"] +pub type Crc0W<'a, REG> = crate::BitWriter<'a, REG, Crc0>; +impl<'a, REG> Crc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Crc0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Crc0::Enabled) + } +} +#[doc = "EIM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Eim0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Eim0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EIM0` reader - EIM0"] +pub type Eim0R = crate::BitReader; +impl Eim0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Eim0 { + match self.bits { + false => Eim0::Disabled, + true => Eim0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Eim0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Eim0::Enabled + } +} +#[doc = "Field `EIM0` writer - EIM0"] +pub type Eim0W<'a, REG> = crate::BitWriter<'a, REG, Eim0>; +impl<'a, REG> Eim0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Eim0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Eim0::Enabled) + } +} +#[doc = "ERM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erm0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erm0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERM0` reader - ERM0"] +pub type Erm0R = crate::BitReader; +impl Erm0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erm0 { + match self.bits { + false => Erm0::Disabled, + true => Erm0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Erm0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Erm0::Enabled + } +} +#[doc = "Field `ERM0` writer - ERM0"] +pub type Erm0W<'a, REG> = crate::BitWriter<'a, REG, Erm0>; +impl<'a, REG> Erm0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Erm0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Erm0::Enabled) + } +} +#[doc = "FMC\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fmc { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fmc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FMC` reader - FMC"] +pub type FmcR = crate::BitReader; +impl FmcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fmc { + match self.bits { + false => Fmc::Disabled, + true => Fmc::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fmc::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fmc::Enabled + } +} +#[doc = "Field `FMC` writer - FMC"] +pub type FmcW<'a, REG> = crate::BitWriter<'a, REG, Fmc>; +impl<'a, REG> FmcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fmc::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fmc::Enabled) + } +} +#[doc = "AOI1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aoi1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aoi1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AOI1` reader - AOI1"] +pub type Aoi1R = crate::BitReader; +impl Aoi1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aoi1 { + match self.bits { + false => Aoi1::Disabled, + true => Aoi1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Aoi1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Aoi1::Enabled + } +} +#[doc = "Field `AOI1` writer - AOI1"] +pub type Aoi1W<'a, REG> = crate::BitWriter<'a, REG, Aoi1>; +impl<'a, REG> Aoi1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Aoi1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Aoi1::Enabled) + } +} +#[doc = "FLEXIO0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexio0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexio0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXIO0` reader - FLEXIO0"] +pub type Flexio0R = crate::BitReader; +impl Flexio0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexio0 { + match self.bits { + false => Flexio0::Disabled, + true => Flexio0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexio0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexio0::Enabled + } +} +#[doc = "Field `FLEXIO0` writer - FLEXIO0"] +pub type Flexio0W<'a, REG> = crate::BitWriter<'a, REG, Flexio0>; +impl<'a, REG> Flexio0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexio0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexio0::Enabled) + } +} +#[doc = "LPI2C0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C0` reader - LPI2C0"] +pub type Lpi2c0R = crate::BitReader; +impl Lpi2c0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c0 { + match self.bits { + false => Lpi2c0::Disabled, + true => Lpi2c0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c0::Enabled + } +} +#[doc = "Field `LPI2C0` writer - LPI2C0"] +pub type Lpi2c0W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c0>; +impl<'a, REG> Lpi2c0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c0::Enabled) + } +} +#[doc = "LPI2C1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C1` reader - LPI2C1"] +pub type Lpi2c1R = crate::BitReader; +impl Lpi2c1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c1 { + match self.bits { + false => Lpi2c1::Disabled, + true => Lpi2c1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c1::Enabled + } +} +#[doc = "Field `LPI2C1` writer - LPI2C1"] +pub type Lpi2c1W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c1>; +impl<'a, REG> Lpi2c1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c1::Enabled) + } +} +#[doc = "LPSPI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpspi0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpspi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPSPI0` reader - LPSPI0"] +pub type Lpspi0R = crate::BitReader; +impl Lpspi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpspi0 { + match self.bits { + false => Lpspi0::Disabled, + true => Lpspi0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpspi0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpspi0::Enabled + } +} +#[doc = "Field `LPSPI0` writer - LPSPI0"] +pub type Lpspi0W<'a, REG> = crate::BitWriter<'a, REG, Lpspi0>; +impl<'a, REG> Lpspi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpspi0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpspi0::Enabled) + } +} +#[doc = "LPSPI1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpspi1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpspi1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPSPI1` reader - LPSPI1"] +pub type Lpspi1R = crate::BitReader; +impl Lpspi1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpspi1 { + match self.bits { + false => Lpspi1::Disabled, + true => Lpspi1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpspi1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpspi1::Enabled + } +} +#[doc = "Field `LPSPI1` writer - LPSPI1"] +pub type Lpspi1W<'a, REG> = crate::BitWriter<'a, REG, Lpspi1>; +impl<'a, REG> Lpspi1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpspi1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpspi1::Enabled) + } +} +#[doc = "LPUART0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART0` reader - LPUART0"] +pub type Lpuart0R = crate::BitReader; +impl Lpuart0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart0 { + match self.bits { + false => Lpuart0::Disabled, + true => Lpuart0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart0::Enabled + } +} +#[doc = "Field `LPUART0` writer - LPUART0"] +pub type Lpuart0W<'a, REG> = crate::BitWriter<'a, REG, Lpuart0>; +impl<'a, REG> Lpuart0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart0::Enabled) + } +} +#[doc = "LPUART1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART1` reader - LPUART1"] +pub type Lpuart1R = crate::BitReader; +impl Lpuart1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart1 { + match self.bits { + false => Lpuart1::Disabled, + true => Lpuart1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart1::Enabled + } +} +#[doc = "Field `LPUART1` writer - LPUART1"] +pub type Lpuart1W<'a, REG> = crate::BitWriter<'a, REG, Lpuart1>; +impl<'a, REG> Lpuart1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart1::Enabled) + } +} +#[doc = "LPUART2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART2` reader - LPUART2"] +pub type Lpuart2R = crate::BitReader; +impl Lpuart2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart2 { + match self.bits { + false => Lpuart2::Disabled, + true => Lpuart2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart2::Enabled + } +} +#[doc = "Field `LPUART2` writer - LPUART2"] +pub type Lpuart2W<'a, REG> = crate::BitWriter<'a, REG, Lpuart2>; +impl<'a, REG> Lpuart2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart2::Enabled) + } +} +#[doc = "LPUART3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart3 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART3` reader - LPUART3"] +pub type Lpuart3R = crate::BitReader; +impl Lpuart3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart3 { + match self.bits { + false => Lpuart3::Disabled, + true => Lpuart3::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart3::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart3::Enabled + } +} +#[doc = "Field `LPUART3` writer - LPUART3"] +pub type Lpuart3W<'a, REG> = crate::BitWriter<'a, REG, Lpuart3>; +impl<'a, REG> Lpuart3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart3::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart3::Enabled) + } +} +#[doc = "LPUART4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart4 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART4` reader - LPUART4"] +pub type Lpuart4R = crate::BitReader; +impl Lpuart4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart4 { + match self.bits { + false => Lpuart4::Disabled, + true => Lpuart4::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart4::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart4::Enabled + } +} +#[doc = "Field `LPUART4` writer - LPUART4"] +pub type Lpuart4W<'a, REG> = crate::BitWriter<'a, REG, Lpuart4>; +impl<'a, REG> Lpuart4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart4::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart4::Enabled) + } +} +#[doc = "USB0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usb0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usb0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USB0` reader - USB0"] +pub type Usb0R = crate::BitReader; +impl Usb0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Usb0 { + match self.bits { + false => Usb0::Disabled, + true => Usb0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Usb0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Usb0::Enabled + } +} +#[doc = "Field `USB0` writer - USB0"] +pub type Usb0W<'a, REG> = crate::BitWriter<'a, REG, Usb0>; +impl<'a, REG> Usb0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Usb0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Usb0::Enabled) + } +} +#[doc = "QDC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Qdc0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Qdc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `QDC0` reader - QDC0"] +pub type Qdc0R = crate::BitReader; +impl Qdc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Qdc0 { + match self.bits { + false => Qdc0::Disabled, + true => Qdc0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Qdc0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Qdc0::Enabled + } +} +#[doc = "Field `QDC0` writer - QDC0"] +pub type Qdc0W<'a, REG> = crate::BitWriter<'a, REG, Qdc0>; +impl<'a, REG> Qdc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Qdc0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Qdc0::Enabled) + } +} +#[doc = "QDC1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Qdc1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Qdc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `QDC1` reader - QDC1"] +pub type Qdc1R = crate::BitReader; +impl Qdc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Qdc1 { + match self.bits { + false => Qdc1::Disabled, + true => Qdc1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Qdc1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Qdc1::Enabled + } +} +#[doc = "Field `QDC1` writer - QDC1"] +pub type Qdc1W<'a, REG> = crate::BitWriter<'a, REG, Qdc1>; +impl<'a, REG> Qdc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Qdc1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Qdc1::Enabled) + } +} +#[doc = "FLEXPWM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexpwm0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexpwm0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXPWM0` reader - FLEXPWM0"] +pub type Flexpwm0R = crate::BitReader; +impl Flexpwm0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexpwm0 { + match self.bits { + false => Flexpwm0::Disabled, + true => Flexpwm0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexpwm0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexpwm0::Enabled + } +} +#[doc = "Field `FLEXPWM0` writer - FLEXPWM0"] +pub type Flexpwm0W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm0>; +impl<'a, REG> Flexpwm0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexpwm0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexpwm0::Enabled) + } +} +impl R { + #[doc = "Bit 0 - INPUTMUX0"] + #[inline(always)] + pub fn inputmux0(&self) -> Inputmux0R { + Inputmux0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I3C0"] + #[inline(always)] + pub fn i3c0(&self) -> I3c0R { + I3c0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTIMER0"] + #[inline(always)] + pub fn ctimer0(&self) -> Ctimer0R { + Ctimer0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - CTIMER1"] + #[inline(always)] + pub fn ctimer1(&self) -> Ctimer1R { + Ctimer1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - CTIMER2"] + #[inline(always)] + pub fn ctimer2(&self) -> Ctimer2R { + Ctimer2R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - CTIMER3"] + #[inline(always)] + pub fn ctimer3(&self) -> Ctimer3R { + Ctimer3R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - CTIMER4"] + #[inline(always)] + pub fn ctimer4(&self) -> Ctimer4R { + Ctimer4R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FREQME"] + #[inline(always)] + pub fn freqme(&self) -> FreqmeR { + FreqmeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - UTICK0"] + #[inline(always)] + pub fn utick0(&self) -> Utick0R { + Utick0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - WWDT0"] + #[inline(always)] + pub fn wwdt0(&self) -> Wwdt0R { + Wwdt0R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SMARTDMA0"] + #[inline(always)] + pub fn smartdma0(&self) -> Smartdma0R { + Smartdma0R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DMA0"] + #[inline(always)] + pub fn dma0(&self) -> Dma0R { + Dma0R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - AOI0"] + #[inline(always)] + pub fn aoi0(&self) -> Aoi0R { + Aoi0R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - CRC0"] + #[inline(always)] + pub fn crc0(&self) -> Crc0R { + Crc0R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - EIM0"] + #[inline(always)] + pub fn eim0(&self) -> Eim0R { + Eim0R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - ERM0"] + #[inline(always)] + pub fn erm0(&self) -> Erm0R { + Erm0R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - FMC"] + #[inline(always)] + pub fn fmc(&self) -> FmcR { + FmcR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - AOI1"] + #[inline(always)] + pub fn aoi1(&self) -> Aoi1R { + Aoi1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - FLEXIO0"] + #[inline(always)] + pub fn flexio0(&self) -> Flexio0R { + Flexio0R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - LPI2C0"] + #[inline(always)] + pub fn lpi2c0(&self) -> Lpi2c0R { + Lpi2c0R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LPI2C1"] + #[inline(always)] + pub fn lpi2c1(&self) -> Lpi2c1R { + Lpi2c1R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LPSPI0"] + #[inline(always)] + pub fn lpspi0(&self) -> Lpspi0R { + Lpspi0R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LPSPI1"] + #[inline(always)] + pub fn lpspi1(&self) -> Lpspi1R { + Lpspi1R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - LPUART0"] + #[inline(always)] + pub fn lpuart0(&self) -> Lpuart0R { + Lpuart0R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - LPUART1"] + #[inline(always)] + pub fn lpuart1(&self) -> Lpuart1R { + Lpuart1R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - LPUART2"] + #[inline(always)] + pub fn lpuart2(&self) -> Lpuart2R { + Lpuart2R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - LPUART3"] + #[inline(always)] + pub fn lpuart3(&self) -> Lpuart3R { + Lpuart3R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LPUART4"] + #[inline(always)] + pub fn lpuart4(&self) -> Lpuart4R { + Lpuart4R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - USB0"] + #[inline(always)] + pub fn usb0(&self) -> Usb0R { + Usb0R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - QDC0"] + #[inline(always)] + pub fn qdc0(&self) -> Qdc0R { + Qdc0R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - QDC1"] + #[inline(always)] + pub fn qdc1(&self) -> Qdc1R { + Qdc1R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - FLEXPWM0"] + #[inline(always)] + pub fn flexpwm0(&self) -> Flexpwm0R { + Flexpwm0R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - INPUTMUX0"] + #[inline(always)] + pub fn inputmux0(&mut self) -> Inputmux0W { + Inputmux0W::new(self, 0) + } + #[doc = "Bit 1 - I3C0"] + #[inline(always)] + pub fn i3c0(&mut self) -> I3c0W { + I3c0W::new(self, 1) + } + #[doc = "Bit 2 - CTIMER0"] + #[inline(always)] + pub fn ctimer0(&mut self) -> Ctimer0W { + Ctimer0W::new(self, 2) + } + #[doc = "Bit 3 - CTIMER1"] + #[inline(always)] + pub fn ctimer1(&mut self) -> Ctimer1W { + Ctimer1W::new(self, 3) + } + #[doc = "Bit 4 - CTIMER2"] + #[inline(always)] + pub fn ctimer2(&mut self) -> Ctimer2W { + Ctimer2W::new(self, 4) + } + #[doc = "Bit 5 - CTIMER3"] + #[inline(always)] + pub fn ctimer3(&mut self) -> Ctimer3W { + Ctimer3W::new(self, 5) + } + #[doc = "Bit 6 - CTIMER4"] + #[inline(always)] + pub fn ctimer4(&mut self) -> Ctimer4W { + Ctimer4W::new(self, 6) + } + #[doc = "Bit 7 - FREQME"] + #[inline(always)] + pub fn freqme(&mut self) -> FreqmeW { + FreqmeW::new(self, 7) + } + #[doc = "Bit 8 - UTICK0"] + #[inline(always)] + pub fn utick0(&mut self) -> Utick0W { + Utick0W::new(self, 8) + } + #[doc = "Bit 9 - WWDT0"] + #[inline(always)] + pub fn wwdt0(&mut self) -> Wwdt0W { + Wwdt0W::new(self, 9) + } + #[doc = "Bit 10 - SMARTDMA0"] + #[inline(always)] + pub fn smartdma0(&mut self) -> Smartdma0W { + Smartdma0W::new(self, 10) + } + #[doc = "Bit 11 - DMA0"] + #[inline(always)] + pub fn dma0(&mut self) -> Dma0W { + Dma0W::new(self, 11) + } + #[doc = "Bit 12 - AOI0"] + #[inline(always)] + pub fn aoi0(&mut self) -> Aoi0W { + Aoi0W::new(self, 12) + } + #[doc = "Bit 13 - CRC0"] + #[inline(always)] + pub fn crc0(&mut self) -> Crc0W { + Crc0W::new(self, 13) + } + #[doc = "Bit 14 - EIM0"] + #[inline(always)] + pub fn eim0(&mut self) -> Eim0W { + Eim0W::new(self, 14) + } + #[doc = "Bit 15 - ERM0"] + #[inline(always)] + pub fn erm0(&mut self) -> Erm0W { + Erm0W::new(self, 15) + } + #[doc = "Bit 16 - FMC"] + #[inline(always)] + pub fn fmc(&mut self) -> FmcW { + FmcW::new(self, 16) + } + #[doc = "Bit 17 - AOI1"] + #[inline(always)] + pub fn aoi1(&mut self) -> Aoi1W { + Aoi1W::new(self, 17) + } + #[doc = "Bit 18 - FLEXIO0"] + #[inline(always)] + pub fn flexio0(&mut self) -> Flexio0W { + Flexio0W::new(self, 18) + } + #[doc = "Bit 19 - LPI2C0"] + #[inline(always)] + pub fn lpi2c0(&mut self) -> Lpi2c0W { + Lpi2c0W::new(self, 19) + } + #[doc = "Bit 20 - LPI2C1"] + #[inline(always)] + pub fn lpi2c1(&mut self) -> Lpi2c1W { + Lpi2c1W::new(self, 20) + } + #[doc = "Bit 21 - LPSPI0"] + #[inline(always)] + pub fn lpspi0(&mut self) -> Lpspi0W { + Lpspi0W::new(self, 21) + } + #[doc = "Bit 22 - LPSPI1"] + #[inline(always)] + pub fn lpspi1(&mut self) -> Lpspi1W { + Lpspi1W::new(self, 22) + } + #[doc = "Bit 23 - LPUART0"] + #[inline(always)] + pub fn lpuart0(&mut self) -> Lpuart0W { + Lpuart0W::new(self, 23) + } + #[doc = "Bit 24 - LPUART1"] + #[inline(always)] + pub fn lpuart1(&mut self) -> Lpuart1W { + Lpuart1W::new(self, 24) + } + #[doc = "Bit 25 - LPUART2"] + #[inline(always)] + pub fn lpuart2(&mut self) -> Lpuart2W { + Lpuart2W::new(self, 25) + } + #[doc = "Bit 26 - LPUART3"] + #[inline(always)] + pub fn lpuart3(&mut self) -> Lpuart3W { + Lpuart3W::new(self, 26) + } + #[doc = "Bit 27 - LPUART4"] + #[inline(always)] + pub fn lpuart4(&mut self) -> Lpuart4W { + Lpuart4W::new(self, 27) + } + #[doc = "Bit 28 - USB0"] + #[inline(always)] + pub fn usb0(&mut self) -> Usb0W { + Usb0W::new(self, 28) + } + #[doc = "Bit 29 - QDC0"] + #[inline(always)] + pub fn qdc0(&mut self) -> Qdc0W { + Qdc0W::new(self, 29) + } + #[doc = "Bit 30 - QDC1"] + #[inline(always)] + pub fn qdc1(&mut self) -> Qdc1W { + Qdc1W::new(self, 30) + } + #[doc = "Bit 31 - FLEXPWM0"] + #[inline(always)] + pub fn flexpwm0(&mut self) -> Flexpwm0W { + Flexpwm0W::new(self, 31) + } +} +#[doc = "Control Automatic Clock Gating 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbAcc0Spec; +impl crate::RegisterSpec for MrccGlbAcc0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_acc0::R`](R) reader structure"] +impl crate::Readable for MrccGlbAcc0Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc0::W`](W) writer structure"] +impl crate::Writable for MrccGlbAcc0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_ACC0 to value 0x0001_0200"] +impl crate::Resettable for MrccGlbAcc0Spec { + const RESET_VALUE: u32 = 0x0001_0200; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs new file mode 100644 index 000000000..241308455 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs @@ -0,0 +1,1848 @@ +#[doc = "Register `MRCC_GLB_ACC1` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_ACC1` writer"] +pub type W = crate::W; +#[doc = "FLEXPWM1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexpwm1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexpwm1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXPWM1` reader - FLEXPWM1"] +pub type Flexpwm1R = crate::BitReader; +impl Flexpwm1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexpwm1 { + match self.bits { + false => Flexpwm1::Disabled, + true => Flexpwm1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexpwm1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexpwm1::Enabled + } +} +#[doc = "Field `FLEXPWM1` writer - FLEXPWM1"] +pub type Flexpwm1W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm1>; +impl<'a, REG> Flexpwm1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexpwm1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexpwm1::Enabled) + } +} +#[doc = "OSTIMER0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ostimer0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ostimer0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSTIMER0` reader - OSTIMER0"] +pub type Ostimer0R = crate::BitReader; +impl Ostimer0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ostimer0 { + match self.bits { + false => Ostimer0::Disabled, + true => Ostimer0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ostimer0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ostimer0::Enabled + } +} +#[doc = "Field `OSTIMER0` writer - OSTIMER0"] +pub type Ostimer0W<'a, REG> = crate::BitWriter<'a, REG, Ostimer0>; +impl<'a, REG> Ostimer0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ostimer0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ostimer0::Enabled) + } +} +#[doc = "ADC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC0` reader - ADC0"] +pub type Adc0R = crate::BitReader; +impl Adc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc0 { + match self.bits { + false => Adc0::Disabled, + true => Adc0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc0::Enabled + } +} +#[doc = "Field `ADC0` writer - ADC0"] +pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG, Adc0>; +impl<'a, REG> Adc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc0::Enabled) + } +} +#[doc = "ADC1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC1` reader - ADC1"] +pub type Adc1R = crate::BitReader; +impl Adc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc1 { + match self.bits { + false => Adc1::Disabled, + true => Adc1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc1::Enabled + } +} +#[doc = "Field `ADC1` writer - ADC1"] +pub type Adc1W<'a, REG> = crate::BitWriter<'a, REG, Adc1>; +impl<'a, REG> Adc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc1::Enabled) + } +} +#[doc = "CMP0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP0` reader - CMP0"] +pub type Cmp0R = crate::BitReader; +impl Cmp0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp0 { + match self.bits { + false => Cmp0::Disabled, + true => Cmp0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp0::Enabled + } +} +#[doc = "Field `CMP0` writer - CMP0"] +pub type Cmp0W<'a, REG> = crate::BitWriter<'a, REG, Cmp0>; +impl<'a, REG> Cmp0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp0::Enabled) + } +} +#[doc = "CMP1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP1` reader - CMP1"] +pub type Cmp1R = crate::BitReader; +impl Cmp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp1 { + match self.bits { + false => Cmp1::Disabled, + true => Cmp1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp1::Enabled + } +} +#[doc = "Field `CMP1` writer - CMP1"] +pub type Cmp1W<'a, REG> = crate::BitWriter<'a, REG, Cmp1>; +impl<'a, REG> Cmp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp1::Enabled) + } +} +#[doc = "CMP2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP2` reader - CMP2"] +pub type Cmp2R = crate::BitReader; +impl Cmp2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp2 { + match self.bits { + false => Cmp2::Disabled, + true => Cmp2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp2::Enabled + } +} +#[doc = "Field `CMP2` writer - CMP2"] +pub type Cmp2W<'a, REG> = crate::BitWriter<'a, REG, Cmp2>; +impl<'a, REG> Cmp2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp2::Enabled) + } +} +#[doc = "DAC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dac0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dac0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAC0` reader - DAC0"] +pub type Dac0R = crate::BitReader; +impl Dac0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dac0 { + match self.bits { + false => Dac0::Disabled, + true => Dac0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dac0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dac0::Enabled + } +} +#[doc = "Field `DAC0` writer - DAC0"] +pub type Dac0W<'a, REG> = crate::BitWriter<'a, REG, Dac0>; +impl<'a, REG> Dac0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dac0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dac0::Enabled) + } +} +#[doc = "OPAMP0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP0` reader - OPAMP0"] +pub type Opamp0R = crate::BitReader; +impl Opamp0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp0 { + match self.bits { + false => Opamp0::Disabled, + true => Opamp0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp0::Enabled + } +} +#[doc = "Field `OPAMP0` writer - OPAMP0"] +pub type Opamp0W<'a, REG> = crate::BitWriter<'a, REG, Opamp0>; +impl<'a, REG> Opamp0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp0::Enabled) + } +} +#[doc = "OPAMP1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP1` reader - OPAMP1"] +pub type Opamp1R = crate::BitReader; +impl Opamp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp1 { + match self.bits { + false => Opamp1::Disabled, + true => Opamp1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp1::Enabled + } +} +#[doc = "Field `OPAMP1` writer - OPAMP1"] +pub type Opamp1W<'a, REG> = crate::BitWriter<'a, REG, Opamp1>; +impl<'a, REG> Opamp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp1::Enabled) + } +} +#[doc = "OPAMP2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP2` reader - OPAMP2"] +pub type Opamp2R = crate::BitReader; +impl Opamp2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp2 { + match self.bits { + false => Opamp2::Disabled, + true => Opamp2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp2::Enabled + } +} +#[doc = "Field `OPAMP2` writer - OPAMP2"] +pub type Opamp2W<'a, REG> = crate::BitWriter<'a, REG, Opamp2>; +impl<'a, REG> Opamp2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp2::Enabled) + } +} +#[doc = "OPAMP3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp3 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP3` reader - OPAMP3"] +pub type Opamp3R = crate::BitReader; +impl Opamp3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp3 { + match self.bits { + false => Opamp3::Disabled, + true => Opamp3::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp3::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp3::Enabled + } +} +#[doc = "Field `OPAMP3` writer - OPAMP3"] +pub type Opamp3W<'a, REG> = crate::BitWriter<'a, REG, Opamp3>; +impl<'a, REG> Opamp3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp3::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp3::Enabled) + } +} +#[doc = "PORT0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT0` reader - PORT0"] +pub type Port0R = crate::BitReader; +impl Port0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port0 { + match self.bits { + false => Port0::Disabled, + true => Port0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port0::Enabled + } +} +#[doc = "Field `PORT0` writer - PORT0"] +pub type Port0W<'a, REG> = crate::BitWriter<'a, REG, Port0>; +impl<'a, REG> Port0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port0::Enabled) + } +} +#[doc = "PORT1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT1` reader - PORT1"] +pub type Port1R = crate::BitReader; +impl Port1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port1 { + match self.bits { + false => Port1::Disabled, + true => Port1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port1::Enabled + } +} +#[doc = "Field `PORT1` writer - PORT1"] +pub type Port1W<'a, REG> = crate::BitWriter<'a, REG, Port1>; +impl<'a, REG> Port1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port1::Enabled) + } +} +#[doc = "PORT2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT2` reader - PORT2"] +pub type Port2R = crate::BitReader; +impl Port2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port2 { + match self.bits { + false => Port2::Disabled, + true => Port2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port2::Enabled + } +} +#[doc = "Field `PORT2` writer - PORT2"] +pub type Port2W<'a, REG> = crate::BitWriter<'a, REG, Port2>; +impl<'a, REG> Port2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port2::Enabled) + } +} +#[doc = "PORT3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port3 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT3` reader - PORT3"] +pub type Port3R = crate::BitReader; +impl Port3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port3 { + match self.bits { + false => Port3::Disabled, + true => Port3::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port3::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port3::Enabled + } +} +#[doc = "Field `PORT3` writer - PORT3"] +pub type Port3W<'a, REG> = crate::BitWriter<'a, REG, Port3>; +impl<'a, REG> Port3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port3::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port3::Enabled) + } +} +#[doc = "PORT4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port4 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT4` reader - PORT4"] +pub type Port4R = crate::BitReader; +impl Port4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port4 { + match self.bits { + false => Port4::Disabled, + true => Port4::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port4::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port4::Enabled + } +} +#[doc = "Field `PORT4` writer - PORT4"] +pub type Port4W<'a, REG> = crate::BitWriter<'a, REG, Port4>; +impl<'a, REG> Port4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port4::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port4::Enabled) + } +} +#[doc = "SLCD0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slcd0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slcd0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLCD0` reader - SLCD0"] +pub type Slcd0R = crate::BitReader; +impl Slcd0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slcd0 { + match self.bits { + false => Slcd0::Disabled, + true => Slcd0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Slcd0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Slcd0::Enabled + } +} +#[doc = "Field `SLCD0` writer - SLCD0"] +pub type Slcd0W<'a, REG> = crate::BitWriter<'a, REG, Slcd0>; +impl<'a, REG> Slcd0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Slcd0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Slcd0::Enabled) + } +} +#[doc = "FLEXCAN0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexcan0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexcan0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXCAN0` reader - FLEXCAN0"] +pub type Flexcan0R = crate::BitReader; +impl Flexcan0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexcan0 { + match self.bits { + false => Flexcan0::Disabled, + true => Flexcan0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexcan0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexcan0::Enabled + } +} +#[doc = "Field `FLEXCAN0` writer - FLEXCAN0"] +pub type Flexcan0W<'a, REG> = crate::BitWriter<'a, REG, Flexcan0>; +impl<'a, REG> Flexcan0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexcan0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexcan0::Enabled) + } +} +#[doc = "FLEXCAN1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexcan1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexcan1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXCAN1` reader - FLEXCAN1"] +pub type Flexcan1R = crate::BitReader; +impl Flexcan1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexcan1 { + match self.bits { + false => Flexcan1::Disabled, + true => Flexcan1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexcan1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexcan1::Enabled + } +} +#[doc = "Field `FLEXCAN1` writer - FLEXCAN1"] +pub type Flexcan1W<'a, REG> = crate::BitWriter<'a, REG, Flexcan1>; +impl<'a, REG> Flexcan1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexcan1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexcan1::Enabled) + } +} +#[doc = "LPI2C2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C2` reader - LPI2C2"] +pub type Lpi2c2R = crate::BitReader; +impl Lpi2c2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c2 { + match self.bits { + false => Lpi2c2::Disabled, + true => Lpi2c2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c2::Enabled + } +} +#[doc = "Field `LPI2C2` writer - LPI2C2"] +pub type Lpi2c2W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c2>; +impl<'a, REG> Lpi2c2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c2::Enabled) + } +} +#[doc = "LPI2C3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c3 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C3` reader - LPI2C3"] +pub type Lpi2c3R = crate::BitReader; +impl Lpi2c3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c3 { + match self.bits { + false => Lpi2c3::Disabled, + true => Lpi2c3::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c3::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c3::Enabled + } +} +#[doc = "Field `LPI2C3` writer - LPI2C3"] +pub type Lpi2c3W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c3>; +impl<'a, REG> Lpi2c3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c3::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c3::Enabled) + } +} +#[doc = "LPUART5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart5 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART5` reader - LPUART5"] +pub type Lpuart5R = crate::BitReader; +impl Lpuart5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart5 { + match self.bits { + false => Lpuart5::Disabled, + true => Lpuart5::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart5::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart5::Enabled + } +} +#[doc = "Field `LPUART5` writer - LPUART5"] +pub type Lpuart5W<'a, REG> = crate::BitWriter<'a, REG, Lpuart5>; +impl<'a, REG> Lpuart5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart5::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart5::Enabled) + } +} +#[doc = "PKC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pkc0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pkc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PKC0` reader - PKC0"] +pub type Pkc0R = crate::BitReader; +impl Pkc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pkc0 { + match self.bits { + false => Pkc0::Disabled, + true => Pkc0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pkc0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pkc0::Enabled + } +} +#[doc = "Field `PKC0` writer - PKC0"] +pub type Pkc0W<'a, REG> = crate::BitWriter<'a, REG, Pkc0>; +impl<'a, REG> Pkc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pkc0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pkc0::Enabled) + } +} +#[doc = "SGI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sgi0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sgi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SGI0` reader - SGI0"] +pub type Sgi0R = crate::BitReader; +impl Sgi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sgi0 { + match self.bits { + false => Sgi0::Disabled, + true => Sgi0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sgi0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sgi0::Enabled + } +} +#[doc = "Field `SGI0` writer - SGI0"] +pub type Sgi0W<'a, REG> = crate::BitWriter<'a, REG, Sgi0>; +impl<'a, REG> Sgi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sgi0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sgi0::Enabled) + } +} +#[doc = "TRNG0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trng0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trng0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRNG0` reader - TRNG0"] +pub type Trng0R = crate::BitReader; +impl Trng0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trng0 { + match self.bits { + false => Trng0::Disabled, + true => Trng0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Trng0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Trng0::Enabled + } +} +#[doc = "Field `TRNG0` writer - TRNG0"] +pub type Trng0W<'a, REG> = crate::BitWriter<'a, REG, Trng0>; +impl<'a, REG> Trng0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Trng0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Trng0::Enabled) + } +} +#[doc = "UDF0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Udf0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Udf0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UDF0` reader - UDF0"] +pub type Udf0R = crate::BitReader; +impl Udf0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Udf0 { + match self.bits { + false => Udf0::Disabled, + true => Udf0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Udf0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Udf0::Enabled + } +} +#[doc = "Field `UDF0` writer - UDF0"] +pub type Udf0W<'a, REG> = crate::BitWriter<'a, REG, Udf0>; +impl<'a, REG> Udf0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Udf0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Udf0::Enabled) + } +} +#[doc = "ADC2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC2` reader - ADC2"] +pub type Adc2R = crate::BitReader; +impl Adc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc2 { + match self.bits { + false => Adc2::Disabled, + true => Adc2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc2::Enabled + } +} +#[doc = "Field `ADC2` writer - ADC2"] +pub type Adc2W<'a, REG> = crate::BitWriter<'a, REG, Adc2>; +impl<'a, REG> Adc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc2::Enabled) + } +} +#[doc = "ADC3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc3 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC3` reader - ADC3"] +pub type Adc3R = crate::BitReader; +impl Adc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc3 { + match self.bits { + false => Adc3::Disabled, + true => Adc3::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc3::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc3::Enabled + } +} +#[doc = "Field `ADC3` writer - ADC3"] +pub type Adc3W<'a, REG> = crate::BitWriter<'a, REG, Adc3>; +impl<'a, REG> Adc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc3::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc3::Enabled) + } +} +impl R { + #[doc = "Bit 0 - FLEXPWM1"] + #[inline(always)] + pub fn flexpwm1(&self) -> Flexpwm1R { + Flexpwm1R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - OSTIMER0"] + #[inline(always)] + pub fn ostimer0(&self) -> Ostimer0R { + Ostimer0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - ADC0"] + #[inline(always)] + pub fn adc0(&self) -> Adc0R { + Adc0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ADC1"] + #[inline(always)] + pub fn adc1(&self) -> Adc1R { + Adc1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - CMP0"] + #[inline(always)] + pub fn cmp0(&self) -> Cmp0R { + Cmp0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - CMP1"] + #[inline(always)] + pub fn cmp1(&self) -> Cmp1R { + Cmp1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - CMP2"] + #[inline(always)] + pub fn cmp2(&self) -> Cmp2R { + Cmp2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - DAC0"] + #[inline(always)] + pub fn dac0(&self) -> Dac0R { + Dac0R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - OPAMP0"] + #[inline(always)] + pub fn opamp0(&self) -> Opamp0R { + Opamp0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - OPAMP1"] + #[inline(always)] + pub fn opamp1(&self) -> Opamp1R { + Opamp1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OPAMP2"] + #[inline(always)] + pub fn opamp2(&self) -> Opamp2R { + Opamp2R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - OPAMP3"] + #[inline(always)] + pub fn opamp3(&self) -> Opamp3R { + Opamp3R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - PORT0"] + #[inline(always)] + pub fn port0(&self) -> Port0R { + Port0R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - PORT1"] + #[inline(always)] + pub fn port1(&self) -> Port1R { + Port1R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PORT2"] + #[inline(always)] + pub fn port2(&self) -> Port2R { + Port2R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - PORT3"] + #[inline(always)] + pub fn port3(&self) -> Port3R { + Port3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - PORT4"] + #[inline(always)] + pub fn port4(&self) -> Port4R { + Port4R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SLCD0"] + #[inline(always)] + pub fn slcd0(&self) -> Slcd0R { + Slcd0R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - FLEXCAN0"] + #[inline(always)] + pub fn flexcan0(&self) -> Flexcan0R { + Flexcan0R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - FLEXCAN1"] + #[inline(always)] + pub fn flexcan1(&self) -> Flexcan1R { + Flexcan1R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LPI2C2"] + #[inline(always)] + pub fn lpi2c2(&self) -> Lpi2c2R { + Lpi2c2R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LPI2C3"] + #[inline(always)] + pub fn lpi2c3(&self) -> Lpi2c3R { + Lpi2c3R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LPUART5"] + #[inline(always)] + pub fn lpuart5(&self) -> Lpuart5R { + Lpuart5R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - PKC0"] + #[inline(always)] + pub fn pkc0(&self) -> Pkc0R { + Pkc0R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - SGI0"] + #[inline(always)] + pub fn sgi0(&self) -> Sgi0R { + Sgi0R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - TRNG0"] + #[inline(always)] + pub fn trng0(&self) -> Trng0R { + Trng0R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - UDF0"] + #[inline(always)] + pub fn udf0(&self) -> Udf0R { + Udf0R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - ADC2"] + #[inline(always)] + pub fn adc2(&self) -> Adc2R { + Adc2R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - ADC3"] + #[inline(always)] + pub fn adc3(&self) -> Adc3R { + Adc3R::new(((self.bits >> 29) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLEXPWM1"] + #[inline(always)] + pub fn flexpwm1(&mut self) -> Flexpwm1W { + Flexpwm1W::new(self, 0) + } + #[doc = "Bit 1 - OSTIMER0"] + #[inline(always)] + pub fn ostimer0(&mut self) -> Ostimer0W { + Ostimer0W::new(self, 1) + } + #[doc = "Bit 2 - ADC0"] + #[inline(always)] + pub fn adc0(&mut self) -> Adc0W { + Adc0W::new(self, 2) + } + #[doc = "Bit 3 - ADC1"] + #[inline(always)] + pub fn adc1(&mut self) -> Adc1W { + Adc1W::new(self, 3) + } + #[doc = "Bit 4 - CMP0"] + #[inline(always)] + pub fn cmp0(&mut self) -> Cmp0W { + Cmp0W::new(self, 4) + } + #[doc = "Bit 5 - CMP1"] + #[inline(always)] + pub fn cmp1(&mut self) -> Cmp1W { + Cmp1W::new(self, 5) + } + #[doc = "Bit 6 - CMP2"] + #[inline(always)] + pub fn cmp2(&mut self) -> Cmp2W { + Cmp2W::new(self, 6) + } + #[doc = "Bit 7 - DAC0"] + #[inline(always)] + pub fn dac0(&mut self) -> Dac0W { + Dac0W::new(self, 7) + } + #[doc = "Bit 8 - OPAMP0"] + #[inline(always)] + pub fn opamp0(&mut self) -> Opamp0W { + Opamp0W::new(self, 8) + } + #[doc = "Bit 9 - OPAMP1"] + #[inline(always)] + pub fn opamp1(&mut self) -> Opamp1W { + Opamp1W::new(self, 9) + } + #[doc = "Bit 10 - OPAMP2"] + #[inline(always)] + pub fn opamp2(&mut self) -> Opamp2W { + Opamp2W::new(self, 10) + } + #[doc = "Bit 11 - OPAMP3"] + #[inline(always)] + pub fn opamp3(&mut self) -> Opamp3W { + Opamp3W::new(self, 11) + } + #[doc = "Bit 12 - PORT0"] + #[inline(always)] + pub fn port0(&mut self) -> Port0W { + Port0W::new(self, 12) + } + #[doc = "Bit 13 - PORT1"] + #[inline(always)] + pub fn port1(&mut self) -> Port1W { + Port1W::new(self, 13) + } + #[doc = "Bit 14 - PORT2"] + #[inline(always)] + pub fn port2(&mut self) -> Port2W { + Port2W::new(self, 14) + } + #[doc = "Bit 15 - PORT3"] + #[inline(always)] + pub fn port3(&mut self) -> Port3W { + Port3W::new(self, 15) + } + #[doc = "Bit 16 - PORT4"] + #[inline(always)] + pub fn port4(&mut self) -> Port4W { + Port4W::new(self, 16) + } + #[doc = "Bit 17 - SLCD0"] + #[inline(always)] + pub fn slcd0(&mut self) -> Slcd0W { + Slcd0W::new(self, 17) + } + #[doc = "Bit 18 - FLEXCAN0"] + #[inline(always)] + pub fn flexcan0(&mut self) -> Flexcan0W { + Flexcan0W::new(self, 18) + } + #[doc = "Bit 19 - FLEXCAN1"] + #[inline(always)] + pub fn flexcan1(&mut self) -> Flexcan1W { + Flexcan1W::new(self, 19) + } + #[doc = "Bit 20 - LPI2C2"] + #[inline(always)] + pub fn lpi2c2(&mut self) -> Lpi2c2W { + Lpi2c2W::new(self, 20) + } + #[doc = "Bit 21 - LPI2C3"] + #[inline(always)] + pub fn lpi2c3(&mut self) -> Lpi2c3W { + Lpi2c3W::new(self, 21) + } + #[doc = "Bit 22 - LPUART5"] + #[inline(always)] + pub fn lpuart5(&mut self) -> Lpuart5W { + Lpuart5W::new(self, 22) + } + #[doc = "Bit 24 - PKC0"] + #[inline(always)] + pub fn pkc0(&mut self) -> Pkc0W { + Pkc0W::new(self, 24) + } + #[doc = "Bit 25 - SGI0"] + #[inline(always)] + pub fn sgi0(&mut self) -> Sgi0W { + Sgi0W::new(self, 25) + } + #[doc = "Bit 26 - TRNG0"] + #[inline(always)] + pub fn trng0(&mut self) -> Trng0W { + Trng0W::new(self, 26) + } + #[doc = "Bit 27 - UDF0"] + #[inline(always)] + pub fn udf0(&mut self) -> Udf0W { + Udf0W::new(self, 27) + } + #[doc = "Bit 28 - ADC2"] + #[inline(always)] + pub fn adc2(&mut self) -> Adc2W { + Adc2W::new(self, 28) + } + #[doc = "Bit 29 - ADC3"] + #[inline(always)] + pub fn adc3(&mut self) -> Adc3W { + Adc3W::new(self, 29) + } +} +#[doc = "Control Automatic Clock Gating 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbAcc1Spec; +impl crate::RegisterSpec for MrccGlbAcc1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_acc1::R`](R) reader structure"] +impl crate::Readable for MrccGlbAcc1Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc1::W`](W) writer structure"] +impl crate::Writable for MrccGlbAcc1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_ACC1 to value 0"] +impl crate::Resettable for MrccGlbAcc1Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs new file mode 100644 index 000000000..4898a871a --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs @@ -0,0 +1,653 @@ +#[doc = "Register `MRCC_GLB_ACC2` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_ACC2` writer"] +pub type W = crate::W; +#[doc = "RAMA\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rama { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rama) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMA` reader - RAMA"] +pub type RamaR = crate::BitReader; +impl RamaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rama { + match self.bits { + false => Rama::Disabled, + true => Rama::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rama::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rama::Enabled + } +} +#[doc = "Field `RAMA` writer - RAMA"] +pub type RamaW<'a, REG> = crate::BitWriter<'a, REG, Rama>; +impl<'a, REG> RamaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rama::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rama::Enabled) + } +} +#[doc = "RAMB\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ramb { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ramb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMB` reader - RAMB"] +pub type RambR = crate::BitReader; +impl RambR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ramb { + match self.bits { + false => Ramb::Disabled, + true => Ramb::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ramb::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ramb::Enabled + } +} +#[doc = "Field `RAMB` writer - RAMB"] +pub type RambW<'a, REG> = crate::BitWriter<'a, REG, Ramb>; +impl<'a, REG> RambW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ramb::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ramb::Enabled) + } +} +#[doc = "RAMC\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ramc { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ramc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMC` reader - RAMC"] +pub type RamcR = crate::BitReader; +impl RamcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ramc { + match self.bits { + false => Ramc::Disabled, + true => Ramc::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ramc::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ramc::Enabled + } +} +#[doc = "Field `RAMC` writer - RAMC"] +pub type RamcW<'a, REG> = crate::BitWriter<'a, REG, Ramc>; +impl<'a, REG> RamcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ramc::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ramc::Enabled) + } +} +#[doc = "GPIO0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO0` reader - GPIO0"] +pub type Gpio0R = crate::BitReader; +impl Gpio0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio0 { + match self.bits { + false => Gpio0::Disabled, + true => Gpio0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio0::Enabled + } +} +#[doc = "Field `GPIO0` writer - GPIO0"] +pub type Gpio0W<'a, REG> = crate::BitWriter<'a, REG, Gpio0>; +impl<'a, REG> Gpio0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio0::Enabled) + } +} +#[doc = "GPIO1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio1 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO1` reader - GPIO1"] +pub type Gpio1R = crate::BitReader; +impl Gpio1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio1 { + match self.bits { + false => Gpio1::Disabled, + true => Gpio1::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio1::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio1::Enabled + } +} +#[doc = "Field `GPIO1` writer - GPIO1"] +pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG, Gpio1>; +impl<'a, REG> Gpio1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio1::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio1::Enabled) + } +} +#[doc = "GPIO2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio2 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO2` reader - GPIO2"] +pub type Gpio2R = crate::BitReader; +impl Gpio2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio2 { + match self.bits { + false => Gpio2::Disabled, + true => Gpio2::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio2::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio2::Enabled + } +} +#[doc = "Field `GPIO2` writer - GPIO2"] +pub type Gpio2W<'a, REG> = crate::BitWriter<'a, REG, Gpio2>; +impl<'a, REG> Gpio2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio2::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio2::Enabled) + } +} +#[doc = "GPIO3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio3 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO3` reader - GPIO3"] +pub type Gpio3R = crate::BitReader; +impl Gpio3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio3 { + match self.bits { + false => Gpio3::Disabled, + true => Gpio3::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio3::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio3::Enabled + } +} +#[doc = "Field `GPIO3` writer - GPIO3"] +pub type Gpio3W<'a, REG> = crate::BitWriter<'a, REG, Gpio3>; +impl<'a, REG> Gpio3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio3::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio3::Enabled) + } +} +#[doc = "GPIO4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio4 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO4` reader - GPIO4"] +pub type Gpio4R = crate::BitReader; +impl Gpio4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio4 { + match self.bits { + false => Gpio4::Disabled, + true => Gpio4::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio4::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio4::Enabled + } +} +#[doc = "Field `GPIO4` writer - GPIO4"] +pub type Gpio4W<'a, REG> = crate::BitWriter<'a, REG, Gpio4>; +impl<'a, REG> Gpio4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio4::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio4::Enabled) + } +} +#[doc = "MAU0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mau0 { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mau0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MAU0` reader - MAU0"] +pub type Mau0R = crate::BitReader; +impl Mau0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mau0 { + match self.bits { + false => Mau0::Disabled, + true => Mau0::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mau0::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mau0::Enabled + } +} +#[doc = "Field `MAU0` writer - MAU0"] +pub type Mau0W<'a, REG> = crate::BitWriter<'a, REG, Mau0>; +impl<'a, REG> Mau0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mau0::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mau0::Enabled) + } +} +#[doc = "ROMC\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Romc { + #[doc = "0: Automatic clock gating is disabled"] + Disabled = 0, + #[doc = "1: Automatic clock gating is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Romc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROMC` reader - ROMC"] +pub type RomcR = crate::BitReader; +impl RomcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Romc { + match self.bits { + false => Romc::Disabled, + true => Romc::Enabled, + } + } + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Romc::Disabled + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Romc::Enabled + } +} +#[doc = "Field `ROMC` writer - ROMC"] +pub type RomcW<'a, REG> = crate::BitWriter<'a, REG, Romc>; +impl<'a, REG> RomcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Automatic clock gating is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Romc::Disabled) + } + #[doc = "Automatic clock gating is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Romc::Enabled) + } +} +impl R { + #[doc = "Bit 1 - RAMA"] + #[inline(always)] + pub fn rama(&self) -> RamaR { + RamaR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RAMB"] + #[inline(always)] + pub fn ramb(&self) -> RambR { + RambR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RAMC"] + #[inline(always)] + pub fn ramc(&self) -> RamcR { + RamcR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - GPIO0"] + #[inline(always)] + pub fn gpio0(&self) -> Gpio0R { + Gpio0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - GPIO1"] + #[inline(always)] + pub fn gpio1(&self) -> Gpio1R { + Gpio1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - GPIO2"] + #[inline(always)] + pub fn gpio2(&self) -> Gpio2R { + Gpio2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - GPIO3"] + #[inline(always)] + pub fn gpio3(&self) -> Gpio3R { + Gpio3R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - GPIO4"] + #[inline(always)] + pub fn gpio4(&self) -> Gpio4R { + Gpio4R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MAU0"] + #[inline(always)] + pub fn mau0(&self) -> Mau0R { + Mau0R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - ROMC"] + #[inline(always)] + pub fn romc(&self) -> RomcR { + RomcR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - RAMA"] + #[inline(always)] + pub fn rama(&mut self) -> RamaW { + RamaW::new(self, 1) + } + #[doc = "Bit 2 - RAMB"] + #[inline(always)] + pub fn ramb(&mut self) -> RambW { + RambW::new(self, 2) + } + #[doc = "Bit 3 - RAMC"] + #[inline(always)] + pub fn ramc(&mut self) -> RamcW { + RamcW::new(self, 3) + } + #[doc = "Bit 4 - GPIO0"] + #[inline(always)] + pub fn gpio0(&mut self) -> Gpio0W { + Gpio0W::new(self, 4) + } + #[doc = "Bit 5 - GPIO1"] + #[inline(always)] + pub fn gpio1(&mut self) -> Gpio1W { + Gpio1W::new(self, 5) + } + #[doc = "Bit 6 - GPIO2"] + #[inline(always)] + pub fn gpio2(&mut self) -> Gpio2W { + Gpio2W::new(self, 6) + } + #[doc = "Bit 7 - GPIO3"] + #[inline(always)] + pub fn gpio3(&mut self) -> Gpio3W { + Gpio3W::new(self, 7) + } + #[doc = "Bit 8 - GPIO4"] + #[inline(always)] + pub fn gpio4(&mut self) -> Gpio4W { + Gpio4W::new(self, 8) + } + #[doc = "Bit 9 - MAU0"] + #[inline(always)] + pub fn mau0(&mut self) -> Mau0W { + Mau0W::new(self, 9) + } + #[doc = "Bit 10 - ROMC"] + #[inline(always)] + pub fn romc(&mut self) -> RomcW { + RomcW::new(self, 10) + } +} +#[doc = "Control Automatic Clock Gating 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbAcc2Spec; +impl crate::RegisterSpec for MrccGlbAcc2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_acc2::R`](R) reader structure"] +impl crate::Readable for MrccGlbAcc2Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc2::W`](W) writer structure"] +impl crate::Writable for MrccGlbAcc2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_ACC2 to value 0x040e"] +impl crate::Resettable for MrccGlbAcc2Spec { + const RESET_VALUE: u32 = 0x040e; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs new file mode 100644 index 000000000..68558c034 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs @@ -0,0 +1,2039 @@ +#[doc = "Register `MRCC_GLB_CC0` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_CC0` writer"] +pub type W = crate::W; +#[doc = "INPUTMUX0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inputmux0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inputmux0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INPUTMUX0` reader - INPUTMUX0"] +pub type Inputmux0R = crate::BitReader; +impl Inputmux0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inputmux0 { + match self.bits { + false => Inputmux0::Disabled, + true => Inputmux0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Inputmux0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Inputmux0::Enabled + } +} +#[doc = "Field `INPUTMUX0` writer - INPUTMUX0"] +pub type Inputmux0W<'a, REG> = crate::BitWriter<'a, REG, Inputmux0>; +impl<'a, REG> Inputmux0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Inputmux0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Inputmux0::Enabled) + } +} +#[doc = "I3C0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I3c0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I3c0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I3C0` reader - I3C0"] +pub type I3c0R = crate::BitReader; +impl I3c0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I3c0 { + match self.bits { + false => I3c0::Disabled, + true => I3c0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == I3c0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == I3c0::Enabled + } +} +#[doc = "Field `I3C0` writer - I3C0"] +pub type I3c0W<'a, REG> = crate::BitWriter<'a, REG, I3c0>; +impl<'a, REG> I3c0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(I3c0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(I3c0::Enabled) + } +} +#[doc = "CTIMER0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER0` reader - CTIMER0"] +pub type Ctimer0R = crate::BitReader; +impl Ctimer0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer0 { + match self.bits { + false => Ctimer0::Disabled, + true => Ctimer0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer0::Enabled + } +} +#[doc = "Field `CTIMER0` writer - CTIMER0"] +pub type Ctimer0W<'a, REG> = crate::BitWriter<'a, REG, Ctimer0>; +impl<'a, REG> Ctimer0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer0::Enabled) + } +} +#[doc = "CTIMER1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER1` reader - CTIMER1"] +pub type Ctimer1R = crate::BitReader; +impl Ctimer1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer1 { + match self.bits { + false => Ctimer1::Disabled, + true => Ctimer1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer1::Enabled + } +} +#[doc = "Field `CTIMER1` writer - CTIMER1"] +pub type Ctimer1W<'a, REG> = crate::BitWriter<'a, REG, Ctimer1>; +impl<'a, REG> Ctimer1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer1::Enabled) + } +} +#[doc = "CTIMER2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER2` reader - CTIMER2"] +pub type Ctimer2R = crate::BitReader; +impl Ctimer2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer2 { + match self.bits { + false => Ctimer2::Disabled, + true => Ctimer2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer2::Enabled + } +} +#[doc = "Field `CTIMER2` writer - CTIMER2"] +pub type Ctimer2W<'a, REG> = crate::BitWriter<'a, REG, Ctimer2>; +impl<'a, REG> Ctimer2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer2::Enabled) + } +} +#[doc = "CTIMER3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer3 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER3` reader - CTIMER3"] +pub type Ctimer3R = crate::BitReader; +impl Ctimer3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer3 { + match self.bits { + false => Ctimer3::Disabled, + true => Ctimer3::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer3::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer3::Enabled + } +} +#[doc = "Field `CTIMER3` writer - CTIMER3"] +pub type Ctimer3W<'a, REG> = crate::BitWriter<'a, REG, Ctimer3>; +impl<'a, REG> Ctimer3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer3::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer3::Enabled) + } +} +#[doc = "CTIMER4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer4 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER4` reader - CTIMER4"] +pub type Ctimer4R = crate::BitReader; +impl Ctimer4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer4 { + match self.bits { + false => Ctimer4::Disabled, + true => Ctimer4::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer4::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer4::Enabled + } +} +#[doc = "Field `CTIMER4` writer - CTIMER4"] +pub type Ctimer4W<'a, REG> = crate::BitWriter<'a, REG, Ctimer4>; +impl<'a, REG> Ctimer4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer4::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer4::Enabled) + } +} +#[doc = "FREQME\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Freqme { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Freqme) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FREQME` reader - FREQME"] +pub type FreqmeR = crate::BitReader; +impl FreqmeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Freqme { + match self.bits { + false => Freqme::Disabled, + true => Freqme::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Freqme::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Freqme::Enabled + } +} +#[doc = "Field `FREQME` writer - FREQME"] +pub type FreqmeW<'a, REG> = crate::BitWriter<'a, REG, Freqme>; +impl<'a, REG> FreqmeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Freqme::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Freqme::Enabled) + } +} +#[doc = "UTICK0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Utick0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Utick0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UTICK0` reader - UTICK0"] +pub type Utick0R = crate::BitReader; +impl Utick0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Utick0 { + match self.bits { + false => Utick0::Disabled, + true => Utick0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Utick0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Utick0::Enabled + } +} +#[doc = "Field `UTICK0` writer - UTICK0"] +pub type Utick0W<'a, REG> = crate::BitWriter<'a, REG, Utick0>; +impl<'a, REG> Utick0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Utick0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Utick0::Enabled) + } +} +#[doc = "WWDT0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wwdt0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wwdt0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WWDT0` reader - WWDT0"] +pub type Wwdt0R = crate::BitReader; +impl Wwdt0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wwdt0 { + match self.bits { + false => Wwdt0::Disabled, + true => Wwdt0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wwdt0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wwdt0::Enabled + } +} +#[doc = "Field `WWDT0` writer - WWDT0"] +pub type Wwdt0W<'a, REG> = crate::BitWriter<'a, REG, Wwdt0>; +impl<'a, REG> Wwdt0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wwdt0::Enabled) + } +} +#[doc = "SMARTDMA0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Smartdma0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Smartdma0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SMARTDMA0` reader - SMARTDMA0"] +pub type Smartdma0R = crate::BitReader; +impl Smartdma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Smartdma0 { + match self.bits { + false => Smartdma0::Disabled, + true => Smartdma0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Smartdma0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Smartdma0::Enabled + } +} +#[doc = "Field `SMARTDMA0` writer - SMARTDMA0"] +pub type Smartdma0W<'a, REG> = crate::BitWriter<'a, REG, Smartdma0>; +impl<'a, REG> Smartdma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Smartdma0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Smartdma0::Enabled) + } +} +#[doc = "DMA0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dma0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dma0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA0` reader - DMA0"] +pub type Dma0R = crate::BitReader; +impl Dma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dma0 { + match self.bits { + false => Dma0::Disabled, + true => Dma0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dma0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dma0::Enabled + } +} +#[doc = "Field `DMA0` writer - DMA0"] +pub type Dma0W<'a, REG> = crate::BitWriter<'a, REG, Dma0>; +impl<'a, REG> Dma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dma0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dma0::Enabled) + } +} +#[doc = "AOI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aoi0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aoi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AOI0` reader - AOI0"] +pub type Aoi0R = crate::BitReader; +impl Aoi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aoi0 { + match self.bits { + false => Aoi0::Disabled, + true => Aoi0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Aoi0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Aoi0::Enabled + } +} +#[doc = "Field `AOI0` writer - AOI0"] +pub type Aoi0W<'a, REG> = crate::BitWriter<'a, REG, Aoi0>; +impl<'a, REG> Aoi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Aoi0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Aoi0::Enabled) + } +} +#[doc = "CRC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crc0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRC0` reader - CRC0"] +pub type Crc0R = crate::BitReader; +impl Crc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crc0 { + match self.bits { + false => Crc0::Disabled, + true => Crc0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Crc0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Crc0::Enabled + } +} +#[doc = "Field `CRC0` writer - CRC0"] +pub type Crc0W<'a, REG> = crate::BitWriter<'a, REG, Crc0>; +impl<'a, REG> Crc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Crc0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Crc0::Enabled) + } +} +#[doc = "EIM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Eim0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Eim0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EIM0` reader - EIM0"] +pub type Eim0R = crate::BitReader; +impl Eim0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Eim0 { + match self.bits { + false => Eim0::Disabled, + true => Eim0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Eim0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Eim0::Enabled + } +} +#[doc = "Field `EIM0` writer - EIM0"] +pub type Eim0W<'a, REG> = crate::BitWriter<'a, REG, Eim0>; +impl<'a, REG> Eim0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Eim0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Eim0::Enabled) + } +} +#[doc = "ERM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erm0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erm0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERM0` reader - ERM0"] +pub type Erm0R = crate::BitReader; +impl Erm0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erm0 { + match self.bits { + false => Erm0::Disabled, + true => Erm0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Erm0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Erm0::Enabled + } +} +#[doc = "Field `ERM0` writer - ERM0"] +pub type Erm0W<'a, REG> = crate::BitWriter<'a, REG, Erm0>; +impl<'a, REG> Erm0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Erm0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Erm0::Enabled) + } +} +#[doc = "FMC\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fmc { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fmc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FMC` reader - FMC"] +pub type FmcR = crate::BitReader; +impl FmcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fmc { + match self.bits { + false => Fmc::Disabled, + true => Fmc::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fmc::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fmc::Enabled + } +} +#[doc = "Field `FMC` writer - FMC"] +pub type FmcW<'a, REG> = crate::BitWriter<'a, REG, Fmc>; +impl<'a, REG> FmcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fmc::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fmc::Enabled) + } +} +#[doc = "AOI1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aoi1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aoi1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AOI1` reader - AOI1"] +pub type Aoi1R = crate::BitReader; +impl Aoi1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aoi1 { + match self.bits { + false => Aoi1::Disabled, + true => Aoi1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Aoi1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Aoi1::Enabled + } +} +#[doc = "Field `AOI1` writer - AOI1"] +pub type Aoi1W<'a, REG> = crate::BitWriter<'a, REG, Aoi1>; +impl<'a, REG> Aoi1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Aoi1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Aoi1::Enabled) + } +} +#[doc = "FLEXIO0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexio0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexio0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXIO0` reader - FLEXIO0"] +pub type Flexio0R = crate::BitReader; +impl Flexio0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexio0 { + match self.bits { + false => Flexio0::Disabled, + true => Flexio0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexio0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexio0::Enabled + } +} +#[doc = "Field `FLEXIO0` writer - FLEXIO0"] +pub type Flexio0W<'a, REG> = crate::BitWriter<'a, REG, Flexio0>; +impl<'a, REG> Flexio0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexio0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexio0::Enabled) + } +} +#[doc = "LPI2C0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C0` reader - LPI2C0"] +pub type Lpi2c0R = crate::BitReader; +impl Lpi2c0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c0 { + match self.bits { + false => Lpi2c0::Disabled, + true => Lpi2c0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c0::Enabled + } +} +#[doc = "Field `LPI2C0` writer - LPI2C0"] +pub type Lpi2c0W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c0>; +impl<'a, REG> Lpi2c0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c0::Enabled) + } +} +#[doc = "LPI2C1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C1` reader - LPI2C1"] +pub type Lpi2c1R = crate::BitReader; +impl Lpi2c1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c1 { + match self.bits { + false => Lpi2c1::Disabled, + true => Lpi2c1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c1::Enabled + } +} +#[doc = "Field `LPI2C1` writer - LPI2C1"] +pub type Lpi2c1W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c1>; +impl<'a, REG> Lpi2c1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c1::Enabled) + } +} +#[doc = "LPSPI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpspi0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpspi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPSPI0` reader - LPSPI0"] +pub type Lpspi0R = crate::BitReader; +impl Lpspi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpspi0 { + match self.bits { + false => Lpspi0::Disabled, + true => Lpspi0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpspi0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpspi0::Enabled + } +} +#[doc = "Field `LPSPI0` writer - LPSPI0"] +pub type Lpspi0W<'a, REG> = crate::BitWriter<'a, REG, Lpspi0>; +impl<'a, REG> Lpspi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpspi0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpspi0::Enabled) + } +} +#[doc = "LPSPI1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpspi1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpspi1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPSPI1` reader - LPSPI1"] +pub type Lpspi1R = crate::BitReader; +impl Lpspi1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpspi1 { + match self.bits { + false => Lpspi1::Disabled, + true => Lpspi1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpspi1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpspi1::Enabled + } +} +#[doc = "Field `LPSPI1` writer - LPSPI1"] +pub type Lpspi1W<'a, REG> = crate::BitWriter<'a, REG, Lpspi1>; +impl<'a, REG> Lpspi1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpspi1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpspi1::Enabled) + } +} +#[doc = "LPUART0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART0` reader - LPUART0"] +pub type Lpuart0R = crate::BitReader; +impl Lpuart0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart0 { + match self.bits { + false => Lpuart0::Disabled, + true => Lpuart0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart0::Enabled + } +} +#[doc = "Field `LPUART0` writer - LPUART0"] +pub type Lpuart0W<'a, REG> = crate::BitWriter<'a, REG, Lpuart0>; +impl<'a, REG> Lpuart0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart0::Enabled) + } +} +#[doc = "LPUART1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART1` reader - LPUART1"] +pub type Lpuart1R = crate::BitReader; +impl Lpuart1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart1 { + match self.bits { + false => Lpuart1::Disabled, + true => Lpuart1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart1::Enabled + } +} +#[doc = "Field `LPUART1` writer - LPUART1"] +pub type Lpuart1W<'a, REG> = crate::BitWriter<'a, REG, Lpuart1>; +impl<'a, REG> Lpuart1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart1::Enabled) + } +} +#[doc = "LPUART2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART2` reader - LPUART2"] +pub type Lpuart2R = crate::BitReader; +impl Lpuart2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart2 { + match self.bits { + false => Lpuart2::Disabled, + true => Lpuart2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart2::Enabled + } +} +#[doc = "Field `LPUART2` writer - LPUART2"] +pub type Lpuart2W<'a, REG> = crate::BitWriter<'a, REG, Lpuart2>; +impl<'a, REG> Lpuart2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart2::Enabled) + } +} +#[doc = "LPUART3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart3 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART3` reader - LPUART3"] +pub type Lpuart3R = crate::BitReader; +impl Lpuart3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart3 { + match self.bits { + false => Lpuart3::Disabled, + true => Lpuart3::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart3::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart3::Enabled + } +} +#[doc = "Field `LPUART3` writer - LPUART3"] +pub type Lpuart3W<'a, REG> = crate::BitWriter<'a, REG, Lpuart3>; +impl<'a, REG> Lpuart3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart3::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart3::Enabled) + } +} +#[doc = "LPUART4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart4 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART4` reader - LPUART4"] +pub type Lpuart4R = crate::BitReader; +impl Lpuart4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart4 { + match self.bits { + false => Lpuart4::Disabled, + true => Lpuart4::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart4::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart4::Enabled + } +} +#[doc = "Field `LPUART4` writer - LPUART4"] +pub type Lpuart4W<'a, REG> = crate::BitWriter<'a, REG, Lpuart4>; +impl<'a, REG> Lpuart4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart4::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart4::Enabled) + } +} +#[doc = "USB0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usb0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usb0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USB0` reader - USB0"] +pub type Usb0R = crate::BitReader; +impl Usb0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Usb0 { + match self.bits { + false => Usb0::Disabled, + true => Usb0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Usb0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Usb0::Enabled + } +} +#[doc = "Field `USB0` writer - USB0"] +pub type Usb0W<'a, REG> = crate::BitWriter<'a, REG, Usb0>; +impl<'a, REG> Usb0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Usb0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Usb0::Enabled) + } +} +#[doc = "QDC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Qdc0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Qdc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `QDC0` reader - QDC0"] +pub type Qdc0R = crate::BitReader; +impl Qdc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Qdc0 { + match self.bits { + false => Qdc0::Disabled, + true => Qdc0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Qdc0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Qdc0::Enabled + } +} +#[doc = "Field `QDC0` writer - QDC0"] +pub type Qdc0W<'a, REG> = crate::BitWriter<'a, REG, Qdc0>; +impl<'a, REG> Qdc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Qdc0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Qdc0::Enabled) + } +} +#[doc = "QDC1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Qdc1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Qdc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `QDC1` reader - QDC1"] +pub type Qdc1R = crate::BitReader; +impl Qdc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Qdc1 { + match self.bits { + false => Qdc1::Disabled, + true => Qdc1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Qdc1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Qdc1::Enabled + } +} +#[doc = "Field `QDC1` writer - QDC1"] +pub type Qdc1W<'a, REG> = crate::BitWriter<'a, REG, Qdc1>; +impl<'a, REG> Qdc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Qdc1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Qdc1::Enabled) + } +} +#[doc = "FLEXPWM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexpwm0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexpwm0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXPWM0` reader - FLEXPWM0"] +pub type Flexpwm0R = crate::BitReader; +impl Flexpwm0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexpwm0 { + match self.bits { + false => Flexpwm0::Disabled, + true => Flexpwm0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexpwm0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexpwm0::Enabled + } +} +#[doc = "Field `FLEXPWM0` writer - FLEXPWM0"] +pub type Flexpwm0W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm0>; +impl<'a, REG> Flexpwm0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexpwm0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexpwm0::Enabled) + } +} +impl R { + #[doc = "Bit 0 - INPUTMUX0"] + #[inline(always)] + pub fn inputmux0(&self) -> Inputmux0R { + Inputmux0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I3C0"] + #[inline(always)] + pub fn i3c0(&self) -> I3c0R { + I3c0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTIMER0"] + #[inline(always)] + pub fn ctimer0(&self) -> Ctimer0R { + Ctimer0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - CTIMER1"] + #[inline(always)] + pub fn ctimer1(&self) -> Ctimer1R { + Ctimer1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - CTIMER2"] + #[inline(always)] + pub fn ctimer2(&self) -> Ctimer2R { + Ctimer2R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - CTIMER3"] + #[inline(always)] + pub fn ctimer3(&self) -> Ctimer3R { + Ctimer3R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - CTIMER4"] + #[inline(always)] + pub fn ctimer4(&self) -> Ctimer4R { + Ctimer4R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FREQME"] + #[inline(always)] + pub fn freqme(&self) -> FreqmeR { + FreqmeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - UTICK0"] + #[inline(always)] + pub fn utick0(&self) -> Utick0R { + Utick0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - WWDT0"] + #[inline(always)] + pub fn wwdt0(&self) -> Wwdt0R { + Wwdt0R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SMARTDMA0"] + #[inline(always)] + pub fn smartdma0(&self) -> Smartdma0R { + Smartdma0R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DMA0"] + #[inline(always)] + pub fn dma0(&self) -> Dma0R { + Dma0R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - AOI0"] + #[inline(always)] + pub fn aoi0(&self) -> Aoi0R { + Aoi0R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - CRC0"] + #[inline(always)] + pub fn crc0(&self) -> Crc0R { + Crc0R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - EIM0"] + #[inline(always)] + pub fn eim0(&self) -> Eim0R { + Eim0R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - ERM0"] + #[inline(always)] + pub fn erm0(&self) -> Erm0R { + Erm0R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - FMC"] + #[inline(always)] + pub fn fmc(&self) -> FmcR { + FmcR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - AOI1"] + #[inline(always)] + pub fn aoi1(&self) -> Aoi1R { + Aoi1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - FLEXIO0"] + #[inline(always)] + pub fn flexio0(&self) -> Flexio0R { + Flexio0R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - LPI2C0"] + #[inline(always)] + pub fn lpi2c0(&self) -> Lpi2c0R { + Lpi2c0R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LPI2C1"] + #[inline(always)] + pub fn lpi2c1(&self) -> Lpi2c1R { + Lpi2c1R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LPSPI0"] + #[inline(always)] + pub fn lpspi0(&self) -> Lpspi0R { + Lpspi0R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LPSPI1"] + #[inline(always)] + pub fn lpspi1(&self) -> Lpspi1R { + Lpspi1R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - LPUART0"] + #[inline(always)] + pub fn lpuart0(&self) -> Lpuart0R { + Lpuart0R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - LPUART1"] + #[inline(always)] + pub fn lpuart1(&self) -> Lpuart1R { + Lpuart1R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - LPUART2"] + #[inline(always)] + pub fn lpuart2(&self) -> Lpuart2R { + Lpuart2R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - LPUART3"] + #[inline(always)] + pub fn lpuart3(&self) -> Lpuart3R { + Lpuart3R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LPUART4"] + #[inline(always)] + pub fn lpuart4(&self) -> Lpuart4R { + Lpuart4R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - USB0"] + #[inline(always)] + pub fn usb0(&self) -> Usb0R { + Usb0R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - QDC0"] + #[inline(always)] + pub fn qdc0(&self) -> Qdc0R { + Qdc0R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - QDC1"] + #[inline(always)] + pub fn qdc1(&self) -> Qdc1R { + Qdc1R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - FLEXPWM0"] + #[inline(always)] + pub fn flexpwm0(&self) -> Flexpwm0R { + Flexpwm0R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - INPUTMUX0"] + #[inline(always)] + pub fn inputmux0(&mut self) -> Inputmux0W { + Inputmux0W::new(self, 0) + } + #[doc = "Bit 1 - I3C0"] + #[inline(always)] + pub fn i3c0(&mut self) -> I3c0W { + I3c0W::new(self, 1) + } + #[doc = "Bit 2 - CTIMER0"] + #[inline(always)] + pub fn ctimer0(&mut self) -> Ctimer0W { + Ctimer0W::new(self, 2) + } + #[doc = "Bit 3 - CTIMER1"] + #[inline(always)] + pub fn ctimer1(&mut self) -> Ctimer1W { + Ctimer1W::new(self, 3) + } + #[doc = "Bit 4 - CTIMER2"] + #[inline(always)] + pub fn ctimer2(&mut self) -> Ctimer2W { + Ctimer2W::new(self, 4) + } + #[doc = "Bit 5 - CTIMER3"] + #[inline(always)] + pub fn ctimer3(&mut self) -> Ctimer3W { + Ctimer3W::new(self, 5) + } + #[doc = "Bit 6 - CTIMER4"] + #[inline(always)] + pub fn ctimer4(&mut self) -> Ctimer4W { + Ctimer4W::new(self, 6) + } + #[doc = "Bit 7 - FREQME"] + #[inline(always)] + pub fn freqme(&mut self) -> FreqmeW { + FreqmeW::new(self, 7) + } + #[doc = "Bit 8 - UTICK0"] + #[inline(always)] + pub fn utick0(&mut self) -> Utick0W { + Utick0W::new(self, 8) + } + #[doc = "Bit 9 - WWDT0"] + #[inline(always)] + pub fn wwdt0(&mut self) -> Wwdt0W { + Wwdt0W::new(self, 9) + } + #[doc = "Bit 10 - SMARTDMA0"] + #[inline(always)] + pub fn smartdma0(&mut self) -> Smartdma0W { + Smartdma0W::new(self, 10) + } + #[doc = "Bit 11 - DMA0"] + #[inline(always)] + pub fn dma0(&mut self) -> Dma0W { + Dma0W::new(self, 11) + } + #[doc = "Bit 12 - AOI0"] + #[inline(always)] + pub fn aoi0(&mut self) -> Aoi0W { + Aoi0W::new(self, 12) + } + #[doc = "Bit 13 - CRC0"] + #[inline(always)] + pub fn crc0(&mut self) -> Crc0W { + Crc0W::new(self, 13) + } + #[doc = "Bit 14 - EIM0"] + #[inline(always)] + pub fn eim0(&mut self) -> Eim0W { + Eim0W::new(self, 14) + } + #[doc = "Bit 15 - ERM0"] + #[inline(always)] + pub fn erm0(&mut self) -> Erm0W { + Erm0W::new(self, 15) + } + #[doc = "Bit 16 - FMC"] + #[inline(always)] + pub fn fmc(&mut self) -> FmcW { + FmcW::new(self, 16) + } + #[doc = "Bit 17 - AOI1"] + #[inline(always)] + pub fn aoi1(&mut self) -> Aoi1W { + Aoi1W::new(self, 17) + } + #[doc = "Bit 18 - FLEXIO0"] + #[inline(always)] + pub fn flexio0(&mut self) -> Flexio0W { + Flexio0W::new(self, 18) + } + #[doc = "Bit 19 - LPI2C0"] + #[inline(always)] + pub fn lpi2c0(&mut self) -> Lpi2c0W { + Lpi2c0W::new(self, 19) + } + #[doc = "Bit 20 - LPI2C1"] + #[inline(always)] + pub fn lpi2c1(&mut self) -> Lpi2c1W { + Lpi2c1W::new(self, 20) + } + #[doc = "Bit 21 - LPSPI0"] + #[inline(always)] + pub fn lpspi0(&mut self) -> Lpspi0W { + Lpspi0W::new(self, 21) + } + #[doc = "Bit 22 - LPSPI1"] + #[inline(always)] + pub fn lpspi1(&mut self) -> Lpspi1W { + Lpspi1W::new(self, 22) + } + #[doc = "Bit 23 - LPUART0"] + #[inline(always)] + pub fn lpuart0(&mut self) -> Lpuart0W { + Lpuart0W::new(self, 23) + } + #[doc = "Bit 24 - LPUART1"] + #[inline(always)] + pub fn lpuart1(&mut self) -> Lpuart1W { + Lpuart1W::new(self, 24) + } + #[doc = "Bit 25 - LPUART2"] + #[inline(always)] + pub fn lpuart2(&mut self) -> Lpuart2W { + Lpuart2W::new(self, 25) + } + #[doc = "Bit 26 - LPUART3"] + #[inline(always)] + pub fn lpuart3(&mut self) -> Lpuart3W { + Lpuart3W::new(self, 26) + } + #[doc = "Bit 27 - LPUART4"] + #[inline(always)] + pub fn lpuart4(&mut self) -> Lpuart4W { + Lpuart4W::new(self, 27) + } + #[doc = "Bit 28 - USB0"] + #[inline(always)] + pub fn usb0(&mut self) -> Usb0W { + Usb0W::new(self, 28) + } + #[doc = "Bit 29 - QDC0"] + #[inline(always)] + pub fn qdc0(&mut self) -> Qdc0W { + Qdc0W::new(self, 29) + } + #[doc = "Bit 30 - QDC1"] + #[inline(always)] + pub fn qdc1(&mut self) -> Qdc1W { + Qdc1W::new(self, 30) + } + #[doc = "Bit 31 - FLEXPWM0"] + #[inline(always)] + pub fn flexpwm0(&mut self) -> Flexpwm0W { + Flexpwm0W::new(self, 31) + } +} +#[doc = "AHB Clock Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc0Spec; +impl crate::RegisterSpec for MrccGlbCc0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_cc0::R`](R) reader structure"] +impl crate::Readable for MrccGlbCc0Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc0::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC0 to value 0x0001_0000"] +impl crate::Resettable for MrccGlbCc0Spec { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs new file mode 100644 index 000000000..9a46b4928 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs @@ -0,0 +1,24 @@ +#[doc = "Register `MRCC_GLB_CC0_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "AHB Clock Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc0ClrSpec; +impl crate::RegisterSpec for MrccGlbCc0ClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc0_clr::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc0ClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC0_CLR to value 0x0001_0000"] +impl crate::Resettable for MrccGlbCc0ClrSpec { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs new file mode 100644 index 000000000..a328615de --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs @@ -0,0 +1,24 @@ +#[doc = "Register `MRCC_GLB_CC0_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "AHB Clock Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc0SetSpec; +impl crate::RegisterSpec for MrccGlbCc0SetSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc0_set::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc0SetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC0_SET to value 0x0001_0000"] +impl crate::Resettable for MrccGlbCc0SetSpec { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs new file mode 100644 index 000000000..5d7971822 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs @@ -0,0 +1,1911 @@ +#[doc = "Register `MRCC_GLB_CC1` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_CC1` writer"] +pub type W = crate::W; +#[doc = "FLEXPWM1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexpwm1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexpwm1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXPWM1` reader - FLEXPWM1"] +pub type Flexpwm1R = crate::BitReader; +impl Flexpwm1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexpwm1 { + match self.bits { + false => Flexpwm1::Disabled, + true => Flexpwm1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexpwm1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexpwm1::Enabled + } +} +#[doc = "Field `FLEXPWM1` writer - FLEXPWM1"] +pub type Flexpwm1W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm1>; +impl<'a, REG> Flexpwm1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexpwm1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexpwm1::Enabled) + } +} +#[doc = "OSTIMER0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ostimer0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ostimer0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSTIMER0` reader - OSTIMER0"] +pub type Ostimer0R = crate::BitReader; +impl Ostimer0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ostimer0 { + match self.bits { + false => Ostimer0::Disabled, + true => Ostimer0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ostimer0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ostimer0::Enabled + } +} +#[doc = "Field `OSTIMER0` writer - OSTIMER0"] +pub type Ostimer0W<'a, REG> = crate::BitWriter<'a, REG, Ostimer0>; +impl<'a, REG> Ostimer0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ostimer0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ostimer0::Enabled) + } +} +#[doc = "ADC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC0` reader - ADC0"] +pub type Adc0R = crate::BitReader; +impl Adc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc0 { + match self.bits { + false => Adc0::Disabled, + true => Adc0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc0::Enabled + } +} +#[doc = "Field `ADC0` writer - ADC0"] +pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG, Adc0>; +impl<'a, REG> Adc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc0::Enabled) + } +} +#[doc = "ADC1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC1` reader - ADC1"] +pub type Adc1R = crate::BitReader; +impl Adc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc1 { + match self.bits { + false => Adc1::Disabled, + true => Adc1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc1::Enabled + } +} +#[doc = "Field `ADC1` writer - ADC1"] +pub type Adc1W<'a, REG> = crate::BitWriter<'a, REG, Adc1>; +impl<'a, REG> Adc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc1::Enabled) + } +} +#[doc = "CMP0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP0` reader - CMP0"] +pub type Cmp0R = crate::BitReader; +impl Cmp0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp0 { + match self.bits { + false => Cmp0::Disabled, + true => Cmp0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp0::Enabled + } +} +#[doc = "Field `CMP0` writer - CMP0"] +pub type Cmp0W<'a, REG> = crate::BitWriter<'a, REG, Cmp0>; +impl<'a, REG> Cmp0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp0::Enabled) + } +} +#[doc = "CMP1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP1` reader - CMP1"] +pub type Cmp1R = crate::BitReader; +impl Cmp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp1 { + match self.bits { + false => Cmp1::Disabled, + true => Cmp1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp1::Enabled + } +} +#[doc = "Field `CMP1` writer - CMP1"] +pub type Cmp1W<'a, REG> = crate::BitWriter<'a, REG, Cmp1>; +impl<'a, REG> Cmp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp1::Enabled) + } +} +#[doc = "CMP2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP2` reader - CMP2"] +pub type Cmp2R = crate::BitReader; +impl Cmp2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp2 { + match self.bits { + false => Cmp2::Disabled, + true => Cmp2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp2::Enabled + } +} +#[doc = "Field `CMP2` writer - CMP2"] +pub type Cmp2W<'a, REG> = crate::BitWriter<'a, REG, Cmp2>; +impl<'a, REG> Cmp2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp2::Enabled) + } +} +#[doc = "DAC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dac0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dac0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAC0` reader - DAC0"] +pub type Dac0R = crate::BitReader; +impl Dac0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dac0 { + match self.bits { + false => Dac0::Disabled, + true => Dac0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dac0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dac0::Enabled + } +} +#[doc = "Field `DAC0` writer - DAC0"] +pub type Dac0W<'a, REG> = crate::BitWriter<'a, REG, Dac0>; +impl<'a, REG> Dac0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dac0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dac0::Enabled) + } +} +#[doc = "OPAMP0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP0` reader - OPAMP0"] +pub type Opamp0R = crate::BitReader; +impl Opamp0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp0 { + match self.bits { + false => Opamp0::Disabled, + true => Opamp0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp0::Enabled + } +} +#[doc = "Field `OPAMP0` writer - OPAMP0"] +pub type Opamp0W<'a, REG> = crate::BitWriter<'a, REG, Opamp0>; +impl<'a, REG> Opamp0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp0::Enabled) + } +} +#[doc = "OPAMP1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP1` reader - OPAMP1"] +pub type Opamp1R = crate::BitReader; +impl Opamp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp1 { + match self.bits { + false => Opamp1::Disabled, + true => Opamp1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp1::Enabled + } +} +#[doc = "Field `OPAMP1` writer - OPAMP1"] +pub type Opamp1W<'a, REG> = crate::BitWriter<'a, REG, Opamp1>; +impl<'a, REG> Opamp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp1::Enabled) + } +} +#[doc = "OPAMP2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP2` reader - OPAMP2"] +pub type Opamp2R = crate::BitReader; +impl Opamp2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp2 { + match self.bits { + false => Opamp2::Disabled, + true => Opamp2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp2::Enabled + } +} +#[doc = "Field `OPAMP2` writer - OPAMP2"] +pub type Opamp2W<'a, REG> = crate::BitWriter<'a, REG, Opamp2>; +impl<'a, REG> Opamp2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp2::Enabled) + } +} +#[doc = "OPAMP3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp3 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP3` reader - OPAMP3"] +pub type Opamp3R = crate::BitReader; +impl Opamp3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp3 { + match self.bits { + false => Opamp3::Disabled, + true => Opamp3::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp3::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp3::Enabled + } +} +#[doc = "Field `OPAMP3` writer - OPAMP3"] +pub type Opamp3W<'a, REG> = crate::BitWriter<'a, REG, Opamp3>; +impl<'a, REG> Opamp3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp3::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp3::Enabled) + } +} +#[doc = "PORT0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT0` reader - PORT0"] +pub type Port0R = crate::BitReader; +impl Port0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port0 { + match self.bits { + false => Port0::Disabled, + true => Port0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port0::Enabled + } +} +#[doc = "Field `PORT0` writer - PORT0"] +pub type Port0W<'a, REG> = crate::BitWriter<'a, REG, Port0>; +impl<'a, REG> Port0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port0::Enabled) + } +} +#[doc = "PORT1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT1` reader - PORT1"] +pub type Port1R = crate::BitReader; +impl Port1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port1 { + match self.bits { + false => Port1::Disabled, + true => Port1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port1::Enabled + } +} +#[doc = "Field `PORT1` writer - PORT1"] +pub type Port1W<'a, REG> = crate::BitWriter<'a, REG, Port1>; +impl<'a, REG> Port1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port1::Enabled) + } +} +#[doc = "PORT2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT2` reader - PORT2"] +pub type Port2R = crate::BitReader; +impl Port2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port2 { + match self.bits { + false => Port2::Disabled, + true => Port2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port2::Enabled + } +} +#[doc = "Field `PORT2` writer - PORT2"] +pub type Port2W<'a, REG> = crate::BitWriter<'a, REG, Port2>; +impl<'a, REG> Port2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port2::Enabled) + } +} +#[doc = "PORT3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port3 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT3` reader - PORT3"] +pub type Port3R = crate::BitReader; +impl Port3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port3 { + match self.bits { + false => Port3::Disabled, + true => Port3::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port3::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port3::Enabled + } +} +#[doc = "Field `PORT3` writer - PORT3"] +pub type Port3W<'a, REG> = crate::BitWriter<'a, REG, Port3>; +impl<'a, REG> Port3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port3::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port3::Enabled) + } +} +#[doc = "PORT4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port4 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT4` reader - PORT4"] +pub type Port4R = crate::BitReader; +impl Port4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port4 { + match self.bits { + false => Port4::Disabled, + true => Port4::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port4::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port4::Enabled + } +} +#[doc = "Field `PORT4` writer - PORT4"] +pub type Port4W<'a, REG> = crate::BitWriter<'a, REG, Port4>; +impl<'a, REG> Port4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port4::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port4::Enabled) + } +} +#[doc = "SLCD0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slcd0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slcd0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLCD0` reader - SLCD0"] +pub type Slcd0R = crate::BitReader; +impl Slcd0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slcd0 { + match self.bits { + false => Slcd0::Disabled, + true => Slcd0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Slcd0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Slcd0::Enabled + } +} +#[doc = "Field `SLCD0` writer - SLCD0"] +pub type Slcd0W<'a, REG> = crate::BitWriter<'a, REG, Slcd0>; +impl<'a, REG> Slcd0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Slcd0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Slcd0::Enabled) + } +} +#[doc = "FLEXCAN0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexcan0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexcan0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXCAN0` reader - FLEXCAN0"] +pub type Flexcan0R = crate::BitReader; +impl Flexcan0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexcan0 { + match self.bits { + false => Flexcan0::Disabled, + true => Flexcan0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexcan0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexcan0::Enabled + } +} +#[doc = "Field `FLEXCAN0` writer - FLEXCAN0"] +pub type Flexcan0W<'a, REG> = crate::BitWriter<'a, REG, Flexcan0>; +impl<'a, REG> Flexcan0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexcan0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexcan0::Enabled) + } +} +#[doc = "FLEXCAN1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexcan1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexcan1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXCAN1` reader - FLEXCAN1"] +pub type Flexcan1R = crate::BitReader; +impl Flexcan1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexcan1 { + match self.bits { + false => Flexcan1::Disabled, + true => Flexcan1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexcan1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexcan1::Enabled + } +} +#[doc = "Field `FLEXCAN1` writer - FLEXCAN1"] +pub type Flexcan1W<'a, REG> = crate::BitWriter<'a, REG, Flexcan1>; +impl<'a, REG> Flexcan1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexcan1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexcan1::Enabled) + } +} +#[doc = "LPI2C2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C2` reader - LPI2C2"] +pub type Lpi2c2R = crate::BitReader; +impl Lpi2c2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c2 { + match self.bits { + false => Lpi2c2::Disabled, + true => Lpi2c2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c2::Enabled + } +} +#[doc = "Field `LPI2C2` writer - LPI2C2"] +pub type Lpi2c2W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c2>; +impl<'a, REG> Lpi2c2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c2::Enabled) + } +} +#[doc = "LPI2C3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c3 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C3` reader - LPI2C3"] +pub type Lpi2c3R = crate::BitReader; +impl Lpi2c3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c3 { + match self.bits { + false => Lpi2c3::Disabled, + true => Lpi2c3::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c3::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c3::Enabled + } +} +#[doc = "Field `LPI2C3` writer - LPI2C3"] +pub type Lpi2c3W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c3>; +impl<'a, REG> Lpi2c3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c3::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c3::Enabled) + } +} +#[doc = "LPUART5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart5 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART5` reader - LPUART5"] +pub type Lpuart5R = crate::BitReader; +impl Lpuart5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart5 { + match self.bits { + false => Lpuart5::Disabled, + true => Lpuart5::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart5::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart5::Enabled + } +} +#[doc = "Field `LPUART5` writer - LPUART5"] +pub type Lpuart5W<'a, REG> = crate::BitWriter<'a, REG, Lpuart5>; +impl<'a, REG> Lpuart5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart5::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart5::Enabled) + } +} +#[doc = "TDET0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tdet0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tdet0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDET0` reader - TDET0"] +pub type Tdet0R = crate::BitReader; +impl Tdet0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tdet0 { + match self.bits { + false => Tdet0::Disabled, + true => Tdet0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Tdet0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Tdet0::Enabled + } +} +#[doc = "Field `TDET0` writer - TDET0"] +pub type Tdet0W<'a, REG> = crate::BitWriter<'a, REG, Tdet0>; +impl<'a, REG> Tdet0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Tdet0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Tdet0::Enabled) + } +} +#[doc = "PKC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pkc0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pkc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PKC0` reader - PKC0"] +pub type Pkc0R = crate::BitReader; +impl Pkc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pkc0 { + match self.bits { + false => Pkc0::Disabled, + true => Pkc0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pkc0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pkc0::Enabled + } +} +#[doc = "Field `PKC0` writer - PKC0"] +pub type Pkc0W<'a, REG> = crate::BitWriter<'a, REG, Pkc0>; +impl<'a, REG> Pkc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pkc0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pkc0::Enabled) + } +} +#[doc = "SGI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sgi0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sgi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SGI0` reader - SGI0"] +pub type Sgi0R = crate::BitReader; +impl Sgi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sgi0 { + match self.bits { + false => Sgi0::Disabled, + true => Sgi0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sgi0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sgi0::Enabled + } +} +#[doc = "Field `SGI0` writer - SGI0"] +pub type Sgi0W<'a, REG> = crate::BitWriter<'a, REG, Sgi0>; +impl<'a, REG> Sgi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sgi0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sgi0::Enabled) + } +} +#[doc = "TRNG0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trng0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trng0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRNG0` reader - TRNG0"] +pub type Trng0R = crate::BitReader; +impl Trng0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trng0 { + match self.bits { + false => Trng0::Disabled, + true => Trng0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Trng0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Trng0::Enabled + } +} +#[doc = "Field `TRNG0` writer - TRNG0"] +pub type Trng0W<'a, REG> = crate::BitWriter<'a, REG, Trng0>; +impl<'a, REG> Trng0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Trng0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Trng0::Enabled) + } +} +#[doc = "UDF0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Udf0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Udf0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UDF0` reader - UDF0"] +pub type Udf0R = crate::BitReader; +impl Udf0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Udf0 { + match self.bits { + false => Udf0::Disabled, + true => Udf0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Udf0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Udf0::Enabled + } +} +#[doc = "Field `UDF0` writer - UDF0"] +pub type Udf0W<'a, REG> = crate::BitWriter<'a, REG, Udf0>; +impl<'a, REG> Udf0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Udf0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Udf0::Enabled) + } +} +#[doc = "ADC2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC2` reader - ADC2"] +pub type Adc2R = crate::BitReader; +impl Adc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc2 { + match self.bits { + false => Adc2::Disabled, + true => Adc2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc2::Enabled + } +} +#[doc = "Field `ADC2` writer - ADC2"] +pub type Adc2W<'a, REG> = crate::BitWriter<'a, REG, Adc2>; +impl<'a, REG> Adc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc2::Enabled) + } +} +#[doc = "ADC3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc3 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC3` reader - ADC3"] +pub type Adc3R = crate::BitReader; +impl Adc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc3 { + match self.bits { + false => Adc3::Disabled, + true => Adc3::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc3::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc3::Enabled + } +} +#[doc = "Field `ADC3` writer - ADC3"] +pub type Adc3W<'a, REG> = crate::BitWriter<'a, REG, Adc3>; +impl<'a, REG> Adc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc3::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc3::Enabled) + } +} +impl R { + #[doc = "Bit 0 - FLEXPWM1"] + #[inline(always)] + pub fn flexpwm1(&self) -> Flexpwm1R { + Flexpwm1R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - OSTIMER0"] + #[inline(always)] + pub fn ostimer0(&self) -> Ostimer0R { + Ostimer0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - ADC0"] + #[inline(always)] + pub fn adc0(&self) -> Adc0R { + Adc0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ADC1"] + #[inline(always)] + pub fn adc1(&self) -> Adc1R { + Adc1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - CMP0"] + #[inline(always)] + pub fn cmp0(&self) -> Cmp0R { + Cmp0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - CMP1"] + #[inline(always)] + pub fn cmp1(&self) -> Cmp1R { + Cmp1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - CMP2"] + #[inline(always)] + pub fn cmp2(&self) -> Cmp2R { + Cmp2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - DAC0"] + #[inline(always)] + pub fn dac0(&self) -> Dac0R { + Dac0R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - OPAMP0"] + #[inline(always)] + pub fn opamp0(&self) -> Opamp0R { + Opamp0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - OPAMP1"] + #[inline(always)] + pub fn opamp1(&self) -> Opamp1R { + Opamp1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OPAMP2"] + #[inline(always)] + pub fn opamp2(&self) -> Opamp2R { + Opamp2R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - OPAMP3"] + #[inline(always)] + pub fn opamp3(&self) -> Opamp3R { + Opamp3R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - PORT0"] + #[inline(always)] + pub fn port0(&self) -> Port0R { + Port0R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - PORT1"] + #[inline(always)] + pub fn port1(&self) -> Port1R { + Port1R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PORT2"] + #[inline(always)] + pub fn port2(&self) -> Port2R { + Port2R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - PORT3"] + #[inline(always)] + pub fn port3(&self) -> Port3R { + Port3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - PORT4"] + #[inline(always)] + pub fn port4(&self) -> Port4R { + Port4R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SLCD0"] + #[inline(always)] + pub fn slcd0(&self) -> Slcd0R { + Slcd0R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - FLEXCAN0"] + #[inline(always)] + pub fn flexcan0(&self) -> Flexcan0R { + Flexcan0R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - FLEXCAN1"] + #[inline(always)] + pub fn flexcan1(&self) -> Flexcan1R { + Flexcan1R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LPI2C2"] + #[inline(always)] + pub fn lpi2c2(&self) -> Lpi2c2R { + Lpi2c2R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LPI2C3"] + #[inline(always)] + pub fn lpi2c3(&self) -> Lpi2c3R { + Lpi2c3R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LPUART5"] + #[inline(always)] + pub fn lpuart5(&self) -> Lpuart5R { + Lpuart5R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - TDET0"] + #[inline(always)] + pub fn tdet0(&self) -> Tdet0R { + Tdet0R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - PKC0"] + #[inline(always)] + pub fn pkc0(&self) -> Pkc0R { + Pkc0R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - SGI0"] + #[inline(always)] + pub fn sgi0(&self) -> Sgi0R { + Sgi0R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - TRNG0"] + #[inline(always)] + pub fn trng0(&self) -> Trng0R { + Trng0R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - UDF0"] + #[inline(always)] + pub fn udf0(&self) -> Udf0R { + Udf0R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - ADC2"] + #[inline(always)] + pub fn adc2(&self) -> Adc2R { + Adc2R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - ADC3"] + #[inline(always)] + pub fn adc3(&self) -> Adc3R { + Adc3R::new(((self.bits >> 29) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLEXPWM1"] + #[inline(always)] + pub fn flexpwm1(&mut self) -> Flexpwm1W { + Flexpwm1W::new(self, 0) + } + #[doc = "Bit 1 - OSTIMER0"] + #[inline(always)] + pub fn ostimer0(&mut self) -> Ostimer0W { + Ostimer0W::new(self, 1) + } + #[doc = "Bit 2 - ADC0"] + #[inline(always)] + pub fn adc0(&mut self) -> Adc0W { + Adc0W::new(self, 2) + } + #[doc = "Bit 3 - ADC1"] + #[inline(always)] + pub fn adc1(&mut self) -> Adc1W { + Adc1W::new(self, 3) + } + #[doc = "Bit 4 - CMP0"] + #[inline(always)] + pub fn cmp0(&mut self) -> Cmp0W { + Cmp0W::new(self, 4) + } + #[doc = "Bit 5 - CMP1"] + #[inline(always)] + pub fn cmp1(&mut self) -> Cmp1W { + Cmp1W::new(self, 5) + } + #[doc = "Bit 6 - CMP2"] + #[inline(always)] + pub fn cmp2(&mut self) -> Cmp2W { + Cmp2W::new(self, 6) + } + #[doc = "Bit 7 - DAC0"] + #[inline(always)] + pub fn dac0(&mut self) -> Dac0W { + Dac0W::new(self, 7) + } + #[doc = "Bit 8 - OPAMP0"] + #[inline(always)] + pub fn opamp0(&mut self) -> Opamp0W { + Opamp0W::new(self, 8) + } + #[doc = "Bit 9 - OPAMP1"] + #[inline(always)] + pub fn opamp1(&mut self) -> Opamp1W { + Opamp1W::new(self, 9) + } + #[doc = "Bit 10 - OPAMP2"] + #[inline(always)] + pub fn opamp2(&mut self) -> Opamp2W { + Opamp2W::new(self, 10) + } + #[doc = "Bit 11 - OPAMP3"] + #[inline(always)] + pub fn opamp3(&mut self) -> Opamp3W { + Opamp3W::new(self, 11) + } + #[doc = "Bit 12 - PORT0"] + #[inline(always)] + pub fn port0(&mut self) -> Port0W { + Port0W::new(self, 12) + } + #[doc = "Bit 13 - PORT1"] + #[inline(always)] + pub fn port1(&mut self) -> Port1W { + Port1W::new(self, 13) + } + #[doc = "Bit 14 - PORT2"] + #[inline(always)] + pub fn port2(&mut self) -> Port2W { + Port2W::new(self, 14) + } + #[doc = "Bit 15 - PORT3"] + #[inline(always)] + pub fn port3(&mut self) -> Port3W { + Port3W::new(self, 15) + } + #[doc = "Bit 16 - PORT4"] + #[inline(always)] + pub fn port4(&mut self) -> Port4W { + Port4W::new(self, 16) + } + #[doc = "Bit 17 - SLCD0"] + #[inline(always)] + pub fn slcd0(&mut self) -> Slcd0W { + Slcd0W::new(self, 17) + } + #[doc = "Bit 18 - FLEXCAN0"] + #[inline(always)] + pub fn flexcan0(&mut self) -> Flexcan0W { + Flexcan0W::new(self, 18) + } + #[doc = "Bit 19 - FLEXCAN1"] + #[inline(always)] + pub fn flexcan1(&mut self) -> Flexcan1W { + Flexcan1W::new(self, 19) + } + #[doc = "Bit 20 - LPI2C2"] + #[inline(always)] + pub fn lpi2c2(&mut self) -> Lpi2c2W { + Lpi2c2W::new(self, 20) + } + #[doc = "Bit 21 - LPI2C3"] + #[inline(always)] + pub fn lpi2c3(&mut self) -> Lpi2c3W { + Lpi2c3W::new(self, 21) + } + #[doc = "Bit 22 - LPUART5"] + #[inline(always)] + pub fn lpuart5(&mut self) -> Lpuart5W { + Lpuart5W::new(self, 22) + } + #[doc = "Bit 23 - TDET0"] + #[inline(always)] + pub fn tdet0(&mut self) -> Tdet0W { + Tdet0W::new(self, 23) + } + #[doc = "Bit 24 - PKC0"] + #[inline(always)] + pub fn pkc0(&mut self) -> Pkc0W { + Pkc0W::new(self, 24) + } + #[doc = "Bit 25 - SGI0"] + #[inline(always)] + pub fn sgi0(&mut self) -> Sgi0W { + Sgi0W::new(self, 25) + } + #[doc = "Bit 26 - TRNG0"] + #[inline(always)] + pub fn trng0(&mut self) -> Trng0W { + Trng0W::new(self, 26) + } + #[doc = "Bit 27 - UDF0"] + #[inline(always)] + pub fn udf0(&mut self) -> Udf0W { + Udf0W::new(self, 27) + } + #[doc = "Bit 28 - ADC2"] + #[inline(always)] + pub fn adc2(&mut self) -> Adc2W { + Adc2W::new(self, 28) + } + #[doc = "Bit 29 - ADC3"] + #[inline(always)] + pub fn adc3(&mut self) -> Adc3W { + Adc3W::new(self, 29) + } +} +#[doc = "AHB Clock Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc1Spec; +impl crate::RegisterSpec for MrccGlbCc1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_cc1::R`](R) reader structure"] +impl crate::Readable for MrccGlbCc1Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc1::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC1 to value 0"] +impl crate::Resettable for MrccGlbCc1Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs new file mode 100644 index 000000000..0e44ab54d --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_CC1_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "AHB Clock Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc1ClrSpec; +impl crate::RegisterSpec for MrccGlbCc1ClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc1_clr::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc1ClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC1_CLR to value 0"] +impl crate::Resettable for MrccGlbCc1ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs new file mode 100644 index 000000000..16204fd7c --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_CC1_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "AHB Clock Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc1SetSpec; +impl crate::RegisterSpec for MrccGlbCc1SetSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc1_set::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc1SetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC1_SET to value 0"] +impl crate::Resettable for MrccGlbCc1SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs new file mode 100644 index 000000000..de25d079c --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs @@ -0,0 +1,651 @@ +#[doc = "Register `MRCC_GLB_CC2` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_CC2` writer"] +pub type W = crate::W; +#[doc = "RAMA\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rama { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rama) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMA` reader - RAMA"] +pub type RamaR = crate::BitReader; +impl RamaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rama { + match self.bits { + false => Rama::Disabled, + true => Rama::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rama::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rama::Enabled + } +} +#[doc = "Field `RAMA` writer - RAMA"] +pub type RamaW<'a, REG> = crate::BitWriter<'a, REG, Rama>; +impl<'a, REG> RamaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rama::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rama::Enabled) + } +} +#[doc = "RAMB\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ramb { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ramb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMB` reader - RAMB"] +pub type RambR = crate::BitReader; +impl RambR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ramb { + match self.bits { + false => Ramb::Disabled, + true => Ramb::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ramb::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ramb::Enabled + } +} +#[doc = "Field `RAMB` writer - RAMB"] +pub type RambW<'a, REG> = crate::BitWriter<'a, REG, Ramb>; +impl<'a, REG> RambW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ramb::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ramb::Enabled) + } +} +#[doc = "RAMC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ramc { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ramc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMC` reader - RAMC"] +pub type RamcR = crate::BitReader; +impl RamcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ramc { + match self.bits { + false => Ramc::Disabled, + true => Ramc::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ramc::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ramc::Enabled + } +} +#[doc = "Field `RAMC` writer - RAMC"] +pub type RamcW<'a, REG> = crate::BitWriter<'a, REG, Ramc>; +impl<'a, REG> RamcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ramc::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ramc::Enabled) + } +} +#[doc = "GPIO0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO0` reader - GPIO0"] +pub type Gpio0R = crate::BitReader; +impl Gpio0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio0 { + match self.bits { + false => Gpio0::Disabled, + true => Gpio0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio0::Enabled + } +} +#[doc = "Field `GPIO0` writer - GPIO0"] +pub type Gpio0W<'a, REG> = crate::BitWriter<'a, REG, Gpio0>; +impl<'a, REG> Gpio0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio0::Enabled) + } +} +#[doc = "GPIO1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio1 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO1` reader - GPIO1"] +pub type Gpio1R = crate::BitReader; +impl Gpio1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio1 { + match self.bits { + false => Gpio1::Disabled, + true => Gpio1::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio1::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio1::Enabled + } +} +#[doc = "Field `GPIO1` writer - GPIO1"] +pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG, Gpio1>; +impl<'a, REG> Gpio1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio1::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio1::Enabled) + } +} +#[doc = "GPIO2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio2 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO2` reader - GPIO2"] +pub type Gpio2R = crate::BitReader; +impl Gpio2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio2 { + match self.bits { + false => Gpio2::Disabled, + true => Gpio2::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio2::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio2::Enabled + } +} +#[doc = "Field `GPIO2` writer - GPIO2"] +pub type Gpio2W<'a, REG> = crate::BitWriter<'a, REG, Gpio2>; +impl<'a, REG> Gpio2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio2::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio2::Enabled) + } +} +#[doc = "GPIO3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio3 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO3` reader - GPIO3"] +pub type Gpio3R = crate::BitReader; +impl Gpio3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio3 { + match self.bits { + false => Gpio3::Disabled, + true => Gpio3::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio3::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio3::Enabled + } +} +#[doc = "Field `GPIO3` writer - GPIO3"] +pub type Gpio3W<'a, REG> = crate::BitWriter<'a, REG, Gpio3>; +impl<'a, REG> Gpio3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio3::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio3::Enabled) + } +} +#[doc = "GPIO4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio4 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO4` reader - GPIO4"] +pub type Gpio4R = crate::BitReader; +impl Gpio4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio4 { + match self.bits { + false => Gpio4::Disabled, + true => Gpio4::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio4::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio4::Enabled + } +} +#[doc = "Field `GPIO4` writer - GPIO4"] +pub type Gpio4W<'a, REG> = crate::BitWriter<'a, REG, Gpio4>; +impl<'a, REG> Gpio4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio4::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio4::Enabled) + } +} +#[doc = "MAU0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mau0 { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mau0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MAU0` reader - MAU0"] +pub type Mau0R = crate::BitReader; +impl Mau0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mau0 { + match self.bits { + false => Mau0::Disabled, + true => Mau0::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mau0::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mau0::Enabled + } +} +#[doc = "Field `MAU0` writer - MAU0"] +pub type Mau0W<'a, REG> = crate::BitWriter<'a, REG, Mau0>; +impl<'a, REG> Mau0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mau0::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mau0::Enabled) + } +} +#[doc = "ROMC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Romc { + #[doc = "0: Peripheral clock is disabled"] + Disabled = 0, + #[doc = "1: Peripheral clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Romc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROMC` reader - ROMC"] +pub type RomcR = crate::BitReader; +impl RomcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Romc { + match self.bits { + false => Romc::Disabled, + true => Romc::Enabled, + } + } + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Romc::Disabled + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Romc::Enabled + } +} +#[doc = "Field `ROMC` writer - ROMC"] +pub type RomcW<'a, REG> = crate::BitWriter<'a, REG, Romc>; +impl<'a, REG> RomcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Romc::Disabled) + } + #[doc = "Peripheral clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Romc::Enabled) + } +} +impl R { + #[doc = "Bit 1 - RAMA"] + #[inline(always)] + pub fn rama(&self) -> RamaR { + RamaR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RAMB"] + #[inline(always)] + pub fn ramb(&self) -> RambR { + RambR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RAMC"] + #[inline(always)] + pub fn ramc(&self) -> RamcR { + RamcR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - GPIO0"] + #[inline(always)] + pub fn gpio0(&self) -> Gpio0R { + Gpio0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - GPIO1"] + #[inline(always)] + pub fn gpio1(&self) -> Gpio1R { + Gpio1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - GPIO2"] + #[inline(always)] + pub fn gpio2(&self) -> Gpio2R { + Gpio2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - GPIO3"] + #[inline(always)] + pub fn gpio3(&self) -> Gpio3R { + Gpio3R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - GPIO4"] + #[inline(always)] + pub fn gpio4(&self) -> Gpio4R { + Gpio4R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MAU0"] + #[inline(always)] + pub fn mau0(&self) -> Mau0R { + Mau0R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - ROMC"] + #[inline(always)] + pub fn romc(&self) -> RomcR { + RomcR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - RAMA"] + #[inline(always)] + pub fn rama(&mut self) -> RamaW { + RamaW::new(self, 1) + } + #[doc = "Bit 2 - RAMB"] + #[inline(always)] + pub fn ramb(&mut self) -> RambW { + RambW::new(self, 2) + } + #[doc = "Bit 3 - RAMC"] + #[inline(always)] + pub fn ramc(&mut self) -> RamcW { + RamcW::new(self, 3) + } + #[doc = "Bit 4 - GPIO0"] + #[inline(always)] + pub fn gpio0(&mut self) -> Gpio0W { + Gpio0W::new(self, 4) + } + #[doc = "Bit 5 - GPIO1"] + #[inline(always)] + pub fn gpio1(&mut self) -> Gpio1W { + Gpio1W::new(self, 5) + } + #[doc = "Bit 6 - GPIO2"] + #[inline(always)] + pub fn gpio2(&mut self) -> Gpio2W { + Gpio2W::new(self, 6) + } + #[doc = "Bit 7 - GPIO3"] + #[inline(always)] + pub fn gpio3(&mut self) -> Gpio3W { + Gpio3W::new(self, 7) + } + #[doc = "Bit 8 - GPIO4"] + #[inline(always)] + pub fn gpio4(&mut self) -> Gpio4W { + Gpio4W::new(self, 8) + } + #[doc = "Bit 9 - MAU0"] + #[inline(always)] + pub fn mau0(&mut self) -> Mau0W { + Mau0W::new(self, 9) + } + #[doc = "Bit 10 - ROMC"] + #[inline(always)] + pub fn romc(&mut self) -> RomcW { + RomcW::new(self, 10) + } +} +#[doc = "AHB Clock Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc2Spec; +impl crate::RegisterSpec for MrccGlbCc2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_cc2::R`](R) reader structure"] +impl crate::Readable for MrccGlbCc2Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc2::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC2 to value 0"] +impl crate::Resettable for MrccGlbCc2Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs new file mode 100644 index 000000000..2f8caa45c --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_CC2_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "AHB Clock Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc2ClrSpec; +impl crate::RegisterSpec for MrccGlbCc2ClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc2_clr::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc2ClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC2_CLR to value 0"] +impl crate::Resettable for MrccGlbCc2ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs new file mode 100644 index 000000000..43b9c0e8c --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_CC2_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "AHB Clock Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbCc2SetSpec; +impl crate::RegisterSpec for MrccGlbCc2SetSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc2_set::W`](W) writer structure"] +impl crate::Writable for MrccGlbCc2SetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_CC2_SET to value 0"] +impl crate::Resettable for MrccGlbCc2SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs new file mode 100644 index 000000000..de64c78ea --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs @@ -0,0 +1,1911 @@ +#[doc = "Register `MRCC_GLB_RST0` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_RST0` writer"] +pub type W = crate::W; +#[doc = "INPUTMUX0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inputmux0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inputmux0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INPUTMUX0` reader - INPUTMUX0"] +pub type Inputmux0R = crate::BitReader; +impl Inputmux0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inputmux0 { + match self.bits { + false => Inputmux0::Disabled, + true => Inputmux0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Inputmux0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Inputmux0::Enabled + } +} +#[doc = "Field `INPUTMUX0` writer - INPUTMUX0"] +pub type Inputmux0W<'a, REG> = crate::BitWriter<'a, REG, Inputmux0>; +impl<'a, REG> Inputmux0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Inputmux0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Inputmux0::Enabled) + } +} +#[doc = "I3C0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I3c0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I3c0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I3C0` reader - I3C0"] +pub type I3c0R = crate::BitReader; +impl I3c0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I3c0 { + match self.bits { + false => I3c0::Disabled, + true => I3c0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == I3c0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == I3c0::Enabled + } +} +#[doc = "Field `I3C0` writer - I3C0"] +pub type I3c0W<'a, REG> = crate::BitWriter<'a, REG, I3c0>; +impl<'a, REG> I3c0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(I3c0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(I3c0::Enabled) + } +} +#[doc = "CTIMER0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER0` reader - CTIMER0"] +pub type Ctimer0R = crate::BitReader; +impl Ctimer0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer0 { + match self.bits { + false => Ctimer0::Disabled, + true => Ctimer0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer0::Enabled + } +} +#[doc = "Field `CTIMER0` writer - CTIMER0"] +pub type Ctimer0W<'a, REG> = crate::BitWriter<'a, REG, Ctimer0>; +impl<'a, REG> Ctimer0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer0::Enabled) + } +} +#[doc = "CTIMER1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER1` reader - CTIMER1"] +pub type Ctimer1R = crate::BitReader; +impl Ctimer1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer1 { + match self.bits { + false => Ctimer1::Disabled, + true => Ctimer1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer1::Enabled + } +} +#[doc = "Field `CTIMER1` writer - CTIMER1"] +pub type Ctimer1W<'a, REG> = crate::BitWriter<'a, REG, Ctimer1>; +impl<'a, REG> Ctimer1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer1::Enabled) + } +} +#[doc = "CTIMER2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER2` reader - CTIMER2"] +pub type Ctimer2R = crate::BitReader; +impl Ctimer2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer2 { + match self.bits { + false => Ctimer2::Disabled, + true => Ctimer2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer2::Enabled + } +} +#[doc = "Field `CTIMER2` writer - CTIMER2"] +pub type Ctimer2W<'a, REG> = crate::BitWriter<'a, REG, Ctimer2>; +impl<'a, REG> Ctimer2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer2::Enabled) + } +} +#[doc = "CTIMER3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer3 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER3` reader - CTIMER3"] +pub type Ctimer3R = crate::BitReader; +impl Ctimer3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer3 { + match self.bits { + false => Ctimer3::Disabled, + true => Ctimer3::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer3::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer3::Enabled + } +} +#[doc = "Field `CTIMER3` writer - CTIMER3"] +pub type Ctimer3W<'a, REG> = crate::BitWriter<'a, REG, Ctimer3>; +impl<'a, REG> Ctimer3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer3::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer3::Enabled) + } +} +#[doc = "CTIMER4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer4 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER4` reader - CTIMER4"] +pub type Ctimer4R = crate::BitReader; +impl Ctimer4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer4 { + match self.bits { + false => Ctimer4::Disabled, + true => Ctimer4::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ctimer4::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ctimer4::Enabled + } +} +#[doc = "Field `CTIMER4` writer - CTIMER4"] +pub type Ctimer4W<'a, REG> = crate::BitWriter<'a, REG, Ctimer4>; +impl<'a, REG> Ctimer4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ctimer4::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ctimer4::Enabled) + } +} +#[doc = "FREQME\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Freqme { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Freqme) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FREQME` reader - FREQME"] +pub type FreqmeR = crate::BitReader; +impl FreqmeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Freqme { + match self.bits { + false => Freqme::Disabled, + true => Freqme::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Freqme::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Freqme::Enabled + } +} +#[doc = "Field `FREQME` writer - FREQME"] +pub type FreqmeW<'a, REG> = crate::BitWriter<'a, REG, Freqme>; +impl<'a, REG> FreqmeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Freqme::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Freqme::Enabled) + } +} +#[doc = "UTICK0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Utick0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Utick0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UTICK0` reader - UTICK0"] +pub type Utick0R = crate::BitReader; +impl Utick0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Utick0 { + match self.bits { + false => Utick0::Disabled, + true => Utick0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Utick0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Utick0::Enabled + } +} +#[doc = "Field `UTICK0` writer - UTICK0"] +pub type Utick0W<'a, REG> = crate::BitWriter<'a, REG, Utick0>; +impl<'a, REG> Utick0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Utick0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Utick0::Enabled) + } +} +#[doc = "SMARTDMA0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Smartdma0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Smartdma0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SMARTDMA0` reader - SMARTDMA0"] +pub type Smartdma0R = crate::BitReader; +impl Smartdma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Smartdma0 { + match self.bits { + false => Smartdma0::Disabled, + true => Smartdma0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Smartdma0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Smartdma0::Enabled + } +} +#[doc = "Field `SMARTDMA0` writer - SMARTDMA0"] +pub type Smartdma0W<'a, REG> = crate::BitWriter<'a, REG, Smartdma0>; +impl<'a, REG> Smartdma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Smartdma0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Smartdma0::Enabled) + } +} +#[doc = "DMA0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dma0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dma0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMA0` reader - DMA0"] +pub type Dma0R = crate::BitReader; +impl Dma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dma0 { + match self.bits { + false => Dma0::Disabled, + true => Dma0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dma0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dma0::Enabled + } +} +#[doc = "Field `DMA0` writer - DMA0"] +pub type Dma0W<'a, REG> = crate::BitWriter<'a, REG, Dma0>; +impl<'a, REG> Dma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dma0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dma0::Enabled) + } +} +#[doc = "AOI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aoi0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aoi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AOI0` reader - AOI0"] +pub type Aoi0R = crate::BitReader; +impl Aoi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aoi0 { + match self.bits { + false => Aoi0::Disabled, + true => Aoi0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Aoi0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Aoi0::Enabled + } +} +#[doc = "Field `AOI0` writer - AOI0"] +pub type Aoi0W<'a, REG> = crate::BitWriter<'a, REG, Aoi0>; +impl<'a, REG> Aoi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Aoi0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Aoi0::Enabled) + } +} +#[doc = "CRC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crc0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRC0` reader - CRC0"] +pub type Crc0R = crate::BitReader; +impl Crc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crc0 { + match self.bits { + false => Crc0::Disabled, + true => Crc0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Crc0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Crc0::Enabled + } +} +#[doc = "Field `CRC0` writer - CRC0"] +pub type Crc0W<'a, REG> = crate::BitWriter<'a, REG, Crc0>; +impl<'a, REG> Crc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Crc0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Crc0::Enabled) + } +} +#[doc = "EIM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Eim0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Eim0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EIM0` reader - EIM0"] +pub type Eim0R = crate::BitReader; +impl Eim0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Eim0 { + match self.bits { + false => Eim0::Disabled, + true => Eim0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Eim0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Eim0::Enabled + } +} +#[doc = "Field `EIM0` writer - EIM0"] +pub type Eim0W<'a, REG> = crate::BitWriter<'a, REG, Eim0>; +impl<'a, REG> Eim0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Eim0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Eim0::Enabled) + } +} +#[doc = "ERM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erm0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erm0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERM0` reader - ERM0"] +pub type Erm0R = crate::BitReader; +impl Erm0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erm0 { + match self.bits { + false => Erm0::Disabled, + true => Erm0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Erm0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Erm0::Enabled + } +} +#[doc = "Field `ERM0` writer - ERM0"] +pub type Erm0W<'a, REG> = crate::BitWriter<'a, REG, Erm0>; +impl<'a, REG> Erm0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Erm0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Erm0::Enabled) + } +} +#[doc = "AOI1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aoi1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aoi1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AOI1` reader - AOI1"] +pub type Aoi1R = crate::BitReader; +impl Aoi1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aoi1 { + match self.bits { + false => Aoi1::Disabled, + true => Aoi1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Aoi1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Aoi1::Enabled + } +} +#[doc = "Field `AOI1` writer - AOI1"] +pub type Aoi1W<'a, REG> = crate::BitWriter<'a, REG, Aoi1>; +impl<'a, REG> Aoi1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Aoi1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Aoi1::Enabled) + } +} +#[doc = "FLEXIO0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexio0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexio0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXIO0` reader - FLEXIO0"] +pub type Flexio0R = crate::BitReader; +impl Flexio0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexio0 { + match self.bits { + false => Flexio0::Disabled, + true => Flexio0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexio0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexio0::Enabled + } +} +#[doc = "Field `FLEXIO0` writer - FLEXIO0"] +pub type Flexio0W<'a, REG> = crate::BitWriter<'a, REG, Flexio0>; +impl<'a, REG> Flexio0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexio0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexio0::Enabled) + } +} +#[doc = "LPI2C0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C0` reader - LPI2C0"] +pub type Lpi2c0R = crate::BitReader; +impl Lpi2c0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c0 { + match self.bits { + false => Lpi2c0::Disabled, + true => Lpi2c0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c0::Enabled + } +} +#[doc = "Field `LPI2C0` writer - LPI2C0"] +pub type Lpi2c0W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c0>; +impl<'a, REG> Lpi2c0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c0::Enabled) + } +} +#[doc = "LPI2C1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C1` reader - LPI2C1"] +pub type Lpi2c1R = crate::BitReader; +impl Lpi2c1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c1 { + match self.bits { + false => Lpi2c1::Disabled, + true => Lpi2c1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c1::Enabled + } +} +#[doc = "Field `LPI2C1` writer - LPI2C1"] +pub type Lpi2c1W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c1>; +impl<'a, REG> Lpi2c1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c1::Enabled) + } +} +#[doc = "LPSPI0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpspi0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpspi0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPSPI0` reader - LPSPI0"] +pub type Lpspi0R = crate::BitReader; +impl Lpspi0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpspi0 { + match self.bits { + false => Lpspi0::Disabled, + true => Lpspi0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpspi0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpspi0::Enabled + } +} +#[doc = "Field `LPSPI0` writer - LPSPI0"] +pub type Lpspi0W<'a, REG> = crate::BitWriter<'a, REG, Lpspi0>; +impl<'a, REG> Lpspi0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpspi0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpspi0::Enabled) + } +} +#[doc = "LPSPI1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpspi1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpspi1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPSPI1` reader - LPSPI1"] +pub type Lpspi1R = crate::BitReader; +impl Lpspi1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpspi1 { + match self.bits { + false => Lpspi1::Disabled, + true => Lpspi1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpspi1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpspi1::Enabled + } +} +#[doc = "Field `LPSPI1` writer - LPSPI1"] +pub type Lpspi1W<'a, REG> = crate::BitWriter<'a, REG, Lpspi1>; +impl<'a, REG> Lpspi1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpspi1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpspi1::Enabled) + } +} +#[doc = "LPUART0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART0` reader - LPUART0"] +pub type Lpuart0R = crate::BitReader; +impl Lpuart0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart0 { + match self.bits { + false => Lpuart0::Disabled, + true => Lpuart0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart0::Enabled + } +} +#[doc = "Field `LPUART0` writer - LPUART0"] +pub type Lpuart0W<'a, REG> = crate::BitWriter<'a, REG, Lpuart0>; +impl<'a, REG> Lpuart0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart0::Enabled) + } +} +#[doc = "LPUART1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART1` reader - LPUART1"] +pub type Lpuart1R = crate::BitReader; +impl Lpuart1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart1 { + match self.bits { + false => Lpuart1::Disabled, + true => Lpuart1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart1::Enabled + } +} +#[doc = "Field `LPUART1` writer - LPUART1"] +pub type Lpuart1W<'a, REG> = crate::BitWriter<'a, REG, Lpuart1>; +impl<'a, REG> Lpuart1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart1::Enabled) + } +} +#[doc = "LPUART2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART2` reader - LPUART2"] +pub type Lpuart2R = crate::BitReader; +impl Lpuart2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart2 { + match self.bits { + false => Lpuart2::Disabled, + true => Lpuart2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart2::Enabled + } +} +#[doc = "Field `LPUART2` writer - LPUART2"] +pub type Lpuart2W<'a, REG> = crate::BitWriter<'a, REG, Lpuart2>; +impl<'a, REG> Lpuart2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart2::Enabled) + } +} +#[doc = "LPUART3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart3 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART3` reader - LPUART3"] +pub type Lpuart3R = crate::BitReader; +impl Lpuart3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart3 { + match self.bits { + false => Lpuart3::Disabled, + true => Lpuart3::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart3::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart3::Enabled + } +} +#[doc = "Field `LPUART3` writer - LPUART3"] +pub type Lpuart3W<'a, REG> = crate::BitWriter<'a, REG, Lpuart3>; +impl<'a, REG> Lpuart3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart3::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart3::Enabled) + } +} +#[doc = "LPUART4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart4 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART4` reader - LPUART4"] +pub type Lpuart4R = crate::BitReader; +impl Lpuart4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart4 { + match self.bits { + false => Lpuart4::Disabled, + true => Lpuart4::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart4::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart4::Enabled + } +} +#[doc = "Field `LPUART4` writer - LPUART4"] +pub type Lpuart4W<'a, REG> = crate::BitWriter<'a, REG, Lpuart4>; +impl<'a, REG> Lpuart4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart4::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart4::Enabled) + } +} +#[doc = "USB0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usb0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usb0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USB0` reader - USB0"] +pub type Usb0R = crate::BitReader; +impl Usb0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Usb0 { + match self.bits { + false => Usb0::Disabled, + true => Usb0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Usb0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Usb0::Enabled + } +} +#[doc = "Field `USB0` writer - USB0"] +pub type Usb0W<'a, REG> = crate::BitWriter<'a, REG, Usb0>; +impl<'a, REG> Usb0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Usb0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Usb0::Enabled) + } +} +#[doc = "QDC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Qdc0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Qdc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `QDC0` reader - QDC0"] +pub type Qdc0R = crate::BitReader; +impl Qdc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Qdc0 { + match self.bits { + false => Qdc0::Disabled, + true => Qdc0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Qdc0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Qdc0::Enabled + } +} +#[doc = "Field `QDC0` writer - QDC0"] +pub type Qdc0W<'a, REG> = crate::BitWriter<'a, REG, Qdc0>; +impl<'a, REG> Qdc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Qdc0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Qdc0::Enabled) + } +} +#[doc = "QDC1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Qdc1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Qdc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `QDC1` reader - QDC1"] +pub type Qdc1R = crate::BitReader; +impl Qdc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Qdc1 { + match self.bits { + false => Qdc1::Disabled, + true => Qdc1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Qdc1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Qdc1::Enabled + } +} +#[doc = "Field `QDC1` writer - QDC1"] +pub type Qdc1W<'a, REG> = crate::BitWriter<'a, REG, Qdc1>; +impl<'a, REG> Qdc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Qdc1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Qdc1::Enabled) + } +} +#[doc = "FLEXPWM0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexpwm0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexpwm0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXPWM0` reader - FLEXPWM0"] +pub type Flexpwm0R = crate::BitReader; +impl Flexpwm0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexpwm0 { + match self.bits { + false => Flexpwm0::Disabled, + true => Flexpwm0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexpwm0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexpwm0::Enabled + } +} +#[doc = "Field `FLEXPWM0` writer - FLEXPWM0"] +pub type Flexpwm0W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm0>; +impl<'a, REG> Flexpwm0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexpwm0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexpwm0::Enabled) + } +} +impl R { + #[doc = "Bit 0 - INPUTMUX0"] + #[inline(always)] + pub fn inputmux0(&self) -> Inputmux0R { + Inputmux0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I3C0"] + #[inline(always)] + pub fn i3c0(&self) -> I3c0R { + I3c0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTIMER0"] + #[inline(always)] + pub fn ctimer0(&self) -> Ctimer0R { + Ctimer0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - CTIMER1"] + #[inline(always)] + pub fn ctimer1(&self) -> Ctimer1R { + Ctimer1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - CTIMER2"] + #[inline(always)] + pub fn ctimer2(&self) -> Ctimer2R { + Ctimer2R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - CTIMER3"] + #[inline(always)] + pub fn ctimer3(&self) -> Ctimer3R { + Ctimer3R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - CTIMER4"] + #[inline(always)] + pub fn ctimer4(&self) -> Ctimer4R { + Ctimer4R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FREQME"] + #[inline(always)] + pub fn freqme(&self) -> FreqmeR { + FreqmeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - UTICK0"] + #[inline(always)] + pub fn utick0(&self) -> Utick0R { + Utick0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 10 - SMARTDMA0"] + #[inline(always)] + pub fn smartdma0(&self) -> Smartdma0R { + Smartdma0R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DMA0"] + #[inline(always)] + pub fn dma0(&self) -> Dma0R { + Dma0R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - AOI0"] + #[inline(always)] + pub fn aoi0(&self) -> Aoi0R { + Aoi0R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - CRC0"] + #[inline(always)] + pub fn crc0(&self) -> Crc0R { + Crc0R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - EIM0"] + #[inline(always)] + pub fn eim0(&self) -> Eim0R { + Eim0R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - ERM0"] + #[inline(always)] + pub fn erm0(&self) -> Erm0R { + Erm0R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - AOI1"] + #[inline(always)] + pub fn aoi1(&self) -> Aoi1R { + Aoi1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - FLEXIO0"] + #[inline(always)] + pub fn flexio0(&self) -> Flexio0R { + Flexio0R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - LPI2C0"] + #[inline(always)] + pub fn lpi2c0(&self) -> Lpi2c0R { + Lpi2c0R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LPI2C1"] + #[inline(always)] + pub fn lpi2c1(&self) -> Lpi2c1R { + Lpi2c1R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LPSPI0"] + #[inline(always)] + pub fn lpspi0(&self) -> Lpspi0R { + Lpspi0R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LPSPI1"] + #[inline(always)] + pub fn lpspi1(&self) -> Lpspi1R { + Lpspi1R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - LPUART0"] + #[inline(always)] + pub fn lpuart0(&self) -> Lpuart0R { + Lpuart0R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - LPUART1"] + #[inline(always)] + pub fn lpuart1(&self) -> Lpuart1R { + Lpuart1R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - LPUART2"] + #[inline(always)] + pub fn lpuart2(&self) -> Lpuart2R { + Lpuart2R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - LPUART3"] + #[inline(always)] + pub fn lpuart3(&self) -> Lpuart3R { + Lpuart3R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LPUART4"] + #[inline(always)] + pub fn lpuart4(&self) -> Lpuart4R { + Lpuart4R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - USB0"] + #[inline(always)] + pub fn usb0(&self) -> Usb0R { + Usb0R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - QDC0"] + #[inline(always)] + pub fn qdc0(&self) -> Qdc0R { + Qdc0R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - QDC1"] + #[inline(always)] + pub fn qdc1(&self) -> Qdc1R { + Qdc1R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - FLEXPWM0"] + #[inline(always)] + pub fn flexpwm0(&self) -> Flexpwm0R { + Flexpwm0R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - INPUTMUX0"] + #[inline(always)] + pub fn inputmux0(&mut self) -> Inputmux0W { + Inputmux0W::new(self, 0) + } + #[doc = "Bit 1 - I3C0"] + #[inline(always)] + pub fn i3c0(&mut self) -> I3c0W { + I3c0W::new(self, 1) + } + #[doc = "Bit 2 - CTIMER0"] + #[inline(always)] + pub fn ctimer0(&mut self) -> Ctimer0W { + Ctimer0W::new(self, 2) + } + #[doc = "Bit 3 - CTIMER1"] + #[inline(always)] + pub fn ctimer1(&mut self) -> Ctimer1W { + Ctimer1W::new(self, 3) + } + #[doc = "Bit 4 - CTIMER2"] + #[inline(always)] + pub fn ctimer2(&mut self) -> Ctimer2W { + Ctimer2W::new(self, 4) + } + #[doc = "Bit 5 - CTIMER3"] + #[inline(always)] + pub fn ctimer3(&mut self) -> Ctimer3W { + Ctimer3W::new(self, 5) + } + #[doc = "Bit 6 - CTIMER4"] + #[inline(always)] + pub fn ctimer4(&mut self) -> Ctimer4W { + Ctimer4W::new(self, 6) + } + #[doc = "Bit 7 - FREQME"] + #[inline(always)] + pub fn freqme(&mut self) -> FreqmeW { + FreqmeW::new(self, 7) + } + #[doc = "Bit 8 - UTICK0"] + #[inline(always)] + pub fn utick0(&mut self) -> Utick0W { + Utick0W::new(self, 8) + } + #[doc = "Bit 10 - SMARTDMA0"] + #[inline(always)] + pub fn smartdma0(&mut self) -> Smartdma0W { + Smartdma0W::new(self, 10) + } + #[doc = "Bit 11 - DMA0"] + #[inline(always)] + pub fn dma0(&mut self) -> Dma0W { + Dma0W::new(self, 11) + } + #[doc = "Bit 12 - AOI0"] + #[inline(always)] + pub fn aoi0(&mut self) -> Aoi0W { + Aoi0W::new(self, 12) + } + #[doc = "Bit 13 - CRC0"] + #[inline(always)] + pub fn crc0(&mut self) -> Crc0W { + Crc0W::new(self, 13) + } + #[doc = "Bit 14 - EIM0"] + #[inline(always)] + pub fn eim0(&mut self) -> Eim0W { + Eim0W::new(self, 14) + } + #[doc = "Bit 15 - ERM0"] + #[inline(always)] + pub fn erm0(&mut self) -> Erm0W { + Erm0W::new(self, 15) + } + #[doc = "Bit 17 - AOI1"] + #[inline(always)] + pub fn aoi1(&mut self) -> Aoi1W { + Aoi1W::new(self, 17) + } + #[doc = "Bit 18 - FLEXIO0"] + #[inline(always)] + pub fn flexio0(&mut self) -> Flexio0W { + Flexio0W::new(self, 18) + } + #[doc = "Bit 19 - LPI2C0"] + #[inline(always)] + pub fn lpi2c0(&mut self) -> Lpi2c0W { + Lpi2c0W::new(self, 19) + } + #[doc = "Bit 20 - LPI2C1"] + #[inline(always)] + pub fn lpi2c1(&mut self) -> Lpi2c1W { + Lpi2c1W::new(self, 20) + } + #[doc = "Bit 21 - LPSPI0"] + #[inline(always)] + pub fn lpspi0(&mut self) -> Lpspi0W { + Lpspi0W::new(self, 21) + } + #[doc = "Bit 22 - LPSPI1"] + #[inline(always)] + pub fn lpspi1(&mut self) -> Lpspi1W { + Lpspi1W::new(self, 22) + } + #[doc = "Bit 23 - LPUART0"] + #[inline(always)] + pub fn lpuart0(&mut self) -> Lpuart0W { + Lpuart0W::new(self, 23) + } + #[doc = "Bit 24 - LPUART1"] + #[inline(always)] + pub fn lpuart1(&mut self) -> Lpuart1W { + Lpuart1W::new(self, 24) + } + #[doc = "Bit 25 - LPUART2"] + #[inline(always)] + pub fn lpuart2(&mut self) -> Lpuart2W { + Lpuart2W::new(self, 25) + } + #[doc = "Bit 26 - LPUART3"] + #[inline(always)] + pub fn lpuart3(&mut self) -> Lpuart3W { + Lpuart3W::new(self, 26) + } + #[doc = "Bit 27 - LPUART4"] + #[inline(always)] + pub fn lpuart4(&mut self) -> Lpuart4W { + Lpuart4W::new(self, 27) + } + #[doc = "Bit 28 - USB0"] + #[inline(always)] + pub fn usb0(&mut self) -> Usb0W { + Usb0W::new(self, 28) + } + #[doc = "Bit 29 - QDC0"] + #[inline(always)] + pub fn qdc0(&mut self) -> Qdc0W { + Qdc0W::new(self, 29) + } + #[doc = "Bit 30 - QDC1"] + #[inline(always)] + pub fn qdc1(&mut self) -> Qdc1W { + Qdc1W::new(self, 30) + } + #[doc = "Bit 31 - FLEXPWM0"] + #[inline(always)] + pub fn flexpwm0(&mut self) -> Flexpwm0W { + Flexpwm0W::new(self, 31) + } +} +#[doc = "Peripheral Reset Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst0Spec; +impl crate::RegisterSpec for MrccGlbRst0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_rst0::R`](R) reader structure"] +impl crate::Readable for MrccGlbRst0Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst0::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST0 to value 0"] +impl crate::Resettable for MrccGlbRst0Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs new file mode 100644 index 000000000..26319587a --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_RST0_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Peripheral Reset Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst0ClrSpec; +impl crate::RegisterSpec for MrccGlbRst0ClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst0_clr::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst0ClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST0_CLR to value 0"] +impl crate::Resettable for MrccGlbRst0ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs new file mode 100644 index 000000000..8e23f0ae0 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_RST0_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Peripheral Reset Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst0SetSpec; +impl crate::RegisterSpec for MrccGlbRst0SetSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst0_set::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst0SetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST0_SET to value 0"] +impl crate::Resettable for MrccGlbRst0SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs new file mode 100644 index 000000000..9004e3f0a --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs @@ -0,0 +1,1659 @@ +#[doc = "Register `MRCC_GLB_RST1` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_RST1` writer"] +pub type W = crate::W; +#[doc = "FLEXPWM1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexpwm1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexpwm1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXPWM1` reader - FLEXPWM1"] +pub type Flexpwm1R = crate::BitReader; +impl Flexpwm1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexpwm1 { + match self.bits { + false => Flexpwm1::Disabled, + true => Flexpwm1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexpwm1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexpwm1::Enabled + } +} +#[doc = "Field `FLEXPWM1` writer - FLEXPWM1"] +pub type Flexpwm1W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm1>; +impl<'a, REG> Flexpwm1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexpwm1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexpwm1::Enabled) + } +} +#[doc = "OSTIMER0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ostimer0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ostimer0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSTIMER0` reader - OSTIMER0"] +pub type Ostimer0R = crate::BitReader; +impl Ostimer0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ostimer0 { + match self.bits { + false => Ostimer0::Disabled, + true => Ostimer0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ostimer0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ostimer0::Enabled + } +} +#[doc = "Field `OSTIMER0` writer - OSTIMER0"] +pub type Ostimer0W<'a, REG> = crate::BitWriter<'a, REG, Ostimer0>; +impl<'a, REG> Ostimer0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ostimer0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ostimer0::Enabled) + } +} +#[doc = "ADC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC0` reader - ADC0"] +pub type Adc0R = crate::BitReader; +impl Adc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc0 { + match self.bits { + false => Adc0::Disabled, + true => Adc0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc0::Enabled + } +} +#[doc = "Field `ADC0` writer - ADC0"] +pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG, Adc0>; +impl<'a, REG> Adc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc0::Enabled) + } +} +#[doc = "ADC1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC1` reader - ADC1"] +pub type Adc1R = crate::BitReader; +impl Adc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc1 { + match self.bits { + false => Adc1::Disabled, + true => Adc1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc1::Enabled + } +} +#[doc = "Field `ADC1` writer - ADC1"] +pub type Adc1W<'a, REG> = crate::BitWriter<'a, REG, Adc1>; +impl<'a, REG> Adc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc1::Enabled) + } +} +#[doc = "CMP1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP1` reader - CMP1"] +pub type Cmp1R = crate::BitReader; +impl Cmp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp1 { + match self.bits { + false => Cmp1::Disabled, + true => Cmp1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp1::Enabled + } +} +#[doc = "Field `CMP1` writer - CMP1"] +pub type Cmp1W<'a, REG> = crate::BitWriter<'a, REG, Cmp1>; +impl<'a, REG> Cmp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp1::Enabled) + } +} +#[doc = "CMP2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cmp2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cmp2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMP2` reader - CMP2"] +pub type Cmp2R = crate::BitReader; +impl Cmp2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cmp2 { + match self.bits { + false => Cmp2::Disabled, + true => Cmp2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cmp2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cmp2::Enabled + } +} +#[doc = "Field `CMP2` writer - CMP2"] +pub type Cmp2W<'a, REG> = crate::BitWriter<'a, REG, Cmp2>; +impl<'a, REG> Cmp2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cmp2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cmp2::Enabled) + } +} +#[doc = "DAC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dac0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dac0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DAC0` reader - DAC0"] +pub type Dac0R = crate::BitReader; +impl Dac0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dac0 { + match self.bits { + false => Dac0::Disabled, + true => Dac0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dac0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dac0::Enabled + } +} +#[doc = "Field `DAC0` writer - DAC0"] +pub type Dac0W<'a, REG> = crate::BitWriter<'a, REG, Dac0>; +impl<'a, REG> Dac0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dac0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dac0::Enabled) + } +} +#[doc = "OPAMP0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP0` reader - OPAMP0"] +pub type Opamp0R = crate::BitReader; +impl Opamp0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp0 { + match self.bits { + false => Opamp0::Disabled, + true => Opamp0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp0::Enabled + } +} +#[doc = "Field `OPAMP0` writer - OPAMP0"] +pub type Opamp0W<'a, REG> = crate::BitWriter<'a, REG, Opamp0>; +impl<'a, REG> Opamp0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp0::Enabled) + } +} +#[doc = "OPAMP1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP1` reader - OPAMP1"] +pub type Opamp1R = crate::BitReader; +impl Opamp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp1 { + match self.bits { + false => Opamp1::Disabled, + true => Opamp1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp1::Enabled + } +} +#[doc = "Field `OPAMP1` writer - OPAMP1"] +pub type Opamp1W<'a, REG> = crate::BitWriter<'a, REG, Opamp1>; +impl<'a, REG> Opamp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp1::Enabled) + } +} +#[doc = "OPAMP2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP2` reader - OPAMP2"] +pub type Opamp2R = crate::BitReader; +impl Opamp2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp2 { + match self.bits { + false => Opamp2::Disabled, + true => Opamp2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp2::Enabled + } +} +#[doc = "Field `OPAMP2` writer - OPAMP2"] +pub type Opamp2W<'a, REG> = crate::BitWriter<'a, REG, Opamp2>; +impl<'a, REG> Opamp2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp2::Enabled) + } +} +#[doc = "OPAMP3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Opamp3 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Opamp3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPAMP3` reader - OPAMP3"] +pub type Opamp3R = crate::BitReader; +impl Opamp3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Opamp3 { + match self.bits { + false => Opamp3::Disabled, + true => Opamp3::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Opamp3::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Opamp3::Enabled + } +} +#[doc = "Field `OPAMP3` writer - OPAMP3"] +pub type Opamp3W<'a, REG> = crate::BitWriter<'a, REG, Opamp3>; +impl<'a, REG> Opamp3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Opamp3::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Opamp3::Enabled) + } +} +#[doc = "PORT0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT0` reader - PORT0"] +pub type Port0R = crate::BitReader; +impl Port0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port0 { + match self.bits { + false => Port0::Disabled, + true => Port0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port0::Enabled + } +} +#[doc = "Field `PORT0` writer - PORT0"] +pub type Port0W<'a, REG> = crate::BitWriter<'a, REG, Port0>; +impl<'a, REG> Port0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port0::Enabled) + } +} +#[doc = "PORT1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT1` reader - PORT1"] +pub type Port1R = crate::BitReader; +impl Port1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port1 { + match self.bits { + false => Port1::Disabled, + true => Port1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port1::Enabled + } +} +#[doc = "Field `PORT1` writer - PORT1"] +pub type Port1W<'a, REG> = crate::BitWriter<'a, REG, Port1>; +impl<'a, REG> Port1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port1::Enabled) + } +} +#[doc = "PORT2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT2` reader - PORT2"] +pub type Port2R = crate::BitReader; +impl Port2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port2 { + match self.bits { + false => Port2::Disabled, + true => Port2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port2::Enabled + } +} +#[doc = "Field `PORT2` writer - PORT2"] +pub type Port2W<'a, REG> = crate::BitWriter<'a, REG, Port2>; +impl<'a, REG> Port2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port2::Enabled) + } +} +#[doc = "PORT3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port3 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT3` reader - PORT3"] +pub type Port3R = crate::BitReader; +impl Port3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port3 { + match self.bits { + false => Port3::Disabled, + true => Port3::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port3::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port3::Enabled + } +} +#[doc = "Field `PORT3` writer - PORT3"] +pub type Port3W<'a, REG> = crate::BitWriter<'a, REG, Port3>; +impl<'a, REG> Port3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port3::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port3::Enabled) + } +} +#[doc = "PORT4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Port4 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Port4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PORT4` reader - PORT4"] +pub type Port4R = crate::BitReader; +impl Port4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Port4 { + match self.bits { + false => Port4::Disabled, + true => Port4::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Port4::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Port4::Enabled + } +} +#[doc = "Field `PORT4` writer - PORT4"] +pub type Port4W<'a, REG> = crate::BitWriter<'a, REG, Port4>; +impl<'a, REG> Port4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Port4::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Port4::Enabled) + } +} +#[doc = "SLCD0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Slcd0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Slcd0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLCD0` reader - SLCD0"] +pub type Slcd0R = crate::BitReader; +impl Slcd0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Slcd0 { + match self.bits { + false => Slcd0::Disabled, + true => Slcd0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Slcd0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Slcd0::Enabled + } +} +#[doc = "Field `SLCD0` writer - SLCD0"] +pub type Slcd0W<'a, REG> = crate::BitWriter<'a, REG, Slcd0>; +impl<'a, REG> Slcd0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Slcd0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Slcd0::Enabled) + } +} +#[doc = "FLEXCAN0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexcan0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexcan0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXCAN0` reader - FLEXCAN0"] +pub type Flexcan0R = crate::BitReader; +impl Flexcan0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexcan0 { + match self.bits { + false => Flexcan0::Disabled, + true => Flexcan0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexcan0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexcan0::Enabled + } +} +#[doc = "Field `FLEXCAN0` writer - FLEXCAN0"] +pub type Flexcan0W<'a, REG> = crate::BitWriter<'a, REG, Flexcan0>; +impl<'a, REG> Flexcan0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexcan0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexcan0::Enabled) + } +} +#[doc = "FLEXCAN1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flexcan1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flexcan1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLEXCAN1` reader - FLEXCAN1"] +pub type Flexcan1R = crate::BitReader; +impl Flexcan1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flexcan1 { + match self.bits { + false => Flexcan1::Disabled, + true => Flexcan1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flexcan1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flexcan1::Enabled + } +} +#[doc = "Field `FLEXCAN1` writer - FLEXCAN1"] +pub type Flexcan1W<'a, REG> = crate::BitWriter<'a, REG, Flexcan1>; +impl<'a, REG> Flexcan1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flexcan1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flexcan1::Enabled) + } +} +#[doc = "LPI2C2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C2` reader - LPI2C2"] +pub type Lpi2c2R = crate::BitReader; +impl Lpi2c2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c2 { + match self.bits { + false => Lpi2c2::Disabled, + true => Lpi2c2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c2::Enabled + } +} +#[doc = "Field `LPI2C2` writer - LPI2C2"] +pub type Lpi2c2W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c2>; +impl<'a, REG> Lpi2c2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c2::Enabled) + } +} +#[doc = "LPI2C3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpi2c3 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpi2c3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPI2C3` reader - LPI2C3"] +pub type Lpi2c3R = crate::BitReader; +impl Lpi2c3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpi2c3 { + match self.bits { + false => Lpi2c3::Disabled, + true => Lpi2c3::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpi2c3::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpi2c3::Enabled + } +} +#[doc = "Field `LPI2C3` writer - LPI2C3"] +pub type Lpi2c3W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c3>; +impl<'a, REG> Lpi2c3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpi2c3::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpi2c3::Enabled) + } +} +#[doc = "LPUART5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpuart5 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpuart5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPUART5` reader - LPUART5"] +pub type Lpuart5R = crate::BitReader; +impl Lpuart5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpuart5 { + match self.bits { + false => Lpuart5::Disabled, + true => Lpuart5::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Lpuart5::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Lpuart5::Enabled + } +} +#[doc = "Field `LPUART5` writer - LPUART5"] +pub type Lpuart5W<'a, REG> = crate::BitWriter<'a, REG, Lpuart5>; +impl<'a, REG> Lpuart5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Lpuart5::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Lpuart5::Enabled) + } +} +#[doc = "PKC0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pkc0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pkc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PKC0` reader - PKC0"] +pub type Pkc0R = crate::BitReader; +impl Pkc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pkc0 { + match self.bits { + false => Pkc0::Disabled, + true => Pkc0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pkc0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pkc0::Enabled + } +} +#[doc = "Field `PKC0` writer - PKC0"] +pub type Pkc0W<'a, REG> = crate::BitWriter<'a, REG, Pkc0>; +impl<'a, REG> Pkc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Pkc0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Pkc0::Enabled) + } +} +#[doc = "TRNG0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Trng0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Trng0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRNG0` reader - TRNG0"] +pub type Trng0R = crate::BitReader; +impl Trng0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Trng0 { + match self.bits { + false => Trng0::Disabled, + true => Trng0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Trng0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Trng0::Enabled + } +} +#[doc = "Field `TRNG0` writer - TRNG0"] +pub type Trng0W<'a, REG> = crate::BitWriter<'a, REG, Trng0>; +impl<'a, REG> Trng0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Trng0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Trng0::Enabled) + } +} +#[doc = "ADC2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC2` reader - ADC2"] +pub type Adc2R = crate::BitReader; +impl Adc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc2 { + match self.bits { + false => Adc2::Disabled, + true => Adc2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc2::Enabled + } +} +#[doc = "Field `ADC2` writer - ADC2"] +pub type Adc2W<'a, REG> = crate::BitWriter<'a, REG, Adc2>; +impl<'a, REG> Adc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc2::Enabled) + } +} +#[doc = "ADC3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc3 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC3` reader - ADC3"] +pub type Adc3R = crate::BitReader; +impl Adc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc3 { + match self.bits { + false => Adc3::Disabled, + true => Adc3::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Adc3::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Adc3::Enabled + } +} +#[doc = "Field `ADC3` writer - ADC3"] +pub type Adc3W<'a, REG> = crate::BitWriter<'a, REG, Adc3>; +impl<'a, REG> Adc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Adc3::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Adc3::Enabled) + } +} +impl R { + #[doc = "Bit 0 - FLEXPWM1"] + #[inline(always)] + pub fn flexpwm1(&self) -> Flexpwm1R { + Flexpwm1R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - OSTIMER0"] + #[inline(always)] + pub fn ostimer0(&self) -> Ostimer0R { + Ostimer0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - ADC0"] + #[inline(always)] + pub fn adc0(&self) -> Adc0R { + Adc0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ADC1"] + #[inline(always)] + pub fn adc1(&self) -> Adc1R { + Adc1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - CMP1"] + #[inline(always)] + pub fn cmp1(&self) -> Cmp1R { + Cmp1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - CMP2"] + #[inline(always)] + pub fn cmp2(&self) -> Cmp2R { + Cmp2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - DAC0"] + #[inline(always)] + pub fn dac0(&self) -> Dac0R { + Dac0R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - OPAMP0"] + #[inline(always)] + pub fn opamp0(&self) -> Opamp0R { + Opamp0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - OPAMP1"] + #[inline(always)] + pub fn opamp1(&self) -> Opamp1R { + Opamp1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OPAMP2"] + #[inline(always)] + pub fn opamp2(&self) -> Opamp2R { + Opamp2R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - OPAMP3"] + #[inline(always)] + pub fn opamp3(&self) -> Opamp3R { + Opamp3R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - PORT0"] + #[inline(always)] + pub fn port0(&self) -> Port0R { + Port0R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - PORT1"] + #[inline(always)] + pub fn port1(&self) -> Port1R { + Port1R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PORT2"] + #[inline(always)] + pub fn port2(&self) -> Port2R { + Port2R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - PORT3"] + #[inline(always)] + pub fn port3(&self) -> Port3R { + Port3R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - PORT4"] + #[inline(always)] + pub fn port4(&self) -> Port4R { + Port4R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SLCD0"] + #[inline(always)] + pub fn slcd0(&self) -> Slcd0R { + Slcd0R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - FLEXCAN0"] + #[inline(always)] + pub fn flexcan0(&self) -> Flexcan0R { + Flexcan0R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - FLEXCAN1"] + #[inline(always)] + pub fn flexcan1(&self) -> Flexcan1R { + Flexcan1R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LPI2C2"] + #[inline(always)] + pub fn lpi2c2(&self) -> Lpi2c2R { + Lpi2c2R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LPI2C3"] + #[inline(always)] + pub fn lpi2c3(&self) -> Lpi2c3R { + Lpi2c3R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LPUART5"] + #[inline(always)] + pub fn lpuart5(&self) -> Lpuart5R { + Lpuart5R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - PKC0"] + #[inline(always)] + pub fn pkc0(&self) -> Pkc0R { + Pkc0R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 26 - TRNG0"] + #[inline(always)] + pub fn trng0(&self) -> Trng0R { + Trng0R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - ADC2"] + #[inline(always)] + pub fn adc2(&self) -> Adc2R { + Adc2R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - ADC3"] + #[inline(always)] + pub fn adc3(&self) -> Adc3R { + Adc3R::new(((self.bits >> 29) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLEXPWM1"] + #[inline(always)] + pub fn flexpwm1(&mut self) -> Flexpwm1W { + Flexpwm1W::new(self, 0) + } + #[doc = "Bit 1 - OSTIMER0"] + #[inline(always)] + pub fn ostimer0(&mut self) -> Ostimer0W { + Ostimer0W::new(self, 1) + } + #[doc = "Bit 2 - ADC0"] + #[inline(always)] + pub fn adc0(&mut self) -> Adc0W { + Adc0W::new(self, 2) + } + #[doc = "Bit 3 - ADC1"] + #[inline(always)] + pub fn adc1(&mut self) -> Adc1W { + Adc1W::new(self, 3) + } + #[doc = "Bit 5 - CMP1"] + #[inline(always)] + pub fn cmp1(&mut self) -> Cmp1W { + Cmp1W::new(self, 5) + } + #[doc = "Bit 6 - CMP2"] + #[inline(always)] + pub fn cmp2(&mut self) -> Cmp2W { + Cmp2W::new(self, 6) + } + #[doc = "Bit 7 - DAC0"] + #[inline(always)] + pub fn dac0(&mut self) -> Dac0W { + Dac0W::new(self, 7) + } + #[doc = "Bit 8 - OPAMP0"] + #[inline(always)] + pub fn opamp0(&mut self) -> Opamp0W { + Opamp0W::new(self, 8) + } + #[doc = "Bit 9 - OPAMP1"] + #[inline(always)] + pub fn opamp1(&mut self) -> Opamp1W { + Opamp1W::new(self, 9) + } + #[doc = "Bit 10 - OPAMP2"] + #[inline(always)] + pub fn opamp2(&mut self) -> Opamp2W { + Opamp2W::new(self, 10) + } + #[doc = "Bit 11 - OPAMP3"] + #[inline(always)] + pub fn opamp3(&mut self) -> Opamp3W { + Opamp3W::new(self, 11) + } + #[doc = "Bit 12 - PORT0"] + #[inline(always)] + pub fn port0(&mut self) -> Port0W { + Port0W::new(self, 12) + } + #[doc = "Bit 13 - PORT1"] + #[inline(always)] + pub fn port1(&mut self) -> Port1W { + Port1W::new(self, 13) + } + #[doc = "Bit 14 - PORT2"] + #[inline(always)] + pub fn port2(&mut self) -> Port2W { + Port2W::new(self, 14) + } + #[doc = "Bit 15 - PORT3"] + #[inline(always)] + pub fn port3(&mut self) -> Port3W { + Port3W::new(self, 15) + } + #[doc = "Bit 16 - PORT4"] + #[inline(always)] + pub fn port4(&mut self) -> Port4W { + Port4W::new(self, 16) + } + #[doc = "Bit 17 - SLCD0"] + #[inline(always)] + pub fn slcd0(&mut self) -> Slcd0W { + Slcd0W::new(self, 17) + } + #[doc = "Bit 18 - FLEXCAN0"] + #[inline(always)] + pub fn flexcan0(&mut self) -> Flexcan0W { + Flexcan0W::new(self, 18) + } + #[doc = "Bit 19 - FLEXCAN1"] + #[inline(always)] + pub fn flexcan1(&mut self) -> Flexcan1W { + Flexcan1W::new(self, 19) + } + #[doc = "Bit 20 - LPI2C2"] + #[inline(always)] + pub fn lpi2c2(&mut self) -> Lpi2c2W { + Lpi2c2W::new(self, 20) + } + #[doc = "Bit 21 - LPI2C3"] + #[inline(always)] + pub fn lpi2c3(&mut self) -> Lpi2c3W { + Lpi2c3W::new(self, 21) + } + #[doc = "Bit 22 - LPUART5"] + #[inline(always)] + pub fn lpuart5(&mut self) -> Lpuart5W { + Lpuart5W::new(self, 22) + } + #[doc = "Bit 24 - PKC0"] + #[inline(always)] + pub fn pkc0(&mut self) -> Pkc0W { + Pkc0W::new(self, 24) + } + #[doc = "Bit 26 - TRNG0"] + #[inline(always)] + pub fn trng0(&mut self) -> Trng0W { + Trng0W::new(self, 26) + } + #[doc = "Bit 28 - ADC2"] + #[inline(always)] + pub fn adc2(&mut self) -> Adc2W { + Adc2W::new(self, 28) + } + #[doc = "Bit 29 - ADC3"] + #[inline(always)] + pub fn adc3(&mut self) -> Adc3W { + Adc3W::new(self, 29) + } +} +#[doc = "Peripheral Reset Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst1Spec; +impl crate::RegisterSpec for MrccGlbRst1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_rst1::R`](R) reader structure"] +impl crate::Readable for MrccGlbRst1Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst1::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST1 to value 0"] +impl crate::Resettable for MrccGlbRst1Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs new file mode 100644 index 000000000..3cd0b5377 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_RST1_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Peripheral Reset Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst1ClrSpec; +impl crate::RegisterSpec for MrccGlbRst1ClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst1_clr::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst1ClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST1_CLR to value 0"] +impl crate::Resettable for MrccGlbRst1ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs new file mode 100644 index 000000000..0afffe172 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_RST1_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Peripheral Reset Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst1SetSpec; +impl crate::RegisterSpec for MrccGlbRst1SetSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst1_set::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst1SetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST1_SET to value 0"] +impl crate::Resettable for MrccGlbRst1SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs new file mode 100644 index 000000000..c46aa85b9 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs @@ -0,0 +1,399 @@ +#[doc = "Register `MRCC_GLB_RST2` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_GLB_RST2` writer"] +pub type W = crate::W; +#[doc = "GPIO0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO0` reader - GPIO0"] +pub type Gpio0R = crate::BitReader; +impl Gpio0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio0 { + match self.bits { + false => Gpio0::Disabled, + true => Gpio0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio0::Enabled + } +} +#[doc = "Field `GPIO0` writer - GPIO0"] +pub type Gpio0W<'a, REG> = crate::BitWriter<'a, REG, Gpio0>; +impl<'a, REG> Gpio0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio0::Enabled) + } +} +#[doc = "GPIO1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio1 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO1` reader - GPIO1"] +pub type Gpio1R = crate::BitReader; +impl Gpio1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio1 { + match self.bits { + false => Gpio1::Disabled, + true => Gpio1::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio1::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio1::Enabled + } +} +#[doc = "Field `GPIO1` writer - GPIO1"] +pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG, Gpio1>; +impl<'a, REG> Gpio1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio1::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio1::Enabled) + } +} +#[doc = "GPIO2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio2 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO2` reader - GPIO2"] +pub type Gpio2R = crate::BitReader; +impl Gpio2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio2 { + match self.bits { + false => Gpio2::Disabled, + true => Gpio2::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio2::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio2::Enabled + } +} +#[doc = "Field `GPIO2` writer - GPIO2"] +pub type Gpio2W<'a, REG> = crate::BitWriter<'a, REG, Gpio2>; +impl<'a, REG> Gpio2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio2::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio2::Enabled) + } +} +#[doc = "GPIO3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio3 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO3` reader - GPIO3"] +pub type Gpio3R = crate::BitReader; +impl Gpio3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio3 { + match self.bits { + false => Gpio3::Disabled, + true => Gpio3::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio3::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio3::Enabled + } +} +#[doc = "Field `GPIO3` writer - GPIO3"] +pub type Gpio3W<'a, REG> = crate::BitWriter<'a, REG, Gpio3>; +impl<'a, REG> Gpio3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio3::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio3::Enabled) + } +} +#[doc = "GPIO4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio4 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO4` reader - GPIO4"] +pub type Gpio4R = crate::BitReader; +impl Gpio4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio4 { + match self.bits { + false => Gpio4::Disabled, + true => Gpio4::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Gpio4::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Gpio4::Enabled + } +} +#[doc = "Field `GPIO4` writer - GPIO4"] +pub type Gpio4W<'a, REG> = crate::BitWriter<'a, REG, Gpio4>; +impl<'a, REG> Gpio4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Gpio4::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Gpio4::Enabled) + } +} +#[doc = "MAU0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mau0 { + #[doc = "0: Peripheral is held in reset"] + Disabled = 0, + #[doc = "1: Peripheral is released from reset"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mau0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MAU0` reader - MAU0"] +pub type Mau0R = crate::BitReader; +impl Mau0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mau0 { + match self.bits { + false => Mau0::Disabled, + true => Mau0::Enabled, + } + } + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mau0::Disabled + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mau0::Enabled + } +} +#[doc = "Field `MAU0` writer - MAU0"] +pub type Mau0W<'a, REG> = crate::BitWriter<'a, REG, Mau0>; +impl<'a, REG> Mau0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Peripheral is held in reset"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mau0::Disabled) + } + #[doc = "Peripheral is released from reset"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mau0::Enabled) + } +} +impl R { + #[doc = "Bit 4 - GPIO0"] + #[inline(always)] + pub fn gpio0(&self) -> Gpio0R { + Gpio0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - GPIO1"] + #[inline(always)] + pub fn gpio1(&self) -> Gpio1R { + Gpio1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - GPIO2"] + #[inline(always)] + pub fn gpio2(&self) -> Gpio2R { + Gpio2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - GPIO3"] + #[inline(always)] + pub fn gpio3(&self) -> Gpio3R { + Gpio3R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - GPIO4"] + #[inline(always)] + pub fn gpio4(&self) -> Gpio4R { + Gpio4R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MAU0"] + #[inline(always)] + pub fn mau0(&self) -> Mau0R { + Mau0R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - GPIO0"] + #[inline(always)] + pub fn gpio0(&mut self) -> Gpio0W { + Gpio0W::new(self, 4) + } + #[doc = "Bit 5 - GPIO1"] + #[inline(always)] + pub fn gpio1(&mut self) -> Gpio1W { + Gpio1W::new(self, 5) + } + #[doc = "Bit 6 - GPIO2"] + #[inline(always)] + pub fn gpio2(&mut self) -> Gpio2W { + Gpio2W::new(self, 6) + } + #[doc = "Bit 7 - GPIO3"] + #[inline(always)] + pub fn gpio3(&mut self) -> Gpio3W { + Gpio3W::new(self, 7) + } + #[doc = "Bit 8 - GPIO4"] + #[inline(always)] + pub fn gpio4(&mut self) -> Gpio4W { + Gpio4W::new(self, 8) + } + #[doc = "Bit 9 - MAU0"] + #[inline(always)] + pub fn mau0(&mut self) -> Mau0W { + Mau0W::new(self, 9) + } +} +#[doc = "Peripheral Reset Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst2Spec; +impl crate::RegisterSpec for MrccGlbRst2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_glb_rst2::R`](R) reader structure"] +impl crate::Readable for MrccGlbRst2Spec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst2::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST2 to value 0"] +impl crate::Resettable for MrccGlbRst2Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs new file mode 100644 index 000000000..91afe580f --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_RST2_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Peripheral Reset Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst2ClrSpec; +impl crate::RegisterSpec for MrccGlbRst2ClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst2_clr::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst2ClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST2_CLR to value 0"] +impl crate::Resettable for MrccGlbRst2ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs new file mode 100644 index 000000000..ccd36786a --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs @@ -0,0 +1,22 @@ +#[doc = "Register `MRCC_GLB_RST2_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Peripheral Reset Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccGlbRst2SetSpec; +impl crate::RegisterSpec for MrccGlbRst2SetSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst2_set::W`](W) writer structure"] +impl crate::Writable for MrccGlbRst2SetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_GLB_RST2_SET to value 0"] +impl crate::Resettable for MrccGlbRst2SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs new file mode 100644 index 000000000..267469047 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_I3C0_FCLK_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_I3C0_FCLK_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "I3C0_FCLK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccI3c0FclkClkdivSpec; +impl crate::RegisterSpec for MrccI3c0FclkClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_i3c0_fclk_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccI3c0FclkClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_i3c0_fclk_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccI3c0FclkClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_I3C0_FCLK_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccI3c0FclkClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs new file mode 100644 index 000000000..c5b13eb95 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_I3C0_FCLK_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_I3C0_FCLK_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "I3C0_FCLK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccI3c0FclkClkselSpec; +impl crate::RegisterSpec for MrccI3c0FclkClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_i3c0_fclk_clksel::R`](R) reader structure"] +impl crate::Readable for MrccI3c0FclkClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_i3c0_fclk_clksel::W`](W) writer structure"] +impl crate::Writable for MrccI3c0FclkClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_I3C0_FCLK_CLKSEL to value 0x07"] +impl crate::Resettable for MrccI3c0FclkClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs new file mode 100644 index 000000000..af9093dd8 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPI2C0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPI2C0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c0ClkdivSpec; +impl crate::RegisterSpec for MrccLpi2c0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpi2c0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs new file mode 100644 index 000000000..1fc51c06f --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_LPI2C0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPI2C0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c0ClkselSpec; +impl crate::RegisterSpec for MrccLpi2c0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpi2c0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs new file mode 100644 index 000000000..69d200248 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPI2C1_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C1_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPI2C1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c1ClkdivSpec; +impl crate::RegisterSpec for MrccLpi2c1ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c1_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c1ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c1_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c1ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C1_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpi2c1ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs new file mode 100644 index 000000000..555c782c7 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_LPI2C1_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C1_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPI2C1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c1ClkselSpec; +impl crate::RegisterSpec for MrccLpi2c1ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c1_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c1ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c1_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c1ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C1_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpi2c1ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs new file mode 100644 index 000000000..9d6d04e96 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPI2C2_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C2_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPI2C2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c2ClkdivSpec; +impl crate::RegisterSpec for MrccLpi2c2ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c2_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c2ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c2_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c2ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C2_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpi2c2ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs new file mode 100644 index 000000000..1179207cd --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_LPI2C2_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C2_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPI2C2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c2ClkselSpec; +impl crate::RegisterSpec for MrccLpi2c2ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c2_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c2ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c2_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c2ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C2_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpi2c2ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs new file mode 100644 index 000000000..afa745322 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPI2C3_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C3_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPI2C3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c3ClkdivSpec; +impl crate::RegisterSpec for MrccLpi2c3ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c3_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c3ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c3_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c3ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C3_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpi2c3ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs new file mode 100644 index 000000000..8137576a7 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_LPI2C3_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPI2C3_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPI2C3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpi2c3ClkselSpec; +impl crate::RegisterSpec for MrccLpi2c3ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpi2c3_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpi2c3ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c3_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpi2c3ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPI2C3_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpi2c3ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs new file mode 100644 index 000000000..85d92c8c4 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPSPI0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPSPI0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPSPI0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpspi0ClkdivSpec; +impl crate::RegisterSpec for MrccLpspi0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpspi0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpspi0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpspi0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPSPI0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpspi0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs new file mode 100644 index 000000000..41244a760 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_LPSPI0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPSPI0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPSPI0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpspi0ClkselSpec; +impl crate::RegisterSpec for MrccLpspi0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpspi0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpspi0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpspi0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPSPI0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpspi0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs new file mode 100644 index 000000000..ccde8afee --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPSPI1_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPSPI1_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPSPI1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpspi1ClkdivSpec; +impl crate::RegisterSpec for MrccLpspi1ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpspi1_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpspi1ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi1_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpspi1ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPSPI1_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpspi1ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs new file mode 100644 index 000000000..c0217bee6 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_LPSPI1_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPSPI1_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPSPI1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpspi1ClkselSpec; +impl crate::RegisterSpec for MrccLpspi1ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpspi1_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpspi1ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi1_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpspi1ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPSPI1_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpspi1ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs new file mode 100644 index 000000000..3a08bff78 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPTMR0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPTMR0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPTMR0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLptmr0ClkdivSpec; +impl crate::RegisterSpec for MrccLptmr0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lptmr0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLptmr0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lptmr0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLptmr0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPTMR0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLptmr0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs new file mode 100644 index 000000000..c93c4c45e --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs @@ -0,0 +1,132 @@ +#[doc = "Register `MRCC_LPTMR0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPTMR0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPTMR0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLptmr0ClkselSpec; +impl crate::RegisterSpec for MrccLptmr0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lptmr0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLptmr0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lptmr0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLptmr0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPTMR0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLptmr0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs new file mode 100644 index 000000000..e15c95f92 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPUART0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPUART0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart0ClkdivSpec; +impl crate::RegisterSpec for MrccLpuart0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpuart0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpuart0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpuart0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs new file mode 100644 index 000000000..88e4a2ebd --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_LPUART0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPUART0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart0ClkselSpec; +impl crate::RegisterSpec for MrccLpuart0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpuart0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpuart0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART0_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpuart0ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs new file mode 100644 index 000000000..96def465f --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPUART1_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART1_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPUART1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart1ClkdivSpec; +impl crate::RegisterSpec for MrccLpuart1ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart1_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpuart1ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart1_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpuart1ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART1_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpuart1ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs new file mode 100644 index 000000000..c0667e0af --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_LPUART1_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART1_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPUART1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart1ClkselSpec; +impl crate::RegisterSpec for MrccLpuart1ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart1_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpuart1ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart1_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpuart1ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART1_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpuart1ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs new file mode 100644 index 000000000..ae202770e --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPUART2_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART2_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPUART2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart2ClkdivSpec; +impl crate::RegisterSpec for MrccLpuart2ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart2_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpuart2ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart2_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpuart2ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART2_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpuart2ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs new file mode 100644 index 000000000..a61e9cc9f --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_LPUART2_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART2_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPUART2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart2ClkselSpec; +impl crate::RegisterSpec for MrccLpuart2ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart2_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpuart2ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart2_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpuart2ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART2_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpuart2ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs new file mode 100644 index 000000000..228849012 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPUART3_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART3_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPUART3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart3ClkdivSpec; +impl crate::RegisterSpec for MrccLpuart3ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart3_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpuart3ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart3_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpuart3ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART3_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpuart3ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs new file mode 100644 index 000000000..f830c0031 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_LPUART3_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART3_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPUART3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart3ClkselSpec; +impl crate::RegisterSpec for MrccLpuart3ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart3_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpuart3ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart3_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpuart3ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART3_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpuart3ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs new file mode 100644 index 000000000..dd8554552 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPUART4_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART4_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPUART4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart4ClkdivSpec; +impl crate::RegisterSpec for MrccLpuart4ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart4_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpuart4ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart4_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpuart4ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART4_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpuart4ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs new file mode 100644 index 000000000..83105959f --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_LPUART4_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART4_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPUART4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart4ClkselSpec; +impl crate::RegisterSpec for MrccLpuart4ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart4_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpuart4ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart4_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpuart4ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART4_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpuart4ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs new file mode 100644 index 000000000..71f59d36b --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_LPUART5_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART5_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "LPUART5 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart5ClkdivSpec; +impl crate::RegisterSpec for MrccLpuart5ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart5_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccLpuart5ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart5_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccLpuart5ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART5_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccLpuart5ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs new file mode 100644 index 000000000..b89a6f388 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MRCC_LPUART5_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_LPUART5_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: FRO_LF_DIV"] + ClkrootFunc0 = 0, + #[doc = "2: FRO_HF_DIV"] + ClkrootFunc2 = 2, + #[doc = "3: CLK_IN"] + ClkrootFunc3 = 3, + #[doc = "4: CLK_16K"] + ClkrootFunc4 = 4, + #[doc = "5: CLK_1M"] + ClkrootFunc5 = 5, + #[doc = "6: PLL1_CLK_DIV"] + ClkrootFunc6 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootFunc0), + 2 => Some(Mux::ClkrootFunc2), + 3 => Some(Mux::ClkrootFunc3), + 4 => Some(Mux::ClkrootFunc4), + 5 => Some(Mux::ClkrootFunc5), + 6 => Some(Mux::ClkrootFunc6), + _ => None, + } + } + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_0(&self) -> bool { + *self == Mux::ClkrootFunc0 + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn is_clkroot_func_2(&self) -> bool { + *self == Mux::ClkrootFunc2 + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_func_3(&self) -> bool { + *self == Mux::ClkrootFunc3 + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_func_4(&self) -> bool { + *self == Mux::ClkrootFunc4 + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_func_5(&self) -> bool { + *self == Mux::ClkrootFunc5 + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn is_clkroot_func_6(&self) -> bool { + *self == Mux::ClkrootFunc6 + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "FRO_LF_DIV"] + #[inline(always)] + pub fn clkroot_func_0(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc0) + } + #[doc = "FRO_HF_DIV"] + #[inline(always)] + pub fn clkroot_func_2(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc2) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_func_3(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc3) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_func_4(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc4) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_func_5(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc5) + } + #[doc = "PLL1_CLK_DIV"] + #[inline(always)] + pub fn clkroot_func_6(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootFunc6) + } +} +impl R { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "LPUART5 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccLpuart5ClkselSpec; +impl crate::RegisterSpec for MrccLpuart5ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_lpuart5_clksel::R`](R) reader structure"] +impl crate::Readable for MrccLpuart5ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart5_clksel::W`](W) writer structure"] +impl crate::Writable for MrccLpuart5ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_LPUART5_CLKSEL to value 0x07"] +impl crate::Resettable for MrccLpuart5ClkselSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs new file mode 100644 index 000000000..d61da5bb0 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs @@ -0,0 +1,93 @@ +#[doc = "Register `MRCC_OSTIMER0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_OSTIMER0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: CLK_16K"] + Clkroot16k = 0, + #[doc = "2: CLK_1M"] + Clkroot1m = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Clkroot16k), + 2 => Some(Mux::Clkroot1m), + _ => None, + } + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_16k(&self) -> bool { + *self == Mux::Clkroot16k + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_1m(&self) -> bool { + *self == Mux::Clkroot1m + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_16k(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot16k) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_1m(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot1m) + } +} +impl R { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "OSTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ostimer0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ostimer0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccOstimer0ClkselSpec; +impl crate::RegisterSpec for MrccOstimer0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_ostimer0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccOstimer0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_ostimer0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccOstimer0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_OSTIMER0_CLKSEL to value 0x03"] +impl crate::Resettable for MrccOstimer0ClkselSpec { + const RESET_VALUE: u32 = 0x03; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs new file mode 100644 index 000000000..3cf688924 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_SYSTICK_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_SYSTICK_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "SYSTICK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccSystickClkdivSpec; +impl crate::RegisterSpec for MrccSystickClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_systick_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccSystickClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_systick_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccSystickClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_SYSTICK_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccSystickClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs new file mode 100644 index 000000000..1545b66dd --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs @@ -0,0 +1,106 @@ +#[doc = "Register `MRCC_SYSTICK_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_SYSTICK_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: CPU_CLK"] + ClkrootCpu = 0, + #[doc = "1: CLK_1M"] + Clkroot1m = 1, + #[doc = "2: CLK_16K"] + Clkroot16k = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootCpu), + 1 => Some(Mux::Clkroot1m), + 2 => Some(Mux::Clkroot16k), + _ => None, + } + } + #[doc = "CPU_CLK"] + #[inline(always)] + pub fn is_clkroot_cpu(&self) -> bool { + *self == Mux::ClkrootCpu + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn is_clkroot_1m(&self) -> bool { + *self == Mux::Clkroot1m + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn is_clkroot_16k(&self) -> bool { + *self == Mux::Clkroot16k + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CPU_CLK"] + #[inline(always)] + pub fn clkroot_cpu(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootCpu) + } + #[doc = "CLK_1M"] + #[inline(always)] + pub fn clkroot_1m(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot1m) + } + #[doc = "CLK_16K"] + #[inline(always)] + pub fn clkroot_16k(self) -> &'a mut crate::W { + self.variant(Mux::Clkroot16k) + } +} +impl R { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "SYSTICK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccSystickClkselSpec; +impl crate::RegisterSpec for MrccSystickClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_systick_clksel::R`](R) reader structure"] +impl crate::Readable for MrccSystickClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_systick_clksel::W`](W) writer structure"] +impl crate::Writable for MrccSystickClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_SYSTICK_CLKSEL to value 0x03"] +impl crate::Resettable for MrccSystickClkselSpec { + const RESET_VALUE: u32 = 0x03; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs new file mode 100644 index 000000000..83588fa02 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs @@ -0,0 +1,177 @@ +#[doc = "Register `MRCC_USB0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_USB0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "USB0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccUsb0ClkdivSpec; +impl crate::RegisterSpec for MrccUsb0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_usb0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccUsb0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_usb0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccUsb0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_USB0_CLKDIV to value 0x4000_0000"] +impl crate::Resettable for MrccUsb0ClkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs new file mode 100644 index 000000000..7d0af232e --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs @@ -0,0 +1,106 @@ +#[doc = "Register `MRCC_USB0_CLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_USB0_CLKSEL` writer"] +pub type W = crate::W; +#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: PLL1_CLK"] + ClkrootSpll = 0, + #[doc = "1: CLK_48M"] + ScgScgFirc48mhzClk = 1, + #[doc = "2: CLK_IN"] + ClkrootSosc = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Functional Clock Mux Select"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::ClkrootSpll), + 1 => Some(Mux::ScgScgFirc48mhzClk), + 2 => Some(Mux::ClkrootSosc), + _ => None, + } + } + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn is_clkroot_spll(&self) -> bool { + *self == Mux::ClkrootSpll + } + #[doc = "CLK_48M"] + #[inline(always)] + pub fn is_scg_scg_firc_48mhz_clk(&self) -> bool { + *self == Mux::ScgScgFirc48mhzClk + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn is_clkroot_sosc(&self) -> bool { + *self == Mux::ClkrootSosc + } +} +#[doc = "Field `MUX` writer - Functional Clock Mux Select"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "PLL1_CLK"] + #[inline(always)] + pub fn clkroot_spll(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSpll) + } + #[doc = "CLK_48M"] + #[inline(always)] + pub fn scg_scg_firc_48mhz_clk(self) -> &'a mut crate::W { + self.variant(Mux::ScgScgFirc48mhzClk) + } + #[doc = "CLK_IN"] + #[inline(always)] + pub fn clkroot_sosc(self) -> &'a mut crate::W { + self.variant(Mux::ClkrootSosc) + } +} +impl R { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Functional Clock Mux Select"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 0) + } +} +#[doc = "USB0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccUsb0ClkselSpec; +impl crate::RegisterSpec for MrccUsb0ClkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_usb0_clksel::R`](R) reader structure"] +impl crate::Readable for MrccUsb0ClkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_usb0_clksel::W`](W) writer structure"] +impl crate::Writable for MrccUsb0ClkselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_USB0_CLKSEL to value 0x03"] +impl crate::Resettable for MrccUsb0ClkselSpec { + const RESET_VALUE: u32 = 0x03; +} diff --git a/mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs new file mode 100644 index 000000000..43aa31c92 --- /dev/null +++ b/mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs @@ -0,0 +1,175 @@ +#[doc = "Register `MRCC_WWDT0_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `MRCC_WWDT0_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Functional Clock Divider"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Functional Clock Divider"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Reset divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider isn't reset"] + On = 0, + #[doc = "1: Divider is reset"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` writer - Reset divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider isn't reset"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Reset::On) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Reset::Off) + } +} +#[doc = "Halt divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + On = 0, + #[doc = "1: Divider clock is stopped"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halt divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::On, + true => Halt::Off, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Halt::On + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Halt::Off + } +} +#[doc = "Field `HALT` writer - Halt divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn on(self) -> &'a mut crate::W { + self.variant(Halt::On) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn off(self) -> &'a mut crate::W { + self.variant(Halt::Off) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + On = 0, + #[doc = "1: Clock frequency isn't stable"] + Off = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::On, + true => Unstab::Off, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == Unstab::On + } + #[doc = "Clock frequency isn't stable"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == Unstab::Off + } +} +impl R { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Functional Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Reset divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halt divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "WWDT0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_wwdt0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_wwdt0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrccWwdt0ClkdivSpec; +impl crate::RegisterSpec for MrccWwdt0ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mrcc_wwdt0_clkdiv::R`](R) reader structure"] +impl crate::Readable for MrccWwdt0ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`mrcc_wwdt0_clkdiv::W`](W) writer structure"] +impl crate::Writable for MrccWwdt0ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MRCC_WWDT0_CLKDIV to value 0"] +impl crate::Resettable for MrccWwdt0ClkdivSpec {} diff --git a/mcxa276-pac/src/opamp0.rs b/mcxa276-pac/src/opamp0.rs new file mode 100644 index 000000000..94ff0bd7d --- /dev/null +++ b/mcxa276-pac/src/opamp0.rs @@ -0,0 +1,39 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + opamp_ctrl: OpampCtrl, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x08 - OPAMP Control"] + #[inline(always)] + pub const fn opamp_ctrl(&self) -> &OpampCtrl { + &self.opamp_ctrl + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "OPAMP_CTRL (rw) register accessor: OPAMP Control\n\nYou can [`read`](crate::Reg::read) this register and get [`opamp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opamp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@opamp_ctrl`] module"] +#[doc(alias = "OPAMP_CTRL")] +pub type OpampCtrl = crate::Reg; +#[doc = "OPAMP Control"] +pub mod opamp_ctrl; diff --git a/mcxa276-pac/src/opamp0/opamp_ctrl.rs b/mcxa276-pac/src/opamp0/opamp_ctrl.rs new file mode 100644 index 000000000..eb3a84a5a --- /dev/null +++ b/mcxa276-pac/src/opamp0/opamp_ctrl.rs @@ -0,0 +1,276 @@ +#[doc = "Register `OPAMP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `OPAMP_CTRL` writer"] +pub type W = crate::W; +#[doc = "OPAMP Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OpaEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OpaEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OPA_EN` reader - OPAMP Enable"] +pub type OpaEnR = crate::BitReader; +impl OpaEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OpaEn { + match self.bits { + false => OpaEn::Disable, + true => OpaEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OpaEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OpaEn::Enable + } +} +#[doc = "Field `OPA_EN` writer - OPAMP Enable"] +pub type OpaEnW<'a, REG> = crate::BitWriter<'a, REG, OpaEn>; +impl<'a, REG> OpaEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OpaEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OpaEn::Enable) + } +} +#[doc = "Compensation capcitor config selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OpaCcSel { + #[doc = "0: Fit 2X gains"] + Tbd1 = 0, + #[doc = "1: Fit 4X gains"] + Tbd2 = 1, + #[doc = "2: Fit 8X gains"] + Tbd3 = 2, + #[doc = "3: Fit 16X gains"] + Tbd4 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OpaCcSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OpaCcSel { + type Ux = u8; +} +impl crate::IsEnum for OpaCcSel {} +#[doc = "Field `OPA_CC_SEL` reader - Compensation capcitor config selection"] +pub type OpaCcSelR = crate::FieldReader; +impl OpaCcSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OpaCcSel { + match self.bits { + 0 => OpaCcSel::Tbd1, + 1 => OpaCcSel::Tbd2, + 2 => OpaCcSel::Tbd3, + 3 => OpaCcSel::Tbd4, + _ => unreachable!(), + } + } + #[doc = "Fit 2X gains"] + #[inline(always)] + pub fn is_tbd1(&self) -> bool { + *self == OpaCcSel::Tbd1 + } + #[doc = "Fit 4X gains"] + #[inline(always)] + pub fn is_tbd2(&self) -> bool { + *self == OpaCcSel::Tbd2 + } + #[doc = "Fit 8X gains"] + #[inline(always)] + pub fn is_tbd3(&self) -> bool { + *self == OpaCcSel::Tbd3 + } + #[doc = "Fit 16X gains"] + #[inline(always)] + pub fn is_tbd4(&self) -> bool { + *self == OpaCcSel::Tbd4 + } +} +#[doc = "Field `OPA_CC_SEL` writer - Compensation capcitor config selection"] +pub type OpaCcSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, OpaCcSel, crate::Safe>; +impl<'a, REG> OpaCcSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Fit 2X gains"] + #[inline(always)] + pub fn tbd1(self) -> &'a mut crate::W { + self.variant(OpaCcSel::Tbd1) + } + #[doc = "Fit 4X gains"] + #[inline(always)] + pub fn tbd2(self) -> &'a mut crate::W { + self.variant(OpaCcSel::Tbd2) + } + #[doc = "Fit 8X gains"] + #[inline(always)] + pub fn tbd3(self) -> &'a mut crate::W { + self.variant(OpaCcSel::Tbd3) + } + #[doc = "Fit 16X gains"] + #[inline(always)] + pub fn tbd4(self) -> &'a mut crate::W { + self.variant(OpaCcSel::Tbd4) + } +} +#[doc = "Bias current config selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OpaBcSel { + #[doc = "0: Default value. Keep power consumption constant"] + Tbd1 = 0, + #[doc = "1: Reduce power consumption to 1/4"] + Tbd2 = 1, + #[doc = "2: Reduce power consumption to 1/2"] + Tbd3 = 2, + #[doc = "3: Double the power consumption"] + Tbd4 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OpaBcSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OpaBcSel { + type Ux = u8; +} +impl crate::IsEnum for OpaBcSel {} +#[doc = "Field `OPA_BC_SEL` reader - Bias current config selection"] +pub type OpaBcSelR = crate::FieldReader; +impl OpaBcSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OpaBcSel { + match self.bits { + 0 => OpaBcSel::Tbd1, + 1 => OpaBcSel::Tbd2, + 2 => OpaBcSel::Tbd3, + 3 => OpaBcSel::Tbd4, + _ => unreachable!(), + } + } + #[doc = "Default value. Keep power consumption constant"] + #[inline(always)] + pub fn is_tbd1(&self) -> bool { + *self == OpaBcSel::Tbd1 + } + #[doc = "Reduce power consumption to 1/4"] + #[inline(always)] + pub fn is_tbd2(&self) -> bool { + *self == OpaBcSel::Tbd2 + } + #[doc = "Reduce power consumption to 1/2"] + #[inline(always)] + pub fn is_tbd3(&self) -> bool { + *self == OpaBcSel::Tbd3 + } + #[doc = "Double the power consumption"] + #[inline(always)] + pub fn is_tbd4(&self) -> bool { + *self == OpaBcSel::Tbd4 + } +} +#[doc = "Field `OPA_BC_SEL` writer - Bias current config selection"] +pub type OpaBcSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, OpaBcSel, crate::Safe>; +impl<'a, REG> OpaBcSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Default value. Keep power consumption constant"] + #[inline(always)] + pub fn tbd1(self) -> &'a mut crate::W { + self.variant(OpaBcSel::Tbd1) + } + #[doc = "Reduce power consumption to 1/4"] + #[inline(always)] + pub fn tbd2(self) -> &'a mut crate::W { + self.variant(OpaBcSel::Tbd2) + } + #[doc = "Reduce power consumption to 1/2"] + #[inline(always)] + pub fn tbd3(self) -> &'a mut crate::W { + self.variant(OpaBcSel::Tbd3) + } + #[doc = "Double the power consumption"] + #[inline(always)] + pub fn tbd4(self) -> &'a mut crate::W { + self.variant(OpaBcSel::Tbd4) + } +} +impl R { + #[doc = "Bit 0 - OPAMP Enable"] + #[inline(always)] + pub fn opa_en(&self) -> OpaEnR { + OpaEnR::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:5 - Compensation capcitor config selection"] + #[inline(always)] + pub fn opa_cc_sel(&self) -> OpaCcSelR { + OpaCcSelR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Bias current config selection"] + #[inline(always)] + pub fn opa_bc_sel(&self) -> OpaBcSelR { + OpaBcSelR::new(((self.bits >> 6) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - OPAMP Enable"] + #[inline(always)] + pub fn opa_en(&mut self) -> OpaEnW { + OpaEnW::new(self, 0) + } + #[doc = "Bits 4:5 - Compensation capcitor config selection"] + #[inline(always)] + pub fn opa_cc_sel(&mut self) -> OpaCcSelW { + OpaCcSelW::new(self, 4) + } + #[doc = "Bits 6:7 - Bias current config selection"] + #[inline(always)] + pub fn opa_bc_sel(&mut self) -> OpaBcSelW { + OpaBcSelW::new(self, 6) + } +} +#[doc = "OPAMP Control\n\nYou can [`read`](crate::Reg::read) this register and get [`opamp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opamp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OpampCtrlSpec; +impl crate::RegisterSpec for OpampCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`opamp_ctrl::R`](R) reader structure"] +impl crate::Readable for OpampCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`opamp_ctrl::W`](W) writer structure"] +impl crate::Writable for OpampCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets OPAMP_CTRL to value 0"] +impl crate::Resettable for OpampCtrlSpec {} diff --git a/mcxa276-pac/src/opamp0/param.rs b/mcxa276-pac/src/opamp0/param.rs new file mode 100644 index 000000000..c132ea417 --- /dev/null +++ b/mcxa276-pac/src/opamp0/param.rs @@ -0,0 +1,16 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for ParamSpec {} diff --git a/mcxa276-pac/src/opamp0/verid.rs b/mcxa276-pac/src/opamp0/verid.rs new file mode 100644 index 000000000..26e3283cc --- /dev/null +++ b/mcxa276-pac/src/opamp0/verid.rs @@ -0,0 +1,34 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0"] +impl crate::Resettable for VeridSpec {} diff --git a/mcxa276-pac/src/ostimer0.rs b/mcxa276-pac/src/ostimer0.rs new file mode 100644 index 000000000..64ad679af --- /dev/null +++ b/mcxa276-pac/src/ostimer0.rs @@ -0,0 +1,84 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + evtimerl: Evtimerl, + evtimerh: Evtimerh, + capture_l: CaptureL, + capture_h: CaptureH, + match_l: MatchL, + match_h: MatchH, + _reserved6: [u8; 0x04], + osevent_ctrl: OseventCtrl, +} +impl RegisterBlock { + #[doc = "0x00 - EVTIMER Low"] + #[inline(always)] + pub const fn evtimerl(&self) -> &Evtimerl { + &self.evtimerl + } + #[doc = "0x04 - EVTIMER High"] + #[inline(always)] + pub const fn evtimerh(&self) -> &Evtimerh { + &self.evtimerh + } + #[doc = "0x08 - Local Capture Low for CPU"] + #[inline(always)] + pub const fn capture_l(&self) -> &CaptureL { + &self.capture_l + } + #[doc = "0x0c - Local Capture High for CPU"] + #[inline(always)] + pub const fn capture_h(&self) -> &CaptureH { + &self.capture_h + } + #[doc = "0x10 - Local Match Low for CPU"] + #[inline(always)] + pub const fn match_l(&self) -> &MatchL { + &self.match_l + } + #[doc = "0x14 - Local Match High for CPU"] + #[inline(always)] + pub const fn match_h(&self) -> &MatchH { + &self.match_h + } + #[doc = "0x1c - OSTIMER Control for CPU"] + #[inline(always)] + pub const fn osevent_ctrl(&self) -> &OseventCtrl { + &self.osevent_ctrl + } +} +#[doc = "EVTIMERL (r) register accessor: EVTIMER Low\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evtimerl`] module"] +#[doc(alias = "EVTIMERL")] +pub type Evtimerl = crate::Reg; +#[doc = "EVTIMER Low"] +pub mod evtimerl; +#[doc = "EVTIMERH (r) register accessor: EVTIMER High\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evtimerh`] module"] +#[doc(alias = "EVTIMERH")] +pub type Evtimerh = crate::Reg; +#[doc = "EVTIMER High"] +pub mod evtimerh; +#[doc = "CAPTURE_L (r) register accessor: Local Capture Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_l::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capture_l`] module"] +#[doc(alias = "CAPTURE_L")] +pub type CaptureL = crate::Reg; +#[doc = "Local Capture Low for CPU"] +pub mod capture_l; +#[doc = "CAPTURE_H (r) register accessor: Local Capture High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_h::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capture_h`] module"] +#[doc(alias = "CAPTURE_H")] +pub type CaptureH = crate::Reg; +#[doc = "Local Capture High for CPU"] +pub mod capture_h; +#[doc = "MATCH_L (rw) register accessor: Local Match Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_l`] module"] +#[doc(alias = "MATCH_L")] +pub type MatchL = crate::Reg; +#[doc = "Local Match Low for CPU"] +pub mod match_l; +#[doc = "MATCH_H (rw) register accessor: Local Match High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_h`] module"] +#[doc(alias = "MATCH_H")] +pub type MatchH = crate::Reg; +#[doc = "Local Match High for CPU"] +pub mod match_h; +#[doc = "OSEVENT_CTRL (rw) register accessor: OSTIMER Control for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`osevent_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osevent_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osevent_ctrl`] module"] +#[doc(alias = "OSEVENT_CTRL")] +pub type OseventCtrl = crate::Reg; +#[doc = "OSTIMER Control for CPU"] +pub mod osevent_ctrl; diff --git a/mcxa276-pac/src/ostimer0/capture_h.rs b/mcxa276-pac/src/ostimer0/capture_h.rs new file mode 100644 index 000000000..57b7c1500 --- /dev/null +++ b/mcxa276-pac/src/ostimer0/capture_h.rs @@ -0,0 +1,20 @@ +#[doc = "Register `CAPTURE_H` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTURE_VALUE` reader - EVTimer Capture Value"] +pub type CaptureValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - EVTimer Capture Value"] + #[inline(always)] + pub fn capture_value(&self) -> CaptureValueR { + CaptureValueR::new((self.bits & 0x03ff) as u16) + } +} +#[doc = "Local Capture High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_h::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CaptureHSpec; +impl crate::RegisterSpec for CaptureHSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`capture_h::R`](R) reader structure"] +impl crate::Readable for CaptureHSpec {} +#[doc = "`reset()` method sets CAPTURE_H to value 0"] +impl crate::Resettable for CaptureHSpec {} diff --git a/mcxa276-pac/src/ostimer0/capture_l.rs b/mcxa276-pac/src/ostimer0/capture_l.rs new file mode 100644 index 000000000..b4e25c3f7 --- /dev/null +++ b/mcxa276-pac/src/ostimer0/capture_l.rs @@ -0,0 +1,20 @@ +#[doc = "Register `CAPTURE_L` reader"] +pub type R = crate::R; +#[doc = "Field `CAPTURE_VALUE` reader - EVTimer Capture Value"] +pub type CaptureValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - EVTimer Capture Value"] + #[inline(always)] + pub fn capture_value(&self) -> CaptureValueR { + CaptureValueR::new(self.bits) + } +} +#[doc = "Local Capture Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_l::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CaptureLSpec; +impl crate::RegisterSpec for CaptureLSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`capture_l::R`](R) reader structure"] +impl crate::Readable for CaptureLSpec {} +#[doc = "`reset()` method sets CAPTURE_L to value 0"] +impl crate::Resettable for CaptureLSpec {} diff --git a/mcxa276-pac/src/ostimer0/evtimerh.rs b/mcxa276-pac/src/ostimer0/evtimerh.rs new file mode 100644 index 000000000..f7afa192b --- /dev/null +++ b/mcxa276-pac/src/ostimer0/evtimerh.rs @@ -0,0 +1,20 @@ +#[doc = "Register `EVTIMERH` reader"] +pub type R = crate::R; +#[doc = "Field `EVTIMER_COUNT_VALUE` reader - EVTimer Count Value"] +pub type EvtimerCountValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - EVTimer Count Value"] + #[inline(always)] + pub fn evtimer_count_value(&self) -> EvtimerCountValueR { + EvtimerCountValueR::new((self.bits & 0x03ff) as u16) + } +} +#[doc = "EVTIMER High\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EvtimerhSpec; +impl crate::RegisterSpec for EvtimerhSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`evtimerh::R`](R) reader structure"] +impl crate::Readable for EvtimerhSpec {} +#[doc = "`reset()` method sets EVTIMERH to value 0"] +impl crate::Resettable for EvtimerhSpec {} diff --git a/mcxa276-pac/src/ostimer0/evtimerl.rs b/mcxa276-pac/src/ostimer0/evtimerl.rs new file mode 100644 index 000000000..99e561df9 --- /dev/null +++ b/mcxa276-pac/src/ostimer0/evtimerl.rs @@ -0,0 +1,20 @@ +#[doc = "Register `EVTIMERL` reader"] +pub type R = crate::R; +#[doc = "Field `EVTIMER_COUNT_VALUE` reader - EVTimer Count Value"] +pub type EvtimerCountValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - EVTimer Count Value"] + #[inline(always)] + pub fn evtimer_count_value(&self) -> EvtimerCountValueR { + EvtimerCountValueR::new(self.bits) + } +} +#[doc = "EVTIMER Low\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EvtimerlSpec; +impl crate::RegisterSpec for EvtimerlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`evtimerl::R`](R) reader structure"] +impl crate::Readable for EvtimerlSpec {} +#[doc = "`reset()` method sets EVTIMERL to value 0"] +impl crate::Resettable for EvtimerlSpec {} diff --git a/mcxa276-pac/src/ostimer0/match_h.rs b/mcxa276-pac/src/ostimer0/match_h.rs new file mode 100644 index 000000000..324335a30 --- /dev/null +++ b/mcxa276-pac/src/ostimer0/match_h.rs @@ -0,0 +1,37 @@ +#[doc = "Register `MATCH_H` reader"] +pub type R = crate::R; +#[doc = "Register `MATCH_H` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH_VALUE` reader - EVTimer Match Value"] +pub type MatchValueR = crate::FieldReader; +#[doc = "Field `MATCH_VALUE` writer - EVTimer Match Value"] +pub type MatchValueW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - EVTimer Match Value"] + #[inline(always)] + pub fn match_value(&self) -> MatchValueR { + MatchValueR::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - EVTimer Match Value"] + #[inline(always)] + pub fn match_value(&mut self) -> MatchValueW { + MatchValueW::new(self, 0) + } +} +#[doc = "Local Match High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MatchHSpec; +impl crate::RegisterSpec for MatchHSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`match_h::R`](R) reader structure"] +impl crate::Readable for MatchHSpec {} +#[doc = "`write(|w| ..)` method takes [`match_h::W`](W) writer structure"] +impl crate::Writable for MatchHSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MATCH_H to value 0xffff_ffff"] +impl crate::Resettable for MatchHSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/mcxa276-pac/src/ostimer0/match_l.rs b/mcxa276-pac/src/ostimer0/match_l.rs new file mode 100644 index 000000000..b4f5ddd0a --- /dev/null +++ b/mcxa276-pac/src/ostimer0/match_l.rs @@ -0,0 +1,37 @@ +#[doc = "Register `MATCH_L` reader"] +pub type R = crate::R; +#[doc = "Register `MATCH_L` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH_VALUE` reader - EVTimer Match Value"] +pub type MatchValueR = crate::FieldReader; +#[doc = "Field `MATCH_VALUE` writer - EVTimer Match Value"] +pub type MatchValueW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - EVTimer Match Value"] + #[inline(always)] + pub fn match_value(&self) -> MatchValueR { + MatchValueR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - EVTimer Match Value"] + #[inline(always)] + pub fn match_value(&mut self) -> MatchValueW { + MatchValueW::new(self, 0) + } +} +#[doc = "Local Match Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MatchLSpec; +impl crate::RegisterSpec for MatchLSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`match_l::R`](R) reader structure"] +impl crate::Readable for MatchLSpec {} +#[doc = "`write(|w| ..)` method takes [`match_l::W`](W) writer structure"] +impl crate::Writable for MatchLSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MATCH_L to value 0xffff_ffff"] +impl crate::Resettable for MatchLSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/mcxa276-pac/src/ostimer0/osevent_ctrl.rs b/mcxa276-pac/src/ostimer0/osevent_ctrl.rs new file mode 100644 index 000000000..79340b633 --- /dev/null +++ b/mcxa276-pac/src/ostimer0/osevent_ctrl.rs @@ -0,0 +1,171 @@ +#[doc = "Register `OSEVENT_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `OSEVENT_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `OSTIMER_INTRFLAG` reader - Interrupt Flag"] +pub type OstimerIntrflagR = crate::BitReader; +#[doc = "Field `OSTIMER_INTRFLAG` writer - Interrupt Flag"] +pub type OstimerIntrflagW<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Interrupt or Wake-Up Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OstimerIntena { + #[doc = "0: Interrupts blocked"] + InterruptsBlocked = 0, + #[doc = "1: Interrupts enabled"] + InterruptsEnabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OstimerIntena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSTIMER_INTENA` reader - Interrupt or Wake-Up Request"] +pub type OstimerIntenaR = crate::BitReader; +impl OstimerIntenaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OstimerIntena { + match self.bits { + false => OstimerIntena::InterruptsBlocked, + true => OstimerIntena::InterruptsEnabled, + } + } + #[doc = "Interrupts blocked"] + #[inline(always)] + pub fn is_interrupts_blocked(&self) -> bool { + *self == OstimerIntena::InterruptsBlocked + } + #[doc = "Interrupts enabled"] + #[inline(always)] + pub fn is_interrupts_enabled(&self) -> bool { + *self == OstimerIntena::InterruptsEnabled + } +} +#[doc = "Field `OSTIMER_INTENA` writer - Interrupt or Wake-Up Request"] +pub type OstimerIntenaW<'a, REG> = crate::BitWriter<'a, REG, OstimerIntena>; +impl<'a, REG> OstimerIntenaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupts blocked"] + #[inline(always)] + pub fn interrupts_blocked(self) -> &'a mut crate::W { + self.variant(OstimerIntena::InterruptsBlocked) + } + #[doc = "Interrupts enabled"] + #[inline(always)] + pub fn interrupts_enabled(self) -> &'a mut crate::W { + self.variant(OstimerIntena::InterruptsEnabled) + } +} +#[doc = "Field `MATCH_WR_RDY` reader - EVTimer Match Write Ready"] +pub type MatchWrRdyR = crate::BitReader; +#[doc = "Debug Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DebugEn { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DebugEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DEBUG_EN` reader - Debug Enable"] +pub type DebugEnR = crate::BitReader; +impl DebugEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DebugEn { + match self.bits { + false => DebugEn::Disable, + true => DebugEn::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DebugEn::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DebugEn::Enable + } +} +#[doc = "Field `DEBUG_EN` writer - Debug Enable"] +pub type DebugEnW<'a, REG> = crate::BitWriter<'a, REG, DebugEn>; +impl<'a, REG> DebugEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DebugEn::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DebugEn::Enable) + } +} +impl R { + #[doc = "Bit 0 - Interrupt Flag"] + #[inline(always)] + pub fn ostimer_intrflag(&self) -> OstimerIntrflagR { + OstimerIntrflagR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt or Wake-Up Request"] + #[inline(always)] + pub fn ostimer_intena(&self) -> OstimerIntenaR { + OstimerIntenaR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - EVTimer Match Write Ready"] + #[inline(always)] + pub fn match_wr_rdy(&self) -> MatchWrRdyR { + MatchWrRdyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Debug Enable"] + #[inline(always)] + pub fn debug_en(&self) -> DebugEnR { + DebugEnR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt Flag"] + #[inline(always)] + pub fn ostimer_intrflag(&mut self) -> OstimerIntrflagW { + OstimerIntrflagW::new(self, 0) + } + #[doc = "Bit 1 - Interrupt or Wake-Up Request"] + #[inline(always)] + pub fn ostimer_intena(&mut self) -> OstimerIntenaW { + OstimerIntenaW::new(self, 1) + } + #[doc = "Bit 3 - Debug Enable"] + #[inline(always)] + pub fn debug_en(&mut self) -> DebugEnW { + DebugEnW::new(self, 3) + } +} +#[doc = "OSTIMER Control for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`osevent_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osevent_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OseventCtrlSpec; +impl crate::RegisterSpec for OseventCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`osevent_ctrl::R`](R) reader structure"] +impl crate::Readable for OseventCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`osevent_ctrl::W`](W) writer structure"] +impl crate::Writable for OseventCtrlSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets OSEVENT_CTRL to value 0x08"] +impl crate::Resettable for OseventCtrlSpec { + const RESET_VALUE: u32 = 0x08; +} diff --git a/mcxa276-pac/src/pkc0.rs b/mcxa276-pac/src/pkc0.rs new file mode 100644 index 000000000..b37692ca1 --- /dev/null +++ b/mcxa276-pac/src/pkc0.rs @@ -0,0 +1,300 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + pkc_status: PkcStatus, + pkc_ctrl: PkcCtrl, + pkc_cfg: PkcCfg, + _reserved3: [u8; 0x04], + pkc_mode1: PkcMode1, + pkc_xyptr1: PkcXyptr1, + pkc_zrptr1: PkcZrptr1, + pkc_len1: PkcLen1, + pkc_mode2: PkcMode2, + pkc_xyptr2: PkcXyptr2, + pkc_zrptr2: PkcZrptr2, + pkc_len2: PkcLen2, + _reserved11: [u8; 0x10], + pkc_uptr: PkcUptr, + pkc_uptrt: PkcUptrt, + pkc_ulen: PkcUlen, + _reserved14: [u8; 0x04], + pkc_mcdata: PkcMcdata, + _reserved15: [u8; 0x0c], + pkc_version: PkcVersion, + _reserved16: [u8; 0x0f4c], + pkc_soft_rst: PkcSoftRst, + _reserved17: [u8; 0x0c], + pkc_access_err: PkcAccessErr, + pkc_access_err_clr: PkcAccessErrClr, + _reserved19: [u8; 0x10], + pkc_int_clr_enable: PkcIntClrEnable, + pkc_int_set_enable: PkcIntSetEnable, + pkc_int_status: PkcIntStatus, + pkc_int_enable: PkcIntEnable, + pkc_int_clr_status: PkcIntClrStatus, + pkc_int_set_status: PkcIntSetStatus, + _reserved25: [u8; 0x0c], + pkc_module_id: PkcModuleId, +} +impl RegisterBlock { + #[doc = "0x00 - Status Register"] + #[inline(always)] + pub const fn pkc_status(&self) -> &PkcStatus { + &self.pkc_status + } + #[doc = "0x04 - Control Register"] + #[inline(always)] + pub const fn pkc_ctrl(&self) -> &PkcCtrl { + &self.pkc_ctrl + } + #[doc = "0x08 - Configuration register"] + #[inline(always)] + pub const fn pkc_cfg(&self) -> &PkcCfg { + &self.pkc_cfg + } + #[doc = "0x10 - Mode register, parameter set 1"] + #[inline(always)] + pub const fn pkc_mode1(&self) -> &PkcMode1 { + &self.pkc_mode1 + } + #[doc = "0x14 - X+Y pointer register, parameter set 1"] + #[inline(always)] + pub const fn pkc_xyptr1(&self) -> &PkcXyptr1 { + &self.pkc_xyptr1 + } + #[doc = "0x18 - Z+R pointer register, parameter set 1"] + #[inline(always)] + pub const fn pkc_zrptr1(&self) -> &PkcZrptr1 { + &self.pkc_zrptr1 + } + #[doc = "0x1c - Length register, parameter set 1"] + #[inline(always)] + pub const fn pkc_len1(&self) -> &PkcLen1 { + &self.pkc_len1 + } + #[doc = "0x20 - Mode register, parameter set 2"] + #[inline(always)] + pub const fn pkc_mode2(&self) -> &PkcMode2 { + &self.pkc_mode2 + } + #[doc = "0x24 - X+Y pointer register, parameter set 2"] + #[inline(always)] + pub const fn pkc_xyptr2(&self) -> &PkcXyptr2 { + &self.pkc_xyptr2 + } + #[doc = "0x28 - Z+R pointer register, parameter set 2"] + #[inline(always)] + pub const fn pkc_zrptr2(&self) -> &PkcZrptr2 { + &self.pkc_zrptr2 + } + #[doc = "0x2c - Length register, parameter set 2"] + #[inline(always)] + pub const fn pkc_len2(&self) -> &PkcLen2 { + &self.pkc_len2 + } + #[doc = "0x40 - Universal pointer FUP program"] + #[inline(always)] + pub const fn pkc_uptr(&self) -> &PkcUptr { + &self.pkc_uptr + } + #[doc = "0x44 - Universal pointer FUP table"] + #[inline(always)] + pub const fn pkc_uptrt(&self) -> &PkcUptrt { + &self.pkc_uptrt + } + #[doc = "0x48 - Universal pointer length"] + #[inline(always)] + pub const fn pkc_ulen(&self) -> &PkcUlen { + &self.pkc_ulen + } + #[doc = "0x50 - MC pattern data interface"] + #[inline(always)] + pub const fn pkc_mcdata(&self) -> &PkcMcdata { + &self.pkc_mcdata + } + #[doc = "0x60 - PKC version register"] + #[inline(always)] + pub const fn pkc_version(&self) -> &PkcVersion { + &self.pkc_version + } + #[doc = "0xfb0 - Software reset"] + #[inline(always)] + pub const fn pkc_soft_rst(&self) -> &PkcSoftRst { + &self.pkc_soft_rst + } + #[doc = "0xfc0 - Access Error"] + #[inline(always)] + pub const fn pkc_access_err(&self) -> &PkcAccessErr { + &self.pkc_access_err + } + #[doc = "0xfc4 - Clear Access Error"] + #[inline(always)] + pub const fn pkc_access_err_clr(&self) -> &PkcAccessErrClr { + &self.pkc_access_err_clr + } + #[doc = "0xfd8 - Interrupt enable clear"] + #[inline(always)] + pub const fn pkc_int_clr_enable(&self) -> &PkcIntClrEnable { + &self.pkc_int_clr_enable + } + #[doc = "0xfdc - Interrupt enable set"] + #[inline(always)] + pub const fn pkc_int_set_enable(&self) -> &PkcIntSetEnable { + &self.pkc_int_set_enable + } + #[doc = "0xfe0 - Interrupt status"] + #[inline(always)] + pub const fn pkc_int_status(&self) -> &PkcIntStatus { + &self.pkc_int_status + } + #[doc = "0xfe4 - Interrupt enable"] + #[inline(always)] + pub const fn pkc_int_enable(&self) -> &PkcIntEnable { + &self.pkc_int_enable + } + #[doc = "0xfe8 - Interrupt status clear"] + #[inline(always)] + pub const fn pkc_int_clr_status(&self) -> &PkcIntClrStatus { + &self.pkc_int_clr_status + } + #[doc = "0xfec - Interrupt status set"] + #[inline(always)] + pub const fn pkc_int_set_status(&self) -> &PkcIntSetStatus { + &self.pkc_int_set_status + } + #[doc = "0xffc - Module ID"] + #[inline(always)] + pub const fn pkc_module_id(&self) -> &PkcModuleId { + &self.pkc_module_id + } +} +#[doc = "PKC_STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_status`] module"] +#[doc(alias = "PKC_STATUS")] +pub type PkcStatus = crate::Reg; +#[doc = "Status Register"] +pub mod pkc_status; +#[doc = "PKC_CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_ctrl`] module"] +#[doc(alias = "PKC_CTRL")] +pub type PkcCtrl = crate::Reg; +#[doc = "Control Register"] +pub mod pkc_ctrl; +#[doc = "PKC_CFG (rw) register accessor: Configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_cfg`] module"] +#[doc(alias = "PKC_CFG")] +pub type PkcCfg = crate::Reg; +#[doc = "Configuration register"] +pub mod pkc_cfg; +#[doc = "PKC_MODE1 (rw) register accessor: Mode register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_mode1`] module"] +#[doc(alias = "PKC_MODE1")] +pub type PkcMode1 = crate::Reg; +#[doc = "Mode register, parameter set 1"] +pub mod pkc_mode1; +#[doc = "PKC_XYPTR1 (rw) register accessor: X+Y pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_xyptr1`] module"] +#[doc(alias = "PKC_XYPTR1")] +pub type PkcXyptr1 = crate::Reg; +#[doc = "X+Y pointer register, parameter set 1"] +pub mod pkc_xyptr1; +#[doc = "PKC_ZRPTR1 (rw) register accessor: Z+R pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_zrptr1`] module"] +#[doc(alias = "PKC_ZRPTR1")] +pub type PkcZrptr1 = crate::Reg; +#[doc = "Z+R pointer register, parameter set 1"] +pub mod pkc_zrptr1; +#[doc = "PKC_LEN1 (rw) register accessor: Length register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_len1`] module"] +#[doc(alias = "PKC_LEN1")] +pub type PkcLen1 = crate::Reg; +#[doc = "Length register, parameter set 1"] +pub mod pkc_len1; +#[doc = "PKC_MODE2 (rw) register accessor: Mode register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_mode2`] module"] +#[doc(alias = "PKC_MODE2")] +pub type PkcMode2 = crate::Reg; +#[doc = "Mode register, parameter set 2"] +pub mod pkc_mode2; +#[doc = "PKC_XYPTR2 (rw) register accessor: X+Y pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_xyptr2`] module"] +#[doc(alias = "PKC_XYPTR2")] +pub type PkcXyptr2 = crate::Reg; +#[doc = "X+Y pointer register, parameter set 2"] +pub mod pkc_xyptr2; +#[doc = "PKC_ZRPTR2 (rw) register accessor: Z+R pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_zrptr2`] module"] +#[doc(alias = "PKC_ZRPTR2")] +pub type PkcZrptr2 = crate::Reg; +#[doc = "Z+R pointer register, parameter set 2"] +pub mod pkc_zrptr2; +#[doc = "PKC_LEN2 (rw) register accessor: Length register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_len2`] module"] +#[doc(alias = "PKC_LEN2")] +pub type PkcLen2 = crate::Reg; +#[doc = "Length register, parameter set 2"] +pub mod pkc_len2; +#[doc = "PKC_UPTR (rw) register accessor: Universal pointer FUP program\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_uptr`] module"] +#[doc(alias = "PKC_UPTR")] +pub type PkcUptr = crate::Reg; +#[doc = "Universal pointer FUP program"] +pub mod pkc_uptr; +#[doc = "PKC_UPTRT (rw) register accessor: Universal pointer FUP table\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptrt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptrt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_uptrt`] module"] +#[doc(alias = "PKC_UPTRT")] +pub type PkcUptrt = crate::Reg; +#[doc = "Universal pointer FUP table"] +pub mod pkc_uptrt; +#[doc = "PKC_ULEN (rw) register accessor: Universal pointer length\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ulen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ulen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_ulen`] module"] +#[doc(alias = "PKC_ULEN")] +pub type PkcUlen = crate::Reg; +#[doc = "Universal pointer length"] +pub mod pkc_ulen; +#[doc = "PKC_MCDATA (rw) register accessor: MC pattern data interface\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mcdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mcdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_mcdata`] module"] +#[doc(alias = "PKC_MCDATA")] +pub type PkcMcdata = crate::Reg; +#[doc = "MC pattern data interface"] +pub mod pkc_mcdata; +#[doc = "PKC_VERSION (r) register accessor: PKC version register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_version`] module"] +#[doc(alias = "PKC_VERSION")] +pub type PkcVersion = crate::Reg; +#[doc = "PKC version register"] +pub mod pkc_version; +#[doc = "PKC_SOFT_RST (w) register accessor: Software reset\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_soft_rst::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_soft_rst`] module"] +#[doc(alias = "PKC_SOFT_RST")] +pub type PkcSoftRst = crate::Reg; +#[doc = "Software reset"] +pub mod pkc_soft_rst; +#[doc = "PKC_ACCESS_ERR (r) register accessor: Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_access_err::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_access_err`] module"] +#[doc(alias = "PKC_ACCESS_ERR")] +pub type PkcAccessErr = crate::Reg; +#[doc = "Access Error"] +pub mod pkc_access_err; +#[doc = "PKC_ACCESS_ERR_CLR (w) register accessor: Clear Access Error\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_access_err_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_access_err_clr`] module"] +#[doc(alias = "PKC_ACCESS_ERR_CLR")] +pub type PkcAccessErrClr = crate::Reg; +#[doc = "Clear Access Error"] +pub mod pkc_access_err_clr; +#[doc = "PKC_INT_CLR_ENABLE (w) register accessor: Interrupt enable clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_enable::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_clr_enable`] module"] +#[doc(alias = "PKC_INT_CLR_ENABLE")] +pub type PkcIntClrEnable = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod pkc_int_clr_enable; +#[doc = "PKC_INT_SET_ENABLE (w) register accessor: Interrupt enable set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_enable::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_set_enable`] module"] +#[doc(alias = "PKC_INT_SET_ENABLE")] +pub type PkcIntSetEnable = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod pkc_int_set_enable; +#[doc = "PKC_INT_STATUS (r) register accessor: Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_status`] module"] +#[doc(alias = "PKC_INT_STATUS")] +pub type PkcIntStatus = crate::Reg; +#[doc = "Interrupt status"] +pub mod pkc_int_status; +#[doc = "PKC_INT_ENABLE (r) register accessor: Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_enable::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_enable`] module"] +#[doc(alias = "PKC_INT_ENABLE")] +pub type PkcIntEnable = crate::Reg; +#[doc = "Interrupt enable"] +pub mod pkc_int_enable; +#[doc = "PKC_INT_CLR_STATUS (w) register accessor: Interrupt status clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_status::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_clr_status`] module"] +#[doc(alias = "PKC_INT_CLR_STATUS")] +pub type PkcIntClrStatus = crate::Reg; +#[doc = "Interrupt status clear"] +pub mod pkc_int_clr_status; +#[doc = "PKC_INT_SET_STATUS (w) register accessor: Interrupt status set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_status::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_set_status`] module"] +#[doc(alias = "PKC_INT_SET_STATUS")] +pub type PkcIntSetStatus = crate::Reg; +#[doc = "Interrupt status set"] +pub mod pkc_int_set_status; +#[doc = "PKC_MODULE_ID (r) register accessor: Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_module_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_module_id`] module"] +#[doc(alias = "PKC_MODULE_ID")] +pub type PkcModuleId = crate::Reg; +#[doc = "Module ID"] +pub mod pkc_module_id; diff --git a/mcxa276-pac/src/pkc0/pkc_access_err.rs b/mcxa276-pac/src/pkc0/pkc_access_err.rs new file mode 100644 index 000000000..7fe9538a9 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_access_err.rs @@ -0,0 +1,69 @@ +#[doc = "Register `PKC_ACCESS_ERR` reader"] +pub type R = crate::R; +#[doc = "Field `APB_NOTAV` reader - APB Error"] +pub type ApbNotavR = crate::BitReader; +#[doc = "Field `APB_WRGMD` reader - APB Error"] +pub type ApbWrgmdR = crate::BitReader; +#[doc = "Field `APB_MASTER` reader - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV)"] +pub type ApbMasterR = crate::FieldReader; +#[doc = "Field `AHB` reader - AHB Error"] +pub type AhbR = crate::BitReader; +#[doc = "Field `PKCC` reader - Error in PKC coprocessor kernel"] +pub type PkccR = crate::BitReader; +#[doc = "Field `FDET` reader - Error due to error detection circuitry"] +pub type FdetR = crate::BitReader; +#[doc = "Field `CTRL` reader - Error in PKC software control"] +pub type CtrlR = crate::BitReader; +#[doc = "Field `UCRC` reader - Error in layer2 CRC check."] +pub type UcrcR = crate::BitReader; +impl R { + #[doc = "Bit 0 - APB Error"] + #[inline(always)] + pub fn apb_notav(&self) -> ApbNotavR { + ApbNotavR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - APB Error"] + #[inline(always)] + pub fn apb_wrgmd(&self) -> ApbWrgmdR { + ApbWrgmdR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:7 - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV)"] + #[inline(always)] + pub fn apb_master(&self) -> ApbMasterR { + ApbMasterR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 10 - AHB Error"] + #[inline(always)] + pub fn ahb(&self) -> AhbR { + AhbR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 16 - Error in PKC coprocessor kernel"] + #[inline(always)] + pub fn pkcc(&self) -> PkccR { + PkccR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Error due to error detection circuitry"] + #[inline(always)] + pub fn fdet(&self) -> FdetR { + FdetR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Error in PKC software control"] + #[inline(always)] + pub fn ctrl(&self) -> CtrlR { + CtrlR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Error in layer2 CRC check."] + #[inline(always)] + pub fn ucrc(&self) -> UcrcR { + UcrcR::new(((self.bits >> 19) & 1) != 0) + } +} +#[doc = "Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_access_err::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcAccessErrSpec; +impl crate::RegisterSpec for PkcAccessErrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_access_err::R`](R) reader structure"] +impl crate::Readable for PkcAccessErrSpec {} +#[doc = "`reset()` method sets PKC_ACCESS_ERR to value 0"] +impl crate::Resettable for PkcAccessErrSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_access_err_clr.rs b/mcxa276-pac/src/pkc0/pkc_access_err_clr.rs new file mode 100644 index 000000000..f0bc34a5b --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_access_err_clr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PKC_ACCESS_ERR_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `ERR_CLR` writer - Write 1 to reset PKC_ACCESS_ERR SFR."] +pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Write 1 to reset PKC_ACCESS_ERR SFR."] + #[inline(always)] + pub fn err_clr(&mut self) -> ErrClrW { + ErrClrW::new(self, 0) + } +} +#[doc = "Clear Access Error\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_access_err_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcAccessErrClrSpec; +impl crate::RegisterSpec for PkcAccessErrClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`pkc_access_err_clr::W`](W) writer structure"] +impl crate::Writable for PkcAccessErrClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_ACCESS_ERR_CLR to value 0"] +impl crate::Resettable for PkcAccessErrClrSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_cfg.rs b/mcxa276-pac/src/pkc0/pkc_cfg.rs new file mode 100644 index 000000000..0def608fc --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_cfg.rs @@ -0,0 +1,149 @@ +#[doc = "Register `PKC_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `IDLEOP` reader - Idle operation feature not available in this version (flag is don't care)."] +pub type IdleopR = crate::BitReader; +#[doc = "Field `IDLEOP` writer - Idle operation feature not available in this version (flag is don't care)."] +pub type IdleopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RFU1` reader - RFU"] +pub type Rfu1R = crate::BitReader; +#[doc = "Field `RFU1` writer - RFU"] +pub type Rfu1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RFU2` reader - RFU"] +pub type Rfu2R = crate::BitReader; +#[doc = "Field `RFU2` writer - RFU"] +pub type Rfu2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLKRND` reader - Clock randomization feature not available in this version (flag is don't care)."] +pub type ClkrndR = crate::BitReader; +#[doc = "Field `CLKRND` writer - Clock randomization feature not available in this version (flag is don't care)."] +pub type ClkrndW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REDMULNOISE` reader - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] +pub type RedmulnoiseR = crate::BitReader; +#[doc = "Field `REDMULNOISE` writer - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] +pub type RedmulnoiseW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RNDDLY` reader - Random delay feature not available in this version (flag is don't care)."] +pub type RnddlyR = crate::FieldReader; +#[doc = "Field `RNDDLY` writer - Random delay feature not available in this version (flag is don't care)."] +pub type RnddlyW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SBXNOISE` reader - Noise feature not available in this version (flag is don't care)."] +pub type SbxnoiseR = crate::BitReader; +#[doc = "Field `SBXNOISE` writer - Noise feature not available in this version (flag is don't care)."] +pub type SbxnoiseW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALPNOISE` reader - Noise feature not available in this version (flag is don't care)."] +pub type AlpnoiseR = crate::BitReader; +#[doc = "Field `ALPNOISE` writer - Noise feature not available in this version (flag is don't care)."] +pub type AlpnoiseW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FMULNOISE` reader - Noise feature not available in this version (flag is don't care)."] +pub type FmulnoiseR = crate::BitReader; +#[doc = "Field `FMULNOISE` writer - Noise feature not available in this version (flag is don't care)."] +pub type FmulnoiseW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Idle operation feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn idleop(&self) -> IdleopR { + IdleopR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RFU"] + #[inline(always)] + pub fn rfu1(&self) -> Rfu1R { + Rfu1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RFU"] + #[inline(always)] + pub fn rfu2(&self) -> Rfu2R { + Rfu2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clock randomization feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn clkrnd(&self) -> ClkrndR { + ClkrndR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn redmulnoise(&self) -> RedmulnoiseR { + RedmulnoiseR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - Random delay feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn rnddly(&self) -> RnddlyR { + RnddlyR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - Noise feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn sbxnoise(&self) -> SbxnoiseR { + SbxnoiseR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Noise feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn alpnoise(&self) -> AlpnoiseR { + AlpnoiseR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Noise feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn fmulnoise(&self) -> FmulnoiseR { + FmulnoiseR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Idle operation feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn idleop(&mut self) -> IdleopW { + IdleopW::new(self, 0) + } + #[doc = "Bit 1 - RFU"] + #[inline(always)] + pub fn rfu1(&mut self) -> Rfu1W { + Rfu1W::new(self, 1) + } + #[doc = "Bit 2 - RFU"] + #[inline(always)] + pub fn rfu2(&mut self) -> Rfu2W { + Rfu2W::new(self, 2) + } + #[doc = "Bit 3 - Clock randomization feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn clkrnd(&mut self) -> ClkrndW { + ClkrndW::new(self, 3) + } + #[doc = "Bit 4 - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn redmulnoise(&mut self) -> RedmulnoiseW { + RedmulnoiseW::new(self, 4) + } + #[doc = "Bits 5:7 - Random delay feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn rnddly(&mut self) -> RnddlyW { + RnddlyW::new(self, 5) + } + #[doc = "Bit 8 - Noise feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn sbxnoise(&mut self) -> SbxnoiseW { + SbxnoiseW::new(self, 8) + } + #[doc = "Bit 9 - Noise feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn alpnoise(&mut self) -> AlpnoiseW { + AlpnoiseW::new(self, 9) + } + #[doc = "Bit 10 - Noise feature not available in this version (flag is don't care)."] + #[inline(always)] + pub fn fmulnoise(&mut self) -> FmulnoiseW { + FmulnoiseW::new(self, 10) + } +} +#[doc = "Configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcCfgSpec; +impl crate::RegisterSpec for PkcCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_cfg::R`](R) reader structure"] +impl crate::Readable for PkcCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`pkc_cfg::W`](W) writer structure"] +impl crate::Writable for PkcCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_CFG to value 0x0719"] +impl crate::Resettable for PkcCfgSpec { + const RESET_VALUE: u32 = 0x0719; +} diff --git a/mcxa276-pac/src/pkc0/pkc_ctrl.rs b/mcxa276-pac/src/pkc0/pkc_ctrl.rs new file mode 100644 index 000000000..7b0296d70 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_ctrl.rs @@ -0,0 +1,191 @@ +#[doc = "Register `PKC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `RESET` reader - PKC reset control bit"] +pub type ResetR = crate::BitReader; +#[doc = "Field `RESET` writer - PKC reset control bit"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STOP` reader - Freeze PKC calculation"] +pub type StopR = crate::BitReader; +#[doc = "Field `STOP` writer - Freeze PKC calculation"] +pub type StopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GOD1` writer - Control bit to start direct operation using parameter set 1"] +pub type God1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GOD2` writer - Control bit to start direct operation using parameter set 2"] +pub type God2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GOM1` writer - Control bit to start MC pattern using parameter set 1"] +pub type Gom1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GOM2` writer - Control bit to start MC pattern using parameter set 2"] +pub type Gom2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GOU` writer - Control bit to start pipe operation"] +pub type GouW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GF2CONV` reader - Convert to GF2 calculation modes"] +pub type Gf2convR = crate::BitReader; +#[doc = "Field `GF2CONV` writer - Convert to GF2 calculation modes"] +pub type Gf2convW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLRCACHE` writer - Clear universal pointer cache"] +pub type ClrcacheW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CACHE_EN` reader - Enable universal pointer cache"] +pub type CacheEnR = crate::BitReader; +#[doc = "Field `CACHE_EN` writer - Enable universal pointer cache"] +pub type CacheEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Reduced multiplier mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Redmul { + #[doc = "0: full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] + Fullsz = 0, + #[doc = "2: 64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] + Value64bit = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Redmul) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Redmul { + type Ux = u8; +} +impl crate::IsEnum for Redmul {} +#[doc = "Field `REDMUL` reader - Reduced multiplier mode"] +pub type RedmulR = crate::FieldReader; +impl RedmulR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Redmul::Fullsz), + 2 => Some(Redmul::Value64bit), + _ => None, + } + } + #[doc = "full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] + #[inline(always)] + pub fn is_fullsz(&self) -> bool { + *self == Redmul::Fullsz + } + #[doc = "64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] + #[inline(always)] + pub fn is_value_64bit(&self) -> bool { + *self == Redmul::Value64bit + } +} +#[doc = "Field `REDMUL` writer - Reduced multiplier mode"] +pub type RedmulW<'a, REG> = crate::FieldWriter<'a, REG, 2, Redmul>; +impl<'a, REG> RedmulW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] + #[inline(always)] + pub fn fullsz(self) -> &'a mut crate::W { + self.variant(Redmul::Fullsz) + } + #[doc = "64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] + #[inline(always)] + pub fn value_64bit(self) -> &'a mut crate::W { + self.variant(Redmul::Value64bit) + } +} +impl R { + #[doc = "Bit 0 - PKC reset control bit"] + #[inline(always)] + pub fn reset(&self) -> ResetR { + ResetR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Freeze PKC calculation"] + #[inline(always)] + pub fn stop(&self) -> StopR { + StopR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 7 - Convert to GF2 calculation modes"] + #[inline(always)] + pub fn gf2conv(&self) -> Gf2convR { + Gf2convR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Enable universal pointer cache"] + #[inline(always)] + pub fn cache_en(&self) -> CacheEnR { + CacheEnR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - Reduced multiplier mode"] + #[inline(always)] + pub fn redmul(&self) -> RedmulR { + RedmulR::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - PKC reset control bit"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 0) + } + #[doc = "Bit 1 - Freeze PKC calculation"] + #[inline(always)] + pub fn stop(&mut self) -> StopW { + StopW::new(self, 1) + } + #[doc = "Bit 2 - Control bit to start direct operation using parameter set 1"] + #[inline(always)] + pub fn god1(&mut self) -> God1W { + God1W::new(self, 2) + } + #[doc = "Bit 3 - Control bit to start direct operation using parameter set 2"] + #[inline(always)] + pub fn god2(&mut self) -> God2W { + God2W::new(self, 3) + } + #[doc = "Bit 4 - Control bit to start MC pattern using parameter set 1"] + #[inline(always)] + pub fn gom1(&mut self) -> Gom1W { + Gom1W::new(self, 4) + } + #[doc = "Bit 5 - Control bit to start MC pattern using parameter set 2"] + #[inline(always)] + pub fn gom2(&mut self) -> Gom2W { + Gom2W::new(self, 5) + } + #[doc = "Bit 6 - Control bit to start pipe operation"] + #[inline(always)] + pub fn gou(&mut self) -> GouW { + GouW::new(self, 6) + } + #[doc = "Bit 7 - Convert to GF2 calculation modes"] + #[inline(always)] + pub fn gf2conv(&mut self) -> Gf2convW { + Gf2convW::new(self, 7) + } + #[doc = "Bit 8 - Clear universal pointer cache"] + #[inline(always)] + pub fn clrcache(&mut self) -> ClrcacheW { + ClrcacheW::new(self, 8) + } + #[doc = "Bit 9 - Enable universal pointer cache"] + #[inline(always)] + pub fn cache_en(&mut self) -> CacheEnW { + CacheEnW::new(self, 9) + } + #[doc = "Bits 10:11 - Reduced multiplier mode"] + #[inline(always)] + pub fn redmul(&mut self) -> RedmulW { + RedmulW::new(self, 10) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcCtrlSpec; +impl crate::RegisterSpec for PkcCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_ctrl::R`](R) reader structure"] +impl crate::Readable for PkcCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`pkc_ctrl::W`](W) writer structure"] +impl crate::Writable for PkcCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_CTRL to value 0x01"] +impl crate::Resettable for PkcCtrlSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs b/mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs new file mode 100644 index 000000000..0e0b45ed8 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PKC_INT_CLR_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `EN_PDONE` writer - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=0)."] +pub type EnPdoneW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=0)."] + #[inline(always)] + pub fn en_pdone(&mut self) -> EnPdoneW { + EnPdoneW::new(self, 0) + } +} +#[doc = "Interrupt enable clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_enable::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcIntClrEnableSpec; +impl crate::RegisterSpec for PkcIntClrEnableSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`pkc_int_clr_enable::W`](W) writer structure"] +impl crate::Writable for PkcIntClrEnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_INT_CLR_ENABLE to value 0"] +impl crate::Resettable for PkcIntClrEnableSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_clr_status.rs b/mcxa276-pac/src/pkc0/pkc_int_clr_status.rs new file mode 100644 index 000000000..16f6f47e5 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_int_clr_status.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PKC_INT_CLR_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `INT_PDONE` writer - Write to clear End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=0)."] +pub type IntPdoneW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Write to clear End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=0)."] + #[inline(always)] + pub fn int_pdone(&mut self) -> IntPdoneW { + IntPdoneW::new(self, 0) + } +} +#[doc = "Interrupt status clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_status::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcIntClrStatusSpec; +impl crate::RegisterSpec for PkcIntClrStatusSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`pkc_int_clr_status::W`](W) writer structure"] +impl crate::Writable for PkcIntClrStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_INT_CLR_STATUS to value 0"] +impl crate::Resettable for PkcIntClrStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_enable.rs b/mcxa276-pac/src/pkc0/pkc_int_enable.rs new file mode 100644 index 000000000..971736c5d --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_int_enable.rs @@ -0,0 +1,20 @@ +#[doc = "Register `PKC_INT_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Field `EN_PDONE` reader - PDONE interrupt enable flag"] +pub type EnPdoneR = crate::BitReader; +impl R { + #[doc = "Bit 0 - PDONE interrupt enable flag"] + #[inline(always)] + pub fn en_pdone(&self) -> EnPdoneR { + EnPdoneR::new((self.bits & 1) != 0) + } +} +#[doc = "Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_enable::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcIntEnableSpec; +impl crate::RegisterSpec for PkcIntEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_int_enable::R`](R) reader structure"] +impl crate::Readable for PkcIntEnableSpec {} +#[doc = "`reset()` method sets PKC_INT_ENABLE to value 0"] +impl crate::Resettable for PkcIntEnableSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_set_enable.rs b/mcxa276-pac/src/pkc0/pkc_int_set_enable.rs new file mode 100644 index 000000000..f054c87e5 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_int_set_enable.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PKC_INT_SET_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `EN_PDONE` writer - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=1)."] +pub type EnPdoneW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=1)."] + #[inline(always)] + pub fn en_pdone(&mut self) -> EnPdoneW { + EnPdoneW::new(self, 0) + } +} +#[doc = "Interrupt enable set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_enable::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcIntSetEnableSpec; +impl crate::RegisterSpec for PkcIntSetEnableSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`pkc_int_set_enable::W`](W) writer structure"] +impl crate::Writable for PkcIntSetEnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_INT_SET_ENABLE to value 0"] +impl crate::Resettable for PkcIntSetEnableSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_set_status.rs b/mcxa276-pac/src/pkc0/pkc_int_set_status.rs new file mode 100644 index 000000000..2f903f6d1 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_int_set_status.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PKC_INT_SET_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `INT_PDONE` writer - Write to set End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=1) to trigger a PKC interrupt via software, e"] +pub type IntPdoneW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Write to set End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=1) to trigger a PKC interrupt via software, e"] + #[inline(always)] + pub fn int_pdone(&mut self) -> IntPdoneW { + IntPdoneW::new(self, 0) + } +} +#[doc = "Interrupt status set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_status::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcIntSetStatusSpec; +impl crate::RegisterSpec for PkcIntSetStatusSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`pkc_int_set_status::W`](W) writer structure"] +impl crate::Writable for PkcIntSetStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_INT_SET_STATUS to value 0"] +impl crate::Resettable for PkcIntSetStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_status.rs b/mcxa276-pac/src/pkc0/pkc_int_status.rs new file mode 100644 index 000000000..0eb5b21f9 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_int_status.rs @@ -0,0 +1,20 @@ +#[doc = "Register `PKC_INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `INT_PDONE` reader - End-of-computation status flag"] +pub type IntPdoneR = crate::BitReader; +impl R { + #[doc = "Bit 0 - End-of-computation status flag"] + #[inline(always)] + pub fn int_pdone(&self) -> IntPdoneR { + IntPdoneR::new((self.bits & 1) != 0) + } +} +#[doc = "Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcIntStatusSpec; +impl crate::RegisterSpec for PkcIntStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_int_status::R`](R) reader structure"] +impl crate::Readable for PkcIntStatusSpec {} +#[doc = "`reset()` method sets PKC_INT_STATUS to value 0"] +impl crate::Resettable for PkcIntStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_len1.rs b/mcxa276-pac/src/pkc0/pkc_len1.rs new file mode 100644 index 000000000..bcb2a6553 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_len1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `PKC_LEN1` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_LEN1` writer"] +pub type W = crate::W; +#[doc = "Field `LEN` reader - Operand length"] +pub type LenR = crate::FieldReader; +#[doc = "Field `LEN` writer - Operand length"] +pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `MCLEN` reader - Loop counter for microcode pattern"] +pub type MclenR = crate::FieldReader; +#[doc = "Field `MCLEN` writer - Loop counter for microcode pattern"] +pub type MclenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Operand length"] + #[inline(always)] + pub fn len(&self) -> LenR { + LenR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Loop counter for microcode pattern"] + #[inline(always)] + pub fn mclen(&self) -> MclenR { + MclenR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Operand length"] + #[inline(always)] + pub fn len(&mut self) -> LenW { + LenW::new(self, 0) + } + #[doc = "Bits 16:31 - Loop counter for microcode pattern"] + #[inline(always)] + pub fn mclen(&mut self) -> MclenW { + MclenW::new(self, 16) + } +} +#[doc = "Length register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcLen1Spec; +impl crate::RegisterSpec for PkcLen1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_len1::R`](R) reader structure"] +impl crate::Readable for PkcLen1Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_len1::W`](W) writer structure"] +impl crate::Writable for PkcLen1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_LEN1 to value 0"] +impl crate::Resettable for PkcLen1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_len2.rs b/mcxa276-pac/src/pkc0/pkc_len2.rs new file mode 100644 index 000000000..7c6585d9a --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_len2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `PKC_LEN2` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_LEN2` writer"] +pub type W = crate::W; +#[doc = "Field `LEN` reader - Operand length"] +pub type LenR = crate::FieldReader; +#[doc = "Field `LEN` writer - Operand length"] +pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `MCLEN` reader - Loop counter for microcode pattern"] +pub type MclenR = crate::FieldReader; +#[doc = "Field `MCLEN` writer - Loop counter for microcode pattern"] +pub type MclenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Operand length"] + #[inline(always)] + pub fn len(&self) -> LenR { + LenR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Loop counter for microcode pattern"] + #[inline(always)] + pub fn mclen(&self) -> MclenR { + MclenR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Operand length"] + #[inline(always)] + pub fn len(&mut self) -> LenW { + LenW::new(self, 0) + } + #[doc = "Bits 16:31 - Loop counter for microcode pattern"] + #[inline(always)] + pub fn mclen(&mut self) -> MclenW { + MclenW::new(self, 16) + } +} +#[doc = "Length register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcLen2Spec; +impl crate::RegisterSpec for PkcLen2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_len2::R`](R) reader structure"] +impl crate::Readable for PkcLen2Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_len2::W`](W) writer structure"] +impl crate::Writable for PkcLen2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_LEN2 to value 0"] +impl crate::Resettable for PkcLen2Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_mcdata.rs b/mcxa276-pac/src/pkc0/pkc_mcdata.rs new file mode 100644 index 000000000..e1816eaec --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_mcdata.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PKC_MCDATA` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_MCDATA` writer"] +pub type W = crate::W; +#[doc = "Field `MCDATA` reader - Microcode read/write data"] +pub type McdataR = crate::FieldReader; +#[doc = "Field `MCDATA` writer - Microcode read/write data"] +pub type McdataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Microcode read/write data"] + #[inline(always)] + pub fn mcdata(&self) -> McdataR { + McdataR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Microcode read/write data"] + #[inline(always)] + pub fn mcdata(&mut self) -> McdataW { + McdataW::new(self, 0) + } +} +#[doc = "MC pattern data interface\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mcdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mcdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcMcdataSpec; +impl crate::RegisterSpec for PkcMcdataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_mcdata::R`](R) reader structure"] +impl crate::Readable for PkcMcdataSpec {} +#[doc = "`write(|w| ..)` method takes [`pkc_mcdata::W`](W) writer structure"] +impl crate::Writable for PkcMcdataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_MCDATA to value 0"] +impl crate::Resettable for PkcMcdataSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_mode1.rs b/mcxa276-pac/src/pkc0/pkc_mode1.rs new file mode 100644 index 000000000..733b239a8 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_mode1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PKC_MODE1` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_MODE1` writer"] +pub type W = crate::W; +#[doc = "Field `MODE` reader - Calculation Mode / MC Start address"] +pub type ModeR = crate::FieldReader; +#[doc = "Field `MODE` writer - Calculation Mode / MC Start address"] +pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 0) + } +} +#[doc = "Mode register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcMode1Spec; +impl crate::RegisterSpec for PkcMode1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_mode1::R`](R) reader structure"] +impl crate::Readable for PkcMode1Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_mode1::W`](W) writer structure"] +impl crate::Writable for PkcMode1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_MODE1 to value 0"] +impl crate::Resettable for PkcMode1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_mode2.rs b/mcxa276-pac/src/pkc0/pkc_mode2.rs new file mode 100644 index 000000000..b49bd60ad --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_mode2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PKC_MODE2` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_MODE2` writer"] +pub type W = crate::W; +#[doc = "Field `MODE` reader - Calculation Mode / MC Start address"] +pub type ModeR = crate::FieldReader; +#[doc = "Field `MODE` writer - Calculation Mode / MC Start address"] +pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] + #[inline(always)] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 0) + } +} +#[doc = "Mode register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcMode2Spec; +impl crate::RegisterSpec for PkcMode2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_mode2::R`](R) reader structure"] +impl crate::Readable for PkcMode2Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_mode2::W`](W) writer structure"] +impl crate::Writable for PkcMode2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_MODE2 to value 0"] +impl crate::Resettable for PkcMode2Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_module_id.rs b/mcxa276-pac/src/pkc0/pkc_module_id.rs new file mode 100644 index 000000000..ae229fdf9 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_module_id.rs @@ -0,0 +1,43 @@ +#[doc = "Register `PKC_MODULE_ID` reader"] +pub type R = crate::R; +#[doc = "Field `SIZE` reader - Address space of the IP"] +pub type SizeR = crate::FieldReader; +#[doc = "Field `MINOR_REV` reader - Minor revision"] +pub type MinorRevR = crate::FieldReader; +#[doc = "Field `MAJOR_REV` reader - Major revision"] +pub type MajorRevR = crate::FieldReader; +#[doc = "Field `ID` reader - Module ID"] +pub type IdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Address space of the IP"] + #[inline(always)] + pub fn size(&self) -> SizeR { + SizeR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Minor revision"] + #[inline(always)] + pub fn minor_rev(&self) -> MinorRevR { + MinorRevR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Major revision"] + #[inline(always)] + pub fn major_rev(&self) -> MajorRevR { + MajorRevR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:31 - Module ID"] + #[inline(always)] + pub fn id(&self) -> IdR { + IdR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_module_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcModuleIdSpec; +impl crate::RegisterSpec for PkcModuleIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_module_id::R`](R) reader structure"] +impl crate::Readable for PkcModuleIdSpec {} +#[doc = "`reset()` method sets PKC_MODULE_ID to value 0xe103_1280"] +impl crate::Resettable for PkcModuleIdSpec { + const RESET_VALUE: u32 = 0xe103_1280; +} diff --git a/mcxa276-pac/src/pkc0/pkc_soft_rst.rs b/mcxa276-pac/src/pkc0/pkc_soft_rst.rs new file mode 100644 index 000000000..72360a81d --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_soft_rst.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PKC_SOFT_RST` writer"] +pub type W = crate::W; +#[doc = "Field `SOFT_RST` writer - Write 1 to reset module (0 has no effect)"] +pub type SoftRstW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Write 1 to reset module (0 has no effect)"] + #[inline(always)] + pub fn soft_rst(&mut self) -> SoftRstW { + SoftRstW::new(self, 0) + } +} +#[doc = "Software reset\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_soft_rst::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcSoftRstSpec; +impl crate::RegisterSpec for PkcSoftRstSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`pkc_soft_rst::W`](W) writer structure"] +impl crate::Writable for PkcSoftRstSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_SOFT_RST to value 0"] +impl crate::Resettable for PkcSoftRstSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_status.rs b/mcxa276-pac/src/pkc0/pkc_status.rs new file mode 100644 index 000000000..cc2e126ce --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_status.rs @@ -0,0 +1,48 @@ +#[doc = "Register `PKC_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `ACTIV` reader - PKC ACTIV"] +pub type ActivR = crate::BitReader; +#[doc = "Field `CARRY` reader - Carry overflow flag"] +pub type CarryR = crate::BitReader; +#[doc = "Field `ZERO` reader - Zero result flag"] +pub type ZeroR = crate::BitReader; +#[doc = "Field `GOANY` reader - Combined GO status flag"] +pub type GoanyR = crate::BitReader; +#[doc = "Field `LOCKED` reader - Parameter set locked"] +pub type LockedR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - PKC ACTIV"] + #[inline(always)] + pub fn activ(&self) -> ActivR { + ActivR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Carry overflow flag"] + #[inline(always)] + pub fn carry(&self) -> CarryR { + CarryR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Zero result flag"] + #[inline(always)] + pub fn zero(&self) -> ZeroR { + ZeroR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Combined GO status flag"] + #[inline(always)] + pub fn goany(&self) -> GoanyR { + GoanyR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 5:6 - Parameter set locked"] + #[inline(always)] + pub fn locked(&self) -> LockedR { + LockedR::new(((self.bits >> 5) & 3) as u8) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcStatusSpec; +impl crate::RegisterSpec for PkcStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_status::R`](R) reader structure"] +impl crate::Readable for PkcStatusSpec {} +#[doc = "`reset()` method sets PKC_STATUS to value 0"] +impl crate::Resettable for PkcStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_ulen.rs b/mcxa276-pac/src/pkc0/pkc_ulen.rs new file mode 100644 index 000000000..c7e60050c --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_ulen.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PKC_ULEN` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_ULEN` writer"] +pub type W = crate::W; +#[doc = "Field `LEN` reader - Length of universal pointer calculation"] +pub type LenR = crate::FieldReader; +#[doc = "Field `LEN` writer - Length of universal pointer calculation"] +pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Length of universal pointer calculation"] + #[inline(always)] + pub fn len(&self) -> LenR { + LenR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Length of universal pointer calculation"] + #[inline(always)] + pub fn len(&mut self) -> LenW { + LenW::new(self, 0) + } +} +#[doc = "Universal pointer length\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ulen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ulen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcUlenSpec; +impl crate::RegisterSpec for PkcUlenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_ulen::R`](R) reader structure"] +impl crate::Readable for PkcUlenSpec {} +#[doc = "`write(|w| ..)` method takes [`pkc_ulen::W`](W) writer structure"] +impl crate::Writable for PkcUlenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_ULEN to value 0"] +impl crate::Resettable for PkcUlenSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_uptr.rs b/mcxa276-pac/src/pkc0/pkc_uptr.rs new file mode 100644 index 000000000..8c591a256 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_uptr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PKC_UPTR` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_UPTR` writer"] +pub type W = crate::W; +#[doc = "Field `PTR` reader - Pointer to start address of PKC FUP program"] +pub type PtrR = crate::FieldReader; +#[doc = "Field `PTR` writer - Pointer to start address of PKC FUP program"] +pub type PtrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Pointer to start address of PKC FUP program"] + #[inline(always)] + pub fn ptr(&self) -> PtrR { + PtrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Pointer to start address of PKC FUP program"] + #[inline(always)] + pub fn ptr(&mut self) -> PtrW { + PtrW::new(self, 0) + } +} +#[doc = "Universal pointer FUP program\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcUptrSpec; +impl crate::RegisterSpec for PkcUptrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_uptr::R`](R) reader structure"] +impl crate::Readable for PkcUptrSpec {} +#[doc = "`write(|w| ..)` method takes [`pkc_uptr::W`](W) writer structure"] +impl crate::Writable for PkcUptrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_UPTR to value 0"] +impl crate::Resettable for PkcUptrSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_uptrt.rs b/mcxa276-pac/src/pkc0/pkc_uptrt.rs new file mode 100644 index 000000000..177dd953e --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_uptrt.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PKC_UPTRT` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_UPTRT` writer"] +pub type W = crate::W; +#[doc = "Field `PTR` reader - Pointer to start address of PKC FUP table"] +pub type PtrR = crate::FieldReader; +#[doc = "Field `PTR` writer - Pointer to start address of PKC FUP table"] +pub type PtrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Pointer to start address of PKC FUP table"] + #[inline(always)] + pub fn ptr(&self) -> PtrR { + PtrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Pointer to start address of PKC FUP table"] + #[inline(always)] + pub fn ptr(&mut self) -> PtrW { + PtrW::new(self, 0) + } +} +#[doc = "Universal pointer FUP table\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptrt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptrt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcUptrtSpec; +impl crate::RegisterSpec for PkcUptrtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_uptrt::R`](R) reader structure"] +impl crate::Readable for PkcUptrtSpec {} +#[doc = "`write(|w| ..)` method takes [`pkc_uptrt::W`](W) writer structure"] +impl crate::Writable for PkcUptrtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_UPTRT to value 0"] +impl crate::Resettable for PkcUptrtSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_version.rs b/mcxa276-pac/src/pkc0/pkc_version.rs new file mode 100644 index 000000000..c0304eed6 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_version.rs @@ -0,0 +1,124 @@ +#[doc = "Register `PKC_VERSION` reader"] +pub type R = crate::R; +#[doc = "Native multiplier size and operand granularity\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mulsize { + #[doc = "2: 64-bit multiplier"] + Bit64 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mulsize) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mulsize { + type Ux = u8; +} +impl crate::IsEnum for Mulsize {} +#[doc = "Field `MULSIZE` reader - Native multiplier size and operand granularity"] +pub type MulsizeR = crate::FieldReader; +impl MulsizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Mulsize::Bit64), + _ => None, + } + } + #[doc = "64-bit multiplier"] + #[inline(always)] + pub fn is_bit64(&self) -> bool { + *self == Mulsize::Bit64 + } +} +#[doc = "Field `MCAVAIL` reader - MC feature (layer1 calculation) is available"] +pub type McavailR = crate::BitReader; +#[doc = "Field `UPAVAIL` reader - UP feature (layer2 calculation) is available"] +pub type UpavailR = crate::BitReader; +#[doc = "Field `UPCACHEAVAIL` reader - UP cache is available"] +pub type UpcacheavailR = crate::BitReader; +#[doc = "Field `GF2AVAIL` reader - GF2 calculation modes are available"] +pub type Gf2availR = crate::BitReader; +#[doc = "Field `PARAMNUM` reader - Number of parameter sets for real calculation"] +pub type ParamnumR = crate::FieldReader; +#[doc = "Field `SBX0AVAIL` reader - SBX0 operation is available"] +pub type Sbx0availR = crate::BitReader; +#[doc = "Field `SBX1AVAIL` reader - SBX1 operation is available"] +pub type Sbx1availR = crate::BitReader; +#[doc = "Field `SBX2AVAIL` reader - SBX2 operation is available"] +pub type Sbx2availR = crate::BitReader; +#[doc = "Field `SBX3AVAIL` reader - SBX3 operation is available"] +pub type Sbx3availR = crate::BitReader; +#[doc = "Field `MCRECONF_SIZE` reader - Size of reconfigurable MC table in bytes."] +pub type McreconfSizeR = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Native multiplier size and operand granularity"] + #[inline(always)] + pub fn mulsize(&self) -> MulsizeR { + MulsizeR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - MC feature (layer1 calculation) is available"] + #[inline(always)] + pub fn mcavail(&self) -> McavailR { + McavailR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - UP feature (layer2 calculation) is available"] + #[inline(always)] + pub fn upavail(&self) -> UpavailR { + UpavailR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - UP cache is available"] + #[inline(always)] + pub fn upcacheavail(&self) -> UpcacheavailR { + UpcacheavailR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - GF2 calculation modes are available"] + #[inline(always)] + pub fn gf2avail(&self) -> Gf2availR { + Gf2availR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Number of parameter sets for real calculation"] + #[inline(always)] + pub fn paramnum(&self) -> ParamnumR { + ParamnumR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - SBX0 operation is available"] + #[inline(always)] + pub fn sbx0avail(&self) -> Sbx0availR { + Sbx0availR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SBX1 operation is available"] + #[inline(always)] + pub fn sbx1avail(&self) -> Sbx1availR { + Sbx1availR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SBX2 operation is available"] + #[inline(always)] + pub fn sbx2avail(&self) -> Sbx2availR { + Sbx2availR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SBX3 operation is available"] + #[inline(always)] + pub fn sbx3avail(&self) -> Sbx3availR { + Sbx3availR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:19 - Size of reconfigurable MC table in bytes."] + #[inline(always)] + pub fn mcreconf_size(&self) -> McreconfSizeR { + McreconfSizeR::new(((self.bits >> 12) & 0xff) as u8) + } +} +#[doc = "PKC version register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcVersionSpec; +impl crate::RegisterSpec for PkcVersionSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_version::R`](R) reader structure"] +impl crate::Readable for PkcVersionSpec {} +#[doc = "`reset()` method sets PKC_VERSION to value 0xbe"] +impl crate::Resettable for PkcVersionSpec { + const RESET_VALUE: u32 = 0xbe; +} diff --git a/mcxa276-pac/src/pkc0/pkc_xyptr1.rs b/mcxa276-pac/src/pkc0/pkc_xyptr1.rs new file mode 100644 index 000000000..185fb9dfb --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_xyptr1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `PKC_XYPTR1` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_XYPTR1` writer"] +pub type W = crate::W; +#[doc = "Field `XPTR` reader - Start address of X operand in PKCRAM with byte granularity"] +pub type XptrR = crate::FieldReader; +#[doc = "Field `XPTR` writer - Start address of X operand in PKCRAM with byte granularity"] +pub type XptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `YPTR` reader - Start address of Y operand in PKCRAM with byte granularity"] +pub type YptrR = crate::FieldReader; +#[doc = "Field `YPTR` writer - Start address of Y operand in PKCRAM with byte granularity"] +pub type YptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn xptr(&self) -> XptrR { + XptrR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn yptr(&self) -> YptrR { + YptrR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn xptr(&mut self) -> XptrW { + XptrW::new(self, 0) + } + #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn yptr(&mut self) -> YptrW { + YptrW::new(self, 16) + } +} +#[doc = "X+Y pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcXyptr1Spec; +impl crate::RegisterSpec for PkcXyptr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_xyptr1::R`](R) reader structure"] +impl crate::Readable for PkcXyptr1Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_xyptr1::W`](W) writer structure"] +impl crate::Writable for PkcXyptr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_XYPTR1 to value 0"] +impl crate::Resettable for PkcXyptr1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_xyptr2.rs b/mcxa276-pac/src/pkc0/pkc_xyptr2.rs new file mode 100644 index 000000000..6114ba782 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_xyptr2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `PKC_XYPTR2` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_XYPTR2` writer"] +pub type W = crate::W; +#[doc = "Field `XPTR` reader - Start address of X operand in PKCRAM with byte granularity"] +pub type XptrR = crate::FieldReader; +#[doc = "Field `XPTR` writer - Start address of X operand in PKCRAM with byte granularity"] +pub type XptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `YPTR` reader - Start address of Y operand in PKCRAM with byte granularity"] +pub type YptrR = crate::FieldReader; +#[doc = "Field `YPTR` writer - Start address of Y operand in PKCRAM with byte granularity"] +pub type YptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn xptr(&self) -> XptrR { + XptrR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn yptr(&self) -> YptrR { + YptrR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn xptr(&mut self) -> XptrW { + XptrW::new(self, 0) + } + #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] + #[inline(always)] + pub fn yptr(&mut self) -> YptrW { + YptrW::new(self, 16) + } +} +#[doc = "X+Y pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcXyptr2Spec; +impl crate::RegisterSpec for PkcXyptr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_xyptr2::R`](R) reader structure"] +impl crate::Readable for PkcXyptr2Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_xyptr2::W`](W) writer structure"] +impl crate::Writable for PkcXyptr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_XYPTR2 to value 0"] +impl crate::Resettable for PkcXyptr2Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_zrptr1.rs b/mcxa276-pac/src/pkc0/pkc_zrptr1.rs new file mode 100644 index 000000000..fd79d9ac5 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_zrptr1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `PKC_ZRPTR1` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_ZRPTR1` writer"] +pub type W = crate::W; +#[doc = "Field `ZPTR` reader - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] +pub type ZptrR = crate::FieldReader; +#[doc = "Field `ZPTR` writer - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] +pub type ZptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `RPTR` reader - Start address of R result in PKCRAM with byte granularity"] +pub type RptrR = crate::FieldReader; +#[doc = "Field `RPTR` writer - Start address of R result in PKCRAM with byte granularity"] +pub type RptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] + #[inline(always)] + pub fn zptr(&self) -> ZptrR { + ZptrR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] + #[inline(always)] + pub fn rptr(&self) -> RptrR { + RptrR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] + #[inline(always)] + pub fn zptr(&mut self) -> ZptrW { + ZptrW::new(self, 0) + } + #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] + #[inline(always)] + pub fn rptr(&mut self) -> RptrW { + RptrW::new(self, 16) + } +} +#[doc = "Z+R pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcZrptr1Spec; +impl crate::RegisterSpec for PkcZrptr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_zrptr1::R`](R) reader structure"] +impl crate::Readable for PkcZrptr1Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_zrptr1::W`](W) writer structure"] +impl crate::Writable for PkcZrptr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_ZRPTR1 to value 0"] +impl crate::Resettable for PkcZrptr1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_zrptr2.rs b/mcxa276-pac/src/pkc0/pkc_zrptr2.rs new file mode 100644 index 000000000..8c1bd2d87 --- /dev/null +++ b/mcxa276-pac/src/pkc0/pkc_zrptr2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `PKC_ZRPTR2` reader"] +pub type R = crate::R; +#[doc = "Register `PKC_ZRPTR2` writer"] +pub type W = crate::W; +#[doc = "Field `ZPTR` reader - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] +pub type ZptrR = crate::FieldReader; +#[doc = "Field `ZPTR` writer - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] +pub type ZptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `RPTR` reader - Start address of R result in PKCRAM with byte granularity"] +pub type RptrR = crate::FieldReader; +#[doc = "Field `RPTR` writer - Start address of R result in PKCRAM with byte granularity"] +pub type RptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] + #[inline(always)] + pub fn zptr(&self) -> ZptrR { + ZptrR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] + #[inline(always)] + pub fn rptr(&self) -> RptrR { + RptrR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] + #[inline(always)] + pub fn zptr(&mut self) -> ZptrW { + ZptrW::new(self, 0) + } + #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] + #[inline(always)] + pub fn rptr(&mut self) -> RptrW { + RptrW::new(self, 16) + } +} +#[doc = "Z+R pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkcZrptr2Spec; +impl crate::RegisterSpec for PkcZrptr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkc_zrptr2::R`](R) reader structure"] +impl crate::Readable for PkcZrptr2Spec {} +#[doc = "`write(|w| ..)` method takes [`pkc_zrptr2::W`](W) writer structure"] +impl crate::Writable for PkcZrptr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKC_ZRPTR2 to value 0"] +impl crate::Resettable for PkcZrptr2Spec {} diff --git a/mcxa276-pac/src/port0.rs b/mcxa276-pac/src/port0.rs new file mode 100644 index 000000000..d7ed05fc0 --- /dev/null +++ b/mcxa276-pac/src/port0.rs @@ -0,0 +1,428 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x0c], + gpclr: Gpclr, + gpchr: Gpchr, + _reserved3: [u8; 0x08], + config: Config, + _reserved4: [u8; 0x3c], + calib0: Calib0, + calib1: Calib1, + _reserved6: [u8; 0x18], + pcr0: Pcr0, + pcr1: Pcr1, + pcr2: Pcr2, + pcr3: Pcr3, + pcr4: Pcr4, + pcr5: Pcr5, + pcr6: Pcr6, + pcr7: Pcr7, + pcr8: Pcr8, + pcr9: Pcr9, + pcr10: Pcr10, + pcr11: Pcr11, + pcr12: Pcr12, + pcr13: Pcr13, + pcr14: Pcr14, + pcr15: Pcr15, + pcr16: Pcr16, + pcr17: Pcr17, + pcr18: Pcr18, + pcr19: Pcr19, + pcr20: Pcr20, + pcr21: Pcr21, + pcr22: Pcr22, + pcr23: Pcr23, + pcr24: Pcr24, + pcr25: Pcr25, + pcr26: Pcr26, + pcr27: Pcr27, + pcr28: Pcr28, + pcr29: Pcr29, + pcr30: Pcr30, + pcr31: Pcr31, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x10 - Global Pin Control Low"] + #[inline(always)] + pub const fn gpclr(&self) -> &Gpclr { + &self.gpclr + } + #[doc = "0x14 - Global Pin Control High"] + #[inline(always)] + pub const fn gpchr(&self) -> &Gpchr { + &self.gpchr + } + #[doc = "0x20 - Configuration"] + #[inline(always)] + pub const fn config(&self) -> &Config { + &self.config + } + #[doc = "0x60 - Calibration 0"] + #[inline(always)] + pub const fn calib0(&self) -> &Calib0 { + &self.calib0 + } + #[doc = "0x64 - Calibration 1"] + #[inline(always)] + pub const fn calib1(&self) -> &Calib1 { + &self.calib1 + } + #[doc = "0x80 - Pin Control 0"] + #[inline(always)] + pub const fn pcr0(&self) -> &Pcr0 { + &self.pcr0 + } + #[doc = "0x84 - Pin Control 1"] + #[inline(always)] + pub const fn pcr1(&self) -> &Pcr1 { + &self.pcr1 + } + #[doc = "0x88 - Pin Control 2"] + #[inline(always)] + pub const fn pcr2(&self) -> &Pcr2 { + &self.pcr2 + } + #[doc = "0x8c - Pin Control 3"] + #[inline(always)] + pub const fn pcr3(&self) -> &Pcr3 { + &self.pcr3 + } + #[doc = "0x90 - Pin Control 4"] + #[inline(always)] + pub const fn pcr4(&self) -> &Pcr4 { + &self.pcr4 + } + #[doc = "0x94 - Pin Control 5"] + #[inline(always)] + pub const fn pcr5(&self) -> &Pcr5 { + &self.pcr5 + } + #[doc = "0x98 - Pin Control 6"] + #[inline(always)] + pub const fn pcr6(&self) -> &Pcr6 { + &self.pcr6 + } + #[doc = "0x9c - Pin Control 7"] + #[inline(always)] + pub const fn pcr7(&self) -> &Pcr7 { + &self.pcr7 + } + #[doc = "0xa0 - Pin Control 8"] + #[inline(always)] + pub const fn pcr8(&self) -> &Pcr8 { + &self.pcr8 + } + #[doc = "0xa4 - Pin Control 9"] + #[inline(always)] + pub const fn pcr9(&self) -> &Pcr9 { + &self.pcr9 + } + #[doc = "0xa8 - Pin Control 10"] + #[inline(always)] + pub const fn pcr10(&self) -> &Pcr10 { + &self.pcr10 + } + #[doc = "0xac - Pin Control 11"] + #[inline(always)] + pub const fn pcr11(&self) -> &Pcr11 { + &self.pcr11 + } + #[doc = "0xb0 - Pin Control 12"] + #[inline(always)] + pub const fn pcr12(&self) -> &Pcr12 { + &self.pcr12 + } + #[doc = "0xb4 - Pin Control 13"] + #[inline(always)] + pub const fn pcr13(&self) -> &Pcr13 { + &self.pcr13 + } + #[doc = "0xb8 - Pin Control 14"] + #[inline(always)] + pub const fn pcr14(&self) -> &Pcr14 { + &self.pcr14 + } + #[doc = "0xbc - Pin Control 15"] + #[inline(always)] + pub const fn pcr15(&self) -> &Pcr15 { + &self.pcr15 + } + #[doc = "0xc0 - Pin Control 16"] + #[inline(always)] + pub const fn pcr16(&self) -> &Pcr16 { + &self.pcr16 + } + #[doc = "0xc4 - Pin Control 17"] + #[inline(always)] + pub const fn pcr17(&self) -> &Pcr17 { + &self.pcr17 + } + #[doc = "0xc8 - Pin Control 18"] + #[inline(always)] + pub const fn pcr18(&self) -> &Pcr18 { + &self.pcr18 + } + #[doc = "0xcc - Pin Control 19"] + #[inline(always)] + pub const fn pcr19(&self) -> &Pcr19 { + &self.pcr19 + } + #[doc = "0xd0 - Pin Control 20"] + #[inline(always)] + pub const fn pcr20(&self) -> &Pcr20 { + &self.pcr20 + } + #[doc = "0xd4 - Pin Control 21"] + #[inline(always)] + pub const fn pcr21(&self) -> &Pcr21 { + &self.pcr21 + } + #[doc = "0xd8 - Pin Control 22"] + #[inline(always)] + pub const fn pcr22(&self) -> &Pcr22 { + &self.pcr22 + } + #[doc = "0xdc - Pin Control 23"] + #[inline(always)] + pub const fn pcr23(&self) -> &Pcr23 { + &self.pcr23 + } + #[doc = "0xe0 - Pin Control 24"] + #[inline(always)] + pub const fn pcr24(&self) -> &Pcr24 { + &self.pcr24 + } + #[doc = "0xe4 - Pin Control 25"] + #[inline(always)] + pub const fn pcr25(&self) -> &Pcr25 { + &self.pcr25 + } + #[doc = "0xe8 - Pin Control 26"] + #[inline(always)] + pub const fn pcr26(&self) -> &Pcr26 { + &self.pcr26 + } + #[doc = "0xec - Pin Control 27"] + #[inline(always)] + pub const fn pcr27(&self) -> &Pcr27 { + &self.pcr27 + } + #[doc = "0xf0 - Pin Control 28"] + #[inline(always)] + pub const fn pcr28(&self) -> &Pcr28 { + &self.pcr28 + } + #[doc = "0xf4 - Pin Control 29"] + #[inline(always)] + pub const fn pcr29(&self) -> &Pcr29 { + &self.pcr29 + } + #[doc = "0xf8 - Pin Control 30"] + #[inline(always)] + pub const fn pcr30(&self) -> &Pcr30 { + &self.pcr30 + } + #[doc = "0xfc - Pin Control 31"] + #[inline(always)] + pub const fn pcr31(&self) -> &Pcr31 { + &self.pcr31 + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] +#[doc(alias = "GPCLR")] +pub type Gpclr = crate::Reg; +#[doc = "Global Pin Control Low"] +pub mod gpclr; +#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] +#[doc(alias = "GPCHR")] +pub type Gpchr = crate::Reg; +#[doc = "Global Pin Control High"] +pub mod gpchr; +#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +#[doc(alias = "CONFIG")] +pub type Config = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] +#[doc(alias = "CALIB0")] +pub type Calib0 = crate::Reg; +#[doc = "Calibration 0"] +pub mod calib0; +#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] +#[doc(alias = "CALIB1")] +pub type Calib1 = crate::Reg; +#[doc = "Calibration 1"] +pub mod calib1; +#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] +#[doc(alias = "PCR0")] +pub type Pcr0 = crate::Reg; +#[doc = "Pin Control 0"] +pub mod pcr0; +#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] +#[doc(alias = "PCR1")] +pub type Pcr1 = crate::Reg; +#[doc = "Pin Control 1"] +pub mod pcr1; +#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] +#[doc(alias = "PCR2")] +pub type Pcr2 = crate::Reg; +#[doc = "Pin Control 2"] +pub mod pcr2; +#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] +#[doc(alias = "PCR3")] +pub type Pcr3 = crate::Reg; +#[doc = "Pin Control 3"] +pub mod pcr3; +#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] +#[doc(alias = "PCR4")] +pub type Pcr4 = crate::Reg; +#[doc = "Pin Control 4"] +pub mod pcr4; +#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] +#[doc(alias = "PCR5")] +pub type Pcr5 = crate::Reg; +#[doc = "Pin Control 5"] +pub mod pcr5; +#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] +#[doc(alias = "PCR6")] +pub type Pcr6 = crate::Reg; +#[doc = "Pin Control 6"] +pub mod pcr6; +#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] +#[doc(alias = "PCR7")] +pub type Pcr7 = crate::Reg; +#[doc = "Pin Control 7"] +pub mod pcr7; +#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] +#[doc(alias = "PCR8")] +pub type Pcr8 = crate::Reg; +#[doc = "Pin Control 8"] +pub mod pcr8; +#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] +#[doc(alias = "PCR9")] +pub type Pcr9 = crate::Reg; +#[doc = "Pin Control 9"] +pub mod pcr9; +#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] +#[doc(alias = "PCR10")] +pub type Pcr10 = crate::Reg; +#[doc = "Pin Control 10"] +pub mod pcr10; +#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] +#[doc(alias = "PCR11")] +pub type Pcr11 = crate::Reg; +#[doc = "Pin Control 11"] +pub mod pcr11; +#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] +#[doc(alias = "PCR12")] +pub type Pcr12 = crate::Reg; +#[doc = "Pin Control 12"] +pub mod pcr12; +#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] +#[doc(alias = "PCR13")] +pub type Pcr13 = crate::Reg; +#[doc = "Pin Control 13"] +pub mod pcr13; +#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] +#[doc(alias = "PCR14")] +pub type Pcr14 = crate::Reg; +#[doc = "Pin Control 14"] +pub mod pcr14; +#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] +#[doc(alias = "PCR15")] +pub type Pcr15 = crate::Reg; +#[doc = "Pin Control 15"] +pub mod pcr15; +#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] +#[doc(alias = "PCR16")] +pub type Pcr16 = crate::Reg; +#[doc = "Pin Control 16"] +pub mod pcr16; +#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] +#[doc(alias = "PCR17")] +pub type Pcr17 = crate::Reg; +#[doc = "Pin Control 17"] +pub mod pcr17; +#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] +#[doc(alias = "PCR18")] +pub type Pcr18 = crate::Reg; +#[doc = "Pin Control 18"] +pub mod pcr18; +#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] +#[doc(alias = "PCR19")] +pub type Pcr19 = crate::Reg; +#[doc = "Pin Control 19"] +pub mod pcr19; +#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] +#[doc(alias = "PCR20")] +pub type Pcr20 = crate::Reg; +#[doc = "Pin Control 20"] +pub mod pcr20; +#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] +#[doc(alias = "PCR21")] +pub type Pcr21 = crate::Reg; +#[doc = "Pin Control 21"] +pub mod pcr21; +#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] +#[doc(alias = "PCR22")] +pub type Pcr22 = crate::Reg; +#[doc = "Pin Control 22"] +pub mod pcr22; +#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] +#[doc(alias = "PCR23")] +pub type Pcr23 = crate::Reg; +#[doc = "Pin Control 23"] +pub mod pcr23; +#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] +#[doc(alias = "PCR24")] +pub type Pcr24 = crate::Reg; +#[doc = "Pin Control 24"] +pub mod pcr24; +#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] +#[doc(alias = "PCR25")] +pub type Pcr25 = crate::Reg; +#[doc = "Pin Control 25"] +pub mod pcr25; +#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] +#[doc(alias = "PCR26")] +pub type Pcr26 = crate::Reg; +#[doc = "Pin Control 26"] +pub mod pcr26; +#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] +#[doc(alias = "PCR27")] +pub type Pcr27 = crate::Reg; +#[doc = "Pin Control 27"] +pub mod pcr27; +#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] +#[doc(alias = "PCR28")] +pub type Pcr28 = crate::Reg; +#[doc = "Pin Control 28"] +pub mod pcr28; +#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] +#[doc(alias = "PCR29")] +pub type Pcr29 = crate::Reg; +#[doc = "Pin Control 29"] +pub mod pcr29; +#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] +#[doc(alias = "PCR30")] +pub type Pcr30 = crate::Reg; +#[doc = "Pin Control 30"] +pub mod pcr30; +#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] +#[doc(alias = "PCR31")] +pub type Pcr31 = crate::Reg; +#[doc = "Pin Control 31"] +pub mod pcr31; diff --git a/mcxa276-pac/src/port0/calib0.rs b/mcxa276-pac/src/port0/calib0.rs new file mode 100644 index 000000000..029fa12f3 --- /dev/null +++ b/mcxa276-pac/src/port0/calib0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB0` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB0` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib0Spec; +impl crate::RegisterSpec for Calib0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] +impl crate::Readable for Calib0Spec {} +#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] +impl crate::Writable for Calib0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB0 to value 0"] +impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port0/calib1.rs b/mcxa276-pac/src/port0/calib1.rs new file mode 100644 index 000000000..e18f61234 --- /dev/null +++ b/mcxa276-pac/src/port0/calib1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB1` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB1` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib1Spec; +impl crate::RegisterSpec for Calib1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] +impl crate::Readable for Calib1Spec {} +#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] +impl crate::Writable for Calib1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB1 to value 0"] +impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port0/config.rs b/mcxa276-pac/src/port0/config.rs new file mode 100644 index 000000000..da92c5b27 --- /dev/null +++ b/mcxa276-pac/src/port0/config.rs @@ -0,0 +1,84 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Port Voltage Range\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Range { + #[doc = "0: 1.71 V-3.6 V"] + Range0 = 0, + #[doc = "1: 2.70 V-3.6 V"] + Range1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Range) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RANGE` reader - Port Voltage Range"] +pub type RangeR = crate::BitReader; +impl RangeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Range { + match self.bits { + false => Range::Range0, + true => Range::Range1, + } + } + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn is_range0(&self) -> bool { + *self == Range::Range0 + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn is_range1(&self) -> bool { + *self == Range::Range1 + } +} +#[doc = "Field `RANGE` writer - Port Voltage Range"] +pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; +impl<'a, REG> RangeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn range0(self) -> &'a mut crate::W { + self.variant(Range::Range0) + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn range1(self) -> &'a mut crate::W { + self.variant(Range::Range1) + } +} +impl R { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&self) -> RangeR { + RangeR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&mut self) -> RangeW { + RangeW::new(self, 0) + } +} +#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConfigSpec; +impl crate::RegisterSpec for ConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for ConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for ConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port0/gpchr.rs b/mcxa276-pac/src/port0/gpchr.rs new file mode 100644 index 000000000..af92d0d62 --- /dev/null +++ b/mcxa276-pac/src/port0/gpchr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCHR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCHR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe16 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] +pub type Gpwe16R = crate::BitReader; +impl Gpwe16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe16 { + match self.bits { + false => Gpwe16::Gpwe0, + true => Gpwe16::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe16::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe16::Gpwe1 + } +} +#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] +pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; +impl<'a, REG> Gpwe16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe17 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] +pub type Gpwe17R = crate::BitReader; +impl Gpwe17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe17 { + match self.bits { + false => Gpwe17::Gpwe0, + true => Gpwe17::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe17::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe17::Gpwe1 + } +} +#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] +pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; +impl<'a, REG> Gpwe17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe18 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] +pub type Gpwe18R = crate::BitReader; +impl Gpwe18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe18 { + match self.bits { + false => Gpwe18::Gpwe0, + true => Gpwe18::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe18::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe18::Gpwe1 + } +} +#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] +pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; +impl<'a, REG> Gpwe18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe19 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] +pub type Gpwe19R = crate::BitReader; +impl Gpwe19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe19 { + match self.bits { + false => Gpwe19::Gpwe0, + true => Gpwe19::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe19::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe19::Gpwe1 + } +} +#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] +pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; +impl<'a, REG> Gpwe19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe20 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] +pub type Gpwe20R = crate::BitReader; +impl Gpwe20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe20 { + match self.bits { + false => Gpwe20::Gpwe0, + true => Gpwe20::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe20::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe20::Gpwe1 + } +} +#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] +pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; +impl<'a, REG> Gpwe20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe21 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] +pub type Gpwe21R = crate::BitReader; +impl Gpwe21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe21 { + match self.bits { + false => Gpwe21::Gpwe0, + true => Gpwe21::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe21::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe21::Gpwe1 + } +} +#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] +pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; +impl<'a, REG> Gpwe21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe22 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] +pub type Gpwe22R = crate::BitReader; +impl Gpwe22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe22 { + match self.bits { + false => Gpwe22::Gpwe0, + true => Gpwe22::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe22::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe22::Gpwe1 + } +} +#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] +pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; +impl<'a, REG> Gpwe22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe23 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] +pub type Gpwe23R = crate::BitReader; +impl Gpwe23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe23 { + match self.bits { + false => Gpwe23::Gpwe0, + true => Gpwe23::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe23::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe23::Gpwe1 + } +} +#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] +pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; +impl<'a, REG> Gpwe23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe24 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] +pub type Gpwe24R = crate::BitReader; +impl Gpwe24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe24 { + match self.bits { + false => Gpwe24::Gpwe0, + true => Gpwe24::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe24::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe24::Gpwe1 + } +} +#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] +pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; +impl<'a, REG> Gpwe24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe25 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] +pub type Gpwe25R = crate::BitReader; +impl Gpwe25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe25 { + match self.bits { + false => Gpwe25::Gpwe0, + true => Gpwe25::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe25::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe25::Gpwe1 + } +} +#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] +pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; +impl<'a, REG> Gpwe25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe26 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] +pub type Gpwe26R = crate::BitReader; +impl Gpwe26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe26 { + match self.bits { + false => Gpwe26::Gpwe0, + true => Gpwe26::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe26::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe26::Gpwe1 + } +} +#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] +pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; +impl<'a, REG> Gpwe26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe27 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] +pub type Gpwe27R = crate::BitReader; +impl Gpwe27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe27 { + match self.bits { + false => Gpwe27::Gpwe0, + true => Gpwe27::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe27::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe27::Gpwe1 + } +} +#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] +pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; +impl<'a, REG> Gpwe27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe28 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] +pub type Gpwe28R = crate::BitReader; +impl Gpwe28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe28 { + match self.bits { + false => Gpwe28::Gpwe0, + true => Gpwe28::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe28::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe28::Gpwe1 + } +} +#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] +pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; +impl<'a, REG> Gpwe28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe29 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] +pub type Gpwe29R = crate::BitReader; +impl Gpwe29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe29 { + match self.bits { + false => Gpwe29::Gpwe0, + true => Gpwe29::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe29::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe29::Gpwe1 + } +} +#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] +pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; +impl<'a, REG> Gpwe29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe30 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] +pub type Gpwe30R = crate::BitReader; +impl Gpwe30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe30 { + match self.bits { + false => Gpwe30::Gpwe0, + true => Gpwe30::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe30::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe30::Gpwe1 + } +} +#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] +pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; +impl<'a, REG> Gpwe30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe31 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] +pub type Gpwe31R = crate::BitReader; +impl Gpwe31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe31 { + match self.bits { + false => Gpwe31::Gpwe0, + true => Gpwe31::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe31::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe31::Gpwe1 + } +} +#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] +pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; +impl<'a, REG> Gpwe31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&self) -> Gpwe16R { + Gpwe16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&self) -> Gpwe17R { + Gpwe17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&self) -> Gpwe18R { + Gpwe18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&self) -> Gpwe19R { + Gpwe19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&self) -> Gpwe20R { + Gpwe20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&self) -> Gpwe21R { + Gpwe21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&self) -> Gpwe22R { + Gpwe22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&self) -> Gpwe23R { + Gpwe23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&self) -> Gpwe24R { + Gpwe24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&self) -> Gpwe25R { + Gpwe25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&self) -> Gpwe26R { + Gpwe26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&self) -> Gpwe27R { + Gpwe27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&self) -> Gpwe28R { + Gpwe28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&self) -> Gpwe29R { + Gpwe29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&self) -> Gpwe30R { + Gpwe30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&self) -> Gpwe31R { + Gpwe31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&mut self) -> Gpwe16W { + Gpwe16W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&mut self) -> Gpwe17W { + Gpwe17W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&mut self) -> Gpwe18W { + Gpwe18W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&mut self) -> Gpwe19W { + Gpwe19W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&mut self) -> Gpwe20W { + Gpwe20W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&mut self) -> Gpwe21W { + Gpwe21W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&mut self) -> Gpwe22W { + Gpwe22W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&mut self) -> Gpwe23W { + Gpwe23W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&mut self) -> Gpwe24W { + Gpwe24W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&mut self) -> Gpwe25W { + Gpwe25W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&mut self) -> Gpwe26W { + Gpwe26W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&mut self) -> Gpwe27W { + Gpwe27W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&mut self) -> Gpwe28W { + Gpwe28W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&mut self) -> Gpwe29W { + Gpwe29W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&mut self) -> Gpwe30W { + Gpwe30W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&mut self) -> Gpwe31W { + Gpwe31W::new(self, 31) + } +} +#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpchrSpec; +impl crate::RegisterSpec for GpchrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] +impl crate::Readable for GpchrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] +impl crate::Writable for GpchrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCHR to value 0"] +impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port0/gpclr.rs b/mcxa276-pac/src/port0/gpclr.rs new file mode 100644 index 000000000..21e5ff23d --- /dev/null +++ b/mcxa276-pac/src/port0/gpclr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe0 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] +pub type Gpwe0R = crate::BitReader; +impl Gpwe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe0 { + match self.bits { + false => Gpwe0::Gpwe0, + true => Gpwe0::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe0::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe0::Gpwe1 + } +} +#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] +pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; +impl<'a, REG> Gpwe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe1 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] +pub type Gpwe1R = crate::BitReader; +impl Gpwe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe1 { + match self.bits { + false => Gpwe1::Gpwe0, + true => Gpwe1::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe1::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe1::Gpwe1 + } +} +#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] +pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; +impl<'a, REG> Gpwe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe2 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] +pub type Gpwe2R = crate::BitReader; +impl Gpwe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe2 { + match self.bits { + false => Gpwe2::Gpwe0, + true => Gpwe2::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe2::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe2::Gpwe1 + } +} +#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] +pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; +impl<'a, REG> Gpwe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe3 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] +pub type Gpwe3R = crate::BitReader; +impl Gpwe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe3 { + match self.bits { + false => Gpwe3::Gpwe0, + true => Gpwe3::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe3::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe3::Gpwe1 + } +} +#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] +pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; +impl<'a, REG> Gpwe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe4 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] +pub type Gpwe4R = crate::BitReader; +impl Gpwe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe4 { + match self.bits { + false => Gpwe4::Gpwe0, + true => Gpwe4::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe4::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe4::Gpwe1 + } +} +#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] +pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; +impl<'a, REG> Gpwe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe5 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] +pub type Gpwe5R = crate::BitReader; +impl Gpwe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe5 { + match self.bits { + false => Gpwe5::Gpwe0, + true => Gpwe5::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe5::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe5::Gpwe1 + } +} +#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] +pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; +impl<'a, REG> Gpwe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe6 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] +pub type Gpwe6R = crate::BitReader; +impl Gpwe6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe6 { + match self.bits { + false => Gpwe6::Gpwe0, + true => Gpwe6::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe6::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe6::Gpwe1 + } +} +#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] +pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; +impl<'a, REG> Gpwe6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe7 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] +pub type Gpwe7R = crate::BitReader; +impl Gpwe7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe7 { + match self.bits { + false => Gpwe7::Gpwe0, + true => Gpwe7::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe7::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe7::Gpwe1 + } +} +#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] +pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; +impl<'a, REG> Gpwe7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe8 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] +pub type Gpwe8R = crate::BitReader; +impl Gpwe8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe8 { + match self.bits { + false => Gpwe8::Gpwe0, + true => Gpwe8::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe8::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe8::Gpwe1 + } +} +#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] +pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; +impl<'a, REG> Gpwe8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe9 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] +pub type Gpwe9R = crate::BitReader; +impl Gpwe9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe9 { + match self.bits { + false => Gpwe9::Gpwe0, + true => Gpwe9::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe9::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe9::Gpwe1 + } +} +#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] +pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; +impl<'a, REG> Gpwe9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe10 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] +pub type Gpwe10R = crate::BitReader; +impl Gpwe10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe10 { + match self.bits { + false => Gpwe10::Gpwe0, + true => Gpwe10::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe10::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe10::Gpwe1 + } +} +#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] +pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; +impl<'a, REG> Gpwe10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe11 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] +pub type Gpwe11R = crate::BitReader; +impl Gpwe11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe11 { + match self.bits { + false => Gpwe11::Gpwe0, + true => Gpwe11::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe11::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe11::Gpwe1 + } +} +#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] +pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; +impl<'a, REG> Gpwe11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe12 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] +pub type Gpwe12R = crate::BitReader; +impl Gpwe12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe12 { + match self.bits { + false => Gpwe12::Gpwe0, + true => Gpwe12::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe12::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe12::Gpwe1 + } +} +#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] +pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; +impl<'a, REG> Gpwe12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe13 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] +pub type Gpwe13R = crate::BitReader; +impl Gpwe13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe13 { + match self.bits { + false => Gpwe13::Gpwe0, + true => Gpwe13::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe13::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe13::Gpwe1 + } +} +#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] +pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; +impl<'a, REG> Gpwe13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe14 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] +pub type Gpwe14R = crate::BitReader; +impl Gpwe14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe14 { + match self.bits { + false => Gpwe14::Gpwe0, + true => Gpwe14::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe14::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe14::Gpwe1 + } +} +#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] +pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; +impl<'a, REG> Gpwe14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe15 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] +pub type Gpwe15R = crate::BitReader; +impl Gpwe15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe15 { + match self.bits { + false => Gpwe15::Gpwe0, + true => Gpwe15::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe15::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe15::Gpwe1 + } +} +#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] +pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; +impl<'a, REG> Gpwe15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&self) -> Gpwe0R { + Gpwe0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&self) -> Gpwe1R { + Gpwe1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&self) -> Gpwe2R { + Gpwe2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&self) -> Gpwe3R { + Gpwe3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&self) -> Gpwe4R { + Gpwe4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&self) -> Gpwe5R { + Gpwe5R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&self) -> Gpwe6R { + Gpwe6R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&self) -> Gpwe7R { + Gpwe7R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&self) -> Gpwe8R { + Gpwe8R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&self) -> Gpwe9R { + Gpwe9R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&self) -> Gpwe10R { + Gpwe10R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&self) -> Gpwe11R { + Gpwe11R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&self) -> Gpwe12R { + Gpwe12R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&self) -> Gpwe13R { + Gpwe13R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&self) -> Gpwe14R { + Gpwe14R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&self) -> Gpwe15R { + Gpwe15R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&mut self) -> Gpwe0W { + Gpwe0W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&mut self) -> Gpwe1W { + Gpwe1W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&mut self) -> Gpwe2W { + Gpwe2W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&mut self) -> Gpwe3W { + Gpwe3W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&mut self) -> Gpwe4W { + Gpwe4W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&mut self) -> Gpwe5W { + Gpwe5W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&mut self) -> Gpwe6W { + Gpwe6W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&mut self) -> Gpwe7W { + Gpwe7W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&mut self) -> Gpwe8W { + Gpwe8W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&mut self) -> Gpwe9W { + Gpwe9W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&mut self) -> Gpwe10W { + Gpwe10W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&mut self) -> Gpwe11W { + Gpwe11W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&mut self) -> Gpwe12W { + Gpwe12W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&mut self) -> Gpwe13W { + Gpwe13W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&mut self) -> Gpwe14W { + Gpwe14W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&mut self) -> Gpwe15W { + Gpwe15W::new(self, 31) + } +} +#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpclrSpec; +impl crate::RegisterSpec for GpclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] +impl crate::Readable for GpclrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] +impl crate::Writable for GpclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCLR to value 0"] +impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port0/pcr0.rs b/mcxa276-pac/src/port0/pcr0.rs new file mode 100644 index 000000000..59f37ae97 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr0.rs @@ -0,0 +1,675 @@ +#[doc = "Register `PCR0` reader"] +pub type R = crate::R; +#[doc = "Register `PCR0` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr0Spec; +impl crate::RegisterSpec for Pcr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] +impl crate::Readable for Pcr0Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] +impl crate::Writable for Pcr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR0 to value 0x1143"] +impl crate::Resettable for Pcr0Spec { + const RESET_VALUE: u32 = 0x1143; +} diff --git a/mcxa276-pac/src/port0/pcr1.rs b/mcxa276-pac/src/port0/pcr1.rs new file mode 100644 index 000000000..f63d93430 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr1.rs @@ -0,0 +1,675 @@ +#[doc = "Register `PCR1` reader"] +pub type R = crate::R; +#[doc = "Register `PCR1` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr1Spec; +impl crate::RegisterSpec for Pcr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] +impl crate::Readable for Pcr1Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] +impl crate::Writable for Pcr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR1 to value 0x1102"] +impl crate::Resettable for Pcr1Spec { + const RESET_VALUE: u32 = 0x1102; +} diff --git a/mcxa276-pac/src/port0/pcr10.rs b/mcxa276-pac/src/port0/pcr10.rs new file mode 100644 index 000000000..9a358f658 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr10.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR10` reader"] +pub type R = crate::R; +#[doc = "Register `PCR10` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr10Spec; +impl crate::RegisterSpec for Pcr10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] +impl crate::Readable for Pcr10Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] +impl crate::Writable for Pcr10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR10 to value 0"] +impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port0/pcr11.rs b/mcxa276-pac/src/port0/pcr11.rs new file mode 100644 index 000000000..7b809b651 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr11.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR11` reader"] +pub type R = crate::R; +#[doc = "Register `PCR11` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr11Spec; +impl crate::RegisterSpec for Pcr11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] +impl crate::Readable for Pcr11Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] +impl crate::Writable for Pcr11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR11 to value 0"] +impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port0/pcr12.rs b/mcxa276-pac/src/port0/pcr12.rs new file mode 100644 index 000000000..2cd7eecc1 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr12.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR12` reader"] +pub type R = crate::R; +#[doc = "Register `PCR12` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr12Spec; +impl crate::RegisterSpec for Pcr12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] +impl crate::Readable for Pcr12Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] +impl crate::Writable for Pcr12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR12 to value 0"] +impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port0/pcr13.rs b/mcxa276-pac/src/port0/pcr13.rs new file mode 100644 index 000000000..0da9c8d55 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr13.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR13` reader"] +pub type R = crate::R; +#[doc = "Register `PCR13` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr13Spec; +impl crate::RegisterSpec for Pcr13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] +impl crate::Readable for Pcr13Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] +impl crate::Writable for Pcr13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR13 to value 0"] +impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port0/pcr14.rs b/mcxa276-pac/src/port0/pcr14.rs new file mode 100644 index 000000000..553559b3f --- /dev/null +++ b/mcxa276-pac/src/port0/pcr14.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR14` reader"] +pub type R = crate::R; +#[doc = "Register `PCR14` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr14Spec; +impl crate::RegisterSpec for Pcr14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] +impl crate::Readable for Pcr14Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] +impl crate::Writable for Pcr14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR14 to value 0"] +impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port0/pcr15.rs b/mcxa276-pac/src/port0/pcr15.rs new file mode 100644 index 000000000..85c188f6b --- /dev/null +++ b/mcxa276-pac/src/port0/pcr15.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR15` reader"] +pub type R = crate::R; +#[doc = "Register `PCR15` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr15Spec; +impl crate::RegisterSpec for Pcr15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] +impl crate::Readable for Pcr15Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] +impl crate::Writable for Pcr15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR15 to value 0"] +impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port0/pcr16.rs b/mcxa276-pac/src/port0/pcr16.rs new file mode 100644 index 000000000..7ee22ee99 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr16.rs @@ -0,0 +1,940 @@ +#[doc = "Register `PCR16` reader"] +pub type R = crate::R; +#[doc = "Register `PCR16` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr16Spec; +impl crate::RegisterSpec for Pcr16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] +impl crate::Readable for Pcr16Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] +impl crate::Writable for Pcr16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR16 to value 0"] +impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port0/pcr17.rs b/mcxa276-pac/src/port0/pcr17.rs new file mode 100644 index 000000000..4e9b5f619 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr17.rs @@ -0,0 +1,877 @@ +#[doc = "Register `PCR17` reader"] +pub type R = crate::R; +#[doc = "Register `PCR17` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr17Spec; +impl crate::RegisterSpec for Pcr17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] +impl crate::Readable for Pcr17Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] +impl crate::Writable for Pcr17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR17 to value 0"] +impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port0/pcr18.rs b/mcxa276-pac/src/port0/pcr18.rs new file mode 100644 index 000000000..b87bafe1a --- /dev/null +++ b/mcxa276-pac/src/port0/pcr18.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR18` reader"] +pub type R = crate::R; +#[doc = "Register `PCR18` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr18Spec; +impl crate::RegisterSpec for Pcr18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] +impl crate::Readable for Pcr18Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] +impl crate::Writable for Pcr18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR18 to value 0"] +impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port0/pcr19.rs b/mcxa276-pac/src/port0/pcr19.rs new file mode 100644 index 000000000..cd55e9cfd --- /dev/null +++ b/mcxa276-pac/src/port0/pcr19.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR19` reader"] +pub type R = crate::R; +#[doc = "Register `PCR19` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr19Spec; +impl crate::RegisterSpec for Pcr19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] +impl crate::Readable for Pcr19Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] +impl crate::Writable for Pcr19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR19 to value 0"] +impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port0/pcr2.rs b/mcxa276-pac/src/port0/pcr2.rs new file mode 100644 index 000000000..dd5c28418 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr2.rs @@ -0,0 +1,753 @@ +#[doc = "Register `PCR2` reader"] +pub type R = crate::R; +#[doc = "Register `PCR2` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr2Spec; +impl crate::RegisterSpec for Pcr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] +impl crate::Readable for Pcr2Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] +impl crate::Writable for Pcr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR2 to value 0x1140"] +impl crate::Resettable for Pcr2Spec { + const RESET_VALUE: u32 = 0x1140; +} diff --git a/mcxa276-pac/src/port0/pcr20.rs b/mcxa276-pac/src/port0/pcr20.rs new file mode 100644 index 000000000..20401202b --- /dev/null +++ b/mcxa276-pac/src/port0/pcr20.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR20` reader"] +pub type R = crate::R; +#[doc = "Register `PCR20` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr20Spec; +impl crate::RegisterSpec for Pcr20Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] +impl crate::Readable for Pcr20Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] +impl crate::Writable for Pcr20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR20 to value 0"] +impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port0/pcr21.rs b/mcxa276-pac/src/port0/pcr21.rs new file mode 100644 index 000000000..9f6076615 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr21.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR21` reader"] +pub type R = crate::R; +#[doc = "Register `PCR21` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr21Spec; +impl crate::RegisterSpec for Pcr21Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] +impl crate::Readable for Pcr21Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] +impl crate::Writable for Pcr21Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR21 to value 0"] +impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port0/pcr22.rs b/mcxa276-pac/src/port0/pcr22.rs new file mode 100644 index 000000000..decbc02c0 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr22.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR22` reader"] +pub type R = crate::R; +#[doc = "Register `PCR22` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr22Spec; +impl crate::RegisterSpec for Pcr22Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] +impl crate::Readable for Pcr22Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] +impl crate::Writable for Pcr22Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR22 to value 0"] +impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port0/pcr23.rs b/mcxa276-pac/src/port0/pcr23.rs new file mode 100644 index 000000000..640773d73 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr23.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR23` reader"] +pub type R = crate::R; +#[doc = "Register `PCR23` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr23Spec; +impl crate::RegisterSpec for Pcr23Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] +impl crate::Readable for Pcr23Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] +impl crate::Writable for Pcr23Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR23 to value 0"] +impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port0/pcr24.rs b/mcxa276-pac/src/port0/pcr24.rs new file mode 100644 index 000000000..fe34d2b88 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr24.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR24` reader"] +pub type R = crate::R; +#[doc = "Register `PCR24` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr24Spec; +impl crate::RegisterSpec for Pcr24Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] +impl crate::Readable for Pcr24Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] +impl crate::Writable for Pcr24Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR24 to value 0"] +impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port0/pcr25.rs b/mcxa276-pac/src/port0/pcr25.rs new file mode 100644 index 000000000..5486437a9 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr25.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR25` reader"] +pub type R = crate::R; +#[doc = "Register `PCR25` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr25Spec; +impl crate::RegisterSpec for Pcr25Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] +impl crate::Readable for Pcr25Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] +impl crate::Writable for Pcr25Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR25 to value 0"] +impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port0/pcr26.rs b/mcxa276-pac/src/port0/pcr26.rs new file mode 100644 index 000000000..fb601b77c --- /dev/null +++ b/mcxa276-pac/src/port0/pcr26.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR26` reader"] +pub type R = crate::R; +#[doc = "Register `PCR26` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr26Spec; +impl crate::RegisterSpec for Pcr26Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] +impl crate::Readable for Pcr26Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] +impl crate::Writable for Pcr26Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR26 to value 0"] +impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port0/pcr27.rs b/mcxa276-pac/src/port0/pcr27.rs new file mode 100644 index 000000000..e53d72f87 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr27.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR27` reader"] +pub type R = crate::R; +#[doc = "Register `PCR27` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr27Spec; +impl crate::RegisterSpec for Pcr27Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] +impl crate::Readable for Pcr27Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] +impl crate::Writable for Pcr27Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR27 to value 0"] +impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port0/pcr28.rs b/mcxa276-pac/src/port0/pcr28.rs new file mode 100644 index 000000000..1315078be --- /dev/null +++ b/mcxa276-pac/src/port0/pcr28.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR28` reader"] +pub type R = crate::R; +#[doc = "Register `PCR28` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr28Spec; +impl crate::RegisterSpec for Pcr28Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] +impl crate::Readable for Pcr28Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] +impl crate::Writable for Pcr28Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR28 to value 0"] +impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port0/pcr29.rs b/mcxa276-pac/src/port0/pcr29.rs new file mode 100644 index 000000000..de7c41baa --- /dev/null +++ b/mcxa276-pac/src/port0/pcr29.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR29` reader"] +pub type R = crate::R; +#[doc = "Register `PCR29` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr29Spec; +impl crate::RegisterSpec for Pcr29Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] +impl crate::Readable for Pcr29Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] +impl crate::Writable for Pcr29Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR29 to value 0"] +impl crate::Resettable for Pcr29Spec {} diff --git a/mcxa276-pac/src/port0/pcr3.rs b/mcxa276-pac/src/port0/pcr3.rs new file mode 100644 index 000000000..762b324a4 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr3.rs @@ -0,0 +1,753 @@ +#[doc = "Register `PCR3` reader"] +pub type R = crate::R; +#[doc = "Register `PCR3` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr3Spec; +impl crate::RegisterSpec for Pcr3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] +impl crate::Readable for Pcr3Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] +impl crate::Writable for Pcr3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR3 to value 0x1103"] +impl crate::Resettable for Pcr3Spec { + const RESET_VALUE: u32 = 0x1103; +} diff --git a/mcxa276-pac/src/port0/pcr30.rs b/mcxa276-pac/src/port0/pcr30.rs new file mode 100644 index 000000000..cce4166f4 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr30.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR30` reader"] +pub type R = crate::R; +#[doc = "Register `PCR30` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr30Spec; +impl crate::RegisterSpec for Pcr30Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] +impl crate::Readable for Pcr30Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] +impl crate::Writable for Pcr30Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR30 to value 0"] +impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port0/pcr31.rs b/mcxa276-pac/src/port0/pcr31.rs new file mode 100644 index 000000000..1f49159c2 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr31.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR31` reader"] +pub type R = crate::R; +#[doc = "Register `PCR31` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr31Spec; +impl crate::RegisterSpec for Pcr31Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] +impl crate::Readable for Pcr31Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] +impl crate::Writable for Pcr31Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR31 to value 0"] +impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port0/pcr4.rs b/mcxa276-pac/src/port0/pcr4.rs new file mode 100644 index 000000000..9890bb2d4 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr4.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR4` reader"] +pub type R = crate::R; +#[doc = "Register `PCR4` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr4Spec; +impl crate::RegisterSpec for Pcr4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] +impl crate::Readable for Pcr4Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] +impl crate::Writable for Pcr4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR4 to value 0"] +impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port0/pcr5.rs b/mcxa276-pac/src/port0/pcr5.rs new file mode 100644 index 000000000..bbc9bfc8a --- /dev/null +++ b/mcxa276-pac/src/port0/pcr5.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR5` reader"] +pub type R = crate::R; +#[doc = "Register `PCR5` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr5Spec; +impl crate::RegisterSpec for Pcr5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] +impl crate::Readable for Pcr5Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] +impl crate::Writable for Pcr5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR5 to value 0"] +impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port0/pcr6.rs b/mcxa276-pac/src/port0/pcr6.rs new file mode 100644 index 000000000..529346a2c --- /dev/null +++ b/mcxa276-pac/src/port0/pcr6.rs @@ -0,0 +1,753 @@ +#[doc = "Register `PCR6` reader"] +pub type R = crate::R; +#[doc = "Register `PCR6` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr6Spec; +impl crate::RegisterSpec for Pcr6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] +impl crate::Readable for Pcr6Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] +impl crate::Writable for Pcr6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR6 to value 0x1103"] +impl crate::Resettable for Pcr6Spec { + const RESET_VALUE: u32 = 0x1103; +} diff --git a/mcxa276-pac/src/port0/pcr7.rs b/mcxa276-pac/src/port0/pcr7.rs new file mode 100644 index 000000000..18e6a4872 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr7.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR7` reader"] +pub type R = crate::R; +#[doc = "Register `PCR7` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr7Spec; +impl crate::RegisterSpec for Pcr7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] +impl crate::Readable for Pcr7Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] +impl crate::Writable for Pcr7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR7 to value 0"] +impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port0/pcr8.rs b/mcxa276-pac/src/port0/pcr8.rs new file mode 100644 index 000000000..8c6d7289b --- /dev/null +++ b/mcxa276-pac/src/port0/pcr8.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR8` reader"] +pub type R = crate::R; +#[doc = "Register `PCR8` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr8Spec; +impl crate::RegisterSpec for Pcr8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] +impl crate::Readable for Pcr8Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] +impl crate::Writable for Pcr8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR8 to value 0"] +impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port0/pcr9.rs b/mcxa276-pac/src/port0/pcr9.rs new file mode 100644 index 000000000..403e7e331 --- /dev/null +++ b/mcxa276-pac/src/port0/pcr9.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR9` reader"] +pub type R = crate::R; +#[doc = "Register `PCR9` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr9Spec; +impl crate::RegisterSpec for Pcr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] +impl crate::Readable for Pcr9Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] +impl crate::Writable for Pcr9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR9 to value 0"] +impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port0/verid.rs b/mcxa276-pac/src/port0/verid.rs new file mode 100644 index 000000000..330f53d57 --- /dev/null +++ b/mcxa276-pac/src/port0/verid.rs @@ -0,0 +1,68 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Basic implementation"] + Feature0 = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Feature0), + _ => None, + } + } + #[doc = "Basic implementation"] + #[inline(always)] + pub fn is_feature0(&self) -> bool { + *self == Feature::Feature0 + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0200_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0200_0000; +} diff --git a/mcxa276-pac/src/port1.rs b/mcxa276-pac/src/port1.rs new file mode 100644 index 000000000..d7ed05fc0 --- /dev/null +++ b/mcxa276-pac/src/port1.rs @@ -0,0 +1,428 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x0c], + gpclr: Gpclr, + gpchr: Gpchr, + _reserved3: [u8; 0x08], + config: Config, + _reserved4: [u8; 0x3c], + calib0: Calib0, + calib1: Calib1, + _reserved6: [u8; 0x18], + pcr0: Pcr0, + pcr1: Pcr1, + pcr2: Pcr2, + pcr3: Pcr3, + pcr4: Pcr4, + pcr5: Pcr5, + pcr6: Pcr6, + pcr7: Pcr7, + pcr8: Pcr8, + pcr9: Pcr9, + pcr10: Pcr10, + pcr11: Pcr11, + pcr12: Pcr12, + pcr13: Pcr13, + pcr14: Pcr14, + pcr15: Pcr15, + pcr16: Pcr16, + pcr17: Pcr17, + pcr18: Pcr18, + pcr19: Pcr19, + pcr20: Pcr20, + pcr21: Pcr21, + pcr22: Pcr22, + pcr23: Pcr23, + pcr24: Pcr24, + pcr25: Pcr25, + pcr26: Pcr26, + pcr27: Pcr27, + pcr28: Pcr28, + pcr29: Pcr29, + pcr30: Pcr30, + pcr31: Pcr31, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x10 - Global Pin Control Low"] + #[inline(always)] + pub const fn gpclr(&self) -> &Gpclr { + &self.gpclr + } + #[doc = "0x14 - Global Pin Control High"] + #[inline(always)] + pub const fn gpchr(&self) -> &Gpchr { + &self.gpchr + } + #[doc = "0x20 - Configuration"] + #[inline(always)] + pub const fn config(&self) -> &Config { + &self.config + } + #[doc = "0x60 - Calibration 0"] + #[inline(always)] + pub const fn calib0(&self) -> &Calib0 { + &self.calib0 + } + #[doc = "0x64 - Calibration 1"] + #[inline(always)] + pub const fn calib1(&self) -> &Calib1 { + &self.calib1 + } + #[doc = "0x80 - Pin Control 0"] + #[inline(always)] + pub const fn pcr0(&self) -> &Pcr0 { + &self.pcr0 + } + #[doc = "0x84 - Pin Control 1"] + #[inline(always)] + pub const fn pcr1(&self) -> &Pcr1 { + &self.pcr1 + } + #[doc = "0x88 - Pin Control 2"] + #[inline(always)] + pub const fn pcr2(&self) -> &Pcr2 { + &self.pcr2 + } + #[doc = "0x8c - Pin Control 3"] + #[inline(always)] + pub const fn pcr3(&self) -> &Pcr3 { + &self.pcr3 + } + #[doc = "0x90 - Pin Control 4"] + #[inline(always)] + pub const fn pcr4(&self) -> &Pcr4 { + &self.pcr4 + } + #[doc = "0x94 - Pin Control 5"] + #[inline(always)] + pub const fn pcr5(&self) -> &Pcr5 { + &self.pcr5 + } + #[doc = "0x98 - Pin Control 6"] + #[inline(always)] + pub const fn pcr6(&self) -> &Pcr6 { + &self.pcr6 + } + #[doc = "0x9c - Pin Control 7"] + #[inline(always)] + pub const fn pcr7(&self) -> &Pcr7 { + &self.pcr7 + } + #[doc = "0xa0 - Pin Control 8"] + #[inline(always)] + pub const fn pcr8(&self) -> &Pcr8 { + &self.pcr8 + } + #[doc = "0xa4 - Pin Control 9"] + #[inline(always)] + pub const fn pcr9(&self) -> &Pcr9 { + &self.pcr9 + } + #[doc = "0xa8 - Pin Control 10"] + #[inline(always)] + pub const fn pcr10(&self) -> &Pcr10 { + &self.pcr10 + } + #[doc = "0xac - Pin Control 11"] + #[inline(always)] + pub const fn pcr11(&self) -> &Pcr11 { + &self.pcr11 + } + #[doc = "0xb0 - Pin Control 12"] + #[inline(always)] + pub const fn pcr12(&self) -> &Pcr12 { + &self.pcr12 + } + #[doc = "0xb4 - Pin Control 13"] + #[inline(always)] + pub const fn pcr13(&self) -> &Pcr13 { + &self.pcr13 + } + #[doc = "0xb8 - Pin Control 14"] + #[inline(always)] + pub const fn pcr14(&self) -> &Pcr14 { + &self.pcr14 + } + #[doc = "0xbc - Pin Control 15"] + #[inline(always)] + pub const fn pcr15(&self) -> &Pcr15 { + &self.pcr15 + } + #[doc = "0xc0 - Pin Control 16"] + #[inline(always)] + pub const fn pcr16(&self) -> &Pcr16 { + &self.pcr16 + } + #[doc = "0xc4 - Pin Control 17"] + #[inline(always)] + pub const fn pcr17(&self) -> &Pcr17 { + &self.pcr17 + } + #[doc = "0xc8 - Pin Control 18"] + #[inline(always)] + pub const fn pcr18(&self) -> &Pcr18 { + &self.pcr18 + } + #[doc = "0xcc - Pin Control 19"] + #[inline(always)] + pub const fn pcr19(&self) -> &Pcr19 { + &self.pcr19 + } + #[doc = "0xd0 - Pin Control 20"] + #[inline(always)] + pub const fn pcr20(&self) -> &Pcr20 { + &self.pcr20 + } + #[doc = "0xd4 - Pin Control 21"] + #[inline(always)] + pub const fn pcr21(&self) -> &Pcr21 { + &self.pcr21 + } + #[doc = "0xd8 - Pin Control 22"] + #[inline(always)] + pub const fn pcr22(&self) -> &Pcr22 { + &self.pcr22 + } + #[doc = "0xdc - Pin Control 23"] + #[inline(always)] + pub const fn pcr23(&self) -> &Pcr23 { + &self.pcr23 + } + #[doc = "0xe0 - Pin Control 24"] + #[inline(always)] + pub const fn pcr24(&self) -> &Pcr24 { + &self.pcr24 + } + #[doc = "0xe4 - Pin Control 25"] + #[inline(always)] + pub const fn pcr25(&self) -> &Pcr25 { + &self.pcr25 + } + #[doc = "0xe8 - Pin Control 26"] + #[inline(always)] + pub const fn pcr26(&self) -> &Pcr26 { + &self.pcr26 + } + #[doc = "0xec - Pin Control 27"] + #[inline(always)] + pub const fn pcr27(&self) -> &Pcr27 { + &self.pcr27 + } + #[doc = "0xf0 - Pin Control 28"] + #[inline(always)] + pub const fn pcr28(&self) -> &Pcr28 { + &self.pcr28 + } + #[doc = "0xf4 - Pin Control 29"] + #[inline(always)] + pub const fn pcr29(&self) -> &Pcr29 { + &self.pcr29 + } + #[doc = "0xf8 - Pin Control 30"] + #[inline(always)] + pub const fn pcr30(&self) -> &Pcr30 { + &self.pcr30 + } + #[doc = "0xfc - Pin Control 31"] + #[inline(always)] + pub const fn pcr31(&self) -> &Pcr31 { + &self.pcr31 + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] +#[doc(alias = "GPCLR")] +pub type Gpclr = crate::Reg; +#[doc = "Global Pin Control Low"] +pub mod gpclr; +#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] +#[doc(alias = "GPCHR")] +pub type Gpchr = crate::Reg; +#[doc = "Global Pin Control High"] +pub mod gpchr; +#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +#[doc(alias = "CONFIG")] +pub type Config = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] +#[doc(alias = "CALIB0")] +pub type Calib0 = crate::Reg; +#[doc = "Calibration 0"] +pub mod calib0; +#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] +#[doc(alias = "CALIB1")] +pub type Calib1 = crate::Reg; +#[doc = "Calibration 1"] +pub mod calib1; +#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] +#[doc(alias = "PCR0")] +pub type Pcr0 = crate::Reg; +#[doc = "Pin Control 0"] +pub mod pcr0; +#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] +#[doc(alias = "PCR1")] +pub type Pcr1 = crate::Reg; +#[doc = "Pin Control 1"] +pub mod pcr1; +#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] +#[doc(alias = "PCR2")] +pub type Pcr2 = crate::Reg; +#[doc = "Pin Control 2"] +pub mod pcr2; +#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] +#[doc(alias = "PCR3")] +pub type Pcr3 = crate::Reg; +#[doc = "Pin Control 3"] +pub mod pcr3; +#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] +#[doc(alias = "PCR4")] +pub type Pcr4 = crate::Reg; +#[doc = "Pin Control 4"] +pub mod pcr4; +#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] +#[doc(alias = "PCR5")] +pub type Pcr5 = crate::Reg; +#[doc = "Pin Control 5"] +pub mod pcr5; +#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] +#[doc(alias = "PCR6")] +pub type Pcr6 = crate::Reg; +#[doc = "Pin Control 6"] +pub mod pcr6; +#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] +#[doc(alias = "PCR7")] +pub type Pcr7 = crate::Reg; +#[doc = "Pin Control 7"] +pub mod pcr7; +#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] +#[doc(alias = "PCR8")] +pub type Pcr8 = crate::Reg; +#[doc = "Pin Control 8"] +pub mod pcr8; +#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] +#[doc(alias = "PCR9")] +pub type Pcr9 = crate::Reg; +#[doc = "Pin Control 9"] +pub mod pcr9; +#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] +#[doc(alias = "PCR10")] +pub type Pcr10 = crate::Reg; +#[doc = "Pin Control 10"] +pub mod pcr10; +#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] +#[doc(alias = "PCR11")] +pub type Pcr11 = crate::Reg; +#[doc = "Pin Control 11"] +pub mod pcr11; +#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] +#[doc(alias = "PCR12")] +pub type Pcr12 = crate::Reg; +#[doc = "Pin Control 12"] +pub mod pcr12; +#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] +#[doc(alias = "PCR13")] +pub type Pcr13 = crate::Reg; +#[doc = "Pin Control 13"] +pub mod pcr13; +#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] +#[doc(alias = "PCR14")] +pub type Pcr14 = crate::Reg; +#[doc = "Pin Control 14"] +pub mod pcr14; +#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] +#[doc(alias = "PCR15")] +pub type Pcr15 = crate::Reg; +#[doc = "Pin Control 15"] +pub mod pcr15; +#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] +#[doc(alias = "PCR16")] +pub type Pcr16 = crate::Reg; +#[doc = "Pin Control 16"] +pub mod pcr16; +#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] +#[doc(alias = "PCR17")] +pub type Pcr17 = crate::Reg; +#[doc = "Pin Control 17"] +pub mod pcr17; +#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] +#[doc(alias = "PCR18")] +pub type Pcr18 = crate::Reg; +#[doc = "Pin Control 18"] +pub mod pcr18; +#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] +#[doc(alias = "PCR19")] +pub type Pcr19 = crate::Reg; +#[doc = "Pin Control 19"] +pub mod pcr19; +#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] +#[doc(alias = "PCR20")] +pub type Pcr20 = crate::Reg; +#[doc = "Pin Control 20"] +pub mod pcr20; +#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] +#[doc(alias = "PCR21")] +pub type Pcr21 = crate::Reg; +#[doc = "Pin Control 21"] +pub mod pcr21; +#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] +#[doc(alias = "PCR22")] +pub type Pcr22 = crate::Reg; +#[doc = "Pin Control 22"] +pub mod pcr22; +#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] +#[doc(alias = "PCR23")] +pub type Pcr23 = crate::Reg; +#[doc = "Pin Control 23"] +pub mod pcr23; +#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] +#[doc(alias = "PCR24")] +pub type Pcr24 = crate::Reg; +#[doc = "Pin Control 24"] +pub mod pcr24; +#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] +#[doc(alias = "PCR25")] +pub type Pcr25 = crate::Reg; +#[doc = "Pin Control 25"] +pub mod pcr25; +#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] +#[doc(alias = "PCR26")] +pub type Pcr26 = crate::Reg; +#[doc = "Pin Control 26"] +pub mod pcr26; +#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] +#[doc(alias = "PCR27")] +pub type Pcr27 = crate::Reg; +#[doc = "Pin Control 27"] +pub mod pcr27; +#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] +#[doc(alias = "PCR28")] +pub type Pcr28 = crate::Reg; +#[doc = "Pin Control 28"] +pub mod pcr28; +#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] +#[doc(alias = "PCR29")] +pub type Pcr29 = crate::Reg; +#[doc = "Pin Control 29"] +pub mod pcr29; +#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] +#[doc(alias = "PCR30")] +pub type Pcr30 = crate::Reg; +#[doc = "Pin Control 30"] +pub mod pcr30; +#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] +#[doc(alias = "PCR31")] +pub type Pcr31 = crate::Reg; +#[doc = "Pin Control 31"] +pub mod pcr31; diff --git a/mcxa276-pac/src/port1/calib0.rs b/mcxa276-pac/src/port1/calib0.rs new file mode 100644 index 000000000..029fa12f3 --- /dev/null +++ b/mcxa276-pac/src/port1/calib0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB0` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB0` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib0Spec; +impl crate::RegisterSpec for Calib0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] +impl crate::Readable for Calib0Spec {} +#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] +impl crate::Writable for Calib0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB0 to value 0"] +impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port1/calib1.rs b/mcxa276-pac/src/port1/calib1.rs new file mode 100644 index 000000000..e18f61234 --- /dev/null +++ b/mcxa276-pac/src/port1/calib1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB1` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB1` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib1Spec; +impl crate::RegisterSpec for Calib1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] +impl crate::Readable for Calib1Spec {} +#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] +impl crate::Writable for Calib1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB1 to value 0"] +impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port1/config.rs b/mcxa276-pac/src/port1/config.rs new file mode 100644 index 000000000..da92c5b27 --- /dev/null +++ b/mcxa276-pac/src/port1/config.rs @@ -0,0 +1,84 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Port Voltage Range\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Range { + #[doc = "0: 1.71 V-3.6 V"] + Range0 = 0, + #[doc = "1: 2.70 V-3.6 V"] + Range1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Range) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RANGE` reader - Port Voltage Range"] +pub type RangeR = crate::BitReader; +impl RangeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Range { + match self.bits { + false => Range::Range0, + true => Range::Range1, + } + } + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn is_range0(&self) -> bool { + *self == Range::Range0 + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn is_range1(&self) -> bool { + *self == Range::Range1 + } +} +#[doc = "Field `RANGE` writer - Port Voltage Range"] +pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; +impl<'a, REG> RangeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn range0(self) -> &'a mut crate::W { + self.variant(Range::Range0) + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn range1(self) -> &'a mut crate::W { + self.variant(Range::Range1) + } +} +impl R { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&self) -> RangeR { + RangeR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&mut self) -> RangeW { + RangeW::new(self, 0) + } +} +#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConfigSpec; +impl crate::RegisterSpec for ConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for ConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for ConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port1/gpchr.rs b/mcxa276-pac/src/port1/gpchr.rs new file mode 100644 index 000000000..af92d0d62 --- /dev/null +++ b/mcxa276-pac/src/port1/gpchr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCHR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCHR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe16 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] +pub type Gpwe16R = crate::BitReader; +impl Gpwe16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe16 { + match self.bits { + false => Gpwe16::Gpwe0, + true => Gpwe16::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe16::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe16::Gpwe1 + } +} +#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] +pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; +impl<'a, REG> Gpwe16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe17 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] +pub type Gpwe17R = crate::BitReader; +impl Gpwe17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe17 { + match self.bits { + false => Gpwe17::Gpwe0, + true => Gpwe17::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe17::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe17::Gpwe1 + } +} +#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] +pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; +impl<'a, REG> Gpwe17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe18 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] +pub type Gpwe18R = crate::BitReader; +impl Gpwe18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe18 { + match self.bits { + false => Gpwe18::Gpwe0, + true => Gpwe18::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe18::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe18::Gpwe1 + } +} +#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] +pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; +impl<'a, REG> Gpwe18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe19 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] +pub type Gpwe19R = crate::BitReader; +impl Gpwe19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe19 { + match self.bits { + false => Gpwe19::Gpwe0, + true => Gpwe19::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe19::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe19::Gpwe1 + } +} +#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] +pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; +impl<'a, REG> Gpwe19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe20 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] +pub type Gpwe20R = crate::BitReader; +impl Gpwe20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe20 { + match self.bits { + false => Gpwe20::Gpwe0, + true => Gpwe20::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe20::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe20::Gpwe1 + } +} +#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] +pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; +impl<'a, REG> Gpwe20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe21 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] +pub type Gpwe21R = crate::BitReader; +impl Gpwe21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe21 { + match self.bits { + false => Gpwe21::Gpwe0, + true => Gpwe21::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe21::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe21::Gpwe1 + } +} +#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] +pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; +impl<'a, REG> Gpwe21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe22 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] +pub type Gpwe22R = crate::BitReader; +impl Gpwe22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe22 { + match self.bits { + false => Gpwe22::Gpwe0, + true => Gpwe22::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe22::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe22::Gpwe1 + } +} +#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] +pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; +impl<'a, REG> Gpwe22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe23 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] +pub type Gpwe23R = crate::BitReader; +impl Gpwe23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe23 { + match self.bits { + false => Gpwe23::Gpwe0, + true => Gpwe23::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe23::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe23::Gpwe1 + } +} +#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] +pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; +impl<'a, REG> Gpwe23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe24 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] +pub type Gpwe24R = crate::BitReader; +impl Gpwe24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe24 { + match self.bits { + false => Gpwe24::Gpwe0, + true => Gpwe24::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe24::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe24::Gpwe1 + } +} +#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] +pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; +impl<'a, REG> Gpwe24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe25 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] +pub type Gpwe25R = crate::BitReader; +impl Gpwe25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe25 { + match self.bits { + false => Gpwe25::Gpwe0, + true => Gpwe25::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe25::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe25::Gpwe1 + } +} +#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] +pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; +impl<'a, REG> Gpwe25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe26 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] +pub type Gpwe26R = crate::BitReader; +impl Gpwe26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe26 { + match self.bits { + false => Gpwe26::Gpwe0, + true => Gpwe26::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe26::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe26::Gpwe1 + } +} +#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] +pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; +impl<'a, REG> Gpwe26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe27 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] +pub type Gpwe27R = crate::BitReader; +impl Gpwe27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe27 { + match self.bits { + false => Gpwe27::Gpwe0, + true => Gpwe27::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe27::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe27::Gpwe1 + } +} +#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] +pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; +impl<'a, REG> Gpwe27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe28 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] +pub type Gpwe28R = crate::BitReader; +impl Gpwe28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe28 { + match self.bits { + false => Gpwe28::Gpwe0, + true => Gpwe28::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe28::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe28::Gpwe1 + } +} +#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] +pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; +impl<'a, REG> Gpwe28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe29 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] +pub type Gpwe29R = crate::BitReader; +impl Gpwe29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe29 { + match self.bits { + false => Gpwe29::Gpwe0, + true => Gpwe29::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe29::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe29::Gpwe1 + } +} +#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] +pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; +impl<'a, REG> Gpwe29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe30 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] +pub type Gpwe30R = crate::BitReader; +impl Gpwe30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe30 { + match self.bits { + false => Gpwe30::Gpwe0, + true => Gpwe30::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe30::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe30::Gpwe1 + } +} +#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] +pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; +impl<'a, REG> Gpwe30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe31 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] +pub type Gpwe31R = crate::BitReader; +impl Gpwe31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe31 { + match self.bits { + false => Gpwe31::Gpwe0, + true => Gpwe31::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe31::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe31::Gpwe1 + } +} +#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] +pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; +impl<'a, REG> Gpwe31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&self) -> Gpwe16R { + Gpwe16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&self) -> Gpwe17R { + Gpwe17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&self) -> Gpwe18R { + Gpwe18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&self) -> Gpwe19R { + Gpwe19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&self) -> Gpwe20R { + Gpwe20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&self) -> Gpwe21R { + Gpwe21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&self) -> Gpwe22R { + Gpwe22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&self) -> Gpwe23R { + Gpwe23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&self) -> Gpwe24R { + Gpwe24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&self) -> Gpwe25R { + Gpwe25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&self) -> Gpwe26R { + Gpwe26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&self) -> Gpwe27R { + Gpwe27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&self) -> Gpwe28R { + Gpwe28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&self) -> Gpwe29R { + Gpwe29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&self) -> Gpwe30R { + Gpwe30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&self) -> Gpwe31R { + Gpwe31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&mut self) -> Gpwe16W { + Gpwe16W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&mut self) -> Gpwe17W { + Gpwe17W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&mut self) -> Gpwe18W { + Gpwe18W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&mut self) -> Gpwe19W { + Gpwe19W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&mut self) -> Gpwe20W { + Gpwe20W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&mut self) -> Gpwe21W { + Gpwe21W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&mut self) -> Gpwe22W { + Gpwe22W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&mut self) -> Gpwe23W { + Gpwe23W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&mut self) -> Gpwe24W { + Gpwe24W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&mut self) -> Gpwe25W { + Gpwe25W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&mut self) -> Gpwe26W { + Gpwe26W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&mut self) -> Gpwe27W { + Gpwe27W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&mut self) -> Gpwe28W { + Gpwe28W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&mut self) -> Gpwe29W { + Gpwe29W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&mut self) -> Gpwe30W { + Gpwe30W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&mut self) -> Gpwe31W { + Gpwe31W::new(self, 31) + } +} +#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpchrSpec; +impl crate::RegisterSpec for GpchrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] +impl crate::Readable for GpchrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] +impl crate::Writable for GpchrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCHR to value 0"] +impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port1/gpclr.rs b/mcxa276-pac/src/port1/gpclr.rs new file mode 100644 index 000000000..21e5ff23d --- /dev/null +++ b/mcxa276-pac/src/port1/gpclr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe0 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] +pub type Gpwe0R = crate::BitReader; +impl Gpwe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe0 { + match self.bits { + false => Gpwe0::Gpwe0, + true => Gpwe0::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe0::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe0::Gpwe1 + } +} +#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] +pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; +impl<'a, REG> Gpwe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe1 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] +pub type Gpwe1R = crate::BitReader; +impl Gpwe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe1 { + match self.bits { + false => Gpwe1::Gpwe0, + true => Gpwe1::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe1::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe1::Gpwe1 + } +} +#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] +pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; +impl<'a, REG> Gpwe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe2 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] +pub type Gpwe2R = crate::BitReader; +impl Gpwe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe2 { + match self.bits { + false => Gpwe2::Gpwe0, + true => Gpwe2::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe2::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe2::Gpwe1 + } +} +#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] +pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; +impl<'a, REG> Gpwe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe3 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] +pub type Gpwe3R = crate::BitReader; +impl Gpwe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe3 { + match self.bits { + false => Gpwe3::Gpwe0, + true => Gpwe3::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe3::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe3::Gpwe1 + } +} +#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] +pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; +impl<'a, REG> Gpwe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe4 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] +pub type Gpwe4R = crate::BitReader; +impl Gpwe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe4 { + match self.bits { + false => Gpwe4::Gpwe0, + true => Gpwe4::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe4::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe4::Gpwe1 + } +} +#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] +pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; +impl<'a, REG> Gpwe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe5 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] +pub type Gpwe5R = crate::BitReader; +impl Gpwe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe5 { + match self.bits { + false => Gpwe5::Gpwe0, + true => Gpwe5::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe5::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe5::Gpwe1 + } +} +#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] +pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; +impl<'a, REG> Gpwe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe6 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] +pub type Gpwe6R = crate::BitReader; +impl Gpwe6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe6 { + match self.bits { + false => Gpwe6::Gpwe0, + true => Gpwe6::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe6::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe6::Gpwe1 + } +} +#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] +pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; +impl<'a, REG> Gpwe6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe7 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] +pub type Gpwe7R = crate::BitReader; +impl Gpwe7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe7 { + match self.bits { + false => Gpwe7::Gpwe0, + true => Gpwe7::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe7::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe7::Gpwe1 + } +} +#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] +pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; +impl<'a, REG> Gpwe7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe8 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] +pub type Gpwe8R = crate::BitReader; +impl Gpwe8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe8 { + match self.bits { + false => Gpwe8::Gpwe0, + true => Gpwe8::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe8::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe8::Gpwe1 + } +} +#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] +pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; +impl<'a, REG> Gpwe8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe9 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] +pub type Gpwe9R = crate::BitReader; +impl Gpwe9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe9 { + match self.bits { + false => Gpwe9::Gpwe0, + true => Gpwe9::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe9::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe9::Gpwe1 + } +} +#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] +pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; +impl<'a, REG> Gpwe9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe10 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] +pub type Gpwe10R = crate::BitReader; +impl Gpwe10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe10 { + match self.bits { + false => Gpwe10::Gpwe0, + true => Gpwe10::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe10::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe10::Gpwe1 + } +} +#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] +pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; +impl<'a, REG> Gpwe10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe11 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] +pub type Gpwe11R = crate::BitReader; +impl Gpwe11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe11 { + match self.bits { + false => Gpwe11::Gpwe0, + true => Gpwe11::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe11::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe11::Gpwe1 + } +} +#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] +pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; +impl<'a, REG> Gpwe11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe12 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] +pub type Gpwe12R = crate::BitReader; +impl Gpwe12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe12 { + match self.bits { + false => Gpwe12::Gpwe0, + true => Gpwe12::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe12::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe12::Gpwe1 + } +} +#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] +pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; +impl<'a, REG> Gpwe12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe13 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] +pub type Gpwe13R = crate::BitReader; +impl Gpwe13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe13 { + match self.bits { + false => Gpwe13::Gpwe0, + true => Gpwe13::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe13::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe13::Gpwe1 + } +} +#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] +pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; +impl<'a, REG> Gpwe13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe14 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] +pub type Gpwe14R = crate::BitReader; +impl Gpwe14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe14 { + match self.bits { + false => Gpwe14::Gpwe0, + true => Gpwe14::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe14::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe14::Gpwe1 + } +} +#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] +pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; +impl<'a, REG> Gpwe14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe15 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] +pub type Gpwe15R = crate::BitReader; +impl Gpwe15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe15 { + match self.bits { + false => Gpwe15::Gpwe0, + true => Gpwe15::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe15::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe15::Gpwe1 + } +} +#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] +pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; +impl<'a, REG> Gpwe15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&self) -> Gpwe0R { + Gpwe0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&self) -> Gpwe1R { + Gpwe1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&self) -> Gpwe2R { + Gpwe2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&self) -> Gpwe3R { + Gpwe3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&self) -> Gpwe4R { + Gpwe4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&self) -> Gpwe5R { + Gpwe5R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&self) -> Gpwe6R { + Gpwe6R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&self) -> Gpwe7R { + Gpwe7R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&self) -> Gpwe8R { + Gpwe8R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&self) -> Gpwe9R { + Gpwe9R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&self) -> Gpwe10R { + Gpwe10R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&self) -> Gpwe11R { + Gpwe11R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&self) -> Gpwe12R { + Gpwe12R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&self) -> Gpwe13R { + Gpwe13R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&self) -> Gpwe14R { + Gpwe14R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&self) -> Gpwe15R { + Gpwe15R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&mut self) -> Gpwe0W { + Gpwe0W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&mut self) -> Gpwe1W { + Gpwe1W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&mut self) -> Gpwe2W { + Gpwe2W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&mut self) -> Gpwe3W { + Gpwe3W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&mut self) -> Gpwe4W { + Gpwe4W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&mut self) -> Gpwe5W { + Gpwe5W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&mut self) -> Gpwe6W { + Gpwe6W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&mut self) -> Gpwe7W { + Gpwe7W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&mut self) -> Gpwe8W { + Gpwe8W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&mut self) -> Gpwe9W { + Gpwe9W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&mut self) -> Gpwe10W { + Gpwe10W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&mut self) -> Gpwe11W { + Gpwe11W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&mut self) -> Gpwe12W { + Gpwe12W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&mut self) -> Gpwe13W { + Gpwe13W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&mut self) -> Gpwe14W { + Gpwe14W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&mut self) -> Gpwe15W { + Gpwe15W::new(self, 31) + } +} +#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpclrSpec; +impl crate::RegisterSpec for GpclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] +impl crate::Readable for GpclrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] +impl crate::Writable for GpclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCLR to value 0"] +impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port1/pcr0.rs b/mcxa276-pac/src/port1/pcr0.rs new file mode 100644 index 000000000..63c1edc30 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr0.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR0` reader"] +pub type R = crate::R; +#[doc = "Register `PCR0` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr0Spec; +impl crate::RegisterSpec for Pcr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] +impl crate::Readable for Pcr0Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] +impl crate::Writable for Pcr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR0 to value 0"] +impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port1/pcr1.rs b/mcxa276-pac/src/port1/pcr1.rs new file mode 100644 index 000000000..8899bfd9b --- /dev/null +++ b/mcxa276-pac/src/port1/pcr1.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR1` reader"] +pub type R = crate::R; +#[doc = "Register `PCR1` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr1Spec; +impl crate::RegisterSpec for Pcr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] +impl crate::Readable for Pcr1Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] +impl crate::Writable for Pcr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR1 to value 0"] +impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port1/pcr10.rs b/mcxa276-pac/src/port1/pcr10.rs new file mode 100644 index 000000000..e5317eb0c --- /dev/null +++ b/mcxa276-pac/src/port1/pcr10.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR10` reader"] +pub type R = crate::R; +#[doc = "Register `PCR10` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr10Spec; +impl crate::RegisterSpec for Pcr10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] +impl crate::Readable for Pcr10Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] +impl crate::Writable for Pcr10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR10 to value 0"] +impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port1/pcr11.rs b/mcxa276-pac/src/port1/pcr11.rs new file mode 100644 index 000000000..bc47cbd2b --- /dev/null +++ b/mcxa276-pac/src/port1/pcr11.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR11` reader"] +pub type R = crate::R; +#[doc = "Register `PCR11` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr11Spec; +impl crate::RegisterSpec for Pcr11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] +impl crate::Readable for Pcr11Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] +impl crate::Writable for Pcr11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR11 to value 0"] +impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port1/pcr12.rs b/mcxa276-pac/src/port1/pcr12.rs new file mode 100644 index 000000000..2cd7eecc1 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr12.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR12` reader"] +pub type R = crate::R; +#[doc = "Register `PCR12` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr12Spec; +impl crate::RegisterSpec for Pcr12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] +impl crate::Readable for Pcr12Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] +impl crate::Writable for Pcr12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR12 to value 0"] +impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port1/pcr13.rs b/mcxa276-pac/src/port1/pcr13.rs new file mode 100644 index 000000000..0da9c8d55 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr13.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR13` reader"] +pub type R = crate::R; +#[doc = "Register `PCR13` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr13Spec; +impl crate::RegisterSpec for Pcr13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] +impl crate::Readable for Pcr13Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] +impl crate::Writable for Pcr13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR13 to value 0"] +impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port1/pcr14.rs b/mcxa276-pac/src/port1/pcr14.rs new file mode 100644 index 000000000..553559b3f --- /dev/null +++ b/mcxa276-pac/src/port1/pcr14.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR14` reader"] +pub type R = crate::R; +#[doc = "Register `PCR14` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr14Spec; +impl crate::RegisterSpec for Pcr14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] +impl crate::Readable for Pcr14Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] +impl crate::Writable for Pcr14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR14 to value 0"] +impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port1/pcr15.rs b/mcxa276-pac/src/port1/pcr15.rs new file mode 100644 index 000000000..85c188f6b --- /dev/null +++ b/mcxa276-pac/src/port1/pcr15.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR15` reader"] +pub type R = crate::R; +#[doc = "Register `PCR15` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr15Spec; +impl crate::RegisterSpec for Pcr15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] +impl crate::Readable for Pcr15Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] +impl crate::Writable for Pcr15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR15 to value 0"] +impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port1/pcr16.rs b/mcxa276-pac/src/port1/pcr16.rs new file mode 100644 index 000000000..70c9dda78 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr16.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR16` reader"] +pub type R = crate::R; +#[doc = "Register `PCR16` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr16Spec; +impl crate::RegisterSpec for Pcr16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] +impl crate::Readable for Pcr16Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] +impl crate::Writable for Pcr16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR16 to value 0"] +impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port1/pcr17.rs b/mcxa276-pac/src/port1/pcr17.rs new file mode 100644 index 000000000..2faf3487b --- /dev/null +++ b/mcxa276-pac/src/port1/pcr17.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR17` reader"] +pub type R = crate::R; +#[doc = "Register `PCR17` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr17Spec; +impl crate::RegisterSpec for Pcr17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] +impl crate::Readable for Pcr17Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] +impl crate::Writable for Pcr17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR17 to value 0"] +impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port1/pcr18.rs b/mcxa276-pac/src/port1/pcr18.rs new file mode 100644 index 000000000..b87bafe1a --- /dev/null +++ b/mcxa276-pac/src/port1/pcr18.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR18` reader"] +pub type R = crate::R; +#[doc = "Register `PCR18` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr18Spec; +impl crate::RegisterSpec for Pcr18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] +impl crate::Readable for Pcr18Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] +impl crate::Writable for Pcr18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR18 to value 0"] +impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port1/pcr19.rs b/mcxa276-pac/src/port1/pcr19.rs new file mode 100644 index 000000000..cd55e9cfd --- /dev/null +++ b/mcxa276-pac/src/port1/pcr19.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR19` reader"] +pub type R = crate::R; +#[doc = "Register `PCR19` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr19Spec; +impl crate::RegisterSpec for Pcr19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] +impl crate::Readable for Pcr19Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] +impl crate::Writable for Pcr19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR19 to value 0"] +impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port1/pcr2.rs b/mcxa276-pac/src/port1/pcr2.rs new file mode 100644 index 000000000..09359160e --- /dev/null +++ b/mcxa276-pac/src/port1/pcr2.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR2` reader"] +pub type R = crate::R; +#[doc = "Register `PCR2` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr2Spec; +impl crate::RegisterSpec for Pcr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] +impl crate::Readable for Pcr2Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] +impl crate::Writable for Pcr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR2 to value 0"] +impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port1/pcr20.rs b/mcxa276-pac/src/port1/pcr20.rs new file mode 100644 index 000000000..d3457f781 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr20.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR20` reader"] +pub type R = crate::R; +#[doc = "Register `PCR20` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr20Spec; +impl crate::RegisterSpec for Pcr20Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] +impl crate::Readable for Pcr20Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] +impl crate::Writable for Pcr20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR20 to value 0"] +impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port1/pcr21.rs b/mcxa276-pac/src/port1/pcr21.rs new file mode 100644 index 000000000..549acb257 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr21.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR21` reader"] +pub type R = crate::R; +#[doc = "Register `PCR21` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr21Spec; +impl crate::RegisterSpec for Pcr21Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] +impl crate::Readable for Pcr21Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] +impl crate::Writable for Pcr21Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR21 to value 0"] +impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port1/pcr22.rs b/mcxa276-pac/src/port1/pcr22.rs new file mode 100644 index 000000000..b52c672cb --- /dev/null +++ b/mcxa276-pac/src/port1/pcr22.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR22` reader"] +pub type R = crate::R; +#[doc = "Register `PCR22` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr22Spec; +impl crate::RegisterSpec for Pcr22Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] +impl crate::Readable for Pcr22Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] +impl crate::Writable for Pcr22Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR22 to value 0"] +impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port1/pcr23.rs b/mcxa276-pac/src/port1/pcr23.rs new file mode 100644 index 000000000..918e561a9 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr23.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR23` reader"] +pub type R = crate::R; +#[doc = "Register `PCR23` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr23Spec; +impl crate::RegisterSpec for Pcr23Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] +impl crate::Readable for Pcr23Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] +impl crate::Writable for Pcr23Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR23 to value 0"] +impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port1/pcr24.rs b/mcxa276-pac/src/port1/pcr24.rs new file mode 100644 index 000000000..1bc9d5574 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr24.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR24` reader"] +pub type R = crate::R; +#[doc = "Register `PCR24` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr24Spec; +impl crate::RegisterSpec for Pcr24Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] +impl crate::Readable for Pcr24Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] +impl crate::Writable for Pcr24Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR24 to value 0"] +impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port1/pcr25.rs b/mcxa276-pac/src/port1/pcr25.rs new file mode 100644 index 000000000..dbc8cae05 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr25.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR25` reader"] +pub type R = crate::R; +#[doc = "Register `PCR25` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr25Spec; +impl crate::RegisterSpec for Pcr25Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] +impl crate::Readable for Pcr25Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] +impl crate::Writable for Pcr25Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR25 to value 0"] +impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port1/pcr26.rs b/mcxa276-pac/src/port1/pcr26.rs new file mode 100644 index 000000000..24ffb3145 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr26.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR26` reader"] +pub type R = crate::R; +#[doc = "Register `PCR26` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr26Spec; +impl crate::RegisterSpec for Pcr26Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] +impl crate::Readable for Pcr26Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] +impl crate::Writable for Pcr26Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR26 to value 0"] +impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port1/pcr27.rs b/mcxa276-pac/src/port1/pcr27.rs new file mode 100644 index 000000000..ac4a51d32 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr27.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR27` reader"] +pub type R = crate::R; +#[doc = "Register `PCR27` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr27Spec; +impl crate::RegisterSpec for Pcr27Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] +impl crate::Readable for Pcr27Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] +impl crate::Writable for Pcr27Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR27 to value 0"] +impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port1/pcr28.rs b/mcxa276-pac/src/port1/pcr28.rs new file mode 100644 index 000000000..1315078be --- /dev/null +++ b/mcxa276-pac/src/port1/pcr28.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR28` reader"] +pub type R = crate::R; +#[doc = "Register `PCR28` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr28Spec; +impl crate::RegisterSpec for Pcr28Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] +impl crate::Readable for Pcr28Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] +impl crate::Writable for Pcr28Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR28 to value 0"] +impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port1/pcr29.rs b/mcxa276-pac/src/port1/pcr29.rs new file mode 100644 index 000000000..4376ab7b9 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr29.rs @@ -0,0 +1,749 @@ +#[doc = "Register `PCR29` reader"] +pub type R = crate::R; +#[doc = "Register `PCR29` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:9 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:9 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr29Spec; +impl crate::RegisterSpec for Pcr29Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] +impl crate::Readable for Pcr29Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] +impl crate::Writable for Pcr29Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR29 to value 0x0133"] +impl crate::Resettable for Pcr29Spec { + const RESET_VALUE: u32 = 0x0133; +} diff --git a/mcxa276-pac/src/port1/pcr3.rs b/mcxa276-pac/src/port1/pcr3.rs new file mode 100644 index 000000000..0bdf66c1b --- /dev/null +++ b/mcxa276-pac/src/port1/pcr3.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR3` reader"] +pub type R = crate::R; +#[doc = "Register `PCR3` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr3Spec; +impl crate::RegisterSpec for Pcr3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] +impl crate::Readable for Pcr3Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] +impl crate::Writable for Pcr3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR3 to value 0"] +impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port1/pcr30.rs b/mcxa276-pac/src/port1/pcr30.rs new file mode 100644 index 000000000..008d44c80 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr30.rs @@ -0,0 +1,940 @@ +#[doc = "Register `PCR30` reader"] +pub type R = crate::R; +#[doc = "Register `PCR30` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr30Spec; +impl crate::RegisterSpec for Pcr30Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] +impl crate::Readable for Pcr30Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] +impl crate::Writable for Pcr30Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR30 to value 0"] +impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port1/pcr31.rs b/mcxa276-pac/src/port1/pcr31.rs new file mode 100644 index 000000000..6ab9e5d70 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr31.rs @@ -0,0 +1,877 @@ +#[doc = "Register `PCR31` reader"] +pub type R = crate::R; +#[doc = "Register `PCR31` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr31Spec; +impl crate::RegisterSpec for Pcr31Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] +impl crate::Readable for Pcr31Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] +impl crate::Writable for Pcr31Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR31 to value 0"] +impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port1/pcr4.rs b/mcxa276-pac/src/port1/pcr4.rs new file mode 100644 index 000000000..9890bb2d4 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr4.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR4` reader"] +pub type R = crate::R; +#[doc = "Register `PCR4` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr4Spec; +impl crate::RegisterSpec for Pcr4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] +impl crate::Readable for Pcr4Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] +impl crate::Writable for Pcr4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR4 to value 0"] +impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port1/pcr5.rs b/mcxa276-pac/src/port1/pcr5.rs new file mode 100644 index 000000000..bbc9bfc8a --- /dev/null +++ b/mcxa276-pac/src/port1/pcr5.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR5` reader"] +pub type R = crate::R; +#[doc = "Register `PCR5` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr5Spec; +impl crate::RegisterSpec for Pcr5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] +impl crate::Readable for Pcr5Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] +impl crate::Writable for Pcr5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR5 to value 0"] +impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port1/pcr6.rs b/mcxa276-pac/src/port1/pcr6.rs new file mode 100644 index 000000000..dcc6c56c6 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr6.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR6` reader"] +pub type R = crate::R; +#[doc = "Register `PCR6` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr6Spec; +impl crate::RegisterSpec for Pcr6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] +impl crate::Readable for Pcr6Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] +impl crate::Writable for Pcr6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR6 to value 0"] +impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port1/pcr7.rs b/mcxa276-pac/src/port1/pcr7.rs new file mode 100644 index 000000000..71a9e66da --- /dev/null +++ b/mcxa276-pac/src/port1/pcr7.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR7` reader"] +pub type R = crate::R; +#[doc = "Register `PCR7` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr7Spec; +impl crate::RegisterSpec for Pcr7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] +impl crate::Readable for Pcr7Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] +impl crate::Writable for Pcr7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR7 to value 0"] +impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port1/pcr8.rs b/mcxa276-pac/src/port1/pcr8.rs new file mode 100644 index 000000000..be20db45e --- /dev/null +++ b/mcxa276-pac/src/port1/pcr8.rs @@ -0,0 +1,940 @@ +#[doc = "Register `PCR8` reader"] +pub type R = crate::R; +#[doc = "Register `PCR8` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr8Spec; +impl crate::RegisterSpec for Pcr8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] +impl crate::Readable for Pcr8Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] +impl crate::Writable for Pcr8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR8 to value 0"] +impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port1/pcr9.rs b/mcxa276-pac/src/port1/pcr9.rs new file mode 100644 index 000000000..1e64e1fb2 --- /dev/null +++ b/mcxa276-pac/src/port1/pcr9.rs @@ -0,0 +1,877 @@ +#[doc = "Register `PCR9` reader"] +pub type R = crate::R; +#[doc = "Register `PCR9` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr9Spec; +impl crate::RegisterSpec for Pcr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] +impl crate::Readable for Pcr9Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] +impl crate::Writable for Pcr9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR9 to value 0"] +impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port1/verid.rs b/mcxa276-pac/src/port1/verid.rs new file mode 100644 index 000000000..330f53d57 --- /dev/null +++ b/mcxa276-pac/src/port1/verid.rs @@ -0,0 +1,68 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Basic implementation"] + Feature0 = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Feature0), + _ => None, + } + } + #[doc = "Basic implementation"] + #[inline(always)] + pub fn is_feature0(&self) -> bool { + *self == Feature::Feature0 + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0200_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0200_0000; +} diff --git a/mcxa276-pac/src/port2.rs b/mcxa276-pac/src/port2.rs new file mode 100644 index 000000000..1f60eec3c --- /dev/null +++ b/mcxa276-pac/src/port2.rs @@ -0,0 +1,405 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x0c], + gpclr: Gpclr, + gpchr: Gpchr, + _reserved3: [u8; 0x08], + config: Config, + _reserved4: [u8; 0x5c], + pcr0: Pcr0, + pcr1: Pcr1, + pcr2: Pcr2, + pcr3: Pcr3, + pcr4: Pcr4, + pcr5: Pcr5, + pcr6: Pcr6, + pcr7: Pcr7, + pcr8: Pcr8, + pcr9: Pcr9, + pcr10: Pcr10, + pcr11: Pcr11, + pcr12: Pcr12, + pcr13: Pcr13, + pcr14: Pcr14, + pcr15: Pcr15, + pcr16: Pcr16, + pcr17: Pcr17, + pcr18: Pcr18, + pcr19: Pcr19, + pcr20: Pcr20, + pcr21: Pcr21, + pcr22: Pcr22, + pcr23: Pcr23, + pcr24: Pcr24, + pcr25: Pcr25, + pcr26: Pcr26, + pcr27: Pcr27, + pcr28: Pcr28, + pcr29: Pcr29, + pcr30: Pcr30, + pcr31: Pcr31, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x10 - Global Pin Control Low"] + #[inline(always)] + pub const fn gpclr(&self) -> &Gpclr { + &self.gpclr + } + #[doc = "0x14 - Global Pin Control High"] + #[inline(always)] + pub const fn gpchr(&self) -> &Gpchr { + &self.gpchr + } + #[doc = "0x20 - Configuration"] + #[inline(always)] + pub const fn config(&self) -> &Config { + &self.config + } + #[doc = "0x80 - Pin Control 0"] + #[inline(always)] + pub const fn pcr0(&self) -> &Pcr0 { + &self.pcr0 + } + #[doc = "0x84 - Pin Control 1"] + #[inline(always)] + pub const fn pcr1(&self) -> &Pcr1 { + &self.pcr1 + } + #[doc = "0x88 - Pin Control 2"] + #[inline(always)] + pub const fn pcr2(&self) -> &Pcr2 { + &self.pcr2 + } + #[doc = "0x8c - Pin Control 3"] + #[inline(always)] + pub const fn pcr3(&self) -> &Pcr3 { + &self.pcr3 + } + #[doc = "0x90 - Pin Control 4"] + #[inline(always)] + pub const fn pcr4(&self) -> &Pcr4 { + &self.pcr4 + } + #[doc = "0x94 - Pin Control 5"] + #[inline(always)] + pub const fn pcr5(&self) -> &Pcr5 { + &self.pcr5 + } + #[doc = "0x98 - Pin Control 6"] + #[inline(always)] + pub const fn pcr6(&self) -> &Pcr6 { + &self.pcr6 + } + #[doc = "0x9c - Pin Control 7"] + #[inline(always)] + pub const fn pcr7(&self) -> &Pcr7 { + &self.pcr7 + } + #[doc = "0xa0 - Pin Control 8"] + #[inline(always)] + pub const fn pcr8(&self) -> &Pcr8 { + &self.pcr8 + } + #[doc = "0xa4 - Pin Control 9"] + #[inline(always)] + pub const fn pcr9(&self) -> &Pcr9 { + &self.pcr9 + } + #[doc = "0xa8 - Pin Control 10"] + #[inline(always)] + pub const fn pcr10(&self) -> &Pcr10 { + &self.pcr10 + } + #[doc = "0xac - Pin Control 11"] + #[inline(always)] + pub const fn pcr11(&self) -> &Pcr11 { + &self.pcr11 + } + #[doc = "0xb0 - Pin Control 12"] + #[inline(always)] + pub const fn pcr12(&self) -> &Pcr12 { + &self.pcr12 + } + #[doc = "0xb4 - Pin Control 13"] + #[inline(always)] + pub const fn pcr13(&self) -> &Pcr13 { + &self.pcr13 + } + #[doc = "0xb8 - Pin Control 14"] + #[inline(always)] + pub const fn pcr14(&self) -> &Pcr14 { + &self.pcr14 + } + #[doc = "0xbc - Pin Control 15"] + #[inline(always)] + pub const fn pcr15(&self) -> &Pcr15 { + &self.pcr15 + } + #[doc = "0xc0 - Pin Control 16"] + #[inline(always)] + pub const fn pcr16(&self) -> &Pcr16 { + &self.pcr16 + } + #[doc = "0xc4 - Pin Control 17"] + #[inline(always)] + pub const fn pcr17(&self) -> &Pcr17 { + &self.pcr17 + } + #[doc = "0xc8 - Pin Control 18"] + #[inline(always)] + pub const fn pcr18(&self) -> &Pcr18 { + &self.pcr18 + } + #[doc = "0xcc - Pin Control 19"] + #[inline(always)] + pub const fn pcr19(&self) -> &Pcr19 { + &self.pcr19 + } + #[doc = "0xd0 - Pin Control 20"] + #[inline(always)] + pub const fn pcr20(&self) -> &Pcr20 { + &self.pcr20 + } + #[doc = "0xd4 - Pin Control 21"] + #[inline(always)] + pub const fn pcr21(&self) -> &Pcr21 { + &self.pcr21 + } + #[doc = "0xd8 - Pin Control 22"] + #[inline(always)] + pub const fn pcr22(&self) -> &Pcr22 { + &self.pcr22 + } + #[doc = "0xdc - Pin Control 23"] + #[inline(always)] + pub const fn pcr23(&self) -> &Pcr23 { + &self.pcr23 + } + #[doc = "0xe0 - Pin Control 24"] + #[inline(always)] + pub const fn pcr24(&self) -> &Pcr24 { + &self.pcr24 + } + #[doc = "0xe4 - Pin Control 25"] + #[inline(always)] + pub const fn pcr25(&self) -> &Pcr25 { + &self.pcr25 + } + #[doc = "0xe8 - Pin Control 26"] + #[inline(always)] + pub const fn pcr26(&self) -> &Pcr26 { + &self.pcr26 + } + #[doc = "0xec - Pin Control 27"] + #[inline(always)] + pub const fn pcr27(&self) -> &Pcr27 { + &self.pcr27 + } + #[doc = "0xf0 - Pin Control 28"] + #[inline(always)] + pub const fn pcr28(&self) -> &Pcr28 { + &self.pcr28 + } + #[doc = "0xf4 - Pin Control 29"] + #[inline(always)] + pub const fn pcr29(&self) -> &Pcr29 { + &self.pcr29 + } + #[doc = "0xf8 - Pin Control 30"] + #[inline(always)] + pub const fn pcr30(&self) -> &Pcr30 { + &self.pcr30 + } + #[doc = "0xfc - Pin Control 31"] + #[inline(always)] + pub const fn pcr31(&self) -> &Pcr31 { + &self.pcr31 + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] +#[doc(alias = "GPCLR")] +pub type Gpclr = crate::Reg; +#[doc = "Global Pin Control Low"] +pub mod gpclr; +#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] +#[doc(alias = "GPCHR")] +pub type Gpchr = crate::Reg; +#[doc = "Global Pin Control High"] +pub mod gpchr; +#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +#[doc(alias = "CONFIG")] +pub type Config = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] +#[doc(alias = "PCR0")] +pub type Pcr0 = crate::Reg; +#[doc = "Pin Control 0"] +pub mod pcr0; +#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] +#[doc(alias = "PCR1")] +pub type Pcr1 = crate::Reg; +#[doc = "Pin Control 1"] +pub mod pcr1; +#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] +#[doc(alias = "PCR2")] +pub type Pcr2 = crate::Reg; +#[doc = "Pin Control 2"] +pub mod pcr2; +#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] +#[doc(alias = "PCR3")] +pub type Pcr3 = crate::Reg; +#[doc = "Pin Control 3"] +pub mod pcr3; +#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] +#[doc(alias = "PCR4")] +pub type Pcr4 = crate::Reg; +#[doc = "Pin Control 4"] +pub mod pcr4; +#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] +#[doc(alias = "PCR5")] +pub type Pcr5 = crate::Reg; +#[doc = "Pin Control 5"] +pub mod pcr5; +#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] +#[doc(alias = "PCR6")] +pub type Pcr6 = crate::Reg; +#[doc = "Pin Control 6"] +pub mod pcr6; +#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] +#[doc(alias = "PCR7")] +pub type Pcr7 = crate::Reg; +#[doc = "Pin Control 7"] +pub mod pcr7; +#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] +#[doc(alias = "PCR8")] +pub type Pcr8 = crate::Reg; +#[doc = "Pin Control 8"] +pub mod pcr8; +#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] +#[doc(alias = "PCR9")] +pub type Pcr9 = crate::Reg; +#[doc = "Pin Control 9"] +pub mod pcr9; +#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] +#[doc(alias = "PCR10")] +pub type Pcr10 = crate::Reg; +#[doc = "Pin Control 10"] +pub mod pcr10; +#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] +#[doc(alias = "PCR11")] +pub type Pcr11 = crate::Reg; +#[doc = "Pin Control 11"] +pub mod pcr11; +#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] +#[doc(alias = "PCR12")] +pub type Pcr12 = crate::Reg; +#[doc = "Pin Control 12"] +pub mod pcr12; +#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] +#[doc(alias = "PCR13")] +pub type Pcr13 = crate::Reg; +#[doc = "Pin Control 13"] +pub mod pcr13; +#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] +#[doc(alias = "PCR14")] +pub type Pcr14 = crate::Reg; +#[doc = "Pin Control 14"] +pub mod pcr14; +#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] +#[doc(alias = "PCR15")] +pub type Pcr15 = crate::Reg; +#[doc = "Pin Control 15"] +pub mod pcr15; +#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] +#[doc(alias = "PCR16")] +pub type Pcr16 = crate::Reg; +#[doc = "Pin Control 16"] +pub mod pcr16; +#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] +#[doc(alias = "PCR17")] +pub type Pcr17 = crate::Reg; +#[doc = "Pin Control 17"] +pub mod pcr17; +#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] +#[doc(alias = "PCR18")] +pub type Pcr18 = crate::Reg; +#[doc = "Pin Control 18"] +pub mod pcr18; +#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] +#[doc(alias = "PCR19")] +pub type Pcr19 = crate::Reg; +#[doc = "Pin Control 19"] +pub mod pcr19; +#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] +#[doc(alias = "PCR20")] +pub type Pcr20 = crate::Reg; +#[doc = "Pin Control 20"] +pub mod pcr20; +#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] +#[doc(alias = "PCR21")] +pub type Pcr21 = crate::Reg; +#[doc = "Pin Control 21"] +pub mod pcr21; +#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] +#[doc(alias = "PCR22")] +pub type Pcr22 = crate::Reg; +#[doc = "Pin Control 22"] +pub mod pcr22; +#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] +#[doc(alias = "PCR23")] +pub type Pcr23 = crate::Reg; +#[doc = "Pin Control 23"] +pub mod pcr23; +#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] +#[doc(alias = "PCR24")] +pub type Pcr24 = crate::Reg; +#[doc = "Pin Control 24"] +pub mod pcr24; +#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] +#[doc(alias = "PCR25")] +pub type Pcr25 = crate::Reg; +#[doc = "Pin Control 25"] +pub mod pcr25; +#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] +#[doc(alias = "PCR26")] +pub type Pcr26 = crate::Reg; +#[doc = "Pin Control 26"] +pub mod pcr26; +#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] +#[doc(alias = "PCR27")] +pub type Pcr27 = crate::Reg; +#[doc = "Pin Control 27"] +pub mod pcr27; +#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] +#[doc(alias = "PCR28")] +pub type Pcr28 = crate::Reg; +#[doc = "Pin Control 28"] +pub mod pcr28; +#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] +#[doc(alias = "PCR29")] +pub type Pcr29 = crate::Reg; +#[doc = "Pin Control 29"] +pub mod pcr29; +#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] +#[doc(alias = "PCR30")] +pub type Pcr30 = crate::Reg; +#[doc = "Pin Control 30"] +pub mod pcr30; +#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] +#[doc(alias = "PCR31")] +pub type Pcr31 = crate::Reg; +#[doc = "Pin Control 31"] +pub mod pcr31; diff --git a/mcxa276-pac/src/port2/config.rs b/mcxa276-pac/src/port2/config.rs new file mode 100644 index 000000000..da92c5b27 --- /dev/null +++ b/mcxa276-pac/src/port2/config.rs @@ -0,0 +1,84 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Port Voltage Range\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Range { + #[doc = "0: 1.71 V-3.6 V"] + Range0 = 0, + #[doc = "1: 2.70 V-3.6 V"] + Range1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Range) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RANGE` reader - Port Voltage Range"] +pub type RangeR = crate::BitReader; +impl RangeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Range { + match self.bits { + false => Range::Range0, + true => Range::Range1, + } + } + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn is_range0(&self) -> bool { + *self == Range::Range0 + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn is_range1(&self) -> bool { + *self == Range::Range1 + } +} +#[doc = "Field `RANGE` writer - Port Voltage Range"] +pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; +impl<'a, REG> RangeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn range0(self) -> &'a mut crate::W { + self.variant(Range::Range0) + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn range1(self) -> &'a mut crate::W { + self.variant(Range::Range1) + } +} +impl R { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&self) -> RangeR { + RangeR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&mut self) -> RangeW { + RangeW::new(self, 0) + } +} +#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConfigSpec; +impl crate::RegisterSpec for ConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for ConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for ConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port2/gpchr.rs b/mcxa276-pac/src/port2/gpchr.rs new file mode 100644 index 000000000..af92d0d62 --- /dev/null +++ b/mcxa276-pac/src/port2/gpchr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCHR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCHR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe16 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] +pub type Gpwe16R = crate::BitReader; +impl Gpwe16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe16 { + match self.bits { + false => Gpwe16::Gpwe0, + true => Gpwe16::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe16::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe16::Gpwe1 + } +} +#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] +pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; +impl<'a, REG> Gpwe16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe17 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] +pub type Gpwe17R = crate::BitReader; +impl Gpwe17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe17 { + match self.bits { + false => Gpwe17::Gpwe0, + true => Gpwe17::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe17::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe17::Gpwe1 + } +} +#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] +pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; +impl<'a, REG> Gpwe17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe18 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] +pub type Gpwe18R = crate::BitReader; +impl Gpwe18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe18 { + match self.bits { + false => Gpwe18::Gpwe0, + true => Gpwe18::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe18::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe18::Gpwe1 + } +} +#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] +pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; +impl<'a, REG> Gpwe18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe19 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] +pub type Gpwe19R = crate::BitReader; +impl Gpwe19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe19 { + match self.bits { + false => Gpwe19::Gpwe0, + true => Gpwe19::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe19::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe19::Gpwe1 + } +} +#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] +pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; +impl<'a, REG> Gpwe19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe20 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] +pub type Gpwe20R = crate::BitReader; +impl Gpwe20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe20 { + match self.bits { + false => Gpwe20::Gpwe0, + true => Gpwe20::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe20::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe20::Gpwe1 + } +} +#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] +pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; +impl<'a, REG> Gpwe20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe21 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] +pub type Gpwe21R = crate::BitReader; +impl Gpwe21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe21 { + match self.bits { + false => Gpwe21::Gpwe0, + true => Gpwe21::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe21::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe21::Gpwe1 + } +} +#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] +pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; +impl<'a, REG> Gpwe21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe22 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] +pub type Gpwe22R = crate::BitReader; +impl Gpwe22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe22 { + match self.bits { + false => Gpwe22::Gpwe0, + true => Gpwe22::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe22::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe22::Gpwe1 + } +} +#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] +pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; +impl<'a, REG> Gpwe22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe23 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] +pub type Gpwe23R = crate::BitReader; +impl Gpwe23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe23 { + match self.bits { + false => Gpwe23::Gpwe0, + true => Gpwe23::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe23::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe23::Gpwe1 + } +} +#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] +pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; +impl<'a, REG> Gpwe23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe24 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] +pub type Gpwe24R = crate::BitReader; +impl Gpwe24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe24 { + match self.bits { + false => Gpwe24::Gpwe0, + true => Gpwe24::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe24::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe24::Gpwe1 + } +} +#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] +pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; +impl<'a, REG> Gpwe24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe25 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] +pub type Gpwe25R = crate::BitReader; +impl Gpwe25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe25 { + match self.bits { + false => Gpwe25::Gpwe0, + true => Gpwe25::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe25::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe25::Gpwe1 + } +} +#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] +pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; +impl<'a, REG> Gpwe25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe26 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] +pub type Gpwe26R = crate::BitReader; +impl Gpwe26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe26 { + match self.bits { + false => Gpwe26::Gpwe0, + true => Gpwe26::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe26::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe26::Gpwe1 + } +} +#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] +pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; +impl<'a, REG> Gpwe26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe27 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] +pub type Gpwe27R = crate::BitReader; +impl Gpwe27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe27 { + match self.bits { + false => Gpwe27::Gpwe0, + true => Gpwe27::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe27::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe27::Gpwe1 + } +} +#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] +pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; +impl<'a, REG> Gpwe27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe28 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] +pub type Gpwe28R = crate::BitReader; +impl Gpwe28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe28 { + match self.bits { + false => Gpwe28::Gpwe0, + true => Gpwe28::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe28::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe28::Gpwe1 + } +} +#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] +pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; +impl<'a, REG> Gpwe28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe29 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] +pub type Gpwe29R = crate::BitReader; +impl Gpwe29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe29 { + match self.bits { + false => Gpwe29::Gpwe0, + true => Gpwe29::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe29::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe29::Gpwe1 + } +} +#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] +pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; +impl<'a, REG> Gpwe29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe30 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] +pub type Gpwe30R = crate::BitReader; +impl Gpwe30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe30 { + match self.bits { + false => Gpwe30::Gpwe0, + true => Gpwe30::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe30::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe30::Gpwe1 + } +} +#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] +pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; +impl<'a, REG> Gpwe30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe31 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] +pub type Gpwe31R = crate::BitReader; +impl Gpwe31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe31 { + match self.bits { + false => Gpwe31::Gpwe0, + true => Gpwe31::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe31::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe31::Gpwe1 + } +} +#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] +pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; +impl<'a, REG> Gpwe31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&self) -> Gpwe16R { + Gpwe16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&self) -> Gpwe17R { + Gpwe17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&self) -> Gpwe18R { + Gpwe18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&self) -> Gpwe19R { + Gpwe19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&self) -> Gpwe20R { + Gpwe20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&self) -> Gpwe21R { + Gpwe21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&self) -> Gpwe22R { + Gpwe22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&self) -> Gpwe23R { + Gpwe23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&self) -> Gpwe24R { + Gpwe24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&self) -> Gpwe25R { + Gpwe25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&self) -> Gpwe26R { + Gpwe26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&self) -> Gpwe27R { + Gpwe27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&self) -> Gpwe28R { + Gpwe28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&self) -> Gpwe29R { + Gpwe29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&self) -> Gpwe30R { + Gpwe30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&self) -> Gpwe31R { + Gpwe31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&mut self) -> Gpwe16W { + Gpwe16W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&mut self) -> Gpwe17W { + Gpwe17W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&mut self) -> Gpwe18W { + Gpwe18W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&mut self) -> Gpwe19W { + Gpwe19W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&mut self) -> Gpwe20W { + Gpwe20W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&mut self) -> Gpwe21W { + Gpwe21W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&mut self) -> Gpwe22W { + Gpwe22W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&mut self) -> Gpwe23W { + Gpwe23W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&mut self) -> Gpwe24W { + Gpwe24W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&mut self) -> Gpwe25W { + Gpwe25W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&mut self) -> Gpwe26W { + Gpwe26W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&mut self) -> Gpwe27W { + Gpwe27W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&mut self) -> Gpwe28W { + Gpwe28W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&mut self) -> Gpwe29W { + Gpwe29W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&mut self) -> Gpwe30W { + Gpwe30W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&mut self) -> Gpwe31W { + Gpwe31W::new(self, 31) + } +} +#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpchrSpec; +impl crate::RegisterSpec for GpchrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] +impl crate::Readable for GpchrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] +impl crate::Writable for GpchrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCHR to value 0"] +impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port2/gpclr.rs b/mcxa276-pac/src/port2/gpclr.rs new file mode 100644 index 000000000..21e5ff23d --- /dev/null +++ b/mcxa276-pac/src/port2/gpclr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe0 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] +pub type Gpwe0R = crate::BitReader; +impl Gpwe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe0 { + match self.bits { + false => Gpwe0::Gpwe0, + true => Gpwe0::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe0::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe0::Gpwe1 + } +} +#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] +pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; +impl<'a, REG> Gpwe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe1 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] +pub type Gpwe1R = crate::BitReader; +impl Gpwe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe1 { + match self.bits { + false => Gpwe1::Gpwe0, + true => Gpwe1::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe1::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe1::Gpwe1 + } +} +#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] +pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; +impl<'a, REG> Gpwe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe2 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] +pub type Gpwe2R = crate::BitReader; +impl Gpwe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe2 { + match self.bits { + false => Gpwe2::Gpwe0, + true => Gpwe2::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe2::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe2::Gpwe1 + } +} +#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] +pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; +impl<'a, REG> Gpwe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe3 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] +pub type Gpwe3R = crate::BitReader; +impl Gpwe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe3 { + match self.bits { + false => Gpwe3::Gpwe0, + true => Gpwe3::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe3::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe3::Gpwe1 + } +} +#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] +pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; +impl<'a, REG> Gpwe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe4 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] +pub type Gpwe4R = crate::BitReader; +impl Gpwe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe4 { + match self.bits { + false => Gpwe4::Gpwe0, + true => Gpwe4::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe4::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe4::Gpwe1 + } +} +#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] +pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; +impl<'a, REG> Gpwe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe5 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] +pub type Gpwe5R = crate::BitReader; +impl Gpwe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe5 { + match self.bits { + false => Gpwe5::Gpwe0, + true => Gpwe5::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe5::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe5::Gpwe1 + } +} +#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] +pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; +impl<'a, REG> Gpwe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe6 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] +pub type Gpwe6R = crate::BitReader; +impl Gpwe6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe6 { + match self.bits { + false => Gpwe6::Gpwe0, + true => Gpwe6::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe6::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe6::Gpwe1 + } +} +#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] +pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; +impl<'a, REG> Gpwe6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe7 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] +pub type Gpwe7R = crate::BitReader; +impl Gpwe7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe7 { + match self.bits { + false => Gpwe7::Gpwe0, + true => Gpwe7::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe7::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe7::Gpwe1 + } +} +#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] +pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; +impl<'a, REG> Gpwe7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe8 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] +pub type Gpwe8R = crate::BitReader; +impl Gpwe8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe8 { + match self.bits { + false => Gpwe8::Gpwe0, + true => Gpwe8::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe8::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe8::Gpwe1 + } +} +#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] +pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; +impl<'a, REG> Gpwe8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe9 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] +pub type Gpwe9R = crate::BitReader; +impl Gpwe9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe9 { + match self.bits { + false => Gpwe9::Gpwe0, + true => Gpwe9::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe9::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe9::Gpwe1 + } +} +#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] +pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; +impl<'a, REG> Gpwe9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe10 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] +pub type Gpwe10R = crate::BitReader; +impl Gpwe10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe10 { + match self.bits { + false => Gpwe10::Gpwe0, + true => Gpwe10::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe10::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe10::Gpwe1 + } +} +#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] +pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; +impl<'a, REG> Gpwe10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe11 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] +pub type Gpwe11R = crate::BitReader; +impl Gpwe11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe11 { + match self.bits { + false => Gpwe11::Gpwe0, + true => Gpwe11::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe11::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe11::Gpwe1 + } +} +#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] +pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; +impl<'a, REG> Gpwe11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe12 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] +pub type Gpwe12R = crate::BitReader; +impl Gpwe12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe12 { + match self.bits { + false => Gpwe12::Gpwe0, + true => Gpwe12::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe12::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe12::Gpwe1 + } +} +#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] +pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; +impl<'a, REG> Gpwe12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe13 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] +pub type Gpwe13R = crate::BitReader; +impl Gpwe13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe13 { + match self.bits { + false => Gpwe13::Gpwe0, + true => Gpwe13::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe13::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe13::Gpwe1 + } +} +#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] +pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; +impl<'a, REG> Gpwe13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe14 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] +pub type Gpwe14R = crate::BitReader; +impl Gpwe14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe14 { + match self.bits { + false => Gpwe14::Gpwe0, + true => Gpwe14::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe14::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe14::Gpwe1 + } +} +#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] +pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; +impl<'a, REG> Gpwe14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe15 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] +pub type Gpwe15R = crate::BitReader; +impl Gpwe15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe15 { + match self.bits { + false => Gpwe15::Gpwe0, + true => Gpwe15::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe15::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe15::Gpwe1 + } +} +#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] +pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; +impl<'a, REG> Gpwe15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&self) -> Gpwe0R { + Gpwe0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&self) -> Gpwe1R { + Gpwe1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&self) -> Gpwe2R { + Gpwe2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&self) -> Gpwe3R { + Gpwe3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&self) -> Gpwe4R { + Gpwe4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&self) -> Gpwe5R { + Gpwe5R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&self) -> Gpwe6R { + Gpwe6R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&self) -> Gpwe7R { + Gpwe7R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&self) -> Gpwe8R { + Gpwe8R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&self) -> Gpwe9R { + Gpwe9R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&self) -> Gpwe10R { + Gpwe10R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&self) -> Gpwe11R { + Gpwe11R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&self) -> Gpwe12R { + Gpwe12R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&self) -> Gpwe13R { + Gpwe13R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&self) -> Gpwe14R { + Gpwe14R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&self) -> Gpwe15R { + Gpwe15R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&mut self) -> Gpwe0W { + Gpwe0W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&mut self) -> Gpwe1W { + Gpwe1W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&mut self) -> Gpwe2W { + Gpwe2W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&mut self) -> Gpwe3W { + Gpwe3W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&mut self) -> Gpwe4W { + Gpwe4W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&mut self) -> Gpwe5W { + Gpwe5W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&mut self) -> Gpwe6W { + Gpwe6W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&mut self) -> Gpwe7W { + Gpwe7W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&mut self) -> Gpwe8W { + Gpwe8W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&mut self) -> Gpwe9W { + Gpwe9W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&mut self) -> Gpwe10W { + Gpwe10W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&mut self) -> Gpwe11W { + Gpwe11W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&mut self) -> Gpwe12W { + Gpwe12W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&mut self) -> Gpwe13W { + Gpwe13W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&mut self) -> Gpwe14W { + Gpwe14W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&mut self) -> Gpwe15W { + Gpwe15W::new(self, 31) + } +} +#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpclrSpec; +impl crate::RegisterSpec for GpclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] +impl crate::Readable for GpclrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] +impl crate::Writable for GpclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCLR to value 0"] +impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port2/pcr0.rs b/mcxa276-pac/src/port2/pcr0.rs new file mode 100644 index 000000000..673ac781a --- /dev/null +++ b/mcxa276-pac/src/port2/pcr0.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR0` reader"] +pub type R = crate::R; +#[doc = "Register `PCR0` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr0Spec; +impl crate::RegisterSpec for Pcr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] +impl crate::Readable for Pcr0Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] +impl crate::Writable for Pcr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR0 to value 0"] +impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port2/pcr1.rs b/mcxa276-pac/src/port2/pcr1.rs new file mode 100644 index 000000000..658d2dec6 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr1.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR1` reader"] +pub type R = crate::R; +#[doc = "Register `PCR1` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr1Spec; +impl crate::RegisterSpec for Pcr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] +impl crate::Readable for Pcr1Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] +impl crate::Writable for Pcr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR1 to value 0"] +impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port2/pcr10.rs b/mcxa276-pac/src/port2/pcr10.rs new file mode 100644 index 000000000..c4f453255 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr10.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR10` reader"] +pub type R = crate::R; +#[doc = "Register `PCR10` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr10Spec; +impl crate::RegisterSpec for Pcr10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] +impl crate::Readable for Pcr10Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] +impl crate::Writable for Pcr10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR10 to value 0"] +impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port2/pcr11.rs b/mcxa276-pac/src/port2/pcr11.rs new file mode 100644 index 000000000..aba6888ef --- /dev/null +++ b/mcxa276-pac/src/port2/pcr11.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR11` reader"] +pub type R = crate::R; +#[doc = "Register `PCR11` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr11Spec; +impl crate::RegisterSpec for Pcr11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] +impl crate::Readable for Pcr11Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] +impl crate::Writable for Pcr11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR11 to value 0"] +impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port2/pcr12.rs b/mcxa276-pac/src/port2/pcr12.rs new file mode 100644 index 000000000..2cd7eecc1 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr12.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR12` reader"] +pub type R = crate::R; +#[doc = "Register `PCR12` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr12Spec; +impl crate::RegisterSpec for Pcr12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] +impl crate::Readable for Pcr12Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] +impl crate::Writable for Pcr12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR12 to value 0"] +impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port2/pcr13.rs b/mcxa276-pac/src/port2/pcr13.rs new file mode 100644 index 000000000..0da9c8d55 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr13.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR13` reader"] +pub type R = crate::R; +#[doc = "Register `PCR13` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr13Spec; +impl crate::RegisterSpec for Pcr13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] +impl crate::Readable for Pcr13Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] +impl crate::Writable for Pcr13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR13 to value 0"] +impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port2/pcr14.rs b/mcxa276-pac/src/port2/pcr14.rs new file mode 100644 index 000000000..8f9a8684c --- /dev/null +++ b/mcxa276-pac/src/port2/pcr14.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR14` reader"] +pub type R = crate::R; +#[doc = "Register `PCR14` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr14Spec; +impl crate::RegisterSpec for Pcr14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] +impl crate::Readable for Pcr14Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] +impl crate::Writable for Pcr14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR14 to value 0"] +impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port2/pcr15.rs b/mcxa276-pac/src/port2/pcr15.rs new file mode 100644 index 000000000..85c188f6b --- /dev/null +++ b/mcxa276-pac/src/port2/pcr15.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR15` reader"] +pub type R = crate::R; +#[doc = "Register `PCR15` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr15Spec; +impl crate::RegisterSpec for Pcr15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] +impl crate::Readable for Pcr15Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] +impl crate::Writable for Pcr15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR15 to value 0"] +impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port2/pcr16.rs b/mcxa276-pac/src/port2/pcr16.rs new file mode 100644 index 000000000..70c9dda78 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr16.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR16` reader"] +pub type R = crate::R; +#[doc = "Register `PCR16` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr16Spec; +impl crate::RegisterSpec for Pcr16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] +impl crate::Readable for Pcr16Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] +impl crate::Writable for Pcr16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR16 to value 0"] +impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port2/pcr17.rs b/mcxa276-pac/src/port2/pcr17.rs new file mode 100644 index 000000000..6e9da55ac --- /dev/null +++ b/mcxa276-pac/src/port2/pcr17.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR17` reader"] +pub type R = crate::R; +#[doc = "Register `PCR17` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr17Spec; +impl crate::RegisterSpec for Pcr17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] +impl crate::Readable for Pcr17Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] +impl crate::Writable for Pcr17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR17 to value 0"] +impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port2/pcr18.rs b/mcxa276-pac/src/port2/pcr18.rs new file mode 100644 index 000000000..9aad79b05 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr18.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR18` reader"] +pub type R = crate::R; +#[doc = "Register `PCR18` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr18Spec; +impl crate::RegisterSpec for Pcr18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] +impl crate::Readable for Pcr18Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] +impl crate::Writable for Pcr18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR18 to value 0"] +impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port2/pcr19.rs b/mcxa276-pac/src/port2/pcr19.rs new file mode 100644 index 000000000..43bb23f08 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr19.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR19` reader"] +pub type R = crate::R; +#[doc = "Register `PCR19` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr19Spec; +impl crate::RegisterSpec for Pcr19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] +impl crate::Readable for Pcr19Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] +impl crate::Writable for Pcr19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR19 to value 0"] +impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port2/pcr2.rs b/mcxa276-pac/src/port2/pcr2.rs new file mode 100644 index 000000000..2bdea035c --- /dev/null +++ b/mcxa276-pac/src/port2/pcr2.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR2` reader"] +pub type R = crate::R; +#[doc = "Register `PCR2` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr2Spec; +impl crate::RegisterSpec for Pcr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] +impl crate::Readable for Pcr2Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] +impl crate::Writable for Pcr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR2 to value 0"] +impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port2/pcr20.rs b/mcxa276-pac/src/port2/pcr20.rs new file mode 100644 index 000000000..d1a076a4a --- /dev/null +++ b/mcxa276-pac/src/port2/pcr20.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR20` reader"] +pub type R = crate::R; +#[doc = "Register `PCR20` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr20Spec; +impl crate::RegisterSpec for Pcr20Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] +impl crate::Readable for Pcr20Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] +impl crate::Writable for Pcr20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR20 to value 0"] +impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port2/pcr21.rs b/mcxa276-pac/src/port2/pcr21.rs new file mode 100644 index 000000000..1ec184fea --- /dev/null +++ b/mcxa276-pac/src/port2/pcr21.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR21` reader"] +pub type R = crate::R; +#[doc = "Register `PCR21` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr21Spec; +impl crate::RegisterSpec for Pcr21Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] +impl crate::Readable for Pcr21Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] +impl crate::Writable for Pcr21Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR21 to value 0"] +impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port2/pcr22.rs b/mcxa276-pac/src/port2/pcr22.rs new file mode 100644 index 000000000..9da7aaab1 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr22.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR22` reader"] +pub type R = crate::R; +#[doc = "Register `PCR22` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr22Spec; +impl crate::RegisterSpec for Pcr22Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] +impl crate::Readable for Pcr22Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] +impl crate::Writable for Pcr22Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR22 to value 0"] +impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port2/pcr23.rs b/mcxa276-pac/src/port2/pcr23.rs new file mode 100644 index 000000000..d8bb46a64 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr23.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR23` reader"] +pub type R = crate::R; +#[doc = "Register `PCR23` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr23Spec; +impl crate::RegisterSpec for Pcr23Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] +impl crate::Readable for Pcr23Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] +impl crate::Writable for Pcr23Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR23 to value 0"] +impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port2/pcr24.rs b/mcxa276-pac/src/port2/pcr24.rs new file mode 100644 index 000000000..e9e31834d --- /dev/null +++ b/mcxa276-pac/src/port2/pcr24.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR24` reader"] +pub type R = crate::R; +#[doc = "Register `PCR24` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr24Spec; +impl crate::RegisterSpec for Pcr24Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] +impl crate::Readable for Pcr24Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] +impl crate::Writable for Pcr24Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR24 to value 0"] +impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port2/pcr25.rs b/mcxa276-pac/src/port2/pcr25.rs new file mode 100644 index 000000000..5d0319242 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr25.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR25` reader"] +pub type R = crate::R; +#[doc = "Register `PCR25` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr25Spec; +impl crate::RegisterSpec for Pcr25Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] +impl crate::Readable for Pcr25Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] +impl crate::Writable for Pcr25Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR25 to value 0"] +impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port2/pcr26.rs b/mcxa276-pac/src/port2/pcr26.rs new file mode 100644 index 000000000..1554cb836 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr26.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR26` reader"] +pub type R = crate::R; +#[doc = "Register `PCR26` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr26Spec; +impl crate::RegisterSpec for Pcr26Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] +impl crate::Readable for Pcr26Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] +impl crate::Writable for Pcr26Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR26 to value 0"] +impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port2/pcr27.rs b/mcxa276-pac/src/port2/pcr27.rs new file mode 100644 index 000000000..ac4a51d32 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr27.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR27` reader"] +pub type R = crate::R; +#[doc = "Register `PCR27` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr27Spec; +impl crate::RegisterSpec for Pcr27Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] +impl crate::Readable for Pcr27Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] +impl crate::Writable for Pcr27Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR27 to value 0"] +impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port2/pcr28.rs b/mcxa276-pac/src/port2/pcr28.rs new file mode 100644 index 000000000..1315078be --- /dev/null +++ b/mcxa276-pac/src/port2/pcr28.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR28` reader"] +pub type R = crate::R; +#[doc = "Register `PCR28` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr28Spec; +impl crate::RegisterSpec for Pcr28Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] +impl crate::Readable for Pcr28Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] +impl crate::Writable for Pcr28Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR28 to value 0"] +impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port2/pcr29.rs b/mcxa276-pac/src/port2/pcr29.rs new file mode 100644 index 000000000..de7c41baa --- /dev/null +++ b/mcxa276-pac/src/port2/pcr29.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR29` reader"] +pub type R = crate::R; +#[doc = "Register `PCR29` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr29Spec; +impl crate::RegisterSpec for Pcr29Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] +impl crate::Readable for Pcr29Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] +impl crate::Writable for Pcr29Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR29 to value 0"] +impl crate::Resettable for Pcr29Spec {} diff --git a/mcxa276-pac/src/port2/pcr3.rs b/mcxa276-pac/src/port2/pcr3.rs new file mode 100644 index 000000000..0bdf66c1b --- /dev/null +++ b/mcxa276-pac/src/port2/pcr3.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR3` reader"] +pub type R = crate::R; +#[doc = "Register `PCR3` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr3Spec; +impl crate::RegisterSpec for Pcr3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] +impl crate::Readable for Pcr3Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] +impl crate::Writable for Pcr3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR3 to value 0"] +impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port2/pcr30.rs b/mcxa276-pac/src/port2/pcr30.rs new file mode 100644 index 000000000..cce4166f4 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr30.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR30` reader"] +pub type R = crate::R; +#[doc = "Register `PCR30` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr30Spec; +impl crate::RegisterSpec for Pcr30Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] +impl crate::Readable for Pcr30Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] +impl crate::Writable for Pcr30Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR30 to value 0"] +impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port2/pcr31.rs b/mcxa276-pac/src/port2/pcr31.rs new file mode 100644 index 000000000..1f49159c2 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr31.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR31` reader"] +pub type R = crate::R; +#[doc = "Register `PCR31` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr31Spec; +impl crate::RegisterSpec for Pcr31Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] +impl crate::Readable for Pcr31Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] +impl crate::Writable for Pcr31Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR31 to value 0"] +impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port2/pcr4.rs b/mcxa276-pac/src/port2/pcr4.rs new file mode 100644 index 000000000..970ee4531 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr4.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR4` reader"] +pub type R = crate::R; +#[doc = "Register `PCR4` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr4Spec; +impl crate::RegisterSpec for Pcr4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] +impl crate::Readable for Pcr4Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] +impl crate::Writable for Pcr4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR4 to value 0"] +impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port2/pcr5.rs b/mcxa276-pac/src/port2/pcr5.rs new file mode 100644 index 000000000..53dad0e29 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr5.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR5` reader"] +pub type R = crate::R; +#[doc = "Register `PCR5` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr5Spec; +impl crate::RegisterSpec for Pcr5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] +impl crate::Readable for Pcr5Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] +impl crate::Writable for Pcr5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR5 to value 0"] +impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port2/pcr6.rs b/mcxa276-pac/src/port2/pcr6.rs new file mode 100644 index 000000000..d10e6a5b8 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr6.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR6` reader"] +pub type R = crate::R; +#[doc = "Register `PCR6` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr6Spec; +impl crate::RegisterSpec for Pcr6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] +impl crate::Readable for Pcr6Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] +impl crate::Writable for Pcr6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR6 to value 0"] +impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port2/pcr7.rs b/mcxa276-pac/src/port2/pcr7.rs new file mode 100644 index 000000000..71a9e66da --- /dev/null +++ b/mcxa276-pac/src/port2/pcr7.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR7` reader"] +pub type R = crate::R; +#[doc = "Register `PCR7` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr7Spec; +impl crate::RegisterSpec for Pcr7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] +impl crate::Readable for Pcr7Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] +impl crate::Writable for Pcr7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR7 to value 0"] +impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port2/pcr8.rs b/mcxa276-pac/src/port2/pcr8.rs new file mode 100644 index 000000000..c4c474965 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr8.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR8` reader"] +pub type R = crate::R; +#[doc = "Register `PCR8` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr8Spec; +impl crate::RegisterSpec for Pcr8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] +impl crate::Readable for Pcr8Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] +impl crate::Writable for Pcr8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR8 to value 0"] +impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port2/pcr9.rs b/mcxa276-pac/src/port2/pcr9.rs new file mode 100644 index 000000000..92a28f062 --- /dev/null +++ b/mcxa276-pac/src/port2/pcr9.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR9` reader"] +pub type R = crate::R; +#[doc = "Register `PCR9` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr9Spec; +impl crate::RegisterSpec for Pcr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] +impl crate::Readable for Pcr9Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] +impl crate::Writable for Pcr9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR9 to value 0"] +impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port2/verid.rs b/mcxa276-pac/src/port2/verid.rs new file mode 100644 index 000000000..330f53d57 --- /dev/null +++ b/mcxa276-pac/src/port2/verid.rs @@ -0,0 +1,68 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Basic implementation"] + Feature0 = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Feature0), + _ => None, + } + } + #[doc = "Basic implementation"] + #[inline(always)] + pub fn is_feature0(&self) -> bool { + *self == Feature::Feature0 + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0200_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0200_0000; +} diff --git a/mcxa276-pac/src/port3.rs b/mcxa276-pac/src/port3.rs new file mode 100644 index 000000000..d7ed05fc0 --- /dev/null +++ b/mcxa276-pac/src/port3.rs @@ -0,0 +1,428 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x0c], + gpclr: Gpclr, + gpchr: Gpchr, + _reserved3: [u8; 0x08], + config: Config, + _reserved4: [u8; 0x3c], + calib0: Calib0, + calib1: Calib1, + _reserved6: [u8; 0x18], + pcr0: Pcr0, + pcr1: Pcr1, + pcr2: Pcr2, + pcr3: Pcr3, + pcr4: Pcr4, + pcr5: Pcr5, + pcr6: Pcr6, + pcr7: Pcr7, + pcr8: Pcr8, + pcr9: Pcr9, + pcr10: Pcr10, + pcr11: Pcr11, + pcr12: Pcr12, + pcr13: Pcr13, + pcr14: Pcr14, + pcr15: Pcr15, + pcr16: Pcr16, + pcr17: Pcr17, + pcr18: Pcr18, + pcr19: Pcr19, + pcr20: Pcr20, + pcr21: Pcr21, + pcr22: Pcr22, + pcr23: Pcr23, + pcr24: Pcr24, + pcr25: Pcr25, + pcr26: Pcr26, + pcr27: Pcr27, + pcr28: Pcr28, + pcr29: Pcr29, + pcr30: Pcr30, + pcr31: Pcr31, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x10 - Global Pin Control Low"] + #[inline(always)] + pub const fn gpclr(&self) -> &Gpclr { + &self.gpclr + } + #[doc = "0x14 - Global Pin Control High"] + #[inline(always)] + pub const fn gpchr(&self) -> &Gpchr { + &self.gpchr + } + #[doc = "0x20 - Configuration"] + #[inline(always)] + pub const fn config(&self) -> &Config { + &self.config + } + #[doc = "0x60 - Calibration 0"] + #[inline(always)] + pub const fn calib0(&self) -> &Calib0 { + &self.calib0 + } + #[doc = "0x64 - Calibration 1"] + #[inline(always)] + pub const fn calib1(&self) -> &Calib1 { + &self.calib1 + } + #[doc = "0x80 - Pin Control 0"] + #[inline(always)] + pub const fn pcr0(&self) -> &Pcr0 { + &self.pcr0 + } + #[doc = "0x84 - Pin Control 1"] + #[inline(always)] + pub const fn pcr1(&self) -> &Pcr1 { + &self.pcr1 + } + #[doc = "0x88 - Pin Control 2"] + #[inline(always)] + pub const fn pcr2(&self) -> &Pcr2 { + &self.pcr2 + } + #[doc = "0x8c - Pin Control 3"] + #[inline(always)] + pub const fn pcr3(&self) -> &Pcr3 { + &self.pcr3 + } + #[doc = "0x90 - Pin Control 4"] + #[inline(always)] + pub const fn pcr4(&self) -> &Pcr4 { + &self.pcr4 + } + #[doc = "0x94 - Pin Control 5"] + #[inline(always)] + pub const fn pcr5(&self) -> &Pcr5 { + &self.pcr5 + } + #[doc = "0x98 - Pin Control 6"] + #[inline(always)] + pub const fn pcr6(&self) -> &Pcr6 { + &self.pcr6 + } + #[doc = "0x9c - Pin Control 7"] + #[inline(always)] + pub const fn pcr7(&self) -> &Pcr7 { + &self.pcr7 + } + #[doc = "0xa0 - Pin Control 8"] + #[inline(always)] + pub const fn pcr8(&self) -> &Pcr8 { + &self.pcr8 + } + #[doc = "0xa4 - Pin Control 9"] + #[inline(always)] + pub const fn pcr9(&self) -> &Pcr9 { + &self.pcr9 + } + #[doc = "0xa8 - Pin Control 10"] + #[inline(always)] + pub const fn pcr10(&self) -> &Pcr10 { + &self.pcr10 + } + #[doc = "0xac - Pin Control 11"] + #[inline(always)] + pub const fn pcr11(&self) -> &Pcr11 { + &self.pcr11 + } + #[doc = "0xb0 - Pin Control 12"] + #[inline(always)] + pub const fn pcr12(&self) -> &Pcr12 { + &self.pcr12 + } + #[doc = "0xb4 - Pin Control 13"] + #[inline(always)] + pub const fn pcr13(&self) -> &Pcr13 { + &self.pcr13 + } + #[doc = "0xb8 - Pin Control 14"] + #[inline(always)] + pub const fn pcr14(&self) -> &Pcr14 { + &self.pcr14 + } + #[doc = "0xbc - Pin Control 15"] + #[inline(always)] + pub const fn pcr15(&self) -> &Pcr15 { + &self.pcr15 + } + #[doc = "0xc0 - Pin Control 16"] + #[inline(always)] + pub const fn pcr16(&self) -> &Pcr16 { + &self.pcr16 + } + #[doc = "0xc4 - Pin Control 17"] + #[inline(always)] + pub const fn pcr17(&self) -> &Pcr17 { + &self.pcr17 + } + #[doc = "0xc8 - Pin Control 18"] + #[inline(always)] + pub const fn pcr18(&self) -> &Pcr18 { + &self.pcr18 + } + #[doc = "0xcc - Pin Control 19"] + #[inline(always)] + pub const fn pcr19(&self) -> &Pcr19 { + &self.pcr19 + } + #[doc = "0xd0 - Pin Control 20"] + #[inline(always)] + pub const fn pcr20(&self) -> &Pcr20 { + &self.pcr20 + } + #[doc = "0xd4 - Pin Control 21"] + #[inline(always)] + pub const fn pcr21(&self) -> &Pcr21 { + &self.pcr21 + } + #[doc = "0xd8 - Pin Control 22"] + #[inline(always)] + pub const fn pcr22(&self) -> &Pcr22 { + &self.pcr22 + } + #[doc = "0xdc - Pin Control 23"] + #[inline(always)] + pub const fn pcr23(&self) -> &Pcr23 { + &self.pcr23 + } + #[doc = "0xe0 - Pin Control 24"] + #[inline(always)] + pub const fn pcr24(&self) -> &Pcr24 { + &self.pcr24 + } + #[doc = "0xe4 - Pin Control 25"] + #[inline(always)] + pub const fn pcr25(&self) -> &Pcr25 { + &self.pcr25 + } + #[doc = "0xe8 - Pin Control 26"] + #[inline(always)] + pub const fn pcr26(&self) -> &Pcr26 { + &self.pcr26 + } + #[doc = "0xec - Pin Control 27"] + #[inline(always)] + pub const fn pcr27(&self) -> &Pcr27 { + &self.pcr27 + } + #[doc = "0xf0 - Pin Control 28"] + #[inline(always)] + pub const fn pcr28(&self) -> &Pcr28 { + &self.pcr28 + } + #[doc = "0xf4 - Pin Control 29"] + #[inline(always)] + pub const fn pcr29(&self) -> &Pcr29 { + &self.pcr29 + } + #[doc = "0xf8 - Pin Control 30"] + #[inline(always)] + pub const fn pcr30(&self) -> &Pcr30 { + &self.pcr30 + } + #[doc = "0xfc - Pin Control 31"] + #[inline(always)] + pub const fn pcr31(&self) -> &Pcr31 { + &self.pcr31 + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] +#[doc(alias = "GPCLR")] +pub type Gpclr = crate::Reg; +#[doc = "Global Pin Control Low"] +pub mod gpclr; +#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] +#[doc(alias = "GPCHR")] +pub type Gpchr = crate::Reg; +#[doc = "Global Pin Control High"] +pub mod gpchr; +#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +#[doc(alias = "CONFIG")] +pub type Config = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] +#[doc(alias = "CALIB0")] +pub type Calib0 = crate::Reg; +#[doc = "Calibration 0"] +pub mod calib0; +#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] +#[doc(alias = "CALIB1")] +pub type Calib1 = crate::Reg; +#[doc = "Calibration 1"] +pub mod calib1; +#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] +#[doc(alias = "PCR0")] +pub type Pcr0 = crate::Reg; +#[doc = "Pin Control 0"] +pub mod pcr0; +#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] +#[doc(alias = "PCR1")] +pub type Pcr1 = crate::Reg; +#[doc = "Pin Control 1"] +pub mod pcr1; +#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] +#[doc(alias = "PCR2")] +pub type Pcr2 = crate::Reg; +#[doc = "Pin Control 2"] +pub mod pcr2; +#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] +#[doc(alias = "PCR3")] +pub type Pcr3 = crate::Reg; +#[doc = "Pin Control 3"] +pub mod pcr3; +#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] +#[doc(alias = "PCR4")] +pub type Pcr4 = crate::Reg; +#[doc = "Pin Control 4"] +pub mod pcr4; +#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] +#[doc(alias = "PCR5")] +pub type Pcr5 = crate::Reg; +#[doc = "Pin Control 5"] +pub mod pcr5; +#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] +#[doc(alias = "PCR6")] +pub type Pcr6 = crate::Reg; +#[doc = "Pin Control 6"] +pub mod pcr6; +#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] +#[doc(alias = "PCR7")] +pub type Pcr7 = crate::Reg; +#[doc = "Pin Control 7"] +pub mod pcr7; +#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] +#[doc(alias = "PCR8")] +pub type Pcr8 = crate::Reg; +#[doc = "Pin Control 8"] +pub mod pcr8; +#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] +#[doc(alias = "PCR9")] +pub type Pcr9 = crate::Reg; +#[doc = "Pin Control 9"] +pub mod pcr9; +#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] +#[doc(alias = "PCR10")] +pub type Pcr10 = crate::Reg; +#[doc = "Pin Control 10"] +pub mod pcr10; +#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] +#[doc(alias = "PCR11")] +pub type Pcr11 = crate::Reg; +#[doc = "Pin Control 11"] +pub mod pcr11; +#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] +#[doc(alias = "PCR12")] +pub type Pcr12 = crate::Reg; +#[doc = "Pin Control 12"] +pub mod pcr12; +#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] +#[doc(alias = "PCR13")] +pub type Pcr13 = crate::Reg; +#[doc = "Pin Control 13"] +pub mod pcr13; +#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] +#[doc(alias = "PCR14")] +pub type Pcr14 = crate::Reg; +#[doc = "Pin Control 14"] +pub mod pcr14; +#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] +#[doc(alias = "PCR15")] +pub type Pcr15 = crate::Reg; +#[doc = "Pin Control 15"] +pub mod pcr15; +#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] +#[doc(alias = "PCR16")] +pub type Pcr16 = crate::Reg; +#[doc = "Pin Control 16"] +pub mod pcr16; +#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] +#[doc(alias = "PCR17")] +pub type Pcr17 = crate::Reg; +#[doc = "Pin Control 17"] +pub mod pcr17; +#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] +#[doc(alias = "PCR18")] +pub type Pcr18 = crate::Reg; +#[doc = "Pin Control 18"] +pub mod pcr18; +#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] +#[doc(alias = "PCR19")] +pub type Pcr19 = crate::Reg; +#[doc = "Pin Control 19"] +pub mod pcr19; +#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] +#[doc(alias = "PCR20")] +pub type Pcr20 = crate::Reg; +#[doc = "Pin Control 20"] +pub mod pcr20; +#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] +#[doc(alias = "PCR21")] +pub type Pcr21 = crate::Reg; +#[doc = "Pin Control 21"] +pub mod pcr21; +#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] +#[doc(alias = "PCR22")] +pub type Pcr22 = crate::Reg; +#[doc = "Pin Control 22"] +pub mod pcr22; +#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] +#[doc(alias = "PCR23")] +pub type Pcr23 = crate::Reg; +#[doc = "Pin Control 23"] +pub mod pcr23; +#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] +#[doc(alias = "PCR24")] +pub type Pcr24 = crate::Reg; +#[doc = "Pin Control 24"] +pub mod pcr24; +#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] +#[doc(alias = "PCR25")] +pub type Pcr25 = crate::Reg; +#[doc = "Pin Control 25"] +pub mod pcr25; +#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] +#[doc(alias = "PCR26")] +pub type Pcr26 = crate::Reg; +#[doc = "Pin Control 26"] +pub mod pcr26; +#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] +#[doc(alias = "PCR27")] +pub type Pcr27 = crate::Reg; +#[doc = "Pin Control 27"] +pub mod pcr27; +#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] +#[doc(alias = "PCR28")] +pub type Pcr28 = crate::Reg; +#[doc = "Pin Control 28"] +pub mod pcr28; +#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] +#[doc(alias = "PCR29")] +pub type Pcr29 = crate::Reg; +#[doc = "Pin Control 29"] +pub mod pcr29; +#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] +#[doc(alias = "PCR30")] +pub type Pcr30 = crate::Reg; +#[doc = "Pin Control 30"] +pub mod pcr30; +#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] +#[doc(alias = "PCR31")] +pub type Pcr31 = crate::Reg; +#[doc = "Pin Control 31"] +pub mod pcr31; diff --git a/mcxa276-pac/src/port3/calib0.rs b/mcxa276-pac/src/port3/calib0.rs new file mode 100644 index 000000000..029fa12f3 --- /dev/null +++ b/mcxa276-pac/src/port3/calib0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB0` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB0` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib0Spec; +impl crate::RegisterSpec for Calib0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] +impl crate::Readable for Calib0Spec {} +#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] +impl crate::Writable for Calib0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB0 to value 0"] +impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port3/calib1.rs b/mcxa276-pac/src/port3/calib1.rs new file mode 100644 index 000000000..e18f61234 --- /dev/null +++ b/mcxa276-pac/src/port3/calib1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB1` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB1` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib1Spec; +impl crate::RegisterSpec for Calib1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] +impl crate::Readable for Calib1Spec {} +#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] +impl crate::Writable for Calib1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB1 to value 0"] +impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port3/config.rs b/mcxa276-pac/src/port3/config.rs new file mode 100644 index 000000000..da92c5b27 --- /dev/null +++ b/mcxa276-pac/src/port3/config.rs @@ -0,0 +1,84 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Port Voltage Range\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Range { + #[doc = "0: 1.71 V-3.6 V"] + Range0 = 0, + #[doc = "1: 2.70 V-3.6 V"] + Range1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Range) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RANGE` reader - Port Voltage Range"] +pub type RangeR = crate::BitReader; +impl RangeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Range { + match self.bits { + false => Range::Range0, + true => Range::Range1, + } + } + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn is_range0(&self) -> bool { + *self == Range::Range0 + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn is_range1(&self) -> bool { + *self == Range::Range1 + } +} +#[doc = "Field `RANGE` writer - Port Voltage Range"] +pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; +impl<'a, REG> RangeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn range0(self) -> &'a mut crate::W { + self.variant(Range::Range0) + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn range1(self) -> &'a mut crate::W { + self.variant(Range::Range1) + } +} +impl R { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&self) -> RangeR { + RangeR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&mut self) -> RangeW { + RangeW::new(self, 0) + } +} +#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConfigSpec; +impl crate::RegisterSpec for ConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for ConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for ConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port3/gpchr.rs b/mcxa276-pac/src/port3/gpchr.rs new file mode 100644 index 000000000..af92d0d62 --- /dev/null +++ b/mcxa276-pac/src/port3/gpchr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCHR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCHR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe16 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] +pub type Gpwe16R = crate::BitReader; +impl Gpwe16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe16 { + match self.bits { + false => Gpwe16::Gpwe0, + true => Gpwe16::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe16::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe16::Gpwe1 + } +} +#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] +pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; +impl<'a, REG> Gpwe16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe17 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] +pub type Gpwe17R = crate::BitReader; +impl Gpwe17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe17 { + match self.bits { + false => Gpwe17::Gpwe0, + true => Gpwe17::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe17::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe17::Gpwe1 + } +} +#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] +pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; +impl<'a, REG> Gpwe17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe18 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] +pub type Gpwe18R = crate::BitReader; +impl Gpwe18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe18 { + match self.bits { + false => Gpwe18::Gpwe0, + true => Gpwe18::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe18::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe18::Gpwe1 + } +} +#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] +pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; +impl<'a, REG> Gpwe18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe19 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] +pub type Gpwe19R = crate::BitReader; +impl Gpwe19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe19 { + match self.bits { + false => Gpwe19::Gpwe0, + true => Gpwe19::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe19::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe19::Gpwe1 + } +} +#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] +pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; +impl<'a, REG> Gpwe19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe20 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] +pub type Gpwe20R = crate::BitReader; +impl Gpwe20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe20 { + match self.bits { + false => Gpwe20::Gpwe0, + true => Gpwe20::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe20::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe20::Gpwe1 + } +} +#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] +pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; +impl<'a, REG> Gpwe20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe21 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] +pub type Gpwe21R = crate::BitReader; +impl Gpwe21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe21 { + match self.bits { + false => Gpwe21::Gpwe0, + true => Gpwe21::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe21::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe21::Gpwe1 + } +} +#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] +pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; +impl<'a, REG> Gpwe21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe22 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] +pub type Gpwe22R = crate::BitReader; +impl Gpwe22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe22 { + match self.bits { + false => Gpwe22::Gpwe0, + true => Gpwe22::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe22::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe22::Gpwe1 + } +} +#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] +pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; +impl<'a, REG> Gpwe22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe23 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] +pub type Gpwe23R = crate::BitReader; +impl Gpwe23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe23 { + match self.bits { + false => Gpwe23::Gpwe0, + true => Gpwe23::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe23::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe23::Gpwe1 + } +} +#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] +pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; +impl<'a, REG> Gpwe23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe24 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] +pub type Gpwe24R = crate::BitReader; +impl Gpwe24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe24 { + match self.bits { + false => Gpwe24::Gpwe0, + true => Gpwe24::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe24::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe24::Gpwe1 + } +} +#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] +pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; +impl<'a, REG> Gpwe24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe25 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] +pub type Gpwe25R = crate::BitReader; +impl Gpwe25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe25 { + match self.bits { + false => Gpwe25::Gpwe0, + true => Gpwe25::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe25::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe25::Gpwe1 + } +} +#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] +pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; +impl<'a, REG> Gpwe25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe26 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] +pub type Gpwe26R = crate::BitReader; +impl Gpwe26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe26 { + match self.bits { + false => Gpwe26::Gpwe0, + true => Gpwe26::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe26::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe26::Gpwe1 + } +} +#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] +pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; +impl<'a, REG> Gpwe26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe27 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] +pub type Gpwe27R = crate::BitReader; +impl Gpwe27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe27 { + match self.bits { + false => Gpwe27::Gpwe0, + true => Gpwe27::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe27::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe27::Gpwe1 + } +} +#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] +pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; +impl<'a, REG> Gpwe27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe28 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] +pub type Gpwe28R = crate::BitReader; +impl Gpwe28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe28 { + match self.bits { + false => Gpwe28::Gpwe0, + true => Gpwe28::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe28::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe28::Gpwe1 + } +} +#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] +pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; +impl<'a, REG> Gpwe28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe29 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] +pub type Gpwe29R = crate::BitReader; +impl Gpwe29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe29 { + match self.bits { + false => Gpwe29::Gpwe0, + true => Gpwe29::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe29::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe29::Gpwe1 + } +} +#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] +pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; +impl<'a, REG> Gpwe29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe30 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] +pub type Gpwe30R = crate::BitReader; +impl Gpwe30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe30 { + match self.bits { + false => Gpwe30::Gpwe0, + true => Gpwe30::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe30::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe30::Gpwe1 + } +} +#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] +pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; +impl<'a, REG> Gpwe30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe31 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] +pub type Gpwe31R = crate::BitReader; +impl Gpwe31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe31 { + match self.bits { + false => Gpwe31::Gpwe0, + true => Gpwe31::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe31::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe31::Gpwe1 + } +} +#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] +pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; +impl<'a, REG> Gpwe31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&self) -> Gpwe16R { + Gpwe16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&self) -> Gpwe17R { + Gpwe17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&self) -> Gpwe18R { + Gpwe18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&self) -> Gpwe19R { + Gpwe19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&self) -> Gpwe20R { + Gpwe20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&self) -> Gpwe21R { + Gpwe21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&self) -> Gpwe22R { + Gpwe22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&self) -> Gpwe23R { + Gpwe23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&self) -> Gpwe24R { + Gpwe24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&self) -> Gpwe25R { + Gpwe25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&self) -> Gpwe26R { + Gpwe26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&self) -> Gpwe27R { + Gpwe27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&self) -> Gpwe28R { + Gpwe28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&self) -> Gpwe29R { + Gpwe29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&self) -> Gpwe30R { + Gpwe30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&self) -> Gpwe31R { + Gpwe31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&mut self) -> Gpwe16W { + Gpwe16W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&mut self) -> Gpwe17W { + Gpwe17W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&mut self) -> Gpwe18W { + Gpwe18W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&mut self) -> Gpwe19W { + Gpwe19W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&mut self) -> Gpwe20W { + Gpwe20W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&mut self) -> Gpwe21W { + Gpwe21W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&mut self) -> Gpwe22W { + Gpwe22W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&mut self) -> Gpwe23W { + Gpwe23W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&mut self) -> Gpwe24W { + Gpwe24W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&mut self) -> Gpwe25W { + Gpwe25W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&mut self) -> Gpwe26W { + Gpwe26W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&mut self) -> Gpwe27W { + Gpwe27W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&mut self) -> Gpwe28W { + Gpwe28W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&mut self) -> Gpwe29W { + Gpwe29W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&mut self) -> Gpwe30W { + Gpwe30W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&mut self) -> Gpwe31W { + Gpwe31W::new(self, 31) + } +} +#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpchrSpec; +impl crate::RegisterSpec for GpchrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] +impl crate::Readable for GpchrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] +impl crate::Writable for GpchrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCHR to value 0"] +impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port3/gpclr.rs b/mcxa276-pac/src/port3/gpclr.rs new file mode 100644 index 000000000..21e5ff23d --- /dev/null +++ b/mcxa276-pac/src/port3/gpclr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe0 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] +pub type Gpwe0R = crate::BitReader; +impl Gpwe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe0 { + match self.bits { + false => Gpwe0::Gpwe0, + true => Gpwe0::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe0::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe0::Gpwe1 + } +} +#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] +pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; +impl<'a, REG> Gpwe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe1 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] +pub type Gpwe1R = crate::BitReader; +impl Gpwe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe1 { + match self.bits { + false => Gpwe1::Gpwe0, + true => Gpwe1::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe1::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe1::Gpwe1 + } +} +#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] +pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; +impl<'a, REG> Gpwe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe2 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] +pub type Gpwe2R = crate::BitReader; +impl Gpwe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe2 { + match self.bits { + false => Gpwe2::Gpwe0, + true => Gpwe2::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe2::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe2::Gpwe1 + } +} +#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] +pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; +impl<'a, REG> Gpwe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe3 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] +pub type Gpwe3R = crate::BitReader; +impl Gpwe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe3 { + match self.bits { + false => Gpwe3::Gpwe0, + true => Gpwe3::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe3::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe3::Gpwe1 + } +} +#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] +pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; +impl<'a, REG> Gpwe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe4 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] +pub type Gpwe4R = crate::BitReader; +impl Gpwe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe4 { + match self.bits { + false => Gpwe4::Gpwe0, + true => Gpwe4::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe4::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe4::Gpwe1 + } +} +#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] +pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; +impl<'a, REG> Gpwe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe5 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] +pub type Gpwe5R = crate::BitReader; +impl Gpwe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe5 { + match self.bits { + false => Gpwe5::Gpwe0, + true => Gpwe5::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe5::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe5::Gpwe1 + } +} +#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] +pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; +impl<'a, REG> Gpwe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe6 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] +pub type Gpwe6R = crate::BitReader; +impl Gpwe6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe6 { + match self.bits { + false => Gpwe6::Gpwe0, + true => Gpwe6::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe6::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe6::Gpwe1 + } +} +#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] +pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; +impl<'a, REG> Gpwe6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe7 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] +pub type Gpwe7R = crate::BitReader; +impl Gpwe7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe7 { + match self.bits { + false => Gpwe7::Gpwe0, + true => Gpwe7::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe7::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe7::Gpwe1 + } +} +#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] +pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; +impl<'a, REG> Gpwe7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe8 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] +pub type Gpwe8R = crate::BitReader; +impl Gpwe8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe8 { + match self.bits { + false => Gpwe8::Gpwe0, + true => Gpwe8::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe8::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe8::Gpwe1 + } +} +#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] +pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; +impl<'a, REG> Gpwe8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe9 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] +pub type Gpwe9R = crate::BitReader; +impl Gpwe9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe9 { + match self.bits { + false => Gpwe9::Gpwe0, + true => Gpwe9::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe9::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe9::Gpwe1 + } +} +#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] +pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; +impl<'a, REG> Gpwe9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe10 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] +pub type Gpwe10R = crate::BitReader; +impl Gpwe10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe10 { + match self.bits { + false => Gpwe10::Gpwe0, + true => Gpwe10::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe10::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe10::Gpwe1 + } +} +#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] +pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; +impl<'a, REG> Gpwe10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe11 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] +pub type Gpwe11R = crate::BitReader; +impl Gpwe11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe11 { + match self.bits { + false => Gpwe11::Gpwe0, + true => Gpwe11::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe11::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe11::Gpwe1 + } +} +#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] +pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; +impl<'a, REG> Gpwe11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe12 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] +pub type Gpwe12R = crate::BitReader; +impl Gpwe12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe12 { + match self.bits { + false => Gpwe12::Gpwe0, + true => Gpwe12::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe12::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe12::Gpwe1 + } +} +#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] +pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; +impl<'a, REG> Gpwe12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe13 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] +pub type Gpwe13R = crate::BitReader; +impl Gpwe13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe13 { + match self.bits { + false => Gpwe13::Gpwe0, + true => Gpwe13::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe13::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe13::Gpwe1 + } +} +#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] +pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; +impl<'a, REG> Gpwe13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe14 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] +pub type Gpwe14R = crate::BitReader; +impl Gpwe14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe14 { + match self.bits { + false => Gpwe14::Gpwe0, + true => Gpwe14::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe14::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe14::Gpwe1 + } +} +#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] +pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; +impl<'a, REG> Gpwe14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe15 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] +pub type Gpwe15R = crate::BitReader; +impl Gpwe15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe15 { + match self.bits { + false => Gpwe15::Gpwe0, + true => Gpwe15::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe15::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe15::Gpwe1 + } +} +#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] +pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; +impl<'a, REG> Gpwe15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&self) -> Gpwe0R { + Gpwe0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&self) -> Gpwe1R { + Gpwe1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&self) -> Gpwe2R { + Gpwe2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&self) -> Gpwe3R { + Gpwe3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&self) -> Gpwe4R { + Gpwe4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&self) -> Gpwe5R { + Gpwe5R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&self) -> Gpwe6R { + Gpwe6R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&self) -> Gpwe7R { + Gpwe7R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&self) -> Gpwe8R { + Gpwe8R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&self) -> Gpwe9R { + Gpwe9R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&self) -> Gpwe10R { + Gpwe10R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&self) -> Gpwe11R { + Gpwe11R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&self) -> Gpwe12R { + Gpwe12R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&self) -> Gpwe13R { + Gpwe13R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&self) -> Gpwe14R { + Gpwe14R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&self) -> Gpwe15R { + Gpwe15R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&mut self) -> Gpwe0W { + Gpwe0W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&mut self) -> Gpwe1W { + Gpwe1W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&mut self) -> Gpwe2W { + Gpwe2W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&mut self) -> Gpwe3W { + Gpwe3W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&mut self) -> Gpwe4W { + Gpwe4W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&mut self) -> Gpwe5W { + Gpwe5W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&mut self) -> Gpwe6W { + Gpwe6W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&mut self) -> Gpwe7W { + Gpwe7W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&mut self) -> Gpwe8W { + Gpwe8W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&mut self) -> Gpwe9W { + Gpwe9W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&mut self) -> Gpwe10W { + Gpwe10W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&mut self) -> Gpwe11W { + Gpwe11W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&mut self) -> Gpwe12W { + Gpwe12W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&mut self) -> Gpwe13W { + Gpwe13W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&mut self) -> Gpwe14W { + Gpwe14W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&mut self) -> Gpwe15W { + Gpwe15W::new(self, 31) + } +} +#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpclrSpec; +impl crate::RegisterSpec for GpclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] +impl crate::Readable for GpclrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] +impl crate::Writable for GpclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCLR to value 0"] +impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port3/pcr0.rs b/mcxa276-pac/src/port3/pcr0.rs new file mode 100644 index 000000000..d2e60dc8d --- /dev/null +++ b/mcxa276-pac/src/port3/pcr0.rs @@ -0,0 +1,877 @@ +#[doc = "Register `PCR0` reader"] +pub type R = crate::R; +#[doc = "Register `PCR0` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr0Spec; +impl crate::RegisterSpec for Pcr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] +impl crate::Readable for Pcr0Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] +impl crate::Writable for Pcr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR0 to value 0"] +impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port3/pcr1.rs b/mcxa276-pac/src/port3/pcr1.rs new file mode 100644 index 000000000..73aa72974 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr1.rs @@ -0,0 +1,877 @@ +#[doc = "Register `PCR1` reader"] +pub type R = crate::R; +#[doc = "Register `PCR1` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Passive Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pfe { + #[doc = "0: Disables"] + Pfe0 = 0, + #[doc = "1: Enables"] + Pfe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PFE` reader - Passive Filter Enable"] +pub type PfeR = crate::BitReader; +impl PfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pfe { + match self.bits { + false => Pfe::Pfe0, + true => Pfe::Pfe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pfe0(&self) -> bool { + *self == Pfe::Pfe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pfe1(&self) -> bool { + *self == Pfe::Pfe1 + } +} +#[doc = "Field `PFE` writer - Passive Filter Enable"] +pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; +impl<'a, REG> PfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pfe0(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pfe1(self) -> &'a mut crate::W { + self.variant(Pfe::Pfe1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&self) -> PfeR { + PfeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 4 - Passive Filter Enable"] + #[inline(always)] + pub fn pfe(&mut self) -> PfeW { + PfeW::new(self, 4) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr1Spec; +impl crate::RegisterSpec for Pcr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] +impl crate::Readable for Pcr1Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] +impl crate::Writable for Pcr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR1 to value 0"] +impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port3/pcr10.rs b/mcxa276-pac/src/port3/pcr10.rs new file mode 100644 index 000000000..e5317eb0c --- /dev/null +++ b/mcxa276-pac/src/port3/pcr10.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR10` reader"] +pub type R = crate::R; +#[doc = "Register `PCR10` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr10Spec; +impl crate::RegisterSpec for Pcr10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] +impl crate::Readable for Pcr10Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] +impl crate::Writable for Pcr10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR10 to value 0"] +impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port3/pcr11.rs b/mcxa276-pac/src/port3/pcr11.rs new file mode 100644 index 000000000..bc47cbd2b --- /dev/null +++ b/mcxa276-pac/src/port3/pcr11.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR11` reader"] +pub type R = crate::R; +#[doc = "Register `PCR11` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr11Spec; +impl crate::RegisterSpec for Pcr11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] +impl crate::Readable for Pcr11Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] +impl crate::Writable for Pcr11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR11 to value 0"] +impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port3/pcr12.rs b/mcxa276-pac/src/port3/pcr12.rs new file mode 100644 index 000000000..2cd7eecc1 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr12.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR12` reader"] +pub type R = crate::R; +#[doc = "Register `PCR12` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr12Spec; +impl crate::RegisterSpec for Pcr12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] +impl crate::Readable for Pcr12Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] +impl crate::Writable for Pcr12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR12 to value 0"] +impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port3/pcr13.rs b/mcxa276-pac/src/port3/pcr13.rs new file mode 100644 index 000000000..0da9c8d55 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr13.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR13` reader"] +pub type R = crate::R; +#[doc = "Register `PCR13` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr13Spec; +impl crate::RegisterSpec for Pcr13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] +impl crate::Readable for Pcr13Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] +impl crate::Writable for Pcr13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR13 to value 0"] +impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port3/pcr14.rs b/mcxa276-pac/src/port3/pcr14.rs new file mode 100644 index 000000000..553559b3f --- /dev/null +++ b/mcxa276-pac/src/port3/pcr14.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR14` reader"] +pub type R = crate::R; +#[doc = "Register `PCR14` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr14Spec; +impl crate::RegisterSpec for Pcr14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] +impl crate::Readable for Pcr14Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] +impl crate::Writable for Pcr14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR14 to value 0"] +impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port3/pcr15.rs b/mcxa276-pac/src/port3/pcr15.rs new file mode 100644 index 000000000..85c188f6b --- /dev/null +++ b/mcxa276-pac/src/port3/pcr15.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR15` reader"] +pub type R = crate::R; +#[doc = "Register `PCR15` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr15Spec; +impl crate::RegisterSpec for Pcr15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] +impl crate::Readable for Pcr15Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] +impl crate::Writable for Pcr15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR15 to value 0"] +impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port3/pcr16.rs b/mcxa276-pac/src/port3/pcr16.rs new file mode 100644 index 000000000..70c9dda78 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr16.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR16` reader"] +pub type R = crate::R; +#[doc = "Register `PCR16` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr16Spec; +impl crate::RegisterSpec for Pcr16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] +impl crate::Readable for Pcr16Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] +impl crate::Writable for Pcr16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR16 to value 0"] +impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port3/pcr17.rs b/mcxa276-pac/src/port3/pcr17.rs new file mode 100644 index 000000000..2faf3487b --- /dev/null +++ b/mcxa276-pac/src/port3/pcr17.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR17` reader"] +pub type R = crate::R; +#[doc = "Register `PCR17` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr17Spec; +impl crate::RegisterSpec for Pcr17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] +impl crate::Readable for Pcr17Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] +impl crate::Writable for Pcr17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR17 to value 0"] +impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port3/pcr18.rs b/mcxa276-pac/src/port3/pcr18.rs new file mode 100644 index 000000000..796f9eede --- /dev/null +++ b/mcxa276-pac/src/port3/pcr18.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR18` reader"] +pub type R = crate::R; +#[doc = "Register `PCR18` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr18Spec; +impl crate::RegisterSpec for Pcr18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] +impl crate::Readable for Pcr18Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] +impl crate::Writable for Pcr18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR18 to value 0"] +impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port3/pcr19.rs b/mcxa276-pac/src/port3/pcr19.rs new file mode 100644 index 000000000..7b5da5c24 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr19.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR19` reader"] +pub type R = crate::R; +#[doc = "Register `PCR19` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr19Spec; +impl crate::RegisterSpec for Pcr19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] +impl crate::Readable for Pcr19Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] +impl crate::Writable for Pcr19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR19 to value 0"] +impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port3/pcr2.rs b/mcxa276-pac/src/port3/pcr2.rs new file mode 100644 index 000000000..09359160e --- /dev/null +++ b/mcxa276-pac/src/port3/pcr2.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR2` reader"] +pub type R = crate::R; +#[doc = "Register `PCR2` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr2Spec; +impl crate::RegisterSpec for Pcr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] +impl crate::Readable for Pcr2Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] +impl crate::Writable for Pcr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR2 to value 0"] +impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port3/pcr20.rs b/mcxa276-pac/src/port3/pcr20.rs new file mode 100644 index 000000000..20401202b --- /dev/null +++ b/mcxa276-pac/src/port3/pcr20.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR20` reader"] +pub type R = crate::R; +#[doc = "Register `PCR20` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr20Spec; +impl crate::RegisterSpec for Pcr20Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] +impl crate::Readable for Pcr20Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] +impl crate::Writable for Pcr20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR20 to value 0"] +impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port3/pcr21.rs b/mcxa276-pac/src/port3/pcr21.rs new file mode 100644 index 000000000..9f6076615 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr21.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR21` reader"] +pub type R = crate::R; +#[doc = "Register `PCR21` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr21Spec; +impl crate::RegisterSpec for Pcr21Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] +impl crate::Readable for Pcr21Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] +impl crate::Writable for Pcr21Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR21 to value 0"] +impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port3/pcr22.rs b/mcxa276-pac/src/port3/pcr22.rs new file mode 100644 index 000000000..decbc02c0 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr22.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR22` reader"] +pub type R = crate::R; +#[doc = "Register `PCR22` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr22Spec; +impl crate::RegisterSpec for Pcr22Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] +impl crate::Readable for Pcr22Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] +impl crate::Writable for Pcr22Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR22 to value 0"] +impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port3/pcr23.rs b/mcxa276-pac/src/port3/pcr23.rs new file mode 100644 index 000000000..640773d73 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr23.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR23` reader"] +pub type R = crate::R; +#[doc = "Register `PCR23` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr23Spec; +impl crate::RegisterSpec for Pcr23Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] +impl crate::Readable for Pcr23Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] +impl crate::Writable for Pcr23Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR23 to value 0"] +impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port3/pcr24.rs b/mcxa276-pac/src/port3/pcr24.rs new file mode 100644 index 000000000..fe34d2b88 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr24.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR24` reader"] +pub type R = crate::R; +#[doc = "Register `PCR24` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr24Spec; +impl crate::RegisterSpec for Pcr24Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] +impl crate::Readable for Pcr24Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] +impl crate::Writable for Pcr24Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR24 to value 0"] +impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port3/pcr25.rs b/mcxa276-pac/src/port3/pcr25.rs new file mode 100644 index 000000000..bf5b458bd --- /dev/null +++ b/mcxa276-pac/src/port3/pcr25.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR25` reader"] +pub type R = crate::R; +#[doc = "Register `PCR25` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr25Spec; +impl crate::RegisterSpec for Pcr25Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] +impl crate::Readable for Pcr25Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] +impl crate::Writable for Pcr25Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR25 to value 0"] +impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port3/pcr26.rs b/mcxa276-pac/src/port3/pcr26.rs new file mode 100644 index 000000000..cb9fb6d2b --- /dev/null +++ b/mcxa276-pac/src/port3/pcr26.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR26` reader"] +pub type R = crate::R; +#[doc = "Register `PCR26` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr26Spec; +impl crate::RegisterSpec for Pcr26Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] +impl crate::Readable for Pcr26Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] +impl crate::Writable for Pcr26Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR26 to value 0"] +impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port3/pcr27.rs b/mcxa276-pac/src/port3/pcr27.rs new file mode 100644 index 000000000..69b0c629a --- /dev/null +++ b/mcxa276-pac/src/port3/pcr27.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR27` reader"] +pub type R = crate::R; +#[doc = "Register `PCR27` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr27Spec; +impl crate::RegisterSpec for Pcr27Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] +impl crate::Readable for Pcr27Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] +impl crate::Writable for Pcr27Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR27 to value 0"] +impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port3/pcr28.rs b/mcxa276-pac/src/port3/pcr28.rs new file mode 100644 index 000000000..313d32bb7 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr28.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR28` reader"] +pub type R = crate::R; +#[doc = "Register `PCR28` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse1 { + #[doc = "0: Normal"] + Dse10 = 0, + #[doc = "1: Double"] + Dse11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE1` reader - Drive Strength Enable"] +pub type Dse1R = crate::BitReader; +impl Dse1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse1 { + match self.bits { + false => Dse1::Dse10, + true => Dse1::Dse11, + } + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_dse10(&self) -> bool { + *self == Dse1::Dse10 + } + #[doc = "Double"] + #[inline(always)] + pub fn is_dse11(&self) -> bool { + *self == Dse1::Dse11 + } +} +#[doc = "Field `DSE1` writer - Drive Strength Enable"] +pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; +impl<'a, REG> Dse1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal"] + #[inline(always)] + pub fn dse10(self) -> &'a mut crate::W { + self.variant(Dse1::Dse10) + } + #[doc = "Double"] + #[inline(always)] + pub fn dse11(self) -> &'a mut crate::W { + self.variant(Dse1::Dse11) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&self) -> Dse1R { + Dse1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 7 - Drive Strength Enable"] + #[inline(always)] + pub fn dse1(&mut self) -> Dse1W { + Dse1W::new(self, 7) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr28Spec; +impl crate::RegisterSpec for Pcr28Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] +impl crate::Readable for Pcr28Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] +impl crate::Writable for Pcr28Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR28 to value 0"] +impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port3/pcr29.rs b/mcxa276-pac/src/port3/pcr29.rs new file mode 100644 index 000000000..7c1f7f594 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr29.rs @@ -0,0 +1,816 @@ +#[doc = "Register `PCR29` reader"] +pub type R = crate::R; +#[doc = "Register `PCR29` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr29Spec; +impl crate::RegisterSpec for Pcr29Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] +impl crate::Readable for Pcr29Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] +impl crate::Writable for Pcr29Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR29 to value 0x1103"] +impl crate::Resettable for Pcr29Spec { + const RESET_VALUE: u32 = 0x1103; +} diff --git a/mcxa276-pac/src/port3/pcr3.rs b/mcxa276-pac/src/port3/pcr3.rs new file mode 100644 index 000000000..0bdf66c1b --- /dev/null +++ b/mcxa276-pac/src/port3/pcr3.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR3` reader"] +pub type R = crate::R; +#[doc = "Register `PCR3` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr3Spec; +impl crate::RegisterSpec for Pcr3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] +impl crate::Readable for Pcr3Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] +impl crate::Writable for Pcr3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR3 to value 0"] +impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port3/pcr30.rs b/mcxa276-pac/src/port3/pcr30.rs new file mode 100644 index 000000000..47270e810 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr30.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR30` reader"] +pub type R = crate::R; +#[doc = "Register `PCR30` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr30Spec; +impl crate::RegisterSpec for Pcr30Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] +impl crate::Readable for Pcr30Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] +impl crate::Writable for Pcr30Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR30 to value 0"] +impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port3/pcr31.rs b/mcxa276-pac/src/port3/pcr31.rs new file mode 100644 index 000000000..71bccb343 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr31.rs @@ -0,0 +1,814 @@ +#[doc = "Register `PCR31` reader"] +pub type R = crate::R; +#[doc = "Register `PCR31` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pv { + #[doc = "0: Low"] + Pv0 = 0, + #[doc = "1: High"] + Pv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PV` reader - Pull Value"] +pub type PvR = crate::BitReader; +impl PvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pv { + match self.bits { + false => Pv::Pv0, + true => Pv::Pv1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_pv0(&self) -> bool { + *self == Pv::Pv0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_pv1(&self) -> bool { + *self == Pv::Pv1 + } +} +#[doc = "Field `PV` writer - Pull Value"] +pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; +impl<'a, REG> PvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn pv0(self) -> &'a mut crate::W { + self.variant(Pv::Pv0) + } + #[doc = "High"] + #[inline(always)] + pub fn pv1(self) -> &'a mut crate::W { + self.variant(Pv::Pv1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&self) -> PvR { + PvR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 2 - Pull Value"] + #[inline(always)] + pub fn pv(&mut self) -> PvW { + PvW::new(self, 2) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr31Spec; +impl crate::RegisterSpec for Pcr31Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] +impl crate::Readable for Pcr31Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] +impl crate::Writable for Pcr31Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR31 to value 0"] +impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port3/pcr4.rs b/mcxa276-pac/src/port3/pcr4.rs new file mode 100644 index 000000000..9890bb2d4 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr4.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR4` reader"] +pub type R = crate::R; +#[doc = "Register `PCR4` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr4Spec; +impl crate::RegisterSpec for Pcr4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] +impl crate::Readable for Pcr4Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] +impl crate::Writable for Pcr4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR4 to value 0"] +impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port3/pcr5.rs b/mcxa276-pac/src/port3/pcr5.rs new file mode 100644 index 000000000..bbc9bfc8a --- /dev/null +++ b/mcxa276-pac/src/port3/pcr5.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR5` reader"] +pub type R = crate::R; +#[doc = "Register `PCR5` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr5Spec; +impl crate::RegisterSpec for Pcr5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] +impl crate::Readable for Pcr5Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] +impl crate::Writable for Pcr5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR5 to value 0"] +impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port3/pcr6.rs b/mcxa276-pac/src/port3/pcr6.rs new file mode 100644 index 000000000..dcc6c56c6 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr6.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR6` reader"] +pub type R = crate::R; +#[doc = "Register `PCR6` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr6Spec; +impl crate::RegisterSpec for Pcr6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] +impl crate::Readable for Pcr6Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] +impl crate::Writable for Pcr6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR6 to value 0"] +impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port3/pcr7.rs b/mcxa276-pac/src/port3/pcr7.rs new file mode 100644 index 000000000..71a9e66da --- /dev/null +++ b/mcxa276-pac/src/port3/pcr7.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR7` reader"] +pub type R = crate::R; +#[doc = "Register `PCR7` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr7Spec; +impl crate::RegisterSpec for Pcr7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] +impl crate::Readable for Pcr7Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] +impl crate::Writable for Pcr7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR7 to value 0"] +impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port3/pcr8.rs b/mcxa276-pac/src/port3/pcr8.rs new file mode 100644 index 000000000..46cac643d --- /dev/null +++ b/mcxa276-pac/src/port3/pcr8.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR8` reader"] +pub type R = crate::R; +#[doc = "Register `PCR8` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr8Spec; +impl crate::RegisterSpec for Pcr8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] +impl crate::Readable for Pcr8Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] +impl crate::Writable for Pcr8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR8 to value 0"] +impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port3/pcr9.rs b/mcxa276-pac/src/port3/pcr9.rs new file mode 100644 index 000000000..d28f59209 --- /dev/null +++ b/mcxa276-pac/src/port3/pcr9.rs @@ -0,0 +1,751 @@ +#[doc = "Register `PCR9` reader"] +pub type R = crate::R; +#[doc = "Register `PCR9` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, + #[doc = "8: Alternative 8 (chip-specific)"] + Mux1000 = 8, + #[doc = "9: Alternative 9 (chip-specific)"] + Mux1001 = 9, + #[doc = "10: Alternative 10 (chip-specific)"] + Mux1010 = 10, + #[doc = "11: Alternative 11 (chip-specific)"] + Mux1011 = 11, + #[doc = "12: Alternative 12 (chip-specific)"] + Mux1100 = 12, + #[doc = "13: Alternative 13 (chip-specific)"] + Mux1101 = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mux::Mux00), + 1 => Some(Mux::Mux01), + 2 => Some(Mux::Mux10), + 3 => Some(Mux::Mux11), + 4 => Some(Mux::Mux100), + 5 => Some(Mux::Mux101), + 6 => Some(Mux::Mux110), + 7 => Some(Mux::Mux111), + 8 => Some(Mux::Mux1000), + 9 => Some(Mux::Mux1001), + 10 => Some(Mux::Mux1010), + 11 => Some(Mux::Mux1011), + 12 => Some(Mux::Mux1100), + 13 => Some(Mux::Mux1101), + _ => None, + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn is_mux1000(&self) -> bool { + *self == Mux::Mux1000 + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn is_mux1001(&self) -> bool { + *self == Mux::Mux1001 + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn is_mux1010(&self) -> bool { + *self == Mux::Mux1010 + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn is_mux1011(&self) -> bool { + *self == Mux::Mux1011 + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn is_mux1100(&self) -> bool { + *self == Mux::Mux1100 + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn is_mux1101(&self) -> bool { + *self == Mux::Mux1101 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } + #[doc = "Alternative 8 (chip-specific)"] + #[inline(always)] + pub fn mux1000(self) -> &'a mut crate::W { + self.variant(Mux::Mux1000) + } + #[doc = "Alternative 9 (chip-specific)"] + #[inline(always)] + pub fn mux1001(self) -> &'a mut crate::W { + self.variant(Mux::Mux1001) + } + #[doc = "Alternative 10 (chip-specific)"] + #[inline(always)] + pub fn mux1010(self) -> &'a mut crate::W { + self.variant(Mux::Mux1010) + } + #[doc = "Alternative 11 (chip-specific)"] + #[inline(always)] + pub fn mux1011(self) -> &'a mut crate::W { + self.variant(Mux::Mux1011) + } + #[doc = "Alternative 12 (chip-specific)"] + #[inline(always)] + pub fn mux1100(self) -> &'a mut crate::W { + self.variant(Mux::Mux1100) + } + #[doc = "Alternative 13 (chip-specific)"] + #[inline(always)] + pub fn mux1101(self) -> &'a mut crate::W { + self.variant(Mux::Mux1101) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:11 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr9Spec; +impl crate::RegisterSpec for Pcr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] +impl crate::Readable for Pcr9Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] +impl crate::Writable for Pcr9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR9 to value 0"] +impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port3/verid.rs b/mcxa276-pac/src/port3/verid.rs new file mode 100644 index 000000000..330f53d57 --- /dev/null +++ b/mcxa276-pac/src/port3/verid.rs @@ -0,0 +1,68 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Basic implementation"] + Feature0 = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Feature0), + _ => None, + } + } + #[doc = "Basic implementation"] + #[inline(always)] + pub fn is_feature0(&self) -> bool { + *self == Feature::Feature0 + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0200_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0200_0000; +} diff --git a/mcxa276-pac/src/port4.rs b/mcxa276-pac/src/port4.rs new file mode 100644 index 000000000..d7ed05fc0 --- /dev/null +++ b/mcxa276-pac/src/port4.rs @@ -0,0 +1,428 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x0c], + gpclr: Gpclr, + gpchr: Gpchr, + _reserved3: [u8; 0x08], + config: Config, + _reserved4: [u8; 0x3c], + calib0: Calib0, + calib1: Calib1, + _reserved6: [u8; 0x18], + pcr0: Pcr0, + pcr1: Pcr1, + pcr2: Pcr2, + pcr3: Pcr3, + pcr4: Pcr4, + pcr5: Pcr5, + pcr6: Pcr6, + pcr7: Pcr7, + pcr8: Pcr8, + pcr9: Pcr9, + pcr10: Pcr10, + pcr11: Pcr11, + pcr12: Pcr12, + pcr13: Pcr13, + pcr14: Pcr14, + pcr15: Pcr15, + pcr16: Pcr16, + pcr17: Pcr17, + pcr18: Pcr18, + pcr19: Pcr19, + pcr20: Pcr20, + pcr21: Pcr21, + pcr22: Pcr22, + pcr23: Pcr23, + pcr24: Pcr24, + pcr25: Pcr25, + pcr26: Pcr26, + pcr27: Pcr27, + pcr28: Pcr28, + pcr29: Pcr29, + pcr30: Pcr30, + pcr31: Pcr31, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x10 - Global Pin Control Low"] + #[inline(always)] + pub const fn gpclr(&self) -> &Gpclr { + &self.gpclr + } + #[doc = "0x14 - Global Pin Control High"] + #[inline(always)] + pub const fn gpchr(&self) -> &Gpchr { + &self.gpchr + } + #[doc = "0x20 - Configuration"] + #[inline(always)] + pub const fn config(&self) -> &Config { + &self.config + } + #[doc = "0x60 - Calibration 0"] + #[inline(always)] + pub const fn calib0(&self) -> &Calib0 { + &self.calib0 + } + #[doc = "0x64 - Calibration 1"] + #[inline(always)] + pub const fn calib1(&self) -> &Calib1 { + &self.calib1 + } + #[doc = "0x80 - Pin Control 0"] + #[inline(always)] + pub const fn pcr0(&self) -> &Pcr0 { + &self.pcr0 + } + #[doc = "0x84 - Pin Control 1"] + #[inline(always)] + pub const fn pcr1(&self) -> &Pcr1 { + &self.pcr1 + } + #[doc = "0x88 - Pin Control 2"] + #[inline(always)] + pub const fn pcr2(&self) -> &Pcr2 { + &self.pcr2 + } + #[doc = "0x8c - Pin Control 3"] + #[inline(always)] + pub const fn pcr3(&self) -> &Pcr3 { + &self.pcr3 + } + #[doc = "0x90 - Pin Control 4"] + #[inline(always)] + pub const fn pcr4(&self) -> &Pcr4 { + &self.pcr4 + } + #[doc = "0x94 - Pin Control 5"] + #[inline(always)] + pub const fn pcr5(&self) -> &Pcr5 { + &self.pcr5 + } + #[doc = "0x98 - Pin Control 6"] + #[inline(always)] + pub const fn pcr6(&self) -> &Pcr6 { + &self.pcr6 + } + #[doc = "0x9c - Pin Control 7"] + #[inline(always)] + pub const fn pcr7(&self) -> &Pcr7 { + &self.pcr7 + } + #[doc = "0xa0 - Pin Control 8"] + #[inline(always)] + pub const fn pcr8(&self) -> &Pcr8 { + &self.pcr8 + } + #[doc = "0xa4 - Pin Control 9"] + #[inline(always)] + pub const fn pcr9(&self) -> &Pcr9 { + &self.pcr9 + } + #[doc = "0xa8 - Pin Control 10"] + #[inline(always)] + pub const fn pcr10(&self) -> &Pcr10 { + &self.pcr10 + } + #[doc = "0xac - Pin Control 11"] + #[inline(always)] + pub const fn pcr11(&self) -> &Pcr11 { + &self.pcr11 + } + #[doc = "0xb0 - Pin Control 12"] + #[inline(always)] + pub const fn pcr12(&self) -> &Pcr12 { + &self.pcr12 + } + #[doc = "0xb4 - Pin Control 13"] + #[inline(always)] + pub const fn pcr13(&self) -> &Pcr13 { + &self.pcr13 + } + #[doc = "0xb8 - Pin Control 14"] + #[inline(always)] + pub const fn pcr14(&self) -> &Pcr14 { + &self.pcr14 + } + #[doc = "0xbc - Pin Control 15"] + #[inline(always)] + pub const fn pcr15(&self) -> &Pcr15 { + &self.pcr15 + } + #[doc = "0xc0 - Pin Control 16"] + #[inline(always)] + pub const fn pcr16(&self) -> &Pcr16 { + &self.pcr16 + } + #[doc = "0xc4 - Pin Control 17"] + #[inline(always)] + pub const fn pcr17(&self) -> &Pcr17 { + &self.pcr17 + } + #[doc = "0xc8 - Pin Control 18"] + #[inline(always)] + pub const fn pcr18(&self) -> &Pcr18 { + &self.pcr18 + } + #[doc = "0xcc - Pin Control 19"] + #[inline(always)] + pub const fn pcr19(&self) -> &Pcr19 { + &self.pcr19 + } + #[doc = "0xd0 - Pin Control 20"] + #[inline(always)] + pub const fn pcr20(&self) -> &Pcr20 { + &self.pcr20 + } + #[doc = "0xd4 - Pin Control 21"] + #[inline(always)] + pub const fn pcr21(&self) -> &Pcr21 { + &self.pcr21 + } + #[doc = "0xd8 - Pin Control 22"] + #[inline(always)] + pub const fn pcr22(&self) -> &Pcr22 { + &self.pcr22 + } + #[doc = "0xdc - Pin Control 23"] + #[inline(always)] + pub const fn pcr23(&self) -> &Pcr23 { + &self.pcr23 + } + #[doc = "0xe0 - Pin Control 24"] + #[inline(always)] + pub const fn pcr24(&self) -> &Pcr24 { + &self.pcr24 + } + #[doc = "0xe4 - Pin Control 25"] + #[inline(always)] + pub const fn pcr25(&self) -> &Pcr25 { + &self.pcr25 + } + #[doc = "0xe8 - Pin Control 26"] + #[inline(always)] + pub const fn pcr26(&self) -> &Pcr26 { + &self.pcr26 + } + #[doc = "0xec - Pin Control 27"] + #[inline(always)] + pub const fn pcr27(&self) -> &Pcr27 { + &self.pcr27 + } + #[doc = "0xf0 - Pin Control 28"] + #[inline(always)] + pub const fn pcr28(&self) -> &Pcr28 { + &self.pcr28 + } + #[doc = "0xf4 - Pin Control 29"] + #[inline(always)] + pub const fn pcr29(&self) -> &Pcr29 { + &self.pcr29 + } + #[doc = "0xf8 - Pin Control 30"] + #[inline(always)] + pub const fn pcr30(&self) -> &Pcr30 { + &self.pcr30 + } + #[doc = "0xfc - Pin Control 31"] + #[inline(always)] + pub const fn pcr31(&self) -> &Pcr31 { + &self.pcr31 + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] +#[doc(alias = "GPCLR")] +pub type Gpclr = crate::Reg; +#[doc = "Global Pin Control Low"] +pub mod gpclr; +#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] +#[doc(alias = "GPCHR")] +pub type Gpchr = crate::Reg; +#[doc = "Global Pin Control High"] +pub mod gpchr; +#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +#[doc(alias = "CONFIG")] +pub type Config = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] +#[doc(alias = "CALIB0")] +pub type Calib0 = crate::Reg; +#[doc = "Calibration 0"] +pub mod calib0; +#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] +#[doc(alias = "CALIB1")] +pub type Calib1 = crate::Reg; +#[doc = "Calibration 1"] +pub mod calib1; +#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] +#[doc(alias = "PCR0")] +pub type Pcr0 = crate::Reg; +#[doc = "Pin Control 0"] +pub mod pcr0; +#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] +#[doc(alias = "PCR1")] +pub type Pcr1 = crate::Reg; +#[doc = "Pin Control 1"] +pub mod pcr1; +#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] +#[doc(alias = "PCR2")] +pub type Pcr2 = crate::Reg; +#[doc = "Pin Control 2"] +pub mod pcr2; +#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] +#[doc(alias = "PCR3")] +pub type Pcr3 = crate::Reg; +#[doc = "Pin Control 3"] +pub mod pcr3; +#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] +#[doc(alias = "PCR4")] +pub type Pcr4 = crate::Reg; +#[doc = "Pin Control 4"] +pub mod pcr4; +#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] +#[doc(alias = "PCR5")] +pub type Pcr5 = crate::Reg; +#[doc = "Pin Control 5"] +pub mod pcr5; +#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] +#[doc(alias = "PCR6")] +pub type Pcr6 = crate::Reg; +#[doc = "Pin Control 6"] +pub mod pcr6; +#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] +#[doc(alias = "PCR7")] +pub type Pcr7 = crate::Reg; +#[doc = "Pin Control 7"] +pub mod pcr7; +#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] +#[doc(alias = "PCR8")] +pub type Pcr8 = crate::Reg; +#[doc = "Pin Control 8"] +pub mod pcr8; +#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] +#[doc(alias = "PCR9")] +pub type Pcr9 = crate::Reg; +#[doc = "Pin Control 9"] +pub mod pcr9; +#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] +#[doc(alias = "PCR10")] +pub type Pcr10 = crate::Reg; +#[doc = "Pin Control 10"] +pub mod pcr10; +#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] +#[doc(alias = "PCR11")] +pub type Pcr11 = crate::Reg; +#[doc = "Pin Control 11"] +pub mod pcr11; +#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] +#[doc(alias = "PCR12")] +pub type Pcr12 = crate::Reg; +#[doc = "Pin Control 12"] +pub mod pcr12; +#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] +#[doc(alias = "PCR13")] +pub type Pcr13 = crate::Reg; +#[doc = "Pin Control 13"] +pub mod pcr13; +#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] +#[doc(alias = "PCR14")] +pub type Pcr14 = crate::Reg; +#[doc = "Pin Control 14"] +pub mod pcr14; +#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] +#[doc(alias = "PCR15")] +pub type Pcr15 = crate::Reg; +#[doc = "Pin Control 15"] +pub mod pcr15; +#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] +#[doc(alias = "PCR16")] +pub type Pcr16 = crate::Reg; +#[doc = "Pin Control 16"] +pub mod pcr16; +#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] +#[doc(alias = "PCR17")] +pub type Pcr17 = crate::Reg; +#[doc = "Pin Control 17"] +pub mod pcr17; +#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] +#[doc(alias = "PCR18")] +pub type Pcr18 = crate::Reg; +#[doc = "Pin Control 18"] +pub mod pcr18; +#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] +#[doc(alias = "PCR19")] +pub type Pcr19 = crate::Reg; +#[doc = "Pin Control 19"] +pub mod pcr19; +#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] +#[doc(alias = "PCR20")] +pub type Pcr20 = crate::Reg; +#[doc = "Pin Control 20"] +pub mod pcr20; +#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] +#[doc(alias = "PCR21")] +pub type Pcr21 = crate::Reg; +#[doc = "Pin Control 21"] +pub mod pcr21; +#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] +#[doc(alias = "PCR22")] +pub type Pcr22 = crate::Reg; +#[doc = "Pin Control 22"] +pub mod pcr22; +#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] +#[doc(alias = "PCR23")] +pub type Pcr23 = crate::Reg; +#[doc = "Pin Control 23"] +pub mod pcr23; +#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] +#[doc(alias = "PCR24")] +pub type Pcr24 = crate::Reg; +#[doc = "Pin Control 24"] +pub mod pcr24; +#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] +#[doc(alias = "PCR25")] +pub type Pcr25 = crate::Reg; +#[doc = "Pin Control 25"] +pub mod pcr25; +#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] +#[doc(alias = "PCR26")] +pub type Pcr26 = crate::Reg; +#[doc = "Pin Control 26"] +pub mod pcr26; +#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] +#[doc(alias = "PCR27")] +pub type Pcr27 = crate::Reg; +#[doc = "Pin Control 27"] +pub mod pcr27; +#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] +#[doc(alias = "PCR28")] +pub type Pcr28 = crate::Reg; +#[doc = "Pin Control 28"] +pub mod pcr28; +#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] +#[doc(alias = "PCR29")] +pub type Pcr29 = crate::Reg; +#[doc = "Pin Control 29"] +pub mod pcr29; +#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] +#[doc(alias = "PCR30")] +pub type Pcr30 = crate::Reg; +#[doc = "Pin Control 30"] +pub mod pcr30; +#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] +#[doc(alias = "PCR31")] +pub type Pcr31 = crate::Reg; +#[doc = "Pin Control 31"] +pub mod pcr31; diff --git a/mcxa276-pac/src/port4/calib0.rs b/mcxa276-pac/src/port4/calib0.rs new file mode 100644 index 000000000..029fa12f3 --- /dev/null +++ b/mcxa276-pac/src/port4/calib0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB0` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB0` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib0Spec; +impl crate::RegisterSpec for Calib0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] +impl crate::Readable for Calib0Spec {} +#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] +impl crate::Writable for Calib0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB0 to value 0"] +impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port4/calib1.rs b/mcxa276-pac/src/port4/calib1.rs new file mode 100644 index 000000000..e18f61234 --- /dev/null +++ b/mcxa276-pac/src/port4/calib1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CALIB1` reader"] +pub type R = crate::R; +#[doc = "Register `CALIB1` writer"] +pub type W = crate::W; +#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] +pub type NcalR = crate::FieldReader; +#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] +pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] +pub type PcalR = crate::FieldReader; +#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] +pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&self) -> NcalR { + NcalR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&self) -> PcalR { + PcalR::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] + #[inline(always)] + pub fn ncal(&mut self) -> NcalW { + NcalW::new(self, 0) + } + #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] + #[inline(always)] + pub fn pcal(&mut self) -> PcalW { + PcalW::new(self, 16) + } +} +#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Calib1Spec; +impl crate::RegisterSpec for Calib1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] +impl crate::Readable for Calib1Spec {} +#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] +impl crate::Writable for Calib1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CALIB1 to value 0"] +impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port4/config.rs b/mcxa276-pac/src/port4/config.rs new file mode 100644 index 000000000..da92c5b27 --- /dev/null +++ b/mcxa276-pac/src/port4/config.rs @@ -0,0 +1,84 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Port Voltage Range\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Range { + #[doc = "0: 1.71 V-3.6 V"] + Range0 = 0, + #[doc = "1: 2.70 V-3.6 V"] + Range1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Range) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RANGE` reader - Port Voltage Range"] +pub type RangeR = crate::BitReader; +impl RangeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Range { + match self.bits { + false => Range::Range0, + true => Range::Range1, + } + } + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn is_range0(&self) -> bool { + *self == Range::Range0 + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn is_range1(&self) -> bool { + *self == Range::Range1 + } +} +#[doc = "Field `RANGE` writer - Port Voltage Range"] +pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; +impl<'a, REG> RangeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "1.71 V-3.6 V"] + #[inline(always)] + pub fn range0(self) -> &'a mut crate::W { + self.variant(Range::Range0) + } + #[doc = "2.70 V-3.6 V"] + #[inline(always)] + pub fn range1(self) -> &'a mut crate::W { + self.variant(Range::Range1) + } +} +impl R { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&self) -> RangeR { + RangeR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Port Voltage Range"] + #[inline(always)] + pub fn range(&mut self) -> RangeW { + RangeW::new(self, 0) + } +} +#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConfigSpec; +impl crate::RegisterSpec for ConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for ConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for ConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port4/gpchr.rs b/mcxa276-pac/src/port4/gpchr.rs new file mode 100644 index 000000000..af92d0d62 --- /dev/null +++ b/mcxa276-pac/src/port4/gpchr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCHR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCHR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe16 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] +pub type Gpwe16R = crate::BitReader; +impl Gpwe16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe16 { + match self.bits { + false => Gpwe16::Gpwe0, + true => Gpwe16::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe16::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe16::Gpwe1 + } +} +#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] +pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; +impl<'a, REG> Gpwe16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe16::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe17 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] +pub type Gpwe17R = crate::BitReader; +impl Gpwe17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe17 { + match self.bits { + false => Gpwe17::Gpwe0, + true => Gpwe17::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe17::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe17::Gpwe1 + } +} +#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] +pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; +impl<'a, REG> Gpwe17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe17::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe18 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] +pub type Gpwe18R = crate::BitReader; +impl Gpwe18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe18 { + match self.bits { + false => Gpwe18::Gpwe0, + true => Gpwe18::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe18::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe18::Gpwe1 + } +} +#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] +pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; +impl<'a, REG> Gpwe18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe18::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe19 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] +pub type Gpwe19R = crate::BitReader; +impl Gpwe19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe19 { + match self.bits { + false => Gpwe19::Gpwe0, + true => Gpwe19::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe19::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe19::Gpwe1 + } +} +#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] +pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; +impl<'a, REG> Gpwe19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe19::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe20 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] +pub type Gpwe20R = crate::BitReader; +impl Gpwe20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe20 { + match self.bits { + false => Gpwe20::Gpwe0, + true => Gpwe20::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe20::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe20::Gpwe1 + } +} +#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] +pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; +impl<'a, REG> Gpwe20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe20::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe21 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] +pub type Gpwe21R = crate::BitReader; +impl Gpwe21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe21 { + match self.bits { + false => Gpwe21::Gpwe0, + true => Gpwe21::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe21::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe21::Gpwe1 + } +} +#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] +pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; +impl<'a, REG> Gpwe21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe21::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe22 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] +pub type Gpwe22R = crate::BitReader; +impl Gpwe22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe22 { + match self.bits { + false => Gpwe22::Gpwe0, + true => Gpwe22::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe22::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe22::Gpwe1 + } +} +#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] +pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; +impl<'a, REG> Gpwe22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe22::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe23 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] +pub type Gpwe23R = crate::BitReader; +impl Gpwe23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe23 { + match self.bits { + false => Gpwe23::Gpwe0, + true => Gpwe23::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe23::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe23::Gpwe1 + } +} +#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] +pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; +impl<'a, REG> Gpwe23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe23::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe24 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] +pub type Gpwe24R = crate::BitReader; +impl Gpwe24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe24 { + match self.bits { + false => Gpwe24::Gpwe0, + true => Gpwe24::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe24::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe24::Gpwe1 + } +} +#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] +pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; +impl<'a, REG> Gpwe24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe24::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe25 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] +pub type Gpwe25R = crate::BitReader; +impl Gpwe25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe25 { + match self.bits { + false => Gpwe25::Gpwe0, + true => Gpwe25::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe25::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe25::Gpwe1 + } +} +#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] +pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; +impl<'a, REG> Gpwe25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe25::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe26 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] +pub type Gpwe26R = crate::BitReader; +impl Gpwe26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe26 { + match self.bits { + false => Gpwe26::Gpwe0, + true => Gpwe26::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe26::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe26::Gpwe1 + } +} +#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] +pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; +impl<'a, REG> Gpwe26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe26::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe27 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] +pub type Gpwe27R = crate::BitReader; +impl Gpwe27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe27 { + match self.bits { + false => Gpwe27::Gpwe0, + true => Gpwe27::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe27::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe27::Gpwe1 + } +} +#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] +pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; +impl<'a, REG> Gpwe27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe27::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe28 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] +pub type Gpwe28R = crate::BitReader; +impl Gpwe28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe28 { + match self.bits { + false => Gpwe28::Gpwe0, + true => Gpwe28::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe28::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe28::Gpwe1 + } +} +#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] +pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; +impl<'a, REG> Gpwe28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe28::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe29 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] +pub type Gpwe29R = crate::BitReader; +impl Gpwe29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe29 { + match self.bits { + false => Gpwe29::Gpwe0, + true => Gpwe29::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe29::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe29::Gpwe1 + } +} +#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] +pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; +impl<'a, REG> Gpwe29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe29::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe30 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] +pub type Gpwe30R = crate::BitReader; +impl Gpwe30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe30 { + match self.bits { + false => Gpwe30::Gpwe0, + true => Gpwe30::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe30::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe30::Gpwe1 + } +} +#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] +pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; +impl<'a, REG> Gpwe30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe30::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe31 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] +pub type Gpwe31R = crate::BitReader; +impl Gpwe31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe31 { + match self.bits { + false => Gpwe31::Gpwe0, + true => Gpwe31::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe31::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe31::Gpwe1 + } +} +#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] +pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; +impl<'a, REG> Gpwe31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe31::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&self) -> Gpwe16R { + Gpwe16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&self) -> Gpwe17R { + Gpwe17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&self) -> Gpwe18R { + Gpwe18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&self) -> Gpwe19R { + Gpwe19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&self) -> Gpwe20R { + Gpwe20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&self) -> Gpwe21R { + Gpwe21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&self) -> Gpwe22R { + Gpwe22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&self) -> Gpwe23R { + Gpwe23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&self) -> Gpwe24R { + Gpwe24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&self) -> Gpwe25R { + Gpwe25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&self) -> Gpwe26R { + Gpwe26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&self) -> Gpwe27R { + Gpwe27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&self) -> Gpwe28R { + Gpwe28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&self) -> Gpwe29R { + Gpwe29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&self) -> Gpwe30R { + Gpwe30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&self) -> Gpwe31R { + Gpwe31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe16(&mut self) -> Gpwe16W { + Gpwe16W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe17(&mut self) -> Gpwe17W { + Gpwe17W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe18(&mut self) -> Gpwe18W { + Gpwe18W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe19(&mut self) -> Gpwe19W { + Gpwe19W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe20(&mut self) -> Gpwe20W { + Gpwe20W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe21(&mut self) -> Gpwe21W { + Gpwe21W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe22(&mut self) -> Gpwe22W { + Gpwe22W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe23(&mut self) -> Gpwe23W { + Gpwe23W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe24(&mut self) -> Gpwe24W { + Gpwe24W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe25(&mut self) -> Gpwe25W { + Gpwe25W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe26(&mut self) -> Gpwe26W { + Gpwe26W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe27(&mut self) -> Gpwe27W { + Gpwe27W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe28(&mut self) -> Gpwe28W { + Gpwe28W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe29(&mut self) -> Gpwe29W { + Gpwe29W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe30(&mut self) -> Gpwe30W { + Gpwe30W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe31(&mut self) -> Gpwe31W { + Gpwe31W::new(self, 31) + } +} +#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpchrSpec; +impl crate::RegisterSpec for GpchrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] +impl crate::Readable for GpchrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] +impl crate::Writable for GpchrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCHR to value 0"] +impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port4/gpclr.rs b/mcxa276-pac/src/port4/gpclr.rs new file mode 100644 index 000000000..21e5ff23d --- /dev/null +++ b/mcxa276-pac/src/port4/gpclr.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `GPCLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPCLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPWD` reader - Global Pin Write Data"] +pub type GpwdR = crate::FieldReader; +#[doc = "Field `GPWD` writer - Global Pin Write Data"] +pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe0 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] +pub type Gpwe0R = crate::BitReader; +impl Gpwe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe0 { + match self.bits { + false => Gpwe0::Gpwe0, + true => Gpwe0::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe0::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe0::Gpwe1 + } +} +#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] +pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; +impl<'a, REG> Gpwe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe0::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe1 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] +pub type Gpwe1R = crate::BitReader; +impl Gpwe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe1 { + match self.bits { + false => Gpwe1::Gpwe0, + true => Gpwe1::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe1::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe1::Gpwe1 + } +} +#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] +pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; +impl<'a, REG> Gpwe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe1::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe2 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] +pub type Gpwe2R = crate::BitReader; +impl Gpwe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe2 { + match self.bits { + false => Gpwe2::Gpwe0, + true => Gpwe2::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe2::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe2::Gpwe1 + } +} +#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] +pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; +impl<'a, REG> Gpwe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe2::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe3 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] +pub type Gpwe3R = crate::BitReader; +impl Gpwe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe3 { + match self.bits { + false => Gpwe3::Gpwe0, + true => Gpwe3::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe3::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe3::Gpwe1 + } +} +#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] +pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; +impl<'a, REG> Gpwe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe3::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe4 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] +pub type Gpwe4R = crate::BitReader; +impl Gpwe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe4 { + match self.bits { + false => Gpwe4::Gpwe0, + true => Gpwe4::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe4::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe4::Gpwe1 + } +} +#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] +pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; +impl<'a, REG> Gpwe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe4::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe5 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] +pub type Gpwe5R = crate::BitReader; +impl Gpwe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe5 { + match self.bits { + false => Gpwe5::Gpwe0, + true => Gpwe5::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe5::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe5::Gpwe1 + } +} +#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] +pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; +impl<'a, REG> Gpwe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe5::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe6 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] +pub type Gpwe6R = crate::BitReader; +impl Gpwe6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe6 { + match self.bits { + false => Gpwe6::Gpwe0, + true => Gpwe6::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe6::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe6::Gpwe1 + } +} +#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] +pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; +impl<'a, REG> Gpwe6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe6::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe7 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] +pub type Gpwe7R = crate::BitReader; +impl Gpwe7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe7 { + match self.bits { + false => Gpwe7::Gpwe0, + true => Gpwe7::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe7::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe7::Gpwe1 + } +} +#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] +pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; +impl<'a, REG> Gpwe7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe7::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe8 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] +pub type Gpwe8R = crate::BitReader; +impl Gpwe8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe8 { + match self.bits { + false => Gpwe8::Gpwe0, + true => Gpwe8::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe8::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe8::Gpwe1 + } +} +#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] +pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; +impl<'a, REG> Gpwe8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe8::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe9 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] +pub type Gpwe9R = crate::BitReader; +impl Gpwe9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe9 { + match self.bits { + false => Gpwe9::Gpwe0, + true => Gpwe9::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe9::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe9::Gpwe1 + } +} +#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] +pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; +impl<'a, REG> Gpwe9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe9::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe10 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] +pub type Gpwe10R = crate::BitReader; +impl Gpwe10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe10 { + match self.bits { + false => Gpwe10::Gpwe0, + true => Gpwe10::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe10::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe10::Gpwe1 + } +} +#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] +pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; +impl<'a, REG> Gpwe10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe10::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe11 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] +pub type Gpwe11R = crate::BitReader; +impl Gpwe11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe11 { + match self.bits { + false => Gpwe11::Gpwe0, + true => Gpwe11::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe11::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe11::Gpwe1 + } +} +#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] +pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; +impl<'a, REG> Gpwe11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe11::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe12 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] +pub type Gpwe12R = crate::BitReader; +impl Gpwe12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe12 { + match self.bits { + false => Gpwe12::Gpwe0, + true => Gpwe12::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe12::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe12::Gpwe1 + } +} +#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] +pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; +impl<'a, REG> Gpwe12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe12::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe13 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] +pub type Gpwe13R = crate::BitReader; +impl Gpwe13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe13 { + match self.bits { + false => Gpwe13::Gpwe0, + true => Gpwe13::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe13::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe13::Gpwe1 + } +} +#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] +pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; +impl<'a, REG> Gpwe13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe13::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe14 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] +pub type Gpwe14R = crate::BitReader; +impl Gpwe14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe14 { + match self.bits { + false => Gpwe14::Gpwe0, + true => Gpwe14::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe14::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe14::Gpwe1 + } +} +#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] +pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; +impl<'a, REG> Gpwe14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe14::Gpwe1) + } +} +#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpwe15 { + #[doc = "0: Not updated"] + Gpwe0 = 0, + #[doc = "1: Updated"] + Gpwe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpwe15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] +pub type Gpwe15R = crate::BitReader; +impl Gpwe15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpwe15 { + match self.bits { + false => Gpwe15::Gpwe0, + true => Gpwe15::Gpwe1, + } + } + #[doc = "Not updated"] + #[inline(always)] + pub fn is_gpwe0(&self) -> bool { + *self == Gpwe15::Gpwe0 + } + #[doc = "Updated"] + #[inline(always)] + pub fn is_gpwe1(&self) -> bool { + *self == Gpwe15::Gpwe1 + } +} +#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] +pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; +impl<'a, REG> Gpwe15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not updated"] + #[inline(always)] + pub fn gpwe0(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe0) + } + #[doc = "Updated"] + #[inline(always)] + pub fn gpwe1(self) -> &'a mut crate::W { + self.variant(Gpwe15::Gpwe1) + } +} +impl R { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&self) -> GpwdR { + GpwdR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&self) -> Gpwe0R { + Gpwe0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&self) -> Gpwe1R { + Gpwe1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&self) -> Gpwe2R { + Gpwe2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&self) -> Gpwe3R { + Gpwe3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&self) -> Gpwe4R { + Gpwe4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&self) -> Gpwe5R { + Gpwe5R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&self) -> Gpwe6R { + Gpwe6R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&self) -> Gpwe7R { + Gpwe7R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&self) -> Gpwe8R { + Gpwe8R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&self) -> Gpwe9R { + Gpwe9R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&self) -> Gpwe10R { + Gpwe10R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&self) -> Gpwe11R { + Gpwe11R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&self) -> Gpwe12R { + Gpwe12R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&self) -> Gpwe13R { + Gpwe13R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&self) -> Gpwe14R { + Gpwe14R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&self) -> Gpwe15R { + Gpwe15R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Global Pin Write Data"] + #[inline(always)] + pub fn gpwd(&mut self) -> GpwdW { + GpwdW::new(self, 0) + } + #[doc = "Bit 16 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe0(&mut self) -> Gpwe0W { + Gpwe0W::new(self, 16) + } + #[doc = "Bit 17 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe1(&mut self) -> Gpwe1W { + Gpwe1W::new(self, 17) + } + #[doc = "Bit 18 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe2(&mut self) -> Gpwe2W { + Gpwe2W::new(self, 18) + } + #[doc = "Bit 19 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe3(&mut self) -> Gpwe3W { + Gpwe3W::new(self, 19) + } + #[doc = "Bit 20 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe4(&mut self) -> Gpwe4W { + Gpwe4W::new(self, 20) + } + #[doc = "Bit 21 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe5(&mut self) -> Gpwe5W { + Gpwe5W::new(self, 21) + } + #[doc = "Bit 22 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe6(&mut self) -> Gpwe6W { + Gpwe6W::new(self, 22) + } + #[doc = "Bit 23 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe7(&mut self) -> Gpwe7W { + Gpwe7W::new(self, 23) + } + #[doc = "Bit 24 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe8(&mut self) -> Gpwe8W { + Gpwe8W::new(self, 24) + } + #[doc = "Bit 25 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe9(&mut self) -> Gpwe9W { + Gpwe9W::new(self, 25) + } + #[doc = "Bit 26 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe10(&mut self) -> Gpwe10W { + Gpwe10W::new(self, 26) + } + #[doc = "Bit 27 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe11(&mut self) -> Gpwe11W { + Gpwe11W::new(self, 27) + } + #[doc = "Bit 28 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe12(&mut self) -> Gpwe12W { + Gpwe12W::new(self, 28) + } + #[doc = "Bit 29 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe13(&mut self) -> Gpwe13W { + Gpwe13W::new(self, 29) + } + #[doc = "Bit 30 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe14(&mut self) -> Gpwe14W { + Gpwe14W::new(self, 30) + } + #[doc = "Bit 31 - Global Pin Write Enable"] + #[inline(always)] + pub fn gpwe15(&mut self) -> Gpwe15W { + Gpwe15W::new(self, 31) + } +} +#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpclrSpec; +impl crate::RegisterSpec for GpclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] +impl crate::Readable for GpclrSpec {} +#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] +impl crate::Writable for GpclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GPCLR to value 0"] +impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port4/pcr0.rs b/mcxa276-pac/src/port4/pcr0.rs new file mode 100644 index 000000000..395c4a341 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr0.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR0` reader"] +pub type R = crate::R; +#[doc = "Register `PCR0` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr0Spec; +impl crate::RegisterSpec for Pcr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] +impl crate::Readable for Pcr0Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] +impl crate::Writable for Pcr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR0 to value 0"] +impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port4/pcr1.rs b/mcxa276-pac/src/port4/pcr1.rs new file mode 100644 index 000000000..41e78955c --- /dev/null +++ b/mcxa276-pac/src/port4/pcr1.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR1` reader"] +pub type R = crate::R; +#[doc = "Register `PCR1` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr1Spec; +impl crate::RegisterSpec for Pcr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] +impl crate::Readable for Pcr1Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] +impl crate::Writable for Pcr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR1 to value 0"] +impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port4/pcr10.rs b/mcxa276-pac/src/port4/pcr10.rs new file mode 100644 index 000000000..9a358f658 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr10.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR10` reader"] +pub type R = crate::R; +#[doc = "Register `PCR10` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr10Spec; +impl crate::RegisterSpec for Pcr10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] +impl crate::Readable for Pcr10Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] +impl crate::Writable for Pcr10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR10 to value 0"] +impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port4/pcr11.rs b/mcxa276-pac/src/port4/pcr11.rs new file mode 100644 index 000000000..7b809b651 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr11.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR11` reader"] +pub type R = crate::R; +#[doc = "Register `PCR11` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr11Spec; +impl crate::RegisterSpec for Pcr11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] +impl crate::Readable for Pcr11Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] +impl crate::Writable for Pcr11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR11 to value 0"] +impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port4/pcr12.rs b/mcxa276-pac/src/port4/pcr12.rs new file mode 100644 index 000000000..2f5662298 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr12.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR12` reader"] +pub type R = crate::R; +#[doc = "Register `PCR12` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr12Spec; +impl crate::RegisterSpec for Pcr12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] +impl crate::Readable for Pcr12Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] +impl crate::Writable for Pcr12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR12 to value 0"] +impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port4/pcr13.rs b/mcxa276-pac/src/port4/pcr13.rs new file mode 100644 index 000000000..232ff4705 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr13.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR13` reader"] +pub type R = crate::R; +#[doc = "Register `PCR13` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr13Spec; +impl crate::RegisterSpec for Pcr13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] +impl crate::Readable for Pcr13Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] +impl crate::Writable for Pcr13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR13 to value 0"] +impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port4/pcr14.rs b/mcxa276-pac/src/port4/pcr14.rs new file mode 100644 index 000000000..b600e6419 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr14.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR14` reader"] +pub type R = crate::R; +#[doc = "Register `PCR14` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr14Spec; +impl crate::RegisterSpec for Pcr14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] +impl crate::Readable for Pcr14Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] +impl crate::Writable for Pcr14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR14 to value 0"] +impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port4/pcr15.rs b/mcxa276-pac/src/port4/pcr15.rs new file mode 100644 index 000000000..a7daba418 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr15.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR15` reader"] +pub type R = crate::R; +#[doc = "Register `PCR15` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr15Spec; +impl crate::RegisterSpec for Pcr15Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] +impl crate::Readable for Pcr15Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] +impl crate::Writable for Pcr15Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR15 to value 0"] +impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port4/pcr16.rs b/mcxa276-pac/src/port4/pcr16.rs new file mode 100644 index 000000000..1f5b9f2a8 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr16.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR16` reader"] +pub type R = crate::R; +#[doc = "Register `PCR16` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr16Spec; +impl crate::RegisterSpec for Pcr16Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] +impl crate::Readable for Pcr16Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] +impl crate::Writable for Pcr16Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR16 to value 0"] +impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port4/pcr17.rs b/mcxa276-pac/src/port4/pcr17.rs new file mode 100644 index 000000000..261687632 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr17.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR17` reader"] +pub type R = crate::R; +#[doc = "Register `PCR17` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr17Spec; +impl crate::RegisterSpec for Pcr17Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] +impl crate::Readable for Pcr17Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] +impl crate::Writable for Pcr17Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR17 to value 0"] +impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port4/pcr18.rs b/mcxa276-pac/src/port4/pcr18.rs new file mode 100644 index 000000000..b6b60a1fc --- /dev/null +++ b/mcxa276-pac/src/port4/pcr18.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR18` reader"] +pub type R = crate::R; +#[doc = "Register `PCR18` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr18Spec; +impl crate::RegisterSpec for Pcr18Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] +impl crate::Readable for Pcr18Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] +impl crate::Writable for Pcr18Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR18 to value 0"] +impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port4/pcr19.rs b/mcxa276-pac/src/port4/pcr19.rs new file mode 100644 index 000000000..231169e90 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr19.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR19` reader"] +pub type R = crate::R; +#[doc = "Register `PCR19` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr19Spec; +impl crate::RegisterSpec for Pcr19Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] +impl crate::Readable for Pcr19Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] +impl crate::Writable for Pcr19Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR19 to value 0"] +impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port4/pcr2.rs b/mcxa276-pac/src/port4/pcr2.rs new file mode 100644 index 000000000..2bdea035c --- /dev/null +++ b/mcxa276-pac/src/port4/pcr2.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR2` reader"] +pub type R = crate::R; +#[doc = "Register `PCR2` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr2Spec; +impl crate::RegisterSpec for Pcr2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] +impl crate::Readable for Pcr2Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] +impl crate::Writable for Pcr2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR2 to value 0"] +impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port4/pcr20.rs b/mcxa276-pac/src/port4/pcr20.rs new file mode 100644 index 000000000..d3457f781 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr20.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR20` reader"] +pub type R = crate::R; +#[doc = "Register `PCR20` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr20Spec; +impl crate::RegisterSpec for Pcr20Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] +impl crate::Readable for Pcr20Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] +impl crate::Writable for Pcr20Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR20 to value 0"] +impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port4/pcr21.rs b/mcxa276-pac/src/port4/pcr21.rs new file mode 100644 index 000000000..549acb257 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr21.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR21` reader"] +pub type R = crate::R; +#[doc = "Register `PCR21` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr21Spec; +impl crate::RegisterSpec for Pcr21Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] +impl crate::Readable for Pcr21Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] +impl crate::Writable for Pcr21Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR21 to value 0"] +impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port4/pcr22.rs b/mcxa276-pac/src/port4/pcr22.rs new file mode 100644 index 000000000..b52c672cb --- /dev/null +++ b/mcxa276-pac/src/port4/pcr22.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR22` reader"] +pub type R = crate::R; +#[doc = "Register `PCR22` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr22Spec; +impl crate::RegisterSpec for Pcr22Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] +impl crate::Readable for Pcr22Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] +impl crate::Writable for Pcr22Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR22 to value 0"] +impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port4/pcr23.rs b/mcxa276-pac/src/port4/pcr23.rs new file mode 100644 index 000000000..918e561a9 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr23.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR23` reader"] +pub type R = crate::R; +#[doc = "Register `PCR23` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr23Spec; +impl crate::RegisterSpec for Pcr23Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] +impl crate::Readable for Pcr23Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] +impl crate::Writable for Pcr23Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR23 to value 0"] +impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port4/pcr24.rs b/mcxa276-pac/src/port4/pcr24.rs new file mode 100644 index 000000000..1bc9d5574 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr24.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR24` reader"] +pub type R = crate::R; +#[doc = "Register `PCR24` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr24Spec; +impl crate::RegisterSpec for Pcr24Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] +impl crate::Readable for Pcr24Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] +impl crate::Writable for Pcr24Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR24 to value 0"] +impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port4/pcr25.rs b/mcxa276-pac/src/port4/pcr25.rs new file mode 100644 index 000000000..dbc8cae05 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr25.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR25` reader"] +pub type R = crate::R; +#[doc = "Register `PCR25` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr25Spec; +impl crate::RegisterSpec for Pcr25Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] +impl crate::Readable for Pcr25Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] +impl crate::Writable for Pcr25Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR25 to value 0"] +impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port4/pcr26.rs b/mcxa276-pac/src/port4/pcr26.rs new file mode 100644 index 000000000..24ffb3145 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr26.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR26` reader"] +pub type R = crate::R; +#[doc = "Register `PCR26` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr26Spec; +impl crate::RegisterSpec for Pcr26Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] +impl crate::Readable for Pcr26Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] +impl crate::Writable for Pcr26Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR26 to value 0"] +impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port4/pcr27.rs b/mcxa276-pac/src/port4/pcr27.rs new file mode 100644 index 000000000..ac4a51d32 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr27.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR27` reader"] +pub type R = crate::R; +#[doc = "Register `PCR27` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr27Spec; +impl crate::RegisterSpec for Pcr27Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] +impl crate::Readable for Pcr27Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] +impl crate::Writable for Pcr27Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR27 to value 0"] +impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port4/pcr28.rs b/mcxa276-pac/src/port4/pcr28.rs new file mode 100644 index 000000000..1315078be --- /dev/null +++ b/mcxa276-pac/src/port4/pcr28.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR28` reader"] +pub type R = crate::R; +#[doc = "Register `PCR28` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr28Spec; +impl crate::RegisterSpec for Pcr28Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] +impl crate::Readable for Pcr28Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] +impl crate::Writable for Pcr28Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR28 to value 0"] +impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port4/pcr29.rs b/mcxa276-pac/src/port4/pcr29.rs new file mode 100644 index 000000000..de7c41baa --- /dev/null +++ b/mcxa276-pac/src/port4/pcr29.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR29` reader"] +pub type R = crate::R; +#[doc = "Register `PCR29` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr29Spec; +impl crate::RegisterSpec for Pcr29Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] +impl crate::Readable for Pcr29Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] +impl crate::Writable for Pcr29Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR29 to value 0"] +impl crate::Resettable for Pcr29Spec {} diff --git a/mcxa276-pac/src/port4/pcr3.rs b/mcxa276-pac/src/port4/pcr3.rs new file mode 100644 index 000000000..8d707c930 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr3.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR3` reader"] +pub type R = crate::R; +#[doc = "Register `PCR3` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr3Spec; +impl crate::RegisterSpec for Pcr3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] +impl crate::Readable for Pcr3Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] +impl crate::Writable for Pcr3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR3 to value 0"] +impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port4/pcr30.rs b/mcxa276-pac/src/port4/pcr30.rs new file mode 100644 index 000000000..cce4166f4 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr30.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR30` reader"] +pub type R = crate::R; +#[doc = "Register `PCR30` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr30Spec; +impl crate::RegisterSpec for Pcr30Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] +impl crate::Readable for Pcr30Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] +impl crate::Writable for Pcr30Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR30 to value 0"] +impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port4/pcr31.rs b/mcxa276-pac/src/port4/pcr31.rs new file mode 100644 index 000000000..1f49159c2 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr31.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR31` reader"] +pub type R = crate::R; +#[doc = "Register `PCR31` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr31Spec; +impl crate::RegisterSpec for Pcr31Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] +impl crate::Readable for Pcr31Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] +impl crate::Writable for Pcr31Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR31 to value 0"] +impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port4/pcr4.rs b/mcxa276-pac/src/port4/pcr4.rs new file mode 100644 index 000000000..970ee4531 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr4.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR4` reader"] +pub type R = crate::R; +#[doc = "Register `PCR4` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr4Spec; +impl crate::RegisterSpec for Pcr4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] +impl crate::Readable for Pcr4Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] +impl crate::Writable for Pcr4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR4 to value 0"] +impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port4/pcr5.rs b/mcxa276-pac/src/port4/pcr5.rs new file mode 100644 index 000000000..53dad0e29 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr5.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR5` reader"] +pub type R = crate::R; +#[doc = "Register `PCR5` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr5Spec; +impl crate::RegisterSpec for Pcr5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] +impl crate::Readable for Pcr5Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] +impl crate::Writable for Pcr5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR5 to value 0"] +impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port4/pcr6.rs b/mcxa276-pac/src/port4/pcr6.rs new file mode 100644 index 000000000..d10e6a5b8 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr6.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR6` reader"] +pub type R = crate::R; +#[doc = "Register `PCR6` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr6Spec; +impl crate::RegisterSpec for Pcr6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] +impl crate::Readable for Pcr6Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] +impl crate::Writable for Pcr6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR6 to value 0"] +impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port4/pcr7.rs b/mcxa276-pac/src/port4/pcr7.rs new file mode 100644 index 000000000..18e6a4872 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr7.rs @@ -0,0 +1,673 @@ +#[doc = "Register `PCR7` reader"] +pub type R = crate::R; +#[doc = "Register `PCR7` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mux { + #[doc = "0: Alternative 0 (GPIO)"] + Mux00 = 0, + #[doc = "1: Alternative 1 (chip-specific)"] + Mux01 = 1, + #[doc = "2: Alternative 2 (chip-specific)"] + Mux10 = 2, + #[doc = "3: Alternative 3 (chip-specific)"] + Mux11 = 3, + #[doc = "4: Alternative 4 (chip-specific)"] + Mux100 = 4, + #[doc = "5: Alternative 5 (chip-specific)"] + Mux101 = 5, + #[doc = "6: Alternative 6 (chip-specific)"] + Mux110 = 6, + #[doc = "7: Alternative 7 (chip-specific)"] + Mux111 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mux) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mux { + type Ux = u8; +} +impl crate::IsEnum for Mux {} +#[doc = "Field `MUX` reader - Pin Multiplex Control"] +pub type MuxR = crate::FieldReader; +impl MuxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mux { + match self.bits { + 0 => Mux::Mux00, + 1 => Mux::Mux01, + 2 => Mux::Mux10, + 3 => Mux::Mux11, + 4 => Mux::Mux100, + 5 => Mux::Mux101, + 6 => Mux::Mux110, + 7 => Mux::Mux111, + _ => unreachable!(), + } + } + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn is_mux00(&self) -> bool { + *self == Mux::Mux00 + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn is_mux01(&self) -> bool { + *self == Mux::Mux01 + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn is_mux10(&self) -> bool { + *self == Mux::Mux10 + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn is_mux11(&self) -> bool { + *self == Mux::Mux11 + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn is_mux100(&self) -> bool { + *self == Mux::Mux100 + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn is_mux101(&self) -> bool { + *self == Mux::Mux101 + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn is_mux110(&self) -> bool { + *self == Mux::Mux110 + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn is_mux111(&self) -> bool { + *self == Mux::Mux111 + } +} +#[doc = "Field `MUX` writer - Pin Multiplex Control"] +pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; +impl<'a, REG> MuxW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Alternative 0 (GPIO)"] + #[inline(always)] + pub fn mux00(self) -> &'a mut crate::W { + self.variant(Mux::Mux00) + } + #[doc = "Alternative 1 (chip-specific)"] + #[inline(always)] + pub fn mux01(self) -> &'a mut crate::W { + self.variant(Mux::Mux01) + } + #[doc = "Alternative 2 (chip-specific)"] + #[inline(always)] + pub fn mux10(self) -> &'a mut crate::W { + self.variant(Mux::Mux10) + } + #[doc = "Alternative 3 (chip-specific)"] + #[inline(always)] + pub fn mux11(self) -> &'a mut crate::W { + self.variant(Mux::Mux11) + } + #[doc = "Alternative 4 (chip-specific)"] + #[inline(always)] + pub fn mux100(self) -> &'a mut crate::W { + self.variant(Mux::Mux100) + } + #[doc = "Alternative 5 (chip-specific)"] + #[inline(always)] + pub fn mux101(self) -> &'a mut crate::W { + self.variant(Mux::Mux101) + } + #[doc = "Alternative 6 (chip-specific)"] + #[inline(always)] + pub fn mux110(self) -> &'a mut crate::W { + self.variant(Mux::Mux110) + } + #[doc = "Alternative 7 (chip-specific)"] + #[inline(always)] + pub fn mux111(self) -> &'a mut crate::W { + self.variant(Mux::Mux111) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&self) -> MuxR { + MuxR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bits 8:10 - Pin Multiplex Control"] + #[inline(always)] + pub fn mux(&mut self) -> MuxW { + MuxW::new(self, 8) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr7Spec; +impl crate::RegisterSpec for Pcr7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] +impl crate::Readable for Pcr7Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] +impl crate::Writable for Pcr7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR7 to value 0"] +impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port4/pcr8.rs b/mcxa276-pac/src/port4/pcr8.rs new file mode 100644 index 000000000..8c6d7289b --- /dev/null +++ b/mcxa276-pac/src/port4/pcr8.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR8` reader"] +pub type R = crate::R; +#[doc = "Register `PCR8` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr8Spec; +impl crate::RegisterSpec for Pcr8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] +impl crate::Readable for Pcr8Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] +impl crate::Writable for Pcr8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR8 to value 0"] +impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port4/pcr9.rs b/mcxa276-pac/src/port4/pcr9.rs new file mode 100644 index 000000000..403e7e331 --- /dev/null +++ b/mcxa276-pac/src/port4/pcr9.rs @@ -0,0 +1,525 @@ +#[doc = "Register `PCR9` reader"] +pub type R = crate::R; +#[doc = "Register `PCR9` writer"] +pub type W = crate::W; +#[doc = "Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ps { + #[doc = "0: Enables internal pulldown resistor"] + Ps0 = 0, + #[doc = "1: Enables internal pullup resistor"] + Ps1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PS` reader - Pull Select"] +pub type PsR = crate::BitReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + false => Ps::Ps0, + true => Ps::Ps1, + } + } + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn is_ps0(&self) -> bool { + *self == Ps::Ps0 + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn is_ps1(&self) -> bool { + *self == Ps::Ps1 + } +} +#[doc = "Field `PS` writer - Pull Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables internal pulldown resistor"] + #[inline(always)] + pub fn ps0(self) -> &'a mut crate::W { + self.variant(Ps::Ps0) + } + #[doc = "Enables internal pullup resistor"] + #[inline(always)] + pub fn ps1(self) -> &'a mut crate::W { + self.variant(Ps::Ps1) + } +} +#[doc = "Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disables"] + Pe0 = 0, + #[doc = "1: Enables"] + Pe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Pull Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Pe0, + true => Pe::Pe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_pe0(&self) -> bool { + *self == Pe::Pe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_pe1(&self) -> bool { + *self == Pe::Pe1 + } +} +#[doc = "Field `PE` writer - Pull Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn pe0(self) -> &'a mut crate::W { + self.variant(Pe::Pe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn pe1(self) -> &'a mut crate::W { + self.variant(Pe::Pe1) + } +} +#[doc = "Slew Rate Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sre { + #[doc = "0: Fast"] + Sre0 = 0, + #[doc = "1: Slow"] + Sre1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRE` reader - Slew Rate Enable"] +pub type SreR = crate::BitReader; +impl SreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sre { + match self.bits { + false => Sre::Sre0, + true => Sre::Sre1, + } + } + #[doc = "Fast"] + #[inline(always)] + pub fn is_sre0(&self) -> bool { + *self == Sre::Sre0 + } + #[doc = "Slow"] + #[inline(always)] + pub fn is_sre1(&self) -> bool { + *self == Sre::Sre1 + } +} +#[doc = "Field `SRE` writer - Slew Rate Enable"] +pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; +impl<'a, REG> SreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fast"] + #[inline(always)] + pub fn sre0(self) -> &'a mut crate::W { + self.variant(Sre::Sre0) + } + #[doc = "Slow"] + #[inline(always)] + pub fn sre1(self) -> &'a mut crate::W { + self.variant(Sre::Sre1) + } +} +#[doc = "Open Drain Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ode { + #[doc = "0: Disables"] + Ode0 = 0, + #[doc = "1: Enables"] + Ode1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODE` reader - Open Drain Enable"] +pub type OdeR = crate::BitReader; +impl OdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ode { + match self.bits { + false => Ode::Ode0, + true => Ode::Ode1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ode0(&self) -> bool { + *self == Ode::Ode0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ode1(&self) -> bool { + *self == Ode::Ode1 + } +} +#[doc = "Field `ODE` writer - Open Drain Enable"] +pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; +impl<'a, REG> OdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ode0(self) -> &'a mut crate::W { + self.variant(Ode::Ode0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ode1(self) -> &'a mut crate::W { + self.variant(Ode::Ode1) + } +} +#[doc = "Drive Strength Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dse { + #[doc = "0: Low"] + Dse0 = 0, + #[doc = "1: High"] + Dse1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DSE` reader - Drive Strength Enable"] +pub type DseR = crate::BitReader; +impl DseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dse { + match self.bits { + false => Dse::Dse0, + true => Dse::Dse1, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_dse0(&self) -> bool { + *self == Dse::Dse0 + } + #[doc = "High"] + #[inline(always)] + pub fn is_dse1(&self) -> bool { + *self == Dse::Dse1 + } +} +#[doc = "Field `DSE` writer - Drive Strength Enable"] +pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; +impl<'a, REG> DseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn dse0(self) -> &'a mut crate::W { + self.variant(Dse::Dse0) + } + #[doc = "High"] + #[inline(always)] + pub fn dse1(self) -> &'a mut crate::W { + self.variant(Dse::Dse1) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Ibe0 = 0, + #[doc = "1: Enables"] + Ibe1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Ibe0, + true => Ibe::Ibe1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_ibe0(&self) -> bool { + *self == Ibe::Ibe0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_ibe1(&self) -> bool { + *self == Ibe::Ibe1 + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn ibe0(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn ibe1(self) -> &'a mut crate::W { + self.variant(Ibe::Ibe1) + } +} +#[doc = "Invert Input\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inv { + #[doc = "0: Does not invert"] + Inv0 = 0, + #[doc = "1: Inverts"] + Inv1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INV` reader - Invert Input"] +pub type InvR = crate::BitReader; +impl InvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inv { + match self.bits { + false => Inv::Inv0, + true => Inv::Inv1, + } + } + #[doc = "Does not invert"] + #[inline(always)] + pub fn is_inv0(&self) -> bool { + *self == Inv::Inv0 + } + #[doc = "Inverts"] + #[inline(always)] + pub fn is_inv1(&self) -> bool { + *self == Inv::Inv1 + } +} +#[doc = "Field `INV` writer - Invert Input"] +pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; +impl<'a, REG> InvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not invert"] + #[inline(always)] + pub fn inv0(self) -> &'a mut crate::W { + self.variant(Inv::Inv0) + } + #[doc = "Inverts"] + #[inline(always)] + pub fn inv1(self) -> &'a mut crate::W { + self.variant(Inv::Inv1) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Does not lock"] + Lk0 = 0, + #[doc = "1: Locks"] + Lk1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::Lk0, + true => Lk::Lk1, + } + } + #[doc = "Does not lock"] + #[inline(always)] + pub fn is_lk0(&self) -> bool { + *self == Lk::Lk0 + } + #[doc = "Locks"] + #[inline(always)] + pub fn is_lk1(&self) -> bool { + *self == Lk::Lk1 + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does not lock"] + #[inline(always)] + pub fn lk0(self) -> &'a mut crate::W { + self.variant(Lk::Lk0) + } + #[doc = "Locks"] + #[inline(always)] + pub fn lk1(self) -> &'a mut crate::W { + self.variant(Lk::Lk1) + } +} +impl R { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&self) -> SreR { + SreR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&self) -> OdeR { + OdeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&self) -> DseR { + DseR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&self) -> InvR { + InvR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pull Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 0) + } + #[doc = "Bit 1 - Pull Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 1) + } + #[doc = "Bit 3 - Slew Rate Enable"] + #[inline(always)] + pub fn sre(&mut self) -> SreW { + SreW::new(self, 3) + } + #[doc = "Bit 5 - Open Drain Enable"] + #[inline(always)] + pub fn ode(&mut self) -> OdeW { + OdeW::new(self, 5) + } + #[doc = "Bit 6 - Drive Strength Enable"] + #[inline(always)] + pub fn dse(&mut self) -> DseW { + DseW::new(self, 6) + } + #[doc = "Bit 12 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 12) + } + #[doc = "Bit 13 - Invert Input"] + #[inline(always)] + pub fn inv(&mut self) -> InvW { + InvW::new(self, 13) + } + #[doc = "Bit 15 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 15) + } +} +#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pcr9Spec; +impl crate::RegisterSpec for Pcr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] +impl crate::Readable for Pcr9Spec {} +#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] +impl crate::Writable for Pcr9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PCR9 to value 0"] +impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port4/verid.rs b/mcxa276-pac/src/port4/verid.rs new file mode 100644 index 000000000..330f53d57 --- /dev/null +++ b/mcxa276-pac/src/port4/verid.rs @@ -0,0 +1,68 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Basic implementation"] + Feature0 = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Feature0), + _ => None, + } + } + #[doc = "Basic implementation"] + #[inline(always)] + pub fn is_feature0(&self) -> bool { + *self == Feature::Feature0 + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0200_0000"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0200_0000; +} diff --git a/mcxa276-pac/src/rtc0.rs b/mcxa276-pac/src/rtc0.rs new file mode 100644 index 000000000..5a61d64e8 --- /dev/null +++ b/mcxa276-pac/src/rtc0.rs @@ -0,0 +1,94 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + tsr: Tsr, + tpr: Tpr, + tar: Tar, + tcr: Tcr, + cr: Cr, + sr: Sr, + lr: Lr, + ier: Ier, +} +impl RegisterBlock { + #[doc = "0x00 - RTC Time Seconds"] + #[inline(always)] + pub const fn tsr(&self) -> &Tsr { + &self.tsr + } + #[doc = "0x04 - RTC Time Prescaler"] + #[inline(always)] + pub const fn tpr(&self) -> &Tpr { + &self.tpr + } + #[doc = "0x08 - RTC Time Alarm"] + #[inline(always)] + pub const fn tar(&self) -> &Tar { + &self.tar + } + #[doc = "0x0c - RTC Time Compensation"] + #[inline(always)] + pub const fn tcr(&self) -> &Tcr { + &self.tcr + } + #[doc = "0x10 - RTC Control"] + #[inline(always)] + pub const fn cr(&self) -> &Cr { + &self.cr + } + #[doc = "0x14 - RTC Status"] + #[inline(always)] + pub const fn sr(&self) -> &Sr { + &self.sr + } + #[doc = "0x18 - RTC Lock"] + #[inline(always)] + pub const fn lr(&self) -> &Lr { + &self.lr + } + #[doc = "0x1c - RTC Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &Ier { + &self.ier + } +} +#[doc = "TSR (rw) register accessor: RTC Time Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsr`] module"] +#[doc(alias = "TSR")] +pub type Tsr = crate::Reg; +#[doc = "RTC Time Seconds"] +pub mod tsr; +#[doc = "TPR (rw) register accessor: RTC Time Prescaler\n\nYou can [`read`](crate::Reg::read) this register and get [`tpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpr`] module"] +#[doc(alias = "TPR")] +pub type Tpr = crate::Reg; +#[doc = "RTC Time Prescaler"] +pub mod tpr; +#[doc = "TAR (rw) register accessor: RTC Time Alarm\n\nYou can [`read`](crate::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] +#[doc(alias = "TAR")] +pub type Tar = crate::Reg; +#[doc = "RTC Time Alarm"] +pub mod tar; +#[doc = "TCR (rw) register accessor: RTC Time Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] +#[doc(alias = "TCR")] +pub type Tcr = crate::Reg; +#[doc = "RTC Time Compensation"] +pub mod tcr; +#[doc = "CR (rw) register accessor: RTC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] +#[doc(alias = "CR")] +pub type Cr = crate::Reg; +#[doc = "RTC Control"] +pub mod cr; +#[doc = "SR (rw) register accessor: RTC Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] +#[doc(alias = "SR")] +pub type Sr = crate::Reg; +#[doc = "RTC Status"] +pub mod sr; +#[doc = "LR (rw) register accessor: RTC Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lr`] module"] +#[doc(alias = "LR")] +pub type Lr = crate::Reg; +#[doc = "RTC Lock"] +pub mod lr; +#[doc = "IER (rw) register accessor: RTC Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] +#[doc(alias = "IER")] +pub type Ier = crate::Reg; +#[doc = "RTC Interrupt Enable"] +pub mod ier; diff --git a/mcxa276-pac/src/rtc0/cr.rs b/mcxa276-pac/src/rtc0/cr.rs new file mode 100644 index 000000000..c4935c9aa --- /dev/null +++ b/mcxa276-pac/src/rtc0/cr.rs @@ -0,0 +1,212 @@ +#[doc = "Register `CR` reader"] +pub type R = crate::R; +#[doc = "Register `CR` writer"] +pub type W = crate::W; +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swr { + #[doc = "0: No effect."] + Swr0 = 0, + #[doc = "1: Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."] + Swr1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWR` reader - Software Reset"] +pub type SwrR = crate::BitReader; +impl SwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swr { + match self.bits { + false => Swr::Swr0, + true => Swr::Swr1, + } + } + #[doc = "No effect."] + #[inline(always)] + pub fn is_swr_0(&self) -> bool { + *self == Swr::Swr0 + } + #[doc = "Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."] + #[inline(always)] + pub fn is_swr_1(&self) -> bool { + *self == Swr::Swr1 + } +} +#[doc = "Field `SWR` writer - Software Reset"] +pub type SwrW<'a, REG> = crate::BitWriter<'a, REG, Swr>; +impl<'a, REG> SwrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect."] + #[inline(always)] + pub fn swr_0(self) -> &'a mut crate::W { + self.variant(Swr::Swr0) + } + #[doc = "Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."] + #[inline(always)] + pub fn swr_1(self) -> &'a mut crate::W { + self.variant(Swr::Swr1) + } +} +#[doc = "Update Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Um { + #[doc = "0: Registers cannot be written when locked."] + Um0 = 0, + #[doc = "1: Registers can be written when locked under limited conditions."] + Um1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Um) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UM` reader - Update Mode"] +pub type UmR = crate::BitReader; +impl UmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Um { + match self.bits { + false => Um::Um0, + true => Um::Um1, + } + } + #[doc = "Registers cannot be written when locked."] + #[inline(always)] + pub fn is_um_0(&self) -> bool { + *self == Um::Um0 + } + #[doc = "Registers can be written when locked under limited conditions."] + #[inline(always)] + pub fn is_um_1(&self) -> bool { + *self == Um::Um1 + } +} +#[doc = "Field `UM` writer - Update Mode"] +pub type UmW<'a, REG> = crate::BitWriter<'a, REG, Um>; +impl<'a, REG> UmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Registers cannot be written when locked."] + #[inline(always)] + pub fn um_0(self) -> &'a mut crate::W { + self.variant(Um::Um0) + } + #[doc = "Registers can be written when locked under limited conditions."] + #[inline(always)] + pub fn um_1(self) -> &'a mut crate::W { + self.variant(Um::Um1) + } +} +#[doc = "LPO Select\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpos { + #[doc = "0: RTC prescaler increments using 32.768 kHz clock."] + Lpos0 = 0, + #[doc = "1: RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."] + Lpos1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpos) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPOS` reader - LPO Select"] +pub type LposR = crate::BitReader; +impl LposR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpos { + match self.bits { + false => Lpos::Lpos0, + true => Lpos::Lpos1, + } + } + #[doc = "RTC prescaler increments using 32.768 kHz clock."] + #[inline(always)] + pub fn is_lpos_0(&self) -> bool { + *self == Lpos::Lpos0 + } + #[doc = "RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."] + #[inline(always)] + pub fn is_lpos_1(&self) -> bool { + *self == Lpos::Lpos1 + } +} +#[doc = "Field `LPOS` writer - LPO Select"] +pub type LposW<'a, REG> = crate::BitWriter<'a, REG, Lpos>; +impl<'a, REG> LposW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RTC prescaler increments using 32.768 kHz clock."] + #[inline(always)] + pub fn lpos_0(self) -> &'a mut crate::W { + self.variant(Lpos::Lpos0) + } + #[doc = "RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."] + #[inline(always)] + pub fn lpos_1(self) -> &'a mut crate::W { + self.variant(Lpos::Lpos1) + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swr(&self) -> SwrR { + SwrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 3 - Update Mode"] + #[inline(always)] + pub fn um(&self) -> UmR { + UmR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 7 - LPO Select"] + #[inline(always)] + pub fn lpos(&self) -> LposR { + LposR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swr(&mut self) -> SwrW { + SwrW::new(self, 0) + } + #[doc = "Bit 3 - Update Mode"] + #[inline(always)] + pub fn um(&mut self) -> UmW { + UmW::new(self, 3) + } + #[doc = "Bit 7 - LPO Select"] + #[inline(always)] + pub fn lpos(&mut self) -> LposW { + LposW::new(self, 7) + } +} +#[doc = "RTC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrSpec; +impl crate::RegisterSpec for CrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CrSpec {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] +impl crate::Writable for CrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CR to value 0x80"] +impl crate::Resettable for CrSpec { + const RESET_VALUE: u32 = 0x80; +} diff --git a/mcxa276-pac/src/rtc0/ier.rs b/mcxa276-pac/src/rtc0/ier.rs new file mode 100644 index 000000000..ca93c35a4 --- /dev/null +++ b/mcxa276-pac/src/rtc0/ier.rs @@ -0,0 +1,423 @@ +#[doc = "Register `IER` reader"] +pub type R = crate::R; +#[doc = "Register `IER` writer"] +pub type W = crate::W; +#[doc = "Time Invalid Interrupt Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie { + #[doc = "0: No interrupt is generated."] + Tiie0 = 0, + #[doc = "1: An interrupt is generated."] + Tiie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE` reader - Time Invalid Interrupt Enable"] +pub type TiieR = crate::BitReader; +impl TiieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie { + match self.bits { + false => Tiie::Tiie0, + true => Tiie::Tiie1, + } + } + #[doc = "No interrupt is generated."] + #[inline(always)] + pub fn is_tiie_0(&self) -> bool { + *self == Tiie::Tiie0 + } + #[doc = "An interrupt is generated."] + #[inline(always)] + pub fn is_tiie_1(&self) -> bool { + *self == Tiie::Tiie1 + } +} +#[doc = "Field `TIIE` writer - Time Invalid Interrupt Enable"] +pub type TiieW<'a, REG> = crate::BitWriter<'a, REG, Tiie>; +impl<'a, REG> TiieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No interrupt is generated."] + #[inline(always)] + pub fn tiie_0(self) -> &'a mut crate::W { + self.variant(Tiie::Tiie0) + } + #[doc = "An interrupt is generated."] + #[inline(always)] + pub fn tiie_1(self) -> &'a mut crate::W { + self.variant(Tiie::Tiie1) + } +} +#[doc = "Time Overflow Interrupt Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Toie { + #[doc = "0: No interrupt is generated."] + Toie0 = 0, + #[doc = "1: An interrupt is generated."] + Toie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Toie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TOIE` reader - Time Overflow Interrupt Enable"] +pub type ToieR = crate::BitReader; +impl ToieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Toie { + match self.bits { + false => Toie::Toie0, + true => Toie::Toie1, + } + } + #[doc = "No interrupt is generated."] + #[inline(always)] + pub fn is_toie_0(&self) -> bool { + *self == Toie::Toie0 + } + #[doc = "An interrupt is generated."] + #[inline(always)] + pub fn is_toie_1(&self) -> bool { + *self == Toie::Toie1 + } +} +#[doc = "Field `TOIE` writer - Time Overflow Interrupt Enable"] +pub type ToieW<'a, REG> = crate::BitWriter<'a, REG, Toie>; +impl<'a, REG> ToieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No interrupt is generated."] + #[inline(always)] + pub fn toie_0(self) -> &'a mut crate::W { + self.variant(Toie::Toie0) + } + #[doc = "An interrupt is generated."] + #[inline(always)] + pub fn toie_1(self) -> &'a mut crate::W { + self.variant(Toie::Toie1) + } +} +#[doc = "Time Alarm Interrupt Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Taie { + #[doc = "0: No interrupt is generated."] + Taie0 = 0, + #[doc = "1: An interrupt is generated."] + Taie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Taie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TAIE` reader - Time Alarm Interrupt Enable"] +pub type TaieR = crate::BitReader; +impl TaieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Taie { + match self.bits { + false => Taie::Taie0, + true => Taie::Taie1, + } + } + #[doc = "No interrupt is generated."] + #[inline(always)] + pub fn is_taie_0(&self) -> bool { + *self == Taie::Taie0 + } + #[doc = "An interrupt is generated."] + #[inline(always)] + pub fn is_taie_1(&self) -> bool { + *self == Taie::Taie1 + } +} +#[doc = "Field `TAIE` writer - Time Alarm Interrupt Enable"] +pub type TaieW<'a, REG> = crate::BitWriter<'a, REG, Taie>; +impl<'a, REG> TaieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No interrupt is generated."] + #[inline(always)] + pub fn taie_0(self) -> &'a mut crate::W { + self.variant(Taie::Taie0) + } + #[doc = "An interrupt is generated."] + #[inline(always)] + pub fn taie_1(self) -> &'a mut crate::W { + self.variant(Taie::Taie1) + } +} +#[doc = "Time Seconds Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tsie { + #[doc = "0: Disables"] + Tsie0 = 0, + #[doc = "1: Enables"] + Tsie1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tsie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TSIE` reader - Time Seconds Interrupt Enable"] +pub type TsieR = crate::BitReader; +impl TsieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tsie { + match self.bits { + false => Tsie::Tsie0, + true => Tsie::Tsie1, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_tsie_0(&self) -> bool { + *self == Tsie::Tsie0 + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_tsie_1(&self) -> bool { + *self == Tsie::Tsie1 + } +} +#[doc = "Field `TSIE` writer - Time Seconds Interrupt Enable"] +pub type TsieW<'a, REG> = crate::BitWriter<'a, REG, Tsie>; +impl<'a, REG> TsieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn tsie_0(self) -> &'a mut crate::W { + self.variant(Tsie::Tsie0) + } + #[doc = "Enables"] + #[inline(always)] + pub fn tsie_1(self) -> &'a mut crate::W { + self.variant(Tsie::Tsie1) + } +} +#[doc = "Timer Seconds Interrupt Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tsic { + #[doc = "0: 1 Hz."] + Tsic0 = 0, + #[doc = "1: 2 Hz."] + Tsic1 = 1, + #[doc = "2: 4 Hz."] + Tsic2 = 2, + #[doc = "3: 8 Hz."] + Tsic3 = 3, + #[doc = "4: 16 Hz."] + Tsic4 = 4, + #[doc = "5: 32 Hz."] + Tsic5 = 5, + #[doc = "6: 64 Hz."] + Tsic6 = 6, + #[doc = "7: 128 Hz."] + Tsic7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tsic) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tsic { + type Ux = u8; +} +impl crate::IsEnum for Tsic {} +#[doc = "Field `TSIC` reader - Timer Seconds Interrupt Configuration"] +pub type TsicR = crate::FieldReader; +impl TsicR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tsic { + match self.bits { + 0 => Tsic::Tsic0, + 1 => Tsic::Tsic1, + 2 => Tsic::Tsic2, + 3 => Tsic::Tsic3, + 4 => Tsic::Tsic4, + 5 => Tsic::Tsic5, + 6 => Tsic::Tsic6, + 7 => Tsic::Tsic7, + _ => unreachable!(), + } + } + #[doc = "1 Hz."] + #[inline(always)] + pub fn is_tsic_0(&self) -> bool { + *self == Tsic::Tsic0 + } + #[doc = "2 Hz."] + #[inline(always)] + pub fn is_tsic_1(&self) -> bool { + *self == Tsic::Tsic1 + } + #[doc = "4 Hz."] + #[inline(always)] + pub fn is_tsic_2(&self) -> bool { + *self == Tsic::Tsic2 + } + #[doc = "8 Hz."] + #[inline(always)] + pub fn is_tsic_3(&self) -> bool { + *self == Tsic::Tsic3 + } + #[doc = "16 Hz."] + #[inline(always)] + pub fn is_tsic_4(&self) -> bool { + *self == Tsic::Tsic4 + } + #[doc = "32 Hz."] + #[inline(always)] + pub fn is_tsic_5(&self) -> bool { + *self == Tsic::Tsic5 + } + #[doc = "64 Hz."] + #[inline(always)] + pub fn is_tsic_6(&self) -> bool { + *self == Tsic::Tsic6 + } + #[doc = "128 Hz."] + #[inline(always)] + pub fn is_tsic_7(&self) -> bool { + *self == Tsic::Tsic7 + } +} +#[doc = "Field `TSIC` writer - Timer Seconds Interrupt Configuration"] +pub type TsicW<'a, REG> = crate::FieldWriter<'a, REG, 3, Tsic, crate::Safe>; +impl<'a, REG> TsicW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1 Hz."] + #[inline(always)] + pub fn tsic_0(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic0) + } + #[doc = "2 Hz."] + #[inline(always)] + pub fn tsic_1(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic1) + } + #[doc = "4 Hz."] + #[inline(always)] + pub fn tsic_2(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic2) + } + #[doc = "8 Hz."] + #[inline(always)] + pub fn tsic_3(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic3) + } + #[doc = "16 Hz."] + #[inline(always)] + pub fn tsic_4(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic4) + } + #[doc = "32 Hz."] + #[inline(always)] + pub fn tsic_5(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic5) + } + #[doc = "64 Hz."] + #[inline(always)] + pub fn tsic_6(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic6) + } + #[doc = "128 Hz."] + #[inline(always)] + pub fn tsic_7(self) -> &'a mut crate::W { + self.variant(Tsic::Tsic7) + } +} +impl R { + #[doc = "Bit 0 - Time Invalid Interrupt Enable"] + #[inline(always)] + pub fn tiie(&self) -> TiieR { + TiieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Time Overflow Interrupt Enable"] + #[inline(always)] + pub fn toie(&self) -> ToieR { + ToieR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Time Alarm Interrupt Enable"] + #[inline(always)] + pub fn taie(&self) -> TaieR { + TaieR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Time Seconds Interrupt Enable"] + #[inline(always)] + pub fn tsie(&self) -> TsieR { + TsieR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 16:18 - Timer Seconds Interrupt Configuration"] + #[inline(always)] + pub fn tsic(&self) -> TsicR { + TsicR::new(((self.bits >> 16) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Time Invalid Interrupt Enable"] + #[inline(always)] + pub fn tiie(&mut self) -> TiieW { + TiieW::new(self, 0) + } + #[doc = "Bit 1 - Time Overflow Interrupt Enable"] + #[inline(always)] + pub fn toie(&mut self) -> ToieW { + ToieW::new(self, 1) + } + #[doc = "Bit 2 - Time Alarm Interrupt Enable"] + #[inline(always)] + pub fn taie(&mut self) -> TaieW { + TaieW::new(self, 2) + } + #[doc = "Bit 4 - Time Seconds Interrupt Enable"] + #[inline(always)] + pub fn tsie(&mut self) -> TsieW { + TsieW::new(self, 4) + } + #[doc = "Bits 16:18 - Timer Seconds Interrupt Configuration"] + #[inline(always)] + pub fn tsic(&mut self) -> TsicW { + TsicW::new(self, 16) + } +} +#[doc = "RTC Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IerSpec; +impl crate::RegisterSpec for IerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IerSpec {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] +impl crate::Writable for IerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IER to value 0x07"] +impl crate::Resettable for IerSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/mcxa276-pac/src/rtc0/lr.rs b/mcxa276-pac/src/rtc0/lr.rs new file mode 100644 index 000000000..af475a01f --- /dev/null +++ b/mcxa276-pac/src/rtc0/lr.rs @@ -0,0 +1,275 @@ +#[doc = "Register `LR` reader"] +pub type R = crate::R; +#[doc = "Register `LR` writer"] +pub type W = crate::W; +#[doc = "Time Compensation Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tcl { + #[doc = "0: Time Compensation Register is locked and writes are ignored."] + Tcl0 = 0, + #[doc = "1: Time Compensation Register is not locked and writes complete as normal."] + Tcl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tcl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCL` reader - Time Compensation Lock"] +pub type TclR = crate::BitReader; +impl TclR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tcl { + match self.bits { + false => Tcl::Tcl0, + true => Tcl::Tcl1, + } + } + #[doc = "Time Compensation Register is locked and writes are ignored."] + #[inline(always)] + pub fn is_tcl_0(&self) -> bool { + *self == Tcl::Tcl0 + } + #[doc = "Time Compensation Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn is_tcl_1(&self) -> bool { + *self == Tcl::Tcl1 + } +} +#[doc = "Field `TCL` writer - Time Compensation Lock"] +pub type TclW<'a, REG> = crate::BitWriter<'a, REG, Tcl>; +impl<'a, REG> TclW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Time Compensation Register is locked and writes are ignored."] + #[inline(always)] + pub fn tcl_0(self) -> &'a mut crate::W { + self.variant(Tcl::Tcl0) + } + #[doc = "Time Compensation Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn tcl_1(self) -> &'a mut crate::W { + self.variant(Tcl::Tcl1) + } +} +#[doc = "Control Register Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crl { + #[doc = "0: Control Register is locked and writes are ignored."] + Crl0 = 0, + #[doc = "1: Control Register is not locked and writes complete as normal."] + Crl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRL` reader - Control Register Lock"] +pub type CrlR = crate::BitReader; +impl CrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crl { + match self.bits { + false => Crl::Crl0, + true => Crl::Crl1, + } + } + #[doc = "Control Register is locked and writes are ignored."] + #[inline(always)] + pub fn is_crl_0(&self) -> bool { + *self == Crl::Crl0 + } + #[doc = "Control Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn is_crl_1(&self) -> bool { + *self == Crl::Crl1 + } +} +#[doc = "Field `CRL` writer - Control Register Lock"] +pub type CrlW<'a, REG> = crate::BitWriter<'a, REG, Crl>; +impl<'a, REG> CrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Control Register is locked and writes are ignored."] + #[inline(always)] + pub fn crl_0(self) -> &'a mut crate::W { + self.variant(Crl::Crl0) + } + #[doc = "Control Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn crl_1(self) -> &'a mut crate::W { + self.variant(Crl::Crl1) + } +} +#[doc = "Status Register Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Srl { + #[doc = "0: Status Register is locked and writes are ignored."] + Srl0 = 0, + #[doc = "1: Status Register is not locked and writes complete as normal."] + Srl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Srl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRL` reader - Status Register Lock"] +pub type SrlR = crate::BitReader; +impl SrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Srl { + match self.bits { + false => Srl::Srl0, + true => Srl::Srl1, + } + } + #[doc = "Status Register is locked and writes are ignored."] + #[inline(always)] + pub fn is_srl_0(&self) -> bool { + *self == Srl::Srl0 + } + #[doc = "Status Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn is_srl_1(&self) -> bool { + *self == Srl::Srl1 + } +} +#[doc = "Field `SRL` writer - Status Register Lock"] +pub type SrlW<'a, REG> = crate::BitWriter<'a, REG, Srl>; +impl<'a, REG> SrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Status Register is locked and writes are ignored."] + #[inline(always)] + pub fn srl_0(self) -> &'a mut crate::W { + self.variant(Srl::Srl0) + } + #[doc = "Status Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn srl_1(self) -> &'a mut crate::W { + self.variant(Srl::Srl1) + } +} +#[doc = "Lock Register Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lrl { + #[doc = "0: Lock Register is locked and writes are ignored."] + Lrl0 = 0, + #[doc = "1: Lock Register is not locked and writes complete as normal."] + Lrl1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lrl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LRL` reader - Lock Register Lock"] +pub type LrlR = crate::BitReader; +impl LrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lrl { + match self.bits { + false => Lrl::Lrl0, + true => Lrl::Lrl1, + } + } + #[doc = "Lock Register is locked and writes are ignored."] + #[inline(always)] + pub fn is_lrl_0(&self) -> bool { + *self == Lrl::Lrl0 + } + #[doc = "Lock Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn is_lrl_1(&self) -> bool { + *self == Lrl::Lrl1 + } +} +#[doc = "Field `LRL` writer - Lock Register Lock"] +pub type LrlW<'a, REG> = crate::BitWriter<'a, REG, Lrl>; +impl<'a, REG> LrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Lock Register is locked and writes are ignored."] + #[inline(always)] + pub fn lrl_0(self) -> &'a mut crate::W { + self.variant(Lrl::Lrl0) + } + #[doc = "Lock Register is not locked and writes complete as normal."] + #[inline(always)] + pub fn lrl_1(self) -> &'a mut crate::W { + self.variant(Lrl::Lrl1) + } +} +impl R { + #[doc = "Bit 3 - Time Compensation Lock"] + #[inline(always)] + pub fn tcl(&self) -> TclR { + TclR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Control Register Lock"] + #[inline(always)] + pub fn crl(&self) -> CrlR { + CrlR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Status Register Lock"] + #[inline(always)] + pub fn srl(&self) -> SrlR { + SrlR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Lock Register Lock"] + #[inline(always)] + pub fn lrl(&self) -> LrlR { + LrlR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Time Compensation Lock"] + #[inline(always)] + pub fn tcl(&mut self) -> TclW { + TclW::new(self, 3) + } + #[doc = "Bit 4 - Control Register Lock"] + #[inline(always)] + pub fn crl(&mut self) -> CrlW { + CrlW::new(self, 4) + } + #[doc = "Bit 5 - Status Register Lock"] + #[inline(always)] + pub fn srl(&mut self) -> SrlW { + SrlW::new(self, 5) + } + #[doc = "Bit 6 - Lock Register Lock"] + #[inline(always)] + pub fn lrl(&mut self) -> LrlW { + LrlW::new(self, 6) + } +} +#[doc = "RTC Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LrSpec; +impl crate::RegisterSpec for LrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lr::R`](R) reader structure"] +impl crate::Readable for LrSpec {} +#[doc = "`write(|w| ..)` method takes [`lr::W`](W) writer structure"] +impl crate::Writable for LrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LR to value 0xff"] +impl crate::Resettable for LrSpec { + const RESET_VALUE: u32 = 0xff; +} diff --git a/mcxa276-pac/src/rtc0/sr.rs b/mcxa276-pac/src/rtc0/sr.rs new file mode 100644 index 000000000..208ae23dc --- /dev/null +++ b/mcxa276-pac/src/rtc0/sr.rs @@ -0,0 +1,209 @@ +#[doc = "Register `SR` reader"] +pub type R = crate::R; +#[doc = "Register `SR` writer"] +pub type W = crate::W; +#[doc = "Time Invalid Flag\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif { + #[doc = "0: Time is valid."] + Tif0 = 0, + #[doc = "1: Time is invalid and time counter is read as zero."] + Tif1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF` reader - Time Invalid Flag"] +pub type TifR = crate::BitReader; +impl TifR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif { + match self.bits { + false => Tif::Tif0, + true => Tif::Tif1, + } + } + #[doc = "Time is valid."] + #[inline(always)] + pub fn is_tif_0(&self) -> bool { + *self == Tif::Tif0 + } + #[doc = "Time is invalid and time counter is read as zero."] + #[inline(always)] + pub fn is_tif_1(&self) -> bool { + *self == Tif::Tif1 + } +} +#[doc = "Time Overflow Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tof { + #[doc = "0: Time overflow has not occurred."] + Tof0 = 0, + #[doc = "1: Time overflow has occurred and time counter reads as zero."] + Tof1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TOF` reader - Time Overflow Flag"] +pub type TofR = crate::BitReader; +impl TofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tof { + match self.bits { + false => Tof::Tof0, + true => Tof::Tof1, + } + } + #[doc = "Time overflow has not occurred."] + #[inline(always)] + pub fn is_tof_0(&self) -> bool { + *self == Tof::Tof0 + } + #[doc = "Time overflow has occurred and time counter reads as zero."] + #[inline(always)] + pub fn is_tof_1(&self) -> bool { + *self == Tof::Tof1 + } +} +#[doc = "Time Alarm Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Taf { + #[doc = "0: Time alarm has not occurred."] + Taf0 = 0, + #[doc = "1: Time alarm has occurred."] + Taf1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Taf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TAF` reader - Time Alarm Flag"] +pub type TafR = crate::BitReader; +impl TafR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Taf { + match self.bits { + false => Taf::Taf0, + true => Taf::Taf1, + } + } + #[doc = "Time alarm has not occurred."] + #[inline(always)] + pub fn is_taf_0(&self) -> bool { + *self == Taf::Taf0 + } + #[doc = "Time alarm has occurred."] + #[inline(always)] + pub fn is_taf_1(&self) -> bool { + *self == Taf::Taf1 + } +} +#[doc = "Time Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tce { + #[doc = "0: Disables."] + Tce0 = 0, + #[doc = "1: Enables."] + Tce1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tce) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TCE` reader - Time Counter Enable"] +pub type TceR = crate::BitReader; +impl TceR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tce { + match self.bits { + false => Tce::Tce0, + true => Tce::Tce1, + } + } + #[doc = "Disables."] + #[inline(always)] + pub fn is_tce_0(&self) -> bool { + *self == Tce::Tce0 + } + #[doc = "Enables."] + #[inline(always)] + pub fn is_tce_1(&self) -> bool { + *self == Tce::Tce1 + } +} +#[doc = "Field `TCE` writer - Time Counter Enable"] +pub type TceW<'a, REG> = crate::BitWriter<'a, REG, Tce>; +impl<'a, REG> TceW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables."] + #[inline(always)] + pub fn tce_0(self) -> &'a mut crate::W { + self.variant(Tce::Tce0) + } + #[doc = "Enables."] + #[inline(always)] + pub fn tce_1(self) -> &'a mut crate::W { + self.variant(Tce::Tce1) + } +} +impl R { + #[doc = "Bit 0 - Time Invalid Flag"] + #[inline(always)] + pub fn tif(&self) -> TifR { + TifR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Time Overflow Flag"] + #[inline(always)] + pub fn tof(&self) -> TofR { + TofR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Time Alarm Flag"] + #[inline(always)] + pub fn taf(&self) -> TafR { + TafR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Time Counter Enable"] + #[inline(always)] + pub fn tce(&self) -> TceR { + TceR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - Time Counter Enable"] + #[inline(always)] + pub fn tce(&mut self) -> TceW { + TceW::new(self, 4) + } +} +#[doc = "RTC Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrSpec; +impl crate::RegisterSpec for SrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SrSpec {} +#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] +impl crate::Writable for SrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SR to value 0x01"] +impl crate::Resettable for SrSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/rtc0/tar.rs b/mcxa276-pac/src/rtc0/tar.rs new file mode 100644 index 000000000..e12208b2b --- /dev/null +++ b/mcxa276-pac/src/rtc0/tar.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TAR` reader"] +pub type R = crate::R; +#[doc = "Register `TAR` writer"] +pub type W = crate::W; +#[doc = "Field `TAR` reader - Time Alarm Register"] +pub type TarR = crate::FieldReader; +#[doc = "Field `TAR` writer - Time Alarm Register"] +pub type TarW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Time Alarm Register"] + #[inline(always)] + pub fn tar(&self) -> TarR { + TarR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Time Alarm Register"] + #[inline(always)] + pub fn tar(&mut self) -> TarW { + TarW::new(self, 0) + } +} +#[doc = "RTC Time Alarm\n\nYou can [`read`](crate::Reg::read) this register and get [`tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TarSpec; +impl crate::RegisterSpec for TarSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tar::R`](R) reader structure"] +impl crate::Readable for TarSpec {} +#[doc = "`write(|w| ..)` method takes [`tar::W`](W) writer structure"] +impl crate::Writable for TarSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TAR to value 0"] +impl crate::Resettable for TarSpec {} diff --git a/mcxa276-pac/src/rtc0/tcr.rs b/mcxa276-pac/src/rtc0/tcr.rs new file mode 100644 index 000000000..fab51d2aa --- /dev/null +++ b/mcxa276-pac/src/rtc0/tcr.rs @@ -0,0 +1,184 @@ +#[doc = "Register `TCR` reader"] +pub type R = crate::R; +#[doc = "Register `TCR` writer"] +pub type W = crate::W; +#[doc = "Time Compensation Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tcr { + #[doc = "0: Time Prescaler Register overflows every 32768 clock cycles."] + Tcr0 = 0, + #[doc = "1: Time Prescaler Register overflows every 32767 clock cycles."] + Tcr1 = 1, + #[doc = "126: Time Prescaler Register overflows every 32642 clock cycles."] + Tcr126 = 126, + #[doc = "127: Time Prescaler Register overflows every 32641 clock cycles."] + Tcr127 = 127, + #[doc = "128: Time Prescaler Register overflows every 32896 clock cycles."] + Tcr128 = 128, + #[doc = "129: Time Prescaler Register overflows every 32895 clock cycles."] + Tcr129 = 129, + #[doc = "255: Time Prescaler Register overflows every 32769 clock cycles."] + Tcr255 = 255, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tcr) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tcr { + type Ux = u8; +} +impl crate::IsEnum for Tcr {} +#[doc = "Field `TCR` reader - Time Compensation Register"] +pub type TcrR = crate::FieldReader; +impl TcrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Tcr::Tcr0), + 1 => Some(Tcr::Tcr1), + 126 => Some(Tcr::Tcr126), + 127 => Some(Tcr::Tcr127), + 128 => Some(Tcr::Tcr128), + 129 => Some(Tcr::Tcr129), + 255 => Some(Tcr::Tcr255), + _ => None, + } + } + #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] + #[inline(always)] + pub fn is_tcr_0(&self) -> bool { + *self == Tcr::Tcr0 + } + #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] + #[inline(always)] + pub fn is_tcr_1(&self) -> bool { + *self == Tcr::Tcr1 + } + #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] + #[inline(always)] + pub fn is_tcr_126(&self) -> bool { + *self == Tcr::Tcr126 + } + #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] + #[inline(always)] + pub fn is_tcr_127(&self) -> bool { + *self == Tcr::Tcr127 + } + #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] + #[inline(always)] + pub fn is_tcr_128(&self) -> bool { + *self == Tcr::Tcr128 + } + #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] + #[inline(always)] + pub fn is_tcr_129(&self) -> bool { + *self == Tcr::Tcr129 + } + #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] + #[inline(always)] + pub fn is_tcr_255(&self) -> bool { + *self == Tcr::Tcr255 + } +} +#[doc = "Field `TCR` writer - Time Compensation Register"] +pub type TcrW<'a, REG> = crate::FieldWriter<'a, REG, 8, Tcr>; +impl<'a, REG> TcrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] + #[inline(always)] + pub fn tcr_0(self) -> &'a mut crate::W { + self.variant(Tcr::Tcr0) + } + #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] + #[inline(always)] + pub fn tcr_1(self) -> &'a mut crate::W { + self.variant(Tcr::Tcr1) + } + #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] + #[inline(always)] + pub fn tcr_126(self) -> &'a mut crate::W { + self.variant(Tcr::Tcr126) + } + #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] + #[inline(always)] + pub fn tcr_127(self) -> &'a mut crate::W { + self.variant(Tcr::Tcr127) + } + #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] + #[inline(always)] + pub fn tcr_128(self) -> &'a mut crate::W { + self.variant(Tcr::Tcr128) + } + #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] + #[inline(always)] + pub fn tcr_129(self) -> &'a mut crate::W { + self.variant(Tcr::Tcr129) + } + #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] + #[inline(always)] + pub fn tcr_255(self) -> &'a mut crate::W { + self.variant(Tcr::Tcr255) + } +} +#[doc = "Field `CIR` reader - Compensation Interval Register"] +pub type CirR = crate::FieldReader; +#[doc = "Field `CIR` writer - Compensation Interval Register"] +pub type CirW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TCV` reader - Time Compensation Value"] +pub type TcvR = crate::FieldReader; +#[doc = "Field `CIC` reader - Compensation Interval Counter"] +pub type CicR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Time Compensation Register"] + #[inline(always)] + pub fn tcr(&self) -> TcrR { + TcrR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Compensation Interval Register"] + #[inline(always)] + pub fn cir(&self) -> CirR { + CirR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Time Compensation Value"] + #[inline(always)] + pub fn tcv(&self) -> TcvR { + TcvR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Compensation Interval Counter"] + #[inline(always)] + pub fn cic(&self) -> CicR { + CicR::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Time Compensation Register"] + #[inline(always)] + pub fn tcr(&mut self) -> TcrW { + TcrW::new(self, 0) + } + #[doc = "Bits 8:15 - Compensation Interval Register"] + #[inline(always)] + pub fn cir(&mut self) -> CirW { + CirW::new(self, 8) + } +} +#[doc = "RTC Time Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcrSpec; +impl crate::RegisterSpec for TcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] +impl crate::Readable for TcrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] +impl crate::Writable for TcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TCR to value 0"] +impl crate::Resettable for TcrSpec {} diff --git a/mcxa276-pac/src/rtc0/tpr.rs b/mcxa276-pac/src/rtc0/tpr.rs new file mode 100644 index 000000000..3fec7f502 --- /dev/null +++ b/mcxa276-pac/src/rtc0/tpr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TPR` reader"] +pub type R = crate::R; +#[doc = "Register `TPR` writer"] +pub type W = crate::W; +#[doc = "Field `TPR` reader - Time Prescaler Register"] +pub type TprR = crate::FieldReader; +#[doc = "Field `TPR` writer - Time Prescaler Register"] +pub type TprW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Time Prescaler Register"] + #[inline(always)] + pub fn tpr(&self) -> TprR { + TprR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Time Prescaler Register"] + #[inline(always)] + pub fn tpr(&mut self) -> TprW { + TprW::new(self, 0) + } +} +#[doc = "RTC Time Prescaler\n\nYou can [`read`](crate::Reg::read) this register and get [`tpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TprSpec; +impl crate::RegisterSpec for TprSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tpr::R`](R) reader structure"] +impl crate::Readable for TprSpec {} +#[doc = "`write(|w| ..)` method takes [`tpr::W`](W) writer structure"] +impl crate::Writable for TprSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TPR to value 0"] +impl crate::Resettable for TprSpec {} diff --git a/mcxa276-pac/src/rtc0/tsr.rs b/mcxa276-pac/src/rtc0/tsr.rs new file mode 100644 index 000000000..ca2ecf566 --- /dev/null +++ b/mcxa276-pac/src/rtc0/tsr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSR` reader"] +pub type R = crate::R; +#[doc = "Register `TSR` writer"] +pub type W = crate::W; +#[doc = "Field `TSR` reader - Time Seconds Register"] +pub type TsrR = crate::FieldReader; +#[doc = "Field `TSR` writer - Time Seconds Register"] +pub type TsrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Time Seconds Register"] + #[inline(always)] + pub fn tsr(&self) -> TsrR { + TsrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Time Seconds Register"] + #[inline(always)] + pub fn tsr(&mut self) -> TsrW { + TsrW::new(self, 0) + } +} +#[doc = "RTC Time Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TsrSpec; +impl crate::RegisterSpec for TsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tsr::R`](R) reader structure"] +impl crate::Readable for TsrSpec {} +#[doc = "`write(|w| ..)` method takes [`tsr::W`](W) writer structure"] +impl crate::Writable for TsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSR to value 0"] +impl crate::Resettable for TsrSpec {} diff --git a/mcxa276-pac/src/sau.rs b/mcxa276-pac/src/sau.rs new file mode 100644 index 000000000..aae9f7bb1 --- /dev/null +++ b/mcxa276-pac/src/sau.rs @@ -0,0 +1,84 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0xd0], + ctrl: Ctrl, + type_: Type, + rnr: Rnr, + rbar: Rbar, + rlar: Rlar, + sfsr: Sfsr, + sfar: Sfar, +} +impl RegisterBlock { + #[doc = "0xd0 - Security Attribution Unit Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0xd4 - Security Attribution Unit Type Register"] + #[inline(always)] + pub const fn type_(&self) -> &Type { + &self.type_ + } + #[doc = "0xd8 - Security Attribution Unit Region Number Register"] + #[inline(always)] + pub const fn rnr(&self) -> &Rnr { + &self.rnr + } + #[doc = "0xdc - Security Attribution Unit Region Base Address Register"] + #[inline(always)] + pub const fn rbar(&self) -> &Rbar { + &self.rbar + } + #[doc = "0xe0 - Security Attribution Unit Region Limit Address Register"] + #[inline(always)] + pub const fn rlar(&self) -> &Rlar { + &self.rlar + } + #[doc = "0xe4 - Secure Fault Status Register"] + #[inline(always)] + pub const fn sfsr(&self) -> &Sfsr { + &self.sfsr + } + #[doc = "0xe8 - Secure Fault Address Register"] + #[inline(always)] + pub const fn sfar(&self) -> &Sfar { + &self.sfar + } +} +#[doc = "CTRL (rw) register accessor: Security Attribution Unit Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Security Attribution Unit Control Register"] +pub mod ctrl; +#[doc = "TYPE (rw) register accessor: Security Attribution Unit Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`type_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`type_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@type_`] module"] +#[doc(alias = "TYPE")] +pub type Type = crate::Reg; +#[doc = "Security Attribution Unit Type Register"] +pub mod type_; +#[doc = "RNR (rw) register accessor: Security Attribution Unit Region Number Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rnr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnr`] module"] +#[doc(alias = "RNR")] +pub type Rnr = crate::Reg; +#[doc = "Security Attribution Unit Region Number Register"] +pub mod rnr; +#[doc = "RBAR (rw) register accessor: Security Attribution Unit Region Base Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rbar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rbar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbar`] module"] +#[doc(alias = "RBAR")] +pub type Rbar = crate::Reg; +#[doc = "Security Attribution Unit Region Base Address Register"] +pub mod rbar; +#[doc = "RLAR (rw) register accessor: Security Attribution Unit Region Limit Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rlar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rlar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rlar`] module"] +#[doc(alias = "RLAR")] +pub type Rlar = crate::Reg; +#[doc = "Security Attribution Unit Region Limit Address Register"] +pub mod rlar; +#[doc = "SFSR (rw) register accessor: Secure Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfsr`] module"] +#[doc(alias = "SFSR")] +pub type Sfsr = crate::Reg; +#[doc = "Secure Fault Status Register"] +pub mod sfsr; +#[doc = "SFAR (rw) register accessor: Secure Fault Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfar`] module"] +#[doc(alias = "SFAR")] +pub type Sfar = crate::Reg; +#[doc = "Secure Fault Address Register"] +pub mod sfar; diff --git a/mcxa276-pac/src/sau/ctrl.rs b/mcxa276-pac/src/sau/ctrl.rs new file mode 100644 index 000000000..1e08b8c60 --- /dev/null +++ b/mcxa276-pac/src/sau/ctrl.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Enable { + #[doc = "0: The SAU is disabled."] + Disabled = 0, + #[doc = "1: The SAU is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Enable) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] +pub type EnableR = crate::BitReader; +impl EnableR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Enable { + match self.bits { + false => Enable::Disabled, + true => Enable::Enabled, + } + } + #[doc = "The SAU is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Enable::Disabled + } + #[doc = "The SAU is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Enable::Enabled + } +} +#[doc = "Field `ENABLE` writer - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG, Enable>; +impl<'a, REG> EnableW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SAU is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Enable::Disabled) + } + #[doc = "The SAU is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Enable::Enabled) + } +} +#[doc = "All Non-secure.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Allns { + #[doc = "0: Memory is marked as Secure and is not Non-secure callable."] + SecuredMemory = 0, + #[doc = "1: Memory is marked as Non-secure."] + NonSecuredMemory = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Allns) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ALLNS` reader - All Non-secure."] +pub type AllnsR = crate::BitReader; +impl AllnsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Allns { + match self.bits { + false => Allns::SecuredMemory, + true => Allns::NonSecuredMemory, + } + } + #[doc = "Memory is marked as Secure and is not Non-secure callable."] + #[inline(always)] + pub fn is_secured_memory(&self) -> bool { + *self == Allns::SecuredMemory + } + #[doc = "Memory is marked as Non-secure."] + #[inline(always)] + pub fn is_non_secured_memory(&self) -> bool { + *self == Allns::NonSecuredMemory + } +} +#[doc = "Field `ALLNS` writer - All Non-secure."] +pub type AllnsW<'a, REG> = crate::BitWriter<'a, REG, Allns>; +impl<'a, REG> AllnsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Memory is marked as Secure and is not Non-secure callable."] + #[inline(always)] + pub fn secured_memory(self) -> &'a mut crate::W { + self.variant(Allns::SecuredMemory) + } + #[doc = "Memory is marked as Non-secure."] + #[inline(always)] + pub fn non_secured_memory(self) -> &'a mut crate::W { + self.variant(Allns::NonSecuredMemory) + } +} +impl R { + #[doc = "Bit 0 - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - All Non-secure."] + #[inline(always)] + pub fn allns(&self) -> AllnsR { + AllnsR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] + #[inline(always)] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 0) + } + #[doc = "Bit 1 - All Non-secure."] + #[inline(always)] + pub fn allns(&mut self) -> AllnsW { + AllnsW::new(self, 1) + } +} +#[doc = "Security Attribution Unit Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/sau/rbar.rs b/mcxa276-pac/src/sau/rbar.rs new file mode 100644 index 000000000..271ec8df1 --- /dev/null +++ b/mcxa276-pac/src/sau/rbar.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RBAR` reader"] +pub type R = crate::R; +#[doc = "Register `RBAR` writer"] +pub type W = crate::W; +#[doc = "Field `BADDR` reader - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] +pub type BaddrR = crate::FieldReader; +#[doc = "Field `BADDR` writer - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] +pub type BaddrW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] + #[inline(always)] + pub fn baddr(&self) -> BaddrR { + BaddrR::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] + #[inline(always)] + pub fn baddr(&mut self) -> BaddrW { + BaddrW::new(self, 5) + } +} +#[doc = "Security Attribution Unit Region Base Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rbar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rbar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RbarSpec; +impl crate::RegisterSpec for RbarSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rbar::R`](R) reader structure"] +impl crate::Readable for RbarSpec {} +#[doc = "`write(|w| ..)` method takes [`rbar::W`](W) writer structure"] +impl crate::Writable for RbarSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RBAR to value 0"] +impl crate::Resettable for RbarSpec {} diff --git a/mcxa276-pac/src/sau/rlar.rs b/mcxa276-pac/src/sau/rlar.rs new file mode 100644 index 000000000..ad851af2f --- /dev/null +++ b/mcxa276-pac/src/sau/rlar.rs @@ -0,0 +1,161 @@ +#[doc = "Register `RLAR` reader"] +pub type R = crate::R; +#[doc = "Register `RLAR` writer"] +pub type W = crate::W; +#[doc = "Enable. SAU region enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Enable { + #[doc = "0: SAU region is enabled."] + Enabled = 0, + #[doc = "1: SAU region is disabled."] + Disabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Enable) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - Enable. SAU region enable."] +pub type EnableR = crate::BitReader; +impl EnableR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Enable { + match self.bits { + false => Enable::Enabled, + true => Enable::Disabled, + } + } + #[doc = "SAU region is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Enable::Enabled + } + #[doc = "SAU region is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Enable::Disabled + } +} +#[doc = "Field `ENABLE` writer - Enable. SAU region enable."] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG, Enable>; +impl<'a, REG> EnableW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SAU region is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Enable::Enabled) + } + #[doc = "SAU region is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Enable::Disabled) + } +} +#[doc = "Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nsc { + #[doc = "0: Region is not Non-secure callable."] + NotNonSecureCallable = 0, + #[doc = "1: Region is Non-secure callable."] + NonSecureCallable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nsc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NSC` reader - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] +pub type NscR = crate::BitReader; +impl NscR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nsc { + match self.bits { + false => Nsc::NotNonSecureCallable, + true => Nsc::NonSecureCallable, + } + } + #[doc = "Region is not Non-secure callable."] + #[inline(always)] + pub fn is_not_non_secure_callable(&self) -> bool { + *self == Nsc::NotNonSecureCallable + } + #[doc = "Region is Non-secure callable."] + #[inline(always)] + pub fn is_non_secure_callable(&self) -> bool { + *self == Nsc::NonSecureCallable + } +} +#[doc = "Field `NSC` writer - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] +pub type NscW<'a, REG> = crate::BitWriter<'a, REG, Nsc>; +impl<'a, REG> NscW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Region is not Non-secure callable."] + #[inline(always)] + pub fn not_non_secure_callable(self) -> &'a mut crate::W { + self.variant(Nsc::NotNonSecureCallable) + } + #[doc = "Region is Non-secure callable."] + #[inline(always)] + pub fn non_secure_callable(self) -> &'a mut crate::W { + self.variant(Nsc::NonSecureCallable) + } +} +#[doc = "Field `LADDR` reader - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] +pub type LaddrR = crate::FieldReader; +#[doc = "Field `LADDR` writer - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] +pub type LaddrW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Enable. SAU region enable."] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] + #[inline(always)] + pub fn nsc(&self) -> NscR { + NscR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] + #[inline(always)] + pub fn laddr(&self) -> LaddrR { + LaddrR::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Enable. SAU region enable."] + #[inline(always)] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 0) + } + #[doc = "Bit 1 - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] + #[inline(always)] + pub fn nsc(&mut self) -> NscW { + NscW::new(self, 1) + } + #[doc = "Bits 5:31 - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] + #[inline(always)] + pub fn laddr(&mut self) -> LaddrW { + LaddrW::new(self, 5) + } +} +#[doc = "Security Attribution Unit Region Limit Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rlar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rlar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RlarSpec; +impl crate::RegisterSpec for RlarSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rlar::R`](R) reader structure"] +impl crate::Readable for RlarSpec {} +#[doc = "`write(|w| ..)` method takes [`rlar::W`](W) writer structure"] +impl crate::Writable for RlarSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RLAR to value 0"] +impl crate::Resettable for RlarSpec {} diff --git a/mcxa276-pac/src/sau/rnr.rs b/mcxa276-pac/src/sau/rnr.rs new file mode 100644 index 000000000..6e871ecd6 --- /dev/null +++ b/mcxa276-pac/src/sau/rnr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RNR` reader"] +pub type R = crate::R; +#[doc = "Register `RNR` writer"] +pub type W = crate::W; +#[doc = "Field `REGION` reader - Region number."] +pub type RegionR = crate::FieldReader; +#[doc = "Field `REGION` writer - Region number."] +pub type RegionW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Region number."] + #[inline(always)] + pub fn region(&self) -> RegionR { + RegionR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Region number."] + #[inline(always)] + pub fn region(&mut self) -> RegionW { + RegionW::new(self, 0) + } +} +#[doc = "Security Attribution Unit Region Number Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rnr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RnrSpec; +impl crate::RegisterSpec for RnrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnr::R`](R) reader structure"] +impl crate::Readable for RnrSpec {} +#[doc = "`write(|w| ..)` method takes [`rnr::W`](W) writer structure"] +impl crate::Writable for RnrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RNR to value 0"] +impl crate::Resettable for RnrSpec {} diff --git a/mcxa276-pac/src/sau/sfar.rs b/mcxa276-pac/src/sau/sfar.rs new file mode 100644 index 000000000..890a7af3c --- /dev/null +++ b/mcxa276-pac/src/sau/sfar.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SFAR` reader"] +pub type R = crate::R; +#[doc = "Register `SFAR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRESS` reader - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] +pub type AddressR = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] +pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] + #[inline(always)] + pub fn address(&mut self) -> AddressW { + AddressW::new(self, 0) + } +} +#[doc = "Secure Fault Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SfarSpec; +impl crate::RegisterSpec for SfarSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sfar::R`](R) reader structure"] +impl crate::Readable for SfarSpec {} +#[doc = "`write(|w| ..)` method takes [`sfar::W`](W) writer structure"] +impl crate::Writable for SfarSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SFAR to value 0"] +impl crate::Resettable for SfarSpec {} diff --git a/mcxa276-pac/src/sau/sfsr.rs b/mcxa276-pac/src/sau/sfsr.rs new file mode 100644 index 000000000..fa65cbc92 --- /dev/null +++ b/mcxa276-pac/src/sau/sfsr.rs @@ -0,0 +1,525 @@ +#[doc = "Register `SFSR` reader"] +pub type R = crate::R; +#[doc = "Register `SFSR` writer"] +pub type W = crate::W; +#[doc = "Invalid entry point.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Invep { + #[doc = "0: Error has not occurred."] + NoError = 0, + #[doc = "1: Error has occurred."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Invep) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INVEP` reader - Invalid entry point."] +pub type InvepR = crate::BitReader; +impl InvepR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Invep { + match self.bits { + false => Invep::NoError, + true => Invep::Error, + } + } + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Invep::NoError + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Invep::Error + } +} +#[doc = "Field `INVEP` writer - Invalid entry point."] +pub type InvepW<'a, REG> = crate::BitWriter<'a, REG, Invep>; +impl<'a, REG> InvepW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Invep::NoError) + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Invep::Error) + } +} +#[doc = "Invalid integrity signature flag.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Invis { + #[doc = "0: Error has not occurred."] + NoError = 0, + #[doc = "1: Error has occurred."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Invis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INVIS` reader - Invalid integrity signature flag."] +pub type InvisR = crate::BitReader; +impl InvisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Invis { + match self.bits { + false => Invis::NoError, + true => Invis::Error, + } + } + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Invis::NoError + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Invis::Error + } +} +#[doc = "Field `INVIS` writer - Invalid integrity signature flag."] +pub type InvisW<'a, REG> = crate::BitWriter<'a, REG, Invis>; +impl<'a, REG> InvisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Invis::NoError) + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Invis::Error) + } +} +#[doc = "Invalid exception return flag.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Inver { + #[doc = "0: Error has not occurred."] + NoError = 0, + #[doc = "1: Error has occurred."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Inver) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INVER` reader - Invalid exception return flag."] +pub type InverR = crate::BitReader; +impl InverR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Inver { + match self.bits { + false => Inver::NoError, + true => Inver::Error, + } + } + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Inver::NoError + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Inver::Error + } +} +#[doc = "Field `INVER` writer - Invalid exception return flag."] +pub type InverW<'a, REG> = crate::BitWriter<'a, REG, Inver>; +impl<'a, REG> InverW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Inver::NoError) + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Inver::Error) + } +} +#[doc = "Attribution unit violation flag.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Auviol { + #[doc = "0: Error has not occurred."] + NoError = 0, + #[doc = "1: Error has occurred."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Auviol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AUVIOL` reader - Attribution unit violation flag."] +pub type AuviolR = crate::BitReader; +impl AuviolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Auviol { + match self.bits { + false => Auviol::NoError, + true => Auviol::Error, + } + } + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Auviol::NoError + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Auviol::Error + } +} +#[doc = "Field `AUVIOL` writer - Attribution unit violation flag."] +pub type AuviolW<'a, REG> = crate::BitWriter<'a, REG, Auviol>; +impl<'a, REG> AuviolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Auviol::NoError) + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Auviol::Error) + } +} +#[doc = "Invalid transition flag.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Invtran { + #[doc = "0: Error has not occurred."] + NoError = 0, + #[doc = "1: Error has occurred."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Invtran) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INVTRAN` reader - Invalid transition flag."] +pub type InvtranR = crate::BitReader; +impl InvtranR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Invtran { + match self.bits { + false => Invtran::NoError, + true => Invtran::Error, + } + } + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Invtran::NoError + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Invtran::Error + } +} +#[doc = "Field `INVTRAN` writer - Invalid transition flag."] +pub type InvtranW<'a, REG> = crate::BitWriter<'a, REG, Invtran>; +impl<'a, REG> InvtranW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Invtran::NoError) + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Invtran::Error) + } +} +#[doc = "Lazy state preservation error flag.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lsperr { + #[doc = "0: Error has not occurred."] + NoError = 0, + #[doc = "1: Error has occurred."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lsperr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LSPERR` reader - Lazy state preservation error flag."] +pub type LsperrR = crate::BitReader; +impl LsperrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lsperr { + match self.bits { + false => Lsperr::NoError, + true => Lsperr::Error, + } + } + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Lsperr::NoError + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Lsperr::Error + } +} +#[doc = "Field `LSPERR` writer - Lazy state preservation error flag."] +pub type LsperrW<'a, REG> = crate::BitWriter<'a, REG, Lsperr>; +impl<'a, REG> LsperrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error has not occurred."] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Lsperr::NoError) + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Lsperr::Error) + } +} +#[doc = "Secure fault address valid.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sfarvalid { + #[doc = "0: SFAR content not valid."] + NotValid = 0, + #[doc = "1: SFAR content valid."] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sfarvalid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SFARVALID` reader - Secure fault address valid."] +pub type SfarvalidR = crate::BitReader; +impl SfarvalidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sfarvalid { + match self.bits { + false => Sfarvalid::NotValid, + true => Sfarvalid::Valid, + } + } + #[doc = "SFAR content not valid."] + #[inline(always)] + pub fn is_not_valid(&self) -> bool { + *self == Sfarvalid::NotValid + } + #[doc = "SFAR content valid."] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Sfarvalid::Valid + } +} +#[doc = "Field `SFARVALID` writer - Secure fault address valid."] +pub type SfarvalidW<'a, REG> = crate::BitWriter<'a, REG, Sfarvalid>; +impl<'a, REG> SfarvalidW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SFAR content not valid."] + #[inline(always)] + pub fn not_valid(self) -> &'a mut crate::W { + self.variant(Sfarvalid::NotValid) + } + #[doc = "SFAR content valid."] + #[inline(always)] + pub fn valid(self) -> &'a mut crate::W { + self.variant(Sfarvalid::Valid) + } +} +#[doc = "Lazy state error flag.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lserr { + #[doc = "0: Error has not occurred"] + NoError = 0, + #[doc = "1: Error has occurred."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lserr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LSERR` reader - Lazy state error flag."] +pub type LserrR = crate::BitReader; +impl LserrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lserr { + match self.bits { + false => Lserr::NoError, + true => Lserr::Error, + } + } + #[doc = "Error has not occurred"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Lserr::NoError + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Lserr::Error + } +} +#[doc = "Field `LSERR` writer - Lazy state error flag."] +pub type LserrW<'a, REG> = crate::BitWriter<'a, REG, Lserr>; +impl<'a, REG> LserrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error has not occurred"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Lserr::NoError) + } + #[doc = "Error has occurred."] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Lserr::Error) + } +} +impl R { + #[doc = "Bit 0 - Invalid entry point."] + #[inline(always)] + pub fn invep(&self) -> InvepR { + InvepR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Invalid integrity signature flag."] + #[inline(always)] + pub fn invis(&self) -> InvisR { + InvisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Invalid exception return flag."] + #[inline(always)] + pub fn inver(&self) -> InverR { + InverR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Attribution unit violation flag."] + #[inline(always)] + pub fn auviol(&self) -> AuviolR { + AuviolR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Invalid transition flag."] + #[inline(always)] + pub fn invtran(&self) -> InvtranR { + InvtranR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Lazy state preservation error flag."] + #[inline(always)] + pub fn lsperr(&self) -> LsperrR { + LsperrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Secure fault address valid."] + #[inline(always)] + pub fn sfarvalid(&self) -> SfarvalidR { + SfarvalidR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Lazy state error flag."] + #[inline(always)] + pub fn lserr(&self) -> LserrR { + LserrR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Invalid entry point."] + #[inline(always)] + pub fn invep(&mut self) -> InvepW { + InvepW::new(self, 0) + } + #[doc = "Bit 1 - Invalid integrity signature flag."] + #[inline(always)] + pub fn invis(&mut self) -> InvisW { + InvisW::new(self, 1) + } + #[doc = "Bit 2 - Invalid exception return flag."] + #[inline(always)] + pub fn inver(&mut self) -> InverW { + InverW::new(self, 2) + } + #[doc = "Bit 3 - Attribution unit violation flag."] + #[inline(always)] + pub fn auviol(&mut self) -> AuviolW { + AuviolW::new(self, 3) + } + #[doc = "Bit 4 - Invalid transition flag."] + #[inline(always)] + pub fn invtran(&mut self) -> InvtranW { + InvtranW::new(self, 4) + } + #[doc = "Bit 5 - Lazy state preservation error flag."] + #[inline(always)] + pub fn lsperr(&mut self) -> LsperrW { + LsperrW::new(self, 5) + } + #[doc = "Bit 6 - Secure fault address valid."] + #[inline(always)] + pub fn sfarvalid(&mut self) -> SfarvalidW { + SfarvalidW::new(self, 6) + } + #[doc = "Bit 7 - Lazy state error flag."] + #[inline(always)] + pub fn lserr(&mut self) -> LserrW { + LserrW::new(self, 7) + } +} +#[doc = "Secure Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SfsrSpec; +impl crate::RegisterSpec for SfsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sfsr::R`](R) reader structure"] +impl crate::Readable for SfsrSpec {} +#[doc = "`write(|w| ..)` method takes [`sfsr::W`](W) writer structure"] +impl crate::Writable for SfsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SFSR to value 0"] +impl crate::Resettable for SfsrSpec {} diff --git a/mcxa276-pac/src/sau/type_.rs b/mcxa276-pac/src/sau/type_.rs new file mode 100644 index 000000000..b2d43fd12 --- /dev/null +++ b/mcxa276-pac/src/sau/type_.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `SREGION` reader - SAU regions. The number of implemented SAU regions."] +pub type SregionR = crate::FieldReader; +#[doc = "Field `SREGION` writer - SAU regions. The number of implemented SAU regions."] +pub type SregionW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - SAU regions. The number of implemented SAU regions."] + #[inline(always)] + pub fn sregion(&self) -> SregionR { + SregionR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SAU regions. The number of implemented SAU regions."] + #[inline(always)] + pub fn sregion(&mut self) -> SregionW { + SregionW::new(self, 0) + } +} +#[doc = "Security Attribution Unit Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`type_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`type_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TypeSpec; +impl crate::RegisterSpec for TypeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`type_::R`](R) reader structure"] +impl crate::Readable for TypeSpec {} +#[doc = "`write(|w| ..)` method takes [`type_::W`](W) writer structure"] +impl crate::Writable for TypeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TYPE to value 0"] +impl crate::Resettable for TypeSpec {} diff --git a/mcxa276-pac/src/scg0.rs b/mcxa276-pac/src/scg0.rs new file mode 100644 index 000000000..6a4d7ba37 --- /dev/null +++ b/mcxa276-pac/src/scg0.rs @@ -0,0 +1,305 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + trim_lock: TrimLock, + _reserved3: [u8; 0x04], + csr: Csr, + rccr: Rccr, + _reserved5: [u8; 0xe8], + sosccsr: Sosccsr, + _reserved6: [u8; 0x04], + sosccfg: Sosccfg, + _reserved7: [u8; 0xf4], + sirccsr: Sirccsr, + _reserved8: [u8; 0x08], + sirctcfg: Sirctcfg, + sirctrim: Sirctrim, + _reserved10: [u8; 0x04], + sircstat: Sircstat, + _reserved11: [u8; 0xe4], + firccsr: Firccsr, + _reserved12: [u8; 0x04], + firccfg: Firccfg, + _reserved13: [u8; 0x04], + firctrim: Firctrim, + _reserved14: [u8; 0xec], + rosccsr: Rosccsr, + _reserved15: [u8; 0x01fc], + spllcsr: Spllcsr, + spllctrl: Spllctrl, + spllstat: Spllstat, + spllndiv: Spllndiv, + spllmdiv: Spllmdiv, + spllpdiv: Spllpdiv, + splllock_cnfg: SplllockCnfg, + _reserved22: [u8; 0x04], + spllsscgstat: Spllsscgstat, + spllsscg0: Spllsscg0, + spllsscg1: Spllsscg1, + _reserved25: [u8; 0x01d4], + ldocsr: Ldocsr, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID Register"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter Register"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x08 - Trim Lock register"] + #[inline(always)] + pub const fn trim_lock(&self) -> &TrimLock { + &self.trim_lock + } + #[doc = "0x10 - Clock Status Register"] + #[inline(always)] + pub const fn csr(&self) -> &Csr { + &self.csr + } + #[doc = "0x14 - Run Clock Control Register"] + #[inline(always)] + pub const fn rccr(&self) -> &Rccr { + &self.rccr + } + #[doc = "0x100 - SOSC Control Status Register"] + #[inline(always)] + pub const fn sosccsr(&self) -> &Sosccsr { + &self.sosccsr + } + #[doc = "0x108 - SOSC Configuration Register"] + #[inline(always)] + pub const fn sosccfg(&self) -> &Sosccfg { + &self.sosccfg + } + #[doc = "0x200 - SIRC Control Status Register"] + #[inline(always)] + pub const fn sirccsr(&self) -> &Sirccsr { + &self.sirccsr + } + #[doc = "0x20c - SIRC Trim Configuration Register"] + #[inline(always)] + pub const fn sirctcfg(&self) -> &Sirctcfg { + &self.sirctcfg + } + #[doc = "0x210 - SIRC Trim Register"] + #[inline(always)] + pub const fn sirctrim(&self) -> &Sirctrim { + &self.sirctrim + } + #[doc = "0x218 - SIRC Auto-trimming Status Register"] + #[inline(always)] + pub const fn sircstat(&self) -> &Sircstat { + &self.sircstat + } + #[doc = "0x300 - FIRC Control Status Register"] + #[inline(always)] + pub const fn firccsr(&self) -> &Firccsr { + &self.firccsr + } + #[doc = "0x308 - FIRC Configuration Register"] + #[inline(always)] + pub const fn firccfg(&self) -> &Firccfg { + &self.firccfg + } + #[doc = "0x310 - FIRC Trim Register"] + #[inline(always)] + pub const fn firctrim(&self) -> &Firctrim { + &self.firctrim + } + #[doc = "0x400 - ROSC Control Status Register"] + #[inline(always)] + pub const fn rosccsr(&self) -> &Rosccsr { + &self.rosccsr + } + #[doc = "0x600 - SPLL Control Status Register"] + #[inline(always)] + pub const fn spllcsr(&self) -> &Spllcsr { + &self.spllcsr + } + #[doc = "0x604 - SPLL Control Register"] + #[inline(always)] + pub const fn spllctrl(&self) -> &Spllctrl { + &self.spllctrl + } + #[doc = "0x608 - SPLL Status Register"] + #[inline(always)] + pub const fn spllstat(&self) -> &Spllstat { + &self.spllstat + } + #[doc = "0x60c - SPLL N Divider Register"] + #[inline(always)] + pub const fn spllndiv(&self) -> &Spllndiv { + &self.spllndiv + } + #[doc = "0x610 - SPLL M Divider Register"] + #[inline(always)] + pub const fn spllmdiv(&self) -> &Spllmdiv { + &self.spllmdiv + } + #[doc = "0x614 - SPLL P Divider Register"] + #[inline(always)] + pub const fn spllpdiv(&self) -> &Spllpdiv { + &self.spllpdiv + } + #[doc = "0x618 - SPLL LOCK Configuration Register"] + #[inline(always)] + pub const fn splllock_cnfg(&self) -> &SplllockCnfg { + &self.splllock_cnfg + } + #[doc = "0x620 - SPLL SSCG Status Register"] + #[inline(always)] + pub const fn spllsscgstat(&self) -> &Spllsscgstat { + &self.spllsscgstat + } + #[doc = "0x624 - SPLL Spread Spectrum Control 0 Register"] + #[inline(always)] + pub const fn spllsscg0(&self) -> &Spllsscg0 { + &self.spllsscg0 + } + #[doc = "0x628 - SPLL Spread Spectrum Control 1 Register"] + #[inline(always)] + pub const fn spllsscg1(&self) -> &Spllsscg1 { + &self.spllsscg1 + } + #[doc = "0x800 - LDO Control and Status Register"] + #[inline(always)] + pub const fn ldocsr(&self) -> &Ldocsr { + &self.ldocsr + } +} +#[doc = "VERID (r) register accessor: Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID Register"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter Register"] +pub mod param; +#[doc = "TRIM_LOCK (rw) register accessor: Trim Lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`trim_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trim_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trim_lock`] module"] +#[doc(alias = "TRIM_LOCK")] +pub type TrimLock = crate::Reg; +#[doc = "Trim Lock register"] +pub mod trim_lock; +#[doc = "CSR (r) register accessor: Clock Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`] module"] +#[doc(alias = "CSR")] +pub type Csr = crate::Reg; +#[doc = "Clock Status Register"] +pub mod csr; +#[doc = "RCCR (rw) register accessor: Run Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rccr`] module"] +#[doc(alias = "RCCR")] +pub type Rccr = crate::Reg; +#[doc = "Run Clock Control Register"] +pub mod rccr; +#[doc = "SOSCCSR (rw) register accessor: SOSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sosccsr`] module"] +#[doc(alias = "SOSCCSR")] +pub type Sosccsr = crate::Reg; +#[doc = "SOSC Control Status Register"] +pub mod sosccsr; +#[doc = "SOSCCFG (rw) register accessor: SOSC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sosccfg`] module"] +#[doc(alias = "SOSCCFG")] +pub type Sosccfg = crate::Reg; +#[doc = "SOSC Configuration Register"] +pub mod sosccfg; +#[doc = "SIRCCSR (rw) register accessor: SIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sirccsr`] module"] +#[doc(alias = "SIRCCSR")] +pub type Sirccsr = crate::Reg; +#[doc = "SIRC Control Status Register"] +pub mod sirccsr; +#[doc = "SIRCTCFG (rw) register accessor: SIRC Trim Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sirctcfg`] module"] +#[doc(alias = "SIRCTCFG")] +pub type Sirctcfg = crate::Reg; +#[doc = "SIRC Trim Configuration Register"] +pub mod sirctcfg; +#[doc = "SIRCTRIM (rw) register accessor: SIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sirctrim`] module"] +#[doc(alias = "SIRCTRIM")] +pub type Sirctrim = crate::Reg; +#[doc = "SIRC Trim Register"] +pub mod sirctrim; +#[doc = "SIRCSTAT (rw) register accessor: SIRC Auto-trimming Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sircstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sircstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sircstat`] module"] +#[doc(alias = "SIRCSTAT")] +pub type Sircstat = crate::Reg; +#[doc = "SIRC Auto-trimming Status Register"] +pub mod sircstat; +#[doc = "FIRCCSR (rw) register accessor: FIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@firccsr`] module"] +#[doc(alias = "FIRCCSR")] +pub type Firccsr = crate::Reg; +#[doc = "FIRC Control Status Register"] +pub mod firccsr; +#[doc = "FIRCCFG (rw) register accessor: FIRC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@firccfg`] module"] +#[doc(alias = "FIRCCFG")] +pub type Firccfg = crate::Reg; +#[doc = "FIRC Configuration Register"] +pub mod firccfg; +#[doc = "FIRCTRIM (rw) register accessor: FIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firctrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firctrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@firctrim`] module"] +#[doc(alias = "FIRCTRIM")] +pub type Firctrim = crate::Reg; +#[doc = "FIRC Trim Register"] +pub mod firctrim; +#[doc = "ROSCCSR (rw) register accessor: ROSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rosccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rosccsr`] module"] +#[doc(alias = "ROSCCSR")] +pub type Rosccsr = crate::Reg; +#[doc = "ROSC Control Status Register"] +pub mod rosccsr; +#[doc = "SPLLCSR (rw) register accessor: SPLL Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllcsr`] module"] +#[doc(alias = "SPLLCSR")] +pub type Spllcsr = crate::Reg; +#[doc = "SPLL Control Status Register"] +pub mod spllcsr; +#[doc = "SPLLCTRL (rw) register accessor: SPLL Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllctrl`] module"] +#[doc(alias = "SPLLCTRL")] +pub type Spllctrl = crate::Reg; +#[doc = "SPLL Control Register"] +pub mod spllctrl; +#[doc = "SPLLSTAT (r) register accessor: SPLL Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllstat`] module"] +#[doc(alias = "SPLLSTAT")] +pub type Spllstat = crate::Reg; +#[doc = "SPLL Status Register"] +pub mod spllstat; +#[doc = "SPLLNDIV (rw) register accessor: SPLL N Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllndiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllndiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllndiv`] module"] +#[doc(alias = "SPLLNDIV")] +pub type Spllndiv = crate::Reg; +#[doc = "SPLL N Divider Register"] +pub mod spllndiv; +#[doc = "SPLLMDIV (rw) register accessor: SPLL M Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllmdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllmdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllmdiv`] module"] +#[doc(alias = "SPLLMDIV")] +pub type Spllmdiv = crate::Reg; +#[doc = "SPLL M Divider Register"] +pub mod spllmdiv; +#[doc = "SPLLPDIV (rw) register accessor: SPLL P Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllpdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllpdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllpdiv`] module"] +#[doc(alias = "SPLLPDIV")] +pub type Spllpdiv = crate::Reg; +#[doc = "SPLL P Divider Register"] +pub mod spllpdiv; +#[doc = "SPLLLOCK_CNFG (rw) register accessor: SPLL LOCK Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`splllock_cnfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`splllock_cnfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@splllock_cnfg`] module"] +#[doc(alias = "SPLLLOCK_CNFG")] +pub type SplllockCnfg = crate::Reg; +#[doc = "SPLL LOCK Configuration Register"] +pub mod splllock_cnfg; +#[doc = "SPLLSSCGSTAT (r) register accessor: SPLL SSCG Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscgstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllsscgstat`] module"] +#[doc(alias = "SPLLSSCGSTAT")] +pub type Spllsscgstat = crate::Reg; +#[doc = "SPLL SSCG Status Register"] +pub mod spllsscgstat; +#[doc = "SPLLSSCG0 (rw) register accessor: SPLL Spread Spectrum Control 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllsscg0`] module"] +#[doc(alias = "SPLLSSCG0")] +pub type Spllsscg0 = crate::Reg; +#[doc = "SPLL Spread Spectrum Control 0 Register"] +pub mod spllsscg0; +#[doc = "SPLLSSCG1 (rw) register accessor: SPLL Spread Spectrum Control 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllsscg1`] module"] +#[doc(alias = "SPLLSSCG1")] +pub type Spllsscg1 = crate::Reg; +#[doc = "SPLL Spread Spectrum Control 1 Register"] +pub mod spllsscg1; +#[doc = "LDOCSR (rw) register accessor: LDO Control and Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ldocsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ldocsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ldocsr`] module"] +#[doc(alias = "LDOCSR")] +pub type Ldocsr = crate::Reg; +#[doc = "LDO Control and Status Register"] +pub mod ldocsr; diff --git a/mcxa276-pac/src/scg0/csr.rs b/mcxa276-pac/src/scg0/csr.rs new file mode 100644 index 000000000..5bf2179c0 --- /dev/null +++ b/mcxa276-pac/src/scg0/csr.rs @@ -0,0 +1,86 @@ +#[doc = "Register `CSR` reader"] +pub type R = crate::R; +#[doc = "System Clock Source\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Scs { + #[doc = "1: SOSC"] + Sosc = 1, + #[doc = "2: SIRC"] + Sirc = 2, + #[doc = "3: FIRC"] + Firc = 3, + #[doc = "4: ROSC"] + Rosc = 4, + #[doc = "6: SPLL"] + Spll = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Scs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Scs { + type Ux = u8; +} +impl crate::IsEnum for Scs {} +#[doc = "Field `SCS` reader - System Clock Source"] +pub type ScsR = crate::FieldReader; +impl ScsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Scs::Sosc), + 2 => Some(Scs::Sirc), + 3 => Some(Scs::Firc), + 4 => Some(Scs::Rosc), + 6 => Some(Scs::Spll), + _ => None, + } + } + #[doc = "SOSC"] + #[inline(always)] + pub fn is_sosc(&self) -> bool { + *self == Scs::Sosc + } + #[doc = "SIRC"] + #[inline(always)] + pub fn is_sirc(&self) -> bool { + *self == Scs::Sirc + } + #[doc = "FIRC"] + #[inline(always)] + pub fn is_firc(&self) -> bool { + *self == Scs::Firc + } + #[doc = "ROSC"] + #[inline(always)] + pub fn is_rosc(&self) -> bool { + *self == Scs::Rosc + } + #[doc = "SPLL"] + #[inline(always)] + pub fn is_spll(&self) -> bool { + *self == Scs::Spll + } +} +impl R { + #[doc = "Bits 24:26 - System Clock Source"] + #[inline(always)] + pub fn scs(&self) -> ScsR { + ScsR::new(((self.bits >> 24) & 7) as u8) + } +} +#[doc = "Clock Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CsrSpec; +impl crate::RegisterSpec for CsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CsrSpec {} +#[doc = "`reset()` method sets CSR to value 0x0300_0000"] +impl crate::Resettable for CsrSpec { + const RESET_VALUE: u32 = 0x0300_0000; +} diff --git a/mcxa276-pac/src/scg0/firccfg.rs b/mcxa276-pac/src/scg0/firccfg.rs new file mode 100644 index 000000000..c476bcdaf --- /dev/null +++ b/mcxa276-pac/src/scg0/firccfg.rs @@ -0,0 +1,119 @@ +#[doc = "Register `FIRCCFG` reader"] +pub type R = crate::R; +#[doc = "Register `FIRCCFG` writer"] +pub type W = crate::W; +#[doc = "Frequency select\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FreqSel { + #[doc = "1: 45 MHz FIRC clock selected, divided from 180 MHz"] + Firc48mhz192s = 1, + #[doc = "3: 60 MHz FIRC clock selected"] + Firc64mhz = 3, + #[doc = "5: 90 MHz FIRC clock selected"] + Firc96mhz = 5, + #[doc = "7: 180 MHz FIRC clock selected"] + Firc192mhz = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FreqSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FreqSel { + type Ux = u8; +} +impl crate::IsEnum for FreqSel {} +#[doc = "Field `FREQ_SEL` reader - Frequency select"] +pub type FreqSelR = crate::FieldReader; +impl FreqSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(FreqSel::Firc48mhz192s), + 3 => Some(FreqSel::Firc64mhz), + 5 => Some(FreqSel::Firc96mhz), + 7 => Some(FreqSel::Firc192mhz), + _ => None, + } + } + #[doc = "45 MHz FIRC clock selected, divided from 180 MHz"] + #[inline(always)] + pub fn is_firc_48mhz_192s(&self) -> bool { + *self == FreqSel::Firc48mhz192s + } + #[doc = "60 MHz FIRC clock selected"] + #[inline(always)] + pub fn is_firc_64mhz(&self) -> bool { + *self == FreqSel::Firc64mhz + } + #[doc = "90 MHz FIRC clock selected"] + #[inline(always)] + pub fn is_firc_96mhz(&self) -> bool { + *self == FreqSel::Firc96mhz + } + #[doc = "180 MHz FIRC clock selected"] + #[inline(always)] + pub fn is_firc_192mhz(&self) -> bool { + *self == FreqSel::Firc192mhz + } +} +#[doc = "Field `FREQ_SEL` writer - Frequency select"] +pub type FreqSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, FreqSel>; +impl<'a, REG> FreqSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "45 MHz FIRC clock selected, divided from 180 MHz"] + #[inline(always)] + pub fn firc_48mhz_192s(self) -> &'a mut crate::W { + self.variant(FreqSel::Firc48mhz192s) + } + #[doc = "60 MHz FIRC clock selected"] + #[inline(always)] + pub fn firc_64mhz(self) -> &'a mut crate::W { + self.variant(FreqSel::Firc64mhz) + } + #[doc = "90 MHz FIRC clock selected"] + #[inline(always)] + pub fn firc_96mhz(self) -> &'a mut crate::W { + self.variant(FreqSel::Firc96mhz) + } + #[doc = "180 MHz FIRC clock selected"] + #[inline(always)] + pub fn firc_192mhz(self) -> &'a mut crate::W { + self.variant(FreqSel::Firc192mhz) + } +} +impl R { + #[doc = "Bits 1:3 - Frequency select"] + #[inline(always)] + pub fn freq_sel(&self) -> FreqSelR { + FreqSelR::new(((self.bits >> 1) & 7) as u8) + } +} +impl W { + #[doc = "Bits 1:3 - Frequency select"] + #[inline(always)] + pub fn freq_sel(&mut self) -> FreqSelW { + FreqSelW::new(self, 1) + } +} +#[doc = "FIRC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FirccfgSpec; +impl crate::RegisterSpec for FirccfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`firccfg::R`](R) reader structure"] +impl crate::Readable for FirccfgSpec {} +#[doc = "`write(|w| ..)` method takes [`firccfg::W`](W) writer structure"] +impl crate::Writable for FirccfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIRCCFG to value 0x03"] +impl crate::Resettable for FirccfgSpec { + const RESET_VALUE: u32 = 0x03; +} diff --git a/mcxa276-pac/src/scg0/firccsr.rs b/mcxa276-pac/src/scg0/firccsr.rs new file mode 100644 index 000000000..ec27bf643 --- /dev/null +++ b/mcxa276-pac/src/scg0/firccsr.rs @@ -0,0 +1,651 @@ +#[doc = "Register `FIRCCSR` reader"] +pub type R = crate::R; +#[doc = "Register `FIRCCSR` writer"] +pub type W = crate::W; +#[doc = "FIRC Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fircen { + #[doc = "0: FIRC is disabled"] + Disabled = 0, + #[doc = "1: FIRC is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fircen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCEN` reader - FIRC Enable"] +pub type FircenR = crate::BitReader; +impl FircenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fircen { + match self.bits { + false => Fircen::Disabled, + true => Fircen::Enabled, + } + } + #[doc = "FIRC is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Fircen::Disabled + } + #[doc = "FIRC is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Fircen::Enabled + } +} +#[doc = "Field `FIRCEN` writer - FIRC Enable"] +pub type FircenW<'a, REG> = crate::BitWriter<'a, REG, Fircen>; +impl<'a, REG> FircenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FIRC is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fircen::Disabled) + } + #[doc = "FIRC is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fircen::Enabled) + } +} +#[doc = "FIRC Stop Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fircsten { + #[doc = "0: FIRC is disabled in Deep Sleep mode"] + DisabledInStopModes = 0, + #[doc = "1: FIRC is enabled in Deep Sleep mode"] + EnabledInStopModes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fircsten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCSTEN` reader - FIRC Stop Enable"] +pub type FircstenR = crate::BitReader; +impl FircstenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fircsten { + match self.bits { + false => Fircsten::DisabledInStopModes, + true => Fircsten::EnabledInStopModes, + } + } + #[doc = "FIRC is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn is_disabled_in_stop_modes(&self) -> bool { + *self == Fircsten::DisabledInStopModes + } + #[doc = "FIRC is enabled in Deep Sleep mode"] + #[inline(always)] + pub fn is_enabled_in_stop_modes(&self) -> bool { + *self == Fircsten::EnabledInStopModes + } +} +#[doc = "Field `FIRCSTEN` writer - FIRC Stop Enable"] +pub type FircstenW<'a, REG> = crate::BitWriter<'a, REG, Fircsten>; +impl<'a, REG> FircstenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FIRC is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn disabled_in_stop_modes(self) -> &'a mut crate::W { + self.variant(Fircsten::DisabledInStopModes) + } + #[doc = "FIRC is enabled in Deep Sleep mode"] + #[inline(always)] + pub fn enabled_in_stop_modes(self) -> &'a mut crate::W { + self.variant(Fircsten::EnabledInStopModes) + } +} +#[doc = "FIRC 45 MHz Clock to peripherals Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FircSclkPeriphEn { + #[doc = "0: FIRC 45 MHz to peripherals is disabled"] + Disabled = 0, + #[doc = "1: FIRC 45 MHz to peripherals is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FircSclkPeriphEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRC_SCLK_PERIPH_EN` reader - FIRC 45 MHz Clock to peripherals Enable"] +pub type FircSclkPeriphEnR = crate::BitReader; +impl FircSclkPeriphEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FircSclkPeriphEn { + match self.bits { + false => FircSclkPeriphEn::Disabled, + true => FircSclkPeriphEn::Enabled, + } + } + #[doc = "FIRC 45 MHz to peripherals is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == FircSclkPeriphEn::Disabled + } + #[doc = "FIRC 45 MHz to peripherals is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == FircSclkPeriphEn::Enabled + } +} +#[doc = "Field `FIRC_SCLK_PERIPH_EN` writer - FIRC 45 MHz Clock to peripherals Enable"] +pub type FircSclkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, FircSclkPeriphEn>; +impl<'a, REG> FircSclkPeriphEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FIRC 45 MHz to peripherals is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(FircSclkPeriphEn::Disabled) + } + #[doc = "FIRC 45 MHz to peripherals is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(FircSclkPeriphEn::Enabled) + } +} +#[doc = "FRO_HF Clock to peripherals Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FircFclkPeriphEn { + #[doc = "0: FRO_HF to peripherals is disabled"] + Disabled = 0, + #[doc = "1: FRO_HF to peripherals is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FircFclkPeriphEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRC_FCLK_PERIPH_EN` reader - FRO_HF Clock to peripherals Enable"] +pub type FircFclkPeriphEnR = crate::BitReader; +impl FircFclkPeriphEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FircFclkPeriphEn { + match self.bits { + false => FircFclkPeriphEn::Disabled, + true => FircFclkPeriphEn::Enabled, + } + } + #[doc = "FRO_HF to peripherals is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == FircFclkPeriphEn::Disabled + } + #[doc = "FRO_HF to peripherals is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == FircFclkPeriphEn::Enabled + } +} +#[doc = "Field `FIRC_FCLK_PERIPH_EN` writer - FRO_HF Clock to peripherals Enable"] +pub type FircFclkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, FircFclkPeriphEn>; +impl<'a, REG> FircFclkPeriphEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FRO_HF to peripherals is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(FircFclkPeriphEn::Disabled) + } + #[doc = "FRO_HF to peripherals is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(FircFclkPeriphEn::Enabled) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Control Status Register can be written"] + WriteEnabled = 0, + #[doc = "1: Control Status Register cannot be written"] + WriteDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::WriteEnabled, + true => Lk::WriteDisabled, + } + } + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn is_write_enabled(&self) -> bool { + *self == Lk::WriteEnabled + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn is_write_disabled(&self) -> bool { + *self == Lk::WriteDisabled + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn write_enabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteEnabled) + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn write_disabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteDisabled) + } +} +#[doc = "FIRC Valid status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fircvld { + #[doc = "0: FIRC is not enabled or clock is not valid."] + NotEnabledOrNotValid = 0, + #[doc = "1: FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog."] + EnabledAndValid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fircvld) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCVLD` reader - FIRC Valid status"] +pub type FircvldR = crate::BitReader; +impl FircvldR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fircvld { + match self.bits { + false => Fircvld::NotEnabledOrNotValid, + true => Fircvld::EnabledAndValid, + } + } + #[doc = "FIRC is not enabled or clock is not valid."] + #[inline(always)] + pub fn is_not_enabled_or_not_valid(&self) -> bool { + *self == Fircvld::NotEnabledOrNotValid + } + #[doc = "FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog."] + #[inline(always)] + pub fn is_enabled_and_valid(&self) -> bool { + *self == Fircvld::EnabledAndValid + } +} +#[doc = "FIRC Selected\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fircsel { + #[doc = "0: FIRC is not the system clock source"] + NotFirc = 0, + #[doc = "1: FIRC is the system clock source"] + Firc = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fircsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCSEL` reader - FIRC Selected"] +pub type FircselR = crate::BitReader; +impl FircselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fircsel { + match self.bits { + false => Fircsel::NotFirc, + true => Fircsel::Firc, + } + } + #[doc = "FIRC is not the system clock source"] + #[inline(always)] + pub fn is_not_firc(&self) -> bool { + *self == Fircsel::NotFirc + } + #[doc = "FIRC is the system clock source"] + #[inline(always)] + pub fn is_firc(&self) -> bool { + *self == Fircsel::Firc + } +} +#[doc = "FIRC Clock Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fircerr { + #[doc = "0: Error not detected with the FIRC trimming"] + ErrorNotDetected = 0, + #[doc = "1: Error detected with the FIRC trimming"] + ErrorDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fircerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCERR` reader - FIRC Clock Error"] +pub type FircerrR = crate::BitReader; +impl FircerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fircerr { + match self.bits { + false => Fircerr::ErrorNotDetected, + true => Fircerr::ErrorDetected, + } + } + #[doc = "Error not detected with the FIRC trimming"] + #[inline(always)] + pub fn is_error_not_detected(&self) -> bool { + *self == Fircerr::ErrorNotDetected + } + #[doc = "Error detected with the FIRC trimming"] + #[inline(always)] + pub fn is_error_detected(&self) -> bool { + *self == Fircerr::ErrorDetected + } +} +#[doc = "Field `FIRCERR` writer - FIRC Clock Error"] +pub type FircerrW<'a, REG> = crate::BitWriter1C<'a, REG, Fircerr>; +impl<'a, REG> FircerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error not detected with the FIRC trimming"] + #[inline(always)] + pub fn error_not_detected(self) -> &'a mut crate::W { + self.variant(Fircerr::ErrorNotDetected) + } + #[doc = "Error detected with the FIRC trimming"] + #[inline(always)] + pub fn error_detected(self) -> &'a mut crate::W { + self.variant(Fircerr::ErrorDetected) + } +} +#[doc = "FIRC Clock Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FircerrIe { + #[doc = "0: FIRCERR interrupt is not enabled"] + ErrorNotDetected = 0, + #[doc = "1: FIRCERR interrupt is enabled"] + ErrorDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FircerrIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCERR_IE` reader - FIRC Clock Error Interrupt Enable"] +pub type FircerrIeR = crate::BitReader; +impl FircerrIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FircerrIe { + match self.bits { + false => FircerrIe::ErrorNotDetected, + true => FircerrIe::ErrorDetected, + } + } + #[doc = "FIRCERR interrupt is not enabled"] + #[inline(always)] + pub fn is_error_not_detected(&self) -> bool { + *self == FircerrIe::ErrorNotDetected + } + #[doc = "FIRCERR interrupt is enabled"] + #[inline(always)] + pub fn is_error_detected(&self) -> bool { + *self == FircerrIe::ErrorDetected + } +} +#[doc = "Field `FIRCERR_IE` writer - FIRC Clock Error Interrupt Enable"] +pub type FircerrIeW<'a, REG> = crate::BitWriter<'a, REG, FircerrIe>; +impl<'a, REG> FircerrIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FIRCERR interrupt is not enabled"] + #[inline(always)] + pub fn error_not_detected(self) -> &'a mut crate::W { + self.variant(FircerrIe::ErrorNotDetected) + } + #[doc = "FIRCERR interrupt is enabled"] + #[inline(always)] + pub fn error_detected(self) -> &'a mut crate::W { + self.variant(FircerrIe::ErrorDetected) + } +} +#[doc = "FIRC Accurate Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FircaccIe { + #[doc = "0: FIRCACC interrupt is not enabled"] + Fircaccnot = 0, + #[doc = "1: FIRCACC interrupt is enabled"] + Fircaccyes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FircaccIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCACC_IE` reader - FIRC Accurate Interrupt Enable"] +pub type FircaccIeR = crate::BitReader; +impl FircaccIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FircaccIe { + match self.bits { + false => FircaccIe::Fircaccnot, + true => FircaccIe::Fircaccyes, + } + } + #[doc = "FIRCACC interrupt is not enabled"] + #[inline(always)] + pub fn is_fircaccnot(&self) -> bool { + *self == FircaccIe::Fircaccnot + } + #[doc = "FIRCACC interrupt is enabled"] + #[inline(always)] + pub fn is_fircaccyes(&self) -> bool { + *self == FircaccIe::Fircaccyes + } +} +#[doc = "Field `FIRCACC_IE` writer - FIRC Accurate Interrupt Enable"] +pub type FircaccIeW<'a, REG> = crate::BitWriter<'a, REG, FircaccIe>; +impl<'a, REG> FircaccIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FIRCACC interrupt is not enabled"] + #[inline(always)] + pub fn fircaccnot(self) -> &'a mut crate::W { + self.variant(FircaccIe::Fircaccnot) + } + #[doc = "FIRCACC interrupt is enabled"] + #[inline(always)] + pub fn fircaccyes(self) -> &'a mut crate::W { + self.variant(FircaccIe::Fircaccyes) + } +} +#[doc = "FIRC Frequency Accurate\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fircacc { + #[doc = "0: FIRC is not enabled or clock is not accurate."] + NotEnabledOrNotValid = 0, + #[doc = "1: FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock."] + EnabledAndValid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fircacc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCACC` reader - FIRC Frequency Accurate"] +pub type FircaccR = crate::BitReader; +impl FircaccR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fircacc { + match self.bits { + false => Fircacc::NotEnabledOrNotValid, + true => Fircacc::EnabledAndValid, + } + } + #[doc = "FIRC is not enabled or clock is not accurate."] + #[inline(always)] + pub fn is_not_enabled_or_not_valid(&self) -> bool { + *self == Fircacc::NotEnabledOrNotValid + } + #[doc = "FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock."] + #[inline(always)] + pub fn is_enabled_and_valid(&self) -> bool { + *self == Fircacc::EnabledAndValid + } +} +impl R { + #[doc = "Bit 0 - FIRC Enable"] + #[inline(always)] + pub fn fircen(&self) -> FircenR { + FircenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIRC Stop Enable"] + #[inline(always)] + pub fn fircsten(&self) -> FircstenR { + FircstenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - FIRC 45 MHz Clock to peripherals Enable"] + #[inline(always)] + pub fn firc_sclk_periph_en(&self) -> FircSclkPeriphEnR { + FircSclkPeriphEnR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - FRO_HF Clock to peripherals Enable"] + #[inline(always)] + pub fn firc_fclk_periph_en(&self) -> FircFclkPeriphEnR { + FircFclkPeriphEnR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - FIRC Valid status"] + #[inline(always)] + pub fn fircvld(&self) -> FircvldR { + FircvldR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - FIRC Selected"] + #[inline(always)] + pub fn fircsel(&self) -> FircselR { + FircselR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - FIRC Clock Error"] + #[inline(always)] + pub fn fircerr(&self) -> FircerrR { + FircerrR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - FIRC Clock Error Interrupt Enable"] + #[inline(always)] + pub fn fircerr_ie(&self) -> FircerrIeR { + FircerrIeR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 30 - FIRC Accurate Interrupt Enable"] + #[inline(always)] + pub fn fircacc_ie(&self) -> FircaccIeR { + FircaccIeR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - FIRC Frequency Accurate"] + #[inline(always)] + pub fn fircacc(&self) -> FircaccR { + FircaccR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FIRC Enable"] + #[inline(always)] + pub fn fircen(&mut self) -> FircenW { + FircenW::new(self, 0) + } + #[doc = "Bit 1 - FIRC Stop Enable"] + #[inline(always)] + pub fn fircsten(&mut self) -> FircstenW { + FircstenW::new(self, 1) + } + #[doc = "Bit 4 - FIRC 45 MHz Clock to peripherals Enable"] + #[inline(always)] + pub fn firc_sclk_periph_en(&mut self) -> FircSclkPeriphEnW { + FircSclkPeriphEnW::new(self, 4) + } + #[doc = "Bit 5 - FRO_HF Clock to peripherals Enable"] + #[inline(always)] + pub fn firc_fclk_periph_en(&mut self) -> FircFclkPeriphEnW { + FircFclkPeriphEnW::new(self, 5) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 23) + } + #[doc = "Bit 26 - FIRC Clock Error"] + #[inline(always)] + pub fn fircerr(&mut self) -> FircerrW { + FircerrW::new(self, 26) + } + #[doc = "Bit 27 - FIRC Clock Error Interrupt Enable"] + #[inline(always)] + pub fn fircerr_ie(&mut self) -> FircerrIeW { + FircerrIeW::new(self, 27) + } + #[doc = "Bit 30 - FIRC Accurate Interrupt Enable"] + #[inline(always)] + pub fn fircacc_ie(&mut self) -> FircaccIeW { + FircaccIeW::new(self, 30) + } +} +#[doc = "FIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FirccsrSpec; +impl crate::RegisterSpec for FirccsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`firccsr::R`](R) reader structure"] +impl crate::Readable for FirccsrSpec {} +#[doc = "`write(|w| ..)` method takes [`firccsr::W`](W) writer structure"] +impl crate::Writable for FirccsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; +} +#[doc = "`reset()` method sets FIRCCSR to value 0x0300_0031"] +impl crate::Resettable for FirccsrSpec { + const RESET_VALUE: u32 = 0x0300_0031; +} diff --git a/mcxa276-pac/src/scg0/firctrim.rs b/mcxa276-pac/src/scg0/firctrim.rs new file mode 100644 index 000000000..213957c35 --- /dev/null +++ b/mcxa276-pac/src/scg0/firctrim.rs @@ -0,0 +1,77 @@ +#[doc = "Register `FIRCTRIM` reader"] +pub type R = crate::R; +#[doc = "Register `FIRCTRIM` writer"] +pub type W = crate::W; +#[doc = "Field `TRIMFINE` reader - Trim Fine"] +pub type TrimfineR = crate::FieldReader; +#[doc = "Field `TRIMFINE` writer - Trim Fine"] +pub type TrimfineW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TRIMCOAR` reader - Trim Coarse"] +pub type TrimcoarR = crate::FieldReader; +#[doc = "Field `TRIMCOAR` writer - Trim Coarse"] +pub type TrimcoarW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TRIMTEMP` reader - Trim Temperature"] +pub type TrimtempR = crate::FieldReader; +#[doc = "Field `TRIMTEMP` writer - Trim Temperature"] +pub type TrimtempW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TRIMSTART` reader - Trim Start"] +pub type TrimstartR = crate::FieldReader; +#[doc = "Field `TRIMSTART` writer - Trim Start"] +pub type TrimstartW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:7 - Trim Fine"] + #[inline(always)] + pub fn trimfine(&self) -> TrimfineR { + TrimfineR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:13 - Trim Coarse"] + #[inline(always)] + pub fn trimcoar(&self) -> TrimcoarR { + TrimcoarR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:19 - Trim Temperature"] + #[inline(always)] + pub fn trimtemp(&self) -> TrimtempR { + TrimtempR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:29 - Trim Start"] + #[inline(always)] + pub fn trimstart(&self) -> TrimstartR { + TrimstartR::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Trim Fine"] + #[inline(always)] + pub fn trimfine(&mut self) -> TrimfineW { + TrimfineW::new(self, 0) + } + #[doc = "Bits 8:13 - Trim Coarse"] + #[inline(always)] + pub fn trimcoar(&mut self) -> TrimcoarW { + TrimcoarW::new(self, 8) + } + #[doc = "Bits 16:19 - Trim Temperature"] + #[inline(always)] + pub fn trimtemp(&mut self) -> TrimtempW { + TrimtempW::new(self, 16) + } + #[doc = "Bits 24:29 - Trim Start"] + #[inline(always)] + pub fn trimstart(&mut self) -> TrimstartW { + TrimstartW::new(self, 24) + } +} +#[doc = "FIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firctrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firctrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FirctrimSpec; +impl crate::RegisterSpec for FirctrimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`firctrim::R`](R) reader structure"] +impl crate::Readable for FirctrimSpec {} +#[doc = "`write(|w| ..)` method takes [`firctrim::W`](W) writer structure"] +impl crate::Writable for FirctrimSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIRCTRIM to value 0"] +impl crate::Resettable for FirctrimSpec {} diff --git a/mcxa276-pac/src/scg0/ldocsr.rs b/mcxa276-pac/src/scg0/ldocsr.rs new file mode 100644 index 000000000..bdc5169b8 --- /dev/null +++ b/mcxa276-pac/src/scg0/ldocsr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `LDOCSR` reader"] +pub type R = crate::R; +#[doc = "Register `LDOCSR` writer"] +pub type W = crate::W; +#[doc = "LDO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldoen { + #[doc = "0: LDO is disabled"] + Disabled = 0, + #[doc = "1: LDO is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldoen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDOEN` reader - LDO Enable"] +pub type LdoenR = crate::BitReader; +impl LdoenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldoen { + match self.bits { + false => Ldoen::Disabled, + true => Ldoen::Enabled, + } + } + #[doc = "LDO is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ldoen::Disabled + } + #[doc = "LDO is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ldoen::Enabled + } +} +#[doc = "Field `LDOEN` writer - LDO Enable"] +pub type LdoenW<'a, REG> = crate::BitWriter<'a, REG, Ldoen>; +impl<'a, REG> LdoenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "LDO is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ldoen::Disabled) + } + #[doc = "LDO is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ldoen::Enabled) + } +} +#[doc = "LDO output voltage select\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum VoutSel { + #[doc = "0: VOUT = 1V"] + Vout1v1 = 0, + #[doc = "1: VOUT = 1V"] + Vout1v2 = 1, + #[doc = "2: VOUT = 1V"] + Vout1v3 = 2, + #[doc = "3: VOUT = 1.05V"] + Vout105v = 3, + #[doc = "4: VOUT = 1.1V"] + Vout11v = 4, + #[doc = "5: VOUT = 1.15V"] + Vout115v = 5, + #[doc = "6: VOUT = 1.2V"] + Vout12v = 6, + #[doc = "7: VOUT = 1.25V"] + Vout125v = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VoutSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for VoutSel { + type Ux = u8; +} +impl crate::IsEnum for VoutSel {} +#[doc = "Field `VOUT_SEL` reader - LDO output voltage select"] +pub type VoutSelR = crate::FieldReader; +impl VoutSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VoutSel { + match self.bits { + 0 => VoutSel::Vout1v1, + 1 => VoutSel::Vout1v2, + 2 => VoutSel::Vout1v3, + 3 => VoutSel::Vout105v, + 4 => VoutSel::Vout11v, + 5 => VoutSel::Vout115v, + 6 => VoutSel::Vout12v, + 7 => VoutSel::Vout125v, + _ => unreachable!(), + } + } + #[doc = "VOUT = 1V"] + #[inline(always)] + pub fn is_vout_1v_1(&self) -> bool { + *self == VoutSel::Vout1v1 + } + #[doc = "VOUT = 1V"] + #[inline(always)] + pub fn is_vout_1v_2(&self) -> bool { + *self == VoutSel::Vout1v2 + } + #[doc = "VOUT = 1V"] + #[inline(always)] + pub fn is_vout_1v_3(&self) -> bool { + *self == VoutSel::Vout1v3 + } + #[doc = "VOUT = 1.05V"] + #[inline(always)] + pub fn is_vout_105v(&self) -> bool { + *self == VoutSel::Vout105v + } + #[doc = "VOUT = 1.1V"] + #[inline(always)] + pub fn is_vout_11v(&self) -> bool { + *self == VoutSel::Vout11v + } + #[doc = "VOUT = 1.15V"] + #[inline(always)] + pub fn is_vout_115v(&self) -> bool { + *self == VoutSel::Vout115v + } + #[doc = "VOUT = 1.2V"] + #[inline(always)] + pub fn is_vout_12v(&self) -> bool { + *self == VoutSel::Vout12v + } + #[doc = "VOUT = 1.25V"] + #[inline(always)] + pub fn is_vout_125v(&self) -> bool { + *self == VoutSel::Vout125v + } +} +#[doc = "Field `VOUT_SEL` writer - LDO output voltage select"] +pub type VoutSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, VoutSel, crate::Safe>; +impl<'a, REG> VoutSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "VOUT = 1V"] + #[inline(always)] + pub fn vout_1v_1(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout1v1) + } + #[doc = "VOUT = 1V"] + #[inline(always)] + pub fn vout_1v_2(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout1v2) + } + #[doc = "VOUT = 1V"] + #[inline(always)] + pub fn vout_1v_3(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout1v3) + } + #[doc = "VOUT = 1.05V"] + #[inline(always)] + pub fn vout_105v(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout105v) + } + #[doc = "VOUT = 1.1V"] + #[inline(always)] + pub fn vout_11v(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout11v) + } + #[doc = "VOUT = 1.15V"] + #[inline(always)] + pub fn vout_115v(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout115v) + } + #[doc = "VOUT = 1.2V"] + #[inline(always)] + pub fn vout_12v(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout12v) + } + #[doc = "VOUT = 1.25V"] + #[inline(always)] + pub fn vout_125v(self) -> &'a mut crate::W { + self.variant(VoutSel::Vout125v) + } +} +#[doc = "LDO Bypass\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ldobypass { + #[doc = "0: LDO is not bypassed"] + Disabled = 0, + #[doc = "1: LDO is bypassed"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ldobypass) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LDOBYPASS` reader - LDO Bypass"] +pub type LdobypassR = crate::BitReader; +impl LdobypassR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ldobypass { + match self.bits { + false => Ldobypass::Disabled, + true => Ldobypass::Enabled, + } + } + #[doc = "LDO is not bypassed"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ldobypass::Disabled + } + #[doc = "LDO is bypassed"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ldobypass::Enabled + } +} +#[doc = "Field `LDOBYPASS` writer - LDO Bypass"] +pub type LdobypassW<'a, REG> = crate::BitWriter<'a, REG, Ldobypass>; +impl<'a, REG> LdobypassW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "LDO is not bypassed"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Ldobypass::Disabled) + } + #[doc = "LDO is bypassed"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Ldobypass::Enabled) + } +} +#[doc = "LDO VOUT OK Inform.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VoutOk { + #[doc = "0: LDO output VOUT is not OK"] + Disabled = 0, + #[doc = "1: LDO output VOUT is OK"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VoutOk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VOUT_OK` reader - LDO VOUT OK Inform."] +pub type VoutOkR = crate::BitReader; +impl VoutOkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VoutOk { + match self.bits { + false => VoutOk::Disabled, + true => VoutOk::Enabled, + } + } + #[doc = "LDO output VOUT is not OK"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == VoutOk::Disabled + } + #[doc = "LDO output VOUT is OK"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == VoutOk::Enabled + } +} +impl R { + #[doc = "Bit 0 - LDO Enable"] + #[inline(always)] + pub fn ldoen(&self) -> LdoenR { + LdoenR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - LDO output voltage select"] + #[inline(always)] + pub fn vout_sel(&self) -> VoutSelR { + VoutSelR::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - LDO Bypass"] + #[inline(always)] + pub fn ldobypass(&self) -> LdobypassR { + LdobypassR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 31 - LDO VOUT OK Inform."] + #[inline(always)] + pub fn vout_ok(&self) -> VoutOkR { + VoutOkR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LDO Enable"] + #[inline(always)] + pub fn ldoen(&mut self) -> LdoenW { + LdoenW::new(self, 0) + } + #[doc = "Bits 1:3 - LDO output voltage select"] + #[inline(always)] + pub fn vout_sel(&mut self) -> VoutSelW { + VoutSelW::new(self, 1) + } + #[doc = "Bit 4 - LDO Bypass"] + #[inline(always)] + pub fn ldobypass(&mut self) -> LdobypassW { + LdobypassW::new(self, 4) + } +} +#[doc = "LDO Control and Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ldocsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ldocsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LdocsrSpec; +impl crate::RegisterSpec for LdocsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ldocsr::R`](R) reader structure"] +impl crate::Readable for LdocsrSpec {} +#[doc = "`write(|w| ..)` method takes [`ldocsr::W`](W) writer structure"] +impl crate::Writable for LdocsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LDOCSR to value 0x08"] +impl crate::Resettable for LdocsrSpec { + const RESET_VALUE: u32 = 0x08; +} diff --git a/mcxa276-pac/src/scg0/param.rs b/mcxa276-pac/src/scg0/param.rs new file mode 100644 index 000000000..d252503fe --- /dev/null +++ b/mcxa276-pac/src/scg0/param.rs @@ -0,0 +1,220 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "SOSC Clock Present\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soscclkpres { + #[doc = "0: SOSC clock source is not present"] + Nopres = 0, + #[doc = "1: SOSC clock source is present"] + Pres = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soscclkpres) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCCLKPRES` reader - SOSC Clock Present"] +pub type SoscclkpresR = crate::BitReader; +impl SoscclkpresR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soscclkpres { + match self.bits { + false => Soscclkpres::Nopres, + true => Soscclkpres::Pres, + } + } + #[doc = "SOSC clock source is not present"] + #[inline(always)] + pub fn is_nopres(&self) -> bool { + *self == Soscclkpres::Nopres + } + #[doc = "SOSC clock source is present"] + #[inline(always)] + pub fn is_pres(&self) -> bool { + *self == Soscclkpres::Pres + } +} +#[doc = "SIRC Clock Present\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sircclkpres { + #[doc = "0: SIRC clock source is not present"] + Nopres = 0, + #[doc = "1: SIRC clock source is present"] + Pres = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sircclkpres) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCCLKPRES` reader - SIRC Clock Present"] +pub type SircclkpresR = crate::BitReader; +impl SircclkpresR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sircclkpres { + match self.bits { + false => Sircclkpres::Nopres, + true => Sircclkpres::Pres, + } + } + #[doc = "SIRC clock source is not present"] + #[inline(always)] + pub fn is_nopres(&self) -> bool { + *self == Sircclkpres::Nopres + } + #[doc = "SIRC clock source is present"] + #[inline(always)] + pub fn is_pres(&self) -> bool { + *self == Sircclkpres::Pres + } +} +#[doc = "FIRC Clock Present\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fircclkpres { + #[doc = "0: FIRC clock source is not present"] + Nopres = 0, + #[doc = "1: FIRC clock source is present"] + Pres = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fircclkpres) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRCCLKPRES` reader - FIRC Clock Present"] +pub type FircclkpresR = crate::BitReader; +impl FircclkpresR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fircclkpres { + match self.bits { + false => Fircclkpres::Nopres, + true => Fircclkpres::Pres, + } + } + #[doc = "FIRC clock source is not present"] + #[inline(always)] + pub fn is_nopres(&self) -> bool { + *self == Fircclkpres::Nopres + } + #[doc = "FIRC clock source is present"] + #[inline(always)] + pub fn is_pres(&self) -> bool { + *self == Fircclkpres::Pres + } +} +#[doc = "ROSC Clock Present\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Roscclkpres { + #[doc = "0: ROSC clock source is not present"] + Nopres = 0, + #[doc = "1: ROSC clock source is present"] + Pres = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Roscclkpres) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROSCCLKPRES` reader - ROSC Clock Present"] +pub type RoscclkpresR = crate::BitReader; +impl RoscclkpresR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Roscclkpres { + match self.bits { + false => Roscclkpres::Nopres, + true => Roscclkpres::Pres, + } + } + #[doc = "ROSC clock source is not present"] + #[inline(always)] + pub fn is_nopres(&self) -> bool { + *self == Roscclkpres::Nopres + } + #[doc = "ROSC clock source is present"] + #[inline(always)] + pub fn is_pres(&self) -> bool { + *self == Roscclkpres::Pres + } +} +#[doc = "SPLL Clock Present\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllclkpres { + #[doc = "0: SPLL clock source is not present"] + Nopres = 0, + #[doc = "1: SPLL clock source is present"] + Pres = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllclkpres) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLCLKPRES` reader - SPLL Clock Present"] +pub type SpllclkpresR = crate::BitReader; +impl SpllclkpresR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllclkpres { + match self.bits { + false => Spllclkpres::Nopres, + true => Spllclkpres::Pres, + } + } + #[doc = "SPLL clock source is not present"] + #[inline(always)] + pub fn is_nopres(&self) -> bool { + *self == Spllclkpres::Nopres + } + #[doc = "SPLL clock source is present"] + #[inline(always)] + pub fn is_pres(&self) -> bool { + *self == Spllclkpres::Pres + } +} +impl R { + #[doc = "Bit 1 - SOSC Clock Present"] + #[inline(always)] + pub fn soscclkpres(&self) -> SoscclkpresR { + SoscclkpresR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SIRC Clock Present"] + #[inline(always)] + pub fn sircclkpres(&self) -> SircclkpresR { + SircclkpresR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIRC Clock Present"] + #[inline(always)] + pub fn fircclkpres(&self) -> FircclkpresR { + FircclkpresR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - ROSC Clock Present"] + #[inline(always)] + pub fn roscclkpres(&self) -> RoscclkpresR { + RoscclkpresR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - SPLL Clock Present"] + #[inline(always)] + pub fn spllclkpres(&self) -> SpllclkpresR { + SpllclkpresR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x5e"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x5e; +} diff --git a/mcxa276-pac/src/scg0/rccr.rs b/mcxa276-pac/src/scg0/rccr.rs new file mode 100644 index 000000000..e47eed92e --- /dev/null +++ b/mcxa276-pac/src/scg0/rccr.rs @@ -0,0 +1,132 @@ +#[doc = "Register `RCCR` reader"] +pub type R = crate::R; +#[doc = "Register `RCCR` writer"] +pub type W = crate::W; +#[doc = "System Clock Source\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Scs { + #[doc = "1: SOSC"] + Sosc = 1, + #[doc = "2: SIRC"] + Sirc = 2, + #[doc = "3: FIRC"] + Firc = 3, + #[doc = "4: ROSC"] + Rosc = 4, + #[doc = "6: SPLL"] + Spll = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Scs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Scs { + type Ux = u8; +} +impl crate::IsEnum for Scs {} +#[doc = "Field `SCS` reader - System Clock Source"] +pub type ScsR = crate::FieldReader; +impl ScsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Scs::Sosc), + 2 => Some(Scs::Sirc), + 3 => Some(Scs::Firc), + 4 => Some(Scs::Rosc), + 6 => Some(Scs::Spll), + _ => None, + } + } + #[doc = "SOSC"] + #[inline(always)] + pub fn is_sosc(&self) -> bool { + *self == Scs::Sosc + } + #[doc = "SIRC"] + #[inline(always)] + pub fn is_sirc(&self) -> bool { + *self == Scs::Sirc + } + #[doc = "FIRC"] + #[inline(always)] + pub fn is_firc(&self) -> bool { + *self == Scs::Firc + } + #[doc = "ROSC"] + #[inline(always)] + pub fn is_rosc(&self) -> bool { + *self == Scs::Rosc + } + #[doc = "SPLL"] + #[inline(always)] + pub fn is_spll(&self) -> bool { + *self == Scs::Spll + } +} +#[doc = "Field `SCS` writer - System Clock Source"] +pub type ScsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Scs>; +impl<'a, REG> ScsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "SOSC"] + #[inline(always)] + pub fn sosc(self) -> &'a mut crate::W { + self.variant(Scs::Sosc) + } + #[doc = "SIRC"] + #[inline(always)] + pub fn sirc(self) -> &'a mut crate::W { + self.variant(Scs::Sirc) + } + #[doc = "FIRC"] + #[inline(always)] + pub fn firc(self) -> &'a mut crate::W { + self.variant(Scs::Firc) + } + #[doc = "ROSC"] + #[inline(always)] + pub fn rosc(self) -> &'a mut crate::W { + self.variant(Scs::Rosc) + } + #[doc = "SPLL"] + #[inline(always)] + pub fn spll(self) -> &'a mut crate::W { + self.variant(Scs::Spll) + } +} +impl R { + #[doc = "Bits 24:26 - System Clock Source"] + #[inline(always)] + pub fn scs(&self) -> ScsR { + ScsR::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bits 24:26 - System Clock Source"] + #[inline(always)] + pub fn scs(&mut self) -> ScsW { + ScsW::new(self, 24) + } +} +#[doc = "Run Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RccrSpec; +impl crate::RegisterSpec for RccrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rccr::R`](R) reader structure"] +impl crate::Readable for RccrSpec {} +#[doc = "`write(|w| ..)` method takes [`rccr::W`](W) writer structure"] +impl crate::Writable for RccrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RCCR to value 0x0300_0000"] +impl crate::Resettable for RccrSpec { + const RESET_VALUE: u32 = 0x0300_0000; +} diff --git a/mcxa276-pac/src/scg0/rosccsr.rs b/mcxa276-pac/src/scg0/rosccsr.rs new file mode 100644 index 000000000..614bf4157 --- /dev/null +++ b/mcxa276-pac/src/scg0/rosccsr.rs @@ -0,0 +1,230 @@ +#[doc = "Register `ROSCCSR` reader"] +pub type R = crate::R; +#[doc = "Register `ROSCCSR` writer"] +pub type W = crate::W; +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Control Status Register can be written"] + WriteEnabled = 0, + #[doc = "1: Control Status Register cannot be written"] + WriteDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::WriteEnabled, + true => Lk::WriteDisabled, + } + } + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn is_write_enabled(&self) -> bool { + *self == Lk::WriteEnabled + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn is_write_disabled(&self) -> bool { + *self == Lk::WriteDisabled + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn write_enabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteEnabled) + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn write_disabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteDisabled) + } +} +#[doc = "ROSC Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Roscvld { + #[doc = "0: ROSC is not enabled or clock is not valid"] + DisabledOrNotValid = 0, + #[doc = "1: ROSC is enabled and output clock is valid"] + EnabledAndValid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Roscvld) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROSCVLD` reader - ROSC Valid"] +pub type RoscvldR = crate::BitReader; +impl RoscvldR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Roscvld { + match self.bits { + false => Roscvld::DisabledOrNotValid, + true => Roscvld::EnabledAndValid, + } + } + #[doc = "ROSC is not enabled or clock is not valid"] + #[inline(always)] + pub fn is_disabled_or_not_valid(&self) -> bool { + *self == Roscvld::DisabledOrNotValid + } + #[doc = "ROSC is enabled and output clock is valid"] + #[inline(always)] + pub fn is_enabled_and_valid(&self) -> bool { + *self == Roscvld::EnabledAndValid + } +} +#[doc = "ROSC Selected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Roscsel { + #[doc = "0: ROSC is not the system clock source"] + NotRosc = 0, + #[doc = "1: ROSC is the system clock source"] + Rosc = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Roscsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROSCSEL` reader - ROSC Selected"] +pub type RoscselR = crate::BitReader; +impl RoscselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Roscsel { + match self.bits { + false => Roscsel::NotRosc, + true => Roscsel::Rosc, + } + } + #[doc = "ROSC is not the system clock source"] + #[inline(always)] + pub fn is_not_rosc(&self) -> bool { + *self == Roscsel::NotRosc + } + #[doc = "ROSC is the system clock source"] + #[inline(always)] + pub fn is_rosc(&self) -> bool { + *self == Roscsel::Rosc + } +} +#[doc = "ROSC Clock Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Roscerr { + #[doc = "0: ROSC Clock has not detected an error"] + DisabledOrNoError = 0, + #[doc = "1: ROSC Clock has detected an error"] + EnabledAndError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Roscerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROSCERR` reader - ROSC Clock Error"] +pub type RoscerrR = crate::BitReader; +impl RoscerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Roscerr { + match self.bits { + false => Roscerr::DisabledOrNoError, + true => Roscerr::EnabledAndError, + } + } + #[doc = "ROSC Clock has not detected an error"] + #[inline(always)] + pub fn is_disabled_or_no_error(&self) -> bool { + *self == Roscerr::DisabledOrNoError + } + #[doc = "ROSC Clock has detected an error"] + #[inline(always)] + pub fn is_enabled_and_error(&self) -> bool { + *self == Roscerr::EnabledAndError + } +} +#[doc = "Field `ROSCERR` writer - ROSC Clock Error"] +pub type RoscerrW<'a, REG> = crate::BitWriter1C<'a, REG, Roscerr>; +impl<'a, REG> RoscerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ROSC Clock has not detected an error"] + #[inline(always)] + pub fn disabled_or_no_error(self) -> &'a mut crate::W { + self.variant(Roscerr::DisabledOrNoError) + } + #[doc = "ROSC Clock has detected an error"] + #[inline(always)] + pub fn enabled_and_error(self) -> &'a mut crate::W { + self.variant(Roscerr::EnabledAndError) + } +} +impl R { + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - ROSC Valid"] + #[inline(always)] + pub fn roscvld(&self) -> RoscvldR { + RoscvldR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - ROSC Selected"] + #[inline(always)] + pub fn roscsel(&self) -> RoscselR { + RoscselR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - ROSC Clock Error"] + #[inline(always)] + pub fn roscerr(&self) -> RoscerrR { + RoscerrR::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 23) + } + #[doc = "Bit 26 - ROSC Clock Error"] + #[inline(always)] + pub fn roscerr(&mut self) -> RoscerrW { + RoscerrW::new(self, 26) + } +} +#[doc = "ROSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rosccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RosccsrSpec; +impl crate::RegisterSpec for RosccsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rosccsr::R`](R) reader structure"] +impl crate::Readable for RosccsrSpec {} +#[doc = "`write(|w| ..)` method takes [`rosccsr::W`](W) writer structure"] +impl crate::Writable for RosccsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; +} +#[doc = "`reset()` method sets ROSCCSR to value 0"] +impl crate::Resettable for RosccsrSpec {} diff --git a/mcxa276-pac/src/scg0/sirccsr.rs b/mcxa276-pac/src/scg0/sirccsr.rs new file mode 100644 index 000000000..810dc3ea3 --- /dev/null +++ b/mcxa276-pac/src/scg0/sirccsr.rs @@ -0,0 +1,651 @@ +#[doc = "Register `SIRCCSR` reader"] +pub type R = crate::R; +#[doc = "Register `SIRCCSR` writer"] +pub type W = crate::W; +#[doc = "SIRC Stop Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sircsten { + #[doc = "0: SIRC is disabled in Deep Sleep mode"] + Disabled = 0, + #[doc = "1: SIRC is enabled in Deep Sleep mode"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sircsten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCSTEN` reader - SIRC Stop Enable"] +pub type SircstenR = crate::BitReader; +impl SircstenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sircsten { + match self.bits { + false => Sircsten::Disabled, + true => Sircsten::Enabled, + } + } + #[doc = "SIRC is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sircsten::Disabled + } + #[doc = "SIRC is enabled in Deep Sleep mode"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sircsten::Enabled + } +} +#[doc = "Field `SIRCSTEN` writer - SIRC Stop Enable"] +pub type SircstenW<'a, REG> = crate::BitWriter<'a, REG, Sircsten>; +impl<'a, REG> SircstenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SIRC is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sircsten::Disabled) + } + #[doc = "SIRC is enabled in Deep Sleep mode"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sircsten::Enabled) + } +} +#[doc = "SIRC Clock to Peripherals Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SircClkPeriphEn { + #[doc = "0: SIRC clock to peripherals is disabled"] + Disabled = 0, + #[doc = "1: SIRC clock to peripherals is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SircClkPeriphEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRC_CLK_PERIPH_EN` reader - SIRC Clock to Peripherals Enable"] +pub type SircClkPeriphEnR = crate::BitReader; +impl SircClkPeriphEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SircClkPeriphEn { + match self.bits { + false => SircClkPeriphEn::Disabled, + true => SircClkPeriphEn::Enabled, + } + } + #[doc = "SIRC clock to peripherals is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SircClkPeriphEn::Disabled + } + #[doc = "SIRC clock to peripherals is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SircClkPeriphEn::Enabled + } +} +#[doc = "Field `SIRC_CLK_PERIPH_EN` writer - SIRC Clock to Peripherals Enable"] +pub type SircClkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, SircClkPeriphEn>; +impl<'a, REG> SircClkPeriphEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SIRC clock to peripherals is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(SircClkPeriphEn::Disabled) + } + #[doc = "SIRC clock to peripherals is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(SircClkPeriphEn::Enabled) + } +} +#[doc = "SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sirctren { + #[doc = "0: Disables trimming SIRC to an external clock source"] + Disabled = 0, + #[doc = "1: Enables trimming SIRC to an external clock source"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sirctren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCTREN` reader - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] +pub type SirctrenR = crate::BitReader; +impl SirctrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sirctren { + match self.bits { + false => Sirctren::Disabled, + true => Sirctren::Enabled, + } + } + #[doc = "Disables trimming SIRC to an external clock source"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sirctren::Disabled + } + #[doc = "Enables trimming SIRC to an external clock source"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sirctren::Enabled + } +} +#[doc = "Field `SIRCTREN` writer - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] +pub type SirctrenW<'a, REG> = crate::BitWriter<'a, REG, Sirctren>; +impl<'a, REG> SirctrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables trimming SIRC to an external clock source"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sirctren::Disabled) + } + #[doc = "Enables trimming SIRC to an external clock source"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sirctren::Enabled) + } +} +#[doc = "SIRC Trim Update\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sirctrup { + #[doc = "0: Disables SIRC trimming updates"] + Disabled = 0, + #[doc = "1: Enables SIRC trimming updates"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sirctrup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCTRUP` reader - SIRC Trim Update"] +pub type SirctrupR = crate::BitReader; +impl SirctrupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sirctrup { + match self.bits { + false => Sirctrup::Disabled, + true => Sirctrup::Enabled, + } + } + #[doc = "Disables SIRC trimming updates"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sirctrup::Disabled + } + #[doc = "Enables SIRC trimming updates"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sirctrup::Enabled + } +} +#[doc = "Field `SIRCTRUP` writer - SIRC Trim Update"] +pub type SirctrupW<'a, REG> = crate::BitWriter<'a, REG, Sirctrup>; +impl<'a, REG> SirctrupW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables SIRC trimming updates"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sirctrup::Disabled) + } + #[doc = "Enables SIRC trimming updates"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sirctrup::Enabled) + } +} +#[doc = "SIRC TRIM LOCK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrimLock { + #[doc = "0: SIRC auto trim not locked to target frequency range"] + SircNotLocked = 0, + #[doc = "1: SIRC auto trim locked to target frequency range"] + SircLocked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrimLock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIM_LOCK` reader - SIRC TRIM LOCK"] +pub type TrimLockR = crate::BitReader; +impl TrimLockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrimLock { + match self.bits { + false => TrimLock::SircNotLocked, + true => TrimLock::SircLocked, + } + } + #[doc = "SIRC auto trim not locked to target frequency range"] + #[inline(always)] + pub fn is_sirc_not_locked(&self) -> bool { + *self == TrimLock::SircNotLocked + } + #[doc = "SIRC auto trim locked to target frequency range"] + #[inline(always)] + pub fn is_sirc_locked(&self) -> bool { + *self == TrimLock::SircLocked + } +} +#[doc = "Coarse Auto Trim Bypass\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoarseTrimBypass { + #[doc = "0: SIRC Coarse Auto Trim NOT Bypassed"] + NotBypassed = 0, + #[doc = "1: SIRC Coarse Auto Trim Bypassed"] + Bypassed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoarseTrimBypass) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COARSE_TRIM_BYPASS` reader - Coarse Auto Trim Bypass"] +pub type CoarseTrimBypassR = crate::BitReader; +impl CoarseTrimBypassR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoarseTrimBypass { + match self.bits { + false => CoarseTrimBypass::NotBypassed, + true => CoarseTrimBypass::Bypassed, + } + } + #[doc = "SIRC Coarse Auto Trim NOT Bypassed"] + #[inline(always)] + pub fn is_not_bypassed(&self) -> bool { + *self == CoarseTrimBypass::NotBypassed + } + #[doc = "SIRC Coarse Auto Trim Bypassed"] + #[inline(always)] + pub fn is_bypassed(&self) -> bool { + *self == CoarseTrimBypass::Bypassed + } +} +#[doc = "Field `COARSE_TRIM_BYPASS` writer - Coarse Auto Trim Bypass"] +pub type CoarseTrimBypassW<'a, REG> = crate::BitWriter<'a, REG, CoarseTrimBypass>; +impl<'a, REG> CoarseTrimBypassW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SIRC Coarse Auto Trim NOT Bypassed"] + #[inline(always)] + pub fn not_bypassed(self) -> &'a mut crate::W { + self.variant(CoarseTrimBypass::NotBypassed) + } + #[doc = "SIRC Coarse Auto Trim Bypassed"] + #[inline(always)] + pub fn bypassed(self) -> &'a mut crate::W { + self.variant(CoarseTrimBypass::Bypassed) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Control Status Register can be written"] + WriteEnabled = 0, + #[doc = "1: Control Status Register cannot be written"] + WriteDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::WriteEnabled, + true => Lk::WriteDisabled, + } + } + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn is_write_enabled(&self) -> bool { + *self == Lk::WriteEnabled + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn is_write_disabled(&self) -> bool { + *self == Lk::WriteDisabled + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn write_enabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteEnabled) + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn write_disabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteDisabled) + } +} +#[doc = "SIRC Valid\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sircvld { + #[doc = "0: SIRC is not enabled or clock is not valid"] + DisabledOrNotValid = 0, + #[doc = "1: SIRC is enabled and output clock is valid"] + EnabledAndValid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sircvld) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCVLD` reader - SIRC Valid"] +pub type SircvldR = crate::BitReader; +impl SircvldR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sircvld { + match self.bits { + false => Sircvld::DisabledOrNotValid, + true => Sircvld::EnabledAndValid, + } + } + #[doc = "SIRC is not enabled or clock is not valid"] + #[inline(always)] + pub fn is_disabled_or_not_valid(&self) -> bool { + *self == Sircvld::DisabledOrNotValid + } + #[doc = "SIRC is enabled and output clock is valid"] + #[inline(always)] + pub fn is_enabled_and_valid(&self) -> bool { + *self == Sircvld::EnabledAndValid + } +} +#[doc = "SIRC Selected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sircsel { + #[doc = "0: SIRC is not the system clock source"] + NotSirc = 0, + #[doc = "1: SIRC is the system clock source"] + Sirc = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sircsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCSEL` reader - SIRC Selected"] +pub type SircselR = crate::BitReader; +impl SircselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sircsel { + match self.bits { + false => Sircsel::NotSirc, + true => Sircsel::Sirc, + } + } + #[doc = "SIRC is not the system clock source"] + #[inline(always)] + pub fn is_not_sirc(&self) -> bool { + *self == Sircsel::NotSirc + } + #[doc = "SIRC is the system clock source"] + #[inline(always)] + pub fn is_sirc(&self) -> bool { + *self == Sircsel::Sirc + } +} +#[doc = "SIRC Clock Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sircerr { + #[doc = "0: Error not detected with the SIRC trimming"] + ErrorNotDetected = 0, + #[doc = "1: Error detected with the SIRC trimming"] + ErrorDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sircerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCERR` reader - SIRC Clock Error"] +pub type SircerrR = crate::BitReader; +impl SircerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sircerr { + match self.bits { + false => Sircerr::ErrorNotDetected, + true => Sircerr::ErrorDetected, + } + } + #[doc = "Error not detected with the SIRC trimming"] + #[inline(always)] + pub fn is_error_not_detected(&self) -> bool { + *self == Sircerr::ErrorNotDetected + } + #[doc = "Error detected with the SIRC trimming"] + #[inline(always)] + pub fn is_error_detected(&self) -> bool { + *self == Sircerr::ErrorDetected + } +} +#[doc = "Field `SIRCERR` writer - SIRC Clock Error"] +pub type SircerrW<'a, REG> = crate::BitWriter1C<'a, REG, Sircerr>; +impl<'a, REG> SircerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error not detected with the SIRC trimming"] + #[inline(always)] + pub fn error_not_detected(self) -> &'a mut crate::W { + self.variant(Sircerr::ErrorNotDetected) + } + #[doc = "Error detected with the SIRC trimming"] + #[inline(always)] + pub fn error_detected(self) -> &'a mut crate::W { + self.variant(Sircerr::ErrorDetected) + } +} +#[doc = "SIRC Clock Error Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SircerrIe { + #[doc = "0: SIRCERR interrupt is not enabled"] + ErrorNotDetected = 0, + #[doc = "1: SIRCERR interrupt is enabled"] + ErrorDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SircerrIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIRCERR_IE` reader - SIRC Clock Error Interrupt Enable"] +pub type SircerrIeR = crate::BitReader; +impl SircerrIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SircerrIe { + match self.bits { + false => SircerrIe::ErrorNotDetected, + true => SircerrIe::ErrorDetected, + } + } + #[doc = "SIRCERR interrupt is not enabled"] + #[inline(always)] + pub fn is_error_not_detected(&self) -> bool { + *self == SircerrIe::ErrorNotDetected + } + #[doc = "SIRCERR interrupt is enabled"] + #[inline(always)] + pub fn is_error_detected(&self) -> bool { + *self == SircerrIe::ErrorDetected + } +} +#[doc = "Field `SIRCERR_IE` writer - SIRC Clock Error Interrupt Enable"] +pub type SircerrIeW<'a, REG> = crate::BitWriter<'a, REG, SircerrIe>; +impl<'a, REG> SircerrIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SIRCERR interrupt is not enabled"] + #[inline(always)] + pub fn error_not_detected(self) -> &'a mut crate::W { + self.variant(SircerrIe::ErrorNotDetected) + } + #[doc = "SIRCERR interrupt is enabled"] + #[inline(always)] + pub fn error_detected(self) -> &'a mut crate::W { + self.variant(SircerrIe::ErrorDetected) + } +} +impl R { + #[doc = "Bit 1 - SIRC Stop Enable"] + #[inline(always)] + pub fn sircsten(&self) -> SircstenR { + SircstenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 5 - SIRC Clock to Peripherals Enable"] + #[inline(always)] + pub fn sirc_clk_periph_en(&self) -> SircClkPeriphEnR { + SircClkPeriphEnR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] + #[inline(always)] + pub fn sirctren(&self) -> SirctrenR { + SirctrenR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SIRC Trim Update"] + #[inline(always)] + pub fn sirctrup(&self) -> SirctrupR { + SirctrupR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SIRC TRIM LOCK"] + #[inline(always)] + pub fn trim_lock(&self) -> TrimLockR { + TrimLockR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Coarse Auto Trim Bypass"] + #[inline(always)] + pub fn coarse_trim_bypass(&self) -> CoarseTrimBypassR { + CoarseTrimBypassR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SIRC Valid"] + #[inline(always)] + pub fn sircvld(&self) -> SircvldR { + SircvldR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - SIRC Selected"] + #[inline(always)] + pub fn sircsel(&self) -> SircselR { + SircselR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - SIRC Clock Error"] + #[inline(always)] + pub fn sircerr(&self) -> SircerrR { + SircerrR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - SIRC Clock Error Interrupt Enable"] + #[inline(always)] + pub fn sircerr_ie(&self) -> SircerrIeR { + SircerrIeR::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - SIRC Stop Enable"] + #[inline(always)] + pub fn sircsten(&mut self) -> SircstenW { + SircstenW::new(self, 1) + } + #[doc = "Bit 5 - SIRC Clock to Peripherals Enable"] + #[inline(always)] + pub fn sirc_clk_periph_en(&mut self) -> SircClkPeriphEnW { + SircClkPeriphEnW::new(self, 5) + } + #[doc = "Bit 8 - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] + #[inline(always)] + pub fn sirctren(&mut self) -> SirctrenW { + SirctrenW::new(self, 8) + } + #[doc = "Bit 9 - SIRC Trim Update"] + #[inline(always)] + pub fn sirctrup(&mut self) -> SirctrupW { + SirctrupW::new(self, 9) + } + #[doc = "Bit 11 - Coarse Auto Trim Bypass"] + #[inline(always)] + pub fn coarse_trim_bypass(&mut self) -> CoarseTrimBypassW { + CoarseTrimBypassW::new(self, 11) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 23) + } + #[doc = "Bit 26 - SIRC Clock Error"] + #[inline(always)] + pub fn sircerr(&mut self) -> SircerrW { + SircerrW::new(self, 26) + } + #[doc = "Bit 27 - SIRC Clock Error Interrupt Enable"] + #[inline(always)] + pub fn sircerr_ie(&mut self) -> SircerrIeW { + SircerrIeW::new(self, 27) + } +} +#[doc = "SIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SirccsrSpec; +impl crate::RegisterSpec for SirccsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sirccsr::R`](R) reader structure"] +impl crate::Readable for SirccsrSpec {} +#[doc = "`write(|w| ..)` method takes [`sirccsr::W`](W) writer structure"] +impl crate::Writable for SirccsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; +} +#[doc = "`reset()` method sets SIRCCSR to value 0x0100_0020"] +impl crate::Resettable for SirccsrSpec { + const RESET_VALUE: u32 = 0x0100_0020; +} diff --git a/mcxa276-pac/src/scg0/sircstat.rs b/mcxa276-pac/src/scg0/sircstat.rs new file mode 100644 index 000000000..d588cd35f --- /dev/null +++ b/mcxa276-pac/src/scg0/sircstat.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SIRCSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `SIRCSTAT` writer"] +pub type W = crate::W; +#[doc = "Field `CCOTRIM` reader - CCO Trim"] +pub type CcotrimR = crate::FieldReader; +#[doc = "Field `CCOTRIM` writer - CCO Trim"] +pub type CcotrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CLTRIM` reader - CL Trim"] +pub type CltrimR = crate::FieldReader; +#[doc = "Field `CLTRIM` writer - CL Trim"] +pub type CltrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - CCO Trim"] + #[inline(always)] + pub fn ccotrim(&self) -> CcotrimR { + CcotrimR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - CL Trim"] + #[inline(always)] + pub fn cltrim(&self) -> CltrimR { + CltrimR::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - CCO Trim"] + #[inline(always)] + pub fn ccotrim(&mut self) -> CcotrimW { + CcotrimW::new(self, 0) + } + #[doc = "Bits 8:13 - CL Trim"] + #[inline(always)] + pub fn cltrim(&mut self) -> CltrimW { + CltrimW::new(self, 8) + } +} +#[doc = "SIRC Auto-trimming Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sircstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sircstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SircstatSpec; +impl crate::RegisterSpec for SircstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sircstat::R`](R) reader structure"] +impl crate::Readable for SircstatSpec {} +#[doc = "`write(|w| ..)` method takes [`sircstat::W`](W) writer structure"] +impl crate::Writable for SircstatSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SIRCSTAT to value 0"] +impl crate::Resettable for SircstatSpec {} diff --git a/mcxa276-pac/src/scg0/sirctcfg.rs b/mcxa276-pac/src/scg0/sirctcfg.rs new file mode 100644 index 000000000..11f8a91bb --- /dev/null +++ b/mcxa276-pac/src/scg0/sirctcfg.rs @@ -0,0 +1,92 @@ +#[doc = "Register `SIRCTCFG` reader"] +pub type R = crate::R; +#[doc = "Register `SIRCTCFG` writer"] +pub type W = crate::W; +#[doc = "Trim Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Trimsrc { + #[doc = "2: SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."] + Sosc = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Trimsrc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Trimsrc { + type Ux = u8; +} +impl crate::IsEnum for Trimsrc {} +#[doc = "Field `TRIMSRC` reader - Trim Source"] +pub type TrimsrcR = crate::FieldReader; +impl TrimsrcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(Trimsrc::Sosc), + _ => None, + } + } + #[doc = "SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."] + #[inline(always)] + pub fn is_sosc(&self) -> bool { + *self == Trimsrc::Sosc + } +} +#[doc = "Field `TRIMSRC` writer - Trim Source"] +pub type TrimsrcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trimsrc>; +impl<'a, REG> TrimsrcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."] + #[inline(always)] + pub fn sosc(self) -> &'a mut crate::W { + self.variant(Trimsrc::Sosc) + } +} +#[doc = "Field `TRIMDIV` reader - SIRC Trim Pre-divider"] +pub type TrimdivR = crate::FieldReader; +#[doc = "Field `TRIMDIV` writer - SIRC Trim Pre-divider"] +pub type TrimdivW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:1 - Trim Source"] + #[inline(always)] + pub fn trimsrc(&self) -> TrimsrcR { + TrimsrcR::new((self.bits & 3) as u8) + } + #[doc = "Bits 16:22 - SIRC Trim Pre-divider"] + #[inline(always)] + pub fn trimdiv(&self) -> TrimdivR { + TrimdivR::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Trim Source"] + #[inline(always)] + pub fn trimsrc(&mut self) -> TrimsrcW { + TrimsrcW::new(self, 0) + } + #[doc = "Bits 16:22 - SIRC Trim Pre-divider"] + #[inline(always)] + pub fn trimdiv(&mut self) -> TrimdivW { + TrimdivW::new(self, 16) + } +} +#[doc = "SIRC Trim Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SirctcfgSpec; +impl crate::RegisterSpec for SirctcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sirctcfg::R`](R) reader structure"] +impl crate::Readable for SirctcfgSpec {} +#[doc = "`write(|w| ..)` method takes [`sirctcfg::W`](W) writer structure"] +impl crate::Writable for SirctcfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SIRCTCFG to value 0"] +impl crate::Resettable for SirctcfgSpec {} diff --git a/mcxa276-pac/src/scg0/sirctrim.rs b/mcxa276-pac/src/scg0/sirctrim.rs new file mode 100644 index 000000000..7515b5b03 --- /dev/null +++ b/mcxa276-pac/src/scg0/sirctrim.rs @@ -0,0 +1,77 @@ +#[doc = "Register `SIRCTRIM` reader"] +pub type R = crate::R; +#[doc = "Register `SIRCTRIM` writer"] +pub type W = crate::W; +#[doc = "Field `CCOTRIM` reader - CCO Trim"] +pub type CcotrimR = crate::FieldReader; +#[doc = "Field `CCOTRIM` writer - CCO Trim"] +pub type CcotrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CLTRIM` reader - CL Trim"] +pub type CltrimR = crate::FieldReader; +#[doc = "Field `CLTRIM` writer - CL Trim"] +pub type CltrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TCTRIM` reader - Trim Temp"] +pub type TctrimR = crate::FieldReader; +#[doc = "Field `TCTRIM` writer - Trim Temp"] +pub type TctrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `FVCHTRIM` reader - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] +pub type FvchtrimR = crate::FieldReader; +#[doc = "Field `FVCHTRIM` writer - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] +pub type FvchtrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:5 - CCO Trim"] + #[inline(always)] + pub fn ccotrim(&self) -> CcotrimR { + CcotrimR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - CL Trim"] + #[inline(always)] + pub fn cltrim(&self) -> CltrimR { + CltrimR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:20 - Trim Temp"] + #[inline(always)] + pub fn tctrim(&self) -> TctrimR { + TctrimR::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] + #[inline(always)] + pub fn fvchtrim(&self) -> FvchtrimR { + FvchtrimR::new(((self.bits >> 24) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - CCO Trim"] + #[inline(always)] + pub fn ccotrim(&mut self) -> CcotrimW { + CcotrimW::new(self, 0) + } + #[doc = "Bits 8:13 - CL Trim"] + #[inline(always)] + pub fn cltrim(&mut self) -> CltrimW { + CltrimW::new(self, 8) + } + #[doc = "Bits 16:20 - Trim Temp"] + #[inline(always)] + pub fn tctrim(&mut self) -> TctrimW { + TctrimW::new(self, 16) + } + #[doc = "Bits 24:28 - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] + #[inline(always)] + pub fn fvchtrim(&mut self) -> FvchtrimW { + FvchtrimW::new(self, 24) + } +} +#[doc = "SIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SirctrimSpec; +impl crate::RegisterSpec for SirctrimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sirctrim::R`](R) reader structure"] +impl crate::Readable for SirctrimSpec {} +#[doc = "`write(|w| ..)` method takes [`sirctrim::W`](W) writer structure"] +impl crate::Writable for SirctrimSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SIRCTRIM to value 0"] +impl crate::Resettable for SirctrimSpec {} diff --git a/mcxa276-pac/src/scg0/sosccfg.rs b/mcxa276-pac/src/scg0/sosccfg.rs new file mode 100644 index 000000000..d549827af --- /dev/null +++ b/mcxa276-pac/src/scg0/sosccfg.rs @@ -0,0 +1,180 @@ +#[doc = "Register `SOSCCFG` reader"] +pub type R = crate::R; +#[doc = "Register `SOSCCFG` writer"] +pub type W = crate::W; +#[doc = "External Reference Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erefs { + #[doc = "0: External reference clock selected."] + External = 0, + #[doc = "1: Internal crystal oscillator of OSC selected."] + Internal = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erefs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EREFS` reader - External Reference Select"] +pub type ErefsR = crate::BitReader; +impl ErefsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erefs { + match self.bits { + false => Erefs::External, + true => Erefs::Internal, + } + } + #[doc = "External reference clock selected."] + #[inline(always)] + pub fn is_external(&self) -> bool { + *self == Erefs::External + } + #[doc = "Internal crystal oscillator of OSC selected."] + #[inline(always)] + pub fn is_internal(&self) -> bool { + *self == Erefs::Internal + } +} +#[doc = "Field `EREFS` writer - External Reference Select"] +pub type ErefsW<'a, REG> = crate::BitWriter<'a, REG, Erefs>; +impl<'a, REG> ErefsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "External reference clock selected."] + #[inline(always)] + pub fn external(self) -> &'a mut crate::W { + self.variant(Erefs::External) + } + #[doc = "Internal crystal oscillator of OSC selected."] + #[inline(always)] + pub fn internal(self) -> &'a mut crate::W { + self.variant(Erefs::Internal) + } +} +#[doc = "SOSC Range Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Range { + #[doc = "0: Frequency range select of 8-16 MHz."] + Freq16to20mhz = 0, + #[doc = "1: Frequency range select of 16-25 MHz."] + LowFreq = 1, + #[doc = "2: Frequency range select of 25-40 MHz."] + MediumFreq = 2, + #[doc = "3: Frequency range select of 40-50 MHz."] + HighFreq = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Range) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Range { + type Ux = u8; +} +impl crate::IsEnum for Range {} +#[doc = "Field `RANGE` reader - SOSC Range Select"] +pub type RangeR = crate::FieldReader; +impl RangeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Range { + match self.bits { + 0 => Range::Freq16to20mhz, + 1 => Range::LowFreq, + 2 => Range::MediumFreq, + 3 => Range::HighFreq, + _ => unreachable!(), + } + } + #[doc = "Frequency range select of 8-16 MHz."] + #[inline(always)] + pub fn is_freq_16to20mhz(&self) -> bool { + *self == Range::Freq16to20mhz + } + #[doc = "Frequency range select of 16-25 MHz."] + #[inline(always)] + pub fn is_low_freq(&self) -> bool { + *self == Range::LowFreq + } + #[doc = "Frequency range select of 25-40 MHz."] + #[inline(always)] + pub fn is_medium_freq(&self) -> bool { + *self == Range::MediumFreq + } + #[doc = "Frequency range select of 40-50 MHz."] + #[inline(always)] + pub fn is_high_freq(&self) -> bool { + *self == Range::HighFreq + } +} +#[doc = "Field `RANGE` writer - SOSC Range Select"] +pub type RangeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Range, crate::Safe>; +impl<'a, REG> RangeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Frequency range select of 8-16 MHz."] + #[inline(always)] + pub fn freq_16to20mhz(self) -> &'a mut crate::W { + self.variant(Range::Freq16to20mhz) + } + #[doc = "Frequency range select of 16-25 MHz."] + #[inline(always)] + pub fn low_freq(self) -> &'a mut crate::W { + self.variant(Range::LowFreq) + } + #[doc = "Frequency range select of 25-40 MHz."] + #[inline(always)] + pub fn medium_freq(self) -> &'a mut crate::W { + self.variant(Range::MediumFreq) + } + #[doc = "Frequency range select of 40-50 MHz."] + #[inline(always)] + pub fn high_freq(self) -> &'a mut crate::W { + self.variant(Range::HighFreq) + } +} +impl R { + #[doc = "Bit 2 - External Reference Select"] + #[inline(always)] + pub fn erefs(&self) -> ErefsR { + ErefsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 4:5 - SOSC Range Select"] + #[inline(always)] + pub fn range(&self) -> RangeR { + RangeR::new(((self.bits >> 4) & 3) as u8) + } +} +impl W { + #[doc = "Bit 2 - External Reference Select"] + #[inline(always)] + pub fn erefs(&mut self) -> ErefsW { + ErefsW::new(self, 2) + } + #[doc = "Bits 4:5 - SOSC Range Select"] + #[inline(always)] + pub fn range(&mut self) -> RangeW { + RangeW::new(self, 4) + } +} +#[doc = "SOSC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SosccfgSpec; +impl crate::RegisterSpec for SosccfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sosccfg::R`](R) reader structure"] +impl crate::Readable for SosccfgSpec {} +#[doc = "`write(|w| ..)` method takes [`sosccfg::W`](W) writer structure"] +impl crate::Writable for SosccfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SOSCCFG to value 0"] +impl crate::Resettable for SosccfgSpec {} diff --git a/mcxa276-pac/src/scg0/sosccsr.rs b/mcxa276-pac/src/scg0/sosccsr.rs new file mode 100644 index 000000000..2736f214e --- /dev/null +++ b/mcxa276-pac/src/scg0/sosccsr.rs @@ -0,0 +1,608 @@ +#[doc = "Register `SOSCCSR` reader"] +pub type R = crate::R; +#[doc = "Register `SOSCCSR` writer"] +pub type W = crate::W; +#[doc = "SOSC Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soscen { + #[doc = "0: SOSC is disabled"] + Disabled = 0, + #[doc = "1: SOSC is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soscen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCEN` reader - SOSC Enable"] +pub type SoscenR = crate::BitReader; +impl SoscenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soscen { + match self.bits { + false => Soscen::Disabled, + true => Soscen::Enabled, + } + } + #[doc = "SOSC is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Soscen::Disabled + } + #[doc = "SOSC is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Soscen::Enabled + } +} +#[doc = "Field `SOSCEN` writer - SOSC Enable"] +pub type SoscenW<'a, REG> = crate::BitWriter<'a, REG, Soscen>; +impl<'a, REG> SoscenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SOSC is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Soscen::Disabled) + } + #[doc = "SOSC is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Soscen::Enabled) + } +} +#[doc = "SOSC Stop Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soscsten { + #[doc = "0: SOSC is disabled in Deep Sleep mode"] + Disabled = 0, + #[doc = "1: SOSC is enabled in Deep Sleep mode only if SOSCEN is set"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soscsten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCSTEN` reader - SOSC Stop Enable"] +pub type SoscstenR = crate::BitReader; +impl SoscstenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soscsten { + match self.bits { + false => Soscsten::Disabled, + true => Soscsten::Enabled, + } + } + #[doc = "SOSC is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Soscsten::Disabled + } + #[doc = "SOSC is enabled in Deep Sleep mode only if SOSCEN is set"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Soscsten::Enabled + } +} +#[doc = "Field `SOSCSTEN` writer - SOSC Stop Enable"] +pub type SoscstenW<'a, REG> = crate::BitWriter<'a, REG, Soscsten>; +impl<'a, REG> SoscstenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SOSC is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Soscsten::Disabled) + } + #[doc = "SOSC is enabled in Deep Sleep mode only if SOSCEN is set"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Soscsten::Enabled) + } +} +#[doc = "SOSC Clock Monitor Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sosccm { + #[doc = "0: SOSC Clock Monitor is disabled"] + Disabled = 0, + #[doc = "1: SOSC Clock Monitor is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sosccm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCCM` reader - SOSC Clock Monitor Enable"] +pub type SosccmR = crate::BitReader; +impl SosccmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sosccm { + match self.bits { + false => Sosccm::Disabled, + true => Sosccm::Enabled, + } + } + #[doc = "SOSC Clock Monitor is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Sosccm::Disabled + } + #[doc = "SOSC Clock Monitor is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Sosccm::Enabled + } +} +#[doc = "Field `SOSCCM` writer - SOSC Clock Monitor Enable"] +pub type SosccmW<'a, REG> = crate::BitWriter<'a, REG, Sosccm>; +impl<'a, REG> SosccmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SOSC Clock Monitor is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Sosccm::Disabled) + } + #[doc = "SOSC Clock Monitor is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Sosccm::Enabled) + } +} +#[doc = "SOSC Clock Monitor Reset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sosccmre { + #[doc = "0: Clock monitor generates an interrupt when an error is detected"] + GenerateInterrupt = 0, + #[doc = "1: Clock monitor generates a reset when an error is detected"] + GenerateReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sosccmre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCCMRE` reader - SOSC Clock Monitor Reset Enable"] +pub type SosccmreR = crate::BitReader; +impl SosccmreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sosccmre { + match self.bits { + false => Sosccmre::GenerateInterrupt, + true => Sosccmre::GenerateReset, + } + } + #[doc = "Clock monitor generates an interrupt when an error is detected"] + #[inline(always)] + pub fn is_generate_interrupt(&self) -> bool { + *self == Sosccmre::GenerateInterrupt + } + #[doc = "Clock monitor generates a reset when an error is detected"] + #[inline(always)] + pub fn is_generate_reset(&self) -> bool { + *self == Sosccmre::GenerateReset + } +} +#[doc = "Field `SOSCCMRE` writer - SOSC Clock Monitor Reset Enable"] +pub type SosccmreW<'a, REG> = crate::BitWriter<'a, REG, Sosccmre>; +impl<'a, REG> SosccmreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Clock monitor generates an interrupt when an error is detected"] + #[inline(always)] + pub fn generate_interrupt(self) -> &'a mut crate::W { + self.variant(Sosccmre::GenerateInterrupt) + } + #[doc = "Clock monitor generates a reset when an error is detected"] + #[inline(always)] + pub fn generate_reset(self) -> &'a mut crate::W { + self.variant(Sosccmre::GenerateReset) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: This Control Status Register can be written"] + WriteEnabled = 0, + #[doc = "1: This Control Status Register cannot be written"] + WriteDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::WriteEnabled, + true => Lk::WriteDisabled, + } + } + #[doc = "This Control Status Register can be written"] + #[inline(always)] + pub fn is_write_enabled(&self) -> bool { + *self == Lk::WriteEnabled + } + #[doc = "This Control Status Register cannot be written"] + #[inline(always)] + pub fn is_write_disabled(&self) -> bool { + *self == Lk::WriteDisabled + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This Control Status Register can be written"] + #[inline(always)] + pub fn write_enabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteEnabled) + } + #[doc = "This Control Status Register cannot be written"] + #[inline(always)] + pub fn write_disabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteDisabled) + } +} +#[doc = "SOSC Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soscvld { + #[doc = "0: SOSC is not enabled or clock is not valid"] + Disabled = 0, + #[doc = "1: SOSC is enabled and output clock is valid"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soscvld) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCVLD` reader - SOSC Valid"] +pub type SoscvldR = crate::BitReader; +impl SoscvldR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soscvld { + match self.bits { + false => Soscvld::Disabled, + true => Soscvld::Enabled, + } + } + #[doc = "SOSC is not enabled or clock is not valid"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Soscvld::Disabled + } + #[doc = "SOSC is enabled and output clock is valid"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Soscvld::Enabled + } +} +#[doc = "SOSC Selected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soscsel { + #[doc = "0: SOSC is not the system clock source"] + NotSosc = 0, + #[doc = "1: SOSC is the system clock source"] + Sosc = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soscsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCSEL` reader - SOSC Selected"] +pub type SoscselR = crate::BitReader; +impl SoscselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soscsel { + match self.bits { + false => Soscsel::NotSosc, + true => Soscsel::Sosc, + } + } + #[doc = "SOSC is not the system clock source"] + #[inline(always)] + pub fn is_not_sosc(&self) -> bool { + *self == Soscsel::NotSosc + } + #[doc = "SOSC is the system clock source"] + #[inline(always)] + pub fn is_sosc(&self) -> bool { + *self == Soscsel::Sosc + } +} +#[doc = "SOSC Clock Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Soscerr { + #[doc = "0: SOSC Clock Monitor is disabled or has not detected an error"] + DisabledOrNoError = 0, + #[doc = "1: SOSC Clock Monitor is enabled and detected an error"] + EnabledAndError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Soscerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCERR` reader - SOSC Clock Error"] +pub type SoscerrR = crate::BitReader; +impl SoscerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Soscerr { + match self.bits { + false => Soscerr::DisabledOrNoError, + true => Soscerr::EnabledAndError, + } + } + #[doc = "SOSC Clock Monitor is disabled or has not detected an error"] + #[inline(always)] + pub fn is_disabled_or_no_error(&self) -> bool { + *self == Soscerr::DisabledOrNoError + } + #[doc = "SOSC Clock Monitor is enabled and detected an error"] + #[inline(always)] + pub fn is_enabled_and_error(&self) -> bool { + *self == Soscerr::EnabledAndError + } +} +#[doc = "Field `SOSCERR` writer - SOSC Clock Error"] +pub type SoscerrW<'a, REG> = crate::BitWriter1C<'a, REG, Soscerr>; +impl<'a, REG> SoscerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SOSC Clock Monitor is disabled or has not detected an error"] + #[inline(always)] + pub fn disabled_or_no_error(self) -> &'a mut crate::W { + self.variant(Soscerr::DisabledOrNoError) + } + #[doc = "SOSC Clock Monitor is enabled and detected an error"] + #[inline(always)] + pub fn enabled_and_error(self) -> &'a mut crate::W { + self.variant(Soscerr::EnabledAndError) + } +} +#[doc = "SOSC Valid Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SoscvldIe { + #[doc = "0: SOSCVLD interrupt is not enabled"] + NotSosc = 0, + #[doc = "1: SOSCVLD interrupt is enabled"] + Sosc = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SoscvldIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSCVLD_IE` reader - SOSC Valid Interrupt Enable"] +pub type SoscvldIeR = crate::BitReader; +impl SoscvldIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SoscvldIe { + match self.bits { + false => SoscvldIe::NotSosc, + true => SoscvldIe::Sosc, + } + } + #[doc = "SOSCVLD interrupt is not enabled"] + #[inline(always)] + pub fn is_not_sosc(&self) -> bool { + *self == SoscvldIe::NotSosc + } + #[doc = "SOSCVLD interrupt is enabled"] + #[inline(always)] + pub fn is_sosc(&self) -> bool { + *self == SoscvldIe::Sosc + } +} +#[doc = "Field `SOSCVLD_IE` writer - SOSC Valid Interrupt Enable"] +pub type SoscvldIeW<'a, REG> = crate::BitWriter<'a, REG, SoscvldIe>; +impl<'a, REG> SoscvldIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SOSCVLD interrupt is not enabled"] + #[inline(always)] + pub fn not_sosc(self) -> &'a mut crate::W { + self.variant(SoscvldIe::NotSosc) + } + #[doc = "SOSCVLD interrupt is enabled"] + #[inline(always)] + pub fn sosc(self) -> &'a mut crate::W { + self.variant(SoscvldIe::Sosc) + } +} +#[doc = "SOSC clock safety enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SoscSafeEn { + #[doc = "0: SOSC clock safety is disabled"] + Disable = 0, + #[doc = "1: SOSC clock safety is enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SoscSafeEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOSC_SAFE_EN` reader - SOSC clock safety enable"] +pub type SoscSafeEnR = crate::BitReader; +impl SoscSafeEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SoscSafeEn { + match self.bits { + false => SoscSafeEn::Disable, + true => SoscSafeEn::Enable, + } + } + #[doc = "SOSC clock safety is disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SoscSafeEn::Disable + } + #[doc = "SOSC clock safety is enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SoscSafeEn::Enable + } +} +#[doc = "Field `SOSC_SAFE_EN` writer - SOSC clock safety enable"] +pub type SoscSafeEnW<'a, REG> = crate::BitWriter<'a, REG, SoscSafeEn>; +impl<'a, REG> SoscSafeEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SOSC clock safety is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SoscSafeEn::Disable) + } + #[doc = "SOSC clock safety is enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SoscSafeEn::Enable) + } +} +impl R { + #[doc = "Bit 0 - SOSC Enable"] + #[inline(always)] + pub fn soscen(&self) -> SoscenR { + SoscenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SOSC Stop Enable"] + #[inline(always)] + pub fn soscsten(&self) -> SoscstenR { + SoscstenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - SOSC Clock Monitor Enable"] + #[inline(always)] + pub fn sosccm(&self) -> SosccmR { + SosccmR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SOSC Clock Monitor Reset Enable"] + #[inline(always)] + pub fn sosccmre(&self) -> SosccmreR { + SosccmreR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SOSC Valid"] + #[inline(always)] + pub fn soscvld(&self) -> SoscvldR { + SoscvldR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - SOSC Selected"] + #[inline(always)] + pub fn soscsel(&self) -> SoscselR { + SoscselR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - SOSC Clock Error"] + #[inline(always)] + pub fn soscerr(&self) -> SoscerrR { + SoscerrR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - SOSC Valid Interrupt Enable"] + #[inline(always)] + pub fn soscvld_ie(&self) -> SoscvldIeR { + SoscvldIeR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - SOSC clock safety enable"] + #[inline(always)] + pub fn sosc_safe_en(&self) -> SoscSafeEnR { + SoscSafeEnR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SOSC Enable"] + #[inline(always)] + pub fn soscen(&mut self) -> SoscenW { + SoscenW::new(self, 0) + } + #[doc = "Bit 1 - SOSC Stop Enable"] + #[inline(always)] + pub fn soscsten(&mut self) -> SoscstenW { + SoscstenW::new(self, 1) + } + #[doc = "Bit 16 - SOSC Clock Monitor Enable"] + #[inline(always)] + pub fn sosccm(&mut self) -> SosccmW { + SosccmW::new(self, 16) + } + #[doc = "Bit 17 - SOSC Clock Monitor Reset Enable"] + #[inline(always)] + pub fn sosccmre(&mut self) -> SosccmreW { + SosccmreW::new(self, 17) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 23) + } + #[doc = "Bit 26 - SOSC Clock Error"] + #[inline(always)] + pub fn soscerr(&mut self) -> SoscerrW { + SoscerrW::new(self, 26) + } + #[doc = "Bit 30 - SOSC Valid Interrupt Enable"] + #[inline(always)] + pub fn soscvld_ie(&mut self) -> SoscvldIeW { + SoscvldIeW::new(self, 30) + } + #[doc = "Bit 31 - SOSC clock safety enable"] + #[inline(always)] + pub fn sosc_safe_en(&mut self) -> SoscSafeEnW { + SoscSafeEnW::new(self, 31) + } +} +#[doc = "SOSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SosccsrSpec; +impl crate::RegisterSpec for SosccsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sosccsr::R`](R) reader structure"] +impl crate::Readable for SosccsrSpec {} +#[doc = "`write(|w| ..)` method takes [`sosccsr::W`](W) writer structure"] +impl crate::Writable for SosccsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; +} +#[doc = "`reset()` method sets SOSCCSR to value 0"] +impl crate::Resettable for SosccsrSpec {} diff --git a/mcxa276-pac/src/scg0/spllcsr.rs b/mcxa276-pac/src/scg0/spllcsr.rs new file mode 100644 index 000000000..96eb57a3b --- /dev/null +++ b/mcxa276-pac/src/scg0/spllcsr.rs @@ -0,0 +1,671 @@ +#[doc = "Register `SPLLCSR` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLCSR` writer"] +pub type W = crate::W; +#[doc = "SPLL Power Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllpwren { + #[doc = "0: SPLL clock is powered off"] + Disabled = 0, + #[doc = "1: SPLL clock is powered on"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllpwren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLPWREN` reader - SPLL Power Enable"] +pub type SpllpwrenR = crate::BitReader; +impl SpllpwrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllpwren { + match self.bits { + false => Spllpwren::Disabled, + true => Spllpwren::Enabled, + } + } + #[doc = "SPLL clock is powered off"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Spllpwren::Disabled + } + #[doc = "SPLL clock is powered on"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Spllpwren::Enabled + } +} +#[doc = "Field `SPLLPWREN` writer - SPLL Power Enable"] +pub type SpllpwrenW<'a, REG> = crate::BitWriter<'a, REG, Spllpwren>; +impl<'a, REG> SpllpwrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPLL clock is powered off"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Spllpwren::Disabled) + } + #[doc = "SPLL clock is powered on"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Spllpwren::Enabled) + } +} +#[doc = "SPLL Clock Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllclken { + #[doc = "0: SPLL clock is disabled"] + Disabled = 0, + #[doc = "1: SPLL clock is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllclken) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLCLKEN` reader - SPLL Clock Enable"] +pub type SpllclkenR = crate::BitReader; +impl SpllclkenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllclken { + match self.bits { + false => Spllclken::Disabled, + true => Spllclken::Enabled, + } + } + #[doc = "SPLL clock is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Spllclken::Disabled + } + #[doc = "SPLL clock is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Spllclken::Enabled + } +} +#[doc = "Field `SPLLCLKEN` writer - SPLL Clock Enable"] +pub type SpllclkenW<'a, REG> = crate::BitWriter<'a, REG, Spllclken>; +impl<'a, REG> SpllclkenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPLL clock is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Spllclken::Disabled) + } + #[doc = "SPLL clock is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Spllclken::Enabled) + } +} +#[doc = "SPLL Stop Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllsten { + #[doc = "0: SPLL is disabled in Deep Sleep mode"] + DisabledInStop = 0, + #[doc = "1: SPLL is enabled in Deep Sleep mode"] + EnabledInStop = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllsten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLSTEN` reader - SPLL Stop Enable"] +pub type SpllstenR = crate::BitReader; +impl SpllstenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllsten { + match self.bits { + false => Spllsten::DisabledInStop, + true => Spllsten::EnabledInStop, + } + } + #[doc = "SPLL is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn is_disabled_in_stop(&self) -> bool { + *self == Spllsten::DisabledInStop + } + #[doc = "SPLL is enabled in Deep Sleep mode"] + #[inline(always)] + pub fn is_enabled_in_stop(&self) -> bool { + *self == Spllsten::EnabledInStop + } +} +#[doc = "Field `SPLLSTEN` writer - SPLL Stop Enable"] +pub type SpllstenW<'a, REG> = crate::BitWriter<'a, REG, Spllsten>; +impl<'a, REG> SpllstenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPLL is disabled in Deep Sleep mode"] + #[inline(always)] + pub fn disabled_in_stop(self) -> &'a mut crate::W { + self.variant(Spllsten::DisabledInStop) + } + #[doc = "SPLL is enabled in Deep Sleep mode"] + #[inline(always)] + pub fn enabled_in_stop(self) -> &'a mut crate::W { + self.variant(Spllsten::EnabledInStop) + } +} +#[doc = "Free running mode clock stable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FrmClockstable { + #[doc = "0: Free running mode clock stable is disabled"] + Disabled = 0, + #[doc = "1: Free running mode clock stable is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FrmClockstable) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRM_CLOCKSTABLE` reader - Free running mode clock stable"] +pub type FrmClockstableR = crate::BitReader; +impl FrmClockstableR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FrmClockstable { + match self.bits { + false => FrmClockstable::Disabled, + true => FrmClockstable::Enabled, + } + } + #[doc = "Free running mode clock stable is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == FrmClockstable::Disabled + } + #[doc = "Free running mode clock stable is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == FrmClockstable::Enabled + } +} +#[doc = "Field `FRM_CLOCKSTABLE` writer - Free running mode clock stable"] +pub type FrmClockstableW<'a, REG> = crate::BitWriter<'a, REG, FrmClockstable>; +impl<'a, REG> FrmClockstableW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Free running mode clock stable is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(FrmClockstable::Disabled) + } + #[doc = "Free running mode clock stable is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(FrmClockstable::Enabled) + } +} +#[doc = "SPLL Clock Monitor\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllcm { + #[doc = "0: SPLL Clock Monitor is disabled"] + Disabled = 0, + #[doc = "1: SPLL Clock Monitor is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllcm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLCM` reader - SPLL Clock Monitor"] +pub type SpllcmR = crate::BitReader; +impl SpllcmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllcm { + match self.bits { + false => Spllcm::Disabled, + true => Spllcm::Enabled, + } + } + #[doc = "SPLL Clock Monitor is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Spllcm::Disabled + } + #[doc = "SPLL Clock Monitor is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Spllcm::Enabled + } +} +#[doc = "Field `SPLLCM` writer - SPLL Clock Monitor"] +pub type SpllcmW<'a, REG> = crate::BitWriter<'a, REG, Spllcm>; +impl<'a, REG> SpllcmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPLL Clock Monitor is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Spllcm::Disabled) + } + #[doc = "SPLL Clock Monitor is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Spllcm::Enabled) + } +} +#[doc = "SPLL Clock Monitor Reset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllcmre { + #[doc = "0: Clock monitor generates an interrupt when an error is detected"] + GenerateInterrupt = 0, + #[doc = "1: Clock monitor generates a reset when an error is detected"] + GenerateReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllcmre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLCMRE` reader - SPLL Clock Monitor Reset Enable"] +pub type SpllcmreR = crate::BitReader; +impl SpllcmreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllcmre { + match self.bits { + false => Spllcmre::GenerateInterrupt, + true => Spllcmre::GenerateReset, + } + } + #[doc = "Clock monitor generates an interrupt when an error is detected"] + #[inline(always)] + pub fn is_generate_interrupt(&self) -> bool { + *self == Spllcmre::GenerateInterrupt + } + #[doc = "Clock monitor generates a reset when an error is detected"] + #[inline(always)] + pub fn is_generate_reset(&self) -> bool { + *self == Spllcmre::GenerateReset + } +} +#[doc = "Field `SPLLCMRE` writer - SPLL Clock Monitor Reset Enable"] +pub type SpllcmreW<'a, REG> = crate::BitWriter<'a, REG, Spllcmre>; +impl<'a, REG> SpllcmreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Clock monitor generates an interrupt when an error is detected"] + #[inline(always)] + pub fn generate_interrupt(self) -> &'a mut crate::W { + self.variant(Spllcmre::GenerateInterrupt) + } + #[doc = "Clock monitor generates a reset when an error is detected"] + #[inline(always)] + pub fn generate_reset(self) -> &'a mut crate::W { + self.variant(Spllcmre::GenerateReset) + } +} +#[doc = "Lock Register\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lk { + #[doc = "0: Control Status Register can be written"] + WriteEnabled = 0, + #[doc = "1: Control Status Register cannot be written"] + WriteDisabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LK` reader - Lock Register"] +pub type LkR = crate::BitReader; +impl LkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lk { + match self.bits { + false => Lk::WriteEnabled, + true => Lk::WriteDisabled, + } + } + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn is_write_enabled(&self) -> bool { + *self == Lk::WriteEnabled + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn is_write_disabled(&self) -> bool { + *self == Lk::WriteDisabled + } +} +#[doc = "Field `LK` writer - Lock Register"] +pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; +impl<'a, REG> LkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Control Status Register can be written"] + #[inline(always)] + pub fn write_enabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteEnabled) + } + #[doc = "Control Status Register cannot be written"] + #[inline(always)] + pub fn write_disabled(self) -> &'a mut crate::W { + self.variant(Lk::WriteDisabled) + } +} +#[doc = "SPLL LOCK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SpllLock { + #[doc = "0: SPLL is not powered on or not locked"] + DisabledOrNotValid = 0, + #[doc = "1: SPLL is locked"] + EnabledAndValid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SpllLock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLL_LOCK` reader - SPLL LOCK"] +pub type SpllLockR = crate::BitReader; +impl SpllLockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SpllLock { + match self.bits { + false => SpllLock::DisabledOrNotValid, + true => SpllLock::EnabledAndValid, + } + } + #[doc = "SPLL is not powered on or not locked"] + #[inline(always)] + pub fn is_disabled_or_not_valid(&self) -> bool { + *self == SpllLock::DisabledOrNotValid + } + #[doc = "SPLL is locked"] + #[inline(always)] + pub fn is_enabled_and_valid(&self) -> bool { + *self == SpllLock::EnabledAndValid + } +} +#[doc = "SPLL Selected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllsel { + #[doc = "0: SPLL is not the system clock source"] + NotSpll = 0, + #[doc = "1: SPLL is the system clock source"] + Spll = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLSEL` reader - SPLL Selected"] +pub type SpllselR = crate::BitReader; +impl SpllselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllsel { + match self.bits { + false => Spllsel::NotSpll, + true => Spllsel::Spll, + } + } + #[doc = "SPLL is not the system clock source"] + #[inline(always)] + pub fn is_not_spll(&self) -> bool { + *self == Spllsel::NotSpll + } + #[doc = "SPLL is the system clock source"] + #[inline(always)] + pub fn is_spll(&self) -> bool { + *self == Spllsel::Spll + } +} +#[doc = "SPLL Clock Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Spllerr { + #[doc = "0: SPLL Clock Monitor is disabled or has not detected an error"] + DisabledOrNoError = 0, + #[doc = "1: SPLL Clock Monitor is enabled and detected an error"] + EnabledAndError = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Spllerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLLERR` reader - SPLL Clock Error"] +pub type SpllerrR = crate::BitReader; +impl SpllerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Spllerr { + match self.bits { + false => Spllerr::DisabledOrNoError, + true => Spllerr::EnabledAndError, + } + } + #[doc = "SPLL Clock Monitor is disabled or has not detected an error"] + #[inline(always)] + pub fn is_disabled_or_no_error(&self) -> bool { + *self == Spllerr::DisabledOrNoError + } + #[doc = "SPLL Clock Monitor is enabled and detected an error"] + #[inline(always)] + pub fn is_enabled_and_error(&self) -> bool { + *self == Spllerr::EnabledAndError + } +} +#[doc = "Field `SPLLERR` writer - SPLL Clock Error"] +pub type SpllerrW<'a, REG> = crate::BitWriter1C<'a, REG, Spllerr>; +impl<'a, REG> SpllerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPLL Clock Monitor is disabled or has not detected an error"] + #[inline(always)] + pub fn disabled_or_no_error(self) -> &'a mut crate::W { + self.variant(Spllerr::DisabledOrNoError) + } + #[doc = "SPLL Clock Monitor is enabled and detected an error"] + #[inline(always)] + pub fn enabled_and_error(self) -> &'a mut crate::W { + self.variant(Spllerr::EnabledAndError) + } +} +#[doc = "SPLL LOCK Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SpllLockIe { + #[doc = "0: SPLL_LOCK interrupt is not enabled"] + NotSpll = 0, + #[doc = "1: SPLL_LOCK interrupt is enabled"] + Spll = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SpllLockIe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPLL_LOCK_IE` reader - SPLL LOCK Interrupt Enable"] +pub type SpllLockIeR = crate::BitReader; +impl SpllLockIeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SpllLockIe { + match self.bits { + false => SpllLockIe::NotSpll, + true => SpllLockIe::Spll, + } + } + #[doc = "SPLL_LOCK interrupt is not enabled"] + #[inline(always)] + pub fn is_not_spll(&self) -> bool { + *self == SpllLockIe::NotSpll + } + #[doc = "SPLL_LOCK interrupt is enabled"] + #[inline(always)] + pub fn is_spll(&self) -> bool { + *self == SpllLockIe::Spll + } +} +#[doc = "Field `SPLL_LOCK_IE` writer - SPLL LOCK Interrupt Enable"] +pub type SpllLockIeW<'a, REG> = crate::BitWriter<'a, REG, SpllLockIe>; +impl<'a, REG> SpllLockIeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPLL_LOCK interrupt is not enabled"] + #[inline(always)] + pub fn not_spll(self) -> &'a mut crate::W { + self.variant(SpllLockIe::NotSpll) + } + #[doc = "SPLL_LOCK interrupt is enabled"] + #[inline(always)] + pub fn spll(self) -> &'a mut crate::W { + self.variant(SpllLockIe::Spll) + } +} +impl R { + #[doc = "Bit 0 - SPLL Power Enable"] + #[inline(always)] + pub fn spllpwren(&self) -> SpllpwrenR { + SpllpwrenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPLL Clock Enable"] + #[inline(always)] + pub fn spllclken(&self) -> SpllclkenR { + SpllclkenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPLL Stop Enable"] + #[inline(always)] + pub fn spllsten(&self) -> SpllstenR { + SpllstenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Free running mode clock stable"] + #[inline(always)] + pub fn frm_clockstable(&self) -> FrmClockstableR { + FrmClockstableR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 16 - SPLL Clock Monitor"] + #[inline(always)] + pub fn spllcm(&self) -> SpllcmR { + SpllcmR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SPLL Clock Monitor Reset Enable"] + #[inline(always)] + pub fn spllcmre(&self) -> SpllcmreR { + SpllcmreR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&self) -> LkR { + LkR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SPLL LOCK"] + #[inline(always)] + pub fn spll_lock(&self) -> SpllLockR { + SpllLockR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - SPLL Selected"] + #[inline(always)] + pub fn spllsel(&self) -> SpllselR { + SpllselR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - SPLL Clock Error"] + #[inline(always)] + pub fn spllerr(&self) -> SpllerrR { + SpllerrR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - SPLL LOCK Interrupt Enable"] + #[inline(always)] + pub fn spll_lock_ie(&self) -> SpllLockIeR { + SpllLockIeR::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SPLL Power Enable"] + #[inline(always)] + pub fn spllpwren(&mut self) -> SpllpwrenW { + SpllpwrenW::new(self, 0) + } + #[doc = "Bit 1 - SPLL Clock Enable"] + #[inline(always)] + pub fn spllclken(&mut self) -> SpllclkenW { + SpllclkenW::new(self, 1) + } + #[doc = "Bit 2 - SPLL Stop Enable"] + #[inline(always)] + pub fn spllsten(&mut self) -> SpllstenW { + SpllstenW::new(self, 2) + } + #[doc = "Bit 3 - Free running mode clock stable"] + #[inline(always)] + pub fn frm_clockstable(&mut self) -> FrmClockstableW { + FrmClockstableW::new(self, 3) + } + #[doc = "Bit 16 - SPLL Clock Monitor"] + #[inline(always)] + pub fn spllcm(&mut self) -> SpllcmW { + SpllcmW::new(self, 16) + } + #[doc = "Bit 17 - SPLL Clock Monitor Reset Enable"] + #[inline(always)] + pub fn spllcmre(&mut self) -> SpllcmreW { + SpllcmreW::new(self, 17) + } + #[doc = "Bit 23 - Lock Register"] + #[inline(always)] + pub fn lk(&mut self) -> LkW { + LkW::new(self, 23) + } + #[doc = "Bit 26 - SPLL Clock Error"] + #[inline(always)] + pub fn spllerr(&mut self) -> SpllerrW { + SpllerrW::new(self, 26) + } + #[doc = "Bit 30 - SPLL LOCK Interrupt Enable"] + #[inline(always)] + pub fn spll_lock_ie(&mut self) -> SpllLockIeW { + SpllLockIeW::new(self, 30) + } +} +#[doc = "SPLL Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpllcsrSpec; +impl crate::RegisterSpec for SpllcsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllcsr::R`](R) reader structure"] +impl crate::Readable for SpllcsrSpec {} +#[doc = "`write(|w| ..)` method takes [`spllcsr::W`](W) writer structure"] +impl crate::Writable for SpllcsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; +} +#[doc = "`reset()` method sets SPLLCSR to value 0"] +impl crate::Resettable for SpllcsrSpec {} diff --git a/mcxa276-pac/src/scg0/spllctrl.rs b/mcxa276-pac/src/scg0/spllctrl.rs new file mode 100644 index 000000000..7d0a8271e --- /dev/null +++ b/mcxa276-pac/src/scg0/spllctrl.rs @@ -0,0 +1,537 @@ +#[doc = "Register `SPLLCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SELR` reader - Bandwidth select R (resistor) value."] +pub type SelrR = crate::FieldReader; +#[doc = "Field `SELR` writer - Bandwidth select R (resistor) value."] +pub type SelrW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SELI` reader - Bandwidth select I (interation) value."] +pub type SeliR = crate::FieldReader; +#[doc = "Field `SELI` writer - Bandwidth select I (interation) value."] +pub type SeliW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SELP` reader - Bandwidth select P (proportional) value."] +pub type SelpR = crate::FieldReader; +#[doc = "Field `SELP` writer - Bandwidth select P (proportional) value."] +pub type SelpW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Bypass of the divide-by-2 divider\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bypasspostdiv2 { + #[doc = "0: Use the divide-by-2 divider in the post-divider."] + NotBypassed = 0, + #[doc = "1: Bypass of the divide-by-2 divider in the post-divider."] + Bypassed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bypasspostdiv2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BYPASSPOSTDIV2` reader - Bypass of the divide-by-2 divider"] +pub type Bypasspostdiv2R = crate::BitReader; +impl Bypasspostdiv2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bypasspostdiv2 { + match self.bits { + false => Bypasspostdiv2::NotBypassed, + true => Bypasspostdiv2::Bypassed, + } + } + #[doc = "Use the divide-by-2 divider in the post-divider."] + #[inline(always)] + pub fn is_not_bypassed(&self) -> bool { + *self == Bypasspostdiv2::NotBypassed + } + #[doc = "Bypass of the divide-by-2 divider in the post-divider."] + #[inline(always)] + pub fn is_bypassed(&self) -> bool { + *self == Bypasspostdiv2::Bypassed + } +} +#[doc = "Field `BYPASSPOSTDIV2` writer - Bypass of the divide-by-2 divider"] +pub type Bypasspostdiv2W<'a, REG> = crate::BitWriter<'a, REG, Bypasspostdiv2>; +impl<'a, REG> Bypasspostdiv2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Use the divide-by-2 divider in the post-divider."] + #[inline(always)] + pub fn not_bypassed(self) -> &'a mut crate::W { + self.variant(Bypasspostdiv2::NotBypassed) + } + #[doc = "Bypass of the divide-by-2 divider in the post-divider."] + #[inline(always)] + pub fn bypassed(self) -> &'a mut crate::W { + self.variant(Bypasspostdiv2::Bypassed) + } +} +#[doc = "Up Limiter.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Limupoff { + #[doc = "0: Application set to non Spectrum and Fractional applications."] + Disabled = 0, + #[doc = "1: Application set to Spectrum and Fractional applications."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Limupoff) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LIMUPOFF` reader - Up Limiter."] +pub type LimupoffR = crate::BitReader; +impl LimupoffR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Limupoff { + match self.bits { + false => Limupoff::Disabled, + true => Limupoff::Enabled, + } + } + #[doc = "Application set to non Spectrum and Fractional applications."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Limupoff::Disabled + } + #[doc = "Application set to Spectrum and Fractional applications."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Limupoff::Enabled + } +} +#[doc = "Field `LIMUPOFF` writer - Up Limiter."] +pub type LimupoffW<'a, REG> = crate::BitWriter<'a, REG, Limupoff>; +impl<'a, REG> LimupoffW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Application set to non Spectrum and Fractional applications."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Limupoff::Disabled) + } + #[doc = "Application set to Spectrum and Fractional applications."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Limupoff::Enabled) + } +} +#[doc = "Control of the bandwidth of the PLL.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Banddirect { + #[doc = "0: The bandwidth is changed synchronously with the feedback-divider"] + Disabled = 0, + #[doc = "1: Modifies the bandwidth of the PLL directly"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Banddirect) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BANDDIRECT` reader - Control of the bandwidth of the PLL."] +pub type BanddirectR = crate::BitReader; +impl BanddirectR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Banddirect { + match self.bits { + false => Banddirect::Disabled, + true => Banddirect::Enabled, + } + } + #[doc = "The bandwidth is changed synchronously with the feedback-divider"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Banddirect::Disabled + } + #[doc = "Modifies the bandwidth of the PLL directly"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Banddirect::Enabled + } +} +#[doc = "Field `BANDDIRECT` writer - Control of the bandwidth of the PLL."] +pub type BanddirectW<'a, REG> = crate::BitWriter<'a, REG, Banddirect>; +impl<'a, REG> BanddirectW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The bandwidth is changed synchronously with the feedback-divider"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Banddirect::Disabled) + } + #[doc = "Modifies the bandwidth of the PLL directly"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Banddirect::Enabled) + } +} +#[doc = "Bypass of the pre-divider.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bypassprediv { + #[doc = "0: Use the pre-divider"] + Disabled = 0, + #[doc = "1: Bypass of the pre-divider"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bypassprediv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BYPASSPREDIV` reader - Bypass of the pre-divider."] +pub type BypasspredivR = crate::BitReader; +impl BypasspredivR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bypassprediv { + match self.bits { + false => Bypassprediv::Disabled, + true => Bypassprediv::Enabled, + } + } + #[doc = "Use the pre-divider"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Bypassprediv::Disabled + } + #[doc = "Bypass of the pre-divider"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Bypassprediv::Enabled + } +} +#[doc = "Field `BYPASSPREDIV` writer - Bypass of the pre-divider."] +pub type BypasspredivW<'a, REG> = crate::BitWriter<'a, REG, Bypassprediv>; +impl<'a, REG> BypasspredivW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Use the pre-divider"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Bypassprediv::Disabled) + } + #[doc = "Bypass of the pre-divider"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Bypassprediv::Enabled) + } +} +#[doc = "Bypass of the post-divider.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bypasspostdiv { + #[doc = "0: Use the post-divider"] + Disabled = 0, + #[doc = "1: Bypass of the post-divider"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bypasspostdiv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BYPASSPOSTDIV` reader - Bypass of the post-divider."] +pub type BypasspostdivR = crate::BitReader; +impl BypasspostdivR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bypasspostdiv { + match self.bits { + false => Bypasspostdiv::Disabled, + true => Bypasspostdiv::Enabled, + } + } + #[doc = "Use the post-divider"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Bypasspostdiv::Disabled + } + #[doc = "Bypass of the post-divider"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Bypasspostdiv::Enabled + } +} +#[doc = "Field `BYPASSPOSTDIV` writer - Bypass of the post-divider."] +pub type BypasspostdivW<'a, REG> = crate::BitWriter<'a, REG, Bypasspostdiv>; +impl<'a, REG> BypasspostdivW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Use the post-divider"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Bypasspostdiv::Disabled) + } + #[doc = "Bypass of the post-divider"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Bypasspostdiv::Enabled) + } +} +#[doc = "Free Running Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frm { + #[doc = "0: Free running mode disabled"] + Disabled = 0, + #[doc = "1: Free running mode enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRM` reader - Free Running Mode Enable"] +pub type FrmR = crate::BitReader; +impl FrmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frm { + match self.bits { + false => Frm::Disabled, + true => Frm::Enabled, + } + } + #[doc = "Free running mode disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Frm::Disabled + } + #[doc = "Free running mode enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Frm::Enabled + } +} +#[doc = "Field `FRM` writer - Free Running Mode Enable"] +pub type FrmW<'a, REG> = crate::BitWriter<'a, REG, Frm>; +impl<'a, REG> FrmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Free running mode disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Frm::Disabled) + } + #[doc = "Free running mode enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Frm::Enabled) + } +} +#[doc = "Clock Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Source { + #[doc = "0: SOSC"] + Sosc = 0, + #[doc = "1: FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."] + Firc = 1, + #[doc = "2: ROSC"] + Rsvd = 2, + #[doc = "3: SIRC 12 MHz clock"] + Sirc = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Source) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Source { + type Ux = u8; +} +impl crate::IsEnum for Source {} +#[doc = "Field `SOURCE` reader - Clock Source"] +pub type SourceR = crate::FieldReader; +impl SourceR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Source { + match self.bits { + 0 => Source::Sosc, + 1 => Source::Firc, + 2 => Source::Rsvd, + 3 => Source::Sirc, + _ => unreachable!(), + } + } + #[doc = "SOSC"] + #[inline(always)] + pub fn is_sosc(&self) -> bool { + *self == Source::Sosc + } + #[doc = "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."] + #[inline(always)] + pub fn is_firc(&self) -> bool { + *self == Source::Firc + } + #[doc = "ROSC"] + #[inline(always)] + pub fn is_rsvd(&self) -> bool { + *self == Source::Rsvd + } + #[doc = "SIRC 12 MHz clock"] + #[inline(always)] + pub fn is_sirc(&self) -> bool { + *self == Source::Sirc + } +} +#[doc = "Field `SOURCE` writer - Clock Source"] +pub type SourceW<'a, REG> = crate::FieldWriter<'a, REG, 2, Source, crate::Safe>; +impl<'a, REG> SourceW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "SOSC"] + #[inline(always)] + pub fn sosc(self) -> &'a mut crate::W { + self.variant(Source::Sosc) + } + #[doc = "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."] + #[inline(always)] + pub fn firc(self) -> &'a mut crate::W { + self.variant(Source::Firc) + } + #[doc = "ROSC"] + #[inline(always)] + pub fn rsvd(self) -> &'a mut crate::W { + self.variant(Source::Rsvd) + } + #[doc = "SIRC 12 MHz clock"] + #[inline(always)] + pub fn sirc(self) -> &'a mut crate::W { + self.variant(Source::Sirc) + } +} +impl R { + #[doc = "Bits 0:3 - Bandwidth select R (resistor) value."] + #[inline(always)] + pub fn selr(&self) -> SelrR { + SelrR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9 - Bandwidth select I (interation) value."] + #[inline(always)] + pub fn seli(&self) -> SeliR { + SeliR::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:14 - Bandwidth select P (proportional) value."] + #[inline(always)] + pub fn selp(&self) -> SelpR { + SelpR::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bit 16 - Bypass of the divide-by-2 divider"] + #[inline(always)] + pub fn bypasspostdiv2(&self) -> Bypasspostdiv2R { + Bypasspostdiv2R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Up Limiter."] + #[inline(always)] + pub fn limupoff(&self) -> LimupoffR { + LimupoffR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Control of the bandwidth of the PLL."] + #[inline(always)] + pub fn banddirect(&self) -> BanddirectR { + BanddirectR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Bypass of the pre-divider."] + #[inline(always)] + pub fn bypassprediv(&self) -> BypasspredivR { + BypasspredivR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Bypass of the post-divider."] + #[inline(always)] + pub fn bypasspostdiv(&self) -> BypasspostdivR { + BypasspostdivR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 22 - Free Running Mode Enable"] + #[inline(always)] + pub fn frm(&self) -> FrmR { + FrmR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 25:26 - Clock Source"] + #[inline(always)] + pub fn source(&self) -> SourceR { + SourceR::new(((self.bits >> 25) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Bandwidth select R (resistor) value."] + #[inline(always)] + pub fn selr(&mut self) -> SelrW { + SelrW::new(self, 0) + } + #[doc = "Bits 4:9 - Bandwidth select I (interation) value."] + #[inline(always)] + pub fn seli(&mut self) -> SeliW { + SeliW::new(self, 4) + } + #[doc = "Bits 10:14 - Bandwidth select P (proportional) value."] + #[inline(always)] + pub fn selp(&mut self) -> SelpW { + SelpW::new(self, 10) + } + #[doc = "Bit 16 - Bypass of the divide-by-2 divider"] + #[inline(always)] + pub fn bypasspostdiv2(&mut self) -> Bypasspostdiv2W { + Bypasspostdiv2W::new(self, 16) + } + #[doc = "Bit 17 - Up Limiter."] + #[inline(always)] + pub fn limupoff(&mut self) -> LimupoffW { + LimupoffW::new(self, 17) + } + #[doc = "Bit 18 - Control of the bandwidth of the PLL."] + #[inline(always)] + pub fn banddirect(&mut self) -> BanddirectW { + BanddirectW::new(self, 18) + } + #[doc = "Bit 19 - Bypass of the pre-divider."] + #[inline(always)] + pub fn bypassprediv(&mut self) -> BypasspredivW { + BypasspredivW::new(self, 19) + } + #[doc = "Bit 20 - Bypass of the post-divider."] + #[inline(always)] + pub fn bypasspostdiv(&mut self) -> BypasspostdivW { + BypasspostdivW::new(self, 20) + } + #[doc = "Bit 22 - Free Running Mode Enable"] + #[inline(always)] + pub fn frm(&mut self) -> FrmW { + FrmW::new(self, 22) + } + #[doc = "Bits 25:26 - Clock Source"] + #[inline(always)] + pub fn source(&mut self) -> SourceW { + SourceW::new(self, 25) + } +} +#[doc = "SPLL Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpllctrlSpec; +impl crate::RegisterSpec for SpllctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllctrl::R`](R) reader structure"] +impl crate::Readable for SpllctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`spllctrl::W`](W) writer structure"] +impl crate::Writable for SpllctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPLLCTRL to value 0"] +impl crate::Resettable for SpllctrlSpec {} diff --git a/mcxa276-pac/src/scg0/splllock_cnfg.rs b/mcxa276-pac/src/scg0/splllock_cnfg.rs new file mode 100644 index 000000000..7fca38584 --- /dev/null +++ b/mcxa276-pac/src/scg0/splllock_cnfg.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SPLLLOCK_CNFG` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLLOCK_CNFG` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_TIME` reader - Configures the number of reference clocks to count before SPLL is considered locked."] +pub type LockTimeR = crate::FieldReader; +#[doc = "Field `LOCK_TIME` writer - Configures the number of reference clocks to count before SPLL is considered locked."] +pub type LockTimeW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - Configures the number of reference clocks to count before SPLL is considered locked."] + #[inline(always)] + pub fn lock_time(&self) -> LockTimeR { + LockTimeR::new(self.bits & 0x0001_ffff) + } +} +impl W { + #[doc = "Bits 0:16 - Configures the number of reference clocks to count before SPLL is considered locked."] + #[inline(always)] + pub fn lock_time(&mut self) -> LockTimeW { + LockTimeW::new(self, 0) + } +} +#[doc = "SPLL LOCK Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`splllock_cnfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`splllock_cnfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SplllockCnfgSpec; +impl crate::RegisterSpec for SplllockCnfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`splllock_cnfg::R`](R) reader structure"] +impl crate::Readable for SplllockCnfgSpec {} +#[doc = "`write(|w| ..)` method takes [`splllock_cnfg::W`](W) writer structure"] +impl crate::Writable for SplllockCnfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPLLLOCK_CNFG to value 0x4f4c"] +impl crate::Resettable for SplllockCnfgSpec { + const RESET_VALUE: u32 = 0x4f4c; +} diff --git a/mcxa276-pac/src/scg0/spllmdiv.rs b/mcxa276-pac/src/scg0/spllmdiv.rs new file mode 100644 index 000000000..7a3b1a4bf --- /dev/null +++ b/mcxa276-pac/src/scg0/spllmdiv.rs @@ -0,0 +1,100 @@ +#[doc = "Register `SPLLMDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLMDIV` writer"] +pub type W = crate::W; +#[doc = "Field `MDIV` reader - Feedback divider ratio (M-divider)."] +pub type MdivR = crate::FieldReader; +#[doc = "Field `MDIV` writer - Feedback divider ratio (M-divider)."] +pub type MdivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Feedback ratio change request.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mreq { + #[doc = "0: Feedback ratio change is not requested"] + Disabled = 0, + #[doc = "1: Feedback ratio change is requested"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mreq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MREQ` reader - Feedback ratio change request."] +pub type MreqR = crate::BitReader; +impl MreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mreq { + match self.bits { + false => Mreq::Disabled, + true => Mreq::Enabled, + } + } + #[doc = "Feedback ratio change is not requested"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mreq::Disabled + } + #[doc = "Feedback ratio change is requested"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mreq::Enabled + } +} +#[doc = "Field `MREQ` writer - Feedback ratio change request."] +pub type MreqW<'a, REG> = crate::BitWriter<'a, REG, Mreq>; +impl<'a, REG> MreqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Feedback ratio change is not requested"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mreq::Disabled) + } + #[doc = "Feedback ratio change is requested"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mreq::Enabled) + } +} +impl R { + #[doc = "Bits 0:15 - Feedback divider ratio (M-divider)."] + #[inline(always)] + pub fn mdiv(&self) -> MdivR { + MdivR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 31 - Feedback ratio change request."] + #[inline(always)] + pub fn mreq(&self) -> MreqR { + MreqR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Feedback divider ratio (M-divider)."] + #[inline(always)] + pub fn mdiv(&mut self) -> MdivW { + MdivW::new(self, 0) + } + #[doc = "Bit 31 - Feedback ratio change request."] + #[inline(always)] + pub fn mreq(&mut self) -> MreqW { + MreqW::new(self, 31) + } +} +#[doc = "SPLL M Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllmdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllmdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpllmdivSpec; +impl crate::RegisterSpec for SpllmdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllmdiv::R`](R) reader structure"] +impl crate::Readable for SpllmdivSpec {} +#[doc = "`write(|w| ..)` method takes [`spllmdiv::W`](W) writer structure"] +impl crate::Writable for SpllmdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPLLMDIV to value 0x01"] +impl crate::Resettable for SpllmdivSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/scg0/spllndiv.rs b/mcxa276-pac/src/scg0/spllndiv.rs new file mode 100644 index 000000000..5b1e0c22d --- /dev/null +++ b/mcxa276-pac/src/scg0/spllndiv.rs @@ -0,0 +1,100 @@ +#[doc = "Register `SPLLNDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLNDIV` writer"] +pub type W = crate::W; +#[doc = "Field `NDIV` reader - Pre-divider divider ratio (N-divider)."] +pub type NdivR = crate::FieldReader; +#[doc = "Field `NDIV` writer - Pre-divider divider ratio (N-divider)."] +pub type NdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Pre-divider ratio change request.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nreq { + #[doc = "0: Pre-divider ratio change is not requested"] + Disabled = 0, + #[doc = "1: Pre-divider ratio change is requested"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nreq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NREQ` reader - Pre-divider ratio change request."] +pub type NreqR = crate::BitReader; +impl NreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nreq { + match self.bits { + false => Nreq::Disabled, + true => Nreq::Enabled, + } + } + #[doc = "Pre-divider ratio change is not requested"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Nreq::Disabled + } + #[doc = "Pre-divider ratio change is requested"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Nreq::Enabled + } +} +#[doc = "Field `NREQ` writer - Pre-divider ratio change request."] +pub type NreqW<'a, REG> = crate::BitWriter<'a, REG, Nreq>; +impl<'a, REG> NreqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pre-divider ratio change is not requested"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Nreq::Disabled) + } + #[doc = "Pre-divider ratio change is requested"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Nreq::Enabled) + } +} +impl R { + #[doc = "Bits 0:7 - Pre-divider divider ratio (N-divider)."] + #[inline(always)] + pub fn ndiv(&self) -> NdivR { + NdivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31 - Pre-divider ratio change request."] + #[inline(always)] + pub fn nreq(&self) -> NreqR { + NreqR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Pre-divider divider ratio (N-divider)."] + #[inline(always)] + pub fn ndiv(&mut self) -> NdivW { + NdivW::new(self, 0) + } + #[doc = "Bit 31 - Pre-divider ratio change request."] + #[inline(always)] + pub fn nreq(&mut self) -> NreqW { + NreqW::new(self, 31) + } +} +#[doc = "SPLL N Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllndiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllndiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpllndivSpec; +impl crate::RegisterSpec for SpllndivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllndiv::R`](R) reader structure"] +impl crate::Readable for SpllndivSpec {} +#[doc = "`write(|w| ..)` method takes [`spllndiv::W`](W) writer structure"] +impl crate::Writable for SpllndivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPLLNDIV to value 0x01"] +impl crate::Resettable for SpllndivSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/scg0/spllpdiv.rs b/mcxa276-pac/src/scg0/spllpdiv.rs new file mode 100644 index 000000000..ed46e330f --- /dev/null +++ b/mcxa276-pac/src/scg0/spllpdiv.rs @@ -0,0 +1,100 @@ +#[doc = "Register `SPLLPDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLPDIV` writer"] +pub type W = crate::W; +#[doc = "Field `PDIV` reader - Post-divider divider ratio (P-divider)"] +pub type PdivR = crate::FieldReader; +#[doc = "Field `PDIV` writer - Post-divider divider ratio (P-divider)"] +pub type PdivW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Post-divider ratio change request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Preq { + #[doc = "0: Post-divider ratio change is not requested"] + Disabled = 0, + #[doc = "1: Post-divider ratio change is requested"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Preq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PREQ` reader - Post-divider ratio change request"] +pub type PreqR = crate::BitReader; +impl PreqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Preq { + match self.bits { + false => Preq::Disabled, + true => Preq::Enabled, + } + } + #[doc = "Post-divider ratio change is not requested"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Preq::Disabled + } + #[doc = "Post-divider ratio change is requested"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Preq::Enabled + } +} +#[doc = "Field `PREQ` writer - Post-divider ratio change request"] +pub type PreqW<'a, REG> = crate::BitWriter<'a, REG, Preq>; +impl<'a, REG> PreqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Post-divider ratio change is not requested"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Preq::Disabled) + } + #[doc = "Post-divider ratio change is requested"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Preq::Enabled) + } +} +impl R { + #[doc = "Bits 0:4 - Post-divider divider ratio (P-divider)"] + #[inline(always)] + pub fn pdiv(&self) -> PdivR { + PdivR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Post-divider ratio change request"] + #[inline(always)] + pub fn preq(&self) -> PreqR { + PreqR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Post-divider divider ratio (P-divider)"] + #[inline(always)] + pub fn pdiv(&mut self) -> PdivW { + PdivW::new(self, 0) + } + #[doc = "Bit 31 - Post-divider ratio change request"] + #[inline(always)] + pub fn preq(&mut self) -> PreqW { + PreqW::new(self, 31) + } +} +#[doc = "SPLL P Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllpdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllpdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpllpdivSpec; +impl crate::RegisterSpec for SpllpdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllpdiv::R`](R) reader structure"] +impl crate::Readable for SpllpdivSpec {} +#[doc = "`write(|w| ..)` method takes [`spllpdiv::W`](W) writer structure"] +impl crate::Writable for SpllpdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPLLPDIV to value 0x01"] +impl crate::Resettable for SpllpdivSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/scg0/spllsscg0.rs b/mcxa276-pac/src/scg0/spllsscg0.rs new file mode 100644 index 000000000..44fdf274e --- /dev/null +++ b/mcxa276-pac/src/scg0/spllsscg0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SPLLSSCG0` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLSSCG0` writer"] +pub type W = crate::W; +#[doc = "Field `SS_MDIV_LSB` reader - SS_MDIV\\[31:0\\]"] +pub type SsMdivLsbR = crate::FieldReader; +#[doc = "Field `SS_MDIV_LSB` writer - SS_MDIV\\[31:0\\]"] +pub type SsMdivLsbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - SS_MDIV\\[31:0\\]"] + #[inline(always)] + pub fn ss_mdiv_lsb(&self) -> SsMdivLsbR { + SsMdivLsbR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - SS_MDIV\\[31:0\\]"] + #[inline(always)] + pub fn ss_mdiv_lsb(&mut self) -> SsMdivLsbW { + SsMdivLsbW::new(self, 0) + } +} +#[doc = "SPLL Spread Spectrum Control 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Spllsscg0Spec; +impl crate::RegisterSpec for Spllsscg0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllsscg0::R`](R) reader structure"] +impl crate::Readable for Spllsscg0Spec {} +#[doc = "`write(|w| ..)` method takes [`spllsscg0::W`](W) writer structure"] +impl crate::Writable for Spllsscg0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPLLSSCG0 to value 0"] +impl crate::Resettable for Spllsscg0Spec {} diff --git a/mcxa276-pac/src/scg0/spllsscg1.rs b/mcxa276-pac/src/scg0/spllsscg1.rs new file mode 100644 index 000000000..aebacacbf --- /dev/null +++ b/mcxa276-pac/src/scg0/spllsscg1.rs @@ -0,0 +1,331 @@ +#[doc = "Register `SPLLSSCG1` reader"] +pub type R = crate::R; +#[doc = "Register `SPLLSSCG1` writer"] +pub type W = crate::W; +#[doc = "Field `SS_MDIV_MSB` reader - SS_MDIV\\[32\\]"] +pub type SsMdivMsbR = crate::BitReader; +#[doc = "Field `SS_MDIV_MSB` writer - SS_MDIV\\[32\\]"] +pub type SsMdivMsbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "SS_MDIV\\[32:0\\] change request.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SsMdivReq { + #[doc = "0: SS_MDIV change is not requested"] + Disabled = 0, + #[doc = "1: SS_MDIV change is requested"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SsMdivReq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SS_MDIV_REQ` reader - SS_MDIV\\[32:0\\] change request."] +pub type SsMdivReqR = crate::BitReader; +impl SsMdivReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SsMdivReq { + match self.bits { + false => SsMdivReq::Disabled, + true => SsMdivReq::Enabled, + } + } + #[doc = "SS_MDIV change is not requested"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SsMdivReq::Disabled + } + #[doc = "SS_MDIV change is requested"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SsMdivReq::Enabled + } +} +#[doc = "Field `SS_MDIV_REQ` writer - SS_MDIV\\[32:0\\] change request."] +pub type SsMdivReqW<'a, REG> = crate::BitWriter<'a, REG, SsMdivReq>; +impl<'a, REG> SsMdivReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SS_MDIV change is not requested"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(SsMdivReq::Disabled) + } + #[doc = "SS_MDIV change is requested"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(SsMdivReq::Enabled) + } +} +#[doc = "Field `MF` reader - Modulation Frequency Control"] +pub type MfR = crate::FieldReader; +#[doc = "Field `MF` writer - Modulation Frequency Control"] +pub type MfW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MR` reader - Modulation Depth Control"] +pub type MrR = crate::FieldReader; +#[doc = "Field `MR` writer - Modulation Depth Control"] +pub type MrW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MC` reader - Modulation Waveform Control"] +pub type McR = crate::FieldReader; +#[doc = "Field `MC` writer - Modulation Waveform Control"] +pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Dither Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dither { + #[doc = "0: Dither is not enabled"] + Disabled = 0, + #[doc = "1: Dither is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dither) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DITHER` reader - Dither Enable"] +pub type DitherR = crate::BitReader; +impl DitherR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dither { + match self.bits { + false => Dither::Disabled, + true => Dither::Enabled, + } + } + #[doc = "Dither is not enabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Dither::Disabled + } + #[doc = "Dither is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Dither::Enabled + } +} +#[doc = "Field `DITHER` writer - Dither Enable"] +pub type DitherW<'a, REG> = crate::BitWriter<'a, REG, Dither>; +impl<'a, REG> DitherW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Dither is not enabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Dither::Disabled) + } + #[doc = "Dither is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Dither::Enabled) + } +} +#[doc = "SS_MDIV select.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SelSsMdiv { + #[doc = "0: Feedback divider ratio is MDIV\\[15:0\\]"] + Disabled = 0, + #[doc = "1: Feedback divider ratio is SS_MDIV\\[32:0\\]"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SelSsMdiv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEL_SS_MDIV` reader - SS_MDIV select."] +pub type SelSsMdivR = crate::BitReader; +impl SelSsMdivR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SelSsMdiv { + match self.bits { + false => SelSsMdiv::Disabled, + true => SelSsMdiv::Enabled, + } + } + #[doc = "Feedback divider ratio is MDIV\\[15:0\\]"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SelSsMdiv::Disabled + } + #[doc = "Feedback divider ratio is SS_MDIV\\[32:0\\]"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SelSsMdiv::Enabled + } +} +#[doc = "Field `SEL_SS_MDIV` writer - SS_MDIV select."] +pub type SelSsMdivW<'a, REG> = crate::BitWriter<'a, REG, SelSsMdiv>; +impl<'a, REG> SelSsMdivW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Feedback divider ratio is MDIV\\[15:0\\]"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(SelSsMdiv::Disabled) + } + #[doc = "Feedback divider ratio is SS_MDIV\\[32:0\\]"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(SelSsMdiv::Enabled) + } +} +#[doc = "SSCG Power Down\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SsPd { + #[doc = "0: SSCG is powered on"] + Disabled = 0, + #[doc = "1: SSCG is powered off"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SsPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SS_PD` reader - SSCG Power Down"] +pub type SsPdR = crate::BitReader; +impl SsPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SsPd { + match self.bits { + false => SsPd::Disabled, + true => SsPd::Enabled, + } + } + #[doc = "SSCG is powered on"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SsPd::Disabled + } + #[doc = "SSCG is powered off"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SsPd::Enabled + } +} +#[doc = "Field `SS_PD` writer - SSCG Power Down"] +pub type SsPdW<'a, REG> = crate::BitWriter<'a, REG, SsPd>; +impl<'a, REG> SsPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SSCG is powered on"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(SsPd::Disabled) + } + #[doc = "SSCG is powered off"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(SsPd::Enabled) + } +} +impl R { + #[doc = "Bit 0 - SS_MDIV\\[32\\]"] + #[inline(always)] + pub fn ss_mdiv_msb(&self) -> SsMdivMsbR { + SsMdivMsbR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SS_MDIV\\[32:0\\] change request."] + #[inline(always)] + pub fn ss_mdiv_req(&self) -> SsMdivReqR { + SsMdivReqR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Modulation Frequency Control"] + #[inline(always)] + pub fn mf(&self) -> MfR { + MfR::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bits 5:7 - Modulation Depth Control"] + #[inline(always)] + pub fn mr(&self) -> MrR { + MrR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:9 - Modulation Waveform Control"] + #[inline(always)] + pub fn mc(&self) -> McR { + McR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Dither Enable"] + #[inline(always)] + pub fn dither(&self) -> DitherR { + DitherR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SS_MDIV select."] + #[inline(always)] + pub fn sel_ss_mdiv(&self) -> SelSsMdivR { + SelSsMdivR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 31 - SSCG Power Down"] + #[inline(always)] + pub fn ss_pd(&self) -> SsPdR { + SsPdR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SS_MDIV\\[32\\]"] + #[inline(always)] + pub fn ss_mdiv_msb(&mut self) -> SsMdivMsbW { + SsMdivMsbW::new(self, 0) + } + #[doc = "Bit 1 - SS_MDIV\\[32:0\\] change request."] + #[inline(always)] + pub fn ss_mdiv_req(&mut self) -> SsMdivReqW { + SsMdivReqW::new(self, 1) + } + #[doc = "Bits 2:4 - Modulation Frequency Control"] + #[inline(always)] + pub fn mf(&mut self) -> MfW { + MfW::new(self, 2) + } + #[doc = "Bits 5:7 - Modulation Depth Control"] + #[inline(always)] + pub fn mr(&mut self) -> MrW { + MrW::new(self, 5) + } + #[doc = "Bits 8:9 - Modulation Waveform Control"] + #[inline(always)] + pub fn mc(&mut self) -> McW { + McW::new(self, 8) + } + #[doc = "Bit 10 - Dither Enable"] + #[inline(always)] + pub fn dither(&mut self) -> DitherW { + DitherW::new(self, 10) + } + #[doc = "Bit 11 - SS_MDIV select."] + #[inline(always)] + pub fn sel_ss_mdiv(&mut self) -> SelSsMdivW { + SelSsMdivW::new(self, 11) + } + #[doc = "Bit 31 - SSCG Power Down"] + #[inline(always)] + pub fn ss_pd(&mut self) -> SsPdW { + SsPdW::new(self, 31) + } +} +#[doc = "SPLL Spread Spectrum Control 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Spllsscg1Spec; +impl crate::RegisterSpec for Spllsscg1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllsscg1::R`](R) reader structure"] +impl crate::Readable for Spllsscg1Spec {} +#[doc = "`write(|w| ..)` method takes [`spllsscg1::W`](W) writer structure"] +impl crate::Writable for Spllsscg1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPLLSSCG1 to value 0x8000_0000"] +impl crate::Resettable for Spllsscg1Spec { + const RESET_VALUE: u32 = 0x8000_0000; +} diff --git a/mcxa276-pac/src/scg0/spllsscgstat.rs b/mcxa276-pac/src/scg0/spllsscgstat.rs new file mode 100644 index 000000000..7cc41dfaa --- /dev/null +++ b/mcxa276-pac/src/scg0/spllsscgstat.rs @@ -0,0 +1,54 @@ +#[doc = "Register `SPLLSSCGSTAT` reader"] +pub type R = crate::R; +#[doc = "SS_MDIV change acknowledge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SsMdivAck { + #[doc = "0: The SS_MDIV, MF, MR, MC ratio change is not accepted by the analog PLL"] + Disabled = 0, + #[doc = "1: The SS_MDIV, MF, MR, MC ratio change is accepted by the analog PLL"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SsMdivAck) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SS_MDIV_ACK` reader - SS_MDIV change acknowledge"] +pub type SsMdivAckR = crate::BitReader; +impl SsMdivAckR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SsMdivAck { + match self.bits { + false => SsMdivAck::Disabled, + true => SsMdivAck::Enabled, + } + } + #[doc = "The SS_MDIV, MF, MR, MC ratio change is not accepted by the analog PLL"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SsMdivAck::Disabled + } + #[doc = "The SS_MDIV, MF, MR, MC ratio change is accepted by the analog PLL"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SsMdivAck::Enabled + } +} +impl R { + #[doc = "Bit 0 - SS_MDIV change acknowledge"] + #[inline(always)] + pub fn ss_mdiv_ack(&self) -> SsMdivAckR { + SsMdivAckR::new((self.bits & 1) != 0) + } +} +#[doc = "SPLL SSCG Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscgstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpllsscgstatSpec; +impl crate::RegisterSpec for SpllsscgstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllsscgstat::R`](R) reader structure"] +impl crate::Readable for SpllsscgstatSpec {} +#[doc = "`reset()` method sets SPLLSSCGSTAT to value 0"] +impl crate::Resettable for SpllsscgstatSpec {} diff --git a/mcxa276-pac/src/scg0/spllstat.rs b/mcxa276-pac/src/scg0/spllstat.rs new file mode 100644 index 000000000..47967789c --- /dev/null +++ b/mcxa276-pac/src/scg0/spllstat.rs @@ -0,0 +1,177 @@ +#[doc = "Register `SPLLSTAT` reader"] +pub type R = crate::R; +#[doc = "Pre-divider (N) ratio change acknowledge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ndivack { + #[doc = "0: The Pre-divider (N) ratio change is not accepted by the analog PLL."] + Disabled = 0, + #[doc = "1: The Pre-divider (N) ratio change is accepted by the analog PLL."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ndivack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NDIVACK` reader - Pre-divider (N) ratio change acknowledge"] +pub type NdivackR = crate::BitReader; +impl NdivackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ndivack { + match self.bits { + false => Ndivack::Disabled, + true => Ndivack::Enabled, + } + } + #[doc = "The Pre-divider (N) ratio change is not accepted by the analog PLL."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Ndivack::Disabled + } + #[doc = "The Pre-divider (N) ratio change is accepted by the analog PLL."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Ndivack::Enabled + } +} +#[doc = "Feedback (M) divider ratio change acknowledge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mdivack { + #[doc = "0: The Feedback (M) ratio change is not accepted by the analog PLL."] + Disabled = 0, + #[doc = "1: The Feedback (M) ratio change is accepted by the analog PLL."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mdivack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MDIVACK` reader - Feedback (M) divider ratio change acknowledge"] +pub type MdivackR = crate::BitReader; +impl MdivackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mdivack { + match self.bits { + false => Mdivack::Disabled, + true => Mdivack::Enabled, + } + } + #[doc = "The Feedback (M) ratio change is not accepted by the analog PLL."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mdivack::Disabled + } + #[doc = "The Feedback (M) ratio change is accepted by the analog PLL."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mdivack::Enabled + } +} +#[doc = "Post-divider (P) ratio change acknowledge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pdivack { + #[doc = "0: The Post-divider (P) ratio change is not accepted by the analog PLL"] + Disabled = 0, + #[doc = "1: The Post-divider (P) ratio change is accepted by the analog PLL"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pdivack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDIVACK` reader - Post-divider (P) ratio change acknowledge"] +pub type PdivackR = crate::BitReader; +impl PdivackR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pdivack { + match self.bits { + false => Pdivack::Disabled, + true => Pdivack::Enabled, + } + } + #[doc = "The Post-divider (P) ratio change is not accepted by the analog PLL"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Pdivack::Disabled + } + #[doc = "The Post-divider (P) ratio change is accepted by the analog PLL"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Pdivack::Enabled + } +} +#[doc = "Free running detector (active high)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Frmdet { + #[doc = "0: Free running is not detected"] + Disabled = 0, + #[doc = "1: Free running is detected"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Frmdet) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRMDET` reader - Free running detector (active high)"] +pub type FrmdetR = crate::BitReader; +impl FrmdetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frmdet { + match self.bits { + false => Frmdet::Disabled, + true => Frmdet::Enabled, + } + } + #[doc = "Free running is not detected"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Frmdet::Disabled + } + #[doc = "Free running is detected"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Frmdet::Enabled + } +} +impl R { + #[doc = "Bit 1 - Pre-divider (N) ratio change acknowledge"] + #[inline(always)] + pub fn ndivack(&self) -> NdivackR { + NdivackR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Feedback (M) divider ratio change acknowledge"] + #[inline(always)] + pub fn mdivack(&self) -> MdivackR { + MdivackR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Post-divider (P) ratio change acknowledge"] + #[inline(always)] + pub fn pdivack(&self) -> PdivackR { + PdivackR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Free running detector (active high)"] + #[inline(always)] + pub fn frmdet(&self) -> FrmdetR { + FrmdetR::new(((self.bits >> 4) & 1) != 0) + } +} +#[doc = "SPLL Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpllstatSpec; +impl crate::RegisterSpec for SpllstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spllstat::R`](R) reader structure"] +impl crate::Readable for SpllstatSpec {} +#[doc = "`reset()` method sets SPLLSTAT to value 0"] +impl crate::Resettable for SpllstatSpec {} diff --git a/mcxa276-pac/src/scg0/trim_lock.rs b/mcxa276-pac/src/scg0/trim_lock.rs new file mode 100644 index 000000000..e10975210 --- /dev/null +++ b/mcxa276-pac/src/scg0/trim_lock.rs @@ -0,0 +1,161 @@ +#[doc = "Register `TRIM_LOCK` reader"] +pub type R = crate::R; +#[doc = "Register `TRIM_LOCK` writer"] +pub type W = crate::W; +#[doc = "TRIM_UNLOCK\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrimUnlock { + #[doc = "0: SCG Trim Registers locked and not writable."] + Locked = 0, + #[doc = "1: SCG Trim registers unlocked and writable."] + NotLocked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrimUnlock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIM_UNLOCK` reader - TRIM_UNLOCK"] +pub type TrimUnlockR = crate::BitReader; +impl TrimUnlockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrimUnlock { + match self.bits { + false => TrimUnlock::Locked, + true => TrimUnlock::NotLocked, + } + } + #[doc = "SCG Trim Registers locked and not writable."] + #[inline(always)] + pub fn is_locked(&self) -> bool { + *self == TrimUnlock::Locked + } + #[doc = "SCG Trim registers unlocked and writable."] + #[inline(always)] + pub fn is_not_locked(&self) -> bool { + *self == TrimUnlock::NotLocked + } +} +#[doc = "Field `TRIM_UNLOCK` writer - TRIM_UNLOCK"] +pub type TrimUnlockW<'a, REG> = crate::BitWriter<'a, REG, TrimUnlock>; +impl<'a, REG> TrimUnlockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SCG Trim Registers locked and not writable."] + #[inline(always)] + pub fn locked(self) -> &'a mut crate::W { + self.variant(TrimUnlock::Locked) + } + #[doc = "SCG Trim registers unlocked and writable."] + #[inline(always)] + pub fn not_locked(self) -> &'a mut crate::W { + self.variant(TrimUnlock::NotLocked) + } +} +#[doc = "IFR_DISABLE\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IfrDisable { + #[doc = "0: IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset."] + Enabled = 0, + #[doc = "1: IFR write access to SCG trim registers during system reset is blocked."] + Disabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IfrDisable) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IFR_DISABLE` reader - IFR_DISABLE"] +pub type IfrDisableR = crate::BitReader; +impl IfrDisableR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IfrDisable { + match self.bits { + false => IfrDisable::Enabled, + true => IfrDisable::Disabled, + } + } + #[doc = "IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IfrDisable::Enabled + } + #[doc = "IFR write access to SCG trim registers during system reset is blocked."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IfrDisable::Disabled + } +} +#[doc = "Field `IFR_DISABLE` writer - IFR_DISABLE"] +pub type IfrDisableW<'a, REG> = crate::BitWriter<'a, REG, IfrDisable>; +impl<'a, REG> IfrDisableW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(IfrDisable::Enabled) + } + #[doc = "IFR write access to SCG trim registers during system reset is blocked."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(IfrDisable::Disabled) + } +} +#[doc = "Field `TRIM_LOCK_KEY` reader - TRIM_LOCK_KEY"] +pub type TrimLockKeyR = crate::FieldReader; +#[doc = "Field `TRIM_LOCK_KEY` writer - TRIM_LOCK_KEY"] +pub type TrimLockKeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - TRIM_UNLOCK"] + #[inline(always)] + pub fn trim_unlock(&self) -> TrimUnlockR { + TrimUnlockR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - IFR_DISABLE"] + #[inline(always)] + pub fn ifr_disable(&self) -> IfrDisableR { + IfrDisableR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 16:31 - TRIM_LOCK_KEY"] + #[inline(always)] + pub fn trim_lock_key(&self) -> TrimLockKeyR { + TrimLockKeyR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - TRIM_UNLOCK"] + #[inline(always)] + pub fn trim_unlock(&mut self) -> TrimUnlockW { + TrimUnlockW::new(self, 0) + } + #[doc = "Bit 1 - IFR_DISABLE"] + #[inline(always)] + pub fn ifr_disable(&mut self) -> IfrDisableW { + IfrDisableW::new(self, 1) + } + #[doc = "Bits 16:31 - TRIM_LOCK_KEY"] + #[inline(always)] + pub fn trim_lock_key(&mut self) -> TrimLockKeyW { + TrimLockKeyW::new(self, 16) + } +} +#[doc = "Trim Lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`trim_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trim_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TrimLockSpec; +impl crate::RegisterSpec for TrimLockSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`trim_lock::R`](R) reader structure"] +impl crate::Readable for TrimLockSpec {} +#[doc = "`write(|w| ..)` method takes [`trim_lock::W`](W) writer structure"] +impl crate::Writable for TrimLockSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TRIM_LOCK to value 0"] +impl crate::Resettable for TrimLockSpec {} diff --git a/mcxa276-pac/src/scg0/verid.rs b/mcxa276-pac/src/scg0/verid.rs new file mode 100644 index 000000000..5fb22a5da --- /dev/null +++ b/mcxa276-pac/src/scg0/verid.rs @@ -0,0 +1,20 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Field `VERSION` reader - SCG Version Number"] +pub type VersionR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - SCG Version Number"] + #[inline(always)] + pub fn version(&self) -> VersionR { + VersionR::new(self.bits) + } +} +#[doc = "Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0"] +impl crate::Resettable for VeridSpec {} diff --git a/mcxa276-pac/src/scn_scb.rs b/mcxa276-pac/src/scn_scb.rs new file mode 100644 index 000000000..1bee058a5 --- /dev/null +++ b/mcxa276-pac/src/scn_scb.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x0c], + cppwr: Cppwr, +} +impl RegisterBlock { + #[doc = "0x0c - Coprocessor Power Control Register"] + #[inline(always)] + pub const fn cppwr(&self) -> &Cppwr { + &self.cppwr + } +} +#[doc = "CPPWR (rw) register accessor: Coprocessor Power Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cppwr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cppwr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cppwr`] module"] +#[doc(alias = "CPPWR")] +pub type Cppwr = crate::Reg; +#[doc = "Coprocessor Power Control Register"] +pub mod cppwr; diff --git a/mcxa276-pac/src/scn_scb/cppwr.rs b/mcxa276-pac/src/scn_scb/cppwr.rs new file mode 100644 index 000000000..c81b6926b --- /dev/null +++ b/mcxa276-pac/src/scn_scb/cppwr.rs @@ -0,0 +1,1183 @@ +#[doc = "Register `CPPWR` reader"] +pub type R = crate::R; +#[doc = "Register `CPPWR` writer"] +pub type W = crate::W; +#[doc = "State UNKNOWN 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su0 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU0` reader - State UNKNOWN 0."] +pub type Su0R = crate::BitReader; +impl Su0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su0 { + match self.bits { + false => Su0::UnknownNotPermitted, + true => Su0::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su0::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su0::UnknownPermitted + } +} +#[doc = "Field `SU0` writer - State UNKNOWN 0."] +pub type Su0W<'a, REG> = crate::BitWriter<'a, REG, Su0>; +impl<'a, REG> Su0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su0::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su0::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus0 { + #[doc = "0: The SU0 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU0 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS0` reader - State UNKNOWN Secure only 0."] +pub type Sus0R = crate::BitReader; +impl Sus0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus0 { + match self.bits { + false => Sus0::SecureAndNonSecure, + true => Sus0::SecureOnly, + } + } + #[doc = "The SU0 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus0::SecureAndNonSecure + } + #[doc = "The SU0 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus0::SecureOnly + } +} +#[doc = "Field `SUS0` writer - State UNKNOWN Secure only 0."] +pub type Sus0W<'a, REG> = crate::BitWriter<'a, REG, Sus0>; +impl<'a, REG> Sus0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU0 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus0::SecureAndNonSecure) + } + #[doc = "The SU0 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus0::SecureOnly) + } +} +#[doc = "State UNKNOWN 1.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su1 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU1` reader - State UNKNOWN 1."] +pub type Su1R = crate::BitReader; +impl Su1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su1 { + match self.bits { + false => Su1::UnknownNotPermitted, + true => Su1::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su1::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su1::UnknownPermitted + } +} +#[doc = "Field `SU1` writer - State UNKNOWN 1."] +pub type Su1W<'a, REG> = crate::BitWriter<'a, REG, Su1>; +impl<'a, REG> Su1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su1::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su1::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 1.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus1 { + #[doc = "0: The SU7 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU7 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS1` reader - State UNKNOWN Secure only 1."] +pub type Sus1R = crate::BitReader; +impl Sus1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus1 { + match self.bits { + false => Sus1::SecureAndNonSecure, + true => Sus1::SecureOnly, + } + } + #[doc = "The SU7 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus1::SecureAndNonSecure + } + #[doc = "The SU7 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus1::SecureOnly + } +} +#[doc = "Field `SUS1` writer - State UNKNOWN Secure only 1."] +pub type Sus1W<'a, REG> = crate::BitWriter<'a, REG, Sus1>; +impl<'a, REG> Sus1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU7 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus1::SecureAndNonSecure) + } + #[doc = "The SU7 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus1::SecureOnly) + } +} +#[doc = "State UNKNOWN 2.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su2 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU2` reader - State UNKNOWN 2."] +pub type Su2R = crate::BitReader; +impl Su2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su2 { + match self.bits { + false => Su2::UnknownNotPermitted, + true => Su2::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su2::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su2::UnknownPermitted + } +} +#[doc = "Field `SU2` writer - State UNKNOWN 2."] +pub type Su2W<'a, REG> = crate::BitWriter<'a, REG, Su2>; +impl<'a, REG> Su2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su2::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su2::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 2.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus2 { + #[doc = "0: The SU2 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU2 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS2` reader - State UNKNOWN Secure only 2."] +pub type Sus2R = crate::BitReader; +impl Sus2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus2 { + match self.bits { + false => Sus2::SecureAndNonSecure, + true => Sus2::SecureOnly, + } + } + #[doc = "The SU2 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus2::SecureAndNonSecure + } + #[doc = "The SU2 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus2::SecureOnly + } +} +#[doc = "Field `SUS2` writer - State UNKNOWN Secure only 2."] +pub type Sus2W<'a, REG> = crate::BitWriter<'a, REG, Sus2>; +impl<'a, REG> Sus2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU2 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus2::SecureAndNonSecure) + } + #[doc = "The SU2 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus2::SecureOnly) + } +} +#[doc = "State UNKNOWN 3.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su3 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU3` reader - State UNKNOWN 3."] +pub type Su3R = crate::BitReader; +impl Su3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su3 { + match self.bits { + false => Su3::UnknownNotPermitted, + true => Su3::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su3::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su3::UnknownPermitted + } +} +#[doc = "Field `SU3` writer - State UNKNOWN 3."] +pub type Su3W<'a, REG> = crate::BitWriter<'a, REG, Su3>; +impl<'a, REG> Su3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su3::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su3::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 3.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus3 { + #[doc = "0: The SU3 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU3 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS3` reader - State UNKNOWN Secure only 3."] +pub type Sus3R = crate::BitReader; +impl Sus3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus3 { + match self.bits { + false => Sus3::SecureAndNonSecure, + true => Sus3::SecureOnly, + } + } + #[doc = "The SU3 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus3::SecureAndNonSecure + } + #[doc = "The SU3 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus3::SecureOnly + } +} +#[doc = "Field `SUS3` writer - State UNKNOWN Secure only 3."] +pub type Sus3W<'a, REG> = crate::BitWriter<'a, REG, Sus3>; +impl<'a, REG> Sus3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU3 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus3::SecureAndNonSecure) + } + #[doc = "The SU3 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus3::SecureOnly) + } +} +#[doc = "State UNKNOWN 4.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su4 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU4` reader - State UNKNOWN 4."] +pub type Su4R = crate::BitReader; +impl Su4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su4 { + match self.bits { + false => Su4::UnknownNotPermitted, + true => Su4::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su4::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su4::UnknownPermitted + } +} +#[doc = "Field `SU4` writer - State UNKNOWN 4."] +pub type Su4W<'a, REG> = crate::BitWriter<'a, REG, Su4>; +impl<'a, REG> Su4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su4::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su4::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 4.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus4 { + #[doc = "0: The SU4 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU4 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS4` reader - State UNKNOWN Secure only 4."] +pub type Sus4R = crate::BitReader; +impl Sus4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus4 { + match self.bits { + false => Sus4::SecureAndNonSecure, + true => Sus4::SecureOnly, + } + } + #[doc = "The SU4 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus4::SecureAndNonSecure + } + #[doc = "The SU4 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus4::SecureOnly + } +} +#[doc = "Field `SUS4` writer - State UNKNOWN Secure only 4."] +pub type Sus4W<'a, REG> = crate::BitWriter<'a, REG, Sus4>; +impl<'a, REG> Sus4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU4 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus4::SecureAndNonSecure) + } + #[doc = "The SU4 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus4::SecureOnly) + } +} +#[doc = "State UNKNOWN 5.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su5 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU5` reader - State UNKNOWN 5."] +pub type Su5R = crate::BitReader; +impl Su5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su5 { + match self.bits { + false => Su5::UnknownNotPermitted, + true => Su5::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su5::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su5::UnknownPermitted + } +} +#[doc = "Field `SU5` writer - State UNKNOWN 5."] +pub type Su5W<'a, REG> = crate::BitWriter<'a, REG, Su5>; +impl<'a, REG> Su5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su5::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su5::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 5.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus5 { + #[doc = "0: The SU5 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU5 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS5` reader - State UNKNOWN Secure only 5."] +pub type Sus5R = crate::BitReader; +impl Sus5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus5 { + match self.bits { + false => Sus5::SecureAndNonSecure, + true => Sus5::SecureOnly, + } + } + #[doc = "The SU5 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus5::SecureAndNonSecure + } + #[doc = "The SU5 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus5::SecureOnly + } +} +#[doc = "Field `SUS5` writer - State UNKNOWN Secure only 5."] +pub type Sus5W<'a, REG> = crate::BitWriter<'a, REG, Sus5>; +impl<'a, REG> Sus5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU5 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus5::SecureAndNonSecure) + } + #[doc = "The SU5 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus5::SecureOnly) + } +} +#[doc = "State UNKNOWN 6.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su6 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU6` reader - State UNKNOWN 6."] +pub type Su6R = crate::BitReader; +impl Su6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su6 { + match self.bits { + false => Su6::UnknownNotPermitted, + true => Su6::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su6::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su6::UnknownPermitted + } +} +#[doc = "Field `SU6` writer - State UNKNOWN 6."] +pub type Su6W<'a, REG> = crate::BitWriter<'a, REG, Su6>; +impl<'a, REG> Su6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su6::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su6::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 6.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus6 { + #[doc = "0: The SU6 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU6 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS6` reader - State UNKNOWN Secure only 6."] +pub type Sus6R = crate::BitReader; +impl Sus6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus6 { + match self.bits { + false => Sus6::SecureAndNonSecure, + true => Sus6::SecureOnly, + } + } + #[doc = "The SU6 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus6::SecureAndNonSecure + } + #[doc = "The SU6 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus6::SecureOnly + } +} +#[doc = "Field `SUS6` writer - State UNKNOWN Secure only 6."] +pub type Sus6W<'a, REG> = crate::BitWriter<'a, REG, Sus6>; +impl<'a, REG> Sus6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU6 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus6::SecureAndNonSecure) + } + #[doc = "The SU6 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus6::SecureOnly) + } +} +#[doc = "State UNKNOWN 7.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su7 { + #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU7` reader - State UNKNOWN 7."] +pub type Su7R = crate::BitReader; +impl Su7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su7 { + match self.bits { + false => Su7::UnknownNotPermitted, + true => Su7::UnknownPermitted, + } + } + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su7::UnknownNotPermitted + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su7::UnknownPermitted + } +} +#[doc = "Field `SU7` writer - State UNKNOWN 7."] +pub type Su7W<'a, REG> = crate::BitWriter<'a, REG, Su7>; +impl<'a, REG> Su7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The coprocessor state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su7::UnknownNotPermitted) + } + #[doc = "The coprocessor state is permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su7::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 7.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus7 { + #[doc = "0: The SU7 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU7 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS7` reader - State UNKNOWN Secure only 7."] +pub type Sus7R = crate::BitReader; +impl Sus7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus7 { + match self.bits { + false => Sus7::SecureAndNonSecure, + true => Sus7::SecureOnly, + } + } + #[doc = "The SU7 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus7::SecureAndNonSecure + } + #[doc = "The SU7 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus7::SecureOnly + } +} +#[doc = "Field `SUS7` writer - State UNKNOWN Secure only 7."] +pub type Sus7W<'a, REG> = crate::BitWriter<'a, REG, Sus7>; +impl<'a, REG> Sus7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU7 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus7::SecureAndNonSecure) + } + #[doc = "The SU7 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus7::SecureOnly) + } +} +#[doc = "State UNKNOWN 10.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Su10 { + #[doc = "0: The floating-point state is not permitted to become UNKNOWN."] + UnknownNotPermitted = 0, + #[doc = "1: The floating-point state is permitted to become UNKNOWN"] + UnknownPermitted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Su10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SU10` reader - State UNKNOWN 10."] +pub type Su10R = crate::BitReader; +impl Su10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Su10 { + match self.bits { + false => Su10::UnknownNotPermitted, + true => Su10::UnknownPermitted, + } + } + #[doc = "The floating-point state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn is_unknown_not_permitted(&self) -> bool { + *self == Su10::UnknownNotPermitted + } + #[doc = "The floating-point state is permitted to become UNKNOWN"] + #[inline(always)] + pub fn is_unknown_permitted(&self) -> bool { + *self == Su10::UnknownPermitted + } +} +#[doc = "Field `SU10` writer - State UNKNOWN 10."] +pub type Su10W<'a, REG> = crate::BitWriter<'a, REG, Su10>; +impl<'a, REG> Su10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The floating-point state is not permitted to become UNKNOWN."] + #[inline(always)] + pub fn unknown_not_permitted(self) -> &'a mut crate::W { + self.variant(Su10::UnknownNotPermitted) + } + #[doc = "The floating-point state is permitted to become UNKNOWN"] + #[inline(always)] + pub fn unknown_permitted(self) -> &'a mut crate::W { + self.variant(Su10::UnknownPermitted) + } +} +#[doc = "State UNKNOWN Secure only 10.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sus10 { + #[doc = "0: The SU10 field is accessible from both Security states."] + SecureAndNonSecure = 0, + #[doc = "1: The SU10 field is only accessible from the Secure state."] + SecureOnly = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sus10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUS10` reader - State UNKNOWN Secure only 10."] +pub type Sus10R = crate::BitReader; +impl Sus10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sus10 { + match self.bits { + false => Sus10::SecureAndNonSecure, + true => Sus10::SecureOnly, + } + } + #[doc = "The SU10 field is accessible from both Security states."] + #[inline(always)] + pub fn is_secure_and_non_secure(&self) -> bool { + *self == Sus10::SecureAndNonSecure + } + #[doc = "The SU10 field is only accessible from the Secure state."] + #[inline(always)] + pub fn is_secure_only(&self) -> bool { + *self == Sus10::SecureOnly + } +} +#[doc = "Field `SUS10` writer - State UNKNOWN Secure only 10."] +pub type Sus10W<'a, REG> = crate::BitWriter<'a, REG, Sus10>; +impl<'a, REG> Sus10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SU10 field is accessible from both Security states."] + #[inline(always)] + pub fn secure_and_non_secure(self) -> &'a mut crate::W { + self.variant(Sus10::SecureAndNonSecure) + } + #[doc = "The SU10 field is only accessible from the Secure state."] + #[inline(always)] + pub fn secure_only(self) -> &'a mut crate::W { + self.variant(Sus10::SecureOnly) + } +} +#[doc = "Field `SU11` reader - State UNKNOWN 11."] +pub type Su11R = crate::BitReader; +#[doc = "Field `SU11` writer - State UNKNOWN 11."] +pub type Su11W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SUS11` reader - State UNKNOWN Secure only 11."] +pub type Sus11R = crate::BitReader; +#[doc = "Field `SUS11` writer - State UNKNOWN Secure only 11."] +pub type Sus11W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - State UNKNOWN 0."] + #[inline(always)] + pub fn su0(&self) -> Su0R { + Su0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - State UNKNOWN Secure only 0."] + #[inline(always)] + pub fn sus0(&self) -> Sus0R { + Sus0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - State UNKNOWN 1."] + #[inline(always)] + pub fn su1(&self) -> Su1R { + Su1R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - State UNKNOWN Secure only 1."] + #[inline(always)] + pub fn sus1(&self) -> Sus1R { + Sus1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - State UNKNOWN 2."] + #[inline(always)] + pub fn su2(&self) -> Su2R { + Su2R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - State UNKNOWN Secure only 2."] + #[inline(always)] + pub fn sus2(&self) -> Sus2R { + Sus2R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - State UNKNOWN 3."] + #[inline(always)] + pub fn su3(&self) -> Su3R { + Su3R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - State UNKNOWN Secure only 3."] + #[inline(always)] + pub fn sus3(&self) -> Sus3R { + Sus3R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - State UNKNOWN 4."] + #[inline(always)] + pub fn su4(&self) -> Su4R { + Su4R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - State UNKNOWN Secure only 4."] + #[inline(always)] + pub fn sus4(&self) -> Sus4R { + Sus4R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - State UNKNOWN 5."] + #[inline(always)] + pub fn su5(&self) -> Su5R { + Su5R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - State UNKNOWN Secure only 5."] + #[inline(always)] + pub fn sus5(&self) -> Sus5R { + Sus5R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - State UNKNOWN 6."] + #[inline(always)] + pub fn su6(&self) -> Su6R { + Su6R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - State UNKNOWN Secure only 6."] + #[inline(always)] + pub fn sus6(&self) -> Sus6R { + Sus6R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - State UNKNOWN 7."] + #[inline(always)] + pub fn su7(&self) -> Su7R { + Su7R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - State UNKNOWN Secure only 7."] + #[inline(always)] + pub fn sus7(&self) -> Sus7R { + Sus7R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 20 - State UNKNOWN 10."] + #[inline(always)] + pub fn su10(&self) -> Su10R { + Su10R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - State UNKNOWN Secure only 10."] + #[inline(always)] + pub fn sus10(&self) -> Sus10R { + Sus10R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - State UNKNOWN 11."] + #[inline(always)] + pub fn su11(&self) -> Su11R { + Su11R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - State UNKNOWN Secure only 11."] + #[inline(always)] + pub fn sus11(&self) -> Sus11R { + Sus11R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - State UNKNOWN 0."] + #[inline(always)] + pub fn su0(&mut self) -> Su0W { + Su0W::new(self, 0) + } + #[doc = "Bit 1 - State UNKNOWN Secure only 0."] + #[inline(always)] + pub fn sus0(&mut self) -> Sus0W { + Sus0W::new(self, 1) + } + #[doc = "Bit 2 - State UNKNOWN 1."] + #[inline(always)] + pub fn su1(&mut self) -> Su1W { + Su1W::new(self, 2) + } + #[doc = "Bit 3 - State UNKNOWN Secure only 1."] + #[inline(always)] + pub fn sus1(&mut self) -> Sus1W { + Sus1W::new(self, 3) + } + #[doc = "Bit 4 - State UNKNOWN 2."] + #[inline(always)] + pub fn su2(&mut self) -> Su2W { + Su2W::new(self, 4) + } + #[doc = "Bit 5 - State UNKNOWN Secure only 2."] + #[inline(always)] + pub fn sus2(&mut self) -> Sus2W { + Sus2W::new(self, 5) + } + #[doc = "Bit 6 - State UNKNOWN 3."] + #[inline(always)] + pub fn su3(&mut self) -> Su3W { + Su3W::new(self, 6) + } + #[doc = "Bit 7 - State UNKNOWN Secure only 3."] + #[inline(always)] + pub fn sus3(&mut self) -> Sus3W { + Sus3W::new(self, 7) + } + #[doc = "Bit 8 - State UNKNOWN 4."] + #[inline(always)] + pub fn su4(&mut self) -> Su4W { + Su4W::new(self, 8) + } + #[doc = "Bit 9 - State UNKNOWN Secure only 4."] + #[inline(always)] + pub fn sus4(&mut self) -> Sus4W { + Sus4W::new(self, 9) + } + #[doc = "Bit 10 - State UNKNOWN 5."] + #[inline(always)] + pub fn su5(&mut self) -> Su5W { + Su5W::new(self, 10) + } + #[doc = "Bit 11 - State UNKNOWN Secure only 5."] + #[inline(always)] + pub fn sus5(&mut self) -> Sus5W { + Sus5W::new(self, 11) + } + #[doc = "Bit 12 - State UNKNOWN 6."] + #[inline(always)] + pub fn su6(&mut self) -> Su6W { + Su6W::new(self, 12) + } + #[doc = "Bit 13 - State UNKNOWN Secure only 6."] + #[inline(always)] + pub fn sus6(&mut self) -> Sus6W { + Sus6W::new(self, 13) + } + #[doc = "Bit 14 - State UNKNOWN 7."] + #[inline(always)] + pub fn su7(&mut self) -> Su7W { + Su7W::new(self, 14) + } + #[doc = "Bit 15 - State UNKNOWN Secure only 7."] + #[inline(always)] + pub fn sus7(&mut self) -> Sus7W { + Sus7W::new(self, 15) + } + #[doc = "Bit 20 - State UNKNOWN 10."] + #[inline(always)] + pub fn su10(&mut self) -> Su10W { + Su10W::new(self, 20) + } + #[doc = "Bit 21 - State UNKNOWN Secure only 10."] + #[inline(always)] + pub fn sus10(&mut self) -> Sus10W { + Sus10W::new(self, 21) + } + #[doc = "Bit 22 - State UNKNOWN 11."] + #[inline(always)] + pub fn su11(&mut self) -> Su11W { + Su11W::new(self, 22) + } + #[doc = "Bit 23 - State UNKNOWN Secure only 11."] + #[inline(always)] + pub fn sus11(&mut self) -> Sus11W { + Sus11W::new(self, 23) + } +} +#[doc = "Coprocessor Power Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cppwr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cppwr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CppwrSpec; +impl crate::RegisterSpec for CppwrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cppwr::R`](R) reader structure"] +impl crate::Readable for CppwrSpec {} +#[doc = "`write(|w| ..)` method takes [`cppwr::W`](W) writer structure"] +impl crate::Writable for CppwrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CPPWR to value 0"] +impl crate::Resettable for CppwrSpec {} diff --git a/mcxa276-pac/src/sgi0.rs b/mcxa276-pac/src/sgi0.rs new file mode 100644 index 000000000..df82e2974 --- /dev/null +++ b/mcxa276-pac/src/sgi0.rs @@ -0,0 +1,863 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x0200], + sgi_datin0a: SgiDatin0a, + sgi_datin0b: SgiDatin0b, + sgi_datin0c: SgiDatin0c, + sgi_datin0d: SgiDatin0d, + sgi_datin1a: SgiDatin1a, + sgi_datin1b: SgiDatin1b, + sgi_datin1c: SgiDatin1c, + sgi_datin1d: SgiDatin1d, + sgi_datin2a: SgiDatin2a, + sgi_datin2b: SgiDatin2b, + sgi_datin2c: SgiDatin2c, + sgi_datin2d: SgiDatin2d, + sgi_datin3a: SgiDatin3a, + sgi_datin3b: SgiDatin3b, + sgi_datin3c: SgiDatin3c, + sgi_datin3d: SgiDatin3d, + sgi_key0a: SgiKey0a, + sgi_key0b: SgiKey0b, + sgi_key0c: SgiKey0c, + sgi_key0d: SgiKey0d, + sgi_key1a: SgiKey1a, + sgi_key1b: SgiKey1b, + sgi_key1c: SgiKey1c, + sgi_key1d: SgiKey1d, + sgi_key2a: SgiKey2a, + sgi_key2b: SgiKey2b, + sgi_key2c: SgiKey2c, + sgi_key2d: SgiKey2d, + sgi_key3a: SgiKey3a, + sgi_key3b: SgiKey3b, + sgi_key3c: SgiKey3c, + sgi_key3d: SgiKey3d, + sgi_key4a: SgiKey4a, + sgi_key4b: SgiKey4b, + sgi_key4c: SgiKey4c, + sgi_key4d: SgiKey4d, + sgi_key5a: SgiKey5a, + sgi_key5b: SgiKey5b, + sgi_key5c: SgiKey5c, + sgi_key5d: SgiKey5d, + sgi_key6a: SgiKey6a, + sgi_key6b: SgiKey6b, + sgi_key6c: SgiKey6c, + sgi_key6d: SgiKey6d, + sgi_key7a: SgiKey7a, + sgi_key7b: SgiKey7b, + sgi_key7c: SgiKey7c, + sgi_key7d: SgiKey7d, + sgi_datouta: SgiDatouta, + sgi_datoutb: SgiDatoutb, + sgi_datoutc: SgiDatoutc, + sgi_datoutd: SgiDatoutd, + _reserved52: [u8; 0x0930], + sgi_status: SgiStatus, + sgi_count: SgiCount, + sgi_keychk: SgiKeychk, + _reserved55: [u8; 0xf4], + sgi_ctrl: SgiCtrl, + sgi_ctrl2: SgiCtrl2, + sgi_dummy_ctrl: SgiDummyCtrl, + sgi_sfr_sw_mask: SgiSfrSwMask, + sgi_sfrseed: SgiSfrseed, + sgi_sha2_ctrl: SgiSha2Ctrl, + sgi_sha_fifo: SgiShaFifo, + sgi_config: SgiConfig, + sgi_config2: SgiConfig2, + sgi_auto_mode: SgiAutoMode, + sgi_auto_dma_ctrl: SgiAutoDmaCtrl, + _reserved66: [u8; 0x04], + sgi_prng_sw_seed: SgiPrngSwSeed, + _reserved67: [u8; 0x0c], + sgi_key_ctrl: SgiKeyCtrl, + _reserved68: [u8; 0x0c], + sgi_key_wrap: SgiKeyWrap, + _reserved69: [u8; 0x01b4], + sgi_version: SgiVersion, + _reserved70: [u8; 0xb4], + sgi_access_err: SgiAccessErr, + sgi_access_err_clr: SgiAccessErrClr, + _reserved72: [u8; 0x18], + sgi_int_status: SgiIntStatus, + sgi_int_enable: SgiIntEnable, + sgi_int_status_clr: SgiIntStatusClr, + sgi_int_status_set: SgiIntStatusSet, + _reserved76: [u8; 0x0c], + sgi_module_id: SgiModuleId, +} +impl RegisterBlock { + #[doc = "0x200 - Input Data register 0 - Word-3"] + #[inline(always)] + pub const fn sgi_datin0a(&self) -> &SgiDatin0a { + &self.sgi_datin0a + } + #[doc = "0x204 - Input Data register 0 - Word-2"] + #[inline(always)] + pub const fn sgi_datin0b(&self) -> &SgiDatin0b { + &self.sgi_datin0b + } + #[doc = "0x208 - Input Data register 0 - Word-1"] + #[inline(always)] + pub const fn sgi_datin0c(&self) -> &SgiDatin0c { + &self.sgi_datin0c + } + #[doc = "0x20c - Input Data register 0 - Word-0"] + #[inline(always)] + pub const fn sgi_datin0d(&self) -> &SgiDatin0d { + &self.sgi_datin0d + } + #[doc = "0x210 - Input Data register 1 - Word-3"] + #[inline(always)] + pub const fn sgi_datin1a(&self) -> &SgiDatin1a { + &self.sgi_datin1a + } + #[doc = "0x214 - Input Data register 1 - Word-2"] + #[inline(always)] + pub const fn sgi_datin1b(&self) -> &SgiDatin1b { + &self.sgi_datin1b + } + #[doc = "0x218 - Input Data register 1 - Word-1"] + #[inline(always)] + pub const fn sgi_datin1c(&self) -> &SgiDatin1c { + &self.sgi_datin1c + } + #[doc = "0x21c - Input Data register 1 - Word-0"] + #[inline(always)] + pub const fn sgi_datin1d(&self) -> &SgiDatin1d { + &self.sgi_datin1d + } + #[doc = "0x220 - Input Data register 2 - Word-3"] + #[inline(always)] + pub const fn sgi_datin2a(&self) -> &SgiDatin2a { + &self.sgi_datin2a + } + #[doc = "0x224 - Input Data register 2 - Word-2"] + #[inline(always)] + pub const fn sgi_datin2b(&self) -> &SgiDatin2b { + &self.sgi_datin2b + } + #[doc = "0x228 - Input Data register 2 - Word-1"] + #[inline(always)] + pub const fn sgi_datin2c(&self) -> &SgiDatin2c { + &self.sgi_datin2c + } + #[doc = "0x22c - Input Data register 2 - Word-0"] + #[inline(always)] + pub const fn sgi_datin2d(&self) -> &SgiDatin2d { + &self.sgi_datin2d + } + #[doc = "0x230 - Input Data register 3 - Word-3"] + #[inline(always)] + pub const fn sgi_datin3a(&self) -> &SgiDatin3a { + &self.sgi_datin3a + } + #[doc = "0x234 - Input Data register 3 - Word-2"] + #[inline(always)] + pub const fn sgi_datin3b(&self) -> &SgiDatin3b { + &self.sgi_datin3b + } + #[doc = "0x238 - Input Data register 3 - Word-1"] + #[inline(always)] + pub const fn sgi_datin3c(&self) -> &SgiDatin3c { + &self.sgi_datin3c + } + #[doc = "0x23c - Input Data register 3 - Word-0"] + #[inline(always)] + pub const fn sgi_datin3d(&self) -> &SgiDatin3d { + &self.sgi_datin3d + } + #[doc = "0x240 - Input Key register 0 - Word-3"] + #[inline(always)] + pub const fn sgi_key0a(&self) -> &SgiKey0a { + &self.sgi_key0a + } + #[doc = "0x244 - Input Key register 0 - Word-2"] + #[inline(always)] + pub const fn sgi_key0b(&self) -> &SgiKey0b { + &self.sgi_key0b + } + #[doc = "0x248 - Input Key register 0 - Word-1"] + #[inline(always)] + pub const fn sgi_key0c(&self) -> &SgiKey0c { + &self.sgi_key0c + } + #[doc = "0x24c - Input Key register 0 - Word-0"] + #[inline(always)] + pub const fn sgi_key0d(&self) -> &SgiKey0d { + &self.sgi_key0d + } + #[doc = "0x250 - Input Key register 1 - Word-3"] + #[inline(always)] + pub const fn sgi_key1a(&self) -> &SgiKey1a { + &self.sgi_key1a + } + #[doc = "0x254 - Input Key register 1 - Word-2"] + #[inline(always)] + pub const fn sgi_key1b(&self) -> &SgiKey1b { + &self.sgi_key1b + } + #[doc = "0x258 - Input Key register 1 - Word-1"] + #[inline(always)] + pub const fn sgi_key1c(&self) -> &SgiKey1c { + &self.sgi_key1c + } + #[doc = "0x25c - Input Key register 1 - Word-0"] + #[inline(always)] + pub const fn sgi_key1d(&self) -> &SgiKey1d { + &self.sgi_key1d + } + #[doc = "0x260 - Input Key register 2 - Word-3"] + #[inline(always)] + pub const fn sgi_key2a(&self) -> &SgiKey2a { + &self.sgi_key2a + } + #[doc = "0x264 - Input Key register 2 - Word-2"] + #[inline(always)] + pub const fn sgi_key2b(&self) -> &SgiKey2b { + &self.sgi_key2b + } + #[doc = "0x268 - Input Key register 2 - Word-1"] + #[inline(always)] + pub const fn sgi_key2c(&self) -> &SgiKey2c { + &self.sgi_key2c + } + #[doc = "0x26c - Input Key register 2 - Word-0"] + #[inline(always)] + pub const fn sgi_key2d(&self) -> &SgiKey2d { + &self.sgi_key2d + } + #[doc = "0x270 - Input Key register 3 - Word-3"] + #[inline(always)] + pub const fn sgi_key3a(&self) -> &SgiKey3a { + &self.sgi_key3a + } + #[doc = "0x274 - Input Key register 3 - Word-2"] + #[inline(always)] + pub const fn sgi_key3b(&self) -> &SgiKey3b { + &self.sgi_key3b + } + #[doc = "0x278 - Input Key register 3 - Word-1"] + #[inline(always)] + pub const fn sgi_key3c(&self) -> &SgiKey3c { + &self.sgi_key3c + } + #[doc = "0x27c - Input Key register 3 - Word-0"] + #[inline(always)] + pub const fn sgi_key3d(&self) -> &SgiKey3d { + &self.sgi_key3d + } + #[doc = "0x280 - Input Key register 4 - Word-3"] + #[inline(always)] + pub const fn sgi_key4a(&self) -> &SgiKey4a { + &self.sgi_key4a + } + #[doc = "0x284 - Input Key register 4 - Word-2"] + #[inline(always)] + pub const fn sgi_key4b(&self) -> &SgiKey4b { + &self.sgi_key4b + } + #[doc = "0x288 - Input Key register 4 - Word-1"] + #[inline(always)] + pub const fn sgi_key4c(&self) -> &SgiKey4c { + &self.sgi_key4c + } + #[doc = "0x28c - Input Key register 4 - Word-0"] + #[inline(always)] + pub const fn sgi_key4d(&self) -> &SgiKey4d { + &self.sgi_key4d + } + #[doc = "0x290 - Input Key register 5 - Word-3"] + #[inline(always)] + pub const fn sgi_key5a(&self) -> &SgiKey5a { + &self.sgi_key5a + } + #[doc = "0x294 - Input Key register 5 - Word-2"] + #[inline(always)] + pub const fn sgi_key5b(&self) -> &SgiKey5b { + &self.sgi_key5b + } + #[doc = "0x298 - Input Key register 5 - Word-1"] + #[inline(always)] + pub const fn sgi_key5c(&self) -> &SgiKey5c { + &self.sgi_key5c + } + #[doc = "0x29c - Input Key register 5 - Word-0"] + #[inline(always)] + pub const fn sgi_key5d(&self) -> &SgiKey5d { + &self.sgi_key5d + } + #[doc = "0x2a0 - Input Key register 6 - Word-3"] + #[inline(always)] + pub const fn sgi_key6a(&self) -> &SgiKey6a { + &self.sgi_key6a + } + #[doc = "0x2a4 - Input Key register 6 - Word-2"] + #[inline(always)] + pub const fn sgi_key6b(&self) -> &SgiKey6b { + &self.sgi_key6b + } + #[doc = "0x2a8 - Input Key register 6 - Word-1"] + #[inline(always)] + pub const fn sgi_key6c(&self) -> &SgiKey6c { + &self.sgi_key6c + } + #[doc = "0x2ac - Input Key register 6 - Word-0"] + #[inline(always)] + pub const fn sgi_key6d(&self) -> &SgiKey6d { + &self.sgi_key6d + } + #[doc = "0x2b0 - Input Key register 7 - Word-3"] + #[inline(always)] + pub const fn sgi_key7a(&self) -> &SgiKey7a { + &self.sgi_key7a + } + #[doc = "0x2b4 - Input Key register 7 - Word-2"] + #[inline(always)] + pub const fn sgi_key7b(&self) -> &SgiKey7b { + &self.sgi_key7b + } + #[doc = "0x2b8 - Input Key register 7 - Word-1"] + #[inline(always)] + pub const fn sgi_key7c(&self) -> &SgiKey7c { + &self.sgi_key7c + } + #[doc = "0x2bc - Input Key register 7 - Word-0"] + #[inline(always)] + pub const fn sgi_key7d(&self) -> &SgiKey7d { + &self.sgi_key7d + } + #[doc = "0x2c0 - Output Data register - Word-3"] + #[inline(always)] + pub const fn sgi_datouta(&self) -> &SgiDatouta { + &self.sgi_datouta + } + #[doc = "0x2c4 - Output Data register - Word-2"] + #[inline(always)] + pub const fn sgi_datoutb(&self) -> &SgiDatoutb { + &self.sgi_datoutb + } + #[doc = "0x2c8 - Output Data register - Word-1"] + #[inline(always)] + pub const fn sgi_datoutc(&self) -> &SgiDatoutc { + &self.sgi_datoutc + } + #[doc = "0x2cc - Output Data register - Word-0"] + #[inline(always)] + pub const fn sgi_datoutd(&self) -> &SgiDatoutd { + &self.sgi_datoutd + } + #[doc = "0xc00 - Status register"] + #[inline(always)] + pub const fn sgi_status(&self) -> &SgiStatus { + &self.sgi_status + } + #[doc = "0xc04 - Calculation counter"] + #[inline(always)] + pub const fn sgi_count(&self) -> &SgiCount { + &self.sgi_count + } + #[doc = "0xc08 - Key checksum register"] + #[inline(always)] + pub const fn sgi_keychk(&self) -> &SgiKeychk { + &self.sgi_keychk + } + #[doc = "0xd00 - SGI Control register"] + #[inline(always)] + pub const fn sgi_ctrl(&self) -> &SgiCtrl { + &self.sgi_ctrl + } + #[doc = "0xd04 - SGI Control register 2"] + #[inline(always)] + pub const fn sgi_ctrl2(&self) -> &SgiCtrl2 { + &self.sgi_ctrl2 + } + #[doc = "0xd08 - Configuration of dummy controls"] + #[inline(always)] + pub const fn sgi_dummy_ctrl(&self) -> &SgiDummyCtrl { + &self.sgi_dummy_ctrl + } + #[doc = "0xd0c - Sofware Assisted Masking register ."] + #[inline(always)] + pub const fn sgi_sfr_sw_mask(&self) -> &SgiSfrSwMask { + &self.sgi_sfr_sw_mask + } + #[doc = "0xd10 - SFRSEED register for SFRMASK feature."] + #[inline(always)] + pub const fn sgi_sfrseed(&self) -> &SgiSfrseed { + &self.sgi_sfrseed + } + #[doc = "0xd14 - SHA Control Register"] + #[inline(always)] + pub const fn sgi_sha2_ctrl(&self) -> &SgiSha2Ctrl { + &self.sgi_sha2_ctrl + } + #[doc = "0xd18 - SHA FIFO lower-bank low"] + #[inline(always)] + pub const fn sgi_sha_fifo(&self) -> &SgiShaFifo { + &self.sgi_sha_fifo + } + #[doc = "0xd1c - SHA Configuration Reg"] + #[inline(always)] + pub const fn sgi_config(&self) -> &SgiConfig { + &self.sgi_config + } + #[doc = "0xd20 - SHA Configuration 2 Reg"] + #[inline(always)] + pub const fn sgi_config2(&self) -> &SgiConfig2 { + &self.sgi_config2 + } + #[doc = "0xd24 - SGI Auto Mode Control register"] + #[inline(always)] + pub const fn sgi_auto_mode(&self) -> &SgiAutoMode { + &self.sgi_auto_mode + } + #[doc = "0xd28 - SGI Auto Mode Control register"] + #[inline(always)] + pub const fn sgi_auto_dma_ctrl(&self) -> &SgiAutoDmaCtrl { + &self.sgi_auto_dma_ctrl + } + #[doc = "0xd30 - SGI internal PRNG SW seeding register"] + #[inline(always)] + pub const fn sgi_prng_sw_seed(&self) -> &SgiPrngSwSeed { + &self.sgi_prng_sw_seed + } + #[doc = "0xd40 - SGI Key Control SFR"] + #[inline(always)] + pub const fn sgi_key_ctrl(&self) -> &SgiKeyCtrl { + &self.sgi_key_ctrl + } + #[doc = "0xd50 - Wrapped key read SFR"] + #[inline(always)] + pub const fn sgi_key_wrap(&self) -> &SgiKeyWrap { + &self.sgi_key_wrap + } + #[doc = "0xf08 - SGI Version"] + #[inline(always)] + pub const fn sgi_version(&self) -> &SgiVersion { + &self.sgi_version + } + #[doc = "0xfc0 - Access Error"] + #[inline(always)] + pub const fn sgi_access_err(&self) -> &SgiAccessErr { + &self.sgi_access_err + } + #[doc = "0xfc4 - Clear Access Error"] + #[inline(always)] + pub const fn sgi_access_err_clr(&self) -> &SgiAccessErrClr { + &self.sgi_access_err_clr + } + #[doc = "0xfe0 - Interrupt status"] + #[inline(always)] + pub const fn sgi_int_status(&self) -> &SgiIntStatus { + &self.sgi_int_status + } + #[doc = "0xfe4 - Interrupt enable"] + #[inline(always)] + pub const fn sgi_int_enable(&self) -> &SgiIntEnable { + &self.sgi_int_enable + } + #[doc = "0xfe8 - Interrupt status clear"] + #[inline(always)] + pub const fn sgi_int_status_clr(&self) -> &SgiIntStatusClr { + &self.sgi_int_status_clr + } + #[doc = "0xfec - Interrupt status set"] + #[inline(always)] + pub const fn sgi_int_status_set(&self) -> &SgiIntStatusSet { + &self.sgi_int_status_set + } + #[doc = "0xffc - Module ID"] + #[inline(always)] + pub const fn sgi_module_id(&self) -> &SgiModuleId { + &self.sgi_module_id + } +} +#[doc = "sgi_datin0a (rw) register accessor: Input Data register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0a`] module"] +#[doc(alias = "sgi_datin0a")] +pub type SgiDatin0a = crate::Reg; +#[doc = "Input Data register 0 - Word-3"] +pub mod sgi_datin0a; +#[doc = "sgi_datin0b (rw) register accessor: Input Data register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0b`] module"] +#[doc(alias = "sgi_datin0b")] +pub type SgiDatin0b = crate::Reg; +#[doc = "Input Data register 0 - Word-2"] +pub mod sgi_datin0b; +#[doc = "sgi_datin0c (rw) register accessor: Input Data register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0c`] module"] +#[doc(alias = "sgi_datin0c")] +pub type SgiDatin0c = crate::Reg; +#[doc = "Input Data register 0 - Word-1"] +pub mod sgi_datin0c; +#[doc = "sgi_datin0d (rw) register accessor: Input Data register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0d`] module"] +#[doc(alias = "sgi_datin0d")] +pub type SgiDatin0d = crate::Reg; +#[doc = "Input Data register 0 - Word-0"] +pub mod sgi_datin0d; +#[doc = "sgi_datin1a (rw) register accessor: Input Data register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1a`] module"] +#[doc(alias = "sgi_datin1a")] +pub type SgiDatin1a = crate::Reg; +#[doc = "Input Data register 1 - Word-3"] +pub mod sgi_datin1a; +#[doc = "sgi_datin1b (rw) register accessor: Input Data register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1b`] module"] +#[doc(alias = "sgi_datin1b")] +pub type SgiDatin1b = crate::Reg; +#[doc = "Input Data register 1 - Word-2"] +pub mod sgi_datin1b; +#[doc = "sgi_datin1c (rw) register accessor: Input Data register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1c`] module"] +#[doc(alias = "sgi_datin1c")] +pub type SgiDatin1c = crate::Reg; +#[doc = "Input Data register 1 - Word-1"] +pub mod sgi_datin1c; +#[doc = "sgi_datin1d (rw) register accessor: Input Data register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1d`] module"] +#[doc(alias = "sgi_datin1d")] +pub type SgiDatin1d = crate::Reg; +#[doc = "Input Data register 1 - Word-0"] +pub mod sgi_datin1d; +#[doc = "sgi_datin2a (rw) register accessor: Input Data register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2a`] module"] +#[doc(alias = "sgi_datin2a")] +pub type SgiDatin2a = crate::Reg; +#[doc = "Input Data register 2 - Word-3"] +pub mod sgi_datin2a; +#[doc = "sgi_datin2b (rw) register accessor: Input Data register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2b`] module"] +#[doc(alias = "sgi_datin2b")] +pub type SgiDatin2b = crate::Reg; +#[doc = "Input Data register 2 - Word-2"] +pub mod sgi_datin2b; +#[doc = "sgi_datin2c (rw) register accessor: Input Data register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2c`] module"] +#[doc(alias = "sgi_datin2c")] +pub type SgiDatin2c = crate::Reg; +#[doc = "Input Data register 2 - Word-1"] +pub mod sgi_datin2c; +#[doc = "sgi_datin2d (rw) register accessor: Input Data register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2d`] module"] +#[doc(alias = "sgi_datin2d")] +pub type SgiDatin2d = crate::Reg; +#[doc = "Input Data register 2 - Word-0"] +pub mod sgi_datin2d; +#[doc = "sgi_datin3a (rw) register accessor: Input Data register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3a`] module"] +#[doc(alias = "sgi_datin3a")] +pub type SgiDatin3a = crate::Reg; +#[doc = "Input Data register 3 - Word-3"] +pub mod sgi_datin3a; +#[doc = "sgi_datin3b (rw) register accessor: Input Data register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3b`] module"] +#[doc(alias = "sgi_datin3b")] +pub type SgiDatin3b = crate::Reg; +#[doc = "Input Data register 3 - Word-2"] +pub mod sgi_datin3b; +#[doc = "sgi_datin3c (rw) register accessor: Input Data register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3c`] module"] +#[doc(alias = "sgi_datin3c")] +pub type SgiDatin3c = crate::Reg; +#[doc = "Input Data register 3 - Word-1"] +pub mod sgi_datin3c; +#[doc = "sgi_datin3d (rw) register accessor: Input Data register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3d`] module"] +#[doc(alias = "sgi_datin3d")] +pub type SgiDatin3d = crate::Reg; +#[doc = "Input Data register 3 - Word-0"] +pub mod sgi_datin3d; +#[doc = "sgi_key0a (rw) register accessor: Input Key register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0a`] module"] +#[doc(alias = "sgi_key0a")] +pub type SgiKey0a = crate::Reg; +#[doc = "Input Key register 0 - Word-3"] +pub mod sgi_key0a; +#[doc = "sgi_key0b (rw) register accessor: Input Key register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0b`] module"] +#[doc(alias = "sgi_key0b")] +pub type SgiKey0b = crate::Reg; +#[doc = "Input Key register 0 - Word-2"] +pub mod sgi_key0b; +#[doc = "sgi_key0c (rw) register accessor: Input Key register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0c`] module"] +#[doc(alias = "sgi_key0c")] +pub type SgiKey0c = crate::Reg; +#[doc = "Input Key register 0 - Word-1"] +pub mod sgi_key0c; +#[doc = "sgi_key0d (rw) register accessor: Input Key register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0d`] module"] +#[doc(alias = "sgi_key0d")] +pub type SgiKey0d = crate::Reg; +#[doc = "Input Key register 0 - Word-0"] +pub mod sgi_key0d; +#[doc = "sgi_key1a (rw) register accessor: Input Key register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1a`] module"] +#[doc(alias = "sgi_key1a")] +pub type SgiKey1a = crate::Reg; +#[doc = "Input Key register 1 - Word-3"] +pub mod sgi_key1a; +#[doc = "sgi_key1b (rw) register accessor: Input Key register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1b`] module"] +#[doc(alias = "sgi_key1b")] +pub type SgiKey1b = crate::Reg; +#[doc = "Input Key register 1 - Word-2"] +pub mod sgi_key1b; +#[doc = "sgi_key1c (rw) register accessor: Input Key register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1c`] module"] +#[doc(alias = "sgi_key1c")] +pub type SgiKey1c = crate::Reg; +#[doc = "Input Key register 1 - Word-1"] +pub mod sgi_key1c; +#[doc = "sgi_key1d (rw) register accessor: Input Key register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1d`] module"] +#[doc(alias = "sgi_key1d")] +pub type SgiKey1d = crate::Reg; +#[doc = "Input Key register 1 - Word-0"] +pub mod sgi_key1d; +#[doc = "sgi_key2a (rw) register accessor: Input Key register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2a`] module"] +#[doc(alias = "sgi_key2a")] +pub type SgiKey2a = crate::Reg; +#[doc = "Input Key register 2 - Word-3"] +pub mod sgi_key2a; +#[doc = "sgi_key2b (rw) register accessor: Input Key register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2b`] module"] +#[doc(alias = "sgi_key2b")] +pub type SgiKey2b = crate::Reg; +#[doc = "Input Key register 2 - Word-2"] +pub mod sgi_key2b; +#[doc = "sgi_key2c (rw) register accessor: Input Key register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2c`] module"] +#[doc(alias = "sgi_key2c")] +pub type SgiKey2c = crate::Reg; +#[doc = "Input Key register 2 - Word-1"] +pub mod sgi_key2c; +#[doc = "sgi_key2d (rw) register accessor: Input Key register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2d`] module"] +#[doc(alias = "sgi_key2d")] +pub type SgiKey2d = crate::Reg; +#[doc = "Input Key register 2 - Word-0"] +pub mod sgi_key2d; +#[doc = "sgi_key3a (rw) register accessor: Input Key register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3a`] module"] +#[doc(alias = "sgi_key3a")] +pub type SgiKey3a = crate::Reg; +#[doc = "Input Key register 3 - Word-3"] +pub mod sgi_key3a; +#[doc = "sgi_key3b (rw) register accessor: Input Key register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3b`] module"] +#[doc(alias = "sgi_key3b")] +pub type SgiKey3b = crate::Reg; +#[doc = "Input Key register 3 - Word-2"] +pub mod sgi_key3b; +#[doc = "sgi_key3c (rw) register accessor: Input Key register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3c`] module"] +#[doc(alias = "sgi_key3c")] +pub type SgiKey3c = crate::Reg; +#[doc = "Input Key register 3 - Word-1"] +pub mod sgi_key3c; +#[doc = "sgi_key3d (rw) register accessor: Input Key register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3d`] module"] +#[doc(alias = "sgi_key3d")] +pub type SgiKey3d = crate::Reg; +#[doc = "Input Key register 3 - Word-0"] +pub mod sgi_key3d; +#[doc = "sgi_key4a (rw) register accessor: Input Key register 4 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4a`] module"] +#[doc(alias = "sgi_key4a")] +pub type SgiKey4a = crate::Reg; +#[doc = "Input Key register 4 - Word-3"] +pub mod sgi_key4a; +#[doc = "sgi_key4b (rw) register accessor: Input Key register 4 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4b`] module"] +#[doc(alias = "sgi_key4b")] +pub type SgiKey4b = crate::Reg; +#[doc = "Input Key register 4 - Word-2"] +pub mod sgi_key4b; +#[doc = "sgi_key4c (rw) register accessor: Input Key register 4 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4c`] module"] +#[doc(alias = "sgi_key4c")] +pub type SgiKey4c = crate::Reg; +#[doc = "Input Key register 4 - Word-1"] +pub mod sgi_key4c; +#[doc = "sgi_key4d (rw) register accessor: Input Key register 4 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4d`] module"] +#[doc(alias = "sgi_key4d")] +pub type SgiKey4d = crate::Reg; +#[doc = "Input Key register 4 - Word-0"] +pub mod sgi_key4d; +#[doc = "sgi_key5a (rw) register accessor: Input Key register 5 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5a`] module"] +#[doc(alias = "sgi_key5a")] +pub type SgiKey5a = crate::Reg; +#[doc = "Input Key register 5 - Word-3"] +pub mod sgi_key5a; +#[doc = "sgi_key5b (rw) register accessor: Input Key register 5 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5b`] module"] +#[doc(alias = "sgi_key5b")] +pub type SgiKey5b = crate::Reg; +#[doc = "Input Key register 5 - Word-2"] +pub mod sgi_key5b; +#[doc = "sgi_key5c (rw) register accessor: Input Key register 5 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5c`] module"] +#[doc(alias = "sgi_key5c")] +pub type SgiKey5c = crate::Reg; +#[doc = "Input Key register 5 - Word-1"] +pub mod sgi_key5c; +#[doc = "sgi_key5d (rw) register accessor: Input Key register 5 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5d`] module"] +#[doc(alias = "sgi_key5d")] +pub type SgiKey5d = crate::Reg; +#[doc = "Input Key register 5 - Word-0"] +pub mod sgi_key5d; +#[doc = "sgi_key6a (rw) register accessor: Input Key register 6 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6a`] module"] +#[doc(alias = "sgi_key6a")] +pub type SgiKey6a = crate::Reg; +#[doc = "Input Key register 6 - Word-3"] +pub mod sgi_key6a; +#[doc = "sgi_key6b (rw) register accessor: Input Key register 6 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6b`] module"] +#[doc(alias = "sgi_key6b")] +pub type SgiKey6b = crate::Reg; +#[doc = "Input Key register 6 - Word-2"] +pub mod sgi_key6b; +#[doc = "sgi_key6c (rw) register accessor: Input Key register 6 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6c`] module"] +#[doc(alias = "sgi_key6c")] +pub type SgiKey6c = crate::Reg; +#[doc = "Input Key register 6 - Word-1"] +pub mod sgi_key6c; +#[doc = "sgi_key6d (rw) register accessor: Input Key register 6 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6d`] module"] +#[doc(alias = "sgi_key6d")] +pub type SgiKey6d = crate::Reg; +#[doc = "Input Key register 6 - Word-0"] +pub mod sgi_key6d; +#[doc = "sgi_key7a (rw) register accessor: Input Key register 7 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7a`] module"] +#[doc(alias = "sgi_key7a")] +pub type SgiKey7a = crate::Reg; +#[doc = "Input Key register 7 - Word-3"] +pub mod sgi_key7a; +#[doc = "sgi_key7b (rw) register accessor: Input Key register 7 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7b`] module"] +#[doc(alias = "sgi_key7b")] +pub type SgiKey7b = crate::Reg; +#[doc = "Input Key register 7 - Word-2"] +pub mod sgi_key7b; +#[doc = "sgi_key7c (rw) register accessor: Input Key register 7 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7c`] module"] +#[doc(alias = "sgi_key7c")] +pub type SgiKey7c = crate::Reg; +#[doc = "Input Key register 7 - Word-1"] +pub mod sgi_key7c; +#[doc = "sgi_key7d (rw) register accessor: Input Key register 7 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7d`] module"] +#[doc(alias = "sgi_key7d")] +pub type SgiKey7d = crate::Reg; +#[doc = "Input Key register 7 - Word-0"] +pub mod sgi_key7d; +#[doc = "sgi_datouta (rw) register accessor: Output Data register - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datouta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datouta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datouta`] module"] +#[doc(alias = "sgi_datouta")] +pub type SgiDatouta = crate::Reg; +#[doc = "Output Data register - Word-3"] +pub mod sgi_datouta; +#[doc = "sgi_datoutb (rw) register accessor: Output Data register - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datoutb`] module"] +#[doc(alias = "sgi_datoutb")] +pub type SgiDatoutb = crate::Reg; +#[doc = "Output Data register - Word-2"] +pub mod sgi_datoutb; +#[doc = "sgi_datoutc (rw) register accessor: Output Data register - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datoutc`] module"] +#[doc(alias = "sgi_datoutc")] +pub type SgiDatoutc = crate::Reg; +#[doc = "Output Data register - Word-1"] +pub mod sgi_datoutc; +#[doc = "sgi_datoutd (rw) register accessor: Output Data register - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datoutd`] module"] +#[doc(alias = "sgi_datoutd")] +pub type SgiDatoutd = crate::Reg; +#[doc = "Output Data register - Word-0"] +pub mod sgi_datoutd; +#[doc = "sgi_status (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_status`] module"] +#[doc(alias = "sgi_status")] +pub type SgiStatus = crate::Reg; +#[doc = "Status register"] +pub mod sgi_status; +#[doc = "sgi_count (rw) register accessor: Calculation counter\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_count`] module"] +#[doc(alias = "sgi_count")] +pub type SgiCount = crate::Reg; +#[doc = "Calculation counter"] +pub mod sgi_count; +#[doc = "sgi_keychk (rw) register accessor: Key checksum register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_keychk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_keychk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_keychk`] module"] +#[doc(alias = "sgi_keychk")] +pub type SgiKeychk = crate::Reg; +#[doc = "Key checksum register"] +pub mod sgi_keychk; +#[doc = "sgi_ctrl (rw) register accessor: SGI Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_ctrl`] module"] +#[doc(alias = "sgi_ctrl")] +pub type SgiCtrl = crate::Reg; +#[doc = "SGI Control register"] +pub mod sgi_ctrl; +#[doc = "sgi_ctrl2 (rw) register accessor: SGI Control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_ctrl2`] module"] +#[doc(alias = "sgi_ctrl2")] +pub type SgiCtrl2 = crate::Reg; +#[doc = "SGI Control register 2"] +pub mod sgi_ctrl2; +#[doc = "sgi_dummy_ctrl (rw) register accessor: Configuration of dummy controls\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_dummy_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_dummy_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_dummy_ctrl`] module"] +#[doc(alias = "sgi_dummy_ctrl")] +pub type SgiDummyCtrl = crate::Reg; +#[doc = "Configuration of dummy controls"] +pub mod sgi_dummy_ctrl; +#[doc = "sgi_sfr_sw_mask (rw) register accessor: Sofware Assisted Masking register .\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfr_sw_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfr_sw_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sfr_sw_mask`] module"] +#[doc(alias = "sgi_sfr_sw_mask")] +pub type SgiSfrSwMask = crate::Reg; +#[doc = "Sofware Assisted Masking register ."] +pub mod sgi_sfr_sw_mask; +#[doc = "sgi_sfrseed (rw) register accessor: SFRSEED register for SFRMASK feature.\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfrseed::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfrseed::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sfrseed`] module"] +#[doc(alias = "sgi_sfrseed")] +pub type SgiSfrseed = crate::Reg; +#[doc = "SFRSEED register for SFRMASK feature."] +pub mod sgi_sfrseed; +#[doc = "sgi_sha2_ctrl (rw) register accessor: SHA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sha2_ctrl`] module"] +#[doc(alias = "sgi_sha2_ctrl")] +pub type SgiSha2Ctrl = crate::Reg; +#[doc = "SHA Control Register"] +pub mod sgi_sha2_ctrl; +#[doc = "sgi_sha_fifo (rw) register accessor: SHA FIFO lower-bank low\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha_fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha_fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sha_fifo`] module"] +#[doc(alias = "sgi_sha_fifo")] +pub type SgiShaFifo = crate::Reg; +#[doc = "SHA FIFO lower-bank low"] +pub mod sgi_sha_fifo; +#[doc = "sgi_config (r) register accessor: SHA Configuration Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_config`] module"] +#[doc(alias = "sgi_config")] +pub type SgiConfig = crate::Reg; +#[doc = "SHA Configuration Reg"] +pub mod sgi_config; +#[doc = "sgi_config2 (r) register accessor: SHA Configuration 2 Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_config2`] module"] +#[doc(alias = "sgi_config2")] +pub type SgiConfig2 = crate::Reg; +#[doc = "SHA Configuration 2 Reg"] +pub mod sgi_config2; +#[doc = "sgi_auto_mode (rw) register accessor: SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_auto_mode`] module"] +#[doc(alias = "sgi_auto_mode")] +pub type SgiAutoMode = crate::Reg; +#[doc = "SGI Auto Mode Control register"] +pub mod sgi_auto_mode; +#[doc = "sgi_auto_dma_ctrl (rw) register accessor: SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_dma_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_dma_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_auto_dma_ctrl`] module"] +#[doc(alias = "sgi_auto_dma_ctrl")] +pub type SgiAutoDmaCtrl = crate::Reg; +#[doc = "SGI Auto Mode Control register"] +pub mod sgi_auto_dma_ctrl; +#[doc = "sgi_prng_sw_seed (rw) register accessor: SGI internal PRNG SW seeding register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_prng_sw_seed::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_prng_sw_seed::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_prng_sw_seed`] module"] +#[doc(alias = "sgi_prng_sw_seed")] +pub type SgiPrngSwSeed = crate::Reg; +#[doc = "SGI internal PRNG SW seeding register"] +pub mod sgi_prng_sw_seed; +#[doc = "sgi_key_ctrl (rw) register accessor: SGI Key Control SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key_ctrl`] module"] +#[doc(alias = "sgi_key_ctrl")] +pub type SgiKeyCtrl = crate::Reg; +#[doc = "SGI Key Control SFR"] +pub mod sgi_key_ctrl; +#[doc = "sgi_key_wrap (r) register accessor: Wrapped key read SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_wrap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key_wrap`] module"] +#[doc(alias = "sgi_key_wrap")] +pub type SgiKeyWrap = crate::Reg; +#[doc = "Wrapped key read SFR"] +pub mod sgi_key_wrap; +#[doc = "sgi_version (r) register accessor: SGI Version\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_version`] module"] +#[doc(alias = "sgi_version")] +pub type SgiVersion = crate::Reg; +#[doc = "SGI Version"] +pub mod sgi_version; +#[doc = "sgi_access_err (rw) register accessor: Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_access_err`] module"] +#[doc(alias = "sgi_access_err")] +pub type SgiAccessErr = crate::Reg; +#[doc = "Access Error"] +pub mod sgi_access_err; +#[doc = "sgi_access_err_clr (rw) register accessor: Clear Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_access_err_clr`] module"] +#[doc(alias = "sgi_access_err_clr")] +pub type SgiAccessErrClr = crate::Reg; +#[doc = "Clear Access Error"] +pub mod sgi_access_err_clr; +#[doc = "sgi_int_status (r) register accessor: Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_status`] module"] +#[doc(alias = "sgi_int_status")] +pub type SgiIntStatus = crate::Reg; +#[doc = "Interrupt status"] +pub mod sgi_int_status; +#[doc = "sgi_int_enable (rw) register accessor: Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_enable`] module"] +#[doc(alias = "sgi_int_enable")] +pub type SgiIntEnable = crate::Reg; +#[doc = "Interrupt enable"] +pub mod sgi_int_enable; +#[doc = "sgi_int_status_clr (rw) register accessor: Interrupt status clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_status_clr`] module"] +#[doc(alias = "sgi_int_status_clr")] +pub type SgiIntStatusClr = crate::Reg; +#[doc = "Interrupt status clear"] +pub mod sgi_int_status_clr; +#[doc = "sgi_int_status_set (rw) register accessor: Interrupt status set\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_status_set`] module"] +#[doc(alias = "sgi_int_status_set")] +pub type SgiIntStatusSet = crate::Reg; +#[doc = "Interrupt status set"] +pub mod sgi_int_status_set; +#[doc = "sgi_module_id (r) register accessor: Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_module_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_module_id`] module"] +#[doc(alias = "sgi_module_id")] +pub type SgiModuleId = crate::Reg; +#[doc = "Module ID"] +pub mod sgi_module_id; diff --git a/mcxa276-pac/src/sgi0/sgi_access_err.rs b/mcxa276-pac/src/sgi0/sgi_access_err.rs new file mode 100644 index 000000000..8eeef6094 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_access_err.rs @@ -0,0 +1,77 @@ +#[doc = "Register `sgi_access_err` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_access_err` writer"] +pub type W = crate::W; +#[doc = "Field `apb_notav` reader - APB Error: address not available"] +pub type ApbNotavR = crate::BitReader; +#[doc = "Field `apb_notav` writer - APB Error: address not available"] +pub type ApbNotavW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `apb_wrgmd` reader - APB Error: Wrong access mode"] +pub type ApbWrgmdR = crate::BitReader; +#[doc = "Field `apb_wrgmd` writer - APB Error: Wrong access mode"] +pub type ApbWrgmdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `accerr_rsvd1` reader - reserved for future erors on SPB I/F"] +pub type AccerrRsvd1R = crate::FieldReader; +#[doc = "Field `apb_master` reader - APB Master that triggered first APB error"] +pub type ApbMasterR = crate::FieldReader; +#[doc = "Field `apb_master` writer - APB Master that triggered first APB error"] +pub type ApbMasterW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `accerr_rsvd2` reader - reserved for more block errors"] +pub type AccerrRsvd2R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - APB Error: address not available"] + #[inline(always)] + pub fn apb_notav(&self) -> ApbNotavR { + ApbNotavR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - APB Error: Wrong access mode"] + #[inline(always)] + pub fn apb_wrgmd(&self) -> ApbWrgmdR { + ApbWrgmdR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - reserved for future erors on SPB I/F"] + #[inline(always)] + pub fn accerr_rsvd1(&self) -> AccerrRsvd1R { + AccerrRsvd1R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:7 - APB Master that triggered first APB error"] + #[inline(always)] + pub fn apb_master(&self) -> ApbMasterR { + ApbMasterR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:31 - reserved for more block errors"] + #[inline(always)] + pub fn accerr_rsvd2(&self) -> AccerrRsvd2R { + AccerrRsvd2R::new((self.bits >> 8) & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - APB Error: address not available"] + #[inline(always)] + pub fn apb_notav(&mut self) -> ApbNotavW { + ApbNotavW::new(self, 0) + } + #[doc = "Bit 1 - APB Error: Wrong access mode"] + #[inline(always)] + pub fn apb_wrgmd(&mut self) -> ApbWrgmdW { + ApbWrgmdW::new(self, 1) + } + #[doc = "Bits 4:7 - APB Master that triggered first APB error"] + #[inline(always)] + pub fn apb_master(&mut self) -> ApbMasterW { + ApbMasterW::new(self, 4) + } +} +#[doc = "Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiAccessErrSpec; +impl crate::RegisterSpec for SgiAccessErrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_access_err::R`](R) reader structure"] +impl crate::Readable for SgiAccessErrSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_access_err::W`](W) writer structure"] +impl crate::Writable for SgiAccessErrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_access_err to value 0"] +impl crate::Resettable for SgiAccessErrSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_access_err_clr.rs b/mcxa276-pac/src/sgi0/sgi_access_err_clr.rs new file mode 100644 index 000000000..c459674d7 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_access_err_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `sgi_access_err_clr` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_access_err_clr` writer"] +pub type W = crate::W; +#[doc = "Field `err_clr` reader - Write to reset SGI_ACCESS_ERR SFR."] +pub type ErrClrR = crate::BitReader; +#[doc = "Field `err_clr` writer - Write to reset SGI_ACCESS_ERR SFR."] +pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `accerrc_rsvd` reader - reserved"] +pub type AccerrcRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Write to reset SGI_ACCESS_ERR SFR."] + #[inline(always)] + pub fn err_clr(&self) -> ErrClrR { + ErrClrR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:31 - reserved"] + #[inline(always)] + pub fn accerrc_rsvd(&self) -> AccerrcRsvdR { + AccerrcRsvdR::new((self.bits >> 1) & 0x7fff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Write to reset SGI_ACCESS_ERR SFR."] + #[inline(always)] + pub fn err_clr(&mut self) -> ErrClrW { + ErrClrW::new(self, 0) + } +} +#[doc = "Clear Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiAccessErrClrSpec; +impl crate::RegisterSpec for SgiAccessErrClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_access_err_clr::R`](R) reader structure"] +impl crate::Readable for SgiAccessErrClrSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_access_err_clr::W`](W) writer structure"] +impl crate::Writable for SgiAccessErrClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_access_err_clr to value 0"] +impl crate::Resettable for SgiAccessErrClrSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs new file mode 100644 index 000000000..d27c4667b --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `sgi_auto_dma_ctrl` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_auto_dma_ctrl` writer"] +pub type W = crate::W; +#[doc = "Field `ife` reader - Input FIFO DMA Enable"] +pub type IfeR = crate::BitReader; +#[doc = "Field `ife` writer - Input FIFO DMA Enable"] +pub type IfeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `auto_dma_rsvd1` reader - reserved"] +pub type AutoDmaRsvd1R = crate::FieldReader; +#[doc = "Field `ofe` reader - Ouput FIFO DMA Enable"] +pub type OfeR = crate::BitReader; +#[doc = "Field `ofe` writer - Ouput FIFO DMA Enable"] +pub type OfeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `auto_dma_rsvd2` reader - reserved"] +pub type AutoDmaRsvd2R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Input FIFO DMA Enable"] + #[inline(always)] + pub fn ife(&self) -> IfeR { + IfeR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:7 - reserved"] + #[inline(always)] + pub fn auto_dma_rsvd1(&self) -> AutoDmaRsvd1R { + AutoDmaRsvd1R::new(((self.bits >> 1) & 0x7f) as u8) + } + #[doc = "Bit 8 - Ouput FIFO DMA Enable"] + #[inline(always)] + pub fn ofe(&self) -> OfeR { + OfeR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:31 - reserved"] + #[inline(always)] + pub fn auto_dma_rsvd2(&self) -> AutoDmaRsvd2R { + AutoDmaRsvd2R::new((self.bits >> 9) & 0x007f_ffff) + } +} +impl W { + #[doc = "Bit 0 - Input FIFO DMA Enable"] + #[inline(always)] + pub fn ife(&mut self) -> IfeW { + IfeW::new(self, 0) + } + #[doc = "Bit 8 - Ouput FIFO DMA Enable"] + #[inline(always)] + pub fn ofe(&mut self) -> OfeW { + OfeW::new(self, 8) + } +} +#[doc = "SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_dma_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_dma_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiAutoDmaCtrlSpec; +impl crate::RegisterSpec for SgiAutoDmaCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_auto_dma_ctrl::R`](R) reader structure"] +impl crate::Readable for SgiAutoDmaCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_auto_dma_ctrl::W`](W) writer structure"] +impl crate::Writable for SgiAutoDmaCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_auto_dma_ctrl to value 0"] +impl crate::Resettable for SgiAutoDmaCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_auto_mode.rs b/mcxa276-pac/src/sgi0/sgi_auto_mode.rs new file mode 100644 index 000000000..0ae39991a --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_auto_mode.rs @@ -0,0 +1,199 @@ +#[doc = "Register `sgi_auto_mode` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_auto_mode` writer"] +pub type W = crate::W; +#[doc = "Field `auto_mode_en` reader - auto_start_en"] +pub type AutoModeEnR = crate::BitReader; +#[doc = "Field `auto_mode_en` writer - auto_start_en"] +pub type AutoModeEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `auto_mode_stop` writer - auto_mode_stop"] +pub type AutoModeStopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `auto_mode_rsvd1` reader - reserved"] +pub type AutoModeRsvd1R = crate::FieldReader; +#[doc = "Field `incr_mode` reader - CTR increment mode"] +pub type IncrModeR = crate::FieldReader; +#[doc = "Field `incr_mode` writer - CTR increment mode"] +pub type IncrModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `auto_mode_rsvd2` reader - reserved"] +pub type AutoModeRsvd2R = crate::FieldReader; +#[doc = "Auto mode of operation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cmd { + #[doc = "0: 8'h00 - ECB mode"] + Ecb = 0, + #[doc = "1: 8'h01 - CTR mode"] + Ctr = 1, + #[doc = "2: 8'h02 - CBC mode"] + Cbc = 2, + #[doc = "3: 8'h03 - CBCMAC mode"] + Cbcmac = 3, + #[doc = "16: 8'h10 - Key Wrap/Unwrap(128 bit key data)"] + Kw128 = 16, + #[doc = "17: 8'h11 - Key Wrap/Unwrap(256 bit key data)"] + Kw256 = 17, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cmd) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cmd { + type Ux = u8; +} +impl crate::IsEnum for Cmd {} +#[doc = "Field `cmd` reader - Auto mode of operation"] +pub type CmdR = crate::FieldReader; +impl CmdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cmd::Ecb), + 1 => Some(Cmd::Ctr), + 2 => Some(Cmd::Cbc), + 3 => Some(Cmd::Cbcmac), + 16 => Some(Cmd::Kw128), + 17 => Some(Cmd::Kw256), + _ => None, + } + } + #[doc = "8'h00 - ECB mode"] + #[inline(always)] + pub fn is_ecb(&self) -> bool { + *self == Cmd::Ecb + } + #[doc = "8'h01 - CTR mode"] + #[inline(always)] + pub fn is_ctr(&self) -> bool { + *self == Cmd::Ctr + } + #[doc = "8'h02 - CBC mode"] + #[inline(always)] + pub fn is_cbc(&self) -> bool { + *self == Cmd::Cbc + } + #[doc = "8'h03 - CBCMAC mode"] + #[inline(always)] + pub fn is_cbcmac(&self) -> bool { + *self == Cmd::Cbcmac + } + #[doc = "8'h10 - Key Wrap/Unwrap(128 bit key data)"] + #[inline(always)] + pub fn is_kw128(&self) -> bool { + *self == Cmd::Kw128 + } + #[doc = "8'h11 - Key Wrap/Unwrap(256 bit key data)"] + #[inline(always)] + pub fn is_kw256(&self) -> bool { + *self == Cmd::Kw256 + } +} +#[doc = "Field `cmd` writer - Auto mode of operation"] +pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 8, Cmd>; +impl<'a, REG> CmdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "8'h00 - ECB mode"] + #[inline(always)] + pub fn ecb(self) -> &'a mut crate::W { + self.variant(Cmd::Ecb) + } + #[doc = "8'h01 - CTR mode"] + #[inline(always)] + pub fn ctr(self) -> &'a mut crate::W { + self.variant(Cmd::Ctr) + } + #[doc = "8'h02 - CBC mode"] + #[inline(always)] + pub fn cbc(self) -> &'a mut crate::W { + self.variant(Cmd::Cbc) + } + #[doc = "8'h03 - CBCMAC mode"] + #[inline(always)] + pub fn cbcmac(self) -> &'a mut crate::W { + self.variant(Cmd::Cbcmac) + } + #[doc = "8'h10 - Key Wrap/Unwrap(128 bit key data)"] + #[inline(always)] + pub fn kw128(self) -> &'a mut crate::W { + self.variant(Cmd::Kw128) + } + #[doc = "8'h11 - Key Wrap/Unwrap(256 bit key data)"] + #[inline(always)] + pub fn kw256(self) -> &'a mut crate::W { + self.variant(Cmd::Kw256) + } +} +#[doc = "Field `auto_mode_rsvd3` reader - reserved"] +pub type AutoModeRsvd3R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - auto_start_en"] + #[inline(always)] + pub fn auto_mode_en(&self) -> AutoModeEnR { + AutoModeEnR::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:3 - reserved"] + #[inline(always)] + pub fn auto_mode_rsvd1(&self) -> AutoModeRsvd1R { + AutoModeRsvd1R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - CTR increment mode"] + #[inline(always)] + pub fn incr_mode(&self) -> IncrModeR { + IncrModeR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - reserved"] + #[inline(always)] + pub fn auto_mode_rsvd2(&self) -> AutoModeRsvd2R { + AutoModeRsvd2R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:15 - Auto mode of operation"] + #[inline(always)] + pub fn cmd(&self) -> CmdR { + CmdR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:31 - reserved"] + #[inline(always)] + pub fn auto_mode_rsvd3(&self) -> AutoModeRsvd3R { + AutoModeRsvd3R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - auto_start_en"] + #[inline(always)] + pub fn auto_mode_en(&mut self) -> AutoModeEnW { + AutoModeEnW::new(self, 0) + } + #[doc = "Bit 1 - auto_mode_stop"] + #[inline(always)] + pub fn auto_mode_stop(&mut self) -> AutoModeStopW { + AutoModeStopW::new(self, 1) + } + #[doc = "Bits 4:5 - CTR increment mode"] + #[inline(always)] + pub fn incr_mode(&mut self) -> IncrModeW { + IncrModeW::new(self, 4) + } + #[doc = "Bits 8:15 - Auto mode of operation"] + #[inline(always)] + pub fn cmd(&mut self) -> CmdW { + CmdW::new(self, 8) + } +} +#[doc = "SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiAutoModeSpec; +impl crate::RegisterSpec for SgiAutoModeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_auto_mode::R`](R) reader structure"] +impl crate::Readable for SgiAutoModeSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_auto_mode::W`](W) writer structure"] +impl crate::Writable for SgiAutoModeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_auto_mode to value 0"] +impl crate::Resettable for SgiAutoModeSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_config.rs b/mcxa276-pac/src/sgi0/sgi_config.rs new file mode 100644 index 000000000..1d6091ed9 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_config.rs @@ -0,0 +1,188 @@ +#[doc = "Register `sgi_config` reader"] +pub type R = crate::R; +#[doc = "Field `row` reader - SGI Diversified for 'ROW'"] +pub type RowR = crate::BitReader; +#[doc = "Field `china` reader - SGI Diversified for 'CHINA'"] +pub type ChinaR = crate::BitReader; +#[doc = "Field `cc` reader - SGI Diversified for 'CC'"] +pub type CcR = crate::BitReader; +#[doc = "Field `has_aes` reader - HAS AES"] +pub type HasAesR = crate::BitReader; +#[doc = "Field `has_des` reader - HAS DES"] +pub type HasDesR = crate::BitReader; +#[doc = "Field `has_sha` reader - HAS SHA"] +pub type HasShaR = crate::BitReader; +#[doc = "Field `has_movem` reader - HAS MOVEM"] +pub type HasMovemR = crate::BitReader; +#[doc = "Field `has_cmac` reader - HAS CMAC"] +pub type HasCmacR = crate::BitReader; +#[doc = "Field `has_gfmul` reader - HAS GFMUL"] +pub type HasGfmulR = crate::BitReader; +#[doc = "Field `internal_prng` reader - HAS INTERNAL PRNG"] +pub type InternalPrngR = crate::BitReader; +#[doc = "Field `key_digest` reader - HAS KEY DIGEST"] +pub type KeyDigestR = crate::BitReader; +#[doc = "Field `count_size` reader - 0 - COUNT=16, 1 - COUNT=32"] +pub type CountSizeR = crate::BitReader; +#[doc = "Field `configc_rsvd` reader - reserved"] +pub type ConfigcRsvdR = crate::BitReader; +#[doc = "Field `fa` reader - HAS FA protection"] +pub type FaR = crate::BitReader; +#[doc = "Field `configb2_rsvd` reader - reserved"] +pub type Configb2RsvdR = crate::BitReader; +#[doc = "Field `bus_width` reader - 0 - BUS_WIDTH=16, 1 - BUS_WIDTH=32"] +pub type BusWidthR = crate::BitReader; +#[doc = "Field `num_datin` reader - NUMBER OF DATIN REGBANKS"] +pub type NumDatinR = crate::FieldReader; +#[doc = "Field `num_key` reader - NUMBER OR KEY REGBANKS"] +pub type NumKeyR = crate::FieldReader; +#[doc = "Field `edc` reader - DATIN to KERNEL End-to-end EDC is enabled"] +pub type EdcR = crate::BitReader; +#[doc = "Field `configb_rsvd` reader - reserved"] +pub type ConfigbRsvdR = crate::FieldReader; +#[doc = "Field `sha_256_only` reader - HAS SHA-256 ONLY"] +pub type Sha256OnlyR = crate::BitReader; +#[doc = "Field `spb_support` reader - ID_CFG_SGI_SPB_SUPPORT is set"] +pub type SpbSupportR = crate::BitReader; +#[doc = "Field `spb_masking` reader - ID_CFG_SGI_SPB_MASKING is set"] +pub type SpbMaskingR = crate::BitReader; +#[doc = "Field `sfr_sw_mask` reader - ID_CFG_SGI_USE_SFR_SW_MASK is set"] +pub type SfrSwMaskR = crate::BitReader; +#[doc = "Field `configa_rsvd` reader - reserved"] +pub type ConfigaRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - SGI Diversified for 'ROW'"] + #[inline(always)] + pub fn row(&self) -> RowR { + RowR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SGI Diversified for 'CHINA'"] + #[inline(always)] + pub fn china(&self) -> ChinaR { + ChinaR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SGI Diversified for 'CC'"] + #[inline(always)] + pub fn cc(&self) -> CcR { + CcR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - HAS AES"] + #[inline(always)] + pub fn has_aes(&self) -> HasAesR { + HasAesR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - HAS DES"] + #[inline(always)] + pub fn has_des(&self) -> HasDesR { + HasDesR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - HAS SHA"] + #[inline(always)] + pub fn has_sha(&self) -> HasShaR { + HasShaR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - HAS MOVEM"] + #[inline(always)] + pub fn has_movem(&self) -> HasMovemR { + HasMovemR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - HAS CMAC"] + #[inline(always)] + pub fn has_cmac(&self) -> HasCmacR { + HasCmacR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HAS GFMUL"] + #[inline(always)] + pub fn has_gfmul(&self) -> HasGfmulR { + HasGfmulR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HAS INTERNAL PRNG"] + #[inline(always)] + pub fn internal_prng(&self) -> InternalPrngR { + InternalPrngR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - HAS KEY DIGEST"] + #[inline(always)] + pub fn key_digest(&self) -> KeyDigestR { + KeyDigestR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 0 - COUNT=16, 1 - COUNT=32"] + #[inline(always)] + pub fn count_size(&self) -> CountSizeR { + CountSizeR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - reserved"] + #[inline(always)] + pub fn configc_rsvd(&self) -> ConfigcRsvdR { + ConfigcRsvdR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - HAS FA protection"] + #[inline(always)] + pub fn fa(&self) -> FaR { + FaR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - reserved"] + #[inline(always)] + pub fn configb2_rsvd(&self) -> Configb2RsvdR { + Configb2RsvdR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 0 - BUS_WIDTH=16, 1 - BUS_WIDTH=32"] + #[inline(always)] + pub fn bus_width(&self) -> BusWidthR { + BusWidthR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:17 - NUMBER OF DATIN REGBANKS"] + #[inline(always)] + pub fn num_datin(&self) -> NumDatinR { + NumDatinR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:20 - NUMBER OR KEY REGBANKS"] + #[inline(always)] + pub fn num_key(&self) -> NumKeyR { + NumKeyR::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bit 21 - DATIN to KERNEL End-to-end EDC is enabled"] + #[inline(always)] + pub fn edc(&self) -> EdcR { + EdcR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:23 - reserved"] + #[inline(always)] + pub fn configb_rsvd(&self) -> ConfigbRsvdR { + ConfigbRsvdR::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bit 24 - HAS SHA-256 ONLY"] + #[inline(always)] + pub fn sha_256_only(&self) -> Sha256OnlyR { + Sha256OnlyR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - ID_CFG_SGI_SPB_SUPPORT is set"] + #[inline(always)] + pub fn spb_support(&self) -> SpbSupportR { + SpbSupportR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - ID_CFG_SGI_SPB_MASKING is set"] + #[inline(always)] + pub fn spb_masking(&self) -> SpbMaskingR { + SpbMaskingR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - ID_CFG_SGI_USE_SFR_SW_MASK is set"] + #[inline(always)] + pub fn sfr_sw_mask(&self) -> SfrSwMaskR { + SfrSwMaskR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - reserved"] + #[inline(always)] + pub fn configa_rsvd(&self) -> ConfigaRsvdR { + ConfigaRsvdR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "SHA Configuration Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiConfigSpec; +impl crate::RegisterSpec for SgiConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_config::R`](R) reader structure"] +impl crate::Readable for SgiConfigSpec {} +#[doc = "`reset()` method sets sgi_config to value 0"] +impl crate::Resettable for SgiConfigSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_config2.rs b/mcxa276-pac/src/sgi0/sgi_config2.rs new file mode 100644 index 000000000..b8a3cc27c --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_config2.rs @@ -0,0 +1,62 @@ +#[doc = "Register `sgi_config2` reader"] +pub type R = crate::R; +#[doc = "Field `aes_used` reader - 0=Apollo; 1=Aegis; 2=Ayna; 3=Athenium; 4=Ajax;"] +pub type AesUsedR = crate::FieldReader; +#[doc = "Field `aes_num_sboxes` reader - Number of AES sboxes"] +pub type AesNumSboxesR = crate::FieldReader; +#[doc = "Field `aes_keysize` reader - 0=128-Only,1=192-Only, 2=256-Only, 3=All Keysizes"] +pub type AesKeysizeR = crate::FieldReader; +#[doc = "Field `config2b_rsvd` reader - reserved"] +pub type Config2bRsvdR = crate::FieldReader; +#[doc = "Field `des_used` reader - 0=Dakar; 1=Danube; 2=Depicta; 3=Digi; 4=Date;"] +pub type DesUsedR = crate::FieldReader; +#[doc = "Field `des_num_sboxes` reader - Number of DES sboxes"] +pub type DesNumSboxesR = crate::FieldReader; +#[doc = "Field `config2a_rsvd` reader - reserved"] +pub type Config2aRsvdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - 0=Apollo; 1=Aegis; 2=Ayna; 3=Athenium; 4=Ajax;"] + #[inline(always)] + pub fn aes_used(&self) -> AesUsedR { + AesUsedR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:8 - Number of AES sboxes"] + #[inline(always)] + pub fn aes_num_sboxes(&self) -> AesNumSboxesR { + AesNumSboxesR::new(((self.bits >> 4) & 0x1f) as u8) + } + #[doc = "Bits 9:10 - 0=128-Only,1=192-Only, 2=256-Only, 3=All Keysizes"] + #[inline(always)] + pub fn aes_keysize(&self) -> AesKeysizeR { + AesKeysizeR::new(((self.bits >> 9) & 3) as u8) + } + #[doc = "Bits 11:15 - reserved"] + #[inline(always)] + pub fn config2b_rsvd(&self) -> Config2bRsvdR { + Config2bRsvdR::new(((self.bits >> 11) & 0x1f) as u8) + } + #[doc = "Bits 16:19 - 0=Dakar; 1=Danube; 2=Depicta; 3=Digi; 4=Date;"] + #[inline(always)] + pub fn des_used(&self) -> DesUsedR { + DesUsedR::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:24 - Number of DES sboxes"] + #[inline(always)] + pub fn des_num_sboxes(&self) -> DesNumSboxesR { + DesNumSboxesR::new(((self.bits >> 20) & 0x1f) as u8) + } + #[doc = "Bits 25:31 - reserved"] + #[inline(always)] + pub fn config2a_rsvd(&self) -> Config2aRsvdR { + Config2aRsvdR::new(((self.bits >> 25) & 0x7f) as u8) + } +} +#[doc = "SHA Configuration 2 Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiConfig2Spec; +impl crate::RegisterSpec for SgiConfig2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_config2::R`](R) reader structure"] +impl crate::Readable for SgiConfig2Spec {} +#[doc = "`reset()` method sets sgi_config2 to value 0"] +impl crate::Resettable for SgiConfig2Spec {} diff --git a/mcxa276-pac/src/sgi0/sgi_count.rs b/mcxa276-pac/src/sgi0/sgi_count.rs new file mode 100644 index 000000000..16cced0a7 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_count.rs @@ -0,0 +1,42 @@ +#[doc = "Register `sgi_count` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_count` writer"] +pub type W = crate::W; +#[doc = "Field `count` reader - Calculation counter, incremented with"] +pub type CountR = crate::FieldReader; +#[doc = "Field `count` writer - Calculation counter, incremented with"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `count_rsvd` reader - reserved"] +pub type CountRsvdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Calculation counter, incremented with"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - reserved"] + #[inline(always)] + pub fn count_rsvd(&self) -> CountRsvdR { + CountRsvdR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Calculation counter, incremented with"] + #[inline(always)] + pub fn count(&mut self) -> CountW { + CountW::new(self, 0) + } +} +#[doc = "Calculation counter\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiCountSpec; +impl crate::RegisterSpec for SgiCountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_count::R`](R) reader structure"] +impl crate::Readable for SgiCountSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_count::W`](W) writer structure"] +impl crate::Writable for SgiCountSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_count to value 0"] +impl crate::Resettable for SgiCountSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_ctrl.rs new file mode 100644 index 000000000..7318a203e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_ctrl.rs @@ -0,0 +1,231 @@ +#[doc = "Register `sgi_ctrl` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_ctrl` writer"] +pub type W = crate::W; +#[doc = "Field `start` writer - Start crypto operation"] +pub type StartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `decrypt` reader - Sets Cipher direction(AES and DES)"] +pub type DecryptR = crate::BitReader; +#[doc = "Field `decrypt` writer - Sets Cipher direction(AES and DES)"] +pub type DecryptW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `aeskeysz` reader - Sets AES key size"] +pub type AeskeyszR = crate::FieldReader; +#[doc = "Field `aeskeysz` writer - Sets AES key size"] +pub type AeskeyszW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `crypto_op` reader - Sets 'Crypto Operation' type"] +pub type CryptoOpR = crate::FieldReader; +#[doc = "Field `crypto_op` writer - Sets 'Crypto Operation' type"] +pub type CryptoOpW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `insel` reader - 4'b0000 - DATIN\\[0\\]"] +pub type InselR = crate::FieldReader; +#[doc = "Field `insel` writer - 4'b0000 - DATIN\\[0\\]"] +pub type InselW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `outsel` reader - 3'b000 - DATOUT = 'Kernel Res'"] +pub type OutselR = crate::FieldReader; +#[doc = "Field `outsel` writer - 3'b000 - DATOUT = 'Kernel Res'"] +pub type OutselW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `datout_res` reader - Kernels data out options"] +pub type DatoutResR = crate::FieldReader; +#[doc = "Field `datout_res` writer - Kernels data out options"] +pub type DatoutResW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `aes_en` reader - AES Kernel Enable"] +pub type AesEnR = crate::BitReader; +#[doc = "Field `aes_en` writer - AES Kernel Enable"] +pub type AesEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `des_en` reader - DES Kernel Enable"] +pub type DesEnR = crate::BitReader; +#[doc = "Field `des_en` writer - DES Kernel Enable"] +pub type DesEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `gcm_en` reader - GFMUL Kernel Enable"] +pub type GcmEnR = crate::BitReader; +#[doc = "Field `gcm_en` writer - GFMUL Kernel Enable"] +pub type GcmEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `prng_en` reader - PRNG Enable(only if SGI has internal PRNG, Please"] +pub type PrngEnR = crate::BitReader; +#[doc = "Field `prng_en` writer - PRNG Enable(only if SGI has internal PRNG, Please"] +pub type PrngEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `inkeysel` reader - Input key selection"] +pub type InkeyselR = crate::FieldReader; +#[doc = "Field `inkeysel` writer - Input key selection"] +pub type InkeyselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `tdeskey` reader - Triple-DES Key Configuration"] +pub type TdeskeyR = crate::BitReader; +#[doc = "Field `tdeskey` writer - Triple-DES Key Configuration"] +pub type TdeskeyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `aes_no_kl` reader - AES No decryption key schedule"] +pub type AesNoKlR = crate::BitReader; +#[doc = "Field `aes_no_kl` writer - AES No decryption key schedule"] +pub type AesNoKlW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `aes_sel` reader - AES Dual Selection"] +pub type AesSelR = crate::BitReader; +#[doc = "Field `aes_sel` writer - AES Dual Selection"] +pub type AesSelW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ctrl_rsvd` reader - reserved"] +pub type CtrlRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 1 - Sets Cipher direction(AES and DES)"] + #[inline(always)] + pub fn decrypt(&self) -> DecryptR { + DecryptR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Sets AES key size"] + #[inline(always)] + pub fn aeskeysz(&self) -> AeskeyszR { + AeskeyszR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:6 - Sets 'Crypto Operation' type"] + #[inline(always)] + pub fn crypto_op(&self) -> CryptoOpR { + CryptoOpR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bits 7:10 - 4'b0000 - DATIN\\[0\\]"] + #[inline(always)] + pub fn insel(&self) -> InselR { + InselR::new(((self.bits >> 7) & 0x0f) as u8) + } + #[doc = "Bits 11:13 - 3'b000 - DATOUT = 'Kernel Res'"] + #[inline(always)] + pub fn outsel(&self) -> OutselR { + OutselR::new(((self.bits >> 11) & 7) as u8) + } + #[doc = "Bits 14:15 - Kernels data out options"] + #[inline(always)] + pub fn datout_res(&self) -> DatoutResR { + DatoutResR::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 16 - AES Kernel Enable"] + #[inline(always)] + pub fn aes_en(&self) -> AesEnR { + AesEnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DES Kernel Enable"] + #[inline(always)] + pub fn des_en(&self) -> DesEnR { + DesEnR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GFMUL Kernel Enable"] + #[inline(always)] + pub fn gcm_en(&self) -> GcmEnR { + GcmEnR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - PRNG Enable(only if SGI has internal PRNG, Please"] + #[inline(always)] + pub fn prng_en(&self) -> PrngEnR { + PrngEnR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:24 - Input key selection"] + #[inline(always)] + pub fn inkeysel(&self) -> InkeyselR { + InkeyselR::new(((self.bits >> 20) & 0x1f) as u8) + } + #[doc = "Bit 25 - Triple-DES Key Configuration"] + #[inline(always)] + pub fn tdeskey(&self) -> TdeskeyR { + TdeskeyR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - AES No decryption key schedule"] + #[inline(always)] + pub fn aes_no_kl(&self) -> AesNoKlR { + AesNoKlR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - AES Dual Selection"] + #[inline(always)] + pub fn aes_sel(&self) -> AesSelR { + AesSelR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - reserved"] + #[inline(always)] + pub fn ctrl_rsvd(&self) -> CtrlRsvdR { + CtrlRsvdR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Start crypto operation"] + #[inline(always)] + pub fn start(&mut self) -> StartW { + StartW::new(self, 0) + } + #[doc = "Bit 1 - Sets Cipher direction(AES and DES)"] + #[inline(always)] + pub fn decrypt(&mut self) -> DecryptW { + DecryptW::new(self, 1) + } + #[doc = "Bits 2:3 - Sets AES key size"] + #[inline(always)] + pub fn aeskeysz(&mut self) -> AeskeyszW { + AeskeyszW::new(self, 2) + } + #[doc = "Bits 4:6 - Sets 'Crypto Operation' type"] + #[inline(always)] + pub fn crypto_op(&mut self) -> CryptoOpW { + CryptoOpW::new(self, 4) + } + #[doc = "Bits 7:10 - 4'b0000 - DATIN\\[0\\]"] + #[inline(always)] + pub fn insel(&mut self) -> InselW { + InselW::new(self, 7) + } + #[doc = "Bits 11:13 - 3'b000 - DATOUT = 'Kernel Res'"] + #[inline(always)] + pub fn outsel(&mut self) -> OutselW { + OutselW::new(self, 11) + } + #[doc = "Bits 14:15 - Kernels data out options"] + #[inline(always)] + pub fn datout_res(&mut self) -> DatoutResW { + DatoutResW::new(self, 14) + } + #[doc = "Bit 16 - AES Kernel Enable"] + #[inline(always)] + pub fn aes_en(&mut self) -> AesEnW { + AesEnW::new(self, 16) + } + #[doc = "Bit 17 - DES Kernel Enable"] + #[inline(always)] + pub fn des_en(&mut self) -> DesEnW { + DesEnW::new(self, 17) + } + #[doc = "Bit 18 - GFMUL Kernel Enable"] + #[inline(always)] + pub fn gcm_en(&mut self) -> GcmEnW { + GcmEnW::new(self, 18) + } + #[doc = "Bit 19 - PRNG Enable(only if SGI has internal PRNG, Please"] + #[inline(always)] + pub fn prng_en(&mut self) -> PrngEnW { + PrngEnW::new(self, 19) + } + #[doc = "Bits 20:24 - Input key selection"] + #[inline(always)] + pub fn inkeysel(&mut self) -> InkeyselW { + InkeyselW::new(self, 20) + } + #[doc = "Bit 25 - Triple-DES Key Configuration"] + #[inline(always)] + pub fn tdeskey(&mut self) -> TdeskeyW { + TdeskeyW::new(self, 25) + } + #[doc = "Bit 26 - AES No decryption key schedule"] + #[inline(always)] + pub fn aes_no_kl(&mut self) -> AesNoKlW { + AesNoKlW::new(self, 26) + } + #[doc = "Bit 27 - AES Dual Selection"] + #[inline(always)] + pub fn aes_sel(&mut self) -> AesSelW { + AesSelW::new(self, 27) + } +} +#[doc = "SGI Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiCtrlSpec; +impl crate::RegisterSpec for SgiCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_ctrl::R`](R) reader structure"] +impl crate::Readable for SgiCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_ctrl::W`](W) writer structure"] +impl crate::Writable for SgiCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_ctrl to value 0"] +impl crate::Resettable for SgiCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_ctrl2.rs b/mcxa276-pac/src/sgi0/sgi_ctrl2.rs new file mode 100644 index 000000000..2a596063d --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_ctrl2.rs @@ -0,0 +1,231 @@ +#[doc = "Register `sgi_ctrl2` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_ctrl2` writer"] +pub type W = crate::W; +#[doc = "Field `flush` writer - Start Full SGI Flush"] +pub type FlushW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `key_flush` writer - Start KEY register-bank Flush"] +pub type KeyFlushW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `datin_flush` writer - Start DATIN register-bank Flush"] +pub type DatinFlushW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `incr` reader - Increment(Triggered by SFR write)"] +pub type IncrR = crate::BitReader; +#[doc = "Field `incr` writer - Increment(Triggered by SFR write)"] +pub type IncrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `xorwr` reader - Write-XOR control"] +pub type XorwrR = crate::BitReader; +#[doc = "Field `xorwr` writer - Write-XOR control"] +pub type XorwrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `flushwr` reader - Flush Write control"] +pub type FlushwrR = crate::BitReader; +#[doc = "Field `flushwr` writer - Flush Write control"] +pub type FlushwrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `incr_cin` reader - Increment Carry-In control"] +pub type IncrCinR = crate::BitReader; +#[doc = "Field `incr_cin` writer - Increment Carry-In control"] +pub type IncrCinW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ctrl2_rsvd3` reader - reserved"] +pub type Ctrl2Rsvd3R = crate::BitReader; +#[doc = "Field `smasken` reader - SFRMASK Enable"] +pub type SmaskenR = crate::BitReader; +#[doc = "Field `smasken` writer - SFRMASK Enable"] +pub type SmaskenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smaskstep` reader - SFRSEED increment control"] +pub type SmaskstepR = crate::BitReader; +#[doc = "Field `smaskstep` writer - SFRSEED increment control"] +pub type SmaskstepW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `smasksw` reader - SFRMASK MASK control"] +pub type SmaskswR = crate::BitReader; +#[doc = "Field `smasksw` writer - SFRMASK MASK control"] +pub type SmaskswW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ctrl2_rsvd2` reader - reserved"] +pub type Ctrl2Rsvd2R = crate::BitReader; +#[doc = "Field `movem` reader - 4-bit optional input for MOVEM feature"] +pub type MovemR = crate::FieldReader; +#[doc = "Field `movem` writer - 4-bit optional input for MOVEM feature"] +pub type MovemW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `keyres` reader - Selects key registers to be updated when rkey=1"] +pub type KeyresR = crate::FieldReader; +#[doc = "Field `keyres` writer - Selects key registers to be updated when rkey=1"] +pub type KeyresW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `rkey` reader - Crypto result location"] +pub type RkeyR = crate::BitReader; +#[doc = "Field `rkey` writer - Crypto result location"] +pub type RkeyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `bytes_order` reader - Byte order of regbank read/write data"] +pub type BytesOrderR = crate::BitReader; +#[doc = "Field `bytes_order` writer - Byte order of regbank read/write data"] +pub type BytesOrderW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `gcm_inxor` reader - GCM INXOR"] +pub type GcmInxorR = crate::BitReader; +#[doc = "Field `gcm_inxor` writer - GCM INXOR"] +pub type GcmInxorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ctrl2_rsvd1` reader - reserved"] +pub type Ctrl2Rsvd1R = crate::FieldReader; +impl R { + #[doc = "Bit 3 - Increment(Triggered by SFR write)"] + #[inline(always)] + pub fn incr(&self) -> IncrR { + IncrR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write-XOR control"] + #[inline(always)] + pub fn xorwr(&self) -> XorwrR { + XorwrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Flush Write control"] + #[inline(always)] + pub fn flushwr(&self) -> FlushwrR { + FlushwrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Increment Carry-In control"] + #[inline(always)] + pub fn incr_cin(&self) -> IncrCinR { + IncrCinR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - reserved"] + #[inline(always)] + pub fn ctrl2_rsvd3(&self) -> Ctrl2Rsvd3R { + Ctrl2Rsvd3R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - SFRMASK Enable"] + #[inline(always)] + pub fn smasken(&self) -> SmaskenR { + SmaskenR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SFRSEED increment control"] + #[inline(always)] + pub fn smaskstep(&self) -> SmaskstepR { + SmaskstepR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SFRMASK MASK control"] + #[inline(always)] + pub fn smasksw(&self) -> SmaskswR { + SmaskswR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - reserved"] + #[inline(always)] + pub fn ctrl2_rsvd2(&self) -> Ctrl2Rsvd2R { + Ctrl2Rsvd2R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - 4-bit optional input for MOVEM feature"] + #[inline(always)] + pub fn movem(&self) -> MovemR { + MovemR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:20 - Selects key registers to be updated when rkey=1"] + #[inline(always)] + pub fn keyres(&self) -> KeyresR { + KeyresR::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 21 - Crypto result location"] + #[inline(always)] + pub fn rkey(&self) -> RkeyR { + RkeyR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Byte order of regbank read/write data"] + #[inline(always)] + pub fn bytes_order(&self) -> BytesOrderR { + BytesOrderR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - GCM INXOR"] + #[inline(always)] + pub fn gcm_inxor(&self) -> GcmInxorR { + GcmInxorR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:31 - reserved"] + #[inline(always)] + pub fn ctrl2_rsvd1(&self) -> Ctrl2Rsvd1R { + Ctrl2Rsvd1R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 0 - Start Full SGI Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FlushW { + FlushW::new(self, 0) + } + #[doc = "Bit 1 - Start KEY register-bank Flush"] + #[inline(always)] + pub fn key_flush(&mut self) -> KeyFlushW { + KeyFlushW::new(self, 1) + } + #[doc = "Bit 2 - Start DATIN register-bank Flush"] + #[inline(always)] + pub fn datin_flush(&mut self) -> DatinFlushW { + DatinFlushW::new(self, 2) + } + #[doc = "Bit 3 - Increment(Triggered by SFR write)"] + #[inline(always)] + pub fn incr(&mut self) -> IncrW { + IncrW::new(self, 3) + } + #[doc = "Bit 4 - Write-XOR control"] + #[inline(always)] + pub fn xorwr(&mut self) -> XorwrW { + XorwrW::new(self, 4) + } + #[doc = "Bit 5 - Flush Write control"] + #[inline(always)] + pub fn flushwr(&mut self) -> FlushwrW { + FlushwrW::new(self, 5) + } + #[doc = "Bit 6 - Increment Carry-In control"] + #[inline(always)] + pub fn incr_cin(&mut self) -> IncrCinW { + IncrCinW::new(self, 6) + } + #[doc = "Bit 8 - SFRMASK Enable"] + #[inline(always)] + pub fn smasken(&mut self) -> SmaskenW { + SmaskenW::new(self, 8) + } + #[doc = "Bit 9 - SFRSEED increment control"] + #[inline(always)] + pub fn smaskstep(&mut self) -> SmaskstepW { + SmaskstepW::new(self, 9) + } + #[doc = "Bit 10 - SFRMASK MASK control"] + #[inline(always)] + pub fn smasksw(&mut self) -> SmaskswW { + SmaskswW::new(self, 10) + } + #[doc = "Bits 12:15 - 4-bit optional input for MOVEM feature"] + #[inline(always)] + pub fn movem(&mut self) -> MovemW { + MovemW::new(self, 12) + } + #[doc = "Bits 16:20 - Selects key registers to be updated when rkey=1"] + #[inline(always)] + pub fn keyres(&mut self) -> KeyresW { + KeyresW::new(self, 16) + } + #[doc = "Bit 21 - Crypto result location"] + #[inline(always)] + pub fn rkey(&mut self) -> RkeyW { + RkeyW::new(self, 21) + } + #[doc = "Bit 22 - Byte order of regbank read/write data"] + #[inline(always)] + pub fn bytes_order(&mut self) -> BytesOrderW { + BytesOrderW::new(self, 22) + } + #[doc = "Bit 23 - GCM INXOR"] + #[inline(always)] + pub fn gcm_inxor(&mut self) -> GcmInxorW { + GcmInxorW::new(self, 23) + } +} +#[doc = "SGI Control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiCtrl2Spec; +impl crate::RegisterSpec for SgiCtrl2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_ctrl2::R`](R) reader structure"] +impl crate::Readable for SgiCtrl2Spec {} +#[doc = "`write(|w| ..)` method takes [`sgi_ctrl2::W`](W) writer structure"] +impl crate::Writable for SgiCtrl2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_ctrl2 to value 0"] +impl crate::Resettable for SgiCtrl2Spec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0a.rs b/mcxa276-pac/src/sgi0/sgi_datin0a.rs new file mode 100644 index 000000000..4db91b17b --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin0a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin0a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin0a` writer"] +pub type W = crate::W; +#[doc = "Field `datin0a` reader - Input Data register"] +pub type Datin0aR = crate::FieldReader; +#[doc = "Field `datin0a` writer - Input Data register"] +pub type Datin0aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0a(&self) -> Datin0aR { + Datin0aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0a(&mut self) -> Datin0aW { + Datin0aW::new(self, 0) + } +} +#[doc = "Input Data register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin0aSpec; +impl crate::RegisterSpec for SgiDatin0aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin0a::R`](R) reader structure"] +impl crate::Readable for SgiDatin0aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin0a::W`](W) writer structure"] +impl crate::Writable for SgiDatin0aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin0a to value 0"] +impl crate::Resettable for SgiDatin0aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0b.rs b/mcxa276-pac/src/sgi0/sgi_datin0b.rs new file mode 100644 index 000000000..47e6c55af --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin0b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin0b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin0b` writer"] +pub type W = crate::W; +#[doc = "Field `datin0b` reader - Input Data register"] +pub type Datin0bR = crate::FieldReader; +#[doc = "Field `datin0b` writer - Input Data register"] +pub type Datin0bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0b(&self) -> Datin0bR { + Datin0bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0b(&mut self) -> Datin0bW { + Datin0bW::new(self, 0) + } +} +#[doc = "Input Data register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin0bSpec; +impl crate::RegisterSpec for SgiDatin0bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin0b::R`](R) reader structure"] +impl crate::Readable for SgiDatin0bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin0b::W`](W) writer structure"] +impl crate::Writable for SgiDatin0bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin0b to value 0"] +impl crate::Resettable for SgiDatin0bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0c.rs b/mcxa276-pac/src/sgi0/sgi_datin0c.rs new file mode 100644 index 000000000..d63ae5258 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin0c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin0c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin0c` writer"] +pub type W = crate::W; +#[doc = "Field `datin0c` reader - Input Data register"] +pub type Datin0cR = crate::FieldReader; +#[doc = "Field `datin0c` writer - Input Data register"] +pub type Datin0cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0c(&self) -> Datin0cR { + Datin0cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0c(&mut self) -> Datin0cW { + Datin0cW::new(self, 0) + } +} +#[doc = "Input Data register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin0cSpec; +impl crate::RegisterSpec for SgiDatin0cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin0c::R`](R) reader structure"] +impl crate::Readable for SgiDatin0cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin0c::W`](W) writer structure"] +impl crate::Writable for SgiDatin0cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin0c to value 0"] +impl crate::Resettable for SgiDatin0cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0d.rs b/mcxa276-pac/src/sgi0/sgi_datin0d.rs new file mode 100644 index 000000000..a348ebab6 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin0d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin0d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin0d` writer"] +pub type W = crate::W; +#[doc = "Field `datin0d` reader - Input Data register"] +pub type Datin0dR = crate::FieldReader; +#[doc = "Field `datin0d` writer - Input Data register"] +pub type Datin0dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0d(&self) -> Datin0dR { + Datin0dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin0d(&mut self) -> Datin0dW { + Datin0dW::new(self, 0) + } +} +#[doc = "Input Data register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin0dSpec; +impl crate::RegisterSpec for SgiDatin0dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin0d::R`](R) reader structure"] +impl crate::Readable for SgiDatin0dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin0d::W`](W) writer structure"] +impl crate::Writable for SgiDatin0dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin0d to value 0"] +impl crate::Resettable for SgiDatin0dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1a.rs b/mcxa276-pac/src/sgi0/sgi_datin1a.rs new file mode 100644 index 000000000..2fa0e17f4 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin1a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin1a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin1a` writer"] +pub type W = crate::W; +#[doc = "Field `datin1a` reader - Input Data register"] +pub type Datin1aR = crate::FieldReader; +#[doc = "Field `datin1a` writer - Input Data register"] +pub type Datin1aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1a(&self) -> Datin1aR { + Datin1aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1a(&mut self) -> Datin1aW { + Datin1aW::new(self, 0) + } +} +#[doc = "Input Data register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin1aSpec; +impl crate::RegisterSpec for SgiDatin1aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin1a::R`](R) reader structure"] +impl crate::Readable for SgiDatin1aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin1a::W`](W) writer structure"] +impl crate::Writable for SgiDatin1aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin1a to value 0"] +impl crate::Resettable for SgiDatin1aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1b.rs b/mcxa276-pac/src/sgi0/sgi_datin1b.rs new file mode 100644 index 000000000..1c05f86b4 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin1b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin1b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin1b` writer"] +pub type W = crate::W; +#[doc = "Field `datin1b` reader - Input Data register"] +pub type Datin1bR = crate::FieldReader; +#[doc = "Field `datin1b` writer - Input Data register"] +pub type Datin1bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1b(&self) -> Datin1bR { + Datin1bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1b(&mut self) -> Datin1bW { + Datin1bW::new(self, 0) + } +} +#[doc = "Input Data register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin1bSpec; +impl crate::RegisterSpec for SgiDatin1bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin1b::R`](R) reader structure"] +impl crate::Readable for SgiDatin1bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin1b::W`](W) writer structure"] +impl crate::Writable for SgiDatin1bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin1b to value 0"] +impl crate::Resettable for SgiDatin1bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1c.rs b/mcxa276-pac/src/sgi0/sgi_datin1c.rs new file mode 100644 index 000000000..8b82af66e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin1c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin1c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin1c` writer"] +pub type W = crate::W; +#[doc = "Field `datin1c` reader - Input Data register"] +pub type Datin1cR = crate::FieldReader; +#[doc = "Field `datin1c` writer - Input Data register"] +pub type Datin1cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1c(&self) -> Datin1cR { + Datin1cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1c(&mut self) -> Datin1cW { + Datin1cW::new(self, 0) + } +} +#[doc = "Input Data register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin1cSpec; +impl crate::RegisterSpec for SgiDatin1cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin1c::R`](R) reader structure"] +impl crate::Readable for SgiDatin1cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin1c::W`](W) writer structure"] +impl crate::Writable for SgiDatin1cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin1c to value 0"] +impl crate::Resettable for SgiDatin1cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1d.rs b/mcxa276-pac/src/sgi0/sgi_datin1d.rs new file mode 100644 index 000000000..772a51785 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin1d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin1d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin1d` writer"] +pub type W = crate::W; +#[doc = "Field `datin1d` reader - Input Data register"] +pub type Datin1dR = crate::FieldReader; +#[doc = "Field `datin1d` writer - Input Data register"] +pub type Datin1dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1d(&self) -> Datin1dR { + Datin1dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin1d(&mut self) -> Datin1dW { + Datin1dW::new(self, 0) + } +} +#[doc = "Input Data register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin1dSpec; +impl crate::RegisterSpec for SgiDatin1dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin1d::R`](R) reader structure"] +impl crate::Readable for SgiDatin1dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin1d::W`](W) writer structure"] +impl crate::Writable for SgiDatin1dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin1d to value 0"] +impl crate::Resettable for SgiDatin1dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2a.rs b/mcxa276-pac/src/sgi0/sgi_datin2a.rs new file mode 100644 index 000000000..9f9751e2e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin2a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin2a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin2a` writer"] +pub type W = crate::W; +#[doc = "Field `datin2a` reader - Input Data register"] +pub type Datin2aR = crate::FieldReader; +#[doc = "Field `datin2a` writer - Input Data register"] +pub type Datin2aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2a(&self) -> Datin2aR { + Datin2aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2a(&mut self) -> Datin2aW { + Datin2aW::new(self, 0) + } +} +#[doc = "Input Data register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin2aSpec; +impl crate::RegisterSpec for SgiDatin2aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin2a::R`](R) reader structure"] +impl crate::Readable for SgiDatin2aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin2a::W`](W) writer structure"] +impl crate::Writable for SgiDatin2aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin2a to value 0"] +impl crate::Resettable for SgiDatin2aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2b.rs b/mcxa276-pac/src/sgi0/sgi_datin2b.rs new file mode 100644 index 000000000..060706280 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin2b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin2b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin2b` writer"] +pub type W = crate::W; +#[doc = "Field `datin2b` reader - Input Data register"] +pub type Datin2bR = crate::FieldReader; +#[doc = "Field `datin2b` writer - Input Data register"] +pub type Datin2bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2b(&self) -> Datin2bR { + Datin2bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2b(&mut self) -> Datin2bW { + Datin2bW::new(self, 0) + } +} +#[doc = "Input Data register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin2bSpec; +impl crate::RegisterSpec for SgiDatin2bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin2b::R`](R) reader structure"] +impl crate::Readable for SgiDatin2bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin2b::W`](W) writer structure"] +impl crate::Writable for SgiDatin2bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin2b to value 0"] +impl crate::Resettable for SgiDatin2bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2c.rs b/mcxa276-pac/src/sgi0/sgi_datin2c.rs new file mode 100644 index 000000000..f76c5e7b5 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin2c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin2c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin2c` writer"] +pub type W = crate::W; +#[doc = "Field `datin2c` reader - Input Data register"] +pub type Datin2cR = crate::FieldReader; +#[doc = "Field `datin2c` writer - Input Data register"] +pub type Datin2cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2c(&self) -> Datin2cR { + Datin2cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2c(&mut self) -> Datin2cW { + Datin2cW::new(self, 0) + } +} +#[doc = "Input Data register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin2cSpec; +impl crate::RegisterSpec for SgiDatin2cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin2c::R`](R) reader structure"] +impl crate::Readable for SgiDatin2cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin2c::W`](W) writer structure"] +impl crate::Writable for SgiDatin2cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin2c to value 0"] +impl crate::Resettable for SgiDatin2cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2d.rs b/mcxa276-pac/src/sgi0/sgi_datin2d.rs new file mode 100644 index 000000000..5fdd6ea5e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin2d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin2d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin2d` writer"] +pub type W = crate::W; +#[doc = "Field `datin2d` reader - Input Data register"] +pub type Datin2dR = crate::FieldReader; +#[doc = "Field `datin2d` writer - Input Data register"] +pub type Datin2dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2d(&self) -> Datin2dR { + Datin2dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin2d(&mut self) -> Datin2dW { + Datin2dW::new(self, 0) + } +} +#[doc = "Input Data register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin2dSpec; +impl crate::RegisterSpec for SgiDatin2dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin2d::R`](R) reader structure"] +impl crate::Readable for SgiDatin2dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin2d::W`](W) writer structure"] +impl crate::Writable for SgiDatin2dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin2d to value 0"] +impl crate::Resettable for SgiDatin2dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3a.rs b/mcxa276-pac/src/sgi0/sgi_datin3a.rs new file mode 100644 index 000000000..9e860357d --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin3a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin3a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin3a` writer"] +pub type W = crate::W; +#[doc = "Field `datin3a` reader - Input Data register"] +pub type Datin3aR = crate::FieldReader; +#[doc = "Field `datin3a` writer - Input Data register"] +pub type Datin3aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3a(&self) -> Datin3aR { + Datin3aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3a(&mut self) -> Datin3aW { + Datin3aW::new(self, 0) + } +} +#[doc = "Input Data register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin3aSpec; +impl crate::RegisterSpec for SgiDatin3aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin3a::R`](R) reader structure"] +impl crate::Readable for SgiDatin3aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin3a::W`](W) writer structure"] +impl crate::Writable for SgiDatin3aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin3a to value 0"] +impl crate::Resettable for SgiDatin3aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3b.rs b/mcxa276-pac/src/sgi0/sgi_datin3b.rs new file mode 100644 index 000000000..4e0c08fc3 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin3b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin3b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin3b` writer"] +pub type W = crate::W; +#[doc = "Field `datin3b` reader - Input Data register"] +pub type Datin3bR = crate::FieldReader; +#[doc = "Field `datin3b` writer - Input Data register"] +pub type Datin3bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3b(&self) -> Datin3bR { + Datin3bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3b(&mut self) -> Datin3bW { + Datin3bW::new(self, 0) + } +} +#[doc = "Input Data register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin3bSpec; +impl crate::RegisterSpec for SgiDatin3bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin3b::R`](R) reader structure"] +impl crate::Readable for SgiDatin3bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin3b::W`](W) writer structure"] +impl crate::Writable for SgiDatin3bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin3b to value 0"] +impl crate::Resettable for SgiDatin3bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3c.rs b/mcxa276-pac/src/sgi0/sgi_datin3c.rs new file mode 100644 index 000000000..1f58a4439 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin3c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin3c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin3c` writer"] +pub type W = crate::W; +#[doc = "Field `datin3c` reader - Input Data register"] +pub type Datin3cR = crate::FieldReader; +#[doc = "Field `datin3c` writer - Input Data register"] +pub type Datin3cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3c(&self) -> Datin3cR { + Datin3cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3c(&mut self) -> Datin3cW { + Datin3cW::new(self, 0) + } +} +#[doc = "Input Data register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin3cSpec; +impl crate::RegisterSpec for SgiDatin3cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin3c::R`](R) reader structure"] +impl crate::Readable for SgiDatin3cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin3c::W`](W) writer structure"] +impl crate::Writable for SgiDatin3cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin3c to value 0"] +impl crate::Resettable for SgiDatin3cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3d.rs b/mcxa276-pac/src/sgi0/sgi_datin3d.rs new file mode 100644 index 000000000..c32d30b38 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datin3d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datin3d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datin3d` writer"] +pub type W = crate::W; +#[doc = "Field `datin3d` reader - Input Data register"] +pub type Datin3dR = crate::FieldReader; +#[doc = "Field `datin3d` writer - Input Data register"] +pub type Datin3dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3d(&self) -> Datin3dR { + Datin3dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Data register"] + #[inline(always)] + pub fn datin3d(&mut self) -> Datin3dW { + Datin3dW::new(self, 0) + } +} +#[doc = "Input Data register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatin3dSpec; +impl crate::RegisterSpec for SgiDatin3dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datin3d::R`](R) reader structure"] +impl crate::Readable for SgiDatin3dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datin3d::W`](W) writer structure"] +impl crate::Writable for SgiDatin3dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datin3d to value 0"] +impl crate::Resettable for SgiDatin3dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datouta.rs b/mcxa276-pac/src/sgi0/sgi_datouta.rs new file mode 100644 index 000000000..175bb01d6 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datouta.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datouta` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datouta` writer"] +pub type W = crate::W; +#[doc = "Field `datouta` reader - Output Data register"] +pub type DatoutaR = crate::FieldReader; +#[doc = "Field `datouta` writer - Output Data register"] +pub type DatoutaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datouta(&self) -> DatoutaR { + DatoutaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datouta(&mut self) -> DatoutaW { + DatoutaW::new(self, 0) + } +} +#[doc = "Output Data register - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datouta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datouta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatoutaSpec; +impl crate::RegisterSpec for SgiDatoutaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datouta::R`](R) reader structure"] +impl crate::Readable for SgiDatoutaSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datouta::W`](W) writer structure"] +impl crate::Writable for SgiDatoutaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datouta to value 0"] +impl crate::Resettable for SgiDatoutaSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datoutb.rs b/mcxa276-pac/src/sgi0/sgi_datoutb.rs new file mode 100644 index 000000000..785fe870c --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datoutb.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datoutb` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datoutb` writer"] +pub type W = crate::W; +#[doc = "Field `datoutb` reader - Output Data register"] +pub type DatoutbR = crate::FieldReader; +#[doc = "Field `datoutb` writer - Output Data register"] +pub type DatoutbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datoutb(&self) -> DatoutbR { + DatoutbR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datoutb(&mut self) -> DatoutbW { + DatoutbW::new(self, 0) + } +} +#[doc = "Output Data register - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatoutbSpec; +impl crate::RegisterSpec for SgiDatoutbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datoutb::R`](R) reader structure"] +impl crate::Readable for SgiDatoutbSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datoutb::W`](W) writer structure"] +impl crate::Writable for SgiDatoutbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datoutb to value 0"] +impl crate::Resettable for SgiDatoutbSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datoutc.rs b/mcxa276-pac/src/sgi0/sgi_datoutc.rs new file mode 100644 index 000000000..a38081e6a --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datoutc.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datoutc` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datoutc` writer"] +pub type W = crate::W; +#[doc = "Field `datoutc` reader - Output Data register"] +pub type DatoutcR = crate::FieldReader; +#[doc = "Field `datoutc` writer - Output Data register"] +pub type DatoutcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datoutc(&self) -> DatoutcR { + DatoutcR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datoutc(&mut self) -> DatoutcW { + DatoutcW::new(self, 0) + } +} +#[doc = "Output Data register - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatoutcSpec; +impl crate::RegisterSpec for SgiDatoutcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datoutc::R`](R) reader structure"] +impl crate::Readable for SgiDatoutcSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datoutc::W`](W) writer structure"] +impl crate::Writable for SgiDatoutcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datoutc to value 0"] +impl crate::Resettable for SgiDatoutcSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datoutd.rs b/mcxa276-pac/src/sgi0/sgi_datoutd.rs new file mode 100644 index 000000000..939d50cc1 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_datoutd.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_datoutd` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_datoutd` writer"] +pub type W = crate::W; +#[doc = "Field `datoutd` reader - Output Data register"] +pub type DatoutdR = crate::FieldReader; +#[doc = "Field `datoutd` writer - Output Data register"] +pub type DatoutdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datoutd(&self) -> DatoutdR { + DatoutdR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Output Data register"] + #[inline(always)] + pub fn datoutd(&mut self) -> DatoutdW { + DatoutdW::new(self, 0) + } +} +#[doc = "Output Data register - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDatoutdSpec; +impl crate::RegisterSpec for SgiDatoutdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_datoutd::R`](R) reader structure"] +impl crate::Readable for SgiDatoutdSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_datoutd::W`](W) writer structure"] +impl crate::Writable for SgiDatoutdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_datoutd to value 0"] +impl crate::Resettable for SgiDatoutdSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_dummy_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_dummy_ctrl.rs new file mode 100644 index 000000000..679b59047 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_dummy_ctrl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `sgi_dummy_ctrl` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_dummy_ctrl` writer"] +pub type W = crate::W; +#[doc = "Field `ddctrl` reader - DES dummy control"] +pub type DdctrlR = crate::FieldReader; +#[doc = "Field `ddctrl` writer - DES dummy control"] +pub type DdctrlW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `dmyctl_rsvd2` reader - reserved"] +pub type DmyctlRsvd2R = crate::FieldReader; +#[doc = "Field `adctrl` reader - AES dummy control"] +pub type AdctrlR = crate::FieldReader; +#[doc = "Field `adctrl` writer - AES dummy control"] +pub type AdctrlW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `dmyctl_rsvd1` reader - reserved"] +pub type DmyctlRsvd1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - DES dummy control"] + #[inline(always)] + pub fn ddctrl(&self) -> DdctrlR { + DdctrlR::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:15 - reserved"] + #[inline(always)] + pub fn dmyctl_rsvd2(&self) -> DmyctlRsvd2R { + DmyctlRsvd2R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:25 - AES dummy control"] + #[inline(always)] + pub fn adctrl(&self) -> AdctrlR { + AdctrlR::new(((self.bits >> 16) & 0x03ff) as u16) + } + #[doc = "Bits 26:31 - reserved"] + #[inline(always)] + pub fn dmyctl_rsvd1(&self) -> DmyctlRsvd1R { + DmyctlRsvd1R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:9 - DES dummy control"] + #[inline(always)] + pub fn ddctrl(&mut self) -> DdctrlW { + DdctrlW::new(self, 0) + } + #[doc = "Bits 16:25 - AES dummy control"] + #[inline(always)] + pub fn adctrl(&mut self) -> AdctrlW { + AdctrlW::new(self, 16) + } +} +#[doc = "Configuration of dummy controls\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_dummy_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_dummy_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiDummyCtrlSpec; +impl crate::RegisterSpec for SgiDummyCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_dummy_ctrl::R`](R) reader structure"] +impl crate::Readable for SgiDummyCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_dummy_ctrl::W`](W) writer structure"] +impl crate::Writable for SgiDummyCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_dummy_ctrl to value 0"] +impl crate::Resettable for SgiDummyCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_enable.rs b/mcxa276-pac/src/sgi0/sgi_int_enable.rs new file mode 100644 index 000000000..97089a820 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_int_enable.rs @@ -0,0 +1,42 @@ +#[doc = "Register `sgi_int_enable` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_int_enable` writer"] +pub type W = crate::W; +#[doc = "Field `int_en` reader - Interrupt enable bit"] +pub type IntEnR = crate::BitReader; +#[doc = "Field `int_en` writer - Interrupt enable bit"] +pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `int_ena_rsvd` reader - reserved"] +pub type IntEnaRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Interrupt enable bit"] + #[inline(always)] + pub fn int_en(&self) -> IntEnR { + IntEnR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:31 - reserved"] + #[inline(always)] + pub fn int_ena_rsvd(&self) -> IntEnaRsvdR { + IntEnaRsvdR::new((self.bits >> 1) & 0x7fff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Interrupt enable bit"] + #[inline(always)] + pub fn int_en(&mut self) -> IntEnW { + IntEnW::new(self, 0) + } +} +#[doc = "Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiIntEnableSpec; +impl crate::RegisterSpec for SgiIntEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_int_enable::R`](R) reader structure"] +impl crate::Readable for SgiIntEnableSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_int_enable::W`](W) writer structure"] +impl crate::Writable for SgiIntEnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_int_enable to value 0"] +impl crate::Resettable for SgiIntEnableSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_status.rs b/mcxa276-pac/src/sgi0/sgi_int_status.rs new file mode 100644 index 000000000..e2bc13560 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_int_status.rs @@ -0,0 +1,27 @@ +#[doc = "Register `sgi_int_status` reader"] +pub type R = crate::R; +#[doc = "Field `int_pdone` reader - Interrupt status flag:"] +pub type IntPdoneR = crate::BitReader; +#[doc = "Field `intst_rsvd` reader - reserved"] +pub type IntstRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Interrupt status flag:"] + #[inline(always)] + pub fn int_pdone(&self) -> IntPdoneR { + IntPdoneR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:31 - reserved"] + #[inline(always)] + pub fn intst_rsvd(&self) -> IntstRsvdR { + IntstRsvdR::new((self.bits >> 1) & 0x7fff_ffff) + } +} +#[doc = "Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiIntStatusSpec; +impl crate::RegisterSpec for SgiIntStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_int_status::R`](R) reader structure"] +impl crate::Readable for SgiIntStatusSpec {} +#[doc = "`reset()` method sets sgi_int_status to value 0"] +impl crate::Resettable for SgiIntStatusSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_status_clr.rs b/mcxa276-pac/src/sgi0/sgi_int_status_clr.rs new file mode 100644 index 000000000..d1aa4dc64 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_int_status_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `sgi_int_status_clr` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_int_status_clr` writer"] +pub type W = crate::W; +#[doc = "Field `int_clr` reader - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] +pub type IntClrR = crate::BitReader; +#[doc = "Field `int_clr` writer - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] +pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `int_stsc_rsvd` reader - reserved"] +pub type IntStscRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] + #[inline(always)] + pub fn int_clr(&self) -> IntClrR { + IntClrR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:31 - reserved"] + #[inline(always)] + pub fn int_stsc_rsvd(&self) -> IntStscRsvdR { + IntStscRsvdR::new((self.bits >> 1) & 0x7fff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] + #[inline(always)] + pub fn int_clr(&mut self) -> IntClrW { + IntClrW::new(self, 0) + } +} +#[doc = "Interrupt status clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiIntStatusClrSpec; +impl crate::RegisterSpec for SgiIntStatusClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_int_status_clr::R`](R) reader structure"] +impl crate::Readable for SgiIntStatusClrSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_int_status_clr::W`](W) writer structure"] +impl crate::Writable for SgiIntStatusClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_int_status_clr to value 0"] +impl crate::Resettable for SgiIntStatusClrSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_status_set.rs b/mcxa276-pac/src/sgi0/sgi_int_status_set.rs new file mode 100644 index 000000000..544c8f756 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_int_status_set.rs @@ -0,0 +1,42 @@ +#[doc = "Register `sgi_int_status_set` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_int_status_set` writer"] +pub type W = crate::W; +#[doc = "Field `int_set` reader - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] +pub type IntSetR = crate::BitReader; +#[doc = "Field `int_set` writer - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] +pub type IntSetW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `int_stss_rsvd` reader - reserved"] +pub type IntStssRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] + #[inline(always)] + pub fn int_set(&self) -> IntSetR { + IntSetR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:31 - reserved"] + #[inline(always)] + pub fn int_stss_rsvd(&self) -> IntStssRsvdR { + IntStssRsvdR::new((self.bits >> 1) & 0x7fff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] + #[inline(always)] + pub fn int_set(&mut self) -> IntSetW { + IntSetW::new(self, 0) + } +} +#[doc = "Interrupt status set\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiIntStatusSetSpec; +impl crate::RegisterSpec for SgiIntStatusSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_int_status_set::R`](R) reader structure"] +impl crate::Readable for SgiIntStatusSetSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_int_status_set::W`](W) writer structure"] +impl crate::Writable for SgiIntStatusSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_int_status_set to value 0"] +impl crate::Resettable for SgiIntStatusSetSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0a.rs b/mcxa276-pac/src/sgi0/sgi_key0a.rs new file mode 100644 index 000000000..da82a59b2 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key0a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key0a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key0a` writer"] +pub type W = crate::W; +#[doc = "Field `key0a` reader - Input Key register"] +pub type Key0aR = crate::FieldReader; +#[doc = "Field `key0a` writer - Input Key register"] +pub type Key0aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0a(&self) -> Key0aR { + Key0aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0a(&mut self) -> Key0aW { + Key0aW::new(self, 0) + } +} +#[doc = "Input Key register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey0aSpec; +impl crate::RegisterSpec for SgiKey0aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key0a::R`](R) reader structure"] +impl crate::Readable for SgiKey0aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key0a::W`](W) writer structure"] +impl crate::Writable for SgiKey0aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key0a to value 0"] +impl crate::Resettable for SgiKey0aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0b.rs b/mcxa276-pac/src/sgi0/sgi_key0b.rs new file mode 100644 index 000000000..df7437d73 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key0b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key0b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key0b` writer"] +pub type W = crate::W; +#[doc = "Field `key0b` reader - Input Key register"] +pub type Key0bR = crate::FieldReader; +#[doc = "Field `key0b` writer - Input Key register"] +pub type Key0bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0b(&self) -> Key0bR { + Key0bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0b(&mut self) -> Key0bW { + Key0bW::new(self, 0) + } +} +#[doc = "Input Key register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey0bSpec; +impl crate::RegisterSpec for SgiKey0bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key0b::R`](R) reader structure"] +impl crate::Readable for SgiKey0bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key0b::W`](W) writer structure"] +impl crate::Writable for SgiKey0bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key0b to value 0"] +impl crate::Resettable for SgiKey0bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0c.rs b/mcxa276-pac/src/sgi0/sgi_key0c.rs new file mode 100644 index 000000000..3a72b89e6 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key0c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key0c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key0c` writer"] +pub type W = crate::W; +#[doc = "Field `key0c` reader - Input Key register"] +pub type Key0cR = crate::FieldReader; +#[doc = "Field `key0c` writer - Input Key register"] +pub type Key0cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0c(&self) -> Key0cR { + Key0cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0c(&mut self) -> Key0cW { + Key0cW::new(self, 0) + } +} +#[doc = "Input Key register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey0cSpec; +impl crate::RegisterSpec for SgiKey0cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key0c::R`](R) reader structure"] +impl crate::Readable for SgiKey0cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key0c::W`](W) writer structure"] +impl crate::Writable for SgiKey0cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key0c to value 0"] +impl crate::Resettable for SgiKey0cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0d.rs b/mcxa276-pac/src/sgi0/sgi_key0d.rs new file mode 100644 index 000000000..50b1ccbc2 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key0d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key0d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key0d` writer"] +pub type W = crate::W; +#[doc = "Field `key0d` reader - Input Key register"] +pub type Key0dR = crate::FieldReader; +#[doc = "Field `key0d` writer - Input Key register"] +pub type Key0dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0d(&self) -> Key0dR { + Key0dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key0d(&mut self) -> Key0dW { + Key0dW::new(self, 0) + } +} +#[doc = "Input Key register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey0dSpec; +impl crate::RegisterSpec for SgiKey0dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key0d::R`](R) reader structure"] +impl crate::Readable for SgiKey0dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key0d::W`](W) writer structure"] +impl crate::Writable for SgiKey0dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key0d to value 0"] +impl crate::Resettable for SgiKey0dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1a.rs b/mcxa276-pac/src/sgi0/sgi_key1a.rs new file mode 100644 index 000000000..014975360 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key1a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key1a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key1a` writer"] +pub type W = crate::W; +#[doc = "Field `key1a` reader - Input Key register"] +pub type Key1aR = crate::FieldReader; +#[doc = "Field `key1a` writer - Input Key register"] +pub type Key1aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1a(&self) -> Key1aR { + Key1aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1a(&mut self) -> Key1aW { + Key1aW::new(self, 0) + } +} +#[doc = "Input Key register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey1aSpec; +impl crate::RegisterSpec for SgiKey1aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key1a::R`](R) reader structure"] +impl crate::Readable for SgiKey1aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key1a::W`](W) writer structure"] +impl crate::Writable for SgiKey1aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key1a to value 0"] +impl crate::Resettable for SgiKey1aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1b.rs b/mcxa276-pac/src/sgi0/sgi_key1b.rs new file mode 100644 index 000000000..58e93abde --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key1b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key1b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key1b` writer"] +pub type W = crate::W; +#[doc = "Field `key1b` reader - Input Key register"] +pub type Key1bR = crate::FieldReader; +#[doc = "Field `key1b` writer - Input Key register"] +pub type Key1bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1b(&self) -> Key1bR { + Key1bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1b(&mut self) -> Key1bW { + Key1bW::new(self, 0) + } +} +#[doc = "Input Key register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey1bSpec; +impl crate::RegisterSpec for SgiKey1bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key1b::R`](R) reader structure"] +impl crate::Readable for SgiKey1bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key1b::W`](W) writer structure"] +impl crate::Writable for SgiKey1bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key1b to value 0"] +impl crate::Resettable for SgiKey1bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1c.rs b/mcxa276-pac/src/sgi0/sgi_key1c.rs new file mode 100644 index 000000000..b46ea2e2e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key1c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key1c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key1c` writer"] +pub type W = crate::W; +#[doc = "Field `key1c` reader - Input Key register"] +pub type Key1cR = crate::FieldReader; +#[doc = "Field `key1c` writer - Input Key register"] +pub type Key1cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1c(&self) -> Key1cR { + Key1cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1c(&mut self) -> Key1cW { + Key1cW::new(self, 0) + } +} +#[doc = "Input Key register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey1cSpec; +impl crate::RegisterSpec for SgiKey1cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key1c::R`](R) reader structure"] +impl crate::Readable for SgiKey1cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key1c::W`](W) writer structure"] +impl crate::Writable for SgiKey1cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key1c to value 0"] +impl crate::Resettable for SgiKey1cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1d.rs b/mcxa276-pac/src/sgi0/sgi_key1d.rs new file mode 100644 index 000000000..5a4c638fd --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key1d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key1d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key1d` writer"] +pub type W = crate::W; +#[doc = "Field `key1d` reader - Input Key register"] +pub type Key1dR = crate::FieldReader; +#[doc = "Field `key1d` writer - Input Key register"] +pub type Key1dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1d(&self) -> Key1dR { + Key1dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key1d(&mut self) -> Key1dW { + Key1dW::new(self, 0) + } +} +#[doc = "Input Key register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey1dSpec; +impl crate::RegisterSpec for SgiKey1dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key1d::R`](R) reader structure"] +impl crate::Readable for SgiKey1dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key1d::W`](W) writer structure"] +impl crate::Writable for SgiKey1dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key1d to value 0"] +impl crate::Resettable for SgiKey1dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2a.rs b/mcxa276-pac/src/sgi0/sgi_key2a.rs new file mode 100644 index 000000000..ac8921f13 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key2a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key2a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key2a` writer"] +pub type W = crate::W; +#[doc = "Field `key2a` reader - Input Key register"] +pub type Key2aR = crate::FieldReader; +#[doc = "Field `key2a` writer - Input Key register"] +pub type Key2aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2a(&self) -> Key2aR { + Key2aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2a(&mut self) -> Key2aW { + Key2aW::new(self, 0) + } +} +#[doc = "Input Key register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey2aSpec; +impl crate::RegisterSpec for SgiKey2aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key2a::R`](R) reader structure"] +impl crate::Readable for SgiKey2aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key2a::W`](W) writer structure"] +impl crate::Writable for SgiKey2aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key2a to value 0"] +impl crate::Resettable for SgiKey2aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2b.rs b/mcxa276-pac/src/sgi0/sgi_key2b.rs new file mode 100644 index 000000000..ee35622ad --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key2b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key2b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key2b` writer"] +pub type W = crate::W; +#[doc = "Field `key2b` reader - Input Key register"] +pub type Key2bR = crate::FieldReader; +#[doc = "Field `key2b` writer - Input Key register"] +pub type Key2bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2b(&self) -> Key2bR { + Key2bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2b(&mut self) -> Key2bW { + Key2bW::new(self, 0) + } +} +#[doc = "Input Key register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey2bSpec; +impl crate::RegisterSpec for SgiKey2bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key2b::R`](R) reader structure"] +impl crate::Readable for SgiKey2bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key2b::W`](W) writer structure"] +impl crate::Writable for SgiKey2bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key2b to value 0"] +impl crate::Resettable for SgiKey2bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2c.rs b/mcxa276-pac/src/sgi0/sgi_key2c.rs new file mode 100644 index 000000000..f7cfe25c5 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key2c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key2c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key2c` writer"] +pub type W = crate::W; +#[doc = "Field `key2c` reader - Input Key register"] +pub type Key2cR = crate::FieldReader; +#[doc = "Field `key2c` writer - Input Key register"] +pub type Key2cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2c(&self) -> Key2cR { + Key2cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2c(&mut self) -> Key2cW { + Key2cW::new(self, 0) + } +} +#[doc = "Input Key register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey2cSpec; +impl crate::RegisterSpec for SgiKey2cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key2c::R`](R) reader structure"] +impl crate::Readable for SgiKey2cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key2c::W`](W) writer structure"] +impl crate::Writable for SgiKey2cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key2c to value 0"] +impl crate::Resettable for SgiKey2cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2d.rs b/mcxa276-pac/src/sgi0/sgi_key2d.rs new file mode 100644 index 000000000..ec9603f3e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key2d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key2d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key2d` writer"] +pub type W = crate::W; +#[doc = "Field `key2d` reader - Input Key register"] +pub type Key2dR = crate::FieldReader; +#[doc = "Field `key2d` writer - Input Key register"] +pub type Key2dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2d(&self) -> Key2dR { + Key2dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key2d(&mut self) -> Key2dW { + Key2dW::new(self, 0) + } +} +#[doc = "Input Key register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey2dSpec; +impl crate::RegisterSpec for SgiKey2dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key2d::R`](R) reader structure"] +impl crate::Readable for SgiKey2dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key2d::W`](W) writer structure"] +impl crate::Writable for SgiKey2dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key2d to value 0"] +impl crate::Resettable for SgiKey2dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3a.rs b/mcxa276-pac/src/sgi0/sgi_key3a.rs new file mode 100644 index 000000000..a6998fbd9 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key3a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key3a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key3a` writer"] +pub type W = crate::W; +#[doc = "Field `key3a` reader - Input Key register"] +pub type Key3aR = crate::FieldReader; +#[doc = "Field `key3a` writer - Input Key register"] +pub type Key3aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3a(&self) -> Key3aR { + Key3aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3a(&mut self) -> Key3aW { + Key3aW::new(self, 0) + } +} +#[doc = "Input Key register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey3aSpec; +impl crate::RegisterSpec for SgiKey3aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key3a::R`](R) reader structure"] +impl crate::Readable for SgiKey3aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key3a::W`](W) writer structure"] +impl crate::Writable for SgiKey3aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key3a to value 0"] +impl crate::Resettable for SgiKey3aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3b.rs b/mcxa276-pac/src/sgi0/sgi_key3b.rs new file mode 100644 index 000000000..335799dfd --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key3b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key3b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key3b` writer"] +pub type W = crate::W; +#[doc = "Field `key3b` reader - Input Key register"] +pub type Key3bR = crate::FieldReader; +#[doc = "Field `key3b` writer - Input Key register"] +pub type Key3bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3b(&self) -> Key3bR { + Key3bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3b(&mut self) -> Key3bW { + Key3bW::new(self, 0) + } +} +#[doc = "Input Key register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey3bSpec; +impl crate::RegisterSpec for SgiKey3bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key3b::R`](R) reader structure"] +impl crate::Readable for SgiKey3bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key3b::W`](W) writer structure"] +impl crate::Writable for SgiKey3bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key3b to value 0"] +impl crate::Resettable for SgiKey3bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3c.rs b/mcxa276-pac/src/sgi0/sgi_key3c.rs new file mode 100644 index 000000000..d2e8f9b4a --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key3c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key3c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key3c` writer"] +pub type W = crate::W; +#[doc = "Field `key3c` reader - Input Key register"] +pub type Key3cR = crate::FieldReader; +#[doc = "Field `key3c` writer - Input Key register"] +pub type Key3cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3c(&self) -> Key3cR { + Key3cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3c(&mut self) -> Key3cW { + Key3cW::new(self, 0) + } +} +#[doc = "Input Key register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey3cSpec; +impl crate::RegisterSpec for SgiKey3cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key3c::R`](R) reader structure"] +impl crate::Readable for SgiKey3cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key3c::W`](W) writer structure"] +impl crate::Writable for SgiKey3cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key3c to value 0"] +impl crate::Resettable for SgiKey3cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3d.rs b/mcxa276-pac/src/sgi0/sgi_key3d.rs new file mode 100644 index 000000000..2753bb18a --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key3d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key3d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key3d` writer"] +pub type W = crate::W; +#[doc = "Field `key3d` reader - Input Key register"] +pub type Key3dR = crate::FieldReader; +#[doc = "Field `key3d` writer - Input Key register"] +pub type Key3dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3d(&self) -> Key3dR { + Key3dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key3d(&mut self) -> Key3dW { + Key3dW::new(self, 0) + } +} +#[doc = "Input Key register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey3dSpec; +impl crate::RegisterSpec for SgiKey3dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key3d::R`](R) reader structure"] +impl crate::Readable for SgiKey3dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key3d::W`](W) writer structure"] +impl crate::Writable for SgiKey3dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key3d to value 0"] +impl crate::Resettable for SgiKey3dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4a.rs b/mcxa276-pac/src/sgi0/sgi_key4a.rs new file mode 100644 index 000000000..071fc45ec --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key4a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key4a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key4a` writer"] +pub type W = crate::W; +#[doc = "Field `key4a` reader - Input Key register"] +pub type Key4aR = crate::FieldReader; +#[doc = "Field `key4a` writer - Input Key register"] +pub type Key4aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4a(&self) -> Key4aR { + Key4aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4a(&mut self) -> Key4aW { + Key4aW::new(self, 0) + } +} +#[doc = "Input Key register 4 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey4aSpec; +impl crate::RegisterSpec for SgiKey4aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key4a::R`](R) reader structure"] +impl crate::Readable for SgiKey4aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key4a::W`](W) writer structure"] +impl crate::Writable for SgiKey4aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key4a to value 0"] +impl crate::Resettable for SgiKey4aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4b.rs b/mcxa276-pac/src/sgi0/sgi_key4b.rs new file mode 100644 index 000000000..39b9419a7 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key4b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key4b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key4b` writer"] +pub type W = crate::W; +#[doc = "Field `key4b` reader - Input Key register"] +pub type Key4bR = crate::FieldReader; +#[doc = "Field `key4b` writer - Input Key register"] +pub type Key4bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4b(&self) -> Key4bR { + Key4bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4b(&mut self) -> Key4bW { + Key4bW::new(self, 0) + } +} +#[doc = "Input Key register 4 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey4bSpec; +impl crate::RegisterSpec for SgiKey4bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key4b::R`](R) reader structure"] +impl crate::Readable for SgiKey4bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key4b::W`](W) writer structure"] +impl crate::Writable for SgiKey4bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key4b to value 0"] +impl crate::Resettable for SgiKey4bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4c.rs b/mcxa276-pac/src/sgi0/sgi_key4c.rs new file mode 100644 index 000000000..b9c32f600 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key4c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key4c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key4c` writer"] +pub type W = crate::W; +#[doc = "Field `key4c` reader - Input Key register"] +pub type Key4cR = crate::FieldReader; +#[doc = "Field `key4c` writer - Input Key register"] +pub type Key4cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4c(&self) -> Key4cR { + Key4cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4c(&mut self) -> Key4cW { + Key4cW::new(self, 0) + } +} +#[doc = "Input Key register 4 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey4cSpec; +impl crate::RegisterSpec for SgiKey4cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key4c::R`](R) reader structure"] +impl crate::Readable for SgiKey4cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key4c::W`](W) writer structure"] +impl crate::Writable for SgiKey4cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key4c to value 0"] +impl crate::Resettable for SgiKey4cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4d.rs b/mcxa276-pac/src/sgi0/sgi_key4d.rs new file mode 100644 index 000000000..dd0c5debc --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key4d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key4d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key4d` writer"] +pub type W = crate::W; +#[doc = "Field `key4d` reader - Input Key register"] +pub type Key4dR = crate::FieldReader; +#[doc = "Field `key4d` writer - Input Key register"] +pub type Key4dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4d(&self) -> Key4dR { + Key4dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key4d(&mut self) -> Key4dW { + Key4dW::new(self, 0) + } +} +#[doc = "Input Key register 4 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey4dSpec; +impl crate::RegisterSpec for SgiKey4dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key4d::R`](R) reader structure"] +impl crate::Readable for SgiKey4dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key4d::W`](W) writer structure"] +impl crate::Writable for SgiKey4dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key4d to value 0"] +impl crate::Resettable for SgiKey4dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5a.rs b/mcxa276-pac/src/sgi0/sgi_key5a.rs new file mode 100644 index 000000000..103f7f5f4 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key5a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key5a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key5a` writer"] +pub type W = crate::W; +#[doc = "Field `key5a` reader - Input Key register"] +pub type Key5aR = crate::FieldReader; +#[doc = "Field `key5a` writer - Input Key register"] +pub type Key5aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5a(&self) -> Key5aR { + Key5aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5a(&mut self) -> Key5aW { + Key5aW::new(self, 0) + } +} +#[doc = "Input Key register 5 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey5aSpec; +impl crate::RegisterSpec for SgiKey5aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key5a::R`](R) reader structure"] +impl crate::Readable for SgiKey5aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key5a::W`](W) writer structure"] +impl crate::Writable for SgiKey5aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key5a to value 0"] +impl crate::Resettable for SgiKey5aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5b.rs b/mcxa276-pac/src/sgi0/sgi_key5b.rs new file mode 100644 index 000000000..8575c3a76 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key5b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key5b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key5b` writer"] +pub type W = crate::W; +#[doc = "Field `key5b` reader - Input Key register"] +pub type Key5bR = crate::FieldReader; +#[doc = "Field `key5b` writer - Input Key register"] +pub type Key5bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5b(&self) -> Key5bR { + Key5bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5b(&mut self) -> Key5bW { + Key5bW::new(self, 0) + } +} +#[doc = "Input Key register 5 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey5bSpec; +impl crate::RegisterSpec for SgiKey5bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key5b::R`](R) reader structure"] +impl crate::Readable for SgiKey5bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key5b::W`](W) writer structure"] +impl crate::Writable for SgiKey5bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key5b to value 0"] +impl crate::Resettable for SgiKey5bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5c.rs b/mcxa276-pac/src/sgi0/sgi_key5c.rs new file mode 100644 index 000000000..3d6ba076f --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key5c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key5c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key5c` writer"] +pub type W = crate::W; +#[doc = "Field `key5c` reader - Input Key register"] +pub type Key5cR = crate::FieldReader; +#[doc = "Field `key5c` writer - Input Key register"] +pub type Key5cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5c(&self) -> Key5cR { + Key5cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5c(&mut self) -> Key5cW { + Key5cW::new(self, 0) + } +} +#[doc = "Input Key register 5 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey5cSpec; +impl crate::RegisterSpec for SgiKey5cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key5c::R`](R) reader structure"] +impl crate::Readable for SgiKey5cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key5c::W`](W) writer structure"] +impl crate::Writable for SgiKey5cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key5c to value 0"] +impl crate::Resettable for SgiKey5cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5d.rs b/mcxa276-pac/src/sgi0/sgi_key5d.rs new file mode 100644 index 000000000..1115a5c8d --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key5d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key5d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key5d` writer"] +pub type W = crate::W; +#[doc = "Field `key5d` reader - Input Key register"] +pub type Key5dR = crate::FieldReader; +#[doc = "Field `key5d` writer - Input Key register"] +pub type Key5dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5d(&self) -> Key5dR { + Key5dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key5d(&mut self) -> Key5dW { + Key5dW::new(self, 0) + } +} +#[doc = "Input Key register 5 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey5dSpec; +impl crate::RegisterSpec for SgiKey5dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key5d::R`](R) reader structure"] +impl crate::Readable for SgiKey5dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key5d::W`](W) writer structure"] +impl crate::Writable for SgiKey5dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key5d to value 0"] +impl crate::Resettable for SgiKey5dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6a.rs b/mcxa276-pac/src/sgi0/sgi_key6a.rs new file mode 100644 index 000000000..1f42bd877 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key6a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key6a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key6a` writer"] +pub type W = crate::W; +#[doc = "Field `key6a` reader - Input Key register"] +pub type Key6aR = crate::FieldReader; +#[doc = "Field `key6a` writer - Input Key register"] +pub type Key6aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6a(&self) -> Key6aR { + Key6aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6a(&mut self) -> Key6aW { + Key6aW::new(self, 0) + } +} +#[doc = "Input Key register 6 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey6aSpec; +impl crate::RegisterSpec for SgiKey6aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key6a::R`](R) reader structure"] +impl crate::Readable for SgiKey6aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key6a::W`](W) writer structure"] +impl crate::Writable for SgiKey6aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key6a to value 0"] +impl crate::Resettable for SgiKey6aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6b.rs b/mcxa276-pac/src/sgi0/sgi_key6b.rs new file mode 100644 index 000000000..f24ae3244 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key6b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key6b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key6b` writer"] +pub type W = crate::W; +#[doc = "Field `key6b` reader - Input Key register"] +pub type Key6bR = crate::FieldReader; +#[doc = "Field `key6b` writer - Input Key register"] +pub type Key6bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6b(&self) -> Key6bR { + Key6bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6b(&mut self) -> Key6bW { + Key6bW::new(self, 0) + } +} +#[doc = "Input Key register 6 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey6bSpec; +impl crate::RegisterSpec for SgiKey6bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key6b::R`](R) reader structure"] +impl crate::Readable for SgiKey6bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key6b::W`](W) writer structure"] +impl crate::Writable for SgiKey6bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key6b to value 0"] +impl crate::Resettable for SgiKey6bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6c.rs b/mcxa276-pac/src/sgi0/sgi_key6c.rs new file mode 100644 index 000000000..1786bd41e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key6c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key6c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key6c` writer"] +pub type W = crate::W; +#[doc = "Field `key6c` reader - Input Key register"] +pub type Key6cR = crate::FieldReader; +#[doc = "Field `key6c` writer - Input Key register"] +pub type Key6cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6c(&self) -> Key6cR { + Key6cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6c(&mut self) -> Key6cW { + Key6cW::new(self, 0) + } +} +#[doc = "Input Key register 6 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey6cSpec; +impl crate::RegisterSpec for SgiKey6cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key6c::R`](R) reader structure"] +impl crate::Readable for SgiKey6cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key6c::W`](W) writer structure"] +impl crate::Writable for SgiKey6cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key6c to value 0"] +impl crate::Resettable for SgiKey6cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6d.rs b/mcxa276-pac/src/sgi0/sgi_key6d.rs new file mode 100644 index 000000000..023340890 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key6d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key6d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key6d` writer"] +pub type W = crate::W; +#[doc = "Field `key6d` reader - Input Key register"] +pub type Key6dR = crate::FieldReader; +#[doc = "Field `key6d` writer - Input Key register"] +pub type Key6dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6d(&self) -> Key6dR { + Key6dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key6d(&mut self) -> Key6dW { + Key6dW::new(self, 0) + } +} +#[doc = "Input Key register 6 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey6dSpec; +impl crate::RegisterSpec for SgiKey6dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key6d::R`](R) reader structure"] +impl crate::Readable for SgiKey6dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key6d::W`](W) writer structure"] +impl crate::Writable for SgiKey6dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key6d to value 0"] +impl crate::Resettable for SgiKey6dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7a.rs b/mcxa276-pac/src/sgi0/sgi_key7a.rs new file mode 100644 index 000000000..1458ede0c --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key7a.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key7a` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key7a` writer"] +pub type W = crate::W; +#[doc = "Field `key7a` reader - Input Key register"] +pub type Key7aR = crate::FieldReader; +#[doc = "Field `key7a` writer - Input Key register"] +pub type Key7aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7a(&self) -> Key7aR { + Key7aR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7a(&mut self) -> Key7aW { + Key7aW::new(self, 0) + } +} +#[doc = "Input Key register 7 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey7aSpec; +impl crate::RegisterSpec for SgiKey7aSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key7a::R`](R) reader structure"] +impl crate::Readable for SgiKey7aSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key7a::W`](W) writer structure"] +impl crate::Writable for SgiKey7aSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key7a to value 0"] +impl crate::Resettable for SgiKey7aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7b.rs b/mcxa276-pac/src/sgi0/sgi_key7b.rs new file mode 100644 index 000000000..d56cc4160 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key7b.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key7b` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key7b` writer"] +pub type W = crate::W; +#[doc = "Field `key7b` reader - Input Key register"] +pub type Key7bR = crate::FieldReader; +#[doc = "Field `key7b` writer - Input Key register"] +pub type Key7bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7b(&self) -> Key7bR { + Key7bR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7b(&mut self) -> Key7bW { + Key7bW::new(self, 0) + } +} +#[doc = "Input Key register 7 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey7bSpec; +impl crate::RegisterSpec for SgiKey7bSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key7b::R`](R) reader structure"] +impl crate::Readable for SgiKey7bSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key7b::W`](W) writer structure"] +impl crate::Writable for SgiKey7bSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key7b to value 0"] +impl crate::Resettable for SgiKey7bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7c.rs b/mcxa276-pac/src/sgi0/sgi_key7c.rs new file mode 100644 index 000000000..293448a85 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key7c.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key7c` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key7c` writer"] +pub type W = crate::W; +#[doc = "Field `key7c` reader - Input Key register"] +pub type Key7cR = crate::FieldReader; +#[doc = "Field `key7c` writer - Input Key register"] +pub type Key7cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7c(&self) -> Key7cR { + Key7cR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7c(&mut self) -> Key7cW { + Key7cW::new(self, 0) + } +} +#[doc = "Input Key register 7 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey7cSpec; +impl crate::RegisterSpec for SgiKey7cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key7c::R`](R) reader structure"] +impl crate::Readable for SgiKey7cSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key7c::W`](W) writer structure"] +impl crate::Writable for SgiKey7cSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key7c to value 0"] +impl crate::Resettable for SgiKey7cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7d.rs b/mcxa276-pac/src/sgi0/sgi_key7d.rs new file mode 100644 index 000000000..8f69b3a10 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key7d.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key7d` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key7d` writer"] +pub type W = crate::W; +#[doc = "Field `key7d` reader - Input Key register"] +pub type Key7dR = crate::FieldReader; +#[doc = "Field `key7d` writer - Input Key register"] +pub type Key7dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7d(&self) -> Key7dR { + Key7dR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Input Key register"] + #[inline(always)] + pub fn key7d(&mut self) -> Key7dW { + Key7dW::new(self, 0) + } +} +#[doc = "Input Key register 7 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKey7dSpec; +impl crate::RegisterSpec for SgiKey7dSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key7d::R`](R) reader structure"] +impl crate::Readable for SgiKey7dSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key7d::W`](W) writer structure"] +impl crate::Writable for SgiKey7dSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key7d to value 0"] +impl crate::Resettable for SgiKey7dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_key_ctrl.rs new file mode 100644 index 000000000..b8372c41e --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key_ctrl.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_key_ctrl` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_key_ctrl` writer"] +pub type W = crate::W; +#[doc = "Field `key_wo` reader - SGI Key control register(1-bit per KEY SFR)"] +pub type KeyWoR = crate::FieldReader; +#[doc = "Field `key_wo` writer - SGI Key control register(1-bit per KEY SFR)"] +pub type KeyWoW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - SGI Key control register(1-bit per KEY SFR)"] + #[inline(always)] + pub fn key_wo(&self) -> KeyWoR { + KeyWoR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - SGI Key control register(1-bit per KEY SFR)"] + #[inline(always)] + pub fn key_wo(&mut self) -> KeyWoW { + KeyWoW::new(self, 0) + } +} +#[doc = "SGI Key Control SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKeyCtrlSpec; +impl crate::RegisterSpec for SgiKeyCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key_ctrl::R`](R) reader structure"] +impl crate::Readable for SgiKeyCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_key_ctrl::W`](W) writer structure"] +impl crate::Writable for SgiKeyCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_key_ctrl to value 0"] +impl crate::Resettable for SgiKeyCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key_wrap.rs b/mcxa276-pac/src/sgi0/sgi_key_wrap.rs new file mode 100644 index 000000000..f6504b19b --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_key_wrap.rs @@ -0,0 +1,20 @@ +#[doc = "Register `sgi_key_wrap` reader"] +pub type R = crate::R; +#[doc = "Field `kw_data` reader - Field contains wrapped key, auto-updated by HW for each word"] +pub type KwDataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Field contains wrapped key, auto-updated by HW for each word"] + #[inline(always)] + pub fn kw_data(&self) -> KwDataR { + KwDataR::new(self.bits) + } +} +#[doc = "Wrapped key read SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_wrap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKeyWrapSpec; +impl crate::RegisterSpec for SgiKeyWrapSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_key_wrap::R`](R) reader structure"] +impl crate::Readable for SgiKeyWrapSpec {} +#[doc = "`reset()` method sets sgi_key_wrap to value 0"] +impl crate::Resettable for SgiKeyWrapSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_keychk.rs b/mcxa276-pac/src/sgi0/sgi_keychk.rs new file mode 100644 index 000000000..6ca36ddc2 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_keychk.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_keychk` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_keychk` writer"] +pub type W = crate::W; +#[doc = "Field `keychksum` reader - Key checksum (32-bit)."] +pub type KeychksumR = crate::FieldReader; +#[doc = "Field `keychksum` writer - Key checksum (32-bit)."] +pub type KeychksumW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Key checksum (32-bit)."] + #[inline(always)] + pub fn keychksum(&self) -> KeychksumR { + KeychksumR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Key checksum (32-bit)."] + #[inline(always)] + pub fn keychksum(&mut self) -> KeychksumW { + KeychksumW::new(self, 0) + } +} +#[doc = "Key checksum register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_keychk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_keychk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiKeychkSpec; +impl crate::RegisterSpec for SgiKeychkSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_keychk::R`](R) reader structure"] +impl crate::Readable for SgiKeychkSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_keychk::W`](W) writer structure"] +impl crate::Writable for SgiKeychkSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_keychk to value 0"] +impl crate::Resettable for SgiKeychkSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_module_id.rs b/mcxa276-pac/src/sgi0/sgi_module_id.rs new file mode 100644 index 000000000..e2e006a41 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_module_id.rs @@ -0,0 +1,20 @@ +#[doc = "Register `sgi_module_id` reader"] +pub type R = crate::R; +#[doc = "Field `placeholder` reader - Module ID"] +pub type PlaceholderR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Module ID"] + #[inline(always)] + pub fn placeholder(&self) -> PlaceholderR { + PlaceholderR::new(self.bits) + } +} +#[doc = "Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_module_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiModuleIdSpec; +impl crate::RegisterSpec for SgiModuleIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_module_id::R`](R) reader structure"] +impl crate::Readable for SgiModuleIdSpec {} +#[doc = "`reset()` method sets sgi_module_id to value 0"] +impl crate::Resettable for SgiModuleIdSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs b/mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs new file mode 100644 index 000000000..e5842648a --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_prng_sw_seed` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_prng_sw_seed` writer"] +pub type W = crate::W; +#[doc = "Field `seed` reader - 32-bits SEED field. A write to the SEED field"] +pub type SeedR = crate::FieldReader; +#[doc = "Field `seed` writer - 32-bits SEED field. A write to the SEED field"] +pub type SeedW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - 32-bits SEED field. A write to the SEED field"] + #[inline(always)] + pub fn seed(&self) -> SeedR { + SeedR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - 32-bits SEED field. A write to the SEED field"] + #[inline(always)] + pub fn seed(&mut self) -> SeedW { + SeedW::new(self, 0) + } +} +#[doc = "SGI internal PRNG SW seeding register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_prng_sw_seed::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_prng_sw_seed::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiPrngSwSeedSpec; +impl crate::RegisterSpec for SgiPrngSwSeedSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_prng_sw_seed::R`](R) reader structure"] +impl crate::Readable for SgiPrngSwSeedSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_prng_sw_seed::W`](W) writer structure"] +impl crate::Writable for SgiPrngSwSeedSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_prng_sw_seed to value 0"] +impl crate::Resettable for SgiPrngSwSeedSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs b/mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs new file mode 100644 index 000000000..d93cfcdaa --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_sfr_sw_mask` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_sfr_sw_mask` writer"] +pub type W = crate::W; +#[doc = "Field `sfr_mask_val` reader - Seed/mask used for sw level masking"] +pub type SfrMaskValR = crate::FieldReader; +#[doc = "Field `sfr_mask_val` writer - Seed/mask used for sw level masking"] +pub type SfrMaskValW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] + #[inline(always)] + pub fn sfr_mask_val(&self) -> SfrMaskValR { + SfrMaskValR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] + #[inline(always)] + pub fn sfr_mask_val(&mut self) -> SfrMaskValW { + SfrMaskValW::new(self, 0) + } +} +#[doc = "Sofware Assisted Masking register .\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfr_sw_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfr_sw_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiSfrSwMaskSpec; +impl crate::RegisterSpec for SgiSfrSwMaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_sfr_sw_mask::R`](R) reader structure"] +impl crate::Readable for SgiSfrSwMaskSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_sfr_sw_mask::W`](W) writer structure"] +impl crate::Writable for SgiSfrSwMaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_sfr_sw_mask to value 0"] +impl crate::Resettable for SgiSfrSwMaskSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_sfrseed.rs b/mcxa276-pac/src/sgi0/sgi_sfrseed.rs new file mode 100644 index 000000000..a478d595c --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_sfrseed.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_sfrseed` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_sfrseed` writer"] +pub type W = crate::W; +#[doc = "Field `sfrseed` reader - Seed/mask used for sw level masking"] +pub type SfrseedR = crate::FieldReader; +#[doc = "Field `sfrseed` writer - Seed/mask used for sw level masking"] +pub type SfrseedW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] + #[inline(always)] + pub fn sfrseed(&self) -> SfrseedR { + SfrseedR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] + #[inline(always)] + pub fn sfrseed(&mut self) -> SfrseedW { + SfrseedW::new(self, 0) + } +} +#[doc = "SFRSEED register for SFRMASK feature.\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfrseed::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfrseed::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiSfrseedSpec; +impl crate::RegisterSpec for SgiSfrseedSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_sfrseed::R`](R) reader structure"] +impl crate::Readable for SgiSfrseedSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_sfrseed::W`](W) writer structure"] +impl crate::Writable for SgiSfrseedSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_sfrseed to value 0"] +impl crate::Resettable for SgiSfrseedSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs new file mode 100644 index 000000000..33f690c7c --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs @@ -0,0 +1,149 @@ +#[doc = "Register `sgi_sha2_ctrl` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_sha2_ctrl` writer"] +pub type W = crate::W; +#[doc = "Field `sha2_en` reader - SHA enable"] +pub type Sha2EnR = crate::BitReader; +#[doc = "Field `sha2_en` writer - SHA enable"] +pub type Sha2EnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `sha2_mode` reader - SHA mode normal or automatic"] +pub type Sha2ModeR = crate::BitReader; +#[doc = "Field `sha2_mode` writer - SHA mode normal or automatic"] +pub type Sha2ModeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `sha2_size` reader - SHA size 0=224;1=256;2=384;3=512"] +pub type Sha2SizeR = crate::FieldReader; +#[doc = "Field `sha2_size` writer - SHA size 0=224;1=256;2=384;3=512"] +pub type Sha2SizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `sha2_low_lim` reader - SHA FIFO low limit"] +pub type Sha2LowLimR = crate::FieldReader; +#[doc = "Field `sha2_low_lim` writer - SHA FIFO low limit"] +pub type Sha2LowLimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `sha2_high_lim` reader - SHA FIFO high limit"] +pub type Sha2HighLimR = crate::FieldReader; +#[doc = "Field `sha2_high_lim` writer - SHA FIFO high limit"] +pub type Sha2HighLimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `sha2_count_en` reader - SHA Calculation counter enable"] +pub type Sha2CountEnR = crate::BitReader; +#[doc = "Field `sha2_count_en` writer - SHA Calculation counter enable"] +pub type Sha2CountEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `hash_reload` reader - SHA HASH reload"] +pub type HashReloadR = crate::BitReader; +#[doc = "Field `hash_reload` writer - SHA HASH reload"] +pub type HashReloadW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `sha2_stop` writer - STOP SHA AUTO mode"] +pub type Sha2StopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `no_auto_init` reader - SHA no automatic HASH initialisation"] +pub type NoAutoInitR = crate::BitReader; +#[doc = "Field `no_auto_init` writer - SHA no automatic HASH initialisation"] +pub type NoAutoInitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `sha2ctl_rsvd` reader - reserved"] +pub type Sha2ctlRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - SHA enable"] + #[inline(always)] + pub fn sha2_en(&self) -> Sha2EnR { + Sha2EnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SHA mode normal or automatic"] + #[inline(always)] + pub fn sha2_mode(&self) -> Sha2ModeR { + Sha2ModeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - SHA size 0=224;1=256;2=384;3=512"] + #[inline(always)] + pub fn sha2_size(&self) -> Sha2SizeR { + Sha2SizeR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:7 - SHA FIFO low limit"] + #[inline(always)] + pub fn sha2_low_lim(&self) -> Sha2LowLimR { + Sha2LowLimR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - SHA FIFO high limit"] + #[inline(always)] + pub fn sha2_high_lim(&self) -> Sha2HighLimR { + Sha2HighLimR::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - SHA Calculation counter enable"] + #[inline(always)] + pub fn sha2_count_en(&self) -> Sha2CountEnR { + Sha2CountEnR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SHA HASH reload"] + #[inline(always)] + pub fn hash_reload(&self) -> HashReloadR { + HashReloadR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - SHA no automatic HASH initialisation"] + #[inline(always)] + pub fn no_auto_init(&self) -> NoAutoInitR { + NoAutoInitR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - reserved"] + #[inline(always)] + pub fn sha2ctl_rsvd(&self) -> Sha2ctlRsvdR { + Sha2ctlRsvdR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - SHA enable"] + #[inline(always)] + pub fn sha2_en(&mut self) -> Sha2EnW { + Sha2EnW::new(self, 0) + } + #[doc = "Bit 1 - SHA mode normal or automatic"] + #[inline(always)] + pub fn sha2_mode(&mut self) -> Sha2ModeW { + Sha2ModeW::new(self, 1) + } + #[doc = "Bits 2:3 - SHA size 0=224;1=256;2=384;3=512"] + #[inline(always)] + pub fn sha2_size(&mut self) -> Sha2SizeW { + Sha2SizeW::new(self, 2) + } + #[doc = "Bits 4:7 - SHA FIFO low limit"] + #[inline(always)] + pub fn sha2_low_lim(&mut self) -> Sha2LowLimW { + Sha2LowLimW::new(self, 4) + } + #[doc = "Bits 8:11 - SHA FIFO high limit"] + #[inline(always)] + pub fn sha2_high_lim(&mut self) -> Sha2HighLimW { + Sha2HighLimW::new(self, 8) + } + #[doc = "Bit 12 - SHA Calculation counter enable"] + #[inline(always)] + pub fn sha2_count_en(&mut self) -> Sha2CountEnW { + Sha2CountEnW::new(self, 12) + } + #[doc = "Bit 13 - SHA HASH reload"] + #[inline(always)] + pub fn hash_reload(&mut self) -> HashReloadW { + HashReloadW::new(self, 13) + } + #[doc = "Bit 14 - STOP SHA AUTO mode"] + #[inline(always)] + pub fn sha2_stop(&mut self) -> Sha2StopW { + Sha2StopW::new(self, 14) + } + #[doc = "Bit 15 - SHA no automatic HASH initialisation"] + #[inline(always)] + pub fn no_auto_init(&mut self) -> NoAutoInitW { + NoAutoInitW::new(self, 15) + } +} +#[doc = "SHA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiSha2CtrlSpec; +impl crate::RegisterSpec for SgiSha2CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_sha2_ctrl::R`](R) reader structure"] +impl crate::Readable for SgiSha2CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_sha2_ctrl::W`](W) writer structure"] +impl crate::Writable for SgiSha2CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_sha2_ctrl to value 0x0f00"] +impl crate::Resettable for SgiSha2CtrlSpec { + const RESET_VALUE: u32 = 0x0f00; +} diff --git a/mcxa276-pac/src/sgi0/sgi_sha_fifo.rs b/mcxa276-pac/src/sgi0/sgi_sha_fifo.rs new file mode 100644 index 000000000..0606e6fd8 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_sha_fifo.rs @@ -0,0 +1,35 @@ +#[doc = "Register `sgi_sha_fifo` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_sha_fifo` writer"] +pub type W = crate::W; +#[doc = "Field `fifo` reader - SHA FIFO register"] +pub type FifoR = crate::FieldReader; +#[doc = "Field `fifo` writer - SHA FIFO register"] +pub type FifoW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - SHA FIFO register"] + #[inline(always)] + pub fn fifo(&self) -> FifoR { + FifoR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - SHA FIFO register"] + #[inline(always)] + pub fn fifo(&mut self) -> FifoW { + FifoW::new(self, 0) + } +} +#[doc = "SHA FIFO lower-bank low\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha_fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha_fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiShaFifoSpec; +impl crate::RegisterSpec for SgiShaFifoSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_sha_fifo::R`](R) reader structure"] +impl crate::Readable for SgiShaFifoSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_sha_fifo::W`](W) writer structure"] +impl crate::Writable for SgiShaFifoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_sha_fifo to value 0"] +impl crate::Resettable for SgiShaFifoSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_status.rs b/mcxa276-pac/src/sgi0/sgi_status.rs new file mode 100644 index 000000000..86f20ce49 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_status.rs @@ -0,0 +1,203 @@ +#[doc = "Register `sgi_status` reader"] +pub type R = crate::R; +#[doc = "Register `sgi_status` writer"] +pub type W = crate::W; +#[doc = "Field `busy` reader - Combined busy flag that remains high"] +pub type BusyR = crate::BitReader; +#[doc = "Field `oflow` reader - Overflow in INCR operation flag"] +pub type OflowR = crate::BitReader; +#[doc = "Field `oflow` writer - Overflow in INCR operation flag"] +pub type OflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `prng_rdy` reader - prng is ready after boot-up-phase"] +pub type PrngRdyR = crate::BitReader; +#[doc = "Error detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Error { + #[doc = "0: ERROR(all values other than 0x05 indicate ERROR)"] + Error = 0, + #[doc = "5: NO_ERROR"] + NoError = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Error) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Error { + type Ux = u8; +} +impl crate::IsEnum for Error {} +#[doc = "Field `error` reader - Error detected"] +pub type ErrorR = crate::FieldReader; +impl ErrorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Error::Error), + 5 => Some(Error::NoError), + _ => None, + } + } + #[doc = "ERROR(all values other than 0x05 indicate ERROR)"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Error::Error + } + #[doc = "NO_ERROR"] + #[inline(always)] + pub fn is_no_error(&self) -> bool { + *self == Error::NoError + } +} +#[doc = "Field `error` writer - Error detected"] +pub type ErrorW<'a, REG> = crate::FieldWriter<'a, REG, 3, Error>; +impl<'a, REG> ErrorW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "ERROR(all values other than 0x05 indicate ERROR)"] + #[inline(always)] + pub fn error(self) -> &'a mut crate::W { + self.variant(Error::Error) + } + #[doc = "NO_ERROR"] + #[inline(always)] + pub fn no_error(self) -> &'a mut crate::W { + self.variant(Error::NoError) + } +} +#[doc = "Field `sha2_busy` reader - SHA2 is busy"] +pub type Sha2BusyR = crate::BitReader; +#[doc = "Field `irq` reader - interrupt detected"] +pub type IrqR = crate::BitReader; +#[doc = "Field `irq` writer - interrupt detected"] +pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `sha_fifo_full` reader - SHA FIFO is full(operates in SHA AUTO mode)"] +pub type ShaFifoFullR = crate::BitReader; +#[doc = "Field `sha_fifo_level` reader - SHA FIFO level"] +pub type ShaFifoLevelR = crate::FieldReader; +#[doc = "Field `sha_error` reader - SHA ERROR"] +pub type ShaErrorR = crate::BitReader; +#[doc = "Field `key_read_err` reader - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] +pub type KeyReadErrR = crate::BitReader; +#[doc = "Field `key_read_err` writer - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] +pub type KeyReadErrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `key_unwrap_err` reader - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] +pub type KeyUnwrapErrR = crate::BitReader; +#[doc = "Field `key_unwrap_err` writer - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] +pub type KeyUnwrapErrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `status_rsvd3` reader - reserved"] +pub type StatusRsvd3R = crate::BitReader; +#[doc = "Field `status_rsvd` reader - reserved"] +pub type StatusRsvdR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Combined busy flag that remains high"] + #[inline(always)] + pub fn busy(&self) -> BusyR { + BusyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Overflow in INCR operation flag"] + #[inline(always)] + pub fn oflow(&self) -> OflowR { + OflowR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - prng is ready after boot-up-phase"] + #[inline(always)] + pub fn prng_rdy(&self) -> PrngRdyR { + PrngRdyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:5 - Error detected"] + #[inline(always)] + pub fn error(&self) -> ErrorR { + ErrorR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - SHA2 is busy"] + #[inline(always)] + pub fn sha2_busy(&self) -> Sha2BusyR { + Sha2BusyR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - interrupt detected"] + #[inline(always)] + pub fn irq(&self) -> IrqR { + IrqR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - SHA FIFO is full(operates in SHA AUTO mode)"] + #[inline(always)] + pub fn sha_fifo_full(&self) -> ShaFifoFullR { + ShaFifoFullR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:14 - SHA FIFO level"] + #[inline(always)] + pub fn sha_fifo_level(&self) -> ShaFifoLevelR { + ShaFifoLevelR::new(((self.bits >> 9) & 0x3f) as u8) + } + #[doc = "Bit 15 - SHA ERROR"] + #[inline(always)] + pub fn sha_error(&self) -> ShaErrorR { + ShaErrorR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] + #[inline(always)] + pub fn key_read_err(&self) -> KeyReadErrR { + KeyReadErrR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] + #[inline(always)] + pub fn key_unwrap_err(&self) -> KeyUnwrapErrR { + KeyUnwrapErrR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - reserved"] + #[inline(always)] + pub fn status_rsvd3(&self) -> StatusRsvd3R { + StatusRsvd3R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:31 - reserved"] + #[inline(always)] + pub fn status_rsvd(&self) -> StatusRsvdR { + StatusRsvdR::new(((self.bits >> 19) & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Overflow in INCR operation flag"] + #[inline(always)] + pub fn oflow(&mut self) -> OflowW { + OflowW::new(self, 1) + } + #[doc = "Bits 3:5 - Error detected"] + #[inline(always)] + pub fn error(&mut self) -> ErrorW { + ErrorW::new(self, 3) + } + #[doc = "Bit 7 - interrupt detected"] + #[inline(always)] + pub fn irq(&mut self) -> IrqW { + IrqW::new(self, 7) + } + #[doc = "Bit 16 - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] + #[inline(always)] + pub fn key_read_err(&mut self) -> KeyReadErrW { + KeyReadErrW::new(self, 16) + } + #[doc = "Bit 17 - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] + #[inline(always)] + pub fn key_unwrap_err(&mut self) -> KeyUnwrapErrW { + KeyUnwrapErrW::new(self, 17) + } +} +#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiStatusSpec; +impl crate::RegisterSpec for SgiStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_status::R`](R) reader structure"] +impl crate::Readable for SgiStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`sgi_status::W`](W) writer structure"] +impl crate::Writable for SgiStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets sgi_status to value 0"] +impl crate::Resettable for SgiStatusSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_version.rs b/mcxa276-pac/src/sgi0/sgi_version.rs new file mode 100644 index 000000000..184804f18 --- /dev/null +++ b/mcxa276-pac/src/sgi0/sgi_version.rs @@ -0,0 +1,55 @@ +#[doc = "Register `sgi_version` reader"] +pub type R = crate::R; +#[doc = "Field `z` reader - Extended revision number in X.Y1Y2.Z, e.g. 1.20.3."] +pub type ZR = crate::FieldReader; +#[doc = "Field `y2` reader - Minor revision number 2 in X.Y1Y2.Z, e.g. 1.20.3."] +pub type Y2R = crate::FieldReader; +#[doc = "Field `y1` reader - Minor revision number 1 in X.Y1Y2.Z, e.g. 1.20.3."] +pub type Y1R = crate::FieldReader; +#[doc = "Field `x` reader - Major revision number in X.Y1Y2.Z, e.g. 1.20.3."] +pub type XR = crate::FieldReader; +#[doc = "Field `milestone` reader - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] +pub type MilestoneR = crate::FieldReader; +#[doc = "Field `version_rsvd_1` reader - Reserved for Future Use"] +pub type VersionRsvd1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Extended revision number in X.Y1Y2.Z, e.g. 1.20.3."] + #[inline(always)] + pub fn z(&self) -> ZR { + ZR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Minor revision number 2 in X.Y1Y2.Z, e.g. 1.20.3."] + #[inline(always)] + pub fn y2(&self) -> Y2R { + Y2R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Minor revision number 1 in X.Y1Y2.Z, e.g. 1.20.3."] + #[inline(always)] + pub fn y1(&self) -> Y1R { + Y1R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Major revision number in X.Y1Y2.Z, e.g. 1.20.3."] + #[inline(always)] + pub fn x(&self) -> XR { + XR::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:17 - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] + #[inline(always)] + pub fn milestone(&self) -> MilestoneR { + MilestoneR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:31 - Reserved for Future Use"] + #[inline(always)] + pub fn version_rsvd_1(&self) -> VersionRsvd1R { + VersionRsvd1R::new(((self.bits >> 18) & 0x3fff) as u16) + } +} +#[doc = "SGI Version\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SgiVersionSpec; +impl crate::RegisterSpec for SgiVersionSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sgi_version::R`](R) reader structure"] +impl crate::Readable for SgiVersionSpec {} +#[doc = "`reset()` method sets sgi_version to value 0"] +impl crate::Resettable for SgiVersionSpec {} diff --git a/mcxa276-pac/src/slcd0.rs b/mcxa276-pac/src/slcd0.rs new file mode 100644 index 000000000..11330eacd --- /dev/null +++ b/mcxa276-pac/src/slcd0.rs @@ -0,0 +1,111 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + lcd_gcr: LcdGcr, + lcd_ar: LcdAr, + lcd_fdcr: LcdFdcr, + lcd_fdsr: LcdFdsr, + lcd_pen0: LcdPen0, + lcd_pen1: LcdPen1, + lcd_bpen0: LcdBpen0, + lcd_bpen1: LcdBpen1, + lcd_wfto: [LcdWfto; 12], +} +impl RegisterBlock { + #[doc = "0x00 - LCD General Control Register"] + #[inline(always)] + pub const fn lcd_gcr(&self) -> &LcdGcr { + &self.lcd_gcr + } + #[doc = "0x04 - LCD Auxiliary Register"] + #[inline(always)] + pub const fn lcd_ar(&self) -> &LcdAr { + &self.lcd_ar + } + #[doc = "0x08 - LCD Fault Detect Control Register"] + #[inline(always)] + pub const fn lcd_fdcr(&self) -> &LcdFdcr { + &self.lcd_fdcr + } + #[doc = "0x0c - LCD Fault Detect Status Register"] + #[inline(always)] + pub const fn lcd_fdsr(&self) -> &LcdFdsr { + &self.lcd_fdsr + } + #[doc = "0x10 - LCD Pin Enable Register 0"] + #[inline(always)] + pub const fn lcd_pen0(&self) -> &LcdPen0 { + &self.lcd_pen0 + } + #[doc = "0x14 - LCD Pin Enable Register 1"] + #[inline(always)] + pub const fn lcd_pen1(&self) -> &LcdPen1 { + &self.lcd_pen1 + } + #[doc = "0x18 - LCD Back Plane Enable Register 0"] + #[inline(always)] + pub const fn lcd_bpen0(&self) -> &LcdBpen0 { + &self.lcd_bpen0 + } + #[doc = "0x1c - LCD Back Plane Enable Register 1"] + #[inline(always)] + pub const fn lcd_bpen1(&self) -> &LcdBpen1 { + &self.lcd_bpen1 + } + #[doc = "0x20..0x50 - LCD Waveform i * 4 + 3 to i * 4 Register"] + #[inline(always)] + pub const fn lcd_wfto(&self, n: usize) -> &LcdWfto { + &self.lcd_wfto[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x20..0x50 - LCD Waveform i * 4 + 3 to i * 4 Register"] + #[inline(always)] + pub fn lcd_wfto_iter(&self) -> impl Iterator { + self.lcd_wfto.iter() + } +} +#[doc = "LCD_GCR (rw) register accessor: LCD General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_gcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_gcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_gcr`] module"] +#[doc(alias = "LCD_GCR")] +pub type LcdGcr = crate::Reg; +#[doc = "LCD General Control Register"] +pub mod lcd_gcr; +#[doc = "LCD_AR (rw) register accessor: LCD Auxiliary Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_ar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_ar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_ar`] module"] +#[doc(alias = "LCD_AR")] +pub type LcdAr = crate::Reg; +#[doc = "LCD Auxiliary Register"] +pub mod lcd_ar; +#[doc = "LCD_FDCR (rw) register accessor: LCD Fault Detect Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_fdcr`] module"] +#[doc(alias = "LCD_FDCR")] +pub type LcdFdcr = crate::Reg; +#[doc = "LCD Fault Detect Control Register"] +pub mod lcd_fdcr; +#[doc = "LCD_FDSR (rw) register accessor: LCD Fault Detect Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_fdsr`] module"] +#[doc(alias = "LCD_FDSR")] +pub type LcdFdsr = crate::Reg; +#[doc = "LCD Fault Detect Status Register"] +pub mod lcd_fdsr; +#[doc = "LCD_PEN0 (rw) register accessor: LCD Pin Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_pen0`] module"] +#[doc(alias = "LCD_PEN0")] +pub type LcdPen0 = crate::Reg; +#[doc = "LCD Pin Enable Register 0"] +pub mod lcd_pen0; +#[doc = "LCD_PEN1 (rw) register accessor: LCD Pin Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_pen1`] module"] +#[doc(alias = "LCD_PEN1")] +pub type LcdPen1 = crate::Reg; +#[doc = "LCD Pin Enable Register 1"] +pub mod lcd_pen1; +#[doc = "LCD_BPEN0 (rw) register accessor: LCD Back Plane Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_bpen0`] module"] +#[doc(alias = "LCD_BPEN0")] +pub type LcdBpen0 = crate::Reg; +#[doc = "LCD Back Plane Enable Register 0"] +pub mod lcd_bpen0; +#[doc = "LCD_BPEN1 (rw) register accessor: LCD Back Plane Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_bpen1`] module"] +#[doc(alias = "LCD_BPEN1")] +pub type LcdBpen1 = crate::Reg; +#[doc = "LCD Back Plane Enable Register 1"] +pub mod lcd_bpen1; +#[doc = "LCD_WFTO (rw) register accessor: LCD Waveform i * 4 + 3 to i * 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_wfto::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_wfto::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_wfto`] module"] +#[doc(alias = "LCD_WFTO")] +pub type LcdWfto = crate::Reg; +#[doc = "LCD Waveform i * 4 + 3 to i * 4 Register"] +pub mod lcd_wfto; diff --git a/mcxa276-pac/src/slcd0/lcd_ar.rs b/mcxa276-pac/src/slcd0/lcd_ar.rs new file mode 100644 index 000000000..cf58b5274 --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_ar.rs @@ -0,0 +1,351 @@ +#[doc = "Register `LCD_AR` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_AR` writer"] +pub type W = crate::W; +#[doc = "Field `BRATE` reader - Blink-rate configuration"] +pub type BrateR = crate::FieldReader; +#[doc = "Field `BRATE` writer - Blink-rate configuration"] +pub type BrateW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Blink mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bmode { + #[doc = "0: Display blank during the blink period."] + Blank = 0, + #[doc = "1: Display alternate display during blink period."] + Alternate = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bmode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BMODE` reader - Blink mode"] +pub type BmodeR = crate::BitReader; +impl BmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bmode { + match self.bits { + false => Bmode::Blank, + true => Bmode::Alternate, + } + } + #[doc = "Display blank during the blink period."] + #[inline(always)] + pub fn is_blank(&self) -> bool { + *self == Bmode::Blank + } + #[doc = "Display alternate display during blink period."] + #[inline(always)] + pub fn is_alternate(&self) -> bool { + *self == Bmode::Alternate + } +} +#[doc = "Field `BMODE` writer - Blink mode"] +pub type BmodeW<'a, REG> = crate::BitWriter<'a, REG, Bmode>; +impl<'a, REG> BmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Display blank during the blink period."] + #[inline(always)] + pub fn blank(self) -> &'a mut crate::W { + self.variant(Bmode::Blank) + } + #[doc = "Display alternate display during blink period."] + #[inline(always)] + pub fn alternate(self) -> &'a mut crate::W { + self.variant(Bmode::Alternate) + } +} +#[doc = "Blank display mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Blank { + #[doc = "0: Normal or alternate display mode."] + NotBlank = 0, + #[doc = "1: Blank display mode."] + Blank = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Blank) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BLANK` reader - Blank display mode"] +pub type BlankR = crate::BitReader; +impl BlankR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Blank { + match self.bits { + false => Blank::NotBlank, + true => Blank::Blank, + } + } + #[doc = "Normal or alternate display mode."] + #[inline(always)] + pub fn is_not_blank(&self) -> bool { + *self == Blank::NotBlank + } + #[doc = "Blank display mode."] + #[inline(always)] + pub fn is_blank(&self) -> bool { + *self == Blank::Blank + } +} +#[doc = "Field `BLANK` writer - Blank display mode"] +pub type BlankW<'a, REG> = crate::BitWriter<'a, REG, Blank>; +impl<'a, REG> BlankW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal or alternate display mode."] + #[inline(always)] + pub fn not_blank(self) -> &'a mut crate::W { + self.variant(Blank::NotBlank) + } + #[doc = "Blank display mode."] + #[inline(always)] + pub fn blank(self) -> &'a mut crate::W { + self.variant(Blank::Blank) + } +} +#[doc = "Alternate display mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Alt { + #[doc = "0: Normal display mode."] + Normal = 0, + #[doc = "1: Alternate display mode."] + Alternate = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Alt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ALT` reader - Alternate display mode"] +pub type AltR = crate::BitReader; +impl AltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Alt { + match self.bits { + false => Alt::Normal, + true => Alt::Alternate, + } + } + #[doc = "Normal display mode."] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == Alt::Normal + } + #[doc = "Alternate display mode."] + #[inline(always)] + pub fn is_alternate(&self) -> bool { + *self == Alt::Alternate + } +} +#[doc = "Field `ALT` writer - Alternate display mode"] +pub type AltW<'a, REG> = crate::BitWriter<'a, REG, Alt>; +impl<'a, REG> AltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal display mode."] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(Alt::Normal) + } + #[doc = "Alternate display mode."] + #[inline(always)] + pub fn alternate(self) -> &'a mut crate::W { + self.variant(Alt::Alternate) + } +} +#[doc = "Blink command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Blink { + #[doc = "0: Disables blinking."] + Disable = 0, + #[doc = "1: Starts blinking at blinking frequency specified by LCD blink rate calculation."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Blink) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BLINK` reader - Blink command"] +pub type BlinkR = crate::BitReader; +impl BlinkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Blink { + match self.bits { + false => Blink::Disable, + true => Blink::Enable, + } + } + #[doc = "Disables blinking."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Blink::Disable + } + #[doc = "Starts blinking at blinking frequency specified by LCD blink rate calculation."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Blink::Enable + } +} +#[doc = "Field `BLINK` writer - Blink command"] +pub type BlinkW<'a, REG> = crate::BitWriter<'a, REG, Blink>; +impl<'a, REG> BlinkW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables blinking."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Blink::Disable) + } + #[doc = "Starts blinking at blinking frequency specified by LCD blink rate calculation."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Blink::Enable) + } +} +#[doc = "LCD Frame Frequency Interrupt flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lcdif { + #[doc = "0: Frame frequency interrupt condition has not occurred."] + Disable = 0, + #[doc = "1: Start of SLCD frame has occurred."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lcdif) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LCDIF` reader - LCD Frame Frequency Interrupt flag"] +pub type LcdifR = crate::BitReader; +impl LcdifR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lcdif { + match self.bits { + false => Lcdif::Disable, + true => Lcdif::Enable, + } + } + #[doc = "Frame frequency interrupt condition has not occurred."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lcdif::Disable + } + #[doc = "Start of SLCD frame has occurred."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lcdif::Enable + } +} +#[doc = "Field `LCDIF` writer - LCD Frame Frequency Interrupt flag"] +pub type LcdifW<'a, REG> = crate::BitWriter1C<'a, REG, Lcdif>; +impl<'a, REG> LcdifW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Frame frequency interrupt condition has not occurred."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lcdif::Disable) + } + #[doc = "Start of SLCD frame has occurred."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lcdif::Enable) + } +} +impl R { + #[doc = "Bits 0:2 - Blink-rate configuration"] + #[inline(always)] + pub fn brate(&self) -> BrateR { + BrateR::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Blink mode"] + #[inline(always)] + pub fn bmode(&self) -> BmodeR { + BmodeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Blank display mode"] + #[inline(always)] + pub fn blank(&self) -> BlankR { + BlankR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Alternate display mode"] + #[inline(always)] + pub fn alt(&self) -> AltR { + AltR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Blink command"] + #[inline(always)] + pub fn blink(&self) -> BlinkR { + BlinkR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 15 - LCD Frame Frequency Interrupt flag"] + #[inline(always)] + pub fn lcdif(&self) -> LcdifR { + LcdifR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Blink-rate configuration"] + #[inline(always)] + pub fn brate(&mut self) -> BrateW { + BrateW::new(self, 0) + } + #[doc = "Bit 3 - Blink mode"] + #[inline(always)] + pub fn bmode(&mut self) -> BmodeW { + BmodeW::new(self, 3) + } + #[doc = "Bit 5 - Blank display mode"] + #[inline(always)] + pub fn blank(&mut self) -> BlankW { + BlankW::new(self, 5) + } + #[doc = "Bit 6 - Alternate display mode"] + #[inline(always)] + pub fn alt(&mut self) -> AltW { + AltW::new(self, 6) + } + #[doc = "Bit 7 - Blink command"] + #[inline(always)] + pub fn blink(&mut self) -> BlinkW { + BlinkW::new(self, 7) + } + #[doc = "Bit 15 - LCD Frame Frequency Interrupt flag"] + #[inline(always)] + pub fn lcdif(&mut self) -> LcdifW { + LcdifW::new(self, 15) + } +} +#[doc = "LCD Auxiliary Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_ar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_ar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdArSpec; +impl crate::RegisterSpec for LcdArSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_ar::R`](R) reader structure"] +impl crate::Readable for LcdArSpec {} +#[doc = "`write(|w| ..)` method takes [`lcd_ar::W`](W) writer structure"] +impl crate::Writable for LcdArSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000; +} +#[doc = "`reset()` method sets LCD_AR to value 0"] +impl crate::Resettable for LcdArSpec {} diff --git a/mcxa276-pac/src/slcd0/lcd_bpen0.rs b/mcxa276-pac/src/slcd0/lcd_bpen0.rs new file mode 100644 index 000000000..ad8e1f360 --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_bpen0.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `LCD_BPEN0` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_BPEN0` writer"] +pub type W = crate::W; +#[doc = "LCD Pin 0 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin0Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin0Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_0_BPEN` reader - LCD Pin 0 Back Plane Enable"] +pub type Pin0BpenR = crate::BitReader; +impl Pin0BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin0Bpen { + match self.bits { + false => Pin0Bpen::Fp, + true => Pin0Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin0Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin0Bpen::Bp + } +} +#[doc = "Field `PIN_0_BPEN` writer - LCD Pin 0 Back Plane Enable"] +pub type Pin0BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin0Bpen>; +impl<'a, REG> Pin0BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin0Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin0Bpen::Bp) + } +} +#[doc = "LCD Pin 1 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin1Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin1Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_1_BPEN` reader - LCD Pin 1 Back Plane Enable"] +pub type Pin1BpenR = crate::BitReader; +impl Pin1BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin1Bpen { + match self.bits { + false => Pin1Bpen::Fp, + true => Pin1Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin1Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin1Bpen::Bp + } +} +#[doc = "Field `PIN_1_BPEN` writer - LCD Pin 1 Back Plane Enable"] +pub type Pin1BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin1Bpen>; +impl<'a, REG> Pin1BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin1Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin1Bpen::Bp) + } +} +#[doc = "LCD Pin 2 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin2Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin2Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_2_BPEN` reader - LCD Pin 2 Back Plane Enable"] +pub type Pin2BpenR = crate::BitReader; +impl Pin2BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin2Bpen { + match self.bits { + false => Pin2Bpen::Fp, + true => Pin2Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin2Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin2Bpen::Bp + } +} +#[doc = "Field `PIN_2_BPEN` writer - LCD Pin 2 Back Plane Enable"] +pub type Pin2BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin2Bpen>; +impl<'a, REG> Pin2BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin2Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin2Bpen::Bp) + } +} +#[doc = "LCD Pin 3 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin3Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin3Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_3_BPEN` reader - LCD Pin 3 Back Plane Enable"] +pub type Pin3BpenR = crate::BitReader; +impl Pin3BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin3Bpen { + match self.bits { + false => Pin3Bpen::Fp, + true => Pin3Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin3Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin3Bpen::Bp + } +} +#[doc = "Field `PIN_3_BPEN` writer - LCD Pin 3 Back Plane Enable"] +pub type Pin3BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin3Bpen>; +impl<'a, REG> Pin3BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin3Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin3Bpen::Bp) + } +} +#[doc = "LCD Pin 4 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin4Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin4Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_4_BPEN` reader - LCD Pin 4 Back Plane Enable"] +pub type Pin4BpenR = crate::BitReader; +impl Pin4BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin4Bpen { + match self.bits { + false => Pin4Bpen::Fp, + true => Pin4Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin4Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin4Bpen::Bp + } +} +#[doc = "Field `PIN_4_BPEN` writer - LCD Pin 4 Back Plane Enable"] +pub type Pin4BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin4Bpen>; +impl<'a, REG> Pin4BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin4Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin4Bpen::Bp) + } +} +#[doc = "LCD Pin 5 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin5Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin5Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_5_BPEN` reader - LCD Pin 5 Back Plane Enable"] +pub type Pin5BpenR = crate::BitReader; +impl Pin5BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin5Bpen { + match self.bits { + false => Pin5Bpen::Fp, + true => Pin5Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin5Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin5Bpen::Bp + } +} +#[doc = "Field `PIN_5_BPEN` writer - LCD Pin 5 Back Plane Enable"] +pub type Pin5BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin5Bpen>; +impl<'a, REG> Pin5BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin5Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin5Bpen::Bp) + } +} +#[doc = "LCD Pin 6 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin6Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin6Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_6_BPEN` reader - LCD Pin 6 Back Plane Enable"] +pub type Pin6BpenR = crate::BitReader; +impl Pin6BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin6Bpen { + match self.bits { + false => Pin6Bpen::Fp, + true => Pin6Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin6Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin6Bpen::Bp + } +} +#[doc = "Field `PIN_6_BPEN` writer - LCD Pin 6 Back Plane Enable"] +pub type Pin6BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin6Bpen>; +impl<'a, REG> Pin6BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin6Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin6Bpen::Bp) + } +} +#[doc = "LCD Pin 7 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin7Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin7Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_7_BPEN` reader - LCD Pin 7 Back Plane Enable"] +pub type Pin7BpenR = crate::BitReader; +impl Pin7BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin7Bpen { + match self.bits { + false => Pin7Bpen::Fp, + true => Pin7Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin7Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin7Bpen::Bp + } +} +#[doc = "Field `PIN_7_BPEN` writer - LCD Pin 7 Back Plane Enable"] +pub type Pin7BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin7Bpen>; +impl<'a, REG> Pin7BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin7Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin7Bpen::Bp) + } +} +#[doc = "LCD Pin 8 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin8Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin8Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_8_BPEN` reader - LCD Pin 8 Back Plane Enable"] +pub type Pin8BpenR = crate::BitReader; +impl Pin8BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin8Bpen { + match self.bits { + false => Pin8Bpen::Fp, + true => Pin8Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin8Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin8Bpen::Bp + } +} +#[doc = "Field `PIN_8_BPEN` writer - LCD Pin 8 Back Plane Enable"] +pub type Pin8BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin8Bpen>; +impl<'a, REG> Pin8BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin8Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin8Bpen::Bp) + } +} +#[doc = "LCD Pin 9 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin9Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin9Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_9_BPEN` reader - LCD Pin 9 Back Plane Enable"] +pub type Pin9BpenR = crate::BitReader; +impl Pin9BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin9Bpen { + match self.bits { + false => Pin9Bpen::Fp, + true => Pin9Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin9Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin9Bpen::Bp + } +} +#[doc = "Field `PIN_9_BPEN` writer - LCD Pin 9 Back Plane Enable"] +pub type Pin9BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin9Bpen>; +impl<'a, REG> Pin9BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin9Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin9Bpen::Bp) + } +} +#[doc = "LCD Pin 10 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin10Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin10Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_10_BPEN` reader - LCD Pin 10 Back Plane Enable"] +pub type Pin10BpenR = crate::BitReader; +impl Pin10BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin10Bpen { + match self.bits { + false => Pin10Bpen::Fp, + true => Pin10Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin10Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin10Bpen::Bp + } +} +#[doc = "Field `PIN_10_BPEN` writer - LCD Pin 10 Back Plane Enable"] +pub type Pin10BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin10Bpen>; +impl<'a, REG> Pin10BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin10Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin10Bpen::Bp) + } +} +#[doc = "LCD Pin 11 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin11Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin11Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_11_BPEN` reader - LCD Pin 11 Back Plane Enable"] +pub type Pin11BpenR = crate::BitReader; +impl Pin11BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin11Bpen { + match self.bits { + false => Pin11Bpen::Fp, + true => Pin11Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin11Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin11Bpen::Bp + } +} +#[doc = "Field `PIN_11_BPEN` writer - LCD Pin 11 Back Plane Enable"] +pub type Pin11BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin11Bpen>; +impl<'a, REG> Pin11BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin11Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin11Bpen::Bp) + } +} +#[doc = "LCD Pin 12 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin12Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin12Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_12_BPEN` reader - LCD Pin 12 Back Plane Enable"] +pub type Pin12BpenR = crate::BitReader; +impl Pin12BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin12Bpen { + match self.bits { + false => Pin12Bpen::Fp, + true => Pin12Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin12Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin12Bpen::Bp + } +} +#[doc = "Field `PIN_12_BPEN` writer - LCD Pin 12 Back Plane Enable"] +pub type Pin12BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin12Bpen>; +impl<'a, REG> Pin12BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin12Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin12Bpen::Bp) + } +} +#[doc = "LCD Pin 13 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin13Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin13Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_13_BPEN` reader - LCD Pin 13 Back Plane Enable"] +pub type Pin13BpenR = crate::BitReader; +impl Pin13BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin13Bpen { + match self.bits { + false => Pin13Bpen::Fp, + true => Pin13Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin13Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin13Bpen::Bp + } +} +#[doc = "Field `PIN_13_BPEN` writer - LCD Pin 13 Back Plane Enable"] +pub type Pin13BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin13Bpen>; +impl<'a, REG> Pin13BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin13Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin13Bpen::Bp) + } +} +#[doc = "LCD Pin 14 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin14Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin14Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_14_BPEN` reader - LCD Pin 14 Back Plane Enable"] +pub type Pin14BpenR = crate::BitReader; +impl Pin14BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin14Bpen { + match self.bits { + false => Pin14Bpen::Fp, + true => Pin14Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin14Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin14Bpen::Bp + } +} +#[doc = "Field `PIN_14_BPEN` writer - LCD Pin 14 Back Plane Enable"] +pub type Pin14BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin14Bpen>; +impl<'a, REG> Pin14BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin14Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin14Bpen::Bp) + } +} +#[doc = "LCD Pin 15 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin15Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin15Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_15_BPEN` reader - LCD Pin 15 Back Plane Enable"] +pub type Pin15BpenR = crate::BitReader; +impl Pin15BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin15Bpen { + match self.bits { + false => Pin15Bpen::Fp, + true => Pin15Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin15Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin15Bpen::Bp + } +} +#[doc = "Field `PIN_15_BPEN` writer - LCD Pin 15 Back Plane Enable"] +pub type Pin15BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin15Bpen>; +impl<'a, REG> Pin15BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin15Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin15Bpen::Bp) + } +} +#[doc = "LCD Pin 16 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin16Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin16Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_16_BPEN` reader - LCD Pin 16 Back Plane Enable"] +pub type Pin16BpenR = crate::BitReader; +impl Pin16BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin16Bpen { + match self.bits { + false => Pin16Bpen::Fp, + true => Pin16Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin16Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin16Bpen::Bp + } +} +#[doc = "Field `PIN_16_BPEN` writer - LCD Pin 16 Back Plane Enable"] +pub type Pin16BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin16Bpen>; +impl<'a, REG> Pin16BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin16Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin16Bpen::Bp) + } +} +#[doc = "LCD Pin 17 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin17Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin17Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_17_BPEN` reader - LCD Pin 17 Back Plane Enable"] +pub type Pin17BpenR = crate::BitReader; +impl Pin17BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin17Bpen { + match self.bits { + false => Pin17Bpen::Fp, + true => Pin17Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin17Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin17Bpen::Bp + } +} +#[doc = "Field `PIN_17_BPEN` writer - LCD Pin 17 Back Plane Enable"] +pub type Pin17BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin17Bpen>; +impl<'a, REG> Pin17BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin17Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin17Bpen::Bp) + } +} +#[doc = "LCD Pin 18 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin18Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin18Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_18_BPEN` reader - LCD Pin 18 Back Plane Enable"] +pub type Pin18BpenR = crate::BitReader; +impl Pin18BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin18Bpen { + match self.bits { + false => Pin18Bpen::Fp, + true => Pin18Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin18Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin18Bpen::Bp + } +} +#[doc = "Field `PIN_18_BPEN` writer - LCD Pin 18 Back Plane Enable"] +pub type Pin18BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin18Bpen>; +impl<'a, REG> Pin18BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin18Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin18Bpen::Bp) + } +} +#[doc = "LCD Pin 19 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin19Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin19Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_19_BPEN` reader - LCD Pin 19 Back Plane Enable"] +pub type Pin19BpenR = crate::BitReader; +impl Pin19BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin19Bpen { + match self.bits { + false => Pin19Bpen::Fp, + true => Pin19Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin19Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin19Bpen::Bp + } +} +#[doc = "Field `PIN_19_BPEN` writer - LCD Pin 19 Back Plane Enable"] +pub type Pin19BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin19Bpen>; +impl<'a, REG> Pin19BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin19Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin19Bpen::Bp) + } +} +#[doc = "LCD Pin 20 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin20Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin20Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_20_BPEN` reader - LCD Pin 20 Back Plane Enable"] +pub type Pin20BpenR = crate::BitReader; +impl Pin20BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin20Bpen { + match self.bits { + false => Pin20Bpen::Fp, + true => Pin20Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin20Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin20Bpen::Bp + } +} +#[doc = "Field `PIN_20_BPEN` writer - LCD Pin 20 Back Plane Enable"] +pub type Pin20BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin20Bpen>; +impl<'a, REG> Pin20BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin20Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin20Bpen::Bp) + } +} +#[doc = "LCD Pin 21 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin21Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin21Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_21_BPEN` reader - LCD Pin 21 Back Plane Enable"] +pub type Pin21BpenR = crate::BitReader; +impl Pin21BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin21Bpen { + match self.bits { + false => Pin21Bpen::Fp, + true => Pin21Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin21Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin21Bpen::Bp + } +} +#[doc = "Field `PIN_21_BPEN` writer - LCD Pin 21 Back Plane Enable"] +pub type Pin21BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin21Bpen>; +impl<'a, REG> Pin21BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin21Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin21Bpen::Bp) + } +} +#[doc = "LCD Pin 22 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin22Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin22Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_22_BPEN` reader - LCD Pin 22 Back Plane Enable"] +pub type Pin22BpenR = crate::BitReader; +impl Pin22BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin22Bpen { + match self.bits { + false => Pin22Bpen::Fp, + true => Pin22Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin22Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin22Bpen::Bp + } +} +#[doc = "Field `PIN_22_BPEN` writer - LCD Pin 22 Back Plane Enable"] +pub type Pin22BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin22Bpen>; +impl<'a, REG> Pin22BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin22Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin22Bpen::Bp) + } +} +#[doc = "LCD Pin 23 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin23Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin23Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_23_BPEN` reader - LCD Pin 23 Back Plane Enable"] +pub type Pin23BpenR = crate::BitReader; +impl Pin23BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin23Bpen { + match self.bits { + false => Pin23Bpen::Fp, + true => Pin23Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin23Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin23Bpen::Bp + } +} +#[doc = "Field `PIN_23_BPEN` writer - LCD Pin 23 Back Plane Enable"] +pub type Pin23BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin23Bpen>; +impl<'a, REG> Pin23BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin23Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin23Bpen::Bp) + } +} +#[doc = "LCD Pin 24 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin24Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin24Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_24_BPEN` reader - LCD Pin 24 Back Plane Enable"] +pub type Pin24BpenR = crate::BitReader; +impl Pin24BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin24Bpen { + match self.bits { + false => Pin24Bpen::Fp, + true => Pin24Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin24Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin24Bpen::Bp + } +} +#[doc = "Field `PIN_24_BPEN` writer - LCD Pin 24 Back Plane Enable"] +pub type Pin24BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin24Bpen>; +impl<'a, REG> Pin24BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin24Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin24Bpen::Bp) + } +} +#[doc = "LCD Pin 25 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin25Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin25Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_25_BPEN` reader - LCD Pin 25 Back Plane Enable"] +pub type Pin25BpenR = crate::BitReader; +impl Pin25BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin25Bpen { + match self.bits { + false => Pin25Bpen::Fp, + true => Pin25Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin25Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin25Bpen::Bp + } +} +#[doc = "Field `PIN_25_BPEN` writer - LCD Pin 25 Back Plane Enable"] +pub type Pin25BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin25Bpen>; +impl<'a, REG> Pin25BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin25Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin25Bpen::Bp) + } +} +#[doc = "LCD Pin 26 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin26Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin26Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_26_BPEN` reader - LCD Pin 26 Back Plane Enable"] +pub type Pin26BpenR = crate::BitReader; +impl Pin26BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin26Bpen { + match self.bits { + false => Pin26Bpen::Fp, + true => Pin26Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin26Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin26Bpen::Bp + } +} +#[doc = "Field `PIN_26_BPEN` writer - LCD Pin 26 Back Plane Enable"] +pub type Pin26BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin26Bpen>; +impl<'a, REG> Pin26BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin26Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin26Bpen::Bp) + } +} +#[doc = "LCD Pin 27 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin27Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin27Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_27_BPEN` reader - LCD Pin 27 Back Plane Enable"] +pub type Pin27BpenR = crate::BitReader; +impl Pin27BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin27Bpen { + match self.bits { + false => Pin27Bpen::Fp, + true => Pin27Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin27Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin27Bpen::Bp + } +} +#[doc = "Field `PIN_27_BPEN` writer - LCD Pin 27 Back Plane Enable"] +pub type Pin27BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin27Bpen>; +impl<'a, REG> Pin27BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin27Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin27Bpen::Bp) + } +} +#[doc = "LCD Pin 28 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin28Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin28Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_28_BPEN` reader - LCD Pin 28 Back Plane Enable"] +pub type Pin28BpenR = crate::BitReader; +impl Pin28BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin28Bpen { + match self.bits { + false => Pin28Bpen::Fp, + true => Pin28Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin28Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin28Bpen::Bp + } +} +#[doc = "Field `PIN_28_BPEN` writer - LCD Pin 28 Back Plane Enable"] +pub type Pin28BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin28Bpen>; +impl<'a, REG> Pin28BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin28Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin28Bpen::Bp) + } +} +#[doc = "LCD Pin 29 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin29Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin29Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_29_BPEN` reader - LCD Pin 29 Back Plane Enable"] +pub type Pin29BpenR = crate::BitReader; +impl Pin29BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin29Bpen { + match self.bits { + false => Pin29Bpen::Fp, + true => Pin29Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin29Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin29Bpen::Bp + } +} +#[doc = "Field `PIN_29_BPEN` writer - LCD Pin 29 Back Plane Enable"] +pub type Pin29BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin29Bpen>; +impl<'a, REG> Pin29BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin29Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin29Bpen::Bp) + } +} +#[doc = "LCD Pin 30 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin30Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin30Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_30_BPEN` reader - LCD Pin 30 Back Plane Enable"] +pub type Pin30BpenR = crate::BitReader; +impl Pin30BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin30Bpen { + match self.bits { + false => Pin30Bpen::Fp, + true => Pin30Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin30Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin30Bpen::Bp + } +} +#[doc = "Field `PIN_30_BPEN` writer - LCD Pin 30 Back Plane Enable"] +pub type Pin30BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin30Bpen>; +impl<'a, REG> Pin30BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin30Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin30Bpen::Bp) + } +} +#[doc = "LCD Pin 31 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin31Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin31Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_31_BPEN` reader - LCD Pin 31 Back Plane Enable"] +pub type Pin31BpenR = crate::BitReader; +impl Pin31BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin31Bpen { + match self.bits { + false => Pin31Bpen::Fp, + true => Pin31Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin31Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin31Bpen::Bp + } +} +#[doc = "Field `PIN_31_BPEN` writer - LCD Pin 31 Back Plane Enable"] +pub type Pin31BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin31Bpen>; +impl<'a, REG> Pin31BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin31Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin31Bpen::Bp) + } +} +impl R { + #[doc = "Bit 0 - LCD Pin 0 Back Plane Enable"] + #[inline(always)] + pub fn pin_0_bpen(&self) -> Pin0BpenR { + Pin0BpenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - LCD Pin 1 Back Plane Enable"] + #[inline(always)] + pub fn pin_1_bpen(&self) -> Pin1BpenR { + Pin1BpenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LCD Pin 2 Back Plane Enable"] + #[inline(always)] + pub fn pin_2_bpen(&self) -> Pin2BpenR { + Pin2BpenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - LCD Pin 3 Back Plane Enable"] + #[inline(always)] + pub fn pin_3_bpen(&self) -> Pin3BpenR { + Pin3BpenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - LCD Pin 4 Back Plane Enable"] + #[inline(always)] + pub fn pin_4_bpen(&self) -> Pin4BpenR { + Pin4BpenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - LCD Pin 5 Back Plane Enable"] + #[inline(always)] + pub fn pin_5_bpen(&self) -> Pin5BpenR { + Pin5BpenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - LCD Pin 6 Back Plane Enable"] + #[inline(always)] + pub fn pin_6_bpen(&self) -> Pin6BpenR { + Pin6BpenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - LCD Pin 7 Back Plane Enable"] + #[inline(always)] + pub fn pin_7_bpen(&self) -> Pin7BpenR { + Pin7BpenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - LCD Pin 8 Back Plane Enable"] + #[inline(always)] + pub fn pin_8_bpen(&self) -> Pin8BpenR { + Pin8BpenR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - LCD Pin 9 Back Plane Enable"] + #[inline(always)] + pub fn pin_9_bpen(&self) -> Pin9BpenR { + Pin9BpenR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - LCD Pin 10 Back Plane Enable"] + #[inline(always)] + pub fn pin_10_bpen(&self) -> Pin10BpenR { + Pin10BpenR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - LCD Pin 11 Back Plane Enable"] + #[inline(always)] + pub fn pin_11_bpen(&self) -> Pin11BpenR { + Pin11BpenR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - LCD Pin 12 Back Plane Enable"] + #[inline(always)] + pub fn pin_12_bpen(&self) -> Pin12BpenR { + Pin12BpenR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - LCD Pin 13 Back Plane Enable"] + #[inline(always)] + pub fn pin_13_bpen(&self) -> Pin13BpenR { + Pin13BpenR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - LCD Pin 14 Back Plane Enable"] + #[inline(always)] + pub fn pin_14_bpen(&self) -> Pin14BpenR { + Pin14BpenR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - LCD Pin 15 Back Plane Enable"] + #[inline(always)] + pub fn pin_15_bpen(&self) -> Pin15BpenR { + Pin15BpenR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - LCD Pin 16 Back Plane Enable"] + #[inline(always)] + pub fn pin_16_bpen(&self) -> Pin16BpenR { + Pin16BpenR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - LCD Pin 17 Back Plane Enable"] + #[inline(always)] + pub fn pin_17_bpen(&self) -> Pin17BpenR { + Pin17BpenR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - LCD Pin 18 Back Plane Enable"] + #[inline(always)] + pub fn pin_18_bpen(&self) -> Pin18BpenR { + Pin18BpenR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - LCD Pin 19 Back Plane Enable"] + #[inline(always)] + pub fn pin_19_bpen(&self) -> Pin19BpenR { + Pin19BpenR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LCD Pin 20 Back Plane Enable"] + #[inline(always)] + pub fn pin_20_bpen(&self) -> Pin20BpenR { + Pin20BpenR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LCD Pin 21 Back Plane Enable"] + #[inline(always)] + pub fn pin_21_bpen(&self) -> Pin21BpenR { + Pin21BpenR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LCD Pin 22 Back Plane Enable"] + #[inline(always)] + pub fn pin_22_bpen(&self) -> Pin22BpenR { + Pin22BpenR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - LCD Pin 23 Back Plane Enable"] + #[inline(always)] + pub fn pin_23_bpen(&self) -> Pin23BpenR { + Pin23BpenR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - LCD Pin 24 Back Plane Enable"] + #[inline(always)] + pub fn pin_24_bpen(&self) -> Pin24BpenR { + Pin24BpenR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - LCD Pin 25 Back Plane Enable"] + #[inline(always)] + pub fn pin_25_bpen(&self) -> Pin25BpenR { + Pin25BpenR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - LCD Pin 26 Back Plane Enable"] + #[inline(always)] + pub fn pin_26_bpen(&self) -> Pin26BpenR { + Pin26BpenR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LCD Pin 27 Back Plane Enable"] + #[inline(always)] + pub fn pin_27_bpen(&self) -> Pin27BpenR { + Pin27BpenR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - LCD Pin 28 Back Plane Enable"] + #[inline(always)] + pub fn pin_28_bpen(&self) -> Pin28BpenR { + Pin28BpenR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - LCD Pin 29 Back Plane Enable"] + #[inline(always)] + pub fn pin_29_bpen(&self) -> Pin29BpenR { + Pin29BpenR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - LCD Pin 30 Back Plane Enable"] + #[inline(always)] + pub fn pin_30_bpen(&self) -> Pin30BpenR { + Pin30BpenR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - LCD Pin 31 Back Plane Enable"] + #[inline(always)] + pub fn pin_31_bpen(&self) -> Pin31BpenR { + Pin31BpenR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LCD Pin 0 Back Plane Enable"] + #[inline(always)] + pub fn pin_0_bpen(&mut self) -> Pin0BpenW { + Pin0BpenW::new(self, 0) + } + #[doc = "Bit 1 - LCD Pin 1 Back Plane Enable"] + #[inline(always)] + pub fn pin_1_bpen(&mut self) -> Pin1BpenW { + Pin1BpenW::new(self, 1) + } + #[doc = "Bit 2 - LCD Pin 2 Back Plane Enable"] + #[inline(always)] + pub fn pin_2_bpen(&mut self) -> Pin2BpenW { + Pin2BpenW::new(self, 2) + } + #[doc = "Bit 3 - LCD Pin 3 Back Plane Enable"] + #[inline(always)] + pub fn pin_3_bpen(&mut self) -> Pin3BpenW { + Pin3BpenW::new(self, 3) + } + #[doc = "Bit 4 - LCD Pin 4 Back Plane Enable"] + #[inline(always)] + pub fn pin_4_bpen(&mut self) -> Pin4BpenW { + Pin4BpenW::new(self, 4) + } + #[doc = "Bit 5 - LCD Pin 5 Back Plane Enable"] + #[inline(always)] + pub fn pin_5_bpen(&mut self) -> Pin5BpenW { + Pin5BpenW::new(self, 5) + } + #[doc = "Bit 6 - LCD Pin 6 Back Plane Enable"] + #[inline(always)] + pub fn pin_6_bpen(&mut self) -> Pin6BpenW { + Pin6BpenW::new(self, 6) + } + #[doc = "Bit 7 - LCD Pin 7 Back Plane Enable"] + #[inline(always)] + pub fn pin_7_bpen(&mut self) -> Pin7BpenW { + Pin7BpenW::new(self, 7) + } + #[doc = "Bit 8 - LCD Pin 8 Back Plane Enable"] + #[inline(always)] + pub fn pin_8_bpen(&mut self) -> Pin8BpenW { + Pin8BpenW::new(self, 8) + } + #[doc = "Bit 9 - LCD Pin 9 Back Plane Enable"] + #[inline(always)] + pub fn pin_9_bpen(&mut self) -> Pin9BpenW { + Pin9BpenW::new(self, 9) + } + #[doc = "Bit 10 - LCD Pin 10 Back Plane Enable"] + #[inline(always)] + pub fn pin_10_bpen(&mut self) -> Pin10BpenW { + Pin10BpenW::new(self, 10) + } + #[doc = "Bit 11 - LCD Pin 11 Back Plane Enable"] + #[inline(always)] + pub fn pin_11_bpen(&mut self) -> Pin11BpenW { + Pin11BpenW::new(self, 11) + } + #[doc = "Bit 12 - LCD Pin 12 Back Plane Enable"] + #[inline(always)] + pub fn pin_12_bpen(&mut self) -> Pin12BpenW { + Pin12BpenW::new(self, 12) + } + #[doc = "Bit 13 - LCD Pin 13 Back Plane Enable"] + #[inline(always)] + pub fn pin_13_bpen(&mut self) -> Pin13BpenW { + Pin13BpenW::new(self, 13) + } + #[doc = "Bit 14 - LCD Pin 14 Back Plane Enable"] + #[inline(always)] + pub fn pin_14_bpen(&mut self) -> Pin14BpenW { + Pin14BpenW::new(self, 14) + } + #[doc = "Bit 15 - LCD Pin 15 Back Plane Enable"] + #[inline(always)] + pub fn pin_15_bpen(&mut self) -> Pin15BpenW { + Pin15BpenW::new(self, 15) + } + #[doc = "Bit 16 - LCD Pin 16 Back Plane Enable"] + #[inline(always)] + pub fn pin_16_bpen(&mut self) -> Pin16BpenW { + Pin16BpenW::new(self, 16) + } + #[doc = "Bit 17 - LCD Pin 17 Back Plane Enable"] + #[inline(always)] + pub fn pin_17_bpen(&mut self) -> Pin17BpenW { + Pin17BpenW::new(self, 17) + } + #[doc = "Bit 18 - LCD Pin 18 Back Plane Enable"] + #[inline(always)] + pub fn pin_18_bpen(&mut self) -> Pin18BpenW { + Pin18BpenW::new(self, 18) + } + #[doc = "Bit 19 - LCD Pin 19 Back Plane Enable"] + #[inline(always)] + pub fn pin_19_bpen(&mut self) -> Pin19BpenW { + Pin19BpenW::new(self, 19) + } + #[doc = "Bit 20 - LCD Pin 20 Back Plane Enable"] + #[inline(always)] + pub fn pin_20_bpen(&mut self) -> Pin20BpenW { + Pin20BpenW::new(self, 20) + } + #[doc = "Bit 21 - LCD Pin 21 Back Plane Enable"] + #[inline(always)] + pub fn pin_21_bpen(&mut self) -> Pin21BpenW { + Pin21BpenW::new(self, 21) + } + #[doc = "Bit 22 - LCD Pin 22 Back Plane Enable"] + #[inline(always)] + pub fn pin_22_bpen(&mut self) -> Pin22BpenW { + Pin22BpenW::new(self, 22) + } + #[doc = "Bit 23 - LCD Pin 23 Back Plane Enable"] + #[inline(always)] + pub fn pin_23_bpen(&mut self) -> Pin23BpenW { + Pin23BpenW::new(self, 23) + } + #[doc = "Bit 24 - LCD Pin 24 Back Plane Enable"] + #[inline(always)] + pub fn pin_24_bpen(&mut self) -> Pin24BpenW { + Pin24BpenW::new(self, 24) + } + #[doc = "Bit 25 - LCD Pin 25 Back Plane Enable"] + #[inline(always)] + pub fn pin_25_bpen(&mut self) -> Pin25BpenW { + Pin25BpenW::new(self, 25) + } + #[doc = "Bit 26 - LCD Pin 26 Back Plane Enable"] + #[inline(always)] + pub fn pin_26_bpen(&mut self) -> Pin26BpenW { + Pin26BpenW::new(self, 26) + } + #[doc = "Bit 27 - LCD Pin 27 Back Plane Enable"] + #[inline(always)] + pub fn pin_27_bpen(&mut self) -> Pin27BpenW { + Pin27BpenW::new(self, 27) + } + #[doc = "Bit 28 - LCD Pin 28 Back Plane Enable"] + #[inline(always)] + pub fn pin_28_bpen(&mut self) -> Pin28BpenW { + Pin28BpenW::new(self, 28) + } + #[doc = "Bit 29 - LCD Pin 29 Back Plane Enable"] + #[inline(always)] + pub fn pin_29_bpen(&mut self) -> Pin29BpenW { + Pin29BpenW::new(self, 29) + } + #[doc = "Bit 30 - LCD Pin 30 Back Plane Enable"] + #[inline(always)] + pub fn pin_30_bpen(&mut self) -> Pin30BpenW { + Pin30BpenW::new(self, 30) + } + #[doc = "Bit 31 - LCD Pin 31 Back Plane Enable"] + #[inline(always)] + pub fn pin_31_bpen(&mut self) -> Pin31BpenW { + Pin31BpenW::new(self, 31) + } +} +#[doc = "LCD Back Plane Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdBpen0Spec; +impl crate::RegisterSpec for LcdBpen0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_bpen0::R`](R) reader structure"] +impl crate::Readable for LcdBpen0Spec {} +#[doc = "`write(|w| ..)` method takes [`lcd_bpen0::W`](W) writer structure"] +impl crate::Writable for LcdBpen0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCD_BPEN0 to value 0"] +impl crate::Resettable for LcdBpen0Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_bpen1.rs b/mcxa276-pac/src/slcd0/lcd_bpen1.rs new file mode 100644 index 000000000..acc24293f --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_bpen1.rs @@ -0,0 +1,1029 @@ +#[doc = "Register `LCD_BPEN1` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_BPEN1` writer"] +pub type W = crate::W; +#[doc = "LCD Pin 32 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin32Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin32Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_32_BPEN` reader - LCD Pin 32 Back Plane Enable"] +pub type Pin32BpenR = crate::BitReader; +impl Pin32BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin32Bpen { + match self.bits { + false => Pin32Bpen::Fp, + true => Pin32Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin32Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin32Bpen::Bp + } +} +#[doc = "Field `PIN_32_BPEN` writer - LCD Pin 32 Back Plane Enable"] +pub type Pin32BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin32Bpen>; +impl<'a, REG> Pin32BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin32Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin32Bpen::Bp) + } +} +#[doc = "LCD Pin 33 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin33Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin33Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_33_BPEN` reader - LCD Pin 33 Back Plane Enable"] +pub type Pin33BpenR = crate::BitReader; +impl Pin33BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin33Bpen { + match self.bits { + false => Pin33Bpen::Fp, + true => Pin33Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin33Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin33Bpen::Bp + } +} +#[doc = "Field `PIN_33_BPEN` writer - LCD Pin 33 Back Plane Enable"] +pub type Pin33BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin33Bpen>; +impl<'a, REG> Pin33BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin33Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin33Bpen::Bp) + } +} +#[doc = "LCD Pin 34 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin34Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin34Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_34_BPEN` reader - LCD Pin 34 Back Plane Enable"] +pub type Pin34BpenR = crate::BitReader; +impl Pin34BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin34Bpen { + match self.bits { + false => Pin34Bpen::Fp, + true => Pin34Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin34Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin34Bpen::Bp + } +} +#[doc = "Field `PIN_34_BPEN` writer - LCD Pin 34 Back Plane Enable"] +pub type Pin34BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin34Bpen>; +impl<'a, REG> Pin34BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin34Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin34Bpen::Bp) + } +} +#[doc = "LCD Pin 35 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin35Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin35Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_35_BPEN` reader - LCD Pin 35 Back Plane Enable"] +pub type Pin35BpenR = crate::BitReader; +impl Pin35BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin35Bpen { + match self.bits { + false => Pin35Bpen::Fp, + true => Pin35Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin35Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin35Bpen::Bp + } +} +#[doc = "Field `PIN_35_BPEN` writer - LCD Pin 35 Back Plane Enable"] +pub type Pin35BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin35Bpen>; +impl<'a, REG> Pin35BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin35Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin35Bpen::Bp) + } +} +#[doc = "LCD Pin 36 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin36Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin36Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_36_BPEN` reader - LCD Pin 36 Back Plane Enable"] +pub type Pin36BpenR = crate::BitReader; +impl Pin36BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin36Bpen { + match self.bits { + false => Pin36Bpen::Fp, + true => Pin36Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin36Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin36Bpen::Bp + } +} +#[doc = "Field `PIN_36_BPEN` writer - LCD Pin 36 Back Plane Enable"] +pub type Pin36BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin36Bpen>; +impl<'a, REG> Pin36BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin36Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin36Bpen::Bp) + } +} +#[doc = "LCD Pin 37 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin37Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin37Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_37_BPEN` reader - LCD Pin 37 Back Plane Enable"] +pub type Pin37BpenR = crate::BitReader; +impl Pin37BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin37Bpen { + match self.bits { + false => Pin37Bpen::Fp, + true => Pin37Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin37Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin37Bpen::Bp + } +} +#[doc = "Field `PIN_37_BPEN` writer - LCD Pin 37 Back Plane Enable"] +pub type Pin37BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin37Bpen>; +impl<'a, REG> Pin37BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin37Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin37Bpen::Bp) + } +} +#[doc = "LCD Pin 38 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin38Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin38Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_38_BPEN` reader - LCD Pin 38 Back Plane Enable"] +pub type Pin38BpenR = crate::BitReader; +impl Pin38BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin38Bpen { + match self.bits { + false => Pin38Bpen::Fp, + true => Pin38Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin38Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin38Bpen::Bp + } +} +#[doc = "Field `PIN_38_BPEN` writer - LCD Pin 38 Back Plane Enable"] +pub type Pin38BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin38Bpen>; +impl<'a, REG> Pin38BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin38Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin38Bpen::Bp) + } +} +#[doc = "LCD Pin 39 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin39Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin39Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_39_BPEN` reader - LCD Pin 39 Back Plane Enable"] +pub type Pin39BpenR = crate::BitReader; +impl Pin39BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin39Bpen { + match self.bits { + false => Pin39Bpen::Fp, + true => Pin39Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin39Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin39Bpen::Bp + } +} +#[doc = "Field `PIN_39_BPEN` writer - LCD Pin 39 Back Plane Enable"] +pub type Pin39BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin39Bpen>; +impl<'a, REG> Pin39BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin39Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin39Bpen::Bp) + } +} +#[doc = "LCD Pin 40 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin40Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin40Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_40_BPEN` reader - LCD Pin 40 Back Plane Enable"] +pub type Pin40BpenR = crate::BitReader; +impl Pin40BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin40Bpen { + match self.bits { + false => Pin40Bpen::Fp, + true => Pin40Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin40Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin40Bpen::Bp + } +} +#[doc = "Field `PIN_40_BPEN` writer - LCD Pin 40 Back Plane Enable"] +pub type Pin40BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin40Bpen>; +impl<'a, REG> Pin40BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin40Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin40Bpen::Bp) + } +} +#[doc = "LCD Pin 41 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin41Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin41Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_41_BPEN` reader - LCD Pin 41 Back Plane Enable"] +pub type Pin41BpenR = crate::BitReader; +impl Pin41BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin41Bpen { + match self.bits { + false => Pin41Bpen::Fp, + true => Pin41Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin41Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin41Bpen::Bp + } +} +#[doc = "Field `PIN_41_BPEN` writer - LCD Pin 41 Back Plane Enable"] +pub type Pin41BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin41Bpen>; +impl<'a, REG> Pin41BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin41Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin41Bpen::Bp) + } +} +#[doc = "LCD Pin 42 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin42Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin42Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_42_BPEN` reader - LCD Pin 42 Back Plane Enable"] +pub type Pin42BpenR = crate::BitReader; +impl Pin42BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin42Bpen { + match self.bits { + false => Pin42Bpen::Fp, + true => Pin42Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin42Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin42Bpen::Bp + } +} +#[doc = "Field `PIN_42_BPEN` writer - LCD Pin 42 Back Plane Enable"] +pub type Pin42BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin42Bpen>; +impl<'a, REG> Pin42BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin42Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin42Bpen::Bp) + } +} +#[doc = "LCD Pin 43 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin43Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin43Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_43_BPEN` reader - LCD Pin 43 Back Plane Enable"] +pub type Pin43BpenR = crate::BitReader; +impl Pin43BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin43Bpen { + match self.bits { + false => Pin43Bpen::Fp, + true => Pin43Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin43Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin43Bpen::Bp + } +} +#[doc = "Field `PIN_43_BPEN` writer - LCD Pin 43 Back Plane Enable"] +pub type Pin43BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin43Bpen>; +impl<'a, REG> Pin43BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin43Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin43Bpen::Bp) + } +} +#[doc = "LCD Pin 44 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin44Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin44Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_44_BPEN` reader - LCD Pin 44 Back Plane Enable"] +pub type Pin44BpenR = crate::BitReader; +impl Pin44BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin44Bpen { + match self.bits { + false => Pin44Bpen::Fp, + true => Pin44Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin44Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin44Bpen::Bp + } +} +#[doc = "Field `PIN_44_BPEN` writer - LCD Pin 44 Back Plane Enable"] +pub type Pin44BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin44Bpen>; +impl<'a, REG> Pin44BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin44Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin44Bpen::Bp) + } +} +#[doc = "LCD Pin 45 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin45Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin45Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_45_BPEN` reader - LCD Pin 45 Back Plane Enable"] +pub type Pin45BpenR = crate::BitReader; +impl Pin45BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin45Bpen { + match self.bits { + false => Pin45Bpen::Fp, + true => Pin45Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin45Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin45Bpen::Bp + } +} +#[doc = "Field `PIN_45_BPEN` writer - LCD Pin 45 Back Plane Enable"] +pub type Pin45BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin45Bpen>; +impl<'a, REG> Pin45BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin45Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin45Bpen::Bp) + } +} +#[doc = "LCD Pin 46 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin46Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin46Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_46_BPEN` reader - LCD Pin 46 Back Plane Enable"] +pub type Pin46BpenR = crate::BitReader; +impl Pin46BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin46Bpen { + match self.bits { + false => Pin46Bpen::Fp, + true => Pin46Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin46Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin46Bpen::Bp + } +} +#[doc = "Field `PIN_46_BPEN` writer - LCD Pin 46 Back Plane Enable"] +pub type Pin46BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin46Bpen>; +impl<'a, REG> Pin46BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin46Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin46Bpen::Bp) + } +} +#[doc = "LCD Pin 47 Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin47Bpen { + #[doc = "0: Pin as front plane."] + Fp = 0, + #[doc = "1: Pin as back plane."] + Bp = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin47Bpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_47_BPEN` reader - LCD Pin 47 Back Plane Enable"] +pub type Pin47BpenR = crate::BitReader; +impl Pin47BpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin47Bpen { + match self.bits { + false => Pin47Bpen::Fp, + true => Pin47Bpen::Bp, + } + } + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn is_fp(&self) -> bool { + *self == Pin47Bpen::Fp + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn is_bp(&self) -> bool { + *self == Pin47Bpen::Bp + } +} +#[doc = "Field `PIN_47_BPEN` writer - LCD Pin 47 Back Plane Enable"] +pub type Pin47BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin47Bpen>; +impl<'a, REG> Pin47BpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin as front plane."] + #[inline(always)] + pub fn fp(self) -> &'a mut crate::W { + self.variant(Pin47Bpen::Fp) + } + #[doc = "Pin as back plane."] + #[inline(always)] + pub fn bp(self) -> &'a mut crate::W { + self.variant(Pin47Bpen::Bp) + } +} +impl R { + #[doc = "Bit 0 - LCD Pin 32 Back Plane Enable"] + #[inline(always)] + pub fn pin_32_bpen(&self) -> Pin32BpenR { + Pin32BpenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - LCD Pin 33 Back Plane Enable"] + #[inline(always)] + pub fn pin_33_bpen(&self) -> Pin33BpenR { + Pin33BpenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LCD Pin 34 Back Plane Enable"] + #[inline(always)] + pub fn pin_34_bpen(&self) -> Pin34BpenR { + Pin34BpenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - LCD Pin 35 Back Plane Enable"] + #[inline(always)] + pub fn pin_35_bpen(&self) -> Pin35BpenR { + Pin35BpenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - LCD Pin 36 Back Plane Enable"] + #[inline(always)] + pub fn pin_36_bpen(&self) -> Pin36BpenR { + Pin36BpenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - LCD Pin 37 Back Plane Enable"] + #[inline(always)] + pub fn pin_37_bpen(&self) -> Pin37BpenR { + Pin37BpenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - LCD Pin 38 Back Plane Enable"] + #[inline(always)] + pub fn pin_38_bpen(&self) -> Pin38BpenR { + Pin38BpenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - LCD Pin 39 Back Plane Enable"] + #[inline(always)] + pub fn pin_39_bpen(&self) -> Pin39BpenR { + Pin39BpenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - LCD Pin 40 Back Plane Enable"] + #[inline(always)] + pub fn pin_40_bpen(&self) -> Pin40BpenR { + Pin40BpenR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - LCD Pin 41 Back Plane Enable"] + #[inline(always)] + pub fn pin_41_bpen(&self) -> Pin41BpenR { + Pin41BpenR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - LCD Pin 42 Back Plane Enable"] + #[inline(always)] + pub fn pin_42_bpen(&self) -> Pin42BpenR { + Pin42BpenR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - LCD Pin 43 Back Plane Enable"] + #[inline(always)] + pub fn pin_43_bpen(&self) -> Pin43BpenR { + Pin43BpenR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - LCD Pin 44 Back Plane Enable"] + #[inline(always)] + pub fn pin_44_bpen(&self) -> Pin44BpenR { + Pin44BpenR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - LCD Pin 45 Back Plane Enable"] + #[inline(always)] + pub fn pin_45_bpen(&self) -> Pin45BpenR { + Pin45BpenR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - LCD Pin 46 Back Plane Enable"] + #[inline(always)] + pub fn pin_46_bpen(&self) -> Pin46BpenR { + Pin46BpenR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - LCD Pin 47 Back Plane Enable"] + #[inline(always)] + pub fn pin_47_bpen(&self) -> Pin47BpenR { + Pin47BpenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LCD Pin 32 Back Plane Enable"] + #[inline(always)] + pub fn pin_32_bpen(&mut self) -> Pin32BpenW { + Pin32BpenW::new(self, 0) + } + #[doc = "Bit 1 - LCD Pin 33 Back Plane Enable"] + #[inline(always)] + pub fn pin_33_bpen(&mut self) -> Pin33BpenW { + Pin33BpenW::new(self, 1) + } + #[doc = "Bit 2 - LCD Pin 34 Back Plane Enable"] + #[inline(always)] + pub fn pin_34_bpen(&mut self) -> Pin34BpenW { + Pin34BpenW::new(self, 2) + } + #[doc = "Bit 3 - LCD Pin 35 Back Plane Enable"] + #[inline(always)] + pub fn pin_35_bpen(&mut self) -> Pin35BpenW { + Pin35BpenW::new(self, 3) + } + #[doc = "Bit 4 - LCD Pin 36 Back Plane Enable"] + #[inline(always)] + pub fn pin_36_bpen(&mut self) -> Pin36BpenW { + Pin36BpenW::new(self, 4) + } + #[doc = "Bit 5 - LCD Pin 37 Back Plane Enable"] + #[inline(always)] + pub fn pin_37_bpen(&mut self) -> Pin37BpenW { + Pin37BpenW::new(self, 5) + } + #[doc = "Bit 6 - LCD Pin 38 Back Plane Enable"] + #[inline(always)] + pub fn pin_38_bpen(&mut self) -> Pin38BpenW { + Pin38BpenW::new(self, 6) + } + #[doc = "Bit 7 - LCD Pin 39 Back Plane Enable"] + #[inline(always)] + pub fn pin_39_bpen(&mut self) -> Pin39BpenW { + Pin39BpenW::new(self, 7) + } + #[doc = "Bit 8 - LCD Pin 40 Back Plane Enable"] + #[inline(always)] + pub fn pin_40_bpen(&mut self) -> Pin40BpenW { + Pin40BpenW::new(self, 8) + } + #[doc = "Bit 9 - LCD Pin 41 Back Plane Enable"] + #[inline(always)] + pub fn pin_41_bpen(&mut self) -> Pin41BpenW { + Pin41BpenW::new(self, 9) + } + #[doc = "Bit 10 - LCD Pin 42 Back Plane Enable"] + #[inline(always)] + pub fn pin_42_bpen(&mut self) -> Pin42BpenW { + Pin42BpenW::new(self, 10) + } + #[doc = "Bit 11 - LCD Pin 43 Back Plane Enable"] + #[inline(always)] + pub fn pin_43_bpen(&mut self) -> Pin43BpenW { + Pin43BpenW::new(self, 11) + } + #[doc = "Bit 12 - LCD Pin 44 Back Plane Enable"] + #[inline(always)] + pub fn pin_44_bpen(&mut self) -> Pin44BpenW { + Pin44BpenW::new(self, 12) + } + #[doc = "Bit 13 - LCD Pin 45 Back Plane Enable"] + #[inline(always)] + pub fn pin_45_bpen(&mut self) -> Pin45BpenW { + Pin45BpenW::new(self, 13) + } + #[doc = "Bit 14 - LCD Pin 46 Back Plane Enable"] + #[inline(always)] + pub fn pin_46_bpen(&mut self) -> Pin46BpenW { + Pin46BpenW::new(self, 14) + } + #[doc = "Bit 15 - LCD Pin 47 Back Plane Enable"] + #[inline(always)] + pub fn pin_47_bpen(&mut self) -> Pin47BpenW { + Pin47BpenW::new(self, 15) + } +} +#[doc = "LCD Back Plane Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdBpen1Spec; +impl crate::RegisterSpec for LcdBpen1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_bpen1::R`](R) reader structure"] +impl crate::Readable for LcdBpen1Spec {} +#[doc = "`write(|w| ..)` method takes [`lcd_bpen1::W`](W) writer structure"] +impl crate::Writable for LcdBpen1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCD_BPEN1 to value 0"] +impl crate::Resettable for LcdBpen1Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_fdcr.rs b/mcxa276-pac/src/slcd0/lcd_fdcr.rs new file mode 100644 index 000000000..7dcf5145c --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_fdcr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `LCD_FDCR` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_FDCR` writer"] +pub type W = crate::W; +#[doc = "Field `FDPINID` reader - Fault Detect Pin ID"] +pub type FdpinidR = crate::FieldReader; +#[doc = "Field `FDPINID` writer - Fault Detect Pin ID"] +pub type FdpinidW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Fault Detect Back Plane Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fdbpen { + #[doc = "0: Type of the selected pin under fault detect test is front plane."] + Front = 0, + #[doc = "1: Type of the selected pin under fault detect test is back plane."] + Back = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fdbpen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FDBPEN` reader - Fault Detect Back Plane Enable"] +pub type FdbpenR = crate::BitReader; +impl FdbpenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fdbpen { + match self.bits { + false => Fdbpen::Front, + true => Fdbpen::Back, + } + } + #[doc = "Type of the selected pin under fault detect test is front plane."] + #[inline(always)] + pub fn is_front(&self) -> bool { + *self == Fdbpen::Front + } + #[doc = "Type of the selected pin under fault detect test is back plane."] + #[inline(always)] + pub fn is_back(&self) -> bool { + *self == Fdbpen::Back + } +} +#[doc = "Field `FDBPEN` writer - Fault Detect Back Plane Enable"] +pub type FdbpenW<'a, REG> = crate::BitWriter<'a, REG, Fdbpen>; +impl<'a, REG> FdbpenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Type of the selected pin under fault detect test is front plane."] + #[inline(always)] + pub fn front(self) -> &'a mut crate::W { + self.variant(Fdbpen::Front) + } + #[doc = "Type of the selected pin under fault detect test is back plane."] + #[inline(always)] + pub fn back(self) -> &'a mut crate::W { + self.variant(Fdbpen::Back) + } +} +#[doc = "Fault Detect Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fden { + #[doc = "0: Disable fault detection."] + Disable = 0, + #[doc = "1: Enable fault detection."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fden) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FDEN` reader - Fault Detect Enable"] +pub type FdenR = crate::BitReader; +impl FdenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fden { + match self.bits { + false => Fden::Disable, + true => Fden::Enable, + } + } + #[doc = "Disable fault detection."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Fden::Disable + } + #[doc = "Enable fault detection."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Fden::Enable + } +} +#[doc = "Field `FDEN` writer - Fault Detect Enable"] +pub type FdenW<'a, REG> = crate::BitWriter<'a, REG, Fden>; +impl<'a, REG> FdenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable fault detection."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Fden::Disable) + } + #[doc = "Enable fault detection."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Fden::Enable) + } +} +#[doc = "Fault Detect Sample Window Width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fdsww { + #[doc = "0: Sample window width is 4 sample clock cycles."] + Sample4Cycles = 0, + #[doc = "1: Sample window width is 8 sample clock cycles."] + Sample8Cycles = 1, + #[doc = "2: Sample window width is 16 sample clock cycles."] + Sample16Cycles = 2, + #[doc = "3: Sample window width is 32 sample clock cycles."] + Sample32Cycles = 3, + #[doc = "4: Sample window width is 64 sample clock cycles."] + Sample64Cycles = 4, + #[doc = "5: Sample window width is 128 sample clock cycles."] + Sample128Cycles = 5, + #[doc = "6: Sample window width is 256 sample clock cycles."] + Sample256Cycles = 6, + #[doc = "7: Sample window width is 512 sample clock cycles."] + Sample512Cycles = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fdsww) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fdsww { + type Ux = u8; +} +impl crate::IsEnum for Fdsww {} +#[doc = "Field `FDSWW` reader - Fault Detect Sample Window Width"] +pub type FdswwR = crate::FieldReader; +impl FdswwR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fdsww { + match self.bits { + 0 => Fdsww::Sample4Cycles, + 1 => Fdsww::Sample8Cycles, + 2 => Fdsww::Sample16Cycles, + 3 => Fdsww::Sample32Cycles, + 4 => Fdsww::Sample64Cycles, + 5 => Fdsww::Sample128Cycles, + 6 => Fdsww::Sample256Cycles, + 7 => Fdsww::Sample512Cycles, + _ => unreachable!(), + } + } + #[doc = "Sample window width is 4 sample clock cycles."] + #[inline(always)] + pub fn is_sample_4_cycles(&self) -> bool { + *self == Fdsww::Sample4Cycles + } + #[doc = "Sample window width is 8 sample clock cycles."] + #[inline(always)] + pub fn is_sample_8_cycles(&self) -> bool { + *self == Fdsww::Sample8Cycles + } + #[doc = "Sample window width is 16 sample clock cycles."] + #[inline(always)] + pub fn is_sample_16_cycles(&self) -> bool { + *self == Fdsww::Sample16Cycles + } + #[doc = "Sample window width is 32 sample clock cycles."] + #[inline(always)] + pub fn is_sample_32_cycles(&self) -> bool { + *self == Fdsww::Sample32Cycles + } + #[doc = "Sample window width is 64 sample clock cycles."] + #[inline(always)] + pub fn is_sample_64_cycles(&self) -> bool { + *self == Fdsww::Sample64Cycles + } + #[doc = "Sample window width is 128 sample clock cycles."] + #[inline(always)] + pub fn is_sample_128_cycles(&self) -> bool { + *self == Fdsww::Sample128Cycles + } + #[doc = "Sample window width is 256 sample clock cycles."] + #[inline(always)] + pub fn is_sample_256_cycles(&self) -> bool { + *self == Fdsww::Sample256Cycles + } + #[doc = "Sample window width is 512 sample clock cycles."] + #[inline(always)] + pub fn is_sample_512_cycles(&self) -> bool { + *self == Fdsww::Sample512Cycles + } +} +#[doc = "Field `FDSWW` writer - Fault Detect Sample Window Width"] +pub type FdswwW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fdsww, crate::Safe>; +impl<'a, REG> FdswwW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Sample window width is 4 sample clock cycles."] + #[inline(always)] + pub fn sample_4_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample4Cycles) + } + #[doc = "Sample window width is 8 sample clock cycles."] + #[inline(always)] + pub fn sample_8_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample8Cycles) + } + #[doc = "Sample window width is 16 sample clock cycles."] + #[inline(always)] + pub fn sample_16_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample16Cycles) + } + #[doc = "Sample window width is 32 sample clock cycles."] + #[inline(always)] + pub fn sample_32_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample32Cycles) + } + #[doc = "Sample window width is 64 sample clock cycles."] + #[inline(always)] + pub fn sample_64_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample64Cycles) + } + #[doc = "Sample window width is 128 sample clock cycles."] + #[inline(always)] + pub fn sample_128_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample128Cycles) + } + #[doc = "Sample window width is 256 sample clock cycles."] + #[inline(always)] + pub fn sample_256_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample256Cycles) + } + #[doc = "Sample window width is 512 sample clock cycles."] + #[inline(always)] + pub fn sample_512_cycles(self) -> &'a mut crate::W { + self.variant(Fdsww::Sample512Cycles) + } +} +#[doc = "Fault Detect Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Fdprs { + #[doc = "0: 1/1 bus clock."] + Div1Bus = 0, + #[doc = "1: 1/2 bus clock."] + Div2Bus = 1, + #[doc = "2: 1/4 bus clock."] + Div4Bus = 2, + #[doc = "3: 1/8 bus clock."] + Div8Bus = 3, + #[doc = "4: 1/16 bus clock."] + Div16Bus = 4, + #[doc = "5: 1/32 bus clock."] + Div32Bus = 5, + #[doc = "6: 1/64 bus clock."] + Div64Bus = 6, + #[doc = "7: 1/128 bus clock."] + Div128Bus = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Fdprs) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Fdprs { + type Ux = u8; +} +impl crate::IsEnum for Fdprs {} +#[doc = "Field `FDPRS` reader - Fault Detect Clock Prescaler"] +pub type FdprsR = crate::FieldReader; +impl FdprsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fdprs { + match self.bits { + 0 => Fdprs::Div1Bus, + 1 => Fdprs::Div2Bus, + 2 => Fdprs::Div4Bus, + 3 => Fdprs::Div8Bus, + 4 => Fdprs::Div16Bus, + 5 => Fdprs::Div32Bus, + 6 => Fdprs::Div64Bus, + 7 => Fdprs::Div128Bus, + _ => unreachable!(), + } + } + #[doc = "1/1 bus clock."] + #[inline(always)] + pub fn is_div_1_bus(&self) -> bool { + *self == Fdprs::Div1Bus + } + #[doc = "1/2 bus clock."] + #[inline(always)] + pub fn is_div_2_bus(&self) -> bool { + *self == Fdprs::Div2Bus + } + #[doc = "1/4 bus clock."] + #[inline(always)] + pub fn is_div_4_bus(&self) -> bool { + *self == Fdprs::Div4Bus + } + #[doc = "1/8 bus clock."] + #[inline(always)] + pub fn is_div_8_bus(&self) -> bool { + *self == Fdprs::Div8Bus + } + #[doc = "1/16 bus clock."] + #[inline(always)] + pub fn is_div_16_bus(&self) -> bool { + *self == Fdprs::Div16Bus + } + #[doc = "1/32 bus clock."] + #[inline(always)] + pub fn is_div_32_bus(&self) -> bool { + *self == Fdprs::Div32Bus + } + #[doc = "1/64 bus clock."] + #[inline(always)] + pub fn is_div_64_bus(&self) -> bool { + *self == Fdprs::Div64Bus + } + #[doc = "1/128 bus clock."] + #[inline(always)] + pub fn is_div_128_bus(&self) -> bool { + *self == Fdprs::Div128Bus + } +} +#[doc = "Field `FDPRS` writer - Fault Detect Clock Prescaler"] +pub type FdprsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fdprs, crate::Safe>; +impl<'a, REG> FdprsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1/1 bus clock."] + #[inline(always)] + pub fn div_1_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div1Bus) + } + #[doc = "1/2 bus clock."] + #[inline(always)] + pub fn div_2_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div2Bus) + } + #[doc = "1/4 bus clock."] + #[inline(always)] + pub fn div_4_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div4Bus) + } + #[doc = "1/8 bus clock."] + #[inline(always)] + pub fn div_8_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div8Bus) + } + #[doc = "1/16 bus clock."] + #[inline(always)] + pub fn div_16_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div16Bus) + } + #[doc = "1/32 bus clock."] + #[inline(always)] + pub fn div_32_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div32Bus) + } + #[doc = "1/64 bus clock."] + #[inline(always)] + pub fn div_64_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div64Bus) + } + #[doc = "1/128 bus clock."] + #[inline(always)] + pub fn div_128_bus(self) -> &'a mut crate::W { + self.variant(Fdprs::Div128Bus) + } +} +impl R { + #[doc = "Bits 0:5 - Fault Detect Pin ID"] + #[inline(always)] + pub fn fdpinid(&self) -> FdpinidR { + FdpinidR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Fault Detect Back Plane Enable"] + #[inline(always)] + pub fn fdbpen(&self) -> FdbpenR { + FdbpenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Fault Detect Enable"] + #[inline(always)] + pub fn fden(&self) -> FdenR { + FdenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 9:11 - Fault Detect Sample Window Width"] + #[inline(always)] + pub fn fdsww(&self) -> FdswwR { + FdswwR::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Fault Detect Clock Prescaler"] + #[inline(always)] + pub fn fdprs(&self) -> FdprsR { + FdprsR::new(((self.bits >> 12) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Fault Detect Pin ID"] + #[inline(always)] + pub fn fdpinid(&mut self) -> FdpinidW { + FdpinidW::new(self, 0) + } + #[doc = "Bit 6 - Fault Detect Back Plane Enable"] + #[inline(always)] + pub fn fdbpen(&mut self) -> FdbpenW { + FdbpenW::new(self, 6) + } + #[doc = "Bit 7 - Fault Detect Enable"] + #[inline(always)] + pub fn fden(&mut self) -> FdenW { + FdenW::new(self, 7) + } + #[doc = "Bits 9:11 - Fault Detect Sample Window Width"] + #[inline(always)] + pub fn fdsww(&mut self) -> FdswwW { + FdswwW::new(self, 9) + } + #[doc = "Bits 12:14 - Fault Detect Clock Prescaler"] + #[inline(always)] + pub fn fdprs(&mut self) -> FdprsW { + FdprsW::new(self, 12) + } +} +#[doc = "LCD Fault Detect Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdFdcrSpec; +impl crate::RegisterSpec for LcdFdcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_fdcr::R`](R) reader structure"] +impl crate::Readable for LcdFdcrSpec {} +#[doc = "`write(|w| ..)` method takes [`lcd_fdcr::W`](W) writer structure"] +impl crate::Writable for LcdFdcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCD_FDCR to value 0"] +impl crate::Resettable for LcdFdcrSpec {} diff --git a/mcxa276-pac/src/slcd0/lcd_fdsr.rs b/mcxa276-pac/src/slcd0/lcd_fdsr.rs new file mode 100644 index 000000000..30edab7cd --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_fdsr.rs @@ -0,0 +1,92 @@ +#[doc = "Register `LCD_FDSR` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_FDSR` writer"] +pub type W = crate::W; +#[doc = "Field `FDCNT` reader - Fault Detect Counter"] +pub type FdcntR = crate::FieldReader; +#[doc = "Fault Detection Complete Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fdcf { + #[doc = "0: Fault detection is not completed."] + NotCompleted = 0, + #[doc = "1: Fault detection is completed."] + Completed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fdcf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FDCF` reader - Fault Detection Complete Flag"] +pub type FdcfR = crate::BitReader; +impl FdcfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fdcf { + match self.bits { + false => Fdcf::NotCompleted, + true => Fdcf::Completed, + } + } + #[doc = "Fault detection is not completed."] + #[inline(always)] + pub fn is_not_completed(&self) -> bool { + *self == Fdcf::NotCompleted + } + #[doc = "Fault detection is completed."] + #[inline(always)] + pub fn is_completed(&self) -> bool { + *self == Fdcf::Completed + } +} +#[doc = "Field `FDCF` writer - Fault Detection Complete Flag"] +pub type FdcfW<'a, REG> = crate::BitWriter1C<'a, REG, Fdcf>; +impl<'a, REG> FdcfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Fault detection is not completed."] + #[inline(always)] + pub fn not_completed(self) -> &'a mut crate::W { + self.variant(Fdcf::NotCompleted) + } + #[doc = "Fault detection is completed."] + #[inline(always)] + pub fn completed(self) -> &'a mut crate::W { + self.variant(Fdcf::Completed) + } +} +impl R { + #[doc = "Bits 0:7 - Fault Detect Counter"] + #[inline(always)] + pub fn fdcnt(&self) -> FdcntR { + FdcntR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 15 - Fault Detection Complete Flag"] + #[inline(always)] + pub fn fdcf(&self) -> FdcfR { + FdcfR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 15 - Fault Detection Complete Flag"] + #[inline(always)] + pub fn fdcf(&mut self) -> FdcfW { + FdcfW::new(self, 15) + } +} +#[doc = "LCD Fault Detect Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdFdsrSpec; +impl crate::RegisterSpec for LcdFdsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_fdsr::R`](R) reader structure"] +impl crate::Readable for LcdFdsrSpec {} +#[doc = "`write(|w| ..)` method takes [`lcd_fdsr::W`](W) writer structure"] +impl crate::Writable for LcdFdsrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000; +} +#[doc = "`reset()` method sets LCD_FDSR to value 0"] +impl crate::Resettable for LcdFdsrSpec {} diff --git a/mcxa276-pac/src/slcd0/lcd_gcr.rs b/mcxa276-pac/src/slcd0/lcd_gcr.rs new file mode 100644 index 000000000..68ae9f002 --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_gcr.rs @@ -0,0 +1,616 @@ +#[doc = "Register `LCD_GCR` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_GCR` writer"] +pub type W = crate::W; +#[doc = "LCD duty select\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Duty { + #[doc = "0: Use 1 BP (1/1 duty cycle)."] + Use1Bp = 0, + #[doc = "1: Use 2 BP (1/2 duty cycle)."] + Use2Bp = 1, + #[doc = "2: Use 3 BP (1/3 duty cycle)."] + Use3Bp = 2, + #[doc = "3: Use 4 BP (1/4 duty cycle).(Default)"] + Use4Bp = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Duty) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Duty { + type Ux = u8; +} +impl crate::IsEnum for Duty {} +#[doc = "Field `DUTY` reader - LCD duty select"] +pub type DutyR = crate::FieldReader; +impl DutyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Duty { + match self.bits { + 0 => Duty::Use1Bp, + 1 => Duty::Use2Bp, + 2 => Duty::Use3Bp, + 3 => Duty::Use4Bp, + _ => unreachable!(), + } + } + #[doc = "Use 1 BP (1/1 duty cycle)."] + #[inline(always)] + pub fn is_use_1_bp(&self) -> bool { + *self == Duty::Use1Bp + } + #[doc = "Use 2 BP (1/2 duty cycle)."] + #[inline(always)] + pub fn is_use_2_bp(&self) -> bool { + *self == Duty::Use2Bp + } + #[doc = "Use 3 BP (1/3 duty cycle)."] + #[inline(always)] + pub fn is_use_3_bp(&self) -> bool { + *self == Duty::Use3Bp + } + #[doc = "Use 4 BP (1/4 duty cycle).(Default)"] + #[inline(always)] + pub fn is_use_4_bp(&self) -> bool { + *self == Duty::Use4Bp + } +} +#[doc = "Field `DUTY` writer - LCD duty select"] +pub type DutyW<'a, REG> = crate::FieldWriter<'a, REG, 2, Duty, crate::Safe>; +impl<'a, REG> DutyW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Use 1 BP (1/1 duty cycle)."] + #[inline(always)] + pub fn use_1_bp(self) -> &'a mut crate::W { + self.variant(Duty::Use1Bp) + } + #[doc = "Use 2 BP (1/2 duty cycle)."] + #[inline(always)] + pub fn use_2_bp(self) -> &'a mut crate::W { + self.variant(Duty::Use2Bp) + } + #[doc = "Use 3 BP (1/3 duty cycle)."] + #[inline(always)] + pub fn use_3_bp(self) -> &'a mut crate::W { + self.variant(Duty::Use3Bp) + } + #[doc = "Use 4 BP (1/4 duty cycle).(Default)"] + #[inline(always)] + pub fn use_4_bp(self) -> &'a mut crate::W { + self.variant(Duty::Use4Bp) + } +} +#[doc = "Field `LCLK` reader - LCD Clock Prescaler"] +pub type LclkR = crate::FieldReader; +#[doc = "Field `LCLK` writer - LCD Clock Prescaler"] +pub type LclkW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "LCD Low Power Waveform\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lcdlp { + #[doc = "0: LCD driver drives standard waveforms."] + High = 0, + #[doc = "1: LCD driver drives low-power waveforms."] + Low = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lcdlp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LCDLP` reader - LCD Low Power Waveform"] +pub type LcdlpR = crate::BitReader; +impl LcdlpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lcdlp { + match self.bits { + false => Lcdlp::High, + true => Lcdlp::Low, + } + } + #[doc = "LCD driver drives standard waveforms."] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == Lcdlp::High + } + #[doc = "LCD driver drives low-power waveforms."] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == Lcdlp::Low + } +} +#[doc = "Field `LCDLP` writer - LCD Low Power Waveform"] +pub type LcdlpW<'a, REG> = crate::BitWriter<'a, REG, Lcdlp>; +impl<'a, REG> LcdlpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "LCD driver drives standard waveforms."] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(Lcdlp::High) + } + #[doc = "LCD driver drives low-power waveforms."] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(Lcdlp::Low) + } +} +#[doc = "Field `LCDEN` reader - LCD Driver Enable"] +pub type LcdenR = crate::BitReader; +#[doc = "Field `LCDEN` writer - LCD Driver Enable"] +pub type LcdenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "LCD Stop\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lcdstp { + #[doc = "0: Allows the LCD driver to continue running during Stop mode."] + Enable = 0, + #[doc = "1: Disables the LCD driver when MCU enters Stop mode."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lcdstp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LCDSTP` reader - LCD Stop"] +pub type LcdstpR = crate::BitReader; +impl LcdstpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lcdstp { + match self.bits { + false => Lcdstp::Enable, + true => Lcdstp::Disable, + } + } + #[doc = "Allows the LCD driver to continue running during Stop mode."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lcdstp::Enable + } + #[doc = "Disables the LCD driver when MCU enters Stop mode."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lcdstp::Disable + } +} +#[doc = "Field `LCDSTP` writer - LCD Stop"] +pub type LcdstpW<'a, REG> = crate::BitWriter<'a, REG, Lcdstp>; +impl<'a, REG> LcdstpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Allows the LCD driver to continue running during Stop mode."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lcdstp::Enable) + } + #[doc = "Disables the LCD driver when MCU enters Stop mode."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lcdstp::Disable) + } +} +#[doc = "LCD Doze enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lcddoze { + #[doc = "0: Allows the LCD driver to continue running during Doze mode."] + Enable = 0, + #[doc = "1: Disables the LCD driver when MCU enters Doze mode."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lcddoze) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LCDDOZE` reader - LCD Doze enable"] +pub type LcddozeR = crate::BitReader; +impl LcddozeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lcddoze { + match self.bits { + false => Lcddoze::Enable, + true => Lcddoze::Disable, + } + } + #[doc = "Allows the LCD driver to continue running during Doze mode."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lcddoze::Enable + } + #[doc = "Disables the LCD driver when MCU enters Doze mode."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lcddoze::Disable + } +} +#[doc = "Field `LCDDOZE` writer - LCD Doze enable"] +pub type LcddozeW<'a, REG> = crate::BitWriter<'a, REG, Lcddoze>; +impl<'a, REG> LcddozeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Allows the LCD driver to continue running during Doze mode."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lcddoze::Enable) + } + #[doc = "Disables the LCD driver when MCU enters Doze mode."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lcddoze::Disable) + } +} +#[doc = "LCD Fault Detection Complete Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fdcien { + #[doc = "0: No interrupt request is generated by this event."] + Disable = 0, + #[doc = "1: When a fault is detected and FDCF bit is set, this event causes an interrupt request."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fdcien) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FDCIEN` reader - LCD Fault Detection Complete Interrupt Enable"] +pub type FdcienR = crate::BitReader; +impl FdcienR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fdcien { + match self.bits { + false => Fdcien::Disable, + true => Fdcien::Enable, + } + } + #[doc = "No interrupt request is generated by this event."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Fdcien::Disable + } + #[doc = "When a fault is detected and FDCF bit is set, this event causes an interrupt request."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Fdcien::Enable + } +} +#[doc = "Field `FDCIEN` writer - LCD Fault Detection Complete Interrupt Enable"] +pub type FdcienW<'a, REG> = crate::BitWriter<'a, REG, Fdcien>; +impl<'a, REG> FdcienW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No interrupt request is generated by this event."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Fdcien::Disable) + } + #[doc = "When a fault is detected and FDCF bit is set, this event causes an interrupt request."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Fdcien::Enable) + } +} +#[doc = "LCD Frame Frequency Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lcdien { + #[doc = "0: No interrupt request is generated by this event."] + Disable = 0, + #[doc = "1: When LCDIF bit is set, this event causes an interrupt request."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lcdien) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LCDIEN` reader - LCD Frame Frequency Interrupt Enable"] +pub type LcdienR = crate::BitReader; +impl LcdienR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lcdien { + match self.bits { + false => Lcdien::Disable, + true => Lcdien::Enable, + } + } + #[doc = "No interrupt request is generated by this event."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lcdien::Disable + } + #[doc = "When LCDIF bit is set, this event causes an interrupt request."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lcdien::Enable + } +} +#[doc = "Field `LCDIEN` writer - LCD Frame Frequency Interrupt Enable"] +pub type LcdienW<'a, REG> = crate::BitWriter<'a, REG, Lcdien>; +impl<'a, REG> LcdienW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No interrupt request is generated by this event."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lcdien::Disable) + } + #[doc = "When LCDIF bit is set, this event causes an interrupt request."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lcdien::Enable) + } +} +#[doc = "Sample & Hold Cycle Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Shcycle { + #[doc = "0: Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period."] + Clk64 = 0, + #[doc = "1: Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period."] + Clk128 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Shcycle) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SHCYCLE` reader - Sample & Hold Cycle Select"] +pub type ShcycleR = crate::BitReader; +impl ShcycleR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Shcycle { + match self.bits { + false => Shcycle::Clk64, + true => Shcycle::Clk128, + } + } + #[doc = "Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period."] + #[inline(always)] + pub fn is_clk64(&self) -> bool { + *self == Shcycle::Clk64 + } + #[doc = "Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period."] + #[inline(always)] + pub fn is_clk128(&self) -> bool { + *self == Shcycle::Clk128 + } +} +#[doc = "Field `SHCYCLE` writer - Sample & Hold Cycle Select"] +pub type ShcycleW<'a, REG> = crate::BitWriter<'a, REG, Shcycle>; +impl<'a, REG> ShcycleW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period."] + #[inline(always)] + pub fn clk64(self) -> &'a mut crate::W { + self.variant(Shcycle::Clk64) + } + #[doc = "Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period."] + #[inline(always)] + pub fn clk128(self) -> &'a mut crate::W { + self.variant(Shcycle::Clk128) + } +} +#[doc = "Sample & Hold Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Shen { + #[doc = "0: Sample & hold is disabled."] + Disable = 0, + #[doc = "1: Sample & hold is enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Shen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SHEN` reader - Sample & Hold Mode Enable"] +pub type ShenR = crate::BitReader; +impl ShenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Shen { + match self.bits { + false => Shen::Disable, + true => Shen::Enable, + } + } + #[doc = "Sample & hold is disabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Shen::Disable + } + #[doc = "Sample & hold is enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Shen::Enable + } +} +#[doc = "Field `SHEN` writer - Sample & Hold Mode Enable"] +pub type ShenW<'a, REG> = crate::BitWriter<'a, REG, Shen>; +impl<'a, REG> ShenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Sample & hold is disabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Shen::Disable) + } + #[doc = "Sample & hold is enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Shen::Enable) + } +} +#[doc = "Field `VLL1TRIM` reader - Level 1 Voltage Trim"] +pub type Vll1trimR = crate::FieldReader; +#[doc = "Field `VLL1TRIM` writer - Level 1 Voltage Trim"] +pub type Vll1trimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `VLL2TRIM` reader - Level 2 Voltage Trim"] +pub type Vll2trimR = crate::FieldReader; +#[doc = "Field `VLL2TRIM` writer - Level 2 Voltage Trim"] +pub type Vll2trimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:1 - LCD duty select"] + #[inline(always)] + pub fn duty(&self) -> DutyR { + DutyR::new((self.bits & 3) as u8) + } + #[doc = "Bits 3:5 - LCD Clock Prescaler"] + #[inline(always)] + pub fn lclk(&self) -> LclkR { + LclkR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - LCD Low Power Waveform"] + #[inline(always)] + pub fn lcdlp(&self) -> LcdlpR { + LcdlpR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - LCD Driver Enable"] + #[inline(always)] + pub fn lcden(&self) -> LcdenR { + LcdenR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - LCD Stop"] + #[inline(always)] + pub fn lcdstp(&self) -> LcdstpR { + LcdstpR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - LCD Doze enable"] + #[inline(always)] + pub fn lcddoze(&self) -> LcddozeR { + LcddozeR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 14 - LCD Fault Detection Complete Interrupt Enable"] + #[inline(always)] + pub fn fdcien(&self) -> FdcienR { + FdcienR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - LCD Frame Frequency Interrupt Enable"] + #[inline(always)] + pub fn lcdien(&self) -> LcdienR { + LcdienR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Sample & Hold Cycle Select"] + #[inline(always)] + pub fn shcycle(&self) -> ShcycleR { + ShcycleR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 23 - Sample & Hold Mode Enable"] + #[inline(always)] + pub fn shen(&self) -> ShenR { + ShenR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:27 - Level 1 Voltage Trim"] + #[inline(always)] + pub fn vll1trim(&self) -> Vll1trimR { + Vll1trimR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Level 2 Voltage Trim"] + #[inline(always)] + pub fn vll2trim(&self) -> Vll2trimR { + Vll2trimR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - LCD duty select"] + #[inline(always)] + pub fn duty(&mut self) -> DutyW { + DutyW::new(self, 0) + } + #[doc = "Bits 3:5 - LCD Clock Prescaler"] + #[inline(always)] + pub fn lclk(&mut self) -> LclkW { + LclkW::new(self, 3) + } + #[doc = "Bit 6 - LCD Low Power Waveform"] + #[inline(always)] + pub fn lcdlp(&mut self) -> LcdlpW { + LcdlpW::new(self, 6) + } + #[doc = "Bit 7 - LCD Driver Enable"] + #[inline(always)] + pub fn lcden(&mut self) -> LcdenW { + LcdenW::new(self, 7) + } + #[doc = "Bit 8 - LCD Stop"] + #[inline(always)] + pub fn lcdstp(&mut self) -> LcdstpW { + LcdstpW::new(self, 8) + } + #[doc = "Bit 9 - LCD Doze enable"] + #[inline(always)] + pub fn lcddoze(&mut self) -> LcddozeW { + LcddozeW::new(self, 9) + } + #[doc = "Bit 14 - LCD Fault Detection Complete Interrupt Enable"] + #[inline(always)] + pub fn fdcien(&mut self) -> FdcienW { + FdcienW::new(self, 14) + } + #[doc = "Bit 15 - LCD Frame Frequency Interrupt Enable"] + #[inline(always)] + pub fn lcdien(&mut self) -> LcdienW { + LcdienW::new(self, 15) + } + #[doc = "Bit 16 - Sample & Hold Cycle Select"] + #[inline(always)] + pub fn shcycle(&mut self) -> ShcycleW { + ShcycleW::new(self, 16) + } + #[doc = "Bit 23 - Sample & Hold Mode Enable"] + #[inline(always)] + pub fn shen(&mut self) -> ShenW { + ShenW::new(self, 23) + } + #[doc = "Bits 24:27 - Level 1 Voltage Trim"] + #[inline(always)] + pub fn vll1trim(&mut self) -> Vll1trimW { + Vll1trimW::new(self, 24) + } + #[doc = "Bits 28:31 - Level 2 Voltage Trim"] + #[inline(always)] + pub fn vll2trim(&mut self) -> Vll2trimW { + Vll2trimW::new(self, 28) + } +} +#[doc = "LCD General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_gcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_gcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdGcrSpec; +impl crate::RegisterSpec for LcdGcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_gcr::R`](R) reader structure"] +impl crate::Readable for LcdGcrSpec {} +#[doc = "`write(|w| ..)` method takes [`lcd_gcr::W`](W) writer structure"] +impl crate::Writable for LcdGcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCD_GCR to value 0x03"] +impl crate::Resettable for LcdGcrSpec { + const RESET_VALUE: u32 = 0x03; +} diff --git a/mcxa276-pac/src/slcd0/lcd_pen0.rs b/mcxa276-pac/src/slcd0/lcd_pen0.rs new file mode 100644 index 000000000..adc747f39 --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_pen0.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `LCD_PEN0` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_PEN0` writer"] +pub type W = crate::W; +#[doc = "LCD Pin 0 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin0En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin0En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_0_EN` reader - LCD Pin 0 Enable"] +pub type Pin0EnR = crate::BitReader; +impl Pin0EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin0En { + match self.bits { + false => Pin0En::Disable, + true => Pin0En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin0En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin0En::Enable + } +} +#[doc = "Field `PIN_0_EN` writer - LCD Pin 0 Enable"] +pub type Pin0EnW<'a, REG> = crate::BitWriter<'a, REG, Pin0En>; +impl<'a, REG> Pin0EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin0En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin0En::Enable) + } +} +#[doc = "LCD Pin 1 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin1En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin1En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_1_EN` reader - LCD Pin 1 Enable"] +pub type Pin1EnR = crate::BitReader; +impl Pin1EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin1En { + match self.bits { + false => Pin1En::Disable, + true => Pin1En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin1En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin1En::Enable + } +} +#[doc = "Field `PIN_1_EN` writer - LCD Pin 1 Enable"] +pub type Pin1EnW<'a, REG> = crate::BitWriter<'a, REG, Pin1En>; +impl<'a, REG> Pin1EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin1En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin1En::Enable) + } +} +#[doc = "LCD Pin 2 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin2En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin2En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_2_EN` reader - LCD Pin 2 Enable"] +pub type Pin2EnR = crate::BitReader; +impl Pin2EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin2En { + match self.bits { + false => Pin2En::Disable, + true => Pin2En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin2En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin2En::Enable + } +} +#[doc = "Field `PIN_2_EN` writer - LCD Pin 2 Enable"] +pub type Pin2EnW<'a, REG> = crate::BitWriter<'a, REG, Pin2En>; +impl<'a, REG> Pin2EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin2En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin2En::Enable) + } +} +#[doc = "LCD Pin 3 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin3En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin3En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_3_EN` reader - LCD Pin 3 Enable"] +pub type Pin3EnR = crate::BitReader; +impl Pin3EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin3En { + match self.bits { + false => Pin3En::Disable, + true => Pin3En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin3En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin3En::Enable + } +} +#[doc = "Field `PIN_3_EN` writer - LCD Pin 3 Enable"] +pub type Pin3EnW<'a, REG> = crate::BitWriter<'a, REG, Pin3En>; +impl<'a, REG> Pin3EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin3En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin3En::Enable) + } +} +#[doc = "LCD Pin 4 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin4En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin4En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_4_EN` reader - LCD Pin 4 Enable"] +pub type Pin4EnR = crate::BitReader; +impl Pin4EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin4En { + match self.bits { + false => Pin4En::Disable, + true => Pin4En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin4En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin4En::Enable + } +} +#[doc = "Field `PIN_4_EN` writer - LCD Pin 4 Enable"] +pub type Pin4EnW<'a, REG> = crate::BitWriter<'a, REG, Pin4En>; +impl<'a, REG> Pin4EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin4En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin4En::Enable) + } +} +#[doc = "LCD Pin 5 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin5En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin5En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_5_EN` reader - LCD Pin 5 Enable"] +pub type Pin5EnR = crate::BitReader; +impl Pin5EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin5En { + match self.bits { + false => Pin5En::Disable, + true => Pin5En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin5En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin5En::Enable + } +} +#[doc = "Field `PIN_5_EN` writer - LCD Pin 5 Enable"] +pub type Pin5EnW<'a, REG> = crate::BitWriter<'a, REG, Pin5En>; +impl<'a, REG> Pin5EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin5En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin5En::Enable) + } +} +#[doc = "LCD Pin 6 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin6En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin6En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_6_EN` reader - LCD Pin 6 Enable"] +pub type Pin6EnR = crate::BitReader; +impl Pin6EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin6En { + match self.bits { + false => Pin6En::Disable, + true => Pin6En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin6En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin6En::Enable + } +} +#[doc = "Field `PIN_6_EN` writer - LCD Pin 6 Enable"] +pub type Pin6EnW<'a, REG> = crate::BitWriter<'a, REG, Pin6En>; +impl<'a, REG> Pin6EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin6En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin6En::Enable) + } +} +#[doc = "LCD Pin 7 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin7En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin7En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_7_EN` reader - LCD Pin 7 Enable"] +pub type Pin7EnR = crate::BitReader; +impl Pin7EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin7En { + match self.bits { + false => Pin7En::Disable, + true => Pin7En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin7En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin7En::Enable + } +} +#[doc = "Field `PIN_7_EN` writer - LCD Pin 7 Enable"] +pub type Pin7EnW<'a, REG> = crate::BitWriter<'a, REG, Pin7En>; +impl<'a, REG> Pin7EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin7En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin7En::Enable) + } +} +#[doc = "LCD Pin 8 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin8En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin8En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_8_EN` reader - LCD Pin 8 Enable"] +pub type Pin8EnR = crate::BitReader; +impl Pin8EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin8En { + match self.bits { + false => Pin8En::Disable, + true => Pin8En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin8En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin8En::Enable + } +} +#[doc = "Field `PIN_8_EN` writer - LCD Pin 8 Enable"] +pub type Pin8EnW<'a, REG> = crate::BitWriter<'a, REG, Pin8En>; +impl<'a, REG> Pin8EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin8En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin8En::Enable) + } +} +#[doc = "LCD Pin 9 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin9En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin9En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_9_EN` reader - LCD Pin 9 Enable"] +pub type Pin9EnR = crate::BitReader; +impl Pin9EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin9En { + match self.bits { + false => Pin9En::Disable, + true => Pin9En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin9En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin9En::Enable + } +} +#[doc = "Field `PIN_9_EN` writer - LCD Pin 9 Enable"] +pub type Pin9EnW<'a, REG> = crate::BitWriter<'a, REG, Pin9En>; +impl<'a, REG> Pin9EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin9En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin9En::Enable) + } +} +#[doc = "LCD Pin 10 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin10En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin10En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_10_EN` reader - LCD Pin 10 Enable"] +pub type Pin10EnR = crate::BitReader; +impl Pin10EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin10En { + match self.bits { + false => Pin10En::Disable, + true => Pin10En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin10En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin10En::Enable + } +} +#[doc = "Field `PIN_10_EN` writer - LCD Pin 10 Enable"] +pub type Pin10EnW<'a, REG> = crate::BitWriter<'a, REG, Pin10En>; +impl<'a, REG> Pin10EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin10En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin10En::Enable) + } +} +#[doc = "LCD Pin 11 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin11En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin11En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_11_EN` reader - LCD Pin 11 Enable"] +pub type Pin11EnR = crate::BitReader; +impl Pin11EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin11En { + match self.bits { + false => Pin11En::Disable, + true => Pin11En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin11En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin11En::Enable + } +} +#[doc = "Field `PIN_11_EN` writer - LCD Pin 11 Enable"] +pub type Pin11EnW<'a, REG> = crate::BitWriter<'a, REG, Pin11En>; +impl<'a, REG> Pin11EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin11En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin11En::Enable) + } +} +#[doc = "LCD Pin 12 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin12En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin12En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_12_EN` reader - LCD Pin 12 Enable"] +pub type Pin12EnR = crate::BitReader; +impl Pin12EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin12En { + match self.bits { + false => Pin12En::Disable, + true => Pin12En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin12En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin12En::Enable + } +} +#[doc = "Field `PIN_12_EN` writer - LCD Pin 12 Enable"] +pub type Pin12EnW<'a, REG> = crate::BitWriter<'a, REG, Pin12En>; +impl<'a, REG> Pin12EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin12En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin12En::Enable) + } +} +#[doc = "LCD Pin 13 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin13En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin13En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_13_EN` reader - LCD Pin 13 Enable"] +pub type Pin13EnR = crate::BitReader; +impl Pin13EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin13En { + match self.bits { + false => Pin13En::Disable, + true => Pin13En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin13En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin13En::Enable + } +} +#[doc = "Field `PIN_13_EN` writer - LCD Pin 13 Enable"] +pub type Pin13EnW<'a, REG> = crate::BitWriter<'a, REG, Pin13En>; +impl<'a, REG> Pin13EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin13En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin13En::Enable) + } +} +#[doc = "LCD Pin 14 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin14En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin14En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_14_EN` reader - LCD Pin 14 Enable"] +pub type Pin14EnR = crate::BitReader; +impl Pin14EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin14En { + match self.bits { + false => Pin14En::Disable, + true => Pin14En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin14En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin14En::Enable + } +} +#[doc = "Field `PIN_14_EN` writer - LCD Pin 14 Enable"] +pub type Pin14EnW<'a, REG> = crate::BitWriter<'a, REG, Pin14En>; +impl<'a, REG> Pin14EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin14En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin14En::Enable) + } +} +#[doc = "LCD Pin 15 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin15En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin15En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_15_EN` reader - LCD Pin 15 Enable"] +pub type Pin15EnR = crate::BitReader; +impl Pin15EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin15En { + match self.bits { + false => Pin15En::Disable, + true => Pin15En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin15En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin15En::Enable + } +} +#[doc = "Field `PIN_15_EN` writer - LCD Pin 15 Enable"] +pub type Pin15EnW<'a, REG> = crate::BitWriter<'a, REG, Pin15En>; +impl<'a, REG> Pin15EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin15En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin15En::Enable) + } +} +#[doc = "LCD Pin 16 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin16En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin16En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_16_EN` reader - LCD Pin 16 Enable"] +pub type Pin16EnR = crate::BitReader; +impl Pin16EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin16En { + match self.bits { + false => Pin16En::Disable, + true => Pin16En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin16En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin16En::Enable + } +} +#[doc = "Field `PIN_16_EN` writer - LCD Pin 16 Enable"] +pub type Pin16EnW<'a, REG> = crate::BitWriter<'a, REG, Pin16En>; +impl<'a, REG> Pin16EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin16En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin16En::Enable) + } +} +#[doc = "LCD Pin 17 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin17En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin17En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_17_EN` reader - LCD Pin 17 Enable"] +pub type Pin17EnR = crate::BitReader; +impl Pin17EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin17En { + match self.bits { + false => Pin17En::Disable, + true => Pin17En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin17En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin17En::Enable + } +} +#[doc = "Field `PIN_17_EN` writer - LCD Pin 17 Enable"] +pub type Pin17EnW<'a, REG> = crate::BitWriter<'a, REG, Pin17En>; +impl<'a, REG> Pin17EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin17En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin17En::Enable) + } +} +#[doc = "LCD Pin 18 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin18En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin18En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_18_EN` reader - LCD Pin 18 Enable"] +pub type Pin18EnR = crate::BitReader; +impl Pin18EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin18En { + match self.bits { + false => Pin18En::Disable, + true => Pin18En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin18En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin18En::Enable + } +} +#[doc = "Field `PIN_18_EN` writer - LCD Pin 18 Enable"] +pub type Pin18EnW<'a, REG> = crate::BitWriter<'a, REG, Pin18En>; +impl<'a, REG> Pin18EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin18En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin18En::Enable) + } +} +#[doc = "LCD Pin 19 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin19En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin19En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_19_EN` reader - LCD Pin 19 Enable"] +pub type Pin19EnR = crate::BitReader; +impl Pin19EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin19En { + match self.bits { + false => Pin19En::Disable, + true => Pin19En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin19En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin19En::Enable + } +} +#[doc = "Field `PIN_19_EN` writer - LCD Pin 19 Enable"] +pub type Pin19EnW<'a, REG> = crate::BitWriter<'a, REG, Pin19En>; +impl<'a, REG> Pin19EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin19En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin19En::Enable) + } +} +#[doc = "LCD Pin 20 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin20En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin20En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_20_EN` reader - LCD Pin 20 Enable"] +pub type Pin20EnR = crate::BitReader; +impl Pin20EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin20En { + match self.bits { + false => Pin20En::Disable, + true => Pin20En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin20En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin20En::Enable + } +} +#[doc = "Field `PIN_20_EN` writer - LCD Pin 20 Enable"] +pub type Pin20EnW<'a, REG> = crate::BitWriter<'a, REG, Pin20En>; +impl<'a, REG> Pin20EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin20En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin20En::Enable) + } +} +#[doc = "LCD Pin 21 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin21En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin21En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_21_EN` reader - LCD Pin 21 Enable"] +pub type Pin21EnR = crate::BitReader; +impl Pin21EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin21En { + match self.bits { + false => Pin21En::Disable, + true => Pin21En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin21En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin21En::Enable + } +} +#[doc = "Field `PIN_21_EN` writer - LCD Pin 21 Enable"] +pub type Pin21EnW<'a, REG> = crate::BitWriter<'a, REG, Pin21En>; +impl<'a, REG> Pin21EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin21En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin21En::Enable) + } +} +#[doc = "LCD Pin 22 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin22En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin22En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_22_EN` reader - LCD Pin 22 Enable"] +pub type Pin22EnR = crate::BitReader; +impl Pin22EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin22En { + match self.bits { + false => Pin22En::Disable, + true => Pin22En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin22En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin22En::Enable + } +} +#[doc = "Field `PIN_22_EN` writer - LCD Pin 22 Enable"] +pub type Pin22EnW<'a, REG> = crate::BitWriter<'a, REG, Pin22En>; +impl<'a, REG> Pin22EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin22En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin22En::Enable) + } +} +#[doc = "LCD Pin 23 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin23En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin23En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_23_EN` reader - LCD Pin 23 Enable"] +pub type Pin23EnR = crate::BitReader; +impl Pin23EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin23En { + match self.bits { + false => Pin23En::Disable, + true => Pin23En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin23En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin23En::Enable + } +} +#[doc = "Field `PIN_23_EN` writer - LCD Pin 23 Enable"] +pub type Pin23EnW<'a, REG> = crate::BitWriter<'a, REG, Pin23En>; +impl<'a, REG> Pin23EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin23En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin23En::Enable) + } +} +#[doc = "LCD Pin 24 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin24En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin24En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_24_EN` reader - LCD Pin 24 Enable"] +pub type Pin24EnR = crate::BitReader; +impl Pin24EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin24En { + match self.bits { + false => Pin24En::Disable, + true => Pin24En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin24En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin24En::Enable + } +} +#[doc = "Field `PIN_24_EN` writer - LCD Pin 24 Enable"] +pub type Pin24EnW<'a, REG> = crate::BitWriter<'a, REG, Pin24En>; +impl<'a, REG> Pin24EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin24En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin24En::Enable) + } +} +#[doc = "LCD Pin 25 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin25En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin25En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_25_EN` reader - LCD Pin 25 Enable"] +pub type Pin25EnR = crate::BitReader; +impl Pin25EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin25En { + match self.bits { + false => Pin25En::Disable, + true => Pin25En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin25En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin25En::Enable + } +} +#[doc = "Field `PIN_25_EN` writer - LCD Pin 25 Enable"] +pub type Pin25EnW<'a, REG> = crate::BitWriter<'a, REG, Pin25En>; +impl<'a, REG> Pin25EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin25En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin25En::Enable) + } +} +#[doc = "LCD Pin 26 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin26En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin26En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_26_EN` reader - LCD Pin 26 Enable"] +pub type Pin26EnR = crate::BitReader; +impl Pin26EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin26En { + match self.bits { + false => Pin26En::Disable, + true => Pin26En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin26En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin26En::Enable + } +} +#[doc = "Field `PIN_26_EN` writer - LCD Pin 26 Enable"] +pub type Pin26EnW<'a, REG> = crate::BitWriter<'a, REG, Pin26En>; +impl<'a, REG> Pin26EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin26En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin26En::Enable) + } +} +#[doc = "LCD Pin 27 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin27En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin27En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_27_EN` reader - LCD Pin 27 Enable"] +pub type Pin27EnR = crate::BitReader; +impl Pin27EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin27En { + match self.bits { + false => Pin27En::Disable, + true => Pin27En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin27En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin27En::Enable + } +} +#[doc = "Field `PIN_27_EN` writer - LCD Pin 27 Enable"] +pub type Pin27EnW<'a, REG> = crate::BitWriter<'a, REG, Pin27En>; +impl<'a, REG> Pin27EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin27En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin27En::Enable) + } +} +#[doc = "LCD Pin 28 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin28En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin28En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_28_EN` reader - LCD Pin 28 Enable"] +pub type Pin28EnR = crate::BitReader; +impl Pin28EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin28En { + match self.bits { + false => Pin28En::Disable, + true => Pin28En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin28En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin28En::Enable + } +} +#[doc = "Field `PIN_28_EN` writer - LCD Pin 28 Enable"] +pub type Pin28EnW<'a, REG> = crate::BitWriter<'a, REG, Pin28En>; +impl<'a, REG> Pin28EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin28En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin28En::Enable) + } +} +#[doc = "LCD Pin 29 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin29En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin29En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_29_EN` reader - LCD Pin 29 Enable"] +pub type Pin29EnR = crate::BitReader; +impl Pin29EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin29En { + match self.bits { + false => Pin29En::Disable, + true => Pin29En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin29En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin29En::Enable + } +} +#[doc = "Field `PIN_29_EN` writer - LCD Pin 29 Enable"] +pub type Pin29EnW<'a, REG> = crate::BitWriter<'a, REG, Pin29En>; +impl<'a, REG> Pin29EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin29En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin29En::Enable) + } +} +#[doc = "LCD Pin 30 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin30En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin30En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_30_EN` reader - LCD Pin 30 Enable"] +pub type Pin30EnR = crate::BitReader; +impl Pin30EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin30En { + match self.bits { + false => Pin30En::Disable, + true => Pin30En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin30En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin30En::Enable + } +} +#[doc = "Field `PIN_30_EN` writer - LCD Pin 30 Enable"] +pub type Pin30EnW<'a, REG> = crate::BitWriter<'a, REG, Pin30En>; +impl<'a, REG> Pin30EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin30En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin30En::Enable) + } +} +#[doc = "LCD Pin 31 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin31En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin31En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_31_EN` reader - LCD Pin 31 Enable"] +pub type Pin31EnR = crate::BitReader; +impl Pin31EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin31En { + match self.bits { + false => Pin31En::Disable, + true => Pin31En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin31En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin31En::Enable + } +} +#[doc = "Field `PIN_31_EN` writer - LCD Pin 31 Enable"] +pub type Pin31EnW<'a, REG> = crate::BitWriter<'a, REG, Pin31En>; +impl<'a, REG> Pin31EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin31En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin31En::Enable) + } +} +impl R { + #[doc = "Bit 0 - LCD Pin 0 Enable"] + #[inline(always)] + pub fn pin_0_en(&self) -> Pin0EnR { + Pin0EnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - LCD Pin 1 Enable"] + #[inline(always)] + pub fn pin_1_en(&self) -> Pin1EnR { + Pin1EnR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LCD Pin 2 Enable"] + #[inline(always)] + pub fn pin_2_en(&self) -> Pin2EnR { + Pin2EnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - LCD Pin 3 Enable"] + #[inline(always)] + pub fn pin_3_en(&self) -> Pin3EnR { + Pin3EnR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - LCD Pin 4 Enable"] + #[inline(always)] + pub fn pin_4_en(&self) -> Pin4EnR { + Pin4EnR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - LCD Pin 5 Enable"] + #[inline(always)] + pub fn pin_5_en(&self) -> Pin5EnR { + Pin5EnR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - LCD Pin 6 Enable"] + #[inline(always)] + pub fn pin_6_en(&self) -> Pin6EnR { + Pin6EnR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - LCD Pin 7 Enable"] + #[inline(always)] + pub fn pin_7_en(&self) -> Pin7EnR { + Pin7EnR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - LCD Pin 8 Enable"] + #[inline(always)] + pub fn pin_8_en(&self) -> Pin8EnR { + Pin8EnR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - LCD Pin 9 Enable"] + #[inline(always)] + pub fn pin_9_en(&self) -> Pin9EnR { + Pin9EnR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - LCD Pin 10 Enable"] + #[inline(always)] + pub fn pin_10_en(&self) -> Pin10EnR { + Pin10EnR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - LCD Pin 11 Enable"] + #[inline(always)] + pub fn pin_11_en(&self) -> Pin11EnR { + Pin11EnR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - LCD Pin 12 Enable"] + #[inline(always)] + pub fn pin_12_en(&self) -> Pin12EnR { + Pin12EnR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - LCD Pin 13 Enable"] + #[inline(always)] + pub fn pin_13_en(&self) -> Pin13EnR { + Pin13EnR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - LCD Pin 14 Enable"] + #[inline(always)] + pub fn pin_14_en(&self) -> Pin14EnR { + Pin14EnR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - LCD Pin 15 Enable"] + #[inline(always)] + pub fn pin_15_en(&self) -> Pin15EnR { + Pin15EnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - LCD Pin 16 Enable"] + #[inline(always)] + pub fn pin_16_en(&self) -> Pin16EnR { + Pin16EnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - LCD Pin 17 Enable"] + #[inline(always)] + pub fn pin_17_en(&self) -> Pin17EnR { + Pin17EnR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - LCD Pin 18 Enable"] + #[inline(always)] + pub fn pin_18_en(&self) -> Pin18EnR { + Pin18EnR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - LCD Pin 19 Enable"] + #[inline(always)] + pub fn pin_19_en(&self) -> Pin19EnR { + Pin19EnR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - LCD Pin 20 Enable"] + #[inline(always)] + pub fn pin_20_en(&self) -> Pin20EnR { + Pin20EnR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - LCD Pin 21 Enable"] + #[inline(always)] + pub fn pin_21_en(&self) -> Pin21EnR { + Pin21EnR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - LCD Pin 22 Enable"] + #[inline(always)] + pub fn pin_22_en(&self) -> Pin22EnR { + Pin22EnR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - LCD Pin 23 Enable"] + #[inline(always)] + pub fn pin_23_en(&self) -> Pin23EnR { + Pin23EnR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - LCD Pin 24 Enable"] + #[inline(always)] + pub fn pin_24_en(&self) -> Pin24EnR { + Pin24EnR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - LCD Pin 25 Enable"] + #[inline(always)] + pub fn pin_25_en(&self) -> Pin25EnR { + Pin25EnR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - LCD Pin 26 Enable"] + #[inline(always)] + pub fn pin_26_en(&self) -> Pin26EnR { + Pin26EnR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LCD Pin 27 Enable"] + #[inline(always)] + pub fn pin_27_en(&self) -> Pin27EnR { + Pin27EnR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - LCD Pin 28 Enable"] + #[inline(always)] + pub fn pin_28_en(&self) -> Pin28EnR { + Pin28EnR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - LCD Pin 29 Enable"] + #[inline(always)] + pub fn pin_29_en(&self) -> Pin29EnR { + Pin29EnR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - LCD Pin 30 Enable"] + #[inline(always)] + pub fn pin_30_en(&self) -> Pin30EnR { + Pin30EnR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - LCD Pin 31 Enable"] + #[inline(always)] + pub fn pin_31_en(&self) -> Pin31EnR { + Pin31EnR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LCD Pin 0 Enable"] + #[inline(always)] + pub fn pin_0_en(&mut self) -> Pin0EnW { + Pin0EnW::new(self, 0) + } + #[doc = "Bit 1 - LCD Pin 1 Enable"] + #[inline(always)] + pub fn pin_1_en(&mut self) -> Pin1EnW { + Pin1EnW::new(self, 1) + } + #[doc = "Bit 2 - LCD Pin 2 Enable"] + #[inline(always)] + pub fn pin_2_en(&mut self) -> Pin2EnW { + Pin2EnW::new(self, 2) + } + #[doc = "Bit 3 - LCD Pin 3 Enable"] + #[inline(always)] + pub fn pin_3_en(&mut self) -> Pin3EnW { + Pin3EnW::new(self, 3) + } + #[doc = "Bit 4 - LCD Pin 4 Enable"] + #[inline(always)] + pub fn pin_4_en(&mut self) -> Pin4EnW { + Pin4EnW::new(self, 4) + } + #[doc = "Bit 5 - LCD Pin 5 Enable"] + #[inline(always)] + pub fn pin_5_en(&mut self) -> Pin5EnW { + Pin5EnW::new(self, 5) + } + #[doc = "Bit 6 - LCD Pin 6 Enable"] + #[inline(always)] + pub fn pin_6_en(&mut self) -> Pin6EnW { + Pin6EnW::new(self, 6) + } + #[doc = "Bit 7 - LCD Pin 7 Enable"] + #[inline(always)] + pub fn pin_7_en(&mut self) -> Pin7EnW { + Pin7EnW::new(self, 7) + } + #[doc = "Bit 8 - LCD Pin 8 Enable"] + #[inline(always)] + pub fn pin_8_en(&mut self) -> Pin8EnW { + Pin8EnW::new(self, 8) + } + #[doc = "Bit 9 - LCD Pin 9 Enable"] + #[inline(always)] + pub fn pin_9_en(&mut self) -> Pin9EnW { + Pin9EnW::new(self, 9) + } + #[doc = "Bit 10 - LCD Pin 10 Enable"] + #[inline(always)] + pub fn pin_10_en(&mut self) -> Pin10EnW { + Pin10EnW::new(self, 10) + } + #[doc = "Bit 11 - LCD Pin 11 Enable"] + #[inline(always)] + pub fn pin_11_en(&mut self) -> Pin11EnW { + Pin11EnW::new(self, 11) + } + #[doc = "Bit 12 - LCD Pin 12 Enable"] + #[inline(always)] + pub fn pin_12_en(&mut self) -> Pin12EnW { + Pin12EnW::new(self, 12) + } + #[doc = "Bit 13 - LCD Pin 13 Enable"] + #[inline(always)] + pub fn pin_13_en(&mut self) -> Pin13EnW { + Pin13EnW::new(self, 13) + } + #[doc = "Bit 14 - LCD Pin 14 Enable"] + #[inline(always)] + pub fn pin_14_en(&mut self) -> Pin14EnW { + Pin14EnW::new(self, 14) + } + #[doc = "Bit 15 - LCD Pin 15 Enable"] + #[inline(always)] + pub fn pin_15_en(&mut self) -> Pin15EnW { + Pin15EnW::new(self, 15) + } + #[doc = "Bit 16 - LCD Pin 16 Enable"] + #[inline(always)] + pub fn pin_16_en(&mut self) -> Pin16EnW { + Pin16EnW::new(self, 16) + } + #[doc = "Bit 17 - LCD Pin 17 Enable"] + #[inline(always)] + pub fn pin_17_en(&mut self) -> Pin17EnW { + Pin17EnW::new(self, 17) + } + #[doc = "Bit 18 - LCD Pin 18 Enable"] + #[inline(always)] + pub fn pin_18_en(&mut self) -> Pin18EnW { + Pin18EnW::new(self, 18) + } + #[doc = "Bit 19 - LCD Pin 19 Enable"] + #[inline(always)] + pub fn pin_19_en(&mut self) -> Pin19EnW { + Pin19EnW::new(self, 19) + } + #[doc = "Bit 20 - LCD Pin 20 Enable"] + #[inline(always)] + pub fn pin_20_en(&mut self) -> Pin20EnW { + Pin20EnW::new(self, 20) + } + #[doc = "Bit 21 - LCD Pin 21 Enable"] + #[inline(always)] + pub fn pin_21_en(&mut self) -> Pin21EnW { + Pin21EnW::new(self, 21) + } + #[doc = "Bit 22 - LCD Pin 22 Enable"] + #[inline(always)] + pub fn pin_22_en(&mut self) -> Pin22EnW { + Pin22EnW::new(self, 22) + } + #[doc = "Bit 23 - LCD Pin 23 Enable"] + #[inline(always)] + pub fn pin_23_en(&mut self) -> Pin23EnW { + Pin23EnW::new(self, 23) + } + #[doc = "Bit 24 - LCD Pin 24 Enable"] + #[inline(always)] + pub fn pin_24_en(&mut self) -> Pin24EnW { + Pin24EnW::new(self, 24) + } + #[doc = "Bit 25 - LCD Pin 25 Enable"] + #[inline(always)] + pub fn pin_25_en(&mut self) -> Pin25EnW { + Pin25EnW::new(self, 25) + } + #[doc = "Bit 26 - LCD Pin 26 Enable"] + #[inline(always)] + pub fn pin_26_en(&mut self) -> Pin26EnW { + Pin26EnW::new(self, 26) + } + #[doc = "Bit 27 - LCD Pin 27 Enable"] + #[inline(always)] + pub fn pin_27_en(&mut self) -> Pin27EnW { + Pin27EnW::new(self, 27) + } + #[doc = "Bit 28 - LCD Pin 28 Enable"] + #[inline(always)] + pub fn pin_28_en(&mut self) -> Pin28EnW { + Pin28EnW::new(self, 28) + } + #[doc = "Bit 29 - LCD Pin 29 Enable"] + #[inline(always)] + pub fn pin_29_en(&mut self) -> Pin29EnW { + Pin29EnW::new(self, 29) + } + #[doc = "Bit 30 - LCD Pin 30 Enable"] + #[inline(always)] + pub fn pin_30_en(&mut self) -> Pin30EnW { + Pin30EnW::new(self, 30) + } + #[doc = "Bit 31 - LCD Pin 31 Enable"] + #[inline(always)] + pub fn pin_31_en(&mut self) -> Pin31EnW { + Pin31EnW::new(self, 31) + } +} +#[doc = "LCD Pin Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdPen0Spec; +impl crate::RegisterSpec for LcdPen0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_pen0::R`](R) reader structure"] +impl crate::Readable for LcdPen0Spec {} +#[doc = "`write(|w| ..)` method takes [`lcd_pen0::W`](W) writer structure"] +impl crate::Writable for LcdPen0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCD_PEN0 to value 0"] +impl crate::Resettable for LcdPen0Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_pen1.rs b/mcxa276-pac/src/slcd0/lcd_pen1.rs new file mode 100644 index 000000000..230e1df46 --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_pen1.rs @@ -0,0 +1,1029 @@ +#[doc = "Register `LCD_PEN1` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_PEN1` writer"] +pub type W = crate::W; +#[doc = "LCD Pin 32 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin32En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin32En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_32_EN` reader - LCD Pin 32 Enable"] +pub type Pin32EnR = crate::BitReader; +impl Pin32EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin32En { + match self.bits { + false => Pin32En::Disable, + true => Pin32En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin32En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin32En::Enable + } +} +#[doc = "Field `PIN_32_EN` writer - LCD Pin 32 Enable"] +pub type Pin32EnW<'a, REG> = crate::BitWriter<'a, REG, Pin32En>; +impl<'a, REG> Pin32EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin32En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin32En::Enable) + } +} +#[doc = "LCD Pin 33 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin33En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin33En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_33_EN` reader - LCD Pin 33 Enable"] +pub type Pin33EnR = crate::BitReader; +impl Pin33EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin33En { + match self.bits { + false => Pin33En::Disable, + true => Pin33En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin33En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin33En::Enable + } +} +#[doc = "Field `PIN_33_EN` writer - LCD Pin 33 Enable"] +pub type Pin33EnW<'a, REG> = crate::BitWriter<'a, REG, Pin33En>; +impl<'a, REG> Pin33EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin33En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin33En::Enable) + } +} +#[doc = "LCD Pin 34 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin34En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin34En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_34_EN` reader - LCD Pin 34 Enable"] +pub type Pin34EnR = crate::BitReader; +impl Pin34EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin34En { + match self.bits { + false => Pin34En::Disable, + true => Pin34En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin34En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin34En::Enable + } +} +#[doc = "Field `PIN_34_EN` writer - LCD Pin 34 Enable"] +pub type Pin34EnW<'a, REG> = crate::BitWriter<'a, REG, Pin34En>; +impl<'a, REG> Pin34EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin34En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin34En::Enable) + } +} +#[doc = "LCD Pin 35 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin35En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin35En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_35_EN` reader - LCD Pin 35 Enable"] +pub type Pin35EnR = crate::BitReader; +impl Pin35EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin35En { + match self.bits { + false => Pin35En::Disable, + true => Pin35En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin35En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin35En::Enable + } +} +#[doc = "Field `PIN_35_EN` writer - LCD Pin 35 Enable"] +pub type Pin35EnW<'a, REG> = crate::BitWriter<'a, REG, Pin35En>; +impl<'a, REG> Pin35EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin35En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin35En::Enable) + } +} +#[doc = "LCD Pin 36 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin36En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin36En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_36_EN` reader - LCD Pin 36 Enable"] +pub type Pin36EnR = crate::BitReader; +impl Pin36EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin36En { + match self.bits { + false => Pin36En::Disable, + true => Pin36En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin36En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin36En::Enable + } +} +#[doc = "Field `PIN_36_EN` writer - LCD Pin 36 Enable"] +pub type Pin36EnW<'a, REG> = crate::BitWriter<'a, REG, Pin36En>; +impl<'a, REG> Pin36EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin36En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin36En::Enable) + } +} +#[doc = "LCD Pin 37 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin37En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin37En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_37_EN` reader - LCD Pin 37 Enable"] +pub type Pin37EnR = crate::BitReader; +impl Pin37EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin37En { + match self.bits { + false => Pin37En::Disable, + true => Pin37En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin37En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin37En::Enable + } +} +#[doc = "Field `PIN_37_EN` writer - LCD Pin 37 Enable"] +pub type Pin37EnW<'a, REG> = crate::BitWriter<'a, REG, Pin37En>; +impl<'a, REG> Pin37EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin37En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin37En::Enable) + } +} +#[doc = "LCD Pin 38 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin38En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin38En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_38_EN` reader - LCD Pin 38 Enable"] +pub type Pin38EnR = crate::BitReader; +impl Pin38EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin38En { + match self.bits { + false => Pin38En::Disable, + true => Pin38En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin38En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin38En::Enable + } +} +#[doc = "Field `PIN_38_EN` writer - LCD Pin 38 Enable"] +pub type Pin38EnW<'a, REG> = crate::BitWriter<'a, REG, Pin38En>; +impl<'a, REG> Pin38EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin38En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin38En::Enable) + } +} +#[doc = "LCD Pin 39 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin39En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin39En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_39_EN` reader - LCD Pin 39 Enable"] +pub type Pin39EnR = crate::BitReader; +impl Pin39EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin39En { + match self.bits { + false => Pin39En::Disable, + true => Pin39En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin39En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin39En::Enable + } +} +#[doc = "Field `PIN_39_EN` writer - LCD Pin 39 Enable"] +pub type Pin39EnW<'a, REG> = crate::BitWriter<'a, REG, Pin39En>; +impl<'a, REG> Pin39EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin39En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin39En::Enable) + } +} +#[doc = "LCD Pin 40 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin40En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin40En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_40_EN` reader - LCD Pin 40 Enable"] +pub type Pin40EnR = crate::BitReader; +impl Pin40EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin40En { + match self.bits { + false => Pin40En::Disable, + true => Pin40En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin40En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin40En::Enable + } +} +#[doc = "Field `PIN_40_EN` writer - LCD Pin 40 Enable"] +pub type Pin40EnW<'a, REG> = crate::BitWriter<'a, REG, Pin40En>; +impl<'a, REG> Pin40EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin40En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin40En::Enable) + } +} +#[doc = "LCD Pin 41 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin41En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin41En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_41_EN` reader - LCD Pin 41 Enable"] +pub type Pin41EnR = crate::BitReader; +impl Pin41EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin41En { + match self.bits { + false => Pin41En::Disable, + true => Pin41En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin41En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin41En::Enable + } +} +#[doc = "Field `PIN_41_EN` writer - LCD Pin 41 Enable"] +pub type Pin41EnW<'a, REG> = crate::BitWriter<'a, REG, Pin41En>; +impl<'a, REG> Pin41EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin41En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin41En::Enable) + } +} +#[doc = "LCD Pin 42 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin42En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin42En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_42_EN` reader - LCD Pin 42 Enable"] +pub type Pin42EnR = crate::BitReader; +impl Pin42EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin42En { + match self.bits { + false => Pin42En::Disable, + true => Pin42En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin42En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin42En::Enable + } +} +#[doc = "Field `PIN_42_EN` writer - LCD Pin 42 Enable"] +pub type Pin42EnW<'a, REG> = crate::BitWriter<'a, REG, Pin42En>; +impl<'a, REG> Pin42EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin42En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin42En::Enable) + } +} +#[doc = "LCD Pin 43 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin43En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin43En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_43_EN` reader - LCD Pin 43 Enable"] +pub type Pin43EnR = crate::BitReader; +impl Pin43EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin43En { + match self.bits { + false => Pin43En::Disable, + true => Pin43En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin43En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin43En::Enable + } +} +#[doc = "Field `PIN_43_EN` writer - LCD Pin 43 Enable"] +pub type Pin43EnW<'a, REG> = crate::BitWriter<'a, REG, Pin43En>; +impl<'a, REG> Pin43EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin43En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin43En::Enable) + } +} +#[doc = "LCD Pin 44 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin44En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin44En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_44_EN` reader - LCD Pin 44 Enable"] +pub type Pin44EnR = crate::BitReader; +impl Pin44EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin44En { + match self.bits { + false => Pin44En::Disable, + true => Pin44En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin44En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin44En::Enable + } +} +#[doc = "Field `PIN_44_EN` writer - LCD Pin 44 Enable"] +pub type Pin44EnW<'a, REG> = crate::BitWriter<'a, REG, Pin44En>; +impl<'a, REG> Pin44EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin44En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin44En::Enable) + } +} +#[doc = "LCD Pin 45 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin45En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin45En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_45_EN` reader - LCD Pin 45 Enable"] +pub type Pin45EnR = crate::BitReader; +impl Pin45EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin45En { + match self.bits { + false => Pin45En::Disable, + true => Pin45En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin45En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin45En::Enable + } +} +#[doc = "Field `PIN_45_EN` writer - LCD Pin 45 Enable"] +pub type Pin45EnW<'a, REG> = crate::BitWriter<'a, REG, Pin45En>; +impl<'a, REG> Pin45EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin45En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin45En::Enable) + } +} +#[doc = "LCD Pin 46 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin46En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin46En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_46_EN` reader - LCD Pin 46 Enable"] +pub type Pin46EnR = crate::BitReader; +impl Pin46EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin46En { + match self.bits { + false => Pin46En::Disable, + true => Pin46En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin46En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin46En::Enable + } +} +#[doc = "Field `PIN_46_EN` writer - LCD Pin 46 Enable"] +pub type Pin46EnW<'a, REG> = crate::BitWriter<'a, REG, Pin46En>; +impl<'a, REG> Pin46EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin46En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin46En::Enable) + } +} +#[doc = "LCD Pin 47 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pin47En { + #[doc = "0: Pin Disable"] + Disable = 0, + #[doc = "1: Pin Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pin47En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIN_47_EN` reader - LCD Pin 47 Enable"] +pub type Pin47EnR = crate::BitReader; +impl Pin47EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pin47En { + match self.bits { + false => Pin47En::Disable, + true => Pin47En::Enable, + } + } + #[doc = "Pin Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Pin47En::Disable + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Pin47En::Enable + } +} +#[doc = "Field `PIN_47_EN` writer - LCD Pin 47 Enable"] +pub type Pin47EnW<'a, REG> = crate::BitWriter<'a, REG, Pin47En>; +impl<'a, REG> Pin47EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Pin47En::Disable) + } + #[doc = "Pin Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Pin47En::Enable) + } +} +impl R { + #[doc = "Bit 0 - LCD Pin 32 Enable"] + #[inline(always)] + pub fn pin_32_en(&self) -> Pin32EnR { + Pin32EnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - LCD Pin 33 Enable"] + #[inline(always)] + pub fn pin_33_en(&self) -> Pin33EnR { + Pin33EnR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LCD Pin 34 Enable"] + #[inline(always)] + pub fn pin_34_en(&self) -> Pin34EnR { + Pin34EnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - LCD Pin 35 Enable"] + #[inline(always)] + pub fn pin_35_en(&self) -> Pin35EnR { + Pin35EnR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - LCD Pin 36 Enable"] + #[inline(always)] + pub fn pin_36_en(&self) -> Pin36EnR { + Pin36EnR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - LCD Pin 37 Enable"] + #[inline(always)] + pub fn pin_37_en(&self) -> Pin37EnR { + Pin37EnR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - LCD Pin 38 Enable"] + #[inline(always)] + pub fn pin_38_en(&self) -> Pin38EnR { + Pin38EnR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - LCD Pin 39 Enable"] + #[inline(always)] + pub fn pin_39_en(&self) -> Pin39EnR { + Pin39EnR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - LCD Pin 40 Enable"] + #[inline(always)] + pub fn pin_40_en(&self) -> Pin40EnR { + Pin40EnR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - LCD Pin 41 Enable"] + #[inline(always)] + pub fn pin_41_en(&self) -> Pin41EnR { + Pin41EnR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - LCD Pin 42 Enable"] + #[inline(always)] + pub fn pin_42_en(&self) -> Pin42EnR { + Pin42EnR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - LCD Pin 43 Enable"] + #[inline(always)] + pub fn pin_43_en(&self) -> Pin43EnR { + Pin43EnR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - LCD Pin 44 Enable"] + #[inline(always)] + pub fn pin_44_en(&self) -> Pin44EnR { + Pin44EnR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - LCD Pin 45 Enable"] + #[inline(always)] + pub fn pin_45_en(&self) -> Pin45EnR { + Pin45EnR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - LCD Pin 46 Enable"] + #[inline(always)] + pub fn pin_46_en(&self) -> Pin46EnR { + Pin46EnR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - LCD Pin 47 Enable"] + #[inline(always)] + pub fn pin_47_en(&self) -> Pin47EnR { + Pin47EnR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LCD Pin 32 Enable"] + #[inline(always)] + pub fn pin_32_en(&mut self) -> Pin32EnW { + Pin32EnW::new(self, 0) + } + #[doc = "Bit 1 - LCD Pin 33 Enable"] + #[inline(always)] + pub fn pin_33_en(&mut self) -> Pin33EnW { + Pin33EnW::new(self, 1) + } + #[doc = "Bit 2 - LCD Pin 34 Enable"] + #[inline(always)] + pub fn pin_34_en(&mut self) -> Pin34EnW { + Pin34EnW::new(self, 2) + } + #[doc = "Bit 3 - LCD Pin 35 Enable"] + #[inline(always)] + pub fn pin_35_en(&mut self) -> Pin35EnW { + Pin35EnW::new(self, 3) + } + #[doc = "Bit 4 - LCD Pin 36 Enable"] + #[inline(always)] + pub fn pin_36_en(&mut self) -> Pin36EnW { + Pin36EnW::new(self, 4) + } + #[doc = "Bit 5 - LCD Pin 37 Enable"] + #[inline(always)] + pub fn pin_37_en(&mut self) -> Pin37EnW { + Pin37EnW::new(self, 5) + } + #[doc = "Bit 6 - LCD Pin 38 Enable"] + #[inline(always)] + pub fn pin_38_en(&mut self) -> Pin38EnW { + Pin38EnW::new(self, 6) + } + #[doc = "Bit 7 - LCD Pin 39 Enable"] + #[inline(always)] + pub fn pin_39_en(&mut self) -> Pin39EnW { + Pin39EnW::new(self, 7) + } + #[doc = "Bit 8 - LCD Pin 40 Enable"] + #[inline(always)] + pub fn pin_40_en(&mut self) -> Pin40EnW { + Pin40EnW::new(self, 8) + } + #[doc = "Bit 9 - LCD Pin 41 Enable"] + #[inline(always)] + pub fn pin_41_en(&mut self) -> Pin41EnW { + Pin41EnW::new(self, 9) + } + #[doc = "Bit 10 - LCD Pin 42 Enable"] + #[inline(always)] + pub fn pin_42_en(&mut self) -> Pin42EnW { + Pin42EnW::new(self, 10) + } + #[doc = "Bit 11 - LCD Pin 43 Enable"] + #[inline(always)] + pub fn pin_43_en(&mut self) -> Pin43EnW { + Pin43EnW::new(self, 11) + } + #[doc = "Bit 12 - LCD Pin 44 Enable"] + #[inline(always)] + pub fn pin_44_en(&mut self) -> Pin44EnW { + Pin44EnW::new(self, 12) + } + #[doc = "Bit 13 - LCD Pin 45 Enable"] + #[inline(always)] + pub fn pin_45_en(&mut self) -> Pin45EnW { + Pin45EnW::new(self, 13) + } + #[doc = "Bit 14 - LCD Pin 46 Enable"] + #[inline(always)] + pub fn pin_46_en(&mut self) -> Pin46EnW { + Pin46EnW::new(self, 14) + } + #[doc = "Bit 15 - LCD Pin 47 Enable"] + #[inline(always)] + pub fn pin_47_en(&mut self) -> Pin47EnW { + Pin47EnW::new(self, 15) + } +} +#[doc = "LCD Pin Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdPen1Spec; +impl crate::RegisterSpec for LcdPen1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_pen1::R`](R) reader structure"] +impl crate::Readable for LcdPen1Spec {} +#[doc = "`write(|w| ..)` method takes [`lcd_pen1::W`](W) writer structure"] +impl crate::Writable for LcdPen1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCD_PEN1 to value 0"] +impl crate::Resettable for LcdPen1Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_wfto.rs b/mcxa276-pac/src/slcd0/lcd_wfto.rs new file mode 100644 index 000000000..5c21b06c8 --- /dev/null +++ b/mcxa276-pac/src/slcd0/lcd_wfto.rs @@ -0,0 +1,77 @@ +#[doc = "Register `LCD_WFTO[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_WFTO[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `WF0` reader - Waveform Pin 0"] +pub type Wf0R = crate::FieldReader; +#[doc = "Field `WF0` writer - Waveform Pin 0"] +pub type Wf0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WF1` reader - Waveform Pin 1"] +pub type Wf1R = crate::FieldReader; +#[doc = "Field `WF1` writer - Waveform Pin 1"] +pub type Wf1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WF2` reader - Waveform Pin 2"] +pub type Wf2R = crate::FieldReader; +#[doc = "Field `WF2` writer - Waveform Pin 2"] +pub type Wf2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WF3` reader - Waveform Pin 3"] +pub type Wf3R = crate::FieldReader; +#[doc = "Field `WF3` writer - Waveform Pin 3"] +pub type Wf3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Waveform Pin 0"] + #[inline(always)] + pub fn wf0(&self) -> Wf0R { + Wf0R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Waveform Pin 1"] + #[inline(always)] + pub fn wf1(&self) -> Wf1R { + Wf1R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Waveform Pin 2"] + #[inline(always)] + pub fn wf2(&self) -> Wf2R { + Wf2R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Waveform Pin 3"] + #[inline(always)] + pub fn wf3(&self) -> Wf3R { + Wf3R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Waveform Pin 0"] + #[inline(always)] + pub fn wf0(&mut self) -> Wf0W { + Wf0W::new(self, 0) + } + #[doc = "Bits 8:15 - Waveform Pin 1"] + #[inline(always)] + pub fn wf1(&mut self) -> Wf1W { + Wf1W::new(self, 8) + } + #[doc = "Bits 16:23 - Waveform Pin 2"] + #[inline(always)] + pub fn wf2(&mut self) -> Wf2W { + Wf2W::new(self, 16) + } + #[doc = "Bits 24:31 - Waveform Pin 3"] + #[inline(always)] + pub fn wf3(&mut self) -> Wf3W { + Wf3W::new(self, 24) + } +} +#[doc = "LCD Waveform i * 4 + 3 to i * 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_wfto::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_wfto::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcdWftoSpec; +impl crate::RegisterSpec for LcdWftoSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_wfto::R`](R) reader structure"] +impl crate::Readable for LcdWftoSpec {} +#[doc = "`write(|w| ..)` method takes [`lcd_wfto::W`](W) writer structure"] +impl crate::Writable for LcdWftoSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LCD_WFTO[%s] to value 0"] +impl crate::Resettable for LcdWftoSpec {} diff --git a/mcxa276-pac/src/smartdma0.rs b/mcxa276-pac/src/smartdma0.rs new file mode 100644 index 000000000..d9f1d5364 --- /dev/null +++ b/mcxa276-pac/src/smartdma0.rs @@ -0,0 +1,128 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x20], + bootadr: Bootadr, + ctrl: Ctrl, + pc: Pc, + sp: Sp, + break_addr: BreakAddr, + break_vect: BreakVect, + emer_vect: EmerVect, + emer_sel: EmerSel, + arm2ezh: Arm2ezh, + ezh2arm: Ezh2arm, + pendtrap: Pendtrap, +} +impl RegisterBlock { + #[doc = "0x20 - Boot Address"] + #[inline(always)] + pub const fn bootadr(&self) -> &Bootadr { + &self.bootadr + } + #[doc = "0x24 - Control"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x28 - Program Counter"] + #[inline(always)] + pub const fn pc(&self) -> &Pc { + &self.pc + } + #[doc = "0x2c - Stack Pointer"] + #[inline(always)] + pub const fn sp(&self) -> &Sp { + &self.sp + } + #[doc = "0x30 - Breakpoint Address"] + #[inline(always)] + pub const fn break_addr(&self) -> &BreakAddr { + &self.break_addr + } + #[doc = "0x34 - Breakpoint Vector"] + #[inline(always)] + pub const fn break_vect(&self) -> &BreakVect { + &self.break_vect + } + #[doc = "0x38 - Emergency Vector"] + #[inline(always)] + pub const fn emer_vect(&self) -> &EmerVect { + &self.emer_vect + } + #[doc = "0x3c - Emergency Select"] + #[inline(always)] + pub const fn emer_sel(&self) -> &EmerSel { + &self.emer_sel + } + #[doc = "0x40 - ARM to EZH Interrupt Control"] + #[inline(always)] + pub const fn arm2ezh(&self) -> &Arm2ezh { + &self.arm2ezh + } + #[doc = "0x44 - EZH to ARM Trigger"] + #[inline(always)] + pub const fn ezh2arm(&self) -> &Ezh2arm { + &self.ezh2arm + } + #[doc = "0x48 - Pending Trap Control"] + #[inline(always)] + pub const fn pendtrap(&self) -> &Pendtrap { + &self.pendtrap + } +} +#[doc = "BOOTADR (rw) register accessor: Boot Address\n\nYou can [`read`](crate::Reg::read) this register and get [`bootadr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootadr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bootadr`] module"] +#[doc(alias = "BOOTADR")] +pub type Bootadr = crate::Reg; +#[doc = "Boot Address"] +pub mod bootadr; +#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "PC (r) register accessor: Program Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`] module"] +#[doc(alias = "PC")] +pub type Pc = crate::Reg; +#[doc = "Program Counter"] +pub mod pc; +#[doc = "SP (r) register accessor: Stack Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sp`] module"] +#[doc(alias = "SP")] +pub type Sp = crate::Reg; +#[doc = "Stack Pointer"] +pub mod sp; +#[doc = "BREAK_ADDR (rw) register accessor: Breakpoint Address\n\nYou can [`read`](crate::Reg::read) this register and get [`break_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@break_addr`] module"] +#[doc(alias = "BREAK_ADDR")] +pub type BreakAddr = crate::Reg; +#[doc = "Breakpoint Address"] +pub mod break_addr; +#[doc = "BREAK_VECT (rw) register accessor: Breakpoint Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`break_vect::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_vect::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@break_vect`] module"] +#[doc(alias = "BREAK_VECT")] +pub type BreakVect = crate::Reg; +#[doc = "Breakpoint Vector"] +pub mod break_vect; +#[doc = "EMER_VECT (rw) register accessor: Emergency Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_vect::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_vect::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emer_vect`] module"] +#[doc(alias = "EMER_VECT")] +pub type EmerVect = crate::Reg; +#[doc = "Emergency Vector"] +pub mod emer_vect; +#[doc = "EMER_SEL (rw) register accessor: Emergency Select\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emer_sel`] module"] +#[doc(alias = "EMER_SEL")] +pub type EmerSel = crate::Reg; +#[doc = "Emergency Select"] +pub mod emer_sel; +#[doc = "ARM2EZH (rw) register accessor: ARM to EZH Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`arm2ezh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arm2ezh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arm2ezh`] module"] +#[doc(alias = "ARM2EZH")] +pub type Arm2ezh = crate::Reg; +#[doc = "ARM to EZH Interrupt Control"] +pub mod arm2ezh; +#[doc = "EZH2ARM (rw) register accessor: EZH to ARM Trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`ezh2arm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ezh2arm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ezh2arm`] module"] +#[doc(alias = "EZH2ARM")] +pub type Ezh2arm = crate::Reg; +#[doc = "EZH to ARM Trigger"] +pub mod ezh2arm; +#[doc = "PENDTRAP (rw) register accessor: Pending Trap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pendtrap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pendtrap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pendtrap`] module"] +#[doc(alias = "PENDTRAP")] +pub type Pendtrap = crate::Reg; +#[doc = "Pending Trap Control"] +pub mod pendtrap; diff --git a/mcxa276-pac/src/smartdma0/arm2ezh.rs b/mcxa276-pac/src/smartdma0/arm2ezh.rs new file mode 100644 index 000000000..6f7bee621 --- /dev/null +++ b/mcxa276-pac/src/smartdma0/arm2ezh.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ARM2EZH` reader"] +pub type R = crate::R; +#[doc = "Register `ARM2EZH` writer"] +pub type W = crate::W; +#[doc = "Field `IE` reader - Interrupt Enable"] +pub type IeR = crate::FieldReader; +#[doc = "Field `IE` writer - Interrupt Enable"] +pub type IeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GP` reader - General purpose register bits"] +pub type GpR = crate::FieldReader; +#[doc = "Field `GP` writer - General purpose register bits"] +pub type GpW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:1 - Interrupt Enable"] + #[inline(always)] + pub fn ie(&self) -> IeR { + IeR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:31 - General purpose register bits"] + #[inline(always)] + pub fn gp(&self) -> GpR { + GpR::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 0:1 - Interrupt Enable"] + #[inline(always)] + pub fn ie(&mut self) -> IeW { + IeW::new(self, 0) + } + #[doc = "Bits 2:31 - General purpose register bits"] + #[inline(always)] + pub fn gp(&mut self) -> GpW { + GpW::new(self, 2) + } +} +#[doc = "ARM to EZH Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`arm2ezh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arm2ezh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Arm2ezhSpec; +impl crate::RegisterSpec for Arm2ezhSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`arm2ezh::R`](R) reader structure"] +impl crate::Readable for Arm2ezhSpec {} +#[doc = "`write(|w| ..)` method takes [`arm2ezh::W`](W) writer structure"] +impl crate::Writable for Arm2ezhSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ARM2EZH to value 0"] +impl crate::Resettable for Arm2ezhSpec {} diff --git a/mcxa276-pac/src/smartdma0/bootadr.rs b/mcxa276-pac/src/smartdma0/bootadr.rs new file mode 100644 index 000000000..630b08c75 --- /dev/null +++ b/mcxa276-pac/src/smartdma0/bootadr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `BOOTADR` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTADR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - 32-bit boot address, the boot address should be 4-byte aligned."] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - 32-bit boot address, the boot address should be 4-byte aligned."] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 2:31 - 32-bit boot address, the boot address should be 4-byte aligned."] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 2:31 - 32-bit boot address, the boot address should be 4-byte aligned."] + #[inline(always)] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 2) + } +} +#[doc = "Boot Address\n\nYou can [`read`](crate::Reg::read) this register and get [`bootadr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootadr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BootadrSpec; +impl crate::RegisterSpec for BootadrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootadr::R`](R) reader structure"] +impl crate::Readable for BootadrSpec {} +#[doc = "`write(|w| ..)` method takes [`bootadr::W`](W) writer structure"] +impl crate::Writable for BootadrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BOOTADR to value 0"] +impl crate::Resettable for BootadrSpec {} diff --git a/mcxa276-pac/src/smartdma0/break_addr.rs b/mcxa276-pac/src/smartdma0/break_addr.rs new file mode 100644 index 000000000..2b303a7f9 --- /dev/null +++ b/mcxa276-pac/src/smartdma0/break_addr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `BREAK_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `BREAK_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - 32-bit address to swap to EZHB_BREAK_VECT location"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - 32-bit address to swap to EZHB_BREAK_VECT location"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 2:31 - 32-bit address to swap to EZHB_BREAK_VECT location"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 2:31 - 32-bit address to swap to EZHB_BREAK_VECT location"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 2) + } +} +#[doc = "Breakpoint Address\n\nYou can [`read`](crate::Reg::read) this register and get [`break_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BreakAddrSpec; +impl crate::RegisterSpec for BreakAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`break_addr::R`](R) reader structure"] +impl crate::Readable for BreakAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`break_addr::W`](W) writer structure"] +impl crate::Writable for BreakAddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BREAK_ADDR to value 0"] +impl crate::Resettable for BreakAddrSpec {} diff --git a/mcxa276-pac/src/smartdma0/break_vect.rs b/mcxa276-pac/src/smartdma0/break_vect.rs new file mode 100644 index 000000000..de7e8439f --- /dev/null +++ b/mcxa276-pac/src/smartdma0/break_vect.rs @@ -0,0 +1,35 @@ +#[doc = "Register `BREAK_VECT` reader"] +pub type R = crate::R; +#[doc = "Register `BREAK_VECT` writer"] +pub type W = crate::W; +#[doc = "Field `VEC` reader - Vector address of user debug routine."] +pub type VecR = crate::FieldReader; +#[doc = "Field `VEC` writer - Vector address of user debug routine."] +pub type VecW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 2:31 - Vector address of user debug routine."] + #[inline(always)] + pub fn vec(&self) -> VecR { + VecR::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 2:31 - Vector address of user debug routine."] + #[inline(always)] + pub fn vec(&mut self) -> VecW { + VecW::new(self, 2) + } +} +#[doc = "Breakpoint Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`break_vect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_vect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BreakVectSpec; +impl crate::RegisterSpec for BreakVectSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`break_vect::R`](R) reader structure"] +impl crate::Readable for BreakVectSpec {} +#[doc = "`write(|w| ..)` method takes [`break_vect::W`](W) writer structure"] +impl crate::Writable for BreakVectSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BREAK_VECT to value 0"] +impl crate::Resettable for BreakVectSpec {} diff --git a/mcxa276-pac/src/smartdma0/ctrl.rs b/mcxa276-pac/src/smartdma0/ctrl.rs new file mode 100644 index 000000000..625179c7e --- /dev/null +++ b/mcxa276-pac/src/smartdma0/ctrl.rs @@ -0,0 +1,105 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `START` reader - Start Bit Ignition"] +pub type StartR = crate::BitReader; +#[doc = "Field `START` writer - Start Bit Ignition"] +pub type StartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXF` reader - External Flag"] +pub type ExfR = crate::BitReader; +#[doc = "Field `EXF` writer - External Flag"] +pub type ExfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERRDIS` reader - Error Disable"] +pub type ErrdisR = crate::BitReader; +#[doc = "Field `ERRDIS` writer - Error Disable"] +pub type ErrdisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUFEN` reader - Buffer Enable"] +pub type BufenR = crate::BitReader; +#[doc = "Field `BUFEN` writer - Buffer Enable"] +pub type BufenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNCEN` reader - Sync Enable"] +pub type SyncenR = crate::BitReader; +#[doc = "Field `SYNCEN` writer - Sync Enable"] +pub type SyncenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WKEY` reader - Write Key"] +pub type WkeyR = crate::FieldReader; +#[doc = "Field `WKEY` writer - Write Key"] +pub type WkeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Start Bit Ignition"] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - External Flag"] + #[inline(always)] + pub fn exf(&self) -> ExfR { + ExfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Error Disable"] + #[inline(always)] + pub fn errdis(&self) -> ErrdisR { + ErrdisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Buffer Enable"] + #[inline(always)] + pub fn bufen(&self) -> BufenR { + BufenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Sync Enable"] + #[inline(always)] + pub fn syncen(&self) -> SyncenR { + SyncenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 16:31 - Write Key"] + #[inline(always)] + pub fn wkey(&self) -> WkeyR { + WkeyR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Start Bit Ignition"] + #[inline(always)] + pub fn start(&mut self) -> StartW { + StartW::new(self, 0) + } + #[doc = "Bit 1 - External Flag"] + #[inline(always)] + pub fn exf(&mut self) -> ExfW { + ExfW::new(self, 1) + } + #[doc = "Bit 2 - Error Disable"] + #[inline(always)] + pub fn errdis(&mut self) -> ErrdisW { + ErrdisW::new(self, 2) + } + #[doc = "Bit 3 - Buffer Enable"] + #[inline(always)] + pub fn bufen(&mut self) -> BufenW { + BufenW::new(self, 3) + } + #[doc = "Bit 4 - Sync Enable"] + #[inline(always)] + pub fn syncen(&mut self) -> SyncenW { + SyncenW::new(self, 4) + } + #[doc = "Bits 16:31 - Write Key"] + #[inline(always)] + pub fn wkey(&mut self) -> WkeyW { + WkeyW::new(self, 16) + } +} +#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/smartdma0/emer_sel.rs b/mcxa276-pac/src/smartdma0/emer_sel.rs new file mode 100644 index 000000000..d91342fb6 --- /dev/null +++ b/mcxa276-pac/src/smartdma0/emer_sel.rs @@ -0,0 +1,49 @@ +#[doc = "Register `EMER_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `EMER_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Emergency code routine"] +pub type EnR = crate::BitReader; +#[doc = "Field `EN` writer - Emergency code routine"] +pub type EnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RQ` reader - Software emergency request"] +pub type RqR = crate::BitReader; +#[doc = "Field `RQ` writer - Software emergency request"] +pub type RqW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 8 - Emergency code routine"] + #[inline(always)] + pub fn en(&self) -> EnR { + EnR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software emergency request"] + #[inline(always)] + pub fn rq(&self) -> RqR { + RqR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Emergency code routine"] + #[inline(always)] + pub fn en(&mut self) -> EnW { + EnW::new(self, 8) + } + #[doc = "Bit 9 - Software emergency request"] + #[inline(always)] + pub fn rq(&mut self) -> RqW { + RqW::new(self, 9) + } +} +#[doc = "Emergency Select\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EmerSelSpec; +impl crate::RegisterSpec for EmerSelSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`emer_sel::R`](R) reader structure"] +impl crate::Readable for EmerSelSpec {} +#[doc = "`write(|w| ..)` method takes [`emer_sel::W`](W) writer structure"] +impl crate::Writable for EmerSelSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EMER_SEL to value 0"] +impl crate::Resettable for EmerSelSpec {} diff --git a/mcxa276-pac/src/smartdma0/emer_vect.rs b/mcxa276-pac/src/smartdma0/emer_vect.rs new file mode 100644 index 000000000..d9e88e767 --- /dev/null +++ b/mcxa276-pac/src/smartdma0/emer_vect.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EMER_VECT` reader"] +pub type R = crate::R; +#[doc = "Register `EMER_VECT` writer"] +pub type W = crate::W; +#[doc = "Field `VEC` reader - Vector address of emergency code routine"] +pub type VecR = crate::FieldReader; +#[doc = "Field `VEC` writer - Vector address of emergency code routine"] +pub type VecW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 2:31 - Vector address of emergency code routine"] + #[inline(always)] + pub fn vec(&self) -> VecR { + VecR::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 2:31 - Vector address of emergency code routine"] + #[inline(always)] + pub fn vec(&mut self) -> VecW { + VecW::new(self, 2) + } +} +#[doc = "Emergency Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_vect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_vect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EmerVectSpec; +impl crate::RegisterSpec for EmerVectSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`emer_vect::R`](R) reader structure"] +impl crate::Readable for EmerVectSpec {} +#[doc = "`write(|w| ..)` method takes [`emer_vect::W`](W) writer structure"] +impl crate::Writable for EmerVectSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EMER_VECT to value 0"] +impl crate::Resettable for EmerVectSpec {} diff --git a/mcxa276-pac/src/smartdma0/ezh2arm.rs b/mcxa276-pac/src/smartdma0/ezh2arm.rs new file mode 100644 index 000000000..2bebdcf10 --- /dev/null +++ b/mcxa276-pac/src/smartdma0/ezh2arm.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EZH2ARM` reader"] +pub type R = crate::R; +#[doc = "Register `EZH2ARM` writer"] +pub type W = crate::W; +#[doc = "Field `GP` reader - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] +pub type GpR = crate::FieldReader; +#[doc = "Field `GP` writer - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] +pub type GpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] + #[inline(always)] + pub fn gp(&self) -> GpR { + GpR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] + #[inline(always)] + pub fn gp(&mut self) -> GpW { + GpW::new(self, 0) + } +} +#[doc = "EZH to ARM Trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`ezh2arm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ezh2arm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ezh2armSpec; +impl crate::RegisterSpec for Ezh2armSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ezh2arm::R`](R) reader structure"] +impl crate::Readable for Ezh2armSpec {} +#[doc = "`write(|w| ..)` method takes [`ezh2arm::W`](W) writer structure"] +impl crate::Writable for Ezh2armSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EZH2ARM to value 0"] +impl crate::Resettable for Ezh2armSpec {} diff --git a/mcxa276-pac/src/smartdma0/pc.rs b/mcxa276-pac/src/smartdma0/pc.rs new file mode 100644 index 000000000..17fa6fb8b --- /dev/null +++ b/mcxa276-pac/src/smartdma0/pc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `PC` reader"] +pub type R = crate::R; +#[doc = "Field `PC` reader - Program Counter"] +pub type PcR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Program Counter"] + #[inline(always)] + pub fn pc(&self) -> PcR { + PcR::new(self.bits) + } +} +#[doc = "Program Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PcSpec; +impl crate::RegisterSpec for PcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pc::R`](R) reader structure"] +impl crate::Readable for PcSpec {} +#[doc = "`reset()` method sets PC to value 0"] +impl crate::Resettable for PcSpec {} diff --git a/mcxa276-pac/src/smartdma0/pendtrap.rs b/mcxa276-pac/src/smartdma0/pendtrap.rs new file mode 100644 index 000000000..5bd3d0e4a --- /dev/null +++ b/mcxa276-pac/src/smartdma0/pendtrap.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PENDTRAP` reader"] +pub type R = crate::R; +#[doc = "Register `PENDTRAP` writer"] +pub type W = crate::W; +#[doc = "Field `STATUS` reader - Status Flag or Pending Trap Request"] +pub type StatusR = crate::FieldReader; +#[doc = "Field `STATUS` writer - Status Flag or Pending Trap Request"] +pub type StatusW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `POL` reader - Polarity"] +pub type PolR = crate::FieldReader; +#[doc = "Field `POL` writer - Polarity"] +pub type PolW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `EN` reader - Enable Pending Trap"] +pub type EnR = crate::FieldReader; +#[doc = "Field `EN` writer - Enable Pending Trap"] +pub type EnW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Status Flag or Pending Trap Request"] + #[inline(always)] + pub fn status(&self) -> StatusR { + StatusR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Polarity"] + #[inline(always)] + pub fn pol(&self) -> PolR { + PolR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Enable Pending Trap"] + #[inline(always)] + pub fn en(&self) -> EnR { + EnR::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Status Flag or Pending Trap Request"] + #[inline(always)] + pub fn status(&mut self) -> StatusW { + StatusW::new(self, 0) + } + #[doc = "Bits 8:15 - Polarity"] + #[inline(always)] + pub fn pol(&mut self) -> PolW { + PolW::new(self, 8) + } + #[doc = "Bits 16:23 - Enable Pending Trap"] + #[inline(always)] + pub fn en(&mut self) -> EnW { + EnW::new(self, 16) + } +} +#[doc = "Pending Trap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pendtrap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pendtrap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PendtrapSpec; +impl crate::RegisterSpec for PendtrapSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pendtrap::R`](R) reader structure"] +impl crate::Readable for PendtrapSpec {} +#[doc = "`write(|w| ..)` method takes [`pendtrap::W`](W) writer structure"] +impl crate::Writable for PendtrapSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PENDTRAP to value 0"] +impl crate::Resettable for PendtrapSpec {} diff --git a/mcxa276-pac/src/smartdma0/sp.rs b/mcxa276-pac/src/smartdma0/sp.rs new file mode 100644 index 000000000..7eb5ed45b --- /dev/null +++ b/mcxa276-pac/src/smartdma0/sp.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SP` reader"] +pub type R = crate::R; +#[doc = "Field `SP` reader - Stack Pointer"] +pub type SpR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stack Pointer"] + #[inline(always)] + pub fn sp(&self) -> SpR { + SpR::new(self.bits) + } +} +#[doc = "Stack Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpSpec; +impl crate::RegisterSpec for SpSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sp::R`](R) reader structure"] +impl crate::Readable for SpSpec {} +#[doc = "`reset()` method sets SP to value 0"] +impl crate::Resettable for SpSpec {} diff --git a/mcxa276-pac/src/spc0.rs b/mcxa276-pac/src/spc0.rs new file mode 100644 index 000000000..5a9aa7295 --- /dev/null +++ b/mcxa276-pac/src/spc0.rs @@ -0,0 +1,214 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x0c], + sc: Sc, + _reserved2: [u8; 0x08], + lpreq_cfg: LpreqCfg, + _reserved3: [u8; 0x10], + pd_status0: PdStatus0, + _reserved4: [u8; 0x0c], + sramctl: Sramctl, + _reserved5: [u8; 0x10], + sramretldo_reftrim: SramretldoReftrim, + sramretldo_cntrl: SramretldoCntrl, + _reserved7: [u8; 0xa4], + active_cfg: ActiveCfg, + active_cfg1: ActiveCfg1, + lp_cfg: LpCfg, + lp_cfg1: LpCfg1, + _reserved11: [u8; 0x10], + lpwkup_delay: LpwkupDelay, + active_vdelay: ActiveVdelay, + _reserved13: [u8; 0x08], + vd_stat: VdStat, + vd_core_cfg: VdCoreCfg, + vd_sys_cfg: VdSysCfg, + _reserved16: [u8; 0x04], + evd_cfg: EvdCfg, + _reserved17: [u8; 0x01bc], + coreldo_cfg: CoreldoCfg, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x10 - Status Control"] + #[inline(always)] + pub const fn sc(&self) -> &Sc { + &self.sc + } + #[doc = "0x1c - Low-Power Request Configuration"] + #[inline(always)] + pub const fn lpreq_cfg(&self) -> &LpreqCfg { + &self.lpreq_cfg + } + #[doc = "0x30 - SPC Power Domain Mode Status"] + #[inline(always)] + pub const fn pd_status0(&self) -> &PdStatus0 { + &self.pd_status0 + } + #[doc = "0x40 - SRAM Control"] + #[inline(always)] + pub const fn sramctl(&self) -> &Sramctl { + &self.sramctl + } + #[doc = "0x54 - SRAM Retention Reference Trim"] + #[inline(always)] + pub const fn sramretldo_reftrim(&self) -> &SramretldoReftrim { + &self.sramretldo_reftrim + } + #[doc = "0x58 - SRAM Retention LDO Control"] + #[inline(always)] + pub const fn sramretldo_cntrl(&self) -> &SramretldoCntrl { + &self.sramretldo_cntrl + } + #[doc = "0x100 - Active Power Mode Configuration"] + #[inline(always)] + pub const fn active_cfg(&self) -> &ActiveCfg { + &self.active_cfg + } + #[doc = "0x104 - Active Power Mode Configuration 1"] + #[inline(always)] + pub const fn active_cfg1(&self) -> &ActiveCfg1 { + &self.active_cfg1 + } + #[doc = "0x108 - Low-Power Mode Configuration"] + #[inline(always)] + pub const fn lp_cfg(&self) -> &LpCfg { + &self.lp_cfg + } + #[doc = "0x10c - Low Power Mode Configuration 1"] + #[inline(always)] + pub const fn lp_cfg1(&self) -> &LpCfg1 { + &self.lp_cfg1 + } + #[doc = "0x120 - Low Power Wake-Up Delay"] + #[inline(always)] + pub const fn lpwkup_delay(&self) -> &LpwkupDelay { + &self.lpwkup_delay + } + #[doc = "0x124 - Active Voltage Trim Delay"] + #[inline(always)] + pub const fn active_vdelay(&self) -> &ActiveVdelay { + &self.active_vdelay + } + #[doc = "0x130 - Voltage Detect Status"] + #[inline(always)] + pub const fn vd_stat(&self) -> &VdStat { + &self.vd_stat + } + #[doc = "0x134 - Core Voltage Detect Configuration"] + #[inline(always)] + pub const fn vd_core_cfg(&self) -> &VdCoreCfg { + &self.vd_core_cfg + } + #[doc = "0x138 - System Voltage Detect Configuration"] + #[inline(always)] + pub const fn vd_sys_cfg(&self) -> &VdSysCfg { + &self.vd_sys_cfg + } + #[doc = "0x140 - External Voltage Domain Configuration"] + #[inline(always)] + pub const fn evd_cfg(&self) -> &EvdCfg { + &self.evd_cfg + } + #[doc = "0x300 - LDO_CORE Configuration"] + #[inline(always)] + pub const fn coreldo_cfg(&self) -> &CoreldoCfg { + &self.coreldo_cfg + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "SC (rw) register accessor: Status Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sc`] module"] +#[doc(alias = "SC")] +pub type Sc = crate::Reg; +#[doc = "Status Control"] +pub mod sc; +#[doc = "LPREQ_CFG (rw) register accessor: Low-Power Request Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lpreq_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpreq_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpreq_cfg`] module"] +#[doc(alias = "LPREQ_CFG")] +pub type LpreqCfg = crate::Reg; +#[doc = "Low-Power Request Configuration"] +pub mod lpreq_cfg; +#[doc = "PD_STATUS0 (rw) register accessor: SPC Power Domain Mode Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_status0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_status0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_status0`] module"] +#[doc(alias = "PD_STATUS0")] +pub type PdStatus0 = crate::Reg; +#[doc = "SPC Power Domain Mode Status"] +pub mod pd_status0; +#[doc = "SRAMCTL (rw) register accessor: SRAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sramctl`] module"] +#[doc(alias = "SRAMCTL")] +pub type Sramctl = crate::Reg; +#[doc = "SRAM Control"] +pub mod sramctl; +#[doc = "SRAMRETLDO_REFTRIM (rw) register accessor: SRAM Retention Reference Trim\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_reftrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_reftrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sramretldo_reftrim`] module"] +#[doc(alias = "SRAMRETLDO_REFTRIM")] +pub type SramretldoReftrim = crate::Reg; +#[doc = "SRAM Retention Reference Trim"] +pub mod sramretldo_reftrim; +#[doc = "SRAMRETLDO_CNTRL (rw) register accessor: SRAM Retention LDO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_cntrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_cntrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sramretldo_cntrl`] module"] +#[doc(alias = "SRAMRETLDO_CNTRL")] +pub type SramretldoCntrl = crate::Reg; +#[doc = "SRAM Retention LDO Control"] +pub mod sramretldo_cntrl; +#[doc = "ACTIVE_CFG (rw) register accessor: Active Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@active_cfg`] module"] +#[doc(alias = "ACTIVE_CFG")] +pub type ActiveCfg = crate::Reg; +#[doc = "Active Power Mode Configuration"] +pub mod active_cfg; +#[doc = "ACTIVE_CFG1 (rw) register accessor: Active Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@active_cfg1`] module"] +#[doc(alias = "ACTIVE_CFG1")] +pub type ActiveCfg1 = crate::Reg; +#[doc = "Active Power Mode Configuration 1"] +pub mod active_cfg1; +#[doc = "LP_CFG (rw) register accessor: Low-Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cfg`] module"] +#[doc(alias = "LP_CFG")] +pub type LpCfg = crate::Reg; +#[doc = "Low-Power Mode Configuration"] +pub mod lp_cfg; +#[doc = "LP_CFG1 (rw) register accessor: Low Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cfg1`] module"] +#[doc(alias = "LP_CFG1")] +pub type LpCfg1 = crate::Reg; +#[doc = "Low Power Mode Configuration 1"] +pub mod lp_cfg1; +#[doc = "LPWKUP_DELAY (rw) register accessor: Low Power Wake-Up Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`lpwkup_delay::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpwkup_delay::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpwkup_delay`] module"] +#[doc(alias = "LPWKUP_DELAY")] +pub type LpwkupDelay = crate::Reg; +#[doc = "Low Power Wake-Up Delay"] +pub mod lpwkup_delay; +#[doc = "ACTIVE_VDELAY (rw) register accessor: Active Voltage Trim Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`active_vdelay::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_vdelay::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@active_vdelay`] module"] +#[doc(alias = "ACTIVE_VDELAY")] +pub type ActiveVdelay = crate::Reg; +#[doc = "Active Voltage Trim Delay"] +pub mod active_vdelay; +#[doc = "VD_STAT (rw) register accessor: Voltage Detect Status\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_stat`] module"] +#[doc(alias = "VD_STAT")] +pub type VdStat = crate::Reg; +#[doc = "Voltage Detect Status"] +pub mod vd_stat; +#[doc = "VD_CORE_CFG (rw) register accessor: Core Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_core_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_core_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_core_cfg`] module"] +#[doc(alias = "VD_CORE_CFG")] +pub type VdCoreCfg = crate::Reg; +#[doc = "Core Voltage Detect Configuration"] +pub mod vd_core_cfg; +#[doc = "VD_SYS_CFG (rw) register accessor: System Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_sys_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_sys_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_sys_cfg`] module"] +#[doc(alias = "VD_SYS_CFG")] +pub type VdSysCfg = crate::Reg; +#[doc = "System Voltage Detect Configuration"] +pub mod vd_sys_cfg; +#[doc = "EVD_CFG (rw) register accessor: External Voltage Domain Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`evd_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evd_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evd_cfg`] module"] +#[doc(alias = "EVD_CFG")] +pub type EvdCfg = crate::Reg; +#[doc = "External Voltage Domain Configuration"] +pub mod evd_cfg; +#[doc = "CORELDO_CFG (r) register accessor: LDO_CORE Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`coreldo_cfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@coreldo_cfg`] module"] +#[doc(alias = "CORELDO_CFG")] +pub type CoreldoCfg = crate::Reg; +#[doc = "LDO_CORE Configuration"] +pub mod coreldo_cfg; diff --git a/mcxa276-pac/src/spc0/active_cfg.rs b/mcxa276-pac/src/spc0/active_cfg.rs new file mode 100644 index 000000000..683f63eca --- /dev/null +++ b/mcxa276-pac/src/spc0/active_cfg.rs @@ -0,0 +1,504 @@ +#[doc = "Register `ACTIVE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ACTIVE_CFG` writer"] +pub type W = crate::W; +#[doc = "LDO_CORE VDD Drive Strength\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoreldoVddDs { + #[doc = "0: Low"] + Low = 0, + #[doc = "1: Normal"] + Normal = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoreldoVddDs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORELDO_VDD_DS` reader - LDO_CORE VDD Drive Strength"] +pub type CoreldoVddDsR = crate::BitReader; +impl CoreldoVddDsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoreldoVddDs { + match self.bits { + false => CoreldoVddDs::Low, + true => CoreldoVddDs::Normal, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == CoreldoVddDs::Low + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == CoreldoVddDs::Normal + } +} +#[doc = "Field `CORELDO_VDD_DS` writer - LDO_CORE VDD Drive Strength"] +pub type CoreldoVddDsW<'a, REG> = crate::BitWriter<'a, REG, CoreldoVddDs>; +impl<'a, REG> CoreldoVddDsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(CoreldoVddDs::Low) + } + #[doc = "Normal"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(CoreldoVddDs::Normal) + } +} +#[doc = "LDO_CORE VDD Regulator Voltage Level\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CoreldoVddLvl { + #[doc = "1: Regulate to mid voltage (1.0 V)"] + Mid = 1, + #[doc = "2: Regulate to normal voltage (1.1 V)"] + Normal = 2, + #[doc = "3: Regulate to overdrive voltage (1.15 V)"] + Over = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CoreldoVddLvl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CoreldoVddLvl { + type Ux = u8; +} +impl crate::IsEnum for CoreldoVddLvl {} +#[doc = "Field `CORELDO_VDD_LVL` reader - LDO_CORE VDD Regulator Voltage Level"] +pub type CoreldoVddLvlR = crate::FieldReader; +impl CoreldoVddLvlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(CoreldoVddLvl::Mid), + 2 => Some(CoreldoVddLvl::Normal), + 3 => Some(CoreldoVddLvl::Over), + _ => None, + } + } + #[doc = "Regulate to mid voltage (1.0 V)"] + #[inline(always)] + pub fn is_mid(&self) -> bool { + *self == CoreldoVddLvl::Mid + } + #[doc = "Regulate to normal voltage (1.1 V)"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == CoreldoVddLvl::Normal + } + #[doc = "Regulate to overdrive voltage (1.15 V)"] + #[inline(always)] + pub fn is_over(&self) -> bool { + *self == CoreldoVddLvl::Over + } +} +#[doc = "Field `CORELDO_VDD_LVL` writer - LDO_CORE VDD Regulator Voltage Level"] +pub type CoreldoVddLvlW<'a, REG> = crate::FieldWriter<'a, REG, 2, CoreldoVddLvl>; +impl<'a, REG> CoreldoVddLvlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Regulate to mid voltage (1.0 V)"] + #[inline(always)] + pub fn mid(self) -> &'a mut crate::W { + self.variant(CoreldoVddLvl::Mid) + } + #[doc = "Regulate to normal voltage (1.1 V)"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(CoreldoVddLvl::Normal) + } + #[doc = "Regulate to overdrive voltage (1.15 V)"] + #[inline(always)] + pub fn over(self) -> &'a mut crate::W { + self.variant(CoreldoVddLvl::Over) + } +} +#[doc = "Bandgap Mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Bgmode { + #[doc = "0: Bandgap disabled"] + Bgmode0 = 0, + #[doc = "1: Bandgap enabled, buffer disabled"] + Bgmode01 = 1, + #[doc = "2: Bandgap enabled, buffer enabled"] + Bgmode10 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Bgmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Bgmode { + type Ux = u8; +} +impl crate::IsEnum for Bgmode {} +#[doc = "Field `BGMODE` reader - Bandgap Mode"] +pub type BgmodeR = crate::FieldReader; +impl BgmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Bgmode::Bgmode0), + 1 => Some(Bgmode::Bgmode01), + 2 => Some(Bgmode::Bgmode10), + _ => None, + } + } + #[doc = "Bandgap disabled"] + #[inline(always)] + pub fn is_bgmode0(&self) -> bool { + *self == Bgmode::Bgmode0 + } + #[doc = "Bandgap enabled, buffer disabled"] + #[inline(always)] + pub fn is_bgmode01(&self) -> bool { + *self == Bgmode::Bgmode01 + } + #[doc = "Bandgap enabled, buffer enabled"] + #[inline(always)] + pub fn is_bgmode10(&self) -> bool { + *self == Bgmode::Bgmode10 + } +} +#[doc = "Field `BGMODE` writer - Bandgap Mode"] +pub type BgmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bgmode>; +impl<'a, REG> BgmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Bandgap disabled"] + #[inline(always)] + pub fn bgmode0(self) -> &'a mut crate::W { + self.variant(Bgmode::Bgmode0) + } + #[doc = "Bandgap enabled, buffer disabled"] + #[inline(always)] + pub fn bgmode01(self) -> &'a mut crate::W { + self.variant(Bgmode::Bgmode01) + } + #[doc = "Bandgap enabled, buffer enabled"] + #[inline(always)] + pub fn bgmode10(self) -> &'a mut crate::W { + self.variant(Bgmode::Bgmode10) + } +} +#[doc = "VDD Voltage Detect Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VddVdDisable { + #[doc = "0: Enable"] + Enable = 0, + #[doc = "1: Disable"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VddVdDisable) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VDD_VD_DISABLE` reader - VDD Voltage Detect Disable"] +pub type VddVdDisableR = crate::BitReader; +impl VddVdDisableR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VddVdDisable { + match self.bits { + false => VddVdDisable::Enable, + true => VddVdDisable::Disable, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == VddVdDisable::Enable + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == VddVdDisable::Disable + } +} +#[doc = "Field `VDD_VD_DISABLE` writer - VDD Voltage Detect Disable"] +pub type VddVdDisableW<'a, REG> = crate::BitWriter<'a, REG, VddVdDisable>; +impl<'a, REG> VddVdDisableW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(VddVdDisable::Enable) + } + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(VddVdDisable::Disable) + } +} +#[doc = "Core Low-Voltage Detection Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoreLvde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoreLvde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORE_LVDE` reader - Core Low-Voltage Detection Enable"] +pub type CoreLvdeR = crate::BitReader; +impl CoreLvdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoreLvde { + match self.bits { + false => CoreLvde::Disable, + true => CoreLvde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CoreLvde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CoreLvde::Enable + } +} +#[doc = "Field `CORE_LVDE` writer - Core Low-Voltage Detection Enable"] +pub type CoreLvdeW<'a, REG> = crate::BitWriter<'a, REG, CoreLvde>; +impl<'a, REG> CoreLvdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(CoreLvde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(CoreLvde::Enable) + } +} +#[doc = "System Low-Voltage Detection Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysLvde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysLvde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYS_LVDE` reader - System Low-Voltage Detection Enable"] +pub type SysLvdeR = crate::BitReader; +impl SysLvdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysLvde { + match self.bits { + false => SysLvde::Disable, + true => SysLvde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SysLvde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SysLvde::Enable + } +} +#[doc = "Field `SYS_LVDE` writer - System Low-Voltage Detection Enable"] +pub type SysLvdeW<'a, REG> = crate::BitWriter<'a, REG, SysLvde>; +impl<'a, REG> SysLvdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SysLvde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SysLvde::Enable) + } +} +#[doc = "System High-Voltage Detection Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysHvde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysHvde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYS_HVDE` reader - System High-Voltage Detection Enable"] +pub type SysHvdeR = crate::BitReader; +impl SysHvdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysHvde { + match self.bits { + false => SysHvde::Disable, + true => SysHvde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SysHvde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SysHvde::Enable + } +} +#[doc = "Field `SYS_HVDE` writer - System High-Voltage Detection Enable"] +pub type SysHvdeW<'a, REG> = crate::BitWriter<'a, REG, SysHvde>; +impl<'a, REG> SysHvdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SysHvde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SysHvde::Enable) + } +} +impl R { + #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] + #[inline(always)] + pub fn coreldo_vdd_ds(&self) -> CoreldoVddDsR { + CoreldoVddDsR::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] + #[inline(always)] + pub fn coreldo_vdd_lvl(&self) -> CoreldoVddLvlR { + CoreldoVddLvlR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 20:21 - Bandgap Mode"] + #[inline(always)] + pub fn bgmode(&self) -> BgmodeR { + BgmodeR::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 23 - VDD Voltage Detect Disable"] + #[inline(always)] + pub fn vdd_vd_disable(&self) -> VddVdDisableR { + VddVdDisableR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Core Low-Voltage Detection Enable"] + #[inline(always)] + pub fn core_lvde(&self) -> CoreLvdeR { + CoreLvdeR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - System Low-Voltage Detection Enable"] + #[inline(always)] + pub fn sys_lvde(&self) -> SysLvdeR { + SysLvdeR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 28 - System High-Voltage Detection Enable"] + #[inline(always)] + pub fn sys_hvde(&self) -> SysHvdeR { + SysHvdeR::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] + #[inline(always)] + pub fn coreldo_vdd_ds(&mut self) -> CoreldoVddDsW { + CoreldoVddDsW::new(self, 0) + } + #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] + #[inline(always)] + pub fn coreldo_vdd_lvl(&mut self) -> CoreldoVddLvlW { + CoreldoVddLvlW::new(self, 2) + } + #[doc = "Bits 20:21 - Bandgap Mode"] + #[inline(always)] + pub fn bgmode(&mut self) -> BgmodeW { + BgmodeW::new(self, 20) + } + #[doc = "Bit 23 - VDD Voltage Detect Disable"] + #[inline(always)] + pub fn vdd_vd_disable(&mut self) -> VddVdDisableW { + VddVdDisableW::new(self, 23) + } + #[doc = "Bit 24 - Core Low-Voltage Detection Enable"] + #[inline(always)] + pub fn core_lvde(&mut self) -> CoreLvdeW { + CoreLvdeW::new(self, 24) + } + #[doc = "Bit 25 - System Low-Voltage Detection Enable"] + #[inline(always)] + pub fn sys_lvde(&mut self) -> SysLvdeW { + SysLvdeW::new(self, 25) + } + #[doc = "Bit 28 - System High-Voltage Detection Enable"] + #[inline(always)] + pub fn sys_hvde(&mut self) -> SysHvdeW { + SysHvdeW::new(self, 28) + } +} +#[doc = "Active Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ActiveCfgSpec; +impl crate::RegisterSpec for ActiveCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`active_cfg::R`](R) reader structure"] +impl crate::Readable for ActiveCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`active_cfg::W`](W) writer structure"] +impl crate::Writable for ActiveCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ACTIVE_CFG to value 0x1310_0005"] +impl crate::Resettable for ActiveCfgSpec { + const RESET_VALUE: u32 = 0x1310_0005; +} diff --git a/mcxa276-pac/src/spc0/active_cfg1.rs b/mcxa276-pac/src/spc0/active_cfg1.rs new file mode 100644 index 000000000..47a95fa3c --- /dev/null +++ b/mcxa276-pac/src/spc0/active_cfg1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `ACTIVE_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `ACTIVE_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `SOC_CNTRL` reader - Active Config Chip Control"] +pub type SocCntrlR = crate::FieldReader; +#[doc = "Field `SOC_CNTRL` writer - Active Config Chip Control"] +pub type SocCntrlW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Active Config Chip Control"] + #[inline(always)] + pub fn soc_cntrl(&self) -> SocCntrlR { + SocCntrlR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Active Config Chip Control"] + #[inline(always)] + pub fn soc_cntrl(&mut self) -> SocCntrlW { + SocCntrlW::new(self, 0) + } +} +#[doc = "Active Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ActiveCfg1Spec; +impl crate::RegisterSpec for ActiveCfg1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`active_cfg1::R`](R) reader structure"] +impl crate::Readable for ActiveCfg1Spec {} +#[doc = "`write(|w| ..)` method takes [`active_cfg1::W`](W) writer structure"] +impl crate::Writable for ActiveCfg1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ACTIVE_CFG1 to value 0x02"] +impl crate::Resettable for ActiveCfg1Spec { + const RESET_VALUE: u32 = 0x02; +} diff --git a/mcxa276-pac/src/spc0/active_vdelay.rs b/mcxa276-pac/src/spc0/active_vdelay.rs new file mode 100644 index 000000000..1b18f95bc --- /dev/null +++ b/mcxa276-pac/src/spc0/active_vdelay.rs @@ -0,0 +1,37 @@ +#[doc = "Register `ACTIVE_VDELAY` reader"] +pub type R = crate::R; +#[doc = "Register `ACTIVE_VDELAY` writer"] +pub type W = crate::W; +#[doc = "Field `ACTIVE_VDELAY` reader - Active Voltage Delay"] +pub type ActiveVdelayR = crate::FieldReader; +#[doc = "Field `ACTIVE_VDELAY` writer - Active Voltage Delay"] +pub type ActiveVdelayW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Active Voltage Delay"] + #[inline(always)] + pub fn active_vdelay(&self) -> ActiveVdelayR { + ActiveVdelayR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Active Voltage Delay"] + #[inline(always)] + pub fn active_vdelay(&mut self) -> ActiveVdelayW { + ActiveVdelayW::new(self, 0) + } +} +#[doc = "Active Voltage Trim Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`active_vdelay::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_vdelay::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ActiveVdelaySpec; +impl crate::RegisterSpec for ActiveVdelaySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`active_vdelay::R`](R) reader structure"] +impl crate::Readable for ActiveVdelaySpec {} +#[doc = "`write(|w| ..)` method takes [`active_vdelay::W`](W) writer structure"] +impl crate::Writable for ActiveVdelaySpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ACTIVE_VDELAY to value 0xc8"] +impl crate::Resettable for ActiveVdelaySpec { + const RESET_VALUE: u32 = 0xc8; +} diff --git a/mcxa276-pac/src/spc0/coreldo_cfg.rs b/mcxa276-pac/src/spc0/coreldo_cfg.rs new file mode 100644 index 000000000..cc45ed404 --- /dev/null +++ b/mcxa276-pac/src/spc0/coreldo_cfg.rs @@ -0,0 +1,16 @@ +#[doc = "Register `CORELDO_CFG` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "LDO_CORE Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`coreldo_cfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CoreldoCfgSpec; +impl crate::RegisterSpec for CoreldoCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`coreldo_cfg::R`](R) reader structure"] +impl crate::Readable for CoreldoCfgSpec {} +#[doc = "`reset()` method sets CORELDO_CFG to value 0"] +impl crate::Resettable for CoreldoCfgSpec {} diff --git a/mcxa276-pac/src/spc0/evd_cfg.rs b/mcxa276-pac/src/spc0/evd_cfg.rs new file mode 100644 index 000000000..5e4f55c49 --- /dev/null +++ b/mcxa276-pac/src/spc0/evd_cfg.rs @@ -0,0 +1,56 @@ +#[doc = "Register `EVD_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `EVD_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `EVDISO` reader - External Voltage Domain Isolation"] +pub type EvdisoR = crate::FieldReader; +#[doc = "Field `EVDISO` writer - External Voltage Domain Isolation"] +pub type EvdisoW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `EVDLPISO` reader - External Voltage Domain Low-Power Isolation"] +pub type EvdlpisoR = crate::FieldReader; +#[doc = "Field `EVDLPISO` writer - External Voltage Domain Low-Power Isolation"] +pub type EvdlpisoW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `EVDSTAT` reader - External Voltage Domain Status"] +pub type EvdstatR = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - External Voltage Domain Isolation"] + #[inline(always)] + pub fn evdiso(&self) -> EvdisoR { + EvdisoR::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:10 - External Voltage Domain Low-Power Isolation"] + #[inline(always)] + pub fn evdlpiso(&self) -> EvdlpisoR { + EvdlpisoR::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 16:18 - External Voltage Domain Status"] + #[inline(always)] + pub fn evdstat(&self) -> EvdstatR { + EvdstatR::new(((self.bits >> 16) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - External Voltage Domain Isolation"] + #[inline(always)] + pub fn evdiso(&mut self) -> EvdisoW { + EvdisoW::new(self, 0) + } + #[doc = "Bits 8:10 - External Voltage Domain Low-Power Isolation"] + #[inline(always)] + pub fn evdlpiso(&mut self) -> EvdlpisoW { + EvdlpisoW::new(self, 8) + } +} +#[doc = "External Voltage Domain Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`evd_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evd_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EvdCfgSpec; +impl crate::RegisterSpec for EvdCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`evd_cfg::R`](R) reader structure"] +impl crate::Readable for EvdCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`evd_cfg::W`](W) writer structure"] +impl crate::Writable for EvdCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EVD_CFG to value 0"] +impl crate::Resettable for EvdCfgSpec {} diff --git a/mcxa276-pac/src/spc0/lp_cfg.rs b/mcxa276-pac/src/spc0/lp_cfg.rs new file mode 100644 index 000000000..4a56f3ab1 --- /dev/null +++ b/mcxa276-pac/src/spc0/lp_cfg.rs @@ -0,0 +1,567 @@ +#[doc = "Register `LP_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CFG` writer"] +pub type W = crate::W; +#[doc = "LDO_CORE VDD Drive Strength\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoreldoVddDs { + #[doc = "0: Low"] + Low = 0, + #[doc = "1: Normal"] + Normal = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoreldoVddDs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORELDO_VDD_DS` reader - LDO_CORE VDD Drive Strength"] +pub type CoreldoVddDsR = crate::BitReader; +impl CoreldoVddDsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoreldoVddDs { + match self.bits { + false => CoreldoVddDs::Low, + true => CoreldoVddDs::Normal, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == CoreldoVddDs::Low + } + #[doc = "Normal"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == CoreldoVddDs::Normal + } +} +#[doc = "Field `CORELDO_VDD_DS` writer - LDO_CORE VDD Drive Strength"] +pub type CoreldoVddDsW<'a, REG> = crate::BitWriter<'a, REG, CoreldoVddDs>; +impl<'a, REG> CoreldoVddDsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(CoreldoVddDs::Low) + } + #[doc = "Normal"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(CoreldoVddDs::Normal) + } +} +#[doc = "LDO_CORE VDD Regulator Voltage Level\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CoreldoVddLvl { + #[doc = "1: Mid voltage (1.0 V)"] + Mid = 1, + #[doc = "2: Normal voltage (1.1 V)"] + Normal = 2, + #[doc = "3: Overdrive voltage (1.15 V)"] + Over = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CoreldoVddLvl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CoreldoVddLvl { + type Ux = u8; +} +impl crate::IsEnum for CoreldoVddLvl {} +#[doc = "Field `CORELDO_VDD_LVL` reader - LDO_CORE VDD Regulator Voltage Level"] +pub type CoreldoVddLvlR = crate::FieldReader; +impl CoreldoVddLvlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(CoreldoVddLvl::Mid), + 2 => Some(CoreldoVddLvl::Normal), + 3 => Some(CoreldoVddLvl::Over), + _ => None, + } + } + #[doc = "Mid voltage (1.0 V)"] + #[inline(always)] + pub fn is_mid(&self) -> bool { + *self == CoreldoVddLvl::Mid + } + #[doc = "Normal voltage (1.1 V)"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == CoreldoVddLvl::Normal + } + #[doc = "Overdrive voltage (1.15 V)"] + #[inline(always)] + pub fn is_over(&self) -> bool { + *self == CoreldoVddLvl::Over + } +} +#[doc = "Field `CORELDO_VDD_LVL` writer - LDO_CORE VDD Regulator Voltage Level"] +pub type CoreldoVddLvlW<'a, REG> = crate::FieldWriter<'a, REG, 2, CoreldoVddLvl>; +impl<'a, REG> CoreldoVddLvlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Mid voltage (1.0 V)"] + #[inline(always)] + pub fn mid(self) -> &'a mut crate::W { + self.variant(CoreldoVddLvl::Mid) + } + #[doc = "Normal voltage (1.1 V)"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(CoreldoVddLvl::Normal) + } + #[doc = "Overdrive voltage (1.15 V)"] + #[inline(always)] + pub fn over(self) -> &'a mut crate::W { + self.variant(CoreldoVddLvl::Over) + } +} +#[doc = "SRAM_LDO Deep Power Low Power IREF Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SramldoDpdOn { + #[doc = "0: Low Power IREF is disabled for power saving in Deep Power Down mode"] + Disabled = 0, + #[doc = "1: Low Power IREF is enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SramldoDpdOn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRAMLDO_DPD_ON` reader - SRAM_LDO Deep Power Low Power IREF Enable"] +pub type SramldoDpdOnR = crate::BitReader; +impl SramldoDpdOnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SramldoDpdOn { + match self.bits { + false => SramldoDpdOn::Disabled, + true => SramldoDpdOn::Enabled, + } + } + #[doc = "Low Power IREF is disabled for power saving in Deep Power Down mode"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SramldoDpdOn::Disabled + } + #[doc = "Low Power IREF is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SramldoDpdOn::Enabled + } +} +#[doc = "Field `SRAMLDO_DPD_ON` writer - SRAM_LDO Deep Power Low Power IREF Enable"] +pub type SramldoDpdOnW<'a, REG> = crate::BitWriter<'a, REG, SramldoDpdOn>; +impl<'a, REG> SramldoDpdOnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low Power IREF is disabled for power saving in Deep Power Down mode"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(SramldoDpdOn::Disabled) + } + #[doc = "Low Power IREF is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(SramldoDpdOn::Enabled) + } +} +#[doc = "Bandgap Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Bgmode { + #[doc = "0: Bandgap disabled"] + Bgmode0 = 0, + #[doc = "1: Bandgap enabled, buffer disabled"] + Bgmode01 = 1, + #[doc = "2: Bandgap enabled, buffer enabled"] + Bgmode10 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Bgmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Bgmode { + type Ux = u8; +} +impl crate::IsEnum for Bgmode {} +#[doc = "Field `BGMODE` reader - Bandgap Mode"] +pub type BgmodeR = crate::FieldReader; +impl BgmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Bgmode::Bgmode0), + 1 => Some(Bgmode::Bgmode01), + 2 => Some(Bgmode::Bgmode10), + _ => None, + } + } + #[doc = "Bandgap disabled"] + #[inline(always)] + pub fn is_bgmode0(&self) -> bool { + *self == Bgmode::Bgmode0 + } + #[doc = "Bandgap enabled, buffer disabled"] + #[inline(always)] + pub fn is_bgmode01(&self) -> bool { + *self == Bgmode::Bgmode01 + } + #[doc = "Bandgap enabled, buffer enabled"] + #[inline(always)] + pub fn is_bgmode10(&self) -> bool { + *self == Bgmode::Bgmode10 + } +} +#[doc = "Field `BGMODE` writer - Bandgap Mode"] +pub type BgmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bgmode>; +impl<'a, REG> BgmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Bandgap disabled"] + #[inline(always)] + pub fn bgmode0(self) -> &'a mut crate::W { + self.variant(Bgmode::Bgmode0) + } + #[doc = "Bandgap enabled, buffer disabled"] + #[inline(always)] + pub fn bgmode01(self) -> &'a mut crate::W { + self.variant(Bgmode::Bgmode01) + } + #[doc = "Bandgap enabled, buffer enabled"] + #[inline(always)] + pub fn bgmode10(self) -> &'a mut crate::W { + self.variant(Bgmode::Bgmode10) + } +} +#[doc = "Low-Power IREF Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LpIrefen { + #[doc = "0: Disable for power saving in Deep Power Down mode"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LpIrefen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LP_IREFEN` reader - Low-Power IREF Enable"] +pub type LpIrefenR = crate::BitReader; +impl LpIrefenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LpIrefen { + match self.bits { + false => LpIrefen::Disable, + true => LpIrefen::Enable, + } + } + #[doc = "Disable for power saving in Deep Power Down mode"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == LpIrefen::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == LpIrefen::Enable + } +} +#[doc = "Field `LP_IREFEN` writer - Low-Power IREF Enable"] +pub type LpIrefenW<'a, REG> = crate::BitWriter<'a, REG, LpIrefen>; +impl<'a, REG> LpIrefenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable for power saving in Deep Power Down mode"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(LpIrefen::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(LpIrefen::Enable) + } +} +#[doc = "Core Low Voltage Detect Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CoreLvde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CoreLvde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORE_LVDE` reader - Core Low Voltage Detect Enable"] +pub type CoreLvdeR = crate::BitReader; +impl CoreLvdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CoreLvde { + match self.bits { + false => CoreLvde::Disable, + true => CoreLvde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CoreLvde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == CoreLvde::Enable + } +} +#[doc = "Field `CORE_LVDE` writer - Core Low Voltage Detect Enable"] +pub type CoreLvdeW<'a, REG> = crate::BitWriter<'a, REG, CoreLvde>; +impl<'a, REG> CoreLvdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(CoreLvde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(CoreLvde::Enable) + } +} +#[doc = "System Low Voltage Detect Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysLvde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysLvde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYS_LVDE` reader - System Low Voltage Detect Enable"] +pub type SysLvdeR = crate::BitReader; +impl SysLvdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysLvde { + match self.bits { + false => SysLvde::Disable, + true => SysLvde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SysLvde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SysLvde::Enable + } +} +#[doc = "Field `SYS_LVDE` writer - System Low Voltage Detect Enable"] +pub type SysLvdeW<'a, REG> = crate::BitWriter<'a, REG, SysLvde>; +impl<'a, REG> SysLvdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SysLvde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SysLvde::Enable) + } +} +#[doc = "System High Voltage Detect Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysHvde { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysHvde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYS_HVDE` reader - System High Voltage Detect Enable"] +pub type SysHvdeR = crate::BitReader; +impl SysHvdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysHvde { + match self.bits { + false => SysHvde::Disable, + true => SysHvde::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SysHvde::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SysHvde::Enable + } +} +#[doc = "Field `SYS_HVDE` writer - System High Voltage Detect Enable"] +pub type SysHvdeW<'a, REG> = crate::BitWriter<'a, REG, SysHvde>; +impl<'a, REG> SysHvdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SysHvde::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SysHvde::Enable) + } +} +impl R { + #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] + #[inline(always)] + pub fn coreldo_vdd_ds(&self) -> CoreldoVddDsR { + CoreldoVddDsR::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] + #[inline(always)] + pub fn coreldo_vdd_lvl(&self) -> CoreldoVddLvlR { + CoreldoVddLvlR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 19 - SRAM_LDO Deep Power Low Power IREF Enable"] + #[inline(always)] + pub fn sramldo_dpd_on(&self) -> SramldoDpdOnR { + SramldoDpdOnR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:21 - Bandgap Mode"] + #[inline(always)] + pub fn bgmode(&self) -> BgmodeR { + BgmodeR::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 23 - Low-Power IREF Enable"] + #[inline(always)] + pub fn lp_irefen(&self) -> LpIrefenR { + LpIrefenR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Core Low Voltage Detect Enable"] + #[inline(always)] + pub fn core_lvde(&self) -> CoreLvdeR { + CoreLvdeR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - System Low Voltage Detect Enable"] + #[inline(always)] + pub fn sys_lvde(&self) -> SysLvdeR { + SysLvdeR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 28 - System High Voltage Detect Enable"] + #[inline(always)] + pub fn sys_hvde(&self) -> SysHvdeR { + SysHvdeR::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] + #[inline(always)] + pub fn coreldo_vdd_ds(&mut self) -> CoreldoVddDsW { + CoreldoVddDsW::new(self, 0) + } + #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] + #[inline(always)] + pub fn coreldo_vdd_lvl(&mut self) -> CoreldoVddLvlW { + CoreldoVddLvlW::new(self, 2) + } + #[doc = "Bit 19 - SRAM_LDO Deep Power Low Power IREF Enable"] + #[inline(always)] + pub fn sramldo_dpd_on(&mut self) -> SramldoDpdOnW { + SramldoDpdOnW::new(self, 19) + } + #[doc = "Bits 20:21 - Bandgap Mode"] + #[inline(always)] + pub fn bgmode(&mut self) -> BgmodeW { + BgmodeW::new(self, 20) + } + #[doc = "Bit 23 - Low-Power IREF Enable"] + #[inline(always)] + pub fn lp_irefen(&mut self) -> LpIrefenW { + LpIrefenW::new(self, 23) + } + #[doc = "Bit 24 - Core Low Voltage Detect Enable"] + #[inline(always)] + pub fn core_lvde(&mut self) -> CoreLvdeW { + CoreLvdeW::new(self, 24) + } + #[doc = "Bit 25 - System Low Voltage Detect Enable"] + #[inline(always)] + pub fn sys_lvde(&mut self) -> SysLvdeW { + SysLvdeW::new(self, 25) + } + #[doc = "Bit 28 - System High Voltage Detect Enable"] + #[inline(always)] + pub fn sys_hvde(&mut self) -> SysHvdeW { + SysHvdeW::new(self, 28) + } +} +#[doc = "Low-Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LpCfgSpec; +impl crate::RegisterSpec for LpCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cfg::R`](R) reader structure"] +impl crate::Readable for LpCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`lp_cfg::W`](W) writer structure"] +impl crate::Writable for LpCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LP_CFG to value 0x0008_0004"] +impl crate::Resettable for LpCfgSpec { + const RESET_VALUE: u32 = 0x0008_0004; +} diff --git a/mcxa276-pac/src/spc0/lp_cfg1.rs b/mcxa276-pac/src/spc0/lp_cfg1.rs new file mode 100644 index 000000000..eb22299d9 --- /dev/null +++ b/mcxa276-pac/src/spc0/lp_cfg1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `LP_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `SOC_CNTRL` reader - Low-Power Configuration Chip Control"] +pub type SocCntrlR = crate::FieldReader; +#[doc = "Field `SOC_CNTRL` writer - Low-Power Configuration Chip Control"] +pub type SocCntrlW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Low-Power Configuration Chip Control"] + #[inline(always)] + pub fn soc_cntrl(&self) -> SocCntrlR { + SocCntrlR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Low-Power Configuration Chip Control"] + #[inline(always)] + pub fn soc_cntrl(&mut self) -> SocCntrlW { + SocCntrlW::new(self, 0) + } +} +#[doc = "Low Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LpCfg1Spec; +impl crate::RegisterSpec for LpCfg1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cfg1::R`](R) reader structure"] +impl crate::Readable for LpCfg1Spec {} +#[doc = "`write(|w| ..)` method takes [`lp_cfg1::W`](W) writer structure"] +impl crate::Writable for LpCfg1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LP_CFG1 to value 0x02"] +impl crate::Resettable for LpCfg1Spec { + const RESET_VALUE: u32 = 0x02; +} diff --git a/mcxa276-pac/src/spc0/lpreq_cfg.rs b/mcxa276-pac/src/spc0/lpreq_cfg.rs new file mode 100644 index 000000000..e3d40e69d --- /dev/null +++ b/mcxa276-pac/src/spc0/lpreq_cfg.rs @@ -0,0 +1,230 @@ +#[doc = "Register `LPREQ_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `LPREQ_CFG` writer"] +pub type W = crate::W; +#[doc = "Low-Power Request Output Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpreqoe { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpreqoe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPREQOE` reader - Low-Power Request Output Enable"] +pub type LpreqoeR = crate::BitReader; +impl LpreqoeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpreqoe { + match self.bits { + false => Lpreqoe::Disable, + true => Lpreqoe::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lpreqoe::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lpreqoe::Enable + } +} +#[doc = "Field `LPREQOE` writer - Low-Power Request Output Enable"] +pub type LpreqoeW<'a, REG> = crate::BitWriter<'a, REG, Lpreqoe>; +impl<'a, REG> LpreqoeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lpreqoe::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lpreqoe::Enable) + } +} +#[doc = "Low-Power Request Output Pin Polarity Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lpreqpol { + #[doc = "0: High"] + High = 0, + #[doc = "1: Low"] + Low = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lpreqpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPREQPOL` reader - Low-Power Request Output Pin Polarity Control"] +pub type LpreqpolR = crate::BitReader; +impl LpreqpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lpreqpol { + match self.bits { + false => Lpreqpol::High, + true => Lpreqpol::Low, + } + } + #[doc = "High"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == Lpreqpol::High + } + #[doc = "Low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == Lpreqpol::Low + } +} +#[doc = "Field `LPREQPOL` writer - Low-Power Request Output Pin Polarity Control"] +pub type LpreqpolW<'a, REG> = crate::BitWriter<'a, REG, Lpreqpol>; +impl<'a, REG> LpreqpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "High"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(Lpreqpol::High) + } + #[doc = "Low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(Lpreqpol::Low) + } +} +#[doc = "Low-Power Request Output Override\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Lpreqov { + #[doc = "0: Not forced"] + ForceNo = 0, + #[doc = "2: Forced low (ignore LPREQPOL settings)"] + ForceLow = 2, + #[doc = "3: Forced high (ignore LPREQPOL settings)"] + ForceHigh = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Lpreqov) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Lpreqov { + type Ux = u8; +} +impl crate::IsEnum for Lpreqov {} +#[doc = "Field `LPREQOV` reader - Low-Power Request Output Override"] +pub type LpreqovR = crate::FieldReader; +impl LpreqovR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Lpreqov::ForceNo), + 2 => Some(Lpreqov::ForceLow), + 3 => Some(Lpreqov::ForceHigh), + _ => None, + } + } + #[doc = "Not forced"] + #[inline(always)] + pub fn is_force_no(&self) -> bool { + *self == Lpreqov::ForceNo + } + #[doc = "Forced low (ignore LPREQPOL settings)"] + #[inline(always)] + pub fn is_force_low(&self) -> bool { + *self == Lpreqov::ForceLow + } + #[doc = "Forced high (ignore LPREQPOL settings)"] + #[inline(always)] + pub fn is_force_high(&self) -> bool { + *self == Lpreqov::ForceHigh + } +} +#[doc = "Field `LPREQOV` writer - Low-Power Request Output Override"] +pub type LpreqovW<'a, REG> = crate::FieldWriter<'a, REG, 2, Lpreqov>; +impl<'a, REG> LpreqovW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Not forced"] + #[inline(always)] + pub fn force_no(self) -> &'a mut crate::W { + self.variant(Lpreqov::ForceNo) + } + #[doc = "Forced low (ignore LPREQPOL settings)"] + #[inline(always)] + pub fn force_low(self) -> &'a mut crate::W { + self.variant(Lpreqov::ForceLow) + } + #[doc = "Forced high (ignore LPREQPOL settings)"] + #[inline(always)] + pub fn force_high(self) -> &'a mut crate::W { + self.variant(Lpreqov::ForceHigh) + } +} +impl R { + #[doc = "Bit 0 - Low-Power Request Output Enable"] + #[inline(always)] + pub fn lpreqoe(&self) -> LpreqoeR { + LpreqoeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Low-Power Request Output Pin Polarity Control"] + #[inline(always)] + pub fn lpreqpol(&self) -> LpreqpolR { + LpreqpolR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Low-Power Request Output Override"] + #[inline(always)] + pub fn lpreqov(&self) -> LpreqovR { + LpreqovR::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Low-Power Request Output Enable"] + #[inline(always)] + pub fn lpreqoe(&mut self) -> LpreqoeW { + LpreqoeW::new(self, 0) + } + #[doc = "Bit 1 - Low-Power Request Output Pin Polarity Control"] + #[inline(always)] + pub fn lpreqpol(&mut self) -> LpreqpolW { + LpreqpolW::new(self, 1) + } + #[doc = "Bits 2:3 - Low-Power Request Output Override"] + #[inline(always)] + pub fn lpreqov(&mut self) -> LpreqovW { + LpreqovW::new(self, 2) + } +} +#[doc = "Low-Power Request Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lpreq_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpreq_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LpreqCfgSpec; +impl crate::RegisterSpec for LpreqCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpreq_cfg::R`](R) reader structure"] +impl crate::Readable for LpreqCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`lpreq_cfg::W`](W) writer structure"] +impl crate::Writable for LpreqCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPREQ_CFG to value 0"] +impl crate::Resettable for LpreqCfgSpec {} diff --git a/mcxa276-pac/src/spc0/lpwkup_delay.rs b/mcxa276-pac/src/spc0/lpwkup_delay.rs new file mode 100644 index 000000000..c3fc96585 --- /dev/null +++ b/mcxa276-pac/src/spc0/lpwkup_delay.rs @@ -0,0 +1,35 @@ +#[doc = "Register `LPWKUP_DELAY` reader"] +pub type R = crate::R; +#[doc = "Register `LPWKUP_DELAY` writer"] +pub type W = crate::W; +#[doc = "Field `LPWKUP_DELAY` reader - Low-Power Wake-Up Delay"] +pub type LpwkupDelayR = crate::FieldReader; +#[doc = "Field `LPWKUP_DELAY` writer - Low-Power Wake-Up Delay"] +pub type LpwkupDelayW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Low-Power Wake-Up Delay"] + #[inline(always)] + pub fn lpwkup_delay(&self) -> LpwkupDelayR { + LpwkupDelayR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Low-Power Wake-Up Delay"] + #[inline(always)] + pub fn lpwkup_delay(&mut self) -> LpwkupDelayW { + LpwkupDelayW::new(self, 0) + } +} +#[doc = "Low Power Wake-Up Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`lpwkup_delay::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpwkup_delay::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LpwkupDelaySpec; +impl crate::RegisterSpec for LpwkupDelaySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpwkup_delay::R`](R) reader structure"] +impl crate::Readable for LpwkupDelaySpec {} +#[doc = "`write(|w| ..)` method takes [`lpwkup_delay::W`](W) writer structure"] +impl crate::Writable for LpwkupDelaySpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPWKUP_DELAY to value 0"] +impl crate::Resettable for LpwkupDelaySpec {} diff --git a/mcxa276-pac/src/spc0/pd_status0.rs b/mcxa276-pac/src/spc0/pd_status0.rs new file mode 100644 index 000000000..b3583f5f3 --- /dev/null +++ b/mcxa276-pac/src/spc0/pd_status0.rs @@ -0,0 +1,189 @@ +#[doc = "Register `PD_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Register `PD_STATUS0` writer"] +pub type W = crate::W; +#[doc = "Power Request Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PwrReqStatus { + #[doc = "0: Did not request"] + ReqNo = 0, + #[doc = "1: Requested"] + ReqYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PwrReqStatus) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWR_REQ_STATUS` reader - Power Request Status Flag"] +pub type PwrReqStatusR = crate::BitReader; +impl PwrReqStatusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PwrReqStatus { + match self.bits { + false => PwrReqStatus::ReqNo, + true => PwrReqStatus::ReqYes, + } + } + #[doc = "Did not request"] + #[inline(always)] + pub fn is_req_no(&self) -> bool { + *self == PwrReqStatus::ReqNo + } + #[doc = "Requested"] + #[inline(always)] + pub fn is_req_yes(&self) -> bool { + *self == PwrReqStatus::ReqYes + } +} +#[doc = "Power Domain Low Power Request Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PdLpReq { + #[doc = "0: Did not request"] + ReqNo = 0, + #[doc = "1: Requested"] + ReqYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PdLpReq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PD_LP_REQ` reader - Power Domain Low Power Request Flag"] +pub type PdLpReqR = crate::BitReader; +impl PdLpReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PdLpReq { + match self.bits { + false => PdLpReq::ReqNo, + true => PdLpReq::ReqYes, + } + } + #[doc = "Did not request"] + #[inline(always)] + pub fn is_req_no(&self) -> bool { + *self == PdLpReq::ReqNo + } + #[doc = "Requested"] + #[inline(always)] + pub fn is_req_yes(&self) -> bool { + *self == PdLpReq::ReqYes + } +} +#[doc = "Field `PD_LP_REQ` writer - Power Domain Low Power Request Flag"] +pub type PdLpReqW<'a, REG> = crate::BitWriter1C<'a, REG, PdLpReq>; +impl<'a, REG> PdLpReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Did not request"] + #[inline(always)] + pub fn req_no(self) -> &'a mut crate::W { + self.variant(PdLpReq::ReqNo) + } + #[doc = "Requested"] + #[inline(always)] + pub fn req_yes(self) -> &'a mut crate::W { + self.variant(PdLpReq::ReqYes) + } +} +#[doc = "Power Domain Low Power Mode Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LpMode { + #[doc = "0: SLEEP with system clock running"] + Mode0 = 0, + #[doc = "1: DSLEEP with system clock off"] + Mode1 = 1, + #[doc = "2: PDOWN with system clock off"] + Mode2 = 2, + #[doc = "8: DPDOWN with system clock off"] + Mode8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LpMode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LpMode { + type Ux = u8; +} +impl crate::IsEnum for LpMode {} +#[doc = "Field `LP_MODE` reader - Power Domain Low Power Mode Request"] +pub type LpModeR = crate::FieldReader; +impl LpModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(LpMode::Mode0), + 1 => Some(LpMode::Mode1), + 2 => Some(LpMode::Mode2), + 8 => Some(LpMode::Mode8), + _ => None, + } + } + #[doc = "SLEEP with system clock running"] + #[inline(always)] + pub fn is_mode0(&self) -> bool { + *self == LpMode::Mode0 + } + #[doc = "DSLEEP with system clock off"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + *self == LpMode::Mode1 + } + #[doc = "PDOWN with system clock off"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + *self == LpMode::Mode2 + } + #[doc = "DPDOWN with system clock off"] + #[inline(always)] + pub fn is_mode8(&self) -> bool { + *self == LpMode::Mode8 + } +} +impl R { + #[doc = "Bit 0 - Power Request Status Flag"] + #[inline(always)] + pub fn pwr_req_status(&self) -> PwrReqStatusR { + PwrReqStatusR::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Power Domain Low Power Request Flag"] + #[inline(always)] + pub fn pd_lp_req(&self) -> PdLpReqR { + PdLpReqR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:11 - Power Domain Low Power Mode Request"] + #[inline(always)] + pub fn lp_mode(&self) -> LpModeR { + LpModeR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 4 - Power Domain Low Power Request Flag"] + #[inline(always)] + pub fn pd_lp_req(&mut self) -> PdLpReqW { + PdLpReqW::new(self, 4) + } +} +#[doc = "SPC Power Domain Mode Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_status0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_status0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PdStatus0Spec; +impl crate::RegisterSpec for PdStatus0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pd_status0::R`](R) reader structure"] +impl crate::Readable for PdStatus0Spec {} +#[doc = "`write(|w| ..)` method takes [`pd_status0::W`](W) writer structure"] +impl crate::Writable for PdStatus0Spec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x10; +} +#[doc = "`reset()` method sets PD_STATUS0 to value 0"] +impl crate::Resettable for PdStatus0Spec {} diff --git a/mcxa276-pac/src/spc0/sc.rs b/mcxa276-pac/src/spc0/sc.rs new file mode 100644 index 000000000..77f14943f --- /dev/null +++ b/mcxa276-pac/src/spc0/sc.rs @@ -0,0 +1,203 @@ +#[doc = "Register `SC` reader"] +pub type R = crate::R; +#[doc = "Register `SC` writer"] +pub type W = crate::W; +#[doc = "SPC Busy Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Busy { + #[doc = "0: Not busy"] + BusyNo = 0, + #[doc = "1: Busy"] + BusyYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Busy) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUSY` reader - SPC Busy Status Flag"] +pub type BusyR = crate::BitReader; +impl BusyR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Busy { + match self.bits { + false => Busy::BusyNo, + true => Busy::BusyYes, + } + } + #[doc = "Not busy"] + #[inline(always)] + pub fn is_busy_no(&self) -> bool { + *self == Busy::BusyNo + } + #[doc = "Busy"] + #[inline(always)] + pub fn is_busy_yes(&self) -> bool { + *self == Busy::BusyYes + } +} +#[doc = "SPC Power Mode Configuration Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SpcLpReq { + #[doc = "0: SPC is in Active mode; the ACTIVE_CFG register has control"] + Active = 0, + #[doc = "1: All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register"] + LowPower = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SpcLpReq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPC_LP_REQ` reader - SPC Power Mode Configuration Status Flag"] +pub type SpcLpReqR = crate::BitReader; +impl SpcLpReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SpcLpReq { + match self.bits { + false => SpcLpReq::Active, + true => SpcLpReq::LowPower, + } + } + #[doc = "SPC is in Active mode; the ACTIVE_CFG register has control"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == SpcLpReq::Active + } + #[doc = "All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + *self == SpcLpReq::LowPower + } +} +#[doc = "Field `SPC_LP_REQ` writer - SPC Power Mode Configuration Status Flag"] +pub type SpcLpReqW<'a, REG> = crate::BitWriter1C<'a, REG, SpcLpReq>; +impl<'a, REG> SpcLpReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPC is in Active mode; the ACTIVE_CFG register has control"] + #[inline(always)] + pub fn active(self) -> &'a mut crate::W { + self.variant(SpcLpReq::Active) + } + #[doc = "All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register"] + #[inline(always)] + pub fn low_power(self) -> &'a mut crate::W { + self.variant(SpcLpReq::LowPower) + } +} +#[doc = "Power Domain Low-Power Mode Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SpcLpMode { + #[doc = "0: Sleep mode with system clock running"] + Mode0 = 0, + #[doc = "1: DSLEEP with system clock off"] + Mode1 = 1, + #[doc = "2: PDOWN with system clock off"] + Mode2 = 2, + #[doc = "8: DPDOWN with system clock off"] + Mode8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SpcLpMode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SpcLpMode { + type Ux = u8; +} +impl crate::IsEnum for SpcLpMode {} +#[doc = "Field `SPC_LP_MODE` reader - Power Domain Low-Power Mode Request"] +pub type SpcLpModeR = crate::FieldReader; +impl SpcLpModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SpcLpMode::Mode0), + 1 => Some(SpcLpMode::Mode1), + 2 => Some(SpcLpMode::Mode2), + 8 => Some(SpcLpMode::Mode8), + _ => None, + } + } + #[doc = "Sleep mode with system clock running"] + #[inline(always)] + pub fn is_mode0(&self) -> bool { + *self == SpcLpMode::Mode0 + } + #[doc = "DSLEEP with system clock off"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + *self == SpcLpMode::Mode1 + } + #[doc = "PDOWN with system clock off"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + *self == SpcLpMode::Mode2 + } + #[doc = "DPDOWN with system clock off"] + #[inline(always)] + pub fn is_mode8(&self) -> bool { + *self == SpcLpMode::Mode8 + } +} +#[doc = "Field `ISO_CLR` reader - Isolation Clear Flags"] +pub type IsoClrR = crate::BitReader; +#[doc = "Field `ISO_CLR` writer - Isolation Clear Flags"] +pub type IsoClrW<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0 - SPC Busy Status Flag"] + #[inline(always)] + pub fn busy(&self) -> BusyR { + BusyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPC Power Mode Configuration Status Flag"] + #[inline(always)] + pub fn spc_lp_req(&self) -> SpcLpReqR { + SpcLpReqR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:7 - Power Domain Low-Power Mode Request"] + #[inline(always)] + pub fn spc_lp_mode(&self) -> SpcLpModeR { + SpcLpModeR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 16 - Isolation Clear Flags"] + #[inline(always)] + pub fn iso_clr(&self) -> IsoClrR { + IsoClrR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - SPC Power Mode Configuration Status Flag"] + #[inline(always)] + pub fn spc_lp_req(&mut self) -> SpcLpReqW { + SpcLpReqW::new(self, 1) + } + #[doc = "Bit 16 - Isolation Clear Flags"] + #[inline(always)] + pub fn iso_clr(&mut self) -> IsoClrW { + IsoClrW::new(self, 16) + } +} +#[doc = "Status Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScSpec; +impl crate::RegisterSpec for ScSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sc::R`](R) reader structure"] +impl crate::Readable for ScSpec {} +#[doc = "`write(|w| ..)` method takes [`sc::W`](W) writer structure"] +impl crate::Writable for ScSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0001_0002; +} +#[doc = "`reset()` method sets SC to value 0"] +impl crate::Resettable for ScSpec {} diff --git a/mcxa276-pac/src/spc0/sramctl.rs b/mcxa276-pac/src/spc0/sramctl.rs new file mode 100644 index 000000000..82494e93b --- /dev/null +++ b/mcxa276-pac/src/spc0/sramctl.rs @@ -0,0 +1,197 @@ +#[doc = "Register `SRAMCTL` reader"] +pub type R = crate::R; +#[doc = "Register `SRAMCTL` writer"] +pub type W = crate::W; +#[doc = "Voltage Select Margin\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Vsm { + #[doc = "1: 1.0 V"] + Vsm1 = 1, + #[doc = "2: 1.1 V"] + Vsm2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Vsm) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Vsm { + type Ux = u8; +} +impl crate::IsEnum for Vsm {} +#[doc = "Field `VSM` reader - Voltage Select Margin"] +pub type VsmR = crate::FieldReader; +impl VsmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Vsm::Vsm1), + 2 => Some(Vsm::Vsm2), + _ => None, + } + } + #[doc = "1.0 V"] + #[inline(always)] + pub fn is_vsm1(&self) -> bool { + *self == Vsm::Vsm1 + } + #[doc = "1.1 V"] + #[inline(always)] + pub fn is_vsm2(&self) -> bool { + *self == Vsm::Vsm2 + } +} +#[doc = "Field `VSM` writer - Voltage Select Margin"] +pub type VsmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Vsm>; +impl<'a, REG> VsmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1.0 V"] + #[inline(always)] + pub fn vsm1(self) -> &'a mut crate::W { + self.variant(Vsm::Vsm1) + } + #[doc = "1.1 V"] + #[inline(always)] + pub fn vsm2(self) -> &'a mut crate::W { + self.variant(Vsm::Vsm2) + } +} +#[doc = "SRAM Voltage Update Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Req { + #[doc = "0: Do not request"] + ReqNo = 0, + #[doc = "1: Request"] + ReqYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Req) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REQ` reader - SRAM Voltage Update Request"] +pub type ReqR = crate::BitReader; +impl ReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Req { + match self.bits { + false => Req::ReqNo, + true => Req::ReqYes, + } + } + #[doc = "Do not request"] + #[inline(always)] + pub fn is_req_no(&self) -> bool { + *self == Req::ReqNo + } + #[doc = "Request"] + #[inline(always)] + pub fn is_req_yes(&self) -> bool { + *self == Req::ReqYes + } +} +#[doc = "Field `REQ` writer - SRAM Voltage Update Request"] +pub type ReqW<'a, REG> = crate::BitWriter<'a, REG, Req>; +impl<'a, REG> ReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Do not request"] + #[inline(always)] + pub fn req_no(self) -> &'a mut crate::W { + self.variant(Req::ReqNo) + } + #[doc = "Request"] + #[inline(always)] + pub fn req_yes(self) -> &'a mut crate::W { + self.variant(Req::ReqYes) + } +} +#[doc = "SRAM Voltage Update Request Acknowledge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ack { + #[doc = "0: Not acknowledged"] + AckNo = 0, + #[doc = "1: Acknowledged"] + AckYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ack) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACK` reader - SRAM Voltage Update Request Acknowledge"] +pub type AckR = crate::BitReader; +impl AckR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ack { + match self.bits { + false => Ack::AckNo, + true => Ack::AckYes, + } + } + #[doc = "Not acknowledged"] + #[inline(always)] + pub fn is_ack_no(&self) -> bool { + *self == Ack::AckNo + } + #[doc = "Acknowledged"] + #[inline(always)] + pub fn is_ack_yes(&self) -> bool { + *self == Ack::AckYes + } +} +impl R { + #[doc = "Bits 0:1 - Voltage Select Margin"] + #[inline(always)] + pub fn vsm(&self) -> VsmR { + VsmR::new((self.bits & 3) as u8) + } + #[doc = "Bit 30 - SRAM Voltage Update Request"] + #[inline(always)] + pub fn req(&self) -> ReqR { + ReqR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - SRAM Voltage Update Request Acknowledge"] + #[inline(always)] + pub fn ack(&self) -> AckR { + AckR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Voltage Select Margin"] + #[inline(always)] + pub fn vsm(&mut self) -> VsmW { + VsmW::new(self, 0) + } + #[doc = "Bit 30 - SRAM Voltage Update Request"] + #[inline(always)] + pub fn req(&mut self) -> ReqW { + ReqW::new(self, 30) + } +} +#[doc = "SRAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SramctlSpec; +impl crate::RegisterSpec for SramctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sramctl::R`](R) reader structure"] +impl crate::Readable for SramctlSpec {} +#[doc = "`write(|w| ..)` method takes [`sramctl::W`](W) writer structure"] +impl crate::Writable for SramctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SRAMCTL to value 0x01"] +impl crate::Resettable for SramctlSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/spc0/sramretldo_cntrl.rs b/mcxa276-pac/src/spc0/sramretldo_cntrl.rs new file mode 100644 index 000000000..cd1382582 --- /dev/null +++ b/mcxa276-pac/src/spc0/sramretldo_cntrl.rs @@ -0,0 +1,100 @@ +#[doc = "Register `SRAMRETLDO_CNTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SRAMRETLDO_CNTRL` writer"] +pub type W = crate::W; +#[doc = "SRAM LDO Regulator Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SramldoOn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SramldoOn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRAMLDO_ON` reader - SRAM LDO Regulator Enable"] +pub type SramldoOnR = crate::BitReader; +impl SramldoOnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SramldoOn { + match self.bits { + false => SramldoOn::Disable, + true => SramldoOn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SramldoOn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SramldoOn::Enable + } +} +#[doc = "Field `SRAMLDO_ON` writer - SRAM LDO Regulator Enable"] +pub type SramldoOnW<'a, REG> = crate::BitWriter<'a, REG, SramldoOn>; +impl<'a, REG> SramldoOnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SramldoOn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SramldoOn::Enable) + } +} +#[doc = "Field `SRAM_RET_EN` reader - SRAM Retention"] +pub type SramRetEnR = crate::FieldReader; +#[doc = "Field `SRAM_RET_EN` writer - SRAM Retention"] +pub type SramRetEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - SRAM LDO Regulator Enable"] + #[inline(always)] + pub fn sramldo_on(&self) -> SramldoOnR { + SramldoOnR::new((self.bits & 1) != 0) + } + #[doc = "Bits 8:11 - SRAM Retention"] + #[inline(always)] + pub fn sram_ret_en(&self) -> SramRetEnR { + SramRetEnR::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - SRAM LDO Regulator Enable"] + #[inline(always)] + pub fn sramldo_on(&mut self) -> SramldoOnW { + SramldoOnW::new(self, 0) + } + #[doc = "Bits 8:11 - SRAM Retention"] + #[inline(always)] + pub fn sram_ret_en(&mut self) -> SramRetEnW { + SramRetEnW::new(self, 8) + } +} +#[doc = "SRAM Retention LDO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_cntrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_cntrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SramretldoCntrlSpec; +impl crate::RegisterSpec for SramretldoCntrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sramretldo_cntrl::R`](R) reader structure"] +impl crate::Readable for SramretldoCntrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sramretldo_cntrl::W`](W) writer structure"] +impl crate::Writable for SramretldoCntrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SRAMRETLDO_CNTRL to value 0x0f01"] +impl crate::Resettable for SramretldoCntrlSpec { + const RESET_VALUE: u32 = 0x0f01; +} diff --git a/mcxa276-pac/src/spc0/sramretldo_reftrim.rs b/mcxa276-pac/src/spc0/sramretldo_reftrim.rs new file mode 100644 index 000000000..97377fbd6 --- /dev/null +++ b/mcxa276-pac/src/spc0/sramretldo_reftrim.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SRAMRETLDO_REFTRIM` reader"] +pub type R = crate::R; +#[doc = "Register `SRAMRETLDO_REFTRIM` writer"] +pub type W = crate::W; +#[doc = "Field `REFTRIM` reader - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] +pub type ReftrimR = crate::FieldReader; +#[doc = "Field `REFTRIM` writer - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] +pub type ReftrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] + #[inline(always)] + pub fn reftrim(&self) -> ReftrimR { + ReftrimR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] + #[inline(always)] + pub fn reftrim(&mut self) -> ReftrimW { + ReftrimW::new(self, 0) + } +} +#[doc = "SRAM Retention Reference Trim\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_reftrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_reftrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SramretldoReftrimSpec; +impl crate::RegisterSpec for SramretldoReftrimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sramretldo_reftrim::R`](R) reader structure"] +impl crate::Readable for SramretldoReftrimSpec {} +#[doc = "`write(|w| ..)` method takes [`sramretldo_reftrim::W`](W) writer structure"] +impl crate::Writable for SramretldoReftrimSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SRAMRETLDO_REFTRIM to value 0x17"] +impl crate::Resettable for SramretldoReftrimSpec { + const RESET_VALUE: u32 = 0x17; +} diff --git a/mcxa276-pac/src/spc0/vd_core_cfg.rs b/mcxa276-pac/src/spc0/vd_core_cfg.rs new file mode 100644 index 000000000..d2242deec --- /dev/null +++ b/mcxa276-pac/src/spc0/vd_core_cfg.rs @@ -0,0 +1,212 @@ +#[doc = "Register `VD_CORE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `VD_CORE_CFG` writer"] +pub type W = crate::W; +#[doc = "Core LVD Reset Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lvdre { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lvdre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LVDRE` reader - Core LVD Reset Enable"] +pub type LvdreR = crate::BitReader; +impl LvdreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lvdre { + match self.bits { + false => Lvdre::Disable, + true => Lvdre::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lvdre::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lvdre::Enable + } +} +#[doc = "Field `LVDRE` writer - Core LVD Reset Enable"] +pub type LvdreW<'a, REG> = crate::BitWriter<'a, REG, Lvdre>; +impl<'a, REG> LvdreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lvdre::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lvdre::Enable) + } +} +#[doc = "Core LVD Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lvdie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lvdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LVDIE` reader - Core LVD Interrupt Enable"] +pub type LvdieR = crate::BitReader; +impl LvdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lvdie { + match self.bits { + false => Lvdie::Disable, + true => Lvdie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lvdie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lvdie::Enable + } +} +#[doc = "Field `LVDIE` writer - Core LVD Interrupt Enable"] +pub type LvdieW<'a, REG> = crate::BitWriter<'a, REG, Lvdie>; +impl<'a, REG> LvdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lvdie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lvdie::Enable) + } +} +#[doc = "Core Voltage Detect Reset Enable Lock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: Allow"] + Allow = 0, + #[doc = "1: Deny"] + Deny = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - Core Voltage Detect Reset Enable Lock"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Allow, + true => Lock::Deny, + } + } + #[doc = "Allow"] + #[inline(always)] + pub fn is_allow(&self) -> bool { + *self == Lock::Allow + } + #[doc = "Deny"] + #[inline(always)] + pub fn is_deny(&self) -> bool { + *self == Lock::Deny + } +} +#[doc = "Field `LOCK` writer - Core Voltage Detect Reset Enable Lock"] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Allow"] + #[inline(always)] + pub fn allow(self) -> &'a mut crate::W { + self.variant(Lock::Allow) + } + #[doc = "Deny"] + #[inline(always)] + pub fn deny(self) -> &'a mut crate::W { + self.variant(Lock::Deny) + } +} +impl R { + #[doc = "Bit 0 - Core LVD Reset Enable"] + #[inline(always)] + pub fn lvdre(&self) -> LvdreR { + LvdreR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Core LVD Interrupt Enable"] + #[inline(always)] + pub fn lvdie(&self) -> LvdieR { + LvdieR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - Core Voltage Detect Reset Enable Lock"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Core LVD Reset Enable"] + #[inline(always)] + pub fn lvdre(&mut self) -> LvdreW { + LvdreW::new(self, 0) + } + #[doc = "Bit 1 - Core LVD Interrupt Enable"] + #[inline(always)] + pub fn lvdie(&mut self) -> LvdieW { + LvdieW::new(self, 1) + } + #[doc = "Bit 16 - Core Voltage Detect Reset Enable Lock"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 16) + } +} +#[doc = "Core Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_core_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_core_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VdCoreCfgSpec; +impl crate::RegisterSpec for VdCoreCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vd_core_cfg::R`](R) reader structure"] +impl crate::Readable for VdCoreCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`vd_core_cfg::W`](W) writer structure"] +impl crate::Writable for VdCoreCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets VD_CORE_CFG to value 0x01"] +impl crate::Resettable for VdCoreCfgSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/spc0/vd_stat.rs b/mcxa276-pac/src/spc0/vd_stat.rs new file mode 100644 index 000000000..ced74dd59 --- /dev/null +++ b/mcxa276-pac/src/spc0/vd_stat.rs @@ -0,0 +1,211 @@ +#[doc = "Register `VD_STAT` reader"] +pub type R = crate::R; +#[doc = "Register `VD_STAT` writer"] +pub type W = crate::W; +#[doc = "Core Low-Voltage Detect Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CorevddLvdf { + #[doc = "0: Event not detected"] + EventNo = 0, + #[doc = "1: Event detected"] + EventYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CorevddLvdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `COREVDD_LVDF` reader - Core Low-Voltage Detect Flag"] +pub type CorevddLvdfR = crate::BitReader; +impl CorevddLvdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CorevddLvdf { + match self.bits { + false => CorevddLvdf::EventNo, + true => CorevddLvdf::EventYes, + } + } + #[doc = "Event not detected"] + #[inline(always)] + pub fn is_event_no(&self) -> bool { + *self == CorevddLvdf::EventNo + } + #[doc = "Event detected"] + #[inline(always)] + pub fn is_event_yes(&self) -> bool { + *self == CorevddLvdf::EventYes + } +} +#[doc = "Field `COREVDD_LVDF` writer - Core Low-Voltage Detect Flag"] +pub type CorevddLvdfW<'a, REG> = crate::BitWriter1C<'a, REG, CorevddLvdf>; +impl<'a, REG> CorevddLvdfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Event not detected"] + #[inline(always)] + pub fn event_no(self) -> &'a mut crate::W { + self.variant(CorevddLvdf::EventNo) + } + #[doc = "Event detected"] + #[inline(always)] + pub fn event_yes(self) -> &'a mut crate::W { + self.variant(CorevddLvdf::EventYes) + } +} +#[doc = "System Low-Voltage Detect Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysvddLvdf { + #[doc = "0: Event not detected"] + EventNo = 0, + #[doc = "1: Event detected"] + EventYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysvddLvdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSVDD_LVDF` reader - System Low-Voltage Detect Flag"] +pub type SysvddLvdfR = crate::BitReader; +impl SysvddLvdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysvddLvdf { + match self.bits { + false => SysvddLvdf::EventNo, + true => SysvddLvdf::EventYes, + } + } + #[doc = "Event not detected"] + #[inline(always)] + pub fn is_event_no(&self) -> bool { + *self == SysvddLvdf::EventNo + } + #[doc = "Event detected"] + #[inline(always)] + pub fn is_event_yes(&self) -> bool { + *self == SysvddLvdf::EventYes + } +} +#[doc = "Field `SYSVDD_LVDF` writer - System Low-Voltage Detect Flag"] +pub type SysvddLvdfW<'a, REG> = crate::BitWriter1C<'a, REG, SysvddLvdf>; +impl<'a, REG> SysvddLvdfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Event not detected"] + #[inline(always)] + pub fn event_no(self) -> &'a mut crate::W { + self.variant(SysvddLvdf::EventNo) + } + #[doc = "Event detected"] + #[inline(always)] + pub fn event_yes(self) -> &'a mut crate::W { + self.variant(SysvddLvdf::EventYes) + } +} +#[doc = "System HVD Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysvddHvdf { + #[doc = "0: Event not detected"] + EventNo = 0, + #[doc = "1: Event detected"] + EventYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysvddHvdf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSVDD_HVDF` reader - System HVD Flag"] +pub type SysvddHvdfR = crate::BitReader; +impl SysvddHvdfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysvddHvdf { + match self.bits { + false => SysvddHvdf::EventNo, + true => SysvddHvdf::EventYes, + } + } + #[doc = "Event not detected"] + #[inline(always)] + pub fn is_event_no(&self) -> bool { + *self == SysvddHvdf::EventNo + } + #[doc = "Event detected"] + #[inline(always)] + pub fn is_event_yes(&self) -> bool { + *self == SysvddHvdf::EventYes + } +} +#[doc = "Field `SYSVDD_HVDF` writer - System HVD Flag"] +pub type SysvddHvdfW<'a, REG> = crate::BitWriter1C<'a, REG, SysvddHvdf>; +impl<'a, REG> SysvddHvdfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Event not detected"] + #[inline(always)] + pub fn event_no(self) -> &'a mut crate::W { + self.variant(SysvddHvdf::EventNo) + } + #[doc = "Event detected"] + #[inline(always)] + pub fn event_yes(self) -> &'a mut crate::W { + self.variant(SysvddHvdf::EventYes) + } +} +impl R { + #[doc = "Bit 0 - Core Low-Voltage Detect Flag"] + #[inline(always)] + pub fn corevdd_lvdf(&self) -> CorevddLvdfR { + CorevddLvdfR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - System Low-Voltage Detect Flag"] + #[inline(always)] + pub fn sysvdd_lvdf(&self) -> SysvddLvdfR { + SysvddLvdfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 5 - System HVD Flag"] + #[inline(always)] + pub fn sysvdd_hvdf(&self) -> SysvddHvdfR { + SysvddHvdfR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Core Low-Voltage Detect Flag"] + #[inline(always)] + pub fn corevdd_lvdf(&mut self) -> CorevddLvdfW { + CorevddLvdfW::new(self, 0) + } + #[doc = "Bit 1 - System Low-Voltage Detect Flag"] + #[inline(always)] + pub fn sysvdd_lvdf(&mut self) -> SysvddLvdfW { + SysvddLvdfW::new(self, 1) + } + #[doc = "Bit 5 - System HVD Flag"] + #[inline(always)] + pub fn sysvdd_hvdf(&mut self) -> SysvddHvdfW { + SysvddHvdfW::new(self, 5) + } +} +#[doc = "Voltage Detect Status\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VdStatSpec; +impl crate::RegisterSpec for VdStatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vd_stat::R`](R) reader structure"] +impl crate::Readable for VdStatSpec {} +#[doc = "`write(|w| ..)` method takes [`vd_stat::W`](W) writer structure"] +impl crate::Writable for VdStatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x23; +} +#[doc = "`reset()` method sets VD_STAT to value 0"] +impl crate::Resettable for VdStatSpec {} diff --git a/mcxa276-pac/src/spc0/vd_sys_cfg.rs b/mcxa276-pac/src/spc0/vd_sys_cfg.rs new file mode 100644 index 000000000..ff1d9a5ff --- /dev/null +++ b/mcxa276-pac/src/spc0/vd_sys_cfg.rs @@ -0,0 +1,338 @@ +#[doc = "Register `VD_SYS_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `VD_SYS_CFG` writer"] +pub type W = crate::W; +#[doc = "System LVD Reset Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lvdre { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lvdre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LVDRE` reader - System LVD Reset Enable"] +pub type LvdreR = crate::BitReader; +impl LvdreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lvdre { + match self.bits { + false => Lvdre::Disable, + true => Lvdre::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lvdre::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lvdre::Enable + } +} +#[doc = "Field `LVDRE` writer - System LVD Reset Enable"] +pub type LvdreW<'a, REG> = crate::BitWriter<'a, REG, Lvdre>; +impl<'a, REG> LvdreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lvdre::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lvdre::Enable) + } +} +#[doc = "System LVD Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lvdie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lvdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LVDIE` reader - System LVD Interrupt Enable"] +pub type LvdieR = crate::BitReader; +impl LvdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lvdie { + match self.bits { + false => Lvdie::Disable, + true => Lvdie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lvdie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lvdie::Enable + } +} +#[doc = "Field `LVDIE` writer - System LVD Interrupt Enable"] +pub type LvdieW<'a, REG> = crate::BitWriter<'a, REG, Lvdie>; +impl<'a, REG> LvdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lvdie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lvdie::Enable) + } +} +#[doc = "System HVD Reset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hvdre { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hvdre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HVDRE` reader - System HVD Reset Enable"] +pub type HvdreR = crate::BitReader; +impl HvdreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hvdre { + match self.bits { + false => Hvdre::Disable, + true => Hvdre::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Hvdre::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Hvdre::Enable + } +} +#[doc = "Field `HVDRE` writer - System HVD Reset Enable"] +pub type HvdreW<'a, REG> = crate::BitWriter<'a, REG, Hvdre>; +impl<'a, REG> HvdreW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Hvdre::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Hvdre::Enable) + } +} +#[doc = "System HVD Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hvdie { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hvdie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HVDIE` reader - System HVD Interrupt Enable"] +pub type HvdieR = crate::BitReader; +impl HvdieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hvdie { + match self.bits { + false => Hvdie::Disable, + true => Hvdie::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Hvdie::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Hvdie::Enable + } +} +#[doc = "Field `HVDIE` writer - System HVD Interrupt Enable"] +pub type HvdieW<'a, REG> = crate::BitWriter<'a, REG, Hvdie>; +impl<'a, REG> HvdieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Hvdie::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Hvdie::Enable) + } +} +#[doc = "System Voltage Detect Reset Enable Lock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: Allow"] + Allow = 0, + #[doc = "1: Deny"] + Deny = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - System Voltage Detect Reset Enable Lock"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Allow, + true => Lock::Deny, + } + } + #[doc = "Allow"] + #[inline(always)] + pub fn is_allow(&self) -> bool { + *self == Lock::Allow + } + #[doc = "Deny"] + #[inline(always)] + pub fn is_deny(&self) -> bool { + *self == Lock::Deny + } +} +#[doc = "Field `LOCK` writer - System Voltage Detect Reset Enable Lock"] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Allow"] + #[inline(always)] + pub fn allow(self) -> &'a mut crate::W { + self.variant(Lock::Allow) + } + #[doc = "Deny"] + #[inline(always)] + pub fn deny(self) -> &'a mut crate::W { + self.variant(Lock::Deny) + } +} +impl R { + #[doc = "Bit 0 - System LVD Reset Enable"] + #[inline(always)] + pub fn lvdre(&self) -> LvdreR { + LvdreR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - System LVD Interrupt Enable"] + #[inline(always)] + pub fn lvdie(&self) -> LvdieR { + LvdieR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - System HVD Reset Enable"] + #[inline(always)] + pub fn hvdre(&self) -> HvdreR { + HvdreR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - System HVD Interrupt Enable"] + #[inline(always)] + pub fn hvdie(&self) -> HvdieR { + HvdieR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 16 - System Voltage Detect Reset Enable Lock"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - System LVD Reset Enable"] + #[inline(always)] + pub fn lvdre(&mut self) -> LvdreW { + LvdreW::new(self, 0) + } + #[doc = "Bit 1 - System LVD Interrupt Enable"] + #[inline(always)] + pub fn lvdie(&mut self) -> LvdieW { + LvdieW::new(self, 1) + } + #[doc = "Bit 2 - System HVD Reset Enable"] + #[inline(always)] + pub fn hvdre(&mut self) -> HvdreW { + HvdreW::new(self, 2) + } + #[doc = "Bit 3 - System HVD Interrupt Enable"] + #[inline(always)] + pub fn hvdie(&mut self) -> HvdieW { + HvdieW::new(self, 3) + } + #[doc = "Bit 16 - System Voltage Detect Reset Enable Lock"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 16) + } +} +#[doc = "System Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_sys_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_sys_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VdSysCfgSpec; +impl crate::RegisterSpec for VdSysCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vd_sys_cfg::R`](R) reader structure"] +impl crate::Readable for VdSysCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`vd_sys_cfg::W`](W) writer structure"] +impl crate::Writable for VdSysCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets VD_SYS_CFG to value 0x01"] +impl crate::Resettable for VdSysCfgSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/spc0/verid.rs b/mcxa276-pac/src/spc0/verid.rs new file mode 100644 index 000000000..931447f66 --- /dev/null +++ b/mcxa276-pac/src/spc0/verid.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Standard features"] + Standard = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Standard), + _ => None, + } + } + #[doc = "Standard features"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == Feature::Standard + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0"] +impl crate::Resettable for VeridSpec {} diff --git a/mcxa276-pac/src/syscon.rs b/mcxa276-pac/src/syscon.rs new file mode 100644 index 000000000..259c5fce1 --- /dev/null +++ b/mcxa276-pac/src/syscon.rs @@ -0,0 +1,497 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x0200], + remap: Remap, + _reserved1: [u8; 0x0c], + ahbmatprio: Ahbmatprio, + _reserved2: [u8; 0x28], + cpu0nstckcal: Cpu0nstckcal, + _reserved3: [u8; 0x08], + nmisrc: Nmisrc, + protlvl: Protlvl, + _reserved5: [u8; 0x0128], + slowclkdiv: Slowclkdiv, + busclkdiv: Busclkdiv, + ahbclkdiv: Ahbclkdiv, + _reserved8: [u8; 0x04], + frohfdiv: Frohfdiv, + frolfdiv: Frolfdiv, + _reserved10: [u8; 0x54], + pll1clkdiv: Pll1clkdiv, + _reserved11: [u8; 0x14], + clkunlock: Clkunlock, + nvm_ctrl: NvmCtrl, + _reserved13: [u8; 0x10], + smart_dmaint: SmartDmaint, + _reserved14: [u8; 0x58], + ram_interleave: RamInterleave, + _reserved15: [u8; 0x0398], + cpustat: Cpustat, + _reserved16: [u8; 0x14], + lpcac_ctrl: LpcacCtrl, + _reserved17: [u8; 0x0110], + pwm0subctl: Pwm0subctl, + pwm1subctl: Pwm1subctl, + ctimerglobalstarten: Ctimerglobalstarten, + ram_ctrl: RamCtrl, + _reserved21: [u8; 0x0218], + gray_code_lsb: GrayCodeLsb, + gray_code_msb: GrayCodeMsb, + binary_code_lsb: BinaryCodeLsb, + binary_code_msb: BinaryCodeMsb, + _reserved25: [u8; 0x02a0], + els_udf: ElsUdf, + _reserved26: [u8; 0x08], + msfcfg: Msfcfg, + els_uid: [ElsUid; 4], + _reserved28: [u8; 0x0c], + rop_state: RopState, + _reserved29: [u8; 0x18], + sram_xen: SramXen, + sram_xen_dp: SramXenDp, + _reserved31: [u8; 0x20], + els_otp_lc_state: ElsOtpLcState, + els_otp_lc_state_dp: ElsOtpLcStateDp, + _reserved33: [u8; 0x0118], + debug_lock_en: DebugLockEn, + debug_features: DebugFeatures, + debug_features_dp: DebugFeaturesDp, + _reserved36: [u8; 0x08], + swd_access_cpu0: SwdAccessCpu0, + _reserved37: [u8; 0x08], + debug_auth_beacon: DebugAuthBeacon, + _reserved38: [u8; 0x2c], + jtag_id: JtagId, + device_type: DeviceType, + device_id0: DeviceId0, + dieid: Dieid, +} +impl RegisterBlock { + #[doc = "0x200 - AHB Matrix Remap Control"] + #[inline(always)] + pub const fn remap(&self) -> &Remap { + &self.remap + } + #[doc = "0x210 - AHB Matrix Priority Control"] + #[inline(always)] + pub const fn ahbmatprio(&self) -> &Ahbmatprio { + &self.ahbmatprio + } + #[doc = "0x23c - Non-Secure CPU0 System Tick Calibration"] + #[inline(always)] + pub const fn cpu0nstckcal(&self) -> &Cpu0nstckcal { + &self.cpu0nstckcal + } + #[doc = "0x248 - NMI Source Select"] + #[inline(always)] + pub const fn nmisrc(&self) -> &Nmisrc { + &self.nmisrc + } + #[doc = "0x24c - Protect Level Control"] + #[inline(always)] + pub const fn protlvl(&self) -> &Protlvl { + &self.protlvl + } + #[doc = "0x378 - SLOW_CLK Clock Divider"] + #[inline(always)] + pub const fn slowclkdiv(&self) -> &Slowclkdiv { + &self.slowclkdiv + } + #[doc = "0x37c - BUS_CLK Clock Divider"] + #[inline(always)] + pub const fn busclkdiv(&self) -> &Busclkdiv { + &self.busclkdiv + } + #[doc = "0x380 - System Clock Divider"] + #[inline(always)] + pub const fn ahbclkdiv(&self) -> &Ahbclkdiv { + &self.ahbclkdiv + } + #[doc = "0x388 - FRO_HF_DIV Clock Divider"] + #[inline(always)] + pub const fn frohfdiv(&self) -> &Frohfdiv { + &self.frohfdiv + } + #[doc = "0x38c - FRO_LF_DIV Clock Divider"] + #[inline(always)] + pub const fn frolfdiv(&self) -> &Frolfdiv { + &self.frolfdiv + } + #[doc = "0x3e4 - PLL1_CLK_DIV Clock Divider"] + #[inline(always)] + pub const fn pll1clkdiv(&self) -> &Pll1clkdiv { + &self.pll1clkdiv + } + #[doc = "0x3fc - Clock Configuration Unlock"] + #[inline(always)] + pub const fn clkunlock(&self) -> &Clkunlock { + &self.clkunlock + } + #[doc = "0x400 - NVM Control"] + #[inline(always)] + pub const fn nvm_ctrl(&self) -> &NvmCtrl { + &self.nvm_ctrl + } + #[doc = "0x414 - SmartDMA Interrupt Hijack"] + #[inline(always)] + pub const fn smart_dmaint(&self) -> &SmartDmaint { + &self.smart_dmaint + } + #[doc = "0x470 - Controls RAM Interleave Integration"] + #[inline(always)] + pub const fn ram_interleave(&self) -> &RamInterleave { + &self.ram_interleave + } + #[doc = "0x80c - CPU Status"] + #[inline(always)] + pub const fn cpustat(&self) -> &Cpustat { + &self.cpustat + } + #[doc = "0x824 - LPCAC Control"] + #[inline(always)] + pub const fn lpcac_ctrl(&self) -> &LpcacCtrl { + &self.lpcac_ctrl + } + #[doc = "0x938 - PWM0 Submodule Control"] + #[inline(always)] + pub const fn pwm0subctl(&self) -> &Pwm0subctl { + &self.pwm0subctl + } + #[doc = "0x93c - PWM1 Submodule Control"] + #[inline(always)] + pub const fn pwm1subctl(&self) -> &Pwm1subctl { + &self.pwm1subctl + } + #[doc = "0x940 - CTIMER Global Start Enable"] + #[inline(always)] + pub const fn ctimerglobalstarten(&self) -> &Ctimerglobalstarten { + &self.ctimerglobalstarten + } + #[doc = "0x944 - RAM Control"] + #[inline(always)] + pub const fn ram_ctrl(&self) -> &RamCtrl { + &self.ram_ctrl + } + #[doc = "0xb60 - Gray to Binary Converter Gray Code \\[31:0\\]"] + #[inline(always)] + pub const fn gray_code_lsb(&self) -> &GrayCodeLsb { + &self.gray_code_lsb + } + #[doc = "0xb64 - Gray to Binary Converter Gray Code \\[41:32\\]"] + #[inline(always)] + pub const fn gray_code_msb(&self) -> &GrayCodeMsb { + &self.gray_code_msb + } + #[doc = "0xb68 - Gray to Binary Converter Binary Code \\[31:0\\]"] + #[inline(always)] + pub const fn binary_code_lsb(&self) -> &BinaryCodeLsb { + &self.binary_code_lsb + } + #[doc = "0xb6c - Gray to Binary Converter Binary Code \\[41:32\\]"] + #[inline(always)] + pub const fn binary_code_msb(&self) -> &BinaryCodeMsb { + &self.binary_code_msb + } + #[doc = "0xe10 - UDF Control"] + #[inline(always)] + pub const fn els_udf(&self) -> &ElsUdf { + &self.els_udf + } + #[doc = "0xe1c - MSF Configuration"] + #[inline(always)] + pub const fn msfcfg(&self) -> &Msfcfg { + &self.msfcfg + } + #[doc = "0xe20..0xe30 - Device UID n"] + #[inline(always)] + pub const fn els_uid(&self, n: usize) -> &ElsUid { + &self.els_uid[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xe20..0xe30 - Device UID n"] + #[inline(always)] + pub fn els_uid_iter(&self) -> impl Iterator { + self.els_uid.iter() + } + #[doc = "0xe3c - ROP State Register"] + #[inline(always)] + pub const fn rop_state(&self) -> &RopState { + &self.rop_state + } + #[doc = "0xe58 - RAM XEN Control"] + #[inline(always)] + pub const fn sram_xen(&self) -> &SramXen { + &self.sram_xen + } + #[doc = "0xe5c - RAM XEN Control (Duplicate)"] + #[inline(always)] + pub const fn sram_xen_dp(&self) -> &SramXenDp { + &self.sram_xen_dp + } + #[doc = "0xe80 - Life Cycle State Register"] + #[inline(always)] + pub const fn els_otp_lc_state(&self) -> &ElsOtpLcState { + &self.els_otp_lc_state + } + #[doc = "0xe84 - Life Cycle State Register (Duplicate)"] + #[inline(always)] + pub const fn els_otp_lc_state_dp(&self) -> &ElsOtpLcStateDp { + &self.els_otp_lc_state_dp + } + #[doc = "0xfa0 - Control Write Access to Security"] + #[inline(always)] + pub const fn debug_lock_en(&self) -> &DebugLockEn { + &self.debug_lock_en + } + #[doc = "0xfa4 - Cortex Debug Features Control"] + #[inline(always)] + pub const fn debug_features(&self) -> &DebugFeatures { + &self.debug_features + } + #[doc = "0xfa8 - Cortex Debug Features Control (Duplicate)"] + #[inline(always)] + pub const fn debug_features_dp(&self) -> &DebugFeaturesDp { + &self.debug_features_dp + } + #[doc = "0xfb4 - CPU0 Software Debug Access"] + #[inline(always)] + pub const fn swd_access_cpu0(&self) -> &SwdAccessCpu0 { + &self.swd_access_cpu0 + } + #[doc = "0xfc0 - Debug Authentication BEACON"] + #[inline(always)] + pub const fn debug_auth_beacon(&self) -> &DebugAuthBeacon { + &self.debug_auth_beacon + } + #[doc = "0xff0 - JTAG Chip ID"] + #[inline(always)] + pub const fn jtag_id(&self) -> &JtagId { + &self.jtag_id + } + #[doc = "0xff4 - Device Type"] + #[inline(always)] + pub const fn device_type(&self) -> &DeviceType { + &self.device_type + } + #[doc = "0xff8 - Device ID"] + #[inline(always)] + pub const fn device_id0(&self) -> &DeviceId0 { + &self.device_id0 + } + #[doc = "0xffc - Chip Revision ID and Number"] + #[inline(always)] + pub const fn dieid(&self) -> &Dieid { + &self.dieid + } +} +#[doc = "REMAP (rw) register accessor: AHB Matrix Remap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap`] module"] +#[doc(alias = "REMAP")] +pub type Remap = crate::Reg; +#[doc = "AHB Matrix Remap Control"] +pub mod remap; +#[doc = "AHBMATPRIO (rw) register accessor: AHB Matrix Priority Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbmatprio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbmatprio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbmatprio`] module"] +#[doc(alias = "AHBMATPRIO")] +pub type Ahbmatprio = crate::Reg; +#[doc = "AHB Matrix Priority Control"] +pub mod ahbmatprio; +#[doc = "CPU0NSTCKCAL (rw) register accessor: Non-Secure CPU0 System Tick Calibration\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu0nstckcal::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu0nstckcal::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu0nstckcal`] module"] +#[doc(alias = "CPU0NSTCKCAL")] +pub type Cpu0nstckcal = crate::Reg; +#[doc = "Non-Secure CPU0 System Tick Calibration"] +pub mod cpu0nstckcal; +#[doc = "NMISRC (rw) register accessor: NMI Source Select\n\nYou can [`read`](crate::Reg::read) this register and get [`nmisrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmisrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmisrc`] module"] +#[doc(alias = "NMISRC")] +pub type Nmisrc = crate::Reg; +#[doc = "NMI Source Select"] +pub mod nmisrc; +#[doc = "PROTLVL (rw) register accessor: Protect Level Control\n\nYou can [`read`](crate::Reg::read) this register and get [`protlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`protlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@protlvl`] module"] +#[doc(alias = "PROTLVL")] +pub type Protlvl = crate::Reg; +#[doc = "Protect Level Control"] +pub mod protlvl; +#[doc = "SLOWCLKDIV (rw) register accessor: SLOW_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`slowclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slowclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slowclkdiv`] module"] +#[doc(alias = "SLOWCLKDIV")] +pub type Slowclkdiv = crate::Reg; +#[doc = "SLOW_CLK Clock Divider"] +pub mod slowclkdiv; +#[doc = "BUSCLKDIV (rw) register accessor: BUS_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`busclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`busclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@busclkdiv`] module"] +#[doc(alias = "BUSCLKDIV")] +pub type Busclkdiv = crate::Reg; +#[doc = "BUS_CLK Clock Divider"] +pub mod busclkdiv; +#[doc = "AHBCLKDIV (rw) register accessor: System Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbclkdiv`] module"] +#[doc(alias = "AHBCLKDIV")] +pub type Ahbclkdiv = crate::Reg; +#[doc = "System Clock Divider"] +pub mod ahbclkdiv; +#[doc = "FROHFDIV (rw) register accessor: FRO_HF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frohfdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frohfdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frohfdiv`] module"] +#[doc(alias = "FROHFDIV")] +pub type Frohfdiv = crate::Reg; +#[doc = "FRO_HF_DIV Clock Divider"] +pub mod frohfdiv; +#[doc = "FROLFDIV (rw) register accessor: FRO_LF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frolfdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolfdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frolfdiv`] module"] +#[doc(alias = "FROLFDIV")] +pub type Frolfdiv = crate::Reg; +#[doc = "FRO_LF_DIV Clock Divider"] +pub mod frolfdiv; +#[doc = "PLL1CLKDIV (rw) register accessor: PLL1_CLK_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pll1clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll1clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll1clkdiv`] module"] +#[doc(alias = "PLL1CLKDIV")] +pub type Pll1clkdiv = crate::Reg; +#[doc = "PLL1_CLK_DIV Clock Divider"] +pub mod pll1clkdiv; +#[doc = "CLKUNLOCK (rw) register accessor: Clock Configuration Unlock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkunlock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkunlock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkunlock`] module"] +#[doc(alias = "CLKUNLOCK")] +pub type Clkunlock = crate::Reg; +#[doc = "Clock Configuration Unlock"] +pub mod clkunlock; +#[doc = "NVM_CTRL (rw) register accessor: NVM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`nvm_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvm_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nvm_ctrl`] module"] +#[doc(alias = "NVM_CTRL")] +pub type NvmCtrl = crate::Reg; +#[doc = "NVM Control"] +pub mod nvm_ctrl; +#[doc = "SmartDMAINT (rw) register accessor: SmartDMA Interrupt Hijack\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dmaint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dmaint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smart_dmaint`] module"] +#[doc(alias = "SmartDMAINT")] +pub type SmartDmaint = crate::Reg; +#[doc = "SmartDMA Interrupt Hijack"] +pub mod smart_dmaint; +#[doc = "RAM_INTERLEAVE (rw) register accessor: Controls RAM Interleave Integration\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_interleave::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_interleave::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_interleave`] module"] +#[doc(alias = "RAM_INTERLEAVE")] +pub type RamInterleave = crate::Reg; +#[doc = "Controls RAM Interleave Integration"] +pub mod ram_interleave; +#[doc = "CPUSTAT (r) register accessor: CPU Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cpustat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpustat`] module"] +#[doc(alias = "CPUSTAT")] +pub type Cpustat = crate::Reg; +#[doc = "CPU Status"] +pub mod cpustat; +#[doc = "LPCAC_CTRL (rw) register accessor: LPCAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`lpcac_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcac_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpcac_ctrl`] module"] +#[doc(alias = "LPCAC_CTRL")] +pub type LpcacCtrl = crate::Reg; +#[doc = "LPCAC Control"] +pub mod lpcac_ctrl; +#[doc = "PWM0SUBCTL (rw) register accessor: PWM0 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0subctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0subctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0subctl`] module"] +#[doc(alias = "PWM0SUBCTL")] +pub type Pwm0subctl = crate::Reg; +#[doc = "PWM0 Submodule Control"] +pub mod pwm0subctl; +#[doc = "PWM1SUBCTL (rw) register accessor: PWM1 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1subctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1subctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1subctl`] module"] +#[doc(alias = "PWM1SUBCTL")] +pub type Pwm1subctl = crate::Reg; +#[doc = "PWM1 Submodule Control"] +pub mod pwm1subctl; +#[doc = "CTIMERGLOBALSTARTEN (rw) register accessor: CTIMER Global Start Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimerglobalstarten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimerglobalstarten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimerglobalstarten`] module"] +#[doc(alias = "CTIMERGLOBALSTARTEN")] +pub type Ctimerglobalstarten = crate::Reg; +#[doc = "CTIMER Global Start Enable"] +pub mod ctimerglobalstarten; +#[doc = "RAM_CTRL (rw) register accessor: RAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_ctrl`] module"] +#[doc(alias = "RAM_CTRL")] +pub type RamCtrl = crate::Reg; +#[doc = "RAM Control"] +pub mod ram_ctrl; +#[doc = "GRAY_CODE_LSB (rw) register accessor: Gray to Binary Converter Gray Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gray_code_lsb`] module"] +#[doc(alias = "GRAY_CODE_LSB")] +pub type GrayCodeLsb = crate::Reg; +#[doc = "Gray to Binary Converter Gray Code \\[31:0\\]"] +pub mod gray_code_lsb; +#[doc = "GRAY_CODE_MSB (rw) register accessor: Gray to Binary Converter Gray Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gray_code_msb`] module"] +#[doc(alias = "GRAY_CODE_MSB")] +pub type GrayCodeMsb = crate::Reg; +#[doc = "Gray to Binary Converter Gray Code \\[41:32\\]"] +pub mod gray_code_msb; +#[doc = "BINARY_CODE_LSB (r) register accessor: Gray to Binary Converter Binary Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_lsb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@binary_code_lsb`] module"] +#[doc(alias = "BINARY_CODE_LSB")] +pub type BinaryCodeLsb = crate::Reg; +#[doc = "Gray to Binary Converter Binary Code \\[31:0\\]"] +pub mod binary_code_lsb; +#[doc = "BINARY_CODE_MSB (r) register accessor: Gray to Binary Converter Binary Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_msb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@binary_code_msb`] module"] +#[doc(alias = "BINARY_CODE_MSB")] +pub type BinaryCodeMsb = crate::Reg; +#[doc = "Gray to Binary Converter Binary Code \\[41:32\\]"] +pub mod binary_code_msb; +#[doc = "ELS_UDF (rw) register accessor: UDF Control\n\nYou can [`read`](crate::Reg::read) this register and get [`els_udf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_udf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_udf`] module"] +#[doc(alias = "ELS_UDF")] +pub type ElsUdf = crate::Reg; +#[doc = "UDF Control"] +pub mod els_udf; +#[doc = "MSFCFG (rw) register accessor: MSF Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`msfcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msfcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msfcfg`] module"] +#[doc(alias = "MSFCFG")] +pub type Msfcfg = crate::Reg; +#[doc = "MSF Configuration"] +pub mod msfcfg; +#[doc = "ELS_UID (rw) register accessor: Device UID n\n\nYou can [`read`](crate::Reg::read) this register and get [`els_uid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_uid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_uid`] module"] +#[doc(alias = "ELS_UID")] +pub type ElsUid = crate::Reg; +#[doc = "Device UID n"] +pub mod els_uid; +#[doc = "ROP_STATE (r) register accessor: ROP State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rop_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rop_state`] module"] +#[doc(alias = "ROP_STATE")] +pub type RopState = crate::Reg; +#[doc = "ROP State Register"] +pub mod rop_state; +#[doc = "SRAM_XEN (rw) register accessor: RAM XEN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_xen`] module"] +#[doc(alias = "SRAM_XEN")] +pub type SramXen = crate::Reg; +#[doc = "RAM XEN Control"] +pub mod sram_xen; +#[doc = "SRAM_XEN_DP (rw) register accessor: RAM XEN Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen_dp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen_dp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_xen_dp`] module"] +#[doc(alias = "SRAM_XEN_DP")] +pub type SramXenDp = crate::Reg; +#[doc = "RAM XEN Control (Duplicate)"] +pub mod sram_xen_dp; +#[doc = "ELS_OTP_LC_STATE (r) register accessor: Life Cycle State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_otp_lc_state`] module"] +#[doc(alias = "ELS_OTP_LC_STATE")] +pub type ElsOtpLcState = crate::Reg; +#[doc = "Life Cycle State Register"] +pub mod els_otp_lc_state; +#[doc = "ELS_OTP_LC_STATE_DP (r) register accessor: Life Cycle State Register (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state_dp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_otp_lc_state_dp`] module"] +#[doc(alias = "ELS_OTP_LC_STATE_DP")] +pub type ElsOtpLcStateDp = crate::Reg; +#[doc = "Life Cycle State Register (Duplicate)"] +pub mod els_otp_lc_state_dp; +#[doc = "DEBUG_LOCK_EN (rw) register accessor: Control Write Access to Security\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_lock_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_lock_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_lock_en`] module"] +#[doc(alias = "DEBUG_LOCK_EN")] +pub type DebugLockEn = crate::Reg; +#[doc = "Control Write Access to Security"] +pub mod debug_lock_en; +#[doc = "DEBUG_FEATURES (rw) register accessor: Cortex Debug Features Control\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_features`] module"] +#[doc(alias = "DEBUG_FEATURES")] +pub type DebugFeatures = crate::Reg; +#[doc = "Cortex Debug Features Control"] +pub mod debug_features; +#[doc = "DEBUG_FEATURES_DP (rw) register accessor: Cortex Debug Features Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features_dp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features_dp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_features_dp`] module"] +#[doc(alias = "DEBUG_FEATURES_DP")] +pub type DebugFeaturesDp = crate::Reg; +#[doc = "Cortex Debug Features Control (Duplicate)"] +pub mod debug_features_dp; +#[doc = "SWD_ACCESS_CPU0 (rw) register accessor: CPU0 Software Debug Access\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_access_cpu0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_access_cpu0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swd_access_cpu0`] module"] +#[doc(alias = "SWD_ACCESS_CPU0")] +pub type SwdAccessCpu0 = crate::Reg; +#[doc = "CPU0 Software Debug Access"] +pub mod swd_access_cpu0; +#[doc = "DEBUG_AUTH_BEACON (rw) register accessor: Debug Authentication BEACON\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_auth_beacon::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_auth_beacon::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_auth_beacon`] module"] +#[doc(alias = "DEBUG_AUTH_BEACON")] +pub type DebugAuthBeacon = crate::Reg; +#[doc = "Debug Authentication BEACON"] +pub mod debug_auth_beacon; +#[doc = "JTAG_ID (r) register accessor: JTAG Chip ID\n\nYou can [`read`](crate::Reg::read) this register and get [`jtag_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_id`] module"] +#[doc(alias = "JTAG_ID")] +pub type JtagId = crate::Reg; +#[doc = "JTAG Chip ID"] +pub mod jtag_id; +#[doc = "DEVICE_TYPE (r) register accessor: Device Type\n\nYou can [`read`](crate::Reg::read) this register and get [`device_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_type`] module"] +#[doc(alias = "DEVICE_TYPE")] +pub type DeviceType = crate::Reg; +#[doc = "Device Type"] +pub mod device_type; +#[doc = "DEVICE_ID0 (r) register accessor: Device ID\n\nYou can [`read`](crate::Reg::read) this register and get [`device_id0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_id0`] module"] +#[doc(alias = "DEVICE_ID0")] +pub type DeviceId0 = crate::Reg; +#[doc = "Device ID"] +pub mod device_id0; +#[doc = "DIEID (r) register accessor: Chip Revision ID and Number\n\nYou can [`read`](crate::Reg::read) this register and get [`dieid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieid`] module"] +#[doc(alias = "DIEID")] +pub type Dieid = crate::Reg; +#[doc = "Chip Revision ID and Number"] +pub mod dieid; diff --git a/mcxa276-pac/src/syscon/ahbclkdiv.rs b/mcxa276-pac/src/syscon/ahbclkdiv.rs new file mode 100644 index 000000000..7b2fe415b --- /dev/null +++ b/mcxa276-pac/src/syscon/ahbclkdiv.rs @@ -0,0 +1,76 @@ +#[doc = "Register `AHBCLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `AHBCLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Clock divider value"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Clock divider value"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + Stable = 0, + #[doc = "1: Clock frequency is not stable"] + Ongoing = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::Stable, + true => Unstab::Ongoing, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_stable(&self) -> bool { + *self == Unstab::Stable + } + #[doc = "Clock frequency is not stable"] + #[inline(always)] + pub fn is_ongoing(&self) -> bool { + *self == Unstab::Ongoing + } +} +impl R { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } +} +#[doc = "System Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AhbclkdivSpec; +impl crate::RegisterSpec for AhbclkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahbclkdiv::R`](R) reader structure"] +impl crate::Readable for AhbclkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`ahbclkdiv::W`](W) writer structure"] +impl crate::Writable for AhbclkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets AHBCLKDIV to value 0"] +impl crate::Resettable for AhbclkdivSpec {} diff --git a/mcxa276-pac/src/syscon/ahbmatprio.rs b/mcxa276-pac/src/syscon/ahbmatprio.rs new file mode 100644 index 000000000..83422a33e --- /dev/null +++ b/mcxa276-pac/src/syscon/ahbmatprio.rs @@ -0,0 +1,695 @@ +#[doc = "Register `AHBMATPRIO` reader"] +pub type R = crate::R; +#[doc = "Register `AHBMATPRIO` writer"] +pub type W = crate::W; +#[doc = "CPU0 C-AHB bus master priority level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu0Cbus { + #[doc = "0: level 0"] + Level0 = 0, + #[doc = "1: level 1"] + Level1 = 1, + #[doc = "2: level 2"] + Level2 = 2, + #[doc = "3: level 3"] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu0Cbus) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu0Cbus { + type Ux = u8; +} +impl crate::IsEnum for Cpu0Cbus {} +#[doc = "Field `CPU0_CBUS` reader - CPU0 C-AHB bus master priority level"] +pub type Cpu0CbusR = crate::FieldReader; +impl Cpu0CbusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpu0Cbus { + match self.bits { + 0 => Cpu0Cbus::Level0, + 1 => Cpu0Cbus::Level1, + 2 => Cpu0Cbus::Level2, + 3 => Cpu0Cbus::Level3, + _ => unreachable!(), + } + } + #[doc = "level 0"] + #[inline(always)] + pub fn is_level0(&self) -> bool { + *self == Cpu0Cbus::Level0 + } + #[doc = "level 1"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == Cpu0Cbus::Level1 + } + #[doc = "level 2"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == Cpu0Cbus::Level2 + } + #[doc = "level 3"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == Cpu0Cbus::Level3 + } +} +#[doc = "Field `CPU0_CBUS` writer - CPU0 C-AHB bus master priority level"] +pub type Cpu0CbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Cbus, crate::Safe>; +impl<'a, REG> Cpu0CbusW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "level 0"] + #[inline(always)] + pub fn level0(self) -> &'a mut crate::W { + self.variant(Cpu0Cbus::Level0) + } + #[doc = "level 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut crate::W { + self.variant(Cpu0Cbus::Level1) + } + #[doc = "level 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut crate::W { + self.variant(Cpu0Cbus::Level2) + } + #[doc = "level 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut crate::W { + self.variant(Cpu0Cbus::Level3) + } +} +#[doc = "CPU0 S-AHB bus master priority level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu0Sbus { + #[doc = "0: level 0"] + Level0 = 0, + #[doc = "1: level 1"] + Level1 = 1, + #[doc = "2: level 2"] + Level2 = 2, + #[doc = "3: level 3"] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu0Sbus) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu0Sbus { + type Ux = u8; +} +impl crate::IsEnum for Cpu0Sbus {} +#[doc = "Field `CPU0_SBUS` reader - CPU0 S-AHB bus master priority level"] +pub type Cpu0SbusR = crate::FieldReader; +impl Cpu0SbusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpu0Sbus { + match self.bits { + 0 => Cpu0Sbus::Level0, + 1 => Cpu0Sbus::Level1, + 2 => Cpu0Sbus::Level2, + 3 => Cpu0Sbus::Level3, + _ => unreachable!(), + } + } + #[doc = "level 0"] + #[inline(always)] + pub fn is_level0(&self) -> bool { + *self == Cpu0Sbus::Level0 + } + #[doc = "level 1"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == Cpu0Sbus::Level1 + } + #[doc = "level 2"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == Cpu0Sbus::Level2 + } + #[doc = "level 3"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == Cpu0Sbus::Level3 + } +} +#[doc = "Field `CPU0_SBUS` writer - CPU0 S-AHB bus master priority level"] +pub type Cpu0SbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Sbus, crate::Safe>; +impl<'a, REG> Cpu0SbusW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "level 0"] + #[inline(always)] + pub fn level0(self) -> &'a mut crate::W { + self.variant(Cpu0Sbus::Level0) + } + #[doc = "level 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut crate::W { + self.variant(Cpu0Sbus::Level1) + } + #[doc = "level 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut crate::W { + self.variant(Cpu0Sbus::Level2) + } + #[doc = "level 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut crate::W { + self.variant(Cpu0Sbus::Level3) + } +} +#[doc = "SmartDMA-I bus master priority level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu1CbusSmartDmaI { + #[doc = "0: level 0"] + Level0 = 0, + #[doc = "1: level 1"] + Level1 = 1, + #[doc = "2: level 2"] + Level2 = 2, + #[doc = "3: level 3"] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu1CbusSmartDmaI) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu1CbusSmartDmaI { + type Ux = u8; +} +impl crate::IsEnum for Cpu1CbusSmartDmaI {} +#[doc = "Field `CPU1_CBUS_SmartDMA_I` reader - SmartDMA-I bus master priority level"] +pub type Cpu1CbusSmartDmaIR = crate::FieldReader; +impl Cpu1CbusSmartDmaIR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpu1CbusSmartDmaI { + match self.bits { + 0 => Cpu1CbusSmartDmaI::Level0, + 1 => Cpu1CbusSmartDmaI::Level1, + 2 => Cpu1CbusSmartDmaI::Level2, + 3 => Cpu1CbusSmartDmaI::Level3, + _ => unreachable!(), + } + } + #[doc = "level 0"] + #[inline(always)] + pub fn is_level0(&self) -> bool { + *self == Cpu1CbusSmartDmaI::Level0 + } + #[doc = "level 1"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == Cpu1CbusSmartDmaI::Level1 + } + #[doc = "level 2"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == Cpu1CbusSmartDmaI::Level2 + } + #[doc = "level 3"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == Cpu1CbusSmartDmaI::Level3 + } +} +#[doc = "Field `CPU1_CBUS_SmartDMA_I` writer - SmartDMA-I bus master priority level"] +pub type Cpu1CbusSmartDmaIW<'a, REG> = + crate::FieldWriter<'a, REG, 2, Cpu1CbusSmartDmaI, crate::Safe>; +impl<'a, REG> Cpu1CbusSmartDmaIW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "level 0"] + #[inline(always)] + pub fn level0(self) -> &'a mut crate::W { + self.variant(Cpu1CbusSmartDmaI::Level0) + } + #[doc = "level 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut crate::W { + self.variant(Cpu1CbusSmartDmaI::Level1) + } + #[doc = "level 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut crate::W { + self.variant(Cpu1CbusSmartDmaI::Level2) + } + #[doc = "level 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut crate::W { + self.variant(Cpu1CbusSmartDmaI::Level3) + } +} +#[doc = "SmartDMA-D bus master priority level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu1SbusSmartDmaD { + #[doc = "0: level 0"] + Level0 = 0, + #[doc = "1: level 1"] + Level1 = 1, + #[doc = "2: level 2"] + Level2 = 2, + #[doc = "3: level 3"] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu1SbusSmartDmaD) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu1SbusSmartDmaD { + type Ux = u8; +} +impl crate::IsEnum for Cpu1SbusSmartDmaD {} +#[doc = "Field `CPU1_SBUS_SmartDMA_D` reader - SmartDMA-D bus master priority level"] +pub type Cpu1SbusSmartDmaDR = crate::FieldReader; +impl Cpu1SbusSmartDmaDR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpu1SbusSmartDmaD { + match self.bits { + 0 => Cpu1SbusSmartDmaD::Level0, + 1 => Cpu1SbusSmartDmaD::Level1, + 2 => Cpu1SbusSmartDmaD::Level2, + 3 => Cpu1SbusSmartDmaD::Level3, + _ => unreachable!(), + } + } + #[doc = "level 0"] + #[inline(always)] + pub fn is_level0(&self) -> bool { + *self == Cpu1SbusSmartDmaD::Level0 + } + #[doc = "level 1"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == Cpu1SbusSmartDmaD::Level1 + } + #[doc = "level 2"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == Cpu1SbusSmartDmaD::Level2 + } + #[doc = "level 3"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == Cpu1SbusSmartDmaD::Level3 + } +} +#[doc = "Field `CPU1_SBUS_SmartDMA_D` writer - SmartDMA-D bus master priority level"] +pub type Cpu1SbusSmartDmaDW<'a, REG> = + crate::FieldWriter<'a, REG, 2, Cpu1SbusSmartDmaD, crate::Safe>; +impl<'a, REG> Cpu1SbusSmartDmaDW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "level 0"] + #[inline(always)] + pub fn level0(self) -> &'a mut crate::W { + self.variant(Cpu1SbusSmartDmaD::Level0) + } + #[doc = "level 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut crate::W { + self.variant(Cpu1SbusSmartDmaD::Level1) + } + #[doc = "level 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut crate::W { + self.variant(Cpu1SbusSmartDmaD::Level2) + } + #[doc = "level 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut crate::W { + self.variant(Cpu1SbusSmartDmaD::Level3) + } +} +#[doc = "DMA0 controller bus master priority level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dma0 { + #[doc = "0: level 0"] + Level0 = 0, + #[doc = "1: level 1"] + Level1 = 1, + #[doc = "2: level 2"] + Level2 = 2, + #[doc = "3: level 3"] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dma0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dma0 { + type Ux = u8; +} +impl crate::IsEnum for Dma0 {} +#[doc = "Field `DMA0` reader - DMA0 controller bus master priority level"] +pub type Dma0R = crate::FieldReader; +impl Dma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dma0 { + match self.bits { + 0 => Dma0::Level0, + 1 => Dma0::Level1, + 2 => Dma0::Level2, + 3 => Dma0::Level3, + _ => unreachable!(), + } + } + #[doc = "level 0"] + #[inline(always)] + pub fn is_level0(&self) -> bool { + *self == Dma0::Level0 + } + #[doc = "level 1"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == Dma0::Level1 + } + #[doc = "level 2"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == Dma0::Level2 + } + #[doc = "level 3"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == Dma0::Level3 + } +} +#[doc = "Field `DMA0` writer - DMA0 controller bus master priority level"] +pub type Dma0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Dma0, crate::Safe>; +impl<'a, REG> Dma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "level 0"] + #[inline(always)] + pub fn level0(self) -> &'a mut crate::W { + self.variant(Dma0::Level0) + } + #[doc = "level 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut crate::W { + self.variant(Dma0::Level1) + } + #[doc = "level 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut crate::W { + self.variant(Dma0::Level2) + } + #[doc = "level 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut crate::W { + self.variant(Dma0::Level3) + } +} +#[doc = "PKC and ELS bus master priority level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PkcEls { + #[doc = "0: level 0"] + Level0 = 0, + #[doc = "1: level 1"] + Level1 = 1, + #[doc = "2: level 2"] + Level2 = 2, + #[doc = "3: level 3"] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PkcEls) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PkcEls { + type Ux = u8; +} +impl crate::IsEnum for PkcEls {} +#[doc = "Field `PKC_ELS` reader - PKC and ELS bus master priority level"] +pub type PkcElsR = crate::FieldReader; +impl PkcElsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PkcEls { + match self.bits { + 0 => PkcEls::Level0, + 1 => PkcEls::Level1, + 2 => PkcEls::Level2, + 3 => PkcEls::Level3, + _ => unreachable!(), + } + } + #[doc = "level 0"] + #[inline(always)] + pub fn is_level0(&self) -> bool { + *self == PkcEls::Level0 + } + #[doc = "level 1"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == PkcEls::Level1 + } + #[doc = "level 2"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == PkcEls::Level2 + } + #[doc = "level 3"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == PkcEls::Level3 + } +} +#[doc = "Field `PKC_ELS` writer - PKC and ELS bus master priority level"] +pub type PkcElsW<'a, REG> = crate::FieldWriter<'a, REG, 2, PkcEls, crate::Safe>; +impl<'a, REG> PkcElsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "level 0"] + #[inline(always)] + pub fn level0(self) -> &'a mut crate::W { + self.variant(PkcEls::Level0) + } + #[doc = "level 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut crate::W { + self.variant(PkcEls::Level1) + } + #[doc = "level 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut crate::W { + self.variant(PkcEls::Level2) + } + #[doc = "level 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut crate::W { + self.variant(PkcEls::Level3) + } +} +#[doc = "USB-FS bus master priority level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum UsbFsEnet { + #[doc = "0: level 0"] + Level0 = 0, + #[doc = "1: level 1"] + Level1 = 1, + #[doc = "2: level 2"] + Level2 = 2, + #[doc = "3: level 3"] + Level3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: UsbFsEnet) -> Self { + variant as _ + } +} +impl crate::FieldSpec for UsbFsEnet { + type Ux = u8; +} +impl crate::IsEnum for UsbFsEnet {} +#[doc = "Field `USB_FS_ENET` reader - USB-FS bus master priority level"] +pub type UsbFsEnetR = crate::FieldReader; +impl UsbFsEnetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> UsbFsEnet { + match self.bits { + 0 => UsbFsEnet::Level0, + 1 => UsbFsEnet::Level1, + 2 => UsbFsEnet::Level2, + 3 => UsbFsEnet::Level3, + _ => unreachable!(), + } + } + #[doc = "level 0"] + #[inline(always)] + pub fn is_level0(&self) -> bool { + *self == UsbFsEnet::Level0 + } + #[doc = "level 1"] + #[inline(always)] + pub fn is_level1(&self) -> bool { + *self == UsbFsEnet::Level1 + } + #[doc = "level 2"] + #[inline(always)] + pub fn is_level2(&self) -> bool { + *self == UsbFsEnet::Level2 + } + #[doc = "level 3"] + #[inline(always)] + pub fn is_level3(&self) -> bool { + *self == UsbFsEnet::Level3 + } +} +#[doc = "Field `USB_FS_ENET` writer - USB-FS bus master priority level"] +pub type UsbFsEnetW<'a, REG> = crate::FieldWriter<'a, REG, 2, UsbFsEnet, crate::Safe>; +impl<'a, REG> UsbFsEnetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "level 0"] + #[inline(always)] + pub fn level0(self) -> &'a mut crate::W { + self.variant(UsbFsEnet::Level0) + } + #[doc = "level 1"] + #[inline(always)] + pub fn level1(self) -> &'a mut crate::W { + self.variant(UsbFsEnet::Level1) + } + #[doc = "level 2"] + #[inline(always)] + pub fn level2(self) -> &'a mut crate::W { + self.variant(UsbFsEnet::Level2) + } + #[doc = "level 3"] + #[inline(always)] + pub fn level3(self) -> &'a mut crate::W { + self.variant(UsbFsEnet::Level3) + } +} +impl R { + #[doc = "Bits 0:1 - CPU0 C-AHB bus master priority level"] + #[inline(always)] + pub fn cpu0_cbus(&self) -> Cpu0CbusR { + Cpu0CbusR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - CPU0 S-AHB bus master priority level"] + #[inline(always)] + pub fn cpu0_sbus(&self) -> Cpu0SbusR { + Cpu0SbusR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - SmartDMA-I bus master priority level"] + #[inline(always)] + pub fn cpu1_cbus_smart_dma_i(&self) -> Cpu1CbusSmartDmaIR { + Cpu1CbusSmartDmaIR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - SmartDMA-D bus master priority level"] + #[inline(always)] + pub fn cpu1_sbus_smart_dma_d(&self) -> Cpu1SbusSmartDmaDR { + Cpu1SbusSmartDmaDR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - DMA0 controller bus master priority level"] + #[inline(always)] + pub fn dma0(&self) -> Dma0R { + Dma0R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 12:13 - PKC and ELS bus master priority level"] + #[inline(always)] + pub fn pkc_els(&self) -> PkcElsR { + PkcElsR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 24:25 - USB-FS bus master priority level"] + #[inline(always)] + pub fn usb_fs_enet(&self) -> UsbFsEnetR { + UsbFsEnetR::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CPU0 C-AHB bus master priority level"] + #[inline(always)] + pub fn cpu0_cbus(&mut self) -> Cpu0CbusW { + Cpu0CbusW::new(self, 0) + } + #[doc = "Bits 2:3 - CPU0 S-AHB bus master priority level"] + #[inline(always)] + pub fn cpu0_sbus(&mut self) -> Cpu0SbusW { + Cpu0SbusW::new(self, 2) + } + #[doc = "Bits 4:5 - SmartDMA-I bus master priority level"] + #[inline(always)] + pub fn cpu1_cbus_smart_dma_i(&mut self) -> Cpu1CbusSmartDmaIW { + Cpu1CbusSmartDmaIW::new(self, 4) + } + #[doc = "Bits 6:7 - SmartDMA-D bus master priority level"] + #[inline(always)] + pub fn cpu1_sbus_smart_dma_d(&mut self) -> Cpu1SbusSmartDmaDW { + Cpu1SbusSmartDmaDW::new(self, 6) + } + #[doc = "Bits 8:9 - DMA0 controller bus master priority level"] + #[inline(always)] + pub fn dma0(&mut self) -> Dma0W { + Dma0W::new(self, 8) + } + #[doc = "Bits 12:13 - PKC and ELS bus master priority level"] + #[inline(always)] + pub fn pkc_els(&mut self) -> PkcElsW { + PkcElsW::new(self, 12) + } + #[doc = "Bits 24:25 - USB-FS bus master priority level"] + #[inline(always)] + pub fn usb_fs_enet(&mut self) -> UsbFsEnetW { + UsbFsEnetW::new(self, 24) + } +} +#[doc = "AHB Matrix Priority Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbmatprio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbmatprio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AhbmatprioSpec; +impl crate::RegisterSpec for AhbmatprioSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahbmatprio::R`](R) reader structure"] +impl crate::Readable for AhbmatprioSpec {} +#[doc = "`write(|w| ..)` method takes [`ahbmatprio::W`](W) writer structure"] +impl crate::Writable for AhbmatprioSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets AHBMATPRIO to value 0"] +impl crate::Resettable for AhbmatprioSpec {} diff --git a/mcxa276-pac/src/syscon/binary_code_lsb.rs b/mcxa276-pac/src/syscon/binary_code_lsb.rs new file mode 100644 index 000000000..1af5e17ce --- /dev/null +++ b/mcxa276-pac/src/syscon/binary_code_lsb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `BINARY_CODE_LSB` reader"] +pub type R = crate::R; +#[doc = "Field `code_bin_31_0` reader - Binary code \\[31:0\\]"] +pub type CodeBin31_0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Binary code \\[31:0\\]"] + #[inline(always)] + pub fn code_bin_31_0(&self) -> CodeBin31_0R { + CodeBin31_0R::new(self.bits) + } +} +#[doc = "Gray to Binary Converter Binary Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_lsb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BinaryCodeLsbSpec; +impl crate::RegisterSpec for BinaryCodeLsbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`binary_code_lsb::R`](R) reader structure"] +impl crate::Readable for BinaryCodeLsbSpec {} +#[doc = "`reset()` method sets BINARY_CODE_LSB to value 0"] +impl crate::Resettable for BinaryCodeLsbSpec {} diff --git a/mcxa276-pac/src/syscon/binary_code_msb.rs b/mcxa276-pac/src/syscon/binary_code_msb.rs new file mode 100644 index 000000000..f5d1bba17 --- /dev/null +++ b/mcxa276-pac/src/syscon/binary_code_msb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `BINARY_CODE_MSB` reader"] +pub type R = crate::R; +#[doc = "Field `code_bin_41_32` reader - Binary code \\[41:32\\]"] +pub type CodeBin41_32R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Binary code \\[41:32\\]"] + #[inline(always)] + pub fn code_bin_41_32(&self) -> CodeBin41_32R { + CodeBin41_32R::new((self.bits & 0x03ff) as u16) + } +} +#[doc = "Gray to Binary Converter Binary Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_msb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BinaryCodeMsbSpec; +impl crate::RegisterSpec for BinaryCodeMsbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`binary_code_msb::R`](R) reader structure"] +impl crate::Readable for BinaryCodeMsbSpec {} +#[doc = "`reset()` method sets BINARY_CODE_MSB to value 0"] +impl crate::Resettable for BinaryCodeMsbSpec {} diff --git a/mcxa276-pac/src/syscon/busclkdiv.rs b/mcxa276-pac/src/syscon/busclkdiv.rs new file mode 100644 index 000000000..290ca9b2d --- /dev/null +++ b/mcxa276-pac/src/syscon/busclkdiv.rs @@ -0,0 +1,197 @@ +#[doc = "Register `BUSCLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `BUSCLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Clock divider value"] +pub type DivR = crate::FieldReader; +#[doc = "Resets the divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider is not reset"] + Released = 0, + #[doc = "1: Divider is reset"] + Asserted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` reader - Resets the divider counter"] +pub type ResetR = crate::BitReader; +impl ResetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reset { + match self.bits { + false => Reset::Released, + true => Reset::Asserted, + } + } + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn is_released(&self) -> bool { + *self == Reset::Released + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn is_asserted(&self) -> bool { + *self == Reset::Asserted + } +} +#[doc = "Field `RESET` writer - Resets the divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn released(self) -> &'a mut crate::W { + self.variant(Reset::Released) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn asserted(self) -> &'a mut crate::W { + self.variant(Reset::Asserted) + } +} +#[doc = "Halts the divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + Run = 0, + #[doc = "1: Divider clock is stopped"] + Halt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halts the divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::Run, + true => Halt::Halt, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == Halt::Run + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_halt(&self) -> bool { + *self == Halt::Halt + } +} +#[doc = "Field `HALT` writer - Halts the divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn run(self) -> &'a mut crate::W { + self.variant(Halt::Run) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn halt(self) -> &'a mut crate::W { + self.variant(Halt::Halt) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + Stable = 0, + #[doc = "1: Clock frequency is not stable"] + Ongoing = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::Stable, + true => Unstab::Ongoing, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_stable(&self) -> bool { + *self == Unstab::Stable + } + #[doc = "Clock frequency is not stable"] + #[inline(always)] + pub fn is_ongoing(&self) -> bool { + *self == Unstab::Ongoing + } +} +impl R { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&self) -> ResetR { + ResetR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "BUS_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`busclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`busclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BusclkdivSpec; +impl crate::RegisterSpec for BusclkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`busclkdiv::R`](R) reader structure"] +impl crate::Readable for BusclkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`busclkdiv::W`](W) writer structure"] +impl crate::Writable for BusclkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BUSCLKDIV to value 0x01"] +impl crate::Resettable for BusclkdivSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/syscon/clkunlock.rs b/mcxa276-pac/src/syscon/clkunlock.rs new file mode 100644 index 000000000..9ed9c9b9c --- /dev/null +++ b/mcxa276-pac/src/syscon/clkunlock.rs @@ -0,0 +1,84 @@ +#[doc = "Register `CLKUNLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `CLKUNLOCK` writer"] +pub type W = crate::W; +#[doc = "Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unlock { + #[doc = "0: Updates are allowed to all clock configuration registers"] + Enable = 0, + #[doc = "1: Freezes all clock configuration registers update."] + Freeze = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unlock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNLOCK` reader - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] +pub type UnlockR = crate::BitReader; +impl UnlockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unlock { + match self.bits { + false => Unlock::Enable, + true => Unlock::Freeze, + } + } + #[doc = "Updates are allowed to all clock configuration registers"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Unlock::Enable + } + #[doc = "Freezes all clock configuration registers update."] + #[inline(always)] + pub fn is_freeze(&self) -> bool { + *self == Unlock::Freeze + } +} +#[doc = "Field `UNLOCK` writer - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] +pub type UnlockW<'a, REG> = crate::BitWriter<'a, REG, Unlock>; +impl<'a, REG> UnlockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Updates are allowed to all clock configuration registers"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Unlock::Enable) + } + #[doc = "Freezes all clock configuration registers update."] + #[inline(always)] + pub fn freeze(self) -> &'a mut crate::W { + self.variant(Unlock::Freeze) + } +} +impl R { + #[doc = "Bit 0 - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] + #[inline(always)] + pub fn unlock(&self) -> UnlockR { + UnlockR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] + #[inline(always)] + pub fn unlock(&mut self) -> UnlockW { + UnlockW::new(self, 0) + } +} +#[doc = "Clock Configuration Unlock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkunlock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkunlock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkunlockSpec; +impl crate::RegisterSpec for ClkunlockSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkunlock::R`](R) reader structure"] +impl crate::Readable for ClkunlockSpec {} +#[doc = "`write(|w| ..)` method takes [`clkunlock::W`](W) writer structure"] +impl crate::Writable for ClkunlockSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKUNLOCK to value 0"] +impl crate::Resettable for ClkunlockSpec {} diff --git a/mcxa276-pac/src/syscon/cpu0nstckcal.rs b/mcxa276-pac/src/syscon/cpu0nstckcal.rs new file mode 100644 index 000000000..626c2e4f5 --- /dev/null +++ b/mcxa276-pac/src/syscon/cpu0nstckcal.rs @@ -0,0 +1,161 @@ +#[doc = "Register `CPU0NSTCKCAL` reader"] +pub type R = crate::R; +#[doc = "Register `CPU0NSTCKCAL` writer"] +pub type W = crate::W; +#[doc = "Field `TENMS` reader - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] +pub type TenmsR = crate::FieldReader; +#[doc = "Field `TENMS` writer - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] +pub type TenmsW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Indicates whether the TENMS value is exact.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Skew { + #[doc = "0: TENMS value is exact"] + Exact = 0, + #[doc = "1: TENMS value is not exact or not given"] + Inexact = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Skew) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - Indicates whether the TENMS value is exact."] +pub type SkewR = crate::BitReader; +impl SkewR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Skew { + match self.bits { + false => Skew::Exact, + true => Skew::Inexact, + } + } + #[doc = "TENMS value is exact"] + #[inline(always)] + pub fn is_exact(&self) -> bool { + *self == Skew::Exact + } + #[doc = "TENMS value is not exact or not given"] + #[inline(always)] + pub fn is_inexact(&self) -> bool { + *self == Skew::Inexact + } +} +#[doc = "Field `SKEW` writer - Indicates whether the TENMS value is exact."] +pub type SkewW<'a, REG> = crate::BitWriter<'a, REG, Skew>; +impl<'a, REG> SkewW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "TENMS value is exact"] + #[inline(always)] + pub fn exact(self) -> &'a mut crate::W { + self.variant(Skew::Exact) + } + #[doc = "TENMS value is not exact or not given"] + #[inline(always)] + pub fn inexact(self) -> &'a mut crate::W { + self.variant(Skew::Inexact) + } +} +#[doc = "Indicates whether the device provides a reference clock to the processor.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Noref { + #[doc = "0: Reference clock is provided"] + YesRef = 0, + #[doc = "1: No reference clock is provided"] + NoRef = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Noref) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - Indicates whether the device provides a reference clock to the processor."] +pub type NorefR = crate::BitReader; +impl NorefR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Noref { + match self.bits { + false => Noref::YesRef, + true => Noref::NoRef, + } + } + #[doc = "Reference clock is provided"] + #[inline(always)] + pub fn is_yes_ref(&self) -> bool { + *self == Noref::YesRef + } + #[doc = "No reference clock is provided"] + #[inline(always)] + pub fn is_no_ref(&self) -> bool { + *self == Noref::NoRef + } +} +#[doc = "Field `NOREF` writer - Indicates whether the device provides a reference clock to the processor."] +pub type NorefW<'a, REG> = crate::BitWriter<'a, REG, Noref>; +impl<'a, REG> NorefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Reference clock is provided"] + #[inline(always)] + pub fn yes_ref(self) -> &'a mut crate::W { + self.variant(Noref::YesRef) + } + #[doc = "No reference clock is provided"] + #[inline(always)] + pub fn no_ref(self) -> &'a mut crate::W { + self.variant(Noref::NoRef) + } +} +impl R { + #[doc = "Bits 0:23 - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] + #[inline(always)] + pub fn tenms(&self) -> TenmsR { + TenmsR::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 24 - Indicates whether the TENMS value is exact."] + #[inline(always)] + pub fn skew(&self) -> SkewR { + SkewR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Indicates whether the device provides a reference clock to the processor."] + #[inline(always)] + pub fn noref(&self) -> NorefR { + NorefR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:23 - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] + #[inline(always)] + pub fn tenms(&mut self) -> TenmsW { + TenmsW::new(self, 0) + } + #[doc = "Bit 24 - Indicates whether the TENMS value is exact."] + #[inline(always)] + pub fn skew(&mut self) -> SkewW { + SkewW::new(self, 24) + } + #[doc = "Bit 25 - Indicates whether the device provides a reference clock to the processor."] + #[inline(always)] + pub fn noref(&mut self) -> NorefW { + NorefW::new(self, 25) + } +} +#[doc = "Non-Secure CPU0 System Tick Calibration\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu0nstckcal::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu0nstckcal::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cpu0nstckcalSpec; +impl crate::RegisterSpec for Cpu0nstckcalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu0nstckcal::R`](R) reader structure"] +impl crate::Readable for Cpu0nstckcalSpec {} +#[doc = "`write(|w| ..)` method takes [`cpu0nstckcal::W`](W) writer structure"] +impl crate::Writable for Cpu0nstckcalSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CPU0NSTCKCAL to value 0"] +impl crate::Resettable for Cpu0nstckcalSpec {} diff --git a/mcxa276-pac/src/syscon/cpustat.rs b/mcxa276-pac/src/syscon/cpustat.rs new file mode 100644 index 000000000..a7b03e62a --- /dev/null +++ b/mcxa276-pac/src/syscon/cpustat.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CPUSTAT` reader"] +pub type R = crate::R; +#[doc = "CPU0 sleeping state\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cpu0sleeping { + #[doc = "0: CPU is not sleeping"] + Awake = 0, + #[doc = "1: CPU is sleeping"] + Sleeping = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cpu0sleeping) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPU0SLEEPING` reader - CPU0 sleeping state"] +pub type Cpu0sleepingR = crate::BitReader; +impl Cpu0sleepingR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpu0sleeping { + match self.bits { + false => Cpu0sleeping::Awake, + true => Cpu0sleeping::Sleeping, + } + } + #[doc = "CPU is not sleeping"] + #[inline(always)] + pub fn is_awake(&self) -> bool { + *self == Cpu0sleeping::Awake + } + #[doc = "CPU is sleeping"] + #[inline(always)] + pub fn is_sleeping(&self) -> bool { + *self == Cpu0sleeping::Sleeping + } +} +#[doc = "CPU0 lockup state\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cpu0lockup { + #[doc = "0: CPU is not in lockup"] + Awake = 0, + #[doc = "1: CPU is in lockup"] + Sleeping = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cpu0lockup) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPU0LOCKUP` reader - CPU0 lockup state"] +pub type Cpu0lockupR = crate::BitReader; +impl Cpu0lockupR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpu0lockup { + match self.bits { + false => Cpu0lockup::Awake, + true => Cpu0lockup::Sleeping, + } + } + #[doc = "CPU is not in lockup"] + #[inline(always)] + pub fn is_awake(&self) -> bool { + *self == Cpu0lockup::Awake + } + #[doc = "CPU is in lockup"] + #[inline(always)] + pub fn is_sleeping(&self) -> bool { + *self == Cpu0lockup::Sleeping + } +} +impl R { + #[doc = "Bit 0 - CPU0 sleeping state"] + #[inline(always)] + pub fn cpu0sleeping(&self) -> Cpu0sleepingR { + Cpu0sleepingR::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - CPU0 lockup state"] + #[inline(always)] + pub fn cpu0lockup(&self) -> Cpu0lockupR { + Cpu0lockupR::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "CPU Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cpustat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CpustatSpec; +impl crate::RegisterSpec for CpustatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpustat::R`](R) reader structure"] +impl crate::Readable for CpustatSpec {} +#[doc = "`reset()` method sets CPUSTAT to value 0"] +impl crate::Resettable for CpustatSpec {} diff --git a/mcxa276-pac/src/syscon/ctimerglobalstarten.rs b/mcxa276-pac/src/syscon/ctimerglobalstarten.rs new file mode 100644 index 000000000..604a8e1b3 --- /dev/null +++ b/mcxa276-pac/src/syscon/ctimerglobalstarten.rs @@ -0,0 +1,336 @@ +#[doc = "Register `CTIMERGLOBALSTARTEN` reader"] +pub type R = crate::R; +#[doc = "Register `CTIMERGLOBALSTARTEN` writer"] +pub type W = crate::W; +#[doc = "Enables the CTIMER0 function clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer0ClkEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer0ClkEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER0_CLK_EN` reader - Enables the CTIMER0 function clock"] +pub type Ctimer0ClkEnR = crate::BitReader; +impl Ctimer0ClkEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer0ClkEn { + match self.bits { + false => Ctimer0ClkEn::Disable, + true => Ctimer0ClkEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ctimer0ClkEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ctimer0ClkEn::Enable + } +} +#[doc = "Field `CTIMER0_CLK_EN` writer - Enables the CTIMER0 function clock"] +pub type Ctimer0ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer0ClkEn>; +impl<'a, REG> Ctimer0ClkEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ctimer0ClkEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ctimer0ClkEn::Enable) + } +} +#[doc = "Enables the CTIMER1 function clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer1ClkEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer1ClkEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER1_CLK_EN` reader - Enables the CTIMER1 function clock"] +pub type Ctimer1ClkEnR = crate::BitReader; +impl Ctimer1ClkEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer1ClkEn { + match self.bits { + false => Ctimer1ClkEn::Disable, + true => Ctimer1ClkEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ctimer1ClkEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ctimer1ClkEn::Enable + } +} +#[doc = "Field `CTIMER1_CLK_EN` writer - Enables the CTIMER1 function clock"] +pub type Ctimer1ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer1ClkEn>; +impl<'a, REG> Ctimer1ClkEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ctimer1ClkEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ctimer1ClkEn::Enable) + } +} +#[doc = "Enables the CTIMER2 function clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer2ClkEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer2ClkEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER2_CLK_EN` reader - Enables the CTIMER2 function clock"] +pub type Ctimer2ClkEnR = crate::BitReader; +impl Ctimer2ClkEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer2ClkEn { + match self.bits { + false => Ctimer2ClkEn::Disable, + true => Ctimer2ClkEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ctimer2ClkEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ctimer2ClkEn::Enable + } +} +#[doc = "Field `CTIMER2_CLK_EN` writer - Enables the CTIMER2 function clock"] +pub type Ctimer2ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer2ClkEn>; +impl<'a, REG> Ctimer2ClkEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ctimer2ClkEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ctimer2ClkEn::Enable) + } +} +#[doc = "Enables the CTIMER3 function clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer3ClkEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer3ClkEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER3_CLK_EN` reader - Enables the CTIMER3 function clock"] +pub type Ctimer3ClkEnR = crate::BitReader; +impl Ctimer3ClkEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer3ClkEn { + match self.bits { + false => Ctimer3ClkEn::Disable, + true => Ctimer3ClkEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ctimer3ClkEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ctimer3ClkEn::Enable + } +} +#[doc = "Field `CTIMER3_CLK_EN` writer - Enables the CTIMER3 function clock"] +pub type Ctimer3ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer3ClkEn>; +impl<'a, REG> Ctimer3ClkEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ctimer3ClkEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ctimer3ClkEn::Enable) + } +} +#[doc = "Enables the CTIMER4 function clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctimer4ClkEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctimer4ClkEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTIMER4_CLK_EN` reader - Enables the CTIMER4 function clock"] +pub type Ctimer4ClkEnR = crate::BitReader; +impl Ctimer4ClkEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctimer4ClkEn { + match self.bits { + false => Ctimer4ClkEn::Disable, + true => Ctimer4ClkEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ctimer4ClkEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ctimer4ClkEn::Enable + } +} +#[doc = "Field `CTIMER4_CLK_EN` writer - Enables the CTIMER4 function clock"] +pub type Ctimer4ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer4ClkEn>; +impl<'a, REG> Ctimer4ClkEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ctimer4ClkEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ctimer4ClkEn::Enable) + } +} +impl R { + #[doc = "Bit 0 - Enables the CTIMER0 function clock"] + #[inline(always)] + pub fn ctimer0_clk_en(&self) -> Ctimer0ClkEnR { + Ctimer0ClkEnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables the CTIMER1 function clock"] + #[inline(always)] + pub fn ctimer1_clk_en(&self) -> Ctimer1ClkEnR { + Ctimer1ClkEnR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables the CTIMER2 function clock"] + #[inline(always)] + pub fn ctimer2_clk_en(&self) -> Ctimer2ClkEnR { + Ctimer2ClkEnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables the CTIMER3 function clock"] + #[inline(always)] + pub fn ctimer3_clk_en(&self) -> Ctimer3ClkEnR { + Ctimer3ClkEnR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables the CTIMER4 function clock"] + #[inline(always)] + pub fn ctimer4_clk_en(&self) -> Ctimer4ClkEnR { + Ctimer4ClkEnR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the CTIMER0 function clock"] + #[inline(always)] + pub fn ctimer0_clk_en(&mut self) -> Ctimer0ClkEnW { + Ctimer0ClkEnW::new(self, 0) + } + #[doc = "Bit 1 - Enables the CTIMER1 function clock"] + #[inline(always)] + pub fn ctimer1_clk_en(&mut self) -> Ctimer1ClkEnW { + Ctimer1ClkEnW::new(self, 1) + } + #[doc = "Bit 2 - Enables the CTIMER2 function clock"] + #[inline(always)] + pub fn ctimer2_clk_en(&mut self) -> Ctimer2ClkEnW { + Ctimer2ClkEnW::new(self, 2) + } + #[doc = "Bit 3 - Enables the CTIMER3 function clock"] + #[inline(always)] + pub fn ctimer3_clk_en(&mut self) -> Ctimer3ClkEnW { + Ctimer3ClkEnW::new(self, 3) + } + #[doc = "Bit 4 - Enables the CTIMER4 function clock"] + #[inline(always)] + pub fn ctimer4_clk_en(&mut self) -> Ctimer4ClkEnW { + Ctimer4ClkEnW::new(self, 4) + } +} +#[doc = "CTIMER Global Start Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimerglobalstarten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimerglobalstarten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtimerglobalstartenSpec; +impl crate::RegisterSpec for CtimerglobalstartenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctimerglobalstarten::R`](R) reader structure"] +impl crate::Readable for CtimerglobalstartenSpec {} +#[doc = "`write(|w| ..)` method takes [`ctimerglobalstarten::W`](W) writer structure"] +impl crate::Writable for CtimerglobalstartenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTIMERGLOBALSTARTEN to value 0"] +impl crate::Resettable for CtimerglobalstartenSpec {} diff --git a/mcxa276-pac/src/syscon/debug_auth_beacon.rs b/mcxa276-pac/src/syscon/debug_auth_beacon.rs new file mode 100644 index 000000000..2194e93eb --- /dev/null +++ b/mcxa276-pac/src/syscon/debug_auth_beacon.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DEBUG_AUTH_BEACON` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUG_AUTH_BEACON` writer"] +pub type W = crate::W; +#[doc = "Field `BEACON` reader - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] +pub type BeaconR = crate::FieldReader; +#[doc = "Field `BEACON` writer - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] +pub type BeaconW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] + #[inline(always)] + pub fn beacon(&self) -> BeaconR { + BeaconR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] + #[inline(always)] + pub fn beacon(&mut self) -> BeaconW { + BeaconW::new(self, 0) + } +} +#[doc = "Debug Authentication BEACON\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_auth_beacon::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_auth_beacon::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DebugAuthBeaconSpec; +impl crate::RegisterSpec for DebugAuthBeaconSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_auth_beacon::R`](R) reader structure"] +impl crate::Readable for DebugAuthBeaconSpec {} +#[doc = "`write(|w| ..)` method takes [`debug_auth_beacon::W`](W) writer structure"] +impl crate::Writable for DebugAuthBeaconSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DEBUG_AUTH_BEACON to value 0"] +impl crate::Resettable for DebugAuthBeaconSpec {} diff --git a/mcxa276-pac/src/syscon/debug_features.rs b/mcxa276-pac/src/syscon/debug_features.rs new file mode 100644 index 000000000..e3cf873fb --- /dev/null +++ b/mcxa276-pac/src/syscon/debug_features.rs @@ -0,0 +1,161 @@ +#[doc = "Register `DEBUG_FEATURES` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUG_FEATURES` writer"] +pub type W = crate::W; +#[doc = "CPU0 invasive debug control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu0Dbgen { + #[doc = "1: Disables debug"] + Disable = 1, + #[doc = "2: Enables debug"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu0Dbgen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu0Dbgen { + type Ux = u8; +} +impl crate::IsEnum for Cpu0Dbgen {} +#[doc = "Field `CPU0_DBGEN` reader - CPU0 invasive debug control"] +pub type Cpu0DbgenR = crate::FieldReader; +impl Cpu0DbgenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Cpu0Dbgen::Disable), + 2 => Some(Cpu0Dbgen::Enable), + _ => None, + } + } + #[doc = "Disables debug"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Cpu0Dbgen::Disable + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Cpu0Dbgen::Enable + } +} +#[doc = "Field `CPU0_DBGEN` writer - CPU0 invasive debug control"] +pub type Cpu0DbgenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Dbgen>; +impl<'a, REG> Cpu0DbgenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disables debug"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Cpu0Dbgen::Disable) + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Cpu0Dbgen::Enable) + } +} +#[doc = "CPU0 non-invasive debug control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu0Niden { + #[doc = "1: Disables debug"] + Disable = 1, + #[doc = "2: Enables debug"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu0Niden) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu0Niden { + type Ux = u8; +} +impl crate::IsEnum for Cpu0Niden {} +#[doc = "Field `CPU0_NIDEN` reader - CPU0 non-invasive debug control"] +pub type Cpu0NidenR = crate::FieldReader; +impl Cpu0NidenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Cpu0Niden::Disable), + 2 => Some(Cpu0Niden::Enable), + _ => None, + } + } + #[doc = "Disables debug"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Cpu0Niden::Disable + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Cpu0Niden::Enable + } +} +#[doc = "Field `CPU0_NIDEN` writer - CPU0 non-invasive debug control"] +pub type Cpu0NidenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Niden>; +impl<'a, REG> Cpu0NidenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disables debug"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Cpu0Niden::Disable) + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Cpu0Niden::Enable) + } +} +impl R { + #[doc = "Bits 0:1 - CPU0 invasive debug control"] + #[inline(always)] + pub fn cpu0_dbgen(&self) -> Cpu0DbgenR { + Cpu0DbgenR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] + #[inline(always)] + pub fn cpu0_niden(&self) -> Cpu0NidenR { + Cpu0NidenR::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CPU0 invasive debug control"] + #[inline(always)] + pub fn cpu0_dbgen(&mut self) -> Cpu0DbgenW { + Cpu0DbgenW::new(self, 0) + } + #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] + #[inline(always)] + pub fn cpu0_niden(&mut self) -> Cpu0NidenW { + Cpu0NidenW::new(self, 2) + } +} +#[doc = "Cortex Debug Features Control\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DebugFeaturesSpec; +impl crate::RegisterSpec for DebugFeaturesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_features::R`](R) reader structure"] +impl crate::Readable for DebugFeaturesSpec {} +#[doc = "`write(|w| ..)` method takes [`debug_features::W`](W) writer structure"] +impl crate::Writable for DebugFeaturesSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DEBUG_FEATURES to value 0"] +impl crate::Resettable for DebugFeaturesSpec {} diff --git a/mcxa276-pac/src/syscon/debug_features_dp.rs b/mcxa276-pac/src/syscon/debug_features_dp.rs new file mode 100644 index 000000000..c5d830887 --- /dev/null +++ b/mcxa276-pac/src/syscon/debug_features_dp.rs @@ -0,0 +1,161 @@ +#[doc = "Register `DEBUG_FEATURES_DP` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUG_FEATURES_DP` writer"] +pub type W = crate::W; +#[doc = "CPU0 invasive debug control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu0Dbgen { + #[doc = "1: Disables debug"] + Disable = 1, + #[doc = "2: Enables debug"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu0Dbgen) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu0Dbgen { + type Ux = u8; +} +impl crate::IsEnum for Cpu0Dbgen {} +#[doc = "Field `CPU0_DBGEN` reader - CPU0 invasive debug control"] +pub type Cpu0DbgenR = crate::FieldReader; +impl Cpu0DbgenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Cpu0Dbgen::Disable), + 2 => Some(Cpu0Dbgen::Enable), + _ => None, + } + } + #[doc = "Disables debug"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Cpu0Dbgen::Disable + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Cpu0Dbgen::Enable + } +} +#[doc = "Field `CPU0_DBGEN` writer - CPU0 invasive debug control"] +pub type Cpu0DbgenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Dbgen>; +impl<'a, REG> Cpu0DbgenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disables debug"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Cpu0Dbgen::Disable) + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Cpu0Dbgen::Enable) + } +} +#[doc = "CPU0 non-invasive debug control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu0Niden { + #[doc = "1: Disables debug"] + Disable = 1, + #[doc = "2: Enables debug"] + Enable = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu0Niden) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu0Niden { + type Ux = u8; +} +impl crate::IsEnum for Cpu0Niden {} +#[doc = "Field `CPU0_NIDEN` reader - CPU0 non-invasive debug control"] +pub type Cpu0NidenR = crate::FieldReader; +impl Cpu0NidenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Cpu0Niden::Disable), + 2 => Some(Cpu0Niden::Enable), + _ => None, + } + } + #[doc = "Disables debug"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Cpu0Niden::Disable + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Cpu0Niden::Enable + } +} +#[doc = "Field `CPU0_NIDEN` writer - CPU0 non-invasive debug control"] +pub type Cpu0NidenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Niden>; +impl<'a, REG> Cpu0NidenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disables debug"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Cpu0Niden::Disable) + } + #[doc = "Enables debug"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Cpu0Niden::Enable) + } +} +impl R { + #[doc = "Bits 0:1 - CPU0 invasive debug control"] + #[inline(always)] + pub fn cpu0_dbgen(&self) -> Cpu0DbgenR { + Cpu0DbgenR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] + #[inline(always)] + pub fn cpu0_niden(&self) -> Cpu0NidenR { + Cpu0NidenR::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CPU0 invasive debug control"] + #[inline(always)] + pub fn cpu0_dbgen(&mut self) -> Cpu0DbgenW { + Cpu0DbgenW::new(self, 0) + } + #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] + #[inline(always)] + pub fn cpu0_niden(&mut self) -> Cpu0NidenW { + Cpu0NidenW::new(self, 2) + } +} +#[doc = "Cortex Debug Features Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features_dp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features_dp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DebugFeaturesDpSpec; +impl crate::RegisterSpec for DebugFeaturesDpSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_features_dp::R`](R) reader structure"] +impl crate::Readable for DebugFeaturesDpSpec {} +#[doc = "`write(|w| ..)` method takes [`debug_features_dp::W`](W) writer structure"] +impl crate::Writable for DebugFeaturesDpSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DEBUG_FEATURES_DP to value 0"] +impl crate::Resettable for DebugFeaturesDpSpec {} diff --git a/mcxa276-pac/src/syscon/debug_lock_en.rs b/mcxa276-pac/src/syscon/debug_lock_en.rs new file mode 100644 index 000000000..4c2160cac --- /dev/null +++ b/mcxa276-pac/src/syscon/debug_lock_en.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DEBUG_LOCK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUG_LOCK_EN` writer"] +pub type W = crate::W; +#[doc = "Controls write access to the security registers\n\nValue on reset: 10"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LockAll { + #[doc = "0: Any other value than b1010: disables write access to all registers"] + Disable = 0, + #[doc = "10: Enables write access to all registers"] + Enable = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LockAll) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LockAll { + type Ux = u8; +} +impl crate::IsEnum for LockAll {} +#[doc = "Field `LOCK_ALL` reader - Controls write access to the security registers"] +pub type LockAllR = crate::FieldReader; +impl LockAllR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(LockAll::Disable), + 10 => Some(LockAll::Enable), + _ => None, + } + } + #[doc = "Any other value than b1010: disables write access to all registers"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == LockAll::Disable + } + #[doc = "Enables write access to all registers"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == LockAll::Enable + } +} +#[doc = "Field `LOCK_ALL` writer - Controls write access to the security registers"] +pub type LockAllW<'a, REG> = crate::FieldWriter<'a, REG, 4, LockAll>; +impl<'a, REG> LockAllW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Any other value than b1010: disables write access to all registers"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(LockAll::Disable) + } + #[doc = "Enables write access to all registers"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(LockAll::Enable) + } +} +impl R { + #[doc = "Bits 0:3 - Controls write access to the security registers"] + #[inline(always)] + pub fn lock_all(&self) -> LockAllR { + LockAllR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controls write access to the security registers"] + #[inline(always)] + pub fn lock_all(&mut self) -> LockAllW { + LockAllW::new(self, 0) + } +} +#[doc = "Control Write Access to Security\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_lock_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_lock_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DebugLockEnSpec; +impl crate::RegisterSpec for DebugLockEnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_lock_en::R`](R) reader structure"] +impl crate::Readable for DebugLockEnSpec {} +#[doc = "`write(|w| ..)` method takes [`debug_lock_en::W`](W) writer structure"] +impl crate::Writable for DebugLockEnSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DEBUG_LOCK_EN to value 0x0a"] +impl crate::Resettable for DebugLockEnSpec { + const RESET_VALUE: u32 = 0x0a; +} diff --git a/mcxa276-pac/src/syscon/device_id0.rs b/mcxa276-pac/src/syscon/device_id0.rs new file mode 100644 index 000000000..5206a8cae --- /dev/null +++ b/mcxa276-pac/src/syscon/device_id0.rs @@ -0,0 +1,297 @@ +#[doc = "Register `DEVICE_ID0` reader"] +pub type R = crate::R; +#[doc = "Indicates the device's ram size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RamSize { + #[doc = "0: 8KB."] + Size8kb = 0, + #[doc = "1: 16KB."] + Size16kb = 1, + #[doc = "2: 32KB."] + Size32kb = 2, + #[doc = "3: 64KB."] + Size64kb = 3, + #[doc = "4: 96KB."] + Size96kb = 4, + #[doc = "5: 128KB."] + Size128kb = 5, + #[doc = "6: 160KB."] + Size160kb = 6, + #[doc = "7: 192KB."] + Size192kb = 7, + #[doc = "8: 256KB."] + Size256kb = 8, + #[doc = "9: 288KB."] + Size288kb = 9, + #[doc = "10: 352KB."] + Size352kb = 10, + #[doc = "11: 512KB."] + Size512kb = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RamSize) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RamSize { + type Ux = u8; +} +impl crate::IsEnum for RamSize {} +#[doc = "Field `RAM_SIZE` reader - Indicates the device's ram size"] +pub type RamSizeR = crate::FieldReader; +impl RamSizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(RamSize::Size8kb), + 1 => Some(RamSize::Size16kb), + 2 => Some(RamSize::Size32kb), + 3 => Some(RamSize::Size64kb), + 4 => Some(RamSize::Size96kb), + 5 => Some(RamSize::Size128kb), + 6 => Some(RamSize::Size160kb), + 7 => Some(RamSize::Size192kb), + 8 => Some(RamSize::Size256kb), + 9 => Some(RamSize::Size288kb), + 10 => Some(RamSize::Size352kb), + 11 => Some(RamSize::Size512kb), + _ => None, + } + } + #[doc = "8KB."] + #[inline(always)] + pub fn is_size_8kb(&self) -> bool { + *self == RamSize::Size8kb + } + #[doc = "16KB."] + #[inline(always)] + pub fn is_size_16kb(&self) -> bool { + *self == RamSize::Size16kb + } + #[doc = "32KB."] + #[inline(always)] + pub fn is_size_32kb(&self) -> bool { + *self == RamSize::Size32kb + } + #[doc = "64KB."] + #[inline(always)] + pub fn is_size_64kb(&self) -> bool { + *self == RamSize::Size64kb + } + #[doc = "96KB."] + #[inline(always)] + pub fn is_size_96kb(&self) -> bool { + *self == RamSize::Size96kb + } + #[doc = "128KB."] + #[inline(always)] + pub fn is_size_128kb(&self) -> bool { + *self == RamSize::Size128kb + } + #[doc = "160KB."] + #[inline(always)] + pub fn is_size_160kb(&self) -> bool { + *self == RamSize::Size160kb + } + #[doc = "192KB."] + #[inline(always)] + pub fn is_size_192kb(&self) -> bool { + *self == RamSize::Size192kb + } + #[doc = "256KB."] + #[inline(always)] + pub fn is_size_256kb(&self) -> bool { + *self == RamSize::Size256kb + } + #[doc = "288KB."] + #[inline(always)] + pub fn is_size_288kb(&self) -> bool { + *self == RamSize::Size288kb + } + #[doc = "352KB."] + #[inline(always)] + pub fn is_size_352kb(&self) -> bool { + *self == RamSize::Size352kb + } + #[doc = "512KB."] + #[inline(always)] + pub fn is_size_512kb(&self) -> bool { + *self == RamSize::Size512kb + } +} +#[doc = "Indicates the device's flash size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FlashSize { + #[doc = "0: 32KB."] + Size32kb = 0, + #[doc = "1: 64KB."] + Size64kb = 1, + #[doc = "2: 128KB."] + Size128kb = 2, + #[doc = "3: 256KB."] + Size256kb = 3, + #[doc = "4: 512KB."] + Size512kb = 4, + #[doc = "5: 768KB."] + Size768kb = 5, + #[doc = "6: 1MB."] + Size1mb = 6, + #[doc = "7: 1.5MB."] + Size1p5mb = 7, + #[doc = "8: 2MB."] + Size2mb = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FlashSize) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FlashSize { + type Ux = u8; +} +impl crate::IsEnum for FlashSize {} +#[doc = "Field `FLASH_SIZE` reader - Indicates the device's flash size"] +pub type FlashSizeR = crate::FieldReader; +impl FlashSizeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(FlashSize::Size32kb), + 1 => Some(FlashSize::Size64kb), + 2 => Some(FlashSize::Size128kb), + 3 => Some(FlashSize::Size256kb), + 4 => Some(FlashSize::Size512kb), + 5 => Some(FlashSize::Size768kb), + 6 => Some(FlashSize::Size1mb), + 7 => Some(FlashSize::Size1p5mb), + 8 => Some(FlashSize::Size2mb), + _ => None, + } + } + #[doc = "32KB."] + #[inline(always)] + pub fn is_size_32kb(&self) -> bool { + *self == FlashSize::Size32kb + } + #[doc = "64KB."] + #[inline(always)] + pub fn is_size_64kb(&self) -> bool { + *self == FlashSize::Size64kb + } + #[doc = "128KB."] + #[inline(always)] + pub fn is_size_128kb(&self) -> bool { + *self == FlashSize::Size128kb + } + #[doc = "256KB."] + #[inline(always)] + pub fn is_size_256kb(&self) -> bool { + *self == FlashSize::Size256kb + } + #[doc = "512KB."] + #[inline(always)] + pub fn is_size_512kb(&self) -> bool { + *self == FlashSize::Size512kb + } + #[doc = "768KB."] + #[inline(always)] + pub fn is_size_768kb(&self) -> bool { + *self == FlashSize::Size768kb + } + #[doc = "1MB."] + #[inline(always)] + pub fn is_size_1mb(&self) -> bool { + *self == FlashSize::Size1mb + } + #[doc = "1.5MB."] + #[inline(always)] + pub fn is_size_1p5mb(&self) -> bool { + *self == FlashSize::Size1p5mb + } + #[doc = "2MB."] + #[inline(always)] + pub fn is_size_2mb(&self) -> bool { + *self == FlashSize::Size2mb + } +} +#[doc = "Field `ROM_REV_MINOR` reader - Indicates the device's ROM revision"] +pub type RomRevMinorR = crate::FieldReader; +#[doc = "no description available\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Security { + #[doc = "5: Secure version."] + NonSec = 5, + #[doc = "10: Non secure version."] + Security10 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Security) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Security { + type Ux = u8; +} +impl crate::IsEnum for Security {} +#[doc = "Field `SECURITY` reader - no description available"] +pub type SecurityR = crate::FieldReader; +impl SecurityR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 5 => Some(Security::NonSec), + 10 => Some(Security::Security10), + _ => None, + } + } + #[doc = "Secure version."] + #[inline(always)] + pub fn is_non_sec(&self) -> bool { + *self == Security::NonSec + } + #[doc = "Non secure version."] + #[inline(always)] + pub fn is_security_10(&self) -> bool { + *self == Security::Security10 + } +} +impl R { + #[doc = "Bits 0:3 - Indicates the device's ram size"] + #[inline(always)] + pub fn ram_size(&self) -> RamSizeR { + RamSizeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates the device's flash size"] + #[inline(always)] + pub fn flash_size(&self) -> FlashSizeR { + FlashSizeR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Indicates the device's ROM revision"] + #[inline(always)] + pub fn rom_rev_minor(&self) -> RomRevMinorR { + RomRevMinorR::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - no description available"] + #[inline(always)] + pub fn security(&self) -> SecurityR { + SecurityR::new(((self.bits >> 24) & 0x0f) as u8) + } +} +#[doc = "Device ID\n\nYou can [`read`](crate::Reg::read) this register and get [`device_id0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DeviceId0Spec; +impl crate::RegisterSpec for DeviceId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`device_id0::R`](R) reader structure"] +impl crate::Readable for DeviceId0Spec {} +#[doc = "`reset()` method sets DEVICE_ID0 to value 0"] +impl crate::Resettable for DeviceId0Spec {} diff --git a/mcxa276-pac/src/syscon/device_type.rs b/mcxa276-pac/src/syscon/device_type.rs new file mode 100644 index 000000000..45620eb0a --- /dev/null +++ b/mcxa276-pac/src/syscon/device_type.rs @@ -0,0 +1,157 @@ +#[doc = "Register `DEVICE_TYPE` reader"] +pub type R = crate::R; +#[doc = "Field `DEVICE_TYPE_NUM` reader - Indicates the device part number"] +pub type DeviceTypeNumR = crate::FieldReader; +#[doc = "Indicates the device type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DeviceTypeSec { + #[doc = "0: Non Secure"] + NonSec = 0, + #[doc = "1: Secure"] + Sec = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DeviceTypeSec) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DEVICE_TYPE_SEC` reader - Indicates the device type"] +pub type DeviceTypeSecR = crate::BitReader; +impl DeviceTypeSecR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DeviceTypeSec { + match self.bits { + false => DeviceTypeSec::NonSec, + true => DeviceTypeSec::Sec, + } + } + #[doc = "Non Secure"] + #[inline(always)] + pub fn is_non_sec(&self) -> bool { + *self == DeviceTypeSec::NonSec + } + #[doc = "Secure"] + #[inline(always)] + pub fn is_sec(&self) -> bool { + *self == DeviceTypeSec::Sec + } +} +#[doc = "Indicates the device's package type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DeviceTypePkg { + #[doc = "0: HLQFP"] + Hlqfp = 0, + #[doc = "1: HTQFP"] + Htqfp = 1, + #[doc = "2: BGA"] + Bga = 2, + #[doc = "3: HDQFP"] + Hdqfp = 3, + #[doc = "4: QFN"] + Qfn = 4, + #[doc = "5: CSP"] + Csp = 5, + #[doc = "6: LQFP"] + Lqfp = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DeviceTypePkg) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DeviceTypePkg { + type Ux = u8; +} +impl crate::IsEnum for DeviceTypePkg {} +#[doc = "Field `DEVICE_TYPE_PKG` reader - Indicates the device's package type"] +pub type DeviceTypePkgR = crate::FieldReader; +impl DeviceTypePkgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DeviceTypePkg::Hlqfp), + 1 => Some(DeviceTypePkg::Htqfp), + 2 => Some(DeviceTypePkg::Bga), + 3 => Some(DeviceTypePkg::Hdqfp), + 4 => Some(DeviceTypePkg::Qfn), + 5 => Some(DeviceTypePkg::Csp), + 6 => Some(DeviceTypePkg::Lqfp), + _ => None, + } + } + #[doc = "HLQFP"] + #[inline(always)] + pub fn is_hlqfp(&self) -> bool { + *self == DeviceTypePkg::Hlqfp + } + #[doc = "HTQFP"] + #[inline(always)] + pub fn is_htqfp(&self) -> bool { + *self == DeviceTypePkg::Htqfp + } + #[doc = "BGA"] + #[inline(always)] + pub fn is_bga(&self) -> bool { + *self == DeviceTypePkg::Bga + } + #[doc = "HDQFP"] + #[inline(always)] + pub fn is_hdqfp(&self) -> bool { + *self == DeviceTypePkg::Hdqfp + } + #[doc = "QFN"] + #[inline(always)] + pub fn is_qfn(&self) -> bool { + *self == DeviceTypePkg::Qfn + } + #[doc = "CSP"] + #[inline(always)] + pub fn is_csp(&self) -> bool { + *self == DeviceTypePkg::Csp + } + #[doc = "LQFP"] + #[inline(always)] + pub fn is_lqfp(&self) -> bool { + *self == DeviceTypePkg::Lqfp + } +} +#[doc = "Field `DEVICE_TYPE_PIN` reader - Indicates the device's pin number"] +pub type DeviceTypePinR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Indicates the device part number"] + #[inline(always)] + pub fn device_type_num(&self) -> DeviceTypeNumR { + DeviceTypeNumR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Indicates the device type"] + #[inline(always)] + pub fn device_type_sec(&self) -> DeviceTypeSecR { + DeviceTypeSecR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 20:23 - Indicates the device's package type"] + #[inline(always)] + pub fn device_type_pkg(&self) -> DeviceTypePkgR { + DeviceTypePkgR::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Indicates the device's pin number"] + #[inline(always)] + pub fn device_type_pin(&self) -> DeviceTypePinR { + DeviceTypePinR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Device Type\n\nYou can [`read`](crate::Reg::read) this register and get [`device_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DeviceTypeSpec; +impl crate::RegisterSpec for DeviceTypeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`device_type::R`](R) reader structure"] +impl crate::Readable for DeviceTypeSpec {} +#[doc = "`reset()` method sets DEVICE_TYPE to value 0x2000"] +impl crate::Resettable for DeviceTypeSpec { + const RESET_VALUE: u32 = 0x2000; +} diff --git a/mcxa276-pac/src/syscon/dieid.rs b/mcxa276-pac/src/syscon/dieid.rs new file mode 100644 index 000000000..a0121ae97 --- /dev/null +++ b/mcxa276-pac/src/syscon/dieid.rs @@ -0,0 +1,36 @@ +#[doc = "Register `DIEID` reader"] +pub type R = crate::R; +#[doc = "Field `MINOR_REVISION` reader - Chip minor revision"] +pub type MinorRevisionR = crate::FieldReader; +#[doc = "Field `MAJOR_REVISION` reader - Chip major revision"] +pub type MajorRevisionR = crate::FieldReader; +#[doc = "Field `MCO_NUM_IN_DIE_ID` reader - Chip number"] +pub type McoNumInDieIdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Chip minor revision"] + #[inline(always)] + pub fn minor_revision(&self) -> MinorRevisionR { + MinorRevisionR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Chip major revision"] + #[inline(always)] + pub fn major_revision(&self) -> MajorRevisionR { + MajorRevisionR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:27 - Chip number"] + #[inline(always)] + pub fn mco_num_in_die_id(&self) -> McoNumInDieIdR { + McoNumInDieIdR::new((self.bits >> 8) & 0x000f_ffff) + } +} +#[doc = "Chip Revision ID and Number\n\nYou can [`read`](crate::Reg::read) this register and get [`dieid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DieidSpec; +impl crate::RegisterSpec for DieidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dieid::R`](R) reader structure"] +impl crate::Readable for DieidSpec {} +#[doc = "`reset()` method sets DIEID to value 0x005d_c1a0"] +impl crate::Resettable for DieidSpec { + const RESET_VALUE: u32 = 0x005d_c1a0; +} diff --git a/mcxa276-pac/src/syscon/els_otp_lc_state.rs b/mcxa276-pac/src/syscon/els_otp_lc_state.rs new file mode 100644 index 000000000..35dd0361b --- /dev/null +++ b/mcxa276-pac/src/syscon/els_otp_lc_state.rs @@ -0,0 +1,20 @@ +#[doc = "Register `ELS_OTP_LC_STATE` reader"] +pub type R = crate::R; +#[doc = "Field `OTP_LC_STATE` reader - OTP life cycle state"] +pub type OtpLcStateR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - OTP life cycle state"] + #[inline(always)] + pub fn otp_lc_state(&self) -> OtpLcStateR { + OtpLcStateR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Life Cycle State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElsOtpLcStateSpec; +impl crate::RegisterSpec for ElsOtpLcStateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`els_otp_lc_state::R`](R) reader structure"] +impl crate::Readable for ElsOtpLcStateSpec {} +#[doc = "`reset()` method sets ELS_OTP_LC_STATE to value 0"] +impl crate::Resettable for ElsOtpLcStateSpec {} diff --git a/mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs b/mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs new file mode 100644 index 000000000..52d3b4323 --- /dev/null +++ b/mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs @@ -0,0 +1,20 @@ +#[doc = "Register `ELS_OTP_LC_STATE_DP` reader"] +pub type R = crate::R; +#[doc = "Field `OTP_LC_STATE_DP` reader - OTP life cycle state"] +pub type OtpLcStateDpR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - OTP life cycle state"] + #[inline(always)] + pub fn otp_lc_state_dp(&self) -> OtpLcStateDpR { + OtpLcStateDpR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Life Cycle State Register (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state_dp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElsOtpLcStateDpSpec; +impl crate::RegisterSpec for ElsOtpLcStateDpSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`els_otp_lc_state_dp::R`](R) reader structure"] +impl crate::Readable for ElsOtpLcStateDpSpec {} +#[doc = "`reset()` method sets ELS_OTP_LC_STATE_DP to value 0"] +impl crate::Resettable for ElsOtpLcStateDpSpec {} diff --git a/mcxa276-pac/src/syscon/els_udf.rs b/mcxa276-pac/src/syscon/els_udf.rs new file mode 100644 index 000000000..1f60f7f0b --- /dev/null +++ b/mcxa276-pac/src/syscon/els_udf.rs @@ -0,0 +1,231 @@ +#[doc = "Register `ELS_UDF` reader"] +pub type R = crate::R; +#[doc = "Register `ELS_UDF` writer"] +pub type W = crate::W; +#[doc = "UDF KEY Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum KeySel { + #[doc = "0: DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] + Duk0 = 0, + #[doc = "1: DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] + Duk1 = 1, + #[doc = "2: DeviceHSM"] + DeviceHsm = 2, + #[doc = "3: NXP_mRoT"] + NxpMRoT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KeySel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for KeySel { + type Ux = u8; +} +impl crate::IsEnum for KeySel {} +#[doc = "Field `KEY_SEL` reader - UDF KEY Select"] +pub type KeySelR = crate::FieldReader; +impl KeySelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> KeySel { + match self.bits { + 0 => KeySel::Duk0, + 1 => KeySel::Duk1, + 2 => KeySel::DeviceHsm, + 3 => KeySel::NxpMRoT, + _ => unreachable!(), + } + } + #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] + #[inline(always)] + pub fn is_duk_0(&self) -> bool { + *self == KeySel::Duk0 + } + #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] + #[inline(always)] + pub fn is_duk_1(&self) -> bool { + *self == KeySel::Duk1 + } + #[doc = "DeviceHSM"] + #[inline(always)] + pub fn is_device_hsm(&self) -> bool { + *self == KeySel::DeviceHsm + } + #[doc = "NXP_mRoT"] + #[inline(always)] + pub fn is_nxp_m_ro_t(&self) -> bool { + *self == KeySel::NxpMRoT + } +} +#[doc = "Field `KEY_SEL` writer - UDF KEY Select"] +pub type KeySelW<'a, REG> = crate::FieldWriter<'a, REG, 2, KeySel, crate::Safe>; +impl<'a, REG> KeySelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] + #[inline(always)] + pub fn duk_0(self) -> &'a mut crate::W { + self.variant(KeySel::Duk0) + } + #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] + #[inline(always)] + pub fn duk_1(self) -> &'a mut crate::W { + self.variant(KeySel::Duk1) + } + #[doc = "DeviceHSM"] + #[inline(always)] + pub fn device_hsm(self) -> &'a mut crate::W { + self.variant(KeySel::DeviceHsm) + } + #[doc = "NXP_mRoT"] + #[inline(always)] + pub fn nxp_m_ro_t(self) -> &'a mut crate::W { + self.variant(KeySel::NxpMRoT) + } +} +#[doc = "UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum UidHidden { + #[doc = "10: Enable the access of UID\\[127:0\\] register. All other value, disable the read/write of UID\\[127:0\\] register."] + UidHidden = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: UidHidden) -> Self { + variant as _ + } +} +impl crate::FieldSpec for UidHidden { + type Ux = u8; +} +impl crate::IsEnum for UidHidden {} +#[doc = "Field `UID_HIDDEN` reader - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] +pub type UidHiddenR = crate::FieldReader; +impl UidHiddenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 10 => Some(UidHidden::UidHidden), + _ => None, + } + } + #[doc = "Enable the access of UID\\[127:0\\] register. All other value, disable the read/write of UID\\[127:0\\] register."] + #[inline(always)] + pub fn is_uid_hidden(&self) -> bool { + *self == UidHidden::UidHidden + } +} +#[doc = "Field `UID_HIDDEN` writer - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] +pub type UidHiddenW<'a, REG> = crate::FieldWriter<'a, REG, 4, UidHidden>; +impl<'a, REG> UidHiddenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Enable the access of UID\\[127:0\\] register. All other value, disable the read/write of UID\\[127:0\\] register."] + #[inline(always)] + pub fn uid_hidden(self) -> &'a mut crate::W { + self.variant(UidHidden::UidHidden) + } +} +#[doc = "UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum UdfHidden { + #[doc = "10: Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus."] + UdfHidden = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: UdfHidden) -> Self { + variant as _ + } +} +impl crate::FieldSpec for UdfHidden { + type Ux = u8; +} +impl crate::IsEnum for UdfHidden {} +#[doc = "Field `UDF_HIDDEN` reader - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] +pub type UdfHiddenR = crate::FieldReader; +impl UdfHiddenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 10 => Some(UdfHidden::UdfHidden), + _ => None, + } + } + #[doc = "Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus."] + #[inline(always)] + pub fn is_udf_hidden(&self) -> bool { + *self == UdfHidden::UdfHidden + } +} +#[doc = "Field `UDF_HIDDEN` writer - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] +pub type UdfHiddenW<'a, REG> = crate::FieldWriter<'a, REG, 4, UdfHidden>; +impl<'a, REG> UdfHiddenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus."] + #[inline(always)] + pub fn udf_hidden(self) -> &'a mut crate::W { + self.variant(UdfHidden::UdfHidden) + } +} +impl R { + #[doc = "Bits 0:1 - UDF KEY Select"] + #[inline(always)] + pub fn key_sel(&self) -> KeySelR { + KeySelR::new((self.bits & 3) as u8) + } + #[doc = "Bits 24:27 - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] + #[inline(always)] + pub fn uid_hidden(&self) -> UidHiddenR { + UidHiddenR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] + #[inline(always)] + pub fn udf_hidden(&self) -> UdfHiddenR { + UdfHiddenR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - UDF KEY Select"] + #[inline(always)] + pub fn key_sel(&mut self) -> KeySelW { + KeySelW::new(self, 0) + } + #[doc = "Bits 24:27 - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] + #[inline(always)] + pub fn uid_hidden(&mut self) -> UidHiddenW { + UidHiddenW::new(self, 24) + } + #[doc = "Bits 28:31 - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] + #[inline(always)] + pub fn udf_hidden(&mut self) -> UdfHiddenW { + UdfHiddenW::new(self, 28) + } +} +#[doc = "UDF Control\n\nYou can [`read`](crate::Reg::read) this register and get [`els_udf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_udf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElsUdfSpec; +impl crate::RegisterSpec for ElsUdfSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`els_udf::R`](R) reader structure"] +impl crate::Readable for ElsUdfSpec {} +#[doc = "`write(|w| ..)` method takes [`els_udf::W`](W) writer structure"] +impl crate::Writable for ElsUdfSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ELS_UDF to value 0"] +impl crate::Resettable for ElsUdfSpec {} diff --git a/mcxa276-pac/src/syscon/els_uid.rs b/mcxa276-pac/src/syscon/els_uid.rs new file mode 100644 index 000000000..9e12d0dff --- /dev/null +++ b/mcxa276-pac/src/syscon/els_uid.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ELS_UID[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `ELS_UID[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `UID0` reader - UID"] +pub type Uid0R = crate::FieldReader; +#[doc = "Field `UID0` writer - UID"] +pub type Uid0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - UID"] + #[inline(always)] + pub fn uid0(&self) -> Uid0R { + Uid0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - UID"] + #[inline(always)] + pub fn uid0(&mut self) -> Uid0W { + Uid0W::new(self, 0) + } +} +#[doc = "Device UID n\n\nYou can [`read`](crate::Reg::read) this register and get [`els_uid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_uid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ElsUidSpec; +impl crate::RegisterSpec for ElsUidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`els_uid::R`](R) reader structure"] +impl crate::Readable for ElsUidSpec {} +#[doc = "`write(|w| ..)` method takes [`els_uid::W`](W) writer structure"] +impl crate::Writable for ElsUidSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ELS_UID[%s] to value 0"] +impl crate::Resettable for ElsUidSpec {} diff --git a/mcxa276-pac/src/syscon/frohfdiv.rs b/mcxa276-pac/src/syscon/frohfdiv.rs new file mode 100644 index 000000000..8e90ba00f --- /dev/null +++ b/mcxa276-pac/src/syscon/frohfdiv.rs @@ -0,0 +1,204 @@ +#[doc = "Register `FROHFDIV` reader"] +pub type R = crate::R; +#[doc = "Register `FROHFDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Clock divider value"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Clock divider value"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Resets the divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider is not reset"] + Released = 0, + #[doc = "1: Divider is reset"] + Asserted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` reader - Resets the divider counter"] +pub type ResetR = crate::BitReader; +impl ResetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reset { + match self.bits { + false => Reset::Released, + true => Reset::Asserted, + } + } + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn is_released(&self) -> bool { + *self == Reset::Released + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn is_asserted(&self) -> bool { + *self == Reset::Asserted + } +} +#[doc = "Field `RESET` writer - Resets the divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn released(self) -> &'a mut crate::W { + self.variant(Reset::Released) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn asserted(self) -> &'a mut crate::W { + self.variant(Reset::Asserted) + } +} +#[doc = "Halts the divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + Run = 0, + #[doc = "1: Divider clock is stopped"] + Halt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halts the divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::Run, + true => Halt::Halt, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == Halt::Run + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_halt(&self) -> bool { + *self == Halt::Halt + } +} +#[doc = "Field `HALT` writer - Halts the divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn run(self) -> &'a mut crate::W { + self.variant(Halt::Run) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn halt(self) -> &'a mut crate::W { + self.variant(Halt::Halt) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + Stable = 0, + #[doc = "1: Clock frequency is not stable"] + Ongoing = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::Stable, + true => Unstab::Ongoing, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_stable(&self) -> bool { + *self == Unstab::Stable + } + #[doc = "Clock frequency is not stable"] + #[inline(always)] + pub fn is_ongoing(&self) -> bool { + *self == Unstab::Ongoing + } +} +impl R { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&self) -> ResetR { + ResetR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "FRO_HF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frohfdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frohfdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrohfdivSpec; +impl crate::RegisterSpec for FrohfdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`frohfdiv::R`](R) reader structure"] +impl crate::Readable for FrohfdivSpec {} +#[doc = "`write(|w| ..)` method takes [`frohfdiv::W`](W) writer structure"] +impl crate::Writable for FrohfdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FROHFDIV to value 0x4000_0000"] +impl crate::Resettable for FrohfdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/syscon/frolfdiv.rs b/mcxa276-pac/src/syscon/frolfdiv.rs new file mode 100644 index 000000000..d132681f0 --- /dev/null +++ b/mcxa276-pac/src/syscon/frolfdiv.rs @@ -0,0 +1,204 @@ +#[doc = "Register `FROLFDIV` reader"] +pub type R = crate::R; +#[doc = "Register `FROLFDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Clock divider value"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Clock divider value"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Resets the divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider is not reset"] + Released = 0, + #[doc = "1: Divider is reset"] + Asserted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` reader - Resets the divider counter"] +pub type ResetR = crate::BitReader; +impl ResetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reset { + match self.bits { + false => Reset::Released, + true => Reset::Asserted, + } + } + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn is_released(&self) -> bool { + *self == Reset::Released + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn is_asserted(&self) -> bool { + *self == Reset::Asserted + } +} +#[doc = "Field `RESET` writer - Resets the divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn released(self) -> &'a mut crate::W { + self.variant(Reset::Released) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn asserted(self) -> &'a mut crate::W { + self.variant(Reset::Asserted) + } +} +#[doc = "Halts the divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + Run = 0, + #[doc = "1: Divider clock is stopped"] + Halt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halts the divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::Run, + true => Halt::Halt, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == Halt::Run + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_halt(&self) -> bool { + *self == Halt::Halt + } +} +#[doc = "Field `HALT` writer - Halts the divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn run(self) -> &'a mut crate::W { + self.variant(Halt::Run) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn halt(self) -> &'a mut crate::W { + self.variant(Halt::Halt) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + Stable = 0, + #[doc = "1: Clock frequency is not stable"] + Ongoing = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::Stable, + true => Unstab::Ongoing, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_stable(&self) -> bool { + *self == Unstab::Stable + } + #[doc = "Clock frequency is not stable"] + #[inline(always)] + pub fn is_ongoing(&self) -> bool { + *self == Unstab::Ongoing + } +} +impl R { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&self) -> ResetR { + ResetR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "FRO_LF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frolfdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolfdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrolfdivSpec; +impl crate::RegisterSpec for FrolfdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`frolfdiv::R`](R) reader structure"] +impl crate::Readable for FrolfdivSpec {} +#[doc = "`write(|w| ..)` method takes [`frolfdiv::W`](W) writer structure"] +impl crate::Writable for FrolfdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FROLFDIV to value 0x4000_0000"] +impl crate::Resettable for FrolfdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/syscon/gray_code_lsb.rs b/mcxa276-pac/src/syscon/gray_code_lsb.rs new file mode 100644 index 000000000..631de5f18 --- /dev/null +++ b/mcxa276-pac/src/syscon/gray_code_lsb.rs @@ -0,0 +1,35 @@ +#[doc = "Register `GRAY_CODE_LSB` reader"] +pub type R = crate::R; +#[doc = "Register `GRAY_CODE_LSB` writer"] +pub type W = crate::W; +#[doc = "Field `code_gray_31_0` reader - Gray code \\[31:0\\]"] +pub type CodeGray31_0R = crate::FieldReader; +#[doc = "Field `code_gray_31_0` writer - Gray code \\[31:0\\]"] +pub type CodeGray31_0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Gray code \\[31:0\\]"] + #[inline(always)] + pub fn code_gray_31_0(&self) -> CodeGray31_0R { + CodeGray31_0R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Gray code \\[31:0\\]"] + #[inline(always)] + pub fn code_gray_31_0(&mut self) -> CodeGray31_0W { + CodeGray31_0W::new(self, 0) + } +} +#[doc = "Gray to Binary Converter Gray Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GrayCodeLsbSpec; +impl crate::RegisterSpec for GrayCodeLsbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gray_code_lsb::R`](R) reader structure"] +impl crate::Readable for GrayCodeLsbSpec {} +#[doc = "`write(|w| ..)` method takes [`gray_code_lsb::W`](W) writer structure"] +impl crate::Writable for GrayCodeLsbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GRAY_CODE_LSB to value 0"] +impl crate::Resettable for GrayCodeLsbSpec {} diff --git a/mcxa276-pac/src/syscon/gray_code_msb.rs b/mcxa276-pac/src/syscon/gray_code_msb.rs new file mode 100644 index 000000000..e916cd756 --- /dev/null +++ b/mcxa276-pac/src/syscon/gray_code_msb.rs @@ -0,0 +1,35 @@ +#[doc = "Register `GRAY_CODE_MSB` reader"] +pub type R = crate::R; +#[doc = "Register `GRAY_CODE_MSB` writer"] +pub type W = crate::W; +#[doc = "Field `code_gray_41_32` reader - Gray code \\[41:32\\]"] +pub type CodeGray41_32R = crate::FieldReader; +#[doc = "Field `code_gray_41_32` writer - Gray code \\[41:32\\]"] +pub type CodeGray41_32W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Gray code \\[41:32\\]"] + #[inline(always)] + pub fn code_gray_41_32(&self) -> CodeGray41_32R { + CodeGray41_32R::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Gray code \\[41:32\\]"] + #[inline(always)] + pub fn code_gray_41_32(&mut self) -> CodeGray41_32W { + CodeGray41_32W::new(self, 0) + } +} +#[doc = "Gray to Binary Converter Gray Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GrayCodeMsbSpec; +impl crate::RegisterSpec for GrayCodeMsbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gray_code_msb::R`](R) reader structure"] +impl crate::Readable for GrayCodeMsbSpec {} +#[doc = "`write(|w| ..)` method takes [`gray_code_msb::W`](W) writer structure"] +impl crate::Writable for GrayCodeMsbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GRAY_CODE_MSB to value 0"] +impl crate::Resettable for GrayCodeMsbSpec {} diff --git a/mcxa276-pac/src/syscon/jtag_id.rs b/mcxa276-pac/src/syscon/jtag_id.rs new file mode 100644 index 000000000..9e1d3d410 --- /dev/null +++ b/mcxa276-pac/src/syscon/jtag_id.rs @@ -0,0 +1,22 @@ +#[doc = "Register `JTAG_ID` reader"] +pub type R = crate::R; +#[doc = "Field `JTAG_ID` reader - Indicates the device ID"] +pub type JtagIdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Indicates the device ID"] + #[inline(always)] + pub fn jtag_id(&self) -> JtagIdR { + JtagIdR::new(self.bits) + } +} +#[doc = "JTAG Chip ID\n\nYou can [`read`](crate::Reg::read) this register and get [`jtag_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct JtagIdSpec; +impl crate::RegisterSpec for JtagIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`jtag_id::R`](R) reader structure"] +impl crate::Readable for JtagIdSpec {} +#[doc = "`reset()` method sets JTAG_ID to value 0x0726_802b"] +impl crate::Resettable for JtagIdSpec { + const RESET_VALUE: u32 = 0x0726_802b; +} diff --git a/mcxa276-pac/src/syscon/lpcac_ctrl.rs b/mcxa276-pac/src/syscon/lpcac_ctrl.rs new file mode 100644 index 000000000..b58299507 --- /dev/null +++ b/mcxa276-pac/src/syscon/lpcac_ctrl.rs @@ -0,0 +1,464 @@ +#[doc = "Register `LPCAC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LPCAC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Disables/enables the cache function.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DisLpcac { + #[doc = "0: Enabled"] + Enable = 0, + #[doc = "1: Disabled"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DisLpcac) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIS_LPCAC` reader - Disables/enables the cache function."] +pub type DisLpcacR = crate::BitReader; +impl DisLpcacR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DisLpcac { + match self.bits { + false => DisLpcac::Enable, + true => DisLpcac::Disable, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DisLpcac::Enable + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DisLpcac::Disable + } +} +#[doc = "Field `DIS_LPCAC` writer - Disables/enables the cache function."] +pub type DisLpcacW<'a, REG> = crate::BitWriter<'a, REG, DisLpcac>; +impl<'a, REG> DisLpcacW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DisLpcac::Enable) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DisLpcac::Disable) + } +} +#[doc = "Clears the cache function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ClrLpcac { + #[doc = "0: Unclears the cache"] + Enable = 0, + #[doc = "1: Clears the cache"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ClrLpcac) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLR_LPCAC` reader - Clears the cache function."] +pub type ClrLpcacR = crate::BitReader; +impl ClrLpcacR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ClrLpcac { + match self.bits { + false => ClrLpcac::Enable, + true => ClrLpcac::Disable, + } + } + #[doc = "Unclears the cache"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == ClrLpcac::Enable + } + #[doc = "Clears the cache"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == ClrLpcac::Disable + } +} +#[doc = "Field `CLR_LPCAC` writer - Clears the cache function."] +pub type ClrLpcacW<'a, REG> = crate::BitWriter<'a, REG, ClrLpcac>; +impl<'a, REG> ClrLpcacW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Unclears the cache"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ClrLpcac::Enable) + } + #[doc = "Clears the cache"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ClrLpcac::Disable) + } +} +#[doc = "Forces no allocation.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FrcNoAlloc { + #[doc = "0: Forces allocation"] + Enable = 0, + #[doc = "1: Forces no allocation"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FrcNoAlloc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRC_NO_ALLOC` reader - Forces no allocation."] +pub type FrcNoAllocR = crate::BitReader; +impl FrcNoAllocR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FrcNoAlloc { + match self.bits { + false => FrcNoAlloc::Enable, + true => FrcNoAlloc::Disable, + } + } + #[doc = "Forces allocation"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == FrcNoAlloc::Enable + } + #[doc = "Forces no allocation"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == FrcNoAlloc::Disable + } +} +#[doc = "Field `FRC_NO_ALLOC` writer - Forces no allocation."] +pub type FrcNoAllocW<'a, REG> = crate::BitWriter<'a, REG, FrcNoAlloc>; +impl<'a, REG> FrcNoAllocW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Forces allocation"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(FrcNoAlloc::Enable) + } + #[doc = "Forces no allocation"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(FrcNoAlloc::Disable) + } +} +#[doc = "Disable LPCAC Write Through Buffer.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DisLpcacWtbf { + #[doc = "0: Enables write through buffer"] + Disable = 0, + #[doc = "1: Disables write through buffer"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DisLpcacWtbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIS_LPCAC_WTBF` reader - Disable LPCAC Write Through Buffer."] +pub type DisLpcacWtbfR = crate::BitReader; +impl DisLpcacWtbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DisLpcacWtbf { + match self.bits { + false => DisLpcacWtbf::Disable, + true => DisLpcacWtbf::Enable, + } + } + #[doc = "Enables write through buffer"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DisLpcacWtbf::Disable + } + #[doc = "Disables write through buffer"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DisLpcacWtbf::Enable + } +} +#[doc = "Field `DIS_LPCAC_WTBF` writer - Disable LPCAC Write Through Buffer."] +pub type DisLpcacWtbfW<'a, REG> = crate::BitWriter<'a, REG, DisLpcacWtbf>; +impl<'a, REG> DisLpcacWtbfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables write through buffer"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DisLpcacWtbf::Disable) + } + #[doc = "Disables write through buffer"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DisLpcacWtbf::Enable) + } +} +#[doc = "Limit LPCAC Write Through Buffer.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LimLpcacWtbf { + #[doc = "0: Write buffer enabled when transaction is bufferable."] + Disable = 0, + #[doc = "1: Write buffer enabled when transaction is cacheable and bufferable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LimLpcacWtbf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LIM_LPCAC_WTBF` reader - Limit LPCAC Write Through Buffer."] +pub type LimLpcacWtbfR = crate::BitReader; +impl LimLpcacWtbfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LimLpcacWtbf { + match self.bits { + false => LimLpcacWtbf::Disable, + true => LimLpcacWtbf::Enable, + } + } + #[doc = "Write buffer enabled when transaction is bufferable."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == LimLpcacWtbf::Disable + } + #[doc = "Write buffer enabled when transaction is cacheable and bufferable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == LimLpcacWtbf::Enable + } +} +#[doc = "Field `LIM_LPCAC_WTBF` writer - Limit LPCAC Write Through Buffer."] +pub type LimLpcacWtbfW<'a, REG> = crate::BitWriter<'a, REG, LimLpcacWtbf>; +impl<'a, REG> LimLpcacWtbfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Write buffer enabled when transaction is bufferable."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(LimLpcacWtbf::Disable) + } + #[doc = "Write buffer enabled when transaction is cacheable and bufferable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(LimLpcacWtbf::Enable) + } +} +#[doc = "LPCAC XOM(eXecute-Only-Memory) attribute control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LpcacXom { + #[doc = "0: Disabled."] + Disable = 0, + #[doc = "1: Enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LpcacXom) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPCAC_XOM` reader - LPCAC XOM(eXecute-Only-Memory) attribute control"] +pub type LpcacXomR = crate::BitReader; +impl LpcacXomR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LpcacXom { + match self.bits { + false => LpcacXom::Disable, + true => LpcacXom::Enable, + } + } + #[doc = "Disabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == LpcacXom::Disable + } + #[doc = "Enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == LpcacXom::Enable + } +} +#[doc = "Field `LPCAC_XOM` writer - LPCAC XOM(eXecute-Only-Memory) attribute control"] +pub type LpcacXomW<'a, REG> = crate::BitWriter<'a, REG, LpcacXom>; +impl<'a, REG> LpcacXomW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(LpcacXom::Disable) + } + #[doc = "Enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(LpcacXom::Enable) + } +} +#[doc = "Request LPCAC memories.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LpcacMemReq { + #[doc = "0: Configure shared memories RAMX1 as general memories."] + Disable = 0, + #[doc = "1: Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LpcacMemReq) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LPCAC_MEM_REQ` reader - Request LPCAC memories."] +pub type LpcacMemReqR = crate::BitReader; +impl LpcacMemReqR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LpcacMemReq { + match self.bits { + false => LpcacMemReq::Disable, + true => LpcacMemReq::Enable, + } + } + #[doc = "Configure shared memories RAMX1 as general memories."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == LpcacMemReq::Disable + } + #[doc = "Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == LpcacMemReq::Enable + } +} +#[doc = "Field `LPCAC_MEM_REQ` writer - Request LPCAC memories."] +pub type LpcacMemReqW<'a, REG> = crate::BitWriter<'a, REG, LpcacMemReq>; +impl<'a, REG> LpcacMemReqW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Configure shared memories RAMX1 as general memories."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(LpcacMemReq::Disable) + } + #[doc = "Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(LpcacMemReq::Enable) + } +} +impl R { + #[doc = "Bit 0 - Disables/enables the cache function."] + #[inline(always)] + pub fn dis_lpcac(&self) -> DisLpcacR { + DisLpcacR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the cache function."] + #[inline(always)] + pub fn clr_lpcac(&self) -> ClrLpcacR { + ClrLpcacR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Forces no allocation."] + #[inline(always)] + pub fn frc_no_alloc(&self) -> FrcNoAllocR { + FrcNoAllocR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Disable LPCAC Write Through Buffer."] + #[inline(always)] + pub fn dis_lpcac_wtbf(&self) -> DisLpcacWtbfR { + DisLpcacWtbfR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Limit LPCAC Write Through Buffer."] + #[inline(always)] + pub fn lim_lpcac_wtbf(&self) -> LimLpcacWtbfR { + LimLpcacWtbfR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - LPCAC XOM(eXecute-Only-Memory) attribute control"] + #[inline(always)] + pub fn lpcac_xom(&self) -> LpcacXomR { + LpcacXomR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Request LPCAC memories."] + #[inline(always)] + pub fn lpcac_mem_req(&self) -> LpcacMemReqR { + LpcacMemReqR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disables/enables the cache function."] + #[inline(always)] + pub fn dis_lpcac(&mut self) -> DisLpcacW { + DisLpcacW::new(self, 0) + } + #[doc = "Bit 1 - Clears the cache function."] + #[inline(always)] + pub fn clr_lpcac(&mut self) -> ClrLpcacW { + ClrLpcacW::new(self, 1) + } + #[doc = "Bit 2 - Forces no allocation."] + #[inline(always)] + pub fn frc_no_alloc(&mut self) -> FrcNoAllocW { + FrcNoAllocW::new(self, 2) + } + #[doc = "Bit 4 - Disable LPCAC Write Through Buffer."] + #[inline(always)] + pub fn dis_lpcac_wtbf(&mut self) -> DisLpcacWtbfW { + DisLpcacWtbfW::new(self, 4) + } + #[doc = "Bit 5 - Limit LPCAC Write Through Buffer."] + #[inline(always)] + pub fn lim_lpcac_wtbf(&mut self) -> LimLpcacWtbfW { + LimLpcacWtbfW::new(self, 5) + } + #[doc = "Bit 7 - LPCAC XOM(eXecute-Only-Memory) attribute control"] + #[inline(always)] + pub fn lpcac_xom(&mut self) -> LpcacXomW { + LpcacXomW::new(self, 7) + } + #[doc = "Bit 8 - Request LPCAC memories."] + #[inline(always)] + pub fn lpcac_mem_req(&mut self) -> LpcacMemReqW { + LpcacMemReqW::new(self, 8) + } +} +#[doc = "LPCAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`lpcac_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcac_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LpcacCtrlSpec; +impl crate::RegisterSpec for LpcacCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpcac_ctrl::R`](R) reader structure"] +impl crate::Readable for LpcacCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`lpcac_ctrl::W`](W) writer structure"] +impl crate::Writable for LpcacCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LPCAC_CTRL to value 0x31"] +impl crate::Resettable for LpcacCtrlSpec { + const RESET_VALUE: u32 = 0x31; +} diff --git a/mcxa276-pac/src/syscon/msfcfg.rs b/mcxa276-pac/src/syscon/msfcfg.rs new file mode 100644 index 000000000..486a350cf --- /dev/null +++ b/mcxa276-pac/src/syscon/msfcfg.rs @@ -0,0 +1,336 @@ +#[doc = "Register `MSFCFG` reader"] +pub type R = crate::R; +#[doc = "Register `MSFCFG` writer"] +pub type W = crate::W; +#[doc = "user IFR sector 0 erase control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IfrEraseDis0 { + #[doc = "0: Enable IFR sector erase."] + Enable = 0, + #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IfrEraseDis0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IFR_ERASE_DIS0` reader - user IFR sector 0 erase control"] +pub type IfrEraseDis0R = crate::BitReader; +impl IfrEraseDis0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IfrEraseDis0 { + match self.bits { + false => IfrEraseDis0::Enable, + true => IfrEraseDis0::Disable, + } + } + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IfrEraseDis0::Enable + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IfrEraseDis0::Disable + } +} +#[doc = "Field `IFR_ERASE_DIS0` writer - user IFR sector 0 erase control"] +pub type IfrEraseDis0W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis0>; +impl<'a, REG> IfrEraseDis0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis0::Enable) + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis0::Disable) + } +} +#[doc = "user IFR sector 1 erase control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IfrEraseDis1 { + #[doc = "0: Enable IFR sector erase."] + Enable = 0, + #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IfrEraseDis1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IFR_ERASE_DIS1` reader - user IFR sector 1 erase control"] +pub type IfrEraseDis1R = crate::BitReader; +impl IfrEraseDis1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IfrEraseDis1 { + match self.bits { + false => IfrEraseDis1::Enable, + true => IfrEraseDis1::Disable, + } + } + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IfrEraseDis1::Enable + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IfrEraseDis1::Disable + } +} +#[doc = "Field `IFR_ERASE_DIS1` writer - user IFR sector 1 erase control"] +pub type IfrEraseDis1W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis1>; +impl<'a, REG> IfrEraseDis1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis1::Enable) + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis1::Disable) + } +} +#[doc = "user IFR sector 2 erase control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IfrEraseDis2 { + #[doc = "0: Enable IFR sector erase."] + Enable = 0, + #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IfrEraseDis2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IFR_ERASE_DIS2` reader - user IFR sector 2 erase control"] +pub type IfrEraseDis2R = crate::BitReader; +impl IfrEraseDis2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IfrEraseDis2 { + match self.bits { + false => IfrEraseDis2::Enable, + true => IfrEraseDis2::Disable, + } + } + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IfrEraseDis2::Enable + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IfrEraseDis2::Disable + } +} +#[doc = "Field `IFR_ERASE_DIS2` writer - user IFR sector 2 erase control"] +pub type IfrEraseDis2W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis2>; +impl<'a, REG> IfrEraseDis2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis2::Enable) + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis2::Disable) + } +} +#[doc = "user IFR sector 3 erase control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IfrEraseDis3 { + #[doc = "0: Enable IFR sector erase."] + Enable = 0, + #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IfrEraseDis3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IFR_ERASE_DIS3` reader - user IFR sector 3 erase control"] +pub type IfrEraseDis3R = crate::BitReader; +impl IfrEraseDis3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IfrEraseDis3 { + match self.bits { + false => IfrEraseDis3::Enable, + true => IfrEraseDis3::Disable, + } + } + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IfrEraseDis3::Enable + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IfrEraseDis3::Disable + } +} +#[doc = "Field `IFR_ERASE_DIS3` writer - user IFR sector 3 erase control"] +pub type IfrEraseDis3W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis3>; +impl<'a, REG> IfrEraseDis3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable IFR sector erase."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis3::Enable) + } + #[doc = "Disable IFR sector erase, write one lock until a system reset."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(IfrEraseDis3::Disable) + } +} +#[doc = "Mass erase control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MassEraseDis { + #[doc = "0: Enables mass erase"] + Enable = 0, + #[doc = "1: Disables mass erase, write one lock until a system reset."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MassEraseDis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MASS_ERASE_DIS` reader - Mass erase control"] +pub type MassEraseDisR = crate::BitReader; +impl MassEraseDisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MassEraseDis { + match self.bits { + false => MassEraseDis::Enable, + true => MassEraseDis::Disable, + } + } + #[doc = "Enables mass erase"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == MassEraseDis::Enable + } + #[doc = "Disables mass erase, write one lock until a system reset."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == MassEraseDis::Disable + } +} +#[doc = "Field `MASS_ERASE_DIS` writer - Mass erase control"] +pub type MassEraseDisW<'a, REG> = crate::BitWriter<'a, REG, MassEraseDis>; +impl<'a, REG> MassEraseDisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables mass erase"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(MassEraseDis::Enable) + } + #[doc = "Disables mass erase, write one lock until a system reset."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(MassEraseDis::Disable) + } +} +impl R { + #[doc = "Bit 0 - user IFR sector 0 erase control"] + #[inline(always)] + pub fn ifr_erase_dis0(&self) -> IfrEraseDis0R { + IfrEraseDis0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - user IFR sector 1 erase control"] + #[inline(always)] + pub fn ifr_erase_dis1(&self) -> IfrEraseDis1R { + IfrEraseDis1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - user IFR sector 2 erase control"] + #[inline(always)] + pub fn ifr_erase_dis2(&self) -> IfrEraseDis2R { + IfrEraseDis2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - user IFR sector 3 erase control"] + #[inline(always)] + pub fn ifr_erase_dis3(&self) -> IfrEraseDis3R { + IfrEraseDis3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Mass erase control"] + #[inline(always)] + pub fn mass_erase_dis(&self) -> MassEraseDisR { + MassEraseDisR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - user IFR sector 0 erase control"] + #[inline(always)] + pub fn ifr_erase_dis0(&mut self) -> IfrEraseDis0W { + IfrEraseDis0W::new(self, 0) + } + #[doc = "Bit 1 - user IFR sector 1 erase control"] + #[inline(always)] + pub fn ifr_erase_dis1(&mut self) -> IfrEraseDis1W { + IfrEraseDis1W::new(self, 1) + } + #[doc = "Bit 2 - user IFR sector 2 erase control"] + #[inline(always)] + pub fn ifr_erase_dis2(&mut self) -> IfrEraseDis2W { + IfrEraseDis2W::new(self, 2) + } + #[doc = "Bit 3 - user IFR sector 3 erase control"] + #[inline(always)] + pub fn ifr_erase_dis3(&mut self) -> IfrEraseDis3W { + IfrEraseDis3W::new(self, 3) + } + #[doc = "Bit 8 - Mass erase control"] + #[inline(always)] + pub fn mass_erase_dis(&mut self) -> MassEraseDisW { + MassEraseDisW::new(self, 8) + } +} +#[doc = "MSF Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`msfcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msfcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MsfcfgSpec; +impl crate::RegisterSpec for MsfcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`msfcfg::R`](R) reader structure"] +impl crate::Readable for MsfcfgSpec {} +#[doc = "`write(|w| ..)` method takes [`msfcfg::W`](W) writer structure"] +impl crate::Writable for MsfcfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MSFCFG to value 0"] +impl crate::Resettable for MsfcfgSpec {} diff --git a/mcxa276-pac/src/syscon/nmisrc.rs b/mcxa276-pac/src/syscon/nmisrc.rs new file mode 100644 index 000000000..ac3b3a449 --- /dev/null +++ b/mcxa276-pac/src/syscon/nmisrc.rs @@ -0,0 +1,98 @@ +#[doc = "Register `NMISRC` reader"] +pub type R = crate::R; +#[doc = "Register `NMISRC` writer"] +pub type W = crate::W; +#[doc = "Field `IRQCPU0` reader - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] +pub type Irqcpu0R = crate::FieldReader; +#[doc = "Field `IRQCPU0` writer - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] +pub type Irqcpu0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nmiencpu0 { + #[doc = "0: Disable."] + Disable = 0, + #[doc = "1: Enable."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nmiencpu0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIENCPU0` reader - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] +pub type Nmiencpu0R = crate::BitReader; +impl Nmiencpu0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nmiencpu0 { + match self.bits { + false => Nmiencpu0::Disable, + true => Nmiencpu0::Enable, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Nmiencpu0::Disable + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Nmiencpu0::Enable + } +} +#[doc = "Field `NMIENCPU0` writer - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] +pub type Nmiencpu0W<'a, REG> = crate::BitWriter<'a, REG, Nmiencpu0>; +impl<'a, REG> Nmiencpu0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Nmiencpu0::Disable) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Nmiencpu0::Enable) + } +} +impl R { + #[doc = "Bits 0:7 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] + #[inline(always)] + pub fn irqcpu0(&self) -> Irqcpu0R { + Irqcpu0R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 31 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] + #[inline(always)] + pub fn nmiencpu0(&self) -> Nmiencpu0R { + Nmiencpu0R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] + #[inline(always)] + pub fn irqcpu0(&mut self) -> Irqcpu0W { + Irqcpu0W::new(self, 0) + } + #[doc = "Bit 31 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] + #[inline(always)] + pub fn nmiencpu0(&mut self) -> Nmiencpu0W { + Nmiencpu0W::new(self, 31) + } +} +#[doc = "NMI Source Select\n\nYou can [`read`](crate::Reg::read) this register and get [`nmisrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmisrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NmisrcSpec; +impl crate::RegisterSpec for NmisrcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`nmisrc::R`](R) reader structure"] +impl crate::Readable for NmisrcSpec {} +#[doc = "`write(|w| ..)` method takes [`nmisrc::W`](W) writer structure"] +impl crate::Writable for NmisrcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets NMISRC to value 0"] +impl crate::Resettable for NmisrcSpec {} diff --git a/mcxa276-pac/src/syscon/nvm_ctrl.rs b/mcxa276-pac/src/syscon/nvm_ctrl.rs new file mode 100644 index 000000000..307e45151 --- /dev/null +++ b/mcxa276-pac/src/syscon/nvm_ctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `NVM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `NVM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Flash speculation control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DisFlashSpec { + #[doc = "0: Enables flash speculation"] + Enable = 0, + #[doc = "1: Disables flash speculation"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DisFlashSpec) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIS_FLASH_SPEC` reader - Flash speculation control"] +pub type DisFlashSpecR = crate::BitReader; +impl DisFlashSpecR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DisFlashSpec { + match self.bits { + false => DisFlashSpec::Enable, + true => DisFlashSpec::Disable, + } + } + #[doc = "Enables flash speculation"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DisFlashSpec::Enable + } + #[doc = "Disables flash speculation"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DisFlashSpec::Disable + } +} +#[doc = "Field `DIS_FLASH_SPEC` writer - Flash speculation control"] +pub type DisFlashSpecW<'a, REG> = crate::BitWriter<'a, REG, DisFlashSpec>; +impl<'a, REG> DisFlashSpecW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables flash speculation"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DisFlashSpec::Enable) + } + #[doc = "Disables flash speculation"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DisFlashSpec::Disable) + } +} +#[doc = "Flash data speculation control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DisDataSpec { + #[doc = "0: Enables data speculation"] + Enable = 0, + #[doc = "1: Disables data speculation"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DisDataSpec) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIS_DATA_SPEC` reader - Flash data speculation control"] +pub type DisDataSpecR = crate::BitReader; +impl DisDataSpecR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DisDataSpec { + match self.bits { + false => DisDataSpec::Enable, + true => DisDataSpec::Disable, + } + } + #[doc = "Enables data speculation"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DisDataSpec::Enable + } + #[doc = "Disables data speculation"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DisDataSpec::Disable + } +} +#[doc = "Field `DIS_DATA_SPEC` writer - Flash data speculation control"] +pub type DisDataSpecW<'a, REG> = crate::BitWriter<'a, REG, DisDataSpec>; +impl<'a, REG> DisDataSpecW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables data speculation"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DisDataSpec::Enable) + } + #[doc = "Disables data speculation"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DisDataSpec::Disable) + } +} +#[doc = "FLASH stall on busy control\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FlashStallEn { + #[doc = "0: No stall on FLASH busy"] + Enable = 0, + #[doc = "1: Stall on FLASH busy"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FlashStallEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASH_STALL_EN` reader - FLASH stall on busy control"] +pub type FlashStallEnR = crate::BitReader; +impl FlashStallEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FlashStallEn { + match self.bits { + false => FlashStallEn::Enable, + true => FlashStallEn::Disable, + } + } + #[doc = "No stall on FLASH busy"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == FlashStallEn::Enable + } + #[doc = "Stall on FLASH busy"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == FlashStallEn::Disable + } +} +#[doc = "Field `FLASH_STALL_EN` writer - FLASH stall on busy control"] +pub type FlashStallEnW<'a, REG> = crate::BitWriter<'a, REG, FlashStallEn>; +impl<'a, REG> FlashStallEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No stall on FLASH busy"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(FlashStallEn::Enable) + } + #[doc = "Stall on FLASH busy"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(FlashStallEn::Disable) + } +} +#[doc = "Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DisMbeccErrInst { + #[doc = "0: Enables bus error on multi-bit ECC error for instruction"] + Enable = 0, + #[doc = "1: Disables bus error on multi-bit ECC error for instruction"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DisMbeccErrInst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIS_MBECC_ERR_INST` reader - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] +pub type DisMbeccErrInstR = crate::BitReader; +impl DisMbeccErrInstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DisMbeccErrInst { + match self.bits { + false => DisMbeccErrInst::Enable, + true => DisMbeccErrInst::Disable, + } + } + #[doc = "Enables bus error on multi-bit ECC error for instruction"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DisMbeccErrInst::Enable + } + #[doc = "Disables bus error on multi-bit ECC error for instruction"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DisMbeccErrInst::Disable + } +} +#[doc = "Field `DIS_MBECC_ERR_INST` writer - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] +pub type DisMbeccErrInstW<'a, REG> = crate::BitWriter<'a, REG, DisMbeccErrInst>; +impl<'a, REG> DisMbeccErrInstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables bus error on multi-bit ECC error for instruction"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DisMbeccErrInst::Enable) + } + #[doc = "Disables bus error on multi-bit ECC error for instruction"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DisMbeccErrInst::Disable) + } +} +#[doc = "Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DisMbeccErrData { + #[doc = "0: Enables bus error on multi-bit ECC error for data"] + Enable = 0, + #[doc = "1: Disables bus error on multi-bit ECC error for data"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DisMbeccErrData) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIS_MBECC_ERR_DATA` reader - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] +pub type DisMbeccErrDataR = crate::BitReader; +impl DisMbeccErrDataR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DisMbeccErrData { + match self.bits { + false => DisMbeccErrData::Enable, + true => DisMbeccErrData::Disable, + } + } + #[doc = "Enables bus error on multi-bit ECC error for data"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DisMbeccErrData::Enable + } + #[doc = "Disables bus error on multi-bit ECC error for data"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DisMbeccErrData::Disable + } +} +#[doc = "Field `DIS_MBECC_ERR_DATA` writer - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] +pub type DisMbeccErrDataW<'a, REG> = crate::BitWriter<'a, REG, DisMbeccErrData>; +impl<'a, REG> DisMbeccErrDataW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enables bus error on multi-bit ECC error for data"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DisMbeccErrData::Enable) + } + #[doc = "Disables bus error on multi-bit ECC error for data"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DisMbeccErrData::Disable) + } +} +impl R { + #[doc = "Bit 0 - Flash speculation control"] + #[inline(always)] + pub fn dis_flash_spec(&self) -> DisFlashSpecR { + DisFlashSpecR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Flash data speculation control"] + #[inline(always)] + pub fn dis_data_spec(&self) -> DisDataSpecR { + DisDataSpecR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 10 - FLASH stall on busy control"] + #[inline(always)] + pub fn flash_stall_en(&self) -> FlashStallEnR { + FlashStallEnR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 16 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] + #[inline(always)] + pub fn dis_mbecc_err_inst(&self) -> DisMbeccErrInstR { + DisMbeccErrInstR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] + #[inline(always)] + pub fn dis_mbecc_err_data(&self) -> DisMbeccErrDataR { + DisMbeccErrDataR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flash speculation control"] + #[inline(always)] + pub fn dis_flash_spec(&mut self) -> DisFlashSpecW { + DisFlashSpecW::new(self, 0) + } + #[doc = "Bit 1 - Flash data speculation control"] + #[inline(always)] + pub fn dis_data_spec(&mut self) -> DisDataSpecW { + DisDataSpecW::new(self, 1) + } + #[doc = "Bit 10 - FLASH stall on busy control"] + #[inline(always)] + pub fn flash_stall_en(&mut self) -> FlashStallEnW { + FlashStallEnW::new(self, 10) + } + #[doc = "Bit 16 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] + #[inline(always)] + pub fn dis_mbecc_err_inst(&mut self) -> DisMbeccErrInstW { + DisMbeccErrInstW::new(self, 16) + } + #[doc = "Bit 17 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] + #[inline(always)] + pub fn dis_mbecc_err_data(&mut self) -> DisMbeccErrDataW { + DisMbeccErrDataW::new(self, 17) + } +} +#[doc = "NVM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`nvm_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvm_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NvmCtrlSpec; +impl crate::RegisterSpec for NvmCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvm_ctrl::R`](R) reader structure"] +impl crate::Readable for NvmCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`nvm_ctrl::W`](W) writer structure"] +impl crate::Writable for NvmCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets NVM_CTRL to value 0x0002_0400"] +impl crate::Resettable for NvmCtrlSpec { + const RESET_VALUE: u32 = 0x0002_0400; +} diff --git a/mcxa276-pac/src/syscon/pll1clkdiv.rs b/mcxa276-pac/src/syscon/pll1clkdiv.rs new file mode 100644 index 000000000..3c4608465 --- /dev/null +++ b/mcxa276-pac/src/syscon/pll1clkdiv.rs @@ -0,0 +1,204 @@ +#[doc = "Register `PLL1CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `PLL1CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Clock divider value"] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Clock divider value"] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Resets the divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider is not reset"] + Released = 0, + #[doc = "1: Divider is reset"] + Asserted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` reader - Resets the divider counter"] +pub type ResetR = crate::BitReader; +impl ResetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reset { + match self.bits { + false => Reset::Released, + true => Reset::Asserted, + } + } + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn is_released(&self) -> bool { + *self == Reset::Released + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn is_asserted(&self) -> bool { + *self == Reset::Asserted + } +} +#[doc = "Field `RESET` writer - Resets the divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn released(self) -> &'a mut crate::W { + self.variant(Reset::Released) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn asserted(self) -> &'a mut crate::W { + self.variant(Reset::Asserted) + } +} +#[doc = "Halts the divider counter\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + Run = 0, + #[doc = "1: Divider clock is stopped"] + Halt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halts the divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::Run, + true => Halt::Halt, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == Halt::Run + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_halt(&self) -> bool { + *self == Halt::Halt + } +} +#[doc = "Field `HALT` writer - Halts the divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn run(self) -> &'a mut crate::W { + self.variant(Halt::Run) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn halt(self) -> &'a mut crate::W { + self.variant(Halt::Halt) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + Stable = 0, + #[doc = "1: Clock frequency is not stable"] + Ongoing = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::Stable, + true => Unstab::Ongoing, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_stable(&self) -> bool { + *self == Unstab::Stable + } + #[doc = "Clock frequency is not stable"] + #[inline(always)] + pub fn is_ongoing(&self) -> bool { + *self == Unstab::Ongoing + } +} +impl R { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&self) -> ResetR { + ResetR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "PLL1_CLK_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pll1clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll1clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pll1clkdivSpec; +impl crate::RegisterSpec for Pll1clkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pll1clkdiv::R`](R) reader structure"] +impl crate::Readable for Pll1clkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`pll1clkdiv::W`](W) writer structure"] +impl crate::Writable for Pll1clkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PLL1CLKDIV to value 0x4000_0000"] +impl crate::Resettable for Pll1clkdivSpec { + const RESET_VALUE: u32 = 0x4000_0000; +} diff --git a/mcxa276-pac/src/syscon/protlvl.rs b/mcxa276-pac/src/syscon/protlvl.rs new file mode 100644 index 000000000..84ba46f16 --- /dev/null +++ b/mcxa276-pac/src/syscon/protlvl.rs @@ -0,0 +1,210 @@ +#[doc = "Register `PROTLVL` reader"] +pub type R = crate::R; +#[doc = "Register `PROTLVL` writer"] +pub type W = crate::W; +#[doc = "Control privileged access of EIM, ERM, Flexcan, MBC, SCG.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Priv { + #[doc = "0: privileged access is disabled. the peripherals could be access in user mode."] + Disable = 0, + #[doc = "1: privileged access is enabled. the peripherals could be access in privilege mode."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Priv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PRIV` reader - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] +pub type PrivR = crate::BitReader; +impl PrivR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Priv { + match self.bits { + false => Priv::Disable, + true => Priv::Enable, + } + } + #[doc = "privileged access is disabled. the peripherals could be access in user mode."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Priv::Disable + } + #[doc = "privileged access is enabled. the peripherals could be access in privilege mode."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Priv::Enable + } +} +#[doc = "Field `PRIV` writer - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] +pub type PrivW<'a, REG> = crate::BitWriter<'a, REG, Priv>; +impl<'a, REG> PrivW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "privileged access is disabled. the peripherals could be access in user mode."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Priv::Disable) + } + #[doc = "privileged access is enabled. the peripherals could be access in privilege mode."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Priv::Enable) + } +} +#[doc = "Control write access to Nonsecure MPU memory regions.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Locknsmpu { + #[doc = "0: Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] + Enable = 0, + #[doc = "1: Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Locknsmpu) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCKNSMPU` reader - Control write access to Nonsecure MPU memory regions."] +pub type LocknsmpuR = crate::BitReader; +impl LocknsmpuR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Locknsmpu { + match self.bits { + false => Locknsmpu::Enable, + true => Locknsmpu::Disable, + } + } + #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Locknsmpu::Enable + } + #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Locknsmpu::Disable + } +} +#[doc = "Field `LOCKNSMPU` writer - Control write access to Nonsecure MPU memory regions."] +pub type LocknsmpuW<'a, REG> = crate::BitWriter<'a, REG, Locknsmpu>; +impl<'a, REG> LocknsmpuW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Locknsmpu::Enable) + } + #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Locknsmpu::Disable) + } +} +#[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: This register is not locked and can be altered."] + Lock0 = 0, + #[doc = "1: This register is locked and cannot be altered until a system reset."] + Lock1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Lock0, + true => Lock::Lock1, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_lock_0(&self) -> bool { + *self == Lock::Lock0 + } + #[doc = "This register is locked and cannot be altered until a system reset."] + #[inline(always)] + pub fn is_lock_1(&self) -> bool { + *self == Lock::Lock1 + } +} +#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn lock_0(self) -> &'a mut crate::W { + self.variant(Lock::Lock0) + } + #[doc = "This register is locked and cannot be altered until a system reset."] + #[inline(always)] + pub fn lock_1(self) -> &'a mut crate::W { + self.variant(Lock::Lock1) + } +} +impl R { + #[doc = "Bit 0 - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] + #[inline(always)] + pub fn priv_(&self) -> PrivR { + PrivR::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - Control write access to Nonsecure MPU memory regions."] + #[inline(always)] + pub fn locknsmpu(&self) -> LocknsmpuR { + LocknsmpuR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] + #[inline(always)] + pub fn priv_(&mut self) -> PrivW { + PrivW::new(self, 0) + } + #[doc = "Bit 16 - Control write access to Nonsecure MPU memory regions."] + #[inline(always)] + pub fn locknsmpu(&mut self) -> LocknsmpuW { + LocknsmpuW::new(self, 16) + } + #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 31) + } +} +#[doc = "Protect Level Control\n\nYou can [`read`](crate::Reg::read) this register and get [`protlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`protlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ProtlvlSpec; +impl crate::RegisterSpec for ProtlvlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`protlvl::R`](R) reader structure"] +impl crate::Readable for ProtlvlSpec {} +#[doc = "`write(|w| ..)` method takes [`protlvl::W`](W) writer structure"] +impl crate::Writable for ProtlvlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PROTLVL to value 0"] +impl crate::Resettable for ProtlvlSpec {} diff --git a/mcxa276-pac/src/syscon/pwm0subctl.rs b/mcxa276-pac/src/syscon/pwm0subctl.rs new file mode 100644 index 000000000..97654b1b0 --- /dev/null +++ b/mcxa276-pac/src/syscon/pwm0subctl.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PWM0SUBCTL` reader"] +pub type R = crate::R; +#[doc = "Register `PWM0SUBCTL` writer"] +pub type W = crate::W; +#[doc = "Enables PWM0 SUB Clock0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk0En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk0En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK0_EN` reader - Enables PWM0 SUB Clock0"] +pub type Clk0EnR = crate::BitReader; +impl Clk0EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk0En { + match self.bits { + false => Clk0En::Disable, + true => Clk0En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk0En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk0En::Enable + } +} +#[doc = "Field `CLK0_EN` writer - Enables PWM0 SUB Clock0"] +pub type Clk0EnW<'a, REG> = crate::BitWriter<'a, REG, Clk0En>; +impl<'a, REG> Clk0EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk0En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk0En::Enable) + } +} +#[doc = "Enables PWM0 SUB Clock1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk1En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk1En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK1_EN` reader - Enables PWM0 SUB Clock1"] +pub type Clk1EnR = crate::BitReader; +impl Clk1EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk1En { + match self.bits { + false => Clk1En::Disable, + true => Clk1En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk1En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk1En::Enable + } +} +#[doc = "Field `CLK1_EN` writer - Enables PWM0 SUB Clock1"] +pub type Clk1EnW<'a, REG> = crate::BitWriter<'a, REG, Clk1En>; +impl<'a, REG> Clk1EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk1En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk1En::Enable) + } +} +#[doc = "Enables PWM0 SUB Clock2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk2En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk2En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK2_EN` reader - Enables PWM0 SUB Clock2"] +pub type Clk2EnR = crate::BitReader; +impl Clk2EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk2En { + match self.bits { + false => Clk2En::Disable, + true => Clk2En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk2En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk2En::Enable + } +} +#[doc = "Field `CLK2_EN` writer - Enables PWM0 SUB Clock2"] +pub type Clk2EnW<'a, REG> = crate::BitWriter<'a, REG, Clk2En>; +impl<'a, REG> Clk2EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk2En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk2En::Enable) + } +} +#[doc = "Enables PWM0 SUB Clock3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk3En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk3En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK3_EN` reader - Enables PWM0 SUB Clock3"] +pub type Clk3EnR = crate::BitReader; +impl Clk3EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk3En { + match self.bits { + false => Clk3En::Disable, + true => Clk3En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk3En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk3En::Enable + } +} +#[doc = "Field `CLK3_EN` writer - Enables PWM0 SUB Clock3"] +pub type Clk3EnW<'a, REG> = crate::BitWriter<'a, REG, Clk3En>; +impl<'a, REG> Clk3EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk3En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk3En::Enable) + } +} +impl R { + #[doc = "Bit 0 - Enables PWM0 SUB Clock0"] + #[inline(always)] + pub fn clk0_en(&self) -> Clk0EnR { + Clk0EnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables PWM0 SUB Clock1"] + #[inline(always)] + pub fn clk1_en(&self) -> Clk1EnR { + Clk1EnR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables PWM0 SUB Clock2"] + #[inline(always)] + pub fn clk2_en(&self) -> Clk2EnR { + Clk2EnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables PWM0 SUB Clock3"] + #[inline(always)] + pub fn clk3_en(&self) -> Clk3EnR { + Clk3EnR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables PWM0 SUB Clock0"] + #[inline(always)] + pub fn clk0_en(&mut self) -> Clk0EnW { + Clk0EnW::new(self, 0) + } + #[doc = "Bit 1 - Enables PWM0 SUB Clock1"] + #[inline(always)] + pub fn clk1_en(&mut self) -> Clk1EnW { + Clk1EnW::new(self, 1) + } + #[doc = "Bit 2 - Enables PWM0 SUB Clock2"] + #[inline(always)] + pub fn clk2_en(&mut self) -> Clk2EnW { + Clk2EnW::new(self, 2) + } + #[doc = "Bit 3 - Enables PWM0 SUB Clock3"] + #[inline(always)] + pub fn clk3_en(&mut self) -> Clk3EnW { + Clk3EnW::new(self, 3) + } +} +#[doc = "PWM0 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0subctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0subctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pwm0subctlSpec; +impl crate::RegisterSpec for Pwm0subctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm0subctl::R`](R) reader structure"] +impl crate::Readable for Pwm0subctlSpec {} +#[doc = "`write(|w| ..)` method takes [`pwm0subctl::W`](W) writer structure"] +impl crate::Writable for Pwm0subctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWM0SUBCTL to value 0"] +impl crate::Resettable for Pwm0subctlSpec {} diff --git a/mcxa276-pac/src/syscon/pwm1subctl.rs b/mcxa276-pac/src/syscon/pwm1subctl.rs new file mode 100644 index 000000000..c71180f04 --- /dev/null +++ b/mcxa276-pac/src/syscon/pwm1subctl.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PWM1SUBCTL` reader"] +pub type R = crate::R; +#[doc = "Register `PWM1SUBCTL` writer"] +pub type W = crate::W; +#[doc = "Enables PWM1 SUB Clock0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk0En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk0En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK0_EN` reader - Enables PWM1 SUB Clock0"] +pub type Clk0EnR = crate::BitReader; +impl Clk0EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk0En { + match self.bits { + false => Clk0En::Disable, + true => Clk0En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk0En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk0En::Enable + } +} +#[doc = "Field `CLK0_EN` writer - Enables PWM1 SUB Clock0"] +pub type Clk0EnW<'a, REG> = crate::BitWriter<'a, REG, Clk0En>; +impl<'a, REG> Clk0EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk0En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk0En::Enable) + } +} +#[doc = "Enables PWM1 SUB Clock1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk1En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk1En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK1_EN` reader - Enables PWM1 SUB Clock1"] +pub type Clk1EnR = crate::BitReader; +impl Clk1EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk1En { + match self.bits { + false => Clk1En::Disable, + true => Clk1En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk1En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk1En::Enable + } +} +#[doc = "Field `CLK1_EN` writer - Enables PWM1 SUB Clock1"] +pub type Clk1EnW<'a, REG> = crate::BitWriter<'a, REG, Clk1En>; +impl<'a, REG> Clk1EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk1En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk1En::Enable) + } +} +#[doc = "Enables PWM1 SUB Clock2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk2En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk2En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK2_EN` reader - Enables PWM1 SUB Clock2"] +pub type Clk2EnR = crate::BitReader; +impl Clk2EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk2En { + match self.bits { + false => Clk2En::Disable, + true => Clk2En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk2En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk2En::Enable + } +} +#[doc = "Field `CLK2_EN` writer - Enables PWM1 SUB Clock2"] +pub type Clk2EnW<'a, REG> = crate::BitWriter<'a, REG, Clk2En>; +impl<'a, REG> Clk2EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk2En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk2En::Enable) + } +} +#[doc = "Enables PWM1 SUB Clock3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Clk3En { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Clk3En) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK3_EN` reader - Enables PWM1 SUB Clock3"] +pub type Clk3EnR = crate::BitReader; +impl Clk3EnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clk3En { + match self.bits { + false => Clk3En::Disable, + true => Clk3En::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Clk3En::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Clk3En::Enable + } +} +#[doc = "Field `CLK3_EN` writer - Enables PWM1 SUB Clock3"] +pub type Clk3EnW<'a, REG> = crate::BitWriter<'a, REG, Clk3En>; +impl<'a, REG> Clk3EnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Clk3En::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Clk3En::Enable) + } +} +impl R { + #[doc = "Bit 0 - Enables PWM1 SUB Clock0"] + #[inline(always)] + pub fn clk0_en(&self) -> Clk0EnR { + Clk0EnR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables PWM1 SUB Clock1"] + #[inline(always)] + pub fn clk1_en(&self) -> Clk1EnR { + Clk1EnR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables PWM1 SUB Clock2"] + #[inline(always)] + pub fn clk2_en(&self) -> Clk2EnR { + Clk2EnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables PWM1 SUB Clock3"] + #[inline(always)] + pub fn clk3_en(&self) -> Clk3EnR { + Clk3EnR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables PWM1 SUB Clock0"] + #[inline(always)] + pub fn clk0_en(&mut self) -> Clk0EnW { + Clk0EnW::new(self, 0) + } + #[doc = "Bit 1 - Enables PWM1 SUB Clock1"] + #[inline(always)] + pub fn clk1_en(&mut self) -> Clk1EnW { + Clk1EnW::new(self, 1) + } + #[doc = "Bit 2 - Enables PWM1 SUB Clock2"] + #[inline(always)] + pub fn clk2_en(&mut self) -> Clk2EnW { + Clk2EnW::new(self, 2) + } + #[doc = "Bit 3 - Enables PWM1 SUB Clock3"] + #[inline(always)] + pub fn clk3_en(&mut self) -> Clk3EnW { + Clk3EnW::new(self, 3) + } +} +#[doc = "PWM1 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1subctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1subctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pwm1subctlSpec; +impl crate::RegisterSpec for Pwm1subctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm1subctl::R`](R) reader structure"] +impl crate::Readable for Pwm1subctlSpec {} +#[doc = "`write(|w| ..)` method takes [`pwm1subctl::W`](W) writer structure"] +impl crate::Writable for Pwm1subctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWM1SUBCTL to value 0"] +impl crate::Resettable for Pwm1subctlSpec {} diff --git a/mcxa276-pac/src/syscon/ram_ctrl.rs b/mcxa276-pac/src/syscon/ram_ctrl.rs new file mode 100644 index 000000000..b8e951205 --- /dev/null +++ b/mcxa276-pac/src/syscon/ram_ctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `RAM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_CTRL` writer"] +pub type W = crate::W; +#[doc = "RAMA ECC enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RamaEccEnable { + #[doc = "0: ECC is disabled"] + Disable = 0, + #[doc = "1: ECC is enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RamaEccEnable) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMA_ECC_ENABLE` reader - RAMA ECC enable"] +pub type RamaEccEnableR = crate::BitReader; +impl RamaEccEnableR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RamaEccEnable { + match self.bits { + false => RamaEccEnable::Disable, + true => RamaEccEnable::Enable, + } + } + #[doc = "ECC is disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RamaEccEnable::Disable + } + #[doc = "ECC is enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RamaEccEnable::Enable + } +} +#[doc = "Field `RAMA_ECC_ENABLE` writer - RAMA ECC enable"] +pub type RamaEccEnableW<'a, REG> = crate::BitWriter<'a, REG, RamaEccEnable>; +impl<'a, REG> RamaEccEnableW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ECC is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RamaEccEnable::Disable) + } + #[doc = "ECC is enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RamaEccEnable::Enable) + } +} +#[doc = "RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RamaCgOverride { + #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] + Disable = 0, + #[doc = "1: Auto clock gating feature is disabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RamaCgOverride) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMA_CG_OVERRIDE` reader - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] +pub type RamaCgOverrideR = crate::BitReader; +impl RamaCgOverrideR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RamaCgOverride { + match self.bits { + false => RamaCgOverride::Disable, + true => RamaCgOverride::Enable, + } + } + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RamaCgOverride::Disable + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RamaCgOverride::Enable + } +} +#[doc = "Field `RAMA_CG_OVERRIDE` writer - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] +pub type RamaCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamaCgOverride>; +impl<'a, REG> RamaCgOverrideW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RamaCgOverride::Disable) + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RamaCgOverride::Enable) + } +} +#[doc = "RAMX bank clock gating control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RamxCgOverride { + #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] + Disable = 0, + #[doc = "1: Auto clock gating feature is disabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RamxCgOverride) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMX_CG_OVERRIDE` reader - RAMX bank clock gating control"] +pub type RamxCgOverrideR = crate::BitReader; +impl RamxCgOverrideR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RamxCgOverride { + match self.bits { + false => RamxCgOverride::Disable, + true => RamxCgOverride::Enable, + } + } + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RamxCgOverride::Disable + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RamxCgOverride::Enable + } +} +#[doc = "Field `RAMX_CG_OVERRIDE` writer - RAMX bank clock gating control"] +pub type RamxCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamxCgOverride>; +impl<'a, REG> RamxCgOverrideW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RamxCgOverride::Disable) + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RamxCgOverride::Enable) + } +} +#[doc = "RAMB bank clock gating control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RambCgOverride { + #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] + Disable = 0, + #[doc = "1: Auto clock gating feature is disabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RambCgOverride) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMB_CG_OVERRIDE` reader - RAMB bank clock gating control"] +pub type RambCgOverrideR = crate::BitReader; +impl RambCgOverrideR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RambCgOverride { + match self.bits { + false => RambCgOverride::Disable, + true => RambCgOverride::Enable, + } + } + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RambCgOverride::Disable + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RambCgOverride::Enable + } +} +#[doc = "Field `RAMB_CG_OVERRIDE` writer - RAMB bank clock gating control"] +pub type RambCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RambCgOverride>; +impl<'a, REG> RambCgOverrideW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RambCgOverride::Disable) + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RambCgOverride::Enable) + } +} +#[doc = "RAMC bank clock gating control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RamcCgOverride { + #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] + Disable = 0, + #[doc = "1: Auto clock gating feature is disabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RamcCgOverride) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMC_CG_OVERRIDE` reader - RAMC bank clock gating control"] +pub type RamcCgOverrideR = crate::BitReader; +impl RamcCgOverrideR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RamcCgOverride { + match self.bits { + false => RamcCgOverride::Disable, + true => RamcCgOverride::Enable, + } + } + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RamcCgOverride::Disable + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RamcCgOverride::Enable + } +} +#[doc = "Field `RAMC_CG_OVERRIDE` writer - RAMC bank clock gating control"] +pub type RamcCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamcCgOverride>; +impl<'a, REG> RamcCgOverrideW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RamcCgOverride::Disable) + } + #[doc = "Auto clock gating feature is disabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RamcCgOverride::Enable) + } +} +impl R { + #[doc = "Bit 0 - RAMA ECC enable"] + #[inline(always)] + pub fn rama_ecc_enable(&self) -> RamaEccEnableR { + RamaEccEnableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] + #[inline(always)] + pub fn rama_cg_override(&self) -> RamaCgOverrideR { + RamaCgOverrideR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - RAMX bank clock gating control"] + #[inline(always)] + pub fn ramx_cg_override(&self) -> RamxCgOverrideR { + RamxCgOverrideR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - RAMB bank clock gating control"] + #[inline(always)] + pub fn ramb_cg_override(&self) -> RambCgOverrideR { + RambCgOverrideR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - RAMC bank clock gating control"] + #[inline(always)] + pub fn ramc_cg_override(&self) -> RamcCgOverrideR { + RamcCgOverrideR::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RAMA ECC enable"] + #[inline(always)] + pub fn rama_ecc_enable(&mut self) -> RamaEccEnableW { + RamaEccEnableW::new(self, 0) + } + #[doc = "Bit 16 - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] + #[inline(always)] + pub fn rama_cg_override(&mut self) -> RamaCgOverrideW { + RamaCgOverrideW::new(self, 16) + } + #[doc = "Bit 17 - RAMX bank clock gating control"] + #[inline(always)] + pub fn ramx_cg_override(&mut self) -> RamxCgOverrideW { + RamxCgOverrideW::new(self, 17) + } + #[doc = "Bit 18 - RAMB bank clock gating control"] + #[inline(always)] + pub fn ramb_cg_override(&mut self) -> RambCgOverrideW { + RambCgOverrideW::new(self, 18) + } + #[doc = "Bit 19 - RAMC bank clock gating control"] + #[inline(always)] + pub fn ramc_cg_override(&mut self) -> RamcCgOverrideW { + RamcCgOverrideW::new(self, 19) + } +} +#[doc = "RAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamCtrlSpec; +impl crate::RegisterSpec for RamCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_ctrl::R`](R) reader structure"] +impl crate::Readable for RamCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ram_ctrl::W`](W) writer structure"] +impl crate::Writable for RamCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM_CTRL to value 0x01"] +impl crate::Resettable for RamCtrlSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/syscon/ram_interleave.rs b/mcxa276-pac/src/syscon/ram_interleave.rs new file mode 100644 index 000000000..cf36f757a --- /dev/null +++ b/mcxa276-pac/src/syscon/ram_interleave.rs @@ -0,0 +1,84 @@ +#[doc = "Register `RAM_INTERLEAVE` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_INTERLEAVE` writer"] +pub type W = crate::W; +#[doc = "Controls RAM access for RAMA1 and RAMA2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Interleave { + #[doc = "0: RAM access is consecutive."] + Normal = 0, + #[doc = "1: RAM access is interleaved. This setting is need for PKC L0 memory access."] + Interleave = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Interleave) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTERLEAVE` reader - Controls RAM access for RAMA1 and RAMA2"] +pub type InterleaveR = crate::BitReader; +impl InterleaveR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Interleave { + match self.bits { + false => Interleave::Normal, + true => Interleave::Interleave, + } + } + #[doc = "RAM access is consecutive."] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == Interleave::Normal + } + #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."] + #[inline(always)] + pub fn is_interleave(&self) -> bool { + *self == Interleave::Interleave + } +} +#[doc = "Field `INTERLEAVE` writer - Controls RAM access for RAMA1 and RAMA2"] +pub type InterleaveW<'a, REG> = crate::BitWriter<'a, REG, Interleave>; +impl<'a, REG> InterleaveW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RAM access is consecutive."] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(Interleave::Normal) + } + #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."] + #[inline(always)] + pub fn interleave(self) -> &'a mut crate::W { + self.variant(Interleave::Interleave) + } +} +impl R { + #[doc = "Bit 0 - Controls RAM access for RAMA1 and RAMA2"] + #[inline(always)] + pub fn interleave(&self) -> InterleaveR { + InterleaveR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controls RAM access for RAMA1 and RAMA2"] + #[inline(always)] + pub fn interleave(&mut self) -> InterleaveW { + InterleaveW::new(self, 0) + } +} +#[doc = "Controls RAM Interleave Integration\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_interleave::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_interleave::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamInterleaveSpec; +impl crate::RegisterSpec for RamInterleaveSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_interleave::R`](R) reader structure"] +impl crate::Readable for RamInterleaveSpec {} +#[doc = "`write(|w| ..)` method takes [`ram_interleave::W`](W) writer structure"] +impl crate::Writable for RamInterleaveSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM_INTERLEAVE to value 0"] +impl crate::Resettable for RamInterleaveSpec {} diff --git a/mcxa276-pac/src/syscon/remap.rs b/mcxa276-pac/src/syscon/remap.rs new file mode 100644 index 000000000..fe3fe156f --- /dev/null +++ b/mcxa276-pac/src/syscon/remap.rs @@ -0,0 +1,504 @@ +#[doc = "Register `REMAP` reader"] +pub type R = crate::R; +#[doc = "Register `REMAP` writer"] +pub type W = crate::W; +#[doc = "RAMX0 address remap for CPU System bus\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cpu0Sbus { + #[doc = "0: RAMX0: alias space is disabled."] + Cpu0Sbus0 = 0, + #[doc = "1: RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] + Cpu0Sbus1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cpu0Sbus) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cpu0Sbus { + type Ux = u8; +} +impl crate::IsEnum for Cpu0Sbus {} +#[doc = "Field `CPU0_SBUS` reader - RAMX0 address remap for CPU System bus"] +pub type Cpu0SbusR = crate::FieldReader; +impl Cpu0SbusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cpu0Sbus::Cpu0Sbus0), + 1 => Some(Cpu0Sbus::Cpu0Sbus1), + _ => None, + } + } + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn is_cpu0_sbus_0(&self) -> bool { + *self == Cpu0Sbus::Cpu0Sbus0 + } + #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] + #[inline(always)] + pub fn is_cpu0_sbus_1(&self) -> bool { + *self == Cpu0Sbus::Cpu0Sbus1 + } +} +#[doc = "Field `CPU0_SBUS` writer - RAMX0 address remap for CPU System bus"] +pub type Cpu0SbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Sbus>; +impl<'a, REG> Cpu0SbusW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn cpu0_sbus_0(self) -> &'a mut crate::W { + self.variant(Cpu0Sbus::Cpu0Sbus0) + } + #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] + #[inline(always)] + pub fn cpu0_sbus_1(self) -> &'a mut crate::W { + self.variant(Cpu0Sbus::Cpu0Sbus1) + } +} +#[doc = "RAMX0 address remap for SmartDMA D-BUS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SmartDmaD { + #[doc = "0: RAMX0: alias space is disabled."] + SmartDmaD0 = 0, + #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] + SmartDmaD1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SmartDmaD) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SmartDmaD { + type Ux = u8; +} +impl crate::IsEnum for SmartDmaD {} +#[doc = "Field `SmartDMA_D` reader - RAMX0 address remap for SmartDMA D-BUS"] +pub type SmartDmaDR = crate::FieldReader; +impl SmartDmaDR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SmartDmaD::SmartDmaD0), + 1 => Some(SmartDmaD::SmartDmaD1), + _ => None, + } + } + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn is_smart_dma_d_0(&self) -> bool { + *self == SmartDmaD::SmartDmaD0 + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn is_smart_dma_d_1(&self) -> bool { + *self == SmartDmaD::SmartDmaD1 + } +} +#[doc = "Field `SmartDMA_D` writer - RAMX0 address remap for SmartDMA D-BUS"] +pub type SmartDmaDW<'a, REG> = crate::FieldWriter<'a, REG, 2, SmartDmaD>; +impl<'a, REG> SmartDmaDW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn smart_dma_d_0(self) -> &'a mut crate::W { + self.variant(SmartDmaD::SmartDmaD0) + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn smart_dma_d_1(self) -> &'a mut crate::W { + self.variant(SmartDmaD::SmartDmaD1) + } +} +#[doc = "RAMX0 address remap for SmartDMA I-BUS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SmartDmaI { + #[doc = "0: RAMX0: alias space is disabled."] + SmartDmaI0 = 0, + #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] + SmartDmaI1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SmartDmaI) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SmartDmaI { + type Ux = u8; +} +impl crate::IsEnum for SmartDmaI {} +#[doc = "Field `SmartDMA_I` reader - RAMX0 address remap for SmartDMA I-BUS"] +pub type SmartDmaIR = crate::FieldReader; +impl SmartDmaIR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SmartDmaI::SmartDmaI0), + 1 => Some(SmartDmaI::SmartDmaI1), + _ => None, + } + } + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn is_smart_dma_i_0(&self) -> bool { + *self == SmartDmaI::SmartDmaI0 + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn is_smart_dma_i_1(&self) -> bool { + *self == SmartDmaI::SmartDmaI1 + } +} +#[doc = "Field `SmartDMA_I` writer - RAMX0 address remap for SmartDMA I-BUS"] +pub type SmartDmaIW<'a, REG> = crate::FieldWriter<'a, REG, 2, SmartDmaI>; +impl<'a, REG> SmartDmaIW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn smart_dma_i_0(self) -> &'a mut crate::W { + self.variant(SmartDmaI::SmartDmaI0) + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn smart_dma_i_1(self) -> &'a mut crate::W { + self.variant(SmartDmaI::SmartDmaI1) + } +} +#[doc = "RAMX0 address remap for DMA0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dma0 { + #[doc = "0: RAMX0: alias space is disabled."] + Dma0_0 = 0, + #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] + Dma0_1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dma0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dma0 { + type Ux = u8; +} +impl crate::IsEnum for Dma0 {} +#[doc = "Field `DMA0` reader - RAMX0 address remap for DMA0"] +pub type Dma0R = crate::FieldReader; +impl Dma0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dma0::Dma0_0), + 1 => Some(Dma0::Dma0_1), + _ => None, + } + } + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn is_dma0_0(&self) -> bool { + *self == Dma0::Dma0_0 + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn is_dma0_1(&self) -> bool { + *self == Dma0::Dma0_1 + } +} +#[doc = "Field `DMA0` writer - RAMX0 address remap for DMA0"] +pub type Dma0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Dma0>; +impl<'a, REG> Dma0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn dma0_0(self) -> &'a mut crate::W { + self.variant(Dma0::Dma0_0) + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn dma0_1(self) -> &'a mut crate::W { + self.variant(Dma0::Dma0_1) + } +} +#[doc = "RAMX0 address remap for PKC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Pkc { + #[doc = "0: RAMX0: alias space is disabled."] + Pkc0 = 0, + #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] + Pkc1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Pkc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Pkc { + type Ux = u8; +} +impl crate::IsEnum for Pkc {} +#[doc = "Field `PKC` reader - RAMX0 address remap for PKC"] +pub type PkcR = crate::FieldReader; +impl PkcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Pkc::Pkc0), + 1 => Some(Pkc::Pkc1), + _ => None, + } + } + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn is_pkc_0(&self) -> bool { + *self == Pkc::Pkc0 + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn is_pkc_1(&self) -> bool { + *self == Pkc::Pkc1 + } +} +#[doc = "Field `PKC` writer - RAMX0 address remap for PKC"] +pub type PkcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pkc>; +impl<'a, REG> PkcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn pkc_0(self) -> &'a mut crate::W { + self.variant(Pkc::Pkc0) + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn pkc_1(self) -> &'a mut crate::W { + self.variant(Pkc::Pkc1) + } +} +#[doc = "RAMX0 address remap for USB0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Usb0 { + #[doc = "0: RAMX0: alias space is disabled."] + Usb0_0 = 0, + #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] + Usb0_1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Usb0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Usb0 { + type Ux = u8; +} +impl crate::IsEnum for Usb0 {} +#[doc = "Field `USB0` reader - RAMX0 address remap for USB0"] +pub type Usb0R = crate::FieldReader; +impl Usb0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Usb0::Usb0_0), + 1 => Some(Usb0::Usb0_1), + _ => None, + } + } + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn is_usb0_0(&self) -> bool { + *self == Usb0::Usb0_0 + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn is_usb0_1(&self) -> bool { + *self == Usb0::Usb0_1 + } +} +#[doc = "Field `USB0` writer - RAMX0 address remap for USB0"] +pub type Usb0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Usb0>; +impl<'a, REG> Usb0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "RAMX0: alias space is disabled."] + #[inline(always)] + pub fn usb0_0(self) -> &'a mut crate::W { + self.variant(Usb0::Usb0_0) + } + #[doc = "RAMX0: same alias space as CPU0_SBUS"] + #[inline(always)] + pub fn usb0_1(self) -> &'a mut crate::W { + self.variant(Usb0::Usb0_1) + } +} +#[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: This register is not locked and can be altered."] + Lock0 = 0, + #[doc = "1: This register is locked and cannot be altered until a system reset."] + Lock1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Lock0, + true => Lock::Lock1, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_lock_0(&self) -> bool { + *self == Lock::Lock0 + } + #[doc = "This register is locked and cannot be altered until a system reset."] + #[inline(always)] + pub fn is_lock_1(&self) -> bool { + *self == Lock::Lock1 + } +} +#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn lock_0(self) -> &'a mut crate::W { + self.variant(Lock::Lock0) + } + #[doc = "This register is locked and cannot be altered until a system reset."] + #[inline(always)] + pub fn lock_1(self) -> &'a mut crate::W { + self.variant(Lock::Lock1) + } +} +impl R { + #[doc = "Bits 2:3 - RAMX0 address remap for CPU System bus"] + #[inline(always)] + pub fn cpu0_sbus(&self) -> Cpu0SbusR { + Cpu0SbusR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - RAMX0 address remap for SmartDMA D-BUS"] + #[inline(always)] + pub fn smart_dma_d(&self) -> SmartDmaDR { + SmartDmaDR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - RAMX0 address remap for SmartDMA I-BUS"] + #[inline(always)] + pub fn smart_dma_i(&self) -> SmartDmaIR { + SmartDmaIR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - RAMX0 address remap for DMA0"] + #[inline(always)] + pub fn dma0(&self) -> Dma0R { + Dma0R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 12:13 - RAMX0 address remap for PKC"] + #[inline(always)] + pub fn pkc(&self) -> PkcR { + PkcR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 24:25 - RAMX0 address remap for USB0"] + #[inline(always)] + pub fn usb0(&self) -> Usb0R { + Usb0R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:3 - RAMX0 address remap for CPU System bus"] + #[inline(always)] + pub fn cpu0_sbus(&mut self) -> Cpu0SbusW { + Cpu0SbusW::new(self, 2) + } + #[doc = "Bits 4:5 - RAMX0 address remap for SmartDMA D-BUS"] + #[inline(always)] + pub fn smart_dma_d(&mut self) -> SmartDmaDW { + SmartDmaDW::new(self, 4) + } + #[doc = "Bits 6:7 - RAMX0 address remap for SmartDMA I-BUS"] + #[inline(always)] + pub fn smart_dma_i(&mut self) -> SmartDmaIW { + SmartDmaIW::new(self, 6) + } + #[doc = "Bits 8:9 - RAMX0 address remap for DMA0"] + #[inline(always)] + pub fn dma0(&mut self) -> Dma0W { + Dma0W::new(self, 8) + } + #[doc = "Bits 12:13 - RAMX0 address remap for PKC"] + #[inline(always)] + pub fn pkc(&mut self) -> PkcW { + PkcW::new(self, 12) + } + #[doc = "Bits 24:25 - RAMX0 address remap for USB0"] + #[inline(always)] + pub fn usb0(&mut self) -> Usb0W { + Usb0W::new(self, 24) + } + #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 31) + } +} +#[doc = "AHB Matrix Remap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RemapSpec; +impl crate::RegisterSpec for RemapSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`remap::R`](R) reader structure"] +impl crate::Readable for RemapSpec {} +#[doc = "`write(|w| ..)` method takes [`remap::W`](W) writer structure"] +impl crate::Writable for RemapSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets REMAP to value 0"] +impl crate::Resettable for RemapSpec {} diff --git a/mcxa276-pac/src/syscon/rop_state.rs b/mcxa276-pac/src/syscon/rop_state.rs new file mode 100644 index 000000000..821c564b7 --- /dev/null +++ b/mcxa276-pac/src/syscon/rop_state.rs @@ -0,0 +1,20 @@ +#[doc = "Register `ROP_STATE` reader"] +pub type R = crate::R; +#[doc = "Field `ROP_STATE` reader - ROP state"] +pub type RopStateR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - ROP state"] + #[inline(always)] + pub fn rop_state(&self) -> RopStateR { + RopStateR::new(self.bits) + } +} +#[doc = "ROP State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rop_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RopStateSpec; +impl crate::RegisterSpec for RopStateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rop_state::R`](R) reader structure"] +impl crate::Readable for RopStateSpec {} +#[doc = "`reset()` method sets ROP_STATE to value 0"] +impl crate::Resettable for RopStateSpec {} diff --git a/mcxa276-pac/src/syscon/slowclkdiv.rs b/mcxa276-pac/src/syscon/slowclkdiv.rs new file mode 100644 index 000000000..b8ac6c522 --- /dev/null +++ b/mcxa276-pac/src/syscon/slowclkdiv.rs @@ -0,0 +1,197 @@ +#[doc = "Register `SLOWCLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SLOWCLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Clock divider value"] +pub type DivR = crate::FieldReader; +#[doc = "Resets the divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Divider is not reset"] + Released = 0, + #[doc = "1: Divider is reset"] + Asserted = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` reader - Resets the divider counter"] +pub type ResetR = crate::BitReader; +impl ResetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reset { + match self.bits { + false => Reset::Released, + true => Reset::Asserted, + } + } + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn is_released(&self) -> bool { + *self == Reset::Released + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn is_asserted(&self) -> bool { + *self == Reset::Asserted + } +} +#[doc = "Field `RESET` writer - Resets the divider counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider is not reset"] + #[inline(always)] + pub fn released(self) -> &'a mut crate::W { + self.variant(Reset::Released) + } + #[doc = "Divider is reset"] + #[inline(always)] + pub fn asserted(self) -> &'a mut crate::W { + self.variant(Reset::Asserted) + } +} +#[doc = "Halts the divider counter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Halt { + #[doc = "0: Divider clock is running"] + Run = 0, + #[doc = "1: Divider clock is stopped"] + Halt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Halt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HALT` reader - Halts the divider counter"] +pub type HaltR = crate::BitReader; +impl HaltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Halt { + match self.bits { + false => Halt::Run, + true => Halt::Halt, + } + } + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == Halt::Run + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn is_halt(&self) -> bool { + *self == Halt::Halt + } +} +#[doc = "Field `HALT` writer - Halts the divider counter"] +pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; +impl<'a, REG> HaltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Divider clock is running"] + #[inline(always)] + pub fn run(self) -> &'a mut crate::W { + self.variant(Halt::Run) + } + #[doc = "Divider clock is stopped"] + #[inline(always)] + pub fn halt(self) -> &'a mut crate::W { + self.variant(Halt::Halt) + } +} +#[doc = "Divider status flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Unstab { + #[doc = "0: Divider clock is stable"] + Stable = 0, + #[doc = "1: Clock frequency is not stable"] + Ongoing = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Unstab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNSTAB` reader - Divider status flag"] +pub type UnstabR = crate::BitReader; +impl UnstabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Unstab { + match self.bits { + false => Unstab::Stable, + true => Unstab::Ongoing, + } + } + #[doc = "Divider clock is stable"] + #[inline(always)] + pub fn is_stable(&self) -> bool { + *self == Unstab::Stable + } + #[doc = "Clock frequency is not stable"] + #[inline(always)] + pub fn is_ongoing(&self) -> bool { + *self == Unstab::Ongoing + } +} +impl R { + #[doc = "Bits 0:7 - Clock divider value"] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&self) -> ResetR { + ResetR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&self) -> HaltR { + HaltR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Divider status flag"] + #[inline(always)] + pub fn unstab(&self) -> UnstabR { + UnstabR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 29 - Resets the divider counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 29) + } + #[doc = "Bit 30 - Halts the divider counter"] + #[inline(always)] + pub fn halt(&mut self) -> HaltW { + HaltW::new(self, 30) + } +} +#[doc = "SLOW_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`slowclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slowclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SlowclkdivSpec; +impl crate::RegisterSpec for SlowclkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`slowclkdiv::R`](R) reader structure"] +impl crate::Readable for SlowclkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`slowclkdiv::W`](W) writer structure"] +impl crate::Writable for SlowclkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SLOWCLKDIV to value 0x05"] +impl crate::Resettable for SlowclkdivSpec { + const RESET_VALUE: u32 = 0x05; +} diff --git a/mcxa276-pac/src/syscon/smart_dmaint.rs b/mcxa276-pac/src/syscon/smart_dmaint.rs new file mode 100644 index 000000000..9fe8450d0 --- /dev/null +++ b/mcxa276-pac/src/syscon/smart_dmaint.rs @@ -0,0 +1,1533 @@ +#[doc = "Register `SmartDMAINT` reader"] +pub type R = crate::R; +#[doc = "Register `SmartDMAINT` writer"] +pub type W = crate::W; +#[doc = "SmartDMA hijack NVIC IRQ1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int0 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT0` reader - SmartDMA hijack NVIC IRQ1"] +pub type Int0R = crate::BitReader; +impl Int0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int0 { + match self.bits { + false => Int0::Disable, + true => Int0::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int0::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int0::Enable + } +} +#[doc = "Field `INT0` writer - SmartDMA hijack NVIC IRQ1"] +pub type Int0W<'a, REG> = crate::BitWriter<'a, REG, Int0>; +impl<'a, REG> Int0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int0::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int0::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT1` reader - SmartDMA hijack NVIC IRQ17"] +pub type Int1R = crate::BitReader; +impl Int1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int1 { + match self.bits { + false => Int1::Disable, + true => Int1::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int1::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int1::Enable + } +} +#[doc = "Field `INT1` writer - SmartDMA hijack NVIC IRQ17"] +pub type Int1W<'a, REG> = crate::BitWriter<'a, REG, Int1>; +impl<'a, REG> Int1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int1::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int1::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int2 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT2` reader - SmartDMA hijack NVIC IRQ18"] +pub type Int2R = crate::BitReader; +impl Int2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int2 { + match self.bits { + false => Int2::Disable, + true => Int2::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int2::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int2::Enable + } +} +#[doc = "Field `INT2` writer - SmartDMA hijack NVIC IRQ18"] +pub type Int2W<'a, REG> = crate::BitWriter<'a, REG, Int2>; +impl<'a, REG> Int2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int2::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int2::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int3 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT3` reader - SmartDMA hijack NVIC IRQ29"] +pub type Int3R = crate::BitReader; +impl Int3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int3 { + match self.bits { + false => Int3::Disable, + true => Int3::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int3::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int3::Enable + } +} +#[doc = "Field `INT3` writer - SmartDMA hijack NVIC IRQ29"] +pub type Int3W<'a, REG> = crate::BitWriter<'a, REG, Int3>; +impl<'a, REG> Int3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int3::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int3::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int4 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT4` reader - SmartDMA hijack NVIC IRQ30"] +pub type Int4R = crate::BitReader; +impl Int4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int4 { + match self.bits { + false => Int4::Disable, + true => Int4::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int4::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int4::Enable + } +} +#[doc = "Field `INT4` writer - SmartDMA hijack NVIC IRQ30"] +pub type Int4W<'a, REG> = crate::BitWriter<'a, REG, Int4>; +impl<'a, REG> Int4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int4::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int4::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int5 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT5` reader - SmartDMA hijack NVIC IRQ31"] +pub type Int5R = crate::BitReader; +impl Int5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int5 { + match self.bits { + false => Int5::Disable, + true => Int5::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int5::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int5::Enable + } +} +#[doc = "Field `INT5` writer - SmartDMA hijack NVIC IRQ31"] +pub type Int5W<'a, REG> = crate::BitWriter<'a, REG, Int5>; +impl<'a, REG> Int5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int5::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int5::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ32\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int6 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT6` reader - SmartDMA hijack NVIC IRQ32"] +pub type Int6R = crate::BitReader; +impl Int6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int6 { + match self.bits { + false => Int6::Disable, + true => Int6::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int6::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int6::Enable + } +} +#[doc = "Field `INT6` writer - SmartDMA hijack NVIC IRQ32"] +pub type Int6W<'a, REG> = crate::BitWriter<'a, REG, Int6>; +impl<'a, REG> Int6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int6::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int6::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ33\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int7 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT7` reader - SmartDMA hijack NVIC IRQ33"] +pub type Int7R = crate::BitReader; +impl Int7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int7 { + match self.bits { + false => Int7::Disable, + true => Int7::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int7::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int7::Enable + } +} +#[doc = "Field `INT7` writer - SmartDMA hijack NVIC IRQ33"] +pub type Int7W<'a, REG> = crate::BitWriter<'a, REG, Int7>; +impl<'a, REG> Int7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int7::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int7::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ34\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int8 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT8` reader - SmartDMA hijack NVIC IRQ34"] +pub type Int8R = crate::BitReader; +impl Int8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int8 { + match self.bits { + false => Int8::Disable, + true => Int8::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int8::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int8::Enable + } +} +#[doc = "Field `INT8` writer - SmartDMA hijack NVIC IRQ34"] +pub type Int8W<'a, REG> = crate::BitWriter<'a, REG, Int8>; +impl<'a, REG> Int8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int8::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int8::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ35\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int9 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT9` reader - SmartDMA hijack NVIC IRQ35"] +pub type Int9R = crate::BitReader; +impl Int9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int9 { + match self.bits { + false => Int9::Disable, + true => Int9::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int9::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int9::Enable + } +} +#[doc = "Field `INT9` writer - SmartDMA hijack NVIC IRQ35"] +pub type Int9W<'a, REG> = crate::BitWriter<'a, REG, Int9>; +impl<'a, REG> Int9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int9::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int9::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ36\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int10 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT10` reader - SmartDMA hijack NVIC IRQ36"] +pub type Int10R = crate::BitReader; +impl Int10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int10 { + match self.bits { + false => Int10::Disable, + true => Int10::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int10::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int10::Enable + } +} +#[doc = "Field `INT10` writer - SmartDMA hijack NVIC IRQ36"] +pub type Int10W<'a, REG> = crate::BitWriter<'a, REG, Int10>; +impl<'a, REG> Int10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int10::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int10::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ37\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int11 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT11` reader - SmartDMA hijack NVIC IRQ37"] +pub type Int11R = crate::BitReader; +impl Int11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int11 { + match self.bits { + false => Int11::Disable, + true => Int11::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int11::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int11::Enable + } +} +#[doc = "Field `INT11` writer - SmartDMA hijack NVIC IRQ37"] +pub type Int11W<'a, REG> = crate::BitWriter<'a, REG, Int11>; +impl<'a, REG> Int11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int11::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int11::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ38\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int12 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT12` reader - SmartDMA hijack NVIC IRQ38"] +pub type Int12R = crate::BitReader; +impl Int12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int12 { + match self.bits { + false => Int12::Disable, + true => Int12::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int12::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int12::Enable + } +} +#[doc = "Field `INT12` writer - SmartDMA hijack NVIC IRQ38"] +pub type Int12W<'a, REG> = crate::BitWriter<'a, REG, Int12>; +impl<'a, REG> Int12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int12::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int12::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ39\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int13 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT13` reader - SmartDMA hijack NVIC IRQ39"] +pub type Int13R = crate::BitReader; +impl Int13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int13 { + match self.bits { + false => Int13::Disable, + true => Int13::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int13::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int13::Enable + } +} +#[doc = "Field `INT13` writer - SmartDMA hijack NVIC IRQ39"] +pub type Int13W<'a, REG> = crate::BitWriter<'a, REG, Int13>; +impl<'a, REG> Int13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int13::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int13::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ40\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int14 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT14` reader - SmartDMA hijack NVIC IRQ40"] +pub type Int14R = crate::BitReader; +impl Int14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int14 { + match self.bits { + false => Int14::Disable, + true => Int14::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int14::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int14::Enable + } +} +#[doc = "Field `INT14` writer - SmartDMA hijack NVIC IRQ40"] +pub type Int14W<'a, REG> = crate::BitWriter<'a, REG, Int14>; +impl<'a, REG> Int14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int14::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int14::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ41\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int15 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT15` reader - SmartDMA hijack NVIC IRQ41"] +pub type Int15R = crate::BitReader; +impl Int15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int15 { + match self.bits { + false => Int15::Disable, + true => Int15::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int15::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int15::Enable + } +} +#[doc = "Field `INT15` writer - SmartDMA hijack NVIC IRQ41"] +pub type Int15W<'a, REG> = crate::BitWriter<'a, REG, Int15>; +impl<'a, REG> Int15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int15::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int15::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ42\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int16 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT16` reader - SmartDMA hijack NVIC IRQ42"] +pub type Int16R = crate::BitReader; +impl Int16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int16 { + match self.bits { + false => Int16::Disable, + true => Int16::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int16::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int16::Enable + } +} +#[doc = "Field `INT16` writer - SmartDMA hijack NVIC IRQ42"] +pub type Int16W<'a, REG> = crate::BitWriter<'a, REG, Int16>; +impl<'a, REG> Int16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int16::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int16::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ45\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int17 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT17` reader - SmartDMA hijack NVIC IRQ45"] +pub type Int17R = crate::BitReader; +impl Int17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int17 { + match self.bits { + false => Int17::Disable, + true => Int17::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int17::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int17::Enable + } +} +#[doc = "Field `INT17` writer - SmartDMA hijack NVIC IRQ45"] +pub type Int17W<'a, REG> = crate::BitWriter<'a, REG, Int17>; +impl<'a, REG> Int17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int17::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int17::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ47\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int18 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT18` reader - SmartDMA hijack NVIC IRQ47"] +pub type Int18R = crate::BitReader; +impl Int18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int18 { + match self.bits { + false => Int18::Disable, + true => Int18::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int18::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int18::Enable + } +} +#[doc = "Field `INT18` writer - SmartDMA hijack NVIC IRQ47"] +pub type Int18W<'a, REG> = crate::BitWriter<'a, REG, Int18>; +impl<'a, REG> Int18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int18::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int18::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ50\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int19 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT19` reader - SmartDMA hijack NVIC IRQ50"] +pub type Int19R = crate::BitReader; +impl Int19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int19 { + match self.bits { + false => Int19::Disable, + true => Int19::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int19::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int19::Enable + } +} +#[doc = "Field `INT19` writer - SmartDMA hijack NVIC IRQ50"] +pub type Int19W<'a, REG> = crate::BitWriter<'a, REG, Int19>; +impl<'a, REG> Int19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int19::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int19::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ51\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int20 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT20` reader - SmartDMA hijack NVIC IRQ51"] +pub type Int20R = crate::BitReader; +impl Int20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int20 { + match self.bits { + false => Int20::Disable, + true => Int20::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int20::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int20::Enable + } +} +#[doc = "Field `INT20` writer - SmartDMA hijack NVIC IRQ51"] +pub type Int20W<'a, REG> = crate::BitWriter<'a, REG, Int20>; +impl<'a, REG> Int20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int20::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int20::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ66\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int21 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT21` reader - SmartDMA hijack NVIC IRQ66"] +pub type Int21R = crate::BitReader; +impl Int21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int21 { + match self.bits { + false => Int21::Disable, + true => Int21::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int21::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int21::Enable + } +} +#[doc = "Field `INT21` writer - SmartDMA hijack NVIC IRQ66"] +pub type Int21W<'a, REG> = crate::BitWriter<'a, REG, Int21>; +impl<'a, REG> Int21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int21::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int21::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ67\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int22 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT22` reader - SmartDMA hijack NVIC IRQ67"] +pub type Int22R = crate::BitReader; +impl Int22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int22 { + match self.bits { + false => Int22::Disable, + true => Int22::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int22::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int22::Enable + } +} +#[doc = "Field `INT22` writer - SmartDMA hijack NVIC IRQ67"] +pub type Int22W<'a, REG> = crate::BitWriter<'a, REG, Int22>; +impl<'a, REG> Int22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int22::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int22::Enable) + } +} +#[doc = "SmartDMA hijack NVIC IRQ77\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Int23 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Int23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INT23` reader - SmartDMA hijack NVIC IRQ77"] +pub type Int23R = crate::BitReader; +impl Int23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Int23 { + match self.bits { + false => Int23::Disable, + true => Int23::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Int23::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Int23::Enable + } +} +#[doc = "Field `INT23` writer - SmartDMA hijack NVIC IRQ77"] +pub type Int23W<'a, REG> = crate::BitWriter<'a, REG, Int23>; +impl<'a, REG> Int23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Int23::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Int23::Enable) + } +} +impl R { + #[doc = "Bit 0 - SmartDMA hijack NVIC IRQ1"] + #[inline(always)] + pub fn int0(&self) -> Int0R { + Int0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SmartDMA hijack NVIC IRQ17"] + #[inline(always)] + pub fn int1(&self) -> Int1R { + Int1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SmartDMA hijack NVIC IRQ18"] + #[inline(always)] + pub fn int2(&self) -> Int2R { + Int2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SmartDMA hijack NVIC IRQ29"] + #[inline(always)] + pub fn int3(&self) -> Int3R { + Int3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - SmartDMA hijack NVIC IRQ30"] + #[inline(always)] + pub fn int4(&self) -> Int4R { + Int4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - SmartDMA hijack NVIC IRQ31"] + #[inline(always)] + pub fn int5(&self) -> Int5R { + Int5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - SmartDMA hijack NVIC IRQ32"] + #[inline(always)] + pub fn int6(&self) -> Int6R { + Int6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - SmartDMA hijack NVIC IRQ33"] + #[inline(always)] + pub fn int7(&self) -> Int7R { + Int7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - SmartDMA hijack NVIC IRQ34"] + #[inline(always)] + pub fn int8(&self) -> Int8R { + Int8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - SmartDMA hijack NVIC IRQ35"] + #[inline(always)] + pub fn int9(&self) -> Int9R { + Int9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SmartDMA hijack NVIC IRQ36"] + #[inline(always)] + pub fn int10(&self) -> Int10R { + Int10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SmartDMA hijack NVIC IRQ37"] + #[inline(always)] + pub fn int11(&self) -> Int11R { + Int11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - SmartDMA hijack NVIC IRQ38"] + #[inline(always)] + pub fn int12(&self) -> Int12R { + Int12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - SmartDMA hijack NVIC IRQ39"] + #[inline(always)] + pub fn int13(&self) -> Int13R { + Int13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - SmartDMA hijack NVIC IRQ40"] + #[inline(always)] + pub fn int14(&self) -> Int14R { + Int14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - SmartDMA hijack NVIC IRQ41"] + #[inline(always)] + pub fn int15(&self) -> Int15R { + Int15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SmartDMA hijack NVIC IRQ42"] + #[inline(always)] + pub fn int16(&self) -> Int16R { + Int16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SmartDMA hijack NVIC IRQ45"] + #[inline(always)] + pub fn int17(&self) -> Int17R { + Int17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - SmartDMA hijack NVIC IRQ47"] + #[inline(always)] + pub fn int18(&self) -> Int18R { + Int18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - SmartDMA hijack NVIC IRQ50"] + #[inline(always)] + pub fn int19(&self) -> Int19R { + Int19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - SmartDMA hijack NVIC IRQ51"] + #[inline(always)] + pub fn int20(&self) -> Int20R { + Int20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - SmartDMA hijack NVIC IRQ66"] + #[inline(always)] + pub fn int21(&self) -> Int21R { + Int21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - SmartDMA hijack NVIC IRQ67"] + #[inline(always)] + pub fn int22(&self) -> Int22R { + Int22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - SmartDMA hijack NVIC IRQ77"] + #[inline(always)] + pub fn int23(&self) -> Int23R { + Int23R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SmartDMA hijack NVIC IRQ1"] + #[inline(always)] + pub fn int0(&mut self) -> Int0W { + Int0W::new(self, 0) + } + #[doc = "Bit 1 - SmartDMA hijack NVIC IRQ17"] + #[inline(always)] + pub fn int1(&mut self) -> Int1W { + Int1W::new(self, 1) + } + #[doc = "Bit 2 - SmartDMA hijack NVIC IRQ18"] + #[inline(always)] + pub fn int2(&mut self) -> Int2W { + Int2W::new(self, 2) + } + #[doc = "Bit 3 - SmartDMA hijack NVIC IRQ29"] + #[inline(always)] + pub fn int3(&mut self) -> Int3W { + Int3W::new(self, 3) + } + #[doc = "Bit 4 - SmartDMA hijack NVIC IRQ30"] + #[inline(always)] + pub fn int4(&mut self) -> Int4W { + Int4W::new(self, 4) + } + #[doc = "Bit 5 - SmartDMA hijack NVIC IRQ31"] + #[inline(always)] + pub fn int5(&mut self) -> Int5W { + Int5W::new(self, 5) + } + #[doc = "Bit 6 - SmartDMA hijack NVIC IRQ32"] + #[inline(always)] + pub fn int6(&mut self) -> Int6W { + Int6W::new(self, 6) + } + #[doc = "Bit 7 - SmartDMA hijack NVIC IRQ33"] + #[inline(always)] + pub fn int7(&mut self) -> Int7W { + Int7W::new(self, 7) + } + #[doc = "Bit 8 - SmartDMA hijack NVIC IRQ34"] + #[inline(always)] + pub fn int8(&mut self) -> Int8W { + Int8W::new(self, 8) + } + #[doc = "Bit 9 - SmartDMA hijack NVIC IRQ35"] + #[inline(always)] + pub fn int9(&mut self) -> Int9W { + Int9W::new(self, 9) + } + #[doc = "Bit 10 - SmartDMA hijack NVIC IRQ36"] + #[inline(always)] + pub fn int10(&mut self) -> Int10W { + Int10W::new(self, 10) + } + #[doc = "Bit 11 - SmartDMA hijack NVIC IRQ37"] + #[inline(always)] + pub fn int11(&mut self) -> Int11W { + Int11W::new(self, 11) + } + #[doc = "Bit 12 - SmartDMA hijack NVIC IRQ38"] + #[inline(always)] + pub fn int12(&mut self) -> Int12W { + Int12W::new(self, 12) + } + #[doc = "Bit 13 - SmartDMA hijack NVIC IRQ39"] + #[inline(always)] + pub fn int13(&mut self) -> Int13W { + Int13W::new(self, 13) + } + #[doc = "Bit 14 - SmartDMA hijack NVIC IRQ40"] + #[inline(always)] + pub fn int14(&mut self) -> Int14W { + Int14W::new(self, 14) + } + #[doc = "Bit 15 - SmartDMA hijack NVIC IRQ41"] + #[inline(always)] + pub fn int15(&mut self) -> Int15W { + Int15W::new(self, 15) + } + #[doc = "Bit 16 - SmartDMA hijack NVIC IRQ42"] + #[inline(always)] + pub fn int16(&mut self) -> Int16W { + Int16W::new(self, 16) + } + #[doc = "Bit 17 - SmartDMA hijack NVIC IRQ45"] + #[inline(always)] + pub fn int17(&mut self) -> Int17W { + Int17W::new(self, 17) + } + #[doc = "Bit 18 - SmartDMA hijack NVIC IRQ47"] + #[inline(always)] + pub fn int18(&mut self) -> Int18W { + Int18W::new(self, 18) + } + #[doc = "Bit 19 - SmartDMA hijack NVIC IRQ50"] + #[inline(always)] + pub fn int19(&mut self) -> Int19W { + Int19W::new(self, 19) + } + #[doc = "Bit 20 - SmartDMA hijack NVIC IRQ51"] + #[inline(always)] + pub fn int20(&mut self) -> Int20W { + Int20W::new(self, 20) + } + #[doc = "Bit 21 - SmartDMA hijack NVIC IRQ66"] + #[inline(always)] + pub fn int21(&mut self) -> Int21W { + Int21W::new(self, 21) + } + #[doc = "Bit 22 - SmartDMA hijack NVIC IRQ67"] + #[inline(always)] + pub fn int22(&mut self) -> Int22W { + Int22W::new(self, 22) + } + #[doc = "Bit 23 - SmartDMA hijack NVIC IRQ77"] + #[inline(always)] + pub fn int23(&mut self) -> Int23W { + Int23W::new(self, 23) + } +} +#[doc = "SmartDMA Interrupt Hijack\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dmaint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dmaint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SmartDmaintSpec; +impl crate::RegisterSpec for SmartDmaintSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`smart_dmaint::R`](R) reader structure"] +impl crate::Readable for SmartDmaintSpec {} +#[doc = "`write(|w| ..)` method takes [`smart_dmaint::W`](W) writer structure"] +impl crate::Writable for SmartDmaintSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SmartDMAINT to value 0"] +impl crate::Resettable for SmartDmaintSpec {} diff --git a/mcxa276-pac/src/syscon/sram_xen.rs b/mcxa276-pac/src/syscon/sram_xen.rs new file mode 100644 index 000000000..000520c10 --- /dev/null +++ b/mcxa276-pac/src/syscon/sram_xen.rs @@ -0,0 +1,462 @@ +#[doc = "Register `SRAM_XEN` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM_XEN` writer"] +pub type W = crate::W; +#[doc = "RAMX0 Execute permission control.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ramx0Xen { + #[doc = "0: Execute permission is disabled, R/W are enabled."] + Disable = 0, + #[doc = "1: Execute permission is enabled, R/W/X are enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ramx0Xen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMX0_XEN` reader - RAMX0 Execute permission control."] +pub type Ramx0XenR = crate::BitReader; +impl Ramx0XenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ramx0Xen { + match self.bits { + false => Ramx0Xen::Disable, + true => Ramx0Xen::Enable, + } + } + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ramx0Xen::Disable + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ramx0Xen::Enable + } +} +#[doc = "Field `RAMX0_XEN` writer - RAMX0 Execute permission control."] +pub type Ramx0XenW<'a, REG> = crate::BitWriter<'a, REG, Ramx0Xen>; +impl<'a, REG> Ramx0XenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ramx0Xen::Disable) + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ramx0Xen::Enable) + } +} +#[doc = "RAMX1 Execute permission control.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ramx1Xen { + #[doc = "0: Execute permission is disabled, R/W are enabled."] + Disable = 0, + #[doc = "1: Execute permission is enabled, R/W/X are enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ramx1Xen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMX1_XEN` reader - RAMX1 Execute permission control."] +pub type Ramx1XenR = crate::BitReader; +impl Ramx1XenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ramx1Xen { + match self.bits { + false => Ramx1Xen::Disable, + true => Ramx1Xen::Enable, + } + } + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ramx1Xen::Disable + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ramx1Xen::Enable + } +} +#[doc = "Field `RAMX1_XEN` writer - RAMX1 Execute permission control."] +pub type Ramx1XenW<'a, REG> = crate::BitWriter<'a, REG, Ramx1Xen>; +impl<'a, REG> Ramx1XenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ramx1Xen::Disable) + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ramx1Xen::Enable) + } +} +#[doc = "RAMA0 Execute permission control.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rama0Xen { + #[doc = "0: Execute permission is disabled, R/W are enabled."] + Disable = 0, + #[doc = "1: Execute permission is enabled, R/W/X are enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rama0Xen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMA0_XEN` reader - RAMA0 Execute permission control."] +pub type Rama0XenR = crate::BitReader; +impl Rama0XenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rama0Xen { + match self.bits { + false => Rama0Xen::Disable, + true => Rama0Xen::Enable, + } + } + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rama0Xen::Disable + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rama0Xen::Enable + } +} +#[doc = "Field `RAMA0_XEN` writer - RAMA0 Execute permission control."] +pub type Rama0XenW<'a, REG> = crate::BitWriter<'a, REG, Rama0Xen>; +impl<'a, REG> Rama0XenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Rama0Xen::Disable) + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Rama0Xen::Enable) + } +} +#[doc = "RAMAx (excepts RAMA0) Execute permission control.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rama1Xen { + #[doc = "0: Execute permission is disabled, R/W are enabled."] + Disable = 0, + #[doc = "1: Execute permission is enabled, R/W/X are enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rama1Xen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMA1_XEN` reader - RAMAx (excepts RAMA0) Execute permission control."] +pub type Rama1XenR = crate::BitReader; +impl Rama1XenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rama1Xen { + match self.bits { + false => Rama1Xen::Disable, + true => Rama1Xen::Enable, + } + } + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rama1Xen::Disable + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rama1Xen::Enable + } +} +#[doc = "Field `RAMA1_XEN` writer - RAMAx (excepts RAMA0) Execute permission control."] +pub type Rama1XenW<'a, REG> = crate::BitWriter<'a, REG, Rama1Xen>; +impl<'a, REG> Rama1XenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Rama1Xen::Disable) + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Rama1Xen::Enable) + } +} +#[doc = "RAMBx Execute permission control.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RambXen { + #[doc = "0: Execute permission is disabled, R/W are enabled."] + Disable = 0, + #[doc = "1: Execute permission is enabled, R/W/X are enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RambXen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMB_XEN` reader - RAMBx Execute permission control."] +pub type RambXenR = crate::BitReader; +impl RambXenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RambXen { + match self.bits { + false => RambXen::Disable, + true => RambXen::Enable, + } + } + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RambXen::Disable + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RambXen::Enable + } +} +#[doc = "Field `RAMB_XEN` writer - RAMBx Execute permission control."] +pub type RambXenW<'a, REG> = crate::BitWriter<'a, REG, RambXen>; +impl<'a, REG> RambXenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RambXen::Disable) + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RambXen::Enable) + } +} +#[doc = "RAMCx Execute permission control.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RamcXen { + #[doc = "0: Execute permission is disabled, R/W are enabled."] + Disable = 0, + #[doc = "1: Execute permission is enabled, R/W/X are enabled."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RamcXen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAMC_XEN` reader - RAMCx Execute permission control."] +pub type RamcXenR = crate::BitReader; +impl RamcXenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RamcXen { + match self.bits { + false => RamcXen::Disable, + true => RamcXen::Enable, + } + } + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == RamcXen::Disable + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == RamcXen::Enable + } +} +#[doc = "Field `RAMC_XEN` writer - RAMCx Execute permission control."] +pub type RamcXenW<'a, REG> = crate::BitWriter<'a, REG, RamcXen>; +impl<'a, REG> RamcXenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Execute permission is disabled, R/W are enabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RamcXen::Disable) + } + #[doc = "Execute permission is enabled, R/W/X are enabled."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RamcXen::Enable) + } +} +#[doc = "This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: This register is not locked and can be altered."] + Lock0 = 0, + #[doc = "1: This register is locked and cannot be altered."] + Lock1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Lock0, + true => Lock::Lock1, + } + } + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn is_lock_0(&self) -> bool { + *self == Lock::Lock0 + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn is_lock_1(&self) -> bool { + *self == Lock::Lock1 + } +} +#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "This register is not locked and can be altered."] + #[inline(always)] + pub fn lock_0(self) -> &'a mut crate::W { + self.variant(Lock::Lock0) + } + #[doc = "This register is locked and cannot be altered."] + #[inline(always)] + pub fn lock_1(self) -> &'a mut crate::W { + self.variant(Lock::Lock1) + } +} +impl R { + #[doc = "Bit 0 - RAMX0 Execute permission control."] + #[inline(always)] + pub fn ramx0_xen(&self) -> Ramx0XenR { + Ramx0XenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RAMX1 Execute permission control."] + #[inline(always)] + pub fn ramx1_xen(&self) -> Ramx1XenR { + Ramx1XenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RAMA0 Execute permission control."] + #[inline(always)] + pub fn rama0_xen(&self) -> Rama0XenR { + Rama0XenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RAMAx (excepts RAMA0) Execute permission control."] + #[inline(always)] + pub fn rama1_xen(&self) -> Rama1XenR { + Rama1XenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RAMBx Execute permission control."] + #[inline(always)] + pub fn ramb_xen(&self) -> RambXenR { + RambXenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RAMCx Execute permission control."] + #[inline(always)] + pub fn ramc_xen(&self) -> RamcXenR { + RamcXenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RAMX0 Execute permission control."] + #[inline(always)] + pub fn ramx0_xen(&mut self) -> Ramx0XenW { + Ramx0XenW::new(self, 0) + } + #[doc = "Bit 1 - RAMX1 Execute permission control."] + #[inline(always)] + pub fn ramx1_xen(&mut self) -> Ramx1XenW { + Ramx1XenW::new(self, 1) + } + #[doc = "Bit 2 - RAMA0 Execute permission control."] + #[inline(always)] + pub fn rama0_xen(&mut self) -> Rama0XenW { + Rama0XenW::new(self, 2) + } + #[doc = "Bit 3 - RAMAx (excepts RAMA0) Execute permission control."] + #[inline(always)] + pub fn rama1_xen(&mut self) -> Rama1XenW { + Rama1XenW::new(self, 3) + } + #[doc = "Bit 4 - RAMBx Execute permission control."] + #[inline(always)] + pub fn ramb_xen(&mut self) -> RambXenW { + RambXenW::new(self, 4) + } + #[doc = "Bit 5 - RAMCx Execute permission control."] + #[inline(always)] + pub fn ramc_xen(&mut self) -> RamcXenW { + RamcXenW::new(self, 5) + } + #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 31) + } +} +#[doc = "RAM XEN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SramXenSpec; +impl crate::RegisterSpec for SramXenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram_xen::R`](R) reader structure"] +impl crate::Readable for SramXenSpec {} +#[doc = "`write(|w| ..)` method takes [`sram_xen::W`](W) writer structure"] +impl crate::Writable for SramXenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SRAM_XEN to value 0"] +impl crate::Resettable for SramXenSpec {} diff --git a/mcxa276-pac/src/syscon/sram_xen_dp.rs b/mcxa276-pac/src/syscon/sram_xen_dp.rs new file mode 100644 index 000000000..53a2ff879 --- /dev/null +++ b/mcxa276-pac/src/syscon/sram_xen_dp.rs @@ -0,0 +1,105 @@ +#[doc = "Register `SRAM_XEN_DP` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM_XEN_DP` writer"] +pub type W = crate::W; +#[doc = "Field `RAMX0_XEN` reader - Refer to SRAM_XEN for more details."] +pub type Ramx0XenR = crate::BitReader; +#[doc = "Field `RAMX0_XEN` writer - Refer to SRAM_XEN for more details."] +pub type Ramx0XenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAMX1_XEN` reader - Refer to SRAM_XEN for more details."] +pub type Ramx1XenR = crate::BitReader; +#[doc = "Field `RAMX1_XEN` writer - Refer to SRAM_XEN for more details."] +pub type Ramx1XenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAMA0_XEN` reader - Refer to SRAM_XEN for more details."] +pub type Rama0XenR = crate::BitReader; +#[doc = "Field `RAMA0_XEN` writer - Refer to SRAM_XEN for more details."] +pub type Rama0XenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAMA1_XEN` reader - Refer to SRAM_XEN for more details."] +pub type Rama1XenR = crate::BitReader; +#[doc = "Field `RAMA1_XEN` writer - Refer to SRAM_XEN for more details."] +pub type Rama1XenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAMB_XEN` reader - Refer to SRAM_XEN for more details."] +pub type RambXenR = crate::BitReader; +#[doc = "Field `RAMB_XEN` writer - Refer to SRAM_XEN for more details."] +pub type RambXenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAMC_XEN` reader - Refer to SRAM_XEN for more details."] +pub type RamcXenR = crate::BitReader; +#[doc = "Field `RAMC_XEN` writer - Refer to SRAM_XEN for more details."] +pub type RamcXenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramx0_xen(&self) -> Ramx0XenR { + Ramx0XenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramx1_xen(&self) -> Ramx1XenR { + Ramx1XenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn rama0_xen(&self) -> Rama0XenR { + Rama0XenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn rama1_xen(&self) -> Rama1XenR { + Rama1XenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramb_xen(&self) -> RambXenR { + RambXenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramc_xen(&self) -> RamcXenR { + RamcXenR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramx0_xen(&mut self) -> Ramx0XenW { + Ramx0XenW::new(self, 0) + } + #[doc = "Bit 1 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramx1_xen(&mut self) -> Ramx1XenW { + Ramx1XenW::new(self, 1) + } + #[doc = "Bit 2 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn rama0_xen(&mut self) -> Rama0XenW { + Rama0XenW::new(self, 2) + } + #[doc = "Bit 3 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn rama1_xen(&mut self) -> Rama1XenW { + Rama1XenW::new(self, 3) + } + #[doc = "Bit 4 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramb_xen(&mut self) -> RambXenW { + RambXenW::new(self, 4) + } + #[doc = "Bit 5 - Refer to SRAM_XEN for more details."] + #[inline(always)] + pub fn ramc_xen(&mut self) -> RamcXenW { + RamcXenW::new(self, 5) + } +} +#[doc = "RAM XEN Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen_dp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen_dp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SramXenDpSpec; +impl crate::RegisterSpec for SramXenDpSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram_xen_dp::R`](R) reader structure"] +impl crate::Readable for SramXenDpSpec {} +#[doc = "`write(|w| ..)` method takes [`sram_xen_dp::W`](W) writer structure"] +impl crate::Writable for SramXenDpSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SRAM_XEN_DP to value 0"] +impl crate::Resettable for SramXenDpSpec {} diff --git a/mcxa276-pac/src/syscon/swd_access_cpu0.rs b/mcxa276-pac/src/syscon/swd_access_cpu0.rs new file mode 100644 index 000000000..0309aedc3 --- /dev/null +++ b/mcxa276-pac/src/syscon/swd_access_cpu0.rs @@ -0,0 +1,91 @@ +#[doc = "Register `SWD_ACCESS_CPU0` reader"] +pub type R = crate::R; +#[doc = "Register `SWD_ACCESS_CPU0` writer"] +pub type W = crate::W; +#[doc = "CPU0 SWD-AP: 0x12345678\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum SecCode { + #[doc = "0: CPU0 DAP is not allowed. Reading back register is read as 0x5."] + Disable = 0, + #[doc = "305419896: Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."] + Enable = 305419896, +} +impl From for u32 { + #[inline(always)] + fn from(variant: SecCode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SecCode { + type Ux = u32; +} +impl crate::IsEnum for SecCode {} +#[doc = "Field `SEC_CODE` reader - CPU0 SWD-AP: 0x12345678"] +pub type SecCodeR = crate::FieldReader; +impl SecCodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SecCode::Disable), + 305419896 => Some(SecCode::Enable), + _ => None, + } + } + #[doc = "CPU0 DAP is not allowed. Reading back register is read as 0x5."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SecCode::Disable + } + #[doc = "Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SecCode::Enable + } +} +#[doc = "Field `SEC_CODE` writer - CPU0 SWD-AP: 0x12345678"] +pub type SecCodeW<'a, REG> = crate::FieldWriter<'a, REG, 32, SecCode>; +impl<'a, REG> SecCodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CPU0 DAP is not allowed. Reading back register is read as 0x5."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(SecCode::Disable) + } + #[doc = "Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(SecCode::Enable) + } +} +impl R { + #[doc = "Bits 0:31 - CPU0 SWD-AP: 0x12345678"] + #[inline(always)] + pub fn sec_code(&self) -> SecCodeR { + SecCodeR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - CPU0 SWD-AP: 0x12345678"] + #[inline(always)] + pub fn sec_code(&mut self) -> SecCodeW { + SecCodeW::new(self, 0) + } +} +#[doc = "CPU0 Software Debug Access\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_access_cpu0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_access_cpu0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwdAccessCpu0Spec; +impl crate::RegisterSpec for SwdAccessCpu0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`swd_access_cpu0::R`](R) reader structure"] +impl crate::Readable for SwdAccessCpu0Spec {} +#[doc = "`write(|w| ..)` method takes [`swd_access_cpu0::W`](W) writer structure"] +impl crate::Writable for SwdAccessCpu0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SWD_ACCESS_CPU0 to value 0"] +impl crate::Resettable for SwdAccessCpu0Spec {} diff --git a/mcxa276-pac/src/tdet0.rs b/mcxa276-pac/src/tdet0.rs new file mode 100644 index 000000000..3715b0033 --- /dev/null +++ b/mcxa276-pac/src/tdet0.rs @@ -0,0 +1,103 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x10], + cr: Cr, + sr: Sr, + lr: Lr, + ier: Ier, + tsr: Tsr, + ter: Ter, + _reserved6: [u8; 0x04], + ppr: Ppr, + _reserved7: [u8; 0x10], + pgfr: [Pgfr; 6], +} +impl RegisterBlock { + #[doc = "0x10 - Control"] + #[inline(always)] + pub const fn cr(&self) -> &Cr { + &self.cr + } + #[doc = "0x14 - Status"] + #[inline(always)] + pub const fn sr(&self) -> &Sr { + &self.sr + } + #[doc = "0x18 - Lock"] + #[inline(always)] + pub const fn lr(&self) -> &Lr { + &self.lr + } + #[doc = "0x1c - Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &Ier { + &self.ier + } + #[doc = "0x20 - Tamper Seconds"] + #[inline(always)] + pub const fn tsr(&self) -> &Tsr { + &self.tsr + } + #[doc = "0x24 - Tamper Enable"] + #[inline(always)] + pub const fn ter(&self) -> &Ter { + &self.ter + } + #[doc = "0x2c - Pin Polarity"] + #[inline(always)] + pub const fn ppr(&self) -> &Ppr { + &self.ppr + } + #[doc = "0x40..0x58 - Pin Glitch Filter"] + #[inline(always)] + pub const fn pgfr(&self, n: usize) -> &Pgfr { + &self.pgfr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x40..0x58 - Pin Glitch Filter"] + #[inline(always)] + pub fn pgfr_iter(&self) -> impl Iterator { + self.pgfr.iter() + } +} +#[doc = "CR (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] +#[doc(alias = "CR")] +pub type Cr = crate::Reg; +#[doc = "Control"] +pub mod cr; +#[doc = "SR (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] +#[doc(alias = "SR")] +pub type Sr = crate::Reg; +#[doc = "Status"] +pub mod sr; +#[doc = "LR (rw) register accessor: Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lr`] module"] +#[doc(alias = "LR")] +pub type Lr = crate::Reg; +#[doc = "Lock"] +pub mod lr; +#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] +#[doc(alias = "IER")] +pub type Ier = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ier; +#[doc = "TSR (rw) register accessor: Tamper Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsr`] module"] +#[doc(alias = "TSR")] +pub type Tsr = crate::Reg; +#[doc = "Tamper Seconds"] +pub mod tsr; +#[doc = "TER (rw) register accessor: Tamper Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ter`] module"] +#[doc(alias = "TER")] +pub type Ter = crate::Reg; +#[doc = "Tamper Enable"] +pub mod ter; +#[doc = "PPR (rw) register accessor: Pin Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`ppr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ppr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppr`] module"] +#[doc(alias = "PPR")] +pub type Ppr = crate::Reg; +#[doc = "Pin Polarity"] +pub mod ppr; +#[doc = "PGFR (rw) register accessor: Pin Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`pgfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pgfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgfr`] module"] +#[doc(alias = "PGFR")] +pub type Pgfr = crate::Reg; +#[doc = "Pin Glitch Filter"] +pub mod pgfr; diff --git a/mcxa276-pac/src/tdet0/cr.rs b/mcxa276-pac/src/tdet0/cr.rs new file mode 100644 index 000000000..b5efa57d5 --- /dev/null +++ b/mcxa276-pac/src/tdet0/cr.rs @@ -0,0 +1,350 @@ +#[doc = "Register `CR` reader"] +pub type R = crate::R; +#[doc = "Register `CR` writer"] +pub type W = crate::W; +#[doc = "Software Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Swr { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Perform a software reset"] + SwReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Swr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SWR` reader - Software Reset"] +pub type SwrR = crate::BitReader; +impl SwrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Swr { + match self.bits { + false => Swr::NoEffect, + true => Swr::SwReset, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Swr::NoEffect + } + #[doc = "Perform a software reset"] + #[inline(always)] + pub fn is_sw_reset(&self) -> bool { + *self == Swr::SwReset + } +} +#[doc = "Field `SWR` writer - Software Reset"] +pub type SwrW<'a, REG> = crate::BitWriter<'a, REG, Swr>; +impl<'a, REG> SwrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Swr::NoEffect) + } + #[doc = "Perform a software reset"] + #[inline(always)] + pub fn sw_reset(self) -> &'a mut crate::W { + self.variant(Swr::SwReset) + } +} +#[doc = "Digital Tamper Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Den { + #[doc = "0: Disables TDET clock and prescaler"] + Disable = 0, + #[doc = "1: Enables TDET clock and prescaler"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Den) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DEN` reader - Digital Tamper Enable"] +pub type DenR = crate::BitReader; +impl DenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Den { + match self.bits { + false => Den::Disable, + true => Den::Enable, + } + } + #[doc = "Disables TDET clock and prescaler"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Den::Disable + } + #[doc = "Enables TDET clock and prescaler"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Den::Enable + } +} +#[doc = "Field `DEN` writer - Digital Tamper Enable"] +pub type DenW<'a, REG> = crate::BitWriter<'a, REG, Den>; +impl<'a, REG> DenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables TDET clock and prescaler"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Den::Disable) + } + #[doc = "Enables TDET clock and prescaler"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Den::Enable) + } +} +#[doc = "Tamper Force System Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tfsr { + #[doc = "0: Do not force chip reset"] + NoReset = 0, + #[doc = "1: Force chip reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tfsr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFSR` reader - Tamper Force System Reset"] +pub type TfsrR = crate::BitReader; +impl TfsrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tfsr { + match self.bits { + false => Tfsr::NoReset, + true => Tfsr::Reset, + } + } + #[doc = "Do not force chip reset"] + #[inline(always)] + pub fn is_no_reset(&self) -> bool { + *self == Tfsr::NoReset + } + #[doc = "Force chip reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Tfsr::Reset + } +} +#[doc = "Field `TFSR` writer - Tamper Force System Reset"] +pub type TfsrW<'a, REG> = crate::BitWriter<'a, REG, Tfsr>; +impl<'a, REG> TfsrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Do not force chip reset"] + #[inline(always)] + pub fn no_reset(self) -> &'a mut crate::W { + self.variant(Tfsr::NoReset) + } + #[doc = "Force chip reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Tfsr::Reset) + } +} +#[doc = "Update Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Um { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Allows the clearing of interrupts"] + ClearInts = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Um) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UM` reader - Update Mode"] +pub type UmR = crate::BitReader; +impl UmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Um { + match self.bits { + false => Um::NoEffect, + true => Um::ClearInts, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Um::NoEffect + } + #[doc = "Allows the clearing of interrupts"] + #[inline(always)] + pub fn is_clear_ints(&self) -> bool { + *self == Um::ClearInts + } +} +#[doc = "Field `UM` writer - Update Mode"] +pub type UmW<'a, REG> = crate::BitWriter<'a, REG, Um>; +impl<'a, REG> UmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Um::NoEffect) + } + #[doc = "Allows the clearing of interrupts"] + #[inline(always)] + pub fn clear_ints(self) -> &'a mut crate::W { + self.variant(Um::ClearInts) + } +} +#[doc = "Disable Prescaler On Tamper\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Distam { + #[doc = "0: No effect"] + NoEffect = 0, + #[doc = "1: Automatically disables the prescaler after tamper detection"] + AutoDis = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Distam) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DISTAM` reader - Disable Prescaler On Tamper"] +pub type DistamR = crate::BitReader; +impl DistamR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Distam { + match self.bits { + false => Distam::NoEffect, + true => Distam::AutoDis, + } + } + #[doc = "No effect"] + #[inline(always)] + pub fn is_no_effect(&self) -> bool { + *self == Distam::NoEffect + } + #[doc = "Automatically disables the prescaler after tamper detection"] + #[inline(always)] + pub fn is_auto_dis(&self) -> bool { + *self == Distam::AutoDis + } +} +#[doc = "Field `DISTAM` writer - Disable Prescaler On Tamper"] +pub type DistamW<'a, REG> = crate::BitWriter<'a, REG, Distam>; +impl<'a, REG> DistamW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect"] + #[inline(always)] + pub fn no_effect(self) -> &'a mut crate::W { + self.variant(Distam::NoEffect) + } + #[doc = "Automatically disables the prescaler after tamper detection"] + #[inline(always)] + pub fn auto_dis(self) -> &'a mut crate::W { + self.variant(Distam::AutoDis) + } +} +#[doc = "Field `DPR` reader - Digital Tamper Prescaler"] +pub type DprR = crate::FieldReader; +#[doc = "Field `DPR` writer - Digital Tamper Prescaler"] +pub type DprW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swr(&self) -> SwrR { + SwrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Digital Tamper Enable"] + #[inline(always)] + pub fn den(&self) -> DenR { + DenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Tamper Force System Reset"] + #[inline(always)] + pub fn tfsr(&self) -> TfsrR { + TfsrR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Update Mode"] + #[inline(always)] + pub fn um(&self) -> UmR { + UmR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Disable Prescaler On Tamper"] + #[inline(always)] + pub fn distam(&self) -> DistamR { + DistamR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 17:31 - Digital Tamper Prescaler"] + #[inline(always)] + pub fn dpr(&self) -> DprR { + DprR::new(((self.bits >> 17) & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swr(&mut self) -> SwrW { + SwrW::new(self, 0) + } + #[doc = "Bit 1 - Digital Tamper Enable"] + #[inline(always)] + pub fn den(&mut self) -> DenW { + DenW::new(self, 1) + } + #[doc = "Bit 2 - Tamper Force System Reset"] + #[inline(always)] + pub fn tfsr(&mut self) -> TfsrW { + TfsrW::new(self, 2) + } + #[doc = "Bit 3 - Update Mode"] + #[inline(always)] + pub fn um(&mut self) -> UmW { + UmW::new(self, 3) + } + #[doc = "Bit 8 - Disable Prescaler On Tamper"] + #[inline(always)] + pub fn distam(&mut self) -> DistamW { + DistamW::new(self, 8) + } + #[doc = "Bits 17:31 - Digital Tamper Prescaler"] + #[inline(always)] + pub fn dpr(&mut self) -> DprW { + DprW::new(self, 17) + } +} +#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrSpec; +impl crate::RegisterSpec for CrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CrSpec {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] +impl crate::Writable for CrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CR to value 0"] +impl crate::Resettable for CrSpec {} diff --git a/mcxa276-pac/src/tdet0/ier.rs b/mcxa276-pac/src/tdet0/ier.rs new file mode 100644 index 000000000..6ec2a8bb6 --- /dev/null +++ b/mcxa276-pac/src/tdet0/ier.rs @@ -0,0 +1,1155 @@ +#[doc = "Register `IER` reader"] +pub type R = crate::R; +#[doc = "Register `IER` writer"] +pub type W = crate::W; +#[doc = "Digital Tamper Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dtie { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dtie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DTIE` reader - Digital Tamper Interrupt Enable"] +pub type DtieR = crate::BitReader; +impl DtieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dtie { + match self.bits { + false => Dtie::Disable, + true => Dtie::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Dtie::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Dtie::Enable + } +} +#[doc = "Field `DTIE` writer - Digital Tamper Interrupt Enable"] +pub type DtieW<'a, REG> = crate::BitWriter<'a, REG, Dtie>; +impl<'a, REG> DtieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Dtie::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Dtie::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie0 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE0` reader - Tamper Input n Interrupt Enable"] +pub type Tiie0R = crate::BitReader; +impl Tiie0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie0 { + match self.bits { + false => Tiie0::Disable, + true => Tiie0::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie0::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie0::Enable + } +} +#[doc = "Field `TIIE0` writer - Tamper Input n Interrupt Enable"] +pub type Tiie0W<'a, REG> = crate::BitWriter<'a, REG, Tiie0>; +impl<'a, REG> Tiie0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie0::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie0::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie1 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE1` reader - Tamper Input n Interrupt Enable"] +pub type Tiie1R = crate::BitReader; +impl Tiie1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie1 { + match self.bits { + false => Tiie1::Disable, + true => Tiie1::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie1::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie1::Enable + } +} +#[doc = "Field `TIIE1` writer - Tamper Input n Interrupt Enable"] +pub type Tiie1W<'a, REG> = crate::BitWriter<'a, REG, Tiie1>; +impl<'a, REG> Tiie1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie1::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie1::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie2 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE2` reader - Tamper Input n Interrupt Enable"] +pub type Tiie2R = crate::BitReader; +impl Tiie2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie2 { + match self.bits { + false => Tiie2::Disable, + true => Tiie2::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie2::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie2::Enable + } +} +#[doc = "Field `TIIE2` writer - Tamper Input n Interrupt Enable"] +pub type Tiie2W<'a, REG> = crate::BitWriter<'a, REG, Tiie2>; +impl<'a, REG> Tiie2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie2::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie2::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie3 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE3` reader - Tamper Input n Interrupt Enable"] +pub type Tiie3R = crate::BitReader; +impl Tiie3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie3 { + match self.bits { + false => Tiie3::Disable, + true => Tiie3::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie3::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie3::Enable + } +} +#[doc = "Field `TIIE3` writer - Tamper Input n Interrupt Enable"] +pub type Tiie3W<'a, REG> = crate::BitWriter<'a, REG, Tiie3>; +impl<'a, REG> Tiie3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie3::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie3::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie4 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE4` reader - Tamper Input n Interrupt Enable"] +pub type Tiie4R = crate::BitReader; +impl Tiie4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie4 { + match self.bits { + false => Tiie4::Disable, + true => Tiie4::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie4::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie4::Enable + } +} +#[doc = "Field `TIIE4` writer - Tamper Input n Interrupt Enable"] +pub type Tiie4W<'a, REG> = crate::BitWriter<'a, REG, Tiie4>; +impl<'a, REG> Tiie4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie4::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie4::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie5 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE5` reader - Tamper Input n Interrupt Enable"] +pub type Tiie5R = crate::BitReader; +impl Tiie5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie5 { + match self.bits { + false => Tiie5::Disable, + true => Tiie5::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie5::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie5::Enable + } +} +#[doc = "Field `TIIE5` writer - Tamper Input n Interrupt Enable"] +pub type Tiie5W<'a, REG> = crate::BitWriter<'a, REG, Tiie5>; +impl<'a, REG> Tiie5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie5::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie5::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie6 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE6` reader - Tamper Input n Interrupt Enable"] +pub type Tiie6R = crate::BitReader; +impl Tiie6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie6 { + match self.bits { + false => Tiie6::Disable, + true => Tiie6::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie6::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie6::Enable + } +} +#[doc = "Field `TIIE6` writer - Tamper Input n Interrupt Enable"] +pub type Tiie6W<'a, REG> = crate::BitWriter<'a, REG, Tiie6>; +impl<'a, REG> Tiie6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie6::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie6::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie7 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE7` reader - Tamper Input n Interrupt Enable"] +pub type Tiie7R = crate::BitReader; +impl Tiie7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie7 { + match self.bits { + false => Tiie7::Disable, + true => Tiie7::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie7::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie7::Enable + } +} +#[doc = "Field `TIIE7` writer - Tamper Input n Interrupt Enable"] +pub type Tiie7W<'a, REG> = crate::BitWriter<'a, REG, Tiie7>; +impl<'a, REG> Tiie7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie7::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie7::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie8 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE8` reader - Tamper Input n Interrupt Enable"] +pub type Tiie8R = crate::BitReader; +impl Tiie8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie8 { + match self.bits { + false => Tiie8::Disable, + true => Tiie8::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie8::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie8::Enable + } +} +#[doc = "Field `TIIE8` writer - Tamper Input n Interrupt Enable"] +pub type Tiie8W<'a, REG> = crate::BitWriter<'a, REG, Tiie8>; +impl<'a, REG> Tiie8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie8::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie8::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie9 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE9` reader - Tamper Input n Interrupt Enable"] +pub type Tiie9R = crate::BitReader; +impl Tiie9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie9 { + match self.bits { + false => Tiie9::Disable, + true => Tiie9::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie9::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie9::Enable + } +} +#[doc = "Field `TIIE9` writer - Tamper Input n Interrupt Enable"] +pub type Tiie9W<'a, REG> = crate::BitWriter<'a, REG, Tiie9>; +impl<'a, REG> Tiie9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie9::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie9::Enable) + } +} +#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tiie10 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tiie10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIIE10` reader - Tamper Input n Interrupt Enable"] +pub type Tiie10R = crate::BitReader; +impl Tiie10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tiie10 { + match self.bits { + false => Tiie10::Disable, + true => Tiie10::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tiie10::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tiie10::Enable + } +} +#[doc = "Field `TIIE10` writer - Tamper Input n Interrupt Enable"] +pub type Tiie10W<'a, REG> = crate::BitWriter<'a, REG, Tiie10>; +impl<'a, REG> Tiie10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tiie10::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tiie10::Enable) + } +} +#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpie0 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpie0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPIE0` reader - Tamper Pin n Interrupt Enable"] +pub type Tpie0R = crate::BitReader; +impl Tpie0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpie0 { + match self.bits { + false => Tpie0::Disable, + true => Tpie0::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpie0::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpie0::Enable + } +} +#[doc = "Field `TPIE0` writer - Tamper Pin n Interrupt Enable"] +pub type Tpie0W<'a, REG> = crate::BitWriter<'a, REG, Tpie0>; +impl<'a, REG> Tpie0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpie0::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpie0::Enable) + } +} +#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpie1 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpie1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPIE1` reader - Tamper Pin n Interrupt Enable"] +pub type Tpie1R = crate::BitReader; +impl Tpie1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpie1 { + match self.bits { + false => Tpie1::Disable, + true => Tpie1::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpie1::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpie1::Enable + } +} +#[doc = "Field `TPIE1` writer - Tamper Pin n Interrupt Enable"] +pub type Tpie1W<'a, REG> = crate::BitWriter<'a, REG, Tpie1>; +impl<'a, REG> Tpie1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpie1::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpie1::Enable) + } +} +#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpie2 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpie2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPIE2` reader - Tamper Pin n Interrupt Enable"] +pub type Tpie2R = crate::BitReader; +impl Tpie2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpie2 { + match self.bits { + false => Tpie2::Disable, + true => Tpie2::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpie2::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpie2::Enable + } +} +#[doc = "Field `TPIE2` writer - Tamper Pin n Interrupt Enable"] +pub type Tpie2W<'a, REG> = crate::BitWriter<'a, REG, Tpie2>; +impl<'a, REG> Tpie2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpie2::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpie2::Enable) + } +} +#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpie3 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpie3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPIE3` reader - Tamper Pin n Interrupt Enable"] +pub type Tpie3R = crate::BitReader; +impl Tpie3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpie3 { + match self.bits { + false => Tpie3::Disable, + true => Tpie3::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpie3::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpie3::Enable + } +} +#[doc = "Field `TPIE3` writer - Tamper Pin n Interrupt Enable"] +pub type Tpie3W<'a, REG> = crate::BitWriter<'a, REG, Tpie3>; +impl<'a, REG> Tpie3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpie3::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpie3::Enable) + } +} +#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpie4 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpie4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPIE4` reader - Tamper Pin n Interrupt Enable"] +pub type Tpie4R = crate::BitReader; +impl Tpie4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpie4 { + match self.bits { + false => Tpie4::Disable, + true => Tpie4::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpie4::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpie4::Enable + } +} +#[doc = "Field `TPIE4` writer - Tamper Pin n Interrupt Enable"] +pub type Tpie4W<'a, REG> = crate::BitWriter<'a, REG, Tpie4>; +impl<'a, REG> Tpie4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpie4::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpie4::Enable) + } +} +#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpie5 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpie5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPIE5` reader - Tamper Pin n Interrupt Enable"] +pub type Tpie5R = crate::BitReader; +impl Tpie5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpie5 { + match self.bits { + false => Tpie5::Disable, + true => Tpie5::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpie5::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpie5::Enable + } +} +#[doc = "Field `TPIE5` writer - Tamper Pin n Interrupt Enable"] +pub type Tpie5W<'a, REG> = crate::BitWriter<'a, REG, Tpie5>; +impl<'a, REG> Tpie5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpie5::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpie5::Enable) + } +} +impl R { + #[doc = "Bit 0 - Digital Tamper Interrupt Enable"] + #[inline(always)] + pub fn dtie(&self) -> DtieR { + DtieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie0(&self) -> Tiie0R { + Tiie0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie1(&self) -> Tiie1R { + Tiie1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie2(&self) -> Tiie2R { + Tiie2R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie3(&self) -> Tiie3R { + Tiie3R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie4(&self) -> Tiie4R { + Tiie4R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie5(&self) -> Tiie5R { + Tiie5R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie6(&self) -> Tiie6R { + Tiie6R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie7(&self) -> Tiie7R { + Tiie7R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie8(&self) -> Tiie8R { + Tiie8R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie9(&self) -> Tiie9R { + Tiie9R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie10(&self) -> Tiie10R { + Tiie10R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie0(&self) -> Tpie0R { + Tpie0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie1(&self) -> Tpie1R { + Tpie1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie2(&self) -> Tpie2R { + Tpie2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie3(&self) -> Tpie3R { + Tpie3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie4(&self) -> Tpie4R { + Tpie4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie5(&self) -> Tpie5R { + Tpie5R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Digital Tamper Interrupt Enable"] + #[inline(always)] + pub fn dtie(&mut self) -> DtieW { + DtieW::new(self, 0) + } + #[doc = "Bit 2 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie0(&mut self) -> Tiie0W { + Tiie0W::new(self, 2) + } + #[doc = "Bit 3 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie1(&mut self) -> Tiie1W { + Tiie1W::new(self, 3) + } + #[doc = "Bit 4 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie2(&mut self) -> Tiie2W { + Tiie2W::new(self, 4) + } + #[doc = "Bit 5 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie3(&mut self) -> Tiie3W { + Tiie3W::new(self, 5) + } + #[doc = "Bit 6 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie4(&mut self) -> Tiie4W { + Tiie4W::new(self, 6) + } + #[doc = "Bit 7 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie5(&mut self) -> Tiie5W { + Tiie5W::new(self, 7) + } + #[doc = "Bit 8 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie6(&mut self) -> Tiie6W { + Tiie6W::new(self, 8) + } + #[doc = "Bit 9 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie7(&mut self) -> Tiie7W { + Tiie7W::new(self, 9) + } + #[doc = "Bit 10 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie8(&mut self) -> Tiie8W { + Tiie8W::new(self, 10) + } + #[doc = "Bit 11 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie9(&mut self) -> Tiie9W { + Tiie9W::new(self, 11) + } + #[doc = "Bit 12 - Tamper Input n Interrupt Enable"] + #[inline(always)] + pub fn tiie10(&mut self) -> Tiie10W { + Tiie10W::new(self, 12) + } + #[doc = "Bit 16 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie0(&mut self) -> Tpie0W { + Tpie0W::new(self, 16) + } + #[doc = "Bit 17 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie1(&mut self) -> Tpie1W { + Tpie1W::new(self, 17) + } + #[doc = "Bit 18 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie2(&mut self) -> Tpie2W { + Tpie2W::new(self, 18) + } + #[doc = "Bit 19 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie3(&mut self) -> Tpie3W { + Tpie3W::new(self, 19) + } + #[doc = "Bit 20 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie4(&mut self) -> Tpie4W { + Tpie4W::new(self, 20) + } + #[doc = "Bit 21 - Tamper Pin n Interrupt Enable"] + #[inline(always)] + pub fn tpie5(&mut self) -> Tpie5W { + Tpie5W::new(self, 21) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IerSpec; +impl crate::RegisterSpec for IerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IerSpec {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] +impl crate::Writable for IerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/tdet0/lr.rs b/mcxa276-pac/src/tdet0/lr.rs new file mode 100644 index 000000000..3e100f663 --- /dev/null +++ b/mcxa276-pac/src/tdet0/lr.rs @@ -0,0 +1,842 @@ +#[doc = "Register `LR` reader"] +pub type R = crate::R; +#[doc = "Register `LR` writer"] +pub type W = crate::W; +#[doc = "Control Register Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crl { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRL` reader - Control Register Lock"] +pub type CrlR = crate::BitReader; +impl CrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crl { + match self.bits { + false => Crl::Lock, + true => Crl::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Crl::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Crl::NotLock + } +} +#[doc = "Field `CRL` writer - Control Register Lock"] +pub type CrlW<'a, REG> = crate::BitWriter<'a, REG, Crl>; +impl<'a, REG> CrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Crl::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Crl::NotLock) + } +} +#[doc = "Status Register Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Srl { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Srl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRL` reader - Status Register Lock"] +pub type SrlR = crate::BitReader; +impl SrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Srl { + match self.bits { + false => Srl::Lock, + true => Srl::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Srl::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Srl::NotLock + } +} +#[doc = "Field `SRL` writer - Status Register Lock"] +pub type SrlW<'a, REG> = crate::BitWriter<'a, REG, Srl>; +impl<'a, REG> SrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Srl::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Srl::NotLock) + } +} +#[doc = "Lock Register Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lrl { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lrl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LRL` reader - Lock Register Lock"] +pub type LrlR = crate::BitReader; +impl LrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lrl { + match self.bits { + false => Lrl::Lock, + true => Lrl::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Lrl::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Lrl::NotLock + } +} +#[doc = "Field `LRL` writer - Lock Register Lock"] +pub type LrlW<'a, REG> = crate::BitWriter<'a, REG, Lrl>; +impl<'a, REG> LrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Lrl::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Lrl::NotLock) + } +} +#[doc = "Interrupt Enable Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Iel { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Iel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IEL` reader - Interrupt Enable Lock"] +pub type IelR = crate::BitReader; +impl IelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Iel { + match self.bits { + false => Iel::Lock, + true => Iel::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Iel::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Iel::NotLock + } +} +#[doc = "Field `IEL` writer - Interrupt Enable Lock"] +pub type IelW<'a, REG> = crate::BitWriter<'a, REG, Iel>; +impl<'a, REG> IelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Iel::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Iel::NotLock) + } +} +#[doc = "Tamper Seconds Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tsl { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tsl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TSL` reader - Tamper Seconds Lock"] +pub type TslR = crate::BitReader; +impl TslR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tsl { + match self.bits { + false => Tsl::Lock, + true => Tsl::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Tsl::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Tsl::NotLock + } +} +#[doc = "Field `TSL` writer - Tamper Seconds Lock"] +pub type TslW<'a, REG> = crate::BitWriter<'a, REG, Tsl>; +impl<'a, REG> TslW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Tsl::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Tsl::NotLock) + } +} +#[doc = "Tamper Enable Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tel { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEL` reader - Tamper Enable Lock"] +pub type TelR = crate::BitReader; +impl TelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tel { + match self.bits { + false => Tel::Lock, + true => Tel::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Tel::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Tel::NotLock + } +} +#[doc = "Field `TEL` writer - Tamper Enable Lock"] +pub type TelW<'a, REG> = crate::BitWriter<'a, REG, Tel>; +impl<'a, REG> TelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Tel::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Tel::NotLock) + } +} +#[doc = "Pin Polarity Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ppl { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ppl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PPL` reader - Pin Polarity Lock"] +pub type PplR = crate::BitReader; +impl PplR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ppl { + match self.bits { + false => Ppl::Lock, + true => Ppl::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Ppl::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Ppl::NotLock + } +} +#[doc = "Field `PPL` writer - Pin Polarity Lock"] +pub type PplW<'a, REG> = crate::BitWriter<'a, REG, Ppl>; +impl<'a, REG> PplW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Ppl::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Ppl::NotLock) + } +} +#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfl0 { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfl0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFL0` reader - Glitch Filter Lock"] +pub type Gfl0R = crate::BitReader; +impl Gfl0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfl0 { + match self.bits { + false => Gfl0::Lock, + true => Gfl0::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Gfl0::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Gfl0::NotLock + } +} +#[doc = "Field `GFL0` writer - Glitch Filter Lock"] +pub type Gfl0W<'a, REG> = crate::BitWriter<'a, REG, Gfl0>; +impl<'a, REG> Gfl0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Gfl0::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Gfl0::NotLock) + } +} +#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfl1 { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfl1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFL1` reader - Glitch Filter Lock"] +pub type Gfl1R = crate::BitReader; +impl Gfl1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfl1 { + match self.bits { + false => Gfl1::Lock, + true => Gfl1::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Gfl1::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Gfl1::NotLock + } +} +#[doc = "Field `GFL1` writer - Glitch Filter Lock"] +pub type Gfl1W<'a, REG> = crate::BitWriter<'a, REG, Gfl1>; +impl<'a, REG> Gfl1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Gfl1::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Gfl1::NotLock) + } +} +#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfl2 { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfl2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFL2` reader - Glitch Filter Lock"] +pub type Gfl2R = crate::BitReader; +impl Gfl2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfl2 { + match self.bits { + false => Gfl2::Lock, + true => Gfl2::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Gfl2::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Gfl2::NotLock + } +} +#[doc = "Field `GFL2` writer - Glitch Filter Lock"] +pub type Gfl2W<'a, REG> = crate::BitWriter<'a, REG, Gfl2>; +impl<'a, REG> Gfl2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Gfl2::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Gfl2::NotLock) + } +} +#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfl3 { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfl3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFL3` reader - Glitch Filter Lock"] +pub type Gfl3R = crate::BitReader; +impl Gfl3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfl3 { + match self.bits { + false => Gfl3::Lock, + true => Gfl3::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Gfl3::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Gfl3::NotLock + } +} +#[doc = "Field `GFL3` writer - Glitch Filter Lock"] +pub type Gfl3W<'a, REG> = crate::BitWriter<'a, REG, Gfl3>; +impl<'a, REG> Gfl3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Gfl3::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Gfl3::NotLock) + } +} +#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfl4 { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfl4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFL4` reader - Glitch Filter Lock"] +pub type Gfl4R = crate::BitReader; +impl Gfl4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfl4 { + match self.bits { + false => Gfl4::Lock, + true => Gfl4::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Gfl4::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Gfl4::NotLock + } +} +#[doc = "Field `GFL4` writer - Glitch Filter Lock"] +pub type Gfl4W<'a, REG> = crate::BitWriter<'a, REG, Gfl4>; +impl<'a, REG> Gfl4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Gfl4::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Gfl4::NotLock) + } +} +#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfl5 { + #[doc = "0: Locked and writes are ignored"] + Lock = 0, + #[doc = "1: Not locked and writes complete as normal"] + NotLock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfl5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFL5` reader - Glitch Filter Lock"] +pub type Gfl5R = crate::BitReader; +impl Gfl5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfl5 { + match self.bits { + false => Gfl5::Lock, + true => Gfl5::NotLock, + } + } + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Gfl5::Lock + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn is_not_lock(&self) -> bool { + *self == Gfl5::NotLock + } +} +#[doc = "Field `GFL5` writer - Glitch Filter Lock"] +pub type Gfl5W<'a, REG> = crate::BitWriter<'a, REG, Gfl5>; +impl<'a, REG> Gfl5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Locked and writes are ignored"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Gfl5::Lock) + } + #[doc = "Not locked and writes complete as normal"] + #[inline(always)] + pub fn not_lock(self) -> &'a mut crate::W { + self.variant(Gfl5::NotLock) + } +} +impl R { + #[doc = "Bit 4 - Control Register Lock"] + #[inline(always)] + pub fn crl(&self) -> CrlR { + CrlR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Status Register Lock"] + #[inline(always)] + pub fn srl(&self) -> SrlR { + SrlR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Lock Register Lock"] + #[inline(always)] + pub fn lrl(&self) -> LrlR { + LrlR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt Enable Lock"] + #[inline(always)] + pub fn iel(&self) -> IelR { + IelR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Tamper Seconds Lock"] + #[inline(always)] + pub fn tsl(&self) -> TslR { + TslR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Tamper Enable Lock"] + #[inline(always)] + pub fn tel(&self) -> TelR { + TelR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Pin Polarity Lock"] + #[inline(always)] + pub fn ppl(&self) -> PplR { + PplR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl0(&self) -> Gfl0R { + Gfl0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl1(&self) -> Gfl1R { + Gfl1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl2(&self) -> Gfl2R { + Gfl2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl3(&self) -> Gfl3R { + Gfl3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl4(&self) -> Gfl4R { + Gfl4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl5(&self) -> Gfl5R { + Gfl5R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - Control Register Lock"] + #[inline(always)] + pub fn crl(&mut self) -> CrlW { + CrlW::new(self, 4) + } + #[doc = "Bit 5 - Status Register Lock"] + #[inline(always)] + pub fn srl(&mut self) -> SrlW { + SrlW::new(self, 5) + } + #[doc = "Bit 6 - Lock Register Lock"] + #[inline(always)] + pub fn lrl(&mut self) -> LrlW { + LrlW::new(self, 6) + } + #[doc = "Bit 7 - Interrupt Enable Lock"] + #[inline(always)] + pub fn iel(&mut self) -> IelW { + IelW::new(self, 7) + } + #[doc = "Bit 8 - Tamper Seconds Lock"] + #[inline(always)] + pub fn tsl(&mut self) -> TslW { + TslW::new(self, 8) + } + #[doc = "Bit 9 - Tamper Enable Lock"] + #[inline(always)] + pub fn tel(&mut self) -> TelW { + TelW::new(self, 9) + } + #[doc = "Bit 11 - Pin Polarity Lock"] + #[inline(always)] + pub fn ppl(&mut self) -> PplW { + PplW::new(self, 11) + } + #[doc = "Bit 16 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl0(&mut self) -> Gfl0W { + Gfl0W::new(self, 16) + } + #[doc = "Bit 17 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl1(&mut self) -> Gfl1W { + Gfl1W::new(self, 17) + } + #[doc = "Bit 18 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl2(&mut self) -> Gfl2W { + Gfl2W::new(self, 18) + } + #[doc = "Bit 19 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl3(&mut self) -> Gfl3W { + Gfl3W::new(self, 19) + } + #[doc = "Bit 20 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl4(&mut self) -> Gfl4W { + Gfl4W::new(self, 20) + } + #[doc = "Bit 21 - Glitch Filter Lock"] + #[inline(always)] + pub fn gfl5(&mut self) -> Gfl5W { + Gfl5W::new(self, 21) + } +} +#[doc = "Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LrSpec; +impl crate::RegisterSpec for LrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lr::R`](R) reader structure"] +impl crate::Readable for LrSpec {} +#[doc = "`write(|w| ..)` method takes [`lr::W`](W) writer structure"] +impl crate::Writable for LrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LR to value 0x003f_0bf0"] +impl crate::Resettable for LrSpec { + const RESET_VALUE: u32 = 0x003f_0bf0; +} diff --git a/mcxa276-pac/src/tdet0/pgfr.rs b/mcxa276-pac/src/tdet0/pgfr.rs new file mode 100644 index 000000000..8b6f5448c --- /dev/null +++ b/mcxa276-pac/src/tdet0/pgfr.rs @@ -0,0 +1,668 @@ +#[doc = "Register `PGFR[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `PGFR[%s]` writer"] +pub type W = crate::W; +#[doc = "Field `GFW` reader - Glitch Filter Width"] +pub type GfwR = crate::FieldReader; +#[doc = "Field `GFW` writer - Glitch Filter Width"] +pub type GfwW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Glitch Filter Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfp { + #[doc = "0: 512 Hz prescaler clock"] + Freq512Hz = 0, + #[doc = "1: 32.768 kHz clock"] + Freq32Khz = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFP` reader - Glitch Filter Prescaler"] +pub type GfpR = crate::BitReader; +impl GfpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfp { + match self.bits { + false => Gfp::Freq512Hz, + true => Gfp::Freq32Khz, + } + } + #[doc = "512 Hz prescaler clock"] + #[inline(always)] + pub fn is_freq_512_hz(&self) -> bool { + *self == Gfp::Freq512Hz + } + #[doc = "32.768 kHz clock"] + #[inline(always)] + pub fn is_freq_32_khz(&self) -> bool { + *self == Gfp::Freq32Khz + } +} +#[doc = "Field `GFP` writer - Glitch Filter Prescaler"] +pub type GfpW<'a, REG> = crate::BitWriter<'a, REG, Gfp>; +impl<'a, REG> GfpW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "512 Hz prescaler clock"] + #[inline(always)] + pub fn freq_512_hz(self) -> &'a mut crate::W { + self.variant(Gfp::Freq512Hz) + } + #[doc = "32.768 kHz clock"] + #[inline(always)] + pub fn freq_32_khz(self) -> &'a mut crate::W { + self.variant(Gfp::Freq32Khz) + } +} +#[doc = "Glitch Filter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gfe { + #[doc = "0: Bypasses"] + Bypass = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GFE` reader - Glitch Filter Enable"] +pub type GfeR = crate::BitReader; +impl GfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gfe { + match self.bits { + false => Gfe::Bypass, + true => Gfe::Enable, + } + } + #[doc = "Bypasses"] + #[inline(always)] + pub fn is_bypass(&self) -> bool { + *self == Gfe::Bypass + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Gfe::Enable + } +} +#[doc = "Field `GFE` writer - Glitch Filter Enable"] +pub type GfeW<'a, REG> = crate::BitWriter<'a, REG, Gfe>; +impl<'a, REG> GfeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Bypasses"] + #[inline(always)] + pub fn bypass(self) -> &'a mut crate::W { + self.variant(Gfe::Bypass) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Gfe::Enable) + } +} +#[doc = "Tamper Pin Sample Width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tpsw { + #[doc = "0: Continuous monitoring, pin sampling disabled"] + Disable = 0, + #[doc = "1: 2 cycles for pull enable and 1 cycle for input buffer enable"] + Cycles2 = 1, + #[doc = "2: 4 cycles for pull enable and 2 cycles for input buffer enable"] + Cycles4 = 2, + #[doc = "3: 8 cycles for pull enable and 4 cycles for input buffer enable"] + Cycles8 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tpsw) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tpsw { + type Ux = u8; +} +impl crate::IsEnum for Tpsw {} +#[doc = "Field `TPSW` reader - Tamper Pin Sample Width"] +pub type TpswR = crate::FieldReader; +impl TpswR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpsw { + match self.bits { + 0 => Tpsw::Disable, + 1 => Tpsw::Cycles2, + 2 => Tpsw::Cycles4, + 3 => Tpsw::Cycles8, + _ => unreachable!(), + } + } + #[doc = "Continuous monitoring, pin sampling disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpsw::Disable + } + #[doc = "2 cycles for pull enable and 1 cycle for input buffer enable"] + #[inline(always)] + pub fn is_cycles_2(&self) -> bool { + *self == Tpsw::Cycles2 + } + #[doc = "4 cycles for pull enable and 2 cycles for input buffer enable"] + #[inline(always)] + pub fn is_cycles_4(&self) -> bool { + *self == Tpsw::Cycles4 + } + #[doc = "8 cycles for pull enable and 4 cycles for input buffer enable"] + #[inline(always)] + pub fn is_cycles_8(&self) -> bool { + *self == Tpsw::Cycles8 + } +} +#[doc = "Field `TPSW` writer - Tamper Pin Sample Width"] +pub type TpswW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tpsw, crate::Safe>; +impl<'a, REG> TpswW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Continuous monitoring, pin sampling disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpsw::Disable) + } + #[doc = "2 cycles for pull enable and 1 cycle for input buffer enable"] + #[inline(always)] + pub fn cycles_2(self) -> &'a mut crate::W { + self.variant(Tpsw::Cycles2) + } + #[doc = "4 cycles for pull enable and 2 cycles for input buffer enable"] + #[inline(always)] + pub fn cycles_4(self) -> &'a mut crate::W { + self.variant(Tpsw::Cycles4) + } + #[doc = "8 cycles for pull enable and 4 cycles for input buffer enable"] + #[inline(always)] + pub fn cycles_8(self) -> &'a mut crate::W { + self.variant(Tpsw::Cycles8) + } +} +#[doc = "Tamper Pin Sample Frequency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tpsf { + #[doc = "0: Every 8 cycles"] + Cycles8 = 0, + #[doc = "1: Every 32 cycles"] + Cycles32 = 1, + #[doc = "2: Every 128 cycles"] + Cycles128 = 2, + #[doc = "3: Every 512 cycles"] + Cycles512 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tpsf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tpsf { + type Ux = u8; +} +impl crate::IsEnum for Tpsf {} +#[doc = "Field `TPSF` reader - Tamper Pin Sample Frequency"] +pub type TpsfR = crate::FieldReader; +impl TpsfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpsf { + match self.bits { + 0 => Tpsf::Cycles8, + 1 => Tpsf::Cycles32, + 2 => Tpsf::Cycles128, + 3 => Tpsf::Cycles512, + _ => unreachable!(), + } + } + #[doc = "Every 8 cycles"] + #[inline(always)] + pub fn is_cycles_8(&self) -> bool { + *self == Tpsf::Cycles8 + } + #[doc = "Every 32 cycles"] + #[inline(always)] + pub fn is_cycles_32(&self) -> bool { + *self == Tpsf::Cycles32 + } + #[doc = "Every 128 cycles"] + #[inline(always)] + pub fn is_cycles_128(&self) -> bool { + *self == Tpsf::Cycles128 + } + #[doc = "Every 512 cycles"] + #[inline(always)] + pub fn is_cycles_512(&self) -> bool { + *self == Tpsf::Cycles512 + } +} +#[doc = "Field `TPSF` writer - Tamper Pin Sample Frequency"] +pub type TpsfW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tpsf, crate::Safe>; +impl<'a, REG> TpsfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Every 8 cycles"] + #[inline(always)] + pub fn cycles_8(self) -> &'a mut crate::W { + self.variant(Tpsf::Cycles8) + } + #[doc = "Every 32 cycles"] + #[inline(always)] + pub fn cycles_32(self) -> &'a mut crate::W { + self.variant(Tpsf::Cycles32) + } + #[doc = "Every 128 cycles"] + #[inline(always)] + pub fn cycles_128(self) -> &'a mut crate::W { + self.variant(Tpsf::Cycles128) + } + #[doc = "Every 512 cycles"] + #[inline(always)] + pub fn cycles_512(self) -> &'a mut crate::W { + self.variant(Tpsf::Cycles512) + } +} +#[doc = "Tamper Pull Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpe { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPE` reader - Tamper Pull Enable"] +pub type TpeR = crate::BitReader; +impl TpeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpe { + match self.bits { + false => Tpe::Disable, + true => Tpe::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpe::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpe::Enable + } +} +#[doc = "Field `TPE` writer - Tamper Pull Enable"] +pub type TpeW<'a, REG> = crate::BitWriter<'a, REG, Tpe>; +impl<'a, REG> TpeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpe::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpe::Enable) + } +} +#[doc = "Tamper Pull Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tps { + #[doc = "0: Asserts"] + Assert = 0, + #[doc = "1: Negates"] + Negate = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tps) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPS` reader - Tamper Pull Select"] +pub type TpsR = crate::BitReader; +impl TpsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tps { + match self.bits { + false => Tps::Assert, + true => Tps::Negate, + } + } + #[doc = "Asserts"] + #[inline(always)] + pub fn is_assert(&self) -> bool { + *self == Tps::Assert + } + #[doc = "Negates"] + #[inline(always)] + pub fn is_negate(&self) -> bool { + *self == Tps::Negate + } +} +#[doc = "Field `TPS` writer - Tamper Pull Select"] +pub type TpsW<'a, REG> = crate::BitWriter<'a, REG, Tps>; +impl<'a, REG> TpsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Asserts"] + #[inline(always)] + pub fn assert(self) -> &'a mut crate::W { + self.variant(Tps::Assert) + } + #[doc = "Negates"] + #[inline(always)] + pub fn negate(self) -> &'a mut crate::W { + self.variant(Tps::Negate) + } +} +#[doc = "Tamper Pull Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpv { + #[doc = "0: Low"] + Low = 0, + #[doc = "1: High"] + High = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPV` reader - Tamper Pull Value"] +pub type TpvR = crate::BitReader; +impl TpvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpv { + match self.bits { + false => Tpv::Low, + true => Tpv::High, + } + } + #[doc = "Low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == Tpv::Low + } + #[doc = "High"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == Tpv::High + } +} +#[doc = "Field `TPV` writer - Tamper Pull Value"] +pub type TpvW<'a, REG> = crate::BitWriter<'a, REG, Tpv>; +impl<'a, REG> TpvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(Tpv::Low) + } + #[doc = "High"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(Tpv::High) + } +} +#[doc = "Tamper Passive Filter\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpf { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPF` reader - Tamper Passive Filter"] +pub type TpfR = crate::BitReader; +impl TpfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpf { + match self.bits { + false => Tpf::Disable, + true => Tpf::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpf::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpf::Enable + } +} +#[doc = "Field `TPF` writer - Tamper Passive Filter"] +pub type TpfW<'a, REG> = crate::BitWriter<'a, REG, Tpf>; +impl<'a, REG> TpfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpf::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpf::Enable) + } +} +#[doc = "Input Buffer Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ibe { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ibe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IBE` reader - Input Buffer Enable"] +pub type IbeR = crate::BitReader; +impl IbeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ibe { + match self.bits { + false => Ibe::Disable, + true => Ibe::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ibe::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ibe::Enable + } +} +#[doc = "Field `IBE` writer - Input Buffer Enable"] +pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; +impl<'a, REG> IbeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ibe::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ibe::Enable) + } +} +impl R { + #[doc = "Bits 0:5 - Glitch Filter Width"] + #[inline(always)] + pub fn gfw(&self) -> GfwR { + GfwR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Glitch Filter Prescaler"] + #[inline(always)] + pub fn gfp(&self) -> GfpR { + GfpR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Glitch Filter Enable"] + #[inline(always)] + pub fn gfe(&self) -> GfeR { + GfeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Tamper Pin Sample Width"] + #[inline(always)] + pub fn tpsw(&self) -> TpswR { + TpswR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Tamper Pin Sample Frequency"] + #[inline(always)] + pub fn tpsf(&self) -> TpsfR { + TpsfR::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 24 - Tamper Pull Enable"] + #[inline(always)] + pub fn tpe(&self) -> TpeR { + TpeR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Tamper Pull Select"] + #[inline(always)] + pub fn tps(&self) -> TpsR { + TpsR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Tamper Pull Value"] + #[inline(always)] + pub fn tpv(&self) -> TpvR { + TpvR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Tamper Passive Filter"] + #[inline(always)] + pub fn tpf(&self) -> TpfR { + TpfR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 31 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&self) -> IbeR { + IbeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Glitch Filter Width"] + #[inline(always)] + pub fn gfw(&mut self) -> GfwW { + GfwW::new(self, 0) + } + #[doc = "Bit 6 - Glitch Filter Prescaler"] + #[inline(always)] + pub fn gfp(&mut self) -> GfpW { + GfpW::new(self, 6) + } + #[doc = "Bit 7 - Glitch Filter Enable"] + #[inline(always)] + pub fn gfe(&mut self) -> GfeW { + GfeW::new(self, 7) + } + #[doc = "Bits 8:9 - Tamper Pin Sample Width"] + #[inline(always)] + pub fn tpsw(&mut self) -> TpswW { + TpswW::new(self, 8) + } + #[doc = "Bits 10:11 - Tamper Pin Sample Frequency"] + #[inline(always)] + pub fn tpsf(&mut self) -> TpsfW { + TpsfW::new(self, 10) + } + #[doc = "Bit 24 - Tamper Pull Enable"] + #[inline(always)] + pub fn tpe(&mut self) -> TpeW { + TpeW::new(self, 24) + } + #[doc = "Bit 25 - Tamper Pull Select"] + #[inline(always)] + pub fn tps(&mut self) -> TpsW { + TpsW::new(self, 25) + } + #[doc = "Bit 26 - Tamper Pull Value"] + #[inline(always)] + pub fn tpv(&mut self) -> TpvW { + TpvW::new(self, 26) + } + #[doc = "Bit 27 - Tamper Passive Filter"] + #[inline(always)] + pub fn tpf(&mut self) -> TpfW { + TpfW::new(self, 27) + } + #[doc = "Bit 31 - Input Buffer Enable"] + #[inline(always)] + pub fn ibe(&mut self) -> IbeW { + IbeW::new(self, 31) + } +} +#[doc = "Pin Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`pgfr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pgfr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PgfrSpec; +impl crate::RegisterSpec for PgfrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgfr::R`](R) reader structure"] +impl crate::Readable for PgfrSpec {} +#[doc = "`write(|w| ..)` method takes [`pgfr::W`](W) writer structure"] +impl crate::Writable for PgfrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PGFR[%s] to value 0"] +impl crate::Resettable for PgfrSpec {} diff --git a/mcxa276-pac/src/tdet0/ppr.rs b/mcxa276-pac/src/tdet0/ppr.rs new file mode 100644 index 000000000..371ac26b9 --- /dev/null +++ b/mcxa276-pac/src/tdet0/ppr.rs @@ -0,0 +1,645 @@ +#[doc = "Register `PPR` reader"] +pub type R = crate::R; +#[doc = "Register `PPR` writer"] +pub type W = crate::W; +#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpp0 { + #[doc = "0: Not inverted"] + NoInvert = 0, + #[doc = "1: Inverted"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpp0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPP0` reader - Tamper Pin n Polarity"] +pub type Tpp0R = crate::BitReader; +impl Tpp0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpp0 { + match self.bits { + false => Tpp0::NoInvert, + true => Tpp0::Invert, + } + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == Tpp0::NoInvert + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == Tpp0::Invert + } +} +#[doc = "Field `TPP0` writer - Tamper Pin n Polarity"] +pub type Tpp0W<'a, REG> = crate::BitWriter<'a, REG, Tpp0>; +impl<'a, REG> Tpp0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not inverted"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(Tpp0::NoInvert) + } + #[doc = "Inverted"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(Tpp0::Invert) + } +} +#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpp1 { + #[doc = "0: Not inverted"] + NoInvert = 0, + #[doc = "1: Inverted"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPP1` reader - Tamper Pin n Polarity"] +pub type Tpp1R = crate::BitReader; +impl Tpp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpp1 { + match self.bits { + false => Tpp1::NoInvert, + true => Tpp1::Invert, + } + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == Tpp1::NoInvert + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == Tpp1::Invert + } +} +#[doc = "Field `TPP1` writer - Tamper Pin n Polarity"] +pub type Tpp1W<'a, REG> = crate::BitWriter<'a, REG, Tpp1>; +impl<'a, REG> Tpp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not inverted"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(Tpp1::NoInvert) + } + #[doc = "Inverted"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(Tpp1::Invert) + } +} +#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpp2 { + #[doc = "0: Not inverted"] + NoInvert = 0, + #[doc = "1: Inverted"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpp2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPP2` reader - Tamper Pin n Polarity"] +pub type Tpp2R = crate::BitReader; +impl Tpp2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpp2 { + match self.bits { + false => Tpp2::NoInvert, + true => Tpp2::Invert, + } + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == Tpp2::NoInvert + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == Tpp2::Invert + } +} +#[doc = "Field `TPP2` writer - Tamper Pin n Polarity"] +pub type Tpp2W<'a, REG> = crate::BitWriter<'a, REG, Tpp2>; +impl<'a, REG> Tpp2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not inverted"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(Tpp2::NoInvert) + } + #[doc = "Inverted"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(Tpp2::Invert) + } +} +#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpp3 { + #[doc = "0: Not inverted"] + NoInvert = 0, + #[doc = "1: Inverted"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpp3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPP3` reader - Tamper Pin n Polarity"] +pub type Tpp3R = crate::BitReader; +impl Tpp3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpp3 { + match self.bits { + false => Tpp3::NoInvert, + true => Tpp3::Invert, + } + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == Tpp3::NoInvert + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == Tpp3::Invert + } +} +#[doc = "Field `TPP3` writer - Tamper Pin n Polarity"] +pub type Tpp3W<'a, REG> = crate::BitWriter<'a, REG, Tpp3>; +impl<'a, REG> Tpp3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not inverted"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(Tpp3::NoInvert) + } + #[doc = "Inverted"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(Tpp3::Invert) + } +} +#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpp4 { + #[doc = "0: Not inverted"] + NoInvert = 0, + #[doc = "1: Inverted"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpp4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPP4` reader - Tamper Pin n Polarity"] +pub type Tpp4R = crate::BitReader; +impl Tpp4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpp4 { + match self.bits { + false => Tpp4::NoInvert, + true => Tpp4::Invert, + } + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == Tpp4::NoInvert + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == Tpp4::Invert + } +} +#[doc = "Field `TPP4` writer - Tamper Pin n Polarity"] +pub type Tpp4W<'a, REG> = crate::BitWriter<'a, REG, Tpp4>; +impl<'a, REG> Tpp4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not inverted"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(Tpp4::NoInvert) + } + #[doc = "Inverted"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(Tpp4::Invert) + } +} +#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpp5 { + #[doc = "0: Not inverted"] + NoInvert = 0, + #[doc = "1: Inverted"] + Invert = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpp5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPP5` reader - Tamper Pin n Polarity"] +pub type Tpp5R = crate::BitReader; +impl Tpp5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpp5 { + match self.bits { + false => Tpp5::NoInvert, + true => Tpp5::Invert, + } + } + #[doc = "Not inverted"] + #[inline(always)] + pub fn is_no_invert(&self) -> bool { + *self == Tpp5::NoInvert + } + #[doc = "Inverted"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == Tpp5::Invert + } +} +#[doc = "Field `TPP5` writer - Tamper Pin n Polarity"] +pub type Tpp5W<'a, REG> = crate::BitWriter<'a, REG, Tpp5>; +impl<'a, REG> Tpp5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not inverted"] + #[inline(always)] + pub fn no_invert(self) -> &'a mut crate::W { + self.variant(Tpp5::NoInvert) + } + #[doc = "Inverted"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(Tpp5::Invert) + } +} +#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpid0 { + #[doc = "0: Zero"] + Zero = 0, + #[doc = "1: One"] + One = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpid0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPID0` reader - Tamper Pin n Input Data"] +pub type Tpid0R = crate::BitReader; +impl Tpid0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpid0 { + match self.bits { + false => Tpid0::Zero, + true => Tpid0::One, + } + } + #[doc = "Zero"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + *self == Tpid0::Zero + } + #[doc = "One"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Tpid0::One + } +} +#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpid1 { + #[doc = "0: Zero"] + Zero = 0, + #[doc = "1: One"] + One = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpid1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPID1` reader - Tamper Pin n Input Data"] +pub type Tpid1R = crate::BitReader; +impl Tpid1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpid1 { + match self.bits { + false => Tpid1::Zero, + true => Tpid1::One, + } + } + #[doc = "Zero"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + *self == Tpid1::Zero + } + #[doc = "One"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Tpid1::One + } +} +#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpid2 { + #[doc = "0: Zero"] + Zero = 0, + #[doc = "1: One"] + One = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpid2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPID2` reader - Tamper Pin n Input Data"] +pub type Tpid2R = crate::BitReader; +impl Tpid2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpid2 { + match self.bits { + false => Tpid2::Zero, + true => Tpid2::One, + } + } + #[doc = "Zero"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + *self == Tpid2::Zero + } + #[doc = "One"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Tpid2::One + } +} +#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpid3 { + #[doc = "0: Zero"] + Zero = 0, + #[doc = "1: One"] + One = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpid3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPID3` reader - Tamper Pin n Input Data"] +pub type Tpid3R = crate::BitReader; +impl Tpid3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpid3 { + match self.bits { + false => Tpid3::Zero, + true => Tpid3::One, + } + } + #[doc = "Zero"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + *self == Tpid3::Zero + } + #[doc = "One"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Tpid3::One + } +} +#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpid4 { + #[doc = "0: Zero"] + Zero = 0, + #[doc = "1: One"] + One = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpid4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPID4` reader - Tamper Pin n Input Data"] +pub type Tpid4R = crate::BitReader; +impl Tpid4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpid4 { + match self.bits { + false => Tpid4::Zero, + true => Tpid4::One, + } + } + #[doc = "Zero"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + *self == Tpid4::Zero + } + #[doc = "One"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Tpid4::One + } +} +#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpid5 { + #[doc = "0: Zero"] + Zero = 0, + #[doc = "1: One"] + One = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpid5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPID5` reader - Tamper Pin n Input Data"] +pub type Tpid5R = crate::BitReader; +impl Tpid5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpid5 { + match self.bits { + false => Tpid5::Zero, + true => Tpid5::One, + } + } + #[doc = "Zero"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + *self == Tpid5::Zero + } + #[doc = "One"] + #[inline(always)] + pub fn is_one(&self) -> bool { + *self == Tpid5::One + } +} +impl R { + #[doc = "Bit 0 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp0(&self) -> Tpp0R { + Tpp0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp1(&self) -> Tpp1R { + Tpp1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp2(&self) -> Tpp2R { + Tpp2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp3(&self) -> Tpp3R { + Tpp3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp4(&self) -> Tpp4R { + Tpp4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp5(&self) -> Tpp5R { + Tpp5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - Tamper Pin n Input Data"] + #[inline(always)] + pub fn tpid0(&self) -> Tpid0R { + Tpid0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tamper Pin n Input Data"] + #[inline(always)] + pub fn tpid1(&self) -> Tpid1R { + Tpid1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Tamper Pin n Input Data"] + #[inline(always)] + pub fn tpid2(&self) -> Tpid2R { + Tpid2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Tamper Pin n Input Data"] + #[inline(always)] + pub fn tpid3(&self) -> Tpid3R { + Tpid3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Tamper Pin n Input Data"] + #[inline(always)] + pub fn tpid4(&self) -> Tpid4R { + Tpid4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Tamper Pin n Input Data"] + #[inline(always)] + pub fn tpid5(&self) -> Tpid5R { + Tpid5R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp0(&mut self) -> Tpp0W { + Tpp0W::new(self, 0) + } + #[doc = "Bit 1 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp1(&mut self) -> Tpp1W { + Tpp1W::new(self, 1) + } + #[doc = "Bit 2 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp2(&mut self) -> Tpp2W { + Tpp2W::new(self, 2) + } + #[doc = "Bit 3 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp3(&mut self) -> Tpp3W { + Tpp3W::new(self, 3) + } + #[doc = "Bit 4 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp4(&mut self) -> Tpp4W { + Tpp4W::new(self, 4) + } + #[doc = "Bit 5 - Tamper Pin n Polarity"] + #[inline(always)] + pub fn tpp5(&mut self) -> Tpp5W { + Tpp5W::new(self, 5) + } +} +#[doc = "Pin Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`ppr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ppr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PprSpec; +impl crate::RegisterSpec for PprSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ppr::R`](R) reader structure"] +impl crate::Readable for PprSpec {} +#[doc = "`write(|w| ..)` method takes [`ppr::W`](W) writer structure"] +impl crate::Writable for PprSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PPR to value 0"] +impl crate::Resettable for PprSpec {} diff --git a/mcxa276-pac/src/tdet0/sr.rs b/mcxa276-pac/src/tdet0/sr.rs new file mode 100644 index 000000000..583131965 --- /dev/null +++ b/mcxa276-pac/src/tdet0/sr.rs @@ -0,0 +1,1219 @@ +#[doc = "Register `SR` reader"] +pub type R = crate::R; +#[doc = "Register `SR` writer"] +pub type W = crate::W; +#[doc = "Digital Tamper Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dtf { + #[doc = "0: TDET tampering not detected"] + NoDet = 0, + #[doc = "1: TDET tampering detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dtf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DTF` reader - Digital Tamper Flag"] +pub type DtfR = crate::BitReader; +impl DtfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dtf { + match self.bits { + false => Dtf::NoDet, + true => Dtf::Det, + } + } + #[doc = "TDET tampering not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Dtf::NoDet + } + #[doc = "TDET tampering detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Dtf::Det + } +} +#[doc = "Field `DTF` writer - Digital Tamper Flag"] +pub type DtfW<'a, REG> = crate::BitWriter1C<'a, REG, Dtf>; +impl<'a, REG> DtfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "TDET tampering not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Dtf::NoDet) + } + #[doc = "TDET tampering detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Dtf::Det) + } +} +#[doc = "Tamper Acknowledge Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Taf { + #[doc = "0: Digital Tamper Flag (SR\\[DTF\\]) is clear or chip reset has not occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] + NotOccur = 0, + #[doc = "1: Chip reset has occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] + Occur = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Taf) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TAF` reader - Tamper Acknowledge Flag"] +pub type TafR = crate::BitReader; +impl TafR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Taf { + match self.bits { + false => Taf::NotOccur, + true => Taf::Occur, + } + } + #[doc = "Digital Tamper Flag (SR\\[DTF\\]) is clear or chip reset has not occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] + #[inline(always)] + pub fn is_not_occur(&self) -> bool { + *self == Taf::NotOccur + } + #[doc = "Chip reset has occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] + #[inline(always)] + pub fn is_occur(&self) -> bool { + *self == Taf::Occur + } +} +#[doc = "Field `TAF` writer - Tamper Acknowledge Flag"] +pub type TafW<'a, REG> = crate::BitWriter1C<'a, REG, Taf>; +impl<'a, REG> TafW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Digital Tamper Flag (SR\\[DTF\\]) is clear or chip reset has not occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] + #[inline(always)] + pub fn not_occur(self) -> &'a mut crate::W { + self.variant(Taf::NotOccur) + } + #[doc = "Chip reset has occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] + #[inline(always)] + pub fn occur(self) -> &'a mut crate::W { + self.variant(Taf::Occur) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif0 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF0` reader - Tamper Input n Flag"] +pub type Tif0R = crate::BitReader; +impl Tif0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif0 { + match self.bits { + false => Tif0::NoDet, + true => Tif0::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif0::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif0::Det + } +} +#[doc = "Field `TIF0` writer - Tamper Input n Flag"] +pub type Tif0W<'a, REG> = crate::BitWriter1C<'a, REG, Tif0>; +impl<'a, REG> Tif0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif0::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif0::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif1 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF1` reader - Tamper Input n Flag"] +pub type Tif1R = crate::BitReader; +impl Tif1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif1 { + match self.bits { + false => Tif1::NoDet, + true => Tif1::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif1::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif1::Det + } +} +#[doc = "Field `TIF1` writer - Tamper Input n Flag"] +pub type Tif1W<'a, REG> = crate::BitWriter1C<'a, REG, Tif1>; +impl<'a, REG> Tif1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif1::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif1::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif2 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF2` reader - Tamper Input n Flag"] +pub type Tif2R = crate::BitReader; +impl Tif2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif2 { + match self.bits { + false => Tif2::NoDet, + true => Tif2::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif2::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif2::Det + } +} +#[doc = "Field `TIF2` writer - Tamper Input n Flag"] +pub type Tif2W<'a, REG> = crate::BitWriter1C<'a, REG, Tif2>; +impl<'a, REG> Tif2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif2::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif2::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif3 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF3` reader - Tamper Input n Flag"] +pub type Tif3R = crate::BitReader; +impl Tif3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif3 { + match self.bits { + false => Tif3::NoDet, + true => Tif3::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif3::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif3::Det + } +} +#[doc = "Field `TIF3` writer - Tamper Input n Flag"] +pub type Tif3W<'a, REG> = crate::BitWriter1C<'a, REG, Tif3>; +impl<'a, REG> Tif3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif3::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif3::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif4 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF4` reader - Tamper Input n Flag"] +pub type Tif4R = crate::BitReader; +impl Tif4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif4 { + match self.bits { + false => Tif4::NoDet, + true => Tif4::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif4::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif4::Det + } +} +#[doc = "Field `TIF4` writer - Tamper Input n Flag"] +pub type Tif4W<'a, REG> = crate::BitWriter1C<'a, REG, Tif4>; +impl<'a, REG> Tif4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif4::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif4::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif5 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF5` reader - Tamper Input n Flag"] +pub type Tif5R = crate::BitReader; +impl Tif5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif5 { + match self.bits { + false => Tif5::NoDet, + true => Tif5::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif5::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif5::Det + } +} +#[doc = "Field `TIF5` writer - Tamper Input n Flag"] +pub type Tif5W<'a, REG> = crate::BitWriter1C<'a, REG, Tif5>; +impl<'a, REG> Tif5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif5::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif5::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif6 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF6` reader - Tamper Input n Flag"] +pub type Tif6R = crate::BitReader; +impl Tif6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif6 { + match self.bits { + false => Tif6::NoDet, + true => Tif6::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif6::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif6::Det + } +} +#[doc = "Field `TIF6` writer - Tamper Input n Flag"] +pub type Tif6W<'a, REG> = crate::BitWriter1C<'a, REG, Tif6>; +impl<'a, REG> Tif6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif6::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif6::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif7 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF7` reader - Tamper Input n Flag"] +pub type Tif7R = crate::BitReader; +impl Tif7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif7 { + match self.bits { + false => Tif7::NoDet, + true => Tif7::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif7::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif7::Det + } +} +#[doc = "Field `TIF7` writer - Tamper Input n Flag"] +pub type Tif7W<'a, REG> = crate::BitWriter1C<'a, REG, Tif7>; +impl<'a, REG> Tif7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif7::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif7::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif8 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF8` reader - Tamper Input n Flag"] +pub type Tif8R = crate::BitReader; +impl Tif8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif8 { + match self.bits { + false => Tif8::NoDet, + true => Tif8::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif8::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif8::Det + } +} +#[doc = "Field `TIF8` writer - Tamper Input n Flag"] +pub type Tif8W<'a, REG> = crate::BitWriter1C<'a, REG, Tif8>; +impl<'a, REG> Tif8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif8::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif8::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif9 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF9` reader - Tamper Input n Flag"] +pub type Tif9R = crate::BitReader; +impl Tif9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif9 { + match self.bits { + false => Tif9::NoDet, + true => Tif9::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif9::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif9::Det + } +} +#[doc = "Field `TIF9` writer - Tamper Input n Flag"] +pub type Tif9W<'a, REG> = crate::BitWriter1C<'a, REG, Tif9>; +impl<'a, REG> Tif9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif9::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif9::Det) + } +} +#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tif10 { + #[doc = "0: On-chip tamper not detected"] + NoDet = 0, + #[doc = "1: On-chip tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tif10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIF10` reader - Tamper Input n Flag"] +pub type Tif10R = crate::BitReader; +impl Tif10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tif10 { + match self.bits { + false => Tif10::NoDet, + true => Tif10::Det, + } + } + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tif10::NoDet + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tif10::Det + } +} +#[doc = "Field `TIF10` writer - Tamper Input n Flag"] +pub type Tif10W<'a, REG> = crate::BitWriter1C<'a, REG, Tif10>; +impl<'a, REG> Tif10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "On-chip tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tif10::NoDet) + } + #[doc = "On-chip tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tif10::Det) + } +} +#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpf0 { + #[doc = "0: Pin tamper not detected"] + NoDet = 0, + #[doc = "1: Pin tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpf0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPF0` reader - Tamper Pin n Flag"] +pub type Tpf0R = crate::BitReader; +impl Tpf0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpf0 { + match self.bits { + false => Tpf0::NoDet, + true => Tpf0::Det, + } + } + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tpf0::NoDet + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tpf0::Det + } +} +#[doc = "Field `TPF0` writer - Tamper Pin n Flag"] +pub type Tpf0W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf0>; +impl<'a, REG> Tpf0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tpf0::NoDet) + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tpf0::Det) + } +} +#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpf1 { + #[doc = "0: Pin tamper not detected"] + NoDet = 0, + #[doc = "1: Pin tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpf1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPF1` reader - Tamper Pin n Flag"] +pub type Tpf1R = crate::BitReader; +impl Tpf1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpf1 { + match self.bits { + false => Tpf1::NoDet, + true => Tpf1::Det, + } + } + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tpf1::NoDet + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tpf1::Det + } +} +#[doc = "Field `TPF1` writer - Tamper Pin n Flag"] +pub type Tpf1W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf1>; +impl<'a, REG> Tpf1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tpf1::NoDet) + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tpf1::Det) + } +} +#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpf2 { + #[doc = "0: Pin tamper not detected"] + NoDet = 0, + #[doc = "1: Pin tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpf2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPF2` reader - Tamper Pin n Flag"] +pub type Tpf2R = crate::BitReader; +impl Tpf2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpf2 { + match self.bits { + false => Tpf2::NoDet, + true => Tpf2::Det, + } + } + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tpf2::NoDet + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tpf2::Det + } +} +#[doc = "Field `TPF2` writer - Tamper Pin n Flag"] +pub type Tpf2W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf2>; +impl<'a, REG> Tpf2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tpf2::NoDet) + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tpf2::Det) + } +} +#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpf3 { + #[doc = "0: Pin tamper not detected"] + NoDet = 0, + #[doc = "1: Pin tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpf3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPF3` reader - Tamper Pin n Flag"] +pub type Tpf3R = crate::BitReader; +impl Tpf3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpf3 { + match self.bits { + false => Tpf3::NoDet, + true => Tpf3::Det, + } + } + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tpf3::NoDet + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tpf3::Det + } +} +#[doc = "Field `TPF3` writer - Tamper Pin n Flag"] +pub type Tpf3W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf3>; +impl<'a, REG> Tpf3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tpf3::NoDet) + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tpf3::Det) + } +} +#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpf4 { + #[doc = "0: Pin tamper not detected"] + NoDet = 0, + #[doc = "1: Pin tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpf4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPF4` reader - Tamper Pin n Flag"] +pub type Tpf4R = crate::BitReader; +impl Tpf4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpf4 { + match self.bits { + false => Tpf4::NoDet, + true => Tpf4::Det, + } + } + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tpf4::NoDet + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tpf4::Det + } +} +#[doc = "Field `TPF4` writer - Tamper Pin n Flag"] +pub type Tpf4W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf4>; +impl<'a, REG> Tpf4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tpf4::NoDet) + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tpf4::Det) + } +} +#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpf5 { + #[doc = "0: Pin tamper not detected"] + NoDet = 0, + #[doc = "1: Pin tamper detected"] + Det = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpf5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPF5` reader - Tamper Pin n Flag"] +pub type Tpf5R = crate::BitReader; +impl Tpf5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpf5 { + match self.bits { + false => Tpf5::NoDet, + true => Tpf5::Det, + } + } + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn is_no_det(&self) -> bool { + *self == Tpf5::NoDet + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn is_det(&self) -> bool { + *self == Tpf5::Det + } +} +#[doc = "Field `TPF5` writer - Tamper Pin n Flag"] +pub type Tpf5W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf5>; +impl<'a, REG> Tpf5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Pin tamper not detected"] + #[inline(always)] + pub fn no_det(self) -> &'a mut crate::W { + self.variant(Tpf5::NoDet) + } + #[doc = "Pin tamper detected"] + #[inline(always)] + pub fn det(self) -> &'a mut crate::W { + self.variant(Tpf5::Det) + } +} +impl R { + #[doc = "Bit 0 - Digital Tamper Flag"] + #[inline(always)] + pub fn dtf(&self) -> DtfR { + DtfR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tamper Acknowledge Flag"] + #[inline(always)] + pub fn taf(&self) -> TafR { + TafR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif0(&self) -> Tif0R { + Tif0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif1(&self) -> Tif1R { + Tif1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif2(&self) -> Tif2R { + Tif2R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif3(&self) -> Tif3R { + Tif3R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif4(&self) -> Tif4R { + Tif4R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif5(&self) -> Tif5R { + Tif5R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif6(&self) -> Tif6R { + Tif6R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif7(&self) -> Tif7R { + Tif7R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif8(&self) -> Tif8R { + Tif8R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif9(&self) -> Tif9R { + Tif9R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif10(&self) -> Tif10R { + Tif10R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf0(&self) -> Tpf0R { + Tpf0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf1(&self) -> Tpf1R { + Tpf1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf2(&self) -> Tpf2R { + Tpf2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf3(&self) -> Tpf3R { + Tpf3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf4(&self) -> Tpf4R { + Tpf4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf5(&self) -> Tpf5R { + Tpf5R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Digital Tamper Flag"] + #[inline(always)] + pub fn dtf(&mut self) -> DtfW { + DtfW::new(self, 0) + } + #[doc = "Bit 1 - Tamper Acknowledge Flag"] + #[inline(always)] + pub fn taf(&mut self) -> TafW { + TafW::new(self, 1) + } + #[doc = "Bit 2 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif0(&mut self) -> Tif0W { + Tif0W::new(self, 2) + } + #[doc = "Bit 3 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif1(&mut self) -> Tif1W { + Tif1W::new(self, 3) + } + #[doc = "Bit 4 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif2(&mut self) -> Tif2W { + Tif2W::new(self, 4) + } + #[doc = "Bit 5 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif3(&mut self) -> Tif3W { + Tif3W::new(self, 5) + } + #[doc = "Bit 6 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif4(&mut self) -> Tif4W { + Tif4W::new(self, 6) + } + #[doc = "Bit 7 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif5(&mut self) -> Tif5W { + Tif5W::new(self, 7) + } + #[doc = "Bit 8 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif6(&mut self) -> Tif6W { + Tif6W::new(self, 8) + } + #[doc = "Bit 9 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif7(&mut self) -> Tif7W { + Tif7W::new(self, 9) + } + #[doc = "Bit 10 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif8(&mut self) -> Tif8W { + Tif8W::new(self, 10) + } + #[doc = "Bit 11 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif9(&mut self) -> Tif9W { + Tif9W::new(self, 11) + } + #[doc = "Bit 12 - Tamper Input n Flag"] + #[inline(always)] + pub fn tif10(&mut self) -> Tif10W { + Tif10W::new(self, 12) + } + #[doc = "Bit 16 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf0(&mut self) -> Tpf0W { + Tpf0W::new(self, 16) + } + #[doc = "Bit 17 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf1(&mut self) -> Tpf1W { + Tpf1W::new(self, 17) + } + #[doc = "Bit 18 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf2(&mut self) -> Tpf2W { + Tpf2W::new(self, 18) + } + #[doc = "Bit 19 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf3(&mut self) -> Tpf3W { + Tpf3W::new(self, 19) + } + #[doc = "Bit 20 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf4(&mut self) -> Tpf4W { + Tpf4W::new(self, 20) + } + #[doc = "Bit 21 - Tamper Pin n Flag"] + #[inline(always)] + pub fn tpf5(&mut self) -> Tpf5W { + Tpf5W::new(self, 21) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrSpec; +impl crate::RegisterSpec for SrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SrSpec {} +#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] +impl crate::Writable for SrSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x003f_1fff; +} +#[doc = "`reset()` method sets SR to value 0"] +impl crate::Resettable for SrSpec {} diff --git a/mcxa276-pac/src/tdet0/ter.rs b/mcxa276-pac/src/tdet0/ter.rs new file mode 100644 index 000000000..f11b6e335 --- /dev/null +++ b/mcxa276-pac/src/tdet0/ter.rs @@ -0,0 +1,1092 @@ +#[doc = "Register `TER` reader"] +pub type R = crate::R; +#[doc = "Register `TER` writer"] +pub type W = crate::W; +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie0 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE0` reader - Tamper Input Enable"] +pub type Tie0R = crate::BitReader; +impl Tie0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie0 { + match self.bits { + false => Tie0::Disable, + true => Tie0::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie0::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie0::Enable + } +} +#[doc = "Field `TIE0` writer - Tamper Input Enable"] +pub type Tie0W<'a, REG> = crate::BitWriter<'a, REG, Tie0>; +impl<'a, REG> Tie0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie0::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie0::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie1 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE1` reader - Tamper Input Enable"] +pub type Tie1R = crate::BitReader; +impl Tie1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie1 { + match self.bits { + false => Tie1::Disable, + true => Tie1::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie1::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie1::Enable + } +} +#[doc = "Field `TIE1` writer - Tamper Input Enable"] +pub type Tie1W<'a, REG> = crate::BitWriter<'a, REG, Tie1>; +impl<'a, REG> Tie1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie1::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie1::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie2 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE2` reader - Tamper Input Enable"] +pub type Tie2R = crate::BitReader; +impl Tie2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie2 { + match self.bits { + false => Tie2::Disable, + true => Tie2::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie2::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie2::Enable + } +} +#[doc = "Field `TIE2` writer - Tamper Input Enable"] +pub type Tie2W<'a, REG> = crate::BitWriter<'a, REG, Tie2>; +impl<'a, REG> Tie2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie2::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie2::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie3 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE3` reader - Tamper Input Enable"] +pub type Tie3R = crate::BitReader; +impl Tie3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie3 { + match self.bits { + false => Tie3::Disable, + true => Tie3::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie3::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie3::Enable + } +} +#[doc = "Field `TIE3` writer - Tamper Input Enable"] +pub type Tie3W<'a, REG> = crate::BitWriter<'a, REG, Tie3>; +impl<'a, REG> Tie3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie3::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie3::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie4 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE4` reader - Tamper Input Enable"] +pub type Tie4R = crate::BitReader; +impl Tie4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie4 { + match self.bits { + false => Tie4::Disable, + true => Tie4::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie4::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie4::Enable + } +} +#[doc = "Field `TIE4` writer - Tamper Input Enable"] +pub type Tie4W<'a, REG> = crate::BitWriter<'a, REG, Tie4>; +impl<'a, REG> Tie4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie4::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie4::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie5 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE5` reader - Tamper Input Enable"] +pub type Tie5R = crate::BitReader; +impl Tie5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie5 { + match self.bits { + false => Tie5::Disable, + true => Tie5::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie5::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie5::Enable + } +} +#[doc = "Field `TIE5` writer - Tamper Input Enable"] +pub type Tie5W<'a, REG> = crate::BitWriter<'a, REG, Tie5>; +impl<'a, REG> Tie5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie5::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie5::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie6 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE6` reader - Tamper Input Enable"] +pub type Tie6R = crate::BitReader; +impl Tie6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie6 { + match self.bits { + false => Tie6::Disable, + true => Tie6::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie6::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie6::Enable + } +} +#[doc = "Field `TIE6` writer - Tamper Input Enable"] +pub type Tie6W<'a, REG> = crate::BitWriter<'a, REG, Tie6>; +impl<'a, REG> Tie6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie6::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie6::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie7 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE7` reader - Tamper Input Enable"] +pub type Tie7R = crate::BitReader; +impl Tie7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie7 { + match self.bits { + false => Tie7::Disable, + true => Tie7::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie7::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie7::Enable + } +} +#[doc = "Field `TIE7` writer - Tamper Input Enable"] +pub type Tie7W<'a, REG> = crate::BitWriter<'a, REG, Tie7>; +impl<'a, REG> Tie7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie7::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie7::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie8 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE8` reader - Tamper Input Enable"] +pub type Tie8R = crate::BitReader; +impl Tie8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie8 { + match self.bits { + false => Tie8::Disable, + true => Tie8::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie8::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie8::Enable + } +} +#[doc = "Field `TIE8` writer - Tamper Input Enable"] +pub type Tie8W<'a, REG> = crate::BitWriter<'a, REG, Tie8>; +impl<'a, REG> Tie8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie8::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie8::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie9 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE9` reader - Tamper Input Enable"] +pub type Tie9R = crate::BitReader; +impl Tie9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie9 { + match self.bits { + false => Tie9::Disable, + true => Tie9::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie9::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie9::Enable + } +} +#[doc = "Field `TIE9` writer - Tamper Input Enable"] +pub type Tie9W<'a, REG> = crate::BitWriter<'a, REG, Tie9>; +impl<'a, REG> Tie9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie9::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie9::Enable) + } +} +#[doc = "Tamper Input Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tie10 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tie10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TIE10` reader - Tamper Input Enable"] +pub type Tie10R = crate::BitReader; +impl Tie10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tie10 { + match self.bits { + false => Tie10::Disable, + true => Tie10::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tie10::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tie10::Enable + } +} +#[doc = "Field `TIE10` writer - Tamper Input Enable"] +pub type Tie10W<'a, REG> = crate::BitWriter<'a, REG, Tie10>; +impl<'a, REG> Tie10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tie10::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tie10::Enable) + } +} +#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpe0 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpe0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPE0` reader - Tamper Pin Enable"] +pub type Tpe0R = crate::BitReader; +impl Tpe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpe0 { + match self.bits { + false => Tpe0::Disable, + true => Tpe0::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpe0::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpe0::Enable + } +} +#[doc = "Field `TPE0` writer - Tamper Pin Enable"] +pub type Tpe0W<'a, REG> = crate::BitWriter<'a, REG, Tpe0>; +impl<'a, REG> Tpe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpe0::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpe0::Enable) + } +} +#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpe1 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpe1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPE1` reader - Tamper Pin Enable"] +pub type Tpe1R = crate::BitReader; +impl Tpe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpe1 { + match self.bits { + false => Tpe1::Disable, + true => Tpe1::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpe1::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpe1::Enable + } +} +#[doc = "Field `TPE1` writer - Tamper Pin Enable"] +pub type Tpe1W<'a, REG> = crate::BitWriter<'a, REG, Tpe1>; +impl<'a, REG> Tpe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpe1::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpe1::Enable) + } +} +#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpe2 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpe2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPE2` reader - Tamper Pin Enable"] +pub type Tpe2R = crate::BitReader; +impl Tpe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpe2 { + match self.bits { + false => Tpe2::Disable, + true => Tpe2::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpe2::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpe2::Enable + } +} +#[doc = "Field `TPE2` writer - Tamper Pin Enable"] +pub type Tpe2W<'a, REG> = crate::BitWriter<'a, REG, Tpe2>; +impl<'a, REG> Tpe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpe2::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpe2::Enable) + } +} +#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpe3 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpe3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPE3` reader - Tamper Pin Enable"] +pub type Tpe3R = crate::BitReader; +impl Tpe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpe3 { + match self.bits { + false => Tpe3::Disable, + true => Tpe3::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpe3::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpe3::Enable + } +} +#[doc = "Field `TPE3` writer - Tamper Pin Enable"] +pub type Tpe3W<'a, REG> = crate::BitWriter<'a, REG, Tpe3>; +impl<'a, REG> Tpe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpe3::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpe3::Enable) + } +} +#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpe4 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpe4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPE4` reader - Tamper Pin Enable"] +pub type Tpe4R = crate::BitReader; +impl Tpe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpe4 { + match self.bits { + false => Tpe4::Disable, + true => Tpe4::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpe4::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpe4::Enable + } +} +#[doc = "Field `TPE4` writer - Tamper Pin Enable"] +pub type Tpe4W<'a, REG> = crate::BitWriter<'a, REG, Tpe4>; +impl<'a, REG> Tpe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpe4::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpe4::Enable) + } +} +#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tpe5 { + #[doc = "0: Disables"] + Disable = 0, + #[doc = "1: Enables"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tpe5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TPE5` reader - Tamper Pin Enable"] +pub type Tpe5R = crate::BitReader; +impl Tpe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tpe5 { + match self.bits { + false => Tpe5::Disable, + true => Tpe5::Enable, + } + } + #[doc = "Disables"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tpe5::Disable + } + #[doc = "Enables"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tpe5::Enable + } +} +#[doc = "Field `TPE5` writer - Tamper Pin Enable"] +pub type Tpe5W<'a, REG> = crate::BitWriter<'a, REG, Tpe5>; +impl<'a, REG> Tpe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Tpe5::Disable) + } + #[doc = "Enables"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Tpe5::Enable) + } +} +impl R { + #[doc = "Bit 2 - Tamper Input Enable"] + #[inline(always)] + pub fn tie0(&self) -> Tie0R { + Tie0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Tamper Input Enable"] + #[inline(always)] + pub fn tie1(&self) -> Tie1R { + Tie1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Tamper Input Enable"] + #[inline(always)] + pub fn tie2(&self) -> Tie2R { + Tie2R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Tamper Input Enable"] + #[inline(always)] + pub fn tie3(&self) -> Tie3R { + Tie3R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Tamper Input Enable"] + #[inline(always)] + pub fn tie4(&self) -> Tie4R { + Tie4R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tamper Input Enable"] + #[inline(always)] + pub fn tie5(&self) -> Tie5R { + Tie5R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Tamper Input Enable"] + #[inline(always)] + pub fn tie6(&self) -> Tie6R { + Tie6R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Tamper Input Enable"] + #[inline(always)] + pub fn tie7(&self) -> Tie7R { + Tie7R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Tamper Input Enable"] + #[inline(always)] + pub fn tie8(&self) -> Tie8R { + Tie8R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Tamper Input Enable"] + #[inline(always)] + pub fn tie9(&self) -> Tie9R { + Tie9R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Tamper Input Enable"] + #[inline(always)] + pub fn tie10(&self) -> Tie10R { + Tie10R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe0(&self) -> Tpe0R { + Tpe0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe1(&self) -> Tpe1R { + Tpe1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe2(&self) -> Tpe2R { + Tpe2R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe3(&self) -> Tpe3R { + Tpe3R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe4(&self) -> Tpe4R { + Tpe4R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe5(&self) -> Tpe5R { + Tpe5R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Tamper Input Enable"] + #[inline(always)] + pub fn tie0(&mut self) -> Tie0W { + Tie0W::new(self, 2) + } + #[doc = "Bit 3 - Tamper Input Enable"] + #[inline(always)] + pub fn tie1(&mut self) -> Tie1W { + Tie1W::new(self, 3) + } + #[doc = "Bit 4 - Tamper Input Enable"] + #[inline(always)] + pub fn tie2(&mut self) -> Tie2W { + Tie2W::new(self, 4) + } + #[doc = "Bit 5 - Tamper Input Enable"] + #[inline(always)] + pub fn tie3(&mut self) -> Tie3W { + Tie3W::new(self, 5) + } + #[doc = "Bit 6 - Tamper Input Enable"] + #[inline(always)] + pub fn tie4(&mut self) -> Tie4W { + Tie4W::new(self, 6) + } + #[doc = "Bit 7 - Tamper Input Enable"] + #[inline(always)] + pub fn tie5(&mut self) -> Tie5W { + Tie5W::new(self, 7) + } + #[doc = "Bit 8 - Tamper Input Enable"] + #[inline(always)] + pub fn tie6(&mut self) -> Tie6W { + Tie6W::new(self, 8) + } + #[doc = "Bit 9 - Tamper Input Enable"] + #[inline(always)] + pub fn tie7(&mut self) -> Tie7W { + Tie7W::new(self, 9) + } + #[doc = "Bit 10 - Tamper Input Enable"] + #[inline(always)] + pub fn tie8(&mut self) -> Tie8W { + Tie8W::new(self, 10) + } + #[doc = "Bit 11 - Tamper Input Enable"] + #[inline(always)] + pub fn tie9(&mut self) -> Tie9W { + Tie9W::new(self, 11) + } + #[doc = "Bit 12 - Tamper Input Enable"] + #[inline(always)] + pub fn tie10(&mut self) -> Tie10W { + Tie10W::new(self, 12) + } + #[doc = "Bit 16 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe0(&mut self) -> Tpe0W { + Tpe0W::new(self, 16) + } + #[doc = "Bit 17 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe1(&mut self) -> Tpe1W { + Tpe1W::new(self, 17) + } + #[doc = "Bit 18 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe2(&mut self) -> Tpe2W { + Tpe2W::new(self, 18) + } + #[doc = "Bit 19 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe3(&mut self) -> Tpe3W { + Tpe3W::new(self, 19) + } + #[doc = "Bit 20 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe4(&mut self) -> Tpe4W { + Tpe4W::new(self, 20) + } + #[doc = "Bit 21 - Tamper Pin Enable"] + #[inline(always)] + pub fn tpe5(&mut self) -> Tpe5W { + Tpe5W::new(self, 21) + } +} +#[doc = "Tamper Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TerSpec; +impl crate::RegisterSpec for TerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ter::R`](R) reader structure"] +impl crate::Readable for TerSpec {} +#[doc = "`write(|w| ..)` method takes [`ter::W`](W) writer structure"] +impl crate::Writable for TerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TER to value 0"] +impl crate::Resettable for TerSpec {} diff --git a/mcxa276-pac/src/tdet0/tsr.rs b/mcxa276-pac/src/tdet0/tsr.rs new file mode 100644 index 000000000..3578e3f4a --- /dev/null +++ b/mcxa276-pac/src/tdet0/tsr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSR` reader"] +pub type R = crate::R; +#[doc = "Register `TSR` writer"] +pub type W = crate::W; +#[doc = "Field `TTS` reader - Tamper Time Seconds"] +pub type TtsR = crate::FieldReader; +#[doc = "Field `TTS` writer - Tamper Time Seconds"] +pub type TtsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Tamper Time Seconds"] + #[inline(always)] + pub fn tts(&self) -> TtsR { + TtsR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Tamper Time Seconds"] + #[inline(always)] + pub fn tts(&mut self) -> TtsW { + TtsW::new(self, 0) + } +} +#[doc = "Tamper Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TsrSpec; +impl crate::RegisterSpec for TsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tsr::R`](R) reader structure"] +impl crate::Readable for TsrSpec {} +#[doc = "`write(|w| ..)` method takes [`tsr::W`](W) writer structure"] +impl crate::Writable for TsrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSR to value 0"] +impl crate::Resettable for TsrSpec {} diff --git a/mcxa276-pac/src/trng0.rs b/mcxa276-pac/src/trng0.rs new file mode 100644 index 000000000..84db31724 --- /dev/null +++ b/mcxa276-pac/src/trng0.rs @@ -0,0 +1,492 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mctl: Mctl, + scmisc: Scmisc, + pkrrng: Pkrrng, + _reserved_3_pkrsq_pkrsq: [u8; 0x04], + sdctl: Sdctl, + _reserved_5_sblim_sblim: [u8; 0x04], + _reserved_6_frqmin_frqmin: [u8; 0x04], + _reserved_7_frqcnt_frqcnt: [u8; 0x04], + _reserved_8_scmc_scmc: [u8; 0x04], + _reserved_9_scr: [u8; 0x04], + _reserved_10_scr: [u8; 0x04], + _reserved_11_scr: [u8; 0x04], + _reserved_12_scr: [u8; 0x04], + _reserved_13_scr: [u8; 0x04], + _reserved_14_scr: [u8; 0x04], + status: Status, + ent0: Ent0, + _reserved17: [u8; 0x3c], + pkrcnt10: Pkrcnt10, + pkrcnt32: Pkrcnt32, + pkrcnt54: Pkrcnt54, + pkrcnt76: Pkrcnt76, + pkrcnt98: Pkrcnt98, + pkrcntba: Pkrcntba, + pkrcntdc: Pkrcntdc, + pkrcntfe: Pkrcntfe, + sec_cfg: SecCfg, + int_ctrl: IntCtrl, + int_mask: IntMask, + int_status: IntStatus, + cser: Cser, + csclr: Csclr, + _reserved31: [u8; 0x34], + osc2_ctl: Osc2Ctl, + vid1: Vid1, + vid2: Vid2, +} +impl RegisterBlock { + #[doc = "0x00 - Miscellaneous Control Register"] + #[inline(always)] + pub const fn mctl(&self) -> &Mctl { + &self.mctl + } + #[doc = "0x04 - Statistical Check Miscellaneous Register"] + #[inline(always)] + pub const fn scmisc(&self) -> &Scmisc { + &self.scmisc + } + #[doc = "0x08 - Poker Range Register"] + #[inline(always)] + pub const fn pkrrng(&self) -> &Pkrrng { + &self.pkrrng + } + #[doc = "0x0c - Poker Square Calculation Result Register"] + #[inline(always)] + pub const fn pkrsq_pkrsq(&self) -> &PkrsqPkrsq { + unsafe { &*core::ptr::from_ref(self).cast::().add(12).cast() } + } + #[doc = "0x0c - Poker Maximum Limit Register"] + #[inline(always)] + pub const fn pkrmax_pkrmax(&self) -> &PkrmaxPkrmax { + unsafe { &*core::ptr::from_ref(self).cast::().add(12).cast() } + } + #[doc = "0x10 - Seed Control Register"] + #[inline(always)] + pub const fn sdctl(&self) -> &Sdctl { + &self.sdctl + } + #[doc = "0x14 - Total Samples Register"] + #[inline(always)] + pub const fn totsam_totsam(&self) -> &TotsamTotsam { + unsafe { &*core::ptr::from_ref(self).cast::().add(20).cast() } + } + #[doc = "0x14 - Sparse Bit Limit Register"] + #[inline(always)] + pub const fn sblim_sblim(&self) -> &SblimSblim { + unsafe { &*core::ptr::from_ref(self).cast::().add(20).cast() } + } + #[doc = "0x18 - Oscillator-2 Frequency Count Register"] + #[inline(always)] + pub const fn osc2_frqcnt_osc2_frqcnt(&self) -> &Osc2FrqcntOsc2Frqcnt { + unsafe { &*core::ptr::from_ref(self).cast::().add(24).cast() } + } + #[doc = "0x18 - Frequency Count Minimum Limit Register"] + #[inline(always)] + pub const fn frqmin_frqmin(&self) -> &FrqminFrqmin { + unsafe { &*core::ptr::from_ref(self).cast::().add(24).cast() } + } + #[doc = "0x1c - Frequency Count Maximum Limit Register"] + #[inline(always)] + pub const fn frqmax_frqmax(&self) -> &FrqmaxFrqmax { + unsafe { &*core::ptr::from_ref(self).cast::().add(28).cast() } + } + #[doc = "0x1c - Frequency Count Register"] + #[inline(always)] + pub const fn frqcnt_frqcnt(&self) -> &FrqcntFrqcnt { + unsafe { &*core::ptr::from_ref(self).cast::().add(28).cast() } + } + #[doc = "0x20 - Statistical Check Monobit Limit Register"] + #[inline(always)] + pub const fn scml_scml(&self) -> &ScmlScml { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x20 - Statistical Check Monobit Count Register"] + #[inline(always)] + pub const fn scmc_scmc(&self) -> &ScmcScmc { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x24 - Statistical Check Run Length 1 Limit Register"] + #[inline(always)] + pub const fn scr1l_scr1l(&self) -> &Scr1lScr1l { + unsafe { &*core::ptr::from_ref(self).cast::().add(36).cast() } + } + #[doc = "0x24 - Statistical Check Run Length 1 Count Register"] + #[inline(always)] + pub const fn scr1c_scr1c(&self) -> &Scr1cScr1c { + unsafe { &*core::ptr::from_ref(self).cast::().add(36).cast() } + } + #[doc = "0x28 - Statistical Check Run Length 2 Limit Register"] + #[inline(always)] + pub const fn scr2l_scr2l(&self) -> &Scr2lScr2l { + unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } + } + #[doc = "0x28 - Statistical Check Run Length 2 Count Register"] + #[inline(always)] + pub const fn scr2c_scr2c(&self) -> &Scr2cScr2c { + unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } + } + #[doc = "0x2c - Statistical Check Run Length 3 Limit Register"] + #[inline(always)] + pub const fn scr3l_scr3l(&self) -> &Scr3lScr3l { + unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } + } + #[doc = "0x2c - Statistical Check Run Length 3 Count Register"] + #[inline(always)] + pub const fn scr3c_scr3c(&self) -> &Scr3cScr3c { + unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } + } + #[doc = "0x30 - Statistical Check Run Length 4 Limit Register"] + #[inline(always)] + pub const fn scr4l_scr4l(&self) -> &Scr4lScr4l { + unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } + } + #[doc = "0x30 - Statistical Check Run Length 4 Count Register"] + #[inline(always)] + pub const fn scr4c_scr4c(&self) -> &Scr4cScr4c { + unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } + } + #[doc = "0x34 - Statistical Check Run Length 5 Limit Register"] + #[inline(always)] + pub const fn scr5l_scr5l(&self) -> &Scr5lScr5l { + unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } + } + #[doc = "0x34 - Statistical Check Run Length 5 Count Register"] + #[inline(always)] + pub const fn scr5c_scr5c(&self) -> &Scr5cScr5c { + unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } + } + #[doc = "0x38 - Statistical Check Run Length 6+ Limit Register"] + #[inline(always)] + pub const fn scr6pl_scr6pl(&self) -> &Scr6plScr6pl { + unsafe { &*core::ptr::from_ref(self).cast::().add(56).cast() } + } + #[doc = "0x38 - Statistical Check Run Length 6+ Count Register"] + #[inline(always)] + pub const fn scr6pc_scr6pc(&self) -> &Scr6pcScr6pc { + unsafe { &*core::ptr::from_ref(self).cast::().add(56).cast() } + } + #[doc = "0x3c - Status Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x40 - Entropy Read Register"] + #[inline(always)] + pub const fn ent0(&self) -> &Ent0 { + &self.ent0 + } + #[doc = "0x80 - Statistical Check Poker Count 1 and 0 Register"] + #[inline(always)] + pub const fn pkrcnt10(&self) -> &Pkrcnt10 { + &self.pkrcnt10 + } + #[doc = "0x84 - Statistical Check Poker Count 3 and 2 Register"] + #[inline(always)] + pub const fn pkrcnt32(&self) -> &Pkrcnt32 { + &self.pkrcnt32 + } + #[doc = "0x88 - Statistical Check Poker Count 5 and 4 Register"] + #[inline(always)] + pub const fn pkrcnt54(&self) -> &Pkrcnt54 { + &self.pkrcnt54 + } + #[doc = "0x8c - Statistical Check Poker Count 7 and 6 Register"] + #[inline(always)] + pub const fn pkrcnt76(&self) -> &Pkrcnt76 { + &self.pkrcnt76 + } + #[doc = "0x90 - Statistical Check Poker Count 9 and 8 Register"] + #[inline(always)] + pub const fn pkrcnt98(&self) -> &Pkrcnt98 { + &self.pkrcnt98 + } + #[doc = "0x94 - Statistical Check Poker Count B and A Register"] + #[inline(always)] + pub const fn pkrcntba(&self) -> &Pkrcntba { + &self.pkrcntba + } + #[doc = "0x98 - Statistical Check Poker Count D and C Register"] + #[inline(always)] + pub const fn pkrcntdc(&self) -> &Pkrcntdc { + &self.pkrcntdc + } + #[doc = "0x9c - Statistical Check Poker Count F and E Register"] + #[inline(always)] + pub const fn pkrcntfe(&self) -> &Pkrcntfe { + &self.pkrcntfe + } + #[doc = "0xa0 - Security Configuration Register"] + #[inline(always)] + pub const fn sec_cfg(&self) -> &SecCfg { + &self.sec_cfg + } + #[doc = "0xa4 - Interrupt Control Register"] + #[inline(always)] + pub const fn int_ctrl(&self) -> &IntCtrl { + &self.int_ctrl + } + #[doc = "0xa8 - Mask Register"] + #[inline(always)] + pub const fn int_mask(&self) -> &IntMask { + &self.int_mask + } + #[doc = "0xac - Interrupt Status Register"] + #[inline(always)] + pub const fn int_status(&self) -> &IntStatus { + &self.int_status + } + #[doc = "0xb0 - Common Security Error Register"] + #[inline(always)] + pub const fn cser(&self) -> &Cser { + &self.cser + } + #[doc = "0xb4 - Common Security Clear Register"] + #[inline(always)] + pub const fn csclr(&self) -> &Csclr { + &self.csclr + } + #[doc = "0xec - TRNG Oscillator 2 Control Register"] + #[inline(always)] + pub const fn osc2_ctl(&self) -> &Osc2Ctl { + &self.osc2_ctl + } + #[doc = "0xf0 - Version ID Register (MS)"] + #[inline(always)] + pub const fn vid1(&self) -> &Vid1 { + &self.vid1 + } + #[doc = "0xf4 - Version ID Register (LS)"] + #[inline(always)] + pub const fn vid2(&self) -> &Vid2 { + &self.vid2 + } +} +#[doc = "MCTL (rw) register accessor: Miscellaneous Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctl`] module"] +#[doc(alias = "MCTL")] +pub type Mctl = crate::Reg; +#[doc = "Miscellaneous Control Register"] +pub mod mctl; +#[doc = "SCMISC (rw) register accessor: Statistical Check Miscellaneous Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmisc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scmisc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scmisc`] module"] +#[doc(alias = "SCMISC")] +pub type Scmisc = crate::Reg; +#[doc = "Statistical Check Miscellaneous Register"] +pub mod scmisc; +#[doc = "PKRRNG (rw) register accessor: Poker Range Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrrng::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrrng::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrrng`] module"] +#[doc(alias = "PKRRNG")] +pub type Pkrrng = crate::Reg; +#[doc = "Poker Range Register"] +pub mod pkrrng; +#[doc = "PKRMAX_PKRMAX (rw) register accessor: Poker Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrmax_pkrmax::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrmax_pkrmax::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrmax_pkrmax`] module"] +#[doc(alias = "PKRMAX_PKRMAX")] +pub type PkrmaxPkrmax = crate::Reg; +#[doc = "Poker Maximum Limit Register"] +pub mod pkrmax_pkrmax; +#[doc = "PKRSQ_PKRSQ (r) register accessor: Poker Square Calculation Result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrsq_pkrsq::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrsq_pkrsq`] module"] +#[doc(alias = "PKRSQ_PKRSQ")] +pub type PkrsqPkrsq = crate::Reg; +#[doc = "Poker Square Calculation Result Register"] +pub mod pkrsq_pkrsq; +#[doc = "SDCTL (rw) register accessor: Seed Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdctl`] module"] +#[doc(alias = "SDCTL")] +pub type Sdctl = crate::Reg; +#[doc = "Seed Control Register"] +pub mod sdctl; +#[doc = "SBLIM_SBLIM (rw) register accessor: Sparse Bit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sblim_sblim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sblim_sblim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sblim_sblim`] module"] +#[doc(alias = "SBLIM_SBLIM")] +pub type SblimSblim = crate::Reg; +#[doc = "Sparse Bit Limit Register"] +pub mod sblim_sblim; +#[doc = "TOTSAM_TOTSAM (r) register accessor: Total Samples Register\n\nYou can [`read`](crate::Reg::read) this register and get [`totsam_totsam::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@totsam_totsam`] module"] +#[doc(alias = "TOTSAM_TOTSAM")] +pub type TotsamTotsam = crate::Reg; +#[doc = "Total Samples Register"] +pub mod totsam_totsam; +#[doc = "FRQMIN_FRQMIN (rw) register accessor: Frequency Count Minimum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmin_frqmin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmin_frqmin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqmin_frqmin`] module"] +#[doc(alias = "FRQMIN_FRQMIN")] +pub type FrqminFrqmin = crate::Reg; +#[doc = "Frequency Count Minimum Limit Register"] +pub mod frqmin_frqmin; +#[doc = "OSC2_FRQCNT_OSC2_FRQCNT (r) register accessor: Oscillator-2 Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_frqcnt_osc2_frqcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc2_frqcnt_osc2_frqcnt`] module"] +#[doc(alias = "OSC2_FRQCNT_OSC2_FRQCNT")] +pub type Osc2FrqcntOsc2Frqcnt = crate::Reg; +#[doc = "Oscillator-2 Frequency Count Register"] +pub mod osc2_frqcnt_osc2_frqcnt; +#[doc = "FRQCNT_FRQCNT (r) register accessor: Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqcnt_frqcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqcnt_frqcnt`] module"] +#[doc(alias = "FRQCNT_FRQCNT")] +pub type FrqcntFrqcnt = crate::Reg; +#[doc = "Frequency Count Register"] +pub mod frqcnt_frqcnt; +#[doc = "FRQMAX_FRQMAX (rw) register accessor: Frequency Count Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmax_frqmax::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmax_frqmax::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqmax_frqmax`] module"] +#[doc(alias = "FRQMAX_FRQMAX")] +pub type FrqmaxFrqmax = crate::Reg; +#[doc = "Frequency Count Maximum Limit Register"] +pub mod frqmax_frqmax; +#[doc = "SCMC_SCMC (r) register accessor: Statistical Check Monobit Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmc_scmc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scmc_scmc`] module"] +#[doc(alias = "SCMC_SCMC")] +pub type ScmcScmc = crate::Reg; +#[doc = "Statistical Check Monobit Count Register"] +pub mod scmc_scmc; +#[doc = "SCML_SCML (rw) register accessor: Statistical Check Monobit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scml_scml::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scml_scml::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scml_scml`] module"] +#[doc(alias = "SCML_SCML")] +pub type ScmlScml = crate::Reg; +#[doc = "Statistical Check Monobit Limit Register"] +pub mod scml_scml; +#[doc = "SCR1C_SCR1C (r) register accessor: Statistical Check Run Length 1 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1c_scr1c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr1c_scr1c`] module"] +#[doc(alias = "SCR1C_SCR1C")] +pub type Scr1cScr1c = crate::Reg; +#[doc = "Statistical Check Run Length 1 Count Register"] +pub mod scr1c_scr1c; +#[doc = "SCR1L_SCR1L (rw) register accessor: Statistical Check Run Length 1 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1l_scr1l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr1l_scr1l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr1l_scr1l`] module"] +#[doc(alias = "SCR1L_SCR1L")] +pub type Scr1lScr1l = crate::Reg; +#[doc = "Statistical Check Run Length 1 Limit Register"] +pub mod scr1l_scr1l; +#[doc = "SCR2C_SCR2C (r) register accessor: Statistical Check Run Length 2 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2c_scr2c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr2c_scr2c`] module"] +#[doc(alias = "SCR2C_SCR2C")] +pub type Scr2cScr2c = crate::Reg; +#[doc = "Statistical Check Run Length 2 Count Register"] +pub mod scr2c_scr2c; +#[doc = "SCR2L_SCR2L (rw) register accessor: Statistical Check Run Length 2 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2l_scr2l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr2l_scr2l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr2l_scr2l`] module"] +#[doc(alias = "SCR2L_SCR2L")] +pub type Scr2lScr2l = crate::Reg; +#[doc = "Statistical Check Run Length 2 Limit Register"] +pub mod scr2l_scr2l; +#[doc = "SCR3C_SCR3C (r) register accessor: Statistical Check Run Length 3 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3c_scr3c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr3c_scr3c`] module"] +#[doc(alias = "SCR3C_SCR3C")] +pub type Scr3cScr3c = crate::Reg; +#[doc = "Statistical Check Run Length 3 Count Register"] +pub mod scr3c_scr3c; +#[doc = "SCR3L_SCR3L (rw) register accessor: Statistical Check Run Length 3 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3l_scr3l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr3l_scr3l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr3l_scr3l`] module"] +#[doc(alias = "SCR3L_SCR3L")] +pub type Scr3lScr3l = crate::Reg; +#[doc = "Statistical Check Run Length 3 Limit Register"] +pub mod scr3l_scr3l; +#[doc = "SCR4C_SCR4C (r) register accessor: Statistical Check Run Length 4 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4c_scr4c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr4c_scr4c`] module"] +#[doc(alias = "SCR4C_SCR4C")] +pub type Scr4cScr4c = crate::Reg; +#[doc = "Statistical Check Run Length 4 Count Register"] +pub mod scr4c_scr4c; +#[doc = "SCR4L_SCR4L (rw) register accessor: Statistical Check Run Length 4 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4l_scr4l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr4l_scr4l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr4l_scr4l`] module"] +#[doc(alias = "SCR4L_SCR4L")] +pub type Scr4lScr4l = crate::Reg; +#[doc = "Statistical Check Run Length 4 Limit Register"] +pub mod scr4l_scr4l; +#[doc = "SCR5C_SCR5C (r) register accessor: Statistical Check Run Length 5 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5c_scr5c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr5c_scr5c`] module"] +#[doc(alias = "SCR5C_SCR5C")] +pub type Scr5cScr5c = crate::Reg; +#[doc = "Statistical Check Run Length 5 Count Register"] +pub mod scr5c_scr5c; +#[doc = "SCR5L_SCR5L (rw) register accessor: Statistical Check Run Length 5 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5l_scr5l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr5l_scr5l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr5l_scr5l`] module"] +#[doc(alias = "SCR5L_SCR5L")] +pub type Scr5lScr5l = crate::Reg; +#[doc = "Statistical Check Run Length 5 Limit Register"] +pub mod scr5l_scr5l; +#[doc = "SCR6PC_SCR6PC (r) register accessor: Statistical Check Run Length 6+ Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pc_scr6pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr6pc_scr6pc`] module"] +#[doc(alias = "SCR6PC_SCR6PC")] +pub type Scr6pcScr6pc = crate::Reg; +#[doc = "Statistical Check Run Length 6+ Count Register"] +pub mod scr6pc_scr6pc; +#[doc = "SCR6PL_SCR6PL (rw) register accessor: Statistical Check Run Length 6+ Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pl_scr6pl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr6pl_scr6pl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr6pl_scr6pl`] module"] +#[doc(alias = "SCR6PL_SCR6PL")] +pub type Scr6plScr6pl = crate::Reg; +#[doc = "Statistical Check Run Length 6+ Limit Register"] +pub mod scr6pl_scr6pl; +#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "ENT0 (r) register accessor: Entropy Read Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ent0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ent0`] module"] +#[doc(alias = "ENT0")] +pub type Ent0 = crate::Reg; +#[doc = "Entropy Read Register"] +pub mod ent0; +#[doc = "PKRCNT10 (r) register accessor: Statistical Check Poker Count 1 and 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt10`] module"] +#[doc(alias = "PKRCNT10")] +pub type Pkrcnt10 = crate::Reg; +#[doc = "Statistical Check Poker Count 1 and 0 Register"] +pub mod pkrcnt10; +#[doc = "PKRCNT32 (r) register accessor: Statistical Check Poker Count 3 and 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt32::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt32`] module"] +#[doc(alias = "PKRCNT32")] +pub type Pkrcnt32 = crate::Reg; +#[doc = "Statistical Check Poker Count 3 and 2 Register"] +pub mod pkrcnt32; +#[doc = "PKRCNT54 (r) register accessor: Statistical Check Poker Count 5 and 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt54::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt54`] module"] +#[doc(alias = "PKRCNT54")] +pub type Pkrcnt54 = crate::Reg; +#[doc = "Statistical Check Poker Count 5 and 4 Register"] +pub mod pkrcnt54; +#[doc = "PKRCNT76 (r) register accessor: Statistical Check Poker Count 7 and 6 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt76::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt76`] module"] +#[doc(alias = "PKRCNT76")] +pub type Pkrcnt76 = crate::Reg; +#[doc = "Statistical Check Poker Count 7 and 6 Register"] +pub mod pkrcnt76; +#[doc = "PKRCNT98 (r) register accessor: Statistical Check Poker Count 9 and 8 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt98::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt98`] module"] +#[doc(alias = "PKRCNT98")] +pub type Pkrcnt98 = crate::Reg; +#[doc = "Statistical Check Poker Count 9 and 8 Register"] +pub mod pkrcnt98; +#[doc = "PKRCNTBA (r) register accessor: Statistical Check Poker Count B and A Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntba::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntba`] module"] +#[doc(alias = "PKRCNTBA")] +pub type Pkrcntba = crate::Reg; +#[doc = "Statistical Check Poker Count B and A Register"] +pub mod pkrcntba; +#[doc = "PKRCNTDC (r) register accessor: Statistical Check Poker Count D and C Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntdc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntdc`] module"] +#[doc(alias = "PKRCNTDC")] +pub type Pkrcntdc = crate::Reg; +#[doc = "Statistical Check Poker Count D and C Register"] +pub mod pkrcntdc; +#[doc = "PKRCNTFE (r) register accessor: Statistical Check Poker Count F and E Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntfe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntfe`] module"] +#[doc(alias = "PKRCNTFE")] +pub type Pkrcntfe = crate::Reg; +#[doc = "Statistical Check Poker Count F and E Register"] +pub mod pkrcntfe; +#[doc = "SEC_CFG (rw) register accessor: Security Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_cfg`] module"] +#[doc(alias = "SEC_CFG")] +pub type SecCfg = crate::Reg; +#[doc = "Security Configuration Register"] +pub mod sec_cfg; +#[doc = "INT_CTRL (rw) register accessor: Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ctrl`] module"] +#[doc(alias = "INT_CTRL")] +pub type IntCtrl = crate::Reg; +#[doc = "Interrupt Control Register"] +pub mod int_ctrl; +#[doc = "INT_MASK (rw) register accessor: Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_mask`] module"] +#[doc(alias = "INT_MASK")] +pub type IntMask = crate::Reg; +#[doc = "Mask Register"] +pub mod int_mask; +#[doc = "INT_STATUS (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"] +#[doc(alias = "INT_STATUS")] +pub type IntStatus = crate::Reg; +#[doc = "Interrupt Status Register"] +pub mod int_status; +#[doc = "CSER (r) register accessor: Common Security Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cser::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cser`] module"] +#[doc(alias = "CSER")] +pub type Cser = crate::Reg; +#[doc = "Common Security Error Register"] +pub mod cser; +#[doc = "CSCLR (w) register accessor: Common Security Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csclr`] module"] +#[doc(alias = "CSCLR")] +pub type Csclr = crate::Reg; +#[doc = "Common Security Clear Register"] +pub mod csclr; +#[doc = "OSC2_CTL (rw) register accessor: TRNG Oscillator 2 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc2_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc2_ctl`] module"] +#[doc(alias = "OSC2_CTL")] +pub type Osc2Ctl = crate::Reg; +#[doc = "TRNG Oscillator 2 Control Register"] +pub mod osc2_ctl; +#[doc = "VID1 (r) register accessor: Version ID Register (MS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid1`] module"] +#[doc(alias = "VID1")] +pub type Vid1 = crate::Reg; +#[doc = "Version ID Register (MS)"] +pub mod vid1; +#[doc = "VID2 (r) register accessor: Version ID Register (LS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid2`] module"] +#[doc(alias = "VID2")] +pub type Vid2 = crate::Reg; +#[doc = "Version ID Register (LS)"] +pub mod vid2; diff --git a/mcxa276-pac/src/trng0/csclr.rs b/mcxa276-pac/src/trng0/csclr.rs new file mode 100644 index 000000000..e4ebc8107 --- /dev/null +++ b/mcxa276-pac/src/trng0/csclr.rs @@ -0,0 +1,159 @@ +#[doc = "Register `CSCLR` writer"] +pub type W = crate::W; +#[doc = "Redundant Signals error/fault Detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RedSigsClr { + #[doc = "0: No effect, ignored"] + RedSigsNoeffect = 0, + #[doc = "1: Clears the CSER\\[RED_SIGS\\] bit."] + RedSigsClear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RedSigsClr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RED_SIGS_CLR` writer - Redundant Signals error/fault Detected"] +pub type RedSigsClrW<'a, REG> = crate::BitWriter<'a, REG, RedSigsClr>; +impl<'a, REG> RedSigsClrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect, ignored"] + #[inline(always)] + pub fn red_sigs_noeffect(self) -> &'a mut crate::W { + self.variant(RedSigsClr::RedSigsNoeffect) + } + #[doc = "Clears the CSER\\[RED_SIGS\\] bit."] + #[inline(always)] + pub fn red_sigs_clear(self) -> &'a mut crate::W { + self.variant(RedSigsClr::RedSigsClear) + } +} +#[doc = "Read only: Redundant FSM error/fault detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RedFsmClr { + #[doc = "0: No effect, ignored"] + RedFsmNoeffect = 0, + #[doc = "1: Clears the CSER\\[RED_FSM\\] bit."] + RedFsmClear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RedFsmClr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RED_FSM_CLR` writer - Read only: Redundant FSM error/fault detected"] +pub type RedFsmClrW<'a, REG> = crate::BitWriter<'a, REG, RedFsmClr>; +impl<'a, REG> RedFsmClrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect, ignored"] + #[inline(always)] + pub fn red_fsm_noeffect(self) -> &'a mut crate::W { + self.variant(RedFsmClr::RedFsmNoeffect) + } + #[doc = "Clears the CSER\\[RED_FSM\\] bit."] + #[inline(always)] + pub fn red_fsm_clear(self) -> &'a mut crate::W { + self.variant(RedFsmClr::RedFsmClear) + } +} +#[doc = "Read only: Local-EDC error/fault detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LocalEdcClr { + #[doc = "0: No effect, ignored"] + LocalEdcNoeffect = 0, + #[doc = "1: Clears the CSER\\[LOCAL_EDC\\] bit."] + LocalEdcClear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LocalEdcClr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCAL_EDC_CLR` writer - Read only: Local-EDC error/fault detected"] +pub type LocalEdcClrW<'a, REG> = crate::BitWriter<'a, REG, LocalEdcClr>; +impl<'a, REG> LocalEdcClrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect, ignored"] + #[inline(always)] + pub fn local_edc_noeffect(self) -> &'a mut crate::W { + self.variant(LocalEdcClr::LocalEdcNoeffect) + } + #[doc = "Clears the CSER\\[LOCAL_EDC\\] bit."] + #[inline(always)] + pub fn local_edc_clear(self) -> &'a mut crate::W { + self.variant(LocalEdcClr::LocalEdcClear) + } +} +#[doc = "Read only: Bus-EDC error/fault detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum BusEdcClr { + #[doc = "0: No effect, ignored"] + BusEdcNoeffect = 0, + #[doc = "1: Clears the CSER\\[BUS_EDC\\] bit."] + BusEdcClear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BusEdcClr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUS_EDC_CLR` writer - Read only: Bus-EDC error/fault detected"] +pub type BusEdcClrW<'a, REG> = crate::BitWriter<'a, REG, BusEdcClr>; +impl<'a, REG> BusEdcClrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect, ignored"] + #[inline(always)] + pub fn bus_edc_noeffect(self) -> &'a mut crate::W { + self.variant(BusEdcClr::BusEdcNoeffect) + } + #[doc = "Clears the CSER\\[BUS_EDC\\] bit."] + #[inline(always)] + pub fn bus_edc_clear(self) -> &'a mut crate::W { + self.variant(BusEdcClr::BusEdcClear) + } +} +impl W { + #[doc = "Bit 0 - Redundant Signals error/fault Detected"] + #[inline(always)] + pub fn red_sigs_clr(&mut self) -> RedSigsClrW { + RedSigsClrW::new(self, 0) + } + #[doc = "Bit 1 - Read only: Redundant FSM error/fault detected"] + #[inline(always)] + pub fn red_fsm_clr(&mut self) -> RedFsmClrW { + RedFsmClrW::new(self, 1) + } + #[doc = "Bit 2 - Read only: Local-EDC error/fault detected"] + #[inline(always)] + pub fn local_edc_clr(&mut self) -> LocalEdcClrW { + LocalEdcClrW::new(self, 2) + } + #[doc = "Bit 3 - Read only: Bus-EDC error/fault detected"] + #[inline(always)] + pub fn bus_edc_clr(&mut self) -> BusEdcClrW { + BusEdcClrW::new(self, 3) + } +} +#[doc = "Common Security Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CsclrSpec; +impl crate::RegisterSpec for CsclrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`csclr::W`](W) writer structure"] +impl crate::Writable for CsclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CSCLR to value 0"] +impl crate::Resettable for CsclrSpec {} diff --git a/mcxa276-pac/src/trng0/cser.rs b/mcxa276-pac/src/trng0/cser.rs new file mode 100644 index 000000000..5b016dd7f --- /dev/null +++ b/mcxa276-pac/src/trng0/cser.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CSER` reader"] +pub type R = crate::R; +#[doc = "Redundant Signals error/fault Detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RedSigs { + #[doc = "0: No redundant signal error/fault"] + RedSigsNoerr = 0, + #[doc = "1: Redundant signal error/fault detected."] + RedSigsErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RedSigs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RED_SIGS` reader - Redundant Signals error/fault Detected"] +pub type RedSigsR = crate::BitReader; +impl RedSigsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RedSigs { + match self.bits { + false => RedSigs::RedSigsNoerr, + true => RedSigs::RedSigsErr, + } + } + #[doc = "No redundant signal error/fault"] + #[inline(always)] + pub fn is_red_sigs_noerr(&self) -> bool { + *self == RedSigs::RedSigsNoerr + } + #[doc = "Redundant signal error/fault detected."] + #[inline(always)] + pub fn is_red_sigs_err(&self) -> bool { + *self == RedSigs::RedSigsErr + } +} +#[doc = "Redundant FSM error/fault detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RedFsm { + #[doc = "0: No redundant FSM error/fault"] + RedFsmNoerr = 0, + #[doc = "1: Redundant FSM error/fault detected."] + RedFsmErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RedFsm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RED_FSM` reader - Redundant FSM error/fault detected"] +pub type RedFsmR = crate::BitReader; +impl RedFsmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RedFsm { + match self.bits { + false => RedFsm::RedFsmNoerr, + true => RedFsm::RedFsmErr, + } + } + #[doc = "No redundant FSM error/fault"] + #[inline(always)] + pub fn is_red_fsm_noerr(&self) -> bool { + *self == RedFsm::RedFsmNoerr + } + #[doc = "Redundant FSM error/fault detected."] + #[inline(always)] + pub fn is_red_fsm_err(&self) -> bool { + *self == RedFsm::RedFsmErr + } +} +#[doc = "Local-EDC error/fault detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LocalEdc { + #[doc = "0: No Local-EDC error/fault detected."] + LocalEdcNoerr = 0, + #[doc = "1: Local-EDC error/fault detected."] + LocalEdcErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LocalEdc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCAL_EDC` reader - Local-EDC error/fault detected"] +pub type LocalEdcR = crate::BitReader; +impl LocalEdcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LocalEdc { + match self.bits { + false => LocalEdc::LocalEdcNoerr, + true => LocalEdc::LocalEdcErr, + } + } + #[doc = "No Local-EDC error/fault detected."] + #[inline(always)] + pub fn is_local_edc_noerr(&self) -> bool { + *self == LocalEdc::LocalEdcNoerr + } + #[doc = "Local-EDC error/fault detected."] + #[inline(always)] + pub fn is_local_edc_err(&self) -> bool { + *self == LocalEdc::LocalEdcErr + } +} +#[doc = "Bus-EDC error/fault detected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum BusEdc { + #[doc = "0: No Bus-EDC error/fault detected."] + BusEdcNoerr = 0, + #[doc = "1: Bus-EDC error/fault detected."] + BusEdcErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BusEdc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BUS_EDC` reader - Bus-EDC error/fault detected"] +pub type BusEdcR = crate::BitReader; +impl BusEdcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> BusEdc { + match self.bits { + false => BusEdc::BusEdcNoerr, + true => BusEdc::BusEdcErr, + } + } + #[doc = "No Bus-EDC error/fault detected."] + #[inline(always)] + pub fn is_bus_edc_noerr(&self) -> bool { + *self == BusEdc::BusEdcNoerr + } + #[doc = "Bus-EDC error/fault detected."] + #[inline(always)] + pub fn is_bus_edc_err(&self) -> bool { + *self == BusEdc::BusEdcErr + } +} +impl R { + #[doc = "Bit 0 - Redundant Signals error/fault Detected"] + #[inline(always)] + pub fn red_sigs(&self) -> RedSigsR { + RedSigsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Redundant FSM error/fault detected"] + #[inline(always)] + pub fn red_fsm(&self) -> RedFsmR { + RedFsmR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Local-EDC error/fault detected"] + #[inline(always)] + pub fn local_edc(&self) -> LocalEdcR { + LocalEdcR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Bus-EDC error/fault detected"] + #[inline(always)] + pub fn bus_edc(&self) -> BusEdcR { + BusEdcR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Common Security Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cser::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CserSpec; +impl crate::RegisterSpec for CserSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cser::R`](R) reader structure"] +impl crate::Readable for CserSpec {} +#[doc = "`reset()` method sets CSER to value 0"] +impl crate::Resettable for CserSpec {} diff --git a/mcxa276-pac/src/trng0/ent0.rs b/mcxa276-pac/src/trng0/ent0.rs new file mode 100644 index 000000000..c21ea5b6e --- /dev/null +++ b/mcxa276-pac/src/trng0/ent0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `ENT0` reader"] +pub type R = crate::R; +#[doc = "Field `ENT` reader - Entropy Value"] +pub type EntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Entropy Value"] + #[inline(always)] + pub fn ent(&self) -> EntR { + EntR::new(self.bits) + } +} +#[doc = "Entropy Read Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ent0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ent0Spec; +impl crate::RegisterSpec for Ent0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ent0::R`](R) reader structure"] +impl crate::Readable for Ent0Spec {} +#[doc = "`reset()` method sets ENT0 to value 0"] +impl crate::Resettable for Ent0Spec {} diff --git a/mcxa276-pac/src/trng0/frqcnt_frqcnt.rs b/mcxa276-pac/src/trng0/frqcnt_frqcnt.rs new file mode 100644 index 000000000..aa9596c04 --- /dev/null +++ b/mcxa276-pac/src/trng0/frqcnt_frqcnt.rs @@ -0,0 +1,20 @@ +#[doc = "Register `FRQCNT` reader"] +pub type R = crate::R; +#[doc = "Field `FRQ_CT` reader - Frequency Count"] +pub type FrqCtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - Frequency Count"] + #[inline(always)] + pub fn frq_ct(&self) -> FrqCtR { + FrqCtR::new(self.bits & 0x003f_ffff) + } +} +#[doc = "Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqcnt_frqcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrqcntFrqcntSpec; +impl crate::RegisterSpec for FrqcntFrqcntSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`frqcnt_frqcnt::R`](R) reader structure"] +impl crate::Readable for FrqcntFrqcntSpec {} +#[doc = "`reset()` method sets FRQCNT to value 0"] +impl crate::Resettable for FrqcntFrqcntSpec {} diff --git a/mcxa276-pac/src/trng0/frqmax_frqmax.rs b/mcxa276-pac/src/trng0/frqmax_frqmax.rs new file mode 100644 index 000000000..9caed58c8 --- /dev/null +++ b/mcxa276-pac/src/trng0/frqmax_frqmax.rs @@ -0,0 +1,37 @@ +#[doc = "Register `FRQMAX` reader"] +pub type R = crate::R; +#[doc = "Register `FRQMAX` writer"] +pub type W = crate::W; +#[doc = "Field `FRQ_MAX` reader - Frequency Counter Maximum Limit"] +pub type FrqMaxR = crate::FieldReader; +#[doc = "Field `FRQ_MAX` writer - Frequency Counter Maximum Limit"] +pub type FrqMaxW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - Frequency Counter Maximum Limit"] + #[inline(always)] + pub fn frq_max(&self) -> FrqMaxR { + FrqMaxR::new(self.bits & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 0:21 - Frequency Counter Maximum Limit"] + #[inline(always)] + pub fn frq_max(&mut self) -> FrqMaxW { + FrqMaxW::new(self, 0) + } +} +#[doc = "Frequency Count Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmax_frqmax::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmax_frqmax::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrqmaxFrqmaxSpec; +impl crate::RegisterSpec for FrqmaxFrqmaxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`frqmax_frqmax::R`](R) reader structure"] +impl crate::Readable for FrqmaxFrqmaxSpec {} +#[doc = "`write(|w| ..)` method takes [`frqmax_frqmax::W`](W) writer structure"] +impl crate::Writable for FrqmaxFrqmaxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FRQMAX to value 0x6400"] +impl crate::Resettable for FrqmaxFrqmaxSpec { + const RESET_VALUE: u32 = 0x6400; +} diff --git a/mcxa276-pac/src/trng0/frqmin_frqmin.rs b/mcxa276-pac/src/trng0/frqmin_frqmin.rs new file mode 100644 index 000000000..5a717d15c --- /dev/null +++ b/mcxa276-pac/src/trng0/frqmin_frqmin.rs @@ -0,0 +1,37 @@ +#[doc = "Register `FRQMIN` reader"] +pub type R = crate::R; +#[doc = "Register `FRQMIN` writer"] +pub type W = crate::W; +#[doc = "Field `FRQ_MIN` reader - Frequency Count Minimum Limit"] +pub type FrqMinR = crate::FieldReader; +#[doc = "Field `FRQ_MIN` writer - Frequency Count Minimum Limit"] +pub type FrqMinW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - Frequency Count Minimum Limit"] + #[inline(always)] + pub fn frq_min(&self) -> FrqMinR { + FrqMinR::new(self.bits & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 0:21 - Frequency Count Minimum Limit"] + #[inline(always)] + pub fn frq_min(&mut self) -> FrqMinW { + FrqMinW::new(self, 0) + } +} +#[doc = "Frequency Count Minimum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmin_frqmin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmin_frqmin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrqminFrqminSpec; +impl crate::RegisterSpec for FrqminFrqminSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`frqmin_frqmin::R`](R) reader structure"] +impl crate::Readable for FrqminFrqminSpec {} +#[doc = "`write(|w| ..)` method takes [`frqmin_frqmin::W`](W) writer structure"] +impl crate::Writable for FrqminFrqminSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FRQMIN to value 0x0640"] +impl crate::Resettable for FrqminFrqminSpec { + const RESET_VALUE: u32 = 0x0640; +} diff --git a/mcxa276-pac/src/trng0/int_ctrl.rs b/mcxa276-pac/src/trng0/int_ctrl.rs new file mode 100644 index 000000000..5f74ee566 --- /dev/null +++ b/mcxa276-pac/src/trng0/int_ctrl.rs @@ -0,0 +1,275 @@ +#[doc = "Register `INT_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_CTRL` writer"] +pub type W = crate::W; +#[doc = "Clear the HW_ERR interrupt.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HwErr { + #[doc = "0: Clears the INT_STATUS\\[HW_ERR\\] bit. Will automatically set after writing."] + HwErrClear = 0, + #[doc = "1: Enables the INT_STATUS\\[HW_ERR\\] bit to be set, thereby enabling interrupt generation for the HW_ERR condition."] + HwErrOn = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HwErr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HW_ERR` reader - Clear the HW_ERR interrupt."] +pub type HwErrR = crate::BitReader; +impl HwErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> HwErr { + match self.bits { + false => HwErr::HwErrClear, + true => HwErr::HwErrOn, + } + } + #[doc = "Clears the INT_STATUS\\[HW_ERR\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn is_hw_err_clear(&self) -> bool { + *self == HwErr::HwErrClear + } + #[doc = "Enables the INT_STATUS\\[HW_ERR\\] bit to be set, thereby enabling interrupt generation for the HW_ERR condition."] + #[inline(always)] + pub fn is_hw_err_on(&self) -> bool { + *self == HwErr::HwErrOn + } +} +#[doc = "Field `HW_ERR` writer - Clear the HW_ERR interrupt."] +pub type HwErrW<'a, REG> = crate::BitWriter<'a, REG, HwErr>; +impl<'a, REG> HwErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Clears the INT_STATUS\\[HW_ERR\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn hw_err_clear(self) -> &'a mut crate::W { + self.variant(HwErr::HwErrClear) + } + #[doc = "Enables the INT_STATUS\\[HW_ERR\\] bit to be set, thereby enabling interrupt generation for the HW_ERR condition."] + #[inline(always)] + pub fn hw_err_on(self) -> &'a mut crate::W { + self.variant(HwErr::HwErrOn) + } +} +#[doc = "Clear the ENT_VAL interrupt.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EntVal { + #[doc = "0: Clears the INT_STATUS\\[ENT_VAL\\] bit. Will automatically set after writing."] + EntValClear = 0, + #[doc = "1: Enables the INT_STATUS\\[ENT_VAL\\] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition."] + EntValOn = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EntVal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENT_VAL` reader - Clear the ENT_VAL interrupt."] +pub type EntValR = crate::BitReader; +impl EntValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EntVal { + match self.bits { + false => EntVal::EntValClear, + true => EntVal::EntValOn, + } + } + #[doc = "Clears the INT_STATUS\\[ENT_VAL\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn is_ent_val_clear(&self) -> bool { + *self == EntVal::EntValClear + } + #[doc = "Enables the INT_STATUS\\[ENT_VAL\\] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition."] + #[inline(always)] + pub fn is_ent_val_on(&self) -> bool { + *self == EntVal::EntValOn + } +} +#[doc = "Field `ENT_VAL` writer - Clear the ENT_VAL interrupt."] +pub type EntValW<'a, REG> = crate::BitWriter<'a, REG, EntVal>; +impl<'a, REG> EntValW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Clears the INT_STATUS\\[ENT_VAL\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn ent_val_clear(self) -> &'a mut crate::W { + self.variant(EntVal::EntValClear) + } + #[doc = "Enables the INT_STATUS\\[ENT_VAL\\] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition."] + #[inline(always)] + pub fn ent_val_on(self) -> &'a mut crate::W { + self.variant(EntVal::EntValOn) + } +} +#[doc = "Clear the FRQ_CT_FAIL interrupt.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FrqCtFail { + #[doc = "0: Clears the INT_STATUS\\[FRQ_CT_FAIL\\] bit. Will automatically set after writing."] + FrqCtFailClear = 0, + #[doc = "1: Enables the INT_STATUS\\[FRQ_CT_FAIL\\] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition."] + FrqCtFailOn = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FrqCtFail) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRQ_CT_FAIL` reader - Clear the FRQ_CT_FAIL interrupt."] +pub type FrqCtFailR = crate::BitReader; +impl FrqCtFailR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FrqCtFail { + match self.bits { + false => FrqCtFail::FrqCtFailClear, + true => FrqCtFail::FrqCtFailOn, + } + } + #[doc = "Clears the INT_STATUS\\[FRQ_CT_FAIL\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn is_frq_ct_fail_clear(&self) -> bool { + *self == FrqCtFail::FrqCtFailClear + } + #[doc = "Enables the INT_STATUS\\[FRQ_CT_FAIL\\] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition."] + #[inline(always)] + pub fn is_frq_ct_fail_on(&self) -> bool { + *self == FrqCtFail::FrqCtFailOn + } +} +#[doc = "Field `FRQ_CT_FAIL` writer - Clear the FRQ_CT_FAIL interrupt."] +pub type FrqCtFailW<'a, REG> = crate::BitWriter<'a, REG, FrqCtFail>; +impl<'a, REG> FrqCtFailW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Clears the INT_STATUS\\[FRQ_CT_FAIL\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn frq_ct_fail_clear(self) -> &'a mut crate::W { + self.variant(FrqCtFail::FrqCtFailClear) + } + #[doc = "Enables the INT_STATUS\\[FRQ_CT_FAIL\\] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition."] + #[inline(always)] + pub fn frq_ct_fail_on(self) -> &'a mut crate::W { + self.variant(FrqCtFail::FrqCtFailOn) + } +} +#[doc = "Clear the INTG_FLT interrupt.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IntgFlt { + #[doc = "0: Clears the INT_STATUS\\[INTG_FLT\\] bit. Will automatically set after writing."] + IntgFltClear = 0, + #[doc = "1: Enables the INT_STATUS\\[INTG_FLT\\] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition."] + IntgFltOn = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IntgFlt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTG_FLT` reader - Clear the INTG_FLT interrupt."] +pub type IntgFltR = crate::BitReader; +impl IntgFltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IntgFlt { + match self.bits { + false => IntgFlt::IntgFltClear, + true => IntgFlt::IntgFltOn, + } + } + #[doc = "Clears the INT_STATUS\\[INTG_FLT\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn is_intg_flt_clear(&self) -> bool { + *self == IntgFlt::IntgFltClear + } + #[doc = "Enables the INT_STATUS\\[INTG_FLT\\] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition."] + #[inline(always)] + pub fn is_intg_flt_on(&self) -> bool { + *self == IntgFlt::IntgFltOn + } +} +#[doc = "Field `INTG_FLT` writer - Clear the INTG_FLT interrupt."] +pub type IntgFltW<'a, REG> = crate::BitWriter<'a, REG, IntgFlt>; +impl<'a, REG> IntgFltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Clears the INT_STATUS\\[INTG_FLT\\] bit. Will automatically set after writing."] + #[inline(always)] + pub fn intg_flt_clear(self) -> &'a mut crate::W { + self.variant(IntgFlt::IntgFltClear) + } + #[doc = "Enables the INT_STATUS\\[INTG_FLT\\] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition."] + #[inline(always)] + pub fn intg_flt_on(self) -> &'a mut crate::W { + self.variant(IntgFlt::IntgFltOn) + } +} +impl R { + #[doc = "Bit 0 - Clear the HW_ERR interrupt."] + #[inline(always)] + pub fn hw_err(&self) -> HwErrR { + HwErrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clear the ENT_VAL interrupt."] + #[inline(always)] + pub fn ent_val(&self) -> EntValR { + EntValR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Clear the FRQ_CT_FAIL interrupt."] + #[inline(always)] + pub fn frq_ct_fail(&self) -> FrqCtFailR { + FrqCtFailR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clear the INTG_FLT interrupt."] + #[inline(always)] + pub fn intg_flt(&self) -> IntgFltR { + IntgFltR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clear the HW_ERR interrupt."] + #[inline(always)] + pub fn hw_err(&mut self) -> HwErrW { + HwErrW::new(self, 0) + } + #[doc = "Bit 1 - Clear the ENT_VAL interrupt."] + #[inline(always)] + pub fn ent_val(&mut self) -> EntValW { + EntValW::new(self, 1) + } + #[doc = "Bit 2 - Clear the FRQ_CT_FAIL interrupt."] + #[inline(always)] + pub fn frq_ct_fail(&mut self) -> FrqCtFailW { + FrqCtFailW::new(self, 2) + } + #[doc = "Bit 3 - Clear the INTG_FLT interrupt."] + #[inline(always)] + pub fn intg_flt(&mut self) -> IntgFltW { + IntgFltW::new(self, 3) + } +} +#[doc = "Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntCtrlSpec; +impl crate::RegisterSpec for IntCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ctrl::R`](R) reader structure"] +impl crate::Readable for IntCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`int_ctrl::W`](W) writer structure"] +impl crate::Writable for IntCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets INT_CTRL to value 0x0f"] +impl crate::Resettable for IntCtrlSpec { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/mcxa276-pac/src/trng0/int_mask.rs b/mcxa276-pac/src/trng0/int_mask.rs new file mode 100644 index 000000000..9fa936199 --- /dev/null +++ b/mcxa276-pac/src/trng0/int_mask.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INT_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MASK` writer"] +pub type W = crate::W; +#[doc = "Mask the HW_ERR interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HwErr { + #[doc = "0: HW_ERR interrupt is disabled."] + HwErrMasked = 0, + #[doc = "1: HW_ERR interrupt is enabled."] + HwErrActive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HwErr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HW_ERR` reader - Mask the HW_ERR interrupt."] +pub type HwErrR = crate::BitReader; +impl HwErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> HwErr { + match self.bits { + false => HwErr::HwErrMasked, + true => HwErr::HwErrActive, + } + } + #[doc = "HW_ERR interrupt is disabled."] + #[inline(always)] + pub fn is_hw_err_masked(&self) -> bool { + *self == HwErr::HwErrMasked + } + #[doc = "HW_ERR interrupt is enabled."] + #[inline(always)] + pub fn is_hw_err_active(&self) -> bool { + *self == HwErr::HwErrActive + } +} +#[doc = "Field `HW_ERR` writer - Mask the HW_ERR interrupt."] +pub type HwErrW<'a, REG> = crate::BitWriter<'a, REG, HwErr>; +impl<'a, REG> HwErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "HW_ERR interrupt is disabled."] + #[inline(always)] + pub fn hw_err_masked(self) -> &'a mut crate::W { + self.variant(HwErr::HwErrMasked) + } + #[doc = "HW_ERR interrupt is enabled."] + #[inline(always)] + pub fn hw_err_active(self) -> &'a mut crate::W { + self.variant(HwErr::HwErrActive) + } +} +#[doc = "Mask the ENT_VAL interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EntVal { + #[doc = "0: ENT_VAL interrupt is disabled."] + EntValMasked = 0, + #[doc = "1: ENT_VAL interrupt is enabled."] + EntValActive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EntVal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENT_VAL` reader - Mask the ENT_VAL interrupt."] +pub type EntValR = crate::BitReader; +impl EntValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EntVal { + match self.bits { + false => EntVal::EntValMasked, + true => EntVal::EntValActive, + } + } + #[doc = "ENT_VAL interrupt is disabled."] + #[inline(always)] + pub fn is_ent_val_masked(&self) -> bool { + *self == EntVal::EntValMasked + } + #[doc = "ENT_VAL interrupt is enabled."] + #[inline(always)] + pub fn is_ent_val_active(&self) -> bool { + *self == EntVal::EntValActive + } +} +#[doc = "Field `ENT_VAL` writer - Mask the ENT_VAL interrupt."] +pub type EntValW<'a, REG> = crate::BitWriter<'a, REG, EntVal>; +impl<'a, REG> EntValW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ENT_VAL interrupt is disabled."] + #[inline(always)] + pub fn ent_val_masked(self) -> &'a mut crate::W { + self.variant(EntVal::EntValMasked) + } + #[doc = "ENT_VAL interrupt is enabled."] + #[inline(always)] + pub fn ent_val_active(self) -> &'a mut crate::W { + self.variant(EntVal::EntValActive) + } +} +#[doc = "Mask the FRQ_CT_FAIL interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FrqCtFail { + #[doc = "0: FRQ_CT_FAIL interrupt is disabled."] + FrqCtFailMasked = 0, + #[doc = "1: FRQ_CT_FAIL interrupt is enabled."] + FrqCtFailActive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FrqCtFail) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRQ_CT_FAIL` reader - Mask the FRQ_CT_FAIL interrupt."] +pub type FrqCtFailR = crate::BitReader; +impl FrqCtFailR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FrqCtFail { + match self.bits { + false => FrqCtFail::FrqCtFailMasked, + true => FrqCtFail::FrqCtFailActive, + } + } + #[doc = "FRQ_CT_FAIL interrupt is disabled."] + #[inline(always)] + pub fn is_frq_ct_fail_masked(&self) -> bool { + *self == FrqCtFail::FrqCtFailMasked + } + #[doc = "FRQ_CT_FAIL interrupt is enabled."] + #[inline(always)] + pub fn is_frq_ct_fail_active(&self) -> bool { + *self == FrqCtFail::FrqCtFailActive + } +} +#[doc = "Field `FRQ_CT_FAIL` writer - Mask the FRQ_CT_FAIL interrupt."] +pub type FrqCtFailW<'a, REG> = crate::BitWriter<'a, REG, FrqCtFail>; +impl<'a, REG> FrqCtFailW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "FRQ_CT_FAIL interrupt is disabled."] + #[inline(always)] + pub fn frq_ct_fail_masked(self) -> &'a mut crate::W { + self.variant(FrqCtFail::FrqCtFailMasked) + } + #[doc = "FRQ_CT_FAIL interrupt is enabled."] + #[inline(always)] + pub fn frq_ct_fail_active(self) -> &'a mut crate::W { + self.variant(FrqCtFail::FrqCtFailActive) + } +} +#[doc = "Mask the INTG_FLT interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IntgFlt { + #[doc = "0: INTG_FLT interrupt is disabled."] + IntgFltMasked = 0, + #[doc = "1: INTG_FLT interrupt is enabled."] + IntgFltActive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IntgFlt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTG_FLT` reader - Mask the INTG_FLT interrupt."] +pub type IntgFltR = crate::BitReader; +impl IntgFltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IntgFlt { + match self.bits { + false => IntgFlt::IntgFltMasked, + true => IntgFlt::IntgFltActive, + } + } + #[doc = "INTG_FLT interrupt is disabled."] + #[inline(always)] + pub fn is_intg_flt_masked(&self) -> bool { + *self == IntgFlt::IntgFltMasked + } + #[doc = "INTG_FLT interrupt is enabled."] + #[inline(always)] + pub fn is_intg_flt_active(&self) -> bool { + *self == IntgFlt::IntgFltActive + } +} +#[doc = "Field `INTG_FLT` writer - Mask the INTG_FLT interrupt."] +pub type IntgFltW<'a, REG> = crate::BitWriter<'a, REG, IntgFlt>; +impl<'a, REG> IntgFltW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "INTG_FLT interrupt is disabled."] + #[inline(always)] + pub fn intg_flt_masked(self) -> &'a mut crate::W { + self.variant(IntgFlt::IntgFltMasked) + } + #[doc = "INTG_FLT interrupt is enabled."] + #[inline(always)] + pub fn intg_flt_active(self) -> &'a mut crate::W { + self.variant(IntgFlt::IntgFltActive) + } +} +impl R { + #[doc = "Bit 0 - Mask the HW_ERR interrupt."] + #[inline(always)] + pub fn hw_err(&self) -> HwErrR { + HwErrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mask the ENT_VAL interrupt."] + #[inline(always)] + pub fn ent_val(&self) -> EntValR { + EntValR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Mask the FRQ_CT_FAIL interrupt."] + #[inline(always)] + pub fn frq_ct_fail(&self) -> FrqCtFailR { + FrqCtFailR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Mask the INTG_FLT interrupt."] + #[inline(always)] + pub fn intg_flt(&self) -> IntgFltR { + IntgFltR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Mask the HW_ERR interrupt."] + #[inline(always)] + pub fn hw_err(&mut self) -> HwErrW { + HwErrW::new(self, 0) + } + #[doc = "Bit 1 - Mask the ENT_VAL interrupt."] + #[inline(always)] + pub fn ent_val(&mut self) -> EntValW { + EntValW::new(self, 1) + } + #[doc = "Bit 2 - Mask the FRQ_CT_FAIL interrupt."] + #[inline(always)] + pub fn frq_ct_fail(&mut self) -> FrqCtFailW { + FrqCtFailW::new(self, 2) + } + #[doc = "Bit 3 - Mask the INTG_FLT interrupt."] + #[inline(always)] + pub fn intg_flt(&mut self) -> IntgFltW { + IntgFltW::new(self, 3) + } +} +#[doc = "Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntMaskSpec; +impl crate::RegisterSpec for IntMaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_mask::R`](R) reader structure"] +impl crate::Readable for IntMaskSpec {} +#[doc = "`write(|w| ..)` method takes [`int_mask::W`](W) writer structure"] +impl crate::Writable for IntMaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets INT_MASK to value 0"] +impl crate::Resettable for IntMaskSpec {} diff --git a/mcxa276-pac/src/trng0/int_status.rs b/mcxa276-pac/src/trng0/int_status.rs new file mode 100644 index 000000000..b2afb31c2 --- /dev/null +++ b/mcxa276-pac/src/trng0/int_status.rs @@ -0,0 +1,177 @@ +#[doc = "Register `INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Read: TRNG Error. Any error in the TRNG will trigger this interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HwErr { + #[doc = "0: No error."] + HwErrNo = 0, + #[doc = "1: Error detected."] + HwErrYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HwErr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HW_ERR` reader - Read: TRNG Error. Any error in the TRNG will trigger this interrupt."] +pub type HwErrR = crate::BitReader; +impl HwErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> HwErr { + match self.bits { + false => HwErr::HwErrNo, + true => HwErr::HwErrYes, + } + } + #[doc = "No error."] + #[inline(always)] + pub fn is_hw_err_no(&self) -> bool { + *self == HwErr::HwErrNo + } + #[doc = "Error detected."] + #[inline(always)] + pub fn is_hw_err_yes(&self) -> bool { + *self == HwErr::HwErrYes + } +} +#[doc = "Entropy Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EntVal { + #[doc = "0: Busy generating entropy. Any value read from the Entropy registers is invalid."] + EntValInvalid = 0, + #[doc = "1: Values read from the Entropy registers are valid."] + EntValValid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EntVal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENT_VAL` reader - Entropy Valid"] +pub type EntValR = crate::BitReader; +impl EntValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EntVal { + match self.bits { + false => EntVal::EntValInvalid, + true => EntVal::EntValValid, + } + } + #[doc = "Busy generating entropy. Any value read from the Entropy registers is invalid."] + #[inline(always)] + pub fn is_ent_val_invalid(&self) -> bool { + *self == EntVal::EntValInvalid + } + #[doc = "Values read from the Entropy registers are valid."] + #[inline(always)] + pub fn is_ent_val_valid(&self) -> bool { + *self == EntVal::EntValValid + } +} +#[doc = "Frequency Count Fail\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FrqCtFail { + #[doc = "0: No hardware nor self test frequency errors."] + FrqCtFailNoErr = 0, + #[doc = "1: The frequency counter has detected a failure."] + FrqCtFailErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FrqCtFail) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRQ_CT_FAIL` reader - Frequency Count Fail"] +pub type FrqCtFailR = crate::BitReader; +impl FrqCtFailR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FrqCtFail { + match self.bits { + false => FrqCtFail::FrqCtFailNoErr, + true => FrqCtFail::FrqCtFailErr, + } + } + #[doc = "No hardware nor self test frequency errors."] + #[inline(always)] + pub fn is_frq_ct_fail_no_err(&self) -> bool { + *self == FrqCtFail::FrqCtFailNoErr + } + #[doc = "The frequency counter has detected a failure."] + #[inline(always)] + pub fn is_frq_ct_fail_err(&self) -> bool { + *self == FrqCtFail::FrqCtFailErr + } +} +#[doc = "Integrity Fault. An internal fault has occurred.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IntgFlt { + #[doc = "0: No internal fault has been detected."] + IntgFltNoErr = 0, + #[doc = "1: TRNG has detected internal fault."] + IntgFltErr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IntgFlt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTG_FLT` reader - Integrity Fault. An internal fault has occurred."] +pub type IntgFltR = crate::BitReader; +impl IntgFltR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IntgFlt { + match self.bits { + false => IntgFlt::IntgFltNoErr, + true => IntgFlt::IntgFltErr, + } + } + #[doc = "No internal fault has been detected."] + #[inline(always)] + pub fn is_intg_flt_no_err(&self) -> bool { + *self == IntgFlt::IntgFltNoErr + } + #[doc = "TRNG has detected internal fault."] + #[inline(always)] + pub fn is_intg_flt_err(&self) -> bool { + *self == IntgFlt::IntgFltErr + } +} +impl R { + #[doc = "Bit 0 - Read: TRNG Error. Any error in the TRNG will trigger this interrupt."] + #[inline(always)] + pub fn hw_err(&self) -> HwErrR { + HwErrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Entropy Valid"] + #[inline(always)] + pub fn ent_val(&self) -> EntValR { + EntValR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Frequency Count Fail"] + #[inline(always)] + pub fn frq_ct_fail(&self) -> FrqCtFailR { + FrqCtFailR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Integrity Fault. An internal fault has occurred."] + #[inline(always)] + pub fn intg_flt(&self) -> IntgFltR { + IntgFltR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntStatusSpec; +impl crate::RegisterSpec for IntStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_status::R`](R) reader structure"] +impl crate::Readable for IntStatusSpec {} +#[doc = "`reset()` method sets INT_STATUS to value 0"] +impl crate::Resettable for IntStatusSpec {} diff --git a/mcxa276-pac/src/trng0/mctl.rs b/mcxa276-pac/src/trng0/mctl.rs new file mode 100644 index 000000000..f86c45532 --- /dev/null +++ b/mcxa276-pac/src/trng0/mctl.rs @@ -0,0 +1,515 @@ +#[doc = "Register `MCTL` reader"] +pub type R = crate::R; +#[doc = "Register `MCTL` writer"] +pub type W = crate::W; +#[doc = "Oscillator1 Divide\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OscDiv { + #[doc = "0: use ring oscillator with no divide"] + OscDivDiv1 = 0, + #[doc = "1: use ring oscillator divided-by-2"] + OscDivDiv2 = 1, + #[doc = "2: use ring oscillator divided-by-4"] + OscDivDiv4 = 2, + #[doc = "3: use ring oscillator divided-by-8"] + OscDivDiv8 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OscDiv) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OscDiv { + type Ux = u8; +} +impl crate::IsEnum for OscDiv {} +#[doc = "Field `OSC_DIV` reader - Oscillator1 Divide"] +pub type OscDivR = crate::FieldReader; +impl OscDivR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OscDiv { + match self.bits { + 0 => OscDiv::OscDivDiv1, + 1 => OscDiv::OscDivDiv2, + 2 => OscDiv::OscDivDiv4, + 3 => OscDiv::OscDivDiv8, + _ => unreachable!(), + } + } + #[doc = "use ring oscillator with no divide"] + #[inline(always)] + pub fn is_osc_div_div1(&self) -> bool { + *self == OscDiv::OscDivDiv1 + } + #[doc = "use ring oscillator divided-by-2"] + #[inline(always)] + pub fn is_osc_div_div2(&self) -> bool { + *self == OscDiv::OscDivDiv2 + } + #[doc = "use ring oscillator divided-by-4"] + #[inline(always)] + pub fn is_osc_div_div4(&self) -> bool { + *self == OscDiv::OscDivDiv4 + } + #[doc = "use ring oscillator divided-by-8"] + #[inline(always)] + pub fn is_osc_div_div8(&self) -> bool { + *self == OscDiv::OscDivDiv8 + } +} +#[doc = "Field `OSC_DIV` writer - Oscillator1 Divide"] +pub type OscDivW<'a, REG> = crate::FieldWriter<'a, REG, 2, OscDiv, crate::Safe>; +impl<'a, REG> OscDivW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "use ring oscillator with no divide"] + #[inline(always)] + pub fn osc_div_div1(self) -> &'a mut crate::W { + self.variant(OscDiv::OscDivDiv1) + } + #[doc = "use ring oscillator divided-by-2"] + #[inline(always)] + pub fn osc_div_div2(self) -> &'a mut crate::W { + self.variant(OscDiv::OscDivDiv2) + } + #[doc = "use ring oscillator divided-by-4"] + #[inline(always)] + pub fn osc_div_div4(self) -> &'a mut crate::W { + self.variant(OscDiv::OscDivDiv4) + } + #[doc = "use ring oscillator divided-by-8"] + #[inline(always)] + pub fn osc_div_div8(self) -> &'a mut crate::W { + self.variant(OscDiv::OscDivDiv8) + } +} +#[doc = "Field `DIS_SLF_TST` writer - Disable Self-Tests"] +pub type DisSlfTstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRNG_ACC` reader - TRNG Access Mode"] +pub type TrngAccR = crate::BitReader; +#[doc = "Field `TRNG_ACC` writer - TRNG Access Mode"] +pub type TrngAccW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Reset Defaults\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RstDef { + #[doc = "0: No impact."] + Disable = 0, + #[doc = "1: Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RstDef) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RST_DEF` writer - Reset Defaults"] +pub type RstDefW<'a, REG> = crate::BitWriter<'a, REG, RstDef>; +impl<'a, REG> RstDefW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No impact."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RstDef::Disable) + } + #[doc = "Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RstDef::Enable) + } +} +#[doc = "Field `FCT_FAIL` reader - Frequency Count Fail"] +pub type FctFailR = crate::BitReader; +#[doc = "Frequency Count Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FctVal { + #[doc = "0: Frequency Count is not valid"] + Disable = 0, + #[doc = "1: Frequency Count is valid"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FctVal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FCT_VAL` reader - Frequency Count Valid"] +pub type FctValR = crate::BitReader; +impl FctValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FctVal { + match self.bits { + false => FctVal::Disable, + true => FctVal::Enable, + } + } + #[doc = "Frequency Count is not valid"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == FctVal::Disable + } + #[doc = "Frequency Count is valid"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == FctVal::Enable + } +} +#[doc = "Entropy Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EntVal { + #[doc = "0: Entropy is not valid"] + Disable = 0, + #[doc = "1: Entropy is valid"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EntVal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENT_VAL` reader - Entropy Valid"] +pub type EntValR = crate::BitReader; +impl EntValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EntVal { + match self.bits { + false => EntVal::Disable, + true => EntVal::Enable, + } + } + #[doc = "Entropy is not valid"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == EntVal::Disable + } + #[doc = "Entropy is valid"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == EntVal::Enable + } +} +#[doc = "Error Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Err { + #[doc = "0: No error"] + Disable = 0, + #[doc = "1: Error detected"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Err) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERR` reader - Error Status"] +pub type ErrR = crate::BitReader; +impl ErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Err { + match self.bits { + false => Err::Disable, + true => Err::Enable, + } + } + #[doc = "No error"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Err::Disable + } + #[doc = "Error detected"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Err::Enable + } +} +#[doc = "Field `ERR` writer - Error Status"] +pub type ErrW<'a, REG> = crate::BitWriter1C<'a, REG, Err>; +impl<'a, REG> ErrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No error"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Err::Disable) + } + #[doc = "Error detected"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Err::Enable) + } +} +#[doc = "TRNG is ok to stop\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TstopOk { + #[doc = "0: TRNG is generating entropy and is not ok to stop"] + Disable = 0, + #[doc = "1: TRNG is not generating entropy and is ok to stop"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TstopOk) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TSTOP_OK` reader - TRNG is ok to stop"] +pub type TstopOkR = crate::BitReader; +impl TstopOkR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TstopOk { + match self.bits { + false => TstopOk::Disable, + true => TstopOk::Enable, + } + } + #[doc = "TRNG is generating entropy and is not ok to stop"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == TstopOk::Disable + } + #[doc = "TRNG is not generating entropy and is ok to stop"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == TstopOk::Enable + } +} +#[doc = "Oscillator 2 Failure\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Osc2Fail { + #[doc = "0: Oscillator 2 is running."] + Disable = 0, + #[doc = "1: Oscillator 2 has failed (see OSC2_CTL\\[OSC_FAILSAFE_LMT\\])."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Osc2Fail) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSC2_FAIL` reader - Oscillator 2 Failure"] +pub type Osc2FailR = crate::BitReader; +impl Osc2FailR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Osc2Fail { + match self.bits { + false => Osc2Fail::Disable, + true => Osc2Fail::Enable, + } + } + #[doc = "Oscillator 2 is running."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Osc2Fail::Disable + } + #[doc = "Oscillator 2 has failed (see OSC2_CTL\\[OSC_FAILSAFE_LMT\\])."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Osc2Fail::Enable + } +} +#[doc = "Program Mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Prgm { + #[doc = "0: TRNG is in Run Mode"] + Disable = 0, + #[doc = "1: TRNG is in Program Mode"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Prgm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PRGM` reader - Program Mode"] +pub type PrgmR = crate::BitReader; +impl PrgmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Prgm { + match self.bits { + false => Prgm::Disable, + true => Prgm::Enable, + } + } + #[doc = "TRNG is in Run Mode"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Prgm::Disable + } + #[doc = "TRNG is in Program Mode"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Prgm::Enable + } +} +#[doc = "Field `PRGM` writer - Program Mode"] +pub type PrgmW<'a, REG> = crate::BitWriter<'a, REG, Prgm>; +impl<'a, REG> PrgmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "TRNG is in Run Mode"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Prgm::Disable) + } + #[doc = "TRNG is in Program Mode"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Prgm::Enable) + } +} +#[doc = "Integrity Error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IntgErr { + #[doc = "0: TRNG detected no internal bit error"] + Disable = 0, + #[doc = "1: TRNG detected internal bit error(s)"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IntgErr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTG_ERR` reader - Integrity Error"] +pub type IntgErrR = crate::BitReader; +impl IntgErrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IntgErr { + match self.bits { + false => IntgErr::Disable, + true => IntgErr::Enable, + } + } + #[doc = "TRNG detected no internal bit error"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IntgErr::Disable + } + #[doc = "TRNG detected internal bit error(s)"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IntgErr::Enable + } +} +impl R { + #[doc = "Bits 2:3 - Oscillator1 Divide"] + #[inline(always)] + pub fn osc_div(&self) -> OscDivR { + OscDivR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 5 - TRNG Access Mode"] + #[inline(always)] + pub fn trng_acc(&self) -> TrngAccR { + TrngAccR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Frequency Count Fail"] + #[inline(always)] + pub fn fct_fail(&self) -> FctFailR { + FctFailR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frequency Count Valid"] + #[inline(always)] + pub fn fct_val(&self) -> FctValR { + FctValR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Entropy Valid"] + #[inline(always)] + pub fn ent_val(&self) -> EntValR { + EntValR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Error Status"] + #[inline(always)] + pub fn err(&self) -> ErrR { + ErrR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TRNG is ok to stop"] + #[inline(always)] + pub fn tstop_ok(&self) -> TstopOkR { + TstopOkR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Oscillator 2 Failure"] + #[inline(always)] + pub fn osc2_fail(&self) -> Osc2FailR { + Osc2FailR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Program Mode"] + #[inline(always)] + pub fn prgm(&self) -> PrgmR { + PrgmR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 31 - Integrity Error"] + #[inline(always)] + pub fn intg_err(&self) -> IntgErrR { + IntgErrR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:3 - Oscillator1 Divide"] + #[inline(always)] + pub fn osc_div(&mut self) -> OscDivW { + OscDivW::new(self, 2) + } + #[doc = "Bit 4 - Disable Self-Tests"] + #[inline(always)] + pub fn dis_slf_tst(&mut self) -> DisSlfTstW { + DisSlfTstW::new(self, 4) + } + #[doc = "Bit 5 - TRNG Access Mode"] + #[inline(always)] + pub fn trng_acc(&mut self) -> TrngAccW { + TrngAccW::new(self, 5) + } + #[doc = "Bit 6 - Reset Defaults"] + #[inline(always)] + pub fn rst_def(&mut self) -> RstDefW { + RstDefW::new(self, 6) + } + #[doc = "Bit 12 - Error Status"] + #[inline(always)] + pub fn err(&mut self) -> ErrW { + ErrW::new(self, 12) + } + #[doc = "Bit 16 - Program Mode"] + #[inline(always)] + pub fn prgm(&mut self) -> PrgmW { + PrgmW::new(self, 16) + } +} +#[doc = "Miscellaneous Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MctlSpec; +impl crate::RegisterSpec for MctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mctl::R`](R) reader structure"] +impl crate::Readable for MctlSpec {} +#[doc = "`write(|w| ..)` method takes [`mctl::W`](W) writer structure"] +impl crate::Writable for MctlSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1000; +} +#[doc = "`reset()` method sets MCTL to value 0x0001_2000"] +impl crate::Resettable for MctlSpec { + const RESET_VALUE: u32 = 0x0001_2000; +} diff --git a/mcxa276-pac/src/trng0/osc2_ctl.rs b/mcxa276-pac/src/trng0/osc2_ctl.rs new file mode 100644 index 000000000..09cef0601 --- /dev/null +++ b/mcxa276-pac/src/trng0/osc2_ctl.rs @@ -0,0 +1,478 @@ +#[doc = "Register `OSC2_CTL` reader"] +pub type R = crate::R; +#[doc = "Register `OSC2_CTL` writer"] +pub type W = crate::W; +#[doc = "TRNG entropy generation control.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TrngEntCtl { + #[doc = "0: Single oscillator mode, using OSC1 (default)"] + TrngEntCtlSingleOsc1 = 0, + #[doc = "1: Dual oscillator mode"] + TrngEntCtlDualOscs = 1, + #[doc = "2: Single oscillator mode, using OSC2"] + TrngEntCtlSingleOsc2 = 2, + #[doc = "3: Unused, (bit field cannot be written to this value)"] + Osc2DivDiv8 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TrngEntCtl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TrngEntCtl { + type Ux = u8; +} +impl crate::IsEnum for TrngEntCtl {} +#[doc = "Field `TRNG_ENT_CTL` reader - TRNG entropy generation control."] +pub type TrngEntCtlR = crate::FieldReader; +impl TrngEntCtlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrngEntCtl { + match self.bits { + 0 => TrngEntCtl::TrngEntCtlSingleOsc1, + 1 => TrngEntCtl::TrngEntCtlDualOscs, + 2 => TrngEntCtl::TrngEntCtlSingleOsc2, + 3 => TrngEntCtl::Osc2DivDiv8, + _ => unreachable!(), + } + } + #[doc = "Single oscillator mode, using OSC1 (default)"] + #[inline(always)] + pub fn is_trng_ent_ctl_single_osc1(&self) -> bool { + *self == TrngEntCtl::TrngEntCtlSingleOsc1 + } + #[doc = "Dual oscillator mode"] + #[inline(always)] + pub fn is_trng_ent_ctl_dual_oscs(&self) -> bool { + *self == TrngEntCtl::TrngEntCtlDualOscs + } + #[doc = "Single oscillator mode, using OSC2"] + #[inline(always)] + pub fn is_trng_ent_ctl_single_osc2(&self) -> bool { + *self == TrngEntCtl::TrngEntCtlSingleOsc2 + } + #[doc = "Unused, (bit field cannot be written to this value)"] + #[inline(always)] + pub fn is_osc2_div_div8(&self) -> bool { + *self == TrngEntCtl::Osc2DivDiv8 + } +} +#[doc = "Field `TRNG_ENT_CTL` writer - TRNG entropy generation control."] +pub type TrngEntCtlW<'a, REG> = crate::FieldWriter<'a, REG, 2, TrngEntCtl, crate::Safe>; +impl<'a, REG> TrngEntCtlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single oscillator mode, using OSC1 (default)"] + #[inline(always)] + pub fn trng_ent_ctl_single_osc1(self) -> &'a mut crate::W { + self.variant(TrngEntCtl::TrngEntCtlSingleOsc1) + } + #[doc = "Dual oscillator mode"] + #[inline(always)] + pub fn trng_ent_ctl_dual_oscs(self) -> &'a mut crate::W { + self.variant(TrngEntCtl::TrngEntCtlDualOscs) + } + #[doc = "Single oscillator mode, using OSC2"] + #[inline(always)] + pub fn trng_ent_ctl_single_osc2(self) -> &'a mut crate::W { + self.variant(TrngEntCtl::TrngEntCtlSingleOsc2) + } + #[doc = "Unused, (bit field cannot be written to this value)"] + #[inline(always)] + pub fn osc2_div_div8(self) -> &'a mut crate::W { + self.variant(TrngEntCtl::Osc2DivDiv8) + } +} +#[doc = "Oscillator 2 Divide.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Osc2Div { + #[doc = "0: Use ring oscillator 2 with no divide"] + Osc2DivDiv1 = 0, + #[doc = "1: Use ring oscillator 2 divided-by-2"] + Osc2DivDiv2 = 1, + #[doc = "2: Use ring oscillator 2 divided-by-4"] + Osc2DivDiv4 = 2, + #[doc = "3: Use ring oscillator 2 divided-by-8"] + Osc2DivDiv8 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Osc2Div) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Osc2Div { + type Ux = u8; +} +impl crate::IsEnum for Osc2Div {} +#[doc = "Field `OSC2_DIV` reader - Oscillator 2 Divide."] +pub type Osc2DivR = crate::FieldReader; +impl Osc2DivR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Osc2Div { + match self.bits { + 0 => Osc2Div::Osc2DivDiv1, + 1 => Osc2Div::Osc2DivDiv2, + 2 => Osc2Div::Osc2DivDiv4, + 3 => Osc2Div::Osc2DivDiv8, + _ => unreachable!(), + } + } + #[doc = "Use ring oscillator 2 with no divide"] + #[inline(always)] + pub fn is_osc2_div_div1(&self) -> bool { + *self == Osc2Div::Osc2DivDiv1 + } + #[doc = "Use ring oscillator 2 divided-by-2"] + #[inline(always)] + pub fn is_osc2_div_div2(&self) -> bool { + *self == Osc2Div::Osc2DivDiv2 + } + #[doc = "Use ring oscillator 2 divided-by-4"] + #[inline(always)] + pub fn is_osc2_div_div4(&self) -> bool { + *self == Osc2Div::Osc2DivDiv4 + } + #[doc = "Use ring oscillator 2 divided-by-8"] + #[inline(always)] + pub fn is_osc2_div_div8(&self) -> bool { + *self == Osc2Div::Osc2DivDiv8 + } +} +#[doc = "Field `OSC2_DIV` writer - Oscillator 2 Divide."] +pub type Osc2DivW<'a, REG> = crate::FieldWriter<'a, REG, 2, Osc2Div, crate::Safe>; +impl<'a, REG> Osc2DivW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Use ring oscillator 2 with no divide"] + #[inline(always)] + pub fn osc2_div_div1(self) -> &'a mut crate::W { + self.variant(Osc2Div::Osc2DivDiv1) + } + #[doc = "Use ring oscillator 2 divided-by-2"] + #[inline(always)] + pub fn osc2_div_div2(self) -> &'a mut crate::W { + self.variant(Osc2Div::Osc2DivDiv2) + } + #[doc = "Use ring oscillator 2 divided-by-4"] + #[inline(always)] + pub fn osc2_div_div4(self) -> &'a mut crate::W { + self.variant(Osc2Div::Osc2DivDiv4) + } + #[doc = "Use ring oscillator 2 divided-by-8"] + #[inline(always)] + pub fn osc2_div_div8(self) -> &'a mut crate::W { + self.variant(Osc2Div::Osc2DivDiv8) + } +} +#[doc = "Oscillator 2 Clock Output Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Osc2OutEn { + #[doc = "0: Ring oscillator 2 output is gated to an output pad."] + Osc2OutEn0 = 0, + #[doc = "1: Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."] + Osc2OutEn1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Osc2OutEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSC2_OUT_EN` reader - Oscillator 2 Clock Output Enable"] +pub type Osc2OutEnR = crate::BitReader; +impl Osc2OutEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Osc2OutEn { + match self.bits { + false => Osc2OutEn::Osc2OutEn0, + true => Osc2OutEn::Osc2OutEn1, + } + } + #[doc = "Ring oscillator 2 output is gated to an output pad."] + #[inline(always)] + pub fn is_osc2_out_en_0(&self) -> bool { + *self == Osc2OutEn::Osc2OutEn0 + } + #[doc = "Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."] + #[inline(always)] + pub fn is_osc2_out_en_1(&self) -> bool { + *self == Osc2OutEn::Osc2OutEn1 + } +} +#[doc = "Field `OSC2_OUT_EN` writer - Oscillator 2 Clock Output Enable"] +pub type Osc2OutEnW<'a, REG> = crate::BitWriter<'a, REG, Osc2OutEn>; +impl<'a, REG> Osc2OutEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Ring oscillator 2 output is gated to an output pad."] + #[inline(always)] + pub fn osc2_out_en_0(self) -> &'a mut crate::W { + self.variant(Osc2OutEn::Osc2OutEn0) + } + #[doc = "Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."] + #[inline(always)] + pub fn osc2_out_en_1(self) -> &'a mut crate::W { + self.variant(Osc2OutEn::Osc2OutEn1) + } +} +#[doc = "TRNG Oscillator 2 Frequency Count Valid\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Osc2FctVal { + #[doc = "0: Frequency count is invalid."] + Disable = 0, + #[doc = "1: If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Osc2FctVal) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSC2_FCT_VAL` reader - TRNG Oscillator 2 Frequency Count Valid"] +pub type Osc2FctValR = crate::BitReader; +impl Osc2FctValR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Osc2FctVal { + match self.bits { + false => Osc2FctVal::Disable, + true => Osc2FctVal::Enable, + } + } + #[doc = "Frequency count is invalid."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Osc2FctVal::Disable + } + #[doc = "If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Osc2FctVal::Enable + } +} +#[doc = "Oscillator fail safe limit.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OscFailsafeLmt { + #[doc = "0: The limit N is 4096 (2^12) system clocks."] + OscFailsafeLmt4k = 0, + #[doc = "1: The limit N is 65536 (2^16) system clocks. (default)"] + OscFailsafeLmt64k = 1, + #[doc = "2: N is 2^20 system clocks."] + OscFailsafeLmt1m = 2, + #[doc = "3: N is 2^22 system clocks (full range of the counter being used)."] + OscFailsafeLmt4m = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OscFailsafeLmt) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OscFailsafeLmt { + type Ux = u8; +} +impl crate::IsEnum for OscFailsafeLmt {} +#[doc = "Field `OSC_FAILSAFE_LMT` reader - Oscillator fail safe limit."] +pub type OscFailsafeLmtR = crate::FieldReader; +impl OscFailsafeLmtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OscFailsafeLmt { + match self.bits { + 0 => OscFailsafeLmt::OscFailsafeLmt4k, + 1 => OscFailsafeLmt::OscFailsafeLmt64k, + 2 => OscFailsafeLmt::OscFailsafeLmt1m, + 3 => OscFailsafeLmt::OscFailsafeLmt4m, + _ => unreachable!(), + } + } + #[doc = "The limit N is 4096 (2^12) system clocks."] + #[inline(always)] + pub fn is_osc_failsafe_lmt_4k(&self) -> bool { + *self == OscFailsafeLmt::OscFailsafeLmt4k + } + #[doc = "The limit N is 65536 (2^16) system clocks. (default)"] + #[inline(always)] + pub fn is_osc_failsafe_lmt_64k(&self) -> bool { + *self == OscFailsafeLmt::OscFailsafeLmt64k + } + #[doc = "N is 2^20 system clocks."] + #[inline(always)] + pub fn is_osc_failsafe_lmt_1m(&self) -> bool { + *self == OscFailsafeLmt::OscFailsafeLmt1m + } + #[doc = "N is 2^22 system clocks (full range of the counter being used)."] + #[inline(always)] + pub fn is_osc_failsafe_lmt_4m(&self) -> bool { + *self == OscFailsafeLmt::OscFailsafeLmt4m + } +} +#[doc = "Field `OSC_FAILSAFE_LMT` writer - Oscillator fail safe limit."] +pub type OscFailsafeLmtW<'a, REG> = crate::FieldWriter<'a, REG, 2, OscFailsafeLmt, crate::Safe>; +impl<'a, REG> OscFailsafeLmtW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "The limit N is 4096 (2^12) system clocks."] + #[inline(always)] + pub fn osc_failsafe_lmt_4k(self) -> &'a mut crate::W { + self.variant(OscFailsafeLmt::OscFailsafeLmt4k) + } + #[doc = "The limit N is 65536 (2^16) system clocks. (default)"] + #[inline(always)] + pub fn osc_failsafe_lmt_64k(self) -> &'a mut crate::W { + self.variant(OscFailsafeLmt::OscFailsafeLmt64k) + } + #[doc = "N is 2^20 system clocks."] + #[inline(always)] + pub fn osc_failsafe_lmt_1m(self) -> &'a mut crate::W { + self.variant(OscFailsafeLmt::OscFailsafeLmt1m) + } + #[doc = "N is 2^22 system clocks (full range of the counter being used)."] + #[inline(always)] + pub fn osc_failsafe_lmt_4m(self) -> &'a mut crate::W { + self.variant(OscFailsafeLmt::OscFailsafeLmt4m) + } +} +#[doc = "Oscillator fail safe test.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OscFailsafeTest { + #[doc = "0: No impact."] + Disable = 0, + #[doc = "1: Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OscFailsafeTest) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSC_FAILSAFE_TEST` reader - Oscillator fail safe test."] +pub type OscFailsafeTestR = crate::BitReader; +impl OscFailsafeTestR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OscFailsafeTest { + match self.bits { + false => OscFailsafeTest::Disable, + true => OscFailsafeTest::Enable, + } + } + #[doc = "No impact."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OscFailsafeTest::Disable + } + #[doc = "Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OscFailsafeTest::Enable + } +} +#[doc = "Field `OSC_FAILSAFE_TEST` writer - Oscillator fail safe test."] +pub type OscFailsafeTestW<'a, REG> = crate::BitWriter<'a, REG, OscFailsafeTest>; +impl<'a, REG> OscFailsafeTestW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No impact."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OscFailsafeTest::Disable) + } + #[doc = "Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OscFailsafeTest::Enable) + } +} +impl R { + #[doc = "Bits 0:1 - TRNG entropy generation control."] + #[inline(always)] + pub fn trng_ent_ctl(&self) -> TrngEntCtlR { + TrngEntCtlR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Oscillator 2 Divide."] + #[inline(always)] + pub fn osc2_div(&self) -> Osc2DivR { + Osc2DivR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Oscillator 2 Clock Output Enable"] + #[inline(always)] + pub fn osc2_out_en(&self) -> Osc2OutEnR { + Osc2OutEnR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 9 - TRNG Oscillator 2 Frequency Count Valid"] + #[inline(always)] + pub fn osc2_fct_val(&self) -> Osc2FctValR { + Osc2FctValR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 12:13 - Oscillator fail safe limit."] + #[inline(always)] + pub fn osc_failsafe_lmt(&self) -> OscFailsafeLmtR { + OscFailsafeLmtR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - Oscillator fail safe test."] + #[inline(always)] + pub fn osc_failsafe_test(&self) -> OscFailsafeTestR { + OscFailsafeTestR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - TRNG entropy generation control."] + #[inline(always)] + pub fn trng_ent_ctl(&mut self) -> TrngEntCtlW { + TrngEntCtlW::new(self, 0) + } + #[doc = "Bits 2:3 - Oscillator 2 Divide."] + #[inline(always)] + pub fn osc2_div(&mut self) -> Osc2DivW { + Osc2DivW::new(self, 2) + } + #[doc = "Bit 4 - Oscillator 2 Clock Output Enable"] + #[inline(always)] + pub fn osc2_out_en(&mut self) -> Osc2OutEnW { + Osc2OutEnW::new(self, 4) + } + #[doc = "Bits 12:13 - Oscillator fail safe limit."] + #[inline(always)] + pub fn osc_failsafe_lmt(&mut self) -> OscFailsafeLmtW { + OscFailsafeLmtW::new(self, 12) + } + #[doc = "Bit 14 - Oscillator fail safe test."] + #[inline(always)] + pub fn osc_failsafe_test(&mut self) -> OscFailsafeTestW { + OscFailsafeTestW::new(self, 14) + } +} +#[doc = "TRNG Oscillator 2 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc2_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Osc2CtlSpec; +impl crate::RegisterSpec for Osc2CtlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`osc2_ctl::R`](R) reader structure"] +impl crate::Readable for Osc2CtlSpec {} +#[doc = "`write(|w| ..)` method takes [`osc2_ctl::W`](W) writer structure"] +impl crate::Writable for Osc2CtlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets OSC2_CTL to value 0x1000"] +impl crate::Resettable for Osc2CtlSpec { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs b/mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs new file mode 100644 index 000000000..85f658787 --- /dev/null +++ b/mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs @@ -0,0 +1,20 @@ +#[doc = "Register `OSC2_FRQCNT` reader"] +pub type R = crate::R; +#[doc = "Field `OSC2_FRQ_CT` reader - Frequency Count"] +pub type Osc2FrqCtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - Frequency Count"] + #[inline(always)] + pub fn osc2_frq_ct(&self) -> Osc2FrqCtR { + Osc2FrqCtR::new(self.bits & 0x003f_ffff) + } +} +#[doc = "Oscillator-2 Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_frqcnt_osc2_frqcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Osc2FrqcntOsc2FrqcntSpec; +impl crate::RegisterSpec for Osc2FrqcntOsc2FrqcntSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`osc2_frqcnt_osc2_frqcnt::R`](R) reader structure"] +impl crate::Readable for Osc2FrqcntOsc2FrqcntSpec {} +#[doc = "`reset()` method sets OSC2_FRQCNT to value 0"] +impl crate::Resettable for Osc2FrqcntOsc2FrqcntSpec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt10.rs b/mcxa276-pac/src/trng0/pkrcnt10.rs new file mode 100644 index 000000000..18763c4af --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcnt10.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNT10` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_0_CT` reader - Poker 0h Count"] +pub type Pkr0CtR = crate::FieldReader; +#[doc = "Field `PKR_1_CT` reader - Poker 1h Count"] +pub type Pkr1CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker 0h Count"] + #[inline(always)] + pub fn pkr_0_ct(&self) -> Pkr0CtR { + Pkr0CtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker 1h Count"] + #[inline(always)] + pub fn pkr_1_ct(&self) -> Pkr1CtR { + Pkr1CtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count 1 and 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pkrcnt10Spec; +impl crate::RegisterSpec for Pkrcnt10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcnt10::R`](R) reader structure"] +impl crate::Readable for Pkrcnt10Spec {} +#[doc = "`reset()` method sets PKRCNT10 to value 0"] +impl crate::Resettable for Pkrcnt10Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt32.rs b/mcxa276-pac/src/trng0/pkrcnt32.rs new file mode 100644 index 000000000..ae25c35d6 --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcnt32.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNT32` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_2_CT` reader - Poker 2h Count"] +pub type Pkr2CtR = crate::FieldReader; +#[doc = "Field `PKR_3_CT` reader - Poker 3h Count"] +pub type Pkr3CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker 2h Count"] + #[inline(always)] + pub fn pkr_2_ct(&self) -> Pkr2CtR { + Pkr2CtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker 3h Count"] + #[inline(always)] + pub fn pkr_3_ct(&self) -> Pkr3CtR { + Pkr3CtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count 3 and 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt32::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pkrcnt32Spec; +impl crate::RegisterSpec for Pkrcnt32Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcnt32::R`](R) reader structure"] +impl crate::Readable for Pkrcnt32Spec {} +#[doc = "`reset()` method sets PKRCNT32 to value 0"] +impl crate::Resettable for Pkrcnt32Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt54.rs b/mcxa276-pac/src/trng0/pkrcnt54.rs new file mode 100644 index 000000000..e003d3274 --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcnt54.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNT54` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_4_CT` reader - Poker 4h Count"] +pub type Pkr4CtR = crate::FieldReader; +#[doc = "Field `PKR_5_CT` reader - Poker 5h Count"] +pub type Pkr5CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker 4h Count"] + #[inline(always)] + pub fn pkr_4_ct(&self) -> Pkr4CtR { + Pkr4CtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker 5h Count"] + #[inline(always)] + pub fn pkr_5_ct(&self) -> Pkr5CtR { + Pkr5CtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count 5 and 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt54::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pkrcnt54Spec; +impl crate::RegisterSpec for Pkrcnt54Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcnt54::R`](R) reader structure"] +impl crate::Readable for Pkrcnt54Spec {} +#[doc = "`reset()` method sets PKRCNT54 to value 0"] +impl crate::Resettable for Pkrcnt54Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt76.rs b/mcxa276-pac/src/trng0/pkrcnt76.rs new file mode 100644 index 000000000..f7cf64de9 --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcnt76.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNT76` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_6_CT` reader - Poker 6h Count"] +pub type Pkr6CtR = crate::FieldReader; +#[doc = "Field `PKR_7_CT` reader - Poker 7h Count"] +pub type Pkr7CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker 6h Count"] + #[inline(always)] + pub fn pkr_6_ct(&self) -> Pkr6CtR { + Pkr6CtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker 7h Count"] + #[inline(always)] + pub fn pkr_7_ct(&self) -> Pkr7CtR { + Pkr7CtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count 7 and 6 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt76::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pkrcnt76Spec; +impl crate::RegisterSpec for Pkrcnt76Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcnt76::R`](R) reader structure"] +impl crate::Readable for Pkrcnt76Spec {} +#[doc = "`reset()` method sets PKRCNT76 to value 0"] +impl crate::Resettable for Pkrcnt76Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt98.rs b/mcxa276-pac/src/trng0/pkrcnt98.rs new file mode 100644 index 000000000..3ad7a337f --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcnt98.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNT98` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_8_CT` reader - Poker 8h Count"] +pub type Pkr8CtR = crate::FieldReader; +#[doc = "Field `PKR_9_CT` reader - Poker 9h Count"] +pub type Pkr9CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker 8h Count"] + #[inline(always)] + pub fn pkr_8_ct(&self) -> Pkr8CtR { + Pkr8CtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker 9h Count"] + #[inline(always)] + pub fn pkr_9_ct(&self) -> Pkr9CtR { + Pkr9CtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count 9 and 8 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt98::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pkrcnt98Spec; +impl crate::RegisterSpec for Pkrcnt98Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcnt98::R`](R) reader structure"] +impl crate::Readable for Pkrcnt98Spec {} +#[doc = "`reset()` method sets PKRCNT98 to value 0"] +impl crate::Resettable for Pkrcnt98Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcntba.rs b/mcxa276-pac/src/trng0/pkrcntba.rs new file mode 100644 index 000000000..98e48b194 --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcntba.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNTBA` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_A_CT` reader - Poker Ah Count"] +pub type PkrACtR = crate::FieldReader; +#[doc = "Field `PKR_B_CT` reader - Poker Bh Count"] +pub type PkrBCtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker Ah Count"] + #[inline(always)] + pub fn pkr_a_ct(&self) -> PkrACtR { + PkrACtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker Bh Count"] + #[inline(always)] + pub fn pkr_b_ct(&self) -> PkrBCtR { + PkrBCtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count B and A Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntba::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkrcntbaSpec; +impl crate::RegisterSpec for PkrcntbaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcntba::R`](R) reader structure"] +impl crate::Readable for PkrcntbaSpec {} +#[doc = "`reset()` method sets PKRCNTBA to value 0"] +impl crate::Resettable for PkrcntbaSpec {} diff --git a/mcxa276-pac/src/trng0/pkrcntdc.rs b/mcxa276-pac/src/trng0/pkrcntdc.rs new file mode 100644 index 000000000..12ed0115f --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcntdc.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNTDC` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_C_CT` reader - Poker Ch Count"] +pub type PkrCCtR = crate::FieldReader; +#[doc = "Field `PKR_D_CT` reader - Poker Dh Count"] +pub type PkrDCtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker Ch Count"] + #[inline(always)] + pub fn pkr_c_ct(&self) -> PkrCCtR { + PkrCCtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker Dh Count"] + #[inline(always)] + pub fn pkr_d_ct(&self) -> PkrDCtR { + PkrDCtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count D and C Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntdc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkrcntdcSpec; +impl crate::RegisterSpec for PkrcntdcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcntdc::R`](R) reader structure"] +impl crate::Readable for PkrcntdcSpec {} +#[doc = "`reset()` method sets PKRCNTDC to value 0"] +impl crate::Resettable for PkrcntdcSpec {} diff --git a/mcxa276-pac/src/trng0/pkrcntfe.rs b/mcxa276-pac/src/trng0/pkrcntfe.rs new file mode 100644 index 000000000..3df6de3d3 --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrcntfe.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PKRCNTFE` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_E_CT` reader - Poker Eh Count"] +pub type PkrECtR = crate::FieldReader; +#[doc = "Field `PKR_F_CT` reader - Poker Fh Count"] +pub type PkrFCtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Poker Eh Count"] + #[inline(always)] + pub fn pkr_e_ct(&self) -> PkrECtR { + PkrECtR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Poker Fh Count"] + #[inline(always)] + pub fn pkr_f_ct(&self) -> PkrFCtR { + PkrFCtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Statistical Check Poker Count F and E Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntfe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkrcntfeSpec; +impl crate::RegisterSpec for PkrcntfeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrcntfe::R`](R) reader structure"] +impl crate::Readable for PkrcntfeSpec {} +#[doc = "`reset()` method sets PKRCNTFE to value 0"] +impl crate::Resettable for PkrcntfeSpec {} diff --git a/mcxa276-pac/src/trng0/pkrmax_pkrmax.rs b/mcxa276-pac/src/trng0/pkrmax_pkrmax.rs new file mode 100644 index 000000000..dab952475 --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrmax_pkrmax.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PKRMAX` reader"] +pub type R = crate::R; +#[doc = "Register `PKRMAX` writer"] +pub type W = crate::W; +#[doc = "Field `PKR_MAX` reader - Poker Maximum Limit."] +pub type PkrMaxR = crate::FieldReader; +#[doc = "Field `PKR_MAX` writer - Poker Maximum Limit."] +pub type PkrMaxW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Poker Maximum Limit."] + #[inline(always)] + pub fn pkr_max(&self) -> PkrMaxR { + PkrMaxR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Poker Maximum Limit."] + #[inline(always)] + pub fn pkr_max(&mut self) -> PkrMaxW { + PkrMaxW::new(self, 0) + } +} +#[doc = "Poker Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrmax_pkrmax::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrmax_pkrmax::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkrmaxPkrmaxSpec; +impl crate::RegisterSpec for PkrmaxPkrmaxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrmax_pkrmax::R`](R) reader structure"] +impl crate::Readable for PkrmaxPkrmaxSpec {} +#[doc = "`write(|w| ..)` method takes [`pkrmax_pkrmax::W`](W) writer structure"] +impl crate::Writable for PkrmaxPkrmaxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKRMAX to value 0x0640"] +impl crate::Resettable for PkrmaxPkrmaxSpec { + const RESET_VALUE: u32 = 0x0640; +} diff --git a/mcxa276-pac/src/trng0/pkrrng.rs b/mcxa276-pac/src/trng0/pkrrng.rs new file mode 100644 index 000000000..2adcc4642 --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrrng.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PKRRNG` reader"] +pub type R = crate::R; +#[doc = "Register `PKRRNG` writer"] +pub type W = crate::W; +#[doc = "Field `PKR_RNG` reader - Poker Range"] +pub type PkrRngR = crate::FieldReader; +#[doc = "Field `PKR_RNG` writer - Poker Range"] +pub type PkrRngW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Poker Range"] + #[inline(always)] + pub fn pkr_rng(&self) -> PkrRngR { + PkrRngR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Poker Range"] + #[inline(always)] + pub fn pkr_rng(&mut self) -> PkrRngW { + PkrRngW::new(self, 0) + } +} +#[doc = "Poker Range Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrrng::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrrng::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkrrngSpec; +impl crate::RegisterSpec for PkrrngSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrrng::R`](R) reader structure"] +impl crate::Readable for PkrrngSpec {} +#[doc = "`write(|w| ..)` method takes [`pkrrng::W`](W) writer structure"] +impl crate::Writable for PkrrngSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PKRRNG to value 0x023a"] +impl crate::Resettable for PkrrngSpec { + const RESET_VALUE: u32 = 0x023a; +} diff --git a/mcxa276-pac/src/trng0/pkrsq_pkrsq.rs b/mcxa276-pac/src/trng0/pkrsq_pkrsq.rs new file mode 100644 index 000000000..fecd7415d --- /dev/null +++ b/mcxa276-pac/src/trng0/pkrsq_pkrsq.rs @@ -0,0 +1,20 @@ +#[doc = "Register `PKRSQ` reader"] +pub type R = crate::R; +#[doc = "Field `PKR_SQ` reader - Poker Square Calculation Result."] +pub type PkrSqR = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - Poker Square Calculation Result."] + #[inline(always)] + pub fn pkr_sq(&self) -> PkrSqR { + PkrSqR::new(self.bits & 0x00ff_ffff) + } +} +#[doc = "Poker Square Calculation Result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrsq_pkrsq::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PkrsqPkrsqSpec; +impl crate::RegisterSpec for PkrsqPkrsqSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkrsq_pkrsq::R`](R) reader structure"] +impl crate::Readable for PkrsqPkrsqSpec {} +#[doc = "`reset()` method sets PKRSQ to value 0"] +impl crate::Resettable for PkrsqPkrsqSpec {} diff --git a/mcxa276-pac/src/trng0/sblim_sblim.rs b/mcxa276-pac/src/trng0/sblim_sblim.rs new file mode 100644 index 000000000..c6b627a96 --- /dev/null +++ b/mcxa276-pac/src/trng0/sblim_sblim.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SBLIM` reader"] +pub type R = crate::R; +#[doc = "Register `SBLIM` writer"] +pub type W = crate::W; +#[doc = "Field `SB_LIM` reader - Sparse Bit Limit"] +pub type SbLimR = crate::FieldReader; +#[doc = "Field `SB_LIM` writer - Sparse Bit Limit"] +pub type SbLimW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Sparse Bit Limit"] + #[inline(always)] + pub fn sb_lim(&self) -> SbLimR { + SbLimR::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Sparse Bit Limit"] + #[inline(always)] + pub fn sb_lim(&mut self) -> SbLimW { + SbLimW::new(self, 0) + } +} +#[doc = "Sparse Bit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sblim_sblim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sblim_sblim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SblimSblimSpec; +impl crate::RegisterSpec for SblimSblimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sblim_sblim::R`](R) reader structure"] +impl crate::Readable for SblimSblimSpec {} +#[doc = "`write(|w| ..)` method takes [`sblim_sblim::W`](W) writer structure"] +impl crate::Writable for SblimSblimSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SBLIM to value 0x3f"] +impl crate::Resettable for SblimSblimSpec { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/mcxa276-pac/src/trng0/scmc_scmc.rs b/mcxa276-pac/src/trng0/scmc_scmc.rs new file mode 100644 index 000000000..2ad6beac5 --- /dev/null +++ b/mcxa276-pac/src/trng0/scmc_scmc.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SCMC` reader"] +pub type R = crate::R; +#[doc = "Field `MONO_CT` reader - Monobit Count"] +pub type MonoCtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Monobit Count"] + #[inline(always)] + pub fn mono_ct(&self) -> MonoCtR { + MonoCtR::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Statistical Check Monobit Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmc_scmc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScmcScmcSpec; +impl crate::RegisterSpec for ScmcScmcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scmc_scmc::R`](R) reader structure"] +impl crate::Readable for ScmcScmcSpec {} +#[doc = "`reset()` method sets SCMC to value 0"] +impl crate::Resettable for ScmcScmcSpec {} diff --git a/mcxa276-pac/src/trng0/scmisc.rs b/mcxa276-pac/src/trng0/scmisc.rs new file mode 100644 index 000000000..c5b58b375 --- /dev/null +++ b/mcxa276-pac/src/trng0/scmisc.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCMISC` reader"] +pub type R = crate::R; +#[doc = "Register `SCMISC` writer"] +pub type W = crate::W; +#[doc = "Field `LRUN_MAX` reader - Long run max limit"] +pub type LrunMaxR = crate::FieldReader; +#[doc = "Field `LRUN_MAX` writer - Long run max limit"] +pub type LrunMaxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RTY_CT` reader - Retry count"] +pub type RtyCtR = crate::FieldReader; +#[doc = "Field `RTY_CT` writer - Retry count"] +pub type RtyCtW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:7 - Long run max limit"] + #[inline(always)] + pub fn lrun_max(&self) -> LrunMaxR { + LrunMaxR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:19 - Retry count"] + #[inline(always)] + pub fn rty_ct(&self) -> RtyCtR { + RtyCtR::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Long run max limit"] + #[inline(always)] + pub fn lrun_max(&mut self) -> LrunMaxW { + LrunMaxW::new(self, 0) + } + #[doc = "Bits 16:19 - Retry count"] + #[inline(always)] + pub fn rty_ct(&mut self) -> RtyCtW { + RtyCtW::new(self, 16) + } +} +#[doc = "Statistical Check Miscellaneous Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmisc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scmisc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScmiscSpec; +impl crate::RegisterSpec for ScmiscSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scmisc::R`](R) reader structure"] +impl crate::Readable for ScmiscSpec {} +#[doc = "`write(|w| ..)` method takes [`scmisc::W`](W) writer structure"] +impl crate::Writable for ScmiscSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCMISC to value 0x0001_001f"] +impl crate::Resettable for ScmiscSpec { + const RESET_VALUE: u32 = 0x0001_001f; +} diff --git a/mcxa276-pac/src/trng0/scml_scml.rs b/mcxa276-pac/src/trng0/scml_scml.rs new file mode 100644 index 000000000..650be71e3 --- /dev/null +++ b/mcxa276-pac/src/trng0/scml_scml.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCML` reader"] +pub type R = crate::R; +#[doc = "Register `SCML` writer"] +pub type W = crate::W; +#[doc = "Field `MONO_MAX` reader - Monobit Maximum Limit"] +pub type MonoMaxR = crate::FieldReader; +#[doc = "Field `MONO_MAX` writer - Monobit Maximum Limit"] +pub type MonoMaxW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `MONO_RNG` reader - Monobit Range"] +pub type MonoRngR = crate::FieldReader; +#[doc = "Field `MONO_RNG` writer - Monobit Range"] +pub type MonoRngW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Monobit Maximum Limit"] + #[inline(always)] + pub fn mono_max(&self) -> MonoMaxR { + MonoMaxR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Monobit Range"] + #[inline(always)] + pub fn mono_rng(&self) -> MonoRngR { + MonoRngR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Monobit Maximum Limit"] + #[inline(always)] + pub fn mono_max(&mut self) -> MonoMaxW { + MonoMaxW::new(self, 0) + } + #[doc = "Bits 16:31 - Monobit Range"] + #[inline(always)] + pub fn mono_rng(&mut self) -> MonoRngW { + MonoRngW::new(self, 16) + } +} +#[doc = "Statistical Check Monobit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scml_scml::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scml_scml::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScmlScmlSpec; +impl crate::RegisterSpec for ScmlScmlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scml_scml::R`](R) reader structure"] +impl crate::Readable for ScmlScmlSpec {} +#[doc = "`write(|w| ..)` method takes [`scml_scml::W`](W) writer structure"] +impl crate::Writable for ScmlScmlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCML to value 0x0078_013c"] +impl crate::Resettable for ScmlScmlSpec { + const RESET_VALUE: u32 = 0x0078_013c; +} diff --git a/mcxa276-pac/src/trng0/scr1c_scr1c.rs b/mcxa276-pac/src/trng0/scr1c_scr1c.rs new file mode 100644 index 000000000..0ac4f1ee1 --- /dev/null +++ b/mcxa276-pac/src/trng0/scr1c_scr1c.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SCR1C` reader"] +pub type R = crate::R; +#[doc = "Field `R1_0_CT` reader - Runs of Zero, Length 1 Count"] +pub type R1_0CtR = crate::FieldReader; +#[doc = "Field `R1_1_CT` reader - Runs of One, Length 1 Count"] +pub type R1_1CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - Runs of Zero, Length 1 Count"] + #[inline(always)] + pub fn r1_0_ct(&self) -> R1_0CtR { + R1_0CtR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bits 16:30 - Runs of One, Length 1 Count"] + #[inline(always)] + pub fn r1_1_ct(&self) -> R1_1CtR { + R1_1CtR::new(((self.bits >> 16) & 0x7fff) as u16) + } +} +#[doc = "Statistical Check Run Length 1 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1c_scr1c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr1cScr1cSpec; +impl crate::RegisterSpec for Scr1cScr1cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr1c_scr1c::R`](R) reader structure"] +impl crate::Readable for Scr1cScr1cSpec {} +#[doc = "`reset()` method sets SCR1C to value 0"] +impl crate::Resettable for Scr1cScr1cSpec {} diff --git a/mcxa276-pac/src/trng0/scr1l_scr1l.rs b/mcxa276-pac/src/trng0/scr1l_scr1l.rs new file mode 100644 index 000000000..25136b7cb --- /dev/null +++ b/mcxa276-pac/src/trng0/scr1l_scr1l.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCR1L` reader"] +pub type R = crate::R; +#[doc = "Register `SCR1L` writer"] +pub type W = crate::W; +#[doc = "Field `RUN1_MAX` reader - Run Length 1 Maximum Limit"] +pub type Run1MaxR = crate::FieldReader; +#[doc = "Field `RUN1_MAX` writer - Run Length 1 Maximum Limit"] +pub type Run1MaxW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `RUN1_RNG` reader - Run Length 1 Range"] +pub type Run1RngR = crate::FieldReader; +#[doc = "Field `RUN1_RNG` writer - Run Length 1 Range"] +pub type Run1RngW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - Run Length 1 Maximum Limit"] + #[inline(always)] + pub fn run1_max(&self) -> Run1MaxR { + Run1MaxR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bits 16:30 - Run Length 1 Range"] + #[inline(always)] + pub fn run1_rng(&self) -> Run1RngR { + Run1RngR::new(((self.bits >> 16) & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bits 0:14 - Run Length 1 Maximum Limit"] + #[inline(always)] + pub fn run1_max(&mut self) -> Run1MaxW { + Run1MaxW::new(self, 0) + } + #[doc = "Bits 16:30 - Run Length 1 Range"] + #[inline(always)] + pub fn run1_rng(&mut self) -> Run1RngW { + Run1RngW::new(self, 16) + } +} +#[doc = "Statistical Check Run Length 1 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1l_scr1l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr1l_scr1l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr1lScr1lSpec; +impl crate::RegisterSpec for Scr1lScr1lSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr1l_scr1l::R`](R) reader structure"] +impl crate::Readable for Scr1lScr1lSpec {} +#[doc = "`write(|w| ..)` method takes [`scr1l_scr1l::W`](W) writer structure"] +impl crate::Writable for Scr1lScr1lSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCR1L to value 0x004f_006b"] +impl crate::Resettable for Scr1lScr1lSpec { + const RESET_VALUE: u32 = 0x004f_006b; +} diff --git a/mcxa276-pac/src/trng0/scr2c_scr2c.rs b/mcxa276-pac/src/trng0/scr2c_scr2c.rs new file mode 100644 index 000000000..8d46cd989 --- /dev/null +++ b/mcxa276-pac/src/trng0/scr2c_scr2c.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SCR2C` reader"] +pub type R = crate::R; +#[doc = "Field `R2_0_CT` reader - Runs of Zero, Length 2 Count"] +pub type R2_0CtR = crate::FieldReader; +#[doc = "Field `R2_1_CT` reader - Runs of One, Length 2 Count"] +pub type R2_1CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - Runs of Zero, Length 2 Count"] + #[inline(always)] + pub fn r2_0_ct(&self) -> R2_0CtR { + R2_0CtR::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - Runs of One, Length 2 Count"] + #[inline(always)] + pub fn r2_1_ct(&self) -> R2_1CtR { + R2_1CtR::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[doc = "Statistical Check Run Length 2 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2c_scr2c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr2cScr2cSpec; +impl crate::RegisterSpec for Scr2cScr2cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr2c_scr2c::R`](R) reader structure"] +impl crate::Readable for Scr2cScr2cSpec {} +#[doc = "`reset()` method sets SCR2C to value 0"] +impl crate::Resettable for Scr2cScr2cSpec {} diff --git a/mcxa276-pac/src/trng0/scr2l_scr2l.rs b/mcxa276-pac/src/trng0/scr2l_scr2l.rs new file mode 100644 index 000000000..74e9cf12f --- /dev/null +++ b/mcxa276-pac/src/trng0/scr2l_scr2l.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCR2L` reader"] +pub type R = crate::R; +#[doc = "Register `SCR2L` writer"] +pub type W = crate::W; +#[doc = "Field `RUN2_MAX` reader - Run Length 2 Maximum Limit"] +pub type Run2MaxR = crate::FieldReader; +#[doc = "Field `RUN2_MAX` writer - Run Length 2 Maximum Limit"] +pub type Run2MaxW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `RUN2_RNG` reader - Run Length 2 Range"] +pub type Run2RngR = crate::FieldReader; +#[doc = "Field `RUN2_RNG` writer - Run Length 2 Range"] +pub type Run2RngW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Run Length 2 Maximum Limit"] + #[inline(always)] + pub fn run2_max(&self) -> Run2MaxR { + Run2MaxR::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - Run Length 2 Range"] + #[inline(always)] + pub fn run2_rng(&self) -> Run2RngR { + Run2RngR::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bits 0:13 - Run Length 2 Maximum Limit"] + #[inline(always)] + pub fn run2_max(&mut self) -> Run2MaxW { + Run2MaxW::new(self, 0) + } + #[doc = "Bits 16:29 - Run Length 2 Range"] + #[inline(always)] + pub fn run2_rng(&mut self) -> Run2RngW { + Run2RngW::new(self, 16) + } +} +#[doc = "Statistical Check Run Length 2 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2l_scr2l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr2l_scr2l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr2lScr2lSpec; +impl crate::RegisterSpec for Scr2lScr2lSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr2l_scr2l::R`](R) reader structure"] +impl crate::Readable for Scr2lScr2lSpec {} +#[doc = "`write(|w| ..)` method takes [`scr2l_scr2l::W`](W) writer structure"] +impl crate::Writable for Scr2lScr2lSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCR2L to value 0x0036_003e"] +impl crate::Resettable for Scr2lScr2lSpec { + const RESET_VALUE: u32 = 0x0036_003e; +} diff --git a/mcxa276-pac/src/trng0/scr3c_scr3c.rs b/mcxa276-pac/src/trng0/scr3c_scr3c.rs new file mode 100644 index 000000000..a46b5f78f --- /dev/null +++ b/mcxa276-pac/src/trng0/scr3c_scr3c.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SCR3C` reader"] +pub type R = crate::R; +#[doc = "Field `R3_0_CT` reader - Runs of Zeroes, Length 3 Count"] +pub type R3_0CtR = crate::FieldReader; +#[doc = "Field `R3_1_CT` reader - Runs of Ones, Length 3 Count"] +pub type R3_1CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - Runs of Zeroes, Length 3 Count"] + #[inline(always)] + pub fn r3_0_ct(&self) -> R3_0CtR { + R3_0CtR::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 16:28 - Runs of Ones, Length 3 Count"] + #[inline(always)] + pub fn r3_1_ct(&self) -> R3_1CtR { + R3_1CtR::new(((self.bits >> 16) & 0x1fff) as u16) + } +} +#[doc = "Statistical Check Run Length 3 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3c_scr3c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr3cScr3cSpec; +impl crate::RegisterSpec for Scr3cScr3cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr3c_scr3c::R`](R) reader structure"] +impl crate::Readable for Scr3cScr3cSpec {} +#[doc = "`reset()` method sets SCR3C to value 0"] +impl crate::Resettable for Scr3cScr3cSpec {} diff --git a/mcxa276-pac/src/trng0/scr3l_scr3l.rs b/mcxa276-pac/src/trng0/scr3l_scr3l.rs new file mode 100644 index 000000000..53c900b2b --- /dev/null +++ b/mcxa276-pac/src/trng0/scr3l_scr3l.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCR3L` reader"] +pub type R = crate::R; +#[doc = "Register `SCR3L` writer"] +pub type W = crate::W; +#[doc = "Field `RUN3_MAX` reader - Run Length 3 Maximum Limit"] +pub type Run3MaxR = crate::FieldReader; +#[doc = "Field `RUN3_MAX` writer - Run Length 3 Maximum Limit"] +pub type Run3MaxW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `RUN3_RNG` reader - Run Length 3 Range"] +pub type Run3RngR = crate::FieldReader; +#[doc = "Field `RUN3_RNG` writer - Run Length 3 Range"] +pub type Run3RngW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - Run Length 3 Maximum Limit"] + #[inline(always)] + pub fn run3_max(&self) -> Run3MaxR { + Run3MaxR::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 16:28 - Run Length 3 Range"] + #[inline(always)] + pub fn run3_rng(&self) -> Run3RngR { + Run3RngR::new(((self.bits >> 16) & 0x1fff) as u16) + } +} +impl W { + #[doc = "Bits 0:12 - Run Length 3 Maximum Limit"] + #[inline(always)] + pub fn run3_max(&mut self) -> Run3MaxW { + Run3MaxW::new(self, 0) + } + #[doc = "Bits 16:28 - Run Length 3 Range"] + #[inline(always)] + pub fn run3_rng(&mut self) -> Run3RngW { + Run3RngW::new(self, 16) + } +} +#[doc = "Statistical Check Run Length 3 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3l_scr3l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr3l_scr3l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr3lScr3lSpec; +impl crate::RegisterSpec for Scr3lScr3lSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr3l_scr3l::R`](R) reader structure"] +impl crate::Readable for Scr3lScr3lSpec {} +#[doc = "`write(|w| ..)` method takes [`scr3l_scr3l::W`](W) writer structure"] +impl crate::Writable for Scr3lScr3lSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCR3L to value 0x002d_0037"] +impl crate::Resettable for Scr3lScr3lSpec { + const RESET_VALUE: u32 = 0x002d_0037; +} diff --git a/mcxa276-pac/src/trng0/scr4c_scr4c.rs b/mcxa276-pac/src/trng0/scr4c_scr4c.rs new file mode 100644 index 000000000..9452806e6 --- /dev/null +++ b/mcxa276-pac/src/trng0/scr4c_scr4c.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SCR4C` reader"] +pub type R = crate::R; +#[doc = "Field `R4_0_CT` reader - Runs of Zero, Length 4 Count"] +pub type R4_0CtR = crate::FieldReader; +#[doc = "Field `R4_1_CT` reader - Runs of One, Length 4 Count"] +pub type R4_1CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Runs of Zero, Length 4 Count"] + #[inline(always)] + pub fn r4_0_ct(&self) -> R4_0CtR { + R4_0CtR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - Runs of One, Length 4 Count"] + #[inline(always)] + pub fn r4_1_ct(&self) -> R4_1CtR { + R4_1CtR::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[doc = "Statistical Check Run Length 4 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4c_scr4c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr4cScr4cSpec; +impl crate::RegisterSpec for Scr4cScr4cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr4c_scr4c::R`](R) reader structure"] +impl crate::Readable for Scr4cScr4cSpec {} +#[doc = "`reset()` method sets SCR4C to value 0"] +impl crate::Resettable for Scr4cScr4cSpec {} diff --git a/mcxa276-pac/src/trng0/scr4l_scr4l.rs b/mcxa276-pac/src/trng0/scr4l_scr4l.rs new file mode 100644 index 000000000..19992e84f --- /dev/null +++ b/mcxa276-pac/src/trng0/scr4l_scr4l.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCR4L` reader"] +pub type R = crate::R; +#[doc = "Register `SCR4L` writer"] +pub type W = crate::W; +#[doc = "Field `RUN4_MAX` reader - Run Length 4 Maximum Limit"] +pub type Run4MaxR = crate::FieldReader; +#[doc = "Field `RUN4_MAX` writer - Run Length 4 Maximum Limit"] +pub type Run4MaxW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `RUN4_RNG` reader - Run Length 4 Range"] +pub type Run4RngR = crate::FieldReader; +#[doc = "Field `RUN4_RNG` writer - Run Length 4 Range"] +pub type Run4RngW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - Run Length 4 Maximum Limit"] + #[inline(always)] + pub fn run4_max(&self) -> Run4MaxR { + Run4MaxR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - Run Length 4 Range"] + #[inline(always)] + pub fn run4_rng(&self) -> Run4RngR { + Run4RngR::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Run Length 4 Maximum Limit"] + #[inline(always)] + pub fn run4_max(&mut self) -> Run4MaxW { + Run4MaxW::new(self, 0) + } + #[doc = "Bits 16:27 - Run Length 4 Range"] + #[inline(always)] + pub fn run4_rng(&mut self) -> Run4RngW { + Run4RngW::new(self, 16) + } +} +#[doc = "Statistical Check Run Length 4 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4l_scr4l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr4l_scr4l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr4lScr4lSpec; +impl crate::RegisterSpec for Scr4lScr4lSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr4l_scr4l::R`](R) reader structure"] +impl crate::Readable for Scr4lScr4lSpec {} +#[doc = "`write(|w| ..)` method takes [`scr4l_scr4l::W`](W) writer structure"] +impl crate::Writable for Scr4lScr4lSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCR4L to value 0x001b_001a"] +impl crate::Resettable for Scr4lScr4lSpec { + const RESET_VALUE: u32 = 0x001b_001a; +} diff --git a/mcxa276-pac/src/trng0/scr5c_scr5c.rs b/mcxa276-pac/src/trng0/scr5c_scr5c.rs new file mode 100644 index 000000000..27396ccfc --- /dev/null +++ b/mcxa276-pac/src/trng0/scr5c_scr5c.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SCR5C` reader"] +pub type R = crate::R; +#[doc = "Field `R5_0_CT` reader - Runs of Zero, Length 5 Count"] +pub type R5_0CtR = crate::FieldReader; +#[doc = "Field `R5_1_CT` reader - Runs of One, Length 5 Count"] +pub type R5_1CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - Runs of Zero, Length 5 Count"] + #[inline(always)] + pub fn r5_0_ct(&self) -> R5_0CtR { + R5_0CtR::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 16:26 - Runs of One, Length 5 Count"] + #[inline(always)] + pub fn r5_1_ct(&self) -> R5_1CtR { + R5_1CtR::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +#[doc = "Statistical Check Run Length 5 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5c_scr5c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr5cScr5cSpec; +impl crate::RegisterSpec for Scr5cScr5cSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr5c_scr5c::R`](R) reader structure"] +impl crate::Readable for Scr5cScr5cSpec {} +#[doc = "`reset()` method sets SCR5C to value 0"] +impl crate::Resettable for Scr5cScr5cSpec {} diff --git a/mcxa276-pac/src/trng0/scr5l_scr5l.rs b/mcxa276-pac/src/trng0/scr5l_scr5l.rs new file mode 100644 index 000000000..11aa84108 --- /dev/null +++ b/mcxa276-pac/src/trng0/scr5l_scr5l.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCR5L` reader"] +pub type R = crate::R; +#[doc = "Register `SCR5L` writer"] +pub type W = crate::W; +#[doc = "Field `RUN5_MAX` reader - Run Length 5 Maximum Limit"] +pub type Run5MaxR = crate::FieldReader; +#[doc = "Field `RUN5_MAX` writer - Run Length 5 Maximum Limit"] +pub type Run5MaxW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `RUN5_RNG` reader - Run Length 5 Range"] +pub type Run5RngR = crate::FieldReader; +#[doc = "Field `RUN5_RNG` writer - Run Length 5 Range"] +pub type Run5RngW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Run Length 5 Maximum Limit"] + #[inline(always)] + pub fn run5_max(&self) -> Run5MaxR { + Run5MaxR::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 16:26 - Run Length 5 Range"] + #[inline(always)] + pub fn run5_rng(&self) -> Run5RngR { + Run5RngR::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:10 - Run Length 5 Maximum Limit"] + #[inline(always)] + pub fn run5_max(&mut self) -> Run5MaxW { + Run5MaxW::new(self, 0) + } + #[doc = "Bits 16:26 - Run Length 5 Range"] + #[inline(always)] + pub fn run5_rng(&mut self) -> Run5RngW { + Run5RngW::new(self, 16) + } +} +#[doc = "Statistical Check Run Length 5 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5l_scr5l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr5l_scr5l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr5lScr5lSpec; +impl crate::RegisterSpec for Scr5lScr5lSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr5l_scr5l::R`](R) reader structure"] +impl crate::Readable for Scr5lScr5lSpec {} +#[doc = "`write(|w| ..)` method takes [`scr5l_scr5l::W`](W) writer structure"] +impl crate::Writable for Scr5lScr5lSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCR5L to value 0x0013_0012"] +impl crate::Resettable for Scr5lScr5lSpec { + const RESET_VALUE: u32 = 0x0013_0012; +} diff --git a/mcxa276-pac/src/trng0/scr6pc_scr6pc.rs b/mcxa276-pac/src/trng0/scr6pc_scr6pc.rs new file mode 100644 index 000000000..4b4b3559e --- /dev/null +++ b/mcxa276-pac/src/trng0/scr6pc_scr6pc.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SCR6PC` reader"] +pub type R = crate::R; +#[doc = "Field `R6P_0_CT` reader - Runs of Zero, Length 6+ Count"] +pub type R6p0CtR = crate::FieldReader; +#[doc = "Field `R6P_1_CT` reader - Runs of One, Length 6+ Count"] +pub type R6p1CtR = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - Runs of Zero, Length 6+ Count"] + #[inline(always)] + pub fn r6p_0_ct(&self) -> R6p0CtR { + R6p0CtR::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 16:26 - Runs of One, Length 6+ Count"] + #[inline(always)] + pub fn r6p_1_ct(&self) -> R6p1CtR { + R6p1CtR::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +#[doc = "Statistical Check Run Length 6+ Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pc_scr6pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr6pcScr6pcSpec; +impl crate::RegisterSpec for Scr6pcScr6pcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr6pc_scr6pc::R`](R) reader structure"] +impl crate::Readable for Scr6pcScr6pcSpec {} +#[doc = "`reset()` method sets SCR6PC to value 0"] +impl crate::Resettable for Scr6pcScr6pcSpec {} diff --git a/mcxa276-pac/src/trng0/scr6pl_scr6pl.rs b/mcxa276-pac/src/trng0/scr6pl_scr6pl.rs new file mode 100644 index 000000000..9e6cfd460 --- /dev/null +++ b/mcxa276-pac/src/trng0/scr6pl_scr6pl.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SCR6PL` reader"] +pub type R = crate::R; +#[doc = "Register `SCR6PL` writer"] +pub type W = crate::W; +#[doc = "Field `RUN6P_MAX` reader - Run Length 6+ Maximum Limit"] +pub type Run6pMaxR = crate::FieldReader; +#[doc = "Field `RUN6P_MAX` writer - Run Length 6+ Maximum Limit"] +pub type Run6pMaxW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `RUN6P_RNG` reader - Run Length 6+ Range"] +pub type Run6pRngR = crate::FieldReader; +#[doc = "Field `RUN6P_RNG` writer - Run Length 6+ Range"] +pub type Run6pRngW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - Run Length 6+ Maximum Limit"] + #[inline(always)] + pub fn run6p_max(&self) -> Run6pMaxR { + Run6pMaxR::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 16:26 - Run Length 6+ Range"] + #[inline(always)] + pub fn run6p_rng(&self) -> Run6pRngR { + Run6pRngR::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:10 - Run Length 6+ Maximum Limit"] + #[inline(always)] + pub fn run6p_max(&mut self) -> Run6pMaxW { + Run6pMaxW::new(self, 0) + } + #[doc = "Bits 16:26 - Run Length 6+ Range"] + #[inline(always)] + pub fn run6p_rng(&mut self) -> Run6pRngW { + Run6pRngW::new(self, 16) + } +} +#[doc = "Statistical Check Run Length 6+ Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pl_scr6pl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr6pl_scr6pl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Scr6plScr6plSpec; +impl crate::RegisterSpec for Scr6plScr6plSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr6pl_scr6pl::R`](R) reader structure"] +impl crate::Readable for Scr6plScr6plSpec {} +#[doc = "`write(|w| ..)` method takes [`scr6pl_scr6pl::W`](W) writer structure"] +impl crate::Writable for Scr6plScr6plSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SCR6PL to value 0x0012_0011"] +impl crate::Resettable for Scr6plScr6plSpec { + const RESET_VALUE: u32 = 0x0012_0011; +} diff --git a/mcxa276-pac/src/trng0/sdctl.rs b/mcxa276-pac/src/trng0/sdctl.rs new file mode 100644 index 000000000..88338a4d9 --- /dev/null +++ b/mcxa276-pac/src/trng0/sdctl.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SDCTL` reader"] +pub type R = crate::R; +#[doc = "Register `SDCTL` writer"] +pub type W = crate::W; +#[doc = "Field `SAMP_SIZE` reader - Sample Size"] +pub type SampSizeR = crate::FieldReader; +#[doc = "Field `SAMP_SIZE` writer - Sample Size"] +pub type SampSizeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `ENT_DLY` reader - Entropy Delay"] +pub type EntDlyR = crate::FieldReader; +#[doc = "Field `ENT_DLY` writer - Entropy Delay"] +pub type EntDlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Sample Size"] + #[inline(always)] + pub fn samp_size(&self) -> SampSizeR { + SampSizeR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Entropy Delay"] + #[inline(always)] + pub fn ent_dly(&self) -> EntDlyR { + EntDlyR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Sample Size"] + #[inline(always)] + pub fn samp_size(&mut self) -> SampSizeW { + SampSizeW::new(self, 0) + } + #[doc = "Bits 16:31 - Entropy Delay"] + #[inline(always)] + pub fn ent_dly(&mut self) -> EntDlyW { + EntDlyW::new(self, 16) + } +} +#[doc = "Seed Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SdctlSpec; +impl crate::RegisterSpec for SdctlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdctl::R`](R) reader structure"] +impl crate::Readable for SdctlSpec {} +#[doc = "`write(|w| ..)` method takes [`sdctl::W`](W) writer structure"] +impl crate::Writable for SdctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SDCTL to value 0x0c80_0200"] +impl crate::Resettable for SdctlSpec { + const RESET_VALUE: u32 = 0x0c80_0200; +} diff --git a/mcxa276-pac/src/trng0/sec_cfg.rs b/mcxa276-pac/src/trng0/sec_cfg.rs new file mode 100644 index 000000000..091ed14eb --- /dev/null +++ b/mcxa276-pac/src/trng0/sec_cfg.rs @@ -0,0 +1,84 @@ +#[doc = "Register `SEC_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `SEC_CFG` writer"] +pub type W = crate::W; +#[doc = "If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NoPrgm { + #[doc = "0: TRNG configuration registers can be modified."] + NoPrgmOff = 0, + #[doc = "1: TRNG configuration registers cannot be modified."] + NoPrgmOn = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NoPrgm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_PRGM` reader - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] +pub type NoPrgmR = crate::BitReader; +impl NoPrgmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NoPrgm { + match self.bits { + false => NoPrgm::NoPrgmOff, + true => NoPrgm::NoPrgmOn, + } + } + #[doc = "TRNG configuration registers can be modified."] + #[inline(always)] + pub fn is_no_prgm_off(&self) -> bool { + *self == NoPrgm::NoPrgmOff + } + #[doc = "TRNG configuration registers cannot be modified."] + #[inline(always)] + pub fn is_no_prgm_on(&self) -> bool { + *self == NoPrgm::NoPrgmOn + } +} +#[doc = "Field `NO_PRGM` writer - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] +pub type NoPrgmW<'a, REG> = crate::BitWriter<'a, REG, NoPrgm>; +impl<'a, REG> NoPrgmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "TRNG configuration registers can be modified."] + #[inline(always)] + pub fn no_prgm_off(self) -> &'a mut crate::W { + self.variant(NoPrgm::NoPrgmOff) + } + #[doc = "TRNG configuration registers cannot be modified."] + #[inline(always)] + pub fn no_prgm_on(self) -> &'a mut crate::W { + self.variant(NoPrgm::NoPrgmOn) + } +} +impl R { + #[doc = "Bit 1 - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] + #[inline(always)] + pub fn no_prgm(&self) -> NoPrgmR { + NoPrgmR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] + #[inline(always)] + pub fn no_prgm(&mut self) -> NoPrgmW { + NoPrgmW::new(self, 1) + } +} +#[doc = "Security Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SecCfgSpec; +impl crate::RegisterSpec for SecCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sec_cfg::R`](R) reader structure"] +impl crate::Readable for SecCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`sec_cfg::W`](W) writer structure"] +impl crate::Writable for SecCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SEC_CFG to value 0"] +impl crate::Resettable for SecCfgSpec {} diff --git a/mcxa276-pac/src/trng0/status.rs b/mcxa276-pac/src/trng0/status.rs new file mode 100644 index 000000000..4588f863c --- /dev/null +++ b/mcxa276-pac/src/trng0/status.rs @@ -0,0 +1,676 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Test Fail, 1-Bit Run, Sampling 0s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf1br0 { + #[doc = "0: The 1-Bit Run, Sampling 0s Test has passed"] + Disable = 0, + #[doc = "1: The 1-Bit Run, Sampling 0s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf1br0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF1BR0` reader - Test Fail, 1-Bit Run, Sampling 0s."] +pub type Tf1br0R = crate::BitReader; +impl Tf1br0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf1br0 { + match self.bits { + false => Tf1br0::Disable, + true => Tf1br0::Enable, + } + } + #[doc = "The 1-Bit Run, Sampling 0s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf1br0::Disable + } + #[doc = "The 1-Bit Run, Sampling 0s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf1br0::Enable + } +} +#[doc = "Test Fail, 1-Bit Run, Sampling 1s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf1br1 { + #[doc = "0: The 1-Bit Run, Sampling 1s Test has passed"] + Disable = 0, + #[doc = "1: The 1-Bit Run, Sampling 1s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf1br1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF1BR1` reader - Test Fail, 1-Bit Run, Sampling 1s."] +pub type Tf1br1R = crate::BitReader; +impl Tf1br1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf1br1 { + match self.bits { + false => Tf1br1::Disable, + true => Tf1br1::Enable, + } + } + #[doc = "The 1-Bit Run, Sampling 1s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf1br1::Disable + } + #[doc = "The 1-Bit Run, Sampling 1s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf1br1::Enable + } +} +#[doc = "Test Fail, 2-Bit Run, Sampling 0s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf2br0 { + #[doc = "0: The 2-Bit Run, Sampling 0s Test has passed"] + Disable = 0, + #[doc = "1: The 2-Bit Run, Sampling 0s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf2br0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF2BR0` reader - Test Fail, 2-Bit Run, Sampling 0s."] +pub type Tf2br0R = crate::BitReader; +impl Tf2br0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf2br0 { + match self.bits { + false => Tf2br0::Disable, + true => Tf2br0::Enable, + } + } + #[doc = "The 2-Bit Run, Sampling 0s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf2br0::Disable + } + #[doc = "The 2-Bit Run, Sampling 0s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf2br0::Enable + } +} +#[doc = "Test Fail, 2-Bit Run, Sampling 1s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf2br1 { + #[doc = "0: The 2-Bit Run, Sampling 1s Test has passed"] + Disable = 0, + #[doc = "1: The 2-Bit Run, Sampling 1s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf2br1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF2BR1` reader - Test Fail, 2-Bit Run, Sampling 1s."] +pub type Tf2br1R = crate::BitReader; +impl Tf2br1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf2br1 { + match self.bits { + false => Tf2br1::Disable, + true => Tf2br1::Enable, + } + } + #[doc = "The 2-Bit Run, Sampling 1s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf2br1::Disable + } + #[doc = "The 2-Bit Run, Sampling 1s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf2br1::Enable + } +} +#[doc = "Test Fail, 3-Bit Run, Sampling 0s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf3br0 { + #[doc = "0: The 3-Bit Run, Sampling 0s Test has passed"] + Disable = 0, + #[doc = "1: The 3-Bit Run, Sampling 0s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf3br0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF3BR0` reader - Test Fail, 3-Bit Run, Sampling 0s."] +pub type Tf3br0R = crate::BitReader; +impl Tf3br0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf3br0 { + match self.bits { + false => Tf3br0::Disable, + true => Tf3br0::Enable, + } + } + #[doc = "The 3-Bit Run, Sampling 0s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf3br0::Disable + } + #[doc = "The 3-Bit Run, Sampling 0s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf3br0::Enable + } +} +#[doc = "Test Fail\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf3br1 { + #[doc = "0: The 3-Bit Run, Sampling 1s Test has passed"] + Disable = 0, + #[doc = "1: The 3-Bit Run, Sampling 1s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf3br1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF3BR1` reader - Test Fail"] +pub type Tf3br1R = crate::BitReader; +impl Tf3br1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf3br1 { + match self.bits { + false => Tf3br1::Disable, + true => Tf3br1::Enable, + } + } + #[doc = "The 3-Bit Run, Sampling 1s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf3br1::Disable + } + #[doc = "The 3-Bit Run, Sampling 1s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf3br1::Enable + } +} +#[doc = "Test Fail, 4-Bit Run, Sampling 0s\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf4br0 { + #[doc = "0: The 4-Bit Run, Sampling 0s Test has passed"] + Disable = 0, + #[doc = "1: The 4-Bit Run, Sampling 0s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf4br0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF4BR0` reader - Test Fail, 4-Bit Run, Sampling 0s"] +pub type Tf4br0R = crate::BitReader; +impl Tf4br0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf4br0 { + match self.bits { + false => Tf4br0::Disable, + true => Tf4br0::Enable, + } + } + #[doc = "The 4-Bit Run, Sampling 0s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf4br0::Disable + } + #[doc = "The 4-Bit Run, Sampling 0s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf4br0::Enable + } +} +#[doc = "Test Fail, 4-Bit Run, Sampling 1s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf4br1 { + #[doc = "0: The 4-Bit Run, Sampling 1s Test has passed"] + Disable = 0, + #[doc = "1: The 4-Bit Run, Sampling 1s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf4br1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF4BR1` reader - Test Fail, 4-Bit Run, Sampling 1s."] +pub type Tf4br1R = crate::BitReader; +impl Tf4br1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf4br1 { + match self.bits { + false => Tf4br1::Disable, + true => Tf4br1::Enable, + } + } + #[doc = "The 4-Bit Run, Sampling 1s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf4br1::Disable + } + #[doc = "The 4-Bit Run, Sampling 1s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf4br1::Enable + } +} +#[doc = "Test Fail, 5-Bit Run, Sampling 0s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf5br0 { + #[doc = "0: The 5-Bit Run, Sampling 0s Test has passed"] + Disable = 0, + #[doc = "1: The 5-Bit Run, Sampling 0s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf5br0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF5BR0` reader - Test Fail, 5-Bit Run, Sampling 0s."] +pub type Tf5br0R = crate::BitReader; +impl Tf5br0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf5br0 { + match self.bits { + false => Tf5br0::Disable, + true => Tf5br0::Enable, + } + } + #[doc = "The 5-Bit Run, Sampling 0s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf5br0::Disable + } + #[doc = "The 5-Bit Run, Sampling 0s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf5br0::Enable + } +} +#[doc = "Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf5br1 { + #[doc = "0: The 5-Bit Run, Sampling 1s Test has passed"] + Disable = 0, + #[doc = "1: The 5-Bit Run, Sampling 1s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf5br1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF5BR1` reader - Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed."] +pub type Tf5br1R = crate::BitReader; +impl Tf5br1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf5br1 { + match self.bits { + false => Tf5br1::Disable, + true => Tf5br1::Enable, + } + } + #[doc = "The 5-Bit Run, Sampling 1s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf5br1::Disable + } + #[doc = "The 5-Bit Run, Sampling 1s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf5br1::Enable + } +} +#[doc = "Test Fail, 6 Plus Bit Run, Sampling 0s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf6pbr0 { + #[doc = "0: The 6 Plus Bit Run, Sampling 0s Test has passed"] + Disable = 0, + #[doc = "1: the 6 Plus Bit Run, Sampling 0s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf6pbr0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF6PBR0` reader - Test Fail, 6 Plus Bit Run, Sampling 0s."] +pub type Tf6pbr0R = crate::BitReader; +impl Tf6pbr0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf6pbr0 { + match self.bits { + false => Tf6pbr0::Disable, + true => Tf6pbr0::Enable, + } + } + #[doc = "The 6 Plus Bit Run, Sampling 0s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf6pbr0::Disable + } + #[doc = "the 6 Plus Bit Run, Sampling 0s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf6pbr0::Enable + } +} +#[doc = "Test Fail, 6 Plus Bit Run, Sampling 1s.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tf6pbr1 { + #[doc = "0: The 6 Plus Bit Run, Sampling 1s Test has passed"] + Disable = 0, + #[doc = "1: The 6 Plus Bit Run, Sampling 1s Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tf6pbr1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TF6PBR1` reader - Test Fail, 6 Plus Bit Run, Sampling 1s."] +pub type Tf6pbr1R = crate::BitReader; +impl Tf6pbr1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tf6pbr1 { + match self.bits { + false => Tf6pbr1::Disable, + true => Tf6pbr1::Enable, + } + } + #[doc = "The 6 Plus Bit Run, Sampling 1s Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tf6pbr1::Disable + } + #[doc = "The 6 Plus Bit Run, Sampling 1s Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tf6pbr1::Enable + } +} +#[doc = "Test Fail, Sparse Bit.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tfsb { + #[doc = "0: The Sparse Bit Test has passed"] + Disable = 0, + #[doc = "1: The Sparse Bit Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tfsb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFSB` reader - Test Fail, Sparse Bit."] +pub type TfsbR = crate::BitReader; +impl TfsbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tfsb { + match self.bits { + false => Tfsb::Disable, + true => Tfsb::Enable, + } + } + #[doc = "The Sparse Bit Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tfsb::Disable + } + #[doc = "The Sparse Bit Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tfsb::Enable + } +} +#[doc = "Test Fail, Long Run.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tflr { + #[doc = "0: The Long Run Test has passed"] + Disable = 0, + #[doc = "1: The Long Run Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tflr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFLR` reader - Test Fail, Long Run."] +pub type TflrR = crate::BitReader; +impl TflrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tflr { + match self.bits { + false => Tflr::Disable, + true => Tflr::Enable, + } + } + #[doc = "The Long Run Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tflr::Disable + } + #[doc = "The Long Run Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tflr::Enable + } +} +#[doc = "Test Fail, Poker.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tfp { + #[doc = "0: The Poker Test has passed"] + Disable = 0, + #[doc = "1: The Poker Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tfp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFP` reader - Test Fail, Poker."] +pub type TfpR = crate::BitReader; +impl TfpR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tfp { + match self.bits { + false => Tfp::Disable, + true => Tfp::Enable, + } + } + #[doc = "The Poker Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tfp::Disable + } + #[doc = "The Poker Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tfp::Enable + } +} +#[doc = "Test Fail, Mono Bit.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tfmb { + #[doc = "0: The Mono Bit Test has passed"] + Disable = 0, + #[doc = "1: The Mono Bit Test has failed"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tfmb) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFMB` reader - Test Fail, Mono Bit."] +pub type TfmbR = crate::BitReader; +impl TfmbR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tfmb { + match self.bits { + false => Tfmb::Disable, + true => Tfmb::Enable, + } + } + #[doc = "The Mono Bit Test has passed"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Tfmb::Disable + } + #[doc = "The Mono Bit Test has failed"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Tfmb::Enable + } +} +#[doc = "Field `RETRY_CT` reader - RETRY COUNT"] +pub type RetryCtR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Test Fail, 1-Bit Run, Sampling 0s."] + #[inline(always)] + pub fn tf1br0(&self) -> Tf1br0R { + Tf1br0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Test Fail, 1-Bit Run, Sampling 1s."] + #[inline(always)] + pub fn tf1br1(&self) -> Tf1br1R { + Tf1br1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Test Fail, 2-Bit Run, Sampling 0s."] + #[inline(always)] + pub fn tf2br0(&self) -> Tf2br0R { + Tf2br0R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Test Fail, 2-Bit Run, Sampling 1s."] + #[inline(always)] + pub fn tf2br1(&self) -> Tf2br1R { + Tf2br1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Test Fail, 3-Bit Run, Sampling 0s."] + #[inline(always)] + pub fn tf3br0(&self) -> Tf3br0R { + Tf3br0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Test Fail"] + #[inline(always)] + pub fn tf3br1(&self) -> Tf3br1R { + Tf3br1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Test Fail, 4-Bit Run, Sampling 0s"] + #[inline(always)] + pub fn tf4br0(&self) -> Tf4br0R { + Tf4br0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Test Fail, 4-Bit Run, Sampling 1s."] + #[inline(always)] + pub fn tf4br1(&self) -> Tf4br1R { + Tf4br1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Test Fail, 5-Bit Run, Sampling 0s."] + #[inline(always)] + pub fn tf5br0(&self) -> Tf5br0R { + Tf5br0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed."] + #[inline(always)] + pub fn tf5br1(&self) -> Tf5br1R { + Tf5br1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Test Fail, 6 Plus Bit Run, Sampling 0s."] + #[inline(always)] + pub fn tf6pbr0(&self) -> Tf6pbr0R { + Tf6pbr0R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Test Fail, 6 Plus Bit Run, Sampling 1s."] + #[inline(always)] + pub fn tf6pbr1(&self) -> Tf6pbr1R { + Tf6pbr1R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Test Fail, Sparse Bit."] + #[inline(always)] + pub fn tfsb(&self) -> TfsbR { + TfsbR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Test Fail, Long Run."] + #[inline(always)] + pub fn tflr(&self) -> TflrR { + TflrR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Test Fail, Poker."] + #[inline(always)] + pub fn tfp(&self) -> TfpR { + TfpR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Test Fail, Mono Bit."] + #[inline(always)] + pub fn tfmb(&self) -> TfmbR { + TfmbR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:19 - RETRY COUNT"] + #[inline(always)] + pub fn retry_ct(&self) -> RetryCtR { + RetryCtR::new(((self.bits >> 16) & 0x0f) as u8) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/mcxa276-pac/src/trng0/totsam_totsam.rs b/mcxa276-pac/src/trng0/totsam_totsam.rs new file mode 100644 index 000000000..6cbf40e9c --- /dev/null +++ b/mcxa276-pac/src/trng0/totsam_totsam.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TOTSAM` reader"] +pub type R = crate::R; +#[doc = "Field `TOT_SAM` reader - Total Samples"] +pub type TotSamR = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Total Samples"] + #[inline(always)] + pub fn tot_sam(&self) -> TotSamR { + TotSamR::new(self.bits & 0x000f_ffff) + } +} +#[doc = "Total Samples Register\n\nYou can [`read`](crate::Reg::read) this register and get [`totsam_totsam::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TotsamTotsamSpec; +impl crate::RegisterSpec for TotsamTotsamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`totsam_totsam::R`](R) reader structure"] +impl crate::Readable for TotsamTotsamSpec {} +#[doc = "`reset()` method sets TOTSAM to value 0"] +impl crate::Resettable for TotsamTotsamSpec {} diff --git a/mcxa276-pac/src/trng0/vid1.rs b/mcxa276-pac/src/trng0/vid1.rs new file mode 100644 index 000000000..7e3f5bf6e --- /dev/null +++ b/mcxa276-pac/src/trng0/vid1.rs @@ -0,0 +1,132 @@ +#[doc = "Register `VID1` reader"] +pub type R = crate::R; +#[doc = "Shows the IP's Minor revision of the TRNG.\n\nValue on reset: 12"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MinRev { + #[doc = "12: Minor revision number for TRNG."] + MinRevVal = 12, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MinRev) -> Self { + variant as _ + } +} +impl crate::FieldSpec for MinRev { + type Ux = u8; +} +impl crate::IsEnum for MinRev {} +#[doc = "Field `MIN_REV` reader - Shows the IP's Minor revision of the TRNG."] +pub type MinRevR = crate::FieldReader; +impl MinRevR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 12 => Some(MinRev::MinRevVal), + _ => None, + } + } + #[doc = "Minor revision number for TRNG."] + #[inline(always)] + pub fn is_min_rev_val(&self) -> bool { + *self == MinRev::MinRevVal + } +} +#[doc = "Shows the IP's Major revision of the TRNG\n\nValue on reset: 20"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MajRev { + #[doc = "20: Major revision number for TRNG."] + MajRevVal = 20, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MajRev) -> Self { + variant as _ + } +} +impl crate::FieldSpec for MajRev { + type Ux = u8; +} +impl crate::IsEnum for MajRev {} +#[doc = "Field `MAJ_REV` reader - Shows the IP's Major revision of the TRNG"] +pub type MajRevR = crate::FieldReader; +impl MajRevR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 20 => Some(MajRev::MajRevVal), + _ => None, + } + } + #[doc = "Major revision number for TRNG."] + #[inline(always)] + pub fn is_maj_rev_val(&self) -> bool { + *self == MajRev::MajRevVal + } +} +#[doc = "Shows the IP ID.\n\nValue on reset: 48"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum IpId { + #[doc = "48: ID for TRNG."] + IpIdVal = 48, +} +impl From for u16 { + #[inline(always)] + fn from(variant: IpId) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IpId { + type Ux = u16; +} +impl crate::IsEnum for IpId {} +#[doc = "Field `IP_ID` reader - Shows the IP ID."] +pub type IpIdR = crate::FieldReader; +impl IpIdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 48 => Some(IpId::IpIdVal), + _ => None, + } + } + #[doc = "ID for TRNG."] + #[inline(always)] + pub fn is_ip_id_val(&self) -> bool { + *self == IpId::IpIdVal + } +} +impl R { + #[doc = "Bits 0:7 - Shows the IP's Minor revision of the TRNG."] + #[inline(always)] + pub fn min_rev(&self) -> MinRevR { + MinRevR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Shows the IP's Major revision of the TRNG"] + #[inline(always)] + pub fn maj_rev(&self) -> MajRevR { + MajRevR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:31 - Shows the IP ID."] + #[inline(always)] + pub fn ip_id(&self) -> IpIdR { + IpIdR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Version ID Register (MS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Vid1Spec; +impl crate::RegisterSpec for Vid1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid1::R`](R) reader structure"] +impl crate::Readable for Vid1Spec {} +#[doc = "`reset()` method sets VID1 to value 0x0030_140c"] +impl crate::Resettable for Vid1Spec { + const RESET_VALUE: u32 = 0x0030_140c; +} diff --git a/mcxa276-pac/src/trng0/vid2.rs b/mcxa276-pac/src/trng0/vid2.rs new file mode 100644 index 000000000..c32b027a3 --- /dev/null +++ b/mcxa276-pac/src/trng0/vid2.rs @@ -0,0 +1,171 @@ +#[doc = "Register `VID2` reader"] +pub type R = crate::R; +#[doc = "Shows the IP's Configuaration options for the TRNG.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ConfigOpt { + #[doc = "0: TRNG_CONFIG_OPT for TRNG."] + ConfigOptVal = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ConfigOpt) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ConfigOpt { + type Ux = u8; +} +impl crate::IsEnum for ConfigOpt {} +#[doc = "Field `CONFIG_OPT` reader - Shows the IP's Configuaration options for the TRNG."] +pub type ConfigOptR = crate::FieldReader; +impl ConfigOptR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ConfigOpt::ConfigOptVal), + _ => None, + } + } + #[doc = "TRNG_CONFIG_OPT for TRNG."] + #[inline(always)] + pub fn is_config_opt_val(&self) -> bool { + *self == ConfigOpt::ConfigOptVal + } +} +#[doc = "Shows the IP's ECO revision of the TRNG.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EcoRev { + #[doc = "0: TRNG_ECO_REV for TRNG."] + EcoRevVal = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EcoRev) -> Self { + variant as _ + } +} +impl crate::FieldSpec for EcoRev { + type Ux = u8; +} +impl crate::IsEnum for EcoRev {} +#[doc = "Field `ECO_REV` reader - Shows the IP's ECO revision of the TRNG."] +pub type EcoRevR = crate::FieldReader; +impl EcoRevR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(EcoRev::EcoRevVal), + _ => None, + } + } + #[doc = "TRNG_ECO_REV for TRNG."] + #[inline(always)] + pub fn is_eco_rev_val(&self) -> bool { + *self == EcoRev::EcoRevVal + } +} +#[doc = "Shows the integration options for the TRNG.\n\nValue on reset: 10"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IntgOpt { + #[doc = "10: INTG_OPT for TRNG."] + IntgOptVal = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IntgOpt) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IntgOpt { + type Ux = u8; +} +impl crate::IsEnum for IntgOpt {} +#[doc = "Field `INTG_OPT` reader - Shows the integration options for the TRNG."] +pub type IntgOptR = crate::FieldReader; +impl IntgOptR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 10 => Some(IntgOpt::IntgOptVal), + _ => None, + } + } + #[doc = "INTG_OPT for TRNG."] + #[inline(always)] + pub fn is_intg_opt_val(&self) -> bool { + *self == IntgOpt::IntgOptVal + } +} +#[doc = "Shows the ERA of the TRNG.\n\nValue on reset: 12"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Era { + #[doc = "12: ERA of the TRNG."] + EraVal = 12, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Era) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Era { + type Ux = u8; +} +impl crate::IsEnum for Era {} +#[doc = "Field `ERA` reader - Shows the ERA of the TRNG."] +pub type EraR = crate::FieldReader; +impl EraR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 12 => Some(Era::EraVal), + _ => None, + } + } + #[doc = "ERA of the TRNG."] + #[inline(always)] + pub fn is_era_val(&self) -> bool { + *self == Era::EraVal + } +} +impl R { + #[doc = "Bits 0:7 - Shows the IP's Configuaration options for the TRNG."] + #[inline(always)] + pub fn config_opt(&self) -> ConfigOptR { + ConfigOptR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Shows the IP's ECO revision of the TRNG."] + #[inline(always)] + pub fn eco_rev(&self) -> EcoRevR { + EcoRevR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Shows the integration options for the TRNG."] + #[inline(always)] + pub fn intg_opt(&self) -> IntgOptR { + IntgOptR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Shows the ERA of the TRNG."] + #[inline(always)] + pub fn era(&self) -> EraR { + EraR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID Register (LS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Vid2Spec; +impl crate::RegisterSpec for Vid2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid2::R`](R) reader structure"] +impl crate::Readable for Vid2Spec {} +#[doc = "`reset()` method sets VID2 to value 0x0c0a_0000"] +impl crate::Resettable for Vid2Spec { + const RESET_VALUE: u32 = 0x0c0a_0000; +} diff --git a/mcxa276-pac/src/udf0.rs b/mcxa276-pac/src/udf0.rs new file mode 100644 index 000000000..81a595164 --- /dev/null +++ b/mcxa276-pac/src/udf0.rs @@ -0,0 +1,50 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + udf_ctrl: UdfCtrl, + udf_status: UdfStatus, + udf_wr_data: UdfWrData, + udf_rd_data: UdfRdData, +} +impl RegisterBlock { + #[doc = "0x00 - Control register"] + #[inline(always)] + pub const fn udf_ctrl(&self) -> &UdfCtrl { + &self.udf_ctrl + } + #[doc = "0x04 - Status register"] + #[inline(always)] + pub const fn udf_status(&self) -> &UdfStatus { + &self.udf_status + } + #[doc = "0x08 - Data In Register"] + #[inline(always)] + pub const fn udf_wr_data(&self) -> &UdfWrData { + &self.udf_wr_data + } + #[doc = "0x0c - Data Out Register"] + #[inline(always)] + pub const fn udf_rd_data(&self) -> &UdfRdData { + &self.udf_rd_data + } +} +#[doc = "udf_ctrl (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_ctrl`] module"] +#[doc(alias = "udf_ctrl")] +pub type UdfCtrl = crate::Reg; +#[doc = "Control register"] +pub mod udf_ctrl; +#[doc = "udf_status (r) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_status`] module"] +#[doc(alias = "udf_status")] +pub type UdfStatus = crate::Reg; +#[doc = "Status register"] +pub mod udf_status; +#[doc = "udf_wr_data (w) register accessor: Data In Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_wr_data::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_wr_data`] module"] +#[doc(alias = "udf_wr_data")] +pub type UdfWrData = crate::Reg; +#[doc = "Data In Register"] +pub mod udf_wr_data; +#[doc = "udf_rd_data (r) register accessor: Data Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_rd_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_rd_data`] module"] +#[doc(alias = "udf_rd_data")] +pub type UdfRdData = crate::Reg; +#[doc = "Data Out Register"] +pub mod udf_rd_data; diff --git a/mcxa276-pac/src/udf0/udf_ctrl.rs b/mcxa276-pac/src/udf0/udf_ctrl.rs new file mode 100644 index 000000000..5a6939125 --- /dev/null +++ b/mcxa276-pac/src/udf0/udf_ctrl.rs @@ -0,0 +1,128 @@ +#[doc = "Register `udf_ctrl` reader"] +pub type R = crate::R; +#[doc = "Register `udf_ctrl` writer"] +pub type W = crate::W; +#[doc = "Field `salt` reader - Bits are internally XORed with i_custom"] +pub type SaltR = crate::FieldReader; +#[doc = "Field `salt` writer - Bits are internally XORed with i_custom"] +pub type SaltW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `lock` reader - Lock access to UDF"] +pub type LockR = crate::FieldReader; +#[doc = "Field `lock` writer - Lock access to UDF"] +pub type LockW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `reserved21` reader - RFU"] +pub type Reserved21R = crate::FieldReader; +#[doc = "Field `reserved21` writer - RFU"] +pub type Reserved21W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `udf_en` reader - Enable the UDF block"] +pub type UdfEnR = crate::FieldReader; +#[doc = "Field `udf_en` writer - Enable the UDF block"] +pub type UdfEnW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `reserved25` reader - RFU"] +pub type Reserved25R = crate::BitReader; +#[doc = "Field `reserved25` writer - RFU"] +pub type Reserved25W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `reserved27` reader - RFU"] +pub type Reserved27R = crate::FieldReader; +#[doc = "Field `reserved27` writer - RFU"] +pub type Reserved27W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `flush` reader - Flush UDF and return to reset state"] +pub type FlushR = crate::FieldReader; +#[doc = "Field `flush` writer - Flush UDF and return to reset state"] +pub type FlushW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `reserved31` reader - reserved"] +pub type Reserved31R = crate::BitReader; +impl R { + #[doc = "Bits 0:15 - Bits are internally XORed with i_custom"] + #[inline(always)] + pub fn salt(&self) -> SaltR { + SaltR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Lock access to UDF"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - RFU"] + #[inline(always)] + pub fn reserved21(&self) -> Reserved21R { + Reserved21R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:24 - Enable the UDF block"] + #[inline(always)] + pub fn udf_en(&self) -> UdfEnR { + UdfEnR::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bit 25 - RFU"] + #[inline(always)] + pub fn reserved25(&self) -> Reserved25R { + Reserved25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:27 - RFU"] + #[inline(always)] + pub fn reserved27(&self) -> Reserved27R { + Reserved27R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:30 - Flush UDF and return to reset state"] + #[inline(always)] + pub fn flush(&self) -> FlushR { + FlushR::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - reserved"] + #[inline(always)] + pub fn reserved31(&self) -> Reserved31R { + Reserved31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Bits are internally XORed with i_custom"] + #[inline(always)] + pub fn salt(&mut self) -> SaltW { + SaltW::new(self, 0) + } + #[doc = "Bits 16:18 - Lock access to UDF"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 16) + } + #[doc = "Bits 19:21 - RFU"] + #[inline(always)] + pub fn reserved21(&mut self) -> Reserved21W { + Reserved21W::new(self, 19) + } + #[doc = "Bits 22:24 - Enable the UDF block"] + #[inline(always)] + pub fn udf_en(&mut self) -> UdfEnW { + UdfEnW::new(self, 22) + } + #[doc = "Bit 25 - RFU"] + #[inline(always)] + pub fn reserved25(&mut self) -> Reserved25W { + Reserved25W::new(self, 25) + } + #[doc = "Bits 26:27 - RFU"] + #[inline(always)] + pub fn reserved27(&mut self) -> Reserved27W { + Reserved27W::new(self, 26) + } + #[doc = "Bits 28:30 - Flush UDF and return to reset state"] + #[inline(always)] + pub fn flush(&mut self) -> FlushW { + FlushW::new(self, 28) + } +} +#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UdfCtrlSpec; +impl crate::RegisterSpec for UdfCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`udf_ctrl::R`](R) reader structure"] +impl crate::Readable for UdfCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`udf_ctrl::W`](W) writer structure"] +impl crate::Writable for UdfCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets udf_ctrl to value 0x0080_0000"] +impl crate::Resettable for UdfCtrlSpec { + const RESET_VALUE: u32 = 0x0080_0000; +} diff --git a/mcxa276-pac/src/udf0/udf_rd_data.rs b/mcxa276-pac/src/udf0/udf_rd_data.rs new file mode 100644 index 000000000..0dd404bc3 --- /dev/null +++ b/mcxa276-pac/src/udf0/udf_rd_data.rs @@ -0,0 +1,20 @@ +#[doc = "Register `udf_rd_data` reader"] +pub type R = crate::R; +#[doc = "Field `o_dat` reader - no description available"] +pub type ODatR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - no description available"] + #[inline(always)] + pub fn o_dat(&self) -> ODatR { + ODatR::new(self.bits) + } +} +#[doc = "Data Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_rd_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UdfRdDataSpec; +impl crate::RegisterSpec for UdfRdDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`udf_rd_data::R`](R) reader structure"] +impl crate::Readable for UdfRdDataSpec {} +#[doc = "`reset()` method sets udf_rd_data to value 0"] +impl crate::Resettable for UdfRdDataSpec {} diff --git a/mcxa276-pac/src/udf0/udf_status.rs b/mcxa276-pac/src/udf0/udf_status.rs new file mode 100644 index 000000000..5365e145e --- /dev/null +++ b/mcxa276-pac/src/udf0/udf_status.rs @@ -0,0 +1,100 @@ +#[doc = "Register `udf_status` reader"] +pub type R = crate::R; +#[doc = "Status bits\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OStatus { + #[doc = "1: 5'b00001 = Reset"] + Reset = 1, + #[doc = "2: 5'b00010 = Init"] + Init = 2, + #[doc = "4: 5'b00100 = Warmup"] + Warmup = 4, + #[doc = "8: 5'b01000 = Ready"] + Ready = 8, + #[doc = "16: 5'b10000 = Error"] + Error = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OStatus) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OStatus { + type Ux = u8; +} +impl crate::IsEnum for OStatus {} +#[doc = "Field `o_status` reader - Status bits"] +pub type OStatusR = crate::FieldReader; +impl OStatusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(OStatus::Reset), + 2 => Some(OStatus::Init), + 4 => Some(OStatus::Warmup), + 8 => Some(OStatus::Ready), + 16 => Some(OStatus::Error), + _ => None, + } + } + #[doc = "5'b00001 = Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == OStatus::Reset + } + #[doc = "5'b00010 = Init"] + #[inline(always)] + pub fn is_init(&self) -> bool { + *self == OStatus::Init + } + #[doc = "5'b00100 = Warmup"] + #[inline(always)] + pub fn is_warmup(&self) -> bool { + *self == OStatus::Warmup + } + #[doc = "5'b01000 = Ready"] + #[inline(always)] + pub fn is_ready(&self) -> bool { + *self == OStatus::Ready + } + #[doc = "5'b10000 = Error"] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == OStatus::Error + } +} +#[doc = "Field `rsv` reader - RFU"] +pub type RsvR = crate::FieldReader; +#[doc = "Field `o_wait` reader - Indicates UDF is processing data"] +pub type OWaitR = crate::BitReader; +impl R { + #[doc = "Bits 0:4 - Status bits"] + #[inline(always)] + pub fn o_status(&self) -> OStatusR { + OStatusR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:30 - RFU"] + #[inline(always)] + pub fn rsv(&self) -> RsvR { + RsvR::new((self.bits >> 5) & 0x03ff_ffff) + } + #[doc = "Bit 31 - Indicates UDF is processing data"] + #[inline(always)] + pub fn o_wait(&self) -> OWaitR { + OWaitR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UdfStatusSpec; +impl crate::RegisterSpec for UdfStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`udf_status::R`](R) reader structure"] +impl crate::Readable for UdfStatusSpec {} +#[doc = "`reset()` method sets udf_status to value 0x01"] +impl crate::Resettable for UdfStatusSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/udf0/udf_wr_data.rs b/mcxa276-pac/src/udf0/udf_wr_data.rs new file mode 100644 index 000000000..b03074374 --- /dev/null +++ b/mcxa276-pac/src/udf0/udf_wr_data.rs @@ -0,0 +1,22 @@ +#[doc = "Register `udf_wr_data` writer"] +pub type W = crate::W; +#[doc = "Field `i_dat` writer - no description available"] +pub type IDatW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - no description available"] + #[inline(always)] + pub fn i_dat(&mut self) -> IDatW { + IDatW::new(self, 0) + } +} +#[doc = "Data In Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_wr_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UdfWrDataSpec; +impl crate::RegisterSpec for UdfWrDataSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`udf_wr_data::W`](W) writer structure"] +impl crate::Writable for UdfWrDataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets udf_wr_data to value 0"] +impl crate::Resettable for UdfWrDataSpec {} diff --git a/mcxa276-pac/src/usb0.rs b/mcxa276-pac/src/usb0.rs new file mode 100644 index 000000000..5b8a661a2 --- /dev/null +++ b/mcxa276-pac/src/usb0.rs @@ -0,0 +1,493 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + perid: Perid, + _reserved1: [u8; 0x03], + idcomp: Idcomp, + _reserved2: [u8; 0x03], + rev: Rev, + _reserved3: [u8; 0x03], + addinfo: Addinfo, + _reserved4: [u8; 0x03], + otgistat: Otgistat, + _reserved5: [u8; 0x03], + otgicr: Otgicr, + _reserved6: [u8; 0x03], + otgstat: Otgstat, + _reserved7: [u8; 0x03], + otgctl: Otgctl, + _reserved8: [u8; 0x63], + istat: Istat, + _reserved9: [u8; 0x03], + inten: Inten, + _reserved10: [u8; 0x03], + errstat: Errstat, + _reserved11: [u8; 0x03], + erren: Erren, + _reserved12: [u8; 0x03], + stat: Stat, + _reserved13: [u8; 0x03], + ctl: Ctl, + _reserved14: [u8; 0x03], + addr: Addr, + _reserved15: [u8; 0x03], + bdtpage1: Bdtpage1, + _reserved16: [u8; 0x03], + frmnuml: Frmnuml, + _reserved17: [u8; 0x03], + frmnumh: Frmnumh, + _reserved18: [u8; 0x03], + token: Token, + _reserved19: [u8; 0x03], + softhld: Softhld, + _reserved20: [u8; 0x03], + bdtpage2: Bdtpage2, + _reserved21: [u8; 0x03], + bdtpage3: Bdtpage3, + _reserved22: [u8; 0x0b], + endpoint: (), + _reserved23: [u8; 0x40], + usbctrl: Usbctrl, + _reserved24: [u8; 0x03], + observe: Observe, + _reserved25: [u8; 0x03], + control: Control, + _reserved26: [u8; 0x03], + usbtrc0: Usbtrc0, + _reserved27: [u8; 0x07], + usbfrmadjust: Usbfrmadjust, + _reserved28: [u8; 0x0f], + keep_alive_ctrl_rsvd: KeepAliveCtrlRsvd, + _reserved29: [u8; 0x03], + keep_alive_wkctrl_rsvd: KeepAliveWkctrlRsvd, + _reserved30: [u8; 0x03], + miscctrl: Miscctrl, + _reserved31: [u8; 0x03], + stall_il_dis: StallIlDis, + _reserved32: [u8; 0x03], + stall_ih_dis: StallIhDis, + _reserved33: [u8; 0x03], + stall_ol_dis: StallOlDis, + _reserved34: [u8; 0x03], + stall_oh_dis: StallOhDis, + _reserved35: [u8; 0x03], + clk_recover_ctrl: ClkRecoverCtrl, + _reserved36: [u8; 0x03], + clk_recover_irc_en: ClkRecoverIrcEn, + _reserved37: [u8; 0x0f], + clk_recover_int_en: ClkRecoverIntEn, + _reserved38: [u8; 0x07], + clk_recover_int_status: ClkRecoverIntStatus, +} +impl RegisterBlock { + #[doc = "0x00 - Peripheral ID"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } + #[doc = "0x04 - Peripheral ID Complement"] + #[inline(always)] + pub const fn idcomp(&self) -> &Idcomp { + &self.idcomp + } + #[doc = "0x08 - Peripheral Revision"] + #[inline(always)] + pub const fn rev(&self) -> &Rev { + &self.rev + } + #[doc = "0x0c - Peripheral Additional Information"] + #[inline(always)] + pub const fn addinfo(&self) -> &Addinfo { + &self.addinfo + } + #[doc = "0x10 - OTG Interrupt Status"] + #[inline(always)] + pub const fn otgistat(&self) -> &Otgistat { + &self.otgistat + } + #[doc = "0x14 - OTG Interrupt Control"] + #[inline(always)] + pub const fn otgicr(&self) -> &Otgicr { + &self.otgicr + } + #[doc = "0x18 - OTG Status"] + #[inline(always)] + pub const fn otgstat(&self) -> &Otgstat { + &self.otgstat + } + #[doc = "0x1c - OTG Control"] + #[inline(always)] + pub const fn otgctl(&self) -> &Otgctl { + &self.otgctl + } + #[doc = "0x80 - Interrupt Status"] + #[inline(always)] + pub const fn istat(&self) -> &Istat { + &self.istat + } + #[doc = "0x84 - Interrupt Enable"] + #[inline(always)] + pub const fn inten(&self) -> &Inten { + &self.inten + } + #[doc = "0x88 - Error Interrupt Status"] + #[inline(always)] + pub const fn errstat(&self) -> &Errstat { + &self.errstat + } + #[doc = "0x8c - Error Interrupt Enable"] + #[inline(always)] + pub const fn erren(&self) -> &Erren { + &self.erren + } + #[doc = "0x90 - Status"] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } + #[doc = "0x94 - Control"] + #[inline(always)] + pub const fn ctl(&self) -> &Ctl { + &self.ctl + } + #[doc = "0x98 - Address"] + #[inline(always)] + pub const fn addr(&self) -> &Addr { + &self.addr + } + #[doc = "0x9c - BDT Page 1"] + #[inline(always)] + pub const fn bdtpage1(&self) -> &Bdtpage1 { + &self.bdtpage1 + } + #[doc = "0xa0 - Frame Number Register Low"] + #[inline(always)] + pub const fn frmnuml(&self) -> &Frmnuml { + &self.frmnuml + } + #[doc = "0xa4 - Frame Number Register High"] + #[inline(always)] + pub const fn frmnumh(&self) -> &Frmnumh { + &self.frmnumh + } + #[doc = "0xa8 - Token"] + #[inline(always)] + pub const fn token(&self) -> &Token { + &self.token + } + #[doc = "0xac - SOF Threshold"] + #[inline(always)] + pub const fn softhld(&self) -> &Softhld { + &self.softhld + } + #[doc = "0xb0 - BDT Page 2"] + #[inline(always)] + pub const fn bdtpage2(&self) -> &Bdtpage2 { + &self.bdtpage2 + } + #[doc = "0xb4 - BDT Page 3"] + #[inline(always)] + pub const fn bdtpage3(&self) -> &Bdtpage3 { + &self.bdtpage3 + } + #[doc = "0xc0..0xd0 - Array of registers: ENDPT"] + #[inline(always)] + pub const fn endpoint(&self, n: usize) -> &Endpoint { + #[allow(clippy::no_effect)] + [(); 16][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(192) + .add(4 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0xc0..0xd0 - Array of registers: ENDPT"] + #[inline(always)] + pub fn endpoint_iter(&self) -> impl Iterator { + (0..16).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(192) + .add(4 * n) + .cast() + }) + } + #[doc = "0x100 - USB Control"] + #[inline(always)] + pub const fn usbctrl(&self) -> &Usbctrl { + &self.usbctrl + } + #[doc = "0x104 - USB OTG Observe"] + #[inline(always)] + pub const fn observe(&self) -> &Observe { + &self.observe + } + #[doc = "0x108 - USB OTG Control"] + #[inline(always)] + pub const fn control(&self) -> &Control { + &self.control + } + #[doc = "0x10c - USB Transceiver Control 0"] + #[inline(always)] + pub const fn usbtrc0(&self) -> &Usbtrc0 { + &self.usbtrc0 + } + #[doc = "0x114 - Frame Adjust"] + #[inline(always)] + pub const fn usbfrmadjust(&self) -> &Usbfrmadjust { + &self.usbfrmadjust + } + #[doc = "0x124 - Reserved"] + #[inline(always)] + pub const fn keep_alive_ctrl_rsvd(&self) -> &KeepAliveCtrlRsvd { + &self.keep_alive_ctrl_rsvd + } + #[doc = "0x128 - Reserved"] + #[inline(always)] + pub const fn keep_alive_wkctrl_rsvd(&self) -> &KeepAliveWkctrlRsvd { + &self.keep_alive_wkctrl_rsvd + } + #[doc = "0x12c - Miscellaneous Control"] + #[inline(always)] + pub const fn miscctrl(&self) -> &Miscctrl { + &self.miscctrl + } + #[doc = "0x130 - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction"] + #[inline(always)] + pub const fn stall_il_dis(&self) -> &StallIlDis { + &self.stall_il_dis + } + #[doc = "0x134 - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction"] + #[inline(always)] + pub const fn stall_ih_dis(&self) -> &StallIhDis { + &self.stall_ih_dis + } + #[doc = "0x138 - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction"] + #[inline(always)] + pub const fn stall_ol_dis(&self) -> &StallOlDis { + &self.stall_ol_dis + } + #[doc = "0x13c - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction"] + #[inline(always)] + pub const fn stall_oh_dis(&self) -> &StallOhDis { + &self.stall_oh_dis + } + #[doc = "0x140 - USB Clock Recovery Control"] + #[inline(always)] + pub const fn clk_recover_ctrl(&self) -> &ClkRecoverCtrl { + &self.clk_recover_ctrl + } + #[doc = "0x144 - FIRC Oscillator Enable"] + #[inline(always)] + pub const fn clk_recover_irc_en(&self) -> &ClkRecoverIrcEn { + &self.clk_recover_irc_en + } + #[doc = "0x154 - Clock Recovery Combined Interrupt Enable"] + #[inline(always)] + pub const fn clk_recover_int_en(&self) -> &ClkRecoverIntEn { + &self.clk_recover_int_en + } + #[doc = "0x15c - Clock Recovery Separated Interrupt Status"] + #[inline(always)] + pub const fn clk_recover_int_status(&self) -> &ClkRecoverIntStatus { + &self.clk_recover_int_status + } +} +#[doc = "PERID (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID"] +pub mod perid; +#[doc = "IDCOMP (r) register accessor: Peripheral ID Complement\n\nYou can [`read`](crate::Reg::read) this register and get [`idcomp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idcomp`] module"] +#[doc(alias = "IDCOMP")] +pub type Idcomp = crate::Reg; +#[doc = "Peripheral ID Complement"] +pub mod idcomp; +#[doc = "REV (r) register accessor: Peripheral Revision\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rev`] module"] +#[doc(alias = "REV")] +pub type Rev = crate::Reg; +#[doc = "Peripheral Revision"] +pub mod rev; +#[doc = "ADDINFO (r) register accessor: Peripheral Additional Information\n\nYou can [`read`](crate::Reg::read) this register and get [`addinfo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addinfo`] module"] +#[doc(alias = "ADDINFO")] +pub type Addinfo = crate::Reg; +#[doc = "Peripheral Additional Information"] +pub mod addinfo; +#[doc = "OTGISTAT (rw) register accessor: OTG Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgistat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgistat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgistat`] module"] +#[doc(alias = "OTGISTAT")] +pub type Otgistat = crate::Reg; +#[doc = "OTG Interrupt Status"] +pub mod otgistat; +#[doc = "OTGICR (rw) register accessor: OTG Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgicr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgicr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgicr`] module"] +#[doc(alias = "OTGICR")] +pub type Otgicr = crate::Reg; +#[doc = "OTG Interrupt Control"] +pub mod otgicr; +#[doc = "OTGSTAT (r) register accessor: OTG Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgstat`] module"] +#[doc(alias = "OTGSTAT")] +pub type Otgstat = crate::Reg; +#[doc = "OTG Status"] +pub mod otgstat; +#[doc = "OTGCTL (rw) register accessor: OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgctl`] module"] +#[doc(alias = "OTGCTL")] +pub type Otgctl = crate::Reg; +#[doc = "OTG Control"] +pub mod otgctl; +#[doc = "ISTAT (rw) register accessor: Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`istat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`istat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@istat`] module"] +#[doc(alias = "ISTAT")] +pub type Istat = crate::Reg; +#[doc = "Interrupt Status"] +pub mod istat; +#[doc = "INTEN (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`] module"] +#[doc(alias = "INTEN")] +pub type Inten = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inten; +#[doc = "ERRSTAT (rw) register accessor: Error Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errstat`] module"] +#[doc(alias = "ERRSTAT")] +pub type Errstat = crate::Reg; +#[doc = "Error Interrupt Status"] +pub mod errstat; +#[doc = "ERREN (rw) register accessor: Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erren`] module"] +#[doc(alias = "ERREN")] +pub type Erren = crate::Reg; +#[doc = "Error Interrupt Enable"] +pub mod erren; +#[doc = "STAT (r) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "CTL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`] module"] +#[doc(alias = "CTL")] +pub type Ctl = crate::Reg; +#[doc = "Control"] +pub mod ctl; +#[doc = "ADDR (rw) register accessor: Address\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`] module"] +#[doc(alias = "ADDR")] +pub type Addr = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "BDTPAGE1 (rw) register accessor: BDT Page 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtpage1`] module"] +#[doc(alias = "BDTPAGE1")] +pub type Bdtpage1 = crate::Reg; +#[doc = "BDT Page 1"] +pub mod bdtpage1; +#[doc = "FRMNUML (r) register accessor: Frame Number Register Low\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnuml::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frmnuml`] module"] +#[doc(alias = "FRMNUML")] +pub type Frmnuml = crate::Reg; +#[doc = "Frame Number Register Low"] +pub mod frmnuml; +#[doc = "FRMNUMH (r) register accessor: Frame Number Register High\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnumh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frmnumh`] module"] +#[doc(alias = "FRMNUMH")] +pub type Frmnumh = crate::Reg; +#[doc = "Frame Number Register High"] +pub mod frmnumh; +#[doc = "TOKEN (rw) register accessor: Token\n\nYou can [`read`](crate::Reg::read) this register and get [`token::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`token::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@token`] module"] +#[doc(alias = "TOKEN")] +pub type Token = crate::Reg; +#[doc = "Token"] +pub mod token; +#[doc = "SOFTHLD (rw) register accessor: SOF Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`softhld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`softhld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@softhld`] module"] +#[doc(alias = "SOFTHLD")] +pub type Softhld = crate::Reg; +#[doc = "SOF Threshold"] +pub mod softhld; +#[doc = "BDTPAGE2 (rw) register accessor: BDT Page 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtpage2`] module"] +#[doc(alias = "BDTPAGE2")] +pub type Bdtpage2 = crate::Reg; +#[doc = "BDT Page 2"] +pub mod bdtpage2; +#[doc = "BDTPAGE3 (rw) register accessor: BDT Page 3\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtpage3`] module"] +#[doc(alias = "BDTPAGE3")] +pub type Bdtpage3 = crate::Reg; +#[doc = "BDT Page 3"] +pub mod bdtpage3; +#[doc = "Array of registers: ENDPT"] +pub use self::endpoint::Endpoint; +#[doc = r"Cluster"] +#[doc = "Array of registers: ENDPT"] +pub mod endpoint; +#[doc = "USBCTRL (rw) register accessor: USB Control\n\nYou can [`read`](crate::Reg::read) this register and get [`usbctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbctrl`] module"] +#[doc(alias = "USBCTRL")] +pub type Usbctrl = crate::Reg; +#[doc = "USB Control"] +pub mod usbctrl; +#[doc = "OBSERVE (r) register accessor: USB OTG Observe\n\nYou can [`read`](crate::Reg::read) this register and get [`observe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@observe`] module"] +#[doc(alias = "OBSERVE")] +pub type Observe = crate::Reg; +#[doc = "USB OTG Observe"] +pub mod observe; +#[doc = "CONTROL (rw) register accessor: USB OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`] module"] +#[doc(alias = "CONTROL")] +pub type Control = crate::Reg; +#[doc = "USB OTG Control"] +pub mod control; +#[doc = "USBTRC0 (rw) register accessor: USB Transceiver Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`usbtrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbtrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbtrc0`] module"] +#[doc(alias = "USBTRC0")] +pub type Usbtrc0 = crate::Reg; +#[doc = "USB Transceiver Control 0"] +pub mod usbtrc0; +#[doc = "USBFRMADJUST (rw) register accessor: Frame Adjust\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfrmadjust::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfrmadjust::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbfrmadjust`] module"] +#[doc(alias = "USBFRMADJUST")] +pub type Usbfrmadjust = crate::Reg; +#[doc = "Frame Adjust"] +pub mod usbfrmadjust; +#[doc = "KEEP_ALIVE_CTRL_RSVD (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_ctrl_rsvd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_ctrl_rsvd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keep_alive_ctrl_rsvd`] module"] +#[doc(alias = "KEEP_ALIVE_CTRL_RSVD")] +pub type KeepAliveCtrlRsvd = crate::Reg; +#[doc = "Reserved"] +pub mod keep_alive_ctrl_rsvd; +#[doc = "KEEP_ALIVE_WKCTRL_RSVD (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_wkctrl_rsvd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_wkctrl_rsvd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keep_alive_wkctrl_rsvd`] module"] +#[doc(alias = "KEEP_ALIVE_WKCTRL_RSVD")] +pub type KeepAliveWkctrlRsvd = crate::Reg; +#[doc = "Reserved"] +pub mod keep_alive_wkctrl_rsvd; +#[doc = "MISCCTRL (rw) register accessor: Miscellaneous Control\n\nYou can [`read`](crate::Reg::read) this register and get [`miscctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`miscctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscctrl`] module"] +#[doc(alias = "MISCCTRL")] +pub type Miscctrl = crate::Reg; +#[doc = "Miscellaneous Control"] +pub mod miscctrl; +#[doc = "STALL_IL_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_il_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_il_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_il_dis`] module"] +#[doc(alias = "STALL_IL_DIS")] +pub type StallIlDis = crate::Reg; +#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction"] +pub mod stall_il_dis; +#[doc = "STALL_IH_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ih_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ih_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_ih_dis`] module"] +#[doc(alias = "STALL_IH_DIS")] +pub type StallIhDis = crate::Reg; +#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction"] +pub mod stall_ih_dis; +#[doc = "STALL_OL_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ol_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ol_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_ol_dis`] module"] +#[doc(alias = "STALL_OL_DIS")] +pub type StallOlDis = crate::Reg; +#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction"] +pub mod stall_ol_dis; +#[doc = "STALL_OH_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_oh_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_oh_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_oh_dis`] module"] +#[doc(alias = "STALL_OH_DIS")] +pub type StallOhDis = crate::Reg; +#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction"] +pub mod stall_oh_dis; +#[doc = "CLK_RECOVER_CTRL (rw) register accessor: USB Clock Recovery Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_ctrl`] module"] +#[doc(alias = "CLK_RECOVER_CTRL")] +pub type ClkRecoverCtrl = crate::Reg; +#[doc = "USB Clock Recovery Control"] +pub mod clk_recover_ctrl; +#[doc = "CLK_RECOVER_IRC_EN (rw) register accessor: FIRC Oscillator Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_irc_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_irc_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_irc_en`] module"] +#[doc(alias = "CLK_RECOVER_IRC_EN")] +pub type ClkRecoverIrcEn = crate::Reg; +#[doc = "FIRC Oscillator Enable"] +pub mod clk_recover_irc_en; +#[doc = "CLK_RECOVER_INT_EN (rw) register accessor: Clock Recovery Combined Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_int_en`] module"] +#[doc(alias = "CLK_RECOVER_INT_EN")] +pub type ClkRecoverIntEn = crate::Reg; +#[doc = "Clock Recovery Combined Interrupt Enable"] +pub mod clk_recover_int_en; +#[doc = "CLK_RECOVER_INT_STATUS (rw) register accessor: Clock Recovery Separated Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_int_status`] module"] +#[doc(alias = "CLK_RECOVER_INT_STATUS")] +pub type ClkRecoverIntStatus = crate::Reg; +#[doc = "Clock Recovery Separated Interrupt Status"] +pub mod clk_recover_int_status; diff --git a/mcxa276-pac/src/usb0/addinfo.rs b/mcxa276-pac/src/usb0/addinfo.rs new file mode 100644 index 000000000..7a66cacd5 --- /dev/null +++ b/mcxa276-pac/src/usb0/addinfo.rs @@ -0,0 +1,56 @@ +#[doc = "Register `ADDINFO` reader"] +pub type R = crate::R; +#[doc = "Host Mode Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Iehost { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Iehost) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IEHOST` reader - Host Mode Enable"] +pub type IehostR = crate::BitReader; +impl IehostR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Iehost { + match self.bits { + false => Iehost::Disabled, + true => Iehost::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Iehost::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Iehost::Enabled + } +} +impl R { + #[doc = "Bit 0 - Host Mode Enable"] + #[inline(always)] + pub fn iehost(&self) -> IehostR { + IehostR::new((self.bits & 1) != 0) + } +} +#[doc = "Peripheral Additional Information\n\nYou can [`read`](crate::Reg::read) this register and get [`addinfo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AddinfoSpec; +impl crate::RegisterSpec for AddinfoSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`addinfo::R`](R) reader structure"] +impl crate::Readable for AddinfoSpec {} +#[doc = "`reset()` method sets ADDINFO to value 0x01"] +impl crate::Resettable for AddinfoSpec { + const RESET_VALUE: u8 = 0x01; +} diff --git a/mcxa276-pac/src/usb0/addr.rs b/mcxa276-pac/src/usb0/addr.rs new file mode 100644 index 000000000..062df4342 --- /dev/null +++ b/mcxa276-pac/src/usb0/addr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - USB Address"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - USB Address"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LSEN` reader - Low Speed Enable"] +pub type LsenR = crate::BitReader; +#[doc = "Field `LSEN` writer - Low Speed Enable"] +pub type LsenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - USB Address"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new(self.bits & 0x7f) + } + #[doc = "Bit 7 - Low Speed Enable"] + #[inline(always)] + pub fn lsen(&self) -> LsenR { + LsenR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - USB Address"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 0) + } + #[doc = "Bit 7 - Low Speed Enable"] + #[inline(always)] + pub fn lsen(&mut self) -> LsenW { + LsenW::new(self, 7) + } +} +#[doc = "Address\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AddrSpec; +impl crate::RegisterSpec for AddrSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`addr::R`](R) reader structure"] +impl crate::Readable for AddrSpec {} +#[doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"] +impl crate::Writable for AddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for AddrSpec {} diff --git a/mcxa276-pac/src/usb0/bdtpage1.rs b/mcxa276-pac/src/usb0/bdtpage1.rs new file mode 100644 index 000000000..a4760a05a --- /dev/null +++ b/mcxa276-pac/src/usb0/bdtpage1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `BDTPAGE1` reader"] +pub type R = crate::R; +#[doc = "Register `BDTPAGE1` writer"] +pub type W = crate::W; +#[doc = "Field `BDTBA` reader - BDT Base Address"] +pub type BdtbaR = crate::FieldReader; +#[doc = "Field `BDTBA` writer - BDT Base Address"] +pub type BdtbaW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 1:7 - BDT Base Address"] + #[inline(always)] + pub fn bdtba(&self) -> BdtbaR { + BdtbaR::new((self.bits >> 1) & 0x7f) + } +} +impl W { + #[doc = "Bits 1:7 - BDT Base Address"] + #[inline(always)] + pub fn bdtba(&mut self) -> BdtbaW { + BdtbaW::new(self, 1) + } +} +#[doc = "BDT Page 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bdtpage1Spec; +impl crate::RegisterSpec for Bdtpage1Spec { + type Ux = u8; +} +#[doc = "`read()` method returns [`bdtpage1::R`](R) reader structure"] +impl crate::Readable for Bdtpage1Spec {} +#[doc = "`write(|w| ..)` method takes [`bdtpage1::W`](W) writer structure"] +impl crate::Writable for Bdtpage1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BDTPAGE1 to value 0"] +impl crate::Resettable for Bdtpage1Spec {} diff --git a/mcxa276-pac/src/usb0/bdtpage2.rs b/mcxa276-pac/src/usb0/bdtpage2.rs new file mode 100644 index 000000000..9bf00e9d3 --- /dev/null +++ b/mcxa276-pac/src/usb0/bdtpage2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `BDTPAGE2` reader"] +pub type R = crate::R; +#[doc = "Register `BDTPAGE2` writer"] +pub type W = crate::W; +#[doc = "Field `BDTBA` reader - BDT Base Address"] +pub type BdtbaR = crate::FieldReader; +#[doc = "Field `BDTBA` writer - BDT Base Address"] +pub type BdtbaW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - BDT Base Address"] + #[inline(always)] + pub fn bdtba(&self) -> BdtbaR { + BdtbaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - BDT Base Address"] + #[inline(always)] + pub fn bdtba(&mut self) -> BdtbaW { + BdtbaW::new(self, 0) + } +} +#[doc = "BDT Page 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bdtpage2Spec; +impl crate::RegisterSpec for Bdtpage2Spec { + type Ux = u8; +} +#[doc = "`read()` method returns [`bdtpage2::R`](R) reader structure"] +impl crate::Readable for Bdtpage2Spec {} +#[doc = "`write(|w| ..)` method takes [`bdtpage2::W`](W) writer structure"] +impl crate::Writable for Bdtpage2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BDTPAGE2 to value 0"] +impl crate::Resettable for Bdtpage2Spec {} diff --git a/mcxa276-pac/src/usb0/bdtpage3.rs b/mcxa276-pac/src/usb0/bdtpage3.rs new file mode 100644 index 000000000..92d757aa1 --- /dev/null +++ b/mcxa276-pac/src/usb0/bdtpage3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `BDTPAGE3` reader"] +pub type R = crate::R; +#[doc = "Register `BDTPAGE3` writer"] +pub type W = crate::W; +#[doc = "Field `BDTBA` reader - BDT Base Address"] +pub type BdtbaR = crate::FieldReader; +#[doc = "Field `BDTBA` writer - BDT Base Address"] +pub type BdtbaW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - BDT Base Address"] + #[inline(always)] + pub fn bdtba(&self) -> BdtbaR { + BdtbaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - BDT Base Address"] + #[inline(always)] + pub fn bdtba(&mut self) -> BdtbaW { + BdtbaW::new(self, 0) + } +} +#[doc = "BDT Page 3\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Bdtpage3Spec; +impl crate::RegisterSpec for Bdtpage3Spec { + type Ux = u8; +} +#[doc = "`read()` method returns [`bdtpage3::R`](R) reader structure"] +impl crate::Readable for Bdtpage3Spec {} +#[doc = "`write(|w| ..)` method takes [`bdtpage3::W`](W) writer structure"] +impl crate::Writable for Bdtpage3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BDTPAGE3 to value 0"] +impl crate::Resettable for Bdtpage3Spec {} diff --git a/mcxa276-pac/src/usb0/clk_recover_ctrl.rs b/mcxa276-pac/src/usb0/clk_recover_ctrl.rs new file mode 100644 index 000000000..879d63714 --- /dev/null +++ b/mcxa276-pac/src/usb0/clk_recover_ctrl.rs @@ -0,0 +1,273 @@ +#[doc = "Register `CLK_RECOVER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_RECOVER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the source for the initial FIRC trim fine value used after a reset.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TrimInitValSel { + #[doc = "0: Mid-scale"] + InitTrimFineMid = 0, + #[doc = "1: IFR"] + InitTrimFineIfr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TrimInitValSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TRIM_INIT_VAL_SEL` reader - Selects the source for the initial FIRC trim fine value used after a reset."] +pub type TrimInitValSelR = crate::BitReader; +impl TrimInitValSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TrimInitValSel { + match self.bits { + false => TrimInitValSel::InitTrimFineMid, + true => TrimInitValSel::InitTrimFineIfr, + } + } + #[doc = "Mid-scale"] + #[inline(always)] + pub fn is_init_trim_fine_mid(&self) -> bool { + *self == TrimInitValSel::InitTrimFineMid + } + #[doc = "IFR"] + #[inline(always)] + pub fn is_init_trim_fine_ifr(&self) -> bool { + *self == TrimInitValSel::InitTrimFineIfr + } +} +#[doc = "Field `TRIM_INIT_VAL_SEL` writer - Selects the source for the initial FIRC trim fine value used after a reset."] +pub type TrimInitValSelW<'a, REG> = crate::BitWriter<'a, REG, TrimInitValSel>; +impl<'a, REG> TrimInitValSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Mid-scale"] + #[inline(always)] + pub fn init_trim_fine_mid(self) -> &'a mut crate::W { + self.variant(TrimInitValSel::InitTrimFineMid) + } + #[doc = "IFR"] + #[inline(always)] + pub fn init_trim_fine_ifr(self) -> &'a mut crate::W { + self.variant(TrimInitValSel::InitTrimFineIfr) + } +} +#[doc = "Restart from IFR Trim Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RestartIfrtrimEn { + #[doc = "0: Trim fine adjustment always works based on the previous updated trim fine value."] + LoadTrimFineMid = 0, + #[doc = "1: Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable."] + LoadTrimFineIfr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RestartIfrtrimEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESTART_IFRTRIM_EN` reader - Restart from IFR Trim Value"] +pub type RestartIfrtrimEnR = crate::BitReader; +impl RestartIfrtrimEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RestartIfrtrimEn { + match self.bits { + false => RestartIfrtrimEn::LoadTrimFineMid, + true => RestartIfrtrimEn::LoadTrimFineIfr, + } + } + #[doc = "Trim fine adjustment always works based on the previous updated trim fine value."] + #[inline(always)] + pub fn is_load_trim_fine_mid(&self) -> bool { + *self == RestartIfrtrimEn::LoadTrimFineMid + } + #[doc = "Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable."] + #[inline(always)] + pub fn is_load_trim_fine_ifr(&self) -> bool { + *self == RestartIfrtrimEn::LoadTrimFineIfr + } +} +#[doc = "Field `RESTART_IFRTRIM_EN` writer - Restart from IFR Trim Value"] +pub type RestartIfrtrimEnW<'a, REG> = crate::BitWriter<'a, REG, RestartIfrtrimEn>; +impl<'a, REG> RestartIfrtrimEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Trim fine adjustment always works based on the previous updated trim fine value."] + #[inline(always)] + pub fn load_trim_fine_mid(self) -> &'a mut crate::W { + self.variant(RestartIfrtrimEn::LoadTrimFineMid) + } + #[doc = "Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable."] + #[inline(always)] + pub fn load_trim_fine_ifr(self) -> &'a mut crate::W { + self.variant(RestartIfrtrimEn::LoadTrimFineIfr) + } +} +#[doc = "Reset or Resume to Rough Phase Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ResetResumeRoughEn { + #[doc = "0: Always works in tracking phase after the first time rough phase, to track transition."] + KeepTrimFineOnReset = 0, + #[doc = "1: Go back to rough stage whenever a bus reset or bus resume occurs."] + UseIfrTrimFineOnReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ResetResumeRoughEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET_RESUME_ROUGH_EN` reader - Reset or Resume to Rough Phase Enable"] +pub type ResetResumeRoughEnR = crate::BitReader; +impl ResetResumeRoughEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ResetResumeRoughEn { + match self.bits { + false => ResetResumeRoughEn::KeepTrimFineOnReset, + true => ResetResumeRoughEn::UseIfrTrimFineOnReset, + } + } + #[doc = "Always works in tracking phase after the first time rough phase, to track transition."] + #[inline(always)] + pub fn is_keep_trim_fine_on_reset(&self) -> bool { + *self == ResetResumeRoughEn::KeepTrimFineOnReset + } + #[doc = "Go back to rough stage whenever a bus reset or bus resume occurs."] + #[inline(always)] + pub fn is_use_ifr_trim_fine_on_reset(&self) -> bool { + *self == ResetResumeRoughEn::UseIfrTrimFineOnReset + } +} +#[doc = "Field `RESET_RESUME_ROUGH_EN` writer - Reset or Resume to Rough Phase Enable"] +pub type ResetResumeRoughEnW<'a, REG> = crate::BitWriter<'a, REG, ResetResumeRoughEn>; +impl<'a, REG> ResetResumeRoughEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Always works in tracking phase after the first time rough phase, to track transition."] + #[inline(always)] + pub fn keep_trim_fine_on_reset(self) -> &'a mut crate::W { + self.variant(ResetResumeRoughEn::KeepTrimFineOnReset) + } + #[doc = "Go back to rough stage whenever a bus reset or bus resume occurs."] + #[inline(always)] + pub fn use_ifr_trim_fine_on_reset(self) -> &'a mut crate::W { + self.variant(ResetResumeRoughEn::UseIfrTrimFineOnReset) + } +} +#[doc = "Crystal-Less USB Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ClockRecoverEn { + #[doc = "0: Disable"] + DisClkRecover = 0, + #[doc = "1: Enable"] + EnClkRecover = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ClockRecoverEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLOCK_RECOVER_EN` reader - Crystal-Less USB Enable"] +pub type ClockRecoverEnR = crate::BitReader; +impl ClockRecoverEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ClockRecoverEn { + match self.bits { + false => ClockRecoverEn::DisClkRecover, + true => ClockRecoverEn::EnClkRecover, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_clk_recover(&self) -> bool { + *self == ClockRecoverEn::DisClkRecover + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_clk_recover(&self) -> bool { + *self == ClockRecoverEn::EnClkRecover + } +} +#[doc = "Field `CLOCK_RECOVER_EN` writer - Crystal-Less USB Enable"] +pub type ClockRecoverEnW<'a, REG> = crate::BitWriter<'a, REG, ClockRecoverEn>; +impl<'a, REG> ClockRecoverEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_clk_recover(self) -> &'a mut crate::W { + self.variant(ClockRecoverEn::DisClkRecover) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_clk_recover(self) -> &'a mut crate::W { + self.variant(ClockRecoverEn::EnClkRecover) + } +} +impl R { + #[doc = "Bit 3 - Selects the source for the initial FIRC trim fine value used after a reset."] + #[inline(always)] + pub fn trim_init_val_sel(&self) -> TrimInitValSelR { + TrimInitValSelR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Restart from IFR Trim Value"] + #[inline(always)] + pub fn restart_ifrtrim_en(&self) -> RestartIfrtrimEnR { + RestartIfrtrimEnR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reset or Resume to Rough Phase Enable"] + #[inline(always)] + pub fn reset_resume_rough_en(&self) -> ResetResumeRoughEnR { + ResetResumeRoughEnR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Crystal-Less USB Enable"] + #[inline(always)] + pub fn clock_recover_en(&self) -> ClockRecoverEnR { + ClockRecoverEnR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Selects the source for the initial FIRC trim fine value used after a reset."] + #[inline(always)] + pub fn trim_init_val_sel(&mut self) -> TrimInitValSelW { + TrimInitValSelW::new(self, 3) + } + #[doc = "Bit 5 - Restart from IFR Trim Value"] + #[inline(always)] + pub fn restart_ifrtrim_en(&mut self) -> RestartIfrtrimEnW { + RestartIfrtrimEnW::new(self, 5) + } + #[doc = "Bit 6 - Reset or Resume to Rough Phase Enable"] + #[inline(always)] + pub fn reset_resume_rough_en(&mut self) -> ResetResumeRoughEnW { + ResetResumeRoughEnW::new(self, 6) + } + #[doc = "Bit 7 - Crystal-Less USB Enable"] + #[inline(always)] + pub fn clock_recover_en(&mut self) -> ClockRecoverEnW { + ClockRecoverEnW::new(self, 7) + } +} +#[doc = "USB Clock Recovery Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkRecoverCtrlSpec; +impl crate::RegisterSpec for ClkRecoverCtrlSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`clk_recover_ctrl::R`](R) reader structure"] +impl crate::Readable for ClkRecoverCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`clk_recover_ctrl::W`](W) writer structure"] +impl crate::Writable for ClkRecoverCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLK_RECOVER_CTRL to value 0"] +impl crate::Resettable for ClkRecoverCtrlSpec {} diff --git a/mcxa276-pac/src/usb0/clk_recover_int_en.rs b/mcxa276-pac/src/usb0/clk_recover_int_en.rs new file mode 100644 index 000000000..e3108a262 --- /dev/null +++ b/mcxa276-pac/src/usb0/clk_recover_int_en.rs @@ -0,0 +1,86 @@ +#[doc = "Register `CLK_RECOVER_INT_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_RECOVER_INT_EN` writer"] +pub type W = crate::W; +#[doc = "Overflow error interrupt enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OvfErrorEn { + #[doc = "0: The interrupt is masked"] + MaskOvfErrInt = 0, + #[doc = "1: The interrupt is enabled"] + EnOvfErrInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OvfErrorEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVF_ERROR_EN` reader - Overflow error interrupt enable"] +pub type OvfErrorEnR = crate::BitReader; +impl OvfErrorEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvfErrorEn { + match self.bits { + false => OvfErrorEn::MaskOvfErrInt, + true => OvfErrorEn::EnOvfErrInt, + } + } + #[doc = "The interrupt is masked"] + #[inline(always)] + pub fn is_mask_ovf_err_int(&self) -> bool { + *self == OvfErrorEn::MaskOvfErrInt + } + #[doc = "The interrupt is enabled"] + #[inline(always)] + pub fn is_en_ovf_err_int(&self) -> bool { + *self == OvfErrorEn::EnOvfErrInt + } +} +#[doc = "Field `OVF_ERROR_EN` writer - Overflow error interrupt enable"] +pub type OvfErrorEnW<'a, REG> = crate::BitWriter<'a, REG, OvfErrorEn>; +impl<'a, REG> OvfErrorEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The interrupt is masked"] + #[inline(always)] + pub fn mask_ovf_err_int(self) -> &'a mut crate::W { + self.variant(OvfErrorEn::MaskOvfErrInt) + } + #[doc = "The interrupt is enabled"] + #[inline(always)] + pub fn en_ovf_err_int(self) -> &'a mut crate::W { + self.variant(OvfErrorEn::EnOvfErrInt) + } +} +impl R { + #[doc = "Bit 4 - Overflow error interrupt enable"] + #[inline(always)] + pub fn ovf_error_en(&self) -> OvfErrorEnR { + OvfErrorEnR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - Overflow error interrupt enable"] + #[inline(always)] + pub fn ovf_error_en(&mut self) -> OvfErrorEnW { + OvfErrorEnW::new(self, 4) + } +} +#[doc = "Clock Recovery Combined Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkRecoverIntEnSpec; +impl crate::RegisterSpec for ClkRecoverIntEnSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`clk_recover_int_en::R`](R) reader structure"] +impl crate::Readable for ClkRecoverIntEnSpec {} +#[doc = "`write(|w| ..)` method takes [`clk_recover_int_en::W`](W) writer structure"] +impl crate::Writable for ClkRecoverIntEnSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLK_RECOVER_INT_EN to value 0x10"] +impl crate::Resettable for ClkRecoverIntEnSpec { + const RESET_VALUE: u8 = 0x10; +} diff --git a/mcxa276-pac/src/usb0/clk_recover_int_status.rs b/mcxa276-pac/src/usb0/clk_recover_int_status.rs new file mode 100644 index 000000000..17d784822 --- /dev/null +++ b/mcxa276-pac/src/usb0/clk_recover_int_status.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLK_RECOVER_INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_RECOVER_INT_STATUS` writer"] +pub type W = crate::W; +#[doc = "Overflow Error Interrupt Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OvfError { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Unmasked interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OvfError) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OVF_ERROR` reader - Overflow Error Interrupt Status Flag"] +pub type OvfErrorR = crate::BitReader; +impl OvfErrorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OvfError { + match self.bits { + false => OvfError::IntNo, + true => OvfError::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == OvfError::IntNo + } + #[doc = "Unmasked interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == OvfError::IntYes + } +} +#[doc = "Field `OVF_ERROR` writer - Overflow Error Interrupt Status Flag"] +pub type OvfErrorW<'a, REG> = crate::BitWriter1C<'a, REG, OvfError>; +impl<'a, REG> OvfErrorW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(OvfError::IntNo) + } + #[doc = "Unmasked interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(OvfError::IntYes) + } +} +impl R { + #[doc = "Bit 4 - Overflow Error Interrupt Status Flag"] + #[inline(always)] + pub fn ovf_error(&self) -> OvfErrorR { + OvfErrorR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - Overflow Error Interrupt Status Flag"] + #[inline(always)] + pub fn ovf_error(&mut self) -> OvfErrorW { + OvfErrorW::new(self, 4) + } +} +#[doc = "Clock Recovery Separated Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkRecoverIntStatusSpec; +impl crate::RegisterSpec for ClkRecoverIntStatusSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`clk_recover_int_status::R`](R) reader structure"] +impl crate::Readable for ClkRecoverIntStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`clk_recover_int_status::W`](W) writer structure"] +impl crate::Writable for ClkRecoverIntStatusSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0x10; +} +#[doc = "`reset()` method sets CLK_RECOVER_INT_STATUS to value 0"] +impl crate::Resettable for ClkRecoverIntStatusSpec {} diff --git a/mcxa276-pac/src/usb0/clk_recover_irc_en.rs b/mcxa276-pac/src/usb0/clk_recover_irc_en.rs new file mode 100644 index 000000000..35e902b0d --- /dev/null +++ b/mcxa276-pac/src/usb0/clk_recover_irc_en.rs @@ -0,0 +1,86 @@ +#[doc = "Register `CLK_RECOVER_IRC_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_RECOVER_IRC_EN` writer"] +pub type W = crate::W; +#[doc = "Fast IRC enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IrcEn { + #[doc = "0: Disable"] + DisIrc = 0, + #[doc = "1: Enable"] + EnIrc = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IrcEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IRC_EN` reader - Fast IRC enable"] +pub type IrcEnR = crate::BitReader; +impl IrcEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IrcEn { + match self.bits { + false => IrcEn::DisIrc, + true => IrcEn::EnIrc, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_irc(&self) -> bool { + *self == IrcEn::DisIrc + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_irc(&self) -> bool { + *self == IrcEn::EnIrc + } +} +#[doc = "Field `IRC_EN` writer - Fast IRC enable"] +pub type IrcEnW<'a, REG> = crate::BitWriter<'a, REG, IrcEn>; +impl<'a, REG> IrcEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_irc(self) -> &'a mut crate::W { + self.variant(IrcEn::DisIrc) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_irc(self) -> &'a mut crate::W { + self.variant(IrcEn::EnIrc) + } +} +impl R { + #[doc = "Bit 1 - Fast IRC enable"] + #[inline(always)] + pub fn irc_en(&self) -> IrcEnR { + IrcEnR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Fast IRC enable"] + #[inline(always)] + pub fn irc_en(&mut self) -> IrcEnW { + IrcEnW::new(self, 1) + } +} +#[doc = "FIRC Oscillator Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_irc_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_irc_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkRecoverIrcEnSpec; +impl crate::RegisterSpec for ClkRecoverIrcEnSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`clk_recover_irc_en::R`](R) reader structure"] +impl crate::Readable for ClkRecoverIrcEnSpec {} +#[doc = "`write(|w| ..)` method takes [`clk_recover_irc_en::W`](W) writer structure"] +impl crate::Writable for ClkRecoverIrcEnSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLK_RECOVER_IRC_EN to value 0x01"] +impl crate::Resettable for ClkRecoverIrcEnSpec { + const RESET_VALUE: u8 = 0x01; +} diff --git a/mcxa276-pac/src/usb0/control.rs b/mcxa276-pac/src/usb0/control.rs new file mode 100644 index 000000000..7eb02207a --- /dev/null +++ b/mcxa276-pac/src/usb0/control.rs @@ -0,0 +1,176 @@ +#[doc = "Register `CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `CONTROL` writer"] +pub type W = crate::W; +#[doc = "VBUS Monitoring Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VbusSourceSel { + #[doc = "1: Resistive divider attached to a GPIO pin"] + Resistive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VbusSourceSel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VBUS_SOURCE_SEL` reader - VBUS Monitoring Source Select"] +pub type VbusSourceSelR = crate::BitReader; +impl VbusSourceSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + true => Some(VbusSourceSel::Resistive), + _ => None, + } + } + #[doc = "Resistive divider attached to a GPIO pin"] + #[inline(always)] + pub fn is_resistive(&self) -> bool { + *self == VbusSourceSel::Resistive + } +} +#[doc = "Field `VBUS_SOURCE_SEL` writer - VBUS Monitoring Source Select"] +pub type VbusSourceSelW<'a, REG> = crate::BitWriter<'a, REG, VbusSourceSel>; +impl<'a, REG> VbusSourceSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Resistive divider attached to a GPIO pin"] + #[inline(always)] + pub fn resistive(self) -> &'a mut crate::W { + self.variant(VbusSourceSel::Resistive) + } +} +#[doc = "VBUS Session Valid status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SessVld { + #[doc = "0: Below"] + SessVldLow = 0, + #[doc = "1: Above"] + SessVldHigh = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SessVld) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SESS_VLD` reader - VBUS Session Valid status"] +pub type SessVldR = crate::BitReader; +impl SessVldR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SessVld { + match self.bits { + false => SessVld::SessVldLow, + true => SessVld::SessVldHigh, + } + } + #[doc = "Below"] + #[inline(always)] + pub fn is_sess_vld_low(&self) -> bool { + *self == SessVld::SessVldLow + } + #[doc = "Above"] + #[inline(always)] + pub fn is_sess_vld_high(&self) -> bool { + *self == SessVld::SessVldHigh + } +} +#[doc = "DP Pullup in Non-OTG Device Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dppullupnonotg { + #[doc = "0: Disable"] + DisDeviceDpPu = 0, + #[doc = "1: Enabled"] + EnDeviceDpPu = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dppullupnonotg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPPULLUPNONOTG` reader - DP Pullup in Non-OTG Device Mode"] +pub type DppullupnonotgR = crate::BitReader; +impl DppullupnonotgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dppullupnonotg { + match self.bits { + false => Dppullupnonotg::DisDeviceDpPu, + true => Dppullupnonotg::EnDeviceDpPu, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_device_dp_pu(&self) -> bool { + *self == Dppullupnonotg::DisDeviceDpPu + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_en_device_dp_pu(&self) -> bool { + *self == Dppullupnonotg::EnDeviceDpPu + } +} +#[doc = "Field `DPPULLUPNONOTG` writer - DP Pullup in Non-OTG Device Mode"] +pub type DppullupnonotgW<'a, REG> = crate::BitWriter<'a, REG, Dppullupnonotg>; +impl<'a, REG> DppullupnonotgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_device_dp_pu(self) -> &'a mut crate::W { + self.variant(Dppullupnonotg::DisDeviceDpPu) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn en_device_dp_pu(self) -> &'a mut crate::W { + self.variant(Dppullupnonotg::EnDeviceDpPu) + } +} +impl R { + #[doc = "Bit 0 - VBUS Monitoring Source Select"] + #[inline(always)] + pub fn vbus_source_sel(&self) -> VbusSourceSelR { + VbusSourceSelR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - VBUS Session Valid status"] + #[inline(always)] + pub fn sess_vld(&self) -> SessVldR { + SessVldR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - DP Pullup in Non-OTG Device Mode"] + #[inline(always)] + pub fn dppullupnonotg(&self) -> DppullupnonotgR { + DppullupnonotgR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - VBUS Monitoring Source Select"] + #[inline(always)] + pub fn vbus_source_sel(&mut self) -> VbusSourceSelW { + VbusSourceSelW::new(self, 0) + } + #[doc = "Bit 4 - DP Pullup in Non-OTG Device Mode"] + #[inline(always)] + pub fn dppullupnonotg(&mut self) -> DppullupnonotgW { + DppullupnonotgW::new(self, 4) + } +} +#[doc = "USB OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ControlSpec; +impl crate::RegisterSpec for ControlSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`control::R`](R) reader structure"] +impl crate::Readable for ControlSpec {} +#[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"] +impl crate::Writable for ControlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONTROL to value 0"] +impl crate::Resettable for ControlSpec {} diff --git a/mcxa276-pac/src/usb0/ctl.rs b/mcxa276-pac/src/usb0/ctl.rs new file mode 100644 index 000000000..6656c7751 --- /dev/null +++ b/mcxa276-pac/src/usb0/ctl.rs @@ -0,0 +1,280 @@ +#[doc = "Register `CTL` reader"] +pub type R = crate::R; +#[doc = "Register `CTL` writer"] +pub type W = crate::W; +#[doc = "USB Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usbensofen { + #[doc = "0: Disable"] + DisUsbSof = 0, + #[doc = "1: Enable"] + EnUsbSof = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usbensofen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USBENSOFEN` reader - USB Enable"] +pub type UsbensofenR = crate::BitReader; +impl UsbensofenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Usbensofen { + match self.bits { + false => Usbensofen::DisUsbSof, + true => Usbensofen::EnUsbSof, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_usb_sof(&self) -> bool { + *self == Usbensofen::DisUsbSof + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_usb_sof(&self) -> bool { + *self == Usbensofen::EnUsbSof + } +} +#[doc = "Field `USBENSOFEN` writer - USB Enable"] +pub type UsbensofenW<'a, REG> = crate::BitWriter<'a, REG, Usbensofen>; +impl<'a, REG> UsbensofenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_usb_sof(self) -> &'a mut crate::W { + self.variant(Usbensofen::DisUsbSof) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_usb_sof(self) -> &'a mut crate::W { + self.variant(Usbensofen::EnUsbSof) + } +} +#[doc = "Field `ODDRST` reader - Odd Reset"] +pub type OddrstR = crate::BitReader; +#[doc = "Field `ODDRST` writer - Odd Reset"] +pub type OddrstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESUME` reader - Resume"] +pub type ResumeR = crate::BitReader; +#[doc = "Field `RESUME` writer - Resume"] +pub type ResumeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Host Mode Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hostmodeen { + #[doc = "0: USBFS operates in Device mode."] + EnDeviceMode = 0, + #[doc = "1: USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."] + EnHostMode = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hostmodeen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HOSTMODEEN` reader - Host Mode Enable"] +pub type HostmodeenR = crate::BitReader; +impl HostmodeenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hostmodeen { + match self.bits { + false => Hostmodeen::EnDeviceMode, + true => Hostmodeen::EnHostMode, + } + } + #[doc = "USBFS operates in Device mode."] + #[inline(always)] + pub fn is_en_device_mode(&self) -> bool { + *self == Hostmodeen::EnDeviceMode + } + #[doc = "USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."] + #[inline(always)] + pub fn is_en_host_mode(&self) -> bool { + *self == Hostmodeen::EnHostMode + } +} +#[doc = "Field `HOSTMODEEN` writer - Host Mode Enable"] +pub type HostmodeenW<'a, REG> = crate::BitWriter<'a, REG, Hostmodeen>; +impl<'a, REG> HostmodeenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "USBFS operates in Device mode."] + #[inline(always)] + pub fn en_device_mode(self) -> &'a mut crate::W { + self.variant(Hostmodeen::EnDeviceMode) + } + #[doc = "USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."] + #[inline(always)] + pub fn en_host_mode(self) -> &'a mut crate::W { + self.variant(Hostmodeen::EnHostMode) + } +} +#[doc = "Reset Signaling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Reset { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Reset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESET` reader - Reset Signaling Enable"] +pub type ResetR = crate::BitReader; +impl ResetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Reset { + match self.bits { + false => Reset::Disable, + true => Reset::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Reset::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Reset::Enable + } +} +#[doc = "Field `RESET` writer - Reset Signaling Enable"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; +impl<'a, REG> ResetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Reset::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Reset::Enable) + } +} +#[doc = "Field `TXSUSPENDTOKENBUSY` reader - TXD Suspend And Token Busy"] +pub type TxsuspendtokenbusyR = crate::BitReader; +#[doc = "Field `TXSUSPENDTOKENBUSY` writer - TXD Suspend And Token Busy"] +pub type TxsuspendtokenbusyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SE0` reader - Live USB Single-Ended Zero signal"] +pub type Se0R = crate::BitReader; +#[doc = "Field `SE0` writer - Live USB Single-Ended Zero signal"] +pub type Se0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JSTATE` reader - Live USB Differential Receiver JSTATE Signal"] +pub type JstateR = crate::BitReader; +#[doc = "Field `JSTATE` writer - Live USB Differential Receiver JSTATE Signal"] +pub type JstateW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - USB Enable"] + #[inline(always)] + pub fn usbensofen(&self) -> UsbensofenR { + UsbensofenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Odd Reset"] + #[inline(always)] + pub fn oddrst(&self) -> OddrstR { + OddrstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Resume"] + #[inline(always)] + pub fn resume(&self) -> ResumeR { + ResumeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Host Mode Enable"] + #[inline(always)] + pub fn hostmodeen(&self) -> HostmodeenR { + HostmodeenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reset Signaling Enable"] + #[inline(always)] + pub fn reset(&self) -> ResetR { + ResetR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXD Suspend And Token Busy"] + #[inline(always)] + pub fn txsuspendtokenbusy(&self) -> TxsuspendtokenbusyR { + TxsuspendtokenbusyR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Live USB Single-Ended Zero signal"] + #[inline(always)] + pub fn se0(&self) -> Se0R { + Se0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Live USB Differential Receiver JSTATE Signal"] + #[inline(always)] + pub fn jstate(&self) -> JstateR { + JstateR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - USB Enable"] + #[inline(always)] + pub fn usbensofen(&mut self) -> UsbensofenW { + UsbensofenW::new(self, 0) + } + #[doc = "Bit 1 - Odd Reset"] + #[inline(always)] + pub fn oddrst(&mut self) -> OddrstW { + OddrstW::new(self, 1) + } + #[doc = "Bit 2 - Resume"] + #[inline(always)] + pub fn resume(&mut self) -> ResumeW { + ResumeW::new(self, 2) + } + #[doc = "Bit 3 - Host Mode Enable"] + #[inline(always)] + pub fn hostmodeen(&mut self) -> HostmodeenW { + HostmodeenW::new(self, 3) + } + #[doc = "Bit 4 - Reset Signaling Enable"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 4) + } + #[doc = "Bit 5 - TXD Suspend And Token Busy"] + #[inline(always)] + pub fn txsuspendtokenbusy(&mut self) -> TxsuspendtokenbusyW { + TxsuspendtokenbusyW::new(self, 5) + } + #[doc = "Bit 6 - Live USB Single-Ended Zero signal"] + #[inline(always)] + pub fn se0(&mut self) -> Se0W { + Se0W::new(self, 6) + } + #[doc = "Bit 7 - Live USB Differential Receiver JSTATE Signal"] + #[inline(always)] + pub fn jstate(&mut self) -> JstateW { + JstateW::new(self, 7) + } +} +#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtlSpec; +impl crate::RegisterSpec for CtlSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`ctl::R`](R) reader structure"] +impl crate::Readable for CtlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] +impl crate::Writable for CtlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTL to value 0"] +impl crate::Resettable for CtlSpec {} diff --git a/mcxa276-pac/src/usb0/endpoint.rs b/mcxa276-pac/src/usb0/endpoint.rs new file mode 100644 index 000000000..a48556c8e --- /dev/null +++ b/mcxa276-pac/src/usb0/endpoint.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[doc = "Array of registers: ENDPT"] +#[doc(alias = "ENDPOINT")] +pub struct Endpoint { + endpt: Endpt, +} +impl Endpoint { + #[doc = "0x00 - Endpoint Control"] + #[inline(always)] + pub const fn endpt(&self) -> &Endpt { + &self.endpt + } +} +#[doc = "ENDPT (rw) register accessor: Endpoint Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endpt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endpt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endpt`] module"] +#[doc(alias = "ENDPT")] +pub type Endpt = crate::Reg; +#[doc = "Endpoint Control"] +pub mod endpt; diff --git a/mcxa276-pac/src/usb0/endpoint/endpt.rs b/mcxa276-pac/src/usb0/endpoint/endpt.rs new file mode 100644 index 000000000..050bd9620 --- /dev/null +++ b/mcxa276-pac/src/usb0/endpoint/endpt.rs @@ -0,0 +1,266 @@ +#[doc = "Register `ENDPT` reader"] +pub type R = crate::R; +#[doc = "Register `ENDPT` writer"] +pub type W = crate::W; +#[doc = "Field `EPHSHK` reader - Endpoint Handshaking Enable"] +pub type EphshkR = crate::BitReader; +#[doc = "Field `EPHSHK` writer - Endpoint Handshaking Enable"] +pub type EphshkW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EPSTALL` reader - Endpoint Stalled"] +pub type EpstallR = crate::BitReader; +#[doc = "Field `EPSTALL` writer - Endpoint Stalled"] +pub type EpstallW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EPTXEN` reader - Endpoint for TX transfers enable"] +pub type EptxenR = crate::BitReader; +#[doc = "Field `EPTXEN` writer - Endpoint for TX transfers enable"] +pub type EptxenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EPRXEN` reader - Endpoint for RX transfers enable"] +pub type EprxenR = crate::BitReader; +#[doc = "Field `EPRXEN` writer - Endpoint for RX transfers enable"] +pub type EprxenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Control Transfer Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Epctldis { + #[doc = "0: Enable"] + Enable = 0, + #[doc = "1: Disable"] + Disable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Epctldis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EPCTLDIS` reader - Control Transfer Disable"] +pub type EpctldisR = crate::BitReader; +impl EpctldisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Epctldis { + match self.bits { + false => Epctldis::Enable, + true => Epctldis::Disable, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Epctldis::Enable + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Epctldis::Disable + } +} +#[doc = "Field `EPCTLDIS` writer - Control Transfer Disable"] +pub type EpctldisW<'a, REG> = crate::BitWriter<'a, REG, Epctldis>; +impl<'a, REG> EpctldisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Epctldis::Enable) + } + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Epctldis::Disable) + } +} +#[doc = "Retry Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Retrydis { + #[doc = "0: Retried NAK'ed transactions in hardware."] + Retried = 0, + #[doc = "1: Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt becomes 1."] + DoNotRetried = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Retrydis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RETRYDIS` reader - Retry Disable"] +pub type RetrydisR = crate::BitReader; +impl RetrydisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Retrydis { + match self.bits { + false => Retrydis::Retried, + true => Retrydis::DoNotRetried, + } + } + #[doc = "Retried NAK'ed transactions in hardware."] + #[inline(always)] + pub fn is_retried(&self) -> bool { + *self == Retrydis::Retried + } + #[doc = "Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt becomes 1."] + #[inline(always)] + pub fn is_do_not_retried(&self) -> bool { + *self == Retrydis::DoNotRetried + } +} +#[doc = "Field `RETRYDIS` writer - Retry Disable"] +pub type RetrydisW<'a, REG> = crate::BitWriter<'a, REG, Retrydis>; +impl<'a, REG> RetrydisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Retried NAK'ed transactions in hardware."] + #[inline(always)] + pub fn retried(self) -> &'a mut crate::W { + self.variant(Retrydis::Retried) + } + #[doc = "Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt becomes 1."] + #[inline(always)] + pub fn do_not_retried(self) -> &'a mut crate::W { + self.variant(Retrydis::DoNotRetried) + } +} +#[doc = "Host Without A Hub\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hostwohub { + #[doc = "0: Connected using a hub (USBFS generates PRE_PID as required)"] + LsThruHub = 0, + #[doc = "1: Connected directly to host without a hub, or was used to attach"] + LsDirectConnect = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hostwohub) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HOSTWOHUB` reader - Host Without A Hub"] +pub type HostwohubR = crate::BitReader; +impl HostwohubR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hostwohub { + match self.bits { + false => Hostwohub::LsThruHub, + true => Hostwohub::LsDirectConnect, + } + } + #[doc = "Connected using a hub (USBFS generates PRE_PID as required)"] + #[inline(always)] + pub fn is_ls_thru_hub(&self) -> bool { + *self == Hostwohub::LsThruHub + } + #[doc = "Connected directly to host without a hub, or was used to attach"] + #[inline(always)] + pub fn is_ls_direct_connect(&self) -> bool { + *self == Hostwohub::LsDirectConnect + } +} +#[doc = "Field `HOSTWOHUB` writer - Host Without A Hub"] +pub type HostwohubW<'a, REG> = crate::BitWriter<'a, REG, Hostwohub>; +impl<'a, REG> HostwohubW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Connected using a hub (USBFS generates PRE_PID as required)"] + #[inline(always)] + pub fn ls_thru_hub(self) -> &'a mut crate::W { + self.variant(Hostwohub::LsThruHub) + } + #[doc = "Connected directly to host without a hub, or was used to attach"] + #[inline(always)] + pub fn ls_direct_connect(self) -> &'a mut crate::W { + self.variant(Hostwohub::LsDirectConnect) + } +} +impl R { + #[doc = "Bit 0 - Endpoint Handshaking Enable"] + #[inline(always)] + pub fn ephshk(&self) -> EphshkR { + EphshkR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint Stalled"] + #[inline(always)] + pub fn epstall(&self) -> EpstallR { + EpstallR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Endpoint for TX transfers enable"] + #[inline(always)] + pub fn eptxen(&self) -> EptxenR { + EptxenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Endpoint for RX transfers enable"] + #[inline(always)] + pub fn eprxen(&self) -> EprxenR { + EprxenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Control Transfer Disable"] + #[inline(always)] + pub fn epctldis(&self) -> EpctldisR { + EpctldisR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Retry Disable"] + #[inline(always)] + pub fn retrydis(&self) -> RetrydisR { + RetrydisR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Host Without A Hub"] + #[inline(always)] + pub fn hostwohub(&self) -> HostwohubR { + HostwohubR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Endpoint Handshaking Enable"] + #[inline(always)] + pub fn ephshk(&mut self) -> EphshkW { + EphshkW::new(self, 0) + } + #[doc = "Bit 1 - Endpoint Stalled"] + #[inline(always)] + pub fn epstall(&mut self) -> EpstallW { + EpstallW::new(self, 1) + } + #[doc = "Bit 2 - Endpoint for TX transfers enable"] + #[inline(always)] + pub fn eptxen(&mut self) -> EptxenW { + EptxenW::new(self, 2) + } + #[doc = "Bit 3 - Endpoint for RX transfers enable"] + #[inline(always)] + pub fn eprxen(&mut self) -> EprxenW { + EprxenW::new(self, 3) + } + #[doc = "Bit 4 - Control Transfer Disable"] + #[inline(always)] + pub fn epctldis(&mut self) -> EpctldisW { + EpctldisW::new(self, 4) + } + #[doc = "Bit 6 - Retry Disable"] + #[inline(always)] + pub fn retrydis(&mut self) -> RetrydisW { + RetrydisW::new(self, 6) + } + #[doc = "Bit 7 - Host Without A Hub"] + #[inline(always)] + pub fn hostwohub(&mut self) -> HostwohubW { + HostwohubW::new(self, 7) + } +} +#[doc = "Endpoint Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endpt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endpt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EndptSpec; +impl crate::RegisterSpec for EndptSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`endpt::R`](R) reader structure"] +impl crate::Readable for EndptSpec {} +#[doc = "`write(|w| ..)` method takes [`endpt::W`](W) writer structure"] +impl crate::Writable for EndptSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ENDPT to value 0"] +impl crate::Resettable for EndptSpec {} diff --git a/mcxa276-pac/src/usb0/erren.rs b/mcxa276-pac/src/usb0/erren.rs new file mode 100644 index 000000000..83b4162e2 --- /dev/null +++ b/mcxa276-pac/src/usb0/erren.rs @@ -0,0 +1,525 @@ +#[doc = "Register `ERREN` reader"] +pub type R = crate::R; +#[doc = "Register `ERREN` writer"] +pub type W = crate::W; +#[doc = "PIDERR Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Piderren { + #[doc = "0: Disable"] + DisPiderrInt = 0, + #[doc = "1: Enable"] + EnPiderrInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Piderren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIDERREN` reader - PIDERR Interrupt Enable"] +pub type PiderrenR = crate::BitReader; +impl PiderrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Piderren { + match self.bits { + false => Piderren::DisPiderrInt, + true => Piderren::EnPiderrInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_piderr_int(&self) -> bool { + *self == Piderren::DisPiderrInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_piderr_int(&self) -> bool { + *self == Piderren::EnPiderrInt + } +} +#[doc = "Field `PIDERREN` writer - PIDERR Interrupt Enable"] +pub type PiderrenW<'a, REG> = crate::BitWriter<'a, REG, Piderren>; +impl<'a, REG> PiderrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_piderr_int(self) -> &'a mut crate::W { + self.variant(Piderren::DisPiderrInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_piderr_int(self) -> &'a mut crate::W { + self.variant(Piderren::EnPiderrInt) + } +} +#[doc = "CRC5/EOF Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crc5eofen { + #[doc = "0: Disable"] + DisCrc5Int = 0, + #[doc = "1: Enable"] + EnCrc5Int = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crc5eofen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRC5EOFEN` reader - CRC5/EOF Interrupt Enable"] +pub type Crc5eofenR = crate::BitReader; +impl Crc5eofenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crc5eofen { + match self.bits { + false => Crc5eofen::DisCrc5Int, + true => Crc5eofen::EnCrc5Int, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_crc5_int(&self) -> bool { + *self == Crc5eofen::DisCrc5Int + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_crc5_int(&self) -> bool { + *self == Crc5eofen::EnCrc5Int + } +} +#[doc = "Field `CRC5EOFEN` writer - CRC5/EOF Interrupt Enable"] +pub type Crc5eofenW<'a, REG> = crate::BitWriter<'a, REG, Crc5eofen>; +impl<'a, REG> Crc5eofenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_crc5_int(self) -> &'a mut crate::W { + self.variant(Crc5eofen::DisCrc5Int) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_crc5_int(self) -> &'a mut crate::W { + self.variant(Crc5eofen::EnCrc5Int) + } +} +#[doc = "CRC16 Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crc16en { + #[doc = "0: Disable"] + DisCrc16Int = 0, + #[doc = "1: Enable"] + EnCrc16Int = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crc16en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRC16EN` reader - CRC16 Interrupt Enable"] +pub type Crc16enR = crate::BitReader; +impl Crc16enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crc16en { + match self.bits { + false => Crc16en::DisCrc16Int, + true => Crc16en::EnCrc16Int, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_crc16_int(&self) -> bool { + *self == Crc16en::DisCrc16Int + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_crc16_int(&self) -> bool { + *self == Crc16en::EnCrc16Int + } +} +#[doc = "Field `CRC16EN` writer - CRC16 Interrupt Enable"] +pub type Crc16enW<'a, REG> = crate::BitWriter<'a, REG, Crc16en>; +impl<'a, REG> Crc16enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_crc16_int(self) -> &'a mut crate::W { + self.variant(Crc16en::DisCrc16Int) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_crc16_int(self) -> &'a mut crate::W { + self.variant(Crc16en::EnCrc16Int) + } +} +#[doc = "DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dfn8en { + #[doc = "0: Disable"] + DisDfn8Int = 0, + #[doc = "1: Enable"] + EnDfn8Int = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dfn8en) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DFN8EN` reader - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] +pub type Dfn8enR = crate::BitReader; +impl Dfn8enR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dfn8en { + match self.bits { + false => Dfn8en::DisDfn8Int, + true => Dfn8en::EnDfn8Int, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_dfn8_int(&self) -> bool { + *self == Dfn8en::DisDfn8Int + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_dfn8_int(&self) -> bool { + *self == Dfn8en::EnDfn8Int + } +} +#[doc = "Field `DFN8EN` writer - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] +pub type Dfn8enW<'a, REG> = crate::BitWriter<'a, REG, Dfn8en>; +impl<'a, REG> Dfn8enW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_dfn8_int(self) -> &'a mut crate::W { + self.variant(Dfn8en::DisDfn8Int) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_dfn8_int(self) -> &'a mut crate::W { + self.variant(Dfn8en::EnDfn8Int) + } +} +#[doc = "BTOERR (Bus Timeout Error) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Btoerren { + #[doc = "0: Disable"] + DisBtoerrInt = 0, + #[doc = "1: Enable"] + EnBtoerrInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Btoerren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BTOERREN` reader - BTOERR (Bus Timeout Error) Interrupt Enable"] +pub type BtoerrenR = crate::BitReader; +impl BtoerrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Btoerren { + match self.bits { + false => Btoerren::DisBtoerrInt, + true => Btoerren::EnBtoerrInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_btoerr_int(&self) -> bool { + *self == Btoerren::DisBtoerrInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_btoerr_int(&self) -> bool { + *self == Btoerren::EnBtoerrInt + } +} +#[doc = "Field `BTOERREN` writer - BTOERR (Bus Timeout Error) Interrupt Enable"] +pub type BtoerrenW<'a, REG> = crate::BitWriter<'a, REG, Btoerren>; +impl<'a, REG> BtoerrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_btoerr_int(self) -> &'a mut crate::W { + self.variant(Btoerren::DisBtoerrInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_btoerr_int(self) -> &'a mut crate::W { + self.variant(Btoerren::EnBtoerrInt) + } +} +#[doc = "DMAERR Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmaerren { + #[doc = "0: Disable"] + DisDmaerrInt = 0, + #[doc = "1: Enable"] + EnDmaerrInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmaerren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMAERREN` reader - DMAERR Interrupt Enable"] +pub type DmaerrenR = crate::BitReader; +impl DmaerrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmaerren { + match self.bits { + false => Dmaerren::DisDmaerrInt, + true => Dmaerren::EnDmaerrInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_dmaerr_int(&self) -> bool { + *self == Dmaerren::DisDmaerrInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_dmaerr_int(&self) -> bool { + *self == Dmaerren::EnDmaerrInt + } +} +#[doc = "Field `DMAERREN` writer - DMAERR Interrupt Enable"] +pub type DmaerrenW<'a, REG> = crate::BitWriter<'a, REG, Dmaerren>; +impl<'a, REG> DmaerrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_dmaerr_int(self) -> &'a mut crate::W { + self.variant(Dmaerren::DisDmaerrInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_dmaerr_int(self) -> &'a mut crate::W { + self.variant(Dmaerren::EnDmaerrInt) + } +} +#[doc = "OWNERR Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ownerren { + #[doc = "0: Disable"] + DisOwnerrInt = 0, + #[doc = "1: Enable"] + EnOwnerrInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ownerren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OWNERREN` reader - OWNERR Interrupt Enable"] +pub type OwnerrenR = crate::BitReader; +impl OwnerrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ownerren { + match self.bits { + false => Ownerren::DisOwnerrInt, + true => Ownerren::EnOwnerrInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ownerr_int(&self) -> bool { + *self == Ownerren::DisOwnerrInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ownerr_int(&self) -> bool { + *self == Ownerren::EnOwnerrInt + } +} +#[doc = "Field `OWNERREN` writer - OWNERR Interrupt Enable"] +pub type OwnerrenW<'a, REG> = crate::BitWriter<'a, REG, Ownerren>; +impl<'a, REG> OwnerrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ownerr_int(self) -> &'a mut crate::W { + self.variant(Ownerren::DisOwnerrInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_ownerr_int(self) -> &'a mut crate::W { + self.variant(Ownerren::EnOwnerrInt) + } +} +#[doc = "BTSERR (Bit Stuff Error) Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Btserren { + #[doc = "0: Disable"] + DisBtserrenInt = 0, + #[doc = "1: Enable"] + EnBtserrenInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Btserren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BTSERREN` reader - BTSERR (Bit Stuff Error) Interrupt Enable"] +pub type BtserrenR = crate::BitReader; +impl BtserrenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Btserren { + match self.bits { + false => Btserren::DisBtserrenInt, + true => Btserren::EnBtserrenInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_btserren_int(&self) -> bool { + *self == Btserren::DisBtserrenInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_btserren_int(&self) -> bool { + *self == Btserren::EnBtserrenInt + } +} +#[doc = "Field `BTSERREN` writer - BTSERR (Bit Stuff Error) Interrupt Enable"] +pub type BtserrenW<'a, REG> = crate::BitWriter<'a, REG, Btserren>; +impl<'a, REG> BtserrenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_btserren_int(self) -> &'a mut crate::W { + self.variant(Btserren::DisBtserrenInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_btserren_int(self) -> &'a mut crate::W { + self.variant(Btserren::EnBtserrenInt) + } +} +impl R { + #[doc = "Bit 0 - PIDERR Interrupt Enable"] + #[inline(always)] + pub fn piderren(&self) -> PiderrenR { + PiderrenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CRC5/EOF Interrupt Enable"] + #[inline(always)] + pub fn crc5eofen(&self) -> Crc5eofenR { + Crc5eofenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CRC16 Interrupt Enable"] + #[inline(always)] + pub fn crc16en(&self) -> Crc16enR { + Crc16enR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] + #[inline(always)] + pub fn dfn8en(&self) -> Dfn8enR { + Dfn8enR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - BTOERR (Bus Timeout Error) Interrupt Enable"] + #[inline(always)] + pub fn btoerren(&self) -> BtoerrenR { + BtoerrenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DMAERR Interrupt Enable"] + #[inline(always)] + pub fn dmaerren(&self) -> DmaerrenR { + DmaerrenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - OWNERR Interrupt Enable"] + #[inline(always)] + pub fn ownerren(&self) -> OwnerrenR { + OwnerrenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - BTSERR (Bit Stuff Error) Interrupt Enable"] + #[inline(always)] + pub fn btserren(&self) -> BtserrenR { + BtserrenR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PIDERR Interrupt Enable"] + #[inline(always)] + pub fn piderren(&mut self) -> PiderrenW { + PiderrenW::new(self, 0) + } + #[doc = "Bit 1 - CRC5/EOF Interrupt Enable"] + #[inline(always)] + pub fn crc5eofen(&mut self) -> Crc5eofenW { + Crc5eofenW::new(self, 1) + } + #[doc = "Bit 2 - CRC16 Interrupt Enable"] + #[inline(always)] + pub fn crc16en(&mut self) -> Crc16enW { + Crc16enW::new(self, 2) + } + #[doc = "Bit 3 - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] + #[inline(always)] + pub fn dfn8en(&mut self) -> Dfn8enW { + Dfn8enW::new(self, 3) + } + #[doc = "Bit 4 - BTOERR (Bus Timeout Error) Interrupt Enable"] + #[inline(always)] + pub fn btoerren(&mut self) -> BtoerrenW { + BtoerrenW::new(self, 4) + } + #[doc = "Bit 5 - DMAERR Interrupt Enable"] + #[inline(always)] + pub fn dmaerren(&mut self) -> DmaerrenW { + DmaerrenW::new(self, 5) + } + #[doc = "Bit 6 - OWNERR Interrupt Enable"] + #[inline(always)] + pub fn ownerren(&mut self) -> OwnerrenW { + OwnerrenW::new(self, 6) + } + #[doc = "Bit 7 - BTSERR (Bit Stuff Error) Interrupt Enable"] + #[inline(always)] + pub fn btserren(&mut self) -> BtserrenW { + BtserrenW::new(self, 7) + } +} +#[doc = "Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErrenSpec; +impl crate::RegisterSpec for ErrenSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`erren::R`](R) reader structure"] +impl crate::Readable for ErrenSpec {} +#[doc = "`write(|w| ..)` method takes [`erren::W`](W) writer structure"] +impl crate::Writable for ErrenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ERREN to value 0"] +impl crate::Resettable for ErrenSpec {} diff --git a/mcxa276-pac/src/usb0/errstat.rs b/mcxa276-pac/src/usb0/errstat.rs new file mode 100644 index 000000000..6df6b2c37 --- /dev/null +++ b/mcxa276-pac/src/usb0/errstat.rs @@ -0,0 +1,526 @@ +#[doc = "Register `ERRSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `ERRSTAT` writer"] +pub type W = crate::W; +#[doc = "PID Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Piderr { + #[doc = "0: Did not fail"] + IntNo = 0, + #[doc = "1: Failed"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Piderr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PIDERR` reader - PID Error Flag"] +pub type PiderrR = crate::BitReader; +impl PiderrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Piderr { + match self.bits { + false => Piderr::IntNo, + true => Piderr::IntYes, + } + } + #[doc = "Did not fail"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Piderr::IntNo + } + #[doc = "Failed"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Piderr::IntYes + } +} +#[doc = "Field `PIDERR` writer - PID Error Flag"] +pub type PiderrW<'a, REG> = crate::BitWriter1C<'a, REG, Piderr>; +impl<'a, REG> PiderrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Did not fail"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Piderr::IntNo) + } + #[doc = "Failed"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Piderr::IntYes) + } +} +#[doc = "CRC5 Error or End of Frame Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crc5eof { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crc5eof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRC5EOF` reader - CRC5 Error or End of Frame Error Flag"] +pub type Crc5eofR = crate::BitReader; +impl Crc5eofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crc5eof { + match self.bits { + false => Crc5eof::IntNo, + true => Crc5eof::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Crc5eof::IntNo + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Crc5eof::IntYes + } +} +#[doc = "Field `CRC5EOF` writer - CRC5 Error or End of Frame Error Flag"] +pub type Crc5eofW<'a, REG> = crate::BitWriter1C<'a, REG, Crc5eof>; +impl<'a, REG> Crc5eofW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Crc5eof::IntNo) + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Crc5eof::IntYes) + } +} +#[doc = "CRC16 Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Crc16 { + #[doc = "0: Not rejected"] + IntNo = 0, + #[doc = "1: Rejected"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Crc16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CRC16` reader - CRC16 Error Flag"] +pub type Crc16R = crate::BitReader; +impl Crc16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Crc16 { + match self.bits { + false => Crc16::IntNo, + true => Crc16::IntYes, + } + } + #[doc = "Not rejected"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Crc16::IntNo + } + #[doc = "Rejected"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Crc16::IntYes + } +} +#[doc = "Field `CRC16` writer - CRC16 Error Flag"] +pub type Crc16W<'a, REG> = crate::BitWriter1C<'a, REG, Crc16>; +impl<'a, REG> Crc16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not rejected"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Crc16::IntNo) + } + #[doc = "Rejected"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Crc16::IntYes) + } +} +#[doc = "Data Field Not 8 Bits Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dfn8 { + #[doc = "0: Integer number of bytes"] + IntNo = 0, + #[doc = "1: Not an integer number of bytes"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dfn8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DFN8` reader - Data Field Not 8 Bits Flag"] +pub type Dfn8R = crate::BitReader; +impl Dfn8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dfn8 { + match self.bits { + false => Dfn8::IntNo, + true => Dfn8::IntYes, + } + } + #[doc = "Integer number of bytes"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Dfn8::IntNo + } + #[doc = "Not an integer number of bytes"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Dfn8::IntYes + } +} +#[doc = "Field `DFN8` writer - Data Field Not 8 Bits Flag"] +pub type Dfn8W<'a, REG> = crate::BitWriter1C<'a, REG, Dfn8>; +impl<'a, REG> Dfn8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Integer number of bytes"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Dfn8::IntNo) + } + #[doc = "Not an integer number of bytes"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Dfn8::IntYes) + } +} +#[doc = "Bus Turnaround Timeout Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Btoerr { + #[doc = "0: Not timed out"] + IntNo = 0, + #[doc = "1: Timed out"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Btoerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BTOERR` reader - Bus Turnaround Timeout Error Flag"] +pub type BtoerrR = crate::BitReader; +impl BtoerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Btoerr { + match self.bits { + false => Btoerr::IntNo, + true => Btoerr::IntYes, + } + } + #[doc = "Not timed out"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Btoerr::IntNo + } + #[doc = "Timed out"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Btoerr::IntYes + } +} +#[doc = "Field `BTOERR` writer - Bus Turnaround Timeout Error Flag"] +pub type BtoerrW<'a, REG> = crate::BitWriter1C<'a, REG, Btoerr>; +impl<'a, REG> BtoerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not timed out"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Btoerr::IntNo) + } + #[doc = "Timed out"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Btoerr::IntYes) + } +} +#[doc = "DMA Access Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmaerr { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmaerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMAERR` reader - DMA Access Error Flag"] +pub type DmaerrR = crate::BitReader; +impl DmaerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmaerr { + match self.bits { + false => Dmaerr::IntNo, + true => Dmaerr::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Dmaerr::IntNo + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Dmaerr::IntYes + } +} +#[doc = "Field `DMAERR` writer - DMA Access Error Flag"] +pub type DmaerrW<'a, REG> = crate::BitWriter1C<'a, REG, Dmaerr>; +impl<'a, REG> DmaerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Dmaerr::IntNo) + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Dmaerr::IntYes) + } +} +#[doc = "BD Unavailable Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ownerr { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ownerr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OWNERR` reader - BD Unavailable Error Flag"] +pub type OwnerrR = crate::BitReader; +impl OwnerrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ownerr { + match self.bits { + false => Ownerr::IntNo, + true => Ownerr::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Ownerr::IntNo + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Ownerr::IntYes + } +} +#[doc = "Field `OWNERR` writer - BD Unavailable Error Flag"] +pub type OwnerrW<'a, REG> = crate::BitWriter1C<'a, REG, Ownerr>; +impl<'a, REG> OwnerrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Ownerr::IntNo) + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Ownerr::IntYes) + } +} +#[doc = "Bit Stuff Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Btserr { + #[doc = "0: Packet not rejected due to the error"] + IntNo = 0, + #[doc = "1: Packet rejected due to the error"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Btserr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BTSERR` reader - Bit Stuff Error Flag"] +pub type BtserrR = crate::BitReader; +impl BtserrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Btserr { + match self.bits { + false => Btserr::IntNo, + true => Btserr::IntYes, + } + } + #[doc = "Packet not rejected due to the error"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Btserr::IntNo + } + #[doc = "Packet rejected due to the error"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Btserr::IntYes + } +} +#[doc = "Field `BTSERR` writer - Bit Stuff Error Flag"] +pub type BtserrW<'a, REG> = crate::BitWriter1C<'a, REG, Btserr>; +impl<'a, REG> BtserrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Packet not rejected due to the error"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Btserr::IntNo) + } + #[doc = "Packet rejected due to the error"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Btserr::IntYes) + } +} +impl R { + #[doc = "Bit 0 - PID Error Flag"] + #[inline(always)] + pub fn piderr(&self) -> PiderrR { + PiderrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CRC5 Error or End of Frame Error Flag"] + #[inline(always)] + pub fn crc5eof(&self) -> Crc5eofR { + Crc5eofR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CRC16 Error Flag"] + #[inline(always)] + pub fn crc16(&self) -> Crc16R { + Crc16R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Data Field Not 8 Bits Flag"] + #[inline(always)] + pub fn dfn8(&self) -> Dfn8R { + Dfn8R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Bus Turnaround Timeout Error Flag"] + #[inline(always)] + pub fn btoerr(&self) -> BtoerrR { + BtoerrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DMA Access Error Flag"] + #[inline(always)] + pub fn dmaerr(&self) -> DmaerrR { + DmaerrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - BD Unavailable Error Flag"] + #[inline(always)] + pub fn ownerr(&self) -> OwnerrR { + OwnerrR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Bit Stuff Error Flag"] + #[inline(always)] + pub fn btserr(&self) -> BtserrR { + BtserrR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PID Error Flag"] + #[inline(always)] + pub fn piderr(&mut self) -> PiderrW { + PiderrW::new(self, 0) + } + #[doc = "Bit 1 - CRC5 Error or End of Frame Error Flag"] + #[inline(always)] + pub fn crc5eof(&mut self) -> Crc5eofW { + Crc5eofW::new(self, 1) + } + #[doc = "Bit 2 - CRC16 Error Flag"] + #[inline(always)] + pub fn crc16(&mut self) -> Crc16W { + Crc16W::new(self, 2) + } + #[doc = "Bit 3 - Data Field Not 8 Bits Flag"] + #[inline(always)] + pub fn dfn8(&mut self) -> Dfn8W { + Dfn8W::new(self, 3) + } + #[doc = "Bit 4 - Bus Turnaround Timeout Error Flag"] + #[inline(always)] + pub fn btoerr(&mut self) -> BtoerrW { + BtoerrW::new(self, 4) + } + #[doc = "Bit 5 - DMA Access Error Flag"] + #[inline(always)] + pub fn dmaerr(&mut self) -> DmaerrW { + DmaerrW::new(self, 5) + } + #[doc = "Bit 6 - BD Unavailable Error Flag"] + #[inline(always)] + pub fn ownerr(&mut self) -> OwnerrW { + OwnerrW::new(self, 6) + } + #[doc = "Bit 7 - Bit Stuff Error Flag"] + #[inline(always)] + pub fn btserr(&mut self) -> BtserrW { + BtserrW::new(self, 7) + } +} +#[doc = "Error Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErrstatSpec; +impl crate::RegisterSpec for ErrstatSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`errstat::R`](R) reader structure"] +impl crate::Readable for ErrstatSpec {} +#[doc = "`write(|w| ..)` method takes [`errstat::W`](W) writer structure"] +impl crate::Writable for ErrstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0xff; +} +#[doc = "`reset()` method sets ERRSTAT to value 0"] +impl crate::Resettable for ErrstatSpec {} diff --git a/mcxa276-pac/src/usb0/frmnumh.rs b/mcxa276-pac/src/usb0/frmnumh.rs new file mode 100644 index 000000000..50c5f0d01 --- /dev/null +++ b/mcxa276-pac/src/usb0/frmnumh.rs @@ -0,0 +1,20 @@ +#[doc = "Register `FRMNUMH` reader"] +pub type R = crate::R; +#[doc = "Field `FRM` reader - Frame Number, Bits 8-10"] +pub type FrmR = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Frame Number, Bits 8-10"] + #[inline(always)] + pub fn frm(&self) -> FrmR { + FrmR::new(self.bits & 7) + } +} +#[doc = "Frame Number Register High\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnumh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrmnumhSpec; +impl crate::RegisterSpec for FrmnumhSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`frmnumh::R`](R) reader structure"] +impl crate::Readable for FrmnumhSpec {} +#[doc = "`reset()` method sets FRMNUMH to value 0"] +impl crate::Resettable for FrmnumhSpec {} diff --git a/mcxa276-pac/src/usb0/frmnuml.rs b/mcxa276-pac/src/usb0/frmnuml.rs new file mode 100644 index 000000000..63d8d1723 --- /dev/null +++ b/mcxa276-pac/src/usb0/frmnuml.rs @@ -0,0 +1,20 @@ +#[doc = "Register `FRMNUML` reader"] +pub type R = crate::R; +#[doc = "Field `FRM` reader - Frame Number, Bits 0-7"] +pub type FrmR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Frame Number, Bits 0-7"] + #[inline(always)] + pub fn frm(&self) -> FrmR { + FrmR::new(self.bits) + } +} +#[doc = "Frame Number Register Low\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnuml::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrmnumlSpec; +impl crate::RegisterSpec for FrmnumlSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`frmnuml::R`](R) reader structure"] +impl crate::Readable for FrmnumlSpec {} +#[doc = "`reset()` method sets FRMNUML to value 0"] +impl crate::Resettable for FrmnumlSpec {} diff --git a/mcxa276-pac/src/usb0/idcomp.rs b/mcxa276-pac/src/usb0/idcomp.rs new file mode 100644 index 000000000..a4fe6bf6f --- /dev/null +++ b/mcxa276-pac/src/usb0/idcomp.rs @@ -0,0 +1,22 @@ +#[doc = "Register `IDCOMP` reader"] +pub type R = crate::R; +#[doc = "Field `NID` reader - Negative Peripheral ID"] +pub type NidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:5 - Negative Peripheral ID"] + #[inline(always)] + pub fn nid(&self) -> NidR { + NidR::new(self.bits & 0x3f) + } +} +#[doc = "Peripheral ID Complement\n\nYou can [`read`](crate::Reg::read) this register and get [`idcomp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IdcompSpec; +impl crate::RegisterSpec for IdcompSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`idcomp::R`](R) reader structure"] +impl crate::Readable for IdcompSpec {} +#[doc = "`reset()` method sets IDCOMP to value 0xfb"] +impl crate::Resettable for IdcompSpec { + const RESET_VALUE: u8 = 0xfb; +} diff --git a/mcxa276-pac/src/usb0/inten.rs b/mcxa276-pac/src/usb0/inten.rs new file mode 100644 index 000000000..157c909e8 --- /dev/null +++ b/mcxa276-pac/src/usb0/inten.rs @@ -0,0 +1,525 @@ +#[doc = "Register `INTEN` reader"] +pub type R = crate::R; +#[doc = "Register `INTEN` writer"] +pub type W = crate::W; +#[doc = "USBRST Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usbrsten { + #[doc = "0: Disable"] + DisUsbrstInt = 0, + #[doc = "1: Enable"] + EnUsbrstInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usbrsten) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USBRSTEN` reader - USBRST Interrupt Enable"] +pub type UsbrstenR = crate::BitReader; +impl UsbrstenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Usbrsten { + match self.bits { + false => Usbrsten::DisUsbrstInt, + true => Usbrsten::EnUsbrstInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_usbrst_int(&self) -> bool { + *self == Usbrsten::DisUsbrstInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_usbrst_int(&self) -> bool { + *self == Usbrsten::EnUsbrstInt + } +} +#[doc = "Field `USBRSTEN` writer - USBRST Interrupt Enable"] +pub type UsbrstenW<'a, REG> = crate::BitWriter<'a, REG, Usbrsten>; +impl<'a, REG> UsbrstenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_usbrst_int(self) -> &'a mut crate::W { + self.variant(Usbrsten::DisUsbrstInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_usbrst_int(self) -> &'a mut crate::W { + self.variant(Usbrsten::EnUsbrstInt) + } +} +#[doc = "ERROR Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Erroren { + #[doc = "0: Disable"] + DisErrorInt = 0, + #[doc = "1: Enable"] + EnErrorInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Erroren) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROREN` reader - ERROR Interrupt Enable"] +pub type ErrorenR = crate::BitReader; +impl ErrorenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Erroren { + match self.bits { + false => Erroren::DisErrorInt, + true => Erroren::EnErrorInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_error_int(&self) -> bool { + *self == Erroren::DisErrorInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_error_int(&self) -> bool { + *self == Erroren::EnErrorInt + } +} +#[doc = "Field `ERROREN` writer - ERROR Interrupt Enable"] +pub type ErrorenW<'a, REG> = crate::BitWriter<'a, REG, Erroren>; +impl<'a, REG> ErrorenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_error_int(self) -> &'a mut crate::W { + self.variant(Erroren::DisErrorInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_error_int(self) -> &'a mut crate::W { + self.variant(Erroren::EnErrorInt) + } +} +#[doc = "SOFTOK Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Softoken { + #[doc = "0: Disable"] + DisSoftokInt = 0, + #[doc = "1: Enable"] + EnSoftokInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Softoken) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOFTOKEN` reader - SOFTOK Interrupt Enable"] +pub type SoftokenR = crate::BitReader; +impl SoftokenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Softoken { + match self.bits { + false => Softoken::DisSoftokInt, + true => Softoken::EnSoftokInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_softok_int(&self) -> bool { + *self == Softoken::DisSoftokInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_softok_int(&self) -> bool { + *self == Softoken::EnSoftokInt + } +} +#[doc = "Field `SOFTOKEN` writer - SOFTOK Interrupt Enable"] +pub type SoftokenW<'a, REG> = crate::BitWriter<'a, REG, Softoken>; +impl<'a, REG> SoftokenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_softok_int(self) -> &'a mut crate::W { + self.variant(Softoken::DisSoftokInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_softok_int(self) -> &'a mut crate::W { + self.variant(Softoken::EnSoftokInt) + } +} +#[doc = "TOKDNE Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tokdneen { + #[doc = "0: Disable"] + DisTokdneInt = 0, + #[doc = "1: Enable"] + EnTokdneInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tokdneen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TOKDNEEN` reader - TOKDNE Interrupt Enable"] +pub type TokdneenR = crate::BitReader; +impl TokdneenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tokdneen { + match self.bits { + false => Tokdneen::DisTokdneInt, + true => Tokdneen::EnTokdneInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_tokdne_int(&self) -> bool { + *self == Tokdneen::DisTokdneInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_tokdne_int(&self) -> bool { + *self == Tokdneen::EnTokdneInt + } +} +#[doc = "Field `TOKDNEEN` writer - TOKDNE Interrupt Enable"] +pub type TokdneenW<'a, REG> = crate::BitWriter<'a, REG, Tokdneen>; +impl<'a, REG> TokdneenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_tokdne_int(self) -> &'a mut crate::W { + self.variant(Tokdneen::DisTokdneInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_tokdne_int(self) -> &'a mut crate::W { + self.variant(Tokdneen::EnTokdneInt) + } +} +#[doc = "SLEEP Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sleepen { + #[doc = "0: Disable"] + DisSleepInt = 0, + #[doc = "1: Enable"] + EnSleepInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sleepen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPEN` reader - SLEEP Interrupt Enable"] +pub type SleepenR = crate::BitReader; +impl SleepenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sleepen { + match self.bits { + false => Sleepen::DisSleepInt, + true => Sleepen::EnSleepInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_sleep_int(&self) -> bool { + *self == Sleepen::DisSleepInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_sleep_int(&self) -> bool { + *self == Sleepen::EnSleepInt + } +} +#[doc = "Field `SLEEPEN` writer - SLEEP Interrupt Enable"] +pub type SleepenW<'a, REG> = crate::BitWriter<'a, REG, Sleepen>; +impl<'a, REG> SleepenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_sleep_int(self) -> &'a mut crate::W { + self.variant(Sleepen::DisSleepInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_sleep_int(self) -> &'a mut crate::W { + self.variant(Sleepen::EnSleepInt) + } +} +#[doc = "RESUME Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Resumeen { + #[doc = "0: Disable"] + DisResumeInt = 0, + #[doc = "1: Enable"] + EnResumeInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Resumeen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESUMEEN` reader - RESUME Interrupt Enable"] +pub type ResumeenR = crate::BitReader; +impl ResumeenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Resumeen { + match self.bits { + false => Resumeen::DisResumeInt, + true => Resumeen::EnResumeInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_resume_int(&self) -> bool { + *self == Resumeen::DisResumeInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_resume_int(&self) -> bool { + *self == Resumeen::EnResumeInt + } +} +#[doc = "Field `RESUMEEN` writer - RESUME Interrupt Enable"] +pub type ResumeenW<'a, REG> = crate::BitWriter<'a, REG, Resumeen>; +impl<'a, REG> ResumeenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_resume_int(self) -> &'a mut crate::W { + self.variant(Resumeen::DisResumeInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_resume_int(self) -> &'a mut crate::W { + self.variant(Resumeen::EnResumeInt) + } +} +#[doc = "ATTACH Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Attachen { + #[doc = "0: Disable"] + DisAttachInt = 0, + #[doc = "1: Enable"] + EnAttachInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Attachen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ATTACHEN` reader - ATTACH Interrupt Enable"] +pub type AttachenR = crate::BitReader; +impl AttachenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Attachen { + match self.bits { + false => Attachen::DisAttachInt, + true => Attachen::EnAttachInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_attach_int(&self) -> bool { + *self == Attachen::DisAttachInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_attach_int(&self) -> bool { + *self == Attachen::EnAttachInt + } +} +#[doc = "Field `ATTACHEN` writer - ATTACH Interrupt Enable"] +pub type AttachenW<'a, REG> = crate::BitWriter<'a, REG, Attachen>; +impl<'a, REG> AttachenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_attach_int(self) -> &'a mut crate::W { + self.variant(Attachen::DisAttachInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_attach_int(self) -> &'a mut crate::W { + self.variant(Attachen::EnAttachInt) + } +} +#[doc = "STALL Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stallen { + #[doc = "0: Disable"] + DisStallInt = 0, + #[doc = "1: Enable"] + EnStallInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stallen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALLEN` reader - STALL Interrupt Enable"] +pub type StallenR = crate::BitReader; +impl StallenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stallen { + match self.bits { + false => Stallen::DisStallInt, + true => Stallen::EnStallInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_stall_int(&self) -> bool { + *self == Stallen::DisStallInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_stall_int(&self) -> bool { + *self == Stallen::EnStallInt + } +} +#[doc = "Field `STALLEN` writer - STALL Interrupt Enable"] +pub type StallenW<'a, REG> = crate::BitWriter<'a, REG, Stallen>; +impl<'a, REG> StallenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_stall_int(self) -> &'a mut crate::W { + self.variant(Stallen::DisStallInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_stall_int(self) -> &'a mut crate::W { + self.variant(Stallen::EnStallInt) + } +} +impl R { + #[doc = "Bit 0 - USBRST Interrupt Enable"] + #[inline(always)] + pub fn usbrsten(&self) -> UsbrstenR { + UsbrstenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERROR Interrupt Enable"] + #[inline(always)] + pub fn erroren(&self) -> ErrorenR { + ErrorenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SOFTOK Interrupt Enable"] + #[inline(always)] + pub fn softoken(&self) -> SoftokenR { + SoftokenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TOKDNE Interrupt Enable"] + #[inline(always)] + pub fn tokdneen(&self) -> TokdneenR { + TokdneenR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - SLEEP Interrupt Enable"] + #[inline(always)] + pub fn sleepen(&self) -> SleepenR { + SleepenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RESUME Interrupt Enable"] + #[inline(always)] + pub fn resumeen(&self) -> ResumeenR { + ResumeenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ATTACH Interrupt Enable"] + #[inline(always)] + pub fn attachen(&self) -> AttachenR { + AttachenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - STALL Interrupt Enable"] + #[inline(always)] + pub fn stallen(&self) -> StallenR { + StallenR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - USBRST Interrupt Enable"] + #[inline(always)] + pub fn usbrsten(&mut self) -> UsbrstenW { + UsbrstenW::new(self, 0) + } + #[doc = "Bit 1 - ERROR Interrupt Enable"] + #[inline(always)] + pub fn erroren(&mut self) -> ErrorenW { + ErrorenW::new(self, 1) + } + #[doc = "Bit 2 - SOFTOK Interrupt Enable"] + #[inline(always)] + pub fn softoken(&mut self) -> SoftokenW { + SoftokenW::new(self, 2) + } + #[doc = "Bit 3 - TOKDNE Interrupt Enable"] + #[inline(always)] + pub fn tokdneen(&mut self) -> TokdneenW { + TokdneenW::new(self, 3) + } + #[doc = "Bit 4 - SLEEP Interrupt Enable"] + #[inline(always)] + pub fn sleepen(&mut self) -> SleepenW { + SleepenW::new(self, 4) + } + #[doc = "Bit 5 - RESUME Interrupt Enable"] + #[inline(always)] + pub fn resumeen(&mut self) -> ResumeenW { + ResumeenW::new(self, 5) + } + #[doc = "Bit 6 - ATTACH Interrupt Enable"] + #[inline(always)] + pub fn attachen(&mut self) -> AttachenW { + AttachenW::new(self, 6) + } + #[doc = "Bit 7 - STALL Interrupt Enable"] + #[inline(always)] + pub fn stallen(&mut self) -> StallenW { + StallenW::new(self, 7) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntenSpec; +impl crate::RegisterSpec for IntenSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`inten::R`](R) reader structure"] +impl crate::Readable for IntenSpec {} +#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"] +impl crate::Writable for IntenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets INTEN to value 0"] +impl crate::Resettable for IntenSpec {} diff --git a/mcxa276-pac/src/usb0/istat.rs b/mcxa276-pac/src/usb0/istat.rs new file mode 100644 index 000000000..cae467a9e --- /dev/null +++ b/mcxa276-pac/src/usb0/istat.rs @@ -0,0 +1,526 @@ +#[doc = "Register `ISTAT` reader"] +pub type R = crate::R; +#[doc = "Register `ISTAT` writer"] +pub type W = crate::W; +#[doc = "USB Reset Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usbrst { + #[doc = "0: Not detected"] + IntNo = 0, + #[doc = "1: Detected"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usbrst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USBRST` reader - USB Reset Flag"] +pub type UsbrstR = crate::BitReader; +impl UsbrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Usbrst { + match self.bits { + false => Usbrst::IntNo, + true => Usbrst::IntYes, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Usbrst::IntNo + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Usbrst::IntYes + } +} +#[doc = "Field `USBRST` writer - USB Reset Flag"] +pub type UsbrstW<'a, REG> = crate::BitWriter1C<'a, REG, Usbrst>; +impl<'a, REG> UsbrstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Usbrst::IntNo) + } + #[doc = "Detected"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Usbrst::IntYes) + } +} +#[doc = "Error Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Error { + #[doc = "0: Error did not occur"] + IntNo = 0, + #[doc = "1: Error occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Error) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ERROR` reader - Error Flag"] +pub type ErrorR = crate::BitReader; +impl ErrorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Error { + match self.bits { + false => Error::IntNo, + true => Error::IntYes, + } + } + #[doc = "Error did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Error::IntNo + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Error::IntYes + } +} +#[doc = "Field `ERROR` writer - Error Flag"] +pub type ErrorW<'a, REG> = crate::BitWriter1C<'a, REG, Error>; +impl<'a, REG> ErrorW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Error did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Error::IntNo) + } + #[doc = "Error occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Error::IntYes) + } +} +#[doc = "Start Of Frame (SOF) Token Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Softok { + #[doc = "0: Did not receive"] + IntNo = 0, + #[doc = "1: Received"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Softok) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOFTOK` reader - Start Of Frame (SOF) Token Flag"] +pub type SoftokR = crate::BitReader; +impl SoftokR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Softok { + match self.bits { + false => Softok::IntNo, + true => Softok::IntYes, + } + } + #[doc = "Did not receive"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Softok::IntNo + } + #[doc = "Received"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Softok::IntYes + } +} +#[doc = "Field `SOFTOK` writer - Start Of Frame (SOF) Token Flag"] +pub type SoftokW<'a, REG> = crate::BitWriter1C<'a, REG, Softok>; +impl<'a, REG> SoftokW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Did not receive"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Softok::IntNo) + } + #[doc = "Received"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Softok::IntYes) + } +} +#[doc = "Current Token Processing Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tokdne { + #[doc = "0: Not processed"] + IntNo = 0, + #[doc = "1: Processed"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tokdne) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TOKDNE` reader - Current Token Processing Flag"] +pub type TokdneR = crate::BitReader; +impl TokdneR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tokdne { + match self.bits { + false => Tokdne::IntNo, + true => Tokdne::IntYes, + } + } + #[doc = "Not processed"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Tokdne::IntNo + } + #[doc = "Processed"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Tokdne::IntYes + } +} +#[doc = "Field `TOKDNE` writer - Current Token Processing Flag"] +pub type TokdneW<'a, REG> = crate::BitWriter1C<'a, REG, Tokdne>; +impl<'a, REG> TokdneW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not processed"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Tokdne::IntNo) + } + #[doc = "Processed"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Tokdne::IntYes) + } +} +#[doc = "Sleep Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sleep { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sleep) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEP` reader - Sleep Flag"] +pub type SleepR = crate::BitReader; +impl SleepR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sleep { + match self.bits { + false => Sleep::IntNo, + true => Sleep::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Sleep::IntNo + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Sleep::IntYes + } +} +#[doc = "Field `SLEEP` writer - Sleep Flag"] +pub type SleepW<'a, REG> = crate::BitWriter1C<'a, REG, Sleep>; +impl<'a, REG> SleepW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Sleep::IntNo) + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Sleep::IntYes) + } +} +#[doc = "Resume Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Resume { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Resume) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESUME` reader - Resume Flag"] +pub type ResumeR = crate::BitReader; +impl ResumeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Resume { + match self.bits { + false => Resume::IntNo, + true => Resume::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Resume::IntNo + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Resume::IntYes + } +} +#[doc = "Field `RESUME` writer - Resume Flag"] +pub type ResumeW<'a, REG> = crate::BitWriter1C<'a, REG, Resume>; +impl<'a, REG> ResumeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Resume::IntNo) + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Resume::IntYes) + } +} +#[doc = "Attach Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Attach { + #[doc = "0: Not detected"] + IntNo = 0, + #[doc = "1: Detected"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Attach) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ATTACH` reader - Attach Interrupt Flag"] +pub type AttachR = crate::BitReader; +impl AttachR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Attach { + match self.bits { + false => Attach::IntNo, + true => Attach::IntYes, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Attach::IntNo + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Attach::IntYes + } +} +#[doc = "Field `ATTACH` writer - Attach Interrupt Flag"] +pub type AttachW<'a, REG> = crate::BitWriter1C<'a, REG, Attach>; +impl<'a, REG> AttachW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not detected"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Attach::IntNo) + } + #[doc = "Detected"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Attach::IntYes) + } +} +#[doc = "Stall Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Stall { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Stall) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL` reader - Stall Interrupt Flag"] +pub type StallR = crate::BitReader; +impl StallR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Stall { + match self.bits { + false => Stall::IntNo, + true => Stall::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Stall::IntNo + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Stall::IntYes + } +} +#[doc = "Field `STALL` writer - Stall Interrupt Flag"] +pub type StallW<'a, REG> = crate::BitWriter1C<'a, REG, Stall>; +impl<'a, REG> StallW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Stall::IntNo) + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Stall::IntYes) + } +} +impl R { + #[doc = "Bit 0 - USB Reset Flag"] + #[inline(always)] + pub fn usbrst(&self) -> UsbrstR { + UsbrstR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Error Flag"] + #[inline(always)] + pub fn error(&self) -> ErrorR { + ErrorR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Start Of Frame (SOF) Token Flag"] + #[inline(always)] + pub fn softok(&self) -> SoftokR { + SoftokR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Current Token Processing Flag"] + #[inline(always)] + pub fn tokdne(&self) -> TokdneR { + TokdneR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Sleep Flag"] + #[inline(always)] + pub fn sleep(&self) -> SleepR { + SleepR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Resume Flag"] + #[inline(always)] + pub fn resume(&self) -> ResumeR { + ResumeR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Attach Interrupt Flag"] + #[inline(always)] + pub fn attach(&self) -> AttachR { + AttachR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&self) -> StallR { + StallR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - USB Reset Flag"] + #[inline(always)] + pub fn usbrst(&mut self) -> UsbrstW { + UsbrstW::new(self, 0) + } + #[doc = "Bit 1 - Error Flag"] + #[inline(always)] + pub fn error(&mut self) -> ErrorW { + ErrorW::new(self, 1) + } + #[doc = "Bit 2 - Start Of Frame (SOF) Token Flag"] + #[inline(always)] + pub fn softok(&mut self) -> SoftokW { + SoftokW::new(self, 2) + } + #[doc = "Bit 3 - Current Token Processing Flag"] + #[inline(always)] + pub fn tokdne(&mut self) -> TokdneW { + TokdneW::new(self, 3) + } + #[doc = "Bit 4 - Sleep Flag"] + #[inline(always)] + pub fn sleep(&mut self) -> SleepW { + SleepW::new(self, 4) + } + #[doc = "Bit 5 - Resume Flag"] + #[inline(always)] + pub fn resume(&mut self) -> ResumeW { + ResumeW::new(self, 5) + } + #[doc = "Bit 6 - Attach Interrupt Flag"] + #[inline(always)] + pub fn attach(&mut self) -> AttachW { + AttachW::new(self, 6) + } + #[doc = "Bit 7 - Stall Interrupt Flag"] + #[inline(always)] + pub fn stall(&mut self) -> StallW { + StallW::new(self, 7) + } +} +#[doc = "Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`istat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`istat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IstatSpec; +impl crate::RegisterSpec for IstatSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`istat::R`](R) reader structure"] +impl crate::Readable for IstatSpec {} +#[doc = "`write(|w| ..)` method takes [`istat::W`](W) writer structure"] +impl crate::Writable for IstatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0xff; +} +#[doc = "`reset()` method sets ISTAT to value 0"] +impl crate::Resettable for IstatSpec {} diff --git a/mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs b/mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs new file mode 100644 index 000000000..121686c20 --- /dev/null +++ b/mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs @@ -0,0 +1,25 @@ +#[doc = "Register `KEEP_ALIVE_CTRL_RSVD` reader"] +pub type R = crate::R; +#[doc = "Register `KEEP_ALIVE_CTRL_RSVD` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_ctrl_rsvd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_ctrl_rsvd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KeepAliveCtrlRsvdSpec; +impl crate::RegisterSpec for KeepAliveCtrlRsvdSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`keep_alive_ctrl_rsvd::R`](R) reader structure"] +impl crate::Readable for KeepAliveCtrlRsvdSpec {} +#[doc = "`write(|w| ..)` method takes [`keep_alive_ctrl_rsvd::W`](W) writer structure"] +impl crate::Writable for KeepAliveCtrlRsvdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets KEEP_ALIVE_CTRL_RSVD to value 0x08"] +impl crate::Resettable for KeepAliveCtrlRsvdSpec { + const RESET_VALUE: u8 = 0x08; +} diff --git a/mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs b/mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs new file mode 100644 index 000000000..f7b3af7ae --- /dev/null +++ b/mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs @@ -0,0 +1,25 @@ +#[doc = "Register `KEEP_ALIVE_WKCTRL_RSVD` reader"] +pub type R = crate::R; +#[doc = "Register `KEEP_ALIVE_WKCTRL_RSVD` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_wkctrl_rsvd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_wkctrl_rsvd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KeepAliveWkctrlRsvdSpec; +impl crate::RegisterSpec for KeepAliveWkctrlRsvdSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`keep_alive_wkctrl_rsvd::R`](R) reader structure"] +impl crate::Readable for KeepAliveWkctrlRsvdSpec {} +#[doc = "`write(|w| ..)` method takes [`keep_alive_wkctrl_rsvd::W`](W) writer structure"] +impl crate::Writable for KeepAliveWkctrlRsvdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets KEEP_ALIVE_WKCTRL_RSVD to value 0x01"] +impl crate::Resettable for KeepAliveWkctrlRsvdSpec { + const RESET_VALUE: u8 = 0x01; +} diff --git a/mcxa276-pac/src/usb0/miscctrl.rs b/mcxa276-pac/src/usb0/miscctrl.rs new file mode 100644 index 000000000..f0d066a00 --- /dev/null +++ b/mcxa276-pac/src/usb0/miscctrl.rs @@ -0,0 +1,399 @@ +#[doc = "Register `MISCCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MISCCTRL` writer"] +pub type W = crate::W; +#[doc = "Dynamic SOF Threshold Compare mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sofdynthld { + #[doc = "0: When the byte-times SOF threshold is reached"] + UseDynSofThreshold = 0, + #[doc = "1: When 8 byte-times SOF threshold is reached or overstepped"] + UseFixedSofThreshold = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sofdynthld) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOFDYNTHLD` reader - Dynamic SOF Threshold Compare mode"] +pub type SofdynthldR = crate::BitReader; +impl SofdynthldR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sofdynthld { + match self.bits { + false => Sofdynthld::UseDynSofThreshold, + true => Sofdynthld::UseFixedSofThreshold, + } + } + #[doc = "When the byte-times SOF threshold is reached"] + #[inline(always)] + pub fn is_use_dyn_sof_threshold(&self) -> bool { + *self == Sofdynthld::UseDynSofThreshold + } + #[doc = "When 8 byte-times SOF threshold is reached or overstepped"] + #[inline(always)] + pub fn is_use_fixed_sof_threshold(&self) -> bool { + *self == Sofdynthld::UseFixedSofThreshold + } +} +#[doc = "Field `SOFDYNTHLD` writer - Dynamic SOF Threshold Compare mode"] +pub type SofdynthldW<'a, REG> = crate::BitWriter<'a, REG, Sofdynthld>; +impl<'a, REG> SofdynthldW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "When the byte-times SOF threshold is reached"] + #[inline(always)] + pub fn use_dyn_sof_threshold(self) -> &'a mut crate::W { + self.variant(Sofdynthld::UseDynSofThreshold) + } + #[doc = "When 8 byte-times SOF threshold is reached or overstepped"] + #[inline(always)] + pub fn use_fixed_sof_threshold(self) -> &'a mut crate::W { + self.variant(Sofdynthld::UseFixedSofThreshold) + } +} +#[doc = "SOF_TOK Interrupt Generation Mode Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sofbusset { + #[doc = "0: According to the SOF threshold value"] + SofTokIntFromThreshold = 0, + #[doc = "1: When the SOF counter reaches 0"] + SofTokIntCounter0 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sofbusset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SOFBUSSET` reader - SOF_TOK Interrupt Generation Mode Select"] +pub type SofbussetR = crate::BitReader; +impl SofbussetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sofbusset { + match self.bits { + false => Sofbusset::SofTokIntFromThreshold, + true => Sofbusset::SofTokIntCounter0, + } + } + #[doc = "According to the SOF threshold value"] + #[inline(always)] + pub fn is_sof_tok_int_from_threshold(&self) -> bool { + *self == Sofbusset::SofTokIntFromThreshold + } + #[doc = "When the SOF counter reaches 0"] + #[inline(always)] + pub fn is_sof_tok_int_counter_0(&self) -> bool { + *self == Sofbusset::SofTokIntCounter0 + } +} +#[doc = "Field `SOFBUSSET` writer - SOF_TOK Interrupt Generation Mode Select"] +pub type SofbussetW<'a, REG> = crate::BitWriter<'a, REG, Sofbusset>; +impl<'a, REG> SofbussetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "According to the SOF threshold value"] + #[inline(always)] + pub fn sof_tok_int_from_threshold(self) -> &'a mut crate::W { + self.variant(Sofbusset::SofTokIntFromThreshold) + } + #[doc = "When the SOF counter reaches 0"] + #[inline(always)] + pub fn sof_tok_int_counter_0(self) -> &'a mut crate::W { + self.variant(Sofbusset::SofTokIntCounter0) + } +} +#[doc = "OWN Error Detect for ISO IN and ISO OUT Disable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ownerrisodis { + #[doc = "0: Enable"] + DisOwnErrorDetectIso = 0, + #[doc = "1: Disable"] + EnOwnErrorDetectIso = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ownerrisodis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OWNERRISODIS` reader - OWN Error Detect for ISO IN and ISO OUT Disable"] +pub type OwnerrisodisR = crate::BitReader; +impl OwnerrisodisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ownerrisodis { + match self.bits { + false => Ownerrisodis::DisOwnErrorDetectIso, + true => Ownerrisodis::EnOwnErrorDetectIso, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_dis_own_error_detect_iso(&self) -> bool { + *self == Ownerrisodis::DisOwnErrorDetectIso + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_en_own_error_detect_iso(&self) -> bool { + *self == Ownerrisodis::EnOwnErrorDetectIso + } +} +#[doc = "Field `OWNERRISODIS` writer - OWN Error Detect for ISO IN and ISO OUT Disable"] +pub type OwnerrisodisW<'a, REG> = crate::BitWriter<'a, REG, Ownerrisodis>; +impl<'a, REG> OwnerrisodisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn dis_own_error_detect_iso(self) -> &'a mut crate::W { + self.variant(Ownerrisodis::DisOwnErrorDetectIso) + } + #[doc = "Disable"] + #[inline(always)] + pub fn en_own_error_detect_iso(self) -> &'a mut crate::W { + self.variant(Ownerrisodis::EnOwnErrorDetectIso) + } +} +#[doc = "VREGIN Rising Edge Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VredgEn { + #[doc = "0: Disable"] + DisVreginReInt = 0, + #[doc = "1: Enable"] + EnVreginReInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VredgEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VREDG_EN` reader - VREGIN Rising Edge Interrupt Enable"] +pub type VredgEnR = crate::BitReader; +impl VredgEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VredgEn { + match self.bits { + false => VredgEn::DisVreginReInt, + true => VredgEn::EnVreginReInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_vregin_re_int(&self) -> bool { + *self == VredgEn::DisVreginReInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_vregin_re_int(&self) -> bool { + *self == VredgEn::EnVreginReInt + } +} +#[doc = "Field `VREDG_EN` writer - VREGIN Rising Edge Interrupt Enable"] +pub type VredgEnW<'a, REG> = crate::BitWriter<'a, REG, VredgEn>; +impl<'a, REG> VredgEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_vregin_re_int(self) -> &'a mut crate::W { + self.variant(VredgEn::DisVreginReInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_vregin_re_int(self) -> &'a mut crate::W { + self.variant(VredgEn::EnVreginReInt) + } +} +#[doc = "VREGIN Falling Edge Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VfedgEn { + #[doc = "0: Disable"] + DisVreginFeInt = 0, + #[doc = "1: Enable"] + EnVreginFeInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VfedgEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VFEDG_EN` reader - VREGIN Falling Edge Interrupt Enable"] +pub type VfedgEnR = crate::BitReader; +impl VfedgEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VfedgEn { + match self.bits { + false => VfedgEn::DisVreginFeInt, + true => VfedgEn::EnVreginFeInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_vregin_fe_int(&self) -> bool { + *self == VfedgEn::DisVreginFeInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_vregin_fe_int(&self) -> bool { + *self == VfedgEn::EnVreginFeInt + } +} +#[doc = "Field `VFEDG_EN` writer - VREGIN Falling Edge Interrupt Enable"] +pub type VfedgEnW<'a, REG> = crate::BitWriter<'a, REG, VfedgEn>; +impl<'a, REG> VfedgEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_vregin_fe_int(self) -> &'a mut crate::W { + self.variant(VfedgEn::DisVreginFeInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_vregin_fe_int(self) -> &'a mut crate::W { + self.variant(VfedgEn::EnVreginFeInt) + } +} +#[doc = "USB Peripheral Mode Stall Adjust Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StlAdjEn { + #[doc = "0: If ENDPTn\\[END_STALL\\] = 1, both IN and OUT directions for the associated endpoint stalls."] + StallBothInOut = 0, + #[doc = "1: If ENDPTn\\[END_STALL\\] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls."] + StallSingleDirection = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StlAdjEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STL_ADJ_EN` reader - USB Peripheral Mode Stall Adjust Enable"] +pub type StlAdjEnR = crate::BitReader; +impl StlAdjEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StlAdjEn { + match self.bits { + false => StlAdjEn::StallBothInOut, + true => StlAdjEn::StallSingleDirection, + } + } + #[doc = "If ENDPTn\\[END_STALL\\] = 1, both IN and OUT directions for the associated endpoint stalls."] + #[inline(always)] + pub fn is_stall_both_in_out(&self) -> bool { + *self == StlAdjEn::StallBothInOut + } + #[doc = "If ENDPTn\\[END_STALL\\] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls."] + #[inline(always)] + pub fn is_stall_single_direction(&self) -> bool { + *self == StlAdjEn::StallSingleDirection + } +} +#[doc = "Field `STL_ADJ_EN` writer - USB Peripheral Mode Stall Adjust Enable"] +pub type StlAdjEnW<'a, REG> = crate::BitWriter<'a, REG, StlAdjEn>; +impl<'a, REG> StlAdjEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "If ENDPTn\\[END_STALL\\] = 1, both IN and OUT directions for the associated endpoint stalls."] + #[inline(always)] + pub fn stall_both_in_out(self) -> &'a mut crate::W { + self.variant(StlAdjEn::StallBothInOut) + } + #[doc = "If ENDPTn\\[END_STALL\\] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls."] + #[inline(always)] + pub fn stall_single_direction(self) -> &'a mut crate::W { + self.variant(StlAdjEn::StallSingleDirection) + } +} +impl R { + #[doc = "Bit 0 - Dynamic SOF Threshold Compare mode"] + #[inline(always)] + pub fn sofdynthld(&self) -> SofdynthldR { + SofdynthldR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SOF_TOK Interrupt Generation Mode Select"] + #[inline(always)] + pub fn sofbusset(&self) -> SofbussetR { + SofbussetR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - OWN Error Detect for ISO IN and ISO OUT Disable"] + #[inline(always)] + pub fn ownerrisodis(&self) -> OwnerrisodisR { + OwnerrisodisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VREGIN Rising Edge Interrupt Enable"] + #[inline(always)] + pub fn vredg_en(&self) -> VredgEnR { + VredgEnR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VREGIN Falling Edge Interrupt Enable"] + #[inline(always)] + pub fn vfedg_en(&self) -> VfedgEnR { + VfedgEnR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - USB Peripheral Mode Stall Adjust Enable"] + #[inline(always)] + pub fn stl_adj_en(&self) -> StlAdjEnR { + StlAdjEnR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Dynamic SOF Threshold Compare mode"] + #[inline(always)] + pub fn sofdynthld(&mut self) -> SofdynthldW { + SofdynthldW::new(self, 0) + } + #[doc = "Bit 1 - SOF_TOK Interrupt Generation Mode Select"] + #[inline(always)] + pub fn sofbusset(&mut self) -> SofbussetW { + SofbussetW::new(self, 1) + } + #[doc = "Bit 2 - OWN Error Detect for ISO IN and ISO OUT Disable"] + #[inline(always)] + pub fn ownerrisodis(&mut self) -> OwnerrisodisW { + OwnerrisodisW::new(self, 2) + } + #[doc = "Bit 3 - VREGIN Rising Edge Interrupt Enable"] + #[inline(always)] + pub fn vredg_en(&mut self) -> VredgEnW { + VredgEnW::new(self, 3) + } + #[doc = "Bit 4 - VREGIN Falling Edge Interrupt Enable"] + #[inline(always)] + pub fn vfedg_en(&mut self) -> VfedgEnW { + VfedgEnW::new(self, 4) + } + #[doc = "Bit 7 - USB Peripheral Mode Stall Adjust Enable"] + #[inline(always)] + pub fn stl_adj_en(&mut self) -> StlAdjEnW { + StlAdjEnW::new(self, 7) + } +} +#[doc = "Miscellaneous Control\n\nYou can [`read`](crate::Reg::read) this register and get [`miscctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`miscctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MiscctrlSpec; +impl crate::RegisterSpec for MiscctrlSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`miscctrl::R`](R) reader structure"] +impl crate::Readable for MiscctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`miscctrl::W`](W) writer structure"] +impl crate::Writable for MiscctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MISCCTRL to value 0"] +impl crate::Resettable for MiscctrlSpec {} diff --git a/mcxa276-pac/src/usb0/observe.rs b/mcxa276-pac/src/usb0/observe.rs new file mode 100644 index 000000000..9b4b8cdf1 --- /dev/null +++ b/mcxa276-pac/src/usb0/observe.rs @@ -0,0 +1,138 @@ +#[doc = "Register `OBSERVE` reader"] +pub type R = crate::R; +#[doc = "D- Pulldown\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmpd { + #[doc = "0: Disabled"] + DmPdDisStat = 0, + #[doc = "1: Enabled"] + DmPdEnStat = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmpd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMPD` reader - D- Pulldown"] +pub type DmpdR = crate::BitReader; +impl DmpdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmpd { + match self.bits { + false => Dmpd::DmPdDisStat, + true => Dmpd::DmPdEnStat, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_dm_pd_dis_stat(&self) -> bool { + *self == Dmpd::DmPdDisStat + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_dm_pd_en_stat(&self) -> bool { + *self == Dmpd::DmPdEnStat + } +} +#[doc = "D+ Pulldown\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dppd { + #[doc = "0: Disabled"] + DpPdDisStat = 0, + #[doc = "1: Enabled"] + DpPdEnStat = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dppd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPPD` reader - D+ Pulldown"] +pub type DppdR = crate::BitReader; +impl DppdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dppd { + match self.bits { + false => Dppd::DpPdDisStat, + true => Dppd::DpPdEnStat, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_dp_pd_dis_stat(&self) -> bool { + *self == Dppd::DpPdDisStat + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_dp_pd_en_stat(&self) -> bool { + *self == Dppd::DpPdEnStat + } +} +#[doc = "D+ Pullup\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dppu { + #[doc = "0: Disabled"] + DpPuDisStat = 0, + #[doc = "1: Enabled"] + DpPuEnStat = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dppu) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPPU` reader - D+ Pullup"] +pub type DppuR = crate::BitReader; +impl DppuR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dppu { + match self.bits { + false => Dppu::DpPuDisStat, + true => Dppu::DpPuEnStat, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_dp_pu_dis_stat(&self) -> bool { + *self == Dppu::DpPuDisStat + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_dp_pu_en_stat(&self) -> bool { + *self == Dppu::DpPuEnStat + } +} +impl R { + #[doc = "Bit 4 - D- Pulldown"] + #[inline(always)] + pub fn dmpd(&self) -> DmpdR { + DmpdR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - D+ Pulldown"] + #[inline(always)] + pub fn dppd(&self) -> DppdR { + DppdR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - D+ Pullup"] + #[inline(always)] + pub fn dppu(&self) -> DppuR { + DppuR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "USB OTG Observe\n\nYou can [`read`](crate::Reg::read) this register and get [`observe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ObserveSpec; +impl crate::RegisterSpec for ObserveSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`observe::R`](R) reader structure"] +impl crate::Readable for ObserveSpec {} +#[doc = "`reset()` method sets OBSERVE to value 0x50"] +impl crate::Resettable for ObserveSpec { + const RESET_VALUE: u8 = 0x50; +} diff --git a/mcxa276-pac/src/usb0/otgctl.rs b/mcxa276-pac/src/usb0/otgctl.rs new file mode 100644 index 000000000..ae11f0b9a --- /dev/null +++ b/mcxa276-pac/src/usb0/otgctl.rs @@ -0,0 +1,273 @@ +#[doc = "Register `OTGCTL` reader"] +pub type R = crate::R; +#[doc = "Register `OTGCTL` writer"] +pub type W = crate::W; +#[doc = "On-The-Go Pullup and Pulldown Resistor Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Otgen { + #[doc = "0: If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."] + ConfigResistorsCtl = 0, + #[doc = "1: Uses the pullup and pulldown controls in this register."] + ConfigResistorsHere = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Otgen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OTGEN` reader - On-The-Go Pullup and Pulldown Resistor Enable"] +pub type OtgenR = crate::BitReader; +impl OtgenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Otgen { + match self.bits { + false => Otgen::ConfigResistorsCtl, + true => Otgen::ConfigResistorsHere, + } + } + #[doc = "If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."] + #[inline(always)] + pub fn is_config_resistors_ctl(&self) -> bool { + *self == Otgen::ConfigResistorsCtl + } + #[doc = "Uses the pullup and pulldown controls in this register."] + #[inline(always)] + pub fn is_config_resistors_here(&self) -> bool { + *self == Otgen::ConfigResistorsHere + } +} +#[doc = "Field `OTGEN` writer - On-The-Go Pullup and Pulldown Resistor Enable"] +pub type OtgenW<'a, REG> = crate::BitWriter<'a, REG, Otgen>; +impl<'a, REG> OtgenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."] + #[inline(always)] + pub fn config_resistors_ctl(self) -> &'a mut crate::W { + self.variant(Otgen::ConfigResistorsCtl) + } + #[doc = "Uses the pullup and pulldown controls in this register."] + #[inline(always)] + pub fn config_resistors_here(self) -> &'a mut crate::W { + self.variant(Otgen::ConfigResistorsHere) + } +} +#[doc = "D- Data Line Pulldown Resistor Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dmlow { + #[doc = "0: Disable"] + DisDmPulldown = 0, + #[doc = "1: Enable"] + EnDmPulldown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dmlow) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DMLOW` reader - D- Data Line Pulldown Resistor Enable"] +pub type DmlowR = crate::BitReader; +impl DmlowR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dmlow { + match self.bits { + false => Dmlow::DisDmPulldown, + true => Dmlow::EnDmPulldown, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_dm_pulldown(&self) -> bool { + *self == Dmlow::DisDmPulldown + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_dm_pulldown(&self) -> bool { + *self == Dmlow::EnDmPulldown + } +} +#[doc = "Field `DMLOW` writer - D- Data Line Pulldown Resistor Enable"] +pub type DmlowW<'a, REG> = crate::BitWriter<'a, REG, Dmlow>; +impl<'a, REG> DmlowW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_dm_pulldown(self) -> &'a mut crate::W { + self.variant(Dmlow::DisDmPulldown) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_dm_pulldown(self) -> &'a mut crate::W { + self.variant(Dmlow::EnDmPulldown) + } +} +#[doc = "D+ Data Line pulldown Resistor Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dplow { + #[doc = "0: Disable"] + DisDpPulldown = 0, + #[doc = "1: Enable"] + EnDpPulldown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dplow) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPLOW` reader - D+ Data Line pulldown Resistor Enable"] +pub type DplowR = crate::BitReader; +impl DplowR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dplow { + match self.bits { + false => Dplow::DisDpPulldown, + true => Dplow::EnDpPulldown, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_dp_pulldown(&self) -> bool { + *self == Dplow::DisDpPulldown + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_dp_pulldown(&self) -> bool { + *self == Dplow::EnDpPulldown + } +} +#[doc = "Field `DPLOW` writer - D+ Data Line pulldown Resistor Enable"] +pub type DplowW<'a, REG> = crate::BitWriter<'a, REG, Dplow>; +impl<'a, REG> DplowW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_dp_pulldown(self) -> &'a mut crate::W { + self.variant(Dplow::DisDpPulldown) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_dp_pulldown(self) -> &'a mut crate::W { + self.variant(Dplow::EnDpPulldown) + } +} +#[doc = "D+ Data Line Pullup Resistor Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dphigh { + #[doc = "0: Disable"] + DisDpPullup = 0, + #[doc = "1: Enable"] + EnDpPullup = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dphigh) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPHIGH` reader - D+ Data Line Pullup Resistor Enable"] +pub type DphighR = crate::BitReader; +impl DphighR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dphigh { + match self.bits { + false => Dphigh::DisDpPullup, + true => Dphigh::EnDpPullup, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_dp_pullup(&self) -> bool { + *self == Dphigh::DisDpPullup + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_dp_pullup(&self) -> bool { + *self == Dphigh::EnDpPullup + } +} +#[doc = "Field `DPHIGH` writer - D+ Data Line Pullup Resistor Enable"] +pub type DphighW<'a, REG> = crate::BitWriter<'a, REG, Dphigh>; +impl<'a, REG> DphighW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_dp_pullup(self) -> &'a mut crate::W { + self.variant(Dphigh::DisDpPullup) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_dp_pullup(self) -> &'a mut crate::W { + self.variant(Dphigh::EnDpPullup) + } +} +impl R { + #[doc = "Bit 2 - On-The-Go Pullup and Pulldown Resistor Enable"] + #[inline(always)] + pub fn otgen(&self) -> OtgenR { + OtgenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - D- Data Line Pulldown Resistor Enable"] + #[inline(always)] + pub fn dmlow(&self) -> DmlowR { + DmlowR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - D+ Data Line pulldown Resistor Enable"] + #[inline(always)] + pub fn dplow(&self) -> DplowR { + DplowR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - D+ Data Line Pullup Resistor Enable"] + #[inline(always)] + pub fn dphigh(&self) -> DphighR { + DphighR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - On-The-Go Pullup and Pulldown Resistor Enable"] + #[inline(always)] + pub fn otgen(&mut self) -> OtgenW { + OtgenW::new(self, 2) + } + #[doc = "Bit 4 - D- Data Line Pulldown Resistor Enable"] + #[inline(always)] + pub fn dmlow(&mut self) -> DmlowW { + DmlowW::new(self, 4) + } + #[doc = "Bit 5 - D+ Data Line pulldown Resistor Enable"] + #[inline(always)] + pub fn dplow(&mut self) -> DplowW { + DplowW::new(self, 5) + } + #[doc = "Bit 7 - D+ Data Line Pullup Resistor Enable"] + #[inline(always)] + pub fn dphigh(&mut self) -> DphighW { + DphighW::new(self, 7) + } +} +#[doc = "OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OtgctlSpec; +impl crate::RegisterSpec for OtgctlSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`otgctl::R`](R) reader structure"] +impl crate::Readable for OtgctlSpec {} +#[doc = "`write(|w| ..)` method takes [`otgctl::W`](W) writer structure"] +impl crate::Writable for OtgctlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets OTGCTL to value 0"] +impl crate::Resettable for OtgctlSpec {} diff --git a/mcxa276-pac/src/usb0/otgicr.rs b/mcxa276-pac/src/usb0/otgicr.rs new file mode 100644 index 000000000..cb5202e68 --- /dev/null +++ b/mcxa276-pac/src/usb0/otgicr.rs @@ -0,0 +1,147 @@ +#[doc = "Register `OTGICR` reader"] +pub type R = crate::R; +#[doc = "Register `OTGICR` writer"] +pub type W = crate::W; +#[doc = "Line State Change Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Linestateen { + #[doc = "0: Disable"] + DisLinestInt = 0, + #[doc = "1: Enable"] + EnLinestInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Linestateen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LINESTATEEN` reader - Line State Change Interrupt Enable"] +pub type LinestateenR = crate::BitReader; +impl LinestateenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Linestateen { + match self.bits { + false => Linestateen::DisLinestInt, + true => Linestateen::EnLinestInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_linest_int(&self) -> bool { + *self == Linestateen::DisLinestInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_linest_int(&self) -> bool { + *self == Linestateen::EnLinestInt + } +} +#[doc = "Field `LINESTATEEN` writer - Line State Change Interrupt Enable"] +pub type LinestateenW<'a, REG> = crate::BitWriter<'a, REG, Linestateen>; +impl<'a, REG> LinestateenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_linest_int(self) -> &'a mut crate::W { + self.variant(Linestateen::DisLinestInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_linest_int(self) -> &'a mut crate::W { + self.variant(Linestateen::EnLinestInt) + } +} +#[doc = "1-Millisecond Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Onemsecen { + #[doc = "0: Disable"] + DisTimerInt = 0, + #[doc = "1: Enable"] + EnTimerInt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Onemsecen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONEMSECEN` reader - 1-Millisecond Interrupt Enable"] +pub type OnemsecenR = crate::BitReader; +impl OnemsecenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Onemsecen { + match self.bits { + false => Onemsecen::DisTimerInt, + true => Onemsecen::EnTimerInt, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_timer_int(&self) -> bool { + *self == Onemsecen::DisTimerInt + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_timer_int(&self) -> bool { + *self == Onemsecen::EnTimerInt + } +} +#[doc = "Field `ONEMSECEN` writer - 1-Millisecond Interrupt Enable"] +pub type OnemsecenW<'a, REG> = crate::BitWriter<'a, REG, Onemsecen>; +impl<'a, REG> OnemsecenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_timer_int(self) -> &'a mut crate::W { + self.variant(Onemsecen::DisTimerInt) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_timer_int(self) -> &'a mut crate::W { + self.variant(Onemsecen::EnTimerInt) + } +} +impl R { + #[doc = "Bit 5 - Line State Change Interrupt Enable"] + #[inline(always)] + pub fn linestateen(&self) -> LinestateenR { + LinestateenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1-Millisecond Interrupt Enable"] + #[inline(always)] + pub fn onemsecen(&self) -> OnemsecenR { + OnemsecenR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 5 - Line State Change Interrupt Enable"] + #[inline(always)] + pub fn linestateen(&mut self) -> LinestateenW { + LinestateenW::new(self, 5) + } + #[doc = "Bit 6 - 1-Millisecond Interrupt Enable"] + #[inline(always)] + pub fn onemsecen(&mut self) -> OnemsecenW { + OnemsecenW::new(self, 6) + } +} +#[doc = "OTG Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OtgicrSpec; +impl crate::RegisterSpec for OtgicrSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`otgicr::R`](R) reader structure"] +impl crate::Readable for OtgicrSpec {} +#[doc = "`write(|w| ..)` method takes [`otgicr::W`](W) writer structure"] +impl crate::Writable for OtgicrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets OTGICR to value 0"] +impl crate::Resettable for OtgicrSpec {} diff --git a/mcxa276-pac/src/usb0/otgistat.rs b/mcxa276-pac/src/usb0/otgistat.rs new file mode 100644 index 000000000..cda3b24a3 --- /dev/null +++ b/mcxa276-pac/src/usb0/otgistat.rs @@ -0,0 +1,148 @@ +#[doc = "Register `OTGISTAT` reader"] +pub type R = crate::R; +#[doc = "Register `OTGISTAT` writer"] +pub type W = crate::W; +#[doc = "Line State Change Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LineStateChg { + #[doc = "0: Interrupt did not occur"] + IntNo = 0, + #[doc = "1: Interrupt occurred"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: LineStateChg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LINE_STATE_CHG` reader - Line State Change Interrupt Flag"] +pub type LineStateChgR = crate::BitReader; +impl LineStateChgR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LineStateChg { + match self.bits { + false => LineStateChg::IntNo, + true => LineStateChg::IntYes, + } + } + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == LineStateChg::IntNo + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == LineStateChg::IntYes + } +} +#[doc = "Field `LINE_STATE_CHG` writer - Line State Change Interrupt Flag"] +pub type LineStateChgW<'a, REG> = crate::BitWriter1C<'a, REG, LineStateChg>; +impl<'a, REG> LineStateChgW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt did not occur"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(LineStateChg::IntNo) + } + #[doc = "Interrupt occurred"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(LineStateChg::IntYes) + } +} +#[doc = "One Millisecond Timer Timeout Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Onemsec { + #[doc = "0: Not timed out"] + IntNo = 0, + #[doc = "1: Timed out"] + IntYes = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Onemsec) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ONEMSEC` reader - One Millisecond Timer Timeout Flag"] +pub type OnemsecR = crate::BitReader; +impl OnemsecR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Onemsec { + match self.bits { + false => Onemsec::IntNo, + true => Onemsec::IntYes, + } + } + #[doc = "Not timed out"] + #[inline(always)] + pub fn is_int_no(&self) -> bool { + *self == Onemsec::IntNo + } + #[doc = "Timed out"] + #[inline(always)] + pub fn is_int_yes(&self) -> bool { + *self == Onemsec::IntYes + } +} +#[doc = "Field `ONEMSEC` writer - One Millisecond Timer Timeout Flag"] +pub type OnemsecW<'a, REG> = crate::BitWriter1C<'a, REG, Onemsec>; +impl<'a, REG> OnemsecW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not timed out"] + #[inline(always)] + pub fn int_no(self) -> &'a mut crate::W { + self.variant(Onemsec::IntNo) + } + #[doc = "Timed out"] + #[inline(always)] + pub fn int_yes(self) -> &'a mut crate::W { + self.variant(Onemsec::IntYes) + } +} +impl R { + #[doc = "Bit 5 - Line State Change Interrupt Flag"] + #[inline(always)] + pub fn line_state_chg(&self) -> LineStateChgR { + LineStateChgR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - One Millisecond Timer Timeout Flag"] + #[inline(always)] + pub fn onemsec(&self) -> OnemsecR { + OnemsecR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 5 - Line State Change Interrupt Flag"] + #[inline(always)] + pub fn line_state_chg(&mut self) -> LineStateChgW { + LineStateChgW::new(self, 5) + } + #[doc = "Bit 6 - One Millisecond Timer Timeout Flag"] + #[inline(always)] + pub fn onemsec(&mut self) -> OnemsecW { + OnemsecW::new(self, 6) + } +} +#[doc = "OTG Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgistat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgistat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OtgistatSpec; +impl crate::RegisterSpec for OtgistatSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`otgistat::R`](R) reader structure"] +impl crate::Readable for OtgistatSpec {} +#[doc = "`write(|w| ..)` method takes [`otgistat::W`](W) writer structure"] +impl crate::Writable for OtgistatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0x60; +} +#[doc = "`reset()` method sets OTGISTAT to value 0"] +impl crate::Resettable for OtgistatSpec {} diff --git a/mcxa276-pac/src/usb0/otgstat.rs b/mcxa276-pac/src/usb0/otgstat.rs new file mode 100644 index 000000000..158c1f525 --- /dev/null +++ b/mcxa276-pac/src/usb0/otgstat.rs @@ -0,0 +1,61 @@ +#[doc = "Register `OTGSTAT` reader"] +pub type R = crate::R; +#[doc = "Line State Stable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Linestatestable { + #[doc = "0: Unstable"] + LinestNotStable = 0, + #[doc = "1: Stable"] + LinestStable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Linestatestable) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LINESTATESTABLE` reader - Line State Stable"] +pub type LinestatestableR = crate::BitReader; +impl LinestatestableR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Linestatestable { + match self.bits { + false => Linestatestable::LinestNotStable, + true => Linestatestable::LinestStable, + } + } + #[doc = "Unstable"] + #[inline(always)] + pub fn is_linest_not_stable(&self) -> bool { + *self == Linestatestable::LinestNotStable + } + #[doc = "Stable"] + #[inline(always)] + pub fn is_linest_stable(&self) -> bool { + *self == Linestatestable::LinestStable + } +} +#[doc = "Field `ONEMSEC` reader - Reserved for 1 ms count"] +pub type OnemsecR = crate::BitReader; +impl R { + #[doc = "Bit 5 - Line State Stable"] + #[inline(always)] + pub fn linestatestable(&self) -> LinestatestableR { + LinestatestableR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved for 1 ms count"] + #[inline(always)] + pub fn onemsec(&self) -> OnemsecR { + OnemsecR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "OTG Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OtgstatSpec; +impl crate::RegisterSpec for OtgstatSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`otgstat::R`](R) reader structure"] +impl crate::Readable for OtgstatSpec {} +#[doc = "`reset()` method sets OTGSTAT to value 0"] +impl crate::Resettable for OtgstatSpec {} diff --git a/mcxa276-pac/src/usb0/perid.rs b/mcxa276-pac/src/usb0/perid.rs new file mode 100644 index 000000000..362f19328 --- /dev/null +++ b/mcxa276-pac/src/usb0/perid.rs @@ -0,0 +1,22 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[doc = "Field `ID` reader - Peripheral Identification"] +pub type IdR = crate::FieldReader; +impl R { + #[doc = "Bits 0:5 - Peripheral Identification"] + #[inline(always)] + pub fn id(&self) -> IdR { + IdR::new(self.bits & 0x3f) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x04"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u8 = 0x04; +} diff --git a/mcxa276-pac/src/usb0/rev.rs b/mcxa276-pac/src/usb0/rev.rs new file mode 100644 index 000000000..50e00f689 --- /dev/null +++ b/mcxa276-pac/src/usb0/rev.rs @@ -0,0 +1,22 @@ +#[doc = "Register `REV` reader"] +pub type R = crate::R; +#[doc = "Field `REV` reader - Revision"] +pub type RevR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Revision"] + #[inline(always)] + pub fn rev(&self) -> RevR { + RevR::new(self.bits) + } +} +#[doc = "Peripheral Revision\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RevSpec; +impl crate::RegisterSpec for RevSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`rev::R`](R) reader structure"] +impl crate::Readable for RevSpec {} +#[doc = "`reset()` method sets REV to value 0x33"] +impl crate::Resettable for RevSpec { + const RESET_VALUE: u8 = 0x33; +} diff --git a/mcxa276-pac/src/usb0/softhld.rs b/mcxa276-pac/src/usb0/softhld.rs new file mode 100644 index 000000000..1e873f12e --- /dev/null +++ b/mcxa276-pac/src/usb0/softhld.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SOFTHLD` reader"] +pub type R = crate::R; +#[doc = "Register `SOFTHLD` writer"] +pub type W = crate::W; +#[doc = "Field `CNT` reader - SOF Count Threshold"] +pub type CntR = crate::FieldReader; +#[doc = "Field `CNT` writer - SOF Count Threshold"] +pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - SOF Count Threshold"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - SOF Count Threshold"] + #[inline(always)] + pub fn cnt(&mut self) -> CntW { + CntW::new(self, 0) + } +} +#[doc = "SOF Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`softhld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`softhld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SofthldSpec; +impl crate::RegisterSpec for SofthldSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`softhld::R`](R) reader structure"] +impl crate::Readable for SofthldSpec {} +#[doc = "`write(|w| ..)` method takes [`softhld::W`](W) writer structure"] +impl crate::Writable for SofthldSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SOFTHLD to value 0"] +impl crate::Resettable for SofthldSpec {} diff --git a/mcxa276-pac/src/usb0/stall_ih_dis.rs b/mcxa276-pac/src/usb0/stall_ih_dis.rs new file mode 100644 index 000000000..ed9b19c10 --- /dev/null +++ b/mcxa276-pac/src/usb0/stall_ih_dis.rs @@ -0,0 +1,525 @@ +#[doc = "Register `STALL_IH_DIS` reader"] +pub type R = crate::R; +#[doc = "Register `STALL_IH_DIS` writer"] +pub type W = crate::W; +#[doc = "Disable Endpoint 8 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis8 { + #[doc = "0: Enable"] + EnEp8InStall = 0, + #[doc = "1: Disable"] + DisEp8InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS8` reader - Disable Endpoint 8 IN Direction"] +pub type StallIDis8R = crate::BitReader; +impl StallIDis8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis8 { + match self.bits { + false => StallIDis8::EnEp8InStall, + true => StallIDis8::DisEp8InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep8_in_stall(&self) -> bool { + *self == StallIDis8::EnEp8InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep8_in_stall(&self) -> bool { + *self == StallIDis8::DisEp8InStall + } +} +#[doc = "Field `STALL_I_DIS8` writer - Disable Endpoint 8 IN Direction"] +pub type StallIDis8W<'a, REG> = crate::BitWriter<'a, REG, StallIDis8>; +impl<'a, REG> StallIDis8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep8_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis8::EnEp8InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep8_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis8::DisEp8InStall) + } +} +#[doc = "Disable Endpoint 9 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis9 { + #[doc = "0: Enable"] + EnEp9InStall = 0, + #[doc = "1: Disable"] + DisEp9InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS9` reader - Disable Endpoint 9 IN Direction"] +pub type StallIDis9R = crate::BitReader; +impl StallIDis9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis9 { + match self.bits { + false => StallIDis9::EnEp9InStall, + true => StallIDis9::DisEp9InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep9_in_stall(&self) -> bool { + *self == StallIDis9::EnEp9InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep9_in_stall(&self) -> bool { + *self == StallIDis9::DisEp9InStall + } +} +#[doc = "Field `STALL_I_DIS9` writer - Disable Endpoint 9 IN Direction"] +pub type StallIDis9W<'a, REG> = crate::BitWriter<'a, REG, StallIDis9>; +impl<'a, REG> StallIDis9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep9_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis9::EnEp9InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep9_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis9::DisEp9InStall) + } +} +#[doc = "Disable Endpoint 10 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis10 { + #[doc = "0: Enable"] + EnEp10InStall = 0, + #[doc = "1: Disable"] + DisEp10InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS10` reader - Disable Endpoint 10 IN Direction"] +pub type StallIDis10R = crate::BitReader; +impl StallIDis10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis10 { + match self.bits { + false => StallIDis10::EnEp10InStall, + true => StallIDis10::DisEp10InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep10_in_stall(&self) -> bool { + *self == StallIDis10::EnEp10InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep10_in_stall(&self) -> bool { + *self == StallIDis10::DisEp10InStall + } +} +#[doc = "Field `STALL_I_DIS10` writer - Disable Endpoint 10 IN Direction"] +pub type StallIDis10W<'a, REG> = crate::BitWriter<'a, REG, StallIDis10>; +impl<'a, REG> StallIDis10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep10_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis10::EnEp10InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep10_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis10::DisEp10InStall) + } +} +#[doc = "Disable Endpoint 11 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis11 { + #[doc = "0: Enable"] + EnEp11InStall = 0, + #[doc = "1: Disable"] + DisEp11InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS11` reader - Disable Endpoint 11 IN Direction"] +pub type StallIDis11R = crate::BitReader; +impl StallIDis11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis11 { + match self.bits { + false => StallIDis11::EnEp11InStall, + true => StallIDis11::DisEp11InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep11_in_stall(&self) -> bool { + *self == StallIDis11::EnEp11InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep11_in_stall(&self) -> bool { + *self == StallIDis11::DisEp11InStall + } +} +#[doc = "Field `STALL_I_DIS11` writer - Disable Endpoint 11 IN Direction"] +pub type StallIDis11W<'a, REG> = crate::BitWriter<'a, REG, StallIDis11>; +impl<'a, REG> StallIDis11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep11_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis11::EnEp11InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep11_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis11::DisEp11InStall) + } +} +#[doc = "Disable Endpoint 12 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis12 { + #[doc = "0: Enable"] + EnEp12InStall = 0, + #[doc = "1: Disable"] + DisEp12InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS12` reader - Disable Endpoint 12 IN Direction"] +pub type StallIDis12R = crate::BitReader; +impl StallIDis12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis12 { + match self.bits { + false => StallIDis12::EnEp12InStall, + true => StallIDis12::DisEp12InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep12_in_stall(&self) -> bool { + *self == StallIDis12::EnEp12InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep12_in_stall(&self) -> bool { + *self == StallIDis12::DisEp12InStall + } +} +#[doc = "Field `STALL_I_DIS12` writer - Disable Endpoint 12 IN Direction"] +pub type StallIDis12W<'a, REG> = crate::BitWriter<'a, REG, StallIDis12>; +impl<'a, REG> StallIDis12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep12_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis12::EnEp12InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep12_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis12::DisEp12InStall) + } +} +#[doc = "Disable Endpoint 13 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis13 { + #[doc = "0: Enable"] + EnEp13InStall = 0, + #[doc = "1: Disable"] + DisEp13InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS13` reader - Disable Endpoint 13 IN Direction"] +pub type StallIDis13R = crate::BitReader; +impl StallIDis13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis13 { + match self.bits { + false => StallIDis13::EnEp13InStall, + true => StallIDis13::DisEp13InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep13_in_stall(&self) -> bool { + *self == StallIDis13::EnEp13InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep13_in_stall(&self) -> bool { + *self == StallIDis13::DisEp13InStall + } +} +#[doc = "Field `STALL_I_DIS13` writer - Disable Endpoint 13 IN Direction"] +pub type StallIDis13W<'a, REG> = crate::BitWriter<'a, REG, StallIDis13>; +impl<'a, REG> StallIDis13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep13_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis13::EnEp13InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep13_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis13::DisEp13InStall) + } +} +#[doc = "Disable Endpoint 14 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis14 { + #[doc = "0: Enable"] + EnEp14InStall = 0, + #[doc = "1: Disable"] + DisEp14InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS14` reader - Disable Endpoint 14 IN Direction"] +pub type StallIDis14R = crate::BitReader; +impl StallIDis14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis14 { + match self.bits { + false => StallIDis14::EnEp14InStall, + true => StallIDis14::DisEp14InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep14_in_stall(&self) -> bool { + *self == StallIDis14::EnEp14InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep14_in_stall(&self) -> bool { + *self == StallIDis14::DisEp14InStall + } +} +#[doc = "Field `STALL_I_DIS14` writer - Disable Endpoint 14 IN Direction"] +pub type StallIDis14W<'a, REG> = crate::BitWriter<'a, REG, StallIDis14>; +impl<'a, REG> StallIDis14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep14_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis14::EnEp14InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep14_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis14::DisEp14InStall) + } +} +#[doc = "Disable Endpoint 15 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis15 { + #[doc = "0: Enable"] + EnEp15InStall = 0, + #[doc = "1: Disable"] + DisEp15InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS15` reader - Disable Endpoint 15 IN Direction"] +pub type StallIDis15R = crate::BitReader; +impl StallIDis15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis15 { + match self.bits { + false => StallIDis15::EnEp15InStall, + true => StallIDis15::DisEp15InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep15_in_stall(&self) -> bool { + *self == StallIDis15::EnEp15InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep15_in_stall(&self) -> bool { + *self == StallIDis15::DisEp15InStall + } +} +#[doc = "Field `STALL_I_DIS15` writer - Disable Endpoint 15 IN Direction"] +pub type StallIDis15W<'a, REG> = crate::BitWriter<'a, REG, StallIDis15>; +impl<'a, REG> StallIDis15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep15_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis15::EnEp15InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep15_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis15::DisEp15InStall) + } +} +impl R { + #[doc = "Bit 0 - Disable Endpoint 8 IN Direction"] + #[inline(always)] + pub fn stall_i_dis8(&self) -> StallIDis8R { + StallIDis8R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Disable Endpoint 9 IN Direction"] + #[inline(always)] + pub fn stall_i_dis9(&self) -> StallIDis9R { + StallIDis9R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Disable Endpoint 10 IN Direction"] + #[inline(always)] + pub fn stall_i_dis10(&self) -> StallIDis10R { + StallIDis10R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Disable Endpoint 11 IN Direction"] + #[inline(always)] + pub fn stall_i_dis11(&self) -> StallIDis11R { + StallIDis11R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Disable Endpoint 12 IN Direction"] + #[inline(always)] + pub fn stall_i_dis12(&self) -> StallIDis12R { + StallIDis12R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Disable Endpoint 13 IN Direction"] + #[inline(always)] + pub fn stall_i_dis13(&self) -> StallIDis13R { + StallIDis13R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Disable Endpoint 14 IN Direction"] + #[inline(always)] + pub fn stall_i_dis14(&self) -> StallIDis14R { + StallIDis14R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Disable Endpoint 15 IN Direction"] + #[inline(always)] + pub fn stall_i_dis15(&self) -> StallIDis15R { + StallIDis15R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disable Endpoint 8 IN Direction"] + #[inline(always)] + pub fn stall_i_dis8(&mut self) -> StallIDis8W { + StallIDis8W::new(self, 0) + } + #[doc = "Bit 1 - Disable Endpoint 9 IN Direction"] + #[inline(always)] + pub fn stall_i_dis9(&mut self) -> StallIDis9W { + StallIDis9W::new(self, 1) + } + #[doc = "Bit 2 - Disable Endpoint 10 IN Direction"] + #[inline(always)] + pub fn stall_i_dis10(&mut self) -> StallIDis10W { + StallIDis10W::new(self, 2) + } + #[doc = "Bit 3 - Disable Endpoint 11 IN Direction"] + #[inline(always)] + pub fn stall_i_dis11(&mut self) -> StallIDis11W { + StallIDis11W::new(self, 3) + } + #[doc = "Bit 4 - Disable Endpoint 12 IN Direction"] + #[inline(always)] + pub fn stall_i_dis12(&mut self) -> StallIDis12W { + StallIDis12W::new(self, 4) + } + #[doc = "Bit 5 - Disable Endpoint 13 IN Direction"] + #[inline(always)] + pub fn stall_i_dis13(&mut self) -> StallIDis13W { + StallIDis13W::new(self, 5) + } + #[doc = "Bit 6 - Disable Endpoint 14 IN Direction"] + #[inline(always)] + pub fn stall_i_dis14(&mut self) -> StallIDis14W { + StallIDis14W::new(self, 6) + } + #[doc = "Bit 7 - Disable Endpoint 15 IN Direction"] + #[inline(always)] + pub fn stall_i_dis15(&mut self) -> StallIDis15W { + StallIDis15W::new(self, 7) + } +} +#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ih_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ih_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StallIhDisSpec; +impl crate::RegisterSpec for StallIhDisSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`stall_ih_dis::R`](R) reader structure"] +impl crate::Readable for StallIhDisSpec {} +#[doc = "`write(|w| ..)` method takes [`stall_ih_dis::W`](W) writer structure"] +impl crate::Writable for StallIhDisSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STALL_IH_DIS to value 0"] +impl crate::Resettable for StallIhDisSpec {} diff --git a/mcxa276-pac/src/usb0/stall_il_dis.rs b/mcxa276-pac/src/usb0/stall_il_dis.rs new file mode 100644 index 000000000..fe0b28c94 --- /dev/null +++ b/mcxa276-pac/src/usb0/stall_il_dis.rs @@ -0,0 +1,525 @@ +#[doc = "Register `STALL_IL_DIS` reader"] +pub type R = crate::R; +#[doc = "Register `STALL_IL_DIS` writer"] +pub type W = crate::W; +#[doc = "Disable Endpoint 0 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis0 { + #[doc = "0: Enable"] + EnEp0InStall = 0, + #[doc = "1: Disable"] + DisEp0InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS0` reader - Disable Endpoint 0 IN Direction"] +pub type StallIDis0R = crate::BitReader; +impl StallIDis0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis0 { + match self.bits { + false => StallIDis0::EnEp0InStall, + true => StallIDis0::DisEp0InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep0_in_stall(&self) -> bool { + *self == StallIDis0::EnEp0InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep0_in_stall(&self) -> bool { + *self == StallIDis0::DisEp0InStall + } +} +#[doc = "Field `STALL_I_DIS0` writer - Disable Endpoint 0 IN Direction"] +pub type StallIDis0W<'a, REG> = crate::BitWriter<'a, REG, StallIDis0>; +impl<'a, REG> StallIDis0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep0_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis0::EnEp0InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep0_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis0::DisEp0InStall) + } +} +#[doc = "Disable Endpoint 1 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis1 { + #[doc = "0: Enable"] + EnEp1InStall = 0, + #[doc = "1: Disable"] + DisEp1InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS1` reader - Disable Endpoint 1 IN Direction"] +pub type StallIDis1R = crate::BitReader; +impl StallIDis1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis1 { + match self.bits { + false => StallIDis1::EnEp1InStall, + true => StallIDis1::DisEp1InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep1_in_stall(&self) -> bool { + *self == StallIDis1::EnEp1InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep1_in_stall(&self) -> bool { + *self == StallIDis1::DisEp1InStall + } +} +#[doc = "Field `STALL_I_DIS1` writer - Disable Endpoint 1 IN Direction"] +pub type StallIDis1W<'a, REG> = crate::BitWriter<'a, REG, StallIDis1>; +impl<'a, REG> StallIDis1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep1_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis1::EnEp1InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep1_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis1::DisEp1InStall) + } +} +#[doc = "Disable Endpoint 2 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis2 { + #[doc = "0: Enable"] + EnEp2InStall = 0, + #[doc = "1: Disable"] + DisEp2InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS2` reader - Disable Endpoint 2 IN Direction"] +pub type StallIDis2R = crate::BitReader; +impl StallIDis2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis2 { + match self.bits { + false => StallIDis2::EnEp2InStall, + true => StallIDis2::DisEp2InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep2_in_stall(&self) -> bool { + *self == StallIDis2::EnEp2InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep2_in_stall(&self) -> bool { + *self == StallIDis2::DisEp2InStall + } +} +#[doc = "Field `STALL_I_DIS2` writer - Disable Endpoint 2 IN Direction"] +pub type StallIDis2W<'a, REG> = crate::BitWriter<'a, REG, StallIDis2>; +impl<'a, REG> StallIDis2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep2_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis2::EnEp2InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep2_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis2::DisEp2InStall) + } +} +#[doc = "Disable Endpoint 3 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis3 { + #[doc = "0: Enable"] + EnEp3InStall = 0, + #[doc = "1: Disable"] + DisEp3InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS3` reader - Disable Endpoint 3 IN Direction"] +pub type StallIDis3R = crate::BitReader; +impl StallIDis3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis3 { + match self.bits { + false => StallIDis3::EnEp3InStall, + true => StallIDis3::DisEp3InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep3_in_stall(&self) -> bool { + *self == StallIDis3::EnEp3InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep3_in_stall(&self) -> bool { + *self == StallIDis3::DisEp3InStall + } +} +#[doc = "Field `STALL_I_DIS3` writer - Disable Endpoint 3 IN Direction"] +pub type StallIDis3W<'a, REG> = crate::BitWriter<'a, REG, StallIDis3>; +impl<'a, REG> StallIDis3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep3_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis3::EnEp3InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep3_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis3::DisEp3InStall) + } +} +#[doc = "Disable Endpoint 4 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis4 { + #[doc = "0: Enable"] + EnEp4InStall = 0, + #[doc = "1: Disable"] + DisEp4InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS4` reader - Disable Endpoint 4 IN Direction"] +pub type StallIDis4R = crate::BitReader; +impl StallIDis4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis4 { + match self.bits { + false => StallIDis4::EnEp4InStall, + true => StallIDis4::DisEp4InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep4_in_stall(&self) -> bool { + *self == StallIDis4::EnEp4InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep4_in_stall(&self) -> bool { + *self == StallIDis4::DisEp4InStall + } +} +#[doc = "Field `STALL_I_DIS4` writer - Disable Endpoint 4 IN Direction"] +pub type StallIDis4W<'a, REG> = crate::BitWriter<'a, REG, StallIDis4>; +impl<'a, REG> StallIDis4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep4_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis4::EnEp4InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep4_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis4::DisEp4InStall) + } +} +#[doc = "Disable Endpoint 5 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis5 { + #[doc = "0: Enable"] + EnEp5InStall = 0, + #[doc = "1: Disable"] + DisEp5InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS5` reader - Disable Endpoint 5 IN Direction"] +pub type StallIDis5R = crate::BitReader; +impl StallIDis5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis5 { + match self.bits { + false => StallIDis5::EnEp5InStall, + true => StallIDis5::DisEp5InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep5_in_stall(&self) -> bool { + *self == StallIDis5::EnEp5InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep5_in_stall(&self) -> bool { + *self == StallIDis5::DisEp5InStall + } +} +#[doc = "Field `STALL_I_DIS5` writer - Disable Endpoint 5 IN Direction"] +pub type StallIDis5W<'a, REG> = crate::BitWriter<'a, REG, StallIDis5>; +impl<'a, REG> StallIDis5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep5_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis5::EnEp5InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep5_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis5::DisEp5InStall) + } +} +#[doc = "Disable Endpoint 6 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis6 { + #[doc = "0: Enable"] + EnEp6InStall = 0, + #[doc = "1: Disable"] + DisEp6InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS6` reader - Disable Endpoint 6 IN Direction"] +pub type StallIDis6R = crate::BitReader; +impl StallIDis6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis6 { + match self.bits { + false => StallIDis6::EnEp6InStall, + true => StallIDis6::DisEp6InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep6_in_stall(&self) -> bool { + *self == StallIDis6::EnEp6InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep6_in_stall(&self) -> bool { + *self == StallIDis6::DisEp6InStall + } +} +#[doc = "Field `STALL_I_DIS6` writer - Disable Endpoint 6 IN Direction"] +pub type StallIDis6W<'a, REG> = crate::BitWriter<'a, REG, StallIDis6>; +impl<'a, REG> StallIDis6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep6_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis6::EnEp6InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep6_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis6::DisEp6InStall) + } +} +#[doc = "Disable Endpoint 7 IN Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallIDis7 { + #[doc = "0: Enable"] + EnEp7InStall = 0, + #[doc = "1: Disable"] + DisEp7InStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallIDis7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_I_DIS7` reader - Disable Endpoint 7 IN Direction"] +pub type StallIDis7R = crate::BitReader; +impl StallIDis7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallIDis7 { + match self.bits { + false => StallIDis7::EnEp7InStall, + true => StallIDis7::DisEp7InStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep7_in_stall(&self) -> bool { + *self == StallIDis7::EnEp7InStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep7_in_stall(&self) -> bool { + *self == StallIDis7::DisEp7InStall + } +} +#[doc = "Field `STALL_I_DIS7` writer - Disable Endpoint 7 IN Direction"] +pub type StallIDis7W<'a, REG> = crate::BitWriter<'a, REG, StallIDis7>; +impl<'a, REG> StallIDis7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep7_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis7::EnEp7InStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep7_in_stall(self) -> &'a mut crate::W { + self.variant(StallIDis7::DisEp7InStall) + } +} +impl R { + #[doc = "Bit 0 - Disable Endpoint 0 IN Direction"] + #[inline(always)] + pub fn stall_i_dis0(&self) -> StallIDis0R { + StallIDis0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Disable Endpoint 1 IN Direction"] + #[inline(always)] + pub fn stall_i_dis1(&self) -> StallIDis1R { + StallIDis1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Disable Endpoint 2 IN Direction"] + #[inline(always)] + pub fn stall_i_dis2(&self) -> StallIDis2R { + StallIDis2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Disable Endpoint 3 IN Direction"] + #[inline(always)] + pub fn stall_i_dis3(&self) -> StallIDis3R { + StallIDis3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Disable Endpoint 4 IN Direction"] + #[inline(always)] + pub fn stall_i_dis4(&self) -> StallIDis4R { + StallIDis4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Disable Endpoint 5 IN Direction"] + #[inline(always)] + pub fn stall_i_dis5(&self) -> StallIDis5R { + StallIDis5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Disable Endpoint 6 IN Direction"] + #[inline(always)] + pub fn stall_i_dis6(&self) -> StallIDis6R { + StallIDis6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Disable Endpoint 7 IN Direction"] + #[inline(always)] + pub fn stall_i_dis7(&self) -> StallIDis7R { + StallIDis7R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disable Endpoint 0 IN Direction"] + #[inline(always)] + pub fn stall_i_dis0(&mut self) -> StallIDis0W { + StallIDis0W::new(self, 0) + } + #[doc = "Bit 1 - Disable Endpoint 1 IN Direction"] + #[inline(always)] + pub fn stall_i_dis1(&mut self) -> StallIDis1W { + StallIDis1W::new(self, 1) + } + #[doc = "Bit 2 - Disable Endpoint 2 IN Direction"] + #[inline(always)] + pub fn stall_i_dis2(&mut self) -> StallIDis2W { + StallIDis2W::new(self, 2) + } + #[doc = "Bit 3 - Disable Endpoint 3 IN Direction"] + #[inline(always)] + pub fn stall_i_dis3(&mut self) -> StallIDis3W { + StallIDis3W::new(self, 3) + } + #[doc = "Bit 4 - Disable Endpoint 4 IN Direction"] + #[inline(always)] + pub fn stall_i_dis4(&mut self) -> StallIDis4W { + StallIDis4W::new(self, 4) + } + #[doc = "Bit 5 - Disable Endpoint 5 IN Direction"] + #[inline(always)] + pub fn stall_i_dis5(&mut self) -> StallIDis5W { + StallIDis5W::new(self, 5) + } + #[doc = "Bit 6 - Disable Endpoint 6 IN Direction"] + #[inline(always)] + pub fn stall_i_dis6(&mut self) -> StallIDis6W { + StallIDis6W::new(self, 6) + } + #[doc = "Bit 7 - Disable Endpoint 7 IN Direction"] + #[inline(always)] + pub fn stall_i_dis7(&mut self) -> StallIDis7W { + StallIDis7W::new(self, 7) + } +} +#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_il_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_il_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StallIlDisSpec; +impl crate::RegisterSpec for StallIlDisSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`stall_il_dis::R`](R) reader structure"] +impl crate::Readable for StallIlDisSpec {} +#[doc = "`write(|w| ..)` method takes [`stall_il_dis::W`](W) writer structure"] +impl crate::Writable for StallIlDisSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STALL_IL_DIS to value 0"] +impl crate::Resettable for StallIlDisSpec {} diff --git a/mcxa276-pac/src/usb0/stall_oh_dis.rs b/mcxa276-pac/src/usb0/stall_oh_dis.rs new file mode 100644 index 000000000..38b838823 --- /dev/null +++ b/mcxa276-pac/src/usb0/stall_oh_dis.rs @@ -0,0 +1,525 @@ +#[doc = "Register `STALL_OH_DIS` reader"] +pub type R = crate::R; +#[doc = "Register `STALL_OH_DIS` writer"] +pub type W = crate::W; +#[doc = "Disable Endpoint 8 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis8 { + #[doc = "0: Enable"] + EnEp8OutStall = 0, + #[doc = "1: Disable"] + DisEp8OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS8` reader - Disable Endpoint 8 OUT Direction"] +pub type StallODis8R = crate::BitReader; +impl StallODis8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis8 { + match self.bits { + false => StallODis8::EnEp8OutStall, + true => StallODis8::DisEp8OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep8_out_stall(&self) -> bool { + *self == StallODis8::EnEp8OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep8_out_stall(&self) -> bool { + *self == StallODis8::DisEp8OutStall + } +} +#[doc = "Field `STALL_O_DIS8` writer - Disable Endpoint 8 OUT Direction"] +pub type StallODis8W<'a, REG> = crate::BitWriter<'a, REG, StallODis8>; +impl<'a, REG> StallODis8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep8_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis8::EnEp8OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep8_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis8::DisEp8OutStall) + } +} +#[doc = "Disable Endpoint 9 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis9 { + #[doc = "0: Enable"] + EnEp9OutStall = 0, + #[doc = "1: Disable"] + DisEp9OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS9` reader - Disable Endpoint 9 OUT Direction"] +pub type StallODis9R = crate::BitReader; +impl StallODis9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis9 { + match self.bits { + false => StallODis9::EnEp9OutStall, + true => StallODis9::DisEp9OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep9_out_stall(&self) -> bool { + *self == StallODis9::EnEp9OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep9_out_stall(&self) -> bool { + *self == StallODis9::DisEp9OutStall + } +} +#[doc = "Field `STALL_O_DIS9` writer - Disable Endpoint 9 OUT Direction"] +pub type StallODis9W<'a, REG> = crate::BitWriter<'a, REG, StallODis9>; +impl<'a, REG> StallODis9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep9_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis9::EnEp9OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep9_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis9::DisEp9OutStall) + } +} +#[doc = "Disable Endpoint 10 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis10 { + #[doc = "0: Enable"] + EnEp10OutStall = 0, + #[doc = "1: Disable"] + DisEp10OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS10` reader - Disable Endpoint 10 OUT Direction"] +pub type StallODis10R = crate::BitReader; +impl StallODis10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis10 { + match self.bits { + false => StallODis10::EnEp10OutStall, + true => StallODis10::DisEp10OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep10_out_stall(&self) -> bool { + *self == StallODis10::EnEp10OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep10_out_stall(&self) -> bool { + *self == StallODis10::DisEp10OutStall + } +} +#[doc = "Field `STALL_O_DIS10` writer - Disable Endpoint 10 OUT Direction"] +pub type StallODis10W<'a, REG> = crate::BitWriter<'a, REG, StallODis10>; +impl<'a, REG> StallODis10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep10_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis10::EnEp10OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep10_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis10::DisEp10OutStall) + } +} +#[doc = "Disable Endpoint 11 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis11 { + #[doc = "0: Enable"] + EnEp11OutStall = 0, + #[doc = "1: Disable"] + DisEp11OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS11` reader - Disable Endpoint 11 OUT Direction"] +pub type StallODis11R = crate::BitReader; +impl StallODis11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis11 { + match self.bits { + false => StallODis11::EnEp11OutStall, + true => StallODis11::DisEp11OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep11_out_stall(&self) -> bool { + *self == StallODis11::EnEp11OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep11_out_stall(&self) -> bool { + *self == StallODis11::DisEp11OutStall + } +} +#[doc = "Field `STALL_O_DIS11` writer - Disable Endpoint 11 OUT Direction"] +pub type StallODis11W<'a, REG> = crate::BitWriter<'a, REG, StallODis11>; +impl<'a, REG> StallODis11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep11_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis11::EnEp11OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep11_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis11::DisEp11OutStall) + } +} +#[doc = "Disable endpoint 12 OUT direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis12 { + #[doc = "0: Enable"] + EnEp12OutStall = 0, + #[doc = "1: Disable"] + DisEp12OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS12` reader - Disable endpoint 12 OUT direction"] +pub type StallODis12R = crate::BitReader; +impl StallODis12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis12 { + match self.bits { + false => StallODis12::EnEp12OutStall, + true => StallODis12::DisEp12OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep12_out_stall(&self) -> bool { + *self == StallODis12::EnEp12OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep12_out_stall(&self) -> bool { + *self == StallODis12::DisEp12OutStall + } +} +#[doc = "Field `STALL_O_DIS12` writer - Disable endpoint 12 OUT direction"] +pub type StallODis12W<'a, REG> = crate::BitWriter<'a, REG, StallODis12>; +impl<'a, REG> StallODis12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep12_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis12::EnEp12OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep12_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis12::DisEp12OutStall) + } +} +#[doc = "Disable Endpoint 13 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis13 { + #[doc = "0: Enable"] + EnEp13OutStall = 0, + #[doc = "1: Disable"] + DisEp13OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS13` reader - Disable Endpoint 13 OUT Direction"] +pub type StallODis13R = crate::BitReader; +impl StallODis13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis13 { + match self.bits { + false => StallODis13::EnEp13OutStall, + true => StallODis13::DisEp13OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep13_out_stall(&self) -> bool { + *self == StallODis13::EnEp13OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep13_out_stall(&self) -> bool { + *self == StallODis13::DisEp13OutStall + } +} +#[doc = "Field `STALL_O_DIS13` writer - Disable Endpoint 13 OUT Direction"] +pub type StallODis13W<'a, REG> = crate::BitWriter<'a, REG, StallODis13>; +impl<'a, REG> StallODis13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep13_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis13::EnEp13OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep13_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis13::DisEp13OutStall) + } +} +#[doc = "Disable Endpoint 14 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis14 { + #[doc = "0: Enable"] + EnEp14OutStall = 0, + #[doc = "1: Disable"] + DisEp14OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS14` reader - Disable Endpoint 14 OUT Direction"] +pub type StallODis14R = crate::BitReader; +impl StallODis14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis14 { + match self.bits { + false => StallODis14::EnEp14OutStall, + true => StallODis14::DisEp14OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep14_out_stall(&self) -> bool { + *self == StallODis14::EnEp14OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep14_out_stall(&self) -> bool { + *self == StallODis14::DisEp14OutStall + } +} +#[doc = "Field `STALL_O_DIS14` writer - Disable Endpoint 14 OUT Direction"] +pub type StallODis14W<'a, REG> = crate::BitWriter<'a, REG, StallODis14>; +impl<'a, REG> StallODis14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep14_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis14::EnEp14OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep14_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis14::DisEp14OutStall) + } +} +#[doc = "Disable Endpoint 15 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis15 { + #[doc = "0: Enable"] + EnEp15OutStall = 0, + #[doc = "1: Disable"] + DisEp15OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS15` reader - Disable Endpoint 15 OUT Direction"] +pub type StallODis15R = crate::BitReader; +impl StallODis15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis15 { + match self.bits { + false => StallODis15::EnEp15OutStall, + true => StallODis15::DisEp15OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep15_out_stall(&self) -> bool { + *self == StallODis15::EnEp15OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep15_out_stall(&self) -> bool { + *self == StallODis15::DisEp15OutStall + } +} +#[doc = "Field `STALL_O_DIS15` writer - Disable Endpoint 15 OUT Direction"] +pub type StallODis15W<'a, REG> = crate::BitWriter<'a, REG, StallODis15>; +impl<'a, REG> StallODis15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep15_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis15::EnEp15OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep15_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis15::DisEp15OutStall) + } +} +impl R { + #[doc = "Bit 0 - Disable Endpoint 8 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis8(&self) -> StallODis8R { + StallODis8R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Disable Endpoint 9 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis9(&self) -> StallODis9R { + StallODis9R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Disable Endpoint 10 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis10(&self) -> StallODis10R { + StallODis10R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Disable Endpoint 11 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis11(&self) -> StallODis11R { + StallODis11R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Disable endpoint 12 OUT direction"] + #[inline(always)] + pub fn stall_o_dis12(&self) -> StallODis12R { + StallODis12R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Disable Endpoint 13 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis13(&self) -> StallODis13R { + StallODis13R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Disable Endpoint 14 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis14(&self) -> StallODis14R { + StallODis14R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Disable Endpoint 15 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis15(&self) -> StallODis15R { + StallODis15R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disable Endpoint 8 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis8(&mut self) -> StallODis8W { + StallODis8W::new(self, 0) + } + #[doc = "Bit 1 - Disable Endpoint 9 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis9(&mut self) -> StallODis9W { + StallODis9W::new(self, 1) + } + #[doc = "Bit 2 - Disable Endpoint 10 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis10(&mut self) -> StallODis10W { + StallODis10W::new(self, 2) + } + #[doc = "Bit 3 - Disable Endpoint 11 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis11(&mut self) -> StallODis11W { + StallODis11W::new(self, 3) + } + #[doc = "Bit 4 - Disable endpoint 12 OUT direction"] + #[inline(always)] + pub fn stall_o_dis12(&mut self) -> StallODis12W { + StallODis12W::new(self, 4) + } + #[doc = "Bit 5 - Disable Endpoint 13 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis13(&mut self) -> StallODis13W { + StallODis13W::new(self, 5) + } + #[doc = "Bit 6 - Disable Endpoint 14 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis14(&mut self) -> StallODis14W { + StallODis14W::new(self, 6) + } + #[doc = "Bit 7 - Disable Endpoint 15 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis15(&mut self) -> StallODis15W { + StallODis15W::new(self, 7) + } +} +#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_oh_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_oh_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StallOhDisSpec; +impl crate::RegisterSpec for StallOhDisSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`stall_oh_dis::R`](R) reader structure"] +impl crate::Readable for StallOhDisSpec {} +#[doc = "`write(|w| ..)` method takes [`stall_oh_dis::W`](W) writer structure"] +impl crate::Writable for StallOhDisSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STALL_OH_DIS to value 0"] +impl crate::Resettable for StallOhDisSpec {} diff --git a/mcxa276-pac/src/usb0/stall_ol_dis.rs b/mcxa276-pac/src/usb0/stall_ol_dis.rs new file mode 100644 index 000000000..54f99b975 --- /dev/null +++ b/mcxa276-pac/src/usb0/stall_ol_dis.rs @@ -0,0 +1,525 @@ +#[doc = "Register `STALL_OL_DIS` reader"] +pub type R = crate::R; +#[doc = "Register `STALL_OL_DIS` writer"] +pub type W = crate::W; +#[doc = "Disable Endpoint 0 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis0 { + #[doc = "0: Enable"] + EnEp0OutStall = 0, + #[doc = "1: Disable"] + DisEp0OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS0` reader - Disable Endpoint 0 OUT Direction"] +pub type StallODis0R = crate::BitReader; +impl StallODis0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis0 { + match self.bits { + false => StallODis0::EnEp0OutStall, + true => StallODis0::DisEp0OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep0_out_stall(&self) -> bool { + *self == StallODis0::EnEp0OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep0_out_stall(&self) -> bool { + *self == StallODis0::DisEp0OutStall + } +} +#[doc = "Field `STALL_O_DIS0` writer - Disable Endpoint 0 OUT Direction"] +pub type StallODis0W<'a, REG> = crate::BitWriter<'a, REG, StallODis0>; +impl<'a, REG> StallODis0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep0_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis0::EnEp0OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep0_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis0::DisEp0OutStall) + } +} +#[doc = "Disable Endpoint 1 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis1 { + #[doc = "0: Enable"] + EnEp1OutStall = 0, + #[doc = "1: Disable"] + DisEp1OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS1` reader - Disable Endpoint 1 OUT Direction"] +pub type StallODis1R = crate::BitReader; +impl StallODis1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis1 { + match self.bits { + false => StallODis1::EnEp1OutStall, + true => StallODis1::DisEp1OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep1_out_stall(&self) -> bool { + *self == StallODis1::EnEp1OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep1_out_stall(&self) -> bool { + *self == StallODis1::DisEp1OutStall + } +} +#[doc = "Field `STALL_O_DIS1` writer - Disable Endpoint 1 OUT Direction"] +pub type StallODis1W<'a, REG> = crate::BitWriter<'a, REG, StallODis1>; +impl<'a, REG> StallODis1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep1_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis1::EnEp1OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep1_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis1::DisEp1OutStall) + } +} +#[doc = "Disable Endpoint 2 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis2 { + #[doc = "0: Enable"] + EnEp2OutStall = 0, + #[doc = "1: Disable"] + DisEp2OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS2` reader - Disable Endpoint 2 OUT Direction"] +pub type StallODis2R = crate::BitReader; +impl StallODis2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis2 { + match self.bits { + false => StallODis2::EnEp2OutStall, + true => StallODis2::DisEp2OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep2_out_stall(&self) -> bool { + *self == StallODis2::EnEp2OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep2_out_stall(&self) -> bool { + *self == StallODis2::DisEp2OutStall + } +} +#[doc = "Field `STALL_O_DIS2` writer - Disable Endpoint 2 OUT Direction"] +pub type StallODis2W<'a, REG> = crate::BitWriter<'a, REG, StallODis2>; +impl<'a, REG> StallODis2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep2_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis2::EnEp2OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep2_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis2::DisEp2OutStall) + } +} +#[doc = "Disable Endpoint 3 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis3 { + #[doc = "0: Enable"] + EnEp3OutStall = 0, + #[doc = "1: Disable"] + DisEp3OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS3` reader - Disable Endpoint 3 OUT Direction"] +pub type StallODis3R = crate::BitReader; +impl StallODis3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis3 { + match self.bits { + false => StallODis3::EnEp3OutStall, + true => StallODis3::DisEp3OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep3_out_stall(&self) -> bool { + *self == StallODis3::EnEp3OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep3_out_stall(&self) -> bool { + *self == StallODis3::DisEp3OutStall + } +} +#[doc = "Field `STALL_O_DIS3` writer - Disable Endpoint 3 OUT Direction"] +pub type StallODis3W<'a, REG> = crate::BitWriter<'a, REG, StallODis3>; +impl<'a, REG> StallODis3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep3_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis3::EnEp3OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep3_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis3::DisEp3OutStall) + } +} +#[doc = "Disable Endpoint 4 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis4 { + #[doc = "0: Enable"] + EnEp4OutStall = 0, + #[doc = "1: Disable"] + DisEp4OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS4` reader - Disable Endpoint 4 OUT Direction"] +pub type StallODis4R = crate::BitReader; +impl StallODis4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis4 { + match self.bits { + false => StallODis4::EnEp4OutStall, + true => StallODis4::DisEp4OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep4_out_stall(&self) -> bool { + *self == StallODis4::EnEp4OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep4_out_stall(&self) -> bool { + *self == StallODis4::DisEp4OutStall + } +} +#[doc = "Field `STALL_O_DIS4` writer - Disable Endpoint 4 OUT Direction"] +pub type StallODis4W<'a, REG> = crate::BitWriter<'a, REG, StallODis4>; +impl<'a, REG> StallODis4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep4_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis4::EnEp4OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep4_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis4::DisEp4OutStall) + } +} +#[doc = "Disable Endpoint 5 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis5 { + #[doc = "0: Enable"] + EnEp5OutStall = 0, + #[doc = "1: Disable"] + DisEp5OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS5` reader - Disable Endpoint 5 OUT Direction"] +pub type StallODis5R = crate::BitReader; +impl StallODis5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis5 { + match self.bits { + false => StallODis5::EnEp5OutStall, + true => StallODis5::DisEp5OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep5_out_stall(&self) -> bool { + *self == StallODis5::EnEp5OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep5_out_stall(&self) -> bool { + *self == StallODis5::DisEp5OutStall + } +} +#[doc = "Field `STALL_O_DIS5` writer - Disable Endpoint 5 OUT Direction"] +pub type StallODis5W<'a, REG> = crate::BitWriter<'a, REG, StallODis5>; +impl<'a, REG> StallODis5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep5_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis5::EnEp5OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep5_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis5::DisEp5OutStall) + } +} +#[doc = "Disable Endpoint 6 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis6 { + #[doc = "0: Enable"] + EnEp6OutStall = 0, + #[doc = "1: Disable"] + DisEp6OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS6` reader - Disable Endpoint 6 OUT Direction"] +pub type StallODis6R = crate::BitReader; +impl StallODis6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis6 { + match self.bits { + false => StallODis6::EnEp6OutStall, + true => StallODis6::DisEp6OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep6_out_stall(&self) -> bool { + *self == StallODis6::EnEp6OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep6_out_stall(&self) -> bool { + *self == StallODis6::DisEp6OutStall + } +} +#[doc = "Field `STALL_O_DIS6` writer - Disable Endpoint 6 OUT Direction"] +pub type StallODis6W<'a, REG> = crate::BitWriter<'a, REG, StallODis6>; +impl<'a, REG> StallODis6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep6_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis6::EnEp6OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep6_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis6::DisEp6OutStall) + } +} +#[doc = "Disable Endpoint 7 OUT Direction\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum StallODis7 { + #[doc = "0: Enable"] + EnEp7OutStall = 0, + #[doc = "1: Disable"] + DisEp7OutStall = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: StallODis7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STALL_O_DIS7` reader - Disable Endpoint 7 OUT Direction"] +pub type StallODis7R = crate::BitReader; +impl StallODis7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> StallODis7 { + match self.bits { + false => StallODis7::EnEp7OutStall, + true => StallODis7::DisEp7OutStall, + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_ep7_out_stall(&self) -> bool { + *self == StallODis7::EnEp7OutStall + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_ep7_out_stall(&self) -> bool { + *self == StallODis7::DisEp7OutStall + } +} +#[doc = "Field `STALL_O_DIS7` writer - Disable Endpoint 7 OUT Direction"] +pub type StallODis7W<'a, REG> = crate::BitWriter<'a, REG, StallODis7>; +impl<'a, REG> StallODis7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn en_ep7_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis7::EnEp7OutStall) + } + #[doc = "Disable"] + #[inline(always)] + pub fn dis_ep7_out_stall(self) -> &'a mut crate::W { + self.variant(StallODis7::DisEp7OutStall) + } +} +impl R { + #[doc = "Bit 0 - Disable Endpoint 0 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis0(&self) -> StallODis0R { + StallODis0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Disable Endpoint 1 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis1(&self) -> StallODis1R { + StallODis1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Disable Endpoint 2 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis2(&self) -> StallODis2R { + StallODis2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Disable Endpoint 3 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis3(&self) -> StallODis3R { + StallODis3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Disable Endpoint 4 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis4(&self) -> StallODis4R { + StallODis4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Disable Endpoint 5 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis5(&self) -> StallODis5R { + StallODis5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Disable Endpoint 6 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis6(&self) -> StallODis6R { + StallODis6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Disable Endpoint 7 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis7(&self) -> StallODis7R { + StallODis7R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disable Endpoint 0 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis0(&mut self) -> StallODis0W { + StallODis0W::new(self, 0) + } + #[doc = "Bit 1 - Disable Endpoint 1 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis1(&mut self) -> StallODis1W { + StallODis1W::new(self, 1) + } + #[doc = "Bit 2 - Disable Endpoint 2 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis2(&mut self) -> StallODis2W { + StallODis2W::new(self, 2) + } + #[doc = "Bit 3 - Disable Endpoint 3 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis3(&mut self) -> StallODis3W { + StallODis3W::new(self, 3) + } + #[doc = "Bit 4 - Disable Endpoint 4 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis4(&mut self) -> StallODis4W { + StallODis4W::new(self, 4) + } + #[doc = "Bit 5 - Disable Endpoint 5 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis5(&mut self) -> StallODis5W { + StallODis5W::new(self, 5) + } + #[doc = "Bit 6 - Disable Endpoint 6 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis6(&mut self) -> StallODis6W { + StallODis6W::new(self, 6) + } + #[doc = "Bit 7 - Disable Endpoint 7 OUT Direction"] + #[inline(always)] + pub fn stall_o_dis7(&mut self) -> StallODis7W { + StallODis7W::new(self, 7) + } +} +#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ol_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ol_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StallOlDisSpec; +impl crate::RegisterSpec for StallOlDisSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`stall_ol_dis::R`](R) reader structure"] +impl crate::Readable for StallOlDisSpec {} +#[doc = "`write(|w| ..)` method takes [`stall_ol_dis::W`](W) writer structure"] +impl crate::Writable for StallOlDisSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STALL_OL_DIS to value 0"] +impl crate::Resettable for StallOlDisSpec {} diff --git a/mcxa276-pac/src/usb0/stat.rs b/mcxa276-pac/src/usb0/stat.rs new file mode 100644 index 000000000..ff7ed6544 --- /dev/null +++ b/mcxa276-pac/src/usb0/stat.rs @@ -0,0 +1,102 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Odd Bank\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Odd { + #[doc = "0: Not in the odd bank"] + NotInOddBank = 0, + #[doc = "1: In the odd bank"] + OddBank = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Odd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ODD` reader - Odd Bank"] +pub type OddR = crate::BitReader; +impl OddR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Odd { + match self.bits { + false => Odd::NotInOddBank, + true => Odd::OddBank, + } + } + #[doc = "Not in the odd bank"] + #[inline(always)] + pub fn is_not_in_odd_bank(&self) -> bool { + *self == Odd::NotInOddBank + } + #[doc = "In the odd bank"] + #[inline(always)] + pub fn is_odd_bank(&self) -> bool { + *self == Odd::OddBank + } +} +#[doc = "Transmit Indicator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Tx { + #[doc = "0: Receive"] + RxTransaction = 0, + #[doc = "1: Transmit"] + TxTransaction = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Tx) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TX` reader - Transmit Indicator"] +pub type TxR = crate::BitReader; +impl TxR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Tx { + match self.bits { + false => Tx::RxTransaction, + true => Tx::TxTransaction, + } + } + #[doc = "Receive"] + #[inline(always)] + pub fn is_rx_transaction(&self) -> bool { + *self == Tx::RxTransaction + } + #[doc = "Transmit"] + #[inline(always)] + pub fn is_tx_transaction(&self) -> bool { + *self == Tx::TxTransaction + } +} +#[doc = "Field `ENDP` reader - Endpoint address"] +pub type EndpR = crate::FieldReader; +impl R { + #[doc = "Bit 2 - Odd Bank"] + #[inline(always)] + pub fn odd(&self) -> OddR { + OddR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit Indicator"] + #[inline(always)] + pub fn tx(&self) -> TxR { + TxR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Endpoint address"] + #[inline(always)] + pub fn endp(&self) -> EndpR { + EndpR::new((self.bits >> 4) & 0x0f) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for StatSpec {} diff --git a/mcxa276-pac/src/usb0/token.rs b/mcxa276-pac/src/usb0/token.rs new file mode 100644 index 000000000..cae7ddecc --- /dev/null +++ b/mcxa276-pac/src/usb0/token.rs @@ -0,0 +1,118 @@ +#[doc = "Register `TOKEN` reader"] +pub type R = crate::R; +#[doc = "Register `TOKEN` writer"] +pub type W = crate::W; +#[doc = "Field `TOKENENDPT` reader - Token Endpoint Address"] +pub type TokenendptR = crate::FieldReader; +#[doc = "Field `TOKENENDPT` writer - Token Endpoint Address"] +pub type TokenendptW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Token Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Tokenpid { + #[doc = "1: OUT token. USBFS performs an OUT (TX) transaction."] + EnOutToken = 1, + #[doc = "9: IN token. USBFS performs an IN (RX) transaction."] + EnInToken = 9, + #[doc = "13: SETUP token. USBFS performs a SETUP (TX) transaction"] + EnSetupToken = 13, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Tokenpid) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Tokenpid { + type Ux = u8; +} +impl crate::IsEnum for Tokenpid {} +#[doc = "Field `TOKENPID` reader - Token Type"] +pub type TokenpidR = crate::FieldReader; +impl TokenpidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Tokenpid::EnOutToken), + 9 => Some(Tokenpid::EnInToken), + 13 => Some(Tokenpid::EnSetupToken), + _ => None, + } + } + #[doc = "OUT token. USBFS performs an OUT (TX) transaction."] + #[inline(always)] + pub fn is_en_out_token(&self) -> bool { + *self == Tokenpid::EnOutToken + } + #[doc = "IN token. USBFS performs an IN (RX) transaction."] + #[inline(always)] + pub fn is_en_in_token(&self) -> bool { + *self == Tokenpid::EnInToken + } + #[doc = "SETUP token. USBFS performs a SETUP (TX) transaction"] + #[inline(always)] + pub fn is_en_setup_token(&self) -> bool { + *self == Tokenpid::EnSetupToken + } +} +#[doc = "Field `TOKENPID` writer - Token Type"] +pub type TokenpidW<'a, REG> = crate::FieldWriter<'a, REG, 4, Tokenpid>; +impl<'a, REG> TokenpidW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "OUT token. USBFS performs an OUT (TX) transaction."] + #[inline(always)] + pub fn en_out_token(self) -> &'a mut crate::W { + self.variant(Tokenpid::EnOutToken) + } + #[doc = "IN token. USBFS performs an IN (RX) transaction."] + #[inline(always)] + pub fn en_in_token(self) -> &'a mut crate::W { + self.variant(Tokenpid::EnInToken) + } + #[doc = "SETUP token. USBFS performs a SETUP (TX) transaction"] + #[inline(always)] + pub fn en_setup_token(self) -> &'a mut crate::W { + self.variant(Tokenpid::EnSetupToken) + } +} +impl R { + #[doc = "Bits 0:3 - Token Endpoint Address"] + #[inline(always)] + pub fn tokenendpt(&self) -> TokenendptR { + TokenendptR::new(self.bits & 0x0f) + } + #[doc = "Bits 4:7 - Token Type"] + #[inline(always)] + pub fn tokenpid(&self) -> TokenpidR { + TokenpidR::new((self.bits >> 4) & 0x0f) + } +} +impl W { + #[doc = "Bits 0:3 - Token Endpoint Address"] + #[inline(always)] + pub fn tokenendpt(&mut self) -> TokenendptW { + TokenendptW::new(self, 0) + } + #[doc = "Bits 4:7 - Token Type"] + #[inline(always)] + pub fn tokenpid(&mut self) -> TokenpidW { + TokenpidW::new(self, 4) + } +} +#[doc = "Token\n\nYou can [`read`](crate::Reg::read) this register and get [`token::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`token::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TokenSpec; +impl crate::RegisterSpec for TokenSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`token::R`](R) reader structure"] +impl crate::Readable for TokenSpec {} +#[doc = "`write(|w| ..)` method takes [`token::W`](W) writer structure"] +impl crate::Writable for TokenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TOKEN to value 0"] +impl crate::Resettable for TokenSpec {} diff --git a/mcxa276-pac/src/usb0/usbctrl.rs b/mcxa276-pac/src/usb0/usbctrl.rs new file mode 100644 index 000000000..a8fcc3f2c --- /dev/null +++ b/mcxa276-pac/src/usb0/usbctrl.rs @@ -0,0 +1,401 @@ +#[doc = "Register `USBCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `USBCTRL` writer"] +pub type W = crate::W; +#[doc = "DP and DM Lane Reversal Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DpdmLaneReverse { + #[doc = "0: Standard USB DP and DM package pin assignment"] + DpDmStandard = 0, + #[doc = "1: Reverse roles of USB DP and DM package pins"] + DpDmReversed = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DpdmLaneReverse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPDM_LANE_REVERSE` reader - DP and DM Lane Reversal Control"] +pub type DpdmLaneReverseR = crate::BitReader; +impl DpdmLaneReverseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DpdmLaneReverse { + match self.bits { + false => DpdmLaneReverse::DpDmStandard, + true => DpdmLaneReverse::DpDmReversed, + } + } + #[doc = "Standard USB DP and DM package pin assignment"] + #[inline(always)] + pub fn is_dp_dm_standard(&self) -> bool { + *self == DpdmLaneReverse::DpDmStandard + } + #[doc = "Reverse roles of USB DP and DM package pins"] + #[inline(always)] + pub fn is_dp_dm_reversed(&self) -> bool { + *self == DpdmLaneReverse::DpDmReversed + } +} +#[doc = "Field `DPDM_LANE_REVERSE` writer - DP and DM Lane Reversal Control"] +pub type DpdmLaneReverseW<'a, REG> = crate::BitWriter<'a, REG, DpdmLaneReverse>; +impl<'a, REG> DpdmLaneReverseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard USB DP and DM package pin assignment"] + #[inline(always)] + pub fn dp_dm_standard(self) -> &'a mut crate::W { + self.variant(DpdmLaneReverse::DpDmStandard) + } + #[doc = "Reverse roles of USB DP and DM package pins"] + #[inline(always)] + pub fn dp_dm_reversed(self) -> &'a mut crate::W { + self.variant(DpdmLaneReverse::DpDmReversed) + } +} +#[doc = "Host-Mode-Only Low-Speed Device EOP Signaling\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HostLsEop { + #[doc = "0: Full-speed device or a low-speed device through a hub"] + HostFsResumeEop = 0, + #[doc = "1: Directly-connected low-speed device"] + HostLsResumeEop = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HostLsEop) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HOST_LS_EOP` reader - Host-Mode-Only Low-Speed Device EOP Signaling"] +pub type HostLsEopR = crate::BitReader; +impl HostLsEopR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> HostLsEop { + match self.bits { + false => HostLsEop::HostFsResumeEop, + true => HostLsEop::HostLsResumeEop, + } + } + #[doc = "Full-speed device or a low-speed device through a hub"] + #[inline(always)] + pub fn is_host_fs_resume_eop(&self) -> bool { + *self == HostLsEop::HostFsResumeEop + } + #[doc = "Directly-connected low-speed device"] + #[inline(always)] + pub fn is_host_ls_resume_eop(&self) -> bool { + *self == HostLsEop::HostLsResumeEop + } +} +#[doc = "Field `HOST_LS_EOP` writer - Host-Mode-Only Low-Speed Device EOP Signaling"] +pub type HostLsEopW<'a, REG> = crate::BitWriter<'a, REG, HostLsEop>; +impl<'a, REG> HostLsEopW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Full-speed device or a low-speed device through a hub"] + #[inline(always)] + pub fn host_fs_resume_eop(self) -> &'a mut crate::W { + self.variant(HostLsEop::HostFsResumeEop) + } + #[doc = "Directly-connected low-speed device"] + #[inline(always)] + pub fn host_ls_resume_eop(self) -> &'a mut crate::W { + self.variant(HostLsEop::HostLsResumeEop) + } +} +#[doc = "UART Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Uartsel { + #[doc = "0: USB DP and DM external package pins are used for USB signaling."] + UsbMode = 0, + #[doc = "1: USB DP and DM external package pins are used for UART signaling."] + UartMode = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Uartsel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UARTSEL` reader - UART Select"] +pub type UartselR = crate::BitReader; +impl UartselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Uartsel { + match self.bits { + false => Uartsel::UsbMode, + true => Uartsel::UartMode, + } + } + #[doc = "USB DP and DM external package pins are used for USB signaling."] + #[inline(always)] + pub fn is_usb_mode(&self) -> bool { + *self == Uartsel::UsbMode + } + #[doc = "USB DP and DM external package pins are used for UART signaling."] + #[inline(always)] + pub fn is_uart_mode(&self) -> bool { + *self == Uartsel::UartMode + } +} +#[doc = "Field `UARTSEL` writer - UART Select"] +pub type UartselW<'a, REG> = crate::BitWriter<'a, REG, Uartsel>; +impl<'a, REG> UartselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "USB DP and DM external package pins are used for USB signaling."] + #[inline(always)] + pub fn usb_mode(self) -> &'a mut crate::W { + self.variant(Uartsel::UsbMode) + } + #[doc = "USB DP and DM external package pins are used for UART signaling."] + #[inline(always)] + pub fn uart_mode(self) -> &'a mut crate::W { + self.variant(Uartsel::UartMode) + } +} +#[doc = "UART Signal Channel Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Uartchls { + #[doc = "0: USB DP and DM signals are used as UART TX/RX."] + UartDpTx = 0, + #[doc = "1: USB DP and DM signals are used as UART RX/TX."] + UartDmTx = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Uartchls) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UARTCHLS` reader - UART Signal Channel Select"] +pub type UartchlsR = crate::BitReader; +impl UartchlsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Uartchls { + match self.bits { + false => Uartchls::UartDpTx, + true => Uartchls::UartDmTx, + } + } + #[doc = "USB DP and DM signals are used as UART TX/RX."] + #[inline(always)] + pub fn is_uart_dp_tx(&self) -> bool { + *self == Uartchls::UartDpTx + } + #[doc = "USB DP and DM signals are used as UART RX/TX."] + #[inline(always)] + pub fn is_uart_dm_tx(&self) -> bool { + *self == Uartchls::UartDmTx + } +} +#[doc = "Field `UARTCHLS` writer - UART Signal Channel Select"] +pub type UartchlsW<'a, REG> = crate::BitWriter<'a, REG, Uartchls>; +impl<'a, REG> UartchlsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "USB DP and DM signals are used as UART TX/RX."] + #[inline(always)] + pub fn uart_dp_tx(self) -> &'a mut crate::W { + self.variant(Uartchls::UartDpTx) + } + #[doc = "USB DP and DM signals are used as UART RX/TX."] + #[inline(always)] + pub fn uart_dm_tx(self) -> &'a mut crate::W { + self.variant(Uartchls::UartDmTx) + } +} +#[doc = "Pulldown Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pde { + #[doc = "0: Disable on D+ and D-"] + DisPulldowns = 0, + #[doc = "1: Enable on D+ and D-"] + EnPulldowns = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pde) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PDE` reader - Pulldown Enable"] +pub type PdeR = crate::BitReader; +impl PdeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pde { + match self.bits { + false => Pde::DisPulldowns, + true => Pde::EnPulldowns, + } + } + #[doc = "Disable on D+ and D-"] + #[inline(always)] + pub fn is_dis_pulldowns(&self) -> bool { + *self == Pde::DisPulldowns + } + #[doc = "Enable on D+ and D-"] + #[inline(always)] + pub fn is_en_pulldowns(&self) -> bool { + *self == Pde::EnPulldowns + } +} +#[doc = "Field `PDE` writer - Pulldown Enable"] +pub type PdeW<'a, REG> = crate::BitWriter<'a, REG, Pde>; +impl<'a, REG> PdeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable on D+ and D-"] + #[inline(always)] + pub fn dis_pulldowns(self) -> &'a mut crate::W { + self.variant(Pde::DisPulldowns) + } + #[doc = "Enable on D+ and D-"] + #[inline(always)] + pub fn en_pulldowns(self) -> &'a mut crate::W { + self.variant(Pde::EnPulldowns) + } +} +#[doc = "Suspend\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Susp { + #[doc = "0: Not in Suspend state"] + XcvrNotSuspend = 0, + #[doc = "1: In Suspend state"] + XcvrSuspend = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Susp) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SUSP` reader - Suspend"] +pub type SuspR = crate::BitReader; +impl SuspR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Susp { + match self.bits { + false => Susp::XcvrNotSuspend, + true => Susp::XcvrSuspend, + } + } + #[doc = "Not in Suspend state"] + #[inline(always)] + pub fn is_xcvr_not_suspend(&self) -> bool { + *self == Susp::XcvrNotSuspend + } + #[doc = "In Suspend state"] + #[inline(always)] + pub fn is_xcvr_suspend(&self) -> bool { + *self == Susp::XcvrSuspend + } +} +#[doc = "Field `SUSP` writer - Suspend"] +pub type SuspW<'a, REG> = crate::BitWriter<'a, REG, Susp>; +impl<'a, REG> SuspW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not in Suspend state"] + #[inline(always)] + pub fn xcvr_not_suspend(self) -> &'a mut crate::W { + self.variant(Susp::XcvrNotSuspend) + } + #[doc = "In Suspend state"] + #[inline(always)] + pub fn xcvr_suspend(self) -> &'a mut crate::W { + self.variant(Susp::XcvrSuspend) + } +} +impl R { + #[doc = "Bit 2 - DP and DM Lane Reversal Control"] + #[inline(always)] + pub fn dpdm_lane_reverse(&self) -> DpdmLaneReverseR { + DpdmLaneReverseR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Host-Mode-Only Low-Speed Device EOP Signaling"] + #[inline(always)] + pub fn host_ls_eop(&self) -> HostLsEopR { + HostLsEopR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - UART Select"] + #[inline(always)] + pub fn uartsel(&self) -> UartselR { + UartselR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - UART Signal Channel Select"] + #[inline(always)] + pub fn uartchls(&self) -> UartchlsR { + UartchlsR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pulldown Enable"] + #[inline(always)] + pub fn pde(&self) -> PdeR { + PdeR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Suspend"] + #[inline(always)] + pub fn susp(&self) -> SuspR { + SuspR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - DP and DM Lane Reversal Control"] + #[inline(always)] + pub fn dpdm_lane_reverse(&mut self) -> DpdmLaneReverseW { + DpdmLaneReverseW::new(self, 2) + } + #[doc = "Bit 3 - Host-Mode-Only Low-Speed Device EOP Signaling"] + #[inline(always)] + pub fn host_ls_eop(&mut self) -> HostLsEopW { + HostLsEopW::new(self, 3) + } + #[doc = "Bit 4 - UART Select"] + #[inline(always)] + pub fn uartsel(&mut self) -> UartselW { + UartselW::new(self, 4) + } + #[doc = "Bit 5 - UART Signal Channel Select"] + #[inline(always)] + pub fn uartchls(&mut self) -> UartchlsW { + UartchlsW::new(self, 5) + } + #[doc = "Bit 6 - Pulldown Enable"] + #[inline(always)] + pub fn pde(&mut self) -> PdeW { + PdeW::new(self, 6) + } + #[doc = "Bit 7 - Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SuspW { + SuspW::new(self, 7) + } +} +#[doc = "USB Control\n\nYou can [`read`](crate::Reg::read) this register and get [`usbctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UsbctrlSpec; +impl crate::RegisterSpec for UsbctrlSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`usbctrl::R`](R) reader structure"] +impl crate::Readable for UsbctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`usbctrl::W`](W) writer structure"] +impl crate::Writable for UsbctrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets USBCTRL to value 0xc0"] +impl crate::Resettable for UsbctrlSpec { + const RESET_VALUE: u8 = 0xc0; +} diff --git a/mcxa276-pac/src/usb0/usbfrmadjust.rs b/mcxa276-pac/src/usb0/usbfrmadjust.rs new file mode 100644 index 000000000..5cda0f0be --- /dev/null +++ b/mcxa276-pac/src/usb0/usbfrmadjust.rs @@ -0,0 +1,35 @@ +#[doc = "Register `USBFRMADJUST` reader"] +pub type R = crate::R; +#[doc = "Register `USBFRMADJUST` writer"] +pub type W = crate::W; +#[doc = "Field `ADJ` reader - Frame Adjustment"] +pub type AdjR = crate::FieldReader; +#[doc = "Field `ADJ` writer - Frame Adjustment"] +pub type AdjW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Frame Adjustment"] + #[inline(always)] + pub fn adj(&self) -> AdjR { + AdjR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Frame Adjustment"] + #[inline(always)] + pub fn adj(&mut self) -> AdjW { + AdjW::new(self, 0) + } +} +#[doc = "Frame Adjust\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfrmadjust::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfrmadjust::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UsbfrmadjustSpec; +impl crate::RegisterSpec for UsbfrmadjustSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`usbfrmadjust::R`](R) reader structure"] +impl crate::Readable for UsbfrmadjustSpec {} +#[doc = "`write(|w| ..)` method takes [`usbfrmadjust::W`](W) writer structure"] +impl crate::Writable for UsbfrmadjustSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets USBFRMADJUST to value 0"] +impl crate::Resettable for UsbfrmadjustSpec {} diff --git a/mcxa276-pac/src/usb0/usbtrc0.rs b/mcxa276-pac/src/usb0/usbtrc0.rs new file mode 100644 index 000000000..c165b8013 --- /dev/null +++ b/mcxa276-pac/src/usb0/usbtrc0.rs @@ -0,0 +1,298 @@ +#[doc = "Register `USBTRC0` reader"] +pub type R = crate::R; +#[doc = "Register `USBTRC0` writer"] +pub type W = crate::W; +#[doc = "USB Asynchronous Interrupt\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum UsbResumeInt { + #[doc = "0: Not generated"] + NoAsyncInt = 0, + #[doc = "1: Generated because of the USB asynchronous interrupt"] + SyncIntGenerated = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UsbResumeInt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USB_RESUME_INT` reader - USB Asynchronous Interrupt"] +pub type UsbResumeIntR = crate::BitReader; +impl UsbResumeIntR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> UsbResumeInt { + match self.bits { + false => UsbResumeInt::NoAsyncInt, + true => UsbResumeInt::SyncIntGenerated, + } + } + #[doc = "Not generated"] + #[inline(always)] + pub fn is_no_async_int(&self) -> bool { + *self == UsbResumeInt::NoAsyncInt + } + #[doc = "Generated because of the USB asynchronous interrupt"] + #[inline(always)] + pub fn is_sync_int_generated(&self) -> bool { + *self == UsbResumeInt::SyncIntGenerated + } +} +#[doc = "Synchronous USB Interrupt Detect\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SyncDet { + #[doc = "0: Not detected"] + NoSyncInt = 0, + #[doc = "1: Detected"] + SyncIntDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SyncDet) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYNC_DET` reader - Synchronous USB Interrupt Detect"] +pub type SyncDetR = crate::BitReader; +impl SyncDetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SyncDet { + match self.bits { + false => SyncDet::NoSyncInt, + true => SyncDet::SyncIntDetected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_no_sync_int(&self) -> bool { + *self == SyncDet::NoSyncInt + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_sync_int_detected(&self) -> bool { + *self == SyncDet::SyncIntDetected + } +} +#[doc = "Field `USB_CLK_RECOVERY_INT` reader - Combined USB Clock Recovery interrupt status"] +pub type UsbClkRecoveryIntR = crate::BitReader; +#[doc = "VREGIN Rising Edge Interrupt Detect\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VredgDet { + #[doc = "0: Not detected"] + NoVregReInt = 0, + #[doc = "1: Detected"] + VregReIntDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VredgDet) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VREDG_DET` reader - VREGIN Rising Edge Interrupt Detect"] +pub type VredgDetR = crate::BitReader; +impl VredgDetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VredgDet { + match self.bits { + false => VredgDet::NoVregReInt, + true => VredgDet::VregReIntDetected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_no_vreg_re_int(&self) -> bool { + *self == VredgDet::NoVregReInt + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_vreg_re_int_detected(&self) -> bool { + *self == VredgDet::VregReIntDetected + } +} +#[doc = "VREGIN Falling Edge Interrupt Detect\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VfedgDet { + #[doc = "0: Not detected"] + NoVregFeInt = 0, + #[doc = "1: Detected"] + VregFeIntDetected = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VfedgDet) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VFEDG_DET` reader - VREGIN Falling Edge Interrupt Detect"] +pub type VfedgDetR = crate::BitReader; +impl VfedgDetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VfedgDet { + match self.bits { + false => VfedgDet::NoVregFeInt, + true => VfedgDet::VregFeIntDetected, + } + } + #[doc = "Not detected"] + #[inline(always)] + pub fn is_no_vreg_fe_int(&self) -> bool { + *self == VfedgDet::NoVregFeInt + } + #[doc = "Detected"] + #[inline(always)] + pub fn is_vreg_fe_int_detected(&self) -> bool { + *self == VfedgDet::VregFeIntDetected + } +} +#[doc = "Asynchronous Resume Interrupt Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usbresmen { + #[doc = "0: Disable"] + DisAsyncWakeup = 0, + #[doc = "1: Enable"] + EnAsyncWakeup = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usbresmen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USBRESMEN` reader - Asynchronous Resume Interrupt Enable"] +pub type UsbresmenR = crate::BitReader; +impl UsbresmenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Usbresmen { + match self.bits { + false => Usbresmen::DisAsyncWakeup, + true => Usbresmen::EnAsyncWakeup, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_dis_async_wakeup(&self) -> bool { + *self == Usbresmen::DisAsyncWakeup + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_en_async_wakeup(&self) -> bool { + *self == Usbresmen::EnAsyncWakeup + } +} +#[doc = "Field `USBRESMEN` writer - Asynchronous Resume Interrupt Enable"] +pub type UsbresmenW<'a, REG> = crate::BitWriter<'a, REG, Usbresmen>; +impl<'a, REG> UsbresmenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn dis_async_wakeup(self) -> &'a mut crate::W { + self.variant(Usbresmen::DisAsyncWakeup) + } + #[doc = "Enable"] + #[inline(always)] + pub fn en_async_wakeup(self) -> &'a mut crate::W { + self.variant(Usbresmen::EnAsyncWakeup) + } +} +#[doc = "Field `VREGIN_STS` reader - VREGIN Status"] +pub type VreginStsR = crate::BitReader; +#[doc = "USB Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Usbreset { + #[doc = "0: Normal USBFS operation"] + NormalOperation = 0, + #[doc = "1: Returns USBFS to its reset state"] + ForceHardReset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Usbreset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `USBRESET` writer - USB Reset"] +pub type UsbresetW<'a, REG> = crate::BitWriter<'a, REG, Usbreset>; +impl<'a, REG> UsbresetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Normal USBFS operation"] + #[inline(always)] + pub fn normal_operation(self) -> &'a mut crate::W { + self.variant(Usbreset::NormalOperation) + } + #[doc = "Returns USBFS to its reset state"] + #[inline(always)] + pub fn force_hard_reset(self) -> &'a mut crate::W { + self.variant(Usbreset::ForceHardReset) + } +} +impl R { + #[doc = "Bit 0 - USB Asynchronous Interrupt"] + #[inline(always)] + pub fn usb_resume_int(&self) -> UsbResumeIntR { + UsbResumeIntR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous USB Interrupt Detect"] + #[inline(always)] + pub fn sync_det(&self) -> SyncDetR { + SyncDetR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Combined USB Clock Recovery interrupt status"] + #[inline(always)] + pub fn usb_clk_recovery_int(&self) -> UsbClkRecoveryIntR { + UsbClkRecoveryIntR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VREGIN Rising Edge Interrupt Detect"] + #[inline(always)] + pub fn vredg_det(&self) -> VredgDetR { + VredgDetR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VREGIN Falling Edge Interrupt Detect"] + #[inline(always)] + pub fn vfedg_det(&self) -> VfedgDetR { + VfedgDetR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Asynchronous Resume Interrupt Enable"] + #[inline(always)] + pub fn usbresmen(&self) -> UsbresmenR { + UsbresmenR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - VREGIN Status"] + #[inline(always)] + pub fn vregin_sts(&self) -> VreginStsR { + VreginStsR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 5 - Asynchronous Resume Interrupt Enable"] + #[inline(always)] + pub fn usbresmen(&mut self) -> UsbresmenW { + UsbresmenW::new(self, 5) + } + #[doc = "Bit 7 - USB Reset"] + #[inline(always)] + pub fn usbreset(&mut self) -> UsbresetW { + UsbresetW::new(self, 7) + } +} +#[doc = "USB Transceiver Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`usbtrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbtrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Usbtrc0Spec; +impl crate::RegisterSpec for Usbtrc0Spec { + type Ux = u8; +} +#[doc = "`read()` method returns [`usbtrc0::R`](R) reader structure"] +impl crate::Readable for Usbtrc0Spec {} +#[doc = "`write(|w| ..)` method takes [`usbtrc0::W`](W) writer structure"] +impl crate::Writable for Usbtrc0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets USBTRC0 to value 0"] +impl crate::Resettable for Usbtrc0Spec {} diff --git a/mcxa276-pac/src/utick0.rs b/mcxa276-pac/src/utick0.rs new file mode 100644 index 000000000..03d70fdc9 --- /dev/null +++ b/mcxa276-pac/src/utick0.rs @@ -0,0 +1,67 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + stat: Stat, + cfg: Cfg, + capclr: Capclr, + cap: [Cap; 4], +} +impl RegisterBlock { + #[doc = "0x00 - Control"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - Status"] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } + #[doc = "0x08 - Capture Configuration"] + #[inline(always)] + pub const fn cfg(&self) -> &Cfg { + &self.cfg + } + #[doc = "0x0c - Capture Clear"] + #[inline(always)] + pub const fn capclr(&self) -> &Capclr { + &self.capclr + } + #[doc = "0x10..0x20 - Capture"] + #[inline(always)] + pub const fn cap(&self, n: usize) -> &Cap { + &self.cap[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x10..0x20 - Capture"] + #[inline(always)] + pub fn cap_iter(&self) -> impl Iterator { + self.cap.iter() + } +} +#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "CFG (rw) register accessor: Capture Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`] module"] +#[doc(alias = "CFG")] +pub type Cfg = crate::Reg; +#[doc = "Capture Configuration"] +pub mod cfg; +#[doc = "CAPCLR (w) register accessor: Capture Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`capclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capclr`] module"] +#[doc(alias = "CAPCLR")] +pub type Capclr = crate::Reg; +#[doc = "Capture Clear"] +pub mod capclr; +#[doc = "CAP (r) register accessor: Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap`] module"] +#[doc(alias = "CAP")] +pub type Cap = crate::Reg; +#[doc = "Capture"] +pub mod cap; diff --git a/mcxa276-pac/src/utick0/cap.rs b/mcxa276-pac/src/utick0/cap.rs new file mode 100644 index 000000000..ca81fc82d --- /dev/null +++ b/mcxa276-pac/src/utick0/cap.rs @@ -0,0 +1,61 @@ +#[doc = "Register `CAP[%s]` reader"] +pub type R = crate::R; +#[doc = "Field `CAP_VALUE` reader - Captured Value for the Related Capture Event"] +pub type CapValueR = crate::FieldReader; +#[doc = "Captured Value Valid Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Valid { + #[doc = "0: Valid value not captured"] + Notvalid = 0, + #[doc = "1: Valid value captured"] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Valid) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VALID` reader - Captured Value Valid Flag"] +pub type ValidR = crate::BitReader; +impl ValidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Valid { + match self.bits { + false => Valid::Notvalid, + true => Valid::Valid, + } + } + #[doc = "Valid value not captured"] + #[inline(always)] + pub fn is_notvalid(&self) -> bool { + *self == Valid::Notvalid + } + #[doc = "Valid value captured"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Valid::Valid + } +} +impl R { + #[doc = "Bits 0:30 - Captured Value for the Related Capture Event"] + #[inline(always)] + pub fn cap_value(&self) -> CapValueR { + CapValueR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Captured Value Valid Flag"] + #[inline(always)] + pub fn valid(&self) -> ValidR { + ValidR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CapSpec; +impl crate::RegisterSpec for CapSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cap::R`](R) reader structure"] +impl crate::Readable for CapSpec {} +#[doc = "`reset()` method sets CAP[%s] to value 0"] +impl crate::Resettable for CapSpec {} diff --git a/mcxa276-pac/src/utick0/capclr.rs b/mcxa276-pac/src/utick0/capclr.rs new file mode 100644 index 000000000..86b8d4d61 --- /dev/null +++ b/mcxa276-pac/src/utick0/capclr.rs @@ -0,0 +1,159 @@ +#[doc = "Register `CAPCLR` writer"] +pub type W = crate::W; +#[doc = "Clear Capture 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capclr0 { + #[doc = "0: Does nothing"] + Capclr0nothing = 0, + #[doc = "1: Clears the CAP0 register value"] + Capclr0cleared = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capclr0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPCLR0` writer - Clear Capture 0"] +pub type Capclr0W<'a, REG> = crate::BitWriter<'a, REG, Capclr0>; +impl<'a, REG> Capclr0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn capclr0nothing(self) -> &'a mut crate::W { + self.variant(Capclr0::Capclr0nothing) + } + #[doc = "Clears the CAP0 register value"] + #[inline(always)] + pub fn capclr0cleared(self) -> &'a mut crate::W { + self.variant(Capclr0::Capclr0cleared) + } +} +#[doc = "Clear Capture 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capclr1 { + #[doc = "0: Does nothing"] + Capclr1nothing = 0, + #[doc = "1: Clears the CAP1 register value"] + Capclr1cleared = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capclr1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPCLR1` writer - Clear Capture 1"] +pub type Capclr1W<'a, REG> = crate::BitWriter<'a, REG, Capclr1>; +impl<'a, REG> Capclr1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn capclr1nothing(self) -> &'a mut crate::W { + self.variant(Capclr1::Capclr1nothing) + } + #[doc = "Clears the CAP1 register value"] + #[inline(always)] + pub fn capclr1cleared(self) -> &'a mut crate::W { + self.variant(Capclr1::Capclr1cleared) + } +} +#[doc = "Clear Capture 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capclr2 { + #[doc = "0: Does nothing"] + Capclr2nothing = 0, + #[doc = "1: Clears the CAP2 register value"] + Capclr2cleared = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capclr2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPCLR2` writer - Clear Capture 2"] +pub type Capclr2W<'a, REG> = crate::BitWriter<'a, REG, Capclr2>; +impl<'a, REG> Capclr2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn capclr2nothing(self) -> &'a mut crate::W { + self.variant(Capclr2::Capclr2nothing) + } + #[doc = "Clears the CAP2 register value"] + #[inline(always)] + pub fn capclr2cleared(self) -> &'a mut crate::W { + self.variant(Capclr2::Capclr2cleared) + } +} +#[doc = "Clear Capture 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capclr3 { + #[doc = "0: Does nothing"] + Capclr3nothing = 0, + #[doc = "1: Clears the CAP3 register value"] + Capclr3cleared = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capclr3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPCLR3` writer - Clear Capture 3"] +pub type Capclr3W<'a, REG> = crate::BitWriter<'a, REG, Capclr3>; +impl<'a, REG> Capclr3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Does nothing"] + #[inline(always)] + pub fn capclr3nothing(self) -> &'a mut crate::W { + self.variant(Capclr3::Capclr3nothing) + } + #[doc = "Clears the CAP3 register value"] + #[inline(always)] + pub fn capclr3cleared(self) -> &'a mut crate::W { + self.variant(Capclr3::Capclr3cleared) + } +} +impl W { + #[doc = "Bit 0 - Clear Capture 0"] + #[inline(always)] + pub fn capclr0(&mut self) -> Capclr0W { + Capclr0W::new(self, 0) + } + #[doc = "Bit 1 - Clear Capture 1"] + #[inline(always)] + pub fn capclr1(&mut self) -> Capclr1W { + Capclr1W::new(self, 1) + } + #[doc = "Bit 2 - Clear Capture 2"] + #[inline(always)] + pub fn capclr2(&mut self) -> Capclr2W { + Capclr2W::new(self, 2) + } + #[doc = "Bit 3 - Clear Capture 3"] + #[inline(always)] + pub fn capclr3(&mut self) -> Capclr3W { + Capclr3W::new(self, 3) + } +} +#[doc = "Capture Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`capclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CapclrSpec; +impl crate::RegisterSpec for CapclrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`capclr::W`](W) writer structure"] +impl crate::Writable for CapclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CAPCLR to value 0"] +impl crate::Resettable for CapclrSpec {} diff --git a/mcxa276-pac/src/utick0/cfg.rs b/mcxa276-pac/src/utick0/cfg.rs new file mode 100644 index 000000000..671c690ce --- /dev/null +++ b/mcxa276-pac/src/utick0/cfg.rs @@ -0,0 +1,525 @@ +#[doc = "Register `CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CFG` writer"] +pub type W = crate::W; +#[doc = "Enable Capture 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capen0 { + #[doc = "0: Disable"] + Capen0isdisabled = 0, + #[doc = "1: Enable"] + Capen0isenabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capen0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPEN0` reader - Enable Capture 0"] +pub type Capen0R = crate::BitReader; +impl Capen0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Capen0 { + match self.bits { + false => Capen0::Capen0isdisabled, + true => Capen0::Capen0isenabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_capen0isdisabled(&self) -> bool { + *self == Capen0::Capen0isdisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_capen0isenabled(&self) -> bool { + *self == Capen0::Capen0isenabled + } +} +#[doc = "Field `CAPEN0` writer - Enable Capture 0"] +pub type Capen0W<'a, REG> = crate::BitWriter<'a, REG, Capen0>; +impl<'a, REG> Capen0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn capen0isdisabled(self) -> &'a mut crate::W { + self.variant(Capen0::Capen0isdisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn capen0isenabled(self) -> &'a mut crate::W { + self.variant(Capen0::Capen0isenabled) + } +} +#[doc = "Enable Capture 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capen1 { + #[doc = "0: Disable"] + Capen1isdisabled = 0, + #[doc = "1: Enable"] + Capen1isenabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capen1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPEN1` reader - Enable Capture 1"] +pub type Capen1R = crate::BitReader; +impl Capen1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Capen1 { + match self.bits { + false => Capen1::Capen1isdisabled, + true => Capen1::Capen1isenabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_capen1isdisabled(&self) -> bool { + *self == Capen1::Capen1isdisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_capen1isenabled(&self) -> bool { + *self == Capen1::Capen1isenabled + } +} +#[doc = "Field `CAPEN1` writer - Enable Capture 1"] +pub type Capen1W<'a, REG> = crate::BitWriter<'a, REG, Capen1>; +impl<'a, REG> Capen1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn capen1isdisabled(self) -> &'a mut crate::W { + self.variant(Capen1::Capen1isdisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn capen1isenabled(self) -> &'a mut crate::W { + self.variant(Capen1::Capen1isenabled) + } +} +#[doc = "Enable Capture 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capen2 { + #[doc = "0: Disable"] + Capen2isdisabled = 0, + #[doc = "1: Enable"] + Capen2isenabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capen2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPEN2` reader - Enable Capture 2"] +pub type Capen2R = crate::BitReader; +impl Capen2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Capen2 { + match self.bits { + false => Capen2::Capen2isdisabled, + true => Capen2::Capen2isenabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_capen2isdisabled(&self) -> bool { + *self == Capen2::Capen2isdisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_capen2isenabled(&self) -> bool { + *self == Capen2::Capen2isenabled + } +} +#[doc = "Field `CAPEN2` writer - Enable Capture 2"] +pub type Capen2W<'a, REG> = crate::BitWriter<'a, REG, Capen2>; +impl<'a, REG> Capen2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn capen2isdisabled(self) -> &'a mut crate::W { + self.variant(Capen2::Capen2isdisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn capen2isenabled(self) -> &'a mut crate::W { + self.variant(Capen2::Capen2isenabled) + } +} +#[doc = "Enable Capture 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Capen3 { + #[doc = "0: Disable"] + Capen3isdisabled = 0, + #[doc = "1: Enable"] + Capen3isenabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Capen3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPEN3` reader - Enable Capture 3"] +pub type Capen3R = crate::BitReader; +impl Capen3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Capen3 { + match self.bits { + false => Capen3::Capen3isdisabled, + true => Capen3::Capen3isenabled, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_capen3isdisabled(&self) -> bool { + *self == Capen3::Capen3isdisabled + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_capen3isenabled(&self) -> bool { + *self == Capen3::Capen3isenabled + } +} +#[doc = "Field `CAPEN3` writer - Enable Capture 3"] +pub type Capen3W<'a, REG> = crate::BitWriter<'a, REG, Capen3>; +impl<'a, REG> Capen3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn capen3isdisabled(self) -> &'a mut crate::W { + self.variant(Capen3::Capen3isdisabled) + } + #[doc = "Enable"] + #[inline(always)] + pub fn capen3isenabled(self) -> &'a mut crate::W { + self.variant(Capen3::Capen3isenabled) + } +} +#[doc = "Capture Polarity 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cappol0 { + #[doc = "0: Positive"] + Cappol0posedgecapture = 0, + #[doc = "1: Negative"] + Cappol0negedgecapture = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cappol0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPPOL0` reader - Capture Polarity 0"] +pub type Cappol0R = crate::BitReader; +impl Cappol0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cappol0 { + match self.bits { + false => Cappol0::Cappol0posedgecapture, + true => Cappol0::Cappol0negedgecapture, + } + } + #[doc = "Positive"] + #[inline(always)] + pub fn is_cappol0posedgecapture(&self) -> bool { + *self == Cappol0::Cappol0posedgecapture + } + #[doc = "Negative"] + #[inline(always)] + pub fn is_cappol0negedgecapture(&self) -> bool { + *self == Cappol0::Cappol0negedgecapture + } +} +#[doc = "Field `CAPPOL0` writer - Capture Polarity 0"] +pub type Cappol0W<'a, REG> = crate::BitWriter<'a, REG, Cappol0>; +impl<'a, REG> Cappol0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Positive"] + #[inline(always)] + pub fn cappol0posedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol0::Cappol0posedgecapture) + } + #[doc = "Negative"] + #[inline(always)] + pub fn cappol0negedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol0::Cappol0negedgecapture) + } +} +#[doc = "Capture-Polarity 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cappol1 { + #[doc = "0: Positive"] + Cappol1posedgecapture = 0, + #[doc = "1: Negative"] + Cappol1negedgecapture = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cappol1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPPOL1` reader - Capture-Polarity 1"] +pub type Cappol1R = crate::BitReader; +impl Cappol1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cappol1 { + match self.bits { + false => Cappol1::Cappol1posedgecapture, + true => Cappol1::Cappol1negedgecapture, + } + } + #[doc = "Positive"] + #[inline(always)] + pub fn is_cappol1posedgecapture(&self) -> bool { + *self == Cappol1::Cappol1posedgecapture + } + #[doc = "Negative"] + #[inline(always)] + pub fn is_cappol1negedgecapture(&self) -> bool { + *self == Cappol1::Cappol1negedgecapture + } +} +#[doc = "Field `CAPPOL1` writer - Capture-Polarity 1"] +pub type Cappol1W<'a, REG> = crate::BitWriter<'a, REG, Cappol1>; +impl<'a, REG> Cappol1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Positive"] + #[inline(always)] + pub fn cappol1posedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol1::Cappol1posedgecapture) + } + #[doc = "Negative"] + #[inline(always)] + pub fn cappol1negedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol1::Cappol1negedgecapture) + } +} +#[doc = "Capture Polarity 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cappol2 { + #[doc = "0: Positive"] + Cappol2posedgecapture = 0, + #[doc = "1: Negative"] + Cappol2negedgecapture = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cappol2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPPOL2` reader - Capture Polarity 2"] +pub type Cappol2R = crate::BitReader; +impl Cappol2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cappol2 { + match self.bits { + false => Cappol2::Cappol2posedgecapture, + true => Cappol2::Cappol2negedgecapture, + } + } + #[doc = "Positive"] + #[inline(always)] + pub fn is_cappol2posedgecapture(&self) -> bool { + *self == Cappol2::Cappol2posedgecapture + } + #[doc = "Negative"] + #[inline(always)] + pub fn is_cappol2negedgecapture(&self) -> bool { + *self == Cappol2::Cappol2negedgecapture + } +} +#[doc = "Field `CAPPOL2` writer - Capture Polarity 2"] +pub type Cappol2W<'a, REG> = crate::BitWriter<'a, REG, Cappol2>; +impl<'a, REG> Cappol2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Positive"] + #[inline(always)] + pub fn cappol2posedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol2::Cappol2posedgecapture) + } + #[doc = "Negative"] + #[inline(always)] + pub fn cappol2negedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol2::Cappol2negedgecapture) + } +} +#[doc = "Capture Polarity 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cappol3 { + #[doc = "0: Positive"] + Cappol3posedgecapture = 0, + #[doc = "1: Negative"] + Cappol3negedgecapture = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cappol3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAPPOL3` reader - Capture Polarity 3"] +pub type Cappol3R = crate::BitReader; +impl Cappol3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cappol3 { + match self.bits { + false => Cappol3::Cappol3posedgecapture, + true => Cappol3::Cappol3negedgecapture, + } + } + #[doc = "Positive"] + #[inline(always)] + pub fn is_cappol3posedgecapture(&self) -> bool { + *self == Cappol3::Cappol3posedgecapture + } + #[doc = "Negative"] + #[inline(always)] + pub fn is_cappol3negedgecapture(&self) -> bool { + *self == Cappol3::Cappol3negedgecapture + } +} +#[doc = "Field `CAPPOL3` writer - Capture Polarity 3"] +pub type Cappol3W<'a, REG> = crate::BitWriter<'a, REG, Cappol3>; +impl<'a, REG> Cappol3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Positive"] + #[inline(always)] + pub fn cappol3posedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol3::Cappol3posedgecapture) + } + #[doc = "Negative"] + #[inline(always)] + pub fn cappol3negedgecapture(self) -> &'a mut crate::W { + self.variant(Cappol3::Cappol3negedgecapture) + } +} +impl R { + #[doc = "Bit 0 - Enable Capture 0"] + #[inline(always)] + pub fn capen0(&self) -> Capen0R { + Capen0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Capture 1"] + #[inline(always)] + pub fn capen1(&self) -> Capen1R { + Capen1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable Capture 2"] + #[inline(always)] + pub fn capen2(&self) -> Capen2R { + Capen2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable Capture 3"] + #[inline(always)] + pub fn capen3(&self) -> Capen3R { + Capen3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Capture Polarity 0"] + #[inline(always)] + pub fn cappol0(&self) -> Cappol0R { + Cappol0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Capture-Polarity 1"] + #[inline(always)] + pub fn cappol1(&self) -> Cappol1R { + Cappol1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Capture Polarity 2"] + #[inline(always)] + pub fn cappol2(&self) -> Cappol2R { + Cappol2R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Capture Polarity 3"] + #[inline(always)] + pub fn cappol3(&self) -> Cappol3R { + Cappol3R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable Capture 0"] + #[inline(always)] + pub fn capen0(&mut self) -> Capen0W { + Capen0W::new(self, 0) + } + #[doc = "Bit 1 - Enable Capture 1"] + #[inline(always)] + pub fn capen1(&mut self) -> Capen1W { + Capen1W::new(self, 1) + } + #[doc = "Bit 2 - Enable Capture 2"] + #[inline(always)] + pub fn capen2(&mut self) -> Capen2W { + Capen2W::new(self, 2) + } + #[doc = "Bit 3 - Enable Capture 3"] + #[inline(always)] + pub fn capen3(&mut self) -> Capen3W { + Capen3W::new(self, 3) + } + #[doc = "Bit 8 - Capture Polarity 0"] + #[inline(always)] + pub fn cappol0(&mut self) -> Cappol0W { + Cappol0W::new(self, 8) + } + #[doc = "Bit 9 - Capture-Polarity 1"] + #[inline(always)] + pub fn cappol1(&mut self) -> Cappol1W { + Cappol1W::new(self, 9) + } + #[doc = "Bit 10 - Capture Polarity 2"] + #[inline(always)] + pub fn cappol2(&mut self) -> Cappol2W { + Cappol2W::new(self, 10) + } + #[doc = "Bit 11 - Capture Polarity 3"] + #[inline(always)] + pub fn cappol3(&mut self) -> Cappol3W { + Cappol3W::new(self, 11) + } +} +#[doc = "Capture Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CfgSpec; +impl crate::RegisterSpec for CfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfg::R`](R) reader structure"] +impl crate::Readable for CfgSpec {} +#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] +impl crate::Writable for CfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CFG to value 0"] +impl crate::Resettable for CfgSpec {} diff --git a/mcxa276-pac/src/utick0/ctrl.rs b/mcxa276-pac/src/utick0/ctrl.rs new file mode 100644 index 000000000..c4fadd7cc --- /dev/null +++ b/mcxa276-pac/src/utick0/ctrl.rs @@ -0,0 +1,98 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DELAYVAL` reader - Tick Interval"] +pub type DelayvalR = crate::FieldReader; +#[doc = "Field `DELAYVAL` writer - Tick Interval"] +pub type DelayvalW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Repeat Delay\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Repeat { + #[doc = "0: One-time delay"] + Delayonce = 0, + #[doc = "1: Delay repeats continuously"] + Delayrepeats = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Repeat) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `REPEAT` reader - Repeat Delay"] +pub type RepeatR = crate::BitReader; +impl RepeatR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Repeat { + match self.bits { + false => Repeat::Delayonce, + true => Repeat::Delayrepeats, + } + } + #[doc = "One-time delay"] + #[inline(always)] + pub fn is_delayonce(&self) -> bool { + *self == Repeat::Delayonce + } + #[doc = "Delay repeats continuously"] + #[inline(always)] + pub fn is_delayrepeats(&self) -> bool { + *self == Repeat::Delayrepeats + } +} +#[doc = "Field `REPEAT` writer - Repeat Delay"] +pub type RepeatW<'a, REG> = crate::BitWriter<'a, REG, Repeat>; +impl<'a, REG> RepeatW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "One-time delay"] + #[inline(always)] + pub fn delayonce(self) -> &'a mut crate::W { + self.variant(Repeat::Delayonce) + } + #[doc = "Delay repeats continuously"] + #[inline(always)] + pub fn delayrepeats(self) -> &'a mut crate::W { + self.variant(Repeat::Delayrepeats) + } +} +impl R { + #[doc = "Bits 0:30 - Tick Interval"] + #[inline(always)] + pub fn delayval(&self) -> DelayvalR { + DelayvalR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Repeat Delay"] + #[inline(always)] + pub fn repeat(&self) -> RepeatR { + RepeatR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Tick Interval"] + #[inline(always)] + pub fn delayval(&mut self) -> DelayvalW { + DelayvalW::new(self, 0) + } + #[doc = "Bit 31 - Repeat Delay"] + #[inline(always)] + pub fn repeat(&mut self) -> RepeatW { + RepeatW::new(self, 31) + } +} +#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/utick0/stat.rs b/mcxa276-pac/src/utick0/stat.rs new file mode 100644 index 000000000..c77ea4bfb --- /dev/null +++ b/mcxa276-pac/src/utick0/stat.rs @@ -0,0 +1,126 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Register `STAT` writer"] +pub type W = crate::W; +#[doc = "Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Intr { + #[doc = "0: Not pending"] + Nopendinginterrupt = 0, + #[doc = "1: Pending"] + Pendinginterrupt = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Intr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTR` reader - Interrupt Flag"] +pub type IntrR = crate::BitReader; +impl IntrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Intr { + match self.bits { + false => Intr::Nopendinginterrupt, + true => Intr::Pendinginterrupt, + } + } + #[doc = "Not pending"] + #[inline(always)] + pub fn is_nopendinginterrupt(&self) -> bool { + *self == Intr::Nopendinginterrupt + } + #[doc = "Pending"] + #[inline(always)] + pub fn is_pendinginterrupt(&self) -> bool { + *self == Intr::Pendinginterrupt + } +} +#[doc = "Field `INTR` writer - Interrupt Flag"] +pub type IntrW<'a, REG> = crate::BitWriter1C<'a, REG, Intr>; +impl<'a, REG> IntrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Not pending"] + #[inline(always)] + pub fn nopendinginterrupt(self) -> &'a mut crate::W { + self.variant(Intr::Nopendinginterrupt) + } + #[doc = "Pending"] + #[inline(always)] + pub fn pendinginterrupt(self) -> &'a mut crate::W { + self.variant(Intr::Pendinginterrupt) + } +} +#[doc = "Timer Active Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Active { + #[doc = "0: Inactive (stopped)"] + Timerisnotactive = 0, + #[doc = "1: Active"] + Timerisactive = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Active) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACTIVE` reader - Timer Active Flag"] +pub type ActiveR = crate::BitReader; +impl ActiveR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Active { + match self.bits { + false => Active::Timerisnotactive, + true => Active::Timerisactive, + } + } + #[doc = "Inactive (stopped)"] + #[inline(always)] + pub fn is_timerisnotactive(&self) -> bool { + *self == Active::Timerisnotactive + } + #[doc = "Active"] + #[inline(always)] + pub fn is_timerisactive(&self) -> bool { + *self == Active::Timerisactive + } +} +impl R { + #[doc = "Bit 0 - Interrupt Flag"] + #[inline(always)] + pub fn intr(&self) -> IntrR { + IntrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer Active Flag"] + #[inline(always)] + pub fn active(&self) -> ActiveR { + ActiveR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt Flag"] + #[inline(always)] + pub fn intr(&mut self) -> IntrW { + IntrW::new(self, 0) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] +impl crate::Writable for StatSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for StatSpec {} diff --git a/mcxa276-pac/src/vbat0.rs b/mcxa276-pac/src/vbat0.rs new file mode 100644 index 000000000..acb3d3b81 --- /dev/null +++ b/mcxa276-pac/src/vbat0.rs @@ -0,0 +1,97 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + _reserved1: [u8; 0x01fc], + froctla: Froctla, + _reserved2: [u8; 0x14], + frolcka: Frolcka, + _reserved3: [u8; 0x04], + froclke: Froclke, + _reserved4: [u8; 0x04dc], + wakeup: (), + _reserved5: [u8; 0xf8], + waklcka: Waklcka, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x200 - FRO16K Control A"] + #[inline(always)] + pub const fn froctla(&self) -> &Froctla { + &self.froctla + } + #[doc = "0x218 - FRO16K Lock A"] + #[inline(always)] + pub const fn frolcka(&self) -> &Frolcka { + &self.frolcka + } + #[doc = "0x220 - FRO16K Clock Enable"] + #[inline(always)] + pub const fn froclke(&self) -> &Froclke { + &self.froclke + } + #[doc = "0x700..0x708 - Array of registers: WAKEUPA"] + #[inline(always)] + pub const fn wakeup(&self, n: usize) -> &Wakeup { + #[allow(clippy::no_effect)] + [(); 2][n]; + unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(1792) + .add(8 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x700..0x708 - Array of registers: WAKEUPA"] + #[inline(always)] + pub fn wakeup_iter(&self) -> impl Iterator { + (0..2).map(move |n| unsafe { + &*core::ptr::from_ref(self) + .cast::() + .add(1792) + .add(8 * n) + .cast() + }) + } + #[doc = "0x7f8 - Wakeup Lock A"] + #[inline(always)] + pub const fn waklcka(&self) -> &Waklcka { + &self.waklcka + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "FROCTLA (rw) register accessor: FRO16K Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`froctla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froctla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@froctla`] module"] +#[doc(alias = "FROCTLA")] +pub type Froctla = crate::Reg; +#[doc = "FRO16K Control A"] +pub mod froctla; +#[doc = "FROLCKA (rw) register accessor: FRO16K Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`frolcka::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolcka::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frolcka`] module"] +#[doc(alias = "FROLCKA")] +pub type Frolcka = crate::Reg; +#[doc = "FRO16K Lock A"] +pub mod frolcka; +#[doc = "FROCLKE (rw) register accessor: FRO16K Clock Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`froclke::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froclke::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@froclke`] module"] +#[doc(alias = "FROCLKE")] +pub type Froclke = crate::Reg; +#[doc = "FRO16K Clock Enable"] +pub mod froclke; +#[doc = "Array of registers: WAKEUPA"] +pub use self::wakeup::Wakeup; +#[doc = r"Cluster"] +#[doc = "Array of registers: WAKEUPA"] +pub mod wakeup; +#[doc = "WAKLCKA (rw) register accessor: Wakeup Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`waklcka::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`waklcka::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@waklcka`] module"] +#[doc(alias = "WAKLCKA")] +pub type Waklcka = crate::Reg; +#[doc = "Wakeup Lock A"] +pub mod waklcka; diff --git a/mcxa276-pac/src/vbat0/froclke.rs b/mcxa276-pac/src/vbat0/froclke.rs new file mode 100644 index 000000000..0a7cd1084 --- /dev/null +++ b/mcxa276-pac/src/vbat0/froclke.rs @@ -0,0 +1,35 @@ +#[doc = "Register `FROCLKE` reader"] +pub type R = crate::R; +#[doc = "Register `FROCLKE` writer"] +pub type W = crate::W; +#[doc = "Field `CLKE` reader - Clock Enable"] +pub type ClkeR = crate::FieldReader; +#[doc = "Field `CLKE` writer - Clock Enable"] +pub type ClkeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Clock Enable"] + #[inline(always)] + pub fn clke(&self) -> ClkeR { + ClkeR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Clock Enable"] + #[inline(always)] + pub fn clke(&mut self) -> ClkeW { + ClkeW::new(self, 0) + } +} +#[doc = "FRO16K Clock Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`froclke::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froclke::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FroclkeSpec; +impl crate::RegisterSpec for FroclkeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`froclke::R`](R) reader structure"] +impl crate::Readable for FroclkeSpec {} +#[doc = "`write(|w| ..)` method takes [`froclke::W`](W) writer structure"] +impl crate::Writable for FroclkeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FROCLKE to value 0"] +impl crate::Resettable for FroclkeSpec {} diff --git a/mcxa276-pac/src/vbat0/froctla.rs b/mcxa276-pac/src/vbat0/froctla.rs new file mode 100644 index 000000000..22b590cd2 --- /dev/null +++ b/mcxa276-pac/src/vbat0/froctla.rs @@ -0,0 +1,86 @@ +#[doc = "Register `FROCTLA` reader"] +pub type R = crate::R; +#[doc = "Register `FROCTLA` writer"] +pub type W = crate::W; +#[doc = "FRO16K Enable\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FroEn { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FroEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FRO_EN` reader - FRO16K Enable"] +pub type FroEnR = crate::BitReader; +impl FroEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FroEn { + match self.bits { + false => FroEn::Disable, + true => FroEn::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == FroEn::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == FroEn::Enable + } +} +#[doc = "Field `FRO_EN` writer - FRO16K Enable"] +pub type FroEnW<'a, REG> = crate::BitWriter<'a, REG, FroEn>; +impl<'a, REG> FroEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(FroEn::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(FroEn::Enable) + } +} +impl R { + #[doc = "Bit 0 - FRO16K Enable"] + #[inline(always)] + pub fn fro_en(&self) -> FroEnR { + FroEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FRO16K Enable"] + #[inline(always)] + pub fn fro_en(&mut self) -> FroEnW { + FroEnW::new(self, 0) + } +} +#[doc = "FRO16K Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`froctla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froctla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FroctlaSpec; +impl crate::RegisterSpec for FroctlaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`froctla::R`](R) reader structure"] +impl crate::Readable for FroctlaSpec {} +#[doc = "`write(|w| ..)` method takes [`froctla::W`](W) writer structure"] +impl crate::Writable for FroctlaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FROCTLA to value 0x01"] +impl crate::Resettable for FroctlaSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/mcxa276-pac/src/vbat0/frolcka.rs b/mcxa276-pac/src/vbat0/frolcka.rs new file mode 100644 index 000000000..09d486049 --- /dev/null +++ b/mcxa276-pac/src/vbat0/frolcka.rs @@ -0,0 +1,84 @@ +#[doc = "Register `FROLCKA` reader"] +pub type R = crate::R; +#[doc = "Register `FROLCKA` writer"] +pub type W = crate::W; +#[doc = "Lock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: Do not block"] + Disable = 0, + #[doc = "1: Block"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - Lock"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Disable, + true => Lock::Enable, + } + } + #[doc = "Do not block"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lock::Disable + } + #[doc = "Block"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lock::Enable + } +} +#[doc = "Field `LOCK` writer - Lock"] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Do not block"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lock::Disable) + } + #[doc = "Block"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lock::Enable) + } +} +impl R { + #[doc = "Bit 0 - Lock"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Lock"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 0) + } +} +#[doc = "FRO16K Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`frolcka::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolcka::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FrolckaSpec; +impl crate::RegisterSpec for FrolckaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`frolcka::R`](R) reader structure"] +impl crate::Readable for FrolckaSpec {} +#[doc = "`write(|w| ..)` method takes [`frolcka::W`](W) writer structure"] +impl crate::Writable for FrolckaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FROLCKA to value 0"] +impl crate::Resettable for FrolckaSpec {} diff --git a/mcxa276-pac/src/vbat0/verid.rs b/mcxa276-pac/src/vbat0/verid.rs new file mode 100644 index 000000000..9e07aa71f --- /dev/null +++ b/mcxa276-pac/src/vbat0/verid.rs @@ -0,0 +1,36 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0101_0001"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0101_0001; +} diff --git a/mcxa276-pac/src/vbat0/wakeup.rs b/mcxa276-pac/src/vbat0/wakeup.rs new file mode 100644 index 000000000..f434b04c5 --- /dev/null +++ b/mcxa276-pac/src/vbat0/wakeup.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[doc = "Array of registers: WAKEUPA"] +#[doc(alias = "WAKEUP")] +pub struct Wakeup { + wakeupa: Wakeupa, +} +impl Wakeup { + #[doc = "0x00 - Wakeup 0 Register A"] + #[inline(always)] + pub const fn wakeupa(&self) -> &Wakeupa { + &self.wakeupa + } +} +#[doc = "WAKEUPA (rw) register accessor: Wakeup 0 Register A\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeupa`] module"] +#[doc(alias = "WAKEUPA")] +pub type Wakeupa = crate::Reg; +#[doc = "Wakeup 0 Register A"] +pub mod wakeupa; diff --git a/mcxa276-pac/src/vbat0/wakeup/wakeupa.rs b/mcxa276-pac/src/vbat0/wakeup/wakeupa.rs new file mode 100644 index 000000000..e3ce80400 --- /dev/null +++ b/mcxa276-pac/src/vbat0/wakeup/wakeupa.rs @@ -0,0 +1,35 @@ +#[doc = "Register `WAKEUPA` reader"] +pub type R = crate::R; +#[doc = "Register `WAKEUPA` writer"] +pub type W = crate::W; +#[doc = "Field `REG` reader - Register"] +pub type RegR = crate::FieldReader; +#[doc = "Field `REG` writer - Register"] +pub type RegW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Register"] + #[inline(always)] + pub fn reg(&self) -> RegR { + RegR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Register"] + #[inline(always)] + pub fn reg(&mut self) -> RegW { + RegW::new(self, 0) + } +} +#[doc = "Wakeup 0 Register A\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WakeupaSpec; +impl crate::RegisterSpec for WakeupaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wakeupa::R`](R) reader structure"] +impl crate::Readable for WakeupaSpec {} +#[doc = "`write(|w| ..)` method takes [`wakeupa::W`](W) writer structure"] +impl crate::Writable for WakeupaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WAKEUPA to value 0"] +impl crate::Resettable for WakeupaSpec {} diff --git a/mcxa276-pac/src/vbat0/waklcka.rs b/mcxa276-pac/src/vbat0/waklcka.rs new file mode 100644 index 000000000..994acaf6d --- /dev/null +++ b/mcxa276-pac/src/vbat0/waklcka.rs @@ -0,0 +1,84 @@ +#[doc = "Register `WAKLCKA` reader"] +pub type R = crate::R; +#[doc = "Register `WAKLCKA` writer"] +pub type W = crate::W; +#[doc = "Lock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: Lock is disabled"] + Disable = 0, + #[doc = "1: Lock is enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - Lock"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::Disable, + true => Lock::Enable, + } + } + #[doc = "Lock is disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Lock::Disable + } + #[doc = "Lock is enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Lock::Enable + } +} +#[doc = "Field `LOCK` writer - Lock"] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Lock is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Lock::Disable) + } + #[doc = "Lock is enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Lock::Enable) + } +} +impl R { + #[doc = "Bit 0 - Lock"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Lock"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 0) + } +} +#[doc = "Wakeup Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`waklcka::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`waklcka::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WaklckaSpec; +impl crate::RegisterSpec for WaklckaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`waklcka::R`](R) reader structure"] +impl crate::Readable for WaklckaSpec {} +#[doc = "`write(|w| ..)` method takes [`waklcka::W`](W) writer structure"] +impl crate::Writable for WaklckaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WAKLCKA to value 0"] +impl crate::Resettable for WaklckaSpec {} diff --git a/mcxa276-pac/src/waketimer0.rs b/mcxa276-pac/src/waketimer0.rs new file mode 100644 index 000000000..0d5d0dbaa --- /dev/null +++ b/mcxa276-pac/src/waketimer0.rs @@ -0,0 +1,29 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + wake_timer_ctrl: WakeTimerCtrl, + _reserved1: [u8; 0x08], + wake_timer_cnt: WakeTimerCnt, +} +impl RegisterBlock { + #[doc = "0x00 - Wake Timer Control"] + #[inline(always)] + pub const fn wake_timer_ctrl(&self) -> &WakeTimerCtrl { + &self.wake_timer_ctrl + } + #[doc = "0x0c - Wake Timer Counter"] + #[inline(always)] + pub const fn wake_timer_cnt(&self) -> &WakeTimerCnt { + &self.wake_timer_cnt + } +} +#[doc = "WAKE_TIMER_CTRL (rw) register accessor: Wake Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wake_timer_ctrl`] module"] +#[doc(alias = "WAKE_TIMER_CTRL")] +pub type WakeTimerCtrl = crate::Reg; +#[doc = "Wake Timer Control"] +pub mod wake_timer_ctrl; +#[doc = "WAKE_TIMER_CNT (rw) register accessor: Wake Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wake_timer_cnt`] module"] +#[doc(alias = "WAKE_TIMER_CNT")] +pub type WakeTimerCnt = crate::Reg; +#[doc = "Wake Timer Counter"] +pub mod wake_timer_cnt; diff --git a/mcxa276-pac/src/waketimer0/wake_timer_cnt.rs b/mcxa276-pac/src/waketimer0/wake_timer_cnt.rs new file mode 100644 index 000000000..de748204e --- /dev/null +++ b/mcxa276-pac/src/waketimer0/wake_timer_cnt.rs @@ -0,0 +1,35 @@ +#[doc = "Register `WAKE_TIMER_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `WAKE_TIMER_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `WAKE_CNT` reader - Wake Counter"] +pub type WakeCntR = crate::FieldReader; +#[doc = "Field `WAKE_CNT` writer - Wake Counter"] +pub type WakeCntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Wake Counter"] + #[inline(always)] + pub fn wake_cnt(&self) -> WakeCntR { + WakeCntR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Wake Counter"] + #[inline(always)] + pub fn wake_cnt(&mut self) -> WakeCntW { + WakeCntW::new(self, 0) + } +} +#[doc = "Wake Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WakeTimerCntSpec; +impl crate::RegisterSpec for WakeTimerCntSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wake_timer_cnt::R`](R) reader structure"] +impl crate::Readable for WakeTimerCntSpec {} +#[doc = "`write(|w| ..)` method takes [`wake_timer_cnt::W`](W) writer structure"] +impl crate::Writable for WakeTimerCntSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WAKE_TIMER_CNT to value 0"] +impl crate::Resettable for WakeTimerCntSpec {} diff --git a/mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs b/mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs new file mode 100644 index 000000000..14eab3655 --- /dev/null +++ b/mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs @@ -0,0 +1,247 @@ +#[doc = "Register `WAKE_TIMER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `WAKE_TIMER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Wake Timer Status Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WakeFlag { + #[doc = "0: Wake timer has not timed out."] + Disable = 0, + #[doc = "1: Wake timer has timed out."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WakeFlag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKE_FLAG` reader - Wake Timer Status Flag"] +pub type WakeFlagR = crate::BitReader; +impl WakeFlagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WakeFlag { + match self.bits { + false => WakeFlag::Disable, + true => WakeFlag::Enable, + } + } + #[doc = "Wake timer has not timed out."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WakeFlag::Disable + } + #[doc = "Wake timer has timed out."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == WakeFlag::Enable + } +} +#[doc = "Field `WAKE_FLAG` writer - Wake Timer Status Flag"] +pub type WakeFlagW<'a, REG> = crate::BitWriter1C<'a, REG, WakeFlag>; +impl<'a, REG> WakeFlagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Wake timer has not timed out."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(WakeFlag::Disable) + } + #[doc = "Wake timer has timed out."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(WakeFlag::Enable) + } +} +#[doc = "Clear Wake Timer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ClrWakeTimer { + #[doc = "0: No effect."] + Disable = 0, + #[doc = "1: Clears the wake timer counter and halts operation until a new count value is loaded."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ClrWakeTimer) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLR_WAKE_TIMER` writer - Clear Wake Timer"] +pub type ClrWakeTimerW<'a, REG> = crate::BitWriter<'a, REG, ClrWakeTimer>; +impl<'a, REG> ClrWakeTimerW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No effect."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ClrWakeTimer::Disable) + } + #[doc = "Clears the wake timer counter and halts operation until a new count value is loaded."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ClrWakeTimer::Enable) + } +} +#[doc = "OSC Divide Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OscDivEna { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OscDivEna) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OSC_DIV_ENA` reader - OSC Divide Enable"] +pub type OscDivEnaR = crate::BitReader; +impl OscDivEnaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OscDivEna { + match self.bits { + false => OscDivEna::Disable, + true => OscDivEna::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OscDivEna::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OscDivEna::Enable + } +} +#[doc = "Field `OSC_DIV_ENA` writer - OSC Divide Enable"] +pub type OscDivEnaW<'a, REG> = crate::BitWriter<'a, REG, OscDivEna>; +impl<'a, REG> OscDivEnaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OscDivEna::Disable) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OscDivEna::Enable) + } +} +#[doc = "Enable Interrupt\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IntrEn { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IntrEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTR_EN` reader - Enable Interrupt"] +pub type IntrEnR = crate::BitReader; +impl IntrEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IntrEn { + match self.bits { + false => IntrEn::Disable, + true => IntrEn::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IntrEn::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == IntrEn::Enable + } +} +#[doc = "Field `INTR_EN` writer - Enable Interrupt"] +pub type IntrEnW<'a, REG> = crate::BitWriter<'a, REG, IntrEn>; +impl<'a, REG> IntrEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(IntrEn::Disable) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(IntrEn::Enable) + } +} +impl R { + #[doc = "Bit 1 - Wake Timer Status Flag"] + #[inline(always)] + pub fn wake_flag(&self) -> WakeFlagR { + WakeFlagR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - OSC Divide Enable"] + #[inline(always)] + pub fn osc_div_ena(&self) -> OscDivEnaR { + OscDivEnaR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable Interrupt"] + #[inline(always)] + pub fn intr_en(&self) -> IntrEnR { + IntrEnR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Wake Timer Status Flag"] + #[inline(always)] + pub fn wake_flag(&mut self) -> WakeFlagW { + WakeFlagW::new(self, 1) + } + #[doc = "Bit 2 - Clear Wake Timer"] + #[inline(always)] + pub fn clr_wake_timer(&mut self) -> ClrWakeTimerW { + ClrWakeTimerW::new(self, 2) + } + #[doc = "Bit 4 - OSC Divide Enable"] + #[inline(always)] + pub fn osc_div_ena(&mut self) -> OscDivEnaW { + OscDivEnaW::new(self, 4) + } + #[doc = "Bit 5 - Enable Interrupt"] + #[inline(always)] + pub fn intr_en(&mut self) -> IntrEnW { + IntrEnW::new(self, 5) + } +} +#[doc = "Wake Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WakeTimerCtrlSpec; +impl crate::RegisterSpec for WakeTimerCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wake_timer_ctrl::R`](R) reader structure"] +impl crate::Readable for WakeTimerCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`wake_timer_ctrl::W`](W) writer structure"] +impl crate::Writable for WakeTimerCtrlSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x02; +} +#[doc = "`reset()` method sets WAKE_TIMER_CTRL to value 0"] +impl crate::Resettable for WakeTimerCtrlSpec {} diff --git a/mcxa276-pac/src/wuu0.rs b/mcxa276-pac/src/wuu0.rs new file mode 100644 index 000000000..15a2e7cd0 --- /dev/null +++ b/mcxa276-pac/src/wuu0.rs @@ -0,0 +1,155 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + verid: Verid, + param: Param, + pe1: Pe1, + pe2: Pe2, + _reserved4: [u8; 0x08], + me: Me, + de: De, + pf: Pf, + _reserved7: [u8; 0x0c], + filt: Filt, + _reserved8: [u8; 0x04], + pdc1: Pdc1, + pdc2: Pdc2, + _reserved10: [u8; 0x08], + fdc: Fdc, + _reserved11: [u8; 0x04], + pmc: Pmc, + _reserved12: [u8; 0x04], + fmc: Fmc, +} +impl RegisterBlock { + #[doc = "0x00 - Version ID"] + #[inline(always)] + pub const fn verid(&self) -> &Verid { + &self.verid + } + #[doc = "0x04 - Parameter"] + #[inline(always)] + pub const fn param(&self) -> &Param { + &self.param + } + #[doc = "0x08 - Pin Enable 1"] + #[inline(always)] + pub const fn pe1(&self) -> &Pe1 { + &self.pe1 + } + #[doc = "0x0c - Pin Enable 2"] + #[inline(always)] + pub const fn pe2(&self) -> &Pe2 { + &self.pe2 + } + #[doc = "0x18 - Module Interrupt Enable"] + #[inline(always)] + pub const fn me(&self) -> &Me { + &self.me + } + #[doc = "0x1c - Module DMA/Trigger Enable"] + #[inline(always)] + pub const fn de(&self) -> &De { + &self.de + } + #[doc = "0x20 - Pin Flag"] + #[inline(always)] + pub const fn pf(&self) -> &Pf { + &self.pf + } + #[doc = "0x30 - Pin Filter"] + #[inline(always)] + pub const fn filt(&self) -> &Filt { + &self.filt + } + #[doc = "0x38 - Pin DMA/Trigger Configuration 1"] + #[inline(always)] + pub const fn pdc1(&self) -> &Pdc1 { + &self.pdc1 + } + #[doc = "0x3c - Pin DMA/Trigger Configuration 2"] + #[inline(always)] + pub const fn pdc2(&self) -> &Pdc2 { + &self.pdc2 + } + #[doc = "0x48 - Pin Filter DMA/Trigger Configuration"] + #[inline(always)] + pub const fn fdc(&self) -> &Fdc { + &self.fdc + } + #[doc = "0x50 - Pin Mode Configuration"] + #[inline(always)] + pub const fn pmc(&self) -> &Pmc { + &self.pmc + } + #[doc = "0x58 - Pin Filter Mode Configuration"] + #[inline(always)] + pub const fn fmc(&self) -> &Fmc { + &self.fmc + } +} +#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +#[doc(alias = "VERID")] +pub type Verid = crate::Reg; +#[doc = "Version ID"] +pub mod verid; +#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] +#[doc(alias = "PARAM")] +pub type Param = crate::Reg; +#[doc = "Parameter"] +pub mod param; +#[doc = "PE1 (rw) register accessor: Pin Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pe1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pe1`] module"] +#[doc(alias = "PE1")] +pub type Pe1 = crate::Reg; +#[doc = "Pin Enable 1"] +pub mod pe1; +#[doc = "PE2 (rw) register accessor: Pin Enable 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pe2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pe2`] module"] +#[doc(alias = "PE2")] +pub type Pe2 = crate::Reg; +#[doc = "Pin Enable 2"] +pub mod pe2; +#[doc = "ME (rw) register accessor: Module Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`me::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`me::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@me`] module"] +#[doc(alias = "ME")] +pub type Me = crate::Reg; +#[doc = "Module Interrupt Enable"] +pub mod me; +#[doc = "DE (rw) register accessor: Module DMA/Trigger Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@de`] module"] +#[doc(alias = "DE")] +pub type De = crate::Reg; +#[doc = "Module DMA/Trigger Enable"] +pub mod de; +#[doc = "PF (rw) register accessor: Pin Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pf`] module"] +#[doc(alias = "PF")] +pub type Pf = crate::Reg; +#[doc = "Pin Flag"] +pub mod pf; +#[doc = "FILT (rw) register accessor: Pin Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filt`] module"] +#[doc(alias = "FILT")] +pub type Filt = crate::Reg; +#[doc = "Pin Filter"] +pub mod filt; +#[doc = "PDC1 (rw) register accessor: Pin DMA/Trigger Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc1`] module"] +#[doc(alias = "PDC1")] +pub type Pdc1 = crate::Reg; +#[doc = "Pin DMA/Trigger Configuration 1"] +pub mod pdc1; +#[doc = "PDC2 (rw) register accessor: Pin DMA/Trigger Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc2`] module"] +#[doc(alias = "PDC2")] +pub type Pdc2 = crate::Reg; +#[doc = "Pin DMA/Trigger Configuration 2"] +pub mod pdc2; +#[doc = "FDC (rw) register accessor: Pin Filter DMA/Trigger Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fdc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdc`] module"] +#[doc(alias = "FDC")] +pub type Fdc = crate::Reg; +#[doc = "Pin Filter DMA/Trigger Configuration"] +pub mod fdc; +#[doc = "PMC (rw) register accessor: Pin Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pmc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmc`] module"] +#[doc(alias = "PMC")] +pub type Pmc = crate::Reg; +#[doc = "Pin Mode Configuration"] +pub mod pmc; +#[doc = "FMC (rw) register accessor: Pin Filter Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fmc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fmc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmc`] module"] +#[doc(alias = "FMC")] +pub type Fmc = crate::Reg; +#[doc = "Pin Filter Mode Configuration"] +pub mod fmc; diff --git a/mcxa276-pac/src/wuu0/de.rs b/mcxa276-pac/src/wuu0/de.rs new file mode 100644 index 000000000..b6ead9e45 --- /dev/null +++ b/mcxa276-pac/src/wuu0/de.rs @@ -0,0 +1,210 @@ +#[doc = "Register `DE` reader"] +pub type R = crate::R; +#[doc = "Register `DE` writer"] +pub type W = crate::W; +#[doc = "DMA/Trigger Wake-up Enable for Module 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wude4 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wude4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUDE4` reader - DMA/Trigger Wake-up Enable for Module 4"] +pub type Wude4R = crate::BitReader; +impl Wude4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wude4 { + match self.bits { + false => Wude4::Disable, + true => Wude4::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wude4::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wude4::Enable + } +} +#[doc = "Field `WUDE4` writer - DMA/Trigger Wake-up Enable for Module 4"] +pub type Wude4W<'a, REG> = crate::BitWriter<'a, REG, Wude4>; +impl<'a, REG> Wude4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wude4::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wude4::Enable) + } +} +#[doc = "DMA/Trigger Wake-up Enable for Module 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wude6 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wude6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUDE6` reader - DMA/Trigger Wake-up Enable for Module 6"] +pub type Wude6R = crate::BitReader; +impl Wude6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wude6 { + match self.bits { + false => Wude6::Disable, + true => Wude6::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wude6::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wude6::Enable + } +} +#[doc = "Field `WUDE6` writer - DMA/Trigger Wake-up Enable for Module 6"] +pub type Wude6W<'a, REG> = crate::BitWriter<'a, REG, Wude6>; +impl<'a, REG> Wude6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wude6::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wude6::Enable) + } +} +#[doc = "DMA/Trigger Wake-up Enable for Module 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wude8 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wude8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUDE8` reader - DMA/Trigger Wake-up Enable for Module 8"] +pub type Wude8R = crate::BitReader; +impl Wude8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wude8 { + match self.bits { + false => Wude8::Disable, + true => Wude8::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wude8::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wude8::Enable + } +} +#[doc = "Field `WUDE8` writer - DMA/Trigger Wake-up Enable for Module 8"] +pub type Wude8W<'a, REG> = crate::BitWriter<'a, REG, Wude8>; +impl<'a, REG> Wude8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wude8::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wude8::Enable) + } +} +impl R { + #[doc = "Bit 4 - DMA/Trigger Wake-up Enable for Module 4"] + #[inline(always)] + pub fn wude4(&self) -> Wude4R { + Wude4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - DMA/Trigger Wake-up Enable for Module 6"] + #[inline(always)] + pub fn wude6(&self) -> Wude6R { + Wude6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - DMA/Trigger Wake-up Enable for Module 8"] + #[inline(always)] + pub fn wude8(&self) -> Wude8R { + Wude8R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - DMA/Trigger Wake-up Enable for Module 4"] + #[inline(always)] + pub fn wude4(&mut self) -> Wude4W { + Wude4W::new(self, 4) + } + #[doc = "Bit 6 - DMA/Trigger Wake-up Enable for Module 6"] + #[inline(always)] + pub fn wude6(&mut self) -> Wude6W { + Wude6W::new(self, 6) + } + #[doc = "Bit 8 - DMA/Trigger Wake-up Enable for Module 8"] + #[inline(always)] + pub fn wude8(&mut self) -> Wude8W { + Wude8W::new(self, 8) + } +} +#[doc = "Module DMA/Trigger Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DeSpec; +impl crate::RegisterSpec for DeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`de::R`](R) reader structure"] +impl crate::Readable for DeSpec {} +#[doc = "`write(|w| ..)` method takes [`de::W`](W) writer structure"] +impl crate::Writable for DeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DE to value 0"] +impl crate::Resettable for DeSpec {} diff --git a/mcxa276-pac/src/wuu0/fdc.rs b/mcxa276-pac/src/wuu0/fdc.rs new file mode 100644 index 000000000..72aae3040 --- /dev/null +++ b/mcxa276-pac/src/wuu0/fdc.rs @@ -0,0 +1,187 @@ +#[doc = "Register `FDC` reader"] +pub type R = crate::R; +#[doc = "Register `FDC` writer"] +pub type W = crate::W; +#[doc = "Filter Configuration for FILTn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Filtc1 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Filtc1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Filtc1 { + type Ux = u8; +} +impl crate::IsEnum for Filtc1 {} +#[doc = "Field `FILTC1` reader - Filter Configuration for FILTn"] +pub type Filtc1R = crate::FieldReader; +impl Filtc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Filtc1::Interrupt), + 1 => Some(Filtc1::DmaReq), + 2 => Some(Filtc1::Trigger), + _ => None, + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Filtc1::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Filtc1::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Filtc1::Trigger + } +} +#[doc = "Field `FILTC1` writer - Filter Configuration for FILTn"] +pub type Filtc1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filtc1>; +impl<'a, REG> Filtc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Filtc1::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Filtc1::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Filtc1::Trigger) + } +} +#[doc = "Filter Configuration for FILTn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Filtc2 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Filtc2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Filtc2 { + type Ux = u8; +} +impl crate::IsEnum for Filtc2 {} +#[doc = "Field `FILTC2` reader - Filter Configuration for FILTn"] +pub type Filtc2R = crate::FieldReader; +impl Filtc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Filtc2::Interrupt), + 1 => Some(Filtc2::DmaReq), + 2 => Some(Filtc2::Trigger), + _ => None, + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Filtc2::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Filtc2::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Filtc2::Trigger + } +} +#[doc = "Field `FILTC2` writer - Filter Configuration for FILTn"] +pub type Filtc2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filtc2>; +impl<'a, REG> Filtc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Filtc2::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Filtc2::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Filtc2::Trigger) + } +} +impl R { + #[doc = "Bits 0:1 - Filter Configuration for FILTn"] + #[inline(always)] + pub fn filtc1(&self) -> Filtc1R { + Filtc1R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Filter Configuration for FILTn"] + #[inline(always)] + pub fn filtc2(&self) -> Filtc2R { + Filtc2R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Filter Configuration for FILTn"] + #[inline(always)] + pub fn filtc1(&mut self) -> Filtc1W { + Filtc1W::new(self, 0) + } + #[doc = "Bits 2:3 - Filter Configuration for FILTn"] + #[inline(always)] + pub fn filtc2(&mut self) -> Filtc2W { + Filtc2W::new(self, 2) + } +} +#[doc = "Pin Filter DMA/Trigger Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fdc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FdcSpec; +impl crate::RegisterSpec for FdcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fdc::R`](R) reader structure"] +impl crate::Readable for FdcSpec {} +#[doc = "`write(|w| ..)` method takes [`fdc::W`](W) writer structure"] +impl crate::Writable for FdcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FDC to value 0"] +impl crate::Resettable for FdcSpec {} diff --git a/mcxa276-pac/src/wuu0/filt.rs b/mcxa276-pac/src/wuu0/filt.rs new file mode 100644 index 000000000..bf5597ba4 --- /dev/null +++ b/mcxa276-pac/src/wuu0/filt.rs @@ -0,0 +1,368 @@ +#[doc = "Register `FILT` reader"] +pub type R = crate::R; +#[doc = "Register `FILT` writer"] +pub type W = crate::W; +#[doc = "Field `FILTSEL1` reader - Filter 1 Pin Select"] +pub type Filtsel1R = crate::FieldReader; +#[doc = "Field `FILTSEL1` writer - Filter 1 Pin Select"] +pub type Filtsel1W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Filter 1 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Filte1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (Detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (Detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (Detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Filte1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Filte1 { + type Ux = u8; +} +impl crate::IsEnum for Filte1 {} +#[doc = "Field `FILTE1` reader - Filter 1 Enable"] +pub type Filte1R = crate::FieldReader; +impl Filte1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filte1 { + match self.bits { + 0 => Filte1::Disable, + 1 => Filte1::EnRiseHi, + 2 => Filte1::EnFallLo, + 3 => Filte1::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Filte1::Disable + } + #[doc = "Enable (Detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Filte1::EnRiseHi + } + #[doc = "Enable (Detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Filte1::EnFallLo + } + #[doc = "Enable (Detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Filte1::EnAny + } +} +#[doc = "Field `FILTE1` writer - Filter 1 Enable"] +pub type Filte1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filte1, crate::Safe>; +impl<'a, REG> Filte1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Filte1::Disable) + } + #[doc = "Enable (Detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Filte1::EnRiseHi) + } + #[doc = "Enable (Detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Filte1::EnFallLo) + } + #[doc = "Enable (Detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Filte1::EnAny) + } +} +#[doc = "Filter 1 Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Filtf1 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Filtf1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILTF1` reader - Filter 1 Flag"] +pub type Filtf1R = crate::BitReader; +impl Filtf1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filtf1 { + match self.bits { + false => Filtf1::NoFlag, + true => Filtf1::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Filtf1::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Filtf1::Flag + } +} +#[doc = "Field `FILTF1` writer - Filter 1 Flag"] +pub type Filtf1W<'a, REG> = crate::BitWriter1C<'a, REG, Filtf1>; +impl<'a, REG> Filtf1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Filtf1::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Filtf1::Flag) + } +} +#[doc = "Field `FILTSEL2` reader - Filter 2 Pin Select"] +pub type Filtsel2R = crate::FieldReader; +#[doc = "Field `FILTSEL2` writer - Filter 2 Pin Select"] +pub type Filtsel2W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Filter 2 Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Filte2 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (Detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (Detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (Detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Filte2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Filte2 { + type Ux = u8; +} +impl crate::IsEnum for Filte2 {} +#[doc = "Field `FILTE2` reader - Filter 2 Enable"] +pub type Filte2R = crate::FieldReader; +impl Filte2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filte2 { + match self.bits { + 0 => Filte2::Disable, + 1 => Filte2::EnRiseHi, + 2 => Filte2::EnFallLo, + 3 => Filte2::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Filte2::Disable + } + #[doc = "Enable (Detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Filte2::EnRiseHi + } + #[doc = "Enable (Detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Filte2::EnFallLo + } + #[doc = "Enable (Detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Filte2::EnAny + } +} +#[doc = "Field `FILTE2` writer - Filter 2 Enable"] +pub type Filte2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filte2, crate::Safe>; +impl<'a, REG> Filte2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Filte2::Disable) + } + #[doc = "Enable (Detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Filte2::EnRiseHi) + } + #[doc = "Enable (Detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Filte2::EnFallLo) + } + #[doc = "Enable (Detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Filte2::EnAny) + } +} +#[doc = "Filter 2 Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Filtf2 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Filtf2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILTF2` reader - Filter 2 Flag"] +pub type Filtf2R = crate::BitReader; +impl Filtf2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filtf2 { + match self.bits { + false => Filtf2::NoFlag, + true => Filtf2::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Filtf2::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Filtf2::Flag + } +} +#[doc = "Field `FILTF2` writer - Filter 2 Flag"] +pub type Filtf2W<'a, REG> = crate::BitWriter1C<'a, REG, Filtf2>; +impl<'a, REG> Filtf2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Filtf2::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Filtf2::Flag) + } +} +impl R { + #[doc = "Bits 0:4 - Filter 1 Pin Select"] + #[inline(always)] + pub fn filtsel1(&self) -> Filtsel1R { + Filtsel1R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Filter 1 Enable"] + #[inline(always)] + pub fn filte1(&self) -> Filte1R { + Filte1R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Filter 1 Flag"] + #[inline(always)] + pub fn filtf1(&self) -> Filtf1R { + Filtf1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - Filter 2 Pin Select"] + #[inline(always)] + pub fn filtsel2(&self) -> Filtsel2R { + Filtsel2R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Filter 2 Enable"] + #[inline(always)] + pub fn filte2(&self) -> Filte2R { + Filte2R::new(((self.bits >> 13) & 3) as u8) + } + #[doc = "Bit 15 - Filter 2 Flag"] + #[inline(always)] + pub fn filtf2(&self) -> Filtf2R { + Filtf2R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Filter 1 Pin Select"] + #[inline(always)] + pub fn filtsel1(&mut self) -> Filtsel1W { + Filtsel1W::new(self, 0) + } + #[doc = "Bits 5:6 - Filter 1 Enable"] + #[inline(always)] + pub fn filte1(&mut self) -> Filte1W { + Filte1W::new(self, 5) + } + #[doc = "Bit 7 - Filter 1 Flag"] + #[inline(always)] + pub fn filtf1(&mut self) -> Filtf1W { + Filtf1W::new(self, 7) + } + #[doc = "Bits 8:12 - Filter 2 Pin Select"] + #[inline(always)] + pub fn filtsel2(&mut self) -> Filtsel2W { + Filtsel2W::new(self, 8) + } + #[doc = "Bits 13:14 - Filter 2 Enable"] + #[inline(always)] + pub fn filte2(&mut self) -> Filte2W { + Filte2W::new(self, 13) + } + #[doc = "Bit 15 - Filter 2 Flag"] + #[inline(always)] + pub fn filtf2(&mut self) -> Filtf2W { + Filtf2W::new(self, 15) + } +} +#[doc = "Pin Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FiltSpec; +impl crate::RegisterSpec for FiltSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`filt::R`](R) reader structure"] +impl crate::Readable for FiltSpec {} +#[doc = "`write(|w| ..)` method takes [`filt::W`](W) writer structure"] +impl crate::Writable for FiltSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8080; +} +#[doc = "`reset()` method sets FILT to value 0"] +impl crate::Resettable for FiltSpec {} diff --git a/mcxa276-pac/src/wuu0/fmc.rs b/mcxa276-pac/src/wuu0/fmc.rs new file mode 100644 index 000000000..791a02c04 --- /dev/null +++ b/mcxa276-pac/src/wuu0/fmc.rs @@ -0,0 +1,147 @@ +#[doc = "Register `FMC` reader"] +pub type R = crate::R; +#[doc = "Register `FMC` writer"] +pub type W = crate::W; +#[doc = "Filter Mode for FILTn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Filtm1 { + #[doc = "0: Active only during Power Down/Deep Power Down mode"] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes"] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Filtm1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILTM1` reader - Filter Mode for FILTn"] +pub type Filtm1R = crate::BitReader; +impl Filtm1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filtm1 { + match self.bits { + false => Filtm1::LowPwrOnly, + true => Filtm1::AnyPwr, + } + } + #[doc = "Active only during Power Down/Deep Power Down mode"] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Filtm1::LowPwrOnly + } + #[doc = "Active during all power modes"] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Filtm1::AnyPwr + } +} +#[doc = "Field `FILTM1` writer - Filter Mode for FILTn"] +pub type Filtm1W<'a, REG> = crate::BitWriter<'a, REG, Filtm1>; +impl<'a, REG> Filtm1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during Power Down/Deep Power Down mode"] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Filtm1::LowPwrOnly) + } + #[doc = "Active during all power modes"] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Filtm1::AnyPwr) + } +} +#[doc = "Filter Mode for FILTn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Filtm2 { + #[doc = "0: Active only during Power Down/Deep Power Down mode"] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes"] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Filtm2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FILTM2` reader - Filter Mode for FILTn"] +pub type Filtm2R = crate::BitReader; +impl Filtm2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Filtm2 { + match self.bits { + false => Filtm2::LowPwrOnly, + true => Filtm2::AnyPwr, + } + } + #[doc = "Active only during Power Down/Deep Power Down mode"] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Filtm2::LowPwrOnly + } + #[doc = "Active during all power modes"] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Filtm2::AnyPwr + } +} +#[doc = "Field `FILTM2` writer - Filter Mode for FILTn"] +pub type Filtm2W<'a, REG> = crate::BitWriter<'a, REG, Filtm2>; +impl<'a, REG> Filtm2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during Power Down/Deep Power Down mode"] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Filtm2::LowPwrOnly) + } + #[doc = "Active during all power modes"] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Filtm2::AnyPwr) + } +} +impl R { + #[doc = "Bit 0 - Filter Mode for FILTn"] + #[inline(always)] + pub fn filtm1(&self) -> Filtm1R { + Filtm1R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Filter Mode for FILTn"] + #[inline(always)] + pub fn filtm2(&self) -> Filtm2R { + Filtm2R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Filter Mode for FILTn"] + #[inline(always)] + pub fn filtm1(&mut self) -> Filtm1W { + Filtm1W::new(self, 0) + } + #[doc = "Bit 1 - Filter Mode for FILTn"] + #[inline(always)] + pub fn filtm2(&mut self) -> Filtm2W { + Filtm2W::new(self, 1) + } +} +#[doc = "Pin Filter Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fmc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fmc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FmcSpec; +impl crate::RegisterSpec for FmcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmc::R`](R) reader structure"] +impl crate::Readable for FmcSpec {} +#[doc = "`write(|w| ..)` method takes [`fmc::W`](W) writer structure"] +impl crate::Writable for FmcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FMC to value 0"] +impl crate::Resettable for FmcSpec {} diff --git a/mcxa276-pac/src/wuu0/me.rs b/mcxa276-pac/src/wuu0/me.rs new file mode 100644 index 000000000..ed940e80f --- /dev/null +++ b/mcxa276-pac/src/wuu0/me.rs @@ -0,0 +1,399 @@ +#[doc = "Register `ME` reader"] +pub type R = crate::R; +#[doc = "Register `ME` writer"] +pub type W = crate::W; +#[doc = "Module Interrupt Wake-up Enable for Module 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wume0 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wume0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUME0` reader - Module Interrupt Wake-up Enable for Module 0"] +pub type Wume0R = crate::BitReader; +impl Wume0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wume0 { + match self.bits { + false => Wume0::Disable, + true => Wume0::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wume0::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wume0::Enable + } +} +#[doc = "Field `WUME0` writer - Module Interrupt Wake-up Enable for Module 0"] +pub type Wume0W<'a, REG> = crate::BitWriter<'a, REG, Wume0>; +impl<'a, REG> Wume0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wume0::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wume0::Enable) + } +} +#[doc = "Module Interrupt Wake-up Enable for Module 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wume1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wume1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUME1` reader - Module Interrupt Wake-up Enable for Module 1"] +pub type Wume1R = crate::BitReader; +impl Wume1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wume1 { + match self.bits { + false => Wume1::Disable, + true => Wume1::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wume1::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wume1::Enable + } +} +#[doc = "Field `WUME1` writer - Module Interrupt Wake-up Enable for Module 1"] +pub type Wume1W<'a, REG> = crate::BitWriter<'a, REG, Wume1>; +impl<'a, REG> Wume1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wume1::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wume1::Enable) + } +} +#[doc = "Module Interrupt Wake-up Enable for Module 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wume2 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wume2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUME2` reader - Module Interrupt Wake-up Enable for Module 2"] +pub type Wume2R = crate::BitReader; +impl Wume2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wume2 { + match self.bits { + false => Wume2::Disable, + true => Wume2::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wume2::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wume2::Enable + } +} +#[doc = "Field `WUME2` writer - Module Interrupt Wake-up Enable for Module 2"] +pub type Wume2W<'a, REG> = crate::BitWriter<'a, REG, Wume2>; +impl<'a, REG> Wume2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wume2::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wume2::Enable) + } +} +#[doc = "Module Interrupt Wake-up Enable for Module 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wume3 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wume3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUME3` reader - Module Interrupt Wake-up Enable for Module 3"] +pub type Wume3R = crate::BitReader; +impl Wume3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wume3 { + match self.bits { + false => Wume3::Disable, + true => Wume3::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wume3::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wume3::Enable + } +} +#[doc = "Field `WUME3` writer - Module Interrupt Wake-up Enable for Module 3"] +pub type Wume3W<'a, REG> = crate::BitWriter<'a, REG, Wume3>; +impl<'a, REG> Wume3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wume3::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wume3::Enable) + } +} +#[doc = "Module Interrupt Wake-up Enable for Module 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wume6 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wume6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUME6` reader - Module Interrupt Wake-up Enable for Module 6"] +pub type Wume6R = crate::BitReader; +impl Wume6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wume6 { + match self.bits { + false => Wume6::Disable, + true => Wume6::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wume6::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wume6::Enable + } +} +#[doc = "Field `WUME6` writer - Module Interrupt Wake-up Enable for Module 6"] +pub type Wume6W<'a, REG> = crate::BitWriter<'a, REG, Wume6>; +impl<'a, REG> Wume6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wume6::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wume6::Enable) + } +} +#[doc = "Module Interrupt Wake-up Enable for Module 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wume8 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wume8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUME8` reader - Module Interrupt Wake-up Enable for Module 8"] +pub type Wume8R = crate::BitReader; +impl Wume8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wume8 { + match self.bits { + false => Wume8::Disable, + true => Wume8::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wume8::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wume8::Enable + } +} +#[doc = "Field `WUME8` writer - Module Interrupt Wake-up Enable for Module 8"] +pub type Wume8W<'a, REG> = crate::BitWriter<'a, REG, Wume8>; +impl<'a, REG> Wume8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wume8::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wume8::Enable) + } +} +impl R { + #[doc = "Bit 0 - Module Interrupt Wake-up Enable for Module 0"] + #[inline(always)] + pub fn wume0(&self) -> Wume0R { + Wume0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Module Interrupt Wake-up Enable for Module 1"] + #[inline(always)] + pub fn wume1(&self) -> Wume1R { + Wume1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Module Interrupt Wake-up Enable for Module 2"] + #[inline(always)] + pub fn wume2(&self) -> Wume2R { + Wume2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Module Interrupt Wake-up Enable for Module 3"] + #[inline(always)] + pub fn wume3(&self) -> Wume3R { + Wume3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - Module Interrupt Wake-up Enable for Module 6"] + #[inline(always)] + pub fn wume6(&self) -> Wume6R { + Wume6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Module Interrupt Wake-up Enable for Module 8"] + #[inline(always)] + pub fn wume8(&self) -> Wume8R { + Wume8R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Module Interrupt Wake-up Enable for Module 0"] + #[inline(always)] + pub fn wume0(&mut self) -> Wume0W { + Wume0W::new(self, 0) + } + #[doc = "Bit 1 - Module Interrupt Wake-up Enable for Module 1"] + #[inline(always)] + pub fn wume1(&mut self) -> Wume1W { + Wume1W::new(self, 1) + } + #[doc = "Bit 2 - Module Interrupt Wake-up Enable for Module 2"] + #[inline(always)] + pub fn wume2(&mut self) -> Wume2W { + Wume2W::new(self, 2) + } + #[doc = "Bit 3 - Module Interrupt Wake-up Enable for Module 3"] + #[inline(always)] + pub fn wume3(&mut self) -> Wume3W { + Wume3W::new(self, 3) + } + #[doc = "Bit 6 - Module Interrupt Wake-up Enable for Module 6"] + #[inline(always)] + pub fn wume6(&mut self) -> Wume6W { + Wume6W::new(self, 6) + } + #[doc = "Bit 8 - Module Interrupt Wake-up Enable for Module 8"] + #[inline(always)] + pub fn wume8(&mut self) -> Wume8W { + Wume8W::new(self, 8) + } +} +#[doc = "Module Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`me::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`me::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MeSpec; +impl crate::RegisterSpec for MeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`me::R`](R) reader structure"] +impl crate::Readable for MeSpec {} +#[doc = "`write(|w| ..)` method takes [`me::W`](W) writer structure"] +impl crate::Writable for MeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ME to value 0"] +impl crate::Resettable for MeSpec {} diff --git a/mcxa276-pac/src/wuu0/param.rs b/mcxa276-pac/src/wuu0/param.rs new file mode 100644 index 000000000..579cd821a --- /dev/null +++ b/mcxa276-pac/src/wuu0/param.rs @@ -0,0 +1,43 @@ +#[doc = "Register `PARAM` reader"] +pub type R = crate::R; +#[doc = "Field `FILTERS` reader - Filter Number"] +pub type FiltersR = crate::FieldReader; +#[doc = "Field `DMAS` reader - DMA Number"] +pub type DmasR = crate::FieldReader; +#[doc = "Field `MODULES` reader - Module Number"] +pub type ModulesR = crate::FieldReader; +#[doc = "Field `PINS` reader - Pin Number"] +pub type PinsR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Filter Number"] + #[inline(always)] + pub fn filters(&self) -> FiltersR { + FiltersR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA Number"] + #[inline(always)] + pub fn dmas(&self) -> DmasR { + DmasR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Module Number"] + #[inline(always)] + pub fn modules(&self) -> ModulesR { + ModulesR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Pin Number"] + #[inline(always)] + pub fn pins(&self) -> PinsR { + PinsR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ParamSpec; +impl crate::RegisterSpec for ParamSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`param::R`](R) reader structure"] +impl crate::Readable for ParamSpec {} +#[doc = "`reset()` method sets PARAM to value 0x2020_2002"] +impl crate::Resettable for ParamSpec { + const RESET_VALUE: u32 = 0x2020_2002; +} diff --git a/mcxa276-pac/src/wuu0/pdc1.rs b/mcxa276-pac/src/wuu0/pdc1.rs new file mode 100644 index 000000000..2e5fcb236 --- /dev/null +++ b/mcxa276-pac/src/wuu0/pdc1.rs @@ -0,0 +1,1557 @@ +#[doc = "Register `PDC1` reader"] +pub type R = crate::R; +#[doc = "Register `PDC1` writer"] +pub type W = crate::W; +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc0 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc0 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc0 {} +#[doc = "Field `WUPDC0` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc0R = crate::FieldReader; +impl Wupdc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc0 { + match self.bits { + 0 => Wupdc0::Interrupt, + 1 => Wupdc0::DmaReq, + 2 => Wupdc0::Trigger, + 3 => Wupdc0::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc0::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc0::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc0::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc0::Res + } +} +#[doc = "Field `WUPDC0` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc0, crate::Safe>; +impl<'a, REG> Wupdc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc0::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc0::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc0::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc0::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc1 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc1 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc1 {} +#[doc = "Field `WUPDC1` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc1R = crate::FieldReader; +impl Wupdc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc1 { + match self.bits { + 0 => Wupdc1::Interrupt, + 1 => Wupdc1::DmaReq, + 2 => Wupdc1::Trigger, + 3 => Wupdc1::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc1::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc1::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc1::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc1::Res + } +} +#[doc = "Field `WUPDC1` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc1, crate::Safe>; +impl<'a, REG> Wupdc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc1::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc1::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc1::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc1::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc2 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc2 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc2 {} +#[doc = "Field `WUPDC2` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc2R = crate::FieldReader; +impl Wupdc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc2 { + match self.bits { + 0 => Wupdc2::Interrupt, + 1 => Wupdc2::DmaReq, + 2 => Wupdc2::Trigger, + 3 => Wupdc2::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc2::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc2::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc2::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc2::Res + } +} +#[doc = "Field `WUPDC2` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc2, crate::Safe>; +impl<'a, REG> Wupdc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc2::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc2::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc2::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc2::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc3 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc3 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc3 {} +#[doc = "Field `WUPDC3` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc3R = crate::FieldReader; +impl Wupdc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc3 { + match self.bits { + 0 => Wupdc3::Interrupt, + 1 => Wupdc3::DmaReq, + 2 => Wupdc3::Trigger, + 3 => Wupdc3::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc3::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc3::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc3::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc3::Res + } +} +#[doc = "Field `WUPDC3` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc3W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc3, crate::Safe>; +impl<'a, REG> Wupdc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc3::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc3::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc3::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc3::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc4 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc4 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc4 {} +#[doc = "Field `WUPDC4` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc4R = crate::FieldReader; +impl Wupdc4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc4 { + match self.bits { + 0 => Wupdc4::Interrupt, + 1 => Wupdc4::DmaReq, + 2 => Wupdc4::Trigger, + 3 => Wupdc4::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc4::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc4::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc4::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc4::Res + } +} +#[doc = "Field `WUPDC4` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc4W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc4, crate::Safe>; +impl<'a, REG> Wupdc4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc4::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc4::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc4::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc4::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc5 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc5 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc5 {} +#[doc = "Field `WUPDC5` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc5R = crate::FieldReader; +impl Wupdc5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc5 { + match self.bits { + 0 => Wupdc5::Interrupt, + 1 => Wupdc5::DmaReq, + 2 => Wupdc5::Trigger, + 3 => Wupdc5::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc5::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc5::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc5::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc5::Res + } +} +#[doc = "Field `WUPDC5` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc5W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc5, crate::Safe>; +impl<'a, REG> Wupdc5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc5::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc5::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc5::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc5::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc6 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc6 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc6 {} +#[doc = "Field `WUPDC6` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc6R = crate::FieldReader; +impl Wupdc6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc6 { + match self.bits { + 0 => Wupdc6::Interrupt, + 1 => Wupdc6::DmaReq, + 2 => Wupdc6::Trigger, + 3 => Wupdc6::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc6::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc6::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc6::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc6::Res + } +} +#[doc = "Field `WUPDC6` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc6W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc6, crate::Safe>; +impl<'a, REG> Wupdc6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc6::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc6::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc6::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc6::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc7 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc7 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc7 {} +#[doc = "Field `WUPDC7` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc7R = crate::FieldReader; +impl Wupdc7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc7 { + match self.bits { + 0 => Wupdc7::Interrupt, + 1 => Wupdc7::DmaReq, + 2 => Wupdc7::Trigger, + 3 => Wupdc7::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc7::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc7::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc7::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc7::Res + } +} +#[doc = "Field `WUPDC7` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc7W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc7, crate::Safe>; +impl<'a, REG> Wupdc7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc7::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc7::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc7::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc7::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc8 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc8) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc8 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc8 {} +#[doc = "Field `WUPDC8` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc8R = crate::FieldReader; +impl Wupdc8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc8 { + match self.bits { + 0 => Wupdc8::Interrupt, + 1 => Wupdc8::DmaReq, + 2 => Wupdc8::Trigger, + 3 => Wupdc8::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc8::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc8::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc8::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc8::Res + } +} +#[doc = "Field `WUPDC8` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc8W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc8, crate::Safe>; +impl<'a, REG> Wupdc8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc8::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc8::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc8::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc8::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc9 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc9) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc9 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc9 {} +#[doc = "Field `WUPDC9` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc9R = crate::FieldReader; +impl Wupdc9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc9 { + match self.bits { + 0 => Wupdc9::Interrupt, + 1 => Wupdc9::DmaReq, + 2 => Wupdc9::Trigger, + 3 => Wupdc9::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc9::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc9::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc9::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc9::Res + } +} +#[doc = "Field `WUPDC9` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc9W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc9, crate::Safe>; +impl<'a, REG> Wupdc9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc9::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc9::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc9::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc9::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc10 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc10) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc10 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc10 {} +#[doc = "Field `WUPDC10` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc10R = crate::FieldReader; +impl Wupdc10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc10 { + match self.bits { + 0 => Wupdc10::Interrupt, + 1 => Wupdc10::DmaReq, + 2 => Wupdc10::Trigger, + 3 => Wupdc10::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc10::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc10::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc10::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc10::Res + } +} +#[doc = "Field `WUPDC10` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc10W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc10, crate::Safe>; +impl<'a, REG> Wupdc10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc10::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc10::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc10::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc10::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc11 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc11) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc11 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc11 {} +#[doc = "Field `WUPDC11` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc11R = crate::FieldReader; +impl Wupdc11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc11 { + match self.bits { + 0 => Wupdc11::Interrupt, + 1 => Wupdc11::DmaReq, + 2 => Wupdc11::Trigger, + 3 => Wupdc11::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc11::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc11::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc11::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc11::Res + } +} +#[doc = "Field `WUPDC11` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc11W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc11, crate::Safe>; +impl<'a, REG> Wupdc11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc11::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc11::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc11::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc11::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc12 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc12) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc12 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc12 {} +#[doc = "Field `WUPDC12` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc12R = crate::FieldReader; +impl Wupdc12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc12 { + match self.bits { + 0 => Wupdc12::Interrupt, + 1 => Wupdc12::DmaReq, + 2 => Wupdc12::Trigger, + 3 => Wupdc12::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc12::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc12::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc12::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc12::Res + } +} +#[doc = "Field `WUPDC12` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc12W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc12, crate::Safe>; +impl<'a, REG> Wupdc12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc12::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc12::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc12::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc12::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc13 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc13) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc13 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc13 {} +#[doc = "Field `WUPDC13` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc13R = crate::FieldReader; +impl Wupdc13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc13 { + match self.bits { + 0 => Wupdc13::Interrupt, + 1 => Wupdc13::DmaReq, + 2 => Wupdc13::Trigger, + 3 => Wupdc13::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc13::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc13::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc13::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc13::Res + } +} +#[doc = "Field `WUPDC13` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc13W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc13, crate::Safe>; +impl<'a, REG> Wupdc13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc13::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc13::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc13::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc13::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc14 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc14) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc14 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc14 {} +#[doc = "Field `WUPDC14` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc14R = crate::FieldReader; +impl Wupdc14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc14 { + match self.bits { + 0 => Wupdc14::Interrupt, + 1 => Wupdc14::DmaReq, + 2 => Wupdc14::Trigger, + 3 => Wupdc14::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc14::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc14::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc14::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc14::Res + } +} +#[doc = "Field `WUPDC14` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc14W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc14, crate::Safe>; +impl<'a, REG> Wupdc14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc14::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc14::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc14::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc14::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc15 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc15) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc15 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc15 {} +#[doc = "Field `WUPDC15` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc15R = crate::FieldReader; +impl Wupdc15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc15 { + match self.bits { + 0 => Wupdc15::Interrupt, + 1 => Wupdc15::DmaReq, + 2 => Wupdc15::Trigger, + 3 => Wupdc15::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc15::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc15::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc15::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc15::Res + } +} +#[doc = "Field `WUPDC15` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc15W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc15, crate::Safe>; +impl<'a, REG> Wupdc15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc15::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc15::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc15::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc15::Res) + } +} +impl R { + #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc0(&self) -> Wupdc0R { + Wupdc0R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc1(&self) -> Wupdc1R { + Wupdc1R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc2(&self) -> Wupdc2R { + Wupdc2R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc3(&self) -> Wupdc3R { + Wupdc3R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc4(&self) -> Wupdc4R { + Wupdc4R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc5(&self) -> Wupdc5R { + Wupdc5R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc6(&self) -> Wupdc6R { + Wupdc6R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc7(&self) -> Wupdc7R { + Wupdc7R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc8(&self) -> Wupdc8R { + Wupdc8R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc9(&self) -> Wupdc9R { + Wupdc9R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc10(&self) -> Wupdc10R { + Wupdc10R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc11(&self) -> Wupdc11R { + Wupdc11R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc12(&self) -> Wupdc12R { + Wupdc12R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc13(&self) -> Wupdc13R { + Wupdc13R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc14(&self) -> Wupdc14R { + Wupdc14R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc15(&self) -> Wupdc15R { + Wupdc15R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc0(&mut self) -> Wupdc0W { + Wupdc0W::new(self, 0) + } + #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc1(&mut self) -> Wupdc1W { + Wupdc1W::new(self, 2) + } + #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc2(&mut self) -> Wupdc2W { + Wupdc2W::new(self, 4) + } + #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc3(&mut self) -> Wupdc3W { + Wupdc3W::new(self, 6) + } + #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc4(&mut self) -> Wupdc4W { + Wupdc4W::new(self, 8) + } + #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc5(&mut self) -> Wupdc5W { + Wupdc5W::new(self, 10) + } + #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc6(&mut self) -> Wupdc6W { + Wupdc6W::new(self, 12) + } + #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc7(&mut self) -> Wupdc7W { + Wupdc7W::new(self, 14) + } + #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc8(&mut self) -> Wupdc8W { + Wupdc8W::new(self, 16) + } + #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc9(&mut self) -> Wupdc9W { + Wupdc9W::new(self, 18) + } + #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc10(&mut self) -> Wupdc10W { + Wupdc10W::new(self, 20) + } + #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc11(&mut self) -> Wupdc11W { + Wupdc11W::new(self, 22) + } + #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc12(&mut self) -> Wupdc12W { + Wupdc12W::new(self, 24) + } + #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc13(&mut self) -> Wupdc13W { + Wupdc13W::new(self, 26) + } + #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc14(&mut self) -> Wupdc14W { + Wupdc14W::new(self, 28) + } + #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc15(&mut self) -> Wupdc15W { + Wupdc15W::new(self, 30) + } +} +#[doc = "Pin DMA/Trigger Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pdc1Spec; +impl crate::RegisterSpec for Pdc1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdc1::R`](R) reader structure"] +impl crate::Readable for Pdc1Spec {} +#[doc = "`write(|w| ..)` method takes [`pdc1::W`](W) writer structure"] +impl crate::Writable for Pdc1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PDC1 to value 0"] +impl crate::Resettable for Pdc1Spec {} diff --git a/mcxa276-pac/src/wuu0/pdc2.rs b/mcxa276-pac/src/wuu0/pdc2.rs new file mode 100644 index 000000000..edbf74576 --- /dev/null +++ b/mcxa276-pac/src/wuu0/pdc2.rs @@ -0,0 +1,1557 @@ +#[doc = "Register `PDC2` reader"] +pub type R = crate::R; +#[doc = "Register `PDC2` writer"] +pub type W = crate::W; +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc16 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc16) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc16 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc16 {} +#[doc = "Field `WUPDC16` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc16R = crate::FieldReader; +impl Wupdc16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc16 { + match self.bits { + 0 => Wupdc16::Interrupt, + 1 => Wupdc16::DmaReq, + 2 => Wupdc16::Trigger, + 3 => Wupdc16::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc16::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc16::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc16::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc16::Res + } +} +#[doc = "Field `WUPDC16` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc16W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc16, crate::Safe>; +impl<'a, REG> Wupdc16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc16::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc16::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc16::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc16::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc17 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc17) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc17 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc17 {} +#[doc = "Field `WUPDC17` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc17R = crate::FieldReader; +impl Wupdc17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc17 { + match self.bits { + 0 => Wupdc17::Interrupt, + 1 => Wupdc17::DmaReq, + 2 => Wupdc17::Trigger, + 3 => Wupdc17::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc17::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc17::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc17::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc17::Res + } +} +#[doc = "Field `WUPDC17` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc17W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc17, crate::Safe>; +impl<'a, REG> Wupdc17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc17::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc17::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc17::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc17::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc18 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc18) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc18 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc18 {} +#[doc = "Field `WUPDC18` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc18R = crate::FieldReader; +impl Wupdc18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc18 { + match self.bits { + 0 => Wupdc18::Interrupt, + 1 => Wupdc18::DmaReq, + 2 => Wupdc18::Trigger, + 3 => Wupdc18::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc18::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc18::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc18::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc18::Res + } +} +#[doc = "Field `WUPDC18` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc18W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc18, crate::Safe>; +impl<'a, REG> Wupdc18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc18::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc18::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc18::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc18::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc19 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc19) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc19 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc19 {} +#[doc = "Field `WUPDC19` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc19R = crate::FieldReader; +impl Wupdc19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc19 { + match self.bits { + 0 => Wupdc19::Interrupt, + 1 => Wupdc19::DmaReq, + 2 => Wupdc19::Trigger, + 3 => Wupdc19::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc19::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc19::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc19::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc19::Res + } +} +#[doc = "Field `WUPDC19` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc19W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc19, crate::Safe>; +impl<'a, REG> Wupdc19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc19::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc19::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc19::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc19::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc20 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc20) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc20 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc20 {} +#[doc = "Field `WUPDC20` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc20R = crate::FieldReader; +impl Wupdc20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc20 { + match self.bits { + 0 => Wupdc20::Interrupt, + 1 => Wupdc20::DmaReq, + 2 => Wupdc20::Trigger, + 3 => Wupdc20::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc20::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc20::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc20::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc20::Res + } +} +#[doc = "Field `WUPDC20` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc20W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc20, crate::Safe>; +impl<'a, REG> Wupdc20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc20::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc20::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc20::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc20::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc21 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc21) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc21 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc21 {} +#[doc = "Field `WUPDC21` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc21R = crate::FieldReader; +impl Wupdc21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc21 { + match self.bits { + 0 => Wupdc21::Interrupt, + 1 => Wupdc21::DmaReq, + 2 => Wupdc21::Trigger, + 3 => Wupdc21::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc21::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc21::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc21::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc21::Res + } +} +#[doc = "Field `WUPDC21` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc21W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc21, crate::Safe>; +impl<'a, REG> Wupdc21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc21::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc21::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc21::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc21::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc22 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc22) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc22 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc22 {} +#[doc = "Field `WUPDC22` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc22R = crate::FieldReader; +impl Wupdc22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc22 { + match self.bits { + 0 => Wupdc22::Interrupt, + 1 => Wupdc22::DmaReq, + 2 => Wupdc22::Trigger, + 3 => Wupdc22::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc22::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc22::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc22::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc22::Res + } +} +#[doc = "Field `WUPDC22` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc22W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc22, crate::Safe>; +impl<'a, REG> Wupdc22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc22::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc22::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc22::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc22::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc23 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc23) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc23 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc23 {} +#[doc = "Field `WUPDC23` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc23R = crate::FieldReader; +impl Wupdc23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc23 { + match self.bits { + 0 => Wupdc23::Interrupt, + 1 => Wupdc23::DmaReq, + 2 => Wupdc23::Trigger, + 3 => Wupdc23::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc23::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc23::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc23::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc23::Res + } +} +#[doc = "Field `WUPDC23` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc23, crate::Safe>; +impl<'a, REG> Wupdc23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc23::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc23::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc23::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc23::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc24 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc24) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc24 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc24 {} +#[doc = "Field `WUPDC24` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc24R = crate::FieldReader; +impl Wupdc24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc24 { + match self.bits { + 0 => Wupdc24::Interrupt, + 1 => Wupdc24::DmaReq, + 2 => Wupdc24::Trigger, + 3 => Wupdc24::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc24::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc24::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc24::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc24::Res + } +} +#[doc = "Field `WUPDC24` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc24W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc24, crate::Safe>; +impl<'a, REG> Wupdc24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc24::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc24::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc24::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc24::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc25 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc25) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc25 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc25 {} +#[doc = "Field `WUPDC25` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc25R = crate::FieldReader; +impl Wupdc25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc25 { + match self.bits { + 0 => Wupdc25::Interrupt, + 1 => Wupdc25::DmaReq, + 2 => Wupdc25::Trigger, + 3 => Wupdc25::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc25::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc25::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc25::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc25::Res + } +} +#[doc = "Field `WUPDC25` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc25W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc25, crate::Safe>; +impl<'a, REG> Wupdc25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc25::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc25::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc25::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc25::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc26 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc26) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc26 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc26 {} +#[doc = "Field `WUPDC26` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc26R = crate::FieldReader; +impl Wupdc26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc26 { + match self.bits { + 0 => Wupdc26::Interrupt, + 1 => Wupdc26::DmaReq, + 2 => Wupdc26::Trigger, + 3 => Wupdc26::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc26::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc26::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc26::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc26::Res + } +} +#[doc = "Field `WUPDC26` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc26W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc26, crate::Safe>; +impl<'a, REG> Wupdc26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc26::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc26::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc26::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc26::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc27 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc27) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc27 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc27 {} +#[doc = "Field `WUPDC27` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc27R = crate::FieldReader; +impl Wupdc27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc27 { + match self.bits { + 0 => Wupdc27::Interrupt, + 1 => Wupdc27::DmaReq, + 2 => Wupdc27::Trigger, + 3 => Wupdc27::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc27::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc27::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc27::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc27::Res + } +} +#[doc = "Field `WUPDC27` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc27W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc27, crate::Safe>; +impl<'a, REG> Wupdc27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc27::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc27::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc27::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc27::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc28 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc28) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc28 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc28 {} +#[doc = "Field `WUPDC28` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc28R = crate::FieldReader; +impl Wupdc28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc28 { + match self.bits { + 0 => Wupdc28::Interrupt, + 1 => Wupdc28::DmaReq, + 2 => Wupdc28::Trigger, + 3 => Wupdc28::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc28::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc28::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc28::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc28::Res + } +} +#[doc = "Field `WUPDC28` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc28W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc28, crate::Safe>; +impl<'a, REG> Wupdc28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc28::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc28::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc28::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc28::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc29 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc29) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc29 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc29 {} +#[doc = "Field `WUPDC29` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc29R = crate::FieldReader; +impl Wupdc29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc29 { + match self.bits { + 0 => Wupdc29::Interrupt, + 1 => Wupdc29::DmaReq, + 2 => Wupdc29::Trigger, + 3 => Wupdc29::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc29::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc29::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc29::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc29::Res + } +} +#[doc = "Field `WUPDC29` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc29W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc29, crate::Safe>; +impl<'a, REG> Wupdc29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc29::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc29::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc29::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc29::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc30 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc30) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc30 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc30 {} +#[doc = "Field `WUPDC30` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc30R = crate::FieldReader; +impl Wupdc30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc30 { + match self.bits { + 0 => Wupdc30::Interrupt, + 1 => Wupdc30::DmaReq, + 2 => Wupdc30::Trigger, + 3 => Wupdc30::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc30::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc30::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc30::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc30::Res + } +} +#[doc = "Field `WUPDC30` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc30W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc30, crate::Safe>; +impl<'a, REG> Wupdc30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc30::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc30::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc30::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc30::Res) + } +} +#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupdc31 { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: DMA request"] + DmaReq = 1, + #[doc = "2: Trigger event"] + Trigger = 2, + #[doc = "3: Reserved"] + Res = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupdc31) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupdc31 { + type Ux = u8; +} +impl crate::IsEnum for Wupdc31 {} +#[doc = "Field `WUPDC31` reader - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc31R = crate::FieldReader; +impl Wupdc31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupdc31 { + match self.bits { + 0 => Wupdc31::Interrupt, + 1 => Wupdc31::DmaReq, + 2 => Wupdc31::Trigger, + 3 => Wupdc31::Res, + _ => unreachable!(), + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wupdc31::Interrupt + } + #[doc = "DMA request"] + #[inline(always)] + pub fn is_dma_req(&self) -> bool { + *self == Wupdc31::DmaReq + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn is_trigger(&self) -> bool { + *self == Wupdc31::Trigger + } + #[doc = "Reserved"] + #[inline(always)] + pub fn is_res(&self) -> bool { + *self == Wupdc31::Res + } +} +#[doc = "Field `WUPDC31` writer - Wake-up Pin Configuration for WUU_Pn"] +pub type Wupdc31W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc31, crate::Safe>; +impl<'a, REG> Wupdc31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wupdc31::Interrupt) + } + #[doc = "DMA request"] + #[inline(always)] + pub fn dma_req(self) -> &'a mut crate::W { + self.variant(Wupdc31::DmaReq) + } + #[doc = "Trigger event"] + #[inline(always)] + pub fn trigger(self) -> &'a mut crate::W { + self.variant(Wupdc31::Trigger) + } + #[doc = "Reserved"] + #[inline(always)] + pub fn res(self) -> &'a mut crate::W { + self.variant(Wupdc31::Res) + } +} +impl R { + #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc16(&self) -> Wupdc16R { + Wupdc16R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc17(&self) -> Wupdc17R { + Wupdc17R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc18(&self) -> Wupdc18R { + Wupdc18R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc19(&self) -> Wupdc19R { + Wupdc19R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc20(&self) -> Wupdc20R { + Wupdc20R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc21(&self) -> Wupdc21R { + Wupdc21R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc22(&self) -> Wupdc22R { + Wupdc22R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc23(&self) -> Wupdc23R { + Wupdc23R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc24(&self) -> Wupdc24R { + Wupdc24R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc25(&self) -> Wupdc25R { + Wupdc25R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc26(&self) -> Wupdc26R { + Wupdc26R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc27(&self) -> Wupdc27R { + Wupdc27R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc28(&self) -> Wupdc28R { + Wupdc28R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc29(&self) -> Wupdc29R { + Wupdc29R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc30(&self) -> Wupdc30R { + Wupdc30R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc31(&self) -> Wupdc31R { + Wupdc31R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc16(&mut self) -> Wupdc16W { + Wupdc16W::new(self, 0) + } + #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc17(&mut self) -> Wupdc17W { + Wupdc17W::new(self, 2) + } + #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc18(&mut self) -> Wupdc18W { + Wupdc18W::new(self, 4) + } + #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc19(&mut self) -> Wupdc19W { + Wupdc19W::new(self, 6) + } + #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc20(&mut self) -> Wupdc20W { + Wupdc20W::new(self, 8) + } + #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc21(&mut self) -> Wupdc21W { + Wupdc21W::new(self, 10) + } + #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc22(&mut self) -> Wupdc22W { + Wupdc22W::new(self, 12) + } + #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc23(&mut self) -> Wupdc23W { + Wupdc23W::new(self, 14) + } + #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc24(&mut self) -> Wupdc24W { + Wupdc24W::new(self, 16) + } + #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc25(&mut self) -> Wupdc25W { + Wupdc25W::new(self, 18) + } + #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc26(&mut self) -> Wupdc26W { + Wupdc26W::new(self, 20) + } + #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc27(&mut self) -> Wupdc27W { + Wupdc27W::new(self, 22) + } + #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc28(&mut self) -> Wupdc28W { + Wupdc28W::new(self, 24) + } + #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc29(&mut self) -> Wupdc29W { + Wupdc29W::new(self, 26) + } + #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc30(&mut self) -> Wupdc30W { + Wupdc30W::new(self, 28) + } + #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupdc31(&mut self) -> Wupdc31W { + Wupdc31W::new(self, 30) + } +} +#[doc = "Pin DMA/Trigger Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pdc2Spec; +impl crate::RegisterSpec for Pdc2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdc2::R`](R) reader structure"] +impl crate::Readable for Pdc2Spec {} +#[doc = "`write(|w| ..)` method takes [`pdc2::W`](W) writer structure"] +impl crate::Writable for Pdc2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PDC2 to value 0"] +impl crate::Resettable for Pdc2Spec {} diff --git a/mcxa276-pac/src/wuu0/pe1.rs b/mcxa276-pac/src/wuu0/pe1.rs new file mode 100644 index 000000000..186cdb3fc --- /dev/null +++ b/mcxa276-pac/src/wuu0/pe1.rs @@ -0,0 +1,1557 @@ +#[doc = "Register `PE1` reader"] +pub type R = crate::R; +#[doc = "Register `PE1` writer"] +pub type W = crate::W; +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe0 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe0 { + type Ux = u8; +} +impl crate::IsEnum for Wupe0 {} +#[doc = "Field `WUPE0` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe0R = crate::FieldReader; +impl Wupe0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe0 { + match self.bits { + 0 => Wupe0::Disable, + 1 => Wupe0::EnRiseHi, + 2 => Wupe0::EnFallLo, + 3 => Wupe0::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe0::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe0::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe0::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe0::EnAny + } +} +#[doc = "Field `WUPE0` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe0, crate::Safe>; +impl<'a, REG> Wupe0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe0::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe0::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe0::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe0::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe1 { + type Ux = u8; +} +impl crate::IsEnum for Wupe1 {} +#[doc = "Field `WUPE1` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe1R = crate::FieldReader; +impl Wupe1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe1 { + match self.bits { + 0 => Wupe1::Disable, + 1 => Wupe1::EnRiseHi, + 2 => Wupe1::EnFallLo, + 3 => Wupe1::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe1::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe1::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe1::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe1::EnAny + } +} +#[doc = "Field `WUPE1` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe1, crate::Safe>; +impl<'a, REG> Wupe1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe1::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe1::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe1::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe1::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe2 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe2 { + type Ux = u8; +} +impl crate::IsEnum for Wupe2 {} +#[doc = "Field `WUPE2` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe2R = crate::FieldReader; +impl Wupe2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe2 { + match self.bits { + 0 => Wupe2::Disable, + 1 => Wupe2::EnRiseHi, + 2 => Wupe2::EnFallLo, + 3 => Wupe2::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe2::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe2::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe2::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe2::EnAny + } +} +#[doc = "Field `WUPE2` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe2, crate::Safe>; +impl<'a, REG> Wupe2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe2::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe2::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe2::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe2::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe3 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe3 { + type Ux = u8; +} +impl crate::IsEnum for Wupe3 {} +#[doc = "Field `WUPE3` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe3R = crate::FieldReader; +impl Wupe3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe3 { + match self.bits { + 0 => Wupe3::Disable, + 1 => Wupe3::EnRiseHi, + 2 => Wupe3::EnFallLo, + 3 => Wupe3::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe3::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe3::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe3::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe3::EnAny + } +} +#[doc = "Field `WUPE3` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe3W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe3, crate::Safe>; +impl<'a, REG> Wupe3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe3::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe3::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe3::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe3::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe4 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe4) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe4 { + type Ux = u8; +} +impl crate::IsEnum for Wupe4 {} +#[doc = "Field `WUPE4` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe4R = crate::FieldReader; +impl Wupe4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe4 { + match self.bits { + 0 => Wupe4::Disable, + 1 => Wupe4::EnRiseHi, + 2 => Wupe4::EnFallLo, + 3 => Wupe4::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe4::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe4::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe4::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe4::EnAny + } +} +#[doc = "Field `WUPE4` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe4W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe4, crate::Safe>; +impl<'a, REG> Wupe4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe4::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe4::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe4::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe4::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe5 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe5) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe5 { + type Ux = u8; +} +impl crate::IsEnum for Wupe5 {} +#[doc = "Field `WUPE5` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe5R = crate::FieldReader; +impl Wupe5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe5 { + match self.bits { + 0 => Wupe5::Disable, + 1 => Wupe5::EnRiseHi, + 2 => Wupe5::EnFallLo, + 3 => Wupe5::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe5::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe5::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe5::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe5::EnAny + } +} +#[doc = "Field `WUPE5` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe5W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe5, crate::Safe>; +impl<'a, REG> Wupe5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe5::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe5::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe5::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe5::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe6 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe6) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe6 { + type Ux = u8; +} +impl crate::IsEnum for Wupe6 {} +#[doc = "Field `WUPE6` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe6R = crate::FieldReader; +impl Wupe6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe6 { + match self.bits { + 0 => Wupe6::Disable, + 1 => Wupe6::EnRiseHi, + 2 => Wupe6::EnFallLo, + 3 => Wupe6::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe6::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe6::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe6::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe6::EnAny + } +} +#[doc = "Field `WUPE6` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe6W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe6, crate::Safe>; +impl<'a, REG> Wupe6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe6::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe6::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe6::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe6::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe7 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe7) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe7 { + type Ux = u8; +} +impl crate::IsEnum for Wupe7 {} +#[doc = "Field `WUPE7` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe7R = crate::FieldReader; +impl Wupe7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe7 { + match self.bits { + 0 => Wupe7::Disable, + 1 => Wupe7::EnRiseHi, + 2 => Wupe7::EnFallLo, + 3 => Wupe7::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe7::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe7::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe7::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe7::EnAny + } +} +#[doc = "Field `WUPE7` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe7W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe7, crate::Safe>; +impl<'a, REG> Wupe7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe7::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe7::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe7::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe7::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe8 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe8) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe8 { + type Ux = u8; +} +impl crate::IsEnum for Wupe8 {} +#[doc = "Field `WUPE8` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe8R = crate::FieldReader; +impl Wupe8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe8 { + match self.bits { + 0 => Wupe8::Disable, + 1 => Wupe8::EnRiseHi, + 2 => Wupe8::EnFallLo, + 3 => Wupe8::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe8::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe8::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe8::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe8::EnAny + } +} +#[doc = "Field `WUPE8` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe8W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe8, crate::Safe>; +impl<'a, REG> Wupe8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe8::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe8::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe8::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe8::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe9 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe9) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe9 { + type Ux = u8; +} +impl crate::IsEnum for Wupe9 {} +#[doc = "Field `WUPE9` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe9R = crate::FieldReader; +impl Wupe9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe9 { + match self.bits { + 0 => Wupe9::Disable, + 1 => Wupe9::EnRiseHi, + 2 => Wupe9::EnFallLo, + 3 => Wupe9::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe9::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe9::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe9::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe9::EnAny + } +} +#[doc = "Field `WUPE9` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe9W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe9, crate::Safe>; +impl<'a, REG> Wupe9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe9::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe9::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe9::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe9::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe10 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe10) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe10 { + type Ux = u8; +} +impl crate::IsEnum for Wupe10 {} +#[doc = "Field `WUPE10` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe10R = crate::FieldReader; +impl Wupe10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe10 { + match self.bits { + 0 => Wupe10::Disable, + 1 => Wupe10::EnRiseHi, + 2 => Wupe10::EnFallLo, + 3 => Wupe10::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe10::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe10::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe10::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe10::EnAny + } +} +#[doc = "Field `WUPE10` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe10W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe10, crate::Safe>; +impl<'a, REG> Wupe10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe10::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe10::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe10::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe10::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe11 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe11) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe11 { + type Ux = u8; +} +impl crate::IsEnum for Wupe11 {} +#[doc = "Field `WUPE11` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe11R = crate::FieldReader; +impl Wupe11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe11 { + match self.bits { + 0 => Wupe11::Disable, + 1 => Wupe11::EnRiseHi, + 2 => Wupe11::EnFallLo, + 3 => Wupe11::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe11::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe11::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe11::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe11::EnAny + } +} +#[doc = "Field `WUPE11` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe11W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe11, crate::Safe>; +impl<'a, REG> Wupe11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe11::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe11::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe11::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe11::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe12 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe12) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe12 { + type Ux = u8; +} +impl crate::IsEnum for Wupe12 {} +#[doc = "Field `WUPE12` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe12R = crate::FieldReader; +impl Wupe12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe12 { + match self.bits { + 0 => Wupe12::Disable, + 1 => Wupe12::EnRiseHi, + 2 => Wupe12::EnFallLo, + 3 => Wupe12::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe12::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe12::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe12::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe12::EnAny + } +} +#[doc = "Field `WUPE12` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe12W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe12, crate::Safe>; +impl<'a, REG> Wupe12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe12::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe12::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe12::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe12::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe13 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe13) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe13 { + type Ux = u8; +} +impl crate::IsEnum for Wupe13 {} +#[doc = "Field `WUPE13` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe13R = crate::FieldReader; +impl Wupe13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe13 { + match self.bits { + 0 => Wupe13::Disable, + 1 => Wupe13::EnRiseHi, + 2 => Wupe13::EnFallLo, + 3 => Wupe13::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe13::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe13::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe13::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe13::EnAny + } +} +#[doc = "Field `WUPE13` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe13W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe13, crate::Safe>; +impl<'a, REG> Wupe13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe13::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe13::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe13::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe13::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe14 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe14) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe14 { + type Ux = u8; +} +impl crate::IsEnum for Wupe14 {} +#[doc = "Field `WUPE14` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe14R = crate::FieldReader; +impl Wupe14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe14 { + match self.bits { + 0 => Wupe14::Disable, + 1 => Wupe14::EnRiseHi, + 2 => Wupe14::EnFallLo, + 3 => Wupe14::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe14::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe14::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe14::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe14::EnAny + } +} +#[doc = "Field `WUPE14` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe14W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe14, crate::Safe>; +impl<'a, REG> Wupe14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe14::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe14::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe14::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe14::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe15 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe15) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe15 { + type Ux = u8; +} +impl crate::IsEnum for Wupe15 {} +#[doc = "Field `WUPE15` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe15R = crate::FieldReader; +impl Wupe15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe15 { + match self.bits { + 0 => Wupe15::Disable, + 1 => Wupe15::EnRiseHi, + 2 => Wupe15::EnFallLo, + 3 => Wupe15::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe15::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe15::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe15::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe15::EnAny + } +} +#[doc = "Field `WUPE15` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe15W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe15, crate::Safe>; +impl<'a, REG> Wupe15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe15::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe15::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe15::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe15::EnAny) + } +} +impl R { + #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe0(&self) -> Wupe0R { + Wupe0R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe1(&self) -> Wupe1R { + Wupe1R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe2(&self) -> Wupe2R { + Wupe2R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe3(&self) -> Wupe3R { + Wupe3R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe4(&self) -> Wupe4R { + Wupe4R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe5(&self) -> Wupe5R { + Wupe5R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe6(&self) -> Wupe6R { + Wupe6R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe7(&self) -> Wupe7R { + Wupe7R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe8(&self) -> Wupe8R { + Wupe8R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe9(&self) -> Wupe9R { + Wupe9R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe10(&self) -> Wupe10R { + Wupe10R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe11(&self) -> Wupe11R { + Wupe11R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe12(&self) -> Wupe12R { + Wupe12R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe13(&self) -> Wupe13R { + Wupe13R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe14(&self) -> Wupe14R { + Wupe14R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe15(&self) -> Wupe15R { + Wupe15R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe0(&mut self) -> Wupe0W { + Wupe0W::new(self, 0) + } + #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe1(&mut self) -> Wupe1W { + Wupe1W::new(self, 2) + } + #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe2(&mut self) -> Wupe2W { + Wupe2W::new(self, 4) + } + #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe3(&mut self) -> Wupe3W { + Wupe3W::new(self, 6) + } + #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe4(&mut self) -> Wupe4W { + Wupe4W::new(self, 8) + } + #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe5(&mut self) -> Wupe5W { + Wupe5W::new(self, 10) + } + #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe6(&mut self) -> Wupe6W { + Wupe6W::new(self, 12) + } + #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe7(&mut self) -> Wupe7W { + Wupe7W::new(self, 14) + } + #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe8(&mut self) -> Wupe8W { + Wupe8W::new(self, 16) + } + #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe9(&mut self) -> Wupe9W { + Wupe9W::new(self, 18) + } + #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe10(&mut self) -> Wupe10W { + Wupe10W::new(self, 20) + } + #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe11(&mut self) -> Wupe11W { + Wupe11W::new(self, 22) + } + #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe12(&mut self) -> Wupe12W { + Wupe12W::new(self, 24) + } + #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe13(&mut self) -> Wupe13W { + Wupe13W::new(self, 26) + } + #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe14(&mut self) -> Wupe14W { + Wupe14W::new(self, 28) + } + #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe15(&mut self) -> Wupe15W { + Wupe15W::new(self, 30) + } +} +#[doc = "Pin Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pe1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pe1Spec; +impl crate::RegisterSpec for Pe1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pe1::R`](R) reader structure"] +impl crate::Readable for Pe1Spec {} +#[doc = "`write(|w| ..)` method takes [`pe1::W`](W) writer structure"] +impl crate::Writable for Pe1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PE1 to value 0"] +impl crate::Resettable for Pe1Spec {} diff --git a/mcxa276-pac/src/wuu0/pe2.rs b/mcxa276-pac/src/wuu0/pe2.rs new file mode 100644 index 000000000..1ff9b579c --- /dev/null +++ b/mcxa276-pac/src/wuu0/pe2.rs @@ -0,0 +1,1557 @@ +#[doc = "Register `PE2` reader"] +pub type R = crate::R; +#[doc = "Register `PE2` writer"] +pub type W = crate::W; +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe16 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe16) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe16 { + type Ux = u8; +} +impl crate::IsEnum for Wupe16 {} +#[doc = "Field `WUPE16` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe16R = crate::FieldReader; +impl Wupe16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe16 { + match self.bits { + 0 => Wupe16::Disable, + 1 => Wupe16::EnRiseHi, + 2 => Wupe16::EnFallLo, + 3 => Wupe16::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe16::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe16::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe16::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe16::EnAny + } +} +#[doc = "Field `WUPE16` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe16W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe16, crate::Safe>; +impl<'a, REG> Wupe16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe16::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe16::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe16::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe16::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe17 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe17) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe17 { + type Ux = u8; +} +impl crate::IsEnum for Wupe17 {} +#[doc = "Field `WUPE17` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe17R = crate::FieldReader; +impl Wupe17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe17 { + match self.bits { + 0 => Wupe17::Disable, + 1 => Wupe17::EnRiseHi, + 2 => Wupe17::EnFallLo, + 3 => Wupe17::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe17::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe17::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe17::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe17::EnAny + } +} +#[doc = "Field `WUPE17` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe17W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe17, crate::Safe>; +impl<'a, REG> Wupe17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe17::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe17::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe17::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe17::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe18 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe18) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe18 { + type Ux = u8; +} +impl crate::IsEnum for Wupe18 {} +#[doc = "Field `WUPE18` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe18R = crate::FieldReader; +impl Wupe18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe18 { + match self.bits { + 0 => Wupe18::Disable, + 1 => Wupe18::EnRiseHi, + 2 => Wupe18::EnFallLo, + 3 => Wupe18::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe18::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe18::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe18::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe18::EnAny + } +} +#[doc = "Field `WUPE18` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe18W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe18, crate::Safe>; +impl<'a, REG> Wupe18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe18::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe18::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe18::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe18::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe19 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe19) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe19 { + type Ux = u8; +} +impl crate::IsEnum for Wupe19 {} +#[doc = "Field `WUPE19` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe19R = crate::FieldReader; +impl Wupe19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe19 { + match self.bits { + 0 => Wupe19::Disable, + 1 => Wupe19::EnRiseHi, + 2 => Wupe19::EnFallLo, + 3 => Wupe19::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe19::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe19::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe19::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe19::EnAny + } +} +#[doc = "Field `WUPE19` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe19W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe19, crate::Safe>; +impl<'a, REG> Wupe19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe19::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe19::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe19::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe19::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe20 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe20) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe20 { + type Ux = u8; +} +impl crate::IsEnum for Wupe20 {} +#[doc = "Field `WUPE20` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe20R = crate::FieldReader; +impl Wupe20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe20 { + match self.bits { + 0 => Wupe20::Disable, + 1 => Wupe20::EnRiseHi, + 2 => Wupe20::EnFallLo, + 3 => Wupe20::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe20::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe20::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe20::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe20::EnAny + } +} +#[doc = "Field `WUPE20` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe20W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe20, crate::Safe>; +impl<'a, REG> Wupe20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe20::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe20::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe20::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe20::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe21 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe21) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe21 { + type Ux = u8; +} +impl crate::IsEnum for Wupe21 {} +#[doc = "Field `WUPE21` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe21R = crate::FieldReader; +impl Wupe21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe21 { + match self.bits { + 0 => Wupe21::Disable, + 1 => Wupe21::EnRiseHi, + 2 => Wupe21::EnFallLo, + 3 => Wupe21::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe21::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe21::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe21::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe21::EnAny + } +} +#[doc = "Field `WUPE21` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe21W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe21, crate::Safe>; +impl<'a, REG> Wupe21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe21::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe21::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe21::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe21::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe22 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe22) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe22 { + type Ux = u8; +} +impl crate::IsEnum for Wupe22 {} +#[doc = "Field `WUPE22` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe22R = crate::FieldReader; +impl Wupe22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe22 { + match self.bits { + 0 => Wupe22::Disable, + 1 => Wupe22::EnRiseHi, + 2 => Wupe22::EnFallLo, + 3 => Wupe22::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe22::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe22::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe22::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe22::EnAny + } +} +#[doc = "Field `WUPE22` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe22W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe22, crate::Safe>; +impl<'a, REG> Wupe22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe22::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe22::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe22::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe22::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe23 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe23) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe23 { + type Ux = u8; +} +impl crate::IsEnum for Wupe23 {} +#[doc = "Field `WUPE23` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe23R = crate::FieldReader; +impl Wupe23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe23 { + match self.bits { + 0 => Wupe23::Disable, + 1 => Wupe23::EnRiseHi, + 2 => Wupe23::EnFallLo, + 3 => Wupe23::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe23::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe23::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe23::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe23::EnAny + } +} +#[doc = "Field `WUPE23` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe23, crate::Safe>; +impl<'a, REG> Wupe23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe23::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe23::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe23::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe23::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe24 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe24) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe24 { + type Ux = u8; +} +impl crate::IsEnum for Wupe24 {} +#[doc = "Field `WUPE24` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe24R = crate::FieldReader; +impl Wupe24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe24 { + match self.bits { + 0 => Wupe24::Disable, + 1 => Wupe24::EnRiseHi, + 2 => Wupe24::EnFallLo, + 3 => Wupe24::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe24::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe24::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe24::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe24::EnAny + } +} +#[doc = "Field `WUPE24` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe24W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe24, crate::Safe>; +impl<'a, REG> Wupe24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe24::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe24::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe24::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe24::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe25 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe25) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe25 { + type Ux = u8; +} +impl crate::IsEnum for Wupe25 {} +#[doc = "Field `WUPE25` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe25R = crate::FieldReader; +impl Wupe25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe25 { + match self.bits { + 0 => Wupe25::Disable, + 1 => Wupe25::EnRiseHi, + 2 => Wupe25::EnFallLo, + 3 => Wupe25::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe25::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe25::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe25::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe25::EnAny + } +} +#[doc = "Field `WUPE25` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe25W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe25, crate::Safe>; +impl<'a, REG> Wupe25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe25::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe25::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe25::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe25::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe26 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe26) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe26 { + type Ux = u8; +} +impl crate::IsEnum for Wupe26 {} +#[doc = "Field `WUPE26` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe26R = crate::FieldReader; +impl Wupe26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe26 { + match self.bits { + 0 => Wupe26::Disable, + 1 => Wupe26::EnRiseHi, + 2 => Wupe26::EnFallLo, + 3 => Wupe26::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe26::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe26::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe26::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe26::EnAny + } +} +#[doc = "Field `WUPE26` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe26W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe26, crate::Safe>; +impl<'a, REG> Wupe26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe26::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe26::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe26::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe26::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe27 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe27) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe27 { + type Ux = u8; +} +impl crate::IsEnum for Wupe27 {} +#[doc = "Field `WUPE27` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe27R = crate::FieldReader; +impl Wupe27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe27 { + match self.bits { + 0 => Wupe27::Disable, + 1 => Wupe27::EnRiseHi, + 2 => Wupe27::EnFallLo, + 3 => Wupe27::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe27::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe27::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe27::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe27::EnAny + } +} +#[doc = "Field `WUPE27` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe27W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe27, crate::Safe>; +impl<'a, REG> Wupe27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe27::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe27::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe27::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe27::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe28 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe28) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe28 { + type Ux = u8; +} +impl crate::IsEnum for Wupe28 {} +#[doc = "Field `WUPE28` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe28R = crate::FieldReader; +impl Wupe28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe28 { + match self.bits { + 0 => Wupe28::Disable, + 1 => Wupe28::EnRiseHi, + 2 => Wupe28::EnFallLo, + 3 => Wupe28::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe28::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe28::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe28::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe28::EnAny + } +} +#[doc = "Field `WUPE28` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe28W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe28, crate::Safe>; +impl<'a, REG> Wupe28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe28::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe28::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe28::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe28::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe29 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe29) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe29 { + type Ux = u8; +} +impl crate::IsEnum for Wupe29 {} +#[doc = "Field `WUPE29` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe29R = crate::FieldReader; +impl Wupe29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe29 { + match self.bits { + 0 => Wupe29::Disable, + 1 => Wupe29::EnRiseHi, + 2 => Wupe29::EnFallLo, + 3 => Wupe29::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe29::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe29::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe29::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe29::EnAny + } +} +#[doc = "Field `WUPE29` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe29W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe29, crate::Safe>; +impl<'a, REG> Wupe29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe29::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe29::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe29::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe29::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe30 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe30) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe30 { + type Ux = u8; +} +impl crate::IsEnum for Wupe30 {} +#[doc = "Field `WUPE30` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe30R = crate::FieldReader; +impl Wupe30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe30 { + match self.bits { + 0 => Wupe30::Disable, + 1 => Wupe30::EnRiseHi, + 2 => Wupe30::EnFallLo, + 3 => Wupe30::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe30::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe30::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe30::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe30::EnAny + } +} +#[doc = "Field `WUPE30` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe30W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe30, crate::Safe>; +impl<'a, REG> Wupe30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe30::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe30::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe30::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe30::EnAny) + } +} +#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wupe31 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable (detect on rising edge or high level)"] + EnRiseHi = 1, + #[doc = "2: Enable (detect on falling edge or low level)"] + EnFallLo = 2, + #[doc = "3: Enable (detect on any edge)"] + EnAny = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wupe31) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wupe31 { + type Ux = u8; +} +impl crate::IsEnum for Wupe31 {} +#[doc = "Field `WUPE31` reader - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe31R = crate::FieldReader; +impl Wupe31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupe31 { + match self.bits { + 0 => Wupe31::Disable, + 1 => Wupe31::EnRiseHi, + 2 => Wupe31::EnFallLo, + 3 => Wupe31::EnAny, + _ => unreachable!(), + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wupe31::Disable + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn is_en_rise_hi(&self) -> bool { + *self == Wupe31::EnRiseHi + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn is_en_fall_lo(&self) -> bool { + *self == Wupe31::EnFallLo + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn is_en_any(&self) -> bool { + *self == Wupe31::EnAny + } +} +#[doc = "Field `WUPE31` writer - Wake-up Pin Enable for WUU_Pn"] +pub type Wupe31W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe31, crate::Safe>; +impl<'a, REG> Wupe31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wupe31::Disable) + } + #[doc = "Enable (detect on rising edge or high level)"] + #[inline(always)] + pub fn en_rise_hi(self) -> &'a mut crate::W { + self.variant(Wupe31::EnRiseHi) + } + #[doc = "Enable (detect on falling edge or low level)"] + #[inline(always)] + pub fn en_fall_lo(self) -> &'a mut crate::W { + self.variant(Wupe31::EnFallLo) + } + #[doc = "Enable (detect on any edge)"] + #[inline(always)] + pub fn en_any(self) -> &'a mut crate::W { + self.variant(Wupe31::EnAny) + } +} +impl R { + #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe16(&self) -> Wupe16R { + Wupe16R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe17(&self) -> Wupe17R { + Wupe17R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe18(&self) -> Wupe18R { + Wupe18R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe19(&self) -> Wupe19R { + Wupe19R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe20(&self) -> Wupe20R { + Wupe20R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe21(&self) -> Wupe21R { + Wupe21R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe22(&self) -> Wupe22R { + Wupe22R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe23(&self) -> Wupe23R { + Wupe23R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe24(&self) -> Wupe24R { + Wupe24R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe25(&self) -> Wupe25R { + Wupe25R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe26(&self) -> Wupe26R { + Wupe26R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe27(&self) -> Wupe27R { + Wupe27R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe28(&self) -> Wupe28R { + Wupe28R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe29(&self) -> Wupe29R { + Wupe29R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe30(&self) -> Wupe30R { + Wupe30R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe31(&self) -> Wupe31R { + Wupe31R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe16(&mut self) -> Wupe16W { + Wupe16W::new(self, 0) + } + #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe17(&mut self) -> Wupe17W { + Wupe17W::new(self, 2) + } + #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe18(&mut self) -> Wupe18W { + Wupe18W::new(self, 4) + } + #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe19(&mut self) -> Wupe19W { + Wupe19W::new(self, 6) + } + #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe20(&mut self) -> Wupe20W { + Wupe20W::new(self, 8) + } + #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe21(&mut self) -> Wupe21W { + Wupe21W::new(self, 10) + } + #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe22(&mut self) -> Wupe22W { + Wupe22W::new(self, 12) + } + #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe23(&mut self) -> Wupe23W { + Wupe23W::new(self, 14) + } + #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe24(&mut self) -> Wupe24W { + Wupe24W::new(self, 16) + } + #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe25(&mut self) -> Wupe25W { + Wupe25W::new(self, 18) + } + #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe26(&mut self) -> Wupe26W { + Wupe26W::new(self, 20) + } + #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe27(&mut self) -> Wupe27W { + Wupe27W::new(self, 22) + } + #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe28(&mut self) -> Wupe28W { + Wupe28W::new(self, 24) + } + #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe29(&mut self) -> Wupe29W { + Wupe29W::new(self, 26) + } + #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe30(&mut self) -> Wupe30W { + Wupe30W::new(self, 28) + } + #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] + #[inline(always)] + pub fn wupe31(&mut self) -> Wupe31W { + Wupe31W::new(self, 30) + } +} +#[doc = "Pin Enable 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pe2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pe2Spec; +impl crate::RegisterSpec for Pe2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pe2::R`](R) reader structure"] +impl crate::Readable for Pe2Spec {} +#[doc = "`write(|w| ..)` method takes [`pe2::W`](W) writer structure"] +impl crate::Writable for Pe2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PE2 to value 0"] +impl crate::Resettable for Pe2Spec {} diff --git a/mcxa276-pac/src/wuu0/pf.rs b/mcxa276-pac/src/wuu0/pf.rs new file mode 100644 index 000000000..a3993eef6 --- /dev/null +++ b/mcxa276-pac/src/wuu0/pf.rs @@ -0,0 +1,2038 @@ +#[doc = "Register `PF` reader"] +pub type R = crate::R; +#[doc = "Register `PF` writer"] +pub type W = crate::W; +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf0 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF0` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf0R = crate::BitReader; +impl Wuf0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf0 { + match self.bits { + false => Wuf0::NoFlag, + true => Wuf0::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf0::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf0::Flag + } +} +#[doc = "Field `WUF0` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf0W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf0>; +impl<'a, REG> Wuf0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf0::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf0::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf1 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF1` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf1R = crate::BitReader; +impl Wuf1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf1 { + match self.bits { + false => Wuf1::NoFlag, + true => Wuf1::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf1::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf1::Flag + } +} +#[doc = "Field `WUF1` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf1W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf1>; +impl<'a, REG> Wuf1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf1::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf1::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf2 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF2` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf2R = crate::BitReader; +impl Wuf2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf2 { + match self.bits { + false => Wuf2::NoFlag, + true => Wuf2::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf2::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf2::Flag + } +} +#[doc = "Field `WUF2` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf2W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf2>; +impl<'a, REG> Wuf2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf2::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf2::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf3 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF3` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf3R = crate::BitReader; +impl Wuf3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf3 { + match self.bits { + false => Wuf3::NoFlag, + true => Wuf3::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf3::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf3::Flag + } +} +#[doc = "Field `WUF3` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf3W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf3>; +impl<'a, REG> Wuf3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf3::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf3::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf4 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF4` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf4R = crate::BitReader; +impl Wuf4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf4 { + match self.bits { + false => Wuf4::NoFlag, + true => Wuf4::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf4::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf4::Flag + } +} +#[doc = "Field `WUF4` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf4W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf4>; +impl<'a, REG> Wuf4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf4::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf4::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf5 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF5` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf5R = crate::BitReader; +impl Wuf5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf5 { + match self.bits { + false => Wuf5::NoFlag, + true => Wuf5::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf5::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf5::Flag + } +} +#[doc = "Field `WUF5` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf5W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf5>; +impl<'a, REG> Wuf5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf5::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf5::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf6 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF6` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf6R = crate::BitReader; +impl Wuf6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf6 { + match self.bits { + false => Wuf6::NoFlag, + true => Wuf6::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf6::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf6::Flag + } +} +#[doc = "Field `WUF6` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf6W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf6>; +impl<'a, REG> Wuf6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf6::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf6::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf7 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF7` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf7R = crate::BitReader; +impl Wuf7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf7 { + match self.bits { + false => Wuf7::NoFlag, + true => Wuf7::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf7::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf7::Flag + } +} +#[doc = "Field `WUF7` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf7W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf7>; +impl<'a, REG> Wuf7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf7::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf7::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf8 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF8` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf8R = crate::BitReader; +impl Wuf8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf8 { + match self.bits { + false => Wuf8::NoFlag, + true => Wuf8::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf8::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf8::Flag + } +} +#[doc = "Field `WUF8` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf8W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf8>; +impl<'a, REG> Wuf8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf8::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf8::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf9 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF9` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf9R = crate::BitReader; +impl Wuf9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf9 { + match self.bits { + false => Wuf9::NoFlag, + true => Wuf9::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf9::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf9::Flag + } +} +#[doc = "Field `WUF9` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf9W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf9>; +impl<'a, REG> Wuf9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf9::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf9::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf10 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF10` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf10R = crate::BitReader; +impl Wuf10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf10 { + match self.bits { + false => Wuf10::NoFlag, + true => Wuf10::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf10::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf10::Flag + } +} +#[doc = "Field `WUF10` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf10W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf10>; +impl<'a, REG> Wuf10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf10::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf10::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf11 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF11` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf11R = crate::BitReader; +impl Wuf11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf11 { + match self.bits { + false => Wuf11::NoFlag, + true => Wuf11::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf11::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf11::Flag + } +} +#[doc = "Field `WUF11` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf11W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf11>; +impl<'a, REG> Wuf11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf11::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf11::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf12 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF12` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf12R = crate::BitReader; +impl Wuf12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf12 { + match self.bits { + false => Wuf12::NoFlag, + true => Wuf12::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf12::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf12::Flag + } +} +#[doc = "Field `WUF12` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf12W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf12>; +impl<'a, REG> Wuf12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf12::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf12::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf13 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF13` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf13R = crate::BitReader; +impl Wuf13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf13 { + match self.bits { + false => Wuf13::NoFlag, + true => Wuf13::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf13::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf13::Flag + } +} +#[doc = "Field `WUF13` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf13W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf13>; +impl<'a, REG> Wuf13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf13::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf13::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf14 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF14` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf14R = crate::BitReader; +impl Wuf14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf14 { + match self.bits { + false => Wuf14::NoFlag, + true => Wuf14::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf14::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf14::Flag + } +} +#[doc = "Field `WUF14` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf14W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf14>; +impl<'a, REG> Wuf14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf14::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf14::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf15 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF15` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf15R = crate::BitReader; +impl Wuf15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf15 { + match self.bits { + false => Wuf15::NoFlag, + true => Wuf15::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf15::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf15::Flag + } +} +#[doc = "Field `WUF15` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf15W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf15>; +impl<'a, REG> Wuf15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf15::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf15::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf16 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF16` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf16R = crate::BitReader; +impl Wuf16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf16 { + match self.bits { + false => Wuf16::NoFlag, + true => Wuf16::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf16::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf16::Flag + } +} +#[doc = "Field `WUF16` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf16W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf16>; +impl<'a, REG> Wuf16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf16::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf16::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf17 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF17` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf17R = crate::BitReader; +impl Wuf17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf17 { + match self.bits { + false => Wuf17::NoFlag, + true => Wuf17::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf17::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf17::Flag + } +} +#[doc = "Field `WUF17` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf17W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf17>; +impl<'a, REG> Wuf17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf17::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf17::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf18 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF18` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf18R = crate::BitReader; +impl Wuf18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf18 { + match self.bits { + false => Wuf18::NoFlag, + true => Wuf18::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf18::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf18::Flag + } +} +#[doc = "Field `WUF18` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf18W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf18>; +impl<'a, REG> Wuf18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf18::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf18::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf19 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF19` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf19R = crate::BitReader; +impl Wuf19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf19 { + match self.bits { + false => Wuf19::NoFlag, + true => Wuf19::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf19::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf19::Flag + } +} +#[doc = "Field `WUF19` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf19W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf19>; +impl<'a, REG> Wuf19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf19::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf19::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf20 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF20` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf20R = crate::BitReader; +impl Wuf20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf20 { + match self.bits { + false => Wuf20::NoFlag, + true => Wuf20::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf20::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf20::Flag + } +} +#[doc = "Field `WUF20` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf20W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf20>; +impl<'a, REG> Wuf20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf20::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf20::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf21 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF21` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf21R = crate::BitReader; +impl Wuf21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf21 { + match self.bits { + false => Wuf21::NoFlag, + true => Wuf21::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf21::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf21::Flag + } +} +#[doc = "Field `WUF21` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf21W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf21>; +impl<'a, REG> Wuf21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf21::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf21::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf22 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF22` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf22R = crate::BitReader; +impl Wuf22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf22 { + match self.bits { + false => Wuf22::NoFlag, + true => Wuf22::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf22::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf22::Flag + } +} +#[doc = "Field `WUF22` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf22W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf22>; +impl<'a, REG> Wuf22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf22::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf22::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf23 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF23` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf23R = crate::BitReader; +impl Wuf23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf23 { + match self.bits { + false => Wuf23::NoFlag, + true => Wuf23::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf23::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf23::Flag + } +} +#[doc = "Field `WUF23` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf23W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf23>; +impl<'a, REG> Wuf23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf23::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf23::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf24 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF24` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf24R = crate::BitReader; +impl Wuf24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf24 { + match self.bits { + false => Wuf24::NoFlag, + true => Wuf24::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf24::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf24::Flag + } +} +#[doc = "Field `WUF24` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf24W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf24>; +impl<'a, REG> Wuf24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf24::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf24::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf25 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF25` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf25R = crate::BitReader; +impl Wuf25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf25 { + match self.bits { + false => Wuf25::NoFlag, + true => Wuf25::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf25::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf25::Flag + } +} +#[doc = "Field `WUF25` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf25W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf25>; +impl<'a, REG> Wuf25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf25::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf25::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf26 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF26` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf26R = crate::BitReader; +impl Wuf26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf26 { + match self.bits { + false => Wuf26::NoFlag, + true => Wuf26::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf26::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf26::Flag + } +} +#[doc = "Field `WUF26` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf26W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf26>; +impl<'a, REG> Wuf26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf26::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf26::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf27 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF27` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf27R = crate::BitReader; +impl Wuf27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf27 { + match self.bits { + false => Wuf27::NoFlag, + true => Wuf27::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf27::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf27::Flag + } +} +#[doc = "Field `WUF27` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf27W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf27>; +impl<'a, REG> Wuf27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf27::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf27::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf28 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF28` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf28R = crate::BitReader; +impl Wuf28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf28 { + match self.bits { + false => Wuf28::NoFlag, + true => Wuf28::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf28::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf28::Flag + } +} +#[doc = "Field `WUF28` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf28W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf28>; +impl<'a, REG> Wuf28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf28::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf28::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf29 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF29` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf29R = crate::BitReader; +impl Wuf29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf29 { + match self.bits { + false => Wuf29::NoFlag, + true => Wuf29::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf29::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf29::Flag + } +} +#[doc = "Field `WUF29` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf29W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf29>; +impl<'a, REG> Wuf29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf29::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf29::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf30 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF30` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf30R = crate::BitReader; +impl Wuf30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf30 { + match self.bits { + false => Wuf30::NoFlag, + true => Wuf30::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf30::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf30::Flag + } +} +#[doc = "Field `WUF30` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf30W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf30>; +impl<'a, REG> Wuf30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf30::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf30::Flag) + } +} +#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wuf31 { + #[doc = "0: No"] + NoFlag = 0, + #[doc = "1: Yes"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wuf31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUF31` reader - Wake-up Flag for WUU_Pn"] +pub type Wuf31R = crate::BitReader; +impl Wuf31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wuf31 { + match self.bits { + false => Wuf31::NoFlag, + true => Wuf31::Flag, + } + } + #[doc = "No"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wuf31::NoFlag + } + #[doc = "Yes"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wuf31::Flag + } +} +#[doc = "Field `WUF31` writer - Wake-up Flag for WUU_Pn"] +pub type Wuf31W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf31>; +impl<'a, REG> Wuf31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wuf31::NoFlag) + } + #[doc = "Yes"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wuf31::Flag) + } +} +impl R { + #[doc = "Bit 0 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf0(&self) -> Wuf0R { + Wuf0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf1(&self) -> Wuf1R { + Wuf1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf2(&self) -> Wuf2R { + Wuf2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf3(&self) -> Wuf3R { + Wuf3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf4(&self) -> Wuf4R { + Wuf4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf5(&self) -> Wuf5R { + Wuf5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf6(&self) -> Wuf6R { + Wuf6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf7(&self) -> Wuf7R { + Wuf7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf8(&self) -> Wuf8R { + Wuf8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf9(&self) -> Wuf9R { + Wuf9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf10(&self) -> Wuf10R { + Wuf10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf11(&self) -> Wuf11R { + Wuf11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf12(&self) -> Wuf12R { + Wuf12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf13(&self) -> Wuf13R { + Wuf13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf14(&self) -> Wuf14R { + Wuf14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf15(&self) -> Wuf15R { + Wuf15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf16(&self) -> Wuf16R { + Wuf16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf17(&self) -> Wuf17R { + Wuf17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf18(&self) -> Wuf18R { + Wuf18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf19(&self) -> Wuf19R { + Wuf19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf20(&self) -> Wuf20R { + Wuf20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf21(&self) -> Wuf21R { + Wuf21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf22(&self) -> Wuf22R { + Wuf22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf23(&self) -> Wuf23R { + Wuf23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf24(&self) -> Wuf24R { + Wuf24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf25(&self) -> Wuf25R { + Wuf25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf26(&self) -> Wuf26R { + Wuf26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf27(&self) -> Wuf27R { + Wuf27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf28(&self) -> Wuf28R { + Wuf28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf29(&self) -> Wuf29R { + Wuf29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf30(&self) -> Wuf30R { + Wuf30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf31(&self) -> Wuf31R { + Wuf31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf0(&mut self) -> Wuf0W { + Wuf0W::new(self, 0) + } + #[doc = "Bit 1 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf1(&mut self) -> Wuf1W { + Wuf1W::new(self, 1) + } + #[doc = "Bit 2 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf2(&mut self) -> Wuf2W { + Wuf2W::new(self, 2) + } + #[doc = "Bit 3 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf3(&mut self) -> Wuf3W { + Wuf3W::new(self, 3) + } + #[doc = "Bit 4 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf4(&mut self) -> Wuf4W { + Wuf4W::new(self, 4) + } + #[doc = "Bit 5 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf5(&mut self) -> Wuf5W { + Wuf5W::new(self, 5) + } + #[doc = "Bit 6 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf6(&mut self) -> Wuf6W { + Wuf6W::new(self, 6) + } + #[doc = "Bit 7 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf7(&mut self) -> Wuf7W { + Wuf7W::new(self, 7) + } + #[doc = "Bit 8 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf8(&mut self) -> Wuf8W { + Wuf8W::new(self, 8) + } + #[doc = "Bit 9 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf9(&mut self) -> Wuf9W { + Wuf9W::new(self, 9) + } + #[doc = "Bit 10 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf10(&mut self) -> Wuf10W { + Wuf10W::new(self, 10) + } + #[doc = "Bit 11 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf11(&mut self) -> Wuf11W { + Wuf11W::new(self, 11) + } + #[doc = "Bit 12 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf12(&mut self) -> Wuf12W { + Wuf12W::new(self, 12) + } + #[doc = "Bit 13 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf13(&mut self) -> Wuf13W { + Wuf13W::new(self, 13) + } + #[doc = "Bit 14 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf14(&mut self) -> Wuf14W { + Wuf14W::new(self, 14) + } + #[doc = "Bit 15 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf15(&mut self) -> Wuf15W { + Wuf15W::new(self, 15) + } + #[doc = "Bit 16 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf16(&mut self) -> Wuf16W { + Wuf16W::new(self, 16) + } + #[doc = "Bit 17 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf17(&mut self) -> Wuf17W { + Wuf17W::new(self, 17) + } + #[doc = "Bit 18 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf18(&mut self) -> Wuf18W { + Wuf18W::new(self, 18) + } + #[doc = "Bit 19 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf19(&mut self) -> Wuf19W { + Wuf19W::new(self, 19) + } + #[doc = "Bit 20 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf20(&mut self) -> Wuf20W { + Wuf20W::new(self, 20) + } + #[doc = "Bit 21 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf21(&mut self) -> Wuf21W { + Wuf21W::new(self, 21) + } + #[doc = "Bit 22 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf22(&mut self) -> Wuf22W { + Wuf22W::new(self, 22) + } + #[doc = "Bit 23 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf23(&mut self) -> Wuf23W { + Wuf23W::new(self, 23) + } + #[doc = "Bit 24 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf24(&mut self) -> Wuf24W { + Wuf24W::new(self, 24) + } + #[doc = "Bit 25 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf25(&mut self) -> Wuf25W { + Wuf25W::new(self, 25) + } + #[doc = "Bit 26 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf26(&mut self) -> Wuf26W { + Wuf26W::new(self, 26) + } + #[doc = "Bit 27 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf27(&mut self) -> Wuf27W { + Wuf27W::new(self, 27) + } + #[doc = "Bit 28 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf28(&mut self) -> Wuf28W { + Wuf28W::new(self, 28) + } + #[doc = "Bit 29 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf29(&mut self) -> Wuf29W { + Wuf29W::new(self, 29) + } + #[doc = "Bit 30 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf30(&mut self) -> Wuf30W { + Wuf30W::new(self, 30) + } + #[doc = "Bit 31 - Wake-up Flag for WUU_Pn"] + #[inline(always)] + pub fn wuf31(&mut self) -> Wuf31W { + Wuf31W::new(self, 31) + } +} +#[doc = "Pin Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PfSpec; +impl crate::RegisterSpec for PfSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pf::R`](R) reader structure"] +impl crate::Readable for PfSpec {} +#[doc = "`write(|w| ..)` method takes [`pf::W`](W) writer structure"] +impl crate::Writable for PfSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets PF to value 0"] +impl crate::Resettable for PfSpec {} diff --git a/mcxa276-pac/src/wuu0/pmc.rs b/mcxa276-pac/src/wuu0/pmc.rs new file mode 100644 index 000000000..0f6e6e9e2 --- /dev/null +++ b/mcxa276-pac/src/wuu0/pmc.rs @@ -0,0 +1,2037 @@ +#[doc = "Register `PMC` reader"] +pub type R = crate::R; +#[doc = "Register `PMC` writer"] +pub type W = crate::W; +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc0 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC0` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc0R = crate::BitReader; +impl Wupmc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc0 { + match self.bits { + false => Wupmc0::LowPwrOnly, + true => Wupmc0::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc0::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc0::AnyPwr + } +} +#[doc = "Field `WUPMC0` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc0W<'a, REG> = crate::BitWriter<'a, REG, Wupmc0>; +impl<'a, REG> Wupmc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc0::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc0::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc1 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC1` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc1R = crate::BitReader; +impl Wupmc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc1 { + match self.bits { + false => Wupmc1::LowPwrOnly, + true => Wupmc1::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc1::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc1::AnyPwr + } +} +#[doc = "Field `WUPMC1` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc1W<'a, REG> = crate::BitWriter<'a, REG, Wupmc1>; +impl<'a, REG> Wupmc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc1::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc1::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc2 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC2` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc2R = crate::BitReader; +impl Wupmc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc2 { + match self.bits { + false => Wupmc2::LowPwrOnly, + true => Wupmc2::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc2::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc2::AnyPwr + } +} +#[doc = "Field `WUPMC2` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc2W<'a, REG> = crate::BitWriter<'a, REG, Wupmc2>; +impl<'a, REG> Wupmc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc2::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc2::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc3 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC3` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc3R = crate::BitReader; +impl Wupmc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc3 { + match self.bits { + false => Wupmc3::LowPwrOnly, + true => Wupmc3::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc3::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc3::AnyPwr + } +} +#[doc = "Field `WUPMC3` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc3W<'a, REG> = crate::BitWriter<'a, REG, Wupmc3>; +impl<'a, REG> Wupmc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc3::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc3::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc4 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc4) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC4` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc4R = crate::BitReader; +impl Wupmc4R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc4 { + match self.bits { + false => Wupmc4::LowPwrOnly, + true => Wupmc4::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc4::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc4::AnyPwr + } +} +#[doc = "Field `WUPMC4` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc4W<'a, REG> = crate::BitWriter<'a, REG, Wupmc4>; +impl<'a, REG> Wupmc4W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc4::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc4::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc5 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc5) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC5` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc5R = crate::BitReader; +impl Wupmc5R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc5 { + match self.bits { + false => Wupmc5::LowPwrOnly, + true => Wupmc5::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc5::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc5::AnyPwr + } +} +#[doc = "Field `WUPMC5` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc5W<'a, REG> = crate::BitWriter<'a, REG, Wupmc5>; +impl<'a, REG> Wupmc5W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc5::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc5::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc6 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc6) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC6` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc6R = crate::BitReader; +impl Wupmc6R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc6 { + match self.bits { + false => Wupmc6::LowPwrOnly, + true => Wupmc6::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc6::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc6::AnyPwr + } +} +#[doc = "Field `WUPMC6` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc6W<'a, REG> = crate::BitWriter<'a, REG, Wupmc6>; +impl<'a, REG> Wupmc6W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc6::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc6::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc7 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc7) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC7` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc7R = crate::BitReader; +impl Wupmc7R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc7 { + match self.bits { + false => Wupmc7::LowPwrOnly, + true => Wupmc7::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc7::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc7::AnyPwr + } +} +#[doc = "Field `WUPMC7` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc7W<'a, REG> = crate::BitWriter<'a, REG, Wupmc7>; +impl<'a, REG> Wupmc7W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc7::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc7::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc8 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc8) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC8` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc8R = crate::BitReader; +impl Wupmc8R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc8 { + match self.bits { + false => Wupmc8::LowPwrOnly, + true => Wupmc8::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc8::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc8::AnyPwr + } +} +#[doc = "Field `WUPMC8` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc8W<'a, REG> = crate::BitWriter<'a, REG, Wupmc8>; +impl<'a, REG> Wupmc8W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc8::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc8::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc9 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc9) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC9` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc9R = crate::BitReader; +impl Wupmc9R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc9 { + match self.bits { + false => Wupmc9::LowPwrOnly, + true => Wupmc9::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc9::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc9::AnyPwr + } +} +#[doc = "Field `WUPMC9` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc9W<'a, REG> = crate::BitWriter<'a, REG, Wupmc9>; +impl<'a, REG> Wupmc9W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc9::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc9::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc10 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc10) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC10` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc10R = crate::BitReader; +impl Wupmc10R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc10 { + match self.bits { + false => Wupmc10::LowPwrOnly, + true => Wupmc10::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc10::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc10::AnyPwr + } +} +#[doc = "Field `WUPMC10` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc10W<'a, REG> = crate::BitWriter<'a, REG, Wupmc10>; +impl<'a, REG> Wupmc10W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc10::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc10::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc11 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc11) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC11` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc11R = crate::BitReader; +impl Wupmc11R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc11 { + match self.bits { + false => Wupmc11::LowPwrOnly, + true => Wupmc11::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc11::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc11::AnyPwr + } +} +#[doc = "Field `WUPMC11` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc11W<'a, REG> = crate::BitWriter<'a, REG, Wupmc11>; +impl<'a, REG> Wupmc11W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc11::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc11::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc12 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc12) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC12` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc12R = crate::BitReader; +impl Wupmc12R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc12 { + match self.bits { + false => Wupmc12::LowPwrOnly, + true => Wupmc12::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc12::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc12::AnyPwr + } +} +#[doc = "Field `WUPMC12` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc12W<'a, REG> = crate::BitWriter<'a, REG, Wupmc12>; +impl<'a, REG> Wupmc12W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc12::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc12::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc13 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc13) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC13` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc13R = crate::BitReader; +impl Wupmc13R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc13 { + match self.bits { + false => Wupmc13::LowPwrOnly, + true => Wupmc13::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc13::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc13::AnyPwr + } +} +#[doc = "Field `WUPMC13` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc13W<'a, REG> = crate::BitWriter<'a, REG, Wupmc13>; +impl<'a, REG> Wupmc13W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc13::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc13::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc14 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc14) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC14` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc14R = crate::BitReader; +impl Wupmc14R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc14 { + match self.bits { + false => Wupmc14::LowPwrOnly, + true => Wupmc14::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc14::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc14::AnyPwr + } +} +#[doc = "Field `WUPMC14` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc14W<'a, REG> = crate::BitWriter<'a, REG, Wupmc14>; +impl<'a, REG> Wupmc14W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc14::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc14::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc15 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc15) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC15` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc15R = crate::BitReader; +impl Wupmc15R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc15 { + match self.bits { + false => Wupmc15::LowPwrOnly, + true => Wupmc15::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc15::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc15::AnyPwr + } +} +#[doc = "Field `WUPMC15` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc15W<'a, REG> = crate::BitWriter<'a, REG, Wupmc15>; +impl<'a, REG> Wupmc15W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc15::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc15::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc16 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc16) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC16` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc16R = crate::BitReader; +impl Wupmc16R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc16 { + match self.bits { + false => Wupmc16::LowPwrOnly, + true => Wupmc16::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc16::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc16::AnyPwr + } +} +#[doc = "Field `WUPMC16` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc16W<'a, REG> = crate::BitWriter<'a, REG, Wupmc16>; +impl<'a, REG> Wupmc16W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc16::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc16::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc17 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc17) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC17` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc17R = crate::BitReader; +impl Wupmc17R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc17 { + match self.bits { + false => Wupmc17::LowPwrOnly, + true => Wupmc17::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc17::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc17::AnyPwr + } +} +#[doc = "Field `WUPMC17` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc17W<'a, REG> = crate::BitWriter<'a, REG, Wupmc17>; +impl<'a, REG> Wupmc17W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc17::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc17::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc18 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc18) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC18` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc18R = crate::BitReader; +impl Wupmc18R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc18 { + match self.bits { + false => Wupmc18::LowPwrOnly, + true => Wupmc18::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc18::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc18::AnyPwr + } +} +#[doc = "Field `WUPMC18` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc18W<'a, REG> = crate::BitWriter<'a, REG, Wupmc18>; +impl<'a, REG> Wupmc18W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc18::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc18::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc19 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc19) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC19` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc19R = crate::BitReader; +impl Wupmc19R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc19 { + match self.bits { + false => Wupmc19::LowPwrOnly, + true => Wupmc19::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc19::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc19::AnyPwr + } +} +#[doc = "Field `WUPMC19` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc19W<'a, REG> = crate::BitWriter<'a, REG, Wupmc19>; +impl<'a, REG> Wupmc19W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc19::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc19::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc20 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc20) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC20` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc20R = crate::BitReader; +impl Wupmc20R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc20 { + match self.bits { + false => Wupmc20::LowPwrOnly, + true => Wupmc20::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc20::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc20::AnyPwr + } +} +#[doc = "Field `WUPMC20` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc20W<'a, REG> = crate::BitWriter<'a, REG, Wupmc20>; +impl<'a, REG> Wupmc20W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc20::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc20::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc21 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc21) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC21` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc21R = crate::BitReader; +impl Wupmc21R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc21 { + match self.bits { + false => Wupmc21::LowPwrOnly, + true => Wupmc21::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc21::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc21::AnyPwr + } +} +#[doc = "Field `WUPMC21` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc21W<'a, REG> = crate::BitWriter<'a, REG, Wupmc21>; +impl<'a, REG> Wupmc21W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc21::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc21::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc22 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc22) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC22` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc22R = crate::BitReader; +impl Wupmc22R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc22 { + match self.bits { + false => Wupmc22::LowPwrOnly, + true => Wupmc22::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc22::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc22::AnyPwr + } +} +#[doc = "Field `WUPMC22` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc22W<'a, REG> = crate::BitWriter<'a, REG, Wupmc22>; +impl<'a, REG> Wupmc22W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc22::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc22::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc23 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc23) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC23` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc23R = crate::BitReader; +impl Wupmc23R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc23 { + match self.bits { + false => Wupmc23::LowPwrOnly, + true => Wupmc23::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc23::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc23::AnyPwr + } +} +#[doc = "Field `WUPMC23` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc23W<'a, REG> = crate::BitWriter<'a, REG, Wupmc23>; +impl<'a, REG> Wupmc23W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc23::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc23::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc24 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc24) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC24` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc24R = crate::BitReader; +impl Wupmc24R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc24 { + match self.bits { + false => Wupmc24::LowPwrOnly, + true => Wupmc24::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc24::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc24::AnyPwr + } +} +#[doc = "Field `WUPMC24` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc24W<'a, REG> = crate::BitWriter<'a, REG, Wupmc24>; +impl<'a, REG> Wupmc24W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc24::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc24::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc25 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc25) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC25` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc25R = crate::BitReader; +impl Wupmc25R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc25 { + match self.bits { + false => Wupmc25::LowPwrOnly, + true => Wupmc25::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc25::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc25::AnyPwr + } +} +#[doc = "Field `WUPMC25` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc25W<'a, REG> = crate::BitWriter<'a, REG, Wupmc25>; +impl<'a, REG> Wupmc25W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc25::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc25::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc26 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc26) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC26` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc26R = crate::BitReader; +impl Wupmc26R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc26 { + match self.bits { + false => Wupmc26::LowPwrOnly, + true => Wupmc26::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc26::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc26::AnyPwr + } +} +#[doc = "Field `WUPMC26` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc26W<'a, REG> = crate::BitWriter<'a, REG, Wupmc26>; +impl<'a, REG> Wupmc26W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc26::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc26::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc27 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc27) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC27` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc27R = crate::BitReader; +impl Wupmc27R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc27 { + match self.bits { + false => Wupmc27::LowPwrOnly, + true => Wupmc27::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc27::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc27::AnyPwr + } +} +#[doc = "Field `WUPMC27` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc27W<'a, REG> = crate::BitWriter<'a, REG, Wupmc27>; +impl<'a, REG> Wupmc27W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc27::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc27::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc28 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc28) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC28` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc28R = crate::BitReader; +impl Wupmc28R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc28 { + match self.bits { + false => Wupmc28::LowPwrOnly, + true => Wupmc28::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc28::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc28::AnyPwr + } +} +#[doc = "Field `WUPMC28` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc28W<'a, REG> = crate::BitWriter<'a, REG, Wupmc28>; +impl<'a, REG> Wupmc28W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc28::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc28::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc29 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc29) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC29` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc29R = crate::BitReader; +impl Wupmc29R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc29 { + match self.bits { + false => Wupmc29::LowPwrOnly, + true => Wupmc29::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc29::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc29::AnyPwr + } +} +#[doc = "Field `WUPMC29` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc29W<'a, REG> = crate::BitWriter<'a, REG, Wupmc29>; +impl<'a, REG> Wupmc29W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc29::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc29::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc30 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc30) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC30` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc30R = crate::BitReader; +impl Wupmc30R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc30 { + match self.bits { + false => Wupmc30::LowPwrOnly, + true => Wupmc30::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc30::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc30::AnyPwr + } +} +#[doc = "Field `WUPMC30` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc30W<'a, REG> = crate::BitWriter<'a, REG, Wupmc30>; +impl<'a, REG> Wupmc30W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc30::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc30::AnyPwr) + } +} +#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wupmc31 { + #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + LowPwrOnly = 0, + #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + AnyPwr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wupmc31) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WUPMC31` reader - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc31R = crate::BitReader; +impl Wupmc31R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wupmc31 { + match self.bits { + false => Wupmc31::LowPwrOnly, + true => Wupmc31::AnyPwr, + } + } + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_low_pwr_only(&self) -> bool { + *self == Wupmc31::LowPwrOnly + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn is_any_pwr(&self) -> bool { + *self == Wupmc31::AnyPwr + } +} +#[doc = "Field `WUPMC31` writer - Wake-up Pin Mode Configuration for WUU_Pn"] +pub type Wupmc31W<'a, REG> = crate::BitWriter<'a, REG, Wupmc31>; +impl<'a, REG> Wupmc31W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn low_pwr_only(self) -> &'a mut crate::W { + self.variant(Wupmc31::LowPwrOnly) + } + #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] + #[inline(always)] + pub fn any_pwr(self) -> &'a mut crate::W { + self.variant(Wupmc31::AnyPwr) + } +} +impl R { + #[doc = "Bit 0 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc0(&self) -> Wupmc0R { + Wupmc0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc1(&self) -> Wupmc1R { + Wupmc1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc2(&self) -> Wupmc2R { + Wupmc2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc3(&self) -> Wupmc3R { + Wupmc3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc4(&self) -> Wupmc4R { + Wupmc4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc5(&self) -> Wupmc5R { + Wupmc5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc6(&self) -> Wupmc6R { + Wupmc6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc7(&self) -> Wupmc7R { + Wupmc7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc8(&self) -> Wupmc8R { + Wupmc8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc9(&self) -> Wupmc9R { + Wupmc9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc10(&self) -> Wupmc10R { + Wupmc10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc11(&self) -> Wupmc11R { + Wupmc11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc12(&self) -> Wupmc12R { + Wupmc12R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc13(&self) -> Wupmc13R { + Wupmc13R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc14(&self) -> Wupmc14R { + Wupmc14R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc15(&self) -> Wupmc15R { + Wupmc15R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc16(&self) -> Wupmc16R { + Wupmc16R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc17(&self) -> Wupmc17R { + Wupmc17R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc18(&self) -> Wupmc18R { + Wupmc18R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc19(&self) -> Wupmc19R { + Wupmc19R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc20(&self) -> Wupmc20R { + Wupmc20R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc21(&self) -> Wupmc21R { + Wupmc21R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc22(&self) -> Wupmc22R { + Wupmc22R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc23(&self) -> Wupmc23R { + Wupmc23R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc24(&self) -> Wupmc24R { + Wupmc24R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc25(&self) -> Wupmc25R { + Wupmc25R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc26(&self) -> Wupmc26R { + Wupmc26R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc27(&self) -> Wupmc27R { + Wupmc27R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc28(&self) -> Wupmc28R { + Wupmc28R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc29(&self) -> Wupmc29R { + Wupmc29R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc30(&self) -> Wupmc30R { + Wupmc30R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc31(&self) -> Wupmc31R { + Wupmc31R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc0(&mut self) -> Wupmc0W { + Wupmc0W::new(self, 0) + } + #[doc = "Bit 1 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc1(&mut self) -> Wupmc1W { + Wupmc1W::new(self, 1) + } + #[doc = "Bit 2 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc2(&mut self) -> Wupmc2W { + Wupmc2W::new(self, 2) + } + #[doc = "Bit 3 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc3(&mut self) -> Wupmc3W { + Wupmc3W::new(self, 3) + } + #[doc = "Bit 4 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc4(&mut self) -> Wupmc4W { + Wupmc4W::new(self, 4) + } + #[doc = "Bit 5 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc5(&mut self) -> Wupmc5W { + Wupmc5W::new(self, 5) + } + #[doc = "Bit 6 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc6(&mut self) -> Wupmc6W { + Wupmc6W::new(self, 6) + } + #[doc = "Bit 7 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc7(&mut self) -> Wupmc7W { + Wupmc7W::new(self, 7) + } + #[doc = "Bit 8 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc8(&mut self) -> Wupmc8W { + Wupmc8W::new(self, 8) + } + #[doc = "Bit 9 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc9(&mut self) -> Wupmc9W { + Wupmc9W::new(self, 9) + } + #[doc = "Bit 10 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc10(&mut self) -> Wupmc10W { + Wupmc10W::new(self, 10) + } + #[doc = "Bit 11 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc11(&mut self) -> Wupmc11W { + Wupmc11W::new(self, 11) + } + #[doc = "Bit 12 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc12(&mut self) -> Wupmc12W { + Wupmc12W::new(self, 12) + } + #[doc = "Bit 13 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc13(&mut self) -> Wupmc13W { + Wupmc13W::new(self, 13) + } + #[doc = "Bit 14 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc14(&mut self) -> Wupmc14W { + Wupmc14W::new(self, 14) + } + #[doc = "Bit 15 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc15(&mut self) -> Wupmc15W { + Wupmc15W::new(self, 15) + } + #[doc = "Bit 16 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc16(&mut self) -> Wupmc16W { + Wupmc16W::new(self, 16) + } + #[doc = "Bit 17 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc17(&mut self) -> Wupmc17W { + Wupmc17W::new(self, 17) + } + #[doc = "Bit 18 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc18(&mut self) -> Wupmc18W { + Wupmc18W::new(self, 18) + } + #[doc = "Bit 19 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc19(&mut self) -> Wupmc19W { + Wupmc19W::new(self, 19) + } + #[doc = "Bit 20 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc20(&mut self) -> Wupmc20W { + Wupmc20W::new(self, 20) + } + #[doc = "Bit 21 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc21(&mut self) -> Wupmc21W { + Wupmc21W::new(self, 21) + } + #[doc = "Bit 22 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc22(&mut self) -> Wupmc22W { + Wupmc22W::new(self, 22) + } + #[doc = "Bit 23 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc23(&mut self) -> Wupmc23W { + Wupmc23W::new(self, 23) + } + #[doc = "Bit 24 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc24(&mut self) -> Wupmc24W { + Wupmc24W::new(self, 24) + } + #[doc = "Bit 25 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc25(&mut self) -> Wupmc25W { + Wupmc25W::new(self, 25) + } + #[doc = "Bit 26 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc26(&mut self) -> Wupmc26W { + Wupmc26W::new(self, 26) + } + #[doc = "Bit 27 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc27(&mut self) -> Wupmc27W { + Wupmc27W::new(self, 27) + } + #[doc = "Bit 28 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc28(&mut self) -> Wupmc28W { + Wupmc28W::new(self, 28) + } + #[doc = "Bit 29 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc29(&mut self) -> Wupmc29W { + Wupmc29W::new(self, 29) + } + #[doc = "Bit 30 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc30(&mut self) -> Wupmc30W { + Wupmc30W::new(self, 30) + } + #[doc = "Bit 31 - Wake-up Pin Mode Configuration for WUU_Pn"] + #[inline(always)] + pub fn wupmc31(&mut self) -> Wupmc31W { + Wupmc31W::new(self, 31) + } +} +#[doc = "Pin Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pmc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PmcSpec; +impl crate::RegisterSpec for PmcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmc::R`](R) reader structure"] +impl crate::Readable for PmcSpec {} +#[doc = "`write(|w| ..)` method takes [`pmc::W`](W) writer structure"] +impl crate::Writable for PmcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PMC to value 0"] +impl crate::Resettable for PmcSpec {} diff --git a/mcxa276-pac/src/wuu0/verid.rs b/mcxa276-pac/src/wuu0/verid.rs new file mode 100644 index 000000000..5ba468f42 --- /dev/null +++ b/mcxa276-pac/src/wuu0/verid.rs @@ -0,0 +1,76 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Feature Specification Number\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Feature { + #[doc = "0: Standard features implemented"] + Standard = 0, + #[doc = "1: Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for external pin/filter detection during all power modes enabled."] + FiltAllPwr = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: Feature) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Feature { + type Ux = u16; +} +impl crate::IsEnum for Feature {} +#[doc = "Field `FEATURE` reader - Feature Specification Number"] +pub type FeatureR = crate::FieldReader; +impl FeatureR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Feature::Standard), + 1 => Some(Feature::FiltAllPwr), + _ => None, + } + } + #[doc = "Standard features implemented"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == Feature::Standard + } + #[doc = "Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for external pin/filter detection during all power modes enabled."] + #[inline(always)] + pub fn is_filt_all_pwr(&self) -> bool { + *self == Feature::FiltAllPwr + } +} +#[doc = "Field `MINOR` reader - Minor Version Number"] +pub type MinorR = crate::FieldReader; +#[doc = "Field `MAJOR` reader - Major Version Number"] +pub type MajorR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Feature Specification Number"] + #[inline(always)] + pub fn feature(&self) -> FeatureR { + FeatureR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Minor Version Number"] + #[inline(always)] + pub fn minor(&self) -> MinorR { + MinorR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Major Version Number"] + #[inline(always)] + pub fn major(&self) -> MajorR { + MajorR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VeridSpec; +impl crate::RegisterSpec for VeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VeridSpec {} +#[doc = "`reset()` method sets VERID to value 0x0100_0001"] +impl crate::Resettable for VeridSpec { + const RESET_VALUE: u32 = 0x0100_0001; +} diff --git a/mcxa276-pac/src/wwdt0.rs b/mcxa276-pac/src/wwdt0.rs new file mode 100644 index 000000000..5c60c190d --- /dev/null +++ b/mcxa276-pac/src/wwdt0.rs @@ -0,0 +1,73 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mod_: Mod, + tc: Tc, + feed: Feed, + tv: Tv, + _reserved4: [u8; 0x04], + warnint: Warnint, + window: Window, +} +impl RegisterBlock { + #[doc = "0x00 - Mode"] + #[inline(always)] + pub const fn mod_(&self) -> &Mod { + &self.mod_ + } + #[doc = "0x04 - Timer Constant"] + #[inline(always)] + pub const fn tc(&self) -> &Tc { + &self.tc + } + #[doc = "0x08 - Feed Sequence"] + #[inline(always)] + pub const fn feed(&self) -> &Feed { + &self.feed + } + #[doc = "0x0c - Timer Value"] + #[inline(always)] + pub const fn tv(&self) -> &Tv { + &self.tv + } + #[doc = "0x14 - Warning Interrupt Compare Value"] + #[inline(always)] + pub const fn warnint(&self) -> &Warnint { + &self.warnint + } + #[doc = "0x18 - Window Compare Value"] + #[inline(always)] + pub const fn window(&self) -> &Window { + &self.window + } +} +#[doc = "MOD (rw) register accessor: Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mod_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mod_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mod_`] module"] +#[doc(alias = "MOD")] +pub type Mod = crate::Reg; +#[doc = "Mode"] +pub mod mod_; +#[doc = "TC (rw) register accessor: Timer Constant\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] module"] +#[doc(alias = "TC")] +pub type Tc = crate::Reg; +#[doc = "Timer Constant"] +pub mod tc; +#[doc = "FEED (w) register accessor: Feed Sequence\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`feed::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@feed`] module"] +#[doc(alias = "FEED")] +pub type Feed = crate::Reg; +#[doc = "Feed Sequence"] +pub mod feed; +#[doc = "TV (r) register accessor: Timer Value\n\nYou can [`read`](crate::Reg::read) this register and get [`tv::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tv`] module"] +#[doc(alias = "TV")] +pub type Tv = crate::Reg; +#[doc = "Timer Value"] +pub mod tv; +#[doc = "WARNINT (rw) register accessor: Warning Interrupt Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`warnint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`warnint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@warnint`] module"] +#[doc(alias = "WARNINT")] +pub type Warnint = crate::Reg; +#[doc = "Warning Interrupt Compare Value"] +pub mod warnint; +#[doc = "WINDOW (rw) register accessor: Window Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`window::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`window::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@window`] module"] +#[doc(alias = "WINDOW")] +pub type Window = crate::Reg; +#[doc = "Window Compare Value"] +pub mod window; diff --git a/mcxa276-pac/src/wwdt0/feed.rs b/mcxa276-pac/src/wwdt0/feed.rs new file mode 100644 index 000000000..7b0acaead --- /dev/null +++ b/mcxa276-pac/src/wwdt0/feed.rs @@ -0,0 +1,22 @@ +#[doc = "Register `FEED` writer"] +pub type W = crate::W; +#[doc = "Field `FEED` writer - Feed Value"] +pub type FeedW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Feed Value"] + #[inline(always)] + pub fn feed(&mut self) -> FeedW { + FeedW::new(self, 0) + } +} +#[doc = "Feed Sequence\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`feed::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FeedSpec; +impl crate::RegisterSpec for FeedSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`feed::W`](W) writer structure"] +impl crate::Writable for FeedSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FEED to value 0"] +impl crate::Resettable for FeedSpec {} diff --git a/mcxa276-pac/src/wwdt0/mod_.rs b/mcxa276-pac/src/wwdt0/mod_.rs new file mode 100644 index 000000000..8a3531328 --- /dev/null +++ b/mcxa276-pac/src/wwdt0/mod_.rs @@ -0,0 +1,463 @@ +#[doc = "Register `MOD` reader"] +pub type R = crate::R; +#[doc = "Register `MOD` writer"] +pub type W = crate::W; +#[doc = "Watchdog Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wden { + #[doc = "0: Timer stopped"] + Stop = 0, + #[doc = "1: Timer running"] + Run = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wden) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDEN` reader - Watchdog Enable"] +pub type WdenR = crate::BitReader; +impl WdenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wden { + match self.bits { + false => Wden::Stop, + true => Wden::Run, + } + } + #[doc = "Timer stopped"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == Wden::Stop + } + #[doc = "Timer running"] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == Wden::Run + } +} +#[doc = "Field `WDEN` writer - Watchdog Enable"] +pub type WdenW<'a, REG> = crate::BitWriter<'a, REG, Wden>; +impl<'a, REG> WdenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Timer stopped"] + #[inline(always)] + pub fn stop(self) -> &'a mut crate::W { + self.variant(Wden::Stop) + } + #[doc = "Timer running"] + #[inline(always)] + pub fn run(self) -> &'a mut crate::W { + self.variant(Wden::Run) + } +} +#[doc = "Watchdog Reset Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdreset { + #[doc = "0: Interrupt"] + Interrupt = 0, + #[doc = "1: Reset"] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdreset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDRESET` reader - Watchdog Reset Enable"] +pub type WdresetR = crate::BitReader; +impl WdresetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdreset { + match self.bits { + false => Wdreset::Interrupt, + true => Wdreset::Reset, + } + } + #[doc = "Interrupt"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == Wdreset::Interrupt + } + #[doc = "Reset"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Wdreset::Reset + } +} +#[doc = "Field `WDRESET` writer - Watchdog Reset Enable"] +pub type WdresetW<'a, REG> = crate::BitWriter<'a, REG, Wdreset>; +impl<'a, REG> WdresetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Interrupt"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(Wdreset::Interrupt) + } + #[doc = "Reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Wdreset::Reset) + } +} +#[doc = "Watchdog Timeout Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdtof { + #[doc = "0: Watchdog event has not occurred."] + Clear = 0, + #[doc = "1: Watchdog event has occurred (causes a chip reset if WDRESET = 1)."] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdtof) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDTOF` reader - Watchdog Timeout Flag"] +pub type WdtofR = crate::BitReader; +impl WdtofR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdtof { + match self.bits { + false => Wdtof::Clear, + true => Wdtof::Reset, + } + } + #[doc = "Watchdog event has not occurred."] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Wdtof::Clear + } + #[doc = "Watchdog event has occurred (causes a chip reset if WDRESET = 1)."] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Wdtof::Reset + } +} +#[doc = "Field `WDTOF` writer - Watchdog Timeout Flag"] +pub type WdtofW<'a, REG> = crate::BitWriter<'a, REG, Wdtof>; +impl<'a, REG> WdtofW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Watchdog event has not occurred."] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Wdtof::Clear) + } + #[doc = "Watchdog event has occurred (causes a chip reset if WDRESET = 1)."] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Wdtof::Reset) + } +} +#[doc = "Warning Interrupt Flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdint { + #[doc = "0: No flag"] + NoFlag = 0, + #[doc = "1: Flag"] + Flag = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdint) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDINT` reader - Warning Interrupt Flag"] +pub type WdintR = crate::BitReader; +impl WdintR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdint { + match self.bits { + false => Wdint::NoFlag, + true => Wdint::Flag, + } + } + #[doc = "No flag"] + #[inline(always)] + pub fn is_no_flag(&self) -> bool { + *self == Wdint::NoFlag + } + #[doc = "Flag"] + #[inline(always)] + pub fn is_flag(&self) -> bool { + *self == Wdint::Flag + } +} +#[doc = "Field `WDINT` writer - Warning Interrupt Flag"] +pub type WdintW<'a, REG> = crate::BitWriter1C<'a, REG, Wdint>; +impl<'a, REG> WdintW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No flag"] + #[inline(always)] + pub fn no_flag(self) -> &'a mut crate::W { + self.variant(Wdint::NoFlag) + } + #[doc = "Flag"] + #[inline(always)] + pub fn flag(self) -> &'a mut crate::W { + self.variant(Wdint::Flag) + } +} +#[doc = "Watchdog Update Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdprotect { + #[doc = "0: Flexible"] + Flexible = 0, + #[doc = "1: Threshold"] + Threshold = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdprotect) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDPROTECT` reader - Watchdog Update Mode"] +pub type WdprotectR = crate::BitReader; +impl WdprotectR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdprotect { + match self.bits { + false => Wdprotect::Flexible, + true => Wdprotect::Threshold, + } + } + #[doc = "Flexible"] + #[inline(always)] + pub fn is_flexible(&self) -> bool { + *self == Wdprotect::Flexible + } + #[doc = "Threshold"] + #[inline(always)] + pub fn is_threshold(&self) -> bool { + *self == Wdprotect::Threshold + } +} +#[doc = "Field `WDPROTECT` writer - Watchdog Update Mode"] +pub type WdprotectW<'a, REG> = crate::BitWriter<'a, REG, Wdprotect>; +impl<'a, REG> WdprotectW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Flexible"] + #[inline(always)] + pub fn flexible(self) -> &'a mut crate::W { + self.variant(Wdprotect::Flexible) + } + #[doc = "Threshold"] + #[inline(always)] + pub fn threshold(self) -> &'a mut crate::W { + self.variant(Wdprotect::Threshold) + } +} +#[doc = "Lock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: No Lock"] + NoLock = 0, + #[doc = "1: Lock"] + Lock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - Lock"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::NoLock, + true => Lock::Lock, + } + } + #[doc = "No Lock"] + #[inline(always)] + pub fn is_no_lock(&self) -> bool { + *self == Lock::NoLock + } + #[doc = "Lock"] + #[inline(always)] + pub fn is_lock(&self) -> bool { + *self == Lock::Lock + } +} +#[doc = "Field `LOCK` writer - Lock"] +pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; +impl<'a, REG> LockW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No Lock"] + #[inline(always)] + pub fn no_lock(self) -> &'a mut crate::W { + self.variant(Lock::NoLock) + } + #[doc = "Lock"] + #[inline(always)] + pub fn lock(self) -> &'a mut crate::W { + self.variant(Lock::Lock) + } +} +#[doc = "Debug Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DebugEn { + #[doc = "0: Disabled"] + Disable = 0, + #[doc = "1: Enabled"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DebugEn) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DEBUG_EN` reader - Debug Enable"] +pub type DebugEnR = crate::BitReader; +impl DebugEnR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DebugEn { + match self.bits { + false => DebugEn::Disable, + true => DebugEn::Enable, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DebugEn::Disable + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == DebugEn::Enable + } +} +#[doc = "Field `DEBUG_EN` writer - Debug Enable"] +pub type DebugEnW<'a, REG> = crate::BitWriter<'a, REG, DebugEn>; +impl<'a, REG> DebugEnW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(DebugEn::Disable) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(DebugEn::Enable) + } +} +impl R { + #[doc = "Bit 0 - Watchdog Enable"] + #[inline(always)] + pub fn wden(&self) -> WdenR { + WdenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Watchdog Reset Enable"] + #[inline(always)] + pub fn wdreset(&self) -> WdresetR { + WdresetR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Watchdog Timeout Flag"] + #[inline(always)] + pub fn wdtof(&self) -> WdtofR { + WdtofR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Warning Interrupt Flag"] + #[inline(always)] + pub fn wdint(&self) -> WdintR { + WdintR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Watchdog Update Mode"] + #[inline(always)] + pub fn wdprotect(&self) -> WdprotectR { + WdprotectR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Lock"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Debug Enable"] + #[inline(always)] + pub fn debug_en(&self) -> DebugEnR { + DebugEnR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Watchdog Enable"] + #[inline(always)] + pub fn wden(&mut self) -> WdenW { + WdenW::new(self, 0) + } + #[doc = "Bit 1 - Watchdog Reset Enable"] + #[inline(always)] + pub fn wdreset(&mut self) -> WdresetW { + WdresetW::new(self, 1) + } + #[doc = "Bit 2 - Watchdog Timeout Flag"] + #[inline(always)] + pub fn wdtof(&mut self) -> WdtofW { + WdtofW::new(self, 2) + } + #[doc = "Bit 3 - Warning Interrupt Flag"] + #[inline(always)] + pub fn wdint(&mut self) -> WdintW { + WdintW::new(self, 3) + } + #[doc = "Bit 4 - Watchdog Update Mode"] + #[inline(always)] + pub fn wdprotect(&mut self) -> WdprotectW { + WdprotectW::new(self, 4) + } + #[doc = "Bit 5 - Lock"] + #[inline(always)] + pub fn lock(&mut self) -> LockW { + LockW::new(self, 5) + } + #[doc = "Bit 6 - Debug Enable"] + #[inline(always)] + pub fn debug_en(&mut self) -> DebugEnW { + DebugEnW::new(self, 6) + } +} +#[doc = "Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mod_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mod_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ModSpec; +impl crate::RegisterSpec for ModSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mod_::R`](R) reader structure"] +impl crate::Readable for ModSpec {} +#[doc = "`write(|w| ..)` method takes [`mod_::W`](W) writer structure"] +impl crate::Writable for ModSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x08; +} +#[doc = "`reset()` method sets MOD to value 0"] +impl crate::Resettable for ModSpec {} diff --git a/mcxa276-pac/src/wwdt0/tc.rs b/mcxa276-pac/src/wwdt0/tc.rs new file mode 100644 index 000000000..cb0769051 --- /dev/null +++ b/mcxa276-pac/src/wwdt0/tc.rs @@ -0,0 +1,37 @@ +#[doc = "Register `TC` reader"] +pub type R = crate::R; +#[doc = "Register `TC` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - Watchdog Timeout Value"] +pub type CountR = crate::FieldReader; +#[doc = "Field `COUNT` writer - Watchdog Timeout Value"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Watchdog Timeout Value"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Watchdog Timeout Value"] + #[inline(always)] + pub fn count(&mut self) -> CountW { + CountW::new(self, 0) + } +} +#[doc = "Timer Constant\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcSpec; +impl crate::RegisterSpec for TcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tc::R`](R) reader structure"] +impl crate::Readable for TcSpec {} +#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] +impl crate::Writable for TcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TC to value 0xff"] +impl crate::Resettable for TcSpec { + const RESET_VALUE: u32 = 0xff; +} diff --git a/mcxa276-pac/src/wwdt0/tv.rs b/mcxa276-pac/src/wwdt0/tv.rs new file mode 100644 index 000000000..cf5542933 --- /dev/null +++ b/mcxa276-pac/src/wwdt0/tv.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TV` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Counter Timer Value"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - Counter Timer Value"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits & 0x00ff_ffff) + } +} +#[doc = "Timer Value\n\nYou can [`read`](crate::Reg::read) this register and get [`tv::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TvSpec; +impl crate::RegisterSpec for TvSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tv::R`](R) reader structure"] +impl crate::Readable for TvSpec {} +#[doc = "`reset()` method sets TV to value 0xff"] +impl crate::Resettable for TvSpec { + const RESET_VALUE: u32 = 0xff; +} diff --git a/mcxa276-pac/src/wwdt0/warnint.rs b/mcxa276-pac/src/wwdt0/warnint.rs new file mode 100644 index 000000000..9c62907e1 --- /dev/null +++ b/mcxa276-pac/src/wwdt0/warnint.rs @@ -0,0 +1,35 @@ +#[doc = "Register `WARNINT` reader"] +pub type R = crate::R; +#[doc = "Register `WARNINT` writer"] +pub type W = crate::W; +#[doc = "Field `WARNINT` reader - Watchdog Warning Interrupt Compare Value"] +pub type WarnintR = crate::FieldReader; +#[doc = "Field `WARNINT` writer - Watchdog Warning Interrupt Compare Value"] +pub type WarnintW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Watchdog Warning Interrupt Compare Value"] + #[inline(always)] + pub fn warnint(&self) -> WarnintR { + WarnintR::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Watchdog Warning Interrupt Compare Value"] + #[inline(always)] + pub fn warnint(&mut self) -> WarnintW { + WarnintW::new(self, 0) + } +} +#[doc = "Warning Interrupt Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`warnint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`warnint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WarnintSpec; +impl crate::RegisterSpec for WarnintSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`warnint::R`](R) reader structure"] +impl crate::Readable for WarnintSpec {} +#[doc = "`write(|w| ..)` method takes [`warnint::W`](W) writer structure"] +impl crate::Writable for WarnintSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WARNINT to value 0"] +impl crate::Resettable for WarnintSpec {} diff --git a/mcxa276-pac/src/wwdt0/window.rs b/mcxa276-pac/src/wwdt0/window.rs new file mode 100644 index 000000000..455c8c8a9 --- /dev/null +++ b/mcxa276-pac/src/wwdt0/window.rs @@ -0,0 +1,37 @@ +#[doc = "Register `WINDOW` reader"] +pub type R = crate::R; +#[doc = "Register `WINDOW` writer"] +pub type W = crate::W; +#[doc = "Field `WINDOW` reader - Watchdog Window Value"] +pub type WindowR = crate::FieldReader; +#[doc = "Field `WINDOW` writer - Watchdog Window Value"] +pub type WindowW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Watchdog Window Value"] + #[inline(always)] + pub fn window(&self) -> WindowR { + WindowR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Watchdog Window Value"] + #[inline(always)] + pub fn window(&mut self) -> WindowW { + WindowW::new(self, 0) + } +} +#[doc = "Window Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`window::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`window::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WindowSpec; +impl crate::RegisterSpec for WindowSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`window::R`](R) reader structure"] +impl crate::Readable for WindowSpec {} +#[doc = "`write(|w| ..)` method takes [`window::W`](W) writer structure"] +impl crate::Writable for WindowSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WINDOW to value 0x00ff_ffff"] +impl crate::Resettable for WindowSpec { + const RESET_VALUE: u32 = 0x00ff_ffff; +} diff --git a/memory.x b/memory.x new file mode 100644 index 000000000..b47534f18 --- /dev/null +++ b/memory.x @@ -0,0 +1,10 @@ +/* Memory layout for MCXA276 - RAM execution with cortex-m-rt */ +MEMORY +{ + /* FLASH and RAM overlap for RAM-execution experiments. */ + FLASH : ORIGIN = 0x20000000, LENGTH = 128K + /* RAM overlaps FLASH */ + RAM : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* Leave symbol and section boundary definitions to cortex-m-rt's link.x. */ diff --git a/ram.ld b/ram.ld new file mode 100644 index 000000000..816ab6819 --- /dev/null +++ b/ram.ld @@ -0,0 +1,109 @@ +/* Simple RAM execution linker script for MCXA276 */ +MEMORY +{ + RAM : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* Pull in device default interrupt symbol aliases (e.g., CMC = DefaultHandler) */ +INCLUDE device.x + + +/* Provide core exception weak aliases if not supplied by cortex-m-rt's link.x */ +PROVIDE(NonMaskableInt = DefaultHandler); +PROVIDE(HardFault = DefaultHandler); +PROVIDE(MemoryManagement = DefaultHandler); +PROVIDE(BusFault = DefaultHandler); +PROVIDE(UsageFault = DefaultHandler); +PROVIDE(SecureFault = DefaultHandler); +PROVIDE(SVCall = DefaultHandler); +PROVIDE(DebugMonitor = DefaultHandler); +PROVIDE(PendSV = DefaultHandler); +PROVIDE(SysTick = DefaultHandler); + +/* In RAM-run we have no FLASH sidata; copy from sdata */ +__sidata = __sdata; + +/* Ensure the PAC interrupt table is kept */ +EXTERN(__INTERRUPTS); + + +/* Pull in defmt's linker script to generate the defmt table that host decoders expect */ +INCLUDE defmt.x + +ENTRY(Reset) +EXTERN(VECTOR_TABLE) +EXTERN(Reset) +EXTERN(main) + +/* Define _stack_start at end of RAM BEFORE it's used in vector table */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +SECTIONS +{ + .vector_table ORIGIN(RAM) : + { + /* Slot 0: Initial stack pointer - use our explicitly set _stack_start */ + LONG(_stack_start); + /* Slot 1: Reset vector - address of Reset function with Thumb bit set */ + LONG(Reset | 1); + /* Cortex-M33 core exceptions (slots 2-14) */ + KEEP(*(.vector_table.exceptions)); + /* Peripheral interrupt vectors provided by PAC (slots 16+) */ + KEEP(*(.vector_table.interrupts)); + } > RAM + + .text : + { + KEEP(*(.text.Reset)); + KEEP(*(.text.main)); + *(.text .text.*); + } > RAM + + /* Keep defmt table and fragments so host decoders can find metadata */ + .defmt : + { + KEEP(*(.defmt)); + KEEP(*(.defmt.*)); + } > RAM + + .rodata : + { + *(.rodata .rodata.*); + } > RAM + + .data : + { + . = ALIGN(4); + __sdata = .; + *(.data .data.*); + . = ALIGN(4); + __edata = .; + } > RAM + + /* Ensure RTT control block with "SEGGER RTT" signature is loaded to RAM */ + .rtt : + { + KEEP(*(.rtt)); + } > RAM + + /* Place uninitialized buffers (like defmt-rtt) in RAM; load is fine for RAM-run */ + .uninit : + { + *(.uninit .uninit.*); + } > RAM + + .bss : + { + . = ALIGN(4); + __sbss = .; + *(.bss .bss.*); + . = ALIGN(4); + __ebss = .; + } > RAM + + /* Discard exception unwinding info */ + /DISCARD/ : + { + *(.ARM.exidx .ARM.exidx.*); + } +} diff --git a/run.sh b/run.sh new file mode 100644 index 000000000..418dc8a24 --- /dev/null +++ b/run.sh @@ -0,0 +1,93 @@ +#!/usr/bin/env bash +set -euo pipefail + +ELF="${1:-}" +if [[ -z "${ELF}" ]]; then + echo "Usage: $0 " + exit 1 +fi +if [[ ! -f "${ELF}" ]]; then + echo "ELF not found: ${ELF}" + exit 1 +fi + +# Configurable via env +CHIP="${CHIP:-MCXA276}" +SPEED="${PROBE_SPEED:-1000}" # kHz +# Default to J-Link if PROBE not provided +PROBE_OPT=(--probe "${PROBE:-1366:0101:000600110607}") +PORT="${PROBE_RS_GDB_PORT:-1337}" + +cleanup() { + if [[ -n "${GDB_SERVER_PID:-}" ]]; then kill "${GDB_SERVER_PID}" 2>/dev/null || true; fi + [[ -n "${GDB_SCRIPT:-}" ]] && rm -f "${GDB_SCRIPT}" || true + [[ -n "${SERVER_LOG:-}" ]] && rm -f "${SERVER_LOG}" || true +} +trap cleanup EXIT + +if ! command -v probe-rs >/dev/null 2>&1; then + echo "probe-rs not found (cargo install probe-rs --features cli)" + exit 1 +fi +if ! command -v gdb-multiarch >/dev/null 2>&1; then + echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." + exit 1 +fi + +# Start probe-rs GDB server and capture its output to a log (do not hide errors) +SERVER_LOG=$(mktemp) +set +e +probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" "${PROBE_OPT[@]}" \ + >"${SERVER_LOG}" 2>&1 & +GDB_SERVER_PID=$! +set -e + +# Wait for server readiness without touching the TCP port to avoid corrupting the GDB protocol +ready="" +for _ in {1..50}; do + if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then ready=1; break; fi + if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then + echo "probe-rs gdb server failed to connect to target. Log:" >&2 + echo "----- probe-rs gdb log -----" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + exit 1 + fi + sleep 0.1 +done +if [[ -z "${ready}" ]]; then + echo "probe-rs gdb server did not report readiness. Log:" >&2 + echo "----- probe-rs gdb log -----" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + exit 1 +fi + +# GDB script: load to RAM and run, no reset +GDB_SCRIPT=$(mktemp) +cat >"${GDB_SCRIPT}" <&2 + echo "----- probe-rs gdb log -----" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + exit 1 +fi + +echo "Program loaded and started (no reset)" diff --git a/rust-toolchain.toml b/rust-toolchain.toml deleted file mode 100644 index 367cc1fc3..000000000 --- a/rust-toolchain.toml +++ /dev/null @@ -1,2 +0,0 @@ -[toolchain] -components = ["rustfmt", "clippy"] diff --git a/rustfmt.toml b/rustfmt.toml index 753065179..0720148fd 100644 --- a/rustfmt.toml +++ b/rustfmt.toml @@ -1 +1,7 @@ -max_width = 120 +# Workspace formatting preferences +edition = "2021" +# Merge and sort imports by crate; reduces noise in diffs +imports_granularity = "Crate" +group_imports = "StdExternalCrate" +# Keep defaults for everything else to stay close to rustfmt stable + diff --git a/src/adc.rs b/src/adc.rs new file mode 100644 index 000000000..dd6530605 --- /dev/null +++ b/src/adc.rs @@ -0,0 +1,376 @@ +//! ADC driver +use crate::pac; +use core::sync::atomic::{AtomicBool, Ordering}; + +use crate::pac::adc1::ctrl::{CalAvgs}; +use crate::pac::adc1::cfg::{Refsel, Pwrsel, Tprictrl, Tres, Tcmdres, HptExdi}; +use crate::pac::adc1::tctrl::{Tcmd, Tpri}; +use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode}; +use crate::pac::adc1::cmdh1::{Next, Avgs, Sts, Cmpen}; + +type Regs = pac::adc1::RegisterBlock; + +static INTERRUPT_TRIGGERED: AtomicBool = AtomicBool::new(false); +// Token-based instance pattern like embassy-imxrt +pub trait Instance { + fn ptr() -> *const Regs; +} + +/// Token for ADC1 +#[cfg(feature = "adc1")] +pub type Adc1 = crate::peripherals::ADC1; +#[cfg(feature = "adc1")] +impl Instance for crate::peripherals::ADC1 { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Adc1::ptr() + } +} + +// Also implement Instance for the Peri wrapper type +#[cfg(feature = "adc1")] +impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Adc1::ptr() + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[repr(u8)] +pub enum TriggerPriorityPolicy { + ConvPreemptImmediatelyNotAutoResumed = 0, + ConvPreemptSoftlyNotAutoResumed = 1, + ConvPreemptImmediatelyAutoRestarted = 4, + ConvPreemptSoftlyAutoRestarted = 5, + ConvPreemptImmediatelyAutoResumed = 12, + ConvPreemptSoftlyAutoResumed = 13, + ConvPreemptSubsequentlyNotAutoResumed = 2, + ConvPreemptSubsequentlyAutoRestarted = 6, + ConvPreemptSubsequentlyAutoResumed = 14, + TriggerPriorityExceptionDisabled = 16, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct LpadcConfig { + pub enable_in_doze_mode: bool, + pub conversion_average_mode: CalAvgs, + pub enable_analog_preliminary: bool, + pub power_up_delay: u8, + pub reference_voltage_source: Refsel, + pub power_level_mode: Pwrsel, + pub trigger_priority_policy: TriggerPriorityPolicy, + pub enable_conv_pause: bool, + pub conv_pause_delay: u16, + pub fifo_watermark: u8, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ConvCommandConfig { + pub sample_channel_mode: Ctype, + pub channel_number: Adch, + pub chained_next_command_number: Next, + pub enable_auto_channel_increment: bool, + pub loop_count: u8, + pub hardware_average_mode: Avgs, + pub sample_time_mode: Sts, + pub hardware_compare_mode: Cmpen, + pub hardware_compare_value_high: u32, + pub hardware_compare_value_low: u32, + pub conversion_resolution_mode: Mode, + pub enable_wait_trigger: bool, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ConvTriggerConfig { + pub target_command_id: Tcmd, + pub delay_power: u8, + pub priority: Tpri, + pub enable_hardware_trigger: bool, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ConvResult { + pub command_id_source: u32, + pub loop_count_index: u32, + pub trigger_id_source: u32, + pub conv_value: u16, +} + + +pub struct Adc { + _inst: core::marker::PhantomData, +} + +impl Adc { + /// initialize ADC + pub fn new(_inst: impl Instance, config : LpadcConfig) -> Self { + let adc = unsafe { &*I::ptr() }; + + /* Reset the module. */ + adc.ctrl().modify(|_, w| w.rst().held_in_reset()); + adc.ctrl().modify(|_, w| w.rst().released_from_reset()); + + adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset()); + + /* Disable the module before setting configuration. */ + adc.ctrl().modify(|_, w| w.adcen().disabled()); + + /* Configure the module generally. */ + if config.enable_in_doze_mode { + adc.ctrl().modify(|_, w| w.dozen().enabled()); + } else { + adc.ctrl().modify(|_, w| w.dozen().disabled()); + } + + /* Set calibration average mode. */ + adc.ctrl().modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode)); + + adc.cfg().write(|w| unsafe { + let w = if config.enable_analog_preliminary { + w.pwren().pre_enabled() + } else { + w + }; + + w.pudly().bits(config.power_up_delay) + .refsel().variant(config.reference_voltage_source) + .pwrsel().variant(config.power_level_mode) + .tprictrl().variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed | + TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted | + TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority, + TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed | + TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted | + TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority, + _ => Tprictrl::AbortCurrentOnPriority, + }) + .tres().variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted | + TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted | + TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed | + TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed | + TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted | + TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled, + _ => Tres::Disabled, + }) + .tcmdres().variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed | + TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed | + TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed | + TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled, + _ => Tcmdres::Disabled, + }) + .hpt_exdi().variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled, + _ => HptExdi::Enabled, + }) + }); + + if config.enable_conv_pause { + adc.pause().modify(|_, w| unsafe { + w.pauseen().enabled() + .pausedly().bits(config.conv_pause_delay) + }); + } else { + adc.pause().write(|w| unsafe { w.bits(0) }); + } + + adc.fctrl0().write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) }); + + // Enable ADC + adc.ctrl().modify(|_, w| w.adcen().enabled()); + + Self { _inst: core::marker::PhantomData } + } + + pub fn deinit(&self) { + let adc = unsafe { &*I::ptr() }; + adc.ctrl().modify(|_, w| w.adcen().disabled()); + } + + + pub fn get_default_config() -> LpadcConfig { + LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::NoAverage, + enable_analog_preliminary: false, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option1, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + } + } + + pub fn do_offset_calibration(&self) { + let adc = unsafe { &*I::ptr() }; + // Enable calibration mode + adc.ctrl().modify(|_, w| w.calofs().offset_calibration_request_pending()); + + // Wait for calibration to complete (polling status register) + while adc.stat().read().cal_rdy().is_not_set() {} + } + + pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32{ + let mut gcra_array = [0u32; 17]; + let mut gcalr: u32 = 0; + + for i in (1..=17).rev() { + let shift = 16 - (i - 1); + let step = 1.0 / (1u32 << shift) as f32; + let tmp = (gain_adjustment / step) as u32; + gcra_array[i - 1] = tmp; + gain_adjustment = gain_adjustment - tmp as f32 * step; + } + + for i in (1..=17).rev() { + gcalr += gcra_array[i - 1] << (i - 1); + } + gcalr + } + + pub fn do_auto_calibration(&self) { + let adc = unsafe { &*I::ptr() }; + adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending()); + + while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} + + + let mut gcca = adc.gcc0().read().gain_cal().bits() as u32; + if gcca & (((0xFFFF >> 0) + 1) >> 1) != 0 { + gcca |= !0xFFFF; + } + + let gcra = 131072.0 / (131072.0 - gcca as f32); + + // Write to GCR0 + adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); + + adc.gcr0().modify(|_, w| w.rdy().set_bit()); + + // Wait for calibration to complete (polling status register) + while adc.stat().read().cal_rdy().is_not_set() {} + } + + pub fn do_software_trigger(&self, trigger_id_mask: u32) { + let adc = unsafe { &*I::ptr() }; + adc.swtrig().write(|w| unsafe { w.bits(trigger_id_mask) }); + } + + pub fn get_default_conv_command_config(&self) -> ConvCommandConfig { + ConvCommandConfig { + sample_channel_mode: Ctype::SingleEndedASideChannel, + channel_number: Adch::SelectCh0, + chained_next_command_number: Next::NoNextCmdTerminateOnFinish, + enable_auto_channel_increment: false, + loop_count: 0, + hardware_average_mode: Avgs::NoAverage, + sample_time_mode: Sts::Sample3p5, + hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult, + hardware_compare_value_high: 0, + hardware_compare_value_low: 0, + conversion_resolution_mode: Mode::Data12Bits, + enable_wait_trigger: false, + } + } + + //TBD Need to add cmdlx and cmdhx with x {2..7} + pub fn set_conv_command_config(&self, index: u32, config: &ConvCommandConfig) { + let adc = unsafe { &*I::ptr() }; + + match index { + 1 => { + adc.cmdl1().write(|w| { + w.adch().variant(config.channel_number) + .ctype().variant(config.sample_channel_mode) + .mode().variant(config.conversion_resolution_mode) + }); + adc.cmdh1().write(|w| unsafe { + w.next().variant(config.chained_next_command_number) + .loop_().bits(config.loop_count) + .avgs().variant(config.hardware_average_mode) + .sts().variant(config.sample_time_mode) + .cmpen().variant(config.hardware_compare_mode); + if config.enable_wait_trigger { + w.wait_trig().enabled(); + } + if config.enable_auto_channel_increment { + w.lwi().enabled(); + } + w + }); + } + _ => panic!("Invalid command index: must be between 1 and 7"), + } + } + + pub fn get_default_conv_trigger_config(&self) -> ConvTriggerConfig { + ConvTriggerConfig { + target_command_id: Tcmd::NotValid, + delay_power: 0, + priority: Tpri::HighestPriority, + enable_hardware_trigger: false, + } + } + + pub fn set_conv_trigger_config(&self, trigger_id: usize, config: &ConvTriggerConfig) { + let adc = unsafe { &*I::ptr() }; + let tctrl = &adc.tctrl(trigger_id); + + tctrl.write(|w| unsafe { + let w = w.tcmd().variant(config.target_command_id); + let w = w.tdly().bits(config.delay_power); + w.tpri().variant(config.priority); + if config.enable_hardware_trigger { + w.hten().enabled() + } else { + w + } + }); + } + + pub fn do_reset_fifo(&self) { + let adc = unsafe { &*I::ptr() }; + adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset()); + } + + pub fn enable_interrupt(&self, mask: u32) { + let adc = unsafe { &*I::ptr() }; + adc.ie().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); + INTERRUPT_TRIGGERED.store(false, Ordering::SeqCst); + } + + pub fn is_interrupt_triggered(&self) -> bool { + INTERRUPT_TRIGGERED.load(Ordering::Relaxed) + } +} + +pub fn get_conv_result() -> Option { + let adc = unsafe { &*pac::Adc1::ptr() }; + let fifo = adc.resfifo0().read().bits(); + const VALID_MASK: u32 = 1 << 31; + if fifo & VALID_MASK == 0 { + return None; + } + + Some(ConvResult { + command_id_source: (fifo >> 24) & 0x0F, + loop_count_index: (fifo >> 20) & 0x0F, + trigger_id_source: (fifo >> 16) & 0x0F, + conv_value: (fifo & 0xFFFF) as u16, + }) +} + +pub fn on_interrupt() { + if get_conv_result().is_some() { + INTERRUPT_TRIGGERED.store(true, Ordering::SeqCst); + } +} + +pub struct AdcHandler; +impl crate::interrupt::typelevel::Handler for AdcHandler { + unsafe fn on_interrupt() { on_interrupt(); } +} \ No newline at end of file diff --git a/src/baremetal/mod.rs b/src/baremetal/mod.rs deleted file mode 100644 index c03b9538b..000000000 --- a/src/baremetal/mod.rs +++ /dev/null @@ -1,6 +0,0 @@ -use core::panic::PanicInfo; - -#[panic_handler] -fn panic(_info: &PanicInfo) -> ! { - loop {} -} diff --git a/src/board.rs b/src/board.rs new file mode 100644 index 000000000..fa679e82c --- /dev/null +++ b/src/board.rs @@ -0,0 +1,14 @@ +use crate::{clocks, pac, pins}; + +/// Initialize clocks and pin muxing for UART2 debug console. +pub unsafe fn init_uart2(p: &pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_uart2_port2(p); + pins::configure_uart2_pins_port2(); + clocks::select_uart2_clock(p); +} + +/// Initialize clocks for the LED GPIO/PORT used by the blink example. +pub unsafe fn init_led(p: &pac::Peripherals) { + clocks::enable_led_port(p); +} diff --git a/src/clocks.rs b/src/clocks.rs new file mode 100644 index 000000000..5336c3efe --- /dev/null +++ b/src/clocks.rs @@ -0,0 +1,136 @@ +//! Clock control helpers (no magic numbers, PAC field access only). +//! Provides reusable gate abstractions for peripherals used by the examples. +use crate::pac; + +/// Trait describing an AHB clock gate that can be toggled through MRCC. +pub trait Gate { + /// Enable the clock gate. + unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock); + + /// Return whether the clock gate is currently enabled. + fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool; +} + +/// Enable a clock gate for the given peripheral set. +#[inline] +pub unsafe fn enable(peripherals: &pac::Peripherals) { + let mrcc = &peripherals.mrcc0; + G::enable(mrcc); + while !G::is_enabled(mrcc) {} + core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); +} + +/// Check whether a gate is currently enabled. +#[inline] +pub fn is_enabled(peripherals: &pac::Peripherals) -> bool { + G::is_enabled(&peripherals.mrcc0) +} + +macro_rules! impl_cc_gate { + ($name:ident, $reg:ident, $field:ident) => { + pub struct $name; + + impl Gate for $name { + #[inline] + unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) { + mrcc.$reg().modify(|_, w| w.$field().enabled()); + } + + #[inline] + fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool { + mrcc.$reg().read().$field().is_enabled() + } + } + }; +} + +pub mod gate { + use super::*; + + impl_cc_gate!(Port2, mrcc_glb_cc1, port2); + impl_cc_gate!(Port3, mrcc_glb_cc1, port3); + impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0); + impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2); + impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3); + impl_cc_gate!(Port1, mrcc_glb_cc1, port1); + impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1); +} + +/// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. +pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) { + enable::(peripherals); + enable::(peripherals); +} + +/// Convenience helper enabling the PORT3 and GPIO3 gates used by the LED in the examples. +pub unsafe fn enable_led_port(peripherals: &pac::Peripherals) { + enable::(peripherals); + enable::(peripherals); +} + +/// Convenience helper enabling the OSTIMER0 clock gate. +pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { + enable::(peripherals); +} + +pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { + // Use FRO_LF_DIV (already running) MUX=0 DIV=0 + let mrcc = &peripherals.mrcc0; + mrcc.mrcc_lpuart2_clksel() + .write(|w| w.mux().clkroot_func_0()); + mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); +} + +pub unsafe fn ensure_frolf_running(peripherals: &pac::Peripherals) { + // Ensure FRO_LF divider clock is running (reset default HALT=1 stops it) + let sys = &peripherals.syscon; + sys.frolfdiv().modify(|_, w| { + // DIV defaults to 0; keep it explicit and clear HALT + unsafe { w.div().bits(0) }.halt().run() + }); +} + +/// Compute the FRO_LF_DIV output frequency currently selected for LPUART2. +/// Assumes select_uart2_clock() has chosen MUX=0 (FRO_LF_DIV) and DIV is set in SYSCON.FRO_LF_DIV. +pub unsafe fn uart2_src_hz(peripherals: &pac::Peripherals) -> u32 { + // SYSCON.FRO_LF_DIV: DIV field is simple divider: freq_out = 12_000_000 / (DIV+1) for many NXP parts. + // On MCXA276 FRO_LF base is 12 MHz; our init keeps DIV=0, so result=12_000_000. + // Read it anyway for future generality. + let div = peripherals.syscon.frolfdiv().read().div().bits() as u32; + let base = 12_000_000u32; + base / (div + 1) +} + +/// Enable clock gate and release reset for OSTIMER0. +/// Select OSTIMER0 clock source = 1 MHz root (working bring-up configuration). +pub unsafe fn select_ostimer0_clock_1m(peripherals: &pac::Peripherals) { + let mrcc = &peripherals.mrcc0; + mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); +} + +pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) { + let vbat = &peripherals.vbat0; + // Enable FRO16K oscillator + vbat.froctla().modify(|_, w| w.fro_en().set_bit()); + + // Lock the control register + vbat.frolcka().modify(|_, w| w.lock().set_bit()); + + // Enable clock outputs to both VSYS and VDD_CORE domains + // Bit 0: clk_16k0 to VSYS domain + // Bit 1: clk_16k1 to VDD_CORE domain + vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) }); +} + +pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { + enable::(peripherals); + enable::(peripherals); +} + +pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { + // Use FRO_LF_DIV (already running) MUX=0 DIV=0 + let mrcc = &peripherals.mrcc0; + mrcc.mrcc_adc_clksel() + .write(|w| w.mux().clkroot_func_0()); + mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); +} \ No newline at end of file diff --git a/src/config.rs b/src/config.rs new file mode 100644 index 000000000..93aed5a99 --- /dev/null +++ b/src/config.rs @@ -0,0 +1,20 @@ +// HAL configuration (minimal), mirroring embassy-imxrt style + +use crate::interrupt::Priority; + +#[non_exhaustive] +pub struct Config { + pub time_interrupt_priority: Priority, + pub rtc_interrupt_priority: Priority, + pub adc_interrupt_priority: Priority, +} + +impl Default for Config { + fn default() -> Self { + Self { + time_interrupt_priority: Priority::from(0), + rtc_interrupt_priority: Priority::from(0), + adc_interrupt_priority: Priority::from(0), + } + } +} diff --git a/src/gpio.rs b/src/gpio.rs new file mode 100644 index 000000000..08f375cba --- /dev/null +++ b/src/gpio.rs @@ -0,0 +1,246 @@ +//! GPIO driver built around a type-erased `Flex` pin, similar to other Embassy HALs. +//! The exported `Output`/`Input` drivers own a `Flex` so they no longer depend on the +//! concrete pin type. + +use core::marker::PhantomData; + +use crate::{pac, pins as pin_config}; + +/// Logical level for GPIO pins. +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum Level { + Low, + High, +} + +pub type Gpio = crate::peripherals::GPIO; + +/// Type-erased representation of a GPIO pin. +#[derive(Copy, Clone)] +pub struct AnyPin { + port: u8, + pin: u8, + gpio: *const pac::gpio0::RegisterBlock, +} + +impl AnyPin { + /// Create an `AnyPin` from raw components. + pub fn new(port: u8, pin: u8, gpio: *const pac::gpio0::RegisterBlock) -> Self { + Self { port, pin, gpio } + } + + #[inline(always)] + fn mask(&self) -> u32 { + 1u32 << self.pin + } + + #[inline(always)] + fn gpio(&self) -> &'static pac::gpio0::RegisterBlock { + unsafe { &*self.gpio } + } + + #[inline(always)] + pub fn port_index(&self) -> u8 { + self.port + } + + #[inline(always)] + pub fn pin_index(&self) -> u8 { + self.pin + } +} + +/// Type-level trait implemented by concrete pin ZSTs. +pub trait PinId { + fn port_index() -> u8; + fn pin_index() -> u8; + fn gpio_ptr() -> *const pac::gpio0::RegisterBlock; + + fn set_mux_gpio() { + unsafe { pin_config::set_pin_mux_gpio(Self::port_index(), Self::pin_index()) } + } + + fn degrade() -> AnyPin { + AnyPin::new(Self::port_index(), Self::pin_index(), Self::gpio_ptr()) + } +} + +pub mod pins { + use super::{pac, AnyPin, PinId}; + + macro_rules! define_pin { + ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => { + pub struct $Name; + impl super::PinId for $Name { + #[inline(always)] + fn port_index() -> u8 { + $port + } + #[inline(always)] + fn pin_index() -> u8 { + $pin + } + #[inline(always)] + fn gpio_ptr() -> *const pac::gpio0::RegisterBlock { + pac::$GpioBlk::ptr() + } + } + + impl $Name { + /// Convenience helper to obtain a type-erased handle to this pin. + pub fn degrade() -> AnyPin { + ::degrade() + } + + pub fn set_mux_gpio() { + ::set_mux_gpio() + } + } + }; + } + + // Extend this list as more pins are needed. + define_pin!(PIO3_18, 3, 18, Gpio3); +} + +/// A flexible pin that can be configured as input or output. +pub struct Flex<'d> { + pin: AnyPin, + _marker: PhantomData<&'d mut ()>, +} + +impl<'d> Flex<'d> { + pub fn new(pin: AnyPin) -> Self { + Self { + pin, + _marker: PhantomData, + } + } + + #[inline(always)] + fn gpio(&self) -> &'static pac::gpio0::RegisterBlock { + self.pin.gpio() + } + + #[inline(always)] + fn mask(&self) -> u32 { + self.pin.mask() + } + + pub fn set_as_input(&mut self) { + let mask = self.mask(); + let gpio = self.gpio(); + gpio.pddr() + .modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); + } + + pub fn set_as_output(&mut self) { + let mask = self.mask(); + let gpio = self.gpio(); + gpio.pddr() + .modify(|r, w| unsafe { w.bits(r.bits() | mask) }); + } + + pub fn set_high(&mut self) { + self.gpio().psor().write(|w| unsafe { w.bits(self.mask()) }); + } + + pub fn set_low(&mut self) { + self.gpio().pcor().write(|w| unsafe { w.bits(self.mask()) }); + } + + pub fn set_level(&mut self, level: Level) { + match level { + Level::High => self.set_high(), + Level::Low => self.set_low(), + } + } + + pub fn toggle(&mut self) { + self.gpio().ptor().write(|w| unsafe { w.bits(self.mask()) }); + } + + pub fn is_high(&self) -> bool { + (self.gpio().pdir().read().bits() & self.mask()) != 0 + } + + pub fn is_low(&self) -> bool { + !self.is_high() + } +} + +/// GPIO output driver that owns a `Flex` pin. +pub struct Output<'d> { + flex: Flex<'d>, +} + +impl<'d> Output<'d> { + pub fn new(pin: AnyPin, initial: Level) -> Self { + let mut flex = Flex::new(pin); + flex.set_level(initial); + flex.set_as_output(); + Self { flex } + } + + #[inline] + pub fn set_high(&mut self) { + self.flex.set_high(); + } + + #[inline] + pub fn set_low(&mut self) { + self.flex.set_low(); + } + + #[inline] + pub fn set_level(&mut self, level: Level) { + self.flex.set_level(level); + } + + #[inline] + pub fn toggle(&mut self) { + self.flex.toggle(); + } + + #[inline] + pub fn is_set_high(&self) -> bool { + self.flex.is_high() + } + + #[inline] + pub fn is_set_low(&self) -> bool { + !self.is_set_high() + } + + /// Expose the inner `Flex` if callers need to reconfigure the pin. + pub fn into_flex(self) -> Flex<'d> { + self.flex + } +} + +/// GPIO input driver that owns a `Flex` pin. +pub struct Input<'d> { + flex: Flex<'d>, +} + +impl<'d> Input<'d> { + pub fn new(pin: AnyPin) -> Self { + let mut flex = Flex::new(pin); + flex.set_as_input(); + Self { flex } + } + + #[inline] + pub fn is_high(&self) -> bool { + self.flex.is_high() + } + + #[inline] + pub fn is_low(&self) -> bool { + self.flex.is_low() + } + + pub fn into_flex(self) -> Flex<'d> { + self.flex + } +} diff --git a/src/interrupt.rs b/src/interrupt.rs new file mode 100644 index 000000000..8226f01ab --- /dev/null +++ b/src/interrupt.rs @@ -0,0 +1,349 @@ +//! Minimal interrupt helpers mirroring embassy-imxrt style for OS_EVENT and LPUART2. +//! Type-level interrupt traits and bindings are provided by the +//! `embassy_hal_internal::interrupt_mod!` macro via the generated module below. + +mod generated { + embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1); +} + +pub use generated::interrupt::typelevel; +pub use generated::interrupt::Priority; + +use crate::pac::Interrupt; +use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; + +/// Trait for configuring and controlling interrupts. +/// +/// This trait provides a consistent interface for interrupt management across +/// different interrupt sources, similar to embassy-imxrt's InterruptExt. +pub trait InterruptExt { + /// Clear any pending interrupt in NVIC. + fn unpend(&self); + + /// Set NVIC priority for this interrupt. + fn set_priority(&self, priority: Priority); + + /// Enable this interrupt in NVIC. + /// + /// # Safety + /// This function is unsafe because it can enable interrupts that may not be + /// properly configured, potentially leading to undefined behavior. + unsafe fn enable(&self); + + /// Disable this interrupt in NVIC. + /// + /// # Safety + /// This function is unsafe because disabling interrupts may leave the system + /// in an inconsistent state if the interrupt was expected to fire. + unsafe fn disable(&self); + + /// Check if the interrupt is pending in NVIC. + fn is_pending(&self) -> bool; +} + +#[derive(Clone, Copy, Debug, Default)] +pub struct DefaultHandlerSnapshot { + pub vector: u16, + pub count: u32, + pub cfsr: u32, + pub hfsr: u32, + pub stacked_pc: u32, + pub stacked_lr: u32, + pub stacked_sp: u32, +} + +static LAST_DEFAULT_VECTOR: AtomicU16 = AtomicU16::new(0); +static LAST_DEFAULT_COUNT: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_CFSR: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_HFSR: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_PC: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_LR: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_SP: AtomicU32 = AtomicU32::new(0); + +#[inline] +pub fn default_handler_snapshot() -> DefaultHandlerSnapshot { + DefaultHandlerSnapshot { + vector: LAST_DEFAULT_VECTOR.load(Ordering::Relaxed), + count: LAST_DEFAULT_COUNT.load(Ordering::Relaxed), + cfsr: LAST_DEFAULT_CFSR.load(Ordering::Relaxed), + hfsr: LAST_DEFAULT_HFSR.load(Ordering::Relaxed), + stacked_pc: LAST_DEFAULT_PC.load(Ordering::Relaxed), + stacked_lr: LAST_DEFAULT_LR.load(Ordering::Relaxed), + stacked_sp: LAST_DEFAULT_SP.load(Ordering::Relaxed), + } +} + +#[inline] +pub fn clear_default_handler_snapshot() { + LAST_DEFAULT_VECTOR.store(0, Ordering::Relaxed); + LAST_DEFAULT_COUNT.store(0, Ordering::Relaxed); + LAST_DEFAULT_CFSR.store(0, Ordering::Relaxed); + LAST_DEFAULT_HFSR.store(0, Ordering::Relaxed); + LAST_DEFAULT_PC.store(0, Ordering::Relaxed); + LAST_DEFAULT_LR.store(0, Ordering::Relaxed); + LAST_DEFAULT_SP.store(0, Ordering::Relaxed); +} + +/// OS_EVENT interrupt helper with methods similar to embassy-imxrt's InterruptExt. +pub struct OsEvent; +pub const OS_EVENT: OsEvent = OsEvent; + +impl InterruptExt for OsEvent { + /// Clear any pending OS_EVENT in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::OS_EVENT); + } + + /// Set NVIC priority for OS_EVENT. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::OS_EVENT, u8::from(priority)); + } + } + + /// Enable OS_EVENT in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::OS_EVENT); + } + + /// Disable OS_EVENT in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::OS_EVENT); + } + + /// Check if OS_EVENT is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::OS_EVENT) + } +} + +impl OsEvent { + /// Configure OS_EVENT interrupt for timer operation. + /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled. + /// Also performs a software event to wake any pending WFE. + pub fn configure_for_timer(&self, priority: Priority) { + // Configure NVIC + self.unpend(); + self.set_priority(priority); + unsafe { + self.enable(); + } + + // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run) + // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not. + unsafe { + cortex_m::interrupt::enable(); + } + + // Wake any executor WFE that might be sleeping when we armed the first deadline + cortex_m::asm::sev(); + } +} + +/// LPUART2 interrupt helper with methods similar to embassy-imxrt's InterruptExt. +pub struct Lpuart2; +pub const LPUART2: Lpuart2 = Lpuart2; + +impl InterruptExt for Lpuart2 { + /// Clear any pending LPUART2 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::LPUART2); + } + + /// Set NVIC priority for LPUART2. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::LPUART2, u8::from(priority)); + } + } + + /// Enable LPUART2 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::LPUART2); + } + + /// Disable LPUART2 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::LPUART2); + } + + /// Check if LPUART2 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::LPUART2) + } +} + +impl Lpuart2 { + /// Configure LPUART2 interrupt for UART operation. + /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled. + pub fn configure_for_uart(&self, priority: Priority) { + // Configure NVIC + self.unpend(); + self.set_priority(priority); + unsafe { + self.enable(); + } + + // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run) + // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not. + unsafe { + cortex_m::interrupt::enable(); + } + } + + /// Install LPUART2 handler into the RAM vector table. + /// Safety: See `install_irq_handler`. + pub unsafe fn install_handler(&self, handler: unsafe extern "C" fn()) { + install_irq_handler(Interrupt::LPUART2, handler); + } +} + +pub struct Rtc; +pub const RTC: Rtc = Rtc; + +impl InterruptExt for Rtc { + /// Clear any pending RTC in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::RTC); + } + + /// Set NVIC priority for RTC. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::RTC, u8::from(priority)); + } + } + + /// Enable RTC in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::RTC); + } + + /// Disable RTC in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::RTC); + } + + /// Check if RTC is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC) + } +} + +pub struct Adc; +pub const ADC1: Adc = Adc; + +impl InterruptExt for Adc { + /// Clear any pending ADC1 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::ADC1); + } + + /// Set NVIC priority for ADC1. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::ADC1, u8::from(priority)); + } + } + + /// Enable ADC1 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::ADC1); + } + + /// Disable ADC1 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::ADC1); + } + + /// Check if ADC1 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC1) + } +} + +/// Set VTOR (Vector Table Offset) to a RAM-based vector table. +/// Pass a pointer to the first word in the RAM table (stack pointer slot 0). +/// Safety: Caller must ensure the RAM table is valid and aligned as required by the core. +pub unsafe fn vtor_set_ram_vector_base(base: *const u32) { + core::ptr::write_volatile(0xE000_ED08 as *mut u32, base as u32); +} + +/// Install an interrupt handler into the current VTOR-based vector table. +/// This writes the function pointer at index 16 + irq number. +/// Safety: Caller must ensure VTOR points at a writable RAM table and that `handler` +/// has the correct ABI and lifetime. +pub unsafe fn install_irq_handler(irq: Interrupt, handler: unsafe extern "C" fn()) { + let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32; + let idx = 16 + (irq as isize as usize); + core::ptr::write_volatile(vtor_base.add(idx), handler as usize as u32); +} + +impl OsEvent { + /// Convenience to install the OS_EVENT handler into the RAM vector table. + /// Safety: See `install_irq_handler`. + pub unsafe fn install_handler(&self, handler: extern "C" fn()) { + install_irq_handler(Interrupt::OS_EVENT, handler); + } +} + +/// Install OS_EVENT handler by raw address. Useful to avoid fn pointer type mismatches. +/// Safety: Caller must ensure the address is a valid `extern "C" fn()` handler. +pub unsafe fn os_event_install_handler_raw(handler_addr: usize) { + let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32; + let idx = 16 + (Interrupt::OS_EVENT as isize as usize); + core::ptr::write_volatile(vtor_base.add(idx), handler_addr as u32); +} + +/// Provide a conservative default IRQ handler that avoids wedging the system. +/// It clears all NVIC pending bits and returns, so spurious or reserved IRQs +/// don’t trap the core in an infinite WFI loop during bring-up. +#[no_mangle] +pub unsafe extern "C" fn DefaultHandler() { + let active = core::ptr::read_volatile(0xE000_ED04 as *const u32) & 0x1FF; + let cfsr = core::ptr::read_volatile(0xE000_ED28 as *const u32); + let hfsr = core::ptr::read_volatile(0xE000_ED2C as *const u32); + + let sp = cortex_m::register::msp::read(); + let stacked = sp as *const u32; + // Stacked registers follow ARMv8-M procedure call standard order + let stacked_pc = unsafe { stacked.add(6).read() }; + let stacked_lr = unsafe { stacked.add(5).read() }; + + LAST_DEFAULT_VECTOR.store(active as u16, Ordering::Relaxed); + LAST_DEFAULT_CFSR.store(cfsr, Ordering::Relaxed); + LAST_DEFAULT_HFSR.store(hfsr, Ordering::Relaxed); + LAST_DEFAULT_COUNT.fetch_add(1, Ordering::Relaxed); + LAST_DEFAULT_PC.store(stacked_pc, Ordering::Relaxed); + LAST_DEFAULT_LR.store(stacked_lr, Ordering::Relaxed); + LAST_DEFAULT_SP.store(sp, Ordering::Relaxed); + + // Do nothing here: on some MCUs/TrustZone setups, writing NVIC from a spurious + // handler can fault if targeting the Secure bank. Just return. + cortex_m::asm::dsb(); + cortex_m::asm::isb(); +} diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 000000000..eb4727106 --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,165 @@ +#![no_std] + +pub mod clocks; // still provide clock helpers +#[cfg(feature = "gpio")] +pub mod gpio; +pub mod pins; // pin mux helpers +pub mod reset; // reset control helpers + +pub mod config; +pub mod interrupt; +pub mod ostimer; +pub mod uart; +pub mod lpuart; +pub mod rtc; +pub mod adc; + +embassy_hal_internal::peripherals!( + #[cfg(feature = "lpuart2")] + LPUART2, + #[cfg(feature = "ostimer0")] + OSTIMER0, + #[cfg(feature = "gpio")] + GPIO, + #[cfg(feature = "rtc0")] + RTC0, + #[cfg(feature = "adc1")] + ADC1, +); + +/// Get access to the PAC Peripherals for low-level register access. +/// This is a lazy-initialized singleton that can be called after init(). +#[allow(static_mut_refs)] +pub fn pac() -> &'static pac::Peripherals { + // SAFETY: We only call this after init(), and the PAC is a singleton. + // The embassy peripheral tokens ensure we don't have multiple mutable accesses. + unsafe { + static mut PAC_INSTANCE: Option = None; + if PAC_INSTANCE.is_none() { + PAC_INSTANCE = Some(pac::Peripherals::steal()); + } + PAC_INSTANCE.as_ref().unwrap() + } +} + +pub use cortex_m_rt; +pub use mcxa276_pac as pac; +// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. + +// Re-export interrupt traits and types +pub use interrupt::InterruptExt; +#[cfg(feature = "ostimer0")] +pub use ostimer::Ostimer0 as Ostimer0Token; +#[cfg(feature = "lpuart2")] +pub use uart::Lpuart2 as Uart2Token; +#[cfg(feature = "rtc0")] +pub use rtc::Rtc0 as Rtc0Token; +#[cfg(feature = "adc1")] +pub use adc::Adc1 as Adc1Token; +#[cfg(feature = "gpio")] +pub use gpio::{pins::*, AnyPin, Flex, Gpio as GpioToken, Input, Level, Output}; + +/// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. +/// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). +#[allow(unused_variables)] +pub fn init(cfg: crate::config::Config) -> Peripherals { + let peripherals = Peripherals::take(); + #[cfg(feature = "ostimer0")] + { + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority); + } + #[cfg(feature = "rtc0")] + { + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); + } + #[cfg(feature = "adc1")] + { + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority); + } + peripherals +} + +/// Optional hook called by cortex-m-rt before RAM init. +/// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state +/// left by soft resets/debug sessions. +/// +/// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor' +/// feature is incompatible with our setup because it expects __vector_table to be +/// defined differently than how our RAM-based linker script arranges it. +#[no_mangle] +pub unsafe extern "C" fn __pre_init() { + // Set the VTOR to point to the interrupt vector table in RAM + // This is required since code runs from RAM on this MCU + crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32); + + // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs. + let nvic = &*cortex_m::peripheral::NVIC::PTR; + for i in 0..4 { + // 4 words x 32 = 128 IRQs + nvic.icer[i].write(0xFFFF_FFFF); + nvic.icpr[i].write(0xFFFF_FFFF); + } + // Do NOT touch peripheral registers here: clocks may be off and accesses can fault. + crate::interrupt::clear_default_handler_snapshot(); +} + +/// Internal helper to dispatch a type-level interrupt handler. +#[inline(always)] +#[doc(hidden)] +pub unsafe fn __handle_interrupt() +where + T: crate::interrupt::typelevel::Interrupt, + H: crate::interrupt::typelevel::Handler, +{ + H::on_interrupt(); +} + +/// Macro to bind interrupts to handlers, similar to embassy-imxrt. +/// +/// Example: +/// - Bind OS_EVENT to the OSTIMER time-driver handler +/// bind_interrupts!(struct Irqs { OS_EVENT => crate::ostimer::time_driver::OsEventHandler; }); +#[macro_export] +macro_rules! bind_interrupts { + ($(#[$attr:meta])* $vis:vis struct $name:ident { + $( + $(#[cfg($cond_irq:meta)])? + $irq:ident => $( + $(#[cfg($cond_handler:meta)])? + $handler:ty + ),*; + )* + }) => { + #[derive(Copy, Clone)] + $(#[$attr])* + $vis struct $name; + + $( + #[allow(non_snake_case)] + #[no_mangle] + $(#[cfg($cond_irq)])? + unsafe extern "C" fn $irq() { + unsafe { + $( + $(#[cfg($cond_handler)])? + <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt(); + )* + } + } + + $(#[cfg($cond_irq)])? + $crate::bind_interrupts!(@inner + $( + $(#[cfg($cond_handler)])? + unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {} + )* + ); + )* + }; + (@inner $($t:tt)*) => { + $($t)* + } +} diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs new file mode 100644 index 000000000..03673d975 --- /dev/null +++ b/src/lpuart/buffered.rs @@ -0,0 +1,686 @@ +use core::future::poll_fn; +use core::marker::PhantomData; +use core::sync::atomic::{AtomicBool, Ordering}; +use core::task::Poll; + +use embassy_hal_internal::atomic_ring_buffer::RingBuffer; +use embassy_hal_internal::Peri; +use embassy_sync::waitqueue::AtomicWaker; + +use super::*; +use crate::interrupt; + +// ============================================================================ +// STATIC STATE MANAGEMENT +// ============================================================================ + +/// State for buffered LPUART operations +pub struct State { + rx_waker: AtomicWaker, + rx_buf: RingBuffer, + tx_waker: AtomicWaker, + tx_buf: RingBuffer, + tx_done: AtomicBool, + initialized: AtomicBool, +} + +impl State { + /// Create a new state instance + pub const fn new() -> Self { + Self { + rx_waker: AtomicWaker::new(), + rx_buf: RingBuffer::new(), + tx_waker: AtomicWaker::new(), + tx_buf: RingBuffer::new(), + tx_done: AtomicBool::new(true), + initialized: AtomicBool::new(false), + } + } +} +// ============================================================================ +// BUFFERED DRIVER STRUCTURES +// ============================================================================ + +/// Buffered LPUART driver +pub struct BufferedLpuart<'a> { + tx: BufferedLpuartTx<'a>, + rx: BufferedLpuartRx<'a>, +} + +/// Buffered LPUART TX driver +pub struct BufferedLpuartTx<'a> { + info: Info, + state: &'static State, + _tx_pin: Peri<'a, AnyPin>, +} + +/// Buffered LPUART RX driver +pub struct BufferedLpuartRx<'a> { + info: Info, + state: &'static State, + _rx_pin: Peri<'a, AnyPin>, +} + +// ============================================================================ +// BUFFERED LPUART IMPLEMENTATION +// ============================================================================ + +impl<'a> BufferedLpuart<'a> { + /// Create a new buffered LPUART instance + pub fn new( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + // Configure pins + tx_pin.as_tx(); + rx_pin.as_rx(); + + // Convert pins to AnyPin + let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); + let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); + + let state = T::buffered_state(); + + // Initialize the peripheral + Self::init::( + Some(&tx_pin), + Some(&rx_pin), + None, + None, + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { + tx: BufferedLpuartTx { + info: T::info(), + state, + _tx_pin: tx_pin, + }, + rx: BufferedLpuartRx { + info: T::info(), + state, + _rx_pin: rx_pin, + }, + }) + } + + /// Create a new buffered LPUART with flexible pin configuration + pub fn new_with_pins( + _inner: Peri<'a, T>, + tx_pin: Option>>, + rx_pin: Option>>, + rts_pin: Option>>, + cts_pin: Option>>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + // Configure pins if provided + let tx_pin = tx_pin.map(|pin| { + pin.as_tx(); + let converted: Peri<'a, AnyPin> = pin.into(); + converted + }); + + let rx_pin = rx_pin.map(|pin| { + pin.as_rx(); + let converted: Peri<'a, AnyPin> = pin.into(); + converted + }); + + let rts_pin = rts_pin.map(|pin| { + pin.as_rts(); + let converted: Peri<'a, AnyPin> = pin.into(); + converted + }); + + let cts_pin = cts_pin.map(|pin| { + pin.as_cts(); + let converted: Peri<'a, AnyPin> = pin.into(); + converted + }); + + let state = T::buffered_state(); + + // Initialize the peripheral + Self::init::( + tx_pin.as_ref(), + rx_pin.as_ref(), + rts_pin.as_ref(), + cts_pin.as_ref(), + tx_buffer, + rx_buffer, + config, + )?; + + // Create TX and RX instances + let (tx, rx) = if let (Some(tx_pin), Some(rx_pin)) = (tx_pin, rx_pin) { + ( + BufferedLpuartTx { + info: T::info(), + state, + _tx_pin: tx_pin, + }, + BufferedLpuartRx { + info: T::info(), + state, + _rx_pin: rx_pin, + }, + ) + } else { + return Err(Error::InvalidArgument); + }; + + Ok(Self { tx, rx }) + } + + fn init( + _tx: Option<&Peri<'a, AnyPin>>, + _rx: Option<&Peri<'a, AnyPin>>, + _rts: Option<&Peri<'a, AnyPin>>, + _cts: Option<&Peri<'a, AnyPin>>, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + mut config: Config, + ) -> Result<()> { + let regs = T::info().regs; + let state = T::buffered_state(); + + // Check if already initialized + if state.initialized.load(Ordering::Relaxed) { + return Err(Error::InvalidArgument); + } + + // Initialize ring buffers + assert!(!tx_buffer.is_empty()); + unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), tx_buffer.len()) } + + assert!(!rx_buffer.is_empty()); + unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_buffer.len()) } + + // Mark as initialized + state.initialized.store(true, Ordering::Relaxed); + + // Enable TX and RX for buffered operation + config.enable_tx = true; + config.enable_rx = true; + + // Perform standard initialization + perform_software_reset(regs); + disable_transceiver(regs); + configure_baudrate(regs, config.baudrate_bps, config.clock)?; + configure_frame_format(regs, &config); + configure_control_settings(regs, &config); + configure_fifo(regs, &config); + clear_all_status_flags(regs); + configure_flow_control(regs, &config); + configure_bit_order(regs, config.msb_firs); + + // Enable interrupts for buffered operation + cortex_m::interrupt::free(|_| { + regs.ctrl().modify(|_, w| { + w.rie() + .enabled() // RX interrupt + .orie() + .enabled() // Overrun interrupt + .peie() + .enabled() // Parity error interrupt + .feie() + .enabled() // Framing error interrupt + .neie() + .enabled() // Noise error interrupt + }); + }); + + // Enable the transceiver + enable_transceiver(regs, config.enable_tx, config.enable_rx); + + // Enable the interrupt + // unsafe { + // // TODO: Used the propper interrupt enable method for the specific LPUART instance + // // T::Interrupt::enable(); + // } + + Ok(()) + } + + /// Split the buffered LPUART into separate TX and RX parts + pub fn split(self) -> (BufferedLpuartTx<'a>, BufferedLpuartRx<'a>) { + (self.tx, self.rx) + } + + /// Get mutable references to TX and RX parts + pub fn split_ref(&mut self) -> (&mut BufferedLpuartTx<'a>, &mut BufferedLpuartRx<'a>) { + (&mut self.tx, &mut self.rx) + } +} + +// ============================================================================ +// BUFFERED TX IMPLEMENTATION +// ============================================================================ + +impl<'a> BufferedLpuartTx<'a> { + /// Create a new TX-only buffered LPUART + pub fn new( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); + + let info = T::info(); + let state = T::buffered_state(); + + // Check if already initialized + if state.initialized.load(Ordering::Relaxed) { + return Err(Error::InvalidArgument); + } + + // Initialize TX ring buffer only + unsafe { + let tx_buf = &state.tx_buf as *const _ as *mut RingBuffer; + (*tx_buf).init(tx_buffer.as_mut_ptr(), tx_buffer.len()); + } + + state.initialized.store(true, Ordering::Relaxed); + + // Initialize with TX only + BufferedLpuart::init::( + Some(&tx_pin), + None, + None, + None, + tx_buffer, + &mut [], // Empty RX buffer + config, + )?; + + Ok(Self { + info, + state, + _tx_pin: tx_pin, + }) + } + + /// Write data asynchronously + pub async fn write(&mut self, buf: &[u8]) -> Result { + let mut written = 0; + + for &byte in buf { + // Wait for space in the buffer + poll_fn(|cx| { + self.state.tx_waker.register(cx.waker()); + + let mut writer = unsafe { self.state.tx_buf.writer() }; + if writer.push_one(byte) { + // Enable TX interrupt to start transmission + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); + }); + Poll::Ready(Ok(())) + } else { + Poll::Pending + } + }) + .await?; + + written += 1; + } + + Ok(written) + } + + /// Flush the TX buffer and wait for transmission to complete + pub async fn flush(&mut self) -> Result<()> { + // Wait for TX buffer to empty and transmission to complete + poll_fn(|cx| { + self.state.tx_waker.register(cx.waker()); + + let tx_empty = self.state.tx_buf.is_empty(); + let fifo_empty = self.info.regs.water().read().txcount().bits() == 0; + let tc_complete = self.info.regs.stat().read().tc().is_complete(); + + if tx_empty && fifo_empty && tc_complete { + Poll::Ready(Ok(())) + } else { + // Enable appropriate interrupt + cortex_m::interrupt::free(|_| { + if !tx_empty { + self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); + } else { + self.info.regs.ctrl().modify(|_, w| w.tcie().enabled()); + } + }); + Poll::Pending + } + }) + .await + } + + /// Try to write without blocking + pub fn try_write(&mut self, buf: &[u8]) -> Result { + let mut writer = unsafe { self.state.tx_buf.writer() }; + let mut written = 0; + + for &byte in buf { + if writer.push_one(byte) { + written += 1; + } else { + break; + } + } + + if written > 0 { + // Enable TX interrupt to start transmission + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); + }); + } + + Ok(written) + } +} + +// ============================================================================ +// BUFFERED RX IMPLEMENTATION +// ============================================================================ + +impl<'a> BufferedLpuartRx<'a> { + /// Create a new RX-only buffered LPUART + pub fn new( + _inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + rx_pin.as_rx(); + let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); + + let info = T::info(); + let state = T::buffered_state(); + + // Check if already initialized + if state.initialized.load(Ordering::Relaxed) { + return Err(Error::InvalidArgument); + } + + // Initialize RX ring buffer only + unsafe { + let rx_buf = &state.rx_buf as *const _ as *mut RingBuffer; + (*rx_buf).init(rx_buffer.as_mut_ptr(), rx_buffer.len()); + } + + state.initialized.store(true, Ordering::Relaxed); + + // Initialize with RX only + BufferedLpuart::init::( + None, + Some(&rx_pin), + None, + None, + &mut [], // Empty TX buffer + rx_buffer, + config, + )?; + + Ok(Self { + info, + state, + _rx_pin: rx_pin, + }) + } + + /// Read data asynchronously + pub async fn read(&mut self, buf: &mut [u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + + let mut read = 0; + + // Try to read available data + poll_fn(|cx| { + self.state.rx_waker.register(cx.waker()); + + // Disable RX interrupt while reading from buffer + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().disabled()); + }); + + let mut reader = unsafe { self.state.rx_buf.reader() }; + let available = reader.pop(|data| { + let to_copy = core::cmp::min(data.len(), buf.len() - read); + if to_copy > 0 { + buf[read..read + to_copy].copy_from_slice(&data[..to_copy]); + read += to_copy; + } + to_copy + }); + + // Re-enable RX interrupt + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().enabled()); + }); + + if read > 0 { + Poll::Ready(Ok(read)) + } else if available == 0 { + Poll::Pending + } else { + Poll::Ready(Ok(0)) + } + }) + .await + } + + /// Try to read without blocking + pub fn try_read(&mut self, buf: &mut [u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + + // Disable RX interrupt while reading from buffer + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().disabled()); + }); + + let mut reader = unsafe { self.state.rx_buf.reader() }; + let read = reader.pop(|data| { + let to_copy = core::cmp::min(data.len(), buf.len()); + if to_copy > 0 { + buf[..to_copy].copy_from_slice(&data[..to_copy]); + } + to_copy + }); + + // Re-enable RX interrupt + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().enabled()); + }); + + Ok(read) + } +} + +// ============================================================================ +// INTERRUPT HANDLER +// ============================================================================ + +/// Buffered UART interrupt handler +pub struct BufferedInterruptHandler { + _phantom: PhantomData, +} + +impl crate::interrupt::typelevel::Handler + for BufferedInterruptHandler +{ + unsafe fn on_interrupt() { + let regs = T::info().regs; + let state = T::buffered_state(); + + // Check if this instance is initialized + if !state.initialized.load(Ordering::Relaxed) { + return; + } + + let ctrl = regs.ctrl().read(); + let stat = regs.stat().read(); + let has_fifo = regs.param().read().rxfifo().bits() > 0; + + // Handle overrun error + if stat.or().is_overrun() { + regs.stat().write(|w| w.or().clear_bit_by_one()); + state.rx_waker.wake(); + return; + } + + // Clear other error flags + if stat.pf().is_parity() { + regs.stat().write(|w| w.pf().clear_bit_by_one()); + } + if stat.fe().is_error() { + regs.stat().write(|w| w.fe().clear_bit_by_one()); + } + if stat.nf().is_noise() { + regs.stat().write(|w| w.nf().clear_bit_by_one()); + } + + // Handle RX data + if ctrl.rie().is_enabled() && (has_data(regs) || stat.idle().is_idle()) { + let mut pushed_any = false; + let mut writer = state.rx_buf.writer(); + + if has_fifo { + // Read from FIFO + while regs.water().read().rxcount().bits() > 0 { + let byte = (regs.data().read().bits() & 0xFF) as u8; + if writer.push_one(byte) { + pushed_any = true; + } else { + // Buffer full, stop reading + break; + } + } + } else { + // Read single byte + if regs.stat().read().rdrf().is_rxdata() { + let byte = (regs.data().read().bits() & 0xFF) as u8; + if writer.push_one(byte) { + pushed_any = true; + } + } + } + + if pushed_any { + state.rx_waker.wake(); + } + + // Clear idle flag if set + if stat.idle().is_idle() { + regs.stat().write(|w| w.idle().clear_bit_by_one()); + } + } + + // Handle TX data + if ctrl.tie().is_enabled() { + let mut sent_any = false; + let mut reader = state.tx_buf.reader(); + + // Send data while TX buffer is ready and we have data + while regs.stat().read().tdre().is_no_txdata() { + if let Some(byte) = reader.pop_one() { + regs.data().write(|w| w.bits(u32::from(byte))); + sent_any = true; + } else { + // No more data to send + break; + } + } + + if sent_any { + state.tx_waker.wake(); + } + + // If buffer is empty, switch to TC interrupt or disable + if state.tx_buf.is_empty() { + cortex_m::interrupt::free(|_| { + regs.ctrl() + .modify(|_, w| w.tie().disabled().tcie().enabled()); + }); + } + } + + // Handle transmission complete + if ctrl.tcie().is_enabled() { + if regs.stat().read().tc().is_complete() { + state.tx_done.store(true, Ordering::Release); + state.tx_waker.wake(); + + // Disable TC interrupt + cortex_m::interrupt::free(|_| { + regs.ctrl().modify(|_, w| w.tcie().disabled()); + }); + } + } + } +} + +// ============================================================================ +// EMBEDDED-IO ASYNC TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_io_async::ErrorType for BufferedLpuartTx<'_> { + type Error = Error; +} + +impl embedded_io_async::ErrorType for BufferedLpuartRx<'_> { + type Error = Error; +} + +impl embedded_io_async::ErrorType for BufferedLpuart<'_> { + type Error = Error; +} + +impl embedded_io_async::Write for BufferedLpuartTx<'_> { + async fn write(&mut self, buf: &[u8]) -> core::result::Result { + self.write(buf).await + } + + async fn flush(&mut self) -> core::result::Result<(), Self::Error> { + self.flush().await + } +} + +impl embedded_io_async::Read for BufferedLpuartRx<'_> { + async fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + self.read(buf).await + } +} + +impl embedded_io_async::Write for BufferedLpuart<'_> { + async fn write(&mut self, buf: &[u8]) -> core::result::Result { + self.tx.write(buf).await + } + + async fn flush(&mut self) -> core::result::Result<(), Self::Error> { + self.tx.flush().await + } +} + +impl embedded_io_async::Read for BufferedLpuart<'_> { + async fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + self.rx.read(buf).await + } +} diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs new file mode 100644 index 000000000..431547f86 --- /dev/null +++ b/src/lpuart/mod.rs @@ -0,0 +1,1208 @@ +use crate::interrupt; +use core::marker::PhantomData; +use embassy_hal_internal::{Peri, PeripheralType}; +use paste::paste; + +use crate::pac; +use crate::pac::lpuart0::baud::Sbns as StopBits; +use crate::pac::lpuart0::ctrl::{ + Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits, +}; +use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; +use crate::pac::lpuart0::stat::Msbf as MsbFirst; + +pub mod buffered; + +// ============================================================================ +// STUB IMPLEMENTATION +// ============================================================================ + +// Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API +// Pin and Clock initialization is currently done at the examples level. + +// --- START LIB --- + +// Use our own instance of Peripherals, until we align `lib.rs` with the EMBASSY-IMXRT approach +// Inlined peripherals_definition! to bypass the `Peripherals::take_with_cs()` check +// SHOULD NOT BE USED IN THE FINAL VERSION +pub mod lib { + // embassy_hal_internal::peripherals!(LPUART2, PIO2_2, PIO2_3) + + embassy_hal_internal::peripherals_definition!(LPUART2, PIO2_2, PIO2_3,); + #[doc = r" Struct containing all the peripheral singletons."] + #[doc = r""] + #[doc = r" To obtain the peripherals, you must initialize the HAL, by calling [`crate::init`]."] + #[allow(non_snake_case)] + pub struct Peripherals { + #[doc = concat!(stringify!(LPUART2)," peripheral")] + pub LPUART2: embassy_hal_internal::Peri<'static, peripherals::LPUART2>, + #[doc = concat!(stringify!(PIO2_2)," peripheral")] + pub PIO2_2: embassy_hal_internal::Peri<'static, peripherals::PIO2_2>, + #[doc = concat!(stringify!(PIO2_3)," peripheral")] + pub PIO2_3: embassy_hal_internal::Peri<'static, peripherals::PIO2_3>, + } + impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub(crate) fn take() -> Self { + critical_section::with(Self::take_with_cs) + } + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub(crate) fn take_with_cs(_cs: critical_section::CriticalSection) -> Self { + #[no_mangle] + static mut _EMBASSY_DEVICE_PERIPHERALS2: bool = false; // ALIGN: Temporary fix to use stub Peripherals + unsafe { + if _EMBASSY_DEVICE_PERIPHERALS2 { + panic!("init called more than once!") + } + _EMBASSY_DEVICE_PERIPHERALS2 = true; + Self::steal() + } + } + } + impl Peripherals { + #[doc = r" Unsafely create an instance of this peripheral out of thin air."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" You must ensure that you're only using one instance of this type at a time."] + #[inline] + pub unsafe fn steal() -> Self { + Self { + LPUART2: peripherals::LPUART2::steal(), + PIO2_2: peripherals::PIO2_2::steal(), + PIO2_3: peripherals::PIO2_3::steal(), + } + } + } + + /// Initialize HAL + pub fn init() -> Peripherals { + Peripherals::take() + } +} + +// --- END LIB --- + +// --- START GPIO --- + +mod gpio { + use embassy_hal_internal::PeripheralType; + trait SealedPin {} + + #[allow(private_bounds)] + pub trait GpioPin: SealedPin + Sized + PeripheralType + Into + 'static { + /// Type-erase the pin. + fn degrade(self) -> AnyPin { + todo!() + } + } + + // Add this macro to implement GpioPin for all pins + macro_rules! impl_gpio_pin { + ($($pin:ident),*) => { + $( + impl SealedPin for super::lib::peripherals::$pin {} + + impl GpioPin for super::lib::peripherals::$pin {} + + impl Into for super::lib::peripherals::$pin { + fn into(self) -> AnyPin { + AnyPin + } + } + )* + }; + } + + // Implement GpioPin for all pins from lib.rs + impl_gpio_pin!(PIO2_2, PIO2_3); + + #[derive(Debug, Clone, Copy)] + pub struct AnyPin; + + impl PeripheralType for AnyPin {} + + pub enum Alt { + ALT3, + } +} + +use gpio::{AnyPin, GpioPin as Pin}; + +// --- END GPIO --- + +// --- START DMA --- +mod dma { + pub struct Channel<'d> { + pub(super) _lifetime: core::marker::PhantomData<&'d ()>, + } +} + +use dma::Channel; + +// --- END DMA --- + +// --- START CLOCK --- +mod clock { + #[derive(Debug, Clone, Copy)] + pub enum Clock { + FroLf, // Low-Frequency Free-Running Oscillator + } +} + +use clock::Clock; + +// --- END CLOCK --- + +// ============================================================================ +// MISC +// ============================================================================ + +mod sealed { + /// Simply seal a trait to prevent external implementations + pub trait Sealed {} +} + +// ============================================================================ +// INSTANCE TRAIT +// ============================================================================ + +pub type Regs = &'static crate::pac::lpuart0::RegisterBlock; + +pub trait SealedInstance { + fn info() -> Info; + fn index() -> usize; + fn buffered_state() -> &'static buffered::State; +} + +pub struct Info { + pub regs: Regs, +} + +/// Trait for LPUART peripheral instances +#[allow(private_bounds)] +pub trait Instance: SealedInstance + PeripheralType + 'static + Send { + type Interrupt: interrupt::typelevel::Interrupt; +} + +macro_rules! impl_instance { + ($($n:expr),*) => { + $( + paste!{ + impl SealedInstance for lib::peripherals::[] { + fn info() -> Info { + Info { + regs: unsafe { &*pac::[]::ptr() }, + } + } + + #[inline] + fn index() -> usize { + $n + } + + fn buffered_state() -> &'static buffered::State { + static BUFFERED_STATE: buffered::State = buffered::State::new(); + &BUFFERED_STATE + } + } + + impl Instance for lib::peripherals::[] { + type Interrupt = crate::interrupt::typelevel::[]; + } + } + )* + }; +} + +// impl_instance!(0, 1, 2, 3, 4); +impl_instance!(2); + +// ============================================================================ +// INSTANCE HELPER FUNCTIONS +// ============================================================================ + +/// Perform software reset on the LPUART peripheral +pub fn perform_software_reset(regs: Regs) { + // Software reset - set and clear RST bit (Global register) + regs.global().write(|w| w.rst().reset()); + regs.global().write(|w| w.rst().no_effect()); +} + +/// Disable both transmitter and receiver +pub fn disable_transceiver(regs: Regs) { + regs.ctrl().modify(|_, w| w.te().disabled().re().disabled()); +} + +/// Calculate and configure baudrate settings +pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result<()> { + let clock_freq = get_fc_freq(clock)?; + let (osr, sbr) = calculate_baudrate(baudrate_bps, clock_freq)?; + + // Configure BAUD register + regs.baud().modify(|_, w| unsafe { + // Clear and set OSR + w.osr().bits((osr - 1) as u8); + // Clear and set SBR + w.sbr().bits(sbr); + // Set BOTHEDGE if OSR is between 4 and 7 + if osr > 3 && osr < 8 { + w.bothedge().enabled() + } else { + w.bothedge().disabled() + } + }); + + Ok(()) +} + +/// Configure frame format (stop bits, data bits) +pub fn configure_frame_format(regs: Regs, config: &Config) { + // Configure stop bits + regs.baud() + .modify(|_, w| w.sbns().variant(config.stop_bits_count)); + + // Clear M10 for now (10-bit mode) + regs.baud().modify(|_, w| w.m10().disabled()); +} + +/// Configure control settings (parity, data bits, idle config, pin swap) +pub fn configure_control_settings(regs: Regs, config: &Config) { + regs.ctrl().modify(|_, w| { + // Parity configuration + let mut w = if let Some(parity) = config.parity_mode { + w.pe().enabled().pt().variant(parity) + } else { + w.pe().disabled() + }; + + // Data bits configuration + w = match config.data_bits_count { + DataBits::Data8 => { + if config.parity_mode.is_some() { + w.m().data9() // 8 data + 1 parity = 9 bits + } else { + w.m().data8() // 8 data bits only + } + } + DataBits::Data9 => w.m().data9(), + }; + + // Idle configuration + w = w.idlecfg().variant(config.rx_idle_config); + w = w.ilt().variant(config.rx_idle_type); + + // Swap TXD/RXD if configured + if config.swap_txd_rxd { + w.swap().swap() + } else { + w.swap().standard() + } + }); +} + +/// Configure FIFO settings and watermarks +pub fn configure_fifo(regs: Regs, config: &Config) { + // Configure WATER register for FIFO watermarks + regs.water().write(|w| unsafe { + w.rxwater() + .bits(config.rx_fifo_watermark as u8) + .txwater() + .bits(config.tx_fifo_watermark as u8) + }); + + // Enable TX/RX FIFOs + regs.fifo() + .modify(|_, w| w.txfe().enabled().rxfe().enabled()); + + // Flush FIFOs + regs.fifo() + .modify(|_, w| w.txflush().txfifo_rst().rxflush().rxfifo_rst()); +} + +/// Clear all status flags +pub fn clear_all_status_flags(regs: Regs) { + regs.stat().reset(); +} + +/// Configure hardware flow control if enabled +pub fn configure_flow_control(regs: Regs, config: &Config) { + if config.enable_rx_rts || config.enable_tx_cts { + regs.modir().modify(|_, w| { + let mut w = w; + + // Configure TX CTS + w = w.txctsc().variant(config.tx_cts_config); + w = w.txctssrc().variant(config.tx_cts_source); + + if config.enable_rx_rts { + w = w.rxrtse().enabled(); + } else { + w = w.rxrtse().disabled(); + } + + if config.enable_tx_cts { + w = w.txctse().enabled(); + } else { + w = w.txctse().disabled(); + } + + w + }); + } +} + +/// Configure bit order (MSB first or LSB first) +pub fn configure_bit_order(regs: Regs, msb_first: MsbFirst) { + regs.stat().modify(|_, w| w.msbf().variant(msb_first)); +} + +/// Enable transmitter and/or receiver based on configuration +pub fn enable_transceiver(regs: Regs, enable_tx: bool, enable_rx: bool) { + regs.ctrl().modify(|_, w| { + let mut w = w; + if enable_tx { + w = w.te().enabled(); + } + if enable_rx { + w = w.re().enabled(); + } + w + }); +} + +pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> { + let mut baud_diff = baudrate; + let mut osr = 0u8; + let mut sbr = 0u16; + + // Try OSR values from 4 to 32 + for osr_temp in 4u8..=32u8 { + // Calculate SBR: (srcClock_Hz * 2 / (baudRate * osr) + 1) / 2 + let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32) + 1) / 2; + + let sbr_temp = if sbr_calc == 0 { + 1 + } else if sbr_calc > 0x1FFF { + 0x1FFF + } else { + sbr_calc as u16 + }; + + // Calculate actual baud rate + let calculated_baud = src_clock_hz / (osr_temp as u32 * sbr_temp as u32); + + let temp_diff = if calculated_baud > baudrate { + calculated_baud - baudrate + } else { + baudrate - calculated_baud + }; + + if temp_diff <= baud_diff { + baud_diff = temp_diff; + osr = osr_temp; + sbr = sbr_temp; + } + } + + // Check if baud rate difference is within 3% + if baud_diff > (baudrate / 100) * 3 { + return Err(Error::UnsupportedBaudrate); + } + + Ok((osr, sbr)) +} + +pub fn get_fc_freq(clock: Clock) -> Result { + // This is a placeholder - actual implementation would query the clock system + // In real implementation, this would get the LPUART clock frequency + match clock { + Clock::FroLf => Ok(12_000_000), // Low frequency oscillator + #[allow(unreachable_patterns)] + _ => Err(Error::InvalidArgument), + } +} + +/// Wait for all transmit operations to complete +pub fn wait_for_tx_complete(regs: Regs) { + // Wait for TX FIFO to empty + while regs.water().read().txcount().bits() != 0 { + // Wait for TX FIFO to drain + } + + // Wait for last character to shift out (TC = Transmission Complete) + while regs.stat().read().tc().is_active() { + // Wait for transmission to complete + } +} + +pub fn check_and_clear_rx_errors(regs: Regs) -> Result<()> { + let stat = regs.stat().read(); + let mut status = Ok(()); + + // Check for overrun first - other error flags are prevented when OR is set + if stat.or().is_overrun() { + regs.stat().write(|w| w.or().clear_bit_by_one()); + + return Err(Error::Overrun); + } + + if stat.pf().is_parity() { + regs.stat().write(|w| w.pf().clear_bit_by_one()); + status = Err(Error::Parity); + } + + if stat.fe().is_error() { + regs.stat().write(|w| w.fe().clear_bit_by_one()); + status = Err(Error::Framing); + } + + if stat.nf().is_noise() { + regs.stat().write(|w| w.nf().clear_bit_by_one()); + status = Err(Error::Noise); + } + + status +} + +pub fn has_data(regs: Regs) -> bool { + if regs.param().read().rxfifo().bits() > 0 { + // FIFO is available - check RXCOUNT in WATER register + regs.water().read().rxcount().bits() > 0 + } else { + // No FIFO - check RDRF flag in STAT register + regs.stat().read().rdrf().is_rxdata() + } +} + +// ============================================================================ +// PIN TRAITS FOR LPUART FUNCTIONALITY +// ============================================================================ + +impl sealed::Sealed for T {} + +/// io configuration trait for Lpuart Tx configuration +pub trait TxPin: Pin + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Tx usage + fn as_tx(&self); +} + +/// io configuration trait for Lpuart Rx configuration +pub trait RxPin: Pin + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Rx usage + fn as_rx(&self); +} + +/// io configuration trait for Lpuart Cts +pub trait CtsPin: Pin + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Cts usage + fn as_cts(&self); +} + +/// io configuration trait for Lpuart Rts +pub trait RtsPin: Pin + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Rts usage + fn as_rts(&self); +} + +macro_rules! impl_pin_trait { + ($fcn:ident, $mode:ident, $($pin:ident, $alt:ident),*) => { + paste! { + $( + impl [<$mode:camel Pin>] for lib::peripherals::$pin { + fn [](&self) { + let _alt = gpio::Alt::$alt; + // todo!("Configure pin for LPUART function") + } + } + )* + } + }; +} + +// Document identifier: MCXA343/344 Rev. 1DraftB ReleaseCandidate, 2025-07-10 - 6.1 MCX A173, A174 Signal Multiplexing and Pin Assignments +// impl_pin_trait!(LPUART0, rx, PIO2_0, ALT2, PIO0_2, ALT2, PIO0_20, ALT3); +// impl_pin_trait!(LPUART0, tx, PIO2_1, ALT2, PIO0_3, ALT2, PIO0_21, ALT3); +// impl_pin_trait!(LPUART0, rts, PIO2_2, ALT2, PIO0_0, ALT2, PIO0_22, ALT3); +// impl_pin_trait!(LPUART0, cts, PIO2_3, ALT2, PIO0_1, ALT2, PIO0_23, ALT3); +impl_pin_trait!(LPUART2, rx, PIO2_3, ALT3); +impl_pin_trait!(LPUART2, tx, PIO2_2, ALT3); + +// ============================================================================ +// ERROR TYPES AND RESULTS +// ============================================================================ + +/// LPUART error types +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + /// Read error + Read, + /// Buffer overflow + Overrun, + /// Noise error + Noise, + /// Framing error + Framing, + /// Parity error + Parity, + /// Failure + Fail, + /// Invalid argument + InvalidArgument, + /// Lpuart baud rate cannot be supported with the given clock + UnsupportedBaudrate, + /// RX FIFO Empty + RxFifoEmpty, + /// TX FIFO Full + TxFifoFull, + /// TX Busy + TxBusy, +} + +/// A specialized Result type for LPUART operations +pub type Result = core::result::Result; + +// ============================================================================ +// CONFIGURATION STRUCTURES +// ============================================================================ + +/// Lpuart config +#[derive(Debug, Clone, Copy)] +pub struct Config { + /// Baud rate in bits per second + pub baudrate_bps: u32, + /// Clock + pub clock: Clock, + /// Parity configuration + pub parity_mode: Option, + /// Number of data bits + pub data_bits_count: DataBits, + /// MSB First or LSB First configuration + pub msb_firs: MsbFirst, + /// Number of stop bits + pub stop_bits_count: StopBits, + /// TX FIFO watermark + pub tx_fifo_watermark: u8, + /// RX FIFO watermark + pub rx_fifo_watermark: u8, + /// RX RTS enable + pub enable_rx_rts: bool, + /// TX CTS enable + pub enable_tx_cts: bool, + /// TX CTS source + pub tx_cts_source: TxCtsSource, + /// TX CTS configure + pub tx_cts_config: TxCtsConfig, + /// RX IDLE type + pub rx_idle_type: IdleType, + /// RX IDLE configuration + pub rx_idle_config: IdleConfig, + /// Enable transmitter + pub enable_tx: bool, + /// Enable receiver + pub enable_rx: bool, + /// Swap TXD and RXD pins + pub swap_txd_rxd: bool, +} + +impl Default for Config { + fn default() -> Self { + Self { + baudrate_bps: 115_200u32, + clock: Clock::FroLf, + parity_mode: None, + data_bits_count: DataBits::Data8, + msb_firs: MsbFirst::LsbFirst, + stop_bits_count: StopBits::One, + tx_fifo_watermark: 0, + rx_fifo_watermark: 1, + enable_rx_rts: false, + enable_tx_cts: false, + tx_cts_source: TxCtsSource::Cts, + tx_cts_config: TxCtsConfig::Start, + rx_idle_type: IdleType::FromStart, + rx_idle_config: IdleConfig::Idle1, + enable_tx: false, + enable_rx: false, + swap_txd_rxd: false, + } + } +} + +/// LPUART status flags +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct Status { + /// Transmit data register empty + pub tx_empty: bool, + /// Transmission complete + pub tx_complete: bool, + /// Receive data register full + pub rx_full: bool, + /// Idle line detected + pub idle: bool, + /// Receiver overrun + pub overrun: bool, + /// Noise error + pub noise: bool, + /// Framing error + pub framing: bool, + /// Parity error + pub parity: bool, +} + +// ============================================================================ +// MODE TRAITS (BLOCKING/ASYNC) +// ============================================================================ + +/// Driver move trait. +#[allow(private_bounds)] +pub trait Mode: sealed::Sealed {} + +/// Blocking mode. +pub struct Blocking; +impl sealed::Sealed for Blocking {} +impl Mode for Blocking {} + +/// Async mode. +pub struct Async; +impl sealed::Sealed for Async {} +impl Mode for Async {} + +// ============================================================================ +// CORE DRIVER STRUCTURES +// ============================================================================ + +/// Lpuart driver. +pub struct Lpuart<'a, M: Mode> { + info: Info, + tx: LpuartTx<'a, M>, + rx: LpuartRx<'a, M>, +} + +/// Lpuart TX driver. +pub struct LpuartTx<'a, M: Mode> { + info: Info, + _tx_pin: Peri<'a, AnyPin>, + _tx_dma: Option>, + mode: PhantomData<(&'a (), M)>, +} + +/// Lpuart Rx driver. +pub struct LpuartRx<'a, M: Mode> { + info: Info, + _rx_pin: Peri<'a, AnyPin>, + _rx_dma: Option>, + mode: PhantomData<(&'a (), M)>, +} + +// ============================================================================ +// LPUART CORE IMPLEMENTATION +// ============================================================================ + +impl<'a, M: Mode> Lpuart<'a, M> { + fn init( + _tx: Option<&Peri<'a, AnyPin>>, + _rx: Option<&Peri<'a, AnyPin>>, + _rts: Option<&Peri<'a, AnyPin>>, + _cts: Option<&Peri<'a, AnyPin>>, + config: Config, + ) -> Result<()> { + let regs = T::info().regs; + + // Perform initialization sequence + perform_software_reset(regs); + disable_transceiver(regs); + configure_baudrate(regs, config.baudrate_bps, config.clock)?; + configure_frame_format(regs, &config); + configure_control_settings(regs, &config); + configure_fifo(regs, &config); + clear_all_status_flags(regs); + configure_flow_control(regs, &config); + configure_bit_order(regs, config.msb_firs); + enable_transceiver(regs, config.enable_tx, config.enable_rx); + + Ok(()) + } + + /// Deinitialize the LPUART peripheral + pub fn deinit(&self) -> Result<()> { + let regs = self.info.regs; + + // Wait for TX operations to complete + wait_for_tx_complete(regs); + + // Clear all status flags + clear_all_status_flags(regs); + + // Disable the module - clear all CTRL register bits + regs.ctrl().reset(); + + Ok(()) + } + + /// Split the Lpuart into a transmitter and receiver + pub fn split(self) -> (LpuartTx<'a, M>, LpuartRx<'a, M>) { + (self.tx, self.rx) + } + + /// Split the Lpuart into a transmitter and receiver by mutable reference + pub fn split_ref(&mut self) -> (&mut LpuartTx<'a, M>, &mut LpuartRx<'a, M>) { + (&mut self.tx, &mut self.rx) + } +} + +// ============================================================================ +// BLOCKING MODE IMPLEMENTATIONS +// ============================================================================ + +impl<'a> Lpuart<'a, Blocking> { + /// Create a new blocking LPUART instance with TX and RX pins. + pub fn new_blocking( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + config: Config, + ) -> Result { + // Configure the pins for LPUART usage + tx_pin.as_tx(); + rx_pin.as_rx(); + + // Convert pins to AnyPin + let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); + let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); + + // Initialize the peripheral + Self::init::(Some(&tx_pin), Some(&rx_pin), None, None, config)?; + + Ok(Self { + info: T::info(), + tx: LpuartTx::new_inner(T::info(), tx_pin, None), + rx: LpuartRx::new_inner(T::info(), rx_pin, None), + }) + } +} + +// ---------------------------------------------------------------------------- +// Blocking TX Implementation +// ---------------------------------------------------------------------------- + +impl<'a, M: Mode> LpuartTx<'a, M> { + fn new_inner(info: Info, tx_pin: Peri<'a, AnyPin>, tx_dma: Option>) -> Self { + Self { + info, + _tx_pin: tx_pin, + _tx_dma: tx_dma, + mode: PhantomData, + } + } +} + +impl<'a> LpuartTx<'a, Blocking> { + /// Create a new blocking LPUART which can only send data. + pub fn new_blocking( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + config: Config, + ) -> Result { + tx_pin.as_tx(); + + let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); + + Lpuart::::init::(Some(&tx_pin), None, None, None, config)?; + + Ok(Self::new_inner(T::info(), tx_pin, None)) + } + + fn write_byte_internal(&mut self, byte: u8) -> Result<()> { + self.info + .regs + .data() + .modify(|_, w| unsafe { w.bits(u32::from(byte)) }); + + Ok(()) + } + + fn blocking_write_byte(&mut self, byte: u8) -> Result<()> { + while self.info.regs.stat().read().tdre().is_txdata() {} + self.write_byte_internal(byte) + } + + fn write_byte(&mut self, byte: u8) -> Result<()> { + if self.info.regs.stat().read().tdre().is_txdata() { + Err(Error::TxFifoFull) + } else { + self.write_byte_internal(byte) + } + } + + /// Write data to LPUART TX blocking execution until all data is sent. + pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> { + for x in buf { + self.blocking_write_byte(*x)?; + } + + Ok(()) + } + + /// Write data to LPUART TX without blocking. + pub fn write(&mut self, buf: &[u8]) -> Result<()> { + for x in buf { + self.write_byte(*x)?; + } + + Ok(()) + } + + /// Flush LPUART TX blocking execution until all data has been transmitted. + pub fn blocking_flush(&mut self) -> Result<()> { + while self.info.regs.water().read().txcount().bits() != 0 { + // Wait for TX FIFO to drain + } + + // Wait for last character to shift out + while self.info.regs.stat().read().tc().is_active() { + // Wait for transmission to complete + } + + Ok(()) + } + + /// Flush LPUART TX. + pub fn flush(&mut self) -> Result<()> { + // Check if TX FIFO is empty + if self.info.regs.water().read().txcount().bits() != 0 { + return Err(Error::TxBusy); + } + + // Check if transmission is complete + if self.info.regs.stat().read().tc().is_active() { + return Err(Error::TxBusy); + } + + Ok(()) + } +} + +// ---------------------------------------------------------------------------- +// Blocking RX Implementation +// ---------------------------------------------------------------------------- + +impl<'a, M: Mode> LpuartRx<'a, M> { + fn new_inner(info: Info, rx_pin: Peri<'a, AnyPin>, rx_dma: Option>) -> Self { + Self { + info, + _rx_pin: rx_pin, + _rx_dma: rx_dma, + mode: PhantomData, + } + } +} + +impl<'a> LpuartRx<'a, Blocking> { + /// Create a new blocking LPUART which can only receive data. + pub fn new_blocking( + _inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + config: Config, + ) -> Result { + rx_pin.as_rx(); + + let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); + + Lpuart::::init::(None, Some(&rx_pin), None, None, config)?; + + Ok(Self::new_inner(T::info(), rx_pin, None)) + } + + fn read_byte_internal(&mut self) -> Result { + let data = self.info.regs.data().read(); + + Ok((data.bits() & 0xFF) as u8) + } + + fn read_byte(&mut self) -> Result { + check_and_clear_rx_errors(self.info.regs)?; + + if !has_data(self.info.regs) { + return Err(Error::RxFifoEmpty); + } + + self.read_byte_internal() + } + + fn blocking_read_byte(&mut self) -> Result { + loop { + if has_data(self.info.regs) { + return self.read_byte_internal(); + } + + check_and_clear_rx_errors(self.info.regs)?; + } + } + + /// Read data from LPUART RX without blocking. + pub fn read(&mut self, buf: &mut [u8]) -> Result<()> { + for byte in buf.iter_mut() { + *byte = self.read_byte()?; + } + Ok(()) + } + + /// Read data from LPUART RX blocking execution until the buffer is filled. + pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> { + for byte in buf.iter_mut() { + *byte = self.blocking_read_byte()?; + } + Ok(()) + } +} + +impl<'a> Lpuart<'a, Blocking> { + /// Read data from LPUART RX blocking execution until the buffer is filled + pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> { + self.rx.blocking_read(buf) + } + + /// Read data from LPUART RX without blocking + pub fn read(&mut self, buf: &mut [u8]) -> Result<()> { + self.rx.read(buf) + } + + /// Write data to LPUART TX blocking execution until all data is sent + pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> { + self.tx.blocking_write(buf) + } + + /// Write data to LPUART TX without blocking + pub fn write(&mut self, buf: &[u8]) -> Result<()> { + self.tx.write(buf) + } + + /// Flush LPUART TX blocking execution until all data has been transmitted + pub fn blocking_flush(&mut self) -> Result<()> { + self.tx.blocking_flush() + } + + /// Flush LPUART TX without blocking + pub fn flush(&mut self) -> Result<()> { + self.tx.flush() + } +} + +// ============================================================================ +// ASYNC MODE IMPLEMENTATIONS +// ============================================================================ + +// TODO: Implement async mode for LPUART + +// ============================================================================ +// EMBEDDED-HAL 0.2 TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_hal_02::serial::Read for LpuartRx<'_, Blocking> { + type Error = Error; + + fn read(&mut self) -> core::result::Result> { + let mut buf = [0; 1]; + match self.read(&mut buf) { + Ok(_) => Ok(buf[0]), + Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_02::serial::Write for LpuartTx<'_, Blocking> { + type Error = Error; + + fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error> { + match self.write(&[word]) { + Ok(_) => Ok(()), + Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } + + fn flush(&mut self) -> core::result::Result<(), nb::Error> { + match self.flush() { + Ok(_) => Ok(()), + Err(Error::TxBusy) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_02::blocking::serial::Write for LpuartTx<'_, Blocking> { + type Error = Error; + + fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> { + self.blocking_write(buffer) + } + + fn bflush(&mut self) -> core::result::Result<(), Self::Error> { + self.blocking_flush() + } +} + +impl embedded_hal_02::serial::Read for Lpuart<'_, Blocking> { + type Error = Error; + + fn read(&mut self) -> core::result::Result> { + embedded_hal_02::serial::Read::read(&mut self.rx) + } +} + +impl embedded_hal_02::serial::Write for Lpuart<'_, Blocking> { + type Error = Error; + + fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error> { + embedded_hal_02::serial::Write::write(&mut self.tx, word) + } + + fn flush(&mut self) -> core::result::Result<(), nb::Error> { + embedded_hal_02::serial::Write::flush(&mut self.tx) + } +} + +impl embedded_hal_02::blocking::serial::Write for Lpuart<'_, Blocking> { + type Error = Error; + + fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> { + self.blocking_write(buffer) + } + + fn bflush(&mut self) -> core::result::Result<(), Self::Error> { + self.blocking_flush() + } +} + +// ============================================================================ +// EMBEDDED-HAL-NB TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_hal_nb::serial::Error for Error { + fn kind(&self) -> embedded_hal_nb::serial::ErrorKind { + match *self { + Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat, + Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun, + Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity, + Self::Noise => embedded_hal_nb::serial::ErrorKind::Noise, + _ => embedded_hal_nb::serial::ErrorKind::Other, + } + } +} + +impl embedded_hal_nb::serial::ErrorType for LpuartRx<'_, Blocking> { + type Error = Error; +} + +impl embedded_hal_nb::serial::ErrorType for LpuartTx<'_, Blocking> { + type Error = Error; +} + +impl embedded_hal_nb::serial::ErrorType for Lpuart<'_, Blocking> { + type Error = Error; +} + +impl embedded_hal_nb::serial::Read for LpuartRx<'_, Blocking> { + fn read(&mut self) -> nb::Result { + let mut buf = [0; 1]; + match self.read(&mut buf) { + Ok(_) => Ok(buf[0]), + Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_nb::serial::Write for LpuartTx<'_, Blocking> { + fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { + match self.write(&[word]) { + Ok(_) => Ok(()), + Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + match self.flush() { + Ok(_) => Ok(()), + Err(Error::TxBusy) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_nb::serial::Read for Lpuart<'_, Blocking> { + fn read(&mut self) -> nb::Result { + embedded_hal_nb::serial::Read::read(&mut self.rx) + } +} + +impl embedded_hal_nb::serial::Write for Lpuart<'_, Blocking> { + fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> { + embedded_hal_nb::serial::Write::write(&mut self.tx, char) + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + embedded_hal_nb::serial::Write::flush(&mut self.tx) + } +} + +// ============================================================================ +// EMBEDDED-IO TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_io::Error for Error { + fn kind(&self) -> embedded_io::ErrorKind { + embedded_io::ErrorKind::Other + } +} + +impl embedded_io::ErrorType for LpuartRx<'_, Blocking> { + type Error = Error; +} + +impl embedded_io::ErrorType for LpuartTx<'_, Blocking> { + type Error = Error; +} + +impl embedded_io::ErrorType for Lpuart<'_, Blocking> { + type Error = Error; +} + +impl embedded_io::Read for LpuartRx<'_, Blocking> { + fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + self.blocking_read(buf).map(|_| buf.len()) + } +} + +impl embedded_io::Write for LpuartTx<'_, Blocking> { + fn write(&mut self, buf: &[u8]) -> core::result::Result { + self.blocking_write(buf).map(|_| buf.len()) + } + + fn flush(&mut self) -> core::result::Result<(), Self::Error> { + self.blocking_flush() + } +} + +impl embedded_io::Read for Lpuart<'_, Blocking> { + fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + embedded_io::Read::read(&mut self.rx, buf) + } +} + +impl embedded_io::Write for Lpuart<'_, Blocking> { + fn write(&mut self, buf: &[u8]) -> core::result::Result { + embedded_io::Write::write(&mut self.tx, buf) + } + + fn flush(&mut self) -> core::result::Result<(), Self::Error> { + embedded_io::Write::flush(&mut self.tx) + } +} diff --git a/src/main.rs b/src/main.rs deleted file mode 100644 index 7111536ff..000000000 --- a/src/main.rs +++ /dev/null @@ -1,18 +0,0 @@ -#![cfg_attr(target_os = "none", no_std)] -#![cfg_attr(target_os = "none", no_main)] - -#[cfg(target_os = "none")] -mod baremetal; - -#[cfg(not(target_os = "none"))] -fn main() { - println!("Hello, world!"); -} - -#[cfg(test)] -mod tests { - #[test] - fn it_works() { - assert_eq!(2 + 2, 4); - } -} diff --git a/src/ostimer.rs b/src/ostimer.rs new file mode 100644 index 000000000..b9688313a --- /dev/null +++ b/src/ostimer.rs @@ -0,0 +1,704 @@ +//! # OSTIMER Driver with Robustness Features +//! +//! This module provides an async timer driver for the NXP MCXA276 OSTIMER peripheral +//! with protection against race conditions and timer rollover issues. +//! +//! ## Features +//! +//! - Async timing with embassy-time integration +//! - Gray code counter handling (42-bit counter) +//! - Interrupt-driven wakeups +//! - Configurable interrupt priority +//! - **Race condition protection**: Critical sections and atomic operations +//! - **Timer rollover handling**: Bounds checking and rollover prevention +//! +//! ## Clock Frequency Configuration +//! +//! The OSTIMER frequency depends on your system's clock configuration. You must provide +//! the actual frequency when calling `time_driver::init()`. +//! +//! ## Race Condition Protection +//! - Critical sections in interrupt handlers prevent concurrent access +//! - Atomic register operations with memory barriers +//! - Proper interrupt flag clearing and validation +//! +//! ## Timer Rollover Handling +//! - Bounds checking prevents scheduling beyond timer capacity +//! - Immediate wake for timestamps that would cause rollover issues +#![allow(dead_code)] + +use crate::interrupt::InterruptExt; +use crate::pac; +use core::sync::atomic::{AtomicBool, Ordering}; + +// PAC defines the shared RegisterBlock under `ostimer0`. +type Regs = pac::ostimer0::RegisterBlock; + +// OSTIMER EVTIMER register layout constants +/// Total width of the EVTIMER counter in bits (42 bits total) +const EVTIMER_TOTAL_BITS: u32 = 42; +/// Width of the low part of EVTIMER (bits 31:0) +const EVTIMER_LO_BITS: u32 = 32; +/// Width of the high part of EVTIMER (bits 41:32) +const EVTIMER_HI_BITS: u32 = 10; +/// Bit position where high part starts in the combined 64-bit value +const EVTIMER_HI_SHIFT: u32 = 32; + +/// Bit mask for the high part of EVTIMER +const EVTIMER_HI_MASK: u16 = (1 << EVTIMER_HI_BITS) - 1; + +/// Maximum value for MATCH_L register (32-bit) +const MATCH_L_MAX: u32 = u32::MAX; +/// Maximum value for MATCH_H register (10-bit) +const MATCH_H_MAX: u16 = EVTIMER_HI_MASK; + +/// Bit mask for extracting the low 32 bits from a 64-bit value +const LOW_32_BIT_MASK: u64 = u32::MAX as u64; + +/// Gray code conversion bit shifts (most significant to least) +const GRAY_CONVERSION_SHIFTS: [u32; 6] = [32, 16, 8, 4, 2, 1]; + +/// Maximum timer value before rollover (2^42 - 1 ticks) +/// Actual rollover time depends on the configured clock frequency +const TIMER_MAX_VALUE: u64 = (1u64 << EVTIMER_TOTAL_BITS) - 1; + +/// Threshold for detecting timer rollover in comparisons (1 second at 1MHz) +const TIMER_ROLLOVER_THRESHOLD: u64 = 1_000_000; + +/// Common default interrupt priority for OSTIMER +const DEFAULT_INTERRUPT_PRIORITY: u8 = 3; + +// Global alarm state for interrupt handling +static ALARM_ACTIVE: AtomicBool = AtomicBool::new(false); +static mut ALARM_CALLBACK: Option = None; +static mut ALARM_FLAG: Option<*const AtomicBool> = None; +static mut ALARM_TARGET_TIME: u64 = 0; + +/// Number of tight spin iterations between elapsed time checks while waiting for MATCH writes to return to the idle (0) state. +const MATCH_WRITE_READY_SPINS: usize = 512; +/// Maximum time (in OSTIMER ticks) to wait for MATCH registers to become writable (~5 ms at 1 MHz). +const MATCH_WRITE_READY_TIMEOUT_TICKS: u64 = 5_000; +/// Short stabilization delay executed after toggling the MRCC reset line to let the OSTIMER bus interface settle. +const RESET_STABILIZE_SPINS: usize = 512; + +pub(super) fn wait_for_match_write_ready(r: &Regs) -> bool { + let start = now_ticks_read(); + let mut spin_budget = 0usize; + + loop { + if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() { + return true; + } + + cortex_m::asm::nop(); + spin_budget += 1; + + if spin_budget >= MATCH_WRITE_READY_SPINS { + spin_budget = 0; + + let elapsed = now_ticks_read().wrapping_sub(start); + if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS { + return false; + } + } + } +} + +pub(super) fn wait_for_match_write_complete(r: &Regs) -> bool { + let start = now_ticks_read(); + let mut spin_budget = 0usize; + + loop { + if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() { + return true; + } + + cortex_m::asm::nop(); + spin_budget += 1; + + if spin_budget >= MATCH_WRITE_READY_SPINS { + spin_budget = 0; + + let elapsed = now_ticks_read().wrapping_sub(start); + if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS { + return false; + } + } + } +} + +fn prime_match_registers(r: &Regs) { + // Disable the interrupt, clear any pending flag, then wait until the MATCH registers are writable. + r.osevent_ctrl().write(|w| { + w.ostimer_intrflag() + .clear_bit_by_one() + .ostimer_intena() + .clear_bit() + }); + + if wait_for_match_write_ready(r) { + r.match_l() + .write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) }); + r.match_h() + .write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) }); + let _ = wait_for_match_write_complete(r); + } +} + +/// Single-shot alarm functionality for OSTIMER +pub struct Alarm<'d> { + /// Whether the alarm is currently active + active: AtomicBool, + /// Callback to execute when alarm expires (optional) + callback: Option, + /// Flag that gets set when alarm expires (optional) + flag: Option<&'d AtomicBool>, + _phantom: core::marker::PhantomData<&'d mut ()>, +} + +impl<'d> Alarm<'d> { + /// Create a new alarm instance + pub fn new() -> Self { + Self { + active: AtomicBool::new(false), + callback: None, + flag: None, + _phantom: core::marker::PhantomData, + } + } + + /// Set a callback that will be executed when the alarm expires + /// Note: Due to interrupt handler constraints, callbacks must be static function pointers + pub fn with_callback(mut self, callback: fn()) -> Self { + self.callback = Some(callback); + self + } + + /// Set a flag that will be set to true when the alarm expires + pub fn with_flag(mut self, flag: &'d AtomicBool) -> Self { + self.flag = Some(flag); + self + } + + /// Check if the alarm is currently active + pub fn is_active(&self) -> bool { + self.active.load(Ordering::Acquire) + } + + /// Cancel the alarm if it's active + pub fn cancel(&self) { + self.active.store(false, Ordering::Release); + } +} + +/// Configuration for Ostimer::new() +#[derive(Copy, Clone)] +pub struct Config { + /// Initialize MATCH registers to their max values and mask/clear the interrupt flag. + pub init_match_max: bool, + /// OSTIMER clock frequency in Hz (must match the actual hardware clock) + pub clock_frequency_hz: u64, +} + +impl Default for Config { + fn default() -> Self { + Self { + init_match_max: true, + // Default to 1MHz - user should override this with actual frequency + clock_frequency_hz: 1_000_000, + } + } +} + +/// OSTIMER peripheral instance +pub struct Ostimer<'d, I: Instance> { + _inst: core::marker::PhantomData, + clock_frequency_hz: u64, + _phantom: core::marker::PhantomData<&'d mut ()>, +} + +impl<'d, I: Instance> Ostimer<'d, I> { + /// Construct OSTIMER handle. + /// Requires clocks for the instance to be enabled by the board before calling. + /// Does not enable NVIC or INTENA; use time_driver::init() for async operation. + pub fn new(_inst: impl Instance, cfg: Config, _p: &'d crate::pac::Peripherals) -> Self { + assert!( + cfg.clock_frequency_hz > 0, + "OSTIMER frequency must be greater than 0" + ); + + if cfg.init_match_max { + let r: &Regs = unsafe { &*I::ptr() }; + // Mask INTENA, clear pending flag, and set MATCH to max so no spurious IRQ fires. + prime_match_registers(r); + } + + Self { + _inst: core::marker::PhantomData, + clock_frequency_hz: cfg.clock_frequency_hz, + _phantom: core::marker::PhantomData, + } + } + + /// Get the configured clock frequency in Hz + pub fn clock_frequency_hz(&self) -> u64 { + self.clock_frequency_hz + } + + /// Read the current timer counter value in timer ticks + /// + /// # Returns + /// Current timer counter value as a 64-bit unsigned integer + pub fn now(&self) -> u64 { + now_ticks_read() + } + + /// Reset the timer counter to zero + /// + /// This performs a hardware reset of the OSTIMER peripheral, which will reset + /// the counter to zero and clear any pending interrupts. Note that this will + /// affect all timer operations including embassy-time. + /// + /// # Safety + /// This operation will reset the entire OSTIMER peripheral. Any active alarms + /// or time_driver operations will be disrupted. Use with caution. + pub fn reset(&self, peripherals: &crate::pac::Peripherals) { + critical_section::with(|_| { + let r: &Regs = unsafe { &*I::ptr() }; + + // Mask the peripheral interrupt flag before we toggle the reset line so that + // no new NVIC activity races with the reset sequence. + r.osevent_ctrl().write(|w| { + w.ostimer_intrflag() + .clear_bit_by_one() + .ostimer_intena() + .clear_bit() + }); + + unsafe { + crate::reset::assert::(peripherals); + } + + for _ in 0..RESET_STABILIZE_SPINS { + cortex_m::asm::nop(); + } + + unsafe { + crate::reset::release::(peripherals); + } + + while !::is_released( + &peripherals.mrcc0, + ) { + cortex_m::asm::nop(); + } + + for _ in 0..RESET_STABILIZE_SPINS { + cortex_m::asm::nop(); + } + + // Clear alarm bookkeeping before re-arming MATCH registers. + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + + prime_match_registers(r); + }); + + // Ensure no stale OS_EVENT request remains pending after the reset sequence. + crate::interrupt::OS_EVENT.unpend(); + } + + /// Schedule a single-shot alarm to expire after the specified delay in microseconds + /// + /// # Parameters + /// * `alarm` - The alarm instance to schedule + /// * `delay_us` - Delay in microseconds from now + /// + /// # Returns + /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity + pub fn schedule_alarm_delay(&self, alarm: &Alarm, delay_us: u64) -> bool { + let delay_ticks = (delay_us * self.clock_frequency_hz) / 1_000_000; + let target_time = now_ticks_read() + delay_ticks; + self.schedule_alarm_at(alarm, target_time) + } + + /// Schedule a single-shot alarm to expire at the specified absolute time in timer ticks + /// + /// # Parameters + /// * `alarm` - The alarm instance to schedule + /// * `target_ticks` - Absolute time in timer ticks when the alarm should expire + /// + /// # Returns + /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity + pub fn schedule_alarm_at(&self, alarm: &Alarm, target_ticks: u64) -> bool { + let now = now_ticks_read(); + + // Check if target time is in the past + if target_ticks <= now { + // Execute callback immediately if alarm was supposed to be active + if alarm.active.load(Ordering::Acquire) { + alarm.active.store(false, Ordering::Release); + if let Some(callback) = alarm.callback { + callback(); + } + if let Some(flag) = &alarm.flag { + flag.store(true, Ordering::Release); + } + } + return true; + } + + // Check for timer rollover + let max_future = now + TIMER_MAX_VALUE; + if target_ticks > max_future { + return false; // Would exceed timer capacity + } + + // Program the timer + let r: &Regs = unsafe { &*I::ptr() }; + + critical_section::with(|_| { + // Disable interrupt and clear flag + r.osevent_ctrl().write(|w| { + w.ostimer_intrflag() + .clear_bit_by_one() + .ostimer_intena() + .clear_bit() + }); + + if !wait_for_match_write_ready(r) { + prime_match_registers(r); + + if !wait_for_match_write_ready(r) { + alarm.active.store(false, Ordering::Release); + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + return false; + } + } + + // Mark alarm as active now that we know the MATCH registers are writable + alarm.active.store(true, Ordering::Release); + + // Set global alarm state for interrupt handler + ALARM_ACTIVE.store(true, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = target_ticks; + ALARM_CALLBACK = alarm.callback; + ALARM_FLAG = alarm.flag.map(|f| f as *const AtomicBool); + } + + // Program MATCH registers (Gray-coded) + let gray = bin_to_gray(target_ticks); + let l = (gray & LOW_32_BIT_MASK) as u32; + let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16; + + r.match_l().write(|w| unsafe { w.match_value().bits(l) }); + r.match_h().write(|w| unsafe { w.match_value().bits(h) }); + + if !wait_for_match_write_complete(r) { + alarm.active.store(false, Ordering::Release); + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + return false; + } + + let now_after_program = now_ticks_read(); + let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set(); + if now_after_program >= target_ticks && !intrflag_set { + alarm.active.store(false, Ordering::Release); + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + return false; + } + + // Enable interrupt + r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit()); + + true + }) + } + + /// Cancel any active alarm + pub fn cancel_alarm(&self, alarm: &Alarm) { + critical_section::with(|_| { + alarm.cancel(); + + // Clear global alarm state + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { ALARM_TARGET_TIME = 0 }; + + // Reset MATCH registers to maximum values to prevent spurious interrupts + let r: &Regs = unsafe { &*I::ptr() }; + prime_match_registers(r); + }); + } + + /// Check if an alarm has expired (call this from your interrupt handler) + /// Returns true if the alarm was active and has now expired + pub fn check_alarm_expired(&self, alarm: &Alarm) -> bool { + if alarm.active.load(Ordering::Acquire) { + alarm.active.store(false, Ordering::Release); + + // Execute callback + if let Some(callback) = alarm.callback { + callback(); + } + + // Set flag + if let Some(flag) = &alarm.flag { + flag.store(true, Ordering::Release); + } + + true + } else { + false + } + } +} + +/// Read current EVTIMER (Gray-coded) and convert to binary ticks. +#[inline(always)] +fn now_ticks_read() -> u64 { + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + + // Read high then low to minimize incoherent snapshots + let hi = (r.evtimerh().read().evtimer_count_value().bits() as u64) & (EVTIMER_HI_MASK as u64); + let lo = r.evtimerl().read().evtimer_count_value().bits() as u64; + + // Combine and convert from Gray code to binary + let gray = lo | (hi << EVTIMER_HI_SHIFT); + gray_to_bin(gray) +} + +// Instance trait like other drivers, providing a PAC pointer for this OSTIMER instance +pub trait Instance { + fn ptr() -> *const Regs; +} + +// Token for OSTIMER0 provided by embassy-hal-internal peripherals macro. +#[cfg(feature = "ostimer0")] +pub type Ostimer0 = crate::peripherals::OSTIMER0; + +#[cfg(feature = "ostimer0")] +impl Instance for crate::peripherals::OSTIMER0 { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Ostimer0::ptr() + } +} + +// Also implement Instance for the Peri wrapper type +#[cfg(feature = "ostimer0")] +impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Ostimer0::ptr() + } +} + +#[inline(always)] +fn bin_to_gray(x: u64) -> u64 { + x ^ (x >> 1) +} + +#[inline(always)] +fn gray_to_bin(gray: u64) -> u64 { + // More efficient iterative conversion using predefined shifts + let mut bin = gray; + for &shift in &GRAY_CONVERSION_SHIFTS { + bin ^= bin >> shift; + } + bin +} + +#[cfg(feature = "ostimer0")] +pub mod time_driver { + use super::{ + bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, + ALARM_TARGET_TIME, EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, + }; + use crate::pac; + use core::sync::atomic::Ordering; + use core::task::Waker; + use embassy_sync::waitqueue::AtomicWaker; + use embassy_time_driver as etd; + pub struct Driver; + static TIMER_WAKER: AtomicWaker = AtomicWaker::new(); + + impl etd::Driver for Driver { + fn now(&self) -> u64 { + // Use the hardware counter (frequency configured in init) + super::now_ticks_read() + } + + fn schedule_wake(&self, timestamp: u64, waker: &Waker) { + let now = self.now(); + + // If timestamp is in the past or very close to now, wake immediately + if timestamp <= now { + waker.wake_by_ref(); + return; + } + + // Prevent scheduling too far in the future (beyond timer rollover) + // This prevents wraparound issues + let max_future = now + super::TIMER_MAX_VALUE; + if timestamp > max_future { + // For very long timeouts, wake immediately to avoid rollover issues + waker.wake_by_ref(); + return; + } + + // Register the waker first so any immediate wake below is observed by the executor. + TIMER_WAKER.register(waker); + + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + + critical_section::with(|_| { + // Mask INTENA and clear flag + r.osevent_ctrl().write(|w| { + w.ostimer_intrflag() + .clear_bit_by_one() + .ostimer_intena() + .clear_bit() + }); + + // Read back to ensure W1C took effect on hardware + let _ = r.osevent_ctrl().read().ostimer_intrflag().bit(); + + if !super::wait_for_match_write_ready(r) { + super::prime_match_registers(r); + + if !super::wait_for_match_write_ready(r) { + // If we can't safely program MATCH, wake immediately and leave INTENA masked. + waker.wake_by_ref(); + return; + } + } + + // Program MATCH (Gray-coded). Write low then high, then fence. + let gray = bin_to_gray(timestamp); + let l = (gray & LOW_32_BIT_MASK) as u32; + + let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16; + + r.match_l().write(|w| unsafe { w.match_value().bits(l) }); + r.match_h().write(|w| unsafe { w.match_value().bits(h) }); + + if !super::wait_for_match_write_complete(r) { + waker.wake_by_ref(); + return; + } + + let now_after_program = super::now_ticks_read(); + let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set(); + if now_after_program >= timestamp && !intrflag_set { + waker.wake_by_ref(); + return; + } + + // Enable peripheral interrupt + r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit()); + }); + } + } + + /// Install the global embassy-time driver and configure NVIC priority for OS_EVENT. + /// + /// # Parameters + /// * `priority` - Interrupt priority for the OSTIMER interrupt + /// * `frequency_hz` - Actual OSTIMER clock frequency in Hz (stored for future use) + /// + /// Note: The frequency parameter is currently accepted for API compatibility. + /// The embassy_time_driver macro handles driver registration automatically. + pub fn init(priority: crate::interrupt::Priority, frequency_hz: u64) { + // Mask/clear at peripheral and set default MATCH + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + super::prime_match_registers(r); + + // Configure NVIC for timer operation + crate::interrupt::OS_EVENT.configure_for_timer(priority); + + // Note: The embassy_time_driver macro automatically registers the driver + // The frequency parameter is accepted for future compatibility + let _ = frequency_hz; // Suppress unused parameter warning + } + + // Export the global time driver expected by embassy-time + embassy_time_driver::time_driver_impl!(static DRIVER: Driver = Driver); + + /// To be called from the OS_EVENT IRQ. + pub fn on_interrupt() { + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + + // Critical section to prevent races with schedule_wake + critical_section::with(|_| { + // Check if interrupt is actually pending and handle it atomically + if r.osevent_ctrl().read().ostimer_intrflag().bit_is_set() { + // Clear flag and disable interrupt atomically + r.osevent_ctrl().write(|w| { + w.ostimer_intrflag() + .clear_bit_by_one() // Write-1-to-clear using safe helper + .ostimer_intena() + .clear_bit() + }); + + // Wake the waiting task + TIMER_WAKER.wake(); + + // Handle alarm callback if active and this interrupt is for the alarm + if ALARM_ACTIVE.load(Ordering::SeqCst) { + let current_time = now_ticks_read(); + let target_time = unsafe { ALARM_TARGET_TIME }; + + // Check if current time is close to alarm target time (within 1000 ticks for timing variations) + if current_time >= target_time && current_time <= target_time + 1000 { + ALARM_ACTIVE.store(false, Ordering::SeqCst); + unsafe { ALARM_TARGET_TIME = 0 }; + + // Execute callback if set + unsafe { + if let Some(callback) = ALARM_CALLBACK { + callback(); + } + } + + // Set flag if provided + unsafe { + if let Some(flag) = ALARM_FLAG { + (*flag).store(true, Ordering::SeqCst); + } + } + } + } + } + }); + } + + /// Type-level handler to be used with bind_interrupts! for OS_EVENT. + pub struct OsEventHandler; + impl crate::interrupt::typelevel::Handler + for OsEventHandler + { + unsafe fn on_interrupt() { + on_interrupt(); + } + } +} diff --git a/src/pins.rs b/src/pins.rs new file mode 100644 index 000000000..d46a3e6b3 --- /dev/null +++ b/src/pins.rs @@ -0,0 +1,127 @@ +//! Pin configuration helpers (separate from peripheral drivers). +use crate::pac; + +pub unsafe fn configure_uart2_pins_port2() { + // P2_2 = LPUART2_TX ALT3, P2_3 = LPUART2_RX ALT3 with pull-up, input enable, high drive, slow slew. + let port2 = &*pac::Port2::ptr(); + port2.pcr2().write(|w| { + w.ps() + .ps1() + .pe() + .pe1() + .sre() + .sre1() + .dse() + .dse1() + .mux() + .mux11() + .ibe() + .ibe1() + }); + port2.pcr3().write(|w| { + w.ps() + .ps1() + .pe() + .pe1() + .sre() + .sre1() + .dse() + .dse1() + .mux() + .mux11() + .ibe() + .ibe1() + }); + core::arch::asm!("dsb sy; isb sy"); +} + +pub unsafe fn configure_adc_pins() { + // P1_10 = ADC1_A8 + let port1 = &*pac::Port1::ptr(); + port1.pcr10().write(|w| { + w.ps() + .ps0() + .pe() + .pe0() + .sre() + .sre0() + .ode() + .ode0() + .dse() + .dse0() + .mux() + .mux00() + .ibe() + .ibe0() + .inv() + .inv0() + .lk() + .lk0() + + }); + core::arch::asm!("dsb sy; isb sy"); +} + +/// Configure a pin for a specific mux alternative. +/// +/// # Arguments +/// * `port` - Port number (0-4) +/// * `pin` - Pin number (varies by port: PORT0=0-7, PORT1=0-19, PORT2=0-26, PORT3=0-31, PORT4=0-7) +/// * `mux` - Mux alternative (0-15, where 0 = GPIO, 1-15 = other functions) +pub unsafe fn set_pin_mux(port: u8, pin: u8, mux: u8) { + // Validate mux value (0-15) + if mux > 15 { + panic!("Invalid mux value: {}, must be 0-15", mux); + } + + // Validate pin number based on port + let max_pin = match port { + 0 => 7, // PORT0: pins 0-7 + 1 => 19, // PORT1: pins 0-19 + 2 => 26, // PORT2: pins 0-26 + 3 => 31, // PORT3: pins 0-31 + 4 => 7, // PORT4: pins 0-7 + _ => panic!("Unsupported GPIO port: {}", port), + }; + + if pin > max_pin { + panic!( + "Invalid pin {} for PORT{}, max pin is {}", + pin, port, max_pin + ); + } + + // Get the base address for the port + let port_base: *mut u32 = match port { + 0 => pac::Port0::ptr() as *mut u32, + 1 => pac::Port1::ptr() as *mut u32, + 2 => pac::Port2::ptr() as *mut u32, + 3 => pac::Port3::ptr() as *mut u32, + 4 => pac::Port4::ptr() as *mut u32, + _ => panic!("Unsupported GPIO port: {}", port), + }; + + // PCR registers are 4 bytes apart, starting at offset 0 for PCR0 + let pcr_addr = port_base.add(pin as usize); + + // Read current PCR value + let current_val = pcr_addr.read_volatile(); + + // Clear mux bits (bits 8-11) and set new mux value + let new_val = (current_val & !(0xF << 8)) | ((mux as u32) << 8); + + // Write back the new value + pcr_addr.write_volatile(new_val); + + core::arch::asm!("dsb sy; isb sy"); +} + +/// Configure a pin for GPIO mode (ALT0). +/// This is a convenience function that calls set_pin_mux with mux=0. +/// +/// # Arguments +/// * `port` - Port number (0-4) +/// * `pin` - Pin number (varies by port: PORT0=0-7, PORT1=0-19, PORT2=0-26, PORT3=0-31, PORT4=0-7) +pub unsafe fn set_pin_mux_gpio(port: u8, pin: u8) { + set_pin_mux(port, pin, 0); +} diff --git a/src/reset.rs b/src/reset.rs new file mode 100644 index 000000000..1c131d1cc --- /dev/null +++ b/src/reset.rs @@ -0,0 +1,112 @@ +//! Reset control helpers built on PAC field writers. +use crate::pac; + +/// Trait describing a reset line that can be asserted/deasserted. +pub trait ResetLine { + /// Drive the peripheral out of reset. + unsafe fn release(mrcc: &pac::mrcc0::RegisterBlock); + + /// Drive the peripheral into reset. + unsafe fn assert(mrcc: &pac::mrcc0::RegisterBlock); + + /// Check whether the peripheral is currently released. + fn is_released(mrcc: &pac::mrcc0::RegisterBlock) -> bool; +} + +/// Release a reset line for the given peripheral set. +#[inline] +pub unsafe fn release(peripherals: &pac::Peripherals) { + R::release(&peripherals.mrcc0); +} + +/// Assert a reset line for the given peripheral set. +#[inline] +pub unsafe fn assert(peripherals: &pac::Peripherals) { + R::assert(&peripherals.mrcc0); +} + +/// Pulse a reset line (assert then release) with a short delay. +#[inline] +pub unsafe fn pulse(peripherals: &pac::Peripherals) { + let mrcc = &peripherals.mrcc0; + R::assert(mrcc); + cortex_m::asm::nop(); + cortex_m::asm::nop(); + R::release(mrcc); +} + +macro_rules! impl_reset_line { + ($name:ident, $reg:ident, $field:ident) => { + pub struct $name; + + impl ResetLine for $name { + #[inline] + unsafe fn release(mrcc: &pac::mrcc0::RegisterBlock) { + mrcc.$reg().modify(|_, w| w.$field().enabled()); + } + + #[inline] + unsafe fn assert(mrcc: &pac::mrcc0::RegisterBlock) { + mrcc.$reg().modify(|_, w| w.$field().disabled()); + } + + #[inline] + fn is_released(mrcc: &pac::mrcc0::RegisterBlock) -> bool { + mrcc.$reg().read().$field().is_enabled() + } + } + }; +} + +pub mod line { + use super::*; + + impl_reset_line!(Port2, mrcc_glb_rst1, port2); + impl_reset_line!(Port3, mrcc_glb_rst1, port3); + impl_reset_line!(Gpio3, mrcc_glb_rst2, gpio3); + impl_reset_line!(Lpuart2, mrcc_glb_rst0, lpuart2); + impl_reset_line!(Ostimer0, mrcc_glb_rst1, ostimer0); + impl_reset_line!(Port1, mrcc_glb_rst1, port1); + impl_reset_line!(Adc1, mrcc_glb_rst1, adc1); +} + +#[inline] +pub unsafe fn release_reset_port2(peripherals: &pac::Peripherals) { + release::(peripherals); +} + +#[inline] +pub unsafe fn release_reset_port3(peripherals: &pac::Peripherals) { + release::(peripherals); +} + +#[inline] +pub unsafe fn release_reset_gpio3(peripherals: &pac::Peripherals) { + release::(peripherals); +} + +#[inline] +pub unsafe fn release_reset_lpuart2(peripherals: &pac::Peripherals) { + release::(peripherals); +} + +#[inline] +pub unsafe fn release_reset_ostimer0(peripherals: &pac::Peripherals) { + release::(peripherals); +} + +/// Convenience shim retained for existing call sites. +#[inline] +pub unsafe fn reset_ostimer0(peripherals: &pac::Peripherals) { + pulse::(peripherals); +} + +#[inline] +pub unsafe fn release_reset_port1(peripherals: &pac::Peripherals) { + release::(peripherals); +} + +#[inline] +pub unsafe fn release_reset_adc1(peripherals: &pac::Peripherals) { + release::(peripherals); +} diff --git a/src/rtc.rs b/src/rtc.rs new file mode 100644 index 000000000..f83baab5e --- /dev/null +++ b/src/rtc.rs @@ -0,0 +1,281 @@ +//! RTC DateTime driver. +use crate::pac; +use crate::pac::rtc0::cr::{Um}; +use core::sync::atomic::{AtomicBool, Ordering}; + +type Regs = pac::rtc0::RegisterBlock; + +static ALARM_TRIGGERED: AtomicBool = AtomicBool::new(false); + +// Token-based instance pattern like embassy-imxrt +pub trait Instance { + fn ptr() -> *const Regs; +} + +/// Token for RTC0 +#[cfg(feature = "rtc0")] +pub type Rtc0 = crate::peripherals::RTC0; +#[cfg(feature = "rtc0")] +impl Instance for crate::peripherals::RTC0 { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Rtc0::ptr() + } +} + +// Also implement Instance for the Peri wrapper type +#[cfg(feature = "rtc0")] +impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::RTC0> { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Rtc0::ptr() + } +} + +const DAYS_IN_A_YEAR: u32 = 365; +const SECONDS_IN_A_DAY: u32 = 86400; +const SECONDS_IN_A_HOUR: u32 = 3600; +const SECONDS_IN_A_MINUTE: u32 = 60; +const YEAR_RANGE_START: u16 = 1970; + +#[derive(Debug, Clone, Copy)] +pub struct RtcDateTime { + pub year: u16, + pub month: u8, + pub day: u8, + pub hour: u8, + pub minute: u8, + pub second: u8, +} +#[derive(Copy, Clone)] +pub struct RtcConfig { + #[allow(dead_code)] + wakeup_select: bool, + update_mode: Um, + #[allow(dead_code)] + supervisor_access: bool, + compensation_interval: u8, + compensation_time: u8, +} + +#[derive(Copy, Clone)] +pub struct RtcInterruptEnable; +impl RtcInterruptEnable { + pub const RTC_TIME_INVALID_INTERRUPT_ENABLE: u32 = 1 << 0; + pub const RTC_TIME_OVERFLOW_INTERRUPT_ENABLE: u32 = 1 << 1; + pub const RTC_ALARM_INTERRUPT_ENABLE: u32 = 1 << 2; + pub const RTC_SECONDS_INTERRUPT_ENABLE: u32 = 1 << 4; +} + +pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 { + let month_days: [u16; 13] = [0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334]; + + let mut seconds = (datetime.year as u32 - 1970) * DAYS_IN_A_YEAR; + seconds += (datetime.year as u32 / 4) - (1970 / 4); + seconds += month_days[datetime.month as usize] as u32; + seconds += datetime.day as u32 - 1; + + if (datetime.year & 3 == 0) && (datetime.month <= 2) { + seconds -= 1; + } + + seconds = seconds * SECONDS_IN_A_DAY + + (datetime.hour as u32 * SECONDS_IN_A_HOUR) + + (datetime.minute as u32 * SECONDS_IN_A_MINUTE) + + datetime.second as u32; + + seconds +} + + +pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { + let mut seconds_remaining = seconds; + let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1; + seconds_remaining %= SECONDS_IN_A_DAY; + + let hour = (seconds_remaining / SECONDS_IN_A_HOUR) as u8; + seconds_remaining %= SECONDS_IN_A_HOUR; + let minute = (seconds_remaining / SECONDS_IN_A_MINUTE) as u8; + let second = (seconds_remaining % SECONDS_IN_A_MINUTE) as u8; + + let mut year = YEAR_RANGE_START; + let mut days_in_year = DAYS_IN_A_YEAR; + + while days > days_in_year { + days -= days_in_year; + year += 1; + + days_in_year = if year % 4 == 0 { + DAYS_IN_A_YEAR + 1 + } else { + DAYS_IN_A_YEAR + }; + } + + let mut days_per_month = [0u8, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31]; + if year % 4 == 0 { + days_per_month[2] = 29; + } + + let mut month = 1; + for m in 1..=12 { + if days <= days_per_month[m] as u32 { + month = m; + break; + } else { + days -= days_per_month[m] as u32; + } + } + + let day = days as u8; + + RtcDateTime { + year, + month: month as u8, + day, + hour, + minute, + second, + } +} + +pub fn get_default_config() -> RtcConfig { + RtcConfig { + wakeup_select: false, + update_mode: Um::Um0, + supervisor_access: false, + compensation_interval: 0, + compensation_time: 0, + } +} +/// Minimal RTC handle for a specific instance I (store the zero-sized token like embassy) +pub struct Rtc { + _inst: core::marker::PhantomData, +} + +impl Rtc { + /// initialize RTC + pub fn new(_inst: impl Instance, config: RtcConfig) -> Self { + let rtc = unsafe { &*I::ptr() }; + + /* RTC reset */ + rtc.cr().modify(|_, w| w.swr().set_bit()); + rtc.cr().modify(|_, w| w.swr().clear_bit()); + rtc.tsr().write(|w| unsafe { w.bits(1) }); + + rtc.cr().modify(|_, w| w.um().variant(config.update_mode)); + + rtc.tcr().modify(|_, w| unsafe { + w.cir().bits(config.compensation_interval) + .tcr().bits(config.compensation_time) + }); + + Self { _inst: core::marker::PhantomData } + } + + pub fn set_datetime(&self, datetime: RtcDateTime) { + let rtc = unsafe { &*I::ptr() }; + let seconds = convert_datetime_to_seconds(&datetime); + rtc.tsr().write(|w| unsafe { w.bits(seconds) }); + } + + pub fn get_datetime(&self) -> RtcDateTime { + let rtc = unsafe { &*I::ptr() }; + let seconds = rtc.tsr().read().bits(); + convert_seconds_to_datetime(seconds) + } + + pub fn set_alarm(&self, alarm: RtcDateTime) { + let rtc = unsafe { &*I::ptr() }; + let seconds = convert_datetime_to_seconds(&alarm); + + rtc.tar().write(|w| unsafe { w.bits(0) }); + let mut timeout = 10000; + while rtc.tar().read().bits() != 0 && timeout > 0 { + timeout -= 1; + } + + rtc.tar().write(|w| unsafe { w.bits(seconds) }); + + let mut timeout = 10000; + while rtc.tar().read().bits() != seconds && timeout > 0 { + timeout -= 1; + } + } + + pub fn get_alarm(&self) -> RtcDateTime{ + let rtc = unsafe { &*I::ptr() }; + let alarm_seconds = rtc.tar().read().bits(); + convert_seconds_to_datetime(alarm_seconds) + } + + pub fn start(&self) { + let rtc = unsafe { &*I::ptr() }; + rtc.sr().modify(|_, w| w.tce().set_bit()); + } + + pub fn stop(&self) { + let rtc = unsafe { &*I::ptr() }; + rtc.sr().modify(|_, w| w.tce().clear_bit()); + } + + pub fn set_interrupt(&self, mask: u32) { + let rtc = unsafe { &*I::ptr() }; + + if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tiie().tiie_1()); + } + if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.toie().toie_1()); + } + if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.taie().taie_1()); + } + if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tsie().tsie_1()); + } + + ALARM_TRIGGERED.store(false, Ordering::SeqCst); + } + + pub fn disable_interrupt(&self, mask: u32) { + let rtc = unsafe { &*I::ptr() }; + + if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tiie().tiie_0()); + } + if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.toie().toie_0()); + } + if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.taie().taie_0()); + } + if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tsie().tsie_0()); + } + } + + pub fn clear_alarm_flag(&self) { + let rtc = unsafe { &*I::ptr() }; + rtc.ier().modify(|_, w| w.taie().clear_bit()); + } + + pub fn is_alarm_triggered(&self) -> bool { + ALARM_TRIGGERED.load(Ordering::Relaxed) + } +} + +pub fn on_interrupt() { + let rtc = unsafe { &*pac::Rtc0::ptr() }; + // Check if this is actually a time alarm interrupt + let sr = rtc.sr().read(); + if sr.taf().bit_is_set() { + rtc.ier().modify(|_, w| w.taie().clear_bit()); + ALARM_TRIGGERED.store(true, Ordering::SeqCst); + } +} + +pub struct RtcHandler; +impl crate::interrupt::typelevel::Handler for RtcHandler { + unsafe fn on_interrupt() { on_interrupt(); } +} \ No newline at end of file diff --git a/src/uart.rs b/src/uart.rs new file mode 100644 index 000000000..45b6b2be3 --- /dev/null +++ b/src/uart.rs @@ -0,0 +1,308 @@ +//! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering. +//! WARNING: This is a narrow implementation only for debug console (115200 8N1). + +use crate::pac; +use core::cell::RefCell; +use cortex_m::interrupt::Mutex; +use embassy_sync::signal::Signal; + +// svd2rust defines the shared LPUART RegisterBlock under lpuart0; all instances reuse it. +type Regs = pac::lpuart0::RegisterBlock; + +// Token-based instance pattern like embassy-imxrt +pub trait Instance { + fn ptr() -> *const Regs; +} + +/// Token for LPUART2 provided by embassy-hal-internal peripherals macro. +#[cfg(feature = "lpuart2")] +pub type Lpuart2 = crate::peripherals::LPUART2; +#[cfg(feature = "lpuart2")] +impl Instance for crate::peripherals::LPUART2 { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Lpuart2::ptr() + } +} + +// Also implement Instance for the Peri wrapper type +#[cfg(feature = "lpuart2")] +impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::LPUART2> { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Lpuart2::ptr() + } +} + +/// UART configuration (explicit src_hz; no hardcoded frequencies) +#[derive(Copy, Clone)] +pub struct Config { + pub src_hz: u32, + pub baud: u32, + pub parity: Parity, + pub stop_bits: StopBits, +} + +#[derive(Copy, Clone)] +pub enum Parity { + None, + Even, + Odd, +} +#[derive(Copy, Clone)] +pub enum StopBits { + One, + Two, +} + +impl Config { + pub fn new(src_hz: u32) -> Self { + Self { + src_hz, + baud: 115_200, + parity: Parity::None, + stop_bits: StopBits::One, + } + } +} + +/// Compute a valid (OSR, SBR) tuple for given source clock and baud. +/// Uses a functional fold approach to find the best OSR/SBR combination +/// with minimal baud rate error. +fn compute_osr_sbr(src_hz: u32, baud: u32) -> (u8, u16) { + let (best_osr, best_sbr, _best_err) = (8u32..=32).fold( + (16u8, 4u16, u32::MAX), // (best_osr, best_sbr, best_err) + |(best_osr, best_sbr, best_err), osr| { + let denom = baud.saturating_mul(osr); + if denom == 0 { + return (best_osr, best_sbr, best_err); + } + + let sbr = (src_hz + denom / 2) / denom; // round + if sbr == 0 || sbr > 0x1FFF { + return (best_osr, best_sbr, best_err); + } + + let actual = src_hz / (osr * sbr); + let err = actual.abs_diff(baud); + + // Update best if this is better, or same error but higher OSR + if err < best_err || (err == best_err && osr as u8 > best_osr) { + (osr as u8, sbr as u16, err) + } else { + (best_osr, best_sbr, best_err) + } + }, + ); + (best_osr, best_sbr) +} + +/// Minimal UART handle for a specific instance I (store the zero-sized token like embassy) +pub struct Uart { + _inst: core::marker::PhantomData, +} + +impl Uart { + /// Create and initialize LPUART (reset + config). Clocks and pins must be prepared by the caller. + pub fn new(_inst: impl Instance, cfg: Config) -> Self { + let l = unsafe { &*I::ptr() }; + // 1) software reset pulse + l.global().write(|w| w.rst().reset()); + cortex_m::asm::delay(3); // Short delay for reset to take effect + l.global().write(|w| w.rst().no_effect()); + cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset + // 2) BAUD + let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud); + l.baud().modify(|_, w| { + let w = match cfg.stop_bits { + StopBits::One => w.sbns().one(), + StopBits::Two => w.sbns().two(), + }; + // OSR field encodes (osr-1); use raw bits to avoid a long match on all variants + let raw_osr = osr.saturating_sub(1) as u8; + unsafe { w.osr().bits(raw_osr).sbr().bits(sbr) } + }); + // 3) CTRL baseline and parity + l.ctrl().write(|w| { + let w = w.ilt().from_stop().idlecfg().idle_2(); + let w = match cfg.parity { + Parity::None => w.pe().disabled(), + Parity::Even => w.pe().enabled().pt().even(), + Parity::Odd => w.pe().enabled().pt().odd(), + }; + w.re().enabled().te().enabled().rie().disabled() + }); + // 4) FIFOs and WATER: keep it simple for polling; disable FIFOs and set RX watermark to 0 + l.fifo().modify(|_, w| { + w.txfe() + .disabled() + .rxfe() + .disabled() + .txflush() + .txfifo_rst() + .rxflush() + .rxfifo_rst() + }); + l.water() + .modify(|_, w| unsafe { w.txwater().bits(0).rxwater().bits(0) }); + Self { _inst: core::marker::PhantomData } + } + + /// Enable RX interrupts. The caller must ensure an appropriate IRQ handler is installed. + pub unsafe fn enable_rx_interrupts(&self) { + let l = &*I::ptr(); + l.ctrl().modify(|_, w| w.rie().enabled()); + } + + #[inline(never)] + pub fn write_byte(&self, b: u8) { + let l = unsafe { &*I::ptr() }; + // Timeout after ~10ms at 12MHz (assuming 115200 baud, should be plenty) + const DATA_OFFSET: usize = 0x1C; // DATA register offset inside LPUART block + let data_ptr = unsafe { (I::ptr() as *mut u8).add(DATA_OFFSET) }; + for _ in 0..120000 { + if l.water().read().txcount().bits() == 0 { + unsafe { core::ptr::write_volatile(data_ptr, b) }; + return; + } + } + // If timeout, skip the write to avoid hanging + } + + #[inline(never)] + pub fn write_str_blocking(&self, s: &str) { + for &b in s.as_bytes() { + if b == b'\n' { + self.write_byte(b'\r'); + } + self.write_byte(b); + } + } + pub fn read_byte_blocking(&self) -> u8 { + let l = unsafe { &*I::ptr() }; + while !l.stat().read().rdrf().is_rxdata() {} + (l.data().read().bits() & 0xFF) as u8 + } +} + +// Simple ring buffer for UART RX data +const RX_BUFFER_SIZE: usize = 256; +pub struct RingBuffer { + buffer: [u8; RX_BUFFER_SIZE], + read_idx: usize, + write_idx: usize, + count: usize, +} + +impl RingBuffer { + pub const fn new() -> Self { + Self { + buffer: [0; RX_BUFFER_SIZE], + read_idx: 0, + write_idx: 0, + count: 0, + } + } + + pub fn push(&mut self, data: u8) -> bool { + if self.count >= RX_BUFFER_SIZE { + return false; // Buffer full + } + self.buffer[self.write_idx] = data; + self.write_idx = (self.write_idx + 1) % RX_BUFFER_SIZE; + self.count += 1; + true + } + + pub fn pop(&mut self) -> Option { + if self.count == 0 { + return None; + } + let data = self.buffer[self.read_idx]; + self.read_idx = (self.read_idx + 1) % RX_BUFFER_SIZE; + self.count -= 1; + Some(data) + } + + pub fn is_empty(&self) -> bool { + self.count == 0 + } + + pub fn len(&self) -> usize { + self.count + } +} + +// Global RX buffer shared between interrupt handler and UART instance +static RX_BUFFER: Mutex> = Mutex::new(RefCell::new(RingBuffer::new())); +static RX_SIGNAL: Signal = + Signal::new(); + +// Debug counter for interrupt handler calls +static mut INTERRUPT_COUNT: u32 = 0; + +impl Uart { + /// Read a byte asynchronously using interrupts + pub async fn read_byte_async(&self) -> u8 { + loop { + // Check if we have data in the buffer + let byte = cortex_m::interrupt::free(|cs| { + let mut buffer = RX_BUFFER.borrow(cs).borrow_mut(); + buffer.pop() + }); + + if let Some(byte) = byte { + return byte; + } + + // Wait for the interrupt signal + RX_SIGNAL.wait().await; + } + } + + /// Check if there's data available in the RX buffer + pub fn rx_data_available(&self) -> bool { + cortex_m::interrupt::free(|cs| { + let buffer = RX_BUFFER.borrow(cs).borrow(); + !buffer.is_empty() + }) + } + + /// Try to read a byte from RX buffer (non-blocking) + pub fn try_read_byte(&self) -> Option { + cortex_m::interrupt::free(|cs| { + let mut buffer = RX_BUFFER.borrow(cs).borrow_mut(); + buffer.pop() + }) + } +} + +/// Type-level handler for LPUART2 interrupts, compatible with bind_interrupts!. +pub struct UartInterruptHandler; + +impl crate::interrupt::typelevel::Handler + for UartInterruptHandler +{ + unsafe fn on_interrupt() { + INTERRUPT_COUNT += 1; + + let lpuart = &*pac::Lpuart2::ptr(); + + // Check if we have RX data + if lpuart.stat().read().rdrf().is_rxdata() { + // Read the data byte + let data = (lpuart.data().read().bits() & 0xFF) as u8; + + // Store in ring buffer + cortex_m::interrupt::free(|cs| { + let mut buffer = RX_BUFFER.borrow(cs).borrow_mut(); + if buffer.push(data) { + // Data added successfully, signal waiting tasks + RX_SIGNAL.signal(()); + } + }); + } + // Always clear any error flags that might cause spurious interrupts + let _ = lpuart.stat().read(); + } +} diff --git a/supply-chain/README.md b/supply-chain/README.md deleted file mode 100644 index d43d50485..000000000 --- a/supply-chain/README.md +++ /dev/null @@ -1,83 +0,0 @@ -# Working with cargo vet - -## Introduction - -`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity. -It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust. -To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet) - ---- - -## Adding a new dependency - -When updating or adding a new dependency, we need to ensure it's audited before being merged into main. -For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository. -_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._ -Follow the process below to ensure compliance: - -### For Developers -1. **Respond to `cargo vet` failures**: - - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire - - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies - -2. **Engage with auditors**: - - Respond to any questions that the auditors might have regarding the need of any new dependencies - -3. **Rebase and verify**: - - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository - - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet` - ```bash - git fetch upstream - git rebase upstream/main - cargo vet - ``` - -4. **Update PR**: - - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR - - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase - ```bash - git push -f - ``` - -5. **Check PR status**: - - The existing PR comment from the previous failure will be updated with a success message once the check passes - -### For Auditors - -1. **Review the questionnaire**: - - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure - - Respond to the developer comment in case more information is needed - -2. **Audit new dependencies**: - - Inspect the `cargo vet` failures using your preferred method - - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked` - - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked` - - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally) - -3. **Follow `cargo vet` recommendations**: - - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies - -4. **Record audits**: - - Use `cargo vet certify` to add new audits to _audits.toml_ - - Verify all dependencies pass using `cargo vet` - -5. **Decide audit location**: - - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) - - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits - -6. **Communicate successful audit**: - - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass - ---- - -## Tips for using `cargo vet`: - -- **Update _imports.lock_**: - - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project. - -- **Add exemptions**: - - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption ` to add the dependency to exemptions in _config.toml_ - - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions` - -- **Prune unnecessary entries**: - - Remove unnecessary exemptions and imports using `cargo vet prune` \ No newline at end of file diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml deleted file mode 100644 index 2772ccb21..000000000 --- a/supply-chain/audits.toml +++ /dev/null @@ -1,4 +0,0 @@ - -# cargo-vet audits file - -[audits] diff --git a/supply-chain/config.toml b/supply-chain/config.toml deleted file mode 100644 index 55618c2ff..000000000 --- a/supply-chain/config.toml +++ /dev/null @@ -1,14 +0,0 @@ - -# cargo-vet config file - -[cargo-vet] -version = "0.10" - -[imports.OpenDevicePartnership] -url = "https://raw.githubusercontent.com/OpenDevicePartnership/rust-crate-audits/main/audits.toml" - -[imports.google] -url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" - -[imports.mozilla] -url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock deleted file mode 100644 index 219dba4ee..000000000 --- a/supply-chain/imports.lock +++ /dev/null @@ -1,8 +0,0 @@ - -# cargo-vet imports lock - -[audits.OpenDevicePartnership.audits] - -[audits.google.audits] - -[audits.mozilla.audits] diff --git a/tools/run_and_attach_rtt.sh b/tools/run_and_attach_rtt.sh new file mode 100644 index 000000000..13041d06b --- /dev/null +++ b/tools/run_and_attach_rtt.sh @@ -0,0 +1,24 @@ +#!/usr/bin/env bash +set -euo pipefail + +ELF="${1:-target/thumbv8m.main-none-eabihf/debug/examples/hello}" +PROBE_ID="${2:-1fc9:0143:H3AYDQVQMTROB}" +CHIP="${3:-MCXA276}" +SPEED="${4:-1000}" + +# 1) Flash & run using the existing run.sh (probe is in use only during this step) +./run.sh "$ELF" + +# 2) Give target a short moment to boot and set up RTT CB in RAM +sleep 0.5 + +# 3) Attach RTT/defmt using probe-rs (no flashing) +exec probe-rs attach \ + --chip "$CHIP" \ + --probe "$PROBE_ID" \ + --protocol swd \ + --speed "$SPEED" \ + "$ELF" \ + --rtt-scan-memory \ + --log-format oneline + diff --git a/tools/run_jlink_noblock.sh b/tools/run_jlink_noblock.sh new file mode 100644 index 000000000..3ea1f2b4b --- /dev/null +++ b/tools/run_jlink_noblock.sh @@ -0,0 +1,76 @@ +#!/usr/bin/env bash +set -euo pipefail + +ELF="${1:-}" +PROBE_ID="${2:-1366:0101:000600110607}" # default to your J-Link +CHIP="${3:-MCXA276}" +SPEED="${4:-1000}" +PORT="${PROBE_RS_GDB_PORT:-1337}" + +if [[ -z "${ELF}" || ! -f "${ELF}" ]]; then + echo "Usage: $0 [probe-id] [chip] [speed-khz]" >&2 + exit 1 +fi + +if ! command -v probe-rs >/dev/null 2>&1; then + echo "probe-rs not found (cargo install probe-rs --features cli)" >&2 + exit 1 +fi +if ! command -v gdb-multiarch >/dev/null 2>&1; then + echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." >&2 + exit 1 +fi + +# Start probe-rs GDB server +SERVER_LOG=$(mktemp) +probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" --probe "${PROBE_ID}" \ + >"${SERVER_LOG}" 2>&1 & +GDB_SERVER_PID=$! + +# Wait for readiness +for _ in {1..50}; do + if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then break; fi + if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then + echo "probe-rs gdb server failed. Log:" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + kill "${GDB_SERVER_PID}" 2>/dev/null || true + exit 1 + fi + sleep 0.1 +done + +# GDB script: load, resume, detach +GDB_SCRIPT=$(mktemp) +cat >"${GDB_SCRIPT}" <&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + kill "${GDB_SERVER_PID}" 2>/dev/null || true + exit 1 +fi + +# Stop server now that we've detached +kill "${GDB_SERVER_PID}" 2>/dev/null || true +rm -f "${GDB_SCRIPT}" "${SERVER_LOG}" || true + +echo "Flashed, resumed, and detached (probe free)." + -- cgit From d61f212b3378f2fd4fbf45dbcd4529ad6a2bfc43 Mon Sep 17 00:00:00 2001 From: Bogdan Petru Chircu Mare Date: Thu, 6 Nov 2025 12:57:06 -0800 Subject: feat(mcxa276): use external mcxa-pac; remove in-tree PAC; ADC: stop writing CMDL1.CTYPE (read-only) --- Cargo.toml | 2 +- SW-Content-Register.txt | 12 +- mcxa276-pac/Cargo.toml | 17 - mcxa276-pac/build.rs | 17 - mcxa276-pac/device.x | 129 - mcxa276-pac/device.x.backup | 105 - mcxa276-pac/src/adc0.rs | 448 -- mcxa276-pac/src/adc0/cal_gar.rs | 35 - mcxa276-pac/src/adc0/cfg.rs | 518 -- mcxa276-pac/src/adc0/cfg2.rs | 177 - mcxa276-pac/src/adc0/cmdh1.rs | 900 --- mcxa276-pac/src/adc0/cmdh2.rs | 900 --- mcxa276-pac/src/adc0/cmdh3.rs | 900 --- mcxa276-pac/src/adc0/cmdh4.rs | 900 --- mcxa276-pac/src/adc0/cmdh5.rs | 900 --- mcxa276-pac/src/adc0/cmdh6.rs | 900 --- mcxa276-pac/src/adc0/cmdh7.rs | 900 --- mcxa276-pac/src/adc0/cmdl1.rs | 331 - mcxa276-pac/src/adc0/cmdl2.rs | 323 - mcxa276-pac/src/adc0/cmdl3.rs | 323 - mcxa276-pac/src/adc0/cmdl4.rs | 323 - mcxa276-pac/src/adc0/cmdl5.rs | 323 - mcxa276-pac/src/adc0/cmdl6.rs | 323 - mcxa276-pac/src/adc0/cmdl7.rs | 323 - mcxa276-pac/src/adc0/ctrl.rs | 649 -- mcxa276-pac/src/adc0/cv.rs | 49 - mcxa276-pac/src/adc0/de.rs | 84 - mcxa276-pac/src/adc0/fctrl0.rs | 42 - mcxa276-pac/src/adc0/gcc0.rs | 61 - mcxa276-pac/src/adc0/gcr0.rs | 100 - mcxa276-pac/src/adc0/hstrim.rs | 35 - mcxa276-pac/src/adc0/ie.rs | 397 -- mcxa276-pac/src/adc0/ofstrim.rs | 35 - mcxa276-pac/src/adc0/param.rs | 115 - mcxa276-pac/src/adc0/pause.rs | 98 - mcxa276-pac/src/adc0/resfifo0.rs | 338 - mcxa276-pac/src/adc0/stat.rs | 492 -- mcxa276-pac/src/adc0/swtrig.rs | 273 - mcxa276-pac/src/adc0/tctrl.rs | 370 - mcxa276-pac/src/adc0/tstat.rs | 396 -- mcxa276-pac/src/adc0/verid.rs | 442 -- mcxa276-pac/src/aoi0.rs | 94 - mcxa276-pac/src/aoi0/bfcrt010.rs | 789 --- mcxa276-pac/src/aoi0/bfcrt011.rs | 789 --- mcxa276-pac/src/aoi0/bfcrt012.rs | 789 --- mcxa276-pac/src/aoi0/bfcrt013.rs | 789 --- mcxa276-pac/src/aoi0/bfcrt230.rs | 789 --- mcxa276-pac/src/aoi0/bfcrt231.rs | 789 --- mcxa276-pac/src/aoi0/bfcrt232.rs | 789 --- mcxa276-pac/src/aoi0/bfcrt233.rs | 789 --- mcxa276-pac/src/can0.rs | 7163 -------------------- mcxa276-pac/src/can0/cbt.rs | 154 - mcxa276-pac/src/can0/crcr.rs | 27 - mcxa276-pac/src/can0/ctrl1.rs | 721 -- mcxa276-pac/src/can0/ctrl1_pn.rs | 520 -- mcxa276-pac/src/can0/ctrl2.rs | 744 -- mcxa276-pac/src/can0/ctrl2_pn.rs | 35 - mcxa276-pac/src/can0/ecr.rs | 77 - mcxa276-pac/src/can0/edcbt.rs | 63 - mcxa276-pac/src/can0/encbt.rs | 63 - mcxa276-pac/src/can0/eprs.rs | 49 - mcxa276-pac/src/can0/erfcr.rs | 140 - mcxa276-pac/src/can0/erffel.rs | 35 - mcxa276-pac/src/can0/erfier.rs | 273 - mcxa276-pac/src/can0/erfsr.rs | 426 -- mcxa276-pac/src/can0/esr1.rs | 1278 ---- mcxa276-pac/src/can0/esr2.rs | 102 - mcxa276-pac/src/can0/etdc.rs | 232 - mcxa276-pac/src/can0/fdcbt.rs | 91 - mcxa276-pac/src/can0/fdcrc.rs | 27 - mcxa276-pac/src/can0/fdctrl.rs | 330 - mcxa276-pac/src/can0/flt_dlc.rs | 51 - mcxa276-pac/src/can0/flt_id1.rs | 161 - mcxa276-pac/src/can0/flt_id2_idmask.rs | 161 - mcxa276-pac/src/can0/iflag1.rs | 302 - mcxa276-pac/src/can0/imask1.rs | 35 - mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb10_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb10_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb10_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb10_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb11_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb11_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb11_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb11_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb12_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb12_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb12_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb12_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb13_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb13_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb13_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb13_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb13_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb13_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb14_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb14_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb14_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb14_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb14_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb14_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb15_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb15_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb15_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb15_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb15_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb15_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb16_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb16_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb16_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb16_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb16_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb17_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb17_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb17_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb17_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb18_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb18_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb18_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb18_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb19_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb19_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb19_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb19_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb19_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb1_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb1_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb20_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb20_16b_id.rs | 63 - .../src/can0/mb_16b_group_mb20_16b_word0.rs | 77 - .../src/can0/mb_16b_group_mb20_16b_word1.rs | 77 - .../src/can0/mb_16b_group_mb20_16b_word2.rs | 77 - .../src/can0/mb_16b_group_mb20_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb2_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb2_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb3_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb3_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb4_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb4_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb5_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb5_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb6_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb6_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb7_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb7_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb8_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb8_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb9_16b_cs.rs | 147 - mcxa276-pac/src/can0/mb_16b_group_mb9_16b_id.rs | 63 - mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word0.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word1.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word2.rs | 77 - mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word3.rs | 77 - mcxa276-pac/src/can0/mb_32b_group_mb0_32b_cs.rs | 147 - mcxa276-pac/src/can0/mb_32b_group_mb0_32b_id.rs | 63 - mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word0.rs | 77 - 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77 - mcxa276-pac/src/can0/mb_8b_group_mb19_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb19_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb1_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb1_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb20_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb20_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb21_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb21_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb22_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb22_8b_id.rs | 63 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| 77 - mcxa276-pac/src/can0/mb_8b_group_mb27_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs | 63 - mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs | 77 - mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs | 147 - mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs | 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mcxa276-pac/src/can0/pl1_lo.rs | 77 - mcxa276-pac/src/can0/pl2_plmask_hi.rs | 77 - mcxa276-pac/src/can0/pl2_plmask_lo.rs | 77 - mcxa276-pac/src/can0/rx14mask.rs | 35 - mcxa276-pac/src/can0/rx15mask.rs | 35 - mcxa276-pac/src/can0/rxfgmask.rs | 35 - mcxa276-pac/src/can0/rxfir.rs | 20 - mcxa276-pac/src/can0/rximr.rs | 35 - mcxa276-pac/src/can0/rxmgmask.rs | 35 - mcxa276-pac/src/can0/timer.rs | 35 - mcxa276-pac/src/can0/wmb.rs | 51 - mcxa276-pac/src/can0/wmb/wmb_cs.rs | 143 - mcxa276-pac/src/can0/wmb/wmb_d03.rs | 41 - mcxa276-pac/src/can0/wmb/wmb_d47.rs | 41 - mcxa276-pac/src/can0/wmb/wmb_id.rs | 20 - mcxa276-pac/src/can0/wu_mtc.rs | 155 - mcxa276-pac/src/cdog0.rs | 216 - mcxa276-pac/src/cdog0/add.rs | 22 - mcxa276-pac/src/cdog0/add1.rs | 22 - mcxa276-pac/src/cdog0/add16.rs | 22 - mcxa276-pac/src/cdog0/add256.rs | 22 - mcxa276-pac/src/cdog0/assert16.rs | 22 - mcxa276-pac/src/cdog0/control.rs | 648 -- mcxa276-pac/src/cdog0/flags.rs | 465 -- mcxa276-pac/src/cdog0/instruction_timer.rs | 22 - mcxa276-pac/src/cdog0/persistent.rs | 35 - mcxa276-pac/src/cdog0/reload.rs | 37 - mcxa276-pac/src/cdog0/restart.rs | 22 - mcxa276-pac/src/cdog0/start.rs | 22 - mcxa276-pac/src/cdog0/status.rs | 43 - mcxa276-pac/src/cdog0/status2.rs | 34 - mcxa276-pac/src/cdog0/stop.rs | 22 - mcxa276-pac/src/cdog0/sub.rs | 22 - mcxa276-pac/src/cdog0/sub1.rs | 22 - mcxa276-pac/src/cdog0/sub16.rs | 22 - mcxa276-pac/src/cdog0/sub256.rs | 22 - mcxa276-pac/src/cmc.rs | 189 - mcxa276-pac/src/cmc/ckctrl.rs | 167 - mcxa276-pac/src/cmc/ckstat.rs | 147 - mcxa276-pac/src/cmc/corectl.rs | 84 - mcxa276-pac/src/cmc/dbgctl.rs | 84 - mcxa276-pac/src/cmc/flashcr.rs | 210 - mcxa276-pac/src/cmc/fm0.rs | 84 - mcxa276-pac/src/cmc/gpmctrl.rs | 35 - mcxa276-pac/src/cmc/mr0.rs | 36 - mcxa276-pac/src/cmc/pmctrlmain.rs | 117 - mcxa276-pac/src/cmc/pmprot.rs | 336 - mcxa276-pac/src/cmc/rpc.rs | 161 - mcxa276-pac/src/cmc/srie.rs | 590 -- mcxa276-pac/src/cmc/srif.rs | 526 -- mcxa276-pac/src/cmc/srs.rs | 710 -- mcxa276-pac/src/cmc/ssrs.rs | 1073 --- mcxa276-pac/src/cmc/verid.rs | 36 - mcxa276-pac/src/cmp0.rs | 151 - mcxa276-pac/src/cmp0/ccr0.rs | 149 - mcxa276-pac/src/cmp0/ccr1.rs | 992 --- mcxa276-pac/src/cmp0/ccr2.rs | 513 -- mcxa276-pac/src/cmp0/csr.rs | 218 - mcxa276-pac/src/cmp0/dcr.rs | 224 - mcxa276-pac/src/cmp0/ier.rs | 210 - mcxa276-pac/src/cmp0/param.rs | 102 - mcxa276-pac/src/cmp0/rrcr0.rs | 1018 --- mcxa276-pac/src/cmp0/rrcr1.rs | 736 -- mcxa276-pac/src/cmp0/rrcr2.rs | 98 - mcxa276-pac/src/cmp0/rrcsr.rs | 133 - mcxa276-pac/src/cmp0/rrsr.rs | 526 -- mcxa276-pac/src/cmp0/verid.rs | 68 - mcxa276-pac/src/crc0.rs | 39 - mcxa276-pac/src/crc0/ctrl.rs | 402 -- mcxa276-pac/src/crc0/data.rs | 79 - mcxa276-pac/src/crc0/gpoly.rs | 51 - mcxa276-pac/src/ctimer0.rs | 168 - mcxa276-pac/src/ctimer0/ccr.rs | 777 --- mcxa276-pac/src/ctimer0/cr.rs | 20 - mcxa276-pac/src/ctimer0/ctcr.rs | 375 - mcxa276-pac/src/ctimer0/emr.rs | 657 -- mcxa276-pac/src/ctimer0/ir.rs | 133 - mcxa276-pac/src/ctimer0/mcr.rs | 1029 --- mcxa276-pac/src/ctimer0/mr.rs | 35 - mcxa276-pac/src/ctimer0/msr.rs | 35 - mcxa276-pac/src/ctimer0/pc.rs | 35 - mcxa276-pac/src/ctimer0/pr.rs | 35 - mcxa276-pac/src/ctimer0/pwmc.rs | 273 - mcxa276-pac/src/ctimer0/tc.rs | 35 - mcxa276-pac/src/ctimer0/tcr.rs | 273 - mcxa276-pac/src/dac0.rs | 138 - mcxa276-pac/src/dac0/data.rs | 35 - mcxa276-pac/src/dac0/der.rs | 147 - mcxa276-pac/src/dac0/fcr.rs | 35 - mcxa276-pac/src/dac0/fpr.rs | 27 - mcxa276-pac/src/dac0/fsr.rs | 399 -- mcxa276-pac/src/dac0/gcr.rs | 687 -- mcxa276-pac/src/dac0/ier.rs | 462 -- mcxa276-pac/src/dac0/param.rs | 102 - mcxa276-pac/src/dac0/pcr.rs | 49 - mcxa276-pac/src/dac0/rcr.rs | 147 - mcxa276-pac/src/dac0/tcr.rs | 84 - mcxa276-pac/src/dac0/verid.rs | 36 - mcxa276-pac/src/dbgmailbox.rs | 51 - mcxa276-pac/src/dbgmailbox/csw.rs | 399 -- mcxa276-pac/src/dbgmailbox/id.rs | 22 - mcxa276-pac/src/dbgmailbox/request.rs | 35 - mcxa276-pac/src/dbgmailbox/return_.rs | 35 - mcxa276-pac/src/dma0.rs | 68 - mcxa276-pac/src/dma0/ch_grpri.rs | 35 - mcxa276-pac/src/dma0/mp_csr.rs | 575 -- mcxa276-pac/src/dma0/mp_es.rs | 430 -- mcxa276-pac/src/dma0/mp_hrs.rs | 20 - mcxa276-pac/src/dma0/mp_int.rs | 20 - mcxa276-pac/src/edma_0_tcd0.rs | 26 - mcxa276-pac/src/edma_0_tcd0/tcd.rs | 229 - mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs | 295 - mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs | 413 -- mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs | 85 - mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs | 35 - mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs | 161 - mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs | 134 - .../edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs | 98 - .../edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs | 98 - .../edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs | 112 - .../edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs | 112 - .../edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs | 161 - .../tcd/mloffyes_tcd_nbytes_mloffyes.rs | 175 - mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs | 241 - mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs | 622 -- mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs | 35 - mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs | 35 - mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs | 35 - mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs | 35 - mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs | 35 - mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs | 35 - mcxa276-pac/src/eim0.rs | 51 - mcxa276-pac/src/eim0/eichd0_word0.rs | 35 - mcxa276-pac/src/eim0/eichd0_word1.rs | 35 - mcxa276-pac/src/eim0/eichen.rs | 84 - mcxa276-pac/src/eim0/eimcr.rs | 84 - mcxa276-pac/src/eqdc0.rs | 441 -- mcxa276-pac/src/eqdc0/ctrl.rs | 1030 --- mcxa276-pac/src/eqdc0/ctrl2.rs | 567 -- mcxa276-pac/src/eqdc0/filt.rs | 126 - mcxa276-pac/src/eqdc0/imr.rs | 317 - mcxa276-pac/src/eqdc0/intctrl.rs | 1030 --- mcxa276-pac/src/eqdc0/lastedge.rs | 22 - mcxa276-pac/src/eqdc0/lastedgeh.rs | 22 - mcxa276-pac/src/eqdc0/lcomp0.rs | 35 - mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs | 22 - mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs | 22 - mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs | 22 - mcxa276-pac/src/eqdc0/linit.rs | 35 - mcxa276-pac/src/eqdc0/lmod.rs | 35 - mcxa276-pac/src/eqdc0/lpos.rs | 35 - mcxa276-pac/src/eqdc0/lposh.rs | 20 - mcxa276-pac/src/eqdc0/lposh1_lposh1.rs | 20 - mcxa276-pac/src/eqdc0/lposh2_lposh2.rs | 20 - mcxa276-pac/src/eqdc0/lposh3_lposh3.rs | 20 - mcxa276-pac/src/eqdc0/lverid.rs | 22 - mcxa276-pac/src/eqdc0/posd.rs | 35 - mcxa276-pac/src/eqdc0/posdh.rs | 20 - mcxa276-pac/src/eqdc0/posdper.rs | 22 - mcxa276-pac/src/eqdc0/posdperbfr.rs | 22 - mcxa276-pac/src/eqdc0/posdperh.rs | 22 - mcxa276-pac/src/eqdc0/rev.rs | 35 - mcxa276-pac/src/eqdc0/revh.rs | 20 - mcxa276-pac/src/eqdc0/tst.rs | 238 - mcxa276-pac/src/eqdc0/ucomp0.rs | 37 - mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs | 24 - mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs | 24 - mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs | 24 - mcxa276-pac/src/eqdc0/uinit.rs | 35 - mcxa276-pac/src/eqdc0/umod.rs | 35 - mcxa276-pac/src/eqdc0/upos.rs | 35 - mcxa276-pac/src/eqdc0/uposh.rs | 20 - mcxa276-pac/src/eqdc0/uposh1_uposh1.rs | 20 - mcxa276-pac/src/eqdc0/uposh2_uposh2.rs | 20 - mcxa276-pac/src/eqdc0/uposh3_uposh3.rs | 20 - mcxa276-pac/src/eqdc0/uverid.rs | 22 - mcxa276-pac/src/eqdc0/wtr.rs | 35 - mcxa276-pac/src/erm0.rs | 75 - mcxa276-pac/src/erm0/corr_err_cnt0.rs | 35 - mcxa276-pac/src/erm0/corr_err_cnt1.rs | 35 - mcxa276-pac/src/erm0/cr0.rs | 273 - mcxa276-pac/src/erm0/ear0.rs | 20 - mcxa276-pac/src/erm0/sr0.rs | 274 - mcxa276-pac/src/erm0/syn0.rs | 20 - mcxa276-pac/src/flexio0.rs | 556 -- mcxa276-pac/src/flexio0/ctrl.rs | 336 - mcxa276-pac/src/flexio0/param.rs | 43 - mcxa276-pac/src/flexio0/pin.rs | 20 - mcxa276-pac/src/flexio0/pinfen.rs | 35 - mcxa276-pac/src/flexio0/pinien.rs | 35 - mcxa276-pac/src/flexio0/pinoutclr.rs | 35 - mcxa276-pac/src/flexio0/pinoutd.rs | 35 - mcxa276-pac/src/flexio0/pinoutdis.rs | 35 - mcxa276-pac/src/flexio0/pinoute.rs | 35 - mcxa276-pac/src/flexio0/pinoutset.rs | 35 - mcxa276-pac/src/flexio0/pinouttog.rs | 35 - mcxa276-pac/src/flexio0/pinren.rs | 35 - mcxa276-pac/src/flexio0/pinstat.rs | 92 - mcxa276-pac/src/flexio0/shiftbuf.rs | 35 - mcxa276-pac/src/flexio0/shiftbufbbs.rs | 35 - mcxa276-pac/src/flexio0/shiftbufbis.rs | 35 - mcxa276-pac/src/flexio0/shiftbufbys.rs | 35 - mcxa276-pac/src/flexio0/shiftbufeos.rs | 35 - mcxa276-pac/src/flexio0/shiftbufhbs.rs | 35 - mcxa276-pac/src/flexio0/shiftbufhws.rs | 35 - mcxa276-pac/src/flexio0/shiftbufnbs.rs | 35 - mcxa276-pac/src/flexio0/shiftbufnis.rs | 35 - mcxa276-pac/src/flexio0/shiftbufoes.rs | 35 - mcxa276-pac/src/flexio0/shiftcfg.rs | 416 -- mcxa276-pac/src/flexio0/shiftctl.rs | 406 -- mcxa276-pac/src/flexio0/shifteien.rs | 35 - mcxa276-pac/src/flexio0/shifterr.rs | 92 - mcxa276-pac/src/flexio0/shiftsden.rs | 35 - mcxa276-pac/src/flexio0/shiftsien.rs | 35 - mcxa276-pac/src/flexio0/shiftstat.rs | 92 - mcxa276-pac/src/flexio0/shiftstate.rs | 35 - mcxa276-pac/src/flexio0/timcfg.rs | 842 --- mcxa276-pac/src/flexio0/timcmp.rs | 35 - mcxa276-pac/src/flexio0/timctl.rs | 608 -- mcxa276-pac/src/flexio0/timersden.rs | 35 - mcxa276-pac/src/flexio0/timien.rs | 35 - mcxa276-pac/src/flexio0/timstat.rs | 92 - mcxa276-pac/src/flexio0/trgstat.rs | 92 - mcxa276-pac/src/flexio0/trigien.rs | 35 - mcxa276-pac/src/flexio0/verid.rs | 92 - mcxa276-pac/src/flexpwm0.rs | 1303 ---- mcxa276-pac/src/flexpwm0/dtsrcsel.rs | 737 -- mcxa276-pac/src/flexpwm0/fctrl0.rs | 301 - mcxa276-pac/src/flexpwm0/fctrl20.rs | 91 - mcxa276-pac/src/flexpwm0/ffilt0.rs | 112 - mcxa276-pac/src/flexpwm0/fsts0.rs | 238 - mcxa276-pac/src/flexpwm0/ftst0.rs | 84 - mcxa276-pac/src/flexpwm0/mask.rs | 70 - mcxa276-pac/src/flexpwm0/mctrl.rs | 245 - mcxa276-pac/src/flexpwm0/mctrl2.rs | 213 - mcxa276-pac/src/flexpwm0/outen.rs | 63 - mcxa276-pac/src/flexpwm0/sm0captcompx.rs | 42 - mcxa276-pac/src/flexpwm0/sm0captctrlx.rs | 493 -- mcxa276-pac/src/flexpwm0/sm0captfiltx.rs | 49 - mcxa276-pac/src/flexpwm0/sm0cnt.rs | 20 - mcxa276-pac/src/flexpwm0/sm0ctrl.rs | 871 --- mcxa276-pac/src/flexpwm0/sm0ctrl2.rs | 607 -- mcxa276-pac/src/flexpwm0/sm0cval0.rs | 20 - mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm0cval1.rs | 20 - mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm0dismap0.rs | 65 - mcxa276-pac/src/flexpwm0/sm0dmaen.rs | 271 - mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs | 37 - mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs | 37 - mcxa276-pac/src/flexpwm0/sm0init.rs | 35 - mcxa276-pac/src/flexpwm0/sm0inten.rs | 343 - mcxa276-pac/src/flexpwm0/sm0octrl.rs | 519 -- mcxa276-pac/src/flexpwm0/sm0sts.rs | 287 - mcxa276-pac/src/flexpwm0/sm0tctrl.rs | 267 - mcxa276-pac/src/flexpwm0/sm0val0.rs | 35 - mcxa276-pac/src/flexpwm0/sm0val1.rs | 35 - mcxa276-pac/src/flexpwm0/sm0val2.rs | 35 - mcxa276-pac/src/flexpwm0/sm0val3.rs | 35 - mcxa276-pac/src/flexpwm0/sm0val4.rs | 35 - mcxa276-pac/src/flexpwm0/sm0val5.rs | 35 - mcxa276-pac/src/flexpwm0/sm1captcompx.rs | 42 - mcxa276-pac/src/flexpwm0/sm1captctrlx.rs | 493 -- mcxa276-pac/src/flexpwm0/sm1captfiltx.rs | 49 - mcxa276-pac/src/flexpwm0/sm1cnt.rs | 20 - mcxa276-pac/src/flexpwm0/sm1ctrl.rs | 871 --- mcxa276-pac/src/flexpwm0/sm1ctrl2.rs | 607 -- mcxa276-pac/src/flexpwm0/sm1cval0.rs | 20 - mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm1cval1.rs | 20 - mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm1dismap0.rs | 65 - mcxa276-pac/src/flexpwm0/sm1dmaen.rs | 271 - mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs | 37 - mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs | 37 - mcxa276-pac/src/flexpwm0/sm1init.rs | 35 - mcxa276-pac/src/flexpwm0/sm1inten.rs | 343 - mcxa276-pac/src/flexpwm0/sm1octrl.rs | 519 -- mcxa276-pac/src/flexpwm0/sm1phasedly.rs | 35 - mcxa276-pac/src/flexpwm0/sm1sts.rs | 287 - mcxa276-pac/src/flexpwm0/sm1tctrl.rs | 267 - mcxa276-pac/src/flexpwm0/sm1val0.rs | 35 - mcxa276-pac/src/flexpwm0/sm1val1.rs | 35 - mcxa276-pac/src/flexpwm0/sm1val2.rs | 35 - mcxa276-pac/src/flexpwm0/sm1val3.rs | 35 - mcxa276-pac/src/flexpwm0/sm1val4.rs | 35 - mcxa276-pac/src/flexpwm0/sm1val5.rs | 35 - mcxa276-pac/src/flexpwm0/sm2captcompx.rs | 42 - mcxa276-pac/src/flexpwm0/sm2captctrlx.rs | 493 -- mcxa276-pac/src/flexpwm0/sm2captfiltx.rs | 49 - mcxa276-pac/src/flexpwm0/sm2cnt.rs | 20 - mcxa276-pac/src/flexpwm0/sm2ctrl.rs | 871 --- mcxa276-pac/src/flexpwm0/sm2ctrl2.rs | 607 -- mcxa276-pac/src/flexpwm0/sm2cval0.rs | 20 - mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm2cval1.rs | 20 - mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm2dismap0.rs | 65 - mcxa276-pac/src/flexpwm0/sm2dmaen.rs | 271 - mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs | 37 - mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs | 37 - mcxa276-pac/src/flexpwm0/sm2init.rs | 35 - mcxa276-pac/src/flexpwm0/sm2inten.rs | 343 - mcxa276-pac/src/flexpwm0/sm2octrl.rs | 519 -- mcxa276-pac/src/flexpwm0/sm2phasedly.rs | 35 - mcxa276-pac/src/flexpwm0/sm2sts.rs | 287 - mcxa276-pac/src/flexpwm0/sm2tctrl.rs | 267 - mcxa276-pac/src/flexpwm0/sm2val0.rs | 35 - mcxa276-pac/src/flexpwm0/sm2val1.rs | 35 - mcxa276-pac/src/flexpwm0/sm2val2.rs | 35 - mcxa276-pac/src/flexpwm0/sm2val3.rs | 35 - mcxa276-pac/src/flexpwm0/sm2val4.rs | 35 - mcxa276-pac/src/flexpwm0/sm2val5.rs | 35 - mcxa276-pac/src/flexpwm0/sm3captcompx.rs | 42 - mcxa276-pac/src/flexpwm0/sm3captctrlx.rs | 493 -- mcxa276-pac/src/flexpwm0/sm3captfiltx.rs | 49 - mcxa276-pac/src/flexpwm0/sm3cnt.rs | 20 - mcxa276-pac/src/flexpwm0/sm3ctrl.rs | 871 --- mcxa276-pac/src/flexpwm0/sm3ctrl2.rs | 607 -- mcxa276-pac/src/flexpwm0/sm3cval0.rs | 20 - mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm3cval1.rs | 20 - mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs | 20 - mcxa276-pac/src/flexpwm0/sm3dismap0.rs | 65 - mcxa276-pac/src/flexpwm0/sm3dmaen.rs | 271 - mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs | 37 - mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs | 37 - mcxa276-pac/src/flexpwm0/sm3init.rs | 35 - mcxa276-pac/src/flexpwm0/sm3inten.rs | 343 - mcxa276-pac/src/flexpwm0/sm3octrl.rs | 519 -- mcxa276-pac/src/flexpwm0/sm3phasedly.rs | 35 - mcxa276-pac/src/flexpwm0/sm3sts.rs | 287 - mcxa276-pac/src/flexpwm0/sm3tctrl.rs | 267 - mcxa276-pac/src/flexpwm0/sm3val0.rs | 35 - mcxa276-pac/src/flexpwm0/sm3val1.rs | 35 - mcxa276-pac/src/flexpwm0/sm3val2.rs | 35 - mcxa276-pac/src/flexpwm0/sm3val3.rs | 35 - mcxa276-pac/src/flexpwm0/sm3val4.rs | 35 - mcxa276-pac/src/flexpwm0/sm3val5.rs | 35 - mcxa276-pac/src/flexpwm0/swcout.rs | 525 -- mcxa276-pac/src/fmc0.rs | 18 - mcxa276-pac/src/fmc0/remap.rs | 112 - mcxa276-pac/src/fmu0.rs | 57 - mcxa276-pac/src/fmu0/fccob.rs | 35 - mcxa276-pac/src/fmu0/fcnfg.rs | 282 - mcxa276-pac/src/fmu0/fctrl.rs | 226 - mcxa276-pac/src/fmu0/fstat.rs | 713 -- mcxa276-pac/src/freqme0.rs | 60 - mcxa276-pac/src/freqme0/ctrlstat.rs | 505 -- mcxa276-pac/src/freqme0/max.rs | 37 - mcxa276-pac/src/freqme0/min.rs | 35 - mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs | 61 - mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs | 274 - mcxa276-pac/src/generic.rs | 768 --- mcxa276-pac/src/generic/raw.rs | 95 - mcxa276-pac/src/glikey0.rs | 62 - mcxa276-pac/src/glikey0/ctrl_0.rs | 128 - mcxa276-pac/src/glikey0/ctrl_1.rs | 79 - mcxa276-pac/src/glikey0/intr_ctrl.rs | 119 - mcxa276-pac/src/glikey0/status.rs | 198 - mcxa276-pac/src/glikey0/version.rs | 71 - mcxa276-pac/src/gpio0.rs | 175 - mcxa276-pac/src/gpio0/gichr.rs | 1043 --- mcxa276-pac/src/gpio0/giclr.rs | 1043 --- mcxa276-pac/src/gpio0/icr.rs | 311 - mcxa276-pac/src/gpio0/isfr0.rs | 2038 ------ mcxa276-pac/src/gpio0/param.rs | 22 - mcxa276-pac/src/gpio0/pcor.rs | 2037 ------ mcxa276-pac/src/gpio0/pddr.rs | 2037 ------ mcxa276-pac/src/gpio0/pdir.rs | 1325 ---- mcxa276-pac/src/gpio0/pdor.rs | 2037 ------ mcxa276-pac/src/gpio0/pdr.rs | 84 - mcxa276-pac/src/gpio0/pidr.rs | 2037 ------ mcxa276-pac/src/gpio0/psor.rs | 2037 ------ mcxa276-pac/src/gpio0/ptor.rs | 2037 ------ mcxa276-pac/src/gpio0/verid.rs | 76 - mcxa276-pac/src/i3c0.rs | 639 -- mcxa276-pac/src/i3c0/byte_mwdatab1.rs | 22 - mcxa276-pac/src/i3c0/byte_swdatab1.rs | 22 - .../src/i3c0/control2_mwmsg_ddr_control2.rs | 58 - mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs | 22 - mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs | 137 - mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs | 22 - mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs | 22 - mcxa276-pac/src/i3c0/halfword_mwdatah1.rs | 22 - mcxa276-pac/src/i3c0/halfword_swdatah1.rs | 22 - mcxa276-pac/src/i3c0/ibiext1.rs | 86 - mcxa276-pac/src/i3c0/ibiext2.rs | 77 - mcxa276-pac/src/i3c0/mconfig.rs | 472 -- mcxa276-pac/src/i3c0/mconfig_ext.rs | 213 - mcxa276-pac/src/i3c0/mctrl.rs | 426 -- mcxa276-pac/src/i3c0/mdatactrl.rs | 419 -- mcxa276-pac/src/i3c0/mdmactrl.rs | 272 - mcxa276-pac/src/i3c0/mdynaddr.rs | 98 - mcxa276-pac/src/i3c0/merrwarn.rs | 715 -- mcxa276-pac/src/i3c0/mibirules.rs | 217 - mcxa276-pac/src/i3c0/mintclr.rs | 526 -- mcxa276-pac/src/i3c0/mintmasked.rs | 307 - mcxa276-pac/src/i3c0/mintset.rs | 477 -- mcxa276-pac/src/i3c0/mrdatab.rs | 20 - mcxa276-pac/src/i3c0/mrdatah.rs | 27 - mcxa276-pac/src/i3c0/mrmsg_ddr.rs | 20 - mcxa276-pac/src/i3c0/mrmsg_sdr.rs | 20 - mcxa276-pac/src/i3c0/mstatus.rs | 709 -- mcxa276-pac/src/i3c0/mwdatab.rs | 94 - mcxa276-pac/src/i3c0/mwdatabe.rs | 22 - mcxa276-pac/src/i3c0/mwdatah.rs | 65 - mcxa276-pac/src/i3c0/mwdatahe.rs | 29 - mcxa276-pac/src/i3c0/scapabilities.rs | 674 -- mcxa276-pac/src/i3c0/scapabilities2.rs | 413 -- mcxa276-pac/src/i3c0/sconfig.rs | 429 -- mcxa276-pac/src/i3c0/sctrl.rs | 236 - mcxa276-pac/src/i3c0/sdatactrl.rs | 419 -- mcxa276-pac/src/i3c0/sdmactrl.rs | 272 - mcxa276-pac/src/i3c0/sdynaddr.rs | 126 - mcxa276-pac/src/i3c0/serrwarn.rs | 715 -- mcxa276-pac/src/i3c0/sid.rs | 22 - mcxa276-pac/src/i3c0/sidext.rs | 51 - mcxa276-pac/src/i3c0/sidpartno.rs | 37 - mcxa276-pac/src/i3c0/sintclr.rs | 176 - mcxa276-pac/src/i3c0/sintmasked.rs | 90 - mcxa276-pac/src/i3c0/sintset.rs | 715 -- mcxa276-pac/src/i3c0/smapctrl0.rs | 132 - mcxa276-pac/src/i3c0/smaxlimits.rs | 49 - mcxa276-pac/src/i3c0/smsgmapaddr.rs | 75 - mcxa276-pac/src/i3c0/srdatab.rs | 20 - mcxa276-pac/src/i3c0/srdatah.rs | 27 - mcxa276-pac/src/i3c0/sstatus.rs | 1216 ---- mcxa276-pac/src/i3c0/stcclock.rs | 51 - mcxa276-pac/src/i3c0/svendorid.rs | 37 - mcxa276-pac/src/i3c0/swdatab.rs | 94 - mcxa276-pac/src/i3c0/swdatabe.rs | 22 - mcxa276-pac/src/i3c0/swdatah.rs | 65 - mcxa276-pac/src/i3c0/swdatahe.rs | 29 - mcxa276-pac/src/inputmux0.rs | 1012 --- mcxa276-pac/src/inputmux0/adc0_trig.rs | 782 --- mcxa276-pac/src/inputmux0/adc1_trig.rs | 782 --- mcxa276-pac/src/inputmux0/adc2_trig.rs | 782 --- mcxa276-pac/src/inputmux0/adc3_trig.rs | 782 --- mcxa276-pac/src/inputmux0/aoi0_input.rs | 1302 ---- mcxa276-pac/src/inputmux0/aoi1_input.rs | 1302 ---- mcxa276-pac/src/inputmux0/cmp0_trig.rs | 652 -- mcxa276-pac/src/inputmux0/cmp1_trig.rs | 652 -- mcxa276-pac/src/inputmux0/cmp2_trig.rs | 652 -- mcxa276-pac/src/inputmux0/ctimer0cap.rs | 1471 ---- mcxa276-pac/src/inputmux0/ctimer1cap.rs | 1471 ---- mcxa276-pac/src/inputmux0/ctimer2cap.rs | 1471 ---- mcxa276-pac/src/inputmux0/ctimer3cap.rs | 1627 ----- mcxa276-pac/src/inputmux0/ctimer4cap.rs | 1627 ----- mcxa276-pac/src/inputmux0/dac0_trig.rs | 652 -- mcxa276-pac/src/inputmux0/ext_trig.rs | 288 - mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_force.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_force.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs | 808 --- mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs | 808 --- mcxa276-pac/src/inputmux0/flexio_trig.rs | 1094 --- mcxa276-pac/src/inputmux0/freqmeas_ref.rs | 418 -- mcxa276-pac/src/inputmux0/freqmeas_tar.rs | 418 -- mcxa276-pac/src/inputmux0/lpi2c0_trig.rs | 587 -- mcxa276-pac/src/inputmux0/lpi2c1_trig.rs | 587 -- mcxa276-pac/src/inputmux0/lpi2c2_trig.rs | 587 -- mcxa276-pac/src/inputmux0/lpi2c3_trig.rs | 587 -- mcxa276-pac/src/inputmux0/lpspi0_trig.rs | 587 -- mcxa276-pac/src/inputmux0/lpspi1_trig.rs | 587 -- mcxa276-pac/src/inputmux0/lpuart0.rs | 652 -- mcxa276-pac/src/inputmux0/lpuart1.rs | 652 -- mcxa276-pac/src/inputmux0/lpuart2.rs | 652 -- mcxa276-pac/src/inputmux0/lpuart3.rs | 652 -- mcxa276-pac/src/inputmux0/lpuart4.rs | 652 -- mcxa276-pac/src/inputmux0/lpuart5.rs | 652 -- mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs | 171 - mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs | 171 - mcxa276-pac/src/inputmux0/qdc0_home.rs | 782 --- mcxa276-pac/src/inputmux0/qdc0_icap1.rs | 782 --- mcxa276-pac/src/inputmux0/qdc0_icap2.rs | 782 --- mcxa276-pac/src/inputmux0/qdc0_icap3.rs | 782 --- mcxa276-pac/src/inputmux0/qdc0_index.rs | 782 --- mcxa276-pac/src/inputmux0/qdc0_phasea.rs | 756 --- mcxa276-pac/src/inputmux0/qdc0_phaseb.rs | 782 --- mcxa276-pac/src/inputmux0/qdc0_trig.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_home.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_icap1.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_icap2.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_icap3.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_index.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_phasea.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_phaseb.rs | 782 --- mcxa276-pac/src/inputmux0/qdc1_trig.rs | 782 --- mcxa276-pac/src/inputmux0/smart_dma_trig.rs | 1081 --- mcxa276-pac/src/inputmux0/timer0trig.rs | 1471 ---- mcxa276-pac/src/inputmux0/timer1trig.rs | 1471 ---- mcxa276-pac/src/inputmux0/timer2trig.rs | 1471 ---- mcxa276-pac/src/inputmux0/timer3trig.rs | 1627 ----- mcxa276-pac/src/inputmux0/timer4trig.rs | 1627 ----- mcxa276-pac/src/inputmux0/trigfil.rs | 49 - mcxa276-pac/src/inputmux0/trigfil_prsc.rs | 180 - mcxa276-pac/src/inputmux0/trigfil_stat0.rs | 505 -- mcxa276-pac/src/inputmux0/usbfs_trig.rs | 145 - mcxa276-pac/src/lib.rs | 1555 ----- mcxa276-pac/src/lpi2c0.rs | 360 - mcxa276-pac/src/lpi2c0/mccr0.rs | 77 - mcxa276-pac/src/lpi2c0/mccr1.rs | 77 - mcxa276-pac/src/lpi2c0/mcfgr0.rs | 525 -- mcxa276-pac/src/lpi2c0/mcfgr1.rs | 767 --- mcxa276-pac/src/lpi2c0/mcfgr2.rs | 63 - mcxa276-pac/src/lpi2c0/mcfgr3.rs | 35 - mcxa276-pac/src/lpi2c0/mcr.rs | 399 -- mcxa276-pac/src/lpi2c0/mder.rs | 147 - mcxa276-pac/src/lpi2c0/mdmr.rs | 49 - mcxa276-pac/src/lpi2c0/mfcr.rs | 49 - mcxa276-pac/src/lpi2c0/mfsr.rs | 27 - mcxa276-pac/src/lpi2c0/mier.rs | 651 -- mcxa276-pac/src/lpi2c0/mrdr.rs | 63 - mcxa276-pac/src/lpi2c0/mrdror.rs | 63 - mcxa276-pac/src/lpi2c0/msr.rs | 692 -- mcxa276-pac/src/lpi2c0/mtdr.rs | 114 - mcxa276-pac/src/lpi2c0/param.rs | 29 - mcxa276-pac/src/lpi2c0/samr.rs | 49 - mcxa276-pac/src/lpi2c0/sasr.rs | 63 - mcxa276-pac/src/lpi2c0/scfgr0.rs | 125 - mcxa276-pac/src/lpi2c0/scfgr1.rs | 1057 --- mcxa276-pac/src/lpi2c0/scfgr2.rs | 77 - mcxa276-pac/src/lpi2c0/scr.rs | 399 -- mcxa276-pac/src/lpi2c0/sder.rs | 336 - mcxa276-pac/src/lpi2c0/sier.rs | 777 --- mcxa276-pac/src/lpi2c0/srdr.rs | 111 - mcxa276-pac/src/lpi2c0/srdror.rs | 111 - mcxa276-pac/src/lpi2c0/ssr.rs | 684 -- mcxa276-pac/src/lpi2c0/star.rs | 84 - mcxa276-pac/src/lpi2c0/stdr.rs | 22 - mcxa276-pac/src/lpi2c0/verid.rs | 76 - mcxa276-pac/src/lpspi0.rs | 266 - mcxa276-pac/src/lpspi0/ccr.rs | 77 - mcxa276-pac/src/lpspi0/ccr1.rs | 77 - mcxa276-pac/src/lpspi0/cfgr0.rs | 399 -- mcxa276-pac/src/lpspi0/cfgr1.rs | 763 --- mcxa276-pac/src/lpspi0/cr.rs | 282 - mcxa276-pac/src/lpspi0/der.rs | 210 - mcxa276-pac/src/lpspi0/dmr0.rs | 35 - mcxa276-pac/src/lpspi0/dmr1.rs | 35 - mcxa276-pac/src/lpspi0/fcr.rs | 49 - mcxa276-pac/src/lpspi0/fsr.rs | 27 - mcxa276-pac/src/lpspi0/ier.rs | 525 -- mcxa276-pac/src/lpspi0/param.rs | 36 - mcxa276-pac/src/lpspi0/rdbr.rs | 20 - mcxa276-pac/src/lpspi0/rdr.rs | 20 - mcxa276-pac/src/lpspi0/rdror.rs | 20 - mcxa276-pac/src/lpspi0/rsr.rs | 97 - mcxa276-pac/src/lpspi0/sr.rs | 525 -- mcxa276-pac/src/lpspi0/tcbr.rs | 22 - mcxa276-pac/src/lpspi0/tcr.rs | 868 --- mcxa276-pac/src/lpspi0/tdbr.rs | 22 - mcxa276-pac/src/lpspi0/tdr.rs | 22 - mcxa276-pac/src/lpspi0/verid.rs | 68 - mcxa276-pac/src/lptmr0.rs | 50 - mcxa276-pac/src/lptmr0/cmr.rs | 35 - mcxa276-pac/src/lptmr0/cnr.rs | 35 - mcxa276-pac/src/lptmr0/csr.rs | 559 -- mcxa276-pac/src/lptmr0/psr.rs | 432 -- mcxa276-pac/src/lpuart0.rs | 149 - mcxa276-pac/src/lpuart0/baud.rs | 1260 ---- mcxa276-pac/src/lpuart0/ctrl.rs | 1835 ----- mcxa276-pac/src/lpuart0/data.rs | 431 -- mcxa276-pac/src/lpuart0/dataro.rs | 22 - mcxa276-pac/src/lpuart0/fifo.rs | 948 --- mcxa276-pac/src/lpuart0/global.rs | 84 - mcxa276-pac/src/lpuart0/match_.rs | 49 - mcxa276-pac/src/lpuart0/modir.rs | 572 -- mcxa276-pac/src/lpuart0/param.rs | 29 - mcxa276-pac/src/lpuart0/pincfg.rs | 117 - mcxa276-pac/src/lpuart0/stat.rs | 1196 ---- mcxa276-pac/src/lpuart0/verid.rs | 76 - mcxa276-pac/src/lpuart0/water.rs | 63 - mcxa276-pac/src/mau0.rs | 119 - mcxa276-pac/src/mau0/gexp_status.rs | 84 - mcxa276-pac/src/mau0/gexp_status_ie.rs | 84 - mcxa276-pac/src/mau0/op_ctrl.rs | 657 -- mcxa276-pac/src/mau0/res0.rs | 35 - mcxa276-pac/src/mau0/res1.rs | 35 - mcxa276-pac/src/mau0/res2.rs | 35 - mcxa276-pac/src/mau0/res3.rs | 35 - mcxa276-pac/src/mau0/res_status.rs | 2037 ------ mcxa276-pac/src/mau0/res_status_ie.rs | 273 - mcxa276-pac/src/mau0/sys_ctlr.rs | 86 - mcxa276-pac/src/mbc0.rs | 350 - mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs | 1709 ----- mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs | 29 - mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs | 29 - mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs | 29 - mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs | 49 - mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs | 779 --- mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs | 842 --- mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs | 842 --- mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs | 842 --- mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs | 842 --- mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs | 842 --- mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs | 842 --- mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs | 842 --- mcxa276-pac/src/mrcc0.rs | 986 --- mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs | 175 - mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs | 104 - mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs | 119 - mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs | 119 - mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs | 2039 ------ mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs | 1848 ----- mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs | 653 -- mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs | 2039 ------ mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs | 24 - mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs | 24 - mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs | 1911 ------ mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs | 651 -- mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs | 1911 ------ mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs | 1659 ----- mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs | 399 -- mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs | 22 - mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs | 132 - mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs | 145 - mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs | 93 - mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs | 106 - mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs | 177 - mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs | 106 - mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs | 175 - mcxa276-pac/src/opamp0.rs | 39 - mcxa276-pac/src/opamp0/opamp_ctrl.rs | 276 - mcxa276-pac/src/opamp0/param.rs | 16 - mcxa276-pac/src/opamp0/verid.rs | 34 - mcxa276-pac/src/ostimer0.rs | 84 - mcxa276-pac/src/ostimer0/capture_h.rs | 20 - mcxa276-pac/src/ostimer0/capture_l.rs | 20 - mcxa276-pac/src/ostimer0/evtimerh.rs | 20 - mcxa276-pac/src/ostimer0/evtimerl.rs | 20 - mcxa276-pac/src/ostimer0/match_h.rs | 37 - mcxa276-pac/src/ostimer0/match_l.rs | 37 - mcxa276-pac/src/ostimer0/osevent_ctrl.rs | 171 - mcxa276-pac/src/pkc0.rs | 300 - mcxa276-pac/src/pkc0/pkc_access_err.rs | 69 - mcxa276-pac/src/pkc0/pkc_access_err_clr.rs | 22 - mcxa276-pac/src/pkc0/pkc_cfg.rs | 149 - mcxa276-pac/src/pkc0/pkc_ctrl.rs | 191 - mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs | 22 - mcxa276-pac/src/pkc0/pkc_int_clr_status.rs | 22 - mcxa276-pac/src/pkc0/pkc_int_enable.rs | 20 - mcxa276-pac/src/pkc0/pkc_int_set_enable.rs | 22 - mcxa276-pac/src/pkc0/pkc_int_set_status.rs | 22 - mcxa276-pac/src/pkc0/pkc_int_status.rs | 20 - mcxa276-pac/src/pkc0/pkc_len1.rs | 49 - mcxa276-pac/src/pkc0/pkc_len2.rs | 49 - mcxa276-pac/src/pkc0/pkc_mcdata.rs | 35 - mcxa276-pac/src/pkc0/pkc_mode1.rs | 35 - mcxa276-pac/src/pkc0/pkc_mode2.rs | 35 - mcxa276-pac/src/pkc0/pkc_module_id.rs | 43 - mcxa276-pac/src/pkc0/pkc_soft_rst.rs | 22 - mcxa276-pac/src/pkc0/pkc_status.rs | 48 - mcxa276-pac/src/pkc0/pkc_ulen.rs | 35 - mcxa276-pac/src/pkc0/pkc_uptr.rs | 35 - mcxa276-pac/src/pkc0/pkc_uptrt.rs | 35 - mcxa276-pac/src/pkc0/pkc_version.rs | 124 - mcxa276-pac/src/pkc0/pkc_xyptr1.rs | 49 - mcxa276-pac/src/pkc0/pkc_xyptr2.rs | 49 - mcxa276-pac/src/pkc0/pkc_zrptr1.rs | 49 - mcxa276-pac/src/pkc0/pkc_zrptr2.rs | 49 - mcxa276-pac/src/port0.rs | 428 -- mcxa276-pac/src/port0/calib0.rs | 49 - mcxa276-pac/src/port0/calib1.rs | 49 - mcxa276-pac/src/port0/config.rs | 84 - mcxa276-pac/src/port0/gpchr.rs | 1043 --- mcxa276-pac/src/port0/gpclr.rs | 1043 --- mcxa276-pac/src/port0/pcr0.rs | 675 -- mcxa276-pac/src/port0/pcr1.rs | 675 -- mcxa276-pac/src/port0/pcr10.rs | 525 -- mcxa276-pac/src/port0/pcr11.rs | 525 -- mcxa276-pac/src/port0/pcr12.rs | 751 -- mcxa276-pac/src/port0/pcr13.rs | 751 -- mcxa276-pac/src/port0/pcr14.rs | 751 -- mcxa276-pac/src/port0/pcr15.rs | 751 -- mcxa276-pac/src/port0/pcr16.rs | 940 --- mcxa276-pac/src/port0/pcr17.rs | 877 --- mcxa276-pac/src/port0/pcr18.rs | 751 -- mcxa276-pac/src/port0/pcr19.rs | 751 -- mcxa276-pac/src/port0/pcr2.rs | 753 -- mcxa276-pac/src/port0/pcr20.rs | 751 -- mcxa276-pac/src/port0/pcr21.rs | 751 -- mcxa276-pac/src/port0/pcr22.rs | 751 -- mcxa276-pac/src/port0/pcr23.rs | 751 -- mcxa276-pac/src/port0/pcr24.rs | 751 -- mcxa276-pac/src/port0/pcr25.rs | 751 -- mcxa276-pac/src/port0/pcr26.rs | 751 -- mcxa276-pac/src/port0/pcr27.rs | 751 -- mcxa276-pac/src/port0/pcr28.rs | 525 -- mcxa276-pac/src/port0/pcr29.rs | 525 -- mcxa276-pac/src/port0/pcr3.rs | 753 -- mcxa276-pac/src/port0/pcr30.rs | 525 -- mcxa276-pac/src/port0/pcr31.rs | 525 -- mcxa276-pac/src/port0/pcr4.rs | 751 -- mcxa276-pac/src/port0/pcr5.rs | 751 -- mcxa276-pac/src/port0/pcr6.rs | 753 -- mcxa276-pac/src/port0/pcr7.rs | 673 -- mcxa276-pac/src/port0/pcr8.rs | 525 -- mcxa276-pac/src/port0/pcr9.rs | 525 -- mcxa276-pac/src/port0/verid.rs | 68 - mcxa276-pac/src/port1.rs | 428 -- mcxa276-pac/src/port1/calib0.rs | 49 - mcxa276-pac/src/port1/calib1.rs | 49 - mcxa276-pac/src/port1/config.rs | 84 - mcxa276-pac/src/port1/gpchr.rs | 1043 --- mcxa276-pac/src/port1/gpclr.rs | 1043 --- mcxa276-pac/src/port1/pcr0.rs | 814 --- mcxa276-pac/src/port1/pcr1.rs | 814 --- mcxa276-pac/src/port1/pcr10.rs | 751 -- mcxa276-pac/src/port1/pcr11.rs | 751 -- mcxa276-pac/src/port1/pcr12.rs | 751 -- mcxa276-pac/src/port1/pcr13.rs | 751 -- mcxa276-pac/src/port1/pcr14.rs | 751 -- mcxa276-pac/src/port1/pcr15.rs | 751 -- mcxa276-pac/src/port1/pcr16.rs | 751 -- mcxa276-pac/src/port1/pcr17.rs | 751 -- mcxa276-pac/src/port1/pcr18.rs | 751 -- mcxa276-pac/src/port1/pcr19.rs | 751 -- mcxa276-pac/src/port1/pcr2.rs | 751 -- mcxa276-pac/src/port1/pcr20.rs | 525 -- mcxa276-pac/src/port1/pcr21.rs | 525 -- mcxa276-pac/src/port1/pcr22.rs | 525 -- mcxa276-pac/src/port1/pcr23.rs | 525 -- mcxa276-pac/src/port1/pcr24.rs | 525 -- mcxa276-pac/src/port1/pcr25.rs | 525 -- mcxa276-pac/src/port1/pcr26.rs | 525 -- mcxa276-pac/src/port1/pcr27.rs | 525 -- mcxa276-pac/src/port1/pcr28.rs | 525 -- mcxa276-pac/src/port1/pcr29.rs | 749 -- mcxa276-pac/src/port1/pcr3.rs | 751 -- mcxa276-pac/src/port1/pcr30.rs | 940 --- mcxa276-pac/src/port1/pcr31.rs | 877 --- mcxa276-pac/src/port1/pcr4.rs | 751 -- mcxa276-pac/src/port1/pcr5.rs | 751 -- mcxa276-pac/src/port1/pcr6.rs | 751 -- mcxa276-pac/src/port1/pcr7.rs | 751 -- mcxa276-pac/src/port1/pcr8.rs | 940 --- mcxa276-pac/src/port1/pcr9.rs | 877 --- mcxa276-pac/src/port1/verid.rs | 68 - mcxa276-pac/src/port2.rs | 405 -- mcxa276-pac/src/port2/config.rs | 84 - mcxa276-pac/src/port2/gpchr.rs | 1043 --- mcxa276-pac/src/port2/gpclr.rs | 1043 --- mcxa276-pac/src/port2/pcr0.rs | 751 -- mcxa276-pac/src/port2/pcr1.rs | 751 -- mcxa276-pac/src/port2/pcr10.rs | 673 -- mcxa276-pac/src/port2/pcr11.rs | 673 -- mcxa276-pac/src/port2/pcr12.rs | 751 -- mcxa276-pac/src/port2/pcr13.rs | 751 -- mcxa276-pac/src/port2/pcr14.rs | 673 -- mcxa276-pac/src/port2/pcr15.rs | 751 -- mcxa276-pac/src/port2/pcr16.rs | 751 -- mcxa276-pac/src/port2/pcr17.rs | 673 -- mcxa276-pac/src/port2/pcr18.rs | 673 -- mcxa276-pac/src/port2/pcr19.rs | 673 -- mcxa276-pac/src/port2/pcr2.rs | 673 -- mcxa276-pac/src/port2/pcr20.rs | 673 -- mcxa276-pac/src/port2/pcr21.rs | 673 -- mcxa276-pac/src/port2/pcr22.rs | 673 -- mcxa276-pac/src/port2/pcr23.rs | 673 -- mcxa276-pac/src/port2/pcr24.rs | 673 -- mcxa276-pac/src/port2/pcr25.rs | 673 -- mcxa276-pac/src/port2/pcr26.rs | 673 -- mcxa276-pac/src/port2/pcr27.rs | 525 -- mcxa276-pac/src/port2/pcr28.rs | 525 -- mcxa276-pac/src/port2/pcr29.rs | 525 -- mcxa276-pac/src/port2/pcr3.rs | 751 -- mcxa276-pac/src/port2/pcr30.rs | 525 -- mcxa276-pac/src/port2/pcr31.rs | 525 -- mcxa276-pac/src/port2/pcr4.rs | 673 -- mcxa276-pac/src/port2/pcr5.rs | 673 -- mcxa276-pac/src/port2/pcr6.rs | 673 -- mcxa276-pac/src/port2/pcr7.rs | 751 -- mcxa276-pac/src/port2/pcr8.rs | 673 -- mcxa276-pac/src/port2/pcr9.rs | 673 -- mcxa276-pac/src/port2/verid.rs | 68 - mcxa276-pac/src/port3.rs | 428 -- mcxa276-pac/src/port3/calib0.rs | 49 - mcxa276-pac/src/port3/calib1.rs | 49 - mcxa276-pac/src/port3/config.rs | 84 - mcxa276-pac/src/port3/gpchr.rs | 1043 --- mcxa276-pac/src/port3/gpclr.rs | 1043 --- mcxa276-pac/src/port3/pcr0.rs | 877 --- mcxa276-pac/src/port3/pcr1.rs | 877 --- mcxa276-pac/src/port3/pcr10.rs | 751 -- mcxa276-pac/src/port3/pcr11.rs | 751 -- mcxa276-pac/src/port3/pcr12.rs | 751 -- mcxa276-pac/src/port3/pcr13.rs | 751 -- mcxa276-pac/src/port3/pcr14.rs | 751 -- mcxa276-pac/src/port3/pcr15.rs | 751 -- mcxa276-pac/src/port3/pcr16.rs | 751 -- mcxa276-pac/src/port3/pcr17.rs | 751 -- mcxa276-pac/src/port3/pcr18.rs | 814 --- mcxa276-pac/src/port3/pcr19.rs | 814 --- mcxa276-pac/src/port3/pcr2.rs | 751 -- mcxa276-pac/src/port3/pcr20.rs | 751 -- mcxa276-pac/src/port3/pcr21.rs | 751 -- mcxa276-pac/src/port3/pcr22.rs | 751 -- mcxa276-pac/src/port3/pcr23.rs | 751 -- mcxa276-pac/src/port3/pcr24.rs | 751 -- mcxa276-pac/src/port3/pcr25.rs | 814 --- mcxa276-pac/src/port3/pcr26.rs | 814 --- mcxa276-pac/src/port3/pcr27.rs | 814 --- mcxa276-pac/src/port3/pcr28.rs | 814 --- mcxa276-pac/src/port3/pcr29.rs | 816 --- mcxa276-pac/src/port3/pcr3.rs | 751 -- mcxa276-pac/src/port3/pcr30.rs | 751 -- mcxa276-pac/src/port3/pcr31.rs | 814 --- mcxa276-pac/src/port3/pcr4.rs | 751 -- mcxa276-pac/src/port3/pcr5.rs | 751 -- mcxa276-pac/src/port3/pcr6.rs | 751 -- mcxa276-pac/src/port3/pcr7.rs | 751 -- mcxa276-pac/src/port3/pcr8.rs | 751 -- mcxa276-pac/src/port3/pcr9.rs | 751 -- mcxa276-pac/src/port3/verid.rs | 68 - mcxa276-pac/src/port4.rs | 428 -- mcxa276-pac/src/port4/calib0.rs | 49 - mcxa276-pac/src/port4/calib1.rs | 49 - mcxa276-pac/src/port4/config.rs | 84 - mcxa276-pac/src/port4/gpchr.rs | 1043 --- mcxa276-pac/src/port4/gpclr.rs | 1043 --- mcxa276-pac/src/port4/pcr0.rs | 673 -- mcxa276-pac/src/port4/pcr1.rs | 673 -- mcxa276-pac/src/port4/pcr10.rs | 525 -- mcxa276-pac/src/port4/pcr11.rs | 525 -- mcxa276-pac/src/port4/pcr12.rs | 525 -- mcxa276-pac/src/port4/pcr13.rs | 525 -- mcxa276-pac/src/port4/pcr14.rs | 525 -- mcxa276-pac/src/port4/pcr15.rs | 525 -- mcxa276-pac/src/port4/pcr16.rs | 525 -- mcxa276-pac/src/port4/pcr17.rs | 525 -- mcxa276-pac/src/port4/pcr18.rs | 525 -- mcxa276-pac/src/port4/pcr19.rs | 525 -- mcxa276-pac/src/port4/pcr2.rs | 673 -- mcxa276-pac/src/port4/pcr20.rs | 525 -- mcxa276-pac/src/port4/pcr21.rs | 525 -- mcxa276-pac/src/port4/pcr22.rs | 525 -- mcxa276-pac/src/port4/pcr23.rs | 525 -- mcxa276-pac/src/port4/pcr24.rs | 525 -- mcxa276-pac/src/port4/pcr25.rs | 525 -- mcxa276-pac/src/port4/pcr26.rs | 525 -- mcxa276-pac/src/port4/pcr27.rs | 525 -- mcxa276-pac/src/port4/pcr28.rs | 525 -- mcxa276-pac/src/port4/pcr29.rs | 525 -- mcxa276-pac/src/port4/pcr3.rs | 673 -- mcxa276-pac/src/port4/pcr30.rs | 525 -- mcxa276-pac/src/port4/pcr31.rs | 525 -- mcxa276-pac/src/port4/pcr4.rs | 673 -- mcxa276-pac/src/port4/pcr5.rs | 673 -- mcxa276-pac/src/port4/pcr6.rs | 673 -- mcxa276-pac/src/port4/pcr7.rs | 673 -- mcxa276-pac/src/port4/pcr8.rs | 525 -- mcxa276-pac/src/port4/pcr9.rs | 525 -- mcxa276-pac/src/port4/verid.rs | 68 - mcxa276-pac/src/rtc0.rs | 94 - mcxa276-pac/src/rtc0/cr.rs | 212 - mcxa276-pac/src/rtc0/ier.rs | 423 -- mcxa276-pac/src/rtc0/lr.rs | 275 - mcxa276-pac/src/rtc0/sr.rs | 209 - mcxa276-pac/src/rtc0/tar.rs | 35 - mcxa276-pac/src/rtc0/tcr.rs | 184 - mcxa276-pac/src/rtc0/tpr.rs | 35 - mcxa276-pac/src/rtc0/tsr.rs | 35 - mcxa276-pac/src/sau.rs | 84 - mcxa276-pac/src/sau/ctrl.rs | 147 - mcxa276-pac/src/sau/rbar.rs | 35 - mcxa276-pac/src/sau/rlar.rs | 161 - mcxa276-pac/src/sau/rnr.rs | 35 - mcxa276-pac/src/sau/sfar.rs | 35 - mcxa276-pac/src/sau/sfsr.rs | 525 -- mcxa276-pac/src/sau/type_.rs | 35 - mcxa276-pac/src/scg0.rs | 305 - mcxa276-pac/src/scg0/csr.rs | 86 - mcxa276-pac/src/scg0/firccfg.rs | 119 - mcxa276-pac/src/scg0/firccsr.rs | 651 -- mcxa276-pac/src/scg0/firctrim.rs | 77 - mcxa276-pac/src/scg0/ldocsr.rs | 338 - mcxa276-pac/src/scg0/param.rs | 220 - mcxa276-pac/src/scg0/rccr.rs | 132 - mcxa276-pac/src/scg0/rosccsr.rs | 230 - mcxa276-pac/src/scg0/sirccsr.rs | 651 -- mcxa276-pac/src/scg0/sircstat.rs | 49 - mcxa276-pac/src/scg0/sirctcfg.rs | 92 - mcxa276-pac/src/scg0/sirctrim.rs | 77 - mcxa276-pac/src/scg0/sosccfg.rs | 180 - mcxa276-pac/src/scg0/sosccsr.rs | 608 -- mcxa276-pac/src/scg0/spllcsr.rs | 671 -- mcxa276-pac/src/scg0/spllctrl.rs | 537 -- mcxa276-pac/src/scg0/splllock_cnfg.rs | 37 - mcxa276-pac/src/scg0/spllmdiv.rs | 100 - mcxa276-pac/src/scg0/spllndiv.rs | 100 - mcxa276-pac/src/scg0/spllpdiv.rs | 100 - mcxa276-pac/src/scg0/spllsscg0.rs | 35 - mcxa276-pac/src/scg0/spllsscg1.rs | 331 - mcxa276-pac/src/scg0/spllsscgstat.rs | 54 - mcxa276-pac/src/scg0/spllstat.rs | 177 - mcxa276-pac/src/scg0/trim_lock.rs | 161 - mcxa276-pac/src/scg0/verid.rs | 20 - mcxa276-pac/src/scn_scb.rs | 18 - mcxa276-pac/src/scn_scb/cppwr.rs | 1183 ---- mcxa276-pac/src/sgi0.rs | 863 --- mcxa276-pac/src/sgi0/sgi_access_err.rs | 77 - mcxa276-pac/src/sgi0/sgi_access_err_clr.rs | 42 - mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs | 63 - mcxa276-pac/src/sgi0/sgi_auto_mode.rs | 199 - mcxa276-pac/src/sgi0/sgi_config.rs | 188 - mcxa276-pac/src/sgi0/sgi_config2.rs | 62 - mcxa276-pac/src/sgi0/sgi_count.rs | 42 - mcxa276-pac/src/sgi0/sgi_ctrl.rs | 231 - mcxa276-pac/src/sgi0/sgi_ctrl2.rs | 231 - mcxa276-pac/src/sgi0/sgi_datin0a.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin0b.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin0c.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin0d.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin1a.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin1b.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin1c.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin1d.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin2a.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin2b.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin2c.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin2d.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin3a.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin3b.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin3c.rs | 35 - mcxa276-pac/src/sgi0/sgi_datin3d.rs | 35 - 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mcxa276-pac/src/sgi0/sgi_key3c.rs | 35 - mcxa276-pac/src/sgi0/sgi_key3d.rs | 35 - mcxa276-pac/src/sgi0/sgi_key4a.rs | 35 - mcxa276-pac/src/sgi0/sgi_key4b.rs | 35 - mcxa276-pac/src/sgi0/sgi_key4c.rs | 35 - mcxa276-pac/src/sgi0/sgi_key4d.rs | 35 - mcxa276-pac/src/sgi0/sgi_key5a.rs | 35 - mcxa276-pac/src/sgi0/sgi_key5b.rs | 35 - mcxa276-pac/src/sgi0/sgi_key5c.rs | 35 - mcxa276-pac/src/sgi0/sgi_key5d.rs | 35 - mcxa276-pac/src/sgi0/sgi_key6a.rs | 35 - mcxa276-pac/src/sgi0/sgi_key6b.rs | 35 - mcxa276-pac/src/sgi0/sgi_key6c.rs | 35 - mcxa276-pac/src/sgi0/sgi_key6d.rs | 35 - mcxa276-pac/src/sgi0/sgi_key7a.rs | 35 - mcxa276-pac/src/sgi0/sgi_key7b.rs | 35 - mcxa276-pac/src/sgi0/sgi_key7c.rs | 35 - mcxa276-pac/src/sgi0/sgi_key7d.rs | 35 - mcxa276-pac/src/sgi0/sgi_key_ctrl.rs | 35 - mcxa276-pac/src/sgi0/sgi_key_wrap.rs | 20 - mcxa276-pac/src/sgi0/sgi_keychk.rs | 35 - mcxa276-pac/src/sgi0/sgi_module_id.rs | 20 - mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs | 35 - mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs | 35 - mcxa276-pac/src/sgi0/sgi_sfrseed.rs | 35 - mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs | 149 - mcxa276-pac/src/sgi0/sgi_sha_fifo.rs | 35 - mcxa276-pac/src/sgi0/sgi_status.rs | 203 - mcxa276-pac/src/sgi0/sgi_version.rs | 55 - mcxa276-pac/src/slcd0.rs | 111 - mcxa276-pac/src/slcd0/lcd_ar.rs | 351 - mcxa276-pac/src/slcd0/lcd_bpen0.rs | 2037 ------ mcxa276-pac/src/slcd0/lcd_bpen1.rs | 1029 --- mcxa276-pac/src/slcd0/lcd_fdcr.rs | 457 -- mcxa276-pac/src/slcd0/lcd_fdsr.rs | 92 - mcxa276-pac/src/slcd0/lcd_gcr.rs | 616 -- mcxa276-pac/src/slcd0/lcd_pen0.rs | 2037 ------ mcxa276-pac/src/slcd0/lcd_pen1.rs | 1029 --- mcxa276-pac/src/slcd0/lcd_wfto.rs | 77 - mcxa276-pac/src/smartdma0.rs | 128 - mcxa276-pac/src/smartdma0/arm2ezh.rs | 49 - mcxa276-pac/src/smartdma0/bootadr.rs | 35 - mcxa276-pac/src/smartdma0/break_addr.rs | 35 - mcxa276-pac/src/smartdma0/break_vect.rs | 35 - mcxa276-pac/src/smartdma0/ctrl.rs | 105 - mcxa276-pac/src/smartdma0/emer_sel.rs | 49 - mcxa276-pac/src/smartdma0/emer_vect.rs | 35 - mcxa276-pac/src/smartdma0/ezh2arm.rs | 35 - mcxa276-pac/src/smartdma0/pc.rs | 20 - mcxa276-pac/src/smartdma0/pendtrap.rs | 63 - mcxa276-pac/src/smartdma0/sp.rs | 20 - mcxa276-pac/src/spc0.rs | 214 - mcxa276-pac/src/spc0/active_cfg.rs | 504 -- mcxa276-pac/src/spc0/active_cfg1.rs | 37 - mcxa276-pac/src/spc0/active_vdelay.rs | 37 - mcxa276-pac/src/spc0/coreldo_cfg.rs | 16 - mcxa276-pac/src/spc0/evd_cfg.rs | 56 - mcxa276-pac/src/spc0/lp_cfg.rs | 567 -- mcxa276-pac/src/spc0/lp_cfg1.rs | 37 - mcxa276-pac/src/spc0/lpreq_cfg.rs | 230 - mcxa276-pac/src/spc0/lpwkup_delay.rs | 35 - mcxa276-pac/src/spc0/pd_status0.rs | 189 - mcxa276-pac/src/spc0/sc.rs | 203 - mcxa276-pac/src/spc0/sramctl.rs | 197 - mcxa276-pac/src/spc0/sramretldo_cntrl.rs | 100 - mcxa276-pac/src/spc0/sramretldo_reftrim.rs | 37 - mcxa276-pac/src/spc0/vd_core_cfg.rs | 212 - mcxa276-pac/src/spc0/vd_stat.rs | 211 - mcxa276-pac/src/spc0/vd_sys_cfg.rs | 338 - mcxa276-pac/src/spc0/verid.rs | 66 - mcxa276-pac/src/syscon.rs | 497 -- mcxa276-pac/src/syscon/ahbclkdiv.rs | 76 - mcxa276-pac/src/syscon/ahbmatprio.rs | 695 -- mcxa276-pac/src/syscon/binary_code_lsb.rs | 20 - mcxa276-pac/src/syscon/binary_code_msb.rs | 20 - mcxa276-pac/src/syscon/busclkdiv.rs | 197 - mcxa276-pac/src/syscon/clkunlock.rs | 84 - mcxa276-pac/src/syscon/cpu0nstckcal.rs | 161 - mcxa276-pac/src/syscon/cpustat.rs | 95 - mcxa276-pac/src/syscon/ctimerglobalstarten.rs | 336 - mcxa276-pac/src/syscon/debug_auth_beacon.rs | 35 - mcxa276-pac/src/syscon/debug_features.rs | 161 - mcxa276-pac/src/syscon/debug_features_dp.rs | 161 - mcxa276-pac/src/syscon/debug_lock_en.rs | 93 - mcxa276-pac/src/syscon/device_id0.rs | 297 - mcxa276-pac/src/syscon/device_type.rs | 157 - mcxa276-pac/src/syscon/dieid.rs | 36 - mcxa276-pac/src/syscon/els_otp_lc_state.rs | 20 - mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs | 20 - mcxa276-pac/src/syscon/els_udf.rs | 231 - mcxa276-pac/src/syscon/els_uid.rs | 35 - mcxa276-pac/src/syscon/frohfdiv.rs | 204 - mcxa276-pac/src/syscon/frolfdiv.rs | 204 - mcxa276-pac/src/syscon/gray_code_lsb.rs | 35 - mcxa276-pac/src/syscon/gray_code_msb.rs | 35 - mcxa276-pac/src/syscon/jtag_id.rs | 22 - mcxa276-pac/src/syscon/lpcac_ctrl.rs | 464 -- mcxa276-pac/src/syscon/msfcfg.rs | 336 - mcxa276-pac/src/syscon/nmisrc.rs | 98 - mcxa276-pac/src/syscon/nvm_ctrl.rs | 338 - mcxa276-pac/src/syscon/pll1clkdiv.rs | 204 - mcxa276-pac/src/syscon/protlvl.rs | 210 - mcxa276-pac/src/syscon/pwm0subctl.rs | 273 - mcxa276-pac/src/syscon/pwm1subctl.rs | 273 - mcxa276-pac/src/syscon/ram_ctrl.rs | 338 - mcxa276-pac/src/syscon/ram_interleave.rs | 84 - mcxa276-pac/src/syscon/remap.rs | 504 -- mcxa276-pac/src/syscon/rop_state.rs | 20 - mcxa276-pac/src/syscon/slowclkdiv.rs | 197 - mcxa276-pac/src/syscon/smart_dmaint.rs | 1533 ----- mcxa276-pac/src/syscon/sram_xen.rs | 462 -- mcxa276-pac/src/syscon/sram_xen_dp.rs | 105 - mcxa276-pac/src/syscon/swd_access_cpu0.rs | 91 - mcxa276-pac/src/tdet0.rs | 103 - mcxa276-pac/src/tdet0/cr.rs | 350 - mcxa276-pac/src/tdet0/ier.rs | 1155 ---- mcxa276-pac/src/tdet0/lr.rs | 842 --- mcxa276-pac/src/tdet0/pgfr.rs | 668 -- mcxa276-pac/src/tdet0/ppr.rs | 645 -- mcxa276-pac/src/tdet0/sr.rs | 1219 ---- mcxa276-pac/src/tdet0/ter.rs | 1092 --- mcxa276-pac/src/tdet0/tsr.rs | 35 - mcxa276-pac/src/trng0.rs | 492 -- mcxa276-pac/src/trng0/csclr.rs | 159 - mcxa276-pac/src/trng0/cser.rs | 177 - mcxa276-pac/src/trng0/ent0.rs | 20 - mcxa276-pac/src/trng0/frqcnt_frqcnt.rs | 20 - mcxa276-pac/src/trng0/frqmax_frqmax.rs | 37 - mcxa276-pac/src/trng0/frqmin_frqmin.rs | 37 - mcxa276-pac/src/trng0/int_ctrl.rs | 275 - mcxa276-pac/src/trng0/int_mask.rs | 273 - mcxa276-pac/src/trng0/int_status.rs | 177 - mcxa276-pac/src/trng0/mctl.rs | 515 -- mcxa276-pac/src/trng0/osc2_ctl.rs | 478 -- mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs | 20 - mcxa276-pac/src/trng0/pkrcnt10.rs | 27 - mcxa276-pac/src/trng0/pkrcnt32.rs | 27 - mcxa276-pac/src/trng0/pkrcnt54.rs | 27 - mcxa276-pac/src/trng0/pkrcnt76.rs | 27 - mcxa276-pac/src/trng0/pkrcnt98.rs | 27 - mcxa276-pac/src/trng0/pkrcntba.rs | 27 - mcxa276-pac/src/trng0/pkrcntdc.rs | 27 - mcxa276-pac/src/trng0/pkrcntfe.rs | 27 - mcxa276-pac/src/trng0/pkrmax_pkrmax.rs | 37 - mcxa276-pac/src/trng0/pkrrng.rs | 37 - mcxa276-pac/src/trng0/pkrsq_pkrsq.rs | 20 - mcxa276-pac/src/trng0/sblim_sblim.rs | 37 - mcxa276-pac/src/trng0/scmc_scmc.rs | 20 - mcxa276-pac/src/trng0/scmisc.rs | 51 - mcxa276-pac/src/trng0/scml_scml.rs | 51 - mcxa276-pac/src/trng0/scr1c_scr1c.rs | 27 - mcxa276-pac/src/trng0/scr1l_scr1l.rs | 51 - mcxa276-pac/src/trng0/scr2c_scr2c.rs | 27 - mcxa276-pac/src/trng0/scr2l_scr2l.rs | 51 - mcxa276-pac/src/trng0/scr3c_scr3c.rs | 27 - mcxa276-pac/src/trng0/scr3l_scr3l.rs | 51 - mcxa276-pac/src/trng0/scr4c_scr4c.rs | 27 - mcxa276-pac/src/trng0/scr4l_scr4l.rs | 51 - mcxa276-pac/src/trng0/scr5c_scr5c.rs | 27 - mcxa276-pac/src/trng0/scr5l_scr5l.rs | 51 - mcxa276-pac/src/trng0/scr6pc_scr6pc.rs | 27 - mcxa276-pac/src/trng0/scr6pl_scr6pl.rs | 51 - mcxa276-pac/src/trng0/sdctl.rs | 51 - mcxa276-pac/src/trng0/sec_cfg.rs | 84 - mcxa276-pac/src/trng0/status.rs | 676 -- mcxa276-pac/src/trng0/totsam_totsam.rs | 20 - mcxa276-pac/src/trng0/vid1.rs | 132 - mcxa276-pac/src/trng0/vid2.rs | 171 - mcxa276-pac/src/udf0.rs | 50 - mcxa276-pac/src/udf0/udf_ctrl.rs | 128 - mcxa276-pac/src/udf0/udf_rd_data.rs | 20 - mcxa276-pac/src/udf0/udf_status.rs | 100 - mcxa276-pac/src/udf0/udf_wr_data.rs | 22 - mcxa276-pac/src/usb0.rs | 493 -- mcxa276-pac/src/usb0/addinfo.rs | 56 - mcxa276-pac/src/usb0/addr.rs | 49 - mcxa276-pac/src/usb0/bdtpage1.rs | 35 - mcxa276-pac/src/usb0/bdtpage2.rs | 35 - mcxa276-pac/src/usb0/bdtpage3.rs | 35 - mcxa276-pac/src/usb0/clk_recover_ctrl.rs | 273 - mcxa276-pac/src/usb0/clk_recover_int_en.rs | 86 - mcxa276-pac/src/usb0/clk_recover_int_status.rs | 85 - mcxa276-pac/src/usb0/clk_recover_irc_en.rs | 86 - mcxa276-pac/src/usb0/control.rs | 176 - mcxa276-pac/src/usb0/ctl.rs | 280 - mcxa276-pac/src/usb0/endpoint.rs | 18 - mcxa276-pac/src/usb0/endpoint/endpt.rs | 266 - mcxa276-pac/src/usb0/erren.rs | 525 -- mcxa276-pac/src/usb0/errstat.rs | 526 -- mcxa276-pac/src/usb0/frmnumh.rs | 20 - mcxa276-pac/src/usb0/frmnuml.rs | 20 - mcxa276-pac/src/usb0/idcomp.rs | 22 - mcxa276-pac/src/usb0/inten.rs | 525 -- mcxa276-pac/src/usb0/istat.rs | 526 -- mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs | 25 - mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs | 25 - mcxa276-pac/src/usb0/miscctrl.rs | 399 -- mcxa276-pac/src/usb0/observe.rs | 138 - mcxa276-pac/src/usb0/otgctl.rs | 273 - mcxa276-pac/src/usb0/otgicr.rs | 147 - mcxa276-pac/src/usb0/otgistat.rs | 148 - mcxa276-pac/src/usb0/otgstat.rs | 61 - mcxa276-pac/src/usb0/perid.rs | 22 - mcxa276-pac/src/usb0/rev.rs | 22 - mcxa276-pac/src/usb0/softhld.rs | 35 - mcxa276-pac/src/usb0/stall_ih_dis.rs | 525 -- mcxa276-pac/src/usb0/stall_il_dis.rs | 525 -- mcxa276-pac/src/usb0/stall_oh_dis.rs | 525 -- mcxa276-pac/src/usb0/stall_ol_dis.rs | 525 -- mcxa276-pac/src/usb0/stat.rs | 102 - mcxa276-pac/src/usb0/token.rs | 118 - mcxa276-pac/src/usb0/usbctrl.rs | 401 -- mcxa276-pac/src/usb0/usbfrmadjust.rs | 35 - mcxa276-pac/src/usb0/usbtrc0.rs | 298 - mcxa276-pac/src/utick0.rs | 67 - mcxa276-pac/src/utick0/cap.rs | 61 - mcxa276-pac/src/utick0/capclr.rs | 159 - mcxa276-pac/src/utick0/cfg.rs | 525 -- mcxa276-pac/src/utick0/ctrl.rs | 98 - mcxa276-pac/src/utick0/stat.rs | 126 - mcxa276-pac/src/vbat0.rs | 97 - mcxa276-pac/src/vbat0/froclke.rs | 35 - mcxa276-pac/src/vbat0/froctla.rs | 86 - mcxa276-pac/src/vbat0/frolcka.rs | 84 - mcxa276-pac/src/vbat0/verid.rs | 36 - mcxa276-pac/src/vbat0/wakeup.rs | 18 - mcxa276-pac/src/vbat0/wakeup/wakeupa.rs | 35 - mcxa276-pac/src/vbat0/waklcka.rs | 84 - mcxa276-pac/src/waketimer0.rs | 29 - mcxa276-pac/src/waketimer0/wake_timer_cnt.rs | 35 - mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs | 247 - mcxa276-pac/src/wuu0.rs | 155 - mcxa276-pac/src/wuu0/de.rs | 210 - mcxa276-pac/src/wuu0/fdc.rs | 187 - mcxa276-pac/src/wuu0/filt.rs | 368 - mcxa276-pac/src/wuu0/fmc.rs | 147 - mcxa276-pac/src/wuu0/me.rs | 399 -- mcxa276-pac/src/wuu0/param.rs | 43 - mcxa276-pac/src/wuu0/pdc1.rs | 1557 ----- mcxa276-pac/src/wuu0/pdc2.rs | 1557 ----- mcxa276-pac/src/wuu0/pe1.rs | 1557 ----- mcxa276-pac/src/wuu0/pe2.rs | 1557 ----- mcxa276-pac/src/wuu0/pf.rs | 2038 ------ mcxa276-pac/src/wuu0/pmc.rs | 2037 ------ mcxa276-pac/src/wuu0/verid.rs | 76 - mcxa276-pac/src/wwdt0.rs | 73 - mcxa276-pac/src/wwdt0/feed.rs | 22 - mcxa276-pac/src/wwdt0/mod_.rs | 463 -- mcxa276-pac/src/wwdt0/tc.rs | 37 - mcxa276-pac/src/wwdt0/tv.rs | 22 - mcxa276-pac/src/wwdt0/warnint.rs | 35 - mcxa276-pac/src/wwdt0/window.rs | 37 - src/adc.rs | 7 +- 2007 files changed, 11 insertions(+), 530048 deletions(-) delete mode 100644 mcxa276-pac/Cargo.toml delete mode 100644 mcxa276-pac/build.rs delete mode 100644 mcxa276-pac/device.x delete mode 100644 mcxa276-pac/device.x.backup delete mode 100644 mcxa276-pac/src/adc0.rs delete mode 100644 mcxa276-pac/src/adc0/cal_gar.rs delete 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mode 100644 mcxa276-pac/src/wwdt0/feed.rs delete mode 100644 mcxa276-pac/src/wwdt0/mod_.rs delete mode 100644 mcxa276-pac/src/wwdt0/tc.rs delete mode 100644 mcxa276-pac/src/wwdt0/tv.rs delete mode 100644 mcxa276-pac/src/wwdt0/warnint.rs delete mode 100644 mcxa276-pac/src/wwdt0/window.rs diff --git a/Cargo.toml b/Cargo.toml index 858dc0974..fd3fba042 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,7 +13,7 @@ name = "embassy_mcxa276" [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m-rt = { version = "0.7", features = ["device"] } -mcxa276-pac = { path = "./mcxa276-pac", features = ["rt"] } +mcxa276-pac = { git = "https://github.com/bogdan-petru/mcxa-pac", features = ["rt"] } embedded-io = "0.6" # Optional defmt support defmt = { version = "0.3", optional = true } diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt index 7f9bee9e5..09f879c2f 100644 --- a/SW-Content-Register.txt +++ b/SW-Content-Register.txt @@ -1,4 +1,4 @@ -Release Name: Embassy MCXA276 HAL +Release Name: Embassy MCXA276 HAL Release Version: 0.1.0 Package License: MIT (see ./License.txt) Note: The crate is dual-licensed “MIT OR Apache-2.0” per Cargo.toml; choosing MIT satisfies the dual-license terms. @@ -25,9 +25,9 @@ mcxa276_pac Name: MCXA276 Peripheral Access Crate (PAC) Outgoing License: MIT OR Apache-2.0 License File: (see crate metadata) Format: Rust source code (auto-generated PAC) - Description: Auto-generated register mappings for MCXA276 peripherals (svd2rust). Includes device.x and interrupt vectors. This tree contains a small manual correction for a missing WAKETIMER0 vector/enum entry. - Location: ./mcxa276-pac - Origin: Generated by svd2rust from NXP SVD; local adjustments by OEMWCSE + Description: Auto-generated register mappings for MCXA276 peripherals (svd2rust). Includes device.x and interrupt vectors. + Location: External (git): https://github.com/bogdan-petru/mcxa-pac (pinned rev a9dd3301) + Origin: Generated by svdtools + svd2rust from NXP SVD 25.06.00 URL: N/A (generated from NXP SVD) examples Name: Example applications @@ -68,9 +68,11 @@ vcell License: MIT OR Apache-2.0 Purpose: Volatile ce defmt, defmt-rtt, rtt-target, panic-probe License: MIT OR Apache-2.0 Purpose: Optional (feature-gated) logging/panic crates Attribution notes -- MCXA276 PAC was generated from NXP SVD data using svd2rust and locally adjusted (see README “Development Notes” for the WAKETIMER0 vector fix). +- MCXA276 PAC is sourced as an external dependency (see Cargo.toml). SVD 25.06.00 already includes OS_EVENT and WAKETIMER0 interrupts (no local fixes). - Examples run from RAM using custom linker setup; see README.txt for platform-specific instructions. Compliance - This repository’s distributed source is covered by MIT (see License.txt). Where crates are pulled from crates.io, those crates retain their own licenses; the dual-license compatibility (MIT OR Apache-2.0) is standard in the Rust embedded ecosystem and is compatible with this project’s selected MIT distribution. + + diff --git a/mcxa276-pac/Cargo.toml b/mcxa276-pac/Cargo.toml deleted file mode 100644 index 7060ceaab..000000000 --- a/mcxa276-pac/Cargo.toml +++ /dev/null @@ -1,17 +0,0 @@ -[package] -name = "mcxa276-pac" -version = "0.1.0" -edition = "2021" -license = "MIT OR Apache-2.0" - -[lib] -path = "src/lib.rs" - -[dependencies] -cortex-m = "0.7" -vcell = "0.1" - -[features] -default = [] -rt = ["cortex-m/inline-asm"] -critical-section = [] diff --git a/mcxa276-pac/build.rs b/mcxa276-pac/build.rs deleted file mode 100644 index d0781acdb..000000000 --- a/mcxa276-pac/build.rs +++ /dev/null @@ -1,17 +0,0 @@ -#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; -fn main() { - if env::var_os("CARGO_FEATURE_RT").is_some() { - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - File::create(out.join("device.x")) - .unwrap() - .write_all(include_bytes!("device.x")) - .unwrap(); - println!("cargo:rustc-link-search={}", out.display()); - println!("cargo:rerun-if-changed=device.x"); - } - println!("cargo:rerun-if-changed=build.rs"); -} diff --git a/mcxa276-pac/device.x b/mcxa276-pac/device.x deleted file mode 100644 index 5f61e8ec0..000000000 --- a/mcxa276-pac/device.x +++ /dev/null @@ -1,129 +0,0 @@ -/* Ensure the OS_EVENT ISR symbol is retained by the linker, even if not - * referenced from Rust code due to LTO/GC. This matches how the C SDK keeps - * ISR symbols alive via the vector table. - */ -EXTERN(OS_EVENT); - - -PROVIDE(Reserved16 = DefaultHandler); -PROVIDE(CMC = DefaultHandler); -PROVIDE(DMA_CH0 = DefaultHandler); -PROVIDE(DMA_CH1 = DefaultHandler); -PROVIDE(DMA_CH2 = DefaultHandler); -PROVIDE(DMA_CH3 = DefaultHandler); -PROVIDE(DMA_CH4 = DefaultHandler); -PROVIDE(DMA_CH5 = DefaultHandler); -PROVIDE(DMA_CH6 = DefaultHandler); -PROVIDE(DMA_CH7 = DefaultHandler); -PROVIDE(ERM0_SINGLE_BIT = DefaultHandler); -PROVIDE(ERM0_MULTI_BIT = DefaultHandler); -PROVIDE(FMU0 = DefaultHandler); -PROVIDE(GLIKEY0 = DefaultHandler); -PROVIDE(MBC0 = DefaultHandler); -PROVIDE(SCG0 = DefaultHandler); -PROVIDE(SPC0 = DefaultHandler); -PROVIDE(TDET = DefaultHandler); -PROVIDE(WUU0 = DefaultHandler); -PROVIDE(CAN0 = DefaultHandler); -PROVIDE(CAN1 = DefaultHandler); -PROVIDE(RESERVED21 = DefaultHandler); -PROVIDE(RESERVED22 = DefaultHandler); -PROVIDE(FLEXIO = DefaultHandler); -PROVIDE(I3C0 = DefaultHandler); -PROVIDE(RESERVED25 = DefaultHandler); -PROVIDE(LPI2C0 = DefaultHandler); -PROVIDE(LPI2C1 = DefaultHandler); -PROVIDE(LPSPI0 = DefaultHandler); -PROVIDE(LPSPI1 = DefaultHandler); -PROVIDE(RESERVED30 = DefaultHandler); -PROVIDE(LPUART0 = DefaultHandler); -PROVIDE(LPUART1 = DefaultHandler); -PROVIDE(LPUART2 = DefaultHandler); -PROVIDE(LPUART3 = DefaultHandler); -PROVIDE(LPUART4 = DefaultHandler); -PROVIDE(USB0 = DefaultHandler); -PROVIDE(RESERVED37 = DefaultHandler); -PROVIDE(CDOG0 = DefaultHandler); -PROVIDE(CTIMER0 = DefaultHandler); -PROVIDE(CTIMER1 = DefaultHandler); -PROVIDE(CTIMER2 = DefaultHandler); -PROVIDE(CTIMER3 = DefaultHandler); -PROVIDE(CTIMER4 = DefaultHandler); -PROVIDE(FLEXPWM0_RELOAD_ERROR = DefaultHandler); -PROVIDE(FLEXPWM0_FAULT = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE0 = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE1 = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE2 = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE3 = DefaultHandler); -PROVIDE(EQDC0_COMPARE = DefaultHandler); -PROVIDE(EQDC0_HOME = DefaultHandler); -PROVIDE(EQDC0_WATCHDOG = DefaultHandler); -PROVIDE(EQDC0_INDEX = DefaultHandler); -PROVIDE(FREQME0 = DefaultHandler); -PROVIDE(LPTMR0 = DefaultHandler); -PROVIDE(RESERVED56 = DefaultHandler); -PROVIDE(OS_EVENT = DefaultHandler); /* IRQ 57 */ -PROVIDE(WAKETIMER0 = DefaultHandler); -PROVIDE(UTICK0 = DefaultHandler); -PROVIDE(WWDT0 = DefaultHandler); -PROVIDE(RESERVED61 = DefaultHandler); -PROVIDE(ADC0 = DefaultHandler); -PROVIDE(ADC1 = DefaultHandler); -PROVIDE(CMP0 = DefaultHandler); -PROVIDE(CMP1 = DefaultHandler); -PROVIDE(CMP2 = DefaultHandler); -PROVIDE(DAC0 = DefaultHandler); -PROVIDE(RESERVED68 = DefaultHandler); -PROVIDE(RESERVED69 = DefaultHandler); -PROVIDE(RESERVED70 = DefaultHandler); -PROVIDE(GPIO0 = DefaultHandler); -PROVIDE(GPIO1 = DefaultHandler); -PROVIDE(GPIO2 = DefaultHandler); -PROVIDE(GPIO3 = DefaultHandler); -PROVIDE(GPIO4 = DefaultHandler); -PROVIDE(RESERVED76 = DefaultHandler); -PROVIDE(LPI2C2 = DefaultHandler); -PROVIDE(LPI2C3 = DefaultHandler); -PROVIDE(FLEXPWM1_RELOAD_ERROR = DefaultHandler); -PROVIDE(FLEXPWM1_FAULT = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE0 = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE1 = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE2 = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE3 = DefaultHandler); -PROVIDE(EQDC1_COMPARE = DefaultHandler); -PROVIDE(EQDC1_HOME = DefaultHandler); -PROVIDE(EQDC1_WATCHDOG = DefaultHandler); -PROVIDE(EQDC1_INDEX = DefaultHandler); -PROVIDE(RESERVED89 = DefaultHandler); -PROVIDE(RESERVED90 = DefaultHandler); -PROVIDE(RESERVED91 = DefaultHandler); -PROVIDE(RESERVED92 = DefaultHandler); -PROVIDE(RESERVED93 = DefaultHandler); -PROVIDE(RESERVED94 = DefaultHandler); -PROVIDE(LPUART5 = DefaultHandler); -PROVIDE(RESERVED96 = DefaultHandler); -PROVIDE(RESERVED97 = DefaultHandler); -PROVIDE(RESERVED98 = DefaultHandler); -PROVIDE(RESERVED99 = DefaultHandler); -PROVIDE(RESERVED100 = DefaultHandler); -PROVIDE(RESERVED101 = DefaultHandler); -PROVIDE(RESERVED102 = DefaultHandler); -PROVIDE(RESERVED103 = DefaultHandler); -PROVIDE(RESERVED104 = DefaultHandler); -PROVIDE(RESERVED105 = DefaultHandler); -PROVIDE(RESERVED106 = DefaultHandler); -PROVIDE(MAU = DefaultHandler); -PROVIDE(SMARTDMA = DefaultHandler); -PROVIDE(CDOG1 = DefaultHandler); -PROVIDE(PKC = DefaultHandler); -PROVIDE(SGI = DefaultHandler); -PROVIDE(RESERVED112 = DefaultHandler); -PROVIDE(TRNG0 = DefaultHandler); -PROVIDE(SECURE_ERR = DefaultHandler); -PROVIDE(RESERVED115 = DefaultHandler); -PROVIDE(ADC2 = DefaultHandler); -PROVIDE(ADC3 = DefaultHandler); -PROVIDE(RESERVED118 = DefaultHandler); -PROVIDE(RTC = DefaultHandler); -PROVIDE(RTC_1HZ = DefaultHandler); -PROVIDE(SLCD = DefaultHandler); diff --git a/mcxa276-pac/device.x.backup b/mcxa276-pac/device.x.backup deleted file mode 100644 index e1e189cf7..000000000 --- a/mcxa276-pac/device.x.backup +++ /dev/null @@ -1,105 +0,0 @@ -/* Ensure the OS_EVENT ISR symbol is retained by the linker, even if not - * referenced from Rust code due to LTO/GC. This matches how the C SDK keeps - * ISR symbols alive via the vector table. - */ -EXTERN(OS_EVENT); - - -PROVIDE(Reserved16 = DefaultHandler); -PROVIDE(CMC = DefaultHandler); -PROVIDE(DMA_CH0 = DefaultHandler); -PROVIDE(DMA_CH1 = DefaultHandler); -PROVIDE(DMA_CH2 = DefaultHandler); -PROVIDE(DMA_CH3 = DefaultHandler); -PROVIDE(DMA_CH4 = DefaultHandler); -PROVIDE(DMA_CH5 = DefaultHandler); -PROVIDE(DMA_CH6 = DefaultHandler); -PROVIDE(DMA_CH7 = DefaultHandler); -PROVIDE(ERM0_SINGLE_BIT = DefaultHandler); -PROVIDE(ERM0_MULTI_BIT = DefaultHandler); -PROVIDE(FMU0 = DefaultHandler); -PROVIDE(GLIKEY0 = DefaultHandler); -PROVIDE(MBC0 = DefaultHandler); -PROVIDE(SCG0 = DefaultHandler); -PROVIDE(SPC0 = DefaultHandler); -PROVIDE(TDET = DefaultHandler); -PROVIDE(WUU0 = DefaultHandler); -PROVIDE(CAN0 = DefaultHandler); -PROVIDE(CAN1 = DefaultHandler); -PROVIDE(RESERVED21 = DefaultHandler); /* IRQ 21 - reserved */ -PROVIDE(RESERVED22 = DefaultHandler); /* IRQ 22 - reserved */ -PROVIDE(FLEXIO = DefaultHandler); -PROVIDE(I3C0 = DefaultHandler); -PROVIDE(RESERVED25 = DefaultHandler); /* IRQ 25 - reserved */ -PROVIDE(LPI2C0 = DefaultHandler); -PROVIDE(LPI2C1 = DefaultHandler); -PROVIDE(LPSPI0 = DefaultHandler); -PROVIDE(LPSPI1 = DefaultHandler); -PROVIDE(RESERVED30 = DefaultHandler); /* IRQ 30 - reserved */ -PROVIDE(LPUART0 = DefaultHandler); -PROVIDE(LPUART1 = DefaultHandler); -PROVIDE(LPUART2 = DefaultHandler); -PROVIDE(LPUART3 = DefaultHandler); -PROVIDE(LPUART4 = DefaultHandler); -PROVIDE(USB0 = DefaultHandler); -PROVIDE(RESERVED37 = DefaultHandler); /* IRQ 37 - reserved */ -PROVIDE(CDOG0 = DefaultHandler); -PROVIDE(CTIMER0 = DefaultHandler); -PROVIDE(CTIMER1 = DefaultHandler); -PROVIDE(CTIMER2 = DefaultHandler); -PROVIDE(CTIMER3 = DefaultHandler); -PROVIDE(CTIMER4 = DefaultHandler); -PROVIDE(FLEXPWM0_RELOAD_ERROR = DefaultHandler); -PROVIDE(FLEXPWM0_FAULT = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE0 = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE1 = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE2 = DefaultHandler); -PROVIDE(FLEXPWM0_SUBMODULE3 = DefaultHandler); -PROVIDE(EQDC0_COMPARE = DefaultHandler); -PROVIDE(EQDC0_HOME = DefaultHandler); -PROVIDE(EQDC0_WATCHDOG = DefaultHandler); -PROVIDE(EQDC0_INDEX = DefaultHandler); -PROVIDE(FREQME0 = DefaultHandler); -PROVIDE(LPTMR0 = DefaultHandler); -PROVIDE(RESERVED56 = DefaultHandler); /* IRQ 56 - reserved */ -PROVIDE(OS_EVENT = DefaultHandler); /* IRQ 57 */ -PROVIDE(WAKETIMER0 = DefaultHandler); -PROVIDE(UTICK0 = DefaultHandler); -PROVIDE(WWDT0 = DefaultHandler); -PROVIDE(RESERVED61 = DefaultHandler); /* IRQ 61 - reserved */ -PROVIDE(ADC0 = DefaultHandler); -PROVIDE(ADC1 = DefaultHandler); -PROVIDE(CMP0 = DefaultHandler); -PROVIDE(CMP1 = DefaultHandler); -PROVIDE(CMP2 = DefaultHandler); -PROVIDE(DAC0 = DefaultHandler); -PROVIDE(GPIO0 = DefaultHandler); -PROVIDE(GPIO1 = DefaultHandler); -PROVIDE(GPIO2 = DefaultHandler); -PROVIDE(GPIO3 = DefaultHandler); -PROVIDE(GPIO4 = DefaultHandler); -PROVIDE(LPI2C2 = DefaultHandler); -PROVIDE(LPI2C3 = DefaultHandler); -PROVIDE(FLEXPWM1_RELOAD_ERROR = DefaultHandler); -PROVIDE(FLEXPWM1_FAULT = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE0 = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE1 = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE2 = DefaultHandler); -PROVIDE(FLEXPWM1_SUBMODULE3 = DefaultHandler); -PROVIDE(EQDC1_COMPARE = DefaultHandler); -PROVIDE(EQDC1_HOME = DefaultHandler); -PROVIDE(EQDC1_WATCHDOG = DefaultHandler); -PROVIDE(EQDC1_INDEX = DefaultHandler); -PROVIDE(LPUART5 = DefaultHandler); -PROVIDE(MAU = DefaultHandler); -PROVIDE(SMARTDMA = DefaultHandler); -PROVIDE(CDOG1 = DefaultHandler); -PROVIDE(PKC = DefaultHandler); -PROVIDE(SGI = DefaultHandler); -PROVIDE(TRNG0 = DefaultHandler); -PROVIDE(ADC2 = DefaultHandler); -PROVIDE(ADC3 = DefaultHandler); -PROVIDE(RTC = DefaultHandler); -PROVIDE(RTC_1HZ = DefaultHandler); -PROVIDE(SLCD = DefaultHandler); - diff --git a/mcxa276-pac/src/adc0.rs b/mcxa276-pac/src/adc0.rs deleted file mode 100644 index 7daa8401f..000000000 --- a/mcxa276-pac/src/adc0.rs +++ /dev/null @@ -1,448 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - _reserved2: [u8; 0x08], - ctrl: Ctrl, - stat: Stat, - ie: Ie, - de: De, - cfg: Cfg, - pause: Pause, - _reserved8: [u8; 0x0c], - swtrig: Swtrig, - tstat: Tstat, - _reserved10: [u8; 0x04], - ofstrim: Ofstrim, - _reserved11: [u8; 0x04], - hstrim: Hstrim, - _reserved12: [u8; 0x54], - tctrl: [Tctrl; 4], - _reserved13: [u8; 0x30], - fctrl0: Fctrl0, - _reserved14: [u8; 0x0c], - gcc0: Gcc0, - _reserved15: [u8; 0x04], - gcr0: Gcr0, - _reserved16: [u8; 0x04], - cmdl1: Cmdl1, - cmdh1: Cmdh1, - cmdl2: Cmdl2, - cmdh2: Cmdh2, - cmdl3: Cmdl3, - cmdh3: Cmdh3, - cmdl4: Cmdl4, - cmdh4: Cmdh4, - cmdl5: Cmdl5, - cmdh5: Cmdh5, - cmdl6: Cmdl6, - cmdh6: Cmdh6, - cmdl7: Cmdl7, - cmdh7: Cmdh7, - _reserved30: [u8; 0xc8], - cv: [Cv; 7], - _reserved31: [u8; 0xe4], - resfifo0: Resfifo0, - _reserved32: [u8; 0xfc], - cal_gar: [CalGar; 34], - _reserved33: [u8; 0x0b70], - cfg2: Cfg2, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID Register"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter Register"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x10 - Control Register"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } - #[doc = "0x14 - Status Register"] - #[inline(always)] - pub const fn stat(&self) -> &Stat { - &self.stat - } - #[doc = "0x18 - Interrupt Enable Register"] - #[inline(always)] - pub const fn ie(&self) -> &Ie { - &self.ie - } - #[doc = "0x1c - DMA Enable Register"] - #[inline(always)] - pub const fn de(&self) -> &De { - &self.de - } - #[doc = "0x20 - Configuration Register"] - #[inline(always)] - pub const fn cfg(&self) -> &Cfg { - &self.cfg - } - #[doc = "0x24 - Pause Register"] - #[inline(always)] - pub const fn pause(&self) -> &Pause { - &self.pause - } - #[doc = "0x34 - Software Trigger Register"] - #[inline(always)] - pub const fn swtrig(&self) -> &Swtrig { - &self.swtrig - } - #[doc = "0x38 - Trigger Status Register"] - #[inline(always)] - pub const fn tstat(&self) -> &Tstat { - &self.tstat - } - #[doc = "0x40 - Offset Trim Register"] - #[inline(always)] - pub const fn ofstrim(&self) -> &Ofstrim { - &self.ofstrim - } - #[doc = "0x48 - High Speed Trim Register"] - #[inline(always)] - pub const fn hstrim(&self) -> &Hstrim { - &self.hstrim - } - #[doc = "0xa0..0xb0 - Trigger Control Register"] - #[inline(always)] - pub const fn tctrl(&self, n: usize) -> &Tctrl { - &self.tctrl[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0xa0..0xb0 - Trigger Control Register"] - #[inline(always)] - pub fn tctrl_iter(&self) -> impl Iterator { - self.tctrl.iter() - } - #[doc = "0xe0 - FIFO Control Register"] - #[inline(always)] - pub const fn fctrl0(&self) -> &Fctrl0 { - &self.fctrl0 - } - #[doc = "0xf0 - Gain Calibration Control"] - #[inline(always)] - pub const fn gcc0(&self) -> &Gcc0 { - &self.gcc0 - } - #[doc = "0xf8 - Gain Calculation Result"] - #[inline(always)] - pub const fn gcr0(&self) -> &Gcr0 { - &self.gcr0 - } - #[doc = "0x100 - Command Low Buffer Register"] - #[inline(always)] - pub const fn cmdl1(&self) -> &Cmdl1 { - &self.cmdl1 - } - #[doc = "0x104 - Command High Buffer Register"] - #[inline(always)] - pub const fn cmdh1(&self) -> &Cmdh1 { - &self.cmdh1 - } - #[doc = "0x108 - Command Low Buffer Register"] - #[inline(always)] - pub const fn cmdl2(&self) -> &Cmdl2 { - &self.cmdl2 - } - #[doc = "0x10c - Command High Buffer Register"] - #[inline(always)] - pub const fn cmdh2(&self) -> &Cmdh2 { - &self.cmdh2 - } - #[doc = "0x110 - Command Low Buffer Register"] - #[inline(always)] - pub const fn cmdl3(&self) -> &Cmdl3 { - &self.cmdl3 - } - #[doc = "0x114 - Command High Buffer Register"] - #[inline(always)] - pub const fn cmdh3(&self) -> &Cmdh3 { - &self.cmdh3 - } - #[doc = "0x118 - Command Low Buffer Register"] - #[inline(always)] - pub const fn cmdl4(&self) -> &Cmdl4 { - &self.cmdl4 - } - #[doc = "0x11c - Command High Buffer Register"] - #[inline(always)] - pub const fn cmdh4(&self) -> &Cmdh4 { - &self.cmdh4 - } - #[doc = "0x120 - Command Low Buffer Register"] - #[inline(always)] - pub const fn cmdl5(&self) -> &Cmdl5 { - &self.cmdl5 - } - #[doc = "0x124 - Command High Buffer Register"] - #[inline(always)] - pub const fn cmdh5(&self) -> &Cmdh5 { - &self.cmdh5 - } - #[doc = "0x128 - Command Low Buffer Register"] - #[inline(always)] - pub const fn cmdl6(&self) -> &Cmdl6 { - &self.cmdl6 - } - #[doc = "0x12c - Command High Buffer Register"] - #[inline(always)] - pub const fn cmdh6(&self) -> &Cmdh6 { - &self.cmdh6 - } - #[doc = "0x130 - Command Low Buffer Register"] - #[inline(always)] - pub const fn cmdl7(&self) -> &Cmdl7 { - &self.cmdl7 - } - #[doc = "0x134 - Command High Buffer Register"] - #[inline(always)] - pub const fn cmdh7(&self) -> &Cmdh7 { - &self.cmdh7 - } - #[doc = "0x200..0x21c - Compare Value Register"] - #[doc = ""] - #[doc = "
`n` is the index of register in the array. `n == 0` corresponds to `CV1` register.
"] - #[inline(always)] - pub const fn cv(&self, n: usize) -> &Cv { - &self.cv[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x200..0x21c - Compare Value Register"] - #[inline(always)] - pub fn cv_iter(&self) -> impl Iterator { - self.cv.iter() - } - #[doc = "0x200 - Compare Value Register"] - #[inline(always)] - pub const fn cv1(&self) -> &Cv { - self.cv(0) - } - #[doc = "0x204 - Compare Value Register"] - #[inline(always)] - pub const fn cv2(&self) -> &Cv { - self.cv(1) - } - #[doc = "0x208 - Compare Value Register"] - #[inline(always)] - pub const fn cv3(&self) -> &Cv { - self.cv(2) - } - #[doc = "0x20c - Compare Value Register"] - #[inline(always)] - pub const fn cv4(&self) -> &Cv { - self.cv(3) - } - #[doc = "0x210 - Compare Value Register"] - #[inline(always)] - pub const fn cv5(&self) -> &Cv { - self.cv(4) - } - #[doc = "0x214 - Compare Value Register"] - #[inline(always)] - pub const fn cv6(&self) -> &Cv { - self.cv(5) - } - #[doc = "0x218 - Compare Value Register"] - #[inline(always)] - pub const fn cv7(&self) -> &Cv { - self.cv(6) - } - #[doc = "0x300 - Data Result FIFO Register"] - #[inline(always)] - pub const fn resfifo0(&self) -> &Resfifo0 { - &self.resfifo0 - } - #[doc = "0x400..0x488 - Calibration General A-Side Registers"] - #[inline(always)] - pub const fn cal_gar(&self, n: usize) -> &CalGar { - &self.cal_gar[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x400..0x488 - Calibration General A-Side Registers"] - #[inline(always)] - pub fn cal_gar_iter(&self) -> impl Iterator { - self.cal_gar.iter() - } - #[doc = "0xff8 - Configuration 2 Register"] - #[inline(always)] - pub const fn cfg2(&self) -> &Cfg2 { - &self.cfg2 - } -} -#[doc = "VERID (r) register accessor: Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID Register"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter Register"] -pub mod param; -#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "Control Register"] -pub mod ctrl; -#[doc = "STAT (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] -#[doc(alias = "STAT")] -pub type Stat = crate::Reg; -#[doc = "Status Register"] -pub mod stat; -#[doc = "IE (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`] module"] -#[doc(alias = "IE")] -pub type Ie = crate::Reg; -#[doc = "Interrupt Enable Register"] -pub mod ie; -#[doc = "DE (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@de`] module"] -#[doc(alias = "DE")] -pub type De = crate::Reg; -#[doc = "DMA Enable Register"] -pub mod de; -#[doc = "CFG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`] module"] -#[doc(alias = "CFG")] -pub type Cfg = crate::Reg; -#[doc = "Configuration Register"] -pub mod cfg; -#[doc = "PAUSE (rw) register accessor: Pause Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pause::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pause`] module"] -#[doc(alias = "PAUSE")] -pub type Pause = crate::Reg; -#[doc = "Pause Register"] -pub mod pause; -#[doc = "SWTRIG (rw) register accessor: Software Trigger Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swtrig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swtrig`] module"] -#[doc(alias = "SWTRIG")] -pub type Swtrig = crate::Reg; -#[doc = "Software Trigger Register"] -pub mod swtrig; -#[doc = "TSTAT (rw) register accessor: Trigger Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstat`] module"] -#[doc(alias = "TSTAT")] -pub type Tstat = crate::Reg; -#[doc = "Trigger Status Register"] -pub mod tstat; -#[doc = "OFSTRIM (rw) register accessor: Offset Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ofstrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ofstrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ofstrim`] module"] -#[doc(alias = "OFSTRIM")] -pub type Ofstrim = crate::Reg; -#[doc = "Offset Trim Register"] -pub mod ofstrim; -#[doc = "HSTRIM (rw) register accessor: High Speed Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hstrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hstrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hstrim`] module"] -#[doc(alias = "HSTRIM")] -pub type Hstrim = crate::Reg; -#[doc = "High Speed Trim Register"] -pub mod hstrim; -#[doc = "TCTRL (rw) register accessor: Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tctrl`] module"] -#[doc(alias = "TCTRL")] -pub type Tctrl = crate::Reg; -#[doc = "Trigger Control Register"] -pub mod tctrl; -#[doc = "FCTRL0 (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl0`] module"] -#[doc(alias = "FCTRL0")] -pub type Fctrl0 = crate::Reg; -#[doc = "FIFO Control Register"] -pub mod fctrl0; -#[doc = "GCC0 (r) register accessor: Gain Calibration Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcc0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcc0`] module"] -#[doc(alias = "GCC0")] -pub type Gcc0 = crate::Reg; -#[doc = "Gain Calibration Control"] -pub mod gcc0; -#[doc = "GCR0 (rw) register accessor: Gain Calculation Result\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr0`] module"] -#[doc(alias = "GCR0")] -pub type Gcr0 = crate::Reg; -#[doc = "Gain Calculation Result"] -pub mod gcr0; -#[doc = "CMDL1 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl1`] module"] -#[doc(alias = "CMDL1")] -pub type Cmdl1 = crate::Reg; -#[doc = "Command Low Buffer Register"] -pub mod cmdl1; -#[doc = "CMDH1 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh1`] module"] -#[doc(alias = "CMDH1")] -pub type Cmdh1 = crate::Reg; -#[doc = "Command High Buffer Register"] -pub mod cmdh1; -#[doc = "CMDL2 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl2`] module"] -#[doc(alias = "CMDL2")] -pub type Cmdl2 = crate::Reg; -#[doc = "Command Low Buffer Register"] -pub mod cmdl2; -#[doc = "CMDH2 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh2`] module"] -#[doc(alias = "CMDH2")] -pub type Cmdh2 = crate::Reg; -#[doc = "Command High Buffer Register"] -pub mod cmdh2; -#[doc = "CMDL3 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl3`] module"] -#[doc(alias = "CMDL3")] -pub type Cmdl3 = crate::Reg; -#[doc = "Command Low Buffer Register"] -pub mod cmdl3; -#[doc = "CMDH3 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh3`] module"] -#[doc(alias = "CMDH3")] -pub type Cmdh3 = crate::Reg; -#[doc = "Command High Buffer Register"] -pub mod cmdh3; -#[doc = "CMDL4 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl4`] module"] -#[doc(alias = "CMDL4")] -pub type Cmdl4 = crate::Reg; -#[doc = "Command Low Buffer Register"] -pub mod cmdl4; -#[doc = "CMDH4 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh4`] module"] -#[doc(alias = "CMDH4")] -pub type Cmdh4 = crate::Reg; -#[doc = "Command High Buffer Register"] -pub mod cmdh4; -#[doc = "CMDL5 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl5`] module"] -#[doc(alias = "CMDL5")] -pub type Cmdl5 = crate::Reg; -#[doc = "Command Low Buffer Register"] -pub mod cmdl5; -#[doc = "CMDH5 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh5`] module"] -#[doc(alias = "CMDH5")] -pub type Cmdh5 = crate::Reg; -#[doc = "Command High Buffer Register"] -pub mod cmdh5; -#[doc = "CMDL6 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl6`] module"] -#[doc(alias = "CMDL6")] -pub type Cmdl6 = crate::Reg; -#[doc = "Command Low Buffer Register"] -pub mod cmdl6; -#[doc = "CMDH6 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh6`] module"] -#[doc(alias = "CMDH6")] -pub type Cmdh6 = crate::Reg; -#[doc = "Command High Buffer Register"] -pub mod cmdh6; -#[doc = "CMDL7 (rw) register accessor: Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdl7`] module"] -#[doc(alias = "CMDL7")] -pub type Cmdl7 = crate::Reg; -#[doc = "Command Low Buffer Register"] -pub mod cmdl7; -#[doc = "CMDH7 (rw) register accessor: Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdh7`] module"] -#[doc(alias = "CMDH7")] -pub type Cmdh7 = crate::Reg; -#[doc = "Command High Buffer Register"] -pub mod cmdh7; -#[doc = "CV (rw) register accessor: Compare Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cv`] module"] -#[doc(alias = "CV")] -pub type Cv = crate::Reg; -#[doc = "Compare Value Register"] -pub mod cv; -#[doc = "RESFIFO0 (r) register accessor: Data Result FIFO Register\n\nYou can [`read`](crate::Reg::read) this register and get [`resfifo0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resfifo0`] module"] -#[doc(alias = "RESFIFO0")] -pub type Resfifo0 = crate::Reg; -#[doc = "Data Result FIFO Register"] -pub mod resfifo0; -#[doc = "CAL_GAR (rw) register accessor: Calibration General A-Side Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`cal_gar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cal_gar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cal_gar`] module"] -#[doc(alias = "CAL_GAR")] -pub type CalGar = crate::Reg; -#[doc = "Calibration General A-Side Registers"] -pub mod cal_gar; -#[doc = "CFG2 (rw) register accessor: Configuration 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg2`] module"] -#[doc(alias = "CFG2")] -pub type Cfg2 = crate::Reg; -#[doc = "Configuration 2 Register"] -pub mod cfg2; diff --git a/mcxa276-pac/src/adc0/cal_gar.rs b/mcxa276-pac/src/adc0/cal_gar.rs deleted file mode 100644 index 3a3375b33..000000000 --- a/mcxa276-pac/src/adc0/cal_gar.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CAL_GAR[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `CAL_GAR[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `CAL_GAR_VAL` reader - Calibration General A Side Register Element"] -pub type CalGarValR = crate::FieldReader; -#[doc = "Field `CAL_GAR_VAL` writer - Calibration General A Side Register Element"] -pub type CalGarValW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Calibration General A Side Register Element"] - #[inline(always)] - pub fn cal_gar_val(&self) -> CalGarValR { - CalGarValR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Calibration General A Side Register Element"] - #[inline(always)] - pub fn cal_gar_val(&mut self) -> CalGarValW { - CalGarValW::new(self, 0) - } -} -#[doc = "Calibration General A-Side Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`cal_gar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cal_gar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CalGarSpec; -impl crate::RegisterSpec for CalGarSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cal_gar::R`](R) reader structure"] -impl crate::Readable for CalGarSpec {} -#[doc = "`write(|w| ..)` method takes [`cal_gar::W`](W) writer structure"] -impl crate::Writable for CalGarSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CAL_GAR[%s] to value 0"] -impl crate::Resettable for CalGarSpec {} diff --git a/mcxa276-pac/src/adc0/cfg.rs b/mcxa276-pac/src/adc0/cfg.rs deleted file mode 100644 index 97c500db0..000000000 --- a/mcxa276-pac/src/adc0/cfg.rs +++ /dev/null @@ -1,518 +0,0 @@ -#[doc = "Register `CFG` reader"] -pub type R = crate::R; -#[doc = "Register `CFG` writer"] -pub type W = crate::W; -#[doc = "ADC Trigger Priority Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tprictrl { - #[doc = "0: If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."] - AbortCurrentOnPriority = 0, - #[doc = "1: If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."] - FinishCurrentOnPriority = 1, - #[doc = "2: If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."] - FinishSequenceOnPriority = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tprictrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tprictrl { - type Ux = u8; -} -impl crate::IsEnum for Tprictrl {} -#[doc = "Field `TPRICTRL` reader - ADC Trigger Priority Control"] -pub type TprictrlR = crate::FieldReader; -impl TprictrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Tprictrl::AbortCurrentOnPriority), - 1 => Some(Tprictrl::FinishCurrentOnPriority), - 2 => Some(Tprictrl::FinishSequenceOnPriority), - _ => None, - } - } - #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."] - #[inline(always)] - pub fn is_abort_current_on_priority(&self) -> bool { - *self == Tprictrl::AbortCurrentOnPriority - } - #[doc = "If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."] - #[inline(always)] - pub fn is_finish_current_on_priority(&self) -> bool { - *self == Tprictrl::FinishCurrentOnPriority - } - #[doc = "If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."] - #[inline(always)] - pub fn is_finish_sequence_on_priority(&self) -> bool { - *self == Tprictrl::FinishSequenceOnPriority - } -} -#[doc = "Field `TPRICTRL` writer - ADC Trigger Priority Control"] -pub type TprictrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tprictrl>; -impl<'a, REG> TprictrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."] - #[inline(always)] - pub fn abort_current_on_priority(self) -> &'a mut crate::W { - self.variant(Tprictrl::AbortCurrentOnPriority) - } - #[doc = "If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."] - #[inline(always)] - pub fn finish_current_on_priority(self) -> &'a mut crate::W { - self.variant(Tprictrl::FinishCurrentOnPriority) - } - #[doc = "If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."] - #[inline(always)] - pub fn finish_sequence_on_priority(self) -> &'a mut crate::W { - self.variant(Tprictrl::FinishSequenceOnPriority) - } -} -#[doc = "Power Configuration Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwrsel { - #[doc = "0: Low power"] - Lowest = 0, - #[doc = "1: High power"] - Highest = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwrsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWRSEL` reader - Power Configuration Select"] -pub type PwrselR = crate::BitReader; -impl PwrselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwrsel { - match self.bits { - false => Pwrsel::Lowest, - true => Pwrsel::Highest, - } - } - #[doc = "Low power"] - #[inline(always)] - pub fn is_lowest(&self) -> bool { - *self == Pwrsel::Lowest - } - #[doc = "High power"] - #[inline(always)] - pub fn is_highest(&self) -> bool { - *self == Pwrsel::Highest - } -} -#[doc = "Field `PWRSEL` writer - Power Configuration Select"] -pub type PwrselW<'a, REG> = crate::BitWriter<'a, REG, Pwrsel>; -impl<'a, REG> PwrselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low power"] - #[inline(always)] - pub fn lowest(self) -> &'a mut crate::W { - self.variant(Pwrsel::Lowest) - } - #[doc = "High power"] - #[inline(always)] - pub fn highest(self) -> &'a mut crate::W { - self.variant(Pwrsel::Highest) - } -} -#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Refsel { - #[doc = "0: (Default) Option 1 setting."] - Option1 = 0, - #[doc = "1: Option 2 setting."] - Option2 = 1, - #[doc = "2: Option 3 setting."] - Option3 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Refsel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Refsel { - type Ux = u8; -} -impl crate::IsEnum for Refsel {} -#[doc = "Field `REFSEL` reader - Voltage Reference Selection"] -pub type RefselR = crate::FieldReader; -impl RefselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Refsel::Option1), - 1 => Some(Refsel::Option2), - 2 => Some(Refsel::Option3), - _ => None, - } - } - #[doc = "(Default) Option 1 setting."] - #[inline(always)] - pub fn is_option_1(&self) -> bool { - *self == Refsel::Option1 - } - #[doc = "Option 2 setting."] - #[inline(always)] - pub fn is_option_2(&self) -> bool { - *self == Refsel::Option2 - } - #[doc = "Option 3 setting."] - #[inline(always)] - pub fn is_option_3(&self) -> bool { - *self == Refsel::Option3 - } -} -#[doc = "Field `REFSEL` writer - Voltage Reference Selection"] -pub type RefselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Refsel>; -impl<'a, REG> RefselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "(Default) Option 1 setting."] - #[inline(always)] - pub fn option_1(self) -> &'a mut crate::W { - self.variant(Refsel::Option1) - } - #[doc = "Option 2 setting."] - #[inline(always)] - pub fn option_2(self) -> &'a mut crate::W { - self.variant(Refsel::Option2) - } - #[doc = "Option 3 setting."] - #[inline(always)] - pub fn option_3(self) -> &'a mut crate::W { - self.variant(Refsel::Option3) - } -} -#[doc = "Trigger Resume Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tres { - #[doc = "0: Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."] - Disabled = 0, - #[doc = "1: Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tres) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRES` reader - Trigger Resume Enable"] -pub type TresR = crate::BitReader; -impl TresR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tres { - match self.bits { - false => Tres::Disabled, - true => Tres::Enabled, - } - } - #[doc = "Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tres::Disabled - } - #[doc = "Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tres::Enabled - } -} -#[doc = "Field `TRES` writer - Trigger Resume Enable"] -pub type TresW<'a, REG> = crate::BitWriter<'a, REG, Tres>; -impl<'a, REG> TresW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tres::Disabled) - } - #[doc = "Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tres::Enabled) - } -} -#[doc = "Trigger Command Resume\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tcmdres { - #[doc = "0: Trigger sequences interrupted by a high priority trigger exception is automatically restarted."] - Disabled = 0, - #[doc = "1: Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tcmdres) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCMDRES` reader - Trigger Command Resume"] -pub type TcmdresR = crate::BitReader; -impl TcmdresR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcmdres { - match self.bits { - false => Tcmdres::Disabled, - true => Tcmdres::Enabled, - } - } - #[doc = "Trigger sequences interrupted by a high priority trigger exception is automatically restarted."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tcmdres::Disabled - } - #[doc = "Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tcmdres::Enabled - } -} -#[doc = "Field `TCMDRES` writer - Trigger Command Resume"] -pub type TcmdresW<'a, REG> = crate::BitWriter<'a, REG, Tcmdres>; -impl<'a, REG> TcmdresW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trigger sequences interrupted by a high priority trigger exception is automatically restarted."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tcmdres::Disabled) - } - #[doc = "Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tcmdres::Enabled) - } -} -#[doc = "High Priority Trigger Exception Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum HptExdi { - #[doc = "0: High priority trigger exceptions are enabled."] - Enabled = 0, - #[doc = "1: High priority trigger exceptions are disabled."] - Disabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: HptExdi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HPT_EXDI` reader - High Priority Trigger Exception Disable"] -pub type HptExdiR = crate::BitReader; -impl HptExdiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> HptExdi { - match self.bits { - false => HptExdi::Enabled, - true => HptExdi::Disabled, - } - } - #[doc = "High priority trigger exceptions are enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == HptExdi::Enabled - } - #[doc = "High priority trigger exceptions are disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == HptExdi::Disabled - } -} -#[doc = "Field `HPT_EXDI` writer - High Priority Trigger Exception Disable"] -pub type HptExdiW<'a, REG> = crate::BitWriter<'a, REG, HptExdi>; -impl<'a, REG> HptExdiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "High priority trigger exceptions are enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(HptExdi::Enabled) - } - #[doc = "High priority trigger exceptions are disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(HptExdi::Disabled) - } -} -#[doc = "Field `PUDLY` reader - Power Up Delay"] -pub type PudlyR = crate::FieldReader; -#[doc = "Field `PUDLY` writer - Power Up Delay"] -pub type PudlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "ADC Analog Pre-Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwren { - #[doc = "0: ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."] - NotPreEnabled = 0, - #[doc = "1: ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."] - PreEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWREN` reader - ADC Analog Pre-Enable"] -pub type PwrenR = crate::BitReader; -impl PwrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwren { - match self.bits { - false => Pwren::NotPreEnabled, - true => Pwren::PreEnabled, - } - } - #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."] - #[inline(always)] - pub fn is_not_pre_enabled(&self) -> bool { - *self == Pwren::NotPreEnabled - } - #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."] - #[inline(always)] - pub fn is_pre_enabled(&self) -> bool { - *self == Pwren::PreEnabled - } -} -#[doc = "Field `PWREN` writer - ADC Analog Pre-Enable"] -pub type PwrenW<'a, REG> = crate::BitWriter<'a, REG, Pwren>; -impl<'a, REG> PwrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."] - #[inline(always)] - pub fn not_pre_enabled(self) -> &'a mut crate::W { - self.variant(Pwren::NotPreEnabled) - } - #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."] - #[inline(always)] - pub fn pre_enabled(self) -> &'a mut crate::W { - self.variant(Pwren::PreEnabled) - } -} -impl R { - #[doc = "Bits 0:1 - ADC Trigger Priority Control"] - #[inline(always)] - pub fn tprictrl(&self) -> TprictrlR { - TprictrlR::new((self.bits & 3) as u8) - } - #[doc = "Bit 5 - Power Configuration Select"] - #[inline(always)] - pub fn pwrsel(&self) -> PwrselR { - PwrselR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bits 6:7 - Voltage Reference Selection"] - #[inline(always)] - pub fn refsel(&self) -> RefselR { - RefselR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - Trigger Resume Enable"] - #[inline(always)] - pub fn tres(&self) -> TresR { - TresR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Trigger Command Resume"] - #[inline(always)] - pub fn tcmdres(&self) -> TcmdresR { - TcmdresR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - High Priority Trigger Exception Disable"] - #[inline(always)] - pub fn hpt_exdi(&self) -> HptExdiR { - HptExdiR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bits 16:23 - Power Up Delay"] - #[inline(always)] - pub fn pudly(&self) -> PudlyR { - PudlyR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bit 28 - ADC Analog Pre-Enable"] - #[inline(always)] - pub fn pwren(&self) -> PwrenR { - PwrenR::new(((self.bits >> 28) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - ADC Trigger Priority Control"] - #[inline(always)] - pub fn tprictrl(&mut self) -> TprictrlW { - TprictrlW::new(self, 0) - } - #[doc = "Bit 5 - Power Configuration Select"] - #[inline(always)] - pub fn pwrsel(&mut self) -> PwrselW { - PwrselW::new(self, 5) - } - #[doc = "Bits 6:7 - Voltage Reference Selection"] - #[inline(always)] - pub fn refsel(&mut self) -> RefselW { - RefselW::new(self, 6) - } - #[doc = "Bit 8 - Trigger Resume Enable"] - #[inline(always)] - pub fn tres(&mut self) -> TresW { - TresW::new(self, 8) - } - #[doc = "Bit 9 - Trigger Command Resume"] - #[inline(always)] - pub fn tcmdres(&mut self) -> TcmdresW { - TcmdresW::new(self, 9) - } - #[doc = "Bit 10 - High Priority Trigger Exception Disable"] - #[inline(always)] - pub fn hpt_exdi(&mut self) -> HptExdiW { - HptExdiW::new(self, 10) - } - #[doc = "Bits 16:23 - Power Up Delay"] - #[inline(always)] - pub fn pudly(&mut self) -> PudlyW { - PudlyW::new(self, 16) - } - #[doc = "Bit 28 - ADC Analog Pre-Enable"] - #[inline(always)] - pub fn pwren(&mut self) -> PwrenW { - PwrenW::new(self, 28) - } -} -#[doc = "Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CfgSpec; -impl crate::RegisterSpec for CfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cfg::R`](R) reader structure"] -impl crate::Readable for CfgSpec {} -#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] -impl crate::Writable for CfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CFG to value 0x0080_0000"] -impl crate::Resettable for CfgSpec { - const RESET_VALUE: u32 = 0x0080_0000; -} diff --git a/mcxa276-pac/src/adc0/cfg2.rs b/mcxa276-pac/src/adc0/cfg2.rs deleted file mode 100644 index c4023415a..000000000 --- a/mcxa276-pac/src/adc0/cfg2.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `CFG2` reader"] -pub type R = crate::R; -#[doc = "Register `CFG2` writer"] -pub type W = crate::W; -#[doc = "Field `JLEFT` reader - Justified Left Enable register"] -pub type JleftR = crate::BitReader; -#[doc = "Field `JLEFT` writer - Justified Left Enable register"] -pub type JleftW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "High Speed Enable register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hs { - #[doc = "0: High speed conversion mode disabled"] - Disabled = 0, - #[doc = "1: High speed conversion mode enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HS` reader - High Speed Enable register"] -pub type HsR = crate::BitReader; -impl HsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hs { - match self.bits { - false => Hs::Disabled, - true => Hs::Enabled, - } - } - #[doc = "High speed conversion mode disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Hs::Disabled - } - #[doc = "High speed conversion mode enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Hs::Enabled - } -} -#[doc = "Field `HS` writer - High Speed Enable register"] -pub type HsW<'a, REG> = crate::BitWriter<'a, REG, Hs>; -impl<'a, REG> HsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "High speed conversion mode disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Hs::Disabled) - } - #[doc = "High speed conversion mode enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Hs::Enabled) - } -} -#[doc = "High Speed Extra register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hsextra { - #[doc = "0: No extra cycle added"] - Hsextra0 = 0, - #[doc = "1: Extra cycle added"] - Hsextra1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hsextra) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HSEXTRA` reader - High Speed Extra register"] -pub type HsextraR = crate::BitReader; -impl HsextraR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hsextra { - match self.bits { - false => Hsextra::Hsextra0, - true => Hsextra::Hsextra1, - } - } - #[doc = "No extra cycle added"] - #[inline(always)] - pub fn is_hsextra_0(&self) -> bool { - *self == Hsextra::Hsextra0 - } - #[doc = "Extra cycle added"] - #[inline(always)] - pub fn is_hsextra_1(&self) -> bool { - *self == Hsextra::Hsextra1 - } -} -#[doc = "Field `HSEXTRA` writer - High Speed Extra register"] -pub type HsextraW<'a, REG> = crate::BitWriter<'a, REG, Hsextra>; -impl<'a, REG> HsextraW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No extra cycle added"] - #[inline(always)] - pub fn hsextra_0(self) -> &'a mut crate::W { - self.variant(Hsextra::Hsextra0) - } - #[doc = "Extra cycle added"] - #[inline(always)] - pub fn hsextra_1(self) -> &'a mut crate::W { - self.variant(Hsextra::Hsextra1) - } -} -#[doc = "Field `TUNE` reader - Tune Mode register"] -pub type TuneR = crate::FieldReader; -#[doc = "Field `TUNE` writer - Tune Mode register"] -pub type TuneW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bit 8 - Justified Left Enable register"] - #[inline(always)] - pub fn jleft(&self) -> JleftR { - JleftR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - High Speed Enable register"] - #[inline(always)] - pub fn hs(&self) -> HsR { - HsR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - High Speed Extra register"] - #[inline(always)] - pub fn hsextra(&self) -> HsextraR { - HsextraR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bits 12:13 - Tune Mode register"] - #[inline(always)] - pub fn tune(&self) -> TuneR { - TuneR::new(((self.bits >> 12) & 3) as u8) - } -} -impl W { - #[doc = "Bit 8 - Justified Left Enable register"] - #[inline(always)] - pub fn jleft(&mut self) -> JleftW { - JleftW::new(self, 8) - } - #[doc = "Bit 9 - High Speed Enable register"] - #[inline(always)] - pub fn hs(&mut self) -> HsW { - HsW::new(self, 9) - } - #[doc = "Bit 10 - High Speed Extra register"] - #[inline(always)] - pub fn hsextra(&mut self) -> HsextraW { - HsextraW::new(self, 10) - } - #[doc = "Bits 12:13 - Tune Mode register"] - #[inline(always)] - pub fn tune(&mut self) -> TuneW { - TuneW::new(self, 12) - } -} -#[doc = "Configuration 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cfg2Spec; -impl crate::RegisterSpec for Cfg2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cfg2::R`](R) reader structure"] -impl crate::Readable for Cfg2Spec {} -#[doc = "`write(|w| ..)` method takes [`cfg2::W`](W) writer structure"] -impl crate::Writable for Cfg2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CFG2 to value 0x1000"] -impl crate::Resettable for Cfg2Spec { - const RESET_VALUE: u32 = 0x1000; -} diff --git a/mcxa276-pac/src/adc0/cmdh1.rs b/mcxa276-pac/src/adc0/cmdh1.rs deleted file mode 100644 index 84204853f..000000000 --- a/mcxa276-pac/src/adc0/cmdh1.rs +++ /dev/null @@ -1,900 +0,0 @@ -#[doc = "Register `CMDH1` reader"] -pub type R = crate::R; -#[doc = "Register `CMDH1` writer"] -pub type W = crate::W; -#[doc = "Compare Function Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpen { - #[doc = "0: Compare disabled."] - DisabledAlwaysStoreResult = 0, - #[doc = "2: Compare enabled. Store on true."] - CompareResultStoreIfTrue = 2, - #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpen { - type Ux = u8; -} -impl crate::IsEnum for Cmpen {} -#[doc = "Field `CMPEN` reader - Compare Function Enable"] -pub type CmpenR = crate::FieldReader; -impl CmpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpen::DisabledAlwaysStoreResult), - 2 => Some(Cmpen::CompareResultStoreIfTrue), - 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), - _ => None, - } - } - #[doc = "Compare disabled."] - #[inline(always)] - pub fn is_disabled_always_store_result(&self) -> bool { - *self == Cmpen::DisabledAlwaysStoreResult - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn is_compare_result_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultStoreIfTrue - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue - } -} -#[doc = "Field `CMPEN` writer - Compare Function Enable"] -pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; -impl<'a, REG> CmpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Compare disabled."] - #[inline(always)] - pub fn disabled_always_store_result(self) -> &'a mut crate::W { - self.variant(Cmpen::DisabledAlwaysStoreResult) - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn compare_result_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultStoreIfTrue) - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) - } -} -#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WaitTrig { - #[doc = "0: This command will be automatically executed."] - Disabled = 0, - #[doc = "1: The active trigger must be asserted again before executing this command."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WaitTrig) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] -pub type WaitTrigR = crate::BitReader; -impl WaitTrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WaitTrig { - match self.bits { - false => WaitTrig::Disabled, - true => WaitTrig::Enabled, - } - } - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WaitTrig::Disabled - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WaitTrig::Enabled - } -} -#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] -pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; -impl<'a, REG> WaitTrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Disabled) - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Enabled) - } -} -#[doc = "Loop with Increment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lwi { - #[doc = "0: Auto channel increment disabled"] - Disabled = 0, - #[doc = "1: Auto channel increment enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lwi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LWI` reader - Loop with Increment"] -pub type LwiR = crate::BitReader; -impl LwiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lwi { - match self.bits { - false => Lwi::Disabled, - true => Lwi::Enabled, - } - } - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lwi::Disabled - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lwi::Enabled - } -} -#[doc = "Field `LWI` writer - Loop with Increment"] -pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; -impl<'a, REG> LwiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lwi::Disabled) - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lwi::Enabled) - } -} -#[doc = "Sample Time Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sts { - #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] - Sample3p5 = 0, - #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - Sample5p5 = 1, - #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - Sample7p5 = 2, - #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - Sample11p5 = 3, - #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - Sample19p5 = 4, - #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - Sample35p5 = 5, - #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - Sample67p5 = 6, - #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - Sample131p5 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sts) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sts { - type Ux = u8; -} -impl crate::IsEnum for Sts {} -#[doc = "Field `STS` reader - Sample Time Select"] -pub type StsR = crate::FieldReader; -impl StsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sts { - match self.bits { - 0 => Sts::Sample3p5, - 1 => Sts::Sample5p5, - 2 => Sts::Sample7p5, - 3 => Sts::Sample11p5, - 4 => Sts::Sample19p5, - 5 => Sts::Sample35p5, - 6 => Sts::Sample67p5, - 7 => Sts::Sample131p5, - _ => unreachable!(), - } - } - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn is_sample_3p5(&self) -> bool { - *self == Sts::Sample3p5 - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_5p5(&self) -> bool { - *self == Sts::Sample5p5 - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_7p5(&self) -> bool { - *self == Sts::Sample7p5 - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_11p5(&self) -> bool { - *self == Sts::Sample11p5 - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_19p5(&self) -> bool { - *self == Sts::Sample19p5 - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_35p5(&self) -> bool { - *self == Sts::Sample35p5 - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_67p5(&self) -> bool { - *self == Sts::Sample67p5 - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_131p5(&self) -> bool { - *self == Sts::Sample131p5 - } -} -#[doc = "Field `STS` writer - Sample Time Select"] -pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; -impl<'a, REG> StsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn sample_3p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample3p5) - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_5p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample5p5) - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_7p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample7p5) - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_11p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample11p5) - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_19p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample19p5) - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_35p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample35p5) - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_67p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample67p5) - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_131p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample131p5) - } -} -#[doc = "Hardware Average Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Avgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Avgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Avgs { - type Ux = u8; -} -impl crate::IsEnum for Avgs {} -#[doc = "Field `AVGS` reader - Hardware Average Select"] -pub type AvgsR = crate::FieldReader; -impl AvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Avgs::NoAverage), - 1 => Some(Avgs::Average2), - 2 => Some(Avgs::Average4), - 3 => Some(Avgs::Average8), - 4 => Some(Avgs::Average16), - 5 => Some(Avgs::Average32), - 6 => Some(Avgs::Average64), - 7 => Some(Avgs::Average128), - 8 => Some(Avgs::Average256), - 9 => Some(Avgs::Average512), - 10 => Some(Avgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == Avgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == Avgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == Avgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == Avgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == Avgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == Avgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == Avgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == Avgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == Avgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == Avgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == Avgs::Average1024 - } -} -#[doc = "Field `AVGS` writer - Hardware Average Select"] -pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; -impl<'a, REG> AvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(Avgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(Avgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(Avgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(Avgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(Avgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(Avgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(Avgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(Avgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(Avgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(Avgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(Avgs::Average1024) - } -} -#[doc = "Loop Count Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loop { - #[doc = "0: Looping not enabled. Command executes 1 time."] - CmdExec1x = 0, - #[doc = "1: Loop 1 time. Command executes 2 times."] - CmdExec2x = 1, - #[doc = "2: Loop 2 times. Command executes 3 times."] - CmdExec3x = 2, - #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes3 = 3, - #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes4 = 4, - #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes5 = 5, - #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes6 = 6, - #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes7 = 7, - #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes8 = 8, - #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes9 = 9, - #[doc = "15: Loop 15 times. Command executes 16 times."] - CmdExec15x = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loop { - type Ux = u8; -} -impl crate::IsEnum for Loop {} -#[doc = "Field `LOOP` reader - Loop Count Select"] -pub type LoopR = crate::FieldReader; -impl LoopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loop::CmdExec1x), - 1 => Some(Loop::CmdExec2x), - 2 => Some(Loop::CmdExec3x), - 3 => Some(Loop::CmdExecutesCorrespondingTimes3), - 4 => Some(Loop::CmdExecutesCorrespondingTimes4), - 5 => Some(Loop::CmdExecutesCorrespondingTimes5), - 6 => Some(Loop::CmdExecutesCorrespondingTimes6), - 7 => Some(Loop::CmdExecutesCorrespondingTimes7), - 8 => Some(Loop::CmdExecutesCorrespondingTimes8), - 9 => Some(Loop::CmdExecutesCorrespondingTimes9), - 15 => Some(Loop::CmdExec15x), - _ => None, - } - } - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn is_cmd_exec_1x(&self) -> bool { - *self == Loop::CmdExec1x - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn is_cmd_exec_2x(&self) -> bool { - *self == Loop::CmdExec2x - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn is_cmd_exec_3x(&self) -> bool { - *self == Loop::CmdExec3x - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes3 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes4 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes5 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes6 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes7 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes8 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes9 - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn is_cmd_exec_15x(&self) -> bool { - *self == Loop::CmdExec15x - } -} -#[doc = "Field `LOOP` writer - Loop Count Select"] -pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; -impl<'a, REG> LoopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn cmd_exec_1x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec1x) - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn cmd_exec_2x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec2x) - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn cmd_exec_3x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec3x) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes3) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes4) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes5) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes6) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes7) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes8) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes9) - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn cmd_exec_15x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec15x) - } -} -#[doc = "Next Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Next { - #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NoNextCmdTerminateOnFinish = 0, - #[doc = "1: Select CMD1 command buffer register as next command."] - DoCmd1Next = 1, - #[doc = "2: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext2 = 2, - #[doc = "3: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext3 = 3, - #[doc = "4: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext4 = 4, - #[doc = "5: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext5 = 5, - #[doc = "6: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext6 = 6, - #[doc = "7: Select CMD7 command buffer register as next command."] - DoCmd7Next = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Next) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Next { - type Ux = u8; -} -impl crate::IsEnum for Next {} -#[doc = "Field `NEXT` reader - Next Command Select"] -pub type NextR = crate::FieldReader; -impl NextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Next { - match self.bits { - 0 => Next::NoNextCmdTerminateOnFinish, - 1 => Next::DoCmd1Next, - 2 => Next::DoCorrespondingCmdNext2, - 3 => Next::DoCorrespondingCmdNext3, - 4 => Next::DoCorrespondingCmdNext4, - 5 => Next::DoCorrespondingCmdNext5, - 6 => Next::DoCorrespondingCmdNext6, - 7 => Next::DoCmd7Next, - _ => unreachable!(), - } - } - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { - *self == Next::NoNextCmdTerminateOnFinish - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd1_next(&self) -> bool { - *self == Next::DoCmd1Next - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_2(&self) -> bool { - *self == Next::DoCorrespondingCmdNext2 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_3(&self) -> bool { - *self == Next::DoCorrespondingCmdNext3 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_4(&self) -> bool { - *self == Next::DoCorrespondingCmdNext4 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_5(&self) -> bool { - *self == Next::DoCorrespondingCmdNext5 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_6(&self) -> bool { - *self == Next::DoCorrespondingCmdNext6 - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd7_next(&self) -> bool { - *self == Next::DoCmd7Next - } -} -#[doc = "Field `NEXT` writer - Next Command Select"] -pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; -impl<'a, REG> NextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { - self.variant(Next::NoNextCmdTerminateOnFinish) - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd1_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd1Next) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext2) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext3) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext4) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext5) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext6) - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd7_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd7Next) - } -} -impl R { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&self) -> CmpenR { - CmpenR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&self) -> WaitTrigR { - WaitTrigR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&self) -> LwiR { - LwiR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&self) -> StsR { - StsR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&self) -> AvgsR { - AvgsR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&self) -> LoopR { - LoopR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&self) -> NextR { - NextR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&mut self) -> CmpenW { - CmpenW::new(self, 0) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&mut self) -> WaitTrigW { - WaitTrigW::new(self, 2) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&mut self) -> LwiW { - LwiW::new(self, 7) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&mut self) -> StsW { - StsW::new(self, 8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&mut self) -> AvgsW { - AvgsW::new(self, 12) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&mut self) -> LoopW { - LoopW::new(self, 16) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&mut self) -> NextW { - NextW::new(self, 24) - } -} -#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdh1Spec; -impl crate::RegisterSpec for Cmdh1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdh1::R`](R) reader structure"] -impl crate::Readable for Cmdh1Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdh1::W`](W) writer structure"] -impl crate::Writable for Cmdh1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDH1 to value 0"] -impl crate::Resettable for Cmdh1Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh2.rs b/mcxa276-pac/src/adc0/cmdh2.rs deleted file mode 100644 index 782af4a8c..000000000 --- a/mcxa276-pac/src/adc0/cmdh2.rs +++ /dev/null @@ -1,900 +0,0 @@ -#[doc = "Register `CMDH2` reader"] -pub type R = crate::R; -#[doc = "Register `CMDH2` writer"] -pub type W = crate::W; -#[doc = "Compare Function Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpen { - #[doc = "0: Compare disabled."] - DisabledAlwaysStoreResult = 0, - #[doc = "2: Compare enabled. Store on true."] - CompareResultStoreIfTrue = 2, - #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpen { - type Ux = u8; -} -impl crate::IsEnum for Cmpen {} -#[doc = "Field `CMPEN` reader - Compare Function Enable"] -pub type CmpenR = crate::FieldReader; -impl CmpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpen::DisabledAlwaysStoreResult), - 2 => Some(Cmpen::CompareResultStoreIfTrue), - 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), - _ => None, - } - } - #[doc = "Compare disabled."] - #[inline(always)] - pub fn is_disabled_always_store_result(&self) -> bool { - *self == Cmpen::DisabledAlwaysStoreResult - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn is_compare_result_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultStoreIfTrue - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue - } -} -#[doc = "Field `CMPEN` writer - Compare Function Enable"] -pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; -impl<'a, REG> CmpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Compare disabled."] - #[inline(always)] - pub fn disabled_always_store_result(self) -> &'a mut crate::W { - self.variant(Cmpen::DisabledAlwaysStoreResult) - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn compare_result_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultStoreIfTrue) - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) - } -} -#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WaitTrig { - #[doc = "0: This command will be automatically executed."] - Disabled = 0, - #[doc = "1: The active trigger must be asserted again before executing this command."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WaitTrig) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] -pub type WaitTrigR = crate::BitReader; -impl WaitTrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WaitTrig { - match self.bits { - false => WaitTrig::Disabled, - true => WaitTrig::Enabled, - } - } - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WaitTrig::Disabled - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WaitTrig::Enabled - } -} -#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] -pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; -impl<'a, REG> WaitTrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Disabled) - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Enabled) - } -} -#[doc = "Loop with Increment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lwi { - #[doc = "0: Auto channel increment disabled"] - Disabled = 0, - #[doc = "1: Auto channel increment enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lwi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LWI` reader - Loop with Increment"] -pub type LwiR = crate::BitReader; -impl LwiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lwi { - match self.bits { - false => Lwi::Disabled, - true => Lwi::Enabled, - } - } - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lwi::Disabled - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lwi::Enabled - } -} -#[doc = "Field `LWI` writer - Loop with Increment"] -pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; -impl<'a, REG> LwiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lwi::Disabled) - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lwi::Enabled) - } -} -#[doc = "Sample Time Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sts { - #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] - Sample3p5 = 0, - #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - Sample5p5 = 1, - #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - Sample7p5 = 2, - #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - Sample11p5 = 3, - #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - Sample19p5 = 4, - #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - Sample35p5 = 5, - #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - Sample67p5 = 6, - #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - Sample131p5 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sts) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sts { - type Ux = u8; -} -impl crate::IsEnum for Sts {} -#[doc = "Field `STS` reader - Sample Time Select"] -pub type StsR = crate::FieldReader; -impl StsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sts { - match self.bits { - 0 => Sts::Sample3p5, - 1 => Sts::Sample5p5, - 2 => Sts::Sample7p5, - 3 => Sts::Sample11p5, - 4 => Sts::Sample19p5, - 5 => Sts::Sample35p5, - 6 => Sts::Sample67p5, - 7 => Sts::Sample131p5, - _ => unreachable!(), - } - } - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn is_sample_3p5(&self) -> bool { - *self == Sts::Sample3p5 - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_5p5(&self) -> bool { - *self == Sts::Sample5p5 - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_7p5(&self) -> bool { - *self == Sts::Sample7p5 - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_11p5(&self) -> bool { - *self == Sts::Sample11p5 - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_19p5(&self) -> bool { - *self == Sts::Sample19p5 - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_35p5(&self) -> bool { - *self == Sts::Sample35p5 - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_67p5(&self) -> bool { - *self == Sts::Sample67p5 - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_131p5(&self) -> bool { - *self == Sts::Sample131p5 - } -} -#[doc = "Field `STS` writer - Sample Time Select"] -pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; -impl<'a, REG> StsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn sample_3p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample3p5) - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_5p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample5p5) - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_7p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample7p5) - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_11p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample11p5) - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_19p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample19p5) - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_35p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample35p5) - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_67p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample67p5) - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_131p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample131p5) - } -} -#[doc = "Hardware Average Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Avgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Avgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Avgs { - type Ux = u8; -} -impl crate::IsEnum for Avgs {} -#[doc = "Field `AVGS` reader - Hardware Average Select"] -pub type AvgsR = crate::FieldReader; -impl AvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Avgs::NoAverage), - 1 => Some(Avgs::Average2), - 2 => Some(Avgs::Average4), - 3 => Some(Avgs::Average8), - 4 => Some(Avgs::Average16), - 5 => Some(Avgs::Average32), - 6 => Some(Avgs::Average64), - 7 => Some(Avgs::Average128), - 8 => Some(Avgs::Average256), - 9 => Some(Avgs::Average512), - 10 => Some(Avgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == Avgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == Avgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == Avgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == Avgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == Avgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == Avgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == Avgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == Avgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == Avgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == Avgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == Avgs::Average1024 - } -} -#[doc = "Field `AVGS` writer - Hardware Average Select"] -pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; -impl<'a, REG> AvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(Avgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(Avgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(Avgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(Avgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(Avgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(Avgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(Avgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(Avgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(Avgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(Avgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(Avgs::Average1024) - } -} -#[doc = "Loop Count Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loop { - #[doc = "0: Looping not enabled. Command executes 1 time."] - CmdExec1x = 0, - #[doc = "1: Loop 1 time. Command executes 2 times."] - CmdExec2x = 1, - #[doc = "2: Loop 2 times. Command executes 3 times."] - CmdExec3x = 2, - #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes3 = 3, - #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes4 = 4, - #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes5 = 5, - #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes6 = 6, - #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes7 = 7, - #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes8 = 8, - #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes9 = 9, - #[doc = "15: Loop 15 times. Command executes 16 times."] - CmdExec15x = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loop { - type Ux = u8; -} -impl crate::IsEnum for Loop {} -#[doc = "Field `LOOP` reader - Loop Count Select"] -pub type LoopR = crate::FieldReader; -impl LoopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loop::CmdExec1x), - 1 => Some(Loop::CmdExec2x), - 2 => Some(Loop::CmdExec3x), - 3 => Some(Loop::CmdExecutesCorrespondingTimes3), - 4 => Some(Loop::CmdExecutesCorrespondingTimes4), - 5 => Some(Loop::CmdExecutesCorrespondingTimes5), - 6 => Some(Loop::CmdExecutesCorrespondingTimes6), - 7 => Some(Loop::CmdExecutesCorrespondingTimes7), - 8 => Some(Loop::CmdExecutesCorrespondingTimes8), - 9 => Some(Loop::CmdExecutesCorrespondingTimes9), - 15 => Some(Loop::CmdExec15x), - _ => None, - } - } - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn is_cmd_exec_1x(&self) -> bool { - *self == Loop::CmdExec1x - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn is_cmd_exec_2x(&self) -> bool { - *self == Loop::CmdExec2x - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn is_cmd_exec_3x(&self) -> bool { - *self == Loop::CmdExec3x - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes3 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes4 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes5 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes6 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes7 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes8 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes9 - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn is_cmd_exec_15x(&self) -> bool { - *self == Loop::CmdExec15x - } -} -#[doc = "Field `LOOP` writer - Loop Count Select"] -pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; -impl<'a, REG> LoopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn cmd_exec_1x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec1x) - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn cmd_exec_2x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec2x) - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn cmd_exec_3x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec3x) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes3) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes4) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes5) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes6) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes7) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes8) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes9) - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn cmd_exec_15x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec15x) - } -} -#[doc = "Next Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Next { - #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NoNextCmdTerminateOnFinish = 0, - #[doc = "1: Select CMD1 command buffer register as next command."] - DoCmd1Next = 1, - #[doc = "2: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext2 = 2, - #[doc = "3: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext3 = 3, - #[doc = "4: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext4 = 4, - #[doc = "5: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext5 = 5, - #[doc = "6: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext6 = 6, - #[doc = "7: Select CMD7 command buffer register as next command."] - DoCmd7Next = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Next) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Next { - type Ux = u8; -} -impl crate::IsEnum for Next {} -#[doc = "Field `NEXT` reader - Next Command Select"] -pub type NextR = crate::FieldReader; -impl NextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Next { - match self.bits { - 0 => Next::NoNextCmdTerminateOnFinish, - 1 => Next::DoCmd1Next, - 2 => Next::DoCorrespondingCmdNext2, - 3 => Next::DoCorrespondingCmdNext3, - 4 => Next::DoCorrespondingCmdNext4, - 5 => Next::DoCorrespondingCmdNext5, - 6 => Next::DoCorrespondingCmdNext6, - 7 => Next::DoCmd7Next, - _ => unreachable!(), - } - } - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { - *self == Next::NoNextCmdTerminateOnFinish - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd1_next(&self) -> bool { - *self == Next::DoCmd1Next - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_2(&self) -> bool { - *self == Next::DoCorrespondingCmdNext2 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_3(&self) -> bool { - *self == Next::DoCorrespondingCmdNext3 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_4(&self) -> bool { - *self == Next::DoCorrespondingCmdNext4 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_5(&self) -> bool { - *self == Next::DoCorrespondingCmdNext5 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_6(&self) -> bool { - *self == Next::DoCorrespondingCmdNext6 - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd7_next(&self) -> bool { - *self == Next::DoCmd7Next - } -} -#[doc = "Field `NEXT` writer - Next Command Select"] -pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; -impl<'a, REG> NextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { - self.variant(Next::NoNextCmdTerminateOnFinish) - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd1_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd1Next) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext2) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext3) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext4) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext5) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext6) - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd7_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd7Next) - } -} -impl R { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&self) -> CmpenR { - CmpenR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&self) -> WaitTrigR { - WaitTrigR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&self) -> LwiR { - LwiR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&self) -> StsR { - StsR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&self) -> AvgsR { - AvgsR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&self) -> LoopR { - LoopR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&self) -> NextR { - NextR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&mut self) -> CmpenW { - CmpenW::new(self, 0) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&mut self) -> WaitTrigW { - WaitTrigW::new(self, 2) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&mut self) -> LwiW { - LwiW::new(self, 7) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&mut self) -> StsW { - StsW::new(self, 8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&mut self) -> AvgsW { - AvgsW::new(self, 12) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&mut self) -> LoopW { - LoopW::new(self, 16) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&mut self) -> NextW { - NextW::new(self, 24) - } -} -#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdh2Spec; -impl crate::RegisterSpec for Cmdh2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdh2::R`](R) reader structure"] -impl crate::Readable for Cmdh2Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdh2::W`](W) writer structure"] -impl crate::Writable for Cmdh2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDH2 to value 0"] -impl crate::Resettable for Cmdh2Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh3.rs b/mcxa276-pac/src/adc0/cmdh3.rs deleted file mode 100644 index ad98b405f..000000000 --- a/mcxa276-pac/src/adc0/cmdh3.rs +++ /dev/null @@ -1,900 +0,0 @@ -#[doc = "Register `CMDH3` reader"] -pub type R = crate::R; -#[doc = "Register `CMDH3` writer"] -pub type W = crate::W; -#[doc = "Compare Function Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpen { - #[doc = "0: Compare disabled."] - DisabledAlwaysStoreResult = 0, - #[doc = "2: Compare enabled. Store on true."] - CompareResultStoreIfTrue = 2, - #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpen { - type Ux = u8; -} -impl crate::IsEnum for Cmpen {} -#[doc = "Field `CMPEN` reader - Compare Function Enable"] -pub type CmpenR = crate::FieldReader; -impl CmpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpen::DisabledAlwaysStoreResult), - 2 => Some(Cmpen::CompareResultStoreIfTrue), - 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), - _ => None, - } - } - #[doc = "Compare disabled."] - #[inline(always)] - pub fn is_disabled_always_store_result(&self) -> bool { - *self == Cmpen::DisabledAlwaysStoreResult - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn is_compare_result_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultStoreIfTrue - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue - } -} -#[doc = "Field `CMPEN` writer - Compare Function Enable"] -pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; -impl<'a, REG> CmpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Compare disabled."] - #[inline(always)] - pub fn disabled_always_store_result(self) -> &'a mut crate::W { - self.variant(Cmpen::DisabledAlwaysStoreResult) - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn compare_result_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultStoreIfTrue) - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) - } -} -#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WaitTrig { - #[doc = "0: This command will be automatically executed."] - Disabled = 0, - #[doc = "1: The active trigger must be asserted again before executing this command."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WaitTrig) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] -pub type WaitTrigR = crate::BitReader; -impl WaitTrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WaitTrig { - match self.bits { - false => WaitTrig::Disabled, - true => WaitTrig::Enabled, - } - } - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WaitTrig::Disabled - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WaitTrig::Enabled - } -} -#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] -pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; -impl<'a, REG> WaitTrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Disabled) - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Enabled) - } -} -#[doc = "Loop with Increment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lwi { - #[doc = "0: Auto channel increment disabled"] - Disabled = 0, - #[doc = "1: Auto channel increment enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lwi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LWI` reader - Loop with Increment"] -pub type LwiR = crate::BitReader; -impl LwiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lwi { - match self.bits { - false => Lwi::Disabled, - true => Lwi::Enabled, - } - } - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lwi::Disabled - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lwi::Enabled - } -} -#[doc = "Field `LWI` writer - Loop with Increment"] -pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; -impl<'a, REG> LwiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lwi::Disabled) - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lwi::Enabled) - } -} -#[doc = "Sample Time Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sts { - #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] - Sample3p5 = 0, - #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - Sample5p5 = 1, - #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - Sample7p5 = 2, - #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - Sample11p5 = 3, - #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - Sample19p5 = 4, - #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - Sample35p5 = 5, - #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - Sample67p5 = 6, - #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - Sample131p5 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sts) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sts { - type Ux = u8; -} -impl crate::IsEnum for Sts {} -#[doc = "Field `STS` reader - Sample Time Select"] -pub type StsR = crate::FieldReader; -impl StsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sts { - match self.bits { - 0 => Sts::Sample3p5, - 1 => Sts::Sample5p5, - 2 => Sts::Sample7p5, - 3 => Sts::Sample11p5, - 4 => Sts::Sample19p5, - 5 => Sts::Sample35p5, - 6 => Sts::Sample67p5, - 7 => Sts::Sample131p5, - _ => unreachable!(), - } - } - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn is_sample_3p5(&self) -> bool { - *self == Sts::Sample3p5 - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_5p5(&self) -> bool { - *self == Sts::Sample5p5 - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_7p5(&self) -> bool { - *self == Sts::Sample7p5 - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_11p5(&self) -> bool { - *self == Sts::Sample11p5 - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_19p5(&self) -> bool { - *self == Sts::Sample19p5 - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_35p5(&self) -> bool { - *self == Sts::Sample35p5 - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_67p5(&self) -> bool { - *self == Sts::Sample67p5 - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_131p5(&self) -> bool { - *self == Sts::Sample131p5 - } -} -#[doc = "Field `STS` writer - Sample Time Select"] -pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; -impl<'a, REG> StsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn sample_3p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample3p5) - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_5p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample5p5) - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_7p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample7p5) - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_11p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample11p5) - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_19p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample19p5) - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_35p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample35p5) - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_67p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample67p5) - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_131p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample131p5) - } -} -#[doc = "Hardware Average Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Avgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Avgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Avgs { - type Ux = u8; -} -impl crate::IsEnum for Avgs {} -#[doc = "Field `AVGS` reader - Hardware Average Select"] -pub type AvgsR = crate::FieldReader; -impl AvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Avgs::NoAverage), - 1 => Some(Avgs::Average2), - 2 => Some(Avgs::Average4), - 3 => Some(Avgs::Average8), - 4 => Some(Avgs::Average16), - 5 => Some(Avgs::Average32), - 6 => Some(Avgs::Average64), - 7 => Some(Avgs::Average128), - 8 => Some(Avgs::Average256), - 9 => Some(Avgs::Average512), - 10 => Some(Avgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == Avgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == Avgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == Avgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == Avgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == Avgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == Avgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == Avgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == Avgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == Avgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == Avgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == Avgs::Average1024 - } -} -#[doc = "Field `AVGS` writer - Hardware Average Select"] -pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; -impl<'a, REG> AvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(Avgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(Avgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(Avgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(Avgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(Avgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(Avgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(Avgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(Avgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(Avgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(Avgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(Avgs::Average1024) - } -} -#[doc = "Loop Count Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loop { - #[doc = "0: Looping not enabled. Command executes 1 time."] - CmdExec1x = 0, - #[doc = "1: Loop 1 time. Command executes 2 times."] - CmdExec2x = 1, - #[doc = "2: Loop 2 times. Command executes 3 times."] - CmdExec3x = 2, - #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes3 = 3, - #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes4 = 4, - #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes5 = 5, - #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes6 = 6, - #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes7 = 7, - #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes8 = 8, - #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes9 = 9, - #[doc = "15: Loop 15 times. Command executes 16 times."] - CmdExec15x = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loop { - type Ux = u8; -} -impl crate::IsEnum for Loop {} -#[doc = "Field `LOOP` reader - Loop Count Select"] -pub type LoopR = crate::FieldReader; -impl LoopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loop::CmdExec1x), - 1 => Some(Loop::CmdExec2x), - 2 => Some(Loop::CmdExec3x), - 3 => Some(Loop::CmdExecutesCorrespondingTimes3), - 4 => Some(Loop::CmdExecutesCorrespondingTimes4), - 5 => Some(Loop::CmdExecutesCorrespondingTimes5), - 6 => Some(Loop::CmdExecutesCorrespondingTimes6), - 7 => Some(Loop::CmdExecutesCorrespondingTimes7), - 8 => Some(Loop::CmdExecutesCorrespondingTimes8), - 9 => Some(Loop::CmdExecutesCorrespondingTimes9), - 15 => Some(Loop::CmdExec15x), - _ => None, - } - } - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn is_cmd_exec_1x(&self) -> bool { - *self == Loop::CmdExec1x - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn is_cmd_exec_2x(&self) -> bool { - *self == Loop::CmdExec2x - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn is_cmd_exec_3x(&self) -> bool { - *self == Loop::CmdExec3x - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes3 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes4 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes5 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes6 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes7 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes8 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes9 - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn is_cmd_exec_15x(&self) -> bool { - *self == Loop::CmdExec15x - } -} -#[doc = "Field `LOOP` writer - Loop Count Select"] -pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; -impl<'a, REG> LoopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn cmd_exec_1x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec1x) - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn cmd_exec_2x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec2x) - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn cmd_exec_3x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec3x) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes3) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes4) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes5) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes6) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes7) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes8) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes9) - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn cmd_exec_15x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec15x) - } -} -#[doc = "Next Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Next { - #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NoNextCmdTerminateOnFinish = 0, - #[doc = "1: Select CMD1 command buffer register as next command."] - DoCmd1Next = 1, - #[doc = "2: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext2 = 2, - #[doc = "3: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext3 = 3, - #[doc = "4: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext4 = 4, - #[doc = "5: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext5 = 5, - #[doc = "6: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext6 = 6, - #[doc = "7: Select CMD7 command buffer register as next command."] - DoCmd7Next = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Next) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Next { - type Ux = u8; -} -impl crate::IsEnum for Next {} -#[doc = "Field `NEXT` reader - Next Command Select"] -pub type NextR = crate::FieldReader; -impl NextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Next { - match self.bits { - 0 => Next::NoNextCmdTerminateOnFinish, - 1 => Next::DoCmd1Next, - 2 => Next::DoCorrespondingCmdNext2, - 3 => Next::DoCorrespondingCmdNext3, - 4 => Next::DoCorrespondingCmdNext4, - 5 => Next::DoCorrespondingCmdNext5, - 6 => Next::DoCorrespondingCmdNext6, - 7 => Next::DoCmd7Next, - _ => unreachable!(), - } - } - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { - *self == Next::NoNextCmdTerminateOnFinish - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd1_next(&self) -> bool { - *self == Next::DoCmd1Next - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_2(&self) -> bool { - *self == Next::DoCorrespondingCmdNext2 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_3(&self) -> bool { - *self == Next::DoCorrespondingCmdNext3 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_4(&self) -> bool { - *self == Next::DoCorrespondingCmdNext4 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_5(&self) -> bool { - *self == Next::DoCorrespondingCmdNext5 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_6(&self) -> bool { - *self == Next::DoCorrespondingCmdNext6 - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd7_next(&self) -> bool { - *self == Next::DoCmd7Next - } -} -#[doc = "Field `NEXT` writer - Next Command Select"] -pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; -impl<'a, REG> NextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { - self.variant(Next::NoNextCmdTerminateOnFinish) - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd1_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd1Next) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext2) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext3) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext4) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext5) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext6) - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd7_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd7Next) - } -} -impl R { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&self) -> CmpenR { - CmpenR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&self) -> WaitTrigR { - WaitTrigR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&self) -> LwiR { - LwiR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&self) -> StsR { - StsR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&self) -> AvgsR { - AvgsR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&self) -> LoopR { - LoopR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&self) -> NextR { - NextR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&mut self) -> CmpenW { - CmpenW::new(self, 0) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&mut self) -> WaitTrigW { - WaitTrigW::new(self, 2) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&mut self) -> LwiW { - LwiW::new(self, 7) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&mut self) -> StsW { - StsW::new(self, 8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&mut self) -> AvgsW { - AvgsW::new(self, 12) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&mut self) -> LoopW { - LoopW::new(self, 16) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&mut self) -> NextW { - NextW::new(self, 24) - } -} -#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdh3Spec; -impl crate::RegisterSpec for Cmdh3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdh3::R`](R) reader structure"] -impl crate::Readable for Cmdh3Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdh3::W`](W) writer structure"] -impl crate::Writable for Cmdh3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDH3 to value 0"] -impl crate::Resettable for Cmdh3Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh4.rs b/mcxa276-pac/src/adc0/cmdh4.rs deleted file mode 100644 index 56eb3de39..000000000 --- a/mcxa276-pac/src/adc0/cmdh4.rs +++ /dev/null @@ -1,900 +0,0 @@ -#[doc = "Register `CMDH4` reader"] -pub type R = crate::R; -#[doc = "Register `CMDH4` writer"] -pub type W = crate::W; -#[doc = "Compare Function Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpen { - #[doc = "0: Compare disabled."] - DisabledAlwaysStoreResult = 0, - #[doc = "2: Compare enabled. Store on true."] - CompareResultStoreIfTrue = 2, - #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpen { - type Ux = u8; -} -impl crate::IsEnum for Cmpen {} -#[doc = "Field `CMPEN` reader - Compare Function Enable"] -pub type CmpenR = crate::FieldReader; -impl CmpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpen::DisabledAlwaysStoreResult), - 2 => Some(Cmpen::CompareResultStoreIfTrue), - 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), - _ => None, - } - } - #[doc = "Compare disabled."] - #[inline(always)] - pub fn is_disabled_always_store_result(&self) -> bool { - *self == Cmpen::DisabledAlwaysStoreResult - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn is_compare_result_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultStoreIfTrue - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue - } -} -#[doc = "Field `CMPEN` writer - Compare Function Enable"] -pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; -impl<'a, REG> CmpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Compare disabled."] - #[inline(always)] - pub fn disabled_always_store_result(self) -> &'a mut crate::W { - self.variant(Cmpen::DisabledAlwaysStoreResult) - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn compare_result_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultStoreIfTrue) - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) - } -} -#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WaitTrig { - #[doc = "0: This command will be automatically executed."] - Disabled = 0, - #[doc = "1: The active trigger must be asserted again before executing this command."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WaitTrig) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] -pub type WaitTrigR = crate::BitReader; -impl WaitTrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WaitTrig { - match self.bits { - false => WaitTrig::Disabled, - true => WaitTrig::Enabled, - } - } - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WaitTrig::Disabled - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WaitTrig::Enabled - } -} -#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] -pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; -impl<'a, REG> WaitTrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Disabled) - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Enabled) - } -} -#[doc = "Loop with Increment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lwi { - #[doc = "0: Auto channel increment disabled"] - Disabled = 0, - #[doc = "1: Auto channel increment enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lwi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LWI` reader - Loop with Increment"] -pub type LwiR = crate::BitReader; -impl LwiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lwi { - match self.bits { - false => Lwi::Disabled, - true => Lwi::Enabled, - } - } - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lwi::Disabled - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lwi::Enabled - } -} -#[doc = "Field `LWI` writer - Loop with Increment"] -pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; -impl<'a, REG> LwiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lwi::Disabled) - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lwi::Enabled) - } -} -#[doc = "Sample Time Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sts { - #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] - Sample3p5 = 0, - #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - Sample5p5 = 1, - #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - Sample7p5 = 2, - #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - Sample11p5 = 3, - #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - Sample19p5 = 4, - #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - Sample35p5 = 5, - #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - Sample67p5 = 6, - #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - Sample131p5 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sts) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sts { - type Ux = u8; -} -impl crate::IsEnum for Sts {} -#[doc = "Field `STS` reader - Sample Time Select"] -pub type StsR = crate::FieldReader; -impl StsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sts { - match self.bits { - 0 => Sts::Sample3p5, - 1 => Sts::Sample5p5, - 2 => Sts::Sample7p5, - 3 => Sts::Sample11p5, - 4 => Sts::Sample19p5, - 5 => Sts::Sample35p5, - 6 => Sts::Sample67p5, - 7 => Sts::Sample131p5, - _ => unreachable!(), - } - } - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn is_sample_3p5(&self) -> bool { - *self == Sts::Sample3p5 - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_5p5(&self) -> bool { - *self == Sts::Sample5p5 - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_7p5(&self) -> bool { - *self == Sts::Sample7p5 - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_11p5(&self) -> bool { - *self == Sts::Sample11p5 - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_19p5(&self) -> bool { - *self == Sts::Sample19p5 - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_35p5(&self) -> bool { - *self == Sts::Sample35p5 - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_67p5(&self) -> bool { - *self == Sts::Sample67p5 - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_131p5(&self) -> bool { - *self == Sts::Sample131p5 - } -} -#[doc = "Field `STS` writer - Sample Time Select"] -pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; -impl<'a, REG> StsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn sample_3p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample3p5) - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_5p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample5p5) - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_7p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample7p5) - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_11p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample11p5) - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_19p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample19p5) - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_35p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample35p5) - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_67p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample67p5) - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_131p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample131p5) - } -} -#[doc = "Hardware Average Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Avgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Avgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Avgs { - type Ux = u8; -} -impl crate::IsEnum for Avgs {} -#[doc = "Field `AVGS` reader - Hardware Average Select"] -pub type AvgsR = crate::FieldReader; -impl AvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Avgs::NoAverage), - 1 => Some(Avgs::Average2), - 2 => Some(Avgs::Average4), - 3 => Some(Avgs::Average8), - 4 => Some(Avgs::Average16), - 5 => Some(Avgs::Average32), - 6 => Some(Avgs::Average64), - 7 => Some(Avgs::Average128), - 8 => Some(Avgs::Average256), - 9 => Some(Avgs::Average512), - 10 => Some(Avgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == Avgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == Avgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == Avgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == Avgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == Avgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == Avgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == Avgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == Avgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == Avgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == Avgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == Avgs::Average1024 - } -} -#[doc = "Field `AVGS` writer - Hardware Average Select"] -pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; -impl<'a, REG> AvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(Avgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(Avgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(Avgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(Avgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(Avgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(Avgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(Avgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(Avgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(Avgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(Avgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(Avgs::Average1024) - } -} -#[doc = "Loop Count Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loop { - #[doc = "0: Looping not enabled. Command executes 1 time."] - CmdExec1x = 0, - #[doc = "1: Loop 1 time. Command executes 2 times."] - CmdExec2x = 1, - #[doc = "2: Loop 2 times. Command executes 3 times."] - CmdExec3x = 2, - #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes3 = 3, - #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes4 = 4, - #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes5 = 5, - #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes6 = 6, - #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes7 = 7, - #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes8 = 8, - #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes9 = 9, - #[doc = "15: Loop 15 times. Command executes 16 times."] - CmdExec15x = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loop { - type Ux = u8; -} -impl crate::IsEnum for Loop {} -#[doc = "Field `LOOP` reader - Loop Count Select"] -pub type LoopR = crate::FieldReader; -impl LoopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loop::CmdExec1x), - 1 => Some(Loop::CmdExec2x), - 2 => Some(Loop::CmdExec3x), - 3 => Some(Loop::CmdExecutesCorrespondingTimes3), - 4 => Some(Loop::CmdExecutesCorrespondingTimes4), - 5 => Some(Loop::CmdExecutesCorrespondingTimes5), - 6 => Some(Loop::CmdExecutesCorrespondingTimes6), - 7 => Some(Loop::CmdExecutesCorrespondingTimes7), - 8 => Some(Loop::CmdExecutesCorrespondingTimes8), - 9 => Some(Loop::CmdExecutesCorrespondingTimes9), - 15 => Some(Loop::CmdExec15x), - _ => None, - } - } - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn is_cmd_exec_1x(&self) -> bool { - *self == Loop::CmdExec1x - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn is_cmd_exec_2x(&self) -> bool { - *self == Loop::CmdExec2x - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn is_cmd_exec_3x(&self) -> bool { - *self == Loop::CmdExec3x - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes3 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes4 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes5 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes6 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes7 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes8 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes9 - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn is_cmd_exec_15x(&self) -> bool { - *self == Loop::CmdExec15x - } -} -#[doc = "Field `LOOP` writer - Loop Count Select"] -pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; -impl<'a, REG> LoopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn cmd_exec_1x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec1x) - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn cmd_exec_2x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec2x) - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn cmd_exec_3x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec3x) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes3) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes4) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes5) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes6) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes7) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes8) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes9) - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn cmd_exec_15x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec15x) - } -} -#[doc = "Next Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Next { - #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NoNextCmdTerminateOnFinish = 0, - #[doc = "1: Select CMD1 command buffer register as next command."] - DoCmd1Next = 1, - #[doc = "2: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext2 = 2, - #[doc = "3: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext3 = 3, - #[doc = "4: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext4 = 4, - #[doc = "5: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext5 = 5, - #[doc = "6: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext6 = 6, - #[doc = "7: Select CMD7 command buffer register as next command."] - DoCmd7Next = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Next) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Next { - type Ux = u8; -} -impl crate::IsEnum for Next {} -#[doc = "Field `NEXT` reader - Next Command Select"] -pub type NextR = crate::FieldReader; -impl NextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Next { - match self.bits { - 0 => Next::NoNextCmdTerminateOnFinish, - 1 => Next::DoCmd1Next, - 2 => Next::DoCorrespondingCmdNext2, - 3 => Next::DoCorrespondingCmdNext3, - 4 => Next::DoCorrespondingCmdNext4, - 5 => Next::DoCorrespondingCmdNext5, - 6 => Next::DoCorrespondingCmdNext6, - 7 => Next::DoCmd7Next, - _ => unreachable!(), - } - } - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { - *self == Next::NoNextCmdTerminateOnFinish - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd1_next(&self) -> bool { - *self == Next::DoCmd1Next - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_2(&self) -> bool { - *self == Next::DoCorrespondingCmdNext2 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_3(&self) -> bool { - *self == Next::DoCorrespondingCmdNext3 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_4(&self) -> bool { - *self == Next::DoCorrespondingCmdNext4 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_5(&self) -> bool { - *self == Next::DoCorrespondingCmdNext5 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_6(&self) -> bool { - *self == Next::DoCorrespondingCmdNext6 - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd7_next(&self) -> bool { - *self == Next::DoCmd7Next - } -} -#[doc = "Field `NEXT` writer - Next Command Select"] -pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; -impl<'a, REG> NextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { - self.variant(Next::NoNextCmdTerminateOnFinish) - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd1_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd1Next) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext2) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext3) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext4) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext5) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext6) - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd7_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd7Next) - } -} -impl R { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&self) -> CmpenR { - CmpenR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&self) -> WaitTrigR { - WaitTrigR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&self) -> LwiR { - LwiR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&self) -> StsR { - StsR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&self) -> AvgsR { - AvgsR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&self) -> LoopR { - LoopR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&self) -> NextR { - NextR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&mut self) -> CmpenW { - CmpenW::new(self, 0) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&mut self) -> WaitTrigW { - WaitTrigW::new(self, 2) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&mut self) -> LwiW { - LwiW::new(self, 7) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&mut self) -> StsW { - StsW::new(self, 8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&mut self) -> AvgsW { - AvgsW::new(self, 12) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&mut self) -> LoopW { - LoopW::new(self, 16) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&mut self) -> NextW { - NextW::new(self, 24) - } -} -#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdh4Spec; -impl crate::RegisterSpec for Cmdh4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdh4::R`](R) reader structure"] -impl crate::Readable for Cmdh4Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdh4::W`](W) writer structure"] -impl crate::Writable for Cmdh4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDH4 to value 0"] -impl crate::Resettable for Cmdh4Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh5.rs b/mcxa276-pac/src/adc0/cmdh5.rs deleted file mode 100644 index eac28578c..000000000 --- a/mcxa276-pac/src/adc0/cmdh5.rs +++ /dev/null @@ -1,900 +0,0 @@ -#[doc = "Register `CMDH5` reader"] -pub type R = crate::R; -#[doc = "Register `CMDH5` writer"] -pub type W = crate::W; -#[doc = "Compare Function Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpen { - #[doc = "0: Compare disabled."] - DisabledAlwaysStoreResult = 0, - #[doc = "2: Compare enabled. Store on true."] - CompareResultStoreIfTrue = 2, - #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpen { - type Ux = u8; -} -impl crate::IsEnum for Cmpen {} -#[doc = "Field `CMPEN` reader - Compare Function Enable"] -pub type CmpenR = crate::FieldReader; -impl CmpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpen::DisabledAlwaysStoreResult), - 2 => Some(Cmpen::CompareResultStoreIfTrue), - 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), - _ => None, - } - } - #[doc = "Compare disabled."] - #[inline(always)] - pub fn is_disabled_always_store_result(&self) -> bool { - *self == Cmpen::DisabledAlwaysStoreResult - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn is_compare_result_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultStoreIfTrue - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue - } -} -#[doc = "Field `CMPEN` writer - Compare Function Enable"] -pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; -impl<'a, REG> CmpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Compare disabled."] - #[inline(always)] - pub fn disabled_always_store_result(self) -> &'a mut crate::W { - self.variant(Cmpen::DisabledAlwaysStoreResult) - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn compare_result_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultStoreIfTrue) - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) - } -} -#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WaitTrig { - #[doc = "0: This command will be automatically executed."] - Disabled = 0, - #[doc = "1: The active trigger must be asserted again before executing this command."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WaitTrig) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] -pub type WaitTrigR = crate::BitReader; -impl WaitTrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WaitTrig { - match self.bits { - false => WaitTrig::Disabled, - true => WaitTrig::Enabled, - } - } - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WaitTrig::Disabled - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WaitTrig::Enabled - } -} -#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] -pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; -impl<'a, REG> WaitTrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Disabled) - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Enabled) - } -} -#[doc = "Loop with Increment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lwi { - #[doc = "0: Auto channel increment disabled"] - Disabled = 0, - #[doc = "1: Auto channel increment enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lwi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LWI` reader - Loop with Increment"] -pub type LwiR = crate::BitReader; -impl LwiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lwi { - match self.bits { - false => Lwi::Disabled, - true => Lwi::Enabled, - } - } - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lwi::Disabled - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lwi::Enabled - } -} -#[doc = "Field `LWI` writer - Loop with Increment"] -pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; -impl<'a, REG> LwiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lwi::Disabled) - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lwi::Enabled) - } -} -#[doc = "Sample Time Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sts { - #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] - Sample3p5 = 0, - #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - Sample5p5 = 1, - #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - Sample7p5 = 2, - #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - Sample11p5 = 3, - #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - Sample19p5 = 4, - #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - Sample35p5 = 5, - #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - Sample67p5 = 6, - #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - Sample131p5 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sts) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sts { - type Ux = u8; -} -impl crate::IsEnum for Sts {} -#[doc = "Field `STS` reader - Sample Time Select"] -pub type StsR = crate::FieldReader; -impl StsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sts { - match self.bits { - 0 => Sts::Sample3p5, - 1 => Sts::Sample5p5, - 2 => Sts::Sample7p5, - 3 => Sts::Sample11p5, - 4 => Sts::Sample19p5, - 5 => Sts::Sample35p5, - 6 => Sts::Sample67p5, - 7 => Sts::Sample131p5, - _ => unreachable!(), - } - } - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn is_sample_3p5(&self) -> bool { - *self == Sts::Sample3p5 - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_5p5(&self) -> bool { - *self == Sts::Sample5p5 - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_7p5(&self) -> bool { - *self == Sts::Sample7p5 - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_11p5(&self) -> bool { - *self == Sts::Sample11p5 - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_19p5(&self) -> bool { - *self == Sts::Sample19p5 - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_35p5(&self) -> bool { - *self == Sts::Sample35p5 - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_67p5(&self) -> bool { - *self == Sts::Sample67p5 - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_131p5(&self) -> bool { - *self == Sts::Sample131p5 - } -} -#[doc = "Field `STS` writer - Sample Time Select"] -pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; -impl<'a, REG> StsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn sample_3p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample3p5) - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_5p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample5p5) - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_7p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample7p5) - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_11p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample11p5) - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_19p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample19p5) - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_35p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample35p5) - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_67p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample67p5) - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_131p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample131p5) - } -} -#[doc = "Hardware Average Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Avgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Avgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Avgs { - type Ux = u8; -} -impl crate::IsEnum for Avgs {} -#[doc = "Field `AVGS` reader - Hardware Average Select"] -pub type AvgsR = crate::FieldReader; -impl AvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Avgs::NoAverage), - 1 => Some(Avgs::Average2), - 2 => Some(Avgs::Average4), - 3 => Some(Avgs::Average8), - 4 => Some(Avgs::Average16), - 5 => Some(Avgs::Average32), - 6 => Some(Avgs::Average64), - 7 => Some(Avgs::Average128), - 8 => Some(Avgs::Average256), - 9 => Some(Avgs::Average512), - 10 => Some(Avgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == Avgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == Avgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == Avgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == Avgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == Avgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == Avgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == Avgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == Avgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == Avgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == Avgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == Avgs::Average1024 - } -} -#[doc = "Field `AVGS` writer - Hardware Average Select"] -pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; -impl<'a, REG> AvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(Avgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(Avgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(Avgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(Avgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(Avgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(Avgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(Avgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(Avgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(Avgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(Avgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(Avgs::Average1024) - } -} -#[doc = "Loop Count Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loop { - #[doc = "0: Looping not enabled. Command executes 1 time."] - CmdExec1x = 0, - #[doc = "1: Loop 1 time. Command executes 2 times."] - CmdExec2x = 1, - #[doc = "2: Loop 2 times. Command executes 3 times."] - CmdExec3x = 2, - #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes3 = 3, - #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes4 = 4, - #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes5 = 5, - #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes6 = 6, - #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes7 = 7, - #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes8 = 8, - #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes9 = 9, - #[doc = "15: Loop 15 times. Command executes 16 times."] - CmdExec15x = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loop { - type Ux = u8; -} -impl crate::IsEnum for Loop {} -#[doc = "Field `LOOP` reader - Loop Count Select"] -pub type LoopR = crate::FieldReader; -impl LoopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loop::CmdExec1x), - 1 => Some(Loop::CmdExec2x), - 2 => Some(Loop::CmdExec3x), - 3 => Some(Loop::CmdExecutesCorrespondingTimes3), - 4 => Some(Loop::CmdExecutesCorrespondingTimes4), - 5 => Some(Loop::CmdExecutesCorrespondingTimes5), - 6 => Some(Loop::CmdExecutesCorrespondingTimes6), - 7 => Some(Loop::CmdExecutesCorrespondingTimes7), - 8 => Some(Loop::CmdExecutesCorrespondingTimes8), - 9 => Some(Loop::CmdExecutesCorrespondingTimes9), - 15 => Some(Loop::CmdExec15x), - _ => None, - } - } - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn is_cmd_exec_1x(&self) -> bool { - *self == Loop::CmdExec1x - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn is_cmd_exec_2x(&self) -> bool { - *self == Loop::CmdExec2x - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn is_cmd_exec_3x(&self) -> bool { - *self == Loop::CmdExec3x - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes3 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes4 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes5 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes6 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes7 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes8 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes9 - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn is_cmd_exec_15x(&self) -> bool { - *self == Loop::CmdExec15x - } -} -#[doc = "Field `LOOP` writer - Loop Count Select"] -pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; -impl<'a, REG> LoopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn cmd_exec_1x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec1x) - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn cmd_exec_2x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec2x) - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn cmd_exec_3x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec3x) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes3) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes4) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes5) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes6) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes7) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes8) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes9) - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn cmd_exec_15x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec15x) - } -} -#[doc = "Next Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Next { - #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NoNextCmdTerminateOnFinish = 0, - #[doc = "1: Select CMD1 command buffer register as next command."] - DoCmd1Next = 1, - #[doc = "2: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext2 = 2, - #[doc = "3: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext3 = 3, - #[doc = "4: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext4 = 4, - #[doc = "5: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext5 = 5, - #[doc = "6: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext6 = 6, - #[doc = "7: Select CMD7 command buffer register as next command."] - DoCmd7Next = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Next) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Next { - type Ux = u8; -} -impl crate::IsEnum for Next {} -#[doc = "Field `NEXT` reader - Next Command Select"] -pub type NextR = crate::FieldReader; -impl NextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Next { - match self.bits { - 0 => Next::NoNextCmdTerminateOnFinish, - 1 => Next::DoCmd1Next, - 2 => Next::DoCorrespondingCmdNext2, - 3 => Next::DoCorrespondingCmdNext3, - 4 => Next::DoCorrespondingCmdNext4, - 5 => Next::DoCorrespondingCmdNext5, - 6 => Next::DoCorrespondingCmdNext6, - 7 => Next::DoCmd7Next, - _ => unreachable!(), - } - } - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { - *self == Next::NoNextCmdTerminateOnFinish - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd1_next(&self) -> bool { - *self == Next::DoCmd1Next - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_2(&self) -> bool { - *self == Next::DoCorrespondingCmdNext2 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_3(&self) -> bool { - *self == Next::DoCorrespondingCmdNext3 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_4(&self) -> bool { - *self == Next::DoCorrespondingCmdNext4 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_5(&self) -> bool { - *self == Next::DoCorrespondingCmdNext5 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_6(&self) -> bool { - *self == Next::DoCorrespondingCmdNext6 - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd7_next(&self) -> bool { - *self == Next::DoCmd7Next - } -} -#[doc = "Field `NEXT` writer - Next Command Select"] -pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; -impl<'a, REG> NextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { - self.variant(Next::NoNextCmdTerminateOnFinish) - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd1_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd1Next) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext2) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext3) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext4) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext5) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext6) - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd7_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd7Next) - } -} -impl R { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&self) -> CmpenR { - CmpenR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&self) -> WaitTrigR { - WaitTrigR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&self) -> LwiR { - LwiR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&self) -> StsR { - StsR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&self) -> AvgsR { - AvgsR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&self) -> LoopR { - LoopR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&self) -> NextR { - NextR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&mut self) -> CmpenW { - CmpenW::new(self, 0) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&mut self) -> WaitTrigW { - WaitTrigW::new(self, 2) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&mut self) -> LwiW { - LwiW::new(self, 7) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&mut self) -> StsW { - StsW::new(self, 8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&mut self) -> AvgsW { - AvgsW::new(self, 12) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&mut self) -> LoopW { - LoopW::new(self, 16) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&mut self) -> NextW { - NextW::new(self, 24) - } -} -#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdh5Spec; -impl crate::RegisterSpec for Cmdh5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdh5::R`](R) reader structure"] -impl crate::Readable for Cmdh5Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdh5::W`](W) writer structure"] -impl crate::Writable for Cmdh5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDH5 to value 0"] -impl crate::Resettable for Cmdh5Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh6.rs b/mcxa276-pac/src/adc0/cmdh6.rs deleted file mode 100644 index c1e7d09a6..000000000 --- a/mcxa276-pac/src/adc0/cmdh6.rs +++ /dev/null @@ -1,900 +0,0 @@ -#[doc = "Register `CMDH6` reader"] -pub type R = crate::R; -#[doc = "Register `CMDH6` writer"] -pub type W = crate::W; -#[doc = "Compare Function Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpen { - #[doc = "0: Compare disabled."] - DisabledAlwaysStoreResult = 0, - #[doc = "2: Compare enabled. Store on true."] - CompareResultStoreIfTrue = 2, - #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpen { - type Ux = u8; -} -impl crate::IsEnum for Cmpen {} -#[doc = "Field `CMPEN` reader - Compare Function Enable"] -pub type CmpenR = crate::FieldReader; -impl CmpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpen::DisabledAlwaysStoreResult), - 2 => Some(Cmpen::CompareResultStoreIfTrue), - 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), - _ => None, - } - } - #[doc = "Compare disabled."] - #[inline(always)] - pub fn is_disabled_always_store_result(&self) -> bool { - *self == Cmpen::DisabledAlwaysStoreResult - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn is_compare_result_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultStoreIfTrue - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue - } -} -#[doc = "Field `CMPEN` writer - Compare Function Enable"] -pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; -impl<'a, REG> CmpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Compare disabled."] - #[inline(always)] - pub fn disabled_always_store_result(self) -> &'a mut crate::W { - self.variant(Cmpen::DisabledAlwaysStoreResult) - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn compare_result_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultStoreIfTrue) - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) - } -} -#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WaitTrig { - #[doc = "0: This command will be automatically executed."] - Disabled = 0, - #[doc = "1: The active trigger must be asserted again before executing this command."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WaitTrig) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] -pub type WaitTrigR = crate::BitReader; -impl WaitTrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WaitTrig { - match self.bits { - false => WaitTrig::Disabled, - true => WaitTrig::Enabled, - } - } - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WaitTrig::Disabled - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WaitTrig::Enabled - } -} -#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] -pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; -impl<'a, REG> WaitTrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Disabled) - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Enabled) - } -} -#[doc = "Loop with Increment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lwi { - #[doc = "0: Auto channel increment disabled"] - Disabled = 0, - #[doc = "1: Auto channel increment enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lwi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LWI` reader - Loop with Increment"] -pub type LwiR = crate::BitReader; -impl LwiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lwi { - match self.bits { - false => Lwi::Disabled, - true => Lwi::Enabled, - } - } - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lwi::Disabled - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lwi::Enabled - } -} -#[doc = "Field `LWI` writer - Loop with Increment"] -pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; -impl<'a, REG> LwiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lwi::Disabled) - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lwi::Enabled) - } -} -#[doc = "Sample Time Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sts { - #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] - Sample3p5 = 0, - #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - Sample5p5 = 1, - #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - Sample7p5 = 2, - #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - Sample11p5 = 3, - #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - Sample19p5 = 4, - #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - Sample35p5 = 5, - #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - Sample67p5 = 6, - #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - Sample131p5 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sts) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sts { - type Ux = u8; -} -impl crate::IsEnum for Sts {} -#[doc = "Field `STS` reader - Sample Time Select"] -pub type StsR = crate::FieldReader; -impl StsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sts { - match self.bits { - 0 => Sts::Sample3p5, - 1 => Sts::Sample5p5, - 2 => Sts::Sample7p5, - 3 => Sts::Sample11p5, - 4 => Sts::Sample19p5, - 5 => Sts::Sample35p5, - 6 => Sts::Sample67p5, - 7 => Sts::Sample131p5, - _ => unreachable!(), - } - } - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn is_sample_3p5(&self) -> bool { - *self == Sts::Sample3p5 - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_5p5(&self) -> bool { - *self == Sts::Sample5p5 - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_7p5(&self) -> bool { - *self == Sts::Sample7p5 - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_11p5(&self) -> bool { - *self == Sts::Sample11p5 - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_19p5(&self) -> bool { - *self == Sts::Sample19p5 - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_35p5(&self) -> bool { - *self == Sts::Sample35p5 - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_67p5(&self) -> bool { - *self == Sts::Sample67p5 - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_131p5(&self) -> bool { - *self == Sts::Sample131p5 - } -} -#[doc = "Field `STS` writer - Sample Time Select"] -pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; -impl<'a, REG> StsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn sample_3p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample3p5) - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_5p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample5p5) - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_7p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample7p5) - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_11p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample11p5) - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_19p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample19p5) - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_35p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample35p5) - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_67p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample67p5) - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_131p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample131p5) - } -} -#[doc = "Hardware Average Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Avgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Avgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Avgs { - type Ux = u8; -} -impl crate::IsEnum for Avgs {} -#[doc = "Field `AVGS` reader - Hardware Average Select"] -pub type AvgsR = crate::FieldReader; -impl AvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Avgs::NoAverage), - 1 => Some(Avgs::Average2), - 2 => Some(Avgs::Average4), - 3 => Some(Avgs::Average8), - 4 => Some(Avgs::Average16), - 5 => Some(Avgs::Average32), - 6 => Some(Avgs::Average64), - 7 => Some(Avgs::Average128), - 8 => Some(Avgs::Average256), - 9 => Some(Avgs::Average512), - 10 => Some(Avgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == Avgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == Avgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == Avgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == Avgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == Avgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == Avgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == Avgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == Avgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == Avgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == Avgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == Avgs::Average1024 - } -} -#[doc = "Field `AVGS` writer - Hardware Average Select"] -pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; -impl<'a, REG> AvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(Avgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(Avgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(Avgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(Avgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(Avgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(Avgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(Avgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(Avgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(Avgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(Avgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(Avgs::Average1024) - } -} -#[doc = "Loop Count Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loop { - #[doc = "0: Looping not enabled. Command executes 1 time."] - CmdExec1x = 0, - #[doc = "1: Loop 1 time. Command executes 2 times."] - CmdExec2x = 1, - #[doc = "2: Loop 2 times. Command executes 3 times."] - CmdExec3x = 2, - #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes3 = 3, - #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes4 = 4, - #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes5 = 5, - #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes6 = 6, - #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes7 = 7, - #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes8 = 8, - #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes9 = 9, - #[doc = "15: Loop 15 times. Command executes 16 times."] - CmdExec15x = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loop { - type Ux = u8; -} -impl crate::IsEnum for Loop {} -#[doc = "Field `LOOP` reader - Loop Count Select"] -pub type LoopR = crate::FieldReader; -impl LoopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loop::CmdExec1x), - 1 => Some(Loop::CmdExec2x), - 2 => Some(Loop::CmdExec3x), - 3 => Some(Loop::CmdExecutesCorrespondingTimes3), - 4 => Some(Loop::CmdExecutesCorrespondingTimes4), - 5 => Some(Loop::CmdExecutesCorrespondingTimes5), - 6 => Some(Loop::CmdExecutesCorrespondingTimes6), - 7 => Some(Loop::CmdExecutesCorrespondingTimes7), - 8 => Some(Loop::CmdExecutesCorrespondingTimes8), - 9 => Some(Loop::CmdExecutesCorrespondingTimes9), - 15 => Some(Loop::CmdExec15x), - _ => None, - } - } - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn is_cmd_exec_1x(&self) -> bool { - *self == Loop::CmdExec1x - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn is_cmd_exec_2x(&self) -> bool { - *self == Loop::CmdExec2x - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn is_cmd_exec_3x(&self) -> bool { - *self == Loop::CmdExec3x - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes3 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes4 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes5 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes6 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes7 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes8 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes9 - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn is_cmd_exec_15x(&self) -> bool { - *self == Loop::CmdExec15x - } -} -#[doc = "Field `LOOP` writer - Loop Count Select"] -pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; -impl<'a, REG> LoopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn cmd_exec_1x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec1x) - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn cmd_exec_2x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec2x) - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn cmd_exec_3x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec3x) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes3) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes4) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes5) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes6) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes7) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes8) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes9) - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn cmd_exec_15x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec15x) - } -} -#[doc = "Next Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Next { - #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NoNextCmdTerminateOnFinish = 0, - #[doc = "1: Select CMD1 command buffer register as next command."] - DoCmd1Next = 1, - #[doc = "2: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext2 = 2, - #[doc = "3: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext3 = 3, - #[doc = "4: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext4 = 4, - #[doc = "5: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext5 = 5, - #[doc = "6: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext6 = 6, - #[doc = "7: Select CMD7 command buffer register as next command."] - DoCmd7Next = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Next) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Next { - type Ux = u8; -} -impl crate::IsEnum for Next {} -#[doc = "Field `NEXT` reader - Next Command Select"] -pub type NextR = crate::FieldReader; -impl NextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Next { - match self.bits { - 0 => Next::NoNextCmdTerminateOnFinish, - 1 => Next::DoCmd1Next, - 2 => Next::DoCorrespondingCmdNext2, - 3 => Next::DoCorrespondingCmdNext3, - 4 => Next::DoCorrespondingCmdNext4, - 5 => Next::DoCorrespondingCmdNext5, - 6 => Next::DoCorrespondingCmdNext6, - 7 => Next::DoCmd7Next, - _ => unreachable!(), - } - } - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { - *self == Next::NoNextCmdTerminateOnFinish - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd1_next(&self) -> bool { - *self == Next::DoCmd1Next - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_2(&self) -> bool { - *self == Next::DoCorrespondingCmdNext2 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_3(&self) -> bool { - *self == Next::DoCorrespondingCmdNext3 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_4(&self) -> bool { - *self == Next::DoCorrespondingCmdNext4 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_5(&self) -> bool { - *self == Next::DoCorrespondingCmdNext5 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_6(&self) -> bool { - *self == Next::DoCorrespondingCmdNext6 - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd7_next(&self) -> bool { - *self == Next::DoCmd7Next - } -} -#[doc = "Field `NEXT` writer - Next Command Select"] -pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; -impl<'a, REG> NextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { - self.variant(Next::NoNextCmdTerminateOnFinish) - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd1_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd1Next) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext2) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext3) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext4) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext5) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext6) - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd7_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd7Next) - } -} -impl R { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&self) -> CmpenR { - CmpenR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&self) -> WaitTrigR { - WaitTrigR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&self) -> LwiR { - LwiR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&self) -> StsR { - StsR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&self) -> AvgsR { - AvgsR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&self) -> LoopR { - LoopR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&self) -> NextR { - NextR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&mut self) -> CmpenW { - CmpenW::new(self, 0) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&mut self) -> WaitTrigW { - WaitTrigW::new(self, 2) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&mut self) -> LwiW { - LwiW::new(self, 7) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&mut self) -> StsW { - StsW::new(self, 8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&mut self) -> AvgsW { - AvgsW::new(self, 12) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&mut self) -> LoopW { - LoopW::new(self, 16) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&mut self) -> NextW { - NextW::new(self, 24) - } -} -#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdh6Spec; -impl crate::RegisterSpec for Cmdh6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdh6::R`](R) reader structure"] -impl crate::Readable for Cmdh6Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdh6::W`](W) writer structure"] -impl crate::Writable for Cmdh6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDH6 to value 0"] -impl crate::Resettable for Cmdh6Spec {} diff --git a/mcxa276-pac/src/adc0/cmdh7.rs b/mcxa276-pac/src/adc0/cmdh7.rs deleted file mode 100644 index 696d7fdbd..000000000 --- a/mcxa276-pac/src/adc0/cmdh7.rs +++ /dev/null @@ -1,900 +0,0 @@ -#[doc = "Register `CMDH7` reader"] -pub type R = crate::R; -#[doc = "Register `CMDH7` writer"] -pub type W = crate::W; -#[doc = "Compare Function Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpen { - #[doc = "0: Compare disabled."] - DisabledAlwaysStoreResult = 0, - #[doc = "2: Compare enabled. Store on true."] - CompareResultStoreIfTrue = 2, - #[doc = "3: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - CompareResultKeepConvertingUntilTrueStoreIfTrue = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpen { - type Ux = u8; -} -impl crate::IsEnum for Cmpen {} -#[doc = "Field `CMPEN` reader - Compare Function Enable"] -pub type CmpenR = crate::FieldReader; -impl CmpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpen::DisabledAlwaysStoreResult), - 2 => Some(Cmpen::CompareResultStoreIfTrue), - 3 => Some(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue), - _ => None, - } - } - #[doc = "Compare disabled."] - #[inline(always)] - pub fn is_disabled_always_store_result(&self) -> bool { - *self == Cmpen::DisabledAlwaysStoreResult - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn is_compare_result_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultStoreIfTrue - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn is_compare_result_keep_converting_until_true_store_if_true(&self) -> bool { - *self == Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue - } -} -#[doc = "Field `CMPEN` writer - Compare Function Enable"] -pub type CmpenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cmpen>; -impl<'a, REG> CmpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Compare disabled."] - #[inline(always)] - pub fn disabled_always_store_result(self) -> &'a mut crate::W { - self.variant(Cmpen::DisabledAlwaysStoreResult) - } - #[doc = "Compare enabled. Store on true."] - #[inline(always)] - pub fn compare_result_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultStoreIfTrue) - } - #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - #[inline(always)] - pub fn compare_result_keep_converting_until_true_store_if_true(self) -> &'a mut crate::W { - self.variant(Cmpen::CompareResultKeepConvertingUntilTrueStoreIfTrue) - } -} -#[doc = "Wait for Trigger Assertion before Execution.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WaitTrig { - #[doc = "0: This command will be automatically executed."] - Disabled = 0, - #[doc = "1: The active trigger must be asserted again before executing this command."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WaitTrig) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAIT_TRIG` reader - Wait for Trigger Assertion before Execution."] -pub type WaitTrigR = crate::BitReader; -impl WaitTrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WaitTrig { - match self.bits { - false => WaitTrig::Disabled, - true => WaitTrig::Enabled, - } - } - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WaitTrig::Disabled - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WaitTrig::Enabled - } -} -#[doc = "Field `WAIT_TRIG` writer - Wait for Trigger Assertion before Execution."] -pub type WaitTrigW<'a, REG> = crate::BitWriter<'a, REG, WaitTrig>; -impl<'a, REG> WaitTrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This command will be automatically executed."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Disabled) - } - #[doc = "The active trigger must be asserted again before executing this command."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WaitTrig::Enabled) - } -} -#[doc = "Loop with Increment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lwi { - #[doc = "0: Auto channel increment disabled"] - Disabled = 0, - #[doc = "1: Auto channel increment enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lwi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LWI` reader - Loop with Increment"] -pub type LwiR = crate::BitReader; -impl LwiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lwi { - match self.bits { - false => Lwi::Disabled, - true => Lwi::Enabled, - } - } - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lwi::Disabled - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lwi::Enabled - } -} -#[doc = "Field `LWI` writer - Loop with Increment"] -pub type LwiW<'a, REG> = crate::BitWriter<'a, REG, Lwi>; -impl<'a, REG> LwiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Auto channel increment disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lwi::Disabled) - } - #[doc = "Auto channel increment enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lwi::Enabled) - } -} -#[doc = "Sample Time Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sts { - #[doc = "0: Minimum sample time of 3.5 ADCK cycles."] - Sample3p5 = 0, - #[doc = "1: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - Sample5p5 = 1, - #[doc = "2: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - Sample7p5 = 2, - #[doc = "3: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - Sample11p5 = 3, - #[doc = "4: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - Sample19p5 = 4, - #[doc = "5: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - Sample35p5 = 5, - #[doc = "6: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - Sample67p5 = 6, - #[doc = "7: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - Sample131p5 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sts) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sts { - type Ux = u8; -} -impl crate::IsEnum for Sts {} -#[doc = "Field `STS` reader - Sample Time Select"] -pub type StsR = crate::FieldReader; -impl StsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sts { - match self.bits { - 0 => Sts::Sample3p5, - 1 => Sts::Sample5p5, - 2 => Sts::Sample7p5, - 3 => Sts::Sample11p5, - 4 => Sts::Sample19p5, - 5 => Sts::Sample35p5, - 6 => Sts::Sample67p5, - 7 => Sts::Sample131p5, - _ => unreachable!(), - } - } - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn is_sample_3p5(&self) -> bool { - *self == Sts::Sample3p5 - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_5p5(&self) -> bool { - *self == Sts::Sample5p5 - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_7p5(&self) -> bool { - *self == Sts::Sample7p5 - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_11p5(&self) -> bool { - *self == Sts::Sample11p5 - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_19p5(&self) -> bool { - *self == Sts::Sample19p5 - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_35p5(&self) -> bool { - *self == Sts::Sample35p5 - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_67p5(&self) -> bool { - *self == Sts::Sample67p5 - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn is_sample_131p5(&self) -> bool { - *self == Sts::Sample131p5 - } -} -#[doc = "Field `STS` writer - Sample Time Select"] -pub type StsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sts, crate::Safe>; -impl<'a, REG> StsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Minimum sample time of 3.5 ADCK cycles."] - #[inline(always)] - pub fn sample_3p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample3p5) - } - #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_5p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample5p5) - } - #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_7p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample7p5) - } - #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_11p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample11p5) - } - #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_19p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample19p5) - } - #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_35p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample35p5) - } - #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_67p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample67p5) - } - #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - #[inline(always)] - pub fn sample_131p5(self) -> &'a mut crate::W { - self.variant(Sts::Sample131p5) - } -} -#[doc = "Hardware Average Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Avgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Avgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Avgs { - type Ux = u8; -} -impl crate::IsEnum for Avgs {} -#[doc = "Field `AVGS` reader - Hardware Average Select"] -pub type AvgsR = crate::FieldReader; -impl AvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Avgs::NoAverage), - 1 => Some(Avgs::Average2), - 2 => Some(Avgs::Average4), - 3 => Some(Avgs::Average8), - 4 => Some(Avgs::Average16), - 5 => Some(Avgs::Average32), - 6 => Some(Avgs::Average64), - 7 => Some(Avgs::Average128), - 8 => Some(Avgs::Average256), - 9 => Some(Avgs::Average512), - 10 => Some(Avgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == Avgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == Avgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == Avgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == Avgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == Avgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == Avgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == Avgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == Avgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == Avgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == Avgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == Avgs::Average1024 - } -} -#[doc = "Field `AVGS` writer - Hardware Average Select"] -pub type AvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Avgs>; -impl<'a, REG> AvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(Avgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(Avgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(Avgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(Avgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(Avgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(Avgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(Avgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(Avgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(Avgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(Avgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(Avgs::Average1024) - } -} -#[doc = "Loop Count Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loop { - #[doc = "0: Looping not enabled. Command executes 1 time."] - CmdExec1x = 0, - #[doc = "1: Loop 1 time. Command executes 2 times."] - CmdExec2x = 1, - #[doc = "2: Loop 2 times. Command executes 3 times."] - CmdExec3x = 2, - #[doc = "3: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes3 = 3, - #[doc = "4: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes4 = 4, - #[doc = "5: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes5 = 5, - #[doc = "6: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes6 = 6, - #[doc = "7: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes7 = 7, - #[doc = "8: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes8 = 8, - #[doc = "9: Loop corresponding number of times. Command executes LOOP+1 times."] - CmdExecutesCorrespondingTimes9 = 9, - #[doc = "15: Loop 15 times. Command executes 16 times."] - CmdExec15x = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loop { - type Ux = u8; -} -impl crate::IsEnum for Loop {} -#[doc = "Field `LOOP` reader - Loop Count Select"] -pub type LoopR = crate::FieldReader; -impl LoopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loop::CmdExec1x), - 1 => Some(Loop::CmdExec2x), - 2 => Some(Loop::CmdExec3x), - 3 => Some(Loop::CmdExecutesCorrespondingTimes3), - 4 => Some(Loop::CmdExecutesCorrespondingTimes4), - 5 => Some(Loop::CmdExecutesCorrespondingTimes5), - 6 => Some(Loop::CmdExecutesCorrespondingTimes6), - 7 => Some(Loop::CmdExecutesCorrespondingTimes7), - 8 => Some(Loop::CmdExecutesCorrespondingTimes8), - 9 => Some(Loop::CmdExecutesCorrespondingTimes9), - 15 => Some(Loop::CmdExec15x), - _ => None, - } - } - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn is_cmd_exec_1x(&self) -> bool { - *self == Loop::CmdExec1x - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn is_cmd_exec_2x(&self) -> bool { - *self == Loop::CmdExec2x - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn is_cmd_exec_3x(&self) -> bool { - *self == Loop::CmdExec3x - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_3(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes3 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_4(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes4 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_5(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes5 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_6(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes6 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_7(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes7 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_8(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes8 - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn is_cmd_executes_corresponding_times_9(&self) -> bool { - *self == Loop::CmdExecutesCorrespondingTimes9 - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn is_cmd_exec_15x(&self) -> bool { - *self == Loop::CmdExec15x - } -} -#[doc = "Field `LOOP` writer - Loop Count Select"] -pub type LoopW<'a, REG> = crate::FieldWriter<'a, REG, 4, Loop>; -impl<'a, REG> LoopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Looping not enabled. Command executes 1 time."] - #[inline(always)] - pub fn cmd_exec_1x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec1x) - } - #[doc = "Loop 1 time. Command executes 2 times."] - #[inline(always)] - pub fn cmd_exec_2x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec2x) - } - #[doc = "Loop 2 times. Command executes 3 times."] - #[inline(always)] - pub fn cmd_exec_3x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec3x) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_3(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes3) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_4(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes4) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_5(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes5) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_6(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes6) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_7(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes7) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_8(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes8) - } - #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - #[inline(always)] - pub fn cmd_executes_corresponding_times_9(self) -> &'a mut crate::W { - self.variant(Loop::CmdExecutesCorrespondingTimes9) - } - #[doc = "Loop 15 times. Command executes 16 times."] - #[inline(always)] - pub fn cmd_exec_15x(self) -> &'a mut crate::W { - self.variant(Loop::CmdExec15x) - } -} -#[doc = "Next Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Next { - #[doc = "0: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NoNextCmdTerminateOnFinish = 0, - #[doc = "1: Select CMD1 command buffer register as next command."] - DoCmd1Next = 1, - #[doc = "2: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext2 = 2, - #[doc = "3: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext3 = 3, - #[doc = "4: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext4 = 4, - #[doc = "5: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext5 = 5, - #[doc = "6: Select corresponding CMD command buffer register as next command"] - DoCorrespondingCmdNext6 = 6, - #[doc = "7: Select CMD7 command buffer register as next command."] - DoCmd7Next = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Next) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Next { - type Ux = u8; -} -impl crate::IsEnum for Next {} -#[doc = "Field `NEXT` reader - Next Command Select"] -pub type NextR = crate::FieldReader; -impl NextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Next { - match self.bits { - 0 => Next::NoNextCmdTerminateOnFinish, - 1 => Next::DoCmd1Next, - 2 => Next::DoCorrespondingCmdNext2, - 3 => Next::DoCorrespondingCmdNext3, - 4 => Next::DoCorrespondingCmdNext4, - 5 => Next::DoCorrespondingCmdNext5, - 6 => Next::DoCorrespondingCmdNext6, - 7 => Next::DoCmd7Next, - _ => unreachable!(), - } - } - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn is_no_next_cmd_terminate_on_finish(&self) -> bool { - *self == Next::NoNextCmdTerminateOnFinish - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd1_next(&self) -> bool { - *self == Next::DoCmd1Next - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_2(&self) -> bool { - *self == Next::DoCorrespondingCmdNext2 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_3(&self) -> bool { - *self == Next::DoCorrespondingCmdNext3 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_4(&self) -> bool { - *self == Next::DoCorrespondingCmdNext4 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_5(&self) -> bool { - *self == Next::DoCorrespondingCmdNext5 - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn is_do_corresponding_cmd_next_6(&self) -> bool { - *self == Next::DoCorrespondingCmdNext6 - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn is_do_cmd7_next(&self) -> bool { - *self == Next::DoCmd7Next - } -} -#[doc = "Field `NEXT` writer - Next Command Select"] -pub type NextW<'a, REG> = crate::FieldWriter<'a, REG, 3, Next, crate::Safe>; -impl<'a, REG> NextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - #[inline(always)] - pub fn no_next_cmd_terminate_on_finish(self) -> &'a mut crate::W { - self.variant(Next::NoNextCmdTerminateOnFinish) - } - #[doc = "Select CMD1 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd1_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd1Next) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_2(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext2) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_3(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext3) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_4(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext4) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_5(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext5) - } - #[doc = "Select corresponding CMD command buffer register as next command"] - #[inline(always)] - pub fn do_corresponding_cmd_next_6(self) -> &'a mut crate::W { - self.variant(Next::DoCorrespondingCmdNext6) - } - #[doc = "Select CMD7 command buffer register as next command."] - #[inline(always)] - pub fn do_cmd7_next(self) -> &'a mut crate::W { - self.variant(Next::DoCmd7Next) - } -} -impl R { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&self) -> CmpenR { - CmpenR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&self) -> WaitTrigR { - WaitTrigR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&self) -> LwiR { - LwiR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&self) -> StsR { - StsR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&self) -> AvgsR { - AvgsR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&self) -> LoopR { - LoopR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&self) -> NextR { - NextR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Compare Function Enable"] - #[inline(always)] - pub fn cmpen(&mut self) -> CmpenW { - CmpenW::new(self, 0) - } - #[doc = "Bit 2 - Wait for Trigger Assertion before Execution."] - #[inline(always)] - pub fn wait_trig(&mut self) -> WaitTrigW { - WaitTrigW::new(self, 2) - } - #[doc = "Bit 7 - Loop with Increment"] - #[inline(always)] - pub fn lwi(&mut self) -> LwiW { - LwiW::new(self, 7) - } - #[doc = "Bits 8:10 - Sample Time Select"] - #[inline(always)] - pub fn sts(&mut self) -> StsW { - StsW::new(self, 8) - } - #[doc = "Bits 12:15 - Hardware Average Select"] - #[inline(always)] - pub fn avgs(&mut self) -> AvgsW { - AvgsW::new(self, 12) - } - #[doc = "Bits 16:19 - Loop Count Select"] - #[inline(always)] - pub fn loop_(&mut self) -> LoopW { - LoopW::new(self, 16) - } - #[doc = "Bits 24:26 - Next Command Select"] - #[inline(always)] - pub fn next(&mut self) -> NextW { - NextW::new(self, 24) - } -} -#[doc = "Command High Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdh7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdh7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdh7Spec; -impl crate::RegisterSpec for Cmdh7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdh7::R`](R) reader structure"] -impl crate::Readable for Cmdh7Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdh7::W`](W) writer structure"] -impl crate::Writable for Cmdh7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDH7 to value 0"] -impl crate::Resettable for Cmdh7Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl1.rs b/mcxa276-pac/src/adc0/cmdl1.rs deleted file mode 100644 index e11d25b2b..000000000 --- a/mcxa276-pac/src/adc0/cmdl1.rs +++ /dev/null @@ -1,331 +0,0 @@ -#[doc = "Register `CMDL1` reader"] -pub type R = crate::R; -#[doc = "Register `CMDL1` writer"] -pub type W = crate::W; -#[doc = "Input Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Adch { - #[doc = "0: Select CH0A."] - SelectCh0 = 0, - #[doc = "1: Select CH1A."] - SelectCh1 = 1, - #[doc = "2: Select CH2A."] - SelectCh2 = 2, - #[doc = "3: Select CH3A."] - SelectCh3 = 3, - #[doc = "4: Select corresponding channel CHnA."] - SelectCorrespondingChannel4 = 4, - #[doc = "5: Select corresponding channel CHnA."] - SelectCorrespondingChannel5 = 5, - #[doc = "6: Select corresponding channel CHnA."] - SelectCorrespondingChannel6 = 6, - #[doc = "7: Select corresponding channel CHnA."] - SelectCorrespondingChannel7 = 7, - #[doc = "8: Select corresponding channel CHnA."] - SelectCorrespondingChannel8 = 8, - #[doc = "9: Select corresponding channel CHnA."] - SelectCorrespondingChannel9 = 9, - #[doc = "30: Select CH30A."] - SelectCh30 = 30, - #[doc = "31: Select CH31A."] - SelectCh31 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Adch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Adch { - type Ux = u8; -} -impl crate::IsEnum for Adch {} -#[doc = "Field `ADCH` reader - Input Channel Select"] -pub type AdchR = crate::FieldReader; -impl AdchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Adch::SelectCh0), - 1 => Some(Adch::SelectCh1), - 2 => Some(Adch::SelectCh2), - 3 => Some(Adch::SelectCh3), - 4 => Some(Adch::SelectCorrespondingChannel4), - 5 => Some(Adch::SelectCorrespondingChannel5), - 6 => Some(Adch::SelectCorrespondingChannel6), - 7 => Some(Adch::SelectCorrespondingChannel7), - 8 => Some(Adch::SelectCorrespondingChannel8), - 9 => Some(Adch::SelectCorrespondingChannel9), - 30 => Some(Adch::SelectCh30), - 31 => Some(Adch::SelectCh31), - _ => None, - } - } - #[doc = "Select CH0A."] - #[inline(always)] - pub fn is_select_ch0(&self) -> bool { - *self == Adch::SelectCh0 - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn is_select_ch1(&self) -> bool { - *self == Adch::SelectCh1 - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn is_select_ch2(&self) -> bool { - *self == Adch::SelectCh2 - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn is_select_ch3(&self) -> bool { - *self == Adch::SelectCh3 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_4(&self) -> bool { - *self == Adch::SelectCorrespondingChannel4 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_5(&self) -> bool { - *self == Adch::SelectCorrespondingChannel5 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_6(&self) -> bool { - *self == Adch::SelectCorrespondingChannel6 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_7(&self) -> bool { - *self == Adch::SelectCorrespondingChannel7 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_8(&self) -> bool { - *self == Adch::SelectCorrespondingChannel8 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_9(&self) -> bool { - *self == Adch::SelectCorrespondingChannel9 - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn is_select_ch30(&self) -> bool { - *self == Adch::SelectCh30 - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn is_select_ch31(&self) -> bool { - *self == Adch::SelectCh31 - } -} -#[doc = "Field `ADCH` writer - Input Channel Select"] -pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; -impl<'a, REG> AdchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select CH0A."] - #[inline(always)] - pub fn select_ch0(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh0) - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn select_ch1(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh1) - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn select_ch2(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh2) - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn select_ch3(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh3) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel4) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel5) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel6) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel7) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel8) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel9) - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn select_ch30(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh30) - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn select_ch31(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh31) - } -} -#[doc = "Conversion Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctype { - #[doc = "0: Single-Ended Mode. Only A side channel is converted."] - SingleEndedASideChannel = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctype { - type Ux = u8; -} -impl crate::IsEnum for Ctype {} -#[doc = "Field `CTYPE` reader - Conversion Type"] -pub type CtypeR = crate::FieldReader; -impl CtypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ctype::SingleEndedASideChannel), - _ => None, - } - } - #[doc = "Single-Ended Mode. Only A side channel is converted."] - #[inline(always)] - pub fn is_single_ended_a_side_channel(&self) -> bool { - *self == Ctype::SingleEndedASideChannel - } -} - -pub type CtypeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ctype>; - -#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mode { - #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] - Data12Bits = 0, - #[doc = "1: High resolution. Single-ended 16-bit conversion."] - Data16Bits = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MODE` reader - Select Resolution of Conversions"] -pub type ModeR = crate::BitReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mode { - match self.bits { - false => Mode::Data12Bits, - true => Mode::Data16Bits, - } - } - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn is_data_12_bits(&self) -> bool { - *self == Mode::Data12Bits - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn is_data_16_bits(&self) -> bool { - *self == Mode::Data16Bits - } -} -#[doc = "Field `MODE` writer - Select Resolution of Conversions"] -pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn data_12_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data12Bits) - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn data_16_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data16Bits) - } -} -impl R { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&self) -> AdchR { - AdchR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&self) -> CtypeR { - CtypeR::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&mut self) -> AdchW { - AdchW::new(self, 0) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&mut self) -> CtypeW { - CtypeW::new(self, 5) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 7) - } -} -#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdl1Spec; -impl crate::RegisterSpec for Cmdl1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdl1::R`](R) reader structure"] -impl crate::Readable for Cmdl1Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdl1::W`](W) writer structure"] -impl crate::Writable for Cmdl1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDL1 to value 0"] -impl crate::Resettable for Cmdl1Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl2.rs b/mcxa276-pac/src/adc0/cmdl2.rs deleted file mode 100644 index 89f46de66..000000000 --- a/mcxa276-pac/src/adc0/cmdl2.rs +++ /dev/null @@ -1,323 +0,0 @@ -#[doc = "Register `CMDL2` reader"] -pub type R = crate::R; -#[doc = "Register `CMDL2` writer"] -pub type W = crate::W; -#[doc = "Input Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Adch { - #[doc = "0: Select CH0A."] - SelectCh0 = 0, - #[doc = "1: Select CH1A."] - SelectCh1 = 1, - #[doc = "2: Select CH2A."] - SelectCh2 = 2, - #[doc = "3: Select CH3A."] - SelectCh3 = 3, - #[doc = "4: Select corresponding channel CHnA."] - SelectCorrespondingChannel4 = 4, - #[doc = "5: Select corresponding channel CHnA."] - SelectCorrespondingChannel5 = 5, - #[doc = "6: Select corresponding channel CHnA."] - SelectCorrespondingChannel6 = 6, - #[doc = "7: Select corresponding channel CHnA."] - SelectCorrespondingChannel7 = 7, - #[doc = "8: Select corresponding channel CHnA."] - SelectCorrespondingChannel8 = 8, - #[doc = "9: Select corresponding channel CHnA."] - SelectCorrespondingChannel9 = 9, - #[doc = "30: Select CH30A."] - SelectCh30 = 30, - #[doc = "31: Select CH31A."] - SelectCh31 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Adch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Adch { - type Ux = u8; -} -impl crate::IsEnum for Adch {} -#[doc = "Field `ADCH` reader - Input Channel Select"] -pub type AdchR = crate::FieldReader; -impl AdchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Adch::SelectCh0), - 1 => Some(Adch::SelectCh1), - 2 => Some(Adch::SelectCh2), - 3 => Some(Adch::SelectCh3), - 4 => Some(Adch::SelectCorrespondingChannel4), - 5 => Some(Adch::SelectCorrespondingChannel5), - 6 => Some(Adch::SelectCorrespondingChannel6), - 7 => Some(Adch::SelectCorrespondingChannel7), - 8 => Some(Adch::SelectCorrespondingChannel8), - 9 => Some(Adch::SelectCorrespondingChannel9), - 30 => Some(Adch::SelectCh30), - 31 => Some(Adch::SelectCh31), - _ => None, - } - } - #[doc = "Select CH0A."] - #[inline(always)] - pub fn is_select_ch0(&self) -> bool { - *self == Adch::SelectCh0 - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn is_select_ch1(&self) -> bool { - *self == Adch::SelectCh1 - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn is_select_ch2(&self) -> bool { - *self == Adch::SelectCh2 - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn is_select_ch3(&self) -> bool { - *self == Adch::SelectCh3 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_4(&self) -> bool { - *self == Adch::SelectCorrespondingChannel4 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_5(&self) -> bool { - *self == Adch::SelectCorrespondingChannel5 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_6(&self) -> bool { - *self == Adch::SelectCorrespondingChannel6 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_7(&self) -> bool { - *self == Adch::SelectCorrespondingChannel7 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_8(&self) -> bool { - *self == Adch::SelectCorrespondingChannel8 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_9(&self) -> bool { - *self == Adch::SelectCorrespondingChannel9 - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn is_select_ch30(&self) -> bool { - *self == Adch::SelectCh30 - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn is_select_ch31(&self) -> bool { - *self == Adch::SelectCh31 - } -} -#[doc = "Field `ADCH` writer - Input Channel Select"] -pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; -impl<'a, REG> AdchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select CH0A."] - #[inline(always)] - pub fn select_ch0(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh0) - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn select_ch1(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh1) - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn select_ch2(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh2) - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn select_ch3(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh3) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel4) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel5) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel6) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel7) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel8) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel9) - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn select_ch30(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh30) - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn select_ch31(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh31) - } -} -#[doc = "Conversion Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctype { - #[doc = "0: Single-Ended Mode. Only A side channel is converted."] - SingleEndedASideChannel = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctype { - type Ux = u8; -} -impl crate::IsEnum for Ctype {} -#[doc = "Field `CTYPE` reader - Conversion Type"] -pub type CtypeR = crate::FieldReader; -impl CtypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ctype::SingleEndedASideChannel), - _ => None, - } - } - #[doc = "Single-Ended Mode. Only A side channel is converted."] - #[inline(always)] - pub fn is_single_ended_a_side_channel(&self) -> bool { - *self == Ctype::SingleEndedASideChannel - } -} -#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mode { - #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] - Data12Bits = 0, - #[doc = "1: High resolution. Single-ended 16-bit conversion."] - Data16Bits = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MODE` reader - Select Resolution of Conversions"] -pub type ModeR = crate::BitReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mode { - match self.bits { - false => Mode::Data12Bits, - true => Mode::Data16Bits, - } - } - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn is_data_12_bits(&self) -> bool { - *self == Mode::Data12Bits - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn is_data_16_bits(&self) -> bool { - *self == Mode::Data16Bits - } -} -#[doc = "Field `MODE` writer - Select Resolution of Conversions"] -pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn data_12_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data12Bits) - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn data_16_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data16Bits) - } -} -impl R { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&self) -> AdchR { - AdchR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&self) -> CtypeR { - CtypeR::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&mut self) -> AdchW { - AdchW::new(self, 0) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 7) - } -} -#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdl2Spec; -impl crate::RegisterSpec for Cmdl2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdl2::R`](R) reader structure"] -impl crate::Readable for Cmdl2Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdl2::W`](W) writer structure"] -impl crate::Writable for Cmdl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDL2 to value 0"] -impl crate::Resettable for Cmdl2Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl3.rs b/mcxa276-pac/src/adc0/cmdl3.rs deleted file mode 100644 index 4a8104641..000000000 --- a/mcxa276-pac/src/adc0/cmdl3.rs +++ /dev/null @@ -1,323 +0,0 @@ -#[doc = "Register `CMDL3` reader"] -pub type R = crate::R; -#[doc = "Register `CMDL3` writer"] -pub type W = crate::W; -#[doc = "Input Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Adch { - #[doc = "0: Select CH0A."] - SelectCh0 = 0, - #[doc = "1: Select CH1A."] - SelectCh1 = 1, - #[doc = "2: Select CH2A."] - SelectCh2 = 2, - #[doc = "3: Select CH3A."] - SelectCh3 = 3, - #[doc = "4: Select corresponding channel CHnA."] - SelectCorrespondingChannel4 = 4, - #[doc = "5: Select corresponding channel CHnA."] - SelectCorrespondingChannel5 = 5, - #[doc = "6: Select corresponding channel CHnA."] - SelectCorrespondingChannel6 = 6, - #[doc = "7: Select corresponding channel CHnA."] - SelectCorrespondingChannel7 = 7, - #[doc = "8: Select corresponding channel CHnA."] - SelectCorrespondingChannel8 = 8, - #[doc = "9: Select corresponding channel CHnA."] - SelectCorrespondingChannel9 = 9, - #[doc = "30: Select CH30A."] - SelectCh30 = 30, - #[doc = "31: Select CH31A."] - SelectCh31 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Adch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Adch { - type Ux = u8; -} -impl crate::IsEnum for Adch {} -#[doc = "Field `ADCH` reader - Input Channel Select"] -pub type AdchR = crate::FieldReader; -impl AdchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Adch::SelectCh0), - 1 => Some(Adch::SelectCh1), - 2 => Some(Adch::SelectCh2), - 3 => Some(Adch::SelectCh3), - 4 => Some(Adch::SelectCorrespondingChannel4), - 5 => Some(Adch::SelectCorrespondingChannel5), - 6 => Some(Adch::SelectCorrespondingChannel6), - 7 => Some(Adch::SelectCorrespondingChannel7), - 8 => Some(Adch::SelectCorrespondingChannel8), - 9 => Some(Adch::SelectCorrespondingChannel9), - 30 => Some(Adch::SelectCh30), - 31 => Some(Adch::SelectCh31), - _ => None, - } - } - #[doc = "Select CH0A."] - #[inline(always)] - pub fn is_select_ch0(&self) -> bool { - *self == Adch::SelectCh0 - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn is_select_ch1(&self) -> bool { - *self == Adch::SelectCh1 - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn is_select_ch2(&self) -> bool { - *self == Adch::SelectCh2 - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn is_select_ch3(&self) -> bool { - *self == Adch::SelectCh3 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_4(&self) -> bool { - *self == Adch::SelectCorrespondingChannel4 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_5(&self) -> bool { - *self == Adch::SelectCorrespondingChannel5 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_6(&self) -> bool { - *self == Adch::SelectCorrespondingChannel6 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_7(&self) -> bool { - *self == Adch::SelectCorrespondingChannel7 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_8(&self) -> bool { - *self == Adch::SelectCorrespondingChannel8 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_9(&self) -> bool { - *self == Adch::SelectCorrespondingChannel9 - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn is_select_ch30(&self) -> bool { - *self == Adch::SelectCh30 - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn is_select_ch31(&self) -> bool { - *self == Adch::SelectCh31 - } -} -#[doc = "Field `ADCH` writer - Input Channel Select"] -pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; -impl<'a, REG> AdchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select CH0A."] - #[inline(always)] - pub fn select_ch0(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh0) - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn select_ch1(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh1) - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn select_ch2(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh2) - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn select_ch3(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh3) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel4) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel5) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel6) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel7) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel8) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel9) - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn select_ch30(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh30) - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn select_ch31(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh31) - } -} -#[doc = "Conversion Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctype { - #[doc = "0: Single-Ended Mode. Only A side channel is converted."] - SingleEndedASideChannel = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctype { - type Ux = u8; -} -impl crate::IsEnum for Ctype {} -#[doc = "Field `CTYPE` reader - Conversion Type"] -pub type CtypeR = crate::FieldReader; -impl CtypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ctype::SingleEndedASideChannel), - _ => None, - } - } - #[doc = "Single-Ended Mode. Only A side channel is converted."] - #[inline(always)] - pub fn is_single_ended_a_side_channel(&self) -> bool { - *self == Ctype::SingleEndedASideChannel - } -} -#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mode { - #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] - Data12Bits = 0, - #[doc = "1: High resolution. Single-ended 16-bit conversion."] - Data16Bits = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MODE` reader - Select Resolution of Conversions"] -pub type ModeR = crate::BitReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mode { - match self.bits { - false => Mode::Data12Bits, - true => Mode::Data16Bits, - } - } - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn is_data_12_bits(&self) -> bool { - *self == Mode::Data12Bits - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn is_data_16_bits(&self) -> bool { - *self == Mode::Data16Bits - } -} -#[doc = "Field `MODE` writer - Select Resolution of Conversions"] -pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn data_12_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data12Bits) - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn data_16_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data16Bits) - } -} -impl R { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&self) -> AdchR { - AdchR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&self) -> CtypeR { - CtypeR::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&mut self) -> AdchW { - AdchW::new(self, 0) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 7) - } -} -#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdl3Spec; -impl crate::RegisterSpec for Cmdl3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdl3::R`](R) reader structure"] -impl crate::Readable for Cmdl3Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdl3::W`](W) writer structure"] -impl crate::Writable for Cmdl3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDL3 to value 0"] -impl crate::Resettable for Cmdl3Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl4.rs b/mcxa276-pac/src/adc0/cmdl4.rs deleted file mode 100644 index 46e64f7d4..000000000 --- a/mcxa276-pac/src/adc0/cmdl4.rs +++ /dev/null @@ -1,323 +0,0 @@ -#[doc = "Register `CMDL4` reader"] -pub type R = crate::R; -#[doc = "Register `CMDL4` writer"] -pub type W = crate::W; -#[doc = "Input Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Adch { - #[doc = "0: Select CH0A."] - SelectCh0 = 0, - #[doc = "1: Select CH1A."] - SelectCh1 = 1, - #[doc = "2: Select CH2A."] - SelectCh2 = 2, - #[doc = "3: Select CH3A."] - SelectCh3 = 3, - #[doc = "4: Select corresponding channel CHnA."] - SelectCorrespondingChannel4 = 4, - #[doc = "5: Select corresponding channel CHnA."] - SelectCorrespondingChannel5 = 5, - #[doc = "6: Select corresponding channel CHnA."] - SelectCorrespondingChannel6 = 6, - #[doc = "7: Select corresponding channel CHnA."] - SelectCorrespondingChannel7 = 7, - #[doc = "8: Select corresponding channel CHnA."] - SelectCorrespondingChannel8 = 8, - #[doc = "9: Select corresponding channel CHnA."] - SelectCorrespondingChannel9 = 9, - #[doc = "30: Select CH30A."] - SelectCh30 = 30, - #[doc = "31: Select CH31A."] - SelectCh31 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Adch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Adch { - type Ux = u8; -} -impl crate::IsEnum for Adch {} -#[doc = "Field `ADCH` reader - Input Channel Select"] -pub type AdchR = crate::FieldReader; -impl AdchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Adch::SelectCh0), - 1 => Some(Adch::SelectCh1), - 2 => Some(Adch::SelectCh2), - 3 => Some(Adch::SelectCh3), - 4 => Some(Adch::SelectCorrespondingChannel4), - 5 => Some(Adch::SelectCorrespondingChannel5), - 6 => Some(Adch::SelectCorrespondingChannel6), - 7 => Some(Adch::SelectCorrespondingChannel7), - 8 => Some(Adch::SelectCorrespondingChannel8), - 9 => Some(Adch::SelectCorrespondingChannel9), - 30 => Some(Adch::SelectCh30), - 31 => Some(Adch::SelectCh31), - _ => None, - } - } - #[doc = "Select CH0A."] - #[inline(always)] - pub fn is_select_ch0(&self) -> bool { - *self == Adch::SelectCh0 - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn is_select_ch1(&self) -> bool { - *self == Adch::SelectCh1 - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn is_select_ch2(&self) -> bool { - *self == Adch::SelectCh2 - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn is_select_ch3(&self) -> bool { - *self == Adch::SelectCh3 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_4(&self) -> bool { - *self == Adch::SelectCorrespondingChannel4 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_5(&self) -> bool { - *self == Adch::SelectCorrespondingChannel5 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_6(&self) -> bool { - *self == Adch::SelectCorrespondingChannel6 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_7(&self) -> bool { - *self == Adch::SelectCorrespondingChannel7 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_8(&self) -> bool { - *self == Adch::SelectCorrespondingChannel8 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_9(&self) -> bool { - *self == Adch::SelectCorrespondingChannel9 - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn is_select_ch30(&self) -> bool { - *self == Adch::SelectCh30 - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn is_select_ch31(&self) -> bool { - *self == Adch::SelectCh31 - } -} -#[doc = "Field `ADCH` writer - Input Channel Select"] -pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; -impl<'a, REG> AdchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select CH0A."] - #[inline(always)] - pub fn select_ch0(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh0) - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn select_ch1(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh1) - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn select_ch2(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh2) - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn select_ch3(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh3) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel4) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel5) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel6) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel7) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel8) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel9) - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn select_ch30(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh30) - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn select_ch31(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh31) - } -} -#[doc = "Conversion Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctype { - #[doc = "0: Single-Ended Mode. Only A side channel is converted."] - SingleEndedASideChannel = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctype { - type Ux = u8; -} -impl crate::IsEnum for Ctype {} -#[doc = "Field `CTYPE` reader - Conversion Type"] -pub type CtypeR = crate::FieldReader; -impl CtypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ctype::SingleEndedASideChannel), - _ => None, - } - } - #[doc = "Single-Ended Mode. Only A side channel is converted."] - #[inline(always)] - pub fn is_single_ended_a_side_channel(&self) -> bool { - *self == Ctype::SingleEndedASideChannel - } -} -#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mode { - #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] - Data12Bits = 0, - #[doc = "1: High resolution. Single-ended 16-bit conversion."] - Data16Bits = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MODE` reader - Select Resolution of Conversions"] -pub type ModeR = crate::BitReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mode { - match self.bits { - false => Mode::Data12Bits, - true => Mode::Data16Bits, - } - } - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn is_data_12_bits(&self) -> bool { - *self == Mode::Data12Bits - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn is_data_16_bits(&self) -> bool { - *self == Mode::Data16Bits - } -} -#[doc = "Field `MODE` writer - Select Resolution of Conversions"] -pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn data_12_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data12Bits) - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn data_16_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data16Bits) - } -} -impl R { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&self) -> AdchR { - AdchR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&self) -> CtypeR { - CtypeR::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&mut self) -> AdchW { - AdchW::new(self, 0) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 7) - } -} -#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdl4Spec; -impl crate::RegisterSpec for Cmdl4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdl4::R`](R) reader structure"] -impl crate::Readable for Cmdl4Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdl4::W`](W) writer structure"] -impl crate::Writable for Cmdl4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDL4 to value 0"] -impl crate::Resettable for Cmdl4Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl5.rs b/mcxa276-pac/src/adc0/cmdl5.rs deleted file mode 100644 index 00f76e7dc..000000000 --- a/mcxa276-pac/src/adc0/cmdl5.rs +++ /dev/null @@ -1,323 +0,0 @@ -#[doc = "Register `CMDL5` reader"] -pub type R = crate::R; -#[doc = "Register `CMDL5` writer"] -pub type W = crate::W; -#[doc = "Input Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Adch { - #[doc = "0: Select CH0A."] - SelectCh0 = 0, - #[doc = "1: Select CH1A."] - SelectCh1 = 1, - #[doc = "2: Select CH2A."] - SelectCh2 = 2, - #[doc = "3: Select CH3A."] - SelectCh3 = 3, - #[doc = "4: Select corresponding channel CHnA."] - SelectCorrespondingChannel4 = 4, - #[doc = "5: Select corresponding channel CHnA."] - SelectCorrespondingChannel5 = 5, - #[doc = "6: Select corresponding channel CHnA."] - SelectCorrespondingChannel6 = 6, - #[doc = "7: Select corresponding channel CHnA."] - SelectCorrespondingChannel7 = 7, - #[doc = "8: Select corresponding channel CHnA."] - SelectCorrespondingChannel8 = 8, - #[doc = "9: Select corresponding channel CHnA."] - SelectCorrespondingChannel9 = 9, - #[doc = "30: Select CH30A."] - SelectCh30 = 30, - #[doc = "31: Select CH31A."] - SelectCh31 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Adch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Adch { - type Ux = u8; -} -impl crate::IsEnum for Adch {} -#[doc = "Field `ADCH` reader - Input Channel Select"] -pub type AdchR = crate::FieldReader; -impl AdchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Adch::SelectCh0), - 1 => Some(Adch::SelectCh1), - 2 => Some(Adch::SelectCh2), - 3 => Some(Adch::SelectCh3), - 4 => Some(Adch::SelectCorrespondingChannel4), - 5 => Some(Adch::SelectCorrespondingChannel5), - 6 => Some(Adch::SelectCorrespondingChannel6), - 7 => Some(Adch::SelectCorrespondingChannel7), - 8 => Some(Adch::SelectCorrespondingChannel8), - 9 => Some(Adch::SelectCorrespondingChannel9), - 30 => Some(Adch::SelectCh30), - 31 => Some(Adch::SelectCh31), - _ => None, - } - } - #[doc = "Select CH0A."] - #[inline(always)] - pub fn is_select_ch0(&self) -> bool { - *self == Adch::SelectCh0 - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn is_select_ch1(&self) -> bool { - *self == Adch::SelectCh1 - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn is_select_ch2(&self) -> bool { - *self == Adch::SelectCh2 - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn is_select_ch3(&self) -> bool { - *self == Adch::SelectCh3 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_4(&self) -> bool { - *self == Adch::SelectCorrespondingChannel4 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_5(&self) -> bool { - *self == Adch::SelectCorrespondingChannel5 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_6(&self) -> bool { - *self == Adch::SelectCorrespondingChannel6 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_7(&self) -> bool { - *self == Adch::SelectCorrespondingChannel7 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_8(&self) -> bool { - *self == Adch::SelectCorrespondingChannel8 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_9(&self) -> bool { - *self == Adch::SelectCorrespondingChannel9 - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn is_select_ch30(&self) -> bool { - *self == Adch::SelectCh30 - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn is_select_ch31(&self) -> bool { - *self == Adch::SelectCh31 - } -} -#[doc = "Field `ADCH` writer - Input Channel Select"] -pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; -impl<'a, REG> AdchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select CH0A."] - #[inline(always)] - pub fn select_ch0(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh0) - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn select_ch1(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh1) - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn select_ch2(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh2) - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn select_ch3(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh3) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel4) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel5) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel6) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel7) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel8) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel9) - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn select_ch30(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh30) - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn select_ch31(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh31) - } -} -#[doc = "Conversion Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctype { - #[doc = "0: Single-Ended Mode. Only A side channel is converted."] - SingleEndedASideChannel = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctype { - type Ux = u8; -} -impl crate::IsEnum for Ctype {} -#[doc = "Field `CTYPE` reader - Conversion Type"] -pub type CtypeR = crate::FieldReader; -impl CtypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ctype::SingleEndedASideChannel), - _ => None, - } - } - #[doc = "Single-Ended Mode. Only A side channel is converted."] - #[inline(always)] - pub fn is_single_ended_a_side_channel(&self) -> bool { - *self == Ctype::SingleEndedASideChannel - } -} -#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mode { - #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] - Data12Bits = 0, - #[doc = "1: High resolution. Single-ended 16-bit conversion."] - Data16Bits = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MODE` reader - Select Resolution of Conversions"] -pub type ModeR = crate::BitReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mode { - match self.bits { - false => Mode::Data12Bits, - true => Mode::Data16Bits, - } - } - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn is_data_12_bits(&self) -> bool { - *self == Mode::Data12Bits - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn is_data_16_bits(&self) -> bool { - *self == Mode::Data16Bits - } -} -#[doc = "Field `MODE` writer - Select Resolution of Conversions"] -pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn data_12_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data12Bits) - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn data_16_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data16Bits) - } -} -impl R { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&self) -> AdchR { - AdchR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&self) -> CtypeR { - CtypeR::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&mut self) -> AdchW { - AdchW::new(self, 0) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 7) - } -} -#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdl5Spec; -impl crate::RegisterSpec for Cmdl5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdl5::R`](R) reader structure"] -impl crate::Readable for Cmdl5Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdl5::W`](W) writer structure"] -impl crate::Writable for Cmdl5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDL5 to value 0"] -impl crate::Resettable for Cmdl5Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl6.rs b/mcxa276-pac/src/adc0/cmdl6.rs deleted file mode 100644 index de768847c..000000000 --- a/mcxa276-pac/src/adc0/cmdl6.rs +++ /dev/null @@ -1,323 +0,0 @@ -#[doc = "Register `CMDL6` reader"] -pub type R = crate::R; -#[doc = "Register `CMDL6` writer"] -pub type W = crate::W; -#[doc = "Input Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Adch { - #[doc = "0: Select CH0A."] - SelectCh0 = 0, - #[doc = "1: Select CH1A."] - SelectCh1 = 1, - #[doc = "2: Select CH2A."] - SelectCh2 = 2, - #[doc = "3: Select CH3A."] - SelectCh3 = 3, - #[doc = "4: Select corresponding channel CHnA."] - SelectCorrespondingChannel4 = 4, - #[doc = "5: Select corresponding channel CHnA."] - SelectCorrespondingChannel5 = 5, - #[doc = "6: Select corresponding channel CHnA."] - SelectCorrespondingChannel6 = 6, - #[doc = "7: Select corresponding channel CHnA."] - SelectCorrespondingChannel7 = 7, - #[doc = "8: Select corresponding channel CHnA."] - SelectCorrespondingChannel8 = 8, - #[doc = "9: Select corresponding channel CHnA."] - SelectCorrespondingChannel9 = 9, - #[doc = "30: Select CH30A."] - SelectCh30 = 30, - #[doc = "31: Select CH31A."] - SelectCh31 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Adch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Adch { - type Ux = u8; -} -impl crate::IsEnum for Adch {} -#[doc = "Field `ADCH` reader - Input Channel Select"] -pub type AdchR = crate::FieldReader; -impl AdchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Adch::SelectCh0), - 1 => Some(Adch::SelectCh1), - 2 => Some(Adch::SelectCh2), - 3 => Some(Adch::SelectCh3), - 4 => Some(Adch::SelectCorrespondingChannel4), - 5 => Some(Adch::SelectCorrespondingChannel5), - 6 => Some(Adch::SelectCorrespondingChannel6), - 7 => Some(Adch::SelectCorrespondingChannel7), - 8 => Some(Adch::SelectCorrespondingChannel8), - 9 => Some(Adch::SelectCorrespondingChannel9), - 30 => Some(Adch::SelectCh30), - 31 => Some(Adch::SelectCh31), - _ => None, - } - } - #[doc = "Select CH0A."] - #[inline(always)] - pub fn is_select_ch0(&self) -> bool { - *self == Adch::SelectCh0 - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn is_select_ch1(&self) -> bool { - *self == Adch::SelectCh1 - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn is_select_ch2(&self) -> bool { - *self == Adch::SelectCh2 - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn is_select_ch3(&self) -> bool { - *self == Adch::SelectCh3 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_4(&self) -> bool { - *self == Adch::SelectCorrespondingChannel4 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_5(&self) -> bool { - *self == Adch::SelectCorrespondingChannel5 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_6(&self) -> bool { - *self == Adch::SelectCorrespondingChannel6 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_7(&self) -> bool { - *self == Adch::SelectCorrespondingChannel7 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_8(&self) -> bool { - *self == Adch::SelectCorrespondingChannel8 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_9(&self) -> bool { - *self == Adch::SelectCorrespondingChannel9 - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn is_select_ch30(&self) -> bool { - *self == Adch::SelectCh30 - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn is_select_ch31(&self) -> bool { - *self == Adch::SelectCh31 - } -} -#[doc = "Field `ADCH` writer - Input Channel Select"] -pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; -impl<'a, REG> AdchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select CH0A."] - #[inline(always)] - pub fn select_ch0(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh0) - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn select_ch1(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh1) - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn select_ch2(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh2) - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn select_ch3(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh3) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel4) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel5) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel6) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel7) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel8) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel9) - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn select_ch30(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh30) - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn select_ch31(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh31) - } -} -#[doc = "Conversion Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctype { - #[doc = "0: Single-Ended Mode. Only A side channel is converted."] - SingleEndedASideChannel = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctype { - type Ux = u8; -} -impl crate::IsEnum for Ctype {} -#[doc = "Field `CTYPE` reader - Conversion Type"] -pub type CtypeR = crate::FieldReader; -impl CtypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ctype::SingleEndedASideChannel), - _ => None, - } - } - #[doc = "Single-Ended Mode. Only A side channel is converted."] - #[inline(always)] - pub fn is_single_ended_a_side_channel(&self) -> bool { - *self == Ctype::SingleEndedASideChannel - } -} -#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mode { - #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] - Data12Bits = 0, - #[doc = "1: High resolution. Single-ended 16-bit conversion."] - Data16Bits = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MODE` reader - Select Resolution of Conversions"] -pub type ModeR = crate::BitReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mode { - match self.bits { - false => Mode::Data12Bits, - true => Mode::Data16Bits, - } - } - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn is_data_12_bits(&self) -> bool { - *self == Mode::Data12Bits - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn is_data_16_bits(&self) -> bool { - *self == Mode::Data16Bits - } -} -#[doc = "Field `MODE` writer - Select Resolution of Conversions"] -pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn data_12_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data12Bits) - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn data_16_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data16Bits) - } -} -impl R { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&self) -> AdchR { - AdchR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&self) -> CtypeR { - CtypeR::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&mut self) -> AdchW { - AdchW::new(self, 0) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 7) - } -} -#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdl6Spec; -impl crate::RegisterSpec for Cmdl6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdl6::R`](R) reader structure"] -impl crate::Readable for Cmdl6Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdl6::W`](W) writer structure"] -impl crate::Writable for Cmdl6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDL6 to value 0"] -impl crate::Resettable for Cmdl6Spec {} diff --git a/mcxa276-pac/src/adc0/cmdl7.rs b/mcxa276-pac/src/adc0/cmdl7.rs deleted file mode 100644 index 08bef528a..000000000 --- a/mcxa276-pac/src/adc0/cmdl7.rs +++ /dev/null @@ -1,323 +0,0 @@ -#[doc = "Register `CMDL7` reader"] -pub type R = crate::R; -#[doc = "Register `CMDL7` writer"] -pub type W = crate::W; -#[doc = "Input Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Adch { - #[doc = "0: Select CH0A."] - SelectCh0 = 0, - #[doc = "1: Select CH1A."] - SelectCh1 = 1, - #[doc = "2: Select CH2A."] - SelectCh2 = 2, - #[doc = "3: Select CH3A."] - SelectCh3 = 3, - #[doc = "4: Select corresponding channel CHnA."] - SelectCorrespondingChannel4 = 4, - #[doc = "5: Select corresponding channel CHnA."] - SelectCorrespondingChannel5 = 5, - #[doc = "6: Select corresponding channel CHnA."] - SelectCorrespondingChannel6 = 6, - #[doc = "7: Select corresponding channel CHnA."] - SelectCorrespondingChannel7 = 7, - #[doc = "8: Select corresponding channel CHnA."] - SelectCorrespondingChannel8 = 8, - #[doc = "9: Select corresponding channel CHnA."] - SelectCorrespondingChannel9 = 9, - #[doc = "30: Select CH30A."] - SelectCh30 = 30, - #[doc = "31: Select CH31A."] - SelectCh31 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Adch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Adch { - type Ux = u8; -} -impl crate::IsEnum for Adch {} -#[doc = "Field `ADCH` reader - Input Channel Select"] -pub type AdchR = crate::FieldReader; -impl AdchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Adch::SelectCh0), - 1 => Some(Adch::SelectCh1), - 2 => Some(Adch::SelectCh2), - 3 => Some(Adch::SelectCh3), - 4 => Some(Adch::SelectCorrespondingChannel4), - 5 => Some(Adch::SelectCorrespondingChannel5), - 6 => Some(Adch::SelectCorrespondingChannel6), - 7 => Some(Adch::SelectCorrespondingChannel7), - 8 => Some(Adch::SelectCorrespondingChannel8), - 9 => Some(Adch::SelectCorrespondingChannel9), - 30 => Some(Adch::SelectCh30), - 31 => Some(Adch::SelectCh31), - _ => None, - } - } - #[doc = "Select CH0A."] - #[inline(always)] - pub fn is_select_ch0(&self) -> bool { - *self == Adch::SelectCh0 - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn is_select_ch1(&self) -> bool { - *self == Adch::SelectCh1 - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn is_select_ch2(&self) -> bool { - *self == Adch::SelectCh2 - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn is_select_ch3(&self) -> bool { - *self == Adch::SelectCh3 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_4(&self) -> bool { - *self == Adch::SelectCorrespondingChannel4 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_5(&self) -> bool { - *self == Adch::SelectCorrespondingChannel5 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_6(&self) -> bool { - *self == Adch::SelectCorrespondingChannel6 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_7(&self) -> bool { - *self == Adch::SelectCorrespondingChannel7 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_8(&self) -> bool { - *self == Adch::SelectCorrespondingChannel8 - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn is_select_corresponding_channel_9(&self) -> bool { - *self == Adch::SelectCorrespondingChannel9 - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn is_select_ch30(&self) -> bool { - *self == Adch::SelectCh30 - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn is_select_ch31(&self) -> bool { - *self == Adch::SelectCh31 - } -} -#[doc = "Field `ADCH` writer - Input Channel Select"] -pub type AdchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adch>; -impl<'a, REG> AdchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select CH0A."] - #[inline(always)] - pub fn select_ch0(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh0) - } - #[doc = "Select CH1A."] - #[inline(always)] - pub fn select_ch1(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh1) - } - #[doc = "Select CH2A."] - #[inline(always)] - pub fn select_ch2(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh2) - } - #[doc = "Select CH3A."] - #[inline(always)] - pub fn select_ch3(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh3) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_4(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel4) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_5(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel5) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_6(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel6) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_7(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel7) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_8(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel8) - } - #[doc = "Select corresponding channel CHnA."] - #[inline(always)] - pub fn select_corresponding_channel_9(self) -> &'a mut crate::W { - self.variant(Adch::SelectCorrespondingChannel9) - } - #[doc = "Select CH30A."] - #[inline(always)] - pub fn select_ch30(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh30) - } - #[doc = "Select CH31A."] - #[inline(always)] - pub fn select_ch31(self) -> &'a mut crate::W { - self.variant(Adch::SelectCh31) - } -} -#[doc = "Conversion Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctype { - #[doc = "0: Single-Ended Mode. Only A side channel is converted."] - SingleEndedASideChannel = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctype { - type Ux = u8; -} -impl crate::IsEnum for Ctype {} -#[doc = "Field `CTYPE` reader - Conversion Type"] -pub type CtypeR = crate::FieldReader; -impl CtypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ctype::SingleEndedASideChannel), - _ => None, - } - } - #[doc = "Single-Ended Mode. Only A side channel is converted."] - #[inline(always)] - pub fn is_single_ended_a_side_channel(&self) -> bool { - *self == Ctype::SingleEndedASideChannel - } -} -#[doc = "Select Resolution of Conversions\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mode { - #[doc = "0: Standard resolution. Single-ended 12-bit conversion."] - Data12Bits = 0, - #[doc = "1: High resolution. Single-ended 16-bit conversion."] - Data16Bits = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MODE` reader - Select Resolution of Conversions"] -pub type ModeR = crate::BitReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mode { - match self.bits { - false => Mode::Data12Bits, - true => Mode::Data16Bits, - } - } - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn is_data_12_bits(&self) -> bool { - *self == Mode::Data12Bits - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn is_data_16_bits(&self) -> bool { - *self == Mode::Data16Bits - } -} -#[doc = "Field `MODE` writer - Select Resolution of Conversions"] -pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard resolution. Single-ended 12-bit conversion."] - #[inline(always)] - pub fn data_12_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data12Bits) - } - #[doc = "High resolution. Single-ended 16-bit conversion."] - #[inline(always)] - pub fn data_16_bits(self) -> &'a mut crate::W { - self.variant(Mode::Data16Bits) - } -} -impl R { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&self) -> AdchR { - AdchR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Conversion Type"] - #[inline(always)] - pub fn ctype(&self) -> CtypeR { - CtypeR::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Input Channel Select"] - #[inline(always)] - pub fn adch(&mut self) -> AdchW { - AdchW::new(self, 0) - } - #[doc = "Bit 7 - Select Resolution of Conversions"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 7) - } -} -#[doc = "Command Low Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdl7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdl7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmdl7Spec; -impl crate::RegisterSpec for Cmdl7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmdl7::R`](R) reader structure"] -impl crate::Readable for Cmdl7Spec {} -#[doc = "`write(|w| ..)` method takes [`cmdl7::W`](W) writer structure"] -impl crate::Writable for Cmdl7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMDL7 to value 0"] -impl crate::Resettable for Cmdl7Spec {} diff --git a/mcxa276-pac/src/adc0/ctrl.rs b/mcxa276-pac/src/adc0/ctrl.rs deleted file mode 100644 index b774553a4..000000000 --- a/mcxa276-pac/src/adc0/ctrl.rs +++ /dev/null @@ -1,649 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "ADC Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adcen { - #[doc = "0: ADC is disabled."] - Disabled = 0, - #[doc = "1: ADC is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADCEN` reader - ADC Enable"] -pub type AdcenR = crate::BitReader; -impl AdcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adcen { - match self.bits { - false => Adcen::Disabled, - true => Adcen::Enabled, - } - } - #[doc = "ADC is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adcen::Disabled - } - #[doc = "ADC is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adcen::Enabled - } -} -#[doc = "Field `ADCEN` writer - ADC Enable"] -pub type AdcenW<'a, REG> = crate::BitWriter<'a, REG, Adcen>; -impl<'a, REG> AdcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ADC is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adcen::Disabled) - } - #[doc = "ADC is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adcen::Enabled) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rst { - #[doc = "0: ADC logic is not reset."] - ReleasedFromReset = 0, - #[doc = "1: ADC logic is reset."] - HeldInReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST` reader - Software Reset"] -pub type RstR = crate::BitReader; -impl RstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rst { - match self.bits { - false => Rst::ReleasedFromReset, - true => Rst::HeldInReset, - } - } - #[doc = "ADC logic is not reset."] - #[inline(always)] - pub fn is_released_from_reset(&self) -> bool { - *self == Rst::ReleasedFromReset - } - #[doc = "ADC logic is reset."] - #[inline(always)] - pub fn is_held_in_reset(&self) -> bool { - *self == Rst::HeldInReset - } -} -#[doc = "Field `RST` writer - Software Reset"] -pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; -impl<'a, REG> RstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ADC logic is not reset."] - #[inline(always)] - pub fn released_from_reset(self) -> &'a mut crate::W { - self.variant(Rst::ReleasedFromReset) - } - #[doc = "ADC logic is reset."] - #[inline(always)] - pub fn held_in_reset(self) -> &'a mut crate::W { - self.variant(Rst::HeldInReset) - } -} -#[doc = "Doze Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dozen { - #[doc = "0: ADC is enabled in low power mode."] - Enabled = 0, - #[doc = "1: ADC is disabled in low power mode."] - Disabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dozen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DOZEN` reader - Doze Enable"] -pub type DozenR = crate::BitReader; -impl DozenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dozen { - match self.bits { - false => Dozen::Enabled, - true => Dozen::Disabled, - } - } - #[doc = "ADC is enabled in low power mode."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dozen::Enabled - } - #[doc = "ADC is disabled in low power mode."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dozen::Disabled - } -} -#[doc = "Field `DOZEN` writer - Doze Enable"] -pub type DozenW<'a, REG> = crate::BitWriter<'a, REG, Dozen>; -impl<'a, REG> DozenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ADC is enabled in low power mode."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dozen::Enabled) - } - #[doc = "ADC is disabled in low power mode."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dozen::Disabled) - } -} -#[doc = "Auto-Calibration Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CalReq { - #[doc = "0: No request for hardware calibration has been made"] - NoCalibrationRequest = 0, - #[doc = "1: A request for hardware calibration has been made"] - CalibrationRequestPending = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CalReq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAL_REQ` reader - Auto-Calibration Request"] -pub type CalReqR = crate::BitReader; -impl CalReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CalReq { - match self.bits { - false => CalReq::NoCalibrationRequest, - true => CalReq::CalibrationRequestPending, - } - } - #[doc = "No request for hardware calibration has been made"] - #[inline(always)] - pub fn is_no_calibration_request(&self) -> bool { - *self == CalReq::NoCalibrationRequest - } - #[doc = "A request for hardware calibration has been made"] - #[inline(always)] - pub fn is_calibration_request_pending(&self) -> bool { - *self == CalReq::CalibrationRequestPending - } -} -#[doc = "Field `CAL_REQ` writer - Auto-Calibration Request"] -pub type CalReqW<'a, REG> = crate::BitWriter<'a, REG, CalReq>; -impl<'a, REG> CalReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No request for hardware calibration has been made"] - #[inline(always)] - pub fn no_calibration_request(self) -> &'a mut crate::W { - self.variant(CalReq::NoCalibrationRequest) - } - #[doc = "A request for hardware calibration has been made"] - #[inline(always)] - pub fn calibration_request_pending(self) -> &'a mut crate::W { - self.variant(CalReq::CalibrationRequestPending) - } -} -#[doc = "Offset Calibration Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Calofs { - #[doc = "0: No request for offset calibration has been made"] - NoActiveOffsetCalibrationRequest = 0, - #[doc = "1: Request for offset calibration function"] - OffsetCalibrationRequestPending = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Calofs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CALOFS` reader - Offset Calibration Request"] -pub type CalofsR = crate::BitReader; -impl CalofsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Calofs { - match self.bits { - false => Calofs::NoActiveOffsetCalibrationRequest, - true => Calofs::OffsetCalibrationRequestPending, - } - } - #[doc = "No request for offset calibration has been made"] - #[inline(always)] - pub fn is_no_active_offset_calibration_request(&self) -> bool { - *self == Calofs::NoActiveOffsetCalibrationRequest - } - #[doc = "Request for offset calibration function"] - #[inline(always)] - pub fn is_offset_calibration_request_pending(&self) -> bool { - *self == Calofs::OffsetCalibrationRequestPending - } -} -#[doc = "Field `CALOFS` writer - Offset Calibration Request"] -pub type CalofsW<'a, REG> = crate::BitWriter<'a, REG, Calofs>; -impl<'a, REG> CalofsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No request for offset calibration has been made"] - #[inline(always)] - pub fn no_active_offset_calibration_request(self) -> &'a mut crate::W { - self.variant(Calofs::NoActiveOffsetCalibrationRequest) - } - #[doc = "Request for offset calibration function"] - #[inline(always)] - pub fn offset_calibration_request_pending(self) -> &'a mut crate::W { - self.variant(Calofs::OffsetCalibrationRequestPending) - } -} -#[doc = "High Speed Mode Trim Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Calhs { - #[doc = "0: No request for high speed mode trim has been made"] - NoActiveHsTrimRequest = 0, - #[doc = "1: Request for high speed mode trim has been made"] - HsTrimRequestPending = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Calhs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CALHS` reader - High Speed Mode Trim Request"] -pub type CalhsR = crate::BitReader; -impl CalhsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Calhs { - match self.bits { - false => Calhs::NoActiveHsTrimRequest, - true => Calhs::HsTrimRequestPending, - } - } - #[doc = "No request for high speed mode trim has been made"] - #[inline(always)] - pub fn is_no_active_hs_trim_request(&self) -> bool { - *self == Calhs::NoActiveHsTrimRequest - } - #[doc = "Request for high speed mode trim has been made"] - #[inline(always)] - pub fn is_hs_trim_request_pending(&self) -> bool { - *self == Calhs::HsTrimRequestPending - } -} -#[doc = "Field `CALHS` writer - High Speed Mode Trim Request"] -pub type CalhsW<'a, REG> = crate::BitWriter<'a, REG, Calhs>; -impl<'a, REG> CalhsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No request for high speed mode trim has been made"] - #[inline(always)] - pub fn no_active_hs_trim_request(self) -> &'a mut crate::W { - self.variant(Calhs::NoActiveHsTrimRequest) - } - #[doc = "Request for high speed mode trim has been made"] - #[inline(always)] - pub fn hs_trim_request_pending(self) -> &'a mut crate::W { - self.variant(Calhs::HsTrimRequestPending) - } -} -#[doc = "Reset FIFO 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rstfifo0 { - #[doc = "0: No effect."] - NoAction = 0, - #[doc = "1: FIFO 0 is reset."] - TriggerReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rstfifo0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSTFIFO0` reader - Reset FIFO 0"] -pub type Rstfifo0R = crate::BitReader; -impl Rstfifo0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rstfifo0 { - match self.bits { - false => Rstfifo0::NoAction, - true => Rstfifo0::TriggerReset, - } - } - #[doc = "No effect."] - #[inline(always)] - pub fn is_no_action(&self) -> bool { - *self == Rstfifo0::NoAction - } - #[doc = "FIFO 0 is reset."] - #[inline(always)] - pub fn is_trigger_reset(&self) -> bool { - *self == Rstfifo0::TriggerReset - } -} -#[doc = "Field `RSTFIFO0` writer - Reset FIFO 0"] -pub type Rstfifo0W<'a, REG> = crate::BitWriter<'a, REG, Rstfifo0>; -impl<'a, REG> Rstfifo0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect."] - #[inline(always)] - pub fn no_action(self) -> &'a mut crate::W { - self.variant(Rstfifo0::NoAction) - } - #[doc = "FIFO 0 is reset."] - #[inline(always)] - pub fn trigger_reset(self) -> &'a mut crate::W { - self.variant(Rstfifo0::TriggerReset) - } -} -#[doc = "Auto-Calibration Averages\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum CalAvgs { - #[doc = "0: Single conversion."] - NoAverage = 0, - #[doc = "1: 2 conversions averaged."] - Average2 = 1, - #[doc = "2: 4 conversions averaged."] - Average4 = 2, - #[doc = "3: 8 conversions averaged."] - Average8 = 3, - #[doc = "4: 16 conversions averaged."] - Average16 = 4, - #[doc = "5: 32 conversions averaged."] - Average32 = 5, - #[doc = "6: 64 conversions averaged."] - Average64 = 6, - #[doc = "7: 128 conversions averaged."] - Average128 = 7, - #[doc = "8: 256 conversions averaged."] - Average256 = 8, - #[doc = "9: 512 conversions averaged."] - Average512 = 9, - #[doc = "10: 1024 conversions averaged."] - Average1024 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: CalAvgs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for CalAvgs { - type Ux = u8; -} -impl crate::IsEnum for CalAvgs {} -#[doc = "Field `CAL_AVGS` reader - Auto-Calibration Averages"] -pub type CalAvgsR = crate::FieldReader; -impl CalAvgsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(CalAvgs::NoAverage), - 1 => Some(CalAvgs::Average2), - 2 => Some(CalAvgs::Average4), - 3 => Some(CalAvgs::Average8), - 4 => Some(CalAvgs::Average16), - 5 => Some(CalAvgs::Average32), - 6 => Some(CalAvgs::Average64), - 7 => Some(CalAvgs::Average128), - 8 => Some(CalAvgs::Average256), - 9 => Some(CalAvgs::Average512), - 10 => Some(CalAvgs::Average1024), - _ => None, - } - } - #[doc = "Single conversion."] - #[inline(always)] - pub fn is_no_average(&self) -> bool { - *self == CalAvgs::NoAverage - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn is_average_2(&self) -> bool { - *self == CalAvgs::Average2 - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn is_average_4(&self) -> bool { - *self == CalAvgs::Average4 - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn is_average_8(&self) -> bool { - *self == CalAvgs::Average8 - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn is_average_16(&self) -> bool { - *self == CalAvgs::Average16 - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn is_average_32(&self) -> bool { - *self == CalAvgs::Average32 - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn is_average_64(&self) -> bool { - *self == CalAvgs::Average64 - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn is_average_128(&self) -> bool { - *self == CalAvgs::Average128 - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn is_average_256(&self) -> bool { - *self == CalAvgs::Average256 - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn is_average_512(&self) -> bool { - *self == CalAvgs::Average512 - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn is_average_1024(&self) -> bool { - *self == CalAvgs::Average1024 - } -} -#[doc = "Field `CAL_AVGS` writer - Auto-Calibration Averages"] -pub type CalAvgsW<'a, REG> = crate::FieldWriter<'a, REG, 4, CalAvgs>; -impl<'a, REG> CalAvgsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single conversion."] - #[inline(always)] - pub fn no_average(self) -> &'a mut crate::W { - self.variant(CalAvgs::NoAverage) - } - #[doc = "2 conversions averaged."] - #[inline(always)] - pub fn average_2(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average2) - } - #[doc = "4 conversions averaged."] - #[inline(always)] - pub fn average_4(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average4) - } - #[doc = "8 conversions averaged."] - #[inline(always)] - pub fn average_8(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average8) - } - #[doc = "16 conversions averaged."] - #[inline(always)] - pub fn average_16(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average16) - } - #[doc = "32 conversions averaged."] - #[inline(always)] - pub fn average_32(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average32) - } - #[doc = "64 conversions averaged."] - #[inline(always)] - pub fn average_64(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average64) - } - #[doc = "128 conversions averaged."] - #[inline(always)] - pub fn average_128(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average128) - } - #[doc = "256 conversions averaged."] - #[inline(always)] - pub fn average_256(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average256) - } - #[doc = "512 conversions averaged."] - #[inline(always)] - pub fn average_512(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average512) - } - #[doc = "1024 conversions averaged."] - #[inline(always)] - pub fn average_1024(self) -> &'a mut crate::W { - self.variant(CalAvgs::Average1024) - } -} -impl R { - #[doc = "Bit 0 - ADC Enable"] - #[inline(always)] - pub fn adcen(&self) -> AdcenR { - AdcenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&self) -> RstR { - RstR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Doze Enable"] - #[inline(always)] - pub fn dozen(&self) -> DozenR { - DozenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Auto-Calibration Request"] - #[inline(always)] - pub fn cal_req(&self) -> CalReqR { - CalReqR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Offset Calibration Request"] - #[inline(always)] - pub fn calofs(&self) -> CalofsR { - CalofsR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 6 - High Speed Mode Trim Request"] - #[inline(always)] - pub fn calhs(&self) -> CalhsR { - CalhsR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - Reset FIFO 0"] - #[inline(always)] - pub fn rstfifo0(&self) -> Rstfifo0R { - Rstfifo0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 16:19 - Auto-Calibration Averages"] - #[inline(always)] - pub fn cal_avgs(&self) -> CalAvgsR { - CalAvgsR::new(((self.bits >> 16) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - ADC Enable"] - #[inline(always)] - pub fn adcen(&mut self) -> AdcenW { - AdcenW::new(self, 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&mut self) -> RstW { - RstW::new(self, 1) - } - #[doc = "Bit 2 - Doze Enable"] - #[inline(always)] - pub fn dozen(&mut self) -> DozenW { - DozenW::new(self, 2) - } - #[doc = "Bit 3 - Auto-Calibration Request"] - #[inline(always)] - pub fn cal_req(&mut self) -> CalReqW { - CalReqW::new(self, 3) - } - #[doc = "Bit 4 - Offset Calibration Request"] - #[inline(always)] - pub fn calofs(&mut self) -> CalofsW { - CalofsW::new(self, 4) - } - #[doc = "Bit 6 - High Speed Mode Trim Request"] - #[inline(always)] - pub fn calhs(&mut self) -> CalhsW { - CalhsW::new(self, 6) - } - #[doc = "Bit 8 - Reset FIFO 0"] - #[inline(always)] - pub fn rstfifo0(&mut self) -> Rstfifo0W { - Rstfifo0W::new(self, 8) - } - #[doc = "Bits 16:19 - Auto-Calibration Averages"] - #[inline(always)] - pub fn cal_avgs(&mut self) -> CalAvgsW { - CalAvgsW::new(self, 16) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/adc0/cv.rs b/mcxa276-pac/src/adc0/cv.rs deleted file mode 100644 index a40845af8..000000000 --- a/mcxa276-pac/src/adc0/cv.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CV%s` reader"] -pub type R = crate::R; -#[doc = "Register `CV%s` writer"] -pub type W = crate::W; -#[doc = "Field `CVL` reader - Compare Value Low"] -pub type CvlR = crate::FieldReader; -#[doc = "Field `CVL` writer - Compare Value Low"] -pub type CvlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `CVH` reader - Compare Value High"] -pub type CvhR = crate::FieldReader; -#[doc = "Field `CVH` writer - Compare Value High"] -pub type CvhW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Compare Value Low"] - #[inline(always)] - pub fn cvl(&self) -> CvlR { - CvlR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Compare Value High"] - #[inline(always)] - pub fn cvh(&self) -> CvhR { - CvhR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Compare Value Low"] - #[inline(always)] - pub fn cvl(&mut self) -> CvlW { - CvlW::new(self, 0) - } - #[doc = "Bits 16:31 - Compare Value High"] - #[inline(always)] - pub fn cvh(&mut self) -> CvhW { - CvhW::new(self, 16) - } -} -#[doc = "Compare Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CvSpec; -impl crate::RegisterSpec for CvSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cv::R`](R) reader structure"] -impl crate::Readable for CvSpec {} -#[doc = "`write(|w| ..)` method takes [`cv::W`](W) writer structure"] -impl crate::Writable for CvSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CV%s to value 0"] -impl crate::Resettable for CvSpec {} diff --git a/mcxa276-pac/src/adc0/de.rs b/mcxa276-pac/src/adc0/de.rs deleted file mode 100644 index 6a75e90a3..000000000 --- a/mcxa276-pac/src/adc0/de.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `DE` reader"] -pub type R = crate::R; -#[doc = "Register `DE` writer"] -pub type W = crate::W; -#[doc = "FIFO 0 Watermark DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fwmde0 { - #[doc = "0: DMA request disabled."] - Disabled = 0, - #[doc = "1: DMA request enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fwmde0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FWMDE0` reader - FIFO 0 Watermark DMA Enable"] -pub type Fwmde0R = crate::BitReader; -impl Fwmde0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fwmde0 { - match self.bits { - false => Fwmde0::Disabled, - true => Fwmde0::Enabled, - } - } - #[doc = "DMA request disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fwmde0::Disabled - } - #[doc = "DMA request enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fwmde0::Enabled - } -} -#[doc = "Field `FWMDE0` writer - FIFO 0 Watermark DMA Enable"] -pub type Fwmde0W<'a, REG> = crate::BitWriter<'a, REG, Fwmde0>; -impl<'a, REG> Fwmde0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DMA request disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fwmde0::Disabled) - } - #[doc = "DMA request enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fwmde0::Enabled) - } -} -impl R { - #[doc = "Bit 0 - FIFO 0 Watermark DMA Enable"] - #[inline(always)] - pub fn fwmde0(&self) -> Fwmde0R { - Fwmde0R::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FIFO 0 Watermark DMA Enable"] - #[inline(always)] - pub fn fwmde0(&mut self) -> Fwmde0W { - Fwmde0W::new(self, 0) - } -} -#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DeSpec; -impl crate::RegisterSpec for DeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`de::R`](R) reader structure"] -impl crate::Readable for DeSpec {} -#[doc = "`write(|w| ..)` method takes [`de::W`](W) writer structure"] -impl crate::Writable for DeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DE to value 0"] -impl crate::Resettable for DeSpec {} diff --git a/mcxa276-pac/src/adc0/fctrl0.rs b/mcxa276-pac/src/adc0/fctrl0.rs deleted file mode 100644 index 3acc78aad..000000000 --- a/mcxa276-pac/src/adc0/fctrl0.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `FCTRL0` reader"] -pub type R = crate::R; -#[doc = "Register `FCTRL0` writer"] -pub type W = crate::W; -#[doc = "Field `FCOUNT` reader - Result FIFO Counter"] -pub type FcountR = crate::FieldReader; -#[doc = "Field `FWMARK` reader - Watermark Level Selection"] -pub type FwmarkR = crate::FieldReader; -#[doc = "Field `FWMARK` writer - Watermark Level Selection"] -pub type FwmarkW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:3 - Result FIFO Counter"] - #[inline(always)] - pub fn fcount(&self) -> FcountR { - FcountR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 16:18 - Watermark Level Selection"] - #[inline(always)] - pub fn fwmark(&self) -> FwmarkR { - FwmarkR::new(((self.bits >> 16) & 7) as u8) - } -} -impl W { - #[doc = "Bits 16:18 - Watermark Level Selection"] - #[inline(always)] - pub fn fwmark(&mut self) -> FwmarkW { - FwmarkW::new(self, 16) - } -} -#[doc = "FIFO Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Fctrl0Spec; -impl crate::RegisterSpec for Fctrl0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fctrl0::R`](R) reader structure"] -impl crate::Readable for Fctrl0Spec {} -#[doc = "`write(|w| ..)` method takes [`fctrl0::W`](W) writer structure"] -impl crate::Writable for Fctrl0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCTRL0 to value 0"] -impl crate::Resettable for Fctrl0Spec {} diff --git a/mcxa276-pac/src/adc0/gcc0.rs b/mcxa276-pac/src/adc0/gcc0.rs deleted file mode 100644 index 6b612c927..000000000 --- a/mcxa276-pac/src/adc0/gcc0.rs +++ /dev/null @@ -1,61 +0,0 @@ -#[doc = "Register `GCC0` reader"] -pub type R = crate::R; -#[doc = "Field `GAIN_CAL` reader - Gain Calibration Value"] -pub type GainCalR = crate::FieldReader; -#[doc = "Gain Calibration Value Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdy { - #[doc = "0: The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set."] - GainCalNotValid = 0, - #[doc = "1: The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa\\[GCALR\\]."] - HardwareCalRoutineCompleted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdy) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDY` reader - Gain Calibration Value Valid"] -pub type RdyR = crate::BitReader; -impl RdyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdy { - match self.bits { - false => Rdy::GainCalNotValid, - true => Rdy::HardwareCalRoutineCompleted, - } - } - #[doc = "The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set."] - #[inline(always)] - pub fn is_gain_cal_not_valid(&self) -> bool { - *self == Rdy::GainCalNotValid - } - #[doc = "The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa\\[GCALR\\]."] - #[inline(always)] - pub fn is_hardware_cal_routine_completed(&self) -> bool { - *self == Rdy::HardwareCalRoutineCompleted - } -} -impl R { - #[doc = "Bits 0:15 - Gain Calibration Value"] - #[inline(always)] - pub fn gain_cal(&self) -> GainCalR { - GainCalR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 24 - Gain Calibration Value Valid"] - #[inline(always)] - pub fn rdy(&self) -> RdyR { - RdyR::new(((self.bits >> 24) & 1) != 0) - } -} -#[doc = "Gain Calibration Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcc0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Gcc0Spec; -impl crate::RegisterSpec for Gcc0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gcc0::R`](R) reader structure"] -impl crate::Readable for Gcc0Spec {} -#[doc = "`reset()` method sets GCC0 to value 0"] -impl crate::Resettable for Gcc0Spec {} diff --git a/mcxa276-pac/src/adc0/gcr0.rs b/mcxa276-pac/src/adc0/gcr0.rs deleted file mode 100644 index c62e2dc56..000000000 --- a/mcxa276-pac/src/adc0/gcr0.rs +++ /dev/null @@ -1,100 +0,0 @@ -#[doc = "Register `GCR0` reader"] -pub type R = crate::R; -#[doc = "Register `GCR0` writer"] -pub type W = crate::W; -#[doc = "Field `GCALR` reader - Gain Calculation Result"] -pub type GcalrR = crate::FieldReader; -#[doc = "Field `GCALR` writer - Gain Calculation Result"] -pub type GcalrW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; -#[doc = "Gain Calculation Ready\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdy { - #[doc = "0: The GCALR value is invalid."] - NotValid = 0, - #[doc = "1: The GCALR value is valid."] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdy) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDY` reader - Gain Calculation Ready"] -pub type RdyR = crate::BitReader; -impl RdyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdy { - match self.bits { - false => Rdy::NotValid, - true => Rdy::Valid, - } - } - #[doc = "The GCALR value is invalid."] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Rdy::NotValid - } - #[doc = "The GCALR value is valid."] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Rdy::Valid - } -} -#[doc = "Field `RDY` writer - Gain Calculation Ready"] -pub type RdyW<'a, REG> = crate::BitWriter<'a, REG, Rdy>; -impl<'a, REG> RdyW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The GCALR value is invalid."] - #[inline(always)] - pub fn not_valid(self) -> &'a mut crate::W { - self.variant(Rdy::NotValid) - } - #[doc = "The GCALR value is valid."] - #[inline(always)] - pub fn valid(self) -> &'a mut crate::W { - self.variant(Rdy::Valid) - } -} -impl R { - #[doc = "Bits 0:16 - Gain Calculation Result"] - #[inline(always)] - pub fn gcalr(&self) -> GcalrR { - GcalrR::new(self.bits & 0x0001_ffff) - } - #[doc = "Bit 24 - Gain Calculation Ready"] - #[inline(always)] - pub fn rdy(&self) -> RdyR { - RdyR::new(((self.bits >> 24) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:16 - Gain Calculation Result"] - #[inline(always)] - pub fn gcalr(&mut self) -> GcalrW { - GcalrW::new(self, 0) - } - #[doc = "Bit 24 - Gain Calculation Ready"] - #[inline(always)] - pub fn rdy(&mut self) -> RdyW { - RdyW::new(self, 24) - } -} -#[doc = "Gain Calculation Result\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Gcr0Spec; -impl crate::RegisterSpec for Gcr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gcr0::R`](R) reader structure"] -impl crate::Readable for Gcr0Spec {} -#[doc = "`write(|w| ..)` method takes [`gcr0::W`](W) writer structure"] -impl crate::Writable for Gcr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GCR0 to value 0x0001_0000"] -impl crate::Resettable for Gcr0Spec { - const RESET_VALUE: u32 = 0x0001_0000; -} diff --git a/mcxa276-pac/src/adc0/hstrim.rs b/mcxa276-pac/src/adc0/hstrim.rs deleted file mode 100644 index b4c32e480..000000000 --- a/mcxa276-pac/src/adc0/hstrim.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `HSTRIM` reader"] -pub type R = crate::R; -#[doc = "Register `HSTRIM` writer"] -pub type W = crate::W; -#[doc = "Field `HSTRIM` reader - Trim for High Speed Conversions"] -pub type HstrimR = crate::FieldReader; -#[doc = "Field `HSTRIM` writer - Trim for High Speed Conversions"] -pub type HstrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bits 0:4 - Trim for High Speed Conversions"] - #[inline(always)] - pub fn hstrim(&self) -> HstrimR { - HstrimR::new((self.bits & 0x1f) as u8) - } -} -impl W { - #[doc = "Bits 0:4 - Trim for High Speed Conversions"] - #[inline(always)] - pub fn hstrim(&mut self) -> HstrimW { - HstrimW::new(self, 0) - } -} -#[doc = "High Speed Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hstrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hstrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct HstrimSpec; -impl crate::RegisterSpec for HstrimSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`hstrim::R`](R) reader structure"] -impl crate::Readable for HstrimSpec {} -#[doc = "`write(|w| ..)` method takes [`hstrim::W`](W) writer structure"] -impl crate::Writable for HstrimSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets HSTRIM to value 0"] -impl crate::Resettable for HstrimSpec {} diff --git a/mcxa276-pac/src/adc0/ie.rs b/mcxa276-pac/src/adc0/ie.rs deleted file mode 100644 index 660d53d43..000000000 --- a/mcxa276-pac/src/adc0/ie.rs +++ /dev/null @@ -1,397 +0,0 @@ -#[doc = "Register `IE` reader"] -pub type R = crate::R; -#[doc = "Register `IE` writer"] -pub type W = crate::W; -#[doc = "FIFO 0 Watermark Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fwmie0 { - #[doc = "0: FIFO 0 watermark interrupts are not enabled."] - Disabled = 0, - #[doc = "1: FIFO 0 watermark interrupts are enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fwmie0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FWMIE0` reader - FIFO 0 Watermark Interrupt Enable"] -pub type Fwmie0R = crate::BitReader; -impl Fwmie0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fwmie0 { - match self.bits { - false => Fwmie0::Disabled, - true => Fwmie0::Enabled, - } - } - #[doc = "FIFO 0 watermark interrupts are not enabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fwmie0::Disabled - } - #[doc = "FIFO 0 watermark interrupts are enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fwmie0::Enabled - } -} -#[doc = "Field `FWMIE0` writer - FIFO 0 Watermark Interrupt Enable"] -pub type Fwmie0W<'a, REG> = crate::BitWriter<'a, REG, Fwmie0>; -impl<'a, REG> Fwmie0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FIFO 0 watermark interrupts are not enabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fwmie0::Disabled) - } - #[doc = "FIFO 0 watermark interrupts are enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fwmie0::Enabled) - } -} -#[doc = "Result FIFO 0 Overflow Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fofie0 { - #[doc = "0: FIFO 0 overflow interrupts are not enabled."] - Disabled = 0, - #[doc = "1: FIFO 0 overflow interrupts are enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fofie0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FOFIE0` reader - Result FIFO 0 Overflow Interrupt Enable"] -pub type Fofie0R = crate::BitReader; -impl Fofie0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fofie0 { - match self.bits { - false => Fofie0::Disabled, - true => Fofie0::Enabled, - } - } - #[doc = "FIFO 0 overflow interrupts are not enabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fofie0::Disabled - } - #[doc = "FIFO 0 overflow interrupts are enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fofie0::Enabled - } -} -#[doc = "Field `FOFIE0` writer - Result FIFO 0 Overflow Interrupt Enable"] -pub type Fofie0W<'a, REG> = crate::BitWriter<'a, REG, Fofie0>; -impl<'a, REG> Fofie0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FIFO 0 overflow interrupts are not enabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fofie0::Disabled) - } - #[doc = "FIFO 0 overflow interrupts are enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fofie0::Enabled) - } -} -#[doc = "Trigger Exception Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TexcIe { - #[doc = "0: Trigger exception interrupts are disabled."] - Disabled = 0, - #[doc = "1: Trigger exception interrupts are enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TexcIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TEXC_IE` reader - Trigger Exception Interrupt Enable"] -pub type TexcIeR = crate::BitReader; -impl TexcIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TexcIe { - match self.bits { - false => TexcIe::Disabled, - true => TexcIe::Enabled, - } - } - #[doc = "Trigger exception interrupts are disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == TexcIe::Disabled - } - #[doc = "Trigger exception interrupts are enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == TexcIe::Enabled - } -} -#[doc = "Field `TEXC_IE` writer - Trigger Exception Interrupt Enable"] -pub type TexcIeW<'a, REG> = crate::BitWriter<'a, REG, TexcIe>; -impl<'a, REG> TexcIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trigger exception interrupts are disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(TexcIe::Disabled) - } - #[doc = "Trigger exception interrupts are enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(TexcIe::Enabled) - } -} -#[doc = "Trigger Completion Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum TcompIe { - #[doc = "0: Trigger completion interrupts are disabled."] - Disabled = 0, - #[doc = "1: Trigger completion interrupts are enabled for trigger source 0 only."] - Trigger0CompleteEnabled = 1, - #[doc = "2: Trigger completion interrupts are enabled for trigger source 1 only."] - Trigger1CompleteEnabled = 2, - #[doc = "3: Associated trigger completion interrupts are enabled."] - TriggerXCompleteEnabled3 = 3, - #[doc = "4: Associated trigger completion interrupts are enabled."] - TriggerXCompleteEnabled4 = 4, - #[doc = "5: Associated trigger completion interrupts are enabled."] - TriggerXCompleteEnabled5 = 5, - #[doc = "6: Associated trigger completion interrupts are enabled."] - TriggerXCompleteEnabled6 = 6, - #[doc = "7: Associated trigger completion interrupts are enabled."] - TriggerXCompleteEnabled7 = 7, - #[doc = "8: Associated trigger completion interrupts are enabled."] - TriggerXCompleteEnabled8 = 8, - #[doc = "9: Associated trigger completion interrupts are enabled."] - TriggerXCompleteEnabled9 = 9, - #[doc = "15: Trigger completion interrupts are enabled for every trigger source."] - AllTriggerCompletesEnabled = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: TcompIe) -> Self { - variant as _ - } -} -impl crate::FieldSpec for TcompIe { - type Ux = u8; -} -impl crate::IsEnum for TcompIe {} -#[doc = "Field `TCOMP_IE` reader - Trigger Completion Interrupt Enable"] -pub type TcompIeR = crate::FieldReader; -impl TcompIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(TcompIe::Disabled), - 1 => Some(TcompIe::Trigger0CompleteEnabled), - 2 => Some(TcompIe::Trigger1CompleteEnabled), - 3 => Some(TcompIe::TriggerXCompleteEnabled3), - 4 => Some(TcompIe::TriggerXCompleteEnabled4), - 5 => Some(TcompIe::TriggerXCompleteEnabled5), - 6 => Some(TcompIe::TriggerXCompleteEnabled6), - 7 => Some(TcompIe::TriggerXCompleteEnabled7), - 8 => Some(TcompIe::TriggerXCompleteEnabled8), - 9 => Some(TcompIe::TriggerXCompleteEnabled9), - 15 => Some(TcompIe::AllTriggerCompletesEnabled), - _ => None, - } - } - #[doc = "Trigger completion interrupts are disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == TcompIe::Disabled - } - #[doc = "Trigger completion interrupts are enabled for trigger source 0 only."] - #[inline(always)] - pub fn is_trigger_0_complete_enabled(&self) -> bool { - *self == TcompIe::Trigger0CompleteEnabled - } - #[doc = "Trigger completion interrupts are enabled for trigger source 1 only."] - #[inline(always)] - pub fn is_trigger_1_complete_enabled(&self) -> bool { - *self == TcompIe::Trigger1CompleteEnabled - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn is_trigger_x_complete_enabled_3(&self) -> bool { - *self == TcompIe::TriggerXCompleteEnabled3 - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn is_trigger_x_complete_enabled_4(&self) -> bool { - *self == TcompIe::TriggerXCompleteEnabled4 - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn is_trigger_x_complete_enabled_5(&self) -> bool { - *self == TcompIe::TriggerXCompleteEnabled5 - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn is_trigger_x_complete_enabled_6(&self) -> bool { - *self == TcompIe::TriggerXCompleteEnabled6 - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn is_trigger_x_complete_enabled_7(&self) -> bool { - *self == TcompIe::TriggerXCompleteEnabled7 - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn is_trigger_x_complete_enabled_8(&self) -> bool { - *self == TcompIe::TriggerXCompleteEnabled8 - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn is_trigger_x_complete_enabled_9(&self) -> bool { - *self == TcompIe::TriggerXCompleteEnabled9 - } - #[doc = "Trigger completion interrupts are enabled for every trigger source."] - #[inline(always)] - pub fn is_all_trigger_completes_enabled(&self) -> bool { - *self == TcompIe::AllTriggerCompletesEnabled - } -} -#[doc = "Field `TCOMP_IE` writer - Trigger Completion Interrupt Enable"] -pub type TcompIeW<'a, REG> = crate::FieldWriter<'a, REG, 4, TcompIe>; -impl<'a, REG> TcompIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Trigger completion interrupts are disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(TcompIe::Disabled) - } - #[doc = "Trigger completion interrupts are enabled for trigger source 0 only."] - #[inline(always)] - pub fn trigger_0_complete_enabled(self) -> &'a mut crate::W { - self.variant(TcompIe::Trigger0CompleteEnabled) - } - #[doc = "Trigger completion interrupts are enabled for trigger source 1 only."] - #[inline(always)] - pub fn trigger_1_complete_enabled(self) -> &'a mut crate::W { - self.variant(TcompIe::Trigger1CompleteEnabled) - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn trigger_x_complete_enabled_3(self) -> &'a mut crate::W { - self.variant(TcompIe::TriggerXCompleteEnabled3) - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn trigger_x_complete_enabled_4(self) -> &'a mut crate::W { - self.variant(TcompIe::TriggerXCompleteEnabled4) - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn trigger_x_complete_enabled_5(self) -> &'a mut crate::W { - self.variant(TcompIe::TriggerXCompleteEnabled5) - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn trigger_x_complete_enabled_6(self) -> &'a mut crate::W { - self.variant(TcompIe::TriggerXCompleteEnabled6) - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn trigger_x_complete_enabled_7(self) -> &'a mut crate::W { - self.variant(TcompIe::TriggerXCompleteEnabled7) - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn trigger_x_complete_enabled_8(self) -> &'a mut crate::W { - self.variant(TcompIe::TriggerXCompleteEnabled8) - } - #[doc = "Associated trigger completion interrupts are enabled."] - #[inline(always)] - pub fn trigger_x_complete_enabled_9(self) -> &'a mut crate::W { - self.variant(TcompIe::TriggerXCompleteEnabled9) - } - #[doc = "Trigger completion interrupts are enabled for every trigger source."] - #[inline(always)] - pub fn all_trigger_completes_enabled(self) -> &'a mut crate::W { - self.variant(TcompIe::AllTriggerCompletesEnabled) - } -} -impl R { - #[doc = "Bit 0 - FIFO 0 Watermark Interrupt Enable"] - #[inline(always)] - pub fn fwmie0(&self) -> Fwmie0R { - Fwmie0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Result FIFO 0 Overflow Interrupt Enable"] - #[inline(always)] - pub fn fofie0(&self) -> Fofie0R { - Fofie0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - Trigger Exception Interrupt Enable"] - #[inline(always)] - pub fn texc_ie(&self) -> TexcIeR { - TexcIeR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 16:19 - Trigger Completion Interrupt Enable"] - #[inline(always)] - pub fn tcomp_ie(&self) -> TcompIeR { - TcompIeR::new(((self.bits >> 16) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - FIFO 0 Watermark Interrupt Enable"] - #[inline(always)] - pub fn fwmie0(&mut self) -> Fwmie0W { - Fwmie0W::new(self, 0) - } - #[doc = "Bit 1 - Result FIFO 0 Overflow Interrupt Enable"] - #[inline(always)] - pub fn fofie0(&mut self) -> Fofie0W { - Fofie0W::new(self, 1) - } - #[doc = "Bit 8 - Trigger Exception Interrupt Enable"] - #[inline(always)] - pub fn texc_ie(&mut self) -> TexcIeW { - TexcIeW::new(self, 8) - } - #[doc = "Bits 16:19 - Trigger Completion Interrupt Enable"] - #[inline(always)] - pub fn tcomp_ie(&mut self) -> TcompIeW { - TcompIeW::new(self, 16) - } -} -#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IeSpec; -impl crate::RegisterSpec for IeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ie::R`](R) reader structure"] -impl crate::Readable for IeSpec {} -#[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"] -impl crate::Writable for IeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IE to value 0"] -impl crate::Resettable for IeSpec {} diff --git a/mcxa276-pac/src/adc0/ofstrim.rs b/mcxa276-pac/src/adc0/ofstrim.rs deleted file mode 100644 index db8115307..000000000 --- a/mcxa276-pac/src/adc0/ofstrim.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `OFSTRIM` reader"] -pub type R = crate::R; -#[doc = "Register `OFSTRIM` writer"] -pub type W = crate::W; -#[doc = "Field `OFSTRIM` reader - Trim for Offset"] -pub type OfstrimR = crate::FieldReader; -#[doc = "Field `OFSTRIM` writer - Trim for Offset"] -pub type OfstrimW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:9 - Trim for Offset"] - #[inline(always)] - pub fn ofstrim(&self) -> OfstrimR { - OfstrimR::new((self.bits & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:9 - Trim for Offset"] - #[inline(always)] - pub fn ofstrim(&mut self) -> OfstrimW { - OfstrimW::new(self, 0) - } -} -#[doc = "Offset Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ofstrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ofstrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OfstrimSpec; -impl crate::RegisterSpec for OfstrimSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ofstrim::R`](R) reader structure"] -impl crate::Readable for OfstrimSpec {} -#[doc = "`write(|w| ..)` method takes [`ofstrim::W`](W) writer structure"] -impl crate::Writable for OfstrimSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets OFSTRIM to value 0"] -impl crate::Resettable for OfstrimSpec {} diff --git a/mcxa276-pac/src/adc0/param.rs b/mcxa276-pac/src/adc0/param.rs deleted file mode 100644 index 7ad41472c..000000000 --- a/mcxa276-pac/src/adc0/param.rs +++ /dev/null @@ -1,115 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "Field `TRIG_NUM` reader - Trigger Number"] -pub type TrigNumR = crate::FieldReader; -#[doc = "Result FIFO Depth\n\nValue on reset: 8"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fifosize { - #[doc = "1: Result FIFO depth = 2 dataword."] - Entries2 = 1, - #[doc = "4: Result FIFO depth = 4 datawords."] - Entries4 = 4, - #[doc = "8: Result FIFO depth = 8 datawords."] - Entries8 = 8, - #[doc = "16: Result FIFO depth = 16 datawords."] - Entries16 = 16, - #[doc = "32: Result FIFO depth = 32 datawords."] - Entries32 = 32, - #[doc = "64: Result FIFO depth = 64 datawords."] - Entries64 = 64, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fifosize) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fifosize { - type Ux = u8; -} -impl crate::IsEnum for Fifosize {} -#[doc = "Field `FIFOSIZE` reader - Result FIFO Depth"] -pub type FifosizeR = crate::FieldReader; -impl FifosizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Fifosize::Entries2), - 4 => Some(Fifosize::Entries4), - 8 => Some(Fifosize::Entries8), - 16 => Some(Fifosize::Entries16), - 32 => Some(Fifosize::Entries32), - 64 => Some(Fifosize::Entries64), - _ => None, - } - } - #[doc = "Result FIFO depth = 2 dataword."] - #[inline(always)] - pub fn is_entries_2(&self) -> bool { - *self == Fifosize::Entries2 - } - #[doc = "Result FIFO depth = 4 datawords."] - #[inline(always)] - pub fn is_entries_4(&self) -> bool { - *self == Fifosize::Entries4 - } - #[doc = "Result FIFO depth = 8 datawords."] - #[inline(always)] - pub fn is_entries_8(&self) -> bool { - *self == Fifosize::Entries8 - } - #[doc = "Result FIFO depth = 16 datawords."] - #[inline(always)] - pub fn is_entries_16(&self) -> bool { - *self == Fifosize::Entries16 - } - #[doc = "Result FIFO depth = 32 datawords."] - #[inline(always)] - pub fn is_entries_32(&self) -> bool { - *self == Fifosize::Entries32 - } - #[doc = "Result FIFO depth = 64 datawords."] - #[inline(always)] - pub fn is_entries_64(&self) -> bool { - *self == Fifosize::Entries64 - } -} -#[doc = "Field `CV_NUM` reader - Compare Value Number"] -pub type CvNumR = crate::FieldReader; -#[doc = "Field `CMD_NUM` reader - Command Buffer Number"] -pub type CmdNumR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Trigger Number"] - #[inline(always)] - pub fn trig_num(&self) -> TrigNumR { - TrigNumR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Result FIFO Depth"] - #[inline(always)] - pub fn fifosize(&self) -> FifosizeR { - FifosizeR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Compare Value Number"] - #[inline(always)] - pub fn cv_num(&self) -> CvNumR { - CvNumR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Command Buffer Number"] - #[inline(always)] - pub fn cmd_num(&self) -> CmdNumR { - CmdNumR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x0707_0804"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x0707_0804; -} diff --git a/mcxa276-pac/src/adc0/pause.rs b/mcxa276-pac/src/adc0/pause.rs deleted file mode 100644 index 2f3ea34b7..000000000 --- a/mcxa276-pac/src/adc0/pause.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `PAUSE` reader"] -pub type R = crate::R; -#[doc = "Register `PAUSE` writer"] -pub type W = crate::W; -#[doc = "Field `PAUSEDLY` reader - Pause Delay"] -pub type PausedlyR = crate::FieldReader; -#[doc = "Field `PAUSEDLY` writer - Pause Delay"] -pub type PausedlyW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "PAUSE Option Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pauseen { - #[doc = "0: Pause operation disabled"] - Disabled = 0, - #[doc = "1: Pause operation enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pauseen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PAUSEEN` reader - PAUSE Option Enable"] -pub type PauseenR = crate::BitReader; -impl PauseenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pauseen { - match self.bits { - false => Pauseen::Disabled, - true => Pauseen::Enabled, - } - } - #[doc = "Pause operation disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pauseen::Disabled - } - #[doc = "Pause operation enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pauseen::Enabled - } -} -#[doc = "Field `PAUSEEN` writer - PAUSE Option Enable"] -pub type PauseenW<'a, REG> = crate::BitWriter<'a, REG, Pauseen>; -impl<'a, REG> PauseenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pause operation disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pauseen::Disabled) - } - #[doc = "Pause operation enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pauseen::Enabled) - } -} -impl R { - #[doc = "Bits 0:8 - Pause Delay"] - #[inline(always)] - pub fn pausedly(&self) -> PausedlyR { - PausedlyR::new((self.bits & 0x01ff) as u16) - } - #[doc = "Bit 31 - PAUSE Option Enable"] - #[inline(always)] - pub fn pauseen(&self) -> PauseenR { - PauseenR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:8 - Pause Delay"] - #[inline(always)] - pub fn pausedly(&mut self) -> PausedlyW { - PausedlyW::new(self, 0) - } - #[doc = "Bit 31 - PAUSE Option Enable"] - #[inline(always)] - pub fn pauseen(&mut self) -> PauseenW { - PauseenW::new(self, 31) - } -} -#[doc = "Pause Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PauseSpec; -impl crate::RegisterSpec for PauseSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pause::R`](R) reader structure"] -impl crate::Readable for PauseSpec {} -#[doc = "`write(|w| ..)` method takes [`pause::W`](W) writer structure"] -impl crate::Writable for PauseSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PAUSE to value 0"] -impl crate::Resettable for PauseSpec {} diff --git a/mcxa276-pac/src/adc0/resfifo0.rs b/mcxa276-pac/src/adc0/resfifo0.rs deleted file mode 100644 index f90df21ac..000000000 --- a/mcxa276-pac/src/adc0/resfifo0.rs +++ /dev/null @@ -1,338 +0,0 @@ -#[doc = "Register `RESFIFO0` reader"] -pub type R = crate::R; -#[doc = "Field `D` reader - Data Result"] -pub type DR = crate::FieldReader; -#[doc = "Trigger Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tsrc { - #[doc = "0: Trigger source 0 initiated this conversion."] - Trigger0 = 0, - #[doc = "1: Trigger source 1 initiated this conversion."] - Trigger1 = 1, - #[doc = "2: Trigger source 2 initiated this conversion."] - Trigger2 = 2, - #[doc = "3: Trigger source 3 initiated this conversion."] - Trigger3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tsrc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tsrc { - type Ux = u8; -} -impl crate::IsEnum for Tsrc {} -#[doc = "Field `TSRC` reader - Trigger Source"] -pub type TsrcR = crate::FieldReader; -impl TsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tsrc { - match self.bits { - 0 => Tsrc::Trigger0, - 1 => Tsrc::Trigger1, - 2 => Tsrc::Trigger2, - 3 => Tsrc::Trigger3, - _ => unreachable!(), - } - } - #[doc = "Trigger source 0 initiated this conversion."] - #[inline(always)] - pub fn is_trigger_0(&self) -> bool { - *self == Tsrc::Trigger0 - } - #[doc = "Trigger source 1 initiated this conversion."] - #[inline(always)] - pub fn is_trigger_1(&self) -> bool { - *self == Tsrc::Trigger1 - } - #[doc = "Trigger source 2 initiated this conversion."] - #[inline(always)] - pub fn is_trigger_2(&self) -> bool { - *self == Tsrc::Trigger2 - } - #[doc = "Trigger source 3 initiated this conversion."] - #[inline(always)] - pub fn is_trigger_3(&self) -> bool { - *self == Tsrc::Trigger3 - } -} -#[doc = "Loop Count Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Loopcnt { - #[doc = "0: Result is from initial conversion in command."] - Result1 = 0, - #[doc = "1: Result is from second conversion in command."] - Result2 = 1, - #[doc = "2: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult2 = 2, - #[doc = "3: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult3 = 3, - #[doc = "4: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult4 = 4, - #[doc = "5: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult5 = 5, - #[doc = "6: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult6 = 6, - #[doc = "7: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult7 = 7, - #[doc = "8: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult8 = 8, - #[doc = "9: Result is from LOOPCNT+1 conversion in command."] - CorrespondingResult9 = 9, - #[doc = "15: Result is from 16th conversion in command."] - Result16 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Loopcnt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Loopcnt { - type Ux = u8; -} -impl crate::IsEnum for Loopcnt {} -#[doc = "Field `LOOPCNT` reader - Loop Count Value"] -pub type LoopcntR = crate::FieldReader; -impl LoopcntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Loopcnt::Result1), - 1 => Some(Loopcnt::Result2), - 2 => Some(Loopcnt::CorrespondingResult2), - 3 => Some(Loopcnt::CorrespondingResult3), - 4 => Some(Loopcnt::CorrespondingResult4), - 5 => Some(Loopcnt::CorrespondingResult5), - 6 => Some(Loopcnt::CorrespondingResult6), - 7 => Some(Loopcnt::CorrespondingResult7), - 8 => Some(Loopcnt::CorrespondingResult8), - 9 => Some(Loopcnt::CorrespondingResult9), - 15 => Some(Loopcnt::Result16), - _ => None, - } - } - #[doc = "Result is from initial conversion in command."] - #[inline(always)] - pub fn is_result_1(&self) -> bool { - *self == Loopcnt::Result1 - } - #[doc = "Result is from second conversion in command."] - #[inline(always)] - pub fn is_result_2(&self) -> bool { - *self == Loopcnt::Result2 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_2(&self) -> bool { - *self == Loopcnt::CorrespondingResult2 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_3(&self) -> bool { - *self == Loopcnt::CorrespondingResult3 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_4(&self) -> bool { - *self == Loopcnt::CorrespondingResult4 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_5(&self) -> bool { - *self == Loopcnt::CorrespondingResult5 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_6(&self) -> bool { - *self == Loopcnt::CorrespondingResult6 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_7(&self) -> bool { - *self == Loopcnt::CorrespondingResult7 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_8(&self) -> bool { - *self == Loopcnt::CorrespondingResult8 - } - #[doc = "Result is from LOOPCNT+1 conversion in command."] - #[inline(always)] - pub fn is_corresponding_result_9(&self) -> bool { - *self == Loopcnt::CorrespondingResult9 - } - #[doc = "Result is from 16th conversion in command."] - #[inline(always)] - pub fn is_result_16(&self) -> bool { - *self == Loopcnt::Result16 - } -} -#[doc = "Command Buffer Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmdsrc { - #[doc = "0: Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer."] - NotValid = 0, - #[doc = "1: CMD1 buffer used as control settings for this conversion."] - Cmd1 = 1, - #[doc = "2: Corresponding command buffer used as control settings for this conversion."] - CorrespondingCmd2 = 2, - #[doc = "3: Corresponding command buffer used as control settings for this conversion."] - CorrespondingCmd3 = 3, - #[doc = "4: Corresponding command buffer used as control settings for this conversion."] - CorrespondingCmd4 = 4, - #[doc = "5: Corresponding command buffer used as control settings for this conversion."] - CorrespondingCmd5 = 5, - #[doc = "6: Corresponding command buffer used as control settings for this conversion."] - CorrespondingCmd6 = 6, - #[doc = "7: CMD7 buffer used as control settings for this conversion."] - Cmd7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmdsrc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmdsrc { - type Ux = u8; -} -impl crate::IsEnum for Cmdsrc {} -#[doc = "Field `CMDSRC` reader - Command Buffer Source"] -pub type CmdsrcR = crate::FieldReader; -impl CmdsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmdsrc { - match self.bits { - 0 => Cmdsrc::NotValid, - 1 => Cmdsrc::Cmd1, - 2 => Cmdsrc::CorrespondingCmd2, - 3 => Cmdsrc::CorrespondingCmd3, - 4 => Cmdsrc::CorrespondingCmd4, - 5 => Cmdsrc::CorrespondingCmd5, - 6 => Cmdsrc::CorrespondingCmd6, - 7 => Cmdsrc::Cmd7, - _ => unreachable!(), - } - } - #[doc = "Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer."] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Cmdsrc::NotValid - } - #[doc = "CMD1 buffer used as control settings for this conversion."] - #[inline(always)] - pub fn is_cmd1(&self) -> bool { - *self == Cmdsrc::Cmd1 - } - #[doc = "Corresponding command buffer used as control settings for this conversion."] - #[inline(always)] - pub fn is_corresponding_cmd_2(&self) -> bool { - *self == Cmdsrc::CorrespondingCmd2 - } - #[doc = "Corresponding command buffer used as control settings for this conversion."] - #[inline(always)] - pub fn is_corresponding_cmd_3(&self) -> bool { - *self == Cmdsrc::CorrespondingCmd3 - } - #[doc = "Corresponding command buffer used as control settings for this conversion."] - #[inline(always)] - pub fn is_corresponding_cmd_4(&self) -> bool { - *self == Cmdsrc::CorrespondingCmd4 - } - #[doc = "Corresponding command buffer used as control settings for this conversion."] - #[inline(always)] - pub fn is_corresponding_cmd_5(&self) -> bool { - *self == Cmdsrc::CorrespondingCmd5 - } - #[doc = "Corresponding command buffer used as control settings for this conversion."] - #[inline(always)] - pub fn is_corresponding_cmd_6(&self) -> bool { - *self == Cmdsrc::CorrespondingCmd6 - } - #[doc = "CMD7 buffer used as control settings for this conversion."] - #[inline(always)] - pub fn is_cmd7(&self) -> bool { - *self == Cmdsrc::Cmd7 - } -} -#[doc = "FIFO Entry is Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Valid { - #[doc = "0: FIFO is empty. Discard any read from RESFIFO."] - NotValid = 0, - #[doc = "1: FIFO record read from RESFIFO is valid."] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Valid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VALID` reader - FIFO Entry is Valid"] -pub type ValidR = crate::BitReader; -impl ValidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Valid { - match self.bits { - false => Valid::NotValid, - true => Valid::Valid, - } - } - #[doc = "FIFO is empty. Discard any read from RESFIFO."] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Valid::NotValid - } - #[doc = "FIFO record read from RESFIFO is valid."] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Valid::Valid - } -} -impl R { - #[doc = "Bits 0:15 - Data Result"] - #[inline(always)] - pub fn d(&self) -> DR { - DR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:17 - Trigger Source"] - #[inline(always)] - pub fn tsrc(&self) -> TsrcR { - TsrcR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 20:23 - Loop Count Value"] - #[inline(always)] - pub fn loopcnt(&self) -> LoopcntR { - LoopcntR::new(((self.bits >> 20) & 0x0f) as u8) - } - #[doc = "Bits 24:26 - Command Buffer Source"] - #[inline(always)] - pub fn cmdsrc(&self) -> CmdsrcR { - CmdsrcR::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 31 - FIFO Entry is Valid"] - #[inline(always)] - pub fn valid(&self) -> ValidR { - ValidR::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "Data Result FIFO Register\n\nYou can [`read`](crate::Reg::read) this register and get [`resfifo0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Resfifo0Spec; -impl crate::RegisterSpec for Resfifo0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`resfifo0::R`](R) reader structure"] -impl crate::Readable for Resfifo0Spec {} -#[doc = "`reset()` method sets RESFIFO0 to value 0"] -impl crate::Resettable for Resfifo0Spec {} diff --git a/mcxa276-pac/src/adc0/stat.rs b/mcxa276-pac/src/adc0/stat.rs deleted file mode 100644 index 785b363cf..000000000 --- a/mcxa276-pac/src/adc0/stat.rs +++ /dev/null @@ -1,492 +0,0 @@ -#[doc = "Register `STAT` reader"] -pub type R = crate::R; -#[doc = "Register `STAT` writer"] -pub type W = crate::W; -#[doc = "Result FIFO 0 Ready Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdy0 { - #[doc = "0: Result FIFO 0 data level not above watermark level."] - BelowThreshold = 0, - #[doc = "1: Result FIFO 0 holding data above watermark level."] - AboveThreshold = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdy0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDY0` reader - Result FIFO 0 Ready Flag"] -pub type Rdy0R = crate::BitReader; -impl Rdy0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdy0 { - match self.bits { - false => Rdy0::BelowThreshold, - true => Rdy0::AboveThreshold, - } - } - #[doc = "Result FIFO 0 data level not above watermark level."] - #[inline(always)] - pub fn is_below_threshold(&self) -> bool { - *self == Rdy0::BelowThreshold - } - #[doc = "Result FIFO 0 holding data above watermark level."] - #[inline(always)] - pub fn is_above_threshold(&self) -> bool { - *self == Rdy0::AboveThreshold - } -} -#[doc = "Result FIFO 0 Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fof0 { - #[doc = "0: No result FIFO 0 overflow has occurred since the last time the flag was cleared."] - NoOverflow = 0, - #[doc = "1: At least one result FIFO 0 overflow has occurred since the last time the flag was cleared."] - OverflowDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fof0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FOF0` reader - Result FIFO 0 Overflow Flag"] -pub type Fof0R = crate::BitReader; -impl Fof0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fof0 { - match self.bits { - false => Fof0::NoOverflow, - true => Fof0::OverflowDetected, - } - } - #[doc = "No result FIFO 0 overflow has occurred since the last time the flag was cleared."] - #[inline(always)] - pub fn is_no_overflow(&self) -> bool { - *self == Fof0::NoOverflow - } - #[doc = "At least one result FIFO 0 overflow has occurred since the last time the flag was cleared."] - #[inline(always)] - pub fn is_overflow_detected(&self) -> bool { - *self == Fof0::OverflowDetected - } -} -#[doc = "Field `FOF0` writer - Result FIFO 0 Overflow Flag"] -pub type Fof0W<'a, REG> = crate::BitWriter1C<'a, REG, Fof0>; -impl<'a, REG> Fof0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No result FIFO 0 overflow has occurred since the last time the flag was cleared."] - #[inline(always)] - pub fn no_overflow(self) -> &'a mut crate::W { - self.variant(Fof0::NoOverflow) - } - #[doc = "At least one result FIFO 0 overflow has occurred since the last time the flag was cleared."] - #[inline(always)] - pub fn overflow_detected(self) -> &'a mut crate::W { - self.variant(Fof0::OverflowDetected) - } -} -#[doc = "Interrupt Flag For High Priority Trigger Exception\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TexcInt { - #[doc = "0: No trigger exceptions have occurred."] - NoException = 0, - #[doc = "1: A trigger exception has occurred and is pending acknowledgement."] - ExceptionDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TexcInt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TEXC_INT` reader - Interrupt Flag For High Priority Trigger Exception"] -pub type TexcIntR = crate::BitReader; -impl TexcIntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TexcInt { - match self.bits { - false => TexcInt::NoException, - true => TexcInt::ExceptionDetected, - } - } - #[doc = "No trigger exceptions have occurred."] - #[inline(always)] - pub fn is_no_exception(&self) -> bool { - *self == TexcInt::NoException - } - #[doc = "A trigger exception has occurred and is pending acknowledgement."] - #[inline(always)] - pub fn is_exception_detected(&self) -> bool { - *self == TexcInt::ExceptionDetected - } -} -#[doc = "Field `TEXC_INT` writer - Interrupt Flag For High Priority Trigger Exception"] -pub type TexcIntW<'a, REG> = crate::BitWriter1C<'a, REG, TexcInt>; -impl<'a, REG> TexcIntW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No trigger exceptions have occurred."] - #[inline(always)] - pub fn no_exception(self) -> &'a mut crate::W { - self.variant(TexcInt::NoException) - } - #[doc = "A trigger exception has occurred and is pending acknowledgement."] - #[inline(always)] - pub fn exception_detected(self) -> &'a mut crate::W { - self.variant(TexcInt::ExceptionDetected) - } -} -#[doc = "Interrupt Flag For Trigger Completion\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TcompInt { - #[doc = "0: Either IE\\[TCOMP_IE\\] is set to 0, or no trigger sequences have run to completion."] - FlagClear = 0, - #[doc = "1: Trigger sequence has been completed and all data is stored in the associated FIFO."] - CompletionDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TcompInt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCOMP_INT` reader - Interrupt Flag For Trigger Completion"] -pub type TcompIntR = crate::BitReader; -impl TcompIntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TcompInt { - match self.bits { - false => TcompInt::FlagClear, - true => TcompInt::CompletionDetected, - } - } - #[doc = "Either IE\\[TCOMP_IE\\] is set to 0, or no trigger sequences have run to completion."] - #[inline(always)] - pub fn is_flag_clear(&self) -> bool { - *self == TcompInt::FlagClear - } - #[doc = "Trigger sequence has been completed and all data is stored in the associated FIFO."] - #[inline(always)] - pub fn is_completion_detected(&self) -> bool { - *self == TcompInt::CompletionDetected - } -} -#[doc = "Field `TCOMP_INT` writer - Interrupt Flag For Trigger Completion"] -pub type TcompIntW<'a, REG> = crate::BitWriter1C<'a, REG, TcompInt>; -impl<'a, REG> TcompIntW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Either IE\\[TCOMP_IE\\] is set to 0, or no trigger sequences have run to completion."] - #[inline(always)] - pub fn flag_clear(self) -> &'a mut crate::W { - self.variant(TcompInt::FlagClear) - } - #[doc = "Trigger sequence has been completed and all data is stored in the associated FIFO."] - #[inline(always)] - pub fn completion_detected(self) -> &'a mut crate::W { - self.variant(TcompInt::CompletionDetected) - } -} -#[doc = "Calibration Ready\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CalRdy { - #[doc = "0: Calibration is incomplete or hasn't been ran."] - NotSet = 0, - #[doc = "1: The ADC is calibrated."] - HardwareCalStepCompleted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CalRdy) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAL_RDY` reader - Calibration Ready"] -pub type CalRdyR = crate::BitReader; -impl CalRdyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CalRdy { - match self.bits { - false => CalRdy::NotSet, - true => CalRdy::HardwareCalStepCompleted, - } - } - #[doc = "Calibration is incomplete or hasn't been ran."] - #[inline(always)] - pub fn is_not_set(&self) -> bool { - *self == CalRdy::NotSet - } - #[doc = "The ADC is calibrated."] - #[inline(always)] - pub fn is_hardware_cal_step_completed(&self) -> bool { - *self == CalRdy::HardwareCalStepCompleted - } -} -#[doc = "ADC Active\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum AdcActive { - #[doc = "0: The ADC is IDLE. There are no pending triggers to service and no active commands are being processed."] - NotActive = 0, - #[doc = "1: The ADC is processing a conversion, running through the power up delay, or servicing a trigger."] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: AdcActive) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC_ACTIVE` reader - ADC Active"] -pub type AdcActiveR = crate::BitReader; -impl AdcActiveR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> AdcActive { - match self.bits { - false => AdcActive::NotActive, - true => AdcActive::Busy, - } - } - #[doc = "The ADC is IDLE. There are no pending triggers to service and no active commands are being processed."] - #[inline(always)] - pub fn is_not_active(&self) -> bool { - *self == AdcActive::NotActive - } - #[doc = "The ADC is processing a conversion, running through the power up delay, or servicing a trigger."] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == AdcActive::Busy - } -} -#[doc = "Trigger Active\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trgact { - #[doc = "0: Command (sequence) associated with Trigger 0 currently being executed."] - Trig0 = 0, - #[doc = "1: Command (sequence) associated with Trigger 1 currently being executed."] - Trig1 = 1, - #[doc = "2: Command (sequence) associated with Trigger 2 currently being executed."] - Trig2 = 2, - #[doc = "3: Command (sequence) associated with Trigger 3 currently being executed."] - Trig3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trgact) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trgact { - type Ux = u8; -} -impl crate::IsEnum for Trgact {} -#[doc = "Field `TRGACT` reader - Trigger Active"] -pub type TrgactR = crate::FieldReader; -impl TrgactR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgact { - match self.bits { - 0 => Trgact::Trig0, - 1 => Trgact::Trig1, - 2 => Trgact::Trig2, - 3 => Trgact::Trig3, - _ => unreachable!(), - } - } - #[doc = "Command (sequence) associated with Trigger 0 currently being executed."] - #[inline(always)] - pub fn is_trig_0(&self) -> bool { - *self == Trgact::Trig0 - } - #[doc = "Command (sequence) associated with Trigger 1 currently being executed."] - #[inline(always)] - pub fn is_trig_1(&self) -> bool { - *self == Trgact::Trig1 - } - #[doc = "Command (sequence) associated with Trigger 2 currently being executed."] - #[inline(always)] - pub fn is_trig_2(&self) -> bool { - *self == Trgact::Trig2 - } - #[doc = "Command (sequence) associated with Trigger 3 currently being executed."] - #[inline(always)] - pub fn is_trig_3(&self) -> bool { - *self == Trgact::Trig3 - } -} -#[doc = "Command Active\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmdact { - #[doc = "0: No command is currently in progress."] - NoCommandActive = 0, - #[doc = "1: Command 1 currently being executed."] - Command1 = 1, - #[doc = "2: Command 2 currently being executed."] - Command2 = 2, - #[doc = "3: Associated command number is currently being executed."] - CommandX3 = 3, - #[doc = "4: Associated command number is currently being executed."] - CommandX4 = 4, - #[doc = "5: Associated command number is currently being executed."] - CommandX5 = 5, - #[doc = "6: Associated command number is currently being executed."] - CommandX6 = 6, - #[doc = "7: Associated command number is currently being executed."] - CommandX7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmdact) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmdact { - type Ux = u8; -} -impl crate::IsEnum for Cmdact {} -#[doc = "Field `CMDACT` reader - Command Active"] -pub type CmdactR = crate::FieldReader; -impl CmdactR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmdact { - match self.bits { - 0 => Cmdact::NoCommandActive, - 1 => Cmdact::Command1, - 2 => Cmdact::Command2, - 3 => Cmdact::CommandX3, - 4 => Cmdact::CommandX4, - 5 => Cmdact::CommandX5, - 6 => Cmdact::CommandX6, - 7 => Cmdact::CommandX7, - _ => unreachable!(), - } - } - #[doc = "No command is currently in progress."] - #[inline(always)] - pub fn is_no_command_active(&self) -> bool { - *self == Cmdact::NoCommandActive - } - #[doc = "Command 1 currently being executed."] - #[inline(always)] - pub fn is_command_1(&self) -> bool { - *self == Cmdact::Command1 - } - #[doc = "Command 2 currently being executed."] - #[inline(always)] - pub fn is_command_2(&self) -> bool { - *self == Cmdact::Command2 - } - #[doc = "Associated command number is currently being executed."] - #[inline(always)] - pub fn is_command_x_3(&self) -> bool { - *self == Cmdact::CommandX3 - } - #[doc = "Associated command number is currently being executed."] - #[inline(always)] - pub fn is_command_x_4(&self) -> bool { - *self == Cmdact::CommandX4 - } - #[doc = "Associated command number is currently being executed."] - #[inline(always)] - pub fn is_command_x_5(&self) -> bool { - *self == Cmdact::CommandX5 - } - #[doc = "Associated command number is currently being executed."] - #[inline(always)] - pub fn is_command_x_6(&self) -> bool { - *self == Cmdact::CommandX6 - } - #[doc = "Associated command number is currently being executed."] - #[inline(always)] - pub fn is_command_x_7(&self) -> bool { - *self == Cmdact::CommandX7 - } -} -impl R { - #[doc = "Bit 0 - Result FIFO 0 Ready Flag"] - #[inline(always)] - pub fn rdy0(&self) -> Rdy0R { - Rdy0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Result FIFO 0 Overflow Flag"] - #[inline(always)] - pub fn fof0(&self) -> Fof0R { - Fof0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - Interrupt Flag For High Priority Trigger Exception"] - #[inline(always)] - pub fn texc_int(&self) -> TexcIntR { - TexcIntR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Interrupt Flag For Trigger Completion"] - #[inline(always)] - pub fn tcomp_int(&self) -> TcompIntR { - TcompIntR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Calibration Ready"] - #[inline(always)] - pub fn cal_rdy(&self) -> CalRdyR { - CalRdyR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - ADC Active"] - #[inline(always)] - pub fn adc_active(&self) -> AdcActiveR { - AdcActiveR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 16:17 - Trigger Active"] - #[inline(always)] - pub fn trgact(&self) -> TrgactR { - TrgactR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 24:26 - Command Active"] - #[inline(always)] - pub fn cmdact(&self) -> CmdactR { - CmdactR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bit 1 - Result FIFO 0 Overflow Flag"] - #[inline(always)] - pub fn fof0(&mut self) -> Fof0W { - Fof0W::new(self, 1) - } - #[doc = "Bit 8 - Interrupt Flag For High Priority Trigger Exception"] - #[inline(always)] - pub fn texc_int(&mut self) -> TexcIntW { - TexcIntW::new(self, 8) - } - #[doc = "Bit 9 - Interrupt Flag For Trigger Completion"] - #[inline(always)] - pub fn tcomp_int(&mut self) -> TcompIntW { - TcompIntW::new(self, 9) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StatSpec; -impl crate::RegisterSpec for StatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`stat::R`](R) reader structure"] -impl crate::Readable for StatSpec {} -#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] -impl crate::Writable for StatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0302; -} -#[doc = "`reset()` method sets STAT to value 0"] -impl crate::Resettable for StatSpec {} diff --git a/mcxa276-pac/src/adc0/swtrig.rs b/mcxa276-pac/src/adc0/swtrig.rs deleted file mode 100644 index 9b9a45a94..000000000 --- a/mcxa276-pac/src/adc0/swtrig.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `SWTRIG` reader"] -pub type R = crate::R; -#[doc = "Register `SWTRIG` writer"] -pub type W = crate::W; -#[doc = "Software Trigger 0 Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swt0 { - #[doc = "0: No trigger 0 event generated."] - NoTrigger = 0, - #[doc = "1: Trigger 0 event generated."] - InitiateTrigger0 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swt0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWT0` reader - Software Trigger 0 Event"] -pub type Swt0R = crate::BitReader; -impl Swt0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swt0 { - match self.bits { - false => Swt0::NoTrigger, - true => Swt0::InitiateTrigger0, - } - } - #[doc = "No trigger 0 event generated."] - #[inline(always)] - pub fn is_no_trigger(&self) -> bool { - *self == Swt0::NoTrigger - } - #[doc = "Trigger 0 event generated."] - #[inline(always)] - pub fn is_initiate_trigger_0(&self) -> bool { - *self == Swt0::InitiateTrigger0 - } -} -#[doc = "Field `SWT0` writer - Software Trigger 0 Event"] -pub type Swt0W<'a, REG> = crate::BitWriter<'a, REG, Swt0>; -impl<'a, REG> Swt0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No trigger 0 event generated."] - #[inline(always)] - pub fn no_trigger(self) -> &'a mut crate::W { - self.variant(Swt0::NoTrigger) - } - #[doc = "Trigger 0 event generated."] - #[inline(always)] - pub fn initiate_trigger_0(self) -> &'a mut crate::W { - self.variant(Swt0::InitiateTrigger0) - } -} -#[doc = "Software Trigger 1 Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swt1 { - #[doc = "0: No trigger 1 event generated."] - NoTrigger = 0, - #[doc = "1: Trigger 1 event generated."] - InitiateTrigger1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swt1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWT1` reader - Software Trigger 1 Event"] -pub type Swt1R = crate::BitReader; -impl Swt1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swt1 { - match self.bits { - false => Swt1::NoTrigger, - true => Swt1::InitiateTrigger1, - } - } - #[doc = "No trigger 1 event generated."] - #[inline(always)] - pub fn is_no_trigger(&self) -> bool { - *self == Swt1::NoTrigger - } - #[doc = "Trigger 1 event generated."] - #[inline(always)] - pub fn is_initiate_trigger_1(&self) -> bool { - *self == Swt1::InitiateTrigger1 - } -} -#[doc = "Field `SWT1` writer - Software Trigger 1 Event"] -pub type Swt1W<'a, REG> = crate::BitWriter<'a, REG, Swt1>; -impl<'a, REG> Swt1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No trigger 1 event generated."] - #[inline(always)] - pub fn no_trigger(self) -> &'a mut crate::W { - self.variant(Swt1::NoTrigger) - } - #[doc = "Trigger 1 event generated."] - #[inline(always)] - pub fn initiate_trigger_1(self) -> &'a mut crate::W { - self.variant(Swt1::InitiateTrigger1) - } -} -#[doc = "Software Trigger 2 Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swt2 { - #[doc = "0: No trigger 2 event generated."] - NoTrigger = 0, - #[doc = "1: Trigger 2 event generated."] - InitiateTrigger2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swt2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWT2` reader - Software Trigger 2 Event"] -pub type Swt2R = crate::BitReader; -impl Swt2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swt2 { - match self.bits { - false => Swt2::NoTrigger, - true => Swt2::InitiateTrigger2, - } - } - #[doc = "No trigger 2 event generated."] - #[inline(always)] - pub fn is_no_trigger(&self) -> bool { - *self == Swt2::NoTrigger - } - #[doc = "Trigger 2 event generated."] - #[inline(always)] - pub fn is_initiate_trigger_2(&self) -> bool { - *self == Swt2::InitiateTrigger2 - } -} -#[doc = "Field `SWT2` writer - Software Trigger 2 Event"] -pub type Swt2W<'a, REG> = crate::BitWriter<'a, REG, Swt2>; -impl<'a, REG> Swt2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No trigger 2 event generated."] - #[inline(always)] - pub fn no_trigger(self) -> &'a mut crate::W { - self.variant(Swt2::NoTrigger) - } - #[doc = "Trigger 2 event generated."] - #[inline(always)] - pub fn initiate_trigger_2(self) -> &'a mut crate::W { - self.variant(Swt2::InitiateTrigger2) - } -} -#[doc = "Software Trigger 3 Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swt3 { - #[doc = "0: No trigger 3 event generated."] - NoTrigger = 0, - #[doc = "1: Trigger 3 event generated."] - InitiateTrigger3 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swt3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWT3` reader - Software Trigger 3 Event"] -pub type Swt3R = crate::BitReader; -impl Swt3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swt3 { - match self.bits { - false => Swt3::NoTrigger, - true => Swt3::InitiateTrigger3, - } - } - #[doc = "No trigger 3 event generated."] - #[inline(always)] - pub fn is_no_trigger(&self) -> bool { - *self == Swt3::NoTrigger - } - #[doc = "Trigger 3 event generated."] - #[inline(always)] - pub fn is_initiate_trigger_3(&self) -> bool { - *self == Swt3::InitiateTrigger3 - } -} -#[doc = "Field `SWT3` writer - Software Trigger 3 Event"] -pub type Swt3W<'a, REG> = crate::BitWriter<'a, REG, Swt3>; -impl<'a, REG> Swt3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No trigger 3 event generated."] - #[inline(always)] - pub fn no_trigger(self) -> &'a mut crate::W { - self.variant(Swt3::NoTrigger) - } - #[doc = "Trigger 3 event generated."] - #[inline(always)] - pub fn initiate_trigger_3(self) -> &'a mut crate::W { - self.variant(Swt3::InitiateTrigger3) - } -} -impl R { - #[doc = "Bit 0 - Software Trigger 0 Event"] - #[inline(always)] - pub fn swt0(&self) -> Swt0R { - Swt0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Software Trigger 1 Event"] - #[inline(always)] - pub fn swt1(&self) -> Swt1R { - Swt1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Software Trigger 2 Event"] - #[inline(always)] - pub fn swt2(&self) -> Swt2R { - Swt2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Software Trigger 3 Event"] - #[inline(always)] - pub fn swt3(&self) -> Swt3R { - Swt3R::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Software Trigger 0 Event"] - #[inline(always)] - pub fn swt0(&mut self) -> Swt0W { - Swt0W::new(self, 0) - } - #[doc = "Bit 1 - Software Trigger 1 Event"] - #[inline(always)] - pub fn swt1(&mut self) -> Swt1W { - Swt1W::new(self, 1) - } - #[doc = "Bit 2 - Software Trigger 2 Event"] - #[inline(always)] - pub fn swt2(&mut self) -> Swt2W { - Swt2W::new(self, 2) - } - #[doc = "Bit 3 - Software Trigger 3 Event"] - #[inline(always)] - pub fn swt3(&mut self) -> Swt3W { - Swt3W::new(self, 3) - } -} -#[doc = "Software Trigger Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swtrig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SwtrigSpec; -impl crate::RegisterSpec for SwtrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`swtrig::R`](R) reader structure"] -impl crate::Readable for SwtrigSpec {} -#[doc = "`write(|w| ..)` method takes [`swtrig::W`](W) writer structure"] -impl crate::Writable for SwtrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWTRIG to value 0"] -impl crate::Resettable for SwtrigSpec {} diff --git a/mcxa276-pac/src/adc0/tctrl.rs b/mcxa276-pac/src/adc0/tctrl.rs deleted file mode 100644 index 148e1ca68..000000000 --- a/mcxa276-pac/src/adc0/tctrl.rs +++ /dev/null @@ -1,370 +0,0 @@ -#[doc = "Register `TCTRL[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `TCTRL[%s]` writer"] -pub type W = crate::W; -#[doc = "Trigger Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hten { - #[doc = "0: Hardware trigger source disabled"] - Disabled = 0, - #[doc = "1: Hardware trigger source enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HTEN` reader - Trigger Enable"] -pub type HtenR = crate::BitReader; -impl HtenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hten { - match self.bits { - false => Hten::Disabled, - true => Hten::Enabled, - } - } - #[doc = "Hardware trigger source disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Hten::Disabled - } - #[doc = "Hardware trigger source enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Hten::Enabled - } -} -#[doc = "Field `HTEN` writer - Trigger Enable"] -pub type HtenW<'a, REG> = crate::BitWriter<'a, REG, Hten>; -impl<'a, REG> HtenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Hardware trigger source disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Hten::Disabled) - } - #[doc = "Hardware trigger source enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Hten::Enabled) - } -} -#[doc = "Trigger Priority Setting\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tpri { - #[doc = "0: Set to highest priority, Level 1"] - HighestPriority = 0, - #[doc = "1: Set to corresponding priority level"] - CorrespondingLowerPriority1 = 1, - #[doc = "2: Set to corresponding priority level"] - CorrespondingLowerPriority2 = 2, - #[doc = "3: Set to lowest priority, Level 4"] - LowestPriority = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tpri) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tpri { - type Ux = u8; -} -impl crate::IsEnum for Tpri {} -#[doc = "Field `TPRI` reader - Trigger Priority Setting"] -pub type TpriR = crate::FieldReader; -impl TpriR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpri { - match self.bits { - 0 => Tpri::HighestPriority, - 1 => Tpri::CorrespondingLowerPriority1, - 2 => Tpri::CorrespondingLowerPriority2, - 3 => Tpri::LowestPriority, - _ => unreachable!(), - } - } - #[doc = "Set to highest priority, Level 1"] - #[inline(always)] - pub fn is_highest_priority(&self) -> bool { - *self == Tpri::HighestPriority - } - #[doc = "Set to corresponding priority level"] - #[inline(always)] - pub fn is_corresponding_lower_priority_1(&self) -> bool { - *self == Tpri::CorrespondingLowerPriority1 - } - #[doc = "Set to corresponding priority level"] - #[inline(always)] - pub fn is_corresponding_lower_priority_2(&self) -> bool { - *self == Tpri::CorrespondingLowerPriority2 - } - #[doc = "Set to lowest priority, Level 4"] - #[inline(always)] - pub fn is_lowest_priority(&self) -> bool { - *self == Tpri::LowestPriority - } -} -#[doc = "Field `TPRI` writer - Trigger Priority Setting"] -pub type TpriW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tpri, crate::Safe>; -impl<'a, REG> TpriW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Set to highest priority, Level 1"] - #[inline(always)] - pub fn highest_priority(self) -> &'a mut crate::W { - self.variant(Tpri::HighestPriority) - } - #[doc = "Set to corresponding priority level"] - #[inline(always)] - pub fn corresponding_lower_priority_1(self) -> &'a mut crate::W { - self.variant(Tpri::CorrespondingLowerPriority1) - } - #[doc = "Set to corresponding priority level"] - #[inline(always)] - pub fn corresponding_lower_priority_2(self) -> &'a mut crate::W { - self.variant(Tpri::CorrespondingLowerPriority2) - } - #[doc = "Set to lowest priority, Level 4"] - #[inline(always)] - pub fn lowest_priority(self) -> &'a mut crate::W { - self.variant(Tpri::LowestPriority) - } -} -#[doc = "Field `RSYNC` reader - Trigger Resync"] -pub type RsyncR = crate::BitReader; -#[doc = "Field `RSYNC` writer - Trigger Resync"] -pub type RsyncW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TDLY` reader - Trigger Delay Select"] -pub type TdlyR = crate::FieldReader; -#[doc = "Field `TDLY` writer - Trigger Delay Select"] -pub type TdlyW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `TSYNC` reader - Trigger Synchronous Select"] -pub type TsyncR = crate::BitReader; -#[doc = "Field `TSYNC` writer - Trigger Synchronous Select"] -pub type TsyncW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Trigger Command Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tcmd { - #[doc = "0: Not a valid selection from the command buffer. Trigger event is ignored."] - NotValid = 0, - #[doc = "1: CMD1 is executed"] - ExecuteCmd1 = 1, - #[doc = "2: Corresponding CMD is executed"] - ExecuteCorrespondingCmd2 = 2, - #[doc = "3: Corresponding CMD is executed"] - ExecuteCorrespondingCmd3 = 3, - #[doc = "4: Corresponding CMD is executed"] - ExecuteCorrespondingCmd4 = 4, - #[doc = "5: Corresponding CMD is executed"] - ExecuteCorrespondingCmd5 = 5, - #[doc = "6: Corresponding CMD is executed"] - ExecuteCorrespondingCmd6 = 6, - #[doc = "7: CMD7 is executed"] - ExecuteCmd7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tcmd) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tcmd { - type Ux = u8; -} -impl crate::IsEnum for Tcmd {} -#[doc = "Field `TCMD` reader - Trigger Command Select"] -pub type TcmdR = crate::FieldReader; -impl TcmdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcmd { - match self.bits { - 0 => Tcmd::NotValid, - 1 => Tcmd::ExecuteCmd1, - 2 => Tcmd::ExecuteCorrespondingCmd2, - 3 => Tcmd::ExecuteCorrespondingCmd3, - 4 => Tcmd::ExecuteCorrespondingCmd4, - 5 => Tcmd::ExecuteCorrespondingCmd5, - 6 => Tcmd::ExecuteCorrespondingCmd6, - 7 => Tcmd::ExecuteCmd7, - _ => unreachable!(), - } - } - #[doc = "Not a valid selection from the command buffer. Trigger event is ignored."] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Tcmd::NotValid - } - #[doc = "CMD1 is executed"] - #[inline(always)] - pub fn is_execute_cmd1(&self) -> bool { - *self == Tcmd::ExecuteCmd1 - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn is_execute_corresponding_cmd_2(&self) -> bool { - *self == Tcmd::ExecuteCorrespondingCmd2 - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn is_execute_corresponding_cmd_3(&self) -> bool { - *self == Tcmd::ExecuteCorrespondingCmd3 - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn is_execute_corresponding_cmd_4(&self) -> bool { - *self == Tcmd::ExecuteCorrespondingCmd4 - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn is_execute_corresponding_cmd_5(&self) -> bool { - *self == Tcmd::ExecuteCorrespondingCmd5 - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn is_execute_corresponding_cmd_6(&self) -> bool { - *self == Tcmd::ExecuteCorrespondingCmd6 - } - #[doc = "CMD7 is executed"] - #[inline(always)] - pub fn is_execute_cmd7(&self) -> bool { - *self == Tcmd::ExecuteCmd7 - } -} -#[doc = "Field `TCMD` writer - Trigger Command Select"] -pub type TcmdW<'a, REG> = crate::FieldWriter<'a, REG, 3, Tcmd, crate::Safe>; -impl<'a, REG> TcmdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Not a valid selection from the command buffer. Trigger event is ignored."] - #[inline(always)] - pub fn not_valid(self) -> &'a mut crate::W { - self.variant(Tcmd::NotValid) - } - #[doc = "CMD1 is executed"] - #[inline(always)] - pub fn execute_cmd1(self) -> &'a mut crate::W { - self.variant(Tcmd::ExecuteCmd1) - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn execute_corresponding_cmd_2(self) -> &'a mut crate::W { - self.variant(Tcmd::ExecuteCorrespondingCmd2) - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn execute_corresponding_cmd_3(self) -> &'a mut crate::W { - self.variant(Tcmd::ExecuteCorrespondingCmd3) - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn execute_corresponding_cmd_4(self) -> &'a mut crate::W { - self.variant(Tcmd::ExecuteCorrespondingCmd4) - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn execute_corresponding_cmd_5(self) -> &'a mut crate::W { - self.variant(Tcmd::ExecuteCorrespondingCmd5) - } - #[doc = "Corresponding CMD is executed"] - #[inline(always)] - pub fn execute_corresponding_cmd_6(self) -> &'a mut crate::W { - self.variant(Tcmd::ExecuteCorrespondingCmd6) - } - #[doc = "CMD7 is executed"] - #[inline(always)] - pub fn execute_cmd7(self) -> &'a mut crate::W { - self.variant(Tcmd::ExecuteCmd7) - } -} -impl R { - #[doc = "Bit 0 - Trigger Enable"] - #[inline(always)] - pub fn hten(&self) -> HtenR { - HtenR::new((self.bits & 1) != 0) - } - #[doc = "Bits 8:9 - Trigger Priority Setting"] - #[inline(always)] - pub fn tpri(&self) -> TpriR { - TpriR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 15 - Trigger Resync"] - #[inline(always)] - pub fn rsync(&self) -> RsyncR { - RsyncR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:19 - Trigger Delay Select"] - #[inline(always)] - pub fn tdly(&self) -> TdlyR { - TdlyR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 23 - Trigger Synchronous Select"] - #[inline(always)] - pub fn tsync(&self) -> TsyncR { - TsyncR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Trigger Command Select"] - #[inline(always)] - pub fn tcmd(&self) -> TcmdR { - TcmdR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Trigger Enable"] - #[inline(always)] - pub fn hten(&mut self) -> HtenW { - HtenW::new(self, 0) - } - #[doc = "Bits 8:9 - Trigger Priority Setting"] - #[inline(always)] - pub fn tpri(&mut self) -> TpriW { - TpriW::new(self, 8) - } - #[doc = "Bit 15 - Trigger Resync"] - #[inline(always)] - pub fn rsync(&mut self) -> RsyncW { - RsyncW::new(self, 15) - } - #[doc = "Bits 16:19 - Trigger Delay Select"] - #[inline(always)] - pub fn tdly(&mut self) -> TdlyW { - TdlyW::new(self, 16) - } - #[doc = "Bit 23 - Trigger Synchronous Select"] - #[inline(always)] - pub fn tsync(&mut self) -> TsyncW { - TsyncW::new(self, 23) - } - #[doc = "Bits 24:26 - Trigger Command Select"] - #[inline(always)] - pub fn tcmd(&mut self) -> TcmdW { - TcmdW::new(self, 24) - } -} -#[doc = "Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TctrlSpec; -impl crate::RegisterSpec for TctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tctrl::R`](R) reader structure"] -impl crate::Readable for TctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`tctrl::W`](W) writer structure"] -impl crate::Writable for TctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCTRL[%s] to value 0"] -impl crate::Resettable for TctrlSpec {} diff --git a/mcxa276-pac/src/adc0/tstat.rs b/mcxa276-pac/src/adc0/tstat.rs deleted file mode 100644 index 0c729a97d..000000000 --- a/mcxa276-pac/src/adc0/tstat.rs +++ /dev/null @@ -1,396 +0,0 @@ -#[doc = "Register `TSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `TSTAT` writer"] -pub type W = crate::W; -#[doc = "Trigger Exception Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum TexcNum { - #[doc = "0: No triggers have been interrupted by a high priority exception. Or CFG\\[TRES\\] = 1."] - NoExceptions = 0, - #[doc = "1: Trigger 0 has been interrupted by a high priority exception."] - Bit0MeansTrigger0Interrupted = 1, - #[doc = "2: Trigger 1 has been interrupted by a high priority exception."] - Bit1MeansTrigger1Interrupted = 2, - #[doc = "3: Associated trigger sequence has interrupted by a high priority exception."] - SetBitsIndicateTriggerXInterrupted3 = 3, - #[doc = "4: Associated trigger sequence has interrupted by a high priority exception."] - SetBitsIndicateTriggerXInterrupted4 = 4, - #[doc = "5: Associated trigger sequence has interrupted by a high priority exception."] - SetBitsIndicateTriggerXInterrupted5 = 5, - #[doc = "6: Associated trigger sequence has interrupted by a high priority exception."] - SetBitsIndicateTriggerXInterrupted6 = 6, - #[doc = "7: Associated trigger sequence has interrupted by a high priority exception."] - SetBitsIndicateTriggerXInterrupted7 = 7, - #[doc = "8: Associated trigger sequence has interrupted by a high priority exception."] - SetBitsIndicateTriggerXInterrupted8 = 8, - #[doc = "9: Associated trigger sequence has interrupted by a high priority exception."] - SetBitsIndicateTriggerXInterrupted9 = 9, - #[doc = "15: Every trigger sequence has been interrupted by a high priority exception."] - AllBitsSetIndicateAllTriggersInterrupted = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: TexcNum) -> Self { - variant as _ - } -} -impl crate::FieldSpec for TexcNum { - type Ux = u8; -} -impl crate::IsEnum for TexcNum {} -#[doc = "Field `TEXC_NUM` reader - Trigger Exception Number"] -pub type TexcNumR = crate::FieldReader; -impl TexcNumR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(TexcNum::NoExceptions), - 1 => Some(TexcNum::Bit0MeansTrigger0Interrupted), - 2 => Some(TexcNum::Bit1MeansTrigger1Interrupted), - 3 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted3), - 4 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted4), - 5 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted5), - 6 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted6), - 7 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted7), - 8 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted8), - 9 => Some(TexcNum::SetBitsIndicateTriggerXInterrupted9), - 15 => Some(TexcNum::AllBitsSetIndicateAllTriggersInterrupted), - _ => None, - } - } - #[doc = "No triggers have been interrupted by a high priority exception. Or CFG\\[TRES\\] = 1."] - #[inline(always)] - pub fn is_no_exceptions(&self) -> bool { - *self == TexcNum::NoExceptions - } - #[doc = "Trigger 0 has been interrupted by a high priority exception."] - #[inline(always)] - pub fn is_bit0_means_trigger_0_interrupted(&self) -> bool { - *self == TexcNum::Bit0MeansTrigger0Interrupted - } - #[doc = "Trigger 1 has been interrupted by a high priority exception."] - #[inline(always)] - pub fn is_bit1_means_trigger_1_interrupted(&self) -> bool { - *self == TexcNum::Bit1MeansTrigger1Interrupted - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_interrupted_3(&self) -> bool { - *self == TexcNum::SetBitsIndicateTriggerXInterrupted3 - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_interrupted_4(&self) -> bool { - *self == TexcNum::SetBitsIndicateTriggerXInterrupted4 - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_interrupted_5(&self) -> bool { - *self == TexcNum::SetBitsIndicateTriggerXInterrupted5 - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_interrupted_6(&self) -> bool { - *self == TexcNum::SetBitsIndicateTriggerXInterrupted6 - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_interrupted_7(&self) -> bool { - *self == TexcNum::SetBitsIndicateTriggerXInterrupted7 - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_interrupted_8(&self) -> bool { - *self == TexcNum::SetBitsIndicateTriggerXInterrupted8 - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_interrupted_9(&self) -> bool { - *self == TexcNum::SetBitsIndicateTriggerXInterrupted9 - } - #[doc = "Every trigger sequence has been interrupted by a high priority exception."] - #[inline(always)] - pub fn is_all_bits_set_indicate_all_triggers_interrupted(&self) -> bool { - *self == TexcNum::AllBitsSetIndicateAllTriggersInterrupted - } -} -#[doc = "Field `TEXC_NUM` writer - Trigger Exception Number"] -pub type TexcNumW<'a, REG> = crate::FieldWriter<'a, REG, 4, TexcNum>; -impl<'a, REG> TexcNumW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No triggers have been interrupted by a high priority exception. Or CFG\\[TRES\\] = 1."] - #[inline(always)] - pub fn no_exceptions(self) -> &'a mut crate::W { - self.variant(TexcNum::NoExceptions) - } - #[doc = "Trigger 0 has been interrupted by a high priority exception."] - #[inline(always)] - pub fn bit0_means_trigger_0_interrupted(self) -> &'a mut crate::W { - self.variant(TexcNum::Bit0MeansTrigger0Interrupted) - } - #[doc = "Trigger 1 has been interrupted by a high priority exception."] - #[inline(always)] - pub fn bit1_means_trigger_1_interrupted(self) -> &'a mut crate::W { - self.variant(TexcNum::Bit1MeansTrigger1Interrupted) - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_interrupted_3(self) -> &'a mut crate::W { - self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted3) - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_interrupted_4(self) -> &'a mut crate::W { - self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted4) - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_interrupted_5(self) -> &'a mut crate::W { - self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted5) - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_interrupted_6(self) -> &'a mut crate::W { - self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted6) - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_interrupted_7(self) -> &'a mut crate::W { - self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted7) - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_interrupted_8(self) -> &'a mut crate::W { - self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted8) - } - #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_interrupted_9(self) -> &'a mut crate::W { - self.variant(TexcNum::SetBitsIndicateTriggerXInterrupted9) - } - #[doc = "Every trigger sequence has been interrupted by a high priority exception."] - #[inline(always)] - pub fn all_bits_set_indicate_all_triggers_interrupted(self) -> &'a mut crate::W { - self.variant(TexcNum::AllBitsSetIndicateAllTriggersInterrupted) - } -} -#[doc = "Trigger Completion Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum TcompFlag { - #[doc = "0: No triggers have been completed. Trigger completion interrupts are disabled."] - NoTrigger = 0, - #[doc = "1: Trigger 0 has been completed and trigger 0 has enabled completion interrupts."] - Bit0MeansTrigger0Completed = 1, - #[doc = "2: Trigger 1 has been completed and trigger 1 has enabled completion interrupts."] - Bit1MeansTrigger1Completed = 2, - #[doc = "3: Associated trigger sequence has completed and has enabled completion interrupts."] - SetBitsIndicateTriggerXCompleted3 = 3, - #[doc = "4: Associated trigger sequence has completed and has enabled completion interrupts."] - SetBitsIndicateTriggerXCompleted4 = 4, - #[doc = "5: Associated trigger sequence has completed and has enabled completion interrupts."] - SetBitsIndicateTriggerXCompleted5 = 5, - #[doc = "6: Associated trigger sequence has completed and has enabled completion interrupts."] - SetBitsIndicateTriggerXCompleted6 = 6, - #[doc = "7: Associated trigger sequence has completed and has enabled completion interrupts."] - SetBitsIndicateTriggerXCompleted7 = 7, - #[doc = "8: Associated trigger sequence has completed and has enabled completion interrupts."] - SetBitsIndicateTriggerXCompleted8 = 8, - #[doc = "9: Associated trigger sequence has completed and has enabled completion interrupts."] - SetBitsIndicateTriggerXCompleted9 = 9, - #[doc = "15: Every trigger sequence has been completed and every trigger has enabled completion interrupts."] - AllBitsSetIndicateAllTriggersCompleted = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: TcompFlag) -> Self { - variant as _ - } -} -impl crate::FieldSpec for TcompFlag { - type Ux = u8; -} -impl crate::IsEnum for TcompFlag {} -#[doc = "Field `TCOMP_FLAG` reader - Trigger Completion Flag"] -pub type TcompFlagR = crate::FieldReader; -impl TcompFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(TcompFlag::NoTrigger), - 1 => Some(TcompFlag::Bit0MeansTrigger0Completed), - 2 => Some(TcompFlag::Bit1MeansTrigger1Completed), - 3 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted3), - 4 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted4), - 5 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted5), - 6 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted6), - 7 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted7), - 8 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted8), - 9 => Some(TcompFlag::SetBitsIndicateTriggerXCompleted9), - 15 => Some(TcompFlag::AllBitsSetIndicateAllTriggersCompleted), - _ => None, - } - } - #[doc = "No triggers have been completed. Trigger completion interrupts are disabled."] - #[inline(always)] - pub fn is_no_trigger(&self) -> bool { - *self == TcompFlag::NoTrigger - } - #[doc = "Trigger 0 has been completed and trigger 0 has enabled completion interrupts."] - #[inline(always)] - pub fn is_bit0_means_trigger_0_completed(&self) -> bool { - *self == TcompFlag::Bit0MeansTrigger0Completed - } - #[doc = "Trigger 1 has been completed and trigger 1 has enabled completion interrupts."] - #[inline(always)] - pub fn is_bit1_means_trigger_1_completed(&self) -> bool { - *self == TcompFlag::Bit1MeansTrigger1Completed - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_completed_3(&self) -> bool { - *self == TcompFlag::SetBitsIndicateTriggerXCompleted3 - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_completed_4(&self) -> bool { - *self == TcompFlag::SetBitsIndicateTriggerXCompleted4 - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_completed_5(&self) -> bool { - *self == TcompFlag::SetBitsIndicateTriggerXCompleted5 - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_completed_6(&self) -> bool { - *self == TcompFlag::SetBitsIndicateTriggerXCompleted6 - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_completed_7(&self) -> bool { - *self == TcompFlag::SetBitsIndicateTriggerXCompleted7 - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_completed_8(&self) -> bool { - *self == TcompFlag::SetBitsIndicateTriggerXCompleted8 - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn is_set_bits_indicate_trigger_x_completed_9(&self) -> bool { - *self == TcompFlag::SetBitsIndicateTriggerXCompleted9 - } - #[doc = "Every trigger sequence has been completed and every trigger has enabled completion interrupts."] - #[inline(always)] - pub fn is_all_bits_set_indicate_all_triggers_completed(&self) -> bool { - *self == TcompFlag::AllBitsSetIndicateAllTriggersCompleted - } -} -#[doc = "Field `TCOMP_FLAG` writer - Trigger Completion Flag"] -pub type TcompFlagW<'a, REG> = crate::FieldWriter<'a, REG, 4, TcompFlag>; -impl<'a, REG> TcompFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No triggers have been completed. Trigger completion interrupts are disabled."] - #[inline(always)] - pub fn no_trigger(self) -> &'a mut crate::W { - self.variant(TcompFlag::NoTrigger) - } - #[doc = "Trigger 0 has been completed and trigger 0 has enabled completion interrupts."] - #[inline(always)] - pub fn bit0_means_trigger_0_completed(self) -> &'a mut crate::W { - self.variant(TcompFlag::Bit0MeansTrigger0Completed) - } - #[doc = "Trigger 1 has been completed and trigger 1 has enabled completion interrupts."] - #[inline(always)] - pub fn bit1_means_trigger_1_completed(self) -> &'a mut crate::W { - self.variant(TcompFlag::Bit1MeansTrigger1Completed) - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_completed_3(self) -> &'a mut crate::W { - self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted3) - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_completed_4(self) -> &'a mut crate::W { - self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted4) - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_completed_5(self) -> &'a mut crate::W { - self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted5) - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_completed_6(self) -> &'a mut crate::W { - self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted6) - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_completed_7(self) -> &'a mut crate::W { - self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted7) - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_completed_8(self) -> &'a mut crate::W { - self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted8) - } - #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - #[inline(always)] - pub fn set_bits_indicate_trigger_x_completed_9(self) -> &'a mut crate::W { - self.variant(TcompFlag::SetBitsIndicateTriggerXCompleted9) - } - #[doc = "Every trigger sequence has been completed and every trigger has enabled completion interrupts."] - #[inline(always)] - pub fn all_bits_set_indicate_all_triggers_completed(self) -> &'a mut crate::W { - self.variant(TcompFlag::AllBitsSetIndicateAllTriggersCompleted) - } -} -impl R { - #[doc = "Bits 0:3 - Trigger Exception Number"] - #[inline(always)] - pub fn texc_num(&self) -> TexcNumR { - TexcNumR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Trigger Completion Flag"] - #[inline(always)] - pub fn tcomp_flag(&self) -> TcompFlagR { - TcompFlagR::new(((self.bits >> 16) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Trigger Exception Number"] - #[inline(always)] - pub fn texc_num(&mut self) -> TexcNumW { - TexcNumW::new(self, 0) - } - #[doc = "Bits 16:19 - Trigger Completion Flag"] - #[inline(always)] - pub fn tcomp_flag(&mut self) -> TcompFlagW { - TcompFlagW::new(self, 16) - } -} -#[doc = "Trigger Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TstatSpec; -impl crate::RegisterSpec for TstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tstat::R`](R) reader structure"] -impl crate::Readable for TstatSpec {} -#[doc = "`write(|w| ..)` method takes [`tstat::W`](W) writer structure"] -impl crate::Writable for TstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_000f; -} -#[doc = "`reset()` method sets TSTAT to value 0"] -impl crate::Resettable for TstatSpec {} diff --git a/mcxa276-pac/src/adc0/verid.rs b/mcxa276-pac/src/adc0/verid.rs deleted file mode 100644 index 4621a8e42..000000000 --- a/mcxa276-pac/src/adc0/verid.rs +++ /dev/null @@ -1,442 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Resolution\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res { - #[doc = "0: Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] - Max13Bit = 0, - #[doc = "1: Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] - Max16Bit = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES` reader - Resolution"] -pub type ResR = crate::BitReader; -impl ResR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res { - match self.bits { - false => Res::Max13Bit, - true => Res::Max16Bit, - } - } - #[doc = "Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] - #[inline(always)] - pub fn is_max_13_bit(&self) -> bool { - *self == Res::Max13Bit - } - #[doc = "Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] - #[inline(always)] - pub fn is_max_16_bit(&self) -> bool { - *self == Res::Max16Bit - } -} -#[doc = "Differential Supported\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Diffen { - #[doc = "0: Differential operation not supported."] - DifferentialNotSupported = 0, - #[doc = "1: Differential operation supported."] - DifferentialSupported = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Diffen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIFFEN` reader - Differential Supported"] -pub type DiffenR = crate::BitReader; -impl DiffenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Diffen { - match self.bits { - false => Diffen::DifferentialNotSupported, - true => Diffen::DifferentialSupported, - } - } - #[doc = "Differential operation not supported."] - #[inline(always)] - pub fn is_differential_not_supported(&self) -> bool { - *self == Diffen::DifferentialNotSupported - } - #[doc = "Differential operation supported."] - #[inline(always)] - pub fn is_differential_supported(&self) -> bool { - *self == Diffen::DifferentialSupported - } -} -#[doc = "Multi Vref Implemented\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mvi { - #[doc = "0: Single voltage reference high (VREFH) input supported."] - MultipleRefNotSupported = 0, - #[doc = "1: Multiple voltage reference high (VREFH) inputs supported."] - MultipleRefSupported = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mvi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MVI` reader - Multi Vref Implemented"] -pub type MviR = crate::BitReader; -impl MviR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mvi { - match self.bits { - false => Mvi::MultipleRefNotSupported, - true => Mvi::MultipleRefSupported, - } - } - #[doc = "Single voltage reference high (VREFH) input supported."] - #[inline(always)] - pub fn is_multiple_ref_not_supported(&self) -> bool { - *self == Mvi::MultipleRefNotSupported - } - #[doc = "Multiple voltage reference high (VREFH) inputs supported."] - #[inline(always)] - pub fn is_multiple_ref_supported(&self) -> bool { - *self == Mvi::MultipleRefSupported - } -} -#[doc = "Channel Scale Width\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Csw { - #[doc = "0: Channel scaling not supported."] - CscaleNotSupported = 0, - #[doc = "1: Channel scaling supported. 1-bit CSCALE control field."] - BitWidth1 = 1, - #[doc = "6: Channel scaling supported. 6-bit CSCALE control field."] - BitWidth6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Csw) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Csw { - type Ux = u8; -} -impl crate::IsEnum for Csw {} -#[doc = "Field `CSW` reader - Channel Scale Width"] -pub type CswR = crate::FieldReader; -impl CswR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Csw::CscaleNotSupported), - 1 => Some(Csw::BitWidth1), - 6 => Some(Csw::BitWidth6), - _ => None, - } - } - #[doc = "Channel scaling not supported."] - #[inline(always)] - pub fn is_cscale_not_supported(&self) -> bool { - *self == Csw::CscaleNotSupported - } - #[doc = "Channel scaling supported. 1-bit CSCALE control field."] - #[inline(always)] - pub fn is_bit_width_1(&self) -> bool { - *self == Csw::BitWidth1 - } - #[doc = "Channel scaling supported. 6-bit CSCALE control field."] - #[inline(always)] - pub fn is_bit_width_6(&self) -> bool { - *self == Csw::BitWidth6 - } -} -#[doc = "Voltage Reference 1 Range Control Bit Implemented\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Vr1rngi { - #[doc = "0: Range control not required. CFG\\[VREF1RNG\\] is not implemented."] - Ref1FixedVoltageRange = 0, - #[doc = "1: Range control required. CFG\\[VREF1RNG\\] is implemented."] - Ref1SelectableVoltageRange = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Vr1rngi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VR1RNGI` reader - Voltage Reference 1 Range Control Bit Implemented"] -pub type Vr1rngiR = crate::BitReader; -impl Vr1rngiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Vr1rngi { - match self.bits { - false => Vr1rngi::Ref1FixedVoltageRange, - true => Vr1rngi::Ref1SelectableVoltageRange, - } - } - #[doc = "Range control not required. CFG\\[VREF1RNG\\] is not implemented."] - #[inline(always)] - pub fn is_ref1_fixed_voltage_range(&self) -> bool { - *self == Vr1rngi::Ref1FixedVoltageRange - } - #[doc = "Range control required. CFG\\[VREF1RNG\\] is implemented."] - #[inline(always)] - pub fn is_ref1_selectable_voltage_range(&self) -> bool { - *self == Vr1rngi::Ref1SelectableVoltageRange - } -} -#[doc = "Internal ADC Clock Implemented\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Iadcki { - #[doc = "0: Internal clock source not implemented."] - InternalClkNotAvailable = 0, - #[doc = "1: Internal clock source (and CFG\\[ADCKEN\\]) implemented."] - InternalClkAvailable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Iadcki) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IADCKI` reader - Internal ADC Clock Implemented"] -pub type IadckiR = crate::BitReader; -impl IadckiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Iadcki { - match self.bits { - false => Iadcki::InternalClkNotAvailable, - true => Iadcki::InternalClkAvailable, - } - } - #[doc = "Internal clock source not implemented."] - #[inline(always)] - pub fn is_internal_clk_not_available(&self) -> bool { - *self == Iadcki::InternalClkNotAvailable - } - #[doc = "Internal clock source (and CFG\\[ADCKEN\\]) implemented."] - #[inline(always)] - pub fn is_internal_clk_available(&self) -> bool { - *self == Iadcki::InternalClkAvailable - } -} -#[doc = "Calibration Function Implemented\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Calofsi { - #[doc = "0: Calibration Not Implemented."] - CalFunctionNotAvailable = 0, - #[doc = "1: Calibration Implemented."] - CalFunctionAvailable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Calofsi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CALOFSI` reader - Calibration Function Implemented"] -pub type CalofsiR = crate::BitReader; -impl CalofsiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Calofsi { - match self.bits { - false => Calofsi::CalFunctionNotAvailable, - true => Calofsi::CalFunctionAvailable, - } - } - #[doc = "Calibration Not Implemented."] - #[inline(always)] - pub fn is_cal_function_not_available(&self) -> bool { - *self == Calofsi::CalFunctionNotAvailable - } - #[doc = "Calibration Implemented."] - #[inline(always)] - pub fn is_cal_function_available(&self) -> bool { - *self == Calofsi::CalFunctionAvailable - } -} -#[doc = "Number of Single Ended Outputs Supported\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum NumSec { - #[doc = "0: This design supports one single ended conversion at a time."] - SingleConvertor = 0, - #[doc = "1: This design supports two simultaneous single ended conversions."] - DualConvertor = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: NumSec) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUM_SEC` reader - Number of Single Ended Outputs Supported"] -pub type NumSecR = crate::BitReader; -impl NumSecR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> NumSec { - match self.bits { - false => NumSec::SingleConvertor, - true => NumSec::DualConvertor, - } - } - #[doc = "This design supports one single ended conversion at a time."] - #[inline(always)] - pub fn is_single_convertor(&self) -> bool { - *self == NumSec::SingleConvertor - } - #[doc = "This design supports two simultaneous single ended conversions."] - #[inline(always)] - pub fn is_dual_convertor(&self) -> bool { - *self == NumSec::DualConvertor - } -} -#[doc = "Number of FIFOs\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum NumFifo { - #[doc = "0: N/A"] - NoFifoImplemented = 0, - #[doc = "1: This design supports one result FIFO."] - Cnt1 = 1, - #[doc = "2: This design supports two result FIFOs."] - Cnt2 = 2, - #[doc = "3: This design supports three result FIFOs."] - Cnt3 = 3, - #[doc = "4: This design supports four result FIFOs."] - Cnt4 = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: NumFifo) -> Self { - variant as _ - } -} -impl crate::FieldSpec for NumFifo { - type Ux = u8; -} -impl crate::IsEnum for NumFifo {} -#[doc = "Field `NUM_FIFO` reader - Number of FIFOs"] -pub type NumFifoR = crate::FieldReader; -impl NumFifoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(NumFifo::NoFifoImplemented), - 1 => Some(NumFifo::Cnt1), - 2 => Some(NumFifo::Cnt2), - 3 => Some(NumFifo::Cnt3), - 4 => Some(NumFifo::Cnt4), - _ => None, - } - } - #[doc = "N/A"] - #[inline(always)] - pub fn is_no_fifo_implemented(&self) -> bool { - *self == NumFifo::NoFifoImplemented - } - #[doc = "This design supports one result FIFO."] - #[inline(always)] - pub fn is_cnt_1(&self) -> bool { - *self == NumFifo::Cnt1 - } - #[doc = "This design supports two result FIFOs."] - #[inline(always)] - pub fn is_cnt_2(&self) -> bool { - *self == NumFifo::Cnt2 - } - #[doc = "This design supports three result FIFOs."] - #[inline(always)] - pub fn is_cnt_3(&self) -> bool { - *self == NumFifo::Cnt3 - } - #[doc = "This design supports four result FIFOs."] - #[inline(always)] - pub fn is_cnt_4(&self) -> bool { - *self == NumFifo::Cnt4 - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Resolution"] - #[inline(always)] - pub fn res(&self) -> ResR { - ResR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Differential Supported"] - #[inline(always)] - pub fn diffen(&self) -> DiffenR { - DiffenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Multi Vref Implemented"] - #[inline(always)] - pub fn mvi(&self) -> MviR { - MviR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Channel Scale Width"] - #[inline(always)] - pub fn csw(&self) -> CswR { - CswR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 8 - Voltage Reference 1 Range Control Bit Implemented"] - #[inline(always)] - pub fn vr1rngi(&self) -> Vr1rngiR { - Vr1rngiR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Internal ADC Clock Implemented"] - #[inline(always)] - pub fn iadcki(&self) -> IadckiR { - IadckiR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Calibration Function Implemented"] - #[inline(always)] - pub fn calofsi(&self) -> CalofsiR { - CalofsiR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Number of Single Ended Outputs Supported"] - #[inline(always)] - pub fn num_sec(&self) -> NumSecR { - NumSecR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Number of FIFOs"] - #[inline(always)] - pub fn num_fifo(&self) -> NumFifoR { - NumFifoR::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0200_1409"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0200_1409; -} diff --git a/mcxa276-pac/src/aoi0.rs b/mcxa276-pac/src/aoi0.rs deleted file mode 100644 index dabdec3c2..000000000 --- a/mcxa276-pac/src/aoi0.rs +++ /dev/null @@ -1,94 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - bfcrt010: Bfcrt010, - bfcrt230: Bfcrt230, - bfcrt011: Bfcrt011, - bfcrt231: Bfcrt231, - bfcrt012: Bfcrt012, - bfcrt232: Bfcrt232, - bfcrt013: Bfcrt013, - bfcrt233: Bfcrt233, -} -impl RegisterBlock { - #[doc = "0x00 - Boolean Function Term 0 and 1 Configuration for EVENT0"] - #[inline(always)] - pub const fn bfcrt010(&self) -> &Bfcrt010 { - &self.bfcrt010 - } - #[doc = "0x02 - Boolean Function Term 2 and 3 Configuration for EVENT0"] - #[inline(always)] - pub const fn bfcrt230(&self) -> &Bfcrt230 { - &self.bfcrt230 - } - #[doc = "0x04 - Boolean Function Term 0 and 1 Configuration for EVENT1"] - #[inline(always)] - pub const fn bfcrt011(&self) -> &Bfcrt011 { - &self.bfcrt011 - } - #[doc = "0x06 - Boolean Function Term 2 and 3 Configuration for EVENT1"] - #[inline(always)] - pub const fn bfcrt231(&self) -> &Bfcrt231 { - &self.bfcrt231 - } - #[doc = "0x08 - Boolean Function Term 0 and 1 Configuration for EVENT2"] - #[inline(always)] - pub const fn bfcrt012(&self) -> &Bfcrt012 { - &self.bfcrt012 - } - #[doc = "0x0a - Boolean Function Term 2 and 3 Configuration for EVENT2"] - #[inline(always)] - pub const fn bfcrt232(&self) -> &Bfcrt232 { - &self.bfcrt232 - } - #[doc = "0x0c - Boolean Function Term 0 and 1 Configuration for EVENT3"] - #[inline(always)] - pub const fn bfcrt013(&self) -> &Bfcrt013 { - &self.bfcrt013 - } - #[doc = "0x0e - Boolean Function Term 2 and 3 Configuration for EVENT3"] - #[inline(always)] - pub const fn bfcrt233(&self) -> &Bfcrt233 { - &self.bfcrt233 - } -} -#[doc = "BFCRT010 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt010::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt010::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt010`] module"] -#[doc(alias = "BFCRT010")] -pub type Bfcrt010 = crate::Reg; -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT0"] -pub mod bfcrt010; -#[doc = "BFCRT230 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt230::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt230::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt230`] module"] -#[doc(alias = "BFCRT230")] -pub type Bfcrt230 = crate::Reg; -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT0"] -pub mod bfcrt230; -#[doc = "BFCRT011 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt011::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt011::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt011`] module"] -#[doc(alias = "BFCRT011")] -pub type Bfcrt011 = crate::Reg; -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT1"] -pub mod bfcrt011; -#[doc = "BFCRT231 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt231::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt231::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt231`] module"] -#[doc(alias = "BFCRT231")] -pub type Bfcrt231 = crate::Reg; -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT1"] -pub mod bfcrt231; -#[doc = "BFCRT012 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt012::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt012::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt012`] module"] -#[doc(alias = "BFCRT012")] -pub type Bfcrt012 = crate::Reg; -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT2"] -pub mod bfcrt012; -#[doc = "BFCRT232 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt232::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt232::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt232`] module"] -#[doc(alias = "BFCRT232")] -pub type Bfcrt232 = crate::Reg; -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT2"] -pub mod bfcrt232; -#[doc = "BFCRT013 (rw) register accessor: Boolean Function Term 0 and 1 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt013::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt013::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt013`] module"] -#[doc(alias = "BFCRT013")] -pub type Bfcrt013 = crate::Reg; -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT3"] -pub mod bfcrt013; -#[doc = "BFCRT233 (rw) register accessor: Boolean Function Term 2 and 3 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt233::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt233::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bfcrt233`] module"] -#[doc(alias = "BFCRT233")] -pub type Bfcrt233 = crate::Reg; -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT3"] -pub mod bfcrt233; diff --git a/mcxa276-pac/src/aoi0/bfcrt010.rs b/mcxa276-pac/src/aoi0/bfcrt010.rs deleted file mode 100644 index d26fb9721..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt010.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT010` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT010` writer"] -pub type W = crate::W; -#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Dc {} -#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] -pub type Pt1DcR = crate::FieldReader; -impl Pt1DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Dc { - match self.bits { - 0 => Pt1Dc::Force0, - 1 => Pt1Dc::Pass, - 2 => Pt1Dc::Complement, - 3 => Pt1Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Dc::Force1 - } -} -#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] -pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; -impl<'a, REG> Pt1DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force1) - } -} -#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Cc {} -#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] -pub type Pt1CcR = crate::FieldReader; -impl Pt1CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Cc { - match self.bits { - 0 => Pt1Cc::Force0, - 1 => Pt1Cc::Pass, - 2 => Pt1Cc::Complement, - 3 => Pt1Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Cc::Force1 - } -} -#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] -pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; -impl<'a, REG> Pt1CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force1) - } -} -#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Bc {} -#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] -pub type Pt1BcR = crate::FieldReader; -impl Pt1BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Bc { - match self.bits { - 0 => Pt1Bc::Force0, - 1 => Pt1Bc::Pass, - 2 => Pt1Bc::Complement, - 3 => Pt1Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Bc::Force1 - } -} -#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] -pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; -impl<'a, REG> Pt1BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force1) - } -} -#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt1Ac {} -#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] -pub type Pt1AcR = crate::FieldReader; -impl Pt1AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Ac { - match self.bits { - 0 => Pt1Ac::Force0, - 1 => Pt1Ac::Pass, - 2 => Pt1Ac::Complement, - 3 => Pt1Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Ac::Force1 - } -} -#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] -pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; -impl<'a, REG> Pt1AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force1) - } -} -#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Dc {} -#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] -pub type Pt0DcR = crate::FieldReader; -impl Pt0DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Dc { - match self.bits { - 0 => Pt0Dc::Force0, - 1 => Pt0Dc::Pass, - 2 => Pt0Dc::Complement, - 3 => Pt0Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Dc::Force1 - } -} -#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] -pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; -impl<'a, REG> Pt0DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force1) - } -} -#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Cc {} -#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] -pub type Pt0CcR = crate::FieldReader; -impl Pt0CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Cc { - match self.bits { - 0 => Pt0Cc::Force0, - 1 => Pt0Cc::Pass, - 2 => Pt0Cc::Complement, - 3 => Pt0Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Cc::Force1 - } -} -#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] -pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; -impl<'a, REG> Pt0CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force1) - } -} -#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Bc {} -#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] -pub type Pt0BcR = crate::FieldReader; -impl Pt0BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Bc { - match self.bits { - 0 => Pt0Bc::Force0, - 1 => Pt0Bc::Pass, - 2 => Pt0Bc::Complement, - 3 => Pt0Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Bc::Force1 - } -} -#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] -pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; -impl<'a, REG> Pt0BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force1) - } -} -#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt0Ac {} -#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] -pub type Pt0AcR = crate::FieldReader; -impl Pt0AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Ac { - match self.bits { - 0 => Pt0Ac::Force0, - 1 => Pt0Ac::Pass, - 2 => Pt0Ac::Complement, - 3 => Pt0Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Ac::Force1 - } -} -#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] -pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; -impl<'a, REG> Pt0AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&self) -> Pt1DcR { - Pt1DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&self) -> Pt1CcR { - Pt1CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&self) -> Pt1BcR { - Pt1BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&self) -> Pt1AcR { - Pt1AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&self) -> Pt0DcR { - Pt0DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&self) -> Pt0CcR { - Pt0CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&self) -> Pt0BcR { - Pt0BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&self) -> Pt0AcR { - Pt0AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&mut self) -> Pt1DcW { - Pt1DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&mut self) -> Pt1CcW { - Pt1CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&mut self) -> Pt1BcW { - Pt1BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&mut self) -> Pt1AcW { - Pt1AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&mut self) -> Pt0DcW { - Pt0DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&mut self) -> Pt0CcW { - Pt0CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&mut self) -> Pt0BcW { - Pt0BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&mut self) -> Pt0AcW { - Pt0AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt010::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt010::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt010Spec; -impl crate::RegisterSpec for Bfcrt010Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt010::R`](R) reader structure"] -impl crate::Readable for Bfcrt010Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt010::W`](W) writer structure"] -impl crate::Writable for Bfcrt010Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT010 to value 0"] -impl crate::Resettable for Bfcrt010Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt011.rs b/mcxa276-pac/src/aoi0/bfcrt011.rs deleted file mode 100644 index ae3cdeca1..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt011.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT011` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT011` writer"] -pub type W = crate::W; -#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Dc {} -#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] -pub type Pt1DcR = crate::FieldReader; -impl Pt1DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Dc { - match self.bits { - 0 => Pt1Dc::Force0, - 1 => Pt1Dc::Pass, - 2 => Pt1Dc::Complement, - 3 => Pt1Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Dc::Force1 - } -} -#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] -pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; -impl<'a, REG> Pt1DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force1) - } -} -#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Cc {} -#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] -pub type Pt1CcR = crate::FieldReader; -impl Pt1CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Cc { - match self.bits { - 0 => Pt1Cc::Force0, - 1 => Pt1Cc::Pass, - 2 => Pt1Cc::Complement, - 3 => Pt1Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Cc::Force1 - } -} -#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] -pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; -impl<'a, REG> Pt1CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force1) - } -} -#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Bc {} -#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] -pub type Pt1BcR = crate::FieldReader; -impl Pt1BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Bc { - match self.bits { - 0 => Pt1Bc::Force0, - 1 => Pt1Bc::Pass, - 2 => Pt1Bc::Complement, - 3 => Pt1Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Bc::Force1 - } -} -#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] -pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; -impl<'a, REG> Pt1BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force1) - } -} -#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt1Ac {} -#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] -pub type Pt1AcR = crate::FieldReader; -impl Pt1AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Ac { - match self.bits { - 0 => Pt1Ac::Force0, - 1 => Pt1Ac::Pass, - 2 => Pt1Ac::Complement, - 3 => Pt1Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Ac::Force1 - } -} -#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] -pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; -impl<'a, REG> Pt1AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force1) - } -} -#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Dc {} -#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] -pub type Pt0DcR = crate::FieldReader; -impl Pt0DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Dc { - match self.bits { - 0 => Pt0Dc::Force0, - 1 => Pt0Dc::Pass, - 2 => Pt0Dc::Complement, - 3 => Pt0Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Dc::Force1 - } -} -#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] -pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; -impl<'a, REG> Pt0DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force1) - } -} -#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Cc {} -#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] -pub type Pt0CcR = crate::FieldReader; -impl Pt0CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Cc { - match self.bits { - 0 => Pt0Cc::Force0, - 1 => Pt0Cc::Pass, - 2 => Pt0Cc::Complement, - 3 => Pt0Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Cc::Force1 - } -} -#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] -pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; -impl<'a, REG> Pt0CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force1) - } -} -#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Bc {} -#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] -pub type Pt0BcR = crate::FieldReader; -impl Pt0BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Bc { - match self.bits { - 0 => Pt0Bc::Force0, - 1 => Pt0Bc::Pass, - 2 => Pt0Bc::Complement, - 3 => Pt0Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Bc::Force1 - } -} -#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] -pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; -impl<'a, REG> Pt0BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force1) - } -} -#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt0Ac {} -#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] -pub type Pt0AcR = crate::FieldReader; -impl Pt0AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Ac { - match self.bits { - 0 => Pt0Ac::Force0, - 1 => Pt0Ac::Pass, - 2 => Pt0Ac::Complement, - 3 => Pt0Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Ac::Force1 - } -} -#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] -pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; -impl<'a, REG> Pt0AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&self) -> Pt1DcR { - Pt1DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&self) -> Pt1CcR { - Pt1CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&self) -> Pt1BcR { - Pt1BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&self) -> Pt1AcR { - Pt1AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&self) -> Pt0DcR { - Pt0DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&self) -> Pt0CcR { - Pt0CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&self) -> Pt0BcR { - Pt0BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&self) -> Pt0AcR { - Pt0AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&mut self) -> Pt1DcW { - Pt1DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&mut self) -> Pt1CcW { - Pt1CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&mut self) -> Pt1BcW { - Pt1BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&mut self) -> Pt1AcW { - Pt1AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&mut self) -> Pt0DcW { - Pt0DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&mut self) -> Pt0CcW { - Pt0CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&mut self) -> Pt0BcW { - Pt0BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&mut self) -> Pt0AcW { - Pt0AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt011::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt011::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt011Spec; -impl crate::RegisterSpec for Bfcrt011Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt011::R`](R) reader structure"] -impl crate::Readable for Bfcrt011Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt011::W`](W) writer structure"] -impl crate::Writable for Bfcrt011Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT011 to value 0"] -impl crate::Resettable for Bfcrt011Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt012.rs b/mcxa276-pac/src/aoi0/bfcrt012.rs deleted file mode 100644 index 50c1efd38..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt012.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT012` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT012` writer"] -pub type W = crate::W; -#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Dc {} -#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] -pub type Pt1DcR = crate::FieldReader; -impl Pt1DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Dc { - match self.bits { - 0 => Pt1Dc::Force0, - 1 => Pt1Dc::Pass, - 2 => Pt1Dc::Complement, - 3 => Pt1Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Dc::Force1 - } -} -#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] -pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; -impl<'a, REG> Pt1DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force1) - } -} -#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Cc {} -#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] -pub type Pt1CcR = crate::FieldReader; -impl Pt1CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Cc { - match self.bits { - 0 => Pt1Cc::Force0, - 1 => Pt1Cc::Pass, - 2 => Pt1Cc::Complement, - 3 => Pt1Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Cc::Force1 - } -} -#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] -pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; -impl<'a, REG> Pt1CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force1) - } -} -#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Bc {} -#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] -pub type Pt1BcR = crate::FieldReader; -impl Pt1BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Bc { - match self.bits { - 0 => Pt1Bc::Force0, - 1 => Pt1Bc::Pass, - 2 => Pt1Bc::Complement, - 3 => Pt1Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Bc::Force1 - } -} -#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] -pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; -impl<'a, REG> Pt1BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force1) - } -} -#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt1Ac {} -#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] -pub type Pt1AcR = crate::FieldReader; -impl Pt1AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Ac { - match self.bits { - 0 => Pt1Ac::Force0, - 1 => Pt1Ac::Pass, - 2 => Pt1Ac::Complement, - 3 => Pt1Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Ac::Force1 - } -} -#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] -pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; -impl<'a, REG> Pt1AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force1) - } -} -#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Dc {} -#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] -pub type Pt0DcR = crate::FieldReader; -impl Pt0DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Dc { - match self.bits { - 0 => Pt0Dc::Force0, - 1 => Pt0Dc::Pass, - 2 => Pt0Dc::Complement, - 3 => Pt0Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Dc::Force1 - } -} -#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] -pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; -impl<'a, REG> Pt0DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force1) - } -} -#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Cc {} -#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] -pub type Pt0CcR = crate::FieldReader; -impl Pt0CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Cc { - match self.bits { - 0 => Pt0Cc::Force0, - 1 => Pt0Cc::Pass, - 2 => Pt0Cc::Complement, - 3 => Pt0Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Cc::Force1 - } -} -#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] -pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; -impl<'a, REG> Pt0CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force1) - } -} -#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Bc {} -#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] -pub type Pt0BcR = crate::FieldReader; -impl Pt0BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Bc { - match self.bits { - 0 => Pt0Bc::Force0, - 1 => Pt0Bc::Pass, - 2 => Pt0Bc::Complement, - 3 => Pt0Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Bc::Force1 - } -} -#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] -pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; -impl<'a, REG> Pt0BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force1) - } -} -#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt0Ac {} -#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] -pub type Pt0AcR = crate::FieldReader; -impl Pt0AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Ac { - match self.bits { - 0 => Pt0Ac::Force0, - 1 => Pt0Ac::Pass, - 2 => Pt0Ac::Complement, - 3 => Pt0Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Ac::Force1 - } -} -#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] -pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; -impl<'a, REG> Pt0AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&self) -> Pt1DcR { - Pt1DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&self) -> Pt1CcR { - Pt1CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&self) -> Pt1BcR { - Pt1BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&self) -> Pt1AcR { - Pt1AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&self) -> Pt0DcR { - Pt0DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&self) -> Pt0CcR { - Pt0CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&self) -> Pt0BcR { - Pt0BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&self) -> Pt0AcR { - Pt0AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&mut self) -> Pt1DcW { - Pt1DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&mut self) -> Pt1CcW { - Pt1CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&mut self) -> Pt1BcW { - Pt1BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&mut self) -> Pt1AcW { - Pt1AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&mut self) -> Pt0DcW { - Pt0DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&mut self) -> Pt0CcW { - Pt0CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&mut self) -> Pt0BcW { - Pt0BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&mut self) -> Pt0AcW { - Pt0AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt012::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt012::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt012Spec; -impl crate::RegisterSpec for Bfcrt012Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt012::R`](R) reader structure"] -impl crate::Readable for Bfcrt012Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt012::W`](W) writer structure"] -impl crate::Writable for Bfcrt012Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT012 to value 0"] -impl crate::Resettable for Bfcrt012Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt013.rs b/mcxa276-pac/src/aoi0/bfcrt013.rs deleted file mode 100644 index 09ae259bd..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt013.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT013` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT013` writer"] -pub type W = crate::W; -#[doc = "Product Term 1, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Dc {} -#[doc = "Field `PT1_DC` reader - Product Term 1, Input D Configuration"] -pub type Pt1DcR = crate::FieldReader; -impl Pt1DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Dc { - match self.bits { - 0 => Pt1Dc::Force0, - 1 => Pt1Dc::Pass, - 2 => Pt1Dc::Complement, - 3 => Pt1Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Dc::Force1 - } -} -#[doc = "Field `PT1_DC` writer - Product Term 1, Input D Configuration"] -pub type Pt1DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Dc, crate::Safe>; -impl<'a, REG> Pt1DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Dc::Force1) - } -} -#[doc = "Product Term 1, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Cc {} -#[doc = "Field `PT1_CC` reader - Product Term 1, Input C Configuration"] -pub type Pt1CcR = crate::FieldReader; -impl Pt1CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Cc { - match self.bits { - 0 => Pt1Cc::Force0, - 1 => Pt1Cc::Pass, - 2 => Pt1Cc::Complement, - 3 => Pt1Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Cc::Force1 - } -} -#[doc = "Field `PT1_CC` writer - Product Term 1, Input C Configuration"] -pub type Pt1CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Cc, crate::Safe>; -impl<'a, REG> Pt1CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Cc::Force1) - } -} -#[doc = "Product Term 1, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt1Bc {} -#[doc = "Field `PT1_BC` reader - Product Term 1, Input B Configuration"] -pub type Pt1BcR = crate::FieldReader; -impl Pt1BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Bc { - match self.bits { - 0 => Pt1Bc::Force0, - 1 => Pt1Bc::Pass, - 2 => Pt1Bc::Complement, - 3 => Pt1Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Bc::Force1 - } -} -#[doc = "Field `PT1_BC` writer - Product Term 1, Input B Configuration"] -pub type Pt1BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Bc, crate::Safe>; -impl<'a, REG> Pt1BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Bc::Force1) - } -} -#[doc = "Product Term 1, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt1Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt1Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt1Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt1Ac {} -#[doc = "Field `PT1_AC` reader - Product Term 1, Input A Configuration"] -pub type Pt1AcR = crate::FieldReader; -impl Pt1AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt1Ac { - match self.bits { - 0 => Pt1Ac::Force0, - 1 => Pt1Ac::Pass, - 2 => Pt1Ac::Complement, - 3 => Pt1Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt1Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt1Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt1Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt1Ac::Force1 - } -} -#[doc = "Field `PT1_AC` writer - Product Term 1, Input A Configuration"] -pub type Pt1AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt1Ac, crate::Safe>; -impl<'a, REG> Pt1AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt1Ac::Force1) - } -} -#[doc = "Product Term 0, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Dc {} -#[doc = "Field `PT0_DC` reader - Product Term 0, Input D Configuration"] -pub type Pt0DcR = crate::FieldReader; -impl Pt0DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Dc { - match self.bits { - 0 => Pt0Dc::Force0, - 1 => Pt0Dc::Pass, - 2 => Pt0Dc::Complement, - 3 => Pt0Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Dc::Force1 - } -} -#[doc = "Field `PT0_DC` writer - Product Term 0, Input D Configuration"] -pub type Pt0DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Dc, crate::Safe>; -impl<'a, REG> Pt0DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Dc::Force1) - } -} -#[doc = "Product Term 0, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Cc {} -#[doc = "Field `PT0_CC` reader - Product Term 0, Input C Configuration"] -pub type Pt0CcR = crate::FieldReader; -impl Pt0CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Cc { - match self.bits { - 0 => Pt0Cc::Force0, - 1 => Pt0Cc::Pass, - 2 => Pt0Cc::Complement, - 3 => Pt0Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Cc::Force1 - } -} -#[doc = "Field `PT0_CC` writer - Product Term 0, Input C Configuration"] -pub type Pt0CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Cc, crate::Safe>; -impl<'a, REG> Pt0CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Cc::Force1) - } -} -#[doc = "Product Term 0, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt0Bc {} -#[doc = "Field `PT0_BC` reader - Product Term 0, Input B Configuration"] -pub type Pt0BcR = crate::FieldReader; -impl Pt0BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Bc { - match self.bits { - 0 => Pt0Bc::Force0, - 1 => Pt0Bc::Pass, - 2 => Pt0Bc::Complement, - 3 => Pt0Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Bc::Force1 - } -} -#[doc = "Field `PT0_BC` writer - Product Term 0, Input B Configuration"] -pub type Pt0BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Bc, crate::Safe>; -impl<'a, REG> Pt0BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Bc::Force1) - } -} -#[doc = "Product Term 0, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt0Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt0Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt0Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt0Ac {} -#[doc = "Field `PT0_AC` reader - Product Term 0, Input A Configuration"] -pub type Pt0AcR = crate::FieldReader; -impl Pt0AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt0Ac { - match self.bits { - 0 => Pt0Ac::Force0, - 1 => Pt0Ac::Pass, - 2 => Pt0Ac::Complement, - 3 => Pt0Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt0Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt0Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt0Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt0Ac::Force1 - } -} -#[doc = "Field `PT0_AC` writer - Product Term 0, Input A Configuration"] -pub type Pt0AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt0Ac, crate::Safe>; -impl<'a, REG> Pt0AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt0Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&self) -> Pt1DcR { - Pt1DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&self) -> Pt1CcR { - Pt1CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&self) -> Pt1BcR { - Pt1BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&self) -> Pt1AcR { - Pt1AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&self) -> Pt0DcR { - Pt0DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&self) -> Pt0CcR { - Pt0CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&self) -> Pt0BcR { - Pt0BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&self) -> Pt0AcR { - Pt0AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 1, Input D Configuration"] - #[inline(always)] - pub fn pt1_dc(&mut self) -> Pt1DcW { - Pt1DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 1, Input C Configuration"] - #[inline(always)] - pub fn pt1_cc(&mut self) -> Pt1CcW { - Pt1CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 1, Input B Configuration"] - #[inline(always)] - pub fn pt1_bc(&mut self) -> Pt1BcW { - Pt1BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 1, Input A Configuration"] - #[inline(always)] - pub fn pt1_ac(&mut self) -> Pt1AcW { - Pt1AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 0, Input D Configuration"] - #[inline(always)] - pub fn pt0_dc(&mut self) -> Pt0DcW { - Pt0DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 0, Input C Configuration"] - #[inline(always)] - pub fn pt0_cc(&mut self) -> Pt0CcW { - Pt0CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 0, Input B Configuration"] - #[inline(always)] - pub fn pt0_bc(&mut self) -> Pt0BcW { - Pt0BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 0, Input A Configuration"] - #[inline(always)] - pub fn pt0_ac(&mut self) -> Pt0AcW { - Pt0AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 0 and 1 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt013::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt013::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt013Spec; -impl crate::RegisterSpec for Bfcrt013Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt013::R`](R) reader structure"] -impl crate::Readable for Bfcrt013Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt013::W`](W) writer structure"] -impl crate::Writable for Bfcrt013Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT013 to value 0"] -impl crate::Resettable for Bfcrt013Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt230.rs b/mcxa276-pac/src/aoi0/bfcrt230.rs deleted file mode 100644 index ab9f3f29e..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt230.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT230` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT230` writer"] -pub type W = crate::W; -#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Dc {} -#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] -pub type Pt3DcR = crate::FieldReader; -impl Pt3DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Dc { - match self.bits { - 0 => Pt3Dc::Force0, - 1 => Pt3Dc::Pass, - 2 => Pt3Dc::Complement, - 3 => Pt3Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Dc::Force1 - } -} -#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] -pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; -impl<'a, REG> Pt3DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force1) - } -} -#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Cc {} -#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] -pub type Pt3CcR = crate::FieldReader; -impl Pt3CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Cc { - match self.bits { - 0 => Pt3Cc::Force0, - 1 => Pt3Cc::Pass, - 2 => Pt3Cc::Complement, - 3 => Pt3Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Cc::Force1 - } -} -#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] -pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; -impl<'a, REG> Pt3CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force1) - } -} -#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Bc {} -#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] -pub type Pt3BcR = crate::FieldReader; -impl Pt3BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Bc { - match self.bits { - 0 => Pt3Bc::Force0, - 1 => Pt3Bc::Pass, - 2 => Pt3Bc::Complement, - 3 => Pt3Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Bc::Force1 - } -} -#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] -pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; -impl<'a, REG> Pt3BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force1) - } -} -#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt3Ac {} -#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] -pub type Pt3AcR = crate::FieldReader; -impl Pt3AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Ac { - match self.bits { - 0 => Pt3Ac::Force0, - 1 => Pt3Ac::Pass, - 2 => Pt3Ac::Complement, - 3 => Pt3Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Ac::Complement - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Ac::Force1 - } -} -#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] -pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; -impl<'a, REG> Pt3AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Complement) - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force1) - } -} -#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Dc {} -#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] -pub type Pt2DcR = crate::FieldReader; -impl Pt2DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Dc { - match self.bits { - 0 => Pt2Dc::Force0, - 1 => Pt2Dc::Pass, - 2 => Pt2Dc::Complement, - 3 => Pt2Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Dc::Force1 - } -} -#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] -pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; -impl<'a, REG> Pt2DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force1) - } -} -#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Cc {} -#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] -pub type Pt2CcR = crate::FieldReader; -impl Pt2CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Cc { - match self.bits { - 0 => Pt2Cc::Force0, - 1 => Pt2Cc::Pass, - 2 => Pt2Cc::Complement, - 3 => Pt2Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Cc::Force1 - } -} -#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] -pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; -impl<'a, REG> Pt2CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force1) - } -} -#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Bc {} -#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] -pub type Pt2BcR = crate::FieldReader; -impl Pt2BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Bc { - match self.bits { - 0 => Pt2Bc::Force0, - 1 => Pt2Bc::Pass, - 2 => Pt2Bc::Complement, - 3 => Pt2Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Bc::Force1 - } -} -#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] -pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; -impl<'a, REG> Pt2BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force1) - } -} -#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt2Ac {} -#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] -pub type Pt2AcR = crate::FieldReader; -impl Pt2AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Ac { - match self.bits { - 0 => Pt2Ac::Force0, - 1 => Pt2Ac::Pass, - 2 => Pt2Ac::Complement, - 3 => Pt2Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Ac::Force1 - } -} -#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] -pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; -impl<'a, REG> Pt2AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&self) -> Pt3DcR { - Pt3DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&self) -> Pt3CcR { - Pt3CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&self) -> Pt3BcR { - Pt3BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&self) -> Pt3AcR { - Pt3AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&self) -> Pt2DcR { - Pt2DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&self) -> Pt2CcR { - Pt2CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&self) -> Pt2BcR { - Pt2BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&self) -> Pt2AcR { - Pt2AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&mut self) -> Pt3DcW { - Pt3DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&mut self) -> Pt3CcW { - Pt3CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&mut self) -> Pt3BcW { - Pt3BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&mut self) -> Pt3AcW { - Pt3AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&mut self) -> Pt2DcW { - Pt2DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&mut self) -> Pt2CcW { - Pt2CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&mut self) -> Pt2BcW { - Pt2BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&mut self) -> Pt2AcW { - Pt2AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT0\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt230::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt230::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt230Spec; -impl crate::RegisterSpec for Bfcrt230Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt230::R`](R) reader structure"] -impl crate::Readable for Bfcrt230Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt230::W`](W) writer structure"] -impl crate::Writable for Bfcrt230Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT230 to value 0"] -impl crate::Resettable for Bfcrt230Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt231.rs b/mcxa276-pac/src/aoi0/bfcrt231.rs deleted file mode 100644 index 01844e802..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt231.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT231` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT231` writer"] -pub type W = crate::W; -#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Dc {} -#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] -pub type Pt3DcR = crate::FieldReader; -impl Pt3DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Dc { - match self.bits { - 0 => Pt3Dc::Force0, - 1 => Pt3Dc::Pass, - 2 => Pt3Dc::Complement, - 3 => Pt3Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Dc::Force1 - } -} -#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] -pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; -impl<'a, REG> Pt3DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force1) - } -} -#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Cc {} -#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] -pub type Pt3CcR = crate::FieldReader; -impl Pt3CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Cc { - match self.bits { - 0 => Pt3Cc::Force0, - 1 => Pt3Cc::Pass, - 2 => Pt3Cc::Complement, - 3 => Pt3Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Cc::Force1 - } -} -#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] -pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; -impl<'a, REG> Pt3CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force1) - } -} -#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Bc {} -#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] -pub type Pt3BcR = crate::FieldReader; -impl Pt3BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Bc { - match self.bits { - 0 => Pt3Bc::Force0, - 1 => Pt3Bc::Pass, - 2 => Pt3Bc::Complement, - 3 => Pt3Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Bc::Force1 - } -} -#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] -pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; -impl<'a, REG> Pt3BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force1) - } -} -#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt3Ac {} -#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] -pub type Pt3AcR = crate::FieldReader; -impl Pt3AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Ac { - match self.bits { - 0 => Pt3Ac::Force0, - 1 => Pt3Ac::Pass, - 2 => Pt3Ac::Complement, - 3 => Pt3Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Ac::Complement - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Ac::Force1 - } -} -#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] -pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; -impl<'a, REG> Pt3AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Complement) - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force1) - } -} -#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Dc {} -#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] -pub type Pt2DcR = crate::FieldReader; -impl Pt2DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Dc { - match self.bits { - 0 => Pt2Dc::Force0, - 1 => Pt2Dc::Pass, - 2 => Pt2Dc::Complement, - 3 => Pt2Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Dc::Force1 - } -} -#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] -pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; -impl<'a, REG> Pt2DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force1) - } -} -#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Cc {} -#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] -pub type Pt2CcR = crate::FieldReader; -impl Pt2CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Cc { - match self.bits { - 0 => Pt2Cc::Force0, - 1 => Pt2Cc::Pass, - 2 => Pt2Cc::Complement, - 3 => Pt2Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Cc::Force1 - } -} -#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] -pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; -impl<'a, REG> Pt2CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force1) - } -} -#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Bc {} -#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] -pub type Pt2BcR = crate::FieldReader; -impl Pt2BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Bc { - match self.bits { - 0 => Pt2Bc::Force0, - 1 => Pt2Bc::Pass, - 2 => Pt2Bc::Complement, - 3 => Pt2Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Bc::Force1 - } -} -#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] -pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; -impl<'a, REG> Pt2BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force1) - } -} -#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt2Ac {} -#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] -pub type Pt2AcR = crate::FieldReader; -impl Pt2AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Ac { - match self.bits { - 0 => Pt2Ac::Force0, - 1 => Pt2Ac::Pass, - 2 => Pt2Ac::Complement, - 3 => Pt2Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Ac::Force1 - } -} -#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] -pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; -impl<'a, REG> Pt2AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&self) -> Pt3DcR { - Pt3DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&self) -> Pt3CcR { - Pt3CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&self) -> Pt3BcR { - Pt3BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&self) -> Pt3AcR { - Pt3AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&self) -> Pt2DcR { - Pt2DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&self) -> Pt2CcR { - Pt2CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&self) -> Pt2BcR { - Pt2BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&self) -> Pt2AcR { - Pt2AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&mut self) -> Pt3DcW { - Pt3DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&mut self) -> Pt3CcW { - Pt3CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&mut self) -> Pt3BcW { - Pt3BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&mut self) -> Pt3AcW { - Pt3AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&mut self) -> Pt2DcW { - Pt2DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&mut self) -> Pt2CcW { - Pt2CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&mut self) -> Pt2BcW { - Pt2BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&mut self) -> Pt2AcW { - Pt2AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT1\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt231::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt231::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt231Spec; -impl crate::RegisterSpec for Bfcrt231Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt231::R`](R) reader structure"] -impl crate::Readable for Bfcrt231Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt231::W`](W) writer structure"] -impl crate::Writable for Bfcrt231Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT231 to value 0"] -impl crate::Resettable for Bfcrt231Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt232.rs b/mcxa276-pac/src/aoi0/bfcrt232.rs deleted file mode 100644 index abbf0c7ba..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt232.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT232` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT232` writer"] -pub type W = crate::W; -#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Dc {} -#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] -pub type Pt3DcR = crate::FieldReader; -impl Pt3DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Dc { - match self.bits { - 0 => Pt3Dc::Force0, - 1 => Pt3Dc::Pass, - 2 => Pt3Dc::Complement, - 3 => Pt3Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Dc::Force1 - } -} -#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] -pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; -impl<'a, REG> Pt3DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force1) - } -} -#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Cc {} -#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] -pub type Pt3CcR = crate::FieldReader; -impl Pt3CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Cc { - match self.bits { - 0 => Pt3Cc::Force0, - 1 => Pt3Cc::Pass, - 2 => Pt3Cc::Complement, - 3 => Pt3Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Cc::Force1 - } -} -#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] -pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; -impl<'a, REG> Pt3CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force1) - } -} -#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Bc {} -#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] -pub type Pt3BcR = crate::FieldReader; -impl Pt3BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Bc { - match self.bits { - 0 => Pt3Bc::Force0, - 1 => Pt3Bc::Pass, - 2 => Pt3Bc::Complement, - 3 => Pt3Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Bc::Force1 - } -} -#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] -pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; -impl<'a, REG> Pt3BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force1) - } -} -#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt3Ac {} -#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] -pub type Pt3AcR = crate::FieldReader; -impl Pt3AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Ac { - match self.bits { - 0 => Pt3Ac::Force0, - 1 => Pt3Ac::Pass, - 2 => Pt3Ac::Complement, - 3 => Pt3Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Ac::Complement - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Ac::Force1 - } -} -#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] -pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; -impl<'a, REG> Pt3AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Complement) - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force1) - } -} -#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Dc {} -#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] -pub type Pt2DcR = crate::FieldReader; -impl Pt2DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Dc { - match self.bits { - 0 => Pt2Dc::Force0, - 1 => Pt2Dc::Pass, - 2 => Pt2Dc::Complement, - 3 => Pt2Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Dc::Force1 - } -} -#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] -pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; -impl<'a, REG> Pt2DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force1) - } -} -#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Cc {} -#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] -pub type Pt2CcR = crate::FieldReader; -impl Pt2CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Cc { - match self.bits { - 0 => Pt2Cc::Force0, - 1 => Pt2Cc::Pass, - 2 => Pt2Cc::Complement, - 3 => Pt2Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Cc::Force1 - } -} -#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] -pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; -impl<'a, REG> Pt2CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force1) - } -} -#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Bc {} -#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] -pub type Pt2BcR = crate::FieldReader; -impl Pt2BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Bc { - match self.bits { - 0 => Pt2Bc::Force0, - 1 => Pt2Bc::Pass, - 2 => Pt2Bc::Complement, - 3 => Pt2Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Bc::Force1 - } -} -#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] -pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; -impl<'a, REG> Pt2BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force1) - } -} -#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt2Ac {} -#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] -pub type Pt2AcR = crate::FieldReader; -impl Pt2AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Ac { - match self.bits { - 0 => Pt2Ac::Force0, - 1 => Pt2Ac::Pass, - 2 => Pt2Ac::Complement, - 3 => Pt2Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Ac::Force1 - } -} -#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] -pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; -impl<'a, REG> Pt2AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&self) -> Pt3DcR { - Pt3DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&self) -> Pt3CcR { - Pt3CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&self) -> Pt3BcR { - Pt3BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&self) -> Pt3AcR { - Pt3AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&self) -> Pt2DcR { - Pt2DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&self) -> Pt2CcR { - Pt2CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&self) -> Pt2BcR { - Pt2BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&self) -> Pt2AcR { - Pt2AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&mut self) -> Pt3DcW { - Pt3DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&mut self) -> Pt3CcW { - Pt3CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&mut self) -> Pt3BcW { - Pt3BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&mut self) -> Pt3AcW { - Pt3AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&mut self) -> Pt2DcW { - Pt2DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&mut self) -> Pt2CcW { - Pt2CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&mut self) -> Pt2BcW { - Pt2BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&mut self) -> Pt2AcW { - Pt2AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT2\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt232::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt232::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt232Spec; -impl crate::RegisterSpec for Bfcrt232Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt232::R`](R) reader structure"] -impl crate::Readable for Bfcrt232Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt232::W`](W) writer structure"] -impl crate::Writable for Bfcrt232Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT232 to value 0"] -impl crate::Resettable for Bfcrt232Spec {} diff --git a/mcxa276-pac/src/aoi0/bfcrt233.rs b/mcxa276-pac/src/aoi0/bfcrt233.rs deleted file mode 100644 index b478f4f86..000000000 --- a/mcxa276-pac/src/aoi0/bfcrt233.rs +++ /dev/null @@ -1,789 +0,0 @@ -#[doc = "Register `BFCRT233` reader"] -pub type R = crate::R; -#[doc = "Register `BFCRT233` writer"] -pub type W = crate::W; -#[doc = "Product Term 3, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Dc {} -#[doc = "Field `PT3_DC` reader - Product Term 3, Input D Configuration"] -pub type Pt3DcR = crate::FieldReader; -impl Pt3DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Dc { - match self.bits { - 0 => Pt3Dc::Force0, - 1 => Pt3Dc::Pass, - 2 => Pt3Dc::Complement, - 3 => Pt3Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Dc::Force1 - } -} -#[doc = "Field `PT3_DC` writer - Product Term 3, Input D Configuration"] -pub type Pt3DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Dc, crate::Safe>; -impl<'a, REG> Pt3DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Dc::Force1) - } -} -#[doc = "Product Term 3, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Cc {} -#[doc = "Field `PT3_CC` reader - Product Term 3, Input C Configuration"] -pub type Pt3CcR = crate::FieldReader; -impl Pt3CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Cc { - match self.bits { - 0 => Pt3Cc::Force0, - 1 => Pt3Cc::Pass, - 2 => Pt3Cc::Complement, - 3 => Pt3Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Cc::Force1 - } -} -#[doc = "Field `PT3_CC` writer - Product Term 3, Input C Configuration"] -pub type Pt3CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Cc, crate::Safe>; -impl<'a, REG> Pt3CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Cc::Force1) - } -} -#[doc = "Product Term 3, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt3Bc {} -#[doc = "Field `PT3_BC` reader - Product Term 3, Input B Configuration"] -pub type Pt3BcR = crate::FieldReader; -impl Pt3BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Bc { - match self.bits { - 0 => Pt3Bc::Force0, - 1 => Pt3Bc::Pass, - 2 => Pt3Bc::Complement, - 3 => Pt3Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Bc::Force1 - } -} -#[doc = "Field `PT3_BC` writer - Product Term 3, Input B Configuration"] -pub type Pt3BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Bc, crate::Safe>; -impl<'a, REG> Pt3BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Bc::Force1) - } -} -#[doc = "Product Term 3, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt3Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt3Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt3Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt3Ac {} -#[doc = "Field `PT3_AC` reader - Product Term 3, Input A Configuration"] -pub type Pt3AcR = crate::FieldReader; -impl Pt3AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt3Ac { - match self.bits { - 0 => Pt3Ac::Force0, - 1 => Pt3Ac::Pass, - 2 => Pt3Ac::Complement, - 3 => Pt3Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt3Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt3Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt3Ac::Complement - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt3Ac::Force1 - } -} -#[doc = "Field `PT3_AC` writer - Product Term 3, Input A Configuration"] -pub type Pt3AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt3Ac, crate::Safe>; -impl<'a, REG> Pt3AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Complement) - } - #[doc = "Force input to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt3Ac::Force1) - } -} -#[doc = "Product Term 2, Input D Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Dc { - #[doc = "0: Force input D to become 0"] - Force0 = 0, - #[doc = "1: Pass input D"] - Pass = 1, - #[doc = "2: Complement input D"] - Complement = 2, - #[doc = "3: Force input D to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Dc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Dc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Dc {} -#[doc = "Field `PT2_DC` reader - Product Term 2, Input D Configuration"] -pub type Pt2DcR = crate::FieldReader; -impl Pt2DcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Dc { - match self.bits { - 0 => Pt2Dc::Force0, - 1 => Pt2Dc::Pass, - 2 => Pt2Dc::Complement, - 3 => Pt2Dc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Dc::Force0 - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Dc::Pass - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Dc::Complement - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Dc::Force1 - } -} -#[doc = "Field `PT2_DC` writer - Product Term 2, Input D Configuration"] -pub type Pt2DcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Dc, crate::Safe>; -impl<'a, REG> Pt2DcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input D to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force0) - } - #[doc = "Pass input D"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Pass) - } - #[doc = "Complement input D"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Complement) - } - #[doc = "Force input D to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Dc::Force1) - } -} -#[doc = "Product Term 2, Input C Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Cc { - #[doc = "0: Force input C to become 0"] - Force0 = 0, - #[doc = "1: Pass input C"] - Pass = 1, - #[doc = "2: Complement input C"] - Complement = 2, - #[doc = "3: Force input C to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Cc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Cc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Cc {} -#[doc = "Field `PT2_CC` reader - Product Term 2, Input C Configuration"] -pub type Pt2CcR = crate::FieldReader; -impl Pt2CcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Cc { - match self.bits { - 0 => Pt2Cc::Force0, - 1 => Pt2Cc::Pass, - 2 => Pt2Cc::Complement, - 3 => Pt2Cc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Cc::Force0 - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Cc::Pass - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Cc::Complement - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Cc::Force1 - } -} -#[doc = "Field `PT2_CC` writer - Product Term 2, Input C Configuration"] -pub type Pt2CcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Cc, crate::Safe>; -impl<'a, REG> Pt2CcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input C to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force0) - } - #[doc = "Pass input C"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Pass) - } - #[doc = "Complement input C"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Complement) - } - #[doc = "Force input C to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Cc::Force1) - } -} -#[doc = "Product Term 2, Input B Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Bc { - #[doc = "0: Force input B to become 0"] - Force0 = 0, - #[doc = "1: Pass input B"] - Pass = 1, - #[doc = "2: Complement input B"] - Complement = 2, - #[doc = "3: Force input B to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Bc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Bc { - type Ux = u8; -} -impl crate::IsEnum for Pt2Bc {} -#[doc = "Field `PT2_BC` reader - Product Term 2, Input B Configuration"] -pub type Pt2BcR = crate::FieldReader; -impl Pt2BcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Bc { - match self.bits { - 0 => Pt2Bc::Force0, - 1 => Pt2Bc::Pass, - 2 => Pt2Bc::Complement, - 3 => Pt2Bc::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Bc::Force0 - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Bc::Pass - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Bc::Complement - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Bc::Force1 - } -} -#[doc = "Field `PT2_BC` writer - Product Term 2, Input B Configuration"] -pub type Pt2BcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Bc, crate::Safe>; -impl<'a, REG> Pt2BcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input B to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force0) - } - #[doc = "Pass input B"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Pass) - } - #[doc = "Complement input B"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Complement) - } - #[doc = "Force input B to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Bc::Force1) - } -} -#[doc = "Product Term 2, Input A Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pt2Ac { - #[doc = "0: Force input A to become 0"] - Force0 = 0, - #[doc = "1: Pass input A"] - Pass = 1, - #[doc = "2: Complement input A"] - Complement = 2, - #[doc = "3: Force input A to become 1"] - Force1 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pt2Ac) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pt2Ac { - type Ux = u8; -} -impl crate::IsEnum for Pt2Ac {} -#[doc = "Field `PT2_AC` reader - Product Term 2, Input A Configuration"] -pub type Pt2AcR = crate::FieldReader; -impl Pt2AcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt2Ac { - match self.bits { - 0 => Pt2Ac::Force0, - 1 => Pt2Ac::Pass, - 2 => Pt2Ac::Complement, - 3 => Pt2Ac::Force1, - _ => unreachable!(), - } - } - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn is_force_0(&self) -> bool { - *self == Pt2Ac::Force0 - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn is_pass(&self) -> bool { - *self == Pt2Ac::Pass - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn is_complement(&self) -> bool { - *self == Pt2Ac::Complement - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn is_force_1(&self) -> bool { - *self == Pt2Ac::Force1 - } -} -#[doc = "Field `PT2_AC` writer - Product Term 2, Input A Configuration"] -pub type Pt2AcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pt2Ac, crate::Safe>; -impl<'a, REG> Pt2AcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Force input A to become 0"] - #[inline(always)] - pub fn force_0(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force0) - } - #[doc = "Pass input A"] - #[inline(always)] - pub fn pass(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Pass) - } - #[doc = "Complement input A"] - #[inline(always)] - pub fn complement(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Complement) - } - #[doc = "Force input A to become 1"] - #[inline(always)] - pub fn force_1(self) -> &'a mut crate::W { - self.variant(Pt2Ac::Force1) - } -} -impl R { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&self) -> Pt3DcR { - Pt3DcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&self) -> Pt3CcR { - Pt3CcR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&self) -> Pt3BcR { - Pt3BcR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&self) -> Pt3AcR { - Pt3AcR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&self) -> Pt2DcR { - Pt2DcR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&self) -> Pt2CcR { - Pt2CcR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&self) -> Pt2BcR { - Pt2BcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&self) -> Pt2AcR { - Pt2AcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Product Term 3, Input D Configuration"] - #[inline(always)] - pub fn pt3_dc(&mut self) -> Pt3DcW { - Pt3DcW::new(self, 0) - } - #[doc = "Bits 2:3 - Product Term 3, Input C Configuration"] - #[inline(always)] - pub fn pt3_cc(&mut self) -> Pt3CcW { - Pt3CcW::new(self, 2) - } - #[doc = "Bits 4:5 - Product Term 3, Input B Configuration"] - #[inline(always)] - pub fn pt3_bc(&mut self) -> Pt3BcW { - Pt3BcW::new(self, 4) - } - #[doc = "Bits 6:7 - Product Term 3, Input A Configuration"] - #[inline(always)] - pub fn pt3_ac(&mut self) -> Pt3AcW { - Pt3AcW::new(self, 6) - } - #[doc = "Bits 8:9 - Product Term 2, Input D Configuration"] - #[inline(always)] - pub fn pt2_dc(&mut self) -> Pt2DcW { - Pt2DcW::new(self, 8) - } - #[doc = "Bits 10:11 - Product Term 2, Input C Configuration"] - #[inline(always)] - pub fn pt2_cc(&mut self) -> Pt2CcW { - Pt2CcW::new(self, 10) - } - #[doc = "Bits 12:13 - Product Term 2, Input B Configuration"] - #[inline(always)] - pub fn pt2_bc(&mut self) -> Pt2BcW { - Pt2BcW::new(self, 12) - } - #[doc = "Bits 14:15 - Product Term 2, Input A Configuration"] - #[inline(always)] - pub fn pt2_ac(&mut self) -> Pt2AcW { - Pt2AcW::new(self, 14) - } -} -#[doc = "Boolean Function Term 2 and 3 Configuration for EVENT3\n\nYou can [`read`](crate::Reg::read) this register and get [`bfcrt233::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfcrt233::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bfcrt233Spec; -impl crate::RegisterSpec for Bfcrt233Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`bfcrt233::R`](R) reader structure"] -impl crate::Readable for Bfcrt233Spec {} -#[doc = "`write(|w| ..)` method takes [`bfcrt233::W`](W) writer structure"] -impl crate::Writable for Bfcrt233Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BFCRT233 to value 0"] -impl crate::Resettable for Bfcrt233Spec {} diff --git a/mcxa276-pac/src/can0.rs b/mcxa276-pac/src/can0.rs deleted file mode 100644 index b328a994f..000000000 --- a/mcxa276-pac/src/can0.rs +++ /dev/null @@ -1,7163 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - mcr: Mcr, - ctrl1: Ctrl1, - timer: Timer, - _reserved3: [u8; 0x04], - rxmgmask: Rxmgmask, - rx14mask: Rx14mask, - rx15mask: Rx15mask, - ecr: Ecr, - esr1: Esr1, - _reserved8: [u8; 0x04], - imask1: Imask1, - _reserved9: [u8; 0x04], - iflag1: Iflag1, - ctrl2: Ctrl2, - esr2: Esr2, - _reserved12: [u8; 0x08], - crcr: Crcr, - rxfgmask: Rxfgmask, - rxfir: Rxfir, - cbt: Cbt, - _reserved16: [u8; 0x2c], - _reserved_16_mb_: [u8; 0x04], - _reserved_17_mb_: [u8; 0x04], - _reserved_18_mb: [u8; 0x04], - _reserved_19_mb: [u8; 0x04], - _reserved_20_mb_: [u8; 0x04], - _reserved_21_mb_: [u8; 0x04], - _reserved_22_mb: [u8; 0x04], - _reserved_23_mb: [u8; 0x04], - _reserved_24_mb_: [u8; 0x04], - _reserved_25_mb_: [u8; 0x04], - _reserved_26_mb: [u8; 0x04], - _reserved_27_mb: [u8; 0x04], - _reserved_28_mb_: [u8; 0x04], - _reserved_29_mb_: [u8; 0x04], - _reserved_30_mb: [u8; 0x04], - _reserved_31_mb: [u8; 0x04], - _reserved_32_mb_: [u8; 0x04], - _reserved_33_mb_: [u8; 0x04], - _reserved_34_mb: [u8; 0x04], - _reserved_35_mb: [u8; 0x04], - _reserved_36_mb_: [u8; 0x04], - _reserved_37_mb_: [u8; 0x04], - _reserved_38_mb: [u8; 0x04], - _reserved_39_mb: [u8; 0x04], - _reserved_40_mb_: [u8; 0x04], - _reserved_41_mb_: [u8; 0x04], - _reserved_42_mb: [u8; 0x04], - _reserved_43_mb: [u8; 0x04], - _reserved_44_mb_: [u8; 0x04], - _reserved_45_mb_: [u8; 0x04], - _reserved_46_mb: [u8; 0x04], - _reserved_47_mb: [u8; 0x04], - _reserved_48_mb_: [u8; 0x04], - _reserved_49_mb_: [u8; 0x04], - _reserved_50_mb: [u8; 0x04], - _reserved_51_mb: [u8; 0x04], - _reserved_52_mb_: [u8; 0x04], - _reserved_53_mb_: [u8; 0x04], - _reserved_54_mb: [u8; 0x04], - _reserved_55_mb: [u8; 0x04], - _reserved_56_mb_: [u8; 0x04], - _reserved_57_mb_: [u8; 0x04], - _reserved_58_mb: [u8; 0x04], - _reserved_59_mb: [u8; 0x04], - _reserved_60_mb_: [u8; 0x04], - _reserved_61_mb_: [u8; 0x04], - _reserved_62_mb: [u8; 0x04], - _reserved_63_mb: [u8; 0x04], - _reserved_64_mb_: [u8; 0x04], - _reserved_65_mb_: [u8; 0x04], - _reserved_66_mb: [u8; 0x04], - _reserved_67_mb: [u8; 0x04], - _reserved_68_mb_: [u8; 0x04], - _reserved_69_mb_: [u8; 0x04], - _reserved_70_mb: [u8; 0x04], - _reserved_71_mb: [u8; 0x04], - _reserved_72_mb_: [u8; 0x04], - _reserved_73_mb_: [u8; 0x04], - _reserved_74_mb: [u8; 0x04], - _reserved_75_mb: [u8; 0x04], - _reserved_76_mb_: [u8; 0x04], - _reserved_77_mb_: [u8; 0x04], - _reserved_78_mb: [u8; 0x04], - _reserved_79_mb: [u8; 0x04], - _reserved_80_mb_: [u8; 0x04], - _reserved_81_mb_: [u8; 0x04], - _reserved_82_mb: [u8; 0x04], - _reserved_83_mb: [u8; 0x04], - _reserved_84_mb_: [u8; 0x04], - _reserved_85_mb_: [u8; 0x04], - _reserved_86_mb: [u8; 0x04], - _reserved_87_mb: [u8; 0x04], - _reserved_88_mb_: [u8; 0x04], - _reserved_89_mb_: [u8; 0x04], - _reserved_90_mb: [u8; 0x04], - _reserved_91_mb: [u8; 0x04], - _reserved_92_mb_: [u8; 0x04], - _reserved_93_mb_: [u8; 0x04], - _reserved_94_mb: [u8; 0x04], - _reserved_95_mb: [u8; 0x04], - _reserved_96_mb_: [u8; 0x04], - _reserved_97_mb_: [u8; 0x04], - _reserved_98_mb: [u8; 0x04], - _reserved_99_mb: [u8; 0x04], - _reserved_100_mb_: [u8; 0x04], - _reserved_101_mb_: [u8; 0x04], - _reserved_102_mb: [u8; 0x04], - _reserved_103_mb: [u8; 0x04], - _reserved_104_mb_: [u8; 0x04], - _reserved_105_mb_: [u8; 0x04], - _reserved_106_mb: [u8; 0x04], - _reserved_107_mb: [u8; 0x04], - _reserved_108_mb_: [u8; 0x04], - _reserved_109_mb_: [u8; 0x04], - _reserved_110_mb: [u8; 0x04], - _reserved_111_mb: [u8; 0x04], - _reserved_112_mb_: [u8; 0x04], - _reserved_113_mb_: [u8; 0x04], - _reserved_114_mb: [u8; 0x04], - _reserved_115_mb: [u8; 0x04], - _reserved_116_mb_: [u8; 0x04], - _reserved_117_mb_: [u8; 0x04], - _reserved_118_mb: [u8; 0x04], - _reserved_119_mb: [u8; 0x04], - _reserved_120_mb_: [u8; 0x04], - _reserved_121_mb_: [u8; 0x04], - _reserved_122_mb: [u8; 0x04], - _reserved_123_mb: [u8; 0x04], - _reserved_124_mb_: [u8; 0x04], - _reserved_125_mb_: [u8; 0x04], - _reserved_126_mb: [u8; 0x04], - _reserved_127_mb: [u8; 0x04], - _reserved_128_mb_: [u8; 0x04], - _reserved_129_mb_: [u8; 0x04], - _reserved_130_mb: [u8; 0x04], - _reserved_131_mb: [u8; 0x04], - _reserved_132_mb_: [u8; 0x04], - _reserved_133_mb_: [u8; 0x04], - _reserved_134_mb: [u8; 0x04], - _reserved_135_mb: [u8; 0x04], - _reserved_136_mb_: [u8; 0x04], - _reserved_137_mb_: [u8; 0x04], - _reserved_138_mb: [u8; 0x04], - _reserved_139_mb: [u8; 0x04], - _reserved_140_mb_: [u8; 0x04], - _reserved_141_mb_: [u8; 0x04], - _reserved_142_mb: [u8; 0x04], - _reserved_143_mb: [u8; 0x04], - _reserved144: [u8; 0x0600], - rximr: [Rximr; 32], - _reserved145: [u8; 0x0200], - ctrl1_pn: Ctrl1Pn, - ctrl2_pn: Ctrl2Pn, - wu_mtc: WuMtc, - flt_id1: FltId1, - flt_dlc: FltDlc, - pl1_lo: Pl1Lo, - pl1_hi: Pl1Hi, - flt_id2_idmask: FltId2Idmask, - pl2_plmask_lo: Pl2PlmaskLo, - pl2_plmask_hi: Pl2PlmaskHi, - _reserved155: [u8; 0x18], - wmb: [Wmb; 4], - _reserved156: [u8; 0x70], - eprs: Eprs, - encbt: Encbt, - edcbt: Edcbt, - etdc: Etdc, - fdctrl: Fdctrl, - fdcbt: Fdcbt, - fdcrc: Fdcrc, - erfcr: Erfcr, - erfier: Erfier, - erfsr: Erfsr, - _reserved166: [u8; 0x23e8], - erffel: [Erffel; 32], -} -impl RegisterBlock { - #[doc = "0x00 - Module Configuration"] - #[inline(always)] - pub const fn mcr(&self) -> &Mcr { - &self.mcr - } - #[doc = "0x04 - Control 1"] - #[inline(always)] - pub const fn ctrl1(&self) -> &Ctrl1 { - &self.ctrl1 - } - #[doc = "0x08 - Free-Running Timer"] - #[inline(always)] - pub const fn timer(&self) -> &Timer { - &self.timer - } - #[doc = "0x10 - RX Message Buffers Global Mask"] - #[inline(always)] - pub const fn rxmgmask(&self) -> &Rxmgmask { - &self.rxmgmask - } - #[doc = "0x14 - Receive 14 Mask"] - #[inline(always)] - pub const fn rx14mask(&self) -> &Rx14mask { - &self.rx14mask - } - #[doc = "0x18 - Receive 15 Mask"] - #[inline(always)] - pub const fn rx15mask(&self) -> &Rx15mask { - &self.rx15mask - } - #[doc = "0x1c - Error Counter"] - #[inline(always)] - pub const fn ecr(&self) -> &Ecr { - &self.ecr - } - #[doc = "0x20 - Error and Status 1"] - #[inline(always)] - pub const fn esr1(&self) -> &Esr1 { - &self.esr1 - } - #[doc = "0x28 - Interrupt Masks 1"] - #[inline(always)] - pub const fn imask1(&self) -> &Imask1 { - &self.imask1 - } - #[doc = "0x30 - Interrupt Flags 1"] - #[inline(always)] - pub const fn iflag1(&self) -> &Iflag1 { - &self.iflag1 - } - #[doc = "0x34 - Control 2"] - #[inline(always)] - pub const fn ctrl2(&self) -> &Ctrl2 { - &self.ctrl2 - } - #[doc = "0x38 - Error and Status 2"] - #[inline(always)] - pub const fn esr2(&self) -> &Esr2 { - &self.esr2 - } - #[doc = "0x44 - Cyclic Redundancy Check"] - #[inline(always)] - pub const fn crcr(&self) -> &Crcr { - &self.crcr - } - #[doc = "0x48 - Legacy RX FIFO Global Mask"] - #[inline(always)] - pub const fn rxfgmask(&self) -> &Rxfgmask { - &self.rxfgmask - } - #[doc = "0x4c - Legacy RX FIFO Information"] - #[inline(always)] - pub const fn rxfir(&self) -> &Rxfir { - &self.rxfir - } - #[doc = "0x50 - CAN Bit Timing"] - #[inline(always)] - pub const fn cbt(&self) -> &Cbt { - &self.cbt - } - #[doc = "0x80 - Message Buffer 0 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb0_8b_cs(&self) -> &Mb8bGroupMb0_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } - } - #[doc = "0x80 - Message Buffer 0 CS Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_cs(&self) -> &Mb64bGroupMb0_64bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } - } - #[doc = "0x80 - Message Buffer 0 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_cs(&self) -> &Mb32bGroupMb0_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } - } - #[doc = "0x80 - Message Buffer 0 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb0_16b_cs(&self) -> &Mb16bGroupMb0_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } - } - #[doc = "0x80 - Message Buffer 0 CS Register"] - #[inline(always)] - pub const fn mb_group_cs0(&self) -> &MbGroupCs0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(128).cast() } - } - #[doc = "0x84 - Message Buffer 0 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb0_8b_id(&self) -> &Mb8bGroupMb0_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } - } - #[doc = "0x84 - Message Buffer 0 ID Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_id(&self) -> &Mb64bGroupMb0_64bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } - } - #[doc = "0x84 - Message Buffer 0 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_id(&self) -> &Mb32bGroupMb0_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } - } - #[doc = "0x84 - Message Buffer 0 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb0_16b_id(&self) -> &Mb16bGroupMb0_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } - } - #[doc = "0x84 - Message Buffer 0 ID Register"] - #[inline(always)] - pub const fn mb_group_id0(&self) -> &MbGroupId0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(132).cast() } - } - #[doc = "0x88 - Message Buffer 0 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word00(&self) -> &MbGroupWord00 { - unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } - } - #[doc = "0x88 - Message Buffer 0 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb0_8b_word0(&self) -> &Mb8bGroupMb0_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } - } - #[doc = "0x88 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word0(&self) -> &Mb64bGroupMb0_64bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } - } - #[doc = "0x88 - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word0(&self) -> &Mb32bGroupMb0_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } - } - #[doc = "0x88 - Message Buffer 0 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb0_16b_word0(&self) -> &Mb16bGroupMb0_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(136).cast() } - } - #[doc = "0x8c - Message Buffer 0 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word10(&self) -> &MbGroupWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } - } - #[doc = "0x8c - Message Buffer 0 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb0_8b_word1(&self) -> &Mb8bGroupMb0_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } - } - #[doc = "0x8c - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word1(&self) -> &Mb64bGroupMb0_64bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } - } - #[doc = "0x8c - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word1(&self) -> &Mb32bGroupMb0_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } - } - #[doc = "0x8c - Message Buffer 0 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb0_16b_word1(&self) -> &Mb16bGroupMb0_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(140).cast() } - } - #[doc = "0x90 - Message Buffer 1 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb1_8b_cs(&self) -> &Mb8bGroupMb1_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } - } - #[doc = "0x90 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word2(&self) -> &Mb64bGroupMb0_64bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } - } - #[doc = "0x90 - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word2(&self) -> &Mb32bGroupMb0_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } - } - #[doc = "0x90 - Message Buffer 0 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb0_16b_word2(&self) -> &Mb16bGroupMb0_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } - } - #[doc = "0x90 - Message Buffer 1 CS Register"] - #[inline(always)] - pub const fn mb_group_cs1(&self) -> &MbGroupCs1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(144).cast() } - } - #[doc = "0x94 - Message Buffer 1 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb1_8b_id(&self) -> &Mb8bGroupMb1_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } - } - #[doc = "0x94 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word3(&self) -> &Mb64bGroupMb0_64bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } - } - #[doc = "0x94 - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word3(&self) -> &Mb32bGroupMb0_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } - } - #[doc = "0x94 - Message Buffer 0 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb0_16b_word3(&self) -> &Mb16bGroupMb0_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } - } - #[doc = "0x94 - Message Buffer 1 ID Register"] - #[inline(always)] - pub const fn mb_group_id1(&self) -> &MbGroupId1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(148).cast() } - } - #[doc = "0x98 - Message Buffer 1 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word01(&self) -> &MbGroupWord01 { - unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } - } - #[doc = "0x98 - Message Buffer 1 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb1_8b_word0(&self) -> &Mb8bGroupMb1_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } - } - #[doc = "0x98 - Message Buffer 1 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb1_16b_cs(&self) -> &Mb16bGroupMb1_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } - } - #[doc = "0x98 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word4(&self) -> &Mb64bGroupMb0_64bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } - } - #[doc = "0x98 - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word4(&self) -> &Mb32bGroupMb0_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(152).cast() } - } - #[doc = "0x9c - Message Buffer 1 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word11(&self) -> &MbGroupWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } - } - #[doc = "0x9c - Message Buffer 1 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb1_8b_word1(&self) -> &Mb8bGroupMb1_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } - } - #[doc = "0x9c - Message Buffer 1 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb1_16b_id(&self) -> &Mb16bGroupMb1_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } - } - #[doc = "0x9c - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word5(&self) -> &Mb64bGroupMb0_64bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } - } - #[doc = "0x9c - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word5(&self) -> &Mb32bGroupMb0_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(156).cast() } - } - #[doc = "0xa0 - Message Buffer 2 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb2_8b_cs(&self) -> &Mb8bGroupMb2_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } - } - #[doc = "0xa0 - Message Buffer 1 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb1_16b_word0(&self) -> &Mb16bGroupMb1_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } - } - #[doc = "0xa0 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word6(&self) -> &Mb64bGroupMb0_64bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } - } - #[doc = "0xa0 - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word6(&self) -> &Mb32bGroupMb0_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } - } - #[doc = "0xa0 - Message Buffer 2 CS Register"] - #[inline(always)] - pub const fn mb_group_cs2(&self) -> &MbGroupCs2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(160).cast() } - } - #[doc = "0xa4 - Message Buffer 2 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb2_8b_id(&self) -> &Mb8bGroupMb2_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } - } - #[doc = "0xa4 - Message Buffer 1 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb1_16b_word1(&self) -> &Mb16bGroupMb1_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } - } - #[doc = "0xa4 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word7(&self) -> &Mb64bGroupMb0_64bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } - } - #[doc = "0xa4 - Message Buffer 0 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb0_32b_word7(&self) -> &Mb32bGroupMb0_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } - } - #[doc = "0xa4 - Message Buffer 2 ID Register"] - #[inline(always)] - pub const fn mb_group_id2(&self) -> &MbGroupId2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(164).cast() } - } - #[doc = "0xa8 - Message Buffer 2 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word02(&self) -> &MbGroupWord02 { - unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } - } - #[doc = "0xa8 - Message Buffer 2 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb2_8b_word0(&self) -> &Mb8bGroupMb2_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } - } - #[doc = "0xa8 - Message Buffer 1 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_cs(&self) -> &Mb32bGroupMb1_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } - } - #[doc = "0xa8 - Message Buffer 1 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb1_16b_word2(&self) -> &Mb16bGroupMb1_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } - } - #[doc = "0xa8 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word8(&self) -> &Mb64bGroupMb0_64bWord8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(168).cast() } - } - #[doc = "0xac - Message Buffer 2 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word12(&self) -> &MbGroupWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } - } - #[doc = "0xac - Message Buffer 2 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb2_8b_word1(&self) -> &Mb8bGroupMb2_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } - } - #[doc = "0xac - Message Buffer 1 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_id(&self) -> &Mb32bGroupMb1_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } - } - #[doc = "0xac - Message Buffer 1 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb1_16b_word3(&self) -> &Mb16bGroupMb1_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } - } - #[doc = "0xac - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word9(&self) -> &Mb64bGroupMb0_64bWord9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(172).cast() } - } - #[doc = "0xb0 - Message Buffer 3 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb3_8b_cs(&self) -> &Mb8bGroupMb3_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } - } - #[doc = "0xb0 - Message Buffer 2 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb2_16b_cs(&self) -> &Mb16bGroupMb2_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } - } - #[doc = "0xb0 - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word0(&self) -> &Mb32bGroupMb1_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } - } - #[doc = "0xb0 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word10(&self) -> &Mb64bGroupMb0_64bWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } - } - #[doc = "0xb0 - Message Buffer 3 CS Register"] - #[inline(always)] - pub const fn mb_group_cs3(&self) -> &MbGroupCs3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(176).cast() } - } - #[doc = "0xb4 - Message Buffer 3 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb3_8b_id(&self) -> &Mb8bGroupMb3_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } - } - #[doc = "0xb4 - Message Buffer 2 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb2_16b_id(&self) -> &Mb16bGroupMb2_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } - } - #[doc = "0xb4 - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word1(&self) -> &Mb32bGroupMb1_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } - } - #[doc = "0xb4 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word11(&self) -> &Mb64bGroupMb0_64bWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } - } - #[doc = "0xb4 - Message Buffer 3 ID Register"] - #[inline(always)] - pub const fn mb_group_id3(&self) -> &MbGroupId3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(180).cast() } - } - #[doc = "0xb8 - Message Buffer 3 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word03(&self) -> &MbGroupWord03 { - unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } - } - #[doc = "0xb8 - Message Buffer 3 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb3_8b_word0(&self) -> &Mb8bGroupMb3_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } - } - #[doc = "0xb8 - Message Buffer 2 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb2_16b_word0(&self) -> &Mb16bGroupMb2_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } - } - #[doc = "0xb8 - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word2(&self) -> &Mb32bGroupMb1_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } - } - #[doc = "0xb8 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word12(&self) -> &Mb64bGroupMb0_64bWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(184).cast() } - } - #[doc = "0xbc - Message Buffer 3 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word13(&self) -> &MbGroupWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } - } - #[doc = "0xbc - Message Buffer 3 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb3_8b_word1(&self) -> &Mb8bGroupMb3_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } - } - #[doc = "0xbc - Message Buffer 2 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb2_16b_word1(&self) -> &Mb16bGroupMb2_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } - } - #[doc = "0xbc - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word3(&self) -> &Mb32bGroupMb1_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } - } - #[doc = "0xbc - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word13(&self) -> &Mb64bGroupMb0_64bWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(188).cast() } - } - #[doc = "0xc0 - Message Buffer 4 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb4_8b_cs(&self) -> &Mb8bGroupMb4_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } - } - #[doc = "0xc0 - Message Buffer 2 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb2_16b_word2(&self) -> &Mb16bGroupMb2_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } - } - #[doc = "0xc0 - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word4(&self) -> &Mb32bGroupMb1_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } - } - #[doc = "0xc0 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word14(&self) -> &Mb64bGroupMb0_64bWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } - } - #[doc = "0xc0 - Message Buffer 4 CS Register"] - #[inline(always)] - pub const fn mb_group_cs4(&self) -> &MbGroupCs4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(192).cast() } - } - #[doc = "0xc4 - Message Buffer 4 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb4_8b_id(&self) -> &Mb8bGroupMb4_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } - } - #[doc = "0xc4 - Message Buffer 2 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb2_16b_word3(&self) -> &Mb16bGroupMb2_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } - } - #[doc = "0xc4 - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word5(&self) -> &Mb32bGroupMb1_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } - } - #[doc = "0xc4 - Message Buffer 0 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb0_64b_word15(&self) -> &Mb64bGroupMb0_64bWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } - } - #[doc = "0xc4 - Message Buffer 4 ID Register"] - #[inline(always)] - pub const fn mb_group_id4(&self) -> &MbGroupId4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(196).cast() } - } - #[doc = "0xc8 - Message Buffer 4 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word04(&self) -> &MbGroupWord04 { - unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } - } - #[doc = "0xc8 - Message Buffer 4 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb4_8b_word0(&self) -> &Mb8bGroupMb4_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } - } - #[doc = "0xc8 - Message Buffer 3 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb3_16b_cs(&self) -> &Mb16bGroupMb3_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } - } - #[doc = "0xc8 - Message Buffer 1 CS Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_cs(&self) -> &Mb64bGroupMb1_64bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } - } - #[doc = "0xc8 - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word6(&self) -> &Mb32bGroupMb1_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(200).cast() } - } - #[doc = "0xcc - Message Buffer 4 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word14(&self) -> &MbGroupWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } - } - #[doc = "0xcc - Message Buffer 4 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb4_8b_word1(&self) -> &Mb8bGroupMb4_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } - } - #[doc = "0xcc - Message Buffer 3 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb3_16b_id(&self) -> &Mb16bGroupMb3_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } - } - #[doc = "0xcc - Message Buffer 1 ID Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_id(&self) -> &Mb64bGroupMb1_64bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } - } - #[doc = "0xcc - Message Buffer 1 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb1_32b_word7(&self) -> &Mb32bGroupMb1_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } - } - #[doc = "0xd0 - Message Buffer 5 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb5_8b_cs(&self) -> &Mb8bGroupMb5_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } - } - #[doc = "0xd0 - Message Buffer 3 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb3_16b_word0(&self) -> &Mb16bGroupMb3_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } - } - #[doc = "0xd0 - Message Buffer 2 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_cs(&self) -> &Mb32bGroupMb2_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } - } - #[doc = "0xd0 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word0(&self) -> &Mb64bGroupMb1_64bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } - } - #[doc = "0xd0 - Message Buffer 5 CS Register"] - #[inline(always)] - pub const fn mb_group_cs5(&self) -> &MbGroupCs5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } - } - #[doc = "0xd4 - Message Buffer 5 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb5_8b_id(&self) -> &Mb8bGroupMb5_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } - } - #[doc = "0xd4 - Message Buffer 3 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb3_16b_word1(&self) -> &Mb16bGroupMb3_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } - } - #[doc = "0xd4 - Message Buffer 2 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_id(&self) -> &Mb32bGroupMb2_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } - } - #[doc = "0xd4 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word1(&self) -> &Mb64bGroupMb1_64bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } - } - #[doc = "0xd4 - Message Buffer 5 ID Register"] - #[inline(always)] - pub const fn mb_group_id5(&self) -> &MbGroupId5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(212).cast() } - } - #[doc = "0xd8 - Message Buffer 5 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word05(&self) -> &MbGroupWord05 { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xd8 - Message Buffer 5 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb5_8b_word0(&self) -> &Mb8bGroupMb5_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xd8 - Message Buffer 3 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb3_16b_word2(&self) -> &Mb16bGroupMb3_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xd8 - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word0(&self) -> &Mb32bGroupMb2_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xd8 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word2(&self) -> &Mb64bGroupMb1_64bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xdc - Message Buffer 5 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word15(&self) -> &MbGroupWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } - } - #[doc = "0xdc - Message Buffer 5 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb5_8b_word1(&self) -> &Mb8bGroupMb5_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } - } - #[doc = "0xdc - Message Buffer 3 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb3_16b_word3(&self) -> &Mb16bGroupMb3_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } - } - #[doc = "0xdc - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word1(&self) -> &Mb32bGroupMb2_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } - } - #[doc = "0xdc - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word3(&self) -> &Mb64bGroupMb1_64bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(220).cast() } - } - #[doc = "0xe0 - Message Buffer 6 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb6_8b_cs(&self) -> &Mb8bGroupMb6_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } - } - #[doc = "0xe0 - Message Buffer 4 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb4_16b_cs(&self) -> &Mb16bGroupMb4_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } - } - #[doc = "0xe0 - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word2(&self) -> &Mb32bGroupMb2_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } - } - #[doc = "0xe0 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word4(&self) -> &Mb64bGroupMb1_64bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } - } - #[doc = "0xe0 - Message Buffer 6 CS Register"] - #[inline(always)] - pub const fn mb_group_cs6(&self) -> &MbGroupCs6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(224).cast() } - } - #[doc = "0xe4 - Message Buffer 6 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb6_8b_id(&self) -> &Mb8bGroupMb6_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } - } - #[doc = "0xe4 - Message Buffer 4 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb4_16b_id(&self) -> &Mb16bGroupMb4_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } - } - #[doc = "0xe4 - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word3(&self) -> &Mb32bGroupMb2_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } - } - #[doc = "0xe4 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word5(&self) -> &Mb64bGroupMb1_64bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } - } - #[doc = "0xe4 - Message Buffer 6 ID Register"] - #[inline(always)] - pub const fn mb_group_id6(&self) -> &MbGroupId6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(228).cast() } - } - #[doc = "0xe8 - Message Buffer 6 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word06(&self) -> &MbGroupWord06 { - unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } - } - #[doc = "0xe8 - Message Buffer 6 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb6_8b_word0(&self) -> &Mb8bGroupMb6_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } - } - #[doc = "0xe8 - Message Buffer 4 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb4_16b_word0(&self) -> &Mb16bGroupMb4_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } - } - #[doc = "0xe8 - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word4(&self) -> &Mb32bGroupMb2_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } - } - #[doc = "0xe8 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word6(&self) -> &Mb64bGroupMb1_64bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(232).cast() } - } - #[doc = "0xec - Message Buffer 6 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word16(&self) -> &MbGroupWord16 { - unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } - } - #[doc = "0xec - Message Buffer 6 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb6_8b_word1(&self) -> &Mb8bGroupMb6_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } - } - #[doc = "0xec - Message Buffer 4 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb4_16b_word1(&self) -> &Mb16bGroupMb4_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } - } - #[doc = "0xec - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word5(&self) -> &Mb32bGroupMb2_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } - } - #[doc = "0xec - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word7(&self) -> &Mb64bGroupMb1_64bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(236).cast() } - } - #[doc = "0xf0 - Message Buffer 7 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb7_8b_cs(&self) -> &Mb8bGroupMb7_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } - } - #[doc = "0xf0 - Message Buffer 4 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb4_16b_word2(&self) -> &Mb16bGroupMb4_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } - } - #[doc = "0xf0 - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word6(&self) -> &Mb32bGroupMb2_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } - } - #[doc = "0xf0 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word8(&self) -> &Mb64bGroupMb1_64bWord8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } - } - #[doc = "0xf0 - Message Buffer 7 CS Register"] - #[inline(always)] - pub const fn mb_group_cs7(&self) -> &MbGroupCs7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(240).cast() } - } - #[doc = "0xf4 - Message Buffer 7 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb7_8b_id(&self) -> &Mb8bGroupMb7_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } - } - #[doc = "0xf4 - Message Buffer 4 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb4_16b_word3(&self) -> &Mb16bGroupMb4_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } - } - #[doc = "0xf4 - Message Buffer 2 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb2_32b_word7(&self) -> &Mb32bGroupMb2_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } - } - #[doc = "0xf4 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word9(&self) -> &Mb64bGroupMb1_64bWord9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } - } - #[doc = "0xf4 - Message Buffer 7 ID Register"] - #[inline(always)] - pub const fn mb_group_id7(&self) -> &MbGroupId7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(244).cast() } - } - #[doc = "0xf8 - Message Buffer 7 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word07(&self) -> &MbGroupWord07 { - unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } - } - #[doc = "0xf8 - Message Buffer 7 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb7_8b_word0(&self) -> &Mb8bGroupMb7_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } - } - #[doc = "0xf8 - Message Buffer 5 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb5_16b_cs(&self) -> &Mb16bGroupMb5_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } - } - #[doc = "0xf8 - Message Buffer 3 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_cs(&self) -> &Mb32bGroupMb3_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } - } - #[doc = "0xf8 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word10(&self) -> &Mb64bGroupMb1_64bWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(248).cast() } - } - #[doc = "0xfc - Message Buffer 7 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word17(&self) -> &MbGroupWord17 { - unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } - } - #[doc = "0xfc - Message Buffer 7 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb7_8b_word1(&self) -> &Mb8bGroupMb7_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } - } - #[doc = "0xfc - Message Buffer 5 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb5_16b_id(&self) -> &Mb16bGroupMb5_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } - } - #[doc = "0xfc - Message Buffer 3 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_id(&self) -> &Mb32bGroupMb3_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } - } - #[doc = "0xfc - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word11(&self) -> &Mb64bGroupMb1_64bWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(252).cast() } - } - #[doc = "0x100 - Message Buffer 8 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb8_8b_cs(&self) -> &Mb8bGroupMb8_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } - } - #[doc = "0x100 - Message Buffer 5 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb5_16b_word0(&self) -> &Mb16bGroupMb5_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } - } - #[doc = "0x100 - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word0(&self) -> &Mb32bGroupMb3_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } - } - #[doc = "0x100 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word12(&self) -> &Mb64bGroupMb1_64bWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } - } - #[doc = "0x100 - Message Buffer 8 CS Register"] - #[inline(always)] - pub const fn mb_group_cs8(&self) -> &MbGroupCs8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(256).cast() } - } - #[doc = "0x104 - Message Buffer 8 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb8_8b_id(&self) -> &Mb8bGroupMb8_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } - } - #[doc = "0x104 - Message Buffer 5 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb5_16b_word1(&self) -> &Mb16bGroupMb5_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } - } - #[doc = "0x104 - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word1(&self) -> &Mb32bGroupMb3_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } - } - #[doc = "0x104 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word13(&self) -> &Mb64bGroupMb1_64bWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } - } - #[doc = "0x104 - Message Buffer 8 ID Register"] - #[inline(always)] - pub const fn mb_group_id8(&self) -> &MbGroupId8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(260).cast() } - } - #[doc = "0x108 - Message Buffer 8 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word08(&self) -> &MbGroupWord08 { - unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } - } - #[doc = "0x108 - Message Buffer 8 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb8_8b_word0(&self) -> &Mb8bGroupMb8_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } - } - #[doc = "0x108 - Message Buffer 5 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb5_16b_word2(&self) -> &Mb16bGroupMb5_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } - } - #[doc = "0x108 - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word2(&self) -> &Mb32bGroupMb3_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } - } - #[doc = "0x108 - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word14(&self) -> &Mb64bGroupMb1_64bWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(264).cast() } - } - #[doc = "0x10c - Message Buffer 8 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word18(&self) -> &MbGroupWord18 { - unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } - } - #[doc = "0x10c - Message Buffer 8 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb8_8b_word1(&self) -> &Mb8bGroupMb8_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } - } - #[doc = "0x10c - Message Buffer 5 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb5_16b_word3(&self) -> &Mb16bGroupMb5_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } - } - #[doc = "0x10c - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word3(&self) -> &Mb32bGroupMb3_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } - } - #[doc = "0x10c - Message Buffer 1 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb1_64b_word15(&self) -> &Mb64bGroupMb1_64bWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(268).cast() } - } - #[doc = "0x110 - Message Buffer 9 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb9_8b_cs(&self) -> &Mb8bGroupMb9_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } - } - #[doc = "0x110 - Message Buffer 6 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb6_16b_cs(&self) -> &Mb16bGroupMb6_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } - } - #[doc = "0x110 - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word4(&self) -> &Mb32bGroupMb3_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } - } - #[doc = "0x110 - Message Buffer 2 CS Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_cs(&self) -> &Mb64bGroupMb2_64bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } - } - #[doc = "0x110 - Message Buffer 9 CS Register"] - #[inline(always)] - pub const fn mb_group_cs9(&self) -> &MbGroupCs9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(272).cast() } - } - #[doc = "0x114 - Message Buffer 9 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb9_8b_id(&self) -> &Mb8bGroupMb9_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } - } - #[doc = "0x114 - Message Buffer 6 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb6_16b_id(&self) -> &Mb16bGroupMb6_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } - } - #[doc = "0x114 - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word5(&self) -> &Mb32bGroupMb3_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } - } - #[doc = "0x114 - Message Buffer 2 ID Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_id(&self) -> &Mb64bGroupMb2_64bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } - } - #[doc = "0x114 - Message Buffer 9 ID Register"] - #[inline(always)] - pub const fn mb_group_id9(&self) -> &MbGroupId9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(276).cast() } - } - #[doc = "0x118 - Message Buffer 9 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word09(&self) -> &MbGroupWord09 { - unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } - } - #[doc = "0x118 - Message Buffer 9 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb9_8b_word0(&self) -> &Mb8bGroupMb9_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } - } - #[doc = "0x118 - Message Buffer 6 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb6_16b_word0(&self) -> &Mb16bGroupMb6_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } - } - #[doc = "0x118 - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word6(&self) -> &Mb32bGroupMb3_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } - } - #[doc = "0x118 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word0(&self) -> &Mb64bGroupMb2_64bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(280).cast() } - } - #[doc = "0x11c - Message Buffer 9 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word19(&self) -> &MbGroupWord19 { - unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } - } - #[doc = "0x11c - Message Buffer 9 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb9_8b_word1(&self) -> &Mb8bGroupMb9_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } - } - #[doc = "0x11c - Message Buffer 6 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb6_16b_word1(&self) -> &Mb16bGroupMb6_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } - } - #[doc = "0x11c - Message Buffer 3 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb3_32b_word7(&self) -> &Mb32bGroupMb3_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } - } - #[doc = "0x11c - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word1(&self) -> &Mb64bGroupMb2_64bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(284).cast() } - } - #[doc = "0x120 - Message Buffer 6 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb6_16b_word2(&self) -> &Mb16bGroupMb6_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } - } - #[doc = "0x120 - Message Buffer 4 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_cs(&self) -> &Mb32bGroupMb4_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } - } - #[doc = "0x120 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word2(&self) -> &Mb64bGroupMb2_64bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } - } - #[doc = "0x120 - Message Buffer 10 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb10_8b_cs(&self) -> &Mb8bGroupMb10_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } - } - #[doc = "0x120 - Message Buffer 10 CS Register"] - #[inline(always)] - pub const fn mb_group_cs10(&self) -> &MbGroupCs10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(288).cast() } - } - #[doc = "0x124 - Message Buffer 6 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb6_16b_word3(&self) -> &Mb16bGroupMb6_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } - } - #[doc = "0x124 - Message Buffer 4 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_id(&self) -> &Mb32bGroupMb4_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } - } - #[doc = "0x124 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word3(&self) -> &Mb64bGroupMb2_64bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } - } - #[doc = "0x124 - Message Buffer 10 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb10_8b_id(&self) -> &Mb8bGroupMb10_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } - } - #[doc = "0x124 - Message Buffer 10 ID Register"] - #[inline(always)] - pub const fn mb_group_id10(&self) -> &MbGroupId10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(292).cast() } - } - #[doc = "0x128 - Message Buffer 10 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word010(&self) -> &MbGroupWord010 { - unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } - } - #[doc = "0x128 - Message Buffer 7 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb7_16b_cs(&self) -> &Mb16bGroupMb7_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } - } - #[doc = "0x128 - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word0(&self) -> &Mb32bGroupMb4_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } - } - #[doc = "0x128 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word4(&self) -> &Mb64bGroupMb2_64bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } - } - #[doc = "0x128 - Message Buffer 10 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb10_8b_word0(&self) -> &Mb8bGroupMb10_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(296).cast() } - } - #[doc = "0x12c - Message Buffer 10 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word110(&self) -> &MbGroupWord110 { - unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } - } - #[doc = "0x12c - Message Buffer 7 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb7_16b_id(&self) -> &Mb16bGroupMb7_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } - } - #[doc = "0x12c - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word1(&self) -> &Mb32bGroupMb4_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } - } - #[doc = "0x12c - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word5(&self) -> &Mb64bGroupMb2_64bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } - } - #[doc = "0x12c - Message Buffer 10 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb10_8b_word1(&self) -> &Mb8bGroupMb10_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(300).cast() } - } - #[doc = "0x130 - Message Buffer 7 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb7_16b_word0(&self) -> &Mb16bGroupMb7_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } - } - #[doc = "0x130 - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word2(&self) -> &Mb32bGroupMb4_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } - } - #[doc = "0x130 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word6(&self) -> &Mb64bGroupMb2_64bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } - } - #[doc = "0x130 - Message Buffer 11 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb11_8b_cs(&self) -> &Mb8bGroupMb11_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } - } - #[doc = "0x130 - Message Buffer 11 CS Register"] - #[inline(always)] - pub const fn mb_group_cs11(&self) -> &MbGroupCs11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(304).cast() } - } - #[doc = "0x134 - Message Buffer 7 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb7_16b_word1(&self) -> &Mb16bGroupMb7_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } - } - #[doc = "0x134 - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word3(&self) -> &Mb32bGroupMb4_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } - } - #[doc = "0x134 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word7(&self) -> &Mb64bGroupMb2_64bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } - } - #[doc = "0x134 - Message Buffer 11 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb11_8b_id(&self) -> &Mb8bGroupMb11_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } - } - #[doc = "0x134 - Message Buffer 11 ID Register"] - #[inline(always)] - pub const fn mb_group_id11(&self) -> &MbGroupId11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(308).cast() } - } - #[doc = "0x138 - Message Buffer 11 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word011(&self) -> &MbGroupWord011 { - unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } - } - #[doc = "0x138 - Message Buffer 7 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb7_16b_word2(&self) -> &Mb16bGroupMb7_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } - } - #[doc = "0x138 - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word4(&self) -> &Mb32bGroupMb4_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } - } - #[doc = "0x138 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word8(&self) -> &Mb64bGroupMb2_64bWord8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } - } - #[doc = "0x138 - Message Buffer 11 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb11_8b_word0(&self) -> &Mb8bGroupMb11_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(312).cast() } - } - #[doc = "0x13c - Message Buffer 11 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word111(&self) -> &MbGroupWord111 { - unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } - } - #[doc = "0x13c - Message Buffer 7 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb7_16b_word3(&self) -> &Mb16bGroupMb7_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } - } - #[doc = "0x13c - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word5(&self) -> &Mb32bGroupMb4_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } - } - #[doc = "0x13c - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word9(&self) -> &Mb64bGroupMb2_64bWord9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } - } - #[doc = "0x13c - Message Buffer 11 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb11_8b_word1(&self) -> &Mb8bGroupMb11_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(316).cast() } - } - #[doc = "0x140 - Message Buffer 8 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb8_16b_cs(&self) -> &Mb16bGroupMb8_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } - } - #[doc = "0x140 - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word6(&self) -> &Mb32bGroupMb4_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } - } - #[doc = "0x140 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word10(&self) -> &Mb64bGroupMb2_64bWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } - } - #[doc = "0x140 - Message Buffer 12 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb12_8b_cs(&self) -> &Mb8bGroupMb12_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } - } - #[doc = "0x140 - Message Buffer 12 CS Register"] - #[inline(always)] - pub const fn mb_group_cs12(&self) -> &MbGroupCs12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(320).cast() } - } - #[doc = "0x144 - Message Buffer 8 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb8_16b_id(&self) -> &Mb16bGroupMb8_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } - } - #[doc = "0x144 - Message Buffer 4 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb4_32b_word7(&self) -> &Mb32bGroupMb4_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } - } - #[doc = "0x144 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word11(&self) -> &Mb64bGroupMb2_64bWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } - } - #[doc = "0x144 - Message Buffer 12 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb12_8b_id(&self) -> &Mb8bGroupMb12_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } - } - #[doc = "0x144 - Message Buffer 12 ID Register"] - #[inline(always)] - pub const fn mb_group_id12(&self) -> &MbGroupId12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(324).cast() } - } - #[doc = "0x148 - Message Buffer 12 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word012(&self) -> &MbGroupWord012 { - unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } - } - #[doc = "0x148 - Message Buffer 8 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb8_16b_word0(&self) -> &Mb16bGroupMb8_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } - } - #[doc = "0x148 - Message Buffer 5 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_cs(&self) -> &Mb32bGroupMb5_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } - } - #[doc = "0x148 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word12(&self) -> &Mb64bGroupMb2_64bWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } - } - #[doc = "0x148 - Message Buffer 12 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb12_8b_word0(&self) -> &Mb8bGroupMb12_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(328).cast() } - } - #[doc = "0x14c - Message Buffer 12 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word112(&self) -> &MbGroupWord112 { - unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } - } - #[doc = "0x14c - Message Buffer 8 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb8_16b_word1(&self) -> &Mb16bGroupMb8_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } - } - #[doc = "0x14c - Message Buffer 5 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_id(&self) -> &Mb32bGroupMb5_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } - } - #[doc = "0x14c - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word13(&self) -> &Mb64bGroupMb2_64bWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } - } - #[doc = "0x14c - Message Buffer 12 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb12_8b_word1(&self) -> &Mb8bGroupMb12_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(332).cast() } - } - #[doc = "0x150 - Message Buffer 8 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb8_16b_word2(&self) -> &Mb16bGroupMb8_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } - } - #[doc = "0x150 - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word0(&self) -> &Mb32bGroupMb5_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } - } - #[doc = "0x150 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word14(&self) -> &Mb64bGroupMb2_64bWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } - } - #[doc = "0x150 - Message Buffer 13 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb13_8b_cs(&self) -> &Mb8bGroupMb13_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } - } - #[doc = "0x150 - Message Buffer 13 CS Register"] - #[inline(always)] - pub const fn mb_group_cs13(&self) -> &MbGroupCs13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(336).cast() } - } - #[doc = "0x154 - Message Buffer 8 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb8_16b_word3(&self) -> &Mb16bGroupMb8_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } - } - #[doc = "0x154 - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word1(&self) -> &Mb32bGroupMb5_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } - } - #[doc = "0x154 - Message Buffer 2 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb2_64b_word15(&self) -> &Mb64bGroupMb2_64bWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } - } - #[doc = "0x154 - Message Buffer 13 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb13_8b_id(&self) -> &Mb8bGroupMb13_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } - } - #[doc = "0x154 - Message Buffer 13 ID Register"] - #[inline(always)] - pub const fn mb_group_id13(&self) -> &MbGroupId13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(340).cast() } - } - #[doc = "0x158 - Message Buffer 13 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word013(&self) -> &MbGroupWord013 { - unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } - } - #[doc = "0x158 - Message Buffer 9 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb9_16b_cs(&self) -> &Mb16bGroupMb9_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } - } - #[doc = "0x158 - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word2(&self) -> &Mb32bGroupMb5_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } - } - #[doc = "0x158 - Message Buffer 3 CS Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_cs(&self) -> &Mb64bGroupMb3_64bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } - } - #[doc = "0x158 - Message Buffer 13 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb13_8b_word0(&self) -> &Mb8bGroupMb13_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(344).cast() } - } - #[doc = "0x15c - Message Buffer 13 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word113(&self) -> &MbGroupWord113 { - unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } - } - #[doc = "0x15c - Message Buffer 9 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb9_16b_id(&self) -> &Mb16bGroupMb9_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } - } - #[doc = "0x15c - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word3(&self) -> &Mb32bGroupMb5_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } - } - #[doc = "0x15c - Message Buffer 3 ID Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_id(&self) -> &Mb64bGroupMb3_64bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } - } - #[doc = "0x15c - Message Buffer 13 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb13_8b_word1(&self) -> &Mb8bGroupMb13_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(348).cast() } - } - #[doc = "0x160 - Message Buffer 9 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb9_16b_word0(&self) -> &Mb16bGroupMb9_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } - } - #[doc = "0x160 - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word4(&self) -> &Mb32bGroupMb5_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } - } - #[doc = "0x160 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word0(&self) -> &Mb64bGroupMb3_64bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } - } - #[doc = "0x160 - Message Buffer 14 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb14_8b_cs(&self) -> &Mb8bGroupMb14_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } - } - #[doc = "0x160 - Message Buffer 14 CS Register"] - #[inline(always)] - pub const fn mb_group_cs14(&self) -> &MbGroupCs14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(352).cast() } - } - #[doc = "0x164 - Message Buffer 9 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb9_16b_word1(&self) -> &Mb16bGroupMb9_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } - } - #[doc = "0x164 - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word5(&self) -> &Mb32bGroupMb5_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } - } - #[doc = "0x164 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word1(&self) -> &Mb64bGroupMb3_64bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } - } - #[doc = "0x164 - Message Buffer 14 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb14_8b_id(&self) -> &Mb8bGroupMb14_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } - } - #[doc = "0x164 - Message Buffer 14 ID Register"] - #[inline(always)] - pub const fn mb_group_id14(&self) -> &MbGroupId14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(356).cast() } - } - #[doc = "0x168 - Message Buffer 14 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word014(&self) -> &MbGroupWord014 { - unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } - } - #[doc = "0x168 - Message Buffer 9 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb9_16b_word2(&self) -> &Mb16bGroupMb9_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } - } - #[doc = "0x168 - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word6(&self) -> &Mb32bGroupMb5_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } - } - #[doc = "0x168 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word2(&self) -> &Mb64bGroupMb3_64bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } - } - #[doc = "0x168 - Message Buffer 14 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb14_8b_word0(&self) -> &Mb8bGroupMb14_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(360).cast() } - } - #[doc = "0x16c - Message Buffer 14 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word114(&self) -> &MbGroupWord114 { - unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } - } - #[doc = "0x16c - Message Buffer 9 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb9_16b_word3(&self) -> &Mb16bGroupMb9_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } - } - #[doc = "0x16c - Message Buffer 5 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb5_32b_word7(&self) -> &Mb32bGroupMb5_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } - } - #[doc = "0x16c - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word3(&self) -> &Mb64bGroupMb3_64bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } - } - #[doc = "0x16c - Message Buffer 14 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb14_8b_word1(&self) -> &Mb8bGroupMb14_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(364).cast() } - } - #[doc = "0x170 - Message Buffer 6 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_cs(&self) -> &Mb32bGroupMb6_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } - } - #[doc = "0x170 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word4(&self) -> &Mb64bGroupMb3_64bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } - } - #[doc = "0x170 - Message Buffer 15 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb15_8b_cs(&self) -> &Mb8bGroupMb15_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } - } - #[doc = "0x170 - Message Buffer 10 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb10_16b_cs(&self) -> &Mb16bGroupMb10_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } - } - #[doc = "0x170 - Message Buffer 15 CS Register"] - #[inline(always)] - pub const fn mb_group_cs15(&self) -> &MbGroupCs15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(368).cast() } - } - #[doc = "0x174 - Message Buffer 6 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_id(&self) -> &Mb32bGroupMb6_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } - } - #[doc = "0x174 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word5(&self) -> &Mb64bGroupMb3_64bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } - } - #[doc = "0x174 - Message Buffer 15 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb15_8b_id(&self) -> &Mb8bGroupMb15_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } - } - #[doc = "0x174 - Message Buffer 10 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb10_16b_id(&self) -> &Mb16bGroupMb10_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } - } - #[doc = "0x174 - Message Buffer 15 ID Register"] - #[inline(always)] - pub const fn mb_group_id15(&self) -> &MbGroupId15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(372).cast() } - } - #[doc = "0x178 - Message Buffer 15 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word015(&self) -> &MbGroupWord015 { - unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } - } - #[doc = "0x178 - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word0(&self) -> &Mb32bGroupMb6_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } - } - #[doc = "0x178 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word6(&self) -> &Mb64bGroupMb3_64bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } - } - #[doc = "0x178 - Message Buffer 15 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb15_8b_word0(&self) -> &Mb8bGroupMb15_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } - } - #[doc = "0x178 - Message Buffer 10 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb10_16b_word0(&self) -> &Mb16bGroupMb10_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(376).cast() } - } - #[doc = "0x17c - Message Buffer 15 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word115(&self) -> &MbGroupWord115 { - unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } - } - #[doc = "0x17c - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word1(&self) -> &Mb32bGroupMb6_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } - } - #[doc = "0x17c - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word7(&self) -> &Mb64bGroupMb3_64bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } - } - #[doc = "0x17c - Message Buffer 15 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb15_8b_word1(&self) -> &Mb8bGroupMb15_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } - } - #[doc = "0x17c - Message Buffer 10 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb10_16b_word1(&self) -> &Mb16bGroupMb10_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(380).cast() } - } - #[doc = "0x180 - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word2(&self) -> &Mb32bGroupMb6_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } - } - #[doc = "0x180 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word8(&self) -> &Mb64bGroupMb3_64bWord8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } - } - #[doc = "0x180 - Message Buffer 16 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb16_8b_cs(&self) -> &Mb8bGroupMb16_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } - } - #[doc = "0x180 - Message Buffer 10 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb10_16b_word2(&self) -> &Mb16bGroupMb10_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } - } - #[doc = "0x180 - Message Buffer 16 CS Register"] - #[inline(always)] - pub const fn mb_group_cs16(&self) -> &MbGroupCs16 { - unsafe { &*core::ptr::from_ref(self).cast::().add(384).cast() } - } - #[doc = "0x184 - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word3(&self) -> &Mb32bGroupMb6_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } - } - #[doc = "0x184 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word9(&self) -> &Mb64bGroupMb3_64bWord9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } - } - #[doc = "0x184 - Message Buffer 16 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb16_8b_id(&self) -> &Mb8bGroupMb16_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } - } - #[doc = "0x184 - Message Buffer 10 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb10_16b_word3(&self) -> &Mb16bGroupMb10_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } - } - #[doc = "0x184 - Message Buffer 16 ID Register"] - #[inline(always)] - pub const fn mb_group_id16(&self) -> &MbGroupId16 { - unsafe { &*core::ptr::from_ref(self).cast::().add(388).cast() } - } - #[doc = "0x188 - Message Buffer 16 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word016(&self) -> &MbGroupWord016 { - unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } - } - #[doc = "0x188 - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word4(&self) -> &Mb32bGroupMb6_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } - } - #[doc = "0x188 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word10(&self) -> &Mb64bGroupMb3_64bWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } - } - #[doc = "0x188 - Message Buffer 16 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb16_8b_word0(&self) -> &Mb8bGroupMb16_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } - } - #[doc = "0x188 - Message Buffer 11 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb11_16b_cs(&self) -> &Mb16bGroupMb11_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(392).cast() } - } - #[doc = "0x18c - Message Buffer 16 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word116(&self) -> &MbGroupWord116 { - unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } - } - #[doc = "0x18c - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word5(&self) -> &Mb32bGroupMb6_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } - } - #[doc = "0x18c - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word11(&self) -> &Mb64bGroupMb3_64bWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } - } - #[doc = "0x18c - Message Buffer 16 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb16_8b_word1(&self) -> &Mb8bGroupMb16_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } - } - #[doc = "0x18c - Message Buffer 11 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb11_16b_id(&self) -> &Mb16bGroupMb11_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(396).cast() } - } - #[doc = "0x190 - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word6(&self) -> &Mb32bGroupMb6_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } - } - #[doc = "0x190 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word12(&self) -> &Mb64bGroupMb3_64bWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } - } - #[doc = "0x190 - Message Buffer 17 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb17_8b_cs(&self) -> &Mb8bGroupMb17_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } - } - #[doc = "0x190 - Message Buffer 11 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb11_16b_word0(&self) -> &Mb16bGroupMb11_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } - } - #[doc = "0x190 - Message Buffer 17 CS Register"] - #[inline(always)] - pub const fn mb_group_cs17(&self) -> &MbGroupCs17 { - unsafe { &*core::ptr::from_ref(self).cast::().add(400).cast() } - } - #[doc = "0x194 - Message Buffer 6 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb6_32b_word7(&self) -> &Mb32bGroupMb6_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } - } - #[doc = "0x194 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word13(&self) -> &Mb64bGroupMb3_64bWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } - } - #[doc = "0x194 - Message Buffer 17 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb17_8b_id(&self) -> &Mb8bGroupMb17_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } - } - #[doc = "0x194 - Message Buffer 11 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb11_16b_word1(&self) -> &Mb16bGroupMb11_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } - } - #[doc = "0x194 - Message Buffer 17 ID Register"] - #[inline(always)] - pub const fn mb_group_id17(&self) -> &MbGroupId17 { - unsafe { &*core::ptr::from_ref(self).cast::().add(404).cast() } - } - #[doc = "0x198 - Message Buffer 17 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word017(&self) -> &MbGroupWord017 { - unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } - } - #[doc = "0x198 - Message Buffer 7 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_cs(&self) -> &Mb32bGroupMb7_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } - } - #[doc = "0x198 - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word14(&self) -> &Mb64bGroupMb3_64bWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } - } - #[doc = "0x198 - Message Buffer 17 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb17_8b_word0(&self) -> &Mb8bGroupMb17_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } - } - #[doc = "0x198 - Message Buffer 11 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb11_16b_word2(&self) -> &Mb16bGroupMb11_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(408).cast() } - } - #[doc = "0x19c - Message Buffer 17 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word117(&self) -> &MbGroupWord117 { - unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } - } - #[doc = "0x19c - Message Buffer 7 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_id(&self) -> &Mb32bGroupMb7_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } - } - #[doc = "0x19c - Message Buffer 3 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb3_64b_word15(&self) -> &Mb64bGroupMb3_64bWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } - } - #[doc = "0x19c - Message Buffer 17 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb17_8b_word1(&self) -> &Mb8bGroupMb17_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } - } - #[doc = "0x19c - Message Buffer 11 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb11_16b_word3(&self) -> &Mb16bGroupMb11_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(412).cast() } - } - #[doc = "0x1a0 - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word0(&self) -> &Mb32bGroupMb7_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } - } - #[doc = "0x1a0 - Message Buffer 4 CS Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_cs(&self) -> &Mb64bGroupMb4_64bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } - } - #[doc = "0x1a0 - Message Buffer 18 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb18_8b_cs(&self) -> &Mb8bGroupMb18_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } - } - #[doc = "0x1a0 - Message Buffer 12 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb12_16b_cs(&self) -> &Mb16bGroupMb12_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } - } - #[doc = "0x1a0 - Message Buffer 18 CS Register"] - #[inline(always)] - pub const fn mb_group_cs18(&self) -> &MbGroupCs18 { - unsafe { &*core::ptr::from_ref(self).cast::().add(416).cast() } - } - #[doc = "0x1a4 - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word1(&self) -> &Mb32bGroupMb7_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } - } - #[doc = "0x1a4 - Message Buffer 4 ID Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_id(&self) -> &Mb64bGroupMb4_64bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } - } - #[doc = "0x1a4 - Message Buffer 18 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb18_8b_id(&self) -> &Mb8bGroupMb18_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } - } - #[doc = "0x1a4 - Message Buffer 12 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb12_16b_id(&self) -> &Mb16bGroupMb12_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } - } - #[doc = "0x1a4 - Message Buffer 18 ID Register"] - #[inline(always)] - pub const fn mb_group_id18(&self) -> &MbGroupId18 { - unsafe { &*core::ptr::from_ref(self).cast::().add(420).cast() } - } - #[doc = "0x1a8 - Message Buffer 18 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word018(&self) -> &MbGroupWord018 { - unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } - } - #[doc = "0x1a8 - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word2(&self) -> &Mb32bGroupMb7_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } - } - #[doc = "0x1a8 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word0(&self) -> &Mb64bGroupMb4_64bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } - } - #[doc = "0x1a8 - Message Buffer 18 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb18_8b_word0(&self) -> &Mb8bGroupMb18_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } - } - #[doc = "0x1a8 - Message Buffer 12 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb12_16b_word0(&self) -> &Mb16bGroupMb12_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(424).cast() } - } - #[doc = "0x1ac - Message Buffer 18 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word118(&self) -> &MbGroupWord118 { - unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } - } - #[doc = "0x1ac - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word3(&self) -> &Mb32bGroupMb7_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } - } - #[doc = "0x1ac - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word1(&self) -> &Mb64bGroupMb4_64bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } - } - #[doc = "0x1ac - Message Buffer 18 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb18_8b_word1(&self) -> &Mb8bGroupMb18_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } - } - #[doc = "0x1ac - Message Buffer 12 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb12_16b_word1(&self) -> &Mb16bGroupMb12_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(428).cast() } - } - #[doc = "0x1b0 - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word4(&self) -> &Mb32bGroupMb7_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } - } - #[doc = "0x1b0 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word2(&self) -> &Mb64bGroupMb4_64bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } - } - #[doc = "0x1b0 - Message Buffer 19 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb19_8b_cs(&self) -> &Mb8bGroupMb19_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } - } - #[doc = "0x1b0 - Message Buffer 12 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb12_16b_word2(&self) -> &Mb16bGroupMb12_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } - } - #[doc = "0x1b0 - Message Buffer 19 CS Register"] - #[inline(always)] - pub const fn mb_group_cs19(&self) -> &MbGroupCs19 { - unsafe { &*core::ptr::from_ref(self).cast::().add(432).cast() } - } - #[doc = "0x1b4 - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word5(&self) -> &Mb32bGroupMb7_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } - } - #[doc = "0x1b4 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word3(&self) -> &Mb64bGroupMb4_64bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } - } - #[doc = "0x1b4 - Message Buffer 19 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb19_8b_id(&self) -> &Mb8bGroupMb19_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } - } - #[doc = "0x1b4 - Message Buffer 12 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb12_16b_word3(&self) -> &Mb16bGroupMb12_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } - } - #[doc = "0x1b4 - Message Buffer 19 ID Register"] - #[inline(always)] - pub const fn mb_group_id19(&self) -> &MbGroupId19 { - unsafe { &*core::ptr::from_ref(self).cast::().add(436).cast() } - } - #[doc = "0x1b8 - Message Buffer 19 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word019(&self) -> &MbGroupWord019 { - unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } - } - #[doc = "0x1b8 - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word6(&self) -> &Mb32bGroupMb7_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } - } - #[doc = "0x1b8 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word4(&self) -> &Mb64bGroupMb4_64bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } - } - #[doc = "0x1b8 - Message Buffer 19 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb19_8b_word0(&self) -> &Mb8bGroupMb19_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } - } - #[doc = "0x1b8 - Message Buffer 13 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb13_16b_cs(&self) -> &Mb16bGroupMb13_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(440).cast() } - } - #[doc = "0x1bc - Message Buffer 19 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word119(&self) -> &MbGroupWord119 { - unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } - } - #[doc = "0x1bc - Message Buffer 7 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb7_32b_word7(&self) -> &Mb32bGroupMb7_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } - } - #[doc = "0x1bc - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word5(&self) -> &Mb64bGroupMb4_64bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } - } - #[doc = "0x1bc - Message Buffer 19 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb19_8b_word1(&self) -> &Mb8bGroupMb19_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } - } - #[doc = "0x1bc - Message Buffer 13 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb13_16b_id(&self) -> &Mb16bGroupMb13_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(444).cast() } - } - #[doc = "0x1c0 - Message Buffer 8 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_cs(&self) -> &Mb32bGroupMb8_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } - } - #[doc = "0x1c0 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word6(&self) -> &Mb64bGroupMb4_64bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } - } - #[doc = "0x1c0 - Message Buffer 20 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb20_8b_cs(&self) -> &Mb8bGroupMb20_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } - } - #[doc = "0x1c0 - Message Buffer 13 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb13_16b_word0(&self) -> &Mb16bGroupMb13_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } - } - #[doc = "0x1c0 - Message Buffer 20 CS Register"] - #[inline(always)] - pub const fn mb_group_cs20(&self) -> &MbGroupCs20 { - unsafe { &*core::ptr::from_ref(self).cast::().add(448).cast() } - } - #[doc = "0x1c4 - Message Buffer 8 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_id(&self) -> &Mb32bGroupMb8_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } - } - #[doc = "0x1c4 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word7(&self) -> &Mb64bGroupMb4_64bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } - } - #[doc = "0x1c4 - Message Buffer 20 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb20_8b_id(&self) -> &Mb8bGroupMb20_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } - } - #[doc = "0x1c4 - Message Buffer 13 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb13_16b_word1(&self) -> &Mb16bGroupMb13_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } - } - #[doc = "0x1c4 - Message Buffer 20 ID Register"] - #[inline(always)] - pub const fn mb_group_id20(&self) -> &MbGroupId20 { - unsafe { &*core::ptr::from_ref(self).cast::().add(452).cast() } - } - #[doc = "0x1c8 - Message Buffer 20 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word020(&self) -> &MbGroupWord020 { - unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } - } - #[doc = "0x1c8 - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word0(&self) -> &Mb32bGroupMb8_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } - } - #[doc = "0x1c8 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word8(&self) -> &Mb64bGroupMb4_64bWord8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } - } - #[doc = "0x1c8 - Message Buffer 20 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb20_8b_word0(&self) -> &Mb8bGroupMb20_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } - } - #[doc = "0x1c8 - Message Buffer 13 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb13_16b_word2(&self) -> &Mb16bGroupMb13_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(456).cast() } - } - #[doc = "0x1cc - Message Buffer 20 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word120(&self) -> &MbGroupWord120 { - unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } - } - #[doc = "0x1cc - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word1(&self) -> &Mb32bGroupMb8_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } - } - #[doc = "0x1cc - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word9(&self) -> &Mb64bGroupMb4_64bWord9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } - } - #[doc = "0x1cc - Message Buffer 20 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb20_8b_word1(&self) -> &Mb8bGroupMb20_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } - } - #[doc = "0x1cc - Message Buffer 13 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb13_16b_word3(&self) -> &Mb16bGroupMb13_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(460).cast() } - } - #[doc = "0x1d0 - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word2(&self) -> &Mb32bGroupMb8_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } - } - #[doc = "0x1d0 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word10(&self) -> &Mb64bGroupMb4_64bWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } - } - #[doc = "0x1d0 - Message Buffer 21 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb21_8b_cs(&self) -> &Mb8bGroupMb21_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } - } - #[doc = "0x1d0 - Message Buffer 14 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb14_16b_cs(&self) -> &Mb16bGroupMb14_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } - } - #[doc = "0x1d0 - Message Buffer 21 CS Register"] - #[inline(always)] - pub const fn mb_group_cs21(&self) -> &MbGroupCs21 { - unsafe { &*core::ptr::from_ref(self).cast::().add(464).cast() } - } - #[doc = "0x1d4 - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word3(&self) -> &Mb32bGroupMb8_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } - } - #[doc = "0x1d4 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word11(&self) -> &Mb64bGroupMb4_64bWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } - } - #[doc = "0x1d4 - Message Buffer 21 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb21_8b_id(&self) -> &Mb8bGroupMb21_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } - } - #[doc = "0x1d4 - Message Buffer 14 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb14_16b_id(&self) -> &Mb16bGroupMb14_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } - } - #[doc = "0x1d4 - Message Buffer 21 ID Register"] - #[inline(always)] - pub const fn mb_group_id21(&self) -> &MbGroupId21 { - unsafe { &*core::ptr::from_ref(self).cast::().add(468).cast() } - } - #[doc = "0x1d8 - Message Buffer 21 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word021(&self) -> &MbGroupWord021 { - unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } - } - #[doc = "0x1d8 - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word4(&self) -> &Mb32bGroupMb8_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } - } - #[doc = "0x1d8 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word12(&self) -> &Mb64bGroupMb4_64bWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } - } - #[doc = "0x1d8 - Message Buffer 21 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb21_8b_word0(&self) -> &Mb8bGroupMb21_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } - } - #[doc = "0x1d8 - Message Buffer 14 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb14_16b_word0(&self) -> &Mb16bGroupMb14_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(472).cast() } - } - #[doc = "0x1dc - Message Buffer 21 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word121(&self) -> &MbGroupWord121 { - unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } - } - #[doc = "0x1dc - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word5(&self) -> &Mb32bGroupMb8_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } - } - #[doc = "0x1dc - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word13(&self) -> &Mb64bGroupMb4_64bWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } - } - #[doc = "0x1dc - Message Buffer 21 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb21_8b_word1(&self) -> &Mb8bGroupMb21_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } - } - #[doc = "0x1dc - Message Buffer 14 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb14_16b_word1(&self) -> &Mb16bGroupMb14_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(476).cast() } - } - #[doc = "0x1e0 - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word6(&self) -> &Mb32bGroupMb8_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } - } - #[doc = "0x1e0 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word14(&self) -> &Mb64bGroupMb4_64bWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } - } - #[doc = "0x1e0 - Message Buffer 22 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb22_8b_cs(&self) -> &Mb8bGroupMb22_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } - } - #[doc = "0x1e0 - Message Buffer 14 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb14_16b_word2(&self) -> &Mb16bGroupMb14_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } - } - #[doc = "0x1e0 - Message Buffer 22 CS Register"] - #[inline(always)] - pub const fn mb_group_cs22(&self) -> &MbGroupCs22 { - unsafe { &*core::ptr::from_ref(self).cast::().add(480).cast() } - } - #[doc = "0x1e4 - Message Buffer 8 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb8_32b_word7(&self) -> &Mb32bGroupMb8_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } - } - #[doc = "0x1e4 - Message Buffer 4 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb4_64b_word15(&self) -> &Mb64bGroupMb4_64bWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } - } - #[doc = "0x1e4 - Message Buffer 22 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb22_8b_id(&self) -> &Mb8bGroupMb22_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } - } - #[doc = "0x1e4 - Message Buffer 14 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb14_16b_word3(&self) -> &Mb16bGroupMb14_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } - } - #[doc = "0x1e4 - Message Buffer 22 ID Register"] - #[inline(always)] - pub const fn mb_group_id22(&self) -> &MbGroupId22 { - unsafe { &*core::ptr::from_ref(self).cast::().add(484).cast() } - } - #[doc = "0x1e8 - Message Buffer 22 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word022(&self) -> &MbGroupWord022 { - unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } - } - #[doc = "0x1e8 - Message Buffer 9 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_cs(&self) -> &Mb32bGroupMb9_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } - } - #[doc = "0x1e8 - Message Buffer 5 CS Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_cs(&self) -> &Mb64bGroupMb5_64bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } - } - #[doc = "0x1e8 - Message Buffer 22 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb22_8b_word0(&self) -> &Mb8bGroupMb22_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } - } - #[doc = "0x1e8 - Message Buffer 15 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb15_16b_cs(&self) -> &Mb16bGroupMb15_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(488).cast() } - } - #[doc = "0x1ec - Message Buffer 22 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word122(&self) -> &MbGroupWord122 { - unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } - } - #[doc = "0x1ec - Message Buffer 9 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_id(&self) -> &Mb32bGroupMb9_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } - } - #[doc = "0x1ec - Message Buffer 5 ID Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_id(&self) -> &Mb64bGroupMb5_64bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } - } - #[doc = "0x1ec - Message Buffer 22 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb22_8b_word1(&self) -> &Mb8bGroupMb22_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } - } - #[doc = "0x1ec - Message Buffer 15 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb15_16b_id(&self) -> &Mb16bGroupMb15_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(492).cast() } - } - #[doc = "0x1f0 - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word0(&self) -> &Mb32bGroupMb9_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } - } - #[doc = "0x1f0 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word0(&self) -> &Mb64bGroupMb5_64bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } - } - #[doc = "0x1f0 - Message Buffer 23 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb23_8b_cs(&self) -> &Mb8bGroupMb23_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } - } - #[doc = "0x1f0 - Message Buffer 15 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb15_16b_word0(&self) -> &Mb16bGroupMb15_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } - } - #[doc = "0x1f0 - Message Buffer 23 CS Register"] - #[inline(always)] - pub const fn mb_group_cs23(&self) -> &MbGroupCs23 { - unsafe { &*core::ptr::from_ref(self).cast::().add(496).cast() } - } - #[doc = "0x1f4 - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word1(&self) -> &Mb32bGroupMb9_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } - } - #[doc = "0x1f4 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word1(&self) -> &Mb64bGroupMb5_64bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } - } - #[doc = "0x1f4 - Message Buffer 23 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb23_8b_id(&self) -> &Mb8bGroupMb23_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } - } - #[doc = "0x1f4 - Message Buffer 15 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb15_16b_word1(&self) -> &Mb16bGroupMb15_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } - } - #[doc = "0x1f4 - Message Buffer 23 ID Register"] - #[inline(always)] - pub const fn mb_group_id23(&self) -> &MbGroupId23 { - unsafe { &*core::ptr::from_ref(self).cast::().add(500).cast() } - } - #[doc = "0x1f8 - Message Buffer 23 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word023(&self) -> &MbGroupWord023 { - unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } - } - #[doc = "0x1f8 - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word2(&self) -> &Mb32bGroupMb9_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } - } - #[doc = "0x1f8 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word2(&self) -> &Mb64bGroupMb5_64bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } - } - #[doc = "0x1f8 - Message Buffer 23 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb23_8b_word0(&self) -> &Mb8bGroupMb23_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } - } - #[doc = "0x1f8 - Message Buffer 15 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb15_16b_word2(&self) -> &Mb16bGroupMb15_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(504).cast() } - } - #[doc = "0x1fc - Message Buffer 23 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word123(&self) -> &MbGroupWord123 { - unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } - } - #[doc = "0x1fc - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word3(&self) -> &Mb32bGroupMb9_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } - } - #[doc = "0x1fc - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word3(&self) -> &Mb64bGroupMb5_64bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } - } - #[doc = "0x1fc - Message Buffer 23 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb23_8b_word1(&self) -> &Mb8bGroupMb23_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } - } - #[doc = "0x1fc - Message Buffer 15 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb15_16b_word3(&self) -> &Mb16bGroupMb15_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(508).cast() } - } - #[doc = "0x200 - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word4(&self) -> &Mb32bGroupMb9_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } - } - #[doc = "0x200 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word4(&self) -> &Mb64bGroupMb5_64bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } - } - #[doc = "0x200 - Message Buffer 24 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb24_8b_cs(&self) -> &Mb8bGroupMb24_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } - } - #[doc = "0x200 - Message Buffer 16 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb16_16b_cs(&self) -> &Mb16bGroupMb16_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } - } - #[doc = "0x200 - Message Buffer 24 CS Register"] - #[inline(always)] - pub const fn mb_group_cs24(&self) -> &MbGroupCs24 { - unsafe { &*core::ptr::from_ref(self).cast::().add(512).cast() } - } - #[doc = "0x204 - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word5(&self) -> &Mb32bGroupMb9_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } - } - #[doc = "0x204 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word5(&self) -> &Mb64bGroupMb5_64bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } - } - #[doc = "0x204 - Message Buffer 24 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb24_8b_id(&self) -> &Mb8bGroupMb24_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } - } - #[doc = "0x204 - Message Buffer 16 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb16_16b_id(&self) -> &Mb16bGroupMb16_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } - } - #[doc = "0x204 - Message Buffer 24 ID Register"] - #[inline(always)] - pub const fn mb_group_id24(&self) -> &MbGroupId24 { - unsafe { &*core::ptr::from_ref(self).cast::().add(516).cast() } - } - #[doc = "0x208 - Message Buffer 24 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word024(&self) -> &MbGroupWord024 { - unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } - } - #[doc = "0x208 - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word6(&self) -> &Mb32bGroupMb9_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } - } - #[doc = "0x208 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word6(&self) -> &Mb64bGroupMb5_64bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } - } - #[doc = "0x208 - Message Buffer 24 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb24_8b_word0(&self) -> &Mb8bGroupMb24_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } - } - #[doc = "0x208 - Message Buffer 16 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb16_16b_word0(&self) -> &Mb16bGroupMb16_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(520).cast() } - } - #[doc = "0x20c - Message Buffer 24 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word124(&self) -> &MbGroupWord124 { - unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } - } - #[doc = "0x20c - Message Buffer 9 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb9_32b_word7(&self) -> &Mb32bGroupMb9_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } - } - #[doc = "0x20c - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word7(&self) -> &Mb64bGroupMb5_64bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } - } - #[doc = "0x20c - Message Buffer 24 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb24_8b_word1(&self) -> &Mb8bGroupMb24_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } - } - #[doc = "0x20c - Message Buffer 16 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb16_16b_word1(&self) -> &Mb16bGroupMb16_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(524).cast() } - } - #[doc = "0x210 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word8(&self) -> &Mb64bGroupMb5_64bWord8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } - } - #[doc = "0x210 - Message Buffer 25 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb25_8b_cs(&self) -> &Mb8bGroupMb25_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } - } - #[doc = "0x210 - Message Buffer 16 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb16_16b_word2(&self) -> &Mb16bGroupMb16_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } - } - #[doc = "0x210 - Message Buffer 10 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_cs(&self) -> &Mb32bGroupMb10_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } - } - #[doc = "0x210 - Message Buffer 25 CS Register"] - #[inline(always)] - pub const fn mb_group_cs25(&self) -> &MbGroupCs25 { - unsafe { &*core::ptr::from_ref(self).cast::().add(528).cast() } - } - #[doc = "0x214 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word9(&self) -> &Mb64bGroupMb5_64bWord9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } - } - #[doc = "0x214 - Message Buffer 25 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb25_8b_id(&self) -> &Mb8bGroupMb25_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } - } - #[doc = "0x214 - Message Buffer 16 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb16_16b_word3(&self) -> &Mb16bGroupMb16_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } - } - #[doc = "0x214 - Message Buffer 10 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_id(&self) -> &Mb32bGroupMb10_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } - } - #[doc = "0x214 - Message Buffer 25 ID Register"] - #[inline(always)] - pub const fn mb_group_id25(&self) -> &MbGroupId25 { - unsafe { &*core::ptr::from_ref(self).cast::().add(532).cast() } - } - #[doc = "0x218 - Message Buffer 25 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word025(&self) -> &MbGroupWord025 { - unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } - } - #[doc = "0x218 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word10(&self) -> &Mb64bGroupMb5_64bWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } - } - #[doc = "0x218 - Message Buffer 25 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb25_8b_word0(&self) -> &Mb8bGroupMb25_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } - } - #[doc = "0x218 - Message Buffer 17 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb17_16b_cs(&self) -> &Mb16bGroupMb17_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } - } - #[doc = "0x218 - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word0(&self) -> &Mb32bGroupMb10_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(536).cast() } - } - #[doc = "0x21c - Message Buffer 25 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word125(&self) -> &MbGroupWord125 { - unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } - } - #[doc = "0x21c - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word11(&self) -> &Mb64bGroupMb5_64bWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } - } - #[doc = "0x21c - Message Buffer 25 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb25_8b_word1(&self) -> &Mb8bGroupMb25_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } - } - #[doc = "0x21c - Message Buffer 17 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb17_16b_id(&self) -> &Mb16bGroupMb17_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } - } - #[doc = "0x21c - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word1(&self) -> &Mb32bGroupMb10_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(540).cast() } - } - #[doc = "0x220 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word12(&self) -> &Mb64bGroupMb5_64bWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } - } - #[doc = "0x220 - Message Buffer 26 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb26_8b_cs(&self) -> &Mb8bGroupMb26_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } - } - #[doc = "0x220 - Message Buffer 17 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb17_16b_word0(&self) -> &Mb16bGroupMb17_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } - } - #[doc = "0x220 - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word2(&self) -> &Mb32bGroupMb10_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } - } - #[doc = "0x220 - Message Buffer 26 CS Register"] - #[inline(always)] - pub const fn mb_group_cs26(&self) -> &MbGroupCs26 { - unsafe { &*core::ptr::from_ref(self).cast::().add(544).cast() } - } - #[doc = "0x224 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word13(&self) -> &Mb64bGroupMb5_64bWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } - } - #[doc = "0x224 - Message Buffer 26 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb26_8b_id(&self) -> &Mb8bGroupMb26_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } - } - #[doc = "0x224 - Message Buffer 17 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb17_16b_word1(&self) -> &Mb16bGroupMb17_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } - } - #[doc = "0x224 - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word3(&self) -> &Mb32bGroupMb10_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } - } - #[doc = "0x224 - Message Buffer 26 ID Register"] - #[inline(always)] - pub const fn mb_group_id26(&self) -> &MbGroupId26 { - unsafe { &*core::ptr::from_ref(self).cast::().add(548).cast() } - } - #[doc = "0x228 - Message Buffer 26 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word026(&self) -> &MbGroupWord026 { - unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } - } - #[doc = "0x228 - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word14(&self) -> &Mb64bGroupMb5_64bWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } - } - #[doc = "0x228 - Message Buffer 26 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb26_8b_word0(&self) -> &Mb8bGroupMb26_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } - } - #[doc = "0x228 - Message Buffer 17 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb17_16b_word2(&self) -> &Mb16bGroupMb17_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } - } - #[doc = "0x228 - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word4(&self) -> &Mb32bGroupMb10_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(552).cast() } - } - #[doc = "0x22c - Message Buffer 26 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word126(&self) -> &MbGroupWord126 { - unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } - } - #[doc = "0x22c - Message Buffer 5 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb5_64b_word15(&self) -> &Mb64bGroupMb5_64bWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } - } - #[doc = "0x22c - Message Buffer 26 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb26_8b_word1(&self) -> &Mb8bGroupMb26_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } - } - #[doc = "0x22c - Message Buffer 17 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb17_16b_word3(&self) -> &Mb16bGroupMb17_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } - } - #[doc = "0x22c - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word5(&self) -> &Mb32bGroupMb10_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(556).cast() } - } - #[doc = "0x230 - Message Buffer 6 CS Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_cs(&self) -> &Mb64bGroupMb6_64bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } - } - #[doc = "0x230 - Message Buffer 27 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb27_8b_cs(&self) -> &Mb8bGroupMb27_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } - } - #[doc = "0x230 - Message Buffer 18 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb18_16b_cs(&self) -> &Mb16bGroupMb18_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } - } - #[doc = "0x230 - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word6(&self) -> &Mb32bGroupMb10_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } - } - #[doc = "0x230 - Message Buffer 27 CS Register"] - #[inline(always)] - pub const fn mb_group_cs27(&self) -> &MbGroupCs27 { - unsafe { &*core::ptr::from_ref(self).cast::().add(560).cast() } - } - #[doc = "0x234 - Message Buffer 6 ID Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_id(&self) -> &Mb64bGroupMb6_64bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } - } - #[doc = "0x234 - Message Buffer 27 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb27_8b_id(&self) -> &Mb8bGroupMb27_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } - } - #[doc = "0x234 - Message Buffer 18 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb18_16b_id(&self) -> &Mb16bGroupMb18_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } - } - #[doc = "0x234 - Message Buffer 10 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb10_32b_word7(&self) -> &Mb32bGroupMb10_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } - } - #[doc = "0x234 - Message Buffer 27 ID Register"] - #[inline(always)] - pub const fn mb_group_id27(&self) -> &MbGroupId27 { - unsafe { &*core::ptr::from_ref(self).cast::().add(564).cast() } - } - #[doc = "0x238 - Message Buffer 27 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word027(&self) -> &MbGroupWord027 { - unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } - } - #[doc = "0x238 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word0(&self) -> &Mb64bGroupMb6_64bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } - } - #[doc = "0x238 - Message Buffer 27 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb27_8b_word0(&self) -> &Mb8bGroupMb27_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } - } - #[doc = "0x238 - Message Buffer 18 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb18_16b_word0(&self) -> &Mb16bGroupMb18_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } - } - #[doc = "0x238 - Message Buffer 11 CS Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_cs(&self) -> &Mb32bGroupMb11_32bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(568).cast() } - } - #[doc = "0x23c - Message Buffer 27 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word127(&self) -> &MbGroupWord127 { - unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } - } - #[doc = "0x23c - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word1(&self) -> &Mb64bGroupMb6_64bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } - } - #[doc = "0x23c - Message Buffer 27 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb27_8b_word1(&self) -> &Mb8bGroupMb27_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } - } - #[doc = "0x23c - Message Buffer 18 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb18_16b_word1(&self) -> &Mb16bGroupMb18_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } - } - #[doc = "0x23c - Message Buffer 11 ID Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_id(&self) -> &Mb32bGroupMb11_32bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(572).cast() } - } - #[doc = "0x240 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word2(&self) -> &Mb64bGroupMb6_64bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } - } - #[doc = "0x240 - Message Buffer 28 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb28_8b_cs(&self) -> &Mb8bGroupMb28_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } - } - #[doc = "0x240 - Message Buffer 18 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb18_16b_word2(&self) -> &Mb16bGroupMb18_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } - } - #[doc = "0x240 - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word0(&self) -> &Mb32bGroupMb11_32bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } - } - #[doc = "0x240 - Message Buffer 28 CS Register"] - #[inline(always)] - pub const fn mb_group_cs28(&self) -> &MbGroupCs28 { - unsafe { &*core::ptr::from_ref(self).cast::().add(576).cast() } - } - #[doc = "0x244 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word3(&self) -> &Mb64bGroupMb6_64bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } - } - #[doc = "0x244 - Message Buffer 28 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb28_8b_id(&self) -> &Mb8bGroupMb28_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } - } - #[doc = "0x244 - Message Buffer 18 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb18_16b_word3(&self) -> &Mb16bGroupMb18_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } - } - #[doc = "0x244 - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word1(&self) -> &Mb32bGroupMb11_32bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } - } - #[doc = "0x244 - Message Buffer 28 ID Register"] - #[inline(always)] - pub const fn mb_group_id28(&self) -> &MbGroupId28 { - unsafe { &*core::ptr::from_ref(self).cast::().add(580).cast() } - } - #[doc = "0x248 - Message Buffer 28 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word028(&self) -> &MbGroupWord028 { - unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } - } - #[doc = "0x248 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word4(&self) -> &Mb64bGroupMb6_64bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } - } - #[doc = "0x248 - Message Buffer 28 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb28_8b_word0(&self) -> &Mb8bGroupMb28_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } - } - #[doc = "0x248 - Message Buffer 19 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb19_16b_cs(&self) -> &Mb16bGroupMb19_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } - } - #[doc = "0x248 - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word2(&self) -> &Mb32bGroupMb11_32bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(584).cast() } - } - #[doc = "0x24c - Message Buffer 28 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word128(&self) -> &MbGroupWord128 { - unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } - } - #[doc = "0x24c - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word5(&self) -> &Mb64bGroupMb6_64bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } - } - #[doc = "0x24c - Message Buffer 28 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb28_8b_word1(&self) -> &Mb8bGroupMb28_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } - } - #[doc = "0x24c - Message Buffer 19 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb19_16b_id(&self) -> &Mb16bGroupMb19_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } - } - #[doc = "0x24c - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word3(&self) -> &Mb32bGroupMb11_32bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(588).cast() } - } - #[doc = "0x250 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word6(&self) -> &Mb64bGroupMb6_64bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } - } - #[doc = "0x250 - Message Buffer 29 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb29_8b_cs(&self) -> &Mb8bGroupMb29_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } - } - #[doc = "0x250 - Message Buffer 19 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb19_16b_word0(&self) -> &Mb16bGroupMb19_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } - } - #[doc = "0x250 - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word4(&self) -> &Mb32bGroupMb11_32bWord4 { - unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } - } - #[doc = "0x250 - Message Buffer 29 CS Register"] - #[inline(always)] - pub const fn mb_group_cs29(&self) -> &MbGroupCs29 { - unsafe { &*core::ptr::from_ref(self).cast::().add(592).cast() } - } - #[doc = "0x254 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word7(&self) -> &Mb64bGroupMb6_64bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } - } - #[doc = "0x254 - Message Buffer 29 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb29_8b_id(&self) -> &Mb8bGroupMb29_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } - } - #[doc = "0x254 - Message Buffer 19 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb19_16b_word1(&self) -> &Mb16bGroupMb19_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } - } - #[doc = "0x254 - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word5(&self) -> &Mb32bGroupMb11_32bWord5 { - unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } - } - #[doc = "0x254 - Message Buffer 29 ID Register"] - #[inline(always)] - pub const fn mb_group_id29(&self) -> &MbGroupId29 { - unsafe { &*core::ptr::from_ref(self).cast::().add(596).cast() } - } - #[doc = "0x258 - Message Buffer 29 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word029(&self) -> &MbGroupWord029 { - unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } - } - #[doc = "0x258 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word8(&self) -> &Mb64bGroupMb6_64bWord8 { - unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } - } - #[doc = "0x258 - Message Buffer 29 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb29_8b_word0(&self) -> &Mb8bGroupMb29_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } - } - #[doc = "0x258 - Message Buffer 19 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb19_16b_word2(&self) -> &Mb16bGroupMb19_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } - } - #[doc = "0x258 - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word6(&self) -> &Mb32bGroupMb11_32bWord6 { - unsafe { &*core::ptr::from_ref(self).cast::().add(600).cast() } - } - #[doc = "0x25c - Message Buffer 29 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word129(&self) -> &MbGroupWord129 { - unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } - } - #[doc = "0x25c - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word9(&self) -> &Mb64bGroupMb6_64bWord9 { - unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } - } - #[doc = "0x25c - Message Buffer 29 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb29_8b_word1(&self) -> &Mb8bGroupMb29_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } - } - #[doc = "0x25c - Message Buffer 19 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb19_16b_word3(&self) -> &Mb16bGroupMb19_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } - } - #[doc = "0x25c - Message Buffer 11 WORD_32B Register"] - #[inline(always)] - pub const fn mb_32b_group_mb11_32b_word7(&self) -> &Mb32bGroupMb11_32bWord7 { - unsafe { &*core::ptr::from_ref(self).cast::().add(604).cast() } - } - #[doc = "0x260 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word10(&self) -> &Mb64bGroupMb6_64bWord10 { - unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } - } - #[doc = "0x260 - Message Buffer 30 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb30_8b_cs(&self) -> &Mb8bGroupMb30_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } - } - #[doc = "0x260 - Message Buffer 20 CS Register"] - #[inline(always)] - pub const fn mb_16b_group_mb20_16b_cs(&self) -> &Mb16bGroupMb20_16bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } - } - #[doc = "0x260 - Message Buffer 30 CS Register"] - #[inline(always)] - pub const fn mb_group_cs30(&self) -> &MbGroupCs30 { - unsafe { &*core::ptr::from_ref(self).cast::().add(608).cast() } - } - #[doc = "0x264 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word11(&self) -> &Mb64bGroupMb6_64bWord11 { - unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } - } - #[doc = "0x264 - Message Buffer 30 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb30_8b_id(&self) -> &Mb8bGroupMb30_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } - } - #[doc = "0x264 - Message Buffer 20 ID Register"] - #[inline(always)] - pub const fn mb_16b_group_mb20_16b_id(&self) -> &Mb16bGroupMb20_16bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } - } - #[doc = "0x264 - Message Buffer 30 ID Register"] - #[inline(always)] - pub const fn mb_group_id30(&self) -> &MbGroupId30 { - unsafe { &*core::ptr::from_ref(self).cast::().add(612).cast() } - } - #[doc = "0x268 - Message Buffer 30 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word030(&self) -> &MbGroupWord030 { - unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } - } - #[doc = "0x268 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word12(&self) -> &Mb64bGroupMb6_64bWord12 { - unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } - } - #[doc = "0x268 - Message Buffer 30 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb30_8b_word0(&self) -> &Mb8bGroupMb30_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } - } - #[doc = "0x268 - Message Buffer 20 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb20_16b_word0(&self) -> &Mb16bGroupMb20_16bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(616).cast() } - } - #[doc = "0x26c - Message Buffer 30 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word130(&self) -> &MbGroupWord130 { - unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } - } - #[doc = "0x26c - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word13(&self) -> &Mb64bGroupMb6_64bWord13 { - unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } - } - #[doc = "0x26c - Message Buffer 30 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb30_8b_word1(&self) -> &Mb8bGroupMb30_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } - } - #[doc = "0x26c - Message Buffer 20 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb20_16b_word1(&self) -> &Mb16bGroupMb20_16bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(620).cast() } - } - #[doc = "0x270 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word14(&self) -> &Mb64bGroupMb6_64bWord14 { - unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } - } - #[doc = "0x270 - Message Buffer 31 CS Register"] - #[inline(always)] - pub const fn mb_8b_group_mb31_8b_cs(&self) -> &Mb8bGroupMb31_8bCs { - unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } - } - #[doc = "0x270 - Message Buffer 20 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb20_16b_word2(&self) -> &Mb16bGroupMb20_16bWord2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } - } - #[doc = "0x270 - Message Buffer 31 CS Register"] - #[inline(always)] - pub const fn mb_group_cs31(&self) -> &MbGroupCs31 { - unsafe { &*core::ptr::from_ref(self).cast::().add(624).cast() } - } - #[doc = "0x274 - Message Buffer 6 WORD_64B Register"] - #[inline(always)] - pub const fn mb_64b_group_mb6_64b_word15(&self) -> &Mb64bGroupMb6_64bWord15 { - unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } - } - #[doc = "0x274 - Message Buffer 31 ID Register"] - #[inline(always)] - pub const fn mb_8b_group_mb31_8b_id(&self) -> &Mb8bGroupMb31_8bId { - unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } - } - #[doc = "0x274 - Message Buffer 20 WORD_16B Register"] - #[inline(always)] - pub const fn mb_16b_group_mb20_16b_word3(&self) -> &Mb16bGroupMb20_16bWord3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } - } - #[doc = "0x274 - Message Buffer 31 ID Register"] - #[inline(always)] - pub const fn mb_group_id31(&self) -> &MbGroupId31 { - unsafe { &*core::ptr::from_ref(self).cast::().add(628).cast() } - } - #[doc = "0x278 - Message Buffer 31 WORD0 Register"] - #[inline(always)] - pub const fn mb_group_word031(&self) -> &MbGroupWord031 { - unsafe { &*core::ptr::from_ref(self).cast::().add(632).cast() } - } - #[doc = "0x278 - Message Buffer 31 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb31_8b_word0(&self) -> &Mb8bGroupMb31_8bWord0 { - unsafe { &*core::ptr::from_ref(self).cast::().add(632).cast() } - } - #[doc = "0x27c - Message Buffer 31 WORD1 Register"] - #[inline(always)] - pub const fn mb_group_word131(&self) -> &MbGroupWord131 { - unsafe { &*core::ptr::from_ref(self).cast::().add(636).cast() } - } - #[doc = "0x27c - Message Buffer 31 WORD_8B Register"] - #[inline(always)] - pub const fn mb_8b_group_mb31_8b_word1(&self) -> &Mb8bGroupMb31_8bWord1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(636).cast() } - } - #[doc = "0x880..0x900 - Receive Individual Mask"] - #[inline(always)] - pub const fn rximr(&self, n: usize) -> &Rximr { - &self.rximr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x880..0x900 - Receive Individual Mask"] - #[inline(always)] - pub fn rximr_iter(&self) -> impl Iterator { - self.rximr.iter() - } - #[doc = "0xb00 - Pretended Networking Control 1"] - #[inline(always)] - pub const fn ctrl1_pn(&self) -> &Ctrl1Pn { - &self.ctrl1_pn - } - #[doc = "0xb04 - Pretended Networking Control 2"] - #[inline(always)] - pub const fn ctrl2_pn(&self) -> &Ctrl2Pn { - &self.ctrl2_pn - } - #[doc = "0xb08 - Pretended Networking Wake-Up Match"] - #[inline(always)] - pub const fn wu_mtc(&self) -> &WuMtc { - &self.wu_mtc - } - #[doc = "0xb0c - Pretended Networking ID Filter 1"] - #[inline(always)] - pub const fn flt_id1(&self) -> &FltId1 { - &self.flt_id1 - } - #[doc = "0xb10 - Pretended Networking Data Length Code (DLC) Filter"] - #[inline(always)] - pub const fn flt_dlc(&self) -> &FltDlc { - &self.flt_dlc - } - #[doc = "0xb14 - Pretended Networking Payload Low Filter 1"] - #[inline(always)] - pub const fn pl1_lo(&self) -> &Pl1Lo { - &self.pl1_lo - } - #[doc = "0xb18 - Pretended Networking Payload High Filter 1"] - #[inline(always)] - pub const fn pl1_hi(&self) -> &Pl1Hi { - &self.pl1_hi - } - #[doc = "0xb1c - Pretended Networking ID Filter 2 or ID Mask"] - #[inline(always)] - pub const fn flt_id2_idmask(&self) -> &FltId2Idmask { - &self.flt_id2_idmask - } - #[doc = "0xb20 - Pretended Networking Payload Low Filter 2 and Payload Low Mask"] - #[inline(always)] - pub const fn pl2_plmask_lo(&self) -> &Pl2PlmaskLo { - &self.pl2_plmask_lo - } - #[doc = "0xb24 - Pretended Networking Payload High Filter 2 and Payload High Mask"] - #[inline(always)] - pub const fn pl2_plmask_hi(&self) -> &Pl2PlmaskHi { - &self.pl2_plmask_hi - } - #[doc = "0xb40..0xb80 - Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] - #[inline(always)] - pub const fn wmb(&self, n: usize) -> &Wmb { - &self.wmb[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0xb40..0xb80 - Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] - #[inline(always)] - pub fn wmb_iter(&self) -> impl Iterator { - self.wmb.iter() - } - #[doc = "0xbf0 - Enhanced CAN Bit Timing Prescalers"] - #[inline(always)] - pub const fn eprs(&self) -> &Eprs { - &self.eprs - } - #[doc = "0xbf4 - Enhanced Nominal CAN Bit Timing"] - #[inline(always)] - pub const fn encbt(&self) -> &Encbt { - &self.encbt - } - #[doc = "0xbf8 - Enhanced Data Phase CAN Bit Timing"] - #[inline(always)] - pub const fn edcbt(&self) -> &Edcbt { - &self.edcbt - } - #[doc = "0xbfc - Enhanced Transceiver Delay Compensation"] - #[inline(always)] - pub const fn etdc(&self) -> &Etdc { - &self.etdc - } - #[doc = "0xc00 - CAN FD Control"] - #[inline(always)] - pub const fn fdctrl(&self) -> &Fdctrl { - &self.fdctrl - } - #[doc = "0xc04 - CAN FD Bit Timing"] - #[inline(always)] - pub const fn fdcbt(&self) -> &Fdcbt { - &self.fdcbt - } - #[doc = "0xc08 - CAN FD CRC"] - #[inline(always)] - pub const fn fdcrc(&self) -> &Fdcrc { - &self.fdcrc - } - #[doc = "0xc0c - Enhanced RX FIFO Control"] - #[inline(always)] - pub const fn erfcr(&self) -> &Erfcr { - &self.erfcr - } - #[doc = "0xc10 - Enhanced RX FIFO Interrupt Enable"] - #[inline(always)] - pub const fn erfier(&self) -> &Erfier { - &self.erfier - } - #[doc = "0xc14 - Enhanced RX FIFO Status"] - #[inline(always)] - pub const fn erfsr(&self) -> &Erfsr { - &self.erfsr - } - #[doc = "0x3000..0x3080 - Enhanced RX FIFO Filter Element"] - #[inline(always)] - pub const fn erffel(&self, n: usize) -> &Erffel { - &self.erffel[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x3000..0x3080 - Enhanced RX FIFO Filter Element"] - #[inline(always)] - pub fn erffel_iter(&self) -> impl Iterator { - self.erffel.iter() - } -} -#[doc = "MCR (rw) register accessor: Module Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] -#[doc(alias = "MCR")] -pub type Mcr = crate::Reg; -#[doc = "Module Configuration"] -pub mod mcr; -#[doc = "CTRL1 (rw) register accessor: Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"] -#[doc(alias = "CTRL1")] -pub type Ctrl1 = crate::Reg; -#[doc = "Control 1"] -pub mod ctrl1; -#[doc = "TIMER (rw) register accessor: Free-Running Timer\n\nYou can [`read`](crate::Reg::read) this register and get [`timer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer`] module"] -#[doc(alias = "TIMER")] -pub type Timer = crate::Reg; -#[doc = "Free-Running Timer"] -pub mod timer; -#[doc = "RXMGMASK (rw) register accessor: RX Message Buffers Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxmgmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxmgmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxmgmask`] module"] -#[doc(alias = "RXMGMASK")] -pub type Rxmgmask = crate::Reg; -#[doc = "RX Message Buffers Global Mask"] -pub mod rxmgmask; -#[doc = "RX14MASK (rw) register accessor: Receive 14 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx14mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx14mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx14mask`] module"] -#[doc(alias = "RX14MASK")] -pub type Rx14mask = crate::Reg; -#[doc = "Receive 14 Mask"] -pub mod rx14mask; -#[doc = "RX15MASK (rw) register accessor: Receive 15 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx15mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx15mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx15mask`] module"] -#[doc(alias = "RX15MASK")] -pub type Rx15mask = crate::Reg; -#[doc = "Receive 15 Mask"] -pub mod rx15mask; -#[doc = "ECR (rw) register accessor: Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`] module"] -#[doc(alias = "ECR")] -pub type Ecr = crate::Reg; -#[doc = "Error Counter"] -pub mod ecr; -#[doc = "ESR1 (rw) register accessor: Error and Status 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr1`] module"] -#[doc(alias = "ESR1")] -pub type Esr1 = crate::Reg; -#[doc = "Error and Status 1"] -pub mod esr1; -#[doc = "IMASK1 (rw) register accessor: Interrupt Masks 1\n\nYou can [`read`](crate::Reg::read) this register and get [`imask1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imask1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask1`] module"] -#[doc(alias = "IMASK1")] -pub type Imask1 = crate::Reg; -#[doc = "Interrupt Masks 1"] -pub mod imask1; -#[doc = "IFLAG1 (rw) register accessor: Interrupt Flags 1\n\nYou can [`read`](crate::Reg::read) this register and get [`iflag1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iflag1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iflag1`] module"] -#[doc(alias = "IFLAG1")] -pub type Iflag1 = crate::Reg; -#[doc = "Interrupt Flags 1"] -pub mod iflag1; -#[doc = "CTRL2 (rw) register accessor: Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"] -#[doc(alias = "CTRL2")] -pub type Ctrl2 = crate::Reg; -#[doc = "Control 2"] -pub mod ctrl2; -#[doc = "ESR2 (r) register accessor: Error and Status 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr2`] module"] -#[doc(alias = "ESR2")] -pub type Esr2 = crate::Reg; -#[doc = "Error and Status 2"] -pub mod esr2; -#[doc = "CRCR (r) register accessor: Cyclic Redundancy Check\n\nYou can [`read`](crate::Reg::read) this register and get [`crcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcr`] module"] -#[doc(alias = "CRCR")] -pub type Crcr = crate::Reg; -#[doc = "Cyclic Redundancy Check"] -pub mod crcr; -#[doc = "RXFGMASK (rw) register accessor: Legacy RX FIFO Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfgmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfgmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfgmask`] module"] -#[doc(alias = "RXFGMASK")] -pub type Rxfgmask = crate::Reg; -#[doc = "Legacy RX FIFO Global Mask"] -pub mod rxfgmask; -#[doc = "RXFIR (r) register accessor: Legacy RX FIFO Information\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfir`] module"] -#[doc(alias = "RXFIR")] -pub type Rxfir = crate::Reg; -#[doc = "Legacy RX FIFO Information"] -pub mod rxfir; -#[doc = "CBT (rw) register accessor: CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`cbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbt`] module"] -#[doc(alias = "CBT")] -pub type Cbt = crate::Reg; -#[doc = "CAN Bit Timing"] -pub mod cbt; -#[doc = "MB_GROUP_CS0 (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs0`] module"] -#[doc(alias = "MB_GROUP_CS0")] -pub type MbGroupCs0 = crate::Reg; -#[doc = "Message Buffer 0 CS Register"] -pub mod mb_group_cs0; -#[doc = "MB_16B_GROUP_MB0_16B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB0_16B_CS")] -pub type Mb16bGroupMb0_16bCs = crate::Reg; -#[doc = "Message Buffer 0 CS Register"] -pub mod mb_16b_group_mb0_16b_cs; -#[doc = "MB_32B_GROUP_MB0_32B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_CS")] -pub type Mb32bGroupMb0_32bCs = crate::Reg; -#[doc = "Message Buffer 0 CS Register"] -pub mod mb_32b_group_mb0_32b_cs; -#[doc = "MB_64B_GROUP_MB0_64B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_cs`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_CS")] -pub type Mb64bGroupMb0_64bCs = crate::Reg; -#[doc = "Message Buffer 0 CS Register"] -pub mod mb_64b_group_mb0_64b_cs; -#[doc = "MB_8B_GROUP_MB0_8B_CS (rw) register accessor: Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB0_8B_CS")] -pub type Mb8bGroupMb0_8bCs = crate::Reg; -#[doc = "Message Buffer 0 CS Register"] -pub mod mb_8b_group_mb0_8b_cs; -#[doc = "MB_GROUP_ID0 (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id0`] module"] -#[doc(alias = "MB_GROUP_ID0")] -pub type MbGroupId0 = crate::Reg; -#[doc = "Message Buffer 0 ID Register"] -pub mod mb_group_id0; -#[doc = "MB_16B_GROUP_MB0_16B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB0_16B_ID")] -pub type Mb16bGroupMb0_16bId = crate::Reg; -#[doc = "Message Buffer 0 ID Register"] -pub mod mb_16b_group_mb0_16b_id; -#[doc = "MB_32B_GROUP_MB0_32B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_ID")] -pub type Mb32bGroupMb0_32bId = crate::Reg; -#[doc = "Message Buffer 0 ID Register"] -pub mod mb_32b_group_mb0_32b_id; -#[doc = "MB_64B_GROUP_MB0_64B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_id`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_ID")] -pub type Mb64bGroupMb0_64bId = crate::Reg; -#[doc = "Message Buffer 0 ID Register"] -pub mod mb_64b_group_mb0_64b_id; -#[doc = "MB_8B_GROUP_MB0_8B_ID (rw) register accessor: Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB0_8B_ID")] -pub type Mb8bGroupMb0_8bId = crate::Reg; -#[doc = "Message Buffer 0 ID Register"] -pub mod mb_8b_group_mb0_8b_id; -#[doc = "MB_16B_GROUP_MB0_16B_WORD0 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD0")] -pub type Mb16bGroupMb0_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_16B Register"] -pub mod mb_16b_group_mb0_16b_word0; -#[doc = "MB_32B_GROUP_MB0_32B_WORD0 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD0")] -pub type Mb32bGroupMb0_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word0; -#[doc = "MB_64B_GROUP_MB0_64B_WORD0 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word0`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD0")] -pub type Mb64bGroupMb0_64bWord0 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word0; -#[doc = "MB_8B_GROUP_MB0_8B_WORD0 (rw) register accessor: Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB0_8B_WORD0")] -pub type Mb8bGroupMb0_8bWord0 = crate::Reg; -#[doc = "Message Buffer 0 WORD_8B Register"] -pub mod mb_8b_group_mb0_8b_word0; -#[doc = "MB_GROUP_WORD00 (rw) register accessor: Message Buffer 0 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word00::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word00::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word00`] module"] -#[doc(alias = "MB_GROUP_WORD00")] -pub type MbGroupWord00 = crate::Reg; -#[doc = "Message Buffer 0 WORD0 Register"] -pub mod mb_group_word00; -#[doc = "MB_16B_GROUP_MB0_16B_WORD1 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD1")] -pub type Mb16bGroupMb0_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_16B Register"] -pub mod mb_16b_group_mb0_16b_word1; -#[doc = "MB_32B_GROUP_MB0_32B_WORD1 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD1")] -pub type Mb32bGroupMb0_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word1; -#[doc = "MB_64B_GROUP_MB0_64B_WORD1 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word1`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD1")] -pub type Mb64bGroupMb0_64bWord1 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word1; -#[doc = "MB_8B_GROUP_MB0_8B_WORD1 (rw) register accessor: Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb0_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB0_8B_WORD1")] -pub type Mb8bGroupMb0_8bWord1 = crate::Reg; -#[doc = "Message Buffer 0 WORD_8B Register"] -pub mod mb_8b_group_mb0_8b_word1; -#[doc = "MB_GROUP_WORD10 (rw) register accessor: Message Buffer 0 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word10`] module"] -#[doc(alias = "MB_GROUP_WORD10")] -pub type MbGroupWord10 = crate::Reg; -#[doc = "Message Buffer 0 WORD1 Register"] -pub mod mb_group_word10; -#[doc = "MB_GROUP_CS1 (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs1`] module"] -#[doc(alias = "MB_GROUP_CS1")] -pub type MbGroupCs1 = crate::Reg; -#[doc = "Message Buffer 1 CS Register"] -pub mod mb_group_cs1; -#[doc = "MB_16B_GROUP_MB0_16B_WORD2 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD2")] -pub type Mb16bGroupMb0_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_16B Register"] -pub mod mb_16b_group_mb0_16b_word2; -#[doc = "MB_32B_GROUP_MB0_32B_WORD2 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD2")] -pub type Mb32bGroupMb0_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word2; -#[doc = "MB_64B_GROUP_MB0_64B_WORD2 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word2`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD2")] -pub type Mb64bGroupMb0_64bWord2 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word2; -#[doc = "MB_8B_GROUP_MB1_8B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB1_8B_CS")] -pub type Mb8bGroupMb1_8bCs = crate::Reg; -#[doc = "Message Buffer 1 CS Register"] -pub mod mb_8b_group_mb1_8b_cs; -#[doc = "MB_GROUP_ID1 (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id1`] module"] -#[doc(alias = "MB_GROUP_ID1")] -pub type MbGroupId1 = crate::Reg; -#[doc = "Message Buffer 1 ID Register"] -pub mod mb_group_id1; -#[doc = "MB_16B_GROUP_MB0_16B_WORD3 (rw) register accessor: Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb0_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB0_16B_WORD3")] -pub type Mb16bGroupMb0_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_16B Register"] -pub mod mb_16b_group_mb0_16b_word3; -#[doc = "MB_32B_GROUP_MB0_32B_WORD3 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD3")] -pub type Mb32bGroupMb0_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word3; -#[doc = "MB_64B_GROUP_MB0_64B_WORD3 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word3`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD3")] -pub type Mb64bGroupMb0_64bWord3 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word3; -#[doc = "MB_8B_GROUP_MB1_8B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB1_8B_ID")] -pub type Mb8bGroupMb1_8bId = crate::Reg; -#[doc = "Message Buffer 1 ID Register"] -pub mod mb_8b_group_mb1_8b_id; -#[doc = "MB_32B_GROUP_MB0_32B_WORD4 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD4")] -pub type Mb32bGroupMb0_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word4; -#[doc = "MB_64B_GROUP_MB0_64B_WORD4 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word4`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD4")] -pub type Mb64bGroupMb0_64bWord4 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word4; -#[doc = "MB_16B_GROUP_MB1_16B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB1_16B_CS")] -pub type Mb16bGroupMb1_16bCs = crate::Reg; -#[doc = "Message Buffer 1 CS Register"] -pub mod mb_16b_group_mb1_16b_cs; -#[doc = "MB_8B_GROUP_MB1_8B_WORD0 (rw) register accessor: Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB1_8B_WORD0")] -pub type Mb8bGroupMb1_8bWord0 = crate::Reg; -#[doc = "Message Buffer 1 WORD_8B Register"] -pub mod mb_8b_group_mb1_8b_word0; -#[doc = "MB_GROUP_WORD01 (rw) register accessor: Message Buffer 1 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word01::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word01::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word01`] module"] -#[doc(alias = "MB_GROUP_WORD01")] -pub type MbGroupWord01 = crate::Reg; -#[doc = "Message Buffer 1 WORD0 Register"] -pub mod mb_group_word01; -#[doc = "MB_32B_GROUP_MB0_32B_WORD5 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD5")] -pub type Mb32bGroupMb0_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word5; -#[doc = "MB_64B_GROUP_MB0_64B_WORD5 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word5`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD5")] -pub type Mb64bGroupMb0_64bWord5 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word5; -#[doc = "MB_16B_GROUP_MB1_16B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB1_16B_ID")] -pub type Mb16bGroupMb1_16bId = crate::Reg; -#[doc = "Message Buffer 1 ID Register"] -pub mod mb_16b_group_mb1_16b_id; -#[doc = "MB_8B_GROUP_MB1_8B_WORD1 (rw) register accessor: Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb1_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB1_8B_WORD1")] -pub type Mb8bGroupMb1_8bWord1 = crate::Reg; -#[doc = "Message Buffer 1 WORD_8B Register"] -pub mod mb_8b_group_mb1_8b_word1; -#[doc = "MB_GROUP_WORD11 (rw) register accessor: Message Buffer 1 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word11`] module"] -#[doc(alias = "MB_GROUP_WORD11")] -pub type MbGroupWord11 = crate::Reg; -#[doc = "Message Buffer 1 WORD1 Register"] -pub mod mb_group_word11; -#[doc = "MB_GROUP_CS2 (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs2`] module"] -#[doc(alias = "MB_GROUP_CS2")] -pub type MbGroupCs2 = crate::Reg; -#[doc = "Message Buffer 2 CS Register"] -pub mod mb_group_cs2; -#[doc = "MB_32B_GROUP_MB0_32B_WORD6 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD6")] -pub type Mb32bGroupMb0_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word6; -#[doc = "MB_64B_GROUP_MB0_64B_WORD6 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word6`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD6")] -pub type Mb64bGroupMb0_64bWord6 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word6; -#[doc = "MB_16B_GROUP_MB1_16B_WORD0 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD0")] -pub type Mb16bGroupMb1_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_16B Register"] -pub mod mb_16b_group_mb1_16b_word0; -#[doc = "MB_8B_GROUP_MB2_8B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB2_8B_CS")] -pub type Mb8bGroupMb2_8bCs = crate::Reg; -#[doc = "Message Buffer 2 CS Register"] -pub mod mb_8b_group_mb2_8b_cs; -#[doc = "MB_GROUP_ID2 (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id2`] module"] -#[doc(alias = "MB_GROUP_ID2")] -pub type MbGroupId2 = crate::Reg; -#[doc = "Message Buffer 2 ID Register"] -pub mod mb_group_id2; -#[doc = "MB_32B_GROUP_MB0_32B_WORD7 (rw) register accessor: Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb0_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB0_32B_WORD7")] -pub type Mb32bGroupMb0_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_32B Register"] -pub mod mb_32b_group_mb0_32b_word7; -#[doc = "MB_64B_GROUP_MB0_64B_WORD7 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word7`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD7")] -pub type Mb64bGroupMb0_64bWord7 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word7; -#[doc = "MB_16B_GROUP_MB1_16B_WORD1 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD1")] -pub type Mb16bGroupMb1_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_16B Register"] -pub mod mb_16b_group_mb1_16b_word1; -#[doc = "MB_8B_GROUP_MB2_8B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB2_8B_ID")] -pub type Mb8bGroupMb2_8bId = crate::Reg; -#[doc = "Message Buffer 2 ID Register"] -pub mod mb_8b_group_mb2_8b_id; -#[doc = "MB_64B_GROUP_MB0_64B_WORD8 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word8`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD8")] -pub type Mb64bGroupMb0_64bWord8 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word8; -#[doc = "MB_16B_GROUP_MB1_16B_WORD2 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD2")] -pub type Mb16bGroupMb1_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_16B Register"] -pub mod mb_16b_group_mb1_16b_word2; -#[doc = "MB_32B_GROUP_MB1_32B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_CS")] -pub type Mb32bGroupMb1_32bCs = crate::Reg; -#[doc = "Message Buffer 1 CS Register"] -pub mod mb_32b_group_mb1_32b_cs; -#[doc = "MB_8B_GROUP_MB2_8B_WORD0 (rw) register accessor: Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB2_8B_WORD0")] -pub type Mb8bGroupMb2_8bWord0 = crate::Reg; -#[doc = "Message Buffer 2 WORD_8B Register"] -pub mod mb_8b_group_mb2_8b_word0; -#[doc = "MB_GROUP_WORD02 (rw) register accessor: Message Buffer 2 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word02::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word02::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word02`] module"] -#[doc(alias = "MB_GROUP_WORD02")] -pub type MbGroupWord02 = crate::Reg; -#[doc = "Message Buffer 2 WORD0 Register"] -pub mod mb_group_word02; -#[doc = "MB_64B_GROUP_MB0_64B_WORD9 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word9`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD9")] -pub type Mb64bGroupMb0_64bWord9 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word9; -#[doc = "MB_16B_GROUP_MB1_16B_WORD3 (rw) register accessor: Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb1_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB1_16B_WORD3")] -pub type Mb16bGroupMb1_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_16B Register"] -pub mod mb_16b_group_mb1_16b_word3; -#[doc = "MB_32B_GROUP_MB1_32B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_ID")] -pub type Mb32bGroupMb1_32bId = crate::Reg; -#[doc = "Message Buffer 1 ID Register"] -pub mod mb_32b_group_mb1_32b_id; -#[doc = "MB_8B_GROUP_MB2_8B_WORD1 (rw) register accessor: Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb2_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB2_8B_WORD1")] -pub type Mb8bGroupMb2_8bWord1 = crate::Reg; -#[doc = "Message Buffer 2 WORD_8B Register"] -pub mod mb_8b_group_mb2_8b_word1; -#[doc = "MB_GROUP_WORD12 (rw) register accessor: Message Buffer 2 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word12`] module"] -#[doc(alias = "MB_GROUP_WORD12")] -pub type MbGroupWord12 = crate::Reg; -#[doc = "Message Buffer 2 WORD1 Register"] -pub mod mb_group_word12; -#[doc = "MB_GROUP_CS3 (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs3`] module"] -#[doc(alias = "MB_GROUP_CS3")] -pub type MbGroupCs3 = crate::Reg; -#[doc = "Message Buffer 3 CS Register"] -pub mod mb_group_cs3; -#[doc = "MB_64B_GROUP_MB0_64B_WORD10 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word10`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD10")] -pub type Mb64bGroupMb0_64bWord10 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word10; -#[doc = "MB_32B_GROUP_MB1_32B_WORD0 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD0")] -pub type Mb32bGroupMb1_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word0; -#[doc = "MB_16B_GROUP_MB2_16B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB2_16B_CS")] -pub type Mb16bGroupMb2_16bCs = crate::Reg; -#[doc = "Message Buffer 2 CS Register"] -pub mod mb_16b_group_mb2_16b_cs; -#[doc = "MB_8B_GROUP_MB3_8B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB3_8B_CS")] -pub type Mb8bGroupMb3_8bCs = crate::Reg; -#[doc = "Message Buffer 3 CS Register"] -pub mod mb_8b_group_mb3_8b_cs; -#[doc = "MB_GROUP_ID3 (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id3`] module"] -#[doc(alias = "MB_GROUP_ID3")] -pub type MbGroupId3 = crate::Reg; -#[doc = "Message Buffer 3 ID Register"] -pub mod mb_group_id3; -#[doc = "MB_64B_GROUP_MB0_64B_WORD11 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word11`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD11")] -pub type Mb64bGroupMb0_64bWord11 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word11; -#[doc = "MB_32B_GROUP_MB1_32B_WORD1 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD1")] -pub type Mb32bGroupMb1_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word1; -#[doc = "MB_16B_GROUP_MB2_16B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB2_16B_ID")] -pub type Mb16bGroupMb2_16bId = crate::Reg; -#[doc = "Message Buffer 2 ID Register"] -pub mod mb_16b_group_mb2_16b_id; -#[doc = "MB_8B_GROUP_MB3_8B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB3_8B_ID")] -pub type Mb8bGroupMb3_8bId = crate::Reg; -#[doc = "Message Buffer 3 ID Register"] -pub mod mb_8b_group_mb3_8b_id; -#[doc = "MB_64B_GROUP_MB0_64B_WORD12 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word12`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD12")] -pub type Mb64bGroupMb0_64bWord12 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word12; -#[doc = "MB_32B_GROUP_MB1_32B_WORD2 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD2")] -pub type Mb32bGroupMb1_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word2; -#[doc = "MB_16B_GROUP_MB2_16B_WORD0 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD0")] -pub type Mb16bGroupMb2_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_16B Register"] -pub mod mb_16b_group_mb2_16b_word0; -#[doc = "MB_8B_GROUP_MB3_8B_WORD0 (rw) register accessor: Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB3_8B_WORD0")] -pub type Mb8bGroupMb3_8bWord0 = crate::Reg; -#[doc = "Message Buffer 3 WORD_8B Register"] -pub mod mb_8b_group_mb3_8b_word0; -#[doc = "MB_GROUP_WORD03 (rw) register accessor: Message Buffer 3 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word03::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word03::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word03`] module"] -#[doc(alias = "MB_GROUP_WORD03")] -pub type MbGroupWord03 = crate::Reg; -#[doc = "Message Buffer 3 WORD0 Register"] -pub mod mb_group_word03; -#[doc = "MB_64B_GROUP_MB0_64B_WORD13 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word13`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD13")] -pub type Mb64bGroupMb0_64bWord13 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word13; -#[doc = "MB_32B_GROUP_MB1_32B_WORD3 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD3")] -pub type Mb32bGroupMb1_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word3; -#[doc = "MB_16B_GROUP_MB2_16B_WORD1 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD1")] -pub type Mb16bGroupMb2_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_16B Register"] -pub mod mb_16b_group_mb2_16b_word1; -#[doc = "MB_8B_GROUP_MB3_8B_WORD1 (rw) register accessor: Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb3_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB3_8B_WORD1")] -pub type Mb8bGroupMb3_8bWord1 = crate::Reg; -#[doc = "Message Buffer 3 WORD_8B Register"] -pub mod mb_8b_group_mb3_8b_word1; -#[doc = "MB_GROUP_WORD13 (rw) register accessor: Message Buffer 3 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word13`] module"] -#[doc(alias = "MB_GROUP_WORD13")] -pub type MbGroupWord13 = crate::Reg; -#[doc = "Message Buffer 3 WORD1 Register"] -pub mod mb_group_word13; -#[doc = "MB_GROUP_CS4 (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs4`] module"] -#[doc(alias = "MB_GROUP_CS4")] -pub type MbGroupCs4 = crate::Reg; -#[doc = "Message Buffer 4 CS Register"] -pub mod mb_group_cs4; -#[doc = "MB_64B_GROUP_MB0_64B_WORD14 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word14`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD14")] -pub type Mb64bGroupMb0_64bWord14 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word14; -#[doc = "MB_32B_GROUP_MB1_32B_WORD4 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD4")] -pub type Mb32bGroupMb1_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word4; -#[doc = "MB_16B_GROUP_MB2_16B_WORD2 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD2")] -pub type Mb16bGroupMb2_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_16B Register"] -pub mod mb_16b_group_mb2_16b_word2; -#[doc = "MB_8B_GROUP_MB4_8B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB4_8B_CS")] -pub type Mb8bGroupMb4_8bCs = crate::Reg; -#[doc = "Message Buffer 4 CS Register"] -pub mod mb_8b_group_mb4_8b_cs; -#[doc = "MB_GROUP_ID4 (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id4`] module"] -#[doc(alias = "MB_GROUP_ID4")] -pub type MbGroupId4 = crate::Reg; -#[doc = "Message Buffer 4 ID Register"] -pub mod mb_group_id4; -#[doc = "MB_64B_GROUP_MB0_64B_WORD15 (rw) register accessor: Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb0_64b_word15`] module"] -#[doc(alias = "MB_64B_GROUP_MB0_64B_WORD15")] -pub type Mb64bGroupMb0_64bWord15 = - crate::Reg; -#[doc = "Message Buffer 0 WORD_64B Register"] -pub mod mb_64b_group_mb0_64b_word15; -#[doc = "MB_32B_GROUP_MB1_32B_WORD5 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD5")] -pub type Mb32bGroupMb1_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word5; -#[doc = "MB_16B_GROUP_MB2_16B_WORD3 (rw) register accessor: Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb2_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB2_16B_WORD3")] -pub type Mb16bGroupMb2_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_16B Register"] -pub mod mb_16b_group_mb2_16b_word3; -#[doc = "MB_8B_GROUP_MB4_8B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB4_8B_ID")] -pub type Mb8bGroupMb4_8bId = crate::Reg; -#[doc = "Message Buffer 4 ID Register"] -pub mod mb_8b_group_mb4_8b_id; -#[doc = "MB_32B_GROUP_MB1_32B_WORD6 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD6")] -pub type Mb32bGroupMb1_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word6; -#[doc = "MB_64B_GROUP_MB1_64B_CS (rw) register accessor: Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_cs`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_CS")] -pub type Mb64bGroupMb1_64bCs = crate::Reg; -#[doc = "Message Buffer 1 CS Register"] -pub mod mb_64b_group_mb1_64b_cs; -#[doc = "MB_16B_GROUP_MB3_16B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB3_16B_CS")] -pub type Mb16bGroupMb3_16bCs = crate::Reg; -#[doc = "Message Buffer 3 CS Register"] -pub mod mb_16b_group_mb3_16b_cs; -#[doc = "MB_8B_GROUP_MB4_8B_WORD0 (rw) register accessor: Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB4_8B_WORD0")] -pub type Mb8bGroupMb4_8bWord0 = crate::Reg; -#[doc = "Message Buffer 4 WORD_8B Register"] -pub mod mb_8b_group_mb4_8b_word0; -#[doc = "MB_GROUP_WORD04 (rw) register accessor: Message Buffer 4 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word04::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word04::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word04`] module"] -#[doc(alias = "MB_GROUP_WORD04")] -pub type MbGroupWord04 = crate::Reg; -#[doc = "Message Buffer 4 WORD0 Register"] -pub mod mb_group_word04; -#[doc = "MB_32B_GROUP_MB1_32B_WORD7 (rw) register accessor: Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb1_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB1_32B_WORD7")] -pub type Mb32bGroupMb1_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_32B Register"] -pub mod mb_32b_group_mb1_32b_word7; -#[doc = "MB_64B_GROUP_MB1_64B_ID (rw) register accessor: Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_id`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_ID")] -pub type Mb64bGroupMb1_64bId = crate::Reg; -#[doc = "Message Buffer 1 ID Register"] -pub mod mb_64b_group_mb1_64b_id; -#[doc = "MB_16B_GROUP_MB3_16B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB3_16B_ID")] -pub type Mb16bGroupMb3_16bId = crate::Reg; -#[doc = "Message Buffer 3 ID Register"] -pub mod mb_16b_group_mb3_16b_id; -#[doc = "MB_8B_GROUP_MB4_8B_WORD1 (rw) register accessor: Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb4_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB4_8B_WORD1")] -pub type Mb8bGroupMb4_8bWord1 = crate::Reg; -#[doc = "Message Buffer 4 WORD_8B Register"] -pub mod mb_8b_group_mb4_8b_word1; -#[doc = "MB_GROUP_WORD14 (rw) register accessor: Message Buffer 4 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word14`] module"] -#[doc(alias = "MB_GROUP_WORD14")] -pub type MbGroupWord14 = crate::Reg; -#[doc = "Message Buffer 4 WORD1 Register"] -pub mod mb_group_word14; -#[doc = "MB_GROUP_CS5 (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs5`] module"] -#[doc(alias = "MB_GROUP_CS5")] -pub type MbGroupCs5 = crate::Reg; -#[doc = "Message Buffer 5 CS Register"] -pub mod mb_group_cs5; -#[doc = "MB_64B_GROUP_MB1_64B_WORD0 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word0`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD0")] -pub type Mb64bGroupMb1_64bWord0 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word0; -#[doc = "MB_32B_GROUP_MB2_32B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_CS")] -pub type Mb32bGroupMb2_32bCs = crate::Reg; -#[doc = "Message Buffer 2 CS Register"] -pub mod mb_32b_group_mb2_32b_cs; -#[doc = "MB_16B_GROUP_MB3_16B_WORD0 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD0")] -pub type Mb16bGroupMb3_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_16B Register"] -pub mod mb_16b_group_mb3_16b_word0; -#[doc = "MB_8B_GROUP_MB5_8B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB5_8B_CS")] -pub type Mb8bGroupMb5_8bCs = crate::Reg; -#[doc = "Message Buffer 5 CS Register"] -pub mod mb_8b_group_mb5_8b_cs; -#[doc = "MB_GROUP_ID5 (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id5`] module"] -#[doc(alias = "MB_GROUP_ID5")] -pub type MbGroupId5 = crate::Reg; -#[doc = "Message Buffer 5 ID Register"] -pub mod mb_group_id5; -#[doc = "MB_64B_GROUP_MB1_64B_WORD1 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word1`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD1")] -pub type Mb64bGroupMb1_64bWord1 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word1; -#[doc = "MB_32B_GROUP_MB2_32B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_ID")] -pub type Mb32bGroupMb2_32bId = crate::Reg; -#[doc = "Message Buffer 2 ID Register"] -pub mod mb_32b_group_mb2_32b_id; -#[doc = "MB_16B_GROUP_MB3_16B_WORD1 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD1")] -pub type Mb16bGroupMb3_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_16B Register"] -pub mod mb_16b_group_mb3_16b_word1; -#[doc = "MB_8B_GROUP_MB5_8B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB5_8B_ID")] -pub type Mb8bGroupMb5_8bId = crate::Reg; -#[doc = "Message Buffer 5 ID Register"] -pub mod mb_8b_group_mb5_8b_id; -#[doc = "MB_64B_GROUP_MB1_64B_WORD2 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word2`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD2")] -pub type Mb64bGroupMb1_64bWord2 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word2; -#[doc = "MB_32B_GROUP_MB2_32B_WORD0 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD0")] -pub type Mb32bGroupMb2_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word0; -#[doc = "MB_16B_GROUP_MB3_16B_WORD2 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD2")] -pub type Mb16bGroupMb3_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_16B Register"] -pub mod mb_16b_group_mb3_16b_word2; -#[doc = "MB_8B_GROUP_MB5_8B_WORD0 (rw) register accessor: Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB5_8B_WORD0")] -pub type Mb8bGroupMb5_8bWord0 = crate::Reg; -#[doc = "Message Buffer 5 WORD_8B Register"] -pub mod mb_8b_group_mb5_8b_word0; -#[doc = "MB_GROUP_WORD05 (rw) register accessor: Message Buffer 5 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word05::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word05::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word05`] module"] -#[doc(alias = "MB_GROUP_WORD05")] -pub type MbGroupWord05 = crate::Reg; -#[doc = "Message Buffer 5 WORD0 Register"] -pub mod mb_group_word05; -#[doc = "MB_64B_GROUP_MB1_64B_WORD3 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word3`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD3")] -pub type Mb64bGroupMb1_64bWord3 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word3; -#[doc = "MB_32B_GROUP_MB2_32B_WORD1 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD1")] -pub type Mb32bGroupMb2_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word1; -#[doc = "MB_16B_GROUP_MB3_16B_WORD3 (rw) register accessor: Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb3_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB3_16B_WORD3")] -pub type Mb16bGroupMb3_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_16B Register"] -pub mod mb_16b_group_mb3_16b_word3; -#[doc = "MB_8B_GROUP_MB5_8B_WORD1 (rw) register accessor: Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb5_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB5_8B_WORD1")] -pub type Mb8bGroupMb5_8bWord1 = crate::Reg; -#[doc = "Message Buffer 5 WORD_8B Register"] -pub mod mb_8b_group_mb5_8b_word1; -#[doc = "MB_GROUP_WORD15 (rw) register accessor: Message Buffer 5 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word15`] module"] -#[doc(alias = "MB_GROUP_WORD15")] -pub type MbGroupWord15 = crate::Reg; -#[doc = "Message Buffer 5 WORD1 Register"] -pub mod mb_group_word15; -#[doc = "MB_GROUP_CS6 (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs6`] module"] -#[doc(alias = "MB_GROUP_CS6")] -pub type MbGroupCs6 = crate::Reg; -#[doc = "Message Buffer 6 CS Register"] -pub mod mb_group_cs6; -#[doc = "MB_64B_GROUP_MB1_64B_WORD4 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word4`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD4")] -pub type Mb64bGroupMb1_64bWord4 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word4; -#[doc = "MB_32B_GROUP_MB2_32B_WORD2 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD2")] -pub type Mb32bGroupMb2_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word2; -#[doc = "MB_16B_GROUP_MB4_16B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB4_16B_CS")] -pub type Mb16bGroupMb4_16bCs = crate::Reg; -#[doc = "Message Buffer 4 CS Register"] -pub mod mb_16b_group_mb4_16b_cs; -#[doc = "MB_8B_GROUP_MB6_8B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB6_8B_CS")] -pub type Mb8bGroupMb6_8bCs = crate::Reg; -#[doc = "Message Buffer 6 CS Register"] -pub mod mb_8b_group_mb6_8b_cs; -#[doc = "MB_GROUP_ID6 (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id6`] module"] -#[doc(alias = "MB_GROUP_ID6")] -pub type MbGroupId6 = crate::Reg; -#[doc = "Message Buffer 6 ID Register"] -pub mod mb_group_id6; -#[doc = "MB_64B_GROUP_MB1_64B_WORD5 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word5`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD5")] -pub type Mb64bGroupMb1_64bWord5 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word5; -#[doc = "MB_32B_GROUP_MB2_32B_WORD3 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD3")] -pub type Mb32bGroupMb2_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word3; -#[doc = "MB_16B_GROUP_MB4_16B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB4_16B_ID")] -pub type Mb16bGroupMb4_16bId = crate::Reg; -#[doc = "Message Buffer 4 ID Register"] -pub mod mb_16b_group_mb4_16b_id; -#[doc = "MB_8B_GROUP_MB6_8B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB6_8B_ID")] -pub type Mb8bGroupMb6_8bId = crate::Reg; -#[doc = "Message Buffer 6 ID Register"] -pub mod mb_8b_group_mb6_8b_id; -#[doc = "MB_64B_GROUP_MB1_64B_WORD6 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word6`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD6")] -pub type Mb64bGroupMb1_64bWord6 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word6; -#[doc = "MB_32B_GROUP_MB2_32B_WORD4 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD4")] -pub type Mb32bGroupMb2_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word4; -#[doc = "MB_16B_GROUP_MB4_16B_WORD0 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD0")] -pub type Mb16bGroupMb4_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_16B Register"] -pub mod mb_16b_group_mb4_16b_word0; -#[doc = "MB_8B_GROUP_MB6_8B_WORD0 (rw) register accessor: Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB6_8B_WORD0")] -pub type Mb8bGroupMb6_8bWord0 = crate::Reg; -#[doc = "Message Buffer 6 WORD_8B Register"] -pub mod mb_8b_group_mb6_8b_word0; -#[doc = "MB_GROUP_WORD06 (rw) register accessor: Message Buffer 6 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word06::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word06::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word06`] module"] -#[doc(alias = "MB_GROUP_WORD06")] -pub type MbGroupWord06 = crate::Reg; -#[doc = "Message Buffer 6 WORD0 Register"] -pub mod mb_group_word06; -#[doc = "MB_64B_GROUP_MB1_64B_WORD7 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word7`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD7")] -pub type Mb64bGroupMb1_64bWord7 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word7; -#[doc = "MB_32B_GROUP_MB2_32B_WORD5 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD5")] -pub type Mb32bGroupMb2_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word5; -#[doc = "MB_16B_GROUP_MB4_16B_WORD1 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD1")] -pub type Mb16bGroupMb4_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_16B Register"] -pub mod mb_16b_group_mb4_16b_word1; -#[doc = "MB_8B_GROUP_MB6_8B_WORD1 (rw) register accessor: Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb6_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB6_8B_WORD1")] -pub type Mb8bGroupMb6_8bWord1 = crate::Reg; -#[doc = "Message Buffer 6 WORD_8B Register"] -pub mod mb_8b_group_mb6_8b_word1; -#[doc = "MB_GROUP_WORD16 (rw) register accessor: Message Buffer 6 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word16`] module"] -#[doc(alias = "MB_GROUP_WORD16")] -pub type MbGroupWord16 = crate::Reg; -#[doc = "Message Buffer 6 WORD1 Register"] -pub mod mb_group_word16; -#[doc = "MB_GROUP_CS7 (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs7`] module"] -#[doc(alias = "MB_GROUP_CS7")] -pub type MbGroupCs7 = crate::Reg; -#[doc = "Message Buffer 7 CS Register"] -pub mod mb_group_cs7; -#[doc = "MB_64B_GROUP_MB1_64B_WORD8 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word8`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD8")] -pub type Mb64bGroupMb1_64bWord8 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word8; -#[doc = "MB_32B_GROUP_MB2_32B_WORD6 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD6")] -pub type Mb32bGroupMb2_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word6; -#[doc = "MB_16B_GROUP_MB4_16B_WORD2 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD2")] -pub type Mb16bGroupMb4_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_16B Register"] -pub mod mb_16b_group_mb4_16b_word2; -#[doc = "MB_8B_GROUP_MB7_8B_CS (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB7_8B_CS")] -pub type Mb8bGroupMb7_8bCs = crate::Reg; -#[doc = "Message Buffer 7 CS Register"] -pub mod mb_8b_group_mb7_8b_cs; -#[doc = "MB_GROUP_ID7 (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id7`] module"] -#[doc(alias = "MB_GROUP_ID7")] -pub type MbGroupId7 = crate::Reg; -#[doc = "Message Buffer 7 ID Register"] -pub mod mb_group_id7; -#[doc = "MB_64B_GROUP_MB1_64B_WORD9 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word9`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD9")] -pub type Mb64bGroupMb1_64bWord9 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word9; -#[doc = "MB_32B_GROUP_MB2_32B_WORD7 (rw) register accessor: Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb2_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB2_32B_WORD7")] -pub type Mb32bGroupMb2_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_32B Register"] -pub mod mb_32b_group_mb2_32b_word7; -#[doc = "MB_16B_GROUP_MB4_16B_WORD3 (rw) register accessor: Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb4_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB4_16B_WORD3")] -pub type Mb16bGroupMb4_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_16B Register"] -pub mod mb_16b_group_mb4_16b_word3; -#[doc = "MB_8B_GROUP_MB7_8B_ID (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB7_8B_ID")] -pub type Mb8bGroupMb7_8bId = crate::Reg; -#[doc = "Message Buffer 7 ID Register"] -pub mod mb_8b_group_mb7_8b_id; -#[doc = "MB_64B_GROUP_MB1_64B_WORD10 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word10`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD10")] -pub type Mb64bGroupMb1_64bWord10 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word10; -#[doc = "MB_32B_GROUP_MB3_32B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_CS")] -pub type Mb32bGroupMb3_32bCs = crate::Reg; -#[doc = "Message Buffer 3 CS Register"] -pub mod mb_32b_group_mb3_32b_cs; -#[doc = "MB_16B_GROUP_MB5_16B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB5_16B_CS")] -pub type Mb16bGroupMb5_16bCs = crate::Reg; -#[doc = "Message Buffer 5 CS Register"] -pub mod mb_16b_group_mb5_16b_cs; -#[doc = "MB_8B_GROUP_MB7_8B_WORD0 (rw) register accessor: Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB7_8B_WORD0")] -pub type Mb8bGroupMb7_8bWord0 = crate::Reg; -#[doc = "Message Buffer 7 WORD_8B Register"] -pub mod mb_8b_group_mb7_8b_word0; -#[doc = "MB_GROUP_WORD07 (rw) register accessor: Message Buffer 7 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word07::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word07::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word07`] module"] -#[doc(alias = "MB_GROUP_WORD07")] -pub type MbGroupWord07 = crate::Reg; -#[doc = "Message Buffer 7 WORD0 Register"] -pub mod mb_group_word07; -#[doc = "MB_64B_GROUP_MB1_64B_WORD11 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word11`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD11")] -pub type Mb64bGroupMb1_64bWord11 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word11; -#[doc = "MB_32B_GROUP_MB3_32B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_ID")] -pub type Mb32bGroupMb3_32bId = crate::Reg; -#[doc = "Message Buffer 3 ID Register"] -pub mod mb_32b_group_mb3_32b_id; -#[doc = "MB_16B_GROUP_MB5_16B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB5_16B_ID")] -pub type Mb16bGroupMb5_16bId = crate::Reg; -#[doc = "Message Buffer 5 ID Register"] -pub mod mb_16b_group_mb5_16b_id; -#[doc = "MB_8B_GROUP_MB7_8B_WORD1 (rw) register accessor: Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb7_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB7_8B_WORD1")] -pub type Mb8bGroupMb7_8bWord1 = crate::Reg; -#[doc = "Message Buffer 7 WORD_8B Register"] -pub mod mb_8b_group_mb7_8b_word1; -#[doc = "MB_GROUP_WORD17 (rw) register accessor: Message Buffer 7 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word17`] module"] -#[doc(alias = "MB_GROUP_WORD17")] -pub type MbGroupWord17 = crate::Reg; -#[doc = "Message Buffer 7 WORD1 Register"] -pub mod mb_group_word17; -#[doc = "MB_GROUP_CS8 (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs8`] module"] -#[doc(alias = "MB_GROUP_CS8")] -pub type MbGroupCs8 = crate::Reg; -#[doc = "Message Buffer 8 CS Register"] -pub mod mb_group_cs8; -#[doc = "MB_64B_GROUP_MB1_64B_WORD12 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word12`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD12")] -pub type Mb64bGroupMb1_64bWord12 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word12; -#[doc = "MB_32B_GROUP_MB3_32B_WORD0 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD0")] -pub type Mb32bGroupMb3_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word0; -#[doc = "MB_16B_GROUP_MB5_16B_WORD0 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD0")] -pub type Mb16bGroupMb5_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_16B Register"] -pub mod mb_16b_group_mb5_16b_word0; -#[doc = "MB_8B_GROUP_MB8_8B_CS (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB8_8B_CS")] -pub type Mb8bGroupMb8_8bCs = crate::Reg; -#[doc = "Message Buffer 8 CS Register"] -pub mod mb_8b_group_mb8_8b_cs; -#[doc = "MB_GROUP_ID8 (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id8`] module"] -#[doc(alias = "MB_GROUP_ID8")] -pub type MbGroupId8 = crate::Reg; -#[doc = "Message Buffer 8 ID Register"] -pub mod mb_group_id8; -#[doc = "MB_64B_GROUP_MB1_64B_WORD13 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word13`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD13")] -pub type Mb64bGroupMb1_64bWord13 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word13; -#[doc = "MB_32B_GROUP_MB3_32B_WORD1 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD1")] -pub type Mb32bGroupMb3_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word1; -#[doc = "MB_16B_GROUP_MB5_16B_WORD1 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD1")] -pub type Mb16bGroupMb5_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_16B Register"] -pub mod mb_16b_group_mb5_16b_word1; -#[doc = "MB_8B_GROUP_MB8_8B_ID (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB8_8B_ID")] -pub type Mb8bGroupMb8_8bId = crate::Reg; -#[doc = "Message Buffer 8 ID Register"] -pub mod mb_8b_group_mb8_8b_id; -#[doc = "MB_64B_GROUP_MB1_64B_WORD14 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word14`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD14")] -pub type Mb64bGroupMb1_64bWord14 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word14; -#[doc = "MB_32B_GROUP_MB3_32B_WORD2 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD2")] -pub type Mb32bGroupMb3_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word2; -#[doc = "MB_16B_GROUP_MB5_16B_WORD2 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD2")] -pub type Mb16bGroupMb5_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_16B Register"] -pub mod mb_16b_group_mb5_16b_word2; -#[doc = "MB_8B_GROUP_MB8_8B_WORD0 (rw) register accessor: Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB8_8B_WORD0")] -pub type Mb8bGroupMb8_8bWord0 = crate::Reg; -#[doc = "Message Buffer 8 WORD_8B Register"] -pub mod mb_8b_group_mb8_8b_word0; -#[doc = "MB_GROUP_WORD08 (rw) register accessor: Message Buffer 8 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word08::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word08::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word08`] module"] -#[doc(alias = "MB_GROUP_WORD08")] -pub type MbGroupWord08 = crate::Reg; -#[doc = "Message Buffer 8 WORD0 Register"] -pub mod mb_group_word08; -#[doc = "MB_64B_GROUP_MB1_64B_WORD15 (rw) register accessor: Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb1_64b_word15`] module"] -#[doc(alias = "MB_64B_GROUP_MB1_64B_WORD15")] -pub type Mb64bGroupMb1_64bWord15 = - crate::Reg; -#[doc = "Message Buffer 1 WORD_64B Register"] -pub mod mb_64b_group_mb1_64b_word15; -#[doc = "MB_32B_GROUP_MB3_32B_WORD3 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD3")] -pub type Mb32bGroupMb3_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word3; -#[doc = "MB_16B_GROUP_MB5_16B_WORD3 (rw) register accessor: Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb5_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB5_16B_WORD3")] -pub type Mb16bGroupMb5_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_16B Register"] -pub mod mb_16b_group_mb5_16b_word3; -#[doc = "MB_8B_GROUP_MB8_8B_WORD1 (rw) register accessor: Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb8_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB8_8B_WORD1")] -pub type Mb8bGroupMb8_8bWord1 = crate::Reg; -#[doc = "Message Buffer 8 WORD_8B Register"] -pub mod mb_8b_group_mb8_8b_word1; -#[doc = "MB_GROUP_WORD18 (rw) register accessor: Message Buffer 8 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word18`] module"] -#[doc(alias = "MB_GROUP_WORD18")] -pub type MbGroupWord18 = crate::Reg; -#[doc = "Message Buffer 8 WORD1 Register"] -pub mod mb_group_word18; -#[doc = "MB_GROUP_CS9 (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs9`] module"] -#[doc(alias = "MB_GROUP_CS9")] -pub type MbGroupCs9 = crate::Reg; -#[doc = "Message Buffer 9 CS Register"] -pub mod mb_group_cs9; -#[doc = "MB_64B_GROUP_MB2_64B_CS (rw) register accessor: Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_cs`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_CS")] -pub type Mb64bGroupMb2_64bCs = crate::Reg; -#[doc = "Message Buffer 2 CS Register"] -pub mod mb_64b_group_mb2_64b_cs; -#[doc = "MB_32B_GROUP_MB3_32B_WORD4 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD4")] -pub type Mb32bGroupMb3_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word4; -#[doc = "MB_16B_GROUP_MB6_16B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB6_16B_CS")] -pub type Mb16bGroupMb6_16bCs = crate::Reg; -#[doc = "Message Buffer 6 CS Register"] -pub mod mb_16b_group_mb6_16b_cs; -#[doc = "MB_8B_GROUP_MB9_8B_CS (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB9_8B_CS")] -pub type Mb8bGroupMb9_8bCs = crate::Reg; -#[doc = "Message Buffer 9 CS Register"] -pub mod mb_8b_group_mb9_8b_cs; -#[doc = "MB_GROUP_ID9 (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id9`] module"] -#[doc(alias = "MB_GROUP_ID9")] -pub type MbGroupId9 = crate::Reg; -#[doc = "Message Buffer 9 ID Register"] -pub mod mb_group_id9; -#[doc = "MB_64B_GROUP_MB2_64B_ID (rw) register accessor: Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_id`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_ID")] -pub type Mb64bGroupMb2_64bId = crate::Reg; -#[doc = "Message Buffer 2 ID Register"] -pub mod mb_64b_group_mb2_64b_id; -#[doc = "MB_32B_GROUP_MB3_32B_WORD5 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD5")] -pub type Mb32bGroupMb3_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word5; -#[doc = "MB_16B_GROUP_MB6_16B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB6_16B_ID")] -pub type Mb16bGroupMb6_16bId = crate::Reg; -#[doc = "Message Buffer 6 ID Register"] -pub mod mb_16b_group_mb6_16b_id; -#[doc = "MB_8B_GROUP_MB9_8B_ID (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB9_8B_ID")] -pub type Mb8bGroupMb9_8bId = crate::Reg; -#[doc = "Message Buffer 9 ID Register"] -pub mod mb_8b_group_mb9_8b_id; -#[doc = "MB_64B_GROUP_MB2_64B_WORD0 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word0`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD0")] -pub type Mb64bGroupMb2_64bWord0 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word0; -#[doc = "MB_32B_GROUP_MB3_32B_WORD6 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD6")] -pub type Mb32bGroupMb3_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word6; -#[doc = "MB_16B_GROUP_MB6_16B_WORD0 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD0")] -pub type Mb16bGroupMb6_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_16B Register"] -pub mod mb_16b_group_mb6_16b_word0; -#[doc = "MB_8B_GROUP_MB9_8B_WORD0 (rw) register accessor: Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB9_8B_WORD0")] -pub type Mb8bGroupMb9_8bWord0 = crate::Reg; -#[doc = "Message Buffer 9 WORD_8B Register"] -pub mod mb_8b_group_mb9_8b_word0; -#[doc = "MB_GROUP_WORD09 (rw) register accessor: Message Buffer 9 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word09::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word09::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word09`] module"] -#[doc(alias = "MB_GROUP_WORD09")] -pub type MbGroupWord09 = crate::Reg; -#[doc = "Message Buffer 9 WORD0 Register"] -pub mod mb_group_word09; -#[doc = "MB_64B_GROUP_MB2_64B_WORD1 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word1`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD1")] -pub type Mb64bGroupMb2_64bWord1 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word1; -#[doc = "MB_32B_GROUP_MB3_32B_WORD7 (rw) register accessor: Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb3_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB3_32B_WORD7")] -pub type Mb32bGroupMb3_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_32B Register"] -pub mod mb_32b_group_mb3_32b_word7; -#[doc = "MB_16B_GROUP_MB6_16B_WORD1 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD1")] -pub type Mb16bGroupMb6_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_16B Register"] -pub mod mb_16b_group_mb6_16b_word1; -#[doc = "MB_8B_GROUP_MB9_8B_WORD1 (rw) register accessor: Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb9_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB9_8B_WORD1")] -pub type Mb8bGroupMb9_8bWord1 = crate::Reg; -#[doc = "Message Buffer 9 WORD_8B Register"] -pub mod mb_8b_group_mb9_8b_word1; -#[doc = "MB_GROUP_WORD19 (rw) register accessor: Message Buffer 9 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word19`] module"] -#[doc(alias = "MB_GROUP_WORD19")] -pub type MbGroupWord19 = crate::Reg; -#[doc = "Message Buffer 9 WORD1 Register"] -pub mod mb_group_word19; -#[doc = "MB_GROUP_CS10 (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs10`] module"] -#[doc(alias = "MB_GROUP_CS10")] -pub type MbGroupCs10 = crate::Reg; -#[doc = "Message Buffer 10 CS Register"] -pub mod mb_group_cs10; -#[doc = "MB_8B_GROUP_MB10_8B_CS (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB10_8B_CS")] -pub type Mb8bGroupMb10_8bCs = crate::Reg; -#[doc = "Message Buffer 10 CS Register"] -pub mod mb_8b_group_mb10_8b_cs; -#[doc = "MB_64B_GROUP_MB2_64B_WORD2 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word2`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD2")] -pub type Mb64bGroupMb2_64bWord2 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word2; -#[doc = "MB_32B_GROUP_MB4_32B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_CS")] -pub type Mb32bGroupMb4_32bCs = crate::Reg; -#[doc = "Message Buffer 4 CS Register"] -pub mod mb_32b_group_mb4_32b_cs; -#[doc = "MB_16B_GROUP_MB6_16B_WORD2 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD2")] -pub type Mb16bGroupMb6_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_16B Register"] -pub mod mb_16b_group_mb6_16b_word2; -#[doc = "MB_GROUP_ID10 (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id10`] module"] -#[doc(alias = "MB_GROUP_ID10")] -pub type MbGroupId10 = crate::Reg; -#[doc = "Message Buffer 10 ID Register"] -pub mod mb_group_id10; -#[doc = "MB_8B_GROUP_MB10_8B_ID (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB10_8B_ID")] -pub type Mb8bGroupMb10_8bId = crate::Reg; -#[doc = "Message Buffer 10 ID Register"] -pub mod mb_8b_group_mb10_8b_id; -#[doc = "MB_64B_GROUP_MB2_64B_WORD3 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word3`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD3")] -pub type Mb64bGroupMb2_64bWord3 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word3; -#[doc = "MB_32B_GROUP_MB4_32B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_ID")] -pub type Mb32bGroupMb4_32bId = crate::Reg; -#[doc = "Message Buffer 4 ID Register"] -pub mod mb_32b_group_mb4_32b_id; -#[doc = "MB_16B_GROUP_MB6_16B_WORD3 (rw) register accessor: Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb6_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB6_16B_WORD3")] -pub type Mb16bGroupMb6_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_16B Register"] -pub mod mb_16b_group_mb6_16b_word3; -#[doc = "MB_8B_GROUP_MB10_8B_WORD0 (rw) register accessor: Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB10_8B_WORD0")] -pub type Mb8bGroupMb10_8bWord0 = crate::Reg; -#[doc = "Message Buffer 10 WORD_8B Register"] -pub mod mb_8b_group_mb10_8b_word0; -#[doc = "MB_64B_GROUP_MB2_64B_WORD4 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word4`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD4")] -pub type Mb64bGroupMb2_64bWord4 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word4; -#[doc = "MB_32B_GROUP_MB4_32B_WORD0 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD0")] -pub type Mb32bGroupMb4_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word0; -#[doc = "MB_16B_GROUP_MB7_16B_CS (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB7_16B_CS")] -pub type Mb16bGroupMb7_16bCs = crate::Reg; -#[doc = "Message Buffer 7 CS Register"] -pub mod mb_16b_group_mb7_16b_cs; -#[doc = "MB_GROUP_WORD010 (rw) register accessor: Message Buffer 10 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word010::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word010::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word010`] module"] -#[doc(alias = "MB_GROUP_WORD010")] -pub type MbGroupWord010 = crate::Reg; -#[doc = "Message Buffer 10 WORD0 Register"] -pub mod mb_group_word010; -#[doc = "MB_8B_GROUP_MB10_8B_WORD1 (rw) register accessor: Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb10_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB10_8B_WORD1")] -pub type Mb8bGroupMb10_8bWord1 = crate::Reg; -#[doc = "Message Buffer 10 WORD_8B Register"] -pub mod mb_8b_group_mb10_8b_word1; -#[doc = "MB_64B_GROUP_MB2_64B_WORD5 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word5`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD5")] -pub type Mb64bGroupMb2_64bWord5 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word5; -#[doc = "MB_32B_GROUP_MB4_32B_WORD1 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD1")] -pub type Mb32bGroupMb4_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word1; -#[doc = "MB_16B_GROUP_MB7_16B_ID (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB7_16B_ID")] -pub type Mb16bGroupMb7_16bId = crate::Reg; -#[doc = "Message Buffer 7 ID Register"] -pub mod mb_16b_group_mb7_16b_id; -#[doc = "MB_GROUP_WORD110 (rw) register accessor: Message Buffer 10 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word110::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word110::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word110`] module"] -#[doc(alias = "MB_GROUP_WORD110")] -pub type MbGroupWord110 = crate::Reg; -#[doc = "Message Buffer 10 WORD1 Register"] -pub mod mb_group_word110; -#[doc = "MB_GROUP_CS11 (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs11`] module"] -#[doc(alias = "MB_GROUP_CS11")] -pub type MbGroupCs11 = crate::Reg; -#[doc = "Message Buffer 11 CS Register"] -pub mod mb_group_cs11; -#[doc = "MB_8B_GROUP_MB11_8B_CS (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB11_8B_CS")] -pub type Mb8bGroupMb11_8bCs = crate::Reg; -#[doc = "Message Buffer 11 CS Register"] -pub mod mb_8b_group_mb11_8b_cs; -#[doc = "MB_64B_GROUP_MB2_64B_WORD6 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word6`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD6")] -pub type Mb64bGroupMb2_64bWord6 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word6; -#[doc = "MB_32B_GROUP_MB4_32B_WORD2 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD2")] -pub type Mb32bGroupMb4_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word2; -#[doc = "MB_16B_GROUP_MB7_16B_WORD0 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD0")] -pub type Mb16bGroupMb7_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_16B Register"] -pub mod mb_16b_group_mb7_16b_word0; -#[doc = "MB_GROUP_ID11 (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id11`] module"] -#[doc(alias = "MB_GROUP_ID11")] -pub type MbGroupId11 = crate::Reg; -#[doc = "Message Buffer 11 ID Register"] -pub mod mb_group_id11; -#[doc = "MB_8B_GROUP_MB11_8B_ID (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB11_8B_ID")] -pub type Mb8bGroupMb11_8bId = crate::Reg; -#[doc = "Message Buffer 11 ID Register"] -pub mod mb_8b_group_mb11_8b_id; -#[doc = "MB_64B_GROUP_MB2_64B_WORD7 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word7`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD7")] -pub type Mb64bGroupMb2_64bWord7 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word7; -#[doc = "MB_32B_GROUP_MB4_32B_WORD3 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD3")] -pub type Mb32bGroupMb4_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word3; -#[doc = "MB_16B_GROUP_MB7_16B_WORD1 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD1")] -pub type Mb16bGroupMb7_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_16B Register"] -pub mod mb_16b_group_mb7_16b_word1; -#[doc = "MB_8B_GROUP_MB11_8B_WORD0 (rw) register accessor: Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB11_8B_WORD0")] -pub type Mb8bGroupMb11_8bWord0 = crate::Reg; -#[doc = "Message Buffer 11 WORD_8B Register"] -pub mod mb_8b_group_mb11_8b_word0; -#[doc = "MB_64B_GROUP_MB2_64B_WORD8 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word8`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD8")] -pub type Mb64bGroupMb2_64bWord8 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word8; -#[doc = "MB_32B_GROUP_MB4_32B_WORD4 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD4")] -pub type Mb32bGroupMb4_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word4; -#[doc = "MB_16B_GROUP_MB7_16B_WORD2 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD2")] -pub type Mb16bGroupMb7_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_16B Register"] -pub mod mb_16b_group_mb7_16b_word2; -#[doc = "MB_GROUP_WORD011 (rw) register accessor: Message Buffer 11 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word011::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word011::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word011`] module"] -#[doc(alias = "MB_GROUP_WORD011")] -pub type MbGroupWord011 = crate::Reg; -#[doc = "Message Buffer 11 WORD0 Register"] -pub mod mb_group_word011; -#[doc = "MB_8B_GROUP_MB11_8B_WORD1 (rw) register accessor: Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb11_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB11_8B_WORD1")] -pub type Mb8bGroupMb11_8bWord1 = crate::Reg; -#[doc = "Message Buffer 11 WORD_8B Register"] -pub mod mb_8b_group_mb11_8b_word1; -#[doc = "MB_64B_GROUP_MB2_64B_WORD9 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word9`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD9")] -pub type Mb64bGroupMb2_64bWord9 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word9; -#[doc = "MB_32B_GROUP_MB4_32B_WORD5 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD5")] -pub type Mb32bGroupMb4_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word5; -#[doc = "MB_16B_GROUP_MB7_16B_WORD3 (rw) register accessor: Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb7_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB7_16B_WORD3")] -pub type Mb16bGroupMb7_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_16B Register"] -pub mod mb_16b_group_mb7_16b_word3; -#[doc = "MB_GROUP_WORD111 (rw) register accessor: Message Buffer 11 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word111::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word111::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word111`] module"] -#[doc(alias = "MB_GROUP_WORD111")] -pub type MbGroupWord111 = crate::Reg; -#[doc = "Message Buffer 11 WORD1 Register"] -pub mod mb_group_word111; -#[doc = "MB_GROUP_CS12 (rw) register accessor: Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs12`] module"] -#[doc(alias = "MB_GROUP_CS12")] -pub type MbGroupCs12 = crate::Reg; -#[doc = "Message Buffer 12 CS Register"] -pub mod mb_group_cs12; -#[doc = "MB_8B_GROUP_MB12_8B_CS (rw) register accessor: Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB12_8B_CS")] -pub type Mb8bGroupMb12_8bCs = crate::Reg; -#[doc = "Message Buffer 12 CS Register"] -pub mod mb_8b_group_mb12_8b_cs; -#[doc = "MB_64B_GROUP_MB2_64B_WORD10 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word10`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD10")] -pub type Mb64bGroupMb2_64bWord10 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word10; -#[doc = "MB_32B_GROUP_MB4_32B_WORD6 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD6")] -pub type Mb32bGroupMb4_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word6; -#[doc = "MB_16B_GROUP_MB8_16B_CS (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB8_16B_CS")] -pub type Mb16bGroupMb8_16bCs = crate::Reg; -#[doc = "Message Buffer 8 CS Register"] -pub mod mb_16b_group_mb8_16b_cs; -#[doc = "MB_GROUP_ID12 (rw) register accessor: Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id12`] module"] -#[doc(alias = "MB_GROUP_ID12")] -pub type MbGroupId12 = crate::Reg; -#[doc = "Message Buffer 12 ID Register"] -pub mod mb_group_id12; -#[doc = "MB_8B_GROUP_MB12_8B_ID (rw) register accessor: Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB12_8B_ID")] -pub type Mb8bGroupMb12_8bId = crate::Reg; -#[doc = "Message Buffer 12 ID Register"] -pub mod mb_8b_group_mb12_8b_id; -#[doc = "MB_64B_GROUP_MB2_64B_WORD11 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word11`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD11")] -pub type Mb64bGroupMb2_64bWord11 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word11; -#[doc = "MB_32B_GROUP_MB4_32B_WORD7 (rw) register accessor: Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb4_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB4_32B_WORD7")] -pub type Mb32bGroupMb4_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_32B Register"] -pub mod mb_32b_group_mb4_32b_word7; -#[doc = "MB_16B_GROUP_MB8_16B_ID (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB8_16B_ID")] -pub type Mb16bGroupMb8_16bId = crate::Reg; -#[doc = "Message Buffer 8 ID Register"] -pub mod mb_16b_group_mb8_16b_id; -#[doc = "MB_8B_GROUP_MB12_8B_WORD0 (rw) register accessor: Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB12_8B_WORD0")] -pub type Mb8bGroupMb12_8bWord0 = crate::Reg; -#[doc = "Message Buffer 12 WORD_8B Register"] -pub mod mb_8b_group_mb12_8b_word0; -#[doc = "MB_64B_GROUP_MB2_64B_WORD12 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word12`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD12")] -pub type Mb64bGroupMb2_64bWord12 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word12; -#[doc = "MB_32B_GROUP_MB5_32B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_CS")] -pub type Mb32bGroupMb5_32bCs = crate::Reg; -#[doc = "Message Buffer 5 CS Register"] -pub mod mb_32b_group_mb5_32b_cs; -#[doc = "MB_16B_GROUP_MB8_16B_WORD0 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD0")] -pub type Mb16bGroupMb8_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_16B Register"] -pub mod mb_16b_group_mb8_16b_word0; -#[doc = "MB_GROUP_WORD012 (rw) register accessor: Message Buffer 12 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word012::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word012::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word012`] module"] -#[doc(alias = "MB_GROUP_WORD012")] -pub type MbGroupWord012 = crate::Reg; -#[doc = "Message Buffer 12 WORD0 Register"] -pub mod mb_group_word012; -#[doc = "MB_8B_GROUP_MB12_8B_WORD1 (rw) register accessor: Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb12_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB12_8B_WORD1")] -pub type Mb8bGroupMb12_8bWord1 = crate::Reg; -#[doc = "Message Buffer 12 WORD_8B Register"] -pub mod mb_8b_group_mb12_8b_word1; -#[doc = "MB_64B_GROUP_MB2_64B_WORD13 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word13`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD13")] -pub type Mb64bGroupMb2_64bWord13 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word13; -#[doc = "MB_32B_GROUP_MB5_32B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_ID")] -pub type Mb32bGroupMb5_32bId = crate::Reg; -#[doc = "Message Buffer 5 ID Register"] -pub mod mb_32b_group_mb5_32b_id; -#[doc = "MB_16B_GROUP_MB8_16B_WORD1 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD1")] -pub type Mb16bGroupMb8_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_16B Register"] -pub mod mb_16b_group_mb8_16b_word1; -#[doc = "MB_GROUP_WORD112 (rw) register accessor: Message Buffer 12 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word112::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word112::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word112`] module"] -#[doc(alias = "MB_GROUP_WORD112")] -pub type MbGroupWord112 = crate::Reg; -#[doc = "Message Buffer 12 WORD1 Register"] -pub mod mb_group_word112; -#[doc = "MB_GROUP_CS13 (rw) register accessor: Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs13`] module"] -#[doc(alias = "MB_GROUP_CS13")] -pub type MbGroupCs13 = crate::Reg; -#[doc = "Message Buffer 13 CS Register"] -pub mod mb_group_cs13; -#[doc = "MB_8B_GROUP_MB13_8B_CS (rw) register accessor: Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB13_8B_CS")] -pub type Mb8bGroupMb13_8bCs = crate::Reg; -#[doc = "Message Buffer 13 CS Register"] -pub mod mb_8b_group_mb13_8b_cs; -#[doc = "MB_64B_GROUP_MB2_64B_WORD14 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word14`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD14")] -pub type Mb64bGroupMb2_64bWord14 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word14; -#[doc = "MB_32B_GROUP_MB5_32B_WORD0 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD0")] -pub type Mb32bGroupMb5_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word0; -#[doc = "MB_16B_GROUP_MB8_16B_WORD2 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD2")] -pub type Mb16bGroupMb8_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_16B Register"] -pub mod mb_16b_group_mb8_16b_word2; -#[doc = "MB_GROUP_ID13 (rw) register accessor: Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id13`] module"] -#[doc(alias = "MB_GROUP_ID13")] -pub type MbGroupId13 = crate::Reg; -#[doc = "Message Buffer 13 ID Register"] -pub mod mb_group_id13; -#[doc = "MB_8B_GROUP_MB13_8B_ID (rw) register accessor: Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB13_8B_ID")] -pub type Mb8bGroupMb13_8bId = crate::Reg; -#[doc = "Message Buffer 13 ID Register"] -pub mod mb_8b_group_mb13_8b_id; -#[doc = "MB_64B_GROUP_MB2_64B_WORD15 (rw) register accessor: Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb2_64b_word15`] module"] -#[doc(alias = "MB_64B_GROUP_MB2_64B_WORD15")] -pub type Mb64bGroupMb2_64bWord15 = - crate::Reg; -#[doc = "Message Buffer 2 WORD_64B Register"] -pub mod mb_64b_group_mb2_64b_word15; -#[doc = "MB_32B_GROUP_MB5_32B_WORD1 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD1")] -pub type Mb32bGroupMb5_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word1; -#[doc = "MB_16B_GROUP_MB8_16B_WORD3 (rw) register accessor: Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb8_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB8_16B_WORD3")] -pub type Mb16bGroupMb8_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_16B Register"] -pub mod mb_16b_group_mb8_16b_word3; -#[doc = "MB_8B_GROUP_MB13_8B_WORD0 (rw) register accessor: Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB13_8B_WORD0")] -pub type Mb8bGroupMb13_8bWord0 = crate::Reg; -#[doc = "Message Buffer 13 WORD_8B Register"] -pub mod mb_8b_group_mb13_8b_word0; -#[doc = "MB_64B_GROUP_MB3_64B_CS (rw) register accessor: Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_cs`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_CS")] -pub type Mb64bGroupMb3_64bCs = crate::Reg; -#[doc = "Message Buffer 3 CS Register"] -pub mod mb_64b_group_mb3_64b_cs; -#[doc = "MB_32B_GROUP_MB5_32B_WORD2 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD2")] -pub type Mb32bGroupMb5_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word2; -#[doc = "MB_16B_GROUP_MB9_16B_CS (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB9_16B_CS")] -pub type Mb16bGroupMb9_16bCs = crate::Reg; -#[doc = "Message Buffer 9 CS Register"] -pub mod mb_16b_group_mb9_16b_cs; -#[doc = "MB_GROUP_WORD013 (rw) register accessor: Message Buffer 13 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word013::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word013::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word013`] module"] -#[doc(alias = "MB_GROUP_WORD013")] -pub type MbGroupWord013 = crate::Reg; -#[doc = "Message Buffer 13 WORD0 Register"] -pub mod mb_group_word013; -#[doc = "MB_8B_GROUP_MB13_8B_WORD1 (rw) register accessor: Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb13_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB13_8B_WORD1")] -pub type Mb8bGroupMb13_8bWord1 = crate::Reg; -#[doc = "Message Buffer 13 WORD_8B Register"] -pub mod mb_8b_group_mb13_8b_word1; -#[doc = "MB_64B_GROUP_MB3_64B_ID (rw) register accessor: Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_id`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_ID")] -pub type Mb64bGroupMb3_64bId = crate::Reg; -#[doc = "Message Buffer 3 ID Register"] -pub mod mb_64b_group_mb3_64b_id; -#[doc = "MB_32B_GROUP_MB5_32B_WORD3 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD3")] -pub type Mb32bGroupMb5_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word3; -#[doc = "MB_16B_GROUP_MB9_16B_ID (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB9_16B_ID")] -pub type Mb16bGroupMb9_16bId = crate::Reg; -#[doc = "Message Buffer 9 ID Register"] -pub mod mb_16b_group_mb9_16b_id; -#[doc = "MB_GROUP_WORD113 (rw) register accessor: Message Buffer 13 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word113::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word113::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word113`] module"] -#[doc(alias = "MB_GROUP_WORD113")] -pub type MbGroupWord113 = crate::Reg; -#[doc = "Message Buffer 13 WORD1 Register"] -pub mod mb_group_word113; -#[doc = "MB_GROUP_CS14 (rw) register accessor: Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs14`] module"] -#[doc(alias = "MB_GROUP_CS14")] -pub type MbGroupCs14 = crate::Reg; -#[doc = "Message Buffer 14 CS Register"] -pub mod mb_group_cs14; -#[doc = "MB_8B_GROUP_MB14_8B_CS (rw) register accessor: Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB14_8B_CS")] -pub type Mb8bGroupMb14_8bCs = crate::Reg; -#[doc = "Message Buffer 14 CS Register"] -pub mod mb_8b_group_mb14_8b_cs; -#[doc = "MB_64B_GROUP_MB3_64B_WORD0 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word0`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD0")] -pub type Mb64bGroupMb3_64bWord0 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word0; -#[doc = "MB_32B_GROUP_MB5_32B_WORD4 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD4")] -pub type Mb32bGroupMb5_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word4; -#[doc = "MB_16B_GROUP_MB9_16B_WORD0 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD0")] -pub type Mb16bGroupMb9_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_16B Register"] -pub mod mb_16b_group_mb9_16b_word0; -#[doc = "MB_GROUP_ID14 (rw) register accessor: Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id14`] module"] -#[doc(alias = "MB_GROUP_ID14")] -pub type MbGroupId14 = crate::Reg; -#[doc = "Message Buffer 14 ID Register"] -pub mod mb_group_id14; -#[doc = "MB_8B_GROUP_MB14_8B_ID (rw) register accessor: Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB14_8B_ID")] -pub type Mb8bGroupMb14_8bId = crate::Reg; -#[doc = "Message Buffer 14 ID Register"] -pub mod mb_8b_group_mb14_8b_id; -#[doc = "MB_64B_GROUP_MB3_64B_WORD1 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word1`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD1")] -pub type Mb64bGroupMb3_64bWord1 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word1; -#[doc = "MB_32B_GROUP_MB5_32B_WORD5 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD5")] -pub type Mb32bGroupMb5_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word5; -#[doc = "MB_16B_GROUP_MB9_16B_WORD1 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD1")] -pub type Mb16bGroupMb9_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_16B Register"] -pub mod mb_16b_group_mb9_16b_word1; -#[doc = "MB_8B_GROUP_MB14_8B_WORD0 (rw) register accessor: Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB14_8B_WORD0")] -pub type Mb8bGroupMb14_8bWord0 = crate::Reg; -#[doc = "Message Buffer 14 WORD_8B Register"] -pub mod mb_8b_group_mb14_8b_word0; -#[doc = "MB_64B_GROUP_MB3_64B_WORD2 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word2`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD2")] -pub type Mb64bGroupMb3_64bWord2 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word2; -#[doc = "MB_32B_GROUP_MB5_32B_WORD6 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD6")] -pub type Mb32bGroupMb5_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word6; -#[doc = "MB_16B_GROUP_MB9_16B_WORD2 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD2")] -pub type Mb16bGroupMb9_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_16B Register"] -pub mod mb_16b_group_mb9_16b_word2; -#[doc = "MB_GROUP_WORD014 (rw) register accessor: Message Buffer 14 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word014::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word014::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word014`] module"] -#[doc(alias = "MB_GROUP_WORD014")] -pub type MbGroupWord014 = crate::Reg; -#[doc = "Message Buffer 14 WORD0 Register"] -pub mod mb_group_word014; -#[doc = "MB_8B_GROUP_MB14_8B_WORD1 (rw) register accessor: Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb14_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB14_8B_WORD1")] -pub type Mb8bGroupMb14_8bWord1 = crate::Reg; -#[doc = "Message Buffer 14 WORD_8B Register"] -pub mod mb_8b_group_mb14_8b_word1; -#[doc = "MB_64B_GROUP_MB3_64B_WORD3 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word3`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD3")] -pub type Mb64bGroupMb3_64bWord3 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word3; -#[doc = "MB_32B_GROUP_MB5_32B_WORD7 (rw) register accessor: Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb5_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB5_32B_WORD7")] -pub type Mb32bGroupMb5_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_32B Register"] -pub mod mb_32b_group_mb5_32b_word7; -#[doc = "MB_16B_GROUP_MB9_16B_WORD3 (rw) register accessor: Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb9_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB9_16B_WORD3")] -pub type Mb16bGroupMb9_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_16B Register"] -pub mod mb_16b_group_mb9_16b_word3; -#[doc = "MB_GROUP_WORD114 (rw) register accessor: Message Buffer 14 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word114::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word114::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word114`] module"] -#[doc(alias = "MB_GROUP_WORD114")] -pub type MbGroupWord114 = crate::Reg; -#[doc = "Message Buffer 14 WORD1 Register"] -pub mod mb_group_word114; -#[doc = "MB_GROUP_CS15 (rw) register accessor: Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs15`] module"] -#[doc(alias = "MB_GROUP_CS15")] -pub type MbGroupCs15 = crate::Reg; -#[doc = "Message Buffer 15 CS Register"] -pub mod mb_group_cs15; -#[doc = "MB_16B_GROUP_MB10_16B_CS (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB10_16B_CS")] -pub type Mb16bGroupMb10_16bCs = crate::Reg; -#[doc = "Message Buffer 10 CS Register"] -pub mod mb_16b_group_mb10_16b_cs; -#[doc = "MB_8B_GROUP_MB15_8B_CS (rw) register accessor: Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB15_8B_CS")] -pub type Mb8bGroupMb15_8bCs = crate::Reg; -#[doc = "Message Buffer 15 CS Register"] -pub mod mb_8b_group_mb15_8b_cs; -#[doc = "MB_64B_GROUP_MB3_64B_WORD4 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word4`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD4")] -pub type Mb64bGroupMb3_64bWord4 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word4; -#[doc = "MB_32B_GROUP_MB6_32B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_CS")] -pub type Mb32bGroupMb6_32bCs = crate::Reg; -#[doc = "Message Buffer 6 CS Register"] -pub mod mb_32b_group_mb6_32b_cs; -#[doc = "MB_GROUP_ID15 (rw) register accessor: Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id15`] module"] -#[doc(alias = "MB_GROUP_ID15")] -pub type MbGroupId15 = crate::Reg; -#[doc = "Message Buffer 15 ID Register"] -pub mod mb_group_id15; -#[doc = "MB_16B_GROUP_MB10_16B_ID (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB10_16B_ID")] -pub type Mb16bGroupMb10_16bId = crate::Reg; -#[doc = "Message Buffer 10 ID Register"] -pub mod mb_16b_group_mb10_16b_id; -#[doc = "MB_8B_GROUP_MB15_8B_ID (rw) register accessor: Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB15_8B_ID")] -pub type Mb8bGroupMb15_8bId = crate::Reg; -#[doc = "Message Buffer 15 ID Register"] -pub mod mb_8b_group_mb15_8b_id; -#[doc = "MB_64B_GROUP_MB3_64B_WORD5 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word5`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD5")] -pub type Mb64bGroupMb3_64bWord5 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word5; -#[doc = "MB_32B_GROUP_MB6_32B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_ID")] -pub type Mb32bGroupMb6_32bId = crate::Reg; -#[doc = "Message Buffer 6 ID Register"] -pub mod mb_32b_group_mb6_32b_id; -#[doc = "MB_16B_GROUP_MB10_16B_WORD0 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD0")] -pub type Mb16bGroupMb10_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_16B Register"] -pub mod mb_16b_group_mb10_16b_word0; -#[doc = "MB_8B_GROUP_MB15_8B_WORD0 (rw) register accessor: Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB15_8B_WORD0")] -pub type Mb8bGroupMb15_8bWord0 = crate::Reg; -#[doc = "Message Buffer 15 WORD_8B Register"] -pub mod mb_8b_group_mb15_8b_word0; -#[doc = "MB_64B_GROUP_MB3_64B_WORD6 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word6`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD6")] -pub type Mb64bGroupMb3_64bWord6 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word6; -#[doc = "MB_32B_GROUP_MB6_32B_WORD0 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD0")] -pub type Mb32bGroupMb6_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word0; -#[doc = "MB_GROUP_WORD015 (rw) register accessor: Message Buffer 15 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word015::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word015::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word015`] module"] -#[doc(alias = "MB_GROUP_WORD015")] -pub type MbGroupWord015 = crate::Reg; -#[doc = "Message Buffer 15 WORD0 Register"] -pub mod mb_group_word015; -#[doc = "MB_16B_GROUP_MB10_16B_WORD1 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD1")] -pub type Mb16bGroupMb10_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_16B Register"] -pub mod mb_16b_group_mb10_16b_word1; -#[doc = "MB_8B_GROUP_MB15_8B_WORD1 (rw) register accessor: Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb15_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB15_8B_WORD1")] -pub type Mb8bGroupMb15_8bWord1 = crate::Reg; -#[doc = "Message Buffer 15 WORD_8B Register"] -pub mod mb_8b_group_mb15_8b_word1; -#[doc = "MB_64B_GROUP_MB3_64B_WORD7 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word7`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD7")] -pub type Mb64bGroupMb3_64bWord7 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word7; -#[doc = "MB_32B_GROUP_MB6_32B_WORD1 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD1")] -pub type Mb32bGroupMb6_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word1; -#[doc = "MB_GROUP_WORD115 (rw) register accessor: Message Buffer 15 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word115::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word115::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word115`] module"] -#[doc(alias = "MB_GROUP_WORD115")] -pub type MbGroupWord115 = crate::Reg; -#[doc = "Message Buffer 15 WORD1 Register"] -pub mod mb_group_word115; -#[doc = "MB_GROUP_CS16 (rw) register accessor: Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs16`] module"] -#[doc(alias = "MB_GROUP_CS16")] -pub type MbGroupCs16 = crate::Reg; -#[doc = "Message Buffer 16 CS Register"] -pub mod mb_group_cs16; -#[doc = "MB_16B_GROUP_MB10_16B_WORD2 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD2")] -pub type Mb16bGroupMb10_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_16B Register"] -pub mod mb_16b_group_mb10_16b_word2; -#[doc = "MB_8B_GROUP_MB16_8B_CS (rw) register accessor: Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB16_8B_CS")] -pub type Mb8bGroupMb16_8bCs = crate::Reg; -#[doc = "Message Buffer 16 CS Register"] -pub mod mb_8b_group_mb16_8b_cs; -#[doc = "MB_64B_GROUP_MB3_64B_WORD8 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word8`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD8")] -pub type Mb64bGroupMb3_64bWord8 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word8; -#[doc = "MB_32B_GROUP_MB6_32B_WORD2 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD2")] -pub type Mb32bGroupMb6_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word2; -#[doc = "MB_GROUP_ID16 (rw) register accessor: Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id16`] module"] -#[doc(alias = "MB_GROUP_ID16")] -pub type MbGroupId16 = crate::Reg; -#[doc = "Message Buffer 16 ID Register"] -pub mod mb_group_id16; -#[doc = "MB_16B_GROUP_MB10_16B_WORD3 (rw) register accessor: Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb10_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB10_16B_WORD3")] -pub type Mb16bGroupMb10_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_16B Register"] -pub mod mb_16b_group_mb10_16b_word3; -#[doc = "MB_8B_GROUP_MB16_8B_ID (rw) register accessor: Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB16_8B_ID")] -pub type Mb8bGroupMb16_8bId = crate::Reg; -#[doc = "Message Buffer 16 ID Register"] -pub mod mb_8b_group_mb16_8b_id; -#[doc = "MB_64B_GROUP_MB3_64B_WORD9 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word9`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD9")] -pub type Mb64bGroupMb3_64bWord9 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word9; -#[doc = "MB_32B_GROUP_MB6_32B_WORD3 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD3")] -pub type Mb32bGroupMb6_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word3; -#[doc = "MB_16B_GROUP_MB11_16B_CS (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB11_16B_CS")] -pub type Mb16bGroupMb11_16bCs = crate::Reg; -#[doc = "Message Buffer 11 CS Register"] -pub mod mb_16b_group_mb11_16b_cs; -#[doc = "MB_8B_GROUP_MB16_8B_WORD0 (rw) register accessor: Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB16_8B_WORD0")] -pub type Mb8bGroupMb16_8bWord0 = crate::Reg; -#[doc = "Message Buffer 16 WORD_8B Register"] -pub mod mb_8b_group_mb16_8b_word0; -#[doc = "MB_64B_GROUP_MB3_64B_WORD10 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word10`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD10")] -pub type Mb64bGroupMb3_64bWord10 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word10; -#[doc = "MB_32B_GROUP_MB6_32B_WORD4 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD4")] -pub type Mb32bGroupMb6_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word4; -#[doc = "MB_GROUP_WORD016 (rw) register accessor: Message Buffer 16 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word016::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word016::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word016`] module"] -#[doc(alias = "MB_GROUP_WORD016")] -pub type MbGroupWord016 = crate::Reg; -#[doc = "Message Buffer 16 WORD0 Register"] -pub mod mb_group_word016; -#[doc = "MB_16B_GROUP_MB11_16B_ID (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB11_16B_ID")] -pub type Mb16bGroupMb11_16bId = crate::Reg; -#[doc = "Message Buffer 11 ID Register"] -pub mod mb_16b_group_mb11_16b_id; -#[doc = "MB_8B_GROUP_MB16_8B_WORD1 (rw) register accessor: Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb16_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB16_8B_WORD1")] -pub type Mb8bGroupMb16_8bWord1 = crate::Reg; -#[doc = "Message Buffer 16 WORD_8B Register"] -pub mod mb_8b_group_mb16_8b_word1; -#[doc = "MB_64B_GROUP_MB3_64B_WORD11 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word11`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD11")] -pub type Mb64bGroupMb3_64bWord11 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word11; -#[doc = "MB_32B_GROUP_MB6_32B_WORD5 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD5")] -pub type Mb32bGroupMb6_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word5; -#[doc = "MB_GROUP_WORD116 (rw) register accessor: Message Buffer 16 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word116::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word116::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word116`] module"] -#[doc(alias = "MB_GROUP_WORD116")] -pub type MbGroupWord116 = crate::Reg; -#[doc = "Message Buffer 16 WORD1 Register"] -pub mod mb_group_word116; -#[doc = "MB_GROUP_CS17 (rw) register accessor: Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs17`] module"] -#[doc(alias = "MB_GROUP_CS17")] -pub type MbGroupCs17 = crate::Reg; -#[doc = "Message Buffer 17 CS Register"] -pub mod mb_group_cs17; -#[doc = "MB_16B_GROUP_MB11_16B_WORD0 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD0")] -pub type Mb16bGroupMb11_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_16B Register"] -pub mod mb_16b_group_mb11_16b_word0; -#[doc = "MB_8B_GROUP_MB17_8B_CS (rw) register accessor: Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB17_8B_CS")] -pub type Mb8bGroupMb17_8bCs = crate::Reg; -#[doc = "Message Buffer 17 CS Register"] -pub mod mb_8b_group_mb17_8b_cs; -#[doc = "MB_64B_GROUP_MB3_64B_WORD12 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word12`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD12")] -pub type Mb64bGroupMb3_64bWord12 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word12; -#[doc = "MB_32B_GROUP_MB6_32B_WORD6 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD6")] -pub type Mb32bGroupMb6_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word6; -#[doc = "MB_GROUP_ID17 (rw) register accessor: Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id17`] module"] -#[doc(alias = "MB_GROUP_ID17")] -pub type MbGroupId17 = crate::Reg; -#[doc = "Message Buffer 17 ID Register"] -pub mod mb_group_id17; -#[doc = "MB_16B_GROUP_MB11_16B_WORD1 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD1")] -pub type Mb16bGroupMb11_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_16B Register"] -pub mod mb_16b_group_mb11_16b_word1; -#[doc = "MB_8B_GROUP_MB17_8B_ID (rw) register accessor: Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB17_8B_ID")] -pub type Mb8bGroupMb17_8bId = crate::Reg; -#[doc = "Message Buffer 17 ID Register"] -pub mod mb_8b_group_mb17_8b_id; -#[doc = "MB_64B_GROUP_MB3_64B_WORD13 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word13`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD13")] -pub type Mb64bGroupMb3_64bWord13 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word13; -#[doc = "MB_32B_GROUP_MB6_32B_WORD7 (rw) register accessor: Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb6_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB6_32B_WORD7")] -pub type Mb32bGroupMb6_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_32B Register"] -pub mod mb_32b_group_mb6_32b_word7; -#[doc = "MB_16B_GROUP_MB11_16B_WORD2 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD2")] -pub type Mb16bGroupMb11_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_16B Register"] -pub mod mb_16b_group_mb11_16b_word2; -#[doc = "MB_8B_GROUP_MB17_8B_WORD0 (rw) register accessor: Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB17_8B_WORD0")] -pub type Mb8bGroupMb17_8bWord0 = crate::Reg; -#[doc = "Message Buffer 17 WORD_8B Register"] -pub mod mb_8b_group_mb17_8b_word0; -#[doc = "MB_64B_GROUP_MB3_64B_WORD14 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word14`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD14")] -pub type Mb64bGroupMb3_64bWord14 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word14; -#[doc = "MB_32B_GROUP_MB7_32B_CS (rw) register accessor: Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_CS")] -pub type Mb32bGroupMb7_32bCs = crate::Reg; -#[doc = "Message Buffer 7 CS Register"] -pub mod mb_32b_group_mb7_32b_cs; -#[doc = "MB_GROUP_WORD017 (rw) register accessor: Message Buffer 17 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word017::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word017::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word017`] module"] -#[doc(alias = "MB_GROUP_WORD017")] -pub type MbGroupWord017 = crate::Reg; -#[doc = "Message Buffer 17 WORD0 Register"] -pub mod mb_group_word017; -#[doc = "MB_16B_GROUP_MB11_16B_WORD3 (rw) register accessor: Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb11_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB11_16B_WORD3")] -pub type Mb16bGroupMb11_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_16B Register"] -pub mod mb_16b_group_mb11_16b_word3; -#[doc = "MB_8B_GROUP_MB17_8B_WORD1 (rw) register accessor: Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb17_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB17_8B_WORD1")] -pub type Mb8bGroupMb17_8bWord1 = crate::Reg; -#[doc = "Message Buffer 17 WORD_8B Register"] -pub mod mb_8b_group_mb17_8b_word1; -#[doc = "MB_64B_GROUP_MB3_64B_WORD15 (rw) register accessor: Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb3_64b_word15`] module"] -#[doc(alias = "MB_64B_GROUP_MB3_64B_WORD15")] -pub type Mb64bGroupMb3_64bWord15 = - crate::Reg; -#[doc = "Message Buffer 3 WORD_64B Register"] -pub mod mb_64b_group_mb3_64b_word15; -#[doc = "MB_32B_GROUP_MB7_32B_ID (rw) register accessor: Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_ID")] -pub type Mb32bGroupMb7_32bId = crate::Reg; -#[doc = "Message Buffer 7 ID Register"] -pub mod mb_32b_group_mb7_32b_id; -#[doc = "MB_GROUP_WORD117 (rw) register accessor: Message Buffer 17 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word117::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word117::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word117`] module"] -#[doc(alias = "MB_GROUP_WORD117")] -pub type MbGroupWord117 = crate::Reg; -#[doc = "Message Buffer 17 WORD1 Register"] -pub mod mb_group_word117; -#[doc = "MB_GROUP_CS18 (rw) register accessor: Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs18`] module"] -#[doc(alias = "MB_GROUP_CS18")] -pub type MbGroupCs18 = crate::Reg; -#[doc = "Message Buffer 18 CS Register"] -pub mod mb_group_cs18; -#[doc = "MB_16B_GROUP_MB12_16B_CS (rw) register accessor: Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB12_16B_CS")] -pub type Mb16bGroupMb12_16bCs = crate::Reg; -#[doc = "Message Buffer 12 CS Register"] -pub mod mb_16b_group_mb12_16b_cs; -#[doc = "MB_8B_GROUP_MB18_8B_CS (rw) register accessor: Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB18_8B_CS")] -pub type Mb8bGroupMb18_8bCs = crate::Reg; -#[doc = "Message Buffer 18 CS Register"] -pub mod mb_8b_group_mb18_8b_cs; -#[doc = "MB_64B_GROUP_MB4_64B_CS (rw) register accessor: Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_cs`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_CS")] -pub type Mb64bGroupMb4_64bCs = crate::Reg; -#[doc = "Message Buffer 4 CS Register"] -pub mod mb_64b_group_mb4_64b_cs; -#[doc = "MB_32B_GROUP_MB7_32B_WORD0 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD0")] -pub type Mb32bGroupMb7_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word0; -#[doc = "MB_GROUP_ID18 (rw) register accessor: Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id18`] module"] -#[doc(alias = "MB_GROUP_ID18")] -pub type MbGroupId18 = crate::Reg; -#[doc = "Message Buffer 18 ID Register"] -pub mod mb_group_id18; -#[doc = "MB_16B_GROUP_MB12_16B_ID (rw) register accessor: Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB12_16B_ID")] -pub type Mb16bGroupMb12_16bId = crate::Reg; -#[doc = "Message Buffer 12 ID Register"] -pub mod mb_16b_group_mb12_16b_id; -#[doc = "MB_8B_GROUP_MB18_8B_ID (rw) register accessor: Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB18_8B_ID")] -pub type Mb8bGroupMb18_8bId = crate::Reg; -#[doc = "Message Buffer 18 ID Register"] -pub mod mb_8b_group_mb18_8b_id; -#[doc = "MB_64B_GROUP_MB4_64B_ID (rw) register accessor: Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_id`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_ID")] -pub type Mb64bGroupMb4_64bId = crate::Reg; -#[doc = "Message Buffer 4 ID Register"] -pub mod mb_64b_group_mb4_64b_id; -#[doc = "MB_32B_GROUP_MB7_32B_WORD1 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD1")] -pub type Mb32bGroupMb7_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word1; -#[doc = "MB_16B_GROUP_MB12_16B_WORD0 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD0")] -pub type Mb16bGroupMb12_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 12 WORD_16B Register"] -pub mod mb_16b_group_mb12_16b_word0; -#[doc = "MB_8B_GROUP_MB18_8B_WORD0 (rw) register accessor: Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB18_8B_WORD0")] -pub type Mb8bGroupMb18_8bWord0 = crate::Reg; -#[doc = "Message Buffer 18 WORD_8B Register"] -pub mod mb_8b_group_mb18_8b_word0; -#[doc = "MB_64B_GROUP_MB4_64B_WORD0 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word0`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD0")] -pub type Mb64bGroupMb4_64bWord0 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word0; -#[doc = "MB_32B_GROUP_MB7_32B_WORD2 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD2")] -pub type Mb32bGroupMb7_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word2; -#[doc = "MB_GROUP_WORD018 (rw) register accessor: Message Buffer 18 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word018::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word018::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word018`] module"] -#[doc(alias = "MB_GROUP_WORD018")] -pub type MbGroupWord018 = crate::Reg; -#[doc = "Message Buffer 18 WORD0 Register"] -pub mod mb_group_word018; -#[doc = "MB_16B_GROUP_MB12_16B_WORD1 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD1")] -pub type Mb16bGroupMb12_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 12 WORD_16B Register"] -pub mod mb_16b_group_mb12_16b_word1; -#[doc = "MB_8B_GROUP_MB18_8B_WORD1 (rw) register accessor: Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb18_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB18_8B_WORD1")] -pub type Mb8bGroupMb18_8bWord1 = crate::Reg; -#[doc = "Message Buffer 18 WORD_8B Register"] -pub mod mb_8b_group_mb18_8b_word1; -#[doc = "MB_64B_GROUP_MB4_64B_WORD1 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word1`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD1")] -pub type Mb64bGroupMb4_64bWord1 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word1; -#[doc = "MB_32B_GROUP_MB7_32B_WORD3 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD3")] -pub type Mb32bGroupMb7_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word3; -#[doc = "MB_GROUP_WORD118 (rw) register accessor: Message Buffer 18 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word118::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word118::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word118`] module"] -#[doc(alias = "MB_GROUP_WORD118")] -pub type MbGroupWord118 = crate::Reg; -#[doc = "Message Buffer 18 WORD1 Register"] -pub mod mb_group_word118; -#[doc = "MB_GROUP_CS19 (rw) register accessor: Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs19`] module"] -#[doc(alias = "MB_GROUP_CS19")] -pub type MbGroupCs19 = crate::Reg; -#[doc = "Message Buffer 19 CS Register"] -pub mod mb_group_cs19; -#[doc = "MB_16B_GROUP_MB12_16B_WORD2 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD2")] -pub type Mb16bGroupMb12_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 12 WORD_16B Register"] -pub mod mb_16b_group_mb12_16b_word2; -#[doc = "MB_8B_GROUP_MB19_8B_CS (rw) register accessor: Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB19_8B_CS")] -pub type Mb8bGroupMb19_8bCs = crate::Reg; -#[doc = "Message Buffer 19 CS Register"] -pub mod mb_8b_group_mb19_8b_cs; -#[doc = "MB_64B_GROUP_MB4_64B_WORD2 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word2`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD2")] -pub type Mb64bGroupMb4_64bWord2 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word2; -#[doc = "MB_32B_GROUP_MB7_32B_WORD4 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD4")] -pub type Mb32bGroupMb7_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word4; -#[doc = "MB_GROUP_ID19 (rw) register accessor: Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id19`] module"] -#[doc(alias = "MB_GROUP_ID19")] -pub type MbGroupId19 = crate::Reg; -#[doc = "Message Buffer 19 ID Register"] -pub mod mb_group_id19; -#[doc = "MB_16B_GROUP_MB12_16B_WORD3 (rw) register accessor: Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb12_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB12_16B_WORD3")] -pub type Mb16bGroupMb12_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 12 WORD_16B Register"] -pub mod mb_16b_group_mb12_16b_word3; -#[doc = "MB_8B_GROUP_MB19_8B_ID (rw) register accessor: Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB19_8B_ID")] -pub type Mb8bGroupMb19_8bId = crate::Reg; -#[doc = "Message Buffer 19 ID Register"] -pub mod mb_8b_group_mb19_8b_id; -#[doc = "MB_64B_GROUP_MB4_64B_WORD3 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word3`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD3")] -pub type Mb64bGroupMb4_64bWord3 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word3; -#[doc = "MB_32B_GROUP_MB7_32B_WORD5 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD5")] -pub type Mb32bGroupMb7_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word5; -#[doc = "MB_16B_GROUP_MB13_16B_CS (rw) register accessor: Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB13_16B_CS")] -pub type Mb16bGroupMb13_16bCs = crate::Reg; -#[doc = "Message Buffer 13 CS Register"] -pub mod mb_16b_group_mb13_16b_cs; -#[doc = "MB_8B_GROUP_MB19_8B_WORD0 (rw) register accessor: Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB19_8B_WORD0")] -pub type Mb8bGroupMb19_8bWord0 = crate::Reg; -#[doc = "Message Buffer 19 WORD_8B Register"] -pub mod mb_8b_group_mb19_8b_word0; -#[doc = "MB_64B_GROUP_MB4_64B_WORD4 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word4`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD4")] -pub type Mb64bGroupMb4_64bWord4 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word4; -#[doc = "MB_32B_GROUP_MB7_32B_WORD6 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD6")] -pub type Mb32bGroupMb7_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word6; -#[doc = "MB_GROUP_WORD019 (rw) register accessor: Message Buffer 19 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word019::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word019::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word019`] module"] -#[doc(alias = "MB_GROUP_WORD019")] -pub type MbGroupWord019 = crate::Reg; -#[doc = "Message Buffer 19 WORD0 Register"] -pub mod mb_group_word019; -#[doc = "MB_16B_GROUP_MB13_16B_ID (rw) register accessor: Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB13_16B_ID")] -pub type Mb16bGroupMb13_16bId = crate::Reg; -#[doc = "Message Buffer 13 ID Register"] -pub mod mb_16b_group_mb13_16b_id; -#[doc = "MB_8B_GROUP_MB19_8B_WORD1 (rw) register accessor: Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb19_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB19_8B_WORD1")] -pub type Mb8bGroupMb19_8bWord1 = crate::Reg; -#[doc = "Message Buffer 19 WORD_8B Register"] -pub mod mb_8b_group_mb19_8b_word1; -#[doc = "MB_64B_GROUP_MB4_64B_WORD5 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word5`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD5")] -pub type Mb64bGroupMb4_64bWord5 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word5; -#[doc = "MB_32B_GROUP_MB7_32B_WORD7 (rw) register accessor: Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb7_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB7_32B_WORD7")] -pub type Mb32bGroupMb7_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 7 WORD_32B Register"] -pub mod mb_32b_group_mb7_32b_word7; -#[doc = "MB_GROUP_WORD119 (rw) register accessor: Message Buffer 19 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word119::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word119::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word119`] module"] -#[doc(alias = "MB_GROUP_WORD119")] -pub type MbGroupWord119 = crate::Reg; -#[doc = "Message Buffer 19 WORD1 Register"] -pub mod mb_group_word119; -#[doc = "MB_GROUP_CS20 (rw) register accessor: Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs20`] module"] -#[doc(alias = "MB_GROUP_CS20")] -pub type MbGroupCs20 = crate::Reg; -#[doc = "Message Buffer 20 CS Register"] -pub mod mb_group_cs20; -#[doc = "MB_16B_GROUP_MB13_16B_WORD0 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD0")] -pub type Mb16bGroupMb13_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 13 WORD_16B Register"] -pub mod mb_16b_group_mb13_16b_word0; -#[doc = "MB_8B_GROUP_MB20_8B_CS (rw) register accessor: Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB20_8B_CS")] -pub type Mb8bGroupMb20_8bCs = crate::Reg; -#[doc = "Message Buffer 20 CS Register"] -pub mod mb_8b_group_mb20_8b_cs; -#[doc = "MB_64B_GROUP_MB4_64B_WORD6 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word6`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD6")] -pub type Mb64bGroupMb4_64bWord6 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word6; -#[doc = "MB_32B_GROUP_MB8_32B_CS (rw) register accessor: Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_CS")] -pub type Mb32bGroupMb8_32bCs = crate::Reg; -#[doc = "Message Buffer 8 CS Register"] -pub mod mb_32b_group_mb8_32b_cs; -#[doc = "MB_GROUP_ID20 (rw) register accessor: Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id20`] module"] -#[doc(alias = "MB_GROUP_ID20")] -pub type MbGroupId20 = crate::Reg; -#[doc = "Message Buffer 20 ID Register"] -pub mod mb_group_id20; -#[doc = "MB_16B_GROUP_MB13_16B_WORD1 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD1")] -pub type Mb16bGroupMb13_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 13 WORD_16B Register"] -pub mod mb_16b_group_mb13_16b_word1; -#[doc = "MB_8B_GROUP_MB20_8B_ID (rw) register accessor: Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB20_8B_ID")] -pub type Mb8bGroupMb20_8bId = crate::Reg; -#[doc = "Message Buffer 20 ID Register"] -pub mod mb_8b_group_mb20_8b_id; -#[doc = "MB_64B_GROUP_MB4_64B_WORD7 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word7`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD7")] -pub type Mb64bGroupMb4_64bWord7 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word7; -#[doc = "MB_32B_GROUP_MB8_32B_ID (rw) register accessor: Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_ID")] -pub type Mb32bGroupMb8_32bId = crate::Reg; -#[doc = "Message Buffer 8 ID Register"] -pub mod mb_32b_group_mb8_32b_id; -#[doc = "MB_16B_GROUP_MB13_16B_WORD2 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD2")] -pub type Mb16bGroupMb13_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 13 WORD_16B Register"] -pub mod mb_16b_group_mb13_16b_word2; -#[doc = "MB_8B_GROUP_MB20_8B_WORD0 (rw) register accessor: Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB20_8B_WORD0")] -pub type Mb8bGroupMb20_8bWord0 = crate::Reg; -#[doc = "Message Buffer 20 WORD_8B Register"] -pub mod mb_8b_group_mb20_8b_word0; -#[doc = "MB_64B_GROUP_MB4_64B_WORD8 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word8`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD8")] -pub type Mb64bGroupMb4_64bWord8 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word8; -#[doc = "MB_32B_GROUP_MB8_32B_WORD0 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD0")] -pub type Mb32bGroupMb8_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word0; -#[doc = "MB_GROUP_WORD020 (rw) register accessor: Message Buffer 20 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word020::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word020::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word020`] module"] -#[doc(alias = "MB_GROUP_WORD020")] -pub type MbGroupWord020 = crate::Reg; -#[doc = "Message Buffer 20 WORD0 Register"] -pub mod mb_group_word020; -#[doc = "MB_16B_GROUP_MB13_16B_WORD3 (rw) register accessor: Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb13_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB13_16B_WORD3")] -pub type Mb16bGroupMb13_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 13 WORD_16B Register"] -pub mod mb_16b_group_mb13_16b_word3; -#[doc = "MB_8B_GROUP_MB20_8B_WORD1 (rw) register accessor: Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb20_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB20_8B_WORD1")] -pub type Mb8bGroupMb20_8bWord1 = crate::Reg; -#[doc = "Message Buffer 20 WORD_8B Register"] -pub mod mb_8b_group_mb20_8b_word1; -#[doc = "MB_64B_GROUP_MB4_64B_WORD9 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word9`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD9")] -pub type Mb64bGroupMb4_64bWord9 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word9; -#[doc = "MB_32B_GROUP_MB8_32B_WORD1 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD1")] -pub type Mb32bGroupMb8_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word1; -#[doc = "MB_GROUP_WORD120 (rw) register accessor: Message Buffer 20 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word120::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word120::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word120`] module"] -#[doc(alias = "MB_GROUP_WORD120")] -pub type MbGroupWord120 = crate::Reg; -#[doc = "Message Buffer 20 WORD1 Register"] -pub mod mb_group_word120; -#[doc = "MB_GROUP_CS21 (rw) register accessor: Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs21`] module"] -#[doc(alias = "MB_GROUP_CS21")] -pub type MbGroupCs21 = crate::Reg; -#[doc = "Message Buffer 21 CS Register"] -pub mod mb_group_cs21; -#[doc = "MB_16B_GROUP_MB14_16B_CS (rw) register accessor: Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB14_16B_CS")] -pub type Mb16bGroupMb14_16bCs = crate::Reg; -#[doc = "Message Buffer 14 CS Register"] -pub mod mb_16b_group_mb14_16b_cs; -#[doc = "MB_8B_GROUP_MB21_8B_CS (rw) register accessor: Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB21_8B_CS")] -pub type Mb8bGroupMb21_8bCs = crate::Reg; -#[doc = "Message Buffer 21 CS Register"] -pub mod mb_8b_group_mb21_8b_cs; -#[doc = "MB_64B_GROUP_MB4_64B_WORD10 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word10`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD10")] -pub type Mb64bGroupMb4_64bWord10 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word10; -#[doc = "MB_32B_GROUP_MB8_32B_WORD2 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD2")] -pub type Mb32bGroupMb8_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word2; -#[doc = "MB_GROUP_ID21 (rw) register accessor: Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id21`] module"] -#[doc(alias = "MB_GROUP_ID21")] -pub type MbGroupId21 = crate::Reg; -#[doc = "Message Buffer 21 ID Register"] -pub mod mb_group_id21; -#[doc = "MB_16B_GROUP_MB14_16B_ID (rw) register accessor: Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB14_16B_ID")] -pub type Mb16bGroupMb14_16bId = crate::Reg; -#[doc = "Message Buffer 14 ID Register"] -pub mod mb_16b_group_mb14_16b_id; -#[doc = "MB_8B_GROUP_MB21_8B_ID (rw) register accessor: Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB21_8B_ID")] -pub type Mb8bGroupMb21_8bId = crate::Reg; -#[doc = "Message Buffer 21 ID Register"] -pub mod mb_8b_group_mb21_8b_id; -#[doc = "MB_64B_GROUP_MB4_64B_WORD11 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word11`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD11")] -pub type Mb64bGroupMb4_64bWord11 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word11; -#[doc = "MB_32B_GROUP_MB8_32B_WORD3 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD3")] -pub type Mb32bGroupMb8_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word3; -#[doc = "MB_16B_GROUP_MB14_16B_WORD0 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD0")] -pub type Mb16bGroupMb14_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 14 WORD_16B Register"] -pub mod mb_16b_group_mb14_16b_word0; -#[doc = "MB_8B_GROUP_MB21_8B_WORD0 (rw) register accessor: Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB21_8B_WORD0")] -pub type Mb8bGroupMb21_8bWord0 = crate::Reg; -#[doc = "Message Buffer 21 WORD_8B Register"] -pub mod mb_8b_group_mb21_8b_word0; -#[doc = "MB_64B_GROUP_MB4_64B_WORD12 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word12`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD12")] -pub type Mb64bGroupMb4_64bWord12 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word12; -#[doc = "MB_32B_GROUP_MB8_32B_WORD4 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD4")] -pub type Mb32bGroupMb8_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word4; -#[doc = "MB_GROUP_WORD021 (rw) register accessor: Message Buffer 21 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word021::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word021::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word021`] module"] -#[doc(alias = "MB_GROUP_WORD021")] -pub type MbGroupWord021 = crate::Reg; -#[doc = "Message Buffer 21 WORD0 Register"] -pub mod mb_group_word021; -#[doc = "MB_16B_GROUP_MB14_16B_WORD1 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD1")] -pub type Mb16bGroupMb14_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 14 WORD_16B Register"] -pub mod mb_16b_group_mb14_16b_word1; -#[doc = "MB_8B_GROUP_MB21_8B_WORD1 (rw) register accessor: Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb21_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB21_8B_WORD1")] -pub type Mb8bGroupMb21_8bWord1 = crate::Reg; -#[doc = "Message Buffer 21 WORD_8B Register"] -pub mod mb_8b_group_mb21_8b_word1; -#[doc = "MB_64B_GROUP_MB4_64B_WORD13 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word13`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD13")] -pub type Mb64bGroupMb4_64bWord13 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word13; -#[doc = "MB_32B_GROUP_MB8_32B_WORD5 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD5")] -pub type Mb32bGroupMb8_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word5; -#[doc = "MB_GROUP_WORD121 (rw) register accessor: Message Buffer 21 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word121::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word121::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word121`] module"] -#[doc(alias = "MB_GROUP_WORD121")] -pub type MbGroupWord121 = crate::Reg; -#[doc = "Message Buffer 21 WORD1 Register"] -pub mod mb_group_word121; -#[doc = "MB_GROUP_CS22 (rw) register accessor: Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs22`] module"] -#[doc(alias = "MB_GROUP_CS22")] -pub type MbGroupCs22 = crate::Reg; -#[doc = "Message Buffer 22 CS Register"] -pub mod mb_group_cs22; -#[doc = "MB_16B_GROUP_MB14_16B_WORD2 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD2")] -pub type Mb16bGroupMb14_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 14 WORD_16B Register"] -pub mod mb_16b_group_mb14_16b_word2; -#[doc = "MB_8B_GROUP_MB22_8B_CS (rw) register accessor: Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB22_8B_CS")] -pub type Mb8bGroupMb22_8bCs = crate::Reg; -#[doc = "Message Buffer 22 CS Register"] -pub mod mb_8b_group_mb22_8b_cs; -#[doc = "MB_64B_GROUP_MB4_64B_WORD14 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word14`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD14")] -pub type Mb64bGroupMb4_64bWord14 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word14; -#[doc = "MB_32B_GROUP_MB8_32B_WORD6 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD6")] -pub type Mb32bGroupMb8_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word6; -#[doc = "MB_GROUP_ID22 (rw) register accessor: Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id22`] module"] -#[doc(alias = "MB_GROUP_ID22")] -pub type MbGroupId22 = crate::Reg; -#[doc = "Message Buffer 22 ID Register"] -pub mod mb_group_id22; -#[doc = "MB_16B_GROUP_MB14_16B_WORD3 (rw) register accessor: Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb14_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB14_16B_WORD3")] -pub type Mb16bGroupMb14_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 14 WORD_16B Register"] -pub mod mb_16b_group_mb14_16b_word3; -#[doc = "MB_8B_GROUP_MB22_8B_ID (rw) register accessor: Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB22_8B_ID")] -pub type Mb8bGroupMb22_8bId = crate::Reg; -#[doc = "Message Buffer 22 ID Register"] -pub mod mb_8b_group_mb22_8b_id; -#[doc = "MB_64B_GROUP_MB4_64B_WORD15 (rw) register accessor: Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb4_64b_word15`] module"] -#[doc(alias = "MB_64B_GROUP_MB4_64B_WORD15")] -pub type Mb64bGroupMb4_64bWord15 = - crate::Reg; -#[doc = "Message Buffer 4 WORD_64B Register"] -pub mod mb_64b_group_mb4_64b_word15; -#[doc = "MB_32B_GROUP_MB8_32B_WORD7 (rw) register accessor: Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb8_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB8_32B_WORD7")] -pub type Mb32bGroupMb8_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 8 WORD_32B Register"] -pub mod mb_32b_group_mb8_32b_word7; -#[doc = "MB_16B_GROUP_MB15_16B_CS (rw) register accessor: Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB15_16B_CS")] -pub type Mb16bGroupMb15_16bCs = crate::Reg; -#[doc = "Message Buffer 15 CS Register"] -pub mod mb_16b_group_mb15_16b_cs; -#[doc = "MB_8B_GROUP_MB22_8B_WORD0 (rw) register accessor: Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB22_8B_WORD0")] -pub type Mb8bGroupMb22_8bWord0 = crate::Reg; -#[doc = "Message Buffer 22 WORD_8B Register"] -pub mod mb_8b_group_mb22_8b_word0; -#[doc = "MB_64B_GROUP_MB5_64B_CS (rw) register accessor: Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_cs`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_CS")] -pub type Mb64bGroupMb5_64bCs = crate::Reg; -#[doc = "Message Buffer 5 CS Register"] -pub mod mb_64b_group_mb5_64b_cs; -#[doc = "MB_32B_GROUP_MB9_32B_CS (rw) register accessor: Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_CS")] -pub type Mb32bGroupMb9_32bCs = crate::Reg; -#[doc = "Message Buffer 9 CS Register"] -pub mod mb_32b_group_mb9_32b_cs; -#[doc = "MB_GROUP_WORD022 (rw) register accessor: Message Buffer 22 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word022::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word022::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word022`] module"] -#[doc(alias = "MB_GROUP_WORD022")] -pub type MbGroupWord022 = crate::Reg; -#[doc = "Message Buffer 22 WORD0 Register"] -pub mod mb_group_word022; -#[doc = "MB_16B_GROUP_MB15_16B_ID (rw) register accessor: Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB15_16B_ID")] -pub type Mb16bGroupMb15_16bId = crate::Reg; -#[doc = "Message Buffer 15 ID Register"] -pub mod mb_16b_group_mb15_16b_id; -#[doc = "MB_8B_GROUP_MB22_8B_WORD1 (rw) register accessor: Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb22_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB22_8B_WORD1")] -pub type Mb8bGroupMb22_8bWord1 = crate::Reg; -#[doc = "Message Buffer 22 WORD_8B Register"] -pub mod mb_8b_group_mb22_8b_word1; -#[doc = "MB_64B_GROUP_MB5_64B_ID (rw) register accessor: Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_id`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_ID")] -pub type Mb64bGroupMb5_64bId = crate::Reg; -#[doc = "Message Buffer 5 ID Register"] -pub mod mb_64b_group_mb5_64b_id; -#[doc = "MB_32B_GROUP_MB9_32B_ID (rw) register accessor: Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_ID")] -pub type Mb32bGroupMb9_32bId = crate::Reg; -#[doc = "Message Buffer 9 ID Register"] -pub mod mb_32b_group_mb9_32b_id; -#[doc = "MB_GROUP_WORD122 (rw) register accessor: Message Buffer 22 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word122::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word122::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word122`] module"] -#[doc(alias = "MB_GROUP_WORD122")] -pub type MbGroupWord122 = crate::Reg; -#[doc = "Message Buffer 22 WORD1 Register"] -pub mod mb_group_word122; -#[doc = "MB_GROUP_CS23 (rw) register accessor: Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs23`] module"] -#[doc(alias = "MB_GROUP_CS23")] -pub type MbGroupCs23 = crate::Reg; -#[doc = "Message Buffer 23 CS Register"] -pub mod mb_group_cs23; -#[doc = "MB_16B_GROUP_MB15_16B_WORD0 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD0")] -pub type Mb16bGroupMb15_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 15 WORD_16B Register"] -pub mod mb_16b_group_mb15_16b_word0; -#[doc = "MB_8B_GROUP_MB23_8B_CS (rw) register accessor: Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB23_8B_CS")] -pub type Mb8bGroupMb23_8bCs = crate::Reg; -#[doc = "Message Buffer 23 CS Register"] -pub mod mb_8b_group_mb23_8b_cs; -#[doc = "MB_64B_GROUP_MB5_64B_WORD0 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word0`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD0")] -pub type Mb64bGroupMb5_64bWord0 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word0; -#[doc = "MB_32B_GROUP_MB9_32B_WORD0 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD0")] -pub type Mb32bGroupMb9_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word0; -#[doc = "MB_GROUP_ID23 (rw) register accessor: Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id23`] module"] -#[doc(alias = "MB_GROUP_ID23")] -pub type MbGroupId23 = crate::Reg; -#[doc = "Message Buffer 23 ID Register"] -pub mod mb_group_id23; -#[doc = "MB_16B_GROUP_MB15_16B_WORD1 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD1")] -pub type Mb16bGroupMb15_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 15 WORD_16B Register"] -pub mod mb_16b_group_mb15_16b_word1; -#[doc = "MB_8B_GROUP_MB23_8B_ID (rw) register accessor: Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB23_8B_ID")] -pub type Mb8bGroupMb23_8bId = crate::Reg; -#[doc = "Message Buffer 23 ID Register"] -pub mod mb_8b_group_mb23_8b_id; -#[doc = "MB_64B_GROUP_MB5_64B_WORD1 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word1`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD1")] -pub type Mb64bGroupMb5_64bWord1 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word1; -#[doc = "MB_32B_GROUP_MB9_32B_WORD1 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD1")] -pub type Mb32bGroupMb9_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word1; -#[doc = "MB_16B_GROUP_MB15_16B_WORD2 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD2")] -pub type Mb16bGroupMb15_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 15 WORD_16B Register"] -pub mod mb_16b_group_mb15_16b_word2; -#[doc = "MB_8B_GROUP_MB23_8B_WORD0 (rw) register accessor: Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB23_8B_WORD0")] -pub type Mb8bGroupMb23_8bWord0 = crate::Reg; -#[doc = "Message Buffer 23 WORD_8B Register"] -pub mod mb_8b_group_mb23_8b_word0; -#[doc = "MB_64B_GROUP_MB5_64B_WORD2 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word2`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD2")] -pub type Mb64bGroupMb5_64bWord2 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word2; -#[doc = "MB_32B_GROUP_MB9_32B_WORD2 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD2")] -pub type Mb32bGroupMb9_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word2; -#[doc = "MB_GROUP_WORD023 (rw) register accessor: Message Buffer 23 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word023::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word023::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word023`] module"] -#[doc(alias = "MB_GROUP_WORD023")] -pub type MbGroupWord023 = crate::Reg; -#[doc = "Message Buffer 23 WORD0 Register"] -pub mod mb_group_word023; -#[doc = "MB_16B_GROUP_MB15_16B_WORD3 (rw) register accessor: Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb15_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB15_16B_WORD3")] -pub type Mb16bGroupMb15_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 15 WORD_16B Register"] -pub mod mb_16b_group_mb15_16b_word3; -#[doc = "MB_8B_GROUP_MB23_8B_WORD1 (rw) register accessor: Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb23_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB23_8B_WORD1")] -pub type Mb8bGroupMb23_8bWord1 = crate::Reg; -#[doc = "Message Buffer 23 WORD_8B Register"] -pub mod mb_8b_group_mb23_8b_word1; -#[doc = "MB_64B_GROUP_MB5_64B_WORD3 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word3`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD3")] -pub type Mb64bGroupMb5_64bWord3 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word3; -#[doc = "MB_32B_GROUP_MB9_32B_WORD3 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD3")] -pub type Mb32bGroupMb9_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word3; -#[doc = "MB_GROUP_WORD123 (rw) register accessor: Message Buffer 23 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word123::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word123::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word123`] module"] -#[doc(alias = "MB_GROUP_WORD123")] -pub type MbGroupWord123 = crate::Reg; -#[doc = "Message Buffer 23 WORD1 Register"] -pub mod mb_group_word123; -#[doc = "MB_GROUP_CS24 (rw) register accessor: Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs24`] module"] -#[doc(alias = "MB_GROUP_CS24")] -pub type MbGroupCs24 = crate::Reg; -#[doc = "Message Buffer 24 CS Register"] -pub mod mb_group_cs24; -#[doc = "MB_16B_GROUP_MB16_16B_CS (rw) register accessor: Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB16_16B_CS")] -pub type Mb16bGroupMb16_16bCs = crate::Reg; -#[doc = "Message Buffer 16 CS Register"] -pub mod mb_16b_group_mb16_16b_cs; -#[doc = "MB_8B_GROUP_MB24_8B_CS (rw) register accessor: Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB24_8B_CS")] -pub type Mb8bGroupMb24_8bCs = crate::Reg; -#[doc = "Message Buffer 24 CS Register"] -pub mod mb_8b_group_mb24_8b_cs; -#[doc = "MB_64B_GROUP_MB5_64B_WORD4 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word4`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD4")] -pub type Mb64bGroupMb5_64bWord4 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word4; -#[doc = "MB_32B_GROUP_MB9_32B_WORD4 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD4")] -pub type Mb32bGroupMb9_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word4; -#[doc = "MB_GROUP_ID24 (rw) register accessor: Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id24`] module"] -#[doc(alias = "MB_GROUP_ID24")] -pub type MbGroupId24 = crate::Reg; -#[doc = "Message Buffer 24 ID Register"] -pub mod mb_group_id24; -#[doc = "MB_16B_GROUP_MB16_16B_ID (rw) register accessor: Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB16_16B_ID")] -pub type Mb16bGroupMb16_16bId = crate::Reg; -#[doc = "Message Buffer 16 ID Register"] -pub mod mb_16b_group_mb16_16b_id; -#[doc = "MB_8B_GROUP_MB24_8B_ID (rw) register accessor: Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB24_8B_ID")] -pub type Mb8bGroupMb24_8bId = crate::Reg; -#[doc = "Message Buffer 24 ID Register"] -pub mod mb_8b_group_mb24_8b_id; -#[doc = "MB_64B_GROUP_MB5_64B_WORD5 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word5`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD5")] -pub type Mb64bGroupMb5_64bWord5 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word5; -#[doc = "MB_32B_GROUP_MB9_32B_WORD5 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD5")] -pub type Mb32bGroupMb9_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word5; -#[doc = "MB_16B_GROUP_MB16_16B_WORD0 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD0")] -pub type Mb16bGroupMb16_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 16 WORD_16B Register"] -pub mod mb_16b_group_mb16_16b_word0; -#[doc = "MB_8B_GROUP_MB24_8B_WORD0 (rw) register accessor: Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB24_8B_WORD0")] -pub type Mb8bGroupMb24_8bWord0 = crate::Reg; -#[doc = "Message Buffer 24 WORD_8B Register"] -pub mod mb_8b_group_mb24_8b_word0; -#[doc = "MB_64B_GROUP_MB5_64B_WORD6 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word6`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD6")] -pub type Mb64bGroupMb5_64bWord6 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word6; -#[doc = "MB_32B_GROUP_MB9_32B_WORD6 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD6")] -pub type Mb32bGroupMb9_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word6; -#[doc = "MB_GROUP_WORD024 (rw) register accessor: Message Buffer 24 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word024::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word024::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word024`] module"] -#[doc(alias = "MB_GROUP_WORD024")] -pub type MbGroupWord024 = crate::Reg; -#[doc = "Message Buffer 24 WORD0 Register"] -pub mod mb_group_word024; -#[doc = "MB_16B_GROUP_MB16_16B_WORD1 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD1")] -pub type Mb16bGroupMb16_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 16 WORD_16B Register"] -pub mod mb_16b_group_mb16_16b_word1; -#[doc = "MB_8B_GROUP_MB24_8B_WORD1 (rw) register accessor: Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb24_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB24_8B_WORD1")] -pub type Mb8bGroupMb24_8bWord1 = crate::Reg; -#[doc = "Message Buffer 24 WORD_8B Register"] -pub mod mb_8b_group_mb24_8b_word1; -#[doc = "MB_64B_GROUP_MB5_64B_WORD7 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word7`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD7")] -pub type Mb64bGroupMb5_64bWord7 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word7; -#[doc = "MB_32B_GROUP_MB9_32B_WORD7 (rw) register accessor: Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb9_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB9_32B_WORD7")] -pub type Mb32bGroupMb9_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 9 WORD_32B Register"] -pub mod mb_32b_group_mb9_32b_word7; -#[doc = "MB_GROUP_WORD124 (rw) register accessor: Message Buffer 24 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word124::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word124::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word124`] module"] -#[doc(alias = "MB_GROUP_WORD124")] -pub type MbGroupWord124 = crate::Reg; -#[doc = "Message Buffer 24 WORD1 Register"] -pub mod mb_group_word124; -#[doc = "MB_GROUP_CS25 (rw) register accessor: Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs25`] module"] -#[doc(alias = "MB_GROUP_CS25")] -pub type MbGroupCs25 = crate::Reg; -#[doc = "Message Buffer 25 CS Register"] -pub mod mb_group_cs25; -#[doc = "MB_32B_GROUP_MB10_32B_CS (rw) register accessor: Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_CS")] -pub type Mb32bGroupMb10_32bCs = crate::Reg; -#[doc = "Message Buffer 10 CS Register"] -pub mod mb_32b_group_mb10_32b_cs; -#[doc = "MB_16B_GROUP_MB16_16B_WORD2 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD2")] -pub type Mb16bGroupMb16_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 16 WORD_16B Register"] -pub mod mb_16b_group_mb16_16b_word2; -#[doc = "MB_8B_GROUP_MB25_8B_CS (rw) register accessor: Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB25_8B_CS")] -pub type Mb8bGroupMb25_8bCs = crate::Reg; -#[doc = "Message Buffer 25 CS Register"] -pub mod mb_8b_group_mb25_8b_cs; -#[doc = "MB_64B_GROUP_MB5_64B_WORD8 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word8`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD8")] -pub type Mb64bGroupMb5_64bWord8 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word8; -#[doc = "MB_GROUP_ID25 (rw) register accessor: Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id25`] module"] -#[doc(alias = "MB_GROUP_ID25")] -pub type MbGroupId25 = crate::Reg; -#[doc = "Message Buffer 25 ID Register"] -pub mod mb_group_id25; -#[doc = "MB_32B_GROUP_MB10_32B_ID (rw) register accessor: Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_ID")] -pub type Mb32bGroupMb10_32bId = crate::Reg; -#[doc = "Message Buffer 10 ID Register"] -pub mod mb_32b_group_mb10_32b_id; -#[doc = "MB_16B_GROUP_MB16_16B_WORD3 (rw) register accessor: Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb16_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB16_16B_WORD3")] -pub type Mb16bGroupMb16_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 16 WORD_16B Register"] -pub mod mb_16b_group_mb16_16b_word3; -#[doc = "MB_8B_GROUP_MB25_8B_ID (rw) register accessor: Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB25_8B_ID")] -pub type Mb8bGroupMb25_8bId = crate::Reg; -#[doc = "Message Buffer 25 ID Register"] -pub mod mb_8b_group_mb25_8b_id; -#[doc = "MB_64B_GROUP_MB5_64B_WORD9 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word9`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD9")] -pub type Mb64bGroupMb5_64bWord9 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word9; -#[doc = "MB_32B_GROUP_MB10_32B_WORD0 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD0")] -pub type Mb32bGroupMb10_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word0; -#[doc = "MB_16B_GROUP_MB17_16B_CS (rw) register accessor: Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB17_16B_CS")] -pub type Mb16bGroupMb17_16bCs = crate::Reg; -#[doc = "Message Buffer 17 CS Register"] -pub mod mb_16b_group_mb17_16b_cs; -#[doc = "MB_8B_GROUP_MB25_8B_WORD0 (rw) register accessor: Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB25_8B_WORD0")] -pub type Mb8bGroupMb25_8bWord0 = crate::Reg; -#[doc = "Message Buffer 25 WORD_8B Register"] -pub mod mb_8b_group_mb25_8b_word0; -#[doc = "MB_64B_GROUP_MB5_64B_WORD10 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word10`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD10")] -pub type Mb64bGroupMb5_64bWord10 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word10; -#[doc = "MB_GROUP_WORD025 (rw) register accessor: Message Buffer 25 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word025::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word025::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word025`] module"] -#[doc(alias = "MB_GROUP_WORD025")] -pub type MbGroupWord025 = crate::Reg; -#[doc = "Message Buffer 25 WORD0 Register"] -pub mod mb_group_word025; -#[doc = "MB_32B_GROUP_MB10_32B_WORD1 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD1")] -pub type Mb32bGroupMb10_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word1; -#[doc = "MB_16B_GROUP_MB17_16B_ID (rw) register accessor: Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB17_16B_ID")] -pub type Mb16bGroupMb17_16bId = crate::Reg; -#[doc = "Message Buffer 17 ID Register"] -pub mod mb_16b_group_mb17_16b_id; -#[doc = "MB_8B_GROUP_MB25_8B_WORD1 (rw) register accessor: Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb25_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB25_8B_WORD1")] -pub type Mb8bGroupMb25_8bWord1 = crate::Reg; -#[doc = "Message Buffer 25 WORD_8B Register"] -pub mod mb_8b_group_mb25_8b_word1; -#[doc = "MB_64B_GROUP_MB5_64B_WORD11 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word11`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD11")] -pub type Mb64bGroupMb5_64bWord11 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word11; -#[doc = "MB_GROUP_WORD125 (rw) register accessor: Message Buffer 25 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word125::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word125::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word125`] module"] -#[doc(alias = "MB_GROUP_WORD125")] -pub type MbGroupWord125 = crate::Reg; -#[doc = "Message Buffer 25 WORD1 Register"] -pub mod mb_group_word125; -#[doc = "MB_GROUP_CS26 (rw) register accessor: Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs26`] module"] -#[doc(alias = "MB_GROUP_CS26")] -pub type MbGroupCs26 = crate::Reg; -#[doc = "Message Buffer 26 CS Register"] -pub mod mb_group_cs26; -#[doc = "MB_32B_GROUP_MB10_32B_WORD2 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD2")] -pub type Mb32bGroupMb10_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word2; -#[doc = "MB_16B_GROUP_MB17_16B_WORD0 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD0")] -pub type Mb16bGroupMb17_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 17 WORD_16B Register"] -pub mod mb_16b_group_mb17_16b_word0; -#[doc = "MB_8B_GROUP_MB26_8B_CS (rw) register accessor: Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB26_8B_CS")] -pub type Mb8bGroupMb26_8bCs = crate::Reg; -#[doc = "Message Buffer 26 CS Register"] -pub mod mb_8b_group_mb26_8b_cs; -#[doc = "MB_64B_GROUP_MB5_64B_WORD12 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word12`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD12")] -pub type Mb64bGroupMb5_64bWord12 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word12; -#[doc = "MB_GROUP_ID26 (rw) register accessor: Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id26`] module"] -#[doc(alias = "MB_GROUP_ID26")] -pub type MbGroupId26 = crate::Reg; -#[doc = "Message Buffer 26 ID Register"] -pub mod mb_group_id26; -#[doc = "MB_32B_GROUP_MB10_32B_WORD3 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD3")] -pub type Mb32bGroupMb10_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word3; -#[doc = "MB_16B_GROUP_MB17_16B_WORD1 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD1")] -pub type Mb16bGroupMb17_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 17 WORD_16B Register"] -pub mod mb_16b_group_mb17_16b_word1; -#[doc = "MB_8B_GROUP_MB26_8B_ID (rw) register accessor: Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB26_8B_ID")] -pub type Mb8bGroupMb26_8bId = crate::Reg; -#[doc = "Message Buffer 26 ID Register"] -pub mod mb_8b_group_mb26_8b_id; -#[doc = "MB_64B_GROUP_MB5_64B_WORD13 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word13`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD13")] -pub type Mb64bGroupMb5_64bWord13 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word13; -#[doc = "MB_32B_GROUP_MB10_32B_WORD4 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD4")] -pub type Mb32bGroupMb10_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word4; -#[doc = "MB_16B_GROUP_MB17_16B_WORD2 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD2")] -pub type Mb16bGroupMb17_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 17 WORD_16B Register"] -pub mod mb_16b_group_mb17_16b_word2; -#[doc = "MB_8B_GROUP_MB26_8B_WORD0 (rw) register accessor: Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB26_8B_WORD0")] -pub type Mb8bGroupMb26_8bWord0 = crate::Reg; -#[doc = "Message Buffer 26 WORD_8B Register"] -pub mod mb_8b_group_mb26_8b_word0; -#[doc = "MB_64B_GROUP_MB5_64B_WORD14 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word14`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD14")] -pub type Mb64bGroupMb5_64bWord14 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word14; -#[doc = "MB_GROUP_WORD026 (rw) register accessor: Message Buffer 26 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word026::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word026::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word026`] module"] -#[doc(alias = "MB_GROUP_WORD026")] -pub type MbGroupWord026 = crate::Reg; -#[doc = "Message Buffer 26 WORD0 Register"] -pub mod mb_group_word026; -#[doc = "MB_32B_GROUP_MB10_32B_WORD5 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD5")] -pub type Mb32bGroupMb10_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word5; -#[doc = "MB_16B_GROUP_MB17_16B_WORD3 (rw) register accessor: Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb17_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB17_16B_WORD3")] -pub type Mb16bGroupMb17_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 17 WORD_16B Register"] -pub mod mb_16b_group_mb17_16b_word3; -#[doc = "MB_8B_GROUP_MB26_8B_WORD1 (rw) register accessor: Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb26_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB26_8B_WORD1")] -pub type Mb8bGroupMb26_8bWord1 = crate::Reg; -#[doc = "Message Buffer 26 WORD_8B Register"] -pub mod mb_8b_group_mb26_8b_word1; -#[doc = "MB_64B_GROUP_MB5_64B_WORD15 (rw) register accessor: Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb5_64b_word15`] module"] -#[doc(alias = "MB_64B_GROUP_MB5_64B_WORD15")] -pub type Mb64bGroupMb5_64bWord15 = - crate::Reg; -#[doc = "Message Buffer 5 WORD_64B Register"] -pub mod mb_64b_group_mb5_64b_word15; -#[doc = "MB_GROUP_WORD126 (rw) register accessor: Message Buffer 26 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word126::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word126::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word126`] module"] -#[doc(alias = "MB_GROUP_WORD126")] -pub type MbGroupWord126 = crate::Reg; -#[doc = "Message Buffer 26 WORD1 Register"] -pub mod mb_group_word126; -#[doc = "MB_GROUP_CS27 (rw) register accessor: Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs27`] module"] -#[doc(alias = "MB_GROUP_CS27")] -pub type MbGroupCs27 = crate::Reg; -#[doc = "Message Buffer 27 CS Register"] -pub mod mb_group_cs27; -#[doc = "MB_32B_GROUP_MB10_32B_WORD6 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD6")] -pub type Mb32bGroupMb10_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word6; -#[doc = "MB_16B_GROUP_MB18_16B_CS (rw) register accessor: Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB18_16B_CS")] -pub type Mb16bGroupMb18_16bCs = crate::Reg; -#[doc = "Message Buffer 18 CS Register"] -pub mod mb_16b_group_mb18_16b_cs; -#[doc = "MB_8B_GROUP_MB27_8B_CS (rw) register accessor: Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB27_8B_CS")] -pub type Mb8bGroupMb27_8bCs = crate::Reg; -#[doc = "Message Buffer 27 CS Register"] -pub mod mb_8b_group_mb27_8b_cs; -#[doc = "MB_64B_GROUP_MB6_64B_CS (rw) register accessor: Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_cs`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_CS")] -pub type Mb64bGroupMb6_64bCs = crate::Reg; -#[doc = "Message Buffer 6 CS Register"] -pub mod mb_64b_group_mb6_64b_cs; -#[doc = "MB_GROUP_ID27 (rw) register accessor: Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id27`] module"] -#[doc(alias = "MB_GROUP_ID27")] -pub type MbGroupId27 = crate::Reg; -#[doc = "Message Buffer 27 ID Register"] -pub mod mb_group_id27; -#[doc = "MB_32B_GROUP_MB10_32B_WORD7 (rw) register accessor: Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb10_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB10_32B_WORD7")] -pub type Mb32bGroupMb10_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 10 WORD_32B Register"] -pub mod mb_32b_group_mb10_32b_word7; -#[doc = "MB_16B_GROUP_MB18_16B_ID (rw) register accessor: Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB18_16B_ID")] -pub type Mb16bGroupMb18_16bId = crate::Reg; -#[doc = "Message Buffer 18 ID Register"] -pub mod mb_16b_group_mb18_16b_id; -#[doc = "MB_8B_GROUP_MB27_8B_ID (rw) register accessor: Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB27_8B_ID")] -pub type Mb8bGroupMb27_8bId = crate::Reg; -#[doc = "Message Buffer 27 ID Register"] -pub mod mb_8b_group_mb27_8b_id; -#[doc = "MB_64B_GROUP_MB6_64B_ID (rw) register accessor: Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_id`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_ID")] -pub type Mb64bGroupMb6_64bId = crate::Reg; -#[doc = "Message Buffer 6 ID Register"] -pub mod mb_64b_group_mb6_64b_id; -#[doc = "MB_32B_GROUP_MB11_32B_CS (rw) register accessor: Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_cs`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_CS")] -pub type Mb32bGroupMb11_32bCs = crate::Reg; -#[doc = "Message Buffer 11 CS Register"] -pub mod mb_32b_group_mb11_32b_cs; -#[doc = "MB_16B_GROUP_MB18_16B_WORD0 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD0")] -pub type Mb16bGroupMb18_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 18 WORD_16B Register"] -pub mod mb_16b_group_mb18_16b_word0; -#[doc = "MB_8B_GROUP_MB27_8B_WORD0 (rw) register accessor: Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB27_8B_WORD0")] -pub type Mb8bGroupMb27_8bWord0 = crate::Reg; -#[doc = "Message Buffer 27 WORD_8B Register"] -pub mod mb_8b_group_mb27_8b_word0; -#[doc = "MB_64B_GROUP_MB6_64B_WORD0 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word0`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD0")] -pub type Mb64bGroupMb6_64bWord0 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word0; -#[doc = "MB_GROUP_WORD027 (rw) register accessor: Message Buffer 27 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word027::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word027::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word027`] module"] -#[doc(alias = "MB_GROUP_WORD027")] -pub type MbGroupWord027 = crate::Reg; -#[doc = "Message Buffer 27 WORD0 Register"] -pub mod mb_group_word027; -#[doc = "MB_32B_GROUP_MB11_32B_ID (rw) register accessor: Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_id`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_ID")] -pub type Mb32bGroupMb11_32bId = crate::Reg; -#[doc = "Message Buffer 11 ID Register"] -pub mod mb_32b_group_mb11_32b_id; -#[doc = "MB_16B_GROUP_MB18_16B_WORD1 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD1")] -pub type Mb16bGroupMb18_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 18 WORD_16B Register"] -pub mod mb_16b_group_mb18_16b_word1; -#[doc = "MB_8B_GROUP_MB27_8B_WORD1 (rw) register accessor: Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb27_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB27_8B_WORD1")] -pub type Mb8bGroupMb27_8bWord1 = crate::Reg; -#[doc = "Message Buffer 27 WORD_8B Register"] -pub mod mb_8b_group_mb27_8b_word1; -#[doc = "MB_64B_GROUP_MB6_64B_WORD1 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word1`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD1")] -pub type Mb64bGroupMb6_64bWord1 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word1; -#[doc = "MB_GROUP_WORD127 (rw) register accessor: Message Buffer 27 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word127::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word127::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word127`] module"] -#[doc(alias = "MB_GROUP_WORD127")] -pub type MbGroupWord127 = crate::Reg; -#[doc = "Message Buffer 27 WORD1 Register"] -pub mod mb_group_word127; -#[doc = "MB_GROUP_CS28 (rw) register accessor: Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs28`] module"] -#[doc(alias = "MB_GROUP_CS28")] -pub type MbGroupCs28 = crate::Reg; -#[doc = "Message Buffer 28 CS Register"] -pub mod mb_group_cs28; -#[doc = "MB_32B_GROUP_MB11_32B_WORD0 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word0`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD0")] -pub type Mb32bGroupMb11_32bWord0 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word0; -#[doc = "MB_16B_GROUP_MB18_16B_WORD2 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD2")] -pub type Mb16bGroupMb18_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 18 WORD_16B Register"] -pub mod mb_16b_group_mb18_16b_word2; -#[doc = "MB_8B_GROUP_MB28_8B_CS (rw) register accessor: Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB28_8B_CS")] -pub type Mb8bGroupMb28_8bCs = crate::Reg; -#[doc = "Message Buffer 28 CS Register"] -pub mod mb_8b_group_mb28_8b_cs; -#[doc = "MB_64B_GROUP_MB6_64B_WORD2 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word2`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD2")] -pub type Mb64bGroupMb6_64bWord2 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word2; -#[doc = "MB_GROUP_ID28 (rw) register accessor: Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id28`] module"] -#[doc(alias = "MB_GROUP_ID28")] -pub type MbGroupId28 = crate::Reg; -#[doc = "Message Buffer 28 ID Register"] -pub mod mb_group_id28; -#[doc = "MB_32B_GROUP_MB11_32B_WORD1 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word1`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD1")] -pub type Mb32bGroupMb11_32bWord1 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word1; -#[doc = "MB_16B_GROUP_MB18_16B_WORD3 (rw) register accessor: Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb18_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB18_16B_WORD3")] -pub type Mb16bGroupMb18_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 18 WORD_16B Register"] -pub mod mb_16b_group_mb18_16b_word3; -#[doc = "MB_8B_GROUP_MB28_8B_ID (rw) register accessor: Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB28_8B_ID")] -pub type Mb8bGroupMb28_8bId = crate::Reg; -#[doc = "Message Buffer 28 ID Register"] -pub mod mb_8b_group_mb28_8b_id; -#[doc = "MB_64B_GROUP_MB6_64B_WORD3 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word3`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD3")] -pub type Mb64bGroupMb6_64bWord3 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word3; -#[doc = "MB_32B_GROUP_MB11_32B_WORD2 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word2`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD2")] -pub type Mb32bGroupMb11_32bWord2 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word2; -#[doc = "MB_16B_GROUP_MB19_16B_CS (rw) register accessor: Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB19_16B_CS")] -pub type Mb16bGroupMb19_16bCs = crate::Reg; -#[doc = "Message Buffer 19 CS Register"] -pub mod mb_16b_group_mb19_16b_cs; -#[doc = "MB_8B_GROUP_MB28_8B_WORD0 (rw) register accessor: Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB28_8B_WORD0")] -pub type Mb8bGroupMb28_8bWord0 = crate::Reg; -#[doc = "Message Buffer 28 WORD_8B Register"] -pub mod mb_8b_group_mb28_8b_word0; -#[doc = "MB_64B_GROUP_MB6_64B_WORD4 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word4`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD4")] -pub type Mb64bGroupMb6_64bWord4 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word4; -#[doc = "MB_GROUP_WORD028 (rw) register accessor: Message Buffer 28 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word028::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word028::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word028`] module"] -#[doc(alias = "MB_GROUP_WORD028")] -pub type MbGroupWord028 = crate::Reg; -#[doc = "Message Buffer 28 WORD0 Register"] -pub mod mb_group_word028; -#[doc = "MB_32B_GROUP_MB11_32B_WORD3 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word3`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD3")] -pub type Mb32bGroupMb11_32bWord3 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word3; -#[doc = "MB_16B_GROUP_MB19_16B_ID (rw) register accessor: Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB19_16B_ID")] -pub type Mb16bGroupMb19_16bId = crate::Reg; -#[doc = "Message Buffer 19 ID Register"] -pub mod mb_16b_group_mb19_16b_id; -#[doc = "MB_8B_GROUP_MB28_8B_WORD1 (rw) register accessor: Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb28_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB28_8B_WORD1")] -pub type Mb8bGroupMb28_8bWord1 = crate::Reg; -#[doc = "Message Buffer 28 WORD_8B Register"] -pub mod mb_8b_group_mb28_8b_word1; -#[doc = "MB_64B_GROUP_MB6_64B_WORD5 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word5`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD5")] -pub type Mb64bGroupMb6_64bWord5 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word5; -#[doc = "MB_GROUP_WORD128 (rw) register accessor: Message Buffer 28 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word128::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word128::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word128`] module"] -#[doc(alias = "MB_GROUP_WORD128")] -pub type MbGroupWord128 = crate::Reg; -#[doc = "Message Buffer 28 WORD1 Register"] -pub mod mb_group_word128; -#[doc = "MB_GROUP_CS29 (rw) register accessor: Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs29`] module"] -#[doc(alias = "MB_GROUP_CS29")] -pub type MbGroupCs29 = crate::Reg; -#[doc = "Message Buffer 29 CS Register"] -pub mod mb_group_cs29; -#[doc = "MB_32B_GROUP_MB11_32B_WORD4 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word4`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD4")] -pub type Mb32bGroupMb11_32bWord4 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word4; -#[doc = "MB_16B_GROUP_MB19_16B_WORD0 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD0")] -pub type Mb16bGroupMb19_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 19 WORD_16B Register"] -pub mod mb_16b_group_mb19_16b_word0; -#[doc = "MB_8B_GROUP_MB29_8B_CS (rw) register accessor: Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB29_8B_CS")] -pub type Mb8bGroupMb29_8bCs = crate::Reg; -#[doc = "Message Buffer 29 CS Register"] -pub mod mb_8b_group_mb29_8b_cs; -#[doc = "MB_64B_GROUP_MB6_64B_WORD6 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word6`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD6")] -pub type Mb64bGroupMb6_64bWord6 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word6; -#[doc = "MB_GROUP_ID29 (rw) register accessor: Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id29`] module"] -#[doc(alias = "MB_GROUP_ID29")] -pub type MbGroupId29 = crate::Reg; -#[doc = "Message Buffer 29 ID Register"] -pub mod mb_group_id29; -#[doc = "MB_32B_GROUP_MB11_32B_WORD5 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word5`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD5")] -pub type Mb32bGroupMb11_32bWord5 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word5; -#[doc = "MB_16B_GROUP_MB19_16B_WORD1 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD1")] -pub type Mb16bGroupMb19_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 19 WORD_16B Register"] -pub mod mb_16b_group_mb19_16b_word1; -#[doc = "MB_8B_GROUP_MB29_8B_ID (rw) register accessor: Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB29_8B_ID")] -pub type Mb8bGroupMb29_8bId = crate::Reg; -#[doc = "Message Buffer 29 ID Register"] -pub mod mb_8b_group_mb29_8b_id; -#[doc = "MB_64B_GROUP_MB6_64B_WORD7 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word7`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD7")] -pub type Mb64bGroupMb6_64bWord7 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word7; -#[doc = "MB_32B_GROUP_MB11_32B_WORD6 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word6`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD6")] -pub type Mb32bGroupMb11_32bWord6 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word6; -#[doc = "MB_16B_GROUP_MB19_16B_WORD2 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD2")] -pub type Mb16bGroupMb19_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 19 WORD_16B Register"] -pub mod mb_16b_group_mb19_16b_word2; -#[doc = "MB_8B_GROUP_MB29_8B_WORD0 (rw) register accessor: Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB29_8B_WORD0")] -pub type Mb8bGroupMb29_8bWord0 = crate::Reg; -#[doc = "Message Buffer 29 WORD_8B Register"] -pub mod mb_8b_group_mb29_8b_word0; -#[doc = "MB_64B_GROUP_MB6_64B_WORD8 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word8`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD8")] -pub type Mb64bGroupMb6_64bWord8 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word8; -#[doc = "MB_GROUP_WORD029 (rw) register accessor: Message Buffer 29 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word029::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word029::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word029`] module"] -#[doc(alias = "MB_GROUP_WORD029")] -pub type MbGroupWord029 = crate::Reg; -#[doc = "Message Buffer 29 WORD0 Register"] -pub mod mb_group_word029; -#[doc = "MB_32B_GROUP_MB11_32B_WORD7 (rw) register accessor: Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_32b_group_mb11_32b_word7`] module"] -#[doc(alias = "MB_32B_GROUP_MB11_32B_WORD7")] -pub type Mb32bGroupMb11_32bWord7 = - crate::Reg; -#[doc = "Message Buffer 11 WORD_32B Register"] -pub mod mb_32b_group_mb11_32b_word7; -#[doc = "MB_16B_GROUP_MB19_16B_WORD3 (rw) register accessor: Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb19_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB19_16B_WORD3")] -pub type Mb16bGroupMb19_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 19 WORD_16B Register"] -pub mod mb_16b_group_mb19_16b_word3; -#[doc = "MB_8B_GROUP_MB29_8B_WORD1 (rw) register accessor: Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb29_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB29_8B_WORD1")] -pub type Mb8bGroupMb29_8bWord1 = crate::Reg; -#[doc = "Message Buffer 29 WORD_8B Register"] -pub mod mb_8b_group_mb29_8b_word1; -#[doc = "MB_64B_GROUP_MB6_64B_WORD9 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word9`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD9")] -pub type Mb64bGroupMb6_64bWord9 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word9; -#[doc = "MB_GROUP_WORD129 (rw) register accessor: Message Buffer 29 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word129::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word129::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word129`] module"] -#[doc(alias = "MB_GROUP_WORD129")] -pub type MbGroupWord129 = crate::Reg; -#[doc = "Message Buffer 29 WORD1 Register"] -pub mod mb_group_word129; -#[doc = "MB_GROUP_CS30 (rw) register accessor: Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs30`] module"] -#[doc(alias = "MB_GROUP_CS30")] -pub type MbGroupCs30 = crate::Reg; -#[doc = "Message Buffer 30 CS Register"] -pub mod mb_group_cs30; -#[doc = "MB_16B_GROUP_MB20_16B_CS (rw) register accessor: Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_cs`] module"] -#[doc(alias = "MB_16B_GROUP_MB20_16B_CS")] -pub type Mb16bGroupMb20_16bCs = crate::Reg; -#[doc = "Message Buffer 20 CS Register"] -pub mod mb_16b_group_mb20_16b_cs; -#[doc = "MB_8B_GROUP_MB30_8B_CS (rw) register accessor: Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB30_8B_CS")] -pub type Mb8bGroupMb30_8bCs = crate::Reg; -#[doc = "Message Buffer 30 CS Register"] -pub mod mb_8b_group_mb30_8b_cs; -#[doc = "MB_64B_GROUP_MB6_64B_WORD10 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word10`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD10")] -pub type Mb64bGroupMb6_64bWord10 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word10; -#[doc = "MB_GROUP_ID30 (rw) register accessor: Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id30`] module"] -#[doc(alias = "MB_GROUP_ID30")] -pub type MbGroupId30 = crate::Reg; -#[doc = "Message Buffer 30 ID Register"] -pub mod mb_group_id30; -#[doc = "MB_16B_GROUP_MB20_16B_ID (rw) register accessor: Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_id`] module"] -#[doc(alias = "MB_16B_GROUP_MB20_16B_ID")] -pub type Mb16bGroupMb20_16bId = crate::Reg; -#[doc = "Message Buffer 20 ID Register"] -pub mod mb_16b_group_mb20_16b_id; -#[doc = "MB_8B_GROUP_MB30_8B_ID (rw) register accessor: Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB30_8B_ID")] -pub type Mb8bGroupMb30_8bId = crate::Reg; -#[doc = "Message Buffer 30 ID Register"] -pub mod mb_8b_group_mb30_8b_id; -#[doc = "MB_64B_GROUP_MB6_64B_WORD11 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word11`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD11")] -pub type Mb64bGroupMb6_64bWord11 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word11; -#[doc = "MB_16B_GROUP_MB20_16B_WORD0 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word0`] module"] -#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD0")] -pub type Mb16bGroupMb20_16bWord0 = - crate::Reg; -#[doc = "Message Buffer 20 WORD_16B Register"] -pub mod mb_16b_group_mb20_16b_word0; -#[doc = "MB_8B_GROUP_MB30_8B_WORD0 (rw) register accessor: Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB30_8B_WORD0")] -pub type Mb8bGroupMb30_8bWord0 = crate::Reg; -#[doc = "Message Buffer 30 WORD_8B Register"] -pub mod mb_8b_group_mb30_8b_word0; -#[doc = "MB_64B_GROUP_MB6_64B_WORD12 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word12`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD12")] -pub type Mb64bGroupMb6_64bWord12 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word12; -#[doc = "MB_GROUP_WORD030 (rw) register accessor: Message Buffer 30 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word030::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word030::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word030`] module"] -#[doc(alias = "MB_GROUP_WORD030")] -pub type MbGroupWord030 = crate::Reg; -#[doc = "Message Buffer 30 WORD0 Register"] -pub mod mb_group_word030; -#[doc = "MB_16B_GROUP_MB20_16B_WORD1 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word1`] module"] -#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD1")] -pub type Mb16bGroupMb20_16bWord1 = - crate::Reg; -#[doc = "Message Buffer 20 WORD_16B Register"] -pub mod mb_16b_group_mb20_16b_word1; -#[doc = "MB_8B_GROUP_MB30_8B_WORD1 (rw) register accessor: Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb30_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB30_8B_WORD1")] -pub type Mb8bGroupMb30_8bWord1 = crate::Reg; -#[doc = "Message Buffer 30 WORD_8B Register"] -pub mod mb_8b_group_mb30_8b_word1; -#[doc = "MB_64B_GROUP_MB6_64B_WORD13 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word13`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD13")] -pub type Mb64bGroupMb6_64bWord13 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word13; -#[doc = "MB_GROUP_WORD130 (rw) register accessor: Message Buffer 30 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word130::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word130::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word130`] module"] -#[doc(alias = "MB_GROUP_WORD130")] -pub type MbGroupWord130 = crate::Reg; -#[doc = "Message Buffer 30 WORD1 Register"] -pub mod mb_group_word130; -#[doc = "MB_GROUP_CS31 (rw) register accessor: Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_cs31`] module"] -#[doc(alias = "MB_GROUP_CS31")] -pub type MbGroupCs31 = crate::Reg; -#[doc = "Message Buffer 31 CS Register"] -pub mod mb_group_cs31; -#[doc = "MB_16B_GROUP_MB20_16B_WORD2 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word2`] module"] -#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD2")] -pub type Mb16bGroupMb20_16bWord2 = - crate::Reg; -#[doc = "Message Buffer 20 WORD_16B Register"] -pub mod mb_16b_group_mb20_16b_word2; -#[doc = "MB_8B_GROUP_MB31_8B_CS (rw) register accessor: Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_cs`] module"] -#[doc(alias = "MB_8B_GROUP_MB31_8B_CS")] -pub type Mb8bGroupMb31_8bCs = crate::Reg; -#[doc = "Message Buffer 31 CS Register"] -pub mod mb_8b_group_mb31_8b_cs; -#[doc = "MB_64B_GROUP_MB6_64B_WORD14 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word14`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD14")] -pub type Mb64bGroupMb6_64bWord14 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word14; -#[doc = "MB_GROUP_ID31 (rw) register accessor: Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_id31`] module"] -#[doc(alias = "MB_GROUP_ID31")] -pub type MbGroupId31 = crate::Reg; -#[doc = "Message Buffer 31 ID Register"] -pub mod mb_group_id31; -#[doc = "MB_16B_GROUP_MB20_16B_WORD3 (rw) register accessor: Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_16b_group_mb20_16b_word3`] module"] -#[doc(alias = "MB_16B_GROUP_MB20_16B_WORD3")] -pub type Mb16bGroupMb20_16bWord3 = - crate::Reg; -#[doc = "Message Buffer 20 WORD_16B Register"] -pub mod mb_16b_group_mb20_16b_word3; -#[doc = "MB_8B_GROUP_MB31_8B_ID (rw) register accessor: Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_id`] module"] -#[doc(alias = "MB_8B_GROUP_MB31_8B_ID")] -pub type Mb8bGroupMb31_8bId = crate::Reg; -#[doc = "Message Buffer 31 ID Register"] -pub mod mb_8b_group_mb31_8b_id; -#[doc = "MB_64B_GROUP_MB6_64B_WORD15 (rw) register accessor: Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_64b_group_mb6_64b_word15`] module"] -#[doc(alias = "MB_64B_GROUP_MB6_64B_WORD15")] -pub type Mb64bGroupMb6_64bWord15 = - crate::Reg; -#[doc = "Message Buffer 6 WORD_64B Register"] -pub mod mb_64b_group_mb6_64b_word15; -#[doc = "MB_8B_GROUP_MB31_8B_WORD0 (rw) register accessor: Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_word0`] module"] -#[doc(alias = "MB_8B_GROUP_MB31_8B_WORD0")] -pub type Mb8bGroupMb31_8bWord0 = crate::Reg; -#[doc = "Message Buffer 31 WORD_8B Register"] -pub mod mb_8b_group_mb31_8b_word0; -#[doc = "MB_GROUP_WORD031 (rw) register accessor: Message Buffer 31 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word031::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word031::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word031`] module"] -#[doc(alias = "MB_GROUP_WORD031")] -pub type MbGroupWord031 = crate::Reg; -#[doc = "Message Buffer 31 WORD0 Register"] -pub mod mb_group_word031; -#[doc = "MB_8B_GROUP_MB31_8B_WORD1 (rw) register accessor: Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_8b_group_mb31_8b_word1`] module"] -#[doc(alias = "MB_8B_GROUP_MB31_8B_WORD1")] -pub type Mb8bGroupMb31_8bWord1 = crate::Reg; -#[doc = "Message Buffer 31 WORD_8B Register"] -pub mod mb_8b_group_mb31_8b_word1; -#[doc = "MB_GROUP_WORD131 (rw) register accessor: Message Buffer 31 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word131::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word131::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_group_word131`] module"] -#[doc(alias = "MB_GROUP_WORD131")] -pub type MbGroupWord131 = crate::Reg; -#[doc = "Message Buffer 31 WORD1 Register"] -pub mod mb_group_word131; -#[doc = "RXIMR (rw) register accessor: Receive Individual Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rximr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rximr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rximr`] module"] -#[doc(alias = "RXIMR")] -pub type Rximr = crate::Reg; -#[doc = "Receive Individual Mask"] -pub mod rximr; -#[doc = "CTRL1_PN (rw) register accessor: Pretended Networking Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1_pn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1_pn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1_pn`] module"] -#[doc(alias = "CTRL1_PN")] -pub type Ctrl1Pn = crate::Reg; -#[doc = "Pretended Networking Control 1"] -pub mod ctrl1_pn; -#[doc = "CTRL2_PN (rw) register accessor: Pretended Networking Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2_pn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2_pn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2_pn`] module"] -#[doc(alias = "CTRL2_PN")] -pub type Ctrl2Pn = crate::Reg; -#[doc = "Pretended Networking Control 2"] -pub mod ctrl2_pn; -#[doc = "WU_MTC (rw) register accessor: Pretended Networking Wake-Up Match\n\nYou can [`read`](crate::Reg::read) this register and get [`wu_mtc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wu_mtc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wu_mtc`] module"] -#[doc(alias = "WU_MTC")] -pub type WuMtc = crate::Reg; -#[doc = "Pretended Networking Wake-Up Match"] -pub mod wu_mtc; -#[doc = "FLT_ID1 (rw) register accessor: Pretended Networking ID Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flt_id1`] module"] -#[doc(alias = "FLT_ID1")] -pub type FltId1 = crate::Reg; -#[doc = "Pretended Networking ID Filter 1"] -pub mod flt_id1; -#[doc = "FLT_DLC (rw) register accessor: Pretended Networking Data Length Code (DLC) Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_dlc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_dlc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flt_dlc`] module"] -#[doc(alias = "FLT_DLC")] -pub type FltDlc = crate::Reg; -#[doc = "Pretended Networking Data Length Code (DLC) Filter"] -pub mod flt_dlc; -#[doc = "PL1_LO (rw) register accessor: Pretended Networking Payload Low Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_lo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_lo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl1_lo`] module"] -#[doc(alias = "PL1_LO")] -pub type Pl1Lo = crate::Reg; -#[doc = "Pretended Networking Payload Low Filter 1"] -pub mod pl1_lo; -#[doc = "PL1_HI (rw) register accessor: Pretended Networking Payload High Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl1_hi`] module"] -#[doc(alias = "PL1_HI")] -pub type Pl1Hi = crate::Reg; -#[doc = "Pretended Networking Payload High Filter 1"] -pub mod pl1_hi; -#[doc = "FLT_ID2_IDMASK (rw) register accessor: Pretended Networking ID Filter 2 or ID Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id2_idmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id2_idmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flt_id2_idmask`] module"] -#[doc(alias = "FLT_ID2_IDMASK")] -pub type FltId2Idmask = crate::Reg; -#[doc = "Pretended Networking ID Filter 2 or ID Mask"] -pub mod flt_id2_idmask; -#[doc = "PL2_PLMASK_LO (rw) register accessor: Pretended Networking Payload Low Filter 2 and Payload Low Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_lo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_lo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl2_plmask_lo`] module"] -#[doc(alias = "PL2_PLMASK_LO")] -pub type Pl2PlmaskLo = crate::Reg; -#[doc = "Pretended Networking Payload Low Filter 2 and Payload Low Mask"] -pub mod pl2_plmask_lo; -#[doc = "PL2_PLMASK_HI (rw) register accessor: Pretended Networking Payload High Filter 2 and Payload High Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pl2_plmask_hi`] module"] -#[doc(alias = "PL2_PLMASK_HI")] -pub type Pl2PlmaskHi = crate::Reg; -#[doc = "Pretended Networking Payload High Filter 2 and Payload High Mask"] -pub mod pl2_plmask_hi; -#[doc = "Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] -pub use self::wmb::Wmb; -#[doc = r"Cluster"] -#[doc = "Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] -pub mod wmb; -#[doc = "EPRS (rw) register accessor: Enhanced CAN Bit Timing Prescalers\n\nYou can [`read`](crate::Reg::read) this register and get [`eprs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eprs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eprs`] module"] -#[doc(alias = "EPRS")] -pub type Eprs = crate::Reg; -#[doc = "Enhanced CAN Bit Timing Prescalers"] -pub mod eprs; -#[doc = "ENCBT (rw) register accessor: Enhanced Nominal CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`encbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`encbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@encbt`] module"] -#[doc(alias = "ENCBT")] -pub type Encbt = crate::Reg; -#[doc = "Enhanced Nominal CAN Bit Timing"] -pub mod encbt; -#[doc = "EDCBT (rw) register accessor: Enhanced Data Phase CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`edcbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edcbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edcbt`] module"] -#[doc(alias = "EDCBT")] -pub type Edcbt = crate::Reg; -#[doc = "Enhanced Data Phase CAN Bit Timing"] -pub mod edcbt; -#[doc = "ETDC (rw) register accessor: Enhanced Transceiver Delay Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`etdc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etdc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etdc`] module"] -#[doc(alias = "ETDC")] -pub type Etdc = crate::Reg; -#[doc = "Enhanced Transceiver Delay Compensation"] -pub mod etdc; -#[doc = "FDCTRL (rw) register accessor: CAN FD Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fdctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdctrl`] module"] -#[doc(alias = "FDCTRL")] -pub type Fdctrl = crate::Reg; -#[doc = "CAN FD Control"] -pub mod fdctrl; -#[doc = "FDCBT (rw) register accessor: CAN FD Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcbt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdcbt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdcbt`] module"] -#[doc(alias = "FDCBT")] -pub type Fdcbt = crate::Reg; -#[doc = "CAN FD Bit Timing"] -pub mod fdcbt; -#[doc = "FDCRC (r) register accessor: CAN FD CRC\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcrc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdcrc`] module"] -#[doc(alias = "FDCRC")] -pub type Fdcrc = crate::Reg; -#[doc = "CAN FD CRC"] -pub mod fdcrc; -#[doc = "ERFCR (rw) register accessor: Enhanced RX FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`erfcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erfcr`] module"] -#[doc(alias = "ERFCR")] -pub type Erfcr = crate::Reg; -#[doc = "Enhanced RX FIFO Control"] -pub mod erfcr; -#[doc = "ERFIER (rw) register accessor: Enhanced RX FIFO Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erfier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erfier`] module"] -#[doc(alias = "ERFIER")] -pub type Erfier = crate::Reg; -#[doc = "Enhanced RX FIFO Interrupt Enable"] -pub mod erfier; -#[doc = "ERFSR (rw) register accessor: Enhanced RX FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`erfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erfsr`] module"] -#[doc(alias = "ERFSR")] -pub type Erfsr = crate::Reg; -#[doc = "Enhanced RX FIFO Status"] -pub mod erfsr; -#[doc = "ERFFEL (rw) register accessor: Enhanced RX FIFO Filter Element\n\nYou can [`read`](crate::Reg::read) this register and get [`erffel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erffel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erffel`] module"] -#[doc(alias = "ERFFEL")] -pub type Erffel = crate::Reg; -#[doc = "Enhanced RX FIFO Filter Element"] -pub mod erffel; diff --git a/mcxa276-pac/src/can0/cbt.rs b/mcxa276-pac/src/can0/cbt.rs deleted file mode 100644 index 674a3e036..000000000 --- a/mcxa276-pac/src/can0/cbt.rs +++ /dev/null @@ -1,154 +0,0 @@ -#[doc = "Register `CBT` reader"] -pub type R = crate::R; -#[doc = "Register `CBT` writer"] -pub type W = crate::W; -#[doc = "Field `EPSEG2` reader - Extended Phase Segment 2"] -pub type Epseg2R = crate::FieldReader; -#[doc = "Field `EPSEG2` writer - Extended Phase Segment 2"] -pub type Epseg2W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `EPSEG1` reader - Extended Phase Segment 1"] -pub type Epseg1R = crate::FieldReader; -#[doc = "Field `EPSEG1` writer - Extended Phase Segment 1"] -pub type Epseg1W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `EPROPSEG` reader - Extended Propagation Segment"] -pub type EpropsegR = crate::FieldReader; -#[doc = "Field `EPROPSEG` writer - Extended Propagation Segment"] -pub type EpropsegW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `ERJW` reader - Extended Resync Jump Width"] -pub type ErjwR = crate::FieldReader; -#[doc = "Field `ERJW` writer - Extended Resync Jump Width"] -pub type ErjwW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `EPRESDIV` reader - Extended Prescaler Division Factor"] -pub type EpresdivR = crate::FieldReader; -#[doc = "Field `EPRESDIV` writer - Extended Prescaler Division Factor"] -pub type EpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Bit Timing Format Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Btf { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Btf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BTF` reader - Bit Timing Format Enable"] -pub type BtfR = crate::BitReader; -impl BtfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Btf { - match self.bits { - false => Btf::Disable, - true => Btf::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Btf::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Btf::Enable - } -} -#[doc = "Field `BTF` writer - Bit Timing Format Enable"] -pub type BtfW<'a, REG> = crate::BitWriter<'a, REG, Btf>; -impl<'a, REG> BtfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Btf::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Btf::Enable) - } -} -impl R { - #[doc = "Bits 0:4 - Extended Phase Segment 2"] - #[inline(always)] - pub fn epseg2(&self) -> Epseg2R { - Epseg2R::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:9 - Extended Phase Segment 1"] - #[inline(always)] - pub fn epseg1(&self) -> Epseg1R { - Epseg1R::new(((self.bits >> 5) & 0x1f) as u8) - } - #[doc = "Bits 10:15 - Extended Propagation Segment"] - #[inline(always)] - pub fn epropseg(&self) -> EpropsegR { - EpropsegR::new(((self.bits >> 10) & 0x3f) as u8) - } - #[doc = "Bits 16:20 - Extended Resync Jump Width"] - #[inline(always)] - pub fn erjw(&self) -> ErjwR { - ErjwR::new(((self.bits >> 16) & 0x1f) as u8) - } - #[doc = "Bits 21:30 - Extended Prescaler Division Factor"] - #[inline(always)] - pub fn epresdiv(&self) -> EpresdivR { - EpresdivR::new(((self.bits >> 21) & 0x03ff) as u16) - } - #[doc = "Bit 31 - Bit Timing Format Enable"] - #[inline(always)] - pub fn btf(&self) -> BtfR { - BtfR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Extended Phase Segment 2"] - #[inline(always)] - pub fn epseg2(&mut self) -> Epseg2W { - Epseg2W::new(self, 0) - } - #[doc = "Bits 5:9 - Extended Phase Segment 1"] - #[inline(always)] - pub fn epseg1(&mut self) -> Epseg1W { - Epseg1W::new(self, 5) - } - #[doc = "Bits 10:15 - Extended Propagation Segment"] - #[inline(always)] - pub fn epropseg(&mut self) -> EpropsegW { - EpropsegW::new(self, 10) - } - #[doc = "Bits 16:20 - Extended Resync Jump Width"] - #[inline(always)] - pub fn erjw(&mut self) -> ErjwW { - ErjwW::new(self, 16) - } - #[doc = "Bits 21:30 - Extended Prescaler Division Factor"] - #[inline(always)] - pub fn epresdiv(&mut self) -> EpresdivW { - EpresdivW::new(self, 21) - } - #[doc = "Bit 31 - Bit Timing Format Enable"] - #[inline(always)] - pub fn btf(&mut self) -> BtfW { - BtfW::new(self, 31) - } -} -#[doc = "CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`cbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CbtSpec; -impl crate::RegisterSpec for CbtSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cbt::R`](R) reader structure"] -impl crate::Readable for CbtSpec {} -#[doc = "`write(|w| ..)` method takes [`cbt::W`](W) writer structure"] -impl crate::Writable for CbtSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CBT to value 0"] -impl crate::Resettable for CbtSpec {} diff --git a/mcxa276-pac/src/can0/crcr.rs b/mcxa276-pac/src/can0/crcr.rs deleted file mode 100644 index 1a5388f16..000000000 --- a/mcxa276-pac/src/can0/crcr.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `CRCR` reader"] -pub type R = crate::R; -#[doc = "Field `TXCRC` reader - Transmitted CRC value"] -pub type TxcrcR = crate::FieldReader; -#[doc = "Field `MBCRC` reader - CRC Message Buffer"] -pub type MbcrcR = crate::FieldReader; -impl R { - #[doc = "Bits 0:14 - Transmitted CRC value"] - #[inline(always)] - pub fn txcrc(&self) -> TxcrcR { - TxcrcR::new((self.bits & 0x7fff) as u16) - } - #[doc = "Bits 16:22 - CRC Message Buffer"] - #[inline(always)] - pub fn mbcrc(&self) -> MbcrcR { - MbcrcR::new(((self.bits >> 16) & 0x7f) as u8) - } -} -#[doc = "Cyclic Redundancy Check\n\nYou can [`read`](crate::Reg::read) this register and get [`crcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CrcrSpec; -impl crate::RegisterSpec for CrcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`crcr::R`](R) reader structure"] -impl crate::Readable for CrcrSpec {} -#[doc = "`reset()` method sets CRCR to value 0"] -impl crate::Resettable for CrcrSpec {} diff --git a/mcxa276-pac/src/can0/ctrl1.rs b/mcxa276-pac/src/can0/ctrl1.rs deleted file mode 100644 index 02c6ef133..000000000 --- a/mcxa276-pac/src/can0/ctrl1.rs +++ /dev/null @@ -1,721 +0,0 @@ -#[doc = "Register `CTRL1` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL1` writer"] -pub type W = crate::W; -#[doc = "Field `PROPSEG` reader - Propagation Segment"] -pub type PropsegR = crate::FieldReader; -#[doc = "Field `PROPSEG` writer - Propagation Segment"] -pub type PropsegW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Listen-Only Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lom { - #[doc = "0: Listen-Only mode is deactivated."] - ListenOnlyModeDisabled = 0, - #[doc = "1: FlexCAN module operates in Listen-Only mode."] - ListenOnlyModeEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lom) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOM` reader - Listen-Only Mode"] -pub type LomR = crate::BitReader; -impl LomR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lom { - match self.bits { - false => Lom::ListenOnlyModeDisabled, - true => Lom::ListenOnlyModeEnabled, - } - } - #[doc = "Listen-Only mode is deactivated."] - #[inline(always)] - pub fn is_listen_only_mode_disabled(&self) -> bool { - *self == Lom::ListenOnlyModeDisabled - } - #[doc = "FlexCAN module operates in Listen-Only mode."] - #[inline(always)] - pub fn is_listen_only_mode_enabled(&self) -> bool { - *self == Lom::ListenOnlyModeEnabled - } -} -#[doc = "Field `LOM` writer - Listen-Only Mode"] -pub type LomW<'a, REG> = crate::BitWriter<'a, REG, Lom>; -impl<'a, REG> LomW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Listen-Only mode is deactivated."] - #[inline(always)] - pub fn listen_only_mode_disabled(self) -> &'a mut crate::W { - self.variant(Lom::ListenOnlyModeDisabled) - } - #[doc = "FlexCAN module operates in Listen-Only mode."] - #[inline(always)] - pub fn listen_only_mode_enabled(self) -> &'a mut crate::W { - self.variant(Lom::ListenOnlyModeEnabled) - } -} -#[doc = "Lowest Buffer Transmitted First\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lbuf { - #[doc = "0: Buffer with highest priority is transmitted first."] - HighestBufferFirst = 0, - #[doc = "1: Lowest number buffer is transmitted first."] - LowestBufferFirst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lbuf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LBUF` reader - Lowest Buffer Transmitted First"] -pub type LbufR = crate::BitReader; -impl LbufR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lbuf { - match self.bits { - false => Lbuf::HighestBufferFirst, - true => Lbuf::LowestBufferFirst, - } - } - #[doc = "Buffer with highest priority is transmitted first."] - #[inline(always)] - pub fn is_highest_buffer_first(&self) -> bool { - *self == Lbuf::HighestBufferFirst - } - #[doc = "Lowest number buffer is transmitted first."] - #[inline(always)] - pub fn is_lowest_buffer_first(&self) -> bool { - *self == Lbuf::LowestBufferFirst - } -} -#[doc = "Field `LBUF` writer - Lowest Buffer Transmitted First"] -pub type LbufW<'a, REG> = crate::BitWriter<'a, REG, Lbuf>; -impl<'a, REG> LbufW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Buffer with highest priority is transmitted first."] - #[inline(always)] - pub fn highest_buffer_first(self) -> &'a mut crate::W { - self.variant(Lbuf::HighestBufferFirst) - } - #[doc = "Lowest number buffer is transmitted first."] - #[inline(always)] - pub fn lowest_buffer_first(self) -> &'a mut crate::W { - self.variant(Lbuf::LowestBufferFirst) - } -} -#[doc = "Timer Sync\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tsyn { - #[doc = "0: Disable"] - TimerSyncDisabled = 0, - #[doc = "1: Enable"] - TimerSyncEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tsyn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TSYN` reader - Timer Sync"] -pub type TsynR = crate::BitReader; -impl TsynR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tsyn { - match self.bits { - false => Tsyn::TimerSyncDisabled, - true => Tsyn::TimerSyncEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_timer_sync_disabled(&self) -> bool { - *self == Tsyn::TimerSyncDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_timer_sync_enabled(&self) -> bool { - *self == Tsyn::TimerSyncEnabled - } -} -#[doc = "Field `TSYN` writer - Timer Sync"] -pub type TsynW<'a, REG> = crate::BitWriter<'a, REG, Tsyn>; -impl<'a, REG> TsynW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn timer_sync_disabled(self) -> &'a mut crate::W { - self.variant(Tsyn::TimerSyncDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn timer_sync_enabled(self) -> &'a mut crate::W { - self.variant(Tsyn::TimerSyncEnabled) - } -} -#[doc = "Bus Off Recovery\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Boffrec { - #[doc = "0: Enabled"] - AutoRecoverEnabled = 0, - #[doc = "1: Disabled"] - AutoRecoverDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Boffrec) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BOFFREC` reader - Bus Off Recovery"] -pub type BoffrecR = crate::BitReader; -impl BoffrecR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Boffrec { - match self.bits { - false => Boffrec::AutoRecoverEnabled, - true => Boffrec::AutoRecoverDisabled, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_auto_recover_enabled(&self) -> bool { - *self == Boffrec::AutoRecoverEnabled - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_auto_recover_disabled(&self) -> bool { - *self == Boffrec::AutoRecoverDisabled - } -} -#[doc = "Field `BOFFREC` writer - Bus Off Recovery"] -pub type BoffrecW<'a, REG> = crate::BitWriter<'a, REG, Boffrec>; -impl<'a, REG> BoffrecW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enabled"] - #[inline(always)] - pub fn auto_recover_enabled(self) -> &'a mut crate::W { - self.variant(Boffrec::AutoRecoverEnabled) - } - #[doc = "Disabled"] - #[inline(always)] - pub fn auto_recover_disabled(self) -> &'a mut crate::W { - self.variant(Boffrec::AutoRecoverDisabled) - } -} -#[doc = "CAN Bit Sampling\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Smp { - #[doc = "0: One sample is used to determine the bit value."] - OneSample = 0, - #[doc = "1: Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples. A majority rule is used."] - ThreeSample = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Smp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SMP` reader - CAN Bit Sampling"] -pub type SmpR = crate::BitReader; -impl SmpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Smp { - match self.bits { - false => Smp::OneSample, - true => Smp::ThreeSample, - } - } - #[doc = "One sample is used to determine the bit value."] - #[inline(always)] - pub fn is_one_sample(&self) -> bool { - *self == Smp::OneSample - } - #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples. A majority rule is used."] - #[inline(always)] - pub fn is_three_sample(&self) -> bool { - *self == Smp::ThreeSample - } -} -#[doc = "Field `SMP` writer - CAN Bit Sampling"] -pub type SmpW<'a, REG> = crate::BitWriter<'a, REG, Smp>; -impl<'a, REG> SmpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "One sample is used to determine the bit value."] - #[inline(always)] - pub fn one_sample(self) -> &'a mut crate::W { - self.variant(Smp::OneSample) - } - #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples. A majority rule is used."] - #[inline(always)] - pub fn three_sample(self) -> &'a mut crate::W { - self.variant(Smp::ThreeSample) - } -} -#[doc = "RX Warning Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rwrnmsk { - #[doc = "0: Disabled"] - RxWarningIntDisabled = 0, - #[doc = "1: Enabled"] - RxWarningIntEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rwrnmsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RWRNMSK` reader - RX Warning Interrupt Mask"] -pub type RwrnmskR = crate::BitReader; -impl RwrnmskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rwrnmsk { - match self.bits { - false => Rwrnmsk::RxWarningIntDisabled, - true => Rwrnmsk::RxWarningIntEnabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_rx_warning_int_disabled(&self) -> bool { - *self == Rwrnmsk::RxWarningIntDisabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_rx_warning_int_enabled(&self) -> bool { - *self == Rwrnmsk::RxWarningIntEnabled - } -} -#[doc = "Field `RWRNMSK` writer - RX Warning Interrupt Mask"] -pub type RwrnmskW<'a, REG> = crate::BitWriter<'a, REG, Rwrnmsk>; -impl<'a, REG> RwrnmskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn rx_warning_int_disabled(self) -> &'a mut crate::W { - self.variant(Rwrnmsk::RxWarningIntDisabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn rx_warning_int_enabled(self) -> &'a mut crate::W { - self.variant(Rwrnmsk::RxWarningIntEnabled) - } -} -#[doc = "TX Warning Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Twrnmsk { - #[doc = "0: Disabled"] - TxWarningIntDisabled = 0, - #[doc = "1: Enabled"] - TxWarningIntEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Twrnmsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TWRNMSK` reader - TX Warning Interrupt Mask"] -pub type TwrnmskR = crate::BitReader; -impl TwrnmskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Twrnmsk { - match self.bits { - false => Twrnmsk::TxWarningIntDisabled, - true => Twrnmsk::TxWarningIntEnabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_tx_warning_int_disabled(&self) -> bool { - *self == Twrnmsk::TxWarningIntDisabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_tx_warning_int_enabled(&self) -> bool { - *self == Twrnmsk::TxWarningIntEnabled - } -} -#[doc = "Field `TWRNMSK` writer - TX Warning Interrupt Mask"] -pub type TwrnmskW<'a, REG> = crate::BitWriter<'a, REG, Twrnmsk>; -impl<'a, REG> TwrnmskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn tx_warning_int_disabled(self) -> &'a mut crate::W { - self.variant(Twrnmsk::TxWarningIntDisabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn tx_warning_int_enabled(self) -> &'a mut crate::W { - self.variant(Twrnmsk::TxWarningIntEnabled) - } -} -#[doc = "Loopback Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpb { - #[doc = "0: Disabled"] - LoopbackDisabled = 0, - #[doc = "1: Enabled"] - LoopbackEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPB` reader - Loopback Mode"] -pub type LpbR = crate::BitReader; -impl LpbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpb { - match self.bits { - false => Lpb::LoopbackDisabled, - true => Lpb::LoopbackEnabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_loopback_disabled(&self) -> bool { - *self == Lpb::LoopbackDisabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_loopback_enabled(&self) -> bool { - *self == Lpb::LoopbackEnabled - } -} -#[doc = "Field `LPB` writer - Loopback Mode"] -pub type LpbW<'a, REG> = crate::BitWriter<'a, REG, Lpb>; -impl<'a, REG> LpbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn loopback_disabled(self) -> &'a mut crate::W { - self.variant(Lpb::LoopbackDisabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn loopback_enabled(self) -> &'a mut crate::W { - self.variant(Lpb::LoopbackEnabled) - } -} -#[doc = "Error Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errmsk { - #[doc = "0: Interrupt disabled"] - ErrorIntDisabled = 0, - #[doc = "1: Interrupt enabled"] - ErrorIntEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errmsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRMSK` reader - Error Interrupt Mask"] -pub type ErrmskR = crate::BitReader; -impl ErrmskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errmsk { - match self.bits { - false => Errmsk::ErrorIntDisabled, - true => Errmsk::ErrorIntEnabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_error_int_disabled(&self) -> bool { - *self == Errmsk::ErrorIntDisabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_error_int_enabled(&self) -> bool { - *self == Errmsk::ErrorIntEnabled - } -} -#[doc = "Field `ERRMSK` writer - Error Interrupt Mask"] -pub type ErrmskW<'a, REG> = crate::BitWriter<'a, REG, Errmsk>; -impl<'a, REG> ErrmskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn error_int_disabled(self) -> &'a mut crate::W { - self.variant(Errmsk::ErrorIntDisabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn error_int_enabled(self) -> &'a mut crate::W { - self.variant(Errmsk::ErrorIntEnabled) - } -} -#[doc = "Bus Off Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Boffmsk { - #[doc = "0: Interrupt disabled"] - BusOffIntDisabled = 0, - #[doc = "1: Interrupt enabled"] - BusOffIntEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Boffmsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BOFFMSK` reader - Bus Off Interrupt Mask"] -pub type BoffmskR = crate::BitReader; -impl BoffmskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Boffmsk { - match self.bits { - false => Boffmsk::BusOffIntDisabled, - true => Boffmsk::BusOffIntEnabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_bus_off_int_disabled(&self) -> bool { - *self == Boffmsk::BusOffIntDisabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_bus_off_int_enabled(&self) -> bool { - *self == Boffmsk::BusOffIntEnabled - } -} -#[doc = "Field `BOFFMSK` writer - Bus Off Interrupt Mask"] -pub type BoffmskW<'a, REG> = crate::BitWriter<'a, REG, Boffmsk>; -impl<'a, REG> BoffmskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn bus_off_int_disabled(self) -> &'a mut crate::W { - self.variant(Boffmsk::BusOffIntDisabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn bus_off_int_enabled(self) -> &'a mut crate::W { - self.variant(Boffmsk::BusOffIntEnabled) - } -} -#[doc = "Field `PSEG2` reader - Phase Segment 2"] -pub type Pseg2R = crate::FieldReader; -#[doc = "Field `PSEG2` writer - Phase Segment 2"] -pub type Pseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `PSEG1` reader - Phase Segment 1"] -pub type Pseg1R = crate::FieldReader; -#[doc = "Field `PSEG1` writer - Phase Segment 1"] -pub type Pseg1W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `RJW` reader - Resync Jump Width"] -pub type RjwR = crate::FieldReader; -#[doc = "Field `RJW` writer - Resync Jump Width"] -pub type RjwW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PRESDIV` reader - Prescaler Division Factor"] -pub type PresdivR = crate::FieldReader; -#[doc = "Field `PRESDIV` writer - Prescaler Division Factor"] -pub type PresdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:2 - Propagation Segment"] - #[inline(always)] - pub fn propseg(&self) -> PropsegR { - PropsegR::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - Listen-Only Mode"] - #[inline(always)] - pub fn lom(&self) -> LomR { - LomR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Lowest Buffer Transmitted First"] - #[inline(always)] - pub fn lbuf(&self) -> LbufR { - LbufR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Timer Sync"] - #[inline(always)] - pub fn tsyn(&self) -> TsynR { - TsynR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Bus Off Recovery"] - #[inline(always)] - pub fn boffrec(&self) -> BoffrecR { - BoffrecR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - CAN Bit Sampling"] - #[inline(always)] - pub fn smp(&self) -> SmpR { - SmpR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 10 - RX Warning Interrupt Mask"] - #[inline(always)] - pub fn rwrnmsk(&self) -> RwrnmskR { - RwrnmskR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - TX Warning Interrupt Mask"] - #[inline(always)] - pub fn twrnmsk(&self) -> TwrnmskR { - TwrnmskR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Loopback Mode"] - #[inline(always)] - pub fn lpb(&self) -> LpbR { - LpbR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 14 - Error Interrupt Mask"] - #[inline(always)] - pub fn errmsk(&self) -> ErrmskR { - ErrmskR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Bus Off Interrupt Mask"] - #[inline(always)] - pub fn boffmsk(&self) -> BoffmskR { - BoffmskR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Phase Segment 2"] - #[inline(always)] - pub fn pseg2(&self) -> Pseg2R { - Pseg2R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 19:21 - Phase Segment 1"] - #[inline(always)] - pub fn pseg1(&self) -> Pseg1R { - Pseg1R::new(((self.bits >> 19) & 7) as u8) - } - #[doc = "Bits 22:23 - Resync Jump Width"] - #[inline(always)] - pub fn rjw(&self) -> RjwR { - RjwR::new(((self.bits >> 22) & 3) as u8) - } - #[doc = "Bits 24:31 - Prescaler Division Factor"] - #[inline(always)] - pub fn presdiv(&self) -> PresdivR { - PresdivR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Propagation Segment"] - #[inline(always)] - pub fn propseg(&mut self) -> PropsegW { - PropsegW::new(self, 0) - } - #[doc = "Bit 3 - Listen-Only Mode"] - #[inline(always)] - pub fn lom(&mut self) -> LomW { - LomW::new(self, 3) - } - #[doc = "Bit 4 - Lowest Buffer Transmitted First"] - #[inline(always)] - pub fn lbuf(&mut self) -> LbufW { - LbufW::new(self, 4) - } - #[doc = "Bit 5 - Timer Sync"] - #[inline(always)] - pub fn tsyn(&mut self) -> TsynW { - TsynW::new(self, 5) - } - #[doc = "Bit 6 - Bus Off Recovery"] - #[inline(always)] - pub fn boffrec(&mut self) -> BoffrecW { - BoffrecW::new(self, 6) - } - #[doc = "Bit 7 - CAN Bit Sampling"] - #[inline(always)] - pub fn smp(&mut self) -> SmpW { - SmpW::new(self, 7) - } - #[doc = "Bit 10 - RX Warning Interrupt Mask"] - #[inline(always)] - pub fn rwrnmsk(&mut self) -> RwrnmskW { - RwrnmskW::new(self, 10) - } - #[doc = "Bit 11 - TX Warning Interrupt Mask"] - #[inline(always)] - pub fn twrnmsk(&mut self) -> TwrnmskW { - TwrnmskW::new(self, 11) - } - #[doc = "Bit 12 - Loopback Mode"] - #[inline(always)] - pub fn lpb(&mut self) -> LpbW { - LpbW::new(self, 12) - } - #[doc = "Bit 14 - Error Interrupt Mask"] - #[inline(always)] - pub fn errmsk(&mut self) -> ErrmskW { - ErrmskW::new(self, 14) - } - #[doc = "Bit 15 - Bus Off Interrupt Mask"] - #[inline(always)] - pub fn boffmsk(&mut self) -> BoffmskW { - BoffmskW::new(self, 15) - } - #[doc = "Bits 16:18 - Phase Segment 2"] - #[inline(always)] - pub fn pseg2(&mut self) -> Pseg2W { - Pseg2W::new(self, 16) - } - #[doc = "Bits 19:21 - Phase Segment 1"] - #[inline(always)] - pub fn pseg1(&mut self) -> Pseg1W { - Pseg1W::new(self, 19) - } - #[doc = "Bits 22:23 - Resync Jump Width"] - #[inline(always)] - pub fn rjw(&mut self) -> RjwW { - RjwW::new(self, 22) - } - #[doc = "Bits 24:31 - Prescaler Division Factor"] - #[inline(always)] - pub fn presdiv(&mut self) -> PresdivW { - PresdivW::new(self, 24) - } -} -#[doc = "Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctrl1Spec; -impl crate::RegisterSpec for Ctrl1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] -impl crate::Readable for Ctrl1Spec {} -#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] -impl crate::Writable for Ctrl1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL1 to value 0"] -impl crate::Resettable for Ctrl1Spec {} diff --git a/mcxa276-pac/src/can0/ctrl1_pn.rs b/mcxa276-pac/src/can0/ctrl1_pn.rs deleted file mode 100644 index d583247f9..000000000 --- a/mcxa276-pac/src/can0/ctrl1_pn.rs +++ /dev/null @@ -1,520 +0,0 @@ -#[doc = "Register `CTRL1_PN` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL1_PN` writer"] -pub type W = crate::W; -#[doc = "Filtering Combination Selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fcs { - #[doc = "0: Message ID filtering only"] - IdFiltering = 0, - #[doc = "1: Message ID filtering and payload filtering"] - IdPayloadFiltering = 1, - #[doc = "2: Message ID filtering occurring a specified number of times"] - IdFilteringNumber = 2, - #[doc = "3: Message ID filtering and payload filtering a specified number of times"] - IdPayloadFilteringNumber = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fcs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fcs { - type Ux = u8; -} -impl crate::IsEnum for Fcs {} -#[doc = "Field `FCS` reader - Filtering Combination Selection"] -pub type FcsR = crate::FieldReader; -impl FcsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fcs { - match self.bits { - 0 => Fcs::IdFiltering, - 1 => Fcs::IdPayloadFiltering, - 2 => Fcs::IdFilteringNumber, - 3 => Fcs::IdPayloadFilteringNumber, - _ => unreachable!(), - } - } - #[doc = "Message ID filtering only"] - #[inline(always)] - pub fn is_id_filtering(&self) -> bool { - *self == Fcs::IdFiltering - } - #[doc = "Message ID filtering and payload filtering"] - #[inline(always)] - pub fn is_id_payload_filtering(&self) -> bool { - *self == Fcs::IdPayloadFiltering - } - #[doc = "Message ID filtering occurring a specified number of times"] - #[inline(always)] - pub fn is_id_filtering_number(&self) -> bool { - *self == Fcs::IdFilteringNumber - } - #[doc = "Message ID filtering and payload filtering a specified number of times"] - #[inline(always)] - pub fn is_id_payload_filtering_number(&self) -> bool { - *self == Fcs::IdPayloadFilteringNumber - } -} -#[doc = "Field `FCS` writer - Filtering Combination Selection"] -pub type FcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Fcs, crate::Safe>; -impl<'a, REG> FcsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Message ID filtering only"] - #[inline(always)] - pub fn id_filtering(self) -> &'a mut crate::W { - self.variant(Fcs::IdFiltering) - } - #[doc = "Message ID filtering and payload filtering"] - #[inline(always)] - pub fn id_payload_filtering(self) -> &'a mut crate::W { - self.variant(Fcs::IdPayloadFiltering) - } - #[doc = "Message ID filtering occurring a specified number of times"] - #[inline(always)] - pub fn id_filtering_number(self) -> &'a mut crate::W { - self.variant(Fcs::IdFilteringNumber) - } - #[doc = "Message ID filtering and payload filtering a specified number of times"] - #[inline(always)] - pub fn id_payload_filtering_number(self) -> &'a mut crate::W { - self.variant(Fcs::IdPayloadFilteringNumber) - } -} -#[doc = "ID Filtering Selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Idfs { - #[doc = "0: Match ID contents to an exact target value"] - MatchExact = 0, - #[doc = "1: Match an ID value greater than or equal to a specified target value"] - MatchGte = 1, - #[doc = "2: Match an ID value smaller than or equal to a specified target value"] - MatchLte = 2, - #[doc = "3: Match an ID value within a range of values, inclusive"] - MatchRange = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Idfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Idfs { - type Ux = u8; -} -impl crate::IsEnum for Idfs {} -#[doc = "Field `IDFS` reader - ID Filtering Selection"] -pub type IdfsR = crate::FieldReader; -impl IdfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Idfs { - match self.bits { - 0 => Idfs::MatchExact, - 1 => Idfs::MatchGte, - 2 => Idfs::MatchLte, - 3 => Idfs::MatchRange, - _ => unreachable!(), - } - } - #[doc = "Match ID contents to an exact target value"] - #[inline(always)] - pub fn is_match_exact(&self) -> bool { - *self == Idfs::MatchExact - } - #[doc = "Match an ID value greater than or equal to a specified target value"] - #[inline(always)] - pub fn is_match_gte(&self) -> bool { - *self == Idfs::MatchGte - } - #[doc = "Match an ID value smaller than or equal to a specified target value"] - #[inline(always)] - pub fn is_match_lte(&self) -> bool { - *self == Idfs::MatchLte - } - #[doc = "Match an ID value within a range of values, inclusive"] - #[inline(always)] - pub fn is_match_range(&self) -> bool { - *self == Idfs::MatchRange - } -} -#[doc = "Field `IDFS` writer - ID Filtering Selection"] -pub type IdfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Idfs, crate::Safe>; -impl<'a, REG> IdfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Match ID contents to an exact target value"] - #[inline(always)] - pub fn match_exact(self) -> &'a mut crate::W { - self.variant(Idfs::MatchExact) - } - #[doc = "Match an ID value greater than or equal to a specified target value"] - #[inline(always)] - pub fn match_gte(self) -> &'a mut crate::W { - self.variant(Idfs::MatchGte) - } - #[doc = "Match an ID value smaller than or equal to a specified target value"] - #[inline(always)] - pub fn match_lte(self) -> &'a mut crate::W { - self.variant(Idfs::MatchLte) - } - #[doc = "Match an ID value within a range of values, inclusive"] - #[inline(always)] - pub fn match_range(self) -> &'a mut crate::W { - self.variant(Idfs::MatchRange) - } -} -#[doc = "Payload Filtering Selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Plfs { - #[doc = "0: Match payload contents to an exact target value"] - MatchExact = 0, - #[doc = "1: Match a payload value greater than or equal to a specified target value"] - MatchGte = 1, - #[doc = "2: Match a payload value smaller than or equal to a specified target value"] - MatchLte = 2, - #[doc = "3: Match upon a payload value within a range of values, inclusive"] - MatchRange = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Plfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Plfs { - type Ux = u8; -} -impl crate::IsEnum for Plfs {} -#[doc = "Field `PLFS` reader - Payload Filtering Selection"] -pub type PlfsR = crate::FieldReader; -impl PlfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Plfs { - match self.bits { - 0 => Plfs::MatchExact, - 1 => Plfs::MatchGte, - 2 => Plfs::MatchLte, - 3 => Plfs::MatchRange, - _ => unreachable!(), - } - } - #[doc = "Match payload contents to an exact target value"] - #[inline(always)] - pub fn is_match_exact(&self) -> bool { - *self == Plfs::MatchExact - } - #[doc = "Match a payload value greater than or equal to a specified target value"] - #[inline(always)] - pub fn is_match_gte(&self) -> bool { - *self == Plfs::MatchGte - } - #[doc = "Match a payload value smaller than or equal to a specified target value"] - #[inline(always)] - pub fn is_match_lte(&self) -> bool { - *self == Plfs::MatchLte - } - #[doc = "Match upon a payload value within a range of values, inclusive"] - #[inline(always)] - pub fn is_match_range(&self) -> bool { - *self == Plfs::MatchRange - } -} -#[doc = "Field `PLFS` writer - Payload Filtering Selection"] -pub type PlfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Plfs, crate::Safe>; -impl<'a, REG> PlfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Match payload contents to an exact target value"] - #[inline(always)] - pub fn match_exact(self) -> &'a mut crate::W { - self.variant(Plfs::MatchExact) - } - #[doc = "Match a payload value greater than or equal to a specified target value"] - #[inline(always)] - pub fn match_gte(self) -> &'a mut crate::W { - self.variant(Plfs::MatchGte) - } - #[doc = "Match a payload value smaller than or equal to a specified target value"] - #[inline(always)] - pub fn match_lte(self) -> &'a mut crate::W { - self.variant(Plfs::MatchLte) - } - #[doc = "Match upon a payload value within a range of values, inclusive"] - #[inline(always)] - pub fn match_range(self) -> &'a mut crate::W { - self.variant(Plfs::MatchRange) - } -} -#[doc = "Number of Messages Matching the Same Filtering Criteria\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Nmatch { - #[doc = "1: Once"] - Match1 = 1, - #[doc = "2: Twice"] - Match2 = 2, - #[doc = "255: 255 times"] - Match255 = 255, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Nmatch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Nmatch { - type Ux = u8; -} -impl crate::IsEnum for Nmatch {} -#[doc = "Field `NMATCH` reader - Number of Messages Matching the Same Filtering Criteria"] -pub type NmatchR = crate::FieldReader; -impl NmatchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Nmatch::Match1), - 2 => Some(Nmatch::Match2), - 255 => Some(Nmatch::Match255), - _ => None, - } - } - #[doc = "Once"] - #[inline(always)] - pub fn is_match_1(&self) -> bool { - *self == Nmatch::Match1 - } - #[doc = "Twice"] - #[inline(always)] - pub fn is_match_2(&self) -> bool { - *self == Nmatch::Match2 - } - #[doc = "255 times"] - #[inline(always)] - pub fn is_match_255(&self) -> bool { - *self == Nmatch::Match255 - } -} -#[doc = "Field `NMATCH` writer - Number of Messages Matching the Same Filtering Criteria"] -pub type NmatchW<'a, REG> = crate::FieldWriter<'a, REG, 8, Nmatch>; -impl<'a, REG> NmatchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Once"] - #[inline(always)] - pub fn match_1(self) -> &'a mut crate::W { - self.variant(Nmatch::Match1) - } - #[doc = "Twice"] - #[inline(always)] - pub fn match_2(self) -> &'a mut crate::W { - self.variant(Nmatch::Match2) - } - #[doc = "255 times"] - #[inline(always)] - pub fn match_255(self) -> &'a mut crate::W { - self.variant(Nmatch::Match255) - } -} -#[doc = "Wake-up by Matching Flag Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WumfMsk { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WumfMsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUMF_MSK` reader - Wake-up by Matching Flag Mask"] -pub type WumfMskR = crate::BitReader; -impl WumfMskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WumfMsk { - match self.bits { - false => WumfMsk::Disable, - true => WumfMsk::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == WumfMsk::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == WumfMsk::Enable - } -} -#[doc = "Field `WUMF_MSK` writer - Wake-up by Matching Flag Mask"] -pub type WumfMskW<'a, REG> = crate::BitWriter<'a, REG, WumfMsk>; -impl<'a, REG> WumfMskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(WumfMsk::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(WumfMsk::Enable) - } -} -#[doc = "Wake-up by Timeout Flag Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WtofMsk { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WtofMsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WTOF_MSK` reader - Wake-up by Timeout Flag Mask"] -pub type WtofMskR = crate::BitReader; -impl WtofMskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WtofMsk { - match self.bits { - false => WtofMsk::Disable, - true => WtofMsk::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == WtofMsk::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == WtofMsk::Enable - } -} -#[doc = "Field `WTOF_MSK` writer - Wake-up by Timeout Flag Mask"] -pub type WtofMskW<'a, REG> = crate::BitWriter<'a, REG, WtofMsk>; -impl<'a, REG> WtofMskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(WtofMsk::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(WtofMsk::Enable) - } -} -impl R { - #[doc = "Bits 0:1 - Filtering Combination Selection"] - #[inline(always)] - pub fn fcs(&self) -> FcsR { - FcsR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - ID Filtering Selection"] - #[inline(always)] - pub fn idfs(&self) -> IdfsR { - IdfsR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Payload Filtering Selection"] - #[inline(always)] - pub fn plfs(&self) -> PlfsR { - PlfsR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 8:15 - Number of Messages Matching the Same Filtering Criteria"] - #[inline(always)] - pub fn nmatch(&self) -> NmatchR { - NmatchR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bit 16 - Wake-up by Matching Flag Mask"] - #[inline(always)] - pub fn wumf_msk(&self) -> WumfMskR { - WumfMskR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Wake-up by Timeout Flag Mask"] - #[inline(always)] - pub fn wtof_msk(&self) -> WtofMskR { - WtofMskR::new(((self.bits >> 17) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - Filtering Combination Selection"] - #[inline(always)] - pub fn fcs(&mut self) -> FcsW { - FcsW::new(self, 0) - } - #[doc = "Bits 2:3 - ID Filtering Selection"] - #[inline(always)] - pub fn idfs(&mut self) -> IdfsW { - IdfsW::new(self, 2) - } - #[doc = "Bits 4:5 - Payload Filtering Selection"] - #[inline(always)] - pub fn plfs(&mut self) -> PlfsW { - PlfsW::new(self, 4) - } - #[doc = "Bits 8:15 - Number of Messages Matching the Same Filtering Criteria"] - #[inline(always)] - pub fn nmatch(&mut self) -> NmatchW { - NmatchW::new(self, 8) - } - #[doc = "Bit 16 - Wake-up by Matching Flag Mask"] - #[inline(always)] - pub fn wumf_msk(&mut self) -> WumfMskW { - WumfMskW::new(self, 16) - } - #[doc = "Bit 17 - Wake-up by Timeout Flag Mask"] - #[inline(always)] - pub fn wtof_msk(&mut self) -> WtofMskW { - WtofMskW::new(self, 17) - } -} -#[doc = "Pretended Networking Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1_pn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1_pn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctrl1PnSpec; -impl crate::RegisterSpec for Ctrl1PnSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl1_pn::R`](R) reader structure"] -impl crate::Readable for Ctrl1PnSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl1_pn::W`](W) writer structure"] -impl crate::Writable for Ctrl1PnSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL1_PN to value 0x0100"] -impl crate::Resettable for Ctrl1PnSpec { - const RESET_VALUE: u32 = 0x0100; -} diff --git a/mcxa276-pac/src/can0/ctrl2.rs b/mcxa276-pac/src/can0/ctrl2.rs deleted file mode 100644 index dddf3b20c..000000000 --- a/mcxa276-pac/src/can0/ctrl2.rs +++ /dev/null @@ -1,744 +0,0 @@ -#[doc = "Register `CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL2` writer"] -pub type W = crate::W; -#[doc = "Payload Byte and Bit Order Selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pes { - #[doc = "0: Big-endian"] - BigEnd = 0, - #[doc = "1: Little-endian"] - LittleEnd = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pes) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PES` reader - Payload Byte and Bit Order Selection"] -pub type PesR = crate::BitReader; -impl PesR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pes { - match self.bits { - false => Pes::BigEnd, - true => Pes::LittleEnd, - } - } - #[doc = "Big-endian"] - #[inline(always)] - pub fn is_big_end(&self) -> bool { - *self == Pes::BigEnd - } - #[doc = "Little-endian"] - #[inline(always)] - pub fn is_little_end(&self) -> bool { - *self == Pes::LittleEnd - } -} -#[doc = "Field `PES` writer - Payload Byte and Bit Order Selection"] -pub type PesW<'a, REG> = crate::BitWriter<'a, REG, Pes>; -impl<'a, REG> PesW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Big-endian"] - #[inline(always)] - pub fn big_end(self) -> &'a mut crate::W { - self.variant(Pes::BigEnd) - } - #[doc = "Little-endian"] - #[inline(always)] - pub fn little_end(self) -> &'a mut crate::W { - self.variant(Pes::LittleEnd) - } -} -#[doc = "ACK Suppression Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Asd { - #[doc = "0: Enabled"] - Enable = 0, - #[doc = "1: Disabled"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Asd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ASD` reader - ACK Suppression Disable"] -pub type AsdR = crate::BitReader; -impl AsdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Asd { - match self.bits { - false => Asd::Enable, - true => Asd::Disable, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Asd::Enable - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Asd::Disable - } -} -#[doc = "Field `ASD` writer - ACK Suppression Disable"] -pub type AsdW<'a, REG> = crate::BitWriter<'a, REG, Asd>; -impl<'a, REG> AsdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Asd::Enable) - } - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Asd::Disable) - } -} -#[doc = "Edge Filter Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Edfltdis { - #[doc = "0: Enabled"] - Enable = 0, - #[doc = "1: Disabled"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Edfltdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EDFLTDIS` reader - Edge Filter Disable"] -pub type EdfltdisR = crate::BitReader; -impl EdfltdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edfltdis { - match self.bits { - false => Edfltdis::Enable, - true => Edfltdis::Disable, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Edfltdis::Enable - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Edfltdis::Disable - } -} -#[doc = "Field `EDFLTDIS` writer - Edge Filter Disable"] -pub type EdfltdisW<'a, REG> = crate::BitWriter<'a, REG, Edfltdis>; -impl<'a, REG> EdfltdisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Edfltdis::Enable) - } - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Edfltdis::Disable) - } -} -#[doc = "ISO CAN FD Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isocanfden { - #[doc = "0: Disable"] - NonIso = 0, - #[doc = "1: Enable"] - Iso = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isocanfden) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISOCANFDEN` reader - ISO CAN FD Enable"] -pub type IsocanfdenR = crate::BitReader; -impl IsocanfdenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isocanfden { - match self.bits { - false => Isocanfden::NonIso, - true => Isocanfden::Iso, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_non_iso(&self) -> bool { - *self == Isocanfden::NonIso - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_iso(&self) -> bool { - *self == Isocanfden::Iso - } -} -#[doc = "Field `ISOCANFDEN` writer - ISO CAN FD Enable"] -pub type IsocanfdenW<'a, REG> = crate::BitWriter<'a, REG, Isocanfden>; -impl<'a, REG> IsocanfdenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn non_iso(self) -> &'a mut crate::W { - self.variant(Isocanfden::NonIso) - } - #[doc = "Enable"] - #[inline(always)] - pub fn iso(self) -> &'a mut crate::W { - self.variant(Isocanfden::Iso) - } -} -#[doc = "Bit Timing Expansion Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bte { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bte) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BTE` reader - Bit Timing Expansion Enable"] -pub type BteR = crate::BitReader; -impl BteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bte { - match self.bits { - false => Bte::Disable, - true => Bte::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Bte::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Bte::Enable - } -} -#[doc = "Field `BTE` writer - Bit Timing Expansion Enable"] -pub type BteW<'a, REG> = crate::BitWriter<'a, REG, Bte>; -impl<'a, REG> BteW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Bte::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Bte::Enable) - } -} -#[doc = "Protocol Exception Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Prexcen { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Prexcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PREXCEN` reader - Protocol Exception Enable"] -pub type PrexcenR = crate::BitReader; -impl PrexcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prexcen { - match self.bits { - false => Prexcen::Disable, - true => Prexcen::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Prexcen::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Prexcen::Enable - } -} -#[doc = "Field `PREXCEN` writer - Protocol Exception Enable"] -pub type PrexcenW<'a, REG> = crate::BitWriter<'a, REG, Prexcen>; -impl<'a, REG> PrexcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Prexcen::Disable) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Prexcen::Enable) - } -} -#[doc = "Entire Frame Arbitration Field Comparison Enable for RX Message Buffers\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Eacen { - #[doc = "0: Disable"] - RtrCompareNo = 0, - #[doc = "1: Enable"] - RtrCompareYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Eacen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EACEN` reader - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] -pub type EacenR = crate::BitReader; -impl EacenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Eacen { - match self.bits { - false => Eacen::RtrCompareNo, - true => Eacen::RtrCompareYes, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_rtr_compare_no(&self) -> bool { - *self == Eacen::RtrCompareNo - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_rtr_compare_yes(&self) -> bool { - *self == Eacen::RtrCompareYes - } -} -#[doc = "Field `EACEN` writer - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] -pub type EacenW<'a, REG> = crate::BitWriter<'a, REG, Eacen>; -impl<'a, REG> EacenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn rtr_compare_no(self) -> &'a mut crate::W { - self.variant(Eacen::RtrCompareNo) - } - #[doc = "Enable"] - #[inline(always)] - pub fn rtr_compare_yes(self) -> &'a mut crate::W { - self.variant(Eacen::RtrCompareYes) - } -} -#[doc = "Remote Request Storing\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rrs { - #[doc = "0: Generated"] - RemoteResponseFrameNotGenerated = 0, - #[doc = "1: Stored"] - RemoteResponseFrameGenerated = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rrs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RRS` reader - Remote Request Storing"] -pub type RrsR = crate::BitReader; -impl RrsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rrs { - match self.bits { - false => Rrs::RemoteResponseFrameNotGenerated, - true => Rrs::RemoteResponseFrameGenerated, - } - } - #[doc = "Generated"] - #[inline(always)] - pub fn is_remote_response_frame_not_generated(&self) -> bool { - *self == Rrs::RemoteResponseFrameNotGenerated - } - #[doc = "Stored"] - #[inline(always)] - pub fn is_remote_response_frame_generated(&self) -> bool { - *self == Rrs::RemoteResponseFrameGenerated - } -} -#[doc = "Field `RRS` writer - Remote Request Storing"] -pub type RrsW<'a, REG> = crate::BitWriter<'a, REG, Rrs>; -impl<'a, REG> RrsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Generated"] - #[inline(always)] - pub fn remote_response_frame_not_generated(self) -> &'a mut crate::W { - self.variant(Rrs::RemoteResponseFrameNotGenerated) - } - #[doc = "Stored"] - #[inline(always)] - pub fn remote_response_frame_generated(self) -> &'a mut crate::W { - self.variant(Rrs::RemoteResponseFrameGenerated) - } -} -#[doc = "Message Buffers Reception Priority\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mrp { - #[doc = "0: Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers."] - Id1 = 0, - #[doc = "1: Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO."] - Id3 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mrp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MRP` reader - Message Buffers Reception Priority"] -pub type MrpR = crate::BitReader; -impl MrpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mrp { - match self.bits { - false => Mrp::Id1, - true => Mrp::Id3, - } - } - #[doc = "Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers."] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Mrp::Id1 - } - #[doc = "Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO."] - #[inline(always)] - pub fn is_id3(&self) -> bool { - *self == Mrp::Id3 - } -} -#[doc = "Field `MRP` writer - Message Buffers Reception Priority"] -pub type MrpW<'a, REG> = crate::BitWriter<'a, REG, Mrp>; -impl<'a, REG> MrpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers."] - #[inline(always)] - pub fn id1(self) -> &'a mut crate::W { - self.variant(Mrp::Id1) - } - #[doc = "Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO."] - #[inline(always)] - pub fn id3(self) -> &'a mut crate::W { - self.variant(Mrp::Id3) - } -} -#[doc = "Field `TASD` reader - Transmission Arbitration Start Delay"] -pub type TasdR = crate::FieldReader; -#[doc = "Field `TASD` writer - Transmission Arbitration Start Delay"] -pub type TasdW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `RFFN` reader - Number of Legacy Receive FIFO Filters"] -pub type RffnR = crate::FieldReader; -#[doc = "Field `RFFN` writer - Number of Legacy Receive FIFO Filters"] -pub type RffnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Bus Off Done Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Boffdonemsk { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Boffdonemsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BOFFDONEMSK` reader - Bus Off Done Interrupt Mask"] -pub type BoffdonemskR = crate::BitReader; -impl BoffdonemskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Boffdonemsk { - match self.bits { - false => Boffdonemsk::Disable, - true => Boffdonemsk::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Boffdonemsk::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Boffdonemsk::Enable - } -} -#[doc = "Field `BOFFDONEMSK` writer - Bus Off Done Interrupt Mask"] -pub type BoffdonemskW<'a, REG> = crate::BitWriter<'a, REG, Boffdonemsk>; -impl<'a, REG> BoffdonemskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Boffdonemsk::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Boffdonemsk::Enable) - } -} -#[doc = "Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ErrmskFast { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ErrmskFast) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRMSK_FAST` reader - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] -pub type ErrmskFastR = crate::BitReader; -impl ErrmskFastR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ErrmskFast { - match self.bits { - false => ErrmskFast::Disable, - true => ErrmskFast::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == ErrmskFast::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == ErrmskFast::Enable - } -} -#[doc = "Field `ERRMSK_FAST` writer - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] -pub type ErrmskFastW<'a, REG> = crate::BitWriter<'a, REG, ErrmskFast>; -impl<'a, REG> ErrmskFastW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(ErrmskFast::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(ErrmskFast::Enable) - } -} -impl R { - #[doc = "Bit 0 - Payload Byte and Bit Order Selection"] - #[inline(always)] - pub fn pes(&self) -> PesR { - PesR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - ACK Suppression Disable"] - #[inline(always)] - pub fn asd(&self) -> AsdR { - AsdR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 11 - Edge Filter Disable"] - #[inline(always)] - pub fn edfltdis(&self) -> EdfltdisR { - EdfltdisR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - ISO CAN FD Enable"] - #[inline(always)] - pub fn isocanfden(&self) -> IsocanfdenR { - IsocanfdenR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Bit Timing Expansion Enable"] - #[inline(always)] - pub fn bte(&self) -> BteR { - BteR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Protocol Exception Enable"] - #[inline(always)] - pub fn prexcen(&self) -> PrexcenR { - PrexcenR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 16 - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] - #[inline(always)] - pub fn eacen(&self) -> EacenR { - EacenR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Remote Request Storing"] - #[inline(always)] - pub fn rrs(&self) -> RrsR { - RrsR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Message Buffers Reception Priority"] - #[inline(always)] - pub fn mrp(&self) -> MrpR { - MrpR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bits 19:23 - Transmission Arbitration Start Delay"] - #[inline(always)] - pub fn tasd(&self) -> TasdR { - TasdR::new(((self.bits >> 19) & 0x1f) as u8) - } - #[doc = "Bits 24:27 - Number of Legacy Receive FIFO Filters"] - #[inline(always)] - pub fn rffn(&self) -> RffnR { - RffnR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 30 - Bus Off Done Interrupt Mask"] - #[inline(always)] - pub fn boffdonemsk(&self) -> BoffdonemskR { - BoffdonemskR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] - #[inline(always)] - pub fn errmsk_fast(&self) -> ErrmskFastR { - ErrmskFastR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Payload Byte and Bit Order Selection"] - #[inline(always)] - pub fn pes(&mut self) -> PesW { - PesW::new(self, 0) - } - #[doc = "Bit 1 - ACK Suppression Disable"] - #[inline(always)] - pub fn asd(&mut self) -> AsdW { - AsdW::new(self, 1) - } - #[doc = "Bit 11 - Edge Filter Disable"] - #[inline(always)] - pub fn edfltdis(&mut self) -> EdfltdisW { - EdfltdisW::new(self, 11) - } - #[doc = "Bit 12 - ISO CAN FD Enable"] - #[inline(always)] - pub fn isocanfden(&mut self) -> IsocanfdenW { - IsocanfdenW::new(self, 12) - } - #[doc = "Bit 13 - Bit Timing Expansion Enable"] - #[inline(always)] - pub fn bte(&mut self) -> BteW { - BteW::new(self, 13) - } - #[doc = "Bit 14 - Protocol Exception Enable"] - #[inline(always)] - pub fn prexcen(&mut self) -> PrexcenW { - PrexcenW::new(self, 14) - } - #[doc = "Bit 16 - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers"] - #[inline(always)] - pub fn eacen(&mut self) -> EacenW { - EacenW::new(self, 16) - } - #[doc = "Bit 17 - Remote Request Storing"] - #[inline(always)] - pub fn rrs(&mut self) -> RrsW { - RrsW::new(self, 17) - } - #[doc = "Bit 18 - Message Buffers Reception Priority"] - #[inline(always)] - pub fn mrp(&mut self) -> MrpW { - MrpW::new(self, 18) - } - #[doc = "Bits 19:23 - Transmission Arbitration Start Delay"] - #[inline(always)] - pub fn tasd(&mut self) -> TasdW { - TasdW::new(self, 19) - } - #[doc = "Bits 24:27 - Number of Legacy Receive FIFO Filters"] - #[inline(always)] - pub fn rffn(&mut self) -> RffnW { - RffnW::new(self, 24) - } - #[doc = "Bit 30 - Bus Off Done Interrupt Mask"] - #[inline(always)] - pub fn boffdonemsk(&mut self) -> BoffdonemskW { - BoffdonemskW::new(self, 30) - } - #[doc = "Bit 31 - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames"] - #[inline(always)] - pub fn errmsk_fast(&mut self) -> ErrmskFastW { - ErrmskFastW::new(self, 31) - } -} -#[doc = "Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctrl2Spec; -impl crate::RegisterSpec for Ctrl2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"] -impl crate::Readable for Ctrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"] -impl crate::Writable for Ctrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL2 to value 0x00a0_0000"] -impl crate::Resettable for Ctrl2Spec { - const RESET_VALUE: u32 = 0x00a0_0000; -} diff --git a/mcxa276-pac/src/can0/ctrl2_pn.rs b/mcxa276-pac/src/can0/ctrl2_pn.rs deleted file mode 100644 index 8a2e137dd..000000000 --- a/mcxa276-pac/src/can0/ctrl2_pn.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CTRL2_PN` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL2_PN` writer"] -pub type W = crate::W; -#[doc = "Field `MATCHTO` reader - Timeout for No Message Matching the Filtering Criteria"] -pub type MatchtoR = crate::FieldReader; -#[doc = "Field `MATCHTO` writer - Timeout for No Message Matching the Filtering Criteria"] -pub type MatchtoW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"] - #[inline(always)] - pub fn matchto(&self) -> MatchtoR { - MatchtoR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"] - #[inline(always)] - pub fn matchto(&mut self) -> MatchtoW { - MatchtoW::new(self, 0) - } -} -#[doc = "Pretended Networking Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2_pn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2_pn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctrl2PnSpec; -impl crate::RegisterSpec for Ctrl2PnSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl2_pn::R`](R) reader structure"] -impl crate::Readable for Ctrl2PnSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl2_pn::W`](W) writer structure"] -impl crate::Writable for Ctrl2PnSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL2_PN to value 0"] -impl crate::Resettable for Ctrl2PnSpec {} diff --git a/mcxa276-pac/src/can0/ecr.rs b/mcxa276-pac/src/can0/ecr.rs deleted file mode 100644 index a19c075aa..000000000 --- a/mcxa276-pac/src/can0/ecr.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `ECR` reader"] -pub type R = crate::R; -#[doc = "Register `ECR` writer"] -pub type W = crate::W; -#[doc = "Field `TXERRCNT` reader - Transmit Error Counter"] -pub type TxerrcntR = crate::FieldReader; -#[doc = "Field `TXERRCNT` writer - Transmit Error Counter"] -pub type TxerrcntW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `RXERRCNT` reader - Receive Error Counter"] -pub type RxerrcntR = crate::FieldReader; -#[doc = "Field `RXERRCNT` writer - Receive Error Counter"] -pub type RxerrcntW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `TXERRCNT_FAST` reader - Transmit Error Counter for Fast Bits"] -pub type TxerrcntFastR = crate::FieldReader; -#[doc = "Field `TXERRCNT_FAST` writer - Transmit Error Counter for Fast Bits"] -pub type TxerrcntFastW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `RXERRCNT_FAST` reader - Receive Error Counter for Fast Bits"] -pub type RxerrcntFastR = crate::FieldReader; -#[doc = "Field `RXERRCNT_FAST` writer - Receive Error Counter for Fast Bits"] -pub type RxerrcntFastW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Transmit Error Counter"] - #[inline(always)] - pub fn txerrcnt(&self) -> TxerrcntR { - TxerrcntR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Receive Error Counter"] - #[inline(always)] - pub fn rxerrcnt(&self) -> RxerrcntR { - RxerrcntR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Transmit Error Counter for Fast Bits"] - #[inline(always)] - pub fn txerrcnt_fast(&self) -> TxerrcntFastR { - TxerrcntFastR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Receive Error Counter for Fast Bits"] - #[inline(always)] - pub fn rxerrcnt_fast(&self) -> RxerrcntFastR { - RxerrcntFastR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Transmit Error Counter"] - #[inline(always)] - pub fn txerrcnt(&mut self) -> TxerrcntW { - TxerrcntW::new(self, 0) - } - #[doc = "Bits 8:15 - Receive Error Counter"] - #[inline(always)] - pub fn rxerrcnt(&mut self) -> RxerrcntW { - RxerrcntW::new(self, 8) - } - #[doc = "Bits 16:23 - Transmit Error Counter for Fast Bits"] - #[inline(always)] - pub fn txerrcnt_fast(&mut self) -> TxerrcntFastW { - TxerrcntFastW::new(self, 16) - } - #[doc = "Bits 24:31 - Receive Error Counter for Fast Bits"] - #[inline(always)] - pub fn rxerrcnt_fast(&mut self) -> RxerrcntFastW { - RxerrcntFastW::new(self, 24) - } -} -#[doc = "Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`ecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EcrSpec; -impl crate::RegisterSpec for EcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ecr::R`](R) reader structure"] -impl crate::Readable for EcrSpec {} -#[doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"] -impl crate::Writable for EcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ECR to value 0"] -impl crate::Resettable for EcrSpec {} diff --git a/mcxa276-pac/src/can0/edcbt.rs b/mcxa276-pac/src/can0/edcbt.rs deleted file mode 100644 index c5a63dda0..000000000 --- a/mcxa276-pac/src/can0/edcbt.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `EDCBT` reader"] -pub type R = crate::R; -#[doc = "Register `EDCBT` writer"] -pub type W = crate::W; -#[doc = "Field `DTSEG1` reader - Data Phase Segment 1"] -pub type Dtseg1R = crate::FieldReader; -#[doc = "Field `DTSEG1` writer - Data Phase Segment 1"] -pub type Dtseg1W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `DTSEG2` reader - Data Phase Time Segment 2"] -pub type Dtseg2R = crate::FieldReader; -#[doc = "Field `DTSEG2` writer - Data Phase Time Segment 2"] -pub type Dtseg2W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DRJW` reader - Data Phase Resynchronization Jump Width"] -pub type DrjwR = crate::FieldReader; -#[doc = "Field `DRJW` writer - Data Phase Resynchronization Jump Width"] -pub type DrjwW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:4 - Data Phase Segment 1"] - #[inline(always)] - pub fn dtseg1(&self) -> Dtseg1R { - Dtseg1R::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 12:15 - Data Phase Time Segment 2"] - #[inline(always)] - pub fn dtseg2(&self) -> Dtseg2R { - Dtseg2R::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 22:25 - Data Phase Resynchronization Jump Width"] - #[inline(always)] - pub fn drjw(&self) -> DrjwR { - DrjwR::new(((self.bits >> 22) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:4 - Data Phase Segment 1"] - #[inline(always)] - pub fn dtseg1(&mut self) -> Dtseg1W { - Dtseg1W::new(self, 0) - } - #[doc = "Bits 12:15 - Data Phase Time Segment 2"] - #[inline(always)] - pub fn dtseg2(&mut self) -> Dtseg2W { - Dtseg2W::new(self, 12) - } - #[doc = "Bits 22:25 - Data Phase Resynchronization Jump Width"] - #[inline(always)] - pub fn drjw(&mut self) -> DrjwW { - DrjwW::new(self, 22) - } -} -#[doc = "Enhanced Data Phase CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`edcbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edcbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EdcbtSpec; -impl crate::RegisterSpec for EdcbtSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`edcbt::R`](R) reader structure"] -impl crate::Readable for EdcbtSpec {} -#[doc = "`write(|w| ..)` method takes [`edcbt::W`](W) writer structure"] -impl crate::Writable for EdcbtSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EDCBT to value 0"] -impl crate::Resettable for EdcbtSpec {} diff --git a/mcxa276-pac/src/can0/encbt.rs b/mcxa276-pac/src/can0/encbt.rs deleted file mode 100644 index a2419451a..000000000 --- a/mcxa276-pac/src/can0/encbt.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ENCBT` reader"] -pub type R = crate::R; -#[doc = "Register `ENCBT` writer"] -pub type W = crate::W; -#[doc = "Field `NTSEG1` reader - Nominal Time Segment 1"] -pub type Ntseg1R = crate::FieldReader; -#[doc = "Field `NTSEG1` writer - Nominal Time Segment 1"] -pub type Ntseg1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `NTSEG2` reader - Nominal Time Segment 2"] -pub type Ntseg2R = crate::FieldReader; -#[doc = "Field `NTSEG2` writer - Nominal Time Segment 2"] -pub type Ntseg2W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `NRJW` reader - Nominal Resynchronization Jump Width"] -pub type NrjwR = crate::FieldReader; -#[doc = "Field `NRJW` writer - Nominal Resynchronization Jump Width"] -pub type NrjwW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bits 0:7 - Nominal Time Segment 1"] - #[inline(always)] - pub fn ntseg1(&self) -> Ntseg1R { - Ntseg1R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 12:18 - Nominal Time Segment 2"] - #[inline(always)] - pub fn ntseg2(&self) -> Ntseg2R { - Ntseg2R::new(((self.bits >> 12) & 0x7f) as u8) - } - #[doc = "Bits 22:28 - Nominal Resynchronization Jump Width"] - #[inline(always)] - pub fn nrjw(&self) -> NrjwR { - NrjwR::new(((self.bits >> 22) & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Nominal Time Segment 1"] - #[inline(always)] - pub fn ntseg1(&mut self) -> Ntseg1W { - Ntseg1W::new(self, 0) - } - #[doc = "Bits 12:18 - Nominal Time Segment 2"] - #[inline(always)] - pub fn ntseg2(&mut self) -> Ntseg2W { - Ntseg2W::new(self, 12) - } - #[doc = "Bits 22:28 - Nominal Resynchronization Jump Width"] - #[inline(always)] - pub fn nrjw(&mut self) -> NrjwW { - NrjwW::new(self, 22) - } -} -#[doc = "Enhanced Nominal CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`encbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`encbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EncbtSpec; -impl crate::RegisterSpec for EncbtSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`encbt::R`](R) reader structure"] -impl crate::Readable for EncbtSpec {} -#[doc = "`write(|w| ..)` method takes [`encbt::W`](W) writer structure"] -impl crate::Writable for EncbtSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ENCBT to value 0"] -impl crate::Resettable for EncbtSpec {} diff --git a/mcxa276-pac/src/can0/eprs.rs b/mcxa276-pac/src/can0/eprs.rs deleted file mode 100644 index 8f77c94f4..000000000 --- a/mcxa276-pac/src/can0/eprs.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `EPRS` reader"] -pub type R = crate::R; -#[doc = "Register `EPRS` writer"] -pub type W = crate::W; -#[doc = "Field `ENPRESDIV` reader - Extended Nominal Prescaler Division Factor"] -pub type EnpresdivR = crate::FieldReader; -#[doc = "Field `ENPRESDIV` writer - Extended Nominal Prescaler Division Factor"] -pub type EnpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `EDPRESDIV` reader - Extended Data Phase Prescaler Division Factor"] -pub type EdpresdivR = crate::FieldReader; -#[doc = "Field `EDPRESDIV` writer - Extended Data Phase Prescaler Division Factor"] -pub type EdpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:9 - Extended Nominal Prescaler Division Factor"] - #[inline(always)] - pub fn enpresdiv(&self) -> EnpresdivR { - EnpresdivR::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 16:25 - Extended Data Phase Prescaler Division Factor"] - #[inline(always)] - pub fn edpresdiv(&self) -> EdpresdivR { - EdpresdivR::new(((self.bits >> 16) & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:9 - Extended Nominal Prescaler Division Factor"] - #[inline(always)] - pub fn enpresdiv(&mut self) -> EnpresdivW { - EnpresdivW::new(self, 0) - } - #[doc = "Bits 16:25 - Extended Data Phase Prescaler Division Factor"] - #[inline(always)] - pub fn edpresdiv(&mut self) -> EdpresdivW { - EdpresdivW::new(self, 16) - } -} -#[doc = "Enhanced CAN Bit Timing Prescalers\n\nYou can [`read`](crate::Reg::read) this register and get [`eprs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eprs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EprsSpec; -impl crate::RegisterSpec for EprsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`eprs::R`](R) reader structure"] -impl crate::Readable for EprsSpec {} -#[doc = "`write(|w| ..)` method takes [`eprs::W`](W) writer structure"] -impl crate::Writable for EprsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EPRS to value 0"] -impl crate::Resettable for EprsSpec {} diff --git a/mcxa276-pac/src/can0/erfcr.rs b/mcxa276-pac/src/can0/erfcr.rs deleted file mode 100644 index a2e9a8f21..000000000 --- a/mcxa276-pac/src/can0/erfcr.rs +++ /dev/null @@ -1,140 +0,0 @@ -#[doc = "Register `ERFCR` reader"] -pub type R = crate::R; -#[doc = "Register `ERFCR` writer"] -pub type W = crate::W; -#[doc = "Field `ERFWM` reader - Enhanced RX FIFO Watermark"] -pub type ErfwmR = crate::FieldReader; -#[doc = "Field `ERFWM` writer - Enhanced RX FIFO Watermark"] -pub type ErfwmW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `NFE` reader - Number of Enhanced RX FIFO Filter Elements"] -pub type NfeR = crate::FieldReader; -#[doc = "Field `NFE` writer - Number of Enhanced RX FIFO Filter Elements"] -pub type NfeW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `NEXIF` reader - Number of Extended ID Filter Elements"] -pub type NexifR = crate::FieldReader; -#[doc = "Field `NEXIF` writer - Number of Extended ID Filter Elements"] -pub type NexifW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `DMALW` reader - DMA Last Word"] -pub type DmalwR = crate::FieldReader; -#[doc = "Field `DMALW` writer - DMA Last Word"] -pub type DmalwW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Enhanced RX FIFO enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfen { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFEN` reader - Enhanced RX FIFO enable"] -pub type ErfenR = crate::BitReader; -impl ErfenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfen { - match self.bits { - false => Erfen::Disable, - true => Erfen::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Erfen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Erfen::Enable - } -} -#[doc = "Field `ERFEN` writer - Enhanced RX FIFO enable"] -pub type ErfenW<'a, REG> = crate::BitWriter<'a, REG, Erfen>; -impl<'a, REG> ErfenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Erfen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Erfen::Enable) - } -} -impl R { - #[doc = "Bits 0:4 - Enhanced RX FIFO Watermark"] - #[inline(always)] - pub fn erfwm(&self) -> ErfwmR { - ErfwmR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 8:13 - Number of Enhanced RX FIFO Filter Elements"] - #[inline(always)] - pub fn nfe(&self) -> NfeR { - NfeR::new(((self.bits >> 8) & 0x3f) as u8) - } - #[doc = "Bits 16:22 - Number of Extended ID Filter Elements"] - #[inline(always)] - pub fn nexif(&self) -> NexifR { - NexifR::new(((self.bits >> 16) & 0x7f) as u8) - } - #[doc = "Bits 26:30 - DMA Last Word"] - #[inline(always)] - pub fn dmalw(&self) -> DmalwR { - DmalwR::new(((self.bits >> 26) & 0x1f) as u8) - } - #[doc = "Bit 31 - Enhanced RX FIFO enable"] - #[inline(always)] - pub fn erfen(&self) -> ErfenR { - ErfenR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Enhanced RX FIFO Watermark"] - #[inline(always)] - pub fn erfwm(&mut self) -> ErfwmW { - ErfwmW::new(self, 0) - } - #[doc = "Bits 8:13 - Number of Enhanced RX FIFO Filter Elements"] - #[inline(always)] - pub fn nfe(&mut self) -> NfeW { - NfeW::new(self, 8) - } - #[doc = "Bits 16:22 - Number of Extended ID Filter Elements"] - #[inline(always)] - pub fn nexif(&mut self) -> NexifW { - NexifW::new(self, 16) - } - #[doc = "Bits 26:30 - DMA Last Word"] - #[inline(always)] - pub fn dmalw(&mut self) -> DmalwW { - DmalwW::new(self, 26) - } - #[doc = "Bit 31 - Enhanced RX FIFO enable"] - #[inline(always)] - pub fn erfen(&mut self) -> ErfenW { - ErfenW::new(self, 31) - } -} -#[doc = "Enhanced RX FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`erfcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ErfcrSpec; -impl crate::RegisterSpec for ErfcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`erfcr::R`](R) reader structure"] -impl crate::Readable for ErfcrSpec {} -#[doc = "`write(|w| ..)` method takes [`erfcr::W`](W) writer structure"] -impl crate::Writable for ErfcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ERFCR to value 0"] -impl crate::Resettable for ErfcrSpec {} diff --git a/mcxa276-pac/src/can0/erffel.rs b/mcxa276-pac/src/can0/erffel.rs deleted file mode 100644 index 6d1be69d9..000000000 --- a/mcxa276-pac/src/can0/erffel.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `ERFFEL[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `ERFFEL[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `FEL` reader - Filter Element Bits"] -pub type FelR = crate::FieldReader; -#[doc = "Field `FEL` writer - Filter Element Bits"] -pub type FelW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Filter Element Bits"] - #[inline(always)] - pub fn fel(&self) -> FelR { - FelR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Filter Element Bits"] - #[inline(always)] - pub fn fel(&mut self) -> FelW { - FelW::new(self, 0) - } -} -#[doc = "Enhanced RX FIFO Filter Element\n\nYou can [`read`](crate::Reg::read) this register and get [`erffel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erffel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ErffelSpec; -impl crate::RegisterSpec for ErffelSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`erffel::R`](R) reader structure"] -impl crate::Readable for ErffelSpec {} -#[doc = "`write(|w| ..)` method takes [`erffel::W`](W) writer structure"] -impl crate::Writable for ErffelSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ERFFEL[%s] to value 0"] -impl crate::Resettable for ErffelSpec {} diff --git a/mcxa276-pac/src/can0/erfier.rs b/mcxa276-pac/src/can0/erfier.rs deleted file mode 100644 index e988db9b8..000000000 --- a/mcxa276-pac/src/can0/erfier.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `ERFIER` reader"] -pub type R = crate::R; -#[doc = "Register `ERFIER` writer"] -pub type W = crate::W; -#[doc = "Enhanced RX FIFO Data Available Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfdaie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfdaie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFDAIE` reader - Enhanced RX FIFO Data Available Interrupt Enable"] -pub type ErfdaieR = crate::BitReader; -impl ErfdaieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfdaie { - match self.bits { - false => Erfdaie::Disable, - true => Erfdaie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Erfdaie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Erfdaie::Enable - } -} -#[doc = "Field `ERFDAIE` writer - Enhanced RX FIFO Data Available Interrupt Enable"] -pub type ErfdaieW<'a, REG> = crate::BitWriter<'a, REG, Erfdaie>; -impl<'a, REG> ErfdaieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Erfdaie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Erfdaie::Enable) - } -} -#[doc = "Enhanced RX FIFO Watermark Indication Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfwmiie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfwmiie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFWMIIE` reader - Enhanced RX FIFO Watermark Indication Interrupt Enable"] -pub type ErfwmiieR = crate::BitReader; -impl ErfwmiieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfwmiie { - match self.bits { - false => Erfwmiie::Disable, - true => Erfwmiie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Erfwmiie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Erfwmiie::Enable - } -} -#[doc = "Field `ERFWMIIE` writer - Enhanced RX FIFO Watermark Indication Interrupt Enable"] -pub type ErfwmiieW<'a, REG> = crate::BitWriter<'a, REG, Erfwmiie>; -impl<'a, REG> ErfwmiieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Erfwmiie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Erfwmiie::Enable) - } -} -#[doc = "Enhanced RX FIFO Overflow Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfovfie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfovfie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFOVFIE` reader - Enhanced RX FIFO Overflow Interrupt Enable"] -pub type ErfovfieR = crate::BitReader; -impl ErfovfieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfovfie { - match self.bits { - false => Erfovfie::Disable, - true => Erfovfie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Erfovfie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Erfovfie::Enable - } -} -#[doc = "Field `ERFOVFIE` writer - Enhanced RX FIFO Overflow Interrupt Enable"] -pub type ErfovfieW<'a, REG> = crate::BitWriter<'a, REG, Erfovfie>; -impl<'a, REG> ErfovfieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Erfovfie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Erfovfie::Enable) - } -} -#[doc = "Enhanced RX FIFO Underflow Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfufwie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfufwie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFUFWIE` reader - Enhanced RX FIFO Underflow Interrupt Enable"] -pub type ErfufwieR = crate::BitReader; -impl ErfufwieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfufwie { - match self.bits { - false => Erfufwie::Disable, - true => Erfufwie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Erfufwie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Erfufwie::Enable - } -} -#[doc = "Field `ERFUFWIE` writer - Enhanced RX FIFO Underflow Interrupt Enable"] -pub type ErfufwieW<'a, REG> = crate::BitWriter<'a, REG, Erfufwie>; -impl<'a, REG> ErfufwieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Erfufwie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Erfufwie::Enable) - } -} -impl R { - #[doc = "Bit 28 - Enhanced RX FIFO Data Available Interrupt Enable"] - #[inline(always)] - pub fn erfdaie(&self) -> ErfdaieR { - ErfdaieR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Interrupt Enable"] - #[inline(always)] - pub fn erfwmiie(&self) -> ErfwmiieR { - ErfwmiieR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Enhanced RX FIFO Overflow Interrupt Enable"] - #[inline(always)] - pub fn erfovfie(&self) -> ErfovfieR { - ErfovfieR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Enhanced RX FIFO Underflow Interrupt Enable"] - #[inline(always)] - pub fn erfufwie(&self) -> ErfufwieR { - ErfufwieR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 28 - Enhanced RX FIFO Data Available Interrupt Enable"] - #[inline(always)] - pub fn erfdaie(&mut self) -> ErfdaieW { - ErfdaieW::new(self, 28) - } - #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Interrupt Enable"] - #[inline(always)] - pub fn erfwmiie(&mut self) -> ErfwmiieW { - ErfwmiieW::new(self, 29) - } - #[doc = "Bit 30 - Enhanced RX FIFO Overflow Interrupt Enable"] - #[inline(always)] - pub fn erfovfie(&mut self) -> ErfovfieW { - ErfovfieW::new(self, 30) - } - #[doc = "Bit 31 - Enhanced RX FIFO Underflow Interrupt Enable"] - #[inline(always)] - pub fn erfufwie(&mut self) -> ErfufwieW { - ErfufwieW::new(self, 31) - } -} -#[doc = "Enhanced RX FIFO Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erfier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ErfierSpec; -impl crate::RegisterSpec for ErfierSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`erfier::R`](R) reader structure"] -impl crate::Readable for ErfierSpec {} -#[doc = "`write(|w| ..)` method takes [`erfier::W`](W) writer structure"] -impl crate::Writable for ErfierSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ERFIER to value 0"] -impl crate::Resettable for ErfierSpec {} diff --git a/mcxa276-pac/src/can0/erfsr.rs b/mcxa276-pac/src/can0/erfsr.rs deleted file mode 100644 index f3ecc3357..000000000 --- a/mcxa276-pac/src/can0/erfsr.rs +++ /dev/null @@ -1,426 +0,0 @@ -#[doc = "Register `ERFSR` reader"] -pub type R = crate::R; -#[doc = "Register `ERFSR` writer"] -pub type W = crate::W; -#[doc = "Field `ERFEL` reader - Enhanced RX FIFO Elements"] -pub type ErfelR = crate::FieldReader; -#[doc = "Enhanced RX FIFO Full Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erff { - #[doc = "0: Not full"] - NotFull = 0, - #[doc = "1: Full"] - Full = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erff) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFF` reader - Enhanced RX FIFO Full Flag"] -pub type ErffR = crate::BitReader; -impl ErffR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erff { - match self.bits { - false => Erff::NotFull, - true => Erff::Full, - } - } - #[doc = "Not full"] - #[inline(always)] - pub fn is_not_full(&self) -> bool { - *self == Erff::NotFull - } - #[doc = "Full"] - #[inline(always)] - pub fn is_full(&self) -> bool { - *self == Erff::Full - } -} -#[doc = "Enhanced RX FIFO Empty Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfe { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFE` reader - Enhanced RX FIFO Empty Flag"] -pub type ErfeR = crate::BitReader; -impl ErfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfe { - match self.bits { - false => Erfe::NotEmpty, - true => Erfe::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Erfe::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Erfe::Empty - } -} -#[doc = "Enhanced RX FIFO Clear\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfclr { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Clear enhanced RX FIFO content"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfclr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFCLR` reader - Enhanced RX FIFO Clear"] -pub type ErfclrR = crate::BitReader; -impl ErfclrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfclr { - match self.bits { - false => Erfclr::NoEffect, - true => Erfclr::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Erfclr::NoEffect - } - #[doc = "Clear enhanced RX FIFO content"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Erfclr::Clear - } -} -#[doc = "Field `ERFCLR` writer - Enhanced RX FIFO Clear"] -pub type ErfclrW<'a, REG> = crate::BitWriter<'a, REG, Erfclr>; -impl<'a, REG> ErfclrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Erfclr::NoEffect) - } - #[doc = "Clear enhanced RX FIFO content"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Erfclr::Clear) - } -} -#[doc = "Enhanced RX FIFO Data Available Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfda { - #[doc = "0: No such occurrence"] - NoMessageStored = 0, - #[doc = "1: At least one message stored in Enhanced RX FIFO"] - MessageStored = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfda) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFDA` reader - Enhanced RX FIFO Data Available Flag"] -pub type ErfdaR = crate::BitReader; -impl ErfdaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfda { - match self.bits { - false => Erfda::NoMessageStored, - true => Erfda::MessageStored, - } - } - #[doc = "No such occurrence"] - #[inline(always)] - pub fn is_no_message_stored(&self) -> bool { - *self == Erfda::NoMessageStored - } - #[doc = "At least one message stored in Enhanced RX FIFO"] - #[inline(always)] - pub fn is_message_stored(&self) -> bool { - *self == Erfda::MessageStored - } -} -#[doc = "Field `ERFDA` writer - Enhanced RX FIFO Data Available Flag"] -pub type ErfdaW<'a, REG> = crate::BitWriter1C<'a, REG, Erfda>; -impl<'a, REG> ErfdaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence"] - #[inline(always)] - pub fn no_message_stored(self) -> &'a mut crate::W { - self.variant(Erfda::NoMessageStored) - } - #[doc = "At least one message stored in Enhanced RX FIFO"] - #[inline(always)] - pub fn message_stored(self) -> &'a mut crate::W { - self.variant(Erfda::MessageStored) - } -} -#[doc = "Enhanced RX FIFO Watermark Indication Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfwmi { - #[doc = "0: No such occurrence"] - WatermarkNo = 0, - #[doc = "1: Number of messages in FIFO is greater than the watermark"] - WatermarkYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfwmi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFWMI` reader - Enhanced RX FIFO Watermark Indication Flag"] -pub type ErfwmiR = crate::BitReader; -impl ErfwmiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfwmi { - match self.bits { - false => Erfwmi::WatermarkNo, - true => Erfwmi::WatermarkYes, - } - } - #[doc = "No such occurrence"] - #[inline(always)] - pub fn is_watermark_no(&self) -> bool { - *self == Erfwmi::WatermarkNo - } - #[doc = "Number of messages in FIFO is greater than the watermark"] - #[inline(always)] - pub fn is_watermark_yes(&self) -> bool { - *self == Erfwmi::WatermarkYes - } -} -#[doc = "Field `ERFWMI` writer - Enhanced RX FIFO Watermark Indication Flag"] -pub type ErfwmiW<'a, REG> = crate::BitWriter1C<'a, REG, Erfwmi>; -impl<'a, REG> ErfwmiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence"] - #[inline(always)] - pub fn watermark_no(self) -> &'a mut crate::W { - self.variant(Erfwmi::WatermarkNo) - } - #[doc = "Number of messages in FIFO is greater than the watermark"] - #[inline(always)] - pub fn watermark_yes(self) -> &'a mut crate::W { - self.variant(Erfwmi::WatermarkYes) - } -} -#[doc = "Enhanced RX FIFO Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfovf { - #[doc = "0: No such occurrence"] - NoOverflow = 0, - #[doc = "1: Overflow"] - Overflow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfovf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFOVF` reader - Enhanced RX FIFO Overflow Flag"] -pub type ErfovfR = crate::BitReader; -impl ErfovfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfovf { - match self.bits { - false => Erfovf::NoOverflow, - true => Erfovf::Overflow, - } - } - #[doc = "No such occurrence"] - #[inline(always)] - pub fn is_no_overflow(&self) -> bool { - *self == Erfovf::NoOverflow - } - #[doc = "Overflow"] - #[inline(always)] - pub fn is_overflow(&self) -> bool { - *self == Erfovf::Overflow - } -} -#[doc = "Field `ERFOVF` writer - Enhanced RX FIFO Overflow Flag"] -pub type ErfovfW<'a, REG> = crate::BitWriter1C<'a, REG, Erfovf>; -impl<'a, REG> ErfovfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence"] - #[inline(always)] - pub fn no_overflow(self) -> &'a mut crate::W { - self.variant(Erfovf::NoOverflow) - } - #[doc = "Overflow"] - #[inline(always)] - pub fn overflow(self) -> &'a mut crate::W { - self.variant(Erfovf::Overflow) - } -} -#[doc = "Enhanced RX FIFO Underflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erfufw { - #[doc = "0: No such occurrence"] - NoUnderflow = 0, - #[doc = "1: Underflow"] - Underflow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erfufw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERFUFW` reader - Enhanced RX FIFO Underflow Flag"] -pub type ErfufwR = crate::BitReader; -impl ErfufwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erfufw { - match self.bits { - false => Erfufw::NoUnderflow, - true => Erfufw::Underflow, - } - } - #[doc = "No such occurrence"] - #[inline(always)] - pub fn is_no_underflow(&self) -> bool { - *self == Erfufw::NoUnderflow - } - #[doc = "Underflow"] - #[inline(always)] - pub fn is_underflow(&self) -> bool { - *self == Erfufw::Underflow - } -} -#[doc = "Field `ERFUFW` writer - Enhanced RX FIFO Underflow Flag"] -pub type ErfufwW<'a, REG> = crate::BitWriter1C<'a, REG, Erfufw>; -impl<'a, REG> ErfufwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence"] - #[inline(always)] - pub fn no_underflow(self) -> &'a mut crate::W { - self.variant(Erfufw::NoUnderflow) - } - #[doc = "Underflow"] - #[inline(always)] - pub fn underflow(self) -> &'a mut crate::W { - self.variant(Erfufw::Underflow) - } -} -impl R { - #[doc = "Bits 0:5 - Enhanced RX FIFO Elements"] - #[inline(always)] - pub fn erfel(&self) -> ErfelR { - ErfelR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 16 - Enhanced RX FIFO Full Flag"] - #[inline(always)] - pub fn erff(&self) -> ErffR { - ErffR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Enhanced RX FIFO Empty Flag"] - #[inline(always)] - pub fn erfe(&self) -> ErfeR { - ErfeR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 27 - Enhanced RX FIFO Clear"] - #[inline(always)] - pub fn erfclr(&self) -> ErfclrR { - ErfclrR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Enhanced RX FIFO Data Available Flag"] - #[inline(always)] - pub fn erfda(&self) -> ErfdaR { - ErfdaR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Flag"] - #[inline(always)] - pub fn erfwmi(&self) -> ErfwmiR { - ErfwmiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Enhanced RX FIFO Overflow Flag"] - #[inline(always)] - pub fn erfovf(&self) -> ErfovfR { - ErfovfR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Enhanced RX FIFO Underflow Flag"] - #[inline(always)] - pub fn erfufw(&self) -> ErfufwR { - ErfufwR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 27 - Enhanced RX FIFO Clear"] - #[inline(always)] - pub fn erfclr(&mut self) -> ErfclrW { - ErfclrW::new(self, 27) - } - #[doc = "Bit 28 - Enhanced RX FIFO Data Available Flag"] - #[inline(always)] - pub fn erfda(&mut self) -> ErfdaW { - ErfdaW::new(self, 28) - } - #[doc = "Bit 29 - Enhanced RX FIFO Watermark Indication Flag"] - #[inline(always)] - pub fn erfwmi(&mut self) -> ErfwmiW { - ErfwmiW::new(self, 29) - } - #[doc = "Bit 30 - Enhanced RX FIFO Overflow Flag"] - #[inline(always)] - pub fn erfovf(&mut self) -> ErfovfW { - ErfovfW::new(self, 30) - } - #[doc = "Bit 31 - Enhanced RX FIFO Underflow Flag"] - #[inline(always)] - pub fn erfufw(&mut self) -> ErfufwW { - ErfufwW::new(self, 31) - } -} -#[doc = "Enhanced RX FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`erfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ErfsrSpec; -impl crate::RegisterSpec for ErfsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`erfsr::R`](R) reader structure"] -impl crate::Readable for ErfsrSpec {} -#[doc = "`write(|w| ..)` method takes [`erfsr::W`](W) writer structure"] -impl crate::Writable for ErfsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xf000_0000; -} -#[doc = "`reset()` method sets ERFSR to value 0"] -impl crate::Resettable for ErfsrSpec {} diff --git a/mcxa276-pac/src/can0/esr1.rs b/mcxa276-pac/src/can0/esr1.rs deleted file mode 100644 index 710716c5d..000000000 --- a/mcxa276-pac/src/can0/esr1.rs +++ /dev/null @@ -1,1278 +0,0 @@ -#[doc = "Register `ESR1` reader"] -pub type R = crate::R; -#[doc = "Register `ESR1` writer"] -pub type W = crate::W; -#[doc = "Wake-up Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wakint { - #[doc = "0: No such occurrence."] - Disable = 0, - #[doc = "1: Indicates that a recessive-to-dominant transition was received on the CAN bus."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wakint) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAKINT` reader - Wake-up Interrupt Flag"] -pub type WakintR = crate::BitReader; -impl WakintR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wakint { - match self.bits { - false => Wakint::Disable, - true => Wakint::Enable, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wakint::Disable - } - #[doc = "Indicates that a recessive-to-dominant transition was received on the CAN bus."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wakint::Enable - } -} -#[doc = "Field `WAKINT` writer - Wake-up Interrupt Flag"] -pub type WakintW<'a, REG> = crate::BitWriter1C<'a, REG, Wakint>; -impl<'a, REG> WakintW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wakint::Disable) - } - #[doc = "Indicates that a recessive-to-dominant transition was received on the CAN bus."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wakint::Enable) - } -} -#[doc = "Error Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errint { - #[doc = "0: No such occurrence."] - Disable = 0, - #[doc = "1: Indicates setting of any error flag in the Error and Status register."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errint) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRINT` reader - Error Interrupt Flag"] -pub type ErrintR = crate::BitReader; -impl ErrintR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errint { - match self.bits { - false => Errint::Disable, - true => Errint::Enable, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Errint::Disable - } - #[doc = "Indicates setting of any error flag in the Error and Status register."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Errint::Enable - } -} -#[doc = "Field `ERRINT` writer - Error Interrupt Flag"] -pub type ErrintW<'a, REG> = crate::BitWriter1C<'a, REG, Errint>; -impl<'a, REG> ErrintW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Errint::Disable) - } - #[doc = "Indicates setting of any error flag in the Error and Status register."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Errint::Enable) - } -} -#[doc = "Bus Off Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Boffint { - #[doc = "0: No such occurrence."] - Disable = 0, - #[doc = "1: FlexCAN module entered Bus Off state."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Boffint) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BOFFINT` reader - Bus Off Interrupt Flag"] -pub type BoffintR = crate::BitReader; -impl BoffintR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Boffint { - match self.bits { - false => Boffint::Disable, - true => Boffint::Enable, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Boffint::Disable - } - #[doc = "FlexCAN module entered Bus Off state."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Boffint::Enable - } -} -#[doc = "Field `BOFFINT` writer - Bus Off Interrupt Flag"] -pub type BoffintW<'a, REG> = crate::BitWriter1C<'a, REG, Boffint>; -impl<'a, REG> BoffintW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Boffint::Disable) - } - #[doc = "FlexCAN module entered Bus Off state."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Boffint::Enable) - } -} -#[doc = "FlexCAN in Reception Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rx { - #[doc = "0: Not receiving"] - Disable = 0, - #[doc = "1: Receiving"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RX` reader - FlexCAN in Reception Flag"] -pub type RxR = crate::BitReader; -impl RxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rx { - match self.bits { - false => Rx::Disable, - true => Rx::Enable, - } - } - #[doc = "Not receiving"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Rx::Disable - } - #[doc = "Receiving"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Rx::Enable - } -} -#[doc = "Fault Confinement State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fltconf { - #[doc = "0: Error Active"] - ErrorActive = 0, - #[doc = "1: Error Passive"] - ErrorPassive = 1, - #[doc = "2: Bus Off"] - BusOff = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fltconf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fltconf { - type Ux = u8; -} -impl crate::IsEnum for Fltconf {} -#[doc = "Field `FLTCONF` reader - Fault Confinement State"] -pub type FltconfR = crate::FieldReader; -impl FltconfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Fltconf::ErrorActive), - 1 => Some(Fltconf::ErrorPassive), - 2 => Some(Fltconf::BusOff), - _ => None, - } - } - #[doc = "Error Active"] - #[inline(always)] - pub fn is_error_active(&self) -> bool { - *self == Fltconf::ErrorActive - } - #[doc = "Error Passive"] - #[inline(always)] - pub fn is_error_passive(&self) -> bool { - *self == Fltconf::ErrorPassive - } - #[doc = "Bus Off"] - #[inline(always)] - pub fn is_bus_off(&self) -> bool { - *self == Fltconf::BusOff - } -} -#[doc = "FlexCAN In Transmission\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tx { - #[doc = "0: Not transmitting"] - TransmitMessageNo = 0, - #[doc = "1: Transmitting"] - TransmitMessageYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TX` reader - FlexCAN In Transmission"] -pub type TxR = crate::BitReader; -impl TxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tx { - match self.bits { - false => Tx::TransmitMessageNo, - true => Tx::TransmitMessageYes, - } - } - #[doc = "Not transmitting"] - #[inline(always)] - pub fn is_transmit_message_no(&self) -> bool { - *self == Tx::TransmitMessageNo - } - #[doc = "Transmitting"] - #[inline(always)] - pub fn is_transmit_message_yes(&self) -> bool { - *self == Tx::TransmitMessageYes - } -} -#[doc = "Idle\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Idle { - #[doc = "0: Not IDLE"] - CanBusNotIdle = 0, - #[doc = "1: IDLE"] - CanBusIdle = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Idle) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IDLE` reader - Idle"] -pub type IdleR = crate::BitReader; -impl IdleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Idle { - match self.bits { - false => Idle::CanBusNotIdle, - true => Idle::CanBusIdle, - } - } - #[doc = "Not IDLE"] - #[inline(always)] - pub fn is_can_bus_not_idle(&self) -> bool { - *self == Idle::CanBusNotIdle - } - #[doc = "IDLE"] - #[inline(always)] - pub fn is_can_bus_idle(&self) -> bool { - *self == Idle::CanBusIdle - } -} -#[doc = "RX Error Warning Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxwrn { - #[doc = "0: No such occurrence."] - RxerrcntLt96 = 0, - #[doc = "1: RXERRCNT is greater than or equal to 96."] - RxerrcntGte96 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxwrn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXWRN` reader - RX Error Warning Flag"] -pub type RxwrnR = crate::BitReader; -impl RxwrnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxwrn { - match self.bits { - false => Rxwrn::RxerrcntLt96, - true => Rxwrn::RxerrcntGte96, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_rxerrcnt_lt_96(&self) -> bool { - *self == Rxwrn::RxerrcntLt96 - } - #[doc = "RXERRCNT is greater than or equal to 96."] - #[inline(always)] - pub fn is_rxerrcnt_gte_96(&self) -> bool { - *self == Rxwrn::RxerrcntGte96 - } -} -#[doc = "TX Error Warning Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txwrn { - #[doc = "0: No such occurrence."] - TxerrcntLt96 = 0, - #[doc = "1: TXERRCNT is 96 or greater."] - TxerrcntGte96 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txwrn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXWRN` reader - TX Error Warning Flag"] -pub type TxwrnR = crate::BitReader; -impl TxwrnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txwrn { - match self.bits { - false => Txwrn::TxerrcntLt96, - true => Txwrn::TxerrcntGte96, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_txerrcnt_lt_96(&self) -> bool { - *self == Txwrn::TxerrcntLt96 - } - #[doc = "TXERRCNT is 96 or greater."] - #[inline(always)] - pub fn is_txerrcnt_gte_96(&self) -> bool { - *self == Txwrn::TxerrcntGte96 - } -} -#[doc = "Stuffing Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stferr { - #[doc = "0: No error"] - StuffingErrorNo = 0, - #[doc = "1: Error occurred since last read of this register."] - StuffingErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stferr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STFERR` reader - Stuffing Error Flag"] -pub type StferrR = crate::BitReader; -impl StferrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stferr { - match self.bits { - false => Stferr::StuffingErrorNo, - true => Stferr::StuffingErrorYes, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_stuffing_error_no(&self) -> bool { - *self == Stferr::StuffingErrorNo - } - #[doc = "Error occurred since last read of this register."] - #[inline(always)] - pub fn is_stuffing_error_yes(&self) -> bool { - *self == Stferr::StuffingErrorYes - } -} -#[doc = "Form Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frmerr { - #[doc = "0: No error"] - FormErrorNo = 0, - #[doc = "1: Error occurred since last read of this register."] - FormErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frmerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRMERR` reader - Form Error Flag"] -pub type FrmerrR = crate::BitReader; -impl FrmerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frmerr { - match self.bits { - false => Frmerr::FormErrorNo, - true => Frmerr::FormErrorYes, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_form_error_no(&self) -> bool { - *self == Frmerr::FormErrorNo - } - #[doc = "Error occurred since last read of this register."] - #[inline(always)] - pub fn is_form_error_yes(&self) -> bool { - *self == Frmerr::FormErrorYes - } -} -#[doc = "Cyclic Redundancy Check Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crcerr { - #[doc = "0: No error"] - CrcErrorNo = 0, - #[doc = "1: Error occurred since last read of this register."] - CrcErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crcerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRCERR` reader - Cyclic Redundancy Check Error Flag"] -pub type CrcerrR = crate::BitReader; -impl CrcerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crcerr { - match self.bits { - false => Crcerr::CrcErrorNo, - true => Crcerr::CrcErrorYes, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_crc_error_no(&self) -> bool { - *self == Crcerr::CrcErrorNo - } - #[doc = "Error occurred since last read of this register."] - #[inline(always)] - pub fn is_crc_error_yes(&self) -> bool { - *self == Crcerr::CrcErrorYes - } -} -#[doc = "Acknowledge Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ackerr { - #[doc = "0: No error"] - AckErrorNo = 0, - #[doc = "1: Error occurred since last read of this register."] - AckErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ackerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ACKERR` reader - Acknowledge Error Flag"] -pub type AckerrR = crate::BitReader; -impl AckerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ackerr { - match self.bits { - false => Ackerr::AckErrorNo, - true => Ackerr::AckErrorYes, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_ack_error_no(&self) -> bool { - *self == Ackerr::AckErrorNo - } - #[doc = "Error occurred since last read of this register."] - #[inline(always)] - pub fn is_ack_error_yes(&self) -> bool { - *self == Ackerr::AckErrorYes - } -} -#[doc = "Bit0 Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bit0err { - #[doc = "0: No such occurrence."] - Bit0ErrorNo = 0, - #[doc = "1: At least one bit sent as dominant is received as recessive."] - Bit0ErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bit0err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BIT0ERR` reader - Bit0 Error Flag"] -pub type Bit0errR = crate::BitReader; -impl Bit0errR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bit0err { - match self.bits { - false => Bit0err::Bit0ErrorNo, - true => Bit0err::Bit0ErrorYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_bit0_error_no(&self) -> bool { - *self == Bit0err::Bit0ErrorNo - } - #[doc = "At least one bit sent as dominant is received as recessive."] - #[inline(always)] - pub fn is_bit0_error_yes(&self) -> bool { - *self == Bit0err::Bit0ErrorYes - } -} -#[doc = "Bit1 Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bit1err { - #[doc = "0: No such occurrence."] - Bit1ErrorNo = 0, - #[doc = "1: At least one bit sent as recessive is received as dominant."] - Bit1ErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bit1err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BIT1ERR` reader - Bit1 Error Flag"] -pub type Bit1errR = crate::BitReader; -impl Bit1errR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bit1err { - match self.bits { - false => Bit1err::Bit1ErrorNo, - true => Bit1err::Bit1ErrorYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_bit1_error_no(&self) -> bool { - *self == Bit1err::Bit1ErrorNo - } - #[doc = "At least one bit sent as recessive is received as dominant."] - #[inline(always)] - pub fn is_bit1_error_yes(&self) -> bool { - *self == Bit1err::Bit1ErrorYes - } -} -#[doc = "RX Warning Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rwrnint { - #[doc = "0: No such occurrence"] - RxWarningIntNo = 0, - #[doc = "1: RX error counter changed from less than 96 to greater than or equal to 96."] - RxWarningIntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rwrnint) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RWRNINT` reader - RX Warning Interrupt Flag"] -pub type RwrnintR = crate::BitReader; -impl RwrnintR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rwrnint { - match self.bits { - false => Rwrnint::RxWarningIntNo, - true => Rwrnint::RxWarningIntYes, - } - } - #[doc = "No such occurrence"] - #[inline(always)] - pub fn is_rx_warning_int_no(&self) -> bool { - *self == Rwrnint::RxWarningIntNo - } - #[doc = "RX error counter changed from less than 96 to greater than or equal to 96."] - #[inline(always)] - pub fn is_rx_warning_int_yes(&self) -> bool { - *self == Rwrnint::RxWarningIntYes - } -} -#[doc = "Field `RWRNINT` writer - RX Warning Interrupt Flag"] -pub type RwrnintW<'a, REG> = crate::BitWriter1C<'a, REG, Rwrnint>; -impl<'a, REG> RwrnintW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence"] - #[inline(always)] - pub fn rx_warning_int_no(self) -> &'a mut crate::W { - self.variant(Rwrnint::RxWarningIntNo) - } - #[doc = "RX error counter changed from less than 96 to greater than or equal to 96."] - #[inline(always)] - pub fn rx_warning_int_yes(self) -> &'a mut crate::W { - self.variant(Rwrnint::RxWarningIntYes) - } -} -#[doc = "TX Warning Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Twrnint { - #[doc = "0: No such occurrence"] - TxWarningIntNo = 0, - #[doc = "1: TX error counter changed from less than 96 to greater than or equal to 96."] - TxWarningIntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Twrnint) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TWRNINT` reader - TX Warning Interrupt Flag"] -pub type TwrnintR = crate::BitReader; -impl TwrnintR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Twrnint { - match self.bits { - false => Twrnint::TxWarningIntNo, - true => Twrnint::TxWarningIntYes, - } - } - #[doc = "No such occurrence"] - #[inline(always)] - pub fn is_tx_warning_int_no(&self) -> bool { - *self == Twrnint::TxWarningIntNo - } - #[doc = "TX error counter changed from less than 96 to greater than or equal to 96."] - #[inline(always)] - pub fn is_tx_warning_int_yes(&self) -> bool { - *self == Twrnint::TxWarningIntYes - } -} -#[doc = "Field `TWRNINT` writer - TX Warning Interrupt Flag"] -pub type TwrnintW<'a, REG> = crate::BitWriter1C<'a, REG, Twrnint>; -impl<'a, REG> TwrnintW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence"] - #[inline(always)] - pub fn tx_warning_int_no(self) -> &'a mut crate::W { - self.variant(Twrnint::TxWarningIntNo) - } - #[doc = "TX error counter changed from less than 96 to greater than or equal to 96."] - #[inline(always)] - pub fn tx_warning_int_yes(self) -> &'a mut crate::W { - self.variant(Twrnint::TxWarningIntYes) - } -} -#[doc = "CAN Synchronization Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Synch { - #[doc = "0: Not synchronized"] - CanBusSyncNo = 0, - #[doc = "1: Synchronized"] - CanBusSyncYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Synch) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYNCH` reader - CAN Synchronization Status Flag"] -pub type SynchR = crate::BitReader; -impl SynchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Synch { - match self.bits { - false => Synch::CanBusSyncNo, - true => Synch::CanBusSyncYes, - } - } - #[doc = "Not synchronized"] - #[inline(always)] - pub fn is_can_bus_sync_no(&self) -> bool { - *self == Synch::CanBusSyncNo - } - #[doc = "Synchronized"] - #[inline(always)] - pub fn is_can_bus_sync_yes(&self) -> bool { - *self == Synch::CanBusSyncYes - } -} -#[doc = "Bus Off Done Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Boffdoneint { - #[doc = "0: No such occurrence"] - BusOffNotDone = 0, - #[doc = "1: FlexCAN module has completed Bus Off process."] - BusOffDone = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Boffdoneint) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BOFFDONEINT` reader - Bus Off Done Interrupt Flag"] -pub type BoffdoneintR = crate::BitReader; -impl BoffdoneintR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Boffdoneint { - match self.bits { - false => Boffdoneint::BusOffNotDone, - true => Boffdoneint::BusOffDone, - } - } - #[doc = "No such occurrence"] - #[inline(always)] - pub fn is_bus_off_not_done(&self) -> bool { - *self == Boffdoneint::BusOffNotDone - } - #[doc = "FlexCAN module has completed Bus Off process."] - #[inline(always)] - pub fn is_bus_off_done(&self) -> bool { - *self == Boffdoneint::BusOffDone - } -} -#[doc = "Field `BOFFDONEINT` writer - Bus Off Done Interrupt Flag"] -pub type BoffdoneintW<'a, REG> = crate::BitWriter1C<'a, REG, Boffdoneint>; -impl<'a, REG> BoffdoneintW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence"] - #[inline(always)] - pub fn bus_off_not_done(self) -> &'a mut crate::W { - self.variant(Boffdoneint::BusOffNotDone) - } - #[doc = "FlexCAN module has completed Bus Off process."] - #[inline(always)] - pub fn bus_off_done(self) -> &'a mut crate::W { - self.variant(Boffdoneint::BusOffDone) - } -} -#[doc = "Fast Error Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ErrintFast { - #[doc = "0: No such occurrence."] - ErrorsDataPhaseNo = 0, - #[doc = "1: Error flag set in the data phase of CAN FD frames that have BRS = 1."] - ErrorsDataPhaseYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ErrintFast) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRINT_FAST` reader - Fast Error Interrupt Flag"] -pub type ErrintFastR = crate::BitReader; -impl ErrintFastR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ErrintFast { - match self.bits { - false => ErrintFast::ErrorsDataPhaseNo, - true => ErrintFast::ErrorsDataPhaseYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_errors_data_phase_no(&self) -> bool { - *self == ErrintFast::ErrorsDataPhaseNo - } - #[doc = "Error flag set in the data phase of CAN FD frames that have BRS = 1."] - #[inline(always)] - pub fn is_errors_data_phase_yes(&self) -> bool { - *self == ErrintFast::ErrorsDataPhaseYes - } -} -#[doc = "Field `ERRINT_FAST` writer - Fast Error Interrupt Flag"] -pub type ErrintFastW<'a, REG> = crate::BitWriter1C<'a, REG, ErrintFast>; -impl<'a, REG> ErrintFastW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No such occurrence."] - #[inline(always)] - pub fn errors_data_phase_no(self) -> &'a mut crate::W { - self.variant(ErrintFast::ErrorsDataPhaseNo) - } - #[doc = "Error flag set in the data phase of CAN FD frames that have BRS = 1."] - #[inline(always)] - pub fn errors_data_phase_yes(self) -> &'a mut crate::W { - self.variant(ErrintFast::ErrorsDataPhaseYes) - } -} -#[doc = "Error Overrun Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errovr { - #[doc = "0: No overrun"] - OverrunNotOccurred = 0, - #[doc = "1: Overrun"] - OverrunOccurred = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errovr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERROVR` reader - Error Overrun Flag"] -pub type ErrovrR = crate::BitReader; -impl ErrovrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errovr { - match self.bits { - false => Errovr::OverrunNotOccurred, - true => Errovr::OverrunOccurred, - } - } - #[doc = "No overrun"] - #[inline(always)] - pub fn is_overrun_not_occurred(&self) -> bool { - *self == Errovr::OverrunNotOccurred - } - #[doc = "Overrun"] - #[inline(always)] - pub fn is_overrun_occurred(&self) -> bool { - *self == Errovr::OverrunOccurred - } -} -#[doc = "Field `ERROVR` writer - Error Overrun Flag"] -pub type ErrovrW<'a, REG> = crate::BitWriter1C<'a, REG, Errovr>; -impl<'a, REG> ErrovrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overrun"] - #[inline(always)] - pub fn overrun_not_occurred(self) -> &'a mut crate::W { - self.variant(Errovr::OverrunNotOccurred) - } - #[doc = "Overrun"] - #[inline(always)] - pub fn overrun_occurred(self) -> &'a mut crate::W { - self.variant(Errovr::OverrunOccurred) - } -} -#[doc = "Fast Stuffing Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StferrFast { - #[doc = "0: No such occurrence."] - StuffingErrorNo = 0, - #[doc = "1: A stuffing error occurred since last read of this register."] - StuffingErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StferrFast) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STFERR_FAST` reader - Fast Stuffing Error Flag"] -pub type StferrFastR = crate::BitReader; -impl StferrFastR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StferrFast { - match self.bits { - false => StferrFast::StuffingErrorNo, - true => StferrFast::StuffingErrorYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_stuffing_error_no(&self) -> bool { - *self == StferrFast::StuffingErrorNo - } - #[doc = "A stuffing error occurred since last read of this register."] - #[inline(always)] - pub fn is_stuffing_error_yes(&self) -> bool { - *self == StferrFast::StuffingErrorYes - } -} -#[doc = "Fast Form Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FrmerrFast { - #[doc = "0: No such occurrence."] - FormErrorNo = 0, - #[doc = "1: A form error occurred since last read of this register."] - FormErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FrmerrFast) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRMERR_FAST` reader - Fast Form Error Flag"] -pub type FrmerrFastR = crate::BitReader; -impl FrmerrFastR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FrmerrFast { - match self.bits { - false => FrmerrFast::FormErrorNo, - true => FrmerrFast::FormErrorYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_form_error_no(&self) -> bool { - *self == FrmerrFast::FormErrorNo - } - #[doc = "A form error occurred since last read of this register."] - #[inline(always)] - pub fn is_form_error_yes(&self) -> bool { - *self == FrmerrFast::FormErrorYes - } -} -#[doc = "Fast Cyclic Redundancy Check Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CrcerrFast { - #[doc = "0: No such occurrence."] - CrcErrorNo = 0, - #[doc = "1: A CRC error occurred since last read of this register."] - CrcErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CrcerrFast) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRCERR_FAST` reader - Fast Cyclic Redundancy Check Error Flag"] -pub type CrcerrFastR = crate::BitReader; -impl CrcerrFastR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CrcerrFast { - match self.bits { - false => CrcerrFast::CrcErrorNo, - true => CrcerrFast::CrcErrorYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_crc_error_no(&self) -> bool { - *self == CrcerrFast::CrcErrorNo - } - #[doc = "A CRC error occurred since last read of this register."] - #[inline(always)] - pub fn is_crc_error_yes(&self) -> bool { - *self == CrcerrFast::CrcErrorYes - } -} -#[doc = "Fast Bit0 Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bit0errFast { - #[doc = "0: No such occurrence."] - Bit0ErrorNo = 0, - #[doc = "1: At least one bit transmitted as dominant is received as recessive."] - Bit0ErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bit0errFast) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BIT0ERR_FAST` reader - Fast Bit0 Error Flag"] -pub type Bit0errFastR = crate::BitReader; -impl Bit0errFastR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bit0errFast { - match self.bits { - false => Bit0errFast::Bit0ErrorNo, - true => Bit0errFast::Bit0ErrorYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_bit0_error_no(&self) -> bool { - *self == Bit0errFast::Bit0ErrorNo - } - #[doc = "At least one bit transmitted as dominant is received as recessive."] - #[inline(always)] - pub fn is_bit0_error_yes(&self) -> bool { - *self == Bit0errFast::Bit0ErrorYes - } -} -#[doc = "Fast Bit1 Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bit1errFast { - #[doc = "0: No such occurrence."] - Bit1ErrorNo = 0, - #[doc = "1: At least one bit transmitted as recessive is received as dominant."] - Bit1ErrorYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bit1errFast) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BIT1ERR_FAST` reader - Fast Bit1 Error Flag"] -pub type Bit1errFastR = crate::BitReader; -impl Bit1errFastR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bit1errFast { - match self.bits { - false => Bit1errFast::Bit1ErrorNo, - true => Bit1errFast::Bit1ErrorYes, - } - } - #[doc = "No such occurrence."] - #[inline(always)] - pub fn is_bit1_error_no(&self) -> bool { - *self == Bit1errFast::Bit1ErrorNo - } - #[doc = "At least one bit transmitted as recessive is received as dominant."] - #[inline(always)] - pub fn is_bit1_error_yes(&self) -> bool { - *self == Bit1errFast::Bit1ErrorYes - } -} -impl R { - #[doc = "Bit 0 - Wake-up Interrupt Flag"] - #[inline(always)] - pub fn wakint(&self) -> WakintR { - WakintR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Error Interrupt Flag"] - #[inline(always)] - pub fn errint(&self) -> ErrintR { - ErrintR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Bus Off Interrupt Flag"] - #[inline(always)] - pub fn boffint(&self) -> BoffintR { - BoffintR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - FlexCAN in Reception Flag"] - #[inline(always)] - pub fn rx(&self) -> RxR { - RxR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - Fault Confinement State"] - #[inline(always)] - pub fn fltconf(&self) -> FltconfR { - FltconfR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - FlexCAN In Transmission"] - #[inline(always)] - pub fn tx(&self) -> TxR { - TxR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Idle"] - #[inline(always)] - pub fn idle(&self) -> IdleR { - IdleR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - RX Error Warning Flag"] - #[inline(always)] - pub fn rxwrn(&self) -> RxwrnR { - RxwrnR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - TX Error Warning Flag"] - #[inline(always)] - pub fn txwrn(&self) -> TxwrnR { - TxwrnR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Stuffing Error Flag"] - #[inline(always)] - pub fn stferr(&self) -> StferrR { - StferrR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Form Error Flag"] - #[inline(always)] - pub fn frmerr(&self) -> FrmerrR { - FrmerrR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Cyclic Redundancy Check Error Flag"] - #[inline(always)] - pub fn crcerr(&self) -> CrcerrR { - CrcerrR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Acknowledge Error Flag"] - #[inline(always)] - pub fn ackerr(&self) -> AckerrR { - AckerrR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Bit0 Error Flag"] - #[inline(always)] - pub fn bit0err(&self) -> Bit0errR { - Bit0errR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Bit1 Error Flag"] - #[inline(always)] - pub fn bit1err(&self) -> Bit1errR { - Bit1errR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - RX Warning Interrupt Flag"] - #[inline(always)] - pub fn rwrnint(&self) -> RwrnintR { - RwrnintR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - TX Warning Interrupt Flag"] - #[inline(always)] - pub fn twrnint(&self) -> TwrnintR { - TwrnintR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - CAN Synchronization Status Flag"] - #[inline(always)] - pub fn synch(&self) -> SynchR { - SynchR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Bus Off Done Interrupt Flag"] - #[inline(always)] - pub fn boffdoneint(&self) -> BoffdoneintR { - BoffdoneintR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Fast Error Interrupt Flag"] - #[inline(always)] - pub fn errint_fast(&self) -> ErrintFastR { - ErrintFastR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Error Overrun Flag"] - #[inline(always)] - pub fn errovr(&self) -> ErrovrR { - ErrovrR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 26 - Fast Stuffing Error Flag"] - #[inline(always)] - pub fn stferr_fast(&self) -> StferrFastR { - StferrFastR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Fast Form Error Flag"] - #[inline(always)] - pub fn frmerr_fast(&self) -> FrmerrFastR { - FrmerrFastR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Fast Cyclic Redundancy Check Error Flag"] - #[inline(always)] - pub fn crcerr_fast(&self) -> CrcerrFastR { - CrcerrFastR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 30 - Fast Bit0 Error Flag"] - #[inline(always)] - pub fn bit0err_fast(&self) -> Bit0errFastR { - Bit0errFastR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Fast Bit1 Error Flag"] - #[inline(always)] - pub fn bit1err_fast(&self) -> Bit1errFastR { - Bit1errFastR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Wake-up Interrupt Flag"] - #[inline(always)] - pub fn wakint(&mut self) -> WakintW { - WakintW::new(self, 0) - } - #[doc = "Bit 1 - Error Interrupt Flag"] - #[inline(always)] - pub fn errint(&mut self) -> ErrintW { - ErrintW::new(self, 1) - } - #[doc = "Bit 2 - Bus Off Interrupt Flag"] - #[inline(always)] - pub fn boffint(&mut self) -> BoffintW { - BoffintW::new(self, 2) - } - #[doc = "Bit 16 - RX Warning Interrupt Flag"] - #[inline(always)] - pub fn rwrnint(&mut self) -> RwrnintW { - RwrnintW::new(self, 16) - } - #[doc = "Bit 17 - TX Warning Interrupt Flag"] - #[inline(always)] - pub fn twrnint(&mut self) -> TwrnintW { - TwrnintW::new(self, 17) - } - #[doc = "Bit 19 - Bus Off Done Interrupt Flag"] - #[inline(always)] - pub fn boffdoneint(&mut self) -> BoffdoneintW { - BoffdoneintW::new(self, 19) - } - #[doc = "Bit 20 - Fast Error Interrupt Flag"] - #[inline(always)] - pub fn errint_fast(&mut self) -> ErrintFastW { - ErrintFastW::new(self, 20) - } - #[doc = "Bit 21 - Error Overrun Flag"] - #[inline(always)] - pub fn errovr(&mut self) -> ErrovrW { - ErrovrW::new(self, 21) - } -} -#[doc = "Error and Status 1\n\nYou can [`read`](crate::Reg::read) this register and get [`esr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Esr1Spec; -impl crate::RegisterSpec for Esr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`esr1::R`](R) reader structure"] -impl crate::Readable for Esr1Spec {} -#[doc = "`write(|w| ..)` method takes [`esr1::W`](W) writer structure"] -impl crate::Writable for Esr1Spec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x003b_0007; -} -#[doc = "`reset()` method sets ESR1 to value 0"] -impl crate::Resettable for Esr1Spec {} diff --git a/mcxa276-pac/src/can0/esr2.rs b/mcxa276-pac/src/can0/esr2.rs deleted file mode 100644 index f1ad5f534..000000000 --- a/mcxa276-pac/src/can0/esr2.rs +++ /dev/null @@ -1,102 +0,0 @@ -#[doc = "Register `ESR2` reader"] -pub type R = crate::R; -#[doc = "Inactive Message Buffer\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Imb { - #[doc = "0: Message buffer indicated by ESR2\\[LPTM\\] is not inactive."] - InactiveMailboxNo = 0, - #[doc = "1: At least one message buffer is inactive."] - InactiveMailboxYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Imb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IMB` reader - Inactive Message Buffer"] -pub type ImbR = crate::BitReader; -impl ImbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Imb { - match self.bits { - false => Imb::InactiveMailboxNo, - true => Imb::InactiveMailboxYes, - } - } - #[doc = "Message buffer indicated by ESR2\\[LPTM\\] is not inactive."] - #[inline(always)] - pub fn is_inactive_mailbox_no(&self) -> bool { - *self == Imb::InactiveMailboxNo - } - #[doc = "At least one message buffer is inactive."] - #[inline(always)] - pub fn is_inactive_mailbox_yes(&self) -> bool { - *self == Imb::InactiveMailboxYes - } -} -#[doc = "Valid Priority Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Vps { - #[doc = "0: Invalid"] - Invalid = 0, - #[doc = "1: Valid"] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Vps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VPS` reader - Valid Priority Status"] -pub type VpsR = crate::BitReader; -impl VpsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Vps { - match self.bits { - false => Vps::Invalid, - true => Vps::Valid, - } - } - #[doc = "Invalid"] - #[inline(always)] - pub fn is_invalid(&self) -> bool { - *self == Vps::Invalid - } - #[doc = "Valid"] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Vps::Valid - } -} -#[doc = "Field `LPTM` reader - Lowest Priority TX Message Buffer"] -pub type LptmR = crate::FieldReader; -impl R { - #[doc = "Bit 13 - Inactive Message Buffer"] - #[inline(always)] - pub fn imb(&self) -> ImbR { - ImbR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Valid Priority Status"] - #[inline(always)] - pub fn vps(&self) -> VpsR { - VpsR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bits 16:22 - Lowest Priority TX Message Buffer"] - #[inline(always)] - pub fn lptm(&self) -> LptmR { - LptmR::new(((self.bits >> 16) & 0x7f) as u8) - } -} -#[doc = "Error and Status 2\n\nYou can [`read`](crate::Reg::read) this register and get [`esr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Esr2Spec; -impl crate::RegisterSpec for Esr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`esr2::R`](R) reader structure"] -impl crate::Readable for Esr2Spec {} -#[doc = "`reset()` method sets ESR2 to value 0"] -impl crate::Resettable for Esr2Spec {} diff --git a/mcxa276-pac/src/can0/etdc.rs b/mcxa276-pac/src/can0/etdc.rs deleted file mode 100644 index 63bc0f19e..000000000 --- a/mcxa276-pac/src/can0/etdc.rs +++ /dev/null @@ -1,232 +0,0 @@ -#[doc = "Register `ETDC` reader"] -pub type R = crate::R; -#[doc = "Register `ETDC` writer"] -pub type W = crate::W; -#[doc = "Field `ETDCVAL` reader - Enhanced Transceiver Delay Compensation Value"] -pub type EtdcvalR = crate::FieldReader; -#[doc = "Transceiver Delay Compensation Fail\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Etdcfail { - #[doc = "0: In range"] - InRange = 0, - #[doc = "1: Out of range"] - OutOfRange = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Etdcfail) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ETDCFAIL` reader - Transceiver Delay Compensation Fail"] -pub type EtdcfailR = crate::BitReader; -impl EtdcfailR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Etdcfail { - match self.bits { - false => Etdcfail::InRange, - true => Etdcfail::OutOfRange, - } - } - #[doc = "In range"] - #[inline(always)] - pub fn is_in_range(&self) -> bool { - *self == Etdcfail::InRange - } - #[doc = "Out of range"] - #[inline(always)] - pub fn is_out_of_range(&self) -> bool { - *self == Etdcfail::OutOfRange - } -} -#[doc = "Field `ETDCFAIL` writer - Transceiver Delay Compensation Fail"] -pub type EtdcfailW<'a, REG> = crate::BitWriter1C<'a, REG, Etdcfail>; -impl<'a, REG> EtdcfailW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "In range"] - #[inline(always)] - pub fn in_range(self) -> &'a mut crate::W { - self.variant(Etdcfail::InRange) - } - #[doc = "Out of range"] - #[inline(always)] - pub fn out_of_range(self) -> &'a mut crate::W { - self.variant(Etdcfail::OutOfRange) - } -} -#[doc = "Field `ETDCOFF` reader - Enhanced Transceiver Delay Compensation Offset"] -pub type EtdcoffR = crate::FieldReader; -#[doc = "Field `ETDCOFF` writer - Enhanced Transceiver Delay Compensation Offset"] -pub type EtdcoffW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Transceiver Delay Measurement Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdmdis { - #[doc = "0: Enable"] - Enable = 0, - #[doc = "1: Disable"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdmdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDMDIS` reader - Transceiver Delay Measurement Disable"] -pub type TdmdisR = crate::BitReader; -impl TdmdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdmdis { - match self.bits { - false => Tdmdis::Enable, - true => Tdmdis::Disable, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tdmdis::Enable - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tdmdis::Disable - } -} -#[doc = "Field `TDMDIS` writer - Transceiver Delay Measurement Disable"] -pub type TdmdisW<'a, REG> = crate::BitWriter<'a, REG, Tdmdis>; -impl<'a, REG> TdmdisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tdmdis::Enable) - } - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tdmdis::Disable) - } -} -#[doc = "Transceiver Delay Compensation Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Etdcen { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Etdcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ETDCEN` reader - Transceiver Delay Compensation Enable"] -pub type EtdcenR = crate::BitReader; -impl EtdcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Etdcen { - match self.bits { - false => Etdcen::Disable, - true => Etdcen::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Etdcen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Etdcen::Enable - } -} -#[doc = "Field `ETDCEN` writer - Transceiver Delay Compensation Enable"] -pub type EtdcenW<'a, REG> = crate::BitWriter<'a, REG, Etdcen>; -impl<'a, REG> EtdcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Etdcen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Etdcen::Enable) - } -} -impl R { - #[doc = "Bits 0:7 - Enhanced Transceiver Delay Compensation Value"] - #[inline(always)] - pub fn etdcval(&self) -> EtdcvalR { - EtdcvalR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 15 - Transceiver Delay Compensation Fail"] - #[inline(always)] - pub fn etdcfail(&self) -> EtdcfailR { - EtdcfailR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:22 - Enhanced Transceiver Delay Compensation Offset"] - #[inline(always)] - pub fn etdcoff(&self) -> EtdcoffR { - EtdcoffR::new(((self.bits >> 16) & 0x7f) as u8) - } - #[doc = "Bit 30 - Transceiver Delay Measurement Disable"] - #[inline(always)] - pub fn tdmdis(&self) -> TdmdisR { - TdmdisR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Transceiver Delay Compensation Enable"] - #[inline(always)] - pub fn etdcen(&self) -> EtdcenR { - EtdcenR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 15 - Transceiver Delay Compensation Fail"] - #[inline(always)] - pub fn etdcfail(&mut self) -> EtdcfailW { - EtdcfailW::new(self, 15) - } - #[doc = "Bits 16:22 - Enhanced Transceiver Delay Compensation Offset"] - #[inline(always)] - pub fn etdcoff(&mut self) -> EtdcoffW { - EtdcoffW::new(self, 16) - } - #[doc = "Bit 30 - Transceiver Delay Measurement Disable"] - #[inline(always)] - pub fn tdmdis(&mut self) -> TdmdisW { - TdmdisW::new(self, 30) - } - #[doc = "Bit 31 - Transceiver Delay Compensation Enable"] - #[inline(always)] - pub fn etdcen(&mut self) -> EtdcenW { - EtdcenW::new(self, 31) - } -} -#[doc = "Enhanced Transceiver Delay Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`etdc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etdc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EtdcSpec; -impl crate::RegisterSpec for EtdcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`etdc::R`](R) reader structure"] -impl crate::Readable for EtdcSpec {} -#[doc = "`write(|w| ..)` method takes [`etdc::W`](W) writer structure"] -impl crate::Writable for EtdcSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000; -} -#[doc = "`reset()` method sets ETDC to value 0"] -impl crate::Resettable for EtdcSpec {} diff --git a/mcxa276-pac/src/can0/fdcbt.rs b/mcxa276-pac/src/can0/fdcbt.rs deleted file mode 100644 index ec76ed206..000000000 --- a/mcxa276-pac/src/can0/fdcbt.rs +++ /dev/null @@ -1,91 +0,0 @@ -#[doc = "Register `FDCBT` reader"] -pub type R = crate::R; -#[doc = "Register `FDCBT` writer"] -pub type W = crate::W; -#[doc = "Field `FPSEG2` reader - Fast Phase Segment 2"] -pub type Fpseg2R = crate::FieldReader; -#[doc = "Field `FPSEG2` writer - Fast Phase Segment 2"] -pub type Fpseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `FPSEG1` reader - Fast Phase Segment 1"] -pub type Fpseg1R = crate::FieldReader; -#[doc = "Field `FPSEG1` writer - Fast Phase Segment 1"] -pub type Fpseg1W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `FPROPSEG` reader - Fast Propagation Segment"] -pub type FpropsegR = crate::FieldReader; -#[doc = "Field `FPROPSEG` writer - Fast Propagation Segment"] -pub type FpropsegW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `FRJW` reader - Fast Resync Jump Width"] -pub type FrjwR = crate::FieldReader; -#[doc = "Field `FRJW` writer - Fast Resync Jump Width"] -pub type FrjwW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `FPRESDIV` reader - Fast Prescaler Division Factor"] -pub type FpresdivR = crate::FieldReader; -#[doc = "Field `FPRESDIV` writer - Fast Prescaler Division Factor"] -pub type FpresdivW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:2 - Fast Phase Segment 2"] - #[inline(always)] - pub fn fpseg2(&self) -> Fpseg2R { - Fpseg2R::new((self.bits & 7) as u8) - } - #[doc = "Bits 5:7 - Fast Phase Segment 1"] - #[inline(always)] - pub fn fpseg1(&self) -> Fpseg1R { - Fpseg1R::new(((self.bits >> 5) & 7) as u8) - } - #[doc = "Bits 10:14 - Fast Propagation Segment"] - #[inline(always)] - pub fn fpropseg(&self) -> FpropsegR { - FpropsegR::new(((self.bits >> 10) & 0x1f) as u8) - } - #[doc = "Bits 16:18 - Fast Resync Jump Width"] - #[inline(always)] - pub fn frjw(&self) -> FrjwR { - FrjwR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 20:29 - Fast Prescaler Division Factor"] - #[inline(always)] - pub fn fpresdiv(&self) -> FpresdivR { - FpresdivR::new(((self.bits >> 20) & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:2 - Fast Phase Segment 2"] - #[inline(always)] - pub fn fpseg2(&mut self) -> Fpseg2W { - Fpseg2W::new(self, 0) - } - #[doc = "Bits 5:7 - Fast Phase Segment 1"] - #[inline(always)] - pub fn fpseg1(&mut self) -> Fpseg1W { - Fpseg1W::new(self, 5) - } - #[doc = "Bits 10:14 - Fast Propagation Segment"] - #[inline(always)] - pub fn fpropseg(&mut self) -> FpropsegW { - FpropsegW::new(self, 10) - } - #[doc = "Bits 16:18 - Fast Resync Jump Width"] - #[inline(always)] - pub fn frjw(&mut self) -> FrjwW { - FrjwW::new(self, 16) - } - #[doc = "Bits 20:29 - Fast Prescaler Division Factor"] - #[inline(always)] - pub fn fpresdiv(&mut self) -> FpresdivW { - FpresdivW::new(self, 20) - } -} -#[doc = "CAN FD Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdcbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FdcbtSpec; -impl crate::RegisterSpec for FdcbtSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fdcbt::R`](R) reader structure"] -impl crate::Readable for FdcbtSpec {} -#[doc = "`write(|w| ..)` method takes [`fdcbt::W`](W) writer structure"] -impl crate::Writable for FdcbtSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FDCBT to value 0"] -impl crate::Resettable for FdcbtSpec {} diff --git a/mcxa276-pac/src/can0/fdcrc.rs b/mcxa276-pac/src/can0/fdcrc.rs deleted file mode 100644 index 6066b3bbb..000000000 --- a/mcxa276-pac/src/can0/fdcrc.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `FDCRC` reader"] -pub type R = crate::R; -#[doc = "Field `FD_TXCRC` reader - Extended Transmitted CRC value"] -pub type FdTxcrcR = crate::FieldReader; -#[doc = "Field `FD_MBCRC` reader - CRC Message Buffer Number for FD_TXCRC"] -pub type FdMbcrcR = crate::FieldReader; -impl R { - #[doc = "Bits 0:20 - Extended Transmitted CRC value"] - #[inline(always)] - pub fn fd_txcrc(&self) -> FdTxcrcR { - FdTxcrcR::new(self.bits & 0x001f_ffff) - } - #[doc = "Bits 24:30 - CRC Message Buffer Number for FD_TXCRC"] - #[inline(always)] - pub fn fd_mbcrc(&self) -> FdMbcrcR { - FdMbcrcR::new(((self.bits >> 24) & 0x7f) as u8) - } -} -#[doc = "CAN FD CRC\n\nYou can [`read`](crate::Reg::read) this register and get [`fdcrc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FdcrcSpec; -impl crate::RegisterSpec for FdcrcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fdcrc::R`](R) reader structure"] -impl crate::Readable for FdcrcSpec {} -#[doc = "`reset()` method sets FDCRC to value 0"] -impl crate::Resettable for FdcrcSpec {} diff --git a/mcxa276-pac/src/can0/fdctrl.rs b/mcxa276-pac/src/can0/fdctrl.rs deleted file mode 100644 index 8e1315d39..000000000 --- a/mcxa276-pac/src/can0/fdctrl.rs +++ /dev/null @@ -1,330 +0,0 @@ -#[doc = "Register `FDCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `FDCTRL` writer"] -pub type W = crate::W; -#[doc = "Field `TDCVAL` reader - Transceiver Delay Compensation Value"] -pub type TdcvalR = crate::FieldReader; -#[doc = "Field `TDCOFF` reader - Transceiver Delay Compensation Offset"] -pub type TdcoffR = crate::FieldReader; -#[doc = "Field `TDCOFF` writer - Transceiver Delay Compensation Offset"] -pub type TdcoffW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Transceiver Delay Compensation Fail\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdcfail { - #[doc = "0: In range"] - InRange = 0, - #[doc = "1: Out of range"] - OutOfRange = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdcfail) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDCFAIL` reader - Transceiver Delay Compensation Fail"] -pub type TdcfailR = crate::BitReader; -impl TdcfailR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdcfail { - match self.bits { - false => Tdcfail::InRange, - true => Tdcfail::OutOfRange, - } - } - #[doc = "In range"] - #[inline(always)] - pub fn is_in_range(&self) -> bool { - *self == Tdcfail::InRange - } - #[doc = "Out of range"] - #[inline(always)] - pub fn is_out_of_range(&self) -> bool { - *self == Tdcfail::OutOfRange - } -} -#[doc = "Field `TDCFAIL` writer - Transceiver Delay Compensation Fail"] -pub type TdcfailW<'a, REG> = crate::BitWriter1C<'a, REG, Tdcfail>; -impl<'a, REG> TdcfailW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "In range"] - #[inline(always)] - pub fn in_range(self) -> &'a mut crate::W { - self.variant(Tdcfail::InRange) - } - #[doc = "Out of range"] - #[inline(always)] - pub fn out_of_range(self) -> &'a mut crate::W { - self.variant(Tdcfail::OutOfRange) - } -} -#[doc = "Transceiver Delay Compensation Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdcen { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDCEN` reader - Transceiver Delay Compensation Enable"] -pub type TdcenR = crate::BitReader; -impl TdcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdcen { - match self.bits { - false => Tdcen::Disable, - true => Tdcen::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tdcen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tdcen::Enable - } -} -#[doc = "Field `TDCEN` writer - Transceiver Delay Compensation Enable"] -pub type TdcenW<'a, REG> = crate::BitWriter<'a, REG, Tdcen>; -impl<'a, REG> TdcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tdcen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tdcen::Enable) - } -} -#[doc = "Message Buffer Data Size for Region 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbdsr0 { - #[doc = "0: 8 bytes"] - R0_8Bytes = 0, - #[doc = "1: 16 bytes"] - R0_16Bytes = 1, - #[doc = "2: 32 bytes"] - R0_32Bytes = 2, - #[doc = "3: 64 bytes"] - R0_64Bytes = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbdsr0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbdsr0 { - type Ux = u8; -} -impl crate::IsEnum for Mbdsr0 {} -#[doc = "Field `MBDSR0` reader - Message Buffer Data Size for Region 0"] -pub type Mbdsr0R = crate::FieldReader; -impl Mbdsr0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbdsr0 { - match self.bits { - 0 => Mbdsr0::R0_8Bytes, - 1 => Mbdsr0::R0_16Bytes, - 2 => Mbdsr0::R0_32Bytes, - 3 => Mbdsr0::R0_64Bytes, - _ => unreachable!(), - } - } - #[doc = "8 bytes"] - #[inline(always)] - pub fn is_r0_8_bytes(&self) -> bool { - *self == Mbdsr0::R0_8Bytes - } - #[doc = "16 bytes"] - #[inline(always)] - pub fn is_r0_16_bytes(&self) -> bool { - *self == Mbdsr0::R0_16Bytes - } - #[doc = "32 bytes"] - #[inline(always)] - pub fn is_r0_32_bytes(&self) -> bool { - *self == Mbdsr0::R0_32Bytes - } - #[doc = "64 bytes"] - #[inline(always)] - pub fn is_r0_64_bytes(&self) -> bool { - *self == Mbdsr0::R0_64Bytes - } -} -#[doc = "Field `MBDSR0` writer - Message Buffer Data Size for Region 0"] -pub type Mbdsr0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Mbdsr0, crate::Safe>; -impl<'a, REG> Mbdsr0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "8 bytes"] - #[inline(always)] - pub fn r0_8_bytes(self) -> &'a mut crate::W { - self.variant(Mbdsr0::R0_8Bytes) - } - #[doc = "16 bytes"] - #[inline(always)] - pub fn r0_16_bytes(self) -> &'a mut crate::W { - self.variant(Mbdsr0::R0_16Bytes) - } - #[doc = "32 bytes"] - #[inline(always)] - pub fn r0_32_bytes(self) -> &'a mut crate::W { - self.variant(Mbdsr0::R0_32Bytes) - } - #[doc = "64 bytes"] - #[inline(always)] - pub fn r0_64_bytes(self) -> &'a mut crate::W { - self.variant(Mbdsr0::R0_64Bytes) - } -} -#[doc = "Bit Rate Switch Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fdrate { - #[doc = "0: Disable"] - Nominal = 0, - #[doc = "1: Enable"] - BitRateSwitching = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fdrate) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FDRATE` reader - Bit Rate Switch Enable"] -pub type FdrateR = crate::BitReader; -impl FdrateR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fdrate { - match self.bits { - false => Fdrate::Nominal, - true => Fdrate::BitRateSwitching, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_nominal(&self) -> bool { - *self == Fdrate::Nominal - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_bit_rate_switching(&self) -> bool { - *self == Fdrate::BitRateSwitching - } -} -#[doc = "Field `FDRATE` writer - Bit Rate Switch Enable"] -pub type FdrateW<'a, REG> = crate::BitWriter<'a, REG, Fdrate>; -impl<'a, REG> FdrateW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn nominal(self) -> &'a mut crate::W { - self.variant(Fdrate::Nominal) - } - #[doc = "Enable"] - #[inline(always)] - pub fn bit_rate_switching(self) -> &'a mut crate::W { - self.variant(Fdrate::BitRateSwitching) - } -} -impl R { - #[doc = "Bits 0:5 - Transceiver Delay Compensation Value"] - #[inline(always)] - pub fn tdcval(&self) -> TdcvalR { - TdcvalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"] - #[inline(always)] - pub fn tdcoff(&self) -> TdcoffR { - TdcoffR::new(((self.bits >> 8) & 0x1f) as u8) - } - #[doc = "Bit 14 - Transceiver Delay Compensation Fail"] - #[inline(always)] - pub fn tdcfail(&self) -> TdcfailR { - TdcfailR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Transceiver Delay Compensation Enable"] - #[inline(always)] - pub fn tdcen(&self) -> TdcenR { - TdcenR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"] - #[inline(always)] - pub fn mbdsr0(&self) -> Mbdsr0R { - Mbdsr0R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bit 31 - Bit Rate Switch Enable"] - #[inline(always)] - pub fn fdrate(&self) -> FdrateR { - FdrateR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"] - #[inline(always)] - pub fn tdcoff(&mut self) -> TdcoffW { - TdcoffW::new(self, 8) - } - #[doc = "Bit 14 - Transceiver Delay Compensation Fail"] - #[inline(always)] - pub fn tdcfail(&mut self) -> TdcfailW { - TdcfailW::new(self, 14) - } - #[doc = "Bit 15 - Transceiver Delay Compensation Enable"] - #[inline(always)] - pub fn tdcen(&mut self) -> TdcenW { - TdcenW::new(self, 15) - } - #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"] - #[inline(always)] - pub fn mbdsr0(&mut self) -> Mbdsr0W { - Mbdsr0W::new(self, 16) - } - #[doc = "Bit 31 - Bit Rate Switch Enable"] - #[inline(always)] - pub fn fdrate(&mut self) -> FdrateW { - FdrateW::new(self, 31) - } -} -#[doc = "CAN FD Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fdctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FdctrlSpec; -impl crate::RegisterSpec for FdctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fdctrl::R`](R) reader structure"] -impl crate::Readable for FdctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`fdctrl::W`](W) writer structure"] -impl crate::Writable for FdctrlSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x4000; -} -#[doc = "`reset()` method sets FDCTRL to value 0x8000_0100"] -impl crate::Resettable for FdctrlSpec { - const RESET_VALUE: u32 = 0x8000_0100; -} diff --git a/mcxa276-pac/src/can0/flt_dlc.rs b/mcxa276-pac/src/can0/flt_dlc.rs deleted file mode 100644 index 1a58a1fed..000000000 --- a/mcxa276-pac/src/can0/flt_dlc.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `FLT_DLC` reader"] -pub type R = crate::R; -#[doc = "Register `FLT_DLC` writer"] -pub type W = crate::W; -#[doc = "Field `FLT_DLC_HI` reader - Upper Limit for Length of Data Bytes Filter"] -pub type FltDlcHiR = crate::FieldReader; -#[doc = "Field `FLT_DLC_HI` writer - Upper Limit for Length of Data Bytes Filter"] -pub type FltDlcHiW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `FLT_DLC_LO` reader - Lower Limit for Length of Data Bytes Filter"] -pub type FltDlcLoR = crate::FieldReader; -#[doc = "Field `FLT_DLC_LO` writer - Lower Limit for Length of Data Bytes Filter"] -pub type FltDlcLoW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"] - #[inline(always)] - pub fn flt_dlc_hi(&self) -> FltDlcHiR { - FltDlcHiR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"] - #[inline(always)] - pub fn flt_dlc_lo(&self) -> FltDlcLoR { - FltDlcLoR::new(((self.bits >> 16) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"] - #[inline(always)] - pub fn flt_dlc_hi(&mut self) -> FltDlcHiW { - FltDlcHiW::new(self, 0) - } - #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"] - #[inline(always)] - pub fn flt_dlc_lo(&mut self) -> FltDlcLoW { - FltDlcLoW::new(self, 16) - } -} -#[doc = "Pretended Networking Data Length Code (DLC) Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_dlc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_dlc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FltDlcSpec; -impl crate::RegisterSpec for FltDlcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flt_dlc::R`](R) reader structure"] -impl crate::Readable for FltDlcSpec {} -#[doc = "`write(|w| ..)` method takes [`flt_dlc::W`](W) writer structure"] -impl crate::Writable for FltDlcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FLT_DLC to value 0x08"] -impl crate::Resettable for FltDlcSpec { - const RESET_VALUE: u32 = 0x08; -} diff --git a/mcxa276-pac/src/can0/flt_id1.rs b/mcxa276-pac/src/can0/flt_id1.rs deleted file mode 100644 index 515c44a7e..000000000 --- a/mcxa276-pac/src/can0/flt_id1.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `FLT_ID1` reader"] -pub type R = crate::R; -#[doc = "Register `FLT_ID1` writer"] -pub type W = crate::W; -#[doc = "Field `FLT_ID1` reader - ID Filter 1 for Pretended Networking filtering"] -pub type FltId1R = crate::FieldReader; -#[doc = "Field `FLT_ID1` writer - ID Filter 1 for Pretended Networking filtering"] -pub type FltId1W<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; -#[doc = "Remote Transmission Request Filter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FltRtr { - #[doc = "0: Reject remote frame (accept data frame)"] - Reject = 0, - #[doc = "1: Accept remote frame"] - Accept = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FltRtr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLT_RTR` reader - Remote Transmission Request Filter"] -pub type FltRtrR = crate::BitReader; -impl FltRtrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FltRtr { - match self.bits { - false => FltRtr::Reject, - true => FltRtr::Accept, - } - } - #[doc = "Reject remote frame (accept data frame)"] - #[inline(always)] - pub fn is_reject(&self) -> bool { - *self == FltRtr::Reject - } - #[doc = "Accept remote frame"] - #[inline(always)] - pub fn is_accept(&self) -> bool { - *self == FltRtr::Accept - } -} -#[doc = "Field `FLT_RTR` writer - Remote Transmission Request Filter"] -pub type FltRtrW<'a, REG> = crate::BitWriter<'a, REG, FltRtr>; -impl<'a, REG> FltRtrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reject remote frame (accept data frame)"] - #[inline(always)] - pub fn reject(self) -> &'a mut crate::W { - self.variant(FltRtr::Reject) - } - #[doc = "Accept remote frame"] - #[inline(always)] - pub fn accept(self) -> &'a mut crate::W { - self.variant(FltRtr::Accept) - } -} -#[doc = "ID Extended Filter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FltIde { - #[doc = "0: Standard"] - Standard = 0, - #[doc = "1: Extended"] - Extended = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FltIde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLT_IDE` reader - ID Extended Filter"] -pub type FltIdeR = crate::BitReader; -impl FltIdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FltIde { - match self.bits { - false => FltIde::Standard, - true => FltIde::Extended, - } - } - #[doc = "Standard"] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == FltIde::Standard - } - #[doc = "Extended"] - #[inline(always)] - pub fn is_extended(&self) -> bool { - *self == FltIde::Extended - } -} -#[doc = "Field `FLT_IDE` writer - ID Extended Filter"] -pub type FltIdeW<'a, REG> = crate::BitWriter<'a, REG, FltIde>; -impl<'a, REG> FltIdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard"] - #[inline(always)] - pub fn standard(self) -> &'a mut crate::W { - self.variant(FltIde::Standard) - } - #[doc = "Extended"] - #[inline(always)] - pub fn extended(self) -> &'a mut crate::W { - self.variant(FltIde::Extended) - } -} -impl R { - #[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"] - #[inline(always)] - pub fn flt_id1(&self) -> FltId1R { - FltId1R::new(self.bits & 0x1fff_ffff) - } - #[doc = "Bit 29 - Remote Transmission Request Filter"] - #[inline(always)] - pub fn flt_rtr(&self) -> FltRtrR { - FltRtrR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - ID Extended Filter"] - #[inline(always)] - pub fn flt_ide(&self) -> FltIdeR { - FltIdeR::new(((self.bits >> 30) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"] - #[inline(always)] - pub fn flt_id1(&mut self) -> FltId1W { - FltId1W::new(self, 0) - } - #[doc = "Bit 29 - Remote Transmission Request Filter"] - #[inline(always)] - pub fn flt_rtr(&mut self) -> FltRtrW { - FltRtrW::new(self, 29) - } - #[doc = "Bit 30 - ID Extended Filter"] - #[inline(always)] - pub fn flt_ide(&mut self) -> FltIdeW { - FltIdeW::new(self, 30) - } -} -#[doc = "Pretended Networking ID Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FltId1Spec; -impl crate::RegisterSpec for FltId1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flt_id1::R`](R) reader structure"] -impl crate::Readable for FltId1Spec {} -#[doc = "`write(|w| ..)` method takes [`flt_id1::W`](W) writer structure"] -impl crate::Writable for FltId1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FLT_ID1 to value 0"] -impl crate::Resettable for FltId1Spec {} diff --git a/mcxa276-pac/src/can0/flt_id2_idmask.rs b/mcxa276-pac/src/can0/flt_id2_idmask.rs deleted file mode 100644 index 634def50c..000000000 --- a/mcxa276-pac/src/can0/flt_id2_idmask.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `FLT_ID2_IDMASK` reader"] -pub type R = crate::R; -#[doc = "Register `FLT_ID2_IDMASK` writer"] -pub type W = crate::W; -#[doc = "Field `FLT_ID2_IDMASK` reader - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] -pub type FltId2IdmaskR = crate::FieldReader; -#[doc = "Field `FLT_ID2_IDMASK` writer - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] -pub type FltId2IdmaskW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; -#[doc = "Remote Transmission Request Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RtrMsk { - #[doc = "0: The corresponding bit in the filter is \"don't care.\""] - FrameTypeNo = 0, - #[doc = "1: The corresponding bit in the filter is checked."] - FrameTypeYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RtrMsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RTR_MSK` reader - Remote Transmission Request Mask"] -pub type RtrMskR = crate::BitReader; -impl RtrMskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RtrMsk { - match self.bits { - false => RtrMsk::FrameTypeNo, - true => RtrMsk::FrameTypeYes, - } - } - #[doc = "The corresponding bit in the filter is \"don't care.\""] - #[inline(always)] - pub fn is_frame_type_no(&self) -> bool { - *self == RtrMsk::FrameTypeNo - } - #[doc = "The corresponding bit in the filter is checked."] - #[inline(always)] - pub fn is_frame_type_yes(&self) -> bool { - *self == RtrMsk::FrameTypeYes - } -} -#[doc = "Field `RTR_MSK` writer - Remote Transmission Request Mask"] -pub type RtrMskW<'a, REG> = crate::BitWriter<'a, REG, RtrMsk>; -impl<'a, REG> RtrMskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The corresponding bit in the filter is \"don't care.\""] - #[inline(always)] - pub fn frame_type_no(self) -> &'a mut crate::W { - self.variant(RtrMsk::FrameTypeNo) - } - #[doc = "The corresponding bit in the filter is checked."] - #[inline(always)] - pub fn frame_type_yes(self) -> &'a mut crate::W { - self.variant(RtrMsk::FrameTypeYes) - } -} -#[doc = "ID Extended Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IdeMsk { - #[doc = "0: The corresponding bit in the filter is \"don't care.\""] - FrameFormatNo = 0, - #[doc = "1: The corresponding bit in the filter is checked."] - FrameFormatYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IdeMsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IDE_MSK` reader - ID Extended Mask"] -pub type IdeMskR = crate::BitReader; -impl IdeMskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IdeMsk { - match self.bits { - false => IdeMsk::FrameFormatNo, - true => IdeMsk::FrameFormatYes, - } - } - #[doc = "The corresponding bit in the filter is \"don't care.\""] - #[inline(always)] - pub fn is_frame_format_no(&self) -> bool { - *self == IdeMsk::FrameFormatNo - } - #[doc = "The corresponding bit in the filter is checked."] - #[inline(always)] - pub fn is_frame_format_yes(&self) -> bool { - *self == IdeMsk::FrameFormatYes - } -} -#[doc = "Field `IDE_MSK` writer - ID Extended Mask"] -pub type IdeMskW<'a, REG> = crate::BitWriter<'a, REG, IdeMsk>; -impl<'a, REG> IdeMskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The corresponding bit in the filter is \"don't care.\""] - #[inline(always)] - pub fn frame_format_no(self) -> &'a mut crate::W { - self.variant(IdeMsk::FrameFormatNo) - } - #[doc = "The corresponding bit in the filter is checked."] - #[inline(always)] - pub fn frame_format_yes(self) -> &'a mut crate::W { - self.variant(IdeMsk::FrameFormatYes) - } -} -impl R { - #[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] - #[inline(always)] - pub fn flt_id2_idmask(&self) -> FltId2IdmaskR { - FltId2IdmaskR::new(self.bits & 0x1fff_ffff) - } - #[doc = "Bit 29 - Remote Transmission Request Mask"] - #[inline(always)] - pub fn rtr_msk(&self) -> RtrMskR { - RtrMskR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - ID Extended Mask"] - #[inline(always)] - pub fn ide_msk(&self) -> IdeMskR { - IdeMskR::new(((self.bits >> 30) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering"] - #[inline(always)] - pub fn flt_id2_idmask(&mut self) -> FltId2IdmaskW { - FltId2IdmaskW::new(self, 0) - } - #[doc = "Bit 29 - Remote Transmission Request Mask"] - #[inline(always)] - pub fn rtr_msk(&mut self) -> RtrMskW { - RtrMskW::new(self, 29) - } - #[doc = "Bit 30 - ID Extended Mask"] - #[inline(always)] - pub fn ide_msk(&mut self) -> IdeMskW { - IdeMskW::new(self, 30) - } -} -#[doc = "Pretended Networking ID Filter 2 or ID Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_id2_idmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_id2_idmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FltId2IdmaskSpec; -impl crate::RegisterSpec for FltId2IdmaskSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flt_id2_idmask::R`](R) reader structure"] -impl crate::Readable for FltId2IdmaskSpec {} -#[doc = "`write(|w| ..)` method takes [`flt_id2_idmask::W`](W) writer structure"] -impl crate::Writable for FltId2IdmaskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FLT_ID2_IDMASK to value 0"] -impl crate::Resettable for FltId2IdmaskSpec {} diff --git a/mcxa276-pac/src/can0/iflag1.rs b/mcxa276-pac/src/can0/iflag1.rs deleted file mode 100644 index deb77b87c..000000000 --- a/mcxa276-pac/src/can0/iflag1.rs +++ /dev/null @@ -1,302 +0,0 @@ -#[doc = "Register `IFLAG1` reader"] -pub type R = crate::R; -#[doc = "Register `IFLAG1` writer"] -pub type W = crate::W; -#[doc = "Buffer MB0 Interrupt or Clear Legacy FIFO bit\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Buf0i { - #[doc = "0: MB0 has no occurrence of successfully completed transmission or reception."] - BufferTxRxNotComplete = 0, - #[doc = "1: MB0 has successfully completed transmission or reception."] - BufferTxRxComplete = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Buf0i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUF0I` reader - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] -pub type Buf0iR = crate::BitReader; -impl Buf0iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Buf0i { - match self.bits { - false => Buf0i::BufferTxRxNotComplete, - true => Buf0i::BufferTxRxComplete, - } - } - #[doc = "MB0 has no occurrence of successfully completed transmission or reception."] - #[inline(always)] - pub fn is_buffer_tx_rx_not_complete(&self) -> bool { - *self == Buf0i::BufferTxRxNotComplete - } - #[doc = "MB0 has successfully completed transmission or reception."] - #[inline(always)] - pub fn is_buffer_tx_rx_complete(&self) -> bool { - *self == Buf0i::BufferTxRxComplete - } -} -#[doc = "Field `BUF0I` writer - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] -pub type Buf0iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf0i>; -impl<'a, REG> Buf0iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "MB0 has no occurrence of successfully completed transmission or reception."] - #[inline(always)] - pub fn buffer_tx_rx_not_complete(self) -> &'a mut crate::W { - self.variant(Buf0i::BufferTxRxNotComplete) - } - #[doc = "MB0 has successfully completed transmission or reception."] - #[inline(always)] - pub fn buffer_tx_rx_complete(self) -> &'a mut crate::W { - self.variant(Buf0i::BufferTxRxComplete) - } -} -#[doc = "Field `BUF4TO1I` reader - Buffer MBi Interrupt or Reserved"] -pub type Buf4to1iR = crate::FieldReader; -#[doc = "Field `BUF4TO1I` writer - Buffer MBi Interrupt or Reserved"] -pub type Buf4to1iW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Buffer MB5 Interrupt or Frames available in Legacy RX FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Buf5i { - #[doc = "0: No occurrence of completed transmission or reception, or no frames available"] - Id1 = 0, - #[doc = "1: MB5 completed transmission or reception, or frames available"] - Id2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Buf5i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUF5I` reader - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] -pub type Buf5iR = crate::BitReader; -impl Buf5iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Buf5i { - match self.bits { - false => Buf5i::Id1, - true => Buf5i::Id2, - } - } - #[doc = "No occurrence of completed transmission or reception, or no frames available"] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Buf5i::Id1 - } - #[doc = "MB5 completed transmission or reception, or frames available"] - #[inline(always)] - pub fn is_id2(&self) -> bool { - *self == Buf5i::Id2 - } -} -#[doc = "Field `BUF5I` writer - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] -pub type Buf5iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf5i>; -impl<'a, REG> Buf5iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No occurrence of completed transmission or reception, or no frames available"] - #[inline(always)] - pub fn id1(self) -> &'a mut crate::W { - self.variant(Buf5i::Id1) - } - #[doc = "MB5 completed transmission or reception, or frames available"] - #[inline(always)] - pub fn id2(self) -> &'a mut crate::W { - self.variant(Buf5i::Id2) - } -} -#[doc = "Buffer MB6 Interrupt or Legacy RX FIFO Warning\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Buf6i { - #[doc = "0: No occurrence of MB6 completing transmission or reception, or FIFO not almost full."] - Id1 = 0, - #[doc = "1: MB6 completed transmission or reception, or FIFO almost full."] - Id2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Buf6i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUF6I` reader - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] -pub type Buf6iR = crate::BitReader; -impl Buf6iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Buf6i { - match self.bits { - false => Buf6i::Id1, - true => Buf6i::Id2, - } - } - #[doc = "No occurrence of MB6 completing transmission or reception, or FIFO not almost full."] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Buf6i::Id1 - } - #[doc = "MB6 completed transmission or reception, or FIFO almost full."] - #[inline(always)] - pub fn is_id2(&self) -> bool { - *self == Buf6i::Id2 - } -} -#[doc = "Field `BUF6I` writer - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] -pub type Buf6iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf6i>; -impl<'a, REG> Buf6iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No occurrence of MB6 completing transmission or reception, or FIFO not almost full."] - #[inline(always)] - pub fn id1(self) -> &'a mut crate::W { - self.variant(Buf6i::Id1) - } - #[doc = "MB6 completed transmission or reception, or FIFO almost full."] - #[inline(always)] - pub fn id2(self) -> &'a mut crate::W { - self.variant(Buf6i::Id2) - } -} -#[doc = "Buffer MB7 Interrupt or Legacy RX FIFO Overflow\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Buf7i { - #[doc = "0: No occurrence of MB7 completing transmission or reception, or no FIFO overflow."] - Id1 = 0, - #[doc = "1: MB7 completed transmission or reception, or FIFO overflow."] - Id2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Buf7i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUF7I` reader - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] -pub type Buf7iR = crate::BitReader; -impl Buf7iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Buf7i { - match self.bits { - false => Buf7i::Id1, - true => Buf7i::Id2, - } - } - #[doc = "No occurrence of MB7 completing transmission or reception, or no FIFO overflow."] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Buf7i::Id1 - } - #[doc = "MB7 completed transmission or reception, or FIFO overflow."] - #[inline(always)] - pub fn is_id2(&self) -> bool { - *self == Buf7i::Id2 - } -} -#[doc = "Field `BUF7I` writer - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] -pub type Buf7iW<'a, REG> = crate::BitWriter1C<'a, REG, Buf7i>; -impl<'a, REG> Buf7iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No occurrence of MB7 completing transmission or reception, or no FIFO overflow."] - #[inline(always)] - pub fn id1(self) -> &'a mut crate::W { - self.variant(Buf7i::Id1) - } - #[doc = "MB7 completed transmission or reception, or FIFO overflow."] - #[inline(always)] - pub fn id2(self) -> &'a mut crate::W { - self.variant(Buf7i::Id2) - } -} -#[doc = "Field `BUF31TO8I` reader - Buffer MBi Interrupt"] -pub type Buf31to8iR = crate::FieldReader; -#[doc = "Field `BUF31TO8I` writer - Buffer MBi Interrupt"] -pub type Buf31to8iW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; -impl R { - #[doc = "Bit 0 - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] - #[inline(always)] - pub fn buf0i(&self) -> Buf0iR { - Buf0iR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:4 - Buffer MBi Interrupt or Reserved"] - #[inline(always)] - pub fn buf4to1i(&self) -> Buf4to1iR { - Buf4to1iR::new(((self.bits >> 1) & 0x0f) as u8) - } - #[doc = "Bit 5 - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] - #[inline(always)] - pub fn buf5i(&self) -> Buf5iR { - Buf5iR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] - #[inline(always)] - pub fn buf6i(&self) -> Buf6iR { - Buf6iR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] - #[inline(always)] - pub fn buf7i(&self) -> Buf7iR { - Buf7iR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:31 - Buffer MBi Interrupt"] - #[inline(always)] - pub fn buf31to8i(&self) -> Buf31to8iR { - Buf31to8iR::new((self.bits >> 8) & 0x00ff_ffff) - } -} -impl W { - #[doc = "Bit 0 - Buffer MB0 Interrupt or Clear Legacy FIFO bit"] - #[inline(always)] - pub fn buf0i(&mut self) -> Buf0iW { - Buf0iW::new(self, 0) - } - #[doc = "Bits 1:4 - Buffer MBi Interrupt or Reserved"] - #[inline(always)] - pub fn buf4to1i(&mut self) -> Buf4to1iW { - Buf4to1iW::new(self, 1) - } - #[doc = "Bit 5 - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO"] - #[inline(always)] - pub fn buf5i(&mut self) -> Buf5iW { - Buf5iW::new(self, 5) - } - #[doc = "Bit 6 - Buffer MB6 Interrupt or Legacy RX FIFO Warning"] - #[inline(always)] - pub fn buf6i(&mut self) -> Buf6iW { - Buf6iW::new(self, 6) - } - #[doc = "Bit 7 - Buffer MB7 Interrupt or Legacy RX FIFO Overflow"] - #[inline(always)] - pub fn buf7i(&mut self) -> Buf7iW { - Buf7iW::new(self, 7) - } - #[doc = "Bits 8:31 - Buffer MBi Interrupt"] - #[inline(always)] - pub fn buf31to8i(&mut self) -> Buf31to8iW { - Buf31to8iW::new(self, 8) - } -} -#[doc = "Interrupt Flags 1\n\nYou can [`read`](crate::Reg::read) this register and get [`iflag1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iflag1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Iflag1Spec; -impl crate::RegisterSpec for Iflag1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`iflag1::R`](R) reader structure"] -impl crate::Readable for Iflag1Spec {} -#[doc = "`write(|w| ..)` method takes [`iflag1::W`](W) writer structure"] -impl crate::Writable for Iflag1Spec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; -} -#[doc = "`reset()` method sets IFLAG1 to value 0"] -impl crate::Resettable for Iflag1Spec {} diff --git a/mcxa276-pac/src/can0/imask1.rs b/mcxa276-pac/src/can0/imask1.rs deleted file mode 100644 index 5986ccdb8..000000000 --- a/mcxa276-pac/src/can0/imask1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `IMASK1` reader"] -pub type R = crate::R; -#[doc = "Register `IMASK1` writer"] -pub type W = crate::W; -#[doc = "Field `BUF31TO0M` reader - Buffer MBi Mask"] -pub type Buf31to0mR = crate::FieldReader; -#[doc = "Field `BUF31TO0M` writer - Buffer MBi Mask"] -pub type Buf31to0mW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Buffer MBi Mask"] - #[inline(always)] - pub fn buf31to0m(&self) -> Buf31to0mR { - Buf31to0mR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Buffer MBi Mask"] - #[inline(always)] - pub fn buf31to0m(&mut self) -> Buf31to0mW { - Buf31to0mW::new(self, 0) - } -} -#[doc = "Interrupt Masks 1\n\nYou can [`read`](crate::Reg::read) this register and get [`imask1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imask1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Imask1Spec; -impl crate::RegisterSpec for Imask1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`imask1::R`](R) reader structure"] -impl crate::Readable for Imask1Spec {} -#[doc = "`write(|w| ..)` method takes [`imask1::W`](W) writer structure"] -impl crate::Writable for Imask1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IMASK1 to value 0"] -impl crate::Resettable for Imask1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs deleted file mode 100644 index c29340f74..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB0_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb0_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb0_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb0_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb0_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb0_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs deleted file mode 100644 index e19ad4c67..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB0_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb0_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb0_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb0_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb0_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb0_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs deleted file mode 100644 index 332317c9b..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb0_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb0_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb0_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb0_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb0_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs deleted file mode 100644 index 0fab7b675..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb0_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb0_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb0_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb0_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb0_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs deleted file mode 100644 index 29222b9a0..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb0_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb0_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb0_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb0_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb0_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs deleted file mode 100644 index 575981d40..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb0_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb0_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb0_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb0_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb0_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb0_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb0_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb0_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb0_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb0_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs deleted file mode 100644 index 430e55b50..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB10_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb10_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb10_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb10_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb10_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb10_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs deleted file mode 100644 index 2922c6d28..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB10_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb10_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb10_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb10_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb10_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb10_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word0.rs deleted file mode 100644 index 7ab1489bc..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb10_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb10_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb10_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb10_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb10_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word1.rs deleted file mode 100644 index 953a98e59..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb10_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb10_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb10_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb10_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb10_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word2.rs deleted file mode 100644 index 6204cc1a3..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb10_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb10_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb10_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb10_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb10_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word3.rs deleted file mode 100644 index 680442f7b..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb10_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb10_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb10_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb10_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb10_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb10_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb10_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb10_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb10_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb10_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs deleted file mode 100644 index b22de9f28..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB11_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb11_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb11_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb11_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb11_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb11_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs deleted file mode 100644 index 125c596e1..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB11_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb11_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb11_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb11_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb11_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb11_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word0.rs deleted file mode 100644 index 785ed8be5..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb11_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb11_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb11_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb11_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb11_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word1.rs deleted file mode 100644 index c3965cf1a..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb11_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb11_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb11_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb11_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb11_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word2.rs deleted file mode 100644 index c660785c8..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb11_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb11_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb11_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb11_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb11_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word3.rs deleted file mode 100644 index 07a278f42..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb11_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb11_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb11_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb11_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb11_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb11_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb11_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb11_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb11_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb11_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs deleted file mode 100644 index 24585d132..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB12_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb12_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb12_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb12_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb12_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb12_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs deleted file mode 100644 index 8a69cf7c0..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB12_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb12_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb12_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb12_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb12_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb12_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word0.rs deleted file mode 100644 index 8b41e97b4..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB12_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb12_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb12_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb12_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb12_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb12_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word1.rs deleted file mode 100644 index d436e50b9..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB12_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb12_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb12_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb12_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb12_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb12_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word2.rs deleted file mode 100644 index 2e7612119..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB12_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb12_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb12_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb12_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb12_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb12_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word3.rs deleted file mode 100644 index a5a152f17..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb12_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB12_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb12_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb12_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb12_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb12_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb12_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb12_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb12_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb12_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb12_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_cs.rs deleted file mode 100644 index 7ceb531c7..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB13_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb13_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb13_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb13_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb13_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb13_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_id.rs deleted file mode 100644 index 0b46483f9..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB13_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb13_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb13_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb13_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb13_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb13_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word0.rs deleted file mode 100644 index c41f50217..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB13_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb13_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb13_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb13_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb13_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb13_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word1.rs deleted file mode 100644 index 6970b5615..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB13_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb13_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb13_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb13_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb13_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb13_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word2.rs deleted file mode 100644 index 3fea5973a..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB13_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb13_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb13_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb13_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb13_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb13_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word3.rs deleted file mode 100644 index 5d3b410ca..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb13_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB13_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb13_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb13_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb13_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb13_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb13_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb13_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb13_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb13_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb13_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_cs.rs deleted file mode 100644 index 948fd734f..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB14_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb14_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb14_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb14_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb14_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb14_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_id.rs deleted file mode 100644 index 080ea3d76..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB14_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb14_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb14_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb14_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb14_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb14_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word0.rs deleted file mode 100644 index fe975bc76..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB14_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb14_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb14_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb14_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb14_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb14_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word1.rs deleted file mode 100644 index e2b11b779..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB14_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb14_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb14_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb14_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb14_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb14_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word2.rs deleted file mode 100644 index f90366aeb..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB14_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb14_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb14_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb14_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb14_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb14_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word3.rs deleted file mode 100644 index 3827e0cce..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb14_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB14_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb14_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb14_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb14_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb14_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb14_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb14_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb14_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb14_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb14_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_cs.rs deleted file mode 100644 index 1fdc8daba..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB15_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb15_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb15_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb15_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb15_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb15_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_id.rs deleted file mode 100644 index b4bf7a53e..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB15_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb15_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb15_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb15_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb15_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb15_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word0.rs deleted file mode 100644 index cda954a25..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB15_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb15_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb15_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb15_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb15_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb15_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word1.rs deleted file mode 100644 index 91947932e..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB15_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb15_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb15_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb15_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb15_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb15_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word2.rs deleted file mode 100644 index 315a6e7f7..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB15_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb15_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb15_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb15_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb15_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb15_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word3.rs deleted file mode 100644 index e27cf31ab..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb15_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB15_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb15_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb15_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb15_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb15_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb15_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb15_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb15_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb15_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb15_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_cs.rs deleted file mode 100644 index d9a648edf..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB16_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb16_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb16_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb16_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb16_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb16_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs deleted file mode 100644 index 1af53e305..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB16_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb16_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb16_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb16_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb16_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb16_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word0.rs deleted file mode 100644 index e8bffa515..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB16_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb16_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb16_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb16_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb16_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb16_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word1.rs deleted file mode 100644 index f0f249b26..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB16_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb16_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb16_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb16_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb16_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb16_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word2.rs deleted file mode 100644 index b49cee5c9..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB16_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb16_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb16_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb16_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb16_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb16_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word3.rs deleted file mode 100644 index 34b90351a..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb16_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB16_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb16_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb16_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb16_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb16_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb16_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb16_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb16_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb16_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb16_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs deleted file mode 100644 index 224e1cf7f..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB17_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb17_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb17_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb17_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb17_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb17_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs deleted file mode 100644 index fa139a9e7..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB17_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb17_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb17_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb17_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb17_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb17_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word0.rs deleted file mode 100644 index e14f01a0c..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB17_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb17_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb17_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb17_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb17_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb17_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word1.rs deleted file mode 100644 index 64455ba31..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB17_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb17_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb17_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb17_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb17_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb17_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word2.rs deleted file mode 100644 index d80679cf8..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB17_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb17_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb17_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb17_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb17_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb17_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word3.rs deleted file mode 100644 index 4c13c6b41..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb17_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB17_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb17_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb17_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb17_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb17_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb17_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb17_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb17_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb17_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb17_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs deleted file mode 100644 index 4ad2f753d..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB18_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb18_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb18_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb18_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb18_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb18_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs deleted file mode 100644 index 4399fe2a3..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB18_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb18_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb18_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb18_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb18_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb18_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word0.rs deleted file mode 100644 index c6cad94d4..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB18_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb18_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb18_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb18_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb18_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb18_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word1.rs deleted file mode 100644 index b8c414931..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB18_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb18_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb18_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb18_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb18_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb18_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word2.rs deleted file mode 100644 index eaf1e0fe3..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB18_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb18_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb18_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb18_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb18_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb18_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word3.rs deleted file mode 100644 index 2650e0bcf..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb18_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB18_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb18_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb18_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb18_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb18_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb18_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb18_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb18_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb18_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb18_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs deleted file mode 100644 index 5e511d69c..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB19_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb19_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb19_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb19_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb19_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb19_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_id.rs deleted file mode 100644 index ce7080934..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB19_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb19_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb19_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb19_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb19_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb19_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word0.rs deleted file mode 100644 index 3c487ef19..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB19_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb19_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb19_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb19_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb19_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb19_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word1.rs deleted file mode 100644 index e0e0aedba..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB19_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb19_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb19_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb19_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb19_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb19_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word2.rs deleted file mode 100644 index d2d99ba39..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB19_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb19_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb19_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb19_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb19_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb19_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word3.rs deleted file mode 100644 index 00767ff58..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb19_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB19_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb19_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb19_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb19_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb19_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb19_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb19_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb19_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb19_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb19_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_cs.rs deleted file mode 100644 index cb7efd9ae..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB1_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb1_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb1_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb1_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb1_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb1_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_id.rs deleted file mode 100644 index 259e9f19a..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB1_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb1_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb1_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb1_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb1_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb1_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word0.rs deleted file mode 100644 index f21e2d94d..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb1_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb1_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb1_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb1_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb1_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word1.rs deleted file mode 100644 index 0c15b09b5..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb1_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb1_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb1_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb1_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb1_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word2.rs deleted file mode 100644 index c04cb3992..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb1_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb1_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb1_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb1_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb1_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word3.rs deleted file mode 100644 index c9ecc19ac..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb1_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb1_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb1_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb1_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb1_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb1_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb1_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb1_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb1_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb1_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_cs.rs deleted file mode 100644 index ab229e3db..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB20_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb20_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb20_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb20_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb20_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb20_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_id.rs deleted file mode 100644 index d8fb8761d..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB20_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb20_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb20_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb20_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb20_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb20_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word0.rs deleted file mode 100644 index b637d1854..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB20_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb20_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb20_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb20_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb20_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb20_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word1.rs deleted file mode 100644 index 9c30a9bc9..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB20_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb20_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb20_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb20_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb20_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb20_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word2.rs deleted file mode 100644 index 783d96107..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB20_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb20_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb20_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb20_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb20_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb20_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word3.rs deleted file mode 100644 index bc4df50d1..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb20_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB20_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb20_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb20_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb20_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb20_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb20_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb20_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb20_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb20_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb20_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_cs.rs deleted file mode 100644 index 2d5dfb6b2..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB2_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb2_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb2_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb2_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb2_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb2_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_id.rs deleted file mode 100644 index 68ee1b1cc..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB2_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb2_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb2_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb2_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb2_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb2_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word0.rs deleted file mode 100644 index a7e570efa..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb2_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb2_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb2_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb2_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb2_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word1.rs deleted file mode 100644 index e28b201fe..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb2_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb2_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb2_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb2_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb2_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word2.rs deleted file mode 100644 index f7f8e46aa..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb2_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb2_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb2_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb2_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb2_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word3.rs deleted file mode 100644 index 4eb044066..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb2_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb2_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb2_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb2_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb2_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb2_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb2_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb2_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb2_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb2_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_cs.rs deleted file mode 100644 index 058fe743b..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB3_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb3_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb3_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb3_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb3_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb3_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_id.rs deleted file mode 100644 index b67b967ba..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB3_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb3_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb3_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb3_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb3_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb3_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word0.rs deleted file mode 100644 index 9054eeb51..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb3_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb3_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb3_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb3_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb3_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word1.rs deleted file mode 100644 index fa3770840..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb3_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb3_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb3_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb3_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb3_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word2.rs deleted file mode 100644 index f14b5778c..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb3_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb3_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb3_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb3_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb3_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word3.rs deleted file mode 100644 index c04a9c2fe..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb3_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb3_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb3_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb3_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb3_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb3_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb3_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb3_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb3_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb3_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_cs.rs deleted file mode 100644 index 42d4eb98c..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB4_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb4_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb4_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb4_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb4_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb4_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_id.rs deleted file mode 100644 index 287d2806b..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB4_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb4_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb4_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb4_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb4_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb4_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word0.rs deleted file mode 100644 index 761e0aceb..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb4_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb4_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb4_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb4_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb4_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word1.rs deleted file mode 100644 index a4bd9817e..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb4_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb4_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb4_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb4_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb4_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word2.rs deleted file mode 100644 index 6f26be3ea..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb4_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb4_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb4_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb4_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb4_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word3.rs deleted file mode 100644 index 862656876..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb4_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb4_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb4_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb4_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb4_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb4_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb4_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb4_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb4_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb4_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_cs.rs deleted file mode 100644 index d4ff540db..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB5_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb5_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb5_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb5_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb5_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb5_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_id.rs deleted file mode 100644 index eb4cfd3e6..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB5_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb5_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb5_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb5_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb5_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb5_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word0.rs deleted file mode 100644 index d7105b181..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb5_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb5_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb5_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb5_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb5_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word1.rs deleted file mode 100644 index 4e7398430..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb5_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb5_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb5_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb5_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb5_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word2.rs deleted file mode 100644 index f1c0145e2..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb5_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb5_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb5_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb5_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb5_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word3.rs deleted file mode 100644 index df620238b..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb5_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb5_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb5_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb5_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb5_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb5_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb5_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb5_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb5_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb5_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_cs.rs deleted file mode 100644 index 215142dc9..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB6_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb6_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb6_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb6_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb6_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb6_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_id.rs deleted file mode 100644 index d9806f764..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB6_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb6_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb6_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb6_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb6_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb6_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word0.rs deleted file mode 100644 index 39236f1a8..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb6_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb6_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb6_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb6_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb6_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word1.rs deleted file mode 100644 index 8ea4c1185..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb6_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb6_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb6_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb6_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb6_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word2.rs deleted file mode 100644 index 0367a8d13..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb6_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb6_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb6_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb6_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb6_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word3.rs deleted file mode 100644 index d96e8e741..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb6_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb6_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb6_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb6_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb6_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb6_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb6_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb6_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb6_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb6_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_cs.rs deleted file mode 100644 index e5b0cb760..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB7_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb7_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb7_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb7_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb7_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb7_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_id.rs deleted file mode 100644 index 1d04c519b..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB7_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb7_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb7_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb7_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb7_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb7_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word0.rs deleted file mode 100644 index 78f1549a2..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb7_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb7_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb7_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb7_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb7_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word1.rs deleted file mode 100644 index f161f9bca..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb7_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb7_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb7_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb7_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb7_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word2.rs deleted file mode 100644 index 7b6d45f9d..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb7_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb7_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb7_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb7_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb7_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word3.rs deleted file mode 100644 index 3bea26157..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb7_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb7_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb7_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb7_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb7_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb7_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb7_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb7_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb7_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb7_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_cs.rs deleted file mode 100644 index c2801f800..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB8_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb8_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb8_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb8_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb8_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb8_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_id.rs deleted file mode 100644 index 1f95b479d..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB8_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb8_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb8_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb8_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb8_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb8_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word0.rs deleted file mode 100644 index d8d277abc..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb8_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb8_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb8_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb8_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb8_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word1.rs deleted file mode 100644 index e54d7a788..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb8_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb8_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb8_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb8_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb8_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word2.rs deleted file mode 100644 index 186ccb68c..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb8_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb8_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb8_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb8_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb8_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word3.rs deleted file mode 100644 index 3e39d7f33..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb8_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb8_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb8_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb8_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb8_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb8_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb8_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb8_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb8_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb8_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_cs.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_cs.rs deleted file mode 100644 index 17e9c958a..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB9_16B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_16B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb9_16bCsSpec; -impl crate::RegisterSpec for Mb16bGroupMb9_16bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_cs::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb9_16bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_cs::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb9_16bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_16B_CS to value 0"] -impl crate::Resettable for Mb16bGroupMb9_16bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_id.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_id.rs deleted file mode 100644 index 9ed56573a..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB9_16B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_16B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb9_16bIdSpec; -impl crate::RegisterSpec for Mb16bGroupMb9_16bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_id::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb9_16bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_id::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb9_16bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_16B_ID to value 0"] -impl crate::Resettable for Mb16bGroupMb9_16bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word0.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word0.rs deleted file mode 100644 index e981fa693..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_16B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_16B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb9_16bWord0Spec; -impl crate::RegisterSpec for Mb16bGroupMb9_16bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word0::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb9_16bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word0::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb9_16bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_16B_WORD0 to value 0"] -impl crate::Resettable for Mb16bGroupMb9_16bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word1.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word1.rs deleted file mode 100644 index b73f4b095..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_16B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_16B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb9_16bWord1Spec; -impl crate::RegisterSpec for Mb16bGroupMb9_16bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word1::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb9_16bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word1::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb9_16bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_16B_WORD1 to value 0"] -impl crate::Resettable for Mb16bGroupMb9_16bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word2.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word2.rs deleted file mode 100644 index 9c42757b2..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_16B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_16B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb9_16bWord2Spec; -impl crate::RegisterSpec for Mb16bGroupMb9_16bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word2::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb9_16bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word2::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb9_16bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_16B_WORD2 to value 0"] -impl crate::Resettable for Mb16bGroupMb9_16bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word3.rs b/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word3.rs deleted file mode 100644 index d25fc7766..000000000 --- a/mcxa276-pac/src/can0/mb_16b_group_mb9_16b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_16B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_16B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_16B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_16b_group_mb9_16b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_16b_group_mb9_16b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb16bGroupMb9_16bWord3Spec; -impl crate::RegisterSpec for Mb16bGroupMb9_16bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_16b_group_mb9_16b_word3::R`](R) reader structure"] -impl crate::Readable for Mb16bGroupMb9_16bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_16b_group_mb9_16b_word3::W`](W) writer structure"] -impl crate::Writable for Mb16bGroupMb9_16bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_16B_WORD3 to value 0"] -impl crate::Resettable for Mb16bGroupMb9_16bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_cs.rs deleted file mode 100644 index 467d57757..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB0_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_id.rs deleted file mode 100644 index 79f2779b4..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB0_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word0.rs deleted file mode 100644 index a387d6732..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word1.rs deleted file mode 100644 index 432439a3e..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word2.rs deleted file mode 100644 index 129b48cfd..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word3.rs deleted file mode 100644 index 25971d452..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word4.rs deleted file mode 100644 index 10c434dd6..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word5.rs deleted file mode 100644 index 990bf3d05..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word6.rs deleted file mode 100644 index 246952dbb..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word7.rs deleted file mode 100644 index 604431468..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb0_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb0_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb0_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb0_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb0_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb0_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb0_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb0_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb0_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb0_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_cs.rs deleted file mode 100644 index 4f1e20248..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB10_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_id.rs deleted file mode 100644 index 1acb1da9c..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB10_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word0.rs deleted file mode 100644 index 656e177e1..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word1.rs deleted file mode 100644 index 3f3c8e3dd..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word2.rs deleted file mode 100644 index e1dbdd349..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word3.rs deleted file mode 100644 index 6f196e1a3..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word4.rs deleted file mode 100644 index 92474dc28..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word5.rs deleted file mode 100644 index b0ffed129..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word6.rs deleted file mode 100644 index 8ff483249..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word7.rs deleted file mode 100644 index 637c8e200..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb10_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb10_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb10_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb10_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb10_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb10_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb10_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb10_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb10_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb10_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_cs.rs deleted file mode 100644 index 36b1a5555..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB11_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_id.rs deleted file mode 100644 index 8f9d7c60f..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB11_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word0.rs deleted file mode 100644 index ca8d38f71..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word1.rs deleted file mode 100644 index 1a3069b3a..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word2.rs deleted file mode 100644 index c05130819..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word3.rs deleted file mode 100644 index b5f8fc0ae..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word4.rs deleted file mode 100644 index 6b4e2b511..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word5.rs deleted file mode 100644 index aab54a566..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word6.rs deleted file mode 100644 index ff793261e..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word7.rs deleted file mode 100644 index ab589dec3..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb11_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb11_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb11_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb11_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb11_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb11_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb11_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb11_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb11_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb11_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_cs.rs deleted file mode 100644 index 23f4f08b7..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB1_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_id.rs deleted file mode 100644 index 086617499..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB1_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word0.rs deleted file mode 100644 index e5f5035f0..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word1.rs deleted file mode 100644 index 08a95adc0..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word2.rs deleted file mode 100644 index d83ee61bf..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word3.rs deleted file mode 100644 index 48b94082a..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word4.rs deleted file mode 100644 index a343fac56..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word5.rs deleted file mode 100644 index 910ac5f43..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word6.rs deleted file mode 100644 index e137c129a..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word7.rs deleted file mode 100644 index 2c6e371ec..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb1_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb1_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb1_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb1_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb1_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb1_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb1_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb1_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb1_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb1_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_cs.rs deleted file mode 100644 index 988c5f86c..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB2_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_id.rs deleted file mode 100644 index 2906375c2..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB2_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word0.rs deleted file mode 100644 index 2f4965a78..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word1.rs deleted file mode 100644 index f48b2ee62..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word2.rs deleted file mode 100644 index b422f8cce..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word3.rs deleted file mode 100644 index 5e2914bc6..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word4.rs deleted file mode 100644 index d85b8ecac..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word5.rs deleted file mode 100644 index 3d17bd888..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word6.rs deleted file mode 100644 index cf72152d9..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word7.rs deleted file mode 100644 index 968f8b0b0..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb2_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb2_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb2_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb2_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb2_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb2_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb2_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb2_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb2_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb2_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_cs.rs deleted file mode 100644 index d33d57e28..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB3_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_id.rs deleted file mode 100644 index 569d47314..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB3_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word0.rs deleted file mode 100644 index e46841da9..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word1.rs deleted file mode 100644 index 5a19c29e6..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word2.rs deleted file mode 100644 index 25fd22c8d..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word3.rs deleted file mode 100644 index 660694e3e..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word4.rs deleted file mode 100644 index 6c0f0c5fd..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word5.rs deleted file mode 100644 index 92c575bbf..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word6.rs deleted file mode 100644 index e53f9efa5..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word7.rs deleted file mode 100644 index 9b933c07f..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb3_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb3_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb3_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb3_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb3_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb3_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb3_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb3_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb3_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb3_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_cs.rs deleted file mode 100644 index 5b6cfcc36..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB4_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_id.rs deleted file mode 100644 index afb2e5fc4..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB4_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word0.rs deleted file mode 100644 index ef7d272ee..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word1.rs deleted file mode 100644 index e56910867..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word2.rs deleted file mode 100644 index 5de3df94f..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word3.rs deleted file mode 100644 index c4e211cc0..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word4.rs deleted file mode 100644 index 0819e875c..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word5.rs deleted file mode 100644 index e8c491f85..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word6.rs deleted file mode 100644 index 977da0c17..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word7.rs deleted file mode 100644 index 37efefcab..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb4_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb4_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb4_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb4_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb4_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb4_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb4_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb4_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb4_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb4_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_cs.rs deleted file mode 100644 index e87b29f90..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB5_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_id.rs deleted file mode 100644 index 145ab2a68..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB5_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word0.rs deleted file mode 100644 index c3bf8fba4..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word1.rs deleted file mode 100644 index 577ece605..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word2.rs deleted file mode 100644 index d036cabe7..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word3.rs deleted file mode 100644 index f5129b317..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word4.rs deleted file mode 100644 index b5af7b961..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word5.rs deleted file mode 100644 index d538364c5..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word6.rs deleted file mode 100644 index 6a280cf42..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word7.rs deleted file mode 100644 index a60a19bb4..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb5_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb5_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb5_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb5_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb5_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb5_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb5_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb5_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb5_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb5_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_cs.rs deleted file mode 100644 index fd6908b79..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB6_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_id.rs deleted file mode 100644 index 9cfe777a0..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB6_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word0.rs deleted file mode 100644 index 24f7b47f9..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word1.rs deleted file mode 100644 index 632c1c1a8..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word2.rs deleted file mode 100644 index fac2552ed..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word3.rs deleted file mode 100644 index bb31710f3..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word4.rs deleted file mode 100644 index 69e7bfb9e..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word5.rs deleted file mode 100644 index 20fe09611..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word6.rs deleted file mode 100644 index e80370b2b..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word7.rs deleted file mode 100644 index 49736d108..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb6_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb6_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb6_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb6_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb6_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb6_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb6_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb6_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb6_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb6_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_cs.rs deleted file mode 100644 index 0aa1b1fae..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB7_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_id.rs deleted file mode 100644 index 8ba4363d0..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB7_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word0.rs deleted file mode 100644 index c2d3a2f33..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word1.rs deleted file mode 100644 index 362a42282..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word2.rs deleted file mode 100644 index 05a753799..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word3.rs deleted file mode 100644 index fc71a3a73..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word4.rs deleted file mode 100644 index 7a1beb53d..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word5.rs deleted file mode 100644 index 3a90c35af..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word6.rs deleted file mode 100644 index 4296781ac..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word7.rs deleted file mode 100644 index 663482e2a..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb7_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb7_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb7_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb7_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb7_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb7_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb7_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb7_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb7_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb7_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_cs.rs deleted file mode 100644 index 3c6c91e4f..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB8_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_id.rs deleted file mode 100644 index b7a836be3..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB8_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word0.rs deleted file mode 100644 index ce539c14a..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word1.rs deleted file mode 100644 index 532fd7383..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word2.rs deleted file mode 100644 index e3661723c..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word3.rs deleted file mode 100644 index 6e9e51eaa..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word4.rs deleted file mode 100644 index 8bdf9b5fb..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word5.rs deleted file mode 100644 index 224f5c3fa..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word6.rs deleted file mode 100644 index 54da88f10..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word7.rs deleted file mode 100644 index 1bffb4321..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb8_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb8_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb8_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb8_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb8_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb8_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb8_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb8_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb8_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb8_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_cs.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_cs.rs deleted file mode 100644 index da396702e..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB9_32B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bCsSpec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_cs::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_cs::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_CS to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_id.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_id.rs deleted file mode 100644 index 23e966337..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB9_32B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bIdSpec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_id::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_id::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_ID to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word0.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word0.rs deleted file mode 100644 index 2fdc71d30..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord0Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word0::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word0::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD0 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word1.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word1.rs deleted file mode 100644 index 6141a6833..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord1Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word1::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word1::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD1 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word2.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word2.rs deleted file mode 100644 index e74137add..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord2Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word2::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word2::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD2 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word3.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word3.rs deleted file mode 100644 index baee3cf8b..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord3Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word3::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word3::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD3 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word4.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word4.rs deleted file mode 100644 index b3031a494..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord4Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word4::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word4::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD4 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word5.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word5.rs deleted file mode 100644 index 35b8ec062..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord5Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word5::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word5::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD5 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word6.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word6.rs deleted file mode 100644 index 46bed45fc..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord6Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word6::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word6::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD6 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word7.rs b/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word7.rs deleted file mode 100644 index b048c142a..000000000 --- a/mcxa276-pac/src/can0/mb_32b_group_mb9_32b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_32B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_32B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_32B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_32b_group_mb9_32b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_32b_group_mb9_32b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb32bGroupMb9_32bWord7Spec; -impl crate::RegisterSpec for Mb32bGroupMb9_32bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_32b_group_mb9_32b_word7::R`](R) reader structure"] -impl crate::Readable for Mb32bGroupMb9_32bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_32b_group_mb9_32b_word7::W`](W) writer structure"] -impl crate::Writable for Mb32bGroupMb9_32bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_32B_WORD7 to value 0"] -impl crate::Resettable for Mb32bGroupMb9_32bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_cs.rs deleted file mode 100644 index e472bf9b2..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB0_64B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bCsSpec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_cs::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_cs::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_CS to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_id.rs deleted file mode 100644 index e7ec8fc22..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB0_64B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bIdSpec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_id::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_id::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_ID to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word0.rs deleted file mode 100644 index 52b560d2a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord0Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word0::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word0::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD0 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word1.rs deleted file mode 100644 index db57f1a9f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord1Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word1::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word1::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD1 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word10.rs deleted file mode 100644 index 80571ca7e..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte43R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte42R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte41R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte40R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&self) -> DataByte43R { - DataByte43R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&self) -> DataByte42R { - DataByte42R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&self) -> DataByte41R { - DataByte41R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&self) -> DataByte40R { - DataByte40R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&mut self) -> DataByte43W { - DataByte43W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&mut self) -> DataByte42W { - DataByte42W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&mut self) -> DataByte41W { - DataByte41W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&mut self) -> DataByte40W { - DataByte40W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord10Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word10::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word10::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD10 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word11.rs deleted file mode 100644 index 57f152338..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte47R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte46R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte45R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte44R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&self) -> DataByte47R { - DataByte47R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&self) -> DataByte46R { - DataByte46R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&self) -> DataByte45R { - DataByte45R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&self) -> DataByte44R { - DataByte44R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&mut self) -> DataByte47W { - DataByte47W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&mut self) -> DataByte46W { - DataByte46W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&mut self) -> DataByte45W { - DataByte45W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&mut self) -> DataByte44W { - DataByte44W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord11Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word11::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word11::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD11 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word12.rs deleted file mode 100644 index d40138602..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte51R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte50R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte49R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte48R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&self) -> DataByte51R { - DataByte51R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&self) -> DataByte50R { - DataByte50R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&self) -> DataByte49R { - DataByte49R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&self) -> DataByte48R { - DataByte48R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&mut self) -> DataByte51W { - DataByte51W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&mut self) -> DataByte50W { - DataByte50W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&mut self) -> DataByte49W { - DataByte49W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&mut self) -> DataByte48W { - DataByte48W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord12Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word12::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word12::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD12 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word13.rs deleted file mode 100644 index 19a217728..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte55R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte54R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte53R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte52R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&self) -> DataByte55R { - DataByte55R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&self) -> DataByte54R { - DataByte54R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&self) -> DataByte53R { - DataByte53R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&self) -> DataByte52R { - DataByte52R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&mut self) -> DataByte55W { - DataByte55W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&mut self) -> DataByte54W { - DataByte54W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&mut self) -> DataByte53W { - DataByte53W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&mut self) -> DataByte52W { - DataByte52W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord13Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word13::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word13::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD13 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word14.rs deleted file mode 100644 index 4152a3698..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte59R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte58R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte57R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte56R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&self) -> DataByte59R { - DataByte59R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&self) -> DataByte58R { - DataByte58R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&self) -> DataByte57R { - DataByte57R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&self) -> DataByte56R { - DataByte56R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&mut self) -> DataByte59W { - DataByte59W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&mut self) -> DataByte58W { - DataByte58W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&mut self) -> DataByte57W { - DataByte57W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&mut self) -> DataByte56W { - DataByte56W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord14Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word14::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word14::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD14 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word15.rs deleted file mode 100644 index 84551327c..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte63R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte62R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte61R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte60R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&self) -> DataByte63R { - DataByte63R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&self) -> DataByte62R { - DataByte62R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&self) -> DataByte61R { - DataByte61R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&self) -> DataByte60R { - DataByte60R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&mut self) -> DataByte63W { - DataByte63W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&mut self) -> DataByte62W { - DataByte62W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&mut self) -> DataByte61W { - DataByte61W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&mut self) -> DataByte60W { - DataByte60W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord15Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word15::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word15::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD15 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word2.rs deleted file mode 100644 index 11224e817..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord2Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word2::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word2::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD2 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word3.rs deleted file mode 100644 index 518e81e10..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord3Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word3::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word3::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD3 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word4.rs deleted file mode 100644 index 00a7b21a5..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord4Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word4::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word4::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD4 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word5.rs deleted file mode 100644 index 7fa733ead..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord5Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word5::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word5::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD5 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word6.rs deleted file mode 100644 index d84ec29a8..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord6Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word6::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word6::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD6 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word7.rs deleted file mode 100644 index e7316091d..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord7Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word7::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word7::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD7 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word8.rs deleted file mode 100644 index c98cba9bb..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word8.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD8` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD8` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte35R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte34R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte33R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte32R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&self) -> DataByte35R { - DataByte35R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&self) -> DataByte34R { - DataByte34R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&self) -> DataByte33R { - DataByte33R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&self) -> DataByte32R { - DataByte32R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&mut self) -> DataByte35W { - DataByte35W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&mut self) -> DataByte34W { - DataByte34W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&mut self) -> DataByte33W { - DataByte33W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&mut self) -> DataByte32W { - DataByte32W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord8Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word8::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word8::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD8 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word9.rs deleted file mode 100644 index 853c59ac9..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb0_64b_word9.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_64B_WORD9` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_64B_WORD9` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte39R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte38R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte37R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte36R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&self) -> DataByte39R { - DataByte39R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&self) -> DataByte38R { - DataByte38R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&self) -> DataByte37R { - DataByte37R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&self) -> DataByte36R { - DataByte36R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&mut self) -> DataByte39W { - DataByte39W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&mut self) -> DataByte38W { - DataByte38W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&mut self) -> DataByte37W { - DataByte37W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&mut self) -> DataByte36W { - DataByte36W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb0_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb0_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb0_64bWord9Spec; -impl crate::RegisterSpec for Mb64bGroupMb0_64bWord9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb0_64b_word9::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb0_64bWord9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb0_64b_word9::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb0_64bWord9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_64B_WORD9 to value 0"] -impl crate::Resettable for Mb64bGroupMb0_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_cs.rs deleted file mode 100644 index 332b83754..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB1_64B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bCsSpec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_cs::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_cs::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_CS to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_id.rs deleted file mode 100644 index e48e6c866..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB1_64B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bIdSpec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_id::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_id::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_ID to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word0.rs deleted file mode 100644 index 3d6c5956b..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord0Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word0::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word0::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD0 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word1.rs deleted file mode 100644 index a1962ffca..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord1Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word1::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word1::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD1 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word10.rs deleted file mode 100644 index 34dcd5f45..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte43R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte42R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte41R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte40R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&self) -> DataByte43R { - DataByte43R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&self) -> DataByte42R { - DataByte42R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&self) -> DataByte41R { - DataByte41R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&self) -> DataByte40R { - DataByte40R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&mut self) -> DataByte43W { - DataByte43W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&mut self) -> DataByte42W { - DataByte42W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&mut self) -> DataByte41W { - DataByte41W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&mut self) -> DataByte40W { - DataByte40W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord10Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word10::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word10::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD10 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word11.rs deleted file mode 100644 index 5aedc20d2..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte47R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte46R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte45R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte44R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&self) -> DataByte47R { - DataByte47R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&self) -> DataByte46R { - DataByte46R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&self) -> DataByte45R { - DataByte45R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&self) -> DataByte44R { - DataByte44R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&mut self) -> DataByte47W { - DataByte47W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&mut self) -> DataByte46W { - DataByte46W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&mut self) -> DataByte45W { - DataByte45W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&mut self) -> DataByte44W { - DataByte44W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord11Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word11::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word11::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD11 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word12.rs deleted file mode 100644 index b06007f12..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte51R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte50R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte49R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte48R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&self) -> DataByte51R { - DataByte51R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&self) -> DataByte50R { - DataByte50R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&self) -> DataByte49R { - DataByte49R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&self) -> DataByte48R { - DataByte48R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&mut self) -> DataByte51W { - DataByte51W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&mut self) -> DataByte50W { - DataByte50W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&mut self) -> DataByte49W { - DataByte49W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&mut self) -> DataByte48W { - DataByte48W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord12Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word12::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word12::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD12 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word13.rs deleted file mode 100644 index 5d63a7340..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte55R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte54R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte53R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte52R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&self) -> DataByte55R { - DataByte55R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&self) -> DataByte54R { - DataByte54R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&self) -> DataByte53R { - DataByte53R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&self) -> DataByte52R { - DataByte52R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&mut self) -> DataByte55W { - DataByte55W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&mut self) -> DataByte54W { - DataByte54W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&mut self) -> DataByte53W { - DataByte53W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&mut self) -> DataByte52W { - DataByte52W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord13Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word13::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word13::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD13 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word14.rs deleted file mode 100644 index 4dc6e8291..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte59R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte58R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte57R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte56R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&self) -> DataByte59R { - DataByte59R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&self) -> DataByte58R { - DataByte58R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&self) -> DataByte57R { - DataByte57R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&self) -> DataByte56R { - DataByte56R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&mut self) -> DataByte59W { - DataByte59W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&mut self) -> DataByte58W { - DataByte58W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&mut self) -> DataByte57W { - DataByte57W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&mut self) -> DataByte56W { - DataByte56W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord14Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word14::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word14::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD14 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word15.rs deleted file mode 100644 index a7a638d88..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte63R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte62R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte61R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte60R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&self) -> DataByte63R { - DataByte63R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&self) -> DataByte62R { - DataByte62R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&self) -> DataByte61R { - DataByte61R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&self) -> DataByte60R { - DataByte60R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&mut self) -> DataByte63W { - DataByte63W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&mut self) -> DataByte62W { - DataByte62W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&mut self) -> DataByte61W { - DataByte61W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&mut self) -> DataByte60W { - DataByte60W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord15Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word15::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word15::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD15 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word2.rs deleted file mode 100644 index bd3a55625..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord2Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word2::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word2::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD2 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word3.rs deleted file mode 100644 index 052320ee6..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord3Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word3::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word3::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD3 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word4.rs deleted file mode 100644 index 15c0ef307..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord4Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word4::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word4::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD4 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word5.rs deleted file mode 100644 index c14450dee..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord5Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word5::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word5::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD5 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word6.rs deleted file mode 100644 index 8372f9a6a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord6Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word6::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word6::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD6 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word7.rs deleted file mode 100644 index d4d516f6f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord7Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word7::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word7::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD7 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word8.rs deleted file mode 100644 index 60cf48c9f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word8.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD8` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD8` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte35R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte34R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte33R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte32R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&self) -> DataByte35R { - DataByte35R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&self) -> DataByte34R { - DataByte34R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&self) -> DataByte33R { - DataByte33R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&self) -> DataByte32R { - DataByte32R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&mut self) -> DataByte35W { - DataByte35W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&mut self) -> DataByte34W { - DataByte34W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&mut self) -> DataByte33W { - DataByte33W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&mut self) -> DataByte32W { - DataByte32W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord8Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word8::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word8::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD8 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word9.rs deleted file mode 100644 index 64bc4e92e..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb1_64b_word9.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_64B_WORD9` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_64B_WORD9` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte39R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte38R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte37R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte36R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&self) -> DataByte39R { - DataByte39R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&self) -> DataByte38R { - DataByte38R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&self) -> DataByte37R { - DataByte37R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&self) -> DataByte36R { - DataByte36R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&mut self) -> DataByte39W { - DataByte39W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&mut self) -> DataByte38W { - DataByte38W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&mut self) -> DataByte37W { - DataByte37W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&mut self) -> DataByte36W { - DataByte36W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb1_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb1_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb1_64bWord9Spec; -impl crate::RegisterSpec for Mb64bGroupMb1_64bWord9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb1_64b_word9::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb1_64bWord9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb1_64b_word9::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb1_64bWord9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_64B_WORD9 to value 0"] -impl crate::Resettable for Mb64bGroupMb1_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_cs.rs deleted file mode 100644 index 7a6d6a66a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB2_64B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bCsSpec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_cs::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_cs::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_CS to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_id.rs deleted file mode 100644 index 1b5fe0b7b..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB2_64B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bIdSpec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_id::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_id::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_ID to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word0.rs deleted file mode 100644 index 2db921e6e..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord0Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word0::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word0::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD0 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word1.rs deleted file mode 100644 index 57d77091d..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord1Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word1::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word1::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD1 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word10.rs deleted file mode 100644 index 724b649e0..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte43R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte42R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte41R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte40R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&self) -> DataByte43R { - DataByte43R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&self) -> DataByte42R { - DataByte42R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&self) -> DataByte41R { - DataByte41R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&self) -> DataByte40R { - DataByte40R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&mut self) -> DataByte43W { - DataByte43W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&mut self) -> DataByte42W { - DataByte42W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&mut self) -> DataByte41W { - DataByte41W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&mut self) -> DataByte40W { - DataByte40W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord10Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word10::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word10::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD10 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word11.rs deleted file mode 100644 index d9976e613..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte47R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte46R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte45R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte44R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&self) -> DataByte47R { - DataByte47R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&self) -> DataByte46R { - DataByte46R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&self) -> DataByte45R { - DataByte45R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&self) -> DataByte44R { - DataByte44R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&mut self) -> DataByte47W { - DataByte47W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&mut self) -> DataByte46W { - DataByte46W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&mut self) -> DataByte45W { - DataByte45W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&mut self) -> DataByte44W { - DataByte44W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord11Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word11::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word11::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD11 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word12.rs deleted file mode 100644 index 2c1ecaeab..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte51R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte50R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte49R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte48R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&self) -> DataByte51R { - DataByte51R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&self) -> DataByte50R { - DataByte50R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&self) -> DataByte49R { - DataByte49R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&self) -> DataByte48R { - DataByte48R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&mut self) -> DataByte51W { - DataByte51W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&mut self) -> DataByte50W { - DataByte50W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&mut self) -> DataByte49W { - DataByte49W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&mut self) -> DataByte48W { - DataByte48W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord12Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word12::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word12::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD12 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word13.rs deleted file mode 100644 index 47d63fa30..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte55R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte54R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte53R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte52R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&self) -> DataByte55R { - DataByte55R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&self) -> DataByte54R { - DataByte54R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&self) -> DataByte53R { - DataByte53R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&self) -> DataByte52R { - DataByte52R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&mut self) -> DataByte55W { - DataByte55W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&mut self) -> DataByte54W { - DataByte54W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&mut self) -> DataByte53W { - DataByte53W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&mut self) -> DataByte52W { - DataByte52W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord13Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word13::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word13::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD13 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word14.rs deleted file mode 100644 index 328f7460f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte59R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte58R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte57R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte56R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&self) -> DataByte59R { - DataByte59R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&self) -> DataByte58R { - DataByte58R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&self) -> DataByte57R { - DataByte57R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&self) -> DataByte56R { - DataByte56R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&mut self) -> DataByte59W { - DataByte59W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&mut self) -> DataByte58W { - DataByte58W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&mut self) -> DataByte57W { - DataByte57W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&mut self) -> DataByte56W { - DataByte56W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord14Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word14::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word14::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD14 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word15.rs deleted file mode 100644 index bea90d785..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte63R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte62R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte61R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte60R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&self) -> DataByte63R { - DataByte63R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&self) -> DataByte62R { - DataByte62R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&self) -> DataByte61R { - DataByte61R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&self) -> DataByte60R { - DataByte60R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&mut self) -> DataByte63W { - DataByte63W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&mut self) -> DataByte62W { - DataByte62W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&mut self) -> DataByte61W { - DataByte61W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&mut self) -> DataByte60W { - DataByte60W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord15Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word15::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word15::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD15 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word2.rs deleted file mode 100644 index 41e25e7dd..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord2Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word2::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word2::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD2 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word3.rs deleted file mode 100644 index bc8354c3c..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord3Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word3::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word3::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD3 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word4.rs deleted file mode 100644 index e0f91aa67..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord4Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word4::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word4::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD4 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word5.rs deleted file mode 100644 index 832d989cf..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord5Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word5::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word5::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD5 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word6.rs deleted file mode 100644 index c93aa6cba..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord6Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word6::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word6::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD6 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word7.rs deleted file mode 100644 index f57ea8d3f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord7Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word7::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word7::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD7 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word8.rs deleted file mode 100644 index f68b4feea..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word8.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD8` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD8` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte35R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte34R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte33R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte32R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&self) -> DataByte35R { - DataByte35R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&self) -> DataByte34R { - DataByte34R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&self) -> DataByte33R { - DataByte33R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&self) -> DataByte32R { - DataByte32R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&mut self) -> DataByte35W { - DataByte35W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&mut self) -> DataByte34W { - DataByte34W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&mut self) -> DataByte33W { - DataByte33W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&mut self) -> DataByte32W { - DataByte32W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord8Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word8::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word8::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD8 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word9.rs deleted file mode 100644 index b7f3dab95..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb2_64b_word9.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_64B_WORD9` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_64B_WORD9` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte39R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte38R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte37R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte36R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&self) -> DataByte39R { - DataByte39R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&self) -> DataByte38R { - DataByte38R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&self) -> DataByte37R { - DataByte37R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&self) -> DataByte36R { - DataByte36R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&mut self) -> DataByte39W { - DataByte39W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&mut self) -> DataByte38W { - DataByte38W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&mut self) -> DataByte37W { - DataByte37W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&mut self) -> DataByte36W { - DataByte36W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb2_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb2_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb2_64bWord9Spec; -impl crate::RegisterSpec for Mb64bGroupMb2_64bWord9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb2_64b_word9::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb2_64bWord9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb2_64b_word9::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb2_64bWord9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_64B_WORD9 to value 0"] -impl crate::Resettable for Mb64bGroupMb2_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_cs.rs deleted file mode 100644 index 1cd000c8f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB3_64B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bCsSpec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_cs::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_cs::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_CS to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_id.rs deleted file mode 100644 index 58301678e..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB3_64B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bIdSpec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_id::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_id::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_ID to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word0.rs deleted file mode 100644 index 5299186a3..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord0Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word0::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word0::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD0 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word1.rs deleted file mode 100644 index 1359f2f45..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord1Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word1::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word1::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD1 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word10.rs deleted file mode 100644 index 254589653..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte43R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte42R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte41R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte40R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&self) -> DataByte43R { - DataByte43R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&self) -> DataByte42R { - DataByte42R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&self) -> DataByte41R { - DataByte41R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&self) -> DataByte40R { - DataByte40R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&mut self) -> DataByte43W { - DataByte43W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&mut self) -> DataByte42W { - DataByte42W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&mut self) -> DataByte41W { - DataByte41W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&mut self) -> DataByte40W { - DataByte40W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord10Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word10::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word10::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD10 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word11.rs deleted file mode 100644 index 3a7880f5e..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte47R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte46R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte45R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte44R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&self) -> DataByte47R { - DataByte47R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&self) -> DataByte46R { - DataByte46R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&self) -> DataByte45R { - DataByte45R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&self) -> DataByte44R { - DataByte44R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&mut self) -> DataByte47W { - DataByte47W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&mut self) -> DataByte46W { - DataByte46W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&mut self) -> DataByte45W { - DataByte45W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&mut self) -> DataByte44W { - DataByte44W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord11Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word11::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word11::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD11 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word12.rs deleted file mode 100644 index a7f80eb7a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte51R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte50R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte49R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte48R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&self) -> DataByte51R { - DataByte51R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&self) -> DataByte50R { - DataByte50R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&self) -> DataByte49R { - DataByte49R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&self) -> DataByte48R { - DataByte48R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&mut self) -> DataByte51W { - DataByte51W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&mut self) -> DataByte50W { - DataByte50W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&mut self) -> DataByte49W { - DataByte49W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&mut self) -> DataByte48W { - DataByte48W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord12Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word12::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word12::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD12 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word13.rs deleted file mode 100644 index e64bfd83c..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte55R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte54R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte53R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte52R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&self) -> DataByte55R { - DataByte55R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&self) -> DataByte54R { - DataByte54R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&self) -> DataByte53R { - DataByte53R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&self) -> DataByte52R { - DataByte52R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&mut self) -> DataByte55W { - DataByte55W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&mut self) -> DataByte54W { - DataByte54W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&mut self) -> DataByte53W { - DataByte53W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&mut self) -> DataByte52W { - DataByte52W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord13Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word13::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word13::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD13 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word14.rs deleted file mode 100644 index 5fb44aaa7..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte59R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte58R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte57R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte56R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&self) -> DataByte59R { - DataByte59R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&self) -> DataByte58R { - DataByte58R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&self) -> DataByte57R { - DataByte57R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&self) -> DataByte56R { - DataByte56R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&mut self) -> DataByte59W { - DataByte59W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&mut self) -> DataByte58W { - DataByte58W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&mut self) -> DataByte57W { - DataByte57W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&mut self) -> DataByte56W { - DataByte56W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord14Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word14::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word14::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD14 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word15.rs deleted file mode 100644 index 1b763ce55..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte63R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte62R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte61R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte60R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&self) -> DataByte63R { - DataByte63R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&self) -> DataByte62R { - DataByte62R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&self) -> DataByte61R { - DataByte61R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&self) -> DataByte60R { - DataByte60R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&mut self) -> DataByte63W { - DataByte63W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&mut self) -> DataByte62W { - DataByte62W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&mut self) -> DataByte61W { - DataByte61W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&mut self) -> DataByte60W { - DataByte60W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord15Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word15::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word15::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD15 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word2.rs deleted file mode 100644 index 8b389288f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord2Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word2::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word2::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD2 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word3.rs deleted file mode 100644 index e09997021..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord3Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word3::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word3::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD3 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word4.rs deleted file mode 100644 index 257f1d0be..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord4Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word4::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word4::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD4 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word5.rs deleted file mode 100644 index 203f3b504..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord5Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word5::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word5::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD5 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word6.rs deleted file mode 100644 index 49c0f9025..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord6Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word6::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word6::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD6 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word7.rs deleted file mode 100644 index 1b5bde3ee..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord7Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word7::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word7::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD7 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word8.rs deleted file mode 100644 index b1e7b64fb..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word8.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD8` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD8` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte35R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte34R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte33R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte32R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&self) -> DataByte35R { - DataByte35R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&self) -> DataByte34R { - DataByte34R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&self) -> DataByte33R { - DataByte33R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&self) -> DataByte32R { - DataByte32R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&mut self) -> DataByte35W { - DataByte35W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&mut self) -> DataByte34W { - DataByte34W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&mut self) -> DataByte33W { - DataByte33W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&mut self) -> DataByte32W { - DataByte32W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord8Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word8::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word8::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD8 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word9.rs deleted file mode 100644 index b42b9f577..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb3_64b_word9.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_64B_WORD9` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_64B_WORD9` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte39R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte38R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte37R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte36R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&self) -> DataByte39R { - DataByte39R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&self) -> DataByte38R { - DataByte38R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&self) -> DataByte37R { - DataByte37R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&self) -> DataByte36R { - DataByte36R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&mut self) -> DataByte39W { - DataByte39W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&mut self) -> DataByte38W { - DataByte38W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&mut self) -> DataByte37W { - DataByte37W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&mut self) -> DataByte36W { - DataByte36W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb3_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb3_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb3_64bWord9Spec; -impl crate::RegisterSpec for Mb64bGroupMb3_64bWord9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb3_64b_word9::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb3_64bWord9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb3_64b_word9::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb3_64bWord9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_64B_WORD9 to value 0"] -impl crate::Resettable for Mb64bGroupMb3_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_cs.rs deleted file mode 100644 index 9067b5e59..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB4_64B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bCsSpec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_cs::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_cs::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_CS to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_id.rs deleted file mode 100644 index 2394e3ff5..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB4_64B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bIdSpec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_id::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_id::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_ID to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word0.rs deleted file mode 100644 index 421d1e203..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord0Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word0::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word0::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD0 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word1.rs deleted file mode 100644 index 433e30849..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord1Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word1::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word1::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD1 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word10.rs deleted file mode 100644 index f816ece1c..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte43R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte42R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte41R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte40R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&self) -> DataByte43R { - DataByte43R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&self) -> DataByte42R { - DataByte42R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&self) -> DataByte41R { - DataByte41R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&self) -> DataByte40R { - DataByte40R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&mut self) -> DataByte43W { - DataByte43W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&mut self) -> DataByte42W { - DataByte42W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&mut self) -> DataByte41W { - DataByte41W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&mut self) -> DataByte40W { - DataByte40W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord10Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word10::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word10::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD10 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word11.rs deleted file mode 100644 index 1aea88db4..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte47R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte46R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte45R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte44R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&self) -> DataByte47R { - DataByte47R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&self) -> DataByte46R { - DataByte46R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&self) -> DataByte45R { - DataByte45R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&self) -> DataByte44R { - DataByte44R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&mut self) -> DataByte47W { - DataByte47W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&mut self) -> DataByte46W { - DataByte46W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&mut self) -> DataByte45W { - DataByte45W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&mut self) -> DataByte44W { - DataByte44W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord11Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word11::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word11::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD11 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word12.rs deleted file mode 100644 index c74731dbc..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte51R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte50R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte49R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte48R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&self) -> DataByte51R { - DataByte51R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&self) -> DataByte50R { - DataByte50R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&self) -> DataByte49R { - DataByte49R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&self) -> DataByte48R { - DataByte48R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&mut self) -> DataByte51W { - DataByte51W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&mut self) -> DataByte50W { - DataByte50W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&mut self) -> DataByte49W { - DataByte49W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&mut self) -> DataByte48W { - DataByte48W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord12Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word12::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word12::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD12 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word13.rs deleted file mode 100644 index e6dcd9554..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte55R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte54R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte53R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte52R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&self) -> DataByte55R { - DataByte55R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&self) -> DataByte54R { - DataByte54R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&self) -> DataByte53R { - DataByte53R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&self) -> DataByte52R { - DataByte52R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&mut self) -> DataByte55W { - DataByte55W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&mut self) -> DataByte54W { - DataByte54W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&mut self) -> DataByte53W { - DataByte53W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&mut self) -> DataByte52W { - DataByte52W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord13Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word13::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word13::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD13 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word14.rs deleted file mode 100644 index fba5e83d6..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte59R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte58R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte57R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte56R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&self) -> DataByte59R { - DataByte59R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&self) -> DataByte58R { - DataByte58R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&self) -> DataByte57R { - DataByte57R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&self) -> DataByte56R { - DataByte56R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&mut self) -> DataByte59W { - DataByte59W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&mut self) -> DataByte58W { - DataByte58W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&mut self) -> DataByte57W { - DataByte57W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&mut self) -> DataByte56W { - DataByte56W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord14Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word14::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word14::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD14 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word15.rs deleted file mode 100644 index 3d08b2ba8..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte63R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte62R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte61R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte60R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&self) -> DataByte63R { - DataByte63R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&self) -> DataByte62R { - DataByte62R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&self) -> DataByte61R { - DataByte61R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&self) -> DataByte60R { - DataByte60R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&mut self) -> DataByte63W { - DataByte63W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&mut self) -> DataByte62W { - DataByte62W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&mut self) -> DataByte61W { - DataByte61W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&mut self) -> DataByte60W { - DataByte60W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord15Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word15::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word15::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD15 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word2.rs deleted file mode 100644 index b31317180..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord2Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word2::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word2::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD2 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word3.rs deleted file mode 100644 index 1dc351d86..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord3Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word3::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word3::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD3 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word4.rs deleted file mode 100644 index 3ad5f0fe8..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord4Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word4::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word4::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD4 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word5.rs deleted file mode 100644 index 26877c4c3..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord5Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word5::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word5::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD5 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word6.rs deleted file mode 100644 index a6783d6bf..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord6Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word6::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word6::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD6 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word7.rs deleted file mode 100644 index 4a7f71501..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord7Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word7::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word7::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD7 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word8.rs deleted file mode 100644 index 2893e4772..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word8.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD8` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD8` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte35R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte34R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte33R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte32R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&self) -> DataByte35R { - DataByte35R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&self) -> DataByte34R { - DataByte34R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&self) -> DataByte33R { - DataByte33R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&self) -> DataByte32R { - DataByte32R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&mut self) -> DataByte35W { - DataByte35W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&mut self) -> DataByte34W { - DataByte34W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&mut self) -> DataByte33W { - DataByte33W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&mut self) -> DataByte32W { - DataByte32W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord8Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word8::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word8::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD8 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word9.rs deleted file mode 100644 index 1acab9847..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb4_64b_word9.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_64B_WORD9` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_64B_WORD9` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte39R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte38R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte37R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte36R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&self) -> DataByte39R { - DataByte39R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&self) -> DataByte38R { - DataByte38R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&self) -> DataByte37R { - DataByte37R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&self) -> DataByte36R { - DataByte36R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&mut self) -> DataByte39W { - DataByte39W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&mut self) -> DataByte38W { - DataByte38W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&mut self) -> DataByte37W { - DataByte37W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&mut self) -> DataByte36W { - DataByte36W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb4_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb4_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb4_64bWord9Spec; -impl crate::RegisterSpec for Mb64bGroupMb4_64bWord9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb4_64b_word9::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb4_64bWord9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb4_64b_word9::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb4_64bWord9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_64B_WORD9 to value 0"] -impl crate::Resettable for Mb64bGroupMb4_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_cs.rs deleted file mode 100644 index ddad14de2..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB5_64B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bCsSpec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_cs::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_cs::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_CS to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_id.rs deleted file mode 100644 index 587fba280..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB5_64B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bIdSpec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_id::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_id::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_ID to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word0.rs deleted file mode 100644 index a33487a2f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord0Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word0::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word0::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD0 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word1.rs deleted file mode 100644 index af557ac31..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord1Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word1::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word1::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD1 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word10.rs deleted file mode 100644 index 2dbec434c..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte43R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte42R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte41R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte40R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&self) -> DataByte43R { - DataByte43R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&self) -> DataByte42R { - DataByte42R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&self) -> DataByte41R { - DataByte41R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&self) -> DataByte40R { - DataByte40R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&mut self) -> DataByte43W { - DataByte43W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&mut self) -> DataByte42W { - DataByte42W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&mut self) -> DataByte41W { - DataByte41W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&mut self) -> DataByte40W { - DataByte40W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord10Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word10::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word10::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD10 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word11.rs deleted file mode 100644 index 00217fd09..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte47R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte46R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte45R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte44R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&self) -> DataByte47R { - DataByte47R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&self) -> DataByte46R { - DataByte46R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&self) -> DataByte45R { - DataByte45R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&self) -> DataByte44R { - DataByte44R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&mut self) -> DataByte47W { - DataByte47W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&mut self) -> DataByte46W { - DataByte46W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&mut self) -> DataByte45W { - DataByte45W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&mut self) -> DataByte44W { - DataByte44W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord11Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word11::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word11::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD11 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word12.rs deleted file mode 100644 index e04dac374..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte51R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte50R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte49R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte48R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&self) -> DataByte51R { - DataByte51R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&self) -> DataByte50R { - DataByte50R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&self) -> DataByte49R { - DataByte49R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&self) -> DataByte48R { - DataByte48R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&mut self) -> DataByte51W { - DataByte51W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&mut self) -> DataByte50W { - DataByte50W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&mut self) -> DataByte49W { - DataByte49W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&mut self) -> DataByte48W { - DataByte48W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord12Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word12::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word12::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD12 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word13.rs deleted file mode 100644 index 55b20069a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte55R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte54R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte53R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte52R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&self) -> DataByte55R { - DataByte55R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&self) -> DataByte54R { - DataByte54R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&self) -> DataByte53R { - DataByte53R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&self) -> DataByte52R { - DataByte52R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&mut self) -> DataByte55W { - DataByte55W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&mut self) -> DataByte54W { - DataByte54W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&mut self) -> DataByte53W { - DataByte53W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&mut self) -> DataByte52W { - DataByte52W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord13Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word13::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word13::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD13 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word14.rs deleted file mode 100644 index 2d7b49d63..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte59R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte58R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte57R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte56R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&self) -> DataByte59R { - DataByte59R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&self) -> DataByte58R { - DataByte58R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&self) -> DataByte57R { - DataByte57R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&self) -> DataByte56R { - DataByte56R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&mut self) -> DataByte59W { - DataByte59W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&mut self) -> DataByte58W { - DataByte58W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&mut self) -> DataByte57W { - DataByte57W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&mut self) -> DataByte56W { - DataByte56W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord14Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word14::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word14::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD14 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word15.rs deleted file mode 100644 index 3f3c2840f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte63R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte62R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte61R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte60R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&self) -> DataByte63R { - DataByte63R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&self) -> DataByte62R { - DataByte62R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&self) -> DataByte61R { - DataByte61R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&self) -> DataByte60R { - DataByte60R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&mut self) -> DataByte63W { - DataByte63W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&mut self) -> DataByte62W { - DataByte62W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&mut self) -> DataByte61W { - DataByte61W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&mut self) -> DataByte60W { - DataByte60W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord15Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word15::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word15::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD15 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word2.rs deleted file mode 100644 index 20868cd42..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord2Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word2::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word2::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD2 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word3.rs deleted file mode 100644 index 251487533..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord3Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word3::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word3::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD3 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word4.rs deleted file mode 100644 index 7443e932a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord4Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word4::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word4::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD4 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word5.rs deleted file mode 100644 index d3e3243f9..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord5Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word5::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word5::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD5 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word6.rs deleted file mode 100644 index c53968433..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord6Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word6::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word6::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD6 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word7.rs deleted file mode 100644 index 6ef3bc4a9..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord7Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word7::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word7::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD7 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word8.rs deleted file mode 100644 index ccae23acb..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word8.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD8` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD8` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte35R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte34R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte33R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte32R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&self) -> DataByte35R { - DataByte35R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&self) -> DataByte34R { - DataByte34R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&self) -> DataByte33R { - DataByte33R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&self) -> DataByte32R { - DataByte32R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&mut self) -> DataByte35W { - DataByte35W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&mut self) -> DataByte34W { - DataByte34W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&mut self) -> DataByte33W { - DataByte33W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&mut self) -> DataByte32W { - DataByte32W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord8Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word8::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word8::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD8 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word9.rs deleted file mode 100644 index e0c740a42..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb5_64b_word9.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_64B_WORD9` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_64B_WORD9` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte39R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte38R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte37R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte36R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&self) -> DataByte39R { - DataByte39R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&self) -> DataByte38R { - DataByte38R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&self) -> DataByte37R { - DataByte37R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&self) -> DataByte36R { - DataByte36R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&mut self) -> DataByte39W { - DataByte39W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&mut self) -> DataByte38W { - DataByte38W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&mut self) -> DataByte37W { - DataByte37W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&mut self) -> DataByte36W { - DataByte36W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb5_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb5_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb5_64bWord9Spec; -impl crate::RegisterSpec for Mb64bGroupMb5_64bWord9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb5_64b_word9::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb5_64bWord9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb5_64b_word9::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb5_64bWord9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_64B_WORD9 to value 0"] -impl crate::Resettable for Mb64bGroupMb5_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_cs.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_cs.rs deleted file mode 100644 index ebe364c60..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB6_64B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bCsSpec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_cs::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_cs::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_CS to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_id.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_id.rs deleted file mode 100644 index 7ab4b38cf..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB6_64B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bIdSpec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_id::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_id::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_ID to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word0.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word0.rs deleted file mode 100644 index bafda4748..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord0Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word0::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word0::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD0 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word1.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word1.rs deleted file mode 100644 index 9d8bbc6a7..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord1Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word1::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word1::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD1 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word10.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word10.rs deleted file mode 100644 index 926ae993f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_43` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte43R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_43` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte43W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_42` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte42R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_42` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte42W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_41` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte41R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_41` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte41W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_40` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte40R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_40` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte40W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&self) -> DataByte43R { - DataByte43R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&self) -> DataByte42R { - DataByte42R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&self) -> DataByte41R { - DataByte41R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&self) -> DataByte40R { - DataByte40R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_43(&mut self) -> DataByte43W { - DataByte43W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_42(&mut self) -> DataByte42W { - DataByte42W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_41(&mut self) -> DataByte41W { - DataByte41W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_40(&mut self) -> DataByte40W { - DataByte40W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord10Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word10::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word10::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD10 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word11.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word11.rs deleted file mode 100644 index b51a9b41b..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_47` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte47R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_47` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte47W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_46` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte46R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_46` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte46W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_45` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte45R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_45` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte45W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_44` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte44R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_44` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte44W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&self) -> DataByte47R { - DataByte47R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&self) -> DataByte46R { - DataByte46R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&self) -> DataByte45R { - DataByte45R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&self) -> DataByte44R { - DataByte44R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_47(&mut self) -> DataByte47W { - DataByte47W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_46(&mut self) -> DataByte46W { - DataByte46W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_45(&mut self) -> DataByte45W { - DataByte45W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_44(&mut self) -> DataByte44W { - DataByte44W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord11Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word11::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word11::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD11 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word12.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word12.rs deleted file mode 100644 index 24630ed6a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_51` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte51R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_51` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte51W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_50` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte50R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_50` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte50W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_49` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte49R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_49` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte49W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_48` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte48R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_48` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte48W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&self) -> DataByte51R { - DataByte51R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&self) -> DataByte50R { - DataByte50R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&self) -> DataByte49R { - DataByte49R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&self) -> DataByte48R { - DataByte48R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_51(&mut self) -> DataByte51W { - DataByte51W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_50(&mut self) -> DataByte50W { - DataByte50W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_49(&mut self) -> DataByte49W { - DataByte49W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_48(&mut self) -> DataByte48W { - DataByte48W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord12Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word12::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word12::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD12 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word13.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word13.rs deleted file mode 100644 index 6468e9eb8..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_55` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte55R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_55` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte55W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_54` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte54R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_54` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte54W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_53` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte53R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_53` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte53W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_52` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte52R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_52` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte52W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&self) -> DataByte55R { - DataByte55R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&self) -> DataByte54R { - DataByte54R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&self) -> DataByte53R { - DataByte53R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&self) -> DataByte52R { - DataByte52R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_55(&mut self) -> DataByte55W { - DataByte55W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_54(&mut self) -> DataByte54W { - DataByte54W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_53(&mut self) -> DataByte53W { - DataByte53W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_52(&mut self) -> DataByte52W { - DataByte52W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord13Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word13::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word13::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD13 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word14.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word14.rs deleted file mode 100644 index 99c593175..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_59` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte59R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_59` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte59W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_58` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte58R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_58` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte58W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_57` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte57R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_57` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte57W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_56` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte56R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_56` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte56W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&self) -> DataByte59R { - DataByte59R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&self) -> DataByte58R { - DataByte58R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&self) -> DataByte57R { - DataByte57R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&self) -> DataByte56R { - DataByte56R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_59(&mut self) -> DataByte59W { - DataByte59W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_58(&mut self) -> DataByte58W { - DataByte58W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_57(&mut self) -> DataByte57W { - DataByte57W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_56(&mut self) -> DataByte56W { - DataByte56W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord14Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word14::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word14::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD14 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word15.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word15.rs deleted file mode 100644 index 6afd5c30f..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_63` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte63R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_63` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte63W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_62` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte62R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_62` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte62W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_61` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte61R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_61` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte61W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_60` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte60R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_60` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte60W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&self) -> DataByte63R { - DataByte63R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&self) -> DataByte62R { - DataByte62R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&self) -> DataByte61R { - DataByte61R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&self) -> DataByte60R { - DataByte60R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_63(&mut self) -> DataByte63W { - DataByte63W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_62(&mut self) -> DataByte62W { - DataByte62W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_61(&mut self) -> DataByte61W { - DataByte61W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_60(&mut self) -> DataByte60W { - DataByte60W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord15Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word15::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word15::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD15 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word2.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word2.rs deleted file mode 100644 index 139fe50f4..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD2` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD2` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_11` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte11R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_11` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte11W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_10` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte10R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_10` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_9` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte9R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_9` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte9W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_8` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte8R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_8` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&self) -> DataByte11R { - DataByte11R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&self) -> DataByte10R { - DataByte10R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&self) -> DataByte9R { - DataByte9R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&self) -> DataByte8R { - DataByte8R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_11(&mut self) -> DataByte11W { - DataByte11W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_10(&mut self) -> DataByte10W { - DataByte10W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_9(&mut self) -> DataByte9W { - DataByte9W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_8(&mut self) -> DataByte8W { - DataByte8W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord2Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word2::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word2::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD2 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord2Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word3.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word3.rs deleted file mode 100644 index e19ed78d7..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word3.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD3` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD3` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_15` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte15R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_15` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte15W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_14` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte14R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_14` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte14W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_13` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte13R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_13` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte13W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_12` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte12R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_12` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte12W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&self) -> DataByte15R { - DataByte15R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&self) -> DataByte14R { - DataByte14R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&self) -> DataByte13R { - DataByte13R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&self) -> DataByte12R { - DataByte12R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_15(&mut self) -> DataByte15W { - DataByte15W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_14(&mut self) -> DataByte14W { - DataByte14W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_13(&mut self) -> DataByte13W { - DataByte13W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_12(&mut self) -> DataByte12W { - DataByte12W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord3Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word3::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word3::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD3 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord3Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word4.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word4.rs deleted file mode 100644 index e2675e2be..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word4.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD4` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD4` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_19` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte19R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_19` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte19W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_18` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte18R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_18` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte18W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_17` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte17R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_17` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte17W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_16` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte16R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_16` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte16W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&self) -> DataByte19R { - DataByte19R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&self) -> DataByte18R { - DataByte18R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&self) -> DataByte17R { - DataByte17R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&self) -> DataByte16R { - DataByte16R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_19(&mut self) -> DataByte19W { - DataByte19W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_18(&mut self) -> DataByte18W { - DataByte18W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_17(&mut self) -> DataByte17W { - DataByte17W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_16(&mut self) -> DataByte16W { - DataByte16W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord4Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word4::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word4::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD4 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord4Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word5.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word5.rs deleted file mode 100644 index d82598368..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word5.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD5` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD5` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_23` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte23R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_23` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte23W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_22` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte22R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_22` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte22W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_21` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte21R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_21` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte21W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_20` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte20R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_20` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte20W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&self) -> DataByte23R { - DataByte23R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&self) -> DataByte22R { - DataByte22R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&self) -> DataByte21R { - DataByte21R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&self) -> DataByte20R { - DataByte20R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_23(&mut self) -> DataByte23W { - DataByte23W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_22(&mut self) -> DataByte22W { - DataByte22W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_21(&mut self) -> DataByte21W { - DataByte21W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_20(&mut self) -> DataByte20W { - DataByte20W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord5Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word5::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word5::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD5 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord5Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word6.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word6.rs deleted file mode 100644 index 428012fe8..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word6.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD6` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD6` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_27` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte27R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_27` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte27W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_26` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte26R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_26` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte26W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_25` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte25R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_25` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte25W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_24` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte24R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_24` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte24W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&self) -> DataByte27R { - DataByte27R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&self) -> DataByte26R { - DataByte26R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&self) -> DataByte25R { - DataByte25R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&self) -> DataByte24R { - DataByte24R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_27(&mut self) -> DataByte27W { - DataByte27W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_26(&mut self) -> DataByte26W { - DataByte26W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_25(&mut self) -> DataByte25W { - DataByte25W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_24(&mut self) -> DataByte24W { - DataByte24W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord6Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word6::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word6::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD6 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord6Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word7.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word7.rs deleted file mode 100644 index 062ca1f11..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word7.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD7` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD7` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_31` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte31R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_31` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte31W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_30` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte30R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_30` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte30W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_29` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte29R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_29` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte29W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_28` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte28R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_28` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte28W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&self) -> DataByte31R { - DataByte31R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&self) -> DataByte30R { - DataByte30R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&self) -> DataByte29R { - DataByte29R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&self) -> DataByte28R { - DataByte28R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_31(&mut self) -> DataByte31W { - DataByte31W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_30(&mut self) -> DataByte30W { - DataByte30W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_29(&mut self) -> DataByte29W { - DataByte29W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_28(&mut self) -> DataByte28W { - DataByte28W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord7Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word7::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word7::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD7 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord7Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word8.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word8.rs deleted file mode 100644 index 82b461123..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word8.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD8` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD8` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_35` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte35R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_35` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte35W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_34` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte34R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_34` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte34W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_33` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte33R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_33` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte33W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_32` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte32R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_32` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte32W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&self) -> DataByte35R { - DataByte35R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&self) -> DataByte34R { - DataByte34R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&self) -> DataByte33R { - DataByte33R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&self) -> DataByte32R { - DataByte32R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_35(&mut self) -> DataByte35W { - DataByte35W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_34(&mut self) -> DataByte34W { - DataByte34W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_33(&mut self) -> DataByte33W { - DataByte33W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_32(&mut self) -> DataByte32W { - DataByte32W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord8Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word8::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word8::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD8 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord8Spec {} diff --git a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word9.rs b/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word9.rs deleted file mode 100644 index 98b72b62a..000000000 --- a/mcxa276-pac/src/can0/mb_64b_group_mb6_64b_word9.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_64B_WORD9` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_64B_WORD9` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_39` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte39R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_39` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte39W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_38` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte38R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_38` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte38W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_37` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte37R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_37` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte37W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_36` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte36R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_36` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte36W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&self) -> DataByte39R { - DataByte39R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&self) -> DataByte38R { - DataByte38R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&self) -> DataByte37R { - DataByte37R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&self) -> DataByte36R { - DataByte36R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_39(&mut self) -> DataByte39W { - DataByte39W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_38(&mut self) -> DataByte38W { - DataByte38W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_37(&mut self) -> DataByte37W { - DataByte37W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_36(&mut self) -> DataByte36W { - DataByte36W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_64B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_64b_group_mb6_64b_word9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_64b_group_mb6_64b_word9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb64bGroupMb6_64bWord9Spec; -impl crate::RegisterSpec for Mb64bGroupMb6_64bWord9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_64b_group_mb6_64b_word9::R`](R) reader structure"] -impl crate::Readable for Mb64bGroupMb6_64bWord9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_64b_group_mb6_64b_word9::W`](W) writer structure"] -impl crate::Writable for Mb64bGroupMb6_64bWord9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_64B_WORD9 to value 0"] -impl crate::Resettable for Mb64bGroupMb6_64bWord9Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_cs.rs deleted file mode 100644 index 64d91968d..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB0_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb0_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb0_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb0_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb0_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb0_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_id.rs deleted file mode 100644 index 831cd7ebe..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB0_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb0_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb0_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb0_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb0_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb0_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word0.rs deleted file mode 100644 index 91a7e70b5..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb0_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb0_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb0_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb0_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb0_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word1.rs deleted file mode 100644 index 64595986c..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb0_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB0_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB0_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb0_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb0_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb0_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb0_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb0_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb0_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb0_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb0_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB0_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb0_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_cs.rs deleted file mode 100644 index fabd51c24..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB10_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb10_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb10_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb10_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb10_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb10_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_id.rs deleted file mode 100644 index d540ed50e..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB10_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb10_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb10_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb10_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb10_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb10_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word0.rs deleted file mode 100644 index 07faacbd1..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb10_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb10_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb10_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb10_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb10_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word1.rs deleted file mode 100644 index df2a992fd..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb10_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB10_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB10_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb10_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb10_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb10_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb10_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb10_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb10_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb10_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb10_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB10_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb10_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_cs.rs deleted file mode 100644 index 1b8b3b2c2..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB11_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb11_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb11_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb11_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb11_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb11_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_id.rs deleted file mode 100644 index 2c497a5aa..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB11_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb11_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb11_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb11_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb11_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb11_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word0.rs deleted file mode 100644 index 9992eed11..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb11_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb11_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb11_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb11_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb11_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word1.rs deleted file mode 100644 index d141dbfe7..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb11_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB11_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB11_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb11_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb11_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb11_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb11_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb11_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb11_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb11_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb11_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB11_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb11_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_cs.rs deleted file mode 100644 index b262164a7..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB12_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb12_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb12_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb12_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb12_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb12_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_id.rs deleted file mode 100644 index 4997280e6..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB12_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb12_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb12_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb12_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb12_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb12_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word0.rs deleted file mode 100644 index 34e0535d8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB12_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb12_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb12_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb12_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb12_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb12_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word1.rs deleted file mode 100644 index 1a0788eb9..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb12_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB12_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB12_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb12_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb12_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb12_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb12_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb12_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb12_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb12_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb12_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB12_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb12_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_cs.rs deleted file mode 100644 index 6d1ddc6f4..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB13_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb13_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb13_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb13_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb13_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb13_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_id.rs deleted file mode 100644 index 63440ee65..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB13_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb13_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb13_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb13_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb13_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb13_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word0.rs deleted file mode 100644 index 80aca89a8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB13_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb13_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb13_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb13_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb13_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb13_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word1.rs deleted file mode 100644 index ba4a393b9..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb13_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB13_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB13_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb13_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb13_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb13_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb13_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb13_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb13_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb13_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb13_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB13_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb13_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_cs.rs deleted file mode 100644 index 18597af49..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB14_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb14_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb14_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb14_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb14_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb14_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_id.rs deleted file mode 100644 index 1870f7106..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB14_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb14_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb14_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb14_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb14_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb14_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word0.rs deleted file mode 100644 index 1c9bb7c55..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB14_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb14_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb14_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb14_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb14_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb14_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word1.rs deleted file mode 100644 index 81b888cb2..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb14_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB14_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB14_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb14_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb14_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb14_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb14_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb14_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb14_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb14_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb14_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB14_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb14_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_cs.rs deleted file mode 100644 index 2a2ce8530..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB15_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb15_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb15_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb15_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb15_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb15_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_id.rs deleted file mode 100644 index b4f8fec8a..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB15_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb15_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb15_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb15_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb15_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb15_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word0.rs deleted file mode 100644 index c327b6d19..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB15_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb15_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb15_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb15_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb15_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb15_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word1.rs deleted file mode 100644 index efc4f8606..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb15_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB15_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB15_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb15_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb15_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb15_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb15_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb15_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb15_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb15_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb15_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB15_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb15_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_cs.rs deleted file mode 100644 index 8a3fdfb5f..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB16_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb16_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb16_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb16_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb16_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb16_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_id.rs deleted file mode 100644 index 27e447ae0..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB16_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb16_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb16_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb16_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb16_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb16_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word0.rs deleted file mode 100644 index 7211d905f..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB16_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb16_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb16_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb16_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb16_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb16_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word1.rs deleted file mode 100644 index 8e8e99534..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb16_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB16_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB16_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb16_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb16_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb16_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb16_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb16_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb16_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb16_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb16_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB16_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb16_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_cs.rs deleted file mode 100644 index 513461780..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB17_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb17_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb17_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb17_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb17_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb17_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_id.rs deleted file mode 100644 index 48fdf7076..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB17_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb17_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb17_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb17_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb17_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb17_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word0.rs deleted file mode 100644 index d0284594f..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB17_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb17_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb17_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb17_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb17_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb17_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word1.rs deleted file mode 100644 index 523ab671e..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb17_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB17_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB17_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb17_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb17_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb17_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb17_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb17_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb17_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb17_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb17_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB17_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb17_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_cs.rs deleted file mode 100644 index 291706aa8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB18_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb18_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb18_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb18_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb18_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb18_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_id.rs deleted file mode 100644 index 9c17ec139..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB18_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb18_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb18_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb18_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb18_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb18_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word0.rs deleted file mode 100644 index 20e99a7b5..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB18_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb18_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb18_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb18_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb18_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb18_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word1.rs deleted file mode 100644 index 0aa8cde57..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb18_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB18_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB18_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb18_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb18_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb18_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb18_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb18_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb18_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb18_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb18_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB18_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb18_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_cs.rs deleted file mode 100644 index f8f0cb63d..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB19_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb19_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb19_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb19_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb19_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb19_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_id.rs deleted file mode 100644 index 6175f3bdf..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB19_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb19_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb19_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb19_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb19_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb19_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word0.rs deleted file mode 100644 index 9cbe96ecd..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB19_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb19_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb19_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb19_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb19_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb19_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word1.rs deleted file mode 100644 index e86c69de0..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb19_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB19_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB19_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb19_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb19_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb19_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb19_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb19_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb19_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb19_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb19_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB19_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb19_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_cs.rs deleted file mode 100644 index 195c7173c..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB1_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb1_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb1_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb1_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb1_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb1_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_id.rs deleted file mode 100644 index e8ad195cf..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB1_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb1_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb1_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb1_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb1_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb1_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word0.rs deleted file mode 100644 index a78bf2957..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb1_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb1_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb1_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb1_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb1_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word1.rs deleted file mode 100644 index 56caed8c9..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb1_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB1_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB1_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb1_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb1_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb1_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb1_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb1_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb1_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb1_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb1_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB1_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb1_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_cs.rs deleted file mode 100644 index 63339f97c..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB20_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb20_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb20_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb20_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb20_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb20_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_id.rs deleted file mode 100644 index 451fb759c..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB20_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb20_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb20_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb20_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb20_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb20_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word0.rs deleted file mode 100644 index b024fae73..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB20_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb20_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb20_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb20_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb20_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb20_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word1.rs deleted file mode 100644 index c6a355d52..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb20_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB20_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB20_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb20_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb20_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb20_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb20_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb20_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb20_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb20_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb20_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB20_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb20_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_cs.rs deleted file mode 100644 index 15edf45d2..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB21_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB21_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb21_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb21_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb21_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb21_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB21_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb21_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_id.rs deleted file mode 100644 index 6d6da8057..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB21_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB21_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb21_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb21_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb21_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb21_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB21_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb21_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word0.rs deleted file mode 100644 index 670dea523..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB21_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB21_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb21_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb21_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb21_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb21_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB21_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb21_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word1.rs deleted file mode 100644 index 7acf2755e..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb21_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB21_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB21_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 21 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb21_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb21_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb21_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb21_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb21_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb21_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb21_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb21_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB21_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb21_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_cs.rs deleted file mode 100644 index 79f5cb974..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB22_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB22_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb22_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb22_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb22_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb22_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB22_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb22_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_id.rs deleted file mode 100644 index f17b27ede..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB22_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB22_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb22_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb22_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb22_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb22_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB22_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb22_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word0.rs deleted file mode 100644 index 5ee011550..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB22_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB22_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb22_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb22_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb22_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb22_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB22_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb22_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word1.rs deleted file mode 100644 index 9b20b1ce5..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb22_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB22_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB22_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 22 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb22_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb22_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb22_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb22_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb22_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb22_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb22_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb22_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB22_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb22_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_cs.rs deleted file mode 100644 index f019a7d03..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB23_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB23_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb23_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb23_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb23_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb23_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB23_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb23_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_id.rs deleted file mode 100644 index 494eb7ea8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB23_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB23_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb23_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb23_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb23_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb23_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB23_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb23_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word0.rs deleted file mode 100644 index 324272bd0..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB23_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB23_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb23_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb23_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb23_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb23_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB23_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb23_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word1.rs deleted file mode 100644 index 99f81153a..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb23_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB23_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB23_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 23 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb23_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb23_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb23_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb23_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb23_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb23_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb23_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb23_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB23_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb23_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_cs.rs deleted file mode 100644 index 65445b5d8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB24_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB24_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb24_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb24_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb24_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb24_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB24_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb24_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_id.rs deleted file mode 100644 index 163558c45..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB24_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB24_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb24_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb24_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb24_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb24_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB24_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb24_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word0.rs deleted file mode 100644 index 904296003..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB24_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB24_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb24_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb24_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb24_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb24_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB24_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb24_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word1.rs deleted file mode 100644 index c22fed693..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb24_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB24_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB24_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 24 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb24_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb24_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb24_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb24_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb24_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb24_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb24_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb24_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB24_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb24_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_cs.rs deleted file mode 100644 index 24ef381f5..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB25_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB25_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb25_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb25_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb25_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb25_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB25_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb25_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_id.rs deleted file mode 100644 index 959365154..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB25_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB25_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb25_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb25_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb25_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb25_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB25_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb25_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word0.rs deleted file mode 100644 index 1b8041311..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB25_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB25_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb25_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb25_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb25_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb25_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB25_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb25_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word1.rs deleted file mode 100644 index 5bddfc97a..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb25_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB25_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB25_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 25 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb25_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb25_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb25_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb25_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb25_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb25_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb25_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb25_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB25_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb25_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_cs.rs deleted file mode 100644 index 7c14cc278..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB26_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB26_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb26_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb26_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb26_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb26_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB26_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb26_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_id.rs deleted file mode 100644 index 94fbd33d7..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB26_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB26_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb26_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb26_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb26_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb26_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB26_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb26_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word0.rs deleted file mode 100644 index 7f9688b70..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB26_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB26_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb26_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb26_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb26_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb26_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB26_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb26_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word1.rs deleted file mode 100644 index 0253e3d35..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb26_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB26_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB26_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 26 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb26_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb26_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb26_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb26_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb26_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb26_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb26_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb26_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB26_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb26_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_cs.rs deleted file mode 100644 index a461fd6f6..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB27_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB27_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb27_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb27_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb27_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb27_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB27_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb27_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs deleted file mode 100644 index ba3fe6be8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB27_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB27_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb27_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb27_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb27_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb27_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB27_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb27_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs deleted file mode 100644 index 0f94dacc8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB27_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB27_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb27_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb27_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb27_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb27_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB27_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb27_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs deleted file mode 100644 index 2061574a5..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb27_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB27_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB27_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 27 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb27_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb27_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb27_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb27_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb27_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb27_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb27_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb27_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB27_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb27_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs deleted file mode 100644 index 01c3df95c..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB28_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB28_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb28_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb28_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb28_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb28_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB28_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb28_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs deleted file mode 100644 index 9151a84e5..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB28_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB28_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb28_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb28_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb28_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb28_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB28_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb28_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs deleted file mode 100644 index 8add84844..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB28_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB28_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb28_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb28_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb28_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb28_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB28_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb28_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs deleted file mode 100644 index cb4312410..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb28_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB28_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB28_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 28 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb28_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb28_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb28_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb28_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb28_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb28_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb28_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb28_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB28_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb28_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs deleted file mode 100644 index 3a6aef983..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB29_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB29_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb29_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb29_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb29_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb29_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB29_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb29_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs deleted file mode 100644 index 0347e3aa0..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB29_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB29_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb29_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb29_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb29_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb29_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB29_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb29_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs deleted file mode 100644 index bfb171199..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB29_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB29_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb29_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb29_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb29_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb29_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB29_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb29_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs deleted file mode 100644 index 7ec594406..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb29_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB29_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB29_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 29 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb29_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb29_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb29_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb29_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb29_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb29_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb29_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb29_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB29_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb29_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs deleted file mode 100644 index 3837df2be..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB2_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb2_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb2_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb2_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb2_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb2_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs deleted file mode 100644 index a2bba19e6..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB2_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb2_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb2_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb2_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb2_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb2_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs deleted file mode 100644 index 2305ed6a6..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb2_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb2_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb2_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb2_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb2_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs deleted file mode 100644 index fe0c62124..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb2_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB2_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB2_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb2_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb2_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb2_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb2_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb2_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb2_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb2_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb2_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB2_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb2_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs deleted file mode 100644 index 25c367b8f..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB30_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB30_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb30_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb30_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb30_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb30_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB30_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb30_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs deleted file mode 100644 index 5f9647ab3..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB30_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB30_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb30_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb30_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb30_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb30_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB30_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb30_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word0.rs deleted file mode 100644 index 92b97c8e1..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB30_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB30_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb30_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb30_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb30_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb30_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB30_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb30_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word1.rs deleted file mode 100644 index 3acacbf5f..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb30_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB30_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB30_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 30 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb30_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb30_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb30_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb30_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb30_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb30_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb30_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb30_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB30_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb30_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_cs.rs deleted file mode 100644 index 64768c412..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB31_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB31_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb31_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb31_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb31_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb31_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB31_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb31_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_id.rs deleted file mode 100644 index 8f785ced7..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB31_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB31_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb31_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb31_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb31_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb31_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB31_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb31_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word0.rs deleted file mode 100644 index 56ba1f800..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB31_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB31_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb31_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb31_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb31_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb31_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB31_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb31_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word1.rs deleted file mode 100644 index 936d6b103..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb31_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB31_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB31_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 31 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb31_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb31_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb31_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb31_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb31_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb31_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb31_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb31_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB31_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb31_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_cs.rs deleted file mode 100644 index 77794ccb1..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB3_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb3_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb3_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb3_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb3_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb3_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_id.rs deleted file mode 100644 index 8b3a0b328..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB3_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb3_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb3_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb3_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb3_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb3_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word0.rs deleted file mode 100644 index daf69a22b..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb3_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb3_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb3_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb3_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb3_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word1.rs deleted file mode 100644 index e4de46f92..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb3_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB3_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB3_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb3_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb3_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb3_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb3_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb3_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb3_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb3_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb3_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB3_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb3_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_cs.rs deleted file mode 100644 index 4085893c4..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB4_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb4_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb4_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb4_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb4_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb4_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_id.rs deleted file mode 100644 index 09ddcc317..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB4_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb4_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb4_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb4_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb4_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb4_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word0.rs deleted file mode 100644 index 08b5c0470..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb4_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb4_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb4_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb4_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb4_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word1.rs deleted file mode 100644 index adbf2004a..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb4_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB4_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB4_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb4_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb4_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb4_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb4_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb4_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb4_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb4_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb4_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB4_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb4_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_cs.rs deleted file mode 100644 index 3b85482ff..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB5_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb5_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb5_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb5_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb5_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb5_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_id.rs deleted file mode 100644 index 11e48ecc0..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB5_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb5_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb5_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb5_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb5_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb5_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word0.rs deleted file mode 100644 index 1c4f4b76f..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb5_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb5_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb5_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb5_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb5_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word1.rs deleted file mode 100644 index 498ad7512..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb5_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB5_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB5_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb5_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb5_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb5_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb5_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb5_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb5_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb5_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb5_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB5_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb5_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_cs.rs deleted file mode 100644 index a7d2b6e6e..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB6_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb6_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb6_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb6_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb6_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb6_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_id.rs deleted file mode 100644 index 8819e5218..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB6_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb6_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb6_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb6_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb6_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb6_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word0.rs deleted file mode 100644 index 7547cc88a..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb6_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb6_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb6_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb6_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb6_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word1.rs deleted file mode 100644 index 0880c7628..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb6_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB6_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB6_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb6_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb6_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb6_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb6_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb6_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb6_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb6_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb6_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB6_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb6_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_cs.rs deleted file mode 100644 index 1b4b05793..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB7_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb7_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb7_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb7_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb7_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb7_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_id.rs deleted file mode 100644 index 1fbcf6e51..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB7_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb7_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb7_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb7_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb7_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb7_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word0.rs deleted file mode 100644 index 22bb2cd92..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb7_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb7_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb7_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb7_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb7_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word1.rs deleted file mode 100644 index f2ea8eaca..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb7_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB7_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB7_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb7_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb7_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb7_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb7_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb7_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb7_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb7_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb7_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB7_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb7_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_cs.rs deleted file mode 100644 index d8cd1ee67..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB8_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb8_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb8_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb8_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb8_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb8_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_id.rs deleted file mode 100644 index 8a95c1fae..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB8_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb8_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb8_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb8_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb8_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb8_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word0.rs deleted file mode 100644 index 30b369d0e..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb8_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb8_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb8_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb8_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb8_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word1.rs deleted file mode 100644 index d76c4a9a6..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb8_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB8_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB8_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb8_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb8_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb8_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb8_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb8_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb8_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb8_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb8_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB8_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb8_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_cs.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_cs.rs deleted file mode 100644 index 347e36ef8..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_cs.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MB9_8B_CS` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_8B_CS` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb9_8bCsSpec; -impl crate::RegisterSpec for Mb8bGroupMb9_8bCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_cs::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb9_8bCsSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_cs::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb9_8bCsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_8B_CS to value 0"] -impl crate::Resettable for Mb8bGroupMb9_8bCsSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_id.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_id.rs deleted file mode 100644 index 16a78a2cc..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MB9_8B_ID` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_8B_ID` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb9_8bIdSpec; -impl crate::RegisterSpec for Mb8bGroupMb9_8bIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_id::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb9_8bIdSpec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_id::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb9_8bIdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_8B_ID to value 0"] -impl crate::Resettable for Mb8bGroupMb9_8bIdSpec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word0.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word0.rs deleted file mode 100644 index fc0d4b252..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_8B_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_8B_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb9_8bWord0Spec; -impl crate::RegisterSpec for Mb8bGroupMb9_8bWord0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_word0::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb9_8bWord0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_word0::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb9_8bWord0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_8B_WORD0 to value 0"] -impl crate::Resettable for Mb8bGroupMb9_8bWord0Spec {} diff --git a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word1.rs b/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word1.rs deleted file mode 100644 index d4413a60a..000000000 --- a/mcxa276-pac/src/can0/mb_8b_group_mb9_8b_word1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MB9_8B_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `MB9_8B_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD_8B Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_8b_group_mb9_8b_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_8b_group_mb9_8b_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mb8bGroupMb9_8bWord1Spec; -impl crate::RegisterSpec for Mb8bGroupMb9_8bWord1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_8b_group_mb9_8b_word1::R`](R) reader structure"] -impl crate::Readable for Mb8bGroupMb9_8bWord1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_8b_group_mb9_8b_word1::W`](W) writer structure"] -impl crate::Writable for Mb8bGroupMb9_8bWord1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MB9_8B_WORD1 to value 0"] -impl crate::Resettable for Mb8bGroupMb9_8bWord1Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs0.rs b/mcxa276-pac/src/can0/mb_group_cs0.rs deleted file mode 100644 index 769483906..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs0.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS0` reader"] -pub type R = crate::R; -#[doc = "Register `CS0` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 0 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs0Spec; -impl crate::RegisterSpec for MbGroupCs0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs0::R`](R) reader structure"] -impl crate::Readable for MbGroupCs0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs0::W`](W) writer structure"] -impl crate::Writable for MbGroupCs0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS0 to value 0"] -impl crate::Resettable for MbGroupCs0Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs1.rs b/mcxa276-pac/src/can0/mb_group_cs1.rs deleted file mode 100644 index 9330bfc8c..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs1.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS1` reader"] -pub type R = crate::R; -#[doc = "Register `CS1` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 1 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs1Spec; -impl crate::RegisterSpec for MbGroupCs1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs1::R`](R) reader structure"] -impl crate::Readable for MbGroupCs1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs1::W`](W) writer structure"] -impl crate::Writable for MbGroupCs1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS1 to value 0"] -impl crate::Resettable for MbGroupCs1Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs10.rs b/mcxa276-pac/src/can0/mb_group_cs10.rs deleted file mode 100644 index e1379bf42..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs10.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS10` reader"] -pub type R = crate::R; -#[doc = "Register `CS10` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 10 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs10Spec; -impl crate::RegisterSpec for MbGroupCs10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs10::R`](R) reader structure"] -impl crate::Readable for MbGroupCs10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs10::W`](W) writer structure"] -impl crate::Writable for MbGroupCs10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS10 to value 0"] -impl crate::Resettable for MbGroupCs10Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs11.rs b/mcxa276-pac/src/can0/mb_group_cs11.rs deleted file mode 100644 index c3efc1f76..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs11.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS11` reader"] -pub type R = crate::R; -#[doc = "Register `CS11` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 11 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs11Spec; -impl crate::RegisterSpec for MbGroupCs11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs11::R`](R) reader structure"] -impl crate::Readable for MbGroupCs11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs11::W`](W) writer structure"] -impl crate::Writable for MbGroupCs11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS11 to value 0"] -impl crate::Resettable for MbGroupCs11Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs12.rs b/mcxa276-pac/src/can0/mb_group_cs12.rs deleted file mode 100644 index c306e5143..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs12.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS12` reader"] -pub type R = crate::R; -#[doc = "Register `CS12` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 12 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs12Spec; -impl crate::RegisterSpec for MbGroupCs12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs12::R`](R) reader structure"] -impl crate::Readable for MbGroupCs12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs12::W`](W) writer structure"] -impl crate::Writable for MbGroupCs12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS12 to value 0"] -impl crate::Resettable for MbGroupCs12Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs13.rs b/mcxa276-pac/src/can0/mb_group_cs13.rs deleted file mode 100644 index 567f0cc88..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs13.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS13` reader"] -pub type R = crate::R; -#[doc = "Register `CS13` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 13 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs13Spec; -impl crate::RegisterSpec for MbGroupCs13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs13::R`](R) reader structure"] -impl crate::Readable for MbGroupCs13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs13::W`](W) writer structure"] -impl crate::Writable for MbGroupCs13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS13 to value 0"] -impl crate::Resettable for MbGroupCs13Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs14.rs b/mcxa276-pac/src/can0/mb_group_cs14.rs deleted file mode 100644 index 85d1b95f9..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs14.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS14` reader"] -pub type R = crate::R; -#[doc = "Register `CS14` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 14 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs14Spec; -impl crate::RegisterSpec for MbGroupCs14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs14::R`](R) reader structure"] -impl crate::Readable for MbGroupCs14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs14::W`](W) writer structure"] -impl crate::Writable for MbGroupCs14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS14 to value 0"] -impl crate::Resettable for MbGroupCs14Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs15.rs b/mcxa276-pac/src/can0/mb_group_cs15.rs deleted file mode 100644 index f2a4c7f91..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs15.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS15` reader"] -pub type R = crate::R; -#[doc = "Register `CS15` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 15 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs15Spec; -impl crate::RegisterSpec for MbGroupCs15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs15::R`](R) reader structure"] -impl crate::Readable for MbGroupCs15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs15::W`](W) writer structure"] -impl crate::Writable for MbGroupCs15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS15 to value 0"] -impl crate::Resettable for MbGroupCs15Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs16.rs b/mcxa276-pac/src/can0/mb_group_cs16.rs deleted file mode 100644 index c8e9ae120..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs16.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS16` reader"] -pub type R = crate::R; -#[doc = "Register `CS16` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 16 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs16Spec; -impl crate::RegisterSpec for MbGroupCs16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs16::R`](R) reader structure"] -impl crate::Readable for MbGroupCs16Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs16::W`](W) writer structure"] -impl crate::Writable for MbGroupCs16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS16 to value 0"] -impl crate::Resettable for MbGroupCs16Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs17.rs b/mcxa276-pac/src/can0/mb_group_cs17.rs deleted file mode 100644 index f5150c686..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs17.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS17` reader"] -pub type R = crate::R; -#[doc = "Register `CS17` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 17 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs17Spec; -impl crate::RegisterSpec for MbGroupCs17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs17::R`](R) reader structure"] -impl crate::Readable for MbGroupCs17Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs17::W`](W) writer structure"] -impl crate::Writable for MbGroupCs17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS17 to value 0"] -impl crate::Resettable for MbGroupCs17Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs18.rs b/mcxa276-pac/src/can0/mb_group_cs18.rs deleted file mode 100644 index 2abac4b34..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs18.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS18` reader"] -pub type R = crate::R; -#[doc = "Register `CS18` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 18 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs18Spec; -impl crate::RegisterSpec for MbGroupCs18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs18::R`](R) reader structure"] -impl crate::Readable for MbGroupCs18Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs18::W`](W) writer structure"] -impl crate::Writable for MbGroupCs18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS18 to value 0"] -impl crate::Resettable for MbGroupCs18Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs19.rs b/mcxa276-pac/src/can0/mb_group_cs19.rs deleted file mode 100644 index 42d209cd5..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs19.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS19` reader"] -pub type R = crate::R; -#[doc = "Register `CS19` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 19 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs19Spec; -impl crate::RegisterSpec for MbGroupCs19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs19::R`](R) reader structure"] -impl crate::Readable for MbGroupCs19Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs19::W`](W) writer structure"] -impl crate::Writable for MbGroupCs19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS19 to value 0"] -impl crate::Resettable for MbGroupCs19Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs2.rs b/mcxa276-pac/src/can0/mb_group_cs2.rs deleted file mode 100644 index be1a59e3a..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs2.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS2` reader"] -pub type R = crate::R; -#[doc = "Register `CS2` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 2 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs2Spec; -impl crate::RegisterSpec for MbGroupCs2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs2::R`](R) reader structure"] -impl crate::Readable for MbGroupCs2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs2::W`](W) writer structure"] -impl crate::Writable for MbGroupCs2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS2 to value 0"] -impl crate::Resettable for MbGroupCs2Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs20.rs b/mcxa276-pac/src/can0/mb_group_cs20.rs deleted file mode 100644 index a06ec6212..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs20.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS20` reader"] -pub type R = crate::R; -#[doc = "Register `CS20` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 20 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs20Spec; -impl crate::RegisterSpec for MbGroupCs20Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs20::R`](R) reader structure"] -impl crate::Readable for MbGroupCs20Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs20::W`](W) writer structure"] -impl crate::Writable for MbGroupCs20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS20 to value 0"] -impl crate::Resettable for MbGroupCs20Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs21.rs b/mcxa276-pac/src/can0/mb_group_cs21.rs deleted file mode 100644 index c357f07ed..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs21.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS21` reader"] -pub type R = crate::R; -#[doc = "Register `CS21` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 21 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs21Spec; -impl crate::RegisterSpec for MbGroupCs21Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs21::R`](R) reader structure"] -impl crate::Readable for MbGroupCs21Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs21::W`](W) writer structure"] -impl crate::Writable for MbGroupCs21Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS21 to value 0"] -impl crate::Resettable for MbGroupCs21Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs22.rs b/mcxa276-pac/src/can0/mb_group_cs22.rs deleted file mode 100644 index ef7177879..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs22.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS22` reader"] -pub type R = crate::R; -#[doc = "Register `CS22` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 22 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs22Spec; -impl crate::RegisterSpec for MbGroupCs22Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs22::R`](R) reader structure"] -impl crate::Readable for MbGroupCs22Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs22::W`](W) writer structure"] -impl crate::Writable for MbGroupCs22Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS22 to value 0"] -impl crate::Resettable for MbGroupCs22Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs23.rs b/mcxa276-pac/src/can0/mb_group_cs23.rs deleted file mode 100644 index 524b32d71..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs23.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS23` reader"] -pub type R = crate::R; -#[doc = "Register `CS23` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 23 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs23Spec; -impl crate::RegisterSpec for MbGroupCs23Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs23::R`](R) reader structure"] -impl crate::Readable for MbGroupCs23Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs23::W`](W) writer structure"] -impl crate::Writable for MbGroupCs23Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS23 to value 0"] -impl crate::Resettable for MbGroupCs23Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs24.rs b/mcxa276-pac/src/can0/mb_group_cs24.rs deleted file mode 100644 index 76be50495..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs24.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS24` reader"] -pub type R = crate::R; -#[doc = "Register `CS24` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 24 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs24Spec; -impl crate::RegisterSpec for MbGroupCs24Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs24::R`](R) reader structure"] -impl crate::Readable for MbGroupCs24Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs24::W`](W) writer structure"] -impl crate::Writable for MbGroupCs24Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS24 to value 0"] -impl crate::Resettable for MbGroupCs24Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs25.rs b/mcxa276-pac/src/can0/mb_group_cs25.rs deleted file mode 100644 index b08373c7f..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs25.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS25` reader"] -pub type R = crate::R; -#[doc = "Register `CS25` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 25 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs25Spec; -impl crate::RegisterSpec for MbGroupCs25Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs25::R`](R) reader structure"] -impl crate::Readable for MbGroupCs25Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs25::W`](W) writer structure"] -impl crate::Writable for MbGroupCs25Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS25 to value 0"] -impl crate::Resettable for MbGroupCs25Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs26.rs b/mcxa276-pac/src/can0/mb_group_cs26.rs deleted file mode 100644 index 43cca1e61..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs26.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS26` reader"] -pub type R = crate::R; -#[doc = "Register `CS26` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 26 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs26Spec; -impl crate::RegisterSpec for MbGroupCs26Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs26::R`](R) reader structure"] -impl crate::Readable for MbGroupCs26Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs26::W`](W) writer structure"] -impl crate::Writable for MbGroupCs26Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS26 to value 0"] -impl crate::Resettable for MbGroupCs26Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs27.rs b/mcxa276-pac/src/can0/mb_group_cs27.rs deleted file mode 100644 index c2bc40667..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs27.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS27` reader"] -pub type R = crate::R; -#[doc = "Register `CS27` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 27 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs27Spec; -impl crate::RegisterSpec for MbGroupCs27Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs27::R`](R) reader structure"] -impl crate::Readable for MbGroupCs27Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs27::W`](W) writer structure"] -impl crate::Writable for MbGroupCs27Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS27 to value 0"] -impl crate::Resettable for MbGroupCs27Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs28.rs b/mcxa276-pac/src/can0/mb_group_cs28.rs deleted file mode 100644 index 38321681d..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs28.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS28` reader"] -pub type R = crate::R; -#[doc = "Register `CS28` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 28 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs28Spec; -impl crate::RegisterSpec for MbGroupCs28Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs28::R`](R) reader structure"] -impl crate::Readable for MbGroupCs28Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs28::W`](W) writer structure"] -impl crate::Writable for MbGroupCs28Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS28 to value 0"] -impl crate::Resettable for MbGroupCs28Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs29.rs b/mcxa276-pac/src/can0/mb_group_cs29.rs deleted file mode 100644 index 2d82aef84..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs29.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS29` reader"] -pub type R = crate::R; -#[doc = "Register `CS29` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 29 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs29Spec; -impl crate::RegisterSpec for MbGroupCs29Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs29::R`](R) reader structure"] -impl crate::Readable for MbGroupCs29Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs29::W`](W) writer structure"] -impl crate::Writable for MbGroupCs29Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS29 to value 0"] -impl crate::Resettable for MbGroupCs29Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs3.rs b/mcxa276-pac/src/can0/mb_group_cs3.rs deleted file mode 100644 index a42c3e4b0..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs3.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS3` reader"] -pub type R = crate::R; -#[doc = "Register `CS3` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 3 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs3Spec; -impl crate::RegisterSpec for MbGroupCs3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs3::R`](R) reader structure"] -impl crate::Readable for MbGroupCs3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs3::W`](W) writer structure"] -impl crate::Writable for MbGroupCs3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS3 to value 0"] -impl crate::Resettable for MbGroupCs3Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs30.rs b/mcxa276-pac/src/can0/mb_group_cs30.rs deleted file mode 100644 index e8fd7468b..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs30.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS30` reader"] -pub type R = crate::R; -#[doc = "Register `CS30` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 30 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs30Spec; -impl crate::RegisterSpec for MbGroupCs30Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs30::R`](R) reader structure"] -impl crate::Readable for MbGroupCs30Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs30::W`](W) writer structure"] -impl crate::Writable for MbGroupCs30Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS30 to value 0"] -impl crate::Resettable for MbGroupCs30Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs31.rs b/mcxa276-pac/src/can0/mb_group_cs31.rs deleted file mode 100644 index 11edfae3e..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs31.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS31` reader"] -pub type R = crate::R; -#[doc = "Register `CS31` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 31 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs31Spec; -impl crate::RegisterSpec for MbGroupCs31Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs31::R`](R) reader structure"] -impl crate::Readable for MbGroupCs31Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs31::W`](W) writer structure"] -impl crate::Writable for MbGroupCs31Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS31 to value 0"] -impl crate::Resettable for MbGroupCs31Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs4.rs b/mcxa276-pac/src/can0/mb_group_cs4.rs deleted file mode 100644 index e6f2125d1..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs4.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS4` reader"] -pub type R = crate::R; -#[doc = "Register `CS4` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 4 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs4Spec; -impl crate::RegisterSpec for MbGroupCs4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs4::R`](R) reader structure"] -impl crate::Readable for MbGroupCs4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs4::W`](W) writer structure"] -impl crate::Writable for MbGroupCs4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS4 to value 0"] -impl crate::Resettable for MbGroupCs4Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs5.rs b/mcxa276-pac/src/can0/mb_group_cs5.rs deleted file mode 100644 index 0103fd6b3..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs5.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS5` reader"] -pub type R = crate::R; -#[doc = "Register `CS5` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 5 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs5Spec; -impl crate::RegisterSpec for MbGroupCs5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs5::R`](R) reader structure"] -impl crate::Readable for MbGroupCs5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs5::W`](W) writer structure"] -impl crate::Writable for MbGroupCs5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS5 to value 0"] -impl crate::Resettable for MbGroupCs5Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs6.rs b/mcxa276-pac/src/can0/mb_group_cs6.rs deleted file mode 100644 index 52bf61660..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs6.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS6` reader"] -pub type R = crate::R; -#[doc = "Register `CS6` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 6 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs6Spec; -impl crate::RegisterSpec for MbGroupCs6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs6::R`](R) reader structure"] -impl crate::Readable for MbGroupCs6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs6::W`](W) writer structure"] -impl crate::Writable for MbGroupCs6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS6 to value 0"] -impl crate::Resettable for MbGroupCs6Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs7.rs b/mcxa276-pac/src/can0/mb_group_cs7.rs deleted file mode 100644 index cfb694949..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs7.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS7` reader"] -pub type R = crate::R; -#[doc = "Register `CS7` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 7 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs7Spec; -impl crate::RegisterSpec for MbGroupCs7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs7::R`](R) reader structure"] -impl crate::Readable for MbGroupCs7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs7::W`](W) writer structure"] -impl crate::Writable for MbGroupCs7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS7 to value 0"] -impl crate::Resettable for MbGroupCs7Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs8.rs b/mcxa276-pac/src/can0/mb_group_cs8.rs deleted file mode 100644 index 6fe0e149f..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs8.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS8` reader"] -pub type R = crate::R; -#[doc = "Register `CS8` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 8 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs8Spec; -impl crate::RegisterSpec for MbGroupCs8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs8::R`](R) reader structure"] -impl crate::Readable for MbGroupCs8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs8::W`](W) writer structure"] -impl crate::Writable for MbGroupCs8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS8 to value 0"] -impl crate::Resettable for MbGroupCs8Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_cs9.rs b/mcxa276-pac/src/can0/mb_group_cs9.rs deleted file mode 100644 index 22266fe90..000000000 --- a/mcxa276-pac/src/can0/mb_group_cs9.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CS9` reader"] -pub type R = crate::R; -#[doc = "Register `CS9` writer"] -pub type W = crate::W; -#[doc = "Field `TIME_STAMP` reader - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampR = crate::FieldReader; -#[doc = "Field `TIME_STAMP` writer - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] -pub type TimeStampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `DLC` reader - Length of the data to be stored/transmitted."] -pub type DlcR = crate::FieldReader; -#[doc = "Field `DLC` writer - Length of the data to be stored/transmitted."] -pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RTR` reader - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrR = crate::BitReader; -#[doc = "Field `RTR` writer - Remote Transmission Request. One/zero for remote/data frame."] -pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IDE` reader - ID Extended. One/zero for extended/standard format frame."] -pub type IdeR = crate::BitReader; -#[doc = "Field `IDE` writer - ID Extended. One/zero for extended/standard format frame."] -pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SRR` reader - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrR = crate::BitReader; -#[doc = "Field `SRR` writer - Substitute Remote Request. Contains a fixed recessive bit."] -pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CODE` reader - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeR = crate::FieldReader; -#[doc = "Field `CODE` writer - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] -pub type CodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ESI` reader - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiR = crate::BitReader; -#[doc = "Field `ESI` writer - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] -pub type EsiW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRS` reader - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsR = crate::BitReader; -#[doc = "Field `BRS` writer - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] -pub type BrsW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EDL` reader - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlR = crate::BitReader; -#[doc = "Field `EDL` writer - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] -pub type EdlW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&self) -> TimeStampR { - TimeStampR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&self) -> CodeR { - CodeR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&self) -> EsiR { - EsiR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&self) -> BrsR { - BrsR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&self) -> EdlR { - EdlR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."] - #[inline(always)] - pub fn time_stamp(&mut self) -> TimeStampW { - TimeStampW::new(self, 0) - } - #[doc = "Bits 16:19 - Length of the data to be stored/transmitted."] - #[inline(always)] - pub fn dlc(&mut self) -> DlcW { - DlcW::new(self, 16) - } - #[doc = "Bit 20 - Remote Transmission Request. One/zero for remote/data frame."] - #[inline(always)] - pub fn rtr(&mut self) -> RtrW { - RtrW::new(self, 20) - } - #[doc = "Bit 21 - ID Extended. One/zero for extended/standard format frame."] - #[inline(always)] - pub fn ide(&mut self) -> IdeW { - IdeW::new(self, 21) - } - #[doc = "Bit 22 - Substitute Remote Request. Contains a fixed recessive bit."] - #[inline(always)] - pub fn srr(&mut self) -> SrrW { - SrrW::new(self, 22) - } - #[doc = "Bits 24:27 - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."] - #[inline(always)] - pub fn code(&mut self) -> CodeW { - CodeW::new(self, 24) - } - #[doc = "Bit 29 - Error State Indicator. This bit indicates if the transmitting node is error active or error passive."] - #[inline(always)] - pub fn esi(&mut self) -> EsiW { - EsiW::new(self, 29) - } - #[doc = "Bit 30 - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."] - #[inline(always)] - pub fn brs(&mut self) -> BrsW { - BrsW::new(self, 30) - } - #[doc = "Bit 31 - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."] - #[inline(always)] - pub fn edl(&mut self) -> EdlW { - EdlW::new(self, 31) - } -} -#[doc = "Message Buffer 9 CS Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_cs9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_cs9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupCs9Spec; -impl crate::RegisterSpec for MbGroupCs9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_cs9::R`](R) reader structure"] -impl crate::Readable for MbGroupCs9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_cs9::W`](W) writer structure"] -impl crate::Writable for MbGroupCs9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CS9 to value 0"] -impl crate::Resettable for MbGroupCs9Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id0.rs b/mcxa276-pac/src/can0/mb_group_id0.rs deleted file mode 100644 index e3d894434..000000000 --- a/mcxa276-pac/src/can0/mb_group_id0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID0` reader"] -pub type R = crate::R; -#[doc = "Register `ID0` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 0 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId0Spec; -impl crate::RegisterSpec for MbGroupId0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id0::R`](R) reader structure"] -impl crate::Readable for MbGroupId0Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id0::W`](W) writer structure"] -impl crate::Writable for MbGroupId0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID0 to value 0"] -impl crate::Resettable for MbGroupId0Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id1.rs b/mcxa276-pac/src/can0/mb_group_id1.rs deleted file mode 100644 index 619300055..000000000 --- a/mcxa276-pac/src/can0/mb_group_id1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID1` reader"] -pub type R = crate::R; -#[doc = "Register `ID1` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 1 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId1Spec; -impl crate::RegisterSpec for MbGroupId1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id1::R`](R) reader structure"] -impl crate::Readable for MbGroupId1Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id1::W`](W) writer structure"] -impl crate::Writable for MbGroupId1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID1 to value 0"] -impl crate::Resettable for MbGroupId1Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id10.rs b/mcxa276-pac/src/can0/mb_group_id10.rs deleted file mode 100644 index 233cbe14b..000000000 --- a/mcxa276-pac/src/can0/mb_group_id10.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID10` reader"] -pub type R = crate::R; -#[doc = "Register `ID10` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 10 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId10Spec; -impl crate::RegisterSpec for MbGroupId10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id10::R`](R) reader structure"] -impl crate::Readable for MbGroupId10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id10::W`](W) writer structure"] -impl crate::Writable for MbGroupId10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID10 to value 0"] -impl crate::Resettable for MbGroupId10Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id11.rs b/mcxa276-pac/src/can0/mb_group_id11.rs deleted file mode 100644 index 10c07330d..000000000 --- a/mcxa276-pac/src/can0/mb_group_id11.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID11` reader"] -pub type R = crate::R; -#[doc = "Register `ID11` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 11 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId11Spec; -impl crate::RegisterSpec for MbGroupId11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id11::R`](R) reader structure"] -impl crate::Readable for MbGroupId11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id11::W`](W) writer structure"] -impl crate::Writable for MbGroupId11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID11 to value 0"] -impl crate::Resettable for MbGroupId11Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id12.rs b/mcxa276-pac/src/can0/mb_group_id12.rs deleted file mode 100644 index adae1a5d0..000000000 --- a/mcxa276-pac/src/can0/mb_group_id12.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID12` reader"] -pub type R = crate::R; -#[doc = "Register `ID12` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 12 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId12Spec; -impl crate::RegisterSpec for MbGroupId12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id12::R`](R) reader structure"] -impl crate::Readable for MbGroupId12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id12::W`](W) writer structure"] -impl crate::Writable for MbGroupId12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID12 to value 0"] -impl crate::Resettable for MbGroupId12Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id13.rs b/mcxa276-pac/src/can0/mb_group_id13.rs deleted file mode 100644 index 8e3cdc83f..000000000 --- a/mcxa276-pac/src/can0/mb_group_id13.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID13` reader"] -pub type R = crate::R; -#[doc = "Register `ID13` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 13 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId13Spec; -impl crate::RegisterSpec for MbGroupId13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id13::R`](R) reader structure"] -impl crate::Readable for MbGroupId13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id13::W`](W) writer structure"] -impl crate::Writable for MbGroupId13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID13 to value 0"] -impl crate::Resettable for MbGroupId13Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id14.rs b/mcxa276-pac/src/can0/mb_group_id14.rs deleted file mode 100644 index 5e4705e52..000000000 --- a/mcxa276-pac/src/can0/mb_group_id14.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID14` reader"] -pub type R = crate::R; -#[doc = "Register `ID14` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 14 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId14Spec; -impl crate::RegisterSpec for MbGroupId14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id14::R`](R) reader structure"] -impl crate::Readable for MbGroupId14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id14::W`](W) writer structure"] -impl crate::Writable for MbGroupId14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID14 to value 0"] -impl crate::Resettable for MbGroupId14Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id15.rs b/mcxa276-pac/src/can0/mb_group_id15.rs deleted file mode 100644 index 1665afe8b..000000000 --- a/mcxa276-pac/src/can0/mb_group_id15.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID15` reader"] -pub type R = crate::R; -#[doc = "Register `ID15` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 15 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId15Spec; -impl crate::RegisterSpec for MbGroupId15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id15::R`](R) reader structure"] -impl crate::Readable for MbGroupId15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id15::W`](W) writer structure"] -impl crate::Writable for MbGroupId15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID15 to value 0"] -impl crate::Resettable for MbGroupId15Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id16.rs b/mcxa276-pac/src/can0/mb_group_id16.rs deleted file mode 100644 index 6a30b2f27..000000000 --- a/mcxa276-pac/src/can0/mb_group_id16.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID16` reader"] -pub type R = crate::R; -#[doc = "Register `ID16` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 16 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId16Spec; -impl crate::RegisterSpec for MbGroupId16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id16::R`](R) reader structure"] -impl crate::Readable for MbGroupId16Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id16::W`](W) writer structure"] -impl crate::Writable for MbGroupId16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID16 to value 0"] -impl crate::Resettable for MbGroupId16Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id17.rs b/mcxa276-pac/src/can0/mb_group_id17.rs deleted file mode 100644 index 1d5544aee..000000000 --- a/mcxa276-pac/src/can0/mb_group_id17.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID17` reader"] -pub type R = crate::R; -#[doc = "Register `ID17` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 17 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId17Spec; -impl crate::RegisterSpec for MbGroupId17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id17::R`](R) reader structure"] -impl crate::Readable for MbGroupId17Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id17::W`](W) writer structure"] -impl crate::Writable for MbGroupId17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID17 to value 0"] -impl crate::Resettable for MbGroupId17Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id18.rs b/mcxa276-pac/src/can0/mb_group_id18.rs deleted file mode 100644 index 61dc3e48d..000000000 --- a/mcxa276-pac/src/can0/mb_group_id18.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID18` reader"] -pub type R = crate::R; -#[doc = "Register `ID18` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 18 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId18Spec; -impl crate::RegisterSpec for MbGroupId18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id18::R`](R) reader structure"] -impl crate::Readable for MbGroupId18Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id18::W`](W) writer structure"] -impl crate::Writable for MbGroupId18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID18 to value 0"] -impl crate::Resettable for MbGroupId18Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id19.rs b/mcxa276-pac/src/can0/mb_group_id19.rs deleted file mode 100644 index a4f3b2284..000000000 --- a/mcxa276-pac/src/can0/mb_group_id19.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID19` reader"] -pub type R = crate::R; -#[doc = "Register `ID19` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 19 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId19Spec; -impl crate::RegisterSpec for MbGroupId19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id19::R`](R) reader structure"] -impl crate::Readable for MbGroupId19Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id19::W`](W) writer structure"] -impl crate::Writable for MbGroupId19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID19 to value 0"] -impl crate::Resettable for MbGroupId19Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id2.rs b/mcxa276-pac/src/can0/mb_group_id2.rs deleted file mode 100644 index 14c8e9289..000000000 --- a/mcxa276-pac/src/can0/mb_group_id2.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID2` reader"] -pub type R = crate::R; -#[doc = "Register `ID2` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 2 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId2Spec; -impl crate::RegisterSpec for MbGroupId2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id2::R`](R) reader structure"] -impl crate::Readable for MbGroupId2Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id2::W`](W) writer structure"] -impl crate::Writable for MbGroupId2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID2 to value 0"] -impl crate::Resettable for MbGroupId2Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id20.rs b/mcxa276-pac/src/can0/mb_group_id20.rs deleted file mode 100644 index 8421b0af7..000000000 --- a/mcxa276-pac/src/can0/mb_group_id20.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID20` reader"] -pub type R = crate::R; -#[doc = "Register `ID20` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 20 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId20Spec; -impl crate::RegisterSpec for MbGroupId20Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id20::R`](R) reader structure"] -impl crate::Readable for MbGroupId20Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id20::W`](W) writer structure"] -impl crate::Writable for MbGroupId20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID20 to value 0"] -impl crate::Resettable for MbGroupId20Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id21.rs b/mcxa276-pac/src/can0/mb_group_id21.rs deleted file mode 100644 index 40cff6b4c..000000000 --- a/mcxa276-pac/src/can0/mb_group_id21.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID21` reader"] -pub type R = crate::R; -#[doc = "Register `ID21` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 21 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId21Spec; -impl crate::RegisterSpec for MbGroupId21Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id21::R`](R) reader structure"] -impl crate::Readable for MbGroupId21Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id21::W`](W) writer structure"] -impl crate::Writable for MbGroupId21Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID21 to value 0"] -impl crate::Resettable for MbGroupId21Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id22.rs b/mcxa276-pac/src/can0/mb_group_id22.rs deleted file mode 100644 index 887ed99e1..000000000 --- a/mcxa276-pac/src/can0/mb_group_id22.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID22` reader"] -pub type R = crate::R; -#[doc = "Register `ID22` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 22 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId22Spec; -impl crate::RegisterSpec for MbGroupId22Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id22::R`](R) reader structure"] -impl crate::Readable for MbGroupId22Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id22::W`](W) writer structure"] -impl crate::Writable for MbGroupId22Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID22 to value 0"] -impl crate::Resettable for MbGroupId22Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id23.rs b/mcxa276-pac/src/can0/mb_group_id23.rs deleted file mode 100644 index 7860d067d..000000000 --- a/mcxa276-pac/src/can0/mb_group_id23.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID23` reader"] -pub type R = crate::R; -#[doc = "Register `ID23` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 23 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId23Spec; -impl crate::RegisterSpec for MbGroupId23Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id23::R`](R) reader structure"] -impl crate::Readable for MbGroupId23Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id23::W`](W) writer structure"] -impl crate::Writable for MbGroupId23Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID23 to value 0"] -impl crate::Resettable for MbGroupId23Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id24.rs b/mcxa276-pac/src/can0/mb_group_id24.rs deleted file mode 100644 index d3294c2b8..000000000 --- a/mcxa276-pac/src/can0/mb_group_id24.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID24` reader"] -pub type R = crate::R; -#[doc = "Register `ID24` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 24 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId24Spec; -impl crate::RegisterSpec for MbGroupId24Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id24::R`](R) reader structure"] -impl crate::Readable for MbGroupId24Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id24::W`](W) writer structure"] -impl crate::Writable for MbGroupId24Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID24 to value 0"] -impl crate::Resettable for MbGroupId24Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id25.rs b/mcxa276-pac/src/can0/mb_group_id25.rs deleted file mode 100644 index 46d8a49d6..000000000 --- a/mcxa276-pac/src/can0/mb_group_id25.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID25` reader"] -pub type R = crate::R; -#[doc = "Register `ID25` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 25 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId25Spec; -impl crate::RegisterSpec for MbGroupId25Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id25::R`](R) reader structure"] -impl crate::Readable for MbGroupId25Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id25::W`](W) writer structure"] -impl crate::Writable for MbGroupId25Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID25 to value 0"] -impl crate::Resettable for MbGroupId25Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id26.rs b/mcxa276-pac/src/can0/mb_group_id26.rs deleted file mode 100644 index 4eea3ac3d..000000000 --- a/mcxa276-pac/src/can0/mb_group_id26.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID26` reader"] -pub type R = crate::R; -#[doc = "Register `ID26` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 26 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId26Spec; -impl crate::RegisterSpec for MbGroupId26Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id26::R`](R) reader structure"] -impl crate::Readable for MbGroupId26Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id26::W`](W) writer structure"] -impl crate::Writable for MbGroupId26Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID26 to value 0"] -impl crate::Resettable for MbGroupId26Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id27.rs b/mcxa276-pac/src/can0/mb_group_id27.rs deleted file mode 100644 index 89c2b2c6c..000000000 --- a/mcxa276-pac/src/can0/mb_group_id27.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID27` reader"] -pub type R = crate::R; -#[doc = "Register `ID27` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 27 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId27Spec; -impl crate::RegisterSpec for MbGroupId27Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id27::R`](R) reader structure"] -impl crate::Readable for MbGroupId27Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id27::W`](W) writer structure"] -impl crate::Writable for MbGroupId27Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID27 to value 0"] -impl crate::Resettable for MbGroupId27Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id28.rs b/mcxa276-pac/src/can0/mb_group_id28.rs deleted file mode 100644 index 5aeff5356..000000000 --- a/mcxa276-pac/src/can0/mb_group_id28.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID28` reader"] -pub type R = crate::R; -#[doc = "Register `ID28` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 28 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId28Spec; -impl crate::RegisterSpec for MbGroupId28Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id28::R`](R) reader structure"] -impl crate::Readable for MbGroupId28Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id28::W`](W) writer structure"] -impl crate::Writable for MbGroupId28Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID28 to value 0"] -impl crate::Resettable for MbGroupId28Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id29.rs b/mcxa276-pac/src/can0/mb_group_id29.rs deleted file mode 100644 index 32f887329..000000000 --- a/mcxa276-pac/src/can0/mb_group_id29.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID29` reader"] -pub type R = crate::R; -#[doc = "Register `ID29` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 29 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId29Spec; -impl crate::RegisterSpec for MbGroupId29Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id29::R`](R) reader structure"] -impl crate::Readable for MbGroupId29Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id29::W`](W) writer structure"] -impl crate::Writable for MbGroupId29Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID29 to value 0"] -impl crate::Resettable for MbGroupId29Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id3.rs b/mcxa276-pac/src/can0/mb_group_id3.rs deleted file mode 100644 index 7aeb45c76..000000000 --- a/mcxa276-pac/src/can0/mb_group_id3.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID3` reader"] -pub type R = crate::R; -#[doc = "Register `ID3` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 3 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId3Spec; -impl crate::RegisterSpec for MbGroupId3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id3::R`](R) reader structure"] -impl crate::Readable for MbGroupId3Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id3::W`](W) writer structure"] -impl crate::Writable for MbGroupId3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID3 to value 0"] -impl crate::Resettable for MbGroupId3Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id30.rs b/mcxa276-pac/src/can0/mb_group_id30.rs deleted file mode 100644 index 3583657ec..000000000 --- a/mcxa276-pac/src/can0/mb_group_id30.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID30` reader"] -pub type R = crate::R; -#[doc = "Register `ID30` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 30 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId30Spec; -impl crate::RegisterSpec for MbGroupId30Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id30::R`](R) reader structure"] -impl crate::Readable for MbGroupId30Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id30::W`](W) writer structure"] -impl crate::Writable for MbGroupId30Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID30 to value 0"] -impl crate::Resettable for MbGroupId30Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id31.rs b/mcxa276-pac/src/can0/mb_group_id31.rs deleted file mode 100644 index fa3972aa7..000000000 --- a/mcxa276-pac/src/can0/mb_group_id31.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID31` reader"] -pub type R = crate::R; -#[doc = "Register `ID31` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 31 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId31Spec; -impl crate::RegisterSpec for MbGroupId31Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id31::R`](R) reader structure"] -impl crate::Readable for MbGroupId31Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id31::W`](W) writer structure"] -impl crate::Writable for MbGroupId31Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID31 to value 0"] -impl crate::Resettable for MbGroupId31Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id4.rs b/mcxa276-pac/src/can0/mb_group_id4.rs deleted file mode 100644 index 26619251d..000000000 --- a/mcxa276-pac/src/can0/mb_group_id4.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID4` reader"] -pub type R = crate::R; -#[doc = "Register `ID4` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 4 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId4Spec; -impl crate::RegisterSpec for MbGroupId4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id4::R`](R) reader structure"] -impl crate::Readable for MbGroupId4Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id4::W`](W) writer structure"] -impl crate::Writable for MbGroupId4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID4 to value 0"] -impl crate::Resettable for MbGroupId4Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id5.rs b/mcxa276-pac/src/can0/mb_group_id5.rs deleted file mode 100644 index 40602ee2c..000000000 --- a/mcxa276-pac/src/can0/mb_group_id5.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID5` reader"] -pub type R = crate::R; -#[doc = "Register `ID5` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 5 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId5Spec; -impl crate::RegisterSpec for MbGroupId5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id5::R`](R) reader structure"] -impl crate::Readable for MbGroupId5Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id5::W`](W) writer structure"] -impl crate::Writable for MbGroupId5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID5 to value 0"] -impl crate::Resettable for MbGroupId5Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id6.rs b/mcxa276-pac/src/can0/mb_group_id6.rs deleted file mode 100644 index 1e22cfbc7..000000000 --- a/mcxa276-pac/src/can0/mb_group_id6.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID6` reader"] -pub type R = crate::R; -#[doc = "Register `ID6` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 6 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId6Spec; -impl crate::RegisterSpec for MbGroupId6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id6::R`](R) reader structure"] -impl crate::Readable for MbGroupId6Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id6::W`](W) writer structure"] -impl crate::Writable for MbGroupId6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID6 to value 0"] -impl crate::Resettable for MbGroupId6Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id7.rs b/mcxa276-pac/src/can0/mb_group_id7.rs deleted file mode 100644 index e63b16d20..000000000 --- a/mcxa276-pac/src/can0/mb_group_id7.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID7` reader"] -pub type R = crate::R; -#[doc = "Register `ID7` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 7 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId7Spec; -impl crate::RegisterSpec for MbGroupId7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id7::R`](R) reader structure"] -impl crate::Readable for MbGroupId7Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id7::W`](W) writer structure"] -impl crate::Writable for MbGroupId7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID7 to value 0"] -impl crate::Resettable for MbGroupId7Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id8.rs b/mcxa276-pac/src/can0/mb_group_id8.rs deleted file mode 100644 index 47f5e1756..000000000 --- a/mcxa276-pac/src/can0/mb_group_id8.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID8` reader"] -pub type R = crate::R; -#[doc = "Register `ID8` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 8 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId8Spec; -impl crate::RegisterSpec for MbGroupId8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id8::R`](R) reader structure"] -impl crate::Readable for MbGroupId8Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id8::W`](W) writer structure"] -impl crate::Writable for MbGroupId8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID8 to value 0"] -impl crate::Resettable for MbGroupId8Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_id9.rs b/mcxa276-pac/src/can0/mb_group_id9.rs deleted file mode 100644 index 882ebea03..000000000 --- a/mcxa276-pac/src/can0/mb_group_id9.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `ID9` reader"] -pub type R = crate::R; -#[doc = "Register `ID9` writer"] -pub type W = crate::W; -#[doc = "Field `EXT` reader - Contains extended (LOW word) identifier of message buffer."] -pub type ExtR = crate::FieldReader; -#[doc = "Field `EXT` writer - Contains extended (LOW word) identifier of message buffer."] -pub type ExtW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; -#[doc = "Field `STD` reader - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdR = crate::FieldReader; -#[doc = "Field `STD` writer - Contains standard/extended (HIGH word) identifier of message buffer."] -pub type StdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `PRIO` reader - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioR = crate::FieldReader; -#[doc = "Field `PRIO` writer - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] -pub type PrioW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&self) -> ExtR { - ExtR::new(self.bits & 0x0003_ffff) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&self) -> StdR { - StdR::new(((self.bits >> 18) & 0x07ff) as u16) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&self) -> PrioR { - PrioR::new(((self.bits >> 29) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:17 - Contains extended (LOW word) identifier of message buffer."] - #[inline(always)] - pub fn ext(&mut self) -> ExtW { - ExtW::new(self, 0) - } - #[doc = "Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer."] - #[inline(always)] - pub fn std(&mut self) -> StdW { - StdW::new(self, 18) - } - #[doc = "Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."] - #[inline(always)] - pub fn prio(&mut self) -> PrioW { - PrioW::new(self, 29) - } -} -#[doc = "Message Buffer 9 ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_id9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_id9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupId9Spec; -impl crate::RegisterSpec for MbGroupId9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_id9::R`](R) reader structure"] -impl crate::Readable for MbGroupId9Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_id9::W`](W) writer structure"] -impl crate::Writable for MbGroupId9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ID9 to value 0"] -impl crate::Resettable for MbGroupId9Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word00.rs b/mcxa276-pac/src/can0/mb_group_word00.rs deleted file mode 100644 index d8857f3ed..000000000 --- a/mcxa276-pac/src/can0/mb_group_word00.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD00` reader"] -pub type R = crate::R; -#[doc = "Register `WORD00` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word00::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word00::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord00Spec; -impl crate::RegisterSpec for MbGroupWord00Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word00::R`](R) reader structure"] -impl crate::Readable for MbGroupWord00Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word00::W`](W) writer structure"] -impl crate::Writable for MbGroupWord00Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD00 to value 0"] -impl crate::Resettable for MbGroupWord00Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word01.rs b/mcxa276-pac/src/can0/mb_group_word01.rs deleted file mode 100644 index 31a4461c6..000000000 --- a/mcxa276-pac/src/can0/mb_group_word01.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD01` reader"] -pub type R = crate::R; -#[doc = "Register `WORD01` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word01::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word01::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord01Spec; -impl crate::RegisterSpec for MbGroupWord01Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word01::R`](R) reader structure"] -impl crate::Readable for MbGroupWord01Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word01::W`](W) writer structure"] -impl crate::Writable for MbGroupWord01Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD01 to value 0"] -impl crate::Resettable for MbGroupWord01Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word010.rs b/mcxa276-pac/src/can0/mb_group_word010.rs deleted file mode 100644 index c2ceee444..000000000 --- a/mcxa276-pac/src/can0/mb_group_word010.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD010` reader"] -pub type R = crate::R; -#[doc = "Register `WORD010` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word010::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word010::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord010Spec; -impl crate::RegisterSpec for MbGroupWord010Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word010::R`](R) reader structure"] -impl crate::Readable for MbGroupWord010Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word010::W`](W) writer structure"] -impl crate::Writable for MbGroupWord010Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD010 to value 0"] -impl crate::Resettable for MbGroupWord010Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word011.rs b/mcxa276-pac/src/can0/mb_group_word011.rs deleted file mode 100644 index fad4380b1..000000000 --- a/mcxa276-pac/src/can0/mb_group_word011.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD011` reader"] -pub type R = crate::R; -#[doc = "Register `WORD011` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word011::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word011::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord011Spec; -impl crate::RegisterSpec for MbGroupWord011Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word011::R`](R) reader structure"] -impl crate::Readable for MbGroupWord011Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word011::W`](W) writer structure"] -impl crate::Writable for MbGroupWord011Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD011 to value 0"] -impl crate::Resettable for MbGroupWord011Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word012.rs b/mcxa276-pac/src/can0/mb_group_word012.rs deleted file mode 100644 index 8049c514a..000000000 --- a/mcxa276-pac/src/can0/mb_group_word012.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD012` reader"] -pub type R = crate::R; -#[doc = "Register `WORD012` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word012::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word012::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord012Spec; -impl crate::RegisterSpec for MbGroupWord012Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word012::R`](R) reader structure"] -impl crate::Readable for MbGroupWord012Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word012::W`](W) writer structure"] -impl crate::Writable for MbGroupWord012Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD012 to value 0"] -impl crate::Resettable for MbGroupWord012Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word013.rs b/mcxa276-pac/src/can0/mb_group_word013.rs deleted file mode 100644 index 602e8354e..000000000 --- a/mcxa276-pac/src/can0/mb_group_word013.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD013` reader"] -pub type R = crate::R; -#[doc = "Register `WORD013` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word013::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word013::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord013Spec; -impl crate::RegisterSpec for MbGroupWord013Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word013::R`](R) reader structure"] -impl crate::Readable for MbGroupWord013Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word013::W`](W) writer structure"] -impl crate::Writable for MbGroupWord013Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD013 to value 0"] -impl crate::Resettable for MbGroupWord013Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word014.rs b/mcxa276-pac/src/can0/mb_group_word014.rs deleted file mode 100644 index 0e4914c24..000000000 --- a/mcxa276-pac/src/can0/mb_group_word014.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD014` reader"] -pub type R = crate::R; -#[doc = "Register `WORD014` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word014::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word014::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord014Spec; -impl crate::RegisterSpec for MbGroupWord014Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word014::R`](R) reader structure"] -impl crate::Readable for MbGroupWord014Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word014::W`](W) writer structure"] -impl crate::Writable for MbGroupWord014Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD014 to value 0"] -impl crate::Resettable for MbGroupWord014Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word015.rs b/mcxa276-pac/src/can0/mb_group_word015.rs deleted file mode 100644 index 2d6aabaea..000000000 --- a/mcxa276-pac/src/can0/mb_group_word015.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD015` reader"] -pub type R = crate::R; -#[doc = "Register `WORD015` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word015::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word015::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord015Spec; -impl crate::RegisterSpec for MbGroupWord015Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word015::R`](R) reader structure"] -impl crate::Readable for MbGroupWord015Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word015::W`](W) writer structure"] -impl crate::Writable for MbGroupWord015Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD015 to value 0"] -impl crate::Resettable for MbGroupWord015Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word016.rs b/mcxa276-pac/src/can0/mb_group_word016.rs deleted file mode 100644 index a3bc01eff..000000000 --- a/mcxa276-pac/src/can0/mb_group_word016.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD016` reader"] -pub type R = crate::R; -#[doc = "Register `WORD016` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word016::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word016::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord016Spec; -impl crate::RegisterSpec for MbGroupWord016Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word016::R`](R) reader structure"] -impl crate::Readable for MbGroupWord016Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word016::W`](W) writer structure"] -impl crate::Writable for MbGroupWord016Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD016 to value 0"] -impl crate::Resettable for MbGroupWord016Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word017.rs b/mcxa276-pac/src/can0/mb_group_word017.rs deleted file mode 100644 index d1d2d29c5..000000000 --- a/mcxa276-pac/src/can0/mb_group_word017.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD017` reader"] -pub type R = crate::R; -#[doc = "Register `WORD017` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word017::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word017::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord017Spec; -impl crate::RegisterSpec for MbGroupWord017Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word017::R`](R) reader structure"] -impl crate::Readable for MbGroupWord017Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word017::W`](W) writer structure"] -impl crate::Writable for MbGroupWord017Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD017 to value 0"] -impl crate::Resettable for MbGroupWord017Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word018.rs b/mcxa276-pac/src/can0/mb_group_word018.rs deleted file mode 100644 index bd584b8d3..000000000 --- a/mcxa276-pac/src/can0/mb_group_word018.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD018` reader"] -pub type R = crate::R; -#[doc = "Register `WORD018` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word018::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word018::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord018Spec; -impl crate::RegisterSpec for MbGroupWord018Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word018::R`](R) reader structure"] -impl crate::Readable for MbGroupWord018Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word018::W`](W) writer structure"] -impl crate::Writable for MbGroupWord018Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD018 to value 0"] -impl crate::Resettable for MbGroupWord018Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word019.rs b/mcxa276-pac/src/can0/mb_group_word019.rs deleted file mode 100644 index 85711056b..000000000 --- a/mcxa276-pac/src/can0/mb_group_word019.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD019` reader"] -pub type R = crate::R; -#[doc = "Register `WORD019` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word019::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word019::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord019Spec; -impl crate::RegisterSpec for MbGroupWord019Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word019::R`](R) reader structure"] -impl crate::Readable for MbGroupWord019Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word019::W`](W) writer structure"] -impl crate::Writable for MbGroupWord019Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD019 to value 0"] -impl crate::Resettable for MbGroupWord019Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word02.rs b/mcxa276-pac/src/can0/mb_group_word02.rs deleted file mode 100644 index b54221d12..000000000 --- a/mcxa276-pac/src/can0/mb_group_word02.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD02` reader"] -pub type R = crate::R; -#[doc = "Register `WORD02` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word02::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word02::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord02Spec; -impl crate::RegisterSpec for MbGroupWord02Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word02::R`](R) reader structure"] -impl crate::Readable for MbGroupWord02Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word02::W`](W) writer structure"] -impl crate::Writable for MbGroupWord02Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD02 to value 0"] -impl crate::Resettable for MbGroupWord02Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word020.rs b/mcxa276-pac/src/can0/mb_group_word020.rs deleted file mode 100644 index e42568514..000000000 --- a/mcxa276-pac/src/can0/mb_group_word020.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD020` reader"] -pub type R = crate::R; -#[doc = "Register `WORD020` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word020::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word020::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord020Spec; -impl crate::RegisterSpec for MbGroupWord020Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word020::R`](R) reader structure"] -impl crate::Readable for MbGroupWord020Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word020::W`](W) writer structure"] -impl crate::Writable for MbGroupWord020Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD020 to value 0"] -impl crate::Resettable for MbGroupWord020Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word021.rs b/mcxa276-pac/src/can0/mb_group_word021.rs deleted file mode 100644 index 0aadc8a92..000000000 --- a/mcxa276-pac/src/can0/mb_group_word021.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD021` reader"] -pub type R = crate::R; -#[doc = "Register `WORD021` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 21 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word021::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word021::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord021Spec; -impl crate::RegisterSpec for MbGroupWord021Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word021::R`](R) reader structure"] -impl crate::Readable for MbGroupWord021Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word021::W`](W) writer structure"] -impl crate::Writable for MbGroupWord021Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD021 to value 0"] -impl crate::Resettable for MbGroupWord021Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word022.rs b/mcxa276-pac/src/can0/mb_group_word022.rs deleted file mode 100644 index c99006982..000000000 --- a/mcxa276-pac/src/can0/mb_group_word022.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD022` reader"] -pub type R = crate::R; -#[doc = "Register `WORD022` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 22 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word022::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word022::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord022Spec; -impl crate::RegisterSpec for MbGroupWord022Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word022::R`](R) reader structure"] -impl crate::Readable for MbGroupWord022Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word022::W`](W) writer structure"] -impl crate::Writable for MbGroupWord022Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD022 to value 0"] -impl crate::Resettable for MbGroupWord022Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word023.rs b/mcxa276-pac/src/can0/mb_group_word023.rs deleted file mode 100644 index 4d56fc116..000000000 --- a/mcxa276-pac/src/can0/mb_group_word023.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD023` reader"] -pub type R = crate::R; -#[doc = "Register `WORD023` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 23 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word023::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word023::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord023Spec; -impl crate::RegisterSpec for MbGroupWord023Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word023::R`](R) reader structure"] -impl crate::Readable for MbGroupWord023Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word023::W`](W) writer structure"] -impl crate::Writable for MbGroupWord023Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD023 to value 0"] -impl crate::Resettable for MbGroupWord023Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word024.rs b/mcxa276-pac/src/can0/mb_group_word024.rs deleted file mode 100644 index 625d0bcf9..000000000 --- a/mcxa276-pac/src/can0/mb_group_word024.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD024` reader"] -pub type R = crate::R; -#[doc = "Register `WORD024` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 24 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word024::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word024::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord024Spec; -impl crate::RegisterSpec for MbGroupWord024Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word024::R`](R) reader structure"] -impl crate::Readable for MbGroupWord024Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word024::W`](W) writer structure"] -impl crate::Writable for MbGroupWord024Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD024 to value 0"] -impl crate::Resettable for MbGroupWord024Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word025.rs b/mcxa276-pac/src/can0/mb_group_word025.rs deleted file mode 100644 index bebd23261..000000000 --- a/mcxa276-pac/src/can0/mb_group_word025.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD025` reader"] -pub type R = crate::R; -#[doc = "Register `WORD025` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 25 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word025::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word025::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord025Spec; -impl crate::RegisterSpec for MbGroupWord025Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word025::R`](R) reader structure"] -impl crate::Readable for MbGroupWord025Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word025::W`](W) writer structure"] -impl crate::Writable for MbGroupWord025Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD025 to value 0"] -impl crate::Resettable for MbGroupWord025Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word026.rs b/mcxa276-pac/src/can0/mb_group_word026.rs deleted file mode 100644 index fbb3112df..000000000 --- a/mcxa276-pac/src/can0/mb_group_word026.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD026` reader"] -pub type R = crate::R; -#[doc = "Register `WORD026` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 26 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word026::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word026::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord026Spec; -impl crate::RegisterSpec for MbGroupWord026Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word026::R`](R) reader structure"] -impl crate::Readable for MbGroupWord026Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word026::W`](W) writer structure"] -impl crate::Writable for MbGroupWord026Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD026 to value 0"] -impl crate::Resettable for MbGroupWord026Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word027.rs b/mcxa276-pac/src/can0/mb_group_word027.rs deleted file mode 100644 index a21f55fdb..000000000 --- a/mcxa276-pac/src/can0/mb_group_word027.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD027` reader"] -pub type R = crate::R; -#[doc = "Register `WORD027` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 27 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word027::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word027::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord027Spec; -impl crate::RegisterSpec for MbGroupWord027Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word027::R`](R) reader structure"] -impl crate::Readable for MbGroupWord027Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word027::W`](W) writer structure"] -impl crate::Writable for MbGroupWord027Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD027 to value 0"] -impl crate::Resettable for MbGroupWord027Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word028.rs b/mcxa276-pac/src/can0/mb_group_word028.rs deleted file mode 100644 index 9529fb1c2..000000000 --- a/mcxa276-pac/src/can0/mb_group_word028.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD028` reader"] -pub type R = crate::R; -#[doc = "Register `WORD028` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 28 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word028::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word028::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord028Spec; -impl crate::RegisterSpec for MbGroupWord028Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word028::R`](R) reader structure"] -impl crate::Readable for MbGroupWord028Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word028::W`](W) writer structure"] -impl crate::Writable for MbGroupWord028Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD028 to value 0"] -impl crate::Resettable for MbGroupWord028Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word029.rs b/mcxa276-pac/src/can0/mb_group_word029.rs deleted file mode 100644 index 6a33706dd..000000000 --- a/mcxa276-pac/src/can0/mb_group_word029.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD029` reader"] -pub type R = crate::R; -#[doc = "Register `WORD029` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 29 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word029::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word029::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord029Spec; -impl crate::RegisterSpec for MbGroupWord029Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word029::R`](R) reader structure"] -impl crate::Readable for MbGroupWord029Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word029::W`](W) writer structure"] -impl crate::Writable for MbGroupWord029Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD029 to value 0"] -impl crate::Resettable for MbGroupWord029Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word03.rs b/mcxa276-pac/src/can0/mb_group_word03.rs deleted file mode 100644 index 8cb49f8a0..000000000 --- a/mcxa276-pac/src/can0/mb_group_word03.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD03` reader"] -pub type R = crate::R; -#[doc = "Register `WORD03` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word03::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word03::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord03Spec; -impl crate::RegisterSpec for MbGroupWord03Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word03::R`](R) reader structure"] -impl crate::Readable for MbGroupWord03Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word03::W`](W) writer structure"] -impl crate::Writable for MbGroupWord03Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD03 to value 0"] -impl crate::Resettable for MbGroupWord03Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word030.rs b/mcxa276-pac/src/can0/mb_group_word030.rs deleted file mode 100644 index 46e693ee5..000000000 --- a/mcxa276-pac/src/can0/mb_group_word030.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD030` reader"] -pub type R = crate::R; -#[doc = "Register `WORD030` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 30 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word030::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word030::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord030Spec; -impl crate::RegisterSpec for MbGroupWord030Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word030::R`](R) reader structure"] -impl crate::Readable for MbGroupWord030Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word030::W`](W) writer structure"] -impl crate::Writable for MbGroupWord030Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD030 to value 0"] -impl crate::Resettable for MbGroupWord030Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word031.rs b/mcxa276-pac/src/can0/mb_group_word031.rs deleted file mode 100644 index 4f875a2b6..000000000 --- a/mcxa276-pac/src/can0/mb_group_word031.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD031` reader"] -pub type R = crate::R; -#[doc = "Register `WORD031` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 31 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word031::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word031::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord031Spec; -impl crate::RegisterSpec for MbGroupWord031Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word031::R`](R) reader structure"] -impl crate::Readable for MbGroupWord031Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word031::W`](W) writer structure"] -impl crate::Writable for MbGroupWord031Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD031 to value 0"] -impl crate::Resettable for MbGroupWord031Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word04.rs b/mcxa276-pac/src/can0/mb_group_word04.rs deleted file mode 100644 index 9465fd728..000000000 --- a/mcxa276-pac/src/can0/mb_group_word04.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD04` reader"] -pub type R = crate::R; -#[doc = "Register `WORD04` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word04::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word04::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord04Spec; -impl crate::RegisterSpec for MbGroupWord04Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word04::R`](R) reader structure"] -impl crate::Readable for MbGroupWord04Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word04::W`](W) writer structure"] -impl crate::Writable for MbGroupWord04Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD04 to value 0"] -impl crate::Resettable for MbGroupWord04Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word05.rs b/mcxa276-pac/src/can0/mb_group_word05.rs deleted file mode 100644 index 402d381b2..000000000 --- a/mcxa276-pac/src/can0/mb_group_word05.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD05` reader"] -pub type R = crate::R; -#[doc = "Register `WORD05` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word05::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word05::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord05Spec; -impl crate::RegisterSpec for MbGroupWord05Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word05::R`](R) reader structure"] -impl crate::Readable for MbGroupWord05Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word05::W`](W) writer structure"] -impl crate::Writable for MbGroupWord05Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD05 to value 0"] -impl crate::Resettable for MbGroupWord05Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word06.rs b/mcxa276-pac/src/can0/mb_group_word06.rs deleted file mode 100644 index 232588181..000000000 --- a/mcxa276-pac/src/can0/mb_group_word06.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD06` reader"] -pub type R = crate::R; -#[doc = "Register `WORD06` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word06::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word06::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord06Spec; -impl crate::RegisterSpec for MbGroupWord06Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word06::R`](R) reader structure"] -impl crate::Readable for MbGroupWord06Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word06::W`](W) writer structure"] -impl crate::Writable for MbGroupWord06Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD06 to value 0"] -impl crate::Resettable for MbGroupWord06Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word07.rs b/mcxa276-pac/src/can0/mb_group_word07.rs deleted file mode 100644 index 76ad0aefa..000000000 --- a/mcxa276-pac/src/can0/mb_group_word07.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD07` reader"] -pub type R = crate::R; -#[doc = "Register `WORD07` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word07::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word07::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord07Spec; -impl crate::RegisterSpec for MbGroupWord07Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word07::R`](R) reader structure"] -impl crate::Readable for MbGroupWord07Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word07::W`](W) writer structure"] -impl crate::Writable for MbGroupWord07Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD07 to value 0"] -impl crate::Resettable for MbGroupWord07Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word08.rs b/mcxa276-pac/src/can0/mb_group_word08.rs deleted file mode 100644 index 339da890d..000000000 --- a/mcxa276-pac/src/can0/mb_group_word08.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD08` reader"] -pub type R = crate::R; -#[doc = "Register `WORD08` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word08::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word08::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord08Spec; -impl crate::RegisterSpec for MbGroupWord08Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word08::R`](R) reader structure"] -impl crate::Readable for MbGroupWord08Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word08::W`](W) writer structure"] -impl crate::Writable for MbGroupWord08Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD08 to value 0"] -impl crate::Resettable for MbGroupWord08Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word09.rs b/mcxa276-pac/src/can0/mb_group_word09.rs deleted file mode 100644 index 789d72676..000000000 --- a/mcxa276-pac/src/can0/mb_group_word09.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD09` reader"] -pub type R = crate::R; -#[doc = "Register `WORD09` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_3` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_3` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_2` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_2` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_1` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_1` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_0` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_0` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word09::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word09::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord09Spec; -impl crate::RegisterSpec for MbGroupWord09Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word09::R`](R) reader structure"] -impl crate::Readable for MbGroupWord09Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word09::W`](W) writer structure"] -impl crate::Writable for MbGroupWord09Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD09 to value 0"] -impl crate::Resettable for MbGroupWord09Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word10.rs b/mcxa276-pac/src/can0/mb_group_word10.rs deleted file mode 100644 index e02ef24da..000000000 --- a/mcxa276-pac/src/can0/mb_group_word10.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD10` reader"] -pub type R = crate::R; -#[doc = "Register `WORD10` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 0 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord10Spec; -impl crate::RegisterSpec for MbGroupWord10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word10::R`](R) reader structure"] -impl crate::Readable for MbGroupWord10Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word10::W`](W) writer structure"] -impl crate::Writable for MbGroupWord10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD10 to value 0"] -impl crate::Resettable for MbGroupWord10Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word11.rs b/mcxa276-pac/src/can0/mb_group_word11.rs deleted file mode 100644 index 27eec95aa..000000000 --- a/mcxa276-pac/src/can0/mb_group_word11.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD11` reader"] -pub type R = crate::R; -#[doc = "Register `WORD11` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 1 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord11Spec; -impl crate::RegisterSpec for MbGroupWord11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word11::R`](R) reader structure"] -impl crate::Readable for MbGroupWord11Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word11::W`](W) writer structure"] -impl crate::Writable for MbGroupWord11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD11 to value 0"] -impl crate::Resettable for MbGroupWord11Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word110.rs b/mcxa276-pac/src/can0/mb_group_word110.rs deleted file mode 100644 index 4d5d3ccf6..000000000 --- a/mcxa276-pac/src/can0/mb_group_word110.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD110` reader"] -pub type R = crate::R; -#[doc = "Register `WORD110` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 10 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word110::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word110::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord110Spec; -impl crate::RegisterSpec for MbGroupWord110Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word110::R`](R) reader structure"] -impl crate::Readable for MbGroupWord110Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word110::W`](W) writer structure"] -impl crate::Writable for MbGroupWord110Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD110 to value 0"] -impl crate::Resettable for MbGroupWord110Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word111.rs b/mcxa276-pac/src/can0/mb_group_word111.rs deleted file mode 100644 index ae0b3cf5b..000000000 --- a/mcxa276-pac/src/can0/mb_group_word111.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD111` reader"] -pub type R = crate::R; -#[doc = "Register `WORD111` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 11 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word111::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word111::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord111Spec; -impl crate::RegisterSpec for MbGroupWord111Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word111::R`](R) reader structure"] -impl crate::Readable for MbGroupWord111Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word111::W`](W) writer structure"] -impl crate::Writable for MbGroupWord111Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD111 to value 0"] -impl crate::Resettable for MbGroupWord111Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word112.rs b/mcxa276-pac/src/can0/mb_group_word112.rs deleted file mode 100644 index 82fbe454c..000000000 --- a/mcxa276-pac/src/can0/mb_group_word112.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD112` reader"] -pub type R = crate::R; -#[doc = "Register `WORD112` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 12 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word112::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word112::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord112Spec; -impl crate::RegisterSpec for MbGroupWord112Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word112::R`](R) reader structure"] -impl crate::Readable for MbGroupWord112Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word112::W`](W) writer structure"] -impl crate::Writable for MbGroupWord112Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD112 to value 0"] -impl crate::Resettable for MbGroupWord112Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word113.rs b/mcxa276-pac/src/can0/mb_group_word113.rs deleted file mode 100644 index 1b6f0100d..000000000 --- a/mcxa276-pac/src/can0/mb_group_word113.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD113` reader"] -pub type R = crate::R; -#[doc = "Register `WORD113` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 13 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word113::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word113::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord113Spec; -impl crate::RegisterSpec for MbGroupWord113Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word113::R`](R) reader structure"] -impl crate::Readable for MbGroupWord113Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word113::W`](W) writer structure"] -impl crate::Writable for MbGroupWord113Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD113 to value 0"] -impl crate::Resettable for MbGroupWord113Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word114.rs b/mcxa276-pac/src/can0/mb_group_word114.rs deleted file mode 100644 index 948f94239..000000000 --- a/mcxa276-pac/src/can0/mb_group_word114.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD114` reader"] -pub type R = crate::R; -#[doc = "Register `WORD114` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 14 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word114::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word114::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord114Spec; -impl crate::RegisterSpec for MbGroupWord114Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word114::R`](R) reader structure"] -impl crate::Readable for MbGroupWord114Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word114::W`](W) writer structure"] -impl crate::Writable for MbGroupWord114Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD114 to value 0"] -impl crate::Resettable for MbGroupWord114Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word115.rs b/mcxa276-pac/src/can0/mb_group_word115.rs deleted file mode 100644 index e46fb8c0d..000000000 --- a/mcxa276-pac/src/can0/mb_group_word115.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD115` reader"] -pub type R = crate::R; -#[doc = "Register `WORD115` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 15 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word115::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word115::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord115Spec; -impl crate::RegisterSpec for MbGroupWord115Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word115::R`](R) reader structure"] -impl crate::Readable for MbGroupWord115Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word115::W`](W) writer structure"] -impl crate::Writable for MbGroupWord115Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD115 to value 0"] -impl crate::Resettable for MbGroupWord115Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word116.rs b/mcxa276-pac/src/can0/mb_group_word116.rs deleted file mode 100644 index 30168273c..000000000 --- a/mcxa276-pac/src/can0/mb_group_word116.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD116` reader"] -pub type R = crate::R; -#[doc = "Register `WORD116` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 16 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word116::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word116::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord116Spec; -impl crate::RegisterSpec for MbGroupWord116Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word116::R`](R) reader structure"] -impl crate::Readable for MbGroupWord116Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word116::W`](W) writer structure"] -impl crate::Writable for MbGroupWord116Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD116 to value 0"] -impl crate::Resettable for MbGroupWord116Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word117.rs b/mcxa276-pac/src/can0/mb_group_word117.rs deleted file mode 100644 index 7ee2bc3c7..000000000 --- a/mcxa276-pac/src/can0/mb_group_word117.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD117` reader"] -pub type R = crate::R; -#[doc = "Register `WORD117` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 17 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word117::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word117::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord117Spec; -impl crate::RegisterSpec for MbGroupWord117Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word117::R`](R) reader structure"] -impl crate::Readable for MbGroupWord117Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word117::W`](W) writer structure"] -impl crate::Writable for MbGroupWord117Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD117 to value 0"] -impl crate::Resettable for MbGroupWord117Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word118.rs b/mcxa276-pac/src/can0/mb_group_word118.rs deleted file mode 100644 index 07b5be19e..000000000 --- a/mcxa276-pac/src/can0/mb_group_word118.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD118` reader"] -pub type R = crate::R; -#[doc = "Register `WORD118` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 18 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word118::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word118::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord118Spec; -impl crate::RegisterSpec for MbGroupWord118Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word118::R`](R) reader structure"] -impl crate::Readable for MbGroupWord118Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word118::W`](W) writer structure"] -impl crate::Writable for MbGroupWord118Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD118 to value 0"] -impl crate::Resettable for MbGroupWord118Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word119.rs b/mcxa276-pac/src/can0/mb_group_word119.rs deleted file mode 100644 index 8147c69f1..000000000 --- a/mcxa276-pac/src/can0/mb_group_word119.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD119` reader"] -pub type R = crate::R; -#[doc = "Register `WORD119` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 19 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word119::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word119::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord119Spec; -impl crate::RegisterSpec for MbGroupWord119Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word119::R`](R) reader structure"] -impl crate::Readable for MbGroupWord119Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word119::W`](W) writer structure"] -impl crate::Writable for MbGroupWord119Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD119 to value 0"] -impl crate::Resettable for MbGroupWord119Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word12.rs b/mcxa276-pac/src/can0/mb_group_word12.rs deleted file mode 100644 index 22cc7177c..000000000 --- a/mcxa276-pac/src/can0/mb_group_word12.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD12` reader"] -pub type R = crate::R; -#[doc = "Register `WORD12` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 2 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord12Spec; -impl crate::RegisterSpec for MbGroupWord12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word12::R`](R) reader structure"] -impl crate::Readable for MbGroupWord12Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word12::W`](W) writer structure"] -impl crate::Writable for MbGroupWord12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD12 to value 0"] -impl crate::Resettable for MbGroupWord12Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word120.rs b/mcxa276-pac/src/can0/mb_group_word120.rs deleted file mode 100644 index 2d8093796..000000000 --- a/mcxa276-pac/src/can0/mb_group_word120.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD120` reader"] -pub type R = crate::R; -#[doc = "Register `WORD120` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 20 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word120::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word120::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord120Spec; -impl crate::RegisterSpec for MbGroupWord120Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word120::R`](R) reader structure"] -impl crate::Readable for MbGroupWord120Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word120::W`](W) writer structure"] -impl crate::Writable for MbGroupWord120Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD120 to value 0"] -impl crate::Resettable for MbGroupWord120Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word121.rs b/mcxa276-pac/src/can0/mb_group_word121.rs deleted file mode 100644 index 80914c0db..000000000 --- a/mcxa276-pac/src/can0/mb_group_word121.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD121` reader"] -pub type R = crate::R; -#[doc = "Register `WORD121` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 21 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word121::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word121::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord121Spec; -impl crate::RegisterSpec for MbGroupWord121Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word121::R`](R) reader structure"] -impl crate::Readable for MbGroupWord121Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word121::W`](W) writer structure"] -impl crate::Writable for MbGroupWord121Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD121 to value 0"] -impl crate::Resettable for MbGroupWord121Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word122.rs b/mcxa276-pac/src/can0/mb_group_word122.rs deleted file mode 100644 index fc3f4676d..000000000 --- a/mcxa276-pac/src/can0/mb_group_word122.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD122` reader"] -pub type R = crate::R; -#[doc = "Register `WORD122` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 22 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word122::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word122::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord122Spec; -impl crate::RegisterSpec for MbGroupWord122Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word122::R`](R) reader structure"] -impl crate::Readable for MbGroupWord122Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word122::W`](W) writer structure"] -impl crate::Writable for MbGroupWord122Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD122 to value 0"] -impl crate::Resettable for MbGroupWord122Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word123.rs b/mcxa276-pac/src/can0/mb_group_word123.rs deleted file mode 100644 index 992311d65..000000000 --- a/mcxa276-pac/src/can0/mb_group_word123.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD123` reader"] -pub type R = crate::R; -#[doc = "Register `WORD123` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 23 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word123::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word123::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord123Spec; -impl crate::RegisterSpec for MbGroupWord123Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word123::R`](R) reader structure"] -impl crate::Readable for MbGroupWord123Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word123::W`](W) writer structure"] -impl crate::Writable for MbGroupWord123Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD123 to value 0"] -impl crate::Resettable for MbGroupWord123Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word124.rs b/mcxa276-pac/src/can0/mb_group_word124.rs deleted file mode 100644 index cbd8a2b01..000000000 --- a/mcxa276-pac/src/can0/mb_group_word124.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD124` reader"] -pub type R = crate::R; -#[doc = "Register `WORD124` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 24 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word124::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word124::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord124Spec; -impl crate::RegisterSpec for MbGroupWord124Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word124::R`](R) reader structure"] -impl crate::Readable for MbGroupWord124Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word124::W`](W) writer structure"] -impl crate::Writable for MbGroupWord124Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD124 to value 0"] -impl crate::Resettable for MbGroupWord124Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word125.rs b/mcxa276-pac/src/can0/mb_group_word125.rs deleted file mode 100644 index df56a3b91..000000000 --- a/mcxa276-pac/src/can0/mb_group_word125.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD125` reader"] -pub type R = crate::R; -#[doc = "Register `WORD125` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 25 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word125::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word125::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord125Spec; -impl crate::RegisterSpec for MbGroupWord125Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word125::R`](R) reader structure"] -impl crate::Readable for MbGroupWord125Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word125::W`](W) writer structure"] -impl crate::Writable for MbGroupWord125Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD125 to value 0"] -impl crate::Resettable for MbGroupWord125Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word126.rs b/mcxa276-pac/src/can0/mb_group_word126.rs deleted file mode 100644 index df72b768f..000000000 --- a/mcxa276-pac/src/can0/mb_group_word126.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD126` reader"] -pub type R = crate::R; -#[doc = "Register `WORD126` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 26 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word126::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word126::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord126Spec; -impl crate::RegisterSpec for MbGroupWord126Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word126::R`](R) reader structure"] -impl crate::Readable for MbGroupWord126Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word126::W`](W) writer structure"] -impl crate::Writable for MbGroupWord126Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD126 to value 0"] -impl crate::Resettable for MbGroupWord126Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word127.rs b/mcxa276-pac/src/can0/mb_group_word127.rs deleted file mode 100644 index 60dc29d96..000000000 --- a/mcxa276-pac/src/can0/mb_group_word127.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD127` reader"] -pub type R = crate::R; -#[doc = "Register `WORD127` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 27 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word127::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word127::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord127Spec; -impl crate::RegisterSpec for MbGroupWord127Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word127::R`](R) reader structure"] -impl crate::Readable for MbGroupWord127Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word127::W`](W) writer structure"] -impl crate::Writable for MbGroupWord127Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD127 to value 0"] -impl crate::Resettable for MbGroupWord127Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word128.rs b/mcxa276-pac/src/can0/mb_group_word128.rs deleted file mode 100644 index 6225aeacf..000000000 --- a/mcxa276-pac/src/can0/mb_group_word128.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD128` reader"] -pub type R = crate::R; -#[doc = "Register `WORD128` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 28 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word128::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word128::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord128Spec; -impl crate::RegisterSpec for MbGroupWord128Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word128::R`](R) reader structure"] -impl crate::Readable for MbGroupWord128Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word128::W`](W) writer structure"] -impl crate::Writable for MbGroupWord128Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD128 to value 0"] -impl crate::Resettable for MbGroupWord128Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word129.rs b/mcxa276-pac/src/can0/mb_group_word129.rs deleted file mode 100644 index 40a5dac5b..000000000 --- a/mcxa276-pac/src/can0/mb_group_word129.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD129` reader"] -pub type R = crate::R; -#[doc = "Register `WORD129` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 29 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word129::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word129::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord129Spec; -impl crate::RegisterSpec for MbGroupWord129Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word129::R`](R) reader structure"] -impl crate::Readable for MbGroupWord129Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word129::W`](W) writer structure"] -impl crate::Writable for MbGroupWord129Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD129 to value 0"] -impl crate::Resettable for MbGroupWord129Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word13.rs b/mcxa276-pac/src/can0/mb_group_word13.rs deleted file mode 100644 index f326e476f..000000000 --- a/mcxa276-pac/src/can0/mb_group_word13.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD13` reader"] -pub type R = crate::R; -#[doc = "Register `WORD13` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 3 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord13Spec; -impl crate::RegisterSpec for MbGroupWord13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word13::R`](R) reader structure"] -impl crate::Readable for MbGroupWord13Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word13::W`](W) writer structure"] -impl crate::Writable for MbGroupWord13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD13 to value 0"] -impl crate::Resettable for MbGroupWord13Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word130.rs b/mcxa276-pac/src/can0/mb_group_word130.rs deleted file mode 100644 index 75ca1b4e8..000000000 --- a/mcxa276-pac/src/can0/mb_group_word130.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD130` reader"] -pub type R = crate::R; -#[doc = "Register `WORD130` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 30 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word130::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word130::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord130Spec; -impl crate::RegisterSpec for MbGroupWord130Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word130::R`](R) reader structure"] -impl crate::Readable for MbGroupWord130Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word130::W`](W) writer structure"] -impl crate::Writable for MbGroupWord130Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD130 to value 0"] -impl crate::Resettable for MbGroupWord130Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word131.rs b/mcxa276-pac/src/can0/mb_group_word131.rs deleted file mode 100644 index f164b5517..000000000 --- a/mcxa276-pac/src/can0/mb_group_word131.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD131` reader"] -pub type R = crate::R; -#[doc = "Register `WORD131` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 31 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word131::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word131::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord131Spec; -impl crate::RegisterSpec for MbGroupWord131Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word131::R`](R) reader structure"] -impl crate::Readable for MbGroupWord131Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word131::W`](W) writer structure"] -impl crate::Writable for MbGroupWord131Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD131 to value 0"] -impl crate::Resettable for MbGroupWord131Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word14.rs b/mcxa276-pac/src/can0/mb_group_word14.rs deleted file mode 100644 index dc26547f5..000000000 --- a/mcxa276-pac/src/can0/mb_group_word14.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD14` reader"] -pub type R = crate::R; -#[doc = "Register `WORD14` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 4 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord14Spec; -impl crate::RegisterSpec for MbGroupWord14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word14::R`](R) reader structure"] -impl crate::Readable for MbGroupWord14Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word14::W`](W) writer structure"] -impl crate::Writable for MbGroupWord14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD14 to value 0"] -impl crate::Resettable for MbGroupWord14Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word15.rs b/mcxa276-pac/src/can0/mb_group_word15.rs deleted file mode 100644 index 03bfed5f4..000000000 --- a/mcxa276-pac/src/can0/mb_group_word15.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD15` reader"] -pub type R = crate::R; -#[doc = "Register `WORD15` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 5 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord15Spec; -impl crate::RegisterSpec for MbGroupWord15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word15::R`](R) reader structure"] -impl crate::Readable for MbGroupWord15Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word15::W`](W) writer structure"] -impl crate::Writable for MbGroupWord15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD15 to value 0"] -impl crate::Resettable for MbGroupWord15Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word16.rs b/mcxa276-pac/src/can0/mb_group_word16.rs deleted file mode 100644 index aa217c012..000000000 --- a/mcxa276-pac/src/can0/mb_group_word16.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD16` reader"] -pub type R = crate::R; -#[doc = "Register `WORD16` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 6 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord16Spec; -impl crate::RegisterSpec for MbGroupWord16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word16::R`](R) reader structure"] -impl crate::Readable for MbGroupWord16Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word16::W`](W) writer structure"] -impl crate::Writable for MbGroupWord16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD16 to value 0"] -impl crate::Resettable for MbGroupWord16Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word17.rs b/mcxa276-pac/src/can0/mb_group_word17.rs deleted file mode 100644 index 379218a35..000000000 --- a/mcxa276-pac/src/can0/mb_group_word17.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD17` reader"] -pub type R = crate::R; -#[doc = "Register `WORD17` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 7 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord17Spec; -impl crate::RegisterSpec for MbGroupWord17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word17::R`](R) reader structure"] -impl crate::Readable for MbGroupWord17Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word17::W`](W) writer structure"] -impl crate::Writable for MbGroupWord17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD17 to value 0"] -impl crate::Resettable for MbGroupWord17Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word18.rs b/mcxa276-pac/src/can0/mb_group_word18.rs deleted file mode 100644 index 4149ab04f..000000000 --- a/mcxa276-pac/src/can0/mb_group_word18.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD18` reader"] -pub type R = crate::R; -#[doc = "Register `WORD18` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 8 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord18Spec; -impl crate::RegisterSpec for MbGroupWord18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word18::R`](R) reader structure"] -impl crate::Readable for MbGroupWord18Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word18::W`](W) writer structure"] -impl crate::Writable for MbGroupWord18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD18 to value 0"] -impl crate::Resettable for MbGroupWord18Spec {} diff --git a/mcxa276-pac/src/can0/mb_group_word19.rs b/mcxa276-pac/src/can0/mb_group_word19.rs deleted file mode 100644 index dd0e33cde..000000000 --- a/mcxa276-pac/src/can0/mb_group_word19.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `WORD19` reader"] -pub type R = crate::R; -#[doc = "Register `WORD19` writer"] -pub type W = crate::W; -#[doc = "Field `DATA_BYTE_7` reader - Data byte 0 of Rx/Tx frame."] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_7` writer - Data byte 0 of Rx/Tx frame."] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_6` reader - Data byte 1 of Rx/Tx frame."] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_6` writer - Data byte 1 of Rx/Tx frame."] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_5` reader - Data byte 2 of Rx/Tx frame."] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_5` writer - Data byte 2 of Rx/Tx frame."] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA_BYTE_4` reader - Data byte 3 of Rx/Tx frame."] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `DATA_BYTE_4` writer - Data byte 3 of Rx/Tx frame."] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 0 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 1 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 2 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 3 of Rx/Tx frame."] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Message Buffer 9 WORD1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mb_group_word19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mb_group_word19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MbGroupWord19Spec; -impl crate::RegisterSpec for MbGroupWord19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mb_group_word19::R`](R) reader structure"] -impl crate::Readable for MbGroupWord19Spec {} -#[doc = "`write(|w| ..)` method takes [`mb_group_word19::W`](W) writer structure"] -impl crate::Writable for MbGroupWord19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WORD19 to value 0"] -impl crate::Resettable for MbGroupWord19Spec {} diff --git a/mcxa276-pac/src/can0/mcr.rs b/mcxa276-pac/src/can0/mcr.rs deleted file mode 100644 index 75bac1515..000000000 --- a/mcxa276-pac/src/can0/mcr.rs +++ /dev/null @@ -1,1390 +0,0 @@ -#[doc = "Register `MCR` reader"] -pub type R = crate::R; -#[doc = "Register `MCR` writer"] -pub type W = crate::W; -#[doc = "Field `MAXMB` reader - Number of the Last Message Buffer"] -pub type MaxmbR = crate::FieldReader; -#[doc = "Field `MAXMB` writer - Number of the Last Message Buffer"] -pub type MaxmbW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "ID Acceptance Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Idam { - #[doc = "0: Format A: One full ID (standard and extended) per ID filter table element."] - OneFullId = 0, - #[doc = "1: Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element."] - TwoFullId = 1, - #[doc = "2: Format C: Four partial 8-bit standard IDs per ID filter table element."] - FourPartialId = 2, - #[doc = "3: Format D: All frames rejected."] - AllFramesRejected = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Idam) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Idam { - type Ux = u8; -} -impl crate::IsEnum for Idam {} -#[doc = "Field `IDAM` reader - ID Acceptance Mode"] -pub type IdamR = crate::FieldReader; -impl IdamR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Idam { - match self.bits { - 0 => Idam::OneFullId, - 1 => Idam::TwoFullId, - 2 => Idam::FourPartialId, - 3 => Idam::AllFramesRejected, - _ => unreachable!(), - } - } - #[doc = "Format A: One full ID (standard and extended) per ID filter table element."] - #[inline(always)] - pub fn is_one_full_id(&self) -> bool { - *self == Idam::OneFullId - } - #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element."] - #[inline(always)] - pub fn is_two_full_id(&self) -> bool { - *self == Idam::TwoFullId - } - #[doc = "Format C: Four partial 8-bit standard IDs per ID filter table element."] - #[inline(always)] - pub fn is_four_partial_id(&self) -> bool { - *self == Idam::FourPartialId - } - #[doc = "Format D: All frames rejected."] - #[inline(always)] - pub fn is_all_frames_rejected(&self) -> bool { - *self == Idam::AllFramesRejected - } -} -#[doc = "Field `IDAM` writer - ID Acceptance Mode"] -pub type IdamW<'a, REG> = crate::FieldWriter<'a, REG, 2, Idam, crate::Safe>; -impl<'a, REG> IdamW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Format A: One full ID (standard and extended) per ID filter table element."] - #[inline(always)] - pub fn one_full_id(self) -> &'a mut crate::W { - self.variant(Idam::OneFullId) - } - #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element."] - #[inline(always)] - pub fn two_full_id(self) -> &'a mut crate::W { - self.variant(Idam::TwoFullId) - } - #[doc = "Format C: Four partial 8-bit standard IDs per ID filter table element."] - #[inline(always)] - pub fn four_partial_id(self) -> &'a mut crate::W { - self.variant(Idam::FourPartialId) - } - #[doc = "Format D: All frames rejected."] - #[inline(always)] - pub fn all_frames_rejected(self) -> &'a mut crate::W { - self.variant(Idam::AllFramesRejected) - } -} -#[doc = "CAN FD Operation Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fden { - #[doc = "0: Disable"] - CanFdDisabled = 0, - #[doc = "1: Enable"] - CanFdEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fden) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FDEN` reader - CAN FD Operation Enable"] -pub type FdenR = crate::BitReader; -impl FdenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fden { - match self.bits { - false => Fden::CanFdDisabled, - true => Fden::CanFdEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_can_fd_disabled(&self) -> bool { - *self == Fden::CanFdDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_can_fd_enabled(&self) -> bool { - *self == Fden::CanFdEnabled - } -} -#[doc = "Field `FDEN` writer - CAN FD Operation Enable"] -pub type FdenW<'a, REG> = crate::BitWriter<'a, REG, Fden>; -impl<'a, REG> FdenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn can_fd_disabled(self) -> &'a mut crate::W { - self.variant(Fden::CanFdDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn can_fd_enabled(self) -> &'a mut crate::W { - self.variant(Fden::CanFdEnabled) - } -} -#[doc = "Abort Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aen { - #[doc = "0: Disabled"] - AbortDisabled = 0, - #[doc = "1: Enabled"] - AbortEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AEN` reader - Abort Enable"] -pub type AenR = crate::BitReader; -impl AenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aen { - match self.bits { - false => Aen::AbortDisabled, - true => Aen::AbortEnabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_abort_disabled(&self) -> bool { - *self == Aen::AbortDisabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_abort_enabled(&self) -> bool { - *self == Aen::AbortEnabled - } -} -#[doc = "Field `AEN` writer - Abort Enable"] -pub type AenW<'a, REG> = crate::BitWriter<'a, REG, Aen>; -impl<'a, REG> AenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn abort_disabled(self) -> &'a mut crate::W { - self.variant(Aen::AbortDisabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn abort_enabled(self) -> &'a mut crate::W { - self.variant(Aen::AbortEnabled) - } -} -#[doc = "Local Priority Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lprioen { - #[doc = "0: Disable"] - LocalPriorityDisabled = 0, - #[doc = "1: Enable"] - LocalPriorityEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lprioen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPRIOEN` reader - Local Priority Enable"] -pub type LprioenR = crate::BitReader; -impl LprioenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lprioen { - match self.bits { - false => Lprioen::LocalPriorityDisabled, - true => Lprioen::LocalPriorityEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_local_priority_disabled(&self) -> bool { - *self == Lprioen::LocalPriorityDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_local_priority_enabled(&self) -> bool { - *self == Lprioen::LocalPriorityEnabled - } -} -#[doc = "Field `LPRIOEN` writer - Local Priority Enable"] -pub type LprioenW<'a, REG> = crate::BitWriter<'a, REG, Lprioen>; -impl<'a, REG> LprioenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn local_priority_disabled(self) -> &'a mut crate::W { - self.variant(Lprioen::LocalPriorityDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn local_priority_enabled(self) -> &'a mut crate::W { - self.variant(Lprioen::LocalPriorityEnabled) - } -} -#[doc = "Pretended Networking Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PnetEn { - #[doc = "0: Disable"] - PnDisabled = 0, - #[doc = "1: Enable"] - PnEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PnetEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PNET_EN` reader - Pretended Networking Enable"] -pub type PnetEnR = crate::BitReader; -impl PnetEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PnetEn { - match self.bits { - false => PnetEn::PnDisabled, - true => PnetEn::PnEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_pn_disabled(&self) -> bool { - *self == PnetEn::PnDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_pn_enabled(&self) -> bool { - *self == PnetEn::PnEnabled - } -} -#[doc = "Field `PNET_EN` writer - Pretended Networking Enable"] -pub type PnetEnW<'a, REG> = crate::BitWriter<'a, REG, PnetEn>; -impl<'a, REG> PnetEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn pn_disabled(self) -> &'a mut crate::W { - self.variant(PnetEn::PnDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn pn_enabled(self) -> &'a mut crate::W { - self.variant(PnetEn::PnEnabled) - } -} -#[doc = "DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dma { - #[doc = "0: Disable"] - Id1 = 0, - #[doc = "1: Enable"] - Id2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dma) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMA` reader - DMA Enable"] -pub type DmaR = crate::BitReader; -impl DmaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dma { - match self.bits { - false => Dma::Id1, - true => Dma::Id2, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Dma::Id1 - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_id2(&self) -> bool { - *self == Dma::Id2 - } -} -#[doc = "Field `DMA` writer - DMA Enable"] -pub type DmaW<'a, REG> = crate::BitWriter<'a, REG, Dma>; -impl<'a, REG> DmaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn id1(self) -> &'a mut crate::W { - self.variant(Dma::Id1) - } - #[doc = "Enable"] - #[inline(always)] - pub fn id2(self) -> &'a mut crate::W { - self.variant(Dma::Id2) - } -} -#[doc = "Individual RX Masking and Queue Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Irmq { - #[doc = "0: Disable"] - IndividualRxMaskingDisabled = 0, - #[doc = "1: Enable"] - IndividualRxMaskingEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Irmq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IRMQ` reader - Individual RX Masking and Queue Enable"] -pub type IrmqR = crate::BitReader; -impl IrmqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Irmq { - match self.bits { - false => Irmq::IndividualRxMaskingDisabled, - true => Irmq::IndividualRxMaskingEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_individual_rx_masking_disabled(&self) -> bool { - *self == Irmq::IndividualRxMaskingDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_individual_rx_masking_enabled(&self) -> bool { - *self == Irmq::IndividualRxMaskingEnabled - } -} -#[doc = "Field `IRMQ` writer - Individual RX Masking and Queue Enable"] -pub type IrmqW<'a, REG> = crate::BitWriter<'a, REG, Irmq>; -impl<'a, REG> IrmqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn individual_rx_masking_disabled(self) -> &'a mut crate::W { - self.variant(Irmq::IndividualRxMaskingDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn individual_rx_masking_enabled(self) -> &'a mut crate::W { - self.variant(Irmq::IndividualRxMaskingEnabled) - } -} -#[doc = "Self-Reception Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Srxdis { - #[doc = "0: Enable"] - SelfReceptionEnabled = 0, - #[doc = "1: Disable"] - SelfReceptionDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Srxdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRXDIS` reader - Self-Reception Disable"] -pub type SrxdisR = crate::BitReader; -impl SrxdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Srxdis { - match self.bits { - false => Srxdis::SelfReceptionEnabled, - true => Srxdis::SelfReceptionDisabled, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_self_reception_enabled(&self) -> bool { - *self == Srxdis::SelfReceptionEnabled - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_self_reception_disabled(&self) -> bool { - *self == Srxdis::SelfReceptionDisabled - } -} -#[doc = "Field `SRXDIS` writer - Self-Reception Disable"] -pub type SrxdisW<'a, REG> = crate::BitWriter<'a, REG, Srxdis>; -impl<'a, REG> SrxdisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn self_reception_enabled(self) -> &'a mut crate::W { - self.variant(Srxdis::SelfReceptionEnabled) - } - #[doc = "Disable"] - #[inline(always)] - pub fn self_reception_disabled(self) -> &'a mut crate::W { - self.variant(Srxdis::SelfReceptionDisabled) - } -} -#[doc = "Doze Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Doze { - #[doc = "0: Disable"] - LowPowerDozeDisabled = 0, - #[doc = "1: Enable"] - LowPowerDozeEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Doze) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DOZE` reader - Doze Mode Enable"] -pub type DozeR = crate::BitReader; -impl DozeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Doze { - match self.bits { - false => Doze::LowPowerDozeDisabled, - true => Doze::LowPowerDozeEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_low_power_doze_disabled(&self) -> bool { - *self == Doze::LowPowerDozeDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_low_power_doze_enabled(&self) -> bool { - *self == Doze::LowPowerDozeEnabled - } -} -#[doc = "Field `DOZE` writer - Doze Mode Enable"] -pub type DozeW<'a, REG> = crate::BitWriter<'a, REG, Doze>; -impl<'a, REG> DozeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn low_power_doze_disabled(self) -> &'a mut crate::W { - self.variant(Doze::LowPowerDozeDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn low_power_doze_enabled(self) -> &'a mut crate::W { - self.variant(Doze::LowPowerDozeEnabled) - } -} -#[doc = "Wake-Up Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Waksrc { - #[doc = "0: No filter applied"] - UnfilteredRxInput = 0, - #[doc = "1: Filter applied"] - FilteredRxInput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Waksrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAKSRC` reader - Wake-Up Source"] -pub type WaksrcR = crate::BitReader; -impl WaksrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Waksrc { - match self.bits { - false => Waksrc::UnfilteredRxInput, - true => Waksrc::FilteredRxInput, - } - } - #[doc = "No filter applied"] - #[inline(always)] - pub fn is_unfiltered_rx_input(&self) -> bool { - *self == Waksrc::UnfilteredRxInput - } - #[doc = "Filter applied"] - #[inline(always)] - pub fn is_filtered_rx_input(&self) -> bool { - *self == Waksrc::FilteredRxInput - } -} -#[doc = "Field `WAKSRC` writer - Wake-Up Source"] -pub type WaksrcW<'a, REG> = crate::BitWriter<'a, REG, Waksrc>; -impl<'a, REG> WaksrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No filter applied"] - #[inline(always)] - pub fn unfiltered_rx_input(self) -> &'a mut crate::W { - self.variant(Waksrc::UnfilteredRxInput) - } - #[doc = "Filter applied"] - #[inline(always)] - pub fn filtered_rx_input(self) -> &'a mut crate::W { - self.variant(Waksrc::FilteredRxInput) - } -} -#[doc = "Low-Power Mode Acknowledge\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpmack { - #[doc = "0: Not in a low-power mode"] - LowPowerNo = 0, - #[doc = "1: In a low-power mode"] - LowPowerYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpmack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPMACK` reader - Low-Power Mode Acknowledge"] -pub type LpmackR = crate::BitReader; -impl LpmackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpmack { - match self.bits { - false => Lpmack::LowPowerNo, - true => Lpmack::LowPowerYes, - } - } - #[doc = "Not in a low-power mode"] - #[inline(always)] - pub fn is_low_power_no(&self) -> bool { - *self == Lpmack::LowPowerNo - } - #[doc = "In a low-power mode"] - #[inline(always)] - pub fn is_low_power_yes(&self) -> bool { - *self == Lpmack::LowPowerYes - } -} -#[doc = "Warning Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wrnen { - #[doc = "0: Disable"] - TwrnintRwrnintInactive = 0, - #[doc = "1: Enable"] - TwrnintRwrnintActive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wrnen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WRNEN` reader - Warning Interrupt Enable"] -pub type WrnenR = crate::BitReader; -impl WrnenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wrnen { - match self.bits { - false => Wrnen::TwrnintRwrnintInactive, - true => Wrnen::TwrnintRwrnintActive, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_twrnint_rwrnint_inactive(&self) -> bool { - *self == Wrnen::TwrnintRwrnintInactive - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_twrnint_rwrnint_active(&self) -> bool { - *self == Wrnen::TwrnintRwrnintActive - } -} -#[doc = "Field `WRNEN` writer - Warning Interrupt Enable"] -pub type WrnenW<'a, REG> = crate::BitWriter<'a, REG, Wrnen>; -impl<'a, REG> WrnenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn twrnint_rwrnint_inactive(self) -> &'a mut crate::W { - self.variant(Wrnen::TwrnintRwrnintInactive) - } - #[doc = "Enable"] - #[inline(always)] - pub fn twrnint_rwrnint_active(self) -> &'a mut crate::W { - self.variant(Wrnen::TwrnintRwrnintActive) - } -} -#[doc = "Self Wake-up\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slfwak { - #[doc = "0: Disable"] - SelfWakeupDisabled = 0, - #[doc = "1: Enable"] - SelfWakeupEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slfwak) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLFWAK` reader - Self Wake-up"] -pub type SlfwakR = crate::BitReader; -impl SlfwakR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slfwak { - match self.bits { - false => Slfwak::SelfWakeupDisabled, - true => Slfwak::SelfWakeupEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_self_wakeup_disabled(&self) -> bool { - *self == Slfwak::SelfWakeupDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_self_wakeup_enabled(&self) -> bool { - *self == Slfwak::SelfWakeupEnabled - } -} -#[doc = "Field `SLFWAK` writer - Self Wake-up"] -pub type SlfwakW<'a, REG> = crate::BitWriter<'a, REG, Slfwak>; -impl<'a, REG> SlfwakW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn self_wakeup_disabled(self) -> &'a mut crate::W { - self.variant(Slfwak::SelfWakeupDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn self_wakeup_enabled(self) -> &'a mut crate::W { - self.variant(Slfwak::SelfWakeupEnabled) - } -} -#[doc = "Supervisor Mode\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Supv { - #[doc = "0: User mode"] - Id1 = 0, - #[doc = "1: Supervisor mode"] - Id2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Supv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUPV` reader - Supervisor Mode"] -pub type SupvR = crate::BitReader; -impl SupvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Supv { - match self.bits { - false => Supv::Id1, - true => Supv::Id2, - } - } - #[doc = "User mode"] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Supv::Id1 - } - #[doc = "Supervisor mode"] - #[inline(always)] - pub fn is_id2(&self) -> bool { - *self == Supv::Id2 - } -} -#[doc = "Field `SUPV` writer - Supervisor Mode"] -pub type SupvW<'a, REG> = crate::BitWriter<'a, REG, Supv>; -impl<'a, REG> SupvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "User mode"] - #[inline(always)] - pub fn id1(self) -> &'a mut crate::W { - self.variant(Supv::Id1) - } - #[doc = "Supervisor mode"] - #[inline(always)] - pub fn id2(self) -> &'a mut crate::W { - self.variant(Supv::Id2) - } -} -#[doc = "Freeze Mode Acknowledge\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frzack { - #[doc = "0: Not in Freeze mode, prescaler running."] - FreezeModeNo = 0, - #[doc = "1: In Freeze mode, prescaler stopped."] - FreezeModeYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frzack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRZACK` reader - Freeze Mode Acknowledge"] -pub type FrzackR = crate::BitReader; -impl FrzackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frzack { - match self.bits { - false => Frzack::FreezeModeNo, - true => Frzack::FreezeModeYes, - } - } - #[doc = "Not in Freeze mode, prescaler running."] - #[inline(always)] - pub fn is_freeze_mode_no(&self) -> bool { - *self == Frzack::FreezeModeNo - } - #[doc = "In Freeze mode, prescaler stopped."] - #[inline(always)] - pub fn is_freeze_mode_yes(&self) -> bool { - *self == Frzack::FreezeModeYes - } -} -#[doc = "Soft Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Softrst { - #[doc = "0: No reset"] - SoftrstNoResetRequest = 0, - #[doc = "1: Soft reset affects reset registers"] - SoftrstResetRegisters = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Softrst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOFTRST` reader - Soft Reset"] -pub type SoftrstR = crate::BitReader; -impl SoftrstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Softrst { - match self.bits { - false => Softrst::SoftrstNoResetRequest, - true => Softrst::SoftrstResetRegisters, - } - } - #[doc = "No reset"] - #[inline(always)] - pub fn is_softrst_no_reset_request(&self) -> bool { - *self == Softrst::SoftrstNoResetRequest - } - #[doc = "Soft reset affects reset registers"] - #[inline(always)] - pub fn is_softrst_reset_registers(&self) -> bool { - *self == Softrst::SoftrstResetRegisters - } -} -#[doc = "Field `SOFTRST` writer - Soft Reset"] -pub type SoftrstW<'a, REG> = crate::BitWriter<'a, REG, Softrst>; -impl<'a, REG> SoftrstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No reset"] - #[inline(always)] - pub fn softrst_no_reset_request(self) -> &'a mut crate::W { - self.variant(Softrst::SoftrstNoResetRequest) - } - #[doc = "Soft reset affects reset registers"] - #[inline(always)] - pub fn softrst_reset_registers(self) -> &'a mut crate::W { - self.variant(Softrst::SoftrstResetRegisters) - } -} -#[doc = "Wake-up Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wakmsk { - #[doc = "0: Disabled"] - WakeupInterruptDisabled = 0, - #[doc = "1: Enabled"] - WakeupInterruptEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wakmsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAKMSK` reader - Wake-up Interrupt Mask"] -pub type WakmskR = crate::BitReader; -impl WakmskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wakmsk { - match self.bits { - false => Wakmsk::WakeupInterruptDisabled, - true => Wakmsk::WakeupInterruptEnabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_wakeup_interrupt_disabled(&self) -> bool { - *self == Wakmsk::WakeupInterruptDisabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_wakeup_interrupt_enabled(&self) -> bool { - *self == Wakmsk::WakeupInterruptEnabled - } -} -#[doc = "Field `WAKMSK` writer - Wake-up Interrupt Mask"] -pub type WakmskW<'a, REG> = crate::BitWriter<'a, REG, Wakmsk>; -impl<'a, REG> WakmskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn wakeup_interrupt_disabled(self) -> &'a mut crate::W { - self.variant(Wakmsk::WakeupInterruptDisabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn wakeup_interrupt_enabled(self) -> &'a mut crate::W { - self.variant(Wakmsk::WakeupInterruptEnabled) - } -} -#[doc = "FlexCAN Not Ready\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Notrdy { - #[doc = "0: FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode."] - Id1 = 0, - #[doc = "1: FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode."] - Id2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Notrdy) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOTRDY` reader - FlexCAN Not Ready"] -pub type NotrdyR = crate::BitReader; -impl NotrdyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Notrdy { - match self.bits { - false => Notrdy::Id1, - true => Notrdy::Id2, - } - } - #[doc = "FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode."] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Notrdy::Id1 - } - #[doc = "FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode."] - #[inline(always)] - pub fn is_id2(&self) -> bool { - *self == Notrdy::Id2 - } -} -#[doc = "Halt FlexCAN\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: No request"] - HaltDisable = 0, - #[doc = "1: Enter Freeze mode, if MCR\\[FRZ\\] = 1."] - HaltEnable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt FlexCAN"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::HaltDisable, - true => Halt::HaltEnable, - } - } - #[doc = "No request"] - #[inline(always)] - pub fn is_halt_disable(&self) -> bool { - *self == Halt::HaltDisable - } - #[doc = "Enter Freeze mode, if MCR\\[FRZ\\] = 1."] - #[inline(always)] - pub fn is_halt_enable(&self) -> bool { - *self == Halt::HaltEnable - } -} -#[doc = "Field `HALT` writer - Halt FlexCAN"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No request"] - #[inline(always)] - pub fn halt_disable(self) -> &'a mut crate::W { - self.variant(Halt::HaltDisable) - } - #[doc = "Enter Freeze mode, if MCR\\[FRZ\\] = 1."] - #[inline(always)] - pub fn halt_enable(self) -> &'a mut crate::W { - self.variant(Halt::HaltEnable) - } -} -#[doc = "Legacy RX FIFO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rfen { - #[doc = "0: Disable"] - Id1 = 0, - #[doc = "1: Enable"] - Id2 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rfen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RFEN` reader - Legacy RX FIFO Enable"] -pub type RfenR = crate::BitReader; -impl RfenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rfen { - match self.bits { - false => Rfen::Id1, - true => Rfen::Id2, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_id1(&self) -> bool { - *self == Rfen::Id1 - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_id2(&self) -> bool { - *self == Rfen::Id2 - } -} -#[doc = "Field `RFEN` writer - Legacy RX FIFO Enable"] -pub type RfenW<'a, REG> = crate::BitWriter<'a, REG, Rfen>; -impl<'a, REG> RfenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn id1(self) -> &'a mut crate::W { - self.variant(Rfen::Id1) - } - #[doc = "Enable"] - #[inline(always)] - pub fn id2(self) -> &'a mut crate::W { - self.variant(Rfen::Id2) - } -} -#[doc = "Freeze Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frz { - #[doc = "0: Disable"] - FreezeModeDisabled = 0, - #[doc = "1: Enable"] - FreezeModeEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frz) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRZ` reader - Freeze Enable"] -pub type FrzR = crate::BitReader; -impl FrzR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frz { - match self.bits { - false => Frz::FreezeModeDisabled, - true => Frz::FreezeModeEnabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_freeze_mode_disabled(&self) -> bool { - *self == Frz::FreezeModeDisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_freeze_mode_enabled(&self) -> bool { - *self == Frz::FreezeModeEnabled - } -} -#[doc = "Field `FRZ` writer - Freeze Enable"] -pub type FrzW<'a, REG> = crate::BitWriter<'a, REG, Frz>; -impl<'a, REG> FrzW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn freeze_mode_disabled(self) -> &'a mut crate::W { - self.variant(Frz::FreezeModeDisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn freeze_mode_enabled(self) -> &'a mut crate::W { - self.variant(Frz::FreezeModeEnabled) - } -} -#[doc = "Module Disable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mdis { - #[doc = "0: Enable"] - FlexcanEnabled = 0, - #[doc = "1: Disable"] - FlexcanDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MDIS` reader - Module Disable"] -pub type MdisR = crate::BitReader; -impl MdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mdis { - match self.bits { - false => Mdis::FlexcanEnabled, - true => Mdis::FlexcanDisabled, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_flexcan_enabled(&self) -> bool { - *self == Mdis::FlexcanEnabled - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_flexcan_disabled(&self) -> bool { - *self == Mdis::FlexcanDisabled - } -} -#[doc = "Field `MDIS` writer - Module Disable"] -pub type MdisW<'a, REG> = crate::BitWriter<'a, REG, Mdis>; -impl<'a, REG> MdisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn flexcan_enabled(self) -> &'a mut crate::W { - self.variant(Mdis::FlexcanEnabled) - } - #[doc = "Disable"] - #[inline(always)] - pub fn flexcan_disabled(self) -> &'a mut crate::W { - self.variant(Mdis::FlexcanDisabled) - } -} -impl R { - #[doc = "Bits 0:6 - Number of the Last Message Buffer"] - #[inline(always)] - pub fn maxmb(&self) -> MaxmbR { - MaxmbR::new((self.bits & 0x7f) as u8) - } - #[doc = "Bits 8:9 - ID Acceptance Mode"] - #[inline(always)] - pub fn idam(&self) -> IdamR { - IdamR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 11 - CAN FD Operation Enable"] - #[inline(always)] - pub fn fden(&self) -> FdenR { - FdenR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Abort Enable"] - #[inline(always)] - pub fn aen(&self) -> AenR { - AenR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Local Priority Enable"] - #[inline(always)] - pub fn lprioen(&self) -> LprioenR { - LprioenR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Pretended Networking Enable"] - #[inline(always)] - pub fn pnet_en(&self) -> PnetEnR { - PnetEnR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - DMA Enable"] - #[inline(always)] - pub fn dma(&self) -> DmaR { - DmaR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Individual RX Masking and Queue Enable"] - #[inline(always)] - pub fn irmq(&self) -> IrmqR { - IrmqR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Self-Reception Disable"] - #[inline(always)] - pub fn srxdis(&self) -> SrxdisR { - SrxdisR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Doze Mode Enable"] - #[inline(always)] - pub fn doze(&self) -> DozeR { - DozeR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Wake-Up Source"] - #[inline(always)] - pub fn waksrc(&self) -> WaksrcR { - WaksrcR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Low-Power Mode Acknowledge"] - #[inline(always)] - pub fn lpmack(&self) -> LpmackR { - LpmackR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Warning Interrupt Enable"] - #[inline(always)] - pub fn wrnen(&self) -> WrnenR { - WrnenR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Self Wake-up"] - #[inline(always)] - pub fn slfwak(&self) -> SlfwakR { - SlfwakR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Supervisor Mode"] - #[inline(always)] - pub fn supv(&self) -> SupvR { - SupvR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Freeze Mode Acknowledge"] - #[inline(always)] - pub fn frzack(&self) -> FrzackR { - FrzackR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Soft Reset"] - #[inline(always)] - pub fn softrst(&self) -> SoftrstR { - SoftrstR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Wake-up Interrupt Mask"] - #[inline(always)] - pub fn wakmsk(&self) -> WakmskR { - WakmskR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - FlexCAN Not Ready"] - #[inline(always)] - pub fn notrdy(&self) -> NotrdyR { - NotrdyR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Halt FlexCAN"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Legacy RX FIFO Enable"] - #[inline(always)] - pub fn rfen(&self) -> RfenR { - RfenR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Freeze Enable"] - #[inline(always)] - pub fn frz(&self) -> FrzR { - FrzR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Module Disable"] - #[inline(always)] - pub fn mdis(&self) -> MdisR { - MdisR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:6 - Number of the Last Message Buffer"] - #[inline(always)] - pub fn maxmb(&mut self) -> MaxmbW { - MaxmbW::new(self, 0) - } - #[doc = "Bits 8:9 - ID Acceptance Mode"] - #[inline(always)] - pub fn idam(&mut self) -> IdamW { - IdamW::new(self, 8) - } - #[doc = "Bit 11 - CAN FD Operation Enable"] - #[inline(always)] - pub fn fden(&mut self) -> FdenW { - FdenW::new(self, 11) - } - #[doc = "Bit 12 - Abort Enable"] - #[inline(always)] - pub fn aen(&mut self) -> AenW { - AenW::new(self, 12) - } - #[doc = "Bit 13 - Local Priority Enable"] - #[inline(always)] - pub fn lprioen(&mut self) -> LprioenW { - LprioenW::new(self, 13) - } - #[doc = "Bit 14 - Pretended Networking Enable"] - #[inline(always)] - pub fn pnet_en(&mut self) -> PnetEnW { - PnetEnW::new(self, 14) - } - #[doc = "Bit 15 - DMA Enable"] - #[inline(always)] - pub fn dma(&mut self) -> DmaW { - DmaW::new(self, 15) - } - #[doc = "Bit 16 - Individual RX Masking and Queue Enable"] - #[inline(always)] - pub fn irmq(&mut self) -> IrmqW { - IrmqW::new(self, 16) - } - #[doc = "Bit 17 - Self-Reception Disable"] - #[inline(always)] - pub fn srxdis(&mut self) -> SrxdisW { - SrxdisW::new(self, 17) - } - #[doc = "Bit 18 - Doze Mode Enable"] - #[inline(always)] - pub fn doze(&mut self) -> DozeW { - DozeW::new(self, 18) - } - #[doc = "Bit 19 - Wake-Up Source"] - #[inline(always)] - pub fn waksrc(&mut self) -> WaksrcW { - WaksrcW::new(self, 19) - } - #[doc = "Bit 21 - Warning Interrupt Enable"] - #[inline(always)] - pub fn wrnen(&mut self) -> WrnenW { - WrnenW::new(self, 21) - } - #[doc = "Bit 22 - Self Wake-up"] - #[inline(always)] - pub fn slfwak(&mut self) -> SlfwakW { - SlfwakW::new(self, 22) - } - #[doc = "Bit 23 - Supervisor Mode"] - #[inline(always)] - pub fn supv(&mut self) -> SupvW { - SupvW::new(self, 23) - } - #[doc = "Bit 25 - Soft Reset"] - #[inline(always)] - pub fn softrst(&mut self) -> SoftrstW { - SoftrstW::new(self, 25) - } - #[doc = "Bit 26 - Wake-up Interrupt Mask"] - #[inline(always)] - pub fn wakmsk(&mut self) -> WakmskW { - WakmskW::new(self, 26) - } - #[doc = "Bit 28 - Halt FlexCAN"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 28) - } - #[doc = "Bit 29 - Legacy RX FIFO Enable"] - #[inline(always)] - pub fn rfen(&mut self) -> RfenW { - RfenW::new(self, 29) - } - #[doc = "Bit 30 - Freeze Enable"] - #[inline(always)] - pub fn frz(&mut self) -> FrzW { - FrzW::new(self, 30) - } - #[doc = "Bit 31 - Module Disable"] - #[inline(always)] - pub fn mdis(&mut self) -> MdisW { - MdisW::new(self, 31) - } -} -#[doc = "Module Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct McrSpec; -impl crate::RegisterSpec for McrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] -impl crate::Readable for McrSpec {} -#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] -impl crate::Writable for McrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCR to value 0xd890_000f"] -impl crate::Resettable for McrSpec { - const RESET_VALUE: u32 = 0xd890_000f; -} diff --git a/mcxa276-pac/src/can0/pl1_hi.rs b/mcxa276-pac/src/can0/pl1_hi.rs deleted file mode 100644 index 0af299fc5..000000000 --- a/mcxa276-pac/src/can0/pl1_hi.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `PL1_HI` reader"] -pub type R = crate::R; -#[doc = "Register `PL1_HI` writer"] -pub type W = crate::W; -#[doc = "Field `Data_byte_7` reader - Data byte 7"] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `Data_byte_7` writer - Data byte 7"] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_6` reader - Data byte 6"] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `Data_byte_6` writer - Data byte 6"] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_5` reader - Data byte 5"] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `Data_byte_5` writer - Data byte 5"] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_4` reader - Data byte 4"] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `Data_byte_4` writer - Data byte 4"] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 7"] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 6"] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 5"] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 4"] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 7"] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 6"] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 5"] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 4"] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Pretended Networking Payload High Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pl1HiSpec; -impl crate::RegisterSpec for Pl1HiSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pl1_hi::R`](R) reader structure"] -impl crate::Readable for Pl1HiSpec {} -#[doc = "`write(|w| ..)` method takes [`pl1_hi::W`](W) writer structure"] -impl crate::Writable for Pl1HiSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PL1_HI to value 0"] -impl crate::Resettable for Pl1HiSpec {} diff --git a/mcxa276-pac/src/can0/pl1_lo.rs b/mcxa276-pac/src/can0/pl1_lo.rs deleted file mode 100644 index 63525cbb8..000000000 --- a/mcxa276-pac/src/can0/pl1_lo.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `PL1_LO` reader"] -pub type R = crate::R; -#[doc = "Register `PL1_LO` writer"] -pub type W = crate::W; -#[doc = "Field `Data_byte_3` reader - Data byte 3"] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `Data_byte_3` writer - Data byte 3"] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_2` reader - Data byte 2"] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `Data_byte_2` writer - Data byte 2"] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_1` reader - Data byte 1"] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `Data_byte_1` writer - Data byte 1"] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_0` reader - Data byte 0"] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `Data_byte_0` writer - Data byte 0"] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data byte 3"] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data byte 2"] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data byte 1"] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data byte 0"] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data byte 3"] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data byte 2"] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data byte 1"] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data byte 0"] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Pretended Networking Payload Low Filter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pl1_lo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl1_lo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pl1LoSpec; -impl crate::RegisterSpec for Pl1LoSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pl1_lo::R`](R) reader structure"] -impl crate::Readable for Pl1LoSpec {} -#[doc = "`write(|w| ..)` method takes [`pl1_lo::W`](W) writer structure"] -impl crate::Writable for Pl1LoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PL1_LO to value 0"] -impl crate::Resettable for Pl1LoSpec {} diff --git a/mcxa276-pac/src/can0/pl2_plmask_hi.rs b/mcxa276-pac/src/can0/pl2_plmask_hi.rs deleted file mode 100644 index ff872f444..000000000 --- a/mcxa276-pac/src/can0/pl2_plmask_hi.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `PL2_PLMASK_HI` reader"] -pub type R = crate::R; -#[doc = "Register `PL2_PLMASK_HI` writer"] -pub type W = crate::W; -#[doc = "Field `Data_byte_7` reader - Data Byte 7"] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `Data_byte_7` writer - Data Byte 7"] -pub type DataByte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_6` reader - Data Byte 6"] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `Data_byte_6` writer - Data Byte 6"] -pub type DataByte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_5` reader - Data Byte 5"] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `Data_byte_5` writer - Data Byte 5"] -pub type DataByte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_4` reader - Data Byte 4"] -pub type DataByte4R = crate::FieldReader; -#[doc = "Field `Data_byte_4` writer - Data Byte 4"] -pub type DataByte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data Byte 7"] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data Byte 6"] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data Byte 5"] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data Byte 4"] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data Byte 7"] - #[inline(always)] - pub fn data_byte_7(&mut self) -> DataByte7W { - DataByte7W::new(self, 0) - } - #[doc = "Bits 8:15 - Data Byte 6"] - #[inline(always)] - pub fn data_byte_6(&mut self) -> DataByte6W { - DataByte6W::new(self, 8) - } - #[doc = "Bits 16:23 - Data Byte 5"] - #[inline(always)] - pub fn data_byte_5(&mut self) -> DataByte5W { - DataByte5W::new(self, 16) - } - #[doc = "Bits 24:31 - Data Byte 4"] - #[inline(always)] - pub fn data_byte_4(&mut self) -> DataByte4W { - DataByte4W::new(self, 24) - } -} -#[doc = "Pretended Networking Payload High Filter 2 and Payload High Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pl2PlmaskHiSpec; -impl crate::RegisterSpec for Pl2PlmaskHiSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pl2_plmask_hi::R`](R) reader structure"] -impl crate::Readable for Pl2PlmaskHiSpec {} -#[doc = "`write(|w| ..)` method takes [`pl2_plmask_hi::W`](W) writer structure"] -impl crate::Writable for Pl2PlmaskHiSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PL2_PLMASK_HI to value 0"] -impl crate::Resettable for Pl2PlmaskHiSpec {} diff --git a/mcxa276-pac/src/can0/pl2_plmask_lo.rs b/mcxa276-pac/src/can0/pl2_plmask_lo.rs deleted file mode 100644 index c1f826020..000000000 --- a/mcxa276-pac/src/can0/pl2_plmask_lo.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `PL2_PLMASK_LO` reader"] -pub type R = crate::R; -#[doc = "Register `PL2_PLMASK_LO` writer"] -pub type W = crate::W; -#[doc = "Field `Data_byte_3` reader - Data Byte 3"] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `Data_byte_3` writer - Data Byte 3"] -pub type DataByte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_2` reader - Data Byte 2"] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `Data_byte_2` writer - Data Byte 2"] -pub type DataByte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_1` reader - Data Byte 1"] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `Data_byte_1` writer - Data Byte 1"] -pub type DataByte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Data_byte_0` reader - Data Byte 0"] -pub type DataByte0R = crate::FieldReader; -#[doc = "Field `Data_byte_0` writer - Data Byte 0"] -pub type DataByte0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Data Byte 3"] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data Byte 2"] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data Byte 1"] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data Byte 0"] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Data Byte 3"] - #[inline(always)] - pub fn data_byte_3(&mut self) -> DataByte3W { - DataByte3W::new(self, 0) - } - #[doc = "Bits 8:15 - Data Byte 2"] - #[inline(always)] - pub fn data_byte_2(&mut self) -> DataByte2W { - DataByte2W::new(self, 8) - } - #[doc = "Bits 16:23 - Data Byte 1"] - #[inline(always)] - pub fn data_byte_1(&mut self) -> DataByte1W { - DataByte1W::new(self, 16) - } - #[doc = "Bits 24:31 - Data Byte 0"] - #[inline(always)] - pub fn data_byte_0(&mut self) -> DataByte0W { - DataByte0W::new(self, 24) - } -} -#[doc = "Pretended Networking Payload Low Filter 2 and Payload Low Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pl2_plmask_lo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pl2_plmask_lo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pl2PlmaskLoSpec; -impl crate::RegisterSpec for Pl2PlmaskLoSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pl2_plmask_lo::R`](R) reader structure"] -impl crate::Readable for Pl2PlmaskLoSpec {} -#[doc = "`write(|w| ..)` method takes [`pl2_plmask_lo::W`](W) writer structure"] -impl crate::Writable for Pl2PlmaskLoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PL2_PLMASK_LO to value 0"] -impl crate::Resettable for Pl2PlmaskLoSpec {} diff --git a/mcxa276-pac/src/can0/rx14mask.rs b/mcxa276-pac/src/can0/rx14mask.rs deleted file mode 100644 index 008dde3e2..000000000 --- a/mcxa276-pac/src/can0/rx14mask.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RX14MASK` reader"] -pub type R = crate::R; -#[doc = "Register `RX14MASK` writer"] -pub type W = crate::W; -#[doc = "Field `RX14M` reader - RX Buffer 14 Mask Bits"] -pub type Rx14mR = crate::FieldReader; -#[doc = "Field `RX14M` writer - RX Buffer 14 Mask Bits"] -pub type Rx14mW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - RX Buffer 14 Mask Bits"] - #[inline(always)] - pub fn rx14m(&self) -> Rx14mR { - Rx14mR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - RX Buffer 14 Mask Bits"] - #[inline(always)] - pub fn rx14m(&mut self) -> Rx14mW { - Rx14mW::new(self, 0) - } -} -#[doc = "Receive 14 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx14mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx14mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Rx14maskSpec; -impl crate::RegisterSpec for Rx14maskSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rx14mask::R`](R) reader structure"] -impl crate::Readable for Rx14maskSpec {} -#[doc = "`write(|w| ..)` method takes [`rx14mask::W`](W) writer structure"] -impl crate::Writable for Rx14maskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RX14MASK to value 0"] -impl crate::Resettable for Rx14maskSpec {} diff --git a/mcxa276-pac/src/can0/rx15mask.rs b/mcxa276-pac/src/can0/rx15mask.rs deleted file mode 100644 index 3232c334c..000000000 --- a/mcxa276-pac/src/can0/rx15mask.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RX15MASK` reader"] -pub type R = crate::R; -#[doc = "Register `RX15MASK` writer"] -pub type W = crate::W; -#[doc = "Field `RX15M` reader - RX Buffer 15 Mask Bits"] -pub type Rx15mR = crate::FieldReader; -#[doc = "Field `RX15M` writer - RX Buffer 15 Mask Bits"] -pub type Rx15mW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - RX Buffer 15 Mask Bits"] - #[inline(always)] - pub fn rx15m(&self) -> Rx15mR { - Rx15mR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - RX Buffer 15 Mask Bits"] - #[inline(always)] - pub fn rx15m(&mut self) -> Rx15mW { - Rx15mW::new(self, 0) - } -} -#[doc = "Receive 15 Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rx15mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx15mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Rx15maskSpec; -impl crate::RegisterSpec for Rx15maskSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rx15mask::R`](R) reader structure"] -impl crate::Readable for Rx15maskSpec {} -#[doc = "`write(|w| ..)` method takes [`rx15mask::W`](W) writer structure"] -impl crate::Writable for Rx15maskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RX15MASK to value 0"] -impl crate::Resettable for Rx15maskSpec {} diff --git a/mcxa276-pac/src/can0/rxfgmask.rs b/mcxa276-pac/src/can0/rxfgmask.rs deleted file mode 100644 index d3fa8aa5e..000000000 --- a/mcxa276-pac/src/can0/rxfgmask.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RXFGMASK` reader"] -pub type R = crate::R; -#[doc = "Register `RXFGMASK` writer"] -pub type W = crate::W; -#[doc = "Field `FGM` reader - Legacy RX FIFO Global Mask Bits"] -pub type FgmR = crate::FieldReader; -#[doc = "Field `FGM` writer - Legacy RX FIFO Global Mask Bits"] -pub type FgmW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Legacy RX FIFO Global Mask Bits"] - #[inline(always)] - pub fn fgm(&self) -> FgmR { - FgmR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Legacy RX FIFO Global Mask Bits"] - #[inline(always)] - pub fn fgm(&mut self) -> FgmW { - FgmW::new(self, 0) - } -} -#[doc = "Legacy RX FIFO Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfgmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfgmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RxfgmaskSpec; -impl crate::RegisterSpec for RxfgmaskSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rxfgmask::R`](R) reader structure"] -impl crate::Readable for RxfgmaskSpec {} -#[doc = "`write(|w| ..)` method takes [`rxfgmask::W`](W) writer structure"] -impl crate::Writable for RxfgmaskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RXFGMASK to value 0"] -impl crate::Resettable for RxfgmaskSpec {} diff --git a/mcxa276-pac/src/can0/rxfir.rs b/mcxa276-pac/src/can0/rxfir.rs deleted file mode 100644 index 8358bfd79..000000000 --- a/mcxa276-pac/src/can0/rxfir.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `RXFIR` reader"] -pub type R = crate::R; -#[doc = "Field `IDHIT` reader - Identifier Acceptance Filter Hit Indicator"] -pub type IdhitR = crate::FieldReader; -impl R { - #[doc = "Bits 0:8 - Identifier Acceptance Filter Hit Indicator"] - #[inline(always)] - pub fn idhit(&self) -> IdhitR { - IdhitR::new((self.bits & 0x01ff) as u16) - } -} -#[doc = "Legacy RX FIFO Information\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RxfirSpec; -impl crate::RegisterSpec for RxfirSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rxfir::R`](R) reader structure"] -impl crate::Readable for RxfirSpec {} -#[doc = "`reset()` method sets RXFIR to value 0"] -impl crate::Resettable for RxfirSpec {} diff --git a/mcxa276-pac/src/can0/rximr.rs b/mcxa276-pac/src/can0/rximr.rs deleted file mode 100644 index 23d4d8868..000000000 --- a/mcxa276-pac/src/can0/rximr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RXIMR[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `RXIMR[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `MI` reader - Individual Mask Bits"] -pub type MiR = crate::FieldReader; -#[doc = "Field `MI` writer - Individual Mask Bits"] -pub type MiW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Individual Mask Bits"] - #[inline(always)] - pub fn mi(&self) -> MiR { - MiR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Individual Mask Bits"] - #[inline(always)] - pub fn mi(&mut self) -> MiW { - MiW::new(self, 0) - } -} -#[doc = "Receive Individual Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rximr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rximr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RximrSpec; -impl crate::RegisterSpec for RximrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rximr::R`](R) reader structure"] -impl crate::Readable for RximrSpec {} -#[doc = "`write(|w| ..)` method takes [`rximr::W`](W) writer structure"] -impl crate::Writable for RximrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RXIMR[%s] to value 0"] -impl crate::Resettable for RximrSpec {} diff --git a/mcxa276-pac/src/can0/rxmgmask.rs b/mcxa276-pac/src/can0/rxmgmask.rs deleted file mode 100644 index f2ebaa2ab..000000000 --- a/mcxa276-pac/src/can0/rxmgmask.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RXMGMASK` reader"] -pub type R = crate::R; -#[doc = "Register `RXMGMASK` writer"] -pub type W = crate::W; -#[doc = "Field `MG` reader - Global Mask for RX Message Buffers"] -pub type MgR = crate::FieldReader; -#[doc = "Field `MG` writer - Global Mask for RX Message Buffers"] -pub type MgW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Global Mask for RX Message Buffers"] - #[inline(always)] - pub fn mg(&self) -> MgR { - MgR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Global Mask for RX Message Buffers"] - #[inline(always)] - pub fn mg(&mut self) -> MgW { - MgW::new(self, 0) - } -} -#[doc = "RX Message Buffers Global Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`rxmgmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxmgmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RxmgmaskSpec; -impl crate::RegisterSpec for RxmgmaskSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rxmgmask::R`](R) reader structure"] -impl crate::Readable for RxmgmaskSpec {} -#[doc = "`write(|w| ..)` method takes [`rxmgmask::W`](W) writer structure"] -impl crate::Writable for RxmgmaskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RXMGMASK to value 0"] -impl crate::Resettable for RxmgmaskSpec {} diff --git a/mcxa276-pac/src/can0/timer.rs b/mcxa276-pac/src/can0/timer.rs deleted file mode 100644 index 080ae41a3..000000000 --- a/mcxa276-pac/src/can0/timer.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TIMER` reader"] -pub type R = crate::R; -#[doc = "Register `TIMER` writer"] -pub type W = crate::W; -#[doc = "Field `TIMER` reader - Timer Value"] -pub type TimerR = crate::FieldReader; -#[doc = "Field `TIMER` writer - Timer Value"] -pub type TimerW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Timer Value"] - #[inline(always)] - pub fn timer(&self) -> TimerR { - TimerR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Timer Value"] - #[inline(always)] - pub fn timer(&mut self) -> TimerW { - TimerW::new(self, 0) - } -} -#[doc = "Free-Running Timer\n\nYou can [`read`](crate::Reg::read) this register and get [`timer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TimerSpec; -impl crate::RegisterSpec for TimerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timer::R`](R) reader structure"] -impl crate::Readable for TimerSpec {} -#[doc = "`write(|w| ..)` method takes [`timer::W`](W) writer structure"] -impl crate::Writable for TimerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMER to value 0"] -impl crate::Resettable for TimerSpec {} diff --git a/mcxa276-pac/src/can0/wmb.rs b/mcxa276-pac/src/can0/wmb.rs deleted file mode 100644 index d7b31fcdc..000000000 --- a/mcxa276-pac/src/can0/wmb.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[repr(C)] -#[doc = "Array of registers: WMB_CS, WMB_D03, WMB_D47, WMB_ID"] -#[doc(alias = "WMB")] -pub struct Wmb { - wmb_cs: WmbCs, - wmb_id: WmbId, - wmb_d03: WmbD03, - wmb_d47: WmbD47, -} -impl Wmb { - #[doc = "0x00 - Wake-Up Message Buffer"] - #[inline(always)] - pub const fn wmb_cs(&self) -> &WmbCs { - &self.wmb_cs - } - #[doc = "0x04 - Wake-Up Message Buffer for ID"] - #[inline(always)] - pub const fn wmb_id(&self) -> &WmbId { - &self.wmb_id - } - #[doc = "0x08 - Wake-Up Message Buffer for Data 0-3"] - #[inline(always)] - pub const fn wmb_d03(&self) -> &WmbD03 { - &self.wmb_d03 - } - #[doc = "0x0c - Wake-Up Message Buffer Register Data 4-7"] - #[inline(always)] - pub const fn wmb_d47(&self) -> &WmbD47 { - &self.wmb_d47 - } -} -#[doc = "WMB_CS (r) register accessor: Wake-Up Message Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_cs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_cs`] module"] -#[doc(alias = "WMB_CS")] -pub type WmbCs = crate::Reg; -#[doc = "Wake-Up Message Buffer"] -pub mod wmb_cs; -#[doc = "WMB_ID (r) register accessor: Wake-Up Message Buffer for ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_id`] module"] -#[doc(alias = "WMB_ID")] -pub type WmbId = crate::Reg; -#[doc = "Wake-Up Message Buffer for ID"] -pub mod wmb_id; -#[doc = "WMB_D03 (r) register accessor: Wake-Up Message Buffer for Data 0-3\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d03::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_d03`] module"] -#[doc(alias = "WMB_D03")] -pub type WmbD03 = crate::Reg; -#[doc = "Wake-Up Message Buffer for Data 0-3"] -pub mod wmb_d03; -#[doc = "WMB_D47 (r) register accessor: Wake-Up Message Buffer Register Data 4-7\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d47::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wmb_d47`] module"] -#[doc(alias = "WMB_D47")] -pub type WmbD47 = crate::Reg; -#[doc = "Wake-Up Message Buffer Register Data 4-7"] -pub mod wmb_d47; diff --git a/mcxa276-pac/src/can0/wmb/wmb_cs.rs b/mcxa276-pac/src/can0/wmb/wmb_cs.rs deleted file mode 100644 index 7e448ab72..000000000 --- a/mcxa276-pac/src/can0/wmb/wmb_cs.rs +++ /dev/null @@ -1,143 +0,0 @@ -#[doc = "Register `WMB_CS` reader"] -pub type R = crate::R; -#[doc = "Field `DLC` reader - Length of Data in Bytes"] -pub type DlcR = crate::FieldReader; -#[doc = "Remote Transmission Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rtr { - #[doc = "0: Data"] - NotRemote = 0, - #[doc = "1: Remote"] - Remote = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rtr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RTR` reader - Remote Transmission Request"] -pub type RtrR = crate::BitReader; -impl RtrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rtr { - match self.bits { - false => Rtr::NotRemote, - true => Rtr::Remote, - } - } - #[doc = "Data"] - #[inline(always)] - pub fn is_not_remote(&self) -> bool { - *self == Rtr::NotRemote - } - #[doc = "Remote"] - #[inline(always)] - pub fn is_remote(&self) -> bool { - *self == Rtr::Remote - } -} -#[doc = "ID Extended Bit\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ide { - #[doc = "0: Standard"] - Standard = 0, - #[doc = "1: Extended"] - Extended = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ide) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IDE` reader - ID Extended Bit"] -pub type IdeR = crate::BitReader; -impl IdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ide { - match self.bits { - false => Ide::Standard, - true => Ide::Extended, - } - } - #[doc = "Standard"] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == Ide::Standard - } - #[doc = "Extended"] - #[inline(always)] - pub fn is_extended(&self) -> bool { - *self == Ide::Extended - } -} -#[doc = "Substitute Remote Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Srr { - #[doc = "0: Dominant"] - Dominant = 0, - #[doc = "1: Recessive"] - Recessive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Srr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRR` reader - Substitute Remote Request"] -pub type SrrR = crate::BitReader; -impl SrrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Srr { - match self.bits { - false => Srr::Dominant, - true => Srr::Recessive, - } - } - #[doc = "Dominant"] - #[inline(always)] - pub fn is_dominant(&self) -> bool { - *self == Srr::Dominant - } - #[doc = "Recessive"] - #[inline(always)] - pub fn is_recessive(&self) -> bool { - *self == Srr::Recessive - } -} -impl R { - #[doc = "Bits 16:19 - Length of Data in Bytes"] - #[inline(always)] - pub fn dlc(&self) -> DlcR { - DlcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 20 - Remote Transmission Request"] - #[inline(always)] - pub fn rtr(&self) -> RtrR { - RtrR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - ID Extended Bit"] - #[inline(always)] - pub fn ide(&self) -> IdeR { - IdeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Substitute Remote Request"] - #[inline(always)] - pub fn srr(&self) -> SrrR { - SrrR::new(((self.bits >> 22) & 1) != 0) - } -} -#[doc = "Wake-Up Message Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_cs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WmbCsSpec; -impl crate::RegisterSpec for WmbCsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wmb_cs::R`](R) reader structure"] -impl crate::Readable for WmbCsSpec {} -#[doc = "`reset()` method sets WMB_CS to value 0"] -impl crate::Resettable for WmbCsSpec {} diff --git a/mcxa276-pac/src/can0/wmb/wmb_d03.rs b/mcxa276-pac/src/can0/wmb/wmb_d03.rs deleted file mode 100644 index afcbf6dce..000000000 --- a/mcxa276-pac/src/can0/wmb/wmb_d03.rs +++ /dev/null @@ -1,41 +0,0 @@ -#[doc = "Register `WMB_D03` reader"] -pub type R = crate::R; -#[doc = "Field `Data_byte_3` reader - Data Byte 3"] -pub type DataByte3R = crate::FieldReader; -#[doc = "Field `Data_byte_2` reader - Data Byte 2"] -pub type DataByte2R = crate::FieldReader; -#[doc = "Field `Data_byte_1` reader - Data Byte 1"] -pub type DataByte1R = crate::FieldReader; -#[doc = "Field `Data_byte_0` reader - Data Byte 0"] -pub type DataByte0R = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Data Byte 3"] - #[inline(always)] - pub fn data_byte_3(&self) -> DataByte3R { - DataByte3R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data Byte 2"] - #[inline(always)] - pub fn data_byte_2(&self) -> DataByte2R { - DataByte2R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data Byte 1"] - #[inline(always)] - pub fn data_byte_1(&self) -> DataByte1R { - DataByte1R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data Byte 0"] - #[inline(always)] - pub fn data_byte_0(&self) -> DataByte0R { - DataByte0R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Wake-Up Message Buffer for Data 0-3\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d03::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WmbD03Spec; -impl crate::RegisterSpec for WmbD03Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wmb_d03::R`](R) reader structure"] -impl crate::Readable for WmbD03Spec {} -#[doc = "`reset()` method sets WMB_D03 to value 0"] -impl crate::Resettable for WmbD03Spec {} diff --git a/mcxa276-pac/src/can0/wmb/wmb_d47.rs b/mcxa276-pac/src/can0/wmb/wmb_d47.rs deleted file mode 100644 index 38f88ea35..000000000 --- a/mcxa276-pac/src/can0/wmb/wmb_d47.rs +++ /dev/null @@ -1,41 +0,0 @@ -#[doc = "Register `WMB_D47` reader"] -pub type R = crate::R; -#[doc = "Field `Data_byte_7` reader - Data Byte 7"] -pub type DataByte7R = crate::FieldReader; -#[doc = "Field `Data_byte_6` reader - Data Byte 6"] -pub type DataByte6R = crate::FieldReader; -#[doc = "Field `Data_byte_5` reader - Data Byte 5"] -pub type DataByte5R = crate::FieldReader; -#[doc = "Field `Data_byte_4` reader - Data Byte 4"] -pub type DataByte4R = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Data Byte 7"] - #[inline(always)] - pub fn data_byte_7(&self) -> DataByte7R { - DataByte7R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Data Byte 6"] - #[inline(always)] - pub fn data_byte_6(&self) -> DataByte6R { - DataByte6R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data Byte 5"] - #[inline(always)] - pub fn data_byte_5(&self) -> DataByte5R { - DataByte5R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Data Byte 4"] - #[inline(always)] - pub fn data_byte_4(&self) -> DataByte4R { - DataByte4R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Wake-Up Message Buffer Register Data 4-7\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_d47::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WmbD47Spec; -impl crate::RegisterSpec for WmbD47Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wmb_d47::R`](R) reader structure"] -impl crate::Readable for WmbD47Spec {} -#[doc = "`reset()` method sets WMB_D47 to value 0"] -impl crate::Resettable for WmbD47Spec {} diff --git a/mcxa276-pac/src/can0/wmb/wmb_id.rs b/mcxa276-pac/src/can0/wmb/wmb_id.rs deleted file mode 100644 index a2fb06787..000000000 --- a/mcxa276-pac/src/can0/wmb/wmb_id.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `WMB_ID` reader"] -pub type R = crate::R; -#[doc = "Field `ID` reader - Received ID in Pretended Networking Mode"] -pub type IdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:28 - Received ID in Pretended Networking Mode"] - #[inline(always)] - pub fn id(&self) -> IdR { - IdR::new(self.bits & 0x1fff_ffff) - } -} -#[doc = "Wake-Up Message Buffer for ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wmb_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WmbIdSpec; -impl crate::RegisterSpec for WmbIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wmb_id::R`](R) reader structure"] -impl crate::Readable for WmbIdSpec {} -#[doc = "`reset()` method sets WMB_ID to value 0"] -impl crate::Resettable for WmbIdSpec {} diff --git a/mcxa276-pac/src/can0/wu_mtc.rs b/mcxa276-pac/src/can0/wu_mtc.rs deleted file mode 100644 index 779145c87..000000000 --- a/mcxa276-pac/src/can0/wu_mtc.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `WU_MTC` reader"] -pub type R = crate::R; -#[doc = "Register `WU_MTC` writer"] -pub type W = crate::W; -#[doc = "Field `MCOUNTER` reader - Number of Matches in Pretended Networking"] -pub type McounterR = crate::FieldReader; -#[doc = "Wake-up by Match Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wumf { - #[doc = "0: No event detected"] - NoMatch = 0, - #[doc = "1: Event detected"] - Match = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wumf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUMF` reader - Wake-up by Match Flag"] -pub type WumfR = crate::BitReader; -impl WumfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wumf { - match self.bits { - false => Wumf::NoMatch, - true => Wumf::Match, - } - } - #[doc = "No event detected"] - #[inline(always)] - pub fn is_no_match(&self) -> bool { - *self == Wumf::NoMatch - } - #[doc = "Event detected"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Wumf::Match - } -} -#[doc = "Field `WUMF` writer - Wake-up by Match Flag"] -pub type WumfW<'a, REG> = crate::BitWriter1C<'a, REG, Wumf>; -impl<'a, REG> WumfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No event detected"] - #[inline(always)] - pub fn no_match(self) -> &'a mut crate::W { - self.variant(Wumf::NoMatch) - } - #[doc = "Event detected"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Wumf::Match) - } -} -#[doc = "Wake-up by Timeout Flag Bit\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wtof { - #[doc = "0: No event detected"] - NoWakeup = 0, - #[doc = "1: Event detected"] - Wakeup = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wtof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WTOF` reader - Wake-up by Timeout Flag Bit"] -pub type WtofR = crate::BitReader; -impl WtofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wtof { - match self.bits { - false => Wtof::NoWakeup, - true => Wtof::Wakeup, - } - } - #[doc = "No event detected"] - #[inline(always)] - pub fn is_no_wakeup(&self) -> bool { - *self == Wtof::NoWakeup - } - #[doc = "Event detected"] - #[inline(always)] - pub fn is_wakeup(&self) -> bool { - *self == Wtof::Wakeup - } -} -#[doc = "Field `WTOF` writer - Wake-up by Timeout Flag Bit"] -pub type WtofW<'a, REG> = crate::BitWriter1C<'a, REG, Wtof>; -impl<'a, REG> WtofW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No event detected"] - #[inline(always)] - pub fn no_wakeup(self) -> &'a mut crate::W { - self.variant(Wtof::NoWakeup) - } - #[doc = "Event detected"] - #[inline(always)] - pub fn wakeup(self) -> &'a mut crate::W { - self.variant(Wtof::Wakeup) - } -} -impl R { - #[doc = "Bits 8:15 - Number of Matches in Pretended Networking"] - #[inline(always)] - pub fn mcounter(&self) -> McounterR { - McounterR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bit 16 - Wake-up by Match Flag"] - #[inline(always)] - pub fn wumf(&self) -> WumfR { - WumfR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Wake-up by Timeout Flag Bit"] - #[inline(always)] - pub fn wtof(&self) -> WtofR { - WtofR::new(((self.bits >> 17) & 1) != 0) - } -} -impl W { - #[doc = "Bit 16 - Wake-up by Match Flag"] - #[inline(always)] - pub fn wumf(&mut self) -> WumfW { - WumfW::new(self, 16) - } - #[doc = "Bit 17 - Wake-up by Timeout Flag Bit"] - #[inline(always)] - pub fn wtof(&mut self) -> WtofW { - WtofW::new(self, 17) - } -} -#[doc = "Pretended Networking Wake-Up Match\n\nYou can [`read`](crate::Reg::read) this register and get [`wu_mtc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wu_mtc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WuMtcSpec; -impl crate::RegisterSpec for WuMtcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wu_mtc::R`](R) reader structure"] -impl crate::Readable for WuMtcSpec {} -#[doc = "`write(|w| ..)` method takes [`wu_mtc::W`](W) writer structure"] -impl crate::Writable for WuMtcSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0003_0000; -} -#[doc = "`reset()` method sets WU_MTC to value 0"] -impl crate::Resettable for WuMtcSpec {} diff --git a/mcxa276-pac/src/cdog0.rs b/mcxa276-pac/src/cdog0.rs deleted file mode 100644 index 4af471705..000000000 --- a/mcxa276-pac/src/cdog0.rs +++ /dev/null @@ -1,216 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - control: Control, - reload: Reload, - instruction_timer: InstructionTimer, - _reserved3: [u8; 0x04], - status: Status, - status2: Status2, - flags: Flags, - persistent: Persistent, - start: Start, - stop: Stop, - restart: Restart, - add: Add, - add1: Add1, - add16: Add16, - add256: Add256, - sub: Sub, - sub1: Sub1, - sub16: Sub16, - sub256: Sub256, - assert16: Assert16, -} -impl RegisterBlock { - #[doc = "0x00 - Control Register"] - #[inline(always)] - pub const fn control(&self) -> &Control { - &self.control - } - #[doc = "0x04 - Instruction Timer Reload Register"] - #[inline(always)] - pub const fn reload(&self) -> &Reload { - &self.reload - } - #[doc = "0x08 - Instruction Timer Register"] - #[inline(always)] - pub const fn instruction_timer(&self) -> &InstructionTimer { - &self.instruction_timer - } - #[doc = "0x10 - Status 1 Register"] - #[inline(always)] - pub const fn status(&self) -> &Status { - &self.status - } - #[doc = "0x14 - Status 2 Register"] - #[inline(always)] - pub const fn status2(&self) -> &Status2 { - &self.status2 - } - #[doc = "0x18 - Flags Register"] - #[inline(always)] - pub const fn flags(&self) -> &Flags { - &self.flags - } - #[doc = "0x1c - Persistent Data Storage Register"] - #[inline(always)] - pub const fn persistent(&self) -> &Persistent { - &self.persistent - } - #[doc = "0x20 - START Command Register"] - #[inline(always)] - pub const fn start(&self) -> &Start { - &self.start - } - #[doc = "0x24 - STOP Command Register"] - #[inline(always)] - pub const fn stop(&self) -> &Stop { - &self.stop - } - #[doc = "0x28 - RESTART Command Register"] - #[inline(always)] - pub const fn restart(&self) -> &Restart { - &self.restart - } - #[doc = "0x2c - ADD Command Register"] - #[inline(always)] - pub const fn add(&self) -> &Add { - &self.add - } - #[doc = "0x30 - ADD1 Command Register"] - #[inline(always)] - pub const fn add1(&self) -> &Add1 { - &self.add1 - } - #[doc = "0x34 - ADD16 Command Register"] - #[inline(always)] - pub const fn add16(&self) -> &Add16 { - &self.add16 - } - #[doc = "0x38 - ADD256 Command Register"] - #[inline(always)] - pub const fn add256(&self) -> &Add256 { - &self.add256 - } - #[doc = "0x3c - SUB Command Register"] - #[inline(always)] - pub const fn sub(&self) -> &Sub { - &self.sub - } - #[doc = "0x40 - SUB1 Command Register"] - #[inline(always)] - pub const fn sub1(&self) -> &Sub1 { - &self.sub1 - } - #[doc = "0x44 - SUB16 Command Register"] - #[inline(always)] - pub const fn sub16(&self) -> &Sub16 { - &self.sub16 - } - #[doc = "0x48 - SUB256 Command Register"] - #[inline(always)] - pub const fn sub256(&self) -> &Sub256 { - &self.sub256 - } - #[doc = "0x4c - ASSERT16 Command Register"] - #[inline(always)] - pub const fn assert16(&self) -> &Assert16 { - &self.assert16 - } -} -#[doc = "CONTROL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`] module"] -#[doc(alias = "CONTROL")] -pub type Control = crate::Reg; -#[doc = "Control Register"] -pub mod control; -#[doc = "RELOAD (rw) register accessor: Instruction Timer Reload Register\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reload`] module"] -#[doc(alias = "RELOAD")] -pub type Reload = crate::Reg; -#[doc = "Instruction Timer Reload Register"] -pub mod reload; -#[doc = "INSTRUCTION_TIMER (r) register accessor: Instruction Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`instruction_timer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@instruction_timer`] module"] -#[doc(alias = "INSTRUCTION_TIMER")] -pub type InstructionTimer = crate::Reg; -#[doc = "Instruction Timer Register"] -pub mod instruction_timer; -#[doc = "STATUS (r) register accessor: Status 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] -#[doc(alias = "STATUS")] -pub type Status = crate::Reg; -#[doc = "Status 1 Register"] -pub mod status; -#[doc = "STATUS2 (r) register accessor: Status 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status2`] module"] -#[doc(alias = "STATUS2")] -pub type Status2 = crate::Reg; -#[doc = "Status 2 Register"] -pub mod status2; -#[doc = "FLAGS (rw) register accessor: Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flags::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flags::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flags`] module"] -#[doc(alias = "FLAGS")] -pub type Flags = crate::Reg; -#[doc = "Flags Register"] -pub mod flags; -#[doc = "PERSISTENT (rw) register accessor: Persistent Data Storage Register\n\nYou can [`read`](crate::Reg::read) this register and get [`persistent::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`persistent::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@persistent`] module"] -#[doc(alias = "PERSISTENT")] -pub type Persistent = crate::Reg; -#[doc = "Persistent Data Storage Register"] -pub mod persistent; -#[doc = "START (w) register accessor: START Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@start`] module"] -#[doc(alias = "START")] -pub type Start = crate::Reg; -#[doc = "START Command Register"] -pub mod start; -#[doc = "STOP (w) register accessor: STOP Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stop::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stop`] module"] -#[doc(alias = "STOP")] -pub type Stop = crate::Reg; -#[doc = "STOP Command Register"] -pub mod stop; -#[doc = "RESTART (w) register accessor: RESTART Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`restart::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@restart`] module"] -#[doc(alias = "RESTART")] -pub type Restart = crate::Reg; -#[doc = "RESTART Command Register"] -pub mod restart; -#[doc = "ADD (w) register accessor: ADD Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add`] module"] -#[doc(alias = "ADD")] -pub type Add = crate::Reg; -#[doc = "ADD Command Register"] -pub mod add; -#[doc = "ADD1 (w) register accessor: ADD1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add1`] module"] -#[doc(alias = "ADD1")] -pub type Add1 = crate::Reg; -#[doc = "ADD1 Command Register"] -pub mod add1; -#[doc = "ADD16 (w) register accessor: ADD16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add16::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add16`] module"] -#[doc(alias = "ADD16")] -pub type Add16 = crate::Reg; -#[doc = "ADD16 Command Register"] -pub mod add16; -#[doc = "ADD256 (w) register accessor: ADD256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add256::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@add256`] module"] -#[doc(alias = "ADD256")] -pub type Add256 = crate::Reg; -#[doc = "ADD256 Command Register"] -pub mod add256; -#[doc = "SUB (w) register accessor: SUB Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub`] module"] -#[doc(alias = "SUB")] -pub type Sub = crate::Reg; -#[doc = "SUB Command Register"] -pub mod sub; -#[doc = "SUB1 (w) register accessor: SUB1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub1`] module"] -#[doc(alias = "SUB1")] -pub type Sub1 = crate::Reg; -#[doc = "SUB1 Command Register"] -pub mod sub1; -#[doc = "SUB16 (w) register accessor: SUB16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub16::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub16`] module"] -#[doc(alias = "SUB16")] -pub type Sub16 = crate::Reg; -#[doc = "SUB16 Command Register"] -pub mod sub16; -#[doc = "SUB256 (w) register accessor: SUB256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub256::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub256`] module"] -#[doc(alias = "SUB256")] -pub type Sub256 = crate::Reg; -#[doc = "SUB256 Command Register"] -pub mod sub256; -#[doc = "ASSERT16 (w) register accessor: ASSERT16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`assert16::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@assert16`] module"] -#[doc(alias = "ASSERT16")] -pub type Assert16 = crate::Reg; -#[doc = "ASSERT16 Command Register"] -pub mod assert16; diff --git a/mcxa276-pac/src/cdog0/add.rs b/mcxa276-pac/src/cdog0/add.rs deleted file mode 100644 index 5d96221f0..000000000 --- a/mcxa276-pac/src/cdog0/add.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `ADD` writer"] -pub type W = crate::W; -#[doc = "Field `AD` writer - ADD Write Value"] -pub type AdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - ADD Write Value"] - #[inline(always)] - pub fn ad(&mut self) -> AdW { - AdW::new(self, 0) - } -} -#[doc = "ADD Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AddSpec; -impl crate::RegisterSpec for AddSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`add::W`](W) writer structure"] -impl crate::Writable for AddSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADD to value 0"] -impl crate::Resettable for AddSpec {} diff --git a/mcxa276-pac/src/cdog0/add1.rs b/mcxa276-pac/src/cdog0/add1.rs deleted file mode 100644 index 01ef747ee..000000000 --- a/mcxa276-pac/src/cdog0/add1.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `ADD1` writer"] -pub type W = crate::W; -#[doc = "Field `AD1` writer - ADD 1"] -pub type Ad1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - ADD 1"] - #[inline(always)] - pub fn ad1(&mut self) -> Ad1W { - Ad1W::new(self, 0) - } -} -#[doc = "ADD1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Add1Spec; -impl crate::RegisterSpec for Add1Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`add1::W`](W) writer structure"] -impl crate::Writable for Add1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADD1 to value 0"] -impl crate::Resettable for Add1Spec {} diff --git a/mcxa276-pac/src/cdog0/add16.rs b/mcxa276-pac/src/cdog0/add16.rs deleted file mode 100644 index bb0f9d388..000000000 --- a/mcxa276-pac/src/cdog0/add16.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `ADD16` writer"] -pub type W = crate::W; -#[doc = "Field `AD16` writer - ADD 16"] -pub type Ad16W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - ADD 16"] - #[inline(always)] - pub fn ad16(&mut self) -> Ad16W { - Ad16W::new(self, 0) - } -} -#[doc = "ADD16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add16::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Add16Spec; -impl crate::RegisterSpec for Add16Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`add16::W`](W) writer structure"] -impl crate::Writable for Add16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADD16 to value 0"] -impl crate::Resettable for Add16Spec {} diff --git a/mcxa276-pac/src/cdog0/add256.rs b/mcxa276-pac/src/cdog0/add256.rs deleted file mode 100644 index c85048dcf..000000000 --- a/mcxa276-pac/src/cdog0/add256.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `ADD256` writer"] -pub type W = crate::W; -#[doc = "Field `AD256` writer - ADD 256"] -pub type Ad256W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - ADD 256"] - #[inline(always)] - pub fn ad256(&mut self) -> Ad256W { - Ad256W::new(self, 0) - } -} -#[doc = "ADD256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`add256::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Add256Spec; -impl crate::RegisterSpec for Add256Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`add256::W`](W) writer structure"] -impl crate::Writable for Add256Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADD256 to value 0"] -impl crate::Resettable for Add256Spec {} diff --git a/mcxa276-pac/src/cdog0/assert16.rs b/mcxa276-pac/src/cdog0/assert16.rs deleted file mode 100644 index c7fcd6b5e..000000000 --- a/mcxa276-pac/src/cdog0/assert16.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `ASSERT16` writer"] -pub type W = crate::W; -#[doc = "Field `AST16` writer - ASSERT16 Command"] -pub type Ast16W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - ASSERT16 Command"] - #[inline(always)] - pub fn ast16(&mut self) -> Ast16W { - Ast16W::new(self, 0) - } -} -#[doc = "ASSERT16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`assert16::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Assert16Spec; -impl crate::RegisterSpec for Assert16Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`assert16::W`](W) writer structure"] -impl crate::Writable for Assert16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ASSERT16 to value 0"] -impl crate::Resettable for Assert16Spec {} diff --git a/mcxa276-pac/src/cdog0/control.rs b/mcxa276-pac/src/cdog0/control.rs deleted file mode 100644 index 7cdd49906..000000000 --- a/mcxa276-pac/src/cdog0/control.rs +++ /dev/null @@ -1,648 +0,0 @@ -#[doc = "Register `CONTROL` reader"] -pub type R = crate::R; -#[doc = "Register `CONTROL` writer"] -pub type W = crate::W; -#[doc = "Lock control\n\nValue on reset: 2"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum LockCtrl { - #[doc = "1: Locked"] - Locked = 1, - #[doc = "2: Unlocked"] - Unlocked = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: LockCtrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for LockCtrl { - type Ux = u8; -} -impl crate::IsEnum for LockCtrl {} -#[doc = "Field `LOCK_CTRL` reader - Lock control"] -pub type LockCtrlR = crate::FieldReader; -impl LockCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(LockCtrl::Locked), - 2 => Some(LockCtrl::Unlocked), - _ => None, - } - } - #[doc = "Locked"] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == LockCtrl::Locked - } - #[doc = "Unlocked"] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == LockCtrl::Unlocked - } -} -#[doc = "Field `LOCK_CTRL` writer - Lock control"] -pub type LockCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, LockCtrl>; -impl<'a, REG> LockCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Locked"] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(LockCtrl::Locked) - } - #[doc = "Unlocked"] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(LockCtrl::Unlocked) - } -} -#[doc = "TIMEOUT fault control\n\nValue on reset: 4"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum TimeoutCtrl { - #[doc = "1: Enable reset"] - EnableReset = 1, - #[doc = "2: Enable interrupt"] - EnableInterrupt = 2, - #[doc = "4: Disable both reset and interrupt"] - DisableBoth = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: TimeoutCtrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for TimeoutCtrl { - type Ux = u8; -} -impl crate::IsEnum for TimeoutCtrl {} -#[doc = "Field `TIMEOUT_CTRL` reader - TIMEOUT fault control"] -pub type TimeoutCtrlR = crate::FieldReader; -impl TimeoutCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(TimeoutCtrl::EnableReset), - 2 => Some(TimeoutCtrl::EnableInterrupt), - 4 => Some(TimeoutCtrl::DisableBoth), - _ => None, - } - } - #[doc = "Enable reset"] - #[inline(always)] - pub fn is_enable_reset(&self) -> bool { - *self == TimeoutCtrl::EnableReset - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn is_enable_interrupt(&self) -> bool { - *self == TimeoutCtrl::EnableInterrupt - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn is_disable_both(&self) -> bool { - *self == TimeoutCtrl::DisableBoth - } -} -#[doc = "Field `TIMEOUT_CTRL` writer - TIMEOUT fault control"] -pub type TimeoutCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, TimeoutCtrl>; -impl<'a, REG> TimeoutCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Enable reset"] - #[inline(always)] - pub fn enable_reset(self) -> &'a mut crate::W { - self.variant(TimeoutCtrl::EnableReset) - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn enable_interrupt(self) -> &'a mut crate::W { - self.variant(TimeoutCtrl::EnableInterrupt) - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn disable_both(self) -> &'a mut crate::W { - self.variant(TimeoutCtrl::DisableBoth) - } -} -#[doc = "MISCOMPARE fault control\n\nValue on reset: 4"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum MiscompareCtrl { - #[doc = "1: Enable reset"] - EnableReset = 1, - #[doc = "2: Enable interrupt"] - EnableInterrupt = 2, - #[doc = "4: Disable both reset and interrupt"] - DisableBoth = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: MiscompareCtrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for MiscompareCtrl { - type Ux = u8; -} -impl crate::IsEnum for MiscompareCtrl {} -#[doc = "Field `MISCOMPARE_CTRL` reader - MISCOMPARE fault control"] -pub type MiscompareCtrlR = crate::FieldReader; -impl MiscompareCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(MiscompareCtrl::EnableReset), - 2 => Some(MiscompareCtrl::EnableInterrupt), - 4 => Some(MiscompareCtrl::DisableBoth), - _ => None, - } - } - #[doc = "Enable reset"] - #[inline(always)] - pub fn is_enable_reset(&self) -> bool { - *self == MiscompareCtrl::EnableReset - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn is_enable_interrupt(&self) -> bool { - *self == MiscompareCtrl::EnableInterrupt - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn is_disable_both(&self) -> bool { - *self == MiscompareCtrl::DisableBoth - } -} -#[doc = "Field `MISCOMPARE_CTRL` writer - MISCOMPARE fault control"] -pub type MiscompareCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, MiscompareCtrl>; -impl<'a, REG> MiscompareCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Enable reset"] - #[inline(always)] - pub fn enable_reset(self) -> &'a mut crate::W { - self.variant(MiscompareCtrl::EnableReset) - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn enable_interrupt(self) -> &'a mut crate::W { - self.variant(MiscompareCtrl::EnableInterrupt) - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn disable_both(self) -> &'a mut crate::W { - self.variant(MiscompareCtrl::DisableBoth) - } -} -#[doc = "SEQUENCE fault control\n\nValue on reset: 4"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum SequenceCtrl { - #[doc = "1: Enable reset"] - EnableReset = 1, - #[doc = "2: Enable interrupt"] - EnableInterrupt = 2, - #[doc = "4: Disable both reset and interrupt"] - DisableBoth = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: SequenceCtrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for SequenceCtrl { - type Ux = u8; -} -impl crate::IsEnum for SequenceCtrl {} -#[doc = "Field `SEQUENCE_CTRL` reader - SEQUENCE fault control"] -pub type SequenceCtrlR = crate::FieldReader; -impl SequenceCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(SequenceCtrl::EnableReset), - 2 => Some(SequenceCtrl::EnableInterrupt), - 4 => Some(SequenceCtrl::DisableBoth), - _ => None, - } - } - #[doc = "Enable reset"] - #[inline(always)] - pub fn is_enable_reset(&self) -> bool { - *self == SequenceCtrl::EnableReset - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn is_enable_interrupt(&self) -> bool { - *self == SequenceCtrl::EnableInterrupt - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn is_disable_both(&self) -> bool { - *self == SequenceCtrl::DisableBoth - } -} -#[doc = "Field `SEQUENCE_CTRL` writer - SEQUENCE fault control"] -pub type SequenceCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, SequenceCtrl>; -impl<'a, REG> SequenceCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Enable reset"] - #[inline(always)] - pub fn enable_reset(self) -> &'a mut crate::W { - self.variant(SequenceCtrl::EnableReset) - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn enable_interrupt(self) -> &'a mut crate::W { - self.variant(SequenceCtrl::EnableInterrupt) - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn disable_both(self) -> &'a mut crate::W { - self.variant(SequenceCtrl::DisableBoth) - } -} -#[doc = "STATE fault control\n\nValue on reset: 4"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum StateCtrl { - #[doc = "1: Enable reset"] - EnableReset = 1, - #[doc = "2: Enable interrupt"] - EnableInterrupt = 2, - #[doc = "4: Disable both reset and interrupt"] - DisableBoth = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: StateCtrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for StateCtrl { - type Ux = u8; -} -impl crate::IsEnum for StateCtrl {} -#[doc = "Field `STATE_CTRL` reader - STATE fault control"] -pub type StateCtrlR = crate::FieldReader; -impl StateCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(StateCtrl::EnableReset), - 2 => Some(StateCtrl::EnableInterrupt), - 4 => Some(StateCtrl::DisableBoth), - _ => None, - } - } - #[doc = "Enable reset"] - #[inline(always)] - pub fn is_enable_reset(&self) -> bool { - *self == StateCtrl::EnableReset - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn is_enable_interrupt(&self) -> bool { - *self == StateCtrl::EnableInterrupt - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn is_disable_both(&self) -> bool { - *self == StateCtrl::DisableBoth - } -} -#[doc = "Field `STATE_CTRL` writer - STATE fault control"] -pub type StateCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, StateCtrl>; -impl<'a, REG> StateCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Enable reset"] - #[inline(always)] - pub fn enable_reset(self) -> &'a mut crate::W { - self.variant(StateCtrl::EnableReset) - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn enable_interrupt(self) -> &'a mut crate::W { - self.variant(StateCtrl::EnableInterrupt) - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn disable_both(self) -> &'a mut crate::W { - self.variant(StateCtrl::DisableBoth) - } -} -#[doc = "ADDRESS fault control\n\nValue on reset: 4"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum AddressCtrl { - #[doc = "1: Enable reset"] - EnableReset = 1, - #[doc = "2: Enable interrupt"] - EnableInterrupt = 2, - #[doc = "4: Disable both reset and interrupt"] - DisableBoth = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: AddressCtrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for AddressCtrl { - type Ux = u8; -} -impl crate::IsEnum for AddressCtrl {} -#[doc = "Field `ADDRESS_CTRL` reader - ADDRESS fault control"] -pub type AddressCtrlR = crate::FieldReader; -impl AddressCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(AddressCtrl::EnableReset), - 2 => Some(AddressCtrl::EnableInterrupt), - 4 => Some(AddressCtrl::DisableBoth), - _ => None, - } - } - #[doc = "Enable reset"] - #[inline(always)] - pub fn is_enable_reset(&self) -> bool { - *self == AddressCtrl::EnableReset - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn is_enable_interrupt(&self) -> bool { - *self == AddressCtrl::EnableInterrupt - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn is_disable_both(&self) -> bool { - *self == AddressCtrl::DisableBoth - } -} -#[doc = "Field `ADDRESS_CTRL` writer - ADDRESS fault control"] -pub type AddressCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, AddressCtrl>; -impl<'a, REG> AddressCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Enable reset"] - #[inline(always)] - pub fn enable_reset(self) -> &'a mut crate::W { - self.variant(AddressCtrl::EnableReset) - } - #[doc = "Enable interrupt"] - #[inline(always)] - pub fn enable_interrupt(self) -> &'a mut crate::W { - self.variant(AddressCtrl::EnableInterrupt) - } - #[doc = "Disable both reset and interrupt"] - #[inline(always)] - pub fn disable_both(self) -> &'a mut crate::W { - self.variant(AddressCtrl::DisableBoth) - } -} -#[doc = "IRQ pause control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum IrqPause { - #[doc = "1: Keep the timer running"] - RunTimer = 1, - #[doc = "2: Stop the timer"] - PauseTimer = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: IrqPause) -> Self { - variant as _ - } -} -impl crate::FieldSpec for IrqPause { - type Ux = u8; -} -impl crate::IsEnum for IrqPause {} -#[doc = "Field `IRQ_PAUSE` reader - IRQ pause control"] -pub type IrqPauseR = crate::FieldReader; -impl IrqPauseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(IrqPause::RunTimer), - 2 => Some(IrqPause::PauseTimer), - _ => None, - } - } - #[doc = "Keep the timer running"] - #[inline(always)] - pub fn is_run_timer(&self) -> bool { - *self == IrqPause::RunTimer - } - #[doc = "Stop the timer"] - #[inline(always)] - pub fn is_pause_timer(&self) -> bool { - *self == IrqPause::PauseTimer - } -} -#[doc = "Field `IRQ_PAUSE` writer - IRQ pause control"] -pub type IrqPauseW<'a, REG> = crate::FieldWriter<'a, REG, 2, IrqPause>; -impl<'a, REG> IrqPauseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Keep the timer running"] - #[inline(always)] - pub fn run_timer(self) -> &'a mut crate::W { - self.variant(IrqPause::RunTimer) - } - #[doc = "Stop the timer"] - #[inline(always)] - pub fn pause_timer(self) -> &'a mut crate::W { - self.variant(IrqPause::PauseTimer) - } -} -#[doc = "DEBUG_HALT control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum DebugHaltCtrl { - #[doc = "1: Keep the timer running"] - RunTimer = 1, - #[doc = "2: Stop the timer"] - PauseTimer = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: DebugHaltCtrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for DebugHaltCtrl { - type Ux = u8; -} -impl crate::IsEnum for DebugHaltCtrl {} -#[doc = "Field `DEBUG_HALT_CTRL` reader - DEBUG_HALT control"] -pub type DebugHaltCtrlR = crate::FieldReader; -impl DebugHaltCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(DebugHaltCtrl::RunTimer), - 2 => Some(DebugHaltCtrl::PauseTimer), - _ => None, - } - } - #[doc = "Keep the timer running"] - #[inline(always)] - pub fn is_run_timer(&self) -> bool { - *self == DebugHaltCtrl::RunTimer - } - #[doc = "Stop the timer"] - #[inline(always)] - pub fn is_pause_timer(&self) -> bool { - *self == DebugHaltCtrl::PauseTimer - } -} -#[doc = "Field `DEBUG_HALT_CTRL` writer - DEBUG_HALT control"] -pub type DebugHaltCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, DebugHaltCtrl>; -impl<'a, REG> DebugHaltCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Keep the timer running"] - #[inline(always)] - pub fn run_timer(self) -> &'a mut crate::W { - self.variant(DebugHaltCtrl::RunTimer) - } - #[doc = "Stop the timer"] - #[inline(always)] - pub fn pause_timer(self) -> &'a mut crate::W { - self.variant(DebugHaltCtrl::PauseTimer) - } -} -impl R { - #[doc = "Bits 0:1 - Lock control"] - #[inline(always)] - pub fn lock_ctrl(&self) -> LockCtrlR { - LockCtrlR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:4 - TIMEOUT fault control"] - #[inline(always)] - pub fn timeout_ctrl(&self) -> TimeoutCtrlR { - TimeoutCtrlR::new(((self.bits >> 2) & 7) as u8) - } - #[doc = "Bits 5:7 - MISCOMPARE fault control"] - #[inline(always)] - pub fn miscompare_ctrl(&self) -> MiscompareCtrlR { - MiscompareCtrlR::new(((self.bits >> 5) & 7) as u8) - } - #[doc = "Bits 8:10 - SEQUENCE fault control"] - #[inline(always)] - pub fn sequence_ctrl(&self) -> SequenceCtrlR { - SequenceCtrlR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 14:16 - STATE fault control"] - #[inline(always)] - pub fn state_ctrl(&self) -> StateCtrlR { - StateCtrlR::new(((self.bits >> 14) & 7) as u8) - } - #[doc = "Bits 17:19 - ADDRESS fault control"] - #[inline(always)] - pub fn address_ctrl(&self) -> AddressCtrlR { - AddressCtrlR::new(((self.bits >> 17) & 7) as u8) - } - #[doc = "Bits 28:29 - IRQ pause control"] - #[inline(always)] - pub fn irq_pause(&self) -> IrqPauseR { - IrqPauseR::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bits 30:31 - DEBUG_HALT control"] - #[inline(always)] - pub fn debug_halt_ctrl(&self) -> DebugHaltCtrlR { - DebugHaltCtrlR::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Lock control"] - #[inline(always)] - pub fn lock_ctrl(&mut self) -> LockCtrlW { - LockCtrlW::new(self, 0) - } - #[doc = "Bits 2:4 - TIMEOUT fault control"] - #[inline(always)] - pub fn timeout_ctrl(&mut self) -> TimeoutCtrlW { - TimeoutCtrlW::new(self, 2) - } - #[doc = "Bits 5:7 - MISCOMPARE fault control"] - #[inline(always)] - pub fn miscompare_ctrl(&mut self) -> MiscompareCtrlW { - MiscompareCtrlW::new(self, 5) - } - #[doc = "Bits 8:10 - SEQUENCE fault control"] - #[inline(always)] - pub fn sequence_ctrl(&mut self) -> SequenceCtrlW { - SequenceCtrlW::new(self, 8) - } - #[doc = "Bits 14:16 - STATE fault control"] - #[inline(always)] - pub fn state_ctrl(&mut self) -> StateCtrlW { - StateCtrlW::new(self, 14) - } - #[doc = "Bits 17:19 - ADDRESS fault control"] - #[inline(always)] - pub fn address_ctrl(&mut self) -> AddressCtrlW { - AddressCtrlW::new(self, 17) - } - #[doc = "Bits 28:29 - IRQ pause control"] - #[inline(always)] - pub fn irq_pause(&mut self) -> IrqPauseW { - IrqPauseW::new(self, 28) - } - #[doc = "Bits 30:31 - DEBUG_HALT control"] - #[inline(always)] - pub fn debug_halt_ctrl(&mut self) -> DebugHaltCtrlW { - DebugHaltCtrlW::new(self, 30) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ControlSpec; -impl crate::RegisterSpec for ControlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`control::R`](R) reader structure"] -impl crate::Readable for ControlSpec {} -#[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"] -impl crate::Writable for ControlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CONTROL to value 0x5009_2492"] -impl crate::Resettable for ControlSpec { - const RESET_VALUE: u32 = 0x5009_2492; -} diff --git a/mcxa276-pac/src/cdog0/flags.rs b/mcxa276-pac/src/cdog0/flags.rs deleted file mode 100644 index 1ab254e8c..000000000 --- a/mcxa276-pac/src/cdog0/flags.rs +++ /dev/null @@ -1,465 +0,0 @@ -#[doc = "Register `FLAGS` reader"] -pub type R = crate::R; -#[doc = "Register `FLAGS` writer"] -pub type W = crate::W; -#[doc = "TIMEOUT fault flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ToFlag { - #[doc = "0: A TIMEOUT fault has not occurred"] - NoFlag = 0, - #[doc = "1: A TIMEOUT fault has occurred"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ToFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TO_FLAG` reader - TIMEOUT fault flag"] -pub type ToFlagR = crate::BitReader; -impl ToFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ToFlag { - match self.bits { - false => ToFlag::NoFlag, - true => ToFlag::Flag, - } - } - #[doc = "A TIMEOUT fault has not occurred"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == ToFlag::NoFlag - } - #[doc = "A TIMEOUT fault has occurred"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == ToFlag::Flag - } -} -#[doc = "Field `TO_FLAG` writer - TIMEOUT fault flag"] -pub type ToFlagW<'a, REG> = crate::BitWriter1C<'a, REG, ToFlag>; -impl<'a, REG> ToFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A TIMEOUT fault has not occurred"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(ToFlag::NoFlag) - } - #[doc = "A TIMEOUT fault has occurred"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(ToFlag::Flag) - } -} -#[doc = "MISCOMPARE fault flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum MiscomFlag { - #[doc = "0: A MISCOMPARE fault has not occurred"] - NoFlag = 0, - #[doc = "1: A MISCOMPARE fault has occurred"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: MiscomFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MISCOM_FLAG` reader - MISCOMPARE fault flag"] -pub type MiscomFlagR = crate::BitReader; -impl MiscomFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> MiscomFlag { - match self.bits { - false => MiscomFlag::NoFlag, - true => MiscomFlag::Flag, - } - } - #[doc = "A MISCOMPARE fault has not occurred"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == MiscomFlag::NoFlag - } - #[doc = "A MISCOMPARE fault has occurred"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == MiscomFlag::Flag - } -} -#[doc = "Field `MISCOM_FLAG` writer - MISCOMPARE fault flag"] -pub type MiscomFlagW<'a, REG> = crate::BitWriter1C<'a, REG, MiscomFlag>; -impl<'a, REG> MiscomFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A MISCOMPARE fault has not occurred"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(MiscomFlag::NoFlag) - } - #[doc = "A MISCOMPARE fault has occurred"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(MiscomFlag::Flag) - } -} -#[doc = "SEQUENCE fault flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SeqFlag { - #[doc = "0: A SEQUENCE fault has not occurred"] - NoFlag = 0, - #[doc = "1: A SEQUENCE fault has occurred"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SeqFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SEQ_FLAG` reader - SEQUENCE fault flag"] -pub type SeqFlagR = crate::BitReader; -impl SeqFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SeqFlag { - match self.bits { - false => SeqFlag::NoFlag, - true => SeqFlag::Flag, - } - } - #[doc = "A SEQUENCE fault has not occurred"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == SeqFlag::NoFlag - } - #[doc = "A SEQUENCE fault has occurred"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == SeqFlag::Flag - } -} -#[doc = "Field `SEQ_FLAG` writer - SEQUENCE fault flag"] -pub type SeqFlagW<'a, REG> = crate::BitWriter1C<'a, REG, SeqFlag>; -impl<'a, REG> SeqFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A SEQUENCE fault has not occurred"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(SeqFlag::NoFlag) - } - #[doc = "A SEQUENCE fault has occurred"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(SeqFlag::Flag) - } -} -#[doc = "CONTROL fault flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CntFlag { - #[doc = "0: A CONTROL fault has not occurred"] - NoFlag = 0, - #[doc = "1: A CONTROL fault has occurred"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CntFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CNT_FLAG` reader - CONTROL fault flag"] -pub type CntFlagR = crate::BitReader; -impl CntFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CntFlag { - match self.bits { - false => CntFlag::NoFlag, - true => CntFlag::Flag, - } - } - #[doc = "A CONTROL fault has not occurred"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == CntFlag::NoFlag - } - #[doc = "A CONTROL fault has occurred"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == CntFlag::Flag - } -} -#[doc = "Field `CNT_FLAG` writer - CONTROL fault flag"] -pub type CntFlagW<'a, REG> = crate::BitWriter1C<'a, REG, CntFlag>; -impl<'a, REG> CntFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A CONTROL fault has not occurred"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(CntFlag::NoFlag) - } - #[doc = "A CONTROL fault has occurred"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(CntFlag::Flag) - } -} -#[doc = "STATE fault flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StateFlag { - #[doc = "0: A STATE fault has not occurred"] - NoFlag = 0, - #[doc = "1: A STATE fault has occurred"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StateFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STATE_FLAG` reader - STATE fault flag"] -pub type StateFlagR = crate::BitReader; -impl StateFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StateFlag { - match self.bits { - false => StateFlag::NoFlag, - true => StateFlag::Flag, - } - } - #[doc = "A STATE fault has not occurred"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == StateFlag::NoFlag - } - #[doc = "A STATE fault has occurred"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == StateFlag::Flag - } -} -#[doc = "Field `STATE_FLAG` writer - STATE fault flag"] -pub type StateFlagW<'a, REG> = crate::BitWriter1C<'a, REG, StateFlag>; -impl<'a, REG> StateFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A STATE fault has not occurred"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(StateFlag::NoFlag) - } - #[doc = "A STATE fault has occurred"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(StateFlag::Flag) - } -} -#[doc = "ADDRESS fault flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum AddrFlag { - #[doc = "0: An ADDRESS fault has not occurred"] - NoFlag = 0, - #[doc = "1: An ADDRESS fault has occurred"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: AddrFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADDR_FLAG` reader - ADDRESS fault flag"] -pub type AddrFlagR = crate::BitReader; -impl AddrFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> AddrFlag { - match self.bits { - false => AddrFlag::NoFlag, - true => AddrFlag::Flag, - } - } - #[doc = "An ADDRESS fault has not occurred"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == AddrFlag::NoFlag - } - #[doc = "An ADDRESS fault has occurred"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == AddrFlag::Flag - } -} -#[doc = "Field `ADDR_FLAG` writer - ADDRESS fault flag"] -pub type AddrFlagW<'a, REG> = crate::BitWriter1C<'a, REG, AddrFlag>; -impl<'a, REG> AddrFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "An ADDRESS fault has not occurred"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(AddrFlag::NoFlag) - } - #[doc = "An ADDRESS fault has occurred"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(AddrFlag::Flag) - } -} -#[doc = "Power-on reset flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PorFlag { - #[doc = "0: A Power-on reset event has not occurred"] - NoFlag = 0, - #[doc = "1: A Power-on reset event has occurred"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PorFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POR_FLAG` reader - Power-on reset flag"] -pub type PorFlagR = crate::BitReader; -impl PorFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PorFlag { - match self.bits { - false => PorFlag::NoFlag, - true => PorFlag::Flag, - } - } - #[doc = "A Power-on reset event has not occurred"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == PorFlag::NoFlag - } - #[doc = "A Power-on reset event has occurred"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == PorFlag::Flag - } -} -#[doc = "Field `POR_FLAG` writer - Power-on reset flag"] -pub type PorFlagW<'a, REG> = crate::BitWriter1C<'a, REG, PorFlag>; -impl<'a, REG> PorFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A Power-on reset event has not occurred"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(PorFlag::NoFlag) - } - #[doc = "A Power-on reset event has occurred"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(PorFlag::Flag) - } -} -impl R { - #[doc = "Bit 0 - TIMEOUT fault flag"] - #[inline(always)] - pub fn to_flag(&self) -> ToFlagR { - ToFlagR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - MISCOMPARE fault flag"] - #[inline(always)] - pub fn miscom_flag(&self) -> MiscomFlagR { - MiscomFlagR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - SEQUENCE fault flag"] - #[inline(always)] - pub fn seq_flag(&self) -> SeqFlagR { - SeqFlagR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - CONTROL fault flag"] - #[inline(always)] - pub fn cnt_flag(&self) -> CntFlagR { - CntFlagR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - STATE fault flag"] - #[inline(always)] - pub fn state_flag(&self) -> StateFlagR { - StateFlagR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - ADDRESS fault flag"] - #[inline(always)] - pub fn addr_flag(&self) -> AddrFlagR { - AddrFlagR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 16 - Power-on reset flag"] - #[inline(always)] - pub fn por_flag(&self) -> PorFlagR { - PorFlagR::new(((self.bits >> 16) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - TIMEOUT fault flag"] - #[inline(always)] - pub fn to_flag(&mut self) -> ToFlagW { - ToFlagW::new(self, 0) - } - #[doc = "Bit 1 - MISCOMPARE fault flag"] - #[inline(always)] - pub fn miscom_flag(&mut self) -> MiscomFlagW { - MiscomFlagW::new(self, 1) - } - #[doc = "Bit 2 - SEQUENCE fault flag"] - #[inline(always)] - pub fn seq_flag(&mut self) -> SeqFlagW { - SeqFlagW::new(self, 2) - } - #[doc = "Bit 3 - CONTROL fault flag"] - #[inline(always)] - pub fn cnt_flag(&mut self) -> CntFlagW { - CntFlagW::new(self, 3) - } - #[doc = "Bit 4 - STATE fault flag"] - #[inline(always)] - pub fn state_flag(&mut self) -> StateFlagW { - StateFlagW::new(self, 4) - } - #[doc = "Bit 5 - ADDRESS fault flag"] - #[inline(always)] - pub fn addr_flag(&mut self) -> AddrFlagW { - AddrFlagW::new(self, 5) - } - #[doc = "Bit 16 - Power-on reset flag"] - #[inline(always)] - pub fn por_flag(&mut self) -> PorFlagW { - PorFlagW::new(self, 16) - } -} -#[doc = "Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flags::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flags::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlagsSpec; -impl crate::RegisterSpec for FlagsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flags::R`](R) reader structure"] -impl crate::Readable for FlagsSpec {} -#[doc = "`write(|w| ..)` method takes [`flags::W`](W) writer structure"] -impl crate::Writable for FlagsSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0001_003f; -} -#[doc = "`reset()` method sets FLAGS to value 0x0001_0000"] -impl crate::Resettable for FlagsSpec { - const RESET_VALUE: u32 = 0x0001_0000; -} diff --git a/mcxa276-pac/src/cdog0/instruction_timer.rs b/mcxa276-pac/src/cdog0/instruction_timer.rs deleted file mode 100644 index b0eff2d6a..000000000 --- a/mcxa276-pac/src/cdog0/instruction_timer.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `INSTRUCTION_TIMER` reader"] -pub type R = crate::R; -#[doc = "Field `INSTIM` reader - Current value of the Instruction Timer"] -pub type InstimR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Current value of the Instruction Timer"] - #[inline(always)] - pub fn instim(&self) -> InstimR { - InstimR::new(self.bits) - } -} -#[doc = "Instruction Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`instruction_timer::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct InstructionTimerSpec; -impl crate::RegisterSpec for InstructionTimerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`instruction_timer::R`](R) reader structure"] -impl crate::Readable for InstructionTimerSpec {} -#[doc = "`reset()` method sets INSTRUCTION_TIMER to value 0xffff_ffff"] -impl crate::Resettable for InstructionTimerSpec { - const RESET_VALUE: u32 = 0xffff_ffff; -} diff --git a/mcxa276-pac/src/cdog0/persistent.rs b/mcxa276-pac/src/cdog0/persistent.rs deleted file mode 100644 index 3cce57e04..000000000 --- a/mcxa276-pac/src/cdog0/persistent.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PERSISTENT` reader"] -pub type R = crate::R; -#[doc = "Register `PERSISTENT` writer"] -pub type W = crate::W; -#[doc = "Field `PERSIS` reader - Persistent Storage"] -pub type PersisR = crate::FieldReader; -#[doc = "Field `PERSIS` writer - Persistent Storage"] -pub type PersisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Persistent Storage"] - #[inline(always)] - pub fn persis(&self) -> PersisR { - PersisR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Persistent Storage"] - #[inline(always)] - pub fn persis(&mut self) -> PersisW { - PersisW::new(self, 0) - } -} -#[doc = "Persistent Data Storage Register\n\nYou can [`read`](crate::Reg::read) this register and get [`persistent::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`persistent::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PersistentSpec; -impl crate::RegisterSpec for PersistentSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`persistent::R`](R) reader structure"] -impl crate::Readable for PersistentSpec {} -#[doc = "`write(|w| ..)` method takes [`persistent::W`](W) writer structure"] -impl crate::Writable for PersistentSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PERSISTENT to value 0"] -impl crate::Resettable for PersistentSpec {} diff --git a/mcxa276-pac/src/cdog0/reload.rs b/mcxa276-pac/src/cdog0/reload.rs deleted file mode 100644 index 78a96ff6e..000000000 --- a/mcxa276-pac/src/cdog0/reload.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `RELOAD` reader"] -pub type R = crate::R; -#[doc = "Register `RELOAD` writer"] -pub type W = crate::W; -#[doc = "Field `RLOAD` reader - Instruction Timer reload value"] -pub type RloadR = crate::FieldReader; -#[doc = "Field `RLOAD` writer - Instruction Timer reload value"] -pub type RloadW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Instruction Timer reload value"] - #[inline(always)] - pub fn rload(&self) -> RloadR { - RloadR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Instruction Timer reload value"] - #[inline(always)] - pub fn rload(&mut self) -> RloadW { - RloadW::new(self, 0) - } -} -#[doc = "Instruction Timer Reload Register\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ReloadSpec; -impl crate::RegisterSpec for ReloadSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`reload::R`](R) reader structure"] -impl crate::Readable for ReloadSpec {} -#[doc = "`write(|w| ..)` method takes [`reload::W`](W) writer structure"] -impl crate::Writable for ReloadSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RELOAD to value 0xffff_ffff"] -impl crate::Resettable for ReloadSpec { - const RESET_VALUE: u32 = 0xffff_ffff; -} diff --git a/mcxa276-pac/src/cdog0/restart.rs b/mcxa276-pac/src/cdog0/restart.rs deleted file mode 100644 index 5061b53c6..000000000 --- a/mcxa276-pac/src/cdog0/restart.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `RESTART` writer"] -pub type W = crate::W; -#[doc = "Field `RSTRT` writer - Restart command"] -pub type RstrtW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Restart command"] - #[inline(always)] - pub fn rstrt(&mut self) -> RstrtW { - RstrtW::new(self, 0) - } -} -#[doc = "RESTART Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`restart::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RestartSpec; -impl crate::RegisterSpec for RestartSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`restart::W`](W) writer structure"] -impl crate::Writable for RestartSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RESTART to value 0"] -impl crate::Resettable for RestartSpec {} diff --git a/mcxa276-pac/src/cdog0/start.rs b/mcxa276-pac/src/cdog0/start.rs deleted file mode 100644 index ea2ba9cde..000000000 --- a/mcxa276-pac/src/cdog0/start.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `START` writer"] -pub type W = crate::W; -#[doc = "Field `STRT` writer - Start command"] -pub type StrtW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Start command"] - #[inline(always)] - pub fn strt(&mut self) -> StrtW { - StrtW::new(self, 0) - } -} -#[doc = "START Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StartSpec; -impl crate::RegisterSpec for StartSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`start::W`](W) writer structure"] -impl crate::Writable for StartSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets START to value 0"] -impl crate::Resettable for StartSpec {} diff --git a/mcxa276-pac/src/cdog0/status.rs b/mcxa276-pac/src/cdog0/status.rs deleted file mode 100644 index 3fa1e0604..000000000 --- a/mcxa276-pac/src/cdog0/status.rs +++ /dev/null @@ -1,43 +0,0 @@ -#[doc = "Register `STATUS` reader"] -pub type R = crate::R; -#[doc = "Field `NUMTOF` reader - Number of TIMEOUT faults (FLAGS\\[TIMEOUT_FLAG\\]) since the last POR"] -pub type NumtofR = crate::FieldReader; -#[doc = "Field `NUMMISCOMPF` reader - Number of MISCOMPARE faults (FLAGS\\[MISCOMPARE_FLAG\\]) since the last POR"] -pub type NummiscompfR = crate::FieldReader; -#[doc = "Field `NUMILSEQF` reader - Number of SEQUENCE faults (FLAGS\\[SEQUENCE_FLAG\\]) since the last POR"] -pub type NumilseqfR = crate::FieldReader; -#[doc = "Field `CURST` reader - Current State"] -pub type CurstR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Number of TIMEOUT faults (FLAGS\\[TIMEOUT_FLAG\\]) since the last POR"] - #[inline(always)] - pub fn numtof(&self) -> NumtofR { - NumtofR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Number of MISCOMPARE faults (FLAGS\\[MISCOMPARE_FLAG\\]) since the last POR"] - #[inline(always)] - pub fn nummiscompf(&self) -> NummiscompfR { - NummiscompfR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Number of SEQUENCE faults (FLAGS\\[SEQUENCE_FLAG\\]) since the last POR"] - #[inline(always)] - pub fn numilseqf(&self) -> NumilseqfR { - NumilseqfR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 28:31 - Current State"] - #[inline(always)] - pub fn curst(&self) -> CurstR { - CurstR::new(((self.bits >> 28) & 0x0f) as u8) - } -} -#[doc = "Status 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StatusSpec; -impl crate::RegisterSpec for StatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`status::R`](R) reader structure"] -impl crate::Readable for StatusSpec {} -#[doc = "`reset()` method sets STATUS to value 0x5000_0000"] -impl crate::Resettable for StatusSpec { - const RESET_VALUE: u32 = 0x5000_0000; -} diff --git a/mcxa276-pac/src/cdog0/status2.rs b/mcxa276-pac/src/cdog0/status2.rs deleted file mode 100644 index 57b68032f..000000000 --- a/mcxa276-pac/src/cdog0/status2.rs +++ /dev/null @@ -1,34 +0,0 @@ -#[doc = "Register `STATUS2` reader"] -pub type R = crate::R; -#[doc = "Field `NUMCNTF` reader - Number of CONTROL faults (FLAGS\\[CONTROL_FLAG\\]) since the last POR"] -pub type NumcntfR = crate::FieldReader; -#[doc = "Field `NUMILLSTF` reader - Number of STATE faults (FLAGS\\[STATE_FLAG\\]) since the last POR"] -pub type NumillstfR = crate::FieldReader; -#[doc = "Field `NUMILLA` reader - Number of ADDRESS faults (FLAGS\\[ADDR_FLAG\\]) since the last POR"] -pub type NumillaR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Number of CONTROL faults (FLAGS\\[CONTROL_FLAG\\]) since the last POR"] - #[inline(always)] - pub fn numcntf(&self) -> NumcntfR { - NumcntfR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Number of STATE faults (FLAGS\\[STATE_FLAG\\]) since the last POR"] - #[inline(always)] - pub fn numillstf(&self) -> NumillstfR { - NumillstfR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Number of ADDRESS faults (FLAGS\\[ADDR_FLAG\\]) since the last POR"] - #[inline(always)] - pub fn numilla(&self) -> NumillaR { - NumillaR::new(((self.bits >> 16) & 0xff) as u8) - } -} -#[doc = "Status 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Status2Spec; -impl crate::RegisterSpec for Status2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`status2::R`](R) reader structure"] -impl crate::Readable for Status2Spec {} -#[doc = "`reset()` method sets STATUS2 to value 0"] -impl crate::Resettable for Status2Spec {} diff --git a/mcxa276-pac/src/cdog0/stop.rs b/mcxa276-pac/src/cdog0/stop.rs deleted file mode 100644 index dedaaac8d..000000000 --- a/mcxa276-pac/src/cdog0/stop.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `STOP` writer"] -pub type W = crate::W; -#[doc = "Field `STP` writer - Stop command"] -pub type StpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Stop command"] - #[inline(always)] - pub fn stp(&mut self) -> StpW { - StpW::new(self, 0) - } -} -#[doc = "STOP Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stop::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StopSpec; -impl crate::RegisterSpec for StopSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`stop::W`](W) writer structure"] -impl crate::Writable for StopSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STOP to value 0"] -impl crate::Resettable for StopSpec {} diff --git a/mcxa276-pac/src/cdog0/sub.rs b/mcxa276-pac/src/cdog0/sub.rs deleted file mode 100644 index e8351bdc2..000000000 --- a/mcxa276-pac/src/cdog0/sub.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SUB` writer"] -pub type W = crate::W; -#[doc = "Field `SB` writer - Subtract Write Value"] -pub type SbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Subtract Write Value"] - #[inline(always)] - pub fn sb(&mut self) -> SbW { - SbW::new(self, 0) - } -} -#[doc = "SUB Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SubSpec; -impl crate::RegisterSpec for SubSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`sub::W`](W) writer structure"] -impl crate::Writable for SubSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SUB to value 0"] -impl crate::Resettable for SubSpec {} diff --git a/mcxa276-pac/src/cdog0/sub1.rs b/mcxa276-pac/src/cdog0/sub1.rs deleted file mode 100644 index 61ae47103..000000000 --- a/mcxa276-pac/src/cdog0/sub1.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SUB1` writer"] -pub type W = crate::W; -#[doc = "Field `SB1` writer - Subtract 1"] -pub type Sb1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Subtract 1"] - #[inline(always)] - pub fn sb1(&mut self) -> Sb1W { - Sb1W::new(self, 0) - } -} -#[doc = "SUB1 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sub1Spec; -impl crate::RegisterSpec for Sub1Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`sub1::W`](W) writer structure"] -impl crate::Writable for Sub1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SUB1 to value 0"] -impl crate::Resettable for Sub1Spec {} diff --git a/mcxa276-pac/src/cdog0/sub16.rs b/mcxa276-pac/src/cdog0/sub16.rs deleted file mode 100644 index be61a4821..000000000 --- a/mcxa276-pac/src/cdog0/sub16.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SUB16` writer"] -pub type W = crate::W; -#[doc = "Field `SB16` writer - Subtract 16"] -pub type Sb16W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Subtract 16"] - #[inline(always)] - pub fn sb16(&mut self) -> Sb16W { - Sb16W::new(self, 0) - } -} -#[doc = "SUB16 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub16::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sub16Spec; -impl crate::RegisterSpec for Sub16Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`sub16::W`](W) writer structure"] -impl crate::Writable for Sub16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SUB16 to value 0"] -impl crate::Resettable for Sub16Spec {} diff --git a/mcxa276-pac/src/cdog0/sub256.rs b/mcxa276-pac/src/cdog0/sub256.rs deleted file mode 100644 index 68a53c4ce..000000000 --- a/mcxa276-pac/src/cdog0/sub256.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SUB256` writer"] -pub type W = crate::W; -#[doc = "Field `SB256` writer - Subtract 256"] -pub type Sb256W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Subtract 256"] - #[inline(always)] - pub fn sb256(&mut self) -> Sb256W { - Sb256W::new(self, 0) - } -} -#[doc = "SUB256 Command Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sub256::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sub256Spec; -impl crate::RegisterSpec for Sub256Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`sub256::W`](W) writer structure"] -impl crate::Writable for Sub256Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SUB256 to value 0"] -impl crate::Resettable for Sub256Spec {} diff --git a/mcxa276-pac/src/cmc.rs b/mcxa276-pac/src/cmc.rs deleted file mode 100644 index cb40e7748..000000000 --- a/mcxa276-pac/src/cmc.rs +++ /dev/null @@ -1,189 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x0c], - ckctrl: Ckctrl, - ckstat: Ckstat, - pmprot: Pmprot, - gpmctrl: Gpmctrl, - pmctrlmain: Pmctrlmain, - _reserved6: [u8; 0x5c], - srs: Srs, - rpc: Rpc, - ssrs: Ssrs, - srie: Srie, - srif: Srif, - _reserved11: [u8; 0x0c], - mr0: Mr0, - _reserved12: [u8; 0x0c], - fm0: Fm0, - _reserved13: [u8; 0x2c], - flashcr: Flashcr, - _reserved14: [u8; 0x2c], - corectl: Corectl, - _reserved15: [u8; 0x0c], - dbgctl: Dbgctl, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x10 - Clock Control"] - #[inline(always)] - pub const fn ckctrl(&self) -> &Ckctrl { - &self.ckctrl - } - #[doc = "0x14 - Clock Status"] - #[inline(always)] - pub const fn ckstat(&self) -> &Ckstat { - &self.ckstat - } - #[doc = "0x18 - Power Mode Protection"] - #[inline(always)] - pub const fn pmprot(&self) -> &Pmprot { - &self.pmprot - } - #[doc = "0x1c - Global Power Mode Control"] - #[inline(always)] - pub const fn gpmctrl(&self) -> &Gpmctrl { - &self.gpmctrl - } - #[doc = "0x20 - Power Mode Control"] - #[inline(always)] - pub const fn pmctrlmain(&self) -> &Pmctrlmain { - &self.pmctrlmain - } - #[doc = "0x80 - System Reset Status"] - #[inline(always)] - pub const fn srs(&self) -> &Srs { - &self.srs - } - #[doc = "0x84 - Reset Pin Control"] - #[inline(always)] - pub const fn rpc(&self) -> &Rpc { - &self.rpc - } - #[doc = "0x88 - Sticky System Reset Status"] - #[inline(always)] - pub const fn ssrs(&self) -> &Ssrs { - &self.ssrs - } - #[doc = "0x8c - System Reset Interrupt Enable"] - #[inline(always)] - pub const fn srie(&self) -> &Srie { - &self.srie - } - #[doc = "0x90 - System Reset Interrupt Flag"] - #[inline(always)] - pub const fn srif(&self) -> &Srif { - &self.srif - } - #[doc = "0xa0 - Mode"] - #[inline(always)] - pub const fn mr0(&self) -> &Mr0 { - &self.mr0 - } - #[doc = "0xb0 - Force Mode"] - #[inline(always)] - pub const fn fm0(&self) -> &Fm0 { - &self.fm0 - } - #[doc = "0xe0 - Flash Control"] - #[inline(always)] - pub const fn flashcr(&self) -> &Flashcr { - &self.flashcr - } - #[doc = "0x110 - Core Control"] - #[inline(always)] - pub const fn corectl(&self) -> &Corectl { - &self.corectl - } - #[doc = "0x120 - Debug Control"] - #[inline(always)] - pub const fn dbgctl(&self) -> &Dbgctl { - &self.dbgctl - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "CKCTRL (rw) register accessor: Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ckctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ckctrl`] module"] -#[doc(alias = "CKCTRL")] -pub type Ckctrl = crate::Reg; -#[doc = "Clock Control"] -pub mod ckctrl; -#[doc = "CKSTAT (rw) register accessor: Clock Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ckstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ckstat`] module"] -#[doc(alias = "CKSTAT")] -pub type Ckstat = crate::Reg; -#[doc = "Clock Status"] -pub mod ckstat; -#[doc = "PMPROT (rw) register accessor: Power Mode Protection\n\nYou can [`read`](crate::Reg::read) this register and get [`pmprot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmprot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmprot`] module"] -#[doc(alias = "PMPROT")] -pub type Pmprot = crate::Reg; -#[doc = "Power Mode Protection"] -pub mod pmprot; -#[doc = "GPMCTRL (rw) register accessor: Global Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gpmctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpmctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpmctrl`] module"] -#[doc(alias = "GPMCTRL")] -pub type Gpmctrl = crate::Reg; -#[doc = "Global Power Mode Control"] -pub mod gpmctrl; -#[doc = "PMCTRLMAIN (rw) register accessor: Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pmctrlmain::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmctrlmain::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmctrlmain`] module"] -#[doc(alias = "PMCTRLMAIN")] -pub type Pmctrlmain = crate::Reg; -#[doc = "Power Mode Control"] -pub mod pmctrlmain; -#[doc = "SRS (r) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`srs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srs`] module"] -#[doc(alias = "SRS")] -pub type Srs = crate::Reg; -#[doc = "System Reset Status"] -pub mod srs; -#[doc = "RPC (rw) register accessor: Reset Pin Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rpc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpc`] module"] -#[doc(alias = "RPC")] -pub type Rpc = crate::Reg; -#[doc = "Reset Pin Control"] -pub mod rpc; -#[doc = "SSRS (rw) register accessor: Sticky System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssrs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssrs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssrs`] module"] -#[doc(alias = "SSRS")] -pub type Ssrs = crate::Reg; -#[doc = "Sticky System Reset Status"] -pub mod ssrs; -#[doc = "SRIE (rw) register accessor: System Reset Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`srie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srie`] module"] -#[doc(alias = "SRIE")] -pub type Srie = crate::Reg; -#[doc = "System Reset Interrupt Enable"] -pub mod srie; -#[doc = "SRIF (rw) register accessor: System Reset Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`srif::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srif::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srif`] module"] -#[doc(alias = "SRIF")] -pub type Srif = crate::Reg; -#[doc = "System Reset Interrupt Flag"] -pub mod srif; -#[doc = "MR0 (rw) register accessor: Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr0`] module"] -#[doc(alias = "MR0")] -pub type Mr0 = crate::Reg; -#[doc = "Mode"] -pub mod mr0; -#[doc = "FM0 (rw) register accessor: Force Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`fm0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fm0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fm0`] module"] -#[doc(alias = "FM0")] -pub type Fm0 = crate::Reg; -#[doc = "Force Mode"] -pub mod fm0; -#[doc = "FLASHCR (rw) register accessor: Flash Control\n\nYou can [`read`](crate::Reg::read) this register and get [`flashcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashcr`] module"] -#[doc(alias = "FLASHCR")] -pub type Flashcr = crate::Reg; -#[doc = "Flash Control"] -pub mod flashcr; -#[doc = "CORECTL (rw) register accessor: Core Control\n\nYou can [`read`](crate::Reg::read) this register and get [`corectl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corectl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@corectl`] module"] -#[doc(alias = "CORECTL")] -pub type Corectl = crate::Reg; -#[doc = "Core Control"] -pub mod corectl; -#[doc = "DBGCTL (rw) register accessor: Debug Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dbgctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbgctl`] module"] -#[doc(alias = "DBGCTL")] -pub type Dbgctl = crate::Reg; -#[doc = "Debug Control"] -pub mod dbgctl; diff --git a/mcxa276-pac/src/cmc/ckctrl.rs b/mcxa276-pac/src/cmc/ckctrl.rs deleted file mode 100644 index 32c829009..000000000 --- a/mcxa276-pac/src/cmc/ckctrl.rs +++ /dev/null @@ -1,167 +0,0 @@ -#[doc = "Register `CKCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CKCTRL` writer"] -pub type W = crate::W; -#[doc = "Clocking Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ckmode { - #[doc = "0: Core clock is on"] - Ckmode0000 = 0, - #[doc = "1: Core clock is off"] - Ckmode0001 = 1, - #[doc = "15: Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] - Ckmode1111 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ckmode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ckmode { - type Ux = u8; -} -impl crate::IsEnum for Ckmode {} -#[doc = "Field `CKMODE` reader - Clocking Mode"] -pub type CkmodeR = crate::FieldReader; -impl CkmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ckmode::Ckmode0000), - 1 => Some(Ckmode::Ckmode0001), - 15 => Some(Ckmode::Ckmode1111), - _ => None, - } - } - #[doc = "Core clock is on"] - #[inline(always)] - pub fn is_ckmode0000(&self) -> bool { - *self == Ckmode::Ckmode0000 - } - #[doc = "Core clock is off"] - #[inline(always)] - pub fn is_ckmode0001(&self) -> bool { - *self == Ckmode::Ckmode0001 - } - #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] - #[inline(always)] - pub fn is_ckmode1111(&self) -> bool { - *self == Ckmode::Ckmode1111 - } -} -#[doc = "Field `CKMODE` writer - Clocking Mode"] -pub type CkmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ckmode>; -impl<'a, REG> CkmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Core clock is on"] - #[inline(always)] - pub fn ckmode0000(self) -> &'a mut crate::W { - self.variant(Ckmode::Ckmode0000) - } - #[doc = "Core clock is off"] - #[inline(always)] - pub fn ckmode0001(self) -> &'a mut crate::W { - self.variant(Ckmode::Ckmode0001) - } - #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] - #[inline(always)] - pub fn ckmode1111(self) -> &'a mut crate::W { - self.variant(Ckmode::Ckmode1111) - } -} -#[doc = "Lock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: Allowed"] - Disabled = 0, - #[doc = "1: Blocked"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - Lock"] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Disabled, - true => Lock::Enabled, - } - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lock::Disabled - } - #[doc = "Blocked"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lock::Enabled - } -} -#[doc = "Field `LOCK` writer - Lock"] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Allowed"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lock::Disabled) - } - #[doc = "Blocked"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lock::Enabled) - } -} -impl R { - #[doc = "Bits 0:3 - Clocking Mode"] - #[inline(always)] - pub fn ckmode(&self) -> CkmodeR { - CkmodeR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 31 - Lock"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Clocking Mode"] - #[inline(always)] - pub fn ckmode(&mut self) -> CkmodeW { - CkmodeW::new(self, 0) - } - #[doc = "Bit 31 - Lock"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 31) - } -} -#[doc = "Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ckctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CkctrlSpec; -impl crate::RegisterSpec for CkctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ckctrl::R`](R) reader structure"] -impl crate::Readable for CkctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ckctrl::W`](W) writer structure"] -impl crate::Writable for CkctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CKCTRL to value 0"] -impl crate::Resettable for CkctrlSpec {} diff --git a/mcxa276-pac/src/cmc/ckstat.rs b/mcxa276-pac/src/cmc/ckstat.rs deleted file mode 100644 index 50cc409bb..000000000 --- a/mcxa276-pac/src/cmc/ckstat.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CKSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `CKSTAT` writer"] -pub type W = crate::W; -#[doc = "Low Power Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ckmode { - #[doc = "0: Core clock is on"] - Ckmode0000 = 0, - #[doc = "1: Core clock is off"] - Ckmode0001 = 1, - #[doc = "15: Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] - Ckmode1111 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ckmode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ckmode { - type Ux = u8; -} -impl crate::IsEnum for Ckmode {} -#[doc = "Field `CKMODE` reader - Low Power Status"] -pub type CkmodeR = crate::FieldReader; -impl CkmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ckmode::Ckmode0000), - 1 => Some(Ckmode::Ckmode0001), - 15 => Some(Ckmode::Ckmode1111), - _ => None, - } - } - #[doc = "Core clock is on"] - #[inline(always)] - pub fn is_ckmode0000(&self) -> bool { - *self == Ckmode::Ckmode0000 - } - #[doc = "Core clock is off"] - #[inline(always)] - pub fn is_ckmode0001(&self) -> bool { - *self == Ckmode::Ckmode0001 - } - #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode"] - #[inline(always)] - pub fn is_ckmode1111(&self) -> bool { - *self == Ckmode::Ckmode1111 - } -} -#[doc = "Field `WAKEUP` reader - Wake-up Source"] -pub type WakeupR = crate::FieldReader; -#[doc = "Clock Status Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Valid { - #[doc = "0: Core clock not gated"] - Disabled = 0, - #[doc = "1: Core clock was gated due to Low-Power mode entry"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Valid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VALID` reader - Clock Status Valid"] -pub type ValidR = crate::BitReader; -impl ValidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Valid { - match self.bits { - false => Valid::Disabled, - true => Valid::Enabled, - } - } - #[doc = "Core clock not gated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Valid::Disabled - } - #[doc = "Core clock was gated due to Low-Power mode entry"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Valid::Enabled - } -} -#[doc = "Field `VALID` writer - Clock Status Valid"] -pub type ValidW<'a, REG> = crate::BitWriter1C<'a, REG, Valid>; -impl<'a, REG> ValidW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Core clock not gated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Valid::Disabled) - } - #[doc = "Core clock was gated due to Low-Power mode entry"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Valid::Enabled) - } -} -impl R { - #[doc = "Bits 0:3 - Low Power Status"] - #[inline(always)] - pub fn ckmode(&self) -> CkmodeR { - CkmodeR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 8:15 - Wake-up Source"] - #[inline(always)] - pub fn wakeup(&self) -> WakeupR { - WakeupR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bit 31 - Clock Status Valid"] - #[inline(always)] - pub fn valid(&self) -> ValidR { - ValidR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 31 - Clock Status Valid"] - #[inline(always)] - pub fn valid(&mut self) -> ValidW { - ValidW::new(self, 31) - } -} -#[doc = "Clock Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ckstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ckstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CkstatSpec; -impl crate::RegisterSpec for CkstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ckstat::R`](R) reader structure"] -impl crate::Readable for CkstatSpec {} -#[doc = "`write(|w| ..)` method takes [`ckstat::W`](W) writer structure"] -impl crate::Writable for CkstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000; -} -#[doc = "`reset()` method sets CKSTAT to value 0"] -impl crate::Resettable for CkstatSpec {} diff --git a/mcxa276-pac/src/cmc/corectl.rs b/mcxa276-pac/src/cmc/corectl.rs deleted file mode 100644 index 693a9681d..000000000 --- a/mcxa276-pac/src/cmc/corectl.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `CORECTL` reader"] -pub type R = crate::R; -#[doc = "Register `CORECTL` writer"] -pub type W = crate::W; -#[doc = "Non-maskable Pin Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npie { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPIE` reader - Non-maskable Pin Interrupt Enable"] -pub type NpieR = crate::BitReader; -impl NpieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npie { - match self.bits { - false => Npie::Disabled, - true => Npie::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Npie::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Npie::Enabled - } -} -#[doc = "Field `NPIE` writer - Non-maskable Pin Interrupt Enable"] -pub type NpieW<'a, REG> = crate::BitWriter<'a, REG, Npie>; -impl<'a, REG> NpieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Npie::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Npie::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Non-maskable Pin Interrupt Enable"] - #[inline(always)] - pub fn npie(&self) -> NpieR { - NpieR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Non-maskable Pin Interrupt Enable"] - #[inline(always)] - pub fn npie(&mut self) -> NpieW { - NpieW::new(self, 0) - } -} -#[doc = "Core Control\n\nYou can [`read`](crate::Reg::read) this register and get [`corectl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corectl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CorectlSpec; -impl crate::RegisterSpec for CorectlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`corectl::R`](R) reader structure"] -impl crate::Readable for CorectlSpec {} -#[doc = "`write(|w| ..)` method takes [`corectl::W`](W) writer structure"] -impl crate::Writable for CorectlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CORECTL to value 0"] -impl crate::Resettable for CorectlSpec {} diff --git a/mcxa276-pac/src/cmc/dbgctl.rs b/mcxa276-pac/src/cmc/dbgctl.rs deleted file mode 100644 index 13a06527c..000000000 --- a/mcxa276-pac/src/cmc/dbgctl.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `DBGCTL` reader"] -pub type R = crate::R; -#[doc = "Register `DBGCTL` writer"] -pub type W = crate::W; -#[doc = "Sleep Or Debug\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sod { - #[doc = "0: Remains enabled"] - Disabled = 0, - #[doc = "1: Disabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sod) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOD` reader - Sleep Or Debug"] -pub type SodR = crate::BitReader; -impl SodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sod { - match self.bits { - false => Sod::Disabled, - true => Sod::Enabled, - } - } - #[doc = "Remains enabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sod::Disabled - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sod::Enabled - } -} -#[doc = "Field `SOD` writer - Sleep Or Debug"] -pub type SodW<'a, REG> = crate::BitWriter<'a, REG, Sod>; -impl<'a, REG> SodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Remains enabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sod::Disabled) - } - #[doc = "Disabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sod::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Sleep Or Debug"] - #[inline(always)] - pub fn sod(&self) -> SodR { - SodR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Sleep Or Debug"] - #[inline(always)] - pub fn sod(&mut self) -> SodW { - SodW::new(self, 0) - } -} -#[doc = "Debug Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dbgctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DbgctlSpec; -impl crate::RegisterSpec for DbgctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`dbgctl::R`](R) reader structure"] -impl crate::Readable for DbgctlSpec {} -#[doc = "`write(|w| ..)` method takes [`dbgctl::W`](W) writer structure"] -impl crate::Writable for DbgctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DBGCTL to value 0"] -impl crate::Resettable for DbgctlSpec {} diff --git a/mcxa276-pac/src/cmc/flashcr.rs b/mcxa276-pac/src/cmc/flashcr.rs deleted file mode 100644 index c196aaaa4..000000000 --- a/mcxa276-pac/src/cmc/flashcr.rs +++ /dev/null @@ -1,210 +0,0 @@ -#[doc = "Register `FLASHCR` reader"] -pub type R = crate::R; -#[doc = "Register `FLASHCR` writer"] -pub type W = crate::W; -#[doc = "Flash Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flashdis { - #[doc = "0: No effect"] - Disabled = 0, - #[doc = "1: Flash memory is disabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flashdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLASHDIS` reader - Flash Disable"] -pub type FlashdisR = crate::BitReader; -impl FlashdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flashdis { - match self.bits { - false => Flashdis::Disabled, - true => Flashdis::Enabled, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flashdis::Disabled - } - #[doc = "Flash memory is disabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flashdis::Enabled - } -} -#[doc = "Field `FLASHDIS` writer - Flash Disable"] -pub type FlashdisW<'a, REG> = crate::BitWriter<'a, REG, Flashdis>; -impl<'a, REG> FlashdisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flashdis::Disabled) - } - #[doc = "Flash memory is disabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flashdis::Enabled) - } -} -#[doc = "Flash Doze\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flashdoze { - #[doc = "0: No effect"] - Disabled = 0, - #[doc = "1: Flash memory is disabled when core is sleeping (CKMODE > 0)"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flashdoze) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLASHDOZE` reader - Flash Doze"] -pub type FlashdozeR = crate::BitReader; -impl FlashdozeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flashdoze { - match self.bits { - false => Flashdoze::Disabled, - true => Flashdoze::Enabled, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flashdoze::Disabled - } - #[doc = "Flash memory is disabled when core is sleeping (CKMODE > 0)"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flashdoze::Enabled - } -} -#[doc = "Field `FLASHDOZE` writer - Flash Doze"] -pub type FlashdozeW<'a, REG> = crate::BitWriter<'a, REG, Flashdoze>; -impl<'a, REG> FlashdozeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flashdoze::Disabled) - } - #[doc = "Flash memory is disabled when core is sleeping (CKMODE > 0)"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flashdoze::Enabled) - } -} -#[doc = "Flash Wake\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flashwake { - #[doc = "0: No effect"] - Disabled = 0, - #[doc = "1: Flash memory is not disabled during flash memory accesses"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flashwake) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLASHWAKE` reader - Flash Wake"] -pub type FlashwakeR = crate::BitReader; -impl FlashwakeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flashwake { - match self.bits { - false => Flashwake::Disabled, - true => Flashwake::Enabled, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flashwake::Disabled - } - #[doc = "Flash memory is not disabled during flash memory accesses"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flashwake::Enabled - } -} -#[doc = "Field `FLASHWAKE` writer - Flash Wake"] -pub type FlashwakeW<'a, REG> = crate::BitWriter<'a, REG, Flashwake>; -impl<'a, REG> FlashwakeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flashwake::Disabled) - } - #[doc = "Flash memory is not disabled during flash memory accesses"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flashwake::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Flash Disable"] - #[inline(always)] - pub fn flashdis(&self) -> FlashdisR { - FlashdisR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Flash Doze"] - #[inline(always)] - pub fn flashdoze(&self) -> FlashdozeR { - FlashdozeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Flash Wake"] - #[inline(always)] - pub fn flashwake(&self) -> FlashwakeR { - FlashwakeR::new(((self.bits >> 2) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Flash Disable"] - #[inline(always)] - pub fn flashdis(&mut self) -> FlashdisW { - FlashdisW::new(self, 0) - } - #[doc = "Bit 1 - Flash Doze"] - #[inline(always)] - pub fn flashdoze(&mut self) -> FlashdozeW { - FlashdozeW::new(self, 1) - } - #[doc = "Bit 2 - Flash Wake"] - #[inline(always)] - pub fn flashwake(&mut self) -> FlashwakeW { - FlashwakeW::new(self, 2) - } -} -#[doc = "Flash Control\n\nYou can [`read`](crate::Reg::read) this register and get [`flashcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlashcrSpec; -impl crate::RegisterSpec for FlashcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flashcr::R`](R) reader structure"] -impl crate::Readable for FlashcrSpec {} -#[doc = "`write(|w| ..)` method takes [`flashcr::W`](W) writer structure"] -impl crate::Writable for FlashcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FLASHCR to value 0"] -impl crate::Resettable for FlashcrSpec {} diff --git a/mcxa276-pac/src/cmc/fm0.rs b/mcxa276-pac/src/cmc/fm0.rs deleted file mode 100644 index 21b886d9e..000000000 --- a/mcxa276-pac/src/cmc/fm0.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `FM0` reader"] -pub type R = crate::R; -#[doc = "Register `FM0` writer"] -pub type W = crate::W; -#[doc = "Boot Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Forcecfg { - #[doc = "0: No effect"] - Disabled = 0, - #[doc = "1: Asserts"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Forcecfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FORCECFG` reader - Boot Configuration"] -pub type ForcecfgR = crate::BitReader; -impl ForcecfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Forcecfg { - match self.bits { - false => Forcecfg::Disabled, - true => Forcecfg::Enabled, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Forcecfg::Disabled - } - #[doc = "Asserts"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Forcecfg::Enabled - } -} -#[doc = "Field `FORCECFG` writer - Boot Configuration"] -pub type ForcecfgW<'a, REG> = crate::BitWriter<'a, REG, Forcecfg>; -impl<'a, REG> ForcecfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Forcecfg::Disabled) - } - #[doc = "Asserts"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Forcecfg::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Boot Configuration"] - #[inline(always)] - pub fn forcecfg(&self) -> ForcecfgR { - ForcecfgR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Boot Configuration"] - #[inline(always)] - pub fn forcecfg(&mut self) -> ForcecfgW { - ForcecfgW::new(self, 0) - } -} -#[doc = "Force Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`fm0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fm0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Fm0Spec; -impl crate::RegisterSpec for Fm0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fm0::R`](R) reader structure"] -impl crate::Readable for Fm0Spec {} -#[doc = "`write(|w| ..)` method takes [`fm0::W`](W) writer structure"] -impl crate::Writable for Fm0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FM0 to value 0"] -impl crate::Resettable for Fm0Spec {} diff --git a/mcxa276-pac/src/cmc/gpmctrl.rs b/mcxa276-pac/src/cmc/gpmctrl.rs deleted file mode 100644 index a9061e1d1..000000000 --- a/mcxa276-pac/src/cmc/gpmctrl.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `GPMCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `GPMCTRL` writer"] -pub type W = crate::W; -#[doc = "Field `LPMODE` reader - Low-Power Mode"] -pub type LpmodeR = crate::FieldReader; -#[doc = "Field `LPMODE` writer - Low-Power Mode"] -pub type LpmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Low-Power Mode"] - #[inline(always)] - pub fn lpmode(&self) -> LpmodeR { - LpmodeR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Low-Power Mode"] - #[inline(always)] - pub fn lpmode(&mut self) -> LpmodeW { - LpmodeW::new(self, 0) - } -} -#[doc = "Global Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gpmctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpmctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpmctrlSpec; -impl crate::RegisterSpec for GpmctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpmctrl::R`](R) reader structure"] -impl crate::Readable for GpmctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`gpmctrl::W`](W) writer structure"] -impl crate::Writable for GpmctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPMCTRL to value 0"] -impl crate::Resettable for GpmctrlSpec {} diff --git a/mcxa276-pac/src/cmc/mr0.rs b/mcxa276-pac/src/cmc/mr0.rs deleted file mode 100644 index 980f4ba52..000000000 --- a/mcxa276-pac/src/cmc/mr0.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `MR0` reader"] -pub type R = crate::R; -#[doc = "Register `MR0` writer"] -pub type W = crate::W; -#[doc = "Field `ISPMODE_n` reader - In System Programming Mode"] -pub type IspmodeNR = crate::BitReader; -#[doc = "Field `ISPMODE_n` writer - In System Programming Mode"] -pub type IspmodeNW<'a, REG> = crate::BitWriter1C<'a, REG>; -impl R { - #[doc = "Bit 0 - In System Programming Mode"] - #[inline(always)] - pub fn ispmode_n(&self) -> IspmodeNR { - IspmodeNR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - In System Programming Mode"] - #[inline(always)] - pub fn ispmode_n(&mut self) -> IspmodeNW { - IspmodeNW::new(self, 0) - } -} -#[doc = "Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mr0Spec; -impl crate::RegisterSpec for Mr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mr0::R`](R) reader structure"] -impl crate::Readable for Mr0Spec {} -#[doc = "`write(|w| ..)` method takes [`mr0::W`](W) writer structure"] -impl crate::Writable for Mr0Spec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; -} -#[doc = "`reset()` method sets MR0 to value 0"] -impl crate::Resettable for Mr0Spec {} diff --git a/mcxa276-pac/src/cmc/pmctrlmain.rs b/mcxa276-pac/src/cmc/pmctrlmain.rs deleted file mode 100644 index 6d5bd0c57..000000000 --- a/mcxa276-pac/src/cmc/pmctrlmain.rs +++ /dev/null @@ -1,117 +0,0 @@ -#[doc = "Register `PMCTRLMAIN` reader"] -pub type R = crate::R; -#[doc = "Register `PMCTRLMAIN` writer"] -pub type W = crate::W; -#[doc = "Low-Power Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Lpmode { - #[doc = "0: Active/Sleep"] - Lpmode0000 = 0, - #[doc = "1: Deep Sleep"] - Lpmode0001 = 1, - #[doc = "3: Power Down"] - Lpmode0011 = 3, - #[doc = "15: Deep-Power Down"] - Lpmode1111 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Lpmode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Lpmode { - type Ux = u8; -} -impl crate::IsEnum for Lpmode {} -#[doc = "Field `LPMODE` reader - Low-Power Mode"] -pub type LpmodeR = crate::FieldReader; -impl LpmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Lpmode::Lpmode0000), - 1 => Some(Lpmode::Lpmode0001), - 3 => Some(Lpmode::Lpmode0011), - 15 => Some(Lpmode::Lpmode1111), - _ => None, - } - } - #[doc = "Active/Sleep"] - #[inline(always)] - pub fn is_lpmode0000(&self) -> bool { - *self == Lpmode::Lpmode0000 - } - #[doc = "Deep Sleep"] - #[inline(always)] - pub fn is_lpmode0001(&self) -> bool { - *self == Lpmode::Lpmode0001 - } - #[doc = "Power Down"] - #[inline(always)] - pub fn is_lpmode0011(&self) -> bool { - *self == Lpmode::Lpmode0011 - } - #[doc = "Deep-Power Down"] - #[inline(always)] - pub fn is_lpmode1111(&self) -> bool { - *self == Lpmode::Lpmode1111 - } -} -#[doc = "Field `LPMODE` writer - Low-Power Mode"] -pub type LpmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Lpmode>; -impl<'a, REG> LpmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Active/Sleep"] - #[inline(always)] - pub fn lpmode0000(self) -> &'a mut crate::W { - self.variant(Lpmode::Lpmode0000) - } - #[doc = "Deep Sleep"] - #[inline(always)] - pub fn lpmode0001(self) -> &'a mut crate::W { - self.variant(Lpmode::Lpmode0001) - } - #[doc = "Power Down"] - #[inline(always)] - pub fn lpmode0011(self) -> &'a mut crate::W { - self.variant(Lpmode::Lpmode0011) - } - #[doc = "Deep-Power Down"] - #[inline(always)] - pub fn lpmode1111(self) -> &'a mut crate::W { - self.variant(Lpmode::Lpmode1111) - } -} -impl R { - #[doc = "Bits 0:3 - Low-Power Mode"] - #[inline(always)] - pub fn lpmode(&self) -> LpmodeR { - LpmodeR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Low-Power Mode"] - #[inline(always)] - pub fn lpmode(&mut self) -> LpmodeW { - LpmodeW::new(self, 0) - } -} -#[doc = "Power Mode Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pmctrlmain::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmctrlmain::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PmctrlmainSpec; -impl crate::RegisterSpec for PmctrlmainSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pmctrlmain::R`](R) reader structure"] -impl crate::Readable for PmctrlmainSpec {} -#[doc = "`write(|w| ..)` method takes [`pmctrlmain::W`](W) writer structure"] -impl crate::Writable for PmctrlmainSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PMCTRLMAIN to value 0"] -impl crate::Resettable for PmctrlmainSpec {} diff --git a/mcxa276-pac/src/cmc/pmprot.rs b/mcxa276-pac/src/cmc/pmprot.rs deleted file mode 100644 index 8ceca76df..000000000 --- a/mcxa276-pac/src/cmc/pmprot.rs +++ /dev/null @@ -1,336 +0,0 @@ -#[doc = "Register `PMPROT` reader"] -pub type R = crate::R; -#[doc = "Register `PMPROT` writer"] -pub type W = crate::W; -#[doc = "Low-Power Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Lpmode { - #[doc = "0: Not allowed"] - Disabled = 0, - #[doc = "1: Allowed"] - En = 1, - #[doc = "2: Allowed"] - En1 = 2, - #[doc = "3: Allowed"] - En2 = 3, - #[doc = "4: Allowed"] - En3 = 4, - #[doc = "5: Allowed"] - En4 = 5, - #[doc = "6: Allowed"] - En5 = 6, - #[doc = "7: Allowed"] - En6 = 7, - #[doc = "8: Allowed"] - En7 = 8, - #[doc = "9: Allowed"] - En8 = 9, - #[doc = "10: Allowed"] - En9 = 10, - #[doc = "11: Allowed"] - En10 = 11, - #[doc = "12: Allowed"] - En11 = 12, - #[doc = "13: Allowed"] - En12 = 13, - #[doc = "14: Allowed"] - En13 = 14, - #[doc = "15: Allowed"] - En14 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Lpmode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Lpmode { - type Ux = u8; -} -impl crate::IsEnum for Lpmode {} -#[doc = "Field `LPMODE` reader - Low-Power Mode"] -pub type LpmodeR = crate::FieldReader; -impl LpmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpmode { - match self.bits { - 0 => Lpmode::Disabled, - 1 => Lpmode::En, - 2 => Lpmode::En1, - 3 => Lpmode::En2, - 4 => Lpmode::En3, - 5 => Lpmode::En4, - 6 => Lpmode::En5, - 7 => Lpmode::En6, - 8 => Lpmode::En7, - 9 => Lpmode::En8, - 10 => Lpmode::En9, - 11 => Lpmode::En10, - 12 => Lpmode::En11, - 13 => Lpmode::En12, - 14 => Lpmode::En13, - 15 => Lpmode::En14, - _ => unreachable!(), - } - } - #[doc = "Not allowed"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpmode::Disabled - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en(&self) -> bool { - *self == Lpmode::En - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en1(&self) -> bool { - *self == Lpmode::En1 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en2(&self) -> bool { - *self == Lpmode::En2 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en3(&self) -> bool { - *self == Lpmode::En3 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en4(&self) -> bool { - *self == Lpmode::En4 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en5(&self) -> bool { - *self == Lpmode::En5 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en6(&self) -> bool { - *self == Lpmode::En6 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en7(&self) -> bool { - *self == Lpmode::En7 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en8(&self) -> bool { - *self == Lpmode::En8 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en9(&self) -> bool { - *self == Lpmode::En9 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en10(&self) -> bool { - *self == Lpmode::En10 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en11(&self) -> bool { - *self == Lpmode::En11 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en12(&self) -> bool { - *self == Lpmode::En12 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en13(&self) -> bool { - *self == Lpmode::En13 - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_en14(&self) -> bool { - *self == Lpmode::En14 - } -} -#[doc = "Field `LPMODE` writer - Low-Power Mode"] -pub type LpmodeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Lpmode, crate::Safe>; -impl<'a, REG> LpmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Not allowed"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpmode::Disabled) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en(self) -> &'a mut crate::W { - self.variant(Lpmode::En) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en1(self) -> &'a mut crate::W { - self.variant(Lpmode::En1) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en2(self) -> &'a mut crate::W { - self.variant(Lpmode::En2) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en3(self) -> &'a mut crate::W { - self.variant(Lpmode::En3) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en4(self) -> &'a mut crate::W { - self.variant(Lpmode::En4) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en5(self) -> &'a mut crate::W { - self.variant(Lpmode::En5) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en6(self) -> &'a mut crate::W { - self.variant(Lpmode::En6) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en7(self) -> &'a mut crate::W { - self.variant(Lpmode::En7) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en8(self) -> &'a mut crate::W { - self.variant(Lpmode::En8) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en9(self) -> &'a mut crate::W { - self.variant(Lpmode::En9) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en10(self) -> &'a mut crate::W { - self.variant(Lpmode::En10) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en11(self) -> &'a mut crate::W { - self.variant(Lpmode::En11) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en12(self) -> &'a mut crate::W { - self.variant(Lpmode::En12) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en13(self) -> &'a mut crate::W { - self.variant(Lpmode::En13) - } - #[doc = "Allowed"] - #[inline(always)] - pub fn en14(self) -> &'a mut crate::W { - self.variant(Lpmode::En14) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: Allowed"] - Disabled = 0, - #[doc = "1: Blocked"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - Lock Register"] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Disabled, - true => Lock::Enabled, - } - } - #[doc = "Allowed"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lock::Disabled - } - #[doc = "Blocked"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lock::Enabled - } -} -#[doc = "Field `LOCK` writer - Lock Register"] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Allowed"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lock::Disabled) - } - #[doc = "Blocked"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lock::Enabled) - } -} -impl R { - #[doc = "Bits 0:3 - Low-Power Mode"] - #[inline(always)] - pub fn lpmode(&self) -> LpmodeR { - LpmodeR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 31 - Lock Register"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Low-Power Mode"] - #[inline(always)] - pub fn lpmode(&mut self) -> LpmodeW { - LpmodeW::new(self, 0) - } - #[doc = "Bit 31 - Lock Register"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 31) - } -} -#[doc = "Power Mode Protection\n\nYou can [`read`](crate::Reg::read) this register and get [`pmprot::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmprot::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PmprotSpec; -impl crate::RegisterSpec for PmprotSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pmprot::R`](R) reader structure"] -impl crate::Readable for PmprotSpec {} -#[doc = "`write(|w| ..)` method takes [`pmprot::W`](W) writer structure"] -impl crate::Writable for PmprotSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PMPROT to value 0"] -impl crate::Resettable for PmprotSpec {} diff --git a/mcxa276-pac/src/cmc/rpc.rs b/mcxa276-pac/src/cmc/rpc.rs deleted file mode 100644 index e7aa3ff80..000000000 --- a/mcxa276-pac/src/cmc/rpc.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `RPC` reader"] -pub type R = crate::R; -#[doc = "Register `RPC` writer"] -pub type W = crate::W; -#[doc = "Field `FILTCFG` reader - Reset Filter Configuration"] -pub type FiltcfgR = crate::FieldReader; -#[doc = "Field `FILTCFG` writer - Reset Filter Configuration"] -pub type FiltcfgW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Filten { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Filten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILTEN` reader - Filter Enable"] -pub type FiltenR = crate::BitReader; -impl FiltenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filten { - match self.bits { - false => Filten::Disabled, - true => Filten::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Filten::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Filten::Enabled - } -} -#[doc = "Field `FILTEN` writer - Filter Enable"] -pub type FiltenW<'a, REG> = crate::BitWriter<'a, REG, Filten>; -impl<'a, REG> FiltenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Filten::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Filten::Enabled) - } -} -#[doc = "Low-Power Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpfen { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpfen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPFEN` reader - Low-Power Filter Enable"] -pub type LpfenR = crate::BitReader; -impl LpfenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpfen { - match self.bits { - false => Lpfen::Disabled, - true => Lpfen::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpfen::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpfen::Enabled - } -} -#[doc = "Field `LPFEN` writer - Low-Power Filter Enable"] -pub type LpfenW<'a, REG> = crate::BitWriter<'a, REG, Lpfen>; -impl<'a, REG> LpfenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpfen::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpfen::Enabled) - } -} -impl R { - #[doc = "Bits 0:4 - Reset Filter Configuration"] - #[inline(always)] - pub fn filtcfg(&self) -> FiltcfgR { - FiltcfgR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bit 8 - Filter Enable"] - #[inline(always)] - pub fn filten(&self) -> FiltenR { - FiltenR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Low-Power Filter Enable"] - #[inline(always)] - pub fn lpfen(&self) -> LpfenR { - LpfenR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Reset Filter Configuration"] - #[inline(always)] - pub fn filtcfg(&mut self) -> FiltcfgW { - FiltcfgW::new(self, 0) - } - #[doc = "Bit 8 - Filter Enable"] - #[inline(always)] - pub fn filten(&mut self) -> FiltenW { - FiltenW::new(self, 8) - } - #[doc = "Bit 9 - Low-Power Filter Enable"] - #[inline(always)] - pub fn lpfen(&mut self) -> LpfenW { - LpfenW::new(self, 9) - } -} -#[doc = "Reset Pin Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rpc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RpcSpec; -impl crate::RegisterSpec for RpcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rpc::R`](R) reader structure"] -impl crate::Readable for RpcSpec {} -#[doc = "`write(|w| ..)` method takes [`rpc::W`](W) writer structure"] -impl crate::Writable for RpcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RPC to value 0"] -impl crate::Resettable for RpcSpec {} diff --git a/mcxa276-pac/src/cmc/srie.rs b/mcxa276-pac/src/cmc/srie.rs deleted file mode 100644 index 50de5f4de..000000000 --- a/mcxa276-pac/src/cmc/srie.rs +++ /dev/null @@ -1,590 +0,0 @@ -#[doc = "Register `SRIE` reader"] -pub type R = crate::R; -#[doc = "Register `SRIE` writer"] -pub type W = crate::W; -#[doc = "Pin Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN` reader - Pin Reset"] -pub type PinR = crate::BitReader; -impl PinR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin { - match self.bits { - false => Pin::Disabled, - true => Pin::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pin::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pin::Enabled - } -} -#[doc = "Field `PIN` writer - Pin Reset"] -pub type PinW<'a, REG> = crate::BitWriter<'a, REG, Pin>; -impl<'a, REG> PinW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pin::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pin::Enabled) - } -} -#[doc = "DAP Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dap { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dap) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAP` reader - DAP Reset"] -pub type DapR = crate::BitReader; -impl DapR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dap { - match self.bits { - false => Dap::Disabled, - true => Dap::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dap::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dap::Enabled - } -} -#[doc = "Field `DAP` writer - DAP Reset"] -pub type DapW<'a, REG> = crate::BitWriter<'a, REG, Dap>; -impl<'a, REG> DapW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dap::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dap::Enabled) - } -} -#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpack { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] -pub type LpackR = crate::BitReader; -impl LpackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpack { - match self.bits { - false => Lpack::Disabled, - true => Lpack::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpack::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpack::Enabled - } -} -#[doc = "Field `LPACK` writer - Low Power Acknowledge Timeout Reset"] -pub type LpackW<'a, REG> = crate::BitWriter<'a, REG, Lpack>; -impl<'a, REG> LpackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpack::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpack::Enabled) - } -} -#[doc = "System Clock Generation Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Scg { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Scg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SCG` reader - System Clock Generation Reset"] -pub type ScgR = crate::BitReader; -impl ScgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Scg { - match self.bits { - false => Scg::Disabled, - true => Scg::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Scg::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Scg::Enabled - } -} -#[doc = "Field `SCG` writer - System Clock Generation Reset"] -pub type ScgW<'a, REG> = crate::BitWriter<'a, REG, Scg>; -impl<'a, REG> ScgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Scg::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Scg::Enabled) - } -} -#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wwdt0 { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wwdt0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] -pub type Wwdt0R = crate::BitReader; -impl Wwdt0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wwdt0 { - match self.bits { - false => Wwdt0::Disabled, - true => Wwdt0::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wwdt0::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wwdt0::Enabled - } -} -#[doc = "Field `WWDT0` writer - Windowed Watchdog 0 Reset"] -pub type Wwdt0W<'a, REG> = crate::BitWriter<'a, REG, Wwdt0>; -impl<'a, REG> Wwdt0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Enabled) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sw { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SW` reader - Software Reset"] -pub type SwR = crate::BitReader; -impl SwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sw { - match self.bits { - false => Sw::Disabled, - true => Sw::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sw::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sw::Enabled - } -} -#[doc = "Field `SW` writer - Software Reset"] -pub type SwW<'a, REG> = crate::BitWriter<'a, REG, Sw>; -impl<'a, REG> SwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sw::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sw::Enabled) - } -} -#[doc = "Lockup Reset\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lockup { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lockup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCKUP` reader - Lockup Reset"] -pub type LockupR = crate::BitReader; -impl LockupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lockup { - match self.bits { - false => Lockup::Disabled, - true => Lockup::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lockup::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lockup::Enabled - } -} -#[doc = "Field `LOCKUP` writer - Lockup Reset"] -pub type LockupW<'a, REG> = crate::BitWriter<'a, REG, Lockup>; -impl<'a, REG> LockupW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lockup::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lockup::Enabled) - } -} -#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog0 { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] -pub type Cdog0R = crate::BitReader; -impl Cdog0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog0 { - match self.bits { - false => Cdog0::Disabled, - true => Cdog0::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog0::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog0::Enabled - } -} -#[doc = "Field `CDOG0` writer - Code Watchdog 0 Reset"] -pub type Cdog0W<'a, REG> = crate::BitWriter<'a, REG, Cdog0>; -impl<'a, REG> Cdog0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cdog0::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cdog0::Enabled) - } -} -#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog1 { - #[doc = "0: Interrupt disabled"] - Disabled = 0, - #[doc = "1: Interrupt enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] -pub type Cdog1R = crate::BitReader; -impl Cdog1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog1 { - match self.bits { - false => Cdog1::Disabled, - true => Cdog1::Enabled, - } - } - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog1::Disabled - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog1::Enabled - } -} -#[doc = "Field `CDOG1` writer - Code Watchdog 1 Reset"] -pub type Cdog1W<'a, REG> = crate::BitWriter<'a, REG, Cdog1>; -impl<'a, REG> Cdog1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cdog1::Disabled) - } - #[doc = "Interrupt enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cdog1::Enabled) - } -} -impl R { - #[doc = "Bit 8 - Pin Reset"] - #[inline(always)] - pub fn pin(&self) -> PinR { - PinR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - DAP Reset"] - #[inline(always)] - pub fn dap(&self) -> DapR { - DapR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] - #[inline(always)] - pub fn lpack(&self) -> LpackR { - LpackR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - System Clock Generation Reset"] - #[inline(always)] - pub fn scg(&self) -> ScgR { - ScgR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] - #[inline(always)] - pub fn wwdt0(&self) -> Wwdt0R { - Wwdt0R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Software Reset"] - #[inline(always)] - pub fn sw(&self) -> SwR { - SwR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Lockup Reset"] - #[inline(always)] - pub fn lockup(&self) -> LockupR { - LockupR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 26 - Code Watchdog 0 Reset"] - #[inline(always)] - pub fn cdog0(&self) -> Cdog0R { - Cdog0R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Code Watchdog 1 Reset"] - #[inline(always)] - pub fn cdog1(&self) -> Cdog1R { - Cdog1R::new(((self.bits >> 27) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - Pin Reset"] - #[inline(always)] - pub fn pin(&mut self) -> PinW { - PinW::new(self, 8) - } - #[doc = "Bit 9 - DAP Reset"] - #[inline(always)] - pub fn dap(&mut self) -> DapW { - DapW::new(self, 9) - } - #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] - #[inline(always)] - pub fn lpack(&mut self) -> LpackW { - LpackW::new(self, 11) - } - #[doc = "Bit 12 - System Clock Generation Reset"] - #[inline(always)] - pub fn scg(&mut self) -> ScgW { - ScgW::new(self, 12) - } - #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] - #[inline(always)] - pub fn wwdt0(&mut self) -> Wwdt0W { - Wwdt0W::new(self, 13) - } - #[doc = "Bit 14 - Software Reset"] - #[inline(always)] - pub fn sw(&mut self) -> SwW { - SwW::new(self, 14) - } - #[doc = "Bit 15 - Lockup Reset"] - #[inline(always)] - pub fn lockup(&mut self) -> LockupW { - LockupW::new(self, 15) - } - #[doc = "Bit 26 - Code Watchdog 0 Reset"] - #[inline(always)] - pub fn cdog0(&mut self) -> Cdog0W { - Cdog0W::new(self, 26) - } - #[doc = "Bit 27 - Code Watchdog 1 Reset"] - #[inline(always)] - pub fn cdog1(&mut self) -> Cdog1W { - Cdog1W::new(self, 27) - } -} -#[doc = "System Reset Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`srie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrieSpec; -impl crate::RegisterSpec for SrieSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`srie::R`](R) reader structure"] -impl crate::Readable for SrieSpec {} -#[doc = "`write(|w| ..)` method takes [`srie::W`](W) writer structure"] -impl crate::Writable for SrieSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SRIE to value 0x8800"] -impl crate::Resettable for SrieSpec { - const RESET_VALUE: u32 = 0x8800; -} diff --git a/mcxa276-pac/src/cmc/srif.rs b/mcxa276-pac/src/cmc/srif.rs deleted file mode 100644 index f77b6780e..000000000 --- a/mcxa276-pac/src/cmc/srif.rs +++ /dev/null @@ -1,526 +0,0 @@ -#[doc = "Register `SRIF` reader"] -pub type R = crate::R; -#[doc = "Register `SRIF` writer"] -pub type W = crate::W; -#[doc = "Pin Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN` reader - Pin Reset"] -pub type PinR = crate::BitReader; -impl PinR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin { - match self.bits { - false => Pin::Disabled, - true => Pin::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pin::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pin::Enabled - } -} -#[doc = "Field `PIN` writer - Pin Reset"] -pub type PinW<'a, REG> = crate::BitWriter1C<'a, REG, Pin>; -impl<'a, REG> PinW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pin::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pin::Enabled) - } -} -#[doc = "DAP Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dap { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dap) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAP` reader - DAP Reset"] -pub type DapR = crate::BitReader; -impl DapR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dap { - match self.bits { - false => Dap::Disabled, - true => Dap::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dap::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dap::Enabled - } -} -#[doc = "Field `DAP` writer - DAP Reset"] -pub type DapW<'a, REG> = crate::BitWriter1C<'a, REG, Dap>; -impl<'a, REG> DapW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dap::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dap::Enabled) - } -} -#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpack { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] -pub type LpackR = crate::BitReader; -impl LpackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpack { - match self.bits { - false => Lpack::Disabled, - true => Lpack::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpack::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpack::Enabled - } -} -#[doc = "Field `LPACK` writer - Low Power Acknowledge Timeout Reset"] -pub type LpackW<'a, REG> = crate::BitWriter1C<'a, REG, Lpack>; -impl<'a, REG> LpackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpack::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpack::Enabled) - } -} -#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wwdt0 { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wwdt0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] -pub type Wwdt0R = crate::BitReader; -impl Wwdt0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wwdt0 { - match self.bits { - false => Wwdt0::Disabled, - true => Wwdt0::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wwdt0::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wwdt0::Enabled - } -} -#[doc = "Field `WWDT0` writer - Windowed Watchdog 0 Reset"] -pub type Wwdt0W<'a, REG> = crate::BitWriter1C<'a, REG, Wwdt0>; -impl<'a, REG> Wwdt0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Enabled) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sw { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SW` reader - Software Reset"] -pub type SwR = crate::BitReader; -impl SwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sw { - match self.bits { - false => Sw::Disabled, - true => Sw::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sw::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sw::Enabled - } -} -#[doc = "Field `SW` writer - Software Reset"] -pub type SwW<'a, REG> = crate::BitWriter1C<'a, REG, Sw>; -impl<'a, REG> SwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sw::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sw::Enabled) - } -} -#[doc = "Lockup Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lockup { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lockup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCKUP` reader - Lockup Reset"] -pub type LockupR = crate::BitReader; -impl LockupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lockup { - match self.bits { - false => Lockup::Disabled, - true => Lockup::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lockup::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lockup::Enabled - } -} -#[doc = "Field `LOCKUP` writer - Lockup Reset"] -pub type LockupW<'a, REG> = crate::BitWriter1C<'a, REG, Lockup>; -impl<'a, REG> LockupW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lockup::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lockup::Enabled) - } -} -#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog0 { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] -pub type Cdog0R = crate::BitReader; -impl Cdog0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog0 { - match self.bits { - false => Cdog0::Disabled, - true => Cdog0::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog0::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog0::Enabled - } -} -#[doc = "Field `CDOG0` writer - Code Watchdog 0 Reset"] -pub type Cdog0W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog0>; -impl<'a, REG> Cdog0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cdog0::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cdog0::Enabled) - } -} -#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog1 { - #[doc = "0: Reset source not pending"] - Disabled = 0, - #[doc = "1: Reset source pending"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] -pub type Cdog1R = crate::BitReader; -impl Cdog1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog1 { - match self.bits { - false => Cdog1::Disabled, - true => Cdog1::Enabled, - } - } - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog1::Disabled - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog1::Enabled - } -} -#[doc = "Field `CDOG1` writer - Code Watchdog 1 Reset"] -pub type Cdog1W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog1>; -impl<'a, REG> Cdog1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset source not pending"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cdog1::Disabled) - } - #[doc = "Reset source pending"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cdog1::Enabled) - } -} -impl R { - #[doc = "Bit 8 - Pin Reset"] - #[inline(always)] - pub fn pin(&self) -> PinR { - PinR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - DAP Reset"] - #[inline(always)] - pub fn dap(&self) -> DapR { - DapR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] - #[inline(always)] - pub fn lpack(&self) -> LpackR { - LpackR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] - #[inline(always)] - pub fn wwdt0(&self) -> Wwdt0R { - Wwdt0R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Software Reset"] - #[inline(always)] - pub fn sw(&self) -> SwR { - SwR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Lockup Reset"] - #[inline(always)] - pub fn lockup(&self) -> LockupR { - LockupR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 26 - Code Watchdog 0 Reset"] - #[inline(always)] - pub fn cdog0(&self) -> Cdog0R { - Cdog0R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Code Watchdog 1 Reset"] - #[inline(always)] - pub fn cdog1(&self) -> Cdog1R { - Cdog1R::new(((self.bits >> 27) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - Pin Reset"] - #[inline(always)] - pub fn pin(&mut self) -> PinW { - PinW::new(self, 8) - } - #[doc = "Bit 9 - DAP Reset"] - #[inline(always)] - pub fn dap(&mut self) -> DapW { - DapW::new(self, 9) - } - #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] - #[inline(always)] - pub fn lpack(&mut self) -> LpackW { - LpackW::new(self, 11) - } - #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] - #[inline(always)] - pub fn wwdt0(&mut self) -> Wwdt0W { - Wwdt0W::new(self, 13) - } - #[doc = "Bit 14 - Software Reset"] - #[inline(always)] - pub fn sw(&mut self) -> SwW { - SwW::new(self, 14) - } - #[doc = "Bit 15 - Lockup Reset"] - #[inline(always)] - pub fn lockup(&mut self) -> LockupW { - LockupW::new(self, 15) - } - #[doc = "Bit 26 - Code Watchdog 0 Reset"] - #[inline(always)] - pub fn cdog0(&mut self) -> Cdog0W { - Cdog0W::new(self, 26) - } - #[doc = "Bit 27 - Code Watchdog 1 Reset"] - #[inline(always)] - pub fn cdog1(&mut self) -> Cdog1W { - Cdog1W::new(self, 27) - } -} -#[doc = "System Reset Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`srif::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srif::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrifSpec; -impl crate::RegisterSpec for SrifSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`srif::R`](R) reader structure"] -impl crate::Readable for SrifSpec {} -#[doc = "`write(|w| ..)` method takes [`srif::W`](W) writer structure"] -impl crate::Writable for SrifSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c00_eb00; -} -#[doc = "`reset()` method sets SRIF to value 0"] -impl crate::Resettable for SrifSpec {} diff --git a/mcxa276-pac/src/cmc/srs.rs b/mcxa276-pac/src/cmc/srs.rs deleted file mode 100644 index d0e91fb63..000000000 --- a/mcxa276-pac/src/cmc/srs.rs +++ /dev/null @@ -1,710 +0,0 @@ -#[doc = "Register `SRS` reader"] -pub type R = crate::R; -#[doc = "Wake-up Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wakeup { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wakeup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAKEUP` reader - Wake-up Reset"] -pub type WakeupR = crate::BitReader; -impl WakeupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wakeup { - match self.bits { - false => Wakeup::Disabled, - true => Wakeup::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wakeup::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wakeup::Enabled - } -} -#[doc = "Power-on Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Por { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Por) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POR` reader - Power-on Reset"] -pub type PorR = crate::BitReader; -impl PorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Por { - match self.bits { - false => Por::Disabled, - true => Por::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Por::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Por::Enabled - } -} -#[doc = "Voltage Detect Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Vd { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Vd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VD` reader - Voltage Detect Reset"] -pub type VdR = crate::BitReader; -impl VdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Vd { - match self.bits { - false => Vd::Disabled, - true => Vd::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Vd::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Vd::Enabled - } -} -#[doc = "Warm Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Warm { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Warm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WARM` reader - Warm Reset"] -pub type WarmR = crate::BitReader; -impl WarmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Warm { - match self.bits { - false => Warm::Disabled, - true => Warm::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Warm::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Warm::Enabled - } -} -#[doc = "Fatal Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fatal { - #[doc = "0: Reset was not generated"] - Disabled = 0, - #[doc = "1: Reset was generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fatal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FATAL` reader - Fatal Reset"] -pub type FatalR = crate::BitReader; -impl FatalR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fatal { - match self.bits { - false => Fatal::Disabled, - true => Fatal::Enabled, - } - } - #[doc = "Reset was not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fatal::Disabled - } - #[doc = "Reset was generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fatal::Enabled - } -} -#[doc = "Pin Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin { - #[doc = "0: Reset was not generated"] - Disabled = 0, - #[doc = "1: Reset was generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN` reader - Pin Reset"] -pub type PinR = crate::BitReader; -impl PinR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin { - match self.bits { - false => Pin::Disabled, - true => Pin::Enabled, - } - } - #[doc = "Reset was not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pin::Disabled - } - #[doc = "Reset was generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pin::Enabled - } -} -#[doc = "Debug Access Port Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dap { - #[doc = "0: Reset was not generated"] - Disabled = 0, - #[doc = "1: Reset was generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dap) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAP` reader - Debug Access Port Reset"] -pub type DapR = crate::BitReader; -impl DapR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dap { - match self.bits { - false => Dap::Disabled, - true => Dap::Enabled, - } - } - #[doc = "Reset was not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dap::Disabled - } - #[doc = "Reset was generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dap::Enabled - } -} -#[doc = "Reset Timeout\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rstack { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rstack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSTACK` reader - Reset Timeout"] -pub type RstackR = crate::BitReader; -impl RstackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rstack { - match self.bits { - false => Rstack::Disabled, - true => Rstack::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rstack::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rstack::Enabled - } -} -#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpack { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] -pub type LpackR = crate::BitReader; -impl LpackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpack { - match self.bits { - false => Lpack::Disabled, - true => Lpack::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpack::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpack::Enabled - } -} -#[doc = "System Clock Generation Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Scg { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Scg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SCG` reader - System Clock Generation Reset"] -pub type ScgR = crate::BitReader; -impl ScgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Scg { - match self.bits { - false => Scg::Disabled, - true => Scg::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Scg::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Scg::Enabled - } -} -#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wwdt0 { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wwdt0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] -pub type Wwdt0R = crate::BitReader; -impl Wwdt0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wwdt0 { - match self.bits { - false => Wwdt0::Disabled, - true => Wwdt0::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wwdt0::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wwdt0::Enabled - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sw { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SW` reader - Software Reset"] -pub type SwR = crate::BitReader; -impl SwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sw { - match self.bits { - false => Sw::Disabled, - true => Sw::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sw::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sw::Enabled - } -} -#[doc = "Lockup Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lockup { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lockup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCKUP` reader - Lockup Reset"] -pub type LockupR = crate::BitReader; -impl LockupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lockup { - match self.bits { - false => Lockup::Disabled, - true => Lockup::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lockup::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lockup::Enabled - } -} -#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog0 { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] -pub type Cdog0R = crate::BitReader; -impl Cdog0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog0 { - match self.bits { - false => Cdog0::Disabled, - true => Cdog0::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog0::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog0::Enabled - } -} -#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog1 { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] -pub type Cdog1R = crate::BitReader; -impl Cdog1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog1 { - match self.bits { - false => Cdog1::Disabled, - true => Cdog1::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog1::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog1::Enabled - } -} -#[doc = "JTAG System Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Jtag { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Jtag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `JTAG` reader - JTAG System Reset"] -pub type JtagR = crate::BitReader; -impl JtagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Jtag { - match self.bits { - false => Jtag::Disabled, - true => Jtag::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Jtag::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Jtag::Enabled - } -} -#[doc = "Tamper Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tamper { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tamper) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TAMPER` reader - Tamper Reset"] -pub type TamperR = crate::BitReader; -impl TamperR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tamper { - match self.bits { - false => Tamper::Disabled, - true => Tamper::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tamper::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tamper::Enabled - } -} -impl R { - #[doc = "Bit 0 - Wake-up Reset"] - #[inline(always)] - pub fn wakeup(&self) -> WakeupR { - WakeupR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Power-on Reset"] - #[inline(always)] - pub fn por(&self) -> PorR { - PorR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Voltage Detect Reset"] - #[inline(always)] - pub fn vd(&self) -> VdR { - VdR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - Warm Reset"] - #[inline(always)] - pub fn warm(&self) -> WarmR { - WarmR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Fatal Reset"] - #[inline(always)] - pub fn fatal(&self) -> FatalR { - FatalR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 8 - Pin Reset"] - #[inline(always)] - pub fn pin(&self) -> PinR { - PinR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Debug Access Port Reset"] - #[inline(always)] - pub fn dap(&self) -> DapR { - DapR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Reset Timeout"] - #[inline(always)] - pub fn rstack(&self) -> RstackR { - RstackR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] - #[inline(always)] - pub fn lpack(&self) -> LpackR { - LpackR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - System Clock Generation Reset"] - #[inline(always)] - pub fn scg(&self) -> ScgR { - ScgR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] - #[inline(always)] - pub fn wwdt0(&self) -> Wwdt0R { - Wwdt0R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Software Reset"] - #[inline(always)] - pub fn sw(&self) -> SwR { - SwR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Lockup Reset"] - #[inline(always)] - pub fn lockup(&self) -> LockupR { - LockupR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 26 - Code Watchdog 0 Reset"] - #[inline(always)] - pub fn cdog0(&self) -> Cdog0R { - Cdog0R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Code Watchdog 1 Reset"] - #[inline(always)] - pub fn cdog1(&self) -> Cdog1R { - Cdog1R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - JTAG System Reset"] - #[inline(always)] - pub fn jtag(&self) -> JtagR { - JtagR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 31 - Tamper Reset"] - #[inline(always)] - pub fn tamper(&self) -> TamperR { - TamperR::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`srs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrsSpec; -impl crate::RegisterSpec for SrsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`srs::R`](R) reader structure"] -impl crate::Readable for SrsSpec {} -#[doc = "`reset()` method sets SRS to value 0"] -impl crate::Resettable for SrsSpec {} diff --git a/mcxa276-pac/src/cmc/ssrs.rs b/mcxa276-pac/src/cmc/ssrs.rs deleted file mode 100644 index 4b69c139f..000000000 --- a/mcxa276-pac/src/cmc/ssrs.rs +++ /dev/null @@ -1,1073 +0,0 @@ -#[doc = "Register `SSRS` reader"] -pub type R = crate::R; -#[doc = "Register `SSRS` writer"] -pub type W = crate::W; -#[doc = "Wake-up Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wakeup { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wakeup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAKEUP` reader - Wake-up Reset"] -pub type WakeupR = crate::BitReader; -impl WakeupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wakeup { - match self.bits { - false => Wakeup::Disabled, - true => Wakeup::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wakeup::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wakeup::Enabled - } -} -#[doc = "Field `WAKEUP` writer - Wake-up Reset"] -pub type WakeupW<'a, REG> = crate::BitWriter1C<'a, REG, Wakeup>; -impl<'a, REG> WakeupW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Wakeup::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Wakeup::Enabled) - } -} -#[doc = "Power-on Reset\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Por { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Por) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POR` reader - Power-on Reset"] -pub type PorR = crate::BitReader; -impl PorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Por { - match self.bits { - false => Por::Disabled, - true => Por::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Por::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Por::Enabled - } -} -#[doc = "Field `POR` writer - Power-on Reset"] -pub type PorW<'a, REG> = crate::BitWriter1C<'a, REG, Por>; -impl<'a, REG> PorW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Por::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Por::Enabled) - } -} -#[doc = "Voltage Detect Reset\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Vd { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Vd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VD` reader - Voltage Detect Reset"] -pub type VdR = crate::BitReader; -impl VdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Vd { - match self.bits { - false => Vd::Disabled, - true => Vd::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Vd::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Vd::Enabled - } -} -#[doc = "Warm Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Warm { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Warm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WARM` reader - Warm Reset"] -pub type WarmR = crate::BitReader; -impl WarmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Warm { - match self.bits { - false => Warm::Disabled, - true => Warm::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Warm::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Warm::Enabled - } -} -#[doc = "Field `WARM` writer - Warm Reset"] -pub type WarmW<'a, REG> = crate::BitWriter1C<'a, REG, Warm>; -impl<'a, REG> WarmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Warm::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Warm::Enabled) - } -} -#[doc = "Fatal Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fatal { - #[doc = "0: Reset was not generated"] - Disabled = 0, - #[doc = "1: Reset was generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fatal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FATAL` reader - Fatal Reset"] -pub type FatalR = crate::BitReader; -impl FatalR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fatal { - match self.bits { - false => Fatal::Disabled, - true => Fatal::Enabled, - } - } - #[doc = "Reset was not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fatal::Disabled - } - #[doc = "Reset was generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fatal::Enabled - } -} -#[doc = "Field `FATAL` writer - Fatal Reset"] -pub type FatalW<'a, REG> = crate::BitWriter1C<'a, REG, Fatal>; -impl<'a, REG> FatalW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset was not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fatal::Disabled) - } - #[doc = "Reset was generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fatal::Enabled) - } -} -#[doc = "Pin Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN` reader - Pin Reset"] -pub type PinR = crate::BitReader; -impl PinR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin { - match self.bits { - false => Pin::Disabled, - true => Pin::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pin::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pin::Enabled - } -} -#[doc = "Field `PIN` writer - Pin Reset"] -pub type PinW<'a, REG> = crate::BitWriter1C<'a, REG, Pin>; -impl<'a, REG> PinW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pin::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pin::Enabled) - } -} -#[doc = "DAP Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dap { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dap) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAP` reader - DAP Reset"] -pub type DapR = crate::BitReader; -impl DapR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dap { - match self.bits { - false => Dap::Disabled, - true => Dap::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dap::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dap::Enabled - } -} -#[doc = "Field `DAP` writer - DAP Reset"] -pub type DapW<'a, REG> = crate::BitWriter1C<'a, REG, Dap>; -impl<'a, REG> DapW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dap::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dap::Enabled) - } -} -#[doc = "Reset Timeout\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rstack { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rstack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSTACK` reader - Reset Timeout"] -pub type RstackR = crate::BitReader; -impl RstackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rstack { - match self.bits { - false => Rstack::Disabled, - true => Rstack::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rstack::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rstack::Enabled - } -} -#[doc = "Field `RSTACK` writer - Reset Timeout"] -pub type RstackW<'a, REG> = crate::BitWriter1C<'a, REG, Rstack>; -impl<'a, REG> RstackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rstack::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rstack::Enabled) - } -} -#[doc = "Low Power Acknowledge Timeout Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpack { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPACK` reader - Low Power Acknowledge Timeout Reset"] -pub type LpackR = crate::BitReader; -impl LpackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpack { - match self.bits { - false => Lpack::Disabled, - true => Lpack::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpack::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpack::Enabled - } -} -#[doc = "Field `LPACK` writer - Low Power Acknowledge Timeout Reset"] -pub type LpackW<'a, REG> = crate::BitWriter1C<'a, REG, Lpack>; -impl<'a, REG> LpackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpack::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpack::Enabled) - } -} -#[doc = "System Clock Generation Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Scg { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Scg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SCG` reader - System Clock Generation Reset"] -pub type ScgR = crate::BitReader; -impl ScgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Scg { - match self.bits { - false => Scg::Disabled, - true => Scg::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Scg::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Scg::Enabled - } -} -#[doc = "Field `SCG` writer - System Clock Generation Reset"] -pub type ScgW<'a, REG> = crate::BitWriter1C<'a, REG, Scg>; -impl<'a, REG> ScgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Scg::Disabled) - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Scg::Enabled) - } -} -#[doc = "Windowed Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wwdt0 { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wwdt0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WWDT0` reader - Windowed Watchdog 0 Reset"] -pub type Wwdt0R = crate::BitReader; -impl Wwdt0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wwdt0 { - match self.bits { - false => Wwdt0::Disabled, - true => Wwdt0::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wwdt0::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wwdt0::Enabled - } -} -#[doc = "Field `WWDT0` writer - Windowed Watchdog 0 Reset"] -pub type Wwdt0W<'a, REG> = crate::BitWriter1C<'a, REG, Wwdt0>; -impl<'a, REG> Wwdt0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Disabled) - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Enabled) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sw { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SW` reader - Software Reset"] -pub type SwR = crate::BitReader; -impl SwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sw { - match self.bits { - false => Sw::Disabled, - true => Sw::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sw::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sw::Enabled - } -} -#[doc = "Field `SW` writer - Software Reset"] -pub type SwW<'a, REG> = crate::BitWriter1C<'a, REG, Sw>; -impl<'a, REG> SwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sw::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sw::Enabled) - } -} -#[doc = "Lockup Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lockup { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lockup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCKUP` reader - Lockup Reset"] -pub type LockupR = crate::BitReader; -impl LockupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lockup { - match self.bits { - false => Lockup::Disabled, - true => Lockup::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lockup::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lockup::Enabled - } -} -#[doc = "Field `LOCKUP` writer - Lockup Reset"] -pub type LockupW<'a, REG> = crate::BitWriter1C<'a, REG, Lockup>; -impl<'a, REG> LockupW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lockup::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lockup::Enabled) - } -} -#[doc = "Code Watchdog 0 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog0 { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG0` reader - Code Watchdog 0 Reset"] -pub type Cdog0R = crate::BitReader; -impl Cdog0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog0 { - match self.bits { - false => Cdog0::Disabled, - true => Cdog0::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog0::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog0::Enabled - } -} -#[doc = "Field `CDOG0` writer - Code Watchdog 0 Reset"] -pub type Cdog0W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog0>; -impl<'a, REG> Cdog0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cdog0::Disabled) - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cdog0::Enabled) - } -} -#[doc = "Code Watchdog 1 Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cdog1 { - #[doc = "0: Reset is not generated"] - Disabled = 0, - #[doc = "1: Reset is generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cdog1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CDOG1` reader - Code Watchdog 1 Reset"] -pub type Cdog1R = crate::BitReader; -impl Cdog1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cdog1 { - match self.bits { - false => Cdog1::Disabled, - true => Cdog1::Enabled, - } - } - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cdog1::Disabled - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cdog1::Enabled - } -} -#[doc = "Field `CDOG1` writer - Code Watchdog 1 Reset"] -pub type Cdog1W<'a, REG> = crate::BitWriter1C<'a, REG, Cdog1>; -impl<'a, REG> Cdog1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset is not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cdog1::Disabled) - } - #[doc = "Reset is generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cdog1::Enabled) - } -} -#[doc = "JTAG System Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Jtag { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Jtag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `JTAG` reader - JTAG System Reset"] -pub type JtagR = crate::BitReader; -impl JtagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Jtag { - match self.bits { - false => Jtag::Disabled, - true => Jtag::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Jtag::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Jtag::Enabled - } -} -#[doc = "Field `JTAG` writer - JTAG System Reset"] -pub type JtagW<'a, REG> = crate::BitWriter1C<'a, REG, Jtag>; -impl<'a, REG> JtagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Jtag::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Jtag::Enabled) - } -} -#[doc = "Tamper Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tamper { - #[doc = "0: Reset not generated"] - Disabled = 0, - #[doc = "1: Reset generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tamper) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TAMPER` reader - Tamper Reset"] -pub type TamperR = crate::BitReader; -impl TamperR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tamper { - match self.bits { - false => Tamper::Disabled, - true => Tamper::Enabled, - } - } - #[doc = "Reset not generated"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tamper::Disabled - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tamper::Enabled - } -} -#[doc = "Field `TAMPER` writer - Tamper Reset"] -pub type TamperW<'a, REG> = crate::BitWriter1C<'a, REG, Tamper>; -impl<'a, REG> TamperW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset not generated"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tamper::Disabled) - } - #[doc = "Reset generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tamper::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Wake-up Reset"] - #[inline(always)] - pub fn wakeup(&self) -> WakeupR { - WakeupR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Power-on Reset"] - #[inline(always)] - pub fn por(&self) -> PorR { - PorR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Voltage Detect Reset"] - #[inline(always)] - pub fn vd(&self) -> VdR { - VdR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - Warm Reset"] - #[inline(always)] - pub fn warm(&self) -> WarmR { - WarmR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Fatal Reset"] - #[inline(always)] - pub fn fatal(&self) -> FatalR { - FatalR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 8 - Pin Reset"] - #[inline(always)] - pub fn pin(&self) -> PinR { - PinR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - DAP Reset"] - #[inline(always)] - pub fn dap(&self) -> DapR { - DapR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Reset Timeout"] - #[inline(always)] - pub fn rstack(&self) -> RstackR { - RstackR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] - #[inline(always)] - pub fn lpack(&self) -> LpackR { - LpackR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - System Clock Generation Reset"] - #[inline(always)] - pub fn scg(&self) -> ScgR { - ScgR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] - #[inline(always)] - pub fn wwdt0(&self) -> Wwdt0R { - Wwdt0R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Software Reset"] - #[inline(always)] - pub fn sw(&self) -> SwR { - SwR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Lockup Reset"] - #[inline(always)] - pub fn lockup(&self) -> LockupR { - LockupR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 26 - Code Watchdog 0 Reset"] - #[inline(always)] - pub fn cdog0(&self) -> Cdog0R { - Cdog0R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Code Watchdog 1 Reset"] - #[inline(always)] - pub fn cdog1(&self) -> Cdog1R { - Cdog1R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - JTAG System Reset"] - #[inline(always)] - pub fn jtag(&self) -> JtagR { - JtagR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 31 - Tamper Reset"] - #[inline(always)] - pub fn tamper(&self) -> TamperR { - TamperR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Wake-up Reset"] - #[inline(always)] - pub fn wakeup(&mut self) -> WakeupW { - WakeupW::new(self, 0) - } - #[doc = "Bit 1 - Power-on Reset"] - #[inline(always)] - pub fn por(&mut self) -> PorW { - PorW::new(self, 1) - } - #[doc = "Bit 4 - Warm Reset"] - #[inline(always)] - pub fn warm(&mut self) -> WarmW { - WarmW::new(self, 4) - } - #[doc = "Bit 5 - Fatal Reset"] - #[inline(always)] - pub fn fatal(&mut self) -> FatalW { - FatalW::new(self, 5) - } - #[doc = "Bit 8 - Pin Reset"] - #[inline(always)] - pub fn pin(&mut self) -> PinW { - PinW::new(self, 8) - } - #[doc = "Bit 9 - DAP Reset"] - #[inline(always)] - pub fn dap(&mut self) -> DapW { - DapW::new(self, 9) - } - #[doc = "Bit 10 - Reset Timeout"] - #[inline(always)] - pub fn rstack(&mut self) -> RstackW { - RstackW::new(self, 10) - } - #[doc = "Bit 11 - Low Power Acknowledge Timeout Reset"] - #[inline(always)] - pub fn lpack(&mut self) -> LpackW { - LpackW::new(self, 11) - } - #[doc = "Bit 12 - System Clock Generation Reset"] - #[inline(always)] - pub fn scg(&mut self) -> ScgW { - ScgW::new(self, 12) - } - #[doc = "Bit 13 - Windowed Watchdog 0 Reset"] - #[inline(always)] - pub fn wwdt0(&mut self) -> Wwdt0W { - Wwdt0W::new(self, 13) - } - #[doc = "Bit 14 - Software Reset"] - #[inline(always)] - pub fn sw(&mut self) -> SwW { - SwW::new(self, 14) - } - #[doc = "Bit 15 - Lockup Reset"] - #[inline(always)] - pub fn lockup(&mut self) -> LockupW { - LockupW::new(self, 15) - } - #[doc = "Bit 26 - Code Watchdog 0 Reset"] - #[inline(always)] - pub fn cdog0(&mut self) -> Cdog0W { - Cdog0W::new(self, 26) - } - #[doc = "Bit 27 - Code Watchdog 1 Reset"] - #[inline(always)] - pub fn cdog1(&mut self) -> Cdog1W { - Cdog1W::new(self, 27) - } - #[doc = "Bit 28 - JTAG System Reset"] - #[inline(always)] - pub fn jtag(&mut self) -> JtagW { - JtagW::new(self, 28) - } - #[doc = "Bit 31 - Tamper Reset"] - #[inline(always)] - pub fn tamper(&mut self) -> TamperW { - TamperW::new(self, 31) - } -} -#[doc = "Sticky System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssrs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssrs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SsrsSpec; -impl crate::RegisterSpec for SsrsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ssrs::R`](R) reader structure"] -impl crate::Readable for SsrsSpec {} -#[doc = "`write(|w| ..)` method takes [`ssrs::W`](W) writer structure"] -impl crate::Writable for SsrsSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x9c00_ff33; -} -#[doc = "`reset()` method sets SSRS to value 0x06"] -impl crate::Resettable for SsrsSpec { - const RESET_VALUE: u32 = 0x06; -} diff --git a/mcxa276-pac/src/cmc/verid.rs b/mcxa276-pac/src/cmc/verid.rs deleted file mode 100644 index 00564cf8e..000000000 --- a/mcxa276-pac/src/cmc/verid.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0300_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0300_0000; -} diff --git a/mcxa276-pac/src/cmp0.rs b/mcxa276-pac/src/cmp0.rs deleted file mode 100644 index 837ef6a8b..000000000 --- a/mcxa276-pac/src/cmp0.rs +++ /dev/null @@ -1,151 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - ccr0: Ccr0, - ccr1: Ccr1, - ccr2: Ccr2, - _reserved5: [u8; 0x04], - dcr: Dcr, - ier: Ier, - csr: Csr, - rrcr0: Rrcr0, - rrcr1: Rrcr1, - rrcsr: Rrcsr, - rrsr: Rrsr, - _reserved12: [u8; 0x04], - rrcr2: Rrcr2, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x08 - Comparator Control Register 0"] - #[inline(always)] - pub const fn ccr0(&self) -> &Ccr0 { - &self.ccr0 - } - #[doc = "0x0c - Comparator Control Register 1"] - #[inline(always)] - pub const fn ccr1(&self) -> &Ccr1 { - &self.ccr1 - } - #[doc = "0x10 - Comparator Control Register 2"] - #[inline(always)] - pub const fn ccr2(&self) -> &Ccr2 { - &self.ccr2 - } - #[doc = "0x18 - DAC Control"] - #[inline(always)] - pub const fn dcr(&self) -> &Dcr { - &self.dcr - } - #[doc = "0x1c - Interrupt Enable"] - #[inline(always)] - pub const fn ier(&self) -> &Ier { - &self.ier - } - #[doc = "0x20 - Comparator Status"] - #[inline(always)] - pub const fn csr(&self) -> &Csr { - &self.csr - } - #[doc = "0x24 - Round Robin Control Register 0"] - #[inline(always)] - pub const fn rrcr0(&self) -> &Rrcr0 { - &self.rrcr0 - } - #[doc = "0x28 - Round Robin Control Register 1"] - #[inline(always)] - pub const fn rrcr1(&self) -> &Rrcr1 { - &self.rrcr1 - } - #[doc = "0x2c - Round Robin Control and Status"] - #[inline(always)] - pub const fn rrcsr(&self) -> &Rrcsr { - &self.rrcsr - } - #[doc = "0x30 - Round Robin Status"] - #[inline(always)] - pub const fn rrsr(&self) -> &Rrsr { - &self.rrsr - } - #[doc = "0x38 - Round Robin Control Register 2"] - #[inline(always)] - pub const fn rrcr2(&self) -> &Rrcr2 { - &self.rrcr2 - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "CCR0 (rw) register accessor: Comparator Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr0`] module"] -#[doc(alias = "CCR0")] -pub type Ccr0 = crate::Reg; -#[doc = "Comparator Control Register 0"] -pub mod ccr0; -#[doc = "CCR1 (rw) register accessor: Comparator Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`] module"] -#[doc(alias = "CCR1")] -pub type Ccr1 = crate::Reg; -#[doc = "Comparator Control Register 1"] -pub mod ccr1; -#[doc = "CCR2 (rw) register accessor: Comparator Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`] module"] -#[doc(alias = "CCR2")] -pub type Ccr2 = crate::Reg; -#[doc = "Comparator Control Register 2"] -pub mod ccr2; -#[doc = "DCR (rw) register accessor: DAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcr`] module"] -#[doc(alias = "DCR")] -pub type Dcr = crate::Reg; -#[doc = "DAC Control"] -pub mod dcr; -#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] -#[doc(alias = "IER")] -pub type Ier = crate::Reg; -#[doc = "Interrupt Enable"] -pub mod ier; -#[doc = "CSR (rw) register accessor: Comparator Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`] module"] -#[doc(alias = "CSR")] -pub type Csr = crate::Reg; -#[doc = "Comparator Status"] -pub mod csr; -#[doc = "RRCR0 (rw) register accessor: Round Robin Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcr0`] module"] -#[doc(alias = "RRCR0")] -pub type Rrcr0 = crate::Reg; -#[doc = "Round Robin Control Register 0"] -pub mod rrcr0; -#[doc = "RRCR1 (rw) register accessor: Round Robin Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcr1`] module"] -#[doc(alias = "RRCR1")] -pub type Rrcr1 = crate::Reg; -#[doc = "Round Robin Control Register 1"] -pub mod rrcr1; -#[doc = "RRCSR (rw) register accessor: Round Robin Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcsr`] module"] -#[doc(alias = "RRCSR")] -pub type Rrcsr = crate::Reg; -#[doc = "Round Robin Control and Status"] -pub mod rrcsr; -#[doc = "RRSR (rw) register accessor: Round Robin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrsr`] module"] -#[doc(alias = "RRSR")] -pub type Rrsr = crate::Reg; -#[doc = "Round Robin Status"] -pub mod rrsr; -#[doc = "RRCR2 (rw) register accessor: Round Robin Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rrcr2`] module"] -#[doc(alias = "RRCR2")] -pub type Rrcr2 = crate::Reg; -#[doc = "Round Robin Control Register 2"] -pub mod rrcr2; diff --git a/mcxa276-pac/src/cmp0/ccr0.rs b/mcxa276-pac/src/cmp0/ccr0.rs deleted file mode 100644 index fdc16d63d..000000000 --- a/mcxa276-pac/src/cmp0/ccr0.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `CCR0` reader"] -pub type R = crate::R; -#[doc = "Register `CCR0` writer"] -pub type W = crate::W; -#[doc = "Comparator Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CmpEn { - #[doc = "0: Disable (The analog logic remains off and consumes no power.)"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CmpEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP_EN` reader - Comparator Enable"] -pub type CmpEnR = crate::BitReader; -impl CmpEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CmpEn { - match self.bits { - false => CmpEn::Disable, - true => CmpEn::Enable, - } - } - #[doc = "Disable (The analog logic remains off and consumes no power.)"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == CmpEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == CmpEn::Enable - } -} -#[doc = "Field `CMP_EN` writer - Comparator Enable"] -pub type CmpEnW<'a, REG> = crate::BitWriter<'a, REG, CmpEn>; -impl<'a, REG> CmpEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable (The analog logic remains off and consumes no power.)"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(CmpEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(CmpEn::Enable) - } -} -#[doc = "Comparator Deep Sleep Mode Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CmpStopEn { - #[doc = "0: Disables the analog comparator regardless of CMP_EN."] - Disable = 0, - #[doc = "1: Allows CMP_EN to enable the analog comparator."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CmpStopEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP_STOP_EN` reader - Comparator Deep Sleep Mode Enable"] -pub type CmpStopEnR = crate::BitReader; -impl CmpStopEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CmpStopEn { - match self.bits { - false => CmpStopEn::Disable, - true => CmpStopEn::Enable, - } - } - #[doc = "Disables the analog comparator regardless of CMP_EN."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == CmpStopEn::Disable - } - #[doc = "Allows CMP_EN to enable the analog comparator."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == CmpStopEn::Enable - } -} -#[doc = "Field `CMP_STOP_EN` writer - Comparator Deep Sleep Mode Enable"] -pub type CmpStopEnW<'a, REG> = crate::BitWriter<'a, REG, CmpStopEn>; -impl<'a, REG> CmpStopEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables the analog comparator regardless of CMP_EN."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(CmpStopEn::Disable) - } - #[doc = "Allows CMP_EN to enable the analog comparator."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(CmpStopEn::Enable) - } -} -impl R { - #[doc = "Bit 0 - Comparator Enable"] - #[inline(always)] - pub fn cmp_en(&self) -> CmpEnR { - CmpEnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Comparator Deep Sleep Mode Enable"] - #[inline(always)] - pub fn cmp_stop_en(&self) -> CmpStopEnR { - CmpStopEnR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Comparator Enable"] - #[inline(always)] - pub fn cmp_en(&mut self) -> CmpEnW { - CmpEnW::new(self, 0) - } - #[doc = "Bit 1 - Comparator Deep Sleep Mode Enable"] - #[inline(always)] - pub fn cmp_stop_en(&mut self) -> CmpStopEnW { - CmpStopEnW::new(self, 1) - } -} -#[doc = "Comparator Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ccr0Spec; -impl crate::RegisterSpec for Ccr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ccr0::R`](R) reader structure"] -impl crate::Readable for Ccr0Spec {} -#[doc = "`write(|w| ..)` method takes [`ccr0::W`](W) writer structure"] -impl crate::Writable for Ccr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CCR0 to value 0x02"] -impl crate::Resettable for Ccr0Spec { - const RESET_VALUE: u32 = 0x02; -} diff --git a/mcxa276-pac/src/cmp0/ccr1.rs b/mcxa276-pac/src/cmp0/ccr1.rs deleted file mode 100644 index d8fb4bcfb..000000000 --- a/mcxa276-pac/src/cmp0/ccr1.rs +++ /dev/null @@ -1,992 +0,0 @@ -#[doc = "Register `CCR1` reader"] -pub type R = crate::R; -#[doc = "Register `CCR1` writer"] -pub type W = crate::W; -#[doc = "Windowing Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WindowEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WindowEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WINDOW_EN` reader - Windowing Enable"] -pub type WindowEnR = crate::BitReader; -impl WindowEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WindowEn { - match self.bits { - false => WindowEn::Disable, - true => WindowEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == WindowEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == WindowEn::Enable - } -} -#[doc = "Field `WINDOW_EN` writer - Windowing Enable"] -pub type WindowEnW<'a, REG> = crate::BitWriter<'a, REG, WindowEn>; -impl<'a, REG> WindowEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(WindowEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(WindowEn::Enable) - } -} -#[doc = "Sampling Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SampleEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SampleEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SAMPLE_EN` reader - Sampling Enable"] -pub type SampleEnR = crate::BitReader; -impl SampleEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SampleEn { - match self.bits { - false => SampleEn::Disable, - true => SampleEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SampleEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SampleEn::Enable - } -} -#[doc = "Field `SAMPLE_EN` writer - Sampling Enable"] -pub type SampleEnW<'a, REG> = crate::BitWriter<'a, REG, SampleEn>; -impl<'a, REG> SampleEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SampleEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SampleEn::Enable) - } -} -#[doc = "DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DmaEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DmaEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMA_EN` reader - DMA Enable"] -pub type DmaEnR = crate::BitReader; -impl DmaEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DmaEn { - match self.bits { - false => DmaEn::Disable, - true => DmaEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DmaEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DmaEn::Enable - } -} -#[doc = "Field `DMA_EN` writer - DMA Enable"] -pub type DmaEnW<'a, REG> = crate::BitWriter<'a, REG, DmaEn>; -impl<'a, REG> DmaEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DmaEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DmaEn::Enable) - } -} -#[doc = "Comparator Invert\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoutInv { - #[doc = "0: Do not invert"] - NoInvert = 0, - #[doc = "1: Invert"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoutInv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COUT_INV` reader - Comparator Invert"] -pub type CoutInvR = crate::BitReader; -impl CoutInvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoutInv { - match self.bits { - false => CoutInv::NoInvert, - true => CoutInv::Invert, - } - } - #[doc = "Do not invert"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == CoutInv::NoInvert - } - #[doc = "Invert"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == CoutInv::Invert - } -} -#[doc = "Field `COUT_INV` writer - Comparator Invert"] -pub type CoutInvW<'a, REG> = crate::BitWriter<'a, REG, CoutInv>; -impl<'a, REG> CoutInvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Do not invert"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(CoutInv::NoInvert) - } - #[doc = "Invert"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(CoutInv::Invert) - } -} -#[doc = "Comparator Output Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoutSel { - #[doc = "0: Use COUT (filtered)"] - Cout = 0, - #[doc = "1: Use COUTA (unfiltered)"] - Couta = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoutSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COUT_SEL` reader - Comparator Output Select"] -pub type CoutSelR = crate::BitReader; -impl CoutSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoutSel { - match self.bits { - false => CoutSel::Cout, - true => CoutSel::Couta, - } - } - #[doc = "Use COUT (filtered)"] - #[inline(always)] - pub fn is_cout(&self) -> bool { - *self == CoutSel::Cout - } - #[doc = "Use COUTA (unfiltered)"] - #[inline(always)] - pub fn is_couta(&self) -> bool { - *self == CoutSel::Couta - } -} -#[doc = "Field `COUT_SEL` writer - Comparator Output Select"] -pub type CoutSelW<'a, REG> = crate::BitWriter<'a, REG, CoutSel>; -impl<'a, REG> CoutSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Use COUT (filtered)"] - #[inline(always)] - pub fn cout(self) -> &'a mut crate::W { - self.variant(CoutSel::Cout) - } - #[doc = "Use COUTA (unfiltered)"] - #[inline(always)] - pub fn couta(self) -> &'a mut crate::W { - self.variant(CoutSel::Couta) - } -} -#[doc = "Comparator Output Pin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoutPen { - #[doc = "0: Not available"] - Unavailable = 0, - #[doc = "1: Available"] - Available = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoutPen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COUT_PEN` reader - Comparator Output Pin Enable"] -pub type CoutPenR = crate::BitReader; -impl CoutPenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoutPen { - match self.bits { - false => CoutPen::Unavailable, - true => CoutPen::Available, - } - } - #[doc = "Not available"] - #[inline(always)] - pub fn is_unavailable(&self) -> bool { - *self == CoutPen::Unavailable - } - #[doc = "Available"] - #[inline(always)] - pub fn is_available(&self) -> bool { - *self == CoutPen::Available - } -} -#[doc = "Field `COUT_PEN` writer - Comparator Output Pin Enable"] -pub type CoutPenW<'a, REG> = crate::BitWriter<'a, REG, CoutPen>; -impl<'a, REG> CoutPenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not available"] - #[inline(always)] - pub fn unavailable(self) -> &'a mut crate::W { - self.variant(CoutPen::Unavailable) - } - #[doc = "Available"] - #[inline(always)] - pub fn available(self) -> &'a mut crate::W { - self.variant(CoutPen::Available) - } -} -#[doc = "COUTA_OW Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoutaOwen { - #[doc = "0: COUTA holds the last sampled value."] - Sampled = 0, - #[doc = "1: Enables the COUTA signal value to be defined by COUTA_OW."] - CoutaOw = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoutaOwen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COUTA_OWEN` reader - COUTA_OW Enable"] -pub type CoutaOwenR = crate::BitReader; -impl CoutaOwenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoutaOwen { - match self.bits { - false => CoutaOwen::Sampled, - true => CoutaOwen::CoutaOw, - } - } - #[doc = "COUTA holds the last sampled value."] - #[inline(always)] - pub fn is_sampled(&self) -> bool { - *self == CoutaOwen::Sampled - } - #[doc = "Enables the COUTA signal value to be defined by COUTA_OW."] - #[inline(always)] - pub fn is_couta_ow(&self) -> bool { - *self == CoutaOwen::CoutaOw - } -} -#[doc = "Field `COUTA_OWEN` writer - COUTA_OW Enable"] -pub type CoutaOwenW<'a, REG> = crate::BitWriter<'a, REG, CoutaOwen>; -impl<'a, REG> CoutaOwenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "COUTA holds the last sampled value."] - #[inline(always)] - pub fn sampled(self) -> &'a mut crate::W { - self.variant(CoutaOwen::Sampled) - } - #[doc = "Enables the COUTA signal value to be defined by COUTA_OW."] - #[inline(always)] - pub fn couta_ow(self) -> &'a mut crate::W { - self.variant(CoutaOwen::CoutaOw) - } -} -#[doc = "COUTA Output Level for Closed Window\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoutaOw { - #[doc = "0: COUTA is 0"] - Couta0 = 0, - #[doc = "1: COUTA is 1"] - Couta1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoutaOw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COUTA_OW` reader - COUTA Output Level for Closed Window"] -pub type CoutaOwR = crate::BitReader; -impl CoutaOwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoutaOw { - match self.bits { - false => CoutaOw::Couta0, - true => CoutaOw::Couta1, - } - } - #[doc = "COUTA is 0"] - #[inline(always)] - pub fn is_couta_0(&self) -> bool { - *self == CoutaOw::Couta0 - } - #[doc = "COUTA is 1"] - #[inline(always)] - pub fn is_couta_1(&self) -> bool { - *self == CoutaOw::Couta1 - } -} -#[doc = "Field `COUTA_OW` writer - COUTA Output Level for Closed Window"] -pub type CoutaOwW<'a, REG> = crate::BitWriter<'a, REG, CoutaOw>; -impl<'a, REG> CoutaOwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "COUTA is 0"] - #[inline(always)] - pub fn couta_0(self) -> &'a mut crate::W { - self.variant(CoutaOw::Couta0) - } - #[doc = "COUTA is 1"] - #[inline(always)] - pub fn couta_1(self) -> &'a mut crate::W { - self.variant(CoutaOw::Couta1) - } -} -#[doc = "WINDOW/SAMPLE Signal Invert\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WindowInv { - #[doc = "0: Do not invert"] - NoInvert = 0, - #[doc = "1: Invert"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WindowInv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WINDOW_INV` reader - WINDOW/SAMPLE Signal Invert"] -pub type WindowInvR = crate::BitReader; -impl WindowInvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WindowInv { - match self.bits { - false => WindowInv::NoInvert, - true => WindowInv::Invert, - } - } - #[doc = "Do not invert"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == WindowInv::NoInvert - } - #[doc = "Invert"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == WindowInv::Invert - } -} -#[doc = "Field `WINDOW_INV` writer - WINDOW/SAMPLE Signal Invert"] -pub type WindowInvW<'a, REG> = crate::BitWriter<'a, REG, WindowInv>; -impl<'a, REG> WindowInvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Do not invert"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(WindowInv::NoInvert) - } - #[doc = "Invert"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(WindowInv::Invert) - } -} -#[doc = "COUT Event Window Close\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WindowCls { - #[doc = "0: COUT event cannot close the window"] - NoClose = 0, - #[doc = "1: COUT event can close the window"] - Close = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WindowCls) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WINDOW_CLS` reader - COUT Event Window Close"] -pub type WindowClsR = crate::BitReader; -impl WindowClsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WindowCls { - match self.bits { - false => WindowCls::NoClose, - true => WindowCls::Close, - } - } - #[doc = "COUT event cannot close the window"] - #[inline(always)] - pub fn is_no_close(&self) -> bool { - *self == WindowCls::NoClose - } - #[doc = "COUT event can close the window"] - #[inline(always)] - pub fn is_close(&self) -> bool { - *self == WindowCls::Close - } -} -#[doc = "Field `WINDOW_CLS` writer - COUT Event Window Close"] -pub type WindowClsW<'a, REG> = crate::BitWriter<'a, REG, WindowCls>; -impl<'a, REG> WindowClsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "COUT event cannot close the window"] - #[inline(always)] - pub fn no_close(self) -> &'a mut crate::W { - self.variant(WindowCls::NoClose) - } - #[doc = "COUT event can close the window"] - #[inline(always)] - pub fn close(self) -> &'a mut crate::W { - self.variant(WindowCls::Close) - } -} -#[doc = "COUT Event Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum EvtSel { - #[doc = "0: Rising edge"] - Rising = 0, - #[doc = "1: Falling edge"] - Falling = 1, - #[doc = "2: Both edges"] - Both = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: EvtSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for EvtSel { - type Ux = u8; -} -impl crate::IsEnum for EvtSel {} -#[doc = "Field `EVT_SEL` reader - COUT Event Select"] -pub type EvtSelR = crate::FieldReader; -impl EvtSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(EvtSel::Rising), - 1 => Some(EvtSel::Falling), - 2 => Some(EvtSel::Both), - _ => None, - } - } - #[doc = "Rising edge"] - #[inline(always)] - pub fn is_rising(&self) -> bool { - *self == EvtSel::Rising - } - #[doc = "Falling edge"] - #[inline(always)] - pub fn is_falling(&self) -> bool { - *self == EvtSel::Falling - } - #[doc = "Both edges"] - #[inline(always)] - pub fn is_both(&self) -> bool { - *self == EvtSel::Both - } -} -#[doc = "Field `EVT_SEL` writer - COUT Event Select"] -pub type EvtSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, EvtSel>; -impl<'a, REG> EvtSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Rising edge"] - #[inline(always)] - pub fn rising(self) -> &'a mut crate::W { - self.variant(EvtSel::Rising) - } - #[doc = "Falling edge"] - #[inline(always)] - pub fn falling(self) -> &'a mut crate::W { - self.variant(EvtSel::Falling) - } - #[doc = "Both edges"] - #[inline(always)] - pub fn both(self) -> &'a mut crate::W { - self.variant(EvtSel::Both) - } -} -#[doc = "Functional Clock Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum FuncClkSel { - #[doc = "0: Select functional clock source 0"] - Func0 = 0, - #[doc = "1: Select functional clock source 1"] - Func1 = 1, - #[doc = "2: Select functional clock source 2"] - Func2 = 2, - #[doc = "3: Select functional clock source 3"] - Func3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: FuncClkSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for FuncClkSel { - type Ux = u8; -} -impl crate::IsEnum for FuncClkSel {} -#[doc = "Field `FUNC_CLK_SEL` reader - Functional Clock Source Select"] -pub type FuncClkSelR = crate::FieldReader; -impl FuncClkSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FuncClkSel { - match self.bits { - 0 => FuncClkSel::Func0, - 1 => FuncClkSel::Func1, - 2 => FuncClkSel::Func2, - 3 => FuncClkSel::Func3, - _ => unreachable!(), - } - } - #[doc = "Select functional clock source 0"] - #[inline(always)] - pub fn is_func0(&self) -> bool { - *self == FuncClkSel::Func0 - } - #[doc = "Select functional clock source 1"] - #[inline(always)] - pub fn is_func1(&self) -> bool { - *self == FuncClkSel::Func1 - } - #[doc = "Select functional clock source 2"] - #[inline(always)] - pub fn is_func2(&self) -> bool { - *self == FuncClkSel::Func2 - } - #[doc = "Select functional clock source 3"] - #[inline(always)] - pub fn is_func3(&self) -> bool { - *self == FuncClkSel::Func3 - } -} -#[doc = "Field `FUNC_CLK_SEL` writer - Functional Clock Source Select"] -pub type FuncClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, FuncClkSel, crate::Safe>; -impl<'a, REG> FuncClkSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select functional clock source 0"] - #[inline(always)] - pub fn func0(self) -> &'a mut crate::W { - self.variant(FuncClkSel::Func0) - } - #[doc = "Select functional clock source 1"] - #[inline(always)] - pub fn func1(self) -> &'a mut crate::W { - self.variant(FuncClkSel::Func1) - } - #[doc = "Select functional clock source 2"] - #[inline(always)] - pub fn func2(self) -> &'a mut crate::W { - self.variant(FuncClkSel::Func2) - } - #[doc = "Select functional clock source 3"] - #[inline(always)] - pub fn func3(self) -> &'a mut crate::W { - self.variant(FuncClkSel::Func3) - } -} -#[doc = "Filter Sample Count\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum FiltCnt { - #[doc = "0: Filter is bypassed: COUT = COUTA"] - Bypassed = 0, - #[doc = "1: 1 consecutive sample (Comparator output is simply sampled.)"] - Sample1 = 1, - #[doc = "2: 2 consecutive samples"] - Sample2 = 2, - #[doc = "3: 3 consecutive samples"] - Sample3 = 3, - #[doc = "4: 4 consecutive samples"] - Sample4 = 4, - #[doc = "5: 5 consecutive samples"] - Sample5 = 5, - #[doc = "6: 6 consecutive samples"] - Sample6 = 6, - #[doc = "7: 7 consecutive samples"] - Sample7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: FiltCnt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for FiltCnt { - type Ux = u8; -} -impl crate::IsEnum for FiltCnt {} -#[doc = "Field `FILT_CNT` reader - Filter Sample Count"] -pub type FiltCntR = crate::FieldReader; -impl FiltCntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FiltCnt { - match self.bits { - 0 => FiltCnt::Bypassed, - 1 => FiltCnt::Sample1, - 2 => FiltCnt::Sample2, - 3 => FiltCnt::Sample3, - 4 => FiltCnt::Sample4, - 5 => FiltCnt::Sample5, - 6 => FiltCnt::Sample6, - 7 => FiltCnt::Sample7, - _ => unreachable!(), - } - } - #[doc = "Filter is bypassed: COUT = COUTA"] - #[inline(always)] - pub fn is_bypassed(&self) -> bool { - *self == FiltCnt::Bypassed - } - #[doc = "1 consecutive sample (Comparator output is simply sampled.)"] - #[inline(always)] - pub fn is_sample_1(&self) -> bool { - *self == FiltCnt::Sample1 - } - #[doc = "2 consecutive samples"] - #[inline(always)] - pub fn is_sample_2(&self) -> bool { - *self == FiltCnt::Sample2 - } - #[doc = "3 consecutive samples"] - #[inline(always)] - pub fn is_sample_3(&self) -> bool { - *self == FiltCnt::Sample3 - } - #[doc = "4 consecutive samples"] - #[inline(always)] - pub fn is_sample_4(&self) -> bool { - *self == FiltCnt::Sample4 - } - #[doc = "5 consecutive samples"] - #[inline(always)] - pub fn is_sample_5(&self) -> bool { - *self == FiltCnt::Sample5 - } - #[doc = "6 consecutive samples"] - #[inline(always)] - pub fn is_sample_6(&self) -> bool { - *self == FiltCnt::Sample6 - } - #[doc = "7 consecutive samples"] - #[inline(always)] - pub fn is_sample_7(&self) -> bool { - *self == FiltCnt::Sample7 - } -} -#[doc = "Field `FILT_CNT` writer - Filter Sample Count"] -pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3, FiltCnt, crate::Safe>; -impl<'a, REG> FiltCntW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Filter is bypassed: COUT = COUTA"] - #[inline(always)] - pub fn bypassed(self) -> &'a mut crate::W { - self.variant(FiltCnt::Bypassed) - } - #[doc = "1 consecutive sample (Comparator output is simply sampled.)"] - #[inline(always)] - pub fn sample_1(self) -> &'a mut crate::W { - self.variant(FiltCnt::Sample1) - } - #[doc = "2 consecutive samples"] - #[inline(always)] - pub fn sample_2(self) -> &'a mut crate::W { - self.variant(FiltCnt::Sample2) - } - #[doc = "3 consecutive samples"] - #[inline(always)] - pub fn sample_3(self) -> &'a mut crate::W { - self.variant(FiltCnt::Sample3) - } - #[doc = "4 consecutive samples"] - #[inline(always)] - pub fn sample_4(self) -> &'a mut crate::W { - self.variant(FiltCnt::Sample4) - } - #[doc = "5 consecutive samples"] - #[inline(always)] - pub fn sample_5(self) -> &'a mut crate::W { - self.variant(FiltCnt::Sample5) - } - #[doc = "6 consecutive samples"] - #[inline(always)] - pub fn sample_6(self) -> &'a mut crate::W { - self.variant(FiltCnt::Sample6) - } - #[doc = "7 consecutive samples"] - #[inline(always)] - pub fn sample_7(self) -> &'a mut crate::W { - self.variant(FiltCnt::Sample7) - } -} -#[doc = "Field `FILT_PER` reader - Filter Sample Period"] -pub type FiltPerR = crate::FieldReader; -#[doc = "Field `FILT_PER` writer - Filter Sample Period"] -pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bit 0 - Windowing Enable"] - #[inline(always)] - pub fn window_en(&self) -> WindowEnR { - WindowEnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Sampling Enable"] - #[inline(always)] - pub fn sample_en(&self) -> SampleEnR { - SampleEnR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - DMA Enable"] - #[inline(always)] - pub fn dma_en(&self) -> DmaEnR { - DmaEnR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Comparator Invert"] - #[inline(always)] - pub fn cout_inv(&self) -> CoutInvR { - CoutInvR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Comparator Output Select"] - #[inline(always)] - pub fn cout_sel(&self) -> CoutSelR { - CoutSelR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Comparator Output Pin Enable"] - #[inline(always)] - pub fn cout_pen(&self) -> CoutPenR { - CoutPenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - COUTA_OW Enable"] - #[inline(always)] - pub fn couta_owen(&self) -> CoutaOwenR { - CoutaOwenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - COUTA Output Level for Closed Window"] - #[inline(always)] - pub fn couta_ow(&self) -> CoutaOwR { - CoutaOwR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - WINDOW/SAMPLE Signal Invert"] - #[inline(always)] - pub fn window_inv(&self) -> WindowInvR { - WindowInvR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - COUT Event Window Close"] - #[inline(always)] - pub fn window_cls(&self) -> WindowClsR { - WindowClsR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 10:11 - COUT Event Select"] - #[inline(always)] - pub fn evt_sel(&self) -> EvtSelR { - EvtSelR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Functional Clock Source Select"] - #[inline(always)] - pub fn func_clk_sel(&self) -> FuncClkSelR { - FuncClkSelR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 16:18 - Filter Sample Count"] - #[inline(always)] - pub fn filt_cnt(&self) -> FiltCntR { - FiltCntR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:31 - Filter Sample Period"] - #[inline(always)] - pub fn filt_per(&self) -> FiltPerR { - FiltPerR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bit 0 - Windowing Enable"] - #[inline(always)] - pub fn window_en(&mut self) -> WindowEnW { - WindowEnW::new(self, 0) - } - #[doc = "Bit 1 - Sampling Enable"] - #[inline(always)] - pub fn sample_en(&mut self) -> SampleEnW { - SampleEnW::new(self, 1) - } - #[doc = "Bit 2 - DMA Enable"] - #[inline(always)] - pub fn dma_en(&mut self) -> DmaEnW { - DmaEnW::new(self, 2) - } - #[doc = "Bit 3 - Comparator Invert"] - #[inline(always)] - pub fn cout_inv(&mut self) -> CoutInvW { - CoutInvW::new(self, 3) - } - #[doc = "Bit 4 - Comparator Output Select"] - #[inline(always)] - pub fn cout_sel(&mut self) -> CoutSelW { - CoutSelW::new(self, 4) - } - #[doc = "Bit 5 - Comparator Output Pin Enable"] - #[inline(always)] - pub fn cout_pen(&mut self) -> CoutPenW { - CoutPenW::new(self, 5) - } - #[doc = "Bit 6 - COUTA_OW Enable"] - #[inline(always)] - pub fn couta_owen(&mut self) -> CoutaOwenW { - CoutaOwenW::new(self, 6) - } - #[doc = "Bit 7 - COUTA Output Level for Closed Window"] - #[inline(always)] - pub fn couta_ow(&mut self) -> CoutaOwW { - CoutaOwW::new(self, 7) - } - #[doc = "Bit 8 - WINDOW/SAMPLE Signal Invert"] - #[inline(always)] - pub fn window_inv(&mut self) -> WindowInvW { - WindowInvW::new(self, 8) - } - #[doc = "Bit 9 - COUT Event Window Close"] - #[inline(always)] - pub fn window_cls(&mut self) -> WindowClsW { - WindowClsW::new(self, 9) - } - #[doc = "Bits 10:11 - COUT Event Select"] - #[inline(always)] - pub fn evt_sel(&mut self) -> EvtSelW { - EvtSelW::new(self, 10) - } - #[doc = "Bits 12:13 - Functional Clock Source Select"] - #[inline(always)] - pub fn func_clk_sel(&mut self) -> FuncClkSelW { - FuncClkSelW::new(self, 12) - } - #[doc = "Bits 16:18 - Filter Sample Count"] - #[inline(always)] - pub fn filt_cnt(&mut self) -> FiltCntW { - FiltCntW::new(self, 16) - } - #[doc = "Bits 24:31 - Filter Sample Period"] - #[inline(always)] - pub fn filt_per(&mut self) -> FiltPerW { - FiltPerW::new(self, 24) - } -} -#[doc = "Comparator Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ccr1Spec; -impl crate::RegisterSpec for Ccr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"] -impl crate::Readable for Ccr1Spec {} -#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"] -impl crate::Writable for Ccr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CCR1 to value 0"] -impl crate::Resettable for Ccr1Spec {} diff --git a/mcxa276-pac/src/cmp0/ccr2.rs b/mcxa276-pac/src/cmp0/ccr2.rs deleted file mode 100644 index 9dc96d0d1..000000000 --- a/mcxa276-pac/src/cmp0/ccr2.rs +++ /dev/null @@ -1,513 +0,0 @@ -#[doc = "Register `CCR2` reader"] -pub type R = crate::R; -#[doc = "Register `CCR2` writer"] -pub type W = crate::W; -#[doc = "CMP High Power Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CmpHpmd { - #[doc = "0: Low power (speed) comparison mode"] - Low = 0, - #[doc = "1: High power (speed) comparison mode"] - High = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CmpHpmd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP_HPMD` reader - CMP High Power Mode Select"] -pub type CmpHpmdR = crate::BitReader; -impl CmpHpmdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CmpHpmd { - match self.bits { - false => CmpHpmd::Low, - true => CmpHpmd::High, - } - } - #[doc = "Low power (speed) comparison mode"] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == CmpHpmd::Low - } - #[doc = "High power (speed) comparison mode"] - #[inline(always)] - pub fn is_high(&self) -> bool { - *self == CmpHpmd::High - } -} -#[doc = "Field `CMP_HPMD` writer - CMP High Power Mode Select"] -pub type CmpHpmdW<'a, REG> = crate::BitWriter<'a, REG, CmpHpmd>; -impl<'a, REG> CmpHpmdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low power (speed) comparison mode"] - #[inline(always)] - pub fn low(self) -> &'a mut crate::W { - self.variant(CmpHpmd::Low) - } - #[doc = "High power (speed) comparison mode"] - #[inline(always)] - pub fn high(self) -> &'a mut crate::W { - self.variant(CmpHpmd::High) - } -} -#[doc = "CMP Nano Power Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CmpNpmd { - #[doc = "0: Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."] - NoNano = 0, - #[doc = "1: Enables CMP Nano power mode."] - Nano = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CmpNpmd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP_NPMD` reader - CMP Nano Power Mode Select"] -pub type CmpNpmdR = crate::BitReader; -impl CmpNpmdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CmpNpmd { - match self.bits { - false => CmpNpmd::NoNano, - true => CmpNpmd::Nano, - } - } - #[doc = "Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."] - #[inline(always)] - pub fn is_no_nano(&self) -> bool { - *self == CmpNpmd::NoNano - } - #[doc = "Enables CMP Nano power mode."] - #[inline(always)] - pub fn is_nano(&self) -> bool { - *self == CmpNpmd::Nano - } -} -#[doc = "Field `CMP_NPMD` writer - CMP Nano Power Mode Select"] -pub type CmpNpmdW<'a, REG> = crate::BitWriter<'a, REG, CmpNpmd>; -impl<'a, REG> CmpNpmdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."] - #[inline(always)] - pub fn no_nano(self) -> &'a mut crate::W { - self.variant(CmpNpmd::NoNano) - } - #[doc = "Enables CMP Nano power mode."] - #[inline(always)] - pub fn nano(self) -> &'a mut crate::W { - self.variant(CmpNpmd::Nano) - } -} -#[doc = "Comparator Hysteresis Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Hystctr { - #[doc = "0: Level 0: Analog comparator hysteresis 0 mV."] - Level0 = 0, - #[doc = "1: Level 1: Analog comparator hysteresis 10 mV."] - Level1 = 1, - #[doc = "2: Level 2: Analog comparator hysteresis 20 mV."] - Level2 = 2, - #[doc = "3: Level 3: Analog comparator hysteresis 30 mV."] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Hystctr) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Hystctr { - type Ux = u8; -} -impl crate::IsEnum for Hystctr {} -#[doc = "Field `HYSTCTR` reader - Comparator Hysteresis Control"] -pub type HystctrR = crate::FieldReader; -impl HystctrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hystctr { - match self.bits { - 0 => Hystctr::Level0, - 1 => Hystctr::Level1, - 2 => Hystctr::Level2, - 3 => Hystctr::Level3, - _ => unreachable!(), - } - } - #[doc = "Level 0: Analog comparator hysteresis 0 mV."] - #[inline(always)] - pub fn is_level_0(&self) -> bool { - *self == Hystctr::Level0 - } - #[doc = "Level 1: Analog comparator hysteresis 10 mV."] - #[inline(always)] - pub fn is_level_1(&self) -> bool { - *self == Hystctr::Level1 - } - #[doc = "Level 2: Analog comparator hysteresis 20 mV."] - #[inline(always)] - pub fn is_level_2(&self) -> bool { - *self == Hystctr::Level2 - } - #[doc = "Level 3: Analog comparator hysteresis 30 mV."] - #[inline(always)] - pub fn is_level_3(&self) -> bool { - *self == Hystctr::Level3 - } -} -#[doc = "Field `HYSTCTR` writer - Comparator Hysteresis Control"] -pub type HystctrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hystctr, crate::Safe>; -impl<'a, REG> HystctrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Level 0: Analog comparator hysteresis 0 mV."] - #[inline(always)] - pub fn level_0(self) -> &'a mut crate::W { - self.variant(Hystctr::Level0) - } - #[doc = "Level 1: Analog comparator hysteresis 10 mV."] - #[inline(always)] - pub fn level_1(self) -> &'a mut crate::W { - self.variant(Hystctr::Level1) - } - #[doc = "Level 2: Analog comparator hysteresis 20 mV."] - #[inline(always)] - pub fn level_2(self) -> &'a mut crate::W { - self.variant(Hystctr::Level2) - } - #[doc = "Level 3: Analog comparator hysteresis 30 mV."] - #[inline(always)] - pub fn level_3(self) -> &'a mut crate::W { - self.variant(Hystctr::Level3) - } -} -#[doc = "Plus Input MUX Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Psel { - #[doc = "0: Input 0p"] - Input0 = 0, - #[doc = "1: Input 1p"] - Input1 = 1, - #[doc = "2: Input 2p"] - Input2 = 2, - #[doc = "3: Input 3p"] - Input3 = 3, - #[doc = "4: Input 4p"] - Input4 = 4, - #[doc = "5: Input 5p"] - Input5 = 5, - #[doc = "7: Internal DAC output"] - Input7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Psel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Psel { - type Ux = u8; -} -impl crate::IsEnum for Psel {} -#[doc = "Field `PSEL` reader - Plus Input MUX Select"] -pub type PselR = crate::FieldReader; -impl PselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Psel::Input0), - 1 => Some(Psel::Input1), - 2 => Some(Psel::Input2), - 3 => Some(Psel::Input3), - 4 => Some(Psel::Input4), - 5 => Some(Psel::Input5), - 7 => Some(Psel::Input7), - _ => None, - } - } - #[doc = "Input 0p"] - #[inline(always)] - pub fn is_input_0(&self) -> bool { - *self == Psel::Input0 - } - #[doc = "Input 1p"] - #[inline(always)] - pub fn is_input_1(&self) -> bool { - *self == Psel::Input1 - } - #[doc = "Input 2p"] - #[inline(always)] - pub fn is_input_2(&self) -> bool { - *self == Psel::Input2 - } - #[doc = "Input 3p"] - #[inline(always)] - pub fn is_input_3(&self) -> bool { - *self == Psel::Input3 - } - #[doc = "Input 4p"] - #[inline(always)] - pub fn is_input_4(&self) -> bool { - *self == Psel::Input4 - } - #[doc = "Input 5p"] - #[inline(always)] - pub fn is_input_5(&self) -> bool { - *self == Psel::Input5 - } - #[doc = "Internal DAC output"] - #[inline(always)] - pub fn is_input_7(&self) -> bool { - *self == Psel::Input7 - } -} -#[doc = "Field `PSEL` writer - Plus Input MUX Select"] -pub type PselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Psel>; -impl<'a, REG> PselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Input 0p"] - #[inline(always)] - pub fn input_0(self) -> &'a mut crate::W { - self.variant(Psel::Input0) - } - #[doc = "Input 1p"] - #[inline(always)] - pub fn input_1(self) -> &'a mut crate::W { - self.variant(Psel::Input1) - } - #[doc = "Input 2p"] - #[inline(always)] - pub fn input_2(self) -> &'a mut crate::W { - self.variant(Psel::Input2) - } - #[doc = "Input 3p"] - #[inline(always)] - pub fn input_3(self) -> &'a mut crate::W { - self.variant(Psel::Input3) - } - #[doc = "Input 4p"] - #[inline(always)] - pub fn input_4(self) -> &'a mut crate::W { - self.variant(Psel::Input4) - } - #[doc = "Input 5p"] - #[inline(always)] - pub fn input_5(self) -> &'a mut crate::W { - self.variant(Psel::Input5) - } - #[doc = "Internal DAC output"] - #[inline(always)] - pub fn input_7(self) -> &'a mut crate::W { - self.variant(Psel::Input7) - } -} -#[doc = "Minus Input MUX Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Msel { - #[doc = "0: Input 0m"] - Input0 = 0, - #[doc = "1: Input 1m"] - Input1 = 1, - #[doc = "2: Input 2m"] - Input2 = 2, - #[doc = "3: Input 3m"] - Input3 = 3, - #[doc = "4: Input 4m"] - Input4 = 4, - #[doc = "5: Input 5m"] - Input5 = 5, - #[doc = "7: Internal DAC output"] - Input7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Msel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Msel { - type Ux = u8; -} -impl crate::IsEnum for Msel {} -#[doc = "Field `MSEL` reader - Minus Input MUX Select"] -pub type MselR = crate::FieldReader; -impl MselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Msel::Input0), - 1 => Some(Msel::Input1), - 2 => Some(Msel::Input2), - 3 => Some(Msel::Input3), - 4 => Some(Msel::Input4), - 5 => Some(Msel::Input5), - 7 => Some(Msel::Input7), - _ => None, - } - } - #[doc = "Input 0m"] - #[inline(always)] - pub fn is_input_0(&self) -> bool { - *self == Msel::Input0 - } - #[doc = "Input 1m"] - #[inline(always)] - pub fn is_input_1(&self) -> bool { - *self == Msel::Input1 - } - #[doc = "Input 2m"] - #[inline(always)] - pub fn is_input_2(&self) -> bool { - *self == Msel::Input2 - } - #[doc = "Input 3m"] - #[inline(always)] - pub fn is_input_3(&self) -> bool { - *self == Msel::Input3 - } - #[doc = "Input 4m"] - #[inline(always)] - pub fn is_input_4(&self) -> bool { - *self == Msel::Input4 - } - #[doc = "Input 5m"] - #[inline(always)] - pub fn is_input_5(&self) -> bool { - *self == Msel::Input5 - } - #[doc = "Internal DAC output"] - #[inline(always)] - pub fn is_input_7(&self) -> bool { - *self == Msel::Input7 - } -} -#[doc = "Field `MSEL` writer - Minus Input MUX Select"] -pub type MselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Msel>; -impl<'a, REG> MselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Input 0m"] - #[inline(always)] - pub fn input_0(self) -> &'a mut crate::W { - self.variant(Msel::Input0) - } - #[doc = "Input 1m"] - #[inline(always)] - pub fn input_1(self) -> &'a mut crate::W { - self.variant(Msel::Input1) - } - #[doc = "Input 2m"] - #[inline(always)] - pub fn input_2(self) -> &'a mut crate::W { - self.variant(Msel::Input2) - } - #[doc = "Input 3m"] - #[inline(always)] - pub fn input_3(self) -> &'a mut crate::W { - self.variant(Msel::Input3) - } - #[doc = "Input 4m"] - #[inline(always)] - pub fn input_4(self) -> &'a mut crate::W { - self.variant(Msel::Input4) - } - #[doc = "Input 5m"] - #[inline(always)] - pub fn input_5(self) -> &'a mut crate::W { - self.variant(Msel::Input5) - } - #[doc = "Internal DAC output"] - #[inline(always)] - pub fn input_7(self) -> &'a mut crate::W { - self.variant(Msel::Input7) - } -} -impl R { - #[doc = "Bit 0 - CMP High Power Mode Select"] - #[inline(always)] - pub fn cmp_hpmd(&self) -> CmpHpmdR { - CmpHpmdR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - CMP Nano Power Mode Select"] - #[inline(always)] - pub fn cmp_npmd(&self) -> CmpNpmdR { - CmpNpmdR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 4:5 - Comparator Hysteresis Control"] - #[inline(always)] - pub fn hystctr(&self) -> HystctrR { - HystctrR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 16:18 - Plus Input MUX Select"] - #[inline(always)] - pub fn psel(&self) -> PselR { - PselR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 20:22 - Minus Input MUX Select"] - #[inline(always)] - pub fn msel(&self) -> MselR { - MselR::new(((self.bits >> 20) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - CMP High Power Mode Select"] - #[inline(always)] - pub fn cmp_hpmd(&mut self) -> CmpHpmdW { - CmpHpmdW::new(self, 0) - } - #[doc = "Bit 1 - CMP Nano Power Mode Select"] - #[inline(always)] - pub fn cmp_npmd(&mut self) -> CmpNpmdW { - CmpNpmdW::new(self, 1) - } - #[doc = "Bits 4:5 - Comparator Hysteresis Control"] - #[inline(always)] - pub fn hystctr(&mut self) -> HystctrW { - HystctrW::new(self, 4) - } - #[doc = "Bits 16:18 - Plus Input MUX Select"] - #[inline(always)] - pub fn psel(&mut self) -> PselW { - PselW::new(self, 16) - } - #[doc = "Bits 20:22 - Minus Input MUX Select"] - #[inline(always)] - pub fn msel(&mut self) -> MselW { - MselW::new(self, 20) - } -} -#[doc = "Comparator Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ccr2Spec; -impl crate::RegisterSpec for Ccr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"] -impl crate::Readable for Ccr2Spec {} -#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"] -impl crate::Writable for Ccr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CCR2 to value 0"] -impl crate::Resettable for Ccr2Spec {} diff --git a/mcxa276-pac/src/cmp0/csr.rs b/mcxa276-pac/src/cmp0/csr.rs deleted file mode 100644 index 61ed95e3f..000000000 --- a/mcxa276-pac/src/cmp0/csr.rs +++ /dev/null @@ -1,218 +0,0 @@ -#[doc = "Register `CSR` reader"] -pub type R = crate::R; -#[doc = "Register `CSR` writer"] -pub type W = crate::W; -#[doc = "Analog Comparator Flag Rising\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cfr { - #[doc = "0: Not detected"] - NotDetected = 0, - #[doc = "1: Detected"] - Detected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cfr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CFR` reader - Analog Comparator Flag Rising"] -pub type CfrR = crate::BitReader; -impl CfrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cfr { - match self.bits { - false => Cfr::NotDetected, - true => Cfr::Detected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_not_detected(&self) -> bool { - *self == Cfr::NotDetected - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_detected(&self) -> bool { - *self == Cfr::Detected - } -} -#[doc = "Field `CFR` writer - Analog Comparator Flag Rising"] -pub type CfrW<'a, REG> = crate::BitWriter1C<'a, REG, Cfr>; -impl<'a, REG> CfrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn not_detected(self) -> &'a mut crate::W { - self.variant(Cfr::NotDetected) - } - #[doc = "Detected"] - #[inline(always)] - pub fn detected(self) -> &'a mut crate::W { - self.variant(Cfr::Detected) - } -} -#[doc = "Analog Comparator Flag Falling\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cff { - #[doc = "0: Not detected"] - NotDetected = 0, - #[doc = "1: Detected"] - Detected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cff) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CFF` reader - Analog Comparator Flag Falling"] -pub type CffR = crate::BitReader; -impl CffR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cff { - match self.bits { - false => Cff::NotDetected, - true => Cff::Detected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_not_detected(&self) -> bool { - *self == Cff::NotDetected - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_detected(&self) -> bool { - *self == Cff::Detected - } -} -#[doc = "Field `CFF` writer - Analog Comparator Flag Falling"] -pub type CffW<'a, REG> = crate::BitWriter1C<'a, REG, Cff>; -impl<'a, REG> CffW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn not_detected(self) -> &'a mut crate::W { - self.variant(Cff::NotDetected) - } - #[doc = "Detected"] - #[inline(always)] - pub fn detected(self) -> &'a mut crate::W { - self.variant(Cff::Detected) - } -} -#[doc = "Round-Robin Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rrf { - #[doc = "0: Not detected"] - NotDetected = 0, - #[doc = "1: Detected"] - Detected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rrf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RRF` reader - Round-Robin Flag"] -pub type RrfR = crate::BitReader; -impl RrfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rrf { - match self.bits { - false => Rrf::NotDetected, - true => Rrf::Detected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_not_detected(&self) -> bool { - *self == Rrf::NotDetected - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_detected(&self) -> bool { - *self == Rrf::Detected - } -} -#[doc = "Field `RRF` writer - Round-Robin Flag"] -pub type RrfW<'a, REG> = crate::BitWriter1C<'a, REG, Rrf>; -impl<'a, REG> RrfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn not_detected(self) -> &'a mut crate::W { - self.variant(Rrf::NotDetected) - } - #[doc = "Detected"] - #[inline(always)] - pub fn detected(self) -> &'a mut crate::W { - self.variant(Rrf::Detected) - } -} -#[doc = "Field `COUT` reader - Analog Comparator Output"] -pub type CoutR = crate::BitReader; -impl R { - #[doc = "Bit 0 - Analog Comparator Flag Rising"] - #[inline(always)] - pub fn cfr(&self) -> CfrR { - CfrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Analog Comparator Flag Falling"] - #[inline(always)] - pub fn cff(&self) -> CffR { - CffR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Round-Robin Flag"] - #[inline(always)] - pub fn rrf(&self) -> RrfR { - RrfR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 8 - Analog Comparator Output"] - #[inline(always)] - pub fn cout(&self) -> CoutR { - CoutR::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Analog Comparator Flag Rising"] - #[inline(always)] - pub fn cfr(&mut self) -> CfrW { - CfrW::new(self, 0) - } - #[doc = "Bit 1 - Analog Comparator Flag Falling"] - #[inline(always)] - pub fn cff(&mut self) -> CffW { - CffW::new(self, 1) - } - #[doc = "Bit 2 - Round-Robin Flag"] - #[inline(always)] - pub fn rrf(&mut self) -> RrfW { - RrfW::new(self, 2) - } -} -#[doc = "Comparator Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CsrSpec; -impl crate::RegisterSpec for CsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`csr::R`](R) reader structure"] -impl crate::Readable for CsrSpec {} -#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] -impl crate::Writable for CsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07; -} -#[doc = "`reset()` method sets CSR to value 0"] -impl crate::Resettable for CsrSpec {} diff --git a/mcxa276-pac/src/cmp0/dcr.rs b/mcxa276-pac/src/cmp0/dcr.rs deleted file mode 100644 index 4f96bbdc7..000000000 --- a/mcxa276-pac/src/cmp0/dcr.rs +++ /dev/null @@ -1,224 +0,0 @@ -#[doc = "Register `DCR` reader"] -pub type R = crate::R; -#[doc = "Register `DCR` writer"] -pub type W = crate::W; -#[doc = "DAC Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DacEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DacEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAC_EN` reader - DAC Enable"] -pub type DacEnR = crate::BitReader; -impl DacEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DacEn { - match self.bits { - false => DacEn::Disable, - true => DacEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DacEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DacEn::Enable - } -} -#[doc = "Field `DAC_EN` writer - DAC Enable"] -pub type DacEnW<'a, REG> = crate::BitWriter<'a, REG, DacEn>; -impl<'a, REG> DacEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DacEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DacEn::Enable) - } -} -#[doc = "DAC High Power Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DacHpmd { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DacHpmd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAC_HPMD` reader - DAC High Power Mode"] -pub type DacHpmdR = crate::BitReader; -impl DacHpmdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DacHpmd { - match self.bits { - false => DacHpmd::Disable, - true => DacHpmd::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DacHpmd::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DacHpmd::Enable - } -} -#[doc = "Field `DAC_HPMD` writer - DAC High Power Mode"] -pub type DacHpmdW<'a, REG> = crate::BitWriter<'a, REG, DacHpmd>; -impl<'a, REG> DacHpmdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DacHpmd::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DacHpmd::Enable) - } -} -#[doc = "DAC Reference High Voltage Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Vrsel { - #[doc = "0: VREFH0"] - Vref0 = 0, - #[doc = "1: VREFH1"] - Vref1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Vrsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VRSEL` reader - DAC Reference High Voltage Source Select"] -pub type VrselR = crate::BitReader; -impl VrselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Vrsel { - match self.bits { - false => Vrsel::Vref0, - true => Vrsel::Vref1, - } - } - #[doc = "VREFH0"] - #[inline(always)] - pub fn is_vref0(&self) -> bool { - *self == Vrsel::Vref0 - } - #[doc = "VREFH1"] - #[inline(always)] - pub fn is_vref1(&self) -> bool { - *self == Vrsel::Vref1 - } -} -#[doc = "Field `VRSEL` writer - DAC Reference High Voltage Source Select"] -pub type VrselW<'a, REG> = crate::BitWriter<'a, REG, Vrsel>; -impl<'a, REG> VrselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "VREFH0"] - #[inline(always)] - pub fn vref0(self) -> &'a mut crate::W { - self.variant(Vrsel::Vref0) - } - #[doc = "VREFH1"] - #[inline(always)] - pub fn vref1(self) -> &'a mut crate::W { - self.variant(Vrsel::Vref1) - } -} -#[doc = "Field `DAC_DATA` reader - DAC Output Voltage Select"] -pub type DacDataR = crate::FieldReader; -#[doc = "Field `DAC_DATA` writer - DAC Output Voltage Select"] -pub type DacDataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bit 0 - DAC Enable"] - #[inline(always)] - pub fn dac_en(&self) -> DacEnR { - DacEnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - DAC High Power Mode"] - #[inline(always)] - pub fn dac_hpmd(&self) -> DacHpmdR { - DacHpmdR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - DAC Reference High Voltage Source Select"] - #[inline(always)] - pub fn vrsel(&self) -> VrselR { - VrselR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 16:23 - DAC Output Voltage Select"] - #[inline(always)] - pub fn dac_data(&self) -> DacDataR { - DacDataR::new(((self.bits >> 16) & 0xff) as u8) - } -} -impl W { - #[doc = "Bit 0 - DAC Enable"] - #[inline(always)] - pub fn dac_en(&mut self) -> DacEnW { - DacEnW::new(self, 0) - } - #[doc = "Bit 1 - DAC High Power Mode"] - #[inline(always)] - pub fn dac_hpmd(&mut self) -> DacHpmdW { - DacHpmdW::new(self, 1) - } - #[doc = "Bit 8 - DAC Reference High Voltage Source Select"] - #[inline(always)] - pub fn vrsel(&mut self) -> VrselW { - VrselW::new(self, 8) - } - #[doc = "Bits 16:23 - DAC Output Voltage Select"] - #[inline(always)] - pub fn dac_data(&mut self) -> DacDataW { - DacDataW::new(self, 16) - } -} -#[doc = "DAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DcrSpec; -impl crate::RegisterSpec for DcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`dcr::R`](R) reader structure"] -impl crate::Readable for DcrSpec {} -#[doc = "`write(|w| ..)` method takes [`dcr::W`](W) writer structure"] -impl crate::Writable for DcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DCR to value 0"] -impl crate::Resettable for DcrSpec {} diff --git a/mcxa276-pac/src/cmp0/ier.rs b/mcxa276-pac/src/cmp0/ier.rs deleted file mode 100644 index 779ec81ca..000000000 --- a/mcxa276-pac/src/cmp0/ier.rs +++ /dev/null @@ -1,210 +0,0 @@ -#[doc = "Register `IER` reader"] -pub type R = crate::R; -#[doc = "Register `IER` writer"] -pub type W = crate::W; -#[doc = "Comparator Flag Rising Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CfrIe { - #[doc = "0: Disables the comparator flag rising interrupt."] - Disable = 0, - #[doc = "1: Enables the comparator flag rising interrupt when CFR is set."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CfrIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CFR_IE` reader - Comparator Flag Rising Interrupt Enable"] -pub type CfrIeR = crate::BitReader; -impl CfrIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CfrIe { - match self.bits { - false => CfrIe::Disable, - true => CfrIe::Enable, - } - } - #[doc = "Disables the comparator flag rising interrupt."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == CfrIe::Disable - } - #[doc = "Enables the comparator flag rising interrupt when CFR is set."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == CfrIe::Enable - } -} -#[doc = "Field `CFR_IE` writer - Comparator Flag Rising Interrupt Enable"] -pub type CfrIeW<'a, REG> = crate::BitWriter<'a, REG, CfrIe>; -impl<'a, REG> CfrIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables the comparator flag rising interrupt."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(CfrIe::Disable) - } - #[doc = "Enables the comparator flag rising interrupt when CFR is set."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(CfrIe::Enable) - } -} -#[doc = "Comparator Flag Falling Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CffIe { - #[doc = "0: Disables the comparator flag falling interrupt."] - Disable = 0, - #[doc = "1: Enables the comparator flag falling interrupt when CFF is set."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CffIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CFF_IE` reader - Comparator Flag Falling Interrupt Enable"] -pub type CffIeR = crate::BitReader; -impl CffIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CffIe { - match self.bits { - false => CffIe::Disable, - true => CffIe::Enable, - } - } - #[doc = "Disables the comparator flag falling interrupt."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == CffIe::Disable - } - #[doc = "Enables the comparator flag falling interrupt when CFF is set."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == CffIe::Enable - } -} -#[doc = "Field `CFF_IE` writer - Comparator Flag Falling Interrupt Enable"] -pub type CffIeW<'a, REG> = crate::BitWriter<'a, REG, CffIe>; -impl<'a, REG> CffIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables the comparator flag falling interrupt."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(CffIe::Disable) - } - #[doc = "Enables the comparator flag falling interrupt when CFF is set."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(CffIe::Enable) - } -} -#[doc = "Round-Robin Flag Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrfIe { - #[doc = "0: Disables the round-robin flag interrupt."] - Disable = 0, - #[doc = "1: Enables the round-robin flag interrupt when the comparison result changes for a given channel."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrfIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RRF_IE` reader - Round-Robin Flag Interrupt Enable"] -pub type RrfIeR = crate::BitReader; -impl RrfIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrfIe { - match self.bits { - false => RrfIe::Disable, - true => RrfIe::Enable, - } - } - #[doc = "Disables the round-robin flag interrupt."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrfIe::Disable - } - #[doc = "Enables the round-robin flag interrupt when the comparison result changes for a given channel."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrfIe::Enable - } -} -#[doc = "Field `RRF_IE` writer - Round-Robin Flag Interrupt Enable"] -pub type RrfIeW<'a, REG> = crate::BitWriter<'a, REG, RrfIe>; -impl<'a, REG> RrfIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables the round-robin flag interrupt."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrfIe::Disable) - } - #[doc = "Enables the round-robin flag interrupt when the comparison result changes for a given channel."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrfIe::Enable) - } -} -impl R { - #[doc = "Bit 0 - Comparator Flag Rising Interrupt Enable"] - #[inline(always)] - pub fn cfr_ie(&self) -> CfrIeR { - CfrIeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Comparator Flag Falling Interrupt Enable"] - #[inline(always)] - pub fn cff_ie(&self) -> CffIeR { - CffIeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Round-Robin Flag Interrupt Enable"] - #[inline(always)] - pub fn rrf_ie(&self) -> RrfIeR { - RrfIeR::new(((self.bits >> 2) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Comparator Flag Rising Interrupt Enable"] - #[inline(always)] - pub fn cfr_ie(&mut self) -> CfrIeW { - CfrIeW::new(self, 0) - } - #[doc = "Bit 1 - Comparator Flag Falling Interrupt Enable"] - #[inline(always)] - pub fn cff_ie(&mut self) -> CffIeW { - CffIeW::new(self, 1) - } - #[doc = "Bit 2 - Round-Robin Flag Interrupt Enable"] - #[inline(always)] - pub fn rrf_ie(&mut self) -> RrfIeW { - RrfIeW::new(self, 2) - } -} -#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IerSpec; -impl crate::RegisterSpec for IerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ier::R`](R) reader structure"] -impl crate::Readable for IerSpec {} -#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] -impl crate::Writable for IerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IER to value 0"] -impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/cmp0/param.rs b/mcxa276-pac/src/cmp0/param.rs deleted file mode 100644 index ae1716e32..000000000 --- a/mcxa276-pac/src/cmp0/param.rs +++ /dev/null @@ -1,102 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "DAC Resolution\n\nValue on reset: 2"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum DacRes { - #[doc = "0: 4-bit DAC"] - Reso4 = 0, - #[doc = "1: 6-bit DAC"] - Reso6 = 1, - #[doc = "2: 8-bit DAC"] - Reso8 = 2, - #[doc = "3: 10-bit DAC"] - Reso10 = 3, - #[doc = "4: 12-bit DAC"] - Reso12 = 4, - #[doc = "5: 14-bit DAC"] - Reso14 = 5, - #[doc = "6: 16-bit DAC"] - Reso16 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: DacRes) -> Self { - variant as _ - } -} -impl crate::FieldSpec for DacRes { - type Ux = u8; -} -impl crate::IsEnum for DacRes {} -#[doc = "Field `DAC_RES` reader - DAC Resolution"] -pub type DacResR = crate::FieldReader; -impl DacResR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(DacRes::Reso4), - 1 => Some(DacRes::Reso6), - 2 => Some(DacRes::Reso8), - 3 => Some(DacRes::Reso10), - 4 => Some(DacRes::Reso12), - 5 => Some(DacRes::Reso14), - 6 => Some(DacRes::Reso16), - _ => None, - } - } - #[doc = "4-bit DAC"] - #[inline(always)] - pub fn is_reso_4(&self) -> bool { - *self == DacRes::Reso4 - } - #[doc = "6-bit DAC"] - #[inline(always)] - pub fn is_reso_6(&self) -> bool { - *self == DacRes::Reso6 - } - #[doc = "8-bit DAC"] - #[inline(always)] - pub fn is_reso_8(&self) -> bool { - *self == DacRes::Reso8 - } - #[doc = "10-bit DAC"] - #[inline(always)] - pub fn is_reso_10(&self) -> bool { - *self == DacRes::Reso10 - } - #[doc = "12-bit DAC"] - #[inline(always)] - pub fn is_reso_12(&self) -> bool { - *self == DacRes::Reso12 - } - #[doc = "14-bit DAC"] - #[inline(always)] - pub fn is_reso_14(&self) -> bool { - *self == DacRes::Reso14 - } - #[doc = "16-bit DAC"] - #[inline(always)] - pub fn is_reso_16(&self) -> bool { - *self == DacRes::Reso16 - } -} -impl R { - #[doc = "Bits 0:3 - DAC Resolution"] - #[inline(always)] - pub fn dac_res(&self) -> DacResR { - DacResR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x02"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x02; -} diff --git a/mcxa276-pac/src/cmp0/rrcr0.rs b/mcxa276-pac/src/cmp0/rrcr0.rs deleted file mode 100644 index 308dcbd49..000000000 --- a/mcxa276-pac/src/cmp0/rrcr0.rs +++ /dev/null @@ -1,1018 +0,0 @@ -#[doc = "Register `RRCR0` reader"] -pub type R = crate::R; -#[doc = "Register `RRCR0` writer"] -pub type W = crate::W; -#[doc = "Round-Robin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_EN` reader - Round-Robin Enable"] -pub type RrEnR = crate::BitReader; -impl RrEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrEn { - match self.bits { - false => RrEn::Disable, - true => RrEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrEn::Enable - } -} -#[doc = "Field `RR_EN` writer - Round-Robin Enable"] -pub type RrEnW<'a, REG> = crate::BitWriter<'a, REG, RrEn>; -impl<'a, REG> RrEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrEn::Enable) - } -} -#[doc = "Round-Robin Trigger Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrTrgSel { - #[doc = "0: External trigger"] - Enable = 0, - #[doc = "1: Internal trigger"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrTrgSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_TRG_SEL` reader - Round-Robin Trigger Select"] -pub type RrTrgSelR = crate::BitReader; -impl RrTrgSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrTrgSel { - match self.bits { - false => RrTrgSel::Enable, - true => RrTrgSel::Disable, - } - } - #[doc = "External trigger"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrTrgSel::Enable - } - #[doc = "Internal trigger"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrTrgSel::Disable - } -} -#[doc = "Field `RR_TRG_SEL` writer - Round-Robin Trigger Select"] -pub type RrTrgSelW<'a, REG> = crate::BitWriter<'a, REG, RrTrgSel>; -impl<'a, REG> RrTrgSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "External trigger"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrTrgSel::Enable) - } - #[doc = "Internal trigger"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrTrgSel::Disable) - } -} -#[doc = "Number of Sample Clocks\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum RrNsam { - #[doc = "0: 0 clock"] - Wait0 = 0, - #[doc = "1: 1 clock"] - Wait1 = 1, - #[doc = "2: 2 clocks"] - Wait2 = 2, - #[doc = "3: 3 clocks"] - Wait3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: RrNsam) -> Self { - variant as _ - } -} -impl crate::FieldSpec for RrNsam { - type Ux = u8; -} -impl crate::IsEnum for RrNsam {} -#[doc = "Field `RR_NSAM` reader - Number of Sample Clocks"] -pub type RrNsamR = crate::FieldReader; -impl RrNsamR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrNsam { - match self.bits { - 0 => RrNsam::Wait0, - 1 => RrNsam::Wait1, - 2 => RrNsam::Wait2, - 3 => RrNsam::Wait3, - _ => unreachable!(), - } - } - #[doc = "0 clock"] - #[inline(always)] - pub fn is_wait_0(&self) -> bool { - *self == RrNsam::Wait0 - } - #[doc = "1 clock"] - #[inline(always)] - pub fn is_wait_1(&self) -> bool { - *self == RrNsam::Wait1 - } - #[doc = "2 clocks"] - #[inline(always)] - pub fn is_wait_2(&self) -> bool { - *self == RrNsam::Wait2 - } - #[doc = "3 clocks"] - #[inline(always)] - pub fn is_wait_3(&self) -> bool { - *self == RrNsam::Wait3 - } -} -#[doc = "Field `RR_NSAM` writer - Number of Sample Clocks"] -pub type RrNsamW<'a, REG> = crate::FieldWriter<'a, REG, 2, RrNsam, crate::Safe>; -impl<'a, REG> RrNsamW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "0 clock"] - #[inline(always)] - pub fn wait_0(self) -> &'a mut crate::W { - self.variant(RrNsam::Wait0) - } - #[doc = "1 clock"] - #[inline(always)] - pub fn wait_1(self) -> &'a mut crate::W { - self.variant(RrNsam::Wait1) - } - #[doc = "2 clocks"] - #[inline(always)] - pub fn wait_2(self) -> &'a mut crate::W { - self.variant(RrNsam::Wait2) - } - #[doc = "3 clocks"] - #[inline(always)] - pub fn wait_3(self) -> &'a mut crate::W { - self.variant(RrNsam::Wait3) - } -} -#[doc = "Round Robin Clock Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum RrClkSel { - #[doc = "0: Select Round Robin clock Source 0"] - Rr0 = 0, - #[doc = "1: Select Round Robin clock Source 1"] - Rr1 = 1, - #[doc = "2: Select Round Robin clock Source 2"] - Rr2 = 2, - #[doc = "3: Select Round Robin clock Source 3"] - Rr3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: RrClkSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for RrClkSel { - type Ux = u8; -} -impl crate::IsEnum for RrClkSel {} -#[doc = "Field `RR_CLK_SEL` reader - Round Robin Clock Source Select"] -pub type RrClkSelR = crate::FieldReader; -impl RrClkSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrClkSel { - match self.bits { - 0 => RrClkSel::Rr0, - 1 => RrClkSel::Rr1, - 2 => RrClkSel::Rr2, - 3 => RrClkSel::Rr3, - _ => unreachable!(), - } - } - #[doc = "Select Round Robin clock Source 0"] - #[inline(always)] - pub fn is_rr0(&self) -> bool { - *self == RrClkSel::Rr0 - } - #[doc = "Select Round Robin clock Source 1"] - #[inline(always)] - pub fn is_rr1(&self) -> bool { - *self == RrClkSel::Rr1 - } - #[doc = "Select Round Robin clock Source 2"] - #[inline(always)] - pub fn is_rr2(&self) -> bool { - *self == RrClkSel::Rr2 - } - #[doc = "Select Round Robin clock Source 3"] - #[inline(always)] - pub fn is_rr3(&self) -> bool { - *self == RrClkSel::Rr3 - } -} -#[doc = "Field `RR_CLK_SEL` writer - Round Robin Clock Source Select"] -pub type RrClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, RrClkSel, crate::Safe>; -impl<'a, REG> RrClkSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Select Round Robin clock Source 0"] - #[inline(always)] - pub fn rr0(self) -> &'a mut crate::W { - self.variant(RrClkSel::Rr0) - } - #[doc = "Select Round Robin clock Source 1"] - #[inline(always)] - pub fn rr1(self) -> &'a mut crate::W { - self.variant(RrClkSel::Rr1) - } - #[doc = "Select Round Robin clock Source 2"] - #[inline(always)] - pub fn rr2(self) -> &'a mut crate::W { - self.variant(RrClkSel::Rr2) - } - #[doc = "Select Round Robin clock Source 3"] - #[inline(always)] - pub fn rr3(self) -> &'a mut crate::W { - self.variant(RrClkSel::Rr3) - } -} -#[doc = "Initialization Delay Modulus\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum RrInitmod { - #[doc = "0: 63 cycles (same as 111111b)"] - Mod63 = 0, - #[doc = "1: 1 to 63 cycles"] - Mod1_63_1 = 1, - #[doc = "2: 1 to 63 cycles"] - Mod1_63_2 = 2, - #[doc = "3: 1 to 63 cycles"] - Mod1_63_3 = 3, - #[doc = "4: 1 to 63 cycles"] - Mod1_63_4 = 4, - #[doc = "5: 1 to 63 cycles"] - Mod1_63_5 = 5, - #[doc = "6: 1 to 63 cycles"] - Mod1_63_6 = 6, - #[doc = "7: 1 to 63 cycles"] - Mod1_63_7 = 7, - #[doc = "8: 1 to 63 cycles"] - Mod1_63_8 = 8, - #[doc = "9: 1 to 63 cycles"] - Mod1_63_9 = 9, -} -impl From for u8 { - #[inline(always)] - fn from(variant: RrInitmod) -> Self { - variant as _ - } -} -impl crate::FieldSpec for RrInitmod { - type Ux = u8; -} -impl crate::IsEnum for RrInitmod {} -#[doc = "Field `RR_INITMOD` reader - Initialization Delay Modulus"] -pub type RrInitmodR = crate::FieldReader; -impl RrInitmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(RrInitmod::Mod63), - 1 => Some(RrInitmod::Mod1_63_1), - 2 => Some(RrInitmod::Mod1_63_2), - 3 => Some(RrInitmod::Mod1_63_3), - 4 => Some(RrInitmod::Mod1_63_4), - 5 => Some(RrInitmod::Mod1_63_5), - 6 => Some(RrInitmod::Mod1_63_6), - 7 => Some(RrInitmod::Mod1_63_7), - 8 => Some(RrInitmod::Mod1_63_8), - 9 => Some(RrInitmod::Mod1_63_9), - _ => None, - } - } - #[doc = "63 cycles (same as 111111b)"] - #[inline(always)] - pub fn is_mod_63(&self) -> bool { - *self == RrInitmod::Mod63 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_1(&self) -> bool { - *self == RrInitmod::Mod1_63_1 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_2(&self) -> bool { - *self == RrInitmod::Mod1_63_2 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_3(&self) -> bool { - *self == RrInitmod::Mod1_63_3 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_4(&self) -> bool { - *self == RrInitmod::Mod1_63_4 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_5(&self) -> bool { - *self == RrInitmod::Mod1_63_5 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_6(&self) -> bool { - *self == RrInitmod::Mod1_63_6 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_7(&self) -> bool { - *self == RrInitmod::Mod1_63_7 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_8(&self) -> bool { - *self == RrInitmod::Mod1_63_8 - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn is_mod_1_63_9(&self) -> bool { - *self == RrInitmod::Mod1_63_9 - } -} -#[doc = "Field `RR_INITMOD` writer - Initialization Delay Modulus"] -pub type RrInitmodW<'a, REG> = crate::FieldWriter<'a, REG, 6, RrInitmod>; -impl<'a, REG> RrInitmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "63 cycles (same as 111111b)"] - #[inline(always)] - pub fn mod_63(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod63) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_1(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_1) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_2(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_2) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_3(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_3) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_4(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_4) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_5(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_5) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_6(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_6) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_7(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_7) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_8(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_8) - } - #[doc = "1 to 63 cycles"] - #[inline(always)] - pub fn mod_1_63_9(self) -> &'a mut crate::W { - self.variant(RrInitmod::Mod1_63_9) - } -} -#[doc = "Number of Sample for One Channel\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum RrSampleCnt { - #[doc = "0: 1 samples"] - Sample0 = 0, - #[doc = "1: 2 samples"] - Sample1 = 1, - #[doc = "2: 3 samples"] - Sample2 = 2, - #[doc = "3: 4 samples"] - Sample3 = 3, - #[doc = "4: 5 samples"] - Sample4 = 4, - #[doc = "5: 6 samples"] - Sample5 = 5, - #[doc = "6: 7 samples"] - Sample6 = 6, - #[doc = "7: 8 samples"] - Sample7 = 7, - #[doc = "8: 9 samples"] - Sample8 = 8, - #[doc = "9: 10 samples"] - Sample9 = 9, - #[doc = "10: 11 samples"] - Sample10 = 10, - #[doc = "11: 12 samples"] - Sample11 = 11, - #[doc = "12: 13 samples"] - Sample12 = 12, - #[doc = "13: 14 samples"] - Sample13 = 13, - #[doc = "14: 15 samples"] - Sample14 = 14, - #[doc = "15: 16 samples"] - Sample15 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: RrSampleCnt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for RrSampleCnt { - type Ux = u8; -} -impl crate::IsEnum for RrSampleCnt {} -#[doc = "Field `RR_SAMPLE_CNT` reader - Number of Sample for One Channel"] -pub type RrSampleCntR = crate::FieldReader; -impl RrSampleCntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrSampleCnt { - match self.bits { - 0 => RrSampleCnt::Sample0, - 1 => RrSampleCnt::Sample1, - 2 => RrSampleCnt::Sample2, - 3 => RrSampleCnt::Sample3, - 4 => RrSampleCnt::Sample4, - 5 => RrSampleCnt::Sample5, - 6 => RrSampleCnt::Sample6, - 7 => RrSampleCnt::Sample7, - 8 => RrSampleCnt::Sample8, - 9 => RrSampleCnt::Sample9, - 10 => RrSampleCnt::Sample10, - 11 => RrSampleCnt::Sample11, - 12 => RrSampleCnt::Sample12, - 13 => RrSampleCnt::Sample13, - 14 => RrSampleCnt::Sample14, - 15 => RrSampleCnt::Sample15, - _ => unreachable!(), - } - } - #[doc = "1 samples"] - #[inline(always)] - pub fn is_sample_0(&self) -> bool { - *self == RrSampleCnt::Sample0 - } - #[doc = "2 samples"] - #[inline(always)] - pub fn is_sample_1(&self) -> bool { - *self == RrSampleCnt::Sample1 - } - #[doc = "3 samples"] - #[inline(always)] - pub fn is_sample_2(&self) -> bool { - *self == RrSampleCnt::Sample2 - } - #[doc = "4 samples"] - #[inline(always)] - pub fn is_sample_3(&self) -> bool { - *self == RrSampleCnt::Sample3 - } - #[doc = "5 samples"] - #[inline(always)] - pub fn is_sample_4(&self) -> bool { - *self == RrSampleCnt::Sample4 - } - #[doc = "6 samples"] - #[inline(always)] - pub fn is_sample_5(&self) -> bool { - *self == RrSampleCnt::Sample5 - } - #[doc = "7 samples"] - #[inline(always)] - pub fn is_sample_6(&self) -> bool { - *self == RrSampleCnt::Sample6 - } - #[doc = "8 samples"] - #[inline(always)] - pub fn is_sample_7(&self) -> bool { - *self == RrSampleCnt::Sample7 - } - #[doc = "9 samples"] - #[inline(always)] - pub fn is_sample_8(&self) -> bool { - *self == RrSampleCnt::Sample8 - } - #[doc = "10 samples"] - #[inline(always)] - pub fn is_sample_9(&self) -> bool { - *self == RrSampleCnt::Sample9 - } - #[doc = "11 samples"] - #[inline(always)] - pub fn is_sample_10(&self) -> bool { - *self == RrSampleCnt::Sample10 - } - #[doc = "12 samples"] - #[inline(always)] - pub fn is_sample_11(&self) -> bool { - *self == RrSampleCnt::Sample11 - } - #[doc = "13 samples"] - #[inline(always)] - pub fn is_sample_12(&self) -> bool { - *self == RrSampleCnt::Sample12 - } - #[doc = "14 samples"] - #[inline(always)] - pub fn is_sample_13(&self) -> bool { - *self == RrSampleCnt::Sample13 - } - #[doc = "15 samples"] - #[inline(always)] - pub fn is_sample_14(&self) -> bool { - *self == RrSampleCnt::Sample14 - } - #[doc = "16 samples"] - #[inline(always)] - pub fn is_sample_15(&self) -> bool { - *self == RrSampleCnt::Sample15 - } -} -#[doc = "Field `RR_SAMPLE_CNT` writer - Number of Sample for One Channel"] -pub type RrSampleCntW<'a, REG> = crate::FieldWriter<'a, REG, 4, RrSampleCnt, crate::Safe>; -impl<'a, REG> RrSampleCntW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "1 samples"] - #[inline(always)] - pub fn sample_0(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample0) - } - #[doc = "2 samples"] - #[inline(always)] - pub fn sample_1(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample1) - } - #[doc = "3 samples"] - #[inline(always)] - pub fn sample_2(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample2) - } - #[doc = "4 samples"] - #[inline(always)] - pub fn sample_3(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample3) - } - #[doc = "5 samples"] - #[inline(always)] - pub fn sample_4(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample4) - } - #[doc = "6 samples"] - #[inline(always)] - pub fn sample_5(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample5) - } - #[doc = "7 samples"] - #[inline(always)] - pub fn sample_6(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample6) - } - #[doc = "8 samples"] - #[inline(always)] - pub fn sample_7(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample7) - } - #[doc = "9 samples"] - #[inline(always)] - pub fn sample_8(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample8) - } - #[doc = "10 samples"] - #[inline(always)] - pub fn sample_9(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample9) - } - #[doc = "11 samples"] - #[inline(always)] - pub fn sample_10(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample10) - } - #[doc = "12 samples"] - #[inline(always)] - pub fn sample_11(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample11) - } - #[doc = "13 samples"] - #[inline(always)] - pub fn sample_12(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample12) - } - #[doc = "14 samples"] - #[inline(always)] - pub fn sample_13(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample13) - } - #[doc = "15 samples"] - #[inline(always)] - pub fn sample_14(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample14) - } - #[doc = "16 samples"] - #[inline(always)] - pub fn sample_15(self) -> &'a mut crate::W { - self.variant(RrSampleCnt::Sample15) - } -} -#[doc = "Sample Time Threshold\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum RrSampleThreshold { - #[doc = "0: At least 1 sampled \"1\", the final result is \"1\""] - Sample0 = 0, - #[doc = "1: At least 2 sampled \"1\", the final result is \"1\""] - Sample1 = 1, - #[doc = "2: At least 3 sampled \"1\", the final result is \"1\""] - Sample2 = 2, - #[doc = "3: At least 4 sampled \"1\", the final result is \"1\""] - Sample3 = 3, - #[doc = "4: At least 5 sampled \"1\", the final result is \"1\""] - Sample4 = 4, - #[doc = "5: At least 6 sampled \"1\", the final result is \"1\""] - Sample5 = 5, - #[doc = "6: At least 7 sampled \"1\", the final result is \"1\""] - Sample6 = 6, - #[doc = "7: At least 8 sampled \"1\", the final result is \"1\""] - Sample7 = 7, - #[doc = "8: At least 9 sampled \"1\", the final result is \"1\""] - Sample8 = 8, - #[doc = "9: At least 10 sampled \"1\", the final result is \"1\""] - Sample9 = 9, - #[doc = "10: At least 11 sampled \"1\", the final result is \"1\""] - Sample10 = 10, - #[doc = "11: At least 12 sampled \"1\", the final result is \"1\""] - Sample11 = 11, - #[doc = "12: At least 13 sampled \"1\", the final result is \"1\""] - Sample12 = 12, - #[doc = "13: At least 14 sampled \"1\", the final result is \"1\""] - Sample13 = 13, - #[doc = "14: At least 15 sampled \"1\", the final result is \"1\""] - Sample14 = 14, - #[doc = "15: At least 16 sampled \"1\", the final result is \"1\""] - Sample15 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: RrSampleThreshold) -> Self { - variant as _ - } -} -impl crate::FieldSpec for RrSampleThreshold { - type Ux = u8; -} -impl crate::IsEnum for RrSampleThreshold {} -#[doc = "Field `RR_SAMPLE_THRESHOLD` reader - Sample Time Threshold"] -pub type RrSampleThresholdR = crate::FieldReader; -impl RrSampleThresholdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrSampleThreshold { - match self.bits { - 0 => RrSampleThreshold::Sample0, - 1 => RrSampleThreshold::Sample1, - 2 => RrSampleThreshold::Sample2, - 3 => RrSampleThreshold::Sample3, - 4 => RrSampleThreshold::Sample4, - 5 => RrSampleThreshold::Sample5, - 6 => RrSampleThreshold::Sample6, - 7 => RrSampleThreshold::Sample7, - 8 => RrSampleThreshold::Sample8, - 9 => RrSampleThreshold::Sample9, - 10 => RrSampleThreshold::Sample10, - 11 => RrSampleThreshold::Sample11, - 12 => RrSampleThreshold::Sample12, - 13 => RrSampleThreshold::Sample13, - 14 => RrSampleThreshold::Sample14, - 15 => RrSampleThreshold::Sample15, - _ => unreachable!(), - } - } - #[doc = "At least 1 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_0(&self) -> bool { - *self == RrSampleThreshold::Sample0 - } - #[doc = "At least 2 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_1(&self) -> bool { - *self == RrSampleThreshold::Sample1 - } - #[doc = "At least 3 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_2(&self) -> bool { - *self == RrSampleThreshold::Sample2 - } - #[doc = "At least 4 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_3(&self) -> bool { - *self == RrSampleThreshold::Sample3 - } - #[doc = "At least 5 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_4(&self) -> bool { - *self == RrSampleThreshold::Sample4 - } - #[doc = "At least 6 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_5(&self) -> bool { - *self == RrSampleThreshold::Sample5 - } - #[doc = "At least 7 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_6(&self) -> bool { - *self == RrSampleThreshold::Sample6 - } - #[doc = "At least 8 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_7(&self) -> bool { - *self == RrSampleThreshold::Sample7 - } - #[doc = "At least 9 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_8(&self) -> bool { - *self == RrSampleThreshold::Sample8 - } - #[doc = "At least 10 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_9(&self) -> bool { - *self == RrSampleThreshold::Sample9 - } - #[doc = "At least 11 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_10(&self) -> bool { - *self == RrSampleThreshold::Sample10 - } - #[doc = "At least 12 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_11(&self) -> bool { - *self == RrSampleThreshold::Sample11 - } - #[doc = "At least 13 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_12(&self) -> bool { - *self == RrSampleThreshold::Sample12 - } - #[doc = "At least 14 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_13(&self) -> bool { - *self == RrSampleThreshold::Sample13 - } - #[doc = "At least 15 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_14(&self) -> bool { - *self == RrSampleThreshold::Sample14 - } - #[doc = "At least 16 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn is_sample_15(&self) -> bool { - *self == RrSampleThreshold::Sample15 - } -} -#[doc = "Field `RR_SAMPLE_THRESHOLD` writer - Sample Time Threshold"] -pub type RrSampleThresholdW<'a, REG> = - crate::FieldWriter<'a, REG, 4, RrSampleThreshold, crate::Safe>; -impl<'a, REG> RrSampleThresholdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "At least 1 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_0(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample0) - } - #[doc = "At least 2 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_1(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample1) - } - #[doc = "At least 3 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_2(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample2) - } - #[doc = "At least 4 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_3(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample3) - } - #[doc = "At least 5 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_4(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample4) - } - #[doc = "At least 6 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_5(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample5) - } - #[doc = "At least 7 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_6(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample6) - } - #[doc = "At least 8 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_7(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample7) - } - #[doc = "At least 9 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_8(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample8) - } - #[doc = "At least 10 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_9(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample9) - } - #[doc = "At least 11 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_10(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample10) - } - #[doc = "At least 12 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_11(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample11) - } - #[doc = "At least 13 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_12(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample12) - } - #[doc = "At least 14 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_13(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample13) - } - #[doc = "At least 15 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_14(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample14) - } - #[doc = "At least 16 sampled \"1\", the final result is \"1\""] - #[inline(always)] - pub fn sample_15(self) -> &'a mut crate::W { - self.variant(RrSampleThreshold::Sample15) - } -} -impl R { - #[doc = "Bit 0 - Round-Robin Enable"] - #[inline(always)] - pub fn rr_en(&self) -> RrEnR { - RrEnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Round-Robin Trigger Select"] - #[inline(always)] - pub fn rr_trg_sel(&self) -> RrTrgSelR { - RrTrgSelR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 8:9 - Number of Sample Clocks"] - #[inline(always)] - pub fn rr_nsam(&self) -> RrNsamR { - RrNsamR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 12:13 - Round Robin Clock Source Select"] - #[inline(always)] - pub fn rr_clk_sel(&self) -> RrClkSelR { - RrClkSelR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 16:21 - Initialization Delay Modulus"] - #[inline(always)] - pub fn rr_initmod(&self) -> RrInitmodR { - RrInitmodR::new(((self.bits >> 16) & 0x3f) as u8) - } - #[doc = "Bits 24:27 - Number of Sample for One Channel"] - #[inline(always)] - pub fn rr_sample_cnt(&self) -> RrSampleCntR { - RrSampleCntR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bits 28:31 - Sample Time Threshold"] - #[inline(always)] - pub fn rr_sample_threshold(&self) -> RrSampleThresholdR { - RrSampleThresholdR::new(((self.bits >> 28) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Round-Robin Enable"] - #[inline(always)] - pub fn rr_en(&mut self) -> RrEnW { - RrEnW::new(self, 0) - } - #[doc = "Bit 1 - Round-Robin Trigger Select"] - #[inline(always)] - pub fn rr_trg_sel(&mut self) -> RrTrgSelW { - RrTrgSelW::new(self, 1) - } - #[doc = "Bits 8:9 - Number of Sample Clocks"] - #[inline(always)] - pub fn rr_nsam(&mut self) -> RrNsamW { - RrNsamW::new(self, 8) - } - #[doc = "Bits 12:13 - Round Robin Clock Source Select"] - #[inline(always)] - pub fn rr_clk_sel(&mut self) -> RrClkSelW { - RrClkSelW::new(self, 12) - } - #[doc = "Bits 16:21 - Initialization Delay Modulus"] - #[inline(always)] - pub fn rr_initmod(&mut self) -> RrInitmodW { - RrInitmodW::new(self, 16) - } - #[doc = "Bits 24:27 - Number of Sample for One Channel"] - #[inline(always)] - pub fn rr_sample_cnt(&mut self) -> RrSampleCntW { - RrSampleCntW::new(self, 24) - } - #[doc = "Bits 28:31 - Sample Time Threshold"] - #[inline(always)] - pub fn rr_sample_threshold(&mut self) -> RrSampleThresholdW { - RrSampleThresholdW::new(self, 28) - } -} -#[doc = "Round Robin Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Rrcr0Spec; -impl crate::RegisterSpec for Rrcr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rrcr0::R`](R) reader structure"] -impl crate::Readable for Rrcr0Spec {} -#[doc = "`write(|w| ..)` method takes [`rrcr0::W`](W) writer structure"] -impl crate::Writable for Rrcr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RRCR0 to value 0"] -impl crate::Resettable for Rrcr0Spec {} diff --git a/mcxa276-pac/src/cmp0/rrcr1.rs b/mcxa276-pac/src/cmp0/rrcr1.rs deleted file mode 100644 index 5f4eac415..000000000 --- a/mcxa276-pac/src/cmp0/rrcr1.rs +++ /dev/null @@ -1,736 +0,0 @@ -#[doc = "Register `RRCR1` reader"] -pub type R = crate::R; -#[doc = "Register `RRCR1` writer"] -pub type W = crate::W; -#[doc = "Channel 0 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh0en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh0en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH0EN` reader - Channel 0 Input Enable in Trigger Mode"] -pub type RrCh0enR = crate::BitReader; -impl RrCh0enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh0en { - match self.bits { - false => RrCh0en::Disable, - true => RrCh0en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh0en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh0en::Enable - } -} -#[doc = "Field `RR_CH0EN` writer - Channel 0 Input Enable in Trigger Mode"] -pub type RrCh0enW<'a, REG> = crate::BitWriter<'a, REG, RrCh0en>; -impl<'a, REG> RrCh0enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh0en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh0en::Enable) - } -} -#[doc = "Channel 1 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh1en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh1en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH1EN` reader - Channel 1 Input Enable in Trigger Mode"] -pub type RrCh1enR = crate::BitReader; -impl RrCh1enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh1en { - match self.bits { - false => RrCh1en::Disable, - true => RrCh1en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh1en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh1en::Enable - } -} -#[doc = "Field `RR_CH1EN` writer - Channel 1 Input Enable in Trigger Mode"] -pub type RrCh1enW<'a, REG> = crate::BitWriter<'a, REG, RrCh1en>; -impl<'a, REG> RrCh1enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh1en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh1en::Enable) - } -} -#[doc = "Channel 2 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh2en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh2en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH2EN` reader - Channel 2 Input Enable in Trigger Mode"] -pub type RrCh2enR = crate::BitReader; -impl RrCh2enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh2en { - match self.bits { - false => RrCh2en::Disable, - true => RrCh2en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh2en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh2en::Enable - } -} -#[doc = "Field `RR_CH2EN` writer - Channel 2 Input Enable in Trigger Mode"] -pub type RrCh2enW<'a, REG> = crate::BitWriter<'a, REG, RrCh2en>; -impl<'a, REG> RrCh2enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh2en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh2en::Enable) - } -} -#[doc = "Channel 3 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh3en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh3en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH3EN` reader - Channel 3 Input Enable in Trigger Mode"] -pub type RrCh3enR = crate::BitReader; -impl RrCh3enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh3en { - match self.bits { - false => RrCh3en::Disable, - true => RrCh3en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh3en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh3en::Enable - } -} -#[doc = "Field `RR_CH3EN` writer - Channel 3 Input Enable in Trigger Mode"] -pub type RrCh3enW<'a, REG> = crate::BitWriter<'a, REG, RrCh3en>; -impl<'a, REG> RrCh3enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh3en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh3en::Enable) - } -} -#[doc = "Channel 4 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh4en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh4en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH4EN` reader - Channel 4 Input Enable in Trigger Mode"] -pub type RrCh4enR = crate::BitReader; -impl RrCh4enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh4en { - match self.bits { - false => RrCh4en::Disable, - true => RrCh4en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh4en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh4en::Enable - } -} -#[doc = "Field `RR_CH4EN` writer - Channel 4 Input Enable in Trigger Mode"] -pub type RrCh4enW<'a, REG> = crate::BitWriter<'a, REG, RrCh4en>; -impl<'a, REG> RrCh4enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh4en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh4en::Enable) - } -} -#[doc = "Channel 5 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh5en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh5en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH5EN` reader - Channel 5 Input Enable in Trigger Mode"] -pub type RrCh5enR = crate::BitReader; -impl RrCh5enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh5en { - match self.bits { - false => RrCh5en::Disable, - true => RrCh5en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh5en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh5en::Enable - } -} -#[doc = "Field `RR_CH5EN` writer - Channel 5 Input Enable in Trigger Mode"] -pub type RrCh5enW<'a, REG> = crate::BitWriter<'a, REG, RrCh5en>; -impl<'a, REG> RrCh5enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh5en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh5en::Enable) - } -} -#[doc = "Channel 6 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh6en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh6en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH6EN` reader - Channel 6 Input Enable in Trigger Mode"] -pub type RrCh6enR = crate::BitReader; -impl RrCh6enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh6en { - match self.bits { - false => RrCh6en::Disable, - true => RrCh6en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh6en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh6en::Enable - } -} -#[doc = "Field `RR_CH6EN` writer - Channel 6 Input Enable in Trigger Mode"] -pub type RrCh6enW<'a, REG> = crate::BitWriter<'a, REG, RrCh6en>; -impl<'a, REG> RrCh6enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh6en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh6en::Enable) - } -} -#[doc = "Channel 7 Input Enable in Trigger Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh7en { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh7en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH7EN` reader - Channel 7 Input Enable in Trigger Mode"] -pub type RrCh7enR = crate::BitReader; -impl RrCh7enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh7en { - match self.bits { - false => RrCh7en::Disable, - true => RrCh7en::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrCh7en::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrCh7en::Enable - } -} -#[doc = "Field `RR_CH7EN` writer - Channel 7 Input Enable in Trigger Mode"] -pub type RrCh7enW<'a, REG> = crate::BitWriter<'a, REG, RrCh7en>; -impl<'a, REG> RrCh7enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrCh7en::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrCh7en::Enable) - } -} -#[doc = "Fixed Port\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fixp { - #[doc = "0: Fix the plus port. Sweep only the inputs to the minus port."] - FixPlus = 0, - #[doc = "1: Fix the minus port. Sweep only the inputs to the plus port."] - FixMinus = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fixp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIXP` reader - Fixed Port"] -pub type FixpR = crate::BitReader; -impl FixpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fixp { - match self.bits { - false => Fixp::FixPlus, - true => Fixp::FixMinus, - } - } - #[doc = "Fix the plus port. Sweep only the inputs to the minus port."] - #[inline(always)] - pub fn is_fix_plus(&self) -> bool { - *self == Fixp::FixPlus - } - #[doc = "Fix the minus port. Sweep only the inputs to the plus port."] - #[inline(always)] - pub fn is_fix_minus(&self) -> bool { - *self == Fixp::FixMinus - } -} -#[doc = "Field `FIXP` writer - Fixed Port"] -pub type FixpW<'a, REG> = crate::BitWriter<'a, REG, Fixp>; -impl<'a, REG> FixpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fix the plus port. Sweep only the inputs to the minus port."] - #[inline(always)] - pub fn fix_plus(self) -> &'a mut crate::W { - self.variant(Fixp::FixPlus) - } - #[doc = "Fix the minus port. Sweep only the inputs to the plus port."] - #[inline(always)] - pub fn fix_minus(self) -> &'a mut crate::W { - self.variant(Fixp::FixMinus) - } -} -#[doc = "Fixed Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fixch { - #[doc = "0: Channel 0"] - FixCh0 = 0, - #[doc = "1: Channel 1"] - FixCh1 = 1, - #[doc = "2: Channel 2"] - FixCh2 = 2, - #[doc = "3: Channel 3"] - FixCh3 = 3, - #[doc = "4: Channel 4"] - FixCh4 = 4, - #[doc = "5: Channel 5"] - FixCh5 = 5, - #[doc = "6: Channel 6"] - FixCh6 = 6, - #[doc = "7: Channel 7"] - FixCh7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fixch) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fixch { - type Ux = u8; -} -impl crate::IsEnum for Fixch {} -#[doc = "Field `FIXCH` reader - Fixed Channel Select"] -pub type FixchR = crate::FieldReader; -impl FixchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fixch { - match self.bits { - 0 => Fixch::FixCh0, - 1 => Fixch::FixCh1, - 2 => Fixch::FixCh2, - 3 => Fixch::FixCh3, - 4 => Fixch::FixCh4, - 5 => Fixch::FixCh5, - 6 => Fixch::FixCh6, - 7 => Fixch::FixCh7, - _ => unreachable!(), - } - } - #[doc = "Channel 0"] - #[inline(always)] - pub fn is_fix_ch0(&self) -> bool { - *self == Fixch::FixCh0 - } - #[doc = "Channel 1"] - #[inline(always)] - pub fn is_fix_ch1(&self) -> bool { - *self == Fixch::FixCh1 - } - #[doc = "Channel 2"] - #[inline(always)] - pub fn is_fix_ch2(&self) -> bool { - *self == Fixch::FixCh2 - } - #[doc = "Channel 3"] - #[inline(always)] - pub fn is_fix_ch3(&self) -> bool { - *self == Fixch::FixCh3 - } - #[doc = "Channel 4"] - #[inline(always)] - pub fn is_fix_ch4(&self) -> bool { - *self == Fixch::FixCh4 - } - #[doc = "Channel 5"] - #[inline(always)] - pub fn is_fix_ch5(&self) -> bool { - *self == Fixch::FixCh5 - } - #[doc = "Channel 6"] - #[inline(always)] - pub fn is_fix_ch6(&self) -> bool { - *self == Fixch::FixCh6 - } - #[doc = "Channel 7"] - #[inline(always)] - pub fn is_fix_ch7(&self) -> bool { - *self == Fixch::FixCh7 - } -} -#[doc = "Field `FIXCH` writer - Fixed Channel Select"] -pub type FixchW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fixch, crate::Safe>; -impl<'a, REG> FixchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Channel 0"] - #[inline(always)] - pub fn fix_ch0(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh0) - } - #[doc = "Channel 1"] - #[inline(always)] - pub fn fix_ch1(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh1) - } - #[doc = "Channel 2"] - #[inline(always)] - pub fn fix_ch2(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh2) - } - #[doc = "Channel 3"] - #[inline(always)] - pub fn fix_ch3(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh3) - } - #[doc = "Channel 4"] - #[inline(always)] - pub fn fix_ch4(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh4) - } - #[doc = "Channel 5"] - #[inline(always)] - pub fn fix_ch5(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh5) - } - #[doc = "Channel 6"] - #[inline(always)] - pub fn fix_ch6(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh6) - } - #[doc = "Channel 7"] - #[inline(always)] - pub fn fix_ch7(self) -> &'a mut crate::W { - self.variant(Fixch::FixCh7) - } -} -impl R { - #[doc = "Bit 0 - Channel 0 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch0en(&self) -> RrCh0enR { - RrCh0enR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Channel 1 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch1en(&self) -> RrCh1enR { - RrCh1enR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Channel 2 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch2en(&self) -> RrCh2enR { - RrCh2enR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Channel 3 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch3en(&self) -> RrCh3enR { - RrCh3enR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Channel 4 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch4en(&self) -> RrCh4enR { - RrCh4enR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Channel 5 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch5en(&self) -> RrCh5enR { - RrCh5enR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Channel 6 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch6en(&self) -> RrCh6enR { - RrCh6enR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Channel 7 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch7en(&self) -> RrCh7enR { - RrCh7enR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 16 - Fixed Port"] - #[inline(always)] - pub fn fixp(&self) -> FixpR { - FixpR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bits 20:22 - Fixed Channel Select"] - #[inline(always)] - pub fn fixch(&self) -> FixchR { - FixchR::new(((self.bits >> 20) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Channel 0 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch0en(&mut self) -> RrCh0enW { - RrCh0enW::new(self, 0) - } - #[doc = "Bit 1 - Channel 1 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch1en(&mut self) -> RrCh1enW { - RrCh1enW::new(self, 1) - } - #[doc = "Bit 2 - Channel 2 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch2en(&mut self) -> RrCh2enW { - RrCh2enW::new(self, 2) - } - #[doc = "Bit 3 - Channel 3 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch3en(&mut self) -> RrCh3enW { - RrCh3enW::new(self, 3) - } - #[doc = "Bit 4 - Channel 4 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch4en(&mut self) -> RrCh4enW { - RrCh4enW::new(self, 4) - } - #[doc = "Bit 5 - Channel 5 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch5en(&mut self) -> RrCh5enW { - RrCh5enW::new(self, 5) - } - #[doc = "Bit 6 - Channel 6 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch6en(&mut self) -> RrCh6enW { - RrCh6enW::new(self, 6) - } - #[doc = "Bit 7 - Channel 7 Input Enable in Trigger Mode"] - #[inline(always)] - pub fn rr_ch7en(&mut self) -> RrCh7enW { - RrCh7enW::new(self, 7) - } - #[doc = "Bit 16 - Fixed Port"] - #[inline(always)] - pub fn fixp(&mut self) -> FixpW { - FixpW::new(self, 16) - } - #[doc = "Bits 20:22 - Fixed Channel Select"] - #[inline(always)] - pub fn fixch(&mut self) -> FixchW { - FixchW::new(self, 20) - } -} -#[doc = "Round Robin Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Rrcr1Spec; -impl crate::RegisterSpec for Rrcr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rrcr1::R`](R) reader structure"] -impl crate::Readable for Rrcr1Spec {} -#[doc = "`write(|w| ..)` method takes [`rrcr1::W`](W) writer structure"] -impl crate::Writable for Rrcr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RRCR1 to value 0"] -impl crate::Resettable for Rrcr1Spec {} diff --git a/mcxa276-pac/src/cmp0/rrcr2.rs b/mcxa276-pac/src/cmp0/rrcr2.rs deleted file mode 100644 index 3ad05ae0d..000000000 --- a/mcxa276-pac/src/cmp0/rrcr2.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `RRCR2` reader"] -pub type R = crate::R; -#[doc = "Register `RRCR2` writer"] -pub type W = crate::W; -#[doc = "Field `RR_TIMER_RELOAD` reader - Number of Sample Clocks"] -pub type RrTimerReloadR = crate::FieldReader; -#[doc = "Field `RR_TIMER_RELOAD` writer - Number of Sample Clocks"] -pub type RrTimerReloadW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; -#[doc = "Round-Robin Internal Timer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrTimerEn { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrTimerEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_TIMER_EN` reader - Round-Robin Internal Timer Enable"] -pub type RrTimerEnR = crate::BitReader; -impl RrTimerEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrTimerEn { - match self.bits { - false => RrTimerEn::Disable, - true => RrTimerEn::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RrTimerEn::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RrTimerEn::Enable - } -} -#[doc = "Field `RR_TIMER_EN` writer - Round-Robin Internal Timer Enable"] -pub type RrTimerEnW<'a, REG> = crate::BitWriter<'a, REG, RrTimerEn>; -impl<'a, REG> RrTimerEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RrTimerEn::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RrTimerEn::Enable) - } -} -impl R { - #[doc = "Bits 0:27 - Number of Sample Clocks"] - #[inline(always)] - pub fn rr_timer_reload(&self) -> RrTimerReloadR { - RrTimerReloadR::new(self.bits & 0x0fff_ffff) - } - #[doc = "Bit 31 - Round-Robin Internal Timer Enable"] - #[inline(always)] - pub fn rr_timer_en(&self) -> RrTimerEnR { - RrTimerEnR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:27 - Number of Sample Clocks"] - #[inline(always)] - pub fn rr_timer_reload(&mut self) -> RrTimerReloadW { - RrTimerReloadW::new(self, 0) - } - #[doc = "Bit 31 - Round-Robin Internal Timer Enable"] - #[inline(always)] - pub fn rr_timer_en(&mut self) -> RrTimerEnW { - RrTimerEnW::new(self, 31) - } -} -#[doc = "Round Robin Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Rrcr2Spec; -impl crate::RegisterSpec for Rrcr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rrcr2::R`](R) reader structure"] -impl crate::Readable for Rrcr2Spec {} -#[doc = "`write(|w| ..)` method takes [`rrcr2::W`](W) writer structure"] -impl crate::Writable for Rrcr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RRCR2 to value 0"] -impl crate::Resettable for Rrcr2Spec {} diff --git a/mcxa276-pac/src/cmp0/rrcsr.rs b/mcxa276-pac/src/cmp0/rrcsr.rs deleted file mode 100644 index 4fcab1c43..000000000 --- a/mcxa276-pac/src/cmp0/rrcsr.rs +++ /dev/null @@ -1,133 +0,0 @@ -#[doc = "Register `RRCSR` reader"] -pub type R = crate::R; -#[doc = "Register `RRCSR` writer"] -pub type W = crate::W; -#[doc = "Field `RR_CH0OUT` reader - Comparison Result for Channel 0"] -pub type RrCh0outR = crate::BitReader; -#[doc = "Field `RR_CH0OUT` writer - Comparison Result for Channel 0"] -pub type RrCh0outW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RR_CH1OUT` reader - Comparison Result for Channel 1"] -pub type RrCh1outR = crate::BitReader; -#[doc = "Field `RR_CH1OUT` writer - Comparison Result for Channel 1"] -pub type RrCh1outW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RR_CH2OUT` reader - Comparison Result for Channel 2"] -pub type RrCh2outR = crate::BitReader; -#[doc = "Field `RR_CH2OUT` writer - Comparison Result for Channel 2"] -pub type RrCh2outW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RR_CH3OUT` reader - Comparison Result for Channel 3"] -pub type RrCh3outR = crate::BitReader; -#[doc = "Field `RR_CH3OUT` writer - Comparison Result for Channel 3"] -pub type RrCh3outW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RR_CH4OUT` reader - Comparison Result for Channel 4"] -pub type RrCh4outR = crate::BitReader; -#[doc = "Field `RR_CH4OUT` writer - Comparison Result for Channel 4"] -pub type RrCh4outW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RR_CH5OUT` reader - Comparison Result for Channel 5"] -pub type RrCh5outR = crate::BitReader; -#[doc = "Field `RR_CH5OUT` writer - Comparison Result for Channel 5"] -pub type RrCh5outW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RR_CH6OUT` reader - Comparison Result for Channel 6"] -pub type RrCh6outR = crate::BitReader; -#[doc = "Field `RR_CH6OUT` writer - Comparison Result for Channel 6"] -pub type RrCh6outW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RR_CH7OUT` reader - Comparison Result for Channel 7"] -pub type RrCh7outR = crate::BitReader; -#[doc = "Field `RR_CH7OUT` writer - Comparison Result for Channel 7"] -pub type RrCh7outW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Comparison Result for Channel 0"] - #[inline(always)] - pub fn rr_ch0out(&self) -> RrCh0outR { - RrCh0outR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Comparison Result for Channel 1"] - #[inline(always)] - pub fn rr_ch1out(&self) -> RrCh1outR { - RrCh1outR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Comparison Result for Channel 2"] - #[inline(always)] - pub fn rr_ch2out(&self) -> RrCh2outR { - RrCh2outR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Comparison Result for Channel 3"] - #[inline(always)] - pub fn rr_ch3out(&self) -> RrCh3outR { - RrCh3outR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Comparison Result for Channel 4"] - #[inline(always)] - pub fn rr_ch4out(&self) -> RrCh4outR { - RrCh4outR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Comparison Result for Channel 5"] - #[inline(always)] - pub fn rr_ch5out(&self) -> RrCh5outR { - RrCh5outR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Comparison Result for Channel 6"] - #[inline(always)] - pub fn rr_ch6out(&self) -> RrCh6outR { - RrCh6outR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Comparison Result for Channel 7"] - #[inline(always)] - pub fn rr_ch7out(&self) -> RrCh7outR { - RrCh7outR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Comparison Result for Channel 0"] - #[inline(always)] - pub fn rr_ch0out(&mut self) -> RrCh0outW { - RrCh0outW::new(self, 0) - } - #[doc = "Bit 1 - Comparison Result for Channel 1"] - #[inline(always)] - pub fn rr_ch1out(&mut self) -> RrCh1outW { - RrCh1outW::new(self, 1) - } - #[doc = "Bit 2 - Comparison Result for Channel 2"] - #[inline(always)] - pub fn rr_ch2out(&mut self) -> RrCh2outW { - RrCh2outW::new(self, 2) - } - #[doc = "Bit 3 - Comparison Result for Channel 3"] - #[inline(always)] - pub fn rr_ch3out(&mut self) -> RrCh3outW { - RrCh3outW::new(self, 3) - } - #[doc = "Bit 4 - Comparison Result for Channel 4"] - #[inline(always)] - pub fn rr_ch4out(&mut self) -> RrCh4outW { - RrCh4outW::new(self, 4) - } - #[doc = "Bit 5 - Comparison Result for Channel 5"] - #[inline(always)] - pub fn rr_ch5out(&mut self) -> RrCh5outW { - RrCh5outW::new(self, 5) - } - #[doc = "Bit 6 - Comparison Result for Channel 6"] - #[inline(always)] - pub fn rr_ch6out(&mut self) -> RrCh6outW { - RrCh6outW::new(self, 6) - } - #[doc = "Bit 7 - Comparison Result for Channel 7"] - #[inline(always)] - pub fn rr_ch7out(&mut self) -> RrCh7outW { - RrCh7outW::new(self, 7) - } -} -#[doc = "Round Robin Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RrcsrSpec; -impl crate::RegisterSpec for RrcsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rrcsr::R`](R) reader structure"] -impl crate::Readable for RrcsrSpec {} -#[doc = "`write(|w| ..)` method takes [`rrcsr::W`](W) writer structure"] -impl crate::Writable for RrcsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RRCSR to value 0"] -impl crate::Resettable for RrcsrSpec {} diff --git a/mcxa276-pac/src/cmp0/rrsr.rs b/mcxa276-pac/src/cmp0/rrsr.rs deleted file mode 100644 index 995a7a59f..000000000 --- a/mcxa276-pac/src/cmp0/rrsr.rs +++ /dev/null @@ -1,526 +0,0 @@ -#[doc = "Register `RRSR` reader"] -pub type R = crate::R; -#[doc = "Register `RRSR` writer"] -pub type W = crate::W; -#[doc = "Channel 0 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh0f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh0f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH0F` reader - Channel 0 Input Changed Flag"] -pub type RrCh0fR = crate::BitReader; -impl RrCh0fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh0f { - match self.bits { - false => RrCh0f::NotDifferent, - true => RrCh0f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh0f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh0f::Different - } -} -#[doc = "Field `RR_CH0F` writer - Channel 0 Input Changed Flag"] -pub type RrCh0fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh0f>; -impl<'a, REG> RrCh0fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh0f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh0f::Different) - } -} -#[doc = "Channel 1 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh1f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh1f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH1F` reader - Channel 1 Input Changed Flag"] -pub type RrCh1fR = crate::BitReader; -impl RrCh1fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh1f { - match self.bits { - false => RrCh1f::NotDifferent, - true => RrCh1f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh1f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh1f::Different - } -} -#[doc = "Field `RR_CH1F` writer - Channel 1 Input Changed Flag"] -pub type RrCh1fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh1f>; -impl<'a, REG> RrCh1fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh1f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh1f::Different) - } -} -#[doc = "Channel 2 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh2f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh2f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH2F` reader - Channel 2 Input Changed Flag"] -pub type RrCh2fR = crate::BitReader; -impl RrCh2fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh2f { - match self.bits { - false => RrCh2f::NotDifferent, - true => RrCh2f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh2f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh2f::Different - } -} -#[doc = "Field `RR_CH2F` writer - Channel 2 Input Changed Flag"] -pub type RrCh2fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh2f>; -impl<'a, REG> RrCh2fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh2f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh2f::Different) - } -} -#[doc = "Channel 3 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh3f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh3f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH3F` reader - Channel 3 Input Changed Flag"] -pub type RrCh3fR = crate::BitReader; -impl RrCh3fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh3f { - match self.bits { - false => RrCh3f::NotDifferent, - true => RrCh3f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh3f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh3f::Different - } -} -#[doc = "Field `RR_CH3F` writer - Channel 3 Input Changed Flag"] -pub type RrCh3fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh3f>; -impl<'a, REG> RrCh3fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh3f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh3f::Different) - } -} -#[doc = "Channel 4 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh4f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh4f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH4F` reader - Channel 4 Input Changed Flag"] -pub type RrCh4fR = crate::BitReader; -impl RrCh4fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh4f { - match self.bits { - false => RrCh4f::NotDifferent, - true => RrCh4f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh4f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh4f::Different - } -} -#[doc = "Field `RR_CH4F` writer - Channel 4 Input Changed Flag"] -pub type RrCh4fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh4f>; -impl<'a, REG> RrCh4fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh4f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh4f::Different) - } -} -#[doc = "Channel 5 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh5f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh5f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH5F` reader - Channel 5 Input Changed Flag"] -pub type RrCh5fR = crate::BitReader; -impl RrCh5fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh5f { - match self.bits { - false => RrCh5f::NotDifferent, - true => RrCh5f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh5f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh5f::Different - } -} -#[doc = "Field `RR_CH5F` writer - Channel 5 Input Changed Flag"] -pub type RrCh5fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh5f>; -impl<'a, REG> RrCh5fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh5f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh5f::Different) - } -} -#[doc = "Channel 6 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh6f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh6f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH6F` reader - Channel 6 Input Changed Flag"] -pub type RrCh6fR = crate::BitReader; -impl RrCh6fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh6f { - match self.bits { - false => RrCh6f::NotDifferent, - true => RrCh6f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh6f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh6f::Different - } -} -#[doc = "Field `RR_CH6F` writer - Channel 6 Input Changed Flag"] -pub type RrCh6fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh6f>; -impl<'a, REG> RrCh6fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh6f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh6f::Different) - } -} -#[doc = "Channel 7 Input Changed Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RrCh7f { - #[doc = "0: No different"] - NotDifferent = 0, - #[doc = "1: Different"] - Different = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RrCh7f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RR_CH7F` reader - Channel 7 Input Changed Flag"] -pub type RrCh7fR = crate::BitReader; -impl RrCh7fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RrCh7f { - match self.bits { - false => RrCh7f::NotDifferent, - true => RrCh7f::Different, - } - } - #[doc = "No different"] - #[inline(always)] - pub fn is_not_different(&self) -> bool { - *self == RrCh7f::NotDifferent - } - #[doc = "Different"] - #[inline(always)] - pub fn is_different(&self) -> bool { - *self == RrCh7f::Different - } -} -#[doc = "Field `RR_CH7F` writer - Channel 7 Input Changed Flag"] -pub type RrCh7fW<'a, REG> = crate::BitWriter1C<'a, REG, RrCh7f>; -impl<'a, REG> RrCh7fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No different"] - #[inline(always)] - pub fn not_different(self) -> &'a mut crate::W { - self.variant(RrCh7f::NotDifferent) - } - #[doc = "Different"] - #[inline(always)] - pub fn different(self) -> &'a mut crate::W { - self.variant(RrCh7f::Different) - } -} -impl R { - #[doc = "Bit 0 - Channel 0 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch0f(&self) -> RrCh0fR { - RrCh0fR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Channel 1 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch1f(&self) -> RrCh1fR { - RrCh1fR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Channel 2 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch2f(&self) -> RrCh2fR { - RrCh2fR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Channel 3 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch3f(&self) -> RrCh3fR { - RrCh3fR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Channel 4 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch4f(&self) -> RrCh4fR { - RrCh4fR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Channel 5 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch5f(&self) -> RrCh5fR { - RrCh5fR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Channel 6 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch6f(&self) -> RrCh6fR { - RrCh6fR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Channel 7 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch7f(&self) -> RrCh7fR { - RrCh7fR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Channel 0 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch0f(&mut self) -> RrCh0fW { - RrCh0fW::new(self, 0) - } - #[doc = "Bit 1 - Channel 1 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch1f(&mut self) -> RrCh1fW { - RrCh1fW::new(self, 1) - } - #[doc = "Bit 2 - Channel 2 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch2f(&mut self) -> RrCh2fW { - RrCh2fW::new(self, 2) - } - #[doc = "Bit 3 - Channel 3 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch3f(&mut self) -> RrCh3fW { - RrCh3fW::new(self, 3) - } - #[doc = "Bit 4 - Channel 4 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch4f(&mut self) -> RrCh4fW { - RrCh4fW::new(self, 4) - } - #[doc = "Bit 5 - Channel 5 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch5f(&mut self) -> RrCh5fW { - RrCh5fW::new(self, 5) - } - #[doc = "Bit 6 - Channel 6 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch6f(&mut self) -> RrCh6fW { - RrCh6fW::new(self, 6) - } - #[doc = "Bit 7 - Channel 7 Input Changed Flag"] - #[inline(always)] - pub fn rr_ch7f(&mut self) -> RrCh7fW { - RrCh7fW::new(self, 7) - } -} -#[doc = "Round Robin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rrsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RrsrSpec; -impl crate::RegisterSpec for RrsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rrsr::R`](R) reader structure"] -impl crate::Readable for RrsrSpec {} -#[doc = "`write(|w| ..)` method takes [`rrsr::W`](W) writer structure"] -impl crate::Writable for RrsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; -} -#[doc = "`reset()` method sets RRSR to value 0"] -impl crate::Resettable for RrsrSpec {} diff --git a/mcxa276-pac/src/cmp0/verid.rs b/mcxa276-pac/src/cmp0/verid.rs deleted file mode 100644 index ed1c0af21..000000000 --- a/mcxa276-pac/src/cmp0/verid.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "1: Round robin feature"] - RoundRobin = 1, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Feature::RoundRobin), - _ => None, - } - } - #[doc = "Round robin feature"] - #[inline(always)] - pub fn is_round_robin(&self) -> bool { - *self == Feature::RoundRobin - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0100_0001"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0100_0001; -} diff --git a/mcxa276-pac/src/crc0.rs b/mcxa276-pac/src/crc0.rs deleted file mode 100644 index 87c4e88a2..000000000 --- a/mcxa276-pac/src/crc0.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - data: Data, - gpoly: Gpoly, - ctrl: Ctrl, -} -impl RegisterBlock { - #[doc = "0x00 - Data"] - #[inline(always)] - pub const fn data(&self) -> &Data { - &self.data - } - #[doc = "0x04 - Polynomial"] - #[inline(always)] - pub const fn gpoly(&self) -> &Gpoly { - &self.gpoly - } - #[doc = "0x08 - Control"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } -} -#[doc = "DATA (rw) register accessor: Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] -#[doc(alias = "DATA")] -pub type Data = crate::Reg; -#[doc = "Data"] -pub mod data; -#[doc = "GPOLY (rw) register accessor: Polynomial\n\nYou can [`read`](crate::Reg::read) this register and get [`gpoly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpoly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpoly`] module"] -#[doc(alias = "GPOLY")] -pub type Gpoly = crate::Reg; -#[doc = "Polynomial"] -pub mod gpoly; -#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "Control"] -pub mod ctrl; diff --git a/mcxa276-pac/src/crc0/ctrl.rs b/mcxa276-pac/src/crc0/ctrl.rs deleted file mode 100644 index f83243b2f..000000000 --- a/mcxa276-pac/src/crc0/ctrl.rs +++ /dev/null @@ -1,402 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "TCRC\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tcrc { - #[doc = "0: 16 bits"] - B16 = 0, - #[doc = "1: 32 bits"] - B32 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tcrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCRC` reader - TCRC"] -pub type TcrcR = crate::BitReader; -impl TcrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcrc { - match self.bits { - false => Tcrc::B16, - true => Tcrc::B32, - } - } - #[doc = "16 bits"] - #[inline(always)] - pub fn is_b16(&self) -> bool { - *self == Tcrc::B16 - } - #[doc = "32 bits"] - #[inline(always)] - pub fn is_b32(&self) -> bool { - *self == Tcrc::B32 - } -} -#[doc = "Field `TCRC` writer - TCRC"] -pub type TcrcW<'a, REG> = crate::BitWriter<'a, REG, Tcrc>; -impl<'a, REG> TcrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "16 bits"] - #[inline(always)] - pub fn b16(self) -> &'a mut crate::W { - self.variant(Tcrc::B16) - } - #[doc = "32 bits"] - #[inline(always)] - pub fn b32(self) -> &'a mut crate::W { - self.variant(Tcrc::B32) - } -} -#[doc = "Write as Seed\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Was { - #[doc = "0: Data values"] - Data = 0, - #[doc = "1: Seed values"] - Seed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Was) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAS` reader - Write as Seed"] -pub type WasR = crate::BitReader; -impl WasR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Was { - match self.bits { - false => Was::Data, - true => Was::Seed, - } - } - #[doc = "Data values"] - #[inline(always)] - pub fn is_data(&self) -> bool { - *self == Was::Data - } - #[doc = "Seed values"] - #[inline(always)] - pub fn is_seed(&self) -> bool { - *self == Was::Seed - } -} -#[doc = "Field `WAS` writer - Write as Seed"] -pub type WasW<'a, REG> = crate::BitWriter<'a, REG, Was>; -impl<'a, REG> WasW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Data values"] - #[inline(always)] - pub fn data(self) -> &'a mut crate::W { - self.variant(Was::Data) - } - #[doc = "Seed values"] - #[inline(always)] - pub fn seed(self) -> &'a mut crate::W { - self.variant(Was::Seed) - } -} -#[doc = "Complement Read of CRC Data Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fxor { - #[doc = "0: Disables XOR on reading data."] - Noxor = 0, - #[doc = "1: Inverts or complements the read value of the CRC Data."] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fxor) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FXOR` reader - Complement Read of CRC Data Register"] -pub type FxorR = crate::BitReader; -impl FxorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fxor { - match self.bits { - false => Fxor::Noxor, - true => Fxor::Invert, - } - } - #[doc = "Disables XOR on reading data."] - #[inline(always)] - pub fn is_noxor(&self) -> bool { - *self == Fxor::Noxor - } - #[doc = "Inverts or complements the read value of the CRC Data."] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == Fxor::Invert - } -} -#[doc = "Field `FXOR` writer - Complement Read of CRC Data Register"] -pub type FxorW<'a, REG> = crate::BitWriter<'a, REG, Fxor>; -impl<'a, REG> FxorW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables XOR on reading data."] - #[inline(always)] - pub fn noxor(self) -> &'a mut crate::W { - self.variant(Fxor::Noxor) - } - #[doc = "Inverts or complements the read value of the CRC Data."] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(Fxor::Invert) - } -} -#[doc = "Transpose Type for Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Totr { - #[doc = "0: No transposition"] - Notrnps = 0, - #[doc = "1: Bits in bytes are transposed, but bytes are not transposed."] - BtsTrnps = 1, - #[doc = "2: Both bits in bytes and bytes are transposed."] - BytsBtsTrnps = 2, - #[doc = "3: Only bytes are transposed, no bits in a byte are transposed."] - BytsTrnps = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Totr) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Totr { - type Ux = u8; -} -impl crate::IsEnum for Totr {} -#[doc = "Field `TOTR` reader - Transpose Type for Read"] -pub type TotrR = crate::FieldReader; -impl TotrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Totr { - match self.bits { - 0 => Totr::Notrnps, - 1 => Totr::BtsTrnps, - 2 => Totr::BytsBtsTrnps, - 3 => Totr::BytsTrnps, - _ => unreachable!(), - } - } - #[doc = "No transposition"] - #[inline(always)] - pub fn is_notrnps(&self) -> bool { - *self == Totr::Notrnps - } - #[doc = "Bits in bytes are transposed, but bytes are not transposed."] - #[inline(always)] - pub fn is_bts_trnps(&self) -> bool { - *self == Totr::BtsTrnps - } - #[doc = "Both bits in bytes and bytes are transposed."] - #[inline(always)] - pub fn is_byts_bts_trnps(&self) -> bool { - *self == Totr::BytsBtsTrnps - } - #[doc = "Only bytes are transposed, no bits in a byte are transposed."] - #[inline(always)] - pub fn is_byts_trnps(&self) -> bool { - *self == Totr::BytsTrnps - } -} -#[doc = "Field `TOTR` writer - Transpose Type for Read"] -pub type TotrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Totr, crate::Safe>; -impl<'a, REG> TotrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No transposition"] - #[inline(always)] - pub fn notrnps(self) -> &'a mut crate::W { - self.variant(Totr::Notrnps) - } - #[doc = "Bits in bytes are transposed, but bytes are not transposed."] - #[inline(always)] - pub fn bts_trnps(self) -> &'a mut crate::W { - self.variant(Totr::BtsTrnps) - } - #[doc = "Both bits in bytes and bytes are transposed."] - #[inline(always)] - pub fn byts_bts_trnps(self) -> &'a mut crate::W { - self.variant(Totr::BytsBtsTrnps) - } - #[doc = "Only bytes are transposed, no bits in a byte are transposed."] - #[inline(always)] - pub fn byts_trnps(self) -> &'a mut crate::W { - self.variant(Totr::BytsTrnps) - } -} -#[doc = "Transpose Type for Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tot { - #[doc = "0: No transposition"] - Notrnps = 0, - #[doc = "1: Bits in bytes are transposed, but bytes are not transposed."] - BtsTrnps = 1, - #[doc = "2: Both bits in bytes and bytes are transposed."] - BytsBtsTrnps = 2, - #[doc = "3: Only bytes are transposed, no bits in a byte are transposed."] - BytsTrnps = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tot) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tot { - type Ux = u8; -} -impl crate::IsEnum for Tot {} -#[doc = "Field `TOT` reader - Transpose Type for Write"] -pub type TotR = crate::FieldReader; -impl TotR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tot { - match self.bits { - 0 => Tot::Notrnps, - 1 => Tot::BtsTrnps, - 2 => Tot::BytsBtsTrnps, - 3 => Tot::BytsTrnps, - _ => unreachable!(), - } - } - #[doc = "No transposition"] - #[inline(always)] - pub fn is_notrnps(&self) -> bool { - *self == Tot::Notrnps - } - #[doc = "Bits in bytes are transposed, but bytes are not transposed."] - #[inline(always)] - pub fn is_bts_trnps(&self) -> bool { - *self == Tot::BtsTrnps - } - #[doc = "Both bits in bytes and bytes are transposed."] - #[inline(always)] - pub fn is_byts_bts_trnps(&self) -> bool { - *self == Tot::BytsBtsTrnps - } - #[doc = "Only bytes are transposed, no bits in a byte are transposed."] - #[inline(always)] - pub fn is_byts_trnps(&self) -> bool { - *self == Tot::BytsTrnps - } -} -#[doc = "Field `TOT` writer - Transpose Type for Write"] -pub type TotW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tot, crate::Safe>; -impl<'a, REG> TotW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No transposition"] - #[inline(always)] - pub fn notrnps(self) -> &'a mut crate::W { - self.variant(Tot::Notrnps) - } - #[doc = "Bits in bytes are transposed, but bytes are not transposed."] - #[inline(always)] - pub fn bts_trnps(self) -> &'a mut crate::W { - self.variant(Tot::BtsTrnps) - } - #[doc = "Both bits in bytes and bytes are transposed."] - #[inline(always)] - pub fn byts_bts_trnps(self) -> &'a mut crate::W { - self.variant(Tot::BytsBtsTrnps) - } - #[doc = "Only bytes are transposed, no bits in a byte are transposed."] - #[inline(always)] - pub fn byts_trnps(self) -> &'a mut crate::W { - self.variant(Tot::BytsTrnps) - } -} -impl R { - #[doc = "Bit 24 - TCRC"] - #[inline(always)] - pub fn tcrc(&self) -> TcrcR { - TcrcR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Write as Seed"] - #[inline(always)] - pub fn was(&self) -> WasR { - WasR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Complement Read of CRC Data Register"] - #[inline(always)] - pub fn fxor(&self) -> FxorR { - FxorR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bits 28:29 - Transpose Type for Read"] - #[inline(always)] - pub fn totr(&self) -> TotrR { - TotrR::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bits 30:31 - Transpose Type for Write"] - #[inline(always)] - pub fn tot(&self) -> TotR { - TotR::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bit 24 - TCRC"] - #[inline(always)] - pub fn tcrc(&mut self) -> TcrcW { - TcrcW::new(self, 24) - } - #[doc = "Bit 25 - Write as Seed"] - #[inline(always)] - pub fn was(&mut self) -> WasW { - WasW::new(self, 25) - } - #[doc = "Bit 26 - Complement Read of CRC Data Register"] - #[inline(always)] - pub fn fxor(&mut self) -> FxorW { - FxorW::new(self, 26) - } - #[doc = "Bits 28:29 - Transpose Type for Read"] - #[inline(always)] - pub fn totr(&mut self) -> TotrW { - TotrW::new(self, 28) - } - #[doc = "Bits 30:31 - Transpose Type for Write"] - #[inline(always)] - pub fn tot(&mut self) -> TotW { - TotW::new(self, 30) - } -} -#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/crc0/data.rs b/mcxa276-pac/src/crc0/data.rs deleted file mode 100644 index 4240630f1..000000000 --- a/mcxa276-pac/src/crc0/data.rs +++ /dev/null @@ -1,79 +0,0 @@ -#[doc = "Register `DATA` reader"] -pub type R = crate::R; -#[doc = "Register `DATA` writer"] -pub type W = crate::W; -#[doc = "Field `LL` reader - Lower Part of Low Byte"] -pub type LlR = crate::FieldReader; -#[doc = "Field `LL` writer - Lower Part of Low Byte"] -pub type LlW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `LU` reader - Upper Part of Low Byte"] -pub type LuR = crate::FieldReader; -#[doc = "Field `LU` writer - Upper Part of Low Byte"] -pub type LuW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `HL` reader - Lower Part of High Byte"] -pub type HlR = crate::FieldReader; -#[doc = "Field `HL` writer - Lower Part of High Byte"] -pub type HlW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `HU` reader - Upper Part of High Byte"] -pub type HuR = crate::FieldReader; -#[doc = "Field `HU` writer - Upper Part of High Byte"] -pub type HuW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Lower Part of Low Byte"] - #[inline(always)] - pub fn ll(&self) -> LlR { - LlR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Upper Part of Low Byte"] - #[inline(always)] - pub fn lu(&self) -> LuR { - LuR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Lower Part of High Byte"] - #[inline(always)] - pub fn hl(&self) -> HlR { - HlR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Upper Part of High Byte"] - #[inline(always)] - pub fn hu(&self) -> HuR { - HuR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Lower Part of Low Byte"] - #[inline(always)] - pub fn ll(&mut self) -> LlW { - LlW::new(self, 0) - } - #[doc = "Bits 8:15 - Upper Part of Low Byte"] - #[inline(always)] - pub fn lu(&mut self) -> LuW { - LuW::new(self, 8) - } - #[doc = "Bits 16:23 - Lower Part of High Byte"] - #[inline(always)] - pub fn hl(&mut self) -> HlW { - HlW::new(self, 16) - } - #[doc = "Bits 24:31 - Upper Part of High Byte"] - #[inline(always)] - pub fn hu(&mut self) -> HuW { - HuW::new(self, 24) - } -} -#[doc = "Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DataSpec; -impl crate::RegisterSpec for DataSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`data::R`](R) reader structure"] -impl crate::Readable for DataSpec {} -#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] -impl crate::Writable for DataSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DATA to value 0xffff_ffff"] -impl crate::Resettable for DataSpec { - const RESET_VALUE: u32 = 0xffff_ffff; -} diff --git a/mcxa276-pac/src/crc0/gpoly.rs b/mcxa276-pac/src/crc0/gpoly.rs deleted file mode 100644 index 8ae5e16f0..000000000 --- a/mcxa276-pac/src/crc0/gpoly.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `GPOLY` reader"] -pub type R = crate::R; -#[doc = "Register `GPOLY` writer"] -pub type W = crate::W; -#[doc = "Field `LOW` reader - Low Half-Word"] -pub type LowR = crate::FieldReader; -#[doc = "Field `LOW` writer - Low Half-Word"] -pub type LowW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `HIGH` reader - High Half-Word"] -pub type HighR = crate::FieldReader; -#[doc = "Field `HIGH` writer - High Half-Word"] -pub type HighW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Low Half-Word"] - #[inline(always)] - pub fn low(&self) -> LowR { - LowR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - High Half-Word"] - #[inline(always)] - pub fn high(&self) -> HighR { - HighR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Low Half-Word"] - #[inline(always)] - pub fn low(&mut self) -> LowW { - LowW::new(self, 0) - } - #[doc = "Bits 16:31 - High Half-Word"] - #[inline(always)] - pub fn high(&mut self) -> HighW { - HighW::new(self, 16) - } -} -#[doc = "Polynomial\n\nYou can [`read`](crate::Reg::read) this register and get [`gpoly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpoly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpolySpec; -impl crate::RegisterSpec for GpolySpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpoly::R`](R) reader structure"] -impl crate::Readable for GpolySpec {} -#[doc = "`write(|w| ..)` method takes [`gpoly::W`](W) writer structure"] -impl crate::Writable for GpolySpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPOLY to value 0x1021"] -impl crate::Resettable for GpolySpec { - const RESET_VALUE: u32 = 0x1021; -} diff --git a/mcxa276-pac/src/ctimer0.rs b/mcxa276-pac/src/ctimer0.rs deleted file mode 100644 index 07cf09412..000000000 --- a/mcxa276-pac/src/ctimer0.rs +++ /dev/null @@ -1,168 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - ir: Ir, - tcr: Tcr, - tc: Tc, - pr: Pr, - pc: Pc, - mcr: Mcr, - mr: [Mr; 4], - ccr: Ccr, - cr: [Cr; 4], - emr: Emr, - _reserved10: [u8; 0x30], - ctcr: Ctcr, - pwmc: Pwmc, - msr: [Msr; 4], -} -impl RegisterBlock { - #[doc = "0x00 - Interrupt"] - #[inline(always)] - pub const fn ir(&self) -> &Ir { - &self.ir - } - #[doc = "0x04 - Timer Control"] - #[inline(always)] - pub const fn tcr(&self) -> &Tcr { - &self.tcr - } - #[doc = "0x08 - Timer Counter"] - #[inline(always)] - pub const fn tc(&self) -> &Tc { - &self.tc - } - #[doc = "0x0c - Prescale"] - #[inline(always)] - pub const fn pr(&self) -> &Pr { - &self.pr - } - #[doc = "0x10 - Prescale Counter"] - #[inline(always)] - pub const fn pc(&self) -> &Pc { - &self.pc - } - #[doc = "0x14 - Match Control"] - #[inline(always)] - pub const fn mcr(&self) -> &Mcr { - &self.mcr - } - #[doc = "0x18..0x28 - Match"] - #[inline(always)] - pub const fn mr(&self, n: usize) -> &Mr { - &self.mr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x18..0x28 - Match"] - #[inline(always)] - pub fn mr_iter(&self) -> impl Iterator { - self.mr.iter() - } - #[doc = "0x28 - Capture Control"] - #[inline(always)] - pub const fn ccr(&self) -> &Ccr { - &self.ccr - } - #[doc = "0x2c..0x3c - Capture"] - #[inline(always)] - pub const fn cr(&self, n: usize) -> &Cr { - &self.cr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x2c..0x3c - Capture"] - #[inline(always)] - pub fn cr_iter(&self) -> impl Iterator { - self.cr.iter() - } - #[doc = "0x3c - External Match"] - #[inline(always)] - pub const fn emr(&self) -> &Emr { - &self.emr - } - #[doc = "0x70 - Count Control"] - #[inline(always)] - pub const fn ctcr(&self) -> &Ctcr { - &self.ctcr - } - #[doc = "0x74 - PWM Control"] - #[inline(always)] - pub const fn pwmc(&self) -> &Pwmc { - &self.pwmc - } - #[doc = "0x78..0x88 - Match Shadow"] - #[inline(always)] - pub const fn msr(&self, n: usize) -> &Msr { - &self.msr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x78..0x88 - Match Shadow"] - #[inline(always)] - pub fn msr_iter(&self) -> impl Iterator { - self.msr.iter() - } -} -#[doc = "IR (rw) register accessor: Interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`] module"] -#[doc(alias = "IR")] -pub type Ir = crate::Reg; -#[doc = "Interrupt"] -pub mod ir; -#[doc = "TCR (rw) register accessor: Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] -#[doc(alias = "TCR")] -pub type Tcr = crate::Reg; -#[doc = "Timer Control"] -pub mod tcr; -#[doc = "TC (rw) register accessor: Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] module"] -#[doc(alias = "TC")] -pub type Tc = crate::Reg; -#[doc = "Timer Counter"] -pub mod tc; -#[doc = "PR (rw) register accessor: Prescale\n\nYou can [`read`](crate::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`] module"] -#[doc(alias = "PR")] -pub type Pr = crate::Reg; -#[doc = "Prescale"] -pub mod pr; -#[doc = "PC (rw) register accessor: Prescale Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`] module"] -#[doc(alias = "PC")] -pub type Pc = crate::Reg; -#[doc = "Prescale Counter"] -pub mod pc; -#[doc = "MCR (rw) register accessor: Match Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] -#[doc(alias = "MCR")] -pub type Mcr = crate::Reg; -#[doc = "Match Control"] -pub mod mcr; -#[doc = "MR (rw) register accessor: Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`] module"] -#[doc(alias = "MR")] -pub type Mr = crate::Reg; -#[doc = "Match"] -pub mod mr; -#[doc = "CCR (rw) register accessor: Capture Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`] module"] -#[doc(alias = "CCR")] -pub type Ccr = crate::Reg; -#[doc = "Capture Control"] -pub mod ccr; -#[doc = "CR (r) register accessor: Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] -#[doc(alias = "CR")] -pub type Cr = crate::Reg; -#[doc = "Capture"] -pub mod cr; -#[doc = "EMR (rw) register accessor: External Match\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`] module"] -#[doc(alias = "EMR")] -pub type Emr = crate::Reg; -#[doc = "External Match"] -pub mod emr; -#[doc = "CTCR (rw) register accessor: Count Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`] module"] -#[doc(alias = "CTCR")] -pub type Ctcr = crate::Reg; -#[doc = "Count Control"] -pub mod ctcr; -#[doc = "PWMC (rw) register accessor: PWM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`] module"] -#[doc(alias = "PWMC")] -pub type Pwmc = crate::Reg; -#[doc = "PWM Control"] -pub mod pwmc; -#[doc = "MSR (rw) register accessor: Match Shadow\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] -#[doc(alias = "MSR")] -pub type Msr = crate::Reg; -#[doc = "Match Shadow"] -pub mod msr; diff --git a/mcxa276-pac/src/ctimer0/ccr.rs b/mcxa276-pac/src/ctimer0/ccr.rs deleted file mode 100644 index cddce8dee..000000000 --- a/mcxa276-pac/src/ctimer0/ccr.rs +++ /dev/null @@ -1,777 +0,0 @@ -#[doc = "Register `CCR` reader"] -pub type R = crate::R; -#[doc = "Register `CCR` writer"] -pub type W = crate::W; -#[doc = "Rising Edge of Capture Channel 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap0re { - #[doc = "0: Does not load"] - Cap0re0 = 0, - #[doc = "1: Loads"] - Capore1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap0re) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP0RE` reader - Rising Edge of Capture Channel 0"] -pub type Cap0reR = crate::BitReader; -impl Cap0reR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap0re { - match self.bits { - false => Cap0re::Cap0re0, - true => Cap0re::Capore1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap0re_0(&self) -> bool { - *self == Cap0re::Cap0re0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_capore_1(&self) -> bool { - *self == Cap0re::Capore1 - } -} -#[doc = "Field `CAP0RE` writer - Rising Edge of Capture Channel 0"] -pub type Cap0reW<'a, REG> = crate::BitWriter<'a, REG, Cap0re>; -impl<'a, REG> Cap0reW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap0re_0(self) -> &'a mut crate::W { - self.variant(Cap0re::Cap0re0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn capore_1(self) -> &'a mut crate::W { - self.variant(Cap0re::Capore1) - } -} -#[doc = "Falling Edge of Capture Channel 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap0fe { - #[doc = "0: Does not load"] - Cap0fe0 = 0, - #[doc = "1: Loads"] - Capofe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap0fe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP0FE` reader - Falling Edge of Capture Channel 0"] -pub type Cap0feR = crate::BitReader; -impl Cap0feR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap0fe { - match self.bits { - false => Cap0fe::Cap0fe0, - true => Cap0fe::Capofe1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap0fe_0(&self) -> bool { - *self == Cap0fe::Cap0fe0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_capofe_1(&self) -> bool { - *self == Cap0fe::Capofe1 - } -} -#[doc = "Field `CAP0FE` writer - Falling Edge of Capture Channel 0"] -pub type Cap0feW<'a, REG> = crate::BitWriter<'a, REG, Cap0fe>; -impl<'a, REG> Cap0feW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap0fe_0(self) -> &'a mut crate::W { - self.variant(Cap0fe::Cap0fe0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn capofe_1(self) -> &'a mut crate::W { - self.variant(Cap0fe::Capofe1) - } -} -#[doc = "Generate Interrupt on Channel 0 Capture Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap0i { - #[doc = "0: Does not generate"] - Cap0i0 = 0, - #[doc = "1: Generates"] - Capoi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap0i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP0I` reader - Generate Interrupt on Channel 0 Capture Event"] -pub type Cap0iR = crate::BitReader; -impl Cap0iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap0i { - match self.bits { - false => Cap0i::Cap0i0, - true => Cap0i::Capoi1, - } - } - #[doc = "Does not generate"] - #[inline(always)] - pub fn is_cap0i_0(&self) -> bool { - *self == Cap0i::Cap0i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_capoi_1(&self) -> bool { - *self == Cap0i::Capoi1 - } -} -#[doc = "Field `CAP0I` writer - Generate Interrupt on Channel 0 Capture Event"] -pub type Cap0iW<'a, REG> = crate::BitWriter<'a, REG, Cap0i>; -impl<'a, REG> Cap0iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generate"] - #[inline(always)] - pub fn cap0i_0(self) -> &'a mut crate::W { - self.variant(Cap0i::Cap0i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn capoi_1(self) -> &'a mut crate::W { - self.variant(Cap0i::Capoi1) - } -} -#[doc = "Rising Edge of Capture Channel 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap1re { - #[doc = "0: Does not load"] - Cap1re0 = 0, - #[doc = "1: Loads"] - Cap1re1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap1re) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP1RE` reader - Rising Edge of Capture Channel 1"] -pub type Cap1reR = crate::BitReader; -impl Cap1reR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap1re { - match self.bits { - false => Cap1re::Cap1re0, - true => Cap1re::Cap1re1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap1re_0(&self) -> bool { - *self == Cap1re::Cap1re0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_cap1re_1(&self) -> bool { - *self == Cap1re::Cap1re1 - } -} -#[doc = "Field `CAP1RE` writer - Rising Edge of Capture Channel 1"] -pub type Cap1reW<'a, REG> = crate::BitWriter<'a, REG, Cap1re>; -impl<'a, REG> Cap1reW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap1re_0(self) -> &'a mut crate::W { - self.variant(Cap1re::Cap1re0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn cap1re_1(self) -> &'a mut crate::W { - self.variant(Cap1re::Cap1re1) - } -} -#[doc = "Falling Edge of Capture Channel 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap1fe { - #[doc = "0: Does not load"] - Cap1fe0 = 0, - #[doc = "1: Loads"] - Cap1fe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap1fe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP1FE` reader - Falling Edge of Capture Channel 1"] -pub type Cap1feR = crate::BitReader; -impl Cap1feR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap1fe { - match self.bits { - false => Cap1fe::Cap1fe0, - true => Cap1fe::Cap1fe1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap1fe_0(&self) -> bool { - *self == Cap1fe::Cap1fe0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_cap1fe_1(&self) -> bool { - *self == Cap1fe::Cap1fe1 - } -} -#[doc = "Field `CAP1FE` writer - Falling Edge of Capture Channel 1"] -pub type Cap1feW<'a, REG> = crate::BitWriter<'a, REG, Cap1fe>; -impl<'a, REG> Cap1feW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap1fe_0(self) -> &'a mut crate::W { - self.variant(Cap1fe::Cap1fe0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn cap1fe_1(self) -> &'a mut crate::W { - self.variant(Cap1fe::Cap1fe1) - } -} -#[doc = "Generate Interrupt on Channel 1 Capture Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap1i { - #[doc = "0: Does not generates"] - Cap1i0 = 0, - #[doc = "1: Generates"] - Cap1i1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap1i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP1I` reader - Generate Interrupt on Channel 1 Capture Event"] -pub type Cap1iR = crate::BitReader; -impl Cap1iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap1i { - match self.bits { - false => Cap1i::Cap1i0, - true => Cap1i::Cap1i1, - } - } - #[doc = "Does not generates"] - #[inline(always)] - pub fn is_cap1i_0(&self) -> bool { - *self == Cap1i::Cap1i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_cap1i_1(&self) -> bool { - *self == Cap1i::Cap1i1 - } -} -#[doc = "Field `CAP1I` writer - Generate Interrupt on Channel 1 Capture Event"] -pub type Cap1iW<'a, REG> = crate::BitWriter<'a, REG, Cap1i>; -impl<'a, REG> Cap1iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generates"] - #[inline(always)] - pub fn cap1i_0(self) -> &'a mut crate::W { - self.variant(Cap1i::Cap1i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn cap1i_1(self) -> &'a mut crate::W { - self.variant(Cap1i::Cap1i1) - } -} -#[doc = "Rising Edge of Capture Channel 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap2re { - #[doc = "0: Does not load"] - Cap2re0 = 0, - #[doc = "1: Loads"] - Cap2re1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap2re) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP2RE` reader - Rising Edge of Capture Channel 2"] -pub type Cap2reR = crate::BitReader; -impl Cap2reR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap2re { - match self.bits { - false => Cap2re::Cap2re0, - true => Cap2re::Cap2re1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap2re_0(&self) -> bool { - *self == Cap2re::Cap2re0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_cap2re_1(&self) -> bool { - *self == Cap2re::Cap2re1 - } -} -#[doc = "Field `CAP2RE` writer - Rising Edge of Capture Channel 2"] -pub type Cap2reW<'a, REG> = crate::BitWriter<'a, REG, Cap2re>; -impl<'a, REG> Cap2reW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap2re_0(self) -> &'a mut crate::W { - self.variant(Cap2re::Cap2re0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn cap2re_1(self) -> &'a mut crate::W { - self.variant(Cap2re::Cap2re1) - } -} -#[doc = "Falling Edge of Capture Channel 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap2fe { - #[doc = "0: Does not load"] - Cap2fe0 = 0, - #[doc = "1: Loads"] - Cap2fe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap2fe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP2FE` reader - Falling Edge of Capture Channel 2"] -pub type Cap2feR = crate::BitReader; -impl Cap2feR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap2fe { - match self.bits { - false => Cap2fe::Cap2fe0, - true => Cap2fe::Cap2fe1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap2fe_0(&self) -> bool { - *self == Cap2fe::Cap2fe0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_cap2fe_1(&self) -> bool { - *self == Cap2fe::Cap2fe1 - } -} -#[doc = "Field `CAP2FE` writer - Falling Edge of Capture Channel 2"] -pub type Cap2feW<'a, REG> = crate::BitWriter<'a, REG, Cap2fe>; -impl<'a, REG> Cap2feW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap2fe_0(self) -> &'a mut crate::W { - self.variant(Cap2fe::Cap2fe0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn cap2fe_1(self) -> &'a mut crate::W { - self.variant(Cap2fe::Cap2fe1) - } -} -#[doc = "Generate Interrupt on Channel 2 Capture Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap2i { - #[doc = "0: Does not generate"] - Cap2i0 = 0, - #[doc = "1: Generates"] - Cap2i1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap2i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP2I` reader - Generate Interrupt on Channel 2 Capture Event"] -pub type Cap2iR = crate::BitReader; -impl Cap2iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap2i { - match self.bits { - false => Cap2i::Cap2i0, - true => Cap2i::Cap2i1, - } - } - #[doc = "Does not generate"] - #[inline(always)] - pub fn is_cap2i_0(&self) -> bool { - *self == Cap2i::Cap2i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_cap2i_1(&self) -> bool { - *self == Cap2i::Cap2i1 - } -} -#[doc = "Field `CAP2I` writer - Generate Interrupt on Channel 2 Capture Event"] -pub type Cap2iW<'a, REG> = crate::BitWriter<'a, REG, Cap2i>; -impl<'a, REG> Cap2iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generate"] - #[inline(always)] - pub fn cap2i_0(self) -> &'a mut crate::W { - self.variant(Cap2i::Cap2i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn cap2i_1(self) -> &'a mut crate::W { - self.variant(Cap2i::Cap2i1) - } -} -#[doc = "Rising Edge of Capture Channel 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap3re { - #[doc = "0: Does not load"] - Cap3re0 = 0, - #[doc = "1: Loads"] - Cap3re1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap3re) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP3RE` reader - Rising Edge of Capture Channel 3"] -pub type Cap3reR = crate::BitReader; -impl Cap3reR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap3re { - match self.bits { - false => Cap3re::Cap3re0, - true => Cap3re::Cap3re1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap3re_0(&self) -> bool { - *self == Cap3re::Cap3re0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_cap3re_1(&self) -> bool { - *self == Cap3re::Cap3re1 - } -} -#[doc = "Field `CAP3RE` writer - Rising Edge of Capture Channel 3"] -pub type Cap3reW<'a, REG> = crate::BitWriter<'a, REG, Cap3re>; -impl<'a, REG> Cap3reW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap3re_0(self) -> &'a mut crate::W { - self.variant(Cap3re::Cap3re0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn cap3re_1(self) -> &'a mut crate::W { - self.variant(Cap3re::Cap3re1) - } -} -#[doc = "Falling Edge of Capture Channel 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap3fe { - #[doc = "0: Does not load"] - Cap3fe0 = 0, - #[doc = "1: Loads"] - Cap3fe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap3fe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP3FE` reader - Falling Edge of Capture Channel 3"] -pub type Cap3feR = crate::BitReader; -impl Cap3feR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap3fe { - match self.bits { - false => Cap3fe::Cap3fe0, - true => Cap3fe::Cap3fe1, - } - } - #[doc = "Does not load"] - #[inline(always)] - pub fn is_cap3fe_0(&self) -> bool { - *self == Cap3fe::Cap3fe0 - } - #[doc = "Loads"] - #[inline(always)] - pub fn is_cap3fe_1(&self) -> bool { - *self == Cap3fe::Cap3fe1 - } -} -#[doc = "Field `CAP3FE` writer - Falling Edge of Capture Channel 3"] -pub type Cap3feW<'a, REG> = crate::BitWriter<'a, REG, Cap3fe>; -impl<'a, REG> Cap3feW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not load"] - #[inline(always)] - pub fn cap3fe_0(self) -> &'a mut crate::W { - self.variant(Cap3fe::Cap3fe0) - } - #[doc = "Loads"] - #[inline(always)] - pub fn cap3fe_1(self) -> &'a mut crate::W { - self.variant(Cap3fe::Cap3fe1) - } -} -#[doc = "Generate Interrupt on Channel 3 Capture Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cap3i { - #[doc = "0: Does not generate"] - Cap3i0 = 0, - #[doc = "1: Generates"] - Cap3i1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cap3i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAP3I` reader - Generate Interrupt on Channel 3 Capture Event"] -pub type Cap3iR = crate::BitReader; -impl Cap3iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cap3i { - match self.bits { - false => Cap3i::Cap3i0, - true => Cap3i::Cap3i1, - } - } - #[doc = "Does not generate"] - #[inline(always)] - pub fn is_cap3i_0(&self) -> bool { - *self == Cap3i::Cap3i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_cap3i_1(&self) -> bool { - *self == Cap3i::Cap3i1 - } -} -#[doc = "Field `CAP3I` writer - Generate Interrupt on Channel 3 Capture Event"] -pub type Cap3iW<'a, REG> = crate::BitWriter<'a, REG, Cap3i>; -impl<'a, REG> Cap3iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generate"] - #[inline(always)] - pub fn cap3i_0(self) -> &'a mut crate::W { - self.variant(Cap3i::Cap3i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn cap3i_1(self) -> &'a mut crate::W { - self.variant(Cap3i::Cap3i1) - } -} -impl R { - #[doc = "Bit 0 - Rising Edge of Capture Channel 0"] - #[inline(always)] - pub fn cap0re(&self) -> Cap0reR { - Cap0reR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Falling Edge of Capture Channel 0"] - #[inline(always)] - pub fn cap0fe(&self) -> Cap0feR { - Cap0feR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Generate Interrupt on Channel 0 Capture Event"] - #[inline(always)] - pub fn cap0i(&self) -> Cap0iR { - Cap0iR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Rising Edge of Capture Channel 1"] - #[inline(always)] - pub fn cap1re(&self) -> Cap1reR { - Cap1reR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Falling Edge of Capture Channel 1"] - #[inline(always)] - pub fn cap1fe(&self) -> Cap1feR { - Cap1feR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Generate Interrupt on Channel 1 Capture Event"] - #[inline(always)] - pub fn cap1i(&self) -> Cap1iR { - Cap1iR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Rising Edge of Capture Channel 2"] - #[inline(always)] - pub fn cap2re(&self) -> Cap2reR { - Cap2reR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Falling Edge of Capture Channel 2"] - #[inline(always)] - pub fn cap2fe(&self) -> Cap2feR { - Cap2feR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Generate Interrupt on Channel 2 Capture Event"] - #[inline(always)] - pub fn cap2i(&self) -> Cap2iR { - Cap2iR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Rising Edge of Capture Channel 3"] - #[inline(always)] - pub fn cap3re(&self) -> Cap3reR { - Cap3reR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Falling Edge of Capture Channel 3"] - #[inline(always)] - pub fn cap3fe(&self) -> Cap3feR { - Cap3feR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Generate Interrupt on Channel 3 Capture Event"] - #[inline(always)] - pub fn cap3i(&self) -> Cap3iR { - Cap3iR::new(((self.bits >> 11) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Rising Edge of Capture Channel 0"] - #[inline(always)] - pub fn cap0re(&mut self) -> Cap0reW { - Cap0reW::new(self, 0) - } - #[doc = "Bit 1 - Falling Edge of Capture Channel 0"] - #[inline(always)] - pub fn cap0fe(&mut self) -> Cap0feW { - Cap0feW::new(self, 1) - } - #[doc = "Bit 2 - Generate Interrupt on Channel 0 Capture Event"] - #[inline(always)] - pub fn cap0i(&mut self) -> Cap0iW { - Cap0iW::new(self, 2) - } - #[doc = "Bit 3 - Rising Edge of Capture Channel 1"] - #[inline(always)] - pub fn cap1re(&mut self) -> Cap1reW { - Cap1reW::new(self, 3) - } - #[doc = "Bit 4 - Falling Edge of Capture Channel 1"] - #[inline(always)] - pub fn cap1fe(&mut self) -> Cap1feW { - Cap1feW::new(self, 4) - } - #[doc = "Bit 5 - Generate Interrupt on Channel 1 Capture Event"] - #[inline(always)] - pub fn cap1i(&mut self) -> Cap1iW { - Cap1iW::new(self, 5) - } - #[doc = "Bit 6 - Rising Edge of Capture Channel 2"] - #[inline(always)] - pub fn cap2re(&mut self) -> Cap2reW { - Cap2reW::new(self, 6) - } - #[doc = "Bit 7 - Falling Edge of Capture Channel 2"] - #[inline(always)] - pub fn cap2fe(&mut self) -> Cap2feW { - Cap2feW::new(self, 7) - } - #[doc = "Bit 8 - Generate Interrupt on Channel 2 Capture Event"] - #[inline(always)] - pub fn cap2i(&mut self) -> Cap2iW { - Cap2iW::new(self, 8) - } - #[doc = "Bit 9 - Rising Edge of Capture Channel 3"] - #[inline(always)] - pub fn cap3re(&mut self) -> Cap3reW { - Cap3reW::new(self, 9) - } - #[doc = "Bit 10 - Falling Edge of Capture Channel 3"] - #[inline(always)] - pub fn cap3fe(&mut self) -> Cap3feW { - Cap3feW::new(self, 10) - } - #[doc = "Bit 11 - Generate Interrupt on Channel 3 Capture Event"] - #[inline(always)] - pub fn cap3i(&mut self) -> Cap3iW { - Cap3iW::new(self, 11) - } -} -#[doc = "Capture Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CcrSpec; -impl crate::RegisterSpec for CcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] -impl crate::Readable for CcrSpec {} -#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] -impl crate::Writable for CcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CCR to value 0"] -impl crate::Resettable for CcrSpec {} diff --git a/mcxa276-pac/src/ctimer0/cr.rs b/mcxa276-pac/src/ctimer0/cr.rs deleted file mode 100644 index c0123971d..000000000 --- a/mcxa276-pac/src/ctimer0/cr.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `CR[%s]` reader"] -pub type R = crate::R; -#[doc = "Field `CAP` reader - Timer Counter Capture Value"] -pub type CapR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Timer Counter Capture Value"] - #[inline(always)] - pub fn cap(&self) -> CapR { - CapR::new(self.bits) - } -} -#[doc = "Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CrSpec; -impl crate::RegisterSpec for CrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cr::R`](R) reader structure"] -impl crate::Readable for CrSpec {} -#[doc = "`reset()` method sets CR[%s] to value 0"] -impl crate::Resettable for CrSpec {} diff --git a/mcxa276-pac/src/ctimer0/ctcr.rs b/mcxa276-pac/src/ctimer0/ctcr.rs deleted file mode 100644 index 52376d1d8..000000000 --- a/mcxa276-pac/src/ctimer0/ctcr.rs +++ /dev/null @@ -1,375 +0,0 @@ -#[doc = "Register `CTCR` reader"] -pub type R = crate::R; -#[doc = "Register `CTCR` writer"] -pub type W = crate::W; -#[doc = "Counter Timer Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ctmode { - #[doc = "0: Timer mode"] - Timer = 0, - #[doc = "1: Counter mode rising edge"] - CounterRisingEdge = 1, - #[doc = "2: Counter mode falling edge"] - CounterFallingEdge = 2, - #[doc = "3: Counter mode dual edge"] - CounterDualEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ctmode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ctmode { - type Ux = u8; -} -impl crate::IsEnum for Ctmode {} -#[doc = "Field `CTMODE` reader - Counter Timer Mode"] -pub type CtmodeR = crate::FieldReader; -impl CtmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctmode { - match self.bits { - 0 => Ctmode::Timer, - 1 => Ctmode::CounterRisingEdge, - 2 => Ctmode::CounterFallingEdge, - 3 => Ctmode::CounterDualEdge, - _ => unreachable!(), - } - } - #[doc = "Timer mode"] - #[inline(always)] - pub fn is_timer(&self) -> bool { - *self == Ctmode::Timer - } - #[doc = "Counter mode rising edge"] - #[inline(always)] - pub fn is_counter_rising_edge(&self) -> bool { - *self == Ctmode::CounterRisingEdge - } - #[doc = "Counter mode falling edge"] - #[inline(always)] - pub fn is_counter_falling_edge(&self) -> bool { - *self == Ctmode::CounterFallingEdge - } - #[doc = "Counter mode dual edge"] - #[inline(always)] - pub fn is_counter_dual_edge(&self) -> bool { - *self == Ctmode::CounterDualEdge - } -} -#[doc = "Field `CTMODE` writer - Counter Timer Mode"] -pub type CtmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ctmode, crate::Safe>; -impl<'a, REG> CtmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer mode"] - #[inline(always)] - pub fn timer(self) -> &'a mut crate::W { - self.variant(Ctmode::Timer) - } - #[doc = "Counter mode rising edge"] - #[inline(always)] - pub fn counter_rising_edge(self) -> &'a mut crate::W { - self.variant(Ctmode::CounterRisingEdge) - } - #[doc = "Counter mode falling edge"] - #[inline(always)] - pub fn counter_falling_edge(self) -> &'a mut crate::W { - self.variant(Ctmode::CounterFallingEdge) - } - #[doc = "Counter mode dual edge"] - #[inline(always)] - pub fn counter_dual_edge(self) -> &'a mut crate::W { - self.variant(Ctmode::CounterDualEdge) - } -} -#[doc = "Count Input Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cinsel { - #[doc = "0: Channel 0, CAPn\\[0\\] for CTIMERn"] - Channel0 = 0, - #[doc = "1: Channel 1, CAPn\\[1\\] for CTIMERn"] - Channel1 = 1, - #[doc = "2: Channel 2, CAPn\\[2\\] for CTIMERn"] - Channel2 = 2, - #[doc = "3: Channel 3, CAPn\\[3\\] for CTIMERn"] - Channel3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cinsel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cinsel { - type Ux = u8; -} -impl crate::IsEnum for Cinsel {} -#[doc = "Field `CINSEL` reader - Count Input Select"] -pub type CinselR = crate::FieldReader; -impl CinselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cinsel { - match self.bits { - 0 => Cinsel::Channel0, - 1 => Cinsel::Channel1, - 2 => Cinsel::Channel2, - 3 => Cinsel::Channel3, - _ => unreachable!(), - } - } - #[doc = "Channel 0, CAPn\\[0\\] for CTIMERn"] - #[inline(always)] - pub fn is_channel_0(&self) -> bool { - *self == Cinsel::Channel0 - } - #[doc = "Channel 1, CAPn\\[1\\] for CTIMERn"] - #[inline(always)] - pub fn is_channel_1(&self) -> bool { - *self == Cinsel::Channel1 - } - #[doc = "Channel 2, CAPn\\[2\\] for CTIMERn"] - #[inline(always)] - pub fn is_channel_2(&self) -> bool { - *self == Cinsel::Channel2 - } - #[doc = "Channel 3, CAPn\\[3\\] for CTIMERn"] - #[inline(always)] - pub fn is_channel_3(&self) -> bool { - *self == Cinsel::Channel3 - } -} -#[doc = "Field `CINSEL` writer - Count Input Select"] -pub type CinselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cinsel, crate::Safe>; -impl<'a, REG> CinselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Channel 0, CAPn\\[0\\] for CTIMERn"] - #[inline(always)] - pub fn channel_0(self) -> &'a mut crate::W { - self.variant(Cinsel::Channel0) - } - #[doc = "Channel 1, CAPn\\[1\\] for CTIMERn"] - #[inline(always)] - pub fn channel_1(self) -> &'a mut crate::W { - self.variant(Cinsel::Channel1) - } - #[doc = "Channel 2, CAPn\\[2\\] for CTIMERn"] - #[inline(always)] - pub fn channel_2(self) -> &'a mut crate::W { - self.variant(Cinsel::Channel2) - } - #[doc = "Channel 3, CAPn\\[3\\] for CTIMERn"] - #[inline(always)] - pub fn channel_3(self) -> &'a mut crate::W { - self.variant(Cinsel::Channel3) - } -} -#[doc = "Field `ENCC` reader - Capture Channel Enable"] -pub type EnccR = crate::BitReader; -#[doc = "Field `ENCC` writer - Capture Channel Enable"] -pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Edge Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Selcc { - #[doc = "0: Capture channel 0 rising edge"] - Channel0Rising = 0, - #[doc = "1: Capture channel 0 falling edge"] - Channel0Falling = 1, - #[doc = "2: Capture channel 1 rising edge"] - Channel1Rising = 2, - #[doc = "3: Capture channel 1 falling edge"] - Channel1Falling = 3, - #[doc = "4: Capture channel 2 rising edge"] - Channel2Rising = 4, - #[doc = "5: Capture channel 2 falling edge"] - Channel2Falling = 5, - #[doc = "6: Capture channel 3 rising edge"] - Channel3Rising = 6, - #[doc = "7: Capture channel 3 falling edge"] - Channel3Falling = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Selcc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Selcc { - type Ux = u8; -} -impl crate::IsEnum for Selcc {} -#[doc = "Field `SELCC` reader - Edge Select"] -pub type SelccR = crate::FieldReader; -impl SelccR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Selcc { - match self.bits { - 0 => Selcc::Channel0Rising, - 1 => Selcc::Channel0Falling, - 2 => Selcc::Channel1Rising, - 3 => Selcc::Channel1Falling, - 4 => Selcc::Channel2Rising, - 5 => Selcc::Channel2Falling, - 6 => Selcc::Channel3Rising, - 7 => Selcc::Channel3Falling, - _ => unreachable!(), - } - } - #[doc = "Capture channel 0 rising edge"] - #[inline(always)] - pub fn is_channel_0_rising(&self) -> bool { - *self == Selcc::Channel0Rising - } - #[doc = "Capture channel 0 falling edge"] - #[inline(always)] - pub fn is_channel_0_falling(&self) -> bool { - *self == Selcc::Channel0Falling - } - #[doc = "Capture channel 1 rising edge"] - #[inline(always)] - pub fn is_channel_1_rising(&self) -> bool { - *self == Selcc::Channel1Rising - } - #[doc = "Capture channel 1 falling edge"] - #[inline(always)] - pub fn is_channel_1_falling(&self) -> bool { - *self == Selcc::Channel1Falling - } - #[doc = "Capture channel 2 rising edge"] - #[inline(always)] - pub fn is_channel_2_rising(&self) -> bool { - *self == Selcc::Channel2Rising - } - #[doc = "Capture channel 2 falling edge"] - #[inline(always)] - pub fn is_channel_2_falling(&self) -> bool { - *self == Selcc::Channel2Falling - } - #[doc = "Capture channel 3 rising edge"] - #[inline(always)] - pub fn is_channel_3_rising(&self) -> bool { - *self == Selcc::Channel3Rising - } - #[doc = "Capture channel 3 falling edge"] - #[inline(always)] - pub fn is_channel_3_falling(&self) -> bool { - *self == Selcc::Channel3Falling - } -} -#[doc = "Field `SELCC` writer - Edge Select"] -pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc, crate::Safe>; -impl<'a, REG> SelccW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Capture channel 0 rising edge"] - #[inline(always)] - pub fn channel_0_rising(self) -> &'a mut crate::W { - self.variant(Selcc::Channel0Rising) - } - #[doc = "Capture channel 0 falling edge"] - #[inline(always)] - pub fn channel_0_falling(self) -> &'a mut crate::W { - self.variant(Selcc::Channel0Falling) - } - #[doc = "Capture channel 1 rising edge"] - #[inline(always)] - pub fn channel_1_rising(self) -> &'a mut crate::W { - self.variant(Selcc::Channel1Rising) - } - #[doc = "Capture channel 1 falling edge"] - #[inline(always)] - pub fn channel_1_falling(self) -> &'a mut crate::W { - self.variant(Selcc::Channel1Falling) - } - #[doc = "Capture channel 2 rising edge"] - #[inline(always)] - pub fn channel_2_rising(self) -> &'a mut crate::W { - self.variant(Selcc::Channel2Rising) - } - #[doc = "Capture channel 2 falling edge"] - #[inline(always)] - pub fn channel_2_falling(self) -> &'a mut crate::W { - self.variant(Selcc::Channel2Falling) - } - #[doc = "Capture channel 3 rising edge"] - #[inline(always)] - pub fn channel_3_rising(self) -> &'a mut crate::W { - self.variant(Selcc::Channel3Rising) - } - #[doc = "Capture channel 3 falling edge"] - #[inline(always)] - pub fn channel_3_falling(self) -> &'a mut crate::W { - self.variant(Selcc::Channel3Falling) - } -} -impl R { - #[doc = "Bits 0:1 - Counter Timer Mode"] - #[inline(always)] - pub fn ctmode(&self) -> CtmodeR { - CtmodeR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Count Input Select"] - #[inline(always)] - pub fn cinsel(&self) -> CinselR { - CinselR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bit 4 - Capture Channel Enable"] - #[inline(always)] - pub fn encc(&self) -> EnccR { - EnccR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 5:7 - Edge Select"] - #[inline(always)] - pub fn selcc(&self) -> SelccR { - SelccR::new(((self.bits >> 5) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Counter Timer Mode"] - #[inline(always)] - pub fn ctmode(&mut self) -> CtmodeW { - CtmodeW::new(self, 0) - } - #[doc = "Bits 2:3 - Count Input Select"] - #[inline(always)] - pub fn cinsel(&mut self) -> CinselW { - CinselW::new(self, 2) - } - #[doc = "Bit 4 - Capture Channel Enable"] - #[inline(always)] - pub fn encc(&mut self) -> EnccW { - EnccW::new(self, 4) - } - #[doc = "Bits 5:7 - Edge Select"] - #[inline(always)] - pub fn selcc(&mut self) -> SelccW { - SelccW::new(self, 5) - } -} -#[doc = "Count Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtcrSpec; -impl crate::RegisterSpec for CtcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"] -impl crate::Readable for CtcrSpec {} -#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"] -impl crate::Writable for CtcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTCR to value 0"] -impl crate::Resettable for CtcrSpec {} diff --git a/mcxa276-pac/src/ctimer0/emr.rs b/mcxa276-pac/src/ctimer0/emr.rs deleted file mode 100644 index 30ae43a01..000000000 --- a/mcxa276-pac/src/ctimer0/emr.rs +++ /dev/null @@ -1,657 +0,0 @@ -#[doc = "Register `EMR` reader"] -pub type R = crate::R; -#[doc = "Register `EMR` writer"] -pub type W = crate::W; -#[doc = "External Match 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Em0 { - #[doc = "0: Low"] - Clear = 0, - #[doc = "1: High"] - Set = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Em0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EM0` reader - External Match 0"] -pub type Em0R = crate::BitReader; -impl Em0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Em0 { - match self.bits { - false => Em0::Clear, - true => Em0::Set, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Em0::Clear - } - #[doc = "High"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Em0::Set - } -} -#[doc = "Field `EM0` writer - External Match 0"] -pub type Em0W<'a, REG> = crate::BitWriter<'a, REG, Em0>; -impl<'a, REG> Em0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Em0::Clear) - } - #[doc = "High"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Em0::Set) - } -} -#[doc = "External Match 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Em1 { - #[doc = "0: Low"] - Clear = 0, - #[doc = "1: High"] - Set = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Em1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EM1` reader - External Match 1"] -pub type Em1R = crate::BitReader; -impl Em1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Em1 { - match self.bits { - false => Em1::Clear, - true => Em1::Set, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Em1::Clear - } - #[doc = "High"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Em1::Set - } -} -#[doc = "Field `EM1` writer - External Match 1"] -pub type Em1W<'a, REG> = crate::BitWriter<'a, REG, Em1>; -impl<'a, REG> Em1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Em1::Clear) - } - #[doc = "High"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Em1::Set) - } -} -#[doc = "External Match 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Em2 { - #[doc = "0: Low"] - Clear = 0, - #[doc = "1: High"] - Set = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Em2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EM2` reader - External Match 2"] -pub type Em2R = crate::BitReader; -impl Em2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Em2 { - match self.bits { - false => Em2::Clear, - true => Em2::Set, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Em2::Clear - } - #[doc = "High"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Em2::Set - } -} -#[doc = "Field `EM2` writer - External Match 2"] -pub type Em2W<'a, REG> = crate::BitWriter<'a, REG, Em2>; -impl<'a, REG> Em2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Em2::Clear) - } - #[doc = "High"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Em2::Set) - } -} -#[doc = "External Match 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Em3 { - #[doc = "0: Low"] - Clear = 0, - #[doc = "1: High"] - Set = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Em3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EM3` reader - External Match 3"] -pub type Em3R = crate::BitReader; -impl Em3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Em3 { - match self.bits { - false => Em3::Clear, - true => Em3::Set, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Em3::Clear - } - #[doc = "High"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Em3::Set - } -} -#[doc = "Field `EM3` writer - External Match 3"] -pub type Em3W<'a, REG> = crate::BitWriter<'a, REG, Em3>; -impl<'a, REG> Em3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Em3::Clear) - } - #[doc = "High"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Em3::Set) - } -} -#[doc = "External Match Control 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Emc0 { - #[doc = "0: Does nothing"] - DoNothing = 0, - #[doc = "1: Goes low"] - Clear = 1, - #[doc = "2: Goes high"] - Set = 2, - #[doc = "3: Toggles"] - Toggle = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Emc0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Emc0 { - type Ux = u8; -} -impl crate::IsEnum for Emc0 {} -#[doc = "Field `EMC0` reader - External Match Control 0"] -pub type Emc0R = crate::FieldReader; -impl Emc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Emc0 { - match self.bits { - 0 => Emc0::DoNothing, - 1 => Emc0::Clear, - 2 => Emc0::Set, - 3 => Emc0::Toggle, - _ => unreachable!(), - } - } - #[doc = "Does nothing"] - #[inline(always)] - pub fn is_do_nothing(&self) -> bool { - *self == Emc0::DoNothing - } - #[doc = "Goes low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Emc0::Clear - } - #[doc = "Goes high"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Emc0::Set - } - #[doc = "Toggles"] - #[inline(always)] - pub fn is_toggle(&self) -> bool { - *self == Emc0::Toggle - } -} -#[doc = "Field `EMC0` writer - External Match Control 0"] -pub type Emc0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc0, crate::Safe>; -impl<'a, REG> Emc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn do_nothing(self) -> &'a mut crate::W { - self.variant(Emc0::DoNothing) - } - #[doc = "Goes low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Emc0::Clear) - } - #[doc = "Goes high"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Emc0::Set) - } - #[doc = "Toggles"] - #[inline(always)] - pub fn toggle(self) -> &'a mut crate::W { - self.variant(Emc0::Toggle) - } -} -#[doc = "External Match Control 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Emc1 { - #[doc = "0: Does nothing"] - DoNothing = 0, - #[doc = "1: Goes low"] - Clear = 1, - #[doc = "2: Goes high"] - Set = 2, - #[doc = "3: Toggles"] - Toggle = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Emc1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Emc1 { - type Ux = u8; -} -impl crate::IsEnum for Emc1 {} -#[doc = "Field `EMC1` reader - External Match Control 1"] -pub type Emc1R = crate::FieldReader; -impl Emc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Emc1 { - match self.bits { - 0 => Emc1::DoNothing, - 1 => Emc1::Clear, - 2 => Emc1::Set, - 3 => Emc1::Toggle, - _ => unreachable!(), - } - } - #[doc = "Does nothing"] - #[inline(always)] - pub fn is_do_nothing(&self) -> bool { - *self == Emc1::DoNothing - } - #[doc = "Goes low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Emc1::Clear - } - #[doc = "Goes high"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Emc1::Set - } - #[doc = "Toggles"] - #[inline(always)] - pub fn is_toggle(&self) -> bool { - *self == Emc1::Toggle - } -} -#[doc = "Field `EMC1` writer - External Match Control 1"] -pub type Emc1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc1, crate::Safe>; -impl<'a, REG> Emc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn do_nothing(self) -> &'a mut crate::W { - self.variant(Emc1::DoNothing) - } - #[doc = "Goes low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Emc1::Clear) - } - #[doc = "Goes high"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Emc1::Set) - } - #[doc = "Toggles"] - #[inline(always)] - pub fn toggle(self) -> &'a mut crate::W { - self.variant(Emc1::Toggle) - } -} -#[doc = "External Match Control 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Emc2 { - #[doc = "0: Does nothing"] - DoNothing = 0, - #[doc = "1: Goes low"] - Clear = 1, - #[doc = "2: Goes high"] - Set = 2, - #[doc = "3: Toggles"] - Toggle = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Emc2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Emc2 { - type Ux = u8; -} -impl crate::IsEnum for Emc2 {} -#[doc = "Field `EMC2` reader - External Match Control 2"] -pub type Emc2R = crate::FieldReader; -impl Emc2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Emc2 { - match self.bits { - 0 => Emc2::DoNothing, - 1 => Emc2::Clear, - 2 => Emc2::Set, - 3 => Emc2::Toggle, - _ => unreachable!(), - } - } - #[doc = "Does nothing"] - #[inline(always)] - pub fn is_do_nothing(&self) -> bool { - *self == Emc2::DoNothing - } - #[doc = "Goes low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Emc2::Clear - } - #[doc = "Goes high"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Emc2::Set - } - #[doc = "Toggles"] - #[inline(always)] - pub fn is_toggle(&self) -> bool { - *self == Emc2::Toggle - } -} -#[doc = "Field `EMC2` writer - External Match Control 2"] -pub type Emc2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc2, crate::Safe>; -impl<'a, REG> Emc2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn do_nothing(self) -> &'a mut crate::W { - self.variant(Emc2::DoNothing) - } - #[doc = "Goes low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Emc2::Clear) - } - #[doc = "Goes high"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Emc2::Set) - } - #[doc = "Toggles"] - #[inline(always)] - pub fn toggle(self) -> &'a mut crate::W { - self.variant(Emc2::Toggle) - } -} -#[doc = "External Match Control 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Emc3 { - #[doc = "0: Does nothing"] - DoNothing = 0, - #[doc = "1: Goes low"] - Clear = 1, - #[doc = "2: Goes high"] - Set = 2, - #[doc = "3: Toggles"] - Toggle = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Emc3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Emc3 { - type Ux = u8; -} -impl crate::IsEnum for Emc3 {} -#[doc = "Field `EMC3` reader - External Match Control 3"] -pub type Emc3R = crate::FieldReader; -impl Emc3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Emc3 { - match self.bits { - 0 => Emc3::DoNothing, - 1 => Emc3::Clear, - 2 => Emc3::Set, - 3 => Emc3::Toggle, - _ => unreachable!(), - } - } - #[doc = "Does nothing"] - #[inline(always)] - pub fn is_do_nothing(&self) -> bool { - *self == Emc3::DoNothing - } - #[doc = "Goes low"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Emc3::Clear - } - #[doc = "Goes high"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Emc3::Set - } - #[doc = "Toggles"] - #[inline(always)] - pub fn is_toggle(&self) -> bool { - *self == Emc3::Toggle - } -} -#[doc = "Field `EMC3` writer - External Match Control 3"] -pub type Emc3W<'a, REG> = crate::FieldWriter<'a, REG, 2, Emc3, crate::Safe>; -impl<'a, REG> Emc3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn do_nothing(self) -> &'a mut crate::W { - self.variant(Emc3::DoNothing) - } - #[doc = "Goes low"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Emc3::Clear) - } - #[doc = "Goes high"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Emc3::Set) - } - #[doc = "Toggles"] - #[inline(always)] - pub fn toggle(self) -> &'a mut crate::W { - self.variant(Emc3::Toggle) - } -} -impl R { - #[doc = "Bit 0 - External Match 0"] - #[inline(always)] - pub fn em0(&self) -> Em0R { - Em0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - External Match 1"] - #[inline(always)] - pub fn em1(&self) -> Em1R { - Em1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - External Match 2"] - #[inline(always)] - pub fn em2(&self) -> Em2R { - Em2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - External Match 3"] - #[inline(always)] - pub fn em3(&self) -> Em3R { - Em3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - External Match Control 0"] - #[inline(always)] - pub fn emc0(&self) -> Emc0R { - Emc0R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - External Match Control 1"] - #[inline(always)] - pub fn emc1(&self) -> Emc1R { - Emc1R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - External Match Control 2"] - #[inline(always)] - pub fn emc2(&self) -> Emc2R { - Emc2R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - External Match Control 3"] - #[inline(always)] - pub fn emc3(&self) -> Emc3R { - Emc3R::new(((self.bits >> 10) & 3) as u8) - } -} -impl W { - #[doc = "Bit 0 - External Match 0"] - #[inline(always)] - pub fn em0(&mut self) -> Em0W { - Em0W::new(self, 0) - } - #[doc = "Bit 1 - External Match 1"] - #[inline(always)] - pub fn em1(&mut self) -> Em1W { - Em1W::new(self, 1) - } - #[doc = "Bit 2 - External Match 2"] - #[inline(always)] - pub fn em2(&mut self) -> Em2W { - Em2W::new(self, 2) - } - #[doc = "Bit 3 - External Match 3"] - #[inline(always)] - pub fn em3(&mut self) -> Em3W { - Em3W::new(self, 3) - } - #[doc = "Bits 4:5 - External Match Control 0"] - #[inline(always)] - pub fn emc0(&mut self) -> Emc0W { - Emc0W::new(self, 4) - } - #[doc = "Bits 6:7 - External Match Control 1"] - #[inline(always)] - pub fn emc1(&mut self) -> Emc1W { - Emc1W::new(self, 6) - } - #[doc = "Bits 8:9 - External Match Control 2"] - #[inline(always)] - pub fn emc2(&mut self) -> Emc2W { - Emc2W::new(self, 8) - } - #[doc = "Bits 10:11 - External Match Control 3"] - #[inline(always)] - pub fn emc3(&mut self) -> Emc3W { - Emc3W::new(self, 10) - } -} -#[doc = "External Match\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EmrSpec; -impl crate::RegisterSpec for EmrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`emr::R`](R) reader structure"] -impl crate::Readable for EmrSpec {} -#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"] -impl crate::Writable for EmrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EMR to value 0"] -impl crate::Resettable for EmrSpec {} diff --git a/mcxa276-pac/src/ctimer0/ir.rs b/mcxa276-pac/src/ctimer0/ir.rs deleted file mode 100644 index 2ab9e5dd9..000000000 --- a/mcxa276-pac/src/ctimer0/ir.rs +++ /dev/null @@ -1,133 +0,0 @@ -#[doc = "Register `IR` reader"] -pub type R = crate::R; -#[doc = "Register `IR` writer"] -pub type W = crate::W; -#[doc = "Field `MR0INT` reader - Interrupt Flag for Match Channel 0 Event"] -pub type Mr0intR = crate::BitReader; -#[doc = "Field `MR0INT` writer - Interrupt Flag for Match Channel 0 Event"] -pub type Mr0intW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MR1INT` reader - Interrupt Flag for Match Channel 1 Event"] -pub type Mr1intR = crate::BitReader; -#[doc = "Field `MR1INT` writer - Interrupt Flag for Match Channel 1 Event"] -pub type Mr1intW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MR2INT` reader - Interrupt Flag for Match Channel 2 Event"] -pub type Mr2intR = crate::BitReader; -#[doc = "Field `MR2INT` writer - Interrupt Flag for Match Channel 2 Event"] -pub type Mr2intW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MR3INT` reader - Interrupt Flag for Match Channel 3 Event"] -pub type Mr3intR = crate::BitReader; -#[doc = "Field `MR3INT` writer - Interrupt Flag for Match Channel 3 Event"] -pub type Mr3intW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CR0INT` reader - Interrupt Flag for Capture Channel 0 Event"] -pub type Cr0intR = crate::BitReader; -#[doc = "Field `CR0INT` writer - Interrupt Flag for Capture Channel 0 Event"] -pub type Cr0intW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CR1INT` reader - Interrupt Flag for Capture Channel 1 Event"] -pub type Cr1intR = crate::BitReader; -#[doc = "Field `CR1INT` writer - Interrupt Flag for Capture Channel 1 Event"] -pub type Cr1intW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CR2INT` reader - Interrupt Flag for Capture Channel 2 Event"] -pub type Cr2intR = crate::BitReader; -#[doc = "Field `CR2INT` writer - Interrupt Flag for Capture Channel 2 Event"] -pub type Cr2intW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CR3INT` reader - Interrupt Flag for Capture Channel 3 Event"] -pub type Cr3intR = crate::BitReader; -#[doc = "Field `CR3INT` writer - Interrupt Flag for Capture Channel 3 Event"] -pub type Cr3intW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Interrupt Flag for Match Channel 0 Event"] - #[inline(always)] - pub fn mr0int(&self) -> Mr0intR { - Mr0intR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Interrupt Flag for Match Channel 1 Event"] - #[inline(always)] - pub fn mr1int(&self) -> Mr1intR { - Mr1intR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Interrupt Flag for Match Channel 2 Event"] - #[inline(always)] - pub fn mr2int(&self) -> Mr2intR { - Mr2intR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Interrupt Flag for Match Channel 3 Event"] - #[inline(always)] - pub fn mr3int(&self) -> Mr3intR { - Mr3intR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Interrupt Flag for Capture Channel 0 Event"] - #[inline(always)] - pub fn cr0int(&self) -> Cr0intR { - Cr0intR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Interrupt Flag for Capture Channel 1 Event"] - #[inline(always)] - pub fn cr1int(&self) -> Cr1intR { - Cr1intR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Interrupt Flag for Capture Channel 2 Event"] - #[inline(always)] - pub fn cr2int(&self) -> Cr2intR { - Cr2intR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Interrupt Flag for Capture Channel 3 Event"] - #[inline(always)] - pub fn cr3int(&self) -> Cr3intR { - Cr3intR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Interrupt Flag for Match Channel 0 Event"] - #[inline(always)] - pub fn mr0int(&mut self) -> Mr0intW { - Mr0intW::new(self, 0) - } - #[doc = "Bit 1 - Interrupt Flag for Match Channel 1 Event"] - #[inline(always)] - pub fn mr1int(&mut self) -> Mr1intW { - Mr1intW::new(self, 1) - } - #[doc = "Bit 2 - Interrupt Flag for Match Channel 2 Event"] - #[inline(always)] - pub fn mr2int(&mut self) -> Mr2intW { - Mr2intW::new(self, 2) - } - #[doc = "Bit 3 - Interrupt Flag for Match Channel 3 Event"] - #[inline(always)] - pub fn mr3int(&mut self) -> Mr3intW { - Mr3intW::new(self, 3) - } - #[doc = "Bit 4 - Interrupt Flag for Capture Channel 0 Event"] - #[inline(always)] - pub fn cr0int(&mut self) -> Cr0intW { - Cr0intW::new(self, 4) - } - #[doc = "Bit 5 - Interrupt Flag for Capture Channel 1 Event"] - #[inline(always)] - pub fn cr1int(&mut self) -> Cr1intW { - Cr1intW::new(self, 5) - } - #[doc = "Bit 6 - Interrupt Flag for Capture Channel 2 Event"] - #[inline(always)] - pub fn cr2int(&mut self) -> Cr2intW { - Cr2intW::new(self, 6) - } - #[doc = "Bit 7 - Interrupt Flag for Capture Channel 3 Event"] - #[inline(always)] - pub fn cr3int(&mut self) -> Cr3intW { - Cr3intW::new(self, 7) - } -} -#[doc = "Interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IrSpec; -impl crate::RegisterSpec for IrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ir::R`](R) reader structure"] -impl crate::Readable for IrSpec {} -#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"] -impl crate::Writable for IrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IR to value 0"] -impl crate::Resettable for IrSpec {} diff --git a/mcxa276-pac/src/ctimer0/mcr.rs b/mcxa276-pac/src/ctimer0/mcr.rs deleted file mode 100644 index 36a580ff8..000000000 --- a/mcxa276-pac/src/ctimer0/mcr.rs +++ /dev/null @@ -1,1029 +0,0 @@ -#[doc = "Register `MCR` reader"] -pub type R = crate::R; -#[doc = "Register `MCR` writer"] -pub type W = crate::W; -#[doc = "Interrupt on MR0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr0i { - #[doc = "0: Does not generate"] - Mr0i0 = 0, - #[doc = "1: Generates"] - Mr0i1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr0i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR0I` reader - Interrupt on MR0"] -pub type Mr0iR = crate::BitReader; -impl Mr0iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr0i { - match self.bits { - false => Mr0i::Mr0i0, - true => Mr0i::Mr0i1, - } - } - #[doc = "Does not generate"] - #[inline(always)] - pub fn is_mr0i_0(&self) -> bool { - *self == Mr0i::Mr0i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_mr0i_1(&self) -> bool { - *self == Mr0i::Mr0i1 - } -} -#[doc = "Field `MR0I` writer - Interrupt on MR0"] -pub type Mr0iW<'a, REG> = crate::BitWriter<'a, REG, Mr0i>; -impl<'a, REG> Mr0iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generate"] - #[inline(always)] - pub fn mr0i_0(self) -> &'a mut crate::W { - self.variant(Mr0i::Mr0i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn mr0i_1(self) -> &'a mut crate::W { - self.variant(Mr0i::Mr0i1) - } -} -#[doc = "Reset on MR0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr0r { - #[doc = "0: Does not reset"] - Mr0r0 = 0, - #[doc = "1: Resets"] - Mr0r1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr0r) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR0R` reader - Reset on MR0"] -pub type Mr0rR = crate::BitReader; -impl Mr0rR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr0r { - match self.bits { - false => Mr0r::Mr0r0, - true => Mr0r::Mr0r1, - } - } - #[doc = "Does not reset"] - #[inline(always)] - pub fn is_mr0r_0(&self) -> bool { - *self == Mr0r::Mr0r0 - } - #[doc = "Resets"] - #[inline(always)] - pub fn is_mr0r_1(&self) -> bool { - *self == Mr0r::Mr0r1 - } -} -#[doc = "Field `MR0R` writer - Reset on MR0"] -pub type Mr0rW<'a, REG> = crate::BitWriter<'a, REG, Mr0r>; -impl<'a, REG> Mr0rW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reset"] - #[inline(always)] - pub fn mr0r_0(self) -> &'a mut crate::W { - self.variant(Mr0r::Mr0r0) - } - #[doc = "Resets"] - #[inline(always)] - pub fn mr0r_1(self) -> &'a mut crate::W { - self.variant(Mr0r::Mr0r1) - } -} -#[doc = "Stop on MR0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr0s { - #[doc = "0: Does not stop"] - Mr0s0 = 0, - #[doc = "1: Stops"] - Mr0s1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr0s) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR0S` reader - Stop on MR0"] -pub type Mr0sR = crate::BitReader; -impl Mr0sR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr0s { - match self.bits { - false => Mr0s::Mr0s0, - true => Mr0s::Mr0s1, - } - } - #[doc = "Does not stop"] - #[inline(always)] - pub fn is_mr0s_0(&self) -> bool { - *self == Mr0s::Mr0s0 - } - #[doc = "Stops"] - #[inline(always)] - pub fn is_mr0s_1(&self) -> bool { - *self == Mr0s::Mr0s1 - } -} -#[doc = "Field `MR0S` writer - Stop on MR0"] -pub type Mr0sW<'a, REG> = crate::BitWriter<'a, REG, Mr0s>; -impl<'a, REG> Mr0sW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not stop"] - #[inline(always)] - pub fn mr0s_0(self) -> &'a mut crate::W { - self.variant(Mr0s::Mr0s0) - } - #[doc = "Stops"] - #[inline(always)] - pub fn mr0s_1(self) -> &'a mut crate::W { - self.variant(Mr0s::Mr0s1) - } -} -#[doc = "Interrupt on MR1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr1i { - #[doc = "0: Does not generate"] - Mr1i0 = 0, - #[doc = "1: Generates"] - Mr1i1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr1i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR1I` reader - Interrupt on MR1"] -pub type Mr1iR = crate::BitReader; -impl Mr1iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr1i { - match self.bits { - false => Mr1i::Mr1i0, - true => Mr1i::Mr1i1, - } - } - #[doc = "Does not generate"] - #[inline(always)] - pub fn is_mr1i_0(&self) -> bool { - *self == Mr1i::Mr1i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_mr1i_1(&self) -> bool { - *self == Mr1i::Mr1i1 - } -} -#[doc = "Field `MR1I` writer - Interrupt on MR1"] -pub type Mr1iW<'a, REG> = crate::BitWriter<'a, REG, Mr1i>; -impl<'a, REG> Mr1iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generate"] - #[inline(always)] - pub fn mr1i_0(self) -> &'a mut crate::W { - self.variant(Mr1i::Mr1i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn mr1i_1(self) -> &'a mut crate::W { - self.variant(Mr1i::Mr1i1) - } -} -#[doc = "Reset on MR1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr1r { - #[doc = "0: Does not reset"] - Mr1r0 = 0, - #[doc = "1: Resets"] - Mr1r1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr1r) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR1R` reader - Reset on MR1"] -pub type Mr1rR = crate::BitReader; -impl Mr1rR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr1r { - match self.bits { - false => Mr1r::Mr1r0, - true => Mr1r::Mr1r1, - } - } - #[doc = "Does not reset"] - #[inline(always)] - pub fn is_mr1r_0(&self) -> bool { - *self == Mr1r::Mr1r0 - } - #[doc = "Resets"] - #[inline(always)] - pub fn is_mr1r_1(&self) -> bool { - *self == Mr1r::Mr1r1 - } -} -#[doc = "Field `MR1R` writer - Reset on MR1"] -pub type Mr1rW<'a, REG> = crate::BitWriter<'a, REG, Mr1r>; -impl<'a, REG> Mr1rW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reset"] - #[inline(always)] - pub fn mr1r_0(self) -> &'a mut crate::W { - self.variant(Mr1r::Mr1r0) - } - #[doc = "Resets"] - #[inline(always)] - pub fn mr1r_1(self) -> &'a mut crate::W { - self.variant(Mr1r::Mr1r1) - } -} -#[doc = "Stop on MR1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr1s { - #[doc = "0: Does not stop"] - Mris0 = 0, - #[doc = "1: Stops"] - Mris1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr1s) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR1S` reader - Stop on MR1"] -pub type Mr1sR = crate::BitReader; -impl Mr1sR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr1s { - match self.bits { - false => Mr1s::Mris0, - true => Mr1s::Mris1, - } - } - #[doc = "Does not stop"] - #[inline(always)] - pub fn is_mris_0(&self) -> bool { - *self == Mr1s::Mris0 - } - #[doc = "Stops"] - #[inline(always)] - pub fn is_mris_1(&self) -> bool { - *self == Mr1s::Mris1 - } -} -#[doc = "Field `MR1S` writer - Stop on MR1"] -pub type Mr1sW<'a, REG> = crate::BitWriter<'a, REG, Mr1s>; -impl<'a, REG> Mr1sW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not stop"] - #[inline(always)] - pub fn mris_0(self) -> &'a mut crate::W { - self.variant(Mr1s::Mris0) - } - #[doc = "Stops"] - #[inline(always)] - pub fn mris_1(self) -> &'a mut crate::W { - self.variant(Mr1s::Mris1) - } -} -#[doc = "Interrupt on MR2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr2i { - #[doc = "0: Does not generate"] - Mr2i0 = 0, - #[doc = "1: Generates"] - Mr2i1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr2i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR2I` reader - Interrupt on MR2"] -pub type Mr2iR = crate::BitReader; -impl Mr2iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr2i { - match self.bits { - false => Mr2i::Mr2i0, - true => Mr2i::Mr2i1, - } - } - #[doc = "Does not generate"] - #[inline(always)] - pub fn is_mr2i_0(&self) -> bool { - *self == Mr2i::Mr2i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_mr2i_1(&self) -> bool { - *self == Mr2i::Mr2i1 - } -} -#[doc = "Field `MR2I` writer - Interrupt on MR2"] -pub type Mr2iW<'a, REG> = crate::BitWriter<'a, REG, Mr2i>; -impl<'a, REG> Mr2iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generate"] - #[inline(always)] - pub fn mr2i_0(self) -> &'a mut crate::W { - self.variant(Mr2i::Mr2i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn mr2i_1(self) -> &'a mut crate::W { - self.variant(Mr2i::Mr2i1) - } -} -#[doc = "Reset on MR2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr2r { - #[doc = "0: Does not reset"] - Mr2r0 = 0, - #[doc = "1: Resets"] - Mr2r1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr2r) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR2R` reader - Reset on MR2"] -pub type Mr2rR = crate::BitReader; -impl Mr2rR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr2r { - match self.bits { - false => Mr2r::Mr2r0, - true => Mr2r::Mr2r1, - } - } - #[doc = "Does not reset"] - #[inline(always)] - pub fn is_mr2r_0(&self) -> bool { - *self == Mr2r::Mr2r0 - } - #[doc = "Resets"] - #[inline(always)] - pub fn is_mr2r_1(&self) -> bool { - *self == Mr2r::Mr2r1 - } -} -#[doc = "Field `MR2R` writer - Reset on MR2"] -pub type Mr2rW<'a, REG> = crate::BitWriter<'a, REG, Mr2r>; -impl<'a, REG> Mr2rW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reset"] - #[inline(always)] - pub fn mr2r_0(self) -> &'a mut crate::W { - self.variant(Mr2r::Mr2r0) - } - #[doc = "Resets"] - #[inline(always)] - pub fn mr2r_1(self) -> &'a mut crate::W { - self.variant(Mr2r::Mr2r1) - } -} -#[doc = "Stop on MR2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr2s { - #[doc = "0: Does not stop"] - Mr2s0 = 0, - #[doc = "1: Stops"] - Mr2s1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr2s) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR2S` reader - Stop on MR2"] -pub type Mr2sR = crate::BitReader; -impl Mr2sR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr2s { - match self.bits { - false => Mr2s::Mr2s0, - true => Mr2s::Mr2s1, - } - } - #[doc = "Does not stop"] - #[inline(always)] - pub fn is_mr2s_0(&self) -> bool { - *self == Mr2s::Mr2s0 - } - #[doc = "Stops"] - #[inline(always)] - pub fn is_mr2s_1(&self) -> bool { - *self == Mr2s::Mr2s1 - } -} -#[doc = "Field `MR2S` writer - Stop on MR2"] -pub type Mr2sW<'a, REG> = crate::BitWriter<'a, REG, Mr2s>; -impl<'a, REG> Mr2sW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not stop"] - #[inline(always)] - pub fn mr2s_0(self) -> &'a mut crate::W { - self.variant(Mr2s::Mr2s0) - } - #[doc = "Stops"] - #[inline(always)] - pub fn mr2s_1(self) -> &'a mut crate::W { - self.variant(Mr2s::Mr2s1) - } -} -#[doc = "Interrupt on MR3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr3i { - #[doc = "0: Does not generate"] - Mr3i0 = 0, - #[doc = "1: Generates"] - Mr3i1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr3i) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR3I` reader - Interrupt on MR3"] -pub type Mr3iR = crate::BitReader; -impl Mr3iR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr3i { - match self.bits { - false => Mr3i::Mr3i0, - true => Mr3i::Mr3i1, - } - } - #[doc = "Does not generate"] - #[inline(always)] - pub fn is_mr3i_0(&self) -> bool { - *self == Mr3i::Mr3i0 - } - #[doc = "Generates"] - #[inline(always)] - pub fn is_mr3i_1(&self) -> bool { - *self == Mr3i::Mr3i1 - } -} -#[doc = "Field `MR3I` writer - Interrupt on MR3"] -pub type Mr3iW<'a, REG> = crate::BitWriter<'a, REG, Mr3i>; -impl<'a, REG> Mr3iW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not generate"] - #[inline(always)] - pub fn mr3i_0(self) -> &'a mut crate::W { - self.variant(Mr3i::Mr3i0) - } - #[doc = "Generates"] - #[inline(always)] - pub fn mr3i_1(self) -> &'a mut crate::W { - self.variant(Mr3i::Mr3i1) - } -} -#[doc = "Reset on MR3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr3r { - #[doc = "0: Does not reset"] - Mr3r0 = 0, - #[doc = "1: Resets"] - Mr3r1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr3r) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR3R` reader - Reset on MR3"] -pub type Mr3rR = crate::BitReader; -impl Mr3rR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr3r { - match self.bits { - false => Mr3r::Mr3r0, - true => Mr3r::Mr3r1, - } - } - #[doc = "Does not reset"] - #[inline(always)] - pub fn is_mr3r_0(&self) -> bool { - *self == Mr3r::Mr3r0 - } - #[doc = "Resets"] - #[inline(always)] - pub fn is_mr3r_1(&self) -> bool { - *self == Mr3r::Mr3r1 - } -} -#[doc = "Field `MR3R` writer - Reset on MR3"] -pub type Mr3rW<'a, REG> = crate::BitWriter<'a, REG, Mr3r>; -impl<'a, REG> Mr3rW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reset"] - #[inline(always)] - pub fn mr3r_0(self) -> &'a mut crate::W { - self.variant(Mr3r::Mr3r0) - } - #[doc = "Resets"] - #[inline(always)] - pub fn mr3r_1(self) -> &'a mut crate::W { - self.variant(Mr3r::Mr3r1) - } -} -#[doc = "Stop on MR3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr3s { - #[doc = "0: Does not stop"] - Mr3s0 = 0, - #[doc = "1: Stops"] - Mr3s1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr3s) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR3S` reader - Stop on MR3"] -pub type Mr3sR = crate::BitReader; -impl Mr3sR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr3s { - match self.bits { - false => Mr3s::Mr3s0, - true => Mr3s::Mr3s1, - } - } - #[doc = "Does not stop"] - #[inline(always)] - pub fn is_mr3s_0(&self) -> bool { - *self == Mr3s::Mr3s0 - } - #[doc = "Stops"] - #[inline(always)] - pub fn is_mr3s_1(&self) -> bool { - *self == Mr3s::Mr3s1 - } -} -#[doc = "Field `MR3S` writer - Stop on MR3"] -pub type Mr3sW<'a, REG> = crate::BitWriter<'a, REG, Mr3s>; -impl<'a, REG> Mr3sW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not stop"] - #[inline(always)] - pub fn mr3s_0(self) -> &'a mut crate::W { - self.variant(Mr3s::Mr3s0) - } - #[doc = "Stops"] - #[inline(always)] - pub fn mr3s_1(self) -> &'a mut crate::W { - self.variant(Mr3s::Mr3s1) - } -} -#[doc = "Reload MR\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr0rl { - #[doc = "0: Does not reload"] - Mr0rl0 = 0, - #[doc = "1: Reloads"] - Mr0rl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr0rl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR0RL` reader - Reload MR"] -pub type Mr0rlR = crate::BitReader; -impl Mr0rlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr0rl { - match self.bits { - false => Mr0rl::Mr0rl0, - true => Mr0rl::Mr0rl1, - } - } - #[doc = "Does not reload"] - #[inline(always)] - pub fn is_mr0rl_0(&self) -> bool { - *self == Mr0rl::Mr0rl0 - } - #[doc = "Reloads"] - #[inline(always)] - pub fn is_mr0rl_1(&self) -> bool { - *self == Mr0rl::Mr0rl1 - } -} -#[doc = "Field `MR0RL` writer - Reload MR"] -pub type Mr0rlW<'a, REG> = crate::BitWriter<'a, REG, Mr0rl>; -impl<'a, REG> Mr0rlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reload"] - #[inline(always)] - pub fn mr0rl_0(self) -> &'a mut crate::W { - self.variant(Mr0rl::Mr0rl0) - } - #[doc = "Reloads"] - #[inline(always)] - pub fn mr0rl_1(self) -> &'a mut crate::W { - self.variant(Mr0rl::Mr0rl1) - } -} -#[doc = "Reload MR\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr1rl { - #[doc = "0: Does not reload"] - Mr1rl0 = 0, - #[doc = "1: Reloads"] - Mr1rl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr1rl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR1RL` reader - Reload MR"] -pub type Mr1rlR = crate::BitReader; -impl Mr1rlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr1rl { - match self.bits { - false => Mr1rl::Mr1rl0, - true => Mr1rl::Mr1rl1, - } - } - #[doc = "Does not reload"] - #[inline(always)] - pub fn is_mr1rl_0(&self) -> bool { - *self == Mr1rl::Mr1rl0 - } - #[doc = "Reloads"] - #[inline(always)] - pub fn is_mr1rl_1(&self) -> bool { - *self == Mr1rl::Mr1rl1 - } -} -#[doc = "Field `MR1RL` writer - Reload MR"] -pub type Mr1rlW<'a, REG> = crate::BitWriter<'a, REG, Mr1rl>; -impl<'a, REG> Mr1rlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reload"] - #[inline(always)] - pub fn mr1rl_0(self) -> &'a mut crate::W { - self.variant(Mr1rl::Mr1rl0) - } - #[doc = "Reloads"] - #[inline(always)] - pub fn mr1rl_1(self) -> &'a mut crate::W { - self.variant(Mr1rl::Mr1rl1) - } -} -#[doc = "Reload MR\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr2rl { - #[doc = "0: Does not reload"] - Mr2rl0 = 0, - #[doc = "1: Reloads"] - Mr2rl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr2rl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR2RL` reader - Reload MR"] -pub type Mr2rlR = crate::BitReader; -impl Mr2rlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr2rl { - match self.bits { - false => Mr2rl::Mr2rl0, - true => Mr2rl::Mr2rl1, - } - } - #[doc = "Does not reload"] - #[inline(always)] - pub fn is_mr2rl_0(&self) -> bool { - *self == Mr2rl::Mr2rl0 - } - #[doc = "Reloads"] - #[inline(always)] - pub fn is_mr2rl_1(&self) -> bool { - *self == Mr2rl::Mr2rl1 - } -} -#[doc = "Field `MR2RL` writer - Reload MR"] -pub type Mr2rlW<'a, REG> = crate::BitWriter<'a, REG, Mr2rl>; -impl<'a, REG> Mr2rlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reload"] - #[inline(always)] - pub fn mr2rl_0(self) -> &'a mut crate::W { - self.variant(Mr2rl::Mr2rl0) - } - #[doc = "Reloads"] - #[inline(always)] - pub fn mr2rl_1(self) -> &'a mut crate::W { - self.variant(Mr2rl::Mr2rl1) - } -} -#[doc = "Reload MR\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mr3rl { - #[doc = "0: Does not reload"] - Mr3rl0 = 0, - #[doc = "1: Reloads"] - Mr3rl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mr3rl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MR3RL` reader - Reload MR"] -pub type Mr3rlR = crate::BitReader; -impl Mr3rlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mr3rl { - match self.bits { - false => Mr3rl::Mr3rl0, - true => Mr3rl::Mr3rl1, - } - } - #[doc = "Does not reload"] - #[inline(always)] - pub fn is_mr3rl_0(&self) -> bool { - *self == Mr3rl::Mr3rl0 - } - #[doc = "Reloads"] - #[inline(always)] - pub fn is_mr3rl_1(&self) -> bool { - *self == Mr3rl::Mr3rl1 - } -} -#[doc = "Field `MR3RL` writer - Reload MR"] -pub type Mr3rlW<'a, REG> = crate::BitWriter<'a, REG, Mr3rl>; -impl<'a, REG> Mr3rlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not reload"] - #[inline(always)] - pub fn mr3rl_0(self) -> &'a mut crate::W { - self.variant(Mr3rl::Mr3rl0) - } - #[doc = "Reloads"] - #[inline(always)] - pub fn mr3rl_1(self) -> &'a mut crate::W { - self.variant(Mr3rl::Mr3rl1) - } -} -impl R { - #[doc = "Bit 0 - Interrupt on MR0"] - #[inline(always)] - pub fn mr0i(&self) -> Mr0iR { - Mr0iR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Reset on MR0"] - #[inline(always)] - pub fn mr0r(&self) -> Mr0rR { - Mr0rR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Stop on MR0"] - #[inline(always)] - pub fn mr0s(&self) -> Mr0sR { - Mr0sR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Interrupt on MR1"] - #[inline(always)] - pub fn mr1i(&self) -> Mr1iR { - Mr1iR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Reset on MR1"] - #[inline(always)] - pub fn mr1r(&self) -> Mr1rR { - Mr1rR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Stop on MR1"] - #[inline(always)] - pub fn mr1s(&self) -> Mr1sR { - Mr1sR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Interrupt on MR2"] - #[inline(always)] - pub fn mr2i(&self) -> Mr2iR { - Mr2iR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Reset on MR2"] - #[inline(always)] - pub fn mr2r(&self) -> Mr2rR { - Mr2rR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Stop on MR2"] - #[inline(always)] - pub fn mr2s(&self) -> Mr2sR { - Mr2sR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Interrupt on MR3"] - #[inline(always)] - pub fn mr3i(&self) -> Mr3iR { - Mr3iR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Reset on MR3"] - #[inline(always)] - pub fn mr3r(&self) -> Mr3rR { - Mr3rR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Stop on MR3"] - #[inline(always)] - pub fn mr3s(&self) -> Mr3sR { - Mr3sR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 24 - Reload MR"] - #[inline(always)] - pub fn mr0rl(&self) -> Mr0rlR { - Mr0rlR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Reload MR"] - #[inline(always)] - pub fn mr1rl(&self) -> Mr1rlR { - Mr1rlR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Reload MR"] - #[inline(always)] - pub fn mr2rl(&self) -> Mr2rlR { - Mr2rlR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Reload MR"] - #[inline(always)] - pub fn mr3rl(&self) -> Mr3rlR { - Mr3rlR::new(((self.bits >> 27) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Interrupt on MR0"] - #[inline(always)] - pub fn mr0i(&mut self) -> Mr0iW { - Mr0iW::new(self, 0) - } - #[doc = "Bit 1 - Reset on MR0"] - #[inline(always)] - pub fn mr0r(&mut self) -> Mr0rW { - Mr0rW::new(self, 1) - } - #[doc = "Bit 2 - Stop on MR0"] - #[inline(always)] - pub fn mr0s(&mut self) -> Mr0sW { - Mr0sW::new(self, 2) - } - #[doc = "Bit 3 - Interrupt on MR1"] - #[inline(always)] - pub fn mr1i(&mut self) -> Mr1iW { - Mr1iW::new(self, 3) - } - #[doc = "Bit 4 - Reset on MR1"] - #[inline(always)] - pub fn mr1r(&mut self) -> Mr1rW { - Mr1rW::new(self, 4) - } - #[doc = "Bit 5 - Stop on MR1"] - #[inline(always)] - pub fn mr1s(&mut self) -> Mr1sW { - Mr1sW::new(self, 5) - } - #[doc = "Bit 6 - Interrupt on MR2"] - #[inline(always)] - pub fn mr2i(&mut self) -> Mr2iW { - Mr2iW::new(self, 6) - } - #[doc = "Bit 7 - Reset on MR2"] - #[inline(always)] - pub fn mr2r(&mut self) -> Mr2rW { - Mr2rW::new(self, 7) - } - #[doc = "Bit 8 - Stop on MR2"] - #[inline(always)] - pub fn mr2s(&mut self) -> Mr2sW { - Mr2sW::new(self, 8) - } - #[doc = "Bit 9 - Interrupt on MR3"] - #[inline(always)] - pub fn mr3i(&mut self) -> Mr3iW { - Mr3iW::new(self, 9) - } - #[doc = "Bit 10 - Reset on MR3"] - #[inline(always)] - pub fn mr3r(&mut self) -> Mr3rW { - Mr3rW::new(self, 10) - } - #[doc = "Bit 11 - Stop on MR3"] - #[inline(always)] - pub fn mr3s(&mut self) -> Mr3sW { - Mr3sW::new(self, 11) - } - #[doc = "Bit 24 - Reload MR"] - #[inline(always)] - pub fn mr0rl(&mut self) -> Mr0rlW { - Mr0rlW::new(self, 24) - } - #[doc = "Bit 25 - Reload MR"] - #[inline(always)] - pub fn mr1rl(&mut self) -> Mr1rlW { - Mr1rlW::new(self, 25) - } - #[doc = "Bit 26 - Reload MR"] - #[inline(always)] - pub fn mr2rl(&mut self) -> Mr2rlW { - Mr2rlW::new(self, 26) - } - #[doc = "Bit 27 - Reload MR"] - #[inline(always)] - pub fn mr3rl(&mut self) -> Mr3rlW { - Mr3rlW::new(self, 27) - } -} -#[doc = "Match Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct McrSpec; -impl crate::RegisterSpec for McrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] -impl crate::Readable for McrSpec {} -#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] -impl crate::Writable for McrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCR to value 0"] -impl crate::Resettable for McrSpec {} diff --git a/mcxa276-pac/src/ctimer0/mr.rs b/mcxa276-pac/src/ctimer0/mr.rs deleted file mode 100644 index 6b5bc4957..000000000 --- a/mcxa276-pac/src/ctimer0/mr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `MR[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `MR[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `MATCH` reader - Timer Counter Match Value"] -pub type MatchR = crate::FieldReader; -#[doc = "Field `MATCH` writer - Timer Counter Match Value"] -pub type MatchW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Timer Counter Match Value"] - #[inline(always)] - pub fn match_(&self) -> MatchR { - MatchR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Timer Counter Match Value"] - #[inline(always)] - pub fn match_(&mut self) -> MatchW { - MatchW::new(self, 0) - } -} -#[doc = "Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrSpec; -impl crate::RegisterSpec for MrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mr::R`](R) reader structure"] -impl crate::Readable for MrSpec {} -#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] -impl crate::Writable for MrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MR[%s] to value 0"] -impl crate::Resettable for MrSpec {} diff --git a/mcxa276-pac/src/ctimer0/msr.rs b/mcxa276-pac/src/ctimer0/msr.rs deleted file mode 100644 index 3062f4419..000000000 --- a/mcxa276-pac/src/ctimer0/msr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `MSR[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `MSR[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `MATCH_SHADOW` reader - Timer Counter Match Shadow Value"] -pub type MatchShadowR = crate::FieldReader; -#[doc = "Field `MATCH_SHADOW` writer - Timer Counter Match Shadow Value"] -pub type MatchShadowW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Timer Counter Match Shadow Value"] - #[inline(always)] - pub fn match_shadow(&self) -> MatchShadowR { - MatchShadowR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Timer Counter Match Shadow Value"] - #[inline(always)] - pub fn match_shadow(&mut self) -> MatchShadowW { - MatchShadowW::new(self, 0) - } -} -#[doc = "Match Shadow\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MsrSpec; -impl crate::RegisterSpec for MsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`msr::R`](R) reader structure"] -impl crate::Readable for MsrSpec {} -#[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"] -impl crate::Writable for MsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MSR[%s] to value 0"] -impl crate::Resettable for MsrSpec {} diff --git a/mcxa276-pac/src/ctimer0/pc.rs b/mcxa276-pac/src/ctimer0/pc.rs deleted file mode 100644 index a9ab5d2b6..000000000 --- a/mcxa276-pac/src/ctimer0/pc.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PC` reader"] -pub type R = crate::R; -#[doc = "Register `PC` writer"] -pub type W = crate::W; -#[doc = "Field `PCVAL` reader - Prescale Counter Value"] -pub type PcvalR = crate::FieldReader; -#[doc = "Field `PCVAL` writer - Prescale Counter Value"] -pub type PcvalW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Prescale Counter Value"] - #[inline(always)] - pub fn pcval(&self) -> PcvalR { - PcvalR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Prescale Counter Value"] - #[inline(always)] - pub fn pcval(&mut self) -> PcvalW { - PcvalW::new(self, 0) - } -} -#[doc = "Prescale Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PcSpec; -impl crate::RegisterSpec for PcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pc::R`](R) reader structure"] -impl crate::Readable for PcSpec {} -#[doc = "`write(|w| ..)` method takes [`pc::W`](W) writer structure"] -impl crate::Writable for PcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PC to value 0"] -impl crate::Resettable for PcSpec {} diff --git a/mcxa276-pac/src/ctimer0/pr.rs b/mcxa276-pac/src/ctimer0/pr.rs deleted file mode 100644 index 03868904c..000000000 --- a/mcxa276-pac/src/ctimer0/pr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PR` reader"] -pub type R = crate::R; -#[doc = "Register `PR` writer"] -pub type W = crate::W; -#[doc = "Field `PRVAL` reader - Prescale Reload Value"] -pub type PrvalR = crate::FieldReader; -#[doc = "Field `PRVAL` writer - Prescale Reload Value"] -pub type PrvalW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Prescale Reload Value"] - #[inline(always)] - pub fn prval(&self) -> PrvalR { - PrvalR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Prescale Reload Value"] - #[inline(always)] - pub fn prval(&mut self) -> PrvalW { - PrvalW::new(self, 0) - } -} -#[doc = "Prescale\n\nYou can [`read`](crate::Reg::read) this register and get [`pr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PrSpec; -impl crate::RegisterSpec for PrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pr::R`](R) reader structure"] -impl crate::Readable for PrSpec {} -#[doc = "`write(|w| ..)` method takes [`pr::W`](W) writer structure"] -impl crate::Writable for PrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PR to value 0"] -impl crate::Resettable for PrSpec {} diff --git a/mcxa276-pac/src/ctimer0/pwmc.rs b/mcxa276-pac/src/ctimer0/pwmc.rs deleted file mode 100644 index f285983f1..000000000 --- a/mcxa276-pac/src/ctimer0/pwmc.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `PWMC` reader"] -pub type R = crate::R; -#[doc = "Register `PWMC` writer"] -pub type W = crate::W; -#[doc = "PWM Mode Enable for Channel 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwmen0 { - #[doc = "0: Disable"] - Match = 0, - #[doc = "1: Enable"] - Pwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwmen0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWMEN0` reader - PWM Mode Enable for Channel 0"] -pub type Pwmen0R = crate::BitReader; -impl Pwmen0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmen0 { - match self.bits { - false => Pwmen0::Match, - true => Pwmen0::Pwm, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Pwmen0::Match - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_pwm(&self) -> bool { - *self == Pwmen0::Pwm - } -} -#[doc = "Field `PWMEN0` writer - PWM Mode Enable for Channel 0"] -pub type Pwmen0W<'a, REG> = crate::BitWriter<'a, REG, Pwmen0>; -impl<'a, REG> Pwmen0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Pwmen0::Match) - } - #[doc = "Enable"] - #[inline(always)] - pub fn pwm(self) -> &'a mut crate::W { - self.variant(Pwmen0::Pwm) - } -} -#[doc = "PWM Mode Enable for Channel 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwmen1 { - #[doc = "0: Disable"] - Match = 0, - #[doc = "1: Enable"] - Pwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwmen1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWMEN1` reader - PWM Mode Enable for Channel 1"] -pub type Pwmen1R = crate::BitReader; -impl Pwmen1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmen1 { - match self.bits { - false => Pwmen1::Match, - true => Pwmen1::Pwm, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Pwmen1::Match - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_pwm(&self) -> bool { - *self == Pwmen1::Pwm - } -} -#[doc = "Field `PWMEN1` writer - PWM Mode Enable for Channel 1"] -pub type Pwmen1W<'a, REG> = crate::BitWriter<'a, REG, Pwmen1>; -impl<'a, REG> Pwmen1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Pwmen1::Match) - } - #[doc = "Enable"] - #[inline(always)] - pub fn pwm(self) -> &'a mut crate::W { - self.variant(Pwmen1::Pwm) - } -} -#[doc = "PWM Mode Enable for Channel 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwmen2 { - #[doc = "0: Disable"] - Match = 0, - #[doc = "1: Enable"] - Pwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwmen2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWMEN2` reader - PWM Mode Enable for Channel 2"] -pub type Pwmen2R = crate::BitReader; -impl Pwmen2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmen2 { - match self.bits { - false => Pwmen2::Match, - true => Pwmen2::Pwm, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Pwmen2::Match - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_pwm(&self) -> bool { - *self == Pwmen2::Pwm - } -} -#[doc = "Field `PWMEN2` writer - PWM Mode Enable for Channel 2"] -pub type Pwmen2W<'a, REG> = crate::BitWriter<'a, REG, Pwmen2>; -impl<'a, REG> Pwmen2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Pwmen2::Match) - } - #[doc = "Enable"] - #[inline(always)] - pub fn pwm(self) -> &'a mut crate::W { - self.variant(Pwmen2::Pwm) - } -} -#[doc = "PWM Mode Enable for Channel 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwmen3 { - #[doc = "0: Disable"] - Match = 0, - #[doc = "1: Enable"] - Pwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwmen3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWMEN3` reader - PWM Mode Enable for Channel 3"] -pub type Pwmen3R = crate::BitReader; -impl Pwmen3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmen3 { - match self.bits { - false => Pwmen3::Match, - true => Pwmen3::Pwm, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Pwmen3::Match - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_pwm(&self) -> bool { - *self == Pwmen3::Pwm - } -} -#[doc = "Field `PWMEN3` writer - PWM Mode Enable for Channel 3"] -pub type Pwmen3W<'a, REG> = crate::BitWriter<'a, REG, Pwmen3>; -impl<'a, REG> Pwmen3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Pwmen3::Match) - } - #[doc = "Enable"] - #[inline(always)] - pub fn pwm(self) -> &'a mut crate::W { - self.variant(Pwmen3::Pwm) - } -} -impl R { - #[doc = "Bit 0 - PWM Mode Enable for Channel 0"] - #[inline(always)] - pub fn pwmen0(&self) -> Pwmen0R { - Pwmen0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - PWM Mode Enable for Channel 1"] - #[inline(always)] - pub fn pwmen1(&self) -> Pwmen1R { - Pwmen1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - PWM Mode Enable for Channel 2"] - #[inline(always)] - pub fn pwmen2(&self) -> Pwmen2R { - Pwmen2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - PWM Mode Enable for Channel 3"] - #[inline(always)] - pub fn pwmen3(&self) -> Pwmen3R { - Pwmen3R::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - PWM Mode Enable for Channel 0"] - #[inline(always)] - pub fn pwmen0(&mut self) -> Pwmen0W { - Pwmen0W::new(self, 0) - } - #[doc = "Bit 1 - PWM Mode Enable for Channel 1"] - #[inline(always)] - pub fn pwmen1(&mut self) -> Pwmen1W { - Pwmen1W::new(self, 1) - } - #[doc = "Bit 2 - PWM Mode Enable for Channel 2"] - #[inline(always)] - pub fn pwmen2(&mut self) -> Pwmen2W { - Pwmen2W::new(self, 2) - } - #[doc = "Bit 3 - PWM Mode Enable for Channel 3"] - #[inline(always)] - pub fn pwmen3(&mut self) -> Pwmen3W { - Pwmen3W::new(self, 3) - } -} -#[doc = "PWM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PwmcSpec; -impl crate::RegisterSpec for PwmcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pwmc::R`](R) reader structure"] -impl crate::Readable for PwmcSpec {} -#[doc = "`write(|w| ..)` method takes [`pwmc::W`](W) writer structure"] -impl crate::Writable for PwmcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PWMC to value 0"] -impl crate::Resettable for PwmcSpec {} diff --git a/mcxa276-pac/src/ctimer0/tc.rs b/mcxa276-pac/src/ctimer0/tc.rs deleted file mode 100644 index 95f86f58c..000000000 --- a/mcxa276-pac/src/ctimer0/tc.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TC` reader"] -pub type R = crate::R; -#[doc = "Register `TC` writer"] -pub type W = crate::W; -#[doc = "Field `TCVAL` reader - Timer Counter Value"] -pub type TcvalR = crate::FieldReader; -#[doc = "Field `TCVAL` writer - Timer Counter Value"] -pub type TcvalW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Timer Counter Value"] - #[inline(always)] - pub fn tcval(&self) -> TcvalR { - TcvalR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Timer Counter Value"] - #[inline(always)] - pub fn tcval(&mut self) -> TcvalW { - TcvalW::new(self, 0) - } -} -#[doc = "Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcSpec; -impl crate::RegisterSpec for TcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tc::R`](R) reader structure"] -impl crate::Readable for TcSpec {} -#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] -impl crate::Writable for TcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TC to value 0"] -impl crate::Resettable for TcSpec {} diff --git a/mcxa276-pac/src/ctimer0/tcr.rs b/mcxa276-pac/src/ctimer0/tcr.rs deleted file mode 100644 index 5b4dc8770..000000000 --- a/mcxa276-pac/src/ctimer0/tcr.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `TCR` reader"] -pub type R = crate::R; -#[doc = "Register `TCR` writer"] -pub type W = crate::W; -#[doc = "Counter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cen { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CEN` reader - Counter Enable"] -pub type CenR = crate::BitReader; -impl CenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cen { - match self.bits { - false => Cen::Disabled, - true => Cen::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cen::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cen::Enabled - } -} -#[doc = "Field `CEN` writer - Counter Enable"] -pub type CenW<'a, REG> = crate::BitWriter<'a, REG, Cen>; -impl<'a, REG> CenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cen::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cen::Enabled) - } -} -#[doc = "Counter Reset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crst { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRST` reader - Counter Reset Enable"] -pub type CrstR = crate::BitReader; -impl CrstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crst { - match self.bits { - false => Crst::Disabled, - true => Crst::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Crst::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Crst::Enabled - } -} -#[doc = "Field `CRST` writer - Counter Reset Enable"] -pub type CrstW<'a, REG> = crate::BitWriter<'a, REG, Crst>; -impl<'a, REG> CrstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Crst::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Crst::Enabled) - } -} -#[doc = "Allow Global Count Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Agcen { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Agcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AGCEN` reader - Allow Global Count Enable"] -pub type AgcenR = crate::BitReader; -impl AgcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Agcen { - match self.bits { - false => Agcen::Disable, - true => Agcen::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Agcen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Agcen::Enable - } -} -#[doc = "Field `AGCEN` writer - Allow Global Count Enable"] -pub type AgcenW<'a, REG> = crate::BitWriter<'a, REG, Agcen>; -impl<'a, REG> AgcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Agcen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Agcen::Enable) - } -} -#[doc = "Allow Trigger Count Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Atcen { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Atcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ATCEN` reader - Allow Trigger Count Enable"] -pub type AtcenR = crate::BitReader; -impl AtcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Atcen { - match self.bits { - false => Atcen::Disable, - true => Atcen::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Atcen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Atcen::Enable - } -} -#[doc = "Field `ATCEN` writer - Allow Trigger Count Enable"] -pub type AtcenW<'a, REG> = crate::BitWriter<'a, REG, Atcen>; -impl<'a, REG> AtcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Atcen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Atcen::Enable) - } -} -impl R { - #[doc = "Bit 0 - Counter Enable"] - #[inline(always)] - pub fn cen(&self) -> CenR { - CenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Counter Reset Enable"] - #[inline(always)] - pub fn crst(&self) -> CrstR { - CrstR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 4 - Allow Global Count Enable"] - #[inline(always)] - pub fn agcen(&self) -> AgcenR { - AgcenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Allow Trigger Count Enable"] - #[inline(always)] - pub fn atcen(&self) -> AtcenR { - AtcenR::new(((self.bits >> 5) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Counter Enable"] - #[inline(always)] - pub fn cen(&mut self) -> CenW { - CenW::new(self, 0) - } - #[doc = "Bit 1 - Counter Reset Enable"] - #[inline(always)] - pub fn crst(&mut self) -> CrstW { - CrstW::new(self, 1) - } - #[doc = "Bit 4 - Allow Global Count Enable"] - #[inline(always)] - pub fn agcen(&mut self) -> AgcenW { - AgcenW::new(self, 4) - } - #[doc = "Bit 5 - Allow Trigger Count Enable"] - #[inline(always)] - pub fn atcen(&mut self) -> AtcenW { - AtcenW::new(self, 5) - } -} -#[doc = "Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcrSpec; -impl crate::RegisterSpec for TcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] -impl crate::Readable for TcrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] -impl crate::Writable for TcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCR to value 0"] -impl crate::Resettable for TcrSpec {} diff --git a/mcxa276-pac/src/dac0.rs b/mcxa276-pac/src/dac0.rs deleted file mode 100644 index b5ff97eab..000000000 --- a/mcxa276-pac/src/dac0.rs +++ /dev/null @@ -1,138 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - data: Data, - gcr: Gcr, - fcr: Fcr, - fpr: Fpr, - fsr: Fsr, - ier: Ier, - der: Der, - rcr: Rcr, - tcr: Tcr, - pcr: Pcr, -} -impl RegisterBlock { - #[doc = "0x00 - Version Identifier"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x08 - Data"] - #[inline(always)] - pub const fn data(&self) -> &Data { - &self.data - } - #[doc = "0x0c - Global Control"] - #[inline(always)] - pub const fn gcr(&self) -> &Gcr { - &self.gcr - } - #[doc = "0x10 - DAC FIFO Control"] - #[inline(always)] - pub const fn fcr(&self) -> &Fcr { - &self.fcr - } - #[doc = "0x14 - DAC FIFO Pointer"] - #[inline(always)] - pub const fn fpr(&self) -> &Fpr { - &self.fpr - } - #[doc = "0x18 - FIFO Status"] - #[inline(always)] - pub const fn fsr(&self) -> &Fsr { - &self.fsr - } - #[doc = "0x1c - Interrupt Enable"] - #[inline(always)] - pub const fn ier(&self) -> &Ier { - &self.ier - } - #[doc = "0x20 - DMA Enable"] - #[inline(always)] - pub const fn der(&self) -> &Der { - &self.der - } - #[doc = "0x24 - Reset Control"] - #[inline(always)] - pub const fn rcr(&self) -> &Rcr { - &self.rcr - } - #[doc = "0x28 - Trigger Control"] - #[inline(always)] - pub const fn tcr(&self) -> &Tcr { - &self.tcr - } - #[doc = "0x2c - Periodic Trigger Control"] - #[inline(always)] - pub const fn pcr(&self) -> &Pcr { - &self.pcr - } -} -#[doc = "VERID (r) register accessor: Version Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version Identifier"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "DATA (rw) register accessor: Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] -#[doc(alias = "DATA")] -pub type Data = crate::Reg; -#[doc = "Data"] -pub mod data; -#[doc = "GCR (rw) register accessor: Global Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr`] module"] -#[doc(alias = "GCR")] -pub type Gcr = crate::Reg; -#[doc = "Global Control"] -pub mod gcr; -#[doc = "FCR (rw) register accessor: DAC FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] -#[doc(alias = "FCR")] -pub type Fcr = crate::Reg; -#[doc = "DAC FIFO Control"] -pub mod fcr; -#[doc = "FPR (r) register accessor: DAC FIFO Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`fpr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpr`] module"] -#[doc(alias = "FPR")] -pub type Fpr = crate::Reg; -#[doc = "DAC FIFO Pointer"] -pub mod fpr; -#[doc = "FSR (rw) register accessor: FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsr`] module"] -#[doc(alias = "FSR")] -pub type Fsr = crate::Reg; -#[doc = "FIFO Status"] -pub mod fsr; -#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] -#[doc(alias = "IER")] -pub type Ier = crate::Reg; -#[doc = "Interrupt Enable"] -pub mod ier; -#[doc = "DER (rw) register accessor: DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@der`] module"] -#[doc(alias = "DER")] -pub type Der = crate::Reg; -#[doc = "DMA Enable"] -pub mod der; -#[doc = "RCR (rw) register accessor: Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcr`] module"] -#[doc(alias = "RCR")] -pub type Rcr = crate::Reg; -#[doc = "Reset Control"] -pub mod rcr; -#[doc = "TCR (rw) register accessor: Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] -#[doc(alias = "TCR")] -pub type Tcr = crate::Reg; -#[doc = "Trigger Control"] -pub mod tcr; -#[doc = "PCR (rw) register accessor: Periodic Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr`] module"] -#[doc(alias = "PCR")] -pub type Pcr = crate::Reg; -#[doc = "Periodic Trigger Control"] -pub mod pcr; diff --git a/mcxa276-pac/src/dac0/data.rs b/mcxa276-pac/src/dac0/data.rs deleted file mode 100644 index 8834695da..000000000 --- a/mcxa276-pac/src/dac0/data.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `DATA` reader"] -pub type R = crate::R; -#[doc = "Register `DATA` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` reader - FIFO Entry or Buffer Entry"] -pub type DataR = crate::FieldReader; -#[doc = "Field `DATA` writer - FIFO Entry or Buffer Entry"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -impl R { - #[doc = "Bits 0:11 - FIFO Entry or Buffer Entry"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0x0fff) as u16) - } -} -impl W { - #[doc = "Bits 0:11 - FIFO Entry or Buffer Entry"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DataSpec; -impl crate::RegisterSpec for DataSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`data::R`](R) reader structure"] -impl crate::Readable for DataSpec {} -#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] -impl crate::Writable for DataSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DATA to value 0"] -impl crate::Resettable for DataSpec {} diff --git a/mcxa276-pac/src/dac0/der.rs b/mcxa276-pac/src/dac0/der.rs deleted file mode 100644 index 98df40938..000000000 --- a/mcxa276-pac/src/dac0/der.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `DER` reader"] -pub type R = crate::R; -#[doc = "Register `DER` writer"] -pub type W = crate::W; -#[doc = "FIFO Empty DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EmptyDmaen { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EmptyDmaen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EMPTY_DMAEN` reader - FIFO Empty DMA Enable"] -pub type EmptyDmaenR = crate::BitReader; -impl EmptyDmaenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EmptyDmaen { - match self.bits { - false => EmptyDmaen::Disabled, - true => EmptyDmaen::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == EmptyDmaen::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == EmptyDmaen::Enabled - } -} -#[doc = "Field `EMPTY_DMAEN` writer - FIFO Empty DMA Enable"] -pub type EmptyDmaenW<'a, REG> = crate::BitWriter<'a, REG, EmptyDmaen>; -impl<'a, REG> EmptyDmaenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(EmptyDmaen::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(EmptyDmaen::Enabled) - } -} -#[doc = "FIFO Watermark DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WmDmaen { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WmDmaen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WM_DMAEN` reader - FIFO Watermark DMA Enable"] -pub type WmDmaenR = crate::BitReader; -impl WmDmaenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WmDmaen { - match self.bits { - false => WmDmaen::Disabled, - true => WmDmaen::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WmDmaen::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WmDmaen::Enabled - } -} -#[doc = "Field `WM_DMAEN` writer - FIFO Watermark DMA Enable"] -pub type WmDmaenW<'a, REG> = crate::BitWriter<'a, REG, WmDmaen>; -impl<'a, REG> WmDmaenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WmDmaen::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WmDmaen::Enabled) - } -} -impl R { - #[doc = "Bit 1 - FIFO Empty DMA Enable"] - #[inline(always)] - pub fn empty_dmaen(&self) -> EmptyDmaenR { - EmptyDmaenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - FIFO Watermark DMA Enable"] - #[inline(always)] - pub fn wm_dmaen(&self) -> WmDmaenR { - WmDmaenR::new(((self.bits >> 2) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - FIFO Empty DMA Enable"] - #[inline(always)] - pub fn empty_dmaen(&mut self) -> EmptyDmaenW { - EmptyDmaenW::new(self, 1) - } - #[doc = "Bit 2 - FIFO Watermark DMA Enable"] - #[inline(always)] - pub fn wm_dmaen(&mut self) -> WmDmaenW { - WmDmaenW::new(self, 2) - } -} -#[doc = "DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DerSpec; -impl crate::RegisterSpec for DerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`der::R`](R) reader structure"] -impl crate::Readable for DerSpec {} -#[doc = "`write(|w| ..)` method takes [`der::W`](W) writer structure"] -impl crate::Writable for DerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DER to value 0"] -impl crate::Resettable for DerSpec {} diff --git a/mcxa276-pac/src/dac0/fcr.rs b/mcxa276-pac/src/dac0/fcr.rs deleted file mode 100644 index 504eb077e..000000000 --- a/mcxa276-pac/src/dac0/fcr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `FCR` reader"] -pub type R = crate::R; -#[doc = "Register `FCR` writer"] -pub type W = crate::W; -#[doc = "Field `WML` reader - Watermark Level"] -pub type WmlR = crate::FieldReader; -#[doc = "Field `WML` writer - Watermark Level"] -pub type WmlW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Watermark Level"] - #[inline(always)] - pub fn wml(&self) -> WmlR { - WmlR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Watermark Level"] - #[inline(always)] - pub fn wml(&mut self) -> WmlW { - WmlW::new(self, 0) - } -} -#[doc = "DAC FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FcrSpec; -impl crate::RegisterSpec for FcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fcr::R`](R) reader structure"] -impl crate::Readable for FcrSpec {} -#[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] -impl crate::Writable for FcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCR to value 0"] -impl crate::Resettable for FcrSpec {} diff --git a/mcxa276-pac/src/dac0/fpr.rs b/mcxa276-pac/src/dac0/fpr.rs deleted file mode 100644 index 0ee0c0cb8..000000000 --- a/mcxa276-pac/src/dac0/fpr.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `FPR` reader"] -pub type R = crate::R; -#[doc = "Field `FIFO_RPT` reader - FIFO Read Pointer"] -pub type FifoRptR = crate::FieldReader; -#[doc = "Field `FIFO_WPT` reader - FIFO Write Pointer"] -pub type FifoWptR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - FIFO Read Pointer"] - #[inline(always)] - pub fn fifo_rpt(&self) -> FifoRptR { - FifoRptR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 16:19 - FIFO Write Pointer"] - #[inline(always)] - pub fn fifo_wpt(&self) -> FifoWptR { - FifoWptR::new(((self.bits >> 16) & 0x0f) as u8) - } -} -#[doc = "DAC FIFO Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`fpr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FprSpec; -impl crate::RegisterSpec for FprSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fpr::R`](R) reader structure"] -impl crate::Readable for FprSpec {} -#[doc = "`reset()` method sets FPR to value 0"] -impl crate::Resettable for FprSpec {} diff --git a/mcxa276-pac/src/dac0/fsr.rs b/mcxa276-pac/src/dac0/fsr.rs deleted file mode 100644 index 2f88b9375..000000000 --- a/mcxa276-pac/src/dac0/fsr.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `FSR` reader"] -pub type R = crate::R; -#[doc = "Register `FSR` writer"] -pub type W = crate::W; -#[doc = "FIFO Full Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Full { - #[doc = "0: Not full"] - NotFull = 0, - #[doc = "1: Full"] - Full = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FULL` reader - FIFO Full Flag"] -pub type FullR = crate::BitReader; -impl FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Full { - match self.bits { - false => Full::NotFull, - true => Full::Full, - } - } - #[doc = "Not full"] - #[inline(always)] - pub fn is_not_full(&self) -> bool { - *self == Full::NotFull - } - #[doc = "Full"] - #[inline(always)] - pub fn is_full(&self) -> bool { - *self == Full::Full - } -} -#[doc = "FIFO Empty Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Empty { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Empty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EMPTY` reader - FIFO Empty Flag"] -pub type EmptyR = crate::BitReader; -impl EmptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Empty { - match self.bits { - false => Empty::NotEmpty, - true => Empty::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Empty::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Empty::Empty - } -} -#[doc = "FIFO Watermark Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wm { - #[doc = "0: Data in FIFO is more than watermark level"] - MoreThanWlevel = 0, - #[doc = "1: Data in FIFO is less than or equal to watermark level"] - LessThanWlevel = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WM` reader - FIFO Watermark Status Flag"] -pub type WmR = crate::BitReader; -impl WmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wm { - match self.bits { - false => Wm::MoreThanWlevel, - true => Wm::LessThanWlevel, - } - } - #[doc = "Data in FIFO is more than watermark level"] - #[inline(always)] - pub fn is_more_than_wlevel(&self) -> bool { - *self == Wm::MoreThanWlevel - } - #[doc = "Data in FIFO is less than or equal to watermark level"] - #[inline(always)] - pub fn is_less_than_wlevel(&self) -> bool { - *self == Wm::LessThanWlevel - } -} -#[doc = "Swing Back One Cycle Complete Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swbk { - #[doc = "0: No swing back cycle has completed since the last time the flag was cleared"] - NoSwing = 0, - #[doc = "1: At least one swing back cycle has occurred since the last time the flag was cleared"] - SwingBack = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swbk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWBK` reader - Swing Back One Cycle Complete Flag"] -pub type SwbkR = crate::BitReader; -impl SwbkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swbk { - match self.bits { - false => Swbk::NoSwing, - true => Swbk::SwingBack, - } - } - #[doc = "No swing back cycle has completed since the last time the flag was cleared"] - #[inline(always)] - pub fn is_no_swing(&self) -> bool { - *self == Swbk::NoSwing - } - #[doc = "At least one swing back cycle has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn is_swing_back(&self) -> bool { - *self == Swbk::SwingBack - } -} -#[doc = "Field `SWBK` writer - Swing Back One Cycle Complete Flag"] -pub type SwbkW<'a, REG> = crate::BitWriter1C<'a, REG, Swbk>; -impl<'a, REG> SwbkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No swing back cycle has completed since the last time the flag was cleared"] - #[inline(always)] - pub fn no_swing(self) -> &'a mut crate::W { - self.variant(Swbk::NoSwing) - } - #[doc = "At least one swing back cycle has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn swing_back(self) -> &'a mut crate::W { - self.variant(Swbk::SwingBack) - } -} -#[doc = "FIFO Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Of { - #[doc = "0: No overflow has occurred since the last time the flag was cleared"] - NoOverflow = 0, - #[doc = "1: At least one FIFO overflow has occurred since the last time the flag was cleared"] - Overflow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Of) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OF` reader - FIFO Overflow Flag"] -pub type OfR = crate::BitReader; -impl OfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Of { - match self.bits { - false => Of::NoOverflow, - true => Of::Overflow, - } - } - #[doc = "No overflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn is_no_overflow(&self) -> bool { - *self == Of::NoOverflow - } - #[doc = "At least one FIFO overflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn is_overflow(&self) -> bool { - *self == Of::Overflow - } -} -#[doc = "Field `OF` writer - FIFO Overflow Flag"] -pub type OfW<'a, REG> = crate::BitWriter1C<'a, REG, Of>; -impl<'a, REG> OfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn no_overflow(self) -> &'a mut crate::W { - self.variant(Of::NoOverflow) - } - #[doc = "At least one FIFO overflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn overflow(self) -> &'a mut crate::W { - self.variant(Of::Overflow) - } -} -#[doc = "FIFO Underflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Uf { - #[doc = "0: No underflow has occurred since the last time the flag was cleared"] - NoUnderflow = 0, - #[doc = "1: At least one trigger underflow has occurred since the last time the flag was cleared"] - Underflow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Uf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UF` reader - FIFO Underflow Flag"] -pub type UfR = crate::BitReader; -impl UfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Uf { - match self.bits { - false => Uf::NoUnderflow, - true => Uf::Underflow, - } - } - #[doc = "No underflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn is_no_underflow(&self) -> bool { - *self == Uf::NoUnderflow - } - #[doc = "At least one trigger underflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn is_underflow(&self) -> bool { - *self == Uf::Underflow - } -} -#[doc = "Field `UF` writer - FIFO Underflow Flag"] -pub type UfW<'a, REG> = crate::BitWriter1C<'a, REG, Uf>; -impl<'a, REG> UfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No underflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn no_underflow(self) -> &'a mut crate::W { - self.variant(Uf::NoUnderflow) - } - #[doc = "At least one trigger underflow has occurred since the last time the flag was cleared"] - #[inline(always)] - pub fn underflow(self) -> &'a mut crate::W { - self.variant(Uf::Underflow) - } -} -#[doc = "Period Trigger Mode Conversion Complete Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptgcoco { - #[doc = "0: Not completed or not started"] - NotStart = 0, - #[doc = "1: Completed"] - Completed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptgcoco) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTGCOCO` reader - Period Trigger Mode Conversion Complete Flag"] -pub type PtgcocoR = crate::BitReader; -impl PtgcocoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptgcoco { - match self.bits { - false => Ptgcoco::NotStart, - true => Ptgcoco::Completed, - } - } - #[doc = "Not completed or not started"] - #[inline(always)] - pub fn is_not_start(&self) -> bool { - *self == Ptgcoco::NotStart - } - #[doc = "Completed"] - #[inline(always)] - pub fn is_completed(&self) -> bool { - *self == Ptgcoco::Completed - } -} -#[doc = "Field `PTGCOCO` writer - Period Trigger Mode Conversion Complete Flag"] -pub type PtgcocoW<'a, REG> = crate::BitWriter1C<'a, REG, Ptgcoco>; -impl<'a, REG> PtgcocoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not completed or not started"] - #[inline(always)] - pub fn not_start(self) -> &'a mut crate::W { - self.variant(Ptgcoco::NotStart) - } - #[doc = "Completed"] - #[inline(always)] - pub fn completed(self) -> &'a mut crate::W { - self.variant(Ptgcoco::Completed) - } -} -impl R { - #[doc = "Bit 0 - FIFO Full Flag"] - #[inline(always)] - pub fn full(&self) -> FullR { - FullR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - FIFO Empty Flag"] - #[inline(always)] - pub fn empty(&self) -> EmptyR { - EmptyR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - FIFO Watermark Status Flag"] - #[inline(always)] - pub fn wm(&self) -> WmR { - WmR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Swing Back One Cycle Complete Flag"] - #[inline(always)] - pub fn swbk(&self) -> SwbkR { - SwbkR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 6 - FIFO Overflow Flag"] - #[inline(always)] - pub fn of(&self) -> OfR { - OfR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - FIFO Underflow Flag"] - #[inline(always)] - pub fn uf(&self) -> UfR { - UfR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Period Trigger Mode Conversion Complete Flag"] - #[inline(always)] - pub fn ptgcoco(&self) -> PtgcocoR { - PtgcocoR::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 3 - Swing Back One Cycle Complete Flag"] - #[inline(always)] - pub fn swbk(&mut self) -> SwbkW { - SwbkW::new(self, 3) - } - #[doc = "Bit 6 - FIFO Overflow Flag"] - #[inline(always)] - pub fn of(&mut self) -> OfW { - OfW::new(self, 6) - } - #[doc = "Bit 7 - FIFO Underflow Flag"] - #[inline(always)] - pub fn uf(&mut self) -> UfW { - UfW::new(self, 7) - } - #[doc = "Bit 8 - Period Trigger Mode Conversion Complete Flag"] - #[inline(always)] - pub fn ptgcoco(&mut self) -> PtgcocoW { - PtgcocoW::new(self, 8) - } -} -#[doc = "FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FsrSpec; -impl crate::RegisterSpec for FsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fsr::R`](R) reader structure"] -impl crate::Readable for FsrSpec {} -#[doc = "`write(|w| ..)` method takes [`fsr::W`](W) writer structure"] -impl crate::Writable for FsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01c8; -} -#[doc = "`reset()` method sets FSR to value 0x02"] -impl crate::Resettable for FsrSpec { - const RESET_VALUE: u32 = 0x02; -} diff --git a/mcxa276-pac/src/dac0/gcr.rs b/mcxa276-pac/src/dac0/gcr.rs deleted file mode 100644 index 0122737b0..000000000 --- a/mcxa276-pac/src/dac0/gcr.rs +++ /dev/null @@ -1,687 +0,0 @@ -#[doc = "Register `GCR` reader"] -pub type R = crate::R; -#[doc = "Register `GCR` writer"] -pub type W = crate::W; -#[doc = "DAC Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dacen { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dacen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DACEN` reader - DAC Enable"] -pub type DacenR = crate::BitReader; -impl DacenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dacen { - match self.bits { - false => Dacen::Disabled, - true => Dacen::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dacen::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dacen::Enabled - } -} -#[doc = "Field `DACEN` writer - DAC Enable"] -pub type DacenW<'a, REG> = crate::BitWriter<'a, REG, Dacen>; -impl<'a, REG> DacenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dacen::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dacen::Enabled) - } -} -#[doc = "DAC Reference Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dacrfs { - #[doc = "0: Selects VREFH0 as the reference voltage."] - Vrefh0 = 0, - #[doc = "1: Selects VREFH1 as the reference voltage."] - Vrefh1 = 1, - #[doc = "2: Selects VREFH2 as the reference voltage."] - Vrefh2 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dacrfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dacrfs { - type Ux = u8; -} -impl crate::IsEnum for Dacrfs {} -#[doc = "Field `DACRFS` reader - DAC Reference Select"] -pub type DacrfsR = crate::FieldReader; -impl DacrfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dacrfs::Vrefh0), - 1 => Some(Dacrfs::Vrefh1), - 2 => Some(Dacrfs::Vrefh2), - _ => None, - } - } - #[doc = "Selects VREFH0 as the reference voltage."] - #[inline(always)] - pub fn is_vrefh0(&self) -> bool { - *self == Dacrfs::Vrefh0 - } - #[doc = "Selects VREFH1 as the reference voltage."] - #[inline(always)] - pub fn is_vrefh1(&self) -> bool { - *self == Dacrfs::Vrefh1 - } - #[doc = "Selects VREFH2 as the reference voltage."] - #[inline(always)] - pub fn is_vrefh2(&self) -> bool { - *self == Dacrfs::Vrefh2 - } -} -#[doc = "Field `DACRFS` writer - DAC Reference Select"] -pub type DacrfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dacrfs>; -impl<'a, REG> DacrfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Selects VREFH0 as the reference voltage."] - #[inline(always)] - pub fn vrefh0(self) -> &'a mut crate::W { - self.variant(Dacrfs::Vrefh0) - } - #[doc = "Selects VREFH1 as the reference voltage."] - #[inline(always)] - pub fn vrefh1(self) -> &'a mut crate::W { - self.variant(Dacrfs::Vrefh1) - } - #[doc = "Selects VREFH2 as the reference voltage."] - #[inline(always)] - pub fn vrefh2(self) -> &'a mut crate::W { - self.variant(Dacrfs::Vrefh2) - } -} -#[doc = "FIFO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fifoen { - #[doc = "0: Disables FIFO mode and enables Buffer mode. Any data written to DATA\\[DATA\\] goes to buffer then goes to conversion."] - BufferMode = 0, - #[doc = "1: Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion."] - FifoMode = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fifoen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIFOEN` reader - FIFO Enable"] -pub type FifoenR = crate::BitReader; -impl FifoenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fifoen { - match self.bits { - false => Fifoen::BufferMode, - true => Fifoen::FifoMode, - } - } - #[doc = "Disables FIFO mode and enables Buffer mode. Any data written to DATA\\[DATA\\] goes to buffer then goes to conversion."] - #[inline(always)] - pub fn is_buffer_mode(&self) -> bool { - *self == Fifoen::BufferMode - } - #[doc = "Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion."] - #[inline(always)] - pub fn is_fifo_mode(&self) -> bool { - *self == Fifoen::FifoMode - } -} -#[doc = "Field `FIFOEN` writer - FIFO Enable"] -pub type FifoenW<'a, REG> = crate::BitWriter<'a, REG, Fifoen>; -impl<'a, REG> FifoenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables FIFO mode and enables Buffer mode. Any data written to DATA\\[DATA\\] goes to buffer then goes to conversion."] - #[inline(always)] - pub fn buffer_mode(self) -> &'a mut crate::W { - self.variant(Fifoen::BufferMode) - } - #[doc = "Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion."] - #[inline(always)] - pub fn fifo_mode(self) -> &'a mut crate::W { - self.variant(Fifoen::FifoMode) - } -} -#[doc = "Swing Back Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swmd { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swmd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWMD` reader - Swing Back Mode"] -pub type SwmdR = crate::BitReader; -impl SwmdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swmd { - match self.bits { - false => Swmd::Disable, - true => Swmd::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Swmd::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Swmd::Enable - } -} -#[doc = "Field `SWMD` writer - Swing Back Mode"] -pub type SwmdW<'a, REG> = crate::BitWriter<'a, REG, Swmd>; -impl<'a, REG> SwmdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Swmd::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Swmd::Enable) - } -} -#[doc = "DAC Trigger Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trgsel { - #[doc = "0: Hardware trigger"] - Hardware = 0, - #[doc = "1: Software trigger"] - Software = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trgsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRGSEL` reader - DAC Trigger Select"] -pub type TrgselR = crate::BitReader; -impl TrgselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgsel { - match self.bits { - false => Trgsel::Hardware, - true => Trgsel::Software, - } - } - #[doc = "Hardware trigger"] - #[inline(always)] - pub fn is_hardware(&self) -> bool { - *self == Trgsel::Hardware - } - #[doc = "Software trigger"] - #[inline(always)] - pub fn is_software(&self) -> bool { - *self == Trgsel::Software - } -} -#[doc = "Field `TRGSEL` writer - DAC Trigger Select"] -pub type TrgselW<'a, REG> = crate::BitWriter<'a, REG, Trgsel>; -impl<'a, REG> TrgselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Hardware trigger"] - #[inline(always)] - pub fn hardware(self) -> &'a mut crate::W { - self.variant(Trgsel::Hardware) - } - #[doc = "Software trigger"] - #[inline(always)] - pub fn software(self) -> &'a mut crate::W { - self.variant(Trgsel::Software) - } -} -#[doc = "DAC Periodic Trigger Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptgen { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptgen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTGEN` reader - DAC Periodic Trigger Mode Enable"] -pub type PtgenR = crate::BitReader; -impl PtgenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptgen { - match self.bits { - false => Ptgen::Disabled, - true => Ptgen::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ptgen::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ptgen::Enabled - } -} -#[doc = "Field `PTGEN` writer - DAC Periodic Trigger Mode Enable"] -pub type PtgenW<'a, REG> = crate::BitWriter<'a, REG, Ptgen>; -impl<'a, REG> PtgenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ptgen::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ptgen::Enabled) - } -} -#[doc = "Field `LATCH_CYC` reader - RCLK Cycles Before Data Latch"] -pub type LatchCycR = crate::FieldReader; -#[doc = "Field `LATCH_CYC` writer - RCLK Cycles Before Data Latch"] -pub type LatchCycW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum BufEn { - #[doc = "0: Not used"] - UseBuf = 0, - #[doc = "1: Used"] - NoUseBuf = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: BufEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUF_EN` reader - Buffer Enable"] -pub type BufEnR = crate::BitReader; -impl BufEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> BufEn { - match self.bits { - false => BufEn::UseBuf, - true => BufEn::NoUseBuf, - } - } - #[doc = "Not used"] - #[inline(always)] - pub fn is_use_buf(&self) -> bool { - *self == BufEn::UseBuf - } - #[doc = "Used"] - #[inline(always)] - pub fn is_no_use_buf(&self) -> bool { - *self == BufEn::NoUseBuf - } -} -#[doc = "Field `BUF_EN` writer - Buffer Enable"] -pub type BufEnW<'a, REG> = crate::BitWriter<'a, REG, BufEn>; -impl<'a, REG> BufEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not used"] - #[inline(always)] - pub fn use_buf(self) -> &'a mut crate::W { - self.variant(BufEn::UseBuf) - } - #[doc = "Used"] - #[inline(always)] - pub fn no_use_buf(self) -> &'a mut crate::W { - self.variant(BufEn::NoUseBuf) - } -} -#[doc = "External On-Chip PTAT Current Reference Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IrefPtatExtSel { - #[doc = "0: Not selected"] - NotSelected = 0, - #[doc = "1: Selected"] - Selected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IrefPtatExtSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IREF_PTAT_EXT_SEL` reader - External On-Chip PTAT Current Reference Select"] -pub type IrefPtatExtSelR = crate::BitReader; -impl IrefPtatExtSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IrefPtatExtSel { - match self.bits { - false => IrefPtatExtSel::NotSelected, - true => IrefPtatExtSel::Selected, - } - } - #[doc = "Not selected"] - #[inline(always)] - pub fn is_not_selected(&self) -> bool { - *self == IrefPtatExtSel::NotSelected - } - #[doc = "Selected"] - #[inline(always)] - pub fn is_selected(&self) -> bool { - *self == IrefPtatExtSel::Selected - } -} -#[doc = "Field `IREF_PTAT_EXT_SEL` writer - External On-Chip PTAT Current Reference Select"] -pub type IrefPtatExtSelW<'a, REG> = crate::BitWriter<'a, REG, IrefPtatExtSel>; -impl<'a, REG> IrefPtatExtSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not selected"] - #[inline(always)] - pub fn not_selected(self) -> &'a mut crate::W { - self.variant(IrefPtatExtSel::NotSelected) - } - #[doc = "Selected"] - #[inline(always)] - pub fn selected(self) -> &'a mut crate::W { - self.variant(IrefPtatExtSel::Selected) - } -} -#[doc = "External On-Chip ZTC Current Reference Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IrefZtcExtSel { - #[doc = "0: Not selected"] - NotSelected = 0, - #[doc = "1: Selected"] - Selected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IrefZtcExtSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IREF_ZTC_EXT_SEL` reader - External On-Chip ZTC Current Reference Select"] -pub type IrefZtcExtSelR = crate::BitReader; -impl IrefZtcExtSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IrefZtcExtSel { - match self.bits { - false => IrefZtcExtSel::NotSelected, - true => IrefZtcExtSel::Selected, - } - } - #[doc = "Not selected"] - #[inline(always)] - pub fn is_not_selected(&self) -> bool { - *self == IrefZtcExtSel::NotSelected - } - #[doc = "Selected"] - #[inline(always)] - pub fn is_selected(&self) -> bool { - *self == IrefZtcExtSel::Selected - } -} -#[doc = "Field `IREF_ZTC_EXT_SEL` writer - External On-Chip ZTC Current Reference Select"] -pub type IrefZtcExtSelW<'a, REG> = crate::BitWriter<'a, REG, IrefZtcExtSel>; -impl<'a, REG> IrefZtcExtSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not selected"] - #[inline(always)] - pub fn not_selected(self) -> &'a mut crate::W { - self.variant(IrefZtcExtSel::NotSelected) - } - #[doc = "Selected"] - #[inline(always)] - pub fn selected(self) -> &'a mut crate::W { - self.variant(IrefZtcExtSel::Selected) - } -} -#[doc = "OPAMP as Buffer, Speed Control Signal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum BufSpdCtrl { - #[doc = "0: Lower Low-Power mode"] - LlpMode = 0, - #[doc = "1: Low-Power mode"] - LpMode = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: BufSpdCtrl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUF_SPD_CTRL` reader - OPAMP as Buffer, Speed Control Signal"] -pub type BufSpdCtrlR = crate::BitReader; -impl BufSpdCtrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> BufSpdCtrl { - match self.bits { - false => BufSpdCtrl::LlpMode, - true => BufSpdCtrl::LpMode, - } - } - #[doc = "Lower Low-Power mode"] - #[inline(always)] - pub fn is_llp_mode(&self) -> bool { - *self == BufSpdCtrl::LlpMode - } - #[doc = "Low-Power mode"] - #[inline(always)] - pub fn is_lp_mode(&self) -> bool { - *self == BufSpdCtrl::LpMode - } -} -#[doc = "Field `BUF_SPD_CTRL` writer - OPAMP as Buffer, Speed Control Signal"] -pub type BufSpdCtrlW<'a, REG> = crate::BitWriter<'a, REG, BufSpdCtrl>; -impl<'a, REG> BufSpdCtrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Lower Low-Power mode"] - #[inline(always)] - pub fn llp_mode(self) -> &'a mut crate::W { - self.variant(BufSpdCtrl::LlpMode) - } - #[doc = "Low-Power mode"] - #[inline(always)] - pub fn lp_mode(self) -> &'a mut crate::W { - self.variant(BufSpdCtrl::LpMode) - } -} -impl R { - #[doc = "Bit 0 - DAC Enable"] - #[inline(always)] - pub fn dacen(&self) -> DacenR { - DacenR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - DAC Reference Select"] - #[inline(always)] - pub fn dacrfs(&self) -> DacrfsR { - DacrfsR::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 3 - FIFO Enable"] - #[inline(always)] - pub fn fifoen(&self) -> FifoenR { - FifoenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Swing Back Mode"] - #[inline(always)] - pub fn swmd(&self) -> SwmdR { - SwmdR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - DAC Trigger Select"] - #[inline(always)] - pub fn trgsel(&self) -> TrgselR { - TrgselR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - DAC Periodic Trigger Mode Enable"] - #[inline(always)] - pub fn ptgen(&self) -> PtgenR { - PtgenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - RCLK Cycles Before Data Latch"] - #[inline(always)] - pub fn latch_cyc(&self) -> LatchCycR { - LatchCycR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 17 - Buffer Enable"] - #[inline(always)] - pub fn buf_en(&self) -> BufEnR { - BufEnR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 20 - External On-Chip PTAT Current Reference Select"] - #[inline(always)] - pub fn iref_ptat_ext_sel(&self) -> IrefPtatExtSelR { - IrefPtatExtSelR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - External On-Chip ZTC Current Reference Select"] - #[inline(always)] - pub fn iref_ztc_ext_sel(&self) -> IrefZtcExtSelR { - IrefZtcExtSelR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 23 - OPAMP as Buffer, Speed Control Signal"] - #[inline(always)] - pub fn buf_spd_ctrl(&self) -> BufSpdCtrlR { - BufSpdCtrlR::new(((self.bits >> 23) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - DAC Enable"] - #[inline(always)] - pub fn dacen(&mut self) -> DacenW { - DacenW::new(self, 0) - } - #[doc = "Bits 1:2 - DAC Reference Select"] - #[inline(always)] - pub fn dacrfs(&mut self) -> DacrfsW { - DacrfsW::new(self, 1) - } - #[doc = "Bit 3 - FIFO Enable"] - #[inline(always)] - pub fn fifoen(&mut self) -> FifoenW { - FifoenW::new(self, 3) - } - #[doc = "Bit 4 - Swing Back Mode"] - #[inline(always)] - pub fn swmd(&mut self) -> SwmdW { - SwmdW::new(self, 4) - } - #[doc = "Bit 5 - DAC Trigger Select"] - #[inline(always)] - pub fn trgsel(&mut self) -> TrgselW { - TrgselW::new(self, 5) - } - #[doc = "Bit 6 - DAC Periodic Trigger Mode Enable"] - #[inline(always)] - pub fn ptgen(&mut self) -> PtgenW { - PtgenW::new(self, 6) - } - #[doc = "Bits 8:11 - RCLK Cycles Before Data Latch"] - #[inline(always)] - pub fn latch_cyc(&mut self) -> LatchCycW { - LatchCycW::new(self, 8) - } - #[doc = "Bit 17 - Buffer Enable"] - #[inline(always)] - pub fn buf_en(&mut self) -> BufEnW { - BufEnW::new(self, 17) - } - #[doc = "Bit 20 - External On-Chip PTAT Current Reference Select"] - #[inline(always)] - pub fn iref_ptat_ext_sel(&mut self) -> IrefPtatExtSelW { - IrefPtatExtSelW::new(self, 20) - } - #[doc = "Bit 21 - External On-Chip ZTC Current Reference Select"] - #[inline(always)] - pub fn iref_ztc_ext_sel(&mut self) -> IrefZtcExtSelW { - IrefZtcExtSelW::new(self, 21) - } - #[doc = "Bit 23 - OPAMP as Buffer, Speed Control Signal"] - #[inline(always)] - pub fn buf_spd_ctrl(&mut self) -> BufSpdCtrlW { - BufSpdCtrlW::new(self, 23) - } -} -#[doc = "Global Control\n\nYou can [`read`](crate::Reg::read) this register and get [`gcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GcrSpec; -impl crate::RegisterSpec for GcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gcr::R`](R) reader structure"] -impl crate::Readable for GcrSpec {} -#[doc = "`write(|w| ..)` method takes [`gcr::W`](W) writer structure"] -impl crate::Writable for GcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GCR to value 0x0100"] -impl crate::Resettable for GcrSpec { - const RESET_VALUE: u32 = 0x0100; -} diff --git a/mcxa276-pac/src/dac0/ier.rs b/mcxa276-pac/src/dac0/ier.rs deleted file mode 100644 index ad3c4b72c..000000000 --- a/mcxa276-pac/src/dac0/ier.rs +++ /dev/null @@ -1,462 +0,0 @@ -#[doc = "Register `IER` reader"] -pub type R = crate::R; -#[doc = "Register `IER` writer"] -pub type W = crate::W; -#[doc = "FIFO Full Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FullIe { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FullIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FULL_IE` reader - FIFO Full Interrupt Enable"] -pub type FullIeR = crate::BitReader; -impl FullIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FullIe { - match self.bits { - false => FullIe::Disabled, - true => FullIe::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == FullIe::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == FullIe::Enabled - } -} -#[doc = "Field `FULL_IE` writer - FIFO Full Interrupt Enable"] -pub type FullIeW<'a, REG> = crate::BitWriter<'a, REG, FullIe>; -impl<'a, REG> FullIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(FullIe::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(FullIe::Enabled) - } -} -#[doc = "FIFO Empty Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EmptyIe { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EmptyIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EMPTY_IE` reader - FIFO Empty Interrupt Enable"] -pub type EmptyIeR = crate::BitReader; -impl EmptyIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EmptyIe { - match self.bits { - false => EmptyIe::Disabled, - true => EmptyIe::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == EmptyIe::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == EmptyIe::Enabled - } -} -#[doc = "Field `EMPTY_IE` writer - FIFO Empty Interrupt Enable"] -pub type EmptyIeW<'a, REG> = crate::BitWriter<'a, REG, EmptyIe>; -impl<'a, REG> EmptyIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(EmptyIe::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(EmptyIe::Enabled) - } -} -#[doc = "FIFO Watermark Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WmIe { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WmIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WM_IE` reader - FIFO Watermark Interrupt Enable"] -pub type WmIeR = crate::BitReader; -impl WmIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WmIe { - match self.bits { - false => WmIe::Disabled, - true => WmIe::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == WmIe::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == WmIe::Enabled - } -} -#[doc = "Field `WM_IE` writer - FIFO Watermark Interrupt Enable"] -pub type WmIeW<'a, REG> = crate::BitWriter<'a, REG, WmIe>; -impl<'a, REG> WmIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(WmIe::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(WmIe::Enabled) - } -} -#[doc = "Swing Back One Cycle Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SwbkIe { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SwbkIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWBK_IE` reader - Swing Back One Cycle Complete Interrupt Enable"] -pub type SwbkIeR = crate::BitReader; -impl SwbkIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SwbkIe { - match self.bits { - false => SwbkIe::Disabled, - true => SwbkIe::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == SwbkIe::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == SwbkIe::Enabled - } -} -#[doc = "Field `SWBK_IE` writer - Swing Back One Cycle Complete Interrupt Enable"] -pub type SwbkIeW<'a, REG> = crate::BitWriter<'a, REG, SwbkIe>; -impl<'a, REG> SwbkIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(SwbkIe::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(SwbkIe::Enabled) - } -} -#[doc = "FIFO Overflow Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OfIe { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OfIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OF_IE` reader - FIFO Overflow Interrupt Enable"] -pub type OfIeR = crate::BitReader; -impl OfIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OfIe { - match self.bits { - false => OfIe::Disabled, - true => OfIe::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == OfIe::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == OfIe::Enabled - } -} -#[doc = "Field `OF_IE` writer - FIFO Overflow Interrupt Enable"] -pub type OfIeW<'a, REG> = crate::BitWriter<'a, REG, OfIe>; -impl<'a, REG> OfIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(OfIe::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(OfIe::Enabled) - } -} -#[doc = "FIFO Underflow Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum UfIe { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: UfIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UF_IE` reader - FIFO Underflow Interrupt Enable"] -pub type UfIeR = crate::BitReader; -impl UfIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> UfIe { - match self.bits { - false => UfIe::Disabled, - true => UfIe::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == UfIe::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == UfIe::Enabled - } -} -#[doc = "Field `UF_IE` writer - FIFO Underflow Interrupt Enable"] -pub type UfIeW<'a, REG> = crate::BitWriter<'a, REG, UfIe>; -impl<'a, REG> UfIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(UfIe::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(UfIe::Enabled) - } -} -#[doc = "PTG Mode Conversion Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PtgcocoIe { - #[doc = "0: Disables"] - Disabled = 0, - #[doc = "1: Enables"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PtgcocoIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTGCOCO_IE` reader - PTG Mode Conversion Complete Interrupt Enable"] -pub type PtgcocoIeR = crate::BitReader; -impl PtgcocoIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PtgcocoIe { - match self.bits { - false => PtgcocoIe::Disabled, - true => PtgcocoIe::Enabled, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == PtgcocoIe::Disabled - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == PtgcocoIe::Enabled - } -} -#[doc = "Field `PTGCOCO_IE` writer - PTG Mode Conversion Complete Interrupt Enable"] -pub type PtgcocoIeW<'a, REG> = crate::BitWriter<'a, REG, PtgcocoIe>; -impl<'a, REG> PtgcocoIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(PtgcocoIe::Disabled) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(PtgcocoIe::Enabled) - } -} -impl R { - #[doc = "Bit 0 - FIFO Full Interrupt Enable"] - #[inline(always)] - pub fn full_ie(&self) -> FullIeR { - FullIeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - FIFO Empty Interrupt Enable"] - #[inline(always)] - pub fn empty_ie(&self) -> EmptyIeR { - EmptyIeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - FIFO Watermark Interrupt Enable"] - #[inline(always)] - pub fn wm_ie(&self) -> WmIeR { - WmIeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Swing Back One Cycle Complete Interrupt Enable"] - #[inline(always)] - pub fn swbk_ie(&self) -> SwbkIeR { - SwbkIeR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 6 - FIFO Overflow Interrupt Enable"] - #[inline(always)] - pub fn of_ie(&self) -> OfIeR { - OfIeR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - FIFO Underflow Interrupt Enable"] - #[inline(always)] - pub fn uf_ie(&self) -> UfIeR { - UfIeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - PTG Mode Conversion Complete Interrupt Enable"] - #[inline(always)] - pub fn ptgcoco_ie(&self) -> PtgcocoIeR { - PtgcocoIeR::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FIFO Full Interrupt Enable"] - #[inline(always)] - pub fn full_ie(&mut self) -> FullIeW { - FullIeW::new(self, 0) - } - #[doc = "Bit 1 - FIFO Empty Interrupt Enable"] - #[inline(always)] - pub fn empty_ie(&mut self) -> EmptyIeW { - EmptyIeW::new(self, 1) - } - #[doc = "Bit 2 - FIFO Watermark Interrupt Enable"] - #[inline(always)] - pub fn wm_ie(&mut self) -> WmIeW { - WmIeW::new(self, 2) - } - #[doc = "Bit 3 - Swing Back One Cycle Complete Interrupt Enable"] - #[inline(always)] - pub fn swbk_ie(&mut self) -> SwbkIeW { - SwbkIeW::new(self, 3) - } - #[doc = "Bit 6 - FIFO Overflow Interrupt Enable"] - #[inline(always)] - pub fn of_ie(&mut self) -> OfIeW { - OfIeW::new(self, 6) - } - #[doc = "Bit 7 - FIFO Underflow Interrupt Enable"] - #[inline(always)] - pub fn uf_ie(&mut self) -> UfIeW { - UfIeW::new(self, 7) - } - #[doc = "Bit 8 - PTG Mode Conversion Complete Interrupt Enable"] - #[inline(always)] - pub fn ptgcoco_ie(&mut self) -> PtgcocoIeW { - PtgcocoIeW::new(self, 8) - } -} -#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IerSpec; -impl crate::RegisterSpec for IerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ier::R`](R) reader structure"] -impl crate::Readable for IerSpec {} -#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] -impl crate::Writable for IerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IER to value 0"] -impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/dac0/param.rs b/mcxa276-pac/src/dac0/param.rs deleted file mode 100644 index df3ecd81e..000000000 --- a/mcxa276-pac/src/dac0/param.rs +++ /dev/null @@ -1,102 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "FIFO Size\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fifosz { - #[doc = "1: FIFO depth is 4"] - Val1 = 1, - #[doc = "2: FIFO depth is 8"] - Val2 = 2, - #[doc = "3: FIFO depth is 16"] - Val3 = 3, - #[doc = "4: FIFO depth is 32"] - Val4 = 4, - #[doc = "5: FIFO depth is 64"] - Val5 = 5, - #[doc = "6: FIFO depth is 128"] - Val6 = 6, - #[doc = "7: FIFO depth is 256"] - Val7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fifosz) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fifosz { - type Ux = u8; -} -impl crate::IsEnum for Fifosz {} -#[doc = "Field `FIFOSZ` reader - FIFO Size"] -pub type FifoszR = crate::FieldReader; -impl FifoszR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Fifosz::Val1), - 2 => Some(Fifosz::Val2), - 3 => Some(Fifosz::Val3), - 4 => Some(Fifosz::Val4), - 5 => Some(Fifosz::Val5), - 6 => Some(Fifosz::Val6), - 7 => Some(Fifosz::Val7), - _ => None, - } - } - #[doc = "FIFO depth is 4"] - #[inline(always)] - pub fn is_val_1(&self) -> bool { - *self == Fifosz::Val1 - } - #[doc = "FIFO depth is 8"] - #[inline(always)] - pub fn is_val_2(&self) -> bool { - *self == Fifosz::Val2 - } - #[doc = "FIFO depth is 16"] - #[inline(always)] - pub fn is_val_3(&self) -> bool { - *self == Fifosz::Val3 - } - #[doc = "FIFO depth is 32"] - #[inline(always)] - pub fn is_val_4(&self) -> bool { - *self == Fifosz::Val4 - } - #[doc = "FIFO depth is 64"] - #[inline(always)] - pub fn is_val_5(&self) -> bool { - *self == Fifosz::Val5 - } - #[doc = "FIFO depth is 128"] - #[inline(always)] - pub fn is_val_6(&self) -> bool { - *self == Fifosz::Val6 - } - #[doc = "FIFO depth is 256"] - #[inline(always)] - pub fn is_val_7(&self) -> bool { - *self == Fifosz::Val7 - } -} -impl R { - #[doc = "Bits 0:2 - FIFO Size"] - #[inline(always)] - pub fn fifosz(&self) -> FifoszR { - FifoszR::new((self.bits & 7) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x03"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x03; -} diff --git a/mcxa276-pac/src/dac0/pcr.rs b/mcxa276-pac/src/dac0/pcr.rs deleted file mode 100644 index de8ace6c1..000000000 --- a/mcxa276-pac/src/dac0/pcr.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `PCR` reader"] -pub type R = crate::R; -#[doc = "Register `PCR` writer"] -pub type W = crate::W; -#[doc = "Field `PTG_NUM` reader - Periodic Trigger Number"] -pub type PtgNumR = crate::FieldReader; -#[doc = "Field `PTG_NUM` writer - Periodic Trigger Number"] -pub type PtgNumW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `PTG_PERIOD` reader - Periodic Trigger Period Width"] -pub type PtgPeriodR = crate::FieldReader; -#[doc = "Field `PTG_PERIOD` writer - Periodic Trigger Period Width"] -pub type PtgPeriodW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Periodic Trigger Number"] - #[inline(always)] - pub fn ptg_num(&self) -> PtgNumR { - PtgNumR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Periodic Trigger Period Width"] - #[inline(always)] - pub fn ptg_period(&self) -> PtgPeriodR { - PtgPeriodR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Periodic Trigger Number"] - #[inline(always)] - pub fn ptg_num(&mut self) -> PtgNumW { - PtgNumW::new(self, 0) - } - #[doc = "Bits 16:31 - Periodic Trigger Period Width"] - #[inline(always)] - pub fn ptg_period(&mut self) -> PtgPeriodW { - PtgPeriodW::new(self, 16) - } -} -#[doc = "Periodic Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PcrSpec; -impl crate::RegisterSpec for PcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr::R`](R) reader structure"] -impl crate::Readable for PcrSpec {} -#[doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] -impl crate::Writable for PcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR to value 0"] -impl crate::Resettable for PcrSpec {} diff --git a/mcxa276-pac/src/dac0/rcr.rs b/mcxa276-pac/src/dac0/rcr.rs deleted file mode 100644 index 3606c34e0..000000000 --- a/mcxa276-pac/src/dac0/rcr.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `RCR` reader"] -pub type R = crate::R; -#[doc = "Register `RCR` writer"] -pub type W = crate::W; -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swrst { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Software reset"] - SoftwareReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swrst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWRST` reader - Software Reset"] -pub type SwrstR = crate::BitReader; -impl SwrstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swrst { - match self.bits { - false => Swrst::NoEffect, - true => Swrst::SoftwareReset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Swrst::NoEffect - } - #[doc = "Software reset"] - #[inline(always)] - pub fn is_software_reset(&self) -> bool { - *self == Swrst::SoftwareReset - } -} -#[doc = "Field `SWRST` writer - Software Reset"] -pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG, Swrst>; -impl<'a, REG> SwrstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Swrst::NoEffect) - } - #[doc = "Software reset"] - #[inline(always)] - pub fn software_reset(self) -> &'a mut crate::W { - self.variant(Swrst::SoftwareReset) - } -} -#[doc = "FIFO Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fiforst { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: FIFO reset"] - FifoReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fiforst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIFORST` reader - FIFO Reset"] -pub type FiforstR = crate::BitReader; -impl FiforstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fiforst { - match self.bits { - false => Fiforst::NoEffect, - true => Fiforst::FifoReset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Fiforst::NoEffect - } - #[doc = "FIFO reset"] - #[inline(always)] - pub fn is_fifo_reset(&self) -> bool { - *self == Fiforst::FifoReset - } -} -#[doc = "Field `FIFORST` writer - FIFO Reset"] -pub type FiforstW<'a, REG> = crate::BitWriter<'a, REG, Fiforst>; -impl<'a, REG> FiforstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Fiforst::NoEffect) - } - #[doc = "FIFO reset"] - #[inline(always)] - pub fn fifo_reset(self) -> &'a mut crate::W { - self.variant(Fiforst::FifoReset) - } -} -impl R { - #[doc = "Bit 0 - Software Reset"] - #[inline(always)] - pub fn swrst(&self) -> SwrstR { - SwrstR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - FIFO Reset"] - #[inline(always)] - pub fn fiforst(&self) -> FiforstR { - FiforstR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Software Reset"] - #[inline(always)] - pub fn swrst(&mut self) -> SwrstW { - SwrstW::new(self, 0) - } - #[doc = "Bit 1 - FIFO Reset"] - #[inline(always)] - pub fn fiforst(&mut self) -> FiforstW { - FiforstW::new(self, 1) - } -} -#[doc = "Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RcrSpec; -impl crate::RegisterSpec for RcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rcr::R`](R) reader structure"] -impl crate::Readable for RcrSpec {} -#[doc = "`write(|w| ..)` method takes [`rcr::W`](W) writer structure"] -impl crate::Writable for RcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RCR to value 0"] -impl crate::Resettable for RcrSpec {} diff --git a/mcxa276-pac/src/dac0/tcr.rs b/mcxa276-pac/src/dac0/tcr.rs deleted file mode 100644 index 45f4f562f..000000000 --- a/mcxa276-pac/src/dac0/tcr.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `TCR` reader"] -pub type R = crate::R; -#[doc = "Register `TCR` writer"] -pub type W = crate::W; -#[doc = "Software Trigger\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swtrg { - #[doc = "0: Not valid"] - NotValid = 0, - #[doc = "1: Valid"] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swtrg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWTRG` reader - Software Trigger"] -pub type SwtrgR = crate::BitReader; -impl SwtrgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swtrg { - match self.bits { - false => Swtrg::NotValid, - true => Swtrg::Valid, - } - } - #[doc = "Not valid"] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Swtrg::NotValid - } - #[doc = "Valid"] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Swtrg::Valid - } -} -#[doc = "Field `SWTRG` writer - Software Trigger"] -pub type SwtrgW<'a, REG> = crate::BitWriter<'a, REG, Swtrg>; -impl<'a, REG> SwtrgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not valid"] - #[inline(always)] - pub fn not_valid(self) -> &'a mut crate::W { - self.variant(Swtrg::NotValid) - } - #[doc = "Valid"] - #[inline(always)] - pub fn valid(self) -> &'a mut crate::W { - self.variant(Swtrg::Valid) - } -} -impl R { - #[doc = "Bit 0 - Software Trigger"] - #[inline(always)] - pub fn swtrg(&self) -> SwtrgR { - SwtrgR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Software Trigger"] - #[inline(always)] - pub fn swtrg(&mut self) -> SwtrgW { - SwtrgW::new(self, 0) - } -} -#[doc = "Trigger Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcrSpec; -impl crate::RegisterSpec for TcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] -impl crate::Readable for TcrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] -impl crate::Writable for TcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCR to value 0"] -impl crate::Resettable for TcrSpec {} diff --git a/mcxa276-pac/src/dac0/verid.rs b/mcxa276-pac/src/dac0/verid.rs deleted file mode 100644 index 8399c41cc..000000000 --- a/mcxa276-pac/src/dac0/verid.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Field `FEATURE` reader - Feature Identification Number"] -pub type FeatureR = crate::FieldReader; -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Identification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version Identifier\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0100_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0100_0000; -} diff --git a/mcxa276-pac/src/dbgmailbox.rs b/mcxa276-pac/src/dbgmailbox.rs deleted file mode 100644 index c3ac277be..000000000 --- a/mcxa276-pac/src/dbgmailbox.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - csw: Csw, - request: Request, - return_: Return, - _reserved3: [u8; 0xf0], - id: Id, -} -impl RegisterBlock { - #[doc = "0x00 - Command and Status Word"] - #[inline(always)] - pub const fn csw(&self) -> &Csw { - &self.csw - } - #[doc = "0x04 - Request Value"] - #[inline(always)] - pub const fn request(&self) -> &Request { - &self.request - } - #[doc = "0x08 - Return Value"] - #[inline(always)] - pub const fn return_(&self) -> &Return { - &self.return_ - } - #[doc = "0xfc - Identification"] - #[inline(always)] - pub const fn id(&self) -> &Id { - &self.id - } -} -#[doc = "CSW (rw) register accessor: Command and Status Word\n\nYou can [`read`](crate::Reg::read) this register and get [`csw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csw`] module"] -#[doc(alias = "CSW")] -pub type Csw = crate::Reg; -#[doc = "Command and Status Word"] -pub mod csw; -#[doc = "REQUEST (rw) register accessor: Request Value\n\nYou can [`read`](crate::Reg::read) this register and get [`request::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`request::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@request`] module"] -#[doc(alias = "REQUEST")] -pub type Request = crate::Reg; -#[doc = "Request Value"] -pub mod request; -#[doc = "RETURN (rw) register accessor: Return Value\n\nYou can [`read`](crate::Reg::read) this register and get [`return_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`return_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@return_`] module"] -#[doc(alias = "RETURN")] -pub type Return = crate::Reg; -#[doc = "Return Value"] -pub mod return_; -#[doc = "ID (r) register accessor: Identification\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`] module"] -#[doc(alias = "ID")] -pub type Id = crate::Reg; -#[doc = "Identification"] -pub mod id; diff --git a/mcxa276-pac/src/dbgmailbox/csw.rs b/mcxa276-pac/src/dbgmailbox/csw.rs deleted file mode 100644 index e29511de4..000000000 --- a/mcxa276-pac/src/dbgmailbox/csw.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `CSW` reader"] -pub type R = crate::R; -#[doc = "Register `CSW` writer"] -pub type W = crate::W; -#[doc = "Resynchronization Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ResynchReq { - #[doc = "0: No request"] - NoRequest = 0, - #[doc = "1: Request for resynchronization"] - Request = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ResynchReq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESYNCH_REQ` reader - Resynchronization Request"] -pub type ResynchReqR = crate::BitReader; -impl ResynchReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ResynchReq { - match self.bits { - false => ResynchReq::NoRequest, - true => ResynchReq::Request, - } - } - #[doc = "No request"] - #[inline(always)] - pub fn is_no_request(&self) -> bool { - *self == ResynchReq::NoRequest - } - #[doc = "Request for resynchronization"] - #[inline(always)] - pub fn is_request(&self) -> bool { - *self == ResynchReq::Request - } -} -#[doc = "Field `RESYNCH_REQ` writer - Resynchronization Request"] -pub type ResynchReqW<'a, REG> = crate::BitWriter<'a, REG, ResynchReq>; -impl<'a, REG> ResynchReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No request"] - #[inline(always)] - pub fn no_request(self) -> &'a mut crate::W { - self.variant(ResynchReq::NoRequest) - } - #[doc = "Request for resynchronization"] - #[inline(always)] - pub fn request(self) -> &'a mut crate::W { - self.variant(ResynchReq::Request) - } -} -#[doc = "Request Pending\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ReqPending { - #[doc = "0: No request pending"] - NoRequestPending = 0, - #[doc = "1: Request for resynchronization pending"] - RequestPending = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ReqPending) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REQ_PENDING` reader - Request Pending"] -pub type ReqPendingR = crate::BitReader; -impl ReqPendingR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ReqPending { - match self.bits { - false => ReqPending::NoRequestPending, - true => ReqPending::RequestPending, - } - } - #[doc = "No request pending"] - #[inline(always)] - pub fn is_no_request_pending(&self) -> bool { - *self == ReqPending::NoRequestPending - } - #[doc = "Request for resynchronization pending"] - #[inline(always)] - pub fn is_request_pending(&self) -> bool { - *self == ReqPending::RequestPending - } -} -#[doc = "Field `REQ_PENDING` writer - Request Pending"] -pub type ReqPendingW<'a, REG> = crate::BitWriter<'a, REG, ReqPending>; -impl<'a, REG> ReqPendingW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No request pending"] - #[inline(always)] - pub fn no_request_pending(self) -> &'a mut crate::W { - self.variant(ReqPending::NoRequestPending) - } - #[doc = "Request for resynchronization pending"] - #[inline(always)] - pub fn request_pending(self) -> &'a mut crate::W { - self.variant(ReqPending::RequestPending) - } -} -#[doc = "DBGMB Overrun Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DbgOrErr { - #[doc = "0: No overrun"] - NoOverrunErr = 0, - #[doc = "1: Overrun occurred"] - OverrunErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DbgOrErr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBG_OR_ERR` reader - DBGMB Overrun Error"] -pub type DbgOrErrR = crate::BitReader; -impl DbgOrErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DbgOrErr { - match self.bits { - false => DbgOrErr::NoOverrunErr, - true => DbgOrErr::OverrunErr, - } - } - #[doc = "No overrun"] - #[inline(always)] - pub fn is_no_overrun_err(&self) -> bool { - *self == DbgOrErr::NoOverrunErr - } - #[doc = "Overrun occurred"] - #[inline(always)] - pub fn is_overrun_err(&self) -> bool { - *self == DbgOrErr::OverrunErr - } -} -#[doc = "Field `DBG_OR_ERR` writer - DBGMB Overrun Error"] -pub type DbgOrErrW<'a, REG> = crate::BitWriter<'a, REG, DbgOrErr>; -impl<'a, REG> DbgOrErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overrun"] - #[inline(always)] - pub fn no_overrun_err(self) -> &'a mut crate::W { - self.variant(DbgOrErr::NoOverrunErr) - } - #[doc = "Overrun occurred"] - #[inline(always)] - pub fn overrun_err(self) -> &'a mut crate::W { - self.variant(DbgOrErr::OverrunErr) - } -} -#[doc = "AHB Overrun Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum AhbOrErr { - #[doc = "0: No overrun"] - NoAhbOverrunErr = 0, - #[doc = "1: Overrun occurred"] - AhbOverrunErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: AhbOrErr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AHB_OR_ERR` reader - AHB Overrun Error"] -pub type AhbOrErrR = crate::BitReader; -impl AhbOrErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> AhbOrErr { - match self.bits { - false => AhbOrErr::NoAhbOverrunErr, - true => AhbOrErr::AhbOverrunErr, - } - } - #[doc = "No overrun"] - #[inline(always)] - pub fn is_no_ahb_overrun_err(&self) -> bool { - *self == AhbOrErr::NoAhbOverrunErr - } - #[doc = "Overrun occurred"] - #[inline(always)] - pub fn is_ahb_overrun_err(&self) -> bool { - *self == AhbOrErr::AhbOverrunErr - } -} -#[doc = "Field `AHB_OR_ERR` writer - AHB Overrun Error"] -pub type AhbOrErrW<'a, REG> = crate::BitWriter<'a, REG, AhbOrErr>; -impl<'a, REG> AhbOrErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overrun"] - #[inline(always)] - pub fn no_ahb_overrun_err(self) -> &'a mut crate::W { - self.variant(AhbOrErr::NoAhbOverrunErr) - } - #[doc = "Overrun occurred"] - #[inline(always)] - pub fn ahb_overrun_err(self) -> &'a mut crate::W { - self.variant(AhbOrErr::AhbOverrunErr) - } -} -#[doc = "Soft Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SoftReset { - #[doc = "0: No effect"] - NoEff = 0, - #[doc = "1: Reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SoftReset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOFT_RESET` reader - Soft Reset"] -pub type SoftResetR = crate::BitReader; -impl SoftResetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SoftReset { - match self.bits { - false => SoftReset::NoEff, - true => SoftReset::Reset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_eff(&self) -> bool { - *self == SoftReset::NoEff - } - #[doc = "Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == SoftReset::Reset - } -} -#[doc = "Field `SOFT_RESET` writer - Soft Reset"] -pub type SoftResetW<'a, REG> = crate::BitWriter<'a, REG, SoftReset>; -impl<'a, REG> SoftResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_eff(self) -> &'a mut crate::W { - self.variant(SoftReset::NoEff) - } - #[doc = "Reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(SoftReset::Reset) - } -} -#[doc = "Chip Reset Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ChipResetReq { - #[doc = "0: No effect"] - NoEff = 0, - #[doc = "1: Reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ChipResetReq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CHIP_RESET_REQ` reader - Chip Reset Request"] -pub type ChipResetReqR = crate::BitReader; -impl ChipResetReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ChipResetReq { - match self.bits { - false => ChipResetReq::NoEff, - true => ChipResetReq::Reset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_eff(&self) -> bool { - *self == ChipResetReq::NoEff - } - #[doc = "Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == ChipResetReq::Reset - } -} -#[doc = "Field `CHIP_RESET_REQ` writer - Chip Reset Request"] -pub type ChipResetReqW<'a, REG> = crate::BitWriter<'a, REG, ChipResetReq>; -impl<'a, REG> ChipResetReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_eff(self) -> &'a mut crate::W { - self.variant(ChipResetReq::NoEff) - } - #[doc = "Reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(ChipResetReq::Reset) - } -} -impl R { - #[doc = "Bit 0 - Resynchronization Request"] - #[inline(always)] - pub fn resynch_req(&self) -> ResynchReqR { - ResynchReqR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Request Pending"] - #[inline(always)] - pub fn req_pending(&self) -> ReqPendingR { - ReqPendingR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - DBGMB Overrun Error"] - #[inline(always)] - pub fn dbg_or_err(&self) -> DbgOrErrR { - DbgOrErrR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - AHB Overrun Error"] - #[inline(always)] - pub fn ahb_or_err(&self) -> AhbOrErrR { - AhbOrErrR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Soft Reset"] - #[inline(always)] - pub fn soft_reset(&self) -> SoftResetR { - SoftResetR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Chip Reset Request"] - #[inline(always)] - pub fn chip_reset_req(&self) -> ChipResetReqR { - ChipResetReqR::new(((self.bits >> 5) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Resynchronization Request"] - #[inline(always)] - pub fn resynch_req(&mut self) -> ResynchReqW { - ResynchReqW::new(self, 0) - } - #[doc = "Bit 1 - Request Pending"] - #[inline(always)] - pub fn req_pending(&mut self) -> ReqPendingW { - ReqPendingW::new(self, 1) - } - #[doc = "Bit 2 - DBGMB Overrun Error"] - #[inline(always)] - pub fn dbg_or_err(&mut self) -> DbgOrErrW { - DbgOrErrW::new(self, 2) - } - #[doc = "Bit 3 - AHB Overrun Error"] - #[inline(always)] - pub fn ahb_or_err(&mut self) -> AhbOrErrW { - AhbOrErrW::new(self, 3) - } - #[doc = "Bit 4 - Soft Reset"] - #[inline(always)] - pub fn soft_reset(&mut self) -> SoftResetW { - SoftResetW::new(self, 4) - } - #[doc = "Bit 5 - Chip Reset Request"] - #[inline(always)] - pub fn chip_reset_req(&mut self) -> ChipResetReqW { - ChipResetReqW::new(self, 5) - } -} -#[doc = "Command and Status Word\n\nYou can [`read`](crate::Reg::read) this register and get [`csw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CswSpec; -impl crate::RegisterSpec for CswSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`csw::R`](R) reader structure"] -impl crate::Readable for CswSpec {} -#[doc = "`write(|w| ..)` method takes [`csw::W`](W) writer structure"] -impl crate::Writable for CswSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CSW to value 0"] -impl crate::Resettable for CswSpec {} diff --git a/mcxa276-pac/src/dbgmailbox/id.rs b/mcxa276-pac/src/dbgmailbox/id.rs deleted file mode 100644 index 302e7ac82..000000000 --- a/mcxa276-pac/src/dbgmailbox/id.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `ID` reader"] -pub type R = crate::R; -#[doc = "Field `ID` reader - Identification Value"] -pub type IdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Identification Value"] - #[inline(always)] - pub fn id(&self) -> IdR { - IdR::new(self.bits) - } -} -#[doc = "Identification\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IdSpec; -impl crate::RegisterSpec for IdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`id::R`](R) reader structure"] -impl crate::Readable for IdSpec {} -#[doc = "`reset()` method sets ID to value 0x002a_0000"] -impl crate::Resettable for IdSpec { - const RESET_VALUE: u32 = 0x002a_0000; -} diff --git a/mcxa276-pac/src/dbgmailbox/request.rs b/mcxa276-pac/src/dbgmailbox/request.rs deleted file mode 100644 index 9b19c2b26..000000000 --- a/mcxa276-pac/src/dbgmailbox/request.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `REQUEST` reader"] -pub type R = crate::R; -#[doc = "Register `REQUEST` writer"] -pub type W = crate::W; -#[doc = "Field `REQUEST` reader - Request Value"] -pub type RequestR = crate::FieldReader; -#[doc = "Field `REQUEST` writer - Request Value"] -pub type RequestW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Request Value"] - #[inline(always)] - pub fn request(&self) -> RequestR { - RequestR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Request Value"] - #[inline(always)] - pub fn request(&mut self) -> RequestW { - RequestW::new(self, 0) - } -} -#[doc = "Request Value\n\nYou can [`read`](crate::Reg::read) this register and get [`request::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`request::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RequestSpec; -impl crate::RegisterSpec for RequestSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`request::R`](R) reader structure"] -impl crate::Readable for RequestSpec {} -#[doc = "`write(|w| ..)` method takes [`request::W`](W) writer structure"] -impl crate::Writable for RequestSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets REQUEST to value 0"] -impl crate::Resettable for RequestSpec {} diff --git a/mcxa276-pac/src/dbgmailbox/return_.rs b/mcxa276-pac/src/dbgmailbox/return_.rs deleted file mode 100644 index 4e9817191..000000000 --- a/mcxa276-pac/src/dbgmailbox/return_.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RETURN` reader"] -pub type R = crate::R; -#[doc = "Register `RETURN` writer"] -pub type W = crate::W; -#[doc = "Field `RET` reader - Return Value"] -pub type RetR = crate::FieldReader; -#[doc = "Field `RET` writer - Return Value"] -pub type RetW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Return Value"] - #[inline(always)] - pub fn ret(&self) -> RetR { - RetR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Return Value"] - #[inline(always)] - pub fn ret(&mut self) -> RetW { - RetW::new(self, 0) - } -} -#[doc = "Return Value\n\nYou can [`read`](crate::Reg::read) this register and get [`return_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`return_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ReturnSpec; -impl crate::RegisterSpec for ReturnSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`return_::R`](R) reader structure"] -impl crate::Readable for ReturnSpec {} -#[doc = "`write(|w| ..)` method takes [`return_::W`](W) writer structure"] -impl crate::Writable for ReturnSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RETURN to value 0"] -impl crate::Resettable for ReturnSpec {} diff --git a/mcxa276-pac/src/dma0.rs b/mcxa276-pac/src/dma0.rs deleted file mode 100644 index c28e9155d..000000000 --- a/mcxa276-pac/src/dma0.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - mp_csr: MpCsr, - mp_es: MpEs, - mp_int: MpInt, - mp_hrs: MpHrs, - _reserved4: [u8; 0xf0], - ch_grpri: [ChGrpri; 8], -} -impl RegisterBlock { - #[doc = "0x00 - Management Page Control"] - #[inline(always)] - pub const fn mp_csr(&self) -> &MpCsr { - &self.mp_csr - } - #[doc = "0x04 - Management Page Error Status"] - #[inline(always)] - pub const fn mp_es(&self) -> &MpEs { - &self.mp_es - } - #[doc = "0x08 - Management Page Interrupt Request Status"] - #[inline(always)] - pub const fn mp_int(&self) -> &MpInt { - &self.mp_int - } - #[doc = "0x0c - Management Page Hardware Request Status"] - #[inline(always)] - pub const fn mp_hrs(&self) -> &MpHrs { - &self.mp_hrs - } - #[doc = "0x100..0x120 - Channel Arbitration Group"] - #[inline(always)] - pub const fn ch_grpri(&self, n: usize) -> &ChGrpri { - &self.ch_grpri[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x100..0x120 - Channel Arbitration Group"] - #[inline(always)] - pub fn ch_grpri_iter(&self) -> impl Iterator { - self.ch_grpri.iter() - } -} -#[doc = "MP_CSR (rw) register accessor: Management Page Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mp_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_csr`] module"] -#[doc(alias = "MP_CSR")] -pub type MpCsr = crate::Reg; -#[doc = "Management Page Control"] -pub mod mp_csr; -#[doc = "MP_ES (r) register accessor: Management Page Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_es::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_es`] module"] -#[doc(alias = "MP_ES")] -pub type MpEs = crate::Reg; -#[doc = "Management Page Error Status"] -pub mod mp_es; -#[doc = "MP_INT (r) register accessor: Management Page Interrupt Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_int::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_int`] module"] -#[doc(alias = "MP_INT")] -pub type MpInt = crate::Reg; -#[doc = "Management Page Interrupt Request Status"] -pub mod mp_int; -#[doc = "MP_HRS (r) register accessor: Management Page Hardware Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_hrs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mp_hrs`] module"] -#[doc(alias = "MP_HRS")] -pub type MpHrs = crate::Reg; -#[doc = "Management Page Hardware Request Status"] -pub mod mp_hrs; -#[doc = "CH_GRPRI (rw) register accessor: Channel Arbitration Group\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_grpri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_grpri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_grpri`] module"] -#[doc(alias = "CH_GRPRI")] -pub type ChGrpri = crate::Reg; -#[doc = "Channel Arbitration Group"] -pub mod ch_grpri; diff --git a/mcxa276-pac/src/dma0/ch_grpri.rs b/mcxa276-pac/src/dma0/ch_grpri.rs deleted file mode 100644 index 910ba4f1a..000000000 --- a/mcxa276-pac/src/dma0/ch_grpri.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CH_GRPRI[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `CH_GRPRI[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `GRPRI` reader - Arbitration Group For Channel n"] -pub type GrpriR = crate::FieldReader; -#[doc = "Field `GRPRI` writer - Arbitration Group For Channel n"] -pub type GrpriW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bits 0:4 - Arbitration Group For Channel n"] - #[inline(always)] - pub fn grpri(&self) -> GrpriR { - GrpriR::new((self.bits & 0x1f) as u8) - } -} -impl W { - #[doc = "Bits 0:4 - Arbitration Group For Channel n"] - #[inline(always)] - pub fn grpri(&mut self) -> GrpriW { - GrpriW::new(self, 0) - } -} -#[doc = "Channel Arbitration Group\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_grpri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_grpri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ChGrpriSpec; -impl crate::RegisterSpec for ChGrpriSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ch_grpri::R`](R) reader structure"] -impl crate::Readable for ChGrpriSpec {} -#[doc = "`write(|w| ..)` method takes [`ch_grpri::W`](W) writer structure"] -impl crate::Writable for ChGrpriSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CH_GRPRI[%s] to value 0"] -impl crate::Resettable for ChGrpriSpec {} diff --git a/mcxa276-pac/src/dma0/mp_csr.rs b/mcxa276-pac/src/dma0/mp_csr.rs deleted file mode 100644 index fb7aab24f..000000000 --- a/mcxa276-pac/src/dma0/mp_csr.rs +++ /dev/null @@ -1,575 +0,0 @@ -#[doc = "Register `MP_CSR` reader"] -pub type R = crate::R; -#[doc = "Register `MP_CSR` writer"] -pub type W = crate::W; -#[doc = "Enable Debug\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Edbg { - #[doc = "0: Debug mode disabled"] - Disable = 0, - #[doc = "1: Debug mode is enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Edbg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EDBG` reader - Enable Debug"] -pub type EdbgR = crate::BitReader; -impl EdbgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edbg { - match self.bits { - false => Edbg::Disable, - true => Edbg::Enable, - } - } - #[doc = "Debug mode disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Edbg::Disable - } - #[doc = "Debug mode is enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Edbg::Enable - } -} -#[doc = "Field `EDBG` writer - Enable Debug"] -pub type EdbgW<'a, REG> = crate::BitWriter<'a, REG, Edbg>; -impl<'a, REG> EdbgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Debug mode disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Edbg::Disable) - } - #[doc = "Debug mode is enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Edbg::Enable) - } -} -#[doc = "Enable Round Robin Channel Arbitration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erca { - #[doc = "0: Round-robin channel arbitration disabled"] - Disable = 0, - #[doc = "1: Round-robin channel arbitration enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erca) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERCA` reader - Enable Round Robin Channel Arbitration"] -pub type ErcaR = crate::BitReader; -impl ErcaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erca { - match self.bits { - false => Erca::Disable, - true => Erca::Enable, - } - } - #[doc = "Round-robin channel arbitration disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Erca::Disable - } - #[doc = "Round-robin channel arbitration enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Erca::Enable - } -} -#[doc = "Field `ERCA` writer - Enable Round Robin Channel Arbitration"] -pub type ErcaW<'a, REG> = crate::BitWriter<'a, REG, Erca>; -impl<'a, REG> ErcaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Round-robin channel arbitration disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Erca::Disable) - } - #[doc = "Round-robin channel arbitration enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Erca::Enable) - } -} -#[doc = "Halt After Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hae { - #[doc = "0: Normal operation"] - NormalOperation = 0, - #[doc = "1: Any error causes the HALT field to be set to 1"] - Halt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HAE` reader - Halt After Error"] -pub type HaeR = crate::BitReader; -impl HaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hae { - match self.bits { - false => Hae::NormalOperation, - true => Hae::Halt, - } - } - #[doc = "Normal operation"] - #[inline(always)] - pub fn is_normal_operation(&self) -> bool { - *self == Hae::NormalOperation - } - #[doc = "Any error causes the HALT field to be set to 1"] - #[inline(always)] - pub fn is_halt(&self) -> bool { - *self == Hae::Halt - } -} -#[doc = "Field `HAE` writer - Halt After Error"] -pub type HaeW<'a, REG> = crate::BitWriter<'a, REG, Hae>; -impl<'a, REG> HaeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal operation"] - #[inline(always)] - pub fn normal_operation(self) -> &'a mut crate::W { - self.variant(Hae::NormalOperation) - } - #[doc = "Any error causes the HALT field to be set to 1"] - #[inline(always)] - pub fn halt(self) -> &'a mut crate::W { - self.variant(Hae::Halt) - } -} -#[doc = "Halt DMA Operations\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Normal operation"] - NormalOperation = 0, - #[doc = "1: Stall the start of any new channels"] - Stall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt DMA Operations"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::NormalOperation, - true => Halt::Stall, - } - } - #[doc = "Normal operation"] - #[inline(always)] - pub fn is_normal_operation(&self) -> bool { - *self == Halt::NormalOperation - } - #[doc = "Stall the start of any new channels"] - #[inline(always)] - pub fn is_stall(&self) -> bool { - *self == Halt::Stall - } -} -#[doc = "Field `HALT` writer - Halt DMA Operations"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal operation"] - #[inline(always)] - pub fn normal_operation(self) -> &'a mut crate::W { - self.variant(Halt::NormalOperation) - } - #[doc = "Stall the start of any new channels"] - #[inline(always)] - pub fn stall(self) -> &'a mut crate::W { - self.variant(Halt::Stall) - } -} -#[doc = "Global Channel Linking Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gclc { - #[doc = "0: Channel linking disabled for all channels"] - Disable = 0, - #[doc = "1: Channel linking available and controlled by each channel's link settings"] - Available = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gclc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GCLC` reader - Global Channel Linking Control"] -pub type GclcR = crate::BitReader; -impl GclcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gclc { - match self.bits { - false => Gclc::Disable, - true => Gclc::Available, - } - } - #[doc = "Channel linking disabled for all channels"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Gclc::Disable - } - #[doc = "Channel linking available and controlled by each channel's link settings"] - #[inline(always)] - pub fn is_available(&self) -> bool { - *self == Gclc::Available - } -} -#[doc = "Field `GCLC` writer - Global Channel Linking Control"] -pub type GclcW<'a, REG> = crate::BitWriter<'a, REG, Gclc>; -impl<'a, REG> GclcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel linking disabled for all channels"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Gclc::Disable) - } - #[doc = "Channel linking available and controlled by each channel's link settings"] - #[inline(always)] - pub fn available(self) -> &'a mut crate::W { - self.variant(Gclc::Available) - } -} -#[doc = "Global Master ID Replication Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gmrc { - #[doc = "0: Master ID replication disabled for all channels"] - Disable = 0, - #[doc = "1: Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"] - Available = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gmrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GMRC` reader - Global Master ID Replication Control"] -pub type GmrcR = crate::BitReader; -impl GmrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gmrc { - match self.bits { - false => Gmrc::Disable, - true => Gmrc::Available, - } - } - #[doc = "Master ID replication disabled for all channels"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Gmrc::Disable - } - #[doc = "Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"] - #[inline(always)] - pub fn is_available(&self) -> bool { - *self == Gmrc::Available - } -} -#[doc = "Field `GMRC` writer - Global Master ID Replication Control"] -pub type GmrcW<'a, REG> = crate::BitWriter<'a, REG, Gmrc>; -impl<'a, REG> GmrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Master ID replication disabled for all channels"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Gmrc::Disable) - } - #[doc = "Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"] - #[inline(always)] - pub fn available(self) -> &'a mut crate::W { - self.variant(Gmrc::Available) - } -} -#[doc = "Cancel Transfer With Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ecx { - #[doc = "0: Normal operation"] - NormalOperation = 0, - #[doc = "1: Cancel the remaining data transfer"] - Cancel = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ecx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ECX` reader - Cancel Transfer With Error"] -pub type EcxR = crate::BitReader; -impl EcxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ecx { - match self.bits { - false => Ecx::NormalOperation, - true => Ecx::Cancel, - } - } - #[doc = "Normal operation"] - #[inline(always)] - pub fn is_normal_operation(&self) -> bool { - *self == Ecx::NormalOperation - } - #[doc = "Cancel the remaining data transfer"] - #[inline(always)] - pub fn is_cancel(&self) -> bool { - *self == Ecx::Cancel - } -} -#[doc = "Field `ECX` writer - Cancel Transfer With Error"] -pub type EcxW<'a, REG> = crate::BitWriter<'a, REG, Ecx>; -impl<'a, REG> EcxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal operation"] - #[inline(always)] - pub fn normal_operation(self) -> &'a mut crate::W { - self.variant(Ecx::NormalOperation) - } - #[doc = "Cancel the remaining data transfer"] - #[inline(always)] - pub fn cancel(self) -> &'a mut crate::W { - self.variant(Ecx::Cancel) - } -} -#[doc = "Cancel Transfer\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx { - #[doc = "0: Normal operation"] - NormalOperation = 0, - #[doc = "1: Cancel the remaining data transfer"] - DataTransferCancel = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX` reader - Cancel Transfer"] -pub type CxR = crate::BitReader; -impl CxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx { - match self.bits { - false => Cx::NormalOperation, - true => Cx::DataTransferCancel, - } - } - #[doc = "Normal operation"] - #[inline(always)] - pub fn is_normal_operation(&self) -> bool { - *self == Cx::NormalOperation - } - #[doc = "Cancel the remaining data transfer"] - #[inline(always)] - pub fn is_data_transfer_cancel(&self) -> bool { - *self == Cx::DataTransferCancel - } -} -#[doc = "Field `CX` writer - Cancel Transfer"] -pub type CxW<'a, REG> = crate::BitWriter<'a, REG, Cx>; -impl<'a, REG> CxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal operation"] - #[inline(always)] - pub fn normal_operation(self) -> &'a mut crate::W { - self.variant(Cx::NormalOperation) - } - #[doc = "Cancel the remaining data transfer"] - #[inline(always)] - pub fn data_transfer_cancel(self) -> &'a mut crate::W { - self.variant(Cx::DataTransferCancel) - } -} -#[doc = "Field `ACTIVE_ID` reader - Active Channel ID"] -pub type ActiveIdR = crate::FieldReader; -#[doc = "DMA Active Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Active { - #[doc = "0: eDMA is idle"] - Idle = 0, - #[doc = "1: eDMA is executing a channel"] - Execution = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Active) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ACTIVE` reader - DMA Active Status"] -pub type ActiveR = crate::BitReader; -impl ActiveR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Active { - match self.bits { - false => Active::Idle, - true => Active::Execution, - } - } - #[doc = "eDMA is idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Active::Idle - } - #[doc = "eDMA is executing a channel"] - #[inline(always)] - pub fn is_execution(&self) -> bool { - *self == Active::Execution - } -} -impl R { - #[doc = "Bit 1 - Enable Debug"] - #[inline(always)] - pub fn edbg(&self) -> EdbgR { - EdbgR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"] - #[inline(always)] - pub fn erca(&self) -> ErcaR { - ErcaR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - Halt After Error"] - #[inline(always)] - pub fn hae(&self) -> HaeR { - HaeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Halt DMA Operations"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Global Channel Linking Control"] - #[inline(always)] - pub fn gclc(&self) -> GclcR { - GclcR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Global Master ID Replication Control"] - #[inline(always)] - pub fn gmrc(&self) -> GmrcR { - GmrcR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Cancel Transfer With Error"] - #[inline(always)] - pub fn ecx(&self) -> EcxR { - EcxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Cancel Transfer"] - #[inline(always)] - pub fn cx(&self) -> CxR { - CxR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 24:26 - Active Channel ID"] - #[inline(always)] - pub fn active_id(&self) -> ActiveIdR { - ActiveIdR::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 31 - DMA Active Status"] - #[inline(always)] - pub fn active(&self) -> ActiveR { - ActiveR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - Enable Debug"] - #[inline(always)] - pub fn edbg(&mut self) -> EdbgW { - EdbgW::new(self, 1) - } - #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"] - #[inline(always)] - pub fn erca(&mut self) -> ErcaW { - ErcaW::new(self, 2) - } - #[doc = "Bit 4 - Halt After Error"] - #[inline(always)] - pub fn hae(&mut self) -> HaeW { - HaeW::new(self, 4) - } - #[doc = "Bit 5 - Halt DMA Operations"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 5) - } - #[doc = "Bit 6 - Global Channel Linking Control"] - #[inline(always)] - pub fn gclc(&mut self) -> GclcW { - GclcW::new(self, 6) - } - #[doc = "Bit 7 - Global Master ID Replication Control"] - #[inline(always)] - pub fn gmrc(&mut self) -> GmrcW { - GmrcW::new(self, 7) - } - #[doc = "Bit 8 - Cancel Transfer With Error"] - #[inline(always)] - pub fn ecx(&mut self) -> EcxW { - EcxW::new(self, 8) - } - #[doc = "Bit 9 - Cancel Transfer"] - #[inline(always)] - pub fn cx(&mut self) -> CxW { - CxW::new(self, 9) - } -} -#[doc = "Management Page Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mp_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MpCsrSpec; -impl crate::RegisterSpec for MpCsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mp_csr::R`](R) reader structure"] -impl crate::Readable for MpCsrSpec {} -#[doc = "`write(|w| ..)` method takes [`mp_csr::W`](W) writer structure"] -impl crate::Writable for MpCsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MP_CSR to value 0x0031_0000"] -impl crate::Resettable for MpCsrSpec { - const RESET_VALUE: u32 = 0x0031_0000; -} diff --git a/mcxa276-pac/src/dma0/mp_es.rs b/mcxa276-pac/src/dma0/mp_es.rs deleted file mode 100644 index 60cba71dd..000000000 --- a/mcxa276-pac/src/dma0/mp_es.rs +++ /dev/null @@ -1,430 +0,0 @@ -#[doc = "Register `MP_ES` reader"] -pub type R = crate::R; -#[doc = "Destination Bus Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dbe { - #[doc = "0: No destination bus error"] - NoError = 0, - #[doc = "1: Last recorded error was a bus error on a destination write"] - BusError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dbe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBE` reader - Destination Bus Error"] -pub type DbeR = crate::BitReader; -impl DbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dbe { - match self.bits { - false => Dbe::NoError, - true => Dbe::BusError, - } - } - #[doc = "No destination bus error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Dbe::NoError - } - #[doc = "Last recorded error was a bus error on a destination write"] - #[inline(always)] - pub fn is_bus_error(&self) -> bool { - *self == Dbe::BusError - } -} -#[doc = "Source Bus Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sbe { - #[doc = "0: No source bus error"] - NoError = 0, - #[doc = "1: Last recorded error was a bus error on a source read"] - BusError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sbe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SBE` reader - Source Bus Error"] -pub type SbeR = crate::BitReader; -impl SbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sbe { - match self.bits { - false => Sbe::NoError, - true => Sbe::BusError, - } - } - #[doc = "No source bus error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Sbe::NoError - } - #[doc = "Last recorded error was a bus error on a source read"] - #[inline(always)] - pub fn is_bus_error(&self) -> bool { - *self == Sbe::BusError - } -} -#[doc = "Scatter/Gather Configuration Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sge { - #[doc = "0: No scatter/gather configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] - ConfigurationError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sge) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SGE` reader - Scatter/Gather Configuration Error"] -pub type SgeR = crate::BitReader; -impl SgeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sge { - match self.bits { - false => Sge::NoError, - true => Sge::ConfigurationError, - } - } - #[doc = "No scatter/gather configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Sge::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] - #[inline(always)] - pub fn is_configuration_error(&self) -> bool { - *self == Sge::ConfigurationError - } -} -#[doc = "NBYTES/CITER Configuration Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nce { - #[doc = "0: No NBYTES/CITER configuration error"] - NoError = 0, - #[doc = "1: The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error"] - ConfigurationError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nce) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NCE` reader - NBYTES/CITER Configuration Error"] -pub type NceR = crate::BitReader; -impl NceR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nce { - match self.bits { - false => Nce::NoError, - true => Nce::ConfigurationError, - } - } - #[doc = "No NBYTES/CITER configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Nce::NoError - } - #[doc = "The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error"] - #[inline(always)] - pub fn is_configuration_error(&self) -> bool { - *self == Nce::ConfigurationError - } -} -#[doc = "Destination Offset Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Doe { - #[doc = "0: No destination offset configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DOFF field"] - ConfigurationError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Doe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DOE` reader - Destination Offset Error"] -pub type DoeR = crate::BitReader; -impl DoeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Doe { - match self.bits { - false => Doe::NoError, - true => Doe::ConfigurationError, - } - } - #[doc = "No destination offset configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Doe::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_DOFF field"] - #[inline(always)] - pub fn is_configuration_error(&self) -> bool { - *self == Doe::ConfigurationError - } -} -#[doc = "Destination Address Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dae { - #[doc = "0: No destination address configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DADDR field"] - ConfigurationError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAE` reader - Destination Address Error"] -pub type DaeR = crate::BitReader; -impl DaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dae { - match self.bits { - false => Dae::NoError, - true => Dae::ConfigurationError, - } - } - #[doc = "No destination address configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Dae::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_DADDR field"] - #[inline(always)] - pub fn is_configuration_error(&self) -> bool { - *self == Dae::ConfigurationError - } -} -#[doc = "Source Offset Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soe { - #[doc = "0: No source offset configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SOFF field"] - ConfigurationError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOE` reader - Source Offset Error"] -pub type SoeR = crate::BitReader; -impl SoeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soe { - match self.bits { - false => Soe::NoError, - true => Soe::ConfigurationError, - } - } - #[doc = "No source offset configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Soe::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_SOFF field"] - #[inline(always)] - pub fn is_configuration_error(&self) -> bool { - *self == Soe::ConfigurationError - } -} -#[doc = "Source Address Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sae { - #[doc = "0: No source address configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SADDR field"] - ConfigurationError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SAE` reader - Source Address Error"] -pub type SaeR = crate::BitReader; -impl SaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sae { - match self.bits { - false => Sae::NoError, - true => Sae::ConfigurationError, - } - } - #[doc = "No source address configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Sae::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_SADDR field"] - #[inline(always)] - pub fn is_configuration_error(&self) -> bool { - *self == Sae::ConfigurationError - } -} -#[doc = "Transfer Canceled\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ecx { - #[doc = "0: No canceled transfers"] - NoCanceledTransfers = 0, - #[doc = "1: Last recorded entry was a canceled transfer by the error cancel transfer input"] - CanceledTransfer = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ecx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ECX` reader - Transfer Canceled"] -pub type EcxR = crate::BitReader; -impl EcxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ecx { - match self.bits { - false => Ecx::NoCanceledTransfers, - true => Ecx::CanceledTransfer, - } - } - #[doc = "No canceled transfers"] - #[inline(always)] - pub fn is_no_canceled_transfers(&self) -> bool { - *self == Ecx::NoCanceledTransfers - } - #[doc = "Last recorded entry was a canceled transfer by the error cancel transfer input"] - #[inline(always)] - pub fn is_canceled_transfer(&self) -> bool { - *self == Ecx::CanceledTransfer - } -} -#[doc = "Field `ERRCHN` reader - Error Channel Number or Canceled Channel Number"] -pub type ErrchnR = crate::FieldReader; -#[doc = "Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Vld { - #[doc = "0: No CHn_ES\\[ERR\\] fields are set to 1"] - NoFieldSetOne = 0, - #[doc = "1: At least one CHn_ES\\[ERR\\] field is set to 1, indicating a valid error exists that software has not cleared"] - AtleastOneField = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Vld) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VLD` reader - Valid"] -pub type VldR = crate::BitReader; -impl VldR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Vld { - match self.bits { - false => Vld::NoFieldSetOne, - true => Vld::AtleastOneField, - } - } - #[doc = "No CHn_ES\\[ERR\\] fields are set to 1"] - #[inline(always)] - pub fn is_no_field_set_one(&self) -> bool { - *self == Vld::NoFieldSetOne - } - #[doc = "At least one CHn_ES\\[ERR\\] field is set to 1, indicating a valid error exists that software has not cleared"] - #[inline(always)] - pub fn is_atleast_one_field(&self) -> bool { - *self == Vld::AtleastOneField - } -} -impl R { - #[doc = "Bit 0 - Destination Bus Error"] - #[inline(always)] - pub fn dbe(&self) -> DbeR { - DbeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Source Bus Error"] - #[inline(always)] - pub fn sbe(&self) -> SbeR { - SbeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Scatter/Gather Configuration Error"] - #[inline(always)] - pub fn sge(&self) -> SgeR { - SgeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - NBYTES/CITER Configuration Error"] - #[inline(always)] - pub fn nce(&self) -> NceR { - NceR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Destination Offset Error"] - #[inline(always)] - pub fn doe(&self) -> DoeR { - DoeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Destination Address Error"] - #[inline(always)] - pub fn dae(&self) -> DaeR { - DaeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Source Offset Error"] - #[inline(always)] - pub fn soe(&self) -> SoeR { - SoeR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Source Address Error"] - #[inline(always)] - pub fn sae(&self) -> SaeR { - SaeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Transfer Canceled"] - #[inline(always)] - pub fn ecx(&self) -> EcxR { - EcxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 24:26 - Error Channel Number or Canceled Channel Number"] - #[inline(always)] - pub fn errchn(&self) -> ErrchnR { - ErrchnR::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 31 - Valid"] - #[inline(always)] - pub fn vld(&self) -> VldR { - VldR::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "Management Page Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_es::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MpEsSpec; -impl crate::RegisterSpec for MpEsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mp_es::R`](R) reader structure"] -impl crate::Readable for MpEsSpec {} -#[doc = "`reset()` method sets MP_ES to value 0"] -impl crate::Resettable for MpEsSpec {} diff --git a/mcxa276-pac/src/dma0/mp_hrs.rs b/mcxa276-pac/src/dma0/mp_hrs.rs deleted file mode 100644 index 460f3dad0..000000000 --- a/mcxa276-pac/src/dma0/mp_hrs.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `MP_HRS` reader"] -pub type R = crate::R; -#[doc = "Field `HRS` reader - Hardware Request Status"] -pub type HrsR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Hardware Request Status"] - #[inline(always)] - pub fn hrs(&self) -> HrsR { - HrsR::new(self.bits) - } -} -#[doc = "Management Page Hardware Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_hrs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MpHrsSpec; -impl crate::RegisterSpec for MpHrsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mp_hrs::R`](R) reader structure"] -impl crate::Readable for MpHrsSpec {} -#[doc = "`reset()` method sets MP_HRS to value 0"] -impl crate::Resettable for MpHrsSpec {} diff --git a/mcxa276-pac/src/dma0/mp_int.rs b/mcxa276-pac/src/dma0/mp_int.rs deleted file mode 100644 index 6807bede7..000000000 --- a/mcxa276-pac/src/dma0/mp_int.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `MP_INT` reader"] -pub type R = crate::R; -#[doc = "Field `INT` reader - Interrupt Request Status"] -pub type IntR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Interrupt Request Status"] - #[inline(always)] - pub fn int(&self) -> IntR { - IntR::new((self.bits & 0xff) as u8) - } -} -#[doc = "Management Page Interrupt Request Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_int::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MpIntSpec; -impl crate::RegisterSpec for MpIntSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mp_int::R`](R) reader structure"] -impl crate::Readable for MpIntSpec {} -#[doc = "`reset()` method sets MP_INT to value 0"] -impl crate::Resettable for MpIntSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0.rs b/mcxa276-pac/src/edma_0_tcd0.rs deleted file mode 100644 index 185852cca..000000000 --- a/mcxa276-pac/src/edma_0_tcd0.rs +++ /dev/null @@ -1,26 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - tcd: (), -} -impl RegisterBlock { - #[doc = "0x00..0x200 - Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] - #[inline(always)] - pub const fn tcd(&self, n: usize) -> &Tcd { - #[allow(clippy::no_effect)] - [(); 8][n]; - unsafe { &*core::ptr::from_ref(self).cast::().add(4096 * n).cast() } - } - #[doc = "Iterator for array of:"] - #[doc = "0x00..0x200 - Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] - #[inline(always)] - pub fn tcd_iter(&self) -> impl Iterator { - (0..8) - .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(4096 * n).cast() }) - } -} -#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] -pub use self::tcd::Tcd; -#[doc = r"Cluster"] -#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] -pub mod tcd; diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd.rs b/mcxa276-pac/src/edma_0_tcd0/tcd.rs deleted file mode 100644 index 675be7afd..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd.rs +++ /dev/null @@ -1,229 +0,0 @@ -#[repr(C)] -#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF"] -#[doc(alias = "TCD")] -pub struct Tcd { - ch_csr: ChCsr, - ch_es: ChEs, - ch_int: ChInt, - ch_sbr: ChSbr, - ch_pri: ChPri, - ch_mux: ChMux, - _reserved6: [u8; 0x08], - tcd_saddr: TcdSaddr, - tcd_soff: TcdSoff, - tcd_attr: TcdAttr, - _reserved_9_mloffno_tcd_nbytes_mloffno: [u8; 0x04], - tcd_slast_sda: TcdSlastSda, - tcd_daddr: TcdDaddr, - tcd_doff: TcdDoff, - _reserved_13_elinkno_tcd_citer_elinkno: [u8; 0x02], - tcd_dlast_sga: TcdDlastSga, - tcd_csr: TcdCsr, - _reserved_16_elinkno_tcd_biter_elinkno: [u8; 0x02], -} -impl Tcd { - #[doc = "0x00 - Channel Control and Status"] - #[inline(always)] - pub const fn ch_csr(&self) -> &ChCsr { - &self.ch_csr - } - #[doc = "0x04 - Channel Error Status"] - #[inline(always)] - pub const fn ch_es(&self) -> &ChEs { - &self.ch_es - } - #[doc = "0x08 - Channel Interrupt Status"] - #[inline(always)] - pub const fn ch_int(&self) -> &ChInt { - &self.ch_int - } - #[doc = "0x0c - Channel System Bus"] - #[inline(always)] - pub const fn ch_sbr(&self) -> &ChSbr { - &self.ch_sbr - } - #[doc = "0x10 - Channel Priority"] - #[inline(always)] - pub const fn ch_pri(&self) -> &ChPri { - &self.ch_pri - } - #[doc = "0x14 - Channel Multiplexor Configuration"] - #[inline(always)] - pub const fn ch_mux(&self) -> &ChMux { - &self.ch_mux - } - #[doc = "0x20 - TCD Source Address"] - #[inline(always)] - pub const fn tcd_saddr(&self) -> &TcdSaddr { - &self.tcd_saddr - } - #[doc = "0x24 - TCD Signed Source Address Offset"] - #[inline(always)] - pub const fn tcd_soff(&self) -> &TcdSoff { - &self.tcd_soff - } - #[doc = "0x26 - TCD Transfer Attributes"] - #[inline(always)] - pub const fn tcd_attr(&self) -> &TcdAttr { - &self.tcd_attr - } - #[doc = "0x28 - TCD Transfer Size with Minor Loop Offsets"] - #[inline(always)] - pub const fn mloffyes_tcd_nbytes_mloffyes(&self) -> &MloffyesTcdNbytesMloffyes { - unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } - } - #[doc = "0x28 - TCD Transfer Size Without Minor Loop Offsets"] - #[inline(always)] - pub const fn mloffno_tcd_nbytes_mloffno(&self) -> &MloffnoTcdNbytesMloffno { - unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } - } - #[doc = "0x2c - TCD Last Source Address Adjustment / Store DADDR Address"] - #[inline(always)] - pub const fn tcd_slast_sda(&self) -> &TcdSlastSda { - &self.tcd_slast_sda - } - #[doc = "0x30 - TCD Destination Address"] - #[inline(always)] - pub const fn tcd_daddr(&self) -> &TcdDaddr { - &self.tcd_daddr - } - #[doc = "0x34 - TCD Signed Destination Address Offset"] - #[inline(always)] - pub const fn tcd_doff(&self) -> &TcdDoff { - &self.tcd_doff - } - #[doc = "0x36 - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"] - #[inline(always)] - pub const fn elinkyes_tcd_citer_elinkyes(&self) -> &ElinkyesTcdCiterElinkyes { - unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } - } - #[doc = "0x36 - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"] - #[inline(always)] - pub const fn elinkno_tcd_citer_elinkno(&self) -> &ElinknoTcdCiterElinkno { - unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } - } - #[doc = "0x38 - TCD Last Destination Address Adjustment / Scatter Gather Address"] - #[inline(always)] - pub const fn tcd_dlast_sga(&self) -> &TcdDlastSga { - &self.tcd_dlast_sga - } - #[doc = "0x3c - TCD Control and Status"] - #[inline(always)] - pub const fn tcd_csr(&self) -> &TcdCsr { - &self.tcd_csr - } - #[doc = "0x3e - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"] - #[inline(always)] - pub const fn elinkyes_tcd_biter_elinkyes(&self) -> &ElinkyesTcdBiterElinkyes { - unsafe { &*core::ptr::from_ref(self).cast::().add(62).cast() } - } - #[doc = "0x3e - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"] - #[inline(always)] - pub const fn elinkno_tcd_biter_elinkno(&self) -> &ElinknoTcdBiterElinkno { - unsafe { &*core::ptr::from_ref(self).cast::().add(62).cast() } - } -} -#[doc = "CH_CSR (rw) register accessor: Channel Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_csr`] module"] -#[doc(alias = "CH_CSR")] -pub type ChCsr = crate::Reg; -#[doc = "Channel Control and Status"] -pub mod ch_csr; -#[doc = "CH_ES (rw) register accessor: Channel Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_es::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_es::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_es`] module"] -#[doc(alias = "CH_ES")] -pub type ChEs = crate::Reg; -#[doc = "Channel Error Status"] -pub mod ch_es; -#[doc = "CH_INT (rw) register accessor: Channel Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_int`] module"] -#[doc(alias = "CH_INT")] -pub type ChInt = crate::Reg; -#[doc = "Channel Interrupt Status"] -pub mod ch_int; -#[doc = "CH_SBR (rw) register accessor: Channel System Bus\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_sbr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_sbr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_sbr`] module"] -#[doc(alias = "CH_SBR")] -pub type ChSbr = crate::Reg; -#[doc = "Channel System Bus"] -pub mod ch_sbr; -#[doc = "CH_PRI (rw) register accessor: Channel Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_pri`] module"] -#[doc(alias = "CH_PRI")] -pub type ChPri = crate::Reg; -#[doc = "Channel Priority"] -pub mod ch_pri; -#[doc = "CH_MUX (rw) register accessor: Channel Multiplexor Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_mux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_mux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_mux`] module"] -#[doc(alias = "CH_MUX")] -pub type ChMux = crate::Reg; -#[doc = "Channel Multiplexor Configuration"] -pub mod ch_mux; -#[doc = "TCD_SADDR (rw) register accessor: TCD Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_saddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_saddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_saddr`] module"] -#[doc(alias = "TCD_SADDR")] -pub type TcdSaddr = crate::Reg; -#[doc = "TCD Source Address"] -pub mod tcd_saddr; -#[doc = "TCD_SOFF (rw) register accessor: TCD Signed Source Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_soff::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_soff::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_soff`] module"] -#[doc(alias = "TCD_SOFF")] -pub type TcdSoff = crate::Reg; -#[doc = "TCD Signed Source Address Offset"] -pub mod tcd_soff; -#[doc = "TCD_ATTR (rw) register accessor: TCD Transfer Attributes\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_attr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_attr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_attr`] module"] -#[doc(alias = "TCD_ATTR")] -pub type TcdAttr = crate::Reg; -#[doc = "TCD Transfer Attributes"] -pub mod tcd_attr; -#[doc = "MLOFFNO_TCD_NBYTES_MLOFFNO (rw) register accessor: TCD Transfer Size Without Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffno_tcd_nbytes_mloffno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffno_tcd_nbytes_mloffno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mloffno_tcd_nbytes_mloffno`] module"] -#[doc(alias = "MLOFFNO_TCD_NBYTES_MLOFFNO")] -pub type MloffnoTcdNbytesMloffno = - crate::Reg; -#[doc = "TCD Transfer Size Without Minor Loop Offsets"] -pub mod mloffno_tcd_nbytes_mloffno; -#[doc = "MLOFFYES_TCD_NBYTES_MLOFFYES (rw) register accessor: TCD Transfer Size with Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffyes_tcd_nbytes_mloffyes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffyes_tcd_nbytes_mloffyes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mloffyes_tcd_nbytes_mloffyes`] module"] -#[doc(alias = "MLOFFYES_TCD_NBYTES_MLOFFYES")] -pub type MloffyesTcdNbytesMloffyes = - crate::Reg; -#[doc = "TCD Transfer Size with Minor Loop Offsets"] -pub mod mloffyes_tcd_nbytes_mloffyes; -#[doc = "TCD_SLAST_SDA (rw) register accessor: TCD Last Source Address Adjustment / Store DADDR Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_slast_sda::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_slast_sda::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_slast_sda`] module"] -#[doc(alias = "TCD_SLAST_SDA")] -pub type TcdSlastSda = crate::Reg; -#[doc = "TCD Last Source Address Adjustment / Store DADDR Address"] -pub mod tcd_slast_sda; -#[doc = "TCD_DADDR (rw) register accessor: TCD Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_daddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_daddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_daddr`] module"] -#[doc(alias = "TCD_DADDR")] -pub type TcdDaddr = crate::Reg; -#[doc = "TCD Destination Address"] -pub mod tcd_daddr; -#[doc = "TCD_DOFF (rw) register accessor: TCD Signed Destination Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_doff::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_doff::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_doff`] module"] -#[doc(alias = "TCD_DOFF")] -pub type TcdDoff = crate::Reg; -#[doc = "TCD Signed Destination Address Offset"] -pub mod tcd_doff; -#[doc = "ELINKNO_TCD_CITER_ELINKNO (rw) register accessor: TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_citer_elinkno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_citer_elinkno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkno_tcd_citer_elinkno`] module"] -#[doc(alias = "ELINKNO_TCD_CITER_ELINKNO")] -pub type ElinknoTcdCiterElinkno = crate::Reg; -#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"] -pub mod elinkno_tcd_citer_elinkno; -#[doc = "ELINKYES_TCD_CITER_ELINKYES (rw) register accessor: TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_citer_elinkyes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_citer_elinkyes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkyes_tcd_citer_elinkyes`] module"] -#[doc(alias = "ELINKYES_TCD_CITER_ELINKYES")] -pub type ElinkyesTcdCiterElinkyes = - crate::Reg; -#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"] -pub mod elinkyes_tcd_citer_elinkyes; -#[doc = "TCD_DLAST_SGA (rw) register accessor: TCD Last Destination Address Adjustment / Scatter Gather Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_dlast_sga::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_dlast_sga::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_dlast_sga`] module"] -#[doc(alias = "TCD_DLAST_SGA")] -pub type TcdDlastSga = crate::Reg; -#[doc = "TCD Last Destination Address Adjustment / Scatter Gather Address"] -pub mod tcd_dlast_sga; -#[doc = "TCD_CSR (rw) register accessor: TCD Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcd_csr`] module"] -#[doc(alias = "TCD_CSR")] -pub type TcdCsr = crate::Reg; -#[doc = "TCD Control and Status"] -pub mod tcd_csr; -#[doc = "ELINKNO_TCD_BITER_ELINKNO (rw) register accessor: TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_biter_elinkno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_biter_elinkno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkno_tcd_biter_elinkno`] module"] -#[doc(alias = "ELINKNO_TCD_BITER_ELINKNO")] -pub type ElinknoTcdBiterElinkno = crate::Reg; -#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"] -pub mod elinkno_tcd_biter_elinkno; -#[doc = "ELINKYES_TCD_BITER_ELINKYES (rw) register accessor: TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_biter_elinkyes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_biter_elinkyes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@elinkyes_tcd_biter_elinkyes`] module"] -#[doc(alias = "ELINKYES_TCD_BITER_ELINKYES")] -pub type ElinkyesTcdBiterElinkyes = - crate::Reg; -#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"] -pub mod elinkyes_tcd_biter_elinkyes; diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs deleted file mode 100644 index 56aa4348b..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_csr.rs +++ /dev/null @@ -1,295 +0,0 @@ -#[doc = "Register `CH_CSR` reader"] -pub type R = crate::R; -#[doc = "Register `CH_CSR` writer"] -pub type W = crate::W; -#[doc = "Enable DMA Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erq { - #[doc = "0: DMA hardware request signal for corresponding channel disabled"] - Disable = 0, - #[doc = "1: DMA hardware request signal for corresponding channel enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERQ` reader - Enable DMA Request"] -pub type ErqR = crate::BitReader; -impl ErqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erq { - match self.bits { - false => Erq::Disable, - true => Erq::Enable, - } - } - #[doc = "DMA hardware request signal for corresponding channel disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Erq::Disable - } - #[doc = "DMA hardware request signal for corresponding channel enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Erq::Enable - } -} -#[doc = "Field `ERQ` writer - Enable DMA Request"] -pub type ErqW<'a, REG> = crate::BitWriter<'a, REG, Erq>; -impl<'a, REG> ErqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DMA hardware request signal for corresponding channel disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Erq::Disable) - } - #[doc = "DMA hardware request signal for corresponding channel enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Erq::Enable) - } -} -#[doc = "Enable Asynchronous DMA Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Earq { - #[doc = "0: Disable asynchronous DMA request for the channel"] - Disable = 0, - #[doc = "1: Enable asynchronous DMA request for the channel"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Earq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EARQ` reader - Enable Asynchronous DMA Request"] -pub type EarqR = crate::BitReader; -impl EarqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Earq { - match self.bits { - false => Earq::Disable, - true => Earq::Enable, - } - } - #[doc = "Disable asynchronous DMA request for the channel"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Earq::Disable - } - #[doc = "Enable asynchronous DMA request for the channel"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Earq::Enable - } -} -#[doc = "Field `EARQ` writer - Enable Asynchronous DMA Request"] -pub type EarqW<'a, REG> = crate::BitWriter<'a, REG, Earq>; -impl<'a, REG> EarqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable asynchronous DMA request for the channel"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Earq::Disable) - } - #[doc = "Enable asynchronous DMA request for the channel"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Earq::Enable) - } -} -#[doc = "Enable Error Interrupt\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Eei { - #[doc = "0: Error signal for corresponding channel does not generate error interrupt"] - NoError = 0, - #[doc = "1: Assertion of error signal for corresponding channel generates error interrupt request"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Eei) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EEI` reader - Enable Error Interrupt"] -pub type EeiR = crate::BitReader; -impl EeiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Eei { - match self.bits { - false => Eei::NoError, - true => Eei::Error, - } - } - #[doc = "Error signal for corresponding channel does not generate error interrupt"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Eei::NoError - } - #[doc = "Assertion of error signal for corresponding channel generates error interrupt request"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Eei::Error - } -} -#[doc = "Field `EEI` writer - Enable Error Interrupt"] -pub type EeiW<'a, REG> = crate::BitWriter<'a, REG, Eei>; -impl<'a, REG> EeiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error signal for corresponding channel does not generate error interrupt"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Eei::NoError) - } - #[doc = "Assertion of error signal for corresponding channel generates error interrupt request"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Eei::Error) - } -} -#[doc = "Enable Buffered Writes\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ebw { - #[doc = "0: Buffered writes on system bus disabled"] - Disable = 0, - #[doc = "1: Buffered writes on system bus enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ebw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EBW` reader - Enable Buffered Writes"] -pub type EbwR = crate::BitReader; -impl EbwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ebw { - match self.bits { - false => Ebw::Disable, - true => Ebw::Enable, - } - } - #[doc = "Buffered writes on system bus disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ebw::Disable - } - #[doc = "Buffered writes on system bus enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ebw::Enable - } -} -#[doc = "Field `EBW` writer - Enable Buffered Writes"] -pub type EbwW<'a, REG> = crate::BitWriter<'a, REG, Ebw>; -impl<'a, REG> EbwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Buffered writes on system bus disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ebw::Disable) - } - #[doc = "Buffered writes on system bus enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ebw::Enable) - } -} -#[doc = "Field `DONE` reader - Channel Done"] -pub type DoneR = crate::BitReader; -#[doc = "Field `DONE` writer - Channel Done"] -pub type DoneW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `ACTIVE` reader - Channel Active"] -pub type ActiveR = crate::BitReader; -impl R { - #[doc = "Bit 0 - Enable DMA Request"] - #[inline(always)] - pub fn erq(&self) -> ErqR { - ErqR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Enable Asynchronous DMA Request"] - #[inline(always)] - pub fn earq(&self) -> EarqR { - EarqR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Enable Error Interrupt"] - #[inline(always)] - pub fn eei(&self) -> EeiR { - EeiR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Enable Buffered Writes"] - #[inline(always)] - pub fn ebw(&self) -> EbwR { - EbwR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 30 - Channel Done"] - #[inline(always)] - pub fn done(&self) -> DoneR { - DoneR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Channel Active"] - #[inline(always)] - pub fn active(&self) -> ActiveR { - ActiveR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enable DMA Request"] - #[inline(always)] - pub fn erq(&mut self) -> ErqW { - ErqW::new(self, 0) - } - #[doc = "Bit 1 - Enable Asynchronous DMA Request"] - #[inline(always)] - pub fn earq(&mut self) -> EarqW { - EarqW::new(self, 1) - } - #[doc = "Bit 2 - Enable Error Interrupt"] - #[inline(always)] - pub fn eei(&mut self) -> EeiW { - EeiW::new(self, 2) - } - #[doc = "Bit 3 - Enable Buffered Writes"] - #[inline(always)] - pub fn ebw(&mut self) -> EbwW { - EbwW::new(self, 3) - } - #[doc = "Bit 30 - Channel Done"] - #[inline(always)] - pub fn done(&mut self) -> DoneW { - DoneW::new(self, 30) - } -} -#[doc = "Channel Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ChCsrSpec; -impl crate::RegisterSpec for ChCsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ch_csr::R`](R) reader structure"] -impl crate::Readable for ChCsrSpec {} -#[doc = "`write(|w| ..)` method takes [`ch_csr::W`](W) writer structure"] -impl crate::Writable for ChCsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x4000_0000; -} -#[doc = "`reset()` method sets CH_CSR to value 0"] -impl crate::Resettable for ChCsrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs deleted file mode 100644 index b7bd233ac..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_es.rs +++ /dev/null @@ -1,413 +0,0 @@ -#[doc = "Register `CH_ES` reader"] -pub type R = crate::R; -#[doc = "Register `CH_ES` writer"] -pub type W = crate::W; -#[doc = "Destination Bus Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dbe { - #[doc = "0: No destination bus error"] - NoError = 0, - #[doc = "1: Last recorded error was bus error on destination write"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dbe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBE` reader - Destination Bus Error"] -pub type DbeR = crate::BitReader; -impl DbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dbe { - match self.bits { - false => Dbe::NoError, - true => Dbe::Error, - } - } - #[doc = "No destination bus error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Dbe::NoError - } - #[doc = "Last recorded error was bus error on destination write"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Dbe::Error - } -} -#[doc = "Source Bus Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sbe { - #[doc = "0: No source bus error"] - NoError = 0, - #[doc = "1: Last recorded error was bus error on source read"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sbe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SBE` reader - Source Bus Error"] -pub type SbeR = crate::BitReader; -impl SbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sbe { - match self.bits { - false => Sbe::NoError, - true => Sbe::Error, - } - } - #[doc = "No source bus error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Sbe::NoError - } - #[doc = "Last recorded error was bus error on source read"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Sbe::Error - } -} -#[doc = "Scatter/Gather Configuration Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sge { - #[doc = "0: No scatter/gather configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sge) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SGE` reader - Scatter/Gather Configuration Error"] -pub type SgeR = crate::BitReader; -impl SgeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sge { - match self.bits { - false => Sge::NoError, - true => Sge::Error, - } - } - #[doc = "No scatter/gather configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Sge::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Sge::Error - } -} -#[doc = "NBYTES/CITER Configuration Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nce { - #[doc = "0: No NBYTES/CITER configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nce) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NCE` reader - NBYTES/CITER Configuration Error"] -pub type NceR = crate::BitReader; -impl NceR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nce { - match self.bits { - false => Nce::NoError, - true => Nce::Error, - } - } - #[doc = "No NBYTES/CITER configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Nce::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Nce::Error - } -} -#[doc = "Destination Offset Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Doe { - #[doc = "0: No destination offset configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DOFF field"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Doe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DOE` reader - Destination Offset Error"] -pub type DoeR = crate::BitReader; -impl DoeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Doe { - match self.bits { - false => Doe::NoError, - true => Doe::Error, - } - } - #[doc = "No destination offset configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Doe::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_DOFF field"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Doe::Error - } -} -#[doc = "Destination Address Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dae { - #[doc = "0: No destination address configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_DADDR field"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAE` reader - Destination Address Error"] -pub type DaeR = crate::BitReader; -impl DaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dae { - match self.bits { - false => Dae::NoError, - true => Dae::Error, - } - } - #[doc = "No destination address configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Dae::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_DADDR field"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Dae::Error - } -} -#[doc = "Source Offset Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soe { - #[doc = "0: No source offset configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SOFF field"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOE` reader - Source Offset Error"] -pub type SoeR = crate::BitReader; -impl SoeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soe { - match self.bits { - false => Soe::NoError, - true => Soe::Error, - } - } - #[doc = "No source offset configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Soe::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_SOFF field"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Soe::Error - } -} -#[doc = "Source Address Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sae { - #[doc = "0: No source address configuration error"] - NoError = 0, - #[doc = "1: Last recorded error was a configuration error detected in the TCDn_SADDR field"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SAE` reader - Source Address Error"] -pub type SaeR = crate::BitReader; -impl SaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sae { - match self.bits { - false => Sae::NoError, - true => Sae::Error, - } - } - #[doc = "No source address configuration error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Sae::NoError - } - #[doc = "Last recorded error was a configuration error detected in the TCDn_SADDR field"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Sae::Error - } -} -#[doc = "Error In Channel\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Err { - #[doc = "0: An error in this channel has not occurred"] - NoError = 0, - #[doc = "1: An error in this channel has occurred"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERR` reader - Error In Channel"] -pub type ErrR = crate::BitReader; -impl ErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Err { - match self.bits { - false => Err::NoError, - true => Err::Error, - } - } - #[doc = "An error in this channel has not occurred"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Err::NoError - } - #[doc = "An error in this channel has occurred"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Err::Error - } -} -#[doc = "Field `ERR` writer - Error In Channel"] -pub type ErrW<'a, REG> = crate::BitWriter1C<'a, REG, Err>; -impl<'a, REG> ErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "An error in this channel has not occurred"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Err::NoError) - } - #[doc = "An error in this channel has occurred"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Err::Error) - } -} -impl R { - #[doc = "Bit 0 - Destination Bus Error"] - #[inline(always)] - pub fn dbe(&self) -> DbeR { - DbeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Source Bus Error"] - #[inline(always)] - pub fn sbe(&self) -> SbeR { - SbeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Scatter/Gather Configuration Error"] - #[inline(always)] - pub fn sge(&self) -> SgeR { - SgeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - NBYTES/CITER Configuration Error"] - #[inline(always)] - pub fn nce(&self) -> NceR { - NceR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Destination Offset Error"] - #[inline(always)] - pub fn doe(&self) -> DoeR { - DoeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Destination Address Error"] - #[inline(always)] - pub fn dae(&self) -> DaeR { - DaeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Source Offset Error"] - #[inline(always)] - pub fn soe(&self) -> SoeR { - SoeR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Source Address Error"] - #[inline(always)] - pub fn sae(&self) -> SaeR { - SaeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 31 - Error In Channel"] - #[inline(always)] - pub fn err(&self) -> ErrR { - ErrR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 31 - Error In Channel"] - #[inline(always)] - pub fn err(&mut self) -> ErrW { - ErrW::new(self, 31) - } -} -#[doc = "Channel Error Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_es::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_es::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ChEsSpec; -impl crate::RegisterSpec for ChEsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ch_es::R`](R) reader structure"] -impl crate::Readable for ChEsSpec {} -#[doc = "`write(|w| ..)` method takes [`ch_es::W`](W) writer structure"] -impl crate::Writable for ChEsSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000; -} -#[doc = "`reset()` method sets CH_ES to value 0"] -impl crate::Resettable for ChEsSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs deleted file mode 100644 index 459d2be13..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_int.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `CH_INT` reader"] -pub type R = crate::R; -#[doc = "Register `CH_INT` writer"] -pub type W = crate::W; -#[doc = "Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int { - #[doc = "0: Interrupt request for corresponding channel cleared"] - InterruptCleared = 0, - #[doc = "1: Interrupt request for corresponding channel active"] - InterruptActive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT` reader - Interrupt Request"] -pub type IntR = crate::BitReader; -impl IntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int { - match self.bits { - false => Int::InterruptCleared, - true => Int::InterruptActive, - } - } - #[doc = "Interrupt request for corresponding channel cleared"] - #[inline(always)] - pub fn is_interrupt_cleared(&self) -> bool { - *self == Int::InterruptCleared - } - #[doc = "Interrupt request for corresponding channel active"] - #[inline(always)] - pub fn is_interrupt_active(&self) -> bool { - *self == Int::InterruptActive - } -} -#[doc = "Field `INT` writer - Interrupt Request"] -pub type IntW<'a, REG> = crate::BitWriter1C<'a, REG, Int>; -impl<'a, REG> IntW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request for corresponding channel cleared"] - #[inline(always)] - pub fn interrupt_cleared(self) -> &'a mut crate::W { - self.variant(Int::InterruptCleared) - } - #[doc = "Interrupt request for corresponding channel active"] - #[inline(always)] - pub fn interrupt_active(self) -> &'a mut crate::W { - self.variant(Int::InterruptActive) - } -} -impl R { - #[doc = "Bit 0 - Interrupt Request"] - #[inline(always)] - pub fn int(&self) -> IntR { - IntR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Interrupt Request"] - #[inline(always)] - pub fn int(&mut self) -> IntW { - IntW::new(self, 0) - } -} -#[doc = "Channel Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ChIntSpec; -impl crate::RegisterSpec for ChIntSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ch_int::R`](R) reader structure"] -impl crate::Readable for ChIntSpec {} -#[doc = "`write(|w| ..)` method takes [`ch_int::W`](W) writer structure"] -impl crate::Writable for ChIntSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; -} -#[doc = "`reset()` method sets CH_INT to value 0"] -impl crate::Resettable for ChIntSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs deleted file mode 100644 index 5b8f04c55..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_mux.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CH_MUX` reader"] -pub type R = crate::R; -#[doc = "Register `CH_MUX` writer"] -pub type W = crate::W; -#[doc = "Field `SRC` reader - Service Request Source"] -pub type SrcR = crate::FieldReader; -#[doc = "Field `SRC` writer - Service Request Source"] -pub type SrcW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bits 0:6 - Service Request Source"] - #[inline(always)] - pub fn src(&self) -> SrcR { - SrcR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Service Request Source"] - #[inline(always)] - pub fn src(&mut self) -> SrcW { - SrcW::new(self, 0) - } -} -#[doc = "Channel Multiplexor Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ChMuxSpec; -impl crate::RegisterSpec for ChMuxSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ch_mux::R`](R) reader structure"] -impl crate::Readable for ChMuxSpec {} -#[doc = "`write(|w| ..)` method takes [`ch_mux::W`](W) writer structure"] -impl crate::Writable for ChMuxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CH_MUX to value 0"] -impl crate::Resettable for ChMuxSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs deleted file mode 100644 index e21686d29..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_pri.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `CH_PRI` reader"] -pub type R = crate::R; -#[doc = "Register `CH_PRI` writer"] -pub type W = crate::W; -#[doc = "Field `APL` reader - Arbitration Priority Level"] -pub type AplR = crate::FieldReader; -#[doc = "Field `APL` writer - Arbitration Priority Level"] -pub type AplW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Disable Preempt Ability\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dpa { - #[doc = "0: Channel can suspend a lower-priority channel"] - Suspend = 0, - #[doc = "1: Channel cannot suspend any other channel, regardless of channel priority"] - CannotSuspend = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dpa) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DPA` reader - Disable Preempt Ability"] -pub type DpaR = crate::BitReader; -impl DpaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dpa { - match self.bits { - false => Dpa::Suspend, - true => Dpa::CannotSuspend, - } - } - #[doc = "Channel can suspend a lower-priority channel"] - #[inline(always)] - pub fn is_suspend(&self) -> bool { - *self == Dpa::Suspend - } - #[doc = "Channel cannot suspend any other channel, regardless of channel priority"] - #[inline(always)] - pub fn is_cannot_suspend(&self) -> bool { - *self == Dpa::CannotSuspend - } -} -#[doc = "Field `DPA` writer - Disable Preempt Ability"] -pub type DpaW<'a, REG> = crate::BitWriter<'a, REG, Dpa>; -impl<'a, REG> DpaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel can suspend a lower-priority channel"] - #[inline(always)] - pub fn suspend(self) -> &'a mut crate::W { - self.variant(Dpa::Suspend) - } - #[doc = "Channel cannot suspend any other channel, regardless of channel priority"] - #[inline(always)] - pub fn cannot_suspend(self) -> &'a mut crate::W { - self.variant(Dpa::CannotSuspend) - } -} -#[doc = "Enable Channel Preemption\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ecp { - #[doc = "0: Channel cannot be suspended by a higher-priority channel's service request"] - CannotSuspend = 0, - #[doc = "1: Channel can be temporarily suspended by a higher-priority channel's service request"] - Suspend = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ecp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ECP` reader - Enable Channel Preemption"] -pub type EcpR = crate::BitReader; -impl EcpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ecp { - match self.bits { - false => Ecp::CannotSuspend, - true => Ecp::Suspend, - } - } - #[doc = "Channel cannot be suspended by a higher-priority channel's service request"] - #[inline(always)] - pub fn is_cannot_suspend(&self) -> bool { - *self == Ecp::CannotSuspend - } - #[doc = "Channel can be temporarily suspended by a higher-priority channel's service request"] - #[inline(always)] - pub fn is_suspend(&self) -> bool { - *self == Ecp::Suspend - } -} -#[doc = "Field `ECP` writer - Enable Channel Preemption"] -pub type EcpW<'a, REG> = crate::BitWriter<'a, REG, Ecp>; -impl<'a, REG> EcpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel cannot be suspended by a higher-priority channel's service request"] - #[inline(always)] - pub fn cannot_suspend(self) -> &'a mut crate::W { - self.variant(Ecp::CannotSuspend) - } - #[doc = "Channel can be temporarily suspended by a higher-priority channel's service request"] - #[inline(always)] - pub fn suspend(self) -> &'a mut crate::W { - self.variant(Ecp::Suspend) - } -} -impl R { - #[doc = "Bits 0:2 - Arbitration Priority Level"] - #[inline(always)] - pub fn apl(&self) -> AplR { - AplR::new((self.bits & 7) as u8) - } - #[doc = "Bit 30 - Disable Preempt Ability"] - #[inline(always)] - pub fn dpa(&self) -> DpaR { - DpaR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Enable Channel Preemption"] - #[inline(always)] - pub fn ecp(&self) -> EcpR { - EcpR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Arbitration Priority Level"] - #[inline(always)] - pub fn apl(&mut self) -> AplW { - AplW::new(self, 0) - } - #[doc = "Bit 30 - Disable Preempt Ability"] - #[inline(always)] - pub fn dpa(&mut self) -> DpaW { - DpaW::new(self, 30) - } - #[doc = "Bit 31 - Enable Channel Preemption"] - #[inline(always)] - pub fn ecp(&mut self) -> EcpW { - EcpW::new(self, 31) - } -} -#[doc = "Channel Priority\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_pri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_pri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ChPriSpec; -impl crate::RegisterSpec for ChPriSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ch_pri::R`](R) reader structure"] -impl crate::Readable for ChPriSpec {} -#[doc = "`write(|w| ..)` method takes [`ch_pri::W`](W) writer structure"] -impl crate::Writable for ChPriSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CH_PRI to value 0"] -impl crate::Resettable for ChPriSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs deleted file mode 100644 index c248fb02d..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/ch_sbr.rs +++ /dev/null @@ -1,134 +0,0 @@ -#[doc = "Register `CH_SBR` reader"] -pub type R = crate::R; -#[doc = "Register `CH_SBR` writer"] -pub type W = crate::W; -#[doc = "Field `MID` reader - Master ID"] -pub type MidR = crate::FieldReader; -#[doc = "Privileged Access Level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pal { - #[doc = "0: User protection level for DMA transfers"] - UserProtection = 0, - #[doc = "1: Privileged protection level for DMA transfers"] - PrivilegedProtection = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PAL` reader - Privileged Access Level"] -pub type PalR = crate::BitReader; -impl PalR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pal { - match self.bits { - false => Pal::UserProtection, - true => Pal::PrivilegedProtection, - } - } - #[doc = "User protection level for DMA transfers"] - #[inline(always)] - pub fn is_user_protection(&self) -> bool { - *self == Pal::UserProtection - } - #[doc = "Privileged protection level for DMA transfers"] - #[inline(always)] - pub fn is_privileged_protection(&self) -> bool { - *self == Pal::PrivilegedProtection - } -} -#[doc = "Enable Master ID Replication\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Emi { - #[doc = "0: Master ID replication is disabled"] - Disable = 0, - #[doc = "1: Master ID replication is enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Emi) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EMI` reader - Enable Master ID Replication"] -pub type EmiR = crate::BitReader; -impl EmiR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Emi { - match self.bits { - false => Emi::Disable, - true => Emi::Enable, - } - } - #[doc = "Master ID replication is disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Emi::Disable - } - #[doc = "Master ID replication is enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Emi::Enable - } -} -#[doc = "Field `EMI` writer - Enable Master ID Replication"] -pub type EmiW<'a, REG> = crate::BitWriter<'a, REG, Emi>; -impl<'a, REG> EmiW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Master ID replication is disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Emi::Disable) - } - #[doc = "Master ID replication is enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Emi::Enable) - } -} -impl R { - #[doc = "Bits 0:3 - Master ID"] - #[inline(always)] - pub fn mid(&self) -> MidR { - MidR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 15 - Privileged Access Level"] - #[inline(always)] - pub fn pal(&self) -> PalR { - PalR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Enable Master ID Replication"] - #[inline(always)] - pub fn emi(&self) -> EmiR { - EmiR::new(((self.bits >> 16) & 1) != 0) - } -} -impl W { - #[doc = "Bit 16 - Enable Master ID Replication"] - #[inline(always)] - pub fn emi(&mut self) -> EmiW { - EmiW::new(self, 16) - } -} -#[doc = "Channel System Bus\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_sbr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_sbr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ChSbrSpec; -impl crate::RegisterSpec for ChSbrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ch_sbr::R`](R) reader structure"] -impl crate::Readable for ChSbrSpec {} -#[doc = "`write(|w| ..)` method takes [`ch_sbr::W`](W) writer structure"] -impl crate::Writable for ChSbrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CH_SBR to value 0x05"] -impl crate::Resettable for ChSbrSpec { - const RESET_VALUE: u32 = 0x05; -} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs deleted file mode 100644 index 97d857cfc..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_biter_elinkno.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `TCD_BITER_ELINKNO` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_BITER_ELINKNO` writer"] -pub type W = crate::W; -#[doc = "Field `BITER` reader - Starting Major Iteration Count"] -pub type BiterR = crate::FieldReader; -#[doc = "Field `BITER` writer - Starting Major Iteration Count"] -pub type BiterW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; -#[doc = "Enables Link\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Elink { - #[doc = "0: Channel-to-channel linking disabled"] - Disable = 0, - #[doc = "1: Channel-to-channel linking enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Elink) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ELINK` reader - Enables Link"] -pub type ElinkR = crate::BitReader; -impl ElinkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Elink { - match self.bits { - false => Elink::Disable, - true => Elink::Enable, - } - } - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Elink::Disable - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Elink::Enable - } -} -#[doc = "Field `ELINK` writer - Enables Link"] -pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; -impl<'a, REG> ElinkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Elink::Disable) - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Elink::Enable) - } -} -impl R { - #[doc = "Bits 0:14 - Starting Major Iteration Count"] - #[inline(always)] - pub fn biter(&self) -> BiterR { - BiterR::new(self.bits & 0x7fff) - } - #[doc = "Bit 15 - Enables Link"] - #[inline(always)] - pub fn elink(&self) -> ElinkR { - ElinkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:14 - Starting Major Iteration Count"] - #[inline(always)] - pub fn biter(&mut self) -> BiterW { - BiterW::new(self, 0) - } - #[doc = "Bit 15 - Enables Link"] - #[inline(always)] - pub fn elink(&mut self) -> ElinkW { - ElinkW::new(self, 15) - } -} -#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_biter_elinkno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_biter_elinkno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElinknoTcdBiterElinknoSpec; -impl crate::RegisterSpec for ElinknoTcdBiterElinknoSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`elinkno_tcd_biter_elinkno::R`](R) reader structure"] -impl crate::Readable for ElinknoTcdBiterElinknoSpec {} -#[doc = "`write(|w| ..)` method takes [`elinkno_tcd_biter_elinkno::W`](W) writer structure"] -impl crate::Writable for ElinknoTcdBiterElinknoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_BITER_ELINKNO to value 0"] -impl crate::Resettable for ElinknoTcdBiterElinknoSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs deleted file mode 100644 index 701f9541b..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkno_tcd_citer_elinkno.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `TCD_CITER_ELINKNO` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_CITER_ELINKNO` writer"] -pub type W = crate::W; -#[doc = "Field `CITER` reader - Current Major Iteration Count"] -pub type CiterR = crate::FieldReader; -#[doc = "Field `CITER` writer - Current Major Iteration Count"] -pub type CiterW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; -#[doc = "Enable Link\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Elink { - #[doc = "0: Channel-to-channel linking disabled"] - Disable = 0, - #[doc = "1: Channel-to-channel linking enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Elink) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ELINK` reader - Enable Link"] -pub type ElinkR = crate::BitReader; -impl ElinkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Elink { - match self.bits { - false => Elink::Disable, - true => Elink::Enable, - } - } - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Elink::Disable - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Elink::Enable - } -} -#[doc = "Field `ELINK` writer - Enable Link"] -pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; -impl<'a, REG> ElinkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Elink::Disable) - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Elink::Enable) - } -} -impl R { - #[doc = "Bits 0:14 - Current Major Iteration Count"] - #[inline(always)] - pub fn citer(&self) -> CiterR { - CiterR::new(self.bits & 0x7fff) - } - #[doc = "Bit 15 - Enable Link"] - #[inline(always)] - pub fn elink(&self) -> ElinkR { - ElinkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:14 - Current Major Iteration Count"] - #[inline(always)] - pub fn citer(&mut self) -> CiterW { - CiterW::new(self, 0) - } - #[doc = "Bit 15 - Enable Link"] - #[inline(always)] - pub fn elink(&mut self) -> ElinkW { - ElinkW::new(self, 15) - } -} -#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkno_tcd_citer_elinkno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkno_tcd_citer_elinkno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElinknoTcdCiterElinknoSpec; -impl crate::RegisterSpec for ElinknoTcdCiterElinknoSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`elinkno_tcd_citer_elinkno::R`](R) reader structure"] -impl crate::Readable for ElinknoTcdCiterElinknoSpec {} -#[doc = "`write(|w| ..)` method takes [`elinkno_tcd_citer_elinkno::W`](W) writer structure"] -impl crate::Writable for ElinknoTcdCiterElinknoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_CITER_ELINKNO to value 0"] -impl crate::Resettable for ElinknoTcdCiterElinknoSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs deleted file mode 100644 index 145ee5789..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_biter_elinkyes.rs +++ /dev/null @@ -1,112 +0,0 @@ -#[doc = "Register `TCD_BITER_ELINKYES` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_BITER_ELINKYES` writer"] -pub type W = crate::W; -#[doc = "Field `BITER` reader - Starting Major Iteration Count"] -pub type BiterR = crate::FieldReader; -#[doc = "Field `BITER` writer - Starting Major Iteration Count"] -pub type BiterW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `LINKCH` reader - Link Channel Number"] -pub type LinkchR = crate::FieldReader; -#[doc = "Field `LINKCH` writer - Link Channel Number"] -pub type LinkchW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Enable Link\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Elink { - #[doc = "0: Channel-to-channel linking disabled"] - Disable = 0, - #[doc = "1: Channel-to-channel linking enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Elink) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ELINK` reader - Enable Link"] -pub type ElinkR = crate::BitReader; -impl ElinkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Elink { - match self.bits { - false => Elink::Disable, - true => Elink::Enable, - } - } - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Elink::Disable - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Elink::Enable - } -} -#[doc = "Field `ELINK` writer - Enable Link"] -pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; -impl<'a, REG> ElinkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Elink::Disable) - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Elink::Enable) - } -} -impl R { - #[doc = "Bits 0:8 - Starting Major Iteration Count"] - #[inline(always)] - pub fn biter(&self) -> BiterR { - BiterR::new(self.bits & 0x01ff) - } - #[doc = "Bits 9:11 - Link Channel Number"] - #[inline(always)] - pub fn linkch(&self) -> LinkchR { - LinkchR::new(((self.bits >> 9) & 7) as u8) - } - #[doc = "Bit 15 - Enable Link"] - #[inline(always)] - pub fn elink(&self) -> ElinkR { - ElinkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:8 - Starting Major Iteration Count"] - #[inline(always)] - pub fn biter(&mut self) -> BiterW { - BiterW::new(self, 0) - } - #[doc = "Bits 9:11 - Link Channel Number"] - #[inline(always)] - pub fn linkch(&mut self) -> LinkchW { - LinkchW::new(self, 9) - } - #[doc = "Bit 15 - Enable Link"] - #[inline(always)] - pub fn elink(&mut self) -> ElinkW { - ElinkW::new(self, 15) - } -} -#[doc = "TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_biter_elinkyes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_biter_elinkyes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElinkyesTcdBiterElinkyesSpec; -impl crate::RegisterSpec for ElinkyesTcdBiterElinkyesSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`elinkyes_tcd_biter_elinkyes::R`](R) reader structure"] -impl crate::Readable for ElinkyesTcdBiterElinkyesSpec {} -#[doc = "`write(|w| ..)` method takes [`elinkyes_tcd_biter_elinkyes::W`](W) writer structure"] -impl crate::Writable for ElinkyesTcdBiterElinkyesSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_BITER_ELINKYES to value 0"] -impl crate::Resettable for ElinkyesTcdBiterElinkyesSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs deleted file mode 100644 index 6c878f783..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/elinkyes_tcd_citer_elinkyes.rs +++ /dev/null @@ -1,112 +0,0 @@ -#[doc = "Register `TCD_CITER_ELINKYES` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_CITER_ELINKYES` writer"] -pub type W = crate::W; -#[doc = "Field `CITER` reader - Current Major Iteration Count"] -pub type CiterR = crate::FieldReader; -#[doc = "Field `CITER` writer - Current Major Iteration Count"] -pub type CiterW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `LINKCH` reader - Minor Loop Link Channel Number"] -pub type LinkchR = crate::FieldReader; -#[doc = "Field `LINKCH` writer - Minor Loop Link Channel Number"] -pub type LinkchW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Enable Link\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Elink { - #[doc = "0: Channel-to-channel linking disabled"] - Disable = 0, - #[doc = "1: Channel-to-channel linking enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Elink) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ELINK` reader - Enable Link"] -pub type ElinkR = crate::BitReader; -impl ElinkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Elink { - match self.bits { - false => Elink::Disable, - true => Elink::Enable, - } - } - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Elink::Disable - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Elink::Enable - } -} -#[doc = "Field `ELINK` writer - Enable Link"] -pub type ElinkW<'a, REG> = crate::BitWriter<'a, REG, Elink>; -impl<'a, REG> ElinkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Elink::Disable) - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Elink::Enable) - } -} -impl R { - #[doc = "Bits 0:8 - Current Major Iteration Count"] - #[inline(always)] - pub fn citer(&self) -> CiterR { - CiterR::new(self.bits & 0x01ff) - } - #[doc = "Bits 9:11 - Minor Loop Link Channel Number"] - #[inline(always)] - pub fn linkch(&self) -> LinkchR { - LinkchR::new(((self.bits >> 9) & 7) as u8) - } - #[doc = "Bit 15 - Enable Link"] - #[inline(always)] - pub fn elink(&self) -> ElinkR { - ElinkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:8 - Current Major Iteration Count"] - #[inline(always)] - pub fn citer(&mut self) -> CiterW { - CiterW::new(self, 0) - } - #[doc = "Bits 9:11 - Minor Loop Link Channel Number"] - #[inline(always)] - pub fn linkch(&mut self) -> LinkchW { - LinkchW::new(self, 9) - } - #[doc = "Bit 15 - Enable Link"] - #[inline(always)] - pub fn elink(&mut self) -> ElinkW { - ElinkW::new(self, 15) - } -} -#[doc = "TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)\n\nYou can [`read`](crate::Reg::read) this register and get [`elinkyes_tcd_citer_elinkyes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`elinkyes_tcd_citer_elinkyes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElinkyesTcdCiterElinkyesSpec; -impl crate::RegisterSpec for ElinkyesTcdCiterElinkyesSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`elinkyes_tcd_citer_elinkyes::R`](R) reader structure"] -impl crate::Readable for ElinkyesTcdCiterElinkyesSpec {} -#[doc = "`write(|w| ..)` method takes [`elinkyes_tcd_citer_elinkyes::W`](W) writer structure"] -impl crate::Writable for ElinkyesTcdCiterElinkyesSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_CITER_ELINKYES to value 0"] -impl crate::Resettable for ElinkyesTcdCiterElinkyesSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs deleted file mode 100644 index 0d9dbadd0..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/mloffno_tcd_nbytes_mloffno.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `TCD_NBYTES_MLOFFNO` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_NBYTES_MLOFFNO` writer"] -pub type W = crate::W; -#[doc = "Field `NBYTES` reader - Number of Bytes To Transfer Per Service Request"] -pub type NbytesR = crate::FieldReader; -#[doc = "Field `NBYTES` writer - Number of Bytes To Transfer Per Service Request"] -pub type NbytesW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; -#[doc = "Destination Minor Loop Offset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmloe { - #[doc = "0: Minor loop offset not applied to DADDR"] - OffsetNotApplied = 0, - #[doc = "1: Minor loop offset applied to DADDR"] - OffsetApplied = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmloe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMLOE` reader - Destination Minor Loop Offset Enable"] -pub type DmloeR = crate::BitReader; -impl DmloeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmloe { - match self.bits { - false => Dmloe::OffsetNotApplied, - true => Dmloe::OffsetApplied, - } - } - #[doc = "Minor loop offset not applied to DADDR"] - #[inline(always)] - pub fn is_offset_not_applied(&self) -> bool { - *self == Dmloe::OffsetNotApplied - } - #[doc = "Minor loop offset applied to DADDR"] - #[inline(always)] - pub fn is_offset_applied(&self) -> bool { - *self == Dmloe::OffsetApplied - } -} -#[doc = "Field `DMLOE` writer - Destination Minor Loop Offset Enable"] -pub type DmloeW<'a, REG> = crate::BitWriter<'a, REG, Dmloe>; -impl<'a, REG> DmloeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Minor loop offset not applied to DADDR"] - #[inline(always)] - pub fn offset_not_applied(self) -> &'a mut crate::W { - self.variant(Dmloe::OffsetNotApplied) - } - #[doc = "Minor loop offset applied to DADDR"] - #[inline(always)] - pub fn offset_applied(self) -> &'a mut crate::W { - self.variant(Dmloe::OffsetApplied) - } -} -#[doc = "Source Minor Loop Offset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Smloe { - #[doc = "0: Minor loop offset not applied to SADDR"] - OffsetNotApplied = 0, - #[doc = "1: Minor loop offset applied to SADDR"] - OffsetApplied = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Smloe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SMLOE` reader - Source Minor Loop Offset Enable"] -pub type SmloeR = crate::BitReader; -impl SmloeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Smloe { - match self.bits { - false => Smloe::OffsetNotApplied, - true => Smloe::OffsetApplied, - } - } - #[doc = "Minor loop offset not applied to SADDR"] - #[inline(always)] - pub fn is_offset_not_applied(&self) -> bool { - *self == Smloe::OffsetNotApplied - } - #[doc = "Minor loop offset applied to SADDR"] - #[inline(always)] - pub fn is_offset_applied(&self) -> bool { - *self == Smloe::OffsetApplied - } -} -#[doc = "Field `SMLOE` writer - Source Minor Loop Offset Enable"] -pub type SmloeW<'a, REG> = crate::BitWriter<'a, REG, Smloe>; -impl<'a, REG> SmloeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Minor loop offset not applied to SADDR"] - #[inline(always)] - pub fn offset_not_applied(self) -> &'a mut crate::W { - self.variant(Smloe::OffsetNotApplied) - } - #[doc = "Minor loop offset applied to SADDR"] - #[inline(always)] - pub fn offset_applied(self) -> &'a mut crate::W { - self.variant(Smloe::OffsetApplied) - } -} -impl R { - #[doc = "Bits 0:29 - Number of Bytes To Transfer Per Service Request"] - #[inline(always)] - pub fn nbytes(&self) -> NbytesR { - NbytesR::new(self.bits & 0x3fff_ffff) - } - #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] - #[inline(always)] - pub fn dmloe(&self) -> DmloeR { - DmloeR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Source Minor Loop Offset Enable"] - #[inline(always)] - pub fn smloe(&self) -> SmloeR { - SmloeR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:29 - Number of Bytes To Transfer Per Service Request"] - #[inline(always)] - pub fn nbytes(&mut self) -> NbytesW { - NbytesW::new(self, 0) - } - #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] - #[inline(always)] - pub fn dmloe(&mut self) -> DmloeW { - DmloeW::new(self, 30) - } - #[doc = "Bit 31 - Source Minor Loop Offset Enable"] - #[inline(always)] - pub fn smloe(&mut self) -> SmloeW { - SmloeW::new(self, 31) - } -} -#[doc = "TCD Transfer Size Without Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffno_tcd_nbytes_mloffno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffno_tcd_nbytes_mloffno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MloffnoTcdNbytesMloffnoSpec; -impl crate::RegisterSpec for MloffnoTcdNbytesMloffnoSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mloffno_tcd_nbytes_mloffno::R`](R) reader structure"] -impl crate::Readable for MloffnoTcdNbytesMloffnoSpec {} -#[doc = "`write(|w| ..)` method takes [`mloffno_tcd_nbytes_mloffno::W`](W) writer structure"] -impl crate::Writable for MloffnoTcdNbytesMloffnoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_NBYTES_MLOFFNO to value 0"] -impl crate::Resettable for MloffnoTcdNbytesMloffnoSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/mloffyes_tcd_nbytes_mloffyes.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/mloffyes_tcd_nbytes_mloffyes.rs deleted file mode 100644 index 971b10f7f..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/mloffyes_tcd_nbytes_mloffyes.rs +++ /dev/null @@ -1,175 +0,0 @@ -#[doc = "Register `TCD_NBYTES_MLOFFYES` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_NBYTES_MLOFFYES` writer"] -pub type W = crate::W; -#[doc = "Field `NBYTES` reader - Number of Bytes To Transfer Per Service Request"] -pub type NbytesR = crate::FieldReader; -#[doc = "Field `NBYTES` writer - Number of Bytes To Transfer Per Service Request"] -pub type NbytesW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `MLOFF` reader - Minor Loop Offset"] -pub type MloffR = crate::FieldReader; -#[doc = "Field `MLOFF` writer - Minor Loop Offset"] -pub type MloffW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; -#[doc = "Destination Minor Loop Offset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmloe { - #[doc = "0: Minor loop offset not applied to DADDR"] - OffsetNotApplied = 0, - #[doc = "1: Minor loop offset applied to DADDR"] - OffsetApplied = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmloe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMLOE` reader - Destination Minor Loop Offset Enable"] -pub type DmloeR = crate::BitReader; -impl DmloeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmloe { - match self.bits { - false => Dmloe::OffsetNotApplied, - true => Dmloe::OffsetApplied, - } - } - #[doc = "Minor loop offset not applied to DADDR"] - #[inline(always)] - pub fn is_offset_not_applied(&self) -> bool { - *self == Dmloe::OffsetNotApplied - } - #[doc = "Minor loop offset applied to DADDR"] - #[inline(always)] - pub fn is_offset_applied(&self) -> bool { - *self == Dmloe::OffsetApplied - } -} -#[doc = "Field `DMLOE` writer - Destination Minor Loop Offset Enable"] -pub type DmloeW<'a, REG> = crate::BitWriter<'a, REG, Dmloe>; -impl<'a, REG> DmloeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Minor loop offset not applied to DADDR"] - #[inline(always)] - pub fn offset_not_applied(self) -> &'a mut crate::W { - self.variant(Dmloe::OffsetNotApplied) - } - #[doc = "Minor loop offset applied to DADDR"] - #[inline(always)] - pub fn offset_applied(self) -> &'a mut crate::W { - self.variant(Dmloe::OffsetApplied) - } -} -#[doc = "Source Minor Loop Offset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Smloe { - #[doc = "0: Minor loop offset not applied to SADDR"] - OffsetNotApplied = 0, - #[doc = "1: Minor loop offset applied to SADDR"] - OffsetApplied = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Smloe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SMLOE` reader - Source Minor Loop Offset Enable"] -pub type SmloeR = crate::BitReader; -impl SmloeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Smloe { - match self.bits { - false => Smloe::OffsetNotApplied, - true => Smloe::OffsetApplied, - } - } - #[doc = "Minor loop offset not applied to SADDR"] - #[inline(always)] - pub fn is_offset_not_applied(&self) -> bool { - *self == Smloe::OffsetNotApplied - } - #[doc = "Minor loop offset applied to SADDR"] - #[inline(always)] - pub fn is_offset_applied(&self) -> bool { - *self == Smloe::OffsetApplied - } -} -#[doc = "Field `SMLOE` writer - Source Minor Loop Offset Enable"] -pub type SmloeW<'a, REG> = crate::BitWriter<'a, REG, Smloe>; -impl<'a, REG> SmloeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Minor loop offset not applied to SADDR"] - #[inline(always)] - pub fn offset_not_applied(self) -> &'a mut crate::W { - self.variant(Smloe::OffsetNotApplied) - } - #[doc = "Minor loop offset applied to SADDR"] - #[inline(always)] - pub fn offset_applied(self) -> &'a mut crate::W { - self.variant(Smloe::OffsetApplied) - } -} -impl R { - #[doc = "Bits 0:9 - Number of Bytes To Transfer Per Service Request"] - #[inline(always)] - pub fn nbytes(&self) -> NbytesR { - NbytesR::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 10:29 - Minor Loop Offset"] - #[inline(always)] - pub fn mloff(&self) -> MloffR { - MloffR::new((self.bits >> 10) & 0x000f_ffff) - } - #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] - #[inline(always)] - pub fn dmloe(&self) -> DmloeR { - DmloeR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Source Minor Loop Offset Enable"] - #[inline(always)] - pub fn smloe(&self) -> SmloeR { - SmloeR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:9 - Number of Bytes To Transfer Per Service Request"] - #[inline(always)] - pub fn nbytes(&mut self) -> NbytesW { - NbytesW::new(self, 0) - } - #[doc = "Bits 10:29 - Minor Loop Offset"] - #[inline(always)] - pub fn mloff(&mut self) -> MloffW { - MloffW::new(self, 10) - } - #[doc = "Bit 30 - Destination Minor Loop Offset Enable"] - #[inline(always)] - pub fn dmloe(&mut self) -> DmloeW { - DmloeW::new(self, 30) - } - #[doc = "Bit 31 - Source Minor Loop Offset Enable"] - #[inline(always)] - pub fn smloe(&mut self) -> SmloeW { - SmloeW::new(self, 31) - } -} -#[doc = "TCD Transfer Size with Minor Loop Offsets\n\nYou can [`read`](crate::Reg::read) this register and get [`mloffyes_tcd_nbytes_mloffyes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mloffyes_tcd_nbytes_mloffyes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MloffyesTcdNbytesMloffyesSpec; -impl crate::RegisterSpec for MloffyesTcdNbytesMloffyesSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mloffyes_tcd_nbytes_mloffyes::R`](R) reader structure"] -impl crate::Readable for MloffyesTcdNbytesMloffyesSpec {} -#[doc = "`write(|w| ..)` method takes [`mloffyes_tcd_nbytes_mloffyes::W`](W) writer structure"] -impl crate::Writable for MloffyesTcdNbytesMloffyesSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_NBYTES_MLOFFYES to value 0"] -impl crate::Resettable for MloffyesTcdNbytesMloffyesSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs deleted file mode 100644 index 5a7921095..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_attr.rs +++ /dev/null @@ -1,241 +0,0 @@ -#[doc = "Register `TCD_ATTR` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_ATTR` writer"] -pub type W = crate::W; -#[doc = "Field `DSIZE` reader - Destination Data Transfer Size"] -pub type DsizeR = crate::FieldReader; -#[doc = "Field `DSIZE` writer - Destination Data Transfer Size"] -pub type DsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `DMOD` reader - Destination Address Modulo"] -pub type DmodR = crate::FieldReader; -#[doc = "Field `DMOD` writer - Destination Address Modulo"] -pub type DmodW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Source Data Transfer Size\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ssize { - #[doc = "0: 8-bit"] - EightBit = 0, - #[doc = "1: 16-bit"] - SixteenBit = 1, - #[doc = "2: 32-bit"] - ThirtytwoBit = 2, - #[doc = "3: 64-bit"] - SixtyfourBit = 3, - #[doc = "4: 16-byte"] - SixteenByte = 4, - #[doc = "5: 32-byte"] - ThirtytwoByte = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ssize) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ssize { - type Ux = u8; -} -impl crate::IsEnum for Ssize {} -#[doc = "Field `SSIZE` reader - Source Data Transfer Size"] -pub type SsizeR = crate::FieldReader; -impl SsizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ssize::EightBit), - 1 => Some(Ssize::SixteenBit), - 2 => Some(Ssize::ThirtytwoBit), - 3 => Some(Ssize::SixtyfourBit), - 4 => Some(Ssize::SixteenByte), - 5 => Some(Ssize::ThirtytwoByte), - _ => None, - } - } - #[doc = "8-bit"] - #[inline(always)] - pub fn is_eight_bit(&self) -> bool { - *self == Ssize::EightBit - } - #[doc = "16-bit"] - #[inline(always)] - pub fn is_sixteen_bit(&self) -> bool { - *self == Ssize::SixteenBit - } - #[doc = "32-bit"] - #[inline(always)] - pub fn is_thirtytwo_bit(&self) -> bool { - *self == Ssize::ThirtytwoBit - } - #[doc = "64-bit"] - #[inline(always)] - pub fn is_sixtyfour_bit(&self) -> bool { - *self == Ssize::SixtyfourBit - } - #[doc = "16-byte"] - #[inline(always)] - pub fn is_sixteen_byte(&self) -> bool { - *self == Ssize::SixteenByte - } - #[doc = "32-byte"] - #[inline(always)] - pub fn is_thirtytwo_byte(&self) -> bool { - *self == Ssize::ThirtytwoByte - } -} -#[doc = "Field `SSIZE` writer - Source Data Transfer Size"] -pub type SsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Ssize>; -impl<'a, REG> SsizeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "8-bit"] - #[inline(always)] - pub fn eight_bit(self) -> &'a mut crate::W { - self.variant(Ssize::EightBit) - } - #[doc = "16-bit"] - #[inline(always)] - pub fn sixteen_bit(self) -> &'a mut crate::W { - self.variant(Ssize::SixteenBit) - } - #[doc = "32-bit"] - #[inline(always)] - pub fn thirtytwo_bit(self) -> &'a mut crate::W { - self.variant(Ssize::ThirtytwoBit) - } - #[doc = "64-bit"] - #[inline(always)] - pub fn sixtyfour_bit(self) -> &'a mut crate::W { - self.variant(Ssize::SixtyfourBit) - } - #[doc = "16-byte"] - #[inline(always)] - pub fn sixteen_byte(self) -> &'a mut crate::W { - self.variant(Ssize::SixteenByte) - } - #[doc = "32-byte"] - #[inline(always)] - pub fn thirtytwo_byte(self) -> &'a mut crate::W { - self.variant(Ssize::ThirtytwoByte) - } -} -#[doc = "Source Address Modulo\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Smod { - #[doc = "0: Source address modulo feature disabled"] - Disable = 0, - #[doc = "1: Source address modulo feature enabled for any non-zero value \\[1-31\\]"] - Enable = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Smod) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Smod { - type Ux = u8; -} -impl crate::IsEnum for Smod {} -#[doc = "Field `SMOD` reader - Source Address Modulo"] -pub type SmodR = crate::FieldReader; -impl SmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Smod::Disable), - 1 => Some(Smod::Enable), - _ => None, - } - } - #[doc = "Source address modulo feature disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Smod::Disable - } - #[doc = "Source address modulo feature enabled for any non-zero value \\[1-31\\]"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Smod::Enable - } -} -#[doc = "Field `SMOD` writer - Source Address Modulo"] -pub type SmodW<'a, REG> = crate::FieldWriter<'a, REG, 5, Smod>; -impl<'a, REG> SmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Source address modulo feature disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Smod::Disable) - } - #[doc = "Source address modulo feature enabled for any non-zero value \\[1-31\\]"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Smod::Enable) - } -} -impl R { - #[doc = "Bits 0:2 - Destination Data Transfer Size"] - #[inline(always)] - pub fn dsize(&self) -> DsizeR { - DsizeR::new((self.bits & 7) as u8) - } - #[doc = "Bits 3:7 - Destination Address Modulo"] - #[inline(always)] - pub fn dmod(&self) -> DmodR { - DmodR::new(((self.bits >> 3) & 0x1f) as u8) - } - #[doc = "Bits 8:10 - Source Data Transfer Size"] - #[inline(always)] - pub fn ssize(&self) -> SsizeR { - SsizeR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 11:15 - Source Address Modulo"] - #[inline(always)] - pub fn smod(&self) -> SmodR { - SmodR::new(((self.bits >> 11) & 0x1f) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Destination Data Transfer Size"] - #[inline(always)] - pub fn dsize(&mut self) -> DsizeW { - DsizeW::new(self, 0) - } - #[doc = "Bits 3:7 - Destination Address Modulo"] - #[inline(always)] - pub fn dmod(&mut self) -> DmodW { - DmodW::new(self, 3) - } - #[doc = "Bits 8:10 - Source Data Transfer Size"] - #[inline(always)] - pub fn ssize(&mut self) -> SsizeW { - SsizeW::new(self, 8) - } - #[doc = "Bits 11:15 - Source Address Modulo"] - #[inline(always)] - pub fn smod(&mut self) -> SmodW { - SmodW::new(self, 11) - } -} -#[doc = "TCD Transfer Attributes\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdAttrSpec; -impl crate::RegisterSpec for TcdAttrSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`tcd_attr::R`](R) reader structure"] -impl crate::Readable for TcdAttrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_attr::W`](W) writer structure"] -impl crate::Writable for TcdAttrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_ATTR to value 0"] -impl crate::Resettable for TcdAttrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs deleted file mode 100644 index e08414837..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_csr.rs +++ /dev/null @@ -1,622 +0,0 @@ -#[doc = "Register `TCD_CSR` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_CSR` writer"] -pub type W = crate::W; -#[doc = "Channel Start\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Start { - #[doc = "0: Channel not explicitly started"] - ChannelNotStarted = 0, - #[doc = "1: Channel explicitly started via a software-initiated service request"] - ChannelStarted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Start) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `START` reader - Channel Start"] -pub type StartR = crate::BitReader; -impl StartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Start { - match self.bits { - false => Start::ChannelNotStarted, - true => Start::ChannelStarted, - } - } - #[doc = "Channel not explicitly started"] - #[inline(always)] - pub fn is_channel_not_started(&self) -> bool { - *self == Start::ChannelNotStarted - } - #[doc = "Channel explicitly started via a software-initiated service request"] - #[inline(always)] - pub fn is_channel_started(&self) -> bool { - *self == Start::ChannelStarted - } -} -#[doc = "Field `START` writer - Channel Start"] -pub type StartW<'a, REG> = crate::BitWriter<'a, REG, Start>; -impl<'a, REG> StartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel not explicitly started"] - #[inline(always)] - pub fn channel_not_started(self) -> &'a mut crate::W { - self.variant(Start::ChannelNotStarted) - } - #[doc = "Channel explicitly started via a software-initiated service request"] - #[inline(always)] - pub fn channel_started(self) -> &'a mut crate::W { - self.variant(Start::ChannelStarted) - } -} -#[doc = "Enable Interrupt If Major count complete\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Intmajor { - #[doc = "0: End-of-major loop interrupt disabled"] - Disable = 0, - #[doc = "1: End-of-major loop interrupt enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Intmajor) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTMAJOR` reader - Enable Interrupt If Major count complete"] -pub type IntmajorR = crate::BitReader; -impl IntmajorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Intmajor { - match self.bits { - false => Intmajor::Disable, - true => Intmajor::Enable, - } - } - #[doc = "End-of-major loop interrupt disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Intmajor::Disable - } - #[doc = "End-of-major loop interrupt enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Intmajor::Enable - } -} -#[doc = "Field `INTMAJOR` writer - Enable Interrupt If Major count complete"] -pub type IntmajorW<'a, REG> = crate::BitWriter<'a, REG, Intmajor>; -impl<'a, REG> IntmajorW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "End-of-major loop interrupt disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Intmajor::Disable) - } - #[doc = "End-of-major loop interrupt enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Intmajor::Enable) - } -} -#[doc = "Enable Interrupt If Major Counter Half-complete\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inthalf { - #[doc = "0: Halfway point interrupt disabled"] - Disable = 0, - #[doc = "1: Halfway point interrupt enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inthalf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTHALF` reader - Enable Interrupt If Major Counter Half-complete"] -pub type InthalfR = crate::BitReader; -impl InthalfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inthalf { - match self.bits { - false => Inthalf::Disable, - true => Inthalf::Enable, - } - } - #[doc = "Halfway point interrupt disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Inthalf::Disable - } - #[doc = "Halfway point interrupt enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Inthalf::Enable - } -} -#[doc = "Field `INTHALF` writer - Enable Interrupt If Major Counter Half-complete"] -pub type InthalfW<'a, REG> = crate::BitWriter<'a, REG, Inthalf>; -impl<'a, REG> InthalfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Halfway point interrupt disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Inthalf::Disable) - } - #[doc = "Halfway point interrupt enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Inthalf::Enable) - } -} -#[doc = "Disable Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dreq { - #[doc = "0: No operation"] - ChannelNotAffected = 0, - #[doc = "1: Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"] - ErqFieldClear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dreq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DREQ` reader - Disable Request"] -pub type DreqR = crate::BitReader; -impl DreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dreq { - match self.bits { - false => Dreq::ChannelNotAffected, - true => Dreq::ErqFieldClear, - } - } - #[doc = "No operation"] - #[inline(always)] - pub fn is_channel_not_affected(&self) -> bool { - *self == Dreq::ChannelNotAffected - } - #[doc = "Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"] - #[inline(always)] - pub fn is_erq_field_clear(&self) -> bool { - *self == Dreq::ErqFieldClear - } -} -#[doc = "Field `DREQ` writer - Disable Request"] -pub type DreqW<'a, REG> = crate::BitWriter<'a, REG, Dreq>; -impl<'a, REG> DreqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No operation"] - #[inline(always)] - pub fn channel_not_affected(self) -> &'a mut crate::W { - self.variant(Dreq::ChannelNotAffected) - } - #[doc = "Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests"] - #[inline(always)] - pub fn erq_field_clear(self) -> &'a mut crate::W { - self.variant(Dreq::ErqFieldClear) - } -} -#[doc = "Enable Scatter/Gather Processing\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Esg { - #[doc = "0: Current channel's TCD is normal format"] - NormalFormat = 0, - #[doc = "1: Current channel's TCD specifies scatter/gather format."] - ScatterGatherFormat = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Esg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ESG` reader - Enable Scatter/Gather Processing"] -pub type EsgR = crate::BitReader; -impl EsgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Esg { - match self.bits { - false => Esg::NormalFormat, - true => Esg::ScatterGatherFormat, - } - } - #[doc = "Current channel's TCD is normal format"] - #[inline(always)] - pub fn is_normal_format(&self) -> bool { - *self == Esg::NormalFormat - } - #[doc = "Current channel's TCD specifies scatter/gather format."] - #[inline(always)] - pub fn is_scatter_gather_format(&self) -> bool { - *self == Esg::ScatterGatherFormat - } -} -#[doc = "Field `ESG` writer - Enable Scatter/Gather Processing"] -pub type EsgW<'a, REG> = crate::BitWriter<'a, REG, Esg>; -impl<'a, REG> EsgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Current channel's TCD is normal format"] - #[inline(always)] - pub fn normal_format(self) -> &'a mut crate::W { - self.variant(Esg::NormalFormat) - } - #[doc = "Current channel's TCD specifies scatter/gather format."] - #[inline(always)] - pub fn scatter_gather_format(self) -> &'a mut crate::W { - self.variant(Esg::ScatterGatherFormat) - } -} -#[doc = "Enable Link When Major Loop Complete\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Majorelink { - #[doc = "0: Channel-to-channel linking disabled"] - Disable = 0, - #[doc = "1: Channel-to-channel linking enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Majorelink) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MAJORELINK` reader - Enable Link When Major Loop Complete"] -pub type MajorelinkR = crate::BitReader; -impl MajorelinkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Majorelink { - match self.bits { - false => Majorelink::Disable, - true => Majorelink::Enable, - } - } - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Majorelink::Disable - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Majorelink::Enable - } -} -#[doc = "Field `MAJORELINK` writer - Enable Link When Major Loop Complete"] -pub type MajorelinkW<'a, REG> = crate::BitWriter<'a, REG, Majorelink>; -impl<'a, REG> MajorelinkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Channel-to-channel linking disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Majorelink::Disable) - } - #[doc = "Channel-to-channel linking enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Majorelink::Enable) - } -} -#[doc = "Enable End-Of-Packet Processing\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Eeop { - #[doc = "0: End-of-packet operation disabled"] - Disable = 0, - #[doc = "1: End-of-packet hardware input signal enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Eeop) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EEOP` reader - Enable End-Of-Packet Processing"] -pub type EeopR = crate::BitReader; -impl EeopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Eeop { - match self.bits { - false => Eeop::Disable, - true => Eeop::Enable, - } - } - #[doc = "End-of-packet operation disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Eeop::Disable - } - #[doc = "End-of-packet hardware input signal enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Eeop::Enable - } -} -#[doc = "Field `EEOP` writer - Enable End-Of-Packet Processing"] -pub type EeopW<'a, REG> = crate::BitWriter<'a, REG, Eeop>; -impl<'a, REG> EeopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "End-of-packet operation disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Eeop::Disable) - } - #[doc = "End-of-packet hardware input signal enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Eeop::Enable) - } -} -#[doc = "Enable Store Destination Address\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Esda { - #[doc = "0: Ability to store destination address to system memory disabled"] - Disable = 0, - #[doc = "1: Ability to store destination address to system memory enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Esda) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ESDA` reader - Enable Store Destination Address"] -pub type EsdaR = crate::BitReader; -impl EsdaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Esda { - match self.bits { - false => Esda::Disable, - true => Esda::Enable, - } - } - #[doc = "Ability to store destination address to system memory disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Esda::Disable - } - #[doc = "Ability to store destination address to system memory enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Esda::Enable - } -} -#[doc = "Field `ESDA` writer - Enable Store Destination Address"] -pub type EsdaW<'a, REG> = crate::BitWriter<'a, REG, Esda>; -impl<'a, REG> EsdaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Ability to store destination address to system memory disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Esda::Disable) - } - #[doc = "Ability to store destination address to system memory enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Esda::Enable) - } -} -#[doc = "Field `MAJORLINKCH` reader - Major Loop Link Channel Number"] -pub type MajorlinkchR = crate::FieldReader; -#[doc = "Field `MAJORLINKCH` writer - Major Loop Link Channel Number"] -pub type MajorlinkchW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Bandwidth Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Bwc { - #[doc = "0: No eDMA engine stalls"] - NoStall = 0, - #[doc = "2: eDMA engine stalls for 4 cycles after each R/W"] - EngineStallsFour = 2, - #[doc = "3: eDMA engine stalls for 8 cycles after each R/W"] - EngineStallsEight = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Bwc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Bwc { - type Ux = u8; -} -impl crate::IsEnum for Bwc {} -#[doc = "Field `BWC` reader - Bandwidth Control"] -pub type BwcR = crate::FieldReader; -impl BwcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Bwc::NoStall), - 2 => Some(Bwc::EngineStallsFour), - 3 => Some(Bwc::EngineStallsEight), - _ => None, - } - } - #[doc = "No eDMA engine stalls"] - #[inline(always)] - pub fn is_no_stall(&self) -> bool { - *self == Bwc::NoStall - } - #[doc = "eDMA engine stalls for 4 cycles after each R/W"] - #[inline(always)] - pub fn is_engine_stalls_four(&self) -> bool { - *self == Bwc::EngineStallsFour - } - #[doc = "eDMA engine stalls for 8 cycles after each R/W"] - #[inline(always)] - pub fn is_engine_stalls_eight(&self) -> bool { - *self == Bwc::EngineStallsEight - } -} -#[doc = "Field `BWC` writer - Bandwidth Control"] -pub type BwcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bwc>; -impl<'a, REG> BwcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No eDMA engine stalls"] - #[inline(always)] - pub fn no_stall(self) -> &'a mut crate::W { - self.variant(Bwc::NoStall) - } - #[doc = "eDMA engine stalls for 4 cycles after each R/W"] - #[inline(always)] - pub fn engine_stalls_four(self) -> &'a mut crate::W { - self.variant(Bwc::EngineStallsFour) - } - #[doc = "eDMA engine stalls for 8 cycles after each R/W"] - #[inline(always)] - pub fn engine_stalls_eight(self) -> &'a mut crate::W { - self.variant(Bwc::EngineStallsEight) - } -} -impl R { - #[doc = "Bit 0 - Channel Start"] - #[inline(always)] - pub fn start(&self) -> StartR { - StartR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Enable Interrupt If Major count complete"] - #[inline(always)] - pub fn intmajor(&self) -> IntmajorR { - IntmajorR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Enable Interrupt If Major Counter Half-complete"] - #[inline(always)] - pub fn inthalf(&self) -> InthalfR { - InthalfR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Disable Request"] - #[inline(always)] - pub fn dreq(&self) -> DreqR { - DreqR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Enable Scatter/Gather Processing"] - #[inline(always)] - pub fn esg(&self) -> EsgR { - EsgR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Enable Link When Major Loop Complete"] - #[inline(always)] - pub fn majorelink(&self) -> MajorelinkR { - MajorelinkR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Enable End-Of-Packet Processing"] - #[inline(always)] - pub fn eeop(&self) -> EeopR { - EeopR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Enable Store Destination Address"] - #[inline(always)] - pub fn esda(&self) -> EsdaR { - EsdaR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Major Loop Link Channel Number"] - #[inline(always)] - pub fn majorlinkch(&self) -> MajorlinkchR { - MajorlinkchR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 14:15 - Bandwidth Control"] - #[inline(always)] - pub fn bwc(&self) -> BwcR { - BwcR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bit 0 - Channel Start"] - #[inline(always)] - pub fn start(&mut self) -> StartW { - StartW::new(self, 0) - } - #[doc = "Bit 1 - Enable Interrupt If Major count complete"] - #[inline(always)] - pub fn intmajor(&mut self) -> IntmajorW { - IntmajorW::new(self, 1) - } - #[doc = "Bit 2 - Enable Interrupt If Major Counter Half-complete"] - #[inline(always)] - pub fn inthalf(&mut self) -> InthalfW { - InthalfW::new(self, 2) - } - #[doc = "Bit 3 - Disable Request"] - #[inline(always)] - pub fn dreq(&mut self) -> DreqW { - DreqW::new(self, 3) - } - #[doc = "Bit 4 - Enable Scatter/Gather Processing"] - #[inline(always)] - pub fn esg(&mut self) -> EsgW { - EsgW::new(self, 4) - } - #[doc = "Bit 5 - Enable Link When Major Loop Complete"] - #[inline(always)] - pub fn majorelink(&mut self) -> MajorelinkW { - MajorelinkW::new(self, 5) - } - #[doc = "Bit 6 - Enable End-Of-Packet Processing"] - #[inline(always)] - pub fn eeop(&mut self) -> EeopW { - EeopW::new(self, 6) - } - #[doc = "Bit 7 - Enable Store Destination Address"] - #[inline(always)] - pub fn esda(&mut self) -> EsdaW { - EsdaW::new(self, 7) - } - #[doc = "Bits 8:10 - Major Loop Link Channel Number"] - #[inline(always)] - pub fn majorlinkch(&mut self) -> MajorlinkchW { - MajorlinkchW::new(self, 8) - } - #[doc = "Bits 14:15 - Bandwidth Control"] - #[inline(always)] - pub fn bwc(&mut self) -> BwcW { - BwcW::new(self, 14) - } -} -#[doc = "TCD Control and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdCsrSpec; -impl crate::RegisterSpec for TcdCsrSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`tcd_csr::R`](R) reader structure"] -impl crate::Readable for TcdCsrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_csr::W`](W) writer structure"] -impl crate::Writable for TcdCsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_CSR to value 0"] -impl crate::Resettable for TcdCsrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs deleted file mode 100644 index 49bd118ff..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_daddr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TCD_DADDR` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_DADDR` writer"] -pub type W = crate::W; -#[doc = "Field `DADDR` reader - Destination Address"] -pub type DaddrR = crate::FieldReader; -#[doc = "Field `DADDR` writer - Destination Address"] -pub type DaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Destination Address"] - #[inline(always)] - pub fn daddr(&self) -> DaddrR { - DaddrR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Destination Address"] - #[inline(always)] - pub fn daddr(&mut self) -> DaddrW { - DaddrW::new(self, 0) - } -} -#[doc = "TCD Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_daddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_daddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdDaddrSpec; -impl crate::RegisterSpec for TcdDaddrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcd_daddr::R`](R) reader structure"] -impl crate::Readable for TcdDaddrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_daddr::W`](W) writer structure"] -impl crate::Writable for TcdDaddrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_DADDR to value 0"] -impl crate::Resettable for TcdDaddrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs deleted file mode 100644 index f7fd4fac8..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_dlast_sga.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TCD_DLAST_SGA` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_DLAST_SGA` writer"] -pub type W = crate::W; -#[doc = "Field `DLAST_SGA` reader - Last Destination Address Adjustment / Scatter Gather Address"] -pub type DlastSgaR = crate::FieldReader; -#[doc = "Field `DLAST_SGA` writer - Last Destination Address Adjustment / Scatter Gather Address"] -pub type DlastSgaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Last Destination Address Adjustment / Scatter Gather Address"] - #[inline(always)] - pub fn dlast_sga(&self) -> DlastSgaR { - DlastSgaR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Last Destination Address Adjustment / Scatter Gather Address"] - #[inline(always)] - pub fn dlast_sga(&mut self) -> DlastSgaW { - DlastSgaW::new(self, 0) - } -} -#[doc = "TCD Last Destination Address Adjustment / Scatter Gather Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_dlast_sga::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_dlast_sga::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdDlastSgaSpec; -impl crate::RegisterSpec for TcdDlastSgaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcd_dlast_sga::R`](R) reader structure"] -impl crate::Readable for TcdDlastSgaSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_dlast_sga::W`](W) writer structure"] -impl crate::Writable for TcdDlastSgaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_DLAST_SGA to value 0"] -impl crate::Resettable for TcdDlastSgaSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs deleted file mode 100644 index a7206017c..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_doff.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TCD_DOFF` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_DOFF` writer"] -pub type W = crate::W; -#[doc = "Field `DOFF` reader - Destination Address Signed Offset"] -pub type DoffR = crate::FieldReader; -#[doc = "Field `DOFF` writer - Destination Address Signed Offset"] -pub type DoffW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Destination Address Signed Offset"] - #[inline(always)] - pub fn doff(&self) -> DoffR { - DoffR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Destination Address Signed Offset"] - #[inline(always)] - pub fn doff(&mut self) -> DoffW { - DoffW::new(self, 0) - } -} -#[doc = "TCD Signed Destination Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_doff::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_doff::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdDoffSpec; -impl crate::RegisterSpec for TcdDoffSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`tcd_doff::R`](R) reader structure"] -impl crate::Readable for TcdDoffSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_doff::W`](W) writer structure"] -impl crate::Writable for TcdDoffSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_DOFF to value 0"] -impl crate::Resettable for TcdDoffSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs deleted file mode 100644 index 855a38687..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_saddr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TCD_SADDR` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_SADDR` writer"] -pub type W = crate::W; -#[doc = "Field `SADDR` reader - Source Address"] -pub type SaddrR = crate::FieldReader; -#[doc = "Field `SADDR` writer - Source Address"] -pub type SaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Source Address"] - #[inline(always)] - pub fn saddr(&self) -> SaddrR { - SaddrR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Source Address"] - #[inline(always)] - pub fn saddr(&mut self) -> SaddrW { - SaddrW::new(self, 0) - } -} -#[doc = "TCD Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_saddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_saddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdSaddrSpec; -impl crate::RegisterSpec for TcdSaddrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcd_saddr::R`](R) reader structure"] -impl crate::Readable for TcdSaddrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_saddr::W`](W) writer structure"] -impl crate::Writable for TcdSaddrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_SADDR to value 0"] -impl crate::Resettable for TcdSaddrSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs deleted file mode 100644 index 7d1b33587..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_slast_sda.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TCD_SLAST_SDA` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_SLAST_SDA` writer"] -pub type W = crate::W; -#[doc = "Field `SLAST_SDA` reader - Last Source Address Adjustment / Store DADDR Address"] -pub type SlastSdaR = crate::FieldReader; -#[doc = "Field `SLAST_SDA` writer - Last Source Address Adjustment / Store DADDR Address"] -pub type SlastSdaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Last Source Address Adjustment / Store DADDR Address"] - #[inline(always)] - pub fn slast_sda(&self) -> SlastSdaR { - SlastSdaR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Last Source Address Adjustment / Store DADDR Address"] - #[inline(always)] - pub fn slast_sda(&mut self) -> SlastSdaW { - SlastSdaW::new(self, 0) - } -} -#[doc = "TCD Last Source Address Adjustment / Store DADDR Address\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_slast_sda::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_slast_sda::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdSlastSdaSpec; -impl crate::RegisterSpec for TcdSlastSdaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcd_slast_sda::R`](R) reader structure"] -impl crate::Readable for TcdSlastSdaSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_slast_sda::W`](W) writer structure"] -impl crate::Writable for TcdSlastSdaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_SLAST_SDA to value 0"] -impl crate::Resettable for TcdSlastSdaSpec {} diff --git a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs b/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs deleted file mode 100644 index a202598d1..000000000 --- a/mcxa276-pac/src/edma_0_tcd0/tcd/tcd_soff.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TCD_SOFF` reader"] -pub type R = crate::R; -#[doc = "Register `TCD_SOFF` writer"] -pub type W = crate::W; -#[doc = "Field `SOFF` reader - Source Address Signed Offset"] -pub type SoffR = crate::FieldReader; -#[doc = "Field `SOFF` writer - Source Address Signed Offset"] -pub type SoffW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Source Address Signed Offset"] - #[inline(always)] - pub fn soff(&self) -> SoffR { - SoffR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Source Address Signed Offset"] - #[inline(always)] - pub fn soff(&mut self) -> SoffW { - SoffW::new(self, 0) - } -} -#[doc = "TCD Signed Source Address Offset\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_soff::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_soff::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcdSoffSpec; -impl crate::RegisterSpec for TcdSoffSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`tcd_soff::R`](R) reader structure"] -impl crate::Readable for TcdSoffSpec {} -#[doc = "`write(|w| ..)` method takes [`tcd_soff::W`](W) writer structure"] -impl crate::Writable for TcdSoffSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCD_SOFF to value 0"] -impl crate::Resettable for TcdSoffSpec {} diff --git a/mcxa276-pac/src/eim0.rs b/mcxa276-pac/src/eim0.rs deleted file mode 100644 index ed857f2b0..000000000 --- a/mcxa276-pac/src/eim0.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - eimcr: Eimcr, - eichen: Eichen, - _reserved2: [u8; 0xf8], - eichd0_word0: Eichd0Word0, - eichd0_word1: Eichd0Word1, -} -impl RegisterBlock { - #[doc = "0x00 - Error Injection Module Configuration Register"] - #[inline(always)] - pub const fn eimcr(&self) -> &Eimcr { - &self.eimcr - } - #[doc = "0x04 - Error Injection Channel Enable register"] - #[inline(always)] - pub const fn eichen(&self) -> &Eichen { - &self.eichen - } - #[doc = "0x100 - Error Injection Channel Descriptor 0, Word0"] - #[inline(always)] - pub const fn eichd0_word0(&self) -> &Eichd0Word0 { - &self.eichd0_word0 - } - #[doc = "0x104 - Error Injection Channel Descriptor 0, Word1"] - #[inline(always)] - pub const fn eichd0_word1(&self) -> &Eichd0Word1 { - &self.eichd0_word1 - } -} -#[doc = "EIMCR (rw) register accessor: Error Injection Module Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eimcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eimcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eimcr`] module"] -#[doc(alias = "EIMCR")] -pub type Eimcr = crate::Reg; -#[doc = "Error Injection Module Configuration Register"] -pub mod eimcr; -#[doc = "EICHEN (rw) register accessor: Error Injection Channel Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`eichen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eichen`] module"] -#[doc(alias = "EICHEN")] -pub type Eichen = crate::Reg; -#[doc = "Error Injection Channel Enable register"] -pub mod eichen; -#[doc = "EICHD0_WORD0 (rw) register accessor: Error Injection Channel Descriptor 0, Word0\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eichd0_word0`] module"] -#[doc(alias = "EICHD0_WORD0")] -pub type Eichd0Word0 = crate::Reg; -#[doc = "Error Injection Channel Descriptor 0, Word0"] -pub mod eichd0_word0; -#[doc = "EICHD0_WORD1 (rw) register accessor: Error Injection Channel Descriptor 0, Word1\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eichd0_word1`] module"] -#[doc(alias = "EICHD0_WORD1")] -pub type Eichd0Word1 = crate::Reg; -#[doc = "Error Injection Channel Descriptor 0, Word1"] -pub mod eichd0_word1; diff --git a/mcxa276-pac/src/eim0/eichd0_word0.rs b/mcxa276-pac/src/eim0/eichd0_word0.rs deleted file mode 100644 index 0dfe456fa..000000000 --- a/mcxa276-pac/src/eim0/eichd0_word0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `EICHD0_WORD0` reader"] -pub type R = crate::R; -#[doc = "Register `EICHD0_WORD0` writer"] -pub type W = crate::W; -#[doc = "Field `CHKBIT_MASK` reader - Checkbit Mask"] -pub type ChkbitMaskR = crate::FieldReader; -#[doc = "Field `CHKBIT_MASK` writer - Checkbit Mask"] -pub type ChkbitMaskW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bits 25:31 - Checkbit Mask"] - #[inline(always)] - pub fn chkbit_mask(&self) -> ChkbitMaskR { - ChkbitMaskR::new(((self.bits >> 25) & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 25:31 - Checkbit Mask"] - #[inline(always)] - pub fn chkbit_mask(&mut self) -> ChkbitMaskW { - ChkbitMaskW::new(self, 25) - } -} -#[doc = "Error Injection Channel Descriptor 0, Word0\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Eichd0Word0Spec; -impl crate::RegisterSpec for Eichd0Word0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`eichd0_word0::R`](R) reader structure"] -impl crate::Readable for Eichd0Word0Spec {} -#[doc = "`write(|w| ..)` method takes [`eichd0_word0::W`](W) writer structure"] -impl crate::Writable for Eichd0Word0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EICHD0_WORD0 to value 0"] -impl crate::Resettable for Eichd0Word0Spec {} diff --git a/mcxa276-pac/src/eim0/eichd0_word1.rs b/mcxa276-pac/src/eim0/eichd0_word1.rs deleted file mode 100644 index dd14d3c4e..000000000 --- a/mcxa276-pac/src/eim0/eichd0_word1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `EICHD0_WORD1` reader"] -pub type R = crate::R; -#[doc = "Register `EICHD0_WORD1` writer"] -pub type W = crate::W; -#[doc = "Field `B0_3DATA_MASK` reader - Data Mask Bytes 0-3"] -pub type B0_3dataMaskR = crate::FieldReader; -#[doc = "Field `B0_3DATA_MASK` writer - Data Mask Bytes 0-3"] -pub type B0_3dataMaskW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Data Mask Bytes 0-3"] - #[inline(always)] - pub fn b0_3data_mask(&self) -> B0_3dataMaskR { - B0_3dataMaskR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Data Mask Bytes 0-3"] - #[inline(always)] - pub fn b0_3data_mask(&mut self) -> B0_3dataMaskW { - B0_3dataMaskW::new(self, 0) - } -} -#[doc = "Error Injection Channel Descriptor 0, Word1\n\nYou can [`read`](crate::Reg::read) this register and get [`eichd0_word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichd0_word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Eichd0Word1Spec; -impl crate::RegisterSpec for Eichd0Word1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`eichd0_word1::R`](R) reader structure"] -impl crate::Readable for Eichd0Word1Spec {} -#[doc = "`write(|w| ..)` method takes [`eichd0_word1::W`](W) writer structure"] -impl crate::Writable for Eichd0Word1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EICHD0_WORD1 to value 0"] -impl crate::Resettable for Eichd0Word1Spec {} diff --git a/mcxa276-pac/src/eim0/eichen.rs b/mcxa276-pac/src/eim0/eichen.rs deleted file mode 100644 index 21daadd2b..000000000 --- a/mcxa276-pac/src/eim0/eichen.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `EICHEN` reader"] -pub type R = crate::R; -#[doc = "Register `EICHEN` writer"] -pub type W = crate::W; -#[doc = "Error Injection Channel 0 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Eich0en { - #[doc = "0: Error injection is disabled on Error Injection Channel 0"] - Disable = 0, - #[doc = "1: Error injection is enabled on Error Injection Channel 0"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Eich0en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EICH0EN` reader - Error Injection Channel 0 Enable"] -pub type Eich0enR = crate::BitReader; -impl Eich0enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Eich0en { - match self.bits { - false => Eich0en::Disable, - true => Eich0en::Enable, - } - } - #[doc = "Error injection is disabled on Error Injection Channel 0"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Eich0en::Disable - } - #[doc = "Error injection is enabled on Error Injection Channel 0"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Eich0en::Enable - } -} -#[doc = "Field `EICH0EN` writer - Error Injection Channel 0 Enable"] -pub type Eich0enW<'a, REG> = crate::BitWriter<'a, REG, Eich0en>; -impl<'a, REG> Eich0enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error injection is disabled on Error Injection Channel 0"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Eich0en::Disable) - } - #[doc = "Error injection is enabled on Error Injection Channel 0"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Eich0en::Enable) - } -} -impl R { - #[doc = "Bit 31 - Error Injection Channel 0 Enable"] - #[inline(always)] - pub fn eich0en(&self) -> Eich0enR { - Eich0enR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 31 - Error Injection Channel 0 Enable"] - #[inline(always)] - pub fn eich0en(&mut self) -> Eich0enW { - Eich0enW::new(self, 31) - } -} -#[doc = "Error Injection Channel Enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`eichen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eichen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EichenSpec; -impl crate::RegisterSpec for EichenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`eichen::R`](R) reader structure"] -impl crate::Readable for EichenSpec {} -#[doc = "`write(|w| ..)` method takes [`eichen::W`](W) writer structure"] -impl crate::Writable for EichenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EICHEN to value 0"] -impl crate::Resettable for EichenSpec {} diff --git a/mcxa276-pac/src/eim0/eimcr.rs b/mcxa276-pac/src/eim0/eimcr.rs deleted file mode 100644 index 12e308c44..000000000 --- a/mcxa276-pac/src/eim0/eimcr.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `EIMCR` reader"] -pub type R = crate::R; -#[doc = "Register `EIMCR` writer"] -pub type W = crate::W; -#[doc = "Global Error Injection Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Geien { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Geien) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GEIEN` reader - Global Error Injection Enable"] -pub type GeienR = crate::BitReader; -impl GeienR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Geien { - match self.bits { - false => Geien::Disable, - true => Geien::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Geien::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Geien::Enable - } -} -#[doc = "Field `GEIEN` writer - Global Error Injection Enable"] -pub type GeienW<'a, REG> = crate::BitWriter<'a, REG, Geien>; -impl<'a, REG> GeienW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Geien::Disable) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Geien::Enable) - } -} -impl R { - #[doc = "Bit 0 - Global Error Injection Enable"] - #[inline(always)] - pub fn geien(&self) -> GeienR { - GeienR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Global Error Injection Enable"] - #[inline(always)] - pub fn geien(&mut self) -> GeienW { - GeienW::new(self, 0) - } -} -#[doc = "Error Injection Module Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eimcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eimcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EimcrSpec; -impl crate::RegisterSpec for EimcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`eimcr::R`](R) reader structure"] -impl crate::Readable for EimcrSpec {} -#[doc = "`write(|w| ..)` method takes [`eimcr::W`](W) writer structure"] -impl crate::Writable for EimcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EIMCR to value 0"] -impl crate::Resettable for EimcrSpec {} diff --git a/mcxa276-pac/src/eqdc0.rs b/mcxa276-pac/src/eqdc0.rs deleted file mode 100644 index 0e60b58a6..000000000 --- a/mcxa276-pac/src/eqdc0.rs +++ /dev/null @@ -1,441 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - ctrl: Ctrl, - ctrl2: Ctrl2, - filt: Filt, - lastedge: Lastedge, - posdper: Posdper, - posdperbfr: Posdperbfr, - upos: Upos, - lpos: Lpos, - posd: Posd, - posdh: Posdh, - uposh: Uposh, - lposh: Lposh, - lastedgeh: Lastedgeh, - posdperh: Posdperh, - revh: Revh, - rev: Rev, - uinit: Uinit, - linit: Linit, - umod: Umod, - lmod: Lmod, - ucomp0: Ucomp0, - lcomp0: Lcomp0, - _reserved_22_ucomp1_ucomp1: [u8; 0x02], - _reserved_23_lcomp1_lcomp1: [u8; 0x02], - _reserved_24_ucomp2_ucomp2: [u8; 0x02], - _reserved_25_lcomp2_lcomp2: [u8; 0x02], - _reserved_26_ucomp3_ucomp3: [u8; 0x02], - _reserved_27_lcomp3_lcomp3: [u8; 0x02], - intctrl: Intctrl, - wtr: Wtr, - imr: Imr, - tst: Tst, - _reserved32: [u8; 0x10], - uverid: Uverid, - lverid: Lverid, -} -impl RegisterBlock { - #[doc = "0x00 - Control Register"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } - #[doc = "0x02 - Control 2 Register"] - #[inline(always)] - pub const fn ctrl2(&self) -> &Ctrl2 { - &self.ctrl2 - } - #[doc = "0x04 - Input Filter Register"] - #[inline(always)] - pub const fn filt(&self) -> &Filt { - &self.filt - } - #[doc = "0x06 - Last Edge Time Register"] - #[inline(always)] - pub const fn lastedge(&self) -> &Lastedge { - &self.lastedge - } - #[doc = "0x08 - Position Difference Period Counter Register"] - #[inline(always)] - pub const fn posdper(&self) -> &Posdper { - &self.posdper - } - #[doc = "0x0a - Position Difference Period Buffer Register"] - #[inline(always)] - pub const fn posdperbfr(&self) -> &Posdperbfr { - &self.posdperbfr - } - #[doc = "0x0c - Upper Position Counter Register"] - #[inline(always)] - pub const fn upos(&self) -> &Upos { - &self.upos - } - #[doc = "0x0e - Lower Position Counter Register"] - #[inline(always)] - pub const fn lpos(&self) -> &Lpos { - &self.lpos - } - #[doc = "0x10 - Position Difference Counter Register"] - #[inline(always)] - pub const fn posd(&self) -> &Posd { - &self.posd - } - #[doc = "0x12 - Position Difference Hold Register"] - #[inline(always)] - pub const fn posdh(&self) -> &Posdh { - &self.posdh - } - #[doc = "0x14 - Upper Position Hold Register"] - #[inline(always)] - pub const fn uposh(&self) -> &Uposh { - &self.uposh - } - #[doc = "0x16 - Lower Position Hold Register"] - #[inline(always)] - pub const fn lposh(&self) -> &Lposh { - &self.lposh - } - #[doc = "0x18 - Last Edge Time Hold Register"] - #[inline(always)] - pub const fn lastedgeh(&self) -> &Lastedgeh { - &self.lastedgeh - } - #[doc = "0x1a - Position Difference Period Hold Register"] - #[inline(always)] - pub const fn posdperh(&self) -> &Posdperh { - &self.posdperh - } - #[doc = "0x1c - Revolution Hold Register"] - #[inline(always)] - pub const fn revh(&self) -> &Revh { - &self.revh - } - #[doc = "0x1e - Revolution Counter Register"] - #[inline(always)] - pub const fn rev(&self) -> &Rev { - &self.rev - } - #[doc = "0x20 - Upper Initialization Register"] - #[inline(always)] - pub const fn uinit(&self) -> &Uinit { - &self.uinit - } - #[doc = "0x22 - Lower Initialization Register"] - #[inline(always)] - pub const fn linit(&self) -> &Linit { - &self.linit - } - #[doc = "0x24 - Upper Modulus Register"] - #[inline(always)] - pub const fn umod(&self) -> &Umod { - &self.umod - } - #[doc = "0x26 - Lower Modulus Register"] - #[inline(always)] - pub const fn lmod(&self) -> &Lmod { - &self.lmod - } - #[doc = "0x28 - Upper Position Compare Register 0"] - #[inline(always)] - pub const fn ucomp0(&self) -> &Ucomp0 { - &self.ucomp0 - } - #[doc = "0x2a - Lower Position Compare Register 0"] - #[inline(always)] - pub const fn lcomp0(&self) -> &Lcomp0 { - &self.lcomp0 - } - #[doc = "0x2c - Upper Position Holder Register 1"] - #[inline(always)] - pub const fn uposh1_uposh1(&self) -> &Uposh1Uposh1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } - } - #[doc = "0x2c - Upper Position Compare 1"] - #[inline(always)] - pub const fn ucomp1_ucomp1(&self) -> &Ucomp1Ucomp1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } - } - #[doc = "0x2e - Lower Position Holder Register 1"] - #[inline(always)] - pub const fn lposh1_lposh1(&self) -> &Lposh1Lposh1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(46).cast() } - } - #[doc = "0x2e - Lower Position Compare 1"] - #[inline(always)] - pub const fn lcomp1_lcomp1(&self) -> &Lcomp1Lcomp1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(46).cast() } - } - #[doc = "0x30 - Upper Position Holder Register 3"] - #[inline(always)] - pub const fn uposh2_uposh2(&self) -> &Uposh2Uposh2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } - } - #[doc = "0x30 - Upper Position Compare 2"] - #[inline(always)] - pub const fn ucomp2_ucomp2(&self) -> &Ucomp2Ucomp2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } - } - #[doc = "0x32 - Lower Position Holder Register 2"] - #[inline(always)] - pub const fn lposh2_lposh2(&self) -> &Lposh2Lposh2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(50).cast() } - } - #[doc = "0x32 - Lower Position Compare 2"] - #[inline(always)] - pub const fn lcomp2_lcomp2(&self) -> &Lcomp2Lcomp2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(50).cast() } - } - #[doc = "0x34 - Upper Position Holder Register 3"] - #[inline(always)] - pub const fn uposh3_uposh3(&self) -> &Uposh3Uposh3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } - } - #[doc = "0x34 - Upper Position Compare 3"] - #[inline(always)] - pub const fn ucomp3_ucomp3(&self) -> &Ucomp3Ucomp3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } - } - #[doc = "0x36 - Lower Position Holder Register 3"] - #[inline(always)] - pub const fn lposh3_lposh3(&self) -> &Lposh3Lposh3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } - } - #[doc = "0x36 - Lower Position Compare 3"] - #[inline(always)] - pub const fn lcomp3_lcomp3(&self) -> &Lcomp3Lcomp3 { - unsafe { &*core::ptr::from_ref(self).cast::().add(54).cast() } - } - #[doc = "0x38 - Interrupt Control Register"] - #[inline(always)] - pub const fn intctrl(&self) -> &Intctrl { - &self.intctrl - } - #[doc = "0x3a - Watchdog Timeout Register"] - #[inline(always)] - pub const fn wtr(&self) -> &Wtr { - &self.wtr - } - #[doc = "0x3c - Input Monitor Register"] - #[inline(always)] - pub const fn imr(&self) -> &Imr { - &self.imr - } - #[doc = "0x3e - Test Register"] - #[inline(always)] - pub const fn tst(&self) -> &Tst { - &self.tst - } - #[doc = "0x50 - Upper VERID"] - #[inline(always)] - pub const fn uverid(&self) -> &Uverid { - &self.uverid - } - #[doc = "0x52 - Lower VERID"] - #[inline(always)] - pub const fn lverid(&self) -> &Lverid { - &self.lverid - } -} -#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "Control Register"] -pub mod ctrl; -#[doc = "CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"] -#[doc(alias = "CTRL2")] -pub type Ctrl2 = crate::Reg; -#[doc = "Control 2 Register"] -pub mod ctrl2; -#[doc = "FILT (rw) register accessor: Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filt`] module"] -#[doc(alias = "FILT")] -pub type Filt = crate::Reg; -#[doc = "Input Filter Register"] -pub mod filt; -#[doc = "LASTEDGE (r) register accessor: Last Edge Time Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedge::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lastedge`] module"] -#[doc(alias = "LASTEDGE")] -pub type Lastedge = crate::Reg; -#[doc = "Last Edge Time Register"] -pub mod lastedge; -#[doc = "POSDPER (r) register accessor: Position Difference Period Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdper::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdper`] module"] -#[doc(alias = "POSDPER")] -pub type Posdper = crate::Reg; -#[doc = "Position Difference Period Counter Register"] -pub mod posdper; -#[doc = "POSDPERBFR (r) register accessor: Position Difference Period Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperbfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdperbfr`] module"] -#[doc(alias = "POSDPERBFR")] -pub type Posdperbfr = crate::Reg; -#[doc = "Position Difference Period Buffer Register"] -pub mod posdperbfr; -#[doc = "UPOS (rw) register accessor: Upper Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`upos::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`upos::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upos`] module"] -#[doc(alias = "UPOS")] -pub type Upos = crate::Reg; -#[doc = "Upper Position Counter Register"] -pub mod upos; -#[doc = "LPOS (rw) register accessor: Lower Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lpos::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpos::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpos`] module"] -#[doc(alias = "LPOS")] -pub type Lpos = crate::Reg; -#[doc = "Lower Position Counter Register"] -pub mod lpos; -#[doc = "POSD (rw) register accessor: Position Difference Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`posd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posd`] module"] -#[doc(alias = "POSD")] -pub type Posd = crate::Reg; -#[doc = "Position Difference Counter Register"] -pub mod posd; -#[doc = "POSDH (r) register accessor: Position Difference Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdh`] module"] -#[doc(alias = "POSDH")] -pub type Posdh = crate::Reg; -#[doc = "Position Difference Hold Register"] -pub mod posdh; -#[doc = "UPOSH (r) register accessor: Upper Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh`] module"] -#[doc(alias = "UPOSH")] -pub type Uposh = crate::Reg; -#[doc = "Upper Position Hold Register"] -pub mod uposh; -#[doc = "LPOSH (r) register accessor: Lower Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh`] module"] -#[doc(alias = "LPOSH")] -pub type Lposh = crate::Reg; -#[doc = "Lower Position Hold Register"] -pub mod lposh; -#[doc = "LASTEDGEH (r) register accessor: Last Edge Time Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedgeh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lastedgeh`] module"] -#[doc(alias = "LASTEDGEH")] -pub type Lastedgeh = crate::Reg; -#[doc = "Last Edge Time Hold Register"] -pub mod lastedgeh; -#[doc = "POSDPERH (r) register accessor: Position Difference Period Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@posdperh`] module"] -#[doc(alias = "POSDPERH")] -pub type Posdperh = crate::Reg; -#[doc = "Position Difference Period Hold Register"] -pub mod posdperh; -#[doc = "REVH (r) register accessor: Revolution Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`revh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@revh`] module"] -#[doc(alias = "REVH")] -pub type Revh = crate::Reg; -#[doc = "Revolution Hold Register"] -pub mod revh; -#[doc = "REV (rw) register accessor: Revolution Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rev::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rev`] module"] -#[doc(alias = "REV")] -pub type Rev = crate::Reg; -#[doc = "Revolution Counter Register"] -pub mod rev; -#[doc = "UINIT (rw) register accessor: Upper Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uinit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uinit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uinit`] module"] -#[doc(alias = "UINIT")] -pub type Uinit = crate::Reg; -#[doc = "Upper Initialization Register"] -pub mod uinit; -#[doc = "LINIT (rw) register accessor: Lower Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`linit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linit`] module"] -#[doc(alias = "LINIT")] -pub type Linit = crate::Reg; -#[doc = "Lower Initialization Register"] -pub mod linit; -#[doc = "UMOD (rw) register accessor: Upper Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`umod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`umod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@umod`] module"] -#[doc(alias = "UMOD")] -pub type Umod = crate::Reg; -#[doc = "Upper Modulus Register"] -pub mod umod; -#[doc = "LMOD (rw) register accessor: Lower Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lmod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lmod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lmod`] module"] -#[doc(alias = "LMOD")] -pub type Lmod = crate::Reg; -#[doc = "Lower Modulus Register"] -pub mod lmod; -#[doc = "UCOMP0 (rw) register accessor: Upper Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucomp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp0`] module"] -#[doc(alias = "UCOMP0")] -pub type Ucomp0 = crate::Reg; -#[doc = "Upper Position Compare Register 0"] -pub mod ucomp0; -#[doc = "LCOMP0 (rw) register accessor: Lower Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcomp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp0`] module"] -#[doc(alias = "LCOMP0")] -pub type Lcomp0 = crate::Reg; -#[doc = "Lower Position Compare Register 0"] -pub mod lcomp0; -#[doc = "UCOMP1_UCOMP1 (w) register accessor: Upper Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp1_ucomp1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp1_ucomp1`] module"] -#[doc(alias = "UCOMP1_UCOMP1")] -pub type Ucomp1Ucomp1 = crate::Reg; -#[doc = "Upper Position Compare 1"] -pub mod ucomp1_ucomp1; -#[doc = "UPOSH1_UPOSH1 (r) register accessor: Upper Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh1_uposh1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh1_uposh1`] module"] -#[doc(alias = "UPOSH1_UPOSH1")] -pub type Uposh1Uposh1 = crate::Reg; -#[doc = "Upper Position Holder Register 1"] -pub mod uposh1_uposh1; -#[doc = "LCOMP1_LCOMP1 (w) register accessor: Lower Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp1_lcomp1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp1_lcomp1`] module"] -#[doc(alias = "LCOMP1_LCOMP1")] -pub type Lcomp1Lcomp1 = crate::Reg; -#[doc = "Lower Position Compare 1"] -pub mod lcomp1_lcomp1; -#[doc = "LPOSH1_LPOSH1 (r) register accessor: Lower Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh1_lposh1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh1_lposh1`] module"] -#[doc(alias = "LPOSH1_LPOSH1")] -pub type Lposh1Lposh1 = crate::Reg; -#[doc = "Lower Position Holder Register 1"] -pub mod lposh1_lposh1; -#[doc = "UCOMP2_UCOMP2 (w) register accessor: Upper Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp2_ucomp2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp2_ucomp2`] module"] -#[doc(alias = "UCOMP2_UCOMP2")] -pub type Ucomp2Ucomp2 = crate::Reg; -#[doc = "Upper Position Compare 2"] -pub mod ucomp2_ucomp2; -#[doc = "UPOSH2_UPOSH2 (r) register accessor: Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh2_uposh2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh2_uposh2`] module"] -#[doc(alias = "UPOSH2_UPOSH2")] -pub type Uposh2Uposh2 = crate::Reg; -#[doc = "Upper Position Holder Register 3"] -pub mod uposh2_uposh2; -#[doc = "LCOMP2_LCOMP2 (w) register accessor: Lower Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp2_lcomp2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp2_lcomp2`] module"] -#[doc(alias = "LCOMP2_LCOMP2")] -pub type Lcomp2Lcomp2 = crate::Reg; -#[doc = "Lower Position Compare 2"] -pub mod lcomp2_lcomp2; -#[doc = "LPOSH2_LPOSH2 (r) register accessor: Lower Position Holder Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh2_lposh2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh2_lposh2`] module"] -#[doc(alias = "LPOSH2_LPOSH2")] -pub type Lposh2Lposh2 = crate::Reg; -#[doc = "Lower Position Holder Register 2"] -pub mod lposh2_lposh2; -#[doc = "UCOMP3_UCOMP3 (w) register accessor: Upper Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp3_ucomp3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucomp3_ucomp3`] module"] -#[doc(alias = "UCOMP3_UCOMP3")] -pub type Ucomp3Ucomp3 = crate::Reg; -#[doc = "Upper Position Compare 3"] -pub mod ucomp3_ucomp3; -#[doc = "UPOSH3_UPOSH3 (r) register accessor: Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh3_uposh3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uposh3_uposh3`] module"] -#[doc(alias = "UPOSH3_UPOSH3")] -pub type Uposh3Uposh3 = crate::Reg; -#[doc = "Upper Position Holder Register 3"] -pub mod uposh3_uposh3; -#[doc = "LCOMP3_LCOMP3 (w) register accessor: Lower Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp3_lcomp3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcomp3_lcomp3`] module"] -#[doc(alias = "LCOMP3_LCOMP3")] -pub type Lcomp3Lcomp3 = crate::Reg; -#[doc = "Lower Position Compare 3"] -pub mod lcomp3_lcomp3; -#[doc = "LPOSH3_LPOSH3 (r) register accessor: Lower Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh3_lposh3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lposh3_lposh3`] module"] -#[doc(alias = "LPOSH3_LPOSH3")] -pub type Lposh3Lposh3 = crate::Reg; -#[doc = "Lower Position Holder Register 3"] -pub mod lposh3_lposh3; -#[doc = "INTCTRL (rw) register accessor: Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intctrl`] module"] -#[doc(alias = "INTCTRL")] -pub type Intctrl = crate::Reg; -#[doc = "Interrupt Control Register"] -pub mod intctrl; -#[doc = "WTR (rw) register accessor: Watchdog Timeout Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wtr`] module"] -#[doc(alias = "WTR")] -pub type Wtr = crate::Reg; -#[doc = "Watchdog Timeout Register"] -pub mod wtr; -#[doc = "IMR (rw) register accessor: Input Monitor Register\n\nYou can [`read`](crate::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imr`] module"] -#[doc(alias = "IMR")] -pub type Imr = crate::Reg; -#[doc = "Input Monitor Register"] -pub mod imr; -#[doc = "TST (rw) register accessor: Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tst`] module"] -#[doc(alias = "TST")] -pub type Tst = crate::Reg; -#[doc = "Test Register"] -pub mod tst; -#[doc = "UVERID (r) register accessor: Upper VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`uverid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uverid`] module"] -#[doc(alias = "UVERID")] -pub type Uverid = crate::Reg; -#[doc = "Upper VERID"] -pub mod uverid; -#[doc = "LVERID (r) register accessor: Lower VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`lverid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lverid`] module"] -#[doc(alias = "LVERID")] -pub type Lverid = crate::Reg; -#[doc = "Lower VERID"] -pub mod lverid; diff --git a/mcxa276-pac/src/eqdc0/ctrl.rs b/mcxa276-pac/src/eqdc0/ctrl.rs deleted file mode 100644 index 7b3fc2c2e..000000000 --- a/mcxa276-pac/src/eqdc0/ctrl.rs +++ /dev/null @@ -1,1030 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "Load Okay\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldok { - #[doc = "0: No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)"] - Ldok0 = 0, - #[doc = "1: Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2\\[LDMOD\\]."] - Ldok1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldok) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDOK` reader - Load Okay"] -pub type LdokR = crate::BitReader; -impl LdokR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldok { - match self.bits { - false => Ldok::Ldok0, - true => Ldok::Ldok1, - } - } - #[doc = "No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)"] - #[inline(always)] - pub fn is_ldok0(&self) -> bool { - *self == Ldok::Ldok0 - } - #[doc = "Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2\\[LDMOD\\]."] - #[inline(always)] - pub fn is_ldok1(&self) -> bool { - *self == Ldok::Ldok1 - } -} -#[doc = "Field `LDOK` writer - Load Okay"] -pub type LdokW<'a, REG> = crate::BitWriter<'a, REG, Ldok>; -impl<'a, REG> LdokW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)"] - #[inline(always)] - pub fn ldok0(self) -> &'a mut crate::W { - self.variant(Ldok::Ldok0) - } - #[doc = "Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2\\[LDMOD\\]."] - #[inline(always)] - pub fn ldok1(self) -> &'a mut crate::W { - self.variant(Ldok::Ldok1) - } -} -#[doc = "DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmaen { - #[doc = "0: DMA is disabled"] - Dmaen0 = 0, - #[doc = "1: DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be loaded into inner-set which in turn triggers DMA again."] - Dmaen1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmaen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMAEN` reader - DMA Enable"] -pub type DmaenR = crate::BitReader; -impl DmaenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmaen { - match self.bits { - false => Dmaen::Dmaen0, - true => Dmaen::Dmaen1, - } - } - #[doc = "DMA is disabled"] - #[inline(always)] - pub fn is_dmaen_0(&self) -> bool { - *self == Dmaen::Dmaen0 - } - #[doc = "DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be loaded into inner-set which in turn triggers DMA again."] - #[inline(always)] - pub fn is_dmaen_1(&self) -> bool { - *self == Dmaen::Dmaen1 - } -} -#[doc = "Field `DMAEN` writer - DMA Enable"] -pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG, Dmaen>; -impl<'a, REG> DmaenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DMA is disabled"] - #[inline(always)] - pub fn dmaen_0(self) -> &'a mut crate::W { - self.variant(Dmaen::Dmaen0) - } - #[doc = "DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be loaded into inner-set which in turn triggers DMA again."] - #[inline(always)] - pub fn dmaen_1(self) -> &'a mut crate::W { - self.variant(Dmaen::Dmaen1) - } -} -#[doc = "Watchdog Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wde { - #[doc = "0: Disabled"] - Wde0 = 0, - #[doc = "1: Enabled"] - Wde1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDE` reader - Watchdog Enable"] -pub type WdeR = crate::BitReader; -impl WdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wde { - match self.bits { - false => Wde::Wde0, - true => Wde::Wde1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_wde0(&self) -> bool { - *self == Wde::Wde0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_wde1(&self) -> bool { - *self == Wde::Wde1 - } -} -#[doc = "Field `WDE` writer - Watchdog Enable"] -pub type WdeW<'a, REG> = crate::BitWriter<'a, REG, Wde>; -impl<'a, REG> WdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn wde0(self) -> &'a mut crate::W { - self.variant(Wde::Wde0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn wde1(self) -> &'a mut crate::W { - self.variant(Wde::Wde1) - } -} -#[doc = "Watchdog Timeout Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wdie { - #[doc = "0: Disabled"] - Wdie0 = 0, - #[doc = "1: Enabled"] - Wdie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDIE` reader - Watchdog Timeout Interrupt Enable"] -pub type WdieR = crate::BitReader; -impl WdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wdie { - match self.bits { - false => Wdie::Wdie0, - true => Wdie::Wdie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_wdie0(&self) -> bool { - *self == Wdie::Wdie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_wdie1(&self) -> bool { - *self == Wdie::Wdie1 - } -} -#[doc = "Field `WDIE` writer - Watchdog Timeout Interrupt Enable"] -pub type WdieW<'a, REG> = crate::BitWriter<'a, REG, Wdie>; -impl<'a, REG> WdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn wdie0(self) -> &'a mut crate::W { - self.variant(Wdie::Wdie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn wdie1(self) -> &'a mut crate::W { - self.variant(Wdie::Wdie1) - } -} -#[doc = "Watchdog Timeout Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wdirq { - #[doc = "0: No Watchdog timeout interrupt has occurred"] - Wdirq0 = 0, - #[doc = "1: Watchdog timeout interrupt has occurred"] - Wdirq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wdirq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDIRQ` reader - Watchdog Timeout Interrupt Request"] -pub type WdirqR = crate::BitReader; -impl WdirqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wdirq { - match self.bits { - false => Wdirq::Wdirq0, - true => Wdirq::Wdirq1, - } - } - #[doc = "No Watchdog timeout interrupt has occurred"] - #[inline(always)] - pub fn is_wdirq0(&self) -> bool { - *self == Wdirq::Wdirq0 - } - #[doc = "Watchdog timeout interrupt has occurred"] - #[inline(always)] - pub fn is_wdirq1(&self) -> bool { - *self == Wdirq::Wdirq1 - } -} -#[doc = "Field `WDIRQ` writer - Watchdog Timeout Interrupt Request"] -pub type WdirqW<'a, REG> = crate::BitWriter1C<'a, REG, Wdirq>; -impl<'a, REG> WdirqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No Watchdog timeout interrupt has occurred"] - #[inline(always)] - pub fn wdirq0(self) -> &'a mut crate::W { - self.variant(Wdirq::Wdirq0) - } - #[doc = "Watchdog timeout interrupt has occurred"] - #[inline(always)] - pub fn wdirq1(self) -> &'a mut crate::W { - self.variant(Wdirq::Wdirq1) - } -} -#[doc = "Select Positive/Negative Edge of INDEX/PRESET Pulse\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Xne { - #[doc = "0: Use positive edge of INDEX/PRESET pulse"] - Xne0 = 0, - #[doc = "1: Use negative edge of INDEX/PRESET pulse"] - Xne1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Xne) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `XNE` reader - Select Positive/Negative Edge of INDEX/PRESET Pulse"] -pub type XneR = crate::BitReader; -impl XneR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Xne { - match self.bits { - false => Xne::Xne0, - true => Xne::Xne1, - } - } - #[doc = "Use positive edge of INDEX/PRESET pulse"] - #[inline(always)] - pub fn is_xne0(&self) -> bool { - *self == Xne::Xne0 - } - #[doc = "Use negative edge of INDEX/PRESET pulse"] - #[inline(always)] - pub fn is_xne1(&self) -> bool { - *self == Xne::Xne1 - } -} -#[doc = "Field `XNE` writer - Select Positive/Negative Edge of INDEX/PRESET Pulse"] -pub type XneW<'a, REG> = crate::BitWriter<'a, REG, Xne>; -impl<'a, REG> XneW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Use positive edge of INDEX/PRESET pulse"] - #[inline(always)] - pub fn xne0(self) -> &'a mut crate::W { - self.variant(Xne::Xne0) - } - #[doc = "Use negative edge of INDEX/PRESET pulse"] - #[inline(always)] - pub fn xne1(self) -> &'a mut crate::W { - self.variant(Xne::Xne1) - } -} -#[doc = "INDEX Triggered Initialization of Position Counters UPOS and LPOS\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Xip { - #[doc = "0: INDEX pulse does not initialize the position counter"] - Xip0 = 0, - #[doc = "1: INDEX pulse initializes the position counter"] - Xip1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Xip) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `XIP` reader - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] -pub type XipR = crate::BitReader; -impl XipR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Xip { - match self.bits { - false => Xip::Xip0, - true => Xip::Xip1, - } - } - #[doc = "INDEX pulse does not initialize the position counter"] - #[inline(always)] - pub fn is_xip0(&self) -> bool { - *self == Xip::Xip0 - } - #[doc = "INDEX pulse initializes the position counter"] - #[inline(always)] - pub fn is_xip1(&self) -> bool { - *self == Xip::Xip1 - } -} -#[doc = "Field `XIP` writer - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] -pub type XipW<'a, REG> = crate::BitWriter<'a, REG, Xip>; -impl<'a, REG> XipW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "INDEX pulse does not initialize the position counter"] - #[inline(always)] - pub fn xip0(self) -> &'a mut crate::W { - self.variant(Xip::Xip0) - } - #[doc = "INDEX pulse initializes the position counter"] - #[inline(always)] - pub fn xip1(self) -> &'a mut crate::W { - self.variant(Xip::Xip1) - } -} -#[doc = "INDEX/PRESET Pulse Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Xie { - #[doc = "0: Disabled"] - Xie0 = 0, - #[doc = "1: Enabled"] - Xie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Xie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `XIE` reader - INDEX/PRESET Pulse Interrupt Enable"] -pub type XieR = crate::BitReader; -impl XieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Xie { - match self.bits { - false => Xie::Xie0, - true => Xie::Xie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_xie0(&self) -> bool { - *self == Xie::Xie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_xie1(&self) -> bool { - *self == Xie::Xie1 - } -} -#[doc = "Field `XIE` writer - INDEX/PRESET Pulse Interrupt Enable"] -pub type XieW<'a, REG> = crate::BitWriter<'a, REG, Xie>; -impl<'a, REG> XieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn xie0(self) -> &'a mut crate::W { - self.variant(Xie::Xie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn xie1(self) -> &'a mut crate::W { - self.variant(Xie::Xie1) - } -} -#[doc = "INDEX/PRESET Pulse Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Xirq { - #[doc = "0: INDEX/PRESET pulse has not occurred"] - Xirq0 = 0, - #[doc = "1: INDEX/PRESET pulse has occurred"] - Xirq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Xirq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `XIRQ` reader - INDEX/PRESET Pulse Interrupt Request"] -pub type XirqR = crate::BitReader; -impl XirqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Xirq { - match self.bits { - false => Xirq::Xirq0, - true => Xirq::Xirq1, - } - } - #[doc = "INDEX/PRESET pulse has not occurred"] - #[inline(always)] - pub fn is_xirq0(&self) -> bool { - *self == Xirq::Xirq0 - } - #[doc = "INDEX/PRESET pulse has occurred"] - #[inline(always)] - pub fn is_xirq1(&self) -> bool { - *self == Xirq::Xirq1 - } -} -#[doc = "Field `XIRQ` writer - INDEX/PRESET Pulse Interrupt Request"] -pub type XirqW<'a, REG> = crate::BitWriter1C<'a, REG, Xirq>; -impl<'a, REG> XirqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "INDEX/PRESET pulse has not occurred"] - #[inline(always)] - pub fn xirq0(self) -> &'a mut crate::W { - self.variant(Xirq::Xirq0) - } - #[doc = "INDEX/PRESET pulse has occurred"] - #[inline(always)] - pub fn xirq1(self) -> &'a mut crate::W { - self.variant(Xirq::Xirq1) - } -} -#[doc = "Enable Single Phase Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ph1 { - #[doc = "0: Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal."] - Ph10 = 0, - #[doc = "1: Single phase mode, bypass the quadrature decoder, refer to CTRL2\\[CMODE\\] description"] - Ph11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ph1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PH1` reader - Enable Single Phase Mode"] -pub type Ph1R = crate::BitReader; -impl Ph1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ph1 { - match self.bits { - false => Ph1::Ph10, - true => Ph1::Ph11, - } - } - #[doc = "Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal."] - #[inline(always)] - pub fn is_ph10(&self) -> bool { - *self == Ph1::Ph10 - } - #[doc = "Single phase mode, bypass the quadrature decoder, refer to CTRL2\\[CMODE\\] description"] - #[inline(always)] - pub fn is_ph11(&self) -> bool { - *self == Ph1::Ph11 - } -} -#[doc = "Field `PH1` writer - Enable Single Phase Mode"] -pub type Ph1W<'a, REG> = crate::BitWriter<'a, REG, Ph1>; -impl<'a, REG> Ph1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal."] - #[inline(always)] - pub fn ph10(self) -> &'a mut crate::W { - self.variant(Ph1::Ph10) - } - #[doc = "Single phase mode, bypass the quadrature decoder, refer to CTRL2\\[CMODE\\] description"] - #[inline(always)] - pub fn ph11(self) -> &'a mut crate::W { - self.variant(Ph1::Ph11) - } -} -#[doc = "Enable Reverse Direction Counting\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rev { - #[doc = "0: Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT"] - Rev0 = 0, - #[doc = "1: Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD"] - Rev1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rev) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REV` reader - Enable Reverse Direction Counting"] -pub type RevR = crate::BitReader; -impl RevR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rev { - match self.bits { - false => Rev::Rev0, - true => Rev::Rev1, - } - } - #[doc = "Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT"] - #[inline(always)] - pub fn is_rev0(&self) -> bool { - *self == Rev::Rev0 - } - #[doc = "Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD"] - #[inline(always)] - pub fn is_rev1(&self) -> bool { - *self == Rev::Rev1 - } -} -#[doc = "Field `REV` writer - Enable Reverse Direction Counting"] -pub type RevW<'a, REG> = crate::BitWriter<'a, REG, Rev>; -impl<'a, REG> RevW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT"] - #[inline(always)] - pub fn rev0(self) -> &'a mut crate::W { - self.variant(Rev::Rev0) - } - #[doc = "Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD"] - #[inline(always)] - pub fn rev1(self) -> &'a mut crate::W { - self.variant(Rev::Rev1) - } -} -#[doc = "Software-Triggered Initialization of Position Counters UPOS and LPOS\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swip { - #[doc = "0: No action"] - Swip0 = 0, - #[doc = "1: Initialize position counter"] - Swip1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swip) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWIP` reader - Software-Triggered Initialization of Position Counters UPOS and LPOS"] -pub type SwipR = crate::BitReader; -impl SwipR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swip { - match self.bits { - false => Swip::Swip0, - true => Swip::Swip1, - } - } - #[doc = "No action"] - #[inline(always)] - pub fn is_swip0(&self) -> bool { - *self == Swip::Swip0 - } - #[doc = "Initialize position counter"] - #[inline(always)] - pub fn is_swip1(&self) -> bool { - *self == Swip::Swip1 - } -} -#[doc = "Field `SWIP` writer - Software-Triggered Initialization of Position Counters UPOS and LPOS"] -pub type SwipW<'a, REG> = crate::BitWriter<'a, REG, Swip>; -impl<'a, REG> SwipW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No action"] - #[inline(always)] - pub fn swip0(self) -> &'a mut crate::W { - self.variant(Swip::Swip0) - } - #[doc = "Initialize position counter"] - #[inline(always)] - pub fn swip1(self) -> &'a mut crate::W { - self.variant(Swip::Swip1) - } -} -#[doc = "Use Negative Edge of HOME/ENABLE Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hne { - #[doc = "0: When CTRL\\[OPMODE\\] = 0,use HOME positive edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters"] - Hne0 = 0, - #[doc = "1: When CTRL\\[OPMODE\\] = 0,use HOME negative edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters"] - Hne1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hne) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HNE` reader - Use Negative Edge of HOME/ENABLE Input"] -pub type HneR = crate::BitReader; -impl HneR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hne { - match self.bits { - false => Hne::Hne0, - true => Hne::Hne1, - } - } - #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME positive edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters"] - #[inline(always)] - pub fn is_hne0(&self) -> bool { - *self == Hne::Hne0 - } - #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME negative edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters"] - #[inline(always)] - pub fn is_hne1(&self) -> bool { - *self == Hne::Hne1 - } -} -#[doc = "Field `HNE` writer - Use Negative Edge of HOME/ENABLE Input"] -pub type HneW<'a, REG> = crate::BitWriter<'a, REG, Hne>; -impl<'a, REG> HneW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME positive edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters"] - #[inline(always)] - pub fn hne0(self) -> &'a mut crate::W { - self.variant(Hne::Hne0) - } - #[doc = "When CTRL\\[OPMODE\\] = 0,use HOME negative edge to trigger initialization of position counters. When CTRL\\[OPMODE\\] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters"] - #[inline(always)] - pub fn hne1(self) -> &'a mut crate::W { - self.variant(Hne::Hne1) - } -} -#[doc = "Enable HOME to Initialize Position Counter UPOS/LPOS\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hip { - #[doc = "0: No action"] - Hip0 = 0, - #[doc = "1: HOME signal initializes the position counter"] - Hip1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hip) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HIP` reader - Enable HOME to Initialize Position Counter UPOS/LPOS"] -pub type HipR = crate::BitReader; -impl HipR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hip { - match self.bits { - false => Hip::Hip0, - true => Hip::Hip1, - } - } - #[doc = "No action"] - #[inline(always)] - pub fn is_hip0(&self) -> bool { - *self == Hip::Hip0 - } - #[doc = "HOME signal initializes the position counter"] - #[inline(always)] - pub fn is_hip1(&self) -> bool { - *self == Hip::Hip1 - } -} -#[doc = "Field `HIP` writer - Enable HOME to Initialize Position Counter UPOS/LPOS"] -pub type HipW<'a, REG> = crate::BitWriter<'a, REG, Hip>; -impl<'a, REG> HipW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No action"] - #[inline(always)] - pub fn hip0(self) -> &'a mut crate::W { - self.variant(Hip::Hip0) - } - #[doc = "HOME signal initializes the position counter"] - #[inline(always)] - pub fn hip1(self) -> &'a mut crate::W { - self.variant(Hip::Hip1) - } -} -#[doc = "HOME/ENABLE Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hie { - #[doc = "0: Disabled"] - Hie0 = 0, - #[doc = "1: Enabled"] - Hie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HIE` reader - HOME/ENABLE Interrupt Enable"] -pub type HieR = crate::BitReader; -impl HieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hie { - match self.bits { - false => Hie::Hie0, - true => Hie::Hie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_hie0(&self) -> bool { - *self == Hie::Hie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_hie1(&self) -> bool { - *self == Hie::Hie1 - } -} -#[doc = "Field `HIE` writer - HOME/ENABLE Interrupt Enable"] -pub type HieW<'a, REG> = crate::BitWriter<'a, REG, Hie>; -impl<'a, REG> HieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn hie0(self) -> &'a mut crate::W { - self.variant(Hie::Hie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn hie1(self) -> &'a mut crate::W { - self.variant(Hie::Hie1) - } -} -#[doc = "HOME/ENABLE Signal Transition Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hirq { - #[doc = "0: No transition on the HOME/ENABLE signal has occurred"] - Hirq0 = 0, - #[doc = "1: A transition on the HOME/ENABLE signal has occurred"] - Hirq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hirq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HIRQ` reader - HOME/ENABLE Signal Transition Interrupt Request"] -pub type HirqR = crate::BitReader; -impl HirqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hirq { - match self.bits { - false => Hirq::Hirq0, - true => Hirq::Hirq1, - } - } - #[doc = "No transition on the HOME/ENABLE signal has occurred"] - #[inline(always)] - pub fn is_hirq0(&self) -> bool { - *self == Hirq::Hirq0 - } - #[doc = "A transition on the HOME/ENABLE signal has occurred"] - #[inline(always)] - pub fn is_hirq1(&self) -> bool { - *self == Hirq::Hirq1 - } -} -#[doc = "Field `HIRQ` writer - HOME/ENABLE Signal Transition Interrupt Request"] -pub type HirqW<'a, REG> = crate::BitWriter1C<'a, REG, Hirq>; -impl<'a, REG> HirqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No transition on the HOME/ENABLE signal has occurred"] - #[inline(always)] - pub fn hirq0(self) -> &'a mut crate::W { - self.variant(Hirq::Hirq0) - } - #[doc = "A transition on the HOME/ENABLE signal has occurred"] - #[inline(always)] - pub fn hirq1(self) -> &'a mut crate::W { - self.variant(Hirq::Hirq1) - } -} -impl R { - #[doc = "Bit 0 - Load Okay"] - #[inline(always)] - pub fn ldok(&self) -> LdokR { - LdokR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - DMA Enable"] - #[inline(always)] - pub fn dmaen(&self) -> DmaenR { - DmaenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Watchdog Enable"] - #[inline(always)] - pub fn wde(&self) -> WdeR { - WdeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Watchdog Timeout Interrupt Enable"] - #[inline(always)] - pub fn wdie(&self) -> WdieR { - WdieR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Watchdog Timeout Interrupt Request"] - #[inline(always)] - pub fn wdirq(&self) -> WdirqR { - WdirqR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Select Positive/Negative Edge of INDEX/PRESET Pulse"] - #[inline(always)] - pub fn xne(&self) -> XneR { - XneR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] - #[inline(always)] - pub fn xip(&self) -> XipR { - XipR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - INDEX/PRESET Pulse Interrupt Enable"] - #[inline(always)] - pub fn xie(&self) -> XieR { - XieR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - INDEX/PRESET Pulse Interrupt Request"] - #[inline(always)] - pub fn xirq(&self) -> XirqR { - XirqR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Enable Single Phase Mode"] - #[inline(always)] - pub fn ph1(&self) -> Ph1R { - Ph1R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Enable Reverse Direction Counting"] - #[inline(always)] - pub fn rev(&self) -> RevR { - RevR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Software-Triggered Initialization of Position Counters UPOS and LPOS"] - #[inline(always)] - pub fn swip(&self) -> SwipR { - SwipR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Use Negative Edge of HOME/ENABLE Input"] - #[inline(always)] - pub fn hne(&self) -> HneR { - HneR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Enable HOME to Initialize Position Counter UPOS/LPOS"] - #[inline(always)] - pub fn hip(&self) -> HipR { - HipR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - HOME/ENABLE Interrupt Enable"] - #[inline(always)] - pub fn hie(&self) -> HieR { - HieR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - HOME/ENABLE Signal Transition Interrupt Request"] - #[inline(always)] - pub fn hirq(&self) -> HirqR { - HirqR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Load Okay"] - #[inline(always)] - pub fn ldok(&mut self) -> LdokW { - LdokW::new(self, 0) - } - #[doc = "Bit 1 - DMA Enable"] - #[inline(always)] - pub fn dmaen(&mut self) -> DmaenW { - DmaenW::new(self, 1) - } - #[doc = "Bit 2 - Watchdog Enable"] - #[inline(always)] - pub fn wde(&mut self) -> WdeW { - WdeW::new(self, 2) - } - #[doc = "Bit 3 - Watchdog Timeout Interrupt Enable"] - #[inline(always)] - pub fn wdie(&mut self) -> WdieW { - WdieW::new(self, 3) - } - #[doc = "Bit 4 - Watchdog Timeout Interrupt Request"] - #[inline(always)] - pub fn wdirq(&mut self) -> WdirqW { - WdirqW::new(self, 4) - } - #[doc = "Bit 5 - Select Positive/Negative Edge of INDEX/PRESET Pulse"] - #[inline(always)] - pub fn xne(&mut self) -> XneW { - XneW::new(self, 5) - } - #[doc = "Bit 6 - INDEX Triggered Initialization of Position Counters UPOS and LPOS"] - #[inline(always)] - pub fn xip(&mut self) -> XipW { - XipW::new(self, 6) - } - #[doc = "Bit 7 - INDEX/PRESET Pulse Interrupt Enable"] - #[inline(always)] - pub fn xie(&mut self) -> XieW { - XieW::new(self, 7) - } - #[doc = "Bit 8 - INDEX/PRESET Pulse Interrupt Request"] - #[inline(always)] - pub fn xirq(&mut self) -> XirqW { - XirqW::new(self, 8) - } - #[doc = "Bit 9 - Enable Single Phase Mode"] - #[inline(always)] - pub fn ph1(&mut self) -> Ph1W { - Ph1W::new(self, 9) - } - #[doc = "Bit 10 - Enable Reverse Direction Counting"] - #[inline(always)] - pub fn rev(&mut self) -> RevW { - RevW::new(self, 10) - } - #[doc = "Bit 11 - Software-Triggered Initialization of Position Counters UPOS and LPOS"] - #[inline(always)] - pub fn swip(&mut self) -> SwipW { - SwipW::new(self, 11) - } - #[doc = "Bit 12 - Use Negative Edge of HOME/ENABLE Input"] - #[inline(always)] - pub fn hne(&mut self) -> HneW { - HneW::new(self, 12) - } - #[doc = "Bit 13 - Enable HOME to Initialize Position Counter UPOS/LPOS"] - #[inline(always)] - pub fn hip(&mut self) -> HipW { - HipW::new(self, 13) - } - #[doc = "Bit 14 - HOME/ENABLE Interrupt Enable"] - #[inline(always)] - pub fn hie(&mut self) -> HieW { - HieW::new(self, 14) - } - #[doc = "Bit 15 - HOME/ENABLE Signal Transition Interrupt Request"] - #[inline(always)] - pub fn hirq(&mut self) -> HirqW { - HirqW::new(self, 15) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x8110; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/eqdc0/ctrl2.rs b/mcxa276-pac/src/eqdc0/ctrl2.rs deleted file mode 100644 index d8f6394bd..000000000 --- a/mcxa276-pac/src/eqdc0/ctrl2.rs +++ /dev/null @@ -1,567 +0,0 @@ -#[doc = "Register `CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL2` writer"] -pub type W = crate::W; -#[doc = "Field `UPDHLD` reader - Update Hold Registers"] -pub type UpdhldR = crate::BitReader; -#[doc = "Field `UPDHLD` writer - Update Hold Registers"] -pub type UpdhldW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UPDPOS` reader - Update Position Registers"] -pub type UpdposR = crate::BitReader; -#[doc = "Field `UPDPOS` writer - Update Position Registers"] -pub type UpdposW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Operation Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opmode { - #[doc = "0: Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."] - Opmode0 = 0, - #[doc = "1: Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."] - Opmode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opmode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPMODE` reader - Operation Mode Select"] -pub type OpmodeR = crate::BitReader; -impl OpmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opmode { - match self.bits { - false => Opmode::Opmode0, - true => Opmode::Opmode1, - } - } - #[doc = "Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."] - #[inline(always)] - pub fn is_opmode0(&self) -> bool { - *self == Opmode::Opmode0 - } - #[doc = "Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."] - #[inline(always)] - pub fn is_opmode1(&self) -> bool { - *self == Opmode::Opmode1 - } -} -#[doc = "Field `OPMODE` writer - Operation Mode Select"] -pub type OpmodeW<'a, REG> = crate::BitWriter<'a, REG, Opmode>; -impl<'a, REG> OpmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME."] - #[inline(always)] - pub fn opmode0(self) -> &'a mut crate::W { - self.variant(Opmode::Opmode0) - } - #[doc = "Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization also need referring to bit CTRL\\[REV\\])."] - #[inline(always)] - pub fn opmode1(self) -> &'a mut crate::W { - self.variant(Opmode::Opmode1) - } -} -#[doc = "Buffered Register Load (Update) Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldmod { - #[doc = "0: Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."] - Ldmod0 = 0, - #[doc = "1: Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."] - Ldmod1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldmod) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDMOD` reader - Buffered Register Load (Update) Mode Select"] -pub type LdmodR = crate::BitReader; -impl LdmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldmod { - match self.bits { - false => Ldmod::Ldmod0, - true => Ldmod::Ldmod1, - } - } - #[doc = "Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn is_ldmod0(&self) -> bool { - *self == Ldmod::Ldmod0 - } - #[doc = "Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn is_ldmod1(&self) -> bool { - *self == Ldmod::Ldmod1 - } -} -#[doc = "Field `LDMOD` writer - Buffered Register Load (Update) Mode Select"] -pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; -impl<'a, REG> LdmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Buffered registers are loaded and take effect immediately upon CTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn ldmod0(self) -> &'a mut crate::W { - self.variant(Ldmod::Ldmod0) - } - #[doc = "Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn ldmod1(self) -> &'a mut crate::W { - self.variant(Ldmod::Ldmod1) - } -} -#[doc = "Revolution Counter Modulus Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Revmod { - #[doc = "0: Use INDEX pulse to increment/decrement revolution counter (REV)"] - Revmod0 = 0, - #[doc = "1: Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"] - Revmod1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Revmod) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REVMOD` reader - Revolution Counter Modulus Enable"] -pub type RevmodR = crate::BitReader; -impl RevmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Revmod { - match self.bits { - false => Revmod::Revmod0, - true => Revmod::Revmod1, - } - } - #[doc = "Use INDEX pulse to increment/decrement revolution counter (REV)"] - #[inline(always)] - pub fn is_revmod0(&self) -> bool { - *self == Revmod::Revmod0 - } - #[doc = "Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"] - #[inline(always)] - pub fn is_revmod1(&self) -> bool { - *self == Revmod::Revmod1 - } -} -#[doc = "Field `REVMOD` writer - Revolution Counter Modulus Enable"] -pub type RevmodW<'a, REG> = crate::BitWriter<'a, REG, Revmod>; -impl<'a, REG> RevmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Use INDEX pulse to increment/decrement revolution counter (REV)"] - #[inline(always)] - pub fn revmod0(self) -> &'a mut crate::W { - self.variant(Revmod::Revmod0) - } - #[doc = "Use modulus counting roll-over/under to increment/decrement revolution counter (REV)"] - #[inline(always)] - pub fn revmod1(self) -> &'a mut crate::W { - self.variant(Revmod::Revmod1) - } -} -#[doc = "Output Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Outctl { - #[doc = "0: POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"] - Outctl0 = 0, - #[doc = "1: All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"] - Outctl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Outctl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OUTCTL` reader - Output Control"] -pub type OutctlR = crate::BitReader; -impl OutctlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Outctl { - match self.bits { - false => Outctl::Outctl0, - true => Outctl::Outctl1, - } - } - #[doc = "POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"] - #[inline(always)] - pub fn is_outctl0(&self) -> bool { - *self == Outctl::Outctl0 - } - #[doc = "All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"] - #[inline(always)] - pub fn is_outctl1(&self) -> bool { - *self == Outctl::Outctl1 - } -} -#[doc = "Field `OUTCTL` writer - Output Control"] -pub type OutctlW<'a, REG> = crate::BitWriter<'a, REG, Outctl>; -impl<'a, REG> OutctlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "POS_MATCH\\[x\\](x range is 0-3) is asserted when the Position Counter is equal to according compare value (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value (UCOMPx/LCOMPx)(x range is 0-3)"] - #[inline(always)] - pub fn outctl0(self) -> &'a mut crate::W { - self.variant(Outctl::Outctl0) - } - #[doc = "All POS_MATCH\\[x\\](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read"] - #[inline(always)] - pub fn outctl1(self) -> &'a mut crate::W { - self.variant(Outctl::Outctl1) - } -} -#[doc = "Period measurement function enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pmen { - #[doc = "0: Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."] - Pmen0 = 0, - #[doc = "1: Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."] - Pmen1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pmen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PMEN` reader - Period measurement function enable"] -pub type PmenR = crate::BitReader; -impl PmenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pmen { - match self.bits { - false => Pmen::Pmen0, - true => Pmen::Pmen1, - } - } - #[doc = "Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."] - #[inline(always)] - pub fn is_pmen0(&self) -> bool { - *self == Pmen::Pmen0 - } - #[doc = "Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."] - #[inline(always)] - pub fn is_pmen1(&self) -> bool { - *self == Pmen::Pmen1 - } -} -#[doc = "Field `PMEN` writer - Period measurement function enable"] -pub type PmenW<'a, REG> = crate::BitWriter<'a, REG, Pmen>; -impl<'a, REG> PmenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read."] - #[inline(always)] - pub fn pmen0(self) -> &'a mut crate::W { - self.variant(Pmen::Pmen0) - } - #[doc = "Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read."] - #[inline(always)] - pub fn pmen1(self) -> &'a mut crate::W { - self.variant(Pmen::Pmen1) - } -} -#[doc = "Enables/disables the position counter to be initialized by Index Event Edge Mark\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Emip { - #[doc = "0: disables the position counter to be initialized by Index Event Edge Mark"] - Emip0 = 0, - #[doc = "1: enables the position counter to be initialized by Index Event Edge Mark."] - Emip1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Emip) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EMIP` reader - Enables/disables the position counter to be initialized by Index Event Edge Mark"] -pub type EmipR = crate::BitReader; -impl EmipR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Emip { - match self.bits { - false => Emip::Emip0, - true => Emip::Emip1, - } - } - #[doc = "disables the position counter to be initialized by Index Event Edge Mark"] - #[inline(always)] - pub fn is_emip0(&self) -> bool { - *self == Emip::Emip0 - } - #[doc = "enables the position counter to be initialized by Index Event Edge Mark."] - #[inline(always)] - pub fn is_emip1(&self) -> bool { - *self == Emip::Emip1 - } -} -#[doc = "Field `EMIP` writer - Enables/disables the position counter to be initialized by Index Event Edge Mark"] -pub type EmipW<'a, REG> = crate::BitWriter<'a, REG, Emip>; -impl<'a, REG> EmipW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "disables the position counter to be initialized by Index Event Edge Mark"] - #[inline(always)] - pub fn emip0(self) -> &'a mut crate::W { - self.variant(Emip::Emip0) - } - #[doc = "enables the position counter to be initialized by Index Event Edge Mark."] - #[inline(always)] - pub fn emip1(self) -> &'a mut crate::W { - self.variant(Emip::Emip1) - } -} -#[doc = "Initial Position Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Initpos { - #[doc = "0: Don't initialize position counter on rising edge of TRIGGER"] - Initpos0 = 0, - #[doc = "1: Initialize position counter on rising edge of TRIGGER"] - Initpos1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Initpos) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INITPOS` reader - Initial Position Register"] -pub type InitposR = crate::BitReader; -impl InitposR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Initpos { - match self.bits { - false => Initpos::Initpos0, - true => Initpos::Initpos1, - } - } - #[doc = "Don't initialize position counter on rising edge of TRIGGER"] - #[inline(always)] - pub fn is_initpos0(&self) -> bool { - *self == Initpos::Initpos0 - } - #[doc = "Initialize position counter on rising edge of TRIGGER"] - #[inline(always)] - pub fn is_initpos1(&self) -> bool { - *self == Initpos::Initpos1 - } -} -#[doc = "Field `INITPOS` writer - Initial Position Register"] -pub type InitposW<'a, REG> = crate::BitWriter<'a, REG, Initpos>; -impl<'a, REG> InitposW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Don't initialize position counter on rising edge of TRIGGER"] - #[inline(always)] - pub fn initpos0(self) -> &'a mut crate::W { - self.variant(Initpos::Initpos0) - } - #[doc = "Initialize position counter on rising edge of TRIGGER"] - #[inline(always)] - pub fn initpos1(self) -> &'a mut crate::W { - self.variant(Initpos::Initpos1) - } -} -#[doc = "Count Once\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Once { - #[doc = "0: Position counter counts repeatedly"] - Once0 = 0, - #[doc = "1: Position counter counts until roll-over or roll-under, then stop."] - Once1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Once) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONCE` reader - Count Once"] -pub type OnceR = crate::BitReader; -impl OnceR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Once { - match self.bits { - false => Once::Once0, - true => Once::Once1, - } - } - #[doc = "Position counter counts repeatedly"] - #[inline(always)] - pub fn is_once0(&self) -> bool { - *self == Once::Once0 - } - #[doc = "Position counter counts until roll-over or roll-under, then stop."] - #[inline(always)] - pub fn is_once1(&self) -> bool { - *self == Once::Once1 - } -} -#[doc = "Field `ONCE` writer - Count Once"] -pub type OnceW<'a, REG> = crate::BitWriter<'a, REG, Once>; -impl<'a, REG> OnceW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Position counter counts repeatedly"] - #[inline(always)] - pub fn once0(self) -> &'a mut crate::W { - self.variant(Once::Once0) - } - #[doc = "Position counter counts until roll-over or roll-under, then stop."] - #[inline(always)] - pub fn once1(self) -> &'a mut crate::W { - self.variant(Once::Once1) - } -} -#[doc = "Field `CMODE` reader - Counting Mode"] -pub type CmodeR = crate::FieldReader; -#[doc = "Field `CMODE` writer - Counting Mode"] -pub type CmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bit 0 - Update Hold Registers"] - #[inline(always)] - pub fn updhld(&self) -> UpdhldR { - UpdhldR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Update Position Registers"] - #[inline(always)] - pub fn updpos(&self) -> UpdposR { - UpdposR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Operation Mode Select"] - #[inline(always)] - pub fn opmode(&self) -> OpmodeR { - OpmodeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Buffered Register Load (Update) Mode Select"] - #[inline(always)] - pub fn ldmod(&self) -> LdmodR { - LdmodR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Revolution Counter Modulus Enable"] - #[inline(always)] - pub fn revmod(&self) -> RevmodR { - RevmodR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Output Control"] - #[inline(always)] - pub fn outctl(&self) -> OutctlR { - OutctlR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Period measurement function enable"] - #[inline(always)] - pub fn pmen(&self) -> PmenR { - PmenR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Enables/disables the position counter to be initialized by Index Event Edge Mark"] - #[inline(always)] - pub fn emip(&self) -> EmipR { - EmipR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Initial Position Register"] - #[inline(always)] - pub fn initpos(&self) -> InitposR { - InitposR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Count Once"] - #[inline(always)] - pub fn once(&self) -> OnceR { - OnceR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bits 14:15 - Counting Mode"] - #[inline(always)] - pub fn cmode(&self) -> CmodeR { - CmodeR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bit 0 - Update Hold Registers"] - #[inline(always)] - pub fn updhld(&mut self) -> UpdhldW { - UpdhldW::new(self, 0) - } - #[doc = "Bit 1 - Update Position Registers"] - #[inline(always)] - pub fn updpos(&mut self) -> UpdposW { - UpdposW::new(self, 1) - } - #[doc = "Bit 2 - Operation Mode Select"] - #[inline(always)] - pub fn opmode(&mut self) -> OpmodeW { - OpmodeW::new(self, 2) - } - #[doc = "Bit 3 - Buffered Register Load (Update) Mode Select"] - #[inline(always)] - pub fn ldmod(&mut self) -> LdmodW { - LdmodW::new(self, 3) - } - #[doc = "Bit 8 - Revolution Counter Modulus Enable"] - #[inline(always)] - pub fn revmod(&mut self) -> RevmodW { - RevmodW::new(self, 8) - } - #[doc = "Bit 9 - Output Control"] - #[inline(always)] - pub fn outctl(&mut self) -> OutctlW { - OutctlW::new(self, 9) - } - #[doc = "Bit 10 - Period measurement function enable"] - #[inline(always)] - pub fn pmen(&mut self) -> PmenW { - PmenW::new(self, 10) - } - #[doc = "Bit 11 - Enables/disables the position counter to be initialized by Index Event Edge Mark"] - #[inline(always)] - pub fn emip(&mut self) -> EmipW { - EmipW::new(self, 11) - } - #[doc = "Bit 12 - Initial Position Register"] - #[inline(always)] - pub fn initpos(&mut self) -> InitposW { - InitposW::new(self, 12) - } - #[doc = "Bit 13 - Count Once"] - #[inline(always)] - pub fn once(&mut self) -> OnceW { - OnceW::new(self, 13) - } - #[doc = "Bits 14:15 - Counting Mode"] - #[inline(always)] - pub fn cmode(&mut self) -> CmodeW { - CmodeW::new(self, 14) - } -} -#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctrl2Spec; -impl crate::RegisterSpec for Ctrl2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"] -impl crate::Readable for Ctrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"] -impl crate::Writable for Ctrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL2 to value 0"] -impl crate::Resettable for Ctrl2Spec {} diff --git a/mcxa276-pac/src/eqdc0/filt.rs b/mcxa276-pac/src/eqdc0/filt.rs deleted file mode 100644 index dc4b6dc7b..000000000 --- a/mcxa276-pac/src/eqdc0/filt.rs +++ /dev/null @@ -1,126 +0,0 @@ -#[doc = "Register `FILT` reader"] -pub type R = crate::R; -#[doc = "Register `FILT` writer"] -pub type W = crate::W; -#[doc = "Field `FILT_PER` reader - Input Filter Sample Period"] -pub type FiltPerR = crate::FieldReader; -#[doc = "Field `FILT_PER` writer - Input Filter Sample Period"] -pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `FILT_CNT` reader - Input Filter Sample Count"] -pub type FiltCntR = crate::FieldReader; -#[doc = "Field `FILT_CNT` writer - Input Filter Sample Count"] -pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Filter Clock Source selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FiltCs { - #[doc = "0: Peripheral Clock"] - FiltCs0 = 0, - #[doc = "1: Prescaled peripheral clock by PRSC"] - FiltCs1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FiltCs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILT_CS` reader - Filter Clock Source selection"] -pub type FiltCsR = crate::BitReader; -impl FiltCsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FiltCs { - match self.bits { - false => FiltCs::FiltCs0, - true => FiltCs::FiltCs1, - } - } - #[doc = "Peripheral Clock"] - #[inline(always)] - pub fn is_filt_cs0(&self) -> bool { - *self == FiltCs::FiltCs0 - } - #[doc = "Prescaled peripheral clock by PRSC"] - #[inline(always)] - pub fn is_filt_cs1(&self) -> bool { - *self == FiltCs::FiltCs1 - } -} -#[doc = "Field `FILT_CS` writer - Filter Clock Source selection"] -pub type FiltCsW<'a, REG> = crate::BitWriter<'a, REG, FiltCs>; -impl<'a, REG> FiltCsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral Clock"] - #[inline(always)] - pub fn filt_cs0(self) -> &'a mut crate::W { - self.variant(FiltCs::FiltCs0) - } - #[doc = "Prescaled peripheral clock by PRSC"] - #[inline(always)] - pub fn filt_cs1(self) -> &'a mut crate::W { - self.variant(FiltCs::FiltCs1) - } -} -#[doc = "Field `PRSC` reader - Prescaler"] -pub type PrscR = crate::FieldReader; -#[doc = "Field `PRSC` writer - Prescaler"] -pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:7 - Input Filter Sample Period"] - #[inline(always)] - pub fn filt_per(&self) -> FiltPerR { - FiltPerR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Input Filter Sample Count"] - #[inline(always)] - pub fn filt_cnt(&self) -> FiltCntR { - FiltCntR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - Filter Clock Source selection"] - #[inline(always)] - pub fn filt_cs(&self) -> FiltCsR { - FiltCsR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15 - Prescaler"] - #[inline(always)] - pub fn prsc(&self) -> PrscR { - PrscR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Input Filter Sample Period"] - #[inline(always)] - pub fn filt_per(&mut self) -> FiltPerW { - FiltPerW::new(self, 0) - } - #[doc = "Bits 8:10 - Input Filter Sample Count"] - #[inline(always)] - pub fn filt_cnt(&mut self) -> FiltCntW { - FiltCntW::new(self, 8) - } - #[doc = "Bit 11 - Filter Clock Source selection"] - #[inline(always)] - pub fn filt_cs(&mut self) -> FiltCsW { - FiltCsW::new(self, 11) - } - #[doc = "Bits 12:15 - Prescaler"] - #[inline(always)] - pub fn prsc(&mut self) -> PrscW { - PrscW::new(self, 12) - } -} -#[doc = "Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FiltSpec; -impl crate::RegisterSpec for FiltSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`filt::R`](R) reader structure"] -impl crate::Readable for FiltSpec {} -#[doc = "`write(|w| ..)` method takes [`filt::W`](W) writer structure"] -impl crate::Writable for FiltSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FILT to value 0"] -impl crate::Resettable for FiltSpec {} diff --git a/mcxa276-pac/src/eqdc0/imr.rs b/mcxa276-pac/src/eqdc0/imr.rs deleted file mode 100644 index ed46ea7b4..000000000 --- a/mcxa276-pac/src/eqdc0/imr.rs +++ /dev/null @@ -1,317 +0,0 @@ -#[doc = "Register `IMR` reader"] -pub type R = crate::R; -#[doc = "Register `IMR` writer"] -pub type W = crate::W; -#[doc = "Field `HOME_ENABLE` reader - HOME_ENABLE"] -pub type HomeEnableR = crate::BitReader; -#[doc = "Field `INDEX_PRESET` reader - INDEX_PRESET"] -pub type IndexPresetR = crate::BitReader; -#[doc = "Field `PHB` reader - PHB"] -pub type PhbR = crate::BitReader; -#[doc = "Field `PHA` reader - PHA"] -pub type PhaR = crate::BitReader; -#[doc = "Field `FHOM_ENA` reader - filter operation on HOME/ENABLE input"] -pub type FhomEnaR = crate::BitReader; -#[doc = "Field `FHOM_ENA` writer - filter operation on HOME/ENABLE input"] -pub type FhomEnaW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FIND_PRE` reader - filter operation on INDEX/PRESET input"] -pub type FindPreR = crate::BitReader; -#[doc = "Field `FIND_PRE` writer - filter operation on INDEX/PRESET input"] -pub type FindPreW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FPHB` reader - filter operation on PHASEB input"] -pub type FphbR = crate::BitReader; -#[doc = "Field `FPHB` writer - filter operation on PHASEB input"] -pub type FphbW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FPHA` reader - filter operation on PHASEA input"] -pub type FphaR = crate::BitReader; -#[doc = "Field `FPHA` writer - filter operation on PHASEA input"] -pub type FphaW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Position Compare 0 Flag Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmpf0 { - #[doc = "0: When the position counter is less than value of COMP0 register"] - Cmpf00 = 0, - #[doc = "1: When the position counter is greater or equal than value of COMP0 register"] - Cmpf01 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmpf0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMPF0` reader - Position Compare 0 Flag Output"] -pub type Cmpf0R = crate::BitReader; -impl Cmpf0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmpf0 { - match self.bits { - false => Cmpf0::Cmpf00, - true => Cmpf0::Cmpf01, - } - } - #[doc = "When the position counter is less than value of COMP0 register"] - #[inline(always)] - pub fn is_cmpf00(&self) -> bool { - *self == Cmpf0::Cmpf00 - } - #[doc = "When the position counter is greater or equal than value of COMP0 register"] - #[inline(always)] - pub fn is_cmpf01(&self) -> bool { - *self == Cmpf0::Cmpf01 - } -} -#[doc = "Position Compare1 Flag Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp1f { - #[doc = "0: When the position counter is less than value of COMP1 register"] - Cmp1f0 = 0, - #[doc = "1: When the position counter is greater or equal than value of COMP1 register"] - Cmp1f1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp1f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP1F` reader - Position Compare1 Flag Output"] -pub type Cmp1fR = crate::BitReader; -impl Cmp1fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp1f { - match self.bits { - false => Cmp1f::Cmp1f0, - true => Cmp1f::Cmp1f1, - } - } - #[doc = "When the position counter is less than value of COMP1 register"] - #[inline(always)] - pub fn is_cmp1f0(&self) -> bool { - *self == Cmp1f::Cmp1f0 - } - #[doc = "When the position counter is greater or equal than value of COMP1 register"] - #[inline(always)] - pub fn is_cmp1f1(&self) -> bool { - *self == Cmp1f::Cmp1f1 - } -} -#[doc = "Position Compare2 Flag Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp2f { - #[doc = "0: When the position counter is less than value of COMP2 register"] - Cmp2f0 = 0, - #[doc = "1: When the position counter is greater or equal than value of COMP2 register"] - Cmp2f1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp2f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP2F` reader - Position Compare2 Flag Output"] -pub type Cmp2fR = crate::BitReader; -impl Cmp2fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp2f { - match self.bits { - false => Cmp2f::Cmp2f0, - true => Cmp2f::Cmp2f1, - } - } - #[doc = "When the position counter is less than value of COMP2 register"] - #[inline(always)] - pub fn is_cmp2f0(&self) -> bool { - *self == Cmp2f::Cmp2f0 - } - #[doc = "When the position counter is greater or equal than value of COMP2 register"] - #[inline(always)] - pub fn is_cmp2f1(&self) -> bool { - *self == Cmp2f::Cmp2f1 - } -} -#[doc = "Position Compare3 Flag Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp3f { - #[doc = "0: When the position counter value is less than value of COMP3 register"] - Cmp3f0 = 0, - #[doc = "1: When the position counter is greater or equal than value of COMP3 register"] - Cmp3f1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp3f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP3F` reader - Position Compare3 Flag Output"] -pub type Cmp3fR = crate::BitReader; -impl Cmp3fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp3f { - match self.bits { - false => Cmp3f::Cmp3f0, - true => Cmp3f::Cmp3f1, - } - } - #[doc = "When the position counter value is less than value of COMP3 register"] - #[inline(always)] - pub fn is_cmp3f0(&self) -> bool { - *self == Cmp3f::Cmp3f0 - } - #[doc = "When the position counter is greater or equal than value of COMP3 register"] - #[inline(always)] - pub fn is_cmp3f1(&self) -> bool { - *self == Cmp3f::Cmp3f1 - } -} -#[doc = "Field `DIRH` reader - Count Direction Flag Hold"] -pub type DirhR = crate::BitReader; -#[doc = "Count Direction Flag Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dir { - #[doc = "0: Current count was in the down direction"] - Dir0 = 0, - #[doc = "1: Current count was in the up direction"] - Dir1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dir) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIR` reader - Count Direction Flag Output"] -pub type DirR = crate::BitReader; -impl DirR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dir { - match self.bits { - false => Dir::Dir0, - true => Dir::Dir1, - } - } - #[doc = "Current count was in the down direction"] - #[inline(always)] - pub fn is_dir0(&self) -> bool { - *self == Dir::Dir0 - } - #[doc = "Current count was in the up direction"] - #[inline(always)] - pub fn is_dir1(&self) -> bool { - *self == Dir::Dir1 - } -} -impl R { - #[doc = "Bit 0 - HOME_ENABLE"] - #[inline(always)] - pub fn home_enable(&self) -> HomeEnableR { - HomeEnableR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - INDEX_PRESET"] - #[inline(always)] - pub fn index_preset(&self) -> IndexPresetR { - IndexPresetR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - PHB"] - #[inline(always)] - pub fn phb(&self) -> PhbR { - PhbR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - PHA"] - #[inline(always)] - pub fn pha(&self) -> PhaR { - PhaR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - filter operation on HOME/ENABLE input"] - #[inline(always)] - pub fn fhom_ena(&self) -> FhomEnaR { - FhomEnaR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - filter operation on INDEX/PRESET input"] - #[inline(always)] - pub fn find_pre(&self) -> FindPreR { - FindPreR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - filter operation on PHASEB input"] - #[inline(always)] - pub fn fphb(&self) -> FphbR { - FphbR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - filter operation on PHASEA input"] - #[inline(always)] - pub fn fpha(&self) -> FphaR { - FphaR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Position Compare 0 Flag Output"] - #[inline(always)] - pub fn cmpf0(&self) -> Cmpf0R { - Cmpf0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Position Compare1 Flag Output"] - #[inline(always)] - pub fn cmp1f(&self) -> Cmp1fR { - Cmp1fR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Position Compare2 Flag Output"] - #[inline(always)] - pub fn cmp2f(&self) -> Cmp2fR { - Cmp2fR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Position Compare3 Flag Output"] - #[inline(always)] - pub fn cmp3f(&self) -> Cmp3fR { - Cmp3fR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 14 - Count Direction Flag Hold"] - #[inline(always)] - pub fn dirh(&self) -> DirhR { - DirhR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Count Direction Flag Output"] - #[inline(always)] - pub fn dir(&self) -> DirR { - DirR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 4 - filter operation on HOME/ENABLE input"] - #[inline(always)] - pub fn fhom_ena(&mut self) -> FhomEnaW { - FhomEnaW::new(self, 4) - } - #[doc = "Bit 5 - filter operation on INDEX/PRESET input"] - #[inline(always)] - pub fn find_pre(&mut self) -> FindPreW { - FindPreW::new(self, 5) - } - #[doc = "Bit 6 - filter operation on PHASEB input"] - #[inline(always)] - pub fn fphb(&mut self) -> FphbW { - FphbW::new(self, 6) - } - #[doc = "Bit 7 - filter operation on PHASEA input"] - #[inline(always)] - pub fn fpha(&mut self) -> FphaW { - FphaW::new(self, 7) - } -} -#[doc = "Input Monitor Register\n\nYou can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ImrSpec; -impl crate::RegisterSpec for ImrSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`imr::R`](R) reader structure"] -impl crate::Readable for ImrSpec {} -#[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"] -impl crate::Writable for ImrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IMR to value 0"] -impl crate::Resettable for ImrSpec {} diff --git a/mcxa276-pac/src/eqdc0/intctrl.rs b/mcxa276-pac/src/eqdc0/intctrl.rs deleted file mode 100644 index 037853cc2..000000000 --- a/mcxa276-pac/src/eqdc0/intctrl.rs +++ /dev/null @@ -1,1030 +0,0 @@ -#[doc = "Register `INTCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `INTCTRL` writer"] -pub type W = crate::W; -#[doc = "Simultaneous PHASEA and PHASEB Change Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sabie { - #[doc = "0: Disabled"] - Sabie0 = 0, - #[doc = "1: Enabled"] - Sabie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sabie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SABIE` reader - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] -pub type SabieR = crate::BitReader; -impl SabieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sabie { - match self.bits { - false => Sabie::Sabie0, - true => Sabie::Sabie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_sabie0(&self) -> bool { - *self == Sabie::Sabie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_sabie1(&self) -> bool { - *self == Sabie::Sabie1 - } -} -#[doc = "Field `SABIE` writer - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] -pub type SabieW<'a, REG> = crate::BitWriter<'a, REG, Sabie>; -impl<'a, REG> SabieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn sabie0(self) -> &'a mut crate::W { - self.variant(Sabie::Sabie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn sabie1(self) -> &'a mut crate::W { - self.variant(Sabie::Sabie1) - } -} -#[doc = "Simultaneous PHASEA and PHASEB Change Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sabirq { - #[doc = "0: No simultaneous change of PHASEA and PHASEB has occurred"] - Sabirq0 = 0, - #[doc = "1: A simultaneous change of PHASEA and PHASEB has occurred"] - Sabirq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sabirq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SABIRQ` reader - Simultaneous PHASEA and PHASEB Change Interrupt Request"] -pub type SabirqR = crate::BitReader; -impl SabirqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sabirq { - match self.bits { - false => Sabirq::Sabirq0, - true => Sabirq::Sabirq1, - } - } - #[doc = "No simultaneous change of PHASEA and PHASEB has occurred"] - #[inline(always)] - pub fn is_sabirq0(&self) -> bool { - *self == Sabirq::Sabirq0 - } - #[doc = "A simultaneous change of PHASEA and PHASEB has occurred"] - #[inline(always)] - pub fn is_sabirq1(&self) -> bool { - *self == Sabirq::Sabirq1 - } -} -#[doc = "Field `SABIRQ` writer - Simultaneous PHASEA and PHASEB Change Interrupt Request"] -pub type SabirqW<'a, REG> = crate::BitWriter1C<'a, REG, Sabirq>; -impl<'a, REG> SabirqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No simultaneous change of PHASEA and PHASEB has occurred"] - #[inline(always)] - pub fn sabirq0(self) -> &'a mut crate::W { - self.variant(Sabirq::Sabirq0) - } - #[doc = "A simultaneous change of PHASEA and PHASEB has occurred"] - #[inline(always)] - pub fn sabirq1(self) -> &'a mut crate::W { - self.variant(Sabirq::Sabirq1) - } -} -#[doc = "Count direction change interrupt enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dirie { - #[doc = "0: Disabled"] - Dirie0 = 0, - #[doc = "1: Enabled"] - Dirie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dirie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIRIE` reader - Count direction change interrupt enable"] -pub type DirieR = crate::BitReader; -impl DirieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dirie { - match self.bits { - false => Dirie::Dirie0, - true => Dirie::Dirie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_dirie0(&self) -> bool { - *self == Dirie::Dirie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_dirie1(&self) -> bool { - *self == Dirie::Dirie1 - } -} -#[doc = "Field `DIRIE` writer - Count direction change interrupt enable"] -pub type DirieW<'a, REG> = crate::BitWriter<'a, REG, Dirie>; -impl<'a, REG> DirieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn dirie0(self) -> &'a mut crate::W { - self.variant(Dirie::Dirie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn dirie1(self) -> &'a mut crate::W { - self.variant(Dirie::Dirie1) - } -} -#[doc = "Count direction change interrupt\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dirirq { - #[doc = "0: Count direction unchanged"] - Dirirq0 = 0, - #[doc = "1: Count direction changed"] - Dirirq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dirirq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIRIRQ` reader - Count direction change interrupt"] -pub type DirirqR = crate::BitReader; -impl DirirqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dirirq { - match self.bits { - false => Dirirq::Dirirq0, - true => Dirirq::Dirirq1, - } - } - #[doc = "Count direction unchanged"] - #[inline(always)] - pub fn is_dirirq0(&self) -> bool { - *self == Dirirq::Dirirq0 - } - #[doc = "Count direction changed"] - #[inline(always)] - pub fn is_dirirq1(&self) -> bool { - *self == Dirirq::Dirirq1 - } -} -#[doc = "Field `DIRIRQ` writer - Count direction change interrupt"] -pub type DirirqW<'a, REG> = crate::BitWriter1C<'a, REG, Dirirq>; -impl<'a, REG> DirirqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Count direction unchanged"] - #[inline(always)] - pub fn dirirq0(self) -> &'a mut crate::W { - self.variant(Dirirq::Dirirq0) - } - #[doc = "Count direction changed"] - #[inline(always)] - pub fn dirirq1(self) -> &'a mut crate::W { - self.variant(Dirirq::Dirirq1) - } -} -#[doc = "Roll-under Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ruie { - #[doc = "0: Disabled"] - Ruie0 = 0, - #[doc = "1: Enabled"] - Ruie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ruie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RUIE` reader - Roll-under Interrupt Enable"] -pub type RuieR = crate::BitReader; -impl RuieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ruie { - match self.bits { - false => Ruie::Ruie0, - true => Ruie::Ruie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_ruie0(&self) -> bool { - *self == Ruie::Ruie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_ruie1(&self) -> bool { - *self == Ruie::Ruie1 - } -} -#[doc = "Field `RUIE` writer - Roll-under Interrupt Enable"] -pub type RuieW<'a, REG> = crate::BitWriter<'a, REG, Ruie>; -impl<'a, REG> RuieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn ruie0(self) -> &'a mut crate::W { - self.variant(Ruie::Ruie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn ruie1(self) -> &'a mut crate::W { - self.variant(Ruie::Ruie1) - } -} -#[doc = "Roll-under Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ruirq { - #[doc = "0: No roll-under has occurred"] - Ruirq0 = 0, - #[doc = "1: Roll-under has occurred"] - Ruirq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ruirq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RUIRQ` reader - Roll-under Interrupt Request"] -pub type RuirqR = crate::BitReader; -impl RuirqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ruirq { - match self.bits { - false => Ruirq::Ruirq0, - true => Ruirq::Ruirq1, - } - } - #[doc = "No roll-under has occurred"] - #[inline(always)] - pub fn is_ruirq0(&self) -> bool { - *self == Ruirq::Ruirq0 - } - #[doc = "Roll-under has occurred"] - #[inline(always)] - pub fn is_ruirq1(&self) -> bool { - *self == Ruirq::Ruirq1 - } -} -#[doc = "Field `RUIRQ` writer - Roll-under Interrupt Request"] -pub type RuirqW<'a, REG> = crate::BitWriter1C<'a, REG, Ruirq>; -impl<'a, REG> RuirqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No roll-under has occurred"] - #[inline(always)] - pub fn ruirq0(self) -> &'a mut crate::W { - self.variant(Ruirq::Ruirq0) - } - #[doc = "Roll-under has occurred"] - #[inline(always)] - pub fn ruirq1(self) -> &'a mut crate::W { - self.variant(Ruirq::Ruirq1) - } -} -#[doc = "Roll-over Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Roie { - #[doc = "0: Disabled"] - Roie = 0, - #[doc = "1: Enabled"] - Roie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Roie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROIE` reader - Roll-over Interrupt Enable"] -pub type RoieR = crate::BitReader; -impl RoieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Roie { - match self.bits { - false => Roie::Roie, - true => Roie::Roie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_roie(&self) -> bool { - *self == Roie::Roie - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_roie1(&self) -> bool { - *self == Roie::Roie1 - } -} -#[doc = "Field `ROIE` writer - Roll-over Interrupt Enable"] -pub type RoieW<'a, REG> = crate::BitWriter<'a, REG, Roie>; -impl<'a, REG> RoieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn roie(self) -> &'a mut crate::W { - self.variant(Roie::Roie) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn roie1(self) -> &'a mut crate::W { - self.variant(Roie::Roie1) - } -} -#[doc = "Roll-over Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Roirq { - #[doc = "0: No roll-over has occurred"] - Roirq0 = 0, - #[doc = "1: Roll-over has occurred"] - Roirq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Roirq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROIRQ` reader - Roll-over Interrupt Request"] -pub type RoirqR = crate::BitReader; -impl RoirqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Roirq { - match self.bits { - false => Roirq::Roirq0, - true => Roirq::Roirq1, - } - } - #[doc = "No roll-over has occurred"] - #[inline(always)] - pub fn is_roirq0(&self) -> bool { - *self == Roirq::Roirq0 - } - #[doc = "Roll-over has occurred"] - #[inline(always)] - pub fn is_roirq1(&self) -> bool { - *self == Roirq::Roirq1 - } -} -#[doc = "Field `ROIRQ` writer - Roll-over Interrupt Request"] -pub type RoirqW<'a, REG> = crate::BitWriter1C<'a, REG, Roirq>; -impl<'a, REG> RoirqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No roll-over has occurred"] - #[inline(always)] - pub fn roirq0(self) -> &'a mut crate::W { - self.variant(Roirq::Roirq0) - } - #[doc = "Roll-over has occurred"] - #[inline(always)] - pub fn roirq1(self) -> &'a mut crate::W { - self.variant(Roirq::Roirq1) - } -} -#[doc = "Compare 0 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp0ie { - #[doc = "0: Disabled"] - Cmp0ie0 = 0, - #[doc = "1: Enabled"] - Cmp0ie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp0ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP0IE` reader - Compare 0 Interrupt Enable"] -pub type Cmp0ieR = crate::BitReader; -impl Cmp0ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp0ie { - match self.bits { - false => Cmp0ie::Cmp0ie0, - true => Cmp0ie::Cmp0ie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_cmp0ie0(&self) -> bool { - *self == Cmp0ie::Cmp0ie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_cmp0ie1(&self) -> bool { - *self == Cmp0ie::Cmp0ie1 - } -} -#[doc = "Field `CMP0IE` writer - Compare 0 Interrupt Enable"] -pub type Cmp0ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp0ie>; -impl<'a, REG> Cmp0ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn cmp0ie0(self) -> &'a mut crate::W { - self.variant(Cmp0ie::Cmp0ie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn cmp0ie1(self) -> &'a mut crate::W { - self.variant(Cmp0ie::Cmp0ie1) - } -} -#[doc = "Compare 0 Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp0irq { - #[doc = "0: No match has occurred (the position counter does not match the COMP0 value)"] - Cmp0irq0 = 0, - #[doc = "1: COMP match has occurred (the position counter matches the COMP0 value)"] - Cmp0irq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp0irq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP0IRQ` reader - Compare 0 Interrupt Request"] -pub type Cmp0irqR = crate::BitReader; -impl Cmp0irqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp0irq { - match self.bits { - false => Cmp0irq::Cmp0irq0, - true => Cmp0irq::Cmp0irq1, - } - } - #[doc = "No match has occurred (the position counter does not match the COMP0 value)"] - #[inline(always)] - pub fn is_cmp0irq0(&self) -> bool { - *self == Cmp0irq::Cmp0irq0 - } - #[doc = "COMP match has occurred (the position counter matches the COMP0 value)"] - #[inline(always)] - pub fn is_cmp0irq1(&self) -> bool { - *self == Cmp0irq::Cmp0irq1 - } -} -#[doc = "Field `CMP0IRQ` writer - Compare 0 Interrupt Request"] -pub type Cmp0irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp0irq>; -impl<'a, REG> Cmp0irqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No match has occurred (the position counter does not match the COMP0 value)"] - #[inline(always)] - pub fn cmp0irq0(self) -> &'a mut crate::W { - self.variant(Cmp0irq::Cmp0irq0) - } - #[doc = "COMP match has occurred (the position counter matches the COMP0 value)"] - #[inline(always)] - pub fn cmp0irq1(self) -> &'a mut crate::W { - self.variant(Cmp0irq::Cmp0irq1) - } -} -#[doc = "Compare1 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp1ie { - #[doc = "0: Disabled"] - Cmp1ie0 = 0, - #[doc = "1: Enabled"] - Cmp1ie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp1ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP1IE` reader - Compare1 Interrupt Enable"] -pub type Cmp1ieR = crate::BitReader; -impl Cmp1ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp1ie { - match self.bits { - false => Cmp1ie::Cmp1ie0, - true => Cmp1ie::Cmp1ie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_cmp1ie0(&self) -> bool { - *self == Cmp1ie::Cmp1ie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_cmp1ie1(&self) -> bool { - *self == Cmp1ie::Cmp1ie1 - } -} -#[doc = "Field `CMP1IE` writer - Compare1 Interrupt Enable"] -pub type Cmp1ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp1ie>; -impl<'a, REG> Cmp1ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn cmp1ie0(self) -> &'a mut crate::W { - self.variant(Cmp1ie::Cmp1ie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn cmp1ie1(self) -> &'a mut crate::W { - self.variant(Cmp1ie::Cmp1ie1) - } -} -#[doc = "Compare1 Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp1irq { - #[doc = "0: No match has occurred (the position counter does not match the COMP1 value)"] - Cmp1irq0 = 0, - #[doc = "1: COMP1 match has occurred (the position counter matches the COMP1 value)"] - Cmp1irq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp1irq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP1IRQ` reader - Compare1 Interrupt Request"] -pub type Cmp1irqR = crate::BitReader; -impl Cmp1irqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp1irq { - match self.bits { - false => Cmp1irq::Cmp1irq0, - true => Cmp1irq::Cmp1irq1, - } - } - #[doc = "No match has occurred (the position counter does not match the COMP1 value)"] - #[inline(always)] - pub fn is_cmp1irq0(&self) -> bool { - *self == Cmp1irq::Cmp1irq0 - } - #[doc = "COMP1 match has occurred (the position counter matches the COMP1 value)"] - #[inline(always)] - pub fn is_cmp1irq1(&self) -> bool { - *self == Cmp1irq::Cmp1irq1 - } -} -#[doc = "Field `CMP1IRQ` writer - Compare1 Interrupt Request"] -pub type Cmp1irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp1irq>; -impl<'a, REG> Cmp1irqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No match has occurred (the position counter does not match the COMP1 value)"] - #[inline(always)] - pub fn cmp1irq0(self) -> &'a mut crate::W { - self.variant(Cmp1irq::Cmp1irq0) - } - #[doc = "COMP1 match has occurred (the position counter matches the COMP1 value)"] - #[inline(always)] - pub fn cmp1irq1(self) -> &'a mut crate::W { - self.variant(Cmp1irq::Cmp1irq1) - } -} -#[doc = "Compare2 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp2ie { - #[doc = "0: Disabled"] - Cmp2ie0 = 0, - #[doc = "1: Enabled"] - Cmp2ie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp2ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP2IE` reader - Compare2 Interrupt Enable"] -pub type Cmp2ieR = crate::BitReader; -impl Cmp2ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp2ie { - match self.bits { - false => Cmp2ie::Cmp2ie0, - true => Cmp2ie::Cmp2ie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_cmp2ie0(&self) -> bool { - *self == Cmp2ie::Cmp2ie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_cmp2ie1(&self) -> bool { - *self == Cmp2ie::Cmp2ie1 - } -} -#[doc = "Field `CMP2IE` writer - Compare2 Interrupt Enable"] -pub type Cmp2ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp2ie>; -impl<'a, REG> Cmp2ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn cmp2ie0(self) -> &'a mut crate::W { - self.variant(Cmp2ie::Cmp2ie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn cmp2ie1(self) -> &'a mut crate::W { - self.variant(Cmp2ie::Cmp2ie1) - } -} -#[doc = "Compare2 Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp2irq { - #[doc = "0: No match has occurred (the position counter does not match the COMP2 value)"] - Cmp2irq0 = 0, - #[doc = "1: COMP2 match has occurred (the position counter matches the COMP2 value)"] - Cmp2irq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp2irq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP2IRQ` reader - Compare2 Interrupt Request"] -pub type Cmp2irqR = crate::BitReader; -impl Cmp2irqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp2irq { - match self.bits { - false => Cmp2irq::Cmp2irq0, - true => Cmp2irq::Cmp2irq1, - } - } - #[doc = "No match has occurred (the position counter does not match the COMP2 value)"] - #[inline(always)] - pub fn is_cmp2irq0(&self) -> bool { - *self == Cmp2irq::Cmp2irq0 - } - #[doc = "COMP2 match has occurred (the position counter matches the COMP2 value)"] - #[inline(always)] - pub fn is_cmp2irq1(&self) -> bool { - *self == Cmp2irq::Cmp2irq1 - } -} -#[doc = "Field `CMP2IRQ` writer - Compare2 Interrupt Request"] -pub type Cmp2irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp2irq>; -impl<'a, REG> Cmp2irqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No match has occurred (the position counter does not match the COMP2 value)"] - #[inline(always)] - pub fn cmp2irq0(self) -> &'a mut crate::W { - self.variant(Cmp2irq::Cmp2irq0) - } - #[doc = "COMP2 match has occurred (the position counter matches the COMP2 value)"] - #[inline(always)] - pub fn cmp2irq1(self) -> &'a mut crate::W { - self.variant(Cmp2irq::Cmp2irq1) - } -} -#[doc = "Compare3 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp3ie { - #[doc = "0: Disabled"] - Cmp3ie0 = 0, - #[doc = "1: Enabled"] - Cmp3ie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp3ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP3IE` reader - Compare3 Interrupt Enable"] -pub type Cmp3ieR = crate::BitReader; -impl Cmp3ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp3ie { - match self.bits { - false => Cmp3ie::Cmp3ie0, - true => Cmp3ie::Cmp3ie1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_cmp3ie0(&self) -> bool { - *self == Cmp3ie::Cmp3ie0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_cmp3ie1(&self) -> bool { - *self == Cmp3ie::Cmp3ie1 - } -} -#[doc = "Field `CMP3IE` writer - Compare3 Interrupt Enable"] -pub type Cmp3ieW<'a, REG> = crate::BitWriter<'a, REG, Cmp3ie>; -impl<'a, REG> Cmp3ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn cmp3ie0(self) -> &'a mut crate::W { - self.variant(Cmp3ie::Cmp3ie0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn cmp3ie1(self) -> &'a mut crate::W { - self.variant(Cmp3ie::Cmp3ie1) - } -} -#[doc = "Compare3 Interrupt Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp3irq { - #[doc = "0: No match has occurred (the position counter does not match the COMP3 value)"] - Cmp3irq0 = 0, - #[doc = "1: COMP3 match has occurred (the position counter matches the COMP3 value)"] - Cmp3irq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp3irq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP3IRQ` reader - Compare3 Interrupt Request"] -pub type Cmp3irqR = crate::BitReader; -impl Cmp3irqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp3irq { - match self.bits { - false => Cmp3irq::Cmp3irq0, - true => Cmp3irq::Cmp3irq1, - } - } - #[doc = "No match has occurred (the position counter does not match the COMP3 value)"] - #[inline(always)] - pub fn is_cmp3irq0(&self) -> bool { - *self == Cmp3irq::Cmp3irq0 - } - #[doc = "COMP3 match has occurred (the position counter matches the COMP3 value)"] - #[inline(always)] - pub fn is_cmp3irq1(&self) -> bool { - *self == Cmp3irq::Cmp3irq1 - } -} -#[doc = "Field `CMP3IRQ` writer - Compare3 Interrupt Request"] -pub type Cmp3irqW<'a, REG> = crate::BitWriter1C<'a, REG, Cmp3irq>; -impl<'a, REG> Cmp3irqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No match has occurred (the position counter does not match the COMP3 value)"] - #[inline(always)] - pub fn cmp3irq0(self) -> &'a mut crate::W { - self.variant(Cmp3irq::Cmp3irq0) - } - #[doc = "COMP3 match has occurred (the position counter matches the COMP3 value)"] - #[inline(always)] - pub fn cmp3irq1(self) -> &'a mut crate::W { - self.variant(Cmp3irq::Cmp3irq1) - } -} -impl R { - #[doc = "Bit 0 - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] - #[inline(always)] - pub fn sabie(&self) -> SabieR { - SabieR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Simultaneous PHASEA and PHASEB Change Interrupt Request"] - #[inline(always)] - pub fn sabirq(&self) -> SabirqR { - SabirqR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Count direction change interrupt enable"] - #[inline(always)] - pub fn dirie(&self) -> DirieR { - DirieR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Count direction change interrupt"] - #[inline(always)] - pub fn dirirq(&self) -> DirirqR { - DirirqR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Roll-under Interrupt Enable"] - #[inline(always)] - pub fn ruie(&self) -> RuieR { - RuieR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Roll-under Interrupt Request"] - #[inline(always)] - pub fn ruirq(&self) -> RuirqR { - RuirqR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Roll-over Interrupt Enable"] - #[inline(always)] - pub fn roie(&self) -> RoieR { - RoieR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Roll-over Interrupt Request"] - #[inline(always)] - pub fn roirq(&self) -> RoirqR { - RoirqR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Compare 0 Interrupt Enable"] - #[inline(always)] - pub fn cmp0ie(&self) -> Cmp0ieR { - Cmp0ieR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Compare 0 Interrupt Request"] - #[inline(always)] - pub fn cmp0irq(&self) -> Cmp0irqR { - Cmp0irqR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Compare1 Interrupt Enable"] - #[inline(always)] - pub fn cmp1ie(&self) -> Cmp1ieR { - Cmp1ieR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Compare1 Interrupt Request"] - #[inline(always)] - pub fn cmp1irq(&self) -> Cmp1irqR { - Cmp1irqR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Compare2 Interrupt Enable"] - #[inline(always)] - pub fn cmp2ie(&self) -> Cmp2ieR { - Cmp2ieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Compare2 Interrupt Request"] - #[inline(always)] - pub fn cmp2irq(&self) -> Cmp2irqR { - Cmp2irqR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Compare3 Interrupt Enable"] - #[inline(always)] - pub fn cmp3ie(&self) -> Cmp3ieR { - Cmp3ieR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Compare3 Interrupt Request"] - #[inline(always)] - pub fn cmp3irq(&self) -> Cmp3irqR { - Cmp3irqR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Simultaneous PHASEA and PHASEB Change Interrupt Enable"] - #[inline(always)] - pub fn sabie(&mut self) -> SabieW { - SabieW::new(self, 0) - } - #[doc = "Bit 1 - Simultaneous PHASEA and PHASEB Change Interrupt Request"] - #[inline(always)] - pub fn sabirq(&mut self) -> SabirqW { - SabirqW::new(self, 1) - } - #[doc = "Bit 2 - Count direction change interrupt enable"] - #[inline(always)] - pub fn dirie(&mut self) -> DirieW { - DirieW::new(self, 2) - } - #[doc = "Bit 3 - Count direction change interrupt"] - #[inline(always)] - pub fn dirirq(&mut self) -> DirirqW { - DirirqW::new(self, 3) - } - #[doc = "Bit 4 - Roll-under Interrupt Enable"] - #[inline(always)] - pub fn ruie(&mut self) -> RuieW { - RuieW::new(self, 4) - } - #[doc = "Bit 5 - Roll-under Interrupt Request"] - #[inline(always)] - pub fn ruirq(&mut self) -> RuirqW { - RuirqW::new(self, 5) - } - #[doc = "Bit 6 - Roll-over Interrupt Enable"] - #[inline(always)] - pub fn roie(&mut self) -> RoieW { - RoieW::new(self, 6) - } - #[doc = "Bit 7 - Roll-over Interrupt Request"] - #[inline(always)] - pub fn roirq(&mut self) -> RoirqW { - RoirqW::new(self, 7) - } - #[doc = "Bit 8 - Compare 0 Interrupt Enable"] - #[inline(always)] - pub fn cmp0ie(&mut self) -> Cmp0ieW { - Cmp0ieW::new(self, 8) - } - #[doc = "Bit 9 - Compare 0 Interrupt Request"] - #[inline(always)] - pub fn cmp0irq(&mut self) -> Cmp0irqW { - Cmp0irqW::new(self, 9) - } - #[doc = "Bit 10 - Compare1 Interrupt Enable"] - #[inline(always)] - pub fn cmp1ie(&mut self) -> Cmp1ieW { - Cmp1ieW::new(self, 10) - } - #[doc = "Bit 11 - Compare1 Interrupt Request"] - #[inline(always)] - pub fn cmp1irq(&mut self) -> Cmp1irqW { - Cmp1irqW::new(self, 11) - } - #[doc = "Bit 12 - Compare2 Interrupt Enable"] - #[inline(always)] - pub fn cmp2ie(&mut self) -> Cmp2ieW { - Cmp2ieW::new(self, 12) - } - #[doc = "Bit 13 - Compare2 Interrupt Request"] - #[inline(always)] - pub fn cmp2irq(&mut self) -> Cmp2irqW { - Cmp2irqW::new(self, 13) - } - #[doc = "Bit 14 - Compare3 Interrupt Enable"] - #[inline(always)] - pub fn cmp3ie(&mut self) -> Cmp3ieW { - Cmp3ieW::new(self, 14) - } - #[doc = "Bit 15 - Compare3 Interrupt Request"] - #[inline(always)] - pub fn cmp3irq(&mut self) -> Cmp3irqW { - Cmp3irqW::new(self, 15) - } -} -#[doc = "Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IntctrlSpec; -impl crate::RegisterSpec for IntctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`intctrl::R`](R) reader structure"] -impl crate::Readable for IntctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`intctrl::W`](W) writer structure"] -impl crate::Writable for IntctrlSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0xaaaa; -} -#[doc = "`reset()` method sets INTCTRL to value 0"] -impl crate::Resettable for IntctrlSpec {} diff --git a/mcxa276-pac/src/eqdc0/lastedge.rs b/mcxa276-pac/src/eqdc0/lastedge.rs deleted file mode 100644 index 291fcbc53..000000000 --- a/mcxa276-pac/src/eqdc0/lastedge.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `LASTEDGE` reader"] -pub type R = crate::R; -#[doc = "Field `LASTEDGE` reader - Last Edge Time Counter"] -pub type LastedgeR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Last Edge Time Counter"] - #[inline(always)] - pub fn lastedge(&self) -> LastedgeR { - LastedgeR::new(self.bits) - } -} -#[doc = "Last Edge Time Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedge::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LastedgeSpec; -impl crate::RegisterSpec for LastedgeSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lastedge::R`](R) reader structure"] -impl crate::Readable for LastedgeSpec {} -#[doc = "`reset()` method sets LASTEDGE to value 0xffff"] -impl crate::Resettable for LastedgeSpec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/eqdc0/lastedgeh.rs b/mcxa276-pac/src/eqdc0/lastedgeh.rs deleted file mode 100644 index c4ed73af4..000000000 --- a/mcxa276-pac/src/eqdc0/lastedgeh.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `LASTEDGEH` reader"] -pub type R = crate::R; -#[doc = "Field `LASTEDGEH` reader - Last Edge Time Hold"] -pub type LastedgehR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Last Edge Time Hold"] - #[inline(always)] - pub fn lastedgeh(&self) -> LastedgehR { - LastedgehR::new(self.bits) - } -} -#[doc = "Last Edge Time Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lastedgeh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LastedgehSpec; -impl crate::RegisterSpec for LastedgehSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lastedgeh::R`](R) reader structure"] -impl crate::Readable for LastedgehSpec {} -#[doc = "`reset()` method sets LASTEDGEH to value 0xffff"] -impl crate::Resettable for LastedgehSpec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/eqdc0/lcomp0.rs b/mcxa276-pac/src/eqdc0/lcomp0.rs deleted file mode 100644 index 33f8dda54..000000000 --- a/mcxa276-pac/src/eqdc0/lcomp0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `LCOMP0` reader"] -pub type R = crate::R; -#[doc = "Register `LCOMP0` writer"] -pub type W = crate::W; -#[doc = "Field `LCOMP0` reader - LCOMP0"] -pub type Lcomp0R = crate::FieldReader; -#[doc = "Field `LCOMP0` writer - LCOMP0"] -pub type Lcomp0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - LCOMP0"] - #[inline(always)] - pub fn lcomp0(&self) -> Lcomp0R { - Lcomp0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - LCOMP0"] - #[inline(always)] - pub fn lcomp0(&mut self) -> Lcomp0W { - Lcomp0W::new(self, 0) - } -} -#[doc = "Lower Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcomp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lcomp0Spec; -impl crate::RegisterSpec for Lcomp0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lcomp0::R`](R) reader structure"] -impl crate::Readable for Lcomp0Spec {} -#[doc = "`write(|w| ..)` method takes [`lcomp0::W`](W) writer structure"] -impl crate::Writable for Lcomp0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCOMP0 to value 0"] -impl crate::Resettable for Lcomp0Spec {} diff --git a/mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs b/mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs deleted file mode 100644 index 599f3480e..000000000 --- a/mcxa276-pac/src/eqdc0/lcomp1_lcomp1.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `LCOMP1` writer"] -pub type W = crate::W; -#[doc = "Field `LCOMP1` writer - LCOMP1"] -pub type Lcomp1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - LCOMP1"] - #[inline(always)] - pub fn lcomp1(&mut self) -> Lcomp1W { - Lcomp1W::new(self, 0) - } -} -#[doc = "Lower Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp1_lcomp1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lcomp1Lcomp1Spec; -impl crate::RegisterSpec for Lcomp1Lcomp1Spec { - type Ux = u16; -} -#[doc = "`write(|w| ..)` method takes [`lcomp1_lcomp1::W`](W) writer structure"] -impl crate::Writable for Lcomp1Lcomp1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCOMP1 to value 0"] -impl crate::Resettable for Lcomp1Lcomp1Spec {} diff --git a/mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs b/mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs deleted file mode 100644 index 6beaa54e2..000000000 --- a/mcxa276-pac/src/eqdc0/lcomp2_lcomp2.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `LCOMP2` writer"] -pub type W = crate::W; -#[doc = "Field `LCOMP2` writer - LCOMP2"] -pub type Lcomp2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - LCOMP2"] - #[inline(always)] - pub fn lcomp2(&mut self) -> Lcomp2W { - Lcomp2W::new(self, 0) - } -} -#[doc = "Lower Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp2_lcomp2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lcomp2Lcomp2Spec; -impl crate::RegisterSpec for Lcomp2Lcomp2Spec { - type Ux = u16; -} -#[doc = "`write(|w| ..)` method takes [`lcomp2_lcomp2::W`](W) writer structure"] -impl crate::Writable for Lcomp2Lcomp2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCOMP2 to value 0"] -impl crate::Resettable for Lcomp2Lcomp2Spec {} diff --git a/mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs b/mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs deleted file mode 100644 index c2befa513..000000000 --- a/mcxa276-pac/src/eqdc0/lcomp3_lcomp3.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `LCOMP3` writer"] -pub type W = crate::W; -#[doc = "Field `LCOMP3` writer - LCOMP3"] -pub type Lcomp3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - LCOMP3"] - #[inline(always)] - pub fn lcomp3(&mut self) -> Lcomp3W { - Lcomp3W::new(self, 0) - } -} -#[doc = "Lower Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcomp3_lcomp3::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lcomp3Lcomp3Spec; -impl crate::RegisterSpec for Lcomp3Lcomp3Spec { - type Ux = u16; -} -#[doc = "`write(|w| ..)` method takes [`lcomp3_lcomp3::W`](W) writer structure"] -impl crate::Writable for Lcomp3Lcomp3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCOMP3 to value 0"] -impl crate::Resettable for Lcomp3Lcomp3Spec {} diff --git a/mcxa276-pac/src/eqdc0/linit.rs b/mcxa276-pac/src/eqdc0/linit.rs deleted file mode 100644 index 432aaf653..000000000 --- a/mcxa276-pac/src/eqdc0/linit.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `LINIT` reader"] -pub type R = crate::R; -#[doc = "Register `LINIT` writer"] -pub type W = crate::W; -#[doc = "Field `INIT` reader - INIT"] -pub type InitR = crate::FieldReader; -#[doc = "Field `INIT` writer - INIT"] -pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - INIT"] - #[inline(always)] - pub fn init(&self) -> InitR { - InitR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - INIT"] - #[inline(always)] - pub fn init(&mut self) -> InitW { - InitW::new(self, 0) - } -} -#[doc = "Lower Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`linit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LinitSpec; -impl crate::RegisterSpec for LinitSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`linit::R`](R) reader structure"] -impl crate::Readable for LinitSpec {} -#[doc = "`write(|w| ..)` method takes [`linit::W`](W) writer structure"] -impl crate::Writable for LinitSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LINIT to value 0"] -impl crate::Resettable for LinitSpec {} diff --git a/mcxa276-pac/src/eqdc0/lmod.rs b/mcxa276-pac/src/eqdc0/lmod.rs deleted file mode 100644 index 5abcab005..000000000 --- a/mcxa276-pac/src/eqdc0/lmod.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `LMOD` reader"] -pub type R = crate::R; -#[doc = "Register `LMOD` writer"] -pub type W = crate::W; -#[doc = "Field `MOD` reader - MOD"] -pub type ModR = crate::FieldReader; -#[doc = "Field `MOD` writer - MOD"] -pub type ModW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - MOD"] - #[inline(always)] - pub fn mod_(&self) -> ModR { - ModR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - MOD"] - #[inline(always)] - pub fn mod_(&mut self) -> ModW { - ModW::new(self, 0) - } -} -#[doc = "Lower Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lmod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lmod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LmodSpec; -impl crate::RegisterSpec for LmodSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lmod::R`](R) reader structure"] -impl crate::Readable for LmodSpec {} -#[doc = "`write(|w| ..)` method takes [`lmod::W`](W) writer structure"] -impl crate::Writable for LmodSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LMOD to value 0"] -impl crate::Resettable for LmodSpec {} diff --git a/mcxa276-pac/src/eqdc0/lpos.rs b/mcxa276-pac/src/eqdc0/lpos.rs deleted file mode 100644 index b1d030dd9..000000000 --- a/mcxa276-pac/src/eqdc0/lpos.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `LPOS` reader"] -pub type R = crate::R; -#[doc = "Register `LPOS` writer"] -pub type W = crate::W; -#[doc = "Field `POS` reader - POS"] -pub type PosR = crate::FieldReader; -#[doc = "Field `POS` writer - POS"] -pub type PosW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - POS"] - #[inline(always)] - pub fn pos(&self) -> PosR { - PosR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - POS"] - #[inline(always)] - pub fn pos(&mut self) -> PosW { - PosW::new(self, 0) - } -} -#[doc = "Lower Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lpos::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpos::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LposSpec; -impl crate::RegisterSpec for LposSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lpos::R`](R) reader structure"] -impl crate::Readable for LposSpec {} -#[doc = "`write(|w| ..)` method takes [`lpos::W`](W) writer structure"] -impl crate::Writable for LposSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPOS to value 0"] -impl crate::Resettable for LposSpec {} diff --git a/mcxa276-pac/src/eqdc0/lposh.rs b/mcxa276-pac/src/eqdc0/lposh.rs deleted file mode 100644 index d8c490a30..000000000 --- a/mcxa276-pac/src/eqdc0/lposh.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `LPOSH` reader"] -pub type R = crate::R; -#[doc = "Field `LPOSH` reader - POSH"] -pub type LposhR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - POSH"] - #[inline(always)] - pub fn lposh(&self) -> LposhR { - LposhR::new(self.bits) - } -} -#[doc = "Lower Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LposhSpec; -impl crate::RegisterSpec for LposhSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lposh::R`](R) reader structure"] -impl crate::Readable for LposhSpec {} -#[doc = "`reset()` method sets LPOSH to value 0"] -impl crate::Resettable for LposhSpec {} diff --git a/mcxa276-pac/src/eqdc0/lposh1_lposh1.rs b/mcxa276-pac/src/eqdc0/lposh1_lposh1.rs deleted file mode 100644 index be342ef9c..000000000 --- a/mcxa276-pac/src/eqdc0/lposh1_lposh1.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `LPOSH1` reader"] -pub type R = crate::R; -#[doc = "Field `LPOSH1` reader - LPOSH1"] -pub type Lposh1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - LPOSH1"] - #[inline(always)] - pub fn lposh1(&self) -> Lposh1R { - Lposh1R::new(self.bits) - } -} -#[doc = "Lower Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh1_lposh1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lposh1Lposh1Spec; -impl crate::RegisterSpec for Lposh1Lposh1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lposh1_lposh1::R`](R) reader structure"] -impl crate::Readable for Lposh1Lposh1Spec {} -#[doc = "`reset()` method sets LPOSH1 to value 0"] -impl crate::Resettable for Lposh1Lposh1Spec {} diff --git a/mcxa276-pac/src/eqdc0/lposh2_lposh2.rs b/mcxa276-pac/src/eqdc0/lposh2_lposh2.rs deleted file mode 100644 index 561660484..000000000 --- a/mcxa276-pac/src/eqdc0/lposh2_lposh2.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `LPOSH2` reader"] -pub type R = crate::R; -#[doc = "Field `LPOSH2` reader - LPOSH2"] -pub type Lposh2R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - LPOSH2"] - #[inline(always)] - pub fn lposh2(&self) -> Lposh2R { - Lposh2R::new(self.bits) - } -} -#[doc = "Lower Position Holder Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh2_lposh2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lposh2Lposh2Spec; -impl crate::RegisterSpec for Lposh2Lposh2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lposh2_lposh2::R`](R) reader structure"] -impl crate::Readable for Lposh2Lposh2Spec {} -#[doc = "`reset()` method sets LPOSH2 to value 0"] -impl crate::Resettable for Lposh2Lposh2Spec {} diff --git a/mcxa276-pac/src/eqdc0/lposh3_lposh3.rs b/mcxa276-pac/src/eqdc0/lposh3_lposh3.rs deleted file mode 100644 index 5abd16bb2..000000000 --- a/mcxa276-pac/src/eqdc0/lposh3_lposh3.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `LPOSH3` reader"] -pub type R = crate::R; -#[doc = "Field `LPOSH3` reader - LPOSH3"] -pub type Lposh3R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - LPOSH3"] - #[inline(always)] - pub fn lposh3(&self) -> Lposh3R { - Lposh3R::new(self.bits) - } -} -#[doc = "Lower Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`lposh3_lposh3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lposh3Lposh3Spec; -impl crate::RegisterSpec for Lposh3Lposh3Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lposh3_lposh3::R`](R) reader structure"] -impl crate::Readable for Lposh3Lposh3Spec {} -#[doc = "`reset()` method sets LPOSH3 to value 0"] -impl crate::Resettable for Lposh3Lposh3Spec {} diff --git a/mcxa276-pac/src/eqdc0/lverid.rs b/mcxa276-pac/src/eqdc0/lverid.rs deleted file mode 100644 index 03f861874..000000000 --- a/mcxa276-pac/src/eqdc0/lverid.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `LVERID` reader"] -pub type R = crate::R; -#[doc = "Field `LVERID` reader - LVERID"] -pub type LveridR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - LVERID"] - #[inline(always)] - pub fn lverid(&self) -> LveridR { - LveridR::new(self.bits) - } -} -#[doc = "Lower VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`lverid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LveridSpec; -impl crate::RegisterSpec for LveridSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`lverid::R`](R) reader structure"] -impl crate::Readable for LveridSpec {} -#[doc = "`reset()` method sets LVERID to value 0x01"] -impl crate::Resettable for LveridSpec { - const RESET_VALUE: u16 = 0x01; -} diff --git a/mcxa276-pac/src/eqdc0/posd.rs b/mcxa276-pac/src/eqdc0/posd.rs deleted file mode 100644 index 707140327..000000000 --- a/mcxa276-pac/src/eqdc0/posd.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `POSD` reader"] -pub type R = crate::R; -#[doc = "Register `POSD` writer"] -pub type W = crate::W; -#[doc = "Field `POSD` reader - POSD"] -pub type PosdR = crate::FieldReader; -#[doc = "Field `POSD` writer - POSD"] -pub type PosdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - POSD"] - #[inline(always)] - pub fn posd(&self) -> PosdR { - PosdR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - POSD"] - #[inline(always)] - pub fn posd(&mut self) -> PosdW { - PosdW::new(self, 0) - } -} -#[doc = "Position Difference Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`posd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PosdSpec; -impl crate::RegisterSpec for PosdSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`posd::R`](R) reader structure"] -impl crate::Readable for PosdSpec {} -#[doc = "`write(|w| ..)` method takes [`posd::W`](W) writer structure"] -impl crate::Writable for PosdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets POSD to value 0"] -impl crate::Resettable for PosdSpec {} diff --git a/mcxa276-pac/src/eqdc0/posdh.rs b/mcxa276-pac/src/eqdc0/posdh.rs deleted file mode 100644 index 894f692af..000000000 --- a/mcxa276-pac/src/eqdc0/posdh.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `POSDH` reader"] -pub type R = crate::R; -#[doc = "Field `POSDH` reader - POSDH"] -pub type PosdhR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - POSDH"] - #[inline(always)] - pub fn posdh(&self) -> PosdhR { - PosdhR::new(self.bits) - } -} -#[doc = "Position Difference Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PosdhSpec; -impl crate::RegisterSpec for PosdhSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`posdh::R`](R) reader structure"] -impl crate::Readable for PosdhSpec {} -#[doc = "`reset()` method sets POSDH to value 0"] -impl crate::Resettable for PosdhSpec {} diff --git a/mcxa276-pac/src/eqdc0/posdper.rs b/mcxa276-pac/src/eqdc0/posdper.rs deleted file mode 100644 index 37d40edbb..000000000 --- a/mcxa276-pac/src/eqdc0/posdper.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `POSDPER` reader"] -pub type R = crate::R; -#[doc = "Field `POSDPER` reader - Position difference period"] -pub type PosdperR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Position difference period"] - #[inline(always)] - pub fn posdper(&self) -> PosdperR { - PosdperR::new(self.bits) - } -} -#[doc = "Position Difference Period Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdper::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PosdperSpec; -impl crate::RegisterSpec for PosdperSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`posdper::R`](R) reader structure"] -impl crate::Readable for PosdperSpec {} -#[doc = "`reset()` method sets POSDPER to value 0xffff"] -impl crate::Resettable for PosdperSpec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/eqdc0/posdperbfr.rs b/mcxa276-pac/src/eqdc0/posdperbfr.rs deleted file mode 100644 index 897b8eb70..000000000 --- a/mcxa276-pac/src/eqdc0/posdperbfr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `POSDPERBFR` reader"] -pub type R = crate::R; -#[doc = "Field `POSDPERBFR` reader - Position difference period buffer"] -pub type PosdperbfrR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Position difference period buffer"] - #[inline(always)] - pub fn posdperbfr(&self) -> PosdperbfrR { - PosdperbfrR::new(self.bits) - } -} -#[doc = "Position Difference Period Buffer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperbfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PosdperbfrSpec; -impl crate::RegisterSpec for PosdperbfrSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`posdperbfr::R`](R) reader structure"] -impl crate::Readable for PosdperbfrSpec {} -#[doc = "`reset()` method sets POSDPERBFR to value 0xffff"] -impl crate::Resettable for PosdperbfrSpec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/eqdc0/posdperh.rs b/mcxa276-pac/src/eqdc0/posdperh.rs deleted file mode 100644 index 1a972bc10..000000000 --- a/mcxa276-pac/src/eqdc0/posdperh.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `POSDPERH` reader"] -pub type R = crate::R; -#[doc = "Field `POSDPERH` reader - Position difference period hold"] -pub type PosdperhR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Position difference period hold"] - #[inline(always)] - pub fn posdperh(&self) -> PosdperhR { - PosdperhR::new(self.bits) - } -} -#[doc = "Position Difference Period Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`posdperh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PosdperhSpec; -impl crate::RegisterSpec for PosdperhSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`posdperh::R`](R) reader structure"] -impl crate::Readable for PosdperhSpec {} -#[doc = "`reset()` method sets POSDPERH to value 0xffff"] -impl crate::Resettable for PosdperhSpec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/eqdc0/rev.rs b/mcxa276-pac/src/eqdc0/rev.rs deleted file mode 100644 index 73cb03d17..000000000 --- a/mcxa276-pac/src/eqdc0/rev.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `REV` reader"] -pub type R = crate::R; -#[doc = "Register `REV` writer"] -pub type W = crate::W; -#[doc = "Field `REV` reader - REV"] -pub type RevR = crate::FieldReader; -#[doc = "Field `REV` writer - REV"] -pub type RevW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - REV"] - #[inline(always)] - pub fn rev(&self) -> RevR { - RevR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - REV"] - #[inline(always)] - pub fn rev(&mut self) -> RevW { - RevW::new(self, 0) - } -} -#[doc = "Revolution Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rev::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RevSpec; -impl crate::RegisterSpec for RevSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`rev::R`](R) reader structure"] -impl crate::Readable for RevSpec {} -#[doc = "`write(|w| ..)` method takes [`rev::W`](W) writer structure"] -impl crate::Writable for RevSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets REV to value 0"] -impl crate::Resettable for RevSpec {} diff --git a/mcxa276-pac/src/eqdc0/revh.rs b/mcxa276-pac/src/eqdc0/revh.rs deleted file mode 100644 index ef0aa96b1..000000000 --- a/mcxa276-pac/src/eqdc0/revh.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `REVH` reader"] -pub type R = crate::R; -#[doc = "Field `REVH` reader - REVH"] -pub type RevhR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - REVH"] - #[inline(always)] - pub fn revh(&self) -> RevhR { - RevhR::new(self.bits) - } -} -#[doc = "Revolution Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`revh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RevhSpec; -impl crate::RegisterSpec for RevhSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`revh::R`](R) reader structure"] -impl crate::Readable for RevhSpec {} -#[doc = "`reset()` method sets REVH to value 0"] -impl crate::Resettable for RevhSpec {} diff --git a/mcxa276-pac/src/eqdc0/tst.rs b/mcxa276-pac/src/eqdc0/tst.rs deleted file mode 100644 index ae86f62c3..000000000 --- a/mcxa276-pac/src/eqdc0/tst.rs +++ /dev/null @@ -1,238 +0,0 @@ -#[doc = "Register `TST` reader"] -pub type R = crate::R; -#[doc = "Register `TST` writer"] -pub type W = crate::W; -#[doc = "Field `TEST_COUNT` reader - TEST_COUNT"] -pub type TestCountR = crate::FieldReader; -#[doc = "Field `TEST_COUNT` writer - TEST_COUNT"] -pub type TestCountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `TEST_PERIOD` reader - TEST_PERIOD"] -pub type TestPeriodR = crate::FieldReader; -#[doc = "Field `TEST_PERIOD` writer - TEST_PERIOD"] -pub type TestPeriodW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Quadrature Decoder Negative Signal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Qdn { - #[doc = "0: Generates a positive quadrature decoder signal"] - Qdn0 = 0, - #[doc = "1: Generates a negative quadrature decoder signal"] - Qdn1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Qdn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `QDN` reader - Quadrature Decoder Negative Signal"] -pub type QdnR = crate::BitReader; -impl QdnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Qdn { - match self.bits { - false => Qdn::Qdn0, - true => Qdn::Qdn1, - } - } - #[doc = "Generates a positive quadrature decoder signal"] - #[inline(always)] - pub fn is_qdn0(&self) -> bool { - *self == Qdn::Qdn0 - } - #[doc = "Generates a negative quadrature decoder signal"] - #[inline(always)] - pub fn is_qdn1(&self) -> bool { - *self == Qdn::Qdn1 - } -} -#[doc = "Field `QDN` writer - Quadrature Decoder Negative Signal"] -pub type QdnW<'a, REG> = crate::BitWriter<'a, REG, Qdn>; -impl<'a, REG> QdnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Generates a positive quadrature decoder signal"] - #[inline(always)] - pub fn qdn0(self) -> &'a mut crate::W { - self.variant(Qdn::Qdn0) - } - #[doc = "Generates a negative quadrature decoder signal"] - #[inline(always)] - pub fn qdn1(self) -> &'a mut crate::W { - self.variant(Qdn::Qdn1) - } -} -#[doc = "Test Counter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tce { - #[doc = "0: Disabled"] - Tce0 = 0, - #[doc = "1: Enabled"] - Tce1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tce) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCE` reader - Test Counter Enable"] -pub type TceR = crate::BitReader; -impl TceR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tce { - match self.bits { - false => Tce::Tce0, - true => Tce::Tce1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_tce0(&self) -> bool { - *self == Tce::Tce0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_tce1(&self) -> bool { - *self == Tce::Tce1 - } -} -#[doc = "Field `TCE` writer - Test Counter Enable"] -pub type TceW<'a, REG> = crate::BitWriter<'a, REG, Tce>; -impl<'a, REG> TceW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn tce0(self) -> &'a mut crate::W { - self.variant(Tce::Tce0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn tce1(self) -> &'a mut crate::W { - self.variant(Tce::Tce1) - } -} -#[doc = "Test Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ten { - #[doc = "0: Disabled"] - Ten0 = 0, - #[doc = "1: Enabled"] - Ten1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TEN` reader - Test Mode Enable"] -pub type TenR = crate::BitReader; -impl TenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ten { - match self.bits { - false => Ten::Ten0, - true => Ten::Ten1, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_ten0(&self) -> bool { - *self == Ten::Ten0 - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_ten1(&self) -> bool { - *self == Ten::Ten1 - } -} -#[doc = "Field `TEN` writer - Test Mode Enable"] -pub type TenW<'a, REG> = crate::BitWriter<'a, REG, Ten>; -impl<'a, REG> TenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn ten0(self) -> &'a mut crate::W { - self.variant(Ten::Ten0) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn ten1(self) -> &'a mut crate::W { - self.variant(Ten::Ten1) - } -} -impl R { - #[doc = "Bits 0:7 - TEST_COUNT"] - #[inline(always)] - pub fn test_count(&self) -> TestCountR { - TestCountR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:12 - TEST_PERIOD"] - #[inline(always)] - pub fn test_period(&self) -> TestPeriodR { - TestPeriodR::new(((self.bits >> 8) & 0x1f) as u8) - } - #[doc = "Bit 13 - Quadrature Decoder Negative Signal"] - #[inline(always)] - pub fn qdn(&self) -> QdnR { - QdnR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Test Counter Enable"] - #[inline(always)] - pub fn tce(&self) -> TceR { - TceR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Test Mode Enable"] - #[inline(always)] - pub fn ten(&self) -> TenR { - TenR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - TEST_COUNT"] - #[inline(always)] - pub fn test_count(&mut self) -> TestCountW { - TestCountW::new(self, 0) - } - #[doc = "Bits 8:12 - TEST_PERIOD"] - #[inline(always)] - pub fn test_period(&mut self) -> TestPeriodW { - TestPeriodW::new(self, 8) - } - #[doc = "Bit 13 - Quadrature Decoder Negative Signal"] - #[inline(always)] - pub fn qdn(&mut self) -> QdnW { - QdnW::new(self, 13) - } - #[doc = "Bit 14 - Test Counter Enable"] - #[inline(always)] - pub fn tce(&mut self) -> TceW { - TceW::new(self, 14) - } - #[doc = "Bit 15 - Test Mode Enable"] - #[inline(always)] - pub fn ten(&mut self) -> TenW { - TenW::new(self, 15) - } -} -#[doc = "Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TstSpec; -impl crate::RegisterSpec for TstSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`tst::R`](R) reader structure"] -impl crate::Readable for TstSpec {} -#[doc = "`write(|w| ..)` method takes [`tst::W`](W) writer structure"] -impl crate::Writable for TstSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TST to value 0"] -impl crate::Resettable for TstSpec {} diff --git a/mcxa276-pac/src/eqdc0/ucomp0.rs b/mcxa276-pac/src/eqdc0/ucomp0.rs deleted file mode 100644 index a53613e16..000000000 --- a/mcxa276-pac/src/eqdc0/ucomp0.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `UCOMP0` reader"] -pub type R = crate::R; -#[doc = "Register `UCOMP0` writer"] -pub type W = crate::W; -#[doc = "Field `UCOMP0` reader - UCOMP0"] -pub type Ucomp0R = crate::FieldReader; -#[doc = "Field `UCOMP0` writer - UCOMP0"] -pub type Ucomp0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - UCOMP0"] - #[inline(always)] - pub fn ucomp0(&self) -> Ucomp0R { - Ucomp0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - UCOMP0"] - #[inline(always)] - pub fn ucomp0(&mut self) -> Ucomp0W { - Ucomp0W::new(self, 0) - } -} -#[doc = "Upper Position Compare Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucomp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ucomp0Spec; -impl crate::RegisterSpec for Ucomp0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`ucomp0::R`](R) reader structure"] -impl crate::Readable for Ucomp0Spec {} -#[doc = "`write(|w| ..)` method takes [`ucomp0::W`](W) writer structure"] -impl crate::Writable for Ucomp0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets UCOMP0 to value 0x8000"] -impl crate::Resettable for Ucomp0Spec { - const RESET_VALUE: u16 = 0x8000; -} diff --git a/mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs b/mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs deleted file mode 100644 index edeff1ed0..000000000 --- a/mcxa276-pac/src/eqdc0/ucomp1_ucomp1.rs +++ /dev/null @@ -1,24 +0,0 @@ -#[doc = "Register `UCOMP1` writer"] -pub type W = crate::W; -#[doc = "Field `UCOMP1` writer - UCOMP1"] -pub type Ucomp1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - UCOMP1"] - #[inline(always)] - pub fn ucomp1(&mut self) -> Ucomp1W { - Ucomp1W::new(self, 0) - } -} -#[doc = "Upper Position Compare 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp1_ucomp1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ucomp1Ucomp1Spec; -impl crate::RegisterSpec for Ucomp1Ucomp1Spec { - type Ux = u16; -} -#[doc = "`write(|w| ..)` method takes [`ucomp1_ucomp1::W`](W) writer structure"] -impl crate::Writable for Ucomp1Ucomp1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets UCOMP1 to value 0x8000"] -impl crate::Resettable for Ucomp1Ucomp1Spec { - const RESET_VALUE: u16 = 0x8000; -} diff --git a/mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs b/mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs deleted file mode 100644 index 505072d53..000000000 --- a/mcxa276-pac/src/eqdc0/ucomp2_ucomp2.rs +++ /dev/null @@ -1,24 +0,0 @@ -#[doc = "Register `UCOMP2` writer"] -pub type W = crate::W; -#[doc = "Field `UCOMP2` writer - UCOMP2"] -pub type Ucomp2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - UCOMP2"] - #[inline(always)] - pub fn ucomp2(&mut self) -> Ucomp2W { - Ucomp2W::new(self, 0) - } -} -#[doc = "Upper Position Compare 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp2_ucomp2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ucomp2Ucomp2Spec; -impl crate::RegisterSpec for Ucomp2Ucomp2Spec { - type Ux = u16; -} -#[doc = "`write(|w| ..)` method takes [`ucomp2_ucomp2::W`](W) writer structure"] -impl crate::Writable for Ucomp2Ucomp2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets UCOMP2 to value 0x8000"] -impl crate::Resettable for Ucomp2Ucomp2Spec { - const RESET_VALUE: u16 = 0x8000; -} diff --git a/mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs b/mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs deleted file mode 100644 index 2e58ab227..000000000 --- a/mcxa276-pac/src/eqdc0/ucomp3_ucomp3.rs +++ /dev/null @@ -1,24 +0,0 @@ -#[doc = "Register `UCOMP3` writer"] -pub type W = crate::W; -#[doc = "Field `UCOMP3` writer - UCOMP3"] -pub type Ucomp3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - UCOMP3"] - #[inline(always)] - pub fn ucomp3(&mut self) -> Ucomp3W { - Ucomp3W::new(self, 0) - } -} -#[doc = "Upper Position Compare 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucomp3_ucomp3::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ucomp3Ucomp3Spec; -impl crate::RegisterSpec for Ucomp3Ucomp3Spec { - type Ux = u16; -} -#[doc = "`write(|w| ..)` method takes [`ucomp3_ucomp3::W`](W) writer structure"] -impl crate::Writable for Ucomp3Ucomp3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets UCOMP3 to value 0x8000"] -impl crate::Resettable for Ucomp3Ucomp3Spec { - const RESET_VALUE: u16 = 0x8000; -} diff --git a/mcxa276-pac/src/eqdc0/uinit.rs b/mcxa276-pac/src/eqdc0/uinit.rs deleted file mode 100644 index 1c83a48aa..000000000 --- a/mcxa276-pac/src/eqdc0/uinit.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `UINIT` reader"] -pub type R = crate::R; -#[doc = "Register `UINIT` writer"] -pub type W = crate::W; -#[doc = "Field `INIT` reader - INIT"] -pub type InitR = crate::FieldReader; -#[doc = "Field `INIT` writer - INIT"] -pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - INIT"] - #[inline(always)] - pub fn init(&self) -> InitR { - InitR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - INIT"] - #[inline(always)] - pub fn init(&mut self) -> InitW { - InitW::new(self, 0) - } -} -#[doc = "Upper Initialization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uinit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uinit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UinitSpec; -impl crate::RegisterSpec for UinitSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`uinit::R`](R) reader structure"] -impl crate::Readable for UinitSpec {} -#[doc = "`write(|w| ..)` method takes [`uinit::W`](W) writer structure"] -impl crate::Writable for UinitSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets UINIT to value 0"] -impl crate::Resettable for UinitSpec {} diff --git a/mcxa276-pac/src/eqdc0/umod.rs b/mcxa276-pac/src/eqdc0/umod.rs deleted file mode 100644 index d27df9085..000000000 --- a/mcxa276-pac/src/eqdc0/umod.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `UMOD` reader"] -pub type R = crate::R; -#[doc = "Register `UMOD` writer"] -pub type W = crate::W; -#[doc = "Field `MOD` reader - MOD"] -pub type ModR = crate::FieldReader; -#[doc = "Field `MOD` writer - MOD"] -pub type ModW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - MOD"] - #[inline(always)] - pub fn mod_(&self) -> ModR { - ModR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - MOD"] - #[inline(always)] - pub fn mod_(&mut self) -> ModW { - ModW::new(self, 0) - } -} -#[doc = "Upper Modulus Register\n\nYou can [`read`](crate::Reg::read) this register and get [`umod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`umod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UmodSpec; -impl crate::RegisterSpec for UmodSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`umod::R`](R) reader structure"] -impl crate::Readable for UmodSpec {} -#[doc = "`write(|w| ..)` method takes [`umod::W`](W) writer structure"] -impl crate::Writable for UmodSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets UMOD to value 0"] -impl crate::Resettable for UmodSpec {} diff --git a/mcxa276-pac/src/eqdc0/upos.rs b/mcxa276-pac/src/eqdc0/upos.rs deleted file mode 100644 index 6b0c64027..000000000 --- a/mcxa276-pac/src/eqdc0/upos.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `UPOS` reader"] -pub type R = crate::R; -#[doc = "Register `UPOS` writer"] -pub type W = crate::W; -#[doc = "Field `POS` reader - POS"] -pub type PosR = crate::FieldReader; -#[doc = "Field `POS` writer - POS"] -pub type PosW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - POS"] - #[inline(always)] - pub fn pos(&self) -> PosR { - PosR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - POS"] - #[inline(always)] - pub fn pos(&mut self) -> PosW { - PosW::new(self, 0) - } -} -#[doc = "Upper Position Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`upos::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`upos::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UposSpec; -impl crate::RegisterSpec for UposSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`upos::R`](R) reader structure"] -impl crate::Readable for UposSpec {} -#[doc = "`write(|w| ..)` method takes [`upos::W`](W) writer structure"] -impl crate::Writable for UposSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets UPOS to value 0"] -impl crate::Resettable for UposSpec {} diff --git a/mcxa276-pac/src/eqdc0/uposh.rs b/mcxa276-pac/src/eqdc0/uposh.rs deleted file mode 100644 index bc8b94910..000000000 --- a/mcxa276-pac/src/eqdc0/uposh.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `UPOSH` reader"] -pub type R = crate::R; -#[doc = "Field `POSH` reader - POSH"] -pub type PoshR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - POSH"] - #[inline(always)] - pub fn posh(&self) -> PoshR { - PoshR::new(self.bits) - } -} -#[doc = "Upper Position Hold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UposhSpec; -impl crate::RegisterSpec for UposhSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`uposh::R`](R) reader structure"] -impl crate::Readable for UposhSpec {} -#[doc = "`reset()` method sets UPOSH to value 0"] -impl crate::Resettable for UposhSpec {} diff --git a/mcxa276-pac/src/eqdc0/uposh1_uposh1.rs b/mcxa276-pac/src/eqdc0/uposh1_uposh1.rs deleted file mode 100644 index ccda5f8f8..000000000 --- a/mcxa276-pac/src/eqdc0/uposh1_uposh1.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `UPOSH1` reader"] -pub type R = crate::R; -#[doc = "Field `UPOSH1` reader - UPOSH1"] -pub type Uposh1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - UPOSH1"] - #[inline(always)] - pub fn uposh1(&self) -> Uposh1R { - Uposh1R::new(self.bits) - } -} -#[doc = "Upper Position Holder Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh1_uposh1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Uposh1Uposh1Spec; -impl crate::RegisterSpec for Uposh1Uposh1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`uposh1_uposh1::R`](R) reader structure"] -impl crate::Readable for Uposh1Uposh1Spec {} -#[doc = "`reset()` method sets UPOSH1 to value 0"] -impl crate::Resettable for Uposh1Uposh1Spec {} diff --git a/mcxa276-pac/src/eqdc0/uposh2_uposh2.rs b/mcxa276-pac/src/eqdc0/uposh2_uposh2.rs deleted file mode 100644 index a26dbcdf8..000000000 --- a/mcxa276-pac/src/eqdc0/uposh2_uposh2.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `UPOSH2` reader"] -pub type R = crate::R; -#[doc = "Field `UPOSH2` reader - UPOSH2"] -pub type Uposh2R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - UPOSH2"] - #[inline(always)] - pub fn uposh2(&self) -> Uposh2R { - Uposh2R::new(self.bits) - } -} -#[doc = "Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh2_uposh2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Uposh2Uposh2Spec; -impl crate::RegisterSpec for Uposh2Uposh2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`uposh2_uposh2::R`](R) reader structure"] -impl crate::Readable for Uposh2Uposh2Spec {} -#[doc = "`reset()` method sets UPOSH2 to value 0"] -impl crate::Resettable for Uposh2Uposh2Spec {} diff --git a/mcxa276-pac/src/eqdc0/uposh3_uposh3.rs b/mcxa276-pac/src/eqdc0/uposh3_uposh3.rs deleted file mode 100644 index 5d2f4a77d..000000000 --- a/mcxa276-pac/src/eqdc0/uposh3_uposh3.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `UPOSH3` reader"] -pub type R = crate::R; -#[doc = "Field `UPOSH3` reader - UPOSH3"] -pub type Uposh3R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - UPOSH3"] - #[inline(always)] - pub fn uposh3(&self) -> Uposh3R { - Uposh3R::new(self.bits) - } -} -#[doc = "Upper Position Holder Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`uposh3_uposh3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Uposh3Uposh3Spec; -impl crate::RegisterSpec for Uposh3Uposh3Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`uposh3_uposh3::R`](R) reader structure"] -impl crate::Readable for Uposh3Uposh3Spec {} -#[doc = "`reset()` method sets UPOSH3 to value 0"] -impl crate::Resettable for Uposh3Uposh3Spec {} diff --git a/mcxa276-pac/src/eqdc0/uverid.rs b/mcxa276-pac/src/eqdc0/uverid.rs deleted file mode 100644 index 23baa3db6..000000000 --- a/mcxa276-pac/src/eqdc0/uverid.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `UVERID` reader"] -pub type R = crate::R; -#[doc = "Field `UVERID` reader - UVERID"] -pub type UveridR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - UVERID"] - #[inline(always)] - pub fn uverid(&self) -> UveridR { - UveridR::new(self.bits) - } -} -#[doc = "Upper VERID\n\nYou can [`read`](crate::Reg::read) this register and get [`uverid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UveridSpec; -impl crate::RegisterSpec for UveridSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`uverid::R`](R) reader structure"] -impl crate::Readable for UveridSpec {} -#[doc = "`reset()` method sets UVERID to value 0x01"] -impl crate::Resettable for UveridSpec { - const RESET_VALUE: u16 = 0x01; -} diff --git a/mcxa276-pac/src/eqdc0/wtr.rs b/mcxa276-pac/src/eqdc0/wtr.rs deleted file mode 100644 index 75f973d46..000000000 --- a/mcxa276-pac/src/eqdc0/wtr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `WTR` reader"] -pub type R = crate::R; -#[doc = "Register `WTR` writer"] -pub type W = crate::W; -#[doc = "Field `WDOG` reader - WDOG"] -pub type WdogR = crate::FieldReader; -#[doc = "Field `WDOG` writer - WDOG"] -pub type WdogW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - WDOG"] - #[inline(always)] - pub fn wdog(&self) -> WdogR { - WdogR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - WDOG"] - #[inline(always)] - pub fn wdog(&mut self) -> WdogW { - WdogW::new(self, 0) - } -} -#[doc = "Watchdog Timeout Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WtrSpec; -impl crate::RegisterSpec for WtrSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`wtr::R`](R) reader structure"] -impl crate::Readable for WtrSpec {} -#[doc = "`write(|w| ..)` method takes [`wtr::W`](W) writer structure"] -impl crate::Writable for WtrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WTR to value 0"] -impl crate::Resettable for WtrSpec {} diff --git a/mcxa276-pac/src/erm0.rs b/mcxa276-pac/src/erm0.rs deleted file mode 100644 index 61516f9c6..000000000 --- a/mcxa276-pac/src/erm0.rs +++ /dev/null @@ -1,75 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - cr0: Cr0, - _reserved1: [u8; 0x0c], - sr0: Sr0, - _reserved2: [u8; 0xec], - ear0: Ear0, - syn0: Syn0, - corr_err_cnt0: CorrErrCnt0, - _reserved5: [u8; 0x0c], - corr_err_cnt1: CorrErrCnt1, -} -impl RegisterBlock { - #[doc = "0x00 - ERM Configuration Register 0"] - #[inline(always)] - pub const fn cr0(&self) -> &Cr0 { - &self.cr0 - } - #[doc = "0x10 - ERM Status Register 0"] - #[inline(always)] - pub const fn sr0(&self) -> &Sr0 { - &self.sr0 - } - #[doc = "0x100 - ERM Memory 0 Error Address Register"] - #[inline(always)] - pub const fn ear0(&self) -> &Ear0 { - &self.ear0 - } - #[doc = "0x104 - ERM Memory 0 Syndrome Register"] - #[inline(always)] - pub const fn syn0(&self) -> &Syn0 { - &self.syn0 - } - #[doc = "0x108 - ERM Memory 0 Correctable Error Count Register"] - #[inline(always)] - pub const fn corr_err_cnt0(&self) -> &CorrErrCnt0 { - &self.corr_err_cnt0 - } - #[doc = "0x118 - ERM Memory 1 Correctable Error Count Register"] - #[inline(always)] - pub const fn corr_err_cnt1(&self) -> &CorrErrCnt1 { - &self.corr_err_cnt1 - } -} -#[doc = "CR0 (rw) register accessor: ERM Configuration Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr0`] module"] -#[doc(alias = "CR0")] -pub type Cr0 = crate::Reg; -#[doc = "ERM Configuration Register 0"] -pub mod cr0; -#[doc = "SR0 (rw) register accessor: ERM Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr0`] module"] -#[doc(alias = "SR0")] -pub type Sr0 = crate::Reg; -#[doc = "ERM Status Register 0"] -pub mod sr0; -#[doc = "EAR0 (r) register accessor: ERM Memory 0 Error Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ear0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ear0`] module"] -#[doc(alias = "EAR0")] -pub type Ear0 = crate::Reg; -#[doc = "ERM Memory 0 Error Address Register"] -pub mod ear0; -#[doc = "SYN0 (r) register accessor: ERM Memory 0 Syndrome Register\n\nYou can [`read`](crate::Reg::read) this register and get [`syn0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syn0`] module"] -#[doc(alias = "SYN0")] -pub type Syn0 = crate::Reg; -#[doc = "ERM Memory 0 Syndrome Register"] -pub mod syn0; -#[doc = "CORR_ERR_CNT0 (rw) register accessor: ERM Memory 0 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@corr_err_cnt0`] module"] -#[doc(alias = "CORR_ERR_CNT0")] -pub type CorrErrCnt0 = crate::Reg; -#[doc = "ERM Memory 0 Correctable Error Count Register"] -pub mod corr_err_cnt0; -#[doc = "CORR_ERR_CNT1 (rw) register accessor: ERM Memory 1 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@corr_err_cnt1`] module"] -#[doc(alias = "CORR_ERR_CNT1")] -pub type CorrErrCnt1 = crate::Reg; -#[doc = "ERM Memory 1 Correctable Error Count Register"] -pub mod corr_err_cnt1; diff --git a/mcxa276-pac/src/erm0/corr_err_cnt0.rs b/mcxa276-pac/src/erm0/corr_err_cnt0.rs deleted file mode 100644 index 4cc41ae4c..000000000 --- a/mcxa276-pac/src/erm0/corr_err_cnt0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CORR_ERR_CNT0` reader"] -pub type R = crate::R; -#[doc = "Register `CORR_ERR_CNT0` writer"] -pub type W = crate::W; -#[doc = "Field `COUNT` reader - Memory n Correctable Error Count"] -pub type CountR = crate::FieldReader; -#[doc = "Field `COUNT` writer - Memory n Correctable Error Count"] -pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Memory n Correctable Error Count"] - #[inline(always)] - pub fn count(&self) -> CountR { - CountR::new((self.bits & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Memory n Correctable Error Count"] - #[inline(always)] - pub fn count(&mut self) -> CountW { - CountW::new(self, 0) - } -} -#[doc = "ERM Memory 0 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CorrErrCnt0Spec; -impl crate::RegisterSpec for CorrErrCnt0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`corr_err_cnt0::R`](R) reader structure"] -impl crate::Readable for CorrErrCnt0Spec {} -#[doc = "`write(|w| ..)` method takes [`corr_err_cnt0::W`](W) writer structure"] -impl crate::Writable for CorrErrCnt0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CORR_ERR_CNT0 to value 0"] -impl crate::Resettable for CorrErrCnt0Spec {} diff --git a/mcxa276-pac/src/erm0/corr_err_cnt1.rs b/mcxa276-pac/src/erm0/corr_err_cnt1.rs deleted file mode 100644 index 73c5cbbaf..000000000 --- a/mcxa276-pac/src/erm0/corr_err_cnt1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CORR_ERR_CNT1` reader"] -pub type R = crate::R; -#[doc = "Register `CORR_ERR_CNT1` writer"] -pub type W = crate::W; -#[doc = "Field `COUNT` reader - Memory n Correctable Error Count"] -pub type CountR = crate::FieldReader; -#[doc = "Field `COUNT` writer - Memory n Correctable Error Count"] -pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Memory n Correctable Error Count"] - #[inline(always)] - pub fn count(&self) -> CountR { - CountR::new((self.bits & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Memory n Correctable Error Count"] - #[inline(always)] - pub fn count(&mut self) -> CountW { - CountW::new(self, 0) - } -} -#[doc = "ERM Memory 1 Correctable Error Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`corr_err_cnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`corr_err_cnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CorrErrCnt1Spec; -impl crate::RegisterSpec for CorrErrCnt1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`corr_err_cnt1::R`](R) reader structure"] -impl crate::Readable for CorrErrCnt1Spec {} -#[doc = "`write(|w| ..)` method takes [`corr_err_cnt1::W`](W) writer structure"] -impl crate::Writable for CorrErrCnt1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CORR_ERR_CNT1 to value 0"] -impl crate::Resettable for CorrErrCnt1Spec {} diff --git a/mcxa276-pac/src/erm0/cr0.rs b/mcxa276-pac/src/erm0/cr0.rs deleted file mode 100644 index 5bb94e07c..000000000 --- a/mcxa276-pac/src/erm0/cr0.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `CR0` reader"] -pub type R = crate::R; -#[doc = "Register `CR0` writer"] -pub type W = crate::W; -#[doc = "ENCIE1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Encie1 { - #[doc = "0: Interrupt notification of Memory 1 non-correctable error events is disabled."] - Disable = 0, - #[doc = "1: Interrupt notification of Memory 1 non-correctable error events is enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Encie1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENCIE1` reader - ENCIE1"] -pub type Encie1R = crate::BitReader; -impl Encie1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Encie1 { - match self.bits { - false => Encie1::Disable, - true => Encie1::Enable, - } - } - #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Encie1::Disable - } - #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Encie1::Enable - } -} -#[doc = "Field `ENCIE1` writer - ENCIE1"] -pub type Encie1W<'a, REG> = crate::BitWriter<'a, REG, Encie1>; -impl<'a, REG> Encie1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Encie1::Disable) - } - #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Encie1::Enable) - } -} -#[doc = "ESCIE1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Escie1 { - #[doc = "0: Interrupt notification of Memory 1 single-bit correction events is disabled."] - Disable = 0, - #[doc = "1: Interrupt notification of Memory 1 single-bit correction events is enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Escie1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ESCIE1` reader - ESCIE1"] -pub type Escie1R = crate::BitReader; -impl Escie1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Escie1 { - match self.bits { - false => Escie1::Disable, - true => Escie1::Enable, - } - } - #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Escie1::Disable - } - #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Escie1::Enable - } -} -#[doc = "Field `ESCIE1` writer - ESCIE1"] -pub type Escie1W<'a, REG> = crate::BitWriter<'a, REG, Escie1>; -impl<'a, REG> Escie1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Escie1::Disable) - } - #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Escie1::Enable) - } -} -#[doc = "ENCIE0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Encie0 { - #[doc = "0: Interrupt notification of Memory 0 non-correctable error events is disabled."] - Disable = 0, - #[doc = "1: Interrupt notification of Memory 0 non-correctable error events is enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Encie0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENCIE0` reader - ENCIE0"] -pub type Encie0R = crate::BitReader; -impl Encie0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Encie0 { - match self.bits { - false => Encie0::Disable, - true => Encie0::Enable, - } - } - #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Encie0::Disable - } - #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Encie0::Enable - } -} -#[doc = "Field `ENCIE0` writer - ENCIE0"] -pub type Encie0W<'a, REG> = crate::BitWriter<'a, REG, Encie0>; -impl<'a, REG> Encie0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Encie0::Disable) - } - #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Encie0::Enable) - } -} -#[doc = "ESCIE0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Escie0 { - #[doc = "0: Interrupt notification of Memory 0 single-bit correction events is disabled."] - Disable = 0, - #[doc = "1: Interrupt notification of Memory 0 single-bit correction events is enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Escie0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ESCIE0` reader - ESCIE0"] -pub type Escie0R = crate::BitReader; -impl Escie0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Escie0 { - match self.bits { - false => Escie0::Disable, - true => Escie0::Enable, - } - } - #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Escie0::Disable - } - #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Escie0::Enable - } -} -#[doc = "Field `ESCIE0` writer - ESCIE0"] -pub type Escie0W<'a, REG> = crate::BitWriter<'a, REG, Escie0>; -impl<'a, REG> Escie0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Escie0::Disable) - } - #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Escie0::Enable) - } -} -impl R { - #[doc = "Bit 26 - ENCIE1"] - #[inline(always)] - pub fn encie1(&self) -> Encie1R { - Encie1R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - ESCIE1"] - #[inline(always)] - pub fn escie1(&self) -> Escie1R { - Escie1R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 30 - ENCIE0"] - #[inline(always)] - pub fn encie0(&self) -> Encie0R { - Encie0R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - ESCIE0"] - #[inline(always)] - pub fn escie0(&self) -> Escie0R { - Escie0R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 26 - ENCIE1"] - #[inline(always)] - pub fn encie1(&mut self) -> Encie1W { - Encie1W::new(self, 26) - } - #[doc = "Bit 27 - ESCIE1"] - #[inline(always)] - pub fn escie1(&mut self) -> Escie1W { - Escie1W::new(self, 27) - } - #[doc = "Bit 30 - ENCIE0"] - #[inline(always)] - pub fn encie0(&mut self) -> Encie0W { - Encie0W::new(self, 30) - } - #[doc = "Bit 31 - ESCIE0"] - #[inline(always)] - pub fn escie0(&mut self) -> Escie0W { - Escie0W::new(self, 31) - } -} -#[doc = "ERM Configuration Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cr0Spec; -impl crate::RegisterSpec for Cr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cr0::R`](R) reader structure"] -impl crate::Readable for Cr0Spec {} -#[doc = "`write(|w| ..)` method takes [`cr0::W`](W) writer structure"] -impl crate::Writable for Cr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CR0 to value 0"] -impl crate::Resettable for Cr0Spec {} diff --git a/mcxa276-pac/src/erm0/ear0.rs b/mcxa276-pac/src/erm0/ear0.rs deleted file mode 100644 index 94c672c4f..000000000 --- a/mcxa276-pac/src/erm0/ear0.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `EAR0` reader"] -pub type R = crate::R; -#[doc = "Field `EAR` reader - EAR"] -pub type EarR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - EAR"] - #[inline(always)] - pub fn ear(&self) -> EarR { - EarR::new(self.bits) - } -} -#[doc = "ERM Memory 0 Error Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ear0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ear0Spec; -impl crate::RegisterSpec for Ear0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ear0::R`](R) reader structure"] -impl crate::Readable for Ear0Spec {} -#[doc = "`reset()` method sets EAR0 to value 0"] -impl crate::Resettable for Ear0Spec {} diff --git a/mcxa276-pac/src/erm0/sr0.rs b/mcxa276-pac/src/erm0/sr0.rs deleted file mode 100644 index 6a8ff0995..000000000 --- a/mcxa276-pac/src/erm0/sr0.rs +++ /dev/null @@ -1,274 +0,0 @@ -#[doc = "Register `SR0` reader"] -pub type R = crate::R; -#[doc = "Register `SR0` writer"] -pub type W = crate::W; -#[doc = "NCE1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nce1 { - #[doc = "0: No non-correctable error event on Memory 1 detected."] - NoError = 0, - #[doc = "1: Non-correctable error event on Memory 1 detected."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nce1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NCE1` reader - NCE1"] -pub type Nce1R = crate::BitReader; -impl Nce1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nce1 { - match self.bits { - false => Nce1::NoError, - true => Nce1::Error, - } - } - #[doc = "No non-correctable error event on Memory 1 detected."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Nce1::NoError - } - #[doc = "Non-correctable error event on Memory 1 detected."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Nce1::Error - } -} -#[doc = "Field `NCE1` writer - NCE1"] -pub type Nce1W<'a, REG> = crate::BitWriter1C<'a, REG, Nce1>; -impl<'a, REG> Nce1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No non-correctable error event on Memory 1 detected."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Nce1::NoError) - } - #[doc = "Non-correctable error event on Memory 1 detected."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Nce1::Error) - } -} -#[doc = "SBC1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sbc1 { - #[doc = "0: No single-bit correction event on Memory 1 detected."] - NoEvent = 0, - #[doc = "1: Single-bit correction event on Memory 1 detected."] - Event = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sbc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SBC1` reader - SBC1"] -pub type Sbc1R = crate::BitReader; -impl Sbc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sbc1 { - match self.bits { - false => Sbc1::NoEvent, - true => Sbc1::Event, - } - } - #[doc = "No single-bit correction event on Memory 1 detected."] - #[inline(always)] - pub fn is_no_event(&self) -> bool { - *self == Sbc1::NoEvent - } - #[doc = "Single-bit correction event on Memory 1 detected."] - #[inline(always)] - pub fn is_event(&self) -> bool { - *self == Sbc1::Event - } -} -#[doc = "Field `SBC1` writer - SBC1"] -pub type Sbc1W<'a, REG> = crate::BitWriter1C<'a, REG, Sbc1>; -impl<'a, REG> Sbc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No single-bit correction event on Memory 1 detected."] - #[inline(always)] - pub fn no_event(self) -> &'a mut crate::W { - self.variant(Sbc1::NoEvent) - } - #[doc = "Single-bit correction event on Memory 1 detected."] - #[inline(always)] - pub fn event(self) -> &'a mut crate::W { - self.variant(Sbc1::Event) - } -} -#[doc = "NCE0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nce0 { - #[doc = "0: No non-correctable error event on Memory 0 detected."] - NoError = 0, - #[doc = "1: Non-correctable error event on Memory 0 detected."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nce0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NCE0` reader - NCE0"] -pub type Nce0R = crate::BitReader; -impl Nce0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nce0 { - match self.bits { - false => Nce0::NoError, - true => Nce0::Error, - } - } - #[doc = "No non-correctable error event on Memory 0 detected."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Nce0::NoError - } - #[doc = "Non-correctable error event on Memory 0 detected."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Nce0::Error - } -} -#[doc = "Field `NCE0` writer - NCE0"] -pub type Nce0W<'a, REG> = crate::BitWriter1C<'a, REG, Nce0>; -impl<'a, REG> Nce0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No non-correctable error event on Memory 0 detected."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Nce0::NoError) - } - #[doc = "Non-correctable error event on Memory 0 detected."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Nce0::Error) - } -} -#[doc = "SBC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sbc0 { - #[doc = "0: No single-bit correction event on Memory 0 detected."] - NoEvent = 0, - #[doc = "1: Single-bit correction event on Memory 0 detected."] - Event = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sbc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SBC0` reader - SBC0"] -pub type Sbc0R = crate::BitReader; -impl Sbc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sbc0 { - match self.bits { - false => Sbc0::NoEvent, - true => Sbc0::Event, - } - } - #[doc = "No single-bit correction event on Memory 0 detected."] - #[inline(always)] - pub fn is_no_event(&self) -> bool { - *self == Sbc0::NoEvent - } - #[doc = "Single-bit correction event on Memory 0 detected."] - #[inline(always)] - pub fn is_event(&self) -> bool { - *self == Sbc0::Event - } -} -#[doc = "Field `SBC0` writer - SBC0"] -pub type Sbc0W<'a, REG> = crate::BitWriter1C<'a, REG, Sbc0>; -impl<'a, REG> Sbc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No single-bit correction event on Memory 0 detected."] - #[inline(always)] - pub fn no_event(self) -> &'a mut crate::W { - self.variant(Sbc0::NoEvent) - } - #[doc = "Single-bit correction event on Memory 0 detected."] - #[inline(always)] - pub fn event(self) -> &'a mut crate::W { - self.variant(Sbc0::Event) - } -} -impl R { - #[doc = "Bit 26 - NCE1"] - #[inline(always)] - pub fn nce1(&self) -> Nce1R { - Nce1R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - SBC1"] - #[inline(always)] - pub fn sbc1(&self) -> Sbc1R { - Sbc1R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 30 - NCE0"] - #[inline(always)] - pub fn nce0(&self) -> Nce0R { - Nce0R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - SBC0"] - #[inline(always)] - pub fn sbc0(&self) -> Sbc0R { - Sbc0R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 26 - NCE1"] - #[inline(always)] - pub fn nce1(&mut self) -> Nce1W { - Nce1W::new(self, 26) - } - #[doc = "Bit 27 - SBC1"] - #[inline(always)] - pub fn sbc1(&mut self) -> Sbc1W { - Sbc1W::new(self, 27) - } - #[doc = "Bit 30 - NCE0"] - #[inline(always)] - pub fn nce0(&mut self) -> Nce0W { - Nce0W::new(self, 30) - } - #[doc = "Bit 31 - SBC0"] - #[inline(always)] - pub fn sbc0(&mut self) -> Sbc0W { - Sbc0W::new(self, 31) - } -} -#[doc = "ERM Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sr0Spec; -impl crate::RegisterSpec for Sr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sr0::R`](R) reader structure"] -impl crate::Readable for Sr0Spec {} -#[doc = "`write(|w| ..)` method takes [`sr0::W`](W) writer structure"] -impl crate::Writable for Sr0Spec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xcc00_0000; -} -#[doc = "`reset()` method sets SR0 to value 0"] -impl crate::Resettable for Sr0Spec {} diff --git a/mcxa276-pac/src/erm0/syn0.rs b/mcxa276-pac/src/erm0/syn0.rs deleted file mode 100644 index a869c7776..000000000 --- a/mcxa276-pac/src/erm0/syn0.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SYN0` reader"] -pub type R = crate::R; -#[doc = "Field `SYNDROME` reader - SYNDROME"] -pub type SyndromeR = crate::FieldReader; -impl R { - #[doc = "Bits 24:31 - SYNDROME"] - #[inline(always)] - pub fn syndrome(&self) -> SyndromeR { - SyndromeR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "ERM Memory 0 Syndrome Register\n\nYou can [`read`](crate::Reg::read) this register and get [`syn0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Syn0Spec; -impl crate::RegisterSpec for Syn0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`syn0::R`](R) reader structure"] -impl crate::Readable for Syn0Spec {} -#[doc = "`reset()` method sets SYN0 to value 0"] -impl crate::Resettable for Syn0Spec {} diff --git a/mcxa276-pac/src/flexio0.rs b/mcxa276-pac/src/flexio0.rs deleted file mode 100644 index b38b79569..000000000 --- a/mcxa276-pac/src/flexio0.rs +++ /dev/null @@ -1,556 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - ctrl: Ctrl, - pin: Pin, - shiftstat: Shiftstat, - shifterr: Shifterr, - timstat: Timstat, - _reserved7: [u8; 0x04], - shiftsien: Shiftsien, - shifteien: Shifteien, - timien: Timien, - _reserved10: [u8; 0x04], - shiftsden: Shiftsden, - _reserved11: [u8; 0x04], - timersden: Timersden, - _reserved12: [u8; 0x04], - shiftstate: Shiftstate, - _reserved13: [u8; 0x04], - trgstat: Trgstat, - trigien: Trigien, - pinstat: Pinstat, - pinien: Pinien, - pinren: Pinren, - pinfen: Pinfen, - pinoutd: Pinoutd, - pinoute: Pinoute, - pinoutdis: Pinoutdis, - pinoutclr: Pinoutclr, - pinoutset: Pinoutset, - pinouttog: Pinouttog, - _reserved25: [u8; 0x08], - shiftctl: [Shiftctl; 4], - _reserved26: [u8; 0x70], - shiftcfg: [Shiftcfg; 4], - _reserved27: [u8; 0xf0], - shiftbuf: [Shiftbuf; 4], - _reserved28: [u8; 0x70], - shiftbufbis: [Shiftbufbis; 4], - _reserved29: [u8; 0x70], - shiftbufbys: [Shiftbufbys; 4], - _reserved30: [u8; 0x70], - shiftbufbbs: [Shiftbufbbs; 4], - _reserved31: [u8; 0x70], - timctl: [Timctl; 4], - _reserved32: [u8; 0x70], - timcfg: [Timcfg; 4], - _reserved33: [u8; 0x70], - timcmp: [Timcmp; 4], - _reserved34: [u8; 0x0170], - shiftbufnbs: [Shiftbufnbs; 4], - _reserved35: [u8; 0x70], - shiftbufhws: [Shiftbufhws; 4], - _reserved36: [u8; 0x70], - shiftbufnis: [Shiftbufnis; 4], - _reserved37: [u8; 0x70], - shiftbufoes: [Shiftbufoes; 4], - _reserved38: [u8; 0x70], - shiftbufeos: [Shiftbufeos; 4], - _reserved39: [u8; 0x70], - shiftbufhbs: [Shiftbufhbs; 4], -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x08 - FLEXIO Control"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } - #[doc = "0x0c - Pin State"] - #[inline(always)] - pub const fn pin(&self) -> &Pin { - &self.pin - } - #[doc = "0x10 - Shifter Status"] - #[inline(always)] - pub const fn shiftstat(&self) -> &Shiftstat { - &self.shiftstat - } - #[doc = "0x14 - Shifter Error"] - #[inline(always)] - pub const fn shifterr(&self) -> &Shifterr { - &self.shifterr - } - #[doc = "0x18 - Timer Status Flag"] - #[inline(always)] - pub const fn timstat(&self) -> &Timstat { - &self.timstat - } - #[doc = "0x20 - Shifter Status Interrupt Enable"] - #[inline(always)] - pub const fn shiftsien(&self) -> &Shiftsien { - &self.shiftsien - } - #[doc = "0x24 - Shifter Error Interrupt Enable"] - #[inline(always)] - pub const fn shifteien(&self) -> &Shifteien { - &self.shifteien - } - #[doc = "0x28 - Timer Interrupt Enable"] - #[inline(always)] - pub const fn timien(&self) -> &Timien { - &self.timien - } - #[doc = "0x30 - Shifter Status DMA Enable"] - #[inline(always)] - pub const fn shiftsden(&self) -> &Shiftsden { - &self.shiftsden - } - #[doc = "0x38 - Timer Status DMA Enable"] - #[inline(always)] - pub const fn timersden(&self) -> &Timersden { - &self.timersden - } - #[doc = "0x40 - Shifter State"] - #[inline(always)] - pub const fn shiftstate(&self) -> &Shiftstate { - &self.shiftstate - } - #[doc = "0x48 - Trigger Status"] - #[inline(always)] - pub const fn trgstat(&self) -> &Trgstat { - &self.trgstat - } - #[doc = "0x4c - External Trigger Interrupt Enable"] - #[inline(always)] - pub const fn trigien(&self) -> &Trigien { - &self.trigien - } - #[doc = "0x50 - Pin Status"] - #[inline(always)] - pub const fn pinstat(&self) -> &Pinstat { - &self.pinstat - } - #[doc = "0x54 - Pin Interrupt Enable"] - #[inline(always)] - pub const fn pinien(&self) -> &Pinien { - &self.pinien - } - #[doc = "0x58 - Pin Rising Edge Enable"] - #[inline(always)] - pub const fn pinren(&self) -> &Pinren { - &self.pinren - } - #[doc = "0x5c - Pin Falling Edge Enable"] - #[inline(always)] - pub const fn pinfen(&self) -> &Pinfen { - &self.pinfen - } - #[doc = "0x60 - Pin Output Data"] - #[inline(always)] - pub const fn pinoutd(&self) -> &Pinoutd { - &self.pinoutd - } - #[doc = "0x64 - Pin Output Enable"] - #[inline(always)] - pub const fn pinoute(&self) -> &Pinoute { - &self.pinoute - } - #[doc = "0x68 - Pin Output Disable"] - #[inline(always)] - pub const fn pinoutdis(&self) -> &Pinoutdis { - &self.pinoutdis - } - #[doc = "0x6c - Pin Output Clear"] - #[inline(always)] - pub const fn pinoutclr(&self) -> &Pinoutclr { - &self.pinoutclr - } - #[doc = "0x70 - Pin Output Set"] - #[inline(always)] - pub const fn pinoutset(&self) -> &Pinoutset { - &self.pinoutset - } - #[doc = "0x74 - Pin Output Toggle"] - #[inline(always)] - pub const fn pinouttog(&self) -> &Pinouttog { - &self.pinouttog - } - #[doc = "0x80..0x90 - Shifter Control"] - #[inline(always)] - pub const fn shiftctl(&self, n: usize) -> &Shiftctl { - &self.shiftctl[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x80..0x90 - Shifter Control"] - #[inline(always)] - pub fn shiftctl_iter(&self) -> impl Iterator { - self.shiftctl.iter() - } - #[doc = "0x100..0x110 - Shifter Configuration"] - #[inline(always)] - pub const fn shiftcfg(&self, n: usize) -> &Shiftcfg { - &self.shiftcfg[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x100..0x110 - Shifter Configuration"] - #[inline(always)] - pub fn shiftcfg_iter(&self) -> impl Iterator { - self.shiftcfg.iter() - } - #[doc = "0x200..0x210 - Shifter Buffer"] - #[inline(always)] - pub const fn shiftbuf(&self, n: usize) -> &Shiftbuf { - &self.shiftbuf[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x200..0x210 - Shifter Buffer"] - #[inline(always)] - pub fn shiftbuf_iter(&self) -> impl Iterator { - self.shiftbuf.iter() - } - #[doc = "0x280..0x290 - Shifter Buffer Bit Swapped"] - #[inline(always)] - pub const fn shiftbufbis(&self, n: usize) -> &Shiftbufbis { - &self.shiftbufbis[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x280..0x290 - Shifter Buffer Bit Swapped"] - #[inline(always)] - pub fn shiftbufbis_iter(&self) -> impl Iterator { - self.shiftbufbis.iter() - } - #[doc = "0x300..0x310 - Shifter Buffer Byte Swapped"] - #[inline(always)] - pub const fn shiftbufbys(&self, n: usize) -> &Shiftbufbys { - &self.shiftbufbys[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x300..0x310 - Shifter Buffer Byte Swapped"] - #[inline(always)] - pub fn shiftbufbys_iter(&self) -> impl Iterator { - self.shiftbufbys.iter() - } - #[doc = "0x380..0x390 - Shifter Buffer Bit Byte Swapped"] - #[inline(always)] - pub const fn shiftbufbbs(&self, n: usize) -> &Shiftbufbbs { - &self.shiftbufbbs[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x380..0x390 - Shifter Buffer Bit Byte Swapped"] - #[inline(always)] - pub fn shiftbufbbs_iter(&self) -> impl Iterator { - self.shiftbufbbs.iter() - } - #[doc = "0x400..0x410 - Timer Control"] - #[inline(always)] - pub const fn timctl(&self, n: usize) -> &Timctl { - &self.timctl[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x400..0x410 - Timer Control"] - #[inline(always)] - pub fn timctl_iter(&self) -> impl Iterator { - self.timctl.iter() - } - #[doc = "0x480..0x490 - Timer Configuration"] - #[inline(always)] - pub const fn timcfg(&self, n: usize) -> &Timcfg { - &self.timcfg[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x480..0x490 - Timer Configuration"] - #[inline(always)] - pub fn timcfg_iter(&self) -> impl Iterator { - self.timcfg.iter() - } - #[doc = "0x500..0x510 - Timer Compare"] - #[inline(always)] - pub const fn timcmp(&self, n: usize) -> &Timcmp { - &self.timcmp[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x500..0x510 - Timer Compare"] - #[inline(always)] - pub fn timcmp_iter(&self) -> impl Iterator { - self.timcmp.iter() - } - #[doc = "0x680..0x690 - Shifter Buffer Nibble Byte Swapped"] - #[inline(always)] - pub const fn shiftbufnbs(&self, n: usize) -> &Shiftbufnbs { - &self.shiftbufnbs[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x680..0x690 - Shifter Buffer Nibble Byte Swapped"] - #[inline(always)] - pub fn shiftbufnbs_iter(&self) -> impl Iterator { - self.shiftbufnbs.iter() - } - #[doc = "0x700..0x710 - Shifter Buffer Halfword Swapped"] - #[inline(always)] - pub const fn shiftbufhws(&self, n: usize) -> &Shiftbufhws { - &self.shiftbufhws[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x700..0x710 - Shifter Buffer Halfword Swapped"] - #[inline(always)] - pub fn shiftbufhws_iter(&self) -> impl Iterator { - self.shiftbufhws.iter() - } - #[doc = "0x780..0x790 - Shifter Buffer Nibble Swapped"] - #[inline(always)] - pub const fn shiftbufnis(&self, n: usize) -> &Shiftbufnis { - &self.shiftbufnis[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x780..0x790 - Shifter Buffer Nibble Swapped"] - #[inline(always)] - pub fn shiftbufnis_iter(&self) -> impl Iterator { - self.shiftbufnis.iter() - } - #[doc = "0x800..0x810 - Shifter Buffer Odd Even Swapped"] - #[inline(always)] - pub const fn shiftbufoes(&self, n: usize) -> &Shiftbufoes { - &self.shiftbufoes[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x800..0x810 - Shifter Buffer Odd Even Swapped"] - #[inline(always)] - pub fn shiftbufoes_iter(&self) -> impl Iterator { - self.shiftbufoes.iter() - } - #[doc = "0x880..0x890 - Shifter Buffer Even Odd Swapped"] - #[inline(always)] - pub const fn shiftbufeos(&self, n: usize) -> &Shiftbufeos { - &self.shiftbufeos[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x880..0x890 - Shifter Buffer Even Odd Swapped"] - #[inline(always)] - pub fn shiftbufeos_iter(&self) -> impl Iterator { - self.shiftbufeos.iter() - } - #[doc = "0x900..0x910 - Shifter Buffer Halfword Byte Swapped"] - #[inline(always)] - pub const fn shiftbufhbs(&self, n: usize) -> &Shiftbufhbs { - &self.shiftbufhbs[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x900..0x910 - Shifter Buffer Halfword Byte Swapped"] - #[inline(always)] - pub fn shiftbufhbs_iter(&self) -> impl Iterator { - self.shiftbufhbs.iter() - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "CTRL (rw) register accessor: FLEXIO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "FLEXIO Control"] -pub mod ctrl; -#[doc = "PIN (r) register accessor: Pin State\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin`] module"] -#[doc(alias = "PIN")] -pub type Pin = crate::Reg; -#[doc = "Pin State"] -pub mod pin; -#[doc = "SHIFTSTAT (rw) register accessor: Shifter Status\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftstat`] module"] -#[doc(alias = "SHIFTSTAT")] -pub type Shiftstat = crate::Reg; -#[doc = "Shifter Status"] -pub mod shiftstat; -#[doc = "SHIFTERR (rw) register accessor: Shifter Error\n\nYou can [`read`](crate::Reg::read) this register and get [`shifterr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifterr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shifterr`] module"] -#[doc(alias = "SHIFTERR")] -pub type Shifterr = crate::Reg; -#[doc = "Shifter Error"] -pub mod shifterr; -#[doc = "TIMSTAT (rw) register accessor: Timer Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`timstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timstat`] module"] -#[doc(alias = "TIMSTAT")] -pub type Timstat = crate::Reg; -#[doc = "Timer Status Flag"] -pub mod timstat; -#[doc = "SHIFTSIEN (rw) register accessor: Shifter Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftsien`] module"] -#[doc(alias = "SHIFTSIEN")] -pub type Shiftsien = crate::Reg; -#[doc = "Shifter Status Interrupt Enable"] -pub mod shiftsien; -#[doc = "SHIFTEIEN (rw) register accessor: Shifter Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shifteien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifteien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shifteien`] module"] -#[doc(alias = "SHIFTEIEN")] -pub type Shifteien = crate::Reg; -#[doc = "Shifter Error Interrupt Enable"] -pub mod shifteien; -#[doc = "TIMIEN (rw) register accessor: Timer Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timien`] module"] -#[doc(alias = "TIMIEN")] -pub type Timien = crate::Reg; -#[doc = "Timer Interrupt Enable"] -pub mod timien; -#[doc = "SHIFTSDEN (rw) register accessor: Shifter Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsden::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsden::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftsden`] module"] -#[doc(alias = "SHIFTSDEN")] -pub type Shiftsden = crate::Reg; -#[doc = "Shifter Status DMA Enable"] -pub mod shiftsden; -#[doc = "TIMERSDEN (rw) register accessor: Timer Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timersden::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timersden::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timersden`] module"] -#[doc(alias = "TIMERSDEN")] -pub type Timersden = crate::Reg; -#[doc = "Timer Status DMA Enable"] -pub mod timersden; -#[doc = "SHIFTSTATE (rw) register accessor: Shifter State\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftstate`] module"] -#[doc(alias = "SHIFTSTATE")] -pub type Shiftstate = crate::Reg; -#[doc = "Shifter State"] -pub mod shiftstate; -#[doc = "TRGSTAT (rw) register accessor: Trigger Status\n\nYou can [`read`](crate::Reg::read) this register and get [`trgstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trgstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trgstat`] module"] -#[doc(alias = "TRGSTAT")] -pub type Trgstat = crate::Reg; -#[doc = "Trigger Status"] -pub mod trgstat; -#[doc = "TRIGIEN (rw) register accessor: External Trigger Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`trigien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigien`] module"] -#[doc(alias = "TRIGIEN")] -pub type Trigien = crate::Reg; -#[doc = "External Trigger Interrupt Enable"] -pub mod trigien; -#[doc = "PINSTAT (rw) register accessor: Pin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pinstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinstat`] module"] -#[doc(alias = "PINSTAT")] -pub type Pinstat = crate::Reg; -#[doc = "Pin Status"] -pub mod pinstat; -#[doc = "PINIEN (rw) register accessor: Pin Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinien`] module"] -#[doc(alias = "PINIEN")] -pub type Pinien = crate::Reg; -#[doc = "Pin Interrupt Enable"] -pub mod pinien; -#[doc = "PINREN (rw) register accessor: Pin Rising Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinren`] module"] -#[doc(alias = "PINREN")] -pub type Pinren = crate::Reg; -#[doc = "Pin Rising Edge Enable"] -pub mod pinren; -#[doc = "PINFEN (rw) register accessor: Pin Falling Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinfen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinfen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinfen`] module"] -#[doc(alias = "PINFEN")] -pub type Pinfen = crate::Reg; -#[doc = "Pin Falling Edge Enable"] -pub mod pinfen; -#[doc = "PINOUTD (rw) register accessor: Pin Output Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutd`] module"] -#[doc(alias = "PINOUTD")] -pub type Pinoutd = crate::Reg; -#[doc = "Pin Output Data"] -pub mod pinoutd; -#[doc = "PINOUTE (rw) register accessor: Pin Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoute::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoute::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoute`] module"] -#[doc(alias = "PINOUTE")] -pub type Pinoute = crate::Reg; -#[doc = "Pin Output Enable"] -pub mod pinoute; -#[doc = "PINOUTDIS (rw) register accessor: Pin Output Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutdis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutdis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutdis`] module"] -#[doc(alias = "PINOUTDIS")] -pub type Pinoutdis = crate::Reg; -#[doc = "Pin Output Disable"] -pub mod pinoutdis; -#[doc = "PINOUTCLR (rw) register accessor: Pin Output Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutclr`] module"] -#[doc(alias = "PINOUTCLR")] -pub type Pinoutclr = crate::Reg; -#[doc = "Pin Output Clear"] -pub mod pinoutclr; -#[doc = "PINOUTSET (rw) register accessor: Pin Output Set\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinoutset`] module"] -#[doc(alias = "PINOUTSET")] -pub type Pinoutset = crate::Reg; -#[doc = "Pin Output Set"] -pub mod pinoutset; -#[doc = "PINOUTTOG (rw) register accessor: Pin Output Toggle\n\nYou can [`read`](crate::Reg::read) this register and get [`pinouttog::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinouttog::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pinouttog`] module"] -#[doc(alias = "PINOUTTOG")] -pub type Pinouttog = crate::Reg; -#[doc = "Pin Output Toggle"] -pub mod pinouttog; -#[doc = "SHIFTCTL (rw) register accessor: Shifter Control\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftctl`] module"] -#[doc(alias = "SHIFTCTL")] -pub type Shiftctl = crate::Reg; -#[doc = "Shifter Control"] -pub mod shiftctl; -#[doc = "SHIFTCFG (rw) register accessor: Shifter Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftcfg`] module"] -#[doc(alias = "SHIFTCFG")] -pub type Shiftcfg = crate::Reg; -#[doc = "Shifter Configuration"] -pub mod shiftcfg; -#[doc = "SHIFTBUF (rw) register accessor: Shifter Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbuf`] module"] -#[doc(alias = "SHIFTBUF")] -pub type Shiftbuf = crate::Reg; -#[doc = "Shifter Buffer"] -pub mod shiftbuf; -#[doc = "SHIFTBUFBIS (rw) register accessor: Shifter Buffer Bit Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufbis`] module"] -#[doc(alias = "SHIFTBUFBIS")] -pub type Shiftbufbis = crate::Reg; -#[doc = "Shifter Buffer Bit Swapped"] -pub mod shiftbufbis; -#[doc = "SHIFTBUFBYS (rw) register accessor: Shifter Buffer Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbys::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbys::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufbys`] module"] -#[doc(alias = "SHIFTBUFBYS")] -pub type Shiftbufbys = crate::Reg; -#[doc = "Shifter Buffer Byte Swapped"] -pub mod shiftbufbys; -#[doc = "SHIFTBUFBBS (rw) register accessor: Shifter Buffer Bit Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbbs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbbs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufbbs`] module"] -#[doc(alias = "SHIFTBUFBBS")] -pub type Shiftbufbbs = crate::Reg; -#[doc = "Shifter Buffer Bit Byte Swapped"] -pub mod shiftbufbbs; -#[doc = "TIMCTL (rw) register accessor: Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`timctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timctl`] module"] -#[doc(alias = "TIMCTL")] -pub type Timctl = crate::Reg; -#[doc = "Timer Control"] -pub mod timctl; -#[doc = "TIMCFG (rw) register accessor: Timer Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`timcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timcfg`] module"] -#[doc(alias = "TIMCFG")] -pub type Timcfg = crate::Reg; -#[doc = "Timer Configuration"] -pub mod timcfg; -#[doc = "TIMCMP (rw) register accessor: Timer Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`timcmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timcmp`] module"] -#[doc(alias = "TIMCMP")] -pub type Timcmp = crate::Reg; -#[doc = "Timer Compare"] -pub mod timcmp; -#[doc = "SHIFTBUFNBS (rw) register accessor: Shifter Buffer Nibble Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnbs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnbs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufnbs`] module"] -#[doc(alias = "SHIFTBUFNBS")] -pub type Shiftbufnbs = crate::Reg; -#[doc = "Shifter Buffer Nibble Byte Swapped"] -pub mod shiftbufnbs; -#[doc = "SHIFTBUFHWS (rw) register accessor: Shifter Buffer Halfword Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhws::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhws::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufhws`] module"] -#[doc(alias = "SHIFTBUFHWS")] -pub type Shiftbufhws = crate::Reg; -#[doc = "Shifter Buffer Halfword Swapped"] -pub mod shiftbufhws; -#[doc = "SHIFTBUFNIS (rw) register accessor: Shifter Buffer Nibble Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufnis`] module"] -#[doc(alias = "SHIFTBUFNIS")] -pub type Shiftbufnis = crate::Reg; -#[doc = "Shifter Buffer Nibble Swapped"] -pub mod shiftbufnis; -#[doc = "SHIFTBUFOES (rw) register accessor: Shifter Buffer Odd Even Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufoes::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufoes::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufoes`] module"] -#[doc(alias = "SHIFTBUFOES")] -pub type Shiftbufoes = crate::Reg; -#[doc = "Shifter Buffer Odd Even Swapped"] -pub mod shiftbufoes; -#[doc = "SHIFTBUFEOS (rw) register accessor: Shifter Buffer Even Odd Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufeos::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufeos::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufeos`] module"] -#[doc(alias = "SHIFTBUFEOS")] -pub type Shiftbufeos = crate::Reg; -#[doc = "Shifter Buffer Even Odd Swapped"] -pub mod shiftbufeos; -#[doc = "SHIFTBUFHBS (rw) register accessor: Shifter Buffer Halfword Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhbs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhbs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftbufhbs`] module"] -#[doc(alias = "SHIFTBUFHBS")] -pub type Shiftbufhbs = crate::Reg; -#[doc = "Shifter Buffer Halfword Byte Swapped"] -pub mod shiftbufhbs; diff --git a/mcxa276-pac/src/flexio0/ctrl.rs b/mcxa276-pac/src/flexio0/ctrl.rs deleted file mode 100644 index 01255862b..000000000 --- a/mcxa276-pac/src/flexio0/ctrl.rs +++ /dev/null @@ -1,336 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "FLEXIO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexen { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXEN` reader - FLEXIO Enable"] -pub type FlexenR = crate::BitReader; -impl FlexenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexen { - match self.bits { - false => Flexen::Disable, - true => Flexen::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Flexen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Flexen::Enable - } -} -#[doc = "Field `FLEXEN` writer - FLEXIO Enable"] -pub type FlexenW<'a, REG> = crate::BitWriter<'a, REG, Flexen>; -impl<'a, REG> FlexenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Flexen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Flexen::Enable) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swrst { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swrst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWRST` reader - Software Reset"] -pub type SwrstR = crate::BitReader; -impl SwrstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swrst { - match self.bits { - false => Swrst::Disable, - true => Swrst::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Swrst::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Swrst::Enable - } -} -#[doc = "Field `SWRST` writer - Software Reset"] -pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG, Swrst>; -impl<'a, REG> SwrstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Swrst::Disable) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Swrst::Enable) - } -} -#[doc = "Fast Access\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fastacc { - #[doc = "0: Normal"] - Normal = 0, - #[doc = "1: Fast"] - Fast = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fastacc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FASTACC` reader - Fast Access"] -pub type FastaccR = crate::BitReader; -impl FastaccR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fastacc { - match self.bits { - false => Fastacc::Normal, - true => Fastacc::Fast, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == Fastacc::Normal - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_fast(&self) -> bool { - *self == Fastacc::Fast - } -} -#[doc = "Field `FASTACC` writer - Fast Access"] -pub type FastaccW<'a, REG> = crate::BitWriter<'a, REG, Fastacc>; -impl<'a, REG> FastaccW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(Fastacc::Normal) - } - #[doc = "Fast"] - #[inline(always)] - pub fn fast(self) -> &'a mut crate::W { - self.variant(Fastacc::Fast) - } -} -#[doc = "Debug Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dbge { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Emable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dbge) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBGE` reader - Debug Enable"] -pub type DbgeR = crate::BitReader; -impl DbgeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dbge { - match self.bits { - false => Dbge::Disable, - true => Dbge::Emable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Dbge::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_emable(&self) -> bool { - *self == Dbge::Emable - } -} -#[doc = "Field `DBGE` writer - Debug Enable"] -pub type DbgeW<'a, REG> = crate::BitWriter<'a, REG, Dbge>; -impl<'a, REG> DbgeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Dbge::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn emable(self) -> &'a mut crate::W { - self.variant(Dbge::Emable) - } -} -#[doc = "Doze Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dozen { - #[doc = "0: Enable"] - Enable = 0, - #[doc = "1: Disable"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dozen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DOZEN` reader - Doze Enable"] -pub type DozenR = crate::BitReader; -impl DozenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dozen { - match self.bits { - false => Dozen::Enable, - true => Dozen::Disable, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dozen::Enable - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Dozen::Disable - } -} -#[doc = "Field `DOZEN` writer - Doze Enable"] -pub type DozenW<'a, REG> = crate::BitWriter<'a, REG, Dozen>; -impl<'a, REG> DozenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dozen::Enable) - } - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Dozen::Disable) - } -} -impl R { - #[doc = "Bit 0 - FLEXIO Enable"] - #[inline(always)] - pub fn flexen(&self) -> FlexenR { - FlexenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn swrst(&self) -> SwrstR { - SwrstR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Fast Access"] - #[inline(always)] - pub fn fastacc(&self) -> FastaccR { - FastaccR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 30 - Debug Enable"] - #[inline(always)] - pub fn dbge(&self) -> DbgeR { - DbgeR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Doze Enable"] - #[inline(always)] - pub fn dozen(&self) -> DozenR { - DozenR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FLEXIO Enable"] - #[inline(always)] - pub fn flexen(&mut self) -> FlexenW { - FlexenW::new(self, 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn swrst(&mut self) -> SwrstW { - SwrstW::new(self, 1) - } - #[doc = "Bit 2 - Fast Access"] - #[inline(always)] - pub fn fastacc(&mut self) -> FastaccW { - FastaccW::new(self, 2) - } - #[doc = "Bit 30 - Debug Enable"] - #[inline(always)] - pub fn dbge(&mut self) -> DbgeW { - DbgeW::new(self, 30) - } - #[doc = "Bit 31 - Doze Enable"] - #[inline(always)] - pub fn dozen(&mut self) -> DozenW { - DozenW::new(self, 31) - } -} -#[doc = "FLEXIO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/flexio0/param.rs b/mcxa276-pac/src/flexio0/param.rs deleted file mode 100644 index 3bd5b8365..000000000 --- a/mcxa276-pac/src/flexio0/param.rs +++ /dev/null @@ -1,43 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "Field `SHIFTER` reader - Shifter Number"] -pub type ShifterR = crate::FieldReader; -#[doc = "Field `TIMER` reader - Timer Number"] -pub type TimerR = crate::FieldReader; -#[doc = "Field `PIN` reader - Pin Number"] -pub type PinR = crate::FieldReader; -#[doc = "Field `TRIGGER` reader - Trigger Number"] -pub type TriggerR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Shifter Number"] - #[inline(always)] - pub fn shifter(&self) -> ShifterR { - ShifterR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Timer Number"] - #[inline(always)] - pub fn timer(&self) -> TimerR { - TimerR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Pin Number"] - #[inline(always)] - pub fn pin(&self) -> PinR { - PinR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Trigger Number"] - #[inline(always)] - pub fn trigger(&self) -> TriggerR { - TriggerR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x0420_0404"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x0420_0404; -} diff --git a/mcxa276-pac/src/flexio0/pin.rs b/mcxa276-pac/src/flexio0/pin.rs deleted file mode 100644 index 32ee93af4..000000000 --- a/mcxa276-pac/src/flexio0/pin.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `PIN` reader"] -pub type R = crate::R; -#[doc = "Field `PDI` reader - Pin Data Input"] -pub type PdiR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Pin Data Input"] - #[inline(always)] - pub fn pdi(&self) -> PdiR { - PdiR::new(self.bits) - } -} -#[doc = "Pin State\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinSpec; -impl crate::RegisterSpec for PinSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin::R`](R) reader structure"] -impl crate::Readable for PinSpec {} -#[doc = "`reset()` method sets PIN to value 0"] -impl crate::Resettable for PinSpec {} diff --git a/mcxa276-pac/src/flexio0/pinfen.rs b/mcxa276-pac/src/flexio0/pinfen.rs deleted file mode 100644 index 5b25594a4..000000000 --- a/mcxa276-pac/src/flexio0/pinfen.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINFEN` reader"] -pub type R = crate::R; -#[doc = "Register `PINFEN` writer"] -pub type W = crate::W; -#[doc = "Field `PFE` reader - Pin Falling Edge"] -pub type PfeR = crate::FieldReader; -#[doc = "Field `PFE` writer - Pin Falling Edge"] -pub type PfeW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Pin Falling Edge"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Pin Falling Edge"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 0) - } -} -#[doc = "Pin Falling Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinfen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinfen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinfenSpec; -impl crate::RegisterSpec for PinfenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinfen::R`](R) reader structure"] -impl crate::Readable for PinfenSpec {} -#[doc = "`write(|w| ..)` method takes [`pinfen::W`](W) writer structure"] -impl crate::Writable for PinfenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINFEN to value 0"] -impl crate::Resettable for PinfenSpec {} diff --git a/mcxa276-pac/src/flexio0/pinien.rs b/mcxa276-pac/src/flexio0/pinien.rs deleted file mode 100644 index a26dd10b3..000000000 --- a/mcxa276-pac/src/flexio0/pinien.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINIEN` reader"] -pub type R = crate::R; -#[doc = "Register `PINIEN` writer"] -pub type W = crate::W; -#[doc = "Field `PSIE` reader - Pin Status Interrupt Enable"] -pub type PsieR = crate::FieldReader; -#[doc = "Field `PSIE` writer - Pin Status Interrupt Enable"] -pub type PsieW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Pin Status Interrupt Enable"] - #[inline(always)] - pub fn psie(&self) -> PsieR { - PsieR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Pin Status Interrupt Enable"] - #[inline(always)] - pub fn psie(&mut self) -> PsieW { - PsieW::new(self, 0) - } -} -#[doc = "Pin Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinienSpec; -impl crate::RegisterSpec for PinienSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinien::R`](R) reader structure"] -impl crate::Readable for PinienSpec {} -#[doc = "`write(|w| ..)` method takes [`pinien::W`](W) writer structure"] -impl crate::Writable for PinienSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINIEN to value 0"] -impl crate::Resettable for PinienSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutclr.rs b/mcxa276-pac/src/flexio0/pinoutclr.rs deleted file mode 100644 index 298cbda09..000000000 --- a/mcxa276-pac/src/flexio0/pinoutclr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINOUTCLR` reader"] -pub type R = crate::R; -#[doc = "Register `PINOUTCLR` writer"] -pub type W = crate::W; -#[doc = "Field `OUTCLR` reader - Output Clear"] -pub type OutclrR = crate::FieldReader; -#[doc = "Field `OUTCLR` writer - Output Clear"] -pub type OutclrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Clear"] - #[inline(always)] - pub fn outclr(&self) -> OutclrR { - OutclrR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Clear"] - #[inline(always)] - pub fn outclr(&mut self) -> OutclrW { - OutclrW::new(self, 0) - } -} -#[doc = "Pin Output Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinoutclrSpec; -impl crate::RegisterSpec for PinoutclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinoutclr::R`](R) reader structure"] -impl crate::Readable for PinoutclrSpec {} -#[doc = "`write(|w| ..)` method takes [`pinoutclr::W`](W) writer structure"] -impl crate::Writable for PinoutclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINOUTCLR to value 0"] -impl crate::Resettable for PinoutclrSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutd.rs b/mcxa276-pac/src/flexio0/pinoutd.rs deleted file mode 100644 index 5dd228031..000000000 --- a/mcxa276-pac/src/flexio0/pinoutd.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINOUTD` reader"] -pub type R = crate::R; -#[doc = "Register `PINOUTD` writer"] -pub type W = crate::W; -#[doc = "Field `OUTD` reader - Output Data"] -pub type OutdR = crate::FieldReader; -#[doc = "Field `OUTD` writer - Output Data"] -pub type OutdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Data"] - #[inline(always)] - pub fn outd(&self) -> OutdR { - OutdR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Data"] - #[inline(always)] - pub fn outd(&mut self) -> OutdW { - OutdW::new(self, 0) - } -} -#[doc = "Pin Output Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinoutdSpec; -impl crate::RegisterSpec for PinoutdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinoutd::R`](R) reader structure"] -impl crate::Readable for PinoutdSpec {} -#[doc = "`write(|w| ..)` method takes [`pinoutd::W`](W) writer structure"] -impl crate::Writable for PinoutdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINOUTD to value 0"] -impl crate::Resettable for PinoutdSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutdis.rs b/mcxa276-pac/src/flexio0/pinoutdis.rs deleted file mode 100644 index 9b51a07a0..000000000 --- a/mcxa276-pac/src/flexio0/pinoutdis.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINOUTDIS` reader"] -pub type R = crate::R; -#[doc = "Register `PINOUTDIS` writer"] -pub type W = crate::W; -#[doc = "Field `OUTDIS` reader - Output Disable"] -pub type OutdisR = crate::FieldReader; -#[doc = "Field `OUTDIS` writer - Output Disable"] -pub type OutdisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Disable"] - #[inline(always)] - pub fn outdis(&self) -> OutdisR { - OutdisR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Disable"] - #[inline(always)] - pub fn outdis(&mut self) -> OutdisW { - OutdisW::new(self, 0) - } -} -#[doc = "Pin Output Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutdis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutdis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinoutdisSpec; -impl crate::RegisterSpec for PinoutdisSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinoutdis::R`](R) reader structure"] -impl crate::Readable for PinoutdisSpec {} -#[doc = "`write(|w| ..)` method takes [`pinoutdis::W`](W) writer structure"] -impl crate::Writable for PinoutdisSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINOUTDIS to value 0"] -impl crate::Resettable for PinoutdisSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoute.rs b/mcxa276-pac/src/flexio0/pinoute.rs deleted file mode 100644 index 4309e68f9..000000000 --- a/mcxa276-pac/src/flexio0/pinoute.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINOUTE` reader"] -pub type R = crate::R; -#[doc = "Register `PINOUTE` writer"] -pub type W = crate::W; -#[doc = "Field `OUTE` reader - Output Enable"] -pub type OuteR = crate::FieldReader; -#[doc = "Field `OUTE` writer - Output Enable"] -pub type OuteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Enable"] - #[inline(always)] - pub fn oute(&self) -> OuteR { - OuteR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Enable"] - #[inline(always)] - pub fn oute(&mut self) -> OuteW { - OuteW::new(self, 0) - } -} -#[doc = "Pin Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoute::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoute::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinouteSpec; -impl crate::RegisterSpec for PinouteSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinoute::R`](R) reader structure"] -impl crate::Readable for PinouteSpec {} -#[doc = "`write(|w| ..)` method takes [`pinoute::W`](W) writer structure"] -impl crate::Writable for PinouteSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINOUTE to value 0"] -impl crate::Resettable for PinouteSpec {} diff --git a/mcxa276-pac/src/flexio0/pinoutset.rs b/mcxa276-pac/src/flexio0/pinoutset.rs deleted file mode 100644 index 9ce1b747f..000000000 --- a/mcxa276-pac/src/flexio0/pinoutset.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINOUTSET` reader"] -pub type R = crate::R; -#[doc = "Register `PINOUTSET` writer"] -pub type W = crate::W; -#[doc = "Field `OUTSET` reader - Output Set"] -pub type OutsetR = crate::FieldReader; -#[doc = "Field `OUTSET` writer - Output Set"] -pub type OutsetW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Set"] - #[inline(always)] - pub fn outset(&self) -> OutsetR { - OutsetR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Set"] - #[inline(always)] - pub fn outset(&mut self) -> OutsetW { - OutsetW::new(self, 0) - } -} -#[doc = "Pin Output Set\n\nYou can [`read`](crate::Reg::read) this register and get [`pinoutset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinoutset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinoutsetSpec; -impl crate::RegisterSpec for PinoutsetSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinoutset::R`](R) reader structure"] -impl crate::Readable for PinoutsetSpec {} -#[doc = "`write(|w| ..)` method takes [`pinoutset::W`](W) writer structure"] -impl crate::Writable for PinoutsetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINOUTSET to value 0"] -impl crate::Resettable for PinoutsetSpec {} diff --git a/mcxa276-pac/src/flexio0/pinouttog.rs b/mcxa276-pac/src/flexio0/pinouttog.rs deleted file mode 100644 index ae9c6b7b8..000000000 --- a/mcxa276-pac/src/flexio0/pinouttog.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINOUTTOG` reader"] -pub type R = crate::R; -#[doc = "Register `PINOUTTOG` writer"] -pub type W = crate::W; -#[doc = "Field `OUTTOG` reader - Output Toggle"] -pub type OuttogR = crate::FieldReader; -#[doc = "Field `OUTTOG` writer - Output Toggle"] -pub type OuttogW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Toggle"] - #[inline(always)] - pub fn outtog(&self) -> OuttogR { - OuttogR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Toggle"] - #[inline(always)] - pub fn outtog(&mut self) -> OuttogW { - OuttogW::new(self, 0) - } -} -#[doc = "Pin Output Toggle\n\nYou can [`read`](crate::Reg::read) this register and get [`pinouttog::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinouttog::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinouttogSpec; -impl crate::RegisterSpec for PinouttogSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinouttog::R`](R) reader structure"] -impl crate::Readable for PinouttogSpec {} -#[doc = "`write(|w| ..)` method takes [`pinouttog::W`](W) writer structure"] -impl crate::Writable for PinouttogSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINOUTTOG to value 0"] -impl crate::Resettable for PinouttogSpec {} diff --git a/mcxa276-pac/src/flexio0/pinren.rs b/mcxa276-pac/src/flexio0/pinren.rs deleted file mode 100644 index ca357706e..000000000 --- a/mcxa276-pac/src/flexio0/pinren.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PINREN` reader"] -pub type R = crate::R; -#[doc = "Register `PINREN` writer"] -pub type W = crate::W; -#[doc = "Field `PRE` reader - Pin Rising Edge"] -pub type PreR = crate::FieldReader; -#[doc = "Field `PRE` writer - Pin Rising Edge"] -pub type PreW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Pin Rising Edge"] - #[inline(always)] - pub fn pre(&self) -> PreR { - PreR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Pin Rising Edge"] - #[inline(always)] - pub fn pre(&mut self) -> PreW { - PreW::new(self, 0) - } -} -#[doc = "Pin Rising Edge Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pinren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinrenSpec; -impl crate::RegisterSpec for PinrenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinren::R`](R) reader structure"] -impl crate::Readable for PinrenSpec {} -#[doc = "`write(|w| ..)` method takes [`pinren::W`](W) writer structure"] -impl crate::Writable for PinrenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINREN to value 0"] -impl crate::Resettable for PinrenSpec {} diff --git a/mcxa276-pac/src/flexio0/pinstat.rs b/mcxa276-pac/src/flexio0/pinstat.rs deleted file mode 100644 index 0509218c1..000000000 --- a/mcxa276-pac/src/flexio0/pinstat.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `PINSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `PINSTAT` writer"] -pub type W = crate::W; -#[doc = "Pin Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u32)] -pub enum Psf { - #[doc = "0: Clear"] - Clr = 0, - #[doc = "1: Set"] - Set = 1, -} -impl From for u32 { - #[inline(always)] - fn from(variant: Psf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Psf { - type Ux = u32; -} -impl crate::IsEnum for Psf {} -#[doc = "Field `PSF` reader - Pin Status Flag"] -pub type PsfR = crate::FieldReader; -impl PsfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Psf::Clr), - 1 => Some(Psf::Set), - _ => None, - } - } - #[doc = "Clear"] - #[inline(always)] - pub fn is_clr(&self) -> bool { - *self == Psf::Clr - } - #[doc = "Set"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Psf::Set - } -} -#[doc = "Field `PSF` writer - Pin Status Flag"] -pub type PsfW<'a, REG> = crate::FieldWriter<'a, REG, 32, Psf>; -impl<'a, REG> PsfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Clear"] - #[inline(always)] - pub fn clr(self) -> &'a mut crate::W { - self.variant(Psf::Clr) - } - #[doc = "Set"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Psf::Set) - } -} -impl R { - #[doc = "Bits 0:31 - Pin Status Flag"] - #[inline(always)] - pub fn psf(&self) -> PsfR { - PsfR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Pin Status Flag"] - #[inline(always)] - pub fn psf(&mut self) -> PsfW { - PsfW::new(self, 0) - } -} -#[doc = "Pin Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pinstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pinstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PinstatSpec; -impl crate::RegisterSpec for PinstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pinstat::R`](R) reader structure"] -impl crate::Readable for PinstatSpec {} -#[doc = "`write(|w| ..)` method takes [`pinstat::W`](W) writer structure"] -impl crate::Writable for PinstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; -} -#[doc = "`reset()` method sets PINSTAT to value 0"] -impl crate::Resettable for PinstatSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbuf.rs b/mcxa276-pac/src/flexio0/shiftbuf.rs deleted file mode 100644 index aa11c9ff4..000000000 --- a/mcxa276-pac/src/flexio0/shiftbuf.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUF[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUF[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUF` reader - Shift Buffer"] -pub type ShiftbufR = crate::FieldReader; -#[doc = "Field `SHIFTBUF` writer - Shift Buffer"] -pub type ShiftbufW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbuf(&self) -> ShiftbufR { - ShiftbufR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbuf(&mut self) -> ShiftbufW { - ShiftbufW::new(self, 0) - } -} -#[doc = "Shifter Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufSpec; -impl crate::RegisterSpec for ShiftbufSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbuf::R`](R) reader structure"] -impl crate::Readable for ShiftbufSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbuf::W`](W) writer structure"] -impl crate::Writable for ShiftbufSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUF[%s] to value 0"] -impl crate::Resettable for ShiftbufSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufbbs.rs b/mcxa276-pac/src/flexio0/shiftbufbbs.rs deleted file mode 100644 index 3b24c5fe4..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufbbs.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFBBS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFBBS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFBBS` reader - Shift Buffer"] -pub type ShiftbufbbsR = crate::FieldReader; -#[doc = "Field `SHIFTBUFBBS` writer - Shift Buffer"] -pub type ShiftbufbbsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufbbs(&self) -> ShiftbufbbsR { - ShiftbufbbsR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufbbs(&mut self) -> ShiftbufbbsW { - ShiftbufbbsW::new(self, 0) - } -} -#[doc = "Shifter Buffer Bit Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbbs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbbs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufbbsSpec; -impl crate::RegisterSpec for ShiftbufbbsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufbbs::R`](R) reader structure"] -impl crate::Readable for ShiftbufbbsSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufbbs::W`](W) writer structure"] -impl crate::Writable for ShiftbufbbsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFBBS[%s] to value 0"] -impl crate::Resettable for ShiftbufbbsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufbis.rs b/mcxa276-pac/src/flexio0/shiftbufbis.rs deleted file mode 100644 index 466ad0f08..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufbis.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFBIS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFBIS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFBIS` reader - Shift Buffer"] -pub type ShiftbufbisR = crate::FieldReader; -#[doc = "Field `SHIFTBUFBIS` writer - Shift Buffer"] -pub type ShiftbufbisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufbis(&self) -> ShiftbufbisR { - ShiftbufbisR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufbis(&mut self) -> ShiftbufbisW { - ShiftbufbisW::new(self, 0) - } -} -#[doc = "Shifter Buffer Bit Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufbisSpec; -impl crate::RegisterSpec for ShiftbufbisSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufbis::R`](R) reader structure"] -impl crate::Readable for ShiftbufbisSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufbis::W`](W) writer structure"] -impl crate::Writable for ShiftbufbisSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFBIS[%s] to value 0"] -impl crate::Resettable for ShiftbufbisSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufbys.rs b/mcxa276-pac/src/flexio0/shiftbufbys.rs deleted file mode 100644 index eb4eb394a..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufbys.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFBYS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFBYS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFBYS` reader - Shift Buffer"] -pub type ShiftbufbysR = crate::FieldReader; -#[doc = "Field `SHIFTBUFBYS` writer - Shift Buffer"] -pub type ShiftbufbysW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufbys(&self) -> ShiftbufbysR { - ShiftbufbysR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufbys(&mut self) -> ShiftbufbysW { - ShiftbufbysW::new(self, 0) - } -} -#[doc = "Shifter Buffer Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufbys::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufbys::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufbysSpec; -impl crate::RegisterSpec for ShiftbufbysSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufbys::R`](R) reader structure"] -impl crate::Readable for ShiftbufbysSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufbys::W`](W) writer structure"] -impl crate::Writable for ShiftbufbysSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFBYS[%s] to value 0"] -impl crate::Resettable for ShiftbufbysSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufeos.rs b/mcxa276-pac/src/flexio0/shiftbufeos.rs deleted file mode 100644 index beb07fc8d..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufeos.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFEOS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFEOS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFEOS` reader - Shift Buffer"] -pub type ShiftbufeosR = crate::FieldReader; -#[doc = "Field `SHIFTBUFEOS` writer - Shift Buffer"] -pub type ShiftbufeosW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufeos(&self) -> ShiftbufeosR { - ShiftbufeosR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufeos(&mut self) -> ShiftbufeosW { - ShiftbufeosW::new(self, 0) - } -} -#[doc = "Shifter Buffer Even Odd Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufeos::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufeos::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufeosSpec; -impl crate::RegisterSpec for ShiftbufeosSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufeos::R`](R) reader structure"] -impl crate::Readable for ShiftbufeosSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufeos::W`](W) writer structure"] -impl crate::Writable for ShiftbufeosSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFEOS[%s] to value 0"] -impl crate::Resettable for ShiftbufeosSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufhbs.rs b/mcxa276-pac/src/flexio0/shiftbufhbs.rs deleted file mode 100644 index 95481c89d..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufhbs.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFHBS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFHBS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFHBS` reader - Shift Buffer"] -pub type ShiftbufhbsR = crate::FieldReader; -#[doc = "Field `SHIFTBUFHBS` writer - Shift Buffer"] -pub type ShiftbufhbsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufhbs(&self) -> ShiftbufhbsR { - ShiftbufhbsR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufhbs(&mut self) -> ShiftbufhbsW { - ShiftbufhbsW::new(self, 0) - } -} -#[doc = "Shifter Buffer Halfword Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhbs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhbs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufhbsSpec; -impl crate::RegisterSpec for ShiftbufhbsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufhbs::R`](R) reader structure"] -impl crate::Readable for ShiftbufhbsSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufhbs::W`](W) writer structure"] -impl crate::Writable for ShiftbufhbsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFHBS[%s] to value 0"] -impl crate::Resettable for ShiftbufhbsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufhws.rs b/mcxa276-pac/src/flexio0/shiftbufhws.rs deleted file mode 100644 index 62f4477d2..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufhws.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFHWS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFHWS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFHWS` reader - Shift Buffer"] -pub type ShiftbufhwsR = crate::FieldReader; -#[doc = "Field `SHIFTBUFHWS` writer - Shift Buffer"] -pub type ShiftbufhwsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufhws(&self) -> ShiftbufhwsR { - ShiftbufhwsR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufhws(&mut self) -> ShiftbufhwsW { - ShiftbufhwsW::new(self, 0) - } -} -#[doc = "Shifter Buffer Halfword Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufhws::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufhws::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufhwsSpec; -impl crate::RegisterSpec for ShiftbufhwsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufhws::R`](R) reader structure"] -impl crate::Readable for ShiftbufhwsSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufhws::W`](W) writer structure"] -impl crate::Writable for ShiftbufhwsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFHWS[%s] to value 0"] -impl crate::Resettable for ShiftbufhwsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufnbs.rs b/mcxa276-pac/src/flexio0/shiftbufnbs.rs deleted file mode 100644 index 6e2d36f22..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufnbs.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFNBS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFNBS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFNBS` reader - Shift Buffer"] -pub type ShiftbufnbsR = crate::FieldReader; -#[doc = "Field `SHIFTBUFNBS` writer - Shift Buffer"] -pub type ShiftbufnbsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufnbs(&self) -> ShiftbufnbsR { - ShiftbufnbsR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufnbs(&mut self) -> ShiftbufnbsW { - ShiftbufnbsW::new(self, 0) - } -} -#[doc = "Shifter Buffer Nibble Byte Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnbs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnbs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufnbsSpec; -impl crate::RegisterSpec for ShiftbufnbsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufnbs::R`](R) reader structure"] -impl crate::Readable for ShiftbufnbsSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufnbs::W`](W) writer structure"] -impl crate::Writable for ShiftbufnbsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFNBS[%s] to value 0"] -impl crate::Resettable for ShiftbufnbsSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufnis.rs b/mcxa276-pac/src/flexio0/shiftbufnis.rs deleted file mode 100644 index fe18a30af..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufnis.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFNIS[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFNIS[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFNIS` reader - Shift Buffer"] -pub type ShiftbufnisR = crate::FieldReader; -#[doc = "Field `SHIFTBUFNIS` writer - Shift Buffer"] -pub type ShiftbufnisW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufnis(&self) -> ShiftbufnisR { - ShiftbufnisR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufnis(&mut self) -> ShiftbufnisW { - ShiftbufnisW::new(self, 0) - } -} -#[doc = "Shifter Buffer Nibble Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufnis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufnis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufnisSpec; -impl crate::RegisterSpec for ShiftbufnisSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufnis::R`](R) reader structure"] -impl crate::Readable for ShiftbufnisSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufnis::W`](W) writer structure"] -impl crate::Writable for ShiftbufnisSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFNIS[%s] to value 0"] -impl crate::Resettable for ShiftbufnisSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftbufoes.rs b/mcxa276-pac/src/flexio0/shiftbufoes.rs deleted file mode 100644 index efb211a47..000000000 --- a/mcxa276-pac/src/flexio0/shiftbufoes.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTBUFOES[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTBUFOES[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `SHIFTBUFOES` reader - Shift Buffer"] -pub type ShiftbufoesR = crate::FieldReader; -#[doc = "Field `SHIFTBUFOES` writer - Shift Buffer"] -pub type ShiftbufoesW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufoes(&self) -> ShiftbufoesR { - ShiftbufoesR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Shift Buffer"] - #[inline(always)] - pub fn shiftbufoes(&mut self) -> ShiftbufoesW { - ShiftbufoesW::new(self, 0) - } -} -#[doc = "Shifter Buffer Odd Even Swapped\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftbufoes::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftbufoes::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftbufoesSpec; -impl crate::RegisterSpec for ShiftbufoesSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftbufoes::R`](R) reader structure"] -impl crate::Readable for ShiftbufoesSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftbufoes::W`](W) writer structure"] -impl crate::Writable for ShiftbufoesSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTBUFOES[%s] to value 0"] -impl crate::Resettable for ShiftbufoesSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftcfg.rs b/mcxa276-pac/src/flexio0/shiftcfg.rs deleted file mode 100644 index 7e742935a..000000000 --- a/mcxa276-pac/src/flexio0/shiftcfg.rs +++ /dev/null @@ -1,416 +0,0 @@ -#[doc = "Register `SHIFTCFG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTCFG[%s]` writer"] -pub type W = crate::W; -#[doc = "Shifter Start\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sstart { - #[doc = "0: Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable"] - Value00 = 0, - #[doc = "1: Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift"] - Value01 = 1, - #[doc = "2: Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, Receiver and Match Store modes set error flag"] - Value10 = 2, - #[doc = "3: Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, Receiver and Match Store modes set error flag"] - Value11 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sstart) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sstart { - type Ux = u8; -} -impl crate::IsEnum for Sstart {} -#[doc = "Field `SSTART` reader - Shifter Start"] -pub type SstartR = crate::FieldReader; -impl SstartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sstart { - match self.bits { - 0 => Sstart::Value00, - 1 => Sstart::Value01, - 2 => Sstart::Value10, - 3 => Sstart::Value11, - _ => unreachable!(), - } - } - #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable"] - #[inline(always)] - pub fn is_value00(&self) -> bool { - *self == Sstart::Value00 - } - #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift"] - #[inline(always)] - pub fn is_value01(&self) -> bool { - *self == Sstart::Value01 - } - #[doc = "Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, Receiver and Match Store modes set error flag"] - #[inline(always)] - pub fn is_value10(&self) -> bool { - *self == Sstart::Value10 - } - #[doc = "Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, Receiver and Match Store modes set error flag"] - #[inline(always)] - pub fn is_value11(&self) -> bool { - *self == Sstart::Value11 - } -} -#[doc = "Field `SSTART` writer - Shifter Start"] -pub type SstartW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sstart, crate::Safe>; -impl<'a, REG> SstartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable"] - #[inline(always)] - pub fn value00(self) -> &'a mut crate::W { - self.variant(Sstart::Value00) - } - #[doc = "Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift"] - #[inline(always)] - pub fn value01(self) -> &'a mut crate::W { - self.variant(Sstart::Value01) - } - #[doc = "Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, Receiver and Match Store modes set error flag"] - #[inline(always)] - pub fn value10(self) -> &'a mut crate::W { - self.variant(Sstart::Value10) - } - #[doc = "Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, Receiver and Match Store modes set error flag"] - #[inline(always)] - pub fn value11(self) -> &'a mut crate::W { - self.variant(Sstart::Value11) - } -} -#[doc = "Shifter Stop\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sstop { - #[doc = "0: Stop bit disabled for Transmitter, Receiver, and Match Store modes"] - Value00 = 0, - #[doc = "1: Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, Receiver and Match Store modes store receive data on the configured shift edge"] - Value01 = 1, - #[doc = "2: Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] - Value10 = 2, - #[doc = "3: Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] - Value11 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sstop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sstop { - type Ux = u8; -} -impl crate::IsEnum for Sstop {} -#[doc = "Field `SSTOP` reader - Shifter Stop"] -pub type SstopR = crate::FieldReader; -impl SstopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sstop { - match self.bits { - 0 => Sstop::Value00, - 1 => Sstop::Value01, - 2 => Sstop::Value10, - 3 => Sstop::Value11, - _ => unreachable!(), - } - } - #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes"] - #[inline(always)] - pub fn is_value00(&self) -> bool { - *self == Sstop::Value00 - } - #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, Receiver and Match Store modes store receive data on the configured shift edge"] - #[inline(always)] - pub fn is_value01(&self) -> bool { - *self == Sstop::Value01 - } - #[doc = "Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] - #[inline(always)] - pub fn is_value10(&self) -> bool { - *self == Sstop::Value10 - } - #[doc = "Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] - #[inline(always)] - pub fn is_value11(&self) -> bool { - *self == Sstop::Value11 - } -} -#[doc = "Field `SSTOP` writer - Shifter Stop"] -pub type SstopW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sstop, crate::Safe>; -impl<'a, REG> SstopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes"] - #[inline(always)] - pub fn value00(self) -> &'a mut crate::W { - self.variant(Sstop::Value00) - } - #[doc = "Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, Receiver and Match Store modes store receive data on the configured shift edge"] - #[inline(always)] - pub fn value01(self) -> &'a mut crate::W { - self.variant(Sstop::Value01) - } - #[doc = "Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] - #[inline(always)] - pub fn value10(self) -> &'a mut crate::W { - self.variant(Sstop::Value10) - } - #[doc = "Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match Store modes set error flag (when timer is in stop condition, these modes also store receive data on the configured shift edge)"] - #[inline(always)] - pub fn value11(self) -> &'a mut crate::W { - self.variant(Sstop::Value11) - } -} -#[doc = "Input Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Insrc { - #[doc = "0: Pin"] - Pin = 0, - #[doc = "1: Shifter n+1 output"] - ShifterNplus1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Insrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INSRC` reader - Input Source"] -pub type InsrcR = crate::BitReader; -impl InsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Insrc { - match self.bits { - false => Insrc::Pin, - true => Insrc::ShifterNplus1, - } - } - #[doc = "Pin"] - #[inline(always)] - pub fn is_pin(&self) -> bool { - *self == Insrc::Pin - } - #[doc = "Shifter n+1 output"] - #[inline(always)] - pub fn is_shifter_nplus1(&self) -> bool { - *self == Insrc::ShifterNplus1 - } -} -#[doc = "Field `INSRC` writer - Input Source"] -pub type InsrcW<'a, REG> = crate::BitWriter<'a, REG, Insrc>; -impl<'a, REG> InsrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin"] - #[inline(always)] - pub fn pin(self) -> &'a mut crate::W { - self.variant(Insrc::Pin) - } - #[doc = "Shifter n+1 output"] - #[inline(always)] - pub fn shifter_nplus1(self) -> &'a mut crate::W { - self.variant(Insrc::ShifterNplus1) - } -} -#[doc = "Late Store\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Latst { - #[doc = "0: Store the pre-shift register state"] - Preshift = 0, - #[doc = "1: Store the post-shift register state"] - Postshift = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Latst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LATST` reader - Late Store"] -pub type LatstR = crate::BitReader; -impl LatstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Latst { - match self.bits { - false => Latst::Preshift, - true => Latst::Postshift, - } - } - #[doc = "Store the pre-shift register state"] - #[inline(always)] - pub fn is_preshift(&self) -> bool { - *self == Latst::Preshift - } - #[doc = "Store the post-shift register state"] - #[inline(always)] - pub fn is_postshift(&self) -> bool { - *self == Latst::Postshift - } -} -#[doc = "Field `LATST` writer - Late Store"] -pub type LatstW<'a, REG> = crate::BitWriter<'a, REG, Latst>; -impl<'a, REG> LatstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Store the pre-shift register state"] - #[inline(always)] - pub fn preshift(self) -> &'a mut crate::W { - self.variant(Latst::Preshift) - } - #[doc = "Store the post-shift register state"] - #[inline(always)] - pub fn postshift(self) -> &'a mut crate::W { - self.variant(Latst::Postshift) - } -} -#[doc = "Shifter Size\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ssize { - #[doc = "0: 32-bit"] - Width32 = 0, - #[doc = "1: 24-bit"] - Width24 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ssize) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SSIZE` reader - Shifter Size"] -pub type SsizeR = crate::BitReader; -impl SsizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ssize { - match self.bits { - false => Ssize::Width32, - true => Ssize::Width24, - } - } - #[doc = "32-bit"] - #[inline(always)] - pub fn is_width32(&self) -> bool { - *self == Ssize::Width32 - } - #[doc = "24-bit"] - #[inline(always)] - pub fn is_width24(&self) -> bool { - *self == Ssize::Width24 - } -} -#[doc = "Field `SSIZE` writer - Shifter Size"] -pub type SsizeW<'a, REG> = crate::BitWriter<'a, REG, Ssize>; -impl<'a, REG> SsizeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "32-bit"] - #[inline(always)] - pub fn width32(self) -> &'a mut crate::W { - self.variant(Ssize::Width32) - } - #[doc = "24-bit"] - #[inline(always)] - pub fn width24(self) -> &'a mut crate::W { - self.variant(Ssize::Width24) - } -} -#[doc = "Field `PWIDTH` reader - Parallel Width"] -pub type PwidthR = crate::FieldReader; -#[doc = "Field `PWIDTH` writer - Parallel Width"] -pub type PwidthW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bits 0:1 - Shifter Start"] - #[inline(always)] - pub fn sstart(&self) -> SstartR { - SstartR::new((self.bits & 3) as u8) - } - #[doc = "Bits 4:5 - Shifter Stop"] - #[inline(always)] - pub fn sstop(&self) -> SstopR { - SstopR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 8 - Input Source"] - #[inline(always)] - pub fn insrc(&self) -> InsrcR { - InsrcR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Late Store"] - #[inline(always)] - pub fn latst(&self) -> LatstR { - LatstR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 12 - Shifter Size"] - #[inline(always)] - pub fn ssize(&self) -> SsizeR { - SsizeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bits 16:20 - Parallel Width"] - #[inline(always)] - pub fn pwidth(&self) -> PwidthR { - PwidthR::new(((self.bits >> 16) & 0x1f) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Shifter Start"] - #[inline(always)] - pub fn sstart(&mut self) -> SstartW { - SstartW::new(self, 0) - } - #[doc = "Bits 4:5 - Shifter Stop"] - #[inline(always)] - pub fn sstop(&mut self) -> SstopW { - SstopW::new(self, 4) - } - #[doc = "Bit 8 - Input Source"] - #[inline(always)] - pub fn insrc(&mut self) -> InsrcW { - InsrcW::new(self, 8) - } - #[doc = "Bit 9 - Late Store"] - #[inline(always)] - pub fn latst(&mut self) -> LatstW { - LatstW::new(self, 9) - } - #[doc = "Bit 12 - Shifter Size"] - #[inline(always)] - pub fn ssize(&mut self) -> SsizeW { - SsizeW::new(self, 12) - } - #[doc = "Bits 16:20 - Parallel Width"] - #[inline(always)] - pub fn pwidth(&mut self) -> PwidthW { - PwidthW::new(self, 16) - } -} -#[doc = "Shifter Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftcfgSpec; -impl crate::RegisterSpec for ShiftcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftcfg::R`](R) reader structure"] -impl crate::Readable for ShiftcfgSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftcfg::W`](W) writer structure"] -impl crate::Writable for ShiftcfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTCFG[%s] to value 0"] -impl crate::Resettable for ShiftcfgSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftctl.rs b/mcxa276-pac/src/flexio0/shiftctl.rs deleted file mode 100644 index 74b1032ee..000000000 --- a/mcxa276-pac/src/flexio0/shiftctl.rs +++ /dev/null @@ -1,406 +0,0 @@ -#[doc = "Register `SHIFTCTL[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTCTL[%s]` writer"] -pub type W = crate::W; -#[doc = "Shifter Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Smod { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer"] - Receive = 1, - #[doc = "2: Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer"] - Transmit = 2, - #[doc = "4: Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer"] - Matchstore = 4, - #[doc = "5: Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents"] - Matchcont = 5, - #[doc = "6: State mode; SHIFTBUF contents store programmable state attributes"] - State = 6, - #[doc = "7: Logic mode; SHIFTBUF contents implement programmable logic lookup table"] - Logic = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Smod) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Smod { - type Ux = u8; -} -impl crate::IsEnum for Smod {} -#[doc = "Field `SMOD` reader - Shifter Mode"] -pub type SmodR = crate::FieldReader; -impl SmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Smod::Disable), - 1 => Some(Smod::Receive), - 2 => Some(Smod::Transmit), - 4 => Some(Smod::Matchstore), - 5 => Some(Smod::Matchcont), - 6 => Some(Smod::State), - 7 => Some(Smod::Logic), - _ => None, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Smod::Disable - } - #[doc = "Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer"] - #[inline(always)] - pub fn is_receive(&self) -> bool { - *self == Smod::Receive - } - #[doc = "Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer"] - #[inline(always)] - pub fn is_transmit(&self) -> bool { - *self == Smod::Transmit - } - #[doc = "Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer"] - #[inline(always)] - pub fn is_matchstore(&self) -> bool { - *self == Smod::Matchstore - } - #[doc = "Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents"] - #[inline(always)] - pub fn is_matchcont(&self) -> bool { - *self == Smod::Matchcont - } - #[doc = "State mode; SHIFTBUF contents store programmable state attributes"] - #[inline(always)] - pub fn is_state(&self) -> bool { - *self == Smod::State - } - #[doc = "Logic mode; SHIFTBUF contents implement programmable logic lookup table"] - #[inline(always)] - pub fn is_logic(&self) -> bool { - *self == Smod::Logic - } -} -#[doc = "Field `SMOD` writer - Shifter Mode"] -pub type SmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Smod>; -impl<'a, REG> SmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Smod::Disable) - } - #[doc = "Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer"] - #[inline(always)] - pub fn receive(self) -> &'a mut crate::W { - self.variant(Smod::Receive) - } - #[doc = "Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer"] - #[inline(always)] - pub fn transmit(self) -> &'a mut crate::W { - self.variant(Smod::Transmit) - } - #[doc = "Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer"] - #[inline(always)] - pub fn matchstore(self) -> &'a mut crate::W { - self.variant(Smod::Matchstore) - } - #[doc = "Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents"] - #[inline(always)] - pub fn matchcont(self) -> &'a mut crate::W { - self.variant(Smod::Matchcont) - } - #[doc = "State mode; SHIFTBUF contents store programmable state attributes"] - #[inline(always)] - pub fn state(self) -> &'a mut crate::W { - self.variant(Smod::State) - } - #[doc = "Logic mode; SHIFTBUF contents implement programmable logic lookup table"] - #[inline(always)] - pub fn logic(self) -> &'a mut crate::W { - self.variant(Smod::Logic) - } -} -#[doc = "Shifter Pin Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pinpol { - #[doc = "0: Active high"] - ActiveHigh = 0, - #[doc = "1: Active low"] - ActiveLow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pinpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PINPOL` reader - Shifter Pin Polarity"] -pub type PinpolR = crate::BitReader; -impl PinpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pinpol { - match self.bits { - false => Pinpol::ActiveHigh, - true => Pinpol::ActiveLow, - } - } - #[doc = "Active high"] - #[inline(always)] - pub fn is_active_high(&self) -> bool { - *self == Pinpol::ActiveHigh - } - #[doc = "Active low"] - #[inline(always)] - pub fn is_active_low(&self) -> bool { - *self == Pinpol::ActiveLow - } -} -#[doc = "Field `PINPOL` writer - Shifter Pin Polarity"] -pub type PinpolW<'a, REG> = crate::BitWriter<'a, REG, Pinpol>; -impl<'a, REG> PinpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active high"] - #[inline(always)] - pub fn active_high(self) -> &'a mut crate::W { - self.variant(Pinpol::ActiveHigh) - } - #[doc = "Active low"] - #[inline(always)] - pub fn active_low(self) -> &'a mut crate::W { - self.variant(Pinpol::ActiveLow) - } -} -#[doc = "Field `PINSEL` reader - Shifter Pin Select"] -pub type PinselR = crate::FieldReader; -#[doc = "Field `PINSEL` writer - Shifter Pin Select"] -pub type PinselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Shifter Pin Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pincfg { - #[doc = "0: Shifter pin output disabled"] - Disable = 0, - #[doc = "1: Shifter pin open-drain or bidirectional output enable"] - OpendBidirouten = 1, - #[doc = "2: Shifter pin bidirectional output data"] - BidirOutdata = 2, - #[doc = "3: Shifter pin output"] - Output = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pincfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pincfg { - type Ux = u8; -} -impl crate::IsEnum for Pincfg {} -#[doc = "Field `PINCFG` reader - Shifter Pin Configuration"] -pub type PincfgR = crate::FieldReader; -impl PincfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pincfg { - match self.bits { - 0 => Pincfg::Disable, - 1 => Pincfg::OpendBidirouten, - 2 => Pincfg::BidirOutdata, - 3 => Pincfg::Output, - _ => unreachable!(), - } - } - #[doc = "Shifter pin output disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pincfg::Disable - } - #[doc = "Shifter pin open-drain or bidirectional output enable"] - #[inline(always)] - pub fn is_opend_bidirouten(&self) -> bool { - *self == Pincfg::OpendBidirouten - } - #[doc = "Shifter pin bidirectional output data"] - #[inline(always)] - pub fn is_bidir_outdata(&self) -> bool { - *self == Pincfg::BidirOutdata - } - #[doc = "Shifter pin output"] - #[inline(always)] - pub fn is_output(&self) -> bool { - *self == Pincfg::Output - } -} -#[doc = "Field `PINCFG` writer - Shifter Pin Configuration"] -pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pincfg, crate::Safe>; -impl<'a, REG> PincfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Shifter pin output disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pincfg::Disable) - } - #[doc = "Shifter pin open-drain or bidirectional output enable"] - #[inline(always)] - pub fn opend_bidirouten(self) -> &'a mut crate::W { - self.variant(Pincfg::OpendBidirouten) - } - #[doc = "Shifter pin bidirectional output data"] - #[inline(always)] - pub fn bidir_outdata(self) -> &'a mut crate::W { - self.variant(Pincfg::BidirOutdata) - } - #[doc = "Shifter pin output"] - #[inline(always)] - pub fn output(self) -> &'a mut crate::W { - self.variant(Pincfg::Output) - } -} -#[doc = "Timer Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Timpol { - #[doc = "0: Positive edge"] - Posedge = 0, - #[doc = "1: Negative edge"] - Negedge = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Timpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIMPOL` reader - Timer Polarity"] -pub type TimpolR = crate::BitReader; -impl TimpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timpol { - match self.bits { - false => Timpol::Posedge, - true => Timpol::Negedge, - } - } - #[doc = "Positive edge"] - #[inline(always)] - pub fn is_posedge(&self) -> bool { - *self == Timpol::Posedge - } - #[doc = "Negative edge"] - #[inline(always)] - pub fn is_negedge(&self) -> bool { - *self == Timpol::Negedge - } -} -#[doc = "Field `TIMPOL` writer - Timer Polarity"] -pub type TimpolW<'a, REG> = crate::BitWriter<'a, REG, Timpol>; -impl<'a, REG> TimpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Positive edge"] - #[inline(always)] - pub fn posedge(self) -> &'a mut crate::W { - self.variant(Timpol::Posedge) - } - #[doc = "Negative edge"] - #[inline(always)] - pub fn negedge(self) -> &'a mut crate::W { - self.variant(Timpol::Negedge) - } -} -#[doc = "Field `TIMSEL` reader - Timer Select"] -pub type TimselR = crate::FieldReader; -#[doc = "Field `TIMSEL` writer - Timer Select"] -pub type TimselW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:2 - Shifter Mode"] - #[inline(always)] - pub fn smod(&self) -> SmodR { - SmodR::new((self.bits & 7) as u8) - } - #[doc = "Bit 7 - Shifter Pin Polarity"] - #[inline(always)] - pub fn pinpol(&self) -> PinpolR { - PinpolR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:12 - Shifter Pin Select"] - #[inline(always)] - pub fn pinsel(&self) -> PinselR { - PinselR::new(((self.bits >> 8) & 0x1f) as u8) - } - #[doc = "Bits 16:17 - Shifter Pin Configuration"] - #[inline(always)] - pub fn pincfg(&self) -> PincfgR { - PincfgR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bit 23 - Timer Polarity"] - #[inline(always)] - pub fn timpol(&self) -> TimpolR { - TimpolR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:25 - Timer Select"] - #[inline(always)] - pub fn timsel(&self) -> TimselR { - TimselR::new(((self.bits >> 24) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Shifter Mode"] - #[inline(always)] - pub fn smod(&mut self) -> SmodW { - SmodW::new(self, 0) - } - #[doc = "Bit 7 - Shifter Pin Polarity"] - #[inline(always)] - pub fn pinpol(&mut self) -> PinpolW { - PinpolW::new(self, 7) - } - #[doc = "Bits 8:12 - Shifter Pin Select"] - #[inline(always)] - pub fn pinsel(&mut self) -> PinselW { - PinselW::new(self, 8) - } - #[doc = "Bits 16:17 - Shifter Pin Configuration"] - #[inline(always)] - pub fn pincfg(&mut self) -> PincfgW { - PincfgW::new(self, 16) - } - #[doc = "Bit 23 - Timer Polarity"] - #[inline(always)] - pub fn timpol(&mut self) -> TimpolW { - TimpolW::new(self, 23) - } - #[doc = "Bits 24:25 - Timer Select"] - #[inline(always)] - pub fn timsel(&mut self) -> TimselW { - TimselW::new(self, 24) - } -} -#[doc = "Shifter Control\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftctlSpec; -impl crate::RegisterSpec for ShiftctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftctl::R`](R) reader structure"] -impl crate::Readable for ShiftctlSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftctl::W`](W) writer structure"] -impl crate::Writable for ShiftctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTCTL[%s] to value 0"] -impl crate::Resettable for ShiftctlSpec {} diff --git a/mcxa276-pac/src/flexio0/shifteien.rs b/mcxa276-pac/src/flexio0/shifteien.rs deleted file mode 100644 index f470cbc76..000000000 --- a/mcxa276-pac/src/flexio0/shifteien.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTEIEN` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTEIEN` writer"] -pub type W = crate::W; -#[doc = "Field `SEIE` reader - Shifter Error Interrupt Enable"] -pub type SeieR = crate::FieldReader; -#[doc = "Field `SEIE` writer - Shifter Error Interrupt Enable"] -pub type SeieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Shifter Error Interrupt Enable"] - #[inline(always)] - pub fn seie(&self) -> SeieR { - SeieR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Shifter Error Interrupt Enable"] - #[inline(always)] - pub fn seie(&mut self) -> SeieW { - SeieW::new(self, 0) - } -} -#[doc = "Shifter Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shifteien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifteien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShifteienSpec; -impl crate::RegisterSpec for ShifteienSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shifteien::R`](R) reader structure"] -impl crate::Readable for ShifteienSpec {} -#[doc = "`write(|w| ..)` method takes [`shifteien::W`](W) writer structure"] -impl crate::Writable for ShifteienSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTEIEN to value 0"] -impl crate::Resettable for ShifteienSpec {} diff --git a/mcxa276-pac/src/flexio0/shifterr.rs b/mcxa276-pac/src/flexio0/shifterr.rs deleted file mode 100644 index 11329f918..000000000 --- a/mcxa276-pac/src/flexio0/shifterr.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `SHIFTERR` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTERR` writer"] -pub type W = crate::W; -#[doc = "Shifter Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sef { - #[doc = "0: Clear"] - Clr = 0, - #[doc = "1: Set"] - Set = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sef) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sef { - type Ux = u8; -} -impl crate::IsEnum for Sef {} -#[doc = "Field `SEF` reader - Shifter Error Flag"] -pub type SefR = crate::FieldReader; -impl SefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Sef::Clr), - 1 => Some(Sef::Set), - _ => None, - } - } - #[doc = "Clear"] - #[inline(always)] - pub fn is_clr(&self) -> bool { - *self == Sef::Clr - } - #[doc = "Set"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Sef::Set - } -} -#[doc = "Field `SEF` writer - Shifter Error Flag"] -pub type SefW<'a, REG> = crate::FieldWriter<'a, REG, 4, Sef>; -impl<'a, REG> SefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Clear"] - #[inline(always)] - pub fn clr(self) -> &'a mut crate::W { - self.variant(Sef::Clr) - } - #[doc = "Set"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Sef::Set) - } -} -impl R { - #[doc = "Bits 0:3 - Shifter Error Flag"] - #[inline(always)] - pub fn sef(&self) -> SefR { - SefR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Shifter Error Flag"] - #[inline(always)] - pub fn sef(&mut self) -> SefW { - SefW::new(self, 0) - } -} -#[doc = "Shifter Error\n\nYou can [`read`](crate::Reg::read) this register and get [`shifterr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shifterr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShifterrSpec; -impl crate::RegisterSpec for ShifterrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shifterr::R`](R) reader structure"] -impl crate::Readable for ShifterrSpec {} -#[doc = "`write(|w| ..)` method takes [`shifterr::W`](W) writer structure"] -impl crate::Writable for ShifterrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; -} -#[doc = "`reset()` method sets SHIFTERR to value 0"] -impl crate::Resettable for ShifterrSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftsden.rs b/mcxa276-pac/src/flexio0/shiftsden.rs deleted file mode 100644 index fd7127afb..000000000 --- a/mcxa276-pac/src/flexio0/shiftsden.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTSDEN` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTSDEN` writer"] -pub type W = crate::W; -#[doc = "Field `SSDE` reader - Shifter Status DMA Enable"] -pub type SsdeR = crate::FieldReader; -#[doc = "Field `SSDE` writer - Shifter Status DMA Enable"] -pub type SsdeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Shifter Status DMA Enable"] - #[inline(always)] - pub fn ssde(&self) -> SsdeR { - SsdeR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Shifter Status DMA Enable"] - #[inline(always)] - pub fn ssde(&mut self) -> SsdeW { - SsdeW::new(self, 0) - } -} -#[doc = "Shifter Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsden::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsden::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftsdenSpec; -impl crate::RegisterSpec for ShiftsdenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftsden::R`](R) reader structure"] -impl crate::Readable for ShiftsdenSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftsden::W`](W) writer structure"] -impl crate::Writable for ShiftsdenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTSDEN to value 0"] -impl crate::Resettable for ShiftsdenSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftsien.rs b/mcxa276-pac/src/flexio0/shiftsien.rs deleted file mode 100644 index 455485028..000000000 --- a/mcxa276-pac/src/flexio0/shiftsien.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTSIEN` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTSIEN` writer"] -pub type W = crate::W; -#[doc = "Field `SSIE` reader - Shifter Status Interrupt Enable"] -pub type SsieR = crate::FieldReader; -#[doc = "Field `SSIE` writer - Shifter Status Interrupt Enable"] -pub type SsieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"] - #[inline(always)] - pub fn ssie(&self) -> SsieR { - SsieR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"] - #[inline(always)] - pub fn ssie(&mut self) -> SsieW { - SsieW::new(self, 0) - } -} -#[doc = "Shifter Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftsienSpec; -impl crate::RegisterSpec for ShiftsienSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftsien::R`](R) reader structure"] -impl crate::Readable for ShiftsienSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftsien::W`](W) writer structure"] -impl crate::Writable for ShiftsienSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTSIEN to value 0"] -impl crate::Resettable for ShiftsienSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftstat.rs b/mcxa276-pac/src/flexio0/shiftstat.rs deleted file mode 100644 index 514033f6f..000000000 --- a/mcxa276-pac/src/flexio0/shiftstat.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `SHIFTSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTSTAT` writer"] -pub type W = crate::W; -#[doc = "Shifter Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ssf { - #[doc = "0: Clear"] - Clr = 0, - #[doc = "1: Set"] - Set = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ssf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ssf { - type Ux = u8; -} -impl crate::IsEnum for Ssf {} -#[doc = "Field `SSF` reader - Shifter Status Flag"] -pub type SsfR = crate::FieldReader; -impl SsfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ssf::Clr), - 1 => Some(Ssf::Set), - _ => None, - } - } - #[doc = "Clear"] - #[inline(always)] - pub fn is_clr(&self) -> bool { - *self == Ssf::Clr - } - #[doc = "Set"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Ssf::Set - } -} -#[doc = "Field `SSF` writer - Shifter Status Flag"] -pub type SsfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ssf>; -impl<'a, REG> SsfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Clear"] - #[inline(always)] - pub fn clr(self) -> &'a mut crate::W { - self.variant(Ssf::Clr) - } - #[doc = "Set"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Ssf::Set) - } -} -impl R { - #[doc = "Bits 0:3 - Shifter Status Flag"] - #[inline(always)] - pub fn ssf(&self) -> SsfR { - SsfR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Shifter Status Flag"] - #[inline(always)] - pub fn ssf(&mut self) -> SsfW { - SsfW::new(self, 0) - } -} -#[doc = "Shifter Status\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftstatSpec; -impl crate::RegisterSpec for ShiftstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftstat::R`](R) reader structure"] -impl crate::Readable for ShiftstatSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftstat::W`](W) writer structure"] -impl crate::Writable for ShiftstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; -} -#[doc = "`reset()` method sets SHIFTSTAT to value 0"] -impl crate::Resettable for ShiftstatSpec {} diff --git a/mcxa276-pac/src/flexio0/shiftstate.rs b/mcxa276-pac/src/flexio0/shiftstate.rs deleted file mode 100644 index a3578c3b8..000000000 --- a/mcxa276-pac/src/flexio0/shiftstate.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SHIFTSTATE` reader"] -pub type R = crate::R; -#[doc = "Register `SHIFTSTATE` writer"] -pub type W = crate::W; -#[doc = "Field `STATE` reader - Current State Pointer"] -pub type StateR = crate::FieldReader; -#[doc = "Field `STATE` writer - Current State Pointer"] -pub type StateW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2 - Current State Pointer"] - #[inline(always)] - pub fn state(&self) -> StateR { - StateR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Current State Pointer"] - #[inline(always)] - pub fn state(&mut self) -> StateW { - StateW::new(self, 0) - } -} -#[doc = "Shifter State\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftstate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftstate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ShiftstateSpec; -impl crate::RegisterSpec for ShiftstateSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`shiftstate::R`](R) reader structure"] -impl crate::Readable for ShiftstateSpec {} -#[doc = "`write(|w| ..)` method takes [`shiftstate::W`](W) writer structure"] -impl crate::Writable for ShiftstateSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SHIFTSTATE to value 0"] -impl crate::Resettable for ShiftstateSpec {} diff --git a/mcxa276-pac/src/flexio0/timcfg.rs b/mcxa276-pac/src/flexio0/timcfg.rs deleted file mode 100644 index 6b4c19875..000000000 --- a/mcxa276-pac/src/flexio0/timcfg.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `TIMCFG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `TIMCFG[%s]` writer"] -pub type W = crate::W; -#[doc = "Timer Start\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tstart { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tstart) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TSTART` reader - Timer Start"] -pub type TstartR = crate::BitReader; -impl TstartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tstart { - match self.bits { - false => Tstart::Disable, - true => Tstart::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tstart::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tstart::Enable - } -} -#[doc = "Field `TSTART` writer - Timer Start"] -pub type TstartW<'a, REG> = crate::BitWriter<'a, REG, Tstart>; -impl<'a, REG> TstartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tstart::Disable) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tstart::Enable) - } -} -#[doc = "Timer Stop\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tstop { - #[doc = "0: Disabled"] - StopDisable = 0, - #[doc = "1: Enabled on timer compare"] - EnableTmrcmp = 1, - #[doc = "2: Enabled on timer disable"] - EnableTmrdisable = 2, - #[doc = "3: Enabled on timer compare and timer disable"] - EnableTmrCmpDis = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tstop) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tstop { - type Ux = u8; -} -impl crate::IsEnum for Tstop {} -#[doc = "Field `TSTOP` reader - Timer Stop"] -pub type TstopR = crate::FieldReader; -impl TstopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tstop { - match self.bits { - 0 => Tstop::StopDisable, - 1 => Tstop::EnableTmrcmp, - 2 => Tstop::EnableTmrdisable, - 3 => Tstop::EnableTmrCmpDis, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_stop_disable(&self) -> bool { - *self == Tstop::StopDisable - } - #[doc = "Enabled on timer compare"] - #[inline(always)] - pub fn is_enable_tmrcmp(&self) -> bool { - *self == Tstop::EnableTmrcmp - } - #[doc = "Enabled on timer disable"] - #[inline(always)] - pub fn is_enable_tmrdisable(&self) -> bool { - *self == Tstop::EnableTmrdisable - } - #[doc = "Enabled on timer compare and timer disable"] - #[inline(always)] - pub fn is_enable_tmr_cmp_dis(&self) -> bool { - *self == Tstop::EnableTmrCmpDis - } -} -#[doc = "Field `TSTOP` writer - Timer Stop"] -pub type TstopW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tstop, crate::Safe>; -impl<'a, REG> TstopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn stop_disable(self) -> &'a mut crate::W { - self.variant(Tstop::StopDisable) - } - #[doc = "Enabled on timer compare"] - #[inline(always)] - pub fn enable_tmrcmp(self) -> &'a mut crate::W { - self.variant(Tstop::EnableTmrcmp) - } - #[doc = "Enabled on timer disable"] - #[inline(always)] - pub fn enable_tmrdisable(self) -> &'a mut crate::W { - self.variant(Tstop::EnableTmrdisable) - } - #[doc = "Enabled on timer compare and timer disable"] - #[inline(always)] - pub fn enable_tmr_cmp_dis(self) -> &'a mut crate::W { - self.variant(Tstop::EnableTmrCmpDis) - } -} -#[doc = "Timer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Timena { - #[doc = "0: Timer always enabled"] - Enable = 0, - #[doc = "1: Timer enabled on timer n-1 enable"] - TmrNminus1En = 1, - #[doc = "2: Timer enabled on trigger high"] - TmrTrighiEn = 2, - #[doc = "3: Timer enabled on trigger high and pin high"] - TmrTrigPinHiEn = 3, - #[doc = "4: Timer enabled on pin rising edge"] - TmrPinriseEn = 4, - #[doc = "5: Timer enabled on pin rising edge and trigger high"] - TmrPinriseTrighiEn = 5, - #[doc = "6: Timer enabled on trigger rising edge"] - TmrTrigriseEn = 6, - #[doc = "7: Timer enabled on trigger rising or falling edge"] - TmrTrigedgeEn = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Timena) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Timena { - type Ux = u8; -} -impl crate::IsEnum for Timena {} -#[doc = "Field `TIMENA` reader - Timer Enable"] -pub type TimenaR = crate::FieldReader; -impl TimenaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timena { - match self.bits { - 0 => Timena::Enable, - 1 => Timena::TmrNminus1En, - 2 => Timena::TmrTrighiEn, - 3 => Timena::TmrTrigPinHiEn, - 4 => Timena::TmrPinriseEn, - 5 => Timena::TmrPinriseTrighiEn, - 6 => Timena::TmrTrigriseEn, - 7 => Timena::TmrTrigedgeEn, - _ => unreachable!(), - } - } - #[doc = "Timer always enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Timena::Enable - } - #[doc = "Timer enabled on timer n-1 enable"] - #[inline(always)] - pub fn is_tmr_nminus1_en(&self) -> bool { - *self == Timena::TmrNminus1En - } - #[doc = "Timer enabled on trigger high"] - #[inline(always)] - pub fn is_tmr_trighi_en(&self) -> bool { - *self == Timena::TmrTrighiEn - } - #[doc = "Timer enabled on trigger high and pin high"] - #[inline(always)] - pub fn is_tmr_trig_pin_hi_en(&self) -> bool { - *self == Timena::TmrTrigPinHiEn - } - #[doc = "Timer enabled on pin rising edge"] - #[inline(always)] - pub fn is_tmr_pinrise_en(&self) -> bool { - *self == Timena::TmrPinriseEn - } - #[doc = "Timer enabled on pin rising edge and trigger high"] - #[inline(always)] - pub fn is_tmr_pinrise_trighi_en(&self) -> bool { - *self == Timena::TmrPinriseTrighiEn - } - #[doc = "Timer enabled on trigger rising edge"] - #[inline(always)] - pub fn is_tmr_trigrise_en(&self) -> bool { - *self == Timena::TmrTrigriseEn - } - #[doc = "Timer enabled on trigger rising or falling edge"] - #[inline(always)] - pub fn is_tmr_trigedge_en(&self) -> bool { - *self == Timena::TmrTrigedgeEn - } -} -#[doc = "Field `TIMENA` writer - Timer Enable"] -pub type TimenaW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timena, crate::Safe>; -impl<'a, REG> TimenaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer always enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Timena::Enable) - } - #[doc = "Timer enabled on timer n-1 enable"] - #[inline(always)] - pub fn tmr_nminus1_en(self) -> &'a mut crate::W { - self.variant(Timena::TmrNminus1En) - } - #[doc = "Timer enabled on trigger high"] - #[inline(always)] - pub fn tmr_trighi_en(self) -> &'a mut crate::W { - self.variant(Timena::TmrTrighiEn) - } - #[doc = "Timer enabled on trigger high and pin high"] - #[inline(always)] - pub fn tmr_trig_pin_hi_en(self) -> &'a mut crate::W { - self.variant(Timena::TmrTrigPinHiEn) - } - #[doc = "Timer enabled on pin rising edge"] - #[inline(always)] - pub fn tmr_pinrise_en(self) -> &'a mut crate::W { - self.variant(Timena::TmrPinriseEn) - } - #[doc = "Timer enabled on pin rising edge and trigger high"] - #[inline(always)] - pub fn tmr_pinrise_trighi_en(self) -> &'a mut crate::W { - self.variant(Timena::TmrPinriseTrighiEn) - } - #[doc = "Timer enabled on trigger rising edge"] - #[inline(always)] - pub fn tmr_trigrise_en(self) -> &'a mut crate::W { - self.variant(Timena::TmrTrigriseEn) - } - #[doc = "Timer enabled on trigger rising or falling edge"] - #[inline(always)] - pub fn tmr_trigedge_en(self) -> &'a mut crate::W { - self.variant(Timena::TmrTrigedgeEn) - } -} -#[doc = "Timer Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Timdis { - #[doc = "0: Timer never disabled"] - Never = 0, - #[doc = "1: Timer disabled on timer n-1 disable"] - TmrNminus1 = 1, - #[doc = "2: Timer disabled on timer compare (upper 8 bits match and decrement)"] - TmrCmp = 2, - #[doc = "3: Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"] - TmrCmpTriglow = 3, - #[doc = "4: Timer disabled on pin rising or falling edge"] - PinEdge = 4, - #[doc = "5: Timer disabled on pin rising or falling edge provided trigger is high"] - PinEdgeTrighi = 5, - #[doc = "6: Timer disabled on trigger falling edge"] - TrigFalledge = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Timdis) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Timdis { - type Ux = u8; -} -impl crate::IsEnum for Timdis {} -#[doc = "Field `TIMDIS` reader - Timer Disable"] -pub type TimdisR = crate::FieldReader; -impl TimdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Timdis::Never), - 1 => Some(Timdis::TmrNminus1), - 2 => Some(Timdis::TmrCmp), - 3 => Some(Timdis::TmrCmpTriglow), - 4 => Some(Timdis::PinEdge), - 5 => Some(Timdis::PinEdgeTrighi), - 6 => Some(Timdis::TrigFalledge), - _ => None, - } - } - #[doc = "Timer never disabled"] - #[inline(always)] - pub fn is_never(&self) -> bool { - *self == Timdis::Never - } - #[doc = "Timer disabled on timer n-1 disable"] - #[inline(always)] - pub fn is_tmr_nminus1(&self) -> bool { - *self == Timdis::TmrNminus1 - } - #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement)"] - #[inline(always)] - pub fn is_tmr_cmp(&self) -> bool { - *self == Timdis::TmrCmp - } - #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"] - #[inline(always)] - pub fn is_tmr_cmp_triglow(&self) -> bool { - *self == Timdis::TmrCmpTriglow - } - #[doc = "Timer disabled on pin rising or falling edge"] - #[inline(always)] - pub fn is_pin_edge(&self) -> bool { - *self == Timdis::PinEdge - } - #[doc = "Timer disabled on pin rising or falling edge provided trigger is high"] - #[inline(always)] - pub fn is_pin_edge_trighi(&self) -> bool { - *self == Timdis::PinEdgeTrighi - } - #[doc = "Timer disabled on trigger falling edge"] - #[inline(always)] - pub fn is_trig_falledge(&self) -> bool { - *self == Timdis::TrigFalledge - } -} -#[doc = "Field `TIMDIS` writer - Timer Disable"] -pub type TimdisW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timdis>; -impl<'a, REG> TimdisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer never disabled"] - #[inline(always)] - pub fn never(self) -> &'a mut crate::W { - self.variant(Timdis::Never) - } - #[doc = "Timer disabled on timer n-1 disable"] - #[inline(always)] - pub fn tmr_nminus1(self) -> &'a mut crate::W { - self.variant(Timdis::TmrNminus1) - } - #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement)"] - #[inline(always)] - pub fn tmr_cmp(self) -> &'a mut crate::W { - self.variant(Timdis::TmrCmp) - } - #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"] - #[inline(always)] - pub fn tmr_cmp_triglow(self) -> &'a mut crate::W { - self.variant(Timdis::TmrCmpTriglow) - } - #[doc = "Timer disabled on pin rising or falling edge"] - #[inline(always)] - pub fn pin_edge(self) -> &'a mut crate::W { - self.variant(Timdis::PinEdge) - } - #[doc = "Timer disabled on pin rising or falling edge provided trigger is high"] - #[inline(always)] - pub fn pin_edge_trighi(self) -> &'a mut crate::W { - self.variant(Timdis::PinEdgeTrighi) - } - #[doc = "Timer disabled on trigger falling edge"] - #[inline(always)] - pub fn trig_falledge(self) -> &'a mut crate::W { - self.variant(Timdis::TrigFalledge) - } -} -#[doc = "Timer Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Timrst { - #[doc = "0: Never reset timer"] - Never = 0, - #[doc = "1: Timer reset on timer output high."] - TmrOutHi = 1, - #[doc = "2: Timer reset on timer pin equal to timer output"] - PinEqTmrOut = 2, - #[doc = "3: Timer reset on timer trigger equal to timer output"] - TrigEqTmrOut = 3, - #[doc = "4: Timer reset on timer pin rising edge"] - PinRiseEdge = 4, - #[doc = "6: Timer reset on trigger rising edge"] - TrigRiseEdge = 6, - #[doc = "7: Timer reset on trigger rising or falling edge"] - TrigEdge = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Timrst) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Timrst { - type Ux = u8; -} -impl crate::IsEnum for Timrst {} -#[doc = "Field `TIMRST` reader - Timer Reset"] -pub type TimrstR = crate::FieldReader; -impl TimrstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Timrst::Never), - 1 => Some(Timrst::TmrOutHi), - 2 => Some(Timrst::PinEqTmrOut), - 3 => Some(Timrst::TrigEqTmrOut), - 4 => Some(Timrst::PinRiseEdge), - 6 => Some(Timrst::TrigRiseEdge), - 7 => Some(Timrst::TrigEdge), - _ => None, - } - } - #[doc = "Never reset timer"] - #[inline(always)] - pub fn is_never(&self) -> bool { - *self == Timrst::Never - } - #[doc = "Timer reset on timer output high."] - #[inline(always)] - pub fn is_tmr_out_hi(&self) -> bool { - *self == Timrst::TmrOutHi - } - #[doc = "Timer reset on timer pin equal to timer output"] - #[inline(always)] - pub fn is_pin_eq_tmr_out(&self) -> bool { - *self == Timrst::PinEqTmrOut - } - #[doc = "Timer reset on timer trigger equal to timer output"] - #[inline(always)] - pub fn is_trig_eq_tmr_out(&self) -> bool { - *self == Timrst::TrigEqTmrOut - } - #[doc = "Timer reset on timer pin rising edge"] - #[inline(always)] - pub fn is_pin_rise_edge(&self) -> bool { - *self == Timrst::PinRiseEdge - } - #[doc = "Timer reset on trigger rising edge"] - #[inline(always)] - pub fn is_trig_rise_edge(&self) -> bool { - *self == Timrst::TrigRiseEdge - } - #[doc = "Timer reset on trigger rising or falling edge"] - #[inline(always)] - pub fn is_trig_edge(&self) -> bool { - *self == Timrst::TrigEdge - } -} -#[doc = "Field `TIMRST` writer - Timer Reset"] -pub type TimrstW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timrst>; -impl<'a, REG> TimrstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Never reset timer"] - #[inline(always)] - pub fn never(self) -> &'a mut crate::W { - self.variant(Timrst::Never) - } - #[doc = "Timer reset on timer output high."] - #[inline(always)] - pub fn tmr_out_hi(self) -> &'a mut crate::W { - self.variant(Timrst::TmrOutHi) - } - #[doc = "Timer reset on timer pin equal to timer output"] - #[inline(always)] - pub fn pin_eq_tmr_out(self) -> &'a mut crate::W { - self.variant(Timrst::PinEqTmrOut) - } - #[doc = "Timer reset on timer trigger equal to timer output"] - #[inline(always)] - pub fn trig_eq_tmr_out(self) -> &'a mut crate::W { - self.variant(Timrst::TrigEqTmrOut) - } - #[doc = "Timer reset on timer pin rising edge"] - #[inline(always)] - pub fn pin_rise_edge(self) -> &'a mut crate::W { - self.variant(Timrst::PinRiseEdge) - } - #[doc = "Timer reset on trigger rising edge"] - #[inline(always)] - pub fn trig_rise_edge(self) -> &'a mut crate::W { - self.variant(Timrst::TrigRiseEdge) - } - #[doc = "Timer reset on trigger rising or falling edge"] - #[inline(always)] - pub fn trig_edge(self) -> &'a mut crate::W { - self.variant(Timrst::TrigEdge) - } -} -#[doc = "Timer Decrement\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Timdec { - #[doc = "0: Decrement counter on FLEXIO clock; shift clock equals timer output"] - FlexioClkShiftclkTmrOut = 0, - #[doc = "1: Decrement counter on trigger input (both edges); shift clock equals timer output"] - TrigEdgeShiftclkTmrOut = 1, - #[doc = "2: Decrement counter on pin input (both edges); shift clock equals pin input"] - PinEdgeShiftclkTmrOut = 2, - #[doc = "3: Decrement counter on trigger input (both edges); shift clock equals trigger input"] - TrigEdgeShiftclkTrigIn = 3, - #[doc = "4: Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"] - FlexioClkDiv16ShiftclkTmrOut = 4, - #[doc = "5: Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"] - FlexioClkDiv256ShiftclkTmrOut = 5, - #[doc = "6: Decrement counter on pin input (rising edge); shift clock equals pin input"] - PinRiseShiftclkPinIn = 6, - #[doc = "7: Decrement counter on trigger input (rising edge); shift clock equals trigger input"] - TrigRiseShiftclkTrigIn = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Timdec) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Timdec { - type Ux = u8; -} -impl crate::IsEnum for Timdec {} -#[doc = "Field `TIMDEC` reader - Timer Decrement"] -pub type TimdecR = crate::FieldReader; -impl TimdecR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timdec { - match self.bits { - 0 => Timdec::FlexioClkShiftclkTmrOut, - 1 => Timdec::TrigEdgeShiftclkTmrOut, - 2 => Timdec::PinEdgeShiftclkTmrOut, - 3 => Timdec::TrigEdgeShiftclkTrigIn, - 4 => Timdec::FlexioClkDiv16ShiftclkTmrOut, - 5 => Timdec::FlexioClkDiv256ShiftclkTmrOut, - 6 => Timdec::PinRiseShiftclkPinIn, - 7 => Timdec::TrigRiseShiftclkTrigIn, - _ => unreachable!(), - } - } - #[doc = "Decrement counter on FLEXIO clock; shift clock equals timer output"] - #[inline(always)] - pub fn is_flexio_clk_shiftclk_tmr_out(&self) -> bool { - *self == Timdec::FlexioClkShiftclkTmrOut - } - #[doc = "Decrement counter on trigger input (both edges); shift clock equals timer output"] - #[inline(always)] - pub fn is_trig_edge_shiftclk_tmr_out(&self) -> bool { - *self == Timdec::TrigEdgeShiftclkTmrOut - } - #[doc = "Decrement counter on pin input (both edges); shift clock equals pin input"] - #[inline(always)] - pub fn is_pin_edge_shiftclk_tmr_out(&self) -> bool { - *self == Timdec::PinEdgeShiftclkTmrOut - } - #[doc = "Decrement counter on trigger input (both edges); shift clock equals trigger input"] - #[inline(always)] - pub fn is_trig_edge_shiftclk_trig_in(&self) -> bool { - *self == Timdec::TrigEdgeShiftclkTrigIn - } - #[doc = "Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"] - #[inline(always)] - pub fn is_flexio_clk_div16_shiftclk_tmr_out(&self) -> bool { - *self == Timdec::FlexioClkDiv16ShiftclkTmrOut - } - #[doc = "Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"] - #[inline(always)] - pub fn is_flexio_clk_div256_shiftclk_tmr_out(&self) -> bool { - *self == Timdec::FlexioClkDiv256ShiftclkTmrOut - } - #[doc = "Decrement counter on pin input (rising edge); shift clock equals pin input"] - #[inline(always)] - pub fn is_pin_rise_shiftclk_pin_in(&self) -> bool { - *self == Timdec::PinRiseShiftclkPinIn - } - #[doc = "Decrement counter on trigger input (rising edge); shift clock equals trigger input"] - #[inline(always)] - pub fn is_trig_rise_shiftclk_trig_in(&self) -> bool { - *self == Timdec::TrigRiseShiftclkTrigIn - } -} -#[doc = "Field `TIMDEC` writer - Timer Decrement"] -pub type TimdecW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timdec, crate::Safe>; -impl<'a, REG> TimdecW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Decrement counter on FLEXIO clock; shift clock equals timer output"] - #[inline(always)] - pub fn flexio_clk_shiftclk_tmr_out(self) -> &'a mut crate::W { - self.variant(Timdec::FlexioClkShiftclkTmrOut) - } - #[doc = "Decrement counter on trigger input (both edges); shift clock equals timer output"] - #[inline(always)] - pub fn trig_edge_shiftclk_tmr_out(self) -> &'a mut crate::W { - self.variant(Timdec::TrigEdgeShiftclkTmrOut) - } - #[doc = "Decrement counter on pin input (both edges); shift clock equals pin input"] - #[inline(always)] - pub fn pin_edge_shiftclk_tmr_out(self) -> &'a mut crate::W { - self.variant(Timdec::PinEdgeShiftclkTmrOut) - } - #[doc = "Decrement counter on trigger input (both edges); shift clock equals trigger input"] - #[inline(always)] - pub fn trig_edge_shiftclk_trig_in(self) -> &'a mut crate::W { - self.variant(Timdec::TrigEdgeShiftclkTrigIn) - } - #[doc = "Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"] - #[inline(always)] - pub fn flexio_clk_div16_shiftclk_tmr_out(self) -> &'a mut crate::W { - self.variant(Timdec::FlexioClkDiv16ShiftclkTmrOut) - } - #[doc = "Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"] - #[inline(always)] - pub fn flexio_clk_div256_shiftclk_tmr_out(self) -> &'a mut crate::W { - self.variant(Timdec::FlexioClkDiv256ShiftclkTmrOut) - } - #[doc = "Decrement counter on pin input (rising edge); shift clock equals pin input"] - #[inline(always)] - pub fn pin_rise_shiftclk_pin_in(self) -> &'a mut crate::W { - self.variant(Timdec::PinRiseShiftclkPinIn) - } - #[doc = "Decrement counter on trigger input (rising edge); shift clock equals trigger input"] - #[inline(always)] - pub fn trig_rise_shiftclk_trig_in(self) -> &'a mut crate::W { - self.variant(Timdec::TrigRiseShiftclkTrigIn) - } -} -#[doc = "Timer Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Timout { - #[doc = "0: Logic one when enabled; not affected by timer reset"] - One = 0, - #[doc = "1: Logic zero when enabled; not affected by timer reset"] - Zero = 1, - #[doc = "2: Logic one when enabled and on timer reset"] - OneTmrreset = 2, - #[doc = "3: Logic zero when enabled and on timer reset"] - ZeroTmrreset = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Timout) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Timout { - type Ux = u8; -} -impl crate::IsEnum for Timout {} -#[doc = "Field `TIMOUT` reader - Timer Output"] -pub type TimoutR = crate::FieldReader; -impl TimoutR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timout { - match self.bits { - 0 => Timout::One, - 1 => Timout::Zero, - 2 => Timout::OneTmrreset, - 3 => Timout::ZeroTmrreset, - _ => unreachable!(), - } - } - #[doc = "Logic one when enabled; not affected by timer reset"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Timout::One - } - #[doc = "Logic zero when enabled; not affected by timer reset"] - #[inline(always)] - pub fn is_zero(&self) -> bool { - *self == Timout::Zero - } - #[doc = "Logic one when enabled and on timer reset"] - #[inline(always)] - pub fn is_one_tmrreset(&self) -> bool { - *self == Timout::OneTmrreset - } - #[doc = "Logic zero when enabled and on timer reset"] - #[inline(always)] - pub fn is_zero_tmrreset(&self) -> bool { - *self == Timout::ZeroTmrreset - } -} -#[doc = "Field `TIMOUT` writer - Timer Output"] -pub type TimoutW<'a, REG> = crate::FieldWriter<'a, REG, 2, Timout, crate::Safe>; -impl<'a, REG> TimoutW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Logic one when enabled; not affected by timer reset"] - #[inline(always)] - pub fn one(self) -> &'a mut crate::W { - self.variant(Timout::One) - } - #[doc = "Logic zero when enabled; not affected by timer reset"] - #[inline(always)] - pub fn zero(self) -> &'a mut crate::W { - self.variant(Timout::Zero) - } - #[doc = "Logic one when enabled and on timer reset"] - #[inline(always)] - pub fn one_tmrreset(self) -> &'a mut crate::W { - self.variant(Timout::OneTmrreset) - } - #[doc = "Logic zero when enabled and on timer reset"] - #[inline(always)] - pub fn zero_tmrreset(self) -> &'a mut crate::W { - self.variant(Timout::ZeroTmrreset) - } -} -impl R { - #[doc = "Bit 1 - Timer Start"] - #[inline(always)] - pub fn tstart(&self) -> TstartR { - TstartR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 4:5 - Timer Stop"] - #[inline(always)] - pub fn tstop(&self) -> TstopR { - TstopR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 8:10 - Timer Enable"] - #[inline(always)] - pub fn timena(&self) -> TimenaR { - TimenaR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 12:14 - Timer Disable"] - #[inline(always)] - pub fn timdis(&self) -> TimdisR { - TimdisR::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bits 16:18 - Timer Reset"] - #[inline(always)] - pub fn timrst(&self) -> TimrstR { - TimrstR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 20:22 - Timer Decrement"] - #[inline(always)] - pub fn timdec(&self) -> TimdecR { - TimdecR::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bits 24:25 - Timer Output"] - #[inline(always)] - pub fn timout(&self) -> TimoutR { - TimoutR::new(((self.bits >> 24) & 3) as u8) - } -} -impl W { - #[doc = "Bit 1 - Timer Start"] - #[inline(always)] - pub fn tstart(&mut self) -> TstartW { - TstartW::new(self, 1) - } - #[doc = "Bits 4:5 - Timer Stop"] - #[inline(always)] - pub fn tstop(&mut self) -> TstopW { - TstopW::new(self, 4) - } - #[doc = "Bits 8:10 - Timer Enable"] - #[inline(always)] - pub fn timena(&mut self) -> TimenaW { - TimenaW::new(self, 8) - } - #[doc = "Bits 12:14 - Timer Disable"] - #[inline(always)] - pub fn timdis(&mut self) -> TimdisW { - TimdisW::new(self, 12) - } - #[doc = "Bits 16:18 - Timer Reset"] - #[inline(always)] - pub fn timrst(&mut self) -> TimrstW { - TimrstW::new(self, 16) - } - #[doc = "Bits 20:22 - Timer Decrement"] - #[inline(always)] - pub fn timdec(&mut self) -> TimdecW { - TimdecW::new(self, 20) - } - #[doc = "Bits 24:25 - Timer Output"] - #[inline(always)] - pub fn timout(&mut self) -> TimoutW { - TimoutW::new(self, 24) - } -} -#[doc = "Timer Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`timcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TimcfgSpec; -impl crate::RegisterSpec for TimcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timcfg::R`](R) reader structure"] -impl crate::Readable for TimcfgSpec {} -#[doc = "`write(|w| ..)` method takes [`timcfg::W`](W) writer structure"] -impl crate::Writable for TimcfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMCFG[%s] to value 0"] -impl crate::Resettable for TimcfgSpec {} diff --git a/mcxa276-pac/src/flexio0/timcmp.rs b/mcxa276-pac/src/flexio0/timcmp.rs deleted file mode 100644 index 24ba62c6d..000000000 --- a/mcxa276-pac/src/flexio0/timcmp.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TIMCMP[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `TIMCMP[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `CMP` reader - Timer Compare Value"] -pub type CmpR = crate::FieldReader; -#[doc = "Field `CMP` writer - Timer Compare Value"] -pub type CmpW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Timer Compare Value"] - #[inline(always)] - pub fn cmp(&self) -> CmpR { - CmpR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Timer Compare Value"] - #[inline(always)] - pub fn cmp(&mut self) -> CmpW { - CmpW::new(self, 0) - } -} -#[doc = "Timer Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`timcmp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcmp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TimcmpSpec; -impl crate::RegisterSpec for TimcmpSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timcmp::R`](R) reader structure"] -impl crate::Readable for TimcmpSpec {} -#[doc = "`write(|w| ..)` method takes [`timcmp::W`](W) writer structure"] -impl crate::Writable for TimcmpSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMCMP[%s] to value 0"] -impl crate::Resettable for TimcmpSpec {} diff --git a/mcxa276-pac/src/flexio0/timctl.rs b/mcxa276-pac/src/flexio0/timctl.rs deleted file mode 100644 index 333ef6ad1..000000000 --- a/mcxa276-pac/src/flexio0/timctl.rs +++ /dev/null @@ -1,608 +0,0 @@ -#[doc = "Register `TIMCTL[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `TIMCTL[%s]` writer"] -pub type W = crate::W; -#[doc = "Timer Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Timod { - #[doc = "0: Timer disabled"] - Disable = 0, - #[doc = "1: Dual 8-bit counters baud mode"] - Dual8bitBaud = 1, - #[doc = "2: Dual 8-bit counters PWM high mode"] - Dual8bitPwmH = 2, - #[doc = "3: Single 16-bit counter mode"] - Single16bit = 3, - #[doc = "4: Single 16-bit counter disable mode"] - Single16bitDisable = 4, - #[doc = "5: Dual 8-bit counters word mode"] - Dual8bitWord = 5, - #[doc = "6: Dual 8-bit counters PWM low mode"] - Dual8bitPwmL = 6, - #[doc = "7: Single 16-bit input capture mode"] - Single16bitInCapture = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Timod) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Timod { - type Ux = u8; -} -impl crate::IsEnum for Timod {} -#[doc = "Field `TIMOD` reader - Timer Mode"] -pub type TimodR = crate::FieldReader; -impl TimodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timod { - match self.bits { - 0 => Timod::Disable, - 1 => Timod::Dual8bitBaud, - 2 => Timod::Dual8bitPwmH, - 3 => Timod::Single16bit, - 4 => Timod::Single16bitDisable, - 5 => Timod::Dual8bitWord, - 6 => Timod::Dual8bitPwmL, - 7 => Timod::Single16bitInCapture, - _ => unreachable!(), - } - } - #[doc = "Timer disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Timod::Disable - } - #[doc = "Dual 8-bit counters baud mode"] - #[inline(always)] - pub fn is_dual8bit_baud(&self) -> bool { - *self == Timod::Dual8bitBaud - } - #[doc = "Dual 8-bit counters PWM high mode"] - #[inline(always)] - pub fn is_dual8bit_pwm_h(&self) -> bool { - *self == Timod::Dual8bitPwmH - } - #[doc = "Single 16-bit counter mode"] - #[inline(always)] - pub fn is_single16bit(&self) -> bool { - *self == Timod::Single16bit - } - #[doc = "Single 16-bit counter disable mode"] - #[inline(always)] - pub fn is_single16bit_disable(&self) -> bool { - *self == Timod::Single16bitDisable - } - #[doc = "Dual 8-bit counters word mode"] - #[inline(always)] - pub fn is_dual8bit_word(&self) -> bool { - *self == Timod::Dual8bitWord - } - #[doc = "Dual 8-bit counters PWM low mode"] - #[inline(always)] - pub fn is_dual8bit_pwm_l(&self) -> bool { - *self == Timod::Dual8bitPwmL - } - #[doc = "Single 16-bit input capture mode"] - #[inline(always)] - pub fn is_single16bit_in_capture(&self) -> bool { - *self == Timod::Single16bitInCapture - } -} -#[doc = "Field `TIMOD` writer - Timer Mode"] -pub type TimodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timod, crate::Safe>; -impl<'a, REG> TimodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Timod::Disable) - } - #[doc = "Dual 8-bit counters baud mode"] - #[inline(always)] - pub fn dual8bit_baud(self) -> &'a mut crate::W { - self.variant(Timod::Dual8bitBaud) - } - #[doc = "Dual 8-bit counters PWM high mode"] - #[inline(always)] - pub fn dual8bit_pwm_h(self) -> &'a mut crate::W { - self.variant(Timod::Dual8bitPwmH) - } - #[doc = "Single 16-bit counter mode"] - #[inline(always)] - pub fn single16bit(self) -> &'a mut crate::W { - self.variant(Timod::Single16bit) - } - #[doc = "Single 16-bit counter disable mode"] - #[inline(always)] - pub fn single16bit_disable(self) -> &'a mut crate::W { - self.variant(Timod::Single16bitDisable) - } - #[doc = "Dual 8-bit counters word mode"] - #[inline(always)] - pub fn dual8bit_word(self) -> &'a mut crate::W { - self.variant(Timod::Dual8bitWord) - } - #[doc = "Dual 8-bit counters PWM low mode"] - #[inline(always)] - pub fn dual8bit_pwm_l(self) -> &'a mut crate::W { - self.variant(Timod::Dual8bitPwmL) - } - #[doc = "Single 16-bit input capture mode"] - #[inline(always)] - pub fn single16bit_in_capture(self) -> &'a mut crate::W { - self.variant(Timod::Single16bitInCapture) - } -} -#[doc = "Timer One Time Operation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Onetim { - #[doc = "0: Generate the timer enable event as normal"] - NotBlocked = 0, - #[doc = "1: Block the timer enable event unless the timer status flag is clear"] - Blocked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Onetim) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONETIM` reader - Timer One Time Operation"] -pub type OnetimR = crate::BitReader; -impl OnetimR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Onetim { - match self.bits { - false => Onetim::NotBlocked, - true => Onetim::Blocked, - } - } - #[doc = "Generate the timer enable event as normal"] - #[inline(always)] - pub fn is_not_blocked(&self) -> bool { - *self == Onetim::NotBlocked - } - #[doc = "Block the timer enable event unless the timer status flag is clear"] - #[inline(always)] - pub fn is_blocked(&self) -> bool { - *self == Onetim::Blocked - } -} -#[doc = "Field `ONETIM` writer - Timer One Time Operation"] -pub type OnetimW<'a, REG> = crate::BitWriter<'a, REG, Onetim>; -impl<'a, REG> OnetimW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Generate the timer enable event as normal"] - #[inline(always)] - pub fn not_blocked(self) -> &'a mut crate::W { - self.variant(Onetim::NotBlocked) - } - #[doc = "Block the timer enable event unless the timer status flag is clear"] - #[inline(always)] - pub fn blocked(self) -> &'a mut crate::W { - self.variant(Onetim::Blocked) - } -} -#[doc = "Timer Pin Input Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pinins { - #[doc = "0: PINSEL selects timer pin input and output"] - Pinsel = 0, - #[doc = "1: PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL"] - Pinselplus1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pinins) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PININS` reader - Timer Pin Input Select"] -pub type PininsR = crate::BitReader; -impl PininsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pinins { - match self.bits { - false => Pinins::Pinsel, - true => Pinins::Pinselplus1, - } - } - #[doc = "PINSEL selects timer pin input and output"] - #[inline(always)] - pub fn is_pinsel(&self) -> bool { - *self == Pinins::Pinsel - } - #[doc = "PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL"] - #[inline(always)] - pub fn is_pinselplus1(&self) -> bool { - *self == Pinins::Pinselplus1 - } -} -#[doc = "Field `PININS` writer - Timer Pin Input Select"] -pub type PininsW<'a, REG> = crate::BitWriter<'a, REG, Pinins>; -impl<'a, REG> PininsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PINSEL selects timer pin input and output"] - #[inline(always)] - pub fn pinsel(self) -> &'a mut crate::W { - self.variant(Pinins::Pinsel) - } - #[doc = "PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL"] - #[inline(always)] - pub fn pinselplus1(self) -> &'a mut crate::W { - self.variant(Pinins::Pinselplus1) - } -} -#[doc = "Timer Pin Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pinpol { - #[doc = "0: Active high"] - ActiveHigh = 0, - #[doc = "1: Active low"] - ActiveLow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pinpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PINPOL` reader - Timer Pin Polarity"] -pub type PinpolR = crate::BitReader; -impl PinpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pinpol { - match self.bits { - false => Pinpol::ActiveHigh, - true => Pinpol::ActiveLow, - } - } - #[doc = "Active high"] - #[inline(always)] - pub fn is_active_high(&self) -> bool { - *self == Pinpol::ActiveHigh - } - #[doc = "Active low"] - #[inline(always)] - pub fn is_active_low(&self) -> bool { - *self == Pinpol::ActiveLow - } -} -#[doc = "Field `PINPOL` writer - Timer Pin Polarity"] -pub type PinpolW<'a, REG> = crate::BitWriter<'a, REG, Pinpol>; -impl<'a, REG> PinpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active high"] - #[inline(always)] - pub fn active_high(self) -> &'a mut crate::W { - self.variant(Pinpol::ActiveHigh) - } - #[doc = "Active low"] - #[inline(always)] - pub fn active_low(self) -> &'a mut crate::W { - self.variant(Pinpol::ActiveLow) - } -} -#[doc = "Field `PINSEL` reader - Timer Pin Select"] -pub type PinselR = crate::FieldReader; -#[doc = "Field `PINSEL` writer - Timer Pin Select"] -pub type PinselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Timer Pin Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pincfg { - #[doc = "0: Timer pin output disabled"] - Outdisable = 0, - #[doc = "1: Timer pin open-drain or bidirectional output enable"] - OpendBidirouten = 1, - #[doc = "2: Timer pin bidirectional output data"] - BidirOutdata = 2, - #[doc = "3: Timer pin output"] - Output = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pincfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pincfg { - type Ux = u8; -} -impl crate::IsEnum for Pincfg {} -#[doc = "Field `PINCFG` reader - Timer Pin Configuration"] -pub type PincfgR = crate::FieldReader; -impl PincfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pincfg { - match self.bits { - 0 => Pincfg::Outdisable, - 1 => Pincfg::OpendBidirouten, - 2 => Pincfg::BidirOutdata, - 3 => Pincfg::Output, - _ => unreachable!(), - } - } - #[doc = "Timer pin output disabled"] - #[inline(always)] - pub fn is_outdisable(&self) -> bool { - *self == Pincfg::Outdisable - } - #[doc = "Timer pin open-drain or bidirectional output enable"] - #[inline(always)] - pub fn is_opend_bidirouten(&self) -> bool { - *self == Pincfg::OpendBidirouten - } - #[doc = "Timer pin bidirectional output data"] - #[inline(always)] - pub fn is_bidir_outdata(&self) -> bool { - *self == Pincfg::BidirOutdata - } - #[doc = "Timer pin output"] - #[inline(always)] - pub fn is_output(&self) -> bool { - *self == Pincfg::Output - } -} -#[doc = "Field `PINCFG` writer - Timer Pin Configuration"] -pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pincfg, crate::Safe>; -impl<'a, REG> PincfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer pin output disabled"] - #[inline(always)] - pub fn outdisable(self) -> &'a mut crate::W { - self.variant(Pincfg::Outdisable) - } - #[doc = "Timer pin open-drain or bidirectional output enable"] - #[inline(always)] - pub fn opend_bidirouten(self) -> &'a mut crate::W { - self.variant(Pincfg::OpendBidirouten) - } - #[doc = "Timer pin bidirectional output data"] - #[inline(always)] - pub fn bidir_outdata(self) -> &'a mut crate::W { - self.variant(Pincfg::BidirOutdata) - } - #[doc = "Timer pin output"] - #[inline(always)] - pub fn output(self) -> &'a mut crate::W { - self.variant(Pincfg::Output) - } -} -#[doc = "Trigger Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trgsrc { - #[doc = "0: External"] - ExtTrig = 0, - #[doc = "1: Internal"] - InternalTrig = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trgsrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRGSRC` reader - Trigger Source"] -pub type TrgsrcR = crate::BitReader; -impl TrgsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgsrc { - match self.bits { - false => Trgsrc::ExtTrig, - true => Trgsrc::InternalTrig, - } - } - #[doc = "External"] - #[inline(always)] - pub fn is_ext_trig(&self) -> bool { - *self == Trgsrc::ExtTrig - } - #[doc = "Internal"] - #[inline(always)] - pub fn is_internal_trig(&self) -> bool { - *self == Trgsrc::InternalTrig - } -} -#[doc = "Field `TRGSRC` writer - Trigger Source"] -pub type TrgsrcW<'a, REG> = crate::BitWriter<'a, REG, Trgsrc>; -impl<'a, REG> TrgsrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "External"] - #[inline(always)] - pub fn ext_trig(self) -> &'a mut crate::W { - self.variant(Trgsrc::ExtTrig) - } - #[doc = "Internal"] - #[inline(always)] - pub fn internal_trig(self) -> &'a mut crate::W { - self.variant(Trgsrc::InternalTrig) - } -} -#[doc = "Trigger Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trgpol { - #[doc = "0: Active high"] - ActiveHigh = 0, - #[doc = "1: Active low"] - ActiveLow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trgpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRGPOL` reader - Trigger Polarity"] -pub type TrgpolR = crate::BitReader; -impl TrgpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgpol { - match self.bits { - false => Trgpol::ActiveHigh, - true => Trgpol::ActiveLow, - } - } - #[doc = "Active high"] - #[inline(always)] - pub fn is_active_high(&self) -> bool { - *self == Trgpol::ActiveHigh - } - #[doc = "Active low"] - #[inline(always)] - pub fn is_active_low(&self) -> bool { - *self == Trgpol::ActiveLow - } -} -#[doc = "Field `TRGPOL` writer - Trigger Polarity"] -pub type TrgpolW<'a, REG> = crate::BitWriter<'a, REG, Trgpol>; -impl<'a, REG> TrgpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active high"] - #[inline(always)] - pub fn active_high(self) -> &'a mut crate::W { - self.variant(Trgpol::ActiveHigh) - } - #[doc = "Active low"] - #[inline(always)] - pub fn active_low(self) -> &'a mut crate::W { - self.variant(Trgpol::ActiveLow) - } -} -#[doc = "Field `TRGSEL` reader - Trigger Select"] -pub type TrgselR = crate::FieldReader; -#[doc = "Field `TRGSEL` writer - Trigger Select"] -pub type TrgselW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:2 - Timer Mode"] - #[inline(always)] - pub fn timod(&self) -> TimodR { - TimodR::new((self.bits & 7) as u8) - } - #[doc = "Bit 5 - Timer One Time Operation"] - #[inline(always)] - pub fn onetim(&self) -> OnetimR { - OnetimR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Timer Pin Input Select"] - #[inline(always)] - pub fn pinins(&self) -> PininsR { - PininsR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Timer Pin Polarity"] - #[inline(always)] - pub fn pinpol(&self) -> PinpolR { - PinpolR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:12 - Timer Pin Select"] - #[inline(always)] - pub fn pinsel(&self) -> PinselR { - PinselR::new(((self.bits >> 8) & 0x1f) as u8) - } - #[doc = "Bits 16:17 - Timer Pin Configuration"] - #[inline(always)] - pub fn pincfg(&self) -> PincfgR { - PincfgR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bit 22 - Trigger Source"] - #[inline(always)] - pub fn trgsrc(&self) -> TrgsrcR { - TrgsrcR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Trigger Polarity"] - #[inline(always)] - pub fn trgpol(&self) -> TrgpolR { - TrgpolR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:29 - Trigger Select"] - #[inline(always)] - pub fn trgsel(&self) -> TrgselR { - TrgselR::new(((self.bits >> 24) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Timer Mode"] - #[inline(always)] - pub fn timod(&mut self) -> TimodW { - TimodW::new(self, 0) - } - #[doc = "Bit 5 - Timer One Time Operation"] - #[inline(always)] - pub fn onetim(&mut self) -> OnetimW { - OnetimW::new(self, 5) - } - #[doc = "Bit 6 - Timer Pin Input Select"] - #[inline(always)] - pub fn pinins(&mut self) -> PininsW { - PininsW::new(self, 6) - } - #[doc = "Bit 7 - Timer Pin Polarity"] - #[inline(always)] - pub fn pinpol(&mut self) -> PinpolW { - PinpolW::new(self, 7) - } - #[doc = "Bits 8:12 - Timer Pin Select"] - #[inline(always)] - pub fn pinsel(&mut self) -> PinselW { - PinselW::new(self, 8) - } - #[doc = "Bits 16:17 - Timer Pin Configuration"] - #[inline(always)] - pub fn pincfg(&mut self) -> PincfgW { - PincfgW::new(self, 16) - } - #[doc = "Bit 22 - Trigger Source"] - #[inline(always)] - pub fn trgsrc(&mut self) -> TrgsrcW { - TrgsrcW::new(self, 22) - } - #[doc = "Bit 23 - Trigger Polarity"] - #[inline(always)] - pub fn trgpol(&mut self) -> TrgpolW { - TrgpolW::new(self, 23) - } - #[doc = "Bits 24:29 - Trigger Select"] - #[inline(always)] - pub fn trgsel(&mut self) -> TrgselW { - TrgselW::new(self, 24) - } -} -#[doc = "Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`timctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TimctlSpec; -impl crate::RegisterSpec for TimctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timctl::R`](R) reader structure"] -impl crate::Readable for TimctlSpec {} -#[doc = "`write(|w| ..)` method takes [`timctl::W`](W) writer structure"] -impl crate::Writable for TimctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMCTL[%s] to value 0"] -impl crate::Resettable for TimctlSpec {} diff --git a/mcxa276-pac/src/flexio0/timersden.rs b/mcxa276-pac/src/flexio0/timersden.rs deleted file mode 100644 index d0ef77437..000000000 --- a/mcxa276-pac/src/flexio0/timersden.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TIMERSDEN` reader"] -pub type R = crate::R; -#[doc = "Register `TIMERSDEN` writer"] -pub type W = crate::W; -#[doc = "Field `TSDE` reader - Timer Status DMA Enable"] -pub type TsdeR = crate::FieldReader; -#[doc = "Field `TSDE` writer - Timer Status DMA Enable"] -pub type TsdeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Timer Status DMA Enable"] - #[inline(always)] - pub fn tsde(&self) -> TsdeR { - TsdeR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Timer Status DMA Enable"] - #[inline(always)] - pub fn tsde(&mut self) -> TsdeW { - TsdeW::new(self, 0) - } -} -#[doc = "Timer Status DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timersden::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timersden::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TimersdenSpec; -impl crate::RegisterSpec for TimersdenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timersden::R`](R) reader structure"] -impl crate::Readable for TimersdenSpec {} -#[doc = "`write(|w| ..)` method takes [`timersden::W`](W) writer structure"] -impl crate::Writable for TimersdenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMERSDEN to value 0"] -impl crate::Resettable for TimersdenSpec {} diff --git a/mcxa276-pac/src/flexio0/timien.rs b/mcxa276-pac/src/flexio0/timien.rs deleted file mode 100644 index eff390467..000000000 --- a/mcxa276-pac/src/flexio0/timien.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TIMIEN` reader"] -pub type R = crate::R; -#[doc = "Register `TIMIEN` writer"] -pub type W = crate::W; -#[doc = "Field `TEIE` reader - Timer Status Interrupt Enable"] -pub type TeieR = crate::FieldReader; -#[doc = "Field `TEIE` writer - Timer Status Interrupt Enable"] -pub type TeieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Timer Status Interrupt Enable"] - #[inline(always)] - pub fn teie(&self) -> TeieR { - TeieR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Timer Status Interrupt Enable"] - #[inline(always)] - pub fn teie(&mut self) -> TeieW { - TeieW::new(self, 0) - } -} -#[doc = "Timer Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`timien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TimienSpec; -impl crate::RegisterSpec for TimienSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timien::R`](R) reader structure"] -impl crate::Readable for TimienSpec {} -#[doc = "`write(|w| ..)` method takes [`timien::W`](W) writer structure"] -impl crate::Writable for TimienSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMIEN to value 0"] -impl crate::Resettable for TimienSpec {} diff --git a/mcxa276-pac/src/flexio0/timstat.rs b/mcxa276-pac/src/flexio0/timstat.rs deleted file mode 100644 index e8ff9ab62..000000000 --- a/mcxa276-pac/src/flexio0/timstat.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `TIMSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `TIMSTAT` writer"] -pub type W = crate::W; -#[doc = "Timer Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tsf { - #[doc = "0: Clear"] - Clr = 0, - #[doc = "1: Set"] - Set = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tsf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tsf { - type Ux = u8; -} -impl crate::IsEnum for Tsf {} -#[doc = "Field `TSF` reader - Timer Status Flag"] -pub type TsfR = crate::FieldReader; -impl TsfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Tsf::Clr), - 1 => Some(Tsf::Set), - _ => None, - } - } - #[doc = "Clear"] - #[inline(always)] - pub fn is_clr(&self) -> bool { - *self == Tsf::Clr - } - #[doc = "Set"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Tsf::Set - } -} -#[doc = "Field `TSF` writer - Timer Status Flag"] -pub type TsfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Tsf>; -impl<'a, REG> TsfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Clear"] - #[inline(always)] - pub fn clr(self) -> &'a mut crate::W { - self.variant(Tsf::Clr) - } - #[doc = "Set"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Tsf::Set) - } -} -impl R { - #[doc = "Bits 0:3 - Timer Status Flag"] - #[inline(always)] - pub fn tsf(&self) -> TsfR { - TsfR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Timer Status Flag"] - #[inline(always)] - pub fn tsf(&mut self) -> TsfW { - TsfW::new(self, 0) - } -} -#[doc = "Timer Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`timstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TimstatSpec; -impl crate::RegisterSpec for TimstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timstat::R`](R) reader structure"] -impl crate::Readable for TimstatSpec {} -#[doc = "`write(|w| ..)` method takes [`timstat::W`](W) writer structure"] -impl crate::Writable for TimstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; -} -#[doc = "`reset()` method sets TIMSTAT to value 0"] -impl crate::Resettable for TimstatSpec {} diff --git a/mcxa276-pac/src/flexio0/trgstat.rs b/mcxa276-pac/src/flexio0/trgstat.rs deleted file mode 100644 index 77aaa7022..000000000 --- a/mcxa276-pac/src/flexio0/trgstat.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `TRGSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `TRGSTAT` writer"] -pub type W = crate::W; -#[doc = "External Trigger Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Etsf { - #[doc = "0: Clear"] - Clr = 0, - #[doc = "1: Set"] - Set = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Etsf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Etsf { - type Ux = u8; -} -impl crate::IsEnum for Etsf {} -#[doc = "Field `ETSF` reader - External Trigger Status Flag"] -pub type EtsfR = crate::FieldReader; -impl EtsfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Etsf::Clr), - 1 => Some(Etsf::Set), - _ => None, - } - } - #[doc = "Clear"] - #[inline(always)] - pub fn is_clr(&self) -> bool { - *self == Etsf::Clr - } - #[doc = "Set"] - #[inline(always)] - pub fn is_set(&self) -> bool { - *self == Etsf::Set - } -} -#[doc = "Field `ETSF` writer - External Trigger Status Flag"] -pub type EtsfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Etsf>; -impl<'a, REG> EtsfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Clear"] - #[inline(always)] - pub fn clr(self) -> &'a mut crate::W { - self.variant(Etsf::Clr) - } - #[doc = "Set"] - #[inline(always)] - pub fn set_(self) -> &'a mut crate::W { - self.variant(Etsf::Set) - } -} -impl R { - #[doc = "Bits 0:3 - External Trigger Status Flag"] - #[inline(always)] - pub fn etsf(&self) -> EtsfR { - EtsfR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - External Trigger Status Flag"] - #[inline(always)] - pub fn etsf(&mut self) -> EtsfW { - EtsfW::new(self, 0) - } -} -#[doc = "Trigger Status\n\nYou can [`read`](crate::Reg::read) this register and get [`trgstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trgstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TrgstatSpec; -impl crate::RegisterSpec for TrgstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`trgstat::R`](R) reader structure"] -impl crate::Readable for TrgstatSpec {} -#[doc = "`write(|w| ..)` method takes [`trgstat::W`](W) writer structure"] -impl crate::Writable for TrgstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; -} -#[doc = "`reset()` method sets TRGSTAT to value 0"] -impl crate::Resettable for TrgstatSpec {} diff --git a/mcxa276-pac/src/flexio0/trigien.rs b/mcxa276-pac/src/flexio0/trigien.rs deleted file mode 100644 index 473c50d5a..000000000 --- a/mcxa276-pac/src/flexio0/trigien.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TRIGIEN` reader"] -pub type R = crate::R; -#[doc = "Register `TRIGIEN` writer"] -pub type W = crate::W; -#[doc = "Field `TRIE` reader - External Trigger Interrupt Enable"] -pub type TrieR = crate::FieldReader; -#[doc = "Field `TRIE` writer - External Trigger Interrupt Enable"] -pub type TrieW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - External Trigger Interrupt Enable"] - #[inline(always)] - pub fn trie(&self) -> TrieR { - TrieR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - External Trigger Interrupt Enable"] - #[inline(always)] - pub fn trie(&mut self) -> TrieW { - TrieW::new(self, 0) - } -} -#[doc = "External Trigger Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`trigien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TrigienSpec; -impl crate::RegisterSpec for TrigienSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`trigien::R`](R) reader structure"] -impl crate::Readable for TrigienSpec {} -#[doc = "`write(|w| ..)` method takes [`trigien::W`](W) writer structure"] -impl crate::Writable for TrigienSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TRIGIEN to value 0"] -impl crate::Resettable for TrigienSpec {} diff --git a/mcxa276-pac/src/flexio0/verid.rs b/mcxa276-pac/src/flexio0/verid.rs deleted file mode 100644 index 0a1eda3e8..000000000 --- a/mcxa276-pac/src/flexio0/verid.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Standard features implemented"] - Standard = 0, - #[doc = "1: State, logic, and parallel modes supported"] - StateLogicParallel = 1, - #[doc = "2: Pin control registers supported"] - Pinctrl = 2, - #[doc = "3: State, logic, and parallel modes, plus pin control registers supported"] - StateLogicParallelPinctrl = 3, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Standard), - 1 => Some(Feature::StateLogicParallel), - 2 => Some(Feature::Pinctrl), - 3 => Some(Feature::StateLogicParallelPinctrl), - _ => None, - } - } - #[doc = "Standard features implemented"] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == Feature::Standard - } - #[doc = "State, logic, and parallel modes supported"] - #[inline(always)] - pub fn is_state_logic_parallel(&self) -> bool { - *self == Feature::StateLogicParallel - } - #[doc = "Pin control registers supported"] - #[inline(always)] - pub fn is_pinctrl(&self) -> bool { - *self == Feature::Pinctrl - } - #[doc = "State, logic, and parallel modes, plus pin control registers supported"] - #[inline(always)] - pub fn is_state_logic_parallel_pinctrl(&self) -> bool { - *self == Feature::StateLogicParallelPinctrl - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0201_0003"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0201_0003; -} diff --git a/mcxa276-pac/src/flexpwm0.rs b/mcxa276-pac/src/flexpwm0.rs deleted file mode 100644 index dd714afa1..000000000 --- a/mcxa276-pac/src/flexpwm0.rs +++ /dev/null @@ -1,1303 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - sm0cnt: Sm0cnt, - sm0init: Sm0init, - sm0ctrl2: Sm0ctrl2, - sm0ctrl: Sm0ctrl, - _reserved4: [u8; 0x02], - sm0val0: Sm0val0, - _reserved5: [u8; 0x02], - sm0val1: Sm0val1, - _reserved6: [u8; 0x02], - sm0val2: Sm0val2, - _reserved7: [u8; 0x02], - sm0val3: Sm0val3, - _reserved8: [u8; 0x02], - sm0val4: Sm0val4, - _reserved9: [u8; 0x02], - sm0val5: Sm0val5, - _reserved10: [u8; 0x02], - sm0octrl: Sm0octrl, - sm0sts: Sm0sts, - sm0inten: Sm0inten, - sm0dmaen: Sm0dmaen, - sm0tctrl: Sm0tctrl, - sm0dismap0: Sm0dismap0, - _reserved16: [u8; 0x02], - sm0dtcnt0: Sm0dtcnt0, - sm0dtcnt1: Sm0dtcnt1, - _reserved18: [u8; 0x08], - sm0captctrlx: Sm0captctrlx, - sm0captcompx: Sm0captcompx, - sm0cval0: Sm0cval0, - sm0cval0cyc: Sm0cval0cyc, - sm0cval1: Sm0cval1, - sm0cval1cyc: Sm0cval1cyc, - _reserved24: [u8; 0x16], - sm0captfiltx: Sm0captfiltx, - sm1cnt: Sm1cnt, - sm1init: Sm1init, - sm1ctrl2: Sm1ctrl2, - sm1ctrl: Sm1ctrl, - _reserved29: [u8; 0x02], - sm1val0: Sm1val0, - _reserved30: [u8; 0x02], - sm1val1: Sm1val1, - _reserved31: [u8; 0x02], - sm1val2: Sm1val2, - _reserved32: [u8; 0x02], - sm1val3: Sm1val3, - _reserved33: [u8; 0x02], - sm1val4: Sm1val4, - _reserved34: [u8; 0x02], - sm1val5: Sm1val5, - _reserved35: [u8; 0x02], - sm1octrl: Sm1octrl, - sm1sts: Sm1sts, - sm1inten: Sm1inten, - sm1dmaen: Sm1dmaen, - sm1tctrl: Sm1tctrl, - sm1dismap0: Sm1dismap0, - _reserved41: [u8; 0x02], - sm1dtcnt0: Sm1dtcnt0, - sm1dtcnt1: Sm1dtcnt1, - _reserved43: [u8; 0x08], - sm1captctrlx: Sm1captctrlx, - sm1captcompx: Sm1captcompx, - sm1cval0: Sm1cval0, - sm1cval0cyc: Sm1cval0cyc, - sm1cval1: Sm1cval1, - sm1cval1cyc: Sm1cval1cyc, - _reserved49: [u8; 0x10], - sm1phasedly: Sm1phasedly, - _reserved50: [u8; 0x04], - sm1captfiltx: Sm1captfiltx, - sm2cnt: Sm2cnt, - sm2init: Sm2init, - sm2ctrl2: Sm2ctrl2, - sm2ctrl: Sm2ctrl, - _reserved55: [u8; 0x02], - sm2val0: Sm2val0, - _reserved56: [u8; 0x02], - sm2val1: Sm2val1, - _reserved57: [u8; 0x02], - sm2val2: Sm2val2, - _reserved58: [u8; 0x02], - sm2val3: Sm2val3, - _reserved59: [u8; 0x02], - sm2val4: Sm2val4, - _reserved60: [u8; 0x02], - sm2val5: Sm2val5, - _reserved61: [u8; 0x02], - sm2octrl: Sm2octrl, - sm2sts: Sm2sts, - sm2inten: Sm2inten, - sm2dmaen: Sm2dmaen, - sm2tctrl: Sm2tctrl, - sm2dismap0: Sm2dismap0, - _reserved67: [u8; 0x02], - sm2dtcnt0: Sm2dtcnt0, - sm2dtcnt1: Sm2dtcnt1, - _reserved69: [u8; 0x08], - sm2captctrlx: Sm2captctrlx, - sm2captcompx: Sm2captcompx, - sm2cval0: Sm2cval0, - sm2cval0cyc: Sm2cval0cyc, - sm2cval1: Sm2cval1, - sm2cval1cyc: Sm2cval1cyc, - _reserved75: [u8; 0x10], - sm2phasedly: Sm2phasedly, - _reserved76: [u8; 0x04], - sm2captfiltx: Sm2captfiltx, - sm3cnt: Sm3cnt, - sm3init: Sm3init, - sm3ctrl2: Sm3ctrl2, - sm3ctrl: Sm3ctrl, - _reserved81: [u8; 0x02], - sm3val0: Sm3val0, - _reserved82: [u8; 0x02], - sm3val1: Sm3val1, - _reserved83: [u8; 0x02], - sm3val2: Sm3val2, - _reserved84: [u8; 0x02], - sm3val3: Sm3val3, - _reserved85: [u8; 0x02], - sm3val4: Sm3val4, - _reserved86: [u8; 0x02], - sm3val5: Sm3val5, - _reserved87: [u8; 0x02], - sm3octrl: Sm3octrl, - sm3sts: Sm3sts, - sm3inten: Sm3inten, - sm3dmaen: Sm3dmaen, - sm3tctrl: Sm3tctrl, - sm3dismap0: Sm3dismap0, - _reserved93: [u8; 0x02], - sm3dtcnt0: Sm3dtcnt0, - sm3dtcnt1: Sm3dtcnt1, - _reserved95: [u8; 0x08], - sm3captctrlx: Sm3captctrlx, - sm3captcompx: Sm3captcompx, - sm3cval0: Sm3cval0, - sm3cval0cyc: Sm3cval0cyc, - sm3cval1: Sm3cval1, - sm3cval1cyc: Sm3cval1cyc, - _reserved101: [u8; 0x10], - sm3phasedly: Sm3phasedly, - _reserved102: [u8; 0x04], - sm3captfiltx: Sm3captfiltx, - outen: Outen, - mask: Mask, - swcout: Swcout, - dtsrcsel: Dtsrcsel, - mctrl: Mctrl, - mctrl2: Mctrl2, - fctrl0: Fctrl0, - fsts0: Fsts0, - ffilt0: Ffilt0, - ftst0: Ftst0, - fctrl20: Fctrl20, -} -impl RegisterBlock { - #[doc = "0x00 - Counter Register"] - #[inline(always)] - pub const fn sm0cnt(&self) -> &Sm0cnt { - &self.sm0cnt - } - #[doc = "0x02 - Initial Count Register"] - #[inline(always)] - pub const fn sm0init(&self) -> &Sm0init { - &self.sm0init - } - #[doc = "0x04 - Control 2 Register"] - #[inline(always)] - pub const fn sm0ctrl2(&self) -> &Sm0ctrl2 { - &self.sm0ctrl2 - } - #[doc = "0x06 - Control Register"] - #[inline(always)] - pub const fn sm0ctrl(&self) -> &Sm0ctrl { - &self.sm0ctrl - } - #[doc = "0x0a - Value Register 0"] - #[inline(always)] - pub const fn sm0val0(&self) -> &Sm0val0 { - &self.sm0val0 - } - #[doc = "0x0e - Value Register 1"] - #[inline(always)] - pub const fn sm0val1(&self) -> &Sm0val1 { - &self.sm0val1 - } - #[doc = "0x12 - Value Register 2"] - #[inline(always)] - pub const fn sm0val2(&self) -> &Sm0val2 { - &self.sm0val2 - } - #[doc = "0x16 - Value Register 3"] - #[inline(always)] - pub const fn sm0val3(&self) -> &Sm0val3 { - &self.sm0val3 - } - #[doc = "0x1a - Value Register 4"] - #[inline(always)] - pub const fn sm0val4(&self) -> &Sm0val4 { - &self.sm0val4 - } - #[doc = "0x1e - Value Register 5"] - #[inline(always)] - pub const fn sm0val5(&self) -> &Sm0val5 { - &self.sm0val5 - } - #[doc = "0x22 - Output Control Register"] - #[inline(always)] - pub const fn sm0octrl(&self) -> &Sm0octrl { - &self.sm0octrl - } - #[doc = "0x24 - Status Register"] - #[inline(always)] - pub const fn sm0sts(&self) -> &Sm0sts { - &self.sm0sts - } - #[doc = "0x26 - Interrupt Enable Register"] - #[inline(always)] - pub const fn sm0inten(&self) -> &Sm0inten { - &self.sm0inten - } - #[doc = "0x28 - DMA Enable Register"] - #[inline(always)] - pub const fn sm0dmaen(&self) -> &Sm0dmaen { - &self.sm0dmaen - } - #[doc = "0x2a - Output Trigger Control Register"] - #[inline(always)] - pub const fn sm0tctrl(&self) -> &Sm0tctrl { - &self.sm0tctrl - } - #[doc = "0x2c - Fault Disable Mapping Register 0"] - #[inline(always)] - pub const fn sm0dismap0(&self) -> &Sm0dismap0 { - &self.sm0dismap0 - } - #[doc = "0x30 - Deadtime Count Register 0"] - #[inline(always)] - pub const fn sm0dtcnt0(&self) -> &Sm0dtcnt0 { - &self.sm0dtcnt0 - } - #[doc = "0x32 - Deadtime Count Register 1"] - #[inline(always)] - pub const fn sm0dtcnt1(&self) -> &Sm0dtcnt1 { - &self.sm0dtcnt1 - } - #[doc = "0x3c - Capture Control X Register"] - #[inline(always)] - pub const fn sm0captctrlx(&self) -> &Sm0captctrlx { - &self.sm0captctrlx - } - #[doc = "0x3e - Capture Compare X Register"] - #[inline(always)] - pub const fn sm0captcompx(&self) -> &Sm0captcompx { - &self.sm0captcompx - } - #[doc = "0x40 - Capture Value 0 Register"] - #[inline(always)] - pub const fn sm0cval0(&self) -> &Sm0cval0 { - &self.sm0cval0 - } - #[doc = "0x42 - Capture Value 0 Cycle Register"] - #[inline(always)] - pub const fn sm0cval0cyc(&self) -> &Sm0cval0cyc { - &self.sm0cval0cyc - } - #[doc = "0x44 - Capture Value 1 Register"] - #[inline(always)] - pub const fn sm0cval1(&self) -> &Sm0cval1 { - &self.sm0cval1 - } - #[doc = "0x46 - Capture Value 1 Cycle Register"] - #[inline(always)] - pub const fn sm0cval1cyc(&self) -> &Sm0cval1cyc { - &self.sm0cval1cyc - } - #[doc = "0x5e - Capture PWM_X Input Filter Register"] - #[inline(always)] - pub const fn sm0captfiltx(&self) -> &Sm0captfiltx { - &self.sm0captfiltx - } - #[doc = "0x60 - Counter Register"] - #[inline(always)] - pub const fn sm1cnt(&self) -> &Sm1cnt { - &self.sm1cnt - } - #[doc = "0x62 - Initial Count Register"] - #[inline(always)] - pub const fn sm1init(&self) -> &Sm1init { - &self.sm1init - } - #[doc = "0x64 - Control 2 Register"] - #[inline(always)] - pub const fn sm1ctrl2(&self) -> &Sm1ctrl2 { - &self.sm1ctrl2 - } - #[doc = "0x66 - Control Register"] - #[inline(always)] - pub const fn sm1ctrl(&self) -> &Sm1ctrl { - &self.sm1ctrl - } - #[doc = "0x6a - Value Register 0"] - #[inline(always)] - pub const fn sm1val0(&self) -> &Sm1val0 { - &self.sm1val0 - } - #[doc = "0x6e - Value Register 1"] - #[inline(always)] - pub const fn sm1val1(&self) -> &Sm1val1 { - &self.sm1val1 - } - #[doc = "0x72 - Value Register 2"] - #[inline(always)] - pub const fn sm1val2(&self) -> &Sm1val2 { - &self.sm1val2 - } - #[doc = "0x76 - Value Register 3"] - #[inline(always)] - pub const fn sm1val3(&self) -> &Sm1val3 { - &self.sm1val3 - } - #[doc = "0x7a - Value Register 4"] - #[inline(always)] - pub const fn sm1val4(&self) -> &Sm1val4 { - &self.sm1val4 - } - #[doc = "0x7e - Value Register 5"] - #[inline(always)] - pub const fn sm1val5(&self) -> &Sm1val5 { - &self.sm1val5 - } - #[doc = "0x82 - Output Control Register"] - #[inline(always)] - pub const fn sm1octrl(&self) -> &Sm1octrl { - &self.sm1octrl - } - #[doc = "0x84 - Status Register"] - #[inline(always)] - pub const fn sm1sts(&self) -> &Sm1sts { - &self.sm1sts - } - #[doc = "0x86 - Interrupt Enable Register"] - #[inline(always)] - pub const fn sm1inten(&self) -> &Sm1inten { - &self.sm1inten - } - #[doc = "0x88 - DMA Enable Register"] - #[inline(always)] - pub const fn sm1dmaen(&self) -> &Sm1dmaen { - &self.sm1dmaen - } - #[doc = "0x8a - Output Trigger Control Register"] - #[inline(always)] - pub const fn sm1tctrl(&self) -> &Sm1tctrl { - &self.sm1tctrl - } - #[doc = "0x8c - Fault Disable Mapping Register 0"] - #[inline(always)] - pub const fn sm1dismap0(&self) -> &Sm1dismap0 { - &self.sm1dismap0 - } - #[doc = "0x90 - Deadtime Count Register 0"] - #[inline(always)] - pub const fn sm1dtcnt0(&self) -> &Sm1dtcnt0 { - &self.sm1dtcnt0 - } - #[doc = "0x92 - Deadtime Count Register 1"] - #[inline(always)] - pub const fn sm1dtcnt1(&self) -> &Sm1dtcnt1 { - &self.sm1dtcnt1 - } - #[doc = "0x9c - Capture Control X Register"] - #[inline(always)] - pub const fn sm1captctrlx(&self) -> &Sm1captctrlx { - &self.sm1captctrlx - } - #[doc = "0x9e - Capture Compare X Register"] - #[inline(always)] - pub const fn sm1captcompx(&self) -> &Sm1captcompx { - &self.sm1captcompx - } - #[doc = "0xa0 - Capture Value 0 Register"] - #[inline(always)] - pub const fn sm1cval0(&self) -> &Sm1cval0 { - &self.sm1cval0 - } - #[doc = "0xa2 - Capture Value 0 Cycle Register"] - #[inline(always)] - pub const fn sm1cval0cyc(&self) -> &Sm1cval0cyc { - &self.sm1cval0cyc - } - #[doc = "0xa4 - Capture Value 1 Register"] - #[inline(always)] - pub const fn sm1cval1(&self) -> &Sm1cval1 { - &self.sm1cval1 - } - #[doc = "0xa6 - Capture Value 1 Cycle Register"] - #[inline(always)] - pub const fn sm1cval1cyc(&self) -> &Sm1cval1cyc { - &self.sm1cval1cyc - } - #[doc = "0xb8 - Phase Delay Register"] - #[inline(always)] - pub const fn sm1phasedly(&self) -> &Sm1phasedly { - &self.sm1phasedly - } - #[doc = "0xbe - Capture PWM_X Input Filter Register"] - #[inline(always)] - pub const fn sm1captfiltx(&self) -> &Sm1captfiltx { - &self.sm1captfiltx - } - #[doc = "0xc0 - Counter Register"] - #[inline(always)] - pub const fn sm2cnt(&self) -> &Sm2cnt { - &self.sm2cnt - } - #[doc = "0xc2 - Initial Count Register"] - #[inline(always)] - pub const fn sm2init(&self) -> &Sm2init { - &self.sm2init - } - #[doc = "0xc4 - Control 2 Register"] - #[inline(always)] - pub const fn sm2ctrl2(&self) -> &Sm2ctrl2 { - &self.sm2ctrl2 - } - #[doc = "0xc6 - Control Register"] - #[inline(always)] - pub const fn sm2ctrl(&self) -> &Sm2ctrl { - &self.sm2ctrl - } - #[doc = "0xca - Value Register 0"] - #[inline(always)] - pub const fn sm2val0(&self) -> &Sm2val0 { - &self.sm2val0 - } - #[doc = "0xce - Value Register 1"] - #[inline(always)] - pub const fn sm2val1(&self) -> &Sm2val1 { - &self.sm2val1 - } - #[doc = "0xd2 - Value Register 2"] - #[inline(always)] - pub const fn sm2val2(&self) -> &Sm2val2 { - &self.sm2val2 - } - #[doc = "0xd6 - Value Register 3"] - #[inline(always)] - pub const fn sm2val3(&self) -> &Sm2val3 { - &self.sm2val3 - } - #[doc = "0xda - Value Register 4"] - #[inline(always)] - pub const fn sm2val4(&self) -> &Sm2val4 { - &self.sm2val4 - } - #[doc = "0xde - Value Register 5"] - #[inline(always)] - pub const fn sm2val5(&self) -> &Sm2val5 { - &self.sm2val5 - } - #[doc = "0xe2 - Output Control Register"] - #[inline(always)] - pub const fn sm2octrl(&self) -> &Sm2octrl { - &self.sm2octrl - } - #[doc = "0xe4 - Status Register"] - #[inline(always)] - pub const fn sm2sts(&self) -> &Sm2sts { - &self.sm2sts - } - #[doc = "0xe6 - Interrupt Enable Register"] - #[inline(always)] - pub const fn sm2inten(&self) -> &Sm2inten { - &self.sm2inten - } - #[doc = "0xe8 - DMA Enable Register"] - #[inline(always)] - pub const fn sm2dmaen(&self) -> &Sm2dmaen { - &self.sm2dmaen - } - #[doc = "0xea - Output Trigger Control Register"] - #[inline(always)] - pub const fn sm2tctrl(&self) -> &Sm2tctrl { - &self.sm2tctrl - } - #[doc = "0xec - Fault Disable Mapping Register 0"] - #[inline(always)] - pub const fn sm2dismap0(&self) -> &Sm2dismap0 { - &self.sm2dismap0 - } - #[doc = "0xf0 - Deadtime Count Register 0"] - #[inline(always)] - pub const fn sm2dtcnt0(&self) -> &Sm2dtcnt0 { - &self.sm2dtcnt0 - } - #[doc = "0xf2 - Deadtime Count Register 1"] - #[inline(always)] - pub const fn sm2dtcnt1(&self) -> &Sm2dtcnt1 { - &self.sm2dtcnt1 - } - #[doc = "0xfc - Capture Control X Register"] - #[inline(always)] - pub const fn sm2captctrlx(&self) -> &Sm2captctrlx { - &self.sm2captctrlx - } - #[doc = "0xfe - Capture Compare X Register"] - #[inline(always)] - pub const fn sm2captcompx(&self) -> &Sm2captcompx { - &self.sm2captcompx - } - #[doc = "0x100 - Capture Value 0 Register"] - #[inline(always)] - pub const fn sm2cval0(&self) -> &Sm2cval0 { - &self.sm2cval0 - } - #[doc = "0x102 - Capture Value 0 Cycle Register"] - #[inline(always)] - pub const fn sm2cval0cyc(&self) -> &Sm2cval0cyc { - &self.sm2cval0cyc - } - #[doc = "0x104 - Capture Value 1 Register"] - #[inline(always)] - pub const fn sm2cval1(&self) -> &Sm2cval1 { - &self.sm2cval1 - } - #[doc = "0x106 - Capture Value 1 Cycle Register"] - #[inline(always)] - pub const fn sm2cval1cyc(&self) -> &Sm2cval1cyc { - &self.sm2cval1cyc - } - #[doc = "0x118 - Phase Delay Register"] - #[inline(always)] - pub const fn sm2phasedly(&self) -> &Sm2phasedly { - &self.sm2phasedly - } - #[doc = "0x11e - Capture PWM_X Input Filter Register"] - #[inline(always)] - pub const fn sm2captfiltx(&self) -> &Sm2captfiltx { - &self.sm2captfiltx - } - #[doc = "0x120 - Counter Register"] - #[inline(always)] - pub const fn sm3cnt(&self) -> &Sm3cnt { - &self.sm3cnt - } - #[doc = "0x122 - Initial Count Register"] - #[inline(always)] - pub const fn sm3init(&self) -> &Sm3init { - &self.sm3init - } - #[doc = "0x124 - Control 2 Register"] - #[inline(always)] - pub const fn sm3ctrl2(&self) -> &Sm3ctrl2 { - &self.sm3ctrl2 - } - #[doc = "0x126 - Control Register"] - #[inline(always)] - pub const fn sm3ctrl(&self) -> &Sm3ctrl { - &self.sm3ctrl - } - #[doc = "0x12a - Value Register 0"] - #[inline(always)] - pub const fn sm3val0(&self) -> &Sm3val0 { - &self.sm3val0 - } - #[doc = "0x12e - Value Register 1"] - #[inline(always)] - pub const fn sm3val1(&self) -> &Sm3val1 { - &self.sm3val1 - } - #[doc = "0x132 - Value Register 2"] - #[inline(always)] - pub const fn sm3val2(&self) -> &Sm3val2 { - &self.sm3val2 - } - #[doc = "0x136 - Value Register 3"] - #[inline(always)] - pub const fn sm3val3(&self) -> &Sm3val3 { - &self.sm3val3 - } - #[doc = "0x13a - Value Register 4"] - #[inline(always)] - pub const fn sm3val4(&self) -> &Sm3val4 { - &self.sm3val4 - } - #[doc = "0x13e - Value Register 5"] - #[inline(always)] - pub const fn sm3val5(&self) -> &Sm3val5 { - &self.sm3val5 - } - #[doc = "0x142 - Output Control Register"] - #[inline(always)] - pub const fn sm3octrl(&self) -> &Sm3octrl { - &self.sm3octrl - } - #[doc = "0x144 - Status Register"] - #[inline(always)] - pub const fn sm3sts(&self) -> &Sm3sts { - &self.sm3sts - } - #[doc = "0x146 - Interrupt Enable Register"] - #[inline(always)] - pub const fn sm3inten(&self) -> &Sm3inten { - &self.sm3inten - } - #[doc = "0x148 - DMA Enable Register"] - #[inline(always)] - pub const fn sm3dmaen(&self) -> &Sm3dmaen { - &self.sm3dmaen - } - #[doc = "0x14a - Output Trigger Control Register"] - #[inline(always)] - pub const fn sm3tctrl(&self) -> &Sm3tctrl { - &self.sm3tctrl - } - #[doc = "0x14c - Fault Disable Mapping Register 0"] - #[inline(always)] - pub const fn sm3dismap0(&self) -> &Sm3dismap0 { - &self.sm3dismap0 - } - #[doc = "0x150 - Deadtime Count Register 0"] - #[inline(always)] - pub const fn sm3dtcnt0(&self) -> &Sm3dtcnt0 { - &self.sm3dtcnt0 - } - #[doc = "0x152 - Deadtime Count Register 1"] - #[inline(always)] - pub const fn sm3dtcnt1(&self) -> &Sm3dtcnt1 { - &self.sm3dtcnt1 - } - #[doc = "0x15c - Capture Control X Register"] - #[inline(always)] - pub const fn sm3captctrlx(&self) -> &Sm3captctrlx { - &self.sm3captctrlx - } - #[doc = "0x15e - Capture Compare X Register"] - #[inline(always)] - pub const fn sm3captcompx(&self) -> &Sm3captcompx { - &self.sm3captcompx - } - #[doc = "0x160 - Capture Value 0 Register"] - #[inline(always)] - pub const fn sm3cval0(&self) -> &Sm3cval0 { - &self.sm3cval0 - } - #[doc = "0x162 - Capture Value 0 Cycle Register"] - #[inline(always)] - pub const fn sm3cval0cyc(&self) -> &Sm3cval0cyc { - &self.sm3cval0cyc - } - #[doc = "0x164 - Capture Value 1 Register"] - #[inline(always)] - pub const fn sm3cval1(&self) -> &Sm3cval1 { - &self.sm3cval1 - } - #[doc = "0x166 - Capture Value 1 Cycle Register"] - #[inline(always)] - pub const fn sm3cval1cyc(&self) -> &Sm3cval1cyc { - &self.sm3cval1cyc - } - #[doc = "0x178 - Phase Delay Register"] - #[inline(always)] - pub const fn sm3phasedly(&self) -> &Sm3phasedly { - &self.sm3phasedly - } - #[doc = "0x17e - Capture PWM_X Input Filter Register"] - #[inline(always)] - pub const fn sm3captfiltx(&self) -> &Sm3captfiltx { - &self.sm3captfiltx - } - #[doc = "0x180 - Output Enable Register"] - #[inline(always)] - pub const fn outen(&self) -> &Outen { - &self.outen - } - #[doc = "0x182 - Mask Register"] - #[inline(always)] - pub const fn mask(&self) -> &Mask { - &self.mask - } - #[doc = "0x184 - Software Controlled Output Register"] - #[inline(always)] - pub const fn swcout(&self) -> &Swcout { - &self.swcout - } - #[doc = "0x186 - PWM Source Select Register"] - #[inline(always)] - pub const fn dtsrcsel(&self) -> &Dtsrcsel { - &self.dtsrcsel - } - #[doc = "0x188 - Master Control Register"] - #[inline(always)] - pub const fn mctrl(&self) -> &Mctrl { - &self.mctrl - } - #[doc = "0x18a - Master Control 2 Register"] - #[inline(always)] - pub const fn mctrl2(&self) -> &Mctrl2 { - &self.mctrl2 - } - #[doc = "0x18c - Fault Control Register"] - #[inline(always)] - pub const fn fctrl0(&self) -> &Fctrl0 { - &self.fctrl0 - } - #[doc = "0x18e - Fault Status Register"] - #[inline(always)] - pub const fn fsts0(&self) -> &Fsts0 { - &self.fsts0 - } - #[doc = "0x190 - Fault Filter Register"] - #[inline(always)] - pub const fn ffilt0(&self) -> &Ffilt0 { - &self.ffilt0 - } - #[doc = "0x192 - Fault Test Register"] - #[inline(always)] - pub const fn ftst0(&self) -> &Ftst0 { - &self.ftst0 - } - #[doc = "0x194 - Fault Control 2 Register"] - #[inline(always)] - pub const fn fctrl20(&self) -> &Fctrl20 { - &self.fctrl20 - } -} -#[doc = "SM0CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cnt`] module"] -#[doc(alias = "SM0CNT")] -pub type Sm0cnt = crate::Reg; -#[doc = "Counter Register"] -pub mod sm0cnt; -#[doc = "SM0INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0init`] module"] -#[doc(alias = "SM0INIT")] -pub type Sm0init = crate::Reg; -#[doc = "Initial Count Register"] -pub mod sm0init; -#[doc = "SM0CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0ctrl2`] module"] -#[doc(alias = "SM0CTRL2")] -pub type Sm0ctrl2 = crate::Reg; -#[doc = "Control 2 Register"] -pub mod sm0ctrl2; -#[doc = "SM0CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0ctrl`] module"] -#[doc(alias = "SM0CTRL")] -pub type Sm0ctrl = crate::Reg; -#[doc = "Control Register"] -pub mod sm0ctrl; -#[doc = "SM0VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val0`] module"] -#[doc(alias = "SM0VAL0")] -pub type Sm0val0 = crate::Reg; -#[doc = "Value Register 0"] -pub mod sm0val0; -#[doc = "SM0VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val1`] module"] -#[doc(alias = "SM0VAL1")] -pub type Sm0val1 = crate::Reg; -#[doc = "Value Register 1"] -pub mod sm0val1; -#[doc = "SM0VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val2`] module"] -#[doc(alias = "SM0VAL2")] -pub type Sm0val2 = crate::Reg; -#[doc = "Value Register 2"] -pub mod sm0val2; -#[doc = "SM0VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val3`] module"] -#[doc(alias = "SM0VAL3")] -pub type Sm0val3 = crate::Reg; -#[doc = "Value Register 3"] -pub mod sm0val3; -#[doc = "SM0VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val4`] module"] -#[doc(alias = "SM0VAL4")] -pub type Sm0val4 = crate::Reg; -#[doc = "Value Register 4"] -pub mod sm0val4; -#[doc = "SM0VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0val5`] module"] -#[doc(alias = "SM0VAL5")] -pub type Sm0val5 = crate::Reg; -#[doc = "Value Register 5"] -pub mod sm0val5; -#[doc = "SM0OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0octrl`] module"] -#[doc(alias = "SM0OCTRL")] -pub type Sm0octrl = crate::Reg; -#[doc = "Output Control Register"] -pub mod sm0octrl; -#[doc = "SM0STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0sts`] module"] -#[doc(alias = "SM0STS")] -pub type Sm0sts = crate::Reg; -#[doc = "Status Register"] -pub mod sm0sts; -#[doc = "SM0INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0inten`] module"] -#[doc(alias = "SM0INTEN")] -pub type Sm0inten = crate::Reg; -#[doc = "Interrupt Enable Register"] -pub mod sm0inten; -#[doc = "SM0DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dmaen`] module"] -#[doc(alias = "SM0DMAEN")] -pub type Sm0dmaen = crate::Reg; -#[doc = "DMA Enable Register"] -pub mod sm0dmaen; -#[doc = "SM0TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0tctrl`] module"] -#[doc(alias = "SM0TCTRL")] -pub type Sm0tctrl = crate::Reg; -#[doc = "Output Trigger Control Register"] -pub mod sm0tctrl; -#[doc = "SM0DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dismap0`] module"] -#[doc(alias = "SM0DISMAP0")] -pub type Sm0dismap0 = crate::Reg; -#[doc = "Fault Disable Mapping Register 0"] -pub mod sm0dismap0; -#[doc = "SM0DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dtcnt0`] module"] -#[doc(alias = "SM0DTCNT0")] -pub type Sm0dtcnt0 = crate::Reg; -#[doc = "Deadtime Count Register 0"] -pub mod sm0dtcnt0; -#[doc = "SM0DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0dtcnt1`] module"] -#[doc(alias = "SM0DTCNT1")] -pub type Sm0dtcnt1 = crate::Reg; -#[doc = "Deadtime Count Register 1"] -pub mod sm0dtcnt1; -#[doc = "SM0CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0captctrlx`] module"] -#[doc(alias = "SM0CAPTCTRLX")] -pub type Sm0captctrlx = crate::Reg; -#[doc = "Capture Control X Register"] -pub mod sm0captctrlx; -#[doc = "SM0CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0captcompx`] module"] -#[doc(alias = "SM0CAPTCOMPX")] -pub type Sm0captcompx = crate::Reg; -#[doc = "Capture Compare X Register"] -pub mod sm0captcompx; -#[doc = "SM0CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval0`] module"] -#[doc(alias = "SM0CVAL0")] -pub type Sm0cval0 = crate::Reg; -#[doc = "Capture Value 0 Register"] -pub mod sm0cval0; -#[doc = "SM0CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval0cyc`] module"] -#[doc(alias = "SM0CVAL0CYC")] -pub type Sm0cval0cyc = crate::Reg; -#[doc = "Capture Value 0 Cycle Register"] -pub mod sm0cval0cyc; -#[doc = "SM0CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval1`] module"] -#[doc(alias = "SM0CVAL1")] -pub type Sm0cval1 = crate::Reg; -#[doc = "Capture Value 1 Register"] -pub mod sm0cval1; -#[doc = "SM0CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0cval1cyc`] module"] -#[doc(alias = "SM0CVAL1CYC")] -pub type Sm0cval1cyc = crate::Reg; -#[doc = "Capture Value 1 Cycle Register"] -pub mod sm0cval1cyc; -#[doc = "SM0CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm0captfiltx`] module"] -#[doc(alias = "SM0CAPTFILTX")] -pub type Sm0captfiltx = crate::Reg; -#[doc = "Capture PWM_X Input Filter Register"] -pub mod sm0captfiltx; -#[doc = "SM1CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cnt`] module"] -#[doc(alias = "SM1CNT")] -pub type Sm1cnt = crate::Reg; -#[doc = "Counter Register"] -pub mod sm1cnt; -#[doc = "SM1INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1init`] module"] -#[doc(alias = "SM1INIT")] -pub type Sm1init = crate::Reg; -#[doc = "Initial Count Register"] -pub mod sm1init; -#[doc = "SM1CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1ctrl2`] module"] -#[doc(alias = "SM1CTRL2")] -pub type Sm1ctrl2 = crate::Reg; -#[doc = "Control 2 Register"] -pub mod sm1ctrl2; -#[doc = "SM1CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1ctrl`] module"] -#[doc(alias = "SM1CTRL")] -pub type Sm1ctrl = crate::Reg; -#[doc = "Control Register"] -pub mod sm1ctrl; -#[doc = "SM1VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val0`] module"] -#[doc(alias = "SM1VAL0")] -pub type Sm1val0 = crate::Reg; -#[doc = "Value Register 0"] -pub mod sm1val0; -#[doc = "SM1VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val1`] module"] -#[doc(alias = "SM1VAL1")] -pub type Sm1val1 = crate::Reg; -#[doc = "Value Register 1"] -pub mod sm1val1; -#[doc = "SM1VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val2`] module"] -#[doc(alias = "SM1VAL2")] -pub type Sm1val2 = crate::Reg; -#[doc = "Value Register 2"] -pub mod sm1val2; -#[doc = "SM1VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val3`] module"] -#[doc(alias = "SM1VAL3")] -pub type Sm1val3 = crate::Reg; -#[doc = "Value Register 3"] -pub mod sm1val3; -#[doc = "SM1VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val4`] module"] -#[doc(alias = "SM1VAL4")] -pub type Sm1val4 = crate::Reg; -#[doc = "Value Register 4"] -pub mod sm1val4; -#[doc = "SM1VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1val5`] module"] -#[doc(alias = "SM1VAL5")] -pub type Sm1val5 = crate::Reg; -#[doc = "Value Register 5"] -pub mod sm1val5; -#[doc = "SM1OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1octrl`] module"] -#[doc(alias = "SM1OCTRL")] -pub type Sm1octrl = crate::Reg; -#[doc = "Output Control Register"] -pub mod sm1octrl; -#[doc = "SM1STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1sts`] module"] -#[doc(alias = "SM1STS")] -pub type Sm1sts = crate::Reg; -#[doc = "Status Register"] -pub mod sm1sts; -#[doc = "SM1INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1inten`] module"] -#[doc(alias = "SM1INTEN")] -pub type Sm1inten = crate::Reg; -#[doc = "Interrupt Enable Register"] -pub mod sm1inten; -#[doc = "SM1DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dmaen`] module"] -#[doc(alias = "SM1DMAEN")] -pub type Sm1dmaen = crate::Reg; -#[doc = "DMA Enable Register"] -pub mod sm1dmaen; -#[doc = "SM1TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1tctrl`] module"] -#[doc(alias = "SM1TCTRL")] -pub type Sm1tctrl = crate::Reg; -#[doc = "Output Trigger Control Register"] -pub mod sm1tctrl; -#[doc = "SM1DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dismap0`] module"] -#[doc(alias = "SM1DISMAP0")] -pub type Sm1dismap0 = crate::Reg; -#[doc = "Fault Disable Mapping Register 0"] -pub mod sm1dismap0; -#[doc = "SM1DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dtcnt0`] module"] -#[doc(alias = "SM1DTCNT0")] -pub type Sm1dtcnt0 = crate::Reg; -#[doc = "Deadtime Count Register 0"] -pub mod sm1dtcnt0; -#[doc = "SM1DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1dtcnt1`] module"] -#[doc(alias = "SM1DTCNT1")] -pub type Sm1dtcnt1 = crate::Reg; -#[doc = "Deadtime Count Register 1"] -pub mod sm1dtcnt1; -#[doc = "SM1CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1captctrlx`] module"] -#[doc(alias = "SM1CAPTCTRLX")] -pub type Sm1captctrlx = crate::Reg; -#[doc = "Capture Control X Register"] -pub mod sm1captctrlx; -#[doc = "SM1CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1captcompx`] module"] -#[doc(alias = "SM1CAPTCOMPX")] -pub type Sm1captcompx = crate::Reg; -#[doc = "Capture Compare X Register"] -pub mod sm1captcompx; -#[doc = "SM1CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval0`] module"] -#[doc(alias = "SM1CVAL0")] -pub type Sm1cval0 = crate::Reg; -#[doc = "Capture Value 0 Register"] -pub mod sm1cval0; -#[doc = "SM1CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval0cyc`] module"] -#[doc(alias = "SM1CVAL0CYC")] -pub type Sm1cval0cyc = crate::Reg; -#[doc = "Capture Value 0 Cycle Register"] -pub mod sm1cval0cyc; -#[doc = "SM1CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval1`] module"] -#[doc(alias = "SM1CVAL1")] -pub type Sm1cval1 = crate::Reg; -#[doc = "Capture Value 1 Register"] -pub mod sm1cval1; -#[doc = "SM1CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1cval1cyc`] module"] -#[doc(alias = "SM1CVAL1CYC")] -pub type Sm1cval1cyc = crate::Reg; -#[doc = "Capture Value 1 Cycle Register"] -pub mod sm1cval1cyc; -#[doc = "SM1PHASEDLY (rw) register accessor: Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1phasedly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1phasedly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1phasedly`] module"] -#[doc(alias = "SM1PHASEDLY")] -pub type Sm1phasedly = crate::Reg; -#[doc = "Phase Delay Register"] -pub mod sm1phasedly; -#[doc = "SM1CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm1captfiltx`] module"] -#[doc(alias = "SM1CAPTFILTX")] -pub type Sm1captfiltx = crate::Reg; -#[doc = "Capture PWM_X Input Filter Register"] -pub mod sm1captfiltx; -#[doc = "SM2CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cnt`] module"] -#[doc(alias = "SM2CNT")] -pub type Sm2cnt = crate::Reg; -#[doc = "Counter Register"] -pub mod sm2cnt; -#[doc = "SM2INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2init`] module"] -#[doc(alias = "SM2INIT")] -pub type Sm2init = crate::Reg; -#[doc = "Initial Count Register"] -pub mod sm2init; -#[doc = "SM2CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2ctrl2`] module"] -#[doc(alias = "SM2CTRL2")] -pub type Sm2ctrl2 = crate::Reg; -#[doc = "Control 2 Register"] -pub mod sm2ctrl2; -#[doc = "SM2CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2ctrl`] module"] -#[doc(alias = "SM2CTRL")] -pub type Sm2ctrl = crate::Reg; -#[doc = "Control Register"] -pub mod sm2ctrl; -#[doc = "SM2VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val0`] module"] -#[doc(alias = "SM2VAL0")] -pub type Sm2val0 = crate::Reg; -#[doc = "Value Register 0"] -pub mod sm2val0; -#[doc = "SM2VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val1`] module"] -#[doc(alias = "SM2VAL1")] -pub type Sm2val1 = crate::Reg; -#[doc = "Value Register 1"] -pub mod sm2val1; -#[doc = "SM2VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val2`] module"] -#[doc(alias = "SM2VAL2")] -pub type Sm2val2 = crate::Reg; -#[doc = "Value Register 2"] -pub mod sm2val2; -#[doc = "SM2VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val3`] module"] -#[doc(alias = "SM2VAL3")] -pub type Sm2val3 = crate::Reg; -#[doc = "Value Register 3"] -pub mod sm2val3; -#[doc = "SM2VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val4`] module"] -#[doc(alias = "SM2VAL4")] -pub type Sm2val4 = crate::Reg; -#[doc = "Value Register 4"] -pub mod sm2val4; -#[doc = "SM2VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2val5`] module"] -#[doc(alias = "SM2VAL5")] -pub type Sm2val5 = crate::Reg; -#[doc = "Value Register 5"] -pub mod sm2val5; -#[doc = "SM2OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2octrl`] module"] -#[doc(alias = "SM2OCTRL")] -pub type Sm2octrl = crate::Reg; -#[doc = "Output Control Register"] -pub mod sm2octrl; -#[doc = "SM2STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2sts`] module"] -#[doc(alias = "SM2STS")] -pub type Sm2sts = crate::Reg; -#[doc = "Status Register"] -pub mod sm2sts; -#[doc = "SM2INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2inten`] module"] -#[doc(alias = "SM2INTEN")] -pub type Sm2inten = crate::Reg; -#[doc = "Interrupt Enable Register"] -pub mod sm2inten; -#[doc = "SM2DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dmaen`] module"] -#[doc(alias = "SM2DMAEN")] -pub type Sm2dmaen = crate::Reg; -#[doc = "DMA Enable Register"] -pub mod sm2dmaen; -#[doc = "SM2TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2tctrl`] module"] -#[doc(alias = "SM2TCTRL")] -pub type Sm2tctrl = crate::Reg; -#[doc = "Output Trigger Control Register"] -pub mod sm2tctrl; -#[doc = "SM2DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dismap0`] module"] -#[doc(alias = "SM2DISMAP0")] -pub type Sm2dismap0 = crate::Reg; -#[doc = "Fault Disable Mapping Register 0"] -pub mod sm2dismap0; -#[doc = "SM2DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dtcnt0`] module"] -#[doc(alias = "SM2DTCNT0")] -pub type Sm2dtcnt0 = crate::Reg; -#[doc = "Deadtime Count Register 0"] -pub mod sm2dtcnt0; -#[doc = "SM2DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2dtcnt1`] module"] -#[doc(alias = "SM2DTCNT1")] -pub type Sm2dtcnt1 = crate::Reg; -#[doc = "Deadtime Count Register 1"] -pub mod sm2dtcnt1; -#[doc = "SM2CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2captctrlx`] module"] -#[doc(alias = "SM2CAPTCTRLX")] -pub type Sm2captctrlx = crate::Reg; -#[doc = "Capture Control X Register"] -pub mod sm2captctrlx; -#[doc = "SM2CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2captcompx`] module"] -#[doc(alias = "SM2CAPTCOMPX")] -pub type Sm2captcompx = crate::Reg; -#[doc = "Capture Compare X Register"] -pub mod sm2captcompx; -#[doc = "SM2CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval0`] module"] -#[doc(alias = "SM2CVAL0")] -pub type Sm2cval0 = crate::Reg; -#[doc = "Capture Value 0 Register"] -pub mod sm2cval0; -#[doc = "SM2CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval0cyc`] module"] -#[doc(alias = "SM2CVAL0CYC")] -pub type Sm2cval0cyc = crate::Reg; -#[doc = "Capture Value 0 Cycle Register"] -pub mod sm2cval0cyc; -#[doc = "SM2CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval1`] module"] -#[doc(alias = "SM2CVAL1")] -pub type Sm2cval1 = crate::Reg; -#[doc = "Capture Value 1 Register"] -pub mod sm2cval1; -#[doc = "SM2CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2cval1cyc`] module"] -#[doc(alias = "SM2CVAL1CYC")] -pub type Sm2cval1cyc = crate::Reg; -#[doc = "Capture Value 1 Cycle Register"] -pub mod sm2cval1cyc; -#[doc = "SM2PHASEDLY (rw) register accessor: Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2phasedly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2phasedly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2phasedly`] module"] -#[doc(alias = "SM2PHASEDLY")] -pub type Sm2phasedly = crate::Reg; -#[doc = "Phase Delay Register"] -pub mod sm2phasedly; -#[doc = "SM2CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm2captfiltx`] module"] -#[doc(alias = "SM2CAPTFILTX")] -pub type Sm2captfiltx = crate::Reg; -#[doc = "Capture PWM_X Input Filter Register"] -pub mod sm2captfiltx; -#[doc = "SM3CNT (r) register accessor: Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cnt`] module"] -#[doc(alias = "SM3CNT")] -pub type Sm3cnt = crate::Reg; -#[doc = "Counter Register"] -pub mod sm3cnt; -#[doc = "SM3INIT (rw) register accessor: Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3init`] module"] -#[doc(alias = "SM3INIT")] -pub type Sm3init = crate::Reg; -#[doc = "Initial Count Register"] -pub mod sm3init; -#[doc = "SM3CTRL2 (rw) register accessor: Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3ctrl2`] module"] -#[doc(alias = "SM3CTRL2")] -pub type Sm3ctrl2 = crate::Reg; -#[doc = "Control 2 Register"] -pub mod sm3ctrl2; -#[doc = "SM3CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3ctrl`] module"] -#[doc(alias = "SM3CTRL")] -pub type Sm3ctrl = crate::Reg; -#[doc = "Control Register"] -pub mod sm3ctrl; -#[doc = "SM3VAL0 (rw) register accessor: Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val0`] module"] -#[doc(alias = "SM3VAL0")] -pub type Sm3val0 = crate::Reg; -#[doc = "Value Register 0"] -pub mod sm3val0; -#[doc = "SM3VAL1 (rw) register accessor: Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val1`] module"] -#[doc(alias = "SM3VAL1")] -pub type Sm3val1 = crate::Reg; -#[doc = "Value Register 1"] -pub mod sm3val1; -#[doc = "SM3VAL2 (rw) register accessor: Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val2`] module"] -#[doc(alias = "SM3VAL2")] -pub type Sm3val2 = crate::Reg; -#[doc = "Value Register 2"] -pub mod sm3val2; -#[doc = "SM3VAL3 (rw) register accessor: Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val3`] module"] -#[doc(alias = "SM3VAL3")] -pub type Sm3val3 = crate::Reg; -#[doc = "Value Register 3"] -pub mod sm3val3; -#[doc = "SM3VAL4 (rw) register accessor: Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val4`] module"] -#[doc(alias = "SM3VAL4")] -pub type Sm3val4 = crate::Reg; -#[doc = "Value Register 4"] -pub mod sm3val4; -#[doc = "SM3VAL5 (rw) register accessor: Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3val5`] module"] -#[doc(alias = "SM3VAL5")] -pub type Sm3val5 = crate::Reg; -#[doc = "Value Register 5"] -pub mod sm3val5; -#[doc = "SM3OCTRL (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3octrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3octrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3octrl`] module"] -#[doc(alias = "SM3OCTRL")] -pub type Sm3octrl = crate::Reg; -#[doc = "Output Control Register"] -pub mod sm3octrl; -#[doc = "SM3STS (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3sts`] module"] -#[doc(alias = "SM3STS")] -pub type Sm3sts = crate::Reg; -#[doc = "Status Register"] -pub mod sm3sts; -#[doc = "SM3INTEN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3inten`] module"] -#[doc(alias = "SM3INTEN")] -pub type Sm3inten = crate::Reg; -#[doc = "Interrupt Enable Register"] -pub mod sm3inten; -#[doc = "SM3DMAEN (rw) register accessor: DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dmaen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dmaen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dmaen`] module"] -#[doc(alias = "SM3DMAEN")] -pub type Sm3dmaen = crate::Reg; -#[doc = "DMA Enable Register"] -pub mod sm3dmaen; -#[doc = "SM3TCTRL (rw) register accessor: Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3tctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3tctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3tctrl`] module"] -#[doc(alias = "SM3TCTRL")] -pub type Sm3tctrl = crate::Reg; -#[doc = "Output Trigger Control Register"] -pub mod sm3tctrl; -#[doc = "SM3DISMAP0 (rw) register accessor: Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dismap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dismap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dismap0`] module"] -#[doc(alias = "SM3DISMAP0")] -pub type Sm3dismap0 = crate::Reg; -#[doc = "Fault Disable Mapping Register 0"] -pub mod sm3dismap0; -#[doc = "SM3DTCNT0 (rw) register accessor: Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dtcnt0`] module"] -#[doc(alias = "SM3DTCNT0")] -pub type Sm3dtcnt0 = crate::Reg; -#[doc = "Deadtime Count Register 0"] -pub mod sm3dtcnt0; -#[doc = "SM3DTCNT1 (rw) register accessor: Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3dtcnt1`] module"] -#[doc(alias = "SM3DTCNT1")] -pub type Sm3dtcnt1 = crate::Reg; -#[doc = "Deadtime Count Register 1"] -pub mod sm3dtcnt1; -#[doc = "SM3CAPTCTRLX (rw) register accessor: Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captctrlx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captctrlx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3captctrlx`] module"] -#[doc(alias = "SM3CAPTCTRLX")] -pub type Sm3captctrlx = crate::Reg; -#[doc = "Capture Control X Register"] -pub mod sm3captctrlx; -#[doc = "SM3CAPTCOMPX (rw) register accessor: Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captcompx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captcompx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3captcompx`] module"] -#[doc(alias = "SM3CAPTCOMPX")] -pub type Sm3captcompx = crate::Reg; -#[doc = "Capture Compare X Register"] -pub mod sm3captcompx; -#[doc = "SM3CVAL0 (r) register accessor: Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval0`] module"] -#[doc(alias = "SM3CVAL0")] -pub type Sm3cval0 = crate::Reg; -#[doc = "Capture Value 0 Register"] -pub mod sm3cval0; -#[doc = "SM3CVAL0CYC (r) register accessor: Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval0cyc`] module"] -#[doc(alias = "SM3CVAL0CYC")] -pub type Sm3cval0cyc = crate::Reg; -#[doc = "Capture Value 0 Cycle Register"] -pub mod sm3cval0cyc; -#[doc = "SM3CVAL1 (r) register accessor: Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval1`] module"] -#[doc(alias = "SM3CVAL1")] -pub type Sm3cval1 = crate::Reg; -#[doc = "Capture Value 1 Register"] -pub mod sm3cval1; -#[doc = "SM3CVAL1CYC (r) register accessor: Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1cyc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3cval1cyc`] module"] -#[doc(alias = "SM3CVAL1CYC")] -pub type Sm3cval1cyc = crate::Reg; -#[doc = "Capture Value 1 Cycle Register"] -pub mod sm3cval1cyc; -#[doc = "SM3PHASEDLY (rw) register accessor: Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3phasedly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3phasedly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3phasedly`] module"] -#[doc(alias = "SM3PHASEDLY")] -pub type Sm3phasedly = crate::Reg; -#[doc = "Phase Delay Register"] -pub mod sm3phasedly; -#[doc = "SM3CAPTFILTX (rw) register accessor: Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captfiltx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captfiltx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sm3captfiltx`] module"] -#[doc(alias = "SM3CAPTFILTX")] -pub type Sm3captfiltx = crate::Reg; -#[doc = "Capture PWM_X Input Filter Register"] -pub mod sm3captfiltx; -#[doc = "OUTEN (rw) register accessor: Output Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outen`] module"] -#[doc(alias = "OUTEN")] -pub type Outen = crate::Reg; -#[doc = "Output Enable Register"] -pub mod outen; -#[doc = "MASK (rw) register accessor: Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mask`] module"] -#[doc(alias = "MASK")] -pub type Mask = crate::Reg; -#[doc = "Mask Register"] -pub mod mask; -#[doc = "SWCOUT (rw) register accessor: Software Controlled Output Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swcout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swcout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swcout`] module"] -#[doc(alias = "SWCOUT")] -pub type Swcout = crate::Reg; -#[doc = "Software Controlled Output Register"] -pub mod swcout; -#[doc = "DTSRCSEL (rw) register accessor: PWM Source Select Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dtsrcsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtsrcsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtsrcsel`] module"] -#[doc(alias = "DTSRCSEL")] -pub type Dtsrcsel = crate::Reg; -#[doc = "PWM Source Select Register"] -pub mod dtsrcsel; -#[doc = "MCTRL (rw) register accessor: Master Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctrl`] module"] -#[doc(alias = "MCTRL")] -pub type Mctrl = crate::Reg; -#[doc = "Master Control Register"] -pub mod mctrl; -#[doc = "MCTRL2 (rw) register accessor: Master Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctrl2`] module"] -#[doc(alias = "MCTRL2")] -pub type Mctrl2 = crate::Reg; -#[doc = "Master Control 2 Register"] -pub mod mctrl2; -#[doc = "FCTRL0 (rw) register accessor: Fault Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl0`] module"] -#[doc(alias = "FCTRL0")] -pub type Fctrl0 = crate::Reg; -#[doc = "Fault Control Register"] -pub mod fctrl0; -#[doc = "FSTS0 (rw) register accessor: Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fsts0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsts0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsts0`] module"] -#[doc(alias = "FSTS0")] -pub type Fsts0 = crate::Reg; -#[doc = "Fault Status Register"] -pub mod fsts0; -#[doc = "FFILT0 (rw) register accessor: Fault Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ffilt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ffilt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ffilt0`] module"] -#[doc(alias = "FFILT0")] -pub type Ffilt0 = crate::Reg; -#[doc = "Fault Filter Register"] -pub mod ffilt0; -#[doc = "FTST0 (rw) register accessor: Fault Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ftst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ftst0`] module"] -#[doc(alias = "FTST0")] -pub type Ftst0 = crate::Reg; -#[doc = "Fault Test Register"] -pub mod ftst0; -#[doc = "FCTRL20 (rw) register accessor: Fault Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl20`] module"] -#[doc(alias = "FCTRL20")] -pub type Fctrl20 = crate::Reg; -#[doc = "Fault Control 2 Register"] -pub mod fctrl20; diff --git a/mcxa276-pac/src/flexpwm0/dtsrcsel.rs b/mcxa276-pac/src/flexpwm0/dtsrcsel.rs deleted file mode 100644 index 3326af76d..000000000 --- a/mcxa276-pac/src/flexpwm0/dtsrcsel.rs +++ /dev/null @@ -1,737 +0,0 @@ -#[doc = "Register `DTSRCSEL` reader"] -pub type R = crate::R; -#[doc = "Register `DTSRCSEL` writer"] -pub type W = crate::W; -#[doc = "Submodule 0 PWM45 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm0sel45 { - #[doc = "0: Generated SM0PWM45 signal used by the deadtime logic."] - Sm0pwm45 = 0, - #[doc = "1: Inverted generated SM0PWM45 signal used by the deadtime logic."] - InvertedSm0pwm45 = 1, - #[doc = "2: SWCOUT\\[SM0OUT45\\] used by the deadtime logic."] - Sm0out45 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm0sel45) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm0sel45 { - type Ux = u8; -} -impl crate::IsEnum for Sm0sel45 {} -#[doc = "Field `SM0SEL45` reader - Submodule 0 PWM45 Control Select"] -pub type Sm0sel45R = crate::FieldReader; -impl Sm0sel45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Sm0sel45::Sm0pwm45), - 1 => Some(Sm0sel45::InvertedSm0pwm45), - 2 => Some(Sm0sel45::Sm0out45), - _ => None, - } - } - #[doc = "Generated SM0PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm0pwm45(&self) -> bool { - *self == Sm0sel45::Sm0pwm45 - } - #[doc = "Inverted generated SM0PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm0pwm45(&self) -> bool { - *self == Sm0sel45::InvertedSm0pwm45 - } - #[doc = "SWCOUT\\[SM0OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm0out45(&self) -> bool { - *self == Sm0sel45::Sm0out45 - } -} -#[doc = "Field `SM0SEL45` writer - Submodule 0 PWM45 Control Select"] -pub type Sm0sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm0sel45>; -impl<'a, REG> Sm0sel45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM0PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm0pwm45(self) -> &'a mut crate::W { - self.variant(Sm0sel45::Sm0pwm45) - } - #[doc = "Inverted generated SM0PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm0pwm45(self) -> &'a mut crate::W { - self.variant(Sm0sel45::InvertedSm0pwm45) - } - #[doc = "SWCOUT\\[SM0OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm0out45(self) -> &'a mut crate::W { - self.variant(Sm0sel45::Sm0out45) - } -} -#[doc = "Submodule 0 PWM23 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm0sel23 { - #[doc = "0: Generated SM0PWM23 signal used by the deadtime logic."] - Sm0pwm23 = 0, - #[doc = "1: Inverted generated SM0PWM23 signal used by the deadtime logic."] - InvertedSm0pwm23 = 1, - #[doc = "2: SWCOUT\\[SM0OUT23\\] used by the deadtime logic."] - Sm0out23 = 2, - #[doc = "3: PWM0_EXTA signal used by the deadtime logic."] - Pwm0Exta = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm0sel23) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm0sel23 { - type Ux = u8; -} -impl crate::IsEnum for Sm0sel23 {} -#[doc = "Field `SM0SEL23` reader - Submodule 0 PWM23 Control Select"] -pub type Sm0sel23R = crate::FieldReader; -impl Sm0sel23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm0sel23 { - match self.bits { - 0 => Sm0sel23::Sm0pwm23, - 1 => Sm0sel23::InvertedSm0pwm23, - 2 => Sm0sel23::Sm0out23, - 3 => Sm0sel23::Pwm0Exta, - _ => unreachable!(), - } - } - #[doc = "Generated SM0PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm0pwm23(&self) -> bool { - *self == Sm0sel23::Sm0pwm23 - } - #[doc = "Inverted generated SM0PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm0pwm23(&self) -> bool { - *self == Sm0sel23::InvertedSm0pwm23 - } - #[doc = "SWCOUT\\[SM0OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm0out23(&self) -> bool { - *self == Sm0sel23::Sm0out23 - } - #[doc = "PWM0_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn is_pwm0_exta(&self) -> bool { - *self == Sm0sel23::Pwm0Exta - } -} -#[doc = "Field `SM0SEL23` writer - Submodule 0 PWM23 Control Select"] -pub type Sm0sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm0sel23, crate::Safe>; -impl<'a, REG> Sm0sel23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM0PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm0pwm23(self) -> &'a mut crate::W { - self.variant(Sm0sel23::Sm0pwm23) - } - #[doc = "Inverted generated SM0PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm0pwm23(self) -> &'a mut crate::W { - self.variant(Sm0sel23::InvertedSm0pwm23) - } - #[doc = "SWCOUT\\[SM0OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm0out23(self) -> &'a mut crate::W { - self.variant(Sm0sel23::Sm0out23) - } - #[doc = "PWM0_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn pwm0_exta(self) -> &'a mut crate::W { - self.variant(Sm0sel23::Pwm0Exta) - } -} -#[doc = "Submodule 1 PWM45 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm1sel45 { - #[doc = "0: Generated SM1PWM45 signal used by the deadtime logic."] - Sm1pwm45 = 0, - #[doc = "1: Inverted generated SM1PWM45 signal used by the deadtime logic."] - InvertedSm1pwm45 = 1, - #[doc = "2: SWCOUT\\[SM1OUT45\\] used by the deadtime logic."] - Sm1out45 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm1sel45) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm1sel45 { - type Ux = u8; -} -impl crate::IsEnum for Sm1sel45 {} -#[doc = "Field `SM1SEL45` reader - Submodule 1 PWM45 Control Select"] -pub type Sm1sel45R = crate::FieldReader; -impl Sm1sel45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Sm1sel45::Sm1pwm45), - 1 => Some(Sm1sel45::InvertedSm1pwm45), - 2 => Some(Sm1sel45::Sm1out45), - _ => None, - } - } - #[doc = "Generated SM1PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm1pwm45(&self) -> bool { - *self == Sm1sel45::Sm1pwm45 - } - #[doc = "Inverted generated SM1PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm1pwm45(&self) -> bool { - *self == Sm1sel45::InvertedSm1pwm45 - } - #[doc = "SWCOUT\\[SM1OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm1out45(&self) -> bool { - *self == Sm1sel45::Sm1out45 - } -} -#[doc = "Field `SM1SEL45` writer - Submodule 1 PWM45 Control Select"] -pub type Sm1sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm1sel45>; -impl<'a, REG> Sm1sel45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM1PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm1pwm45(self) -> &'a mut crate::W { - self.variant(Sm1sel45::Sm1pwm45) - } - #[doc = "Inverted generated SM1PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm1pwm45(self) -> &'a mut crate::W { - self.variant(Sm1sel45::InvertedSm1pwm45) - } - #[doc = "SWCOUT\\[SM1OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm1out45(self) -> &'a mut crate::W { - self.variant(Sm1sel45::Sm1out45) - } -} -#[doc = "Submodule 1 PWM23 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm1sel23 { - #[doc = "0: Generated SM1PWM23 signal used by the deadtime logic."] - Sm1pwm23 = 0, - #[doc = "1: Inverted generated SM1PWM23 signal used by the deadtime logic."] - InvertedSm1pwm23 = 1, - #[doc = "2: SWCOUT\\[SM1OUT23\\] used by the deadtime logic."] - Sm1out23 = 2, - #[doc = "3: PWM1_EXTA signal used by the deadtime logic."] - Pwm1Exta = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm1sel23) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm1sel23 { - type Ux = u8; -} -impl crate::IsEnum for Sm1sel23 {} -#[doc = "Field `SM1SEL23` reader - Submodule 1 PWM23 Control Select"] -pub type Sm1sel23R = crate::FieldReader; -impl Sm1sel23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm1sel23 { - match self.bits { - 0 => Sm1sel23::Sm1pwm23, - 1 => Sm1sel23::InvertedSm1pwm23, - 2 => Sm1sel23::Sm1out23, - 3 => Sm1sel23::Pwm1Exta, - _ => unreachable!(), - } - } - #[doc = "Generated SM1PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm1pwm23(&self) -> bool { - *self == Sm1sel23::Sm1pwm23 - } - #[doc = "Inverted generated SM1PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm1pwm23(&self) -> bool { - *self == Sm1sel23::InvertedSm1pwm23 - } - #[doc = "SWCOUT\\[SM1OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm1out23(&self) -> bool { - *self == Sm1sel23::Sm1out23 - } - #[doc = "PWM1_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn is_pwm1_exta(&self) -> bool { - *self == Sm1sel23::Pwm1Exta - } -} -#[doc = "Field `SM1SEL23` writer - Submodule 1 PWM23 Control Select"] -pub type Sm1sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm1sel23, crate::Safe>; -impl<'a, REG> Sm1sel23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM1PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm1pwm23(self) -> &'a mut crate::W { - self.variant(Sm1sel23::Sm1pwm23) - } - #[doc = "Inverted generated SM1PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm1pwm23(self) -> &'a mut crate::W { - self.variant(Sm1sel23::InvertedSm1pwm23) - } - #[doc = "SWCOUT\\[SM1OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm1out23(self) -> &'a mut crate::W { - self.variant(Sm1sel23::Sm1out23) - } - #[doc = "PWM1_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn pwm1_exta(self) -> &'a mut crate::W { - self.variant(Sm1sel23::Pwm1Exta) - } -} -#[doc = "Submodule 2 PWM45 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm2sel45 { - #[doc = "0: Generated SM2PWM45 signal used by the deadtime logic."] - Sm2pwm45 = 0, - #[doc = "1: Inverted generated SM2PWM45 signal used by the deadtime logic."] - InvertedSm2pwm45 = 1, - #[doc = "2: SWCOUT\\[SM2OUT45\\] used by the deadtime logic."] - Sm2out45 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm2sel45) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm2sel45 { - type Ux = u8; -} -impl crate::IsEnum for Sm2sel45 {} -#[doc = "Field `SM2SEL45` reader - Submodule 2 PWM45 Control Select"] -pub type Sm2sel45R = crate::FieldReader; -impl Sm2sel45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Sm2sel45::Sm2pwm45), - 1 => Some(Sm2sel45::InvertedSm2pwm45), - 2 => Some(Sm2sel45::Sm2out45), - _ => None, - } - } - #[doc = "Generated SM2PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm2pwm45(&self) -> bool { - *self == Sm2sel45::Sm2pwm45 - } - #[doc = "Inverted generated SM2PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm2pwm45(&self) -> bool { - *self == Sm2sel45::InvertedSm2pwm45 - } - #[doc = "SWCOUT\\[SM2OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm2out45(&self) -> bool { - *self == Sm2sel45::Sm2out45 - } -} -#[doc = "Field `SM2SEL45` writer - Submodule 2 PWM45 Control Select"] -pub type Sm2sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm2sel45>; -impl<'a, REG> Sm2sel45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM2PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm2pwm45(self) -> &'a mut crate::W { - self.variant(Sm2sel45::Sm2pwm45) - } - #[doc = "Inverted generated SM2PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm2pwm45(self) -> &'a mut crate::W { - self.variant(Sm2sel45::InvertedSm2pwm45) - } - #[doc = "SWCOUT\\[SM2OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm2out45(self) -> &'a mut crate::W { - self.variant(Sm2sel45::Sm2out45) - } -} -#[doc = "Submodule 2 PWM23 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm2sel23 { - #[doc = "0: Generated SM2PWM23 signal used by the deadtime logic."] - Sm2pwm23 = 0, - #[doc = "1: Inverted generated SM2PWM23 signal used by the deadtime logic."] - InvertedSm2pwm23 = 1, - #[doc = "2: SWCOUT\\[SM2OUT23\\] used by the deadtime logic."] - Sm2out23 = 2, - #[doc = "3: PWM2_EXTA signal used by the deadtime logic."] - Pwm2Exta = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm2sel23) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm2sel23 { - type Ux = u8; -} -impl crate::IsEnum for Sm2sel23 {} -#[doc = "Field `SM2SEL23` reader - Submodule 2 PWM23 Control Select"] -pub type Sm2sel23R = crate::FieldReader; -impl Sm2sel23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm2sel23 { - match self.bits { - 0 => Sm2sel23::Sm2pwm23, - 1 => Sm2sel23::InvertedSm2pwm23, - 2 => Sm2sel23::Sm2out23, - 3 => Sm2sel23::Pwm2Exta, - _ => unreachable!(), - } - } - #[doc = "Generated SM2PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm2pwm23(&self) -> bool { - *self == Sm2sel23::Sm2pwm23 - } - #[doc = "Inverted generated SM2PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm2pwm23(&self) -> bool { - *self == Sm2sel23::InvertedSm2pwm23 - } - #[doc = "SWCOUT\\[SM2OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm2out23(&self) -> bool { - *self == Sm2sel23::Sm2out23 - } - #[doc = "PWM2_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn is_pwm2_exta(&self) -> bool { - *self == Sm2sel23::Pwm2Exta - } -} -#[doc = "Field `SM2SEL23` writer - Submodule 2 PWM23 Control Select"] -pub type Sm2sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm2sel23, crate::Safe>; -impl<'a, REG> Sm2sel23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM2PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm2pwm23(self) -> &'a mut crate::W { - self.variant(Sm2sel23::Sm2pwm23) - } - #[doc = "Inverted generated SM2PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm2pwm23(self) -> &'a mut crate::W { - self.variant(Sm2sel23::InvertedSm2pwm23) - } - #[doc = "SWCOUT\\[SM2OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm2out23(self) -> &'a mut crate::W { - self.variant(Sm2sel23::Sm2out23) - } - #[doc = "PWM2_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn pwm2_exta(self) -> &'a mut crate::W { - self.variant(Sm2sel23::Pwm2Exta) - } -} -#[doc = "Submodule 3 PWM45 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm3sel45 { - #[doc = "0: Generated SM3PWM45 signal used by the deadtime logic."] - Sm3pwm45 = 0, - #[doc = "1: Inverted generated SM3PWM45 signal used by the deadtime logic."] - InvertedSm3pwm45 = 1, - #[doc = "2: SWCOUT\\[SM3OUT45\\] used by the deadtime logic."] - Sm3out45 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm3sel45) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm3sel45 { - type Ux = u8; -} -impl crate::IsEnum for Sm3sel45 {} -#[doc = "Field `SM3SEL45` reader - Submodule 3 PWM45 Control Select"] -pub type Sm3sel45R = crate::FieldReader; -impl Sm3sel45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Sm3sel45::Sm3pwm45), - 1 => Some(Sm3sel45::InvertedSm3pwm45), - 2 => Some(Sm3sel45::Sm3out45), - _ => None, - } - } - #[doc = "Generated SM3PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm3pwm45(&self) -> bool { - *self == Sm3sel45::Sm3pwm45 - } - #[doc = "Inverted generated SM3PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm3pwm45(&self) -> bool { - *self == Sm3sel45::InvertedSm3pwm45 - } - #[doc = "SWCOUT\\[SM3OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm3out45(&self) -> bool { - *self == Sm3sel45::Sm3out45 - } -} -#[doc = "Field `SM3SEL45` writer - Submodule 3 PWM45 Control Select"] -pub type Sm3sel45W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm3sel45>; -impl<'a, REG> Sm3sel45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM3PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm3pwm45(self) -> &'a mut crate::W { - self.variant(Sm3sel45::Sm3pwm45) - } - #[doc = "Inverted generated SM3PWM45 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm3pwm45(self) -> &'a mut crate::W { - self.variant(Sm3sel45::InvertedSm3pwm45) - } - #[doc = "SWCOUT\\[SM3OUT45\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm3out45(self) -> &'a mut crate::W { - self.variant(Sm3sel45::Sm3out45) - } -} -#[doc = "Submodule 3 PWM23 Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Sm3sel23 { - #[doc = "0: Generated SM3PWM23 signal used by the deadtime logic."] - Sm3pwm23 = 0, - #[doc = "1: Inverted generated SM3PWM23 signal used by the deadtime logic."] - InvertedSm3pwm23 = 1, - #[doc = "2: SWCOUT\\[SM3OUT23\\] used by the deadtime logic."] - Sm3out23 = 2, - #[doc = "3: PWM3_EXTA signal used by the deadtime logic."] - Pwm3Exta = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Sm3sel23) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Sm3sel23 { - type Ux = u8; -} -impl crate::IsEnum for Sm3sel23 {} -#[doc = "Field `SM3SEL23` reader - Submodule 3 PWM23 Control Select"] -pub type Sm3sel23R = crate::FieldReader; -impl Sm3sel23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm3sel23 { - match self.bits { - 0 => Sm3sel23::Sm3pwm23, - 1 => Sm3sel23::InvertedSm3pwm23, - 2 => Sm3sel23::Sm3out23, - 3 => Sm3sel23::Pwm3Exta, - _ => unreachable!(), - } - } - #[doc = "Generated SM3PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_sm3pwm23(&self) -> bool { - *self == Sm3sel23::Sm3pwm23 - } - #[doc = "Inverted generated SM3PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn is_inverted_sm3pwm23(&self) -> bool { - *self == Sm3sel23::InvertedSm3pwm23 - } - #[doc = "SWCOUT\\[SM3OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn is_sm3out23(&self) -> bool { - *self == Sm3sel23::Sm3out23 - } - #[doc = "PWM3_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn is_pwm3_exta(&self) -> bool { - *self == Sm3sel23::Pwm3Exta - } -} -#[doc = "Field `SM3SEL23` writer - Submodule 3 PWM23 Control Select"] -pub type Sm3sel23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Sm3sel23, crate::Safe>; -impl<'a, REG> Sm3sel23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Generated SM3PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn sm3pwm23(self) -> &'a mut crate::W { - self.variant(Sm3sel23::Sm3pwm23) - } - #[doc = "Inverted generated SM3PWM23 signal used by the deadtime logic."] - #[inline(always)] - pub fn inverted_sm3pwm23(self) -> &'a mut crate::W { - self.variant(Sm3sel23::InvertedSm3pwm23) - } - #[doc = "SWCOUT\\[SM3OUT23\\] used by the deadtime logic."] - #[inline(always)] - pub fn sm3out23(self) -> &'a mut crate::W { - self.variant(Sm3sel23::Sm3out23) - } - #[doc = "PWM3_EXTA signal used by the deadtime logic."] - #[inline(always)] - pub fn pwm3_exta(self) -> &'a mut crate::W { - self.variant(Sm3sel23::Pwm3Exta) - } -} -impl R { - #[doc = "Bits 0:1 - Submodule 0 PWM45 Control Select"] - #[inline(always)] - pub fn sm0sel45(&self) -> Sm0sel45R { - Sm0sel45R::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Submodule 0 PWM23 Control Select"] - #[inline(always)] - pub fn sm0sel23(&self) -> Sm0sel23R { - Sm0sel23R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Submodule 1 PWM45 Control Select"] - #[inline(always)] - pub fn sm1sel45(&self) -> Sm1sel45R { - Sm1sel45R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Submodule 1 PWM23 Control Select"] - #[inline(always)] - pub fn sm1sel23(&self) -> Sm1sel23R { - Sm1sel23R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Submodule 2 PWM45 Control Select"] - #[inline(always)] - pub fn sm2sel45(&self) -> Sm2sel45R { - Sm2sel45R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Submodule 2 PWM23 Control Select"] - #[inline(always)] - pub fn sm2sel23(&self) -> Sm2sel23R { - Sm2sel23R::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Submodule 3 PWM45 Control Select"] - #[inline(always)] - pub fn sm3sel45(&self) -> Sm3sel45R { - Sm3sel45R::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Submodule 3 PWM23 Control Select"] - #[inline(always)] - pub fn sm3sel23(&self) -> Sm3sel23R { - Sm3sel23R::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Submodule 0 PWM45 Control Select"] - #[inline(always)] - pub fn sm0sel45(&mut self) -> Sm0sel45W { - Sm0sel45W::new(self, 0) - } - #[doc = "Bits 2:3 - Submodule 0 PWM23 Control Select"] - #[inline(always)] - pub fn sm0sel23(&mut self) -> Sm0sel23W { - Sm0sel23W::new(self, 2) - } - #[doc = "Bits 4:5 - Submodule 1 PWM45 Control Select"] - #[inline(always)] - pub fn sm1sel45(&mut self) -> Sm1sel45W { - Sm1sel45W::new(self, 4) - } - #[doc = "Bits 6:7 - Submodule 1 PWM23 Control Select"] - #[inline(always)] - pub fn sm1sel23(&mut self) -> Sm1sel23W { - Sm1sel23W::new(self, 6) - } - #[doc = "Bits 8:9 - Submodule 2 PWM45 Control Select"] - #[inline(always)] - pub fn sm2sel45(&mut self) -> Sm2sel45W { - Sm2sel45W::new(self, 8) - } - #[doc = "Bits 10:11 - Submodule 2 PWM23 Control Select"] - #[inline(always)] - pub fn sm2sel23(&mut self) -> Sm2sel23W { - Sm2sel23W::new(self, 10) - } - #[doc = "Bits 12:13 - Submodule 3 PWM45 Control Select"] - #[inline(always)] - pub fn sm3sel45(&mut self) -> Sm3sel45W { - Sm3sel45W::new(self, 12) - } - #[doc = "Bits 14:15 - Submodule 3 PWM23 Control Select"] - #[inline(always)] - pub fn sm3sel23(&mut self) -> Sm3sel23W { - Sm3sel23W::new(self, 14) - } -} -#[doc = "PWM Source Select Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dtsrcsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtsrcsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DtsrcselSpec; -impl crate::RegisterSpec for DtsrcselSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`dtsrcsel::R`](R) reader structure"] -impl crate::Readable for DtsrcselSpec {} -#[doc = "`write(|w| ..)` method takes [`dtsrcsel::W`](W) writer structure"] -impl crate::Writable for DtsrcselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DTSRCSEL to value 0"] -impl crate::Resettable for DtsrcselSpec {} diff --git a/mcxa276-pac/src/flexpwm0/fctrl0.rs b/mcxa276-pac/src/flexpwm0/fctrl0.rs deleted file mode 100644 index cdc5147e6..000000000 --- a/mcxa276-pac/src/flexpwm0/fctrl0.rs +++ /dev/null @@ -1,301 +0,0 @@ -#[doc = "Register `FCTRL0` reader"] -pub type R = crate::R; -#[doc = "Register `FCTRL0` writer"] -pub type W = crate::W; -#[doc = "Fault Interrupt Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fie { - #[doc = "0: FAULTx CPU interrupt requests disabled."] - Disabled = 0, - #[doc = "1: FAULTx CPU interrupt requests enabled."] - Enabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fie) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fie { - type Ux = u8; -} -impl crate::IsEnum for Fie {} -#[doc = "Field `FIE` reader - Fault Interrupt Enables"] -pub type FieR = crate::FieldReader; -impl FieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Fie::Disabled), - 1 => Some(Fie::Enabled), - _ => None, - } - } - #[doc = "FAULTx CPU interrupt requests disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fie::Disabled - } - #[doc = "FAULTx CPU interrupt requests enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fie::Enabled - } -} -#[doc = "Field `FIE` writer - Fault Interrupt Enables"] -pub type FieW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fie>; -impl<'a, REG> FieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FAULTx CPU interrupt requests disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fie::Disabled) - } - #[doc = "FAULTx CPU interrupt requests enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fie::Enabled) - } -} -#[doc = "Fault Safety Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fsafe { - #[doc = "0: Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."] - Normal = 0, - #[doc = "1: Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."] - Safe = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fsafe) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fsafe { - type Ux = u8; -} -impl crate::IsEnum for Fsafe {} -#[doc = "Field `FSAFE` reader - Fault Safety Mode"] -pub type FsafeR = crate::FieldReader; -impl FsafeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Fsafe::Normal), - 1 => Some(Fsafe::Safe), - _ => None, - } - } - #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == Fsafe::Normal - } - #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."] - #[inline(always)] - pub fn is_safe(&self) -> bool { - *self == Fsafe::Safe - } -} -#[doc = "Field `FSAFE` writer - Fault Safety Mode"] -pub type FsafeW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fsafe>; -impl<'a, REG> FsafeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(Fsafe::Normal) - } - #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."] - #[inline(always)] - pub fn safe(self) -> &'a mut crate::W { - self.variant(Fsafe::Safe) - } -} -#[doc = "Automatic Fault Clearing\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fauto { - #[doc = "0: Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."] - Manual = 0, - #[doc = "1: Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."] - Automatic = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fauto) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fauto { - type Ux = u8; -} -impl crate::IsEnum for Fauto {} -#[doc = "Field `FAUTO` reader - Automatic Fault Clearing"] -pub type FautoR = crate::FieldReader; -impl FautoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Fauto::Manual), - 1 => Some(Fauto::Automatic), - _ => None, - } - } - #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."] - #[inline(always)] - pub fn is_manual(&self) -> bool { - *self == Fauto::Manual - } - #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."] - #[inline(always)] - pub fn is_automatic(&self) -> bool { - *self == Fauto::Automatic - } -} -#[doc = "Field `FAUTO` writer - Automatic Fault Clearing"] -pub type FautoW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fauto>; -impl<'a, REG> FautoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."] - #[inline(always)] - pub fn manual(self) -> &'a mut crate::W { - self.variant(Fauto::Manual) - } - #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."] - #[inline(always)] - pub fn automatic(self) -> &'a mut crate::W { - self.variant(Fauto::Automatic) - } -} -#[doc = "Fault Level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Flvl { - #[doc = "0: A logic 0 on the fault input indicates a fault condition."] - Logic0 = 0, - #[doc = "1: A logic 1 on the fault input indicates a fault condition."] - Logic1 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Flvl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Flvl { - type Ux = u8; -} -impl crate::IsEnum for Flvl {} -#[doc = "Field `FLVL` reader - Fault Level"] -pub type FlvlR = crate::FieldReader; -impl FlvlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Flvl::Logic0), - 1 => Some(Flvl::Logic1), - _ => None, - } - } - #[doc = "A logic 0 on the fault input indicates a fault condition."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Flvl::Logic0 - } - #[doc = "A logic 1 on the fault input indicates a fault condition."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Flvl::Logic1 - } -} -#[doc = "Field `FLVL` writer - Fault Level"] -pub type FlvlW<'a, REG> = crate::FieldWriter<'a, REG, 4, Flvl>; -impl<'a, REG> FlvlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "A logic 0 on the fault input indicates a fault condition."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Flvl::Logic0) - } - #[doc = "A logic 1 on the fault input indicates a fault condition."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Flvl::Logic1) - } -} -impl R { - #[doc = "Bits 0:3 - Fault Interrupt Enables"] - #[inline(always)] - pub fn fie(&self) -> FieR { - FieR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - Fault Safety Mode"] - #[inline(always)] - pub fn fsafe(&self) -> FsafeR { - FsafeR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - Automatic Fault Clearing"] - #[inline(always)] - pub fn fauto(&self) -> FautoR { - FautoR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Fault Level"] - #[inline(always)] - pub fn flvl(&self) -> FlvlR { - FlvlR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Fault Interrupt Enables"] - #[inline(always)] - pub fn fie(&mut self) -> FieW { - FieW::new(self, 0) - } - #[doc = "Bits 4:7 - Fault Safety Mode"] - #[inline(always)] - pub fn fsafe(&mut self) -> FsafeW { - FsafeW::new(self, 4) - } - #[doc = "Bits 8:11 - Automatic Fault Clearing"] - #[inline(always)] - pub fn fauto(&mut self) -> FautoW { - FautoW::new(self, 8) - } - #[doc = "Bits 12:15 - Fault Level"] - #[inline(always)] - pub fn flvl(&mut self) -> FlvlW { - FlvlW::new(self, 12) - } -} -#[doc = "Fault Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Fctrl0Spec; -impl crate::RegisterSpec for Fctrl0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`fctrl0::R`](R) reader structure"] -impl crate::Readable for Fctrl0Spec {} -#[doc = "`write(|w| ..)` method takes [`fctrl0::W`](W) writer structure"] -impl crate::Writable for Fctrl0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCTRL0 to value 0"] -impl crate::Resettable for Fctrl0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/fctrl20.rs b/mcxa276-pac/src/flexpwm0/fctrl20.rs deleted file mode 100644 index 9042f9d77..000000000 --- a/mcxa276-pac/src/flexpwm0/fctrl20.rs +++ /dev/null @@ -1,91 +0,0 @@ -#[doc = "Register `FCTRL20` reader"] -pub type R = crate::R; -#[doc = "Register `FCTRL20` writer"] -pub type W = crate::W; -#[doc = "No Combinational Path From Fault Input To PWM Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Nocomb { - #[doc = "0: There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."] - Enabled = 0, - #[doc = "1: The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."] - Disabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Nocomb) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Nocomb { - type Ux = u8; -} -impl crate::IsEnum for Nocomb {} -#[doc = "Field `NOCOMB` reader - No Combinational Path From Fault Input To PWM Output"] -pub type NocombR = crate::FieldReader; -impl NocombR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Nocomb::Enabled), - 1 => Some(Nocomb::Disabled), - _ => None, - } - } - #[doc = "There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Nocomb::Enabled - } - #[doc = "The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Nocomb::Disabled - } -} -#[doc = "Field `NOCOMB` writer - No Combinational Path From Fault Input To PWM Output"] -pub type NocombW<'a, REG> = crate::FieldWriter<'a, REG, 4, Nocomb>; -impl<'a, REG> NocombW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Nocomb::Enabled) - } - #[doc = "The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Nocomb::Disabled) - } -} -impl R { - #[doc = "Bits 0:3 - No Combinational Path From Fault Input To PWM Output"] - #[inline(always)] - pub fn nocomb(&self) -> NocombR { - NocombR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - No Combinational Path From Fault Input To PWM Output"] - #[inline(always)] - pub fn nocomb(&mut self) -> NocombW { - NocombW::new(self, 0) - } -} -#[doc = "Fault Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Fctrl20Spec; -impl crate::RegisterSpec for Fctrl20Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`fctrl20::R`](R) reader structure"] -impl crate::Readable for Fctrl20Spec {} -#[doc = "`write(|w| ..)` method takes [`fctrl20::W`](W) writer structure"] -impl crate::Writable for Fctrl20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCTRL20 to value 0"] -impl crate::Resettable for Fctrl20Spec {} diff --git a/mcxa276-pac/src/flexpwm0/ffilt0.rs b/mcxa276-pac/src/flexpwm0/ffilt0.rs deleted file mode 100644 index 787387a5a..000000000 --- a/mcxa276-pac/src/flexpwm0/ffilt0.rs +++ /dev/null @@ -1,112 +0,0 @@ -#[doc = "Register `FFILT0` reader"] -pub type R = crate::R; -#[doc = "Register `FFILT0` writer"] -pub type W = crate::W; -#[doc = "Field `FILT_PER` reader - Fault Filter Period"] -pub type FiltPerR = crate::FieldReader; -#[doc = "Field `FILT_PER` writer - Fault Filter Period"] -pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `FILT_CNT` reader - Fault Filter Count"] -pub type FiltCntR = crate::FieldReader; -#[doc = "Field `FILT_CNT` writer - Fault Filter Count"] -pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Fault Glitch Stretch Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gstr { - #[doc = "0: Fault input glitch stretching is disabled."] - Disabled = 0, - #[doc = "1: Input fault signals are stretched to at least 2 IPBus clock cycles."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gstr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GSTR` reader - Fault Glitch Stretch Enable"] -pub type GstrR = crate::BitReader; -impl GstrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gstr { - match self.bits { - false => Gstr::Disabled, - true => Gstr::Enabled, - } - } - #[doc = "Fault input glitch stretching is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gstr::Disabled - } - #[doc = "Input fault signals are stretched to at least 2 IPBus clock cycles."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gstr::Enabled - } -} -#[doc = "Field `GSTR` writer - Fault Glitch Stretch Enable"] -pub type GstrW<'a, REG> = crate::BitWriter<'a, REG, Gstr>; -impl<'a, REG> GstrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fault input glitch stretching is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gstr::Disabled) - } - #[doc = "Input fault signals are stretched to at least 2 IPBus clock cycles."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gstr::Enabled) - } -} -impl R { - #[doc = "Bits 0:7 - Fault Filter Period"] - #[inline(always)] - pub fn filt_per(&self) -> FiltPerR { - FiltPerR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Fault Filter Count"] - #[inline(always)] - pub fn filt_cnt(&self) -> FiltCntR { - FiltCntR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 15 - Fault Glitch Stretch Enable"] - #[inline(always)] - pub fn gstr(&self) -> GstrR { - GstrR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - Fault Filter Period"] - #[inline(always)] - pub fn filt_per(&mut self) -> FiltPerW { - FiltPerW::new(self, 0) - } - #[doc = "Bits 8:10 - Fault Filter Count"] - #[inline(always)] - pub fn filt_cnt(&mut self) -> FiltCntW { - FiltCntW::new(self, 8) - } - #[doc = "Bit 15 - Fault Glitch Stretch Enable"] - #[inline(always)] - pub fn gstr(&mut self) -> GstrW { - GstrW::new(self, 15) - } -} -#[doc = "Fault Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ffilt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ffilt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ffilt0Spec; -impl crate::RegisterSpec for Ffilt0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`ffilt0::R`](R) reader structure"] -impl crate::Readable for Ffilt0Spec {} -#[doc = "`write(|w| ..)` method takes [`ffilt0::W`](W) writer structure"] -impl crate::Writable for Ffilt0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FFILT0 to value 0"] -impl crate::Resettable for Ffilt0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/fsts0.rs b/mcxa276-pac/src/flexpwm0/fsts0.rs deleted file mode 100644 index 9c16b9485..000000000 --- a/mcxa276-pac/src/flexpwm0/fsts0.rs +++ /dev/null @@ -1,238 +0,0 @@ -#[doc = "Register `FSTS0` reader"] -pub type R = crate::R; -#[doc = "Register `FSTS0` writer"] -pub type W = crate::W; -#[doc = "Fault Flags\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fflag { - #[doc = "0: No fault on the FAULTx pin."] - NoFlag = 0, - #[doc = "1: Fault on the FAULTx pin."] - Flag = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fflag) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fflag { - type Ux = u8; -} -impl crate::IsEnum for Fflag {} -#[doc = "Field `FFLAG` reader - Fault Flags"] -pub type FflagR = crate::FieldReader; -impl FflagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Fflag::NoFlag), - 1 => Some(Fflag::Flag), - _ => None, - } - } - #[doc = "No fault on the FAULTx pin."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Fflag::NoFlag - } - #[doc = "Fault on the FAULTx pin."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Fflag::Flag - } -} -#[doc = "Field `FFLAG` writer - Fault Flags"] -pub type FflagW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fflag>; -impl<'a, REG> FflagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No fault on the FAULTx pin."] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Fflag::NoFlag) - } - #[doc = "Fault on the FAULTx pin."] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Fflag::Flag) - } -} -#[doc = "Full Cycle\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ffull { - #[doc = "0: PWM outputs are not re-enabled at the start of a full cycle"] - PwmOutputsNotReenabled = 0, - #[doc = "1: PWM outputs are re-enabled at the start of a full cycle"] - PwmOutputsReenabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ffull) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ffull { - type Ux = u8; -} -impl crate::IsEnum for Ffull {} -#[doc = "Field `FFULL` reader - Full Cycle"] -pub type FfullR = crate::FieldReader; -impl FfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ffull::PwmOutputsNotReenabled), - 1 => Some(Ffull::PwmOutputsReenabled), - _ => None, - } - } - #[doc = "PWM outputs are not re-enabled at the start of a full cycle"] - #[inline(always)] - pub fn is_pwm_outputs_not_reenabled(&self) -> bool { - *self == Ffull::PwmOutputsNotReenabled - } - #[doc = "PWM outputs are re-enabled at the start of a full cycle"] - #[inline(always)] - pub fn is_pwm_outputs_reenabled(&self) -> bool { - *self == Ffull::PwmOutputsReenabled - } -} -#[doc = "Field `FFULL` writer - Full Cycle"] -pub type FfullW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ffull>; -impl<'a, REG> FfullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM outputs are not re-enabled at the start of a full cycle"] - #[inline(always)] - pub fn pwm_outputs_not_reenabled(self) -> &'a mut crate::W { - self.variant(Ffull::PwmOutputsNotReenabled) - } - #[doc = "PWM outputs are re-enabled at the start of a full cycle"] - #[inline(always)] - pub fn pwm_outputs_reenabled(self) -> &'a mut crate::W { - self.variant(Ffull::PwmOutputsReenabled) - } -} -#[doc = "Field `FFPIN` reader - Filtered Fault Pins"] -pub type FfpinR = crate::FieldReader; -#[doc = "Half Cycle Fault Recovery\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fhalf { - #[doc = "0: PWM outputs are not re-enabled at the start of a half cycle."] - PwmOutputsNotReenabled = 0, - #[doc = "1: PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."] - PwmOutputsReenabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fhalf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fhalf { - type Ux = u8; -} -impl crate::IsEnum for Fhalf {} -#[doc = "Field `FHALF` reader - Half Cycle Fault Recovery"] -pub type FhalfR = crate::FieldReader; -impl FhalfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Fhalf::PwmOutputsNotReenabled), - 1 => Some(Fhalf::PwmOutputsReenabled), - _ => None, - } - } - #[doc = "PWM outputs are not re-enabled at the start of a half cycle."] - #[inline(always)] - pub fn is_pwm_outputs_not_reenabled(&self) -> bool { - *self == Fhalf::PwmOutputsNotReenabled - } - #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."] - #[inline(always)] - pub fn is_pwm_outputs_reenabled(&self) -> bool { - *self == Fhalf::PwmOutputsReenabled - } -} -#[doc = "Field `FHALF` writer - Half Cycle Fault Recovery"] -pub type FhalfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fhalf>; -impl<'a, REG> FhalfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM outputs are not re-enabled at the start of a half cycle."] - #[inline(always)] - pub fn pwm_outputs_not_reenabled(self) -> &'a mut crate::W { - self.variant(Fhalf::PwmOutputsNotReenabled) - } - #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."] - #[inline(always)] - pub fn pwm_outputs_reenabled(self) -> &'a mut crate::W { - self.variant(Fhalf::PwmOutputsReenabled) - } -} -impl R { - #[doc = "Bits 0:3 - Fault Flags"] - #[inline(always)] - pub fn fflag(&self) -> FflagR { - FflagR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - Full Cycle"] - #[inline(always)] - pub fn ffull(&self) -> FfullR { - FfullR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - Filtered Fault Pins"] - #[inline(always)] - pub fn ffpin(&self) -> FfpinR { - FfpinR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Half Cycle Fault Recovery"] - #[inline(always)] - pub fn fhalf(&self) -> FhalfR { - FhalfR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Fault Flags"] - #[inline(always)] - pub fn fflag(&mut self) -> FflagW { - FflagW::new(self, 0) - } - #[doc = "Bits 4:7 - Full Cycle"] - #[inline(always)] - pub fn ffull(&mut self) -> FfullW { - FfullW::new(self, 4) - } - #[doc = "Bits 12:15 - Half Cycle Fault Recovery"] - #[inline(always)] - pub fn fhalf(&mut self) -> FhalfW { - FhalfW::new(self, 12) - } -} -#[doc = "Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fsts0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsts0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Fsts0Spec; -impl crate::RegisterSpec for Fsts0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`fsts0::R`](R) reader structure"] -impl crate::Readable for Fsts0Spec {} -#[doc = "`write(|w| ..)` method takes [`fsts0::W`](W) writer structure"] -impl crate::Writable for Fsts0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FSTS0 to value 0"] -impl crate::Resettable for Fsts0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/ftst0.rs b/mcxa276-pac/src/flexpwm0/ftst0.rs deleted file mode 100644 index 11b12404d..000000000 --- a/mcxa276-pac/src/flexpwm0/ftst0.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `FTST0` reader"] -pub type R = crate::R; -#[doc = "Register `FTST0` writer"] -pub type W = crate::W; -#[doc = "Fault Test\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ftest { - #[doc = "0: No fault"] - NoFault = 0, - #[doc = "1: Cause a simulated fault"] - Fault = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ftest) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FTEST` reader - Fault Test"] -pub type FtestR = crate::BitReader; -impl FtestR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ftest { - match self.bits { - false => Ftest::NoFault, - true => Ftest::Fault, - } - } - #[doc = "No fault"] - #[inline(always)] - pub fn is_no_fault(&self) -> bool { - *self == Ftest::NoFault - } - #[doc = "Cause a simulated fault"] - #[inline(always)] - pub fn is_fault(&self) -> bool { - *self == Ftest::Fault - } -} -#[doc = "Field `FTEST` writer - Fault Test"] -pub type FtestW<'a, REG> = crate::BitWriter<'a, REG, Ftest>; -impl<'a, REG> FtestW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No fault"] - #[inline(always)] - pub fn no_fault(self) -> &'a mut crate::W { - self.variant(Ftest::NoFault) - } - #[doc = "Cause a simulated fault"] - #[inline(always)] - pub fn fault(self) -> &'a mut crate::W { - self.variant(Ftest::Fault) - } -} -impl R { - #[doc = "Bit 0 - Fault Test"] - #[inline(always)] - pub fn ftest(&self) -> FtestR { - FtestR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Fault Test"] - #[inline(always)] - pub fn ftest(&mut self) -> FtestW { - FtestW::new(self, 0) - } -} -#[doc = "Fault Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ftst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ftst0Spec; -impl crate::RegisterSpec for Ftst0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`ftst0::R`](R) reader structure"] -impl crate::Readable for Ftst0Spec {} -#[doc = "`write(|w| ..)` method takes [`ftst0::W`](W) writer structure"] -impl crate::Writable for Ftst0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FTST0 to value 0"] -impl crate::Resettable for Ftst0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/mask.rs b/mcxa276-pac/src/flexpwm0/mask.rs deleted file mode 100644 index 8a8ec7566..000000000 --- a/mcxa276-pac/src/flexpwm0/mask.rs +++ /dev/null @@ -1,70 +0,0 @@ -#[doc = "Register `MASK` reader"] -pub type R = crate::R; -#[doc = "Register `MASK` writer"] -pub type W = crate::W; -#[doc = "Field `MASKX` reader - PWM_X Masks"] -pub type MaskxR = crate::FieldReader; -#[doc = "Field `MASKX` writer - PWM_X Masks"] -pub type MaskxW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `MASKB` reader - PWM_B Masks"] -pub type MaskbR = crate::FieldReader; -#[doc = "Field `MASKB` writer - PWM_B Masks"] -pub type MaskbW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `MASKA` reader - PWM_A Masks"] -pub type MaskaR = crate::FieldReader; -#[doc = "Field `MASKA` writer - PWM_A Masks"] -pub type MaskaW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `UPDATE_MASK` writer - Update Mask Bits Immediately"] -pub type UpdateMaskW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - PWM_X Masks"] - #[inline(always)] - pub fn maskx(&self) -> MaskxR { - MaskxR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - PWM_B Masks"] - #[inline(always)] - pub fn maskb(&self) -> MaskbR { - MaskbR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - PWM_A Masks"] - #[inline(always)] - pub fn maska(&self) -> MaskaR { - MaskaR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - PWM_X Masks"] - #[inline(always)] - pub fn maskx(&mut self) -> MaskxW { - MaskxW::new(self, 0) - } - #[doc = "Bits 4:7 - PWM_B Masks"] - #[inline(always)] - pub fn maskb(&mut self) -> MaskbW { - MaskbW::new(self, 4) - } - #[doc = "Bits 8:11 - PWM_A Masks"] - #[inline(always)] - pub fn maska(&mut self) -> MaskaW { - MaskaW::new(self, 8) - } - #[doc = "Bits 12:15 - Update Mask Bits Immediately"] - #[inline(always)] - pub fn update_mask(&mut self) -> UpdateMaskW { - UpdateMaskW::new(self, 12) - } -} -#[doc = "Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MaskSpec; -impl crate::RegisterSpec for MaskSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`mask::R`](R) reader structure"] -impl crate::Readable for MaskSpec {} -#[doc = "`write(|w| ..)` method takes [`mask::W`](W) writer structure"] -impl crate::Writable for MaskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MASK to value 0"] -impl crate::Resettable for MaskSpec {} diff --git a/mcxa276-pac/src/flexpwm0/mctrl.rs b/mcxa276-pac/src/flexpwm0/mctrl.rs deleted file mode 100644 index 4ab080fde..000000000 --- a/mcxa276-pac/src/flexpwm0/mctrl.rs +++ /dev/null @@ -1,245 +0,0 @@ -#[doc = "Register `MCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `MCTRL` writer"] -pub type W = crate::W; -#[doc = "Load Okay\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ldok { - #[doc = "0: Do not load new values."] - Disabled = 0, - #[doc = "1: Load prescaler, modulus, and PWM values of the corresponding submodule."] - Enabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ldok) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ldok { - type Ux = u8; -} -impl crate::IsEnum for Ldok {} -#[doc = "Field `LDOK` reader - Load Okay"] -pub type LdokR = crate::FieldReader; -impl LdokR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ldok::Disabled), - 1 => Some(Ldok::Enabled), - _ => None, - } - } - #[doc = "Do not load new values."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ldok::Disabled - } - #[doc = "Load prescaler, modulus, and PWM values of the corresponding submodule."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ldok::Enabled - } -} -#[doc = "Field `LDOK` writer - Load Okay"] -pub type LdokW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldok>; -impl<'a, REG> LdokW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Do not load new values."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ldok::Disabled) - } - #[doc = "Load prescaler, modulus, and PWM values of the corresponding submodule."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ldok::Enabled) - } -} -#[doc = "Field `CLDOK` reader - Clear Load Okay"] -pub type CldokR = crate::FieldReader; -#[doc = "Field `CLDOK` writer - Clear Load Okay"] -pub type CldokW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Run\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Run { - #[doc = "0: PWM counter is stopped, but PWM outputs hold the current state."] - Disabled = 0, - #[doc = "1: PWM counter is started in the corresponding submodule."] - Enabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Run) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Run { - type Ux = u8; -} -impl crate::IsEnum for Run {} -#[doc = "Field `RUN` reader - Run"] -pub type RunR = crate::FieldReader; -impl RunR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Run::Disabled), - 1 => Some(Run::Enabled), - _ => None, - } - } - #[doc = "PWM counter is stopped, but PWM outputs hold the current state."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Run::Disabled - } - #[doc = "PWM counter is started in the corresponding submodule."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Run::Enabled - } -} -#[doc = "Field `RUN` writer - Run"] -pub type RunW<'a, REG> = crate::FieldWriter<'a, REG, 4, Run>; -impl<'a, REG> RunW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM counter is stopped, but PWM outputs hold the current state."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Run::Disabled) - } - #[doc = "PWM counter is started in the corresponding submodule."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Run::Enabled) - } -} -#[doc = "Current Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ipol { - #[doc = "0: PWM23 is used to generate complementary PWM pair in the corresponding submodule."] - Pwm23 = 0, - #[doc = "1: PWM45 is used to generate complementary PWM pair in the corresponding submodule."] - Pwm45 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ipol) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ipol { - type Ux = u8; -} -impl crate::IsEnum for Ipol {} -#[doc = "Field `IPOL` reader - Current Polarity"] -pub type IpolR = crate::FieldReader; -impl IpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ipol::Pwm23), - 1 => Some(Ipol::Pwm45), - _ => None, - } - } - #[doc = "PWM23 is used to generate complementary PWM pair in the corresponding submodule."] - #[inline(always)] - pub fn is_pwm23(&self) -> bool { - *self == Ipol::Pwm23 - } - #[doc = "PWM45 is used to generate complementary PWM pair in the corresponding submodule."] - #[inline(always)] - pub fn is_pwm45(&self) -> bool { - *self == Ipol::Pwm45 - } -} -#[doc = "Field `IPOL` writer - Current Polarity"] -pub type IpolW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ipol>; -impl<'a, REG> IpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM23 is used to generate complementary PWM pair in the corresponding submodule."] - #[inline(always)] - pub fn pwm23(self) -> &'a mut crate::W { - self.variant(Ipol::Pwm23) - } - #[doc = "PWM45 is used to generate complementary PWM pair in the corresponding submodule."] - #[inline(always)] - pub fn pwm45(self) -> &'a mut crate::W { - self.variant(Ipol::Pwm45) - } -} -impl R { - #[doc = "Bits 0:3 - Load Okay"] - #[inline(always)] - pub fn ldok(&self) -> LdokR { - LdokR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - Clear Load Okay"] - #[inline(always)] - pub fn cldok(&self) -> CldokR { - CldokR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - Run"] - #[inline(always)] - pub fn run(&self) -> RunR { - RunR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Current Polarity"] - #[inline(always)] - pub fn ipol(&self) -> IpolR { - IpolR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Load Okay"] - #[inline(always)] - pub fn ldok(&mut self) -> LdokW { - LdokW::new(self, 0) - } - #[doc = "Bits 4:7 - Clear Load Okay"] - #[inline(always)] - pub fn cldok(&mut self) -> CldokW { - CldokW::new(self, 4) - } - #[doc = "Bits 8:11 - Run"] - #[inline(always)] - pub fn run(&mut self) -> RunW { - RunW::new(self, 8) - } - #[doc = "Bits 12:15 - Current Polarity"] - #[inline(always)] - pub fn ipol(&mut self) -> IpolW { - IpolW::new(self, 12) - } -} -#[doc = "Master Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MctrlSpec; -impl crate::RegisterSpec for MctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`mctrl::R`](R) reader structure"] -impl crate::Readable for MctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`mctrl::W`](W) writer structure"] -impl crate::Writable for MctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCTRL to value 0"] -impl crate::Resettable for MctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/mctrl2.rs b/mcxa276-pac/src/flexpwm0/mctrl2.rs deleted file mode 100644 index f8a69d710..000000000 --- a/mcxa276-pac/src/flexpwm0/mctrl2.rs +++ /dev/null @@ -1,213 +0,0 @@ -#[doc = "Register `MCTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `MCTRL2` writer"] -pub type W = crate::W; -#[doc = "Write protect\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wrprot { - #[doc = "0: Write protection off (default)."] - Disabled = 0, - #[doc = "1: Write protection on."] - Enabled = 1, - #[doc = "2: Write protection off and locked until chip reset."] - DisabledLocked = 2, - #[doc = "3: Write protection on and locked until chip reset."] - EnabledLocked = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wrprot) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wrprot { - type Ux = u8; -} -impl crate::IsEnum for Wrprot {} -#[doc = "Field `WRPROT` reader - Write protect"] -pub type WrprotR = crate::FieldReader; -impl WrprotR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wrprot { - match self.bits { - 0 => Wrprot::Disabled, - 1 => Wrprot::Enabled, - 2 => Wrprot::DisabledLocked, - 3 => Wrprot::EnabledLocked, - _ => unreachable!(), - } - } - #[doc = "Write protection off (default)."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wrprot::Disabled - } - #[doc = "Write protection on."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wrprot::Enabled - } - #[doc = "Write protection off and locked until chip reset."] - #[inline(always)] - pub fn is_disabled_locked(&self) -> bool { - *self == Wrprot::DisabledLocked - } - #[doc = "Write protection on and locked until chip reset."] - #[inline(always)] - pub fn is_enabled_locked(&self) -> bool { - *self == Wrprot::EnabledLocked - } -} -#[doc = "Field `WRPROT` writer - Write protect"] -pub type WrprotW<'a, REG> = crate::FieldWriter<'a, REG, 2, Wrprot, crate::Safe>; -impl<'a, REG> WrprotW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Write protection off (default)."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Wrprot::Disabled) - } - #[doc = "Write protection on."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Wrprot::Enabled) - } - #[doc = "Write protection off and locked until chip reset."] - #[inline(always)] - pub fn disabled_locked(self) -> &'a mut crate::W { - self.variant(Wrprot::DisabledLocked) - } - #[doc = "Write protection on and locked until chip reset."] - #[inline(always)] - pub fn enabled_locked(self) -> &'a mut crate::W { - self.variant(Wrprot::EnabledLocked) - } -} -#[doc = "Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum StretchCntPrsc { - #[doc = "0: Stretch count is zero, no stretch."] - Disabled = 0, - #[doc = "1: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period."] - Enabled = 1, - #[doc = "2: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period."] - DisabledLocked = 2, - #[doc = "3: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period."] - EnabledLocked = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: StretchCntPrsc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for StretchCntPrsc { - type Ux = u8; -} -impl crate::IsEnum for StretchCntPrsc {} -#[doc = "Field `STRETCH_CNT_PRSC` reader - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] -pub type StretchCntPrscR = crate::FieldReader; -impl StretchCntPrscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StretchCntPrsc { - match self.bits { - 0 => StretchCntPrsc::Disabled, - 1 => StretchCntPrsc::Enabled, - 2 => StretchCntPrsc::DisabledLocked, - 3 => StretchCntPrsc::EnabledLocked, - _ => unreachable!(), - } - } - #[doc = "Stretch count is zero, no stretch."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == StretchCntPrsc::Disabled - } - #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == StretchCntPrsc::Enabled - } - #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period."] - #[inline(always)] - pub fn is_disabled_locked(&self) -> bool { - *self == StretchCntPrsc::DisabledLocked - } - #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period."] - #[inline(always)] - pub fn is_enabled_locked(&self) -> bool { - *self == StretchCntPrsc::EnabledLocked - } -} -#[doc = "Field `STRETCH_CNT_PRSC` writer - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] -pub type StretchCntPrscW<'a, REG> = crate::FieldWriter<'a, REG, 2, StretchCntPrsc, crate::Safe>; -impl<'a, REG> StretchCntPrscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Stretch count is zero, no stretch."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(StretchCntPrsc::Disabled) - } - #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(StretchCntPrsc::Enabled) - } - #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period."] - #[inline(always)] - pub fn disabled_locked(self) -> &'a mut crate::W { - self.variant(StretchCntPrsc::DisabledLocked) - } - #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period."] - #[inline(always)] - pub fn enabled_locked(self) -> &'a mut crate::W { - self.variant(StretchCntPrsc::EnabledLocked) - } -} -impl R { - #[doc = "Bits 2:3 - Write protect"] - #[inline(always)] - pub fn wrprot(&self) -> WrprotR { - WrprotR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 6:7 - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] - #[inline(always)] - pub fn stretch_cnt_prsc(&self) -> StretchCntPrscR { - StretchCntPrscR::new(((self.bits >> 6) & 3) as u8) - } -} -impl W { - #[doc = "Bits 2:3 - Write protect"] - #[inline(always)] - pub fn wrprot(&mut self) -> WrprotW { - WrprotW::new(self, 2) - } - #[doc = "Bits 6:7 - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig"] - #[inline(always)] - pub fn stretch_cnt_prsc(&mut self) -> StretchCntPrscW { - StretchCntPrscW::new(self, 6) - } -} -#[doc = "Master Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mctrl2Spec; -impl crate::RegisterSpec for Mctrl2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`mctrl2::R`](R) reader structure"] -impl crate::Readable for Mctrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`mctrl2::W`](W) writer structure"] -impl crate::Writable for Mctrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCTRL2 to value 0"] -impl crate::Resettable for Mctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/outen.rs b/mcxa276-pac/src/flexpwm0/outen.rs deleted file mode 100644 index a69227e19..000000000 --- a/mcxa276-pac/src/flexpwm0/outen.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `OUTEN` reader"] -pub type R = crate::R; -#[doc = "Register `OUTEN` writer"] -pub type W = crate::W; -#[doc = "Field `PWMX_EN` reader - PWM_X Output Enables"] -pub type PwmxEnR = crate::FieldReader; -#[doc = "Field `PWMX_EN` writer - PWM_X Output Enables"] -pub type PwmxEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `PWMB_EN` reader - PWM_B Output Enables"] -pub type PwmbEnR = crate::FieldReader; -#[doc = "Field `PWMB_EN` writer - PWM_B Output Enables"] -pub type PwmbEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `PWMA_EN` reader - PWM_A Output Enables"] -pub type PwmaEnR = crate::FieldReader; -#[doc = "Field `PWMA_EN` writer - PWM_A Output Enables"] -pub type PwmaEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - PWM_X Output Enables"] - #[inline(always)] - pub fn pwmx_en(&self) -> PwmxEnR { - PwmxEnR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - PWM_B Output Enables"] - #[inline(always)] - pub fn pwmb_en(&self) -> PwmbEnR { - PwmbEnR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - PWM_A Output Enables"] - #[inline(always)] - pub fn pwma_en(&self) -> PwmaEnR { - PwmaEnR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - PWM_X Output Enables"] - #[inline(always)] - pub fn pwmx_en(&mut self) -> PwmxEnW { - PwmxEnW::new(self, 0) - } - #[doc = "Bits 4:7 - PWM_B Output Enables"] - #[inline(always)] - pub fn pwmb_en(&mut self) -> PwmbEnW { - PwmbEnW::new(self, 4) - } - #[doc = "Bits 8:11 - PWM_A Output Enables"] - #[inline(always)] - pub fn pwma_en(&mut self) -> PwmaEnW { - PwmaEnW::new(self, 8) - } -} -#[doc = "Output Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OutenSpec; -impl crate::RegisterSpec for OutenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`outen::R`](R) reader structure"] -impl crate::Readable for OutenSpec {} -#[doc = "`write(|w| ..)` method takes [`outen::W`](W) writer structure"] -impl crate::Writable for OutenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets OUTEN to value 0"] -impl crate::Resettable for OutenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0captcompx.rs b/mcxa276-pac/src/flexpwm0/sm0captcompx.rs deleted file mode 100644 index 90a7ac13d..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0captcompx.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `SM0CAPTCOMPX` reader"] -pub type R = crate::R; -#[doc = "Register `SM0CAPTCOMPX` writer"] -pub type W = crate::W; -#[doc = "Field `EDGCMPX` reader - Edge Compare X"] -pub type EdgcmpxR = crate::FieldReader; -#[doc = "Field `EDGCMPX` writer - Edge Compare X"] -pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EDGCNTX` reader - Edge Counter X"] -pub type EdgcntxR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&self) -> EdgcmpxR { - EdgcmpxR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Edge Counter X"] - #[inline(always)] - pub fn edgcntx(&self) -> EdgcntxR { - EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&mut self) -> EdgcmpxW { - EdgcmpxW::new(self, 0) - } -} -#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0captcompxSpec; -impl crate::RegisterSpec for Sm0captcompxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0captcompx::R`](R) reader structure"] -impl crate::Readable for Sm0captcompxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0captcompx::W`](W) writer structure"] -impl crate::Writable for Sm0captcompxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0CAPTCOMPX to value 0"] -impl crate::Resettable for Sm0captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm0captctrlx.rs deleted file mode 100644 index fa6ebc270..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0captctrlx.rs +++ /dev/null @@ -1,493 +0,0 @@ -#[doc = "Register `SM0CAPTCTRLX` reader"] -pub type R = crate::R; -#[doc = "Register `SM0CAPTCTRLX` writer"] -pub type W = crate::W; -#[doc = "Arm X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Armx { - #[doc = "0: Input capture operation is disabled."] - Disabled = 0, - #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Armx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ARMX` reader - Arm X"] -pub type ArmxR = crate::BitReader; -impl ArmxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Armx { - match self.bits { - false => Armx::Disabled, - true => Armx::Enabled, - } - } - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Armx::Disabled - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Armx::Enabled - } -} -#[doc = "Field `ARMX` writer - Arm X"] -pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; -impl<'a, REG> ArmxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Armx::Disabled) - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Armx::Enabled) - } -} -#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Oneshotx { - #[doc = "0: Free Running"] - FreeRunning = 0, - #[doc = "1: One Shot"] - OneShot = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Oneshotx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] -pub type OneshotxR = crate::BitReader; -impl OneshotxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Oneshotx { - match self.bits { - false => Oneshotx::FreeRunning, - true => Oneshotx::OneShot, - } - } - #[doc = "Free Running"] - #[inline(always)] - pub fn is_free_running(&self) -> bool { - *self == Oneshotx::FreeRunning - } - #[doc = "One Shot"] - #[inline(always)] - pub fn is_one_shot(&self) -> bool { - *self == Oneshotx::OneShot - } -} -#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] -pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; -impl<'a, REG> OneshotxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Free Running"] - #[inline(always)] - pub fn free_running(self) -> &'a mut crate::W { - self.variant(Oneshotx::FreeRunning) - } - #[doc = "One Shot"] - #[inline(always)] - pub fn one_shot(self) -> &'a mut crate::W { - self.variant(Oneshotx::OneShot) - } -} -#[doc = "Edge X 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx0 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx0 { - type Ux = u8; -} -impl crate::IsEnum for Edgx0 {} -#[doc = "Field `EDGX0` reader - Edge X 0"] -pub type Edgx0R = crate::FieldReader; -impl Edgx0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx0 { - match self.bits { - 0 => Edgx0::Disabled, - 1 => Edgx0::FallingEdge, - 2 => Edgx0::RisingEdge, - 3 => Edgx0::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx0::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx0::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx0::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx0::AnyEdge - } -} -#[doc = "Field `EDGX0` writer - Edge X 0"] -pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; -impl<'a, REG> Edgx0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx0::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::AnyEdge) - } -} -#[doc = "Edge X 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx1 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx1 { - type Ux = u8; -} -impl crate::IsEnum for Edgx1 {} -#[doc = "Field `EDGX1` reader - Edge X 1"] -pub type Edgx1R = crate::FieldReader; -impl Edgx1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx1 { - match self.bits { - 0 => Edgx1::Disabled, - 1 => Edgx1::FallingEdge, - 2 => Edgx1::RisingEdge, - 3 => Edgx1::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx1::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx1::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx1::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx1::AnyEdge - } -} -#[doc = "Field `EDGX1` writer - Edge X 1"] -pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; -impl<'a, REG> Edgx1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx1::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::AnyEdge) - } -} -#[doc = "Input Select X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum InpSelx { - #[doc = "0: Raw PWM_X input signal selected as source."] - PwmX = 0, - #[doc = "1: Edge Counter"] - EdgeCounter = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: InpSelx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INP_SELX` reader - Input Select X"] -pub type InpSelxR = crate::BitReader; -impl InpSelxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InpSelx { - match self.bits { - false => InpSelx::PwmX, - true => InpSelx::EdgeCounter, - } - } - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InpSelx::PwmX - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn is_edge_counter(&self) -> bool { - *self == InpSelx::EdgeCounter - } -} -#[doc = "Field `INP_SELX` writer - Input Select X"] -pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; -impl<'a, REG> InpSelxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InpSelx::PwmX) - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn edge_counter(self) -> &'a mut crate::W { - self.variant(InpSelx::EdgeCounter) - } -} -#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EdgcntxEn { - #[doc = "0: Edge counter disabled and held in reset"] - Disabled = 0, - #[doc = "1: Edge counter enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EdgcntxEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] -pub type EdgcntxEnR = crate::BitReader; -impl EdgcntxEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EdgcntxEn { - match self.bits { - false => EdgcntxEn::Disabled, - true => EdgcntxEn::Enabled, - } - } - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == EdgcntxEn::Disabled - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == EdgcntxEn::Enabled - } -} -#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] -pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; -impl<'a, REG> EdgcntxEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Disabled) - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Enabled) - } -} -#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] -pub type CfxwmR = crate::FieldReader; -#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] -pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] -pub type Cx0cntR = crate::FieldReader; -#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] -pub type Cx1cntR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&self) -> ArmxR { - ArmxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&self) -> OneshotxR { - OneshotxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&self) -> Edgx0R { - Edgx0R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&self) -> Edgx1R { - Edgx1R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&self) -> InpSelxR { - InpSelxR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&self) -> EdgcntxEnR { - EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&self) -> CfxwmR { - CfxwmR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] - #[inline(always)] - pub fn cx0cnt(&self) -> Cx0cntR { - Cx0cntR::new(((self.bits >> 10) & 7) as u8) - } - #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] - #[inline(always)] - pub fn cx1cnt(&self) -> Cx1cntR { - Cx1cntR::new(((self.bits >> 13) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&mut self) -> ArmxW { - ArmxW::new(self, 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&mut self) -> OneshotxW { - OneshotxW::new(self, 1) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&mut self) -> Edgx0W { - Edgx0W::new(self, 2) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&mut self) -> Edgx1W { - Edgx1W::new(self, 4) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&mut self) -> InpSelxW { - InpSelxW::new(self, 6) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&mut self) -> EdgcntxEnW { - EdgcntxEnW::new(self, 7) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&mut self) -> CfxwmW { - CfxwmW::new(self, 8) - } -} -#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0captctrlxSpec; -impl crate::RegisterSpec for Sm0captctrlxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0captctrlx::R`](R) reader structure"] -impl crate::Readable for Sm0captctrlxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0captctrlx::W`](W) writer structure"] -impl crate::Writable for Sm0captctrlxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0CAPTCTRLX to value 0"] -impl crate::Resettable for Sm0captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm0captfiltx.rs deleted file mode 100644 index 4457d33d6..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0captfiltx.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `SM0CAPTFILTX` reader"] -pub type R = crate::R; -#[doc = "Register `SM0CAPTFILTX` writer"] -pub type W = crate::W; -#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] -pub type CaptxFiltPerR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] -pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] -pub type CaptxFiltCntR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] -pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&self) -> CaptxFiltPerR { - CaptxFiltPerR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { - CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { - CaptxFiltPerW::new(self, 0) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { - CaptxFiltCntW::new(self, 8) - } -} -#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0captfiltxSpec; -impl crate::RegisterSpec for Sm0captfiltxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0captfiltx::R`](R) reader structure"] -impl crate::Readable for Sm0captfiltxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0captfiltx::W`](W) writer structure"] -impl crate::Writable for Sm0captfiltxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0CAPTFILTX to value 0"] -impl crate::Resettable for Sm0captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cnt.rs b/mcxa276-pac/src/flexpwm0/sm0cnt.rs deleted file mode 100644 index 628826230..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0cnt.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM0CNT` reader"] -pub type R = crate::R; -#[doc = "Field `CNT` reader - Counter Register Bits"] -pub type CntR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Counter Register Bits"] - #[inline(always)] - pub fn cnt(&self) -> CntR { - CntR::new(self.bits) - } -} -#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0cntSpec; -impl crate::RegisterSpec for Sm0cntSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0cnt::R`](R) reader structure"] -impl crate::Readable for Sm0cntSpec {} -#[doc = "`reset()` method sets SM0CNT to value 0"] -impl crate::Resettable for Sm0cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0ctrl.rs b/mcxa276-pac/src/flexpwm0/sm0ctrl.rs deleted file mode 100644 index 123bd6598..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0ctrl.rs +++ /dev/null @@ -1,871 +0,0 @@ -#[doc = "Register `SM0CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM0CTRL` writer"] -pub type W = crate::W; -#[doc = "Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblen { - #[doc = "0: Double switching disabled."] - Disabled = 0, - #[doc = "1: Double switching enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLEN` reader - Double Switching Enable"] -pub type DblenR = crate::BitReader; -impl DblenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblen { - match self.bits { - false => Dblen::Disabled, - true => Dblen::Enabled, - } - } - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblen::Disabled - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblen::Enabled - } -} -#[doc = "Field `DBLEN` writer - Double Switching Enable"] -pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; -impl<'a, REG> DblenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblen::Disabled) - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblen::Enabled) - } -} -#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblx { - #[doc = "0: PWM_X double pulse disabled."] - Disabled = 0, - #[doc = "1: PWM_X double pulse enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] -pub type DblxR = crate::BitReader; -impl DblxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblx { - match self.bits { - false => Dblx::Disabled, - true => Dblx::Enabled, - } - } - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblx::Disabled - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblx::Enabled - } -} -#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] -pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; -impl<'a, REG> DblxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblx::Disabled) - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblx::Enabled) - } -} -#[doc = "Load Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldmod { - #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - NextPwmReload = 0, - #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - MtctrlLdokSet = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldmod) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDMOD` reader - Load Mode Select"] -pub type LdmodR = crate::BitReader; -impl LdmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldmod { - match self.bits { - false => Ldmod::NextPwmReload, - true => Ldmod::MtctrlLdokSet, - } - } - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn is_next_pwm_reload(&self) -> bool { - *self == Ldmod::NextPwmReload - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn is_mtctrl_ldok_set(&self) -> bool { - *self == Ldmod::MtctrlLdokSet - } -} -#[doc = "Field `LDMOD` writer - Load Mode Select"] -pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; -impl<'a, REG> LdmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn next_pwm_reload(self) -> &'a mut crate::W { - self.variant(Ldmod::NextPwmReload) - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { - self.variant(Ldmod::MtctrlLdokSet) - } -} -#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Split { - #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - Disabled = 0, - #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Split) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitR = crate::BitReader; -impl SplitR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Split { - match self.bits { - false => Split::Disabled, - true => Split::Enabled, - } - } - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Split::Disabled - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Split::Enabled - } -} -#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; -impl<'a, REG> SplitW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Split::Disabled) - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Split::Enabled) - } -} -#[doc = "Prescaler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Prsc { - #[doc = "0: Prescaler 1"] - One = 0, - #[doc = "1: Prescaler 2"] - Two = 1, - #[doc = "2: Prescaler 4"] - Four = 2, - #[doc = "3: Prescaler 8"] - Eight = 3, - #[doc = "4: Prescaler 16"] - Sixteen = 4, - #[doc = "5: Prescaler 32"] - Thirtytwo = 5, - #[doc = "6: Prescaler 64"] - Sixtyfour = 6, - #[doc = "7: Prescaler 128"] - Hundredtwentyeight = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Prsc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Prsc { - type Ux = u8; -} -impl crate::IsEnum for Prsc {} -#[doc = "Field `PRSC` reader - Prescaler"] -pub type PrscR = crate::FieldReader; -impl PrscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prsc { - match self.bits { - 0 => Prsc::One, - 1 => Prsc::Two, - 2 => Prsc::Four, - 3 => Prsc::Eight, - 4 => Prsc::Sixteen, - 5 => Prsc::Thirtytwo, - 6 => Prsc::Sixtyfour, - 7 => Prsc::Hundredtwentyeight, - _ => unreachable!(), - } - } - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Prsc::One - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn is_two(&self) -> bool { - *self == Prsc::Two - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn is_four(&self) -> bool { - *self == Prsc::Four - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn is_eight(&self) -> bool { - *self == Prsc::Eight - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn is_sixteen(&self) -> bool { - *self == Prsc::Sixteen - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn is_thirtytwo(&self) -> bool { - *self == Prsc::Thirtytwo - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn is_sixtyfour(&self) -> bool { - *self == Prsc::Sixtyfour - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn is_hundredtwentyeight(&self) -> bool { - *self == Prsc::Hundredtwentyeight - } -} -#[doc = "Field `PRSC` writer - Prescaler"] -pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; -impl<'a, REG> PrscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn one(self) -> &'a mut crate::W { - self.variant(Prsc::One) - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn two(self) -> &'a mut crate::W { - self.variant(Prsc::Two) - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn four(self) -> &'a mut crate::W { - self.variant(Prsc::Four) - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn eight(self) -> &'a mut crate::W { - self.variant(Prsc::Eight) - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn sixteen(self) -> &'a mut crate::W { - self.variant(Prsc::Sixteen) - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn thirtytwo(self) -> &'a mut crate::W { - self.variant(Prsc::Thirtytwo) - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn sixtyfour(self) -> &'a mut crate::W { - self.variant(Prsc::Sixtyfour) - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn hundredtwentyeight(self) -> &'a mut crate::W { - self.variant(Prsc::Hundredtwentyeight) - } -} -#[doc = "Compare Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Compmode { - #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - EqualTo = 0, - #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - EqualToOrGreaterThan = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Compmode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPMODE` reader - Compare Mode"] -pub type CompmodeR = crate::BitReader; -impl CompmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Compmode { - match self.bits { - false => Compmode::EqualTo, - true => Compmode::EqualToOrGreaterThan, - } - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn is_equal_to(&self) -> bool { - *self == Compmode::EqualTo - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn is_equal_to_or_greater_than(&self) -> bool { - *self == Compmode::EqualToOrGreaterThan - } -} -#[doc = "Field `COMPMODE` writer - Compare Mode"] -pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; -impl<'a, REG> CompmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn equal_to(self) -> &'a mut crate::W { - self.variant(Compmode::EqualTo) - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { - self.variant(Compmode::EqualToOrGreaterThan) - } -} -#[doc = "Field `DT` reader - Deadtime"] -pub type DtR = crate::FieldReader; -#[doc = "Full Cycle Reload\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Full { - #[doc = "0: Full-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Full-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FULL` reader - Full Cycle Reload"] -pub type FullR = crate::BitReader; -impl FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Full { - match self.bits { - false => Full::Disabled, - true => Full::Enabled, - } - } - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Full::Disabled - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Full::Enabled - } -} -#[doc = "Field `FULL` writer - Full Cycle Reload"] -pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; -impl<'a, REG> FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Full::Disabled) - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Full::Enabled) - } -} -#[doc = "Half Cycle Reload\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Half { - #[doc = "0: Half-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Half-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Half) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALF` reader - Half Cycle Reload"] -pub type HalfR = crate::BitReader; -impl HalfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Half { - match self.bits { - false => Half::Disabled, - true => Half::Enabled, - } - } - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Half::Disabled - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Half::Enabled - } -} -#[doc = "Field `HALF` writer - Half Cycle Reload"] -pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; -impl<'a, REG> HalfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Half::Disabled) - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Half::Enabled) - } -} -#[doc = "Load Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ldfq { - #[doc = "0: Every PWM opportunity"] - Everypwm = 0, - #[doc = "1: Every 2 PWM opportunities"] - Every2pwm = 1, - #[doc = "2: Every 3 PWM opportunities"] - Every3pwm = 2, - #[doc = "3: Every 4 PWM opportunities"] - Every4pwm = 3, - #[doc = "4: Every 5 PWM opportunities"] - Every5pwm = 4, - #[doc = "5: Every 6 PWM opportunities"] - Every6pwm = 5, - #[doc = "6: Every 7 PWM opportunities"] - Every7pwm = 6, - #[doc = "7: Every 8 PWM opportunities"] - Every8pwm = 7, - #[doc = "8: Every 9 PWM opportunities"] - Every9pwm = 8, - #[doc = "9: Every 10 PWM opportunities"] - Every10pwm = 9, - #[doc = "10: Every 11 PWM opportunities"] - Every11pwm = 10, - #[doc = "11: Every 12 PWM opportunities"] - Every12pwm = 11, - #[doc = "12: Every 13 PWM opportunities"] - Every13pwm = 12, - #[doc = "13: Every 14 PWM opportunities"] - Every14pwm = 13, - #[doc = "14: Every 15 PWM opportunities"] - Every15pwm = 14, - #[doc = "15: Every 16 PWM opportunities"] - Every16pwm = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ldfq) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ldfq { - type Ux = u8; -} -impl crate::IsEnum for Ldfq {} -#[doc = "Field `LDFQ` reader - Load Frequency"] -pub type LdfqR = crate::FieldReader; -impl LdfqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldfq { - match self.bits { - 0 => Ldfq::Everypwm, - 1 => Ldfq::Every2pwm, - 2 => Ldfq::Every3pwm, - 3 => Ldfq::Every4pwm, - 4 => Ldfq::Every5pwm, - 5 => Ldfq::Every6pwm, - 6 => Ldfq::Every7pwm, - 7 => Ldfq::Every8pwm, - 8 => Ldfq::Every9pwm, - 9 => Ldfq::Every10pwm, - 10 => Ldfq::Every11pwm, - 11 => Ldfq::Every12pwm, - 12 => Ldfq::Every13pwm, - 13 => Ldfq::Every14pwm, - 14 => Ldfq::Every15pwm, - 15 => Ldfq::Every16pwm, - _ => unreachable!(), - } - } - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Ldfq::Everypwm - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn is_every2pwm(&self) -> bool { - *self == Ldfq::Every2pwm - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn is_every3pwm(&self) -> bool { - *self == Ldfq::Every3pwm - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn is_every4pwm(&self) -> bool { - *self == Ldfq::Every4pwm - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn is_every5pwm(&self) -> bool { - *self == Ldfq::Every5pwm - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn is_every6pwm(&self) -> bool { - *self == Ldfq::Every6pwm - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn is_every7pwm(&self) -> bool { - *self == Ldfq::Every7pwm - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn is_every8pwm(&self) -> bool { - *self == Ldfq::Every8pwm - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn is_every9pwm(&self) -> bool { - *self == Ldfq::Every9pwm - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn is_every10pwm(&self) -> bool { - *self == Ldfq::Every10pwm - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn is_every11pwm(&self) -> bool { - *self == Ldfq::Every11pwm - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn is_every12pwm(&self) -> bool { - *self == Ldfq::Every12pwm - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn is_every13pwm(&self) -> bool { - *self == Ldfq::Every13pwm - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn is_every14pwm(&self) -> bool { - *self == Ldfq::Every14pwm - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn is_every15pwm(&self) -> bool { - *self == Ldfq::Every15pwm - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn is_every16pwm(&self) -> bool { - *self == Ldfq::Every16pwm - } -} -#[doc = "Field `LDFQ` writer - Load Frequency"] -pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; -impl<'a, REG> LdfqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Everypwm) - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn every2pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every2pwm) - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn every3pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every3pwm) - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn every4pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every4pwm) - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn every5pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every5pwm) - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn every6pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every6pwm) - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn every7pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every7pwm) - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn every8pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every8pwm) - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn every9pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every9pwm) - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn every10pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every10pwm) - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn every11pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every11pwm) - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn every12pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every12pwm) - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn every13pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every13pwm) - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn every14pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every14pwm) - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn every15pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every15pwm) - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn every16pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every16pwm) - } -} -impl R { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&self) -> DblenR { - DblenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&self) -> DblxR { - DblxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&self) -> LdmodR { - LdmodR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&self) -> SplitR { - SplitR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&self) -> PrscR { - PrscR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&self) -> CompmodeR { - CompmodeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Deadtime"] - #[inline(always)] - pub fn dt(&self) -> DtR { - DtR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&self) -> FullR { - FullR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&self) -> HalfR { - HalfR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&self) -> LdfqR { - LdfqR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&mut self) -> DblenW { - DblenW::new(self, 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&mut self) -> DblxW { - DblxW::new(self, 1) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&mut self) -> LdmodW { - LdmodW::new(self, 2) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&mut self) -> SplitW { - SplitW::new(self, 3) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&mut self) -> PrscW { - PrscW::new(self, 4) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&mut self) -> CompmodeW { - CompmodeW::new(self, 7) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&mut self) -> FullW { - FullW::new(self, 10) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&mut self) -> HalfW { - HalfW::new(self, 11) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&mut self) -> LdfqW { - LdfqW::new(self, 12) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0ctrlSpec; -impl crate::RegisterSpec for Sm0ctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0ctrl::R`](R) reader structure"] -impl crate::Readable for Sm0ctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0ctrl::W`](W) writer structure"] -impl crate::Writable for Sm0ctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0CTRL to value 0x0400"] -impl crate::Resettable for Sm0ctrlSpec { - const RESET_VALUE: u16 = 0x0400; -} diff --git a/mcxa276-pac/src/flexpwm0/sm0ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm0ctrl2.rs deleted file mode 100644 index a76bf79b9..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0ctrl2.rs +++ /dev/null @@ -1,607 +0,0 @@ -#[doc = "Register `SM0CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM0CTRL2` writer"] -pub type W = crate::W; -#[doc = "Clock Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ClkSel { - #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] - Ipbus = 0, - #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] - ExtClk = 1, - #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - AuxClk = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ClkSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ClkSel { - type Ux = u8; -} -impl crate::IsEnum for ClkSel {} -#[doc = "Field `CLK_SEL` reader - Clock Source Select"] -pub type ClkSelR = crate::FieldReader; -impl ClkSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(ClkSel::Ipbus), - 1 => Some(ClkSel::ExtClk), - 2 => Some(ClkSel::AuxClk), - _ => None, - } - } - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ipbus(&self) -> bool { - *self == ClkSel::Ipbus - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ext_clk(&self) -> bool { - *self == ClkSel::ExtClk - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn is_aux_clk(&self) -> bool { - *self == ClkSel::AuxClk - } -} -#[doc = "Field `CLK_SEL` writer - Clock Source Select"] -pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; -impl<'a, REG> ClkSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ipbus(self) -> &'a mut crate::W { - self.variant(ClkSel::Ipbus) - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ext_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::ExtClk) - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn aux_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::AuxClk) - } -} -#[doc = "Reload Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ReloadSel { - #[doc = "0: The local RELOAD signal is used to reload registers."] - Local = 0, - #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - Master = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ReloadSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] -pub type ReloadSelR = crate::BitReader; -impl ReloadSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ReloadSel { - match self.bits { - false => ReloadSel::Local, - true => ReloadSel::Master, - } - } - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ReloadSel::Local - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ReloadSel::Master - } -} -#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] -pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; -impl<'a, REG> ReloadSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ReloadSel::Local) - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ReloadSel::Master) - } -} -#[doc = "Force Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ForceSel { - #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - Local = 0, - #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - Master = 1, - #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - LocalReload = 2, - #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterReload = 3, - #[doc = "4: The local sync signal from this submodule is used to force updates."] - LocalSync = 4, - #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterSync = 5, - #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - ExtForce = 6, - #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - ExtSync = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ForceSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ForceSel { - type Ux = u8; -} -impl crate::IsEnum for ForceSel {} -#[doc = "Field `FORCE_SEL` reader - Force Select"] -pub type ForceSelR = crate::FieldReader; -impl ForceSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ForceSel { - match self.bits { - 0 => ForceSel::Local, - 1 => ForceSel::Master, - 2 => ForceSel::LocalReload, - 3 => ForceSel::MasterReload, - 4 => ForceSel::LocalSync, - 5 => ForceSel::MasterSync, - 6 => ForceSel::ExtForce, - 7 => ForceSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ForceSel::Local - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ForceSel::Master - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == ForceSel::LocalReload - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == ForceSel::MasterReload - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == ForceSel::LocalSync - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == ForceSel::MasterSync - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_force(&self) -> bool { - *self == ForceSel::ExtForce - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == ForceSel::ExtSync - } -} -#[doc = "Field `FORCE_SEL` writer - Force Select"] -pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; -impl<'a, REG> ForceSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ForceSel::Local) - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ForceSel::Master) - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalReload) - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterReload) - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalSync) - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterSync) - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_force(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtForce) - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtSync) - } -} -#[doc = "Field `FORCE` reader - Force Initialization"] -pub type ForceR = crate::BitReader; -#[doc = "Field `FORCE` writer - Force Initialization"] -pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Force Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frcen { - #[doc = "0: Initialization from a FORCE_OUT is disabled."] - Disabled = 0, - #[doc = "1: Initialization from a FORCE_OUT is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRCEN` reader - Force Enable"] -pub type FrcenR = crate::BitReader; -impl FrcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frcen { - match self.bits { - false => Frcen::Disabled, - true => Frcen::Enabled, - } - } - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Frcen::Disabled - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Frcen::Enabled - } -} -#[doc = "Field `FRCEN` writer - Force Enable"] -pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; -impl<'a, REG> FrcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Frcen::Disabled) - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Frcen::Enabled) - } -} -#[doc = "Initialization Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum InitSel { - #[doc = "0: Local sync (PWM_X) causes initialization."] - PwmX = 0, - #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - MasterReload = 1, - #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - MasterSync = 2, - #[doc = "3: EXT_SYNC causes initialization."] - ExtSync = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: InitSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for InitSel { - type Ux = u8; -} -impl crate::IsEnum for InitSel {} -#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] -pub type InitSelR = crate::FieldReader; -impl InitSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InitSel { - match self.bits { - 0 => InitSel::PwmX, - 1 => InitSel::MasterReload, - 2 => InitSel::MasterSync, - 3 => InitSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InitSel::PwmX - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == InitSel::MasterReload - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == InitSel::MasterSync - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == InitSel::ExtSync - } -} -#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] -pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; -impl<'a, REG> InitSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InitSel::PwmX) - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(InitSel::MasterReload) - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(InitSel::MasterSync) - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(InitSel::ExtSync) - } -} -#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] -pub type PwmxInitR = crate::BitReader; -#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] -pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] -pub type Pwm45InitR = crate::BitReader; -#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] -pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] -pub type Pwm23InitR = crate::BitReader; -#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] -pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Indep { - #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] - Complementary = 0, - #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] - Independent = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Indep) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] -pub type IndepR = crate::BitReader; -impl IndepR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Indep { - match self.bits { - false => Indep::Complementary, - true => Indep::Independent, - } - } - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn is_complementary(&self) -> bool { - *self == Indep::Complementary - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn is_independent(&self) -> bool { - *self == Indep::Independent - } -} -#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] -pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; -impl<'a, REG> IndepW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn complementary(self) -> &'a mut crate::W { - self.variant(Indep::Complementary) - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn independent(self) -> &'a mut crate::W { - self.variant(Indep::Independent) - } -} -#[doc = "Field `DBGEN` reader - Debug Enable"] -pub type DbgenR = crate::BitReader; -#[doc = "Field `DBGEN` writer - Debug Enable"] -pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&self) -> ClkSelR { - ClkSelR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&self) -> ReloadSelR { - ReloadSelR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&self) -> ForceSelR { - ForceSelR::new(((self.bits >> 3) & 7) as u8) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&self) -> ForceR { - ForceR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&self) -> FrcenR { - FrcenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&self) -> InitSelR { - InitSelR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&self) -> PwmxInitR { - PwmxInitR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&self) -> Pwm45InitR { - Pwm45InitR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&self) -> Pwm23InitR { - Pwm23InitR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&self) -> IndepR { - IndepR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&self) -> DbgenR { - DbgenR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&mut self) -> ClkSelW { - ClkSelW::new(self, 0) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&mut self) -> ReloadSelW { - ReloadSelW::new(self, 2) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&mut self) -> ForceSelW { - ForceSelW::new(self, 3) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&mut self) -> ForceW { - ForceW::new(self, 6) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&mut self) -> FrcenW { - FrcenW::new(self, 7) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&mut self) -> InitSelW { - InitSelW::new(self, 8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&mut self) -> PwmxInitW { - PwmxInitW::new(self, 10) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&mut self) -> Pwm45InitW { - Pwm45InitW::new(self, 11) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&mut self) -> Pwm23InitW { - Pwm23InitW::new(self, 12) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&mut self) -> IndepW { - IndepW::new(self, 13) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&mut self) -> DbgenW { - DbgenW::new(self, 15) - } -} -#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0ctrl2Spec; -impl crate::RegisterSpec for Sm0ctrl2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0ctrl2::R`](R) reader structure"] -impl crate::Readable for Sm0ctrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0ctrl2::W`](W) writer structure"] -impl crate::Writable for Sm0ctrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0CTRL2 to value 0"] -impl crate::Resettable for Sm0ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval0.rs b/mcxa276-pac/src/flexpwm0/sm0cval0.rs deleted file mode 100644 index 49f95676a..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0cval0.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM0CVAL0` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] -pub type Captval0R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 0"] - #[inline(always)] - pub fn captval0(&self) -> Captval0R { - Captval0R::new(self.bits) - } -} -#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0cval0Spec; -impl crate::RegisterSpec for Sm0cval0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0cval0::R`](R) reader structure"] -impl crate::Readable for Sm0cval0Spec {} -#[doc = "`reset()` method sets SM0CVAL0 to value 0"] -impl crate::Resettable for Sm0cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs deleted file mode 100644 index 9ae3f990b..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0cval0cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM0CVAL0CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] -pub type Cval0cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 0 Cycle"] - #[inline(always)] - pub fn cval0cyc(&self) -> Cval0cycR { - Cval0cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0cval0cycSpec; -impl crate::RegisterSpec for Sm0cval0cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0cval0cyc::R`](R) reader structure"] -impl crate::Readable for Sm0cval0cycSpec {} -#[doc = "`reset()` method sets SM0CVAL0CYC to value 0"] -impl crate::Resettable for Sm0cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval1.rs b/mcxa276-pac/src/flexpwm0/sm0cval1.rs deleted file mode 100644 index 2dd690fa0..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0cval1.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM0CVAL1` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] -pub type Captval1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 1"] - #[inline(always)] - pub fn captval1(&self) -> Captval1R { - Captval1R::new(self.bits) - } -} -#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0cval1Spec; -impl crate::RegisterSpec for Sm0cval1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0cval1::R`](R) reader structure"] -impl crate::Readable for Sm0cval1Spec {} -#[doc = "`reset()` method sets SM0CVAL1 to value 0"] -impl crate::Resettable for Sm0cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs deleted file mode 100644 index fd9d7737b..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0cval1cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM0CVAL1CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] -pub type Cval1cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 1 Cycle"] - #[inline(always)] - pub fn cval1cyc(&self) -> Cval1cycR { - Cval1cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0cval1cycSpec; -impl crate::RegisterSpec for Sm0cval1cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0cval1cyc::R`](R) reader structure"] -impl crate::Readable for Sm0cval1cycSpec {} -#[doc = "`reset()` method sets SM0CVAL1CYC to value 0"] -impl crate::Resettable for Sm0cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0dismap0.rs b/mcxa276-pac/src/flexpwm0/sm0dismap0.rs deleted file mode 100644 index ec64ffdf9..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0dismap0.rs +++ /dev/null @@ -1,65 +0,0 @@ -#[doc = "Register `SM0DISMAP0` reader"] -pub type R = crate::R; -#[doc = "Register `SM0DISMAP0` writer"] -pub type W = crate::W; -#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] -pub type Dis0aR = crate::FieldReader; -#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] -pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] -pub type Dis0bR = crate::FieldReader; -#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] -pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] -pub type Dis0xR = crate::FieldReader; -#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] -pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&self) -> Dis0aR { - Dis0aR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&self) -> Dis0bR { - Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&self) -> Dis0xR { - Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&mut self) -> Dis0aW { - Dis0aW::new(self, 0) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&mut self) -> Dis0bW { - Dis0bW::new(self, 4) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&mut self) -> Dis0xW { - Dis0xW::new(self, 8) - } -} -#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0dismap0Spec; -impl crate::RegisterSpec for Sm0dismap0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0dismap0::R`](R) reader structure"] -impl crate::Readable for Sm0dismap0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0dismap0::W`](W) writer structure"] -impl crate::Writable for Sm0dismap0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0DISMAP0 to value 0xffff"] -impl crate::Resettable for Sm0dismap0Spec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm0dmaen.rs b/mcxa276-pac/src/flexpwm0/sm0dmaen.rs deleted file mode 100644 index d6719ff21..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0dmaen.rs +++ /dev/null @@ -1,271 +0,0 @@ -#[doc = "Register `SM0DMAEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM0DMAEN` writer"] -pub type W = crate::W; -#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] -pub type Cx0deR = crate::BitReader; -#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] -pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] -pub type Cx1deR = crate::BitReader; -#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] -pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Captde { - #[doc = "0: Read DMA requests disabled."] - Disabled = 0, - #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - Exceedfifo = 1, - #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] - LocalSync = 2, - #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] - LocalReload = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Captde) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Captde { - type Ux = u8; -} -impl crate::IsEnum for Captde {} -#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] -pub type CaptdeR = crate::FieldReader; -impl CaptdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Captde { - match self.bits { - 0 => Captde::Disabled, - 1 => Captde::Exceedfifo, - 2 => Captde::LocalSync, - 3 => Captde::LocalReload, - _ => unreachable!(), - } - } - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Captde::Disabled - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn is_exceedfifo(&self) -> bool { - *self == Captde::Exceedfifo - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == Captde::LocalSync - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == Captde::LocalReload - } -} -#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] -pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; -impl<'a, REG> CaptdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Captde::Disabled) - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn exceedfifo(self) -> &'a mut crate::W { - self.variant(Captde::Exceedfifo) - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(Captde::LocalSync) - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(Captde::LocalReload) - } -} -#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fand { - #[doc = "0: Selected FIFO watermarks are OR'ed together."] - Or = 0, - #[doc = "1: Selected FIFO watermarks are AND'ed together."] - And = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fand) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] -pub type FandR = crate::BitReader; -impl FandR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fand { - match self.bits { - false => Fand::Or, - true => Fand::And, - } - } - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn is_or(&self) -> bool { - *self == Fand::Or - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn is_and(&self) -> bool { - *self == Fand::And - } -} -#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] -pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; -impl<'a, REG> FandW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn or(self) -> &'a mut crate::W { - self.variant(Fand::Or) - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn and(self) -> &'a mut crate::W { - self.variant(Fand::And) - } -} -#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Valde { - #[doc = "0: DMA write requests disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Valde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] -pub type ValdeR = crate::BitReader; -impl ValdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Valde { - match self.bits { - false => Valde::Disabled, - true => Valde::Enabled, - } - } - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Valde::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Valde::Enabled - } -} -#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] -pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; -impl<'a, REG> ValdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Valde::Disabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Valde::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&self) -> Cx0deR { - Cx0deR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&self) -> Cx1deR { - Cx1deR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&self) -> CaptdeR { - CaptdeR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&self) -> FandR { - FandR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&self) -> ValdeR { - ValdeR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&mut self) -> Cx0deW { - Cx0deW::new(self, 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&mut self) -> Cx1deW { - Cx1deW::new(self, 1) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&mut self) -> CaptdeW { - CaptdeW::new(self, 6) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&mut self) -> FandW { - FandW::new(self, 8) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&mut self) -> ValdeW { - ValdeW::new(self, 9) - } -} -#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0dmaenSpec; -impl crate::RegisterSpec for Sm0dmaenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0dmaen::R`](R) reader structure"] -impl crate::Readable for Sm0dmaenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0dmaen::W`](W) writer structure"] -impl crate::Writable for Sm0dmaenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0DMAEN to value 0"] -impl crate::Resettable for Sm0dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs deleted file mode 100644 index f5548e94c..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0dtcnt0.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM0DTCNT0` reader"] -pub type R = crate::R; -#[doc = "Register `SM0DTCNT0` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] -pub type Dtcnt0R = crate::FieldReader; -#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] -pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&self) -> Dtcnt0R { - Dtcnt0R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&mut self) -> Dtcnt0W { - Dtcnt0W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0dtcnt0Spec; -impl crate::RegisterSpec for Sm0dtcnt0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0dtcnt0::R`](R) reader structure"] -impl crate::Readable for Sm0dtcnt0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0dtcnt0::W`](W) writer structure"] -impl crate::Writable for Sm0dtcnt0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0DTCNT0 to value 0x07ff"] -impl crate::Resettable for Sm0dtcnt0Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs deleted file mode 100644 index 408c6739f..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0dtcnt1.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM0DTCNT1` reader"] -pub type R = crate::R; -#[doc = "Register `SM0DTCNT1` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] -pub type Dtcnt1R = crate::FieldReader; -#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] -pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&self) -> Dtcnt1R { - Dtcnt1R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&mut self) -> Dtcnt1W { - Dtcnt1W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0dtcnt1Spec; -impl crate::RegisterSpec for Sm0dtcnt1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0dtcnt1::R`](R) reader structure"] -impl crate::Readable for Sm0dtcnt1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0dtcnt1::W`](W) writer structure"] -impl crate::Writable for Sm0dtcnt1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0DTCNT1 to value 0x07ff"] -impl crate::Resettable for Sm0dtcnt1Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm0init.rs b/mcxa276-pac/src/flexpwm0/sm0init.rs deleted file mode 100644 index c2b0617d3..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0init.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM0INIT` reader"] -pub type R = crate::R; -#[doc = "Register `SM0INIT` writer"] -pub type W = crate::W; -#[doc = "Field `INIT` reader - Initial Count Register Bits"] -pub type InitR = crate::FieldReader; -#[doc = "Field `INIT` writer - Initial Count Register Bits"] -pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&self) -> InitR { - InitR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&mut self) -> InitW { - InitW::new(self, 0) - } -} -#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0initSpec; -impl crate::RegisterSpec for Sm0initSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0init::R`](R) reader structure"] -impl crate::Readable for Sm0initSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0init::W`](W) writer structure"] -impl crate::Writable for Sm0initSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0INIT to value 0"] -impl crate::Resettable for Sm0initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0inten.rs b/mcxa276-pac/src/flexpwm0/sm0inten.rs deleted file mode 100644 index 6f2cdae10..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0inten.rs +++ /dev/null @@ -1,343 +0,0 @@ -#[doc = "Register `SM0INTEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM0INTEN` writer"] -pub type W = crate::W; -#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpie { - #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - Disabled = 0, - #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - Enabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpie) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpie { - type Ux = u8; -} -impl crate::IsEnum for Cmpie {} -#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] -pub type CmpieR = crate::FieldReader; -impl CmpieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpie::Disabled), - 1 => Some(Cmpie::Enabled), - _ => None, - } - } - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmpie::Disabled - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmpie::Enabled - } -} -#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] -pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; -impl<'a, REG> CmpieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Disabled) - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Enabled) - } -} -#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx0ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx0ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] -pub type Cx0ieR = crate::BitReader; -impl Cx0ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx0ie { - match self.bits { - false => Cx0ie::Disabled, - true => Cx0ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx0ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx0ie::Enabled - } -} -#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] -pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; -impl<'a, REG> Cx0ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Enabled) - } -} -#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx1ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx1ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] -pub type Cx1ieR = crate::BitReader; -impl Cx1ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx1ie { - match self.bits { - false => Cx1ie::Disabled, - true => Cx1ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx1ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx1ie::Enabled - } -} -#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] -pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; -impl<'a, REG> Cx1ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Enabled) - } -} -#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rie { - #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RIE` reader - Reload Interrupt Enable"] -pub type RieR = crate::BitReader; -impl RieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rie { - match self.bits { - false => Rie::Disabled, - true => Rie::Enabled, - } - } - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rie::Disabled - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rie::Enabled - } -} -#[doc = "Field `RIE` writer - Reload Interrupt Enable"] -pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; -impl<'a, REG> RieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rie::Disabled) - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rie::Enabled) - } -} -#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reie { - #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] -pub type ReieR = crate::BitReader; -impl ReieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reie { - match self.bits { - false => Reie::Disabled, - true => Reie::Enabled, - } - } - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Reie::Disabled - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Reie::Enabled - } -} -#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] -pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; -impl<'a, REG> ReieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Reie::Disabled) - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Reie::Enabled) - } -} -impl R { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&self) -> CmpieR { - CmpieR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&self) -> Cx0ieR { - Cx0ieR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&self) -> Cx1ieR { - Cx1ieR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&self) -> RieR { - RieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&self) -> ReieR { - ReieR::new(((self.bits >> 13) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&mut self) -> CmpieW { - CmpieW::new(self, 0) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&mut self) -> Cx0ieW { - Cx0ieW::new(self, 6) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&mut self) -> Cx1ieW { - Cx1ieW::new(self, 7) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&mut self) -> RieW { - RieW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&mut self) -> ReieW { - ReieW::new(self, 13) - } -} -#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0intenSpec; -impl crate::RegisterSpec for Sm0intenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0inten::R`](R) reader structure"] -impl crate::Readable for Sm0intenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0inten::W`](W) writer structure"] -impl crate::Writable for Sm0intenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0INTEN to value 0"] -impl crate::Resettable for Sm0intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0octrl.rs b/mcxa276-pac/src/flexpwm0/sm0octrl.rs deleted file mode 100644 index 9eac3b923..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0octrl.rs +++ /dev/null @@ -1,519 +0,0 @@ -#[doc = "Register `SM0OCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM0OCTRL` writer"] -pub type W = crate::W; -#[doc = "PWM_X Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmxfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmxfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmxfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmxfs {} -#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] -pub type PwmxfsR = crate::FieldReader; -impl PwmxfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmxfs { - match self.bits { - 0 => Pwmxfs::Logic0, - 1 => Pwmxfs::Logic1, - 2 => Pwmxfs::Tristated2, - 3 => Pwmxfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmxfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmxfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmxfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmxfs::Tristated3 - } -} -#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] -pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; -impl<'a, REG> PwmxfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated3) - } -} -#[doc = "PWM_B Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmbfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmbfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmbfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmbfs {} -#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] -pub type PwmbfsR = crate::FieldReader; -impl PwmbfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmbfs { - match self.bits { - 0 => Pwmbfs::Logic0, - 1 => Pwmbfs::Logic1, - 2 => Pwmbfs::Tristated2, - 3 => Pwmbfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmbfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmbfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmbfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmbfs::Tristated3 - } -} -#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] -pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; -impl<'a, REG> PwmbfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated3) - } -} -#[doc = "PWM_A Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmafs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmafs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmafs { - type Ux = u8; -} -impl crate::IsEnum for Pwmafs {} -#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] -pub type PwmafsR = crate::FieldReader; -impl PwmafsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmafs { - match self.bits { - 0 => Pwmafs::Logic0, - 1 => Pwmafs::Logic1, - 2 => Pwmafs::Tristated2, - 3 => Pwmafs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmafs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmafs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmafs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmafs::Tristated3 - } -} -#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] -pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; -impl<'a, REG> PwmafsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated3) - } -} -#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polx { - #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLX` reader - PWM_X Output Polarity"] -pub type PolxR = crate::BitReader; -impl PolxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polx { - match self.bits { - false => Polx::NotInverted, - true => Polx::Inverted, - } - } - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polx::NotInverted - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polx::Inverted - } -} -#[doc = "Field `POLX` writer - PWM_X Output Polarity"] -pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; -impl<'a, REG> PolxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polx::NotInverted) - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polx::Inverted) - } -} -#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polb { - #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLB` reader - PWM_B Output Polarity"] -pub type PolbR = crate::BitReader; -impl PolbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polb { - match self.bits { - false => Polb::NotInverted, - true => Polb::Inverted, - } - } - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polb::NotInverted - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polb::Inverted - } -} -#[doc = "Field `POLB` writer - PWM_B Output Polarity"] -pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; -impl<'a, REG> PolbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polb::NotInverted) - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polb::Inverted) - } -} -#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pola { - #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pola) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLA` reader - PWM_A Output Polarity"] -pub type PolaR = crate::BitReader; -impl PolaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pola { - match self.bits { - false => Pola::NotInverted, - true => Pola::Inverted, - } - } - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Pola::NotInverted - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Pola::Inverted - } -} -#[doc = "Field `POLA` writer - PWM_A Output Polarity"] -pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; -impl<'a, REG> PolaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Pola::NotInverted) - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Pola::Inverted) - } -} -#[doc = "Field `PWMX_IN` reader - PWM_X Input"] -pub type PwmxInR = crate::BitReader; -#[doc = "Field `PWMB_IN` reader - PWM_B Input"] -pub type PwmbInR = crate::BitReader; -#[doc = "Field `PWMA_IN` reader - PWM_A Input"] -pub type PwmaInR = crate::BitReader; -impl R { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&self) -> PwmxfsR { - PwmxfsR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&self) -> PwmbfsR { - PwmbfsR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&self) -> PwmafsR { - PwmafsR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&self) -> PolxR { - PolxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&self) -> PolbR { - PolbR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&self) -> PolaR { - PolaR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 13 - PWM_X Input"] - #[inline(always)] - pub fn pwmx_in(&self) -> PwmxInR { - PwmxInR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - PWM_B Input"] - #[inline(always)] - pub fn pwmb_in(&self) -> PwmbInR { - PwmbInR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - PWM_A Input"] - #[inline(always)] - pub fn pwma_in(&self) -> PwmaInR { - PwmaInR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&mut self) -> PwmxfsW { - PwmxfsW::new(self, 0) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&mut self) -> PwmbfsW { - PwmbfsW::new(self, 2) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&mut self) -> PwmafsW { - PwmafsW::new(self, 4) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&mut self) -> PolxW { - PolxW::new(self, 8) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&mut self) -> PolbW { - PolbW::new(self, 9) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&mut self) -> PolaW { - PolaW::new(self, 10) - } -} -#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0octrlSpec; -impl crate::RegisterSpec for Sm0octrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0octrl::R`](R) reader structure"] -impl crate::Readable for Sm0octrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0octrl::W`](W) writer structure"] -impl crate::Writable for Sm0octrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0OCTRL to value 0"] -impl crate::Resettable for Sm0octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0sts.rs b/mcxa276-pac/src/flexpwm0/sm0sts.rs deleted file mode 100644 index 087cd434e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0sts.rs +++ /dev/null @@ -1,287 +0,0 @@ -#[doc = "Register `SM0STS` reader"] -pub type R = crate::R; -#[doc = "Register `SM0STS` writer"] -pub type W = crate::W; -#[doc = "Compare Flags\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpf { - #[doc = "0: No compare event has occurred for a particular VALx value."] - NoEvent = 0, - #[doc = "1: A compare event has occurred for a particular VALx value."] - Event = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpf { - type Ux = u8; -} -impl crate::IsEnum for Cmpf {} -#[doc = "Field `CMPF` reader - Compare Flags"] -pub type CmpfR = crate::FieldReader; -impl CmpfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpf::NoEvent), - 1 => Some(Cmpf::Event), - _ => None, - } - } - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_no_event(&self) -> bool { - *self == Cmpf::NoEvent - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_event(&self) -> bool { - *self == Cmpf::Event - } -} -#[doc = "Field `CMPF` writer - Compare Flags"] -pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; -impl<'a, REG> CmpfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn no_event(self) -> &'a mut crate::W { - self.variant(Cmpf::NoEvent) - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn event(self) -> &'a mut crate::W { - self.variant(Cmpf::Event) - } -} -#[doc = "Field `CFX0` reader - Capture Flag X0"] -pub type Cfx0R = crate::BitReader; -#[doc = "Field `CFX0` writer - Capture Flag X0"] -pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `CFX1` reader - Capture Flag X1"] -pub type Cfx1R = crate::BitReader; -#[doc = "Field `CFX1` writer - Capture Flag X1"] -pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Reload Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rf { - #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] - NoFlag = 0, - #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RF` reader - Reload Flag"] -pub type RfR = crate::BitReader; -impl RfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rf { - match self.bits { - false => Rf::NoFlag, - true => Rf::Flag, - } - } - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Rf::NoFlag - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Rf::Flag - } -} -#[doc = "Field `RF` writer - Reload Flag"] -pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; -impl<'a, REG> RfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Rf::NoFlag) - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Rf::Flag) - } -} -#[doc = "Reload Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ref { - #[doc = "0: No reload error occurred."] - NoFlag = 0, - #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ref) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REF` reader - Reload Error Flag"] -pub type RefR = crate::BitReader; -impl RefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ref { - match self.bits { - false => Ref::NoFlag, - true => Ref::Flag, - } - } - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ref::NoFlag - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ref::Flag - } -} -#[doc = "Field `REF` writer - Reload Error Flag"] -pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; -impl<'a, REG> RefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Ref::NoFlag) - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Ref::Flag) - } -} -#[doc = "Registers Updated Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ruf { - #[doc = "0: No register update has occurred since last reload."] - NoFlag = 0, - #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ruf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RUF` reader - Registers Updated Flag"] -pub type RufR = crate::BitReader; -impl RufR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ruf { - match self.bits { - false => Ruf::NoFlag, - true => Ruf::Flag, - } - } - #[doc = "No register update has occurred since last reload."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ruf::NoFlag - } - #[doc = "At least one of the double buffered registers has been updated since the last reload."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ruf::Flag - } -} -impl R { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&self) -> CmpfR { - CmpfR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&self) -> Cfx0R { - Cfx0R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&self) -> Cfx1R { - Cfx1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&self) -> RfR { - RfR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&self) -> RefR { - RefR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Registers Updated Flag"] - #[inline(always)] - pub fn ruf(&self) -> RufR { - RufR::new(((self.bits >> 14) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&mut self) -> CmpfW { - CmpfW::new(self, 0) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&mut self) -> Cfx0W { - Cfx0W::new(self, 6) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&mut self) -> Cfx1W { - Cfx1W::new(self, 7) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&mut self) -> RfW { - RfW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&mut self) -> RefW { - RefW::new(self, 13) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0stsSpec; -impl crate::RegisterSpec for Sm0stsSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0sts::R`](R) reader structure"] -impl crate::Readable for Sm0stsSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0sts::W`](W) writer structure"] -impl crate::Writable for Sm0stsSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; -} -#[doc = "`reset()` method sets SM0STS to value 0"] -impl crate::Resettable for Sm0stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0tctrl.rs b/mcxa276-pac/src/flexpwm0/sm0tctrl.rs deleted file mode 100644 index c4976fdb1..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0tctrl.rs +++ /dev/null @@ -1,267 +0,0 @@ -#[doc = "Register `SM0TCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM0TCTRL` writer"] -pub type W = crate::W; -#[doc = "Output Trigger Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OutTrigEn { - #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - Val0 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OutTrigEn) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OutTrigEn { - type Ux = u8; -} -impl crate::IsEnum for OutTrigEn {} -#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] -pub type OutTrigEnR = crate::FieldReader; -impl OutTrigEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(OutTrigEn::Val0), - _ => None, - } - } - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == OutTrigEn::Val0 - } -} -#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] -pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; -impl<'a, REG> OutTrigEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn val0(self) -> &'a mut crate::W { - self.variant(OutTrigEn::Val0) - } -} -#[doc = "Trigger Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trgfrq { - #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Everypwm = 0, - #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Finalpwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trgfrq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] -pub type TrgfrqR = crate::BitReader; -impl TrgfrqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgfrq { - match self.bits { - false => Trgfrq::Everypwm, - true => Trgfrq::Finalpwm, - } - } - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Trgfrq::Everypwm - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_finalpwm(&self) -> bool { - *self == Trgfrq::Finalpwm - } -} -#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] -pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; -impl<'a, REG> TrgfrqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Everypwm) - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn finalpwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Finalpwm) - } -} -#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwbot1 { - #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - PwmOutTrig1Signal = 0, - #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] - PwmbOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwbot1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] -pub type Pwbot1R = crate::BitReader; -impl Pwbot1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwbot1 { - match self.bits { - false => Pwbot1::PwmOutTrig1Signal, - true => Pwbot1::PwmbOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwm_out_trig1_signal(&self) -> bool { - *self == Pwbot1::PwmOutTrig1Signal - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwmb_output(&self) -> bool { - *self == Pwbot1::PwmbOutput - } -} -#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] -pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; -impl<'a, REG> Pwbot1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmOutTrig1Signal) - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwmb_output(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmbOutput) - } -} -#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwaot0 { - #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - PwmOutTrig0Signal = 0, - #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] - PwmaOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwaot0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] -pub type Pwaot0R = crate::BitReader; -impl Pwaot0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwaot0 { - match self.bits { - false => Pwaot0::PwmOutTrig0Signal, - true => Pwaot0::PwmaOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwm_out_trig0_signal(&self) -> bool { - *self == Pwaot0::PwmOutTrig0Signal - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwma_output(&self) -> bool { - *self == Pwaot0::PwmaOutput - } -} -#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] -pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; -impl<'a, REG> Pwaot0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmOutTrig0Signal) - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwma_output(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmaOutput) - } -} -impl R { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&self) -> OutTrigEnR { - OutTrigEnR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&self) -> TrgfrqR { - TrgfrqR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&self) -> Pwbot1R { - Pwbot1R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&self) -> Pwaot0R { - Pwaot0R::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&mut self) -> OutTrigEnW { - OutTrigEnW::new(self, 0) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&mut self) -> TrgfrqW { - TrgfrqW::new(self, 12) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&mut self) -> Pwbot1W { - Pwbot1W::new(self, 14) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&mut self) -> Pwaot0W { - Pwaot0W::new(self, 15) - } -} -#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0tctrlSpec; -impl crate::RegisterSpec for Sm0tctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0tctrl::R`](R) reader structure"] -impl crate::Readable for Sm0tctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm0tctrl::W`](W) writer structure"] -impl crate::Writable for Sm0tctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0TCTRL to value 0"] -impl crate::Resettable for Sm0tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val0.rs b/mcxa276-pac/src/flexpwm0/sm0val0.rs deleted file mode 100644 index 3f15605b5..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0val0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM0VAL0` reader"] -pub type R = crate::R; -#[doc = "Register `SM0VAL0` writer"] -pub type W = crate::W; -#[doc = "Field `VAL0` reader - Value 0"] -pub type Val0R = crate::FieldReader; -#[doc = "Field `VAL0` writer - Value 0"] -pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&self) -> Val0R { - Val0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&mut self) -> Val0W { - Val0W::new(self, 0) - } -} -#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0val0Spec; -impl crate::RegisterSpec for Sm0val0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0val0::R`](R) reader structure"] -impl crate::Readable for Sm0val0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0val0::W`](W) writer structure"] -impl crate::Writable for Sm0val0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0VAL0 to value 0"] -impl crate::Resettable for Sm0val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val1.rs b/mcxa276-pac/src/flexpwm0/sm0val1.rs deleted file mode 100644 index b924478d1..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0val1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM0VAL1` reader"] -pub type R = crate::R; -#[doc = "Register `SM0VAL1` writer"] -pub type W = crate::W; -#[doc = "Field `VAL1` reader - Value 1"] -pub type Val1R = crate::FieldReader; -#[doc = "Field `VAL1` writer - Value 1"] -pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&self) -> Val1R { - Val1R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&mut self) -> Val1W { - Val1W::new(self, 0) - } -} -#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0val1Spec; -impl crate::RegisterSpec for Sm0val1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0val1::R`](R) reader structure"] -impl crate::Readable for Sm0val1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0val1::W`](W) writer structure"] -impl crate::Writable for Sm0val1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0VAL1 to value 0"] -impl crate::Resettable for Sm0val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val2.rs b/mcxa276-pac/src/flexpwm0/sm0val2.rs deleted file mode 100644 index bee801ffb..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0val2.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM0VAL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM0VAL2` writer"] -pub type W = crate::W; -#[doc = "Field `VAL2` reader - Value 2"] -pub type Val2R = crate::FieldReader; -#[doc = "Field `VAL2` writer - Value 2"] -pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&self) -> Val2R { - Val2R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&mut self) -> Val2W { - Val2W::new(self, 0) - } -} -#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0val2Spec; -impl crate::RegisterSpec for Sm0val2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0val2::R`](R) reader structure"] -impl crate::Readable for Sm0val2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0val2::W`](W) writer structure"] -impl crate::Writable for Sm0val2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0VAL2 to value 0"] -impl crate::Resettable for Sm0val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val3.rs b/mcxa276-pac/src/flexpwm0/sm0val3.rs deleted file mode 100644 index a1831ca34..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0val3.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM0VAL3` reader"] -pub type R = crate::R; -#[doc = "Register `SM0VAL3` writer"] -pub type W = crate::W; -#[doc = "Field `VAL3` reader - Value 3"] -pub type Val3R = crate::FieldReader; -#[doc = "Field `VAL3` writer - Value 3"] -pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&self) -> Val3R { - Val3R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&mut self) -> Val3W { - Val3W::new(self, 0) - } -} -#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0val3Spec; -impl crate::RegisterSpec for Sm0val3Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0val3::R`](R) reader structure"] -impl crate::Readable for Sm0val3Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0val3::W`](W) writer structure"] -impl crate::Writable for Sm0val3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0VAL3 to value 0"] -impl crate::Resettable for Sm0val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val4.rs b/mcxa276-pac/src/flexpwm0/sm0val4.rs deleted file mode 100644 index 1e1f114dd..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0val4.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM0VAL4` reader"] -pub type R = crate::R; -#[doc = "Register `SM0VAL4` writer"] -pub type W = crate::W; -#[doc = "Field `VAL4` reader - Value 4"] -pub type Val4R = crate::FieldReader; -#[doc = "Field `VAL4` writer - Value 4"] -pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&self) -> Val4R { - Val4R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&mut self) -> Val4W { - Val4W::new(self, 0) - } -} -#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0val4Spec; -impl crate::RegisterSpec for Sm0val4Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0val4::R`](R) reader structure"] -impl crate::Readable for Sm0val4Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0val4::W`](W) writer structure"] -impl crate::Writable for Sm0val4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0VAL4 to value 0"] -impl crate::Resettable for Sm0val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm0val5.rs b/mcxa276-pac/src/flexpwm0/sm0val5.rs deleted file mode 100644 index 6b7f10d45..000000000 --- a/mcxa276-pac/src/flexpwm0/sm0val5.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM0VAL5` reader"] -pub type R = crate::R; -#[doc = "Register `SM0VAL5` writer"] -pub type W = crate::W; -#[doc = "Field `VAL5` reader - Value 5"] -pub type Val5R = crate::FieldReader; -#[doc = "Field `VAL5` writer - Value 5"] -pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&self) -> Val5R { - Val5R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&mut self) -> Val5W { - Val5W::new(self, 0) - } -} -#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm0val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm0val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm0val5Spec; -impl crate::RegisterSpec for Sm0val5Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm0val5::R`](R) reader structure"] -impl crate::Readable for Sm0val5Spec {} -#[doc = "`write(|w| ..)` method takes [`sm0val5::W`](W) writer structure"] -impl crate::Writable for Sm0val5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM0VAL5 to value 0"] -impl crate::Resettable for Sm0val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1captcompx.rs b/mcxa276-pac/src/flexpwm0/sm1captcompx.rs deleted file mode 100644 index abb6a9523..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1captcompx.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `SM1CAPTCOMPX` reader"] -pub type R = crate::R; -#[doc = "Register `SM1CAPTCOMPX` writer"] -pub type W = crate::W; -#[doc = "Field `EDGCMPX` reader - Edge Compare X"] -pub type EdgcmpxR = crate::FieldReader; -#[doc = "Field `EDGCMPX` writer - Edge Compare X"] -pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EDGCNTX` reader - Edge Counter X"] -pub type EdgcntxR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&self) -> EdgcmpxR { - EdgcmpxR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Edge Counter X"] - #[inline(always)] - pub fn edgcntx(&self) -> EdgcntxR { - EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&mut self) -> EdgcmpxW { - EdgcmpxW::new(self, 0) - } -} -#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1captcompxSpec; -impl crate::RegisterSpec for Sm1captcompxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1captcompx::R`](R) reader structure"] -impl crate::Readable for Sm1captcompxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1captcompx::W`](W) writer structure"] -impl crate::Writable for Sm1captcompxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1CAPTCOMPX to value 0"] -impl crate::Resettable for Sm1captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm1captctrlx.rs deleted file mode 100644 index 0eb57f95b..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1captctrlx.rs +++ /dev/null @@ -1,493 +0,0 @@ -#[doc = "Register `SM1CAPTCTRLX` reader"] -pub type R = crate::R; -#[doc = "Register `SM1CAPTCTRLX` writer"] -pub type W = crate::W; -#[doc = "Arm X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Armx { - #[doc = "0: Input capture operation is disabled."] - Disabled = 0, - #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Armx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ARMX` reader - Arm X"] -pub type ArmxR = crate::BitReader; -impl ArmxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Armx { - match self.bits { - false => Armx::Disabled, - true => Armx::Enabled, - } - } - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Armx::Disabled - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Armx::Enabled - } -} -#[doc = "Field `ARMX` writer - Arm X"] -pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; -impl<'a, REG> ArmxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Armx::Disabled) - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Armx::Enabled) - } -} -#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Oneshotx { - #[doc = "0: Free Running"] - FreeRunning = 0, - #[doc = "1: One Shot"] - OneShot = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Oneshotx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] -pub type OneshotxR = crate::BitReader; -impl OneshotxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Oneshotx { - match self.bits { - false => Oneshotx::FreeRunning, - true => Oneshotx::OneShot, - } - } - #[doc = "Free Running"] - #[inline(always)] - pub fn is_free_running(&self) -> bool { - *self == Oneshotx::FreeRunning - } - #[doc = "One Shot"] - #[inline(always)] - pub fn is_one_shot(&self) -> bool { - *self == Oneshotx::OneShot - } -} -#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] -pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; -impl<'a, REG> OneshotxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Free Running"] - #[inline(always)] - pub fn free_running(self) -> &'a mut crate::W { - self.variant(Oneshotx::FreeRunning) - } - #[doc = "One Shot"] - #[inline(always)] - pub fn one_shot(self) -> &'a mut crate::W { - self.variant(Oneshotx::OneShot) - } -} -#[doc = "Edge X 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx0 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx0 { - type Ux = u8; -} -impl crate::IsEnum for Edgx0 {} -#[doc = "Field `EDGX0` reader - Edge X 0"] -pub type Edgx0R = crate::FieldReader; -impl Edgx0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx0 { - match self.bits { - 0 => Edgx0::Disabled, - 1 => Edgx0::FallingEdge, - 2 => Edgx0::RisingEdge, - 3 => Edgx0::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx0::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx0::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx0::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx0::AnyEdge - } -} -#[doc = "Field `EDGX0` writer - Edge X 0"] -pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; -impl<'a, REG> Edgx0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx0::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::AnyEdge) - } -} -#[doc = "Edge X 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx1 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx1 { - type Ux = u8; -} -impl crate::IsEnum for Edgx1 {} -#[doc = "Field `EDGX1` reader - Edge X 1"] -pub type Edgx1R = crate::FieldReader; -impl Edgx1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx1 { - match self.bits { - 0 => Edgx1::Disabled, - 1 => Edgx1::FallingEdge, - 2 => Edgx1::RisingEdge, - 3 => Edgx1::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx1::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx1::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx1::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx1::AnyEdge - } -} -#[doc = "Field `EDGX1` writer - Edge X 1"] -pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; -impl<'a, REG> Edgx1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx1::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::AnyEdge) - } -} -#[doc = "Input Select X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum InpSelx { - #[doc = "0: Raw PWM_X input signal selected as source."] - PwmX = 0, - #[doc = "1: Edge Counter"] - EdgeCounter = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: InpSelx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INP_SELX` reader - Input Select X"] -pub type InpSelxR = crate::BitReader; -impl InpSelxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InpSelx { - match self.bits { - false => InpSelx::PwmX, - true => InpSelx::EdgeCounter, - } - } - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InpSelx::PwmX - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn is_edge_counter(&self) -> bool { - *self == InpSelx::EdgeCounter - } -} -#[doc = "Field `INP_SELX` writer - Input Select X"] -pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; -impl<'a, REG> InpSelxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InpSelx::PwmX) - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn edge_counter(self) -> &'a mut crate::W { - self.variant(InpSelx::EdgeCounter) - } -} -#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EdgcntxEn { - #[doc = "0: Edge counter disabled and held in reset"] - Disabled = 0, - #[doc = "1: Edge counter enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EdgcntxEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] -pub type EdgcntxEnR = crate::BitReader; -impl EdgcntxEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EdgcntxEn { - match self.bits { - false => EdgcntxEn::Disabled, - true => EdgcntxEn::Enabled, - } - } - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == EdgcntxEn::Disabled - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == EdgcntxEn::Enabled - } -} -#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] -pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; -impl<'a, REG> EdgcntxEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Disabled) - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Enabled) - } -} -#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] -pub type CfxwmR = crate::FieldReader; -#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] -pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] -pub type Cx0cntR = crate::FieldReader; -#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] -pub type Cx1cntR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&self) -> ArmxR { - ArmxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&self) -> OneshotxR { - OneshotxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&self) -> Edgx0R { - Edgx0R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&self) -> Edgx1R { - Edgx1R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&self) -> InpSelxR { - InpSelxR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&self) -> EdgcntxEnR { - EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&self) -> CfxwmR { - CfxwmR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] - #[inline(always)] - pub fn cx0cnt(&self) -> Cx0cntR { - Cx0cntR::new(((self.bits >> 10) & 7) as u8) - } - #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] - #[inline(always)] - pub fn cx1cnt(&self) -> Cx1cntR { - Cx1cntR::new(((self.bits >> 13) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&mut self) -> ArmxW { - ArmxW::new(self, 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&mut self) -> OneshotxW { - OneshotxW::new(self, 1) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&mut self) -> Edgx0W { - Edgx0W::new(self, 2) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&mut self) -> Edgx1W { - Edgx1W::new(self, 4) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&mut self) -> InpSelxW { - InpSelxW::new(self, 6) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&mut self) -> EdgcntxEnW { - EdgcntxEnW::new(self, 7) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&mut self) -> CfxwmW { - CfxwmW::new(self, 8) - } -} -#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1captctrlxSpec; -impl crate::RegisterSpec for Sm1captctrlxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1captctrlx::R`](R) reader structure"] -impl crate::Readable for Sm1captctrlxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1captctrlx::W`](W) writer structure"] -impl crate::Writable for Sm1captctrlxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1CAPTCTRLX to value 0"] -impl crate::Resettable for Sm1captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm1captfiltx.rs deleted file mode 100644 index 886ae63ba..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1captfiltx.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `SM1CAPTFILTX` reader"] -pub type R = crate::R; -#[doc = "Register `SM1CAPTFILTX` writer"] -pub type W = crate::W; -#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] -pub type CaptxFiltPerR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] -pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] -pub type CaptxFiltCntR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] -pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&self) -> CaptxFiltPerR { - CaptxFiltPerR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { - CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { - CaptxFiltPerW::new(self, 0) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { - CaptxFiltCntW::new(self, 8) - } -} -#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1captfiltxSpec; -impl crate::RegisterSpec for Sm1captfiltxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1captfiltx::R`](R) reader structure"] -impl crate::Readable for Sm1captfiltxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1captfiltx::W`](W) writer structure"] -impl crate::Writable for Sm1captfiltxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1CAPTFILTX to value 0"] -impl crate::Resettable for Sm1captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cnt.rs b/mcxa276-pac/src/flexpwm0/sm1cnt.rs deleted file mode 100644 index 356cc2e91..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1cnt.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM1CNT` reader"] -pub type R = crate::R; -#[doc = "Field `CNT` reader - Counter Register Bits"] -pub type CntR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Counter Register Bits"] - #[inline(always)] - pub fn cnt(&self) -> CntR { - CntR::new(self.bits) - } -} -#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1cntSpec; -impl crate::RegisterSpec for Sm1cntSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1cnt::R`](R) reader structure"] -impl crate::Readable for Sm1cntSpec {} -#[doc = "`reset()` method sets SM1CNT to value 0"] -impl crate::Resettable for Sm1cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1ctrl.rs b/mcxa276-pac/src/flexpwm0/sm1ctrl.rs deleted file mode 100644 index c4871e038..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1ctrl.rs +++ /dev/null @@ -1,871 +0,0 @@ -#[doc = "Register `SM1CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM1CTRL` writer"] -pub type W = crate::W; -#[doc = "Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblen { - #[doc = "0: Double switching disabled."] - Disabled = 0, - #[doc = "1: Double switching enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLEN` reader - Double Switching Enable"] -pub type DblenR = crate::BitReader; -impl DblenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblen { - match self.bits { - false => Dblen::Disabled, - true => Dblen::Enabled, - } - } - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblen::Disabled - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblen::Enabled - } -} -#[doc = "Field `DBLEN` writer - Double Switching Enable"] -pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; -impl<'a, REG> DblenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblen::Disabled) - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblen::Enabled) - } -} -#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblx { - #[doc = "0: PWM_X double pulse disabled."] - Disabled = 0, - #[doc = "1: PWM_X double pulse enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] -pub type DblxR = crate::BitReader; -impl DblxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblx { - match self.bits { - false => Dblx::Disabled, - true => Dblx::Enabled, - } - } - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblx::Disabled - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblx::Enabled - } -} -#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] -pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; -impl<'a, REG> DblxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblx::Disabled) - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblx::Enabled) - } -} -#[doc = "Load Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldmod { - #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - NextPwmReload = 0, - #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - MtctrlLdokSet = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldmod) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDMOD` reader - Load Mode Select"] -pub type LdmodR = crate::BitReader; -impl LdmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldmod { - match self.bits { - false => Ldmod::NextPwmReload, - true => Ldmod::MtctrlLdokSet, - } - } - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn is_next_pwm_reload(&self) -> bool { - *self == Ldmod::NextPwmReload - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn is_mtctrl_ldok_set(&self) -> bool { - *self == Ldmod::MtctrlLdokSet - } -} -#[doc = "Field `LDMOD` writer - Load Mode Select"] -pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; -impl<'a, REG> LdmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn next_pwm_reload(self) -> &'a mut crate::W { - self.variant(Ldmod::NextPwmReload) - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { - self.variant(Ldmod::MtctrlLdokSet) - } -} -#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Split { - #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - Disabled = 0, - #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Split) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitR = crate::BitReader; -impl SplitR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Split { - match self.bits { - false => Split::Disabled, - true => Split::Enabled, - } - } - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Split::Disabled - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Split::Enabled - } -} -#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; -impl<'a, REG> SplitW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Split::Disabled) - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Split::Enabled) - } -} -#[doc = "Prescaler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Prsc { - #[doc = "0: Prescaler 1"] - One = 0, - #[doc = "1: Prescaler 2"] - Two = 1, - #[doc = "2: Prescaler 4"] - Four = 2, - #[doc = "3: Prescaler 8"] - Eight = 3, - #[doc = "4: Prescaler 16"] - Sixteen = 4, - #[doc = "5: Prescaler 32"] - Thirtytwo = 5, - #[doc = "6: Prescaler 64"] - Sixtyfour = 6, - #[doc = "7: Prescaler 128"] - Hundredtwentyeight = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Prsc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Prsc { - type Ux = u8; -} -impl crate::IsEnum for Prsc {} -#[doc = "Field `PRSC` reader - Prescaler"] -pub type PrscR = crate::FieldReader; -impl PrscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prsc { - match self.bits { - 0 => Prsc::One, - 1 => Prsc::Two, - 2 => Prsc::Four, - 3 => Prsc::Eight, - 4 => Prsc::Sixteen, - 5 => Prsc::Thirtytwo, - 6 => Prsc::Sixtyfour, - 7 => Prsc::Hundredtwentyeight, - _ => unreachable!(), - } - } - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Prsc::One - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn is_two(&self) -> bool { - *self == Prsc::Two - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn is_four(&self) -> bool { - *self == Prsc::Four - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn is_eight(&self) -> bool { - *self == Prsc::Eight - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn is_sixteen(&self) -> bool { - *self == Prsc::Sixteen - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn is_thirtytwo(&self) -> bool { - *self == Prsc::Thirtytwo - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn is_sixtyfour(&self) -> bool { - *self == Prsc::Sixtyfour - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn is_hundredtwentyeight(&self) -> bool { - *self == Prsc::Hundredtwentyeight - } -} -#[doc = "Field `PRSC` writer - Prescaler"] -pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; -impl<'a, REG> PrscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn one(self) -> &'a mut crate::W { - self.variant(Prsc::One) - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn two(self) -> &'a mut crate::W { - self.variant(Prsc::Two) - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn four(self) -> &'a mut crate::W { - self.variant(Prsc::Four) - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn eight(self) -> &'a mut crate::W { - self.variant(Prsc::Eight) - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn sixteen(self) -> &'a mut crate::W { - self.variant(Prsc::Sixteen) - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn thirtytwo(self) -> &'a mut crate::W { - self.variant(Prsc::Thirtytwo) - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn sixtyfour(self) -> &'a mut crate::W { - self.variant(Prsc::Sixtyfour) - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn hundredtwentyeight(self) -> &'a mut crate::W { - self.variant(Prsc::Hundredtwentyeight) - } -} -#[doc = "Compare Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Compmode { - #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - EqualTo = 0, - #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - EqualToOrGreaterThan = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Compmode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPMODE` reader - Compare Mode"] -pub type CompmodeR = crate::BitReader; -impl CompmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Compmode { - match self.bits { - false => Compmode::EqualTo, - true => Compmode::EqualToOrGreaterThan, - } - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn is_equal_to(&self) -> bool { - *self == Compmode::EqualTo - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn is_equal_to_or_greater_than(&self) -> bool { - *self == Compmode::EqualToOrGreaterThan - } -} -#[doc = "Field `COMPMODE` writer - Compare Mode"] -pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; -impl<'a, REG> CompmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn equal_to(self) -> &'a mut crate::W { - self.variant(Compmode::EqualTo) - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { - self.variant(Compmode::EqualToOrGreaterThan) - } -} -#[doc = "Field `DT` reader - Deadtime"] -pub type DtR = crate::FieldReader; -#[doc = "Full Cycle Reload\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Full { - #[doc = "0: Full-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Full-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FULL` reader - Full Cycle Reload"] -pub type FullR = crate::BitReader; -impl FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Full { - match self.bits { - false => Full::Disabled, - true => Full::Enabled, - } - } - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Full::Disabled - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Full::Enabled - } -} -#[doc = "Field `FULL` writer - Full Cycle Reload"] -pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; -impl<'a, REG> FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Full::Disabled) - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Full::Enabled) - } -} -#[doc = "Half Cycle Reload\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Half { - #[doc = "0: Half-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Half-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Half) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALF` reader - Half Cycle Reload"] -pub type HalfR = crate::BitReader; -impl HalfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Half { - match self.bits { - false => Half::Disabled, - true => Half::Enabled, - } - } - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Half::Disabled - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Half::Enabled - } -} -#[doc = "Field `HALF` writer - Half Cycle Reload"] -pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; -impl<'a, REG> HalfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Half::Disabled) - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Half::Enabled) - } -} -#[doc = "Load Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ldfq { - #[doc = "0: Every PWM opportunity"] - Everypwm = 0, - #[doc = "1: Every 2 PWM opportunities"] - Every2pwm = 1, - #[doc = "2: Every 3 PWM opportunities"] - Every3pwm = 2, - #[doc = "3: Every 4 PWM opportunities"] - Every4pwm = 3, - #[doc = "4: Every 5 PWM opportunities"] - Every5pwm = 4, - #[doc = "5: Every 6 PWM opportunities"] - Every6pwm = 5, - #[doc = "6: Every 7 PWM opportunities"] - Every7pwm = 6, - #[doc = "7: Every 8 PWM opportunities"] - Every8pwm = 7, - #[doc = "8: Every 9 PWM opportunities"] - Every9pwm = 8, - #[doc = "9: Every 10 PWM opportunities"] - Every10pwm = 9, - #[doc = "10: Every 11 PWM opportunities"] - Every11pwm = 10, - #[doc = "11: Every 12 PWM opportunities"] - Every12pwm = 11, - #[doc = "12: Every 13 PWM opportunities"] - Every13pwm = 12, - #[doc = "13: Every 14 PWM opportunities"] - Every14pwm = 13, - #[doc = "14: Every 15 PWM opportunities"] - Every15pwm = 14, - #[doc = "15: Every 16 PWM opportunities"] - Every16pwm = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ldfq) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ldfq { - type Ux = u8; -} -impl crate::IsEnum for Ldfq {} -#[doc = "Field `LDFQ` reader - Load Frequency"] -pub type LdfqR = crate::FieldReader; -impl LdfqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldfq { - match self.bits { - 0 => Ldfq::Everypwm, - 1 => Ldfq::Every2pwm, - 2 => Ldfq::Every3pwm, - 3 => Ldfq::Every4pwm, - 4 => Ldfq::Every5pwm, - 5 => Ldfq::Every6pwm, - 6 => Ldfq::Every7pwm, - 7 => Ldfq::Every8pwm, - 8 => Ldfq::Every9pwm, - 9 => Ldfq::Every10pwm, - 10 => Ldfq::Every11pwm, - 11 => Ldfq::Every12pwm, - 12 => Ldfq::Every13pwm, - 13 => Ldfq::Every14pwm, - 14 => Ldfq::Every15pwm, - 15 => Ldfq::Every16pwm, - _ => unreachable!(), - } - } - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Ldfq::Everypwm - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn is_every2pwm(&self) -> bool { - *self == Ldfq::Every2pwm - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn is_every3pwm(&self) -> bool { - *self == Ldfq::Every3pwm - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn is_every4pwm(&self) -> bool { - *self == Ldfq::Every4pwm - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn is_every5pwm(&self) -> bool { - *self == Ldfq::Every5pwm - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn is_every6pwm(&self) -> bool { - *self == Ldfq::Every6pwm - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn is_every7pwm(&self) -> bool { - *self == Ldfq::Every7pwm - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn is_every8pwm(&self) -> bool { - *self == Ldfq::Every8pwm - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn is_every9pwm(&self) -> bool { - *self == Ldfq::Every9pwm - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn is_every10pwm(&self) -> bool { - *self == Ldfq::Every10pwm - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn is_every11pwm(&self) -> bool { - *self == Ldfq::Every11pwm - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn is_every12pwm(&self) -> bool { - *self == Ldfq::Every12pwm - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn is_every13pwm(&self) -> bool { - *self == Ldfq::Every13pwm - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn is_every14pwm(&self) -> bool { - *self == Ldfq::Every14pwm - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn is_every15pwm(&self) -> bool { - *self == Ldfq::Every15pwm - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn is_every16pwm(&self) -> bool { - *self == Ldfq::Every16pwm - } -} -#[doc = "Field `LDFQ` writer - Load Frequency"] -pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; -impl<'a, REG> LdfqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Everypwm) - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn every2pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every2pwm) - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn every3pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every3pwm) - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn every4pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every4pwm) - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn every5pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every5pwm) - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn every6pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every6pwm) - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn every7pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every7pwm) - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn every8pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every8pwm) - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn every9pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every9pwm) - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn every10pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every10pwm) - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn every11pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every11pwm) - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn every12pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every12pwm) - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn every13pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every13pwm) - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn every14pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every14pwm) - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn every15pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every15pwm) - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn every16pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every16pwm) - } -} -impl R { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&self) -> DblenR { - DblenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&self) -> DblxR { - DblxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&self) -> LdmodR { - LdmodR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&self) -> SplitR { - SplitR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&self) -> PrscR { - PrscR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&self) -> CompmodeR { - CompmodeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Deadtime"] - #[inline(always)] - pub fn dt(&self) -> DtR { - DtR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&self) -> FullR { - FullR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&self) -> HalfR { - HalfR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&self) -> LdfqR { - LdfqR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&mut self) -> DblenW { - DblenW::new(self, 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&mut self) -> DblxW { - DblxW::new(self, 1) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&mut self) -> LdmodW { - LdmodW::new(self, 2) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&mut self) -> SplitW { - SplitW::new(self, 3) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&mut self) -> PrscW { - PrscW::new(self, 4) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&mut self) -> CompmodeW { - CompmodeW::new(self, 7) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&mut self) -> FullW { - FullW::new(self, 10) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&mut self) -> HalfW { - HalfW::new(self, 11) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&mut self) -> LdfqW { - LdfqW::new(self, 12) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1ctrlSpec; -impl crate::RegisterSpec for Sm1ctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1ctrl::R`](R) reader structure"] -impl crate::Readable for Sm1ctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1ctrl::W`](W) writer structure"] -impl crate::Writable for Sm1ctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1CTRL to value 0x0400"] -impl crate::Resettable for Sm1ctrlSpec { - const RESET_VALUE: u16 = 0x0400; -} diff --git a/mcxa276-pac/src/flexpwm0/sm1ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm1ctrl2.rs deleted file mode 100644 index f3a7ec0fe..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1ctrl2.rs +++ /dev/null @@ -1,607 +0,0 @@ -#[doc = "Register `SM1CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM1CTRL2` writer"] -pub type W = crate::W; -#[doc = "Clock Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ClkSel { - #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] - Ipbus = 0, - #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] - ExtClk = 1, - #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - AuxClk = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ClkSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ClkSel { - type Ux = u8; -} -impl crate::IsEnum for ClkSel {} -#[doc = "Field `CLK_SEL` reader - Clock Source Select"] -pub type ClkSelR = crate::FieldReader; -impl ClkSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(ClkSel::Ipbus), - 1 => Some(ClkSel::ExtClk), - 2 => Some(ClkSel::AuxClk), - _ => None, - } - } - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ipbus(&self) -> bool { - *self == ClkSel::Ipbus - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ext_clk(&self) -> bool { - *self == ClkSel::ExtClk - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn is_aux_clk(&self) -> bool { - *self == ClkSel::AuxClk - } -} -#[doc = "Field `CLK_SEL` writer - Clock Source Select"] -pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; -impl<'a, REG> ClkSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ipbus(self) -> &'a mut crate::W { - self.variant(ClkSel::Ipbus) - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ext_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::ExtClk) - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn aux_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::AuxClk) - } -} -#[doc = "Reload Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ReloadSel { - #[doc = "0: The local RELOAD signal is used to reload registers."] - Local = 0, - #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - Master = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ReloadSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] -pub type ReloadSelR = crate::BitReader; -impl ReloadSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ReloadSel { - match self.bits { - false => ReloadSel::Local, - true => ReloadSel::Master, - } - } - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ReloadSel::Local - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ReloadSel::Master - } -} -#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] -pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; -impl<'a, REG> ReloadSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ReloadSel::Local) - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ReloadSel::Master) - } -} -#[doc = "Force Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ForceSel { - #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - Local = 0, - #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - Master = 1, - #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - LocalReload = 2, - #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterReload = 3, - #[doc = "4: The local sync signal from this submodule is used to force updates."] - LocalSync = 4, - #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterSync = 5, - #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - ExtForce = 6, - #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - ExtSync = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ForceSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ForceSel { - type Ux = u8; -} -impl crate::IsEnum for ForceSel {} -#[doc = "Field `FORCE_SEL` reader - Force Select"] -pub type ForceSelR = crate::FieldReader; -impl ForceSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ForceSel { - match self.bits { - 0 => ForceSel::Local, - 1 => ForceSel::Master, - 2 => ForceSel::LocalReload, - 3 => ForceSel::MasterReload, - 4 => ForceSel::LocalSync, - 5 => ForceSel::MasterSync, - 6 => ForceSel::ExtForce, - 7 => ForceSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ForceSel::Local - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ForceSel::Master - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == ForceSel::LocalReload - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == ForceSel::MasterReload - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == ForceSel::LocalSync - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == ForceSel::MasterSync - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_force(&self) -> bool { - *self == ForceSel::ExtForce - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == ForceSel::ExtSync - } -} -#[doc = "Field `FORCE_SEL` writer - Force Select"] -pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; -impl<'a, REG> ForceSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ForceSel::Local) - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ForceSel::Master) - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalReload) - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterReload) - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalSync) - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterSync) - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_force(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtForce) - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtSync) - } -} -#[doc = "Field `FORCE` reader - Force Initialization"] -pub type ForceR = crate::BitReader; -#[doc = "Field `FORCE` writer - Force Initialization"] -pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Force Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frcen { - #[doc = "0: Initialization from a FORCE_OUT is disabled."] - Disabled = 0, - #[doc = "1: Initialization from a FORCE_OUT is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRCEN` reader - Force Enable"] -pub type FrcenR = crate::BitReader; -impl FrcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frcen { - match self.bits { - false => Frcen::Disabled, - true => Frcen::Enabled, - } - } - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Frcen::Disabled - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Frcen::Enabled - } -} -#[doc = "Field `FRCEN` writer - Force Enable"] -pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; -impl<'a, REG> FrcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Frcen::Disabled) - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Frcen::Enabled) - } -} -#[doc = "Initialization Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum InitSel { - #[doc = "0: Local sync (PWM_X) causes initialization."] - PwmX = 0, - #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - MasterReload = 1, - #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - MasterSync = 2, - #[doc = "3: EXT_SYNC causes initialization."] - ExtSync = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: InitSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for InitSel { - type Ux = u8; -} -impl crate::IsEnum for InitSel {} -#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] -pub type InitSelR = crate::FieldReader; -impl InitSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InitSel { - match self.bits { - 0 => InitSel::PwmX, - 1 => InitSel::MasterReload, - 2 => InitSel::MasterSync, - 3 => InitSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InitSel::PwmX - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == InitSel::MasterReload - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == InitSel::MasterSync - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == InitSel::ExtSync - } -} -#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] -pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; -impl<'a, REG> InitSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InitSel::PwmX) - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(InitSel::MasterReload) - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(InitSel::MasterSync) - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(InitSel::ExtSync) - } -} -#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] -pub type PwmxInitR = crate::BitReader; -#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] -pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] -pub type Pwm45InitR = crate::BitReader; -#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] -pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] -pub type Pwm23InitR = crate::BitReader; -#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] -pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Indep { - #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] - Complementary = 0, - #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] - Independent = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Indep) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] -pub type IndepR = crate::BitReader; -impl IndepR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Indep { - match self.bits { - false => Indep::Complementary, - true => Indep::Independent, - } - } - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn is_complementary(&self) -> bool { - *self == Indep::Complementary - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn is_independent(&self) -> bool { - *self == Indep::Independent - } -} -#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] -pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; -impl<'a, REG> IndepW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn complementary(self) -> &'a mut crate::W { - self.variant(Indep::Complementary) - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn independent(self) -> &'a mut crate::W { - self.variant(Indep::Independent) - } -} -#[doc = "Field `DBGEN` reader - Debug Enable"] -pub type DbgenR = crate::BitReader; -#[doc = "Field `DBGEN` writer - Debug Enable"] -pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&self) -> ClkSelR { - ClkSelR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&self) -> ReloadSelR { - ReloadSelR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&self) -> ForceSelR { - ForceSelR::new(((self.bits >> 3) & 7) as u8) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&self) -> ForceR { - ForceR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&self) -> FrcenR { - FrcenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&self) -> InitSelR { - InitSelR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&self) -> PwmxInitR { - PwmxInitR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&self) -> Pwm45InitR { - Pwm45InitR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&self) -> Pwm23InitR { - Pwm23InitR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&self) -> IndepR { - IndepR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&self) -> DbgenR { - DbgenR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&mut self) -> ClkSelW { - ClkSelW::new(self, 0) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&mut self) -> ReloadSelW { - ReloadSelW::new(self, 2) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&mut self) -> ForceSelW { - ForceSelW::new(self, 3) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&mut self) -> ForceW { - ForceW::new(self, 6) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&mut self) -> FrcenW { - FrcenW::new(self, 7) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&mut self) -> InitSelW { - InitSelW::new(self, 8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&mut self) -> PwmxInitW { - PwmxInitW::new(self, 10) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&mut self) -> Pwm45InitW { - Pwm45InitW::new(self, 11) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&mut self) -> Pwm23InitW { - Pwm23InitW::new(self, 12) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&mut self) -> IndepW { - IndepW::new(self, 13) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&mut self) -> DbgenW { - DbgenW::new(self, 15) - } -} -#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1ctrl2Spec; -impl crate::RegisterSpec for Sm1ctrl2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1ctrl2::R`](R) reader structure"] -impl crate::Readable for Sm1ctrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1ctrl2::W`](W) writer structure"] -impl crate::Writable for Sm1ctrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1CTRL2 to value 0"] -impl crate::Resettable for Sm1ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval0.rs b/mcxa276-pac/src/flexpwm0/sm1cval0.rs deleted file mode 100644 index fff0002f4..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1cval0.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM1CVAL0` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] -pub type Captval0R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 0"] - #[inline(always)] - pub fn captval0(&self) -> Captval0R { - Captval0R::new(self.bits) - } -} -#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1cval0Spec; -impl crate::RegisterSpec for Sm1cval0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1cval0::R`](R) reader structure"] -impl crate::Readable for Sm1cval0Spec {} -#[doc = "`reset()` method sets SM1CVAL0 to value 0"] -impl crate::Resettable for Sm1cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs deleted file mode 100644 index 4189165fe..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1cval0cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM1CVAL0CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] -pub type Cval0cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 0 Cycle"] - #[inline(always)] - pub fn cval0cyc(&self) -> Cval0cycR { - Cval0cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1cval0cycSpec; -impl crate::RegisterSpec for Sm1cval0cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1cval0cyc::R`](R) reader structure"] -impl crate::Readable for Sm1cval0cycSpec {} -#[doc = "`reset()` method sets SM1CVAL0CYC to value 0"] -impl crate::Resettable for Sm1cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval1.rs b/mcxa276-pac/src/flexpwm0/sm1cval1.rs deleted file mode 100644 index 9b04841aa..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1cval1.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM1CVAL1` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] -pub type Captval1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 1"] - #[inline(always)] - pub fn captval1(&self) -> Captval1R { - Captval1R::new(self.bits) - } -} -#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1cval1Spec; -impl crate::RegisterSpec for Sm1cval1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1cval1::R`](R) reader structure"] -impl crate::Readable for Sm1cval1Spec {} -#[doc = "`reset()` method sets SM1CVAL1 to value 0"] -impl crate::Resettable for Sm1cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs deleted file mode 100644 index 7127a47c1..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1cval1cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM1CVAL1CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] -pub type Cval1cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 1 Cycle"] - #[inline(always)] - pub fn cval1cyc(&self) -> Cval1cycR { - Cval1cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1cval1cycSpec; -impl crate::RegisterSpec for Sm1cval1cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1cval1cyc::R`](R) reader structure"] -impl crate::Readable for Sm1cval1cycSpec {} -#[doc = "`reset()` method sets SM1CVAL1CYC to value 0"] -impl crate::Resettable for Sm1cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1dismap0.rs b/mcxa276-pac/src/flexpwm0/sm1dismap0.rs deleted file mode 100644 index cf2fa86f5..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1dismap0.rs +++ /dev/null @@ -1,65 +0,0 @@ -#[doc = "Register `SM1DISMAP0` reader"] -pub type R = crate::R; -#[doc = "Register `SM1DISMAP0` writer"] -pub type W = crate::W; -#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] -pub type Dis0aR = crate::FieldReader; -#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] -pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] -pub type Dis0bR = crate::FieldReader; -#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] -pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] -pub type Dis0xR = crate::FieldReader; -#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] -pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&self) -> Dis0aR { - Dis0aR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&self) -> Dis0bR { - Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&self) -> Dis0xR { - Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&mut self) -> Dis0aW { - Dis0aW::new(self, 0) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&mut self) -> Dis0bW { - Dis0bW::new(self, 4) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&mut self) -> Dis0xW { - Dis0xW::new(self, 8) - } -} -#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1dismap0Spec; -impl crate::RegisterSpec for Sm1dismap0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1dismap0::R`](R) reader structure"] -impl crate::Readable for Sm1dismap0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1dismap0::W`](W) writer structure"] -impl crate::Writable for Sm1dismap0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1DISMAP0 to value 0xffff"] -impl crate::Resettable for Sm1dismap0Spec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm1dmaen.rs b/mcxa276-pac/src/flexpwm0/sm1dmaen.rs deleted file mode 100644 index 7d907159e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1dmaen.rs +++ /dev/null @@ -1,271 +0,0 @@ -#[doc = "Register `SM1DMAEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM1DMAEN` writer"] -pub type W = crate::W; -#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] -pub type Cx0deR = crate::BitReader; -#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] -pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] -pub type Cx1deR = crate::BitReader; -#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] -pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Captde { - #[doc = "0: Read DMA requests disabled."] - Disabled = 0, - #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - Exceedfifo = 1, - #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] - LocalSync = 2, - #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] - LocalReload = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Captde) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Captde { - type Ux = u8; -} -impl crate::IsEnum for Captde {} -#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] -pub type CaptdeR = crate::FieldReader; -impl CaptdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Captde { - match self.bits { - 0 => Captde::Disabled, - 1 => Captde::Exceedfifo, - 2 => Captde::LocalSync, - 3 => Captde::LocalReload, - _ => unreachable!(), - } - } - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Captde::Disabled - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn is_exceedfifo(&self) -> bool { - *self == Captde::Exceedfifo - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == Captde::LocalSync - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == Captde::LocalReload - } -} -#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] -pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; -impl<'a, REG> CaptdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Captde::Disabled) - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn exceedfifo(self) -> &'a mut crate::W { - self.variant(Captde::Exceedfifo) - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(Captde::LocalSync) - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(Captde::LocalReload) - } -} -#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fand { - #[doc = "0: Selected FIFO watermarks are OR'ed together."] - Or = 0, - #[doc = "1: Selected FIFO watermarks are AND'ed together."] - And = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fand) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] -pub type FandR = crate::BitReader; -impl FandR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fand { - match self.bits { - false => Fand::Or, - true => Fand::And, - } - } - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn is_or(&self) -> bool { - *self == Fand::Or - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn is_and(&self) -> bool { - *self == Fand::And - } -} -#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] -pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; -impl<'a, REG> FandW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn or(self) -> &'a mut crate::W { - self.variant(Fand::Or) - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn and(self) -> &'a mut crate::W { - self.variant(Fand::And) - } -} -#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Valde { - #[doc = "0: DMA write requests disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Valde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] -pub type ValdeR = crate::BitReader; -impl ValdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Valde { - match self.bits { - false => Valde::Disabled, - true => Valde::Enabled, - } - } - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Valde::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Valde::Enabled - } -} -#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] -pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; -impl<'a, REG> ValdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Valde::Disabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Valde::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&self) -> Cx0deR { - Cx0deR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&self) -> Cx1deR { - Cx1deR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&self) -> CaptdeR { - CaptdeR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&self) -> FandR { - FandR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&self) -> ValdeR { - ValdeR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&mut self) -> Cx0deW { - Cx0deW::new(self, 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&mut self) -> Cx1deW { - Cx1deW::new(self, 1) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&mut self) -> CaptdeW { - CaptdeW::new(self, 6) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&mut self) -> FandW { - FandW::new(self, 8) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&mut self) -> ValdeW { - ValdeW::new(self, 9) - } -} -#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1dmaenSpec; -impl crate::RegisterSpec for Sm1dmaenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1dmaen::R`](R) reader structure"] -impl crate::Readable for Sm1dmaenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1dmaen::W`](W) writer structure"] -impl crate::Writable for Sm1dmaenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1DMAEN to value 0"] -impl crate::Resettable for Sm1dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs deleted file mode 100644 index 79641844e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1dtcnt0.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM1DTCNT0` reader"] -pub type R = crate::R; -#[doc = "Register `SM1DTCNT0` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] -pub type Dtcnt0R = crate::FieldReader; -#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] -pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&self) -> Dtcnt0R { - Dtcnt0R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&mut self) -> Dtcnt0W { - Dtcnt0W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1dtcnt0Spec; -impl crate::RegisterSpec for Sm1dtcnt0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1dtcnt0::R`](R) reader structure"] -impl crate::Readable for Sm1dtcnt0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1dtcnt0::W`](W) writer structure"] -impl crate::Writable for Sm1dtcnt0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1DTCNT0 to value 0x07ff"] -impl crate::Resettable for Sm1dtcnt0Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs deleted file mode 100644 index 6c4da6a1e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1dtcnt1.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM1DTCNT1` reader"] -pub type R = crate::R; -#[doc = "Register `SM1DTCNT1` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] -pub type Dtcnt1R = crate::FieldReader; -#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] -pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&self) -> Dtcnt1R { - Dtcnt1R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&mut self) -> Dtcnt1W { - Dtcnt1W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1dtcnt1Spec; -impl crate::RegisterSpec for Sm1dtcnt1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1dtcnt1::R`](R) reader structure"] -impl crate::Readable for Sm1dtcnt1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1dtcnt1::W`](W) writer structure"] -impl crate::Writable for Sm1dtcnt1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1DTCNT1 to value 0x07ff"] -impl crate::Resettable for Sm1dtcnt1Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm1init.rs b/mcxa276-pac/src/flexpwm0/sm1init.rs deleted file mode 100644 index 7aa2d506e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1init.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1INIT` reader"] -pub type R = crate::R; -#[doc = "Register `SM1INIT` writer"] -pub type W = crate::W; -#[doc = "Field `INIT` reader - Initial Count Register Bits"] -pub type InitR = crate::FieldReader; -#[doc = "Field `INIT` writer - Initial Count Register Bits"] -pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&self) -> InitR { - InitR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&mut self) -> InitW { - InitW::new(self, 0) - } -} -#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1initSpec; -impl crate::RegisterSpec for Sm1initSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1init::R`](R) reader structure"] -impl crate::Readable for Sm1initSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1init::W`](W) writer structure"] -impl crate::Writable for Sm1initSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1INIT to value 0"] -impl crate::Resettable for Sm1initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1inten.rs b/mcxa276-pac/src/flexpwm0/sm1inten.rs deleted file mode 100644 index 3ede52ad7..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1inten.rs +++ /dev/null @@ -1,343 +0,0 @@ -#[doc = "Register `SM1INTEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM1INTEN` writer"] -pub type W = crate::W; -#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpie { - #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - Disabled = 0, - #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - Enabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpie) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpie { - type Ux = u8; -} -impl crate::IsEnum for Cmpie {} -#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] -pub type CmpieR = crate::FieldReader; -impl CmpieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpie::Disabled), - 1 => Some(Cmpie::Enabled), - _ => None, - } - } - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmpie::Disabled - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmpie::Enabled - } -} -#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] -pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; -impl<'a, REG> CmpieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Disabled) - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Enabled) - } -} -#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx0ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx0ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] -pub type Cx0ieR = crate::BitReader; -impl Cx0ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx0ie { - match self.bits { - false => Cx0ie::Disabled, - true => Cx0ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx0ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx0ie::Enabled - } -} -#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] -pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; -impl<'a, REG> Cx0ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Enabled) - } -} -#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx1ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx1ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] -pub type Cx1ieR = crate::BitReader; -impl Cx1ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx1ie { - match self.bits { - false => Cx1ie::Disabled, - true => Cx1ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx1ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx1ie::Enabled - } -} -#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] -pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; -impl<'a, REG> Cx1ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Enabled) - } -} -#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rie { - #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RIE` reader - Reload Interrupt Enable"] -pub type RieR = crate::BitReader; -impl RieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rie { - match self.bits { - false => Rie::Disabled, - true => Rie::Enabled, - } - } - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rie::Disabled - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rie::Enabled - } -} -#[doc = "Field `RIE` writer - Reload Interrupt Enable"] -pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; -impl<'a, REG> RieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rie::Disabled) - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rie::Enabled) - } -} -#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reie { - #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] -pub type ReieR = crate::BitReader; -impl ReieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reie { - match self.bits { - false => Reie::Disabled, - true => Reie::Enabled, - } - } - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Reie::Disabled - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Reie::Enabled - } -} -#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] -pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; -impl<'a, REG> ReieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Reie::Disabled) - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Reie::Enabled) - } -} -impl R { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&self) -> CmpieR { - CmpieR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&self) -> Cx0ieR { - Cx0ieR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&self) -> Cx1ieR { - Cx1ieR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&self) -> RieR { - RieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&self) -> ReieR { - ReieR::new(((self.bits >> 13) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&mut self) -> CmpieW { - CmpieW::new(self, 0) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&mut self) -> Cx0ieW { - Cx0ieW::new(self, 6) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&mut self) -> Cx1ieW { - Cx1ieW::new(self, 7) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&mut self) -> RieW { - RieW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&mut self) -> ReieW { - ReieW::new(self, 13) - } -} -#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1intenSpec; -impl crate::RegisterSpec for Sm1intenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1inten::R`](R) reader structure"] -impl crate::Readable for Sm1intenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1inten::W`](W) writer structure"] -impl crate::Writable for Sm1intenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1INTEN to value 0"] -impl crate::Resettable for Sm1intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1octrl.rs b/mcxa276-pac/src/flexpwm0/sm1octrl.rs deleted file mode 100644 index a5f6c4d2c..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1octrl.rs +++ /dev/null @@ -1,519 +0,0 @@ -#[doc = "Register `SM1OCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM1OCTRL` writer"] -pub type W = crate::W; -#[doc = "PWM_X Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmxfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmxfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmxfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmxfs {} -#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] -pub type PwmxfsR = crate::FieldReader; -impl PwmxfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmxfs { - match self.bits { - 0 => Pwmxfs::Logic0, - 1 => Pwmxfs::Logic1, - 2 => Pwmxfs::Tristated2, - 3 => Pwmxfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmxfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmxfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmxfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmxfs::Tristated3 - } -} -#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] -pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; -impl<'a, REG> PwmxfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated3) - } -} -#[doc = "PWM_B Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmbfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmbfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmbfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmbfs {} -#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] -pub type PwmbfsR = crate::FieldReader; -impl PwmbfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmbfs { - match self.bits { - 0 => Pwmbfs::Logic0, - 1 => Pwmbfs::Logic1, - 2 => Pwmbfs::Tristated2, - 3 => Pwmbfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmbfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmbfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmbfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmbfs::Tristated3 - } -} -#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] -pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; -impl<'a, REG> PwmbfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated3) - } -} -#[doc = "PWM_A Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmafs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmafs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmafs { - type Ux = u8; -} -impl crate::IsEnum for Pwmafs {} -#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] -pub type PwmafsR = crate::FieldReader; -impl PwmafsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmafs { - match self.bits { - 0 => Pwmafs::Logic0, - 1 => Pwmafs::Logic1, - 2 => Pwmafs::Tristated2, - 3 => Pwmafs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmafs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmafs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmafs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmafs::Tristated3 - } -} -#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] -pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; -impl<'a, REG> PwmafsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated3) - } -} -#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polx { - #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLX` reader - PWM_X Output Polarity"] -pub type PolxR = crate::BitReader; -impl PolxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polx { - match self.bits { - false => Polx::NotInverted, - true => Polx::Inverted, - } - } - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polx::NotInverted - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polx::Inverted - } -} -#[doc = "Field `POLX` writer - PWM_X Output Polarity"] -pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; -impl<'a, REG> PolxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polx::NotInverted) - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polx::Inverted) - } -} -#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polb { - #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLB` reader - PWM_B Output Polarity"] -pub type PolbR = crate::BitReader; -impl PolbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polb { - match self.bits { - false => Polb::NotInverted, - true => Polb::Inverted, - } - } - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polb::NotInverted - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polb::Inverted - } -} -#[doc = "Field `POLB` writer - PWM_B Output Polarity"] -pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; -impl<'a, REG> PolbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polb::NotInverted) - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polb::Inverted) - } -} -#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pola { - #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pola) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLA` reader - PWM_A Output Polarity"] -pub type PolaR = crate::BitReader; -impl PolaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pola { - match self.bits { - false => Pola::NotInverted, - true => Pola::Inverted, - } - } - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Pola::NotInverted - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Pola::Inverted - } -} -#[doc = "Field `POLA` writer - PWM_A Output Polarity"] -pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; -impl<'a, REG> PolaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Pola::NotInverted) - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Pola::Inverted) - } -} -#[doc = "Field `PWMX_IN` reader - PWM_X Input"] -pub type PwmxInR = crate::BitReader; -#[doc = "Field `PWMB_IN` reader - PWM_B Input"] -pub type PwmbInR = crate::BitReader; -#[doc = "Field `PWMA_IN` reader - PWM_A Input"] -pub type PwmaInR = crate::BitReader; -impl R { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&self) -> PwmxfsR { - PwmxfsR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&self) -> PwmbfsR { - PwmbfsR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&self) -> PwmafsR { - PwmafsR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&self) -> PolxR { - PolxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&self) -> PolbR { - PolbR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&self) -> PolaR { - PolaR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 13 - PWM_X Input"] - #[inline(always)] - pub fn pwmx_in(&self) -> PwmxInR { - PwmxInR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - PWM_B Input"] - #[inline(always)] - pub fn pwmb_in(&self) -> PwmbInR { - PwmbInR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - PWM_A Input"] - #[inline(always)] - pub fn pwma_in(&self) -> PwmaInR { - PwmaInR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&mut self) -> PwmxfsW { - PwmxfsW::new(self, 0) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&mut self) -> PwmbfsW { - PwmbfsW::new(self, 2) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&mut self) -> PwmafsW { - PwmafsW::new(self, 4) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&mut self) -> PolxW { - PolxW::new(self, 8) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&mut self) -> PolbW { - PolbW::new(self, 9) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&mut self) -> PolaW { - PolaW::new(self, 10) - } -} -#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1octrlSpec; -impl crate::RegisterSpec for Sm1octrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1octrl::R`](R) reader structure"] -impl crate::Readable for Sm1octrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1octrl::W`](W) writer structure"] -impl crate::Writable for Sm1octrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1OCTRL to value 0"] -impl crate::Resettable for Sm1octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1phasedly.rs b/mcxa276-pac/src/flexpwm0/sm1phasedly.rs deleted file mode 100644 index a12b72dc8..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1phasedly.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1PHASEDLY` reader"] -pub type R = crate::R; -#[doc = "Register `SM1PHASEDLY` writer"] -pub type W = crate::W; -#[doc = "Field `PHASEDLY` reader - Initial Count Register Bits"] -pub type PhasedlyR = crate::FieldReader; -#[doc = "Field `PHASEDLY` writer - Initial Count Register Bits"] -pub type PhasedlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn phasedly(&self) -> PhasedlyR { - PhasedlyR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn phasedly(&mut self) -> PhasedlyW { - PhasedlyW::new(self, 0) - } -} -#[doc = "Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1phasedly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1phasedly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1phasedlySpec; -impl crate::RegisterSpec for Sm1phasedlySpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1phasedly::R`](R) reader structure"] -impl crate::Readable for Sm1phasedlySpec {} -#[doc = "`write(|w| ..)` method takes [`sm1phasedly::W`](W) writer structure"] -impl crate::Writable for Sm1phasedlySpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1PHASEDLY to value 0"] -impl crate::Resettable for Sm1phasedlySpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1sts.rs b/mcxa276-pac/src/flexpwm0/sm1sts.rs deleted file mode 100644 index f3d7abadd..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1sts.rs +++ /dev/null @@ -1,287 +0,0 @@ -#[doc = "Register `SM1STS` reader"] -pub type R = crate::R; -#[doc = "Register `SM1STS` writer"] -pub type W = crate::W; -#[doc = "Compare Flags\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpf { - #[doc = "0: No compare event has occurred for a particular VALx value."] - NoEvent = 0, - #[doc = "1: A compare event has occurred for a particular VALx value."] - Event = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpf { - type Ux = u8; -} -impl crate::IsEnum for Cmpf {} -#[doc = "Field `CMPF` reader - Compare Flags"] -pub type CmpfR = crate::FieldReader; -impl CmpfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpf::NoEvent), - 1 => Some(Cmpf::Event), - _ => None, - } - } - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_no_event(&self) -> bool { - *self == Cmpf::NoEvent - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_event(&self) -> bool { - *self == Cmpf::Event - } -} -#[doc = "Field `CMPF` writer - Compare Flags"] -pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; -impl<'a, REG> CmpfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn no_event(self) -> &'a mut crate::W { - self.variant(Cmpf::NoEvent) - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn event(self) -> &'a mut crate::W { - self.variant(Cmpf::Event) - } -} -#[doc = "Field `CFX0` reader - Capture Flag X0"] -pub type Cfx0R = crate::BitReader; -#[doc = "Field `CFX0` writer - Capture Flag X0"] -pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `CFX1` reader - Capture Flag X1"] -pub type Cfx1R = crate::BitReader; -#[doc = "Field `CFX1` writer - Capture Flag X1"] -pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Reload Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rf { - #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] - NoFlag = 0, - #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RF` reader - Reload Flag"] -pub type RfR = crate::BitReader; -impl RfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rf { - match self.bits { - false => Rf::NoFlag, - true => Rf::Flag, - } - } - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Rf::NoFlag - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Rf::Flag - } -} -#[doc = "Field `RF` writer - Reload Flag"] -pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; -impl<'a, REG> RfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Rf::NoFlag) - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Rf::Flag) - } -} -#[doc = "Reload Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ref { - #[doc = "0: No reload error occurred."] - NoFlag = 0, - #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ref) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REF` reader - Reload Error Flag"] -pub type RefR = crate::BitReader; -impl RefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ref { - match self.bits { - false => Ref::NoFlag, - true => Ref::Flag, - } - } - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ref::NoFlag - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ref::Flag - } -} -#[doc = "Field `REF` writer - Reload Error Flag"] -pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; -impl<'a, REG> RefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Ref::NoFlag) - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Ref::Flag) - } -} -#[doc = "Registers Updated Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ruf { - #[doc = "0: No register update has occurred since last reload."] - NoFlag = 0, - #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ruf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RUF` reader - Registers Updated Flag"] -pub type RufR = crate::BitReader; -impl RufR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ruf { - match self.bits { - false => Ruf::NoFlag, - true => Ruf::Flag, - } - } - #[doc = "No register update has occurred since last reload."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ruf::NoFlag - } - #[doc = "At least one of the double buffered registers has been updated since the last reload."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ruf::Flag - } -} -impl R { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&self) -> CmpfR { - CmpfR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&self) -> Cfx0R { - Cfx0R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&self) -> Cfx1R { - Cfx1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&self) -> RfR { - RfR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&self) -> RefR { - RefR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Registers Updated Flag"] - #[inline(always)] - pub fn ruf(&self) -> RufR { - RufR::new(((self.bits >> 14) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&mut self) -> CmpfW { - CmpfW::new(self, 0) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&mut self) -> Cfx0W { - Cfx0W::new(self, 6) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&mut self) -> Cfx1W { - Cfx1W::new(self, 7) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&mut self) -> RfW { - RfW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&mut self) -> RefW { - RefW::new(self, 13) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1stsSpec; -impl crate::RegisterSpec for Sm1stsSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1sts::R`](R) reader structure"] -impl crate::Readable for Sm1stsSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1sts::W`](W) writer structure"] -impl crate::Writable for Sm1stsSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; -} -#[doc = "`reset()` method sets SM1STS to value 0"] -impl crate::Resettable for Sm1stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1tctrl.rs b/mcxa276-pac/src/flexpwm0/sm1tctrl.rs deleted file mode 100644 index d7771b5ab..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1tctrl.rs +++ /dev/null @@ -1,267 +0,0 @@ -#[doc = "Register `SM1TCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM1TCTRL` writer"] -pub type W = crate::W; -#[doc = "Output Trigger Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OutTrigEn { - #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - Val0 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OutTrigEn) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OutTrigEn { - type Ux = u8; -} -impl crate::IsEnum for OutTrigEn {} -#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] -pub type OutTrigEnR = crate::FieldReader; -impl OutTrigEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(OutTrigEn::Val0), - _ => None, - } - } - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == OutTrigEn::Val0 - } -} -#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] -pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; -impl<'a, REG> OutTrigEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn val0(self) -> &'a mut crate::W { - self.variant(OutTrigEn::Val0) - } -} -#[doc = "Trigger Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trgfrq { - #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Everypwm = 0, - #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Finalpwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trgfrq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] -pub type TrgfrqR = crate::BitReader; -impl TrgfrqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgfrq { - match self.bits { - false => Trgfrq::Everypwm, - true => Trgfrq::Finalpwm, - } - } - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Trgfrq::Everypwm - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_finalpwm(&self) -> bool { - *self == Trgfrq::Finalpwm - } -} -#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] -pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; -impl<'a, REG> TrgfrqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Everypwm) - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn finalpwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Finalpwm) - } -} -#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwbot1 { - #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - PwmOutTrig1Signal = 0, - #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] - PwmbOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwbot1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] -pub type Pwbot1R = crate::BitReader; -impl Pwbot1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwbot1 { - match self.bits { - false => Pwbot1::PwmOutTrig1Signal, - true => Pwbot1::PwmbOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwm_out_trig1_signal(&self) -> bool { - *self == Pwbot1::PwmOutTrig1Signal - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwmb_output(&self) -> bool { - *self == Pwbot1::PwmbOutput - } -} -#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] -pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; -impl<'a, REG> Pwbot1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmOutTrig1Signal) - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwmb_output(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmbOutput) - } -} -#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwaot0 { - #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - PwmOutTrig0Signal = 0, - #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] - PwmaOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwaot0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] -pub type Pwaot0R = crate::BitReader; -impl Pwaot0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwaot0 { - match self.bits { - false => Pwaot0::PwmOutTrig0Signal, - true => Pwaot0::PwmaOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwm_out_trig0_signal(&self) -> bool { - *self == Pwaot0::PwmOutTrig0Signal - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwma_output(&self) -> bool { - *self == Pwaot0::PwmaOutput - } -} -#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] -pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; -impl<'a, REG> Pwaot0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmOutTrig0Signal) - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwma_output(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmaOutput) - } -} -impl R { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&self) -> OutTrigEnR { - OutTrigEnR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&self) -> TrgfrqR { - TrgfrqR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&self) -> Pwbot1R { - Pwbot1R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&self) -> Pwaot0R { - Pwaot0R::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&mut self) -> OutTrigEnW { - OutTrigEnW::new(self, 0) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&mut self) -> TrgfrqW { - TrgfrqW::new(self, 12) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&mut self) -> Pwbot1W { - Pwbot1W::new(self, 14) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&mut self) -> Pwaot0W { - Pwaot0W::new(self, 15) - } -} -#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1tctrlSpec; -impl crate::RegisterSpec for Sm1tctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1tctrl::R`](R) reader structure"] -impl crate::Readable for Sm1tctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm1tctrl::W`](W) writer structure"] -impl crate::Writable for Sm1tctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1TCTRL to value 0"] -impl crate::Resettable for Sm1tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val0.rs b/mcxa276-pac/src/flexpwm0/sm1val0.rs deleted file mode 100644 index 4ac06c756..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1val0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1VAL0` reader"] -pub type R = crate::R; -#[doc = "Register `SM1VAL0` writer"] -pub type W = crate::W; -#[doc = "Field `VAL0` reader - Value 0"] -pub type Val0R = crate::FieldReader; -#[doc = "Field `VAL0` writer - Value 0"] -pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&self) -> Val0R { - Val0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&mut self) -> Val0W { - Val0W::new(self, 0) - } -} -#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1val0Spec; -impl crate::RegisterSpec for Sm1val0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1val0::R`](R) reader structure"] -impl crate::Readable for Sm1val0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1val0::W`](W) writer structure"] -impl crate::Writable for Sm1val0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1VAL0 to value 0"] -impl crate::Resettable for Sm1val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val1.rs b/mcxa276-pac/src/flexpwm0/sm1val1.rs deleted file mode 100644 index 9450fd208..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1val1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1VAL1` reader"] -pub type R = crate::R; -#[doc = "Register `SM1VAL1` writer"] -pub type W = crate::W; -#[doc = "Field `VAL1` reader - Value 1"] -pub type Val1R = crate::FieldReader; -#[doc = "Field `VAL1` writer - Value 1"] -pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&self) -> Val1R { - Val1R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&mut self) -> Val1W { - Val1W::new(self, 0) - } -} -#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1val1Spec; -impl crate::RegisterSpec for Sm1val1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1val1::R`](R) reader structure"] -impl crate::Readable for Sm1val1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1val1::W`](W) writer structure"] -impl crate::Writable for Sm1val1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1VAL1 to value 0"] -impl crate::Resettable for Sm1val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val2.rs b/mcxa276-pac/src/flexpwm0/sm1val2.rs deleted file mode 100644 index f25eef07e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1val2.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1VAL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM1VAL2` writer"] -pub type W = crate::W; -#[doc = "Field `VAL2` reader - Value 2"] -pub type Val2R = crate::FieldReader; -#[doc = "Field `VAL2` writer - Value 2"] -pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&self) -> Val2R { - Val2R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&mut self) -> Val2W { - Val2W::new(self, 0) - } -} -#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1val2Spec; -impl crate::RegisterSpec for Sm1val2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1val2::R`](R) reader structure"] -impl crate::Readable for Sm1val2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1val2::W`](W) writer structure"] -impl crate::Writable for Sm1val2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1VAL2 to value 0"] -impl crate::Resettable for Sm1val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val3.rs b/mcxa276-pac/src/flexpwm0/sm1val3.rs deleted file mode 100644 index fb3238584..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1val3.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1VAL3` reader"] -pub type R = crate::R; -#[doc = "Register `SM1VAL3` writer"] -pub type W = crate::W; -#[doc = "Field `VAL3` reader - Value 3"] -pub type Val3R = crate::FieldReader; -#[doc = "Field `VAL3` writer - Value 3"] -pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&self) -> Val3R { - Val3R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&mut self) -> Val3W { - Val3W::new(self, 0) - } -} -#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1val3Spec; -impl crate::RegisterSpec for Sm1val3Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1val3::R`](R) reader structure"] -impl crate::Readable for Sm1val3Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1val3::W`](W) writer structure"] -impl crate::Writable for Sm1val3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1VAL3 to value 0"] -impl crate::Resettable for Sm1val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val4.rs b/mcxa276-pac/src/flexpwm0/sm1val4.rs deleted file mode 100644 index 17e62368b..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1val4.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1VAL4` reader"] -pub type R = crate::R; -#[doc = "Register `SM1VAL4` writer"] -pub type W = crate::W; -#[doc = "Field `VAL4` reader - Value 4"] -pub type Val4R = crate::FieldReader; -#[doc = "Field `VAL4` writer - Value 4"] -pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&self) -> Val4R { - Val4R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&mut self) -> Val4W { - Val4W::new(self, 0) - } -} -#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1val4Spec; -impl crate::RegisterSpec for Sm1val4Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1val4::R`](R) reader structure"] -impl crate::Readable for Sm1val4Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1val4::W`](W) writer structure"] -impl crate::Writable for Sm1val4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1VAL4 to value 0"] -impl crate::Resettable for Sm1val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm1val5.rs b/mcxa276-pac/src/flexpwm0/sm1val5.rs deleted file mode 100644 index cb367d28e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm1val5.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM1VAL5` reader"] -pub type R = crate::R; -#[doc = "Register `SM1VAL5` writer"] -pub type W = crate::W; -#[doc = "Field `VAL5` reader - Value 5"] -pub type Val5R = crate::FieldReader; -#[doc = "Field `VAL5` writer - Value 5"] -pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&self) -> Val5R { - Val5R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&mut self) -> Val5W { - Val5W::new(self, 0) - } -} -#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm1val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm1val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm1val5Spec; -impl crate::RegisterSpec for Sm1val5Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm1val5::R`](R) reader structure"] -impl crate::Readable for Sm1val5Spec {} -#[doc = "`write(|w| ..)` method takes [`sm1val5::W`](W) writer structure"] -impl crate::Writable for Sm1val5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM1VAL5 to value 0"] -impl crate::Resettable for Sm1val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2captcompx.rs b/mcxa276-pac/src/flexpwm0/sm2captcompx.rs deleted file mode 100644 index 37563946f..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2captcompx.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `SM2CAPTCOMPX` reader"] -pub type R = crate::R; -#[doc = "Register `SM2CAPTCOMPX` writer"] -pub type W = crate::W; -#[doc = "Field `EDGCMPX` reader - Edge Compare X"] -pub type EdgcmpxR = crate::FieldReader; -#[doc = "Field `EDGCMPX` writer - Edge Compare X"] -pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EDGCNTX` reader - Edge Counter X"] -pub type EdgcntxR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&self) -> EdgcmpxR { - EdgcmpxR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Edge Counter X"] - #[inline(always)] - pub fn edgcntx(&self) -> EdgcntxR { - EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&mut self) -> EdgcmpxW { - EdgcmpxW::new(self, 0) - } -} -#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2captcompxSpec; -impl crate::RegisterSpec for Sm2captcompxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2captcompx::R`](R) reader structure"] -impl crate::Readable for Sm2captcompxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2captcompx::W`](W) writer structure"] -impl crate::Writable for Sm2captcompxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2CAPTCOMPX to value 0"] -impl crate::Resettable for Sm2captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm2captctrlx.rs deleted file mode 100644 index 4e71b6d60..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2captctrlx.rs +++ /dev/null @@ -1,493 +0,0 @@ -#[doc = "Register `SM2CAPTCTRLX` reader"] -pub type R = crate::R; -#[doc = "Register `SM2CAPTCTRLX` writer"] -pub type W = crate::W; -#[doc = "Arm X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Armx { - #[doc = "0: Input capture operation is disabled."] - Disabled = 0, - #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Armx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ARMX` reader - Arm X"] -pub type ArmxR = crate::BitReader; -impl ArmxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Armx { - match self.bits { - false => Armx::Disabled, - true => Armx::Enabled, - } - } - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Armx::Disabled - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Armx::Enabled - } -} -#[doc = "Field `ARMX` writer - Arm X"] -pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; -impl<'a, REG> ArmxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Armx::Disabled) - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Armx::Enabled) - } -} -#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Oneshotx { - #[doc = "0: Free Running"] - FreeRunning = 0, - #[doc = "1: One Shot"] - OneShot = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Oneshotx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] -pub type OneshotxR = crate::BitReader; -impl OneshotxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Oneshotx { - match self.bits { - false => Oneshotx::FreeRunning, - true => Oneshotx::OneShot, - } - } - #[doc = "Free Running"] - #[inline(always)] - pub fn is_free_running(&self) -> bool { - *self == Oneshotx::FreeRunning - } - #[doc = "One Shot"] - #[inline(always)] - pub fn is_one_shot(&self) -> bool { - *self == Oneshotx::OneShot - } -} -#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] -pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; -impl<'a, REG> OneshotxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Free Running"] - #[inline(always)] - pub fn free_running(self) -> &'a mut crate::W { - self.variant(Oneshotx::FreeRunning) - } - #[doc = "One Shot"] - #[inline(always)] - pub fn one_shot(self) -> &'a mut crate::W { - self.variant(Oneshotx::OneShot) - } -} -#[doc = "Edge X 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx0 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx0 { - type Ux = u8; -} -impl crate::IsEnum for Edgx0 {} -#[doc = "Field `EDGX0` reader - Edge X 0"] -pub type Edgx0R = crate::FieldReader; -impl Edgx0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx0 { - match self.bits { - 0 => Edgx0::Disabled, - 1 => Edgx0::FallingEdge, - 2 => Edgx0::RisingEdge, - 3 => Edgx0::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx0::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx0::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx0::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx0::AnyEdge - } -} -#[doc = "Field `EDGX0` writer - Edge X 0"] -pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; -impl<'a, REG> Edgx0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx0::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::AnyEdge) - } -} -#[doc = "Edge X 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx1 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx1 { - type Ux = u8; -} -impl crate::IsEnum for Edgx1 {} -#[doc = "Field `EDGX1` reader - Edge X 1"] -pub type Edgx1R = crate::FieldReader; -impl Edgx1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx1 { - match self.bits { - 0 => Edgx1::Disabled, - 1 => Edgx1::FallingEdge, - 2 => Edgx1::RisingEdge, - 3 => Edgx1::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx1::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx1::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx1::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx1::AnyEdge - } -} -#[doc = "Field `EDGX1` writer - Edge X 1"] -pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; -impl<'a, REG> Edgx1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx1::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::AnyEdge) - } -} -#[doc = "Input Select X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum InpSelx { - #[doc = "0: Raw PWM_X input signal selected as source."] - PwmX = 0, - #[doc = "1: Edge Counter"] - EdgeCounter = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: InpSelx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INP_SELX` reader - Input Select X"] -pub type InpSelxR = crate::BitReader; -impl InpSelxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InpSelx { - match self.bits { - false => InpSelx::PwmX, - true => InpSelx::EdgeCounter, - } - } - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InpSelx::PwmX - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn is_edge_counter(&self) -> bool { - *self == InpSelx::EdgeCounter - } -} -#[doc = "Field `INP_SELX` writer - Input Select X"] -pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; -impl<'a, REG> InpSelxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InpSelx::PwmX) - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn edge_counter(self) -> &'a mut crate::W { - self.variant(InpSelx::EdgeCounter) - } -} -#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EdgcntxEn { - #[doc = "0: Edge counter disabled and held in reset"] - Disabled = 0, - #[doc = "1: Edge counter enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EdgcntxEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] -pub type EdgcntxEnR = crate::BitReader; -impl EdgcntxEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EdgcntxEn { - match self.bits { - false => EdgcntxEn::Disabled, - true => EdgcntxEn::Enabled, - } - } - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == EdgcntxEn::Disabled - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == EdgcntxEn::Enabled - } -} -#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] -pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; -impl<'a, REG> EdgcntxEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Disabled) - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Enabled) - } -} -#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] -pub type CfxwmR = crate::FieldReader; -#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] -pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] -pub type Cx0cntR = crate::FieldReader; -#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] -pub type Cx1cntR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&self) -> ArmxR { - ArmxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&self) -> OneshotxR { - OneshotxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&self) -> Edgx0R { - Edgx0R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&self) -> Edgx1R { - Edgx1R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&self) -> InpSelxR { - InpSelxR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&self) -> EdgcntxEnR { - EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&self) -> CfxwmR { - CfxwmR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] - #[inline(always)] - pub fn cx0cnt(&self) -> Cx0cntR { - Cx0cntR::new(((self.bits >> 10) & 7) as u8) - } - #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] - #[inline(always)] - pub fn cx1cnt(&self) -> Cx1cntR { - Cx1cntR::new(((self.bits >> 13) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&mut self) -> ArmxW { - ArmxW::new(self, 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&mut self) -> OneshotxW { - OneshotxW::new(self, 1) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&mut self) -> Edgx0W { - Edgx0W::new(self, 2) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&mut self) -> Edgx1W { - Edgx1W::new(self, 4) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&mut self) -> InpSelxW { - InpSelxW::new(self, 6) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&mut self) -> EdgcntxEnW { - EdgcntxEnW::new(self, 7) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&mut self) -> CfxwmW { - CfxwmW::new(self, 8) - } -} -#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2captctrlxSpec; -impl crate::RegisterSpec for Sm2captctrlxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2captctrlx::R`](R) reader structure"] -impl crate::Readable for Sm2captctrlxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2captctrlx::W`](W) writer structure"] -impl crate::Writable for Sm2captctrlxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2CAPTCTRLX to value 0"] -impl crate::Resettable for Sm2captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm2captfiltx.rs deleted file mode 100644 index 760637d43..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2captfiltx.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `SM2CAPTFILTX` reader"] -pub type R = crate::R; -#[doc = "Register `SM2CAPTFILTX` writer"] -pub type W = crate::W; -#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] -pub type CaptxFiltPerR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] -pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] -pub type CaptxFiltCntR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] -pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&self) -> CaptxFiltPerR { - CaptxFiltPerR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { - CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { - CaptxFiltPerW::new(self, 0) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { - CaptxFiltCntW::new(self, 8) - } -} -#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2captfiltxSpec; -impl crate::RegisterSpec for Sm2captfiltxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2captfiltx::R`](R) reader structure"] -impl crate::Readable for Sm2captfiltxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2captfiltx::W`](W) writer structure"] -impl crate::Writable for Sm2captfiltxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2CAPTFILTX to value 0"] -impl crate::Resettable for Sm2captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cnt.rs b/mcxa276-pac/src/flexpwm0/sm2cnt.rs deleted file mode 100644 index 81d78d086..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2cnt.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM2CNT` reader"] -pub type R = crate::R; -#[doc = "Field `CNT` reader - Counter Register Bits"] -pub type CntR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Counter Register Bits"] - #[inline(always)] - pub fn cnt(&self) -> CntR { - CntR::new(self.bits) - } -} -#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2cntSpec; -impl crate::RegisterSpec for Sm2cntSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2cnt::R`](R) reader structure"] -impl crate::Readable for Sm2cntSpec {} -#[doc = "`reset()` method sets SM2CNT to value 0"] -impl crate::Resettable for Sm2cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2ctrl.rs b/mcxa276-pac/src/flexpwm0/sm2ctrl.rs deleted file mode 100644 index 2856a9962..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2ctrl.rs +++ /dev/null @@ -1,871 +0,0 @@ -#[doc = "Register `SM2CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM2CTRL` writer"] -pub type W = crate::W; -#[doc = "Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblen { - #[doc = "0: Double switching disabled."] - Disabled = 0, - #[doc = "1: Double switching enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLEN` reader - Double Switching Enable"] -pub type DblenR = crate::BitReader; -impl DblenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblen { - match self.bits { - false => Dblen::Disabled, - true => Dblen::Enabled, - } - } - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblen::Disabled - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblen::Enabled - } -} -#[doc = "Field `DBLEN` writer - Double Switching Enable"] -pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; -impl<'a, REG> DblenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblen::Disabled) - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblen::Enabled) - } -} -#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblx { - #[doc = "0: PWM_X double pulse disabled."] - Disabled = 0, - #[doc = "1: PWM_X double pulse enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] -pub type DblxR = crate::BitReader; -impl DblxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblx { - match self.bits { - false => Dblx::Disabled, - true => Dblx::Enabled, - } - } - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblx::Disabled - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblx::Enabled - } -} -#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] -pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; -impl<'a, REG> DblxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblx::Disabled) - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblx::Enabled) - } -} -#[doc = "Load Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldmod { - #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - NextPwmReload = 0, - #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - MtctrlLdokSet = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldmod) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDMOD` reader - Load Mode Select"] -pub type LdmodR = crate::BitReader; -impl LdmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldmod { - match self.bits { - false => Ldmod::NextPwmReload, - true => Ldmod::MtctrlLdokSet, - } - } - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn is_next_pwm_reload(&self) -> bool { - *self == Ldmod::NextPwmReload - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn is_mtctrl_ldok_set(&self) -> bool { - *self == Ldmod::MtctrlLdokSet - } -} -#[doc = "Field `LDMOD` writer - Load Mode Select"] -pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; -impl<'a, REG> LdmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn next_pwm_reload(self) -> &'a mut crate::W { - self.variant(Ldmod::NextPwmReload) - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { - self.variant(Ldmod::MtctrlLdokSet) - } -} -#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Split { - #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - Disabled = 0, - #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Split) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitR = crate::BitReader; -impl SplitR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Split { - match self.bits { - false => Split::Disabled, - true => Split::Enabled, - } - } - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Split::Disabled - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Split::Enabled - } -} -#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; -impl<'a, REG> SplitW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Split::Disabled) - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Split::Enabled) - } -} -#[doc = "Prescaler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Prsc { - #[doc = "0: Prescaler 1"] - One = 0, - #[doc = "1: Prescaler 2"] - Two = 1, - #[doc = "2: Prescaler 4"] - Four = 2, - #[doc = "3: Prescaler 8"] - Eight = 3, - #[doc = "4: Prescaler 16"] - Sixteen = 4, - #[doc = "5: Prescaler 32"] - Thirtytwo = 5, - #[doc = "6: Prescaler 64"] - Sixtyfour = 6, - #[doc = "7: Prescaler 128"] - Hundredtwentyeight = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Prsc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Prsc { - type Ux = u8; -} -impl crate::IsEnum for Prsc {} -#[doc = "Field `PRSC` reader - Prescaler"] -pub type PrscR = crate::FieldReader; -impl PrscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prsc { - match self.bits { - 0 => Prsc::One, - 1 => Prsc::Two, - 2 => Prsc::Four, - 3 => Prsc::Eight, - 4 => Prsc::Sixteen, - 5 => Prsc::Thirtytwo, - 6 => Prsc::Sixtyfour, - 7 => Prsc::Hundredtwentyeight, - _ => unreachable!(), - } - } - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Prsc::One - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn is_two(&self) -> bool { - *self == Prsc::Two - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn is_four(&self) -> bool { - *self == Prsc::Four - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn is_eight(&self) -> bool { - *self == Prsc::Eight - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn is_sixteen(&self) -> bool { - *self == Prsc::Sixteen - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn is_thirtytwo(&self) -> bool { - *self == Prsc::Thirtytwo - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn is_sixtyfour(&self) -> bool { - *self == Prsc::Sixtyfour - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn is_hundredtwentyeight(&self) -> bool { - *self == Prsc::Hundredtwentyeight - } -} -#[doc = "Field `PRSC` writer - Prescaler"] -pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; -impl<'a, REG> PrscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn one(self) -> &'a mut crate::W { - self.variant(Prsc::One) - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn two(self) -> &'a mut crate::W { - self.variant(Prsc::Two) - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn four(self) -> &'a mut crate::W { - self.variant(Prsc::Four) - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn eight(self) -> &'a mut crate::W { - self.variant(Prsc::Eight) - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn sixteen(self) -> &'a mut crate::W { - self.variant(Prsc::Sixteen) - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn thirtytwo(self) -> &'a mut crate::W { - self.variant(Prsc::Thirtytwo) - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn sixtyfour(self) -> &'a mut crate::W { - self.variant(Prsc::Sixtyfour) - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn hundredtwentyeight(self) -> &'a mut crate::W { - self.variant(Prsc::Hundredtwentyeight) - } -} -#[doc = "Compare Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Compmode { - #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - EqualTo = 0, - #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - EqualToOrGreaterThan = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Compmode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPMODE` reader - Compare Mode"] -pub type CompmodeR = crate::BitReader; -impl CompmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Compmode { - match self.bits { - false => Compmode::EqualTo, - true => Compmode::EqualToOrGreaterThan, - } - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn is_equal_to(&self) -> bool { - *self == Compmode::EqualTo - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn is_equal_to_or_greater_than(&self) -> bool { - *self == Compmode::EqualToOrGreaterThan - } -} -#[doc = "Field `COMPMODE` writer - Compare Mode"] -pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; -impl<'a, REG> CompmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn equal_to(self) -> &'a mut crate::W { - self.variant(Compmode::EqualTo) - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { - self.variant(Compmode::EqualToOrGreaterThan) - } -} -#[doc = "Field `DT` reader - Deadtime"] -pub type DtR = crate::FieldReader; -#[doc = "Full Cycle Reload\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Full { - #[doc = "0: Full-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Full-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FULL` reader - Full Cycle Reload"] -pub type FullR = crate::BitReader; -impl FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Full { - match self.bits { - false => Full::Disabled, - true => Full::Enabled, - } - } - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Full::Disabled - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Full::Enabled - } -} -#[doc = "Field `FULL` writer - Full Cycle Reload"] -pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; -impl<'a, REG> FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Full::Disabled) - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Full::Enabled) - } -} -#[doc = "Half Cycle Reload\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Half { - #[doc = "0: Half-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Half-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Half) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALF` reader - Half Cycle Reload"] -pub type HalfR = crate::BitReader; -impl HalfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Half { - match self.bits { - false => Half::Disabled, - true => Half::Enabled, - } - } - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Half::Disabled - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Half::Enabled - } -} -#[doc = "Field `HALF` writer - Half Cycle Reload"] -pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; -impl<'a, REG> HalfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Half::Disabled) - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Half::Enabled) - } -} -#[doc = "Load Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ldfq { - #[doc = "0: Every PWM opportunity"] - Everypwm = 0, - #[doc = "1: Every 2 PWM opportunities"] - Every2pwm = 1, - #[doc = "2: Every 3 PWM opportunities"] - Every3pwm = 2, - #[doc = "3: Every 4 PWM opportunities"] - Every4pwm = 3, - #[doc = "4: Every 5 PWM opportunities"] - Every5pwm = 4, - #[doc = "5: Every 6 PWM opportunities"] - Every6pwm = 5, - #[doc = "6: Every 7 PWM opportunities"] - Every7pwm = 6, - #[doc = "7: Every 8 PWM opportunities"] - Every8pwm = 7, - #[doc = "8: Every 9 PWM opportunities"] - Every9pwm = 8, - #[doc = "9: Every 10 PWM opportunities"] - Every10pwm = 9, - #[doc = "10: Every 11 PWM opportunities"] - Every11pwm = 10, - #[doc = "11: Every 12 PWM opportunities"] - Every12pwm = 11, - #[doc = "12: Every 13 PWM opportunities"] - Every13pwm = 12, - #[doc = "13: Every 14 PWM opportunities"] - Every14pwm = 13, - #[doc = "14: Every 15 PWM opportunities"] - Every15pwm = 14, - #[doc = "15: Every 16 PWM opportunities"] - Every16pwm = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ldfq) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ldfq { - type Ux = u8; -} -impl crate::IsEnum for Ldfq {} -#[doc = "Field `LDFQ` reader - Load Frequency"] -pub type LdfqR = crate::FieldReader; -impl LdfqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldfq { - match self.bits { - 0 => Ldfq::Everypwm, - 1 => Ldfq::Every2pwm, - 2 => Ldfq::Every3pwm, - 3 => Ldfq::Every4pwm, - 4 => Ldfq::Every5pwm, - 5 => Ldfq::Every6pwm, - 6 => Ldfq::Every7pwm, - 7 => Ldfq::Every8pwm, - 8 => Ldfq::Every9pwm, - 9 => Ldfq::Every10pwm, - 10 => Ldfq::Every11pwm, - 11 => Ldfq::Every12pwm, - 12 => Ldfq::Every13pwm, - 13 => Ldfq::Every14pwm, - 14 => Ldfq::Every15pwm, - 15 => Ldfq::Every16pwm, - _ => unreachable!(), - } - } - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Ldfq::Everypwm - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn is_every2pwm(&self) -> bool { - *self == Ldfq::Every2pwm - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn is_every3pwm(&self) -> bool { - *self == Ldfq::Every3pwm - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn is_every4pwm(&self) -> bool { - *self == Ldfq::Every4pwm - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn is_every5pwm(&self) -> bool { - *self == Ldfq::Every5pwm - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn is_every6pwm(&self) -> bool { - *self == Ldfq::Every6pwm - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn is_every7pwm(&self) -> bool { - *self == Ldfq::Every7pwm - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn is_every8pwm(&self) -> bool { - *self == Ldfq::Every8pwm - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn is_every9pwm(&self) -> bool { - *self == Ldfq::Every9pwm - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn is_every10pwm(&self) -> bool { - *self == Ldfq::Every10pwm - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn is_every11pwm(&self) -> bool { - *self == Ldfq::Every11pwm - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn is_every12pwm(&self) -> bool { - *self == Ldfq::Every12pwm - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn is_every13pwm(&self) -> bool { - *self == Ldfq::Every13pwm - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn is_every14pwm(&self) -> bool { - *self == Ldfq::Every14pwm - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn is_every15pwm(&self) -> bool { - *self == Ldfq::Every15pwm - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn is_every16pwm(&self) -> bool { - *self == Ldfq::Every16pwm - } -} -#[doc = "Field `LDFQ` writer - Load Frequency"] -pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; -impl<'a, REG> LdfqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Everypwm) - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn every2pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every2pwm) - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn every3pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every3pwm) - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn every4pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every4pwm) - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn every5pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every5pwm) - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn every6pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every6pwm) - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn every7pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every7pwm) - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn every8pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every8pwm) - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn every9pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every9pwm) - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn every10pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every10pwm) - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn every11pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every11pwm) - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn every12pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every12pwm) - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn every13pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every13pwm) - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn every14pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every14pwm) - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn every15pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every15pwm) - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn every16pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every16pwm) - } -} -impl R { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&self) -> DblenR { - DblenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&self) -> DblxR { - DblxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&self) -> LdmodR { - LdmodR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&self) -> SplitR { - SplitR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&self) -> PrscR { - PrscR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&self) -> CompmodeR { - CompmodeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Deadtime"] - #[inline(always)] - pub fn dt(&self) -> DtR { - DtR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&self) -> FullR { - FullR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&self) -> HalfR { - HalfR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&self) -> LdfqR { - LdfqR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&mut self) -> DblenW { - DblenW::new(self, 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&mut self) -> DblxW { - DblxW::new(self, 1) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&mut self) -> LdmodW { - LdmodW::new(self, 2) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&mut self) -> SplitW { - SplitW::new(self, 3) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&mut self) -> PrscW { - PrscW::new(self, 4) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&mut self) -> CompmodeW { - CompmodeW::new(self, 7) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&mut self) -> FullW { - FullW::new(self, 10) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&mut self) -> HalfW { - HalfW::new(self, 11) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&mut self) -> LdfqW { - LdfqW::new(self, 12) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2ctrlSpec; -impl crate::RegisterSpec for Sm2ctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2ctrl::R`](R) reader structure"] -impl crate::Readable for Sm2ctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2ctrl::W`](W) writer structure"] -impl crate::Writable for Sm2ctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2CTRL to value 0x0400"] -impl crate::Resettable for Sm2ctrlSpec { - const RESET_VALUE: u16 = 0x0400; -} diff --git a/mcxa276-pac/src/flexpwm0/sm2ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm2ctrl2.rs deleted file mode 100644 index 2b115e937..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2ctrl2.rs +++ /dev/null @@ -1,607 +0,0 @@ -#[doc = "Register `SM2CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM2CTRL2` writer"] -pub type W = crate::W; -#[doc = "Clock Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ClkSel { - #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] - Ipbus = 0, - #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] - ExtClk = 1, - #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - AuxClk = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ClkSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ClkSel { - type Ux = u8; -} -impl crate::IsEnum for ClkSel {} -#[doc = "Field `CLK_SEL` reader - Clock Source Select"] -pub type ClkSelR = crate::FieldReader; -impl ClkSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(ClkSel::Ipbus), - 1 => Some(ClkSel::ExtClk), - 2 => Some(ClkSel::AuxClk), - _ => None, - } - } - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ipbus(&self) -> bool { - *self == ClkSel::Ipbus - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ext_clk(&self) -> bool { - *self == ClkSel::ExtClk - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn is_aux_clk(&self) -> bool { - *self == ClkSel::AuxClk - } -} -#[doc = "Field `CLK_SEL` writer - Clock Source Select"] -pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; -impl<'a, REG> ClkSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ipbus(self) -> &'a mut crate::W { - self.variant(ClkSel::Ipbus) - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ext_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::ExtClk) - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn aux_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::AuxClk) - } -} -#[doc = "Reload Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ReloadSel { - #[doc = "0: The local RELOAD signal is used to reload registers."] - Local = 0, - #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - Master = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ReloadSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] -pub type ReloadSelR = crate::BitReader; -impl ReloadSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ReloadSel { - match self.bits { - false => ReloadSel::Local, - true => ReloadSel::Master, - } - } - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ReloadSel::Local - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ReloadSel::Master - } -} -#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] -pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; -impl<'a, REG> ReloadSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ReloadSel::Local) - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ReloadSel::Master) - } -} -#[doc = "Force Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ForceSel { - #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - Local = 0, - #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - Master = 1, - #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - LocalReload = 2, - #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterReload = 3, - #[doc = "4: The local sync signal from this submodule is used to force updates."] - LocalSync = 4, - #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterSync = 5, - #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - ExtForce = 6, - #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - ExtSync = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ForceSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ForceSel { - type Ux = u8; -} -impl crate::IsEnum for ForceSel {} -#[doc = "Field `FORCE_SEL` reader - Force Select"] -pub type ForceSelR = crate::FieldReader; -impl ForceSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ForceSel { - match self.bits { - 0 => ForceSel::Local, - 1 => ForceSel::Master, - 2 => ForceSel::LocalReload, - 3 => ForceSel::MasterReload, - 4 => ForceSel::LocalSync, - 5 => ForceSel::MasterSync, - 6 => ForceSel::ExtForce, - 7 => ForceSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ForceSel::Local - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ForceSel::Master - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == ForceSel::LocalReload - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == ForceSel::MasterReload - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == ForceSel::LocalSync - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == ForceSel::MasterSync - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_force(&self) -> bool { - *self == ForceSel::ExtForce - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == ForceSel::ExtSync - } -} -#[doc = "Field `FORCE_SEL` writer - Force Select"] -pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; -impl<'a, REG> ForceSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ForceSel::Local) - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ForceSel::Master) - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalReload) - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterReload) - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalSync) - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterSync) - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_force(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtForce) - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtSync) - } -} -#[doc = "Field `FORCE` reader - Force Initialization"] -pub type ForceR = crate::BitReader; -#[doc = "Field `FORCE` writer - Force Initialization"] -pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Force Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frcen { - #[doc = "0: Initialization from a FORCE_OUT is disabled."] - Disabled = 0, - #[doc = "1: Initialization from a FORCE_OUT is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRCEN` reader - Force Enable"] -pub type FrcenR = crate::BitReader; -impl FrcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frcen { - match self.bits { - false => Frcen::Disabled, - true => Frcen::Enabled, - } - } - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Frcen::Disabled - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Frcen::Enabled - } -} -#[doc = "Field `FRCEN` writer - Force Enable"] -pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; -impl<'a, REG> FrcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Frcen::Disabled) - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Frcen::Enabled) - } -} -#[doc = "Initialization Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum InitSel { - #[doc = "0: Local sync (PWM_X) causes initialization."] - PwmX = 0, - #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - MasterReload = 1, - #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - MasterSync = 2, - #[doc = "3: EXT_SYNC causes initialization."] - ExtSync = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: InitSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for InitSel { - type Ux = u8; -} -impl crate::IsEnum for InitSel {} -#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] -pub type InitSelR = crate::FieldReader; -impl InitSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InitSel { - match self.bits { - 0 => InitSel::PwmX, - 1 => InitSel::MasterReload, - 2 => InitSel::MasterSync, - 3 => InitSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InitSel::PwmX - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == InitSel::MasterReload - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == InitSel::MasterSync - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == InitSel::ExtSync - } -} -#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] -pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; -impl<'a, REG> InitSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InitSel::PwmX) - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(InitSel::MasterReload) - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(InitSel::MasterSync) - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(InitSel::ExtSync) - } -} -#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] -pub type PwmxInitR = crate::BitReader; -#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] -pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] -pub type Pwm45InitR = crate::BitReader; -#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] -pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] -pub type Pwm23InitR = crate::BitReader; -#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] -pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Indep { - #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] - Complementary = 0, - #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] - Independent = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Indep) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] -pub type IndepR = crate::BitReader; -impl IndepR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Indep { - match self.bits { - false => Indep::Complementary, - true => Indep::Independent, - } - } - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn is_complementary(&self) -> bool { - *self == Indep::Complementary - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn is_independent(&self) -> bool { - *self == Indep::Independent - } -} -#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] -pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; -impl<'a, REG> IndepW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn complementary(self) -> &'a mut crate::W { - self.variant(Indep::Complementary) - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn independent(self) -> &'a mut crate::W { - self.variant(Indep::Independent) - } -} -#[doc = "Field `DBGEN` reader - Debug Enable"] -pub type DbgenR = crate::BitReader; -#[doc = "Field `DBGEN` writer - Debug Enable"] -pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&self) -> ClkSelR { - ClkSelR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&self) -> ReloadSelR { - ReloadSelR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&self) -> ForceSelR { - ForceSelR::new(((self.bits >> 3) & 7) as u8) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&self) -> ForceR { - ForceR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&self) -> FrcenR { - FrcenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&self) -> InitSelR { - InitSelR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&self) -> PwmxInitR { - PwmxInitR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&self) -> Pwm45InitR { - Pwm45InitR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&self) -> Pwm23InitR { - Pwm23InitR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&self) -> IndepR { - IndepR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&self) -> DbgenR { - DbgenR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&mut self) -> ClkSelW { - ClkSelW::new(self, 0) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&mut self) -> ReloadSelW { - ReloadSelW::new(self, 2) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&mut self) -> ForceSelW { - ForceSelW::new(self, 3) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&mut self) -> ForceW { - ForceW::new(self, 6) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&mut self) -> FrcenW { - FrcenW::new(self, 7) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&mut self) -> InitSelW { - InitSelW::new(self, 8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&mut self) -> PwmxInitW { - PwmxInitW::new(self, 10) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&mut self) -> Pwm45InitW { - Pwm45InitW::new(self, 11) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&mut self) -> Pwm23InitW { - Pwm23InitW::new(self, 12) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&mut self) -> IndepW { - IndepW::new(self, 13) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&mut self) -> DbgenW { - DbgenW::new(self, 15) - } -} -#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2ctrl2Spec; -impl crate::RegisterSpec for Sm2ctrl2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2ctrl2::R`](R) reader structure"] -impl crate::Readable for Sm2ctrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2ctrl2::W`](W) writer structure"] -impl crate::Writable for Sm2ctrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2CTRL2 to value 0"] -impl crate::Resettable for Sm2ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval0.rs b/mcxa276-pac/src/flexpwm0/sm2cval0.rs deleted file mode 100644 index 228743cfd..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2cval0.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM2CVAL0` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] -pub type Captval0R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 0"] - #[inline(always)] - pub fn captval0(&self) -> Captval0R { - Captval0R::new(self.bits) - } -} -#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2cval0Spec; -impl crate::RegisterSpec for Sm2cval0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2cval0::R`](R) reader structure"] -impl crate::Readable for Sm2cval0Spec {} -#[doc = "`reset()` method sets SM2CVAL0 to value 0"] -impl crate::Resettable for Sm2cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs deleted file mode 100644 index 1146b3fa2..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2cval0cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM2CVAL0CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] -pub type Cval0cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 0 Cycle"] - #[inline(always)] - pub fn cval0cyc(&self) -> Cval0cycR { - Cval0cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2cval0cycSpec; -impl crate::RegisterSpec for Sm2cval0cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2cval0cyc::R`](R) reader structure"] -impl crate::Readable for Sm2cval0cycSpec {} -#[doc = "`reset()` method sets SM2CVAL0CYC to value 0"] -impl crate::Resettable for Sm2cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval1.rs b/mcxa276-pac/src/flexpwm0/sm2cval1.rs deleted file mode 100644 index 9f667cdb7..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2cval1.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM2CVAL1` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] -pub type Captval1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 1"] - #[inline(always)] - pub fn captval1(&self) -> Captval1R { - Captval1R::new(self.bits) - } -} -#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2cval1Spec; -impl crate::RegisterSpec for Sm2cval1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2cval1::R`](R) reader structure"] -impl crate::Readable for Sm2cval1Spec {} -#[doc = "`reset()` method sets SM2CVAL1 to value 0"] -impl crate::Resettable for Sm2cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs deleted file mode 100644 index d62b3e407..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2cval1cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM2CVAL1CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] -pub type Cval1cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 1 Cycle"] - #[inline(always)] - pub fn cval1cyc(&self) -> Cval1cycR { - Cval1cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2cval1cycSpec; -impl crate::RegisterSpec for Sm2cval1cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2cval1cyc::R`](R) reader structure"] -impl crate::Readable for Sm2cval1cycSpec {} -#[doc = "`reset()` method sets SM2CVAL1CYC to value 0"] -impl crate::Resettable for Sm2cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2dismap0.rs b/mcxa276-pac/src/flexpwm0/sm2dismap0.rs deleted file mode 100644 index aa571c2d7..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2dismap0.rs +++ /dev/null @@ -1,65 +0,0 @@ -#[doc = "Register `SM2DISMAP0` reader"] -pub type R = crate::R; -#[doc = "Register `SM2DISMAP0` writer"] -pub type W = crate::W; -#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] -pub type Dis0aR = crate::FieldReader; -#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] -pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] -pub type Dis0bR = crate::FieldReader; -#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] -pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] -pub type Dis0xR = crate::FieldReader; -#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] -pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&self) -> Dis0aR { - Dis0aR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&self) -> Dis0bR { - Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&self) -> Dis0xR { - Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&mut self) -> Dis0aW { - Dis0aW::new(self, 0) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&mut self) -> Dis0bW { - Dis0bW::new(self, 4) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&mut self) -> Dis0xW { - Dis0xW::new(self, 8) - } -} -#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2dismap0Spec; -impl crate::RegisterSpec for Sm2dismap0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2dismap0::R`](R) reader structure"] -impl crate::Readable for Sm2dismap0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2dismap0::W`](W) writer structure"] -impl crate::Writable for Sm2dismap0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2DISMAP0 to value 0xffff"] -impl crate::Resettable for Sm2dismap0Spec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm2dmaen.rs b/mcxa276-pac/src/flexpwm0/sm2dmaen.rs deleted file mode 100644 index 750bf3156..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2dmaen.rs +++ /dev/null @@ -1,271 +0,0 @@ -#[doc = "Register `SM2DMAEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM2DMAEN` writer"] -pub type W = crate::W; -#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] -pub type Cx0deR = crate::BitReader; -#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] -pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] -pub type Cx1deR = crate::BitReader; -#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] -pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Captde { - #[doc = "0: Read DMA requests disabled."] - Disabled = 0, - #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - Exceedfifo = 1, - #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] - LocalSync = 2, - #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] - LocalReload = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Captde) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Captde { - type Ux = u8; -} -impl crate::IsEnum for Captde {} -#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] -pub type CaptdeR = crate::FieldReader; -impl CaptdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Captde { - match self.bits { - 0 => Captde::Disabled, - 1 => Captde::Exceedfifo, - 2 => Captde::LocalSync, - 3 => Captde::LocalReload, - _ => unreachable!(), - } - } - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Captde::Disabled - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn is_exceedfifo(&self) -> bool { - *self == Captde::Exceedfifo - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == Captde::LocalSync - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == Captde::LocalReload - } -} -#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] -pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; -impl<'a, REG> CaptdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Captde::Disabled) - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn exceedfifo(self) -> &'a mut crate::W { - self.variant(Captde::Exceedfifo) - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(Captde::LocalSync) - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(Captde::LocalReload) - } -} -#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fand { - #[doc = "0: Selected FIFO watermarks are OR'ed together."] - Or = 0, - #[doc = "1: Selected FIFO watermarks are AND'ed together."] - And = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fand) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] -pub type FandR = crate::BitReader; -impl FandR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fand { - match self.bits { - false => Fand::Or, - true => Fand::And, - } - } - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn is_or(&self) -> bool { - *self == Fand::Or - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn is_and(&self) -> bool { - *self == Fand::And - } -} -#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] -pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; -impl<'a, REG> FandW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn or(self) -> &'a mut crate::W { - self.variant(Fand::Or) - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn and(self) -> &'a mut crate::W { - self.variant(Fand::And) - } -} -#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Valde { - #[doc = "0: DMA write requests disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Valde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] -pub type ValdeR = crate::BitReader; -impl ValdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Valde { - match self.bits { - false => Valde::Disabled, - true => Valde::Enabled, - } - } - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Valde::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Valde::Enabled - } -} -#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] -pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; -impl<'a, REG> ValdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Valde::Disabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Valde::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&self) -> Cx0deR { - Cx0deR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&self) -> Cx1deR { - Cx1deR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&self) -> CaptdeR { - CaptdeR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&self) -> FandR { - FandR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&self) -> ValdeR { - ValdeR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&mut self) -> Cx0deW { - Cx0deW::new(self, 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&mut self) -> Cx1deW { - Cx1deW::new(self, 1) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&mut self) -> CaptdeW { - CaptdeW::new(self, 6) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&mut self) -> FandW { - FandW::new(self, 8) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&mut self) -> ValdeW { - ValdeW::new(self, 9) - } -} -#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2dmaenSpec; -impl crate::RegisterSpec for Sm2dmaenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2dmaen::R`](R) reader structure"] -impl crate::Readable for Sm2dmaenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2dmaen::W`](W) writer structure"] -impl crate::Writable for Sm2dmaenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2DMAEN to value 0"] -impl crate::Resettable for Sm2dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs deleted file mode 100644 index b35817d79..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2dtcnt0.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM2DTCNT0` reader"] -pub type R = crate::R; -#[doc = "Register `SM2DTCNT0` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] -pub type Dtcnt0R = crate::FieldReader; -#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] -pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&self) -> Dtcnt0R { - Dtcnt0R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&mut self) -> Dtcnt0W { - Dtcnt0W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2dtcnt0Spec; -impl crate::RegisterSpec for Sm2dtcnt0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2dtcnt0::R`](R) reader structure"] -impl crate::Readable for Sm2dtcnt0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2dtcnt0::W`](W) writer structure"] -impl crate::Writable for Sm2dtcnt0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2DTCNT0 to value 0x07ff"] -impl crate::Resettable for Sm2dtcnt0Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs deleted file mode 100644 index ae1998374..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2dtcnt1.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM2DTCNT1` reader"] -pub type R = crate::R; -#[doc = "Register `SM2DTCNT1` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] -pub type Dtcnt1R = crate::FieldReader; -#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] -pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&self) -> Dtcnt1R { - Dtcnt1R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&mut self) -> Dtcnt1W { - Dtcnt1W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2dtcnt1Spec; -impl crate::RegisterSpec for Sm2dtcnt1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2dtcnt1::R`](R) reader structure"] -impl crate::Readable for Sm2dtcnt1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2dtcnt1::W`](W) writer structure"] -impl crate::Writable for Sm2dtcnt1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2DTCNT1 to value 0x07ff"] -impl crate::Resettable for Sm2dtcnt1Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm2init.rs b/mcxa276-pac/src/flexpwm0/sm2init.rs deleted file mode 100644 index 40972e549..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2init.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2INIT` reader"] -pub type R = crate::R; -#[doc = "Register `SM2INIT` writer"] -pub type W = crate::W; -#[doc = "Field `INIT` reader - Initial Count Register Bits"] -pub type InitR = crate::FieldReader; -#[doc = "Field `INIT` writer - Initial Count Register Bits"] -pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&self) -> InitR { - InitR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&mut self) -> InitW { - InitW::new(self, 0) - } -} -#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2initSpec; -impl crate::RegisterSpec for Sm2initSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2init::R`](R) reader structure"] -impl crate::Readable for Sm2initSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2init::W`](W) writer structure"] -impl crate::Writable for Sm2initSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2INIT to value 0"] -impl crate::Resettable for Sm2initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2inten.rs b/mcxa276-pac/src/flexpwm0/sm2inten.rs deleted file mode 100644 index 8fb99fdd7..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2inten.rs +++ /dev/null @@ -1,343 +0,0 @@ -#[doc = "Register `SM2INTEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM2INTEN` writer"] -pub type W = crate::W; -#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpie { - #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - Disabled = 0, - #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - Enabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpie) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpie { - type Ux = u8; -} -impl crate::IsEnum for Cmpie {} -#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] -pub type CmpieR = crate::FieldReader; -impl CmpieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpie::Disabled), - 1 => Some(Cmpie::Enabled), - _ => None, - } - } - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmpie::Disabled - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmpie::Enabled - } -} -#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] -pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; -impl<'a, REG> CmpieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Disabled) - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Enabled) - } -} -#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx0ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx0ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] -pub type Cx0ieR = crate::BitReader; -impl Cx0ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx0ie { - match self.bits { - false => Cx0ie::Disabled, - true => Cx0ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx0ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx0ie::Enabled - } -} -#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] -pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; -impl<'a, REG> Cx0ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Enabled) - } -} -#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx1ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx1ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] -pub type Cx1ieR = crate::BitReader; -impl Cx1ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx1ie { - match self.bits { - false => Cx1ie::Disabled, - true => Cx1ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx1ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx1ie::Enabled - } -} -#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] -pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; -impl<'a, REG> Cx1ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Enabled) - } -} -#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rie { - #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RIE` reader - Reload Interrupt Enable"] -pub type RieR = crate::BitReader; -impl RieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rie { - match self.bits { - false => Rie::Disabled, - true => Rie::Enabled, - } - } - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rie::Disabled - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rie::Enabled - } -} -#[doc = "Field `RIE` writer - Reload Interrupt Enable"] -pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; -impl<'a, REG> RieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rie::Disabled) - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rie::Enabled) - } -} -#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reie { - #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] -pub type ReieR = crate::BitReader; -impl ReieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reie { - match self.bits { - false => Reie::Disabled, - true => Reie::Enabled, - } - } - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Reie::Disabled - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Reie::Enabled - } -} -#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] -pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; -impl<'a, REG> ReieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Reie::Disabled) - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Reie::Enabled) - } -} -impl R { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&self) -> CmpieR { - CmpieR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&self) -> Cx0ieR { - Cx0ieR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&self) -> Cx1ieR { - Cx1ieR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&self) -> RieR { - RieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&self) -> ReieR { - ReieR::new(((self.bits >> 13) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&mut self) -> CmpieW { - CmpieW::new(self, 0) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&mut self) -> Cx0ieW { - Cx0ieW::new(self, 6) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&mut self) -> Cx1ieW { - Cx1ieW::new(self, 7) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&mut self) -> RieW { - RieW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&mut self) -> ReieW { - ReieW::new(self, 13) - } -} -#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2intenSpec; -impl crate::RegisterSpec for Sm2intenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2inten::R`](R) reader structure"] -impl crate::Readable for Sm2intenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2inten::W`](W) writer structure"] -impl crate::Writable for Sm2intenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2INTEN to value 0"] -impl crate::Resettable for Sm2intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2octrl.rs b/mcxa276-pac/src/flexpwm0/sm2octrl.rs deleted file mode 100644 index 45f411730..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2octrl.rs +++ /dev/null @@ -1,519 +0,0 @@ -#[doc = "Register `SM2OCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM2OCTRL` writer"] -pub type W = crate::W; -#[doc = "PWM_X Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmxfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmxfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmxfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmxfs {} -#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] -pub type PwmxfsR = crate::FieldReader; -impl PwmxfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmxfs { - match self.bits { - 0 => Pwmxfs::Logic0, - 1 => Pwmxfs::Logic1, - 2 => Pwmxfs::Tristated2, - 3 => Pwmxfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmxfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmxfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmxfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmxfs::Tristated3 - } -} -#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] -pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; -impl<'a, REG> PwmxfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated3) - } -} -#[doc = "PWM_B Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmbfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmbfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmbfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmbfs {} -#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] -pub type PwmbfsR = crate::FieldReader; -impl PwmbfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmbfs { - match self.bits { - 0 => Pwmbfs::Logic0, - 1 => Pwmbfs::Logic1, - 2 => Pwmbfs::Tristated2, - 3 => Pwmbfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmbfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmbfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmbfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmbfs::Tristated3 - } -} -#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] -pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; -impl<'a, REG> PwmbfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated3) - } -} -#[doc = "PWM_A Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmafs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmafs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmafs { - type Ux = u8; -} -impl crate::IsEnum for Pwmafs {} -#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] -pub type PwmafsR = crate::FieldReader; -impl PwmafsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmafs { - match self.bits { - 0 => Pwmafs::Logic0, - 1 => Pwmafs::Logic1, - 2 => Pwmafs::Tristated2, - 3 => Pwmafs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmafs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmafs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmafs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmafs::Tristated3 - } -} -#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] -pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; -impl<'a, REG> PwmafsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated3) - } -} -#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polx { - #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLX` reader - PWM_X Output Polarity"] -pub type PolxR = crate::BitReader; -impl PolxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polx { - match self.bits { - false => Polx::NotInverted, - true => Polx::Inverted, - } - } - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polx::NotInverted - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polx::Inverted - } -} -#[doc = "Field `POLX` writer - PWM_X Output Polarity"] -pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; -impl<'a, REG> PolxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polx::NotInverted) - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polx::Inverted) - } -} -#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polb { - #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLB` reader - PWM_B Output Polarity"] -pub type PolbR = crate::BitReader; -impl PolbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polb { - match self.bits { - false => Polb::NotInverted, - true => Polb::Inverted, - } - } - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polb::NotInverted - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polb::Inverted - } -} -#[doc = "Field `POLB` writer - PWM_B Output Polarity"] -pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; -impl<'a, REG> PolbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polb::NotInverted) - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polb::Inverted) - } -} -#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pola { - #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pola) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLA` reader - PWM_A Output Polarity"] -pub type PolaR = crate::BitReader; -impl PolaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pola { - match self.bits { - false => Pola::NotInverted, - true => Pola::Inverted, - } - } - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Pola::NotInverted - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Pola::Inverted - } -} -#[doc = "Field `POLA` writer - PWM_A Output Polarity"] -pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; -impl<'a, REG> PolaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Pola::NotInverted) - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Pola::Inverted) - } -} -#[doc = "Field `PWMX_IN` reader - PWM_X Input"] -pub type PwmxInR = crate::BitReader; -#[doc = "Field `PWMB_IN` reader - PWM_B Input"] -pub type PwmbInR = crate::BitReader; -#[doc = "Field `PWMA_IN` reader - PWM_A Input"] -pub type PwmaInR = crate::BitReader; -impl R { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&self) -> PwmxfsR { - PwmxfsR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&self) -> PwmbfsR { - PwmbfsR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&self) -> PwmafsR { - PwmafsR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&self) -> PolxR { - PolxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&self) -> PolbR { - PolbR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&self) -> PolaR { - PolaR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 13 - PWM_X Input"] - #[inline(always)] - pub fn pwmx_in(&self) -> PwmxInR { - PwmxInR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - PWM_B Input"] - #[inline(always)] - pub fn pwmb_in(&self) -> PwmbInR { - PwmbInR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - PWM_A Input"] - #[inline(always)] - pub fn pwma_in(&self) -> PwmaInR { - PwmaInR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&mut self) -> PwmxfsW { - PwmxfsW::new(self, 0) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&mut self) -> PwmbfsW { - PwmbfsW::new(self, 2) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&mut self) -> PwmafsW { - PwmafsW::new(self, 4) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&mut self) -> PolxW { - PolxW::new(self, 8) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&mut self) -> PolbW { - PolbW::new(self, 9) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&mut self) -> PolaW { - PolaW::new(self, 10) - } -} -#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2octrlSpec; -impl crate::RegisterSpec for Sm2octrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2octrl::R`](R) reader structure"] -impl crate::Readable for Sm2octrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2octrl::W`](W) writer structure"] -impl crate::Writable for Sm2octrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2OCTRL to value 0"] -impl crate::Resettable for Sm2octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2phasedly.rs b/mcxa276-pac/src/flexpwm0/sm2phasedly.rs deleted file mode 100644 index 429a1f3ce..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2phasedly.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2PHASEDLY` reader"] -pub type R = crate::R; -#[doc = "Register `SM2PHASEDLY` writer"] -pub type W = crate::W; -#[doc = "Field `PHASEDLY` reader - Initial Count Register Bits"] -pub type PhasedlyR = crate::FieldReader; -#[doc = "Field `PHASEDLY` writer - Initial Count Register Bits"] -pub type PhasedlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn phasedly(&self) -> PhasedlyR { - PhasedlyR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn phasedly(&mut self) -> PhasedlyW { - PhasedlyW::new(self, 0) - } -} -#[doc = "Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2phasedly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2phasedly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2phasedlySpec; -impl crate::RegisterSpec for Sm2phasedlySpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2phasedly::R`](R) reader structure"] -impl crate::Readable for Sm2phasedlySpec {} -#[doc = "`write(|w| ..)` method takes [`sm2phasedly::W`](W) writer structure"] -impl crate::Writable for Sm2phasedlySpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2PHASEDLY to value 0"] -impl crate::Resettable for Sm2phasedlySpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2sts.rs b/mcxa276-pac/src/flexpwm0/sm2sts.rs deleted file mode 100644 index 8700f66e1..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2sts.rs +++ /dev/null @@ -1,287 +0,0 @@ -#[doc = "Register `SM2STS` reader"] -pub type R = crate::R; -#[doc = "Register `SM2STS` writer"] -pub type W = crate::W; -#[doc = "Compare Flags\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpf { - #[doc = "0: No compare event has occurred for a particular VALx value."] - NoEvent = 0, - #[doc = "1: A compare event has occurred for a particular VALx value."] - Event = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpf { - type Ux = u8; -} -impl crate::IsEnum for Cmpf {} -#[doc = "Field `CMPF` reader - Compare Flags"] -pub type CmpfR = crate::FieldReader; -impl CmpfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpf::NoEvent), - 1 => Some(Cmpf::Event), - _ => None, - } - } - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_no_event(&self) -> bool { - *self == Cmpf::NoEvent - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_event(&self) -> bool { - *self == Cmpf::Event - } -} -#[doc = "Field `CMPF` writer - Compare Flags"] -pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; -impl<'a, REG> CmpfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn no_event(self) -> &'a mut crate::W { - self.variant(Cmpf::NoEvent) - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn event(self) -> &'a mut crate::W { - self.variant(Cmpf::Event) - } -} -#[doc = "Field `CFX0` reader - Capture Flag X0"] -pub type Cfx0R = crate::BitReader; -#[doc = "Field `CFX0` writer - Capture Flag X0"] -pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `CFX1` reader - Capture Flag X1"] -pub type Cfx1R = crate::BitReader; -#[doc = "Field `CFX1` writer - Capture Flag X1"] -pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Reload Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rf { - #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] - NoFlag = 0, - #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RF` reader - Reload Flag"] -pub type RfR = crate::BitReader; -impl RfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rf { - match self.bits { - false => Rf::NoFlag, - true => Rf::Flag, - } - } - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Rf::NoFlag - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Rf::Flag - } -} -#[doc = "Field `RF` writer - Reload Flag"] -pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; -impl<'a, REG> RfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Rf::NoFlag) - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Rf::Flag) - } -} -#[doc = "Reload Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ref { - #[doc = "0: No reload error occurred."] - NoFlag = 0, - #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ref) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REF` reader - Reload Error Flag"] -pub type RefR = crate::BitReader; -impl RefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ref { - match self.bits { - false => Ref::NoFlag, - true => Ref::Flag, - } - } - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ref::NoFlag - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ref::Flag - } -} -#[doc = "Field `REF` writer - Reload Error Flag"] -pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; -impl<'a, REG> RefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Ref::NoFlag) - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Ref::Flag) - } -} -#[doc = "Registers Updated Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ruf { - #[doc = "0: No register update has occurred since last reload."] - NoFlag = 0, - #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ruf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RUF` reader - Registers Updated Flag"] -pub type RufR = crate::BitReader; -impl RufR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ruf { - match self.bits { - false => Ruf::NoFlag, - true => Ruf::Flag, - } - } - #[doc = "No register update has occurred since last reload."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ruf::NoFlag - } - #[doc = "At least one of the double buffered registers has been updated since the last reload."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ruf::Flag - } -} -impl R { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&self) -> CmpfR { - CmpfR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&self) -> Cfx0R { - Cfx0R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&self) -> Cfx1R { - Cfx1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&self) -> RfR { - RfR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&self) -> RefR { - RefR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Registers Updated Flag"] - #[inline(always)] - pub fn ruf(&self) -> RufR { - RufR::new(((self.bits >> 14) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&mut self) -> CmpfW { - CmpfW::new(self, 0) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&mut self) -> Cfx0W { - Cfx0W::new(self, 6) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&mut self) -> Cfx1W { - Cfx1W::new(self, 7) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&mut self) -> RfW { - RfW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&mut self) -> RefW { - RefW::new(self, 13) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2stsSpec; -impl crate::RegisterSpec for Sm2stsSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2sts::R`](R) reader structure"] -impl crate::Readable for Sm2stsSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2sts::W`](W) writer structure"] -impl crate::Writable for Sm2stsSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; -} -#[doc = "`reset()` method sets SM2STS to value 0"] -impl crate::Resettable for Sm2stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2tctrl.rs b/mcxa276-pac/src/flexpwm0/sm2tctrl.rs deleted file mode 100644 index 4ebb12b79..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2tctrl.rs +++ /dev/null @@ -1,267 +0,0 @@ -#[doc = "Register `SM2TCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM2TCTRL` writer"] -pub type W = crate::W; -#[doc = "Output Trigger Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OutTrigEn { - #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - Val0 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OutTrigEn) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OutTrigEn { - type Ux = u8; -} -impl crate::IsEnum for OutTrigEn {} -#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] -pub type OutTrigEnR = crate::FieldReader; -impl OutTrigEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(OutTrigEn::Val0), - _ => None, - } - } - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == OutTrigEn::Val0 - } -} -#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] -pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; -impl<'a, REG> OutTrigEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn val0(self) -> &'a mut crate::W { - self.variant(OutTrigEn::Val0) - } -} -#[doc = "Trigger Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trgfrq { - #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Everypwm = 0, - #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Finalpwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trgfrq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] -pub type TrgfrqR = crate::BitReader; -impl TrgfrqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgfrq { - match self.bits { - false => Trgfrq::Everypwm, - true => Trgfrq::Finalpwm, - } - } - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Trgfrq::Everypwm - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_finalpwm(&self) -> bool { - *self == Trgfrq::Finalpwm - } -} -#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] -pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; -impl<'a, REG> TrgfrqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Everypwm) - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn finalpwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Finalpwm) - } -} -#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwbot1 { - #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - PwmOutTrig1Signal = 0, - #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] - PwmbOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwbot1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] -pub type Pwbot1R = crate::BitReader; -impl Pwbot1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwbot1 { - match self.bits { - false => Pwbot1::PwmOutTrig1Signal, - true => Pwbot1::PwmbOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwm_out_trig1_signal(&self) -> bool { - *self == Pwbot1::PwmOutTrig1Signal - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwmb_output(&self) -> bool { - *self == Pwbot1::PwmbOutput - } -} -#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] -pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; -impl<'a, REG> Pwbot1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmOutTrig1Signal) - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwmb_output(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmbOutput) - } -} -#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwaot0 { - #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - PwmOutTrig0Signal = 0, - #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] - PwmaOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwaot0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] -pub type Pwaot0R = crate::BitReader; -impl Pwaot0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwaot0 { - match self.bits { - false => Pwaot0::PwmOutTrig0Signal, - true => Pwaot0::PwmaOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwm_out_trig0_signal(&self) -> bool { - *self == Pwaot0::PwmOutTrig0Signal - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwma_output(&self) -> bool { - *self == Pwaot0::PwmaOutput - } -} -#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] -pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; -impl<'a, REG> Pwaot0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmOutTrig0Signal) - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwma_output(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmaOutput) - } -} -impl R { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&self) -> OutTrigEnR { - OutTrigEnR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&self) -> TrgfrqR { - TrgfrqR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&self) -> Pwbot1R { - Pwbot1R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&self) -> Pwaot0R { - Pwaot0R::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&mut self) -> OutTrigEnW { - OutTrigEnW::new(self, 0) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&mut self) -> TrgfrqW { - TrgfrqW::new(self, 12) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&mut self) -> Pwbot1W { - Pwbot1W::new(self, 14) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&mut self) -> Pwaot0W { - Pwaot0W::new(self, 15) - } -} -#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2tctrlSpec; -impl crate::RegisterSpec for Sm2tctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2tctrl::R`](R) reader structure"] -impl crate::Readable for Sm2tctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm2tctrl::W`](W) writer structure"] -impl crate::Writable for Sm2tctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2TCTRL to value 0"] -impl crate::Resettable for Sm2tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val0.rs b/mcxa276-pac/src/flexpwm0/sm2val0.rs deleted file mode 100644 index c9e859833..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2val0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2VAL0` reader"] -pub type R = crate::R; -#[doc = "Register `SM2VAL0` writer"] -pub type W = crate::W; -#[doc = "Field `VAL0` reader - Value 0"] -pub type Val0R = crate::FieldReader; -#[doc = "Field `VAL0` writer - Value 0"] -pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&self) -> Val0R { - Val0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&mut self) -> Val0W { - Val0W::new(self, 0) - } -} -#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2val0Spec; -impl crate::RegisterSpec for Sm2val0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2val0::R`](R) reader structure"] -impl crate::Readable for Sm2val0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2val0::W`](W) writer structure"] -impl crate::Writable for Sm2val0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2VAL0 to value 0"] -impl crate::Resettable for Sm2val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val1.rs b/mcxa276-pac/src/flexpwm0/sm2val1.rs deleted file mode 100644 index 9f1031bdd..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2val1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2VAL1` reader"] -pub type R = crate::R; -#[doc = "Register `SM2VAL1` writer"] -pub type W = crate::W; -#[doc = "Field `VAL1` reader - Value 1"] -pub type Val1R = crate::FieldReader; -#[doc = "Field `VAL1` writer - Value 1"] -pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&self) -> Val1R { - Val1R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&mut self) -> Val1W { - Val1W::new(self, 0) - } -} -#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2val1Spec; -impl crate::RegisterSpec for Sm2val1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2val1::R`](R) reader structure"] -impl crate::Readable for Sm2val1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2val1::W`](W) writer structure"] -impl crate::Writable for Sm2val1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2VAL1 to value 0"] -impl crate::Resettable for Sm2val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val2.rs b/mcxa276-pac/src/flexpwm0/sm2val2.rs deleted file mode 100644 index 1620ddd68..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2val2.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2VAL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM2VAL2` writer"] -pub type W = crate::W; -#[doc = "Field `VAL2` reader - Value 2"] -pub type Val2R = crate::FieldReader; -#[doc = "Field `VAL2` writer - Value 2"] -pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&self) -> Val2R { - Val2R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&mut self) -> Val2W { - Val2W::new(self, 0) - } -} -#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2val2Spec; -impl crate::RegisterSpec for Sm2val2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2val2::R`](R) reader structure"] -impl crate::Readable for Sm2val2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2val2::W`](W) writer structure"] -impl crate::Writable for Sm2val2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2VAL2 to value 0"] -impl crate::Resettable for Sm2val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val3.rs b/mcxa276-pac/src/flexpwm0/sm2val3.rs deleted file mode 100644 index 4d0f2072d..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2val3.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2VAL3` reader"] -pub type R = crate::R; -#[doc = "Register `SM2VAL3` writer"] -pub type W = crate::W; -#[doc = "Field `VAL3` reader - Value 3"] -pub type Val3R = crate::FieldReader; -#[doc = "Field `VAL3` writer - Value 3"] -pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&self) -> Val3R { - Val3R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&mut self) -> Val3W { - Val3W::new(self, 0) - } -} -#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2val3Spec; -impl crate::RegisterSpec for Sm2val3Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2val3::R`](R) reader structure"] -impl crate::Readable for Sm2val3Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2val3::W`](W) writer structure"] -impl crate::Writable for Sm2val3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2VAL3 to value 0"] -impl crate::Resettable for Sm2val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val4.rs b/mcxa276-pac/src/flexpwm0/sm2val4.rs deleted file mode 100644 index 35a962784..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2val4.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2VAL4` reader"] -pub type R = crate::R; -#[doc = "Register `SM2VAL4` writer"] -pub type W = crate::W; -#[doc = "Field `VAL4` reader - Value 4"] -pub type Val4R = crate::FieldReader; -#[doc = "Field `VAL4` writer - Value 4"] -pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&self) -> Val4R { - Val4R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&mut self) -> Val4W { - Val4W::new(self, 0) - } -} -#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2val4Spec; -impl crate::RegisterSpec for Sm2val4Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2val4::R`](R) reader structure"] -impl crate::Readable for Sm2val4Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2val4::W`](W) writer structure"] -impl crate::Writable for Sm2val4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2VAL4 to value 0"] -impl crate::Resettable for Sm2val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm2val5.rs b/mcxa276-pac/src/flexpwm0/sm2val5.rs deleted file mode 100644 index 4f570009f..000000000 --- a/mcxa276-pac/src/flexpwm0/sm2val5.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM2VAL5` reader"] -pub type R = crate::R; -#[doc = "Register `SM2VAL5` writer"] -pub type W = crate::W; -#[doc = "Field `VAL5` reader - Value 5"] -pub type Val5R = crate::FieldReader; -#[doc = "Field `VAL5` writer - Value 5"] -pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&self) -> Val5R { - Val5R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&mut self) -> Val5W { - Val5W::new(self, 0) - } -} -#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm2val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm2val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm2val5Spec; -impl crate::RegisterSpec for Sm2val5Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm2val5::R`](R) reader structure"] -impl crate::Readable for Sm2val5Spec {} -#[doc = "`write(|w| ..)` method takes [`sm2val5::W`](W) writer structure"] -impl crate::Writable for Sm2val5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM2VAL5 to value 0"] -impl crate::Resettable for Sm2val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3captcompx.rs b/mcxa276-pac/src/flexpwm0/sm3captcompx.rs deleted file mode 100644 index 62f88b8e0..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3captcompx.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `SM3CAPTCOMPX` reader"] -pub type R = crate::R; -#[doc = "Register `SM3CAPTCOMPX` writer"] -pub type W = crate::W; -#[doc = "Field `EDGCMPX` reader - Edge Compare X"] -pub type EdgcmpxR = crate::FieldReader; -#[doc = "Field `EDGCMPX` writer - Edge Compare X"] -pub type EdgcmpxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EDGCNTX` reader - Edge Counter X"] -pub type EdgcntxR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&self) -> EdgcmpxR { - EdgcmpxR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Edge Counter X"] - #[inline(always)] - pub fn edgcntx(&self) -> EdgcntxR { - EdgcntxR::new(((self.bits >> 8) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Edge Compare X"] - #[inline(always)] - pub fn edgcmpx(&mut self) -> EdgcmpxW { - EdgcmpxW::new(self, 0) - } -} -#[doc = "Capture Compare X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captcompx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captcompx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3captcompxSpec; -impl crate::RegisterSpec for Sm3captcompxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3captcompx::R`](R) reader structure"] -impl crate::Readable for Sm3captcompxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3captcompx::W`](W) writer structure"] -impl crate::Writable for Sm3captcompxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3CAPTCOMPX to value 0"] -impl crate::Resettable for Sm3captcompxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3captctrlx.rs b/mcxa276-pac/src/flexpwm0/sm3captctrlx.rs deleted file mode 100644 index dc88b9521..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3captctrlx.rs +++ /dev/null @@ -1,493 +0,0 @@ -#[doc = "Register `SM3CAPTCTRLX` reader"] -pub type R = crate::R; -#[doc = "Register `SM3CAPTCTRLX` writer"] -pub type W = crate::W; -#[doc = "Arm X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Armx { - #[doc = "0: Input capture operation is disabled."] - Disabled = 0, - #[doc = "1: Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Armx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ARMX` reader - Arm X"] -pub type ArmxR = crate::BitReader; -impl ArmxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Armx { - match self.bits { - false => Armx::Disabled, - true => Armx::Enabled, - } - } - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Armx::Disabled - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Armx::Enabled - } -} -#[doc = "Field `ARMX` writer - Arm X"] -pub type ArmxW<'a, REG> = crate::BitWriter<'a, REG, Armx>; -impl<'a, REG> ArmxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input capture operation is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Armx::Disabled) - } - #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Armx::Enabled) - } -} -#[doc = "One Shot Mode Aux\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Oneshotx { - #[doc = "0: Free Running"] - FreeRunning = 0, - #[doc = "1: One Shot"] - OneShot = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Oneshotx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONESHOTX` reader - One Shot Mode Aux"] -pub type OneshotxR = crate::BitReader; -impl OneshotxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Oneshotx { - match self.bits { - false => Oneshotx::FreeRunning, - true => Oneshotx::OneShot, - } - } - #[doc = "Free Running"] - #[inline(always)] - pub fn is_free_running(&self) -> bool { - *self == Oneshotx::FreeRunning - } - #[doc = "One Shot"] - #[inline(always)] - pub fn is_one_shot(&self) -> bool { - *self == Oneshotx::OneShot - } -} -#[doc = "Field `ONESHOTX` writer - One Shot Mode Aux"] -pub type OneshotxW<'a, REG> = crate::BitWriter<'a, REG, Oneshotx>; -impl<'a, REG> OneshotxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Free Running"] - #[inline(always)] - pub fn free_running(self) -> &'a mut crate::W { - self.variant(Oneshotx::FreeRunning) - } - #[doc = "One Shot"] - #[inline(always)] - pub fn one_shot(self) -> &'a mut crate::W { - self.variant(Oneshotx::OneShot) - } -} -#[doc = "Edge X 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx0 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx0 { - type Ux = u8; -} -impl crate::IsEnum for Edgx0 {} -#[doc = "Field `EDGX0` reader - Edge X 0"] -pub type Edgx0R = crate::FieldReader; -impl Edgx0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx0 { - match self.bits { - 0 => Edgx0::Disabled, - 1 => Edgx0::FallingEdge, - 2 => Edgx0::RisingEdge, - 3 => Edgx0::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx0::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx0::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx0::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx0::AnyEdge - } -} -#[doc = "Field `EDGX0` writer - Edge X 0"] -pub type Edgx0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx0, crate::Safe>; -impl<'a, REG> Edgx0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx0::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx0::AnyEdge) - } -} -#[doc = "Edge X 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Edgx1 { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Capture falling edges"] - FallingEdge = 1, - #[doc = "2: Capture rising edges"] - RisingEdge = 2, - #[doc = "3: Capture any edge"] - AnyEdge = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Edgx1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Edgx1 { - type Ux = u8; -} -impl crate::IsEnum for Edgx1 {} -#[doc = "Field `EDGX1` reader - Edge X 1"] -pub type Edgx1R = crate::FieldReader; -impl Edgx1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Edgx1 { - match self.bits { - 0 => Edgx1::Disabled, - 1 => Edgx1::FallingEdge, - 2 => Edgx1::RisingEdge, - 3 => Edgx1::AnyEdge, - _ => unreachable!(), - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Edgx1::Disabled - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn is_falling_edge(&self) -> bool { - *self == Edgx1::FallingEdge - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn is_rising_edge(&self) -> bool { - *self == Edgx1::RisingEdge - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn is_any_edge(&self) -> bool { - *self == Edgx1::AnyEdge - } -} -#[doc = "Field `EDGX1` writer - Edge X 1"] -pub type Edgx1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Edgx1, crate::Safe>; -impl<'a, REG> Edgx1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Edgx1::Disabled) - } - #[doc = "Capture falling edges"] - #[inline(always)] - pub fn falling_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::FallingEdge) - } - #[doc = "Capture rising edges"] - #[inline(always)] - pub fn rising_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::RisingEdge) - } - #[doc = "Capture any edge"] - #[inline(always)] - pub fn any_edge(self) -> &'a mut crate::W { - self.variant(Edgx1::AnyEdge) - } -} -#[doc = "Input Select X\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum InpSelx { - #[doc = "0: Raw PWM_X input signal selected as source."] - PwmX = 0, - #[doc = "1: Edge Counter"] - EdgeCounter = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: InpSelx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INP_SELX` reader - Input Select X"] -pub type InpSelxR = crate::BitReader; -impl InpSelxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InpSelx { - match self.bits { - false => InpSelx::PwmX, - true => InpSelx::EdgeCounter, - } - } - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InpSelx::PwmX - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn is_edge_counter(&self) -> bool { - *self == InpSelx::EdgeCounter - } -} -#[doc = "Field `INP_SELX` writer - Input Select X"] -pub type InpSelxW<'a, REG> = crate::BitWriter<'a, REG, InpSelx>; -impl<'a, REG> InpSelxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Raw PWM_X input signal selected as source."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InpSelx::PwmX) - } - #[doc = "Edge Counter"] - #[inline(always)] - pub fn edge_counter(self) -> &'a mut crate::W { - self.variant(InpSelx::EdgeCounter) - } -} -#[doc = "Edge Counter X Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EdgcntxEn { - #[doc = "0: Edge counter disabled and held in reset"] - Disabled = 0, - #[doc = "1: Edge counter enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EdgcntxEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EDGCNTX_EN` reader - Edge Counter X Enable"] -pub type EdgcntxEnR = crate::BitReader; -impl EdgcntxEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EdgcntxEn { - match self.bits { - false => EdgcntxEn::Disabled, - true => EdgcntxEn::Enabled, - } - } - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == EdgcntxEn::Disabled - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == EdgcntxEn::Enabled - } -} -#[doc = "Field `EDGCNTX_EN` writer - Edge Counter X Enable"] -pub type EdgcntxEnW<'a, REG> = crate::BitWriter<'a, REG, EdgcntxEn>; -impl<'a, REG> EdgcntxEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Edge counter disabled and held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Disabled) - } - #[doc = "Edge counter enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(EdgcntxEn::Enabled) - } -} -#[doc = "Field `CFXWM` reader - Capture X FIFOs Water Mark"] -pub type CfxwmR = crate::FieldReader; -#[doc = "Field `CFXWM` writer - Capture X FIFOs Water Mark"] -pub type CfxwmW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `CX0CNT` reader - Capture X0 FIFO Word Count"] -pub type Cx0cntR = crate::FieldReader; -#[doc = "Field `CX1CNT` reader - Capture X1 FIFO Word Count"] -pub type Cx1cntR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&self) -> ArmxR { - ArmxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&self) -> OneshotxR { - OneshotxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&self) -> Edgx0R { - Edgx0R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&self) -> Edgx1R { - Edgx1R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&self) -> InpSelxR { - InpSelxR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&self) -> EdgcntxEnR { - EdgcntxEnR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&self) -> CfxwmR { - CfxwmR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:12 - Capture X0 FIFO Word Count"] - #[inline(always)] - pub fn cx0cnt(&self) -> Cx0cntR { - Cx0cntR::new(((self.bits >> 10) & 7) as u8) - } - #[doc = "Bits 13:15 - Capture X1 FIFO Word Count"] - #[inline(always)] - pub fn cx1cnt(&self) -> Cx1cntR { - Cx1cntR::new(((self.bits >> 13) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Arm X"] - #[inline(always)] - pub fn armx(&mut self) -> ArmxW { - ArmxW::new(self, 0) - } - #[doc = "Bit 1 - One Shot Mode Aux"] - #[inline(always)] - pub fn oneshotx(&mut self) -> OneshotxW { - OneshotxW::new(self, 1) - } - #[doc = "Bits 2:3 - Edge X 0"] - #[inline(always)] - pub fn edgx0(&mut self) -> Edgx0W { - Edgx0W::new(self, 2) - } - #[doc = "Bits 4:5 - Edge X 1"] - #[inline(always)] - pub fn edgx1(&mut self) -> Edgx1W { - Edgx1W::new(self, 4) - } - #[doc = "Bit 6 - Input Select X"] - #[inline(always)] - pub fn inp_selx(&mut self) -> InpSelxW { - InpSelxW::new(self, 6) - } - #[doc = "Bit 7 - Edge Counter X Enable"] - #[inline(always)] - pub fn edgcntx_en(&mut self) -> EdgcntxEnW { - EdgcntxEnW::new(self, 7) - } - #[doc = "Bits 8:9 - Capture X FIFOs Water Mark"] - #[inline(always)] - pub fn cfxwm(&mut self) -> CfxwmW { - CfxwmW::new(self, 8) - } -} -#[doc = "Capture Control X Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captctrlx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captctrlx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3captctrlxSpec; -impl crate::RegisterSpec for Sm3captctrlxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3captctrlx::R`](R) reader structure"] -impl crate::Readable for Sm3captctrlxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3captctrlx::W`](W) writer structure"] -impl crate::Writable for Sm3captctrlxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3CAPTCTRLX to value 0"] -impl crate::Resettable for Sm3captctrlxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3captfiltx.rs b/mcxa276-pac/src/flexpwm0/sm3captfiltx.rs deleted file mode 100644 index 4cb5c4899..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3captfiltx.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `SM3CAPTFILTX` reader"] -pub type R = crate::R; -#[doc = "Register `SM3CAPTFILTX` writer"] -pub type W = crate::W; -#[doc = "Field `CAPTX_FILT_PER` reader - Input Capture Filter Period"] -pub type CaptxFiltPerR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_PER` writer - Input Capture Filter Period"] -pub type CaptxFiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `CAPTX_FILT_CNT` reader - Input Capture Filter Count"] -pub type CaptxFiltCntR = crate::FieldReader; -#[doc = "Field `CAPTX_FILT_CNT` writer - Input Capture Filter Count"] -pub type CaptxFiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&self) -> CaptxFiltPerR { - CaptxFiltPerR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&self) -> CaptxFiltCntR { - CaptxFiltCntR::new(((self.bits >> 8) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Input Capture Filter Period"] - #[inline(always)] - pub fn captx_filt_per(&mut self) -> CaptxFiltPerW { - CaptxFiltPerW::new(self, 0) - } - #[doc = "Bits 8:10 - Input Capture Filter Count"] - #[inline(always)] - pub fn captx_filt_cnt(&mut self) -> CaptxFiltCntW { - CaptxFiltCntW::new(self, 8) - } -} -#[doc = "Capture PWM_X Input Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3captfiltx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3captfiltx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3captfiltxSpec; -impl crate::RegisterSpec for Sm3captfiltxSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3captfiltx::R`](R) reader structure"] -impl crate::Readable for Sm3captfiltxSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3captfiltx::W`](W) writer structure"] -impl crate::Writable for Sm3captfiltxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3CAPTFILTX to value 0"] -impl crate::Resettable for Sm3captfiltxSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cnt.rs b/mcxa276-pac/src/flexpwm0/sm3cnt.rs deleted file mode 100644 index 14c00cbf3..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3cnt.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM3CNT` reader"] -pub type R = crate::R; -#[doc = "Field `CNT` reader - Counter Register Bits"] -pub type CntR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Counter Register Bits"] - #[inline(always)] - pub fn cnt(&self) -> CntR { - CntR::new(self.bits) - } -} -#[doc = "Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3cntSpec; -impl crate::RegisterSpec for Sm3cntSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3cnt::R`](R) reader structure"] -impl crate::Readable for Sm3cntSpec {} -#[doc = "`reset()` method sets SM3CNT to value 0"] -impl crate::Resettable for Sm3cntSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3ctrl.rs b/mcxa276-pac/src/flexpwm0/sm3ctrl.rs deleted file mode 100644 index 832674137..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3ctrl.rs +++ /dev/null @@ -1,871 +0,0 @@ -#[doc = "Register `SM3CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM3CTRL` writer"] -pub type W = crate::W; -#[doc = "Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblen { - #[doc = "0: Double switching disabled."] - Disabled = 0, - #[doc = "1: Double switching enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLEN` reader - Double Switching Enable"] -pub type DblenR = crate::BitReader; -impl DblenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblen { - match self.bits { - false => Dblen::Disabled, - true => Dblen::Enabled, - } - } - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblen::Disabled - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblen::Enabled - } -} -#[doc = "Field `DBLEN` writer - Double Switching Enable"] -pub type DblenW<'a, REG> = crate::BitWriter<'a, REG, Dblen>; -impl<'a, REG> DblenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Double switching disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblen::Disabled) - } - #[doc = "Double switching enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblen::Enabled) - } -} -#[doc = "PWM_X Double Switching Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dblx { - #[doc = "0: PWM_X double pulse disabled."] - Disabled = 0, - #[doc = "1: PWM_X double pulse enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dblx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBLX` reader - PWM_X Double Switching Enable"] -pub type DblxR = crate::BitReader; -impl DblxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dblx { - match self.bits { - false => Dblx::Disabled, - true => Dblx::Enabled, - } - } - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dblx::Disabled - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dblx::Enabled - } -} -#[doc = "Field `DBLX` writer - PWM_X Double Switching Enable"] -pub type DblxW<'a, REG> = crate::BitWriter<'a, REG, Dblx>; -impl<'a, REG> DblxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X double pulse disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dblx::Disabled) - } - #[doc = "PWM_X double pulse enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dblx::Enabled) - } -} -#[doc = "Load Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldmod { - #[doc = "0: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - NextPwmReload = 0, - #[doc = "1: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - MtctrlLdokSet = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldmod) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDMOD` reader - Load Mode Select"] -pub type LdmodR = crate::BitReader; -impl LdmodR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldmod { - match self.bits { - false => Ldmod::NextPwmReload, - true => Ldmod::MtctrlLdokSet, - } - } - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn is_next_pwm_reload(&self) -> bool { - *self == Ldmod::NextPwmReload - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn is_mtctrl_ldok_set(&self) -> bool { - *self == Ldmod::MtctrlLdokSet - } -} -#[doc = "Field `LDMOD` writer - Load Mode Select"] -pub type LdmodW<'a, REG> = crate::BitWriter<'a, REG, Ldmod>; -impl<'a, REG> LdmodW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - #[inline(always)] - pub fn next_pwm_reload(self) -> &'a mut crate::W { - self.variant(Ldmod::NextPwmReload) - } - #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - #[inline(always)] - pub fn mtctrl_ldok_set(self) -> &'a mut crate::W { - self.variant(Ldmod::MtctrlLdokSet) - } -} -#[doc = "Split the DBLPWM signal to PWM_A and PWM_B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Split { - #[doc = "0: DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - Disabled = 0, - #[doc = "1: DBLPWM is split to PWM_A and PWM_B."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Split) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLIT` reader - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitR = crate::BitReader; -impl SplitR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Split { - match self.bits { - false => Split::Disabled, - true => Split::Enabled, - } - } - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Split::Disabled - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Split::Enabled - } -} -#[doc = "Field `SPLIT` writer - Split the DBLPWM signal to PWM_A and PWM_B"] -pub type SplitW<'a, REG> = crate::BitWriter<'a, REG, Split>; -impl<'a, REG> SplitW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DBLPWM is not split. PWM_A and PWM_B each have double pulses."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Split::Disabled) - } - #[doc = "DBLPWM is split to PWM_A and PWM_B."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Split::Enabled) - } -} -#[doc = "Prescaler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Prsc { - #[doc = "0: Prescaler 1"] - One = 0, - #[doc = "1: Prescaler 2"] - Two = 1, - #[doc = "2: Prescaler 4"] - Four = 2, - #[doc = "3: Prescaler 8"] - Eight = 3, - #[doc = "4: Prescaler 16"] - Sixteen = 4, - #[doc = "5: Prescaler 32"] - Thirtytwo = 5, - #[doc = "6: Prescaler 64"] - Sixtyfour = 6, - #[doc = "7: Prescaler 128"] - Hundredtwentyeight = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Prsc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Prsc { - type Ux = u8; -} -impl crate::IsEnum for Prsc {} -#[doc = "Field `PRSC` reader - Prescaler"] -pub type PrscR = crate::FieldReader; -impl PrscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prsc { - match self.bits { - 0 => Prsc::One, - 1 => Prsc::Two, - 2 => Prsc::Four, - 3 => Prsc::Eight, - 4 => Prsc::Sixteen, - 5 => Prsc::Thirtytwo, - 6 => Prsc::Sixtyfour, - 7 => Prsc::Hundredtwentyeight, - _ => unreachable!(), - } - } - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Prsc::One - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn is_two(&self) -> bool { - *self == Prsc::Two - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn is_four(&self) -> bool { - *self == Prsc::Four - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn is_eight(&self) -> bool { - *self == Prsc::Eight - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn is_sixteen(&self) -> bool { - *self == Prsc::Sixteen - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn is_thirtytwo(&self) -> bool { - *self == Prsc::Thirtytwo - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn is_sixtyfour(&self) -> bool { - *self == Prsc::Sixtyfour - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn is_hundredtwentyeight(&self) -> bool { - *self == Prsc::Hundredtwentyeight - } -} -#[doc = "Field `PRSC` writer - Prescaler"] -pub type PrscW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prsc, crate::Safe>; -impl<'a, REG> PrscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Prescaler 1"] - #[inline(always)] - pub fn one(self) -> &'a mut crate::W { - self.variant(Prsc::One) - } - #[doc = "Prescaler 2"] - #[inline(always)] - pub fn two(self) -> &'a mut crate::W { - self.variant(Prsc::Two) - } - #[doc = "Prescaler 4"] - #[inline(always)] - pub fn four(self) -> &'a mut crate::W { - self.variant(Prsc::Four) - } - #[doc = "Prescaler 8"] - #[inline(always)] - pub fn eight(self) -> &'a mut crate::W { - self.variant(Prsc::Eight) - } - #[doc = "Prescaler 16"] - #[inline(always)] - pub fn sixteen(self) -> &'a mut crate::W { - self.variant(Prsc::Sixteen) - } - #[doc = "Prescaler 32"] - #[inline(always)] - pub fn thirtytwo(self) -> &'a mut crate::W { - self.variant(Prsc::Thirtytwo) - } - #[doc = "Prescaler 64"] - #[inline(always)] - pub fn sixtyfour(self) -> &'a mut crate::W { - self.variant(Prsc::Sixtyfour) - } - #[doc = "Prescaler 128"] - #[inline(always)] - pub fn hundredtwentyeight(self) -> &'a mut crate::W { - self.variant(Prsc::Hundredtwentyeight) - } -} -#[doc = "Compare Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Compmode { - #[doc = "0: The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - EqualTo = 0, - #[doc = "1: The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - EqualToOrGreaterThan = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Compmode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPMODE` reader - Compare Mode"] -pub type CompmodeR = crate::BitReader; -impl CompmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Compmode { - match self.bits { - false => Compmode::EqualTo, - true => Compmode::EqualToOrGreaterThan, - } - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn is_equal_to(&self) -> bool { - *self == Compmode::EqualTo - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn is_equal_to_or_greater_than(&self) -> bool { - *self == Compmode::EqualToOrGreaterThan - } -} -#[doc = "Field `COMPMODE` writer - Compare Mode"] -pub type CompmodeW<'a, REG> = crate::BitWriter<'a, REG, Compmode>; -impl<'a, REG> CompmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - #[inline(always)] - pub fn equal_to(self) -> &'a mut crate::W { - self.variant(Compmode::EqualTo) - } - #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - #[inline(always)] - pub fn equal_to_or_greater_than(self) -> &'a mut crate::W { - self.variant(Compmode::EqualToOrGreaterThan) - } -} -#[doc = "Field `DT` reader - Deadtime"] -pub type DtR = crate::FieldReader; -#[doc = "Full Cycle Reload\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Full { - #[doc = "0: Full-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Full-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FULL` reader - Full Cycle Reload"] -pub type FullR = crate::BitReader; -impl FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Full { - match self.bits { - false => Full::Disabled, - true => Full::Enabled, - } - } - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Full::Disabled - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Full::Enabled - } -} -#[doc = "Field `FULL` writer - Full Cycle Reload"] -pub type FullW<'a, REG> = crate::BitWriter<'a, REG, Full>; -impl<'a, REG> FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Full-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Full::Disabled) - } - #[doc = "Full-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Full::Enabled) - } -} -#[doc = "Half Cycle Reload\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Half { - #[doc = "0: Half-cycle reloads disabled."] - Disabled = 0, - #[doc = "1: Half-cycle reloads enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Half) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALF` reader - Half Cycle Reload"] -pub type HalfR = crate::BitReader; -impl HalfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Half { - match self.bits { - false => Half::Disabled, - true => Half::Enabled, - } - } - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Half::Disabled - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Half::Enabled - } -} -#[doc = "Field `HALF` writer - Half Cycle Reload"] -pub type HalfW<'a, REG> = crate::BitWriter<'a, REG, Half>; -impl<'a, REG> HalfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Half-cycle reloads disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Half::Disabled) - } - #[doc = "Half-cycle reloads enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Half::Enabled) - } -} -#[doc = "Load Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ldfq { - #[doc = "0: Every PWM opportunity"] - Everypwm = 0, - #[doc = "1: Every 2 PWM opportunities"] - Every2pwm = 1, - #[doc = "2: Every 3 PWM opportunities"] - Every3pwm = 2, - #[doc = "3: Every 4 PWM opportunities"] - Every4pwm = 3, - #[doc = "4: Every 5 PWM opportunities"] - Every5pwm = 4, - #[doc = "5: Every 6 PWM opportunities"] - Every6pwm = 5, - #[doc = "6: Every 7 PWM opportunities"] - Every7pwm = 6, - #[doc = "7: Every 8 PWM opportunities"] - Every8pwm = 7, - #[doc = "8: Every 9 PWM opportunities"] - Every9pwm = 8, - #[doc = "9: Every 10 PWM opportunities"] - Every10pwm = 9, - #[doc = "10: Every 11 PWM opportunities"] - Every11pwm = 10, - #[doc = "11: Every 12 PWM opportunities"] - Every12pwm = 11, - #[doc = "12: Every 13 PWM opportunities"] - Every13pwm = 12, - #[doc = "13: Every 14 PWM opportunities"] - Every14pwm = 13, - #[doc = "14: Every 15 PWM opportunities"] - Every15pwm = 14, - #[doc = "15: Every 16 PWM opportunities"] - Every16pwm = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ldfq) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ldfq { - type Ux = u8; -} -impl crate::IsEnum for Ldfq {} -#[doc = "Field `LDFQ` reader - Load Frequency"] -pub type LdfqR = crate::FieldReader; -impl LdfqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldfq { - match self.bits { - 0 => Ldfq::Everypwm, - 1 => Ldfq::Every2pwm, - 2 => Ldfq::Every3pwm, - 3 => Ldfq::Every4pwm, - 4 => Ldfq::Every5pwm, - 5 => Ldfq::Every6pwm, - 6 => Ldfq::Every7pwm, - 7 => Ldfq::Every8pwm, - 8 => Ldfq::Every9pwm, - 9 => Ldfq::Every10pwm, - 10 => Ldfq::Every11pwm, - 11 => Ldfq::Every12pwm, - 12 => Ldfq::Every13pwm, - 13 => Ldfq::Every14pwm, - 14 => Ldfq::Every15pwm, - 15 => Ldfq::Every16pwm, - _ => unreachable!(), - } - } - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Ldfq::Everypwm - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn is_every2pwm(&self) -> bool { - *self == Ldfq::Every2pwm - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn is_every3pwm(&self) -> bool { - *self == Ldfq::Every3pwm - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn is_every4pwm(&self) -> bool { - *self == Ldfq::Every4pwm - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn is_every5pwm(&self) -> bool { - *self == Ldfq::Every5pwm - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn is_every6pwm(&self) -> bool { - *self == Ldfq::Every6pwm - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn is_every7pwm(&self) -> bool { - *self == Ldfq::Every7pwm - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn is_every8pwm(&self) -> bool { - *self == Ldfq::Every8pwm - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn is_every9pwm(&self) -> bool { - *self == Ldfq::Every9pwm - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn is_every10pwm(&self) -> bool { - *self == Ldfq::Every10pwm - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn is_every11pwm(&self) -> bool { - *self == Ldfq::Every11pwm - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn is_every12pwm(&self) -> bool { - *self == Ldfq::Every12pwm - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn is_every13pwm(&self) -> bool { - *self == Ldfq::Every13pwm - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn is_every14pwm(&self) -> bool { - *self == Ldfq::Every14pwm - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn is_every15pwm(&self) -> bool { - *self == Ldfq::Every15pwm - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn is_every16pwm(&self) -> bool { - *self == Ldfq::Every16pwm - } -} -#[doc = "Field `LDFQ` writer - Load Frequency"] -pub type LdfqW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ldfq, crate::Safe>; -impl<'a, REG> LdfqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Every PWM opportunity"] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Everypwm) - } - #[doc = "Every 2 PWM opportunities"] - #[inline(always)] - pub fn every2pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every2pwm) - } - #[doc = "Every 3 PWM opportunities"] - #[inline(always)] - pub fn every3pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every3pwm) - } - #[doc = "Every 4 PWM opportunities"] - #[inline(always)] - pub fn every4pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every4pwm) - } - #[doc = "Every 5 PWM opportunities"] - #[inline(always)] - pub fn every5pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every5pwm) - } - #[doc = "Every 6 PWM opportunities"] - #[inline(always)] - pub fn every6pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every6pwm) - } - #[doc = "Every 7 PWM opportunities"] - #[inline(always)] - pub fn every7pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every7pwm) - } - #[doc = "Every 8 PWM opportunities"] - #[inline(always)] - pub fn every8pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every8pwm) - } - #[doc = "Every 9 PWM opportunities"] - #[inline(always)] - pub fn every9pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every9pwm) - } - #[doc = "Every 10 PWM opportunities"] - #[inline(always)] - pub fn every10pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every10pwm) - } - #[doc = "Every 11 PWM opportunities"] - #[inline(always)] - pub fn every11pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every11pwm) - } - #[doc = "Every 12 PWM opportunities"] - #[inline(always)] - pub fn every12pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every12pwm) - } - #[doc = "Every 13 PWM opportunities"] - #[inline(always)] - pub fn every13pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every13pwm) - } - #[doc = "Every 14 PWM opportunities"] - #[inline(always)] - pub fn every14pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every14pwm) - } - #[doc = "Every 15 PWM opportunities"] - #[inline(always)] - pub fn every15pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every15pwm) - } - #[doc = "Every 16 PWM opportunities"] - #[inline(always)] - pub fn every16pwm(self) -> &'a mut crate::W { - self.variant(Ldfq::Every16pwm) - } -} -impl R { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&self) -> DblenR { - DblenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&self) -> DblxR { - DblxR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&self) -> LdmodR { - LdmodR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&self) -> SplitR { - SplitR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&self) -> PrscR { - PrscR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&self) -> CompmodeR { - CompmodeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Deadtime"] - #[inline(always)] - pub fn dt(&self) -> DtR { - DtR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&self) -> FullR { - FullR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&self) -> HalfR { - HalfR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&self) -> LdfqR { - LdfqR::new(((self.bits >> 12) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Double Switching Enable"] - #[inline(always)] - pub fn dblen(&mut self) -> DblenW { - DblenW::new(self, 0) - } - #[doc = "Bit 1 - PWM_X Double Switching Enable"] - #[inline(always)] - pub fn dblx(&mut self) -> DblxW { - DblxW::new(self, 1) - } - #[doc = "Bit 2 - Load Mode Select"] - #[inline(always)] - pub fn ldmod(&mut self) -> LdmodW { - LdmodW::new(self, 2) - } - #[doc = "Bit 3 - Split the DBLPWM signal to PWM_A and PWM_B"] - #[inline(always)] - pub fn split(&mut self) -> SplitW { - SplitW::new(self, 3) - } - #[doc = "Bits 4:6 - Prescaler"] - #[inline(always)] - pub fn prsc(&mut self) -> PrscW { - PrscW::new(self, 4) - } - #[doc = "Bit 7 - Compare Mode"] - #[inline(always)] - pub fn compmode(&mut self) -> CompmodeW { - CompmodeW::new(self, 7) - } - #[doc = "Bit 10 - Full Cycle Reload"] - #[inline(always)] - pub fn full(&mut self) -> FullW { - FullW::new(self, 10) - } - #[doc = "Bit 11 - Half Cycle Reload"] - #[inline(always)] - pub fn half(&mut self) -> HalfW { - HalfW::new(self, 11) - } - #[doc = "Bits 12:15 - Load Frequency"] - #[inline(always)] - pub fn ldfq(&mut self) -> LdfqW { - LdfqW::new(self, 12) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3ctrlSpec; -impl crate::RegisterSpec for Sm3ctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3ctrl::R`](R) reader structure"] -impl crate::Readable for Sm3ctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3ctrl::W`](W) writer structure"] -impl crate::Writable for Sm3ctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3CTRL to value 0x0400"] -impl crate::Resettable for Sm3ctrlSpec { - const RESET_VALUE: u16 = 0x0400; -} diff --git a/mcxa276-pac/src/flexpwm0/sm3ctrl2.rs b/mcxa276-pac/src/flexpwm0/sm3ctrl2.rs deleted file mode 100644 index 22721e058..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3ctrl2.rs +++ /dev/null @@ -1,607 +0,0 @@ -#[doc = "Register `SM3CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM3CTRL2` writer"] -pub type W = crate::W; -#[doc = "Clock Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ClkSel { - #[doc = "0: The IPBus clock is used as the clock for the local prescaler and counter."] - Ipbus = 0, - #[doc = "1: EXT_CLK is used as the clock for the local prescaler and counter."] - ExtClk = 1, - #[doc = "2: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - AuxClk = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ClkSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ClkSel { - type Ux = u8; -} -impl crate::IsEnum for ClkSel {} -#[doc = "Field `CLK_SEL` reader - Clock Source Select"] -pub type ClkSelR = crate::FieldReader; -impl ClkSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(ClkSel::Ipbus), - 1 => Some(ClkSel::ExtClk), - 2 => Some(ClkSel::AuxClk), - _ => None, - } - } - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ipbus(&self) -> bool { - *self == ClkSel::Ipbus - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn is_ext_clk(&self) -> bool { - *self == ClkSel::ExtClk - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn is_aux_clk(&self) -> bool { - *self == ClkSel::AuxClk - } -} -#[doc = "Field `CLK_SEL` writer - Clock Source Select"] -pub type ClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSel>; -impl<'a, REG> ClkSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ipbus(self) -> &'a mut crate::W { - self.variant(ClkSel::Ipbus) - } - #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - #[inline(always)] - pub fn ext_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::ExtClk) - } - #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - #[inline(always)] - pub fn aux_clk(self) -> &'a mut crate::W { - self.variant(ClkSel::AuxClk) - } -} -#[doc = "Reload Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ReloadSel { - #[doc = "0: The local RELOAD signal is used to reload registers."] - Local = 0, - #[doc = "1: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - Master = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ReloadSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RELOAD_SEL` reader - Reload Source Select"] -pub type ReloadSelR = crate::BitReader; -impl ReloadSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ReloadSel { - match self.bits { - false => ReloadSel::Local, - true => ReloadSel::Master, - } - } - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ReloadSel::Local - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ReloadSel::Master - } -} -#[doc = "Field `RELOAD_SEL` writer - Reload Source Select"] -pub type ReloadSelW<'a, REG> = crate::BitWriter<'a, REG, ReloadSel>; -impl<'a, REG> ReloadSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The local RELOAD signal is used to reload registers."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ReloadSel::Local) - } - #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ReloadSel::Master) - } -} -#[doc = "Force Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ForceSel { - #[doc = "0: The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - Local = 0, - #[doc = "1: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - Master = 1, - #[doc = "2: The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - LocalReload = 2, - #[doc = "3: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterReload = 3, - #[doc = "4: The local sync signal from this submodule is used to force updates."] - LocalSync = 4, - #[doc = "5: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MasterSync = 5, - #[doc = "6: The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - ExtForce = 6, - #[doc = "7: The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - ExtSync = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ForceSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ForceSel { - type Ux = u8; -} -impl crate::IsEnum for ForceSel {} -#[doc = "Field `FORCE_SEL` reader - Force Select"] -pub type ForceSelR = crate::FieldReader; -impl ForceSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ForceSel { - match self.bits { - 0 => ForceSel::Local, - 1 => ForceSel::Master, - 2 => ForceSel::LocalReload, - 3 => ForceSel::MasterReload, - 4 => ForceSel::LocalSync, - 5 => ForceSel::MasterSync, - 6 => ForceSel::ExtForce, - 7 => ForceSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local(&self) -> bool { - *self == ForceSel::Local - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == ForceSel::Master - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == ForceSel::LocalReload - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == ForceSel::MasterReload - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == ForceSel::LocalSync - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == ForceSel::MasterSync - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_force(&self) -> bool { - *self == ForceSel::ExtForce - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == ForceSel::ExtSync - } -} -#[doc = "Field `FORCE_SEL` writer - Force Select"] -pub type ForceSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, ForceSel, crate::Safe>; -impl<'a, REG> ForceSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - #[inline(always)] - pub fn local(self) -> &'a mut crate::W { - self.variant(ForceSel::Local) - } - #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(ForceSel::Master) - } - #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalReload) - } - #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterReload) - } - #[doc = "The local sync signal from this submodule is used to force updates."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::LocalSync) - } - #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::MasterSync) - } - #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_force(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtForce) - } - #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(ForceSel::ExtSync) - } -} -#[doc = "Field `FORCE` reader - Force Initialization"] -pub type ForceR = crate::BitReader; -#[doc = "Field `FORCE` writer - Force Initialization"] -pub type ForceW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Force Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frcen { - #[doc = "0: Initialization from a FORCE_OUT is disabled."] - Disabled = 0, - #[doc = "1: Initialization from a FORCE_OUT is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRCEN` reader - Force Enable"] -pub type FrcenR = crate::BitReader; -impl FrcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frcen { - match self.bits { - false => Frcen::Disabled, - true => Frcen::Enabled, - } - } - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Frcen::Disabled - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Frcen::Enabled - } -} -#[doc = "Field `FRCEN` writer - Force Enable"] -pub type FrcenW<'a, REG> = crate::BitWriter<'a, REG, Frcen>; -impl<'a, REG> FrcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Initialization from a FORCE_OUT is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Frcen::Disabled) - } - #[doc = "Initialization from a FORCE_OUT is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Frcen::Enabled) - } -} -#[doc = "Initialization Control Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum InitSel { - #[doc = "0: Local sync (PWM_X) causes initialization."] - PwmX = 0, - #[doc = "1: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - MasterReload = 1, - #[doc = "2: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - MasterSync = 2, - #[doc = "3: EXT_SYNC causes initialization."] - ExtSync = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: InitSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for InitSel { - type Ux = u8; -} -impl crate::IsEnum for InitSel {} -#[doc = "Field `INIT_SEL` reader - Initialization Control Select"] -pub type InitSelR = crate::FieldReader; -impl InitSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> InitSel { - match self.bits { - 0 => InitSel::PwmX, - 1 => InitSel::MasterReload, - 2 => InitSel::MasterSync, - 3 => InitSel::ExtSync, - _ => unreachable!(), - } - } - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn is_pwm_x(&self) -> bool { - *self == InitSel::PwmX - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn is_master_reload(&self) -> bool { - *self == InitSel::MasterReload - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn is_master_sync(&self) -> bool { - *self == InitSel::MasterSync - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn is_ext_sync(&self) -> bool { - *self == InitSel::ExtSync - } -} -#[doc = "Field `INIT_SEL` writer - Initialization Control Select"] -pub type InitSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InitSel, crate::Safe>; -impl<'a, REG> InitSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Local sync (PWM_X) causes initialization."] - #[inline(always)] - pub fn pwm_x(self) -> &'a mut crate::W { - self.variant(InitSel::PwmX) - } - #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - #[inline(always)] - pub fn master_reload(self) -> &'a mut crate::W { - self.variant(InitSel::MasterReload) - } - #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - #[inline(always)] - pub fn master_sync(self) -> &'a mut crate::W { - self.variant(InitSel::MasterSync) - } - #[doc = "EXT_SYNC causes initialization."] - #[inline(always)] - pub fn ext_sync(self) -> &'a mut crate::W { - self.variant(InitSel::ExtSync) - } -} -#[doc = "Field `PWMX_INIT` reader - PWM_X Initial Value"] -pub type PwmxInitR = crate::BitReader; -#[doc = "Field `PWMX_INIT` writer - PWM_X Initial Value"] -pub type PwmxInitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM45_INIT` reader - PWM45 Initial Value"] -pub type Pwm45InitR = crate::BitReader; -#[doc = "Field `PWM45_INIT` writer - PWM45 Initial Value"] -pub type Pwm45InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PWM23_INIT` reader - PWM23 Initial Value"] -pub type Pwm23InitR = crate::BitReader; -#[doc = "Field `PWM23_INIT` writer - PWM23 Initial Value"] -pub type Pwm23InitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Independent or Complementary Pair Operation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Indep { - #[doc = "0: PWM_A and PWM_B form a complementary PWM pair."] - Complementary = 0, - #[doc = "1: PWM_A and PWM_B outputs are independent PWMs."] - Independent = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Indep) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INDEP` reader - Independent or Complementary Pair Operation"] -pub type IndepR = crate::BitReader; -impl IndepR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Indep { - match self.bits { - false => Indep::Complementary, - true => Indep::Independent, - } - } - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn is_complementary(&self) -> bool { - *self == Indep::Complementary - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn is_independent(&self) -> bool { - *self == Indep::Independent - } -} -#[doc = "Field `INDEP` writer - Independent or Complementary Pair Operation"] -pub type IndepW<'a, REG> = crate::BitWriter<'a, REG, Indep>; -impl<'a, REG> IndepW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - #[inline(always)] - pub fn complementary(self) -> &'a mut crate::W { - self.variant(Indep::Complementary) - } - #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - #[inline(always)] - pub fn independent(self) -> &'a mut crate::W { - self.variant(Indep::Independent) - } -} -#[doc = "Field `DBGEN` reader - Debug Enable"] -pub type DbgenR = crate::BitReader; -#[doc = "Field `DBGEN` writer - Debug Enable"] -pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&self) -> ClkSelR { - ClkSelR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&self) -> ReloadSelR { - ReloadSelR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&self) -> ForceSelR { - ForceSelR::new(((self.bits >> 3) & 7) as u8) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&self) -> ForceR { - ForceR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&self) -> FrcenR { - FrcenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&self) -> InitSelR { - InitSelR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&self) -> PwmxInitR { - PwmxInitR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&self) -> Pwm45InitR { - Pwm45InitR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&self) -> Pwm23InitR { - Pwm23InitR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&self) -> IndepR { - IndepR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&self) -> DbgenR { - DbgenR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - Clock Source Select"] - #[inline(always)] - pub fn clk_sel(&mut self) -> ClkSelW { - ClkSelW::new(self, 0) - } - #[doc = "Bit 2 - Reload Source Select"] - #[inline(always)] - pub fn reload_sel(&mut self) -> ReloadSelW { - ReloadSelW::new(self, 2) - } - #[doc = "Bits 3:5 - Force Select"] - #[inline(always)] - pub fn force_sel(&mut self) -> ForceSelW { - ForceSelW::new(self, 3) - } - #[doc = "Bit 6 - Force Initialization"] - #[inline(always)] - pub fn force(&mut self) -> ForceW { - ForceW::new(self, 6) - } - #[doc = "Bit 7 - Force Enable"] - #[inline(always)] - pub fn frcen(&mut self) -> FrcenW { - FrcenW::new(self, 7) - } - #[doc = "Bits 8:9 - Initialization Control Select"] - #[inline(always)] - pub fn init_sel(&mut self) -> InitSelW { - InitSelW::new(self, 8) - } - #[doc = "Bit 10 - PWM_X Initial Value"] - #[inline(always)] - pub fn pwmx_init(&mut self) -> PwmxInitW { - PwmxInitW::new(self, 10) - } - #[doc = "Bit 11 - PWM45 Initial Value"] - #[inline(always)] - pub fn pwm45_init(&mut self) -> Pwm45InitW { - Pwm45InitW::new(self, 11) - } - #[doc = "Bit 12 - PWM23 Initial Value"] - #[inline(always)] - pub fn pwm23_init(&mut self) -> Pwm23InitW { - Pwm23InitW::new(self, 12) - } - #[doc = "Bit 13 - Independent or Complementary Pair Operation"] - #[inline(always)] - pub fn indep(&mut self) -> IndepW { - IndepW::new(self, 13) - } - #[doc = "Bit 15 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&mut self) -> DbgenW { - DbgenW::new(self, 15) - } -} -#[doc = "Control 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3ctrl2Spec; -impl crate::RegisterSpec for Sm3ctrl2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3ctrl2::R`](R) reader structure"] -impl crate::Readable for Sm3ctrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3ctrl2::W`](W) writer structure"] -impl crate::Writable for Sm3ctrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3CTRL2 to value 0"] -impl crate::Resettable for Sm3ctrl2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval0.rs b/mcxa276-pac/src/flexpwm0/sm3cval0.rs deleted file mode 100644 index 5a45fd69d..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3cval0.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM3CVAL0` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL0` reader - Capture Value 0"] -pub type Captval0R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 0"] - #[inline(always)] - pub fn captval0(&self) -> Captval0R { - Captval0R::new(self.bits) - } -} -#[doc = "Capture Value 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3cval0Spec; -impl crate::RegisterSpec for Sm3cval0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3cval0::R`](R) reader structure"] -impl crate::Readable for Sm3cval0Spec {} -#[doc = "`reset()` method sets SM3CVAL0 to value 0"] -impl crate::Resettable for Sm3cval0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs b/mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs deleted file mode 100644 index ecfc79254..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3cval0cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM3CVAL0CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL0CYC` reader - Capture Value 0 Cycle"] -pub type Cval0cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 0 Cycle"] - #[inline(always)] - pub fn cval0cyc(&self) -> Cval0cycR { - Cval0cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 0 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval0cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3cval0cycSpec; -impl crate::RegisterSpec for Sm3cval0cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3cval0cyc::R`](R) reader structure"] -impl crate::Readable for Sm3cval0cycSpec {} -#[doc = "`reset()` method sets SM3CVAL0CYC to value 0"] -impl crate::Resettable for Sm3cval0cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval1.rs b/mcxa276-pac/src/flexpwm0/sm3cval1.rs deleted file mode 100644 index de6510093..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3cval1.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM3CVAL1` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTVAL1` reader - Capture Value 1"] -pub type Captval1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Capture Value 1"] - #[inline(always)] - pub fn captval1(&self) -> Captval1R { - Captval1R::new(self.bits) - } -} -#[doc = "Capture Value 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3cval1Spec; -impl crate::RegisterSpec for Sm3cval1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3cval1::R`](R) reader structure"] -impl crate::Readable for Sm3cval1Spec {} -#[doc = "`reset()` method sets SM3CVAL1 to value 0"] -impl crate::Resettable for Sm3cval1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs b/mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs deleted file mode 100644 index bf80ed837..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3cval1cyc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SM3CVAL1CYC` reader"] -pub type R = crate::R; -#[doc = "Field `CVAL1CYC` reader - Capture Value 1 Cycle"] -pub type Cval1cycR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Capture Value 1 Cycle"] - #[inline(always)] - pub fn cval1cyc(&self) -> Cval1cycR { - Cval1cycR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Capture Value 1 Cycle Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3cval1cyc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3cval1cycSpec; -impl crate::RegisterSpec for Sm3cval1cycSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3cval1cyc::R`](R) reader structure"] -impl crate::Readable for Sm3cval1cycSpec {} -#[doc = "`reset()` method sets SM3CVAL1CYC to value 0"] -impl crate::Resettable for Sm3cval1cycSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3dismap0.rs b/mcxa276-pac/src/flexpwm0/sm3dismap0.rs deleted file mode 100644 index e1553271f..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3dismap0.rs +++ /dev/null @@ -1,65 +0,0 @@ -#[doc = "Register `SM3DISMAP0` reader"] -pub type R = crate::R; -#[doc = "Register `SM3DISMAP0` writer"] -pub type W = crate::W; -#[doc = "Field `DIS0A` reader - PWM_A Fault Disable Mask 0"] -pub type Dis0aR = crate::FieldReader; -#[doc = "Field `DIS0A` writer - PWM_A Fault Disable Mask 0"] -pub type Dis0aW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0B` reader - PWM_B Fault Disable Mask 0"] -pub type Dis0bR = crate::FieldReader; -#[doc = "Field `DIS0B` writer - PWM_B Fault Disable Mask 0"] -pub type Dis0bW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DIS0X` reader - PWM_X Fault Disable Mask 0"] -pub type Dis0xR = crate::FieldReader; -#[doc = "Field `DIS0X` writer - PWM_X Fault Disable Mask 0"] -pub type Dis0xW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&self) -> Dis0aR { - Dis0aR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&self) -> Dis0bR { - Dis0bR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&self) -> Dis0xR { - Dis0xR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - PWM_A Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0a(&mut self) -> Dis0aW { - Dis0aW::new(self, 0) - } - #[doc = "Bits 4:7 - PWM_B Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0b(&mut self) -> Dis0bW { - Dis0bW::new(self, 4) - } - #[doc = "Bits 8:11 - PWM_X Fault Disable Mask 0"] - #[inline(always)] - pub fn dis0x(&mut self) -> Dis0xW { - Dis0xW::new(self, 8) - } -} -#[doc = "Fault Disable Mapping Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dismap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dismap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3dismap0Spec; -impl crate::RegisterSpec for Sm3dismap0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3dismap0::R`](R) reader structure"] -impl crate::Readable for Sm3dismap0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3dismap0::W`](W) writer structure"] -impl crate::Writable for Sm3dismap0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3DISMAP0 to value 0xffff"] -impl crate::Resettable for Sm3dismap0Spec { - const RESET_VALUE: u16 = 0xffff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm3dmaen.rs b/mcxa276-pac/src/flexpwm0/sm3dmaen.rs deleted file mode 100644 index b4f400b8f..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3dmaen.rs +++ /dev/null @@ -1,271 +0,0 @@ -#[doc = "Register `SM3DMAEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM3DMAEN` writer"] -pub type W = crate::W; -#[doc = "Field `CX0DE` reader - Capture X0 FIFO DMA Enable"] -pub type Cx0deR = crate::BitReader; -#[doc = "Field `CX0DE` writer - Capture X0 FIFO DMA Enable"] -pub type Cx0deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CX1DE` reader - Capture X1 FIFO DMA Enable"] -pub type Cx1deR = crate::BitReader; -#[doc = "Field `CX1DE` writer - Capture X1 FIFO DMA Enable"] -pub type Cx1deW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Capture DMA Enable Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Captde { - #[doc = "0: Read DMA requests disabled."] - Disabled = 0, - #[doc = "1: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - Exceedfifo = 1, - #[doc = "2: A local synchronization (VAL1 matches counter) sets the read DMA request."] - LocalSync = 2, - #[doc = "3: A local reload (STS\\[RF\\] being set) sets the read DMA request."] - LocalReload = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Captde) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Captde { - type Ux = u8; -} -impl crate::IsEnum for Captde {} -#[doc = "Field `CAPTDE` reader - Capture DMA Enable Source Select"] -pub type CaptdeR = crate::FieldReader; -impl CaptdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Captde { - match self.bits { - 0 => Captde::Disabled, - 1 => Captde::Exceedfifo, - 2 => Captde::LocalSync, - 3 => Captde::LocalReload, - _ => unreachable!(), - } - } - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Captde::Disabled - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn is_exceedfifo(&self) -> bool { - *self == Captde::Exceedfifo - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn is_local_sync(&self) -> bool { - *self == Captde::LocalSync - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn is_local_reload(&self) -> bool { - *self == Captde::LocalReload - } -} -#[doc = "Field `CAPTDE` writer - Capture DMA Enable Source Select"] -pub type CaptdeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Captde, crate::Safe>; -impl<'a, REG> CaptdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Read DMA requests disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Captde::Disabled) - } - #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - #[inline(always)] - pub fn exceedfifo(self) -> &'a mut crate::W { - self.variant(Captde::Exceedfifo) - } - #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - #[inline(always)] - pub fn local_sync(self) -> &'a mut crate::W { - self.variant(Captde::LocalSync) - } - #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - #[inline(always)] - pub fn local_reload(self) -> &'a mut crate::W { - self.variant(Captde::LocalReload) - } -} -#[doc = "FIFO Watermark AND Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fand { - #[doc = "0: Selected FIFO watermarks are OR'ed together."] - Or = 0, - #[doc = "1: Selected FIFO watermarks are AND'ed together."] - And = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fand) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FAND` reader - FIFO Watermark AND Control"] -pub type FandR = crate::BitReader; -impl FandR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fand { - match self.bits { - false => Fand::Or, - true => Fand::And, - } - } - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn is_or(&self) -> bool { - *self == Fand::Or - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn is_and(&self) -> bool { - *self == Fand::And - } -} -#[doc = "Field `FAND` writer - FIFO Watermark AND Control"] -pub type FandW<'a, REG> = crate::BitWriter<'a, REG, Fand>; -impl<'a, REG> FandW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Selected FIFO watermarks are OR'ed together."] - #[inline(always)] - pub fn or(self) -> &'a mut crate::W { - self.variant(Fand::Or) - } - #[doc = "Selected FIFO watermarks are AND'ed together."] - #[inline(always)] - pub fn and(self) -> &'a mut crate::W { - self.variant(Fand::And) - } -} -#[doc = "Value Registers DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Valde { - #[doc = "0: DMA write requests disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Valde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VALDE` reader - Value Registers DMA Enable"] -pub type ValdeR = crate::BitReader; -impl ValdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Valde { - match self.bits { - false => Valde::Disabled, - true => Valde::Enabled, - } - } - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Valde::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Valde::Enabled - } -} -#[doc = "Field `VALDE` writer - Value Registers DMA Enable"] -pub type ValdeW<'a, REG> = crate::BitWriter<'a, REG, Valde>; -impl<'a, REG> ValdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DMA write requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Valde::Disabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Valde::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&self) -> Cx0deR { - Cx0deR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&self) -> Cx1deR { - Cx1deR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&self) -> CaptdeR { - CaptdeR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&self) -> FandR { - FandR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&self) -> ValdeR { - ValdeR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Capture X0 FIFO DMA Enable"] - #[inline(always)] - pub fn cx0de(&mut self) -> Cx0deW { - Cx0deW::new(self, 0) - } - #[doc = "Bit 1 - Capture X1 FIFO DMA Enable"] - #[inline(always)] - pub fn cx1de(&mut self) -> Cx1deW { - Cx1deW::new(self, 1) - } - #[doc = "Bits 6:7 - Capture DMA Enable Source Select"] - #[inline(always)] - pub fn captde(&mut self) -> CaptdeW { - CaptdeW::new(self, 6) - } - #[doc = "Bit 8 - FIFO Watermark AND Control"] - #[inline(always)] - pub fn fand(&mut self) -> FandW { - FandW::new(self, 8) - } - #[doc = "Bit 9 - Value Registers DMA Enable"] - #[inline(always)] - pub fn valde(&mut self) -> ValdeW { - ValdeW::new(self, 9) - } -} -#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dmaen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dmaen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3dmaenSpec; -impl crate::RegisterSpec for Sm3dmaenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3dmaen::R`](R) reader structure"] -impl crate::Readable for Sm3dmaenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3dmaen::W`](W) writer structure"] -impl crate::Writable for Sm3dmaenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3DMAEN to value 0"] -impl crate::Resettable for Sm3dmaenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs b/mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs deleted file mode 100644 index 80a4a13e8..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3dtcnt0.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM3DTCNT0` reader"] -pub type R = crate::R; -#[doc = "Register `SM3DTCNT0` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT0` reader - Deadtime Count Register 0"] -pub type Dtcnt0R = crate::FieldReader; -#[doc = "Field `DTCNT0` writer - Deadtime Count Register 0"] -pub type Dtcnt0W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&self) -> Dtcnt0R { - Dtcnt0R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 0"] - #[inline(always)] - pub fn dtcnt0(&mut self) -> Dtcnt0W { - Dtcnt0W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3dtcnt0Spec; -impl crate::RegisterSpec for Sm3dtcnt0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3dtcnt0::R`](R) reader structure"] -impl crate::Readable for Sm3dtcnt0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3dtcnt0::W`](W) writer structure"] -impl crate::Writable for Sm3dtcnt0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3DTCNT0 to value 0x07ff"] -impl crate::Resettable for Sm3dtcnt0Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs b/mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs deleted file mode 100644 index 2d83230bc..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3dtcnt1.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SM3DTCNT1` reader"] -pub type R = crate::R; -#[doc = "Register `SM3DTCNT1` writer"] -pub type W = crate::W; -#[doc = "Field `DTCNT1` reader - Deadtime Count Register 1"] -pub type Dtcnt1R = crate::FieldReader; -#[doc = "Field `DTCNT1` writer - Deadtime Count Register 1"] -pub type Dtcnt1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&self) -> Dtcnt1R { - Dtcnt1R::new(self.bits & 0x07ff) - } -} -impl W { - #[doc = "Bits 0:10 - Deadtime Count Register 1"] - #[inline(always)] - pub fn dtcnt1(&mut self) -> Dtcnt1W { - Dtcnt1W::new(self, 0) - } -} -#[doc = "Deadtime Count Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3dtcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3dtcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3dtcnt1Spec; -impl crate::RegisterSpec for Sm3dtcnt1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3dtcnt1::R`](R) reader structure"] -impl crate::Readable for Sm3dtcnt1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3dtcnt1::W`](W) writer structure"] -impl crate::Writable for Sm3dtcnt1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3DTCNT1 to value 0x07ff"] -impl crate::Resettable for Sm3dtcnt1Spec { - const RESET_VALUE: u16 = 0x07ff; -} diff --git a/mcxa276-pac/src/flexpwm0/sm3init.rs b/mcxa276-pac/src/flexpwm0/sm3init.rs deleted file mode 100644 index e71f5609d..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3init.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3INIT` reader"] -pub type R = crate::R; -#[doc = "Register `SM3INIT` writer"] -pub type W = crate::W; -#[doc = "Field `INIT` reader - Initial Count Register Bits"] -pub type InitR = crate::FieldReader; -#[doc = "Field `INIT` writer - Initial Count Register Bits"] -pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&self) -> InitR { - InitR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn init(&mut self) -> InitW { - InitW::new(self, 0) - } -} -#[doc = "Initial Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3initSpec; -impl crate::RegisterSpec for Sm3initSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3init::R`](R) reader structure"] -impl crate::Readable for Sm3initSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3init::W`](W) writer structure"] -impl crate::Writable for Sm3initSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3INIT to value 0"] -impl crate::Resettable for Sm3initSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3inten.rs b/mcxa276-pac/src/flexpwm0/sm3inten.rs deleted file mode 100644 index 6dd4613d4..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3inten.rs +++ /dev/null @@ -1,343 +0,0 @@ -#[doc = "Register `SM3INTEN` reader"] -pub type R = crate::R; -#[doc = "Register `SM3INTEN` writer"] -pub type W = crate::W; -#[doc = "Compare Interrupt Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpie { - #[doc = "0: The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - Disabled = 0, - #[doc = "1: The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - Enabled = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpie) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpie { - type Ux = u8; -} -impl crate::IsEnum for Cmpie {} -#[doc = "Field `CMPIE` reader - Compare Interrupt Enables"] -pub type CmpieR = crate::FieldReader; -impl CmpieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpie::Disabled), - 1 => Some(Cmpie::Enabled), - _ => None, - } - } - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmpie::Disabled - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmpie::Enabled - } -} -#[doc = "Field `CMPIE` writer - Compare Interrupt Enables"] -pub type CmpieW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpie>; -impl<'a, REG> CmpieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Disabled) - } - #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmpie::Enabled) - } -} -#[doc = "Capture X 0 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx0ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX0\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX0\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx0ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX0IE` reader - Capture X 0 Interrupt Enable"] -pub type Cx0ieR = crate::BitReader; -impl Cx0ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx0ie { - match self.bits { - false => Cx0ie::Disabled, - true => Cx0ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx0ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx0ie::Enabled - } -} -#[doc = "Field `CX0IE` writer - Capture X 0 Interrupt Enable"] -pub type Cx0ieW<'a, REG> = crate::BitWriter<'a, REG, Cx0ie>; -impl<'a, REG> Cx0ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX0\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx0ie::Enabled) - } -} -#[doc = "Capture X 1 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cx1ie { - #[doc = "0: Interrupt request disabled for STS\\[CFX1\\]."] - Disabled = 0, - #[doc = "1: Interrupt request enabled for STS\\[CFX1\\]."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cx1ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CX1IE` reader - Capture X 1 Interrupt Enable"] -pub type Cx1ieR = crate::BitReader; -impl Cx1ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cx1ie { - match self.bits { - false => Cx1ie::Disabled, - true => Cx1ie::Enabled, - } - } - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cx1ie::Disabled - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cx1ie::Enabled - } -} -#[doc = "Field `CX1IE` writer - Capture X 1 Interrupt Enable"] -pub type Cx1ieW<'a, REG> = crate::BitWriter<'a, REG, Cx1ie>; -impl<'a, REG> Cx1ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt request disabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Disabled) - } - #[doc = "Interrupt request enabled for STS\\[CFX1\\]."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cx1ie::Enabled) - } -} -#[doc = "Reload Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rie { - #[doc = "0: STS\\[RF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[RF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RIE` reader - Reload Interrupt Enable"] -pub type RieR = crate::BitReader; -impl RieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rie { - match self.bits { - false => Rie::Disabled, - true => Rie::Enabled, - } - } - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rie::Disabled - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rie::Enabled - } -} -#[doc = "Field `RIE` writer - Reload Interrupt Enable"] -pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; -impl<'a, REG> RieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[RF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rie::Disabled) - } - #[doc = "STS\\[RF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rie::Enabled) - } -} -#[doc = "Reload Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reie { - #[doc = "0: STS\\[REF\\] CPU interrupt requests disabled"] - Disabled = 0, - #[doc = "1: STS\\[REF\\] CPU interrupt requests enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REIE` reader - Reload Error Interrupt Enable"] -pub type ReieR = crate::BitReader; -impl ReieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reie { - match self.bits { - false => Reie::Disabled, - true => Reie::Enabled, - } - } - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Reie::Disabled - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Reie::Enabled - } -} -#[doc = "Field `REIE` writer - Reload Error Interrupt Enable"] -pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; -impl<'a, REG> ReieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STS\\[REF\\] CPU interrupt requests disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Reie::Disabled) - } - #[doc = "STS\\[REF\\] CPU interrupt requests enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Reie::Enabled) - } -} -impl R { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&self) -> CmpieR { - CmpieR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&self) -> Cx0ieR { - Cx0ieR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&self) -> Cx1ieR { - Cx1ieR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&self) -> RieR { - RieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&self) -> ReieR { - ReieR::new(((self.bits >> 13) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Interrupt Enables"] - #[inline(always)] - pub fn cmpie(&mut self) -> CmpieW { - CmpieW::new(self, 0) - } - #[doc = "Bit 6 - Capture X 0 Interrupt Enable"] - #[inline(always)] - pub fn cx0ie(&mut self) -> Cx0ieW { - Cx0ieW::new(self, 6) - } - #[doc = "Bit 7 - Capture X 1 Interrupt Enable"] - #[inline(always)] - pub fn cx1ie(&mut self) -> Cx1ieW { - Cx1ieW::new(self, 7) - } - #[doc = "Bit 12 - Reload Interrupt Enable"] - #[inline(always)] - pub fn rie(&mut self) -> RieW { - RieW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&mut self) -> ReieW { - ReieW::new(self, 13) - } -} -#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3intenSpec; -impl crate::RegisterSpec for Sm3intenSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3inten::R`](R) reader structure"] -impl crate::Readable for Sm3intenSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3inten::W`](W) writer structure"] -impl crate::Writable for Sm3intenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3INTEN to value 0"] -impl crate::Resettable for Sm3intenSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3octrl.rs b/mcxa276-pac/src/flexpwm0/sm3octrl.rs deleted file mode 100644 index a83bd4c8e..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3octrl.rs +++ /dev/null @@ -1,519 +0,0 @@ -#[doc = "Register `SM3OCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM3OCTRL` writer"] -pub type W = crate::W; -#[doc = "PWM_X Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmxfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmxfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmxfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmxfs {} -#[doc = "Field `PWMXFS` reader - PWM_X Fault State"] -pub type PwmxfsR = crate::FieldReader; -impl PwmxfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmxfs { - match self.bits { - 0 => Pwmxfs::Logic0, - 1 => Pwmxfs::Logic1, - 2 => Pwmxfs::Tristated2, - 3 => Pwmxfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmxfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmxfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmxfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmxfs::Tristated3 - } -} -#[doc = "Field `PWMXFS` writer - PWM_X Fault State"] -pub type PwmxfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmxfs, crate::Safe>; -impl<'a, REG> PwmxfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmxfs::Tristated3) - } -} -#[doc = "PWM_B Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmbfs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmbfs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmbfs { - type Ux = u8; -} -impl crate::IsEnum for Pwmbfs {} -#[doc = "Field `PWMBFS` reader - PWM_B Fault State"] -pub type PwmbfsR = crate::FieldReader; -impl PwmbfsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmbfs { - match self.bits { - 0 => Pwmbfs::Logic0, - 1 => Pwmbfs::Logic1, - 2 => Pwmbfs::Tristated2, - 3 => Pwmbfs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmbfs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmbfs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmbfs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmbfs::Tristated3 - } -} -#[doc = "Field `PWMBFS` writer - PWM_B Fault State"] -pub type PwmbfsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmbfs, crate::Safe>; -impl<'a, REG> PwmbfsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmbfs::Tristated3) - } -} -#[doc = "PWM_A Fault State\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pwmafs { - #[doc = "0: Output is forced to logic 0 state prior to consideration of output polarity control."] - Logic0 = 0, - #[doc = "1: Output is forced to logic 1 state prior to consideration of output polarity control."] - Logic1 = 1, - #[doc = "2: Output is put in a high-impedance state."] - Tristated2 = 2, - #[doc = "3: Output is put in a high-impedance state."] - Tristated3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pwmafs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pwmafs { - type Ux = u8; -} -impl crate::IsEnum for Pwmafs {} -#[doc = "Field `PWMAFS` reader - PWM_A Fault State"] -pub type PwmafsR = crate::FieldReader; -impl PwmafsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwmafs { - match self.bits { - 0 => Pwmafs::Logic0, - 1 => Pwmafs::Logic1, - 2 => Pwmafs::Tristated2, - 3 => Pwmafs::Tristated3, - _ => unreachable!(), - } - } - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Pwmafs::Logic0 - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Pwmafs::Logic1 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_2(&self) -> bool { - *self == Pwmafs::Tristated2 - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn is_tristated_3(&self) -> bool { - *self == Pwmafs::Tristated3 - } -} -#[doc = "Field `PWMAFS` writer - PWM_A Fault State"] -pub type PwmafsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwmafs, crate::Safe>; -impl<'a, REG> PwmafsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic0) - } - #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Pwmafs::Logic1) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_2(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated2) - } - #[doc = "Output is put in a high-impedance state."] - #[inline(always)] - pub fn tristated_3(self) -> &'a mut crate::W { - self.variant(Pwmafs::Tristated3) - } -} -#[doc = "PWM_X Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polx { - #[doc = "0: PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLX` reader - PWM_X Output Polarity"] -pub type PolxR = crate::BitReader; -impl PolxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polx { - match self.bits { - false => Polx::NotInverted, - true => Polx::Inverted, - } - } - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polx::NotInverted - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polx::Inverted - } -} -#[doc = "Field `POLX` writer - PWM_X Output Polarity"] -pub type PolxW<'a, REG> = crate::BitWriter<'a, REG, Polx>; -impl<'a, REG> PolxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polx::NotInverted) - } - #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polx::Inverted) - } -} -#[doc = "PWM_B Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Polb { - #[doc = "0: PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Polb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLB` reader - PWM_B Output Polarity"] -pub type PolbR = crate::BitReader; -impl PolbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Polb { - match self.bits { - false => Polb::NotInverted, - true => Polb::Inverted, - } - } - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Polb::NotInverted - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Polb::Inverted - } -} -#[doc = "Field `POLB` writer - PWM_B Output Polarity"] -pub type PolbW<'a, REG> = crate::BitWriter<'a, REG, Polb>; -impl<'a, REG> PolbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Polb::NotInverted) - } - #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Polb::Inverted) - } -} -#[doc = "PWM_A Output Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pola { - #[doc = "0: PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - NotInverted = 0, - #[doc = "1: PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pola) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `POLA` reader - PWM_A Output Polarity"] -pub type PolaR = crate::BitReader; -impl PolaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pola { - match self.bits { - false => Pola::NotInverted, - true => Pola::Inverted, - } - } - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Pola::NotInverted - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Pola::Inverted - } -} -#[doc = "Field `POLA` writer - PWM_A Output Polarity"] -pub type PolaW<'a, REG> = crate::BitWriter<'a, REG, Pola>; -impl<'a, REG> PolaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Pola::NotInverted) - } - #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Pola::Inverted) - } -} -#[doc = "Field `PWMX_IN` reader - PWM_X Input"] -pub type PwmxInR = crate::BitReader; -#[doc = "Field `PWMB_IN` reader - PWM_B Input"] -pub type PwmbInR = crate::BitReader; -#[doc = "Field `PWMA_IN` reader - PWM_A Input"] -pub type PwmaInR = crate::BitReader; -impl R { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&self) -> PwmxfsR { - PwmxfsR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&self) -> PwmbfsR { - PwmbfsR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&self) -> PwmafsR { - PwmafsR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&self) -> PolxR { - PolxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&self) -> PolbR { - PolbR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&self) -> PolaR { - PolaR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 13 - PWM_X Input"] - #[inline(always)] - pub fn pwmx_in(&self) -> PwmxInR { - PwmxInR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - PWM_B Input"] - #[inline(always)] - pub fn pwmb_in(&self) -> PwmbInR { - PwmbInR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - PWM_A Input"] - #[inline(always)] - pub fn pwma_in(&self) -> PwmaInR { - PwmaInR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - PWM_X Fault State"] - #[inline(always)] - pub fn pwmxfs(&mut self) -> PwmxfsW { - PwmxfsW::new(self, 0) - } - #[doc = "Bits 2:3 - PWM_B Fault State"] - #[inline(always)] - pub fn pwmbfs(&mut self) -> PwmbfsW { - PwmbfsW::new(self, 2) - } - #[doc = "Bits 4:5 - PWM_A Fault State"] - #[inline(always)] - pub fn pwmafs(&mut self) -> PwmafsW { - PwmafsW::new(self, 4) - } - #[doc = "Bit 8 - PWM_X Output Polarity"] - #[inline(always)] - pub fn polx(&mut self) -> PolxW { - PolxW::new(self, 8) - } - #[doc = "Bit 9 - PWM_B Output Polarity"] - #[inline(always)] - pub fn polb(&mut self) -> PolbW { - PolbW::new(self, 9) - } - #[doc = "Bit 10 - PWM_A Output Polarity"] - #[inline(always)] - pub fn pola(&mut self) -> PolaW { - PolaW::new(self, 10) - } -} -#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3octrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3octrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3octrlSpec; -impl crate::RegisterSpec for Sm3octrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3octrl::R`](R) reader structure"] -impl crate::Readable for Sm3octrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3octrl::W`](W) writer structure"] -impl crate::Writable for Sm3octrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3OCTRL to value 0"] -impl crate::Resettable for Sm3octrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3phasedly.rs b/mcxa276-pac/src/flexpwm0/sm3phasedly.rs deleted file mode 100644 index ccaa095f9..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3phasedly.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3PHASEDLY` reader"] -pub type R = crate::R; -#[doc = "Register `SM3PHASEDLY` writer"] -pub type W = crate::W; -#[doc = "Field `PHASEDLY` reader - Initial Count Register Bits"] -pub type PhasedlyR = crate::FieldReader; -#[doc = "Field `PHASEDLY` writer - Initial Count Register Bits"] -pub type PhasedlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn phasedly(&self) -> PhasedlyR { - PhasedlyR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Initial Count Register Bits"] - #[inline(always)] - pub fn phasedly(&mut self) -> PhasedlyW { - PhasedlyW::new(self, 0) - } -} -#[doc = "Phase Delay Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3phasedly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3phasedly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3phasedlySpec; -impl crate::RegisterSpec for Sm3phasedlySpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3phasedly::R`](R) reader structure"] -impl crate::Readable for Sm3phasedlySpec {} -#[doc = "`write(|w| ..)` method takes [`sm3phasedly::W`](W) writer structure"] -impl crate::Writable for Sm3phasedlySpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3PHASEDLY to value 0"] -impl crate::Resettable for Sm3phasedlySpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3sts.rs b/mcxa276-pac/src/flexpwm0/sm3sts.rs deleted file mode 100644 index 5dd9c7723..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3sts.rs +++ /dev/null @@ -1,287 +0,0 @@ -#[doc = "Register `SM3STS` reader"] -pub type R = crate::R; -#[doc = "Register `SM3STS` writer"] -pub type W = crate::W; -#[doc = "Compare Flags\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmpf { - #[doc = "0: No compare event has occurred for a particular VALx value."] - NoEvent = 0, - #[doc = "1: A compare event has occurred for a particular VALx value."] - Event = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmpf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmpf { - type Ux = u8; -} -impl crate::IsEnum for Cmpf {} -#[doc = "Field `CMPF` reader - Compare Flags"] -pub type CmpfR = crate::FieldReader; -impl CmpfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmpf::NoEvent), - 1 => Some(Cmpf::Event), - _ => None, - } - } - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_no_event(&self) -> bool { - *self == Cmpf::NoEvent - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn is_event(&self) -> bool { - *self == Cmpf::Event - } -} -#[doc = "Field `CMPF` writer - Compare Flags"] -pub type CmpfW<'a, REG> = crate::FieldWriter<'a, REG, 6, Cmpf>; -impl<'a, REG> CmpfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn no_event(self) -> &'a mut crate::W { - self.variant(Cmpf::NoEvent) - } - #[doc = "A compare event has occurred for a particular VALx value."] - #[inline(always)] - pub fn event(self) -> &'a mut crate::W { - self.variant(Cmpf::Event) - } -} -#[doc = "Field `CFX0` reader - Capture Flag X0"] -pub type Cfx0R = crate::BitReader; -#[doc = "Field `CFX0` writer - Capture Flag X0"] -pub type Cfx0W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `CFX1` reader - Capture Flag X1"] -pub type Cfx1R = crate::BitReader; -#[doc = "Field `CFX1` writer - Capture Flag X1"] -pub type Cfx1W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Reload Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rf { - #[doc = "0: No new reload cycle since last STS\\[RF\\] clearing"] - NoFlag = 0, - #[doc = "1: New reload cycle since last STS\\[RF\\] clearing"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RF` reader - Reload Flag"] -pub type RfR = crate::BitReader; -impl RfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rf { - match self.bits { - false => Rf::NoFlag, - true => Rf::Flag, - } - } - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Rf::NoFlag - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Rf::Flag - } -} -#[doc = "Field `RF` writer - Reload Flag"] -pub type RfW<'a, REG> = crate::BitWriter1C<'a, REG, Rf>; -impl<'a, REG> RfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No new reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Rf::NoFlag) - } - #[doc = "New reload cycle since last STS\\[RF\\] clearing"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Rf::Flag) - } -} -#[doc = "Reload Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ref { - #[doc = "0: No reload error occurred."] - NoFlag = 0, - #[doc = "1: Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ref) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REF` reader - Reload Error Flag"] -pub type RefR = crate::BitReader; -impl RefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ref { - match self.bits { - false => Ref::NoFlag, - true => Ref::Flag, - } - } - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ref::NoFlag - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ref::Flag - } -} -#[doc = "Field `REF` writer - Reload Error Flag"] -pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; -impl<'a, REG> RefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No reload error occurred."] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Ref::NoFlag) - } - #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Ref::Flag) - } -} -#[doc = "Registers Updated Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ruf { - #[doc = "0: No register update has occurred since last reload."] - NoFlag = 0, - #[doc = "1: At least one of the double buffered registers has been updated since the last reload."] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ruf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RUF` reader - Registers Updated Flag"] -pub type RufR = crate::BitReader; -impl RufR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ruf { - match self.bits { - false => Ruf::NoFlag, - true => Ruf::Flag, - } - } - #[doc = "No register update has occurred since last reload."] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Ruf::NoFlag - } - #[doc = "At least one of the double buffered registers has been updated since the last reload."] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Ruf::Flag - } -} -impl R { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&self) -> CmpfR { - CmpfR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&self) -> Cfx0R { - Cfx0R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&self) -> Cfx1R { - Cfx1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&self) -> RfR { - RfR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&self) -> RefR { - RefR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Registers Updated Flag"] - #[inline(always)] - pub fn ruf(&self) -> RufR { - RufR::new(((self.bits >> 14) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Compare Flags"] - #[inline(always)] - pub fn cmpf(&mut self) -> CmpfW { - CmpfW::new(self, 0) - } - #[doc = "Bit 6 - Capture Flag X0"] - #[inline(always)] - pub fn cfx0(&mut self) -> Cfx0W { - Cfx0W::new(self, 6) - } - #[doc = "Bit 7 - Capture Flag X1"] - #[inline(always)] - pub fn cfx1(&mut self) -> Cfx1W { - Cfx1W::new(self, 7) - } - #[doc = "Bit 12 - Reload Flag"] - #[inline(always)] - pub fn rf(&mut self) -> RfW { - RfW::new(self, 12) - } - #[doc = "Bit 13 - Reload Error Flag"] - #[inline(always)] - pub fn ref_(&mut self) -> RefW { - RefW::new(self, 13) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3stsSpec; -impl crate::RegisterSpec for Sm3stsSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3sts::R`](R) reader structure"] -impl crate::Readable for Sm3stsSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3sts::W`](W) writer structure"] -impl crate::Writable for Sm3stsSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0x30ff; -} -#[doc = "`reset()` method sets SM3STS to value 0"] -impl crate::Resettable for Sm3stsSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3tctrl.rs b/mcxa276-pac/src/flexpwm0/sm3tctrl.rs deleted file mode 100644 index 1cdc4fbc7..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3tctrl.rs +++ /dev/null @@ -1,267 +0,0 @@ -#[doc = "Register `SM3TCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SM3TCTRL` writer"] -pub type W = crate::W; -#[doc = "Output Trigger Enables\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OutTrigEn { - #[doc = "1: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - Val0 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OutTrigEn) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OutTrigEn { - type Ux = u8; -} -impl crate::IsEnum for OutTrigEn {} -#[doc = "Field `OUT_TRIG_EN` reader - Output Trigger Enables"] -pub type OutTrigEnR = crate::FieldReader; -impl OutTrigEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(OutTrigEn::Val0), - _ => None, - } - } - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == OutTrigEn::Val0 - } -} -#[doc = "Field `OUT_TRIG_EN` writer - Output Trigger Enables"] -pub type OutTrigEnW<'a, REG> = crate::FieldWriter<'a, REG, 6, OutTrigEn>; -impl<'a, REG> OutTrigEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - #[inline(always)] - pub fn val0(self) -> &'a mut crate::W { - self.variant(OutTrigEn::Val0) - } -} -#[doc = "Trigger Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trgfrq { - #[doc = "0: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Everypwm = 0, - #[doc = "1: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - Finalpwm = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trgfrq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRGFRQ` reader - Trigger Frequency"] -pub type TrgfrqR = crate::BitReader; -impl TrgfrqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgfrq { - match self.bits { - false => Trgfrq::Everypwm, - true => Trgfrq::Finalpwm, - } - } - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_everypwm(&self) -> bool { - *self == Trgfrq::Everypwm - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn is_finalpwm(&self) -> bool { - *self == Trgfrq::Finalpwm - } -} -#[doc = "Field `TRGFRQ` writer - Trigger Frequency"] -pub type TrgfrqW<'a, REG> = crate::BitWriter<'a, REG, Trgfrq>; -impl<'a, REG> TrgfrqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn everypwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Everypwm) - } - #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - #[inline(always)] - pub fn finalpwm(self) -> &'a mut crate::W { - self.variant(Trgfrq::Finalpwm) - } -} -#[doc = "Mux Output Trigger 1 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwbot1 { - #[doc = "0: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - PwmOutTrig1Signal = 0, - #[doc = "1: Route the PWM_B output to the PWM_MUX_TRIG1 port."] - PwmbOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwbot1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWBOT1` reader - Mux Output Trigger 1 Source Select"] -pub type Pwbot1R = crate::BitReader; -impl Pwbot1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwbot1 { - match self.bits { - false => Pwbot1::PwmOutTrig1Signal, - true => Pwbot1::PwmbOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwm_out_trig1_signal(&self) -> bool { - *self == Pwbot1::PwmOutTrig1Signal - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn is_pwmb_output(&self) -> bool { - *self == Pwbot1::PwmbOutput - } -} -#[doc = "Field `PWBOT1` writer - Mux Output Trigger 1 Source Select"] -pub type Pwbot1W<'a, REG> = crate::BitWriter<'a, REG, Pwbot1>; -impl<'a, REG> Pwbot1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwm_out_trig1_signal(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmOutTrig1Signal) - } - #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - #[inline(always)] - pub fn pwmb_output(self) -> &'a mut crate::W { - self.variant(Pwbot1::PwmbOutput) - } -} -#[doc = "Mux Output Trigger 0 Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pwaot0 { - #[doc = "0: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - PwmOutTrig0Signal = 0, - #[doc = "1: Route the PWM_A output to the PWM_MUX_TRIG0 port."] - PwmaOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pwaot0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWAOT0` reader - Mux Output Trigger 0 Source Select"] -pub type Pwaot0R = crate::BitReader; -impl Pwaot0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pwaot0 { - match self.bits { - false => Pwaot0::PwmOutTrig0Signal, - true => Pwaot0::PwmaOutput, - } - } - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwm_out_trig0_signal(&self) -> bool { - *self == Pwaot0::PwmOutTrig0Signal - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn is_pwma_output(&self) -> bool { - *self == Pwaot0::PwmaOutput - } -} -#[doc = "Field `PWAOT0` writer - Mux Output Trigger 0 Source Select"] -pub type Pwaot0W<'a, REG> = crate::BitWriter<'a, REG, Pwaot0>; -impl<'a, REG> Pwaot0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwm_out_trig0_signal(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmOutTrig0Signal) - } - #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - #[inline(always)] - pub fn pwma_output(self) -> &'a mut crate::W { - self.variant(Pwaot0::PwmaOutput) - } -} -impl R { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&self) -> OutTrigEnR { - OutTrigEnR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&self) -> TrgfrqR { - TrgfrqR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&self) -> Pwbot1R { - Pwbot1R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&self) -> Pwaot0R { - Pwaot0R::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Output Trigger Enables"] - #[inline(always)] - pub fn out_trig_en(&mut self) -> OutTrigEnW { - OutTrigEnW::new(self, 0) - } - #[doc = "Bit 12 - Trigger Frequency"] - #[inline(always)] - pub fn trgfrq(&mut self) -> TrgfrqW { - TrgfrqW::new(self, 12) - } - #[doc = "Bit 14 - Mux Output Trigger 1 Source Select"] - #[inline(always)] - pub fn pwbot1(&mut self) -> Pwbot1W { - Pwbot1W::new(self, 14) - } - #[doc = "Bit 15 - Mux Output Trigger 0 Source Select"] - #[inline(always)] - pub fn pwaot0(&mut self) -> Pwaot0W { - Pwaot0W::new(self, 15) - } -} -#[doc = "Output Trigger Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3tctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3tctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3tctrlSpec; -impl crate::RegisterSpec for Sm3tctrlSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3tctrl::R`](R) reader structure"] -impl crate::Readable for Sm3tctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sm3tctrl::W`](W) writer structure"] -impl crate::Writable for Sm3tctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3TCTRL to value 0"] -impl crate::Resettable for Sm3tctrlSpec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val0.rs b/mcxa276-pac/src/flexpwm0/sm3val0.rs deleted file mode 100644 index bce081cba..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3val0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3VAL0` reader"] -pub type R = crate::R; -#[doc = "Register `SM3VAL0` writer"] -pub type W = crate::W; -#[doc = "Field `VAL0` reader - Value 0"] -pub type Val0R = crate::FieldReader; -#[doc = "Field `VAL0` writer - Value 0"] -pub type Val0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&self) -> Val0R { - Val0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 0"] - #[inline(always)] - pub fn val0(&mut self) -> Val0W { - Val0W::new(self, 0) - } -} -#[doc = "Value Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3val0Spec; -impl crate::RegisterSpec for Sm3val0Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3val0::R`](R) reader structure"] -impl crate::Readable for Sm3val0Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3val0::W`](W) writer structure"] -impl crate::Writable for Sm3val0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3VAL0 to value 0"] -impl crate::Resettable for Sm3val0Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val1.rs b/mcxa276-pac/src/flexpwm0/sm3val1.rs deleted file mode 100644 index d54d73992..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3val1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3VAL1` reader"] -pub type R = crate::R; -#[doc = "Register `SM3VAL1` writer"] -pub type W = crate::W; -#[doc = "Field `VAL1` reader - Value 1"] -pub type Val1R = crate::FieldReader; -#[doc = "Field `VAL1` writer - Value 1"] -pub type Val1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&self) -> Val1R { - Val1R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 1"] - #[inline(always)] - pub fn val1(&mut self) -> Val1W { - Val1W::new(self, 0) - } -} -#[doc = "Value Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3val1Spec; -impl crate::RegisterSpec for Sm3val1Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3val1::R`](R) reader structure"] -impl crate::Readable for Sm3val1Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3val1::W`](W) writer structure"] -impl crate::Writable for Sm3val1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3VAL1 to value 0"] -impl crate::Resettable for Sm3val1Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val2.rs b/mcxa276-pac/src/flexpwm0/sm3val2.rs deleted file mode 100644 index 02c26ec2a..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3val2.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3VAL2` reader"] -pub type R = crate::R; -#[doc = "Register `SM3VAL2` writer"] -pub type W = crate::W; -#[doc = "Field `VAL2` reader - Value 2"] -pub type Val2R = crate::FieldReader; -#[doc = "Field `VAL2` writer - Value 2"] -pub type Val2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&self) -> Val2R { - Val2R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 2"] - #[inline(always)] - pub fn val2(&mut self) -> Val2W { - Val2W::new(self, 0) - } -} -#[doc = "Value Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3val2Spec; -impl crate::RegisterSpec for Sm3val2Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3val2::R`](R) reader structure"] -impl crate::Readable for Sm3val2Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3val2::W`](W) writer structure"] -impl crate::Writable for Sm3val2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3VAL2 to value 0"] -impl crate::Resettable for Sm3val2Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val3.rs b/mcxa276-pac/src/flexpwm0/sm3val3.rs deleted file mode 100644 index 443c3efc9..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3val3.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3VAL3` reader"] -pub type R = crate::R; -#[doc = "Register `SM3VAL3` writer"] -pub type W = crate::W; -#[doc = "Field `VAL3` reader - Value 3"] -pub type Val3R = crate::FieldReader; -#[doc = "Field `VAL3` writer - Value 3"] -pub type Val3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&self) -> Val3R { - Val3R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 3"] - #[inline(always)] - pub fn val3(&mut self) -> Val3W { - Val3W::new(self, 0) - } -} -#[doc = "Value Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3val3Spec; -impl crate::RegisterSpec for Sm3val3Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3val3::R`](R) reader structure"] -impl crate::Readable for Sm3val3Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3val3::W`](W) writer structure"] -impl crate::Writable for Sm3val3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3VAL3 to value 0"] -impl crate::Resettable for Sm3val3Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val4.rs b/mcxa276-pac/src/flexpwm0/sm3val4.rs deleted file mode 100644 index 6690c8284..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3val4.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3VAL4` reader"] -pub type R = crate::R; -#[doc = "Register `SM3VAL4` writer"] -pub type W = crate::W; -#[doc = "Field `VAL4` reader - Value 4"] -pub type Val4R = crate::FieldReader; -#[doc = "Field `VAL4` writer - Value 4"] -pub type Val4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&self) -> Val4R { - Val4R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 4"] - #[inline(always)] - pub fn val4(&mut self) -> Val4W { - Val4W::new(self, 0) - } -} -#[doc = "Value Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3val4Spec; -impl crate::RegisterSpec for Sm3val4Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3val4::R`](R) reader structure"] -impl crate::Readable for Sm3val4Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3val4::W`](W) writer structure"] -impl crate::Writable for Sm3val4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3VAL4 to value 0"] -impl crate::Resettable for Sm3val4Spec {} diff --git a/mcxa276-pac/src/flexpwm0/sm3val5.rs b/mcxa276-pac/src/flexpwm0/sm3val5.rs deleted file mode 100644 index 4b2b561f0..000000000 --- a/mcxa276-pac/src/flexpwm0/sm3val5.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SM3VAL5` reader"] -pub type R = crate::R; -#[doc = "Register `SM3VAL5` writer"] -pub type W = crate::W; -#[doc = "Field `VAL5` reader - Value 5"] -pub type Val5R = crate::FieldReader; -#[doc = "Field `VAL5` writer - Value 5"] -pub type Val5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&self) -> Val5R { - Val5R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:15 - Value 5"] - #[inline(always)] - pub fn val5(&mut self) -> Val5W { - Val5W::new(self, 0) - } -} -#[doc = "Value Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sm3val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm3val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Sm3val5Spec; -impl crate::RegisterSpec for Sm3val5Spec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sm3val5::R`](R) reader structure"] -impl crate::Readable for Sm3val5Spec {} -#[doc = "`write(|w| ..)` method takes [`sm3val5::W`](W) writer structure"] -impl crate::Writable for Sm3val5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SM3VAL5 to value 0"] -impl crate::Resettable for Sm3val5Spec {} diff --git a/mcxa276-pac/src/flexpwm0/swcout.rs b/mcxa276-pac/src/flexpwm0/swcout.rs deleted file mode 100644 index 976f04130..000000000 --- a/mcxa276-pac/src/flexpwm0/swcout.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `SWCOUT` reader"] -pub type R = crate::R; -#[doc = "Register `SWCOUT` writer"] -pub type W = crate::W; -#[doc = "Submodule 0 Software Controlled Output 45\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm0out45 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm0out45) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM0OUT45` reader - Submodule 0 Software Controlled Output 45"] -pub type Sm0out45R = crate::BitReader; -impl Sm0out45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm0out45 { - match self.bits { - false => Sm0out45::Logic0, - true => Sm0out45::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm0out45::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm0out45::Logic1 - } -} -#[doc = "Field `SM0OUT45` writer - Submodule 0 Software Controlled Output 45"] -pub type Sm0out45W<'a, REG> = crate::BitWriter<'a, REG, Sm0out45>; -impl<'a, REG> Sm0out45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm0out45::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm0out45::Logic1) - } -} -#[doc = "Submodule 0 Software Controlled Output 23\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm0out23 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm0out23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM0OUT23` reader - Submodule 0 Software Controlled Output 23"] -pub type Sm0out23R = crate::BitReader; -impl Sm0out23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm0out23 { - match self.bits { - false => Sm0out23::Logic0, - true => Sm0out23::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm0out23::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm0out23::Logic1 - } -} -#[doc = "Field `SM0OUT23` writer - Submodule 0 Software Controlled Output 23"] -pub type Sm0out23W<'a, REG> = crate::BitWriter<'a, REG, Sm0out23>; -impl<'a, REG> Sm0out23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm0out23::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm0out23::Logic1) - } -} -#[doc = "Submodule 1 Software Controlled Output 45\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm1out45 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm1out45) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM1OUT45` reader - Submodule 1 Software Controlled Output 45"] -pub type Sm1out45R = crate::BitReader; -impl Sm1out45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm1out45 { - match self.bits { - false => Sm1out45::Logic0, - true => Sm1out45::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm1out45::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm1out45::Logic1 - } -} -#[doc = "Field `SM1OUT45` writer - Submodule 1 Software Controlled Output 45"] -pub type Sm1out45W<'a, REG> = crate::BitWriter<'a, REG, Sm1out45>; -impl<'a, REG> Sm1out45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm1out45::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm1out45::Logic1) - } -} -#[doc = "Submodule 1 Software Controlled Output 23\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm1out23 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm1out23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM1OUT23` reader - Submodule 1 Software Controlled Output 23"] -pub type Sm1out23R = crate::BitReader; -impl Sm1out23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm1out23 { - match self.bits { - false => Sm1out23::Logic0, - true => Sm1out23::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm1out23::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm1out23::Logic1 - } -} -#[doc = "Field `SM1OUT23` writer - Submodule 1 Software Controlled Output 23"] -pub type Sm1out23W<'a, REG> = crate::BitWriter<'a, REG, Sm1out23>; -impl<'a, REG> Sm1out23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm1out23::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm1out23::Logic1) - } -} -#[doc = "Submodule 2 Software Controlled Output 45\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm2out45 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm2out45) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM2OUT45` reader - Submodule 2 Software Controlled Output 45"] -pub type Sm2out45R = crate::BitReader; -impl Sm2out45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm2out45 { - match self.bits { - false => Sm2out45::Logic0, - true => Sm2out45::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm2out45::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm2out45::Logic1 - } -} -#[doc = "Field `SM2OUT45` writer - Submodule 2 Software Controlled Output 45"] -pub type Sm2out45W<'a, REG> = crate::BitWriter<'a, REG, Sm2out45>; -impl<'a, REG> Sm2out45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm2out45::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm2out45::Logic1) - } -} -#[doc = "Submodule 2 Software Controlled Output 23\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm2out23 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm2out23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM2OUT23` reader - Submodule 2 Software Controlled Output 23"] -pub type Sm2out23R = crate::BitReader; -impl Sm2out23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm2out23 { - match self.bits { - false => Sm2out23::Logic0, - true => Sm2out23::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm2out23::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm2out23::Logic1 - } -} -#[doc = "Field `SM2OUT23` writer - Submodule 2 Software Controlled Output 23"] -pub type Sm2out23W<'a, REG> = crate::BitWriter<'a, REG, Sm2out23>; -impl<'a, REG> Sm2out23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm2out23::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm2out23::Logic1) - } -} -#[doc = "Submodule 3 Software Controlled Output 45\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm3out45 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm3out45) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM3OUT45` reader - Submodule 3 Software Controlled Output 45"] -pub type Sm3out45R = crate::BitReader; -impl Sm3out45R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm3out45 { - match self.bits { - false => Sm3out45::Logic0, - true => Sm3out45::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm3out45::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm3out45::Logic1 - } -} -#[doc = "Field `SM3OUT45` writer - Submodule 3 Software Controlled Output 45"] -pub type Sm3out45W<'a, REG> = crate::BitWriter<'a, REG, Sm3out45>; -impl<'a, REG> Sm3out45W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm3out45::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm3out45::Logic1) - } -} -#[doc = "Submodule 3 Software Controlled Output 23\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sm3out23 { - #[doc = "0: A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."] - Logic0 = 0, - #[doc = "1: A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."] - Logic1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sm3out23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SM3OUT23` reader - Submodule 3 Software Controlled Output 23"] -pub type Sm3out23R = crate::BitReader; -impl Sm3out23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sm3out23 { - match self.bits { - false => Sm3out23::Logic0, - true => Sm3out23::Logic1, - } - } - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."] - #[inline(always)] - pub fn is_logic_0(&self) -> bool { - *self == Sm3out23::Logic0 - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."] - #[inline(always)] - pub fn is_logic_1(&self) -> bool { - *self == Sm3out23::Logic1 - } -} -#[doc = "Field `SM3OUT23` writer - Submodule 3 Software Controlled Output 23"] -pub type Sm3out23W<'a, REG> = crate::BitWriter<'a, REG, Sm3out23>; -impl<'a, REG> Sm3out23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."] - #[inline(always)] - pub fn logic_0(self) -> &'a mut crate::W { - self.variant(Sm3out23::Logic0) - } - #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."] - #[inline(always)] - pub fn logic_1(self) -> &'a mut crate::W { - self.variant(Sm3out23::Logic1) - } -} -impl R { - #[doc = "Bit 0 - Submodule 0 Software Controlled Output 45"] - #[inline(always)] - pub fn sm0out45(&self) -> Sm0out45R { - Sm0out45R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Submodule 0 Software Controlled Output 23"] - #[inline(always)] - pub fn sm0out23(&self) -> Sm0out23R { - Sm0out23R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Submodule 1 Software Controlled Output 45"] - #[inline(always)] - pub fn sm1out45(&self) -> Sm1out45R { - Sm1out45R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Submodule 1 Software Controlled Output 23"] - #[inline(always)] - pub fn sm1out23(&self) -> Sm1out23R { - Sm1out23R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Submodule 2 Software Controlled Output 45"] - #[inline(always)] - pub fn sm2out45(&self) -> Sm2out45R { - Sm2out45R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Submodule 2 Software Controlled Output 23"] - #[inline(always)] - pub fn sm2out23(&self) -> Sm2out23R { - Sm2out23R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Submodule 3 Software Controlled Output 45"] - #[inline(always)] - pub fn sm3out45(&self) -> Sm3out45R { - Sm3out45R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Submodule 3 Software Controlled Output 23"] - #[inline(always)] - pub fn sm3out23(&self) -> Sm3out23R { - Sm3out23R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Submodule 0 Software Controlled Output 45"] - #[inline(always)] - pub fn sm0out45(&mut self) -> Sm0out45W { - Sm0out45W::new(self, 0) - } - #[doc = "Bit 1 - Submodule 0 Software Controlled Output 23"] - #[inline(always)] - pub fn sm0out23(&mut self) -> Sm0out23W { - Sm0out23W::new(self, 1) - } - #[doc = "Bit 2 - Submodule 1 Software Controlled Output 45"] - #[inline(always)] - pub fn sm1out45(&mut self) -> Sm1out45W { - Sm1out45W::new(self, 2) - } - #[doc = "Bit 3 - Submodule 1 Software Controlled Output 23"] - #[inline(always)] - pub fn sm1out23(&mut self) -> Sm1out23W { - Sm1out23W::new(self, 3) - } - #[doc = "Bit 4 - Submodule 2 Software Controlled Output 45"] - #[inline(always)] - pub fn sm2out45(&mut self) -> Sm2out45W { - Sm2out45W::new(self, 4) - } - #[doc = "Bit 5 - Submodule 2 Software Controlled Output 23"] - #[inline(always)] - pub fn sm2out23(&mut self) -> Sm2out23W { - Sm2out23W::new(self, 5) - } - #[doc = "Bit 6 - Submodule 3 Software Controlled Output 45"] - #[inline(always)] - pub fn sm3out45(&mut self) -> Sm3out45W { - Sm3out45W::new(self, 6) - } - #[doc = "Bit 7 - Submodule 3 Software Controlled Output 23"] - #[inline(always)] - pub fn sm3out23(&mut self) -> Sm3out23W { - Sm3out23W::new(self, 7) - } -} -#[doc = "Software Controlled Output Register\n\nYou can [`read`](crate::Reg::read) this register and get [`swcout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swcout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SwcoutSpec; -impl crate::RegisterSpec for SwcoutSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`swcout::R`](R) reader structure"] -impl crate::Readable for SwcoutSpec {} -#[doc = "`write(|w| ..)` method takes [`swcout::W`](W) writer structure"] -impl crate::Writable for SwcoutSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWCOUT to value 0"] -impl crate::Resettable for SwcoutSpec {} diff --git a/mcxa276-pac/src/fmc0.rs b/mcxa276-pac/src/fmc0.rs deleted file mode 100644 index aca9ec192..000000000 --- a/mcxa276-pac/src/fmc0.rs +++ /dev/null @@ -1,18 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x20], - remap: Remap, -} -impl RegisterBlock { - #[doc = "0x20 - Data Remap"] - #[inline(always)] - pub const fn remap(&self) -> &Remap { - &self.remap - } -} -#[doc = "REMAP (rw) register accessor: Data Remap\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap`] module"] -#[doc(alias = "REMAP")] -pub type Remap = crate::Reg; -#[doc = "Data Remap"] -pub mod remap; diff --git a/mcxa276-pac/src/fmc0/remap.rs b/mcxa276-pac/src/fmc0/remap.rs deleted file mode 100644 index 80438fc5f..000000000 --- a/mcxa276-pac/src/fmc0/remap.rs +++ /dev/null @@ -1,112 +0,0 @@ -#[doc = "Register `REMAP` reader"] -pub type R = crate::R; -#[doc = "Register `REMAP` writer"] -pub type W = crate::W; -#[doc = "Remap Lock Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Remaplk { - #[doc = "0: Lock disabled: can write to REMAP"] - LockDisabled = 0, - #[doc = "1: Lock enabled: cannot write to REMAP"] - LockEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Remaplk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REMAPLK` reader - Remap Lock Enable"] -pub type RemaplkR = crate::BitReader; -impl RemaplkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Remaplk { - match self.bits { - false => Remaplk::LockDisabled, - true => Remaplk::LockEnabled, - } - } - #[doc = "Lock disabled: can write to REMAP"] - #[inline(always)] - pub fn is_lock_disabled(&self) -> bool { - *self == Remaplk::LockDisabled - } - #[doc = "Lock enabled: cannot write to REMAP"] - #[inline(always)] - pub fn is_lock_enabled(&self) -> bool { - *self == Remaplk::LockEnabled - } -} -#[doc = "Field `REMAPLK` writer - Remap Lock Enable"] -pub type RemaplkW<'a, REG> = crate::BitWriter<'a, REG, Remaplk>; -impl<'a, REG> RemaplkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Lock disabled: can write to REMAP"] - #[inline(always)] - pub fn lock_disabled(self) -> &'a mut crate::W { - self.variant(Remaplk::LockDisabled) - } - #[doc = "Lock enabled: cannot write to REMAP"] - #[inline(always)] - pub fn lock_enabled(self) -> &'a mut crate::W { - self.variant(Remaplk::LockEnabled) - } -} -#[doc = "Field `LIM` reader - LIM Remapping Address"] -pub type LimR = crate::FieldReader; -#[doc = "Field `LIM` writer - LIM Remapping Address"] -pub type LimW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `LIMDP` reader - LIMDP Remapping Address"] -pub type LimdpR = crate::FieldReader; -#[doc = "Field `LIMDP` writer - LIMDP Remapping Address"] -pub type LimdpW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bit 0 - Remap Lock Enable"] - #[inline(always)] - pub fn remaplk(&self) -> RemaplkR { - RemaplkR::new((self.bits & 1) != 0) - } - #[doc = "Bits 16:22 - LIM Remapping Address"] - #[inline(always)] - pub fn lim(&self) -> LimR { - LimR::new(((self.bits >> 16) & 0x7f) as u8) - } - #[doc = "Bits 24:30 - LIMDP Remapping Address"] - #[inline(always)] - pub fn limdp(&self) -> LimdpR { - LimdpR::new(((self.bits >> 24) & 0x7f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Remap Lock Enable"] - #[inline(always)] - pub fn remaplk(&mut self) -> RemaplkW { - RemaplkW::new(self, 0) - } - #[doc = "Bits 16:22 - LIM Remapping Address"] - #[inline(always)] - pub fn lim(&mut self) -> LimW { - LimW::new(self, 16) - } - #[doc = "Bits 24:30 - LIMDP Remapping Address"] - #[inline(always)] - pub fn limdp(&mut self) -> LimdpW { - LimdpW::new(self, 24) - } -} -#[doc = "Data Remap\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RemapSpec; -impl crate::RegisterSpec for RemapSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`remap::R`](R) reader structure"] -impl crate::Readable for RemapSpec {} -#[doc = "`write(|w| ..)` method takes [`remap::W`](W) writer structure"] -impl crate::Writable for RemapSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets REMAP to value 0"] -impl crate::Resettable for RemapSpec {} diff --git a/mcxa276-pac/src/fmu0.rs b/mcxa276-pac/src/fmu0.rs deleted file mode 100644 index 774fc87f3..000000000 --- a/mcxa276-pac/src/fmu0.rs +++ /dev/null @@ -1,57 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - fstat: Fstat, - fcnfg: Fcnfg, - fctrl: Fctrl, - _reserved3: [u8; 0x04], - fccob: [Fccob; 8], -} -impl RegisterBlock { - #[doc = "0x00 - Flash Status Register"] - #[inline(always)] - pub const fn fstat(&self) -> &Fstat { - &self.fstat - } - #[doc = "0x04 - Flash Configuration Register"] - #[inline(always)] - pub const fn fcnfg(&self) -> &Fcnfg { - &self.fcnfg - } - #[doc = "0x08 - Flash Control Register"] - #[inline(always)] - pub const fn fctrl(&self) -> &Fctrl { - &self.fctrl - } - #[doc = "0x10..0x30 - Flash Common Command Object Registers"] - #[inline(always)] - pub const fn fccob(&self, n: usize) -> &Fccob { - &self.fccob[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x10..0x30 - Flash Common Command Object Registers"] - #[inline(always)] - pub fn fccob_iter(&self) -> impl Iterator { - self.fccob.iter() - } -} -#[doc = "FSTAT (rw) register accessor: Flash Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fstat`] module"] -#[doc(alias = "FSTAT")] -pub type Fstat = crate::Reg; -#[doc = "Flash Status Register"] -pub mod fstat; -#[doc = "FCNFG (rw) register accessor: Flash Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fcnfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcnfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcnfg`] module"] -#[doc(alias = "FCNFG")] -pub type Fcnfg = crate::Reg; -#[doc = "Flash Configuration Register"] -pub mod fcnfg; -#[doc = "FCTRL (rw) register accessor: Flash Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fctrl`] module"] -#[doc(alias = "FCTRL")] -pub type Fctrl = crate::Reg; -#[doc = "Flash Control Register"] -pub mod fctrl; -#[doc = "FCCOB (rw) register accessor: Flash Common Command Object Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`fccob::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fccob::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fccob`] module"] -#[doc(alias = "FCCOB")] -pub type Fccob = crate::Reg; -#[doc = "Flash Common Command Object Registers"] -pub mod fccob; diff --git a/mcxa276-pac/src/fmu0/fccob.rs b/mcxa276-pac/src/fmu0/fccob.rs deleted file mode 100644 index c515ff9c4..000000000 --- a/mcxa276-pac/src/fmu0/fccob.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `FCCOB%s` reader"] -pub type R = crate::R; -#[doc = "Register `FCCOB%s` writer"] -pub type W = crate::W; -#[doc = "Field `CCOBn` reader - CCOBn"] -pub type CcobnR = crate::FieldReader; -#[doc = "Field `CCOBn` writer - CCOBn"] -pub type CcobnW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - CCOBn"] - #[inline(always)] - pub fn ccobn(&self) -> CcobnR { - CcobnR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - CCOBn"] - #[inline(always)] - pub fn ccobn(&mut self) -> CcobnW { - CcobnW::new(self, 0) - } -} -#[doc = "Flash Common Command Object Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`fccob::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fccob::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FccobSpec; -impl crate::RegisterSpec for FccobSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fccob::R`](R) reader structure"] -impl crate::Readable for FccobSpec {} -#[doc = "`write(|w| ..)` method takes [`fccob::W`](W) writer structure"] -impl crate::Writable for FccobSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCCOB%s to value 0"] -impl crate::Resettable for FccobSpec {} diff --git a/mcxa276-pac/src/fmu0/fcnfg.rs b/mcxa276-pac/src/fmu0/fcnfg.rs deleted file mode 100644 index b2add0044..000000000 --- a/mcxa276-pac/src/fmu0/fcnfg.rs +++ /dev/null @@ -1,282 +0,0 @@ -#[doc = "Register `FCNFG` reader"] -pub type R = crate::R; -#[doc = "Register `FCNFG` writer"] -pub type W = crate::W; -#[doc = "Command Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ccie { - #[doc = "0: Command complete interrupt disabled"] - Ccie0 = 0, - #[doc = "1: Command complete interrupt enabled"] - Ccie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ccie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CCIE` reader - Command Complete Interrupt Enable"] -pub type CcieR = crate::BitReader; -impl CcieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ccie { - match self.bits { - false => Ccie::Ccie0, - true => Ccie::Ccie1, - } - } - #[doc = "Command complete interrupt disabled"] - #[inline(always)] - pub fn is_ccie0(&self) -> bool { - *self == Ccie::Ccie0 - } - #[doc = "Command complete interrupt enabled"] - #[inline(always)] - pub fn is_ccie1(&self) -> bool { - *self == Ccie::Ccie1 - } -} -#[doc = "Field `CCIE` writer - Command Complete Interrupt Enable"] -pub type CcieW<'a, REG> = crate::BitWriter<'a, REG, Ccie>; -impl<'a, REG> CcieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Command complete interrupt disabled"] - #[inline(always)] - pub fn ccie0(self) -> &'a mut crate::W { - self.variant(Ccie::Ccie0) - } - #[doc = "Command complete interrupt enabled"] - #[inline(always)] - pub fn ccie1(self) -> &'a mut crate::W { - self.variant(Ccie::Ccie1) - } -} -#[doc = "Mass Erase Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ersreq { - #[doc = "0: No request or request complete"] - Ersreq0 = 0, - #[doc = "1: Request to run the Mass Erase operation"] - Ersreq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ersreq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERSREQ` reader - Mass Erase Request"] -pub type ErsreqR = crate::BitReader; -impl ErsreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ersreq { - match self.bits { - false => Ersreq::Ersreq0, - true => Ersreq::Ersreq1, - } - } - #[doc = "No request or request complete"] - #[inline(always)] - pub fn is_ersreq0(&self) -> bool { - *self == Ersreq::Ersreq0 - } - #[doc = "Request to run the Mass Erase operation"] - #[inline(always)] - pub fn is_ersreq1(&self) -> bool { - *self == Ersreq::Ersreq1 - } -} -#[doc = "Double Bit Fault Detect Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dfdie { - #[doc = "0: Double bit fault detect interrupt disabled"] - Dfdie0 = 0, - #[doc = "1: Double bit fault detect interrupt enabled"] - Dfdie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dfdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DFDIE` reader - Double Bit Fault Detect Interrupt Enable"] -pub type DfdieR = crate::BitReader; -impl DfdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dfdie { - match self.bits { - false => Dfdie::Dfdie0, - true => Dfdie::Dfdie1, - } - } - #[doc = "Double bit fault detect interrupt disabled"] - #[inline(always)] - pub fn is_dfdie0(&self) -> bool { - *self == Dfdie::Dfdie0 - } - #[doc = "Double bit fault detect interrupt enabled"] - #[inline(always)] - pub fn is_dfdie1(&self) -> bool { - *self == Dfdie::Dfdie1 - } -} -#[doc = "Field `DFDIE` writer - Double Bit Fault Detect Interrupt Enable"] -pub type DfdieW<'a, REG> = crate::BitWriter<'a, REG, Dfdie>; -impl<'a, REG> DfdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Double bit fault detect interrupt disabled"] - #[inline(always)] - pub fn dfdie0(self) -> &'a mut crate::W { - self.variant(Dfdie::Dfdie0) - } - #[doc = "Double bit fault detect interrupt enabled"] - #[inline(always)] - pub fn dfdie1(self) -> &'a mut crate::W { - self.variant(Dfdie::Dfdie1) - } -} -#[doc = "Erase IFR Sector Enable - Block 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ersien0 { - #[doc = "0: Block 0 IFR Sector X is protected from erase by ERSSCR command"] - Ersien00 = 0, - #[doc = "1: Block 0 IFR Sector X is not protected from erase by ERSSCR command"] - Ersien01 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ersien0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ersien0 { - type Ux = u8; -} -impl crate::IsEnum for Ersien0 {} -#[doc = "Field `ERSIEN0` reader - Erase IFR Sector Enable - Block 0"] -pub type Ersien0R = crate::FieldReader; -impl Ersien0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ersien0::Ersien00), - 1 => Some(Ersien0::Ersien01), - _ => None, - } - } - #[doc = "Block 0 IFR Sector X is protected from erase by ERSSCR command"] - #[inline(always)] - pub fn is_ersien00(&self) -> bool { - *self == Ersien0::Ersien00 - } - #[doc = "Block 0 IFR Sector X is not protected from erase by ERSSCR command"] - #[inline(always)] - pub fn is_ersien01(&self) -> bool { - *self == Ersien0::Ersien01 - } -} -#[doc = "Erase IFR Sector Enable - Block 1 (for dual block configs)\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ersien1 { - #[doc = "0: Block 1 IFR Sector X is protected from erase by ERSSCR command"] - Ersien10 = 0, - #[doc = "1: Block 1 IFR Sector X is not protected from erase by ERSSCR command"] - Ersien11 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ersien1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ersien1 { - type Ux = u8; -} -impl crate::IsEnum for Ersien1 {} -#[doc = "Field `ERSIEN1` reader - Erase IFR Sector Enable - Block 1 (for dual block configs)"] -pub type Ersien1R = crate::FieldReader; -impl Ersien1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ersien1::Ersien10), - 1 => Some(Ersien1::Ersien11), - _ => None, - } - } - #[doc = "Block 1 IFR Sector X is protected from erase by ERSSCR command"] - #[inline(always)] - pub fn is_ersien10(&self) -> bool { - *self == Ersien1::Ersien10 - } - #[doc = "Block 1 IFR Sector X is not protected from erase by ERSSCR command"] - #[inline(always)] - pub fn is_ersien11(&self) -> bool { - *self == Ersien1::Ersien11 - } -} -impl R { - #[doc = "Bit 7 - Command Complete Interrupt Enable"] - #[inline(always)] - pub fn ccie(&self) -> CcieR { - CcieR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Mass Erase Request"] - #[inline(always)] - pub fn ersreq(&self) -> ErsreqR { - ErsreqR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Enable"] - #[inline(always)] - pub fn dfdie(&self) -> DfdieR { - DfdieR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bits 24:27 - Erase IFR Sector Enable - Block 0"] - #[inline(always)] - pub fn ersien0(&self) -> Ersien0R { - Ersien0R::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bits 28:31 - Erase IFR Sector Enable - Block 1 (for dual block configs)"] - #[inline(always)] - pub fn ersien1(&self) -> Ersien1R { - Ersien1R::new(((self.bits >> 28) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 7 - Command Complete Interrupt Enable"] - #[inline(always)] - pub fn ccie(&mut self) -> CcieW { - CcieW::new(self, 7) - } - #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Enable"] - #[inline(always)] - pub fn dfdie(&mut self) -> DfdieW { - DfdieW::new(self, 16) - } -} -#[doc = "Flash Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fcnfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcnfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FcnfgSpec; -impl crate::RegisterSpec for FcnfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fcnfg::R`](R) reader structure"] -impl crate::Readable for FcnfgSpec {} -#[doc = "`write(|w| ..)` method takes [`fcnfg::W`](W) writer structure"] -impl crate::Writable for FcnfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCNFG to value 0"] -impl crate::Resettable for FcnfgSpec {} diff --git a/mcxa276-pac/src/fmu0/fctrl.rs b/mcxa276-pac/src/fmu0/fctrl.rs deleted file mode 100644 index 8504ae006..000000000 --- a/mcxa276-pac/src/fmu0/fctrl.rs +++ /dev/null @@ -1,226 +0,0 @@ -#[doc = "Register `FCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `FCTRL` writer"] -pub type W = crate::W; -#[doc = "Field `RWSC` reader - Read Wait-State Control"] -pub type RwscR = crate::FieldReader; -#[doc = "Field `RWSC` writer - Read Wait-State Control"] -pub type RwscW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Low speed active mode\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lsactive { - #[doc = "0: Full speed active mode requested"] - Lsactive0 = 0, - #[doc = "1: Low speed active mode requested"] - Lsactive1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lsactive) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LSACTIVE` reader - Low speed active mode"] -pub type LsactiveR = crate::BitReader; -impl LsactiveR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lsactive { - match self.bits { - false => Lsactive::Lsactive0, - true => Lsactive::Lsactive1, - } - } - #[doc = "Full speed active mode requested"] - #[inline(always)] - pub fn is_lsactive0(&self) -> bool { - *self == Lsactive::Lsactive0 - } - #[doc = "Low speed active mode requested"] - #[inline(always)] - pub fn is_lsactive1(&self) -> bool { - *self == Lsactive::Lsactive1 - } -} -#[doc = "Field `LSACTIVE` writer - Low speed active mode"] -pub type LsactiveW<'a, REG> = crate::BitWriter<'a, REG, Lsactive>; -impl<'a, REG> LsactiveW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Full speed active mode requested"] - #[inline(always)] - pub fn lsactive0(self) -> &'a mut crate::W { - self.variant(Lsactive::Lsactive0) - } - #[doc = "Low speed active mode requested"] - #[inline(always)] - pub fn lsactive1(self) -> &'a mut crate::W { - self.variant(Lsactive::Lsactive1) - } -} -#[doc = "Force Double Bit Fault Detect\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fdfd { - #[doc = "0: FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"] - Fdfd0 = 0, - #[doc = "1: FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."] - Fdfd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fdfd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FDFD` reader - Force Double Bit Fault Detect"] -pub type FdfdR = crate::BitReader; -impl FdfdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fdfd { - match self.bits { - false => Fdfd::Fdfd0, - true => Fdfd::Fdfd1, - } - } - #[doc = "FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"] - #[inline(always)] - pub fn is_fdfd0(&self) -> bool { - *self == Fdfd::Fdfd0 - } - #[doc = "FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."] - #[inline(always)] - pub fn is_fdfd1(&self) -> bool { - *self == Fdfd::Fdfd1 - } -} -#[doc = "Field `FDFD` writer - Force Double Bit Fault Detect"] -pub type FdfdW<'a, REG> = crate::BitWriter<'a, REG, Fdfd>; -impl<'a, REG> FdfdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller"] - #[inline(always)] - pub fn fdfd0(self) -> &'a mut crate::W { - self.variant(Fdfd::Fdfd0) - } - #[doc = "FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."] - #[inline(always)] - pub fn fdfd1(self) -> &'a mut crate::W { - self.variant(Fdfd::Fdfd1) - } -} -#[doc = "Abort Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Abtreq { - #[doc = "0: No request to abort a command write sequence"] - Abtreq0 = 0, - #[doc = "1: Request to abort a command write sequence"] - Abtreq1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Abtreq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ABTREQ` reader - Abort Request"] -pub type AbtreqR = crate::BitReader; -impl AbtreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Abtreq { - match self.bits { - false => Abtreq::Abtreq0, - true => Abtreq::Abtreq1, - } - } - #[doc = "No request to abort a command write sequence"] - #[inline(always)] - pub fn is_abtreq0(&self) -> bool { - *self == Abtreq::Abtreq0 - } - #[doc = "Request to abort a command write sequence"] - #[inline(always)] - pub fn is_abtreq1(&self) -> bool { - *self == Abtreq::Abtreq1 - } -} -#[doc = "Field `ABTREQ` writer - Abort Request"] -pub type AbtreqW<'a, REG> = crate::BitWriter<'a, REG, Abtreq>; -impl<'a, REG> AbtreqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No request to abort a command write sequence"] - #[inline(always)] - pub fn abtreq0(self) -> &'a mut crate::W { - self.variant(Abtreq::Abtreq0) - } - #[doc = "Request to abort a command write sequence"] - #[inline(always)] - pub fn abtreq1(self) -> &'a mut crate::W { - self.variant(Abtreq::Abtreq1) - } -} -impl R { - #[doc = "Bits 0:3 - Read Wait-State Control"] - #[inline(always)] - pub fn rwsc(&self) -> RwscR { - RwscR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 8 - Low speed active mode"] - #[inline(always)] - pub fn lsactive(&self) -> LsactiveR { - LsactiveR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 16 - Force Double Bit Fault Detect"] - #[inline(always)] - pub fn fdfd(&self) -> FdfdR { - FdfdR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 24 - Abort Request"] - #[inline(always)] - pub fn abtreq(&self) -> AbtreqR { - AbtreqR::new(((self.bits >> 24) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Read Wait-State Control"] - #[inline(always)] - pub fn rwsc(&mut self) -> RwscW { - RwscW::new(self, 0) - } - #[doc = "Bit 8 - Low speed active mode"] - #[inline(always)] - pub fn lsactive(&mut self) -> LsactiveW { - LsactiveW::new(self, 8) - } - #[doc = "Bit 16 - Force Double Bit Fault Detect"] - #[inline(always)] - pub fn fdfd(&mut self) -> FdfdW { - FdfdW::new(self, 16) - } - #[doc = "Bit 24 - Abort Request"] - #[inline(always)] - pub fn abtreq(&mut self) -> AbtreqW { - AbtreqW::new(self, 24) - } -} -#[doc = "Flash Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FctrlSpec; -impl crate::RegisterSpec for FctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fctrl::R`](R) reader structure"] -impl crate::Readable for FctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`fctrl::W`](W) writer structure"] -impl crate::Writable for FctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCTRL to value 0x0100"] -impl crate::Resettable for FctrlSpec { - const RESET_VALUE: u32 = 0x0100; -} diff --git a/mcxa276-pac/src/fmu0/fstat.rs b/mcxa276-pac/src/fmu0/fstat.rs deleted file mode 100644 index 7dc1014d4..000000000 --- a/mcxa276-pac/src/fmu0/fstat.rs +++ /dev/null @@ -1,713 +0,0 @@ -#[doc = "Register `FSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `FSTAT` writer"] -pub type W = crate::W; -#[doc = "Command Fail Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fail { - #[doc = "0: Error not detected"] - Fail0 = 0, - #[doc = "1: Error detected"] - Fail1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fail) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FAIL` reader - Command Fail Flag"] -pub type FailR = crate::BitReader; -impl FailR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fail { - match self.bits { - false => Fail::Fail0, - true => Fail::Fail1, - } - } - #[doc = "Error not detected"] - #[inline(always)] - pub fn is_fail0(&self) -> bool { - *self == Fail::Fail0 - } - #[doc = "Error detected"] - #[inline(always)] - pub fn is_fail1(&self) -> bool { - *self == Fail::Fail1 - } -} -#[doc = "Command Abort Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmdabt { - #[doc = "0: No command abort detected"] - Cmdabt0 = 0, - #[doc = "1: Command abort detected"] - Cmdabt1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmdabt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMDABT` reader - Command Abort Flag"] -pub type CmdabtR = crate::BitReader; -impl CmdabtR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmdabt { - match self.bits { - false => Cmdabt::Cmdabt0, - true => Cmdabt::Cmdabt1, - } - } - #[doc = "No command abort detected"] - #[inline(always)] - pub fn is_cmdabt0(&self) -> bool { - *self == Cmdabt::Cmdabt0 - } - #[doc = "Command abort detected"] - #[inline(always)] - pub fn is_cmdabt1(&self) -> bool { - *self == Cmdabt::Cmdabt1 - } -} -#[doc = "Field `CMDABT` writer - Command Abort Flag"] -pub type CmdabtW<'a, REG> = crate::BitWriter1C<'a, REG, Cmdabt>; -impl<'a, REG> CmdabtW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No command abort detected"] - #[inline(always)] - pub fn cmdabt0(self) -> &'a mut crate::W { - self.variant(Cmdabt::Cmdabt0) - } - #[doc = "Command abort detected"] - #[inline(always)] - pub fn cmdabt1(self) -> &'a mut crate::W { - self.variant(Cmdabt::Cmdabt1) - } -} -#[doc = "Command Protection Violation Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pviol { - #[doc = "0: No protection violation detected"] - Pviol0 = 0, - #[doc = "1: Protection violation detected"] - Pviol1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pviol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PVIOL` reader - Command Protection Violation Flag"] -pub type PviolR = crate::BitReader; -impl PviolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pviol { - match self.bits { - false => Pviol::Pviol0, - true => Pviol::Pviol1, - } - } - #[doc = "No protection violation detected"] - #[inline(always)] - pub fn is_pviol0(&self) -> bool { - *self == Pviol::Pviol0 - } - #[doc = "Protection violation detected"] - #[inline(always)] - pub fn is_pviol1(&self) -> bool { - *self == Pviol::Pviol1 - } -} -#[doc = "Field `PVIOL` writer - Command Protection Violation Flag"] -pub type PviolW<'a, REG> = crate::BitWriter1C<'a, REG, Pviol>; -impl<'a, REG> PviolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No protection violation detected"] - #[inline(always)] - pub fn pviol0(self) -> &'a mut crate::W { - self.variant(Pviol::Pviol0) - } - #[doc = "Protection violation detected"] - #[inline(always)] - pub fn pviol1(self) -> &'a mut crate::W { - self.variant(Pviol::Pviol1) - } -} -#[doc = "Command Access Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Accerr { - #[doc = "0: No access error detected"] - Accerr0 = 0, - #[doc = "1: Access error detected"] - Accerr1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Accerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ACCERR` reader - Command Access Error Flag"] -pub type AccerrR = crate::BitReader; -impl AccerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Accerr { - match self.bits { - false => Accerr::Accerr0, - true => Accerr::Accerr1, - } - } - #[doc = "No access error detected"] - #[inline(always)] - pub fn is_accerr0(&self) -> bool { - *self == Accerr::Accerr0 - } - #[doc = "Access error detected"] - #[inline(always)] - pub fn is_accerr1(&self) -> bool { - *self == Accerr::Accerr1 - } -} -#[doc = "Field `ACCERR` writer - Command Access Error Flag"] -pub type AccerrW<'a, REG> = crate::BitWriter1C<'a, REG, Accerr>; -impl<'a, REG> AccerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No access error detected"] - #[inline(always)] - pub fn accerr0(self) -> &'a mut crate::W { - self.variant(Accerr::Accerr0) - } - #[doc = "Access error detected"] - #[inline(always)] - pub fn accerr1(self) -> &'a mut crate::W { - self.variant(Accerr::Accerr1) - } -} -#[doc = "Command Write Sequence Abort Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cwsabt { - #[doc = "0: Command write sequence not aborted"] - Cwsabt0 = 0, - #[doc = "1: Command write sequence aborted"] - Cwsabt1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cwsabt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CWSABT` reader - Command Write Sequence Abort Flag"] -pub type CwsabtR = crate::BitReader; -impl CwsabtR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cwsabt { - match self.bits { - false => Cwsabt::Cwsabt0, - true => Cwsabt::Cwsabt1, - } - } - #[doc = "Command write sequence not aborted"] - #[inline(always)] - pub fn is_cwsabt0(&self) -> bool { - *self == Cwsabt::Cwsabt0 - } - #[doc = "Command write sequence aborted"] - #[inline(always)] - pub fn is_cwsabt1(&self) -> bool { - *self == Cwsabt::Cwsabt1 - } -} -#[doc = "Field `CWSABT` writer - Command Write Sequence Abort Flag"] -pub type CwsabtW<'a, REG> = crate::BitWriter1C<'a, REG, Cwsabt>; -impl<'a, REG> CwsabtW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Command write sequence not aborted"] - #[inline(always)] - pub fn cwsabt0(self) -> &'a mut crate::W { - self.variant(Cwsabt::Cwsabt0) - } - #[doc = "Command write sequence aborted"] - #[inline(always)] - pub fn cwsabt1(self) -> &'a mut crate::W { - self.variant(Cwsabt::Cwsabt1) - } -} -#[doc = "Command Complete Interrupt Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ccif { - #[doc = "0: Flash command, initialization, or power mode recovery in progress"] - Ccif0 = 0, - #[doc = "1: Flash command, initialization, or power mode recovery has completed"] - Ccif1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ccif) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CCIF` reader - Command Complete Interrupt Flag"] -pub type CcifR = crate::BitReader; -impl CcifR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ccif { - match self.bits { - false => Ccif::Ccif0, - true => Ccif::Ccif1, - } - } - #[doc = "Flash command, initialization, or power mode recovery in progress"] - #[inline(always)] - pub fn is_ccif0(&self) -> bool { - *self == Ccif::Ccif0 - } - #[doc = "Flash command, initialization, or power mode recovery has completed"] - #[inline(always)] - pub fn is_ccif1(&self) -> bool { - *self == Ccif::Ccif1 - } -} -#[doc = "Field `CCIF` writer - Command Complete Interrupt Flag"] -pub type CcifW<'a, REG> = crate::BitWriter1C<'a, REG, Ccif>; -impl<'a, REG> CcifW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Flash command, initialization, or power mode recovery in progress"] - #[inline(always)] - pub fn ccif0(self) -> &'a mut crate::W { - self.variant(Ccif::Ccif0) - } - #[doc = "Flash command, initialization, or power mode recovery has completed"] - #[inline(always)] - pub fn ccif1(self) -> &'a mut crate::W { - self.variant(Ccif::Ccif1) - } -} -#[doc = "Command protection level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmdprt { - #[doc = "0: Secure, normal access"] - Cmdprt00 = 0, - #[doc = "1: Secure, privileged access"] - Cmdprt01 = 1, - #[doc = "2: Nonsecure, normal access"] - Cmdprt10 = 2, - #[doc = "3: Nonsecure, privileged access"] - Cmdprt11 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmdprt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmdprt { - type Ux = u8; -} -impl crate::IsEnum for Cmdprt {} -#[doc = "Field `CMDPRT` reader - Command protection level"] -pub type CmdprtR = crate::FieldReader; -impl CmdprtR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmdprt { - match self.bits { - 0 => Cmdprt::Cmdprt00, - 1 => Cmdprt::Cmdprt01, - 2 => Cmdprt::Cmdprt10, - 3 => Cmdprt::Cmdprt11, - _ => unreachable!(), - } - } - #[doc = "Secure, normal access"] - #[inline(always)] - pub fn is_cmdprt00(&self) -> bool { - *self == Cmdprt::Cmdprt00 - } - #[doc = "Secure, privileged access"] - #[inline(always)] - pub fn is_cmdprt01(&self) -> bool { - *self == Cmdprt::Cmdprt01 - } - #[doc = "Nonsecure, normal access"] - #[inline(always)] - pub fn is_cmdprt10(&self) -> bool { - *self == Cmdprt::Cmdprt10 - } - #[doc = "Nonsecure, privileged access"] - #[inline(always)] - pub fn is_cmdprt11(&self) -> bool { - *self == Cmdprt::Cmdprt11 - } -} -#[doc = "Command protection status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmdp { - #[doc = "0: Command protection level and domain ID are stale"] - Cmdp0 = 0, - #[doc = "1: Command protection level (CMDPRT) and domain ID (CMDDID) are set"] - Cmdp1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmdp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMDP` reader - Command protection status flag"] -pub type CmdpR = crate::BitReader; -impl CmdpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmdp { - match self.bits { - false => Cmdp::Cmdp0, - true => Cmdp::Cmdp1, - } - } - #[doc = "Command protection level and domain ID are stale"] - #[inline(always)] - pub fn is_cmdp0(&self) -> bool { - *self == Cmdp::Cmdp0 - } - #[doc = "Command protection level (CMDPRT) and domain ID (CMDDID) are set"] - #[inline(always)] - pub fn is_cmdp1(&self) -> bool { - *self == Cmdp::Cmdp1 - } -} -#[doc = "Field `CMDDID` reader - Command domain ID"] -pub type CmddidR = crate::FieldReader; -#[doc = "Double Bit Fault Detect Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dfdif { - #[doc = "0: Double bit fault not detected during a valid flash read access"] - Dfdif0 = 0, - #[doc = "1: Double bit fault detected (or FCTRL\\[FDFD\\] is set) during a valid flash read access"] - Dfdif1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dfdif) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DFDIF` reader - Double Bit Fault Detect Interrupt Flag"] -pub type DfdifR = crate::BitReader; -impl DfdifR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dfdif { - match self.bits { - false => Dfdif::Dfdif0, - true => Dfdif::Dfdif1, - } - } - #[doc = "Double bit fault not detected during a valid flash read access"] - #[inline(always)] - pub fn is_dfdif0(&self) -> bool { - *self == Dfdif::Dfdif0 - } - #[doc = "Double bit fault detected (or FCTRL\\[FDFD\\] is set) during a valid flash read access"] - #[inline(always)] - pub fn is_dfdif1(&self) -> bool { - *self == Dfdif::Dfdif1 - } -} -#[doc = "Field `DFDIF` writer - Double Bit Fault Detect Interrupt Flag"] -pub type DfdifW<'a, REG> = crate::BitWriter1C<'a, REG, Dfdif>; -impl<'a, REG> DfdifW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Double bit fault not detected during a valid flash read access"] - #[inline(always)] - pub fn dfdif0(self) -> &'a mut crate::W { - self.variant(Dfdif::Dfdif0) - } - #[doc = "Double bit fault detected (or FCTRL\\[FDFD\\] is set) during a valid flash read access"] - #[inline(always)] - pub fn dfdif1(self) -> &'a mut crate::W { - self.variant(Dfdif::Dfdif1) - } -} -#[doc = "Salvage Used for Erase operation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SalvUsed { - #[doc = "0: Salvage not used during last operation"] - SalvUsed0 = 0, - #[doc = "1: Salvage used during the last erase operation"] - SalvUsed1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SalvUsed) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SALV_USED` reader - Salvage Used for Erase operation"] -pub type SalvUsedR = crate::BitReader; -impl SalvUsedR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SalvUsed { - match self.bits { - false => SalvUsed::SalvUsed0, - true => SalvUsed::SalvUsed1, - } - } - #[doc = "Salvage not used during last operation"] - #[inline(always)] - pub fn is_salv_used0(&self) -> bool { - *self == SalvUsed::SalvUsed0 - } - #[doc = "Salvage used during the last erase operation"] - #[inline(always)] - pub fn is_salv_used1(&self) -> bool { - *self == SalvUsed::SalvUsed1 - } -} -#[doc = "Program-Erase Write Enable Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pewen { - #[doc = "0: Writes are not enabled"] - Pewen00 = 0, - #[doc = "1: Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)"] - Pewen01 = 1, - #[doc = "2: Writes are enabled for one flash or IFR page (page programming)"] - Pewen10 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pewen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pewen { - type Ux = u8; -} -impl crate::IsEnum for Pewen {} -#[doc = "Field `PEWEN` reader - Program-Erase Write Enable Control"] -pub type PewenR = crate::FieldReader; -impl PewenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Pewen::Pewen00), - 1 => Some(Pewen::Pewen01), - 2 => Some(Pewen::Pewen10), - _ => None, - } - } - #[doc = "Writes are not enabled"] - #[inline(always)] - pub fn is_pewen00(&self) -> bool { - *self == Pewen::Pewen00 - } - #[doc = "Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)"] - #[inline(always)] - pub fn is_pewen01(&self) -> bool { - *self == Pewen::Pewen01 - } - #[doc = "Writes are enabled for one flash or IFR page (page programming)"] - #[inline(always)] - pub fn is_pewen10(&self) -> bool { - *self == Pewen::Pewen10 - } -} -#[doc = "Program-Erase Ready Control/Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Perdy { - #[doc = "0: Program or sector erase command operation not stalled"] - Perdy0 = 0, - #[doc = "1: Program or sector erase command operation ready to execute"] - Perdy1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Perdy) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PERDY` reader - Program-Erase Ready Control/Status Flag"] -pub type PerdyR = crate::BitReader; -impl PerdyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Perdy { - match self.bits { - false => Perdy::Perdy0, - true => Perdy::Perdy1, - } - } - #[doc = "Program or sector erase command operation not stalled"] - #[inline(always)] - pub fn is_perdy0(&self) -> bool { - *self == Perdy::Perdy0 - } - #[doc = "Program or sector erase command operation ready to execute"] - #[inline(always)] - pub fn is_perdy1(&self) -> bool { - *self == Perdy::Perdy1 - } -} -#[doc = "Field `PERDY` writer - Program-Erase Ready Control/Status Flag"] -pub type PerdyW<'a, REG> = crate::BitWriter1C<'a, REG, Perdy>; -impl<'a, REG> PerdyW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Program or sector erase command operation not stalled"] - #[inline(always)] - pub fn perdy0(self) -> &'a mut crate::W { - self.variant(Perdy::Perdy0) - } - #[doc = "Program or sector erase command operation ready to execute"] - #[inline(always)] - pub fn perdy1(self) -> &'a mut crate::W { - self.variant(Perdy::Perdy1) - } -} -impl R { - #[doc = "Bit 0 - Command Fail Flag"] - #[inline(always)] - pub fn fail(&self) -> FailR { - FailR::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - Command Abort Flag"] - #[inline(always)] - pub fn cmdabt(&self) -> CmdabtR { - CmdabtR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - Command Protection Violation Flag"] - #[inline(always)] - pub fn pviol(&self) -> PviolR { - PviolR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Command Access Error Flag"] - #[inline(always)] - pub fn accerr(&self) -> AccerrR { - AccerrR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Command Write Sequence Abort Flag"] - #[inline(always)] - pub fn cwsabt(&self) -> CwsabtR { - CwsabtR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Command Complete Interrupt Flag"] - #[inline(always)] - pub fn ccif(&self) -> CcifR { - CcifR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Command protection level"] - #[inline(always)] - pub fn cmdprt(&self) -> CmdprtR { - CmdprtR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 11 - Command protection status flag"] - #[inline(always)] - pub fn cmdp(&self) -> CmdpR { - CmdpR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15 - Command domain ID"] - #[inline(always)] - pub fn cmddid(&self) -> CmddidR { - CmddidR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Flag"] - #[inline(always)] - pub fn dfdif(&self) -> DfdifR { - DfdifR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Salvage Used for Erase operation"] - #[inline(always)] - pub fn salv_used(&self) -> SalvUsedR { - SalvUsedR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bits 24:25 - Program-Erase Write Enable Control"] - #[inline(always)] - pub fn pewen(&self) -> PewenR { - PewenR::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bit 31 - Program-Erase Ready Control/Status Flag"] - #[inline(always)] - pub fn perdy(&self) -> PerdyR { - PerdyR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 2 - Command Abort Flag"] - #[inline(always)] - pub fn cmdabt(&mut self) -> CmdabtW { - CmdabtW::new(self, 2) - } - #[doc = "Bit 4 - Command Protection Violation Flag"] - #[inline(always)] - pub fn pviol(&mut self) -> PviolW { - PviolW::new(self, 4) - } - #[doc = "Bit 5 - Command Access Error Flag"] - #[inline(always)] - pub fn accerr(&mut self) -> AccerrW { - AccerrW::new(self, 5) - } - #[doc = "Bit 6 - Command Write Sequence Abort Flag"] - #[inline(always)] - pub fn cwsabt(&mut self) -> CwsabtW { - CwsabtW::new(self, 6) - } - #[doc = "Bit 7 - Command Complete Interrupt Flag"] - #[inline(always)] - pub fn ccif(&mut self) -> CcifW { - CcifW::new(self, 7) - } - #[doc = "Bit 16 - Double Bit Fault Detect Interrupt Flag"] - #[inline(always)] - pub fn dfdif(&mut self) -> DfdifW { - DfdifW::new(self, 16) - } - #[doc = "Bit 31 - Program-Erase Ready Control/Status Flag"] - #[inline(always)] - pub fn perdy(&mut self) -> PerdyW { - PerdyW::new(self, 31) - } -} -#[doc = "Flash Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FstatSpec; -impl crate::RegisterSpec for FstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fstat::R`](R) reader structure"] -impl crate::Readable for FstatSpec {} -#[doc = "`write(|w| ..)` method takes [`fstat::W`](W) writer structure"] -impl crate::Writable for FstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8001_00f4; -} -#[doc = "`reset()` method sets FSTAT to value 0x80"] -impl crate::Resettable for FstatSpec { - const RESET_VALUE: u32 = 0x80; -} diff --git a/mcxa276-pac/src/freqme0.rs b/mcxa276-pac/src/freqme0.rs deleted file mode 100644 index 4f6ccd5be..000000000 --- a/mcxa276-pac/src/freqme0.rs +++ /dev/null @@ -1,60 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved_0_read_mode_ctrl_r: [u8; 0x04], - ctrlstat: Ctrlstat, - min: Min, - max: Max, -} -impl RegisterBlock { - #[doc = "0x00 - Control (in Write mode)"] - #[inline(always)] - pub const fn write_mode_ctrl_w(&self) -> &WriteModeCtrlW { - unsafe { &*core::ptr::from_ref(self).cast::().cast() } - } - #[doc = "0x00 - Control (in Read mode)"] - #[inline(always)] - pub const fn read_mode_ctrl_r(&self) -> &ReadModeCtrlR { - unsafe { &*core::ptr::from_ref(self).cast::().cast() } - } - #[doc = "0x04 - Control Status"] - #[inline(always)] - pub const fn ctrlstat(&self) -> &Ctrlstat { - &self.ctrlstat - } - #[doc = "0x08 - Minimum"] - #[inline(always)] - pub const fn min(&self) -> &Min { - &self.min - } - #[doc = "0x0c - Maximum"] - #[inline(always)] - pub const fn max(&self) -> &Max { - &self.max - } -} -#[doc = "READ_MODE_CTRL_R (r) register accessor: Control (in Read mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`read_mode_ctrl_r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read_mode_ctrl_r`] module"] -#[doc(alias = "READ_MODE_CTRL_R")] -pub type ReadModeCtrlR = crate::Reg; -#[doc = "Control (in Read mode)"] -pub mod read_mode_ctrl_r; -#[doc = "WRITE_MODE_CTRL_W (w) register accessor: Control (in Write mode)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_mode_ctrl_w::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@write_mode_ctrl_w`] module"] -#[doc(alias = "WRITE_MODE_CTRL_W")] -pub type WriteModeCtrlW = crate::Reg; -#[doc = "Control (in Write mode)"] -pub mod write_mode_ctrl_w; -#[doc = "CTRLSTAT (rw) register accessor: Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrlstat`] module"] -#[doc(alias = "CTRLSTAT")] -pub type Ctrlstat = crate::Reg; -#[doc = "Control Status"] -pub mod ctrlstat; -#[doc = "MIN (rw) register accessor: Minimum\n\nYou can [`read`](crate::Reg::read) this register and get [`min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@min`] module"] -#[doc(alias = "MIN")] -pub type Min = crate::Reg; -#[doc = "Minimum"] -pub mod min; -#[doc = "MAX (rw) register accessor: Maximum\n\nYou can [`read`](crate::Reg::read) this register and get [`max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max`] module"] -#[doc(alias = "MAX")] -pub type Max = crate::Reg; -#[doc = "Maximum"] -pub mod max; diff --git a/mcxa276-pac/src/freqme0/ctrlstat.rs b/mcxa276-pac/src/freqme0/ctrlstat.rs deleted file mode 100644 index 2e3bb461d..000000000 --- a/mcxa276-pac/src/freqme0/ctrlstat.rs +++ /dev/null @@ -1,505 +0,0 @@ -#[doc = "Register `CTRLSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `CTRLSTAT` writer"] -pub type W = crate::W; -#[doc = "Field `REF_SCALE` reader - Reference Scale"] -pub type RefScaleR = crate::FieldReader; -#[doc = "Pulse Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PulseMode { - #[doc = "0: Frequency Measurement mode"] - Freq = 0, - #[doc = "1: Pulse Width Measurement mode"] - Pulse = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PulseMode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PULSE_MODE` reader - Pulse Mode"] -pub type PulseModeR = crate::BitReader; -impl PulseModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PulseMode { - match self.bits { - false => PulseMode::Freq, - true => PulseMode::Pulse, - } - } - #[doc = "Frequency Measurement mode"] - #[inline(always)] - pub fn is_freq(&self) -> bool { - *self == PulseMode::Freq - } - #[doc = "Pulse Width Measurement mode"] - #[inline(always)] - pub fn is_pulse(&self) -> bool { - *self == PulseMode::Pulse - } -} -#[doc = "Pulse Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PulsePol { - #[doc = "0: High period"] - High = 0, - #[doc = "1: Low period"] - Low = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PulsePol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PULSE_POL` reader - Pulse Polarity"] -pub type PulsePolR = crate::BitReader; -impl PulsePolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PulsePol { - match self.bits { - false => PulsePol::High, - true => PulsePol::Low, - } - } - #[doc = "High period"] - #[inline(always)] - pub fn is_high(&self) -> bool { - *self == PulsePol::High - } - #[doc = "Low period"] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == PulsePol::Low - } -} -#[doc = "Less Than Minimum Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LtMinIntEn { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LtMinIntEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LT_MIN_INT_EN` reader - Less Than Minimum Interrupt Enable"] -pub type LtMinIntEnR = crate::BitReader; -impl LtMinIntEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LtMinIntEn { - match self.bits { - false => LtMinIntEn::Disabled, - true => LtMinIntEn::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == LtMinIntEn::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == LtMinIntEn::Enabled - } -} -#[doc = "Greater Than Maximum Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GtMaxIntEn { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GtMaxIntEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GT_MAX_INT_EN` reader - Greater Than Maximum Interrupt Enable"] -pub type GtMaxIntEnR = crate::BitReader; -impl GtMaxIntEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GtMaxIntEn { - match self.bits { - false => GtMaxIntEn::Disabled, - true => GtMaxIntEn::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GtMaxIntEn::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == GtMaxIntEn::Enabled - } -} -#[doc = "Result Ready Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ResultReadyIntEn { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ResultReadyIntEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESULT_READY_INT_EN` reader - Result Ready Interrupt Enable"] -pub type ResultReadyIntEnR = crate::BitReader; -impl ResultReadyIntEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ResultReadyIntEn { - match self.bits { - false => ResultReadyIntEn::Disabled, - true => ResultReadyIntEn::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == ResultReadyIntEn::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == ResultReadyIntEn::Enabled - } -} -#[doc = "Less Than Minimum Results Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LtMinStat { - #[doc = "0: Greater than MIN\\[MIN_VALUE\\]"] - InRange = 0, - #[doc = "1: Less than MIN\\[MIN_VALUE\\]"] - LtMin = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LtMinStat) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LT_MIN_STAT` reader - Less Than Minimum Results Status"] -pub type LtMinStatR = crate::BitReader; -impl LtMinStatR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LtMinStat { - match self.bits { - false => LtMinStat::InRange, - true => LtMinStat::LtMin, - } - } - #[doc = "Greater than MIN\\[MIN_VALUE\\]"] - #[inline(always)] - pub fn is_in_range(&self) -> bool { - *self == LtMinStat::InRange - } - #[doc = "Less than MIN\\[MIN_VALUE\\]"] - #[inline(always)] - pub fn is_lt_min(&self) -> bool { - *self == LtMinStat::LtMin - } -} -#[doc = "Field `LT_MIN_STAT` writer - Less Than Minimum Results Status"] -pub type LtMinStatW<'a, REG> = crate::BitWriter1C<'a, REG, LtMinStat>; -impl<'a, REG> LtMinStatW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Greater than MIN\\[MIN_VALUE\\]"] - #[inline(always)] - pub fn in_range(self) -> &'a mut crate::W { - self.variant(LtMinStat::InRange) - } - #[doc = "Less than MIN\\[MIN_VALUE\\]"] - #[inline(always)] - pub fn lt_min(self) -> &'a mut crate::W { - self.variant(LtMinStat::LtMin) - } -} -#[doc = "Greater Than Maximum Result Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GtMaxStat { - #[doc = "0: Less than MAX\\[MAX_VALUE\\]"] - InRange = 0, - #[doc = "1: Greater than MAX\\[MAX_VALUE\\]"] - GtMax = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GtMaxStat) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GT_MAX_STAT` reader - Greater Than Maximum Result Status"] -pub type GtMaxStatR = crate::BitReader; -impl GtMaxStatR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GtMaxStat { - match self.bits { - false => GtMaxStat::InRange, - true => GtMaxStat::GtMax, - } - } - #[doc = "Less than MAX\\[MAX_VALUE\\]"] - #[inline(always)] - pub fn is_in_range(&self) -> bool { - *self == GtMaxStat::InRange - } - #[doc = "Greater than MAX\\[MAX_VALUE\\]"] - #[inline(always)] - pub fn is_gt_max(&self) -> bool { - *self == GtMaxStat::GtMax - } -} -#[doc = "Field `GT_MAX_STAT` writer - Greater Than Maximum Result Status"] -pub type GtMaxStatW<'a, REG> = crate::BitWriter1C<'a, REG, GtMaxStat>; -impl<'a, REG> GtMaxStatW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Less than MAX\\[MAX_VALUE\\]"] - #[inline(always)] - pub fn in_range(self) -> &'a mut crate::W { - self.variant(GtMaxStat::InRange) - } - #[doc = "Greater than MAX\\[MAX_VALUE\\]"] - #[inline(always)] - pub fn gt_max(self) -> &'a mut crate::W { - self.variant(GtMaxStat::GtMax) - } -} -#[doc = "Result Ready Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ResultReadyStat { - #[doc = "0: Not complete"] - NotComplete = 0, - #[doc = "1: Complete"] - Complete = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ResultReadyStat) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESULT_READY_STAT` reader - Result Ready Status"] -pub type ResultReadyStatR = crate::BitReader; -impl ResultReadyStatR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ResultReadyStat { - match self.bits { - false => ResultReadyStat::NotComplete, - true => ResultReadyStat::Complete, - } - } - #[doc = "Not complete"] - #[inline(always)] - pub fn is_not_complete(&self) -> bool { - *self == ResultReadyStat::NotComplete - } - #[doc = "Complete"] - #[inline(always)] - pub fn is_complete(&self) -> bool { - *self == ResultReadyStat::Complete - } -} -#[doc = "Field `RESULT_READY_STAT` writer - Result Ready Status"] -pub type ResultReadyStatW<'a, REG> = crate::BitWriter1C<'a, REG, ResultReadyStat>; -impl<'a, REG> ResultReadyStatW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not complete"] - #[inline(always)] - pub fn not_complete(self) -> &'a mut crate::W { - self.variant(ResultReadyStat::NotComplete) - } - #[doc = "Complete"] - #[inline(always)] - pub fn complete(self) -> &'a mut crate::W { - self.variant(ResultReadyStat::Complete) - } -} -#[doc = "Continuous Mode Enable Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ContinuousModeEn { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ContinuousModeEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CONTINUOUS_MODE_EN` reader - Continuous Mode Enable Status"] -pub type ContinuousModeEnR = crate::BitReader; -impl ContinuousModeEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ContinuousModeEn { - match self.bits { - false => ContinuousModeEn::Disabled, - true => ContinuousModeEn::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == ContinuousModeEn::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == ContinuousModeEn::Enabled - } -} -#[doc = "Measurement in Progress Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum MeasureInProgress { - #[doc = "0: Not in progress"] - Idle = 0, - #[doc = "1: In progress"] - Ongoing = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: MeasureInProgress) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MEASURE_IN_PROGRESS` reader - Measurement in Progress Status"] -pub type MeasureInProgressR = crate::BitReader; -impl MeasureInProgressR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> MeasureInProgress { - match self.bits { - false => MeasureInProgress::Idle, - true => MeasureInProgress::Ongoing, - } - } - #[doc = "Not in progress"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == MeasureInProgress::Idle - } - #[doc = "In progress"] - #[inline(always)] - pub fn is_ongoing(&self) -> bool { - *self == MeasureInProgress::Ongoing - } -} -impl R { - #[doc = "Bits 0:4 - Reference Scale"] - #[inline(always)] - pub fn ref_scale(&self) -> RefScaleR { - RefScaleR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bit 8 - Pulse Mode"] - #[inline(always)] - pub fn pulse_mode(&self) -> PulseModeR { - PulseModeR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Pulse Polarity"] - #[inline(always)] - pub fn pulse_pol(&self) -> PulsePolR { - PulsePolR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 12 - Less Than Minimum Interrupt Enable"] - #[inline(always)] - pub fn lt_min_int_en(&self) -> LtMinIntEnR { - LtMinIntEnR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Greater Than Maximum Interrupt Enable"] - #[inline(always)] - pub fn gt_max_int_en(&self) -> GtMaxIntEnR { - GtMaxIntEnR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Result Ready Interrupt Enable"] - #[inline(always)] - pub fn result_ready_int_en(&self) -> ResultReadyIntEnR { - ResultReadyIntEnR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 24 - Less Than Minimum Results Status"] - #[inline(always)] - pub fn lt_min_stat(&self) -> LtMinStatR { - LtMinStatR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Greater Than Maximum Result Status"] - #[inline(always)] - pub fn gt_max_stat(&self) -> GtMaxStatR { - GtMaxStatR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Result Ready Status"] - #[inline(always)] - pub fn result_ready_stat(&self) -> ResultReadyStatR { - ResultReadyStatR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 30 - Continuous Mode Enable Status"] - #[inline(always)] - pub fn continuous_mode_en(&self) -> ContinuousModeEnR { - ContinuousModeEnR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Measurement in Progress Status"] - #[inline(always)] - pub fn measure_in_progress(&self) -> MeasureInProgressR { - MeasureInProgressR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 24 - Less Than Minimum Results Status"] - #[inline(always)] - pub fn lt_min_stat(&mut self) -> LtMinStatW { - LtMinStatW::new(self, 24) - } - #[doc = "Bit 25 - Greater Than Maximum Result Status"] - #[inline(always)] - pub fn gt_max_stat(&mut self) -> GtMaxStatW { - GtMaxStatW::new(self, 25) - } - #[doc = "Bit 26 - Result Ready Status"] - #[inline(always)] - pub fn result_ready_stat(&mut self) -> ResultReadyStatW { - ResultReadyStatW::new(self, 26) - } -} -#[doc = "Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlstatSpec; -impl crate::RegisterSpec for CtrlstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrlstat::R`](R) reader structure"] -impl crate::Readable for CtrlstatSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrlstat::W`](W) writer structure"] -impl crate::Writable for CtrlstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0700_0000; -} -#[doc = "`reset()` method sets CTRLSTAT to value 0"] -impl crate::Resettable for CtrlstatSpec {} diff --git a/mcxa276-pac/src/freqme0/max.rs b/mcxa276-pac/src/freqme0/max.rs deleted file mode 100644 index ed470581a..000000000 --- a/mcxa276-pac/src/freqme0/max.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `MAX` reader"] -pub type R = crate::R; -#[doc = "Register `MAX` writer"] -pub type W = crate::W; -#[doc = "Field `MAX_VALUE` reader - Maximum Value"] -pub type MaxValueR = crate::FieldReader; -#[doc = "Field `MAX_VALUE` writer - Maximum Value"] -pub type MaxValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; -impl R { - #[doc = "Bits 0:30 - Maximum Value"] - #[inline(always)] - pub fn max_value(&self) -> MaxValueR { - MaxValueR::new(self.bits & 0x7fff_ffff) - } -} -impl W { - #[doc = "Bits 0:30 - Maximum Value"] - #[inline(always)] - pub fn max_value(&mut self) -> MaxValueW { - MaxValueW::new(self, 0) - } -} -#[doc = "Maximum\n\nYou can [`read`](crate::Reg::read) this register and get [`max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MaxSpec; -impl crate::RegisterSpec for MaxSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`max::R`](R) reader structure"] -impl crate::Readable for MaxSpec {} -#[doc = "`write(|w| ..)` method takes [`max::W`](W) writer structure"] -impl crate::Writable for MaxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MAX to value 0x7fff_ffff"] -impl crate::Resettable for MaxSpec { - const RESET_VALUE: u32 = 0x7fff_ffff; -} diff --git a/mcxa276-pac/src/freqme0/min.rs b/mcxa276-pac/src/freqme0/min.rs deleted file mode 100644 index 622bd623b..000000000 --- a/mcxa276-pac/src/freqme0/min.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `MIN` reader"] -pub type R = crate::R; -#[doc = "Register `MIN` writer"] -pub type W = crate::W; -#[doc = "Field `MIN_VALUE` reader - Minimum Value"] -pub type MinValueR = crate::FieldReader; -#[doc = "Field `MIN_VALUE` writer - Minimum Value"] -pub type MinValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; -impl R { - #[doc = "Bits 0:30 - Minimum Value"] - #[inline(always)] - pub fn min_value(&self) -> MinValueR { - MinValueR::new(self.bits & 0x7fff_ffff) - } -} -impl W { - #[doc = "Bits 0:30 - Minimum Value"] - #[inline(always)] - pub fn min_value(&mut self) -> MinValueW { - MinValueW::new(self, 0) - } -} -#[doc = "Minimum\n\nYou can [`read`](crate::Reg::read) this register and get [`min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MinSpec; -impl crate::RegisterSpec for MinSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`min::R`](R) reader structure"] -impl crate::Readable for MinSpec {} -#[doc = "`write(|w| ..)` method takes [`min::W`](W) writer structure"] -impl crate::Writable for MinSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MIN to value 0"] -impl crate::Resettable for MinSpec {} diff --git a/mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs b/mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs deleted file mode 100644 index b70744109..000000000 --- a/mcxa276-pac/src/freqme0/read_mode_ctrl_r.rs +++ /dev/null @@ -1,61 +0,0 @@ -#[doc = "Register `CTRL_R` reader"] -pub type R = crate::R; -#[doc = "Field `RESULT` reader - Indicates the measurement result-either the target clock counter value (for Frequency Measurement mode) or pulse width measurement (for Pulse Width Measurement mode)"] -pub type ResultR = crate::FieldReader; -#[doc = "Measurement In Progress\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum MeasureInProgress { - #[doc = "0: Complete"] - CycleDone = 0, - #[doc = "1: In progress"] - InProgress = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: MeasureInProgress) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MEASURE_IN_PROGRESS` reader - Measurement In Progress"] -pub type MeasureInProgressR = crate::BitReader; -impl MeasureInProgressR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> MeasureInProgress { - match self.bits { - false => MeasureInProgress::CycleDone, - true => MeasureInProgress::InProgress, - } - } - #[doc = "Complete"] - #[inline(always)] - pub fn is_cycle_done(&self) -> bool { - *self == MeasureInProgress::CycleDone - } - #[doc = "In progress"] - #[inline(always)] - pub fn is_in_progress(&self) -> bool { - *self == MeasureInProgress::InProgress - } -} -impl R { - #[doc = "Bits 0:30 - Indicates the measurement result-either the target clock counter value (for Frequency Measurement mode) or pulse width measurement (for Pulse Width Measurement mode)"] - #[inline(always)] - pub fn result(&self) -> ResultR { - ResultR::new(self.bits & 0x7fff_ffff) - } - #[doc = "Bit 31 - Measurement In Progress"] - #[inline(always)] - pub fn measure_in_progress(&self) -> MeasureInProgressR { - MeasureInProgressR::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "Control (in Read mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`read_mode_ctrl_r::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ReadModeCtrlRSpec; -impl crate::RegisterSpec for ReadModeCtrlRSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`read_mode_ctrl_r::R`](R) reader structure"] -impl crate::Readable for ReadModeCtrlRSpec {} -#[doc = "`reset()` method sets CTRL_R to value 0"] -impl crate::Resettable for ReadModeCtrlRSpec {} diff --git a/mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs b/mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs deleted file mode 100644 index a9278342b..000000000 --- a/mcxa276-pac/src/freqme0/write_mode_ctrl_w.rs +++ /dev/null @@ -1,274 +0,0 @@ -#[doc = "Register `CTRL_W` writer"] -pub type W = crate::W; -#[doc = "Field `REF_SCALE` writer - Reference Clock Scaling Factor"] -pub type RefScaleW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Pulse Width Measurement Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PulseMode { - #[doc = "0: Frequency Measurement mode"] - FreqMeMode = 0, - #[doc = "1: Pulse Width Measurement mode"] - PulseMeMode = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PulseMode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PULSE_MODE` writer - Pulse Width Measurement Mode Select"] -pub type PulseModeW<'a, REG> = crate::BitWriter<'a, REG, PulseMode>; -impl<'a, REG> PulseModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Frequency Measurement mode"] - #[inline(always)] - pub fn freq_me_mode(self) -> &'a mut crate::W { - self.variant(PulseMode::FreqMeMode) - } - #[doc = "Pulse Width Measurement mode"] - #[inline(always)] - pub fn pulse_me_mode(self) -> &'a mut crate::W { - self.variant(PulseMode::PulseMeMode) - } -} -#[doc = "Pulse Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PulsePol { - #[doc = "0: High period"] - HighPeriod = 0, - #[doc = "1: Low period"] - LowPeriod = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PulsePol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PULSE_POL` writer - Pulse Polarity"] -pub type PulsePolW<'a, REG> = crate::BitWriter<'a, REG, PulsePol>; -impl<'a, REG> PulsePolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "High period"] - #[inline(always)] - pub fn high_period(self) -> &'a mut crate::W { - self.variant(PulsePol::HighPeriod) - } - #[doc = "Low period"] - #[inline(always)] - pub fn low_period(self) -> &'a mut crate::W { - self.variant(PulsePol::LowPeriod) - } -} -#[doc = "Less Than Minimum Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LtMinIntEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LtMinIntEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LT_MIN_INT_EN` writer - Less Than Minimum Interrupt Enable"] -pub type LtMinIntEnW<'a, REG> = crate::BitWriter<'a, REG, LtMinIntEn>; -impl<'a, REG> LtMinIntEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(LtMinIntEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(LtMinIntEn::Enable) - } -} -#[doc = "Greater Than Maximum Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GtMaxIntEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GtMaxIntEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GT_MAX_INT_EN` writer - Greater Than Maximum Interrupt Enable"] -pub type GtMaxIntEnW<'a, REG> = crate::BitWriter<'a, REG, GtMaxIntEn>; -impl<'a, REG> GtMaxIntEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(GtMaxIntEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(GtMaxIntEn::Enable) - } -} -#[doc = "Result Ready Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ResultReadyIntEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ResultReadyIntEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESULT_READY_INT_EN` writer - Result Ready Interrupt Enable"] -pub type ResultReadyIntEnW<'a, REG> = crate::BitWriter<'a, REG, ResultReadyIntEn>; -impl<'a, REG> ResultReadyIntEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(ResultReadyIntEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(ResultReadyIntEn::Enable) - } -} -#[doc = "Continuous Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ContinuousModeEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ContinuousModeEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CONTINUOUS_MODE_EN` writer - Continuous Mode Enable"] -pub type ContinuousModeEnW<'a, REG> = crate::BitWriter<'a, REG, ContinuousModeEn>; -impl<'a, REG> ContinuousModeEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(ContinuousModeEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(ContinuousModeEn::Enable) - } -} -#[doc = "Measurement In Progress\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum MeasureInProgress { - #[doc = "0: Terminates measurement"] - ForceTerminate = 0, - #[doc = "1: Initiates measurement"] - InitiateAFreqmeCycle = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: MeasureInProgress) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MEASURE_IN_PROGRESS` writer - Measurement In Progress"] -pub type MeasureInProgressW<'a, REG> = crate::BitWriter<'a, REG, MeasureInProgress>; -impl<'a, REG> MeasureInProgressW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Terminates measurement"] - #[inline(always)] - pub fn force_terminate(self) -> &'a mut crate::W { - self.variant(MeasureInProgress::ForceTerminate) - } - #[doc = "Initiates measurement"] - #[inline(always)] - pub fn initiate_a_freqme_cycle(self) -> &'a mut crate::W { - self.variant(MeasureInProgress::InitiateAFreqmeCycle) - } -} -impl W { - #[doc = "Bits 0:4 - Reference Clock Scaling Factor"] - #[inline(always)] - pub fn ref_scale(&mut self) -> RefScaleW { - RefScaleW::new(self, 0) - } - #[doc = "Bit 8 - Pulse Width Measurement Mode Select"] - #[inline(always)] - pub fn pulse_mode(&mut self) -> PulseModeW { - PulseModeW::new(self, 8) - } - #[doc = "Bit 9 - Pulse Polarity"] - #[inline(always)] - pub fn pulse_pol(&mut self) -> PulsePolW { - PulsePolW::new(self, 9) - } - #[doc = "Bit 12 - Less Than Minimum Interrupt Enable"] - #[inline(always)] - pub fn lt_min_int_en(&mut self) -> LtMinIntEnW { - LtMinIntEnW::new(self, 12) - } - #[doc = "Bit 13 - Greater Than Maximum Interrupt Enable"] - #[inline(always)] - pub fn gt_max_int_en(&mut self) -> GtMaxIntEnW { - GtMaxIntEnW::new(self, 13) - } - #[doc = "Bit 14 - Result Ready Interrupt Enable"] - #[inline(always)] - pub fn result_ready_int_en(&mut self) -> ResultReadyIntEnW { - ResultReadyIntEnW::new(self, 14) - } - #[doc = "Bit 30 - Continuous Mode Enable"] - #[inline(always)] - pub fn continuous_mode_en(&mut self) -> ContinuousModeEnW { - ContinuousModeEnW::new(self, 30) - } - #[doc = "Bit 31 - Measurement In Progress"] - #[inline(always)] - pub fn measure_in_progress(&mut self) -> MeasureInProgressW { - MeasureInProgressW::new(self, 31) - } -} -#[doc = "Control (in Write mode)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_mode_ctrl_w::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WriteModeCtrlWSpec; -impl crate::RegisterSpec for WriteModeCtrlWSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`write_mode_ctrl_w::W`](W) writer structure"] -impl crate::Writable for WriteModeCtrlWSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL_W to value 0"] -impl crate::Resettable for WriteModeCtrlWSpec {} diff --git a/mcxa276-pac/src/generic.rs b/mcxa276-pac/src/generic.rs deleted file mode 100644 index 1bb995a4e..000000000 --- a/mcxa276-pac/src/generic.rs +++ /dev/null @@ -1,768 +0,0 @@ -use core::marker; -#[doc = " Generic peripheral accessor"] -pub struct Periph { - _marker: marker::PhantomData, -} -unsafe impl Send for Periph {} -impl Periph { - #[doc = "Pointer to the register block"] - pub const PTR: *const RB = A as *const _; - #[doc = "Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const RB { - Self::PTR - } - #[doc = " Steal an instance of this peripheral"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = " that may race with any existing instances, for example by only"] - #[doc = " accessing read-only or write-only registers, or by consuming the"] - #[doc = " original peripheral and using critical sections to coordinate"] - #[doc = " access between multiple new instances."] - #[doc = ""] - #[doc = " Additionally, other software such as HALs may rely on only one"] - #[doc = " peripheral instance existing to ensure memory safety; ensure"] - #[doc = " no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: marker::PhantomData, - } - } -} -impl core::ops::Deref for Periph { - type Target = RB; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] -pub trait RawReg: - Copy - + From - + core::ops::BitOr - + core::ops::BitAnd - + core::ops::BitOrAssign - + core::ops::BitAndAssign - + core::ops::Not - + core::ops::Shl -{ - #[doc = " Mask for bits of width `WI`"] - fn mask() -> Self; - #[doc = " `0`"] - const ZERO: Self; - #[doc = " `1`"] - const ONE: Self; -} -macro_rules! raw_reg { - ($ U : ty , $ size : literal , $ mask : ident) => { - impl RawReg for $U { - #[inline(always)] - fn mask() -> Self { - $mask::() - } - const ZERO: Self = 0; - const ONE: Self = 1; - } - const fn $mask() -> $U { - <$U>::MAX >> ($size - WI) - } - impl FieldSpec for $U { - type Ux = $U; - } - }; -} -raw_reg!(u8, 8, mask_u8); -raw_reg!(u16, 16, mask_u16); -raw_reg!(u32, 32, mask_u32); -raw_reg!(u64, 64, mask_u64); -#[doc = " Raw register type"] -pub trait RegisterSpec { - #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] - type Ux: RawReg; -} -#[doc = " Raw field type"] -pub trait FieldSpec: Sized { - #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] - type Ux: Copy + core::fmt::Debug + PartialEq + From; -} -#[doc = " Marker for fields with fixed values"] -pub trait IsEnum: FieldSpec {} -#[doc = " Trait implemented by readable registers to enable the `read` method."] -#[doc = ""] -#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec {} -#[doc = " Trait implemented by writeable registers."] -#[doc = ""] -#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] -#[doc = ""] -#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] -pub trait Writable: RegisterSpec { - #[doc = " Is it safe to write any bits to register"] - type Safety; - #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; - #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; -} -#[doc = " Reset value of the register."] -#[doc = ""] -#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] -#[doc = " register by using the `reset` method."] -pub trait Resettable: RegisterSpec { - #[doc = " Reset value of the register."] - const RESET_VALUE: Self::Ux = Self::Ux::ZERO; - #[doc = " Reset value of the register."] - #[inline(always)] - fn reset_value() -> Self::Ux { - Self::RESET_VALUE - } -} -#[doc(hidden)] -pub mod raw; -#[doc = " Register reader."] -#[doc = ""] -#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] -#[doc = " method."] -pub type R = raw::R; -impl R { - #[doc = " Reads raw bits from register."] - #[inline(always)] - pub const fn bits(&self) -> REG::Ux { - self.bits - } -} -impl PartialEq for R -where - REG::Ux: PartialEq, - FI: Copy, - REG::Ux: From, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(®::Ux::from(*other)) - } -} -#[doc = " Register writer."] -#[doc = ""] -#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub type W = raw::W; -impl W { - #[doc = " Writes raw bits to the register."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -impl W -where - REG: Writable, -{ - #[doc = " Writes raw bits to the register."] - #[inline(always)] - pub fn set(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = " Field reader."] -#[doc = ""] -#[doc = " Result of the `read` methods of fields."] -pub type FieldReader = raw::FieldReader; -#[doc = " Bit-wise field reader"] -pub type BitReader = raw::BitReader; -impl FieldReader { - #[doc = " Reads raw bits from field."] - #[inline(always)] - pub const fn bits(&self) -> FI::Ux { - self.bits - } -} -impl core::fmt::Debug for FieldReader { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.bits, f) - } -} -impl PartialEq for FieldReader -where - FI: FieldSpec + Copy, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(&FI::Ux::from(*other)) - } -} -impl PartialEq for BitReader -where - FI: Copy, - bool: From, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(&bool::from(*other)) - } -} -impl BitReader { - #[doc = " Value of the field as raw bits."] - #[inline(always)] - pub const fn bit(&self) -> bool { - self.bits - } - #[doc = " Returns `true` if the bit is clear (0)."] - #[inline(always)] - pub const fn bit_is_clear(&self) -> bool { - !self.bit() - } - #[doc = " Returns `true` if the bit is set (1)."] - #[inline(always)] - pub const fn bit_is_set(&self) -> bool { - self.bit() - } -} -impl core::fmt::Debug for BitReader { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.bits, f) - } -} -#[doc = " Marker for register/field writers which can take any value of specified width"] -pub struct Safe; -#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] -pub struct Unsafe; -#[doc = " Marker for field writers are safe to write in specified inclusive range"] -pub struct Range; -#[doc = " Marker for field writers are safe to write in specified inclusive range"] -pub struct RangeFrom; -#[doc = " Marker for field writers are safe to write in specified inclusive range"] -pub struct RangeTo; -#[doc = " Write field Proxy"] -pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = - raw::FieldWriter<'a, REG, WI, FI, Safety>; -impl FieldWriter<'_, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - #[doc = " Field width"] - pub const WIDTH: u8 = WI; - #[doc = " Field width"] - #[inline(always)] - pub const fn width(&self) -> u8 { - WI - } - #[doc = " Field offset"] - #[inline(always)] - pub const fn offset(&self) -> u8 { - self.o - } -} -impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << self.o); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; - self.w - } -} -impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> - FieldWriter<'a, REG, WI, FI, Range> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, - u64: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - { - let value = u64::from(value); - assert!(value >= MIN && value <= MAX); - } - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, - u64: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - { - let value = u64::from(value); - assert!(value >= MIN); - } - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, - u64: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - { - let value = u64::from(value); - assert!(value <= MAX); - } - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: IsEnum, - REG::Ux: From, -{ - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - unsafe { self.bits(FI::Ux::from(variant)) } - } -} -macro_rules! bit_proxy { - ($ writer : ident , $ mwv : ident) => { - #[doc(hidden)] - pub struct $mwv; - #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; - impl<'a, REG, FI> $writer<'a, REG, FI> - where - REG: Writable + RegisterSpec, - bool: From, - { - #[doc = " Field width"] - pub const WIDTH: u8 = 1; - #[doc = " Field width"] - #[inline(always)] - pub const fn width(&self) -> u8 { - Self::WIDTH - } - #[doc = " Field offset"] - #[inline(always)] - pub const fn offset(&self) -> u8 { - self.o - } - #[doc = " Writes bit to the field"] - #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut W { - self.w.bits &= !(REG::Ux::ONE << self.o); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - self.bit(bool::from(variant)) - } - } - }; -} -bit_proxy!(BitWriter, BitM); -bit_proxy!(BitWriter1S, Bit1S); -bit_proxy!(BitWriter0C, Bit0C); -bit_proxy!(BitWriter1C, Bit1C); -bit_proxy!(BitWriter0S, Bit0S); -bit_proxy!(BitWriter1T, Bit1T); -bit_proxy!(BitWriter0T, Bit0T); -impl<'a, REG, FI> BitWriter<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Sets the field bit"] - #[inline(always)] - pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::ONE << self.o; - self.w - } - #[doc = " Clears the field bit"] - #[inline(always)] - pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::ONE << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1S<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Sets the field bit"] - #[inline(always)] - pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::ONE << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0C<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Clears the field bit"] - #[inline(always)] - pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::ONE << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1C<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Clears the field bit by passing one"] - #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut W { - self.w.bits |= REG::Ux::ONE << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0S<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Sets the field bit by passing zero"] - #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::ONE << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1T<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Toggle the field bit by passing one"] - #[inline(always)] - pub fn toggle_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::ONE << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0T<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Toggle the field bit by passing zero"] - #[inline(always)] - pub fn toggle_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::ONE << self.o); - self.w - } -} -#[doc = " This structure provides volatile access to registers."] -#[repr(transparent)] -pub struct Reg { - register: vcell::VolatileCell, - _marker: marker::PhantomData, -} -unsafe impl Send for Reg where REG::Ux: Send {} -impl Reg { - #[doc = " Returns the underlying memory address of register."] - #[doc = ""] - #[doc = " ```ignore"] - #[doc = " let reg_ptr = periph.reg.as_ptr();"] - #[doc = " ```"] - #[inline(always)] - pub fn as_ptr(&self) -> *mut REG::Ux { - self.register.as_ptr() - } -} -impl Reg { - #[doc = " Reads the contents of a `Readable` register."] - #[doc = ""] - #[doc = " You can read the raw contents of a register by using `bits`:"] - #[doc = " ```ignore"] - #[doc = " let bits = periph.reg.read().bits();"] - #[doc = " ```"] - #[doc = " or get the content of a particular field of a register:"] - #[doc = " ```ignore"] - #[doc = " let reader = periph.reg.read();"] - #[doc = " let bits = reader.field1().bits();"] - #[doc = " let flag = reader.field2().bit_is_set();"] - #[doc = " ```"] - #[inline(always)] - pub fn read(&self) -> R { - R { - bits: self.register.get(), - _reg: marker::PhantomData, - } - } -} -impl Reg { - #[doc = " Writes the reset value to `Writable` register."] - #[doc = ""] - #[doc = " Resets the register to its initial state."] - #[inline(always)] - pub fn reset(&self) { - self.register.set(REG::RESET_VALUE) - } - #[doc = " Writes bits to a `Writable` register."] - #[doc = ""] - #[doc = " You can write raw bits into a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] - #[doc = " ```"] - #[doc = " or write only the fields you need:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| w"] - #[doc = " .field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT)"] - #[doc = " );"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT)"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " In the latter case, other fields will be set to their reset value."] - #[inline(always)] - pub fn write(&self, f: F) -> REG::Ux - where - F: FnOnce(&mut W) -> &mut W, - { - let value = f(&mut W { - bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP - | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }) - .bits; - self.register.set(value); - value - } - #[doc = " Writes bits to a `Writable` register and produce a value."] - #[doc = ""] - #[doc = " You can write raw bits into a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"] - #[doc = " ```"] - #[doc = " or write only the fields you need:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write_and(|w| {"] - #[doc = " w.field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write_and(|w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " In the latter case, other fields will be set to their reset value."] - #[doc = ""] - #[doc = " Values can be returned from the closure:"] - #[doc = " ```ignore"] - #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"] - #[doc = " ```"] - #[inline(always)] - pub fn from_write(&self, f: F) -> T - where - F: FnOnce(&mut W) -> T, - { - let mut writer = W { - bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP - | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }; - let result = f(&mut writer); - self.register.set(writer.bits); - result - } -} -impl Reg { - #[doc = " Writes 0 to a `Writable` register."] - #[doc = ""] - #[doc = " Similar to `write`, but unused bits will contain 0."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Unsafe to use with registers which don't allow to write 0."] - #[inline(always)] - pub unsafe fn write_with_zero(&self, f: F) -> REG::Ux - where - F: FnOnce(&mut W) -> &mut W, - { - let value = f(&mut W { - bits: REG::Ux::ZERO, - _reg: marker::PhantomData, - }) - .bits; - self.register.set(value); - value - } - #[doc = " Writes 0 to a `Writable` register and produces a value."] - #[doc = ""] - #[doc = " Similar to `write`, but unused bits will contain 0."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Unsafe to use with registers which don't allow to write 0."] - #[inline(always)] - pub unsafe fn from_write_with_zero(&self, f: F) -> T - where - F: FnOnce(&mut W) -> T, - { - let mut writer = W { - bits: REG::Ux::ZERO, - _reg: marker::PhantomData, - }; - let result = f(&mut writer); - self.register.set(writer.bits); - result - } -} -impl Reg { - #[doc = " Modifies the contents of the register by reading and then writing it."] - #[doc = ""] - #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] - #[doc = " r.bits() | 3"] - #[doc = " ) });"] - #[doc = " ```"] - #[doc = " or"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| w"] - #[doc = " .field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT)"] - #[doc = " );"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT)"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " Other fields will have the value they had before the call to `modify`."] - #[inline(always)] - pub fn modify(&self, f: F) -> REG::Ux - where - for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, - { - let bits = self.register.get(); - let value = f( - &R { - bits, - _reg: marker::PhantomData, - }, - &mut W { - bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }, - ) - .bits; - self.register.set(value); - value - } - #[doc = " Modifies the contents of the register by reading and then writing it"] - #[doc = " and produces a value."] - #[doc = ""] - #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] - #[doc = " ```ignore"] - #[doc = " let bits = periph.reg.modify(|r, w| {"] - #[doc = " let new_bits = r.bits() | 3;"] - #[doc = " unsafe {"] - #[doc = " w.bits(new_bits);"] - #[doc = " }"] - #[doc = ""] - #[doc = " new_bits"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " or"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| {"] - #[doc = " w.field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " Other fields will have the value they had before the call to `modify`."] - #[inline(always)] - pub fn from_modify(&self, f: F) -> T - where - for<'w> F: FnOnce(&R, &'w mut W) -> T, - { - let bits = self.register.get(); - let mut writer = W { - bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }; - let result = f( - &R { - bits, - _reg: marker::PhantomData, - }, - &mut writer, - ); - self.register.set(writer.bits); - result - } -} -impl core::fmt::Debug for crate::generic::Reg -where - R: core::fmt::Debug, -{ - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} diff --git a/mcxa276-pac/src/generic/raw.rs b/mcxa276-pac/src/generic/raw.rs deleted file mode 100644 index d60a23a7c..000000000 --- a/mcxa276-pac/src/generic/raw.rs +++ /dev/null @@ -1,95 +0,0 @@ -use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; -pub struct R { - pub(crate) bits: REG::Ux, - pub(super) _reg: marker::PhantomData, -} -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - pub(super) _reg: marker::PhantomData, -} -pub struct FieldReader -where - FI: FieldSpec, -{ - pub(crate) bits: FI::Ux, - _reg: marker::PhantomData, -} -impl FieldReader { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) const fn new(bits: FI::Ux) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -pub struct BitReader { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReader { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) const fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -#[must_use = "after creating `FieldWriter` you need to call field value setting method"] -pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - pub(crate) w: &'a mut W, - pub(crate) o: u8, - _field: marker::PhantomData<(FI, Safety)>, -} -impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut W, o: u8) -> Self { - Self { - w, - o, - _field: marker::PhantomData, - } - } -} -#[must_use = "after creating `BitWriter` you need to call bit setting method"] -pub struct BitWriter<'a, REG, FI = bool, M = BitM> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut W, - pub(crate) o: u8, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut W, o: u8) -> Self { - Self { - w, - o, - _field: marker::PhantomData, - } - } -} diff --git a/mcxa276-pac/src/glikey0.rs b/mcxa276-pac/src/glikey0.rs deleted file mode 100644 index 02c444c32..000000000 --- a/mcxa276-pac/src/glikey0.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - ctrl_0: Ctrl0, - ctrl_1: Ctrl1, - intr_ctrl: IntrCtrl, - status: Status, - _reserved4: [u8; 0xec], - version: Version, -} -impl RegisterBlock { - #[doc = "0x00 - Control Register 0 SFR"] - #[inline(always)] - pub const fn ctrl_0(&self) -> &Ctrl0 { - &self.ctrl_0 - } - #[doc = "0x04 - Control Register 1 SFR"] - #[inline(always)] - pub const fn ctrl_1(&self) -> &Ctrl1 { - &self.ctrl_1 - } - #[doc = "0x08 - Interrupt Control"] - #[inline(always)] - pub const fn intr_ctrl(&self) -> &IntrCtrl { - &self.intr_ctrl - } - #[doc = "0x0c - Status"] - #[inline(always)] - pub const fn status(&self) -> &Status { - &self.status - } - #[doc = "0xfc - IP Version"] - #[inline(always)] - pub const fn version(&self) -> &Version { - &self.version - } -} -#[doc = "CTRL_0 (rw) register accessor: Control Register 0 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_0`] module"] -#[doc(alias = "CTRL_0")] -pub type Ctrl0 = crate::Reg; -#[doc = "Control Register 0 SFR"] -pub mod ctrl_0; -#[doc = "CTRL_1 (rw) register accessor: Control Register 1 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_1`] module"] -#[doc(alias = "CTRL_1")] -pub type Ctrl1 = crate::Reg; -#[doc = "Control Register 1 SFR"] -pub mod ctrl_1; -#[doc = "INTR_CTRL (rw) register accessor: Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_ctrl`] module"] -#[doc(alias = "INTR_CTRL")] -pub type IntrCtrl = crate::Reg; -#[doc = "Interrupt Control"] -pub mod intr_ctrl; -#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] -#[doc(alias = "STATUS")] -pub type Status = crate::Reg; -#[doc = "Status"] -pub mod status; -#[doc = "VERSION (r) register accessor: IP Version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] -#[doc(alias = "VERSION")] -pub type Version = crate::Reg; -#[doc = "IP Version"] -pub mod version; diff --git a/mcxa276-pac/src/glikey0/ctrl_0.rs b/mcxa276-pac/src/glikey0/ctrl_0.rs deleted file mode 100644 index 775c9c7cd..000000000 --- a/mcxa276-pac/src/glikey0/ctrl_0.rs +++ /dev/null @@ -1,128 +0,0 @@ -#[doc = "Register `CTRL_0` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL_0` writer"] -pub type W = crate::W; -#[doc = "Field `WRITE_INDEX` reader - Write Index"] -pub type WriteIndexR = crate::FieldReader; -#[doc = "Field `WRITE_INDEX` writer - Write Index"] -pub type WriteIndexW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `RESERVED15` reader - Reserved for Future Use"] -pub type Reserved15R = crate::FieldReader; -#[doc = "Field `WR_EN_0` reader - Write Enable 0"] -pub type WrEn0R = crate::FieldReader; -#[doc = "Field `WR_EN_0` writer - Write Enable 0"] -pub type WrEn0W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SftRst { - #[doc = "0: No effect"] - Disable = 0, - #[doc = "1: Triggers the soft reset"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SftRst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SFT_RST` reader - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] -pub type SftRstR = crate::BitReader; -impl SftRstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SftRst { - match self.bits { - false => SftRst::Disable, - true => SftRst::Enable, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SftRst::Disable - } - #[doc = "Triggers the soft reset"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SftRst::Enable - } -} -#[doc = "Field `SFT_RST` writer - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] -pub type SftRstW<'a, REG> = crate::BitWriter<'a, REG, SftRst>; -impl<'a, REG> SftRstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SftRst::Disable) - } - #[doc = "Triggers the soft reset"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SftRst::Enable) - } -} -#[doc = "Field `RESERVED31` reader - Reserved for Future Use"] -pub type Reserved31R = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Write Index"] - #[inline(always)] - pub fn write_index(&self) -> WriteIndexR { - WriteIndexR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Reserved for Future Use"] - #[inline(always)] - pub fn reserved15(&self) -> Reserved15R { - Reserved15R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:17 - Write Enable 0"] - #[inline(always)] - pub fn wr_en_0(&self) -> WrEn0R { - WrEn0R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bit 18 - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] - #[inline(always)] - pub fn sft_rst(&self) -> SftRstR { - SftRstR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bits 19:31 - Reserved for Future Use"] - #[inline(always)] - pub fn reserved31(&self) -> Reserved31R { - Reserved31R::new(((self.bits >> 19) & 0x1fff) as u16) - } -} -impl W { - #[doc = "Bits 0:7 - Write Index"] - #[inline(always)] - pub fn write_index(&mut self) -> WriteIndexW { - WriteIndexW::new(self, 0) - } - #[doc = "Bits 16:17 - Write Enable 0"] - #[inline(always)] - pub fn wr_en_0(&mut self) -> WrEn0W { - WrEn0W::new(self, 16) - } - #[doc = "Bit 18 - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0"] - #[inline(always)] - pub fn sft_rst(&mut self) -> SftRstW { - SftRstW::new(self, 18) - } -} -#[doc = "Control Register 0 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctrl0Spec; -impl crate::RegisterSpec for Ctrl0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl_0::R`](R) reader structure"] -impl crate::Readable for Ctrl0Spec {} -#[doc = "`write(|w| ..)` method takes [`ctrl_0::W`](W) writer structure"] -impl crate::Writable for Ctrl0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL_0 to value 0x0002_0000"] -impl crate::Resettable for Ctrl0Spec { - const RESET_VALUE: u32 = 0x0002_0000; -} diff --git a/mcxa276-pac/src/glikey0/ctrl_1.rs b/mcxa276-pac/src/glikey0/ctrl_1.rs deleted file mode 100644 index ad8c97531..000000000 --- a/mcxa276-pac/src/glikey0/ctrl_1.rs +++ /dev/null @@ -1,79 +0,0 @@ -#[doc = "Register `CTRL_1` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL_1` writer"] -pub type W = crate::W; -#[doc = "Field `READ_INDEX` reader - Index status, Writing an index value to this register will request the block to return the lock status of this index."] -pub type ReadIndexR = crate::FieldReader; -#[doc = "Field `READ_INDEX` writer - Index status, Writing an index value to this register will request the block to return the lock status of this index."] -pub type ReadIndexW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `RESERVED15` reader - Reserved for Future Use"] -pub type Reserved15R = crate::FieldReader; -#[doc = "Field `WR_EN_1` reader - Write Enable One"] -pub type WrEn1R = crate::FieldReader; -#[doc = "Field `WR_EN_1` writer - Write Enable One"] -pub type WrEn1W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `SFR_LOCK` reader - LOCK register for GLIKEY"] -pub type SfrLockR = crate::FieldReader; -#[doc = "Field `SFR_LOCK` writer - LOCK register for GLIKEY"] -pub type SfrLockW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `RESERVED31` reader - Reserved for Future Use"] -pub type Reserved31R = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Index status, Writing an index value to this register will request the block to return the lock status of this index."] - #[inline(always)] - pub fn read_index(&self) -> ReadIndexR { - ReadIndexR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Reserved for Future Use"] - #[inline(always)] - pub fn reserved15(&self) -> Reserved15R { - Reserved15R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:17 - Write Enable One"] - #[inline(always)] - pub fn wr_en_1(&self) -> WrEn1R { - WrEn1R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:21 - LOCK register for GLIKEY"] - #[inline(always)] - pub fn sfr_lock(&self) -> SfrLockR { - SfrLockR::new(((self.bits >> 18) & 0x0f) as u8) - } - #[doc = "Bits 22:31 - Reserved for Future Use"] - #[inline(always)] - pub fn reserved31(&self) -> Reserved31R { - Reserved31R::new(((self.bits >> 22) & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:7 - Index status, Writing an index value to this register will request the block to return the lock status of this index."] - #[inline(always)] - pub fn read_index(&mut self) -> ReadIndexW { - ReadIndexW::new(self, 0) - } - #[doc = "Bits 16:17 - Write Enable One"] - #[inline(always)] - pub fn wr_en_1(&mut self) -> WrEn1W { - WrEn1W::new(self, 16) - } - #[doc = "Bits 18:21 - LOCK register for GLIKEY"] - #[inline(always)] - pub fn sfr_lock(&mut self) -> SfrLockW { - SfrLockW::new(self, 18) - } -} -#[doc = "Control Register 1 SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctrl1Spec; -impl crate::RegisterSpec for Ctrl1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl_1::R`](R) reader structure"] -impl crate::Readable for Ctrl1Spec {} -#[doc = "`write(|w| ..)` method takes [`ctrl_1::W`](W) writer structure"] -impl crate::Writable for Ctrl1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL_1 to value 0x0028_0000"] -impl crate::Resettable for Ctrl1Spec { - const RESET_VALUE: u32 = 0x0028_0000; -} diff --git a/mcxa276-pac/src/glikey0/intr_ctrl.rs b/mcxa276-pac/src/glikey0/intr_ctrl.rs deleted file mode 100644 index e9648235c..000000000 --- a/mcxa276-pac/src/glikey0/intr_ctrl.rs +++ /dev/null @@ -1,119 +0,0 @@ -#[doc = "Register `INTR_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `INTR_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `INT_EN` reader - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] -pub type IntEnR = crate::BitReader; -#[doc = "Field `INT_EN` writer - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] -pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_CLR` reader - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] -pub type IntClrR = crate::BitReader; -#[doc = "Field `INT_CLR` writer - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] -pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IntSet { - #[doc = "0: No effect"] - Disable = 0, - #[doc = "1: Triggers interrupt"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IntSet) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT_SET` reader - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] -pub type IntSetR = crate::BitReader; -impl IntSetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IntSet { - match self.bits { - false => IntSet::Disable, - true => IntSet::Enable, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IntSet::Disable - } - #[doc = "Triggers interrupt"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IntSet::Enable - } -} -#[doc = "Field `INT_SET` writer - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] -pub type IntSetW<'a, REG> = crate::BitWriter<'a, REG, IntSet>; -impl<'a, REG> IntSetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(IntSet::Disable) - } - #[doc = "Triggers interrupt"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(IntSet::Enable) - } -} -#[doc = "Field `RESERVED31` reader - Reserved for Future Use"] -pub type Reserved31R = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] - #[inline(always)] - pub fn int_en(&self) -> IntEnR { - IntEnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] - #[inline(always)] - pub fn int_clr(&self) -> IntClrR { - IntClrR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] - #[inline(always)] - pub fn int_set(&self) -> IntSetR { - IntSetR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 3:31 - Reserved for Future Use"] - #[inline(always)] - pub fn reserved31(&self) -> Reserved31R { - Reserved31R::new((self.bits >> 3) & 0x1fff_ffff) - } -} -impl W { - #[doc = "Bit 0 - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port"] - #[inline(always)] - pub fn int_en(&mut self) -> IntEnW { - IntEnW::new(self, 0) - } - #[doc = "Bit 1 - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0"] - #[inline(always)] - pub fn int_clr(&mut self) -> IntClrW { - IntClrW::new(self, 1) - } - #[doc = "Bit 2 - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0"] - #[inline(always)] - pub fn int_set(&mut self) -> IntSetW { - IntSetW::new(self, 2) - } -} -#[doc = "Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IntrCtrlSpec; -impl crate::RegisterSpec for IntrCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`intr_ctrl::R`](R) reader structure"] -impl crate::Readable for IntrCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`intr_ctrl::W`](W) writer structure"] -impl crate::Writable for IntrCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets INTR_CTRL to value 0"] -impl crate::Resettable for IntrCtrlSpec {} diff --git a/mcxa276-pac/src/glikey0/status.rs b/mcxa276-pac/src/glikey0/status.rs deleted file mode 100644 index eae5bd127..000000000 --- a/mcxa276-pac/src/glikey0/status.rs +++ /dev/null @@ -1,198 +0,0 @@ -#[doc = "Register `STATUS` reader"] -pub type R = crate::R; -#[doc = "Interrupt Status.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IntStatus { - #[doc = "0: No effect"] - Disable = 0, - #[doc = "1: Triggers interrupt"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IntStatus) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT_STATUS` reader - Interrupt Status."] -pub type IntStatusR = crate::BitReader; -impl IntStatusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IntStatus { - match self.bits { - false => IntStatus::Disable, - true => IntStatus::Enable, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IntStatus::Disable - } - #[doc = "Triggers interrupt"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IntStatus::Enable - } -} -#[doc = "Provides the current lock status of indexes.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LockStatus { - #[doc = "0: Current read index is not locked"] - Lock0 = 0, - #[doc = "1: Current read index is locked"] - Lock1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LockStatus) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK_STATUS` reader - Provides the current lock status of indexes."] -pub type LockStatusR = crate::BitReader; -impl LockStatusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LockStatus { - match self.bits { - false => LockStatus::Lock0, - true => LockStatus::Lock1, - } - } - #[doc = "Current read index is not locked"] - #[inline(always)] - pub fn is_lock0(&self) -> bool { - *self == LockStatus::Lock0 - } - #[doc = "Current read index is locked"] - #[inline(always)] - pub fn is_lock1(&self) -> bool { - *self == LockStatus::Lock1 - } -} -#[doc = "Status of the Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ErrorStatus { - #[doc = "0: No error"] - Stat0 = 0, - #[doc = "1: FSM error has occurred"] - Stat1 = 1, - #[doc = "2: Write index out of the bound (OOB) error"] - Stat2 = 2, - #[doc = "3: Write index OOB and FSM error"] - Stat3 = 3, - #[doc = "4: Read index OOB error"] - Stat4 = 4, - #[doc = "6: Write index and read index OOB error"] - Stat5 = 6, - #[doc = "7: Read index OOB, write index OOB, and FSM error"] - Stat6 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ErrorStatus) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ErrorStatus { - type Ux = u8; -} -impl crate::IsEnum for ErrorStatus {} -#[doc = "Field `ERROR_STATUS` reader - Status of the Error"] -pub type ErrorStatusR = crate::FieldReader; -impl ErrorStatusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(ErrorStatus::Stat0), - 1 => Some(ErrorStatus::Stat1), - 2 => Some(ErrorStatus::Stat2), - 3 => Some(ErrorStatus::Stat3), - 4 => Some(ErrorStatus::Stat4), - 6 => Some(ErrorStatus::Stat5), - 7 => Some(ErrorStatus::Stat6), - _ => None, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_stat0(&self) -> bool { - *self == ErrorStatus::Stat0 - } - #[doc = "FSM error has occurred"] - #[inline(always)] - pub fn is_stat1(&self) -> bool { - *self == ErrorStatus::Stat1 - } - #[doc = "Write index out of the bound (OOB) error"] - #[inline(always)] - pub fn is_stat2(&self) -> bool { - *self == ErrorStatus::Stat2 - } - #[doc = "Write index OOB and FSM error"] - #[inline(always)] - pub fn is_stat3(&self) -> bool { - *self == ErrorStatus::Stat3 - } - #[doc = "Read index OOB error"] - #[inline(always)] - pub fn is_stat4(&self) -> bool { - *self == ErrorStatus::Stat4 - } - #[doc = "Write index and read index OOB error"] - #[inline(always)] - pub fn is_stat5(&self) -> bool { - *self == ErrorStatus::Stat5 - } - #[doc = "Read index OOB, write index OOB, and FSM error"] - #[inline(always)] - pub fn is_stat6(&self) -> bool { - *self == ErrorStatus::Stat6 - } -} -#[doc = "Field `RESERVED18` reader - Reserved for Future Use"] -pub type Reserved18R = crate::FieldReader; -#[doc = "Field `FSM_STATE` reader - Status of FSM"] -pub type FsmStateR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Interrupt Status."] - #[inline(always)] - pub fn int_status(&self) -> IntStatusR { - IntStatusR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Provides the current lock status of indexes."] - #[inline(always)] - pub fn lock_status(&self) -> LockStatusR { - LockStatusR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:4 - Status of the Error"] - #[inline(always)] - pub fn error_status(&self) -> ErrorStatusR { - ErrorStatusR::new(((self.bits >> 2) & 7) as u8) - } - #[doc = "Bits 5:18 - Reserved for Future Use"] - #[inline(always)] - pub fn reserved18(&self) -> Reserved18R { - Reserved18R::new(((self.bits >> 5) & 0x3fff) as u16) - } - #[doc = "Bits 19:31 - Status of FSM"] - #[inline(always)] - pub fn fsm_state(&self) -> FsmStateR { - FsmStateR::new(((self.bits >> 19) & 0x1fff) as u16) - } -} -#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StatusSpec; -impl crate::RegisterSpec for StatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`status::R`](R) reader structure"] -impl crate::Readable for StatusSpec {} -#[doc = "`reset()` method sets STATUS to value 0x00b0_0000"] -impl crate::Resettable for StatusSpec { - const RESET_VALUE: u32 = 0x00b0_0000; -} diff --git a/mcxa276-pac/src/glikey0/version.rs b/mcxa276-pac/src/glikey0/version.rs deleted file mode 100644 index a8c02d94a..000000000 --- a/mcxa276-pac/src/glikey0/version.rs +++ /dev/null @@ -1,71 +0,0 @@ -#[doc = "Register `VERSION` reader"] -pub type R = crate::R; -#[doc = "Field `Reserved3` reader - Reserved"] -pub type Reserved3R = crate::FieldReader; -#[doc = "Field `Reserved7` reader - Reserved"] -pub type Reserved7R = crate::FieldReader; -#[doc = "Field `Reserved11` reader - Reserved"] -pub type Reserved11R = crate::FieldReader; -#[doc = "Field `Reserved15` reader - Reserved"] -pub type Reserved15R = crate::FieldReader; -#[doc = "Field `MILESTONE` reader - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] -pub type MilestoneR = crate::FieldReader; -#[doc = "Field `FSM_CONFIG` reader - 0:4 step, 1:8 step"] -pub type FsmConfigR = crate::BitReader; -#[doc = "Field `INDEX_CONFIG` reader - Configured number of addressable indexes"] -pub type IndexConfigR = crate::FieldReader; -#[doc = "Field `Reserved31` reader - Reserved for Future Use"] -pub type Reserved31R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Reserved"] - #[inline(always)] - pub fn reserved3(&self) -> Reserved3R { - Reserved3R::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - Reserved"] - #[inline(always)] - pub fn reserved7(&self) -> Reserved7R { - Reserved7R::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - Reserved"] - #[inline(always)] - pub fn reserved11(&self) -> Reserved11R { - Reserved11R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Reserved"] - #[inline(always)] - pub fn reserved15(&self) -> Reserved15R { - Reserved15R::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:17 - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] - #[inline(always)] - pub fn milestone(&self) -> MilestoneR { - MilestoneR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bit 18 - 0:4 step, 1:8 step"] - #[inline(always)] - pub fn fsm_config(&self) -> FsmConfigR { - FsmConfigR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bits 19:26 - Configured number of addressable indexes"] - #[inline(always)] - pub fn index_config(&self) -> IndexConfigR { - IndexConfigR::new(((self.bits >> 19) & 0xff) as u8) - } - #[doc = "Bits 27:31 - Reserved for Future Use"] - #[inline(always)] - pub fn reserved31(&self) -> Reserved31R { - Reserved31R::new(((self.bits >> 27) & 0x1f) as u8) - } -} -#[doc = "IP Version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VersionSpec; -impl crate::RegisterSpec for VersionSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`version::R`](R) reader structure"] -impl crate::Readable for VersionSpec {} -#[doc = "`reset()` method sets VERSION to value 0x007b_0100"] -impl crate::Resettable for VersionSpec { - const RESET_VALUE: u32 = 0x007b_0100; -} diff --git a/mcxa276-pac/src/gpio0.rs b/mcxa276-pac/src/gpio0.rs deleted file mode 100644 index f42ec291b..000000000 --- a/mcxa276-pac/src/gpio0.rs +++ /dev/null @@ -1,175 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - _reserved2: [u8; 0x38], - pdor: Pdor, - psor: Psor, - pcor: Pcor, - ptor: Ptor, - pdir: Pdir, - pddr: Pddr, - pidr: Pidr, - _reserved9: [u8; 0x04], - pdr: [Pdr; 32], - icr: [Icr; 32], - giclr: Giclr, - gichr: Gichr, - _reserved13: [u8; 0x18], - isfr0: Isfr0, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x40 - Port Data Output"] - #[inline(always)] - pub const fn pdor(&self) -> &Pdor { - &self.pdor - } - #[doc = "0x44 - Port Set Output"] - #[inline(always)] - pub const fn psor(&self) -> &Psor { - &self.psor - } - #[doc = "0x48 - Port Clear Output"] - #[inline(always)] - pub const fn pcor(&self) -> &Pcor { - &self.pcor - } - #[doc = "0x4c - Port Toggle Output"] - #[inline(always)] - pub const fn ptor(&self) -> &Ptor { - &self.ptor - } - #[doc = "0x50 - Port Data Input"] - #[inline(always)] - pub const fn pdir(&self) -> &Pdir { - &self.pdir - } - #[doc = "0x54 - Port Data Direction"] - #[inline(always)] - pub const fn pddr(&self) -> &Pddr { - &self.pddr - } - #[doc = "0x58 - Port Input Disable"] - #[inline(always)] - pub const fn pidr(&self) -> &Pidr { - &self.pidr - } - #[doc = "0x60..0x80 - Pin Data"] - #[inline(always)] - pub const fn pdr(&self, n: usize) -> &Pdr { - &self.pdr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x60..0x80 - Pin Data"] - #[inline(always)] - pub fn pdr_iter(&self) -> impl Iterator { - self.pdr.iter() - } - #[doc = "0x80..0x100 - Interrupt Control index"] - #[inline(always)] - pub const fn icr(&self, n: usize) -> &Icr { - &self.icr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x80..0x100 - Interrupt Control index"] - #[inline(always)] - pub fn icr_iter(&self) -> impl Iterator { - self.icr.iter() - } - #[doc = "0x100 - Global Interrupt Control Low"] - #[inline(always)] - pub const fn giclr(&self) -> &Giclr { - &self.giclr - } - #[doc = "0x104 - Global Interrupt Control High"] - #[inline(always)] - pub const fn gichr(&self) -> &Gichr { - &self.gichr - } - #[doc = "0x120 - Interrupt Status Flag"] - #[inline(always)] - pub const fn isfr0(&self) -> &Isfr0 { - &self.isfr0 - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "PDOR (rw) register accessor: Port Data Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pdor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdor`] module"] -#[doc(alias = "PDOR")] -pub type Pdor = crate::Reg; -#[doc = "Port Data Output"] -pub mod pdor; -#[doc = "PSOR (rw) register accessor: Port Set Output\n\nYou can [`read`](crate::Reg::read) this register and get [`psor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psor`] module"] -#[doc(alias = "PSOR")] -pub type Psor = crate::Reg; -#[doc = "Port Set Output"] -pub mod psor; -#[doc = "PCOR (rw) register accessor: Port Clear Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pcor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcor`] module"] -#[doc(alias = "PCOR")] -pub type Pcor = crate::Reg; -#[doc = "Port Clear Output"] -pub mod pcor; -#[doc = "PTOR (rw) register accessor: Port Toggle Output\n\nYou can [`read`](crate::Reg::read) this register and get [`ptor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ptor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ptor`] module"] -#[doc(alias = "PTOR")] -pub type Ptor = crate::Reg; -#[doc = "Port Toggle Output"] -pub mod ptor; -#[doc = "PDIR (r) register accessor: Port Data Input\n\nYou can [`read`](crate::Reg::read) this register and get [`pdir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdir`] module"] -#[doc(alias = "PDIR")] -pub type Pdir = crate::Reg; -#[doc = "Port Data Input"] -pub mod pdir; -#[doc = "PDDR (rw) register accessor: Port Data Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`pddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pddr`] module"] -#[doc(alias = "PDDR")] -pub type Pddr = crate::Reg; -#[doc = "Port Data Direction"] -pub mod pddr; -#[doc = "PIDR (rw) register accessor: Port Input Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pidr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pidr`] module"] -#[doc(alias = "PIDR")] -pub type Pidr = crate::Reg; -#[doc = "Port Input Disable"] -pub mod pidr; -#[doc = "PDR (rw) register accessor: Pin Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdr`] module"] -#[doc(alias = "PDR")] -pub type Pdr = crate::Reg; -#[doc = "Pin Data"] -pub mod pdr; -#[doc = "ICR (rw) register accessor: Interrupt Control index\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] module"] -#[doc(alias = "ICR")] -pub type Icr = crate::Reg; -#[doc = "Interrupt Control index"] -pub mod icr; -#[doc = "GICLR (rw) register accessor: Global Interrupt Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`giclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@giclr`] module"] -#[doc(alias = "GICLR")] -pub type Giclr = crate::Reg; -#[doc = "Global Interrupt Control Low"] -pub mod giclr; -#[doc = "GICHR (rw) register accessor: Global Interrupt Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gichr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gichr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gichr`] module"] -#[doc(alias = "GICHR")] -pub type Gichr = crate::Reg; -#[doc = "Global Interrupt Control High"] -pub mod gichr; -#[doc = "ISFR0 (rw) register accessor: Interrupt Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`isfr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isfr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isfr0`] module"] -#[doc(alias = "ISFR0")] -pub type Isfr0 = crate::Reg; -#[doc = "Interrupt Status Flag"] -pub mod isfr0; diff --git a/mcxa276-pac/src/gpio0/gichr.rs b/mcxa276-pac/src/gpio0/gichr.rs deleted file mode 100644 index 4d2d773d7..000000000 --- a/mcxa276-pac/src/gpio0/gichr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GICHR` reader"] -pub type R = crate::R; -#[doc = "Register `GICHR` writer"] -pub type W = crate::W; -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe16 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE16` reader - Global Interrupt Write Enable"] -pub type Giwe16R = crate::BitReader; -impl Giwe16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe16 { - match self.bits { - false => Giwe16::Giwe0, - true => Giwe16::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe16::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe16::Giwe1 - } -} -#[doc = "Field `GIWE16` writer - Global Interrupt Write Enable"] -pub type Giwe16W<'a, REG> = crate::BitWriter<'a, REG, Giwe16>; -impl<'a, REG> Giwe16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe16::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe16::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe17 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE17` reader - Global Interrupt Write Enable"] -pub type Giwe17R = crate::BitReader; -impl Giwe17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe17 { - match self.bits { - false => Giwe17::Giwe0, - true => Giwe17::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe17::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe17::Giwe1 - } -} -#[doc = "Field `GIWE17` writer - Global Interrupt Write Enable"] -pub type Giwe17W<'a, REG> = crate::BitWriter<'a, REG, Giwe17>; -impl<'a, REG> Giwe17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe17::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe17::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe18 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE18` reader - Global Interrupt Write Enable"] -pub type Giwe18R = crate::BitReader; -impl Giwe18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe18 { - match self.bits { - false => Giwe18::Giwe0, - true => Giwe18::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe18::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe18::Giwe1 - } -} -#[doc = "Field `GIWE18` writer - Global Interrupt Write Enable"] -pub type Giwe18W<'a, REG> = crate::BitWriter<'a, REG, Giwe18>; -impl<'a, REG> Giwe18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe18::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe18::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe19 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE19` reader - Global Interrupt Write Enable"] -pub type Giwe19R = crate::BitReader; -impl Giwe19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe19 { - match self.bits { - false => Giwe19::Giwe0, - true => Giwe19::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe19::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe19::Giwe1 - } -} -#[doc = "Field `GIWE19` writer - Global Interrupt Write Enable"] -pub type Giwe19W<'a, REG> = crate::BitWriter<'a, REG, Giwe19>; -impl<'a, REG> Giwe19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe19::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe19::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe20 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE20` reader - Global Interrupt Write Enable"] -pub type Giwe20R = crate::BitReader; -impl Giwe20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe20 { - match self.bits { - false => Giwe20::Giwe0, - true => Giwe20::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe20::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe20::Giwe1 - } -} -#[doc = "Field `GIWE20` writer - Global Interrupt Write Enable"] -pub type Giwe20W<'a, REG> = crate::BitWriter<'a, REG, Giwe20>; -impl<'a, REG> Giwe20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe20::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe20::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe21 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE21` reader - Global Interrupt Write Enable"] -pub type Giwe21R = crate::BitReader; -impl Giwe21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe21 { - match self.bits { - false => Giwe21::Giwe0, - true => Giwe21::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe21::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe21::Giwe1 - } -} -#[doc = "Field `GIWE21` writer - Global Interrupt Write Enable"] -pub type Giwe21W<'a, REG> = crate::BitWriter<'a, REG, Giwe21>; -impl<'a, REG> Giwe21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe21::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe21::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe22 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE22` reader - Global Interrupt Write Enable"] -pub type Giwe22R = crate::BitReader; -impl Giwe22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe22 { - match self.bits { - false => Giwe22::Giwe0, - true => Giwe22::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe22::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe22::Giwe1 - } -} -#[doc = "Field `GIWE22` writer - Global Interrupt Write Enable"] -pub type Giwe22W<'a, REG> = crate::BitWriter<'a, REG, Giwe22>; -impl<'a, REG> Giwe22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe22::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe22::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe23 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE23` reader - Global Interrupt Write Enable"] -pub type Giwe23R = crate::BitReader; -impl Giwe23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe23 { - match self.bits { - false => Giwe23::Giwe0, - true => Giwe23::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe23::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe23::Giwe1 - } -} -#[doc = "Field `GIWE23` writer - Global Interrupt Write Enable"] -pub type Giwe23W<'a, REG> = crate::BitWriter<'a, REG, Giwe23>; -impl<'a, REG> Giwe23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe23::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe23::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe24 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE24` reader - Global Interrupt Write Enable"] -pub type Giwe24R = crate::BitReader; -impl Giwe24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe24 { - match self.bits { - false => Giwe24::Giwe0, - true => Giwe24::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe24::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe24::Giwe1 - } -} -#[doc = "Field `GIWE24` writer - Global Interrupt Write Enable"] -pub type Giwe24W<'a, REG> = crate::BitWriter<'a, REG, Giwe24>; -impl<'a, REG> Giwe24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe24::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe24::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe25 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE25` reader - Global Interrupt Write Enable"] -pub type Giwe25R = crate::BitReader; -impl Giwe25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe25 { - match self.bits { - false => Giwe25::Giwe0, - true => Giwe25::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe25::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe25::Giwe1 - } -} -#[doc = "Field `GIWE25` writer - Global Interrupt Write Enable"] -pub type Giwe25W<'a, REG> = crate::BitWriter<'a, REG, Giwe25>; -impl<'a, REG> Giwe25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe25::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe25::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe26 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE26` reader - Global Interrupt Write Enable"] -pub type Giwe26R = crate::BitReader; -impl Giwe26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe26 { - match self.bits { - false => Giwe26::Giwe0, - true => Giwe26::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe26::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe26::Giwe1 - } -} -#[doc = "Field `GIWE26` writer - Global Interrupt Write Enable"] -pub type Giwe26W<'a, REG> = crate::BitWriter<'a, REG, Giwe26>; -impl<'a, REG> Giwe26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe26::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe26::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe27 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE27` reader - Global Interrupt Write Enable"] -pub type Giwe27R = crate::BitReader; -impl Giwe27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe27 { - match self.bits { - false => Giwe27::Giwe0, - true => Giwe27::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe27::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe27::Giwe1 - } -} -#[doc = "Field `GIWE27` writer - Global Interrupt Write Enable"] -pub type Giwe27W<'a, REG> = crate::BitWriter<'a, REG, Giwe27>; -impl<'a, REG> Giwe27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe27::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe27::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe28 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE28` reader - Global Interrupt Write Enable"] -pub type Giwe28R = crate::BitReader; -impl Giwe28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe28 { - match self.bits { - false => Giwe28::Giwe0, - true => Giwe28::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe28::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe28::Giwe1 - } -} -#[doc = "Field `GIWE28` writer - Global Interrupt Write Enable"] -pub type Giwe28W<'a, REG> = crate::BitWriter<'a, REG, Giwe28>; -impl<'a, REG> Giwe28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe28::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe28::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe29 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE29` reader - Global Interrupt Write Enable"] -pub type Giwe29R = crate::BitReader; -impl Giwe29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe29 { - match self.bits { - false => Giwe29::Giwe0, - true => Giwe29::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe29::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe29::Giwe1 - } -} -#[doc = "Field `GIWE29` writer - Global Interrupt Write Enable"] -pub type Giwe29W<'a, REG> = crate::BitWriter<'a, REG, Giwe29>; -impl<'a, REG> Giwe29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe29::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe29::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe30 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE30` reader - Global Interrupt Write Enable"] -pub type Giwe30R = crate::BitReader; -impl Giwe30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe30 { - match self.bits { - false => Giwe30::Giwe0, - true => Giwe30::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe30::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe30::Giwe1 - } -} -#[doc = "Field `GIWE30` writer - Global Interrupt Write Enable"] -pub type Giwe30W<'a, REG> = crate::BitWriter<'a, REG, Giwe30>; -impl<'a, REG> Giwe30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe30::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe30::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe31 { - #[doc = "0: Not updated."] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE31` reader - Global Interrupt Write Enable"] -pub type Giwe31R = crate::BitReader; -impl Giwe31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe31 { - match self.bits { - false => Giwe31::Giwe0, - true => Giwe31::Giwe1, - } - } - #[doc = "Not updated."] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe31::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe31::Giwe1 - } -} -#[doc = "Field `GIWE31` writer - Global Interrupt Write Enable"] -pub type Giwe31W<'a, REG> = crate::BitWriter<'a, REG, Giwe31>; -impl<'a, REG> Giwe31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated."] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe31::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe31::Giwe1) - } -} -#[doc = "Field `GIWD` reader - Global Interrupt Write Data"] -pub type GiwdR = crate::FieldReader; -#[doc = "Field `GIWD` writer - Global Interrupt Write Data"] -pub type GiwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bit 0 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe16(&self) -> Giwe16R { - Giwe16R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe17(&self) -> Giwe17R { - Giwe17R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe18(&self) -> Giwe18R { - Giwe18R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe19(&self) -> Giwe19R { - Giwe19R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe20(&self) -> Giwe20R { - Giwe20R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe21(&self) -> Giwe21R { - Giwe21R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe22(&self) -> Giwe22R { - Giwe22R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe23(&self) -> Giwe23R { - Giwe23R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe24(&self) -> Giwe24R { - Giwe24R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe25(&self) -> Giwe25R { - Giwe25R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe26(&self) -> Giwe26R { - Giwe26R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe27(&self) -> Giwe27R { - Giwe27R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe28(&self) -> Giwe28R { - Giwe28R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe29(&self) -> Giwe29R { - Giwe29R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe30(&self) -> Giwe30R { - Giwe30R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe31(&self) -> Giwe31R { - Giwe31R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:31 - Global Interrupt Write Data"] - #[inline(always)] - pub fn giwd(&self) -> GiwdR { - GiwdR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bit 0 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe16(&mut self) -> Giwe16W { - Giwe16W::new(self, 0) - } - #[doc = "Bit 1 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe17(&mut self) -> Giwe17W { - Giwe17W::new(self, 1) - } - #[doc = "Bit 2 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe18(&mut self) -> Giwe18W { - Giwe18W::new(self, 2) - } - #[doc = "Bit 3 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe19(&mut self) -> Giwe19W { - Giwe19W::new(self, 3) - } - #[doc = "Bit 4 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe20(&mut self) -> Giwe20W { - Giwe20W::new(self, 4) - } - #[doc = "Bit 5 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe21(&mut self) -> Giwe21W { - Giwe21W::new(self, 5) - } - #[doc = "Bit 6 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe22(&mut self) -> Giwe22W { - Giwe22W::new(self, 6) - } - #[doc = "Bit 7 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe23(&mut self) -> Giwe23W { - Giwe23W::new(self, 7) - } - #[doc = "Bit 8 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe24(&mut self) -> Giwe24W { - Giwe24W::new(self, 8) - } - #[doc = "Bit 9 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe25(&mut self) -> Giwe25W { - Giwe25W::new(self, 9) - } - #[doc = "Bit 10 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe26(&mut self) -> Giwe26W { - Giwe26W::new(self, 10) - } - #[doc = "Bit 11 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe27(&mut self) -> Giwe27W { - Giwe27W::new(self, 11) - } - #[doc = "Bit 12 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe28(&mut self) -> Giwe28W { - Giwe28W::new(self, 12) - } - #[doc = "Bit 13 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe29(&mut self) -> Giwe29W { - Giwe29W::new(self, 13) - } - #[doc = "Bit 14 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe30(&mut self) -> Giwe30W { - Giwe30W::new(self, 14) - } - #[doc = "Bit 15 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe31(&mut self) -> Giwe31W { - Giwe31W::new(self, 15) - } - #[doc = "Bits 16:31 - Global Interrupt Write Data"] - #[inline(always)] - pub fn giwd(&mut self) -> GiwdW { - GiwdW::new(self, 16) - } -} -#[doc = "Global Interrupt Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gichr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gichr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GichrSpec; -impl crate::RegisterSpec for GichrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gichr::R`](R) reader structure"] -impl crate::Readable for GichrSpec {} -#[doc = "`write(|w| ..)` method takes [`gichr::W`](W) writer structure"] -impl crate::Writable for GichrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GICHR to value 0"] -impl crate::Resettable for GichrSpec {} diff --git a/mcxa276-pac/src/gpio0/giclr.rs b/mcxa276-pac/src/gpio0/giclr.rs deleted file mode 100644 index 239b49ca1..000000000 --- a/mcxa276-pac/src/gpio0/giclr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GICLR` reader"] -pub type R = crate::R; -#[doc = "Register `GICLR` writer"] -pub type W = crate::W; -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe0 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE0` reader - Global Interrupt Write Enable"] -pub type Giwe0R = crate::BitReader; -impl Giwe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe0 { - match self.bits { - false => Giwe0::Giwe0, - true => Giwe0::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe0::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe0::Giwe1 - } -} -#[doc = "Field `GIWE0` writer - Global Interrupt Write Enable"] -pub type Giwe0W<'a, REG> = crate::BitWriter<'a, REG, Giwe0>; -impl<'a, REG> Giwe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe0::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe0::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe1 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE1` reader - Global Interrupt Write Enable"] -pub type Giwe1R = crate::BitReader; -impl Giwe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe1 { - match self.bits { - false => Giwe1::Giwe0, - true => Giwe1::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe1::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe1::Giwe1 - } -} -#[doc = "Field `GIWE1` writer - Global Interrupt Write Enable"] -pub type Giwe1W<'a, REG> = crate::BitWriter<'a, REG, Giwe1>; -impl<'a, REG> Giwe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe1::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe1::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe2 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE2` reader - Global Interrupt Write Enable"] -pub type Giwe2R = crate::BitReader; -impl Giwe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe2 { - match self.bits { - false => Giwe2::Giwe0, - true => Giwe2::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe2::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe2::Giwe1 - } -} -#[doc = "Field `GIWE2` writer - Global Interrupt Write Enable"] -pub type Giwe2W<'a, REG> = crate::BitWriter<'a, REG, Giwe2>; -impl<'a, REG> Giwe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe2::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe2::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe3 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE3` reader - Global Interrupt Write Enable"] -pub type Giwe3R = crate::BitReader; -impl Giwe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe3 { - match self.bits { - false => Giwe3::Giwe0, - true => Giwe3::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe3::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe3::Giwe1 - } -} -#[doc = "Field `GIWE3` writer - Global Interrupt Write Enable"] -pub type Giwe3W<'a, REG> = crate::BitWriter<'a, REG, Giwe3>; -impl<'a, REG> Giwe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe3::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe3::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe4 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE4` reader - Global Interrupt Write Enable"] -pub type Giwe4R = crate::BitReader; -impl Giwe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe4 { - match self.bits { - false => Giwe4::Giwe0, - true => Giwe4::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe4::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe4::Giwe1 - } -} -#[doc = "Field `GIWE4` writer - Global Interrupt Write Enable"] -pub type Giwe4W<'a, REG> = crate::BitWriter<'a, REG, Giwe4>; -impl<'a, REG> Giwe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe4::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe4::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe5 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE5` reader - Global Interrupt Write Enable"] -pub type Giwe5R = crate::BitReader; -impl Giwe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe5 { - match self.bits { - false => Giwe5::Giwe0, - true => Giwe5::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe5::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe5::Giwe1 - } -} -#[doc = "Field `GIWE5` writer - Global Interrupt Write Enable"] -pub type Giwe5W<'a, REG> = crate::BitWriter<'a, REG, Giwe5>; -impl<'a, REG> Giwe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe5::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe5::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe6 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE6` reader - Global Interrupt Write Enable"] -pub type Giwe6R = crate::BitReader; -impl Giwe6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe6 { - match self.bits { - false => Giwe6::Giwe0, - true => Giwe6::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe6::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe6::Giwe1 - } -} -#[doc = "Field `GIWE6` writer - Global Interrupt Write Enable"] -pub type Giwe6W<'a, REG> = crate::BitWriter<'a, REG, Giwe6>; -impl<'a, REG> Giwe6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe6::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe6::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe7 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE7` reader - Global Interrupt Write Enable"] -pub type Giwe7R = crate::BitReader; -impl Giwe7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe7 { - match self.bits { - false => Giwe7::Giwe0, - true => Giwe7::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe7::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe7::Giwe1 - } -} -#[doc = "Field `GIWE7` writer - Global Interrupt Write Enable"] -pub type Giwe7W<'a, REG> = crate::BitWriter<'a, REG, Giwe7>; -impl<'a, REG> Giwe7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe7::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe7::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe8 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE8` reader - Global Interrupt Write Enable"] -pub type Giwe8R = crate::BitReader; -impl Giwe8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe8 { - match self.bits { - false => Giwe8::Giwe0, - true => Giwe8::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe8::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe8::Giwe1 - } -} -#[doc = "Field `GIWE8` writer - Global Interrupt Write Enable"] -pub type Giwe8W<'a, REG> = crate::BitWriter<'a, REG, Giwe8>; -impl<'a, REG> Giwe8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe8::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe8::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe9 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE9` reader - Global Interrupt Write Enable"] -pub type Giwe9R = crate::BitReader; -impl Giwe9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe9 { - match self.bits { - false => Giwe9::Giwe0, - true => Giwe9::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe9::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe9::Giwe1 - } -} -#[doc = "Field `GIWE9` writer - Global Interrupt Write Enable"] -pub type Giwe9W<'a, REG> = crate::BitWriter<'a, REG, Giwe9>; -impl<'a, REG> Giwe9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe9::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe9::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe10 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE10` reader - Global Interrupt Write Enable"] -pub type Giwe10R = crate::BitReader; -impl Giwe10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe10 { - match self.bits { - false => Giwe10::Giwe0, - true => Giwe10::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe10::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe10::Giwe1 - } -} -#[doc = "Field `GIWE10` writer - Global Interrupt Write Enable"] -pub type Giwe10W<'a, REG> = crate::BitWriter<'a, REG, Giwe10>; -impl<'a, REG> Giwe10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe10::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe10::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe11 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE11` reader - Global Interrupt Write Enable"] -pub type Giwe11R = crate::BitReader; -impl Giwe11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe11 { - match self.bits { - false => Giwe11::Giwe0, - true => Giwe11::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe11::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe11::Giwe1 - } -} -#[doc = "Field `GIWE11` writer - Global Interrupt Write Enable"] -pub type Giwe11W<'a, REG> = crate::BitWriter<'a, REG, Giwe11>; -impl<'a, REG> Giwe11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe11::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe11::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe12 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE12` reader - Global Interrupt Write Enable"] -pub type Giwe12R = crate::BitReader; -impl Giwe12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe12 { - match self.bits { - false => Giwe12::Giwe0, - true => Giwe12::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe12::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe12::Giwe1 - } -} -#[doc = "Field `GIWE12` writer - Global Interrupt Write Enable"] -pub type Giwe12W<'a, REG> = crate::BitWriter<'a, REG, Giwe12>; -impl<'a, REG> Giwe12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe12::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe12::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe13 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE13` reader - Global Interrupt Write Enable"] -pub type Giwe13R = crate::BitReader; -impl Giwe13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe13 { - match self.bits { - false => Giwe13::Giwe0, - true => Giwe13::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe13::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe13::Giwe1 - } -} -#[doc = "Field `GIWE13` writer - Global Interrupt Write Enable"] -pub type Giwe13W<'a, REG> = crate::BitWriter<'a, REG, Giwe13>; -impl<'a, REG> Giwe13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe13::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe13::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe14 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE14` reader - Global Interrupt Write Enable"] -pub type Giwe14R = crate::BitReader; -impl Giwe14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe14 { - match self.bits { - false => Giwe14::Giwe0, - true => Giwe14::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe14::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe14::Giwe1 - } -} -#[doc = "Field `GIWE14` writer - Global Interrupt Write Enable"] -pub type Giwe14W<'a, REG> = crate::BitWriter<'a, REG, Giwe14>; -impl<'a, REG> Giwe14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe14::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe14::Giwe1) - } -} -#[doc = "Global Interrupt Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Giwe15 { - #[doc = "0: Not updated"] - Giwe0 = 0, - #[doc = "1: Updated"] - Giwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Giwe15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GIWE15` reader - Global Interrupt Write Enable"] -pub type Giwe15R = crate::BitReader; -impl Giwe15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Giwe15 { - match self.bits { - false => Giwe15::Giwe0, - true => Giwe15::Giwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_giwe0(&self) -> bool { - *self == Giwe15::Giwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_giwe1(&self) -> bool { - *self == Giwe15::Giwe1 - } -} -#[doc = "Field `GIWE15` writer - Global Interrupt Write Enable"] -pub type Giwe15W<'a, REG> = crate::BitWriter<'a, REG, Giwe15>; -impl<'a, REG> Giwe15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn giwe0(self) -> &'a mut crate::W { - self.variant(Giwe15::Giwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn giwe1(self) -> &'a mut crate::W { - self.variant(Giwe15::Giwe1) - } -} -#[doc = "Field `GIWD` reader - Global Interrupt Write Data"] -pub type GiwdR = crate::FieldReader; -#[doc = "Field `GIWD` writer - Global Interrupt Write Data"] -pub type GiwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bit 0 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe0(&self) -> Giwe0R { - Giwe0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe1(&self) -> Giwe1R { - Giwe1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe2(&self) -> Giwe2R { - Giwe2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe3(&self) -> Giwe3R { - Giwe3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe4(&self) -> Giwe4R { - Giwe4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe5(&self) -> Giwe5R { - Giwe5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe6(&self) -> Giwe6R { - Giwe6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe7(&self) -> Giwe7R { - Giwe7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe8(&self) -> Giwe8R { - Giwe8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe9(&self) -> Giwe9R { - Giwe9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe10(&self) -> Giwe10R { - Giwe10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe11(&self) -> Giwe11R { - Giwe11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe12(&self) -> Giwe12R { - Giwe12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe13(&self) -> Giwe13R { - Giwe13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe14(&self) -> Giwe14R { - Giwe14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe15(&self) -> Giwe15R { - Giwe15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:31 - Global Interrupt Write Data"] - #[inline(always)] - pub fn giwd(&self) -> GiwdR { - GiwdR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bit 0 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe0(&mut self) -> Giwe0W { - Giwe0W::new(self, 0) - } - #[doc = "Bit 1 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe1(&mut self) -> Giwe1W { - Giwe1W::new(self, 1) - } - #[doc = "Bit 2 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe2(&mut self) -> Giwe2W { - Giwe2W::new(self, 2) - } - #[doc = "Bit 3 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe3(&mut self) -> Giwe3W { - Giwe3W::new(self, 3) - } - #[doc = "Bit 4 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe4(&mut self) -> Giwe4W { - Giwe4W::new(self, 4) - } - #[doc = "Bit 5 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe5(&mut self) -> Giwe5W { - Giwe5W::new(self, 5) - } - #[doc = "Bit 6 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe6(&mut self) -> Giwe6W { - Giwe6W::new(self, 6) - } - #[doc = "Bit 7 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe7(&mut self) -> Giwe7W { - Giwe7W::new(self, 7) - } - #[doc = "Bit 8 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe8(&mut self) -> Giwe8W { - Giwe8W::new(self, 8) - } - #[doc = "Bit 9 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe9(&mut self) -> Giwe9W { - Giwe9W::new(self, 9) - } - #[doc = "Bit 10 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe10(&mut self) -> Giwe10W { - Giwe10W::new(self, 10) - } - #[doc = "Bit 11 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe11(&mut self) -> Giwe11W { - Giwe11W::new(self, 11) - } - #[doc = "Bit 12 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe12(&mut self) -> Giwe12W { - Giwe12W::new(self, 12) - } - #[doc = "Bit 13 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe13(&mut self) -> Giwe13W { - Giwe13W::new(self, 13) - } - #[doc = "Bit 14 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe14(&mut self) -> Giwe14W { - Giwe14W::new(self, 14) - } - #[doc = "Bit 15 - Global Interrupt Write Enable"] - #[inline(always)] - pub fn giwe15(&mut self) -> Giwe15W { - Giwe15W::new(self, 15) - } - #[doc = "Bits 16:31 - Global Interrupt Write Data"] - #[inline(always)] - pub fn giwd(&mut self) -> GiwdW { - GiwdW::new(self, 16) - } -} -#[doc = "Global Interrupt Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`giclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`giclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GiclrSpec; -impl crate::RegisterSpec for GiclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`giclr::R`](R) reader structure"] -impl crate::Readable for GiclrSpec {} -#[doc = "`write(|w| ..)` method takes [`giclr::W`](W) writer structure"] -impl crate::Writable for GiclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GICLR to value 0"] -impl crate::Resettable for GiclrSpec {} diff --git a/mcxa276-pac/src/gpio0/icr.rs b/mcxa276-pac/src/gpio0/icr.rs deleted file mode 100644 index 5cdb64489..000000000 --- a/mcxa276-pac/src/gpio0/icr.rs +++ /dev/null @@ -1,311 +0,0 @@ -#[doc = "Register `ICR[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `ICR[%s]` writer"] -pub type W = crate::W; -#[doc = "Interrupt Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Irqc { - #[doc = "0: ISF is disabled"] - Irqc0 = 0, - #[doc = "1: ISF and DMA request on rising edge"] - Irqc1 = 1, - #[doc = "2: ISF and DMA request on falling edge"] - Irqc2 = 2, - #[doc = "3: ISF and DMA request on either edge"] - Irqc3 = 3, - #[doc = "5: ISF sets on rising edge"] - Irqc5 = 5, - #[doc = "6: ISF sets on falling edge"] - Irqc6 = 6, - #[doc = "7: ISF sets on either edge"] - Irqc7 = 7, - #[doc = "8: ISF and interrupt when logic 0"] - Irqc8 = 8, - #[doc = "9: ISF and interrupt on rising edge"] - Irqc9 = 9, - #[doc = "10: ISF and interrupt on falling edge"] - Irqc10 = 10, - #[doc = "11: ISF and Interrupt on either edge"] - Irqc11 = 11, - #[doc = "12: ISF and interrupt when logic 1"] - Irqc12 = 12, - #[doc = "13: Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] - Irqc13 = 13, - #[doc = "14: Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] - Irqc14 = 14, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Irqc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Irqc { - type Ux = u8; -} -impl crate::IsEnum for Irqc {} -#[doc = "Field `IRQC` reader - Interrupt Configuration"] -pub type IrqcR = crate::FieldReader; -impl IrqcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Irqc::Irqc0), - 1 => Some(Irqc::Irqc1), - 2 => Some(Irqc::Irqc2), - 3 => Some(Irqc::Irqc3), - 5 => Some(Irqc::Irqc5), - 6 => Some(Irqc::Irqc6), - 7 => Some(Irqc::Irqc7), - 8 => Some(Irqc::Irqc8), - 9 => Some(Irqc::Irqc9), - 10 => Some(Irqc::Irqc10), - 11 => Some(Irqc::Irqc11), - 12 => Some(Irqc::Irqc12), - 13 => Some(Irqc::Irqc13), - 14 => Some(Irqc::Irqc14), - _ => None, - } - } - #[doc = "ISF is disabled"] - #[inline(always)] - pub fn is_irqc0(&self) -> bool { - *self == Irqc::Irqc0 - } - #[doc = "ISF and DMA request on rising edge"] - #[inline(always)] - pub fn is_irqc1(&self) -> bool { - *self == Irqc::Irqc1 - } - #[doc = "ISF and DMA request on falling edge"] - #[inline(always)] - pub fn is_irqc2(&self) -> bool { - *self == Irqc::Irqc2 - } - #[doc = "ISF and DMA request on either edge"] - #[inline(always)] - pub fn is_irqc3(&self) -> bool { - *self == Irqc::Irqc3 - } - #[doc = "ISF sets on rising edge"] - #[inline(always)] - pub fn is_irqc5(&self) -> bool { - *self == Irqc::Irqc5 - } - #[doc = "ISF sets on falling edge"] - #[inline(always)] - pub fn is_irqc6(&self) -> bool { - *self == Irqc::Irqc6 - } - #[doc = "ISF sets on either edge"] - #[inline(always)] - pub fn is_irqc7(&self) -> bool { - *self == Irqc::Irqc7 - } - #[doc = "ISF and interrupt when logic 0"] - #[inline(always)] - pub fn is_irqc8(&self) -> bool { - *self == Irqc::Irqc8 - } - #[doc = "ISF and interrupt on rising edge"] - #[inline(always)] - pub fn is_irqc9(&self) -> bool { - *self == Irqc::Irqc9 - } - #[doc = "ISF and interrupt on falling edge"] - #[inline(always)] - pub fn is_irqc10(&self) -> bool { - *self == Irqc::Irqc10 - } - #[doc = "ISF and Interrupt on either edge"] - #[inline(always)] - pub fn is_irqc11(&self) -> bool { - *self == Irqc::Irqc11 - } - #[doc = "ISF and interrupt when logic 1"] - #[inline(always)] - pub fn is_irqc12(&self) -> bool { - *self == Irqc::Irqc12 - } - #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] - #[inline(always)] - pub fn is_irqc13(&self) -> bool { - *self == Irqc::Irqc13 - } - #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] - #[inline(always)] - pub fn is_irqc14(&self) -> bool { - *self == Irqc::Irqc14 - } -} -#[doc = "Field `IRQC` writer - Interrupt Configuration"] -pub type IrqcW<'a, REG> = crate::FieldWriter<'a, REG, 4, Irqc>; -impl<'a, REG> IrqcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ISF is disabled"] - #[inline(always)] - pub fn irqc0(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc0) - } - #[doc = "ISF and DMA request on rising edge"] - #[inline(always)] - pub fn irqc1(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc1) - } - #[doc = "ISF and DMA request on falling edge"] - #[inline(always)] - pub fn irqc2(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc2) - } - #[doc = "ISF and DMA request on either edge"] - #[inline(always)] - pub fn irqc3(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc3) - } - #[doc = "ISF sets on rising edge"] - #[inline(always)] - pub fn irqc5(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc5) - } - #[doc = "ISF sets on falling edge"] - #[inline(always)] - pub fn irqc6(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc6) - } - #[doc = "ISF sets on either edge"] - #[inline(always)] - pub fn irqc7(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc7) - } - #[doc = "ISF and interrupt when logic 0"] - #[inline(always)] - pub fn irqc8(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc8) - } - #[doc = "ISF and interrupt on rising edge"] - #[inline(always)] - pub fn irqc9(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc9) - } - #[doc = "ISF and interrupt on falling edge"] - #[inline(always)] - pub fn irqc10(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc10) - } - #[doc = "ISF and Interrupt on either edge"] - #[inline(always)] - pub fn irqc11(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc11) - } - #[doc = "ISF and interrupt when logic 1"] - #[inline(always)] - pub fn irqc12(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc12) - } - #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] - #[inline(always)] - pub fn irqc13(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc13) - } - #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"] - #[inline(always)] - pub fn irqc14(self) -> &'a mut crate::W { - self.variant(Irqc::Irqc14) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF` reader - Interrupt Status Flag"] -pub type IsfR = crate::BitReader; -impl IsfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf { - match self.bits { - false => Isf::Isf0, - true => Isf::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf::Isf1 - } -} -#[doc = "Field `ISF` writer - Interrupt Status Flag"] -pub type IsfW<'a, REG> = crate::BitWriter1C<'a, REG, Isf>; -impl<'a, REG> IsfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf::Isf1) - } -} -impl R { - #[doc = "Bits 16:19 - Interrupt Configuration"] - #[inline(always)] - pub fn irqc(&self) -> IrqcR { - IrqcR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 24 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf(&self) -> IsfR { - IsfR::new(((self.bits >> 24) & 1) != 0) - } -} -impl W { - #[doc = "Bits 16:19 - Interrupt Configuration"] - #[inline(always)] - pub fn irqc(&mut self) -> IrqcW { - IrqcW::new(self, 16) - } - #[doc = "Bit 24 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf(&mut self) -> IsfW { - IsfW::new(self, 24) - } -} -#[doc = "Interrupt Control index\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IcrSpec; -impl crate::RegisterSpec for IcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`icr::R`](R) reader structure"] -impl crate::Readable for IcrSpec {} -#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] -impl crate::Writable for IcrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0100_0000; -} -#[doc = "`reset()` method sets ICR[%s] to value 0"] -impl crate::Resettable for IcrSpec {} diff --git a/mcxa276-pac/src/gpio0/isfr0.rs b/mcxa276-pac/src/gpio0/isfr0.rs deleted file mode 100644 index aff3f0b1b..000000000 --- a/mcxa276-pac/src/gpio0/isfr0.rs +++ /dev/null @@ -1,2038 +0,0 @@ -#[doc = "Register `ISFR0` reader"] -pub type R = crate::R; -#[doc = "Register `ISFR0` writer"] -pub type W = crate::W; -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf0 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF0` reader - Interrupt Status Flag"] -pub type Isf0R = crate::BitReader; -impl Isf0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf0 { - match self.bits { - false => Isf0::Isf0, - true => Isf0::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf0::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf0::Isf1 - } -} -#[doc = "Field `ISF0` writer - Interrupt Status Flag"] -pub type Isf0W<'a, REG> = crate::BitWriter1C<'a, REG, Isf0>; -impl<'a, REG> Isf0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf0::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf0::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf1 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF1` reader - Interrupt Status Flag"] -pub type Isf1R = crate::BitReader; -impl Isf1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf1 { - match self.bits { - false => Isf1::Isf0, - true => Isf1::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf1::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf1::Isf1 - } -} -#[doc = "Field `ISF1` writer - Interrupt Status Flag"] -pub type Isf1W<'a, REG> = crate::BitWriter1C<'a, REG, Isf1>; -impl<'a, REG> Isf1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf1::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf1::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf2 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF2` reader - Interrupt Status Flag"] -pub type Isf2R = crate::BitReader; -impl Isf2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf2 { - match self.bits { - false => Isf2::Isf0, - true => Isf2::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf2::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf2::Isf1 - } -} -#[doc = "Field `ISF2` writer - Interrupt Status Flag"] -pub type Isf2W<'a, REG> = crate::BitWriter1C<'a, REG, Isf2>; -impl<'a, REG> Isf2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf2::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf2::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf3 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF3` reader - Interrupt Status Flag"] -pub type Isf3R = crate::BitReader; -impl Isf3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf3 { - match self.bits { - false => Isf3::Isf0, - true => Isf3::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf3::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf3::Isf1 - } -} -#[doc = "Field `ISF3` writer - Interrupt Status Flag"] -pub type Isf3W<'a, REG> = crate::BitWriter1C<'a, REG, Isf3>; -impl<'a, REG> Isf3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf3::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf3::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf4 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF4` reader - Interrupt Status Flag"] -pub type Isf4R = crate::BitReader; -impl Isf4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf4 { - match self.bits { - false => Isf4::Isf0, - true => Isf4::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf4::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf4::Isf1 - } -} -#[doc = "Field `ISF4` writer - Interrupt Status Flag"] -pub type Isf4W<'a, REG> = crate::BitWriter1C<'a, REG, Isf4>; -impl<'a, REG> Isf4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf4::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf4::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf5 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF5` reader - Interrupt Status Flag"] -pub type Isf5R = crate::BitReader; -impl Isf5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf5 { - match self.bits { - false => Isf5::Isf0, - true => Isf5::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf5::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf5::Isf1 - } -} -#[doc = "Field `ISF5` writer - Interrupt Status Flag"] -pub type Isf5W<'a, REG> = crate::BitWriter1C<'a, REG, Isf5>; -impl<'a, REG> Isf5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf5::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf5::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf6 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF6` reader - Interrupt Status Flag"] -pub type Isf6R = crate::BitReader; -impl Isf6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf6 { - match self.bits { - false => Isf6::Isf0, - true => Isf6::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf6::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf6::Isf1 - } -} -#[doc = "Field `ISF6` writer - Interrupt Status Flag"] -pub type Isf6W<'a, REG> = crate::BitWriter1C<'a, REG, Isf6>; -impl<'a, REG> Isf6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf6::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf6::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf7 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF7` reader - Interrupt Status Flag"] -pub type Isf7R = crate::BitReader; -impl Isf7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf7 { - match self.bits { - false => Isf7::Isf0, - true => Isf7::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf7::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf7::Isf1 - } -} -#[doc = "Field `ISF7` writer - Interrupt Status Flag"] -pub type Isf7W<'a, REG> = crate::BitWriter1C<'a, REG, Isf7>; -impl<'a, REG> Isf7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf7::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf7::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf8 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF8` reader - Interrupt Status Flag"] -pub type Isf8R = crate::BitReader; -impl Isf8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf8 { - match self.bits { - false => Isf8::Isf0, - true => Isf8::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf8::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf8::Isf1 - } -} -#[doc = "Field `ISF8` writer - Interrupt Status Flag"] -pub type Isf8W<'a, REG> = crate::BitWriter1C<'a, REG, Isf8>; -impl<'a, REG> Isf8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf8::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf8::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf9 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF9` reader - Interrupt Status Flag"] -pub type Isf9R = crate::BitReader; -impl Isf9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf9 { - match self.bits { - false => Isf9::Isf0, - true => Isf9::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf9::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf9::Isf1 - } -} -#[doc = "Field `ISF9` writer - Interrupt Status Flag"] -pub type Isf9W<'a, REG> = crate::BitWriter1C<'a, REG, Isf9>; -impl<'a, REG> Isf9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf9::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf9::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf10 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF10` reader - Interrupt Status Flag"] -pub type Isf10R = crate::BitReader; -impl Isf10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf10 { - match self.bits { - false => Isf10::Isf0, - true => Isf10::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf10::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf10::Isf1 - } -} -#[doc = "Field `ISF10` writer - Interrupt Status Flag"] -pub type Isf10W<'a, REG> = crate::BitWriter1C<'a, REG, Isf10>; -impl<'a, REG> Isf10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf10::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf10::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf11 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF11` reader - Interrupt Status Flag"] -pub type Isf11R = crate::BitReader; -impl Isf11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf11 { - match self.bits { - false => Isf11::Isf0, - true => Isf11::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf11::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf11::Isf1 - } -} -#[doc = "Field `ISF11` writer - Interrupt Status Flag"] -pub type Isf11W<'a, REG> = crate::BitWriter1C<'a, REG, Isf11>; -impl<'a, REG> Isf11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf11::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf11::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf12 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF12` reader - Interrupt Status Flag"] -pub type Isf12R = crate::BitReader; -impl Isf12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf12 { - match self.bits { - false => Isf12::Isf0, - true => Isf12::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf12::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf12::Isf1 - } -} -#[doc = "Field `ISF12` writer - Interrupt Status Flag"] -pub type Isf12W<'a, REG> = crate::BitWriter1C<'a, REG, Isf12>; -impl<'a, REG> Isf12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf12::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf12::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf13 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF13` reader - Interrupt Status Flag"] -pub type Isf13R = crate::BitReader; -impl Isf13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf13 { - match self.bits { - false => Isf13::Isf0, - true => Isf13::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf13::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf13::Isf1 - } -} -#[doc = "Field `ISF13` writer - Interrupt Status Flag"] -pub type Isf13W<'a, REG> = crate::BitWriter1C<'a, REG, Isf13>; -impl<'a, REG> Isf13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf13::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf13::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf14 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF14` reader - Interrupt Status Flag"] -pub type Isf14R = crate::BitReader; -impl Isf14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf14 { - match self.bits { - false => Isf14::Isf0, - true => Isf14::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf14::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf14::Isf1 - } -} -#[doc = "Field `ISF14` writer - Interrupt Status Flag"] -pub type Isf14W<'a, REG> = crate::BitWriter1C<'a, REG, Isf14>; -impl<'a, REG> Isf14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf14::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf14::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf15 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF15` reader - Interrupt Status Flag"] -pub type Isf15R = crate::BitReader; -impl Isf15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf15 { - match self.bits { - false => Isf15::Isf0, - true => Isf15::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf15::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf15::Isf1 - } -} -#[doc = "Field `ISF15` writer - Interrupt Status Flag"] -pub type Isf15W<'a, REG> = crate::BitWriter1C<'a, REG, Isf15>; -impl<'a, REG> Isf15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf15::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf15::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf16 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF16` reader - Interrupt Status Flag"] -pub type Isf16R = crate::BitReader; -impl Isf16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf16 { - match self.bits { - false => Isf16::Isf0, - true => Isf16::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf16::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf16::Isf1 - } -} -#[doc = "Field `ISF16` writer - Interrupt Status Flag"] -pub type Isf16W<'a, REG> = crate::BitWriter1C<'a, REG, Isf16>; -impl<'a, REG> Isf16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf16::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf16::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf17 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF17` reader - Interrupt Status Flag"] -pub type Isf17R = crate::BitReader; -impl Isf17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf17 { - match self.bits { - false => Isf17::Isf0, - true => Isf17::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf17::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf17::Isf1 - } -} -#[doc = "Field `ISF17` writer - Interrupt Status Flag"] -pub type Isf17W<'a, REG> = crate::BitWriter1C<'a, REG, Isf17>; -impl<'a, REG> Isf17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf17::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf17::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf18 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF18` reader - Interrupt Status Flag"] -pub type Isf18R = crate::BitReader; -impl Isf18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf18 { - match self.bits { - false => Isf18::Isf0, - true => Isf18::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf18::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf18::Isf1 - } -} -#[doc = "Field `ISF18` writer - Interrupt Status Flag"] -pub type Isf18W<'a, REG> = crate::BitWriter1C<'a, REG, Isf18>; -impl<'a, REG> Isf18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf18::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf18::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf19 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF19` reader - Interrupt Status Flag"] -pub type Isf19R = crate::BitReader; -impl Isf19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf19 { - match self.bits { - false => Isf19::Isf0, - true => Isf19::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf19::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf19::Isf1 - } -} -#[doc = "Field `ISF19` writer - Interrupt Status Flag"] -pub type Isf19W<'a, REG> = crate::BitWriter1C<'a, REG, Isf19>; -impl<'a, REG> Isf19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf19::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf19::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf20 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF20` reader - Interrupt Status Flag"] -pub type Isf20R = crate::BitReader; -impl Isf20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf20 { - match self.bits { - false => Isf20::Isf0, - true => Isf20::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf20::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf20::Isf1 - } -} -#[doc = "Field `ISF20` writer - Interrupt Status Flag"] -pub type Isf20W<'a, REG> = crate::BitWriter1C<'a, REG, Isf20>; -impl<'a, REG> Isf20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf20::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf20::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf21 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF21` reader - Interrupt Status Flag"] -pub type Isf21R = crate::BitReader; -impl Isf21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf21 { - match self.bits { - false => Isf21::Isf0, - true => Isf21::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf21::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf21::Isf1 - } -} -#[doc = "Field `ISF21` writer - Interrupt Status Flag"] -pub type Isf21W<'a, REG> = crate::BitWriter1C<'a, REG, Isf21>; -impl<'a, REG> Isf21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf21::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf21::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf22 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF22` reader - Interrupt Status Flag"] -pub type Isf22R = crate::BitReader; -impl Isf22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf22 { - match self.bits { - false => Isf22::Isf0, - true => Isf22::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf22::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf22::Isf1 - } -} -#[doc = "Field `ISF22` writer - Interrupt Status Flag"] -pub type Isf22W<'a, REG> = crate::BitWriter1C<'a, REG, Isf22>; -impl<'a, REG> Isf22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf22::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf22::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf23 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF23` reader - Interrupt Status Flag"] -pub type Isf23R = crate::BitReader; -impl Isf23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf23 { - match self.bits { - false => Isf23::Isf0, - true => Isf23::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf23::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf23::Isf1 - } -} -#[doc = "Field `ISF23` writer - Interrupt Status Flag"] -pub type Isf23W<'a, REG> = crate::BitWriter1C<'a, REG, Isf23>; -impl<'a, REG> Isf23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf23::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf23::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf24 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF24` reader - Interrupt Status Flag"] -pub type Isf24R = crate::BitReader; -impl Isf24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf24 { - match self.bits { - false => Isf24::Isf0, - true => Isf24::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf24::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf24::Isf1 - } -} -#[doc = "Field `ISF24` writer - Interrupt Status Flag"] -pub type Isf24W<'a, REG> = crate::BitWriter1C<'a, REG, Isf24>; -impl<'a, REG> Isf24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf24::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf24::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf25 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF25` reader - Interrupt Status Flag"] -pub type Isf25R = crate::BitReader; -impl Isf25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf25 { - match self.bits { - false => Isf25::Isf0, - true => Isf25::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf25::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf25::Isf1 - } -} -#[doc = "Field `ISF25` writer - Interrupt Status Flag"] -pub type Isf25W<'a, REG> = crate::BitWriter1C<'a, REG, Isf25>; -impl<'a, REG> Isf25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf25::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf25::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf26 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF26` reader - Interrupt Status Flag"] -pub type Isf26R = crate::BitReader; -impl Isf26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf26 { - match self.bits { - false => Isf26::Isf0, - true => Isf26::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf26::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf26::Isf1 - } -} -#[doc = "Field `ISF26` writer - Interrupt Status Flag"] -pub type Isf26W<'a, REG> = crate::BitWriter1C<'a, REG, Isf26>; -impl<'a, REG> Isf26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf26::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf26::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf27 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF27` reader - Interrupt Status Flag"] -pub type Isf27R = crate::BitReader; -impl Isf27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf27 { - match self.bits { - false => Isf27::Isf0, - true => Isf27::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf27::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf27::Isf1 - } -} -#[doc = "Field `ISF27` writer - Interrupt Status Flag"] -pub type Isf27W<'a, REG> = crate::BitWriter1C<'a, REG, Isf27>; -impl<'a, REG> Isf27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf27::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf27::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf28 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF28` reader - Interrupt Status Flag"] -pub type Isf28R = crate::BitReader; -impl Isf28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf28 { - match self.bits { - false => Isf28::Isf0, - true => Isf28::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf28::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf28::Isf1 - } -} -#[doc = "Field `ISF28` writer - Interrupt Status Flag"] -pub type Isf28W<'a, REG> = crate::BitWriter1C<'a, REG, Isf28>; -impl<'a, REG> Isf28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf28::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf28::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf29 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF29` reader - Interrupt Status Flag"] -pub type Isf29R = crate::BitReader; -impl Isf29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf29 { - match self.bits { - false => Isf29::Isf0, - true => Isf29::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf29::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf29::Isf1 - } -} -#[doc = "Field `ISF29` writer - Interrupt Status Flag"] -pub type Isf29W<'a, REG> = crate::BitWriter1C<'a, REG, Isf29>; -impl<'a, REG> Isf29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf29::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf29::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf30 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF30` reader - Interrupt Status Flag"] -pub type Isf30R = crate::BitReader; -impl Isf30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf30 { - match self.bits { - false => Isf30::Isf0, - true => Isf30::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf30::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf30::Isf1 - } -} -#[doc = "Field `ISF30` writer - Interrupt Status Flag"] -pub type Isf30W<'a, REG> = crate::BitWriter1C<'a, REG, Isf30>; -impl<'a, REG> Isf30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf30::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf30::Isf1) - } -} -#[doc = "Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Isf31 { - #[doc = "0: Not detected"] - Isf0 = 0, - #[doc = "1: Detected"] - Isf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Isf31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ISF31` reader - Interrupt Status Flag"] -pub type Isf31R = crate::BitReader; -impl Isf31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Isf31 { - match self.bits { - false => Isf31::Isf0, - true => Isf31::Isf1, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_isf0(&self) -> bool { - *self == Isf31::Isf0 - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_isf1(&self) -> bool { - *self == Isf31::Isf1 - } -} -#[doc = "Field `ISF31` writer - Interrupt Status Flag"] -pub type Isf31W<'a, REG> = crate::BitWriter1C<'a, REG, Isf31>; -impl<'a, REG> Isf31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn isf0(self) -> &'a mut crate::W { - self.variant(Isf31::Isf0) - } - #[doc = "Detected"] - #[inline(always)] - pub fn isf1(self) -> &'a mut crate::W { - self.variant(Isf31::Isf1) - } -} -impl R { - #[doc = "Bit 0 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf0(&self) -> Isf0R { - Isf0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf1(&self) -> Isf1R { - Isf1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf2(&self) -> Isf2R { - Isf2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf3(&self) -> Isf3R { - Isf3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf4(&self) -> Isf4R { - Isf4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf5(&self) -> Isf5R { - Isf5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf6(&self) -> Isf6R { - Isf6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf7(&self) -> Isf7R { - Isf7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf8(&self) -> Isf8R { - Isf8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf9(&self) -> Isf9R { - Isf9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf10(&self) -> Isf10R { - Isf10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf11(&self) -> Isf11R { - Isf11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf12(&self) -> Isf12R { - Isf12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf13(&self) -> Isf13R { - Isf13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf14(&self) -> Isf14R { - Isf14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf15(&self) -> Isf15R { - Isf15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf16(&self) -> Isf16R { - Isf16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf17(&self) -> Isf17R { - Isf17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf18(&self) -> Isf18R { - Isf18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf19(&self) -> Isf19R { - Isf19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf20(&self) -> Isf20R { - Isf20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf21(&self) -> Isf21R { - Isf21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf22(&self) -> Isf22R { - Isf22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf23(&self) -> Isf23R { - Isf23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf24(&self) -> Isf24R { - Isf24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf25(&self) -> Isf25R { - Isf25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf26(&self) -> Isf26R { - Isf26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf27(&self) -> Isf27R { - Isf27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf28(&self) -> Isf28R { - Isf28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf29(&self) -> Isf29R { - Isf29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf30(&self) -> Isf30R { - Isf30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf31(&self) -> Isf31R { - Isf31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf0(&mut self) -> Isf0W { - Isf0W::new(self, 0) - } - #[doc = "Bit 1 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf1(&mut self) -> Isf1W { - Isf1W::new(self, 1) - } - #[doc = "Bit 2 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf2(&mut self) -> Isf2W { - Isf2W::new(self, 2) - } - #[doc = "Bit 3 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf3(&mut self) -> Isf3W { - Isf3W::new(self, 3) - } - #[doc = "Bit 4 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf4(&mut self) -> Isf4W { - Isf4W::new(self, 4) - } - #[doc = "Bit 5 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf5(&mut self) -> Isf5W { - Isf5W::new(self, 5) - } - #[doc = "Bit 6 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf6(&mut self) -> Isf6W { - Isf6W::new(self, 6) - } - #[doc = "Bit 7 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf7(&mut self) -> Isf7W { - Isf7W::new(self, 7) - } - #[doc = "Bit 8 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf8(&mut self) -> Isf8W { - Isf8W::new(self, 8) - } - #[doc = "Bit 9 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf9(&mut self) -> Isf9W { - Isf9W::new(self, 9) - } - #[doc = "Bit 10 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf10(&mut self) -> Isf10W { - Isf10W::new(self, 10) - } - #[doc = "Bit 11 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf11(&mut self) -> Isf11W { - Isf11W::new(self, 11) - } - #[doc = "Bit 12 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf12(&mut self) -> Isf12W { - Isf12W::new(self, 12) - } - #[doc = "Bit 13 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf13(&mut self) -> Isf13W { - Isf13W::new(self, 13) - } - #[doc = "Bit 14 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf14(&mut self) -> Isf14W { - Isf14W::new(self, 14) - } - #[doc = "Bit 15 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf15(&mut self) -> Isf15W { - Isf15W::new(self, 15) - } - #[doc = "Bit 16 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf16(&mut self) -> Isf16W { - Isf16W::new(self, 16) - } - #[doc = "Bit 17 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf17(&mut self) -> Isf17W { - Isf17W::new(self, 17) - } - #[doc = "Bit 18 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf18(&mut self) -> Isf18W { - Isf18W::new(self, 18) - } - #[doc = "Bit 19 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf19(&mut self) -> Isf19W { - Isf19W::new(self, 19) - } - #[doc = "Bit 20 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf20(&mut self) -> Isf20W { - Isf20W::new(self, 20) - } - #[doc = "Bit 21 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf21(&mut self) -> Isf21W { - Isf21W::new(self, 21) - } - #[doc = "Bit 22 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf22(&mut self) -> Isf22W { - Isf22W::new(self, 22) - } - #[doc = "Bit 23 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf23(&mut self) -> Isf23W { - Isf23W::new(self, 23) - } - #[doc = "Bit 24 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf24(&mut self) -> Isf24W { - Isf24W::new(self, 24) - } - #[doc = "Bit 25 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf25(&mut self) -> Isf25W { - Isf25W::new(self, 25) - } - #[doc = "Bit 26 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf26(&mut self) -> Isf26W { - Isf26W::new(self, 26) - } - #[doc = "Bit 27 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf27(&mut self) -> Isf27W { - Isf27W::new(self, 27) - } - #[doc = "Bit 28 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf28(&mut self) -> Isf28W { - Isf28W::new(self, 28) - } - #[doc = "Bit 29 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf29(&mut self) -> Isf29W { - Isf29W::new(self, 29) - } - #[doc = "Bit 30 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf30(&mut self) -> Isf30W { - Isf30W::new(self, 30) - } - #[doc = "Bit 31 - Interrupt Status Flag"] - #[inline(always)] - pub fn isf31(&mut self) -> Isf31W { - Isf31W::new(self, 31) - } -} -#[doc = "Interrupt Status Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`isfr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isfr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Isfr0Spec; -impl crate::RegisterSpec for Isfr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`isfr0::R`](R) reader structure"] -impl crate::Readable for Isfr0Spec {} -#[doc = "`write(|w| ..)` method takes [`isfr0::W`](W) writer structure"] -impl crate::Writable for Isfr0Spec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; -} -#[doc = "`reset()` method sets ISFR0 to value 0"] -impl crate::Resettable for Isfr0Spec {} diff --git a/mcxa276-pac/src/gpio0/param.rs b/mcxa276-pac/src/gpio0/param.rs deleted file mode 100644 index 8544fc60e..000000000 --- a/mcxa276-pac/src/gpio0/param.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "Field `IRQNUM` reader - Interrupt Number"] -pub type IrqnumR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Interrupt Number"] - #[inline(always)] - pub fn irqnum(&self) -> IrqnumR { - IrqnumR::new((self.bits & 0x0f) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x01"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/gpio0/pcor.rs b/mcxa276-pac/src/gpio0/pcor.rs deleted file mode 100644 index 705ec181b..000000000 --- a/mcxa276-pac/src/gpio0/pcor.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `PCOR` reader"] -pub type R = crate::R; -#[doc = "Register `PCOR` writer"] -pub type W = crate::W; -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco0 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO0` reader - Port Clear Output"] -pub type Ptco0R = crate::BitReader; -impl Ptco0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco0 { - match self.bits { - false => Ptco0::Ptco0, - true => Ptco0::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco0::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco0::Ptco1 - } -} -#[doc = "Field `PTCO0` writer - Port Clear Output"] -pub type Ptco0W<'a, REG> = crate::BitWriter<'a, REG, Ptco0>; -impl<'a, REG> Ptco0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco0::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco0::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco1 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO1` reader - Port Clear Output"] -pub type Ptco1R = crate::BitReader; -impl Ptco1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco1 { - match self.bits { - false => Ptco1::Ptco0, - true => Ptco1::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco1::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco1::Ptco1 - } -} -#[doc = "Field `PTCO1` writer - Port Clear Output"] -pub type Ptco1W<'a, REG> = crate::BitWriter<'a, REG, Ptco1>; -impl<'a, REG> Ptco1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco1::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco1::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco2 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO2` reader - Port Clear Output"] -pub type Ptco2R = crate::BitReader; -impl Ptco2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco2 { - match self.bits { - false => Ptco2::Ptco0, - true => Ptco2::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco2::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco2::Ptco1 - } -} -#[doc = "Field `PTCO2` writer - Port Clear Output"] -pub type Ptco2W<'a, REG> = crate::BitWriter<'a, REG, Ptco2>; -impl<'a, REG> Ptco2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco2::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco2::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco3 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO3` reader - Port Clear Output"] -pub type Ptco3R = crate::BitReader; -impl Ptco3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco3 { - match self.bits { - false => Ptco3::Ptco0, - true => Ptco3::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco3::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco3::Ptco1 - } -} -#[doc = "Field `PTCO3` writer - Port Clear Output"] -pub type Ptco3W<'a, REG> = crate::BitWriter<'a, REG, Ptco3>; -impl<'a, REG> Ptco3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco3::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco3::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco4 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO4` reader - Port Clear Output"] -pub type Ptco4R = crate::BitReader; -impl Ptco4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco4 { - match self.bits { - false => Ptco4::Ptco0, - true => Ptco4::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco4::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco4::Ptco1 - } -} -#[doc = "Field `PTCO4` writer - Port Clear Output"] -pub type Ptco4W<'a, REG> = crate::BitWriter<'a, REG, Ptco4>; -impl<'a, REG> Ptco4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco4::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco4::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco5 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO5` reader - Port Clear Output"] -pub type Ptco5R = crate::BitReader; -impl Ptco5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco5 { - match self.bits { - false => Ptco5::Ptco0, - true => Ptco5::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco5::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco5::Ptco1 - } -} -#[doc = "Field `PTCO5` writer - Port Clear Output"] -pub type Ptco5W<'a, REG> = crate::BitWriter<'a, REG, Ptco5>; -impl<'a, REG> Ptco5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco5::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco5::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco6 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO6` reader - Port Clear Output"] -pub type Ptco6R = crate::BitReader; -impl Ptco6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco6 { - match self.bits { - false => Ptco6::Ptco0, - true => Ptco6::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco6::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco6::Ptco1 - } -} -#[doc = "Field `PTCO6` writer - Port Clear Output"] -pub type Ptco6W<'a, REG> = crate::BitWriter<'a, REG, Ptco6>; -impl<'a, REG> Ptco6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco6::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco6::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco7 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO7` reader - Port Clear Output"] -pub type Ptco7R = crate::BitReader; -impl Ptco7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco7 { - match self.bits { - false => Ptco7::Ptco0, - true => Ptco7::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco7::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco7::Ptco1 - } -} -#[doc = "Field `PTCO7` writer - Port Clear Output"] -pub type Ptco7W<'a, REG> = crate::BitWriter<'a, REG, Ptco7>; -impl<'a, REG> Ptco7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco7::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco7::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco8 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO8` reader - Port Clear Output"] -pub type Ptco8R = crate::BitReader; -impl Ptco8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco8 { - match self.bits { - false => Ptco8::Ptco0, - true => Ptco8::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco8::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco8::Ptco1 - } -} -#[doc = "Field `PTCO8` writer - Port Clear Output"] -pub type Ptco8W<'a, REG> = crate::BitWriter<'a, REG, Ptco8>; -impl<'a, REG> Ptco8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco8::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco8::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco9 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO9` reader - Port Clear Output"] -pub type Ptco9R = crate::BitReader; -impl Ptco9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco9 { - match self.bits { - false => Ptco9::Ptco0, - true => Ptco9::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco9::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco9::Ptco1 - } -} -#[doc = "Field `PTCO9` writer - Port Clear Output"] -pub type Ptco9W<'a, REG> = crate::BitWriter<'a, REG, Ptco9>; -impl<'a, REG> Ptco9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco9::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco9::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco10 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO10` reader - Port Clear Output"] -pub type Ptco10R = crate::BitReader; -impl Ptco10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco10 { - match self.bits { - false => Ptco10::Ptco0, - true => Ptco10::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco10::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco10::Ptco1 - } -} -#[doc = "Field `PTCO10` writer - Port Clear Output"] -pub type Ptco10W<'a, REG> = crate::BitWriter<'a, REG, Ptco10>; -impl<'a, REG> Ptco10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco10::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco10::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco11 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO11` reader - Port Clear Output"] -pub type Ptco11R = crate::BitReader; -impl Ptco11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco11 { - match self.bits { - false => Ptco11::Ptco0, - true => Ptco11::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco11::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco11::Ptco1 - } -} -#[doc = "Field `PTCO11` writer - Port Clear Output"] -pub type Ptco11W<'a, REG> = crate::BitWriter<'a, REG, Ptco11>; -impl<'a, REG> Ptco11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco11::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco11::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco12 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO12` reader - Port Clear Output"] -pub type Ptco12R = crate::BitReader; -impl Ptco12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco12 { - match self.bits { - false => Ptco12::Ptco0, - true => Ptco12::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco12::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco12::Ptco1 - } -} -#[doc = "Field `PTCO12` writer - Port Clear Output"] -pub type Ptco12W<'a, REG> = crate::BitWriter<'a, REG, Ptco12>; -impl<'a, REG> Ptco12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco12::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco12::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco13 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO13` reader - Port Clear Output"] -pub type Ptco13R = crate::BitReader; -impl Ptco13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco13 { - match self.bits { - false => Ptco13::Ptco0, - true => Ptco13::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco13::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco13::Ptco1 - } -} -#[doc = "Field `PTCO13` writer - Port Clear Output"] -pub type Ptco13W<'a, REG> = crate::BitWriter<'a, REG, Ptco13>; -impl<'a, REG> Ptco13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco13::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco13::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco14 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO14` reader - Port Clear Output"] -pub type Ptco14R = crate::BitReader; -impl Ptco14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco14 { - match self.bits { - false => Ptco14::Ptco0, - true => Ptco14::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco14::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco14::Ptco1 - } -} -#[doc = "Field `PTCO14` writer - Port Clear Output"] -pub type Ptco14W<'a, REG> = crate::BitWriter<'a, REG, Ptco14>; -impl<'a, REG> Ptco14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco14::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco14::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco15 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO15` reader - Port Clear Output"] -pub type Ptco15R = crate::BitReader; -impl Ptco15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco15 { - match self.bits { - false => Ptco15::Ptco0, - true => Ptco15::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco15::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco15::Ptco1 - } -} -#[doc = "Field `PTCO15` writer - Port Clear Output"] -pub type Ptco15W<'a, REG> = crate::BitWriter<'a, REG, Ptco15>; -impl<'a, REG> Ptco15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco15::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco15::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco16 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO16` reader - Port Clear Output"] -pub type Ptco16R = crate::BitReader; -impl Ptco16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco16 { - match self.bits { - false => Ptco16::Ptco0, - true => Ptco16::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco16::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco16::Ptco1 - } -} -#[doc = "Field `PTCO16` writer - Port Clear Output"] -pub type Ptco16W<'a, REG> = crate::BitWriter<'a, REG, Ptco16>; -impl<'a, REG> Ptco16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco16::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco16::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco17 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO17` reader - Port Clear Output"] -pub type Ptco17R = crate::BitReader; -impl Ptco17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco17 { - match self.bits { - false => Ptco17::Ptco0, - true => Ptco17::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco17::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco17::Ptco1 - } -} -#[doc = "Field `PTCO17` writer - Port Clear Output"] -pub type Ptco17W<'a, REG> = crate::BitWriter<'a, REG, Ptco17>; -impl<'a, REG> Ptco17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco17::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco17::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco18 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO18` reader - Port Clear Output"] -pub type Ptco18R = crate::BitReader; -impl Ptco18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco18 { - match self.bits { - false => Ptco18::Ptco0, - true => Ptco18::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco18::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco18::Ptco1 - } -} -#[doc = "Field `PTCO18` writer - Port Clear Output"] -pub type Ptco18W<'a, REG> = crate::BitWriter<'a, REG, Ptco18>; -impl<'a, REG> Ptco18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco18::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco18::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco19 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO19` reader - Port Clear Output"] -pub type Ptco19R = crate::BitReader; -impl Ptco19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco19 { - match self.bits { - false => Ptco19::Ptco0, - true => Ptco19::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco19::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco19::Ptco1 - } -} -#[doc = "Field `PTCO19` writer - Port Clear Output"] -pub type Ptco19W<'a, REG> = crate::BitWriter<'a, REG, Ptco19>; -impl<'a, REG> Ptco19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco19::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco19::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco20 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO20` reader - Port Clear Output"] -pub type Ptco20R = crate::BitReader; -impl Ptco20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco20 { - match self.bits { - false => Ptco20::Ptco0, - true => Ptco20::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco20::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco20::Ptco1 - } -} -#[doc = "Field `PTCO20` writer - Port Clear Output"] -pub type Ptco20W<'a, REG> = crate::BitWriter<'a, REG, Ptco20>; -impl<'a, REG> Ptco20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco20::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco20::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco21 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO21` reader - Port Clear Output"] -pub type Ptco21R = crate::BitReader; -impl Ptco21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco21 { - match self.bits { - false => Ptco21::Ptco0, - true => Ptco21::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco21::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco21::Ptco1 - } -} -#[doc = "Field `PTCO21` writer - Port Clear Output"] -pub type Ptco21W<'a, REG> = crate::BitWriter<'a, REG, Ptco21>; -impl<'a, REG> Ptco21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco21::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco21::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco22 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO22` reader - Port Clear Output"] -pub type Ptco22R = crate::BitReader; -impl Ptco22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco22 { - match self.bits { - false => Ptco22::Ptco0, - true => Ptco22::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco22::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco22::Ptco1 - } -} -#[doc = "Field `PTCO22` writer - Port Clear Output"] -pub type Ptco22W<'a, REG> = crate::BitWriter<'a, REG, Ptco22>; -impl<'a, REG> Ptco22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco22::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco22::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco23 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO23` reader - Port Clear Output"] -pub type Ptco23R = crate::BitReader; -impl Ptco23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco23 { - match self.bits { - false => Ptco23::Ptco0, - true => Ptco23::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco23::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco23::Ptco1 - } -} -#[doc = "Field `PTCO23` writer - Port Clear Output"] -pub type Ptco23W<'a, REG> = crate::BitWriter<'a, REG, Ptco23>; -impl<'a, REG> Ptco23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco23::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco23::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco24 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO24` reader - Port Clear Output"] -pub type Ptco24R = crate::BitReader; -impl Ptco24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco24 { - match self.bits { - false => Ptco24::Ptco0, - true => Ptco24::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco24::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco24::Ptco1 - } -} -#[doc = "Field `PTCO24` writer - Port Clear Output"] -pub type Ptco24W<'a, REG> = crate::BitWriter<'a, REG, Ptco24>; -impl<'a, REG> Ptco24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco24::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco24::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco25 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO25` reader - Port Clear Output"] -pub type Ptco25R = crate::BitReader; -impl Ptco25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco25 { - match self.bits { - false => Ptco25::Ptco0, - true => Ptco25::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco25::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco25::Ptco1 - } -} -#[doc = "Field `PTCO25` writer - Port Clear Output"] -pub type Ptco25W<'a, REG> = crate::BitWriter<'a, REG, Ptco25>; -impl<'a, REG> Ptco25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco25::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco25::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco26 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO26` reader - Port Clear Output"] -pub type Ptco26R = crate::BitReader; -impl Ptco26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco26 { - match self.bits { - false => Ptco26::Ptco0, - true => Ptco26::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco26::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco26::Ptco1 - } -} -#[doc = "Field `PTCO26` writer - Port Clear Output"] -pub type Ptco26W<'a, REG> = crate::BitWriter<'a, REG, Ptco26>; -impl<'a, REG> Ptco26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco26::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco26::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco27 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO27` reader - Port Clear Output"] -pub type Ptco27R = crate::BitReader; -impl Ptco27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco27 { - match self.bits { - false => Ptco27::Ptco0, - true => Ptco27::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco27::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco27::Ptco1 - } -} -#[doc = "Field `PTCO27` writer - Port Clear Output"] -pub type Ptco27W<'a, REG> = crate::BitWriter<'a, REG, Ptco27>; -impl<'a, REG> Ptco27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco27::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco27::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco28 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO28` reader - Port Clear Output"] -pub type Ptco28R = crate::BitReader; -impl Ptco28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco28 { - match self.bits { - false => Ptco28::Ptco0, - true => Ptco28::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco28::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco28::Ptco1 - } -} -#[doc = "Field `PTCO28` writer - Port Clear Output"] -pub type Ptco28W<'a, REG> = crate::BitWriter<'a, REG, Ptco28>; -impl<'a, REG> Ptco28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco28::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco28::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco29 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO29` reader - Port Clear Output"] -pub type Ptco29R = crate::BitReader; -impl Ptco29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco29 { - match self.bits { - false => Ptco29::Ptco0, - true => Ptco29::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco29::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco29::Ptco1 - } -} -#[doc = "Field `PTCO29` writer - Port Clear Output"] -pub type Ptco29W<'a, REG> = crate::BitWriter<'a, REG, Ptco29>; -impl<'a, REG> Ptco29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco29::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco29::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco30 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO30` reader - Port Clear Output"] -pub type Ptco30R = crate::BitReader; -impl Ptco30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco30 { - match self.bits { - false => Ptco30::Ptco0, - true => Ptco30::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco30::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco30::Ptco1 - } -} -#[doc = "Field `PTCO30` writer - Port Clear Output"] -pub type Ptco30W<'a, REG> = crate::BitWriter<'a, REG, Ptco30>; -impl<'a, REG> Ptco30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco30::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco30::Ptco1) - } -} -#[doc = "Port Clear Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptco31 { - #[doc = "0: No change"] - Ptco0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 0"] - Ptco1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptco31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTCO31` reader - Port Clear Output"] -pub type Ptco31R = crate::BitReader; -impl Ptco31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptco31 { - match self.bits { - false => Ptco31::Ptco0, - true => Ptco31::Ptco1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptco0(&self) -> bool { - *self == Ptco31::Ptco0 - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn is_ptco1(&self) -> bool { - *self == Ptco31::Ptco1 - } -} -#[doc = "Field `PTCO31` writer - Port Clear Output"] -pub type Ptco31W<'a, REG> = crate::BitWriter<'a, REG, Ptco31>; -impl<'a, REG> Ptco31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptco0(self) -> &'a mut crate::W { - self.variant(Ptco31::Ptco0) - } - #[doc = "Corresponding field in PDOR becomes 0"] - #[inline(always)] - pub fn ptco1(self) -> &'a mut crate::W { - self.variant(Ptco31::Ptco1) - } -} -impl R { - #[doc = "Bit 0 - Port Clear Output"] - #[inline(always)] - pub fn ptco0(&self) -> Ptco0R { - Ptco0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Port Clear Output"] - #[inline(always)] - pub fn ptco1(&self) -> Ptco1R { - Ptco1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Port Clear Output"] - #[inline(always)] - pub fn ptco2(&self) -> Ptco2R { - Ptco2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Port Clear Output"] - #[inline(always)] - pub fn ptco3(&self) -> Ptco3R { - Ptco3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Port Clear Output"] - #[inline(always)] - pub fn ptco4(&self) -> Ptco4R { - Ptco4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Port Clear Output"] - #[inline(always)] - pub fn ptco5(&self) -> Ptco5R { - Ptco5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Port Clear Output"] - #[inline(always)] - pub fn ptco6(&self) -> Ptco6R { - Ptco6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Port Clear Output"] - #[inline(always)] - pub fn ptco7(&self) -> Ptco7R { - Ptco7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Port Clear Output"] - #[inline(always)] - pub fn ptco8(&self) -> Ptco8R { - Ptco8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Port Clear Output"] - #[inline(always)] - pub fn ptco9(&self) -> Ptco9R { - Ptco9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Port Clear Output"] - #[inline(always)] - pub fn ptco10(&self) -> Ptco10R { - Ptco10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Port Clear Output"] - #[inline(always)] - pub fn ptco11(&self) -> Ptco11R { - Ptco11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Port Clear Output"] - #[inline(always)] - pub fn ptco12(&self) -> Ptco12R { - Ptco12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Port Clear Output"] - #[inline(always)] - pub fn ptco13(&self) -> Ptco13R { - Ptco13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Port Clear Output"] - #[inline(always)] - pub fn ptco14(&self) -> Ptco14R { - Ptco14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Port Clear Output"] - #[inline(always)] - pub fn ptco15(&self) -> Ptco15R { - Ptco15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Port Clear Output"] - #[inline(always)] - pub fn ptco16(&self) -> Ptco16R { - Ptco16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Port Clear Output"] - #[inline(always)] - pub fn ptco17(&self) -> Ptco17R { - Ptco17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Port Clear Output"] - #[inline(always)] - pub fn ptco18(&self) -> Ptco18R { - Ptco18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Port Clear Output"] - #[inline(always)] - pub fn ptco19(&self) -> Ptco19R { - Ptco19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Port Clear Output"] - #[inline(always)] - pub fn ptco20(&self) -> Ptco20R { - Ptco20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Port Clear Output"] - #[inline(always)] - pub fn ptco21(&self) -> Ptco21R { - Ptco21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Port Clear Output"] - #[inline(always)] - pub fn ptco22(&self) -> Ptco22R { - Ptco22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Port Clear Output"] - #[inline(always)] - pub fn ptco23(&self) -> Ptco23R { - Ptco23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Port Clear Output"] - #[inline(always)] - pub fn ptco24(&self) -> Ptco24R { - Ptco24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Port Clear Output"] - #[inline(always)] - pub fn ptco25(&self) -> Ptco25R { - Ptco25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Port Clear Output"] - #[inline(always)] - pub fn ptco26(&self) -> Ptco26R { - Ptco26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Port Clear Output"] - #[inline(always)] - pub fn ptco27(&self) -> Ptco27R { - Ptco27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Port Clear Output"] - #[inline(always)] - pub fn ptco28(&self) -> Ptco28R { - Ptco28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Port Clear Output"] - #[inline(always)] - pub fn ptco29(&self) -> Ptco29R { - Ptco29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Port Clear Output"] - #[inline(always)] - pub fn ptco30(&self) -> Ptco30R { - Ptco30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Port Clear Output"] - #[inline(always)] - pub fn ptco31(&self) -> Ptco31R { - Ptco31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Clear Output"] - #[inline(always)] - pub fn ptco0(&mut self) -> Ptco0W { - Ptco0W::new(self, 0) - } - #[doc = "Bit 1 - Port Clear Output"] - #[inline(always)] - pub fn ptco1(&mut self) -> Ptco1W { - Ptco1W::new(self, 1) - } - #[doc = "Bit 2 - Port Clear Output"] - #[inline(always)] - pub fn ptco2(&mut self) -> Ptco2W { - Ptco2W::new(self, 2) - } - #[doc = "Bit 3 - Port Clear Output"] - #[inline(always)] - pub fn ptco3(&mut self) -> Ptco3W { - Ptco3W::new(self, 3) - } - #[doc = "Bit 4 - Port Clear Output"] - #[inline(always)] - pub fn ptco4(&mut self) -> Ptco4W { - Ptco4W::new(self, 4) - } - #[doc = "Bit 5 - Port Clear Output"] - #[inline(always)] - pub fn ptco5(&mut self) -> Ptco5W { - Ptco5W::new(self, 5) - } - #[doc = "Bit 6 - Port Clear Output"] - #[inline(always)] - pub fn ptco6(&mut self) -> Ptco6W { - Ptco6W::new(self, 6) - } - #[doc = "Bit 7 - Port Clear Output"] - #[inline(always)] - pub fn ptco7(&mut self) -> Ptco7W { - Ptco7W::new(self, 7) - } - #[doc = "Bit 8 - Port Clear Output"] - #[inline(always)] - pub fn ptco8(&mut self) -> Ptco8W { - Ptco8W::new(self, 8) - } - #[doc = "Bit 9 - Port Clear Output"] - #[inline(always)] - pub fn ptco9(&mut self) -> Ptco9W { - Ptco9W::new(self, 9) - } - #[doc = "Bit 10 - Port Clear Output"] - #[inline(always)] - pub fn ptco10(&mut self) -> Ptco10W { - Ptco10W::new(self, 10) - } - #[doc = "Bit 11 - Port Clear Output"] - #[inline(always)] - pub fn ptco11(&mut self) -> Ptco11W { - Ptco11W::new(self, 11) - } - #[doc = "Bit 12 - Port Clear Output"] - #[inline(always)] - pub fn ptco12(&mut self) -> Ptco12W { - Ptco12W::new(self, 12) - } - #[doc = "Bit 13 - Port Clear Output"] - #[inline(always)] - pub fn ptco13(&mut self) -> Ptco13W { - Ptco13W::new(self, 13) - } - #[doc = "Bit 14 - Port Clear Output"] - #[inline(always)] - pub fn ptco14(&mut self) -> Ptco14W { - Ptco14W::new(self, 14) - } - #[doc = "Bit 15 - Port Clear Output"] - #[inline(always)] - pub fn ptco15(&mut self) -> Ptco15W { - Ptco15W::new(self, 15) - } - #[doc = "Bit 16 - Port Clear Output"] - #[inline(always)] - pub fn ptco16(&mut self) -> Ptco16W { - Ptco16W::new(self, 16) - } - #[doc = "Bit 17 - Port Clear Output"] - #[inline(always)] - pub fn ptco17(&mut self) -> Ptco17W { - Ptco17W::new(self, 17) - } - #[doc = "Bit 18 - Port Clear Output"] - #[inline(always)] - pub fn ptco18(&mut self) -> Ptco18W { - Ptco18W::new(self, 18) - } - #[doc = "Bit 19 - Port Clear Output"] - #[inline(always)] - pub fn ptco19(&mut self) -> Ptco19W { - Ptco19W::new(self, 19) - } - #[doc = "Bit 20 - Port Clear Output"] - #[inline(always)] - pub fn ptco20(&mut self) -> Ptco20W { - Ptco20W::new(self, 20) - } - #[doc = "Bit 21 - Port Clear Output"] - #[inline(always)] - pub fn ptco21(&mut self) -> Ptco21W { - Ptco21W::new(self, 21) - } - #[doc = "Bit 22 - Port Clear Output"] - #[inline(always)] - pub fn ptco22(&mut self) -> Ptco22W { - Ptco22W::new(self, 22) - } - #[doc = "Bit 23 - Port Clear Output"] - #[inline(always)] - pub fn ptco23(&mut self) -> Ptco23W { - Ptco23W::new(self, 23) - } - #[doc = "Bit 24 - Port Clear Output"] - #[inline(always)] - pub fn ptco24(&mut self) -> Ptco24W { - Ptco24W::new(self, 24) - } - #[doc = "Bit 25 - Port Clear Output"] - #[inline(always)] - pub fn ptco25(&mut self) -> Ptco25W { - Ptco25W::new(self, 25) - } - #[doc = "Bit 26 - Port Clear Output"] - #[inline(always)] - pub fn ptco26(&mut self) -> Ptco26W { - Ptco26W::new(self, 26) - } - #[doc = "Bit 27 - Port Clear Output"] - #[inline(always)] - pub fn ptco27(&mut self) -> Ptco27W { - Ptco27W::new(self, 27) - } - #[doc = "Bit 28 - Port Clear Output"] - #[inline(always)] - pub fn ptco28(&mut self) -> Ptco28W { - Ptco28W::new(self, 28) - } - #[doc = "Bit 29 - Port Clear Output"] - #[inline(always)] - pub fn ptco29(&mut self) -> Ptco29W { - Ptco29W::new(self, 29) - } - #[doc = "Bit 30 - Port Clear Output"] - #[inline(always)] - pub fn ptco30(&mut self) -> Ptco30W { - Ptco30W::new(self, 30) - } - #[doc = "Bit 31 - Port Clear Output"] - #[inline(always)] - pub fn ptco31(&mut self) -> Ptco31W { - Ptco31W::new(self, 31) - } -} -#[doc = "Port Clear Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pcor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PcorSpec; -impl crate::RegisterSpec for PcorSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcor::R`](R) reader structure"] -impl crate::Readable for PcorSpec {} -#[doc = "`write(|w| ..)` method takes [`pcor::W`](W) writer structure"] -impl crate::Writable for PcorSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCOR to value 0"] -impl crate::Resettable for PcorSpec {} diff --git a/mcxa276-pac/src/gpio0/pddr.rs b/mcxa276-pac/src/gpio0/pddr.rs deleted file mode 100644 index 66008cdc6..000000000 --- a/mcxa276-pac/src/gpio0/pddr.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `PDDR` reader"] -pub type R = crate::R; -#[doc = "Register `PDDR` writer"] -pub type W = crate::W; -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd0 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD0` reader - Port Data Direction"] -pub type Pdd0R = crate::BitReader; -impl Pdd0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd0 { - match self.bits { - false => Pdd0::Pdd0, - true => Pdd0::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd0::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd0::Pdd1 - } -} -#[doc = "Field `PDD0` writer - Port Data Direction"] -pub type Pdd0W<'a, REG> = crate::BitWriter<'a, REG, Pdd0>; -impl<'a, REG> Pdd0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd0::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd0::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd1 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD1` reader - Port Data Direction"] -pub type Pdd1R = crate::BitReader; -impl Pdd1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd1 { - match self.bits { - false => Pdd1::Pdd0, - true => Pdd1::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd1::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd1::Pdd1 - } -} -#[doc = "Field `PDD1` writer - Port Data Direction"] -pub type Pdd1W<'a, REG> = crate::BitWriter<'a, REG, Pdd1>; -impl<'a, REG> Pdd1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd1::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd1::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd2 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD2` reader - Port Data Direction"] -pub type Pdd2R = crate::BitReader; -impl Pdd2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd2 { - match self.bits { - false => Pdd2::Pdd0, - true => Pdd2::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd2::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd2::Pdd1 - } -} -#[doc = "Field `PDD2` writer - Port Data Direction"] -pub type Pdd2W<'a, REG> = crate::BitWriter<'a, REG, Pdd2>; -impl<'a, REG> Pdd2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd2::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd2::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd3 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD3` reader - Port Data Direction"] -pub type Pdd3R = crate::BitReader; -impl Pdd3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd3 { - match self.bits { - false => Pdd3::Pdd0, - true => Pdd3::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd3::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd3::Pdd1 - } -} -#[doc = "Field `PDD3` writer - Port Data Direction"] -pub type Pdd3W<'a, REG> = crate::BitWriter<'a, REG, Pdd3>; -impl<'a, REG> Pdd3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd3::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd3::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd4 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD4` reader - Port Data Direction"] -pub type Pdd4R = crate::BitReader; -impl Pdd4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd4 { - match self.bits { - false => Pdd4::Pdd0, - true => Pdd4::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd4::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd4::Pdd1 - } -} -#[doc = "Field `PDD4` writer - Port Data Direction"] -pub type Pdd4W<'a, REG> = crate::BitWriter<'a, REG, Pdd4>; -impl<'a, REG> Pdd4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd4::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd4::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd5 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD5` reader - Port Data Direction"] -pub type Pdd5R = crate::BitReader; -impl Pdd5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd5 { - match self.bits { - false => Pdd5::Pdd0, - true => Pdd5::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd5::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd5::Pdd1 - } -} -#[doc = "Field `PDD5` writer - Port Data Direction"] -pub type Pdd5W<'a, REG> = crate::BitWriter<'a, REG, Pdd5>; -impl<'a, REG> Pdd5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd5::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd5::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd6 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD6` reader - Port Data Direction"] -pub type Pdd6R = crate::BitReader; -impl Pdd6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd6 { - match self.bits { - false => Pdd6::Pdd0, - true => Pdd6::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd6::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd6::Pdd1 - } -} -#[doc = "Field `PDD6` writer - Port Data Direction"] -pub type Pdd6W<'a, REG> = crate::BitWriter<'a, REG, Pdd6>; -impl<'a, REG> Pdd6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd6::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd6::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd7 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD7` reader - Port Data Direction"] -pub type Pdd7R = crate::BitReader; -impl Pdd7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd7 { - match self.bits { - false => Pdd7::Pdd0, - true => Pdd7::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd7::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd7::Pdd1 - } -} -#[doc = "Field `PDD7` writer - Port Data Direction"] -pub type Pdd7W<'a, REG> = crate::BitWriter<'a, REG, Pdd7>; -impl<'a, REG> Pdd7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd7::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd7::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd8 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD8` reader - Port Data Direction"] -pub type Pdd8R = crate::BitReader; -impl Pdd8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd8 { - match self.bits { - false => Pdd8::Pdd0, - true => Pdd8::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd8::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd8::Pdd1 - } -} -#[doc = "Field `PDD8` writer - Port Data Direction"] -pub type Pdd8W<'a, REG> = crate::BitWriter<'a, REG, Pdd8>; -impl<'a, REG> Pdd8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd8::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd8::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd9 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD9` reader - Port Data Direction"] -pub type Pdd9R = crate::BitReader; -impl Pdd9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd9 { - match self.bits { - false => Pdd9::Pdd0, - true => Pdd9::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd9::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd9::Pdd1 - } -} -#[doc = "Field `PDD9` writer - Port Data Direction"] -pub type Pdd9W<'a, REG> = crate::BitWriter<'a, REG, Pdd9>; -impl<'a, REG> Pdd9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd9::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd9::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd10 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD10` reader - Port Data Direction"] -pub type Pdd10R = crate::BitReader; -impl Pdd10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd10 { - match self.bits { - false => Pdd10::Pdd0, - true => Pdd10::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd10::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd10::Pdd1 - } -} -#[doc = "Field `PDD10` writer - Port Data Direction"] -pub type Pdd10W<'a, REG> = crate::BitWriter<'a, REG, Pdd10>; -impl<'a, REG> Pdd10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd10::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd10::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd11 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD11` reader - Port Data Direction"] -pub type Pdd11R = crate::BitReader; -impl Pdd11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd11 { - match self.bits { - false => Pdd11::Pdd0, - true => Pdd11::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd11::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd11::Pdd1 - } -} -#[doc = "Field `PDD11` writer - Port Data Direction"] -pub type Pdd11W<'a, REG> = crate::BitWriter<'a, REG, Pdd11>; -impl<'a, REG> Pdd11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd11::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd11::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd12 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD12` reader - Port Data Direction"] -pub type Pdd12R = crate::BitReader; -impl Pdd12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd12 { - match self.bits { - false => Pdd12::Pdd0, - true => Pdd12::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd12::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd12::Pdd1 - } -} -#[doc = "Field `PDD12` writer - Port Data Direction"] -pub type Pdd12W<'a, REG> = crate::BitWriter<'a, REG, Pdd12>; -impl<'a, REG> Pdd12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd12::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd12::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd13 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD13` reader - Port Data Direction"] -pub type Pdd13R = crate::BitReader; -impl Pdd13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd13 { - match self.bits { - false => Pdd13::Pdd0, - true => Pdd13::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd13::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd13::Pdd1 - } -} -#[doc = "Field `PDD13` writer - Port Data Direction"] -pub type Pdd13W<'a, REG> = crate::BitWriter<'a, REG, Pdd13>; -impl<'a, REG> Pdd13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd13::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd13::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd14 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD14` reader - Port Data Direction"] -pub type Pdd14R = crate::BitReader; -impl Pdd14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd14 { - match self.bits { - false => Pdd14::Pdd0, - true => Pdd14::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd14::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd14::Pdd1 - } -} -#[doc = "Field `PDD14` writer - Port Data Direction"] -pub type Pdd14W<'a, REG> = crate::BitWriter<'a, REG, Pdd14>; -impl<'a, REG> Pdd14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd14::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd14::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd15 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD15` reader - Port Data Direction"] -pub type Pdd15R = crate::BitReader; -impl Pdd15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd15 { - match self.bits { - false => Pdd15::Pdd0, - true => Pdd15::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd15::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd15::Pdd1 - } -} -#[doc = "Field `PDD15` writer - Port Data Direction"] -pub type Pdd15W<'a, REG> = crate::BitWriter<'a, REG, Pdd15>; -impl<'a, REG> Pdd15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd15::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd15::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd16 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD16` reader - Port Data Direction"] -pub type Pdd16R = crate::BitReader; -impl Pdd16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd16 { - match self.bits { - false => Pdd16::Pdd0, - true => Pdd16::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd16::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd16::Pdd1 - } -} -#[doc = "Field `PDD16` writer - Port Data Direction"] -pub type Pdd16W<'a, REG> = crate::BitWriter<'a, REG, Pdd16>; -impl<'a, REG> Pdd16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd16::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd16::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd17 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD17` reader - Port Data Direction"] -pub type Pdd17R = crate::BitReader; -impl Pdd17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd17 { - match self.bits { - false => Pdd17::Pdd0, - true => Pdd17::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd17::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd17::Pdd1 - } -} -#[doc = "Field `PDD17` writer - Port Data Direction"] -pub type Pdd17W<'a, REG> = crate::BitWriter<'a, REG, Pdd17>; -impl<'a, REG> Pdd17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd17::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd17::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd18 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD18` reader - Port Data Direction"] -pub type Pdd18R = crate::BitReader; -impl Pdd18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd18 { - match self.bits { - false => Pdd18::Pdd0, - true => Pdd18::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd18::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd18::Pdd1 - } -} -#[doc = "Field `PDD18` writer - Port Data Direction"] -pub type Pdd18W<'a, REG> = crate::BitWriter<'a, REG, Pdd18>; -impl<'a, REG> Pdd18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd18::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd18::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd19 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD19` reader - Port Data Direction"] -pub type Pdd19R = crate::BitReader; -impl Pdd19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd19 { - match self.bits { - false => Pdd19::Pdd0, - true => Pdd19::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd19::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd19::Pdd1 - } -} -#[doc = "Field `PDD19` writer - Port Data Direction"] -pub type Pdd19W<'a, REG> = crate::BitWriter<'a, REG, Pdd19>; -impl<'a, REG> Pdd19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd19::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd19::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd20 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD20` reader - Port Data Direction"] -pub type Pdd20R = crate::BitReader; -impl Pdd20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd20 { - match self.bits { - false => Pdd20::Pdd0, - true => Pdd20::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd20::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd20::Pdd1 - } -} -#[doc = "Field `PDD20` writer - Port Data Direction"] -pub type Pdd20W<'a, REG> = crate::BitWriter<'a, REG, Pdd20>; -impl<'a, REG> Pdd20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd20::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd20::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd21 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD21` reader - Port Data Direction"] -pub type Pdd21R = crate::BitReader; -impl Pdd21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd21 { - match self.bits { - false => Pdd21::Pdd0, - true => Pdd21::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd21::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd21::Pdd1 - } -} -#[doc = "Field `PDD21` writer - Port Data Direction"] -pub type Pdd21W<'a, REG> = crate::BitWriter<'a, REG, Pdd21>; -impl<'a, REG> Pdd21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd21::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd21::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd22 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD22` reader - Port Data Direction"] -pub type Pdd22R = crate::BitReader; -impl Pdd22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd22 { - match self.bits { - false => Pdd22::Pdd0, - true => Pdd22::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd22::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd22::Pdd1 - } -} -#[doc = "Field `PDD22` writer - Port Data Direction"] -pub type Pdd22W<'a, REG> = crate::BitWriter<'a, REG, Pdd22>; -impl<'a, REG> Pdd22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd22::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd22::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd23 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD23` reader - Port Data Direction"] -pub type Pdd23R = crate::BitReader; -impl Pdd23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd23 { - match self.bits { - false => Pdd23::Pdd0, - true => Pdd23::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd23::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd23::Pdd1 - } -} -#[doc = "Field `PDD23` writer - Port Data Direction"] -pub type Pdd23W<'a, REG> = crate::BitWriter<'a, REG, Pdd23>; -impl<'a, REG> Pdd23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd23::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd23::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd24 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD24` reader - Port Data Direction"] -pub type Pdd24R = crate::BitReader; -impl Pdd24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd24 { - match self.bits { - false => Pdd24::Pdd0, - true => Pdd24::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd24::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd24::Pdd1 - } -} -#[doc = "Field `PDD24` writer - Port Data Direction"] -pub type Pdd24W<'a, REG> = crate::BitWriter<'a, REG, Pdd24>; -impl<'a, REG> Pdd24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd24::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd24::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd25 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD25` reader - Port Data Direction"] -pub type Pdd25R = crate::BitReader; -impl Pdd25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd25 { - match self.bits { - false => Pdd25::Pdd0, - true => Pdd25::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd25::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd25::Pdd1 - } -} -#[doc = "Field `PDD25` writer - Port Data Direction"] -pub type Pdd25W<'a, REG> = crate::BitWriter<'a, REG, Pdd25>; -impl<'a, REG> Pdd25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd25::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd25::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd26 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD26` reader - Port Data Direction"] -pub type Pdd26R = crate::BitReader; -impl Pdd26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd26 { - match self.bits { - false => Pdd26::Pdd0, - true => Pdd26::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd26::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd26::Pdd1 - } -} -#[doc = "Field `PDD26` writer - Port Data Direction"] -pub type Pdd26W<'a, REG> = crate::BitWriter<'a, REG, Pdd26>; -impl<'a, REG> Pdd26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd26::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd26::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd27 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD27` reader - Port Data Direction"] -pub type Pdd27R = crate::BitReader; -impl Pdd27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd27 { - match self.bits { - false => Pdd27::Pdd0, - true => Pdd27::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd27::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd27::Pdd1 - } -} -#[doc = "Field `PDD27` writer - Port Data Direction"] -pub type Pdd27W<'a, REG> = crate::BitWriter<'a, REG, Pdd27>; -impl<'a, REG> Pdd27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd27::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd27::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd28 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD28` reader - Port Data Direction"] -pub type Pdd28R = crate::BitReader; -impl Pdd28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd28 { - match self.bits { - false => Pdd28::Pdd0, - true => Pdd28::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd28::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd28::Pdd1 - } -} -#[doc = "Field `PDD28` writer - Port Data Direction"] -pub type Pdd28W<'a, REG> = crate::BitWriter<'a, REG, Pdd28>; -impl<'a, REG> Pdd28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd28::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd28::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd29 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD29` reader - Port Data Direction"] -pub type Pdd29R = crate::BitReader; -impl Pdd29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd29 { - match self.bits { - false => Pdd29::Pdd0, - true => Pdd29::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd29::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd29::Pdd1 - } -} -#[doc = "Field `PDD29` writer - Port Data Direction"] -pub type Pdd29W<'a, REG> = crate::BitWriter<'a, REG, Pdd29>; -impl<'a, REG> Pdd29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd29::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd29::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd30 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD30` reader - Port Data Direction"] -pub type Pdd30R = crate::BitReader; -impl Pdd30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd30 { - match self.bits { - false => Pdd30::Pdd0, - true => Pdd30::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd30::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd30::Pdd1 - } -} -#[doc = "Field `PDD30` writer - Port Data Direction"] -pub type Pdd30W<'a, REG> = crate::BitWriter<'a, REG, Pdd30>; -impl<'a, REG> Pdd30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd30::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd30::Pdd1) - } -} -#[doc = "Port Data Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdd31 { - #[doc = "0: Input"] - Pdd0 = 0, - #[doc = "1: Output"] - Pdd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdd31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDD31` reader - Port Data Direction"] -pub type Pdd31R = crate::BitReader; -impl Pdd31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdd31 { - match self.bits { - false => Pdd31::Pdd0, - true => Pdd31::Pdd1, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_pdd0(&self) -> bool { - *self == Pdd31::Pdd0 - } - #[doc = "Output"] - #[inline(always)] - pub fn is_pdd1(&self) -> bool { - *self == Pdd31::Pdd1 - } -} -#[doc = "Field `PDD31` writer - Port Data Direction"] -pub type Pdd31W<'a, REG> = crate::BitWriter<'a, REG, Pdd31>; -impl<'a, REG> Pdd31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn pdd0(self) -> &'a mut crate::W { - self.variant(Pdd31::Pdd0) - } - #[doc = "Output"] - #[inline(always)] - pub fn pdd1(self) -> &'a mut crate::W { - self.variant(Pdd31::Pdd1) - } -} -impl R { - #[doc = "Bit 0 - Port Data Direction"] - #[inline(always)] - pub fn pdd0(&self) -> Pdd0R { - Pdd0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Port Data Direction"] - #[inline(always)] - pub fn pdd1(&self) -> Pdd1R { - Pdd1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Port Data Direction"] - #[inline(always)] - pub fn pdd2(&self) -> Pdd2R { - Pdd2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Port Data Direction"] - #[inline(always)] - pub fn pdd3(&self) -> Pdd3R { - Pdd3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Port Data Direction"] - #[inline(always)] - pub fn pdd4(&self) -> Pdd4R { - Pdd4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Port Data Direction"] - #[inline(always)] - pub fn pdd5(&self) -> Pdd5R { - Pdd5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Port Data Direction"] - #[inline(always)] - pub fn pdd6(&self) -> Pdd6R { - Pdd6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Port Data Direction"] - #[inline(always)] - pub fn pdd7(&self) -> Pdd7R { - Pdd7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Port Data Direction"] - #[inline(always)] - pub fn pdd8(&self) -> Pdd8R { - Pdd8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Port Data Direction"] - #[inline(always)] - pub fn pdd9(&self) -> Pdd9R { - Pdd9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Port Data Direction"] - #[inline(always)] - pub fn pdd10(&self) -> Pdd10R { - Pdd10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Port Data Direction"] - #[inline(always)] - pub fn pdd11(&self) -> Pdd11R { - Pdd11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Port Data Direction"] - #[inline(always)] - pub fn pdd12(&self) -> Pdd12R { - Pdd12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Port Data Direction"] - #[inline(always)] - pub fn pdd13(&self) -> Pdd13R { - Pdd13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Port Data Direction"] - #[inline(always)] - pub fn pdd14(&self) -> Pdd14R { - Pdd14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Port Data Direction"] - #[inline(always)] - pub fn pdd15(&self) -> Pdd15R { - Pdd15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Port Data Direction"] - #[inline(always)] - pub fn pdd16(&self) -> Pdd16R { - Pdd16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Port Data Direction"] - #[inline(always)] - pub fn pdd17(&self) -> Pdd17R { - Pdd17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Port Data Direction"] - #[inline(always)] - pub fn pdd18(&self) -> Pdd18R { - Pdd18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Port Data Direction"] - #[inline(always)] - pub fn pdd19(&self) -> Pdd19R { - Pdd19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Port Data Direction"] - #[inline(always)] - pub fn pdd20(&self) -> Pdd20R { - Pdd20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Port Data Direction"] - #[inline(always)] - pub fn pdd21(&self) -> Pdd21R { - Pdd21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Port Data Direction"] - #[inline(always)] - pub fn pdd22(&self) -> Pdd22R { - Pdd22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Port Data Direction"] - #[inline(always)] - pub fn pdd23(&self) -> Pdd23R { - Pdd23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Port Data Direction"] - #[inline(always)] - pub fn pdd24(&self) -> Pdd24R { - Pdd24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Port Data Direction"] - #[inline(always)] - pub fn pdd25(&self) -> Pdd25R { - Pdd25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Port Data Direction"] - #[inline(always)] - pub fn pdd26(&self) -> Pdd26R { - Pdd26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Port Data Direction"] - #[inline(always)] - pub fn pdd27(&self) -> Pdd27R { - Pdd27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Port Data Direction"] - #[inline(always)] - pub fn pdd28(&self) -> Pdd28R { - Pdd28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Port Data Direction"] - #[inline(always)] - pub fn pdd29(&self) -> Pdd29R { - Pdd29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Port Data Direction"] - #[inline(always)] - pub fn pdd30(&self) -> Pdd30R { - Pdd30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Port Data Direction"] - #[inline(always)] - pub fn pdd31(&self) -> Pdd31R { - Pdd31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Data Direction"] - #[inline(always)] - pub fn pdd0(&mut self) -> Pdd0W { - Pdd0W::new(self, 0) - } - #[doc = "Bit 1 - Port Data Direction"] - #[inline(always)] - pub fn pdd1(&mut self) -> Pdd1W { - Pdd1W::new(self, 1) - } - #[doc = "Bit 2 - Port Data Direction"] - #[inline(always)] - pub fn pdd2(&mut self) -> Pdd2W { - Pdd2W::new(self, 2) - } - #[doc = "Bit 3 - Port Data Direction"] - #[inline(always)] - pub fn pdd3(&mut self) -> Pdd3W { - Pdd3W::new(self, 3) - } - #[doc = "Bit 4 - Port Data Direction"] - #[inline(always)] - pub fn pdd4(&mut self) -> Pdd4W { - Pdd4W::new(self, 4) - } - #[doc = "Bit 5 - Port Data Direction"] - #[inline(always)] - pub fn pdd5(&mut self) -> Pdd5W { - Pdd5W::new(self, 5) - } - #[doc = "Bit 6 - Port Data Direction"] - #[inline(always)] - pub fn pdd6(&mut self) -> Pdd6W { - Pdd6W::new(self, 6) - } - #[doc = "Bit 7 - Port Data Direction"] - #[inline(always)] - pub fn pdd7(&mut self) -> Pdd7W { - Pdd7W::new(self, 7) - } - #[doc = "Bit 8 - Port Data Direction"] - #[inline(always)] - pub fn pdd8(&mut self) -> Pdd8W { - Pdd8W::new(self, 8) - } - #[doc = "Bit 9 - Port Data Direction"] - #[inline(always)] - pub fn pdd9(&mut self) -> Pdd9W { - Pdd9W::new(self, 9) - } - #[doc = "Bit 10 - Port Data Direction"] - #[inline(always)] - pub fn pdd10(&mut self) -> Pdd10W { - Pdd10W::new(self, 10) - } - #[doc = "Bit 11 - Port Data Direction"] - #[inline(always)] - pub fn pdd11(&mut self) -> Pdd11W { - Pdd11W::new(self, 11) - } - #[doc = "Bit 12 - Port Data Direction"] - #[inline(always)] - pub fn pdd12(&mut self) -> Pdd12W { - Pdd12W::new(self, 12) - } - #[doc = "Bit 13 - Port Data Direction"] - #[inline(always)] - pub fn pdd13(&mut self) -> Pdd13W { - Pdd13W::new(self, 13) - } - #[doc = "Bit 14 - Port Data Direction"] - #[inline(always)] - pub fn pdd14(&mut self) -> Pdd14W { - Pdd14W::new(self, 14) - } - #[doc = "Bit 15 - Port Data Direction"] - #[inline(always)] - pub fn pdd15(&mut self) -> Pdd15W { - Pdd15W::new(self, 15) - } - #[doc = "Bit 16 - Port Data Direction"] - #[inline(always)] - pub fn pdd16(&mut self) -> Pdd16W { - Pdd16W::new(self, 16) - } - #[doc = "Bit 17 - Port Data Direction"] - #[inline(always)] - pub fn pdd17(&mut self) -> Pdd17W { - Pdd17W::new(self, 17) - } - #[doc = "Bit 18 - Port Data Direction"] - #[inline(always)] - pub fn pdd18(&mut self) -> Pdd18W { - Pdd18W::new(self, 18) - } - #[doc = "Bit 19 - Port Data Direction"] - #[inline(always)] - pub fn pdd19(&mut self) -> Pdd19W { - Pdd19W::new(self, 19) - } - #[doc = "Bit 20 - Port Data Direction"] - #[inline(always)] - pub fn pdd20(&mut self) -> Pdd20W { - Pdd20W::new(self, 20) - } - #[doc = "Bit 21 - Port Data Direction"] - #[inline(always)] - pub fn pdd21(&mut self) -> Pdd21W { - Pdd21W::new(self, 21) - } - #[doc = "Bit 22 - Port Data Direction"] - #[inline(always)] - pub fn pdd22(&mut self) -> Pdd22W { - Pdd22W::new(self, 22) - } - #[doc = "Bit 23 - Port Data Direction"] - #[inline(always)] - pub fn pdd23(&mut self) -> Pdd23W { - Pdd23W::new(self, 23) - } - #[doc = "Bit 24 - Port Data Direction"] - #[inline(always)] - pub fn pdd24(&mut self) -> Pdd24W { - Pdd24W::new(self, 24) - } - #[doc = "Bit 25 - Port Data Direction"] - #[inline(always)] - pub fn pdd25(&mut self) -> Pdd25W { - Pdd25W::new(self, 25) - } - #[doc = "Bit 26 - Port Data Direction"] - #[inline(always)] - pub fn pdd26(&mut self) -> Pdd26W { - Pdd26W::new(self, 26) - } - #[doc = "Bit 27 - Port Data Direction"] - #[inline(always)] - pub fn pdd27(&mut self) -> Pdd27W { - Pdd27W::new(self, 27) - } - #[doc = "Bit 28 - Port Data Direction"] - #[inline(always)] - pub fn pdd28(&mut self) -> Pdd28W { - Pdd28W::new(self, 28) - } - #[doc = "Bit 29 - Port Data Direction"] - #[inline(always)] - pub fn pdd29(&mut self) -> Pdd29W { - Pdd29W::new(self, 29) - } - #[doc = "Bit 30 - Port Data Direction"] - #[inline(always)] - pub fn pdd30(&mut self) -> Pdd30W { - Pdd30W::new(self, 30) - } - #[doc = "Bit 31 - Port Data Direction"] - #[inline(always)] - pub fn pdd31(&mut self) -> Pdd31W { - Pdd31W::new(self, 31) - } -} -#[doc = "Port Data Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`pddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PddrSpec; -impl crate::RegisterSpec for PddrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pddr::R`](R) reader structure"] -impl crate::Readable for PddrSpec {} -#[doc = "`write(|w| ..)` method takes [`pddr::W`](W) writer structure"] -impl crate::Writable for PddrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PDDR to value 0"] -impl crate::Resettable for PddrSpec {} diff --git a/mcxa276-pac/src/gpio0/pdir.rs b/mcxa276-pac/src/gpio0/pdir.rs deleted file mode 100644 index 6064118c9..000000000 --- a/mcxa276-pac/src/gpio0/pdir.rs +++ /dev/null @@ -1,1325 +0,0 @@ -#[doc = "Register `PDIR` reader"] -pub type R = crate::R; -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi0 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI0` reader - Port Data Input"] -pub type Pdi0R = crate::BitReader; -impl Pdi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi0 { - match self.bits { - false => Pdi0::Pdi0, - true => Pdi0::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi0::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi0::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi1 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI1` reader - Port Data Input"] -pub type Pdi1R = crate::BitReader; -impl Pdi1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi1 { - match self.bits { - false => Pdi1::Pdi0, - true => Pdi1::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi1::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi1::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi2 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI2` reader - Port Data Input"] -pub type Pdi2R = crate::BitReader; -impl Pdi2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi2 { - match self.bits { - false => Pdi2::Pdi0, - true => Pdi2::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi2::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi2::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi3 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI3` reader - Port Data Input"] -pub type Pdi3R = crate::BitReader; -impl Pdi3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi3 { - match self.bits { - false => Pdi3::Pdi0, - true => Pdi3::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi3::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi3::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi4 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI4` reader - Port Data Input"] -pub type Pdi4R = crate::BitReader; -impl Pdi4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi4 { - match self.bits { - false => Pdi4::Pdi0, - true => Pdi4::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi4::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi4::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi5 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI5` reader - Port Data Input"] -pub type Pdi5R = crate::BitReader; -impl Pdi5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi5 { - match self.bits { - false => Pdi5::Pdi0, - true => Pdi5::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi5::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi5::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi6 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI6` reader - Port Data Input"] -pub type Pdi6R = crate::BitReader; -impl Pdi6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi6 { - match self.bits { - false => Pdi6::Pdi0, - true => Pdi6::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi6::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi6::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi7 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI7` reader - Port Data Input"] -pub type Pdi7R = crate::BitReader; -impl Pdi7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi7 { - match self.bits { - false => Pdi7::Pdi0, - true => Pdi7::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi7::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi7::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi8 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI8` reader - Port Data Input"] -pub type Pdi8R = crate::BitReader; -impl Pdi8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi8 { - match self.bits { - false => Pdi8::Pdi0, - true => Pdi8::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi8::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi8::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi9 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI9` reader - Port Data Input"] -pub type Pdi9R = crate::BitReader; -impl Pdi9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi9 { - match self.bits { - false => Pdi9::Pdi0, - true => Pdi9::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi9::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi9::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi10 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI10` reader - Port Data Input"] -pub type Pdi10R = crate::BitReader; -impl Pdi10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi10 { - match self.bits { - false => Pdi10::Pdi0, - true => Pdi10::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi10::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi10::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi11 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI11` reader - Port Data Input"] -pub type Pdi11R = crate::BitReader; -impl Pdi11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi11 { - match self.bits { - false => Pdi11::Pdi0, - true => Pdi11::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi11::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi11::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi12 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI12` reader - Port Data Input"] -pub type Pdi12R = crate::BitReader; -impl Pdi12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi12 { - match self.bits { - false => Pdi12::Pdi0, - true => Pdi12::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi12::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi12::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi13 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI13` reader - Port Data Input"] -pub type Pdi13R = crate::BitReader; -impl Pdi13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi13 { - match self.bits { - false => Pdi13::Pdi0, - true => Pdi13::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi13::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi13::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi14 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI14` reader - Port Data Input"] -pub type Pdi14R = crate::BitReader; -impl Pdi14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi14 { - match self.bits { - false => Pdi14::Pdi0, - true => Pdi14::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi14::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi14::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi15 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI15` reader - Port Data Input"] -pub type Pdi15R = crate::BitReader; -impl Pdi15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi15 { - match self.bits { - false => Pdi15::Pdi0, - true => Pdi15::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi15::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi15::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi16 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI16` reader - Port Data Input"] -pub type Pdi16R = crate::BitReader; -impl Pdi16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi16 { - match self.bits { - false => Pdi16::Pdi0, - true => Pdi16::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi16::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi16::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi17 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI17` reader - Port Data Input"] -pub type Pdi17R = crate::BitReader; -impl Pdi17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi17 { - match self.bits { - false => Pdi17::Pdi0, - true => Pdi17::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi17::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi17::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi18 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI18` reader - Port Data Input"] -pub type Pdi18R = crate::BitReader; -impl Pdi18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi18 { - match self.bits { - false => Pdi18::Pdi0, - true => Pdi18::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi18::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi18::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi19 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI19` reader - Port Data Input"] -pub type Pdi19R = crate::BitReader; -impl Pdi19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi19 { - match self.bits { - false => Pdi19::Pdi0, - true => Pdi19::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi19::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi19::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi20 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI20` reader - Port Data Input"] -pub type Pdi20R = crate::BitReader; -impl Pdi20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi20 { - match self.bits { - false => Pdi20::Pdi0, - true => Pdi20::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi20::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi20::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi21 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI21` reader - Port Data Input"] -pub type Pdi21R = crate::BitReader; -impl Pdi21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi21 { - match self.bits { - false => Pdi21::Pdi0, - true => Pdi21::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi21::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi21::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi22 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI22` reader - Port Data Input"] -pub type Pdi22R = crate::BitReader; -impl Pdi22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi22 { - match self.bits { - false => Pdi22::Pdi0, - true => Pdi22::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi22::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi22::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi23 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI23` reader - Port Data Input"] -pub type Pdi23R = crate::BitReader; -impl Pdi23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi23 { - match self.bits { - false => Pdi23::Pdi0, - true => Pdi23::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi23::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi23::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi24 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI24` reader - Port Data Input"] -pub type Pdi24R = crate::BitReader; -impl Pdi24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi24 { - match self.bits { - false => Pdi24::Pdi0, - true => Pdi24::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi24::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi24::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi25 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI25` reader - Port Data Input"] -pub type Pdi25R = crate::BitReader; -impl Pdi25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi25 { - match self.bits { - false => Pdi25::Pdi0, - true => Pdi25::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi25::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi25::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi26 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI26` reader - Port Data Input"] -pub type Pdi26R = crate::BitReader; -impl Pdi26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi26 { - match self.bits { - false => Pdi26::Pdi0, - true => Pdi26::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi26::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi26::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi27 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI27` reader - Port Data Input"] -pub type Pdi27R = crate::BitReader; -impl Pdi27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi27 { - match self.bits { - false => Pdi27::Pdi0, - true => Pdi27::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi27::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi27::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi28 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI28` reader - Port Data Input"] -pub type Pdi28R = crate::BitReader; -impl Pdi28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi28 { - match self.bits { - false => Pdi28::Pdi0, - true => Pdi28::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi28::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi28::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi29 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI29` reader - Port Data Input"] -pub type Pdi29R = crate::BitReader; -impl Pdi29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi29 { - match self.bits { - false => Pdi29::Pdi0, - true => Pdi29::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi29::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi29::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi30 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI30` reader - Port Data Input"] -pub type Pdi30R = crate::BitReader; -impl Pdi30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi30 { - match self.bits { - false => Pdi30::Pdi0, - true => Pdi30::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi30::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi30::Pdi1 - } -} -#[doc = "Port Data Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdi31 { - #[doc = "0: Logic 0"] - Pdi0 = 0, - #[doc = "1: Logic 1"] - Pdi1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdi31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDI31` reader - Port Data Input"] -pub type Pdi31R = crate::BitReader; -impl Pdi31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdi31 { - match self.bits { - false => Pdi31::Pdi0, - true => Pdi31::Pdi1, - } - } - #[doc = "Logic 0"] - #[inline(always)] - pub fn is_pdi0(&self) -> bool { - *self == Pdi31::Pdi0 - } - #[doc = "Logic 1"] - #[inline(always)] - pub fn is_pdi1(&self) -> bool { - *self == Pdi31::Pdi1 - } -} -impl R { - #[doc = "Bit 0 - Port Data Input"] - #[inline(always)] - pub fn pdi0(&self) -> Pdi0R { - Pdi0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Port Data Input"] - #[inline(always)] - pub fn pdi1(&self) -> Pdi1R { - Pdi1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Port Data Input"] - #[inline(always)] - pub fn pdi2(&self) -> Pdi2R { - Pdi2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Port Data Input"] - #[inline(always)] - pub fn pdi3(&self) -> Pdi3R { - Pdi3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Port Data Input"] - #[inline(always)] - pub fn pdi4(&self) -> Pdi4R { - Pdi4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Port Data Input"] - #[inline(always)] - pub fn pdi5(&self) -> Pdi5R { - Pdi5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Port Data Input"] - #[inline(always)] - pub fn pdi6(&self) -> Pdi6R { - Pdi6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Port Data Input"] - #[inline(always)] - pub fn pdi7(&self) -> Pdi7R { - Pdi7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Port Data Input"] - #[inline(always)] - pub fn pdi8(&self) -> Pdi8R { - Pdi8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Port Data Input"] - #[inline(always)] - pub fn pdi9(&self) -> Pdi9R { - Pdi9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Port Data Input"] - #[inline(always)] - pub fn pdi10(&self) -> Pdi10R { - Pdi10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Port Data Input"] - #[inline(always)] - pub fn pdi11(&self) -> Pdi11R { - Pdi11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Port Data Input"] - #[inline(always)] - pub fn pdi12(&self) -> Pdi12R { - Pdi12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Port Data Input"] - #[inline(always)] - pub fn pdi13(&self) -> Pdi13R { - Pdi13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Port Data Input"] - #[inline(always)] - pub fn pdi14(&self) -> Pdi14R { - Pdi14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Port Data Input"] - #[inline(always)] - pub fn pdi15(&self) -> Pdi15R { - Pdi15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Port Data Input"] - #[inline(always)] - pub fn pdi16(&self) -> Pdi16R { - Pdi16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Port Data Input"] - #[inline(always)] - pub fn pdi17(&self) -> Pdi17R { - Pdi17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Port Data Input"] - #[inline(always)] - pub fn pdi18(&self) -> Pdi18R { - Pdi18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Port Data Input"] - #[inline(always)] - pub fn pdi19(&self) -> Pdi19R { - Pdi19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Port Data Input"] - #[inline(always)] - pub fn pdi20(&self) -> Pdi20R { - Pdi20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Port Data Input"] - #[inline(always)] - pub fn pdi21(&self) -> Pdi21R { - Pdi21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Port Data Input"] - #[inline(always)] - pub fn pdi22(&self) -> Pdi22R { - Pdi22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Port Data Input"] - #[inline(always)] - pub fn pdi23(&self) -> Pdi23R { - Pdi23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Port Data Input"] - #[inline(always)] - pub fn pdi24(&self) -> Pdi24R { - Pdi24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Port Data Input"] - #[inline(always)] - pub fn pdi25(&self) -> Pdi25R { - Pdi25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Port Data Input"] - #[inline(always)] - pub fn pdi26(&self) -> Pdi26R { - Pdi26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Port Data Input"] - #[inline(always)] - pub fn pdi27(&self) -> Pdi27R { - Pdi27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Port Data Input"] - #[inline(always)] - pub fn pdi28(&self) -> Pdi28R { - Pdi28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Port Data Input"] - #[inline(always)] - pub fn pdi29(&self) -> Pdi29R { - Pdi29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Port Data Input"] - #[inline(always)] - pub fn pdi30(&self) -> Pdi30R { - Pdi30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Port Data Input"] - #[inline(always)] - pub fn pdi31(&self) -> Pdi31R { - Pdi31R::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "Port Data Input\n\nYou can [`read`](crate::Reg::read) this register and get [`pdir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PdirSpec; -impl crate::RegisterSpec for PdirSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pdir::R`](R) reader structure"] -impl crate::Readable for PdirSpec {} -#[doc = "`reset()` method sets PDIR to value 0"] -impl crate::Resettable for PdirSpec {} diff --git a/mcxa276-pac/src/gpio0/pdor.rs b/mcxa276-pac/src/gpio0/pdor.rs deleted file mode 100644 index c1aa0b516..000000000 --- a/mcxa276-pac/src/gpio0/pdor.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `PDOR` reader"] -pub type R = crate::R; -#[doc = "Register `PDOR` writer"] -pub type W = crate::W; -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo0 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO0` reader - Port Data Output"] -pub type Pdo0R = crate::BitReader; -impl Pdo0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo0 { - match self.bits { - false => Pdo0::Pdo0, - true => Pdo0::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo0::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo0::Pdo1 - } -} -#[doc = "Field `PDO0` writer - Port Data Output"] -pub type Pdo0W<'a, REG> = crate::BitWriter<'a, REG, Pdo0>; -impl<'a, REG> Pdo0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo0::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo0::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo1 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO1` reader - Port Data Output"] -pub type Pdo1R = crate::BitReader; -impl Pdo1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo1 { - match self.bits { - false => Pdo1::Pdo0, - true => Pdo1::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo1::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo1::Pdo1 - } -} -#[doc = "Field `PDO1` writer - Port Data Output"] -pub type Pdo1W<'a, REG> = crate::BitWriter<'a, REG, Pdo1>; -impl<'a, REG> Pdo1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo1::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo1::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo2 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO2` reader - Port Data Output"] -pub type Pdo2R = crate::BitReader; -impl Pdo2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo2 { - match self.bits { - false => Pdo2::Pdo0, - true => Pdo2::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo2::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo2::Pdo1 - } -} -#[doc = "Field `PDO2` writer - Port Data Output"] -pub type Pdo2W<'a, REG> = crate::BitWriter<'a, REG, Pdo2>; -impl<'a, REG> Pdo2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo2::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo2::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo3 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO3` reader - Port Data Output"] -pub type Pdo3R = crate::BitReader; -impl Pdo3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo3 { - match self.bits { - false => Pdo3::Pdo0, - true => Pdo3::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo3::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo3::Pdo1 - } -} -#[doc = "Field `PDO3` writer - Port Data Output"] -pub type Pdo3W<'a, REG> = crate::BitWriter<'a, REG, Pdo3>; -impl<'a, REG> Pdo3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo3::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo3::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo4 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO4` reader - Port Data Output"] -pub type Pdo4R = crate::BitReader; -impl Pdo4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo4 { - match self.bits { - false => Pdo4::Pdo0, - true => Pdo4::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo4::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo4::Pdo1 - } -} -#[doc = "Field `PDO4` writer - Port Data Output"] -pub type Pdo4W<'a, REG> = crate::BitWriter<'a, REG, Pdo4>; -impl<'a, REG> Pdo4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo4::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo4::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo5 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO5` reader - Port Data Output"] -pub type Pdo5R = crate::BitReader; -impl Pdo5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo5 { - match self.bits { - false => Pdo5::Pdo0, - true => Pdo5::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo5::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo5::Pdo1 - } -} -#[doc = "Field `PDO5` writer - Port Data Output"] -pub type Pdo5W<'a, REG> = crate::BitWriter<'a, REG, Pdo5>; -impl<'a, REG> Pdo5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo5::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo5::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo6 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO6` reader - Port Data Output"] -pub type Pdo6R = crate::BitReader; -impl Pdo6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo6 { - match self.bits { - false => Pdo6::Pdo0, - true => Pdo6::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo6::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo6::Pdo1 - } -} -#[doc = "Field `PDO6` writer - Port Data Output"] -pub type Pdo6W<'a, REG> = crate::BitWriter<'a, REG, Pdo6>; -impl<'a, REG> Pdo6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo6::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo6::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo7 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO7` reader - Port Data Output"] -pub type Pdo7R = crate::BitReader; -impl Pdo7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo7 { - match self.bits { - false => Pdo7::Pdo0, - true => Pdo7::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo7::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo7::Pdo1 - } -} -#[doc = "Field `PDO7` writer - Port Data Output"] -pub type Pdo7W<'a, REG> = crate::BitWriter<'a, REG, Pdo7>; -impl<'a, REG> Pdo7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo7::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo7::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo8 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO8` reader - Port Data Output"] -pub type Pdo8R = crate::BitReader; -impl Pdo8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo8 { - match self.bits { - false => Pdo8::Pdo0, - true => Pdo8::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo8::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo8::Pdo1 - } -} -#[doc = "Field `PDO8` writer - Port Data Output"] -pub type Pdo8W<'a, REG> = crate::BitWriter<'a, REG, Pdo8>; -impl<'a, REG> Pdo8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo8::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo8::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo9 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO9` reader - Port Data Output"] -pub type Pdo9R = crate::BitReader; -impl Pdo9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo9 { - match self.bits { - false => Pdo9::Pdo0, - true => Pdo9::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo9::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo9::Pdo1 - } -} -#[doc = "Field `PDO9` writer - Port Data Output"] -pub type Pdo9W<'a, REG> = crate::BitWriter<'a, REG, Pdo9>; -impl<'a, REG> Pdo9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo9::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo9::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo10 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO10` reader - Port Data Output"] -pub type Pdo10R = crate::BitReader; -impl Pdo10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo10 { - match self.bits { - false => Pdo10::Pdo0, - true => Pdo10::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo10::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo10::Pdo1 - } -} -#[doc = "Field `PDO10` writer - Port Data Output"] -pub type Pdo10W<'a, REG> = crate::BitWriter<'a, REG, Pdo10>; -impl<'a, REG> Pdo10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo10::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo10::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo11 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO11` reader - Port Data Output"] -pub type Pdo11R = crate::BitReader; -impl Pdo11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo11 { - match self.bits { - false => Pdo11::Pdo0, - true => Pdo11::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo11::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo11::Pdo1 - } -} -#[doc = "Field `PDO11` writer - Port Data Output"] -pub type Pdo11W<'a, REG> = crate::BitWriter<'a, REG, Pdo11>; -impl<'a, REG> Pdo11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo11::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo11::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo12 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO12` reader - Port Data Output"] -pub type Pdo12R = crate::BitReader; -impl Pdo12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo12 { - match self.bits { - false => Pdo12::Pdo0, - true => Pdo12::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo12::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo12::Pdo1 - } -} -#[doc = "Field `PDO12` writer - Port Data Output"] -pub type Pdo12W<'a, REG> = crate::BitWriter<'a, REG, Pdo12>; -impl<'a, REG> Pdo12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo12::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo12::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo13 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO13` reader - Port Data Output"] -pub type Pdo13R = crate::BitReader; -impl Pdo13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo13 { - match self.bits { - false => Pdo13::Pdo0, - true => Pdo13::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo13::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo13::Pdo1 - } -} -#[doc = "Field `PDO13` writer - Port Data Output"] -pub type Pdo13W<'a, REG> = crate::BitWriter<'a, REG, Pdo13>; -impl<'a, REG> Pdo13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo13::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo13::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo14 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO14` reader - Port Data Output"] -pub type Pdo14R = crate::BitReader; -impl Pdo14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo14 { - match self.bits { - false => Pdo14::Pdo0, - true => Pdo14::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo14::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo14::Pdo1 - } -} -#[doc = "Field `PDO14` writer - Port Data Output"] -pub type Pdo14W<'a, REG> = crate::BitWriter<'a, REG, Pdo14>; -impl<'a, REG> Pdo14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo14::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo14::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo15 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO15` reader - Port Data Output"] -pub type Pdo15R = crate::BitReader; -impl Pdo15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo15 { - match self.bits { - false => Pdo15::Pdo0, - true => Pdo15::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo15::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo15::Pdo1 - } -} -#[doc = "Field `PDO15` writer - Port Data Output"] -pub type Pdo15W<'a, REG> = crate::BitWriter<'a, REG, Pdo15>; -impl<'a, REG> Pdo15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo15::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo15::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo16 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO16` reader - Port Data Output"] -pub type Pdo16R = crate::BitReader; -impl Pdo16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo16 { - match self.bits { - false => Pdo16::Pdo0, - true => Pdo16::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo16::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo16::Pdo1 - } -} -#[doc = "Field `PDO16` writer - Port Data Output"] -pub type Pdo16W<'a, REG> = crate::BitWriter<'a, REG, Pdo16>; -impl<'a, REG> Pdo16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo16::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo16::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo17 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO17` reader - Port Data Output"] -pub type Pdo17R = crate::BitReader; -impl Pdo17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo17 { - match self.bits { - false => Pdo17::Pdo0, - true => Pdo17::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo17::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo17::Pdo1 - } -} -#[doc = "Field `PDO17` writer - Port Data Output"] -pub type Pdo17W<'a, REG> = crate::BitWriter<'a, REG, Pdo17>; -impl<'a, REG> Pdo17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo17::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo17::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo18 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO18` reader - Port Data Output"] -pub type Pdo18R = crate::BitReader; -impl Pdo18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo18 { - match self.bits { - false => Pdo18::Pdo0, - true => Pdo18::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo18::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo18::Pdo1 - } -} -#[doc = "Field `PDO18` writer - Port Data Output"] -pub type Pdo18W<'a, REG> = crate::BitWriter<'a, REG, Pdo18>; -impl<'a, REG> Pdo18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo18::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo18::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo19 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO19` reader - Port Data Output"] -pub type Pdo19R = crate::BitReader; -impl Pdo19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo19 { - match self.bits { - false => Pdo19::Pdo0, - true => Pdo19::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo19::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo19::Pdo1 - } -} -#[doc = "Field `PDO19` writer - Port Data Output"] -pub type Pdo19W<'a, REG> = crate::BitWriter<'a, REG, Pdo19>; -impl<'a, REG> Pdo19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo19::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo19::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo20 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO20` reader - Port Data Output"] -pub type Pdo20R = crate::BitReader; -impl Pdo20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo20 { - match self.bits { - false => Pdo20::Pdo0, - true => Pdo20::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo20::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo20::Pdo1 - } -} -#[doc = "Field `PDO20` writer - Port Data Output"] -pub type Pdo20W<'a, REG> = crate::BitWriter<'a, REG, Pdo20>; -impl<'a, REG> Pdo20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo20::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo20::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo21 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO21` reader - Port Data Output"] -pub type Pdo21R = crate::BitReader; -impl Pdo21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo21 { - match self.bits { - false => Pdo21::Pdo0, - true => Pdo21::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo21::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo21::Pdo1 - } -} -#[doc = "Field `PDO21` writer - Port Data Output"] -pub type Pdo21W<'a, REG> = crate::BitWriter<'a, REG, Pdo21>; -impl<'a, REG> Pdo21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo21::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo21::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo22 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO22` reader - Port Data Output"] -pub type Pdo22R = crate::BitReader; -impl Pdo22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo22 { - match self.bits { - false => Pdo22::Pdo0, - true => Pdo22::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo22::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo22::Pdo1 - } -} -#[doc = "Field `PDO22` writer - Port Data Output"] -pub type Pdo22W<'a, REG> = crate::BitWriter<'a, REG, Pdo22>; -impl<'a, REG> Pdo22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo22::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo22::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo23 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO23` reader - Port Data Output"] -pub type Pdo23R = crate::BitReader; -impl Pdo23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo23 { - match self.bits { - false => Pdo23::Pdo0, - true => Pdo23::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo23::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo23::Pdo1 - } -} -#[doc = "Field `PDO23` writer - Port Data Output"] -pub type Pdo23W<'a, REG> = crate::BitWriter<'a, REG, Pdo23>; -impl<'a, REG> Pdo23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo23::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo23::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo24 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO24` reader - Port Data Output"] -pub type Pdo24R = crate::BitReader; -impl Pdo24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo24 { - match self.bits { - false => Pdo24::Pdo0, - true => Pdo24::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo24::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo24::Pdo1 - } -} -#[doc = "Field `PDO24` writer - Port Data Output"] -pub type Pdo24W<'a, REG> = crate::BitWriter<'a, REG, Pdo24>; -impl<'a, REG> Pdo24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo24::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo24::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo25 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO25` reader - Port Data Output"] -pub type Pdo25R = crate::BitReader; -impl Pdo25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo25 { - match self.bits { - false => Pdo25::Pdo0, - true => Pdo25::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo25::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo25::Pdo1 - } -} -#[doc = "Field `PDO25` writer - Port Data Output"] -pub type Pdo25W<'a, REG> = crate::BitWriter<'a, REG, Pdo25>; -impl<'a, REG> Pdo25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo25::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo25::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo26 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO26` reader - Port Data Output"] -pub type Pdo26R = crate::BitReader; -impl Pdo26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo26 { - match self.bits { - false => Pdo26::Pdo0, - true => Pdo26::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo26::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo26::Pdo1 - } -} -#[doc = "Field `PDO26` writer - Port Data Output"] -pub type Pdo26W<'a, REG> = crate::BitWriter<'a, REG, Pdo26>; -impl<'a, REG> Pdo26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo26::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo26::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo27 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO27` reader - Port Data Output"] -pub type Pdo27R = crate::BitReader; -impl Pdo27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo27 { - match self.bits { - false => Pdo27::Pdo0, - true => Pdo27::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo27::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo27::Pdo1 - } -} -#[doc = "Field `PDO27` writer - Port Data Output"] -pub type Pdo27W<'a, REG> = crate::BitWriter<'a, REG, Pdo27>; -impl<'a, REG> Pdo27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo27::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo27::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo28 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO28` reader - Port Data Output"] -pub type Pdo28R = crate::BitReader; -impl Pdo28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo28 { - match self.bits { - false => Pdo28::Pdo0, - true => Pdo28::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo28::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo28::Pdo1 - } -} -#[doc = "Field `PDO28` writer - Port Data Output"] -pub type Pdo28W<'a, REG> = crate::BitWriter<'a, REG, Pdo28>; -impl<'a, REG> Pdo28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo28::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo28::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo29 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO29` reader - Port Data Output"] -pub type Pdo29R = crate::BitReader; -impl Pdo29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo29 { - match self.bits { - false => Pdo29::Pdo0, - true => Pdo29::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo29::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo29::Pdo1 - } -} -#[doc = "Field `PDO29` writer - Port Data Output"] -pub type Pdo29W<'a, REG> = crate::BitWriter<'a, REG, Pdo29>; -impl<'a, REG> Pdo29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo29::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo29::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo30 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO30` reader - Port Data Output"] -pub type Pdo30R = crate::BitReader; -impl Pdo30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo30 { - match self.bits { - false => Pdo30::Pdo0, - true => Pdo30::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo30::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo30::Pdo1 - } -} -#[doc = "Field `PDO30` writer - Port Data Output"] -pub type Pdo30W<'a, REG> = crate::BitWriter<'a, REG, Pdo30>; -impl<'a, REG> Pdo30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo30::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo30::Pdo1) - } -} -#[doc = "Port Data Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdo31 { - #[doc = "0: Logic level 0"] - Pdo0 = 0, - #[doc = "1: Logic level 1"] - Pdo1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdo31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDO31` reader - Port Data Output"] -pub type Pdo31R = crate::BitReader; -impl Pdo31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdo31 { - match self.bits { - false => Pdo31::Pdo0, - true => Pdo31::Pdo1, - } - } - #[doc = "Logic level 0"] - #[inline(always)] - pub fn is_pdo0(&self) -> bool { - *self == Pdo31::Pdo0 - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn is_pdo1(&self) -> bool { - *self == Pdo31::Pdo1 - } -} -#[doc = "Field `PDO31` writer - Port Data Output"] -pub type Pdo31W<'a, REG> = crate::BitWriter<'a, REG, Pdo31>; -impl<'a, REG> Pdo31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic level 0"] - #[inline(always)] - pub fn pdo0(self) -> &'a mut crate::W { - self.variant(Pdo31::Pdo0) - } - #[doc = "Logic level 1"] - #[inline(always)] - pub fn pdo1(self) -> &'a mut crate::W { - self.variant(Pdo31::Pdo1) - } -} -impl R { - #[doc = "Bit 0 - Port Data Output"] - #[inline(always)] - pub fn pdo0(&self) -> Pdo0R { - Pdo0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Port Data Output"] - #[inline(always)] - pub fn pdo1(&self) -> Pdo1R { - Pdo1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Port Data Output"] - #[inline(always)] - pub fn pdo2(&self) -> Pdo2R { - Pdo2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Port Data Output"] - #[inline(always)] - pub fn pdo3(&self) -> Pdo3R { - Pdo3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Port Data Output"] - #[inline(always)] - pub fn pdo4(&self) -> Pdo4R { - Pdo4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Port Data Output"] - #[inline(always)] - pub fn pdo5(&self) -> Pdo5R { - Pdo5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Port Data Output"] - #[inline(always)] - pub fn pdo6(&self) -> Pdo6R { - Pdo6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Port Data Output"] - #[inline(always)] - pub fn pdo7(&self) -> Pdo7R { - Pdo7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Port Data Output"] - #[inline(always)] - pub fn pdo8(&self) -> Pdo8R { - Pdo8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Port Data Output"] - #[inline(always)] - pub fn pdo9(&self) -> Pdo9R { - Pdo9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Port Data Output"] - #[inline(always)] - pub fn pdo10(&self) -> Pdo10R { - Pdo10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Port Data Output"] - #[inline(always)] - pub fn pdo11(&self) -> Pdo11R { - Pdo11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Port Data Output"] - #[inline(always)] - pub fn pdo12(&self) -> Pdo12R { - Pdo12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Port Data Output"] - #[inline(always)] - pub fn pdo13(&self) -> Pdo13R { - Pdo13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Port Data Output"] - #[inline(always)] - pub fn pdo14(&self) -> Pdo14R { - Pdo14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Port Data Output"] - #[inline(always)] - pub fn pdo15(&self) -> Pdo15R { - Pdo15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Port Data Output"] - #[inline(always)] - pub fn pdo16(&self) -> Pdo16R { - Pdo16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Port Data Output"] - #[inline(always)] - pub fn pdo17(&self) -> Pdo17R { - Pdo17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Port Data Output"] - #[inline(always)] - pub fn pdo18(&self) -> Pdo18R { - Pdo18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Port Data Output"] - #[inline(always)] - pub fn pdo19(&self) -> Pdo19R { - Pdo19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Port Data Output"] - #[inline(always)] - pub fn pdo20(&self) -> Pdo20R { - Pdo20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Port Data Output"] - #[inline(always)] - pub fn pdo21(&self) -> Pdo21R { - Pdo21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Port Data Output"] - #[inline(always)] - pub fn pdo22(&self) -> Pdo22R { - Pdo22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Port Data Output"] - #[inline(always)] - pub fn pdo23(&self) -> Pdo23R { - Pdo23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Port Data Output"] - #[inline(always)] - pub fn pdo24(&self) -> Pdo24R { - Pdo24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Port Data Output"] - #[inline(always)] - pub fn pdo25(&self) -> Pdo25R { - Pdo25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Port Data Output"] - #[inline(always)] - pub fn pdo26(&self) -> Pdo26R { - Pdo26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Port Data Output"] - #[inline(always)] - pub fn pdo27(&self) -> Pdo27R { - Pdo27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Port Data Output"] - #[inline(always)] - pub fn pdo28(&self) -> Pdo28R { - Pdo28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Port Data Output"] - #[inline(always)] - pub fn pdo29(&self) -> Pdo29R { - Pdo29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Port Data Output"] - #[inline(always)] - pub fn pdo30(&self) -> Pdo30R { - Pdo30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Port Data Output"] - #[inline(always)] - pub fn pdo31(&self) -> Pdo31R { - Pdo31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Data Output"] - #[inline(always)] - pub fn pdo0(&mut self) -> Pdo0W { - Pdo0W::new(self, 0) - } - #[doc = "Bit 1 - Port Data Output"] - #[inline(always)] - pub fn pdo1(&mut self) -> Pdo1W { - Pdo1W::new(self, 1) - } - #[doc = "Bit 2 - Port Data Output"] - #[inline(always)] - pub fn pdo2(&mut self) -> Pdo2W { - Pdo2W::new(self, 2) - } - #[doc = "Bit 3 - Port Data Output"] - #[inline(always)] - pub fn pdo3(&mut self) -> Pdo3W { - Pdo3W::new(self, 3) - } - #[doc = "Bit 4 - Port Data Output"] - #[inline(always)] - pub fn pdo4(&mut self) -> Pdo4W { - Pdo4W::new(self, 4) - } - #[doc = "Bit 5 - Port Data Output"] - #[inline(always)] - pub fn pdo5(&mut self) -> Pdo5W { - Pdo5W::new(self, 5) - } - #[doc = "Bit 6 - Port Data Output"] - #[inline(always)] - pub fn pdo6(&mut self) -> Pdo6W { - Pdo6W::new(self, 6) - } - #[doc = "Bit 7 - Port Data Output"] - #[inline(always)] - pub fn pdo7(&mut self) -> Pdo7W { - Pdo7W::new(self, 7) - } - #[doc = "Bit 8 - Port Data Output"] - #[inline(always)] - pub fn pdo8(&mut self) -> Pdo8W { - Pdo8W::new(self, 8) - } - #[doc = "Bit 9 - Port Data Output"] - #[inline(always)] - pub fn pdo9(&mut self) -> Pdo9W { - Pdo9W::new(self, 9) - } - #[doc = "Bit 10 - Port Data Output"] - #[inline(always)] - pub fn pdo10(&mut self) -> Pdo10W { - Pdo10W::new(self, 10) - } - #[doc = "Bit 11 - Port Data Output"] - #[inline(always)] - pub fn pdo11(&mut self) -> Pdo11W { - Pdo11W::new(self, 11) - } - #[doc = "Bit 12 - Port Data Output"] - #[inline(always)] - pub fn pdo12(&mut self) -> Pdo12W { - Pdo12W::new(self, 12) - } - #[doc = "Bit 13 - Port Data Output"] - #[inline(always)] - pub fn pdo13(&mut self) -> Pdo13W { - Pdo13W::new(self, 13) - } - #[doc = "Bit 14 - Port Data Output"] - #[inline(always)] - pub fn pdo14(&mut self) -> Pdo14W { - Pdo14W::new(self, 14) - } - #[doc = "Bit 15 - Port Data Output"] - #[inline(always)] - pub fn pdo15(&mut self) -> Pdo15W { - Pdo15W::new(self, 15) - } - #[doc = "Bit 16 - Port Data Output"] - #[inline(always)] - pub fn pdo16(&mut self) -> Pdo16W { - Pdo16W::new(self, 16) - } - #[doc = "Bit 17 - Port Data Output"] - #[inline(always)] - pub fn pdo17(&mut self) -> Pdo17W { - Pdo17W::new(self, 17) - } - #[doc = "Bit 18 - Port Data Output"] - #[inline(always)] - pub fn pdo18(&mut self) -> Pdo18W { - Pdo18W::new(self, 18) - } - #[doc = "Bit 19 - Port Data Output"] - #[inline(always)] - pub fn pdo19(&mut self) -> Pdo19W { - Pdo19W::new(self, 19) - } - #[doc = "Bit 20 - Port Data Output"] - #[inline(always)] - pub fn pdo20(&mut self) -> Pdo20W { - Pdo20W::new(self, 20) - } - #[doc = "Bit 21 - Port Data Output"] - #[inline(always)] - pub fn pdo21(&mut self) -> Pdo21W { - Pdo21W::new(self, 21) - } - #[doc = "Bit 22 - Port Data Output"] - #[inline(always)] - pub fn pdo22(&mut self) -> Pdo22W { - Pdo22W::new(self, 22) - } - #[doc = "Bit 23 - Port Data Output"] - #[inline(always)] - pub fn pdo23(&mut self) -> Pdo23W { - Pdo23W::new(self, 23) - } - #[doc = "Bit 24 - Port Data Output"] - #[inline(always)] - pub fn pdo24(&mut self) -> Pdo24W { - Pdo24W::new(self, 24) - } - #[doc = "Bit 25 - Port Data Output"] - #[inline(always)] - pub fn pdo25(&mut self) -> Pdo25W { - Pdo25W::new(self, 25) - } - #[doc = "Bit 26 - Port Data Output"] - #[inline(always)] - pub fn pdo26(&mut self) -> Pdo26W { - Pdo26W::new(self, 26) - } - #[doc = "Bit 27 - Port Data Output"] - #[inline(always)] - pub fn pdo27(&mut self) -> Pdo27W { - Pdo27W::new(self, 27) - } - #[doc = "Bit 28 - Port Data Output"] - #[inline(always)] - pub fn pdo28(&mut self) -> Pdo28W { - Pdo28W::new(self, 28) - } - #[doc = "Bit 29 - Port Data Output"] - #[inline(always)] - pub fn pdo29(&mut self) -> Pdo29W { - Pdo29W::new(self, 29) - } - #[doc = "Bit 30 - Port Data Output"] - #[inline(always)] - pub fn pdo30(&mut self) -> Pdo30W { - Pdo30W::new(self, 30) - } - #[doc = "Bit 31 - Port Data Output"] - #[inline(always)] - pub fn pdo31(&mut self) -> Pdo31W { - Pdo31W::new(self, 31) - } -} -#[doc = "Port Data Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pdor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PdorSpec; -impl crate::RegisterSpec for PdorSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pdor::R`](R) reader structure"] -impl crate::Readable for PdorSpec {} -#[doc = "`write(|w| ..)` method takes [`pdor::W`](W) writer structure"] -impl crate::Writable for PdorSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PDOR to value 0"] -impl crate::Resettable for PdorSpec {} diff --git a/mcxa276-pac/src/gpio0/pdr.rs b/mcxa276-pac/src/gpio0/pdr.rs deleted file mode 100644 index f37f80c6d..000000000 --- a/mcxa276-pac/src/gpio0/pdr.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `PDR[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `PDR[%s]` writer"] -pub type W = crate::W; -#[doc = "Pin Data (I/O)\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pd { - #[doc = "0: Logic zero"] - Pd0 = 0, - #[doc = "1: Logic one"] - Pd1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PD` reader - Pin Data (I/O)"] -pub type PdR = crate::BitReader; -impl PdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pd { - match self.bits { - false => Pd::Pd0, - true => Pd::Pd1, - } - } - #[doc = "Logic zero"] - #[inline(always)] - pub fn is_pd0(&self) -> bool { - *self == Pd::Pd0 - } - #[doc = "Logic one"] - #[inline(always)] - pub fn is_pd1(&self) -> bool { - *self == Pd::Pd1 - } -} -#[doc = "Field `PD` writer - Pin Data (I/O)"] -pub type PdW<'a, REG> = crate::BitWriter<'a, REG, Pd>; -impl<'a, REG> PdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Logic zero"] - #[inline(always)] - pub fn pd0(self) -> &'a mut crate::W { - self.variant(Pd::Pd0) - } - #[doc = "Logic one"] - #[inline(always)] - pub fn pd1(self) -> &'a mut crate::W { - self.variant(Pd::Pd1) - } -} -impl R { - #[doc = "Bit 0 - Pin Data (I/O)"] - #[inline(always)] - pub fn pd(&self) -> PdR { - PdR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pin Data (I/O)"] - #[inline(always)] - pub fn pd(&mut self) -> PdW { - PdW::new(self, 0) - } -} -#[doc = "Pin Data\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PdrSpec; -impl crate::RegisterSpec for PdrSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`pdr::R`](R) reader structure"] -impl crate::Readable for PdrSpec {} -#[doc = "`write(|w| ..)` method takes [`pdr::W`](W) writer structure"] -impl crate::Writable for PdrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PDR[%s] to value 0"] -impl crate::Resettable for PdrSpec {} diff --git a/mcxa276-pac/src/gpio0/pidr.rs b/mcxa276-pac/src/gpio0/pidr.rs deleted file mode 100644 index 619c9b97b..000000000 --- a/mcxa276-pac/src/gpio0/pidr.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `PIDR` reader"] -pub type R = crate::R; -#[doc = "Register `PIDR` writer"] -pub type W = crate::W; -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid0 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID0` reader - Port Input Disable"] -pub type Pid0R = crate::BitReader; -impl Pid0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid0 { - match self.bits { - false => Pid0::Pid0, - true => Pid0::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid0::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid0::Pid1 - } -} -#[doc = "Field `PID0` writer - Port Input Disable"] -pub type Pid0W<'a, REG> = crate::BitWriter<'a, REG, Pid0>; -impl<'a, REG> Pid0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid0::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid0::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid1 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID1` reader - Port Input Disable"] -pub type Pid1R = crate::BitReader; -impl Pid1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid1 { - match self.bits { - false => Pid1::Pid0, - true => Pid1::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid1::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid1::Pid1 - } -} -#[doc = "Field `PID1` writer - Port Input Disable"] -pub type Pid1W<'a, REG> = crate::BitWriter<'a, REG, Pid1>; -impl<'a, REG> Pid1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid1::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid1::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid2 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID2` reader - Port Input Disable"] -pub type Pid2R = crate::BitReader; -impl Pid2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid2 { - match self.bits { - false => Pid2::Pid0, - true => Pid2::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid2::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid2::Pid1 - } -} -#[doc = "Field `PID2` writer - Port Input Disable"] -pub type Pid2W<'a, REG> = crate::BitWriter<'a, REG, Pid2>; -impl<'a, REG> Pid2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid2::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid2::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid3 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID3` reader - Port Input Disable"] -pub type Pid3R = crate::BitReader; -impl Pid3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid3 { - match self.bits { - false => Pid3::Pid0, - true => Pid3::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid3::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid3::Pid1 - } -} -#[doc = "Field `PID3` writer - Port Input Disable"] -pub type Pid3W<'a, REG> = crate::BitWriter<'a, REG, Pid3>; -impl<'a, REG> Pid3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid3::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid3::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid4 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID4` reader - Port Input Disable"] -pub type Pid4R = crate::BitReader; -impl Pid4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid4 { - match self.bits { - false => Pid4::Pid0, - true => Pid4::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid4::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid4::Pid1 - } -} -#[doc = "Field `PID4` writer - Port Input Disable"] -pub type Pid4W<'a, REG> = crate::BitWriter<'a, REG, Pid4>; -impl<'a, REG> Pid4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid4::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid4::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid5 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID5` reader - Port Input Disable"] -pub type Pid5R = crate::BitReader; -impl Pid5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid5 { - match self.bits { - false => Pid5::Pid0, - true => Pid5::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid5::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid5::Pid1 - } -} -#[doc = "Field `PID5` writer - Port Input Disable"] -pub type Pid5W<'a, REG> = crate::BitWriter<'a, REG, Pid5>; -impl<'a, REG> Pid5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid5::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid5::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid6 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID6` reader - Port Input Disable"] -pub type Pid6R = crate::BitReader; -impl Pid6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid6 { - match self.bits { - false => Pid6::Pid0, - true => Pid6::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid6::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid6::Pid1 - } -} -#[doc = "Field `PID6` writer - Port Input Disable"] -pub type Pid6W<'a, REG> = crate::BitWriter<'a, REG, Pid6>; -impl<'a, REG> Pid6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid6::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid6::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid7 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID7` reader - Port Input Disable"] -pub type Pid7R = crate::BitReader; -impl Pid7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid7 { - match self.bits { - false => Pid7::Pid0, - true => Pid7::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid7::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid7::Pid1 - } -} -#[doc = "Field `PID7` writer - Port Input Disable"] -pub type Pid7W<'a, REG> = crate::BitWriter<'a, REG, Pid7>; -impl<'a, REG> Pid7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid7::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid7::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid8 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID8` reader - Port Input Disable"] -pub type Pid8R = crate::BitReader; -impl Pid8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid8 { - match self.bits { - false => Pid8::Pid0, - true => Pid8::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid8::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid8::Pid1 - } -} -#[doc = "Field `PID8` writer - Port Input Disable"] -pub type Pid8W<'a, REG> = crate::BitWriter<'a, REG, Pid8>; -impl<'a, REG> Pid8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid8::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid8::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid9 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID9` reader - Port Input Disable"] -pub type Pid9R = crate::BitReader; -impl Pid9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid9 { - match self.bits { - false => Pid9::Pid0, - true => Pid9::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid9::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid9::Pid1 - } -} -#[doc = "Field `PID9` writer - Port Input Disable"] -pub type Pid9W<'a, REG> = crate::BitWriter<'a, REG, Pid9>; -impl<'a, REG> Pid9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid9::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid9::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid10 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID10` reader - Port Input Disable"] -pub type Pid10R = crate::BitReader; -impl Pid10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid10 { - match self.bits { - false => Pid10::Pid0, - true => Pid10::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid10::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid10::Pid1 - } -} -#[doc = "Field `PID10` writer - Port Input Disable"] -pub type Pid10W<'a, REG> = crate::BitWriter<'a, REG, Pid10>; -impl<'a, REG> Pid10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid10::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid10::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid11 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID11` reader - Port Input Disable"] -pub type Pid11R = crate::BitReader; -impl Pid11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid11 { - match self.bits { - false => Pid11::Pid0, - true => Pid11::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid11::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid11::Pid1 - } -} -#[doc = "Field `PID11` writer - Port Input Disable"] -pub type Pid11W<'a, REG> = crate::BitWriter<'a, REG, Pid11>; -impl<'a, REG> Pid11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid11::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid11::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid12 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID12` reader - Port Input Disable"] -pub type Pid12R = crate::BitReader; -impl Pid12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid12 { - match self.bits { - false => Pid12::Pid0, - true => Pid12::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid12::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid12::Pid1 - } -} -#[doc = "Field `PID12` writer - Port Input Disable"] -pub type Pid12W<'a, REG> = crate::BitWriter<'a, REG, Pid12>; -impl<'a, REG> Pid12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid12::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid12::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid13 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID13` reader - Port Input Disable"] -pub type Pid13R = crate::BitReader; -impl Pid13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid13 { - match self.bits { - false => Pid13::Pid0, - true => Pid13::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid13::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid13::Pid1 - } -} -#[doc = "Field `PID13` writer - Port Input Disable"] -pub type Pid13W<'a, REG> = crate::BitWriter<'a, REG, Pid13>; -impl<'a, REG> Pid13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid13::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid13::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid14 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID14` reader - Port Input Disable"] -pub type Pid14R = crate::BitReader; -impl Pid14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid14 { - match self.bits { - false => Pid14::Pid0, - true => Pid14::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid14::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid14::Pid1 - } -} -#[doc = "Field `PID14` writer - Port Input Disable"] -pub type Pid14W<'a, REG> = crate::BitWriter<'a, REG, Pid14>; -impl<'a, REG> Pid14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid14::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid14::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid15 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID15` reader - Port Input Disable"] -pub type Pid15R = crate::BitReader; -impl Pid15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid15 { - match self.bits { - false => Pid15::Pid0, - true => Pid15::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid15::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid15::Pid1 - } -} -#[doc = "Field `PID15` writer - Port Input Disable"] -pub type Pid15W<'a, REG> = crate::BitWriter<'a, REG, Pid15>; -impl<'a, REG> Pid15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid15::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid15::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid16 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID16` reader - Port Input Disable"] -pub type Pid16R = crate::BitReader; -impl Pid16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid16 { - match self.bits { - false => Pid16::Pid0, - true => Pid16::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid16::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid16::Pid1 - } -} -#[doc = "Field `PID16` writer - Port Input Disable"] -pub type Pid16W<'a, REG> = crate::BitWriter<'a, REG, Pid16>; -impl<'a, REG> Pid16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid16::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid16::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid17 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID17` reader - Port Input Disable"] -pub type Pid17R = crate::BitReader; -impl Pid17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid17 { - match self.bits { - false => Pid17::Pid0, - true => Pid17::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid17::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid17::Pid1 - } -} -#[doc = "Field `PID17` writer - Port Input Disable"] -pub type Pid17W<'a, REG> = crate::BitWriter<'a, REG, Pid17>; -impl<'a, REG> Pid17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid17::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid17::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid18 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID18` reader - Port Input Disable"] -pub type Pid18R = crate::BitReader; -impl Pid18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid18 { - match self.bits { - false => Pid18::Pid0, - true => Pid18::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid18::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid18::Pid1 - } -} -#[doc = "Field `PID18` writer - Port Input Disable"] -pub type Pid18W<'a, REG> = crate::BitWriter<'a, REG, Pid18>; -impl<'a, REG> Pid18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid18::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid18::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid19 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID19` reader - Port Input Disable"] -pub type Pid19R = crate::BitReader; -impl Pid19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid19 { - match self.bits { - false => Pid19::Pid0, - true => Pid19::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid19::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid19::Pid1 - } -} -#[doc = "Field `PID19` writer - Port Input Disable"] -pub type Pid19W<'a, REG> = crate::BitWriter<'a, REG, Pid19>; -impl<'a, REG> Pid19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid19::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid19::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid20 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID20` reader - Port Input Disable"] -pub type Pid20R = crate::BitReader; -impl Pid20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid20 { - match self.bits { - false => Pid20::Pid0, - true => Pid20::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid20::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid20::Pid1 - } -} -#[doc = "Field `PID20` writer - Port Input Disable"] -pub type Pid20W<'a, REG> = crate::BitWriter<'a, REG, Pid20>; -impl<'a, REG> Pid20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid20::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid20::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid21 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID21` reader - Port Input Disable"] -pub type Pid21R = crate::BitReader; -impl Pid21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid21 { - match self.bits { - false => Pid21::Pid0, - true => Pid21::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid21::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid21::Pid1 - } -} -#[doc = "Field `PID21` writer - Port Input Disable"] -pub type Pid21W<'a, REG> = crate::BitWriter<'a, REG, Pid21>; -impl<'a, REG> Pid21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid21::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid21::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid22 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID22` reader - Port Input Disable"] -pub type Pid22R = crate::BitReader; -impl Pid22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid22 { - match self.bits { - false => Pid22::Pid0, - true => Pid22::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid22::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid22::Pid1 - } -} -#[doc = "Field `PID22` writer - Port Input Disable"] -pub type Pid22W<'a, REG> = crate::BitWriter<'a, REG, Pid22>; -impl<'a, REG> Pid22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid22::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid22::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid23 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID23` reader - Port Input Disable"] -pub type Pid23R = crate::BitReader; -impl Pid23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid23 { - match self.bits { - false => Pid23::Pid0, - true => Pid23::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid23::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid23::Pid1 - } -} -#[doc = "Field `PID23` writer - Port Input Disable"] -pub type Pid23W<'a, REG> = crate::BitWriter<'a, REG, Pid23>; -impl<'a, REG> Pid23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid23::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid23::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid24 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID24` reader - Port Input Disable"] -pub type Pid24R = crate::BitReader; -impl Pid24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid24 { - match self.bits { - false => Pid24::Pid0, - true => Pid24::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid24::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid24::Pid1 - } -} -#[doc = "Field `PID24` writer - Port Input Disable"] -pub type Pid24W<'a, REG> = crate::BitWriter<'a, REG, Pid24>; -impl<'a, REG> Pid24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid24::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid24::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid25 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID25` reader - Port Input Disable"] -pub type Pid25R = crate::BitReader; -impl Pid25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid25 { - match self.bits { - false => Pid25::Pid0, - true => Pid25::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid25::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid25::Pid1 - } -} -#[doc = "Field `PID25` writer - Port Input Disable"] -pub type Pid25W<'a, REG> = crate::BitWriter<'a, REG, Pid25>; -impl<'a, REG> Pid25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid25::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid25::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid26 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID26` reader - Port Input Disable"] -pub type Pid26R = crate::BitReader; -impl Pid26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid26 { - match self.bits { - false => Pid26::Pid0, - true => Pid26::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid26::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid26::Pid1 - } -} -#[doc = "Field `PID26` writer - Port Input Disable"] -pub type Pid26W<'a, REG> = crate::BitWriter<'a, REG, Pid26>; -impl<'a, REG> Pid26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid26::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid26::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid27 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID27` reader - Port Input Disable"] -pub type Pid27R = crate::BitReader; -impl Pid27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid27 { - match self.bits { - false => Pid27::Pid0, - true => Pid27::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid27::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid27::Pid1 - } -} -#[doc = "Field `PID27` writer - Port Input Disable"] -pub type Pid27W<'a, REG> = crate::BitWriter<'a, REG, Pid27>; -impl<'a, REG> Pid27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid27::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid27::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid28 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID28` reader - Port Input Disable"] -pub type Pid28R = crate::BitReader; -impl Pid28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid28 { - match self.bits { - false => Pid28::Pid0, - true => Pid28::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid28::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid28::Pid1 - } -} -#[doc = "Field `PID28` writer - Port Input Disable"] -pub type Pid28W<'a, REG> = crate::BitWriter<'a, REG, Pid28>; -impl<'a, REG> Pid28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid28::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid28::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid29 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID29` reader - Port Input Disable"] -pub type Pid29R = crate::BitReader; -impl Pid29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid29 { - match self.bits { - false => Pid29::Pid0, - true => Pid29::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid29::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid29::Pid1 - } -} -#[doc = "Field `PID29` writer - Port Input Disable"] -pub type Pid29W<'a, REG> = crate::BitWriter<'a, REG, Pid29>; -impl<'a, REG> Pid29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid29::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid29::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid30 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID30` reader - Port Input Disable"] -pub type Pid30R = crate::BitReader; -impl Pid30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid30 { - match self.bits { - false => Pid30::Pid0, - true => Pid30::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid30::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid30::Pid1 - } -} -#[doc = "Field `PID30` writer - Port Input Disable"] -pub type Pid30W<'a, REG> = crate::BitWriter<'a, REG, Pid30>; -impl<'a, REG> Pid30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid30::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid30::Pid1) - } -} -#[doc = "Port Input Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pid31 { - #[doc = "0: Configured for general-purpose input"] - Pid0 = 0, - #[doc = "1: Disabled for general-purpose input"] - Pid1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pid31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PID31` reader - Port Input Disable"] -pub type Pid31R = crate::BitReader; -impl Pid31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pid31 { - match self.bits { - false => Pid31::Pid0, - true => Pid31::Pid1, - } - } - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn is_pid0(&self) -> bool { - *self == Pid31::Pid0 - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn is_pid1(&self) -> bool { - *self == Pid31::Pid1 - } -} -#[doc = "Field `PID31` writer - Port Input Disable"] -pub type Pid31W<'a, REG> = crate::BitWriter<'a, REG, Pid31>; -impl<'a, REG> Pid31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configured for general-purpose input"] - #[inline(always)] - pub fn pid0(self) -> &'a mut crate::W { - self.variant(Pid31::Pid0) - } - #[doc = "Disabled for general-purpose input"] - #[inline(always)] - pub fn pid1(self) -> &'a mut crate::W { - self.variant(Pid31::Pid1) - } -} -impl R { - #[doc = "Bit 0 - Port Input Disable"] - #[inline(always)] - pub fn pid0(&self) -> Pid0R { - Pid0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Port Input Disable"] - #[inline(always)] - pub fn pid1(&self) -> Pid1R { - Pid1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Port Input Disable"] - #[inline(always)] - pub fn pid2(&self) -> Pid2R { - Pid2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Port Input Disable"] - #[inline(always)] - pub fn pid3(&self) -> Pid3R { - Pid3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Port Input Disable"] - #[inline(always)] - pub fn pid4(&self) -> Pid4R { - Pid4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Port Input Disable"] - #[inline(always)] - pub fn pid5(&self) -> Pid5R { - Pid5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Port Input Disable"] - #[inline(always)] - pub fn pid6(&self) -> Pid6R { - Pid6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Port Input Disable"] - #[inline(always)] - pub fn pid7(&self) -> Pid7R { - Pid7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Port Input Disable"] - #[inline(always)] - pub fn pid8(&self) -> Pid8R { - Pid8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Port Input Disable"] - #[inline(always)] - pub fn pid9(&self) -> Pid9R { - Pid9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Port Input Disable"] - #[inline(always)] - pub fn pid10(&self) -> Pid10R { - Pid10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Port Input Disable"] - #[inline(always)] - pub fn pid11(&self) -> Pid11R { - Pid11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Port Input Disable"] - #[inline(always)] - pub fn pid12(&self) -> Pid12R { - Pid12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Port Input Disable"] - #[inline(always)] - pub fn pid13(&self) -> Pid13R { - Pid13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Port Input Disable"] - #[inline(always)] - pub fn pid14(&self) -> Pid14R { - Pid14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Port Input Disable"] - #[inline(always)] - pub fn pid15(&self) -> Pid15R { - Pid15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Port Input Disable"] - #[inline(always)] - pub fn pid16(&self) -> Pid16R { - Pid16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Port Input Disable"] - #[inline(always)] - pub fn pid17(&self) -> Pid17R { - Pid17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Port Input Disable"] - #[inline(always)] - pub fn pid18(&self) -> Pid18R { - Pid18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Port Input Disable"] - #[inline(always)] - pub fn pid19(&self) -> Pid19R { - Pid19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Port Input Disable"] - #[inline(always)] - pub fn pid20(&self) -> Pid20R { - Pid20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Port Input Disable"] - #[inline(always)] - pub fn pid21(&self) -> Pid21R { - Pid21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Port Input Disable"] - #[inline(always)] - pub fn pid22(&self) -> Pid22R { - Pid22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Port Input Disable"] - #[inline(always)] - pub fn pid23(&self) -> Pid23R { - Pid23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Port Input Disable"] - #[inline(always)] - pub fn pid24(&self) -> Pid24R { - Pid24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Port Input Disable"] - #[inline(always)] - pub fn pid25(&self) -> Pid25R { - Pid25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Port Input Disable"] - #[inline(always)] - pub fn pid26(&self) -> Pid26R { - Pid26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Port Input Disable"] - #[inline(always)] - pub fn pid27(&self) -> Pid27R { - Pid27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Port Input Disable"] - #[inline(always)] - pub fn pid28(&self) -> Pid28R { - Pid28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Port Input Disable"] - #[inline(always)] - pub fn pid29(&self) -> Pid29R { - Pid29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Port Input Disable"] - #[inline(always)] - pub fn pid30(&self) -> Pid30R { - Pid30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Port Input Disable"] - #[inline(always)] - pub fn pid31(&self) -> Pid31R { - Pid31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Input Disable"] - #[inline(always)] - pub fn pid0(&mut self) -> Pid0W { - Pid0W::new(self, 0) - } - #[doc = "Bit 1 - Port Input Disable"] - #[inline(always)] - pub fn pid1(&mut self) -> Pid1W { - Pid1W::new(self, 1) - } - #[doc = "Bit 2 - Port Input Disable"] - #[inline(always)] - pub fn pid2(&mut self) -> Pid2W { - Pid2W::new(self, 2) - } - #[doc = "Bit 3 - Port Input Disable"] - #[inline(always)] - pub fn pid3(&mut self) -> Pid3W { - Pid3W::new(self, 3) - } - #[doc = "Bit 4 - Port Input Disable"] - #[inline(always)] - pub fn pid4(&mut self) -> Pid4W { - Pid4W::new(self, 4) - } - #[doc = "Bit 5 - Port Input Disable"] - #[inline(always)] - pub fn pid5(&mut self) -> Pid5W { - Pid5W::new(self, 5) - } - #[doc = "Bit 6 - Port Input Disable"] - #[inline(always)] - pub fn pid6(&mut self) -> Pid6W { - Pid6W::new(self, 6) - } - #[doc = "Bit 7 - Port Input Disable"] - #[inline(always)] - pub fn pid7(&mut self) -> Pid7W { - Pid7W::new(self, 7) - } - #[doc = "Bit 8 - Port Input Disable"] - #[inline(always)] - pub fn pid8(&mut self) -> Pid8W { - Pid8W::new(self, 8) - } - #[doc = "Bit 9 - Port Input Disable"] - #[inline(always)] - pub fn pid9(&mut self) -> Pid9W { - Pid9W::new(self, 9) - } - #[doc = "Bit 10 - Port Input Disable"] - #[inline(always)] - pub fn pid10(&mut self) -> Pid10W { - Pid10W::new(self, 10) - } - #[doc = "Bit 11 - Port Input Disable"] - #[inline(always)] - pub fn pid11(&mut self) -> Pid11W { - Pid11W::new(self, 11) - } - #[doc = "Bit 12 - Port Input Disable"] - #[inline(always)] - pub fn pid12(&mut self) -> Pid12W { - Pid12W::new(self, 12) - } - #[doc = "Bit 13 - Port Input Disable"] - #[inline(always)] - pub fn pid13(&mut self) -> Pid13W { - Pid13W::new(self, 13) - } - #[doc = "Bit 14 - Port Input Disable"] - #[inline(always)] - pub fn pid14(&mut self) -> Pid14W { - Pid14W::new(self, 14) - } - #[doc = "Bit 15 - Port Input Disable"] - #[inline(always)] - pub fn pid15(&mut self) -> Pid15W { - Pid15W::new(self, 15) - } - #[doc = "Bit 16 - Port Input Disable"] - #[inline(always)] - pub fn pid16(&mut self) -> Pid16W { - Pid16W::new(self, 16) - } - #[doc = "Bit 17 - Port Input Disable"] - #[inline(always)] - pub fn pid17(&mut self) -> Pid17W { - Pid17W::new(self, 17) - } - #[doc = "Bit 18 - Port Input Disable"] - #[inline(always)] - pub fn pid18(&mut self) -> Pid18W { - Pid18W::new(self, 18) - } - #[doc = "Bit 19 - Port Input Disable"] - #[inline(always)] - pub fn pid19(&mut self) -> Pid19W { - Pid19W::new(self, 19) - } - #[doc = "Bit 20 - Port Input Disable"] - #[inline(always)] - pub fn pid20(&mut self) -> Pid20W { - Pid20W::new(self, 20) - } - #[doc = "Bit 21 - Port Input Disable"] - #[inline(always)] - pub fn pid21(&mut self) -> Pid21W { - Pid21W::new(self, 21) - } - #[doc = "Bit 22 - Port Input Disable"] - #[inline(always)] - pub fn pid22(&mut self) -> Pid22W { - Pid22W::new(self, 22) - } - #[doc = "Bit 23 - Port Input Disable"] - #[inline(always)] - pub fn pid23(&mut self) -> Pid23W { - Pid23W::new(self, 23) - } - #[doc = "Bit 24 - Port Input Disable"] - #[inline(always)] - pub fn pid24(&mut self) -> Pid24W { - Pid24W::new(self, 24) - } - #[doc = "Bit 25 - Port Input Disable"] - #[inline(always)] - pub fn pid25(&mut self) -> Pid25W { - Pid25W::new(self, 25) - } - #[doc = "Bit 26 - Port Input Disable"] - #[inline(always)] - pub fn pid26(&mut self) -> Pid26W { - Pid26W::new(self, 26) - } - #[doc = "Bit 27 - Port Input Disable"] - #[inline(always)] - pub fn pid27(&mut self) -> Pid27W { - Pid27W::new(self, 27) - } - #[doc = "Bit 28 - Port Input Disable"] - #[inline(always)] - pub fn pid28(&mut self) -> Pid28W { - Pid28W::new(self, 28) - } - #[doc = "Bit 29 - Port Input Disable"] - #[inline(always)] - pub fn pid29(&mut self) -> Pid29W { - Pid29W::new(self, 29) - } - #[doc = "Bit 30 - Port Input Disable"] - #[inline(always)] - pub fn pid30(&mut self) -> Pid30W { - Pid30W::new(self, 30) - } - #[doc = "Bit 31 - Port Input Disable"] - #[inline(always)] - pub fn pid31(&mut self) -> Pid31W { - Pid31W::new(self, 31) - } -} -#[doc = "Port Input Disable\n\nYou can [`read`](crate::Reg::read) this register and get [`pidr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PidrSpec; -impl crate::RegisterSpec for PidrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pidr::R`](R) reader structure"] -impl crate::Readable for PidrSpec {} -#[doc = "`write(|w| ..)` method takes [`pidr::W`](W) writer structure"] -impl crate::Writable for PidrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIDR to value 0"] -impl crate::Resettable for PidrSpec {} diff --git a/mcxa276-pac/src/gpio0/psor.rs b/mcxa276-pac/src/gpio0/psor.rs deleted file mode 100644 index e0cea51f1..000000000 --- a/mcxa276-pac/src/gpio0/psor.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `PSOR` reader"] -pub type R = crate::R; -#[doc = "Register `PSOR` writer"] -pub type W = crate::W; -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso0 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO0` reader - Port Set Output"] -pub type Ptso0R = crate::BitReader; -impl Ptso0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso0 { - match self.bits { - false => Ptso0::Ptso0, - true => Ptso0::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso0::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso0::Ptso1 - } -} -#[doc = "Field `PTSO0` writer - Port Set Output"] -pub type Ptso0W<'a, REG> = crate::BitWriter<'a, REG, Ptso0>; -impl<'a, REG> Ptso0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso0::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso0::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso1 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO1` reader - Port Set Output"] -pub type Ptso1R = crate::BitReader; -impl Ptso1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso1 { - match self.bits { - false => Ptso1::Ptso0, - true => Ptso1::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso1::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso1::Ptso1 - } -} -#[doc = "Field `PTSO1` writer - Port Set Output"] -pub type Ptso1W<'a, REG> = crate::BitWriter<'a, REG, Ptso1>; -impl<'a, REG> Ptso1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso1::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso1::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso2 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO2` reader - Port Set Output"] -pub type Ptso2R = crate::BitReader; -impl Ptso2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso2 { - match self.bits { - false => Ptso2::Ptso0, - true => Ptso2::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso2::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso2::Ptso1 - } -} -#[doc = "Field `PTSO2` writer - Port Set Output"] -pub type Ptso2W<'a, REG> = crate::BitWriter<'a, REG, Ptso2>; -impl<'a, REG> Ptso2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso2::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso2::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso3 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO3` reader - Port Set Output"] -pub type Ptso3R = crate::BitReader; -impl Ptso3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso3 { - match self.bits { - false => Ptso3::Ptso0, - true => Ptso3::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso3::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso3::Ptso1 - } -} -#[doc = "Field `PTSO3` writer - Port Set Output"] -pub type Ptso3W<'a, REG> = crate::BitWriter<'a, REG, Ptso3>; -impl<'a, REG> Ptso3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso3::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso3::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso4 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO4` reader - Port Set Output"] -pub type Ptso4R = crate::BitReader; -impl Ptso4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso4 { - match self.bits { - false => Ptso4::Ptso0, - true => Ptso4::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso4::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso4::Ptso1 - } -} -#[doc = "Field `PTSO4` writer - Port Set Output"] -pub type Ptso4W<'a, REG> = crate::BitWriter<'a, REG, Ptso4>; -impl<'a, REG> Ptso4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso4::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso4::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso5 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO5` reader - Port Set Output"] -pub type Ptso5R = crate::BitReader; -impl Ptso5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso5 { - match self.bits { - false => Ptso5::Ptso0, - true => Ptso5::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso5::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso5::Ptso1 - } -} -#[doc = "Field `PTSO5` writer - Port Set Output"] -pub type Ptso5W<'a, REG> = crate::BitWriter<'a, REG, Ptso5>; -impl<'a, REG> Ptso5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso5::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso5::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso6 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO6` reader - Port Set Output"] -pub type Ptso6R = crate::BitReader; -impl Ptso6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso6 { - match self.bits { - false => Ptso6::Ptso0, - true => Ptso6::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso6::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso6::Ptso1 - } -} -#[doc = "Field `PTSO6` writer - Port Set Output"] -pub type Ptso6W<'a, REG> = crate::BitWriter<'a, REG, Ptso6>; -impl<'a, REG> Ptso6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso6::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso6::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso7 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO7` reader - Port Set Output"] -pub type Ptso7R = crate::BitReader; -impl Ptso7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso7 { - match self.bits { - false => Ptso7::Ptso0, - true => Ptso7::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso7::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso7::Ptso1 - } -} -#[doc = "Field `PTSO7` writer - Port Set Output"] -pub type Ptso7W<'a, REG> = crate::BitWriter<'a, REG, Ptso7>; -impl<'a, REG> Ptso7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso7::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso7::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso8 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO8` reader - Port Set Output"] -pub type Ptso8R = crate::BitReader; -impl Ptso8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso8 { - match self.bits { - false => Ptso8::Ptso0, - true => Ptso8::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso8::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso8::Ptso1 - } -} -#[doc = "Field `PTSO8` writer - Port Set Output"] -pub type Ptso8W<'a, REG> = crate::BitWriter<'a, REG, Ptso8>; -impl<'a, REG> Ptso8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso8::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso8::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso9 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO9` reader - Port Set Output"] -pub type Ptso9R = crate::BitReader; -impl Ptso9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso9 { - match self.bits { - false => Ptso9::Ptso0, - true => Ptso9::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso9::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso9::Ptso1 - } -} -#[doc = "Field `PTSO9` writer - Port Set Output"] -pub type Ptso9W<'a, REG> = crate::BitWriter<'a, REG, Ptso9>; -impl<'a, REG> Ptso9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso9::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso9::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso10 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO10` reader - Port Set Output"] -pub type Ptso10R = crate::BitReader; -impl Ptso10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso10 { - match self.bits { - false => Ptso10::Ptso0, - true => Ptso10::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso10::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso10::Ptso1 - } -} -#[doc = "Field `PTSO10` writer - Port Set Output"] -pub type Ptso10W<'a, REG> = crate::BitWriter<'a, REG, Ptso10>; -impl<'a, REG> Ptso10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso10::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso10::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso11 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO11` reader - Port Set Output"] -pub type Ptso11R = crate::BitReader; -impl Ptso11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso11 { - match self.bits { - false => Ptso11::Ptso0, - true => Ptso11::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso11::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso11::Ptso1 - } -} -#[doc = "Field `PTSO11` writer - Port Set Output"] -pub type Ptso11W<'a, REG> = crate::BitWriter<'a, REG, Ptso11>; -impl<'a, REG> Ptso11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso11::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso11::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso12 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO12` reader - Port Set Output"] -pub type Ptso12R = crate::BitReader; -impl Ptso12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso12 { - match self.bits { - false => Ptso12::Ptso0, - true => Ptso12::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso12::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso12::Ptso1 - } -} -#[doc = "Field `PTSO12` writer - Port Set Output"] -pub type Ptso12W<'a, REG> = crate::BitWriter<'a, REG, Ptso12>; -impl<'a, REG> Ptso12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso12::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso12::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso13 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO13` reader - Port Set Output"] -pub type Ptso13R = crate::BitReader; -impl Ptso13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso13 { - match self.bits { - false => Ptso13::Ptso0, - true => Ptso13::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso13::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso13::Ptso1 - } -} -#[doc = "Field `PTSO13` writer - Port Set Output"] -pub type Ptso13W<'a, REG> = crate::BitWriter<'a, REG, Ptso13>; -impl<'a, REG> Ptso13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso13::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso13::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso14 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO14` reader - Port Set Output"] -pub type Ptso14R = crate::BitReader; -impl Ptso14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso14 { - match self.bits { - false => Ptso14::Ptso0, - true => Ptso14::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso14::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso14::Ptso1 - } -} -#[doc = "Field `PTSO14` writer - Port Set Output"] -pub type Ptso14W<'a, REG> = crate::BitWriter<'a, REG, Ptso14>; -impl<'a, REG> Ptso14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso14::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso14::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso15 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO15` reader - Port Set Output"] -pub type Ptso15R = crate::BitReader; -impl Ptso15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso15 { - match self.bits { - false => Ptso15::Ptso0, - true => Ptso15::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso15::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso15::Ptso1 - } -} -#[doc = "Field `PTSO15` writer - Port Set Output"] -pub type Ptso15W<'a, REG> = crate::BitWriter<'a, REG, Ptso15>; -impl<'a, REG> Ptso15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso15::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso15::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso16 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO16` reader - Port Set Output"] -pub type Ptso16R = crate::BitReader; -impl Ptso16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso16 { - match self.bits { - false => Ptso16::Ptso0, - true => Ptso16::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso16::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso16::Ptso1 - } -} -#[doc = "Field `PTSO16` writer - Port Set Output"] -pub type Ptso16W<'a, REG> = crate::BitWriter<'a, REG, Ptso16>; -impl<'a, REG> Ptso16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso16::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso16::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso17 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO17` reader - Port Set Output"] -pub type Ptso17R = crate::BitReader; -impl Ptso17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso17 { - match self.bits { - false => Ptso17::Ptso0, - true => Ptso17::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso17::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso17::Ptso1 - } -} -#[doc = "Field `PTSO17` writer - Port Set Output"] -pub type Ptso17W<'a, REG> = crate::BitWriter<'a, REG, Ptso17>; -impl<'a, REG> Ptso17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso17::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso17::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso18 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO18` reader - Port Set Output"] -pub type Ptso18R = crate::BitReader; -impl Ptso18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso18 { - match self.bits { - false => Ptso18::Ptso0, - true => Ptso18::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso18::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso18::Ptso1 - } -} -#[doc = "Field `PTSO18` writer - Port Set Output"] -pub type Ptso18W<'a, REG> = crate::BitWriter<'a, REG, Ptso18>; -impl<'a, REG> Ptso18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso18::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso18::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso19 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO19` reader - Port Set Output"] -pub type Ptso19R = crate::BitReader; -impl Ptso19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso19 { - match self.bits { - false => Ptso19::Ptso0, - true => Ptso19::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso19::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso19::Ptso1 - } -} -#[doc = "Field `PTSO19` writer - Port Set Output"] -pub type Ptso19W<'a, REG> = crate::BitWriter<'a, REG, Ptso19>; -impl<'a, REG> Ptso19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso19::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso19::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso20 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO20` reader - Port Set Output"] -pub type Ptso20R = crate::BitReader; -impl Ptso20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso20 { - match self.bits { - false => Ptso20::Ptso0, - true => Ptso20::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso20::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso20::Ptso1 - } -} -#[doc = "Field `PTSO20` writer - Port Set Output"] -pub type Ptso20W<'a, REG> = crate::BitWriter<'a, REG, Ptso20>; -impl<'a, REG> Ptso20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso20::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso20::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso21 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO21` reader - Port Set Output"] -pub type Ptso21R = crate::BitReader; -impl Ptso21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso21 { - match self.bits { - false => Ptso21::Ptso0, - true => Ptso21::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso21::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso21::Ptso1 - } -} -#[doc = "Field `PTSO21` writer - Port Set Output"] -pub type Ptso21W<'a, REG> = crate::BitWriter<'a, REG, Ptso21>; -impl<'a, REG> Ptso21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso21::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso21::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso22 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO22` reader - Port Set Output"] -pub type Ptso22R = crate::BitReader; -impl Ptso22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso22 { - match self.bits { - false => Ptso22::Ptso0, - true => Ptso22::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso22::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso22::Ptso1 - } -} -#[doc = "Field `PTSO22` writer - Port Set Output"] -pub type Ptso22W<'a, REG> = crate::BitWriter<'a, REG, Ptso22>; -impl<'a, REG> Ptso22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso22::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso22::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso23 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO23` reader - Port Set Output"] -pub type Ptso23R = crate::BitReader; -impl Ptso23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso23 { - match self.bits { - false => Ptso23::Ptso0, - true => Ptso23::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso23::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso23::Ptso1 - } -} -#[doc = "Field `PTSO23` writer - Port Set Output"] -pub type Ptso23W<'a, REG> = crate::BitWriter<'a, REG, Ptso23>; -impl<'a, REG> Ptso23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso23::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso23::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso24 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO24` reader - Port Set Output"] -pub type Ptso24R = crate::BitReader; -impl Ptso24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso24 { - match self.bits { - false => Ptso24::Ptso0, - true => Ptso24::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso24::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso24::Ptso1 - } -} -#[doc = "Field `PTSO24` writer - Port Set Output"] -pub type Ptso24W<'a, REG> = crate::BitWriter<'a, REG, Ptso24>; -impl<'a, REG> Ptso24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso24::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso24::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso25 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO25` reader - Port Set Output"] -pub type Ptso25R = crate::BitReader; -impl Ptso25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso25 { - match self.bits { - false => Ptso25::Ptso0, - true => Ptso25::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso25::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso25::Ptso1 - } -} -#[doc = "Field `PTSO25` writer - Port Set Output"] -pub type Ptso25W<'a, REG> = crate::BitWriter<'a, REG, Ptso25>; -impl<'a, REG> Ptso25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso25::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso25::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso26 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO26` reader - Port Set Output"] -pub type Ptso26R = crate::BitReader; -impl Ptso26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso26 { - match self.bits { - false => Ptso26::Ptso0, - true => Ptso26::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso26::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso26::Ptso1 - } -} -#[doc = "Field `PTSO26` writer - Port Set Output"] -pub type Ptso26W<'a, REG> = crate::BitWriter<'a, REG, Ptso26>; -impl<'a, REG> Ptso26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso26::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso26::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso27 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO27` reader - Port Set Output"] -pub type Ptso27R = crate::BitReader; -impl Ptso27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso27 { - match self.bits { - false => Ptso27::Ptso0, - true => Ptso27::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso27::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso27::Ptso1 - } -} -#[doc = "Field `PTSO27` writer - Port Set Output"] -pub type Ptso27W<'a, REG> = crate::BitWriter<'a, REG, Ptso27>; -impl<'a, REG> Ptso27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso27::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso27::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso28 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO28` reader - Port Set Output"] -pub type Ptso28R = crate::BitReader; -impl Ptso28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso28 { - match self.bits { - false => Ptso28::Ptso0, - true => Ptso28::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso28::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso28::Ptso1 - } -} -#[doc = "Field `PTSO28` writer - Port Set Output"] -pub type Ptso28W<'a, REG> = crate::BitWriter<'a, REG, Ptso28>; -impl<'a, REG> Ptso28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso28::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso28::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso29 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO29` reader - Port Set Output"] -pub type Ptso29R = crate::BitReader; -impl Ptso29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso29 { - match self.bits { - false => Ptso29::Ptso0, - true => Ptso29::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso29::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso29::Ptso1 - } -} -#[doc = "Field `PTSO29` writer - Port Set Output"] -pub type Ptso29W<'a, REG> = crate::BitWriter<'a, REG, Ptso29>; -impl<'a, REG> Ptso29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso29::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso29::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso30 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO30` reader - Port Set Output"] -pub type Ptso30R = crate::BitReader; -impl Ptso30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso30 { - match self.bits { - false => Ptso30::Ptso0, - true => Ptso30::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso30::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso30::Ptso1 - } -} -#[doc = "Field `PTSO30` writer - Port Set Output"] -pub type Ptso30W<'a, REG> = crate::BitWriter<'a, REG, Ptso30>; -impl<'a, REG> Ptso30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso30::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso30::Ptso1) - } -} -#[doc = "Port Set Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptso31 { - #[doc = "0: No change"] - Ptso0 = 0, - #[doc = "1: Corresponding field in PDOR becomes 1"] - Ptso1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptso31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTSO31` reader - Port Set Output"] -pub type Ptso31R = crate::BitReader; -impl Ptso31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptso31 { - match self.bits { - false => Ptso31::Ptso0, - true => Ptso31::Ptso1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptso0(&self) -> bool { - *self == Ptso31::Ptso0 - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn is_ptso1(&self) -> bool { - *self == Ptso31::Ptso1 - } -} -#[doc = "Field `PTSO31` writer - Port Set Output"] -pub type Ptso31W<'a, REG> = crate::BitWriter<'a, REG, Ptso31>; -impl<'a, REG> Ptso31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptso0(self) -> &'a mut crate::W { - self.variant(Ptso31::Ptso0) - } - #[doc = "Corresponding field in PDOR becomes 1"] - #[inline(always)] - pub fn ptso1(self) -> &'a mut crate::W { - self.variant(Ptso31::Ptso1) - } -} -impl R { - #[doc = "Bit 0 - Port Set Output"] - #[inline(always)] - pub fn ptso0(&self) -> Ptso0R { - Ptso0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Port Set Output"] - #[inline(always)] - pub fn ptso1(&self) -> Ptso1R { - Ptso1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Port Set Output"] - #[inline(always)] - pub fn ptso2(&self) -> Ptso2R { - Ptso2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Port Set Output"] - #[inline(always)] - pub fn ptso3(&self) -> Ptso3R { - Ptso3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Port Set Output"] - #[inline(always)] - pub fn ptso4(&self) -> Ptso4R { - Ptso4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Port Set Output"] - #[inline(always)] - pub fn ptso5(&self) -> Ptso5R { - Ptso5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Port Set Output"] - #[inline(always)] - pub fn ptso6(&self) -> Ptso6R { - Ptso6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Port Set Output"] - #[inline(always)] - pub fn ptso7(&self) -> Ptso7R { - Ptso7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Port Set Output"] - #[inline(always)] - pub fn ptso8(&self) -> Ptso8R { - Ptso8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Port Set Output"] - #[inline(always)] - pub fn ptso9(&self) -> Ptso9R { - Ptso9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Port Set Output"] - #[inline(always)] - pub fn ptso10(&self) -> Ptso10R { - Ptso10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Port Set Output"] - #[inline(always)] - pub fn ptso11(&self) -> Ptso11R { - Ptso11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Port Set Output"] - #[inline(always)] - pub fn ptso12(&self) -> Ptso12R { - Ptso12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Port Set Output"] - #[inline(always)] - pub fn ptso13(&self) -> Ptso13R { - Ptso13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Port Set Output"] - #[inline(always)] - pub fn ptso14(&self) -> Ptso14R { - Ptso14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Port Set Output"] - #[inline(always)] - pub fn ptso15(&self) -> Ptso15R { - Ptso15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Port Set Output"] - #[inline(always)] - pub fn ptso16(&self) -> Ptso16R { - Ptso16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Port Set Output"] - #[inline(always)] - pub fn ptso17(&self) -> Ptso17R { - Ptso17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Port Set Output"] - #[inline(always)] - pub fn ptso18(&self) -> Ptso18R { - Ptso18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Port Set Output"] - #[inline(always)] - pub fn ptso19(&self) -> Ptso19R { - Ptso19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Port Set Output"] - #[inline(always)] - pub fn ptso20(&self) -> Ptso20R { - Ptso20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Port Set Output"] - #[inline(always)] - pub fn ptso21(&self) -> Ptso21R { - Ptso21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Port Set Output"] - #[inline(always)] - pub fn ptso22(&self) -> Ptso22R { - Ptso22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Port Set Output"] - #[inline(always)] - pub fn ptso23(&self) -> Ptso23R { - Ptso23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Port Set Output"] - #[inline(always)] - pub fn ptso24(&self) -> Ptso24R { - Ptso24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Port Set Output"] - #[inline(always)] - pub fn ptso25(&self) -> Ptso25R { - Ptso25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Port Set Output"] - #[inline(always)] - pub fn ptso26(&self) -> Ptso26R { - Ptso26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Port Set Output"] - #[inline(always)] - pub fn ptso27(&self) -> Ptso27R { - Ptso27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Port Set Output"] - #[inline(always)] - pub fn ptso28(&self) -> Ptso28R { - Ptso28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Port Set Output"] - #[inline(always)] - pub fn ptso29(&self) -> Ptso29R { - Ptso29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Port Set Output"] - #[inline(always)] - pub fn ptso30(&self) -> Ptso30R { - Ptso30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Port Set Output"] - #[inline(always)] - pub fn ptso31(&self) -> Ptso31R { - Ptso31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Set Output"] - #[inline(always)] - pub fn ptso0(&mut self) -> Ptso0W { - Ptso0W::new(self, 0) - } - #[doc = "Bit 1 - Port Set Output"] - #[inline(always)] - pub fn ptso1(&mut self) -> Ptso1W { - Ptso1W::new(self, 1) - } - #[doc = "Bit 2 - Port Set Output"] - #[inline(always)] - pub fn ptso2(&mut self) -> Ptso2W { - Ptso2W::new(self, 2) - } - #[doc = "Bit 3 - Port Set Output"] - #[inline(always)] - pub fn ptso3(&mut self) -> Ptso3W { - Ptso3W::new(self, 3) - } - #[doc = "Bit 4 - Port Set Output"] - #[inline(always)] - pub fn ptso4(&mut self) -> Ptso4W { - Ptso4W::new(self, 4) - } - #[doc = "Bit 5 - Port Set Output"] - #[inline(always)] - pub fn ptso5(&mut self) -> Ptso5W { - Ptso5W::new(self, 5) - } - #[doc = "Bit 6 - Port Set Output"] - #[inline(always)] - pub fn ptso6(&mut self) -> Ptso6W { - Ptso6W::new(self, 6) - } - #[doc = "Bit 7 - Port Set Output"] - #[inline(always)] - pub fn ptso7(&mut self) -> Ptso7W { - Ptso7W::new(self, 7) - } - #[doc = "Bit 8 - Port Set Output"] - #[inline(always)] - pub fn ptso8(&mut self) -> Ptso8W { - Ptso8W::new(self, 8) - } - #[doc = "Bit 9 - Port Set Output"] - #[inline(always)] - pub fn ptso9(&mut self) -> Ptso9W { - Ptso9W::new(self, 9) - } - #[doc = "Bit 10 - Port Set Output"] - #[inline(always)] - pub fn ptso10(&mut self) -> Ptso10W { - Ptso10W::new(self, 10) - } - #[doc = "Bit 11 - Port Set Output"] - #[inline(always)] - pub fn ptso11(&mut self) -> Ptso11W { - Ptso11W::new(self, 11) - } - #[doc = "Bit 12 - Port Set Output"] - #[inline(always)] - pub fn ptso12(&mut self) -> Ptso12W { - Ptso12W::new(self, 12) - } - #[doc = "Bit 13 - Port Set Output"] - #[inline(always)] - pub fn ptso13(&mut self) -> Ptso13W { - Ptso13W::new(self, 13) - } - #[doc = "Bit 14 - Port Set Output"] - #[inline(always)] - pub fn ptso14(&mut self) -> Ptso14W { - Ptso14W::new(self, 14) - } - #[doc = "Bit 15 - Port Set Output"] - #[inline(always)] - pub fn ptso15(&mut self) -> Ptso15W { - Ptso15W::new(self, 15) - } - #[doc = "Bit 16 - Port Set Output"] - #[inline(always)] - pub fn ptso16(&mut self) -> Ptso16W { - Ptso16W::new(self, 16) - } - #[doc = "Bit 17 - Port Set Output"] - #[inline(always)] - pub fn ptso17(&mut self) -> Ptso17W { - Ptso17W::new(self, 17) - } - #[doc = "Bit 18 - Port Set Output"] - #[inline(always)] - pub fn ptso18(&mut self) -> Ptso18W { - Ptso18W::new(self, 18) - } - #[doc = "Bit 19 - Port Set Output"] - #[inline(always)] - pub fn ptso19(&mut self) -> Ptso19W { - Ptso19W::new(self, 19) - } - #[doc = "Bit 20 - Port Set Output"] - #[inline(always)] - pub fn ptso20(&mut self) -> Ptso20W { - Ptso20W::new(self, 20) - } - #[doc = "Bit 21 - Port Set Output"] - #[inline(always)] - pub fn ptso21(&mut self) -> Ptso21W { - Ptso21W::new(self, 21) - } - #[doc = "Bit 22 - Port Set Output"] - #[inline(always)] - pub fn ptso22(&mut self) -> Ptso22W { - Ptso22W::new(self, 22) - } - #[doc = "Bit 23 - Port Set Output"] - #[inline(always)] - pub fn ptso23(&mut self) -> Ptso23W { - Ptso23W::new(self, 23) - } - #[doc = "Bit 24 - Port Set Output"] - #[inline(always)] - pub fn ptso24(&mut self) -> Ptso24W { - Ptso24W::new(self, 24) - } - #[doc = "Bit 25 - Port Set Output"] - #[inline(always)] - pub fn ptso25(&mut self) -> Ptso25W { - Ptso25W::new(self, 25) - } - #[doc = "Bit 26 - Port Set Output"] - #[inline(always)] - pub fn ptso26(&mut self) -> Ptso26W { - Ptso26W::new(self, 26) - } - #[doc = "Bit 27 - Port Set Output"] - #[inline(always)] - pub fn ptso27(&mut self) -> Ptso27W { - Ptso27W::new(self, 27) - } - #[doc = "Bit 28 - Port Set Output"] - #[inline(always)] - pub fn ptso28(&mut self) -> Ptso28W { - Ptso28W::new(self, 28) - } - #[doc = "Bit 29 - Port Set Output"] - #[inline(always)] - pub fn ptso29(&mut self) -> Ptso29W { - Ptso29W::new(self, 29) - } - #[doc = "Bit 30 - Port Set Output"] - #[inline(always)] - pub fn ptso30(&mut self) -> Ptso30W { - Ptso30W::new(self, 30) - } - #[doc = "Bit 31 - Port Set Output"] - #[inline(always)] - pub fn ptso31(&mut self) -> Ptso31W { - Ptso31W::new(self, 31) - } -} -#[doc = "Port Set Output\n\nYou can [`read`](crate::Reg::read) this register and get [`psor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PsorSpec; -impl crate::RegisterSpec for PsorSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`psor::R`](R) reader structure"] -impl crate::Readable for PsorSpec {} -#[doc = "`write(|w| ..)` method takes [`psor::W`](W) writer structure"] -impl crate::Writable for PsorSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PSOR to value 0"] -impl crate::Resettable for PsorSpec {} diff --git a/mcxa276-pac/src/gpio0/ptor.rs b/mcxa276-pac/src/gpio0/ptor.rs deleted file mode 100644 index fda81c765..000000000 --- a/mcxa276-pac/src/gpio0/ptor.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `PTOR` reader"] -pub type R = crate::R; -#[doc = "Register `PTOR` writer"] -pub type W = crate::W; -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto0 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO0` reader - Port Toggle Output"] -pub type Ptto0R = crate::BitReader; -impl Ptto0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto0 { - match self.bits { - false => Ptto0::Ptto0, - true => Ptto0::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto0::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto0::Ptto1 - } -} -#[doc = "Field `PTTO0` writer - Port Toggle Output"] -pub type Ptto0W<'a, REG> = crate::BitWriter<'a, REG, Ptto0>; -impl<'a, REG> Ptto0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto0::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto0::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto1 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO1` reader - Port Toggle Output"] -pub type Ptto1R = crate::BitReader; -impl Ptto1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto1 { - match self.bits { - false => Ptto1::Ptto0, - true => Ptto1::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto1::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto1::Ptto1 - } -} -#[doc = "Field `PTTO1` writer - Port Toggle Output"] -pub type Ptto1W<'a, REG> = crate::BitWriter<'a, REG, Ptto1>; -impl<'a, REG> Ptto1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto1::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto1::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto2 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO2` reader - Port Toggle Output"] -pub type Ptto2R = crate::BitReader; -impl Ptto2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto2 { - match self.bits { - false => Ptto2::Ptto0, - true => Ptto2::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto2::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto2::Ptto1 - } -} -#[doc = "Field `PTTO2` writer - Port Toggle Output"] -pub type Ptto2W<'a, REG> = crate::BitWriter<'a, REG, Ptto2>; -impl<'a, REG> Ptto2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto2::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto2::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto3 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO3` reader - Port Toggle Output"] -pub type Ptto3R = crate::BitReader; -impl Ptto3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto3 { - match self.bits { - false => Ptto3::Ptto0, - true => Ptto3::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto3::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto3::Ptto1 - } -} -#[doc = "Field `PTTO3` writer - Port Toggle Output"] -pub type Ptto3W<'a, REG> = crate::BitWriter<'a, REG, Ptto3>; -impl<'a, REG> Ptto3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto3::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto3::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto4 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO4` reader - Port Toggle Output"] -pub type Ptto4R = crate::BitReader; -impl Ptto4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto4 { - match self.bits { - false => Ptto4::Ptto0, - true => Ptto4::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto4::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto4::Ptto1 - } -} -#[doc = "Field `PTTO4` writer - Port Toggle Output"] -pub type Ptto4W<'a, REG> = crate::BitWriter<'a, REG, Ptto4>; -impl<'a, REG> Ptto4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto4::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto4::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto5 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO5` reader - Port Toggle Output"] -pub type Ptto5R = crate::BitReader; -impl Ptto5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto5 { - match self.bits { - false => Ptto5::Ptto0, - true => Ptto5::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto5::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto5::Ptto1 - } -} -#[doc = "Field `PTTO5` writer - Port Toggle Output"] -pub type Ptto5W<'a, REG> = crate::BitWriter<'a, REG, Ptto5>; -impl<'a, REG> Ptto5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto5::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto5::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto6 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO6` reader - Port Toggle Output"] -pub type Ptto6R = crate::BitReader; -impl Ptto6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto6 { - match self.bits { - false => Ptto6::Ptto0, - true => Ptto6::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto6::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto6::Ptto1 - } -} -#[doc = "Field `PTTO6` writer - Port Toggle Output"] -pub type Ptto6W<'a, REG> = crate::BitWriter<'a, REG, Ptto6>; -impl<'a, REG> Ptto6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto6::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto6::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto7 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO7` reader - Port Toggle Output"] -pub type Ptto7R = crate::BitReader; -impl Ptto7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto7 { - match self.bits { - false => Ptto7::Ptto0, - true => Ptto7::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto7::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto7::Ptto1 - } -} -#[doc = "Field `PTTO7` writer - Port Toggle Output"] -pub type Ptto7W<'a, REG> = crate::BitWriter<'a, REG, Ptto7>; -impl<'a, REG> Ptto7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto7::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto7::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto8 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO8` reader - Port Toggle Output"] -pub type Ptto8R = crate::BitReader; -impl Ptto8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto8 { - match self.bits { - false => Ptto8::Ptto0, - true => Ptto8::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto8::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto8::Ptto1 - } -} -#[doc = "Field `PTTO8` writer - Port Toggle Output"] -pub type Ptto8W<'a, REG> = crate::BitWriter<'a, REG, Ptto8>; -impl<'a, REG> Ptto8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto8::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto8::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto9 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO9` reader - Port Toggle Output"] -pub type Ptto9R = crate::BitReader; -impl Ptto9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto9 { - match self.bits { - false => Ptto9::Ptto0, - true => Ptto9::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto9::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto9::Ptto1 - } -} -#[doc = "Field `PTTO9` writer - Port Toggle Output"] -pub type Ptto9W<'a, REG> = crate::BitWriter<'a, REG, Ptto9>; -impl<'a, REG> Ptto9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto9::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto9::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto10 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO10` reader - Port Toggle Output"] -pub type Ptto10R = crate::BitReader; -impl Ptto10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto10 { - match self.bits { - false => Ptto10::Ptto0, - true => Ptto10::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto10::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto10::Ptto1 - } -} -#[doc = "Field `PTTO10` writer - Port Toggle Output"] -pub type Ptto10W<'a, REG> = crate::BitWriter<'a, REG, Ptto10>; -impl<'a, REG> Ptto10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto10::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto10::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto11 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO11` reader - Port Toggle Output"] -pub type Ptto11R = crate::BitReader; -impl Ptto11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto11 { - match self.bits { - false => Ptto11::Ptto0, - true => Ptto11::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto11::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto11::Ptto1 - } -} -#[doc = "Field `PTTO11` writer - Port Toggle Output"] -pub type Ptto11W<'a, REG> = crate::BitWriter<'a, REG, Ptto11>; -impl<'a, REG> Ptto11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto11::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto11::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto12 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO12` reader - Port Toggle Output"] -pub type Ptto12R = crate::BitReader; -impl Ptto12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto12 { - match self.bits { - false => Ptto12::Ptto0, - true => Ptto12::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto12::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto12::Ptto1 - } -} -#[doc = "Field `PTTO12` writer - Port Toggle Output"] -pub type Ptto12W<'a, REG> = crate::BitWriter<'a, REG, Ptto12>; -impl<'a, REG> Ptto12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto12::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto12::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto13 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO13` reader - Port Toggle Output"] -pub type Ptto13R = crate::BitReader; -impl Ptto13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto13 { - match self.bits { - false => Ptto13::Ptto0, - true => Ptto13::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto13::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto13::Ptto1 - } -} -#[doc = "Field `PTTO13` writer - Port Toggle Output"] -pub type Ptto13W<'a, REG> = crate::BitWriter<'a, REG, Ptto13>; -impl<'a, REG> Ptto13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto13::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto13::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto14 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO14` reader - Port Toggle Output"] -pub type Ptto14R = crate::BitReader; -impl Ptto14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto14 { - match self.bits { - false => Ptto14::Ptto0, - true => Ptto14::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto14::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto14::Ptto1 - } -} -#[doc = "Field `PTTO14` writer - Port Toggle Output"] -pub type Ptto14W<'a, REG> = crate::BitWriter<'a, REG, Ptto14>; -impl<'a, REG> Ptto14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto14::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto14::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto15 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO15` reader - Port Toggle Output"] -pub type Ptto15R = crate::BitReader; -impl Ptto15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto15 { - match self.bits { - false => Ptto15::Ptto0, - true => Ptto15::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto15::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto15::Ptto1 - } -} -#[doc = "Field `PTTO15` writer - Port Toggle Output"] -pub type Ptto15W<'a, REG> = crate::BitWriter<'a, REG, Ptto15>; -impl<'a, REG> Ptto15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto15::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto15::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto16 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO16` reader - Port Toggle Output"] -pub type Ptto16R = crate::BitReader; -impl Ptto16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto16 { - match self.bits { - false => Ptto16::Ptto0, - true => Ptto16::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto16::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto16::Ptto1 - } -} -#[doc = "Field `PTTO16` writer - Port Toggle Output"] -pub type Ptto16W<'a, REG> = crate::BitWriter<'a, REG, Ptto16>; -impl<'a, REG> Ptto16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto16::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto16::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto17 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO17` reader - Port Toggle Output"] -pub type Ptto17R = crate::BitReader; -impl Ptto17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto17 { - match self.bits { - false => Ptto17::Ptto0, - true => Ptto17::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto17::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto17::Ptto1 - } -} -#[doc = "Field `PTTO17` writer - Port Toggle Output"] -pub type Ptto17W<'a, REG> = crate::BitWriter<'a, REG, Ptto17>; -impl<'a, REG> Ptto17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto17::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto17::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto18 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO18` reader - Port Toggle Output"] -pub type Ptto18R = crate::BitReader; -impl Ptto18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto18 { - match self.bits { - false => Ptto18::Ptto0, - true => Ptto18::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto18::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto18::Ptto1 - } -} -#[doc = "Field `PTTO18` writer - Port Toggle Output"] -pub type Ptto18W<'a, REG> = crate::BitWriter<'a, REG, Ptto18>; -impl<'a, REG> Ptto18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto18::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto18::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto19 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO19` reader - Port Toggle Output"] -pub type Ptto19R = crate::BitReader; -impl Ptto19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto19 { - match self.bits { - false => Ptto19::Ptto0, - true => Ptto19::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto19::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto19::Ptto1 - } -} -#[doc = "Field `PTTO19` writer - Port Toggle Output"] -pub type Ptto19W<'a, REG> = crate::BitWriter<'a, REG, Ptto19>; -impl<'a, REG> Ptto19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto19::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto19::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto20 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO20` reader - Port Toggle Output"] -pub type Ptto20R = crate::BitReader; -impl Ptto20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto20 { - match self.bits { - false => Ptto20::Ptto0, - true => Ptto20::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto20::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto20::Ptto1 - } -} -#[doc = "Field `PTTO20` writer - Port Toggle Output"] -pub type Ptto20W<'a, REG> = crate::BitWriter<'a, REG, Ptto20>; -impl<'a, REG> Ptto20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto20::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto20::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto21 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO21` reader - Port Toggle Output"] -pub type Ptto21R = crate::BitReader; -impl Ptto21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto21 { - match self.bits { - false => Ptto21::Ptto0, - true => Ptto21::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto21::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto21::Ptto1 - } -} -#[doc = "Field `PTTO21` writer - Port Toggle Output"] -pub type Ptto21W<'a, REG> = crate::BitWriter<'a, REG, Ptto21>; -impl<'a, REG> Ptto21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto21::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto21::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto22 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO22` reader - Port Toggle Output"] -pub type Ptto22R = crate::BitReader; -impl Ptto22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto22 { - match self.bits { - false => Ptto22::Ptto0, - true => Ptto22::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto22::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto22::Ptto1 - } -} -#[doc = "Field `PTTO22` writer - Port Toggle Output"] -pub type Ptto22W<'a, REG> = crate::BitWriter<'a, REG, Ptto22>; -impl<'a, REG> Ptto22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto22::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto22::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto23 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO23` reader - Port Toggle Output"] -pub type Ptto23R = crate::BitReader; -impl Ptto23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto23 { - match self.bits { - false => Ptto23::Ptto0, - true => Ptto23::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto23::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto23::Ptto1 - } -} -#[doc = "Field `PTTO23` writer - Port Toggle Output"] -pub type Ptto23W<'a, REG> = crate::BitWriter<'a, REG, Ptto23>; -impl<'a, REG> Ptto23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto23::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto23::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto24 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO24` reader - Port Toggle Output"] -pub type Ptto24R = crate::BitReader; -impl Ptto24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto24 { - match self.bits { - false => Ptto24::Ptto0, - true => Ptto24::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto24::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto24::Ptto1 - } -} -#[doc = "Field `PTTO24` writer - Port Toggle Output"] -pub type Ptto24W<'a, REG> = crate::BitWriter<'a, REG, Ptto24>; -impl<'a, REG> Ptto24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto24::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto24::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto25 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO25` reader - Port Toggle Output"] -pub type Ptto25R = crate::BitReader; -impl Ptto25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto25 { - match self.bits { - false => Ptto25::Ptto0, - true => Ptto25::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto25::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto25::Ptto1 - } -} -#[doc = "Field `PTTO25` writer - Port Toggle Output"] -pub type Ptto25W<'a, REG> = crate::BitWriter<'a, REG, Ptto25>; -impl<'a, REG> Ptto25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto25::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto25::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto26 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO26` reader - Port Toggle Output"] -pub type Ptto26R = crate::BitReader; -impl Ptto26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto26 { - match self.bits { - false => Ptto26::Ptto0, - true => Ptto26::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto26::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto26::Ptto1 - } -} -#[doc = "Field `PTTO26` writer - Port Toggle Output"] -pub type Ptto26W<'a, REG> = crate::BitWriter<'a, REG, Ptto26>; -impl<'a, REG> Ptto26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto26::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto26::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto27 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO27` reader - Port Toggle Output"] -pub type Ptto27R = crate::BitReader; -impl Ptto27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto27 { - match self.bits { - false => Ptto27::Ptto0, - true => Ptto27::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto27::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto27::Ptto1 - } -} -#[doc = "Field `PTTO27` writer - Port Toggle Output"] -pub type Ptto27W<'a, REG> = crate::BitWriter<'a, REG, Ptto27>; -impl<'a, REG> Ptto27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto27::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto27::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto28 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO28` reader - Port Toggle Output"] -pub type Ptto28R = crate::BitReader; -impl Ptto28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto28 { - match self.bits { - false => Ptto28::Ptto0, - true => Ptto28::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto28::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto28::Ptto1 - } -} -#[doc = "Field `PTTO28` writer - Port Toggle Output"] -pub type Ptto28W<'a, REG> = crate::BitWriter<'a, REG, Ptto28>; -impl<'a, REG> Ptto28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto28::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto28::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto29 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO29` reader - Port Toggle Output"] -pub type Ptto29R = crate::BitReader; -impl Ptto29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto29 { - match self.bits { - false => Ptto29::Ptto0, - true => Ptto29::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto29::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto29::Ptto1 - } -} -#[doc = "Field `PTTO29` writer - Port Toggle Output"] -pub type Ptto29W<'a, REG> = crate::BitWriter<'a, REG, Ptto29>; -impl<'a, REG> Ptto29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto29::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto29::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto30 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO30` reader - Port Toggle Output"] -pub type Ptto30R = crate::BitReader; -impl Ptto30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto30 { - match self.bits { - false => Ptto30::Ptto0, - true => Ptto30::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto30::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto30::Ptto1 - } -} -#[doc = "Field `PTTO30` writer - Port Toggle Output"] -pub type Ptto30W<'a, REG> = crate::BitWriter<'a, REG, Ptto30>; -impl<'a, REG> Ptto30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto30::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto30::Ptto1) - } -} -#[doc = "Port Toggle Output\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ptto31 { - #[doc = "0: No change"] - Ptto0 = 0, - #[doc = "1: Set to the inverse of its current logic state"] - Ptto1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ptto31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PTTO31` reader - Port Toggle Output"] -pub type Ptto31R = crate::BitReader; -impl Ptto31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ptto31 { - match self.bits { - false => Ptto31::Ptto0, - true => Ptto31::Ptto1, - } - } - #[doc = "No change"] - #[inline(always)] - pub fn is_ptto0(&self) -> bool { - *self == Ptto31::Ptto0 - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn is_ptto1(&self) -> bool { - *self == Ptto31::Ptto1 - } -} -#[doc = "Field `PTTO31` writer - Port Toggle Output"] -pub type Ptto31W<'a, REG> = crate::BitWriter<'a, REG, Ptto31>; -impl<'a, REG> Ptto31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No change"] - #[inline(always)] - pub fn ptto0(self) -> &'a mut crate::W { - self.variant(Ptto31::Ptto0) - } - #[doc = "Set to the inverse of its current logic state"] - #[inline(always)] - pub fn ptto1(self) -> &'a mut crate::W { - self.variant(Ptto31::Ptto1) - } -} -impl R { - #[doc = "Bit 0 - Port Toggle Output"] - #[inline(always)] - pub fn ptto0(&self) -> Ptto0R { - Ptto0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Port Toggle Output"] - #[inline(always)] - pub fn ptto1(&self) -> Ptto1R { - Ptto1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Port Toggle Output"] - #[inline(always)] - pub fn ptto2(&self) -> Ptto2R { - Ptto2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Port Toggle Output"] - #[inline(always)] - pub fn ptto3(&self) -> Ptto3R { - Ptto3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Port Toggle Output"] - #[inline(always)] - pub fn ptto4(&self) -> Ptto4R { - Ptto4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Port Toggle Output"] - #[inline(always)] - pub fn ptto5(&self) -> Ptto5R { - Ptto5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Port Toggle Output"] - #[inline(always)] - pub fn ptto6(&self) -> Ptto6R { - Ptto6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Port Toggle Output"] - #[inline(always)] - pub fn ptto7(&self) -> Ptto7R { - Ptto7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Port Toggle Output"] - #[inline(always)] - pub fn ptto8(&self) -> Ptto8R { - Ptto8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Port Toggle Output"] - #[inline(always)] - pub fn ptto9(&self) -> Ptto9R { - Ptto9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Port Toggle Output"] - #[inline(always)] - pub fn ptto10(&self) -> Ptto10R { - Ptto10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Port Toggle Output"] - #[inline(always)] - pub fn ptto11(&self) -> Ptto11R { - Ptto11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Port Toggle Output"] - #[inline(always)] - pub fn ptto12(&self) -> Ptto12R { - Ptto12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Port Toggle Output"] - #[inline(always)] - pub fn ptto13(&self) -> Ptto13R { - Ptto13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Port Toggle Output"] - #[inline(always)] - pub fn ptto14(&self) -> Ptto14R { - Ptto14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Port Toggle Output"] - #[inline(always)] - pub fn ptto15(&self) -> Ptto15R { - Ptto15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Port Toggle Output"] - #[inline(always)] - pub fn ptto16(&self) -> Ptto16R { - Ptto16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Port Toggle Output"] - #[inline(always)] - pub fn ptto17(&self) -> Ptto17R { - Ptto17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Port Toggle Output"] - #[inline(always)] - pub fn ptto18(&self) -> Ptto18R { - Ptto18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Port Toggle Output"] - #[inline(always)] - pub fn ptto19(&self) -> Ptto19R { - Ptto19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Port Toggle Output"] - #[inline(always)] - pub fn ptto20(&self) -> Ptto20R { - Ptto20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Port Toggle Output"] - #[inline(always)] - pub fn ptto21(&self) -> Ptto21R { - Ptto21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Port Toggle Output"] - #[inline(always)] - pub fn ptto22(&self) -> Ptto22R { - Ptto22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Port Toggle Output"] - #[inline(always)] - pub fn ptto23(&self) -> Ptto23R { - Ptto23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Port Toggle Output"] - #[inline(always)] - pub fn ptto24(&self) -> Ptto24R { - Ptto24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Port Toggle Output"] - #[inline(always)] - pub fn ptto25(&self) -> Ptto25R { - Ptto25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Port Toggle Output"] - #[inline(always)] - pub fn ptto26(&self) -> Ptto26R { - Ptto26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Port Toggle Output"] - #[inline(always)] - pub fn ptto27(&self) -> Ptto27R { - Ptto27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Port Toggle Output"] - #[inline(always)] - pub fn ptto28(&self) -> Ptto28R { - Ptto28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Port Toggle Output"] - #[inline(always)] - pub fn ptto29(&self) -> Ptto29R { - Ptto29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Port Toggle Output"] - #[inline(always)] - pub fn ptto30(&self) -> Ptto30R { - Ptto30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Port Toggle Output"] - #[inline(always)] - pub fn ptto31(&self) -> Ptto31R { - Ptto31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Toggle Output"] - #[inline(always)] - pub fn ptto0(&mut self) -> Ptto0W { - Ptto0W::new(self, 0) - } - #[doc = "Bit 1 - Port Toggle Output"] - #[inline(always)] - pub fn ptto1(&mut self) -> Ptto1W { - Ptto1W::new(self, 1) - } - #[doc = "Bit 2 - Port Toggle Output"] - #[inline(always)] - pub fn ptto2(&mut self) -> Ptto2W { - Ptto2W::new(self, 2) - } - #[doc = "Bit 3 - Port Toggle Output"] - #[inline(always)] - pub fn ptto3(&mut self) -> Ptto3W { - Ptto3W::new(self, 3) - } - #[doc = "Bit 4 - Port Toggle Output"] - #[inline(always)] - pub fn ptto4(&mut self) -> Ptto4W { - Ptto4W::new(self, 4) - } - #[doc = "Bit 5 - Port Toggle Output"] - #[inline(always)] - pub fn ptto5(&mut self) -> Ptto5W { - Ptto5W::new(self, 5) - } - #[doc = "Bit 6 - Port Toggle Output"] - #[inline(always)] - pub fn ptto6(&mut self) -> Ptto6W { - Ptto6W::new(self, 6) - } - #[doc = "Bit 7 - Port Toggle Output"] - #[inline(always)] - pub fn ptto7(&mut self) -> Ptto7W { - Ptto7W::new(self, 7) - } - #[doc = "Bit 8 - Port Toggle Output"] - #[inline(always)] - pub fn ptto8(&mut self) -> Ptto8W { - Ptto8W::new(self, 8) - } - #[doc = "Bit 9 - Port Toggle Output"] - #[inline(always)] - pub fn ptto9(&mut self) -> Ptto9W { - Ptto9W::new(self, 9) - } - #[doc = "Bit 10 - Port Toggle Output"] - #[inline(always)] - pub fn ptto10(&mut self) -> Ptto10W { - Ptto10W::new(self, 10) - } - #[doc = "Bit 11 - Port Toggle Output"] - #[inline(always)] - pub fn ptto11(&mut self) -> Ptto11W { - Ptto11W::new(self, 11) - } - #[doc = "Bit 12 - Port Toggle Output"] - #[inline(always)] - pub fn ptto12(&mut self) -> Ptto12W { - Ptto12W::new(self, 12) - } - #[doc = "Bit 13 - Port Toggle Output"] - #[inline(always)] - pub fn ptto13(&mut self) -> Ptto13W { - Ptto13W::new(self, 13) - } - #[doc = "Bit 14 - Port Toggle Output"] - #[inline(always)] - pub fn ptto14(&mut self) -> Ptto14W { - Ptto14W::new(self, 14) - } - #[doc = "Bit 15 - Port Toggle Output"] - #[inline(always)] - pub fn ptto15(&mut self) -> Ptto15W { - Ptto15W::new(self, 15) - } - #[doc = "Bit 16 - Port Toggle Output"] - #[inline(always)] - pub fn ptto16(&mut self) -> Ptto16W { - Ptto16W::new(self, 16) - } - #[doc = "Bit 17 - Port Toggle Output"] - #[inline(always)] - pub fn ptto17(&mut self) -> Ptto17W { - Ptto17W::new(self, 17) - } - #[doc = "Bit 18 - Port Toggle Output"] - #[inline(always)] - pub fn ptto18(&mut self) -> Ptto18W { - Ptto18W::new(self, 18) - } - #[doc = "Bit 19 - Port Toggle Output"] - #[inline(always)] - pub fn ptto19(&mut self) -> Ptto19W { - Ptto19W::new(self, 19) - } - #[doc = "Bit 20 - Port Toggle Output"] - #[inline(always)] - pub fn ptto20(&mut self) -> Ptto20W { - Ptto20W::new(self, 20) - } - #[doc = "Bit 21 - Port Toggle Output"] - #[inline(always)] - pub fn ptto21(&mut self) -> Ptto21W { - Ptto21W::new(self, 21) - } - #[doc = "Bit 22 - Port Toggle Output"] - #[inline(always)] - pub fn ptto22(&mut self) -> Ptto22W { - Ptto22W::new(self, 22) - } - #[doc = "Bit 23 - Port Toggle Output"] - #[inline(always)] - pub fn ptto23(&mut self) -> Ptto23W { - Ptto23W::new(self, 23) - } - #[doc = "Bit 24 - Port Toggle Output"] - #[inline(always)] - pub fn ptto24(&mut self) -> Ptto24W { - Ptto24W::new(self, 24) - } - #[doc = "Bit 25 - Port Toggle Output"] - #[inline(always)] - pub fn ptto25(&mut self) -> Ptto25W { - Ptto25W::new(self, 25) - } - #[doc = "Bit 26 - Port Toggle Output"] - #[inline(always)] - pub fn ptto26(&mut self) -> Ptto26W { - Ptto26W::new(self, 26) - } - #[doc = "Bit 27 - Port Toggle Output"] - #[inline(always)] - pub fn ptto27(&mut self) -> Ptto27W { - Ptto27W::new(self, 27) - } - #[doc = "Bit 28 - Port Toggle Output"] - #[inline(always)] - pub fn ptto28(&mut self) -> Ptto28W { - Ptto28W::new(self, 28) - } - #[doc = "Bit 29 - Port Toggle Output"] - #[inline(always)] - pub fn ptto29(&mut self) -> Ptto29W { - Ptto29W::new(self, 29) - } - #[doc = "Bit 30 - Port Toggle Output"] - #[inline(always)] - pub fn ptto30(&mut self) -> Ptto30W { - Ptto30W::new(self, 30) - } - #[doc = "Bit 31 - Port Toggle Output"] - #[inline(always)] - pub fn ptto31(&mut self) -> Ptto31W { - Ptto31W::new(self, 31) - } -} -#[doc = "Port Toggle Output\n\nYou can [`read`](crate::Reg::read) this register and get [`ptor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ptor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PtorSpec; -impl crate::RegisterSpec for PtorSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ptor::R`](R) reader structure"] -impl crate::Readable for PtorSpec {} -#[doc = "`write(|w| ..)` method takes [`ptor::W`](W) writer structure"] -impl crate::Writable for PtorSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PTOR to value 0"] -impl crate::Resettable for PtorSpec {} diff --git a/mcxa276-pac/src/gpio0/verid.rs b/mcxa276-pac/src/gpio0/verid.rs deleted file mode 100644 index 76e8a3874..000000000 --- a/mcxa276-pac/src/gpio0/verid.rs +++ /dev/null @@ -1,76 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Basic implementation"] - Feature0 = 0, - #[doc = "1: Protection registers implemented"] - Feature1 = 1, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Feature0), - 1 => Some(Feature::Feature1), - _ => None, - } - } - #[doc = "Basic implementation"] - #[inline(always)] - pub fn is_feature0(&self) -> bool { - *self == Feature::Feature0 - } - #[doc = "Protection registers implemented"] - #[inline(always)] - pub fn is_feature1(&self) -> bool { - *self == Feature::Feature1 - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0201_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0201_0000; -} diff --git a/mcxa276-pac/src/i3c0.rs b/mcxa276-pac/src/i3c0.rs deleted file mode 100644 index 31bb9d14b..000000000 --- a/mcxa276-pac/src/i3c0.rs +++ /dev/null @@ -1,639 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - mconfig: Mconfig, - sconfig: Sconfig, - sstatus: Sstatus, - sctrl: Sctrl, - sintset: Sintset, - sintclr: Sintclr, - sintmasked: Sintmasked, - serrwarn: Serrwarn, - sdmactrl: Sdmactrl, - _reserved9: [u8; 0x08], - sdatactrl: Sdatactrl, - swdatab: Swdatab, - swdatabe: Swdatabe, - swdatah: Swdatah, - swdatahe: Swdatahe, - srdatab: Srdatab, - _reserved15: [u8; 0x04], - srdatah: Srdatah, - _reserved16: [u8; 0x08], - _reserved_16_byte_swdatab1: [u8; 0x04], - _reserved17: [u8; 0x04], - scapabilities2: Scapabilities2, - scapabilities: Scapabilities, - sdynaddr: Sdynaddr, - smaxlimits: Smaxlimits, - sidpartno: Sidpartno, - sidext: Sidext, - svendorid: Svendorid, - stcclock: Stcclock, - smsgmapaddr: Smsgmapaddr, - mconfig_ext: MconfigExt, - mctrl: Mctrl, - mstatus: Mstatus, - mibirules: Mibirules, - mintset: Mintset, - mintclr: Mintclr, - mintmasked: Mintmasked, - merrwarn: Merrwarn, - mdmactrl: Mdmactrl, - _reserved35: [u8; 0x08], - mdatactrl: Mdatactrl, - mwdatab: Mwdatab, - mwdatabe: Mwdatabe, - mwdatah: Mwdatah, - mwdatahe: Mwdatahe, - mrdatab: Mrdatab, - _reserved41: [u8; 0x04], - mrdatah: Mrdatah, - _reserved_42_byte_mwdatab1: [u8; 0x04], - _reserved_43_data_mwmsg_sdr_data: [u8; 0x04], - mrmsg_sdr: MrmsgSdr, - _reserved_45_data_mwmsg_ddr_data: [u8; 0x04], - mrmsg_ddr: MrmsgDdr, - _reserved47: [u8; 0x04], - mdynaddr: Mdynaddr, - _reserved48: [u8; 0x34], - smapctrl0: Smapctrl0, - _reserved49: [u8; 0x20], - ibiext1: Ibiext1, - ibiext2: Ibiext2, - _reserved51: [u8; 0x0eb4], - sid: Sid, -} -impl RegisterBlock { - #[doc = "0x00 - Controller Configuration"] - #[inline(always)] - pub const fn mconfig(&self) -> &Mconfig { - &self.mconfig - } - #[doc = "0x04 - Target Configuration"] - #[inline(always)] - pub const fn sconfig(&self) -> &Sconfig { - &self.sconfig - } - #[doc = "0x08 - Target Status"] - #[inline(always)] - pub const fn sstatus(&self) -> &Sstatus { - &self.sstatus - } - #[doc = "0x0c - Target Control"] - #[inline(always)] - pub const fn sctrl(&self) -> &Sctrl { - &self.sctrl - } - #[doc = "0x10 - Target Interrupt Set"] - #[inline(always)] - pub const fn sintset(&self) -> &Sintset { - &self.sintset - } - #[doc = "0x14 - Target Interrupt Clear"] - #[inline(always)] - pub const fn sintclr(&self) -> &Sintclr { - &self.sintclr - } - #[doc = "0x18 - Target Interrupt Mask"] - #[inline(always)] - pub const fn sintmasked(&self) -> &Sintmasked { - &self.sintmasked - } - #[doc = "0x1c - Target Errors and Warnings"] - #[inline(always)] - pub const fn serrwarn(&self) -> &Serrwarn { - &self.serrwarn - } - #[doc = "0x20 - Target DMA Control"] - #[inline(always)] - pub const fn sdmactrl(&self) -> &Sdmactrl { - &self.sdmactrl - } - #[doc = "0x2c - Target Data Control"] - #[inline(always)] - pub const fn sdatactrl(&self) -> &Sdatactrl { - &self.sdatactrl - } - #[doc = "0x30 - Target Write Data Byte"] - #[inline(always)] - pub const fn swdatab(&self) -> &Swdatab { - &self.swdatab - } - #[doc = "0x34 - Target Write Data Byte End"] - #[inline(always)] - pub const fn swdatabe(&self) -> &Swdatabe { - &self.swdatabe - } - #[doc = "0x38 - Target Write Data Halfword"] - #[inline(always)] - pub const fn swdatah(&self) -> &Swdatah { - &self.swdatah - } - #[doc = "0x3c - Target Write Data Halfword End"] - #[inline(always)] - pub const fn swdatahe(&self) -> &Swdatahe { - &self.swdatahe - } - #[doc = "0x40 - Target Read Data Byte"] - #[inline(always)] - pub const fn srdatab(&self) -> &Srdatab { - &self.srdatab - } - #[doc = "0x48 - Target Read Data Halfword"] - #[inline(always)] - pub const fn srdatah(&self) -> &Srdatah { - &self.srdatah - } - #[doc = "0x54 - Target Write Data Halfword"] - #[inline(always)] - pub const fn halfword_swdatah1(&self) -> &HalfwordSwdatah1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(84).cast() } - } - #[doc = "0x54 - Target Write Data Byte"] - #[inline(always)] - pub const fn byte_swdatab1(&self) -> &ByteSwdatab1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(84).cast() } - } - #[doc = "0x5c - Target Capabilities 2"] - #[inline(always)] - pub const fn scapabilities2(&self) -> &Scapabilities2 { - &self.scapabilities2 - } - #[doc = "0x60 - Target Capabilities"] - #[inline(always)] - pub const fn scapabilities(&self) -> &Scapabilities { - &self.scapabilities - } - #[doc = "0x64 - Target Dynamic Address"] - #[inline(always)] - pub const fn sdynaddr(&self) -> &Sdynaddr { - &self.sdynaddr - } - #[doc = "0x68 - Target Maximum Limits"] - #[inline(always)] - pub const fn smaxlimits(&self) -> &Smaxlimits { - &self.smaxlimits - } - #[doc = "0x6c - Target ID Part Number"] - #[inline(always)] - pub const fn sidpartno(&self) -> &Sidpartno { - &self.sidpartno - } - #[doc = "0x70 - Target ID Extension"] - #[inline(always)] - pub const fn sidext(&self) -> &Sidext { - &self.sidext - } - #[doc = "0x74 - Target Vendor ID"] - #[inline(always)] - pub const fn svendorid(&self) -> &Svendorid { - &self.svendorid - } - #[doc = "0x78 - Target Time Control Clock"] - #[inline(always)] - pub const fn stcclock(&self) -> &Stcclock { - &self.stcclock - } - #[doc = "0x7c - Target Message Map Address"] - #[inline(always)] - pub const fn smsgmapaddr(&self) -> &Smsgmapaddr { - &self.smsgmapaddr - } - #[doc = "0x80 - Controller Extended Configuration"] - #[inline(always)] - pub const fn mconfig_ext(&self) -> &MconfigExt { - &self.mconfig_ext - } - #[doc = "0x84 - Controller Control"] - #[inline(always)] - pub const fn mctrl(&self) -> &Mctrl { - &self.mctrl - } - #[doc = "0x88 - Controller Status"] - #[inline(always)] - pub const fn mstatus(&self) -> &Mstatus { - &self.mstatus - } - #[doc = "0x8c - Controller In-band Interrupt Registry and Rules"] - #[inline(always)] - pub const fn mibirules(&self) -> &Mibirules { - &self.mibirules - } - #[doc = "0x90 - Controller Interrupt Set"] - #[inline(always)] - pub const fn mintset(&self) -> &Mintset { - &self.mintset - } - #[doc = "0x94 - Controller Interrupt Clear"] - #[inline(always)] - pub const fn mintclr(&self) -> &Mintclr { - &self.mintclr - } - #[doc = "0x98 - Controller Interrupt Mask"] - #[inline(always)] - pub const fn mintmasked(&self) -> &Mintmasked { - &self.mintmasked - } - #[doc = "0x9c - Controller Errors and Warnings"] - #[inline(always)] - pub const fn merrwarn(&self) -> &Merrwarn { - &self.merrwarn - } - #[doc = "0xa0 - Controller DMA Control"] - #[inline(always)] - pub const fn mdmactrl(&self) -> &Mdmactrl { - &self.mdmactrl - } - #[doc = "0xac - Controller Data Control"] - #[inline(always)] - pub const fn mdatactrl(&self) -> &Mdatactrl { - &self.mdatactrl - } - #[doc = "0xb0 - Controller Write Data Byte"] - #[inline(always)] - pub const fn mwdatab(&self) -> &Mwdatab { - &self.mwdatab - } - #[doc = "0xb4 - Controller Write Data Byte End"] - #[inline(always)] - pub const fn mwdatabe(&self) -> &Mwdatabe { - &self.mwdatabe - } - #[doc = "0xb8 - Controller Write Data Halfword"] - #[inline(always)] - pub const fn mwdatah(&self) -> &Mwdatah { - &self.mwdatah - } - #[doc = "0xbc - Controller Write Data Halfword End"] - #[inline(always)] - pub const fn mwdatahe(&self) -> &Mwdatahe { - &self.mwdatahe - } - #[doc = "0xc0 - Controller Read Data Byte"] - #[inline(always)] - pub const fn mrdatab(&self) -> &Mrdatab { - &self.mrdatab - } - #[doc = "0xc8 - Controller Read Data Halfword"] - #[inline(always)] - pub const fn mrdatah(&self) -> &Mrdatah { - &self.mrdatah - } - #[doc = "0xcc - Controller Write Halfword Data (to Bus)"] - #[inline(always)] - pub const fn halfword_mwdatah1(&self) -> &HalfwordMwdatah1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } - } - #[doc = "0xcc - Controller Write Byte Data 1 (to Bus)"] - #[inline(always)] - pub const fn byte_mwdatab1(&self) -> &ByteMwdatab1 { - unsafe { &*core::ptr::from_ref(self).cast::().add(204).cast() } - } - #[doc = "0xd0 - Controller Write Message Data in SDR mode"] - #[inline(always)] - pub const fn data_mwmsg_sdr_data(&self) -> &DataMwmsgSdrData { - unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } - } - #[doc = "0xd0 - Controller Write Message Control in SDR mode"] - #[inline(always)] - pub const fn control_mwmsg_sdr_control(&self) -> &ControlMwmsgSdrControl { - unsafe { &*core::ptr::from_ref(self).cast::().add(208).cast() } - } - #[doc = "0xd4 - Controller Read Message in SDR mode"] - #[inline(always)] - pub const fn mrmsg_sdr(&self) -> &MrmsgSdr { - &self.mrmsg_sdr - } - #[doc = "0xd8 - Controller Write Message Data in DDR mode"] - #[inline(always)] - pub const fn data_mwmsg_ddr_data(&self) -> &DataMwmsgDdrData { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xd8 - Controller Write Message in DDR Mode Control 2"] - #[inline(always)] - pub const fn control2_mwmsg_ddr_control2(&self) -> &Control2MwmsgDdrControl2 { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xd8 - Controller Write Message in DDR mode: First Control Word"] - #[inline(always)] - pub const fn control_mwmsg_ddr_control(&self) -> &ControlMwmsgDdrControl { - unsafe { &*core::ptr::from_ref(self).cast::().add(216).cast() } - } - #[doc = "0xdc - Controller Read Message in DDR mode"] - #[inline(always)] - pub const fn mrmsg_ddr(&self) -> &MrmsgDdr { - &self.mrmsg_ddr - } - #[doc = "0xe4 - Controller Dynamic Address"] - #[inline(always)] - pub const fn mdynaddr(&self) -> &Mdynaddr { - &self.mdynaddr - } - #[doc = "0x11c - Map Feature Control 0"] - #[inline(always)] - pub const fn smapctrl0(&self) -> &Smapctrl0 { - &self.smapctrl0 - } - #[doc = "0x140 - Extended IBI Data 1"] - #[inline(always)] - pub const fn ibiext1(&self) -> &Ibiext1 { - &self.ibiext1 - } - #[doc = "0x144 - Extended IBI Data 2"] - #[inline(always)] - pub const fn ibiext2(&self) -> &Ibiext2 { - &self.ibiext2 - } - #[doc = "0xffc - Target Module ID"] - #[inline(always)] - pub const fn sid(&self) -> &Sid { - &self.sid - } -} -#[doc = "MCONFIG (rw) register accessor: Controller Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mconfig`] module"] -#[doc(alias = "MCONFIG")] -pub type Mconfig = crate::Reg; -#[doc = "Controller Configuration"] -pub mod mconfig; -#[doc = "SCONFIG (rw) register accessor: Target Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`sconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sconfig`] module"] -#[doc(alias = "SCONFIG")] -pub type Sconfig = crate::Reg; -#[doc = "Target Configuration"] -pub mod sconfig; -#[doc = "SSTATUS (rw) register accessor: Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sstatus`] module"] -#[doc(alias = "SSTATUS")] -pub type Sstatus = crate::Reg; -#[doc = "Target Status"] -pub mod sstatus; -#[doc = "SCTRL (rw) register accessor: Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sctrl`] module"] -#[doc(alias = "SCTRL")] -pub type Sctrl = crate::Reg; -#[doc = "Target Control"] -pub mod sctrl; -#[doc = "SINTSET (rw) register accessor: Target Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`sintset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sintset`] module"] -#[doc(alias = "SINTSET")] -pub type Sintset = crate::Reg; -#[doc = "Target Interrupt Set"] -pub mod sintset; -#[doc = "SINTCLR (rw) register accessor: Target Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sintclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sintclr`] module"] -#[doc(alias = "SINTCLR")] -pub type Sintclr = crate::Reg; -#[doc = "Target Interrupt Clear"] -pub mod sintclr; -#[doc = "SINTMASKED (r) register accessor: Target Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`sintmasked::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sintmasked`] module"] -#[doc(alias = "SINTMASKED")] -pub type Sintmasked = crate::Reg; -#[doc = "Target Interrupt Mask"] -pub mod sintmasked; -#[doc = "SERRWARN (rw) register accessor: Target Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`serrwarn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serrwarn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@serrwarn`] module"] -#[doc(alias = "SERRWARN")] -pub type Serrwarn = crate::Reg; -#[doc = "Target Errors and Warnings"] -pub mod serrwarn; -#[doc = "SDMACTRL (rw) register accessor: Target DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdmactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdmactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmactrl`] module"] -#[doc(alias = "SDMACTRL")] -pub type Sdmactrl = crate::Reg; -#[doc = "Target DMA Control"] -pub mod sdmactrl; -#[doc = "SDATACTRL (rw) register accessor: Target Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdatactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdatactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdatactrl`] module"] -#[doc(alias = "SDATACTRL")] -pub type Sdatactrl = crate::Reg; -#[doc = "Target Data Control"] -pub mod sdatactrl; -#[doc = "SWDATAB (w) register accessor: Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatab::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatab`] module"] -#[doc(alias = "SWDATAB")] -pub type Swdatab = crate::Reg; -#[doc = "Target Write Data Byte"] -pub mod swdatab; -#[doc = "SWDATABE (w) register accessor: Target Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatabe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatabe`] module"] -#[doc(alias = "SWDATABE")] -pub type Swdatabe = crate::Reg; -#[doc = "Target Write Data Byte End"] -pub mod swdatabe; -#[doc = "SWDATAH (w) register accessor: Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatah::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatah`] module"] -#[doc(alias = "SWDATAH")] -pub type Swdatah = crate::Reg; -#[doc = "Target Write Data Halfword"] -pub mod swdatah; -#[doc = "SWDATAHE (w) register accessor: Target Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatahe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdatahe`] module"] -#[doc(alias = "SWDATAHE")] -pub type Swdatahe = crate::Reg; -#[doc = "Target Write Data Halfword End"] -pub mod swdatahe; -#[doc = "SRDATAB (r) register accessor: Target Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatab::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdatab`] module"] -#[doc(alias = "SRDATAB")] -pub type Srdatab = crate::Reg; -#[doc = "Target Read Data Byte"] -pub mod srdatab; -#[doc = "SRDATAH (r) register accessor: Target Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatah::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdatah`] module"] -#[doc(alias = "SRDATAH")] -pub type Srdatah = crate::Reg; -#[doc = "Target Read Data Halfword"] -pub mod srdatah; -#[doc = "Byte_SWDATAB1 (w) register accessor: Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_swdatab1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@byte_swdatab1`] module"] -#[doc(alias = "Byte_SWDATAB1")] -pub type ByteSwdatab1 = crate::Reg; -#[doc = "Target Write Data Byte"] -pub mod byte_swdatab1; -#[doc = "Halfword_SWDATAH1 (w) register accessor: Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_swdatah1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halfword_swdatah1`] module"] -#[doc(alias = "Halfword_SWDATAH1")] -pub type HalfwordSwdatah1 = crate::Reg; -#[doc = "Target Write Data Halfword"] -pub mod halfword_swdatah1; -#[doc = "SCAPABILITIES2 (r) register accessor: Target Capabilities 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scapabilities2`] module"] -#[doc(alias = "SCAPABILITIES2")] -pub type Scapabilities2 = crate::Reg; -#[doc = "Target Capabilities 2"] -pub mod scapabilities2; -#[doc = "SCAPABILITIES (r) register accessor: Target Capabilities\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scapabilities`] module"] -#[doc(alias = "SCAPABILITIES")] -pub type Scapabilities = crate::Reg; -#[doc = "Target Capabilities"] -pub mod scapabilities; -#[doc = "SDYNADDR (rw) register accessor: Target Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sdynaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdynaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdynaddr`] module"] -#[doc(alias = "SDYNADDR")] -pub type Sdynaddr = crate::Reg; -#[doc = "Target Dynamic Address"] -pub mod sdynaddr; -#[doc = "SMAXLIMITS (rw) register accessor: Target Maximum Limits\n\nYou can [`read`](crate::Reg::read) this register and get [`smaxlimits::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smaxlimits::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smaxlimits`] module"] -#[doc(alias = "SMAXLIMITS")] -pub type Smaxlimits = crate::Reg; -#[doc = "Target Maximum Limits"] -pub mod smaxlimits; -#[doc = "SIDPARTNO (rw) register accessor: Target ID Part Number\n\nYou can [`read`](crate::Reg::read) this register and get [`sidpartno::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidpartno::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sidpartno`] module"] -#[doc(alias = "SIDPARTNO")] -pub type Sidpartno = crate::Reg; -#[doc = "Target ID Part Number"] -pub mod sidpartno; -#[doc = "SIDEXT (rw) register accessor: Target ID Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`sidext::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidext::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sidext`] module"] -#[doc(alias = "SIDEXT")] -pub type Sidext = crate::Reg; -#[doc = "Target ID Extension"] -pub mod sidext; -#[doc = "SVENDORID (rw) register accessor: Target Vendor ID\n\nYou can [`read`](crate::Reg::read) this register and get [`svendorid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`svendorid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@svendorid`] module"] -#[doc(alias = "SVENDORID")] -pub type Svendorid = crate::Reg; -#[doc = "Target Vendor ID"] -pub mod svendorid; -#[doc = "STCCLOCK (rw) register accessor: Target Time Control Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`stcclock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stcclock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stcclock`] module"] -#[doc(alias = "STCCLOCK")] -pub type Stcclock = crate::Reg; -#[doc = "Target Time Control Clock"] -pub mod stcclock; -#[doc = "SMSGMAPADDR (r) register accessor: Target Message Map Address\n\nYou can [`read`](crate::Reg::read) this register and get [`smsgmapaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smsgmapaddr`] module"] -#[doc(alias = "SMSGMAPADDR")] -pub type Smsgmapaddr = crate::Reg; -#[doc = "Target Message Map Address"] -pub mod smsgmapaddr; -#[doc = "MCONFIG_EXT (rw) register accessor: Controller Extended Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig_ext::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig_ext::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mconfig_ext`] module"] -#[doc(alias = "MCONFIG_EXT")] -pub type MconfigExt = crate::Reg; -#[doc = "Controller Extended Configuration"] -pub mod mconfig_ext; -#[doc = "MCTRL (rw) register accessor: Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctrl`] module"] -#[doc(alias = "MCTRL")] -pub type Mctrl = crate::Reg; -#[doc = "Controller Control"] -pub mod mctrl; -#[doc = "MSTATUS (rw) register accessor: Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mstatus`] module"] -#[doc(alias = "MSTATUS")] -pub type Mstatus = crate::Reg; -#[doc = "Controller Status"] -pub mod mstatus; -#[doc = "MIBIRULES (rw) register accessor: Controller In-band Interrupt Registry and Rules\n\nYou can [`read`](crate::Reg::read) this register and get [`mibirules::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mibirules::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mibirules`] module"] -#[doc(alias = "MIBIRULES")] -pub type Mibirules = crate::Reg; -#[doc = "Controller In-band Interrupt Registry and Rules"] -pub mod mibirules; -#[doc = "MINTSET (rw) register accessor: Controller Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`mintset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintset`] module"] -#[doc(alias = "MINTSET")] -pub type Mintset = crate::Reg; -#[doc = "Controller Interrupt Set"] -pub mod mintset; -#[doc = "MINTCLR (rw) register accessor: Controller Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`mintclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintclr`] module"] -#[doc(alias = "MINTCLR")] -pub type Mintclr = crate::Reg; -#[doc = "Controller Interrupt Clear"] -pub mod mintclr; -#[doc = "MINTMASKED (r) register accessor: Controller Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mintmasked::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintmasked`] module"] -#[doc(alias = "MINTMASKED")] -pub type Mintmasked = crate::Reg; -#[doc = "Controller Interrupt Mask"] -pub mod mintmasked; -#[doc = "MERRWARN (rw) register accessor: Controller Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`merrwarn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`merrwarn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@merrwarn`] module"] -#[doc(alias = "MERRWARN")] -pub type Merrwarn = crate::Reg; -#[doc = "Controller Errors and Warnings"] -pub mod merrwarn; -#[doc = "MDMACTRL (rw) register accessor: Controller DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdmactrl`] module"] -#[doc(alias = "MDMACTRL")] -pub type Mdmactrl = crate::Reg; -#[doc = "Controller DMA Control"] -pub mod mdmactrl; -#[doc = "MDATACTRL (rw) register accessor: Controller Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdatactrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdatactrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdatactrl`] module"] -#[doc(alias = "MDATACTRL")] -pub type Mdatactrl = crate::Reg; -#[doc = "Controller Data Control"] -pub mod mdatactrl; -#[doc = "MWDATAB (w) register accessor: Controller Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatab::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatab`] module"] -#[doc(alias = "MWDATAB")] -pub type Mwdatab = crate::Reg; -#[doc = "Controller Write Data Byte"] -pub mod mwdatab; -#[doc = "MWDATABE (w) register accessor: Controller Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatabe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatabe`] module"] -#[doc(alias = "MWDATABE")] -pub type Mwdatabe = crate::Reg; -#[doc = "Controller Write Data Byte End"] -pub mod mwdatabe; -#[doc = "MWDATAH (w) register accessor: Controller Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatah::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatah`] module"] -#[doc(alias = "MWDATAH")] -pub type Mwdatah = crate::Reg; -#[doc = "Controller Write Data Halfword"] -pub mod mwdatah; -#[doc = "MWDATAHE (w) register accessor: Controller Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatahe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mwdatahe`] module"] -#[doc(alias = "MWDATAHE")] -pub type Mwdatahe = crate::Reg; -#[doc = "Controller Write Data Halfword End"] -pub mod mwdatahe; -#[doc = "MRDATAB (r) register accessor: Controller Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatab::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdatab`] module"] -#[doc(alias = "MRDATAB")] -pub type Mrdatab = crate::Reg; -#[doc = "Controller Read Data Byte"] -pub mod mrdatab; -#[doc = "MRDATAH (r) register accessor: Controller Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatah::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdatah`] module"] -#[doc(alias = "MRDATAH")] -pub type Mrdatah = crate::Reg; -#[doc = "Controller Read Data Halfword"] -pub mod mrdatah; -#[doc = "BYTE_MWDATAB1 (w) register accessor: Controller Write Byte Data 1 (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_mwdatab1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@byte_mwdatab1`] module"] -#[doc(alias = "BYTE_MWDATAB1")] -pub type ByteMwdatab1 = crate::Reg; -#[doc = "Controller Write Byte Data 1 (to Bus)"] -pub mod byte_mwdatab1; -#[doc = "HALFWORD_MWDATAH1 (w) register accessor: Controller Write Halfword Data (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_mwdatah1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halfword_mwdatah1`] module"] -#[doc(alias = "HALFWORD_MWDATAH1")] -pub type HalfwordMwdatah1 = crate::Reg; -#[doc = "Controller Write Halfword Data (to Bus)"] -pub mod halfword_mwdatah1; -#[doc = "CONTROL_MWMSG_SDR_CONTROL (w) register accessor: Controller Write Message Control in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_sdr_control::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control_mwmsg_sdr_control`] module"] -#[doc(alias = "CONTROL_MWMSG_SDR_CONTROL")] -pub type ControlMwmsgSdrControl = crate::Reg; -#[doc = "Controller Write Message Control in SDR mode"] -pub mod control_mwmsg_sdr_control; -#[doc = "DATA_MWMSG_SDR_DATA (w) register accessor: Controller Write Message Data in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_sdr_data::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_mwmsg_sdr_data`] module"] -#[doc(alias = "DATA_MWMSG_SDR_DATA")] -pub type DataMwmsgSdrData = crate::Reg; -#[doc = "Controller Write Message Data in SDR mode"] -pub mod data_mwmsg_sdr_data; -#[doc = "MRMSG_SDR (r) register accessor: Controller Read Message in SDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_sdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrmsg_sdr`] module"] -#[doc(alias = "MRMSG_SDR")] -pub type MrmsgSdr = crate::Reg; -#[doc = "Controller Read Message in SDR mode"] -pub mod mrmsg_sdr; -#[doc = "CONTROL_MWMSG_DDR_CONTROL (w) register accessor: Controller Write Message in DDR mode: First Control Word\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_ddr_control::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control_mwmsg_ddr_control`] module"] -#[doc(alias = "CONTROL_MWMSG_DDR_CONTROL")] -pub type ControlMwmsgDdrControl = crate::Reg; -#[doc = "Controller Write Message in DDR mode: First Control Word"] -pub mod control_mwmsg_ddr_control; -#[doc = "CONTROL2_MWMSG_DDR_CONTROL2 (w) register accessor: Controller Write Message in DDR Mode Control 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control2_mwmsg_ddr_control2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control2_mwmsg_ddr_control2`] module"] -#[doc(alias = "CONTROL2_MWMSG_DDR_CONTROL2")] -pub type Control2MwmsgDdrControl2 = - crate::Reg; -#[doc = "Controller Write Message in DDR Mode Control 2"] -pub mod control2_mwmsg_ddr_control2; -#[doc = "DATA_MWMSG_DDR_DATA (w) register accessor: Controller Write Message Data in DDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_ddr_data::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_mwmsg_ddr_data`] module"] -#[doc(alias = "DATA_MWMSG_DDR_DATA")] -pub type DataMwmsgDdrData = crate::Reg; -#[doc = "Controller Write Message Data in DDR mode"] -pub mod data_mwmsg_ddr_data; -#[doc = "MRMSG_DDR (r) register accessor: Controller Read Message in DDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_ddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrmsg_ddr`] module"] -#[doc(alias = "MRMSG_DDR")] -pub type MrmsgDdr = crate::Reg; -#[doc = "Controller Read Message in DDR mode"] -pub mod mrmsg_ddr; -#[doc = "MDYNADDR (rw) register accessor: Controller Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mdynaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdynaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdynaddr`] module"] -#[doc(alias = "MDYNADDR")] -pub type Mdynaddr = crate::Reg; -#[doc = "Controller Dynamic Address"] -pub mod mdynaddr; -#[doc = "SMAPCTRL0 (r) register accessor: Map Feature Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`smapctrl0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smapctrl0`] module"] -#[doc(alias = "SMAPCTRL0")] -pub type Smapctrl0 = crate::Reg; -#[doc = "Map Feature Control 0"] -pub mod smapctrl0; -#[doc = "IBIEXT1 (rw) register accessor: Extended IBI Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibiext1`] module"] -#[doc(alias = "IBIEXT1")] -pub type Ibiext1 = crate::Reg; -#[doc = "Extended IBI Data 1"] -pub mod ibiext1; -#[doc = "IBIEXT2 (rw) register accessor: Extended IBI Data 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibiext2`] module"] -#[doc(alias = "IBIEXT2")] -pub type Ibiext2 = crate::Reg; -#[doc = "Extended IBI Data 2"] -pub mod ibiext2; -#[doc = "SID (r) register accessor: Target Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sid`] module"] -#[doc(alias = "SID")] -pub type Sid = crate::Reg; -#[doc = "Target Module ID"] -pub mod sid; diff --git a/mcxa276-pac/src/i3c0/byte_mwdatab1.rs b/mcxa276-pac/src/i3c0/byte_mwdatab1.rs deleted file mode 100644 index e32cde5d1..000000000 --- a/mcxa276-pac/src/i3c0/byte_mwdatab1.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MWDATAB1` writer"] -pub type W = crate::W; -#[doc = "Field `VALUE` writer - Value"] -pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Value"] - #[inline(always)] - pub fn value(&mut self) -> ValueW { - ValueW::new(self, 0) - } -} -#[doc = "Controller Write Byte Data 1 (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_mwdatab1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ByteMwdatab1Spec; -impl crate::RegisterSpec for ByteMwdatab1Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`byte_mwdatab1::W`](W) writer structure"] -impl crate::Writable for ByteMwdatab1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWDATAB1 to value 0"] -impl crate::Resettable for ByteMwdatab1Spec {} diff --git a/mcxa276-pac/src/i3c0/byte_swdatab1.rs b/mcxa276-pac/src/i3c0/byte_swdatab1.rs deleted file mode 100644 index 1e3015ee5..000000000 --- a/mcxa276-pac/src/i3c0/byte_swdatab1.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SWDATAB1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`byte_swdatab1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ByteSwdatab1Spec; -impl crate::RegisterSpec for ByteSwdatab1Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`byte_swdatab1::W`](W) writer structure"] -impl crate::Writable for ByteSwdatab1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWDATAB1 to value 0"] -impl crate::Resettable for ByteSwdatab1Spec {} diff --git a/mcxa276-pac/src/i3c0/control2_mwmsg_ddr_control2.rs b/mcxa276-pac/src/i3c0/control2_mwmsg_ddr_control2.rs deleted file mode 100644 index 0f7963eae..000000000 --- a/mcxa276-pac/src/i3c0/control2_mwmsg_ddr_control2.rs +++ /dev/null @@ -1,58 +0,0 @@ -#[doc = "Register `MWMSG_DDR_CONTROL2` writer"] -pub type W = crate::W; -#[doc = "Field `LEN` writer - Length of Message"] -pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "End of Message\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum End { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: End) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END` writer - End of Message"] -pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; -impl<'a, REG> EndW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(End::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(End::End) - } -} -impl W { - #[doc = "Bits 0:9 - Length of Message"] - #[inline(always)] - pub fn len(&mut self) -> LenW { - LenW::new(self, 0) - } - #[doc = "Bit 14 - End of Message"] - #[inline(always)] - pub fn end(&mut self) -> EndW { - EndW::new(self, 14) - } -} -#[doc = "Controller Write Message in DDR Mode Control 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control2_mwmsg_ddr_control2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Control2MwmsgDdrControl2Spec; -impl crate::RegisterSpec for Control2MwmsgDdrControl2Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`control2_mwmsg_ddr_control2::W`](W) writer structure"] -impl crate::Writable for Control2MwmsgDdrControl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWMSG_DDR_CONTROL2 to value 0"] -impl crate::Resettable for Control2MwmsgDdrControl2Spec {} diff --git a/mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs b/mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs deleted file mode 100644 index 155c85e33..000000000 --- a/mcxa276-pac/src/i3c0/control_mwmsg_ddr_control.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MWMSG_DDR_CONTROL` writer"] -pub type W = crate::W; -#[doc = "Field `ADDRCMD` writer - Address Command"] -pub type AddrcmdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - Address Command"] - #[inline(always)] - pub fn addrcmd(&mut self) -> AddrcmdW { - AddrcmdW::new(self, 0) - } -} -#[doc = "Controller Write Message in DDR mode: First Control Word\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_ddr_control::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ControlMwmsgDdrControlSpec; -impl crate::RegisterSpec for ControlMwmsgDdrControlSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`control_mwmsg_ddr_control::W`](W) writer structure"] -impl crate::Writable for ControlMwmsgDdrControlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWMSG_DDR_CONTROL to value 0"] -impl crate::Resettable for ControlMwmsgDdrControlSpec {} diff --git a/mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs b/mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs deleted file mode 100644 index 511e4049b..000000000 --- a/mcxa276-pac/src/i3c0/control_mwmsg_sdr_control.rs +++ /dev/null @@ -1,137 +0,0 @@ -#[doc = "Register `MWMSG_SDR_CONTROL` writer"] -pub type W = crate::W; -#[doc = "Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dir { - #[doc = "0: Write"] - Write = 0, - #[doc = "1: Read"] - Read = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dir) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIR` writer - Direction"] -pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>; -impl<'a, REG> DirW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write"] - #[inline(always)] - pub fn write(self) -> &'a mut crate::W { - self.variant(Dir::Write) - } - #[doc = "Read"] - #[inline(always)] - pub fn read(self) -> &'a mut crate::W { - self.variant(Dir::Read) - } -} -#[doc = "Field `ADDR` writer - Address"] -pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "End of SDR Message\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum End { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: End) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END` writer - End of SDR Message"] -pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; -impl<'a, REG> EndW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(End::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(End::End) - } -} -#[doc = "I2C\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum I2c { - #[doc = "0: I3C message"] - I3cmessage = 0, - #[doc = "1: I2C message"] - I2cmessage = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: I2c) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `I2C` writer - I2C"] -pub type I2cW<'a, REG> = crate::BitWriter<'a, REG, I2c>; -impl<'a, REG> I2cW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "I3C message"] - #[inline(always)] - pub fn i3cmessage(self) -> &'a mut crate::W { - self.variant(I2c::I3cmessage) - } - #[doc = "I2C message"] - #[inline(always)] - pub fn i2cmessage(self) -> &'a mut crate::W { - self.variant(I2c::I2cmessage) - } -} -#[doc = "Field `LEN` writer - Length"] -pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl W { - #[doc = "Bit 0 - Direction"] - #[inline(always)] - pub fn dir(&mut self) -> DirW { - DirW::new(self, 0) - } - #[doc = "Bits 1:7 - Address"] - #[inline(always)] - pub fn addr(&mut self) -> AddrW { - AddrW::new(self, 1) - } - #[doc = "Bit 8 - End of SDR Message"] - #[inline(always)] - pub fn end(&mut self) -> EndW { - EndW::new(self, 8) - } - #[doc = "Bit 10 - I2C"] - #[inline(always)] - pub fn i2c(&mut self) -> I2cW { - I2cW::new(self, 10) - } - #[doc = "Bits 11:15 - Length"] - #[inline(always)] - pub fn len(&mut self) -> LenW { - LenW::new(self, 11) - } -} -#[doc = "Controller Write Message Control in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control_mwmsg_sdr_control::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ControlMwmsgSdrControlSpec; -impl crate::RegisterSpec for ControlMwmsgSdrControlSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`control_mwmsg_sdr_control::W`](W) writer structure"] -impl crate::Writable for ControlMwmsgSdrControlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWMSG_SDR_CONTROL to value 0"] -impl crate::Resettable for ControlMwmsgSdrControlSpec {} diff --git a/mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs b/mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs deleted file mode 100644 index c747baf48..000000000 --- a/mcxa276-pac/src/i3c0/data_mwmsg_ddr_data.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MWMSG_DDR_DATA` writer"] -pub type W = crate::W; -#[doc = "Field `DATA16B` writer - Data"] -pub type Data16bW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - Data"] - #[inline(always)] - pub fn data16b(&mut self) -> Data16bW { - Data16bW::new(self, 0) - } -} -#[doc = "Controller Write Message Data in DDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_ddr_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DataMwmsgDdrDataSpec; -impl crate::RegisterSpec for DataMwmsgDdrDataSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`data_mwmsg_ddr_data::W`](W) writer structure"] -impl crate::Writable for DataMwmsgDdrDataSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWMSG_DDR_DATA to value 0"] -impl crate::Resettable for DataMwmsgDdrDataSpec {} diff --git a/mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs b/mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs deleted file mode 100644 index 0ffebbf4d..000000000 --- a/mcxa276-pac/src/i3c0/data_mwmsg_sdr_data.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MWMSG_SDR_DATA` writer"] -pub type W = crate::W; -#[doc = "Field `DATA16B` writer - Data"] -pub type Data16bW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - Data"] - #[inline(always)] - pub fn data16b(&mut self) -> Data16bW { - Data16bW::new(self, 0) - } -} -#[doc = "Controller Write Message Data in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_mwmsg_sdr_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DataMwmsgSdrDataSpec; -impl crate::RegisterSpec for DataMwmsgSdrDataSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`data_mwmsg_sdr_data::W`](W) writer structure"] -impl crate::Writable for DataMwmsgSdrDataSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWMSG_SDR_DATA to value 0"] -impl crate::Resettable for DataMwmsgSdrDataSpec {} diff --git a/mcxa276-pac/src/i3c0/halfword_mwdatah1.rs b/mcxa276-pac/src/i3c0/halfword_mwdatah1.rs deleted file mode 100644 index c7ed2ed65..000000000 --- a/mcxa276-pac/src/i3c0/halfword_mwdatah1.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MWDATAH1` writer"] -pub type W = crate::W; -#[doc = "Field `VALUE` writer - Value"] -pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - Value"] - #[inline(always)] - pub fn value(&mut self) -> ValueW { - ValueW::new(self, 0) - } -} -#[doc = "Controller Write Halfword Data (to Bus)\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_mwdatah1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct HalfwordMwdatah1Spec; -impl crate::RegisterSpec for HalfwordMwdatah1Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`halfword_mwdatah1::W`](W) writer structure"] -impl crate::Writable for HalfwordMwdatah1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWDATAH1 to value 0"] -impl crate::Resettable for HalfwordMwdatah1Spec {} diff --git a/mcxa276-pac/src/i3c0/halfword_swdatah1.rs b/mcxa276-pac/src/i3c0/halfword_swdatah1.rs deleted file mode 100644 index 1e409f566..000000000 --- a/mcxa276-pac/src/i3c0/halfword_swdatah1.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SWDATAH1` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl W { - #[doc = "Bits 0:15 - Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halfword_swdatah1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct HalfwordSwdatah1Spec; -impl crate::RegisterSpec for HalfwordSwdatah1Spec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`halfword_swdatah1::W`](W) writer structure"] -impl crate::Writable for HalfwordSwdatah1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWDATAH1 to value 0"] -impl crate::Resettable for HalfwordSwdatah1Spec {} diff --git a/mcxa276-pac/src/i3c0/ibiext1.rs b/mcxa276-pac/src/i3c0/ibiext1.rs deleted file mode 100644 index 86a545869..000000000 --- a/mcxa276-pac/src/i3c0/ibiext1.rs +++ /dev/null @@ -1,86 +0,0 @@ -#[doc = "Register `IBIEXT1` reader"] -pub type R = crate::R; -#[doc = "Register `IBIEXT1` writer"] -pub type W = crate::W; -#[doc = "Field `CNT` reader - Count"] -pub type CntR = crate::FieldReader; -#[doc = "Field `CNT` writer - Count"] -pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `MAX` reader - Maximum"] -pub type MaxR = crate::FieldReader; -#[doc = "Field `EXT1` reader - Extra Byte 1"] -pub type Ext1R = crate::FieldReader; -#[doc = "Field `EXT1` writer - Extra Byte 1"] -pub type Ext1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EXT2` reader - Extra Byte 2"] -pub type Ext2R = crate::FieldReader; -#[doc = "Field `EXT2` writer - Extra Byte 2"] -pub type Ext2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EXT3` reader - Extra Byte 3"] -pub type Ext3R = crate::FieldReader; -#[doc = "Field `EXT3` writer - Extra Byte 3"] -pub type Ext3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:2 - Count"] - #[inline(always)] - pub fn cnt(&self) -> CntR { - CntR::new((self.bits & 7) as u8) - } - #[doc = "Bits 4:6 - Maximum"] - #[inline(always)] - pub fn max(&self) -> MaxR { - MaxR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bits 8:15 - Extra Byte 1"] - #[inline(always)] - pub fn ext1(&self) -> Ext1R { - Ext1R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Extra Byte 2"] - #[inline(always)] - pub fn ext2(&self) -> Ext2R { - Ext2R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Extra Byte 3"] - #[inline(always)] - pub fn ext3(&self) -> Ext3R { - Ext3R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Count"] - #[inline(always)] - pub fn cnt(&mut self) -> CntW { - CntW::new(self, 0) - } - #[doc = "Bits 8:15 - Extra Byte 1"] - #[inline(always)] - pub fn ext1(&mut self) -> Ext1W { - Ext1W::new(self, 8) - } - #[doc = "Bits 16:23 - Extra Byte 2"] - #[inline(always)] - pub fn ext2(&mut self) -> Ext2W { - Ext2W::new(self, 16) - } - #[doc = "Bits 24:31 - Extra Byte 3"] - #[inline(always)] - pub fn ext3(&mut self) -> Ext3W { - Ext3W::new(self, 24) - } -} -#[doc = "Extended IBI Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ibiext1Spec; -impl crate::RegisterSpec for Ibiext1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ibiext1::R`](R) reader structure"] -impl crate::Readable for Ibiext1Spec {} -#[doc = "`write(|w| ..)` method takes [`ibiext1::W`](W) writer structure"] -impl crate::Writable for Ibiext1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IBIEXT1 to value 0x70"] -impl crate::Resettable for Ibiext1Spec { - const RESET_VALUE: u32 = 0x70; -} diff --git a/mcxa276-pac/src/i3c0/ibiext2.rs b/mcxa276-pac/src/i3c0/ibiext2.rs deleted file mode 100644 index 163a8f0da..000000000 --- a/mcxa276-pac/src/i3c0/ibiext2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `IBIEXT2` reader"] -pub type R = crate::R; -#[doc = "Register `IBIEXT2` writer"] -pub type W = crate::W; -#[doc = "Field `EXT4` reader - Extra Byte 4"] -pub type Ext4R = crate::FieldReader; -#[doc = "Field `EXT4` writer - Extra Byte 4"] -pub type Ext4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EXT5` reader - Extra Byte 5"] -pub type Ext5R = crate::FieldReader; -#[doc = "Field `EXT5` writer - Extra Byte 5"] -pub type Ext5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EXT6` reader - Extra Byte 6"] -pub type Ext6R = crate::FieldReader; -#[doc = "Field `EXT6` writer - Extra Byte 6"] -pub type Ext6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EXT7` reader - Extra Byte 7"] -pub type Ext7R = crate::FieldReader; -#[doc = "Field `EXT7` writer - Extra Byte 7"] -pub type Ext7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Extra Byte 4"] - #[inline(always)] - pub fn ext4(&self) -> Ext4R { - Ext4R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Extra Byte 5"] - #[inline(always)] - pub fn ext5(&self) -> Ext5R { - Ext5R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Extra Byte 6"] - #[inline(always)] - pub fn ext6(&self) -> Ext6R { - Ext6R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Extra Byte 7"] - #[inline(always)] - pub fn ext7(&self) -> Ext7R { - Ext7R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Extra Byte 4"] - #[inline(always)] - pub fn ext4(&mut self) -> Ext4W { - Ext4W::new(self, 0) - } - #[doc = "Bits 8:15 - Extra Byte 5"] - #[inline(always)] - pub fn ext5(&mut self) -> Ext5W { - Ext5W::new(self, 8) - } - #[doc = "Bits 16:23 - Extra Byte 6"] - #[inline(always)] - pub fn ext6(&mut self) -> Ext6W { - Ext6W::new(self, 16) - } - #[doc = "Bits 24:31 - Extra Byte 7"] - #[inline(always)] - pub fn ext7(&mut self) -> Ext7W { - Ext7W::new(self, 24) - } -} -#[doc = "Extended IBI Data 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ibiext2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibiext2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ibiext2Spec; -impl crate::RegisterSpec for Ibiext2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ibiext2::R`](R) reader structure"] -impl crate::Readable for Ibiext2Spec {} -#[doc = "`write(|w| ..)` method takes [`ibiext2::W`](W) writer structure"] -impl crate::Writable for Ibiext2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IBIEXT2 to value 0"] -impl crate::Resettable for Ibiext2Spec {} diff --git a/mcxa276-pac/src/i3c0/mconfig.rs b/mcxa276-pac/src/i3c0/mconfig.rs deleted file mode 100644 index d69d1d395..000000000 --- a/mcxa276-pac/src/i3c0/mconfig.rs +++ /dev/null @@ -1,472 +0,0 @@ -#[doc = "Register `MCONFIG` reader"] -pub type R = crate::R; -#[doc = "Register `MCONFIG` writer"] -pub type W = crate::W; -#[doc = "Controller Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mstena { - #[doc = "0: CONTROLLER_OFF"] - MasterOff = 0, - #[doc = "1: CONTROLLER_ON"] - MasterOn = 1, - #[doc = "2: CONTROLLER_CAPABLE"] - MasterCapable = 2, - #[doc = "3: I2C_CONTROLLER_MODE"] - I2cMasterMode = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mstena) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mstena { - type Ux = u8; -} -impl crate::IsEnum for Mstena {} -#[doc = "Field `MSTENA` reader - Controller Enable"] -pub type MstenaR = crate::FieldReader; -impl MstenaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mstena { - match self.bits { - 0 => Mstena::MasterOff, - 1 => Mstena::MasterOn, - 2 => Mstena::MasterCapable, - 3 => Mstena::I2cMasterMode, - _ => unreachable!(), - } - } - #[doc = "CONTROLLER_OFF"] - #[inline(always)] - pub fn is_master_off(&self) -> bool { - *self == Mstena::MasterOff - } - #[doc = "CONTROLLER_ON"] - #[inline(always)] - pub fn is_master_on(&self) -> bool { - *self == Mstena::MasterOn - } - #[doc = "CONTROLLER_CAPABLE"] - #[inline(always)] - pub fn is_master_capable(&self) -> bool { - *self == Mstena::MasterCapable - } - #[doc = "I2C_CONTROLLER_MODE"] - #[inline(always)] - pub fn is_i2c_master_mode(&self) -> bool { - *self == Mstena::I2cMasterMode - } -} -#[doc = "Field `MSTENA` writer - Controller Enable"] -pub type MstenaW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mstena, crate::Safe>; -impl<'a, REG> MstenaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CONTROLLER_OFF"] - #[inline(always)] - pub fn master_off(self) -> &'a mut crate::W { - self.variant(Mstena::MasterOff) - } - #[doc = "CONTROLLER_ON"] - #[inline(always)] - pub fn master_on(self) -> &'a mut crate::W { - self.variant(Mstena::MasterOn) - } - #[doc = "CONTROLLER_CAPABLE"] - #[inline(always)] - pub fn master_capable(self) -> &'a mut crate::W { - self.variant(Mstena::MasterCapable) - } - #[doc = "I2C_CONTROLLER_MODE"] - #[inline(always)] - pub fn i2c_master_mode(self) -> &'a mut crate::W { - self.variant(Mstena::I2cMasterMode) - } -} -#[doc = "Disable Timeout\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Disto { - #[doc = "0: Enabled"] - Enable = 0, - #[doc = "1: Disabled, if configured"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Disto) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DISTO` reader - Disable Timeout"] -pub type DistoR = crate::BitReader; -impl DistoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Disto { - match self.bits { - false => Disto::Enable, - true => Disto::Disable, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Disto::Enable - } - #[doc = "Disabled, if configured"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Disto::Disable - } -} -#[doc = "Field `DISTO` writer - Disable Timeout"] -pub type DistoW<'a, REG> = crate::BitWriter<'a, REG, Disto>; -impl<'a, REG> DistoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Disto::Enable) - } - #[doc = "Disabled, if configured"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Disto::Disable) - } -} -#[doc = "High-Keeper\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Hkeep { - #[doc = "0: None"] - None = 0, - #[doc = "1: WIRED_IN"] - WiredIn = 1, - #[doc = "2: PASSIVE_SDA (I2C mode, no clock stretches mode)"] - PassiveSda = 2, - #[doc = "3: PASSIVE_ON_SDA_SCL"] - PassiveOnSdaScl = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Hkeep) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Hkeep { - type Ux = u8; -} -impl crate::IsEnum for Hkeep {} -#[doc = "Field `HKEEP` reader - High-Keeper"] -pub type HkeepR = crate::FieldReader; -impl HkeepR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hkeep { - match self.bits { - 0 => Hkeep::None, - 1 => Hkeep::WiredIn, - 2 => Hkeep::PassiveSda, - 3 => Hkeep::PassiveOnSdaScl, - _ => unreachable!(), - } - } - #[doc = "None"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Hkeep::None - } - #[doc = "WIRED_IN"] - #[inline(always)] - pub fn is_wired_in(&self) -> bool { - *self == Hkeep::WiredIn - } - #[doc = "PASSIVE_SDA (I2C mode, no clock stretches mode)"] - #[inline(always)] - pub fn is_passive_sda(&self) -> bool { - *self == Hkeep::PassiveSda - } - #[doc = "PASSIVE_ON_SDA_SCL"] - #[inline(always)] - pub fn is_passive_on_sda_scl(&self) -> bool { - *self == Hkeep::PassiveOnSdaScl - } -} -#[doc = "Field `HKEEP` writer - High-Keeper"] -pub type HkeepW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hkeep, crate::Safe>; -impl<'a, REG> HkeepW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "None"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Hkeep::None) - } - #[doc = "WIRED_IN"] - #[inline(always)] - pub fn wired_in(self) -> &'a mut crate::W { - self.variant(Hkeep::WiredIn) - } - #[doc = "PASSIVE_SDA (I2C mode, no clock stretches mode)"] - #[inline(always)] - pub fn passive_sda(self) -> &'a mut crate::W { - self.variant(Hkeep::PassiveSda) - } - #[doc = "PASSIVE_ON_SDA_SCL"] - #[inline(always)] - pub fn passive_on_sda_scl(self) -> &'a mut crate::W { - self.variant(Hkeep::PassiveOnSdaScl) - } -} -#[doc = "Open-drain Stop\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Odstop { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Odstop) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODSTOP` reader - Open-drain Stop"] -pub type OdstopR = crate::BitReader; -impl OdstopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Odstop { - match self.bits { - false => Odstop::Disable, - true => Odstop::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Odstop::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Odstop::Enable - } -} -#[doc = "Field `ODSTOP` writer - Open-drain Stop"] -pub type OdstopW<'a, REG> = crate::BitWriter<'a, REG, Odstop>; -impl<'a, REG> OdstopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Odstop::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Odstop::Enable) - } -} -#[doc = "Field `PPBAUD` reader - Push-Pull Baud Rate"] -pub type PpbaudR = crate::FieldReader; -#[doc = "Field `PPBAUD` writer - Push-Pull Baud Rate"] -pub type PpbaudW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `PPLOW` reader - Push-Pull Low"] -pub type PplowR = crate::FieldReader; -#[doc = "Field `PPLOW` writer - Push-Pull Low"] -pub type PplowW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ODBAUD` reader - Open-drain Baud Rate"] -pub type OdbaudR = crate::FieldReader; -#[doc = "Field `ODBAUD` writer - Open-drain Baud Rate"] -pub type OdbaudW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Open-drain High Push-Pull\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Odhpp { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Odhpp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODHPP` reader - Open-drain High Push-Pull"] -pub type OdhppR = crate::BitReader; -impl OdhppR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Odhpp { - match self.bits { - false => Odhpp::Disable, - true => Odhpp::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Odhpp::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Odhpp::Enable - } -} -#[doc = "Field `ODHPP` writer - Open-drain High Push-Pull"] -pub type OdhppW<'a, REG> = crate::BitWriter<'a, REG, Odhpp>; -impl<'a, REG> OdhppW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Odhpp::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Odhpp::Enable) - } -} -#[doc = "Field `SKEW` reader - Skew"] -pub type SkewR = crate::FieldReader; -#[doc = "Field `SKEW` writer - Skew"] -pub type SkewW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `I2CBAUD` reader - I2C Baud Rate"] -pub type I2cbaudR = crate::FieldReader; -#[doc = "Field `I2CBAUD` writer - I2C Baud Rate"] -pub type I2cbaudW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:1 - Controller Enable"] - #[inline(always)] - pub fn mstena(&self) -> MstenaR { - MstenaR::new((self.bits & 3) as u8) - } - #[doc = "Bit 3 - Disable Timeout"] - #[inline(always)] - pub fn disto(&self) -> DistoR { - DistoR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - High-Keeper"] - #[inline(always)] - pub fn hkeep(&self) -> HkeepR { - HkeepR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - Open-drain Stop"] - #[inline(always)] - pub fn odstop(&self) -> OdstopR { - OdstopR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Push-Pull Baud Rate"] - #[inline(always)] - pub fn ppbaud(&self) -> PpbaudR { - PpbaudR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Push-Pull Low"] - #[inline(always)] - pub fn pplow(&self) -> PplowR { - PplowR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:23 - Open-drain Baud Rate"] - #[inline(always)] - pub fn odbaud(&self) -> OdbaudR { - OdbaudR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bit 24 - Open-drain High Push-Pull"] - #[inline(always)] - pub fn odhpp(&self) -> OdhppR { - OdhppR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bits 25:27 - Skew"] - #[inline(always)] - pub fn skew(&self) -> SkewR { - SkewR::new(((self.bits >> 25) & 7) as u8) - } - #[doc = "Bits 28:31 - I2C Baud Rate"] - #[inline(always)] - pub fn i2cbaud(&self) -> I2cbaudR { - I2cbaudR::new(((self.bits >> 28) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Controller Enable"] - #[inline(always)] - pub fn mstena(&mut self) -> MstenaW { - MstenaW::new(self, 0) - } - #[doc = "Bit 3 - Disable Timeout"] - #[inline(always)] - pub fn disto(&mut self) -> DistoW { - DistoW::new(self, 3) - } - #[doc = "Bits 4:5 - High-Keeper"] - #[inline(always)] - pub fn hkeep(&mut self) -> HkeepW { - HkeepW::new(self, 4) - } - #[doc = "Bit 6 - Open-drain Stop"] - #[inline(always)] - pub fn odstop(&mut self) -> OdstopW { - OdstopW::new(self, 6) - } - #[doc = "Bits 8:11 - Push-Pull Baud Rate"] - #[inline(always)] - pub fn ppbaud(&mut self) -> PpbaudW { - PpbaudW::new(self, 8) - } - #[doc = "Bits 12:15 - Push-Pull Low"] - #[inline(always)] - pub fn pplow(&mut self) -> PplowW { - PplowW::new(self, 12) - } - #[doc = "Bits 16:23 - Open-drain Baud Rate"] - #[inline(always)] - pub fn odbaud(&mut self) -> OdbaudW { - OdbaudW::new(self, 16) - } - #[doc = "Bit 24 - Open-drain High Push-Pull"] - #[inline(always)] - pub fn odhpp(&mut self) -> OdhppW { - OdhppW::new(self, 24) - } - #[doc = "Bits 25:27 - Skew"] - #[inline(always)] - pub fn skew(&mut self) -> SkewW { - SkewW::new(self, 25) - } - #[doc = "Bits 28:31 - I2C Baud Rate"] - #[inline(always)] - pub fn i2cbaud(&mut self) -> I2cbaudW { - I2cbaudW::new(self, 28) - } -} -#[doc = "Controller Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MconfigSpec; -impl crate::RegisterSpec for MconfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mconfig::R`](R) reader structure"] -impl crate::Readable for MconfigSpec {} -#[doc = "`write(|w| ..)` method takes [`mconfig::W`](W) writer structure"] -impl crate::Writable for MconfigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCONFIG to value 0"] -impl crate::Resettable for MconfigSpec {} diff --git a/mcxa276-pac/src/i3c0/mconfig_ext.rs b/mcxa276-pac/src/i3c0/mconfig_ext.rs deleted file mode 100644 index 4b4c2d9b6..000000000 --- a/mcxa276-pac/src/i3c0/mconfig_ext.rs +++ /dev/null @@ -1,213 +0,0 @@ -#[doc = "Register `MCONFIG_EXT` reader"] -pub type R = crate::R; -#[doc = "Register `MCONFIG_EXT` writer"] -pub type W = crate::W; -#[doc = "I3C CAS Delay After START\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum I3cCasDel { - #[doc = "0: No delay"] - NoDelay = 0, - #[doc = "1: Increases SCL clock period by 1/2"] - OneHalfClk = 1, - #[doc = "2: Increases SCL clock period by 1"] - OneClk = 2, - #[doc = "3: Increases SCL clock period by 3/2"] - OneAndOneHalfClk = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: I3cCasDel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for I3cCasDel { - type Ux = u8; -} -impl crate::IsEnum for I3cCasDel {} -#[doc = "Field `I3C_CAS_DEL` reader - I3C CAS Delay After START"] -pub type I3cCasDelR = crate::FieldReader; -impl I3cCasDelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> I3cCasDel { - match self.bits { - 0 => I3cCasDel::NoDelay, - 1 => I3cCasDel::OneHalfClk, - 2 => I3cCasDel::OneClk, - 3 => I3cCasDel::OneAndOneHalfClk, - _ => unreachable!(), - } - } - #[doc = "No delay"] - #[inline(always)] - pub fn is_no_delay(&self) -> bool { - *self == I3cCasDel::NoDelay - } - #[doc = "Increases SCL clock period by 1/2"] - #[inline(always)] - pub fn is_one_half_clk(&self) -> bool { - *self == I3cCasDel::OneHalfClk - } - #[doc = "Increases SCL clock period by 1"] - #[inline(always)] - pub fn is_one_clk(&self) -> bool { - *self == I3cCasDel::OneClk - } - #[doc = "Increases SCL clock period by 3/2"] - #[inline(always)] - pub fn is_one_and_one_half_clk(&self) -> bool { - *self == I3cCasDel::OneAndOneHalfClk - } -} -#[doc = "Field `I3C_CAS_DEL` writer - I3C CAS Delay After START"] -pub type I3cCasDelW<'a, REG> = crate::FieldWriter<'a, REG, 2, I3cCasDel, crate::Safe>; -impl<'a, REG> I3cCasDelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No delay"] - #[inline(always)] - pub fn no_delay(self) -> &'a mut crate::W { - self.variant(I3cCasDel::NoDelay) - } - #[doc = "Increases SCL clock period by 1/2"] - #[inline(always)] - pub fn one_half_clk(self) -> &'a mut crate::W { - self.variant(I3cCasDel::OneHalfClk) - } - #[doc = "Increases SCL clock period by 1"] - #[inline(always)] - pub fn one_clk(self) -> &'a mut crate::W { - self.variant(I3cCasDel::OneClk) - } - #[doc = "Increases SCL clock period by 3/2"] - #[inline(always)] - pub fn one_and_one_half_clk(self) -> &'a mut crate::W { - self.variant(I3cCasDel::OneAndOneHalfClk) - } -} -#[doc = "I3C CAS Delay After Repeated START\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum I3cCasrDel { - #[doc = "0: No delay"] - NoDelay = 0, - #[doc = "1: Increases SCL clock period by 1/2"] - OneHalfClk = 1, - #[doc = "2: Increases SCL clock period by 1"] - OneClk = 2, - #[doc = "3: Increases SCL clock period by 1 1/2"] - OneAndOneHalfClk = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: I3cCasrDel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for I3cCasrDel { - type Ux = u8; -} -impl crate::IsEnum for I3cCasrDel {} -#[doc = "Field `I3C_CASR_DEL` reader - I3C CAS Delay After Repeated START"] -pub type I3cCasrDelR = crate::FieldReader; -impl I3cCasrDelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> I3cCasrDel { - match self.bits { - 0 => I3cCasrDel::NoDelay, - 1 => I3cCasrDel::OneHalfClk, - 2 => I3cCasrDel::OneClk, - 3 => I3cCasrDel::OneAndOneHalfClk, - _ => unreachable!(), - } - } - #[doc = "No delay"] - #[inline(always)] - pub fn is_no_delay(&self) -> bool { - *self == I3cCasrDel::NoDelay - } - #[doc = "Increases SCL clock period by 1/2"] - #[inline(always)] - pub fn is_one_half_clk(&self) -> bool { - *self == I3cCasrDel::OneHalfClk - } - #[doc = "Increases SCL clock period by 1"] - #[inline(always)] - pub fn is_one_clk(&self) -> bool { - *self == I3cCasrDel::OneClk - } - #[doc = "Increases SCL clock period by 1 1/2"] - #[inline(always)] - pub fn is_one_and_one_half_clk(&self) -> bool { - *self == I3cCasrDel::OneAndOneHalfClk - } -} -#[doc = "Field `I3C_CASR_DEL` writer - I3C CAS Delay After Repeated START"] -pub type I3cCasrDelW<'a, REG> = crate::FieldWriter<'a, REG, 2, I3cCasrDel, crate::Safe>; -impl<'a, REG> I3cCasrDelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No delay"] - #[inline(always)] - pub fn no_delay(self) -> &'a mut crate::W { - self.variant(I3cCasrDel::NoDelay) - } - #[doc = "Increases SCL clock period by 1/2"] - #[inline(always)] - pub fn one_half_clk(self) -> &'a mut crate::W { - self.variant(I3cCasrDel::OneHalfClk) - } - #[doc = "Increases SCL clock period by 1"] - #[inline(always)] - pub fn one_clk(self) -> &'a mut crate::W { - self.variant(I3cCasrDel::OneClk) - } - #[doc = "Increases SCL clock period by 1 1/2"] - #[inline(always)] - pub fn one_and_one_half_clk(self) -> &'a mut crate::W { - self.variant(I3cCasrDel::OneAndOneHalfClk) - } -} -impl R { - #[doc = "Bits 16:17 - I3C CAS Delay After START"] - #[inline(always)] - pub fn i3c_cas_del(&self) -> I3cCasDelR { - I3cCasDelR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:19 - I3C CAS Delay After Repeated START"] - #[inline(always)] - pub fn i3c_casr_del(&self) -> I3cCasrDelR { - I3cCasrDelR::new(((self.bits >> 18) & 3) as u8) - } -} -impl W { - #[doc = "Bits 16:17 - I3C CAS Delay After START"] - #[inline(always)] - pub fn i3c_cas_del(&mut self) -> I3cCasDelW { - I3cCasDelW::new(self, 16) - } - #[doc = "Bits 18:19 - I3C CAS Delay After Repeated START"] - #[inline(always)] - pub fn i3c_casr_del(&mut self) -> I3cCasrDelW { - I3cCasrDelW::new(self, 18) - } -} -#[doc = "Controller Extended Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mconfig_ext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mconfig_ext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MconfigExtSpec; -impl crate::RegisterSpec for MconfigExtSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mconfig_ext::R`](R) reader structure"] -impl crate::Readable for MconfigExtSpec {} -#[doc = "`write(|w| ..)` method takes [`mconfig_ext::W`](W) writer structure"] -impl crate::Writable for MconfigExtSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCONFIG_EXT to value 0"] -impl crate::Resettable for MconfigExtSpec {} diff --git a/mcxa276-pac/src/i3c0/mctrl.rs b/mcxa276-pac/src/i3c0/mctrl.rs deleted file mode 100644 index 58c9b7105..000000000 --- a/mcxa276-pac/src/i3c0/mctrl.rs +++ /dev/null @@ -1,426 +0,0 @@ -#[doc = "Register `MCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `MCTRL` writer"] -pub type W = crate::W; -#[doc = "Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Request { - #[doc = "0: NONE"] - None = 0, - #[doc = "1: EMITSTARTADDR"] - Emitstartaddr = 1, - #[doc = "2: EMITSTOP"] - Emitstop = 2, - #[doc = "3: IBIACKNACK"] - Ibiacknack = 3, - #[doc = "4: PROCESSDAA"] - Processdaa = 4, - #[doc = "6: Force Exit and Target Reset"] - Forceexit = 6, - #[doc = "7: AUTOIBI"] - Autoibi = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Request) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Request { - type Ux = u8; -} -impl crate::IsEnum for Request {} -#[doc = "Field `REQUEST` reader - Request"] -pub type RequestR = crate::FieldReader; -impl RequestR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Request::None), - 1 => Some(Request::Emitstartaddr), - 2 => Some(Request::Emitstop), - 3 => Some(Request::Ibiacknack), - 4 => Some(Request::Processdaa), - 6 => Some(Request::Forceexit), - 7 => Some(Request::Autoibi), - _ => None, - } - } - #[doc = "NONE"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Request::None - } - #[doc = "EMITSTARTADDR"] - #[inline(always)] - pub fn is_emitstartaddr(&self) -> bool { - *self == Request::Emitstartaddr - } - #[doc = "EMITSTOP"] - #[inline(always)] - pub fn is_emitstop(&self) -> bool { - *self == Request::Emitstop - } - #[doc = "IBIACKNACK"] - #[inline(always)] - pub fn is_ibiacknack(&self) -> bool { - *self == Request::Ibiacknack - } - #[doc = "PROCESSDAA"] - #[inline(always)] - pub fn is_processdaa(&self) -> bool { - *self == Request::Processdaa - } - #[doc = "Force Exit and Target Reset"] - #[inline(always)] - pub fn is_forceexit(&self) -> bool { - *self == Request::Forceexit - } - #[doc = "AUTOIBI"] - #[inline(always)] - pub fn is_autoibi(&self) -> bool { - *self == Request::Autoibi - } -} -#[doc = "Field `REQUEST` writer - Request"] -pub type RequestW<'a, REG> = crate::FieldWriter<'a, REG, 3, Request>; -impl<'a, REG> RequestW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "NONE"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Request::None) - } - #[doc = "EMITSTARTADDR"] - #[inline(always)] - pub fn emitstartaddr(self) -> &'a mut crate::W { - self.variant(Request::Emitstartaddr) - } - #[doc = "EMITSTOP"] - #[inline(always)] - pub fn emitstop(self) -> &'a mut crate::W { - self.variant(Request::Emitstop) - } - #[doc = "IBIACKNACK"] - #[inline(always)] - pub fn ibiacknack(self) -> &'a mut crate::W { - self.variant(Request::Ibiacknack) - } - #[doc = "PROCESSDAA"] - #[inline(always)] - pub fn processdaa(self) -> &'a mut crate::W { - self.variant(Request::Processdaa) - } - #[doc = "Force Exit and Target Reset"] - #[inline(always)] - pub fn forceexit(self) -> &'a mut crate::W { - self.variant(Request::Forceexit) - } - #[doc = "AUTOIBI"] - #[inline(always)] - pub fn autoibi(self) -> &'a mut crate::W { - self.variant(Request::Autoibi) - } -} -#[doc = "Bus Type with EmitStartAddr\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Type { - #[doc = "0: I3C"] - I3c = 0, - #[doc = "1: I2C"] - I2c = 1, - #[doc = "2: DDR"] - Ddr = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Type) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Type { - type Ux = u8; -} -impl crate::IsEnum for Type {} -#[doc = "Field `TYPE` reader - Bus Type with EmitStartAddr"] -pub type TypeR = crate::FieldReader; -impl TypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Type::I3c), - 1 => Some(Type::I2c), - 2 => Some(Type::Ddr), - _ => None, - } - } - #[doc = "I3C"] - #[inline(always)] - pub fn is_i3c(&self) -> bool { - *self == Type::I3c - } - #[doc = "I2C"] - #[inline(always)] - pub fn is_i2c(&self) -> bool { - *self == Type::I2c - } - #[doc = "DDR"] - #[inline(always)] - pub fn is_ddr(&self) -> bool { - *self == Type::Ddr - } -} -#[doc = "Field `TYPE` writer - Bus Type with EmitStartAddr"] -pub type TypeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Type>; -impl<'a, REG> TypeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "I3C"] - #[inline(always)] - pub fn i3c(self) -> &'a mut crate::W { - self.variant(Type::I3c) - } - #[doc = "I2C"] - #[inline(always)] - pub fn i2c(self) -> &'a mut crate::W { - self.variant(Type::I2c) - } - #[doc = "DDR"] - #[inline(always)] - pub fn ddr(self) -> &'a mut crate::W { - self.variant(Type::Ddr) - } -} -#[doc = "In-Band Interrupt Response\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ibiresp { - #[doc = "0: ACK (acknowledge)"] - Ack = 0, - #[doc = "1: NACK (reject)"] - Nack = 1, - #[doc = "2: Acknowledge with mandatory byte"] - AckWithMandatory = 2, - #[doc = "3: Manual"] - Manual = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ibiresp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ibiresp { - type Ux = u8; -} -impl crate::IsEnum for Ibiresp {} -#[doc = "Field `IBIRESP` reader - In-Band Interrupt Response"] -pub type IbirespR = crate::FieldReader; -impl IbirespR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibiresp { - match self.bits { - 0 => Ibiresp::Ack, - 1 => Ibiresp::Nack, - 2 => Ibiresp::AckWithMandatory, - 3 => Ibiresp::Manual, - _ => unreachable!(), - } - } - #[doc = "ACK (acknowledge)"] - #[inline(always)] - pub fn is_ack(&self) -> bool { - *self == Ibiresp::Ack - } - #[doc = "NACK (reject)"] - #[inline(always)] - pub fn is_nack(&self) -> bool { - *self == Ibiresp::Nack - } - #[doc = "Acknowledge with mandatory byte"] - #[inline(always)] - pub fn is_ack_with_mandatory(&self) -> bool { - *self == Ibiresp::AckWithMandatory - } - #[doc = "Manual"] - #[inline(always)] - pub fn is_manual(&self) -> bool { - *self == Ibiresp::Manual - } -} -#[doc = "Field `IBIRESP` writer - In-Band Interrupt Response"] -pub type IbirespW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ibiresp, crate::Safe>; -impl<'a, REG> IbirespW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ACK (acknowledge)"] - #[inline(always)] - pub fn ack(self) -> &'a mut crate::W { - self.variant(Ibiresp::Ack) - } - #[doc = "NACK (reject)"] - #[inline(always)] - pub fn nack(self) -> &'a mut crate::W { - self.variant(Ibiresp::Nack) - } - #[doc = "Acknowledge with mandatory byte"] - #[inline(always)] - pub fn ack_with_mandatory(self) -> &'a mut crate::W { - self.variant(Ibiresp::AckWithMandatory) - } - #[doc = "Manual"] - #[inline(always)] - pub fn manual(self) -> &'a mut crate::W { - self.variant(Ibiresp::Manual) - } -} -#[doc = "Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dir { - #[doc = "0: Write"] - Dirwrite = 0, - #[doc = "1: Read"] - Dirread = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dir) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIR` reader - Direction"] -pub type DirR = crate::BitReader; -impl DirR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dir { - match self.bits { - false => Dir::Dirwrite, - true => Dir::Dirread, - } - } - #[doc = "Write"] - #[inline(always)] - pub fn is_dirwrite(&self) -> bool { - *self == Dir::Dirwrite - } - #[doc = "Read"] - #[inline(always)] - pub fn is_dirread(&self) -> bool { - *self == Dir::Dirread - } -} -#[doc = "Field `DIR` writer - Direction"] -pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>; -impl<'a, REG> DirW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write"] - #[inline(always)] - pub fn dirwrite(self) -> &'a mut crate::W { - self.variant(Dir::Dirwrite) - } - #[doc = "Read"] - #[inline(always)] - pub fn dirread(self) -> &'a mut crate::W { - self.variant(Dir::Dirread) - } -} -#[doc = "Field `ADDR` reader - Address"] -pub type AddrR = crate::FieldReader; -#[doc = "Field `ADDR` writer - Address"] -pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `RDTERM` reader - Read Terminate Counter"] -pub type RdtermR = crate::FieldReader; -#[doc = "Field `RDTERM` writer - Read Terminate Counter"] -pub type RdtermW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:2 - Request"] - #[inline(always)] - pub fn request(&self) -> RequestR { - RequestR::new((self.bits & 7) as u8) - } - #[doc = "Bits 4:5 - Bus Type with EmitStartAddr"] - #[inline(always)] - pub fn type_(&self) -> TypeR { - TypeR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - In-Band Interrupt Response"] - #[inline(always)] - pub fn ibiresp(&self) -> IbirespR { - IbirespR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - Direction"] - #[inline(always)] - pub fn dir(&self) -> DirR { - DirR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 9:15 - Address"] - #[inline(always)] - pub fn addr(&self) -> AddrR { - AddrR::new(((self.bits >> 9) & 0x7f) as u8) - } - #[doc = "Bits 16:23 - Read Terminate Counter"] - #[inline(always)] - pub fn rdterm(&self) -> RdtermR { - RdtermR::new(((self.bits >> 16) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Request"] - #[inline(always)] - pub fn request(&mut self) -> RequestW { - RequestW::new(self, 0) - } - #[doc = "Bits 4:5 - Bus Type with EmitStartAddr"] - #[inline(always)] - pub fn type_(&mut self) -> TypeW { - TypeW::new(self, 4) - } - #[doc = "Bits 6:7 - In-Band Interrupt Response"] - #[inline(always)] - pub fn ibiresp(&mut self) -> IbirespW { - IbirespW::new(self, 6) - } - #[doc = "Bit 8 - Direction"] - #[inline(always)] - pub fn dir(&mut self) -> DirW { - DirW::new(self, 8) - } - #[doc = "Bits 9:15 - Address"] - #[inline(always)] - pub fn addr(&mut self) -> AddrW { - AddrW::new(self, 9) - } - #[doc = "Bits 16:23 - Read Terminate Counter"] - #[inline(always)] - pub fn rdterm(&mut self) -> RdtermW { - RdtermW::new(self, 16) - } -} -#[doc = "Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MctrlSpec; -impl crate::RegisterSpec for MctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mctrl::R`](R) reader structure"] -impl crate::Readable for MctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`mctrl::W`](W) writer structure"] -impl crate::Writable for MctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCTRL to value 0"] -impl crate::Resettable for MctrlSpec {} diff --git a/mcxa276-pac/src/i3c0/mdatactrl.rs b/mcxa276-pac/src/i3c0/mdatactrl.rs deleted file mode 100644 index 4b4e39a58..000000000 --- a/mcxa276-pac/src/i3c0/mdatactrl.rs +++ /dev/null @@ -1,419 +0,0 @@ -#[doc = "Register `MDATACTRL` reader"] -pub type R = crate::R; -#[doc = "Register `MDATACTRL` writer"] -pub type W = crate::W; -#[doc = "Flush To-Bus Buffer or FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flushtb { - #[doc = "0: No action"] - NoAction = 0, - #[doc = "1: Flush the buffer"] - Flush = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flushtb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLUSHTB` writer - Flush To-Bus Buffer or FIFO"] -pub type FlushtbW<'a, REG> = crate::BitWriter<'a, REG, Flushtb>; -impl<'a, REG> FlushtbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No action"] - #[inline(always)] - pub fn no_action(self) -> &'a mut crate::W { - self.variant(Flushtb::NoAction) - } - #[doc = "Flush the buffer"] - #[inline(always)] - pub fn flush(self) -> &'a mut crate::W { - self.variant(Flushtb::Flush) - } -} -#[doc = "Flush From-Bus Buffer or FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flushfb { - #[doc = "0: No action"] - NoAction = 0, - #[doc = "1: Flush the buffer"] - Flush = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flushfb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLUSHFB` writer - Flush From-Bus Buffer or FIFO"] -pub type FlushfbW<'a, REG> = crate::BitWriter<'a, REG, Flushfb>; -impl<'a, REG> FlushfbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No action"] - #[inline(always)] - pub fn no_action(self) -> &'a mut crate::W { - self.variant(Flushfb::NoAction) - } - #[doc = "Flush the buffer"] - #[inline(always)] - pub fn flush(self) -> &'a mut crate::W { - self.variant(Flushfb::Flush) - } -} -#[doc = "Unlock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unlock { - #[doc = "0: Locked"] - Disabled = 0, - #[doc = "1: Unlocked"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unlock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNLOCK` writer - Unlock"] -pub type UnlockW<'a, REG> = crate::BitWriter<'a, REG, Unlock>; -impl<'a, REG> UnlockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Unlock::Disabled) - } - #[doc = "Unlocked"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Unlock::Enabled) - } -} -#[doc = "Transmit Trigger Level\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Txtrig { - #[doc = "0: Trigger when empty"] - Empty = 0, - #[doc = "1: Trigger when 1/4 full or less"] - QuarterOrLess = 1, - #[doc = "2: Trigger when 1/2 full or less"] - HalfOrLess = 2, - #[doc = "3: Trigger when 1 less than full or less (default)"] - FullOrLess = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Txtrig) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Txtrig { - type Ux = u8; -} -impl crate::IsEnum for Txtrig {} -#[doc = "Field `TXTRIG` reader - Transmit Trigger Level"] -pub type TxtrigR = crate::FieldReader; -impl TxtrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txtrig { - match self.bits { - 0 => Txtrig::Empty, - 1 => Txtrig::QuarterOrLess, - 2 => Txtrig::HalfOrLess, - 3 => Txtrig::FullOrLess, - _ => unreachable!(), - } - } - #[doc = "Trigger when empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Txtrig::Empty - } - #[doc = "Trigger when 1/4 full or less"] - #[inline(always)] - pub fn is_quarter_or_less(&self) -> bool { - *self == Txtrig::QuarterOrLess - } - #[doc = "Trigger when 1/2 full or less"] - #[inline(always)] - pub fn is_half_or_less(&self) -> bool { - *self == Txtrig::HalfOrLess - } - #[doc = "Trigger when 1 less than full or less (default)"] - #[inline(always)] - pub fn is_full_or_less(&self) -> bool { - *self == Txtrig::FullOrLess - } -} -#[doc = "Field `TXTRIG` writer - Transmit Trigger Level"] -pub type TxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txtrig, crate::Safe>; -impl<'a, REG> TxtrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Trigger when empty"] - #[inline(always)] - pub fn empty(self) -> &'a mut crate::W { - self.variant(Txtrig::Empty) - } - #[doc = "Trigger when 1/4 full or less"] - #[inline(always)] - pub fn quarter_or_less(self) -> &'a mut crate::W { - self.variant(Txtrig::QuarterOrLess) - } - #[doc = "Trigger when 1/2 full or less"] - #[inline(always)] - pub fn half_or_less(self) -> &'a mut crate::W { - self.variant(Txtrig::HalfOrLess) - } - #[doc = "Trigger when 1 less than full or less (default)"] - #[inline(always)] - pub fn full_or_less(self) -> &'a mut crate::W { - self.variant(Txtrig::FullOrLess) - } -} -#[doc = "Receive Trigger Level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Rxtrig { - #[doc = "0: Trigger when not empty (default)"] - NotEmpty = 0, - #[doc = "1: Trigger when 1/4 full or more"] - QuarterOrMore = 1, - #[doc = "2: Trigger when 1/2 full or more"] - HalfOrMore = 2, - #[doc = "3: Trigger when 3/4 full or more"] - ThreeQuarterOrMore = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Rxtrig) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Rxtrig { - type Ux = u8; -} -impl crate::IsEnum for Rxtrig {} -#[doc = "Field `RXTRIG` reader - Receive Trigger Level"] -pub type RxtrigR = crate::FieldReader; -impl RxtrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxtrig { - match self.bits { - 0 => Rxtrig::NotEmpty, - 1 => Rxtrig::QuarterOrMore, - 2 => Rxtrig::HalfOrMore, - 3 => Rxtrig::ThreeQuarterOrMore, - _ => unreachable!(), - } - } - #[doc = "Trigger when not empty (default)"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxtrig::NotEmpty - } - #[doc = "Trigger when 1/4 full or more"] - #[inline(always)] - pub fn is_quarter_or_more(&self) -> bool { - *self == Rxtrig::QuarterOrMore - } - #[doc = "Trigger when 1/2 full or more"] - #[inline(always)] - pub fn is_half_or_more(&self) -> bool { - *self == Rxtrig::HalfOrMore - } - #[doc = "Trigger when 3/4 full or more"] - #[inline(always)] - pub fn is_three_quarter_or_more(&self) -> bool { - *self == Rxtrig::ThreeQuarterOrMore - } -} -#[doc = "Field `RXTRIG` writer - Receive Trigger Level"] -pub type RxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxtrig, crate::Safe>; -impl<'a, REG> RxtrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Trigger when not empty (default)"] - #[inline(always)] - pub fn not_empty(self) -> &'a mut crate::W { - self.variant(Rxtrig::NotEmpty) - } - #[doc = "Trigger when 1/4 full or more"] - #[inline(always)] - pub fn quarter_or_more(self) -> &'a mut crate::W { - self.variant(Rxtrig::QuarterOrMore) - } - #[doc = "Trigger when 1/2 full or more"] - #[inline(always)] - pub fn half_or_more(self) -> &'a mut crate::W { - self.variant(Rxtrig::HalfOrMore) - } - #[doc = "Trigger when 3/4 full or more"] - #[inline(always)] - pub fn three_quarter_or_more(self) -> &'a mut crate::W { - self.variant(Rxtrig::ThreeQuarterOrMore) - } -} -#[doc = "Field `TXCOUNT` reader - Transmit Entry Count"] -pub type TxcountR = crate::FieldReader; -#[doc = "Field `RXCOUNT` reader - Receive Entry Count"] -pub type RxcountR = crate::FieldReader; -#[doc = "Transmit is Full\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txfull { - #[doc = "0: Not full"] - NotFull = 0, - #[doc = "1: Full"] - Full = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txfull) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXFULL` reader - Transmit is Full"] -pub type TxfullR = crate::BitReader; -impl TxfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txfull { - match self.bits { - false => Txfull::NotFull, - true => Txfull::Full, - } - } - #[doc = "Not full"] - #[inline(always)] - pub fn is_not_full(&self) -> bool { - *self == Txfull::NotFull - } - #[doc = "Full"] - #[inline(always)] - pub fn is_full(&self) -> bool { - *self == Txfull::Full - } -} -#[doc = "Receive is Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempty { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPTY` reader - Receive is Empty"] -pub type RxemptyR = crate::BitReader; -impl RxemptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempty { - match self.bits { - false => Rxempty::NotEmpty, - true => Rxempty::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempty::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempty::Empty - } -} -impl R { - #[doc = "Bits 4:5 - Transmit Trigger Level"] - #[inline(always)] - pub fn txtrig(&self) -> TxtrigR { - TxtrigR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Receive Trigger Level"] - #[inline(always)] - pub fn rxtrig(&self) -> RxtrigR { - RxtrigR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 16:20 - Transmit Entry Count"] - #[inline(always)] - pub fn txcount(&self) -> TxcountR { - TxcountR::new(((self.bits >> 16) & 0x1f) as u8) - } - #[doc = "Bits 24:28 - Receive Entry Count"] - #[inline(always)] - pub fn rxcount(&self) -> RxcountR { - RxcountR::new(((self.bits >> 24) & 0x1f) as u8) - } - #[doc = "Bit 30 - Transmit is Full"] - #[inline(always)] - pub fn txfull(&self) -> TxfullR { - TxfullR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Receive is Empty"] - #[inline(always)] - pub fn rxempty(&self) -> RxemptyR { - RxemptyR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Flush To-Bus Buffer or FIFO"] - #[inline(always)] - pub fn flushtb(&mut self) -> FlushtbW { - FlushtbW::new(self, 0) - } - #[doc = "Bit 1 - Flush From-Bus Buffer or FIFO"] - #[inline(always)] - pub fn flushfb(&mut self) -> FlushfbW { - FlushfbW::new(self, 1) - } - #[doc = "Bit 3 - Unlock"] - #[inline(always)] - pub fn unlock(&mut self) -> UnlockW { - UnlockW::new(self, 3) - } - #[doc = "Bits 4:5 - Transmit Trigger Level"] - #[inline(always)] - pub fn txtrig(&mut self) -> TxtrigW { - TxtrigW::new(self, 4) - } - #[doc = "Bits 6:7 - Receive Trigger Level"] - #[inline(always)] - pub fn rxtrig(&mut self) -> RxtrigW { - RxtrigW::new(self, 6) - } -} -#[doc = "Controller Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdatactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdatactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MdatactrlSpec; -impl crate::RegisterSpec for MdatactrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mdatactrl::R`](R) reader structure"] -impl crate::Readable for MdatactrlSpec {} -#[doc = "`write(|w| ..)` method takes [`mdatactrl::W`](W) writer structure"] -impl crate::Writable for MdatactrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MDATACTRL to value 0x8000_0030"] -impl crate::Resettable for MdatactrlSpec { - const RESET_VALUE: u32 = 0x8000_0030; -} diff --git a/mcxa276-pac/src/i3c0/mdmactrl.rs b/mcxa276-pac/src/i3c0/mdmactrl.rs deleted file mode 100644 index 6c21d00f2..000000000 --- a/mcxa276-pac/src/i3c0/mdmactrl.rs +++ /dev/null @@ -1,272 +0,0 @@ -#[doc = "Register `MDMACTRL` reader"] -pub type R = crate::R; -#[doc = "Register `MDMACTRL` writer"] -pub type W = crate::W; -#[doc = "DMA from Bus\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dmafb { - #[doc = "0: DMA not used"] - NotUsed = 0, - #[doc = "1: Enable DMA for one frame"] - EnableOneFrame = 1, - #[doc = "2: Enable DMA until DMA is turned off"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dmafb) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dmafb { - type Ux = u8; -} -impl crate::IsEnum for Dmafb {} -#[doc = "Field `DMAFB` reader - DMA from Bus"] -pub type DmafbR = crate::FieldReader; -impl DmafbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dmafb::NotUsed), - 1 => Some(Dmafb::EnableOneFrame), - 2 => Some(Dmafb::Enable), - _ => None, - } - } - #[doc = "DMA not used"] - #[inline(always)] - pub fn is_not_used(&self) -> bool { - *self == Dmafb::NotUsed - } - #[doc = "Enable DMA for one frame"] - #[inline(always)] - pub fn is_enable_one_frame(&self) -> bool { - *self == Dmafb::EnableOneFrame - } - #[doc = "Enable DMA until DMA is turned off"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dmafb::Enable - } -} -#[doc = "Field `DMAFB` writer - DMA from Bus"] -pub type DmafbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmafb>; -impl<'a, REG> DmafbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "DMA not used"] - #[inline(always)] - pub fn not_used(self) -> &'a mut crate::W { - self.variant(Dmafb::NotUsed) - } - #[doc = "Enable DMA for one frame"] - #[inline(always)] - pub fn enable_one_frame(self) -> &'a mut crate::W { - self.variant(Dmafb::EnableOneFrame) - } - #[doc = "Enable DMA until DMA is turned off"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dmafb::Enable) - } -} -#[doc = "DMA to Bus\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dmatb { - #[doc = "0: DMA not used"] - NotUsed = 0, - #[doc = "1: Enable DMA for one frame (ended by DMA or terminated)"] - EnableOneFrame = 1, - #[doc = "2: Enable DMA until DMA is turned off"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dmatb) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dmatb { - type Ux = u8; -} -impl crate::IsEnum for Dmatb {} -#[doc = "Field `DMATB` reader - DMA to Bus"] -pub type DmatbR = crate::FieldReader; -impl DmatbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dmatb::NotUsed), - 1 => Some(Dmatb::EnableOneFrame), - 2 => Some(Dmatb::Enable), - _ => None, - } - } - #[doc = "DMA not used"] - #[inline(always)] - pub fn is_not_used(&self) -> bool { - *self == Dmatb::NotUsed - } - #[doc = "Enable DMA for one frame (ended by DMA or terminated)"] - #[inline(always)] - pub fn is_enable_one_frame(&self) -> bool { - *self == Dmatb::EnableOneFrame - } - #[doc = "Enable DMA until DMA is turned off"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dmatb::Enable - } -} -#[doc = "Field `DMATB` writer - DMA to Bus"] -pub type DmatbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmatb>; -impl<'a, REG> DmatbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "DMA not used"] - #[inline(always)] - pub fn not_used(self) -> &'a mut crate::W { - self.variant(Dmatb::NotUsed) - } - #[doc = "Enable DMA for one frame (ended by DMA or terminated)"] - #[inline(always)] - pub fn enable_one_frame(self) -> &'a mut crate::W { - self.variant(Dmatb::EnableOneFrame) - } - #[doc = "Enable DMA until DMA is turned off"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dmatb::Enable) - } -} -#[doc = "DMA Width\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dmawidth { - #[doc = "0: Byte"] - Byte0 = 0, - #[doc = "1: Byte"] - Byte1 = 1, - #[doc = "2: Halfword (16 bits)"] - HalfWord = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dmawidth) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dmawidth { - type Ux = u8; -} -impl crate::IsEnum for Dmawidth {} -#[doc = "Field `DMAWIDTH` reader - DMA Width"] -pub type DmawidthR = crate::FieldReader; -impl DmawidthR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dmawidth::Byte0), - 1 => Some(Dmawidth::Byte1), - 2 => Some(Dmawidth::HalfWord), - _ => None, - } - } - #[doc = "Byte"] - #[inline(always)] - pub fn is_byte_0(&self) -> bool { - *self == Dmawidth::Byte0 - } - #[doc = "Byte"] - #[inline(always)] - pub fn is_byte_1(&self) -> bool { - *self == Dmawidth::Byte1 - } - #[doc = "Halfword (16 bits)"] - #[inline(always)] - pub fn is_half_word(&self) -> bool { - *self == Dmawidth::HalfWord - } -} -#[doc = "Field `DMAWIDTH` writer - DMA Width"] -pub type DmawidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmawidth>; -impl<'a, REG> DmawidthW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Byte"] - #[inline(always)] - pub fn byte_0(self) -> &'a mut crate::W { - self.variant(Dmawidth::Byte0) - } - #[doc = "Byte"] - #[inline(always)] - pub fn byte_1(self) -> &'a mut crate::W { - self.variant(Dmawidth::Byte1) - } - #[doc = "Halfword (16 bits)"] - #[inline(always)] - pub fn half_word(self) -> &'a mut crate::W { - self.variant(Dmawidth::HalfWord) - } -} -impl R { - #[doc = "Bits 0:1 - DMA from Bus"] - #[inline(always)] - pub fn dmafb(&self) -> DmafbR { - DmafbR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - DMA to Bus"] - #[inline(always)] - pub fn dmatb(&self) -> DmatbR { - DmatbR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - DMA Width"] - #[inline(always)] - pub fn dmawidth(&self) -> DmawidthR { - DmawidthR::new(((self.bits >> 4) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - DMA from Bus"] - #[inline(always)] - pub fn dmafb(&mut self) -> DmafbW { - DmafbW::new(self, 0) - } - #[doc = "Bits 2:3 - DMA to Bus"] - #[inline(always)] - pub fn dmatb(&mut self) -> DmatbW { - DmatbW::new(self, 2) - } - #[doc = "Bits 4:5 - DMA Width"] - #[inline(always)] - pub fn dmawidth(&mut self) -> DmawidthW { - DmawidthW::new(self, 4) - } -} -#[doc = "Controller DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MdmactrlSpec; -impl crate::RegisterSpec for MdmactrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mdmactrl::R`](R) reader structure"] -impl crate::Readable for MdmactrlSpec {} -#[doc = "`write(|w| ..)` method takes [`mdmactrl::W`](W) writer structure"] -impl crate::Writable for MdmactrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MDMACTRL to value 0x10"] -impl crate::Resettable for MdmactrlSpec { - const RESET_VALUE: u32 = 0x10; -} diff --git a/mcxa276-pac/src/i3c0/mdynaddr.rs b/mcxa276-pac/src/i3c0/mdynaddr.rs deleted file mode 100644 index 0381838ee..000000000 --- a/mcxa276-pac/src/i3c0/mdynaddr.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `MDYNADDR` reader"] -pub type R = crate::R; -#[doc = "Register `MDYNADDR` writer"] -pub type W = crate::W; -#[doc = "Dynamic Address Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Davalid { - #[doc = "0: No valid DA assigned"] - NoValid = 0, - #[doc = "1: Valid DA assigned"] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Davalid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAVALID` reader - Dynamic Address Valid"] -pub type DavalidR = crate::BitReader; -impl DavalidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Davalid { - match self.bits { - false => Davalid::NoValid, - true => Davalid::Valid, - } - } - #[doc = "No valid DA assigned"] - #[inline(always)] - pub fn is_no_valid(&self) -> bool { - *self == Davalid::NoValid - } - #[doc = "Valid DA assigned"] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Davalid::Valid - } -} -#[doc = "Field `DAVALID` writer - Dynamic Address Valid"] -pub type DavalidW<'a, REG> = crate::BitWriter<'a, REG, Davalid>; -impl<'a, REG> DavalidW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No valid DA assigned"] - #[inline(always)] - pub fn no_valid(self) -> &'a mut crate::W { - self.variant(Davalid::NoValid) - } - #[doc = "Valid DA assigned"] - #[inline(always)] - pub fn valid(self) -> &'a mut crate::W { - self.variant(Davalid::Valid) - } -} -#[doc = "Field `DADDR` reader - Dynamic Address"] -pub type DaddrR = crate::FieldReader; -#[doc = "Field `DADDR` writer - Dynamic Address"] -pub type DaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bit 0 - Dynamic Address Valid"] - #[inline(always)] - pub fn davalid(&self) -> DavalidR { - DavalidR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:7 - Dynamic Address"] - #[inline(always)] - pub fn daddr(&self) -> DaddrR { - DaddrR::new(((self.bits >> 1) & 0x7f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Dynamic Address Valid"] - #[inline(always)] - pub fn davalid(&mut self) -> DavalidW { - DavalidW::new(self, 0) - } - #[doc = "Bits 1:7 - Dynamic Address"] - #[inline(always)] - pub fn daddr(&mut self) -> DaddrW { - DaddrW::new(self, 1) - } -} -#[doc = "Controller Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mdynaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdynaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MdynaddrSpec; -impl crate::RegisterSpec for MdynaddrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mdynaddr::R`](R) reader structure"] -impl crate::Readable for MdynaddrSpec {} -#[doc = "`write(|w| ..)` method takes [`mdynaddr::W`](W) writer structure"] -impl crate::Writable for MdynaddrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MDYNADDR to value 0"] -impl crate::Resettable for MdynaddrSpec {} diff --git a/mcxa276-pac/src/i3c0/merrwarn.rs b/mcxa276-pac/src/i3c0/merrwarn.rs deleted file mode 100644 index e73710666..000000000 --- a/mcxa276-pac/src/i3c0/merrwarn.rs +++ /dev/null @@ -1,715 +0,0 @@ -#[doc = "Register `MERRWARN` reader"] -pub type R = crate::R; -#[doc = "Register `MERRWARN` writer"] -pub type W = crate::W; -#[doc = "Underrun Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Urun { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Urun) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `URUN` reader - Underrun Error Flag"] -pub type UrunR = crate::BitReader; -impl UrunR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Urun { - match self.bits { - false => Urun::NoError, - true => Urun::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Urun::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Urun::Error - } -} -#[doc = "Field `URUN` writer - Underrun Error Flag"] -pub type UrunW<'a, REG> = crate::BitWriter1C<'a, REG, Urun>; -impl<'a, REG> UrunW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Urun::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Urun::Error) - } -} -#[doc = "Not Acknowledge Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nack { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NACK` reader - Not Acknowledge Error Flag"] -pub type NackR = crate::BitReader; -impl NackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nack { - match self.bits { - false => Nack::NoError, - true => Nack::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Nack::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Nack::Error - } -} -#[doc = "Field `NACK` writer - Not Acknowledge Error Flag"] -pub type NackW<'a, REG> = crate::BitWriter1C<'a, REG, Nack>; -impl<'a, REG> NackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Nack::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Nack::Error) - } -} -#[doc = "Write Abort Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wrabt { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wrabt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WRABT` reader - Write Abort Error Flag"] -pub type WrabtR = crate::BitReader; -impl WrabtR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wrabt { - match self.bits { - false => Wrabt::NoError, - true => Wrabt::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Wrabt::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Wrabt::Error - } -} -#[doc = "Field `WRABT` writer - Write Abort Error Flag"] -pub type WrabtW<'a, REG> = crate::BitWriter1C<'a, REG, Wrabt>; -impl<'a, REG> WrabtW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Wrabt::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Wrabt::Error) - } -} -#[doc = "Terminate Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Term { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Term) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TERM` reader - Terminate Error Flag"] -pub type TermR = crate::BitReader; -impl TermR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Term { - match self.bits { - false => Term::NoError, - true => Term::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Term::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Term::Error - } -} -#[doc = "Field `TERM` writer - Terminate Error Flag"] -pub type TermW<'a, REG> = crate::BitWriter1C<'a, REG, Term>; -impl<'a, REG> TermW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Term::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Term::Error) - } -} -#[doc = "High Data Rate Parity Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hpar { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hpar) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HPAR` reader - High Data Rate Parity Flag"] -pub type HparR = crate::BitReader; -impl HparR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hpar { - match self.bits { - false => Hpar::NoError, - true => Hpar::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Hpar::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Hpar::Error - } -} -#[doc = "Field `HPAR` writer - High Data Rate Parity Flag"] -pub type HparW<'a, REG> = crate::BitWriter1C<'a, REG, Hpar>; -impl<'a, REG> HparW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Hpar::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Hpar::Error) - } -} -#[doc = "High Data Rate CRC Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hcrc { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hcrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HCRC` reader - High Data Rate CRC Error Flag"] -pub type HcrcR = crate::BitReader; -impl HcrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hcrc { - match self.bits { - false => Hcrc::NoError, - true => Hcrc::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Hcrc::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Hcrc::Error - } -} -#[doc = "Field `HCRC` writer - High Data Rate CRC Error Flag"] -pub type HcrcW<'a, REG> = crate::BitWriter1C<'a, REG, Hcrc>; -impl<'a, REG> HcrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Hcrc::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Hcrc::Error) - } -} -#[doc = "Overread Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Oread { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Oread) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OREAD` reader - Overread Error Flag"] -pub type OreadR = crate::BitReader; -impl OreadR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Oread { - match self.bits { - false => Oread::NoError, - true => Oread::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Oread::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Oread::Error - } -} -#[doc = "Field `OREAD` writer - Overread Error Flag"] -pub type OreadW<'a, REG> = crate::BitWriter1C<'a, REG, Oread>; -impl<'a, REG> OreadW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Oread::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Oread::Error) - } -} -#[doc = "Overwrite Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Owrite { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Owrite) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OWRITE` reader - Overwrite Error Flag"] -pub type OwriteR = crate::BitReader; -impl OwriteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Owrite { - match self.bits { - false => Owrite::NoError, - true => Owrite::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Owrite::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Owrite::Error - } -} -#[doc = "Field `OWRITE` writer - Overwrite Error Flag"] -pub type OwriteW<'a, REG> = crate::BitWriter1C<'a, REG, Owrite>; -impl<'a, REG> OwriteW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Owrite::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Owrite::Error) - } -} -#[doc = "Message Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Msgerr { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Msgerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MSGERR` reader - Message Error Flag"] -pub type MsgerrR = crate::BitReader; -impl MsgerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Msgerr { - match self.bits { - false => Msgerr::NoError, - true => Msgerr::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Msgerr::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Msgerr::Error - } -} -#[doc = "Field `MSGERR` writer - Message Error Flag"] -pub type MsgerrW<'a, REG> = crate::BitWriter1C<'a, REG, Msgerr>; -impl<'a, REG> MsgerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Msgerr::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Msgerr::Error) - } -} -#[doc = "Invalid Request Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Invreq { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Invreq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INVREQ` reader - Invalid Request Error Flag"] -pub type InvreqR = crate::BitReader; -impl InvreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Invreq { - match self.bits { - false => Invreq::NoError, - true => Invreq::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Invreq::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Invreq::Error - } -} -#[doc = "Field `INVREQ` writer - Invalid Request Error Flag"] -pub type InvreqW<'a, REG> = crate::BitWriter1C<'a, REG, Invreq>; -impl<'a, REG> InvreqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Invreq::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Invreq::Error) - } -} -#[doc = "Timeout Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Timeout { - #[doc = "0: No error"] - NoError = 0, - #[doc = "1: Error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Timeout) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIMEOUT` reader - Timeout Error Flag"] -pub type TimeoutR = crate::BitReader; -impl TimeoutR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timeout { - match self.bits { - false => Timeout::NoError, - true => Timeout::Error, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Timeout::NoError - } - #[doc = "Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Timeout::Error - } -} -#[doc = "Field `TIMEOUT` writer - Timeout Error Flag"] -pub type TimeoutW<'a, REG> = crate::BitWriter1C<'a, REG, Timeout>; -impl<'a, REG> TimeoutW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Timeout::NoError) - } - #[doc = "Error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Timeout::Error) - } -} -impl R { - #[doc = "Bit 1 - Underrun Error Flag"] - #[inline(always)] - pub fn urun(&self) -> UrunR { - UrunR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Not Acknowledge Error Flag"] - #[inline(always)] - pub fn nack(&self) -> NackR { - NackR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Write Abort Error Flag"] - #[inline(always)] - pub fn wrabt(&self) -> WrabtR { - WrabtR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Terminate Error Flag"] - #[inline(always)] - pub fn term(&self) -> TermR { - TermR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 9 - High Data Rate Parity Flag"] - #[inline(always)] - pub fn hpar(&self) -> HparR { - HparR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - High Data Rate CRC Error Flag"] - #[inline(always)] - pub fn hcrc(&self) -> HcrcR { - HcrcR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 16 - Overread Error Flag"] - #[inline(always)] - pub fn oread(&self) -> OreadR { - OreadR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Overwrite Error Flag"] - #[inline(always)] - pub fn owrite(&self) -> OwriteR { - OwriteR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Message Error Flag"] - #[inline(always)] - pub fn msgerr(&self) -> MsgerrR { - MsgerrR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Invalid Request Error Flag"] - #[inline(always)] - pub fn invreq(&self) -> InvreqR { - InvreqR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Timeout Error Flag"] - #[inline(always)] - pub fn timeout(&self) -> TimeoutR { - TimeoutR::new(((self.bits >> 20) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - Underrun Error Flag"] - #[inline(always)] - pub fn urun(&mut self) -> UrunW { - UrunW::new(self, 1) - } - #[doc = "Bit 2 - Not Acknowledge Error Flag"] - #[inline(always)] - pub fn nack(&mut self) -> NackW { - NackW::new(self, 2) - } - #[doc = "Bit 3 - Write Abort Error Flag"] - #[inline(always)] - pub fn wrabt(&mut self) -> WrabtW { - WrabtW::new(self, 3) - } - #[doc = "Bit 4 - Terminate Error Flag"] - #[inline(always)] - pub fn term(&mut self) -> TermW { - TermW::new(self, 4) - } - #[doc = "Bit 9 - High Data Rate Parity Flag"] - #[inline(always)] - pub fn hpar(&mut self) -> HparW { - HparW::new(self, 9) - } - #[doc = "Bit 10 - High Data Rate CRC Error Flag"] - #[inline(always)] - pub fn hcrc(&mut self) -> HcrcW { - HcrcW::new(self, 10) - } - #[doc = "Bit 16 - Overread Error Flag"] - #[inline(always)] - pub fn oread(&mut self) -> OreadW { - OreadW::new(self, 16) - } - #[doc = "Bit 17 - Overwrite Error Flag"] - #[inline(always)] - pub fn owrite(&mut self) -> OwriteW { - OwriteW::new(self, 17) - } - #[doc = "Bit 18 - Message Error Flag"] - #[inline(always)] - pub fn msgerr(&mut self) -> MsgerrW { - MsgerrW::new(self, 18) - } - #[doc = "Bit 19 - Invalid Request Error Flag"] - #[inline(always)] - pub fn invreq(&mut self) -> InvreqW { - InvreqW::new(self, 19) - } - #[doc = "Bit 20 - Timeout Error Flag"] - #[inline(always)] - pub fn timeout(&mut self) -> TimeoutW { - TimeoutW::new(self, 20) - } -} -#[doc = "Controller Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`merrwarn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`merrwarn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MerrwarnSpec; -impl crate::RegisterSpec for MerrwarnSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`merrwarn::R`](R) reader structure"] -impl crate::Readable for MerrwarnSpec {} -#[doc = "`write(|w| ..)` method takes [`merrwarn::W`](W) writer structure"] -impl crate::Writable for MerrwarnSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_061e; -} -#[doc = "`reset()` method sets MERRWARN to value 0"] -impl crate::Resettable for MerrwarnSpec {} diff --git a/mcxa276-pac/src/i3c0/mibirules.rs b/mcxa276-pac/src/i3c0/mibirules.rs deleted file mode 100644 index 256a57ccd..000000000 --- a/mcxa276-pac/src/i3c0/mibirules.rs +++ /dev/null @@ -1,217 +0,0 @@ -#[doc = "Register `MIBIRULES` reader"] -pub type R = crate::R; -#[doc = "Register `MIBIRULES` writer"] -pub type W = crate::W; -#[doc = "Field `ADDR0` reader - ADDR0"] -pub type Addr0R = crate::FieldReader; -#[doc = "Field `ADDR0` writer - ADDR0"] -pub type Addr0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `ADDR1` reader - ADDR1"] -pub type Addr1R = crate::FieldReader; -#[doc = "Field `ADDR1` writer - ADDR1"] -pub type Addr1W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `ADDR2` reader - ADDR2"] -pub type Addr2R = crate::FieldReader; -#[doc = "Field `ADDR2` writer - ADDR2"] -pub type Addr2W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `ADDR3` reader - ADDR3"] -pub type Addr3R = crate::FieldReader; -#[doc = "Field `ADDR3` writer - ADDR3"] -pub type Addr3W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `ADDR4` reader - ADDR4"] -pub type Addr4R = crate::FieldReader; -#[doc = "Field `ADDR4` writer - ADDR4"] -pub type Addr4W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Most Significant Address Bit is 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Msb0 { - #[doc = "0: MSB is not 0"] - Disable = 0, - #[doc = "1: MSB is 0"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Msb0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MSB0` reader - Most Significant Address Bit is 0"] -pub type Msb0R = crate::BitReader; -impl Msb0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Msb0 { - match self.bits { - false => Msb0::Disable, - true => Msb0::Enable, - } - } - #[doc = "MSB is not 0"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Msb0::Disable - } - #[doc = "MSB is 0"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Msb0::Enable - } -} -#[doc = "Field `MSB0` writer - Most Significant Address Bit is 0"] -pub type Msb0W<'a, REG> = crate::BitWriter<'a, REG, Msb0>; -impl<'a, REG> Msb0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "MSB is not 0"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Msb0::Disable) - } - #[doc = "MSB is 0"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Msb0::Enable) - } -} -#[doc = "No IBI byte\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nobyte { - #[doc = "0: With mandatory IBI byte"] - Ibibyte = 0, - #[doc = "1: Without mandatory IBI byte"] - NoIbibyte = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nobyte) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOBYTE` reader - No IBI byte"] -pub type NobyteR = crate::BitReader; -impl NobyteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nobyte { - match self.bits { - false => Nobyte::Ibibyte, - true => Nobyte::NoIbibyte, - } - } - #[doc = "With mandatory IBI byte"] - #[inline(always)] - pub fn is_ibibyte(&self) -> bool { - *self == Nobyte::Ibibyte - } - #[doc = "Without mandatory IBI byte"] - #[inline(always)] - pub fn is_no_ibibyte(&self) -> bool { - *self == Nobyte::NoIbibyte - } -} -#[doc = "Field `NOBYTE` writer - No IBI byte"] -pub type NobyteW<'a, REG> = crate::BitWriter<'a, REG, Nobyte>; -impl<'a, REG> NobyteW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "With mandatory IBI byte"] - #[inline(always)] - pub fn ibibyte(self) -> &'a mut crate::W { - self.variant(Nobyte::Ibibyte) - } - #[doc = "Without mandatory IBI byte"] - #[inline(always)] - pub fn no_ibibyte(self) -> &'a mut crate::W { - self.variant(Nobyte::NoIbibyte) - } -} -impl R { - #[doc = "Bits 0:5 - ADDR0"] - #[inline(always)] - pub fn addr0(&self) -> Addr0R { - Addr0R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11 - ADDR1"] - #[inline(always)] - pub fn addr1(&self) -> Addr1R { - Addr1R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bits 12:17 - ADDR2"] - #[inline(always)] - pub fn addr2(&self) -> Addr2R { - Addr2R::new(((self.bits >> 12) & 0x3f) as u8) - } - #[doc = "Bits 18:23 - ADDR3"] - #[inline(always)] - pub fn addr3(&self) -> Addr3R { - Addr3R::new(((self.bits >> 18) & 0x3f) as u8) - } - #[doc = "Bits 24:29 - ADDR4"] - #[inline(always)] - pub fn addr4(&self) -> Addr4R { - Addr4R::new(((self.bits >> 24) & 0x3f) as u8) - } - #[doc = "Bit 30 - Most Significant Address Bit is 0"] - #[inline(always)] - pub fn msb0(&self) -> Msb0R { - Msb0R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - No IBI byte"] - #[inline(always)] - pub fn nobyte(&self) -> NobyteR { - NobyteR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - ADDR0"] - #[inline(always)] - pub fn addr0(&mut self) -> Addr0W { - Addr0W::new(self, 0) - } - #[doc = "Bits 6:11 - ADDR1"] - #[inline(always)] - pub fn addr1(&mut self) -> Addr1W { - Addr1W::new(self, 6) - } - #[doc = "Bits 12:17 - ADDR2"] - #[inline(always)] - pub fn addr2(&mut self) -> Addr2W { - Addr2W::new(self, 12) - } - #[doc = "Bits 18:23 - ADDR3"] - #[inline(always)] - pub fn addr3(&mut self) -> Addr3W { - Addr3W::new(self, 18) - } - #[doc = "Bits 24:29 - ADDR4"] - #[inline(always)] - pub fn addr4(&mut self) -> Addr4W { - Addr4W::new(self, 24) - } - #[doc = "Bit 30 - Most Significant Address Bit is 0"] - #[inline(always)] - pub fn msb0(&mut self) -> Msb0W { - Msb0W::new(self, 30) - } - #[doc = "Bit 31 - No IBI byte"] - #[inline(always)] - pub fn nobyte(&mut self) -> NobyteW { - NobyteW::new(self, 31) - } -} -#[doc = "Controller In-band Interrupt Registry and Rules\n\nYou can [`read`](crate::Reg::read) this register and get [`mibirules::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mibirules::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MibirulesSpec; -impl crate::RegisterSpec for MibirulesSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mibirules::R`](R) reader structure"] -impl crate::Readable for MibirulesSpec {} -#[doc = "`write(|w| ..)` method takes [`mibirules::W`](W) writer structure"] -impl crate::Writable for MibirulesSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MIBIRULES to value 0"] -impl crate::Resettable for MibirulesSpec {} diff --git a/mcxa276-pac/src/i3c0/mintclr.rs b/mcxa276-pac/src/i3c0/mintclr.rs deleted file mode 100644 index 21aea1fdf..000000000 --- a/mcxa276-pac/src/i3c0/mintclr.rs +++ /dev/null @@ -1,526 +0,0 @@ -#[doc = "Register `MINTCLR` reader"] -pub type R = crate::R; -#[doc = "Register `MINTCLR` writer"] -pub type W = crate::W; -#[doc = "SLVSTART Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slvstart { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slvstart) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLVSTART` reader - SLVSTART Interrupt Enable Clear Flag"] -pub type SlvstartR = crate::BitReader; -impl SlvstartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slvstart { - match self.bits { - false => Slvstart::None, - true => Slvstart::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Slvstart::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Slvstart::Clear - } -} -#[doc = "Field `SLVSTART` writer - SLVSTART Interrupt Enable Clear Flag"] -pub type SlvstartW<'a, REG> = crate::BitWriter1C<'a, REG, Slvstart>; -impl<'a, REG> SlvstartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Slvstart::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Slvstart::Clear) - } -} -#[doc = "MCTRLDONE Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mctrldone { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mctrldone) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MCTRLDONE` reader - MCTRLDONE Interrupt Enable Clear Flag"] -pub type MctrldoneR = crate::BitReader; -impl MctrldoneR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mctrldone { - match self.bits { - false => Mctrldone::None, - true => Mctrldone::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Mctrldone::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Mctrldone::Clear - } -} -#[doc = "Field `MCTRLDONE` writer - MCTRLDONE Interrupt Enable Clear Flag"] -pub type MctrldoneW<'a, REG> = crate::BitWriter1C<'a, REG, Mctrldone>; -impl<'a, REG> MctrldoneW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Mctrldone::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Mctrldone::Clear) - } -} -#[doc = "COMPLETE Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Complete { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Complete) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPLETE` reader - COMPLETE Interrupt Enable Clear Flag"] -pub type CompleteR = crate::BitReader; -impl CompleteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Complete { - match self.bits { - false => Complete::None, - true => Complete::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Complete::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Complete::Clear - } -} -#[doc = "Field `COMPLETE` writer - COMPLETE Interrupt Enable Clear Flag"] -pub type CompleteW<'a, REG> = crate::BitWriter1C<'a, REG, Complete>; -impl<'a, REG> CompleteW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Complete::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Complete::Clear) - } -} -#[doc = "RXPEND Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxpend { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxpend) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXPEND` reader - RXPEND Interrupt Enable Clear Flag"] -pub type RxpendR = crate::BitReader; -impl RxpendR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxpend { - match self.bits { - false => Rxpend::None, - true => Rxpend::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Rxpend::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Rxpend::Clear - } -} -#[doc = "Field `RXPEND` writer - RXPEND Interrupt Enable Clear Flag"] -pub type RxpendW<'a, REG> = crate::BitWriter1C<'a, REG, Rxpend>; -impl<'a, REG> RxpendW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Rxpend::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Rxpend::Clear) - } -} -#[doc = "TXNOTFULL Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txnotfull { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txnotfull) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXNOTFULL` reader - TXNOTFULL Interrupt Enable Clear Flag"] -pub type TxnotfullR = crate::BitReader; -impl TxnotfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txnotfull { - match self.bits { - false => Txnotfull::None, - true => Txnotfull::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Txnotfull::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Txnotfull::Clear - } -} -#[doc = "Field `TXNOTFULL` writer - TXNOTFULL Interrupt Enable Clear Flag"] -pub type TxnotfullW<'a, REG> = crate::BitWriter1C<'a, REG, Txnotfull>; -impl<'a, REG> TxnotfullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Txnotfull::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Txnotfull::Clear) - } -} -#[doc = "IBIWON Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibiwon { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibiwon) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBIWON` reader - IBIWON Interrupt Enable Clear Flag"] -pub type IbiwonR = crate::BitReader; -impl IbiwonR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibiwon { - match self.bits { - false => Ibiwon::None, - true => Ibiwon::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Ibiwon::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Ibiwon::Clear - } -} -#[doc = "Field `IBIWON` writer - IBIWON Interrupt Enable Clear Flag"] -pub type IbiwonW<'a, REG> = crate::BitWriter1C<'a, REG, Ibiwon>; -impl<'a, REG> IbiwonW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Ibiwon::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Ibiwon::Clear) - } -} -#[doc = "ERRWARN Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errwarn { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errwarn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Enable Clear Flag"] -pub type ErrwarnR = crate::BitReader; -impl ErrwarnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errwarn { - match self.bits { - false => Errwarn::None, - true => Errwarn::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Errwarn::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Errwarn::Clear - } -} -#[doc = "Field `ERRWARN` writer - ERRWARN Interrupt Enable Clear Flag"] -pub type ErrwarnW<'a, REG> = crate::BitWriter1C<'a, REG, Errwarn>; -impl<'a, REG> ErrwarnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Errwarn::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Errwarn::Clear) - } -} -#[doc = "NOWCONTROLLER Interrupt Enable Clear Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nowmaster { - #[doc = "0: No effect"] - None = 0, - #[doc = "1: Interrupt enable cleared"] - Clear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nowmaster) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOWMASTER` reader - NOWCONTROLLER Interrupt Enable Clear Flag"] -pub type NowmasterR = crate::BitReader; -impl NowmasterR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nowmaster { - match self.bits { - false => Nowmaster::None, - true => Nowmaster::Clear, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Nowmaster::None - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Nowmaster::Clear - } -} -#[doc = "Field `NOWMASTER` writer - NOWCONTROLLER Interrupt Enable Clear Flag"] -pub type NowmasterW<'a, REG> = crate::BitWriter1C<'a, REG, Nowmaster>; -impl<'a, REG> NowmasterW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Nowmaster::None) - } - #[doc = "Interrupt enable cleared"] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Nowmaster::Clear) - } -} -impl R { - #[doc = "Bit 8 - SLVSTART Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn slvstart(&self) -> SlvstartR { - SlvstartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - MCTRLDONE Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn mctrldone(&self) -> MctrldoneR { - MctrldoneR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - COMPLETE Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn complete(&self) -> CompleteR { - CompleteR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn rxpend(&self) -> RxpendR { - RxpendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - TXNOTFULL Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn txnotfull(&self) -> TxnotfullR { - TxnotfullR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - IBIWON Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn ibiwon(&self) -> IbiwonR { - IbiwonR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 19 - NOWCONTROLLER Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn nowmaster(&self) -> NowmasterR { - NowmasterR::new(((self.bits >> 19) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - SLVSTART Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn slvstart(&mut self) -> SlvstartW { - SlvstartW::new(self, 8) - } - #[doc = "Bit 9 - MCTRLDONE Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn mctrldone(&mut self) -> MctrldoneW { - MctrldoneW::new(self, 9) - } - #[doc = "Bit 10 - COMPLETE Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn complete(&mut self) -> CompleteW { - CompleteW::new(self, 10) - } - #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn rxpend(&mut self) -> RxpendW { - RxpendW::new(self, 11) - } - #[doc = "Bit 12 - TXNOTFULL Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn txnotfull(&mut self) -> TxnotfullW { - TxnotfullW::new(self, 12) - } - #[doc = "Bit 13 - IBIWON Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn ibiwon(&mut self) -> IbiwonW { - IbiwonW::new(self, 13) - } - #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn errwarn(&mut self) -> ErrwarnW { - ErrwarnW::new(self, 15) - } - #[doc = "Bit 19 - NOWCONTROLLER Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn nowmaster(&mut self) -> NowmasterW { - NowmasterW::new(self, 19) - } -} -#[doc = "Controller Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`mintclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MintclrSpec; -impl crate::RegisterSpec for MintclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mintclr::R`](R) reader structure"] -impl crate::Readable for MintclrSpec {} -#[doc = "`write(|w| ..)` method takes [`mintclr::W`](W) writer structure"] -impl crate::Writable for MintclrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0008_bf00; -} -#[doc = "`reset()` method sets MINTCLR to value 0"] -impl crate::Resettable for MintclrSpec {} diff --git a/mcxa276-pac/src/i3c0/mintmasked.rs b/mcxa276-pac/src/i3c0/mintmasked.rs deleted file mode 100644 index eb4e620b5..000000000 --- a/mcxa276-pac/src/i3c0/mintmasked.rs +++ /dev/null @@ -1,307 +0,0 @@ -#[doc = "Register `MINTMASKED` reader"] -pub type R = crate::R; -#[doc = "SLVSTART Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slvstart { - #[doc = "0: Disabled"] - NotEnabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slvstart) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLVSTART` reader - SLVSTART Interrupt Mask"] -pub type SlvstartR = crate::BitReader; -impl SlvstartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slvstart { - match self.bits { - false => Slvstart::NotEnabled, - true => Slvstart::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_not_enabled(&self) -> bool { - *self == Slvstart::NotEnabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Slvstart::Enabled - } -} -#[doc = "MCTRLDONE Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mctrldone { - #[doc = "0: Disabled"] - NotEnabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mctrldone) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MCTRLDONE` reader - MCTRLDONE Interrupt Mask"] -pub type MctrldoneR = crate::BitReader; -impl MctrldoneR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mctrldone { - match self.bits { - false => Mctrldone::NotEnabled, - true => Mctrldone::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_not_enabled(&self) -> bool { - *self == Mctrldone::NotEnabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Mctrldone::Enabled - } -} -#[doc = "COMPLETE Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Complete { - #[doc = "0: Disabled"] - NotEnabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Complete) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPLETE` reader - COMPLETE Interrupt Mask"] -pub type CompleteR = crate::BitReader; -impl CompleteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Complete { - match self.bits { - false => Complete::NotEnabled, - true => Complete::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_not_enabled(&self) -> bool { - *self == Complete::NotEnabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Complete::Enabled - } -} -#[doc = "Field `RXPEND` reader - RXPEND Interrupt Mask"] -pub type RxpendR = crate::BitReader; -#[doc = "TXNOTFULL Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txnotfull { - #[doc = "0: Disabled"] - NotEnabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txnotfull) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXNOTFULL` reader - TXNOTFULL Interrupt Mask"] -pub type TxnotfullR = crate::BitReader; -impl TxnotfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txnotfull { - match self.bits { - false => Txnotfull::NotEnabled, - true => Txnotfull::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_not_enabled(&self) -> bool { - *self == Txnotfull::NotEnabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Txnotfull::Enabled - } -} -#[doc = "IBIWON Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibiwon { - #[doc = "0: Disabled"] - NotEnabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibiwon) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBIWON` reader - IBIWON Interrupt Mask"] -pub type IbiwonR = crate::BitReader; -impl IbiwonR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibiwon { - match self.bits { - false => Ibiwon::NotEnabled, - true => Ibiwon::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_not_enabled(&self) -> bool { - *self == Ibiwon::NotEnabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ibiwon::Enabled - } -} -#[doc = "ERRWARN Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errwarn { - #[doc = "0: Disabled"] - NotEnabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errwarn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Mask"] -pub type ErrwarnR = crate::BitReader; -impl ErrwarnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errwarn { - match self.bits { - false => Errwarn::NotEnabled, - true => Errwarn::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_not_enabled(&self) -> bool { - *self == Errwarn::NotEnabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Errwarn::Enabled - } -} -#[doc = "NOWCONTROLLER Interrupt Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nowmaster { - #[doc = "0: Disabled"] - NotEnabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nowmaster) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOWMASTER` reader - NOWCONTROLLER Interrupt Mask"] -pub type NowmasterR = crate::BitReader; -impl NowmasterR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nowmaster { - match self.bits { - false => Nowmaster::NotEnabled, - true => Nowmaster::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_not_enabled(&self) -> bool { - *self == Nowmaster::NotEnabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Nowmaster::Enabled - } -} -impl R { - #[doc = "Bit 8 - SLVSTART Interrupt Mask"] - #[inline(always)] - pub fn slvstart(&self) -> SlvstartR { - SlvstartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - MCTRLDONE Interrupt Mask"] - #[inline(always)] - pub fn mctrldone(&self) -> MctrldoneR { - MctrldoneR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - COMPLETE Interrupt Mask"] - #[inline(always)] - pub fn complete(&self) -> CompleteR { - CompleteR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - RXPEND Interrupt Mask"] - #[inline(always)] - pub fn rxpend(&self) -> RxpendR { - RxpendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - TXNOTFULL Interrupt Mask"] - #[inline(always)] - pub fn txnotfull(&self) -> TxnotfullR { - TxnotfullR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - IBIWON Interrupt Mask"] - #[inline(always)] - pub fn ibiwon(&self) -> IbiwonR { - IbiwonR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - ERRWARN Interrupt Mask"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 19 - NOWCONTROLLER Interrupt Mask"] - #[inline(always)] - pub fn nowmaster(&self) -> NowmasterR { - NowmasterR::new(((self.bits >> 19) & 1) != 0) - } -} -#[doc = "Controller Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`mintmasked::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MintmaskedSpec; -impl crate::RegisterSpec for MintmaskedSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mintmasked::R`](R) reader structure"] -impl crate::Readable for MintmaskedSpec {} -#[doc = "`reset()` method sets MINTMASKED to value 0"] -impl crate::Resettable for MintmaskedSpec {} diff --git a/mcxa276-pac/src/i3c0/mintset.rs b/mcxa276-pac/src/i3c0/mintset.rs deleted file mode 100644 index 3235bf681..000000000 --- a/mcxa276-pac/src/i3c0/mintset.rs +++ /dev/null @@ -1,477 +0,0 @@ -#[doc = "Register `MINTSET` reader"] -pub type R = crate::R; -#[doc = "Register `MINTSET` writer"] -pub type W = crate::W; -#[doc = "Target Start Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slvstart { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slvstart) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLVSTART` reader - Target Start Interrupt Enable"] -pub type SlvstartR = crate::BitReader; -impl SlvstartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slvstart { - match self.bits { - false => Slvstart::Disable, - true => Slvstart::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Slvstart::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Slvstart::Enable - } -} -#[doc = "Field `SLVSTART` writer - Target Start Interrupt Enable"] -pub type SlvstartW<'a, REG> = crate::BitWriter1S<'a, REG, Slvstart>; -impl<'a, REG> SlvstartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Slvstart::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Slvstart::Enable) - } -} -#[doc = "Controller Control Done Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mctrldone { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mctrldone) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MCTRLDONE` reader - Controller Control Done Interrupt Enable"] -pub type MctrldoneR = crate::BitReader; -impl MctrldoneR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mctrldone { - match self.bits { - false => Mctrldone::Disable, - true => Mctrldone::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Mctrldone::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Mctrldone::Enable - } -} -#[doc = "Field `MCTRLDONE` writer - Controller Control Done Interrupt Enable"] -pub type MctrldoneW<'a, REG> = crate::BitWriter1S<'a, REG, Mctrldone>; -impl<'a, REG> MctrldoneW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Mctrldone::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Mctrldone::Enable) - } -} -#[doc = "Completed Message Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Complete { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Complete) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPLETE` reader - Completed Message Interrupt Enable"] -pub type CompleteR = crate::BitReader; -impl CompleteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Complete { - match self.bits { - false => Complete::Disable, - true => Complete::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Complete::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Complete::Enable - } -} -#[doc = "Field `COMPLETE` writer - Completed Message Interrupt Enable"] -pub type CompleteW<'a, REG> = crate::BitWriter1S<'a, REG, Complete>; -impl<'a, REG> CompleteW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Complete::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Complete::Enable) - } -} -#[doc = "Field `RXPEND` reader - Receive Pending Interrupt Enable"] -pub type RxpendR = crate::BitReader; -#[doc = "Field `RXPEND` writer - Receive Pending Interrupt Enable"] -pub type RxpendW<'a, REG> = crate::BitWriter1S<'a, REG>; -#[doc = "Transmit Buffer/FIFO Not Full Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txnotfull { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txnotfull) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXNOTFULL` reader - Transmit Buffer/FIFO Not Full Interrupt Enable"] -pub type TxnotfullR = crate::BitReader; -impl TxnotfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txnotfull { - match self.bits { - false => Txnotfull::Disable, - true => Txnotfull::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Txnotfull::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Txnotfull::Enable - } -} -#[doc = "Field `TXNOTFULL` writer - Transmit Buffer/FIFO Not Full Interrupt Enable"] -pub type TxnotfullW<'a, REG> = crate::BitWriter1S<'a, REG, Txnotfull>; -impl<'a, REG> TxnotfullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Txnotfull::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Txnotfull::Enable) - } -} -#[doc = "IBI Won Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibiwon { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibiwon) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBIWON` reader - IBI Won Interrupt Enable"] -pub type IbiwonR = crate::BitReader; -impl IbiwonR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibiwon { - match self.bits { - false => Ibiwon::Disable, - true => Ibiwon::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ibiwon::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ibiwon::Enable - } -} -#[doc = "Field `IBIWON` writer - IBI Won Interrupt Enable"] -pub type IbiwonW<'a, REG> = crate::BitWriter1S<'a, REG, Ibiwon>; -impl<'a, REG> IbiwonW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ibiwon::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ibiwon::Enable) - } -} -#[doc = "Error or Warning (ERRWARN) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errwarn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errwarn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRWARN` reader - Error or Warning (ERRWARN) Interrupt Enable"] -pub type ErrwarnR = crate::BitReader; -impl ErrwarnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errwarn { - match self.bits { - false => Errwarn::Disable, - true => Errwarn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Errwarn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Errwarn::Enable - } -} -#[doc = "Field `ERRWARN` writer - Error or Warning (ERRWARN) Interrupt Enable"] -pub type ErrwarnW<'a, REG> = crate::BitWriter1S<'a, REG, Errwarn>; -impl<'a, REG> ErrwarnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Errwarn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Errwarn::Enable) - } -} -#[doc = "Now Controller Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nowmaster { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nowmaster) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOWMASTER` reader - Now Controller Interrupt Enable"] -pub type NowmasterR = crate::BitReader; -impl NowmasterR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nowmaster { - match self.bits { - false => Nowmaster::Disable, - true => Nowmaster::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Nowmaster::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Nowmaster::Enable - } -} -#[doc = "Field `NOWMASTER` writer - Now Controller Interrupt Enable"] -pub type NowmasterW<'a, REG> = crate::BitWriter1S<'a, REG, Nowmaster>; -impl<'a, REG> NowmasterW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Nowmaster::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Nowmaster::Enable) - } -} -impl R { - #[doc = "Bit 8 - Target Start Interrupt Enable"] - #[inline(always)] - pub fn slvstart(&self) -> SlvstartR { - SlvstartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Controller Control Done Interrupt Enable"] - #[inline(always)] - pub fn mctrldone(&self) -> MctrldoneR { - MctrldoneR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Completed Message Interrupt Enable"] - #[inline(always)] - pub fn complete(&self) -> CompleteR { - CompleteR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Receive Pending Interrupt Enable"] - #[inline(always)] - pub fn rxpend(&self) -> RxpendR { - RxpendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Transmit Buffer/FIFO Not Full Interrupt Enable"] - #[inline(always)] - pub fn txnotfull(&self) -> TxnotfullR { - TxnotfullR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - IBI Won Interrupt Enable"] - #[inline(always)] - pub fn ibiwon(&self) -> IbiwonR { - IbiwonR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Error or Warning (ERRWARN) Interrupt Enable"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 19 - Now Controller Interrupt Enable"] - #[inline(always)] - pub fn nowmaster(&self) -> NowmasterR { - NowmasterR::new(((self.bits >> 19) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - Target Start Interrupt Enable"] - #[inline(always)] - pub fn slvstart(&mut self) -> SlvstartW { - SlvstartW::new(self, 8) - } - #[doc = "Bit 9 - Controller Control Done Interrupt Enable"] - #[inline(always)] - pub fn mctrldone(&mut self) -> MctrldoneW { - MctrldoneW::new(self, 9) - } - #[doc = "Bit 10 - Completed Message Interrupt Enable"] - #[inline(always)] - pub fn complete(&mut self) -> CompleteW { - CompleteW::new(self, 10) - } - #[doc = "Bit 11 - Receive Pending Interrupt Enable"] - #[inline(always)] - pub fn rxpend(&mut self) -> RxpendW { - RxpendW::new(self, 11) - } - #[doc = "Bit 12 - Transmit Buffer/FIFO Not Full Interrupt Enable"] - #[inline(always)] - pub fn txnotfull(&mut self) -> TxnotfullW { - TxnotfullW::new(self, 12) - } - #[doc = "Bit 13 - IBI Won Interrupt Enable"] - #[inline(always)] - pub fn ibiwon(&mut self) -> IbiwonW { - IbiwonW::new(self, 13) - } - #[doc = "Bit 15 - Error or Warning (ERRWARN) Interrupt Enable"] - #[inline(always)] - pub fn errwarn(&mut self) -> ErrwarnW { - ErrwarnW::new(self, 15) - } - #[doc = "Bit 19 - Now Controller Interrupt Enable"] - #[inline(always)] - pub fn nowmaster(&mut self) -> NowmasterW { - NowmasterW::new(self, 19) - } -} -#[doc = "Controller Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`mintset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mintset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MintsetSpec; -impl crate::RegisterSpec for MintsetSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mintset::R`](R) reader structure"] -impl crate::Readable for MintsetSpec {} -#[doc = "`write(|w| ..)` method takes [`mintset::W`](W) writer structure"] -impl crate::Writable for MintsetSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0008_bf00; -} -#[doc = "`reset()` method sets MINTSET to value 0"] -impl crate::Resettable for MintsetSpec {} diff --git a/mcxa276-pac/src/i3c0/mrdatab.rs b/mcxa276-pac/src/i3c0/mrdatab.rs deleted file mode 100644 index 25437af63..000000000 --- a/mcxa276-pac/src/i3c0/mrdatab.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `MRDATAB` reader"] -pub type R = crate::R; -#[doc = "Field `VALUE` reader - Value"] -pub type ValueR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Value"] - #[inline(always)] - pub fn value(&self) -> ValueR { - ValueR::new((self.bits & 0xff) as u8) - } -} -#[doc = "Controller Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatab::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrdatabSpec; -impl crate::RegisterSpec for MrdatabSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrdatab::R`](R) reader structure"] -impl crate::Readable for MrdatabSpec {} -#[doc = "`reset()` method sets MRDATAB to value 0"] -impl crate::Resettable for MrdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/mrdatah.rs b/mcxa276-pac/src/i3c0/mrdatah.rs deleted file mode 100644 index 4de10af62..000000000 --- a/mcxa276-pac/src/i3c0/mrdatah.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `MRDATAH` reader"] -pub type R = crate::R; -#[doc = "Field `LSB` reader - Low Byte"] -pub type LsbR = crate::FieldReader; -#[doc = "Field `MSB` reader - High Byte"] -pub type MsbR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Low Byte"] - #[inline(always)] - pub fn lsb(&self) -> LsbR { - LsbR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - High Byte"] - #[inline(always)] - pub fn msb(&self) -> MsbR { - MsbR::new(((self.bits >> 8) & 0xff) as u8) - } -} -#[doc = "Controller Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdatah::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrdatahSpec; -impl crate::RegisterSpec for MrdatahSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrdatah::R`](R) reader structure"] -impl crate::Readable for MrdatahSpec {} -#[doc = "`reset()` method sets MRDATAH to value 0"] -impl crate::Resettable for MrdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/mrmsg_ddr.rs b/mcxa276-pac/src/i3c0/mrmsg_ddr.rs deleted file mode 100644 index 611d4d5e7..000000000 --- a/mcxa276-pac/src/i3c0/mrmsg_ddr.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `MRMSG_DDR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Data"] -pub type DataR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0xffff) as u16) - } -} -#[doc = "Controller Read Message in DDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_ddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrmsgDdrSpec; -impl crate::RegisterSpec for MrmsgDdrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrmsg_ddr::R`](R) reader structure"] -impl crate::Readable for MrmsgDdrSpec {} -#[doc = "`reset()` method sets MRMSG_DDR to value 0"] -impl crate::Resettable for MrmsgDdrSpec {} diff --git a/mcxa276-pac/src/i3c0/mrmsg_sdr.rs b/mcxa276-pac/src/i3c0/mrmsg_sdr.rs deleted file mode 100644 index b867262f4..000000000 --- a/mcxa276-pac/src/i3c0/mrmsg_sdr.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `MRMSG_SDR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Data"] -pub type DataR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0xffff) as u16) - } -} -#[doc = "Controller Read Message in SDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_sdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrmsgSdrSpec; -impl crate::RegisterSpec for MrmsgSdrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrmsg_sdr::R`](R) reader structure"] -impl crate::Readable for MrmsgSdrSpec {} -#[doc = "`reset()` method sets MRMSG_SDR to value 0"] -impl crate::Resettable for MrmsgSdrSpec {} diff --git a/mcxa276-pac/src/i3c0/mstatus.rs b/mcxa276-pac/src/i3c0/mstatus.rs deleted file mode 100644 index 20d7cf0b1..000000000 --- a/mcxa276-pac/src/i3c0/mstatus.rs +++ /dev/null @@ -1,709 +0,0 @@ -#[doc = "Register `MSTATUS` reader"] -pub type R = crate::R; -#[doc = "Register `MSTATUS` writer"] -pub type W = crate::W; -#[doc = "State of the Controller\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum State { - #[doc = "0: IDLE (bus has stopped)"] - Idle = 0, - #[doc = "1: SLVREQ (target request)"] - Slvreq = 1, - #[doc = "2: MSGSDR"] - Msgsdr = 2, - #[doc = "3: NORMACT"] - Normact = 3, - #[doc = "4: MSGDDR"] - Ddr = 4, - #[doc = "5: DAA"] - Daa = 5, - #[doc = "6: IBIACK"] - Ibiack = 6, - #[doc = "7: IBIRCV"] - Ibircv = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: State) -> Self { - variant as _ - } -} -impl crate::FieldSpec for State { - type Ux = u8; -} -impl crate::IsEnum for State {} -#[doc = "Field `STATE` reader - State of the Controller"] -pub type StateR = crate::FieldReader; -impl StateR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> State { - match self.bits { - 0 => State::Idle, - 1 => State::Slvreq, - 2 => State::Msgsdr, - 3 => State::Normact, - 4 => State::Ddr, - 5 => State::Daa, - 6 => State::Ibiack, - 7 => State::Ibircv, - _ => unreachable!(), - } - } - #[doc = "IDLE (bus has stopped)"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == State::Idle - } - #[doc = "SLVREQ (target request)"] - #[inline(always)] - pub fn is_slvreq(&self) -> bool { - *self == State::Slvreq - } - #[doc = "MSGSDR"] - #[inline(always)] - pub fn is_msgsdr(&self) -> bool { - *self == State::Msgsdr - } - #[doc = "NORMACT"] - #[inline(always)] - pub fn is_normact(&self) -> bool { - *self == State::Normact - } - #[doc = "MSGDDR"] - #[inline(always)] - pub fn is_ddr(&self) -> bool { - *self == State::Ddr - } - #[doc = "DAA"] - #[inline(always)] - pub fn is_daa(&self) -> bool { - *self == State::Daa - } - #[doc = "IBIACK"] - #[inline(always)] - pub fn is_ibiack(&self) -> bool { - *self == State::Ibiack - } - #[doc = "IBIRCV"] - #[inline(always)] - pub fn is_ibircv(&self) -> bool { - *self == State::Ibircv - } -} -#[doc = "Between\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Between { - #[doc = "0: Inactive (for other cases)"] - Inactive = 0, - #[doc = "1: Active"] - Active = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Between) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BETWEEN` reader - Between"] -pub type BetweenR = crate::BitReader; -impl BetweenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Between { - match self.bits { - false => Between::Inactive, - true => Between::Active, - } - } - #[doc = "Inactive (for other cases)"] - #[inline(always)] - pub fn is_inactive(&self) -> bool { - *self == Between::Inactive - } - #[doc = "Active"] - #[inline(always)] - pub fn is_active(&self) -> bool { - *self == Between::Active - } -} -#[doc = "Not Acknowledged\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nacked { - #[doc = "0: Not NACKed"] - NotNacked = 0, - #[doc = "1: NACKed (not acknowledged)"] - Nacked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nacked) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NACKED` reader - Not Acknowledged"] -pub type NackedR = crate::BitReader; -impl NackedR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nacked { - match self.bits { - false => Nacked::NotNacked, - true => Nacked::Nacked, - } - } - #[doc = "Not NACKed"] - #[inline(always)] - pub fn is_not_nacked(&self) -> bool { - *self == Nacked::NotNacked - } - #[doc = "NACKed (not acknowledged)"] - #[inline(always)] - pub fn is_nacked(&self) -> bool { - *self == Nacked::Nacked - } -} -#[doc = "In-Band Interrupt (IBI) Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ibitype { - #[doc = "0: NONE (no IBI: this status occurs when MSTATUS\\[IBIWON\\] becomes 0)"] - None = 0, - #[doc = "1: IBI"] - Ibi = 1, - #[doc = "2: CR"] - Mr = 2, - #[doc = "3: HJ"] - Hj = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ibitype) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ibitype { - type Ux = u8; -} -impl crate::IsEnum for Ibitype {} -#[doc = "Field `IBITYPE` reader - In-Band Interrupt (IBI) Type"] -pub type IbitypeR = crate::FieldReader; -impl IbitypeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibitype { - match self.bits { - 0 => Ibitype::None, - 1 => Ibitype::Ibi, - 2 => Ibitype::Mr, - 3 => Ibitype::Hj, - _ => unreachable!(), - } - } - #[doc = "NONE (no IBI: this status occurs when MSTATUS\\[IBIWON\\] becomes 0)"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Ibitype::None - } - #[doc = "IBI"] - #[inline(always)] - pub fn is_ibi(&self) -> bool { - *self == Ibitype::Ibi - } - #[doc = "CR"] - #[inline(always)] - pub fn is_mr(&self) -> bool { - *self == Ibitype::Mr - } - #[doc = "HJ"] - #[inline(always)] - pub fn is_hj(&self) -> bool { - *self == Ibitype::Hj - } -} -#[doc = "Target Start Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slvstart { - #[doc = "0: Target not requesting START"] - NotStart = 0, - #[doc = "1: Target requesting START"] - Start = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slvstart) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLVSTART` reader - Target Start Flag"] -pub type SlvstartR = crate::BitReader; -impl SlvstartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slvstart { - match self.bits { - false => Slvstart::NotStart, - true => Slvstart::Start, - } - } - #[doc = "Target not requesting START"] - #[inline(always)] - pub fn is_not_start(&self) -> bool { - *self == Slvstart::NotStart - } - #[doc = "Target requesting START"] - #[inline(always)] - pub fn is_start(&self) -> bool { - *self == Slvstart::Start - } -} -#[doc = "Field `SLVSTART` writer - Target Start Flag"] -pub type SlvstartW<'a, REG> = crate::BitWriter1C<'a, REG, Slvstart>; -impl<'a, REG> SlvstartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Target not requesting START"] - #[inline(always)] - pub fn not_start(self) -> &'a mut crate::W { - self.variant(Slvstart::NotStart) - } - #[doc = "Target requesting START"] - #[inline(always)] - pub fn start(self) -> &'a mut crate::W { - self.variant(Slvstart::Start) - } -} -#[doc = "Controller Control Done Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mctrldone { - #[doc = "0: Not done"] - NotDone = 0, - #[doc = "1: Done"] - Done = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mctrldone) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MCTRLDONE` reader - Controller Control Done Flag"] -pub type MctrldoneR = crate::BitReader; -impl MctrldoneR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mctrldone { - match self.bits { - false => Mctrldone::NotDone, - true => Mctrldone::Done, - } - } - #[doc = "Not done"] - #[inline(always)] - pub fn is_not_done(&self) -> bool { - *self == Mctrldone::NotDone - } - #[doc = "Done"] - #[inline(always)] - pub fn is_done(&self) -> bool { - *self == Mctrldone::Done - } -} -#[doc = "Field `MCTRLDONE` writer - Controller Control Done Flag"] -pub type MctrldoneW<'a, REG> = crate::BitWriter1C<'a, REG, Mctrldone>; -impl<'a, REG> MctrldoneW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not done"] - #[inline(always)] - pub fn not_done(self) -> &'a mut crate::W { - self.variant(Mctrldone::NotDone) - } - #[doc = "Done"] - #[inline(always)] - pub fn done(self) -> &'a mut crate::W { - self.variant(Mctrldone::Done) - } -} -#[doc = "Complete Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Complete { - #[doc = "0: Not complete"] - NotComplete = 0, - #[doc = "1: Complete"] - Complete = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Complete) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COMPLETE` reader - Complete Flag"] -pub type CompleteR = crate::BitReader; -impl CompleteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Complete { - match self.bits { - false => Complete::NotComplete, - true => Complete::Complete, - } - } - #[doc = "Not complete"] - #[inline(always)] - pub fn is_not_complete(&self) -> bool { - *self == Complete::NotComplete - } - #[doc = "Complete"] - #[inline(always)] - pub fn is_complete(&self) -> bool { - *self == Complete::Complete - } -} -#[doc = "Field `COMPLETE` writer - Complete Flag"] -pub type CompleteW<'a, REG> = crate::BitWriter1C<'a, REG, Complete>; -impl<'a, REG> CompleteW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not complete"] - #[inline(always)] - pub fn not_complete(self) -> &'a mut crate::W { - self.variant(Complete::NotComplete) - } - #[doc = "Complete"] - #[inline(always)] - pub fn complete(self) -> &'a mut crate::W { - self.variant(Complete::Complete) - } -} -#[doc = "RXPEND\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxpend { - #[doc = "0: No receive message pending"] - Idle = 0, - #[doc = "1: Receive message pending"] - Pending = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxpend) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXPEND` reader - RXPEND"] -pub type RxpendR = crate::BitReader; -impl RxpendR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxpend { - match self.bits { - false => Rxpend::Idle, - true => Rxpend::Pending, - } - } - #[doc = "No receive message pending"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Rxpend::Idle - } - #[doc = "Receive message pending"] - #[inline(always)] - pub fn is_pending(&self) -> bool { - *self == Rxpend::Pending - } -} -#[doc = "TX Buffer or FIFO Not Full\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txnotfull { - #[doc = "0: Receive buffer or FIFO full"] - Full = 0, - #[doc = "1: Receive buffer or FIFO not full"] - Notfull = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txnotfull) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXNOTFULL` reader - TX Buffer or FIFO Not Full"] -pub type TxnotfullR = crate::BitReader; -impl TxnotfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txnotfull { - match self.bits { - false => Txnotfull::Full, - true => Txnotfull::Notfull, - } - } - #[doc = "Receive buffer or FIFO full"] - #[inline(always)] - pub fn is_full(&self) -> bool { - *self == Txnotfull::Full - } - #[doc = "Receive buffer or FIFO not full"] - #[inline(always)] - pub fn is_notfull(&self) -> bool { - *self == Txnotfull::Notfull - } -} -#[doc = "In-Band Interrupt (IBI) Won Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibiwon { - #[doc = "0: No IBI arbitration won"] - NotWon = 0, - #[doc = "1: IBI arbitration won"] - Won = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibiwon) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBIWON` reader - In-Band Interrupt (IBI) Won Flag"] -pub type IbiwonR = crate::BitReader; -impl IbiwonR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibiwon { - match self.bits { - false => Ibiwon::NotWon, - true => Ibiwon::Won, - } - } - #[doc = "No IBI arbitration won"] - #[inline(always)] - pub fn is_not_won(&self) -> bool { - *self == Ibiwon::NotWon - } - #[doc = "IBI arbitration won"] - #[inline(always)] - pub fn is_won(&self) -> bool { - *self == Ibiwon::Won - } -} -#[doc = "Field `IBIWON` writer - In-Band Interrupt (IBI) Won Flag"] -pub type IbiwonW<'a, REG> = crate::BitWriter1C<'a, REG, Ibiwon>; -impl<'a, REG> IbiwonW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No IBI arbitration won"] - #[inline(always)] - pub fn not_won(self) -> &'a mut crate::W { - self.variant(Ibiwon::NotWon) - } - #[doc = "IBI arbitration won"] - #[inline(always)] - pub fn won(self) -> &'a mut crate::W { - self.variant(Ibiwon::Won) - } -} -#[doc = "Error or Warning\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errwarn { - #[doc = "0: No error or warning"] - NoError = 0, - #[doc = "1: Error or warning"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errwarn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRWARN` reader - Error or Warning"] -pub type ErrwarnR = crate::BitReader; -impl ErrwarnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errwarn { - match self.bits { - false => Errwarn::NoError, - true => Errwarn::Error, - } - } - #[doc = "No error or warning"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Errwarn::NoError - } - #[doc = "Error or warning"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Errwarn::Error - } -} -#[doc = "Module is now Controller Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nowmaster { - #[doc = "0: Not a controller"] - NotMaster = 0, - #[doc = "1: Controller"] - Master = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nowmaster) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOWMASTER` reader - Module is now Controller Flag"] -pub type NowmasterR = crate::BitReader; -impl NowmasterR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nowmaster { - match self.bits { - false => Nowmaster::NotMaster, - true => Nowmaster::Master, - } - } - #[doc = "Not a controller"] - #[inline(always)] - pub fn is_not_master(&self) -> bool { - *self == Nowmaster::NotMaster - } - #[doc = "Controller"] - #[inline(always)] - pub fn is_master(&self) -> bool { - *self == Nowmaster::Master - } -} -#[doc = "Field `NOWMASTER` writer - Module is now Controller Flag"] -pub type NowmasterW<'a, REG> = crate::BitWriter1C<'a, REG, Nowmaster>; -impl<'a, REG> NowmasterW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not a controller"] - #[inline(always)] - pub fn not_master(self) -> &'a mut crate::W { - self.variant(Nowmaster::NotMaster) - } - #[doc = "Controller"] - #[inline(always)] - pub fn master(self) -> &'a mut crate::W { - self.variant(Nowmaster::Master) - } -} -#[doc = "Field `IBIADDR` reader - IBI Address"] -pub type IbiaddrR = crate::FieldReader; -impl R { - #[doc = "Bits 0:2 - State of the Controller"] - #[inline(always)] - pub fn state(&self) -> StateR { - StateR::new((self.bits & 7) as u8) - } - #[doc = "Bit 4 - Between"] - #[inline(always)] - pub fn between(&self) -> BetweenR { - BetweenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Not Acknowledged"] - #[inline(always)] - pub fn nacked(&self) -> NackedR { - NackedR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bits 6:7 - In-Band Interrupt (IBI) Type"] - #[inline(always)] - pub fn ibitype(&self) -> IbitypeR { - IbitypeR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - Target Start Flag"] - #[inline(always)] - pub fn slvstart(&self) -> SlvstartR { - SlvstartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Controller Control Done Flag"] - #[inline(always)] - pub fn mctrldone(&self) -> MctrldoneR { - MctrldoneR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Complete Flag"] - #[inline(always)] - pub fn complete(&self) -> CompleteR { - CompleteR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - RXPEND"] - #[inline(always)] - pub fn rxpend(&self) -> RxpendR { - RxpendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - TX Buffer or FIFO Not Full"] - #[inline(always)] - pub fn txnotfull(&self) -> TxnotfullR { - TxnotfullR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - In-Band Interrupt (IBI) Won Flag"] - #[inline(always)] - pub fn ibiwon(&self) -> IbiwonR { - IbiwonR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Error or Warning"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 19 - Module is now Controller Flag"] - #[inline(always)] - pub fn nowmaster(&self) -> NowmasterR { - NowmasterR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 24:30 - IBI Address"] - #[inline(always)] - pub fn ibiaddr(&self) -> IbiaddrR { - IbiaddrR::new(((self.bits >> 24) & 0x7f) as u8) - } -} -impl W { - #[doc = "Bit 8 - Target Start Flag"] - #[inline(always)] - pub fn slvstart(&mut self) -> SlvstartW { - SlvstartW::new(self, 8) - } - #[doc = "Bit 9 - Controller Control Done Flag"] - #[inline(always)] - pub fn mctrldone(&mut self) -> MctrldoneW { - MctrldoneW::new(self, 9) - } - #[doc = "Bit 10 - Complete Flag"] - #[inline(always)] - pub fn complete(&mut self) -> CompleteW { - CompleteW::new(self, 10) - } - #[doc = "Bit 13 - In-Band Interrupt (IBI) Won Flag"] - #[inline(always)] - pub fn ibiwon(&mut self) -> IbiwonW { - IbiwonW::new(self, 13) - } - #[doc = "Bit 19 - Module is now Controller Flag"] - #[inline(always)] - pub fn nowmaster(&mut self) -> NowmasterW { - NowmasterW::new(self, 19) - } -} -#[doc = "Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MstatusSpec; -impl crate::RegisterSpec for MstatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mstatus::R`](R) reader structure"] -impl crate::Readable for MstatusSpec {} -#[doc = "`write(|w| ..)` method takes [`mstatus::W`](W) writer structure"] -impl crate::Writable for MstatusSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0008_2700; -} -#[doc = "`reset()` method sets MSTATUS to value 0x1000"] -impl crate::Resettable for MstatusSpec { - const RESET_VALUE: u32 = 0x1000; -} diff --git a/mcxa276-pac/src/i3c0/mwdatab.rs b/mcxa276-pac/src/i3c0/mwdatab.rs deleted file mode 100644 index ef418e75a..000000000 --- a/mcxa276-pac/src/i3c0/mwdatab.rs +++ /dev/null @@ -1,94 +0,0 @@ -#[doc = "Register `MWDATAB` writer"] -pub type W = crate::W; -#[doc = "Field `VALUE` writer - Data Byte"] -pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "End of Message\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum End { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: End) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END` writer - End of Message"] -pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; -impl<'a, REG> EndW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(End::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(End::End) - } -} -#[doc = "End of Message ALSO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EndAlso { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EndAlso) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END_ALSO` writer - End of Message ALSO"] -pub type EndAlsoW<'a, REG> = crate::BitWriter<'a, REG, EndAlso>; -impl<'a, REG> EndAlsoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(EndAlso::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(EndAlso::End) - } -} -impl W { - #[doc = "Bits 0:7 - Data Byte"] - #[inline(always)] - pub fn value(&mut self) -> ValueW { - ValueW::new(self, 0) - } - #[doc = "Bit 8 - End of Message"] - #[inline(always)] - pub fn end(&mut self) -> EndW { - EndW::new(self, 8) - } - #[doc = "Bit 16 - End of Message ALSO"] - #[inline(always)] - pub fn end_also(&mut self) -> EndAlsoW { - EndAlsoW::new(self, 16) - } -} -#[doc = "Controller Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatab::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MwdatabSpec; -impl crate::RegisterSpec for MwdatabSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mwdatab::W`](W) writer structure"] -impl crate::Writable for MwdatabSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWDATAB to value 0"] -impl crate::Resettable for MwdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/mwdatabe.rs b/mcxa276-pac/src/i3c0/mwdatabe.rs deleted file mode 100644 index 6ba1ff920..000000000 --- a/mcxa276-pac/src/i3c0/mwdatabe.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MWDATABE` writer"] -pub type W = crate::W; -#[doc = "Field `VALUE` writer - Data"] -pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Data"] - #[inline(always)] - pub fn value(&mut self) -> ValueW { - ValueW::new(self, 0) - } -} -#[doc = "Controller Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatabe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MwdatabeSpec; -impl crate::RegisterSpec for MwdatabeSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mwdatabe::W`](W) writer structure"] -impl crate::Writable for MwdatabeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWDATABE to value 0"] -impl crate::Resettable for MwdatabeSpec {} diff --git a/mcxa276-pac/src/i3c0/mwdatah.rs b/mcxa276-pac/src/i3c0/mwdatah.rs deleted file mode 100644 index a96e018c7..000000000 --- a/mcxa276-pac/src/i3c0/mwdatah.rs +++ /dev/null @@ -1,65 +0,0 @@ -#[doc = "Register `MWDATAH` writer"] -pub type W = crate::W; -#[doc = "Field `DATA0` writer - Data Byte 0"] -pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA1` writer - Data Byte 1"] -pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "End of Message\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum End { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: End) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END` writer - End of Message"] -pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; -impl<'a, REG> EndW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(End::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(End::End) - } -} -impl W { - #[doc = "Bits 0:7 - Data Byte 0"] - #[inline(always)] - pub fn data0(&mut self) -> Data0W { - Data0W::new(self, 0) - } - #[doc = "Bits 8:15 - Data Byte 1"] - #[inline(always)] - pub fn data1(&mut self) -> Data1W { - Data1W::new(self, 8) - } - #[doc = "Bit 16 - End of Message"] - #[inline(always)] - pub fn end(&mut self) -> EndW { - EndW::new(self, 16) - } -} -#[doc = "Controller Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatah::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MwdatahSpec; -impl crate::RegisterSpec for MwdatahSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mwdatah::W`](W) writer structure"] -impl crate::Writable for MwdatahSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWDATAH to value 0"] -impl crate::Resettable for MwdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/mwdatahe.rs b/mcxa276-pac/src/i3c0/mwdatahe.rs deleted file mode 100644 index e37e91b52..000000000 --- a/mcxa276-pac/src/i3c0/mwdatahe.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `MWDATAHE` writer"] -pub type W = crate::W; -#[doc = "Field `DATA0` writer - Data Byte 0"] -pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA1` writer - Data Byte 1"] -pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Data Byte 0"] - #[inline(always)] - pub fn data0(&mut self) -> Data0W { - Data0W::new(self, 0) - } - #[doc = "Bits 8:15 - Data Byte 1"] - #[inline(always)] - pub fn data1(&mut self) -> Data1W { - Data1W::new(self, 8) - } -} -#[doc = "Controller Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwdatahe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MwdataheSpec; -impl crate::RegisterSpec for MwdataheSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mwdatahe::W`](W) writer structure"] -impl crate::Writable for MwdataheSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MWDATAHE to value 0"] -impl crate::Resettable for MwdataheSpec {} diff --git a/mcxa276-pac/src/i3c0/scapabilities.rs b/mcxa276-pac/src/i3c0/scapabilities.rs deleted file mode 100644 index 18c174154..000000000 --- a/mcxa276-pac/src/i3c0/scapabilities.rs +++ /dev/null @@ -1,674 +0,0 @@ -#[doc = "Register `SCAPABILITIES` reader"] -pub type R = crate::R; -#[doc = "ID 48b Handler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Idena { - #[doc = "0: Application"] - Application = 0, - #[doc = "1: Hardware"] - Hw = 1, - #[doc = "2: Hardware, but the I3C module instance handles ID 48b"] - HwBut = 2, - #[doc = "3: A part number register (PARTNO)"] - Partno = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Idena) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Idena { - type Ux = u8; -} -impl crate::IsEnum for Idena {} -#[doc = "Field `IDENA` reader - ID 48b Handler"] -pub type IdenaR = crate::FieldReader; -impl IdenaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Idena { - match self.bits { - 0 => Idena::Application, - 1 => Idena::Hw, - 2 => Idena::HwBut, - 3 => Idena::Partno, - _ => unreachable!(), - } - } - #[doc = "Application"] - #[inline(always)] - pub fn is_application(&self) -> bool { - *self == Idena::Application - } - #[doc = "Hardware"] - #[inline(always)] - pub fn is_hw(&self) -> bool { - *self == Idena::Hw - } - #[doc = "Hardware, but the I3C module instance handles ID 48b"] - #[inline(always)] - pub fn is_hw_but(&self) -> bool { - *self == Idena::HwBut - } - #[doc = "A part number register (PARTNO)"] - #[inline(always)] - pub fn is_partno(&self) -> bool { - *self == Idena::Partno - } -} -#[doc = "ID Register\n\nValue on reset: 12"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Idreg { - #[doc = "0: All ID register features disabled"] - AllDisabled = 0, - #[doc = "1: ID Instance is a register; used if there is no PARTNO register"] - IdInstance = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Idreg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Idreg { - type Ux = u8; -} -impl crate::IsEnum for Idreg {} -#[doc = "Field `IDREG` reader - ID Register"] -pub type IdregR = crate::FieldReader; -impl IdregR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Idreg::AllDisabled), - 1 => Some(Idreg::IdInstance), - _ => None, - } - } - #[doc = "All ID register features disabled"] - #[inline(always)] - pub fn is_all_disabled(&self) -> bool { - *self == Idreg::AllDisabled - } - #[doc = "ID Instance is a register; used if there is no PARTNO register"] - #[inline(always)] - pub fn is_id_instance(&self) -> bool { - *self == Idreg::IdInstance - } -} -#[doc = "High Data Rate Support\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Hdrsupp { - #[doc = "0: No HDR modes supported"] - NoHdr = 0, - #[doc = "1: DDR mode supported"] - Ddr = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Hdrsupp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Hdrsupp { - type Ux = u8; -} -impl crate::IsEnum for Hdrsupp {} -#[doc = "Field `HDRSUPP` reader - High Data Rate Support"] -pub type HdrsuppR = crate::FieldReader; -impl HdrsuppR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Hdrsupp::NoHdr), - 1 => Some(Hdrsupp::Ddr), - _ => None, - } - } - #[doc = "No HDR modes supported"] - #[inline(always)] - pub fn is_no_hdr(&self) -> bool { - *self == Hdrsupp::NoHdr - } - #[doc = "DDR mode supported"] - #[inline(always)] - pub fn is_ddr(&self) -> bool { - *self == Hdrsupp::Ddr - } -} -#[doc = "Controller\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Master { - #[doc = "0: Not supported"] - Masternotsupported = 0, - #[doc = "1: Supported"] - Mastersupported = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Master) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MASTER` reader - Controller"] -pub type MasterR = crate::BitReader; -impl MasterR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Master { - match self.bits { - false => Master::Masternotsupported, - true => Master::Mastersupported, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_masternotsupported(&self) -> bool { - *self == Master::Masternotsupported - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_mastersupported(&self) -> bool { - *self == Master::Mastersupported - } -} -#[doc = "Static Address\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Saddr { - #[doc = "0: No static address"] - NoStatic = 0, - #[doc = "1: Static address is fixed in hardware"] - Static = 1, - #[doc = "2: Hardware controls the static address dynamically (for example, from the pin strap)"] - HwControl = 2, - #[doc = "3: SCONFIG register supplies the static address"] - Config = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Saddr) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Saddr { - type Ux = u8; -} -impl crate::IsEnum for Saddr {} -#[doc = "Field `SADDR` reader - Static Address"] -pub type SaddrR = crate::FieldReader; -impl SaddrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Saddr { - match self.bits { - 0 => Saddr::NoStatic, - 1 => Saddr::Static, - 2 => Saddr::HwControl, - 3 => Saddr::Config, - _ => unreachable!(), - } - } - #[doc = "No static address"] - #[inline(always)] - pub fn is_no_static(&self) -> bool { - *self == Saddr::NoStatic - } - #[doc = "Static address is fixed in hardware"] - #[inline(always)] - pub fn is_static(&self) -> bool { - *self == Saddr::Static - } - #[doc = "Hardware controls the static address dynamically (for example, from the pin strap)"] - #[inline(always)] - pub fn is_hw_control(&self) -> bool { - *self == Saddr::HwControl - } - #[doc = "SCONFIG register supplies the static address"] - #[inline(always)] - pub fn is_config(&self) -> bool { - *self == Saddr::Config - } -} -#[doc = "Common Command Codes Handling\n\nValue on reset: 15"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Ccchandle { - #[doc = "0: All handling features disabled"] - AllDisabled = 0, - #[doc = "1: The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items"] - BlockHandle = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Ccchandle) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Ccchandle { - type Ux = u8; -} -impl crate::IsEnum for Ccchandle {} -#[doc = "Field `CCCHANDLE` reader - Common Command Codes Handling"] -pub type CcchandleR = crate::FieldReader; -impl CcchandleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Ccchandle::AllDisabled), - 1 => Some(Ccchandle::BlockHandle), - _ => None, - } - } - #[doc = "All handling features disabled"] - #[inline(always)] - pub fn is_all_disabled(&self) -> bool { - *self == Ccchandle::AllDisabled - } - #[doc = "The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items"] - #[inline(always)] - pub fn is_block_handle(&self) -> bool { - *self == Ccchandle::BlockHandle - } -} -#[doc = "In-Band Interrupts, Controller Requests, Hot-Join Events\n\nValue on reset: 31"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum IbiMrHj { - #[doc = "0: Application cannot generate IBI, CR, or HJ"] - AllDisabled = 0, - #[doc = "1: Application can generate an IBI"] - Ibi = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: IbiMrHj) -> Self { - variant as _ - } -} -impl crate::FieldSpec for IbiMrHj { - type Ux = u8; -} -impl crate::IsEnum for IbiMrHj {} -#[doc = "Field `IBI_MR_HJ` reader - In-Band Interrupts, Controller Requests, Hot-Join Events"] -pub type IbiMrHjR = crate::FieldReader; -impl IbiMrHjR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(IbiMrHj::AllDisabled), - 1 => Some(IbiMrHj::Ibi), - _ => None, - } - } - #[doc = "Application cannot generate IBI, CR, or HJ"] - #[inline(always)] - pub fn is_all_disabled(&self) -> bool { - *self == IbiMrHj::AllDisabled - } - #[doc = "Application can generate an IBI"] - #[inline(always)] - pub fn is_ibi(&self) -> bool { - *self == IbiMrHj::Ibi - } -} -#[doc = "Time Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Timectrl { - #[doc = "0: No time control supported"] - NoTimeControlType = 0, - #[doc = "1: At least one time-control type supported"] - Atleast1TimeControl = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Timectrl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIMECTRL` reader - Time Control"] -pub type TimectrlR = crate::BitReader; -impl TimectrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timectrl { - match self.bits { - false => Timectrl::NoTimeControlType, - true => Timectrl::Atleast1TimeControl, - } - } - #[doc = "No time control supported"] - #[inline(always)] - pub fn is_no_time_control_type(&self) -> bool { - *self == Timectrl::NoTimeControlType - } - #[doc = "At least one time-control type supported"] - #[inline(always)] - pub fn is_atleast1_time_control(&self) -> bool { - *self == Timectrl::Atleast1TimeControl - } -} -#[doc = "External FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Extfifo { - #[doc = "0: No external FIFO available"] - NoExtFifo = 0, - #[doc = "1: Standard available or free external FIFO"] - StdExtFifo = 1, - #[doc = "2: Request track external FIFO"] - RequestExtFifo = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Extfifo) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Extfifo { - type Ux = u8; -} -impl crate::IsEnum for Extfifo {} -#[doc = "Field `EXTFIFO` reader - External FIFO"] -pub type ExtfifoR = crate::FieldReader; -impl ExtfifoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Extfifo::NoExtFifo), - 1 => Some(Extfifo::StdExtFifo), - 2 => Some(Extfifo::RequestExtFifo), - _ => None, - } - } - #[doc = "No external FIFO available"] - #[inline(always)] - pub fn is_no_ext_fifo(&self) -> bool { - *self == Extfifo::NoExtFifo - } - #[doc = "Standard available or free external FIFO"] - #[inline(always)] - pub fn is_std_ext_fifo(&self) -> bool { - *self == Extfifo::StdExtFifo - } - #[doc = "Request track external FIFO"] - #[inline(always)] - pub fn is_request_ext_fifo(&self) -> bool { - *self == Extfifo::RequestExtFifo - } -} -#[doc = "FIFO Transmit\n\nValue on reset: 2"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fifotx { - #[doc = "0: Two"] - Fifo2byte = 0, - #[doc = "1: Four"] - Fifo4byte = 1, - #[doc = "2: Eight"] - Fifo8byte = 2, - #[doc = "3: 16 or larger"] - Fifo16byte = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fifotx) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fifotx { - type Ux = u8; -} -impl crate::IsEnum for Fifotx {} -#[doc = "Field `FIFOTX` reader - FIFO Transmit"] -pub type FifotxR = crate::FieldReader; -impl FifotxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fifotx { - match self.bits { - 0 => Fifotx::Fifo2byte, - 1 => Fifotx::Fifo4byte, - 2 => Fifotx::Fifo8byte, - 3 => Fifotx::Fifo16byte, - _ => unreachable!(), - } - } - #[doc = "Two"] - #[inline(always)] - pub fn is_fifo_2byte(&self) -> bool { - *self == Fifotx::Fifo2byte - } - #[doc = "Four"] - #[inline(always)] - pub fn is_fifo_4byte(&self) -> bool { - *self == Fifotx::Fifo4byte - } - #[doc = "Eight"] - #[inline(always)] - pub fn is_fifo_8byte(&self) -> bool { - *self == Fifotx::Fifo8byte - } - #[doc = "16 or larger"] - #[inline(always)] - pub fn is_fifo_16byte(&self) -> bool { - *self == Fifotx::Fifo16byte - } -} -#[doc = "FIFO Receive\n\nValue on reset: 2"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fiforx { - #[doc = "0: Two or three"] - Fifo2byte = 0, - #[doc = "1: Four"] - Fifo4byte = 1, - #[doc = "2: Eight"] - Fifo8byte = 2, - #[doc = "3: 16 or larger"] - Fifo16byte = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fiforx) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fiforx { - type Ux = u8; -} -impl crate::IsEnum for Fiforx {} -#[doc = "Field `FIFORX` reader - FIFO Receive"] -pub type FiforxR = crate::FieldReader; -impl FiforxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fiforx { - match self.bits { - 0 => Fiforx::Fifo2byte, - 1 => Fiforx::Fifo4byte, - 2 => Fiforx::Fifo8byte, - 3 => Fiforx::Fifo16byte, - _ => unreachable!(), - } - } - #[doc = "Two or three"] - #[inline(always)] - pub fn is_fifo_2byte(&self) -> bool { - *self == Fiforx::Fifo2byte - } - #[doc = "Four"] - #[inline(always)] - pub fn is_fifo_4byte(&self) -> bool { - *self == Fiforx::Fifo4byte - } - #[doc = "Eight"] - #[inline(always)] - pub fn is_fifo_8byte(&self) -> bool { - *self == Fiforx::Fifo8byte - } - #[doc = "16 or larger"] - #[inline(always)] - pub fn is_fifo_16byte(&self) -> bool { - *self == Fiforx::Fifo16byte - } -} -#[doc = "Interrupts\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int { - #[doc = "0: Not supported"] - Interruptsno = 0, - #[doc = "1: Supported"] - Interruptsyes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT` reader - Interrupts"] -pub type IntR = crate::BitReader; -impl IntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int { - match self.bits { - false => Int::Interruptsno, - true => Int::Interruptsyes, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_interruptsno(&self) -> bool { - *self == Int::Interruptsno - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_interruptsyes(&self) -> bool { - *self == Int::Interruptsyes - } -} -#[doc = "Direct Memory Access\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dma { - #[doc = "0: Not supported"] - Dmano = 0, - #[doc = "1: Supported"] - Dmayes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dma) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMA` reader - Direct Memory Access"] -pub type DmaR = crate::BitReader; -impl DmaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dma { - match self.bits { - false => Dma::Dmano, - true => Dma::Dmayes, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_dmano(&self) -> bool { - *self == Dma::Dmano - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_dmayes(&self) -> bool { - *self == Dma::Dmayes - } -} -impl R { - #[doc = "Bits 0:1 - ID 48b Handler"] - #[inline(always)] - pub fn idena(&self) -> IdenaR { - IdenaR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:5 - ID Register"] - #[inline(always)] - pub fn idreg(&self) -> IdregR { - IdregR::new(((self.bits >> 2) & 0x0f) as u8) - } - #[doc = "Bits 6:7 - High Data Rate Support"] - #[inline(always)] - pub fn hdrsupp(&self) -> HdrsuppR { - HdrsuppR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 9 - Controller"] - #[inline(always)] - pub fn master(&self) -> MasterR { - MasterR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 10:11 - Static Address"] - #[inline(always)] - pub fn saddr(&self) -> SaddrR { - SaddrR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:15 - Common Command Codes Handling"] - #[inline(always)] - pub fn ccchandle(&self) -> CcchandleR { - CcchandleR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:20 - In-Band Interrupts, Controller Requests, Hot-Join Events"] - #[inline(always)] - pub fn ibi_mr_hj(&self) -> IbiMrHjR { - IbiMrHjR::new(((self.bits >> 16) & 0x1f) as u8) - } - #[doc = "Bit 21 - Time Control"] - #[inline(always)] - pub fn timectrl(&self) -> TimectrlR { - TimectrlR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bits 23:25 - External FIFO"] - #[inline(always)] - pub fn extfifo(&self) -> ExtfifoR { - ExtfifoR::new(((self.bits >> 23) & 7) as u8) - } - #[doc = "Bits 26:27 - FIFO Transmit"] - #[inline(always)] - pub fn fifotx(&self) -> FifotxR { - FifotxR::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:29 - FIFO Receive"] - #[inline(always)] - pub fn fiforx(&self) -> FiforxR { - FiforxR::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bit 30 - Interrupts"] - #[inline(always)] - pub fn int(&self) -> IntR { - IntR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Direct Memory Access"] - #[inline(always)] - pub fn dma(&self) -> DmaR { - DmaR::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "Target Capabilities\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ScapabilitiesSpec; -impl crate::RegisterSpec for ScapabilitiesSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scapabilities::R`](R) reader structure"] -impl crate::Readable for ScapabilitiesSpec {} -#[doc = "`reset()` method sets SCAPABILITIES to value 0xe83f_fe70"] -impl crate::Resettable for ScapabilitiesSpec { - const RESET_VALUE: u32 = 0xe83f_fe70; -} diff --git a/mcxa276-pac/src/i3c0/scapabilities2.rs b/mcxa276-pac/src/i3c0/scapabilities2.rs deleted file mode 100644 index a2339be0f..000000000 --- a/mcxa276-pac/src/i3c0/scapabilities2.rs +++ /dev/null @@ -1,413 +0,0 @@ -#[doc = "Register `SCAPABILITIES2` reader"] -pub type R = crate::R; -#[doc = "Field `MAPCNT` reader - Map Count"] -pub type MapcntR = crate::FieldReader; -#[doc = "I2C 10-bit Address\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum I2c10b { - #[doc = "0: Not supported"] - Disable = 0, - #[doc = "1: Supported"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: I2c10b) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `I2C10B` reader - I2C 10-bit Address"] -pub type I2c10bR = crate::BitReader; -impl I2c10bR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> I2c10b { - match self.bits { - false => I2c10b::Disable, - true => I2c10b::Enable, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == I2c10b::Disable - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == I2c10b::Enable - } -} -#[doc = "I2C Device ID\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum I2cdevid { - #[doc = "0: Not supported"] - Disable = 0, - #[doc = "1: Supported"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: I2cdevid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `I2CDEVID` reader - I2C Device ID"] -pub type I2cdevidR = crate::BitReader; -impl I2cdevidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> I2cdevid { - match self.bits { - false => I2cdevid::Disable, - true => I2cdevid::Enable, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == I2cdevid::Disable - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == I2cdevid::Enable - } -} -#[doc = "In-Band Interrupt EXTDATA\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibiext { - #[doc = "0: Not supported"] - Disable = 0, - #[doc = "1: Supported"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibiext) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBIEXT` reader - In-Band Interrupt EXTDATA"] -pub type IbiextR = crate::BitReader; -impl IbiextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibiext { - match self.bits { - false => Ibiext::Disable, - true => Ibiext::Enable, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ibiext::Disable - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ibiext::Enable - } -} -#[doc = "In-Band Interrupt Extended Register\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibixreg { - #[doc = "0: Not supported"] - Disable = 0, - #[doc = "1: Supported"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibixreg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBIXREG` reader - In-Band Interrupt Extended Register"] -pub type IbixregR = crate::BitReader; -impl IbixregR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibixreg { - match self.bits { - false => Ibixreg::Disable, - true => Ibixreg::Enable, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ibixreg::Disable - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ibixreg::Enable - } -} -#[doc = "Target Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slvrst { - #[doc = "0: Not supported"] - Disable = 0, - #[doc = "1: Supported"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slvrst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLVRST` reader - Target Reset"] -pub type SlvrstR = crate::BitReader; -impl SlvrstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slvrst { - match self.bits { - false => Slvrst::Disable, - true => Slvrst::Enable, - } - } - #[doc = "Not supported"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Slvrst::Disable - } - #[doc = "Supported"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Slvrst::Enable - } -} -#[doc = "Group\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Group { - #[doc = "0: v1.1 group addressing not supported"] - Notsupported = 0, - #[doc = "1: One group supported"] - One = 1, - #[doc = "2: Two groups supported"] - Two = 2, - #[doc = "3: Three groups supported"] - Three = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Group) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Group { - type Ux = u8; -} -impl crate::IsEnum for Group {} -#[doc = "Field `GROUP` reader - Group"] -pub type GroupR = crate::FieldReader; -impl GroupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Group { - match self.bits { - 0 => Group::Notsupported, - 1 => Group::One, - 2 => Group::Two, - 3 => Group::Three, - _ => unreachable!(), - } - } - #[doc = "v1.1 group addressing not supported"] - #[inline(always)] - pub fn is_notsupported(&self) -> bool { - *self == Group::Notsupported - } - #[doc = "One group supported"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Group::One - } - #[doc = "Two groups supported"] - #[inline(always)] - pub fn is_two(&self) -> bool { - *self == Group::Two - } - #[doc = "Three groups supported"] - #[inline(always)] - pub fn is_three(&self) -> bool { - *self == Group::Three - } -} -#[doc = "SETAASA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aasa { - #[doc = "0: SETAASA not supported"] - Notsupported = 0, - #[doc = "1: SETAASA supported"] - Supported = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aasa) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AASA` reader - SETAASA"] -pub type AasaR = crate::BitReader; -impl AasaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aasa { - match self.bits { - false => Aasa::Notsupported, - true => Aasa::Supported, - } - } - #[doc = "SETAASA not supported"] - #[inline(always)] - pub fn is_notsupported(&self) -> bool { - *self == Aasa::Notsupported - } - #[doc = "SETAASA supported"] - #[inline(always)] - pub fn is_supported(&self) -> bool { - *self == Aasa::Supported - } -} -#[doc = "Target-Target(s)-Tunnel Subscriber Capable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sstsub { - #[doc = "0: Not subscriber capable"] - Notsupported = 0, - #[doc = "1: Subscriber capable"] - Supported = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sstsub) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SSTSUB` reader - Target-Target(s)-Tunnel Subscriber Capable"] -pub type SstsubR = crate::BitReader; -impl SstsubR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sstsub { - match self.bits { - false => Sstsub::Notsupported, - true => Sstsub::Supported, - } - } - #[doc = "Not subscriber capable"] - #[inline(always)] - pub fn is_notsupported(&self) -> bool { - *self == Sstsub::Notsupported - } - #[doc = "Subscriber capable"] - #[inline(always)] - pub fn is_supported(&self) -> bool { - *self == Sstsub::Supported - } -} -#[doc = "Target-Target(s)-Tunnel Write Capable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sstwr { - #[doc = "0: Not write capable"] - Notsupported = 0, - #[doc = "1: Write capable"] - Supported = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sstwr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SSTWR` reader - Target-Target(s)-Tunnel Write Capable"] -pub type SstwrR = crate::BitReader; -impl SstwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sstwr { - match self.bits { - false => Sstwr::Notsupported, - true => Sstwr::Supported, - } - } - #[doc = "Not write capable"] - #[inline(always)] - pub fn is_notsupported(&self) -> bool { - *self == Sstwr::Notsupported - } - #[doc = "Write capable"] - #[inline(always)] - pub fn is_supported(&self) -> bool { - *self == Sstwr::Supported - } -} -impl R { - #[doc = "Bits 0:3 - Map Count"] - #[inline(always)] - pub fn mapcnt(&self) -> MapcntR { - MapcntR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 4 - I2C 10-bit Address"] - #[inline(always)] - pub fn i2c10b(&self) -> I2c10bR { - I2c10bR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 6 - I2C Device ID"] - #[inline(always)] - pub fn i2cdevid(&self) -> I2cdevidR { - I2cdevidR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - In-Band Interrupt EXTDATA"] - #[inline(always)] - pub fn ibiext(&self) -> IbiextR { - IbiextR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - In-Band Interrupt Extended Register"] - #[inline(always)] - pub fn ibixreg(&self) -> IbixregR { - IbixregR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 17 - Target Reset"] - #[inline(always)] - pub fn slvrst(&self) -> SlvrstR { - SlvrstR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bits 18:19 - Group"] - #[inline(always)] - pub fn group(&self) -> GroupR { - GroupR::new(((self.bits >> 18) & 3) as u8) - } - #[doc = "Bit 21 - SETAASA"] - #[inline(always)] - pub fn aasa(&self) -> AasaR { - AasaR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Target-Target(s)-Tunnel Subscriber Capable"] - #[inline(always)] - pub fn sstsub(&self) -> SstsubR { - SstsubR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Target-Target(s)-Tunnel Write Capable"] - #[inline(always)] - pub fn sstwr(&self) -> SstwrR { - SstwrR::new(((self.bits >> 23) & 1) != 0) - } -} -#[doc = "Target Capabilities 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scapabilities2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scapabilities2Spec; -impl crate::RegisterSpec for Scapabilities2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scapabilities2::R`](R) reader structure"] -impl crate::Readable for Scapabilities2Spec {} -#[doc = "`reset()` method sets SCAPABILITIES2 to value 0x0300"] -impl crate::Resettable for Scapabilities2Spec { - const RESET_VALUE: u32 = 0x0300; -} diff --git a/mcxa276-pac/src/i3c0/sconfig.rs b/mcxa276-pac/src/i3c0/sconfig.rs deleted file mode 100644 index d364ddc66..000000000 --- a/mcxa276-pac/src/i3c0/sconfig.rs +++ /dev/null @@ -1,429 +0,0 @@ -#[doc = "Register `SCONFIG` reader"] -pub type R = crate::R; -#[doc = "Register `SCONFIG` writer"] -pub type W = crate::W; -#[doc = "Target Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slvena { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slvena) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLVENA` reader - Target Enable"] -pub type SlvenaR = crate::BitReader; -impl SlvenaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slvena { - match self.bits { - false => Slvena::Disable, - true => Slvena::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Slvena::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Slvena::Enable - } -} -#[doc = "Field `SLVENA` writer - Target Enable"] -pub type SlvenaW<'a, REG> = crate::BitWriter<'a, REG, Slvena>; -impl<'a, REG> SlvenaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Slvena::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Slvena::Enable) - } -} -#[doc = "Not Acknowledge\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nack { - #[doc = "0: Always disable NACK mode"] - Disable = 0, - #[doc = "1: Always enable NACK mode (works normally)"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NACK` reader - Not Acknowledge"] -pub type NackR = crate::BitReader; -impl NackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nack { - match self.bits { - false => Nack::Disable, - true => Nack::Enable, - } - } - #[doc = "Always disable NACK mode"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Nack::Disable - } - #[doc = "Always enable NACK mode (works normally)"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Nack::Enable - } -} -#[doc = "Field `NACK` writer - Not Acknowledge"] -pub type NackW<'a, REG> = crate::BitWriter<'a, REG, Nack>; -impl<'a, REG> NackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Always disable NACK mode"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Nack::Disable) - } - #[doc = "Always enable NACK mode (works normally)"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Nack::Enable) - } -} -#[doc = "Match Start or Stop\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Matchss { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Matchss) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MATCHSS` reader - Match Start or Stop"] -pub type MatchssR = crate::BitReader; -impl MatchssR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Matchss { - match self.bits { - false => Matchss::Disable, - true => Matchss::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Matchss::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Matchss::Enable - } -} -#[doc = "Field `MATCHSS` writer - Match Start or Stop"] -pub type MatchssW<'a, REG> = crate::BitWriter<'a, REG, Matchss>; -impl<'a, REG> MatchssW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Matchss::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Matchss::Enable) - } -} -#[doc = "Ignore TE0 or TE1 Errors\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum S0ignore { - #[doc = "0: Do not ignore TE0 or TE1 errors"] - Disable = 0, - #[doc = "1: Ignore TE0 or TE1 errors"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: S0ignore) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `S0IGNORE` reader - Ignore TE0 or TE1 Errors"] -pub type S0ignoreR = crate::BitReader; -impl S0ignoreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> S0ignore { - match self.bits { - false => S0ignore::Disable, - true => S0ignore::Enable, - } - } - #[doc = "Do not ignore TE0 or TE1 errors"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == S0ignore::Disable - } - #[doc = "Ignore TE0 or TE1 errors"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == S0ignore::Enable - } -} -#[doc = "Field `S0IGNORE` writer - Ignore TE0 or TE1 Errors"] -pub type S0ignoreW<'a, REG> = crate::BitWriter<'a, REG, S0ignore>; -impl<'a, REG> S0ignoreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Do not ignore TE0 or TE1 errors"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(S0ignore::Disable) - } - #[doc = "Ignore TE0 or TE1 errors"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(S0ignore::Enable) - } -} -#[doc = "HDR OK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hdrok { - #[doc = "0: Disable HDR OK"] - Disable = 0, - #[doc = "1: Enable HDR OK"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hdrok) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HDROK` reader - HDR OK"] -pub type HdrokR = crate::BitReader; -impl HdrokR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hdrok { - match self.bits { - false => Hdrok::Disable, - true => Hdrok::Enable, - } - } - #[doc = "Disable HDR OK"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Hdrok::Disable - } - #[doc = "Enable HDR OK"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Hdrok::Enable - } -} -#[doc = "Field `HDROK` writer - HDR OK"] -pub type HdrokW<'a, REG> = crate::BitWriter<'a, REG, Hdrok>; -impl<'a, REG> HdrokW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable HDR OK"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Hdrok::Disable) - } - #[doc = "Enable HDR OK"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Hdrok::Enable) - } -} -#[doc = "Offline\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Offline { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Offline) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OFFLINE` reader - Offline"] -pub type OfflineR = crate::BitReader; -impl OfflineR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Offline { - match self.bits { - false => Offline::Disable, - true => Offline::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Offline::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Offline::Enable - } -} -#[doc = "Field `OFFLINE` writer - Offline"] -pub type OfflineW<'a, REG> = crate::BitWriter<'a, REG, Offline>; -impl<'a, REG> OfflineW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Offline::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Offline::Enable) - } -} -#[doc = "Field `BAMATCH` reader - Bus Available Match"] -pub type BamatchR = crate::FieldReader; -#[doc = "Field `BAMATCH` writer - Bus Available Match"] -pub type BamatchW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `SADDR` reader - Static Address"] -pub type SaddrR = crate::FieldReader; -#[doc = "Field `SADDR` writer - Static Address"] -pub type SaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bit 0 - Target Enable"] - #[inline(always)] - pub fn slvena(&self) -> SlvenaR { - SlvenaR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Not Acknowledge"] - #[inline(always)] - pub fn nack(&self) -> NackR { - NackR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Match Start or Stop"] - #[inline(always)] - pub fn matchss(&self) -> MatchssR { - MatchssR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Ignore TE0 or TE1 Errors"] - #[inline(always)] - pub fn s0ignore(&self) -> S0ignoreR { - S0ignoreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - HDR OK"] - #[inline(always)] - pub fn hdrok(&self) -> HdrokR { - HdrokR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 9 - Offline"] - #[inline(always)] - pub fn offline(&self) -> OfflineR { - OfflineR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 16:21 - Bus Available Match"] - #[inline(always)] - pub fn bamatch(&self) -> BamatchR { - BamatchR::new(((self.bits >> 16) & 0x3f) as u8) - } - #[doc = "Bits 25:31 - Static Address"] - #[inline(always)] - pub fn saddr(&self) -> SaddrR { - SaddrR::new(((self.bits >> 25) & 0x7f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Target Enable"] - #[inline(always)] - pub fn slvena(&mut self) -> SlvenaW { - SlvenaW::new(self, 0) - } - #[doc = "Bit 1 - Not Acknowledge"] - #[inline(always)] - pub fn nack(&mut self) -> NackW { - NackW::new(self, 1) - } - #[doc = "Bit 2 - Match Start or Stop"] - #[inline(always)] - pub fn matchss(&mut self) -> MatchssW { - MatchssW::new(self, 2) - } - #[doc = "Bit 3 - Ignore TE0 or TE1 Errors"] - #[inline(always)] - pub fn s0ignore(&mut self) -> S0ignoreW { - S0ignoreW::new(self, 3) - } - #[doc = "Bit 4 - HDR OK"] - #[inline(always)] - pub fn hdrok(&mut self) -> HdrokW { - HdrokW::new(self, 4) - } - #[doc = "Bit 9 - Offline"] - #[inline(always)] - pub fn offline(&mut self) -> OfflineW { - OfflineW::new(self, 9) - } - #[doc = "Bits 16:21 - Bus Available Match"] - #[inline(always)] - pub fn bamatch(&mut self) -> BamatchW { - BamatchW::new(self, 16) - } - #[doc = "Bits 25:31 - Static Address"] - #[inline(always)] - pub fn saddr(&mut self) -> SaddrW { - SaddrW::new(self, 25) - } -} -#[doc = "Target Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`sconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SconfigSpec; -impl crate::RegisterSpec for SconfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sconfig::R`](R) reader structure"] -impl crate::Readable for SconfigSpec {} -#[doc = "`write(|w| ..)` method takes [`sconfig::W`](W) writer structure"] -impl crate::Writable for SconfigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCONFIG to value 0x0017_0000"] -impl crate::Resettable for SconfigSpec { - const RESET_VALUE: u32 = 0x0017_0000; -} diff --git a/mcxa276-pac/src/i3c0/sctrl.rs b/mcxa276-pac/src/i3c0/sctrl.rs deleted file mode 100644 index 565ed5a51..000000000 --- a/mcxa276-pac/src/i3c0/sctrl.rs +++ /dev/null @@ -1,236 +0,0 @@ -#[doc = "Register `SCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SCTRL` writer"] -pub type W = crate::W; -#[doc = "Event\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Event { - #[doc = "0: NORMAL_MODE"] - NormalMode = 0, - #[doc = "1: IBI"] - Ibi = 1, - #[doc = "2: CONTROLLER_REQUEST"] - MasterRequest = 2, - #[doc = "3: HOT_JOIN_REQUEST"] - HotJoinRequest = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Event) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Event { - type Ux = u8; -} -impl crate::IsEnum for Event {} -#[doc = "Field `EVENT` reader - Event"] -pub type EventR = crate::FieldReader; -impl EventR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Event { - match self.bits { - 0 => Event::NormalMode, - 1 => Event::Ibi, - 2 => Event::MasterRequest, - 3 => Event::HotJoinRequest, - _ => unreachable!(), - } - } - #[doc = "NORMAL_MODE"] - #[inline(always)] - pub fn is_normal_mode(&self) -> bool { - *self == Event::NormalMode - } - #[doc = "IBI"] - #[inline(always)] - pub fn is_ibi(&self) -> bool { - *self == Event::Ibi - } - #[doc = "CONTROLLER_REQUEST"] - #[inline(always)] - pub fn is_master_request(&self) -> bool { - *self == Event::MasterRequest - } - #[doc = "HOT_JOIN_REQUEST"] - #[inline(always)] - pub fn is_hot_join_request(&self) -> bool { - *self == Event::HotJoinRequest - } -} -#[doc = "Field `EVENT` writer - Event"] -pub type EventW<'a, REG> = crate::FieldWriter<'a, REG, 2, Event, crate::Safe>; -impl<'a, REG> EventW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "NORMAL_MODE"] - #[inline(always)] - pub fn normal_mode(self) -> &'a mut crate::W { - self.variant(Event::NormalMode) - } - #[doc = "IBI"] - #[inline(always)] - pub fn ibi(self) -> &'a mut crate::W { - self.variant(Event::Ibi) - } - #[doc = "CONTROLLER_REQUEST"] - #[inline(always)] - pub fn master_request(self) -> &'a mut crate::W { - self.variant(Event::MasterRequest) - } - #[doc = "HOT_JOIN_REQUEST"] - #[inline(always)] - pub fn hot_join_request(self) -> &'a mut crate::W { - self.variant(Event::HotJoinRequest) - } -} -#[doc = "Extended Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Extdata { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Extdata) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EXTDATA` reader - Extended Data"] -pub type ExtdataR = crate::BitReader; -impl ExtdataR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Extdata { - match self.bits { - false => Extdata::Disable, - true => Extdata::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Extdata::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Extdata::Enable - } -} -#[doc = "Field `EXTDATA` writer - Extended Data"] -pub type ExtdataW<'a, REG> = crate::BitWriter<'a, REG, Extdata>; -impl<'a, REG> ExtdataW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Extdata::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Extdata::Enable) - } -} -#[doc = "Field `IBIDATA` reader - In-Band Interrupt Data"] -pub type IbidataR = crate::FieldReader; -#[doc = "Field `IBIDATA` writer - In-Band Interrupt Data"] -pub type IbidataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `PENDINT` reader - Pending Interrupt"] -pub type PendintR = crate::FieldReader; -#[doc = "Field `PENDINT` writer - Pending Interrupt"] -pub type PendintW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ACTSTATE` reader - Activity State of Target"] -pub type ActstateR = crate::FieldReader; -#[doc = "Field `ACTSTATE` writer - Activity State of Target"] -pub type ActstateW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `VENDINFO` reader - Vendor Information"] -pub type VendinfoR = crate::FieldReader; -#[doc = "Field `VENDINFO` writer - Vendor Information"] -pub type VendinfoW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:1 - Event"] - #[inline(always)] - pub fn event(&self) -> EventR { - EventR::new((self.bits & 3) as u8) - } - #[doc = "Bit 3 - Extended Data"] - #[inline(always)] - pub fn extdata(&self) -> ExtdataR { - ExtdataR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 8:15 - In-Band Interrupt Data"] - #[inline(always)] - pub fn ibidata(&self) -> IbidataR { - IbidataR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:19 - Pending Interrupt"] - #[inline(always)] - pub fn pendint(&self) -> PendintR { - PendintR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 20:21 - Activity State of Target"] - #[inline(always)] - pub fn actstate(&self) -> ActstateR { - ActstateR::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bits 24:31 - Vendor Information"] - #[inline(always)] - pub fn vendinfo(&self) -> VendinfoR { - VendinfoR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Event"] - #[inline(always)] - pub fn event(&mut self) -> EventW { - EventW::new(self, 0) - } - #[doc = "Bit 3 - Extended Data"] - #[inline(always)] - pub fn extdata(&mut self) -> ExtdataW { - ExtdataW::new(self, 3) - } - #[doc = "Bits 8:15 - In-Band Interrupt Data"] - #[inline(always)] - pub fn ibidata(&mut self) -> IbidataW { - IbidataW::new(self, 8) - } - #[doc = "Bits 16:19 - Pending Interrupt"] - #[inline(always)] - pub fn pendint(&mut self) -> PendintW { - PendintW::new(self, 16) - } - #[doc = "Bits 20:21 - Activity State of Target"] - #[inline(always)] - pub fn actstate(&mut self) -> ActstateW { - ActstateW::new(self, 20) - } - #[doc = "Bits 24:31 - Vendor Information"] - #[inline(always)] - pub fn vendinfo(&mut self) -> VendinfoW { - VendinfoW::new(self, 24) - } -} -#[doc = "Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SctrlSpec; -impl crate::RegisterSpec for SctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sctrl::R`](R) reader structure"] -impl crate::Readable for SctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sctrl::W`](W) writer structure"] -impl crate::Writable for SctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCTRL to value 0"] -impl crate::Resettable for SctrlSpec {} diff --git a/mcxa276-pac/src/i3c0/sdatactrl.rs b/mcxa276-pac/src/i3c0/sdatactrl.rs deleted file mode 100644 index 4e9e5ba1d..000000000 --- a/mcxa276-pac/src/i3c0/sdatactrl.rs +++ /dev/null @@ -1,419 +0,0 @@ -#[doc = "Register `SDATACTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SDATACTRL` writer"] -pub type W = crate::W; -#[doc = "Flush To-Bus Buffer or FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flushtb { - #[doc = "0: No action"] - NoAction = 0, - #[doc = "1: Flush the buffer"] - Flush = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flushtb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLUSHTB` writer - Flush To-Bus Buffer or FIFO"] -pub type FlushtbW<'a, REG> = crate::BitWriter<'a, REG, Flushtb>; -impl<'a, REG> FlushtbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No action"] - #[inline(always)] - pub fn no_action(self) -> &'a mut crate::W { - self.variant(Flushtb::NoAction) - } - #[doc = "Flush the buffer"] - #[inline(always)] - pub fn flush(self) -> &'a mut crate::W { - self.variant(Flushtb::Flush) - } -} -#[doc = "Flush From-Bus Buffer or FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flushfb { - #[doc = "0: No action"] - NoAction = 0, - #[doc = "1: Flush the buffer"] - Flush = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flushfb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLUSHFB` writer - Flush From-Bus Buffer or FIFO"] -pub type FlushfbW<'a, REG> = crate::BitWriter<'a, REG, Flushfb>; -impl<'a, REG> FlushfbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No action"] - #[inline(always)] - pub fn no_action(self) -> &'a mut crate::W { - self.variant(Flushfb::NoAction) - } - #[doc = "Flush the buffer"] - #[inline(always)] - pub fn flush(self) -> &'a mut crate::W { - self.variant(Flushfb::Flush) - } -} -#[doc = "Unlock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unlock { - #[doc = "0: Cannot be changed"] - Disabled = 0, - #[doc = "1: Can be changed"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unlock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNLOCK` writer - Unlock"] -pub type UnlockW<'a, REG> = crate::BitWriter<'a, REG, Unlock>; -impl<'a, REG> UnlockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Cannot be changed"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Unlock::Disabled) - } - #[doc = "Can be changed"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Unlock::Enabled) - } -} -#[doc = "Transmit Trigger Level\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Txtrig { - #[doc = "0: Trigger when empty"] - Triggrempty = 0, - #[doc = "1: Trigger when 1/4 full or less"] - Triggronefourth = 1, - #[doc = "2: Trigger when 1/2 full or less"] - Triggronehalf = 2, - #[doc = "3: Default (trigger when 1 less than full or less)"] - Triggroneless = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Txtrig) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Txtrig { - type Ux = u8; -} -impl crate::IsEnum for Txtrig {} -#[doc = "Field `TXTRIG` reader - Transmit Trigger Level"] -pub type TxtrigR = crate::FieldReader; -impl TxtrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txtrig { - match self.bits { - 0 => Txtrig::Triggrempty, - 1 => Txtrig::Triggronefourth, - 2 => Txtrig::Triggronehalf, - 3 => Txtrig::Triggroneless, - _ => unreachable!(), - } - } - #[doc = "Trigger when empty"] - #[inline(always)] - pub fn is_triggrempty(&self) -> bool { - *self == Txtrig::Triggrempty - } - #[doc = "Trigger when 1/4 full or less"] - #[inline(always)] - pub fn is_triggronefourth(&self) -> bool { - *self == Txtrig::Triggronefourth - } - #[doc = "Trigger when 1/2 full or less"] - #[inline(always)] - pub fn is_triggronehalf(&self) -> bool { - *self == Txtrig::Triggronehalf - } - #[doc = "Default (trigger when 1 less than full or less)"] - #[inline(always)] - pub fn is_triggroneless(&self) -> bool { - *self == Txtrig::Triggroneless - } -} -#[doc = "Field `TXTRIG` writer - Transmit Trigger Level"] -pub type TxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txtrig, crate::Safe>; -impl<'a, REG> TxtrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Trigger when empty"] - #[inline(always)] - pub fn triggrempty(self) -> &'a mut crate::W { - self.variant(Txtrig::Triggrempty) - } - #[doc = "Trigger when 1/4 full or less"] - #[inline(always)] - pub fn triggronefourth(self) -> &'a mut crate::W { - self.variant(Txtrig::Triggronefourth) - } - #[doc = "Trigger when 1/2 full or less"] - #[inline(always)] - pub fn triggronehalf(self) -> &'a mut crate::W { - self.variant(Txtrig::Triggronehalf) - } - #[doc = "Default (trigger when 1 less than full or less)"] - #[inline(always)] - pub fn triggroneless(self) -> &'a mut crate::W { - self.variant(Txtrig::Triggroneless) - } -} -#[doc = "Receive Trigger Level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Rxtrig { - #[doc = "0: Trigger when not empty (default)"] - Triggrnotempty = 0, - #[doc = "1: Trigger when 1/4 or more full"] - Triggronefourth = 1, - #[doc = "2: Trigger when 1/2 or more full"] - Triggronehalf = 2, - #[doc = "3: Trigger when 3/4 or more full"] - Triggrthreefourths = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Rxtrig) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Rxtrig { - type Ux = u8; -} -impl crate::IsEnum for Rxtrig {} -#[doc = "Field `RXTRIG` reader - Receive Trigger Level"] -pub type RxtrigR = crate::FieldReader; -impl RxtrigR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxtrig { - match self.bits { - 0 => Rxtrig::Triggrnotempty, - 1 => Rxtrig::Triggronefourth, - 2 => Rxtrig::Triggronehalf, - 3 => Rxtrig::Triggrthreefourths, - _ => unreachable!(), - } - } - #[doc = "Trigger when not empty (default)"] - #[inline(always)] - pub fn is_triggrnotempty(&self) -> bool { - *self == Rxtrig::Triggrnotempty - } - #[doc = "Trigger when 1/4 or more full"] - #[inline(always)] - pub fn is_triggronefourth(&self) -> bool { - *self == Rxtrig::Triggronefourth - } - #[doc = "Trigger when 1/2 or more full"] - #[inline(always)] - pub fn is_triggronehalf(&self) -> bool { - *self == Rxtrig::Triggronehalf - } - #[doc = "Trigger when 3/4 or more full"] - #[inline(always)] - pub fn is_triggrthreefourths(&self) -> bool { - *self == Rxtrig::Triggrthreefourths - } -} -#[doc = "Field `RXTRIG` writer - Receive Trigger Level"] -pub type RxtrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxtrig, crate::Safe>; -impl<'a, REG> RxtrigW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Trigger when not empty (default)"] - #[inline(always)] - pub fn triggrnotempty(self) -> &'a mut crate::W { - self.variant(Rxtrig::Triggrnotempty) - } - #[doc = "Trigger when 1/4 or more full"] - #[inline(always)] - pub fn triggronefourth(self) -> &'a mut crate::W { - self.variant(Rxtrig::Triggronefourth) - } - #[doc = "Trigger when 1/2 or more full"] - #[inline(always)] - pub fn triggronehalf(self) -> &'a mut crate::W { - self.variant(Rxtrig::Triggronehalf) - } - #[doc = "Trigger when 3/4 or more full"] - #[inline(always)] - pub fn triggrthreefourths(self) -> &'a mut crate::W { - self.variant(Rxtrig::Triggrthreefourths) - } -} -#[doc = "Field `TXCOUNT` reader - Count of Entries in Transmit"] -pub type TxcountR = crate::FieldReader; -#[doc = "Field `RXCOUNT` reader - Count of Entries in Receive"] -pub type RxcountR = crate::FieldReader; -#[doc = "Transmit is Full\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txfull { - #[doc = "0: Not full"] - Txisnotfull = 0, - #[doc = "1: Full"] - Txisfull = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txfull) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXFULL` reader - Transmit is Full"] -pub type TxfullR = crate::BitReader; -impl TxfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txfull { - match self.bits { - false => Txfull::Txisnotfull, - true => Txfull::Txisfull, - } - } - #[doc = "Not full"] - #[inline(always)] - pub fn is_txisnotfull(&self) -> bool { - *self == Txfull::Txisnotfull - } - #[doc = "Full"] - #[inline(always)] - pub fn is_txisfull(&self) -> bool { - *self == Txfull::Txisfull - } -} -#[doc = "Receive is Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempty { - #[doc = "0: Not empty"] - Rxisnotempty = 0, - #[doc = "1: Empty"] - Rxisempty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPTY` reader - Receive is Empty"] -pub type RxemptyR = crate::BitReader; -impl RxemptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempty { - match self.bits { - false => Rxempty::Rxisnotempty, - true => Rxempty::Rxisempty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_rxisnotempty(&self) -> bool { - *self == Rxempty::Rxisnotempty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_rxisempty(&self) -> bool { - *self == Rxempty::Rxisempty - } -} -impl R { - #[doc = "Bits 4:5 - Transmit Trigger Level"] - #[inline(always)] - pub fn txtrig(&self) -> TxtrigR { - TxtrigR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Receive Trigger Level"] - #[inline(always)] - pub fn rxtrig(&self) -> RxtrigR { - RxtrigR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 16:20 - Count of Entries in Transmit"] - #[inline(always)] - pub fn txcount(&self) -> TxcountR { - TxcountR::new(((self.bits >> 16) & 0x1f) as u8) - } - #[doc = "Bits 24:28 - Count of Entries in Receive"] - #[inline(always)] - pub fn rxcount(&self) -> RxcountR { - RxcountR::new(((self.bits >> 24) & 0x1f) as u8) - } - #[doc = "Bit 30 - Transmit is Full"] - #[inline(always)] - pub fn txfull(&self) -> TxfullR { - TxfullR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Receive is Empty"] - #[inline(always)] - pub fn rxempty(&self) -> RxemptyR { - RxemptyR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Flush To-Bus Buffer or FIFO"] - #[inline(always)] - pub fn flushtb(&mut self) -> FlushtbW { - FlushtbW::new(self, 0) - } - #[doc = "Bit 1 - Flush From-Bus Buffer or FIFO"] - #[inline(always)] - pub fn flushfb(&mut self) -> FlushfbW { - FlushfbW::new(self, 1) - } - #[doc = "Bit 3 - Unlock"] - #[inline(always)] - pub fn unlock(&mut self) -> UnlockW { - UnlockW::new(self, 3) - } - #[doc = "Bits 4:5 - Transmit Trigger Level"] - #[inline(always)] - pub fn txtrig(&mut self) -> TxtrigW { - TxtrigW::new(self, 4) - } - #[doc = "Bits 6:7 - Receive Trigger Level"] - #[inline(always)] - pub fn rxtrig(&mut self) -> RxtrigW { - RxtrigW::new(self, 6) - } -} -#[doc = "Target Data Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdatactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdatactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SdatactrlSpec; -impl crate::RegisterSpec for SdatactrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sdatactrl::R`](R) reader structure"] -impl crate::Readable for SdatactrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sdatactrl::W`](W) writer structure"] -impl crate::Writable for SdatactrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SDATACTRL to value 0x8000_0030"] -impl crate::Resettable for SdatactrlSpec { - const RESET_VALUE: u32 = 0x8000_0030; -} diff --git a/mcxa276-pac/src/i3c0/sdmactrl.rs b/mcxa276-pac/src/i3c0/sdmactrl.rs deleted file mode 100644 index 251a989bc..000000000 --- a/mcxa276-pac/src/i3c0/sdmactrl.rs +++ /dev/null @@ -1,272 +0,0 @@ -#[doc = "Register `SDMACTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SDMACTRL` writer"] -pub type W = crate::W; -#[doc = "DMA Read (From-Bus) Trigger\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dmafb { - #[doc = "0: DMA not used"] - NotUsed = 0, - #[doc = "1: DMA enabled for one frame"] - EnableOneFrame = 1, - #[doc = "2: DMA enabled until turned off"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dmafb) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dmafb { - type Ux = u8; -} -impl crate::IsEnum for Dmafb {} -#[doc = "Field `DMAFB` reader - DMA Read (From-Bus) Trigger"] -pub type DmafbR = crate::FieldReader; -impl DmafbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dmafb::NotUsed), - 1 => Some(Dmafb::EnableOneFrame), - 2 => Some(Dmafb::Enable), - _ => None, - } - } - #[doc = "DMA not used"] - #[inline(always)] - pub fn is_not_used(&self) -> bool { - *self == Dmafb::NotUsed - } - #[doc = "DMA enabled for one frame"] - #[inline(always)] - pub fn is_enable_one_frame(&self) -> bool { - *self == Dmafb::EnableOneFrame - } - #[doc = "DMA enabled until turned off"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dmafb::Enable - } -} -#[doc = "Field `DMAFB` writer - DMA Read (From-Bus) Trigger"] -pub type DmafbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmafb>; -impl<'a, REG> DmafbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "DMA not used"] - #[inline(always)] - pub fn not_used(self) -> &'a mut crate::W { - self.variant(Dmafb::NotUsed) - } - #[doc = "DMA enabled for one frame"] - #[inline(always)] - pub fn enable_one_frame(self) -> &'a mut crate::W { - self.variant(Dmafb::EnableOneFrame) - } - #[doc = "DMA enabled until turned off"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dmafb::Enable) - } -} -#[doc = "DMA Write (To-Bus) Trigger\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dmatb { - #[doc = "0: DMA not used"] - NotUsed = 0, - #[doc = "1: DMA enabled for one frame"] - EnableOneFrame = 1, - #[doc = "2: DMA enabled until turned off"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dmatb) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dmatb { - type Ux = u8; -} -impl crate::IsEnum for Dmatb {} -#[doc = "Field `DMATB` reader - DMA Write (To-Bus) Trigger"] -pub type DmatbR = crate::FieldReader; -impl DmatbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dmatb::NotUsed), - 1 => Some(Dmatb::EnableOneFrame), - 2 => Some(Dmatb::Enable), - _ => None, - } - } - #[doc = "DMA not used"] - #[inline(always)] - pub fn is_not_used(&self) -> bool { - *self == Dmatb::NotUsed - } - #[doc = "DMA enabled for one frame"] - #[inline(always)] - pub fn is_enable_one_frame(&self) -> bool { - *self == Dmatb::EnableOneFrame - } - #[doc = "DMA enabled until turned off"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dmatb::Enable - } -} -#[doc = "Field `DMATB` writer - DMA Write (To-Bus) Trigger"] -pub type DmatbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmatb>; -impl<'a, REG> DmatbW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "DMA not used"] - #[inline(always)] - pub fn not_used(self) -> &'a mut crate::W { - self.variant(Dmatb::NotUsed) - } - #[doc = "DMA enabled for one frame"] - #[inline(always)] - pub fn enable_one_frame(self) -> &'a mut crate::W { - self.variant(Dmatb::EnableOneFrame) - } - #[doc = "DMA enabled until turned off"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dmatb::Enable) - } -} -#[doc = "Width of DMA Operations\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dmawidth { - #[doc = "0: Byte"] - Byte0 = 0, - #[doc = "1: Byte"] - Byte1 = 1, - #[doc = "2: Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)"] - HalfWord = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dmawidth) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dmawidth { - type Ux = u8; -} -impl crate::IsEnum for Dmawidth {} -#[doc = "Field `DMAWIDTH` reader - Width of DMA Operations"] -pub type DmawidthR = crate::FieldReader; -impl DmawidthR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dmawidth::Byte0), - 1 => Some(Dmawidth::Byte1), - 2 => Some(Dmawidth::HalfWord), - _ => None, - } - } - #[doc = "Byte"] - #[inline(always)] - pub fn is_byte_0(&self) -> bool { - *self == Dmawidth::Byte0 - } - #[doc = "Byte"] - #[inline(always)] - pub fn is_byte_1(&self) -> bool { - *self == Dmawidth::Byte1 - } - #[doc = "Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)"] - #[inline(always)] - pub fn is_half_word(&self) -> bool { - *self == Dmawidth::HalfWord - } -} -#[doc = "Field `DMAWIDTH` writer - Width of DMA Operations"] -pub type DmawidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmawidth>; -impl<'a, REG> DmawidthW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Byte"] - #[inline(always)] - pub fn byte_0(self) -> &'a mut crate::W { - self.variant(Dmawidth::Byte0) - } - #[doc = "Byte"] - #[inline(always)] - pub fn byte_1(self) -> &'a mut crate::W { - self.variant(Dmawidth::Byte1) - } - #[doc = "Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)"] - #[inline(always)] - pub fn half_word(self) -> &'a mut crate::W { - self.variant(Dmawidth::HalfWord) - } -} -impl R { - #[doc = "Bits 0:1 - DMA Read (From-Bus) Trigger"] - #[inline(always)] - pub fn dmafb(&self) -> DmafbR { - DmafbR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - DMA Write (To-Bus) Trigger"] - #[inline(always)] - pub fn dmatb(&self) -> DmatbR { - DmatbR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Width of DMA Operations"] - #[inline(always)] - pub fn dmawidth(&self) -> DmawidthR { - DmawidthR::new(((self.bits >> 4) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - DMA Read (From-Bus) Trigger"] - #[inline(always)] - pub fn dmafb(&mut self) -> DmafbW { - DmafbW::new(self, 0) - } - #[doc = "Bits 2:3 - DMA Write (To-Bus) Trigger"] - #[inline(always)] - pub fn dmatb(&mut self) -> DmatbW { - DmatbW::new(self, 2) - } - #[doc = "Bits 4:5 - Width of DMA Operations"] - #[inline(always)] - pub fn dmawidth(&mut self) -> DmawidthW { - DmawidthW::new(self, 4) - } -} -#[doc = "Target DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sdmactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdmactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SdmactrlSpec; -impl crate::RegisterSpec for SdmactrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sdmactrl::R`](R) reader structure"] -impl crate::Readable for SdmactrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sdmactrl::W`](W) writer structure"] -impl crate::Writable for SdmactrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SDMACTRL to value 0x10"] -impl crate::Resettable for SdmactrlSpec { - const RESET_VALUE: u32 = 0x10; -} diff --git a/mcxa276-pac/src/i3c0/sdynaddr.rs b/mcxa276-pac/src/i3c0/sdynaddr.rs deleted file mode 100644 index 2c82a449b..000000000 --- a/mcxa276-pac/src/i3c0/sdynaddr.rs +++ /dev/null @@ -1,126 +0,0 @@ -#[doc = "Register `SDYNADDR` reader"] -pub type R = crate::R; -#[doc = "Register `SDYNADDR` writer"] -pub type W = crate::W; -#[doc = "Dynamic Address Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Davalid { - #[doc = "0: DANOTASSIGNED: a dynamic address is not assigned"] - Danotassigned = 0, - #[doc = "1: DAASSIGNED: a dynamic address is assigned"] - Daassigned = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Davalid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAVALID` reader - Dynamic Address Valid"] -pub type DavalidR = crate::BitReader; -impl DavalidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Davalid { - match self.bits { - false => Davalid::Danotassigned, - true => Davalid::Daassigned, - } - } - #[doc = "DANOTASSIGNED: a dynamic address is not assigned"] - #[inline(always)] - pub fn is_danotassigned(&self) -> bool { - *self == Davalid::Danotassigned - } - #[doc = "DAASSIGNED: a dynamic address is assigned"] - #[inline(always)] - pub fn is_daassigned(&self) -> bool { - *self == Davalid::Daassigned - } -} -#[doc = "Field `DAVALID` writer - Dynamic Address Valid"] -pub type DavalidW<'a, REG> = crate::BitWriter<'a, REG, Davalid>; -impl<'a, REG> DavalidW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "DANOTASSIGNED: a dynamic address is not assigned"] - #[inline(always)] - pub fn danotassigned(self) -> &'a mut crate::W { - self.variant(Davalid::Danotassigned) - } - #[doc = "DAASSIGNED: a dynamic address is assigned"] - #[inline(always)] - pub fn daassigned(self) -> &'a mut crate::W { - self.variant(Davalid::Daassigned) - } -} -#[doc = "Field `DADDR` reader - Dynamic Address"] -pub type DaddrR = crate::FieldReader; -#[doc = "Field `DADDR` writer - Dynamic Address"] -pub type DaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `MAPSA` writer - Map a Static Address"] -pub type MapsaW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SA10B` writer - 10-Bit Static Address"] -pub type Sa10bW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `KEY` reader - Key"] -pub type KeyR = crate::FieldReader; -#[doc = "Field `KEY` writer - Key"] -pub type KeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bit 0 - Dynamic Address Valid"] - #[inline(always)] - pub fn davalid(&self) -> DavalidR { - DavalidR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:7 - Dynamic Address"] - #[inline(always)] - pub fn daddr(&self) -> DaddrR { - DaddrR::new(((self.bits >> 1) & 0x7f) as u8) - } - #[doc = "Bits 16:31 - Key"] - #[inline(always)] - pub fn key(&self) -> KeyR { - KeyR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bit 0 - Dynamic Address Valid"] - #[inline(always)] - pub fn davalid(&mut self) -> DavalidW { - DavalidW::new(self, 0) - } - #[doc = "Bits 1:7 - Dynamic Address"] - #[inline(always)] - pub fn daddr(&mut self) -> DaddrW { - DaddrW::new(self, 1) - } - #[doc = "Bit 12 - Map a Static Address"] - #[inline(always)] - pub fn mapsa(&mut self) -> MapsaW { - MapsaW::new(self, 12) - } - #[doc = "Bits 13:15 - 10-Bit Static Address"] - #[inline(always)] - pub fn sa10b(&mut self) -> Sa10bW { - Sa10bW::new(self, 13) - } - #[doc = "Bits 16:31 - Key"] - #[inline(always)] - pub fn key(&mut self) -> KeyW { - KeyW::new(self, 16) - } -} -#[doc = "Target Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sdynaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdynaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SdynaddrSpec; -impl crate::RegisterSpec for SdynaddrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sdynaddr::R`](R) reader structure"] -impl crate::Readable for SdynaddrSpec {} -#[doc = "`write(|w| ..)` method takes [`sdynaddr::W`](W) writer structure"] -impl crate::Writable for SdynaddrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SDYNADDR to value 0"] -impl crate::Resettable for SdynaddrSpec {} diff --git a/mcxa276-pac/src/i3c0/serrwarn.rs b/mcxa276-pac/src/i3c0/serrwarn.rs deleted file mode 100644 index 811c2a11e..000000000 --- a/mcxa276-pac/src/i3c0/serrwarn.rs +++ /dev/null @@ -1,715 +0,0 @@ -#[doc = "Register `SERRWARN` reader"] -pub type R = crate::R; -#[doc = "Register `SERRWARN` writer"] -pub type W = crate::W; -#[doc = "Overrun Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Orun { - #[doc = "0: No overrun error"] - NoError = 0, - #[doc = "1: Overrun error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Orun) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ORUN` reader - Overrun Error Flag"] -pub type OrunR = crate::BitReader; -impl OrunR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Orun { - match self.bits { - false => Orun::NoError, - true => Orun::Error, - } - } - #[doc = "No overrun error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Orun::NoError - } - #[doc = "Overrun error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Orun::Error - } -} -#[doc = "Field `ORUN` writer - Overrun Error Flag"] -pub type OrunW<'a, REG> = crate::BitWriter1C<'a, REG, Orun>; -impl<'a, REG> OrunW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overrun error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Orun::NoError) - } - #[doc = "Overrun error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Orun::Error) - } -} -#[doc = "Underrun Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Urun { - #[doc = "0: No underrun error"] - NoError = 0, - #[doc = "1: Underrun error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Urun) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `URUN` reader - Underrun Error Flag"] -pub type UrunR = crate::BitReader; -impl UrunR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Urun { - match self.bits { - false => Urun::NoError, - true => Urun::Error, - } - } - #[doc = "No underrun error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Urun::NoError - } - #[doc = "Underrun error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Urun::Error - } -} -#[doc = "Field `URUN` writer - Underrun Error Flag"] -pub type UrunW<'a, REG> = crate::BitWriter1C<'a, REG, Urun>; -impl<'a, REG> UrunW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No underrun error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Urun::NoError) - } - #[doc = "Underrun error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Urun::Error) - } -} -#[doc = "Underrun and Not Acknowledged (NACKed) Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Urunnack { - #[doc = "0: No underrun; not acknowledged error"] - NoError = 0, - #[doc = "1: Underrun; not acknowledged error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Urunnack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `URUNNACK` reader - Underrun and Not Acknowledged (NACKed) Error Flag"] -pub type UrunnackR = crate::BitReader; -impl UrunnackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Urunnack { - match self.bits { - false => Urunnack::NoError, - true => Urunnack::Error, - } - } - #[doc = "No underrun; not acknowledged error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Urunnack::NoError - } - #[doc = "Underrun; not acknowledged error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Urunnack::Error - } -} -#[doc = "Field `URUNNACK` writer - Underrun and Not Acknowledged (NACKed) Error Flag"] -pub type UrunnackW<'a, REG> = crate::BitWriter1C<'a, REG, Urunnack>; -impl<'a, REG> UrunnackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No underrun; not acknowledged error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Urunnack::NoError) - } - #[doc = "Underrun; not acknowledged error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Urunnack::Error) - } -} -#[doc = "Terminated Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Term { - #[doc = "0: No terminated error"] - NoError = 0, - #[doc = "1: Terminated error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Term) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TERM` reader - Terminated Error Flag"] -pub type TermR = crate::BitReader; -impl TermR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Term { - match self.bits { - false => Term::NoError, - true => Term::Error, - } - } - #[doc = "No terminated error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Term::NoError - } - #[doc = "Terminated error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Term::Error - } -} -#[doc = "Field `TERM` writer - Terminated Error Flag"] -pub type TermW<'a, REG> = crate::BitWriter1C<'a, REG, Term>; -impl<'a, REG> TermW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No terminated error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Term::NoError) - } - #[doc = "Terminated error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Term::Error) - } -} -#[doc = "Invalid Start Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Invstart { - #[doc = "0: No invalid start error"] - NoError = 0, - #[doc = "1: Invalid start error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Invstart) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INVSTART` reader - Invalid Start Error Flag"] -pub type InvstartR = crate::BitReader; -impl InvstartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Invstart { - match self.bits { - false => Invstart::NoError, - true => Invstart::Error, - } - } - #[doc = "No invalid start error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Invstart::NoError - } - #[doc = "Invalid start error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Invstart::Error - } -} -#[doc = "Field `INVSTART` writer - Invalid Start Error Flag"] -pub type InvstartW<'a, REG> = crate::BitWriter1C<'a, REG, Invstart>; -impl<'a, REG> InvstartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No invalid start error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Invstart::NoError) - } - #[doc = "Invalid start error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Invstart::Error) - } -} -#[doc = "SDR Parity Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spar { - #[doc = "0: No SDR parity error"] - NoError = 0, - #[doc = "1: SDR parity error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spar) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPAR` reader - SDR Parity Error Flag"] -pub type SparR = crate::BitReader; -impl SparR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spar { - match self.bits { - false => Spar::NoError, - true => Spar::Error, - } - } - #[doc = "No SDR parity error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Spar::NoError - } - #[doc = "SDR parity error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Spar::Error - } -} -#[doc = "Field `SPAR` writer - SDR Parity Error Flag"] -pub type SparW<'a, REG> = crate::BitWriter1C<'a, REG, Spar>; -impl<'a, REG> SparW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No SDR parity error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Spar::NoError) - } - #[doc = "SDR parity error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Spar::Error) - } -} -#[doc = "HDR Parity Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hpar { - #[doc = "0: No HDR parity error"] - NoError = 0, - #[doc = "1: HDR parity error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hpar) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HPAR` reader - HDR Parity Error Flag"] -pub type HparR = crate::BitReader; -impl HparR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hpar { - match self.bits { - false => Hpar::NoError, - true => Hpar::Error, - } - } - #[doc = "No HDR parity error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Hpar::NoError - } - #[doc = "HDR parity error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Hpar::Error - } -} -#[doc = "Field `HPAR` writer - HDR Parity Error Flag"] -pub type HparW<'a, REG> = crate::BitWriter1C<'a, REG, Hpar>; -impl<'a, REG> HparW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No HDR parity error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Hpar::NoError) - } - #[doc = "HDR parity error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Hpar::Error) - } -} -#[doc = "HDR-DDR CRC Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hcrc { - #[doc = "0: No HDR-DDR CRC error occurred"] - NoError = 0, - #[doc = "1: HDR-DDR CRC error occurred"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hcrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HCRC` reader - HDR-DDR CRC Error Flag"] -pub type HcrcR = crate::BitReader; -impl HcrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hcrc { - match self.bits { - false => Hcrc::NoError, - true => Hcrc::Error, - } - } - #[doc = "No HDR-DDR CRC error occurred"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Hcrc::NoError - } - #[doc = "HDR-DDR CRC error occurred"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Hcrc::Error - } -} -#[doc = "Field `HCRC` writer - HDR-DDR CRC Error Flag"] -pub type HcrcW<'a, REG> = crate::BitWriter1C<'a, REG, Hcrc>; -impl<'a, REG> HcrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No HDR-DDR CRC error occurred"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Hcrc::NoError) - } - #[doc = "HDR-DDR CRC error occurred"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Hcrc::Error) - } -} -#[doc = "TE0 or TE1 Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum S0s1 { - #[doc = "0: No TE0 or TE1 error occurred"] - NoError = 0, - #[doc = "1: TE0 or TE1 error occurred"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: S0s1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `S0S1` reader - TE0 or TE1 Error Flag"] -pub type S0s1R = crate::BitReader; -impl S0s1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> S0s1 { - match self.bits { - false => S0s1::NoError, - true => S0s1::Error, - } - } - #[doc = "No TE0 or TE1 error occurred"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == S0s1::NoError - } - #[doc = "TE0 or TE1 error occurred"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == S0s1::Error - } -} -#[doc = "Field `S0S1` writer - TE0 or TE1 Error Flag"] -pub type S0s1W<'a, REG> = crate::BitWriter1C<'a, REG, S0s1>; -impl<'a, REG> S0s1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No TE0 or TE1 error occurred"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(S0s1::NoError) - } - #[doc = "TE0 or TE1 error occurred"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(S0s1::Error) - } -} -#[doc = "Over-Read Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Oread { - #[doc = "0: No over-read error"] - NoError = 0, - #[doc = "1: Over-read error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Oread) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OREAD` reader - Over-Read Error Flag"] -pub type OreadR = crate::BitReader; -impl OreadR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Oread { - match self.bits { - false => Oread::NoError, - true => Oread::Error, - } - } - #[doc = "No over-read error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Oread::NoError - } - #[doc = "Over-read error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Oread::Error - } -} -#[doc = "Field `OREAD` writer - Over-Read Error Flag"] -pub type OreadW<'a, REG> = crate::BitWriter1C<'a, REG, Oread>; -impl<'a, REG> OreadW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No over-read error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Oread::NoError) - } - #[doc = "Over-read error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Oread::Error) - } -} -#[doc = "Over-Write Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Owrite { - #[doc = "0: No overwrite error"] - NoError = 0, - #[doc = "1: Overwrite error"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Owrite) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OWRITE` reader - Over-Write Error Flag"] -pub type OwriteR = crate::BitReader; -impl OwriteR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Owrite { - match self.bits { - false => Owrite::NoError, - true => Owrite::Error, - } - } - #[doc = "No overwrite error"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Owrite::NoError - } - #[doc = "Overwrite error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Owrite::Error - } -} -#[doc = "Field `OWRITE` writer - Over-Write Error Flag"] -pub type OwriteW<'a, REG> = crate::BitWriter1C<'a, REG, Owrite>; -impl<'a, REG> OwriteW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overwrite error"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Owrite::NoError) - } - #[doc = "Overwrite error"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Owrite::Error) - } -} -impl R { - #[doc = "Bit 0 - Overrun Error Flag"] - #[inline(always)] - pub fn orun(&self) -> OrunR { - OrunR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Underrun Error Flag"] - #[inline(always)] - pub fn urun(&self) -> UrunR { - UrunR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Underrun and Not Acknowledged (NACKed) Error Flag"] - #[inline(always)] - pub fn urunnack(&self) -> UrunnackR { - UrunnackR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Terminated Error Flag"] - #[inline(always)] - pub fn term(&self) -> TermR { - TermR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Invalid Start Error Flag"] - #[inline(always)] - pub fn invstart(&self) -> InvstartR { - InvstartR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 8 - SDR Parity Error Flag"] - #[inline(always)] - pub fn spar(&self) -> SparR { - SparR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - HDR Parity Error Flag"] - #[inline(always)] - pub fn hpar(&self) -> HparR { - HparR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - HDR-DDR CRC Error Flag"] - #[inline(always)] - pub fn hcrc(&self) -> HcrcR { - HcrcR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - TE0 or TE1 Error Flag"] - #[inline(always)] - pub fn s0s1(&self) -> S0s1R { - S0s1R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 16 - Over-Read Error Flag"] - #[inline(always)] - pub fn oread(&self) -> OreadR { - OreadR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Over-Write Error Flag"] - #[inline(always)] - pub fn owrite(&self) -> OwriteR { - OwriteR::new(((self.bits >> 17) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Overrun Error Flag"] - #[inline(always)] - pub fn orun(&mut self) -> OrunW { - OrunW::new(self, 0) - } - #[doc = "Bit 1 - Underrun Error Flag"] - #[inline(always)] - pub fn urun(&mut self) -> UrunW { - UrunW::new(self, 1) - } - #[doc = "Bit 2 - Underrun and Not Acknowledged (NACKed) Error Flag"] - #[inline(always)] - pub fn urunnack(&mut self) -> UrunnackW { - UrunnackW::new(self, 2) - } - #[doc = "Bit 3 - Terminated Error Flag"] - #[inline(always)] - pub fn term(&mut self) -> TermW { - TermW::new(self, 3) - } - #[doc = "Bit 4 - Invalid Start Error Flag"] - #[inline(always)] - pub fn invstart(&mut self) -> InvstartW { - InvstartW::new(self, 4) - } - #[doc = "Bit 8 - SDR Parity Error Flag"] - #[inline(always)] - pub fn spar(&mut self) -> SparW { - SparW::new(self, 8) - } - #[doc = "Bit 9 - HDR Parity Error Flag"] - #[inline(always)] - pub fn hpar(&mut self) -> HparW { - HparW::new(self, 9) - } - #[doc = "Bit 10 - HDR-DDR CRC Error Flag"] - #[inline(always)] - pub fn hcrc(&mut self) -> HcrcW { - HcrcW::new(self, 10) - } - #[doc = "Bit 11 - TE0 or TE1 Error Flag"] - #[inline(always)] - pub fn s0s1(&mut self) -> S0s1W { - S0s1W::new(self, 11) - } - #[doc = "Bit 16 - Over-Read Error Flag"] - #[inline(always)] - pub fn oread(&mut self) -> OreadW { - OreadW::new(self, 16) - } - #[doc = "Bit 17 - Over-Write Error Flag"] - #[inline(always)] - pub fn owrite(&mut self) -> OwriteW { - OwriteW::new(self, 17) - } -} -#[doc = "Target Errors and Warnings\n\nYou can [`read`](crate::Reg::read) this register and get [`serrwarn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`serrwarn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SerrwarnSpec; -impl crate::RegisterSpec for SerrwarnSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`serrwarn::R`](R) reader structure"] -impl crate::Readable for SerrwarnSpec {} -#[doc = "`write(|w| ..)` method takes [`serrwarn::W`](W) writer structure"] -impl crate::Writable for SerrwarnSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0003_0f1f; -} -#[doc = "`reset()` method sets SERRWARN to value 0"] -impl crate::Resettable for SerrwarnSpec {} diff --git a/mcxa276-pac/src/i3c0/sid.rs b/mcxa276-pac/src/i3c0/sid.rs deleted file mode 100644 index 169c84886..000000000 --- a/mcxa276-pac/src/i3c0/sid.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SID` reader"] -pub type R = crate::R; -#[doc = "Field `ID` reader - ID"] -pub type IdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - ID"] - #[inline(always)] - pub fn id(&self) -> IdR { - IdR::new(self.bits) - } -} -#[doc = "Target Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SidSpec; -impl crate::RegisterSpec for SidSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sid::R`](R) reader structure"] -impl crate::Readable for SidSpec {} -#[doc = "`reset()` method sets SID to value 0xedcb_0100"] -impl crate::Resettable for SidSpec { - const RESET_VALUE: u32 = 0xedcb_0100; -} diff --git a/mcxa276-pac/src/i3c0/sidext.rs b/mcxa276-pac/src/i3c0/sidext.rs deleted file mode 100644 index bb25a3385..000000000 --- a/mcxa276-pac/src/i3c0/sidext.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SIDEXT` reader"] -pub type R = crate::R; -#[doc = "Register `SIDEXT` writer"] -pub type W = crate::W; -#[doc = "Field `DCR` reader - Device Characteristic Register"] -pub type DcrR = crate::FieldReader; -#[doc = "Field `DCR` writer - Device Characteristic Register"] -pub type DcrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `BCR` reader - Bus Characteristics Register"] -pub type BcrR = crate::FieldReader; -#[doc = "Field `BCR` writer - Bus Characteristics Register"] -pub type BcrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 8:15 - Device Characteristic Register"] - #[inline(always)] - pub fn dcr(&self) -> DcrR { - DcrR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Bus Characteristics Register"] - #[inline(always)] - pub fn bcr(&self) -> BcrR { - BcrR::new(((self.bits >> 16) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 8:15 - Device Characteristic Register"] - #[inline(always)] - pub fn dcr(&mut self) -> DcrW { - DcrW::new(self, 8) - } - #[doc = "Bits 16:23 - Bus Characteristics Register"] - #[inline(always)] - pub fn bcr(&mut self) -> BcrW { - BcrW::new(self, 16) - } -} -#[doc = "Target ID Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`sidext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SidextSpec; -impl crate::RegisterSpec for SidextSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sidext::R`](R) reader structure"] -impl crate::Readable for SidextSpec {} -#[doc = "`write(|w| ..)` method takes [`sidext::W`](W) writer structure"] -impl crate::Writable for SidextSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SIDEXT to value 0x0066_ef00"] -impl crate::Resettable for SidextSpec { - const RESET_VALUE: u32 = 0x0066_ef00; -} diff --git a/mcxa276-pac/src/i3c0/sidpartno.rs b/mcxa276-pac/src/i3c0/sidpartno.rs deleted file mode 100644 index ce972d60d..000000000 --- a/mcxa276-pac/src/i3c0/sidpartno.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SIDPARTNO` reader"] -pub type R = crate::R; -#[doc = "Register `SIDPARTNO` writer"] -pub type W = crate::W; -#[doc = "Field `PARTNO` reader - Part Number"] -pub type PartnoR = crate::FieldReader; -#[doc = "Field `PARTNO` writer - Part Number"] -pub type PartnoW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Part Number"] - #[inline(always)] - pub fn partno(&self) -> PartnoR { - PartnoR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Part Number"] - #[inline(always)] - pub fn partno(&mut self) -> PartnoW { - PartnoW::new(self, 0) - } -} -#[doc = "Target ID Part Number\n\nYou can [`read`](crate::Reg::read) this register and get [`sidpartno::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidpartno::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SidpartnoSpec; -impl crate::RegisterSpec for SidpartnoSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sidpartno::R`](R) reader structure"] -impl crate::Readable for SidpartnoSpec {} -#[doc = "`write(|w| ..)` method takes [`sidpartno::W`](W) writer structure"] -impl crate::Writable for SidpartnoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SIDPARTNO to value 0x3000_0000"] -impl crate::Resettable for SidpartnoSpec { - const RESET_VALUE: u32 = 0x3000_0000; -} diff --git a/mcxa276-pac/src/i3c0/sintclr.rs b/mcxa276-pac/src/i3c0/sintclr.rs deleted file mode 100644 index 090fce885..000000000 --- a/mcxa276-pac/src/i3c0/sintclr.rs +++ /dev/null @@ -1,176 +0,0 @@ -#[doc = "Register `SINTCLR` reader"] -pub type R = crate::R; -#[doc = "Register `SINTCLR` writer"] -pub type W = crate::W; -#[doc = "Field `START` reader - START Interrupt Enable Clear Flag"] -pub type StartR = crate::BitReader; -#[doc = "Field `START` writer - START Interrupt Enable Clear Flag"] -pub type StartW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `MATCHED` reader - Matched Interrupt Enable Clear Flag"] -pub type MatchedR = crate::BitReader; -#[doc = "Field `MATCHED` writer - Matched Interrupt Enable Clear Flag"] -pub type MatchedW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `STOP` reader - STOP Interrupt Enable Clear Flag"] -pub type StopR = crate::BitReader; -#[doc = "Field `STOP` writer - STOP Interrupt Enable Clear Flag"] -pub type StopW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `RXPEND` reader - RXPEND Interrupt Enable Clear Flag"] -pub type RxpendR = crate::BitReader; -#[doc = "Field `RXPEND` writer - RXPEND Interrupt Enable Clear Flag"] -pub type RxpendW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `TXSEND` reader - TXSEND Interrupt Enable Clear Flag"] -pub type TxsendR = crate::BitReader; -#[doc = "Field `TXSEND` writer - TXSEND Interrupt Enable Clear Flag"] -pub type TxsendW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `DACHG` reader - DACHG Interrupt Enable Clear Flag"] -pub type DachgR = crate::BitReader; -#[doc = "Field `DACHG` writer - DACHG Interrupt Enable Clear Flag"] -pub type DachgW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `CCC` reader - CCC Interrupt Enable Clear Flag"] -pub type CccR = crate::BitReader; -#[doc = "Field `CCC` writer - CCC Interrupt Enable Clear Flag"] -pub type CccW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Enable Clear Flag"] -pub type ErrwarnR = crate::BitReader; -#[doc = "Field `ERRWARN` writer - ERRWARN Interrupt Enable Clear Flag"] -pub type ErrwarnW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `DDRMATCHED` reader - DDRMATCHED Interrupt Enable Clear Flag"] -pub type DdrmatchedR = crate::BitReader; -#[doc = "Field `DDRMATCHED` writer - DDRMATCHED Interrupt Enable Clear Flag"] -pub type DdrmatchedW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `CHANDLED` reader - CHANDLED Interrupt Enable Clear Flag"] -pub type ChandledR = crate::BitReader; -#[doc = "Field `CHANDLED` writer - CHANDLED Interrupt Enable Clear Flag"] -pub type ChandledW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `EVENT` reader - EVENT Interrupt Enable Clear Flag"] -pub type EventR = crate::BitReader; -#[doc = "Field `EVENT` writer - EVENT Interrupt Enable Clear Flag"] -pub type EventW<'a, REG> = crate::BitWriter1C<'a, REG>; -impl R { - #[doc = "Bit 8 - START Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn start(&self) -> StartR { - StartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Matched Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn matched(&self) -> MatchedR { - MatchedR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - STOP Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn stop(&self) -> StopR { - StopR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn rxpend(&self) -> RxpendR { - RxpendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - TXSEND Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn txsend(&self) -> TxsendR { - TxsendR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - DACHG Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn dachg(&self) -> DachgR { - DachgR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - CCC Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn ccc(&self) -> CccR { - CccR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - DDRMATCHED Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn ddrmatched(&self) -> DdrmatchedR { - DdrmatchedR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - CHANDLED Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn chandled(&self) -> ChandledR { - ChandledR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - EVENT Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn event(&self) -> EventR { - EventR::new(((self.bits >> 18) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - START Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn start(&mut self) -> StartW { - StartW::new(self, 8) - } - #[doc = "Bit 9 - Matched Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn matched(&mut self) -> MatchedW { - MatchedW::new(self, 9) - } - #[doc = "Bit 10 - STOP Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn stop(&mut self) -> StopW { - StopW::new(self, 10) - } - #[doc = "Bit 11 - RXPEND Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn rxpend(&mut self) -> RxpendW { - RxpendW::new(self, 11) - } - #[doc = "Bit 12 - TXSEND Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn txsend(&mut self) -> TxsendW { - TxsendW::new(self, 12) - } - #[doc = "Bit 13 - DACHG Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn dachg(&mut self) -> DachgW { - DachgW::new(self, 13) - } - #[doc = "Bit 14 - CCC Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn ccc(&mut self) -> CccW { - CccW::new(self, 14) - } - #[doc = "Bit 15 - ERRWARN Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn errwarn(&mut self) -> ErrwarnW { - ErrwarnW::new(self, 15) - } - #[doc = "Bit 16 - DDRMATCHED Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn ddrmatched(&mut self) -> DdrmatchedW { - DdrmatchedW::new(self, 16) - } - #[doc = "Bit 17 - CHANDLED Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn chandled(&mut self) -> ChandledW { - ChandledW::new(self, 17) - } - #[doc = "Bit 18 - EVENT Interrupt Enable Clear Flag"] - #[inline(always)] - pub fn event(&mut self) -> EventW { - EventW::new(self, 18) - } -} -#[doc = "Target Interrupt Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sintclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SintclrSpec; -impl crate::RegisterSpec for SintclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sintclr::R`](R) reader structure"] -impl crate::Readable for SintclrSpec {} -#[doc = "`write(|w| ..)` method takes [`sintclr::W`](W) writer structure"] -impl crate::Writable for SintclrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ff00; -} -#[doc = "`reset()` method sets SINTCLR to value 0"] -impl crate::Resettable for SintclrSpec {} diff --git a/mcxa276-pac/src/i3c0/sintmasked.rs b/mcxa276-pac/src/i3c0/sintmasked.rs deleted file mode 100644 index dce9621a3..000000000 --- a/mcxa276-pac/src/i3c0/sintmasked.rs +++ /dev/null @@ -1,90 +0,0 @@ -#[doc = "Register `SINTMASKED` reader"] -pub type R = crate::R; -#[doc = "Field `START` reader - START Interrupt Mask"] -pub type StartR = crate::BitReader; -#[doc = "Field `MATCHED` reader - MATCHED Interrupt Mask"] -pub type MatchedR = crate::BitReader; -#[doc = "Field `STOP` reader - STOP Interrupt Mask"] -pub type StopR = crate::BitReader; -#[doc = "Field `RXPEND` reader - RXPEND Interrupt Mask"] -pub type RxpendR = crate::BitReader; -#[doc = "Field `TXSEND` reader - TXSEND Interrupt Mask"] -pub type TxsendR = crate::BitReader; -#[doc = "Field `DACHG` reader - DACHG Interrupt Mask"] -pub type DachgR = crate::BitReader; -#[doc = "Field `CCC` reader - CCC Interrupt Mask"] -pub type CccR = crate::BitReader; -#[doc = "Field `ERRWARN` reader - ERRWARN Interrupt Mask"] -pub type ErrwarnR = crate::BitReader; -#[doc = "Field `DDRMATCHED` reader - DDRMATCHED Interrupt Mask"] -pub type DdrmatchedR = crate::BitReader; -#[doc = "Field `CHANDLED` reader - CHANDLED Interrupt Mask"] -pub type ChandledR = crate::BitReader; -#[doc = "Field `EVENT` reader - EVENT Interrupt Mask"] -pub type EventR = crate::BitReader; -impl R { - #[doc = "Bit 8 - START Interrupt Mask"] - #[inline(always)] - pub fn start(&self) -> StartR { - StartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - MATCHED Interrupt Mask"] - #[inline(always)] - pub fn matched(&self) -> MatchedR { - MatchedR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - STOP Interrupt Mask"] - #[inline(always)] - pub fn stop(&self) -> StopR { - StopR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - RXPEND Interrupt Mask"] - #[inline(always)] - pub fn rxpend(&self) -> RxpendR { - RxpendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - TXSEND Interrupt Mask"] - #[inline(always)] - pub fn txsend(&self) -> TxsendR { - TxsendR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - DACHG Interrupt Mask"] - #[inline(always)] - pub fn dachg(&self) -> DachgR { - DachgR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - CCC Interrupt Mask"] - #[inline(always)] - pub fn ccc(&self) -> CccR { - CccR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - ERRWARN Interrupt Mask"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - DDRMATCHED Interrupt Mask"] - #[inline(always)] - pub fn ddrmatched(&self) -> DdrmatchedR { - DdrmatchedR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - CHANDLED Interrupt Mask"] - #[inline(always)] - pub fn chandled(&self) -> ChandledR { - ChandledR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - EVENT Interrupt Mask"] - #[inline(always)] - pub fn event(&self) -> EventR { - EventR::new(((self.bits >> 18) & 1) != 0) - } -} -#[doc = "Target Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`sintmasked::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SintmaskedSpec; -impl crate::RegisterSpec for SintmaskedSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sintmasked::R`](R) reader structure"] -impl crate::Readable for SintmaskedSpec {} -#[doc = "`reset()` method sets SINTMASKED to value 0"] -impl crate::Resettable for SintmaskedSpec {} diff --git a/mcxa276-pac/src/i3c0/sintset.rs b/mcxa276-pac/src/i3c0/sintset.rs deleted file mode 100644 index 766634744..000000000 --- a/mcxa276-pac/src/i3c0/sintset.rs +++ /dev/null @@ -1,715 +0,0 @@ -#[doc = "Register `SINTSET` reader"] -pub type R = crate::R; -#[doc = "Register `SINTSET` writer"] -pub type W = crate::W; -#[doc = "Start Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Start { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Start) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `START` reader - Start Interrupt Enable"] -pub type StartR = crate::BitReader; -impl StartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Start { - match self.bits { - false => Start::Disable, - true => Start::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Start::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Start::Enable - } -} -#[doc = "Field `START` writer - Start Interrupt Enable"] -pub type StartW<'a, REG> = crate::BitWriter1S<'a, REG, Start>; -impl<'a, REG> StartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Start::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Start::Enable) - } -} -#[doc = "Match Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Matched { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Matched) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MATCHED` reader - Match Interrupt Enable"] -pub type MatchedR = crate::BitReader; -impl MatchedR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Matched { - match self.bits { - false => Matched::Disable, - true => Matched::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Matched::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Matched::Enable - } -} -#[doc = "Field `MATCHED` writer - Match Interrupt Enable"] -pub type MatchedW<'a, REG> = crate::BitWriter1S<'a, REG, Matched>; -impl<'a, REG> MatchedW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Matched::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Matched::Enable) - } -} -#[doc = "Stop Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stop { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stop) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STOP` reader - Stop Interrupt Enable"] -pub type StopR = crate::BitReader; -impl StopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stop { - match self.bits { - false => Stop::Disable, - true => Stop::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Stop::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Stop::Enable - } -} -#[doc = "Field `STOP` writer - Stop Interrupt Enable"] -pub type StopW<'a, REG> = crate::BitWriter1S<'a, REG, Stop>; -impl<'a, REG> StopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Stop::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Stop::Enable) - } -} -#[doc = "Receive Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxpend { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxpend) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXPEND` reader - Receive Interrupt Enable"] -pub type RxpendR = crate::BitReader; -impl RxpendR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxpend { - match self.bits { - false => Rxpend::Disable, - true => Rxpend::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Rxpend::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Rxpend::Enable - } -} -#[doc = "Field `RXPEND` writer - Receive Interrupt Enable"] -pub type RxpendW<'a, REG> = crate::BitWriter1S<'a, REG, Rxpend>; -impl<'a, REG> RxpendW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Rxpend::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Rxpend::Enable) - } -} -#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txsend { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txsend) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXSEND` reader - Transmit Interrupt Enable"] -pub type TxsendR = crate::BitReader; -impl TxsendR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txsend { - match self.bits { - false => Txsend::Disable, - true => Txsend::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Txsend::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Txsend::Enable - } -} -#[doc = "Field `TXSEND` writer - Transmit Interrupt Enable"] -pub type TxsendW<'a, REG> = crate::BitWriter1S<'a, REG, Txsend>; -impl<'a, REG> TxsendW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Txsend::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Txsend::Enable) - } -} -#[doc = "Dynamic Address Change Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dachg { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dachg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DACHG` reader - Dynamic Address Change Interrupt Enable"] -pub type DachgR = crate::BitReader; -impl DachgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dachg { - match self.bits { - false => Dachg::Disable, - true => Dachg::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Dachg::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dachg::Enable - } -} -#[doc = "Field `DACHG` writer - Dynamic Address Change Interrupt Enable"] -pub type DachgW<'a, REG> = crate::BitWriter1S<'a, REG, Dachg>; -impl<'a, REG> DachgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Dachg::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dachg::Enable) - } -} -#[doc = "Common Command Code (CCC) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ccc { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ccc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CCC` reader - Common Command Code (CCC) Interrupt Enable"] -pub type CccR = crate::BitReader; -impl CccR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ccc { - match self.bits { - false => Ccc::Disable, - true => Ccc::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ccc::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ccc::Enable - } -} -#[doc = "Field `CCC` writer - Common Command Code (CCC) Interrupt Enable"] -pub type CccW<'a, REG> = crate::BitWriter1S<'a, REG, Ccc>; -impl<'a, REG> CccW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ccc::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ccc::Enable) - } -} -#[doc = "Error or Warning Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Errwarn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Errwarn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERRWARN` reader - Error or Warning Interrupt Enable"] -pub type ErrwarnR = crate::BitReader; -impl ErrwarnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Errwarn { - match self.bits { - false => Errwarn::Disable, - true => Errwarn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Errwarn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Errwarn::Enable - } -} -#[doc = "Field `ERRWARN` writer - Error or Warning Interrupt Enable"] -pub type ErrwarnW<'a, REG> = crate::BitWriter1S<'a, REG, Errwarn>; -impl<'a, REG> ErrwarnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Errwarn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Errwarn::Enable) - } -} -#[doc = "Double Data Rate Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ddrmatched { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ddrmatched) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DDRMATCHED` reader - Double Data Rate Interrupt Enable"] -pub type DdrmatchedR = crate::BitReader; -impl DdrmatchedR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ddrmatched { - match self.bits { - false => Ddrmatched::Disable, - true => Ddrmatched::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ddrmatched::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ddrmatched::Enable - } -} -#[doc = "Field `DDRMATCHED` writer - Double Data Rate Interrupt Enable"] -pub type DdrmatchedW<'a, REG> = crate::BitWriter1S<'a, REG, Ddrmatched>; -impl<'a, REG> DdrmatchedW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ddrmatched::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ddrmatched::Enable) - } -} -#[doc = "Common Command Code (CCC) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Chandled { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Chandled) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CHANDLED` reader - Common Command Code (CCC) Interrupt Enable"] -pub type ChandledR = crate::BitReader; -impl ChandledR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Chandled { - match self.bits { - false => Chandled::Disable, - true => Chandled::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Chandled::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Chandled::Enable - } -} -#[doc = "Field `CHANDLED` writer - Common Command Code (CCC) Interrupt Enable"] -pub type ChandledW<'a, REG> = crate::BitWriter1S<'a, REG, Chandled>; -impl<'a, REG> ChandledW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Chandled::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Chandled::Enable) - } -} -#[doc = "Event Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Event { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Event) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EVENT` reader - Event Interrupt Enable"] -pub type EventR = crate::BitReader; -impl EventR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Event { - match self.bits { - false => Event::Disable, - true => Event::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Event::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Event::Enable - } -} -#[doc = "Field `EVENT` writer - Event Interrupt Enable"] -pub type EventW<'a, REG> = crate::BitWriter1S<'a, REG, Event>; -impl<'a, REG> EventW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Event::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Event::Enable) - } -} -impl R { - #[doc = "Bit 8 - Start Interrupt Enable"] - #[inline(always)] - pub fn start(&self) -> StartR { - StartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Match Interrupt Enable"] - #[inline(always)] - pub fn matched(&self) -> MatchedR { - MatchedR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Stop Interrupt Enable"] - #[inline(always)] - pub fn stop(&self) -> StopR { - StopR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Receive Interrupt Enable"] - #[inline(always)] - pub fn rxpend(&self) -> RxpendR { - RxpendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Transmit Interrupt Enable"] - #[inline(always)] - pub fn txsend(&self) -> TxsendR { - TxsendR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Dynamic Address Change Interrupt Enable"] - #[inline(always)] - pub fn dachg(&self) -> DachgR { - DachgR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Common Command Code (CCC) Interrupt Enable"] - #[inline(always)] - pub fn ccc(&self) -> CccR { - CccR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Error or Warning Interrupt Enable"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Double Data Rate Interrupt Enable"] - #[inline(always)] - pub fn ddrmatched(&self) -> DdrmatchedR { - DdrmatchedR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Common Command Code (CCC) Interrupt Enable"] - #[inline(always)] - pub fn chandled(&self) -> ChandledR { - ChandledR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Event Interrupt Enable"] - #[inline(always)] - pub fn event(&self) -> EventR { - EventR::new(((self.bits >> 18) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - Start Interrupt Enable"] - #[inline(always)] - pub fn start(&mut self) -> StartW { - StartW::new(self, 8) - } - #[doc = "Bit 9 - Match Interrupt Enable"] - #[inline(always)] - pub fn matched(&mut self) -> MatchedW { - MatchedW::new(self, 9) - } - #[doc = "Bit 10 - Stop Interrupt Enable"] - #[inline(always)] - pub fn stop(&mut self) -> StopW { - StopW::new(self, 10) - } - #[doc = "Bit 11 - Receive Interrupt Enable"] - #[inline(always)] - pub fn rxpend(&mut self) -> RxpendW { - RxpendW::new(self, 11) - } - #[doc = "Bit 12 - Transmit Interrupt Enable"] - #[inline(always)] - pub fn txsend(&mut self) -> TxsendW { - TxsendW::new(self, 12) - } - #[doc = "Bit 13 - Dynamic Address Change Interrupt Enable"] - #[inline(always)] - pub fn dachg(&mut self) -> DachgW { - DachgW::new(self, 13) - } - #[doc = "Bit 14 - Common Command Code (CCC) Interrupt Enable"] - #[inline(always)] - pub fn ccc(&mut self) -> CccW { - CccW::new(self, 14) - } - #[doc = "Bit 15 - Error or Warning Interrupt Enable"] - #[inline(always)] - pub fn errwarn(&mut self) -> ErrwarnW { - ErrwarnW::new(self, 15) - } - #[doc = "Bit 16 - Double Data Rate Interrupt Enable"] - #[inline(always)] - pub fn ddrmatched(&mut self) -> DdrmatchedW { - DdrmatchedW::new(self, 16) - } - #[doc = "Bit 17 - Common Command Code (CCC) Interrupt Enable"] - #[inline(always)] - pub fn chandled(&mut self) -> ChandledW { - ChandledW::new(self, 17) - } - #[doc = "Bit 18 - Event Interrupt Enable"] - #[inline(always)] - pub fn event(&mut self) -> EventW { - EventW::new(self, 18) - } -} -#[doc = "Target Interrupt Set\n\nYou can [`read`](crate::Reg::read) this register and get [`sintset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sintset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SintsetSpec; -impl crate::RegisterSpec for SintsetSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sintset::R`](R) reader structure"] -impl crate::Readable for SintsetSpec {} -#[doc = "`write(|w| ..)` method takes [`sintset::W`](W) writer structure"] -impl crate::Writable for SintsetSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ff00; -} -#[doc = "`reset()` method sets SINTSET to value 0"] -impl crate::Resettable for SintsetSpec {} diff --git a/mcxa276-pac/src/i3c0/smapctrl0.rs b/mcxa276-pac/src/i3c0/smapctrl0.rs deleted file mode 100644 index 7d1bad73b..000000000 --- a/mcxa276-pac/src/i3c0/smapctrl0.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `SMAPCTRL0` reader"] -pub type R = crate::R; -#[doc = "Enable Primary Dynamic Address\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ena { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ena) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENA` reader - Enable Primary Dynamic Address"] -pub type EnaR = crate::BitReader; -impl EnaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ena { - match self.bits { - false => Ena::Disable, - true => Ena::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ena::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ena::Enable - } -} -#[doc = "Field `DA` reader - Dynamic Address"] -pub type DaR = crate::FieldReader; -#[doc = "Cause\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cause { - #[doc = "0: No information (this value occurs when not configured to write DA)"] - None = 0, - #[doc = "1: Set using ENTDAA"] - Entdaa = 1, - #[doc = "2: Set using SETDASA, SETAASA, or SETNEWDA"] - Setdasa = 2, - #[doc = "3: Cleared using RSTDAA"] - Rstdaa = 3, - #[doc = "4: Auto MAP change happened last"] - Automap = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cause) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cause { - type Ux = u8; -} -impl crate::IsEnum for Cause {} -#[doc = "Field `CAUSE` reader - Cause"] -pub type CauseR = crate::FieldReader; -impl CauseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cause::None), - 1 => Some(Cause::Entdaa), - 2 => Some(Cause::Setdasa), - 3 => Some(Cause::Rstdaa), - 4 => Some(Cause::Automap), - _ => None, - } - } - #[doc = "No information (this value occurs when not configured to write DA)"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Cause::None - } - #[doc = "Set using ENTDAA"] - #[inline(always)] - pub fn is_entdaa(&self) -> bool { - *self == Cause::Entdaa - } - #[doc = "Set using SETDASA, SETAASA, or SETNEWDA"] - #[inline(always)] - pub fn is_setdasa(&self) -> bool { - *self == Cause::Setdasa - } - #[doc = "Cleared using RSTDAA"] - #[inline(always)] - pub fn is_rstdaa(&self) -> bool { - *self == Cause::Rstdaa - } - #[doc = "Auto MAP change happened last"] - #[inline(always)] - pub fn is_automap(&self) -> bool { - *self == Cause::Automap - } -} -impl R { - #[doc = "Bit 0 - Enable Primary Dynamic Address"] - #[inline(always)] - pub fn ena(&self) -> EnaR { - EnaR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:7 - Dynamic Address"] - #[inline(always)] - pub fn da(&self) -> DaR { - DaR::new(((self.bits >> 1) & 0x7f) as u8) - } - #[doc = "Bits 8:10 - Cause"] - #[inline(always)] - pub fn cause(&self) -> CauseR { - CauseR::new(((self.bits >> 8) & 7) as u8) - } -} -#[doc = "Map Feature Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`smapctrl0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Smapctrl0Spec; -impl crate::RegisterSpec for Smapctrl0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`smapctrl0::R`](R) reader structure"] -impl crate::Readable for Smapctrl0Spec {} -#[doc = "`reset()` method sets SMAPCTRL0 to value 0"] -impl crate::Resettable for Smapctrl0Spec {} diff --git a/mcxa276-pac/src/i3c0/smaxlimits.rs b/mcxa276-pac/src/i3c0/smaxlimits.rs deleted file mode 100644 index 646940296..000000000 --- a/mcxa276-pac/src/i3c0/smaxlimits.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `SMAXLIMITS` reader"] -pub type R = crate::R; -#[doc = "Register `SMAXLIMITS` writer"] -pub type W = crate::W; -#[doc = "Field `MAXRD` reader - Maximum Read Length"] -pub type MaxrdR = crate::FieldReader; -#[doc = "Field `MAXRD` writer - Maximum Read Length"] -pub type MaxrdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `MAXWR` reader - Maximum Write Length"] -pub type MaxwrR = crate::FieldReader; -#[doc = "Field `MAXWR` writer - Maximum Write Length"] -pub type MaxwrW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -impl R { - #[doc = "Bits 0:11 - Maximum Read Length"] - #[inline(always)] - pub fn maxrd(&self) -> MaxrdR { - MaxrdR::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:27 - Maximum Write Length"] - #[inline(always)] - pub fn maxwr(&self) -> MaxwrR { - MaxwrR::new(((self.bits >> 16) & 0x0fff) as u16) - } -} -impl W { - #[doc = "Bits 0:11 - Maximum Read Length"] - #[inline(always)] - pub fn maxrd(&mut self) -> MaxrdW { - MaxrdW::new(self, 0) - } - #[doc = "Bits 16:27 - Maximum Write Length"] - #[inline(always)] - pub fn maxwr(&mut self) -> MaxwrW { - MaxwrW::new(self, 16) - } -} -#[doc = "Target Maximum Limits\n\nYou can [`read`](crate::Reg::read) this register and get [`smaxlimits::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smaxlimits::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SmaxlimitsSpec; -impl crate::RegisterSpec for SmaxlimitsSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`smaxlimits::R`](R) reader structure"] -impl crate::Readable for SmaxlimitsSpec {} -#[doc = "`write(|w| ..)` method takes [`smaxlimits::W`](W) writer structure"] -impl crate::Writable for SmaxlimitsSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SMAXLIMITS to value 0"] -impl crate::Resettable for SmaxlimitsSpec {} diff --git a/mcxa276-pac/src/i3c0/smsgmapaddr.rs b/mcxa276-pac/src/i3c0/smsgmapaddr.rs deleted file mode 100644 index c853cd7e3..000000000 --- a/mcxa276-pac/src/i3c0/smsgmapaddr.rs +++ /dev/null @@ -1,75 +0,0 @@ -#[doc = "Register `SMSGMAPADDR` reader"] -pub type R = crate::R; -#[doc = "Field `MAPLAST` reader - Matched Address Index"] -pub type MaplastR = crate::FieldReader; -#[doc = "Last Static Address Matched\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Laststatic { - #[doc = "0: I3C dynamic address"] - I3c = 0, - #[doc = "1: I2C static address"] - I2c = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Laststatic) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LASTSTATIC` reader - Last Static Address Matched"] -pub type LaststaticR = crate::BitReader; -impl LaststaticR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Laststatic { - match self.bits { - false => Laststatic::I3c, - true => Laststatic::I2c, - } - } - #[doc = "I3C dynamic address"] - #[inline(always)] - pub fn is_i3c(&self) -> bool { - *self == Laststatic::I3c - } - #[doc = "I2C static address"] - #[inline(always)] - pub fn is_i2c(&self) -> bool { - *self == Laststatic::I2c - } -} -#[doc = "Field `MAPLASTM1` reader - Matched Previous Address Index 1"] -pub type Maplastm1R = crate::FieldReader; -#[doc = "Field `MAPLASTM2` reader - Matched Previous Index 2"] -pub type Maplastm2R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Matched Address Index"] - #[inline(always)] - pub fn maplast(&self) -> MaplastR { - MaplastR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 4 - Last Static Address Matched"] - #[inline(always)] - pub fn laststatic(&self) -> LaststaticR { - LaststaticR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 8:11 - Matched Previous Address Index 1"] - #[inline(always)] - pub fn maplastm1(&self) -> Maplastm1R { - Maplastm1R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 16:19 - Matched Previous Index 2"] - #[inline(always)] - pub fn maplastm2(&self) -> Maplastm2R { - Maplastm2R::new(((self.bits >> 16) & 0x0f) as u8) - } -} -#[doc = "Target Message Map Address\n\nYou can [`read`](crate::Reg::read) this register and get [`smsgmapaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SmsgmapaddrSpec; -impl crate::RegisterSpec for SmsgmapaddrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`smsgmapaddr::R`](R) reader structure"] -impl crate::Readable for SmsgmapaddrSpec {} -#[doc = "`reset()` method sets SMSGMAPADDR to value 0"] -impl crate::Resettable for SmsgmapaddrSpec {} diff --git a/mcxa276-pac/src/i3c0/srdatab.rs b/mcxa276-pac/src/i3c0/srdatab.rs deleted file mode 100644 index 1d3b85a8d..000000000 --- a/mcxa276-pac/src/i3c0/srdatab.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SRDATAB` reader"] -pub type R = crate::R; -#[doc = "Field `DATA0` reader - Data 0"] -pub type Data0R = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Data 0"] - #[inline(always)] - pub fn data0(&self) -> Data0R { - Data0R::new((self.bits & 0xff) as u8) - } -} -#[doc = "Target Read Data Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatab::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrdatabSpec; -impl crate::RegisterSpec for SrdatabSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`srdatab::R`](R) reader structure"] -impl crate::Readable for SrdatabSpec {} -#[doc = "`reset()` method sets SRDATAB to value 0"] -impl crate::Resettable for SrdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/srdatah.rs b/mcxa276-pac/src/i3c0/srdatah.rs deleted file mode 100644 index e25167f76..000000000 --- a/mcxa276-pac/src/i3c0/srdatah.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `SRDATAH` reader"] -pub type R = crate::R; -#[doc = "Field `LSB` reader - Low Byte"] -pub type LsbR = crate::FieldReader; -#[doc = "Field `MSB` reader - High Byte"] -pub type MsbR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Low Byte"] - #[inline(always)] - pub fn lsb(&self) -> LsbR { - LsbR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - High Byte"] - #[inline(always)] - pub fn msb(&self) -> MsbR { - MsbR::new(((self.bits >> 8) & 0xff) as u8) - } -} -#[doc = "Target Read Data Halfword\n\nYou can [`read`](crate::Reg::read) this register and get [`srdatah::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrdatahSpec; -impl crate::RegisterSpec for SrdatahSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`srdatah::R`](R) reader structure"] -impl crate::Readable for SrdatahSpec {} -#[doc = "`reset()` method sets SRDATAH to value 0"] -impl crate::Resettable for SrdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/sstatus.rs b/mcxa276-pac/src/i3c0/sstatus.rs deleted file mode 100644 index d02f9d08a..000000000 --- a/mcxa276-pac/src/i3c0/sstatus.rs +++ /dev/null @@ -1,1216 +0,0 @@ -#[doc = "Register `SSTATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SSTATUS` writer"] -pub type W = crate::W; -#[doc = "Status not Stop\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stnotstop { - #[doc = "0: In STOP condition"] - Stopped = 0, - #[doc = "1: Busy"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stnotstop) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STNOTSTOP` reader - Status not Stop"] -pub type StnotstopR = crate::BitReader; -impl StnotstopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stnotstop { - match self.bits { - false => Stnotstop::Stopped, - true => Stnotstop::Busy, - } - } - #[doc = "In STOP condition"] - #[inline(always)] - pub fn is_stopped(&self) -> bool { - *self == Stnotstop::Stopped - } - #[doc = "Busy"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Stnotstop::Busy - } -} -#[doc = "Status Message\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stmsg { - #[doc = "0: Idle"] - Idle = 0, - #[doc = "1: Busy"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stmsg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STMSG` reader - Status Message"] -pub type StmsgR = crate::BitReader; -impl StmsgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stmsg { - match self.bits { - false => Stmsg::Idle, - true => Stmsg::Busy, - } - } - #[doc = "Idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Stmsg::Idle - } - #[doc = "Busy"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Stmsg::Busy - } -} -#[doc = "Status Common Command Code Handler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stccch { - #[doc = "0: No CCC message handled"] - Idle = 0, - #[doc = "1: Handled automatically"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stccch) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STCCCH` reader - Status Common Command Code Handler"] -pub type StccchR = crate::BitReader; -impl StccchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stccch { - match self.bits { - false => Stccch::Idle, - true => Stccch::Busy, - } - } - #[doc = "No CCC message handled"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Stccch::Idle - } - #[doc = "Handled automatically"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Stccch::Busy - } -} -#[doc = "Status Request Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Streqrd { - #[doc = "0: Not an SDR read"] - Idle = 0, - #[doc = "1: SDR read from this target or an IBI is being pushed out"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Streqrd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STREQRD` reader - Status Request Read"] -pub type StreqrdR = crate::BitReader; -impl StreqrdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Streqrd { - match self.bits { - false => Streqrd::Idle, - true => Streqrd::Busy, - } - } - #[doc = "Not an SDR read"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Streqrd::Idle - } - #[doc = "SDR read from this target or an IBI is being pushed out"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Streqrd::Busy - } -} -#[doc = "Status Request Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Streqwr { - #[doc = "0: Not an SDR write"] - Idle = 0, - #[doc = "1: SDR write data from the controller, but not in ENTDAA mode"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Streqwr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STREQWR` reader - Status Request Write"] -pub type StreqwrR = crate::BitReader; -impl StreqwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Streqwr { - match self.bits { - false => Streqwr::Idle, - true => Streqwr::Busy, - } - } - #[doc = "Not an SDR write"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Streqwr::Idle - } - #[doc = "SDR write data from the controller, but not in ENTDAA mode"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Streqwr::Busy - } -} -#[doc = "Status Dynamic Address Assignment\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stdaa { - #[doc = "0: Not in ENTDAA mode"] - NotInEntdaa = 0, - #[doc = "1: In ENTDAA mode"] - InEntdaa = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stdaa) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STDAA` reader - Status Dynamic Address Assignment"] -pub type StdaaR = crate::BitReader; -impl StdaaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stdaa { - match self.bits { - false => Stdaa::NotInEntdaa, - true => Stdaa::InEntdaa, - } - } - #[doc = "Not in ENTDAA mode"] - #[inline(always)] - pub fn is_not_in_entdaa(&self) -> bool { - *self == Stdaa::NotInEntdaa - } - #[doc = "In ENTDAA mode"] - #[inline(always)] - pub fn is_in_entdaa(&self) -> bool { - *self == Stdaa::InEntdaa - } -} -#[doc = "Status High Data Rate\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sthdr { - #[doc = "0: I3C bus not in HDR-DDR mode"] - NotInHdrDdr = 0, - #[doc = "1: I3C bus in HDR-DDR mode"] - InHdrDdr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sthdr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STHDR` reader - Status High Data Rate"] -pub type SthdrR = crate::BitReader; -impl SthdrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sthdr { - match self.bits { - false => Sthdr::NotInHdrDdr, - true => Sthdr::InHdrDdr, - } - } - #[doc = "I3C bus not in HDR-DDR mode"] - #[inline(always)] - pub fn is_not_in_hdr_ddr(&self) -> bool { - *self == Sthdr::NotInHdrDdr - } - #[doc = "I3C bus in HDR-DDR mode"] - #[inline(always)] - pub fn is_in_hdr_ddr(&self) -> bool { - *self == Sthdr::InHdrDdr - } -} -#[doc = "Start Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Start { - #[doc = "0: Not detected"] - StartNotDetected = 0, - #[doc = "1: Detected"] - StartDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Start) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `START` reader - Start Flag"] -pub type StartR = crate::BitReader; -impl StartR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Start { - match self.bits { - false => Start::StartNotDetected, - true => Start::StartDetected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_start_not_detected(&self) -> bool { - *self == Start::StartNotDetected - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_start_detected(&self) -> bool { - *self == Start::StartDetected - } -} -#[doc = "Field `START` writer - Start Flag"] -pub type StartW<'a, REG> = crate::BitWriter1C<'a, REG, Start>; -impl<'a, REG> StartW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn start_not_detected(self) -> &'a mut crate::W { - self.variant(Start::StartNotDetected) - } - #[doc = "Detected"] - #[inline(always)] - pub fn start_detected(self) -> &'a mut crate::W { - self.variant(Start::StartDetected) - } -} -#[doc = "Matched Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Matched { - #[doc = "0: Header not matched"] - NotMatched = 0, - #[doc = "1: Header matched"] - Matched = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Matched) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MATCHED` reader - Matched Flag"] -pub type MatchedR = crate::BitReader; -impl MatchedR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Matched { - match self.bits { - false => Matched::NotMatched, - true => Matched::Matched, - } - } - #[doc = "Header not matched"] - #[inline(always)] - pub fn is_not_matched(&self) -> bool { - *self == Matched::NotMatched - } - #[doc = "Header matched"] - #[inline(always)] - pub fn is_matched(&self) -> bool { - *self == Matched::Matched - } -} -#[doc = "Field `MATCHED` writer - Matched Flag"] -pub type MatchedW<'a, REG> = crate::BitWriter1C<'a, REG, Matched>; -impl<'a, REG> MatchedW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Header not matched"] - #[inline(always)] - pub fn not_matched(self) -> &'a mut crate::W { - self.variant(Matched::NotMatched) - } - #[doc = "Header matched"] - #[inline(always)] - pub fn matched(self) -> &'a mut crate::W { - self.variant(Matched::Matched) - } -} -#[doc = "Stop Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stop { - #[doc = "0: No Stopped state detected"] - NoStopDetected = 0, - #[doc = "1: Stopped state detected"] - StopDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stop) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STOP` reader - Stop Flag"] -pub type StopR = crate::BitReader; -impl StopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stop { - match self.bits { - false => Stop::NoStopDetected, - true => Stop::StopDetected, - } - } - #[doc = "No Stopped state detected"] - #[inline(always)] - pub fn is_no_stop_detected(&self) -> bool { - *self == Stop::NoStopDetected - } - #[doc = "Stopped state detected"] - #[inline(always)] - pub fn is_stop_detected(&self) -> bool { - *self == Stop::StopDetected - } -} -#[doc = "Field `STOP` writer - Stop Flag"] -pub type StopW<'a, REG> = crate::BitWriter1C<'a, REG, Stop>; -impl<'a, REG> StopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No Stopped state detected"] - #[inline(always)] - pub fn no_stop_detected(self) -> &'a mut crate::W { - self.variant(Stop::NoStopDetected) - } - #[doc = "Stopped state detected"] - #[inline(always)] - pub fn stop_detected(self) -> &'a mut crate::W { - self.variant(Stop::StopDetected) - } -} -#[doc = "Received Message Pending\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RxPend { - #[doc = "0: No received message pending"] - NoMsgPending = 0, - #[doc = "1: Received message pending"] - MsgPending = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RxPend) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RX_PEND` reader - Received Message Pending"] -pub type RxPendR = crate::BitReader; -impl RxPendR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RxPend { - match self.bits { - false => RxPend::NoMsgPending, - true => RxPend::MsgPending, - } - } - #[doc = "No received message pending"] - #[inline(always)] - pub fn is_no_msg_pending(&self) -> bool { - *self == RxPend::NoMsgPending - } - #[doc = "Received message pending"] - #[inline(always)] - pub fn is_msg_pending(&self) -> bool { - *self == RxPend::MsgPending - } -} -#[doc = "Transmit Buffer Not Full\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txnotfull { - #[doc = "0: Transmit buffer full"] - Full = 0, - #[doc = "1: Transmit buffer not full"] - NotFull = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txnotfull) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXNOTFULL` reader - Transmit Buffer Not Full"] -pub type TxnotfullR = crate::BitReader; -impl TxnotfullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txnotfull { - match self.bits { - false => Txnotfull::Full, - true => Txnotfull::NotFull, - } - } - #[doc = "Transmit buffer full"] - #[inline(always)] - pub fn is_full(&self) -> bool { - *self == Txnotfull::Full - } - #[doc = "Transmit buffer not full"] - #[inline(always)] - pub fn is_not_full(&self) -> bool { - *self == Txnotfull::NotFull - } -} -#[doc = "Dynamic Address Change Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dachg { - #[doc = "0: No DA change detected"] - NoChangeDetected = 0, - #[doc = "1: DA change detected"] - ChangeDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dachg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DACHG` reader - Dynamic Address Change Flag"] -pub type DachgR = crate::BitReader; -impl DachgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dachg { - match self.bits { - false => Dachg::NoChangeDetected, - true => Dachg::ChangeDetected, - } - } - #[doc = "No DA change detected"] - #[inline(always)] - pub fn is_no_change_detected(&self) -> bool { - *self == Dachg::NoChangeDetected - } - #[doc = "DA change detected"] - #[inline(always)] - pub fn is_change_detected(&self) -> bool { - *self == Dachg::ChangeDetected - } -} -#[doc = "Field `DACHG` writer - Dynamic Address Change Flag"] -pub type DachgW<'a, REG> = crate::BitWriter1C<'a, REG, Dachg>; -impl<'a, REG> DachgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No DA change detected"] - #[inline(always)] - pub fn no_change_detected(self) -> &'a mut crate::W { - self.variant(Dachg::NoChangeDetected) - } - #[doc = "DA change detected"] - #[inline(always)] - pub fn change_detected(self) -> &'a mut crate::W { - self.variant(Dachg::ChangeDetected) - } -} -#[doc = "Common Command Code Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ccc { - #[doc = "0: CCC not received"] - NoCccReceived = 0, - #[doc = "1: CCC received"] - CccReceived = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ccc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CCC` reader - Common Command Code Flag"] -pub type CccR = crate::BitReader; -impl CccR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ccc { - match self.bits { - false => Ccc::NoCccReceived, - true => Ccc::CccReceived, - } - } - #[doc = "CCC not received"] - #[inline(always)] - pub fn is_no_ccc_received(&self) -> bool { - *self == Ccc::NoCccReceived - } - #[doc = "CCC received"] - #[inline(always)] - pub fn is_ccc_received(&self) -> bool { - *self == Ccc::CccReceived - } -} -#[doc = "Field `CCC` writer - Common Command Code Flag"] -pub type CccW<'a, REG> = crate::BitWriter1C<'a, REG, Ccc>; -impl<'a, REG> CccW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "CCC not received"] - #[inline(always)] - pub fn no_ccc_received(self) -> &'a mut crate::W { - self.variant(Ccc::NoCccReceived) - } - #[doc = "CCC received"] - #[inline(always)] - pub fn ccc_received(self) -> &'a mut crate::W { - self.variant(Ccc::CccReceived) - } -} -#[doc = "Field `ERRWARN` reader - Error Warning"] -pub type ErrwarnR = crate::BitReader; -#[doc = "High Data Rate Command Match Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hdrmatch { - #[doc = "0: Did not match"] - NoMatch = 0, - #[doc = "1: Matched the I3C dynamic address"] - Match = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hdrmatch) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HDRMATCH` reader - High Data Rate Command Match Flag"] -pub type HdrmatchR = crate::BitReader; -impl HdrmatchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hdrmatch { - match self.bits { - false => Hdrmatch::NoMatch, - true => Hdrmatch::Match, - } - } - #[doc = "Did not match"] - #[inline(always)] - pub fn is_no_match(&self) -> bool { - *self == Hdrmatch::NoMatch - } - #[doc = "Matched the I3C dynamic address"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Hdrmatch::Match - } -} -#[doc = "Field `HDRMATCH` writer - High Data Rate Command Match Flag"] -pub type HdrmatchW<'a, REG> = crate::BitWriter1C<'a, REG, Hdrmatch>; -impl<'a, REG> HdrmatchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Did not match"] - #[inline(always)] - pub fn no_match(self) -> &'a mut crate::W { - self.variant(Hdrmatch::NoMatch) - } - #[doc = "Matched the I3C dynamic address"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Hdrmatch::Match) - } -} -#[doc = "Common Command Code Handled Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Chandled { - #[doc = "0: CCC handling not in progress"] - NotHandled = 0, - #[doc = "1: CCC handling in progress"] - Handled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Chandled) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CHANDLED` reader - Common Command Code Handled Flag"] -pub type ChandledR = crate::BitReader; -impl ChandledR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Chandled { - match self.bits { - false => Chandled::NotHandled, - true => Chandled::Handled, - } - } - #[doc = "CCC handling not in progress"] - #[inline(always)] - pub fn is_not_handled(&self) -> bool { - *self == Chandled::NotHandled - } - #[doc = "CCC handling in progress"] - #[inline(always)] - pub fn is_handled(&self) -> bool { - *self == Chandled::Handled - } -} -#[doc = "Field `CHANDLED` writer - Common Command Code Handled Flag"] -pub type ChandledW<'a, REG> = crate::BitWriter1C<'a, REG, Chandled>; -impl<'a, REG> ChandledW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "CCC handling not in progress"] - #[inline(always)] - pub fn not_handled(self) -> &'a mut crate::W { - self.variant(Chandled::NotHandled) - } - #[doc = "CCC handling in progress"] - #[inline(always)] - pub fn handled(self) -> &'a mut crate::W { - self.variant(Chandled::Handled) - } -} -#[doc = "Event Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Event { - #[doc = "0: No event occurred"] - NoEvent = 0, - #[doc = "1: IBI, CR, or HJ occurred"] - Event = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Event) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EVENT` reader - Event Flag"] -pub type EventR = crate::BitReader; -impl EventR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Event { - match self.bits { - false => Event::NoEvent, - true => Event::Event, - } - } - #[doc = "No event occurred"] - #[inline(always)] - pub fn is_no_event(&self) -> bool { - *self == Event::NoEvent - } - #[doc = "IBI, CR, or HJ occurred"] - #[inline(always)] - pub fn is_event(&self) -> bool { - *self == Event::Event - } -} -#[doc = "Field `EVENT` writer - Event Flag"] -pub type EventW<'a, REG> = crate::BitWriter1C<'a, REG, Event>; -impl<'a, REG> EventW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No event occurred"] - #[inline(always)] - pub fn no_event(self) -> &'a mut crate::W { - self.variant(Event::NoEvent) - } - #[doc = "IBI, CR, or HJ occurred"] - #[inline(always)] - pub fn event(self) -> &'a mut crate::W { - self.variant(Event::Event) - } -} -#[doc = "Event Details\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Evdet { - #[doc = "0: NONE (no event or no pending event)"] - None = 0, - #[doc = "1: NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))"] - NoRequest = 1, - #[doc = "2: NACKed (not acknowledged, request sent and rejected); I3C tries again"] - Nacked = 2, - #[doc = "3: ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)"] - Acked = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Evdet) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Evdet { - type Ux = u8; -} -impl crate::IsEnum for Evdet {} -#[doc = "Field `EVDET` reader - Event Details"] -pub type EvdetR = crate::FieldReader; -impl EvdetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Evdet { - match self.bits { - 0 => Evdet::None, - 1 => Evdet::NoRequest, - 2 => Evdet::Nacked, - 3 => Evdet::Acked, - _ => unreachable!(), - } - } - #[doc = "NONE (no event or no pending event)"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Evdet::None - } - #[doc = "NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))"] - #[inline(always)] - pub fn is_no_request(&self) -> bool { - *self == Evdet::NoRequest - } - #[doc = "NACKed (not acknowledged, request sent and rejected); I3C tries again"] - #[inline(always)] - pub fn is_nacked(&self) -> bool { - *self == Evdet::Nacked - } - #[doc = "ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)"] - #[inline(always)] - pub fn is_acked(&self) -> bool { - *self == Evdet::Acked - } -} -#[doc = "In-Band Interrupts Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibidis { - #[doc = "0: Enabled"] - InterruptsEnabled = 0, - #[doc = "1: Disabled"] - InterruptsDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibidis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBIDIS` reader - In-Band Interrupts Disable"] -pub type IbidisR = crate::BitReader; -impl IbidisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibidis { - match self.bits { - false => Ibidis::InterruptsEnabled, - true => Ibidis::InterruptsDisabled, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_interrupts_enabled(&self) -> bool { - *self == Ibidis::InterruptsEnabled - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_interrupts_disabled(&self) -> bool { - *self == Ibidis::InterruptsDisabled - } -} -#[doc = "Controller Requests Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mrdis { - #[doc = "0: Enabled"] - MrEnabled = 0, - #[doc = "1: Disabled"] - MrDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mrdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MRDIS` reader - Controller Requests Disable"] -pub type MrdisR = crate::BitReader; -impl MrdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mrdis { - match self.bits { - false => Mrdis::MrEnabled, - true => Mrdis::MrDisabled, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_mr_enabled(&self) -> bool { - *self == Mrdis::MrEnabled - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_mr_disabled(&self) -> bool { - *self == Mrdis::MrDisabled - } -} -#[doc = "Hot-Join Disabled\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hjdis { - #[doc = "0: Enabled"] - MrEnabled = 0, - #[doc = "1: Disabled"] - MrDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hjdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HJDIS` reader - Hot-Join Disabled"] -pub type HjdisR = crate::BitReader; -impl HjdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hjdis { - match self.bits { - false => Hjdis::MrEnabled, - true => Hjdis::MrDisabled, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_mr_enabled(&self) -> bool { - *self == Hjdis::MrEnabled - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_mr_disabled(&self) -> bool { - *self == Hjdis::MrDisabled - } -} -#[doc = "Activity State from Common Command Codes (CCC)\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Actstate { - #[doc = "0: NO_LATENCY (normal bus operations)"] - NoLatency = 0, - #[doc = "1: LATENCY_1MS (1 ms of latency)"] - Latency1ms = 1, - #[doc = "2: LATENCY_100MS (100 ms of latency)"] - Latency100ms = 2, - #[doc = "3: LATENCY_10S (10 seconds of latency)"] - Latency10s = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Actstate) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Actstate { - type Ux = u8; -} -impl crate::IsEnum for Actstate {} -#[doc = "Field `ACTSTATE` reader - Activity State from Common Command Codes (CCC)"] -pub type ActstateR = crate::FieldReader; -impl ActstateR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Actstate { - match self.bits { - 0 => Actstate::NoLatency, - 1 => Actstate::Latency1ms, - 2 => Actstate::Latency100ms, - 3 => Actstate::Latency10s, - _ => unreachable!(), - } - } - #[doc = "NO_LATENCY (normal bus operations)"] - #[inline(always)] - pub fn is_no_latency(&self) -> bool { - *self == Actstate::NoLatency - } - #[doc = "LATENCY_1MS (1 ms of latency)"] - #[inline(always)] - pub fn is_latency_1ms(&self) -> bool { - *self == Actstate::Latency1ms - } - #[doc = "LATENCY_100MS (100 ms of latency)"] - #[inline(always)] - pub fn is_latency_100ms(&self) -> bool { - *self == Actstate::Latency100ms - } - #[doc = "LATENCY_10S (10 seconds of latency)"] - #[inline(always)] - pub fn is_latency_10s(&self) -> bool { - *self == Actstate::Latency10s - } -} -#[doc = "Time Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Timectrl { - #[doc = "0: NO_TIME_CONTROL (no time control is enabled)"] - NoTimeControl = 0, - #[doc = "1: SYNC_MODE (Synchronous mode is enabled)"] - Sync = 1, - #[doc = "2: ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)"] - AsyncMode = 2, - #[doc = "3: BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)"] - Bothsyncasync = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Timectrl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Timectrl { - type Ux = u8; -} -impl crate::IsEnum for Timectrl {} -#[doc = "Field `TIMECTRL` reader - Time Control"] -pub type TimectrlR = crate::FieldReader; -impl TimectrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timectrl { - match self.bits { - 0 => Timectrl::NoTimeControl, - 1 => Timectrl::Sync, - 2 => Timectrl::AsyncMode, - 3 => Timectrl::Bothsyncasync, - _ => unreachable!(), - } - } - #[doc = "NO_TIME_CONTROL (no time control is enabled)"] - #[inline(always)] - pub fn is_no_time_control(&self) -> bool { - *self == Timectrl::NoTimeControl - } - #[doc = "SYNC_MODE (Synchronous mode is enabled)"] - #[inline(always)] - pub fn is_sync(&self) -> bool { - *self == Timectrl::Sync - } - #[doc = "ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)"] - #[inline(always)] - pub fn is_async_mode(&self) -> bool { - *self == Timectrl::AsyncMode - } - #[doc = "BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)"] - #[inline(always)] - pub fn is_bothsyncasync(&self) -> bool { - *self == Timectrl::Bothsyncasync - } -} -impl R { - #[doc = "Bit 0 - Status not Stop"] - #[inline(always)] - pub fn stnotstop(&self) -> StnotstopR { - StnotstopR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Status Message"] - #[inline(always)] - pub fn stmsg(&self) -> StmsgR { - StmsgR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Status Common Command Code Handler"] - #[inline(always)] - pub fn stccch(&self) -> StccchR { - StccchR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Status Request Read"] - #[inline(always)] - pub fn streqrd(&self) -> StreqrdR { - StreqrdR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Status Request Write"] - #[inline(always)] - pub fn streqwr(&self) -> StreqwrR { - StreqwrR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Status Dynamic Address Assignment"] - #[inline(always)] - pub fn stdaa(&self) -> StdaaR { - StdaaR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Status High Data Rate"] - #[inline(always)] - pub fn sthdr(&self) -> SthdrR { - SthdrR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - Start Flag"] - #[inline(always)] - pub fn start(&self) -> StartR { - StartR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Matched Flag"] - #[inline(always)] - pub fn matched(&self) -> MatchedR { - MatchedR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Stop Flag"] - #[inline(always)] - pub fn stop(&self) -> StopR { - StopR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Received Message Pending"] - #[inline(always)] - pub fn rx_pend(&self) -> RxPendR { - RxPendR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Transmit Buffer Not Full"] - #[inline(always)] - pub fn txnotfull(&self) -> TxnotfullR { - TxnotfullR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Dynamic Address Change Flag"] - #[inline(always)] - pub fn dachg(&self) -> DachgR { - DachgR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Common Command Code Flag"] - #[inline(always)] - pub fn ccc(&self) -> CccR { - CccR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Error Warning"] - #[inline(always)] - pub fn errwarn(&self) -> ErrwarnR { - ErrwarnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - High Data Rate Command Match Flag"] - #[inline(always)] - pub fn hdrmatch(&self) -> HdrmatchR { - HdrmatchR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Common Command Code Handled Flag"] - #[inline(always)] - pub fn chandled(&self) -> ChandledR { - ChandledR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Event Flag"] - #[inline(always)] - pub fn event(&self) -> EventR { - EventR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bits 20:21 - Event Details"] - #[inline(always)] - pub fn evdet(&self) -> EvdetR { - EvdetR::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bit 24 - In-Band Interrupts Disable"] - #[inline(always)] - pub fn ibidis(&self) -> IbidisR { - IbidisR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Controller Requests Disable"] - #[inline(always)] - pub fn mrdis(&self) -> MrdisR { - MrdisR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 27 - Hot-Join Disabled"] - #[inline(always)] - pub fn hjdis(&self) -> HjdisR { - HjdisR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:29 - Activity State from Common Command Codes (CCC)"] - #[inline(always)] - pub fn actstate(&self) -> ActstateR { - ActstateR::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bits 30:31 - Time Control"] - #[inline(always)] - pub fn timectrl(&self) -> TimectrlR { - TimectrlR::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bit 8 - Start Flag"] - #[inline(always)] - pub fn start(&mut self) -> StartW { - StartW::new(self, 8) - } - #[doc = "Bit 9 - Matched Flag"] - #[inline(always)] - pub fn matched(&mut self) -> MatchedW { - MatchedW::new(self, 9) - } - #[doc = "Bit 10 - Stop Flag"] - #[inline(always)] - pub fn stop(&mut self) -> StopW { - StopW::new(self, 10) - } - #[doc = "Bit 13 - Dynamic Address Change Flag"] - #[inline(always)] - pub fn dachg(&mut self) -> DachgW { - DachgW::new(self, 13) - } - #[doc = "Bit 14 - Common Command Code Flag"] - #[inline(always)] - pub fn ccc(&mut self) -> CccW { - CccW::new(self, 14) - } - #[doc = "Bit 16 - High Data Rate Command Match Flag"] - #[inline(always)] - pub fn hdrmatch(&mut self) -> HdrmatchW { - HdrmatchW::new(self, 16) - } - #[doc = "Bit 17 - Common Command Code Handled Flag"] - #[inline(always)] - pub fn chandled(&mut self) -> ChandledW { - ChandledW::new(self, 17) - } - #[doc = "Bit 18 - Event Flag"] - #[inline(always)] - pub fn event(&mut self) -> EventW { - EventW::new(self, 18) - } -} -#[doc = "Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SstatusSpec; -impl crate::RegisterSpec for SstatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sstatus::R`](R) reader structure"] -impl crate::Readable for SstatusSpec {} -#[doc = "`write(|w| ..)` method takes [`sstatus::W`](W) writer structure"] -impl crate::Writable for SstatusSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_6700; -} -#[doc = "`reset()` method sets SSTATUS to value 0x1400"] -impl crate::Resettable for SstatusSpec { - const RESET_VALUE: u32 = 0x1400; -} diff --git a/mcxa276-pac/src/i3c0/stcclock.rs b/mcxa276-pac/src/i3c0/stcclock.rs deleted file mode 100644 index 3dc6e039c..000000000 --- a/mcxa276-pac/src/i3c0/stcclock.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `STCCLOCK` reader"] -pub type R = crate::R; -#[doc = "Register `STCCLOCK` writer"] -pub type W = crate::W; -#[doc = "Field `ACCURACY` reader - Clock Accuracy"] -pub type AccuracyR = crate::FieldReader; -#[doc = "Field `ACCURACY` writer - Clock Accuracy"] -pub type AccuracyW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `FREQ` reader - Clock Frequency"] -pub type FreqR = crate::FieldReader; -#[doc = "Field `FREQ` writer - Clock Frequency"] -pub type FreqW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Clock Accuracy"] - #[inline(always)] - pub fn accuracy(&self) -> AccuracyR { - AccuracyR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Clock Frequency"] - #[inline(always)] - pub fn freq(&self) -> FreqR { - FreqR::new(((self.bits >> 8) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Clock Accuracy"] - #[inline(always)] - pub fn accuracy(&mut self) -> AccuracyW { - AccuracyW::new(self, 0) - } - #[doc = "Bits 8:15 - Clock Frequency"] - #[inline(always)] - pub fn freq(&mut self) -> FreqW { - FreqW::new(self, 8) - } -} -#[doc = "Target Time Control Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`stcclock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stcclock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StcclockSpec; -impl crate::RegisterSpec for StcclockSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`stcclock::R`](R) reader structure"] -impl crate::Readable for StcclockSpec {} -#[doc = "`write(|w| ..)` method takes [`stcclock::W`](W) writer structure"] -impl crate::Writable for StcclockSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STCCLOCK to value 0x3014"] -impl crate::Resettable for StcclockSpec { - const RESET_VALUE: u32 = 0x3014; -} diff --git a/mcxa276-pac/src/i3c0/svendorid.rs b/mcxa276-pac/src/i3c0/svendorid.rs deleted file mode 100644 index 3baa73692..000000000 --- a/mcxa276-pac/src/i3c0/svendorid.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SVENDORID` reader"] -pub type R = crate::R; -#[doc = "Register `SVENDORID` writer"] -pub type W = crate::W; -#[doc = "Field `VID` reader - Vendor ID"] -pub type VidR = crate::FieldReader; -#[doc = "Field `VID` writer - Vendor ID"] -pub type VidW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; -impl R { - #[doc = "Bits 0:14 - Vendor ID"] - #[inline(always)] - pub fn vid(&self) -> VidR { - VidR::new((self.bits & 0x7fff) as u16) - } -} -impl W { - #[doc = "Bits 0:14 - Vendor ID"] - #[inline(always)] - pub fn vid(&mut self) -> VidW { - VidW::new(self, 0) - } -} -#[doc = "Target Vendor ID\n\nYou can [`read`](crate::Reg::read) this register and get [`svendorid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`svendorid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SvendoridSpec; -impl crate::RegisterSpec for SvendoridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`svendorid::R`](R) reader structure"] -impl crate::Readable for SvendoridSpec {} -#[doc = "`write(|w| ..)` method takes [`svendorid::W`](W) writer structure"] -impl crate::Writable for SvendoridSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SVENDORID to value 0x011b"] -impl crate::Resettable for SvendoridSpec { - const RESET_VALUE: u32 = 0x011b; -} diff --git a/mcxa276-pac/src/i3c0/swdatab.rs b/mcxa276-pac/src/i3c0/swdatab.rs deleted file mode 100644 index 1455e1c40..000000000 --- a/mcxa276-pac/src/i3c0/swdatab.rs +++ /dev/null @@ -1,94 +0,0 @@ -#[doc = "Register `SWDATAB` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "End\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum End { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: End) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END` writer - End"] -pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; -impl<'a, REG> EndW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(End::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(End::End) - } -} -#[doc = "End Also\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EndAlso { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EndAlso) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END_ALSO` writer - End Also"] -pub type EndAlsoW<'a, REG> = crate::BitWriter<'a, REG, EndAlso>; -impl<'a, REG> EndAlsoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(EndAlso::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(EndAlso::End) - } -} -impl W { - #[doc = "Bits 0:7 - Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } - #[doc = "Bit 8 - End"] - #[inline(always)] - pub fn end(&mut self) -> EndW { - EndW::new(self, 8) - } - #[doc = "Bit 16 - End Also"] - #[inline(always)] - pub fn end_also(&mut self) -> EndAlsoW { - EndAlsoW::new(self, 16) - } -} -#[doc = "Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatab::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SwdatabSpec; -impl crate::RegisterSpec for SwdatabSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`swdatab::W`](W) writer structure"] -impl crate::Writable for SwdatabSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWDATAB to value 0"] -impl crate::Resettable for SwdatabSpec {} diff --git a/mcxa276-pac/src/i3c0/swdatabe.rs b/mcxa276-pac/src/i3c0/swdatabe.rs deleted file mode 100644 index e72d0bf90..000000000 --- a/mcxa276-pac/src/i3c0/swdatabe.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `SWDATABE` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Target Write Data Byte End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatabe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SwdatabeSpec; -impl crate::RegisterSpec for SwdatabeSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`swdatabe::W`](W) writer structure"] -impl crate::Writable for SwdatabeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWDATABE to value 0"] -impl crate::Resettable for SwdatabeSpec {} diff --git a/mcxa276-pac/src/i3c0/swdatah.rs b/mcxa276-pac/src/i3c0/swdatah.rs deleted file mode 100644 index 2c2f2af44..000000000 --- a/mcxa276-pac/src/i3c0/swdatah.rs +++ /dev/null @@ -1,65 +0,0 @@ -#[doc = "Register `SWDATAH` writer"] -pub type W = crate::W; -#[doc = "Field `DATA0` writer - Data 0"] -pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA1` writer - Data 1"] -pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "End of Message\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum End { - #[doc = "0: Not the end"] - NotEnd = 0, - #[doc = "1: End"] - End = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: End) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `END` writer - End of Message"] -pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>; -impl<'a, REG> EndW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not the end"] - #[inline(always)] - pub fn not_end(self) -> &'a mut crate::W { - self.variant(End::NotEnd) - } - #[doc = "End"] - #[inline(always)] - pub fn end(self) -> &'a mut crate::W { - self.variant(End::End) - } -} -impl W { - #[doc = "Bits 0:7 - Data 0"] - #[inline(always)] - pub fn data0(&mut self) -> Data0W { - Data0W::new(self, 0) - } - #[doc = "Bits 8:15 - Data 1"] - #[inline(always)] - pub fn data1(&mut self) -> Data1W { - Data1W::new(self, 8) - } - #[doc = "Bit 16 - End of Message"] - #[inline(always)] - pub fn end(&mut self) -> EndW { - EndW::new(self, 16) - } -} -#[doc = "Target Write Data Halfword\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatah::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SwdatahSpec; -impl crate::RegisterSpec for SwdatahSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`swdatah::W`](W) writer structure"] -impl crate::Writable for SwdatahSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWDATAH to value 0"] -impl crate::Resettable for SwdatahSpec {} diff --git a/mcxa276-pac/src/i3c0/swdatahe.rs b/mcxa276-pac/src/i3c0/swdatahe.rs deleted file mode 100644 index c54041f54..000000000 --- a/mcxa276-pac/src/i3c0/swdatahe.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `SWDATAHE` writer"] -pub type W = crate::W; -#[doc = "Field `DATA0` writer - Data 0"] -pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA1` writer - Data 1"] -pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Data 0"] - #[inline(always)] - pub fn data0(&mut self) -> Data0W { - Data0W::new(self, 0) - } - #[doc = "Bits 8:15 - Data 1"] - #[inline(always)] - pub fn data1(&mut self) -> Data1W { - Data1W::new(self, 8) - } -} -#[doc = "Target Write Data Halfword End\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatahe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SwdataheSpec; -impl crate::RegisterSpec for SwdataheSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`swdatahe::W`](W) writer structure"] -impl crate::Writable for SwdataheSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWDATAHE to value 0"] -impl crate::Resettable for SwdataheSpec {} diff --git a/mcxa276-pac/src/inputmux0.rs b/mcxa276-pac/src/inputmux0.rs deleted file mode 100644 index 9faa6aeb0..000000000 --- a/mcxa276-pac/src/inputmux0.rs +++ /dev/null @@ -1,1012 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x20], - ctimer0cap: [Ctimer0cap; 4], - timer0trig: Timer0trig, - _reserved2: [u8; 0x0c], - ctimer1cap: [Ctimer1cap; 4], - timer1trig: Timer1trig, - _reserved4: [u8; 0x0c], - ctimer2cap: [Ctimer2cap; 4], - timer2trig: Timer2trig, - _reserved6: [u8; 0x2c], - smart_dma_trig: [SmartDmaTrig; 8], - _reserved7: [u8; 0xc0], - freqmeas_ref: FreqmeasRef, - freqmeas_tar: FreqmeasTar, - _reserved9: [u8; 0x18], - ctimer3cap: [Ctimer3cap; 4], - timer3trig: Timer3trig, - _reserved11: [u8; 0x0c], - ctimer4cap: [Ctimer4cap; 4], - timer4trig: Timer4trig, - _reserved13: [u8; 0x2c], - aoi1_input: [Aoi1Input; 16], - _reserved14: [u8; 0x20], - cmp0_trig: Cmp0Trig, - _reserved15: [u8; 0x1c], - adc0_trig: [Adc0Trig; 4], - _reserved16: [u8; 0x10], - adc2_trig: [Adc2Trig; 4], - _reserved17: [u8; 0x10], - adc1_trig: [Adc1Trig; 4], - _reserved18: [u8; 0x10], - adc3_trig: [Adc3Trig; 4], - _reserved19: [u8; 0x10], - dac0_trig: Dac0Trig, - _reserved20: [u8; 0x5c], - qdc0_trig: Qdc0Trig, - qdc0_home: Qdc0Home, - qdc0_index: Qdc0Index, - qdc0_phaseb: Qdc0Phaseb, - qdc0_phasea: Qdc0Phasea, - qdc0_icap1: Qdc0Icap1, - qdc0_icap2: Qdc0Icap2, - qdc0_icap3: Qdc0Icap3, - qdc1_trig: Qdc1Trig, - qdc1_home: Qdc1Home, - qdc1_index: Qdc1Index, - qdc1_phaseb: Qdc1Phaseb, - qdc1_phasea: Qdc1Phasea, - qdc1_icap1: Qdc1Icap1, - qdc1_icap2: Qdc1Icap2, - qdc1_icap3: Qdc1Icap3, - flex_pwm0_sm0_exta0: FlexPwm0Sm0Exta0, - flex_pwm0_sm0_extsync: FlexPwm0Sm0Extsync, - flex_pwm0_sm1_exta: FlexPwm0Sm1Exta, - flex_pwm0_sm1_extsync: FlexPwm0Sm1Extsync, - flex_pwm0_sm2_exta: FlexPwm0Sm2Exta, - flex_pwm0_sm2_extsync: FlexPwm0Sm2Extsync, - flex_pwm0_sm3_exta0: FlexPwm0Sm3Exta0, - flex_pwm0_sm3_extsync: FlexPwm0Sm3Extsync, - flex_pwm0_fault: [FlexPwm0Fault; 4], - flex_pwm0_force: FlexPwm0Force, - _reserved46: [u8; 0x0c], - flex_pwm1_sm0_exta0: FlexPwm1Sm0Exta0, - flex_pwm1_sm0_extsync: FlexPwm1Sm0Extsync, - flex_pwm1_sm1_exta: FlexPwm1Sm1Exta, - flex_pwm1_sm1_extsync: FlexPwm1Sm1Extsync, - flex_pwm1_sm2_exta: FlexPwm1Sm2Exta, - flex_pwm1_sm2_extsync: FlexPwm1Sm2Extsync, - flex_pwm1_sm3_exta0: FlexPwm1Sm3Exta0, - flex_pwm1_sm3_extsync: FlexPwm1Sm3Extsync, - flex_pwm1_fault: [FlexPwm1Fault; 4], - flex_pwm1_force: FlexPwm1Force, - _reserved56: [u8; 0x0c], - pwm0_ext_clk: Pwm0ExtClk, - pwm1_ext_clk: Pwm1ExtClk, - _reserved58: [u8; 0x18], - aoi0_input: [Aoi0Input; 16], - usbfs_trig: UsbfsTrig, - _reserved60: [u8; 0x3c], - ext_trig: [ExtTrig; 8], - cmp1_trig: Cmp1Trig, - _reserved62: [u8; 0x1c], - cmp2_trig: Cmp2Trig, - _reserved63: [u8; 0x3c], - lpi2c2_trig: Lpi2c2Trig, - _reserved64: [u8; 0x1c], - lpi2c3_trig: Lpi2c3Trig, - _reserved65: [u8; 0x3c], - lpi2c0_trig: Lpi2c0Trig, - _reserved66: [u8; 0x1c], - lpi2c1_trig: Lpi2c1Trig, - _reserved67: [u8; 0x1c], - lpspi0_trig: Lpspi0Trig, - _reserved68: [u8; 0x1c], - lpspi1_trig: Lpspi1Trig, - _reserved69: [u8; 0x1c], - lpuart0: Lpuart0, - _reserved70: [u8; 0x1c], - lpuart1: Lpuart1, - _reserved71: [u8; 0x1c], - lpuart2: Lpuart2, - _reserved72: [u8; 0x1c], - lpuart3: Lpuart3, - _reserved73: [u8; 0x1c], - lpuart4: Lpuart4, - _reserved74: [u8; 0x1c], - lpuart5: Lpuart5, - _reserved75: [u8; 0x1c], - flexio_trig: [FlexioTrig; 4], - _reserved76: [u8; 0x0310], - trigfil_prsc: TrigfilPrsc, - trigfil_stat0: TrigfilStat0, - _reserved78: [u8; 0x08], - trigfil: [Trigfil; 12], -} -impl RegisterBlock { - #[doc = "0x20..0x30 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub const fn ctimer0cap(&self, n: usize) -> &Ctimer0cap { - &self.ctimer0cap[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x20..0x30 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub fn ctimer0cap_iter(&self) -> impl Iterator { - self.ctimer0cap.iter() - } - #[doc = "0x30 - Trigger register for TIMER0"] - #[inline(always)] - pub const fn timer0trig(&self) -> &Timer0trig { - &self.timer0trig - } - #[doc = "0x40..0x50 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub const fn ctimer1cap(&self, n: usize) -> &Ctimer1cap { - &self.ctimer1cap[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x40..0x50 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub fn ctimer1cap_iter(&self) -> impl Iterator { - self.ctimer1cap.iter() - } - #[doc = "0x50 - Trigger register for TIMER1"] - #[inline(always)] - pub const fn timer1trig(&self) -> &Timer1trig { - &self.timer1trig - } - #[doc = "0x60..0x70 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub const fn ctimer2cap(&self, n: usize) -> &Ctimer2cap { - &self.ctimer2cap[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x60..0x70 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub fn ctimer2cap_iter(&self) -> impl Iterator { - self.ctimer2cap.iter() - } - #[doc = "0x70 - Trigger register for TIMER2 inputs"] - #[inline(always)] - pub const fn timer2trig(&self) -> &Timer2trig { - &self.timer2trig - } - #[doc = "0xa0..0xc0 - SmartDMA Trigger Input Connections"] - #[inline(always)] - pub const fn smart_dma_trig(&self, n: usize) -> &SmartDmaTrig { - &self.smart_dma_trig[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0xa0..0xc0 - SmartDMA Trigger Input Connections"] - #[inline(always)] - pub fn smart_dma_trig_iter(&self) -> impl Iterator { - self.smart_dma_trig.iter() - } - #[doc = "0x180 - Selection for frequency measurement reference clock"] - #[inline(always)] - pub const fn freqmeas_ref(&self) -> &FreqmeasRef { - &self.freqmeas_ref - } - #[doc = "0x184 - Selection for frequency measurement reference clock"] - #[inline(always)] - pub const fn freqmeas_tar(&self) -> &FreqmeasTar { - &self.freqmeas_tar - } - #[doc = "0x1a0..0x1b0 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub const fn ctimer3cap(&self, n: usize) -> &Ctimer3cap { - &self.ctimer3cap[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x1a0..0x1b0 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub fn ctimer3cap_iter(&self) -> impl Iterator { - self.ctimer3cap.iter() - } - #[doc = "0x1b0 - Trigger register for TIMER3"] - #[inline(always)] - pub const fn timer3trig(&self) -> &Timer3trig { - &self.timer3trig - } - #[doc = "0x1c0..0x1d0 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub const fn ctimer4cap(&self, n: usize) -> &Ctimer4cap { - &self.ctimer4cap[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x1c0..0x1d0 - Capture select register for CTIMER inputs"] - #[inline(always)] - pub fn ctimer4cap_iter(&self) -> impl Iterator { - self.ctimer4cap.iter() - } - #[doc = "0x1d0 - Trigger register for TIMER4"] - #[inline(always)] - pub const fn timer4trig(&self) -> &Timer4trig { - &self.timer4trig - } - #[doc = "0x200..0x240 - AOI1 trigger input connections 0"] - #[inline(always)] - pub const fn aoi1_input(&self, n: usize) -> &Aoi1Input { - &self.aoi1_input[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x200..0x240 - AOI1 trigger input connections 0"] - #[inline(always)] - pub fn aoi1_input_iter(&self) -> impl Iterator { - self.aoi1_input.iter() - } - #[doc = "0x260 - CMP0 input connections"] - #[inline(always)] - pub const fn cmp0_trig(&self) -> &Cmp0Trig { - &self.cmp0_trig - } - #[doc = "0x280..0x290 - ADC Trigger input connections"] - #[inline(always)] - pub const fn adc0_trig(&self, n: usize) -> &Adc0Trig { - &self.adc0_trig[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x280..0x290 - ADC Trigger input connections"] - #[inline(always)] - pub fn adc0_trig_iter(&self) -> impl Iterator { - self.adc0_trig.iter() - } - #[doc = "0x2a0..0x2b0 - ADC Trigger input connections"] - #[inline(always)] - pub const fn adc2_trig(&self, n: usize) -> &Adc2Trig { - &self.adc2_trig[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x2a0..0x2b0 - ADC Trigger input connections"] - #[inline(always)] - pub fn adc2_trig_iter(&self) -> impl Iterator { - self.adc2_trig.iter() - } - #[doc = "0x2c0..0x2d0 - ADC Trigger input connections"] - #[inline(always)] - pub const fn adc1_trig(&self, n: usize) -> &Adc1Trig { - &self.adc1_trig[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x2c0..0x2d0 - ADC Trigger input connections"] - #[inline(always)] - pub fn adc1_trig_iter(&self) -> impl Iterator { - self.adc1_trig.iter() - } - #[doc = "0x2e0..0x2f0 - ADC Trigger input connections"] - #[inline(always)] - pub const fn adc3_trig(&self, n: usize) -> &Adc3Trig { - &self.adc3_trig[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x2e0..0x2f0 - ADC Trigger input connections"] - #[inline(always)] - pub fn adc3_trig_iter(&self) -> impl Iterator { - self.adc3_trig.iter() - } - #[doc = "0x300 - DAC0 Trigger input connections."] - #[inline(always)] - pub const fn dac0_trig(&self) -> &Dac0Trig { - &self.dac0_trig - } - #[doc = "0x360 - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_trig(&self) -> &Qdc0Trig { - &self.qdc0_trig - } - #[doc = "0x364 - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_home(&self) -> &Qdc0Home { - &self.qdc0_home - } - #[doc = "0x368 - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_index(&self) -> &Qdc0Index { - &self.qdc0_index - } - #[doc = "0x36c - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_phaseb(&self) -> &Qdc0Phaseb { - &self.qdc0_phaseb - } - #[doc = "0x370 - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_phasea(&self) -> &Qdc0Phasea { - &self.qdc0_phasea - } - #[doc = "0x374 - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_icap1(&self) -> &Qdc0Icap1 { - &self.qdc0_icap1 - } - #[doc = "0x378 - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_icap2(&self) -> &Qdc0Icap2 { - &self.qdc0_icap2 - } - #[doc = "0x37c - QDC0 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc0_icap3(&self) -> &Qdc0Icap3 { - &self.qdc0_icap3 - } - #[doc = "0x380 - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_trig(&self) -> &Qdc1Trig { - &self.qdc1_trig - } - #[doc = "0x384 - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_home(&self) -> &Qdc1Home { - &self.qdc1_home - } - #[doc = "0x388 - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_index(&self) -> &Qdc1Index { - &self.qdc1_index - } - #[doc = "0x38c - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_phaseb(&self) -> &Qdc1Phaseb { - &self.qdc1_phaseb - } - #[doc = "0x390 - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_phasea(&self) -> &Qdc1Phasea { - &self.qdc1_phasea - } - #[doc = "0x394 - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_icap1(&self) -> &Qdc1Icap1 { - &self.qdc1_icap1 - } - #[doc = "0x398 - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_icap2(&self) -> &Qdc1Icap2 { - &self.qdc1_icap2 - } - #[doc = "0x39c - QDC1 Trigger Input Connections"] - #[inline(always)] - pub const fn qdc1_icap3(&self) -> &Qdc1Icap3 { - &self.qdc1_icap3 - } - #[doc = "0x3a0 - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm0_exta0(&self) -> &FlexPwm0Sm0Exta0 { - &self.flex_pwm0_sm0_exta0 - } - #[doc = "0x3a4 - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm0_extsync(&self) -> &FlexPwm0Sm0Extsync { - &self.flex_pwm0_sm0_extsync - } - #[doc = "0x3a8 - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm1_exta(&self) -> &FlexPwm0Sm1Exta { - &self.flex_pwm0_sm1_exta - } - #[doc = "0x3ac - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm1_extsync(&self) -> &FlexPwm0Sm1Extsync { - &self.flex_pwm0_sm1_extsync - } - #[doc = "0x3b0 - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm2_exta(&self) -> &FlexPwm0Sm2Exta { - &self.flex_pwm0_sm2_exta - } - #[doc = "0x3b4 - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm2_extsync(&self) -> &FlexPwm0Sm2Extsync { - &self.flex_pwm0_sm2_extsync - } - #[doc = "0x3b8 - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm3_exta0(&self) -> &FlexPwm0Sm3Exta0 { - &self.flex_pwm0_sm3_exta0 - } - #[doc = "0x3bc - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_sm3_extsync(&self) -> &FlexPwm0Sm3Extsync { - &self.flex_pwm0_sm3_extsync - } - #[doc = "0x3c0..0x3d0 - PWM0 Fault Input Trigger Connections"] - #[inline(always)] - pub const fn flex_pwm0_fault(&self, n: usize) -> &FlexPwm0Fault { - &self.flex_pwm0_fault[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x3c0..0x3d0 - PWM0 Fault Input Trigger Connections"] - #[inline(always)] - pub fn flex_pwm0_fault_iter(&self) -> impl Iterator { - self.flex_pwm0_fault.iter() - } - #[doc = "0x3d0 - PWM0 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm0_force(&self) -> &FlexPwm0Force { - &self.flex_pwm0_force - } - #[doc = "0x3e0 - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm0_exta0(&self) -> &FlexPwm1Sm0Exta0 { - &self.flex_pwm1_sm0_exta0 - } - #[doc = "0x3e4 - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm0_extsync(&self) -> &FlexPwm1Sm0Extsync { - &self.flex_pwm1_sm0_extsync - } - #[doc = "0x3e8 - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm1_exta(&self) -> &FlexPwm1Sm1Exta { - &self.flex_pwm1_sm1_exta - } - #[doc = "0x3ec - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm1_extsync(&self) -> &FlexPwm1Sm1Extsync { - &self.flex_pwm1_sm1_extsync - } - #[doc = "0x3f0 - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm2_exta(&self) -> &FlexPwm1Sm2Exta { - &self.flex_pwm1_sm2_exta - } - #[doc = "0x3f4 - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm2_extsync(&self) -> &FlexPwm1Sm2Extsync { - &self.flex_pwm1_sm2_extsync - } - #[doc = "0x3f8 - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm3_exta0(&self) -> &FlexPwm1Sm3Exta0 { - &self.flex_pwm1_sm3_exta0 - } - #[doc = "0x3fc - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_sm3_extsync(&self) -> &FlexPwm1Sm3Extsync { - &self.flex_pwm1_sm3_extsync - } - #[doc = "0x400..0x410 - PWM1 Fault Input Trigger Connections"] - #[inline(always)] - pub const fn flex_pwm1_fault(&self, n: usize) -> &FlexPwm1Fault { - &self.flex_pwm1_fault[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x400..0x410 - PWM1 Fault Input Trigger Connections"] - #[inline(always)] - pub fn flex_pwm1_fault_iter(&self) -> impl Iterator { - self.flex_pwm1_fault.iter() - } - #[doc = "0x410 - PWM1 input trigger connections"] - #[inline(always)] - pub const fn flex_pwm1_force(&self) -> &FlexPwm1Force { - &self.flex_pwm1_force - } - #[doc = "0x420 - PWM0 external clock trigger"] - #[inline(always)] - pub const fn pwm0_ext_clk(&self) -> &Pwm0ExtClk { - &self.pwm0_ext_clk - } - #[doc = "0x424 - PWM1 external clock trigger"] - #[inline(always)] - pub const fn pwm1_ext_clk(&self) -> &Pwm1ExtClk { - &self.pwm1_ext_clk - } - #[doc = "0x440..0x480 - AOI0 trigger input connections 0"] - #[inline(always)] - pub const fn aoi0_input(&self, n: usize) -> &Aoi0Input { - &self.aoi0_input[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x440..0x480 - AOI0 trigger input connections 0"] - #[inline(always)] - pub fn aoi0_input_iter(&self) -> impl Iterator { - self.aoi0_input.iter() - } - #[doc = "0x480 - USB-FS trigger input connections"] - #[inline(always)] - pub const fn usbfs_trig(&self) -> &UsbfsTrig { - &self.usbfs_trig - } - #[doc = "0x4c0..0x4e0 - EXT trigger connections"] - #[inline(always)] - pub const fn ext_trig(&self, n: usize) -> &ExtTrig { - &self.ext_trig[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x4c0..0x4e0 - EXT trigger connections"] - #[inline(always)] - pub fn ext_trig_iter(&self) -> impl Iterator { - self.ext_trig.iter() - } - #[doc = "0x4e0 - CMP1 input connections"] - #[inline(always)] - pub const fn cmp1_trig(&self) -> &Cmp1Trig { - &self.cmp1_trig - } - #[doc = "0x500 - CMP2 input connections"] - #[inline(always)] - pub const fn cmp2_trig(&self) -> &Cmp2Trig { - &self.cmp2_trig - } - #[doc = "0x540 - LPI2C2 trigger input connections"] - #[inline(always)] - pub const fn lpi2c2_trig(&self) -> &Lpi2c2Trig { - &self.lpi2c2_trig - } - #[doc = "0x560 - LPI2C3 trigger input connections"] - #[inline(always)] - pub const fn lpi2c3_trig(&self) -> &Lpi2c3Trig { - &self.lpi2c3_trig - } - #[doc = "0x5a0 - LPI2C0 trigger input connections"] - #[inline(always)] - pub const fn lpi2c0_trig(&self) -> &Lpi2c0Trig { - &self.lpi2c0_trig - } - #[doc = "0x5c0 - LPI2C1 trigger input connections"] - #[inline(always)] - pub const fn lpi2c1_trig(&self) -> &Lpi2c1Trig { - &self.lpi2c1_trig - } - #[doc = "0x5e0 - LPSPI0 trigger input connections"] - #[inline(always)] - pub const fn lpspi0_trig(&self) -> &Lpspi0Trig { - &self.lpspi0_trig - } - #[doc = "0x600 - LPSPI1 trigger input connections"] - #[inline(always)] - pub const fn lpspi1_trig(&self) -> &Lpspi1Trig { - &self.lpspi1_trig - } - #[doc = "0x620 - LPUART0 trigger input connections"] - #[inline(always)] - pub const fn lpuart0(&self) -> &Lpuart0 { - &self.lpuart0 - } - #[doc = "0x640 - LPUART1 trigger input connections"] - #[inline(always)] - pub const fn lpuart1(&self) -> &Lpuart1 { - &self.lpuart1 - } - #[doc = "0x660 - LPUART2 trigger input connections"] - #[inline(always)] - pub const fn lpuart2(&self) -> &Lpuart2 { - &self.lpuart2 - } - #[doc = "0x680 - LPUART3 trigger input connections"] - #[inline(always)] - pub const fn lpuart3(&self) -> &Lpuart3 { - &self.lpuart3 - } - #[doc = "0x6a0 - LPUART4 trigger input connections"] - #[inline(always)] - pub const fn lpuart4(&self) -> &Lpuart4 { - &self.lpuart4 - } - #[doc = "0x6c0 - LPUART5 trigger input connections"] - #[inline(always)] - pub const fn lpuart5(&self) -> &Lpuart5 { - &self.lpuart5 - } - #[doc = "0x6e0..0x6f0 - FlexIO Trigger Input Connections"] - #[inline(always)] - pub const fn flexio_trig(&self, n: usize) -> &FlexioTrig { - &self.flexio_trig[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x6e0..0x6f0 - FlexIO Trigger Input Connections"] - #[inline(always)] - pub fn flexio_trig_iter(&self) -> impl Iterator { - self.flexio_trig.iter() - } - #[doc = "0xa00 - Trigger filter prescaller"] - #[inline(always)] - pub const fn trigfil_prsc(&self) -> &TrigfilPrsc { - &self.trigfil_prsc - } - #[doc = "0xa04 - Trigger filter stat"] - #[inline(always)] - pub const fn trigfil_stat0(&self) -> &TrigfilStat0 { - &self.trigfil_stat0 - } - #[doc = "0xa10..0xa40 - TRIGFIL control"] - #[inline(always)] - pub const fn trigfil(&self, n: usize) -> &Trigfil { - &self.trigfil[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0xa10..0xa40 - TRIGFIL control"] - #[inline(always)] - pub fn trigfil_iter(&self) -> impl Iterator { - self.trigfil.iter() - } -} -#[doc = "CTIMER0CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer0cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer0cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer0cap`] module"] -#[doc(alias = "CTIMER0CAP")] -pub type Ctimer0cap = crate::Reg; -#[doc = "Capture select register for CTIMER inputs"] -pub mod ctimer0cap; -#[doc = "TIMER0TRIG (rw) register accessor: Trigger register for TIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`timer0trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer0trig`] module"] -#[doc(alias = "TIMER0TRIG")] -pub type Timer0trig = crate::Reg; -#[doc = "Trigger register for TIMER0"] -pub mod timer0trig; -#[doc = "CTIMER1CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer1cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer1cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer1cap`] module"] -#[doc(alias = "CTIMER1CAP")] -pub type Ctimer1cap = crate::Reg; -#[doc = "Capture select register for CTIMER inputs"] -pub mod ctimer1cap; -#[doc = "TIMER1TRIG (rw) register accessor: Trigger register for TIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1trig`] module"] -#[doc(alias = "TIMER1TRIG")] -pub type Timer1trig = crate::Reg; -#[doc = "Trigger register for TIMER1"] -pub mod timer1trig; -#[doc = "CTIMER2CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer2cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer2cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer2cap`] module"] -#[doc(alias = "CTIMER2CAP")] -pub type Ctimer2cap = crate::Reg; -#[doc = "Capture select register for CTIMER inputs"] -pub mod ctimer2cap; -#[doc = "TIMER2TRIG (rw) register accessor: Trigger register for TIMER2 inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2trig`] module"] -#[doc(alias = "TIMER2TRIG")] -pub type Timer2trig = crate::Reg; -#[doc = "Trigger register for TIMER2 inputs"] -pub mod timer2trig; -#[doc = "SmartDMA_TRIG (rw) register accessor: SmartDMA Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dma_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dma_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smart_dma_trig`] module"] -#[doc(alias = "SmartDMA_TRIG")] -pub type SmartDmaTrig = crate::Reg; -#[doc = "SmartDMA Trigger Input Connections"] -pub mod smart_dma_trig; -#[doc = "FREQMEAS_REF (rw) register accessor: Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_ref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_ref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@freqmeas_ref`] module"] -#[doc(alias = "FREQMEAS_REF")] -pub type FreqmeasRef = crate::Reg; -#[doc = "Selection for frequency measurement reference clock"] -pub mod freqmeas_ref; -#[doc = "FREQMEAS_TAR (rw) register accessor: Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@freqmeas_tar`] module"] -#[doc(alias = "FREQMEAS_TAR")] -pub type FreqmeasTar = crate::Reg; -#[doc = "Selection for frequency measurement reference clock"] -pub mod freqmeas_tar; -#[doc = "CTIMER3CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer3cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer3cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer3cap`] module"] -#[doc(alias = "CTIMER3CAP")] -pub type Ctimer3cap = crate::Reg; -#[doc = "Capture select register for CTIMER inputs"] -pub mod ctimer3cap; -#[doc = "TIMER3TRIG (rw) register accessor: Trigger register for TIMER3\n\nYou can [`read`](crate::Reg::read) this register and get [`timer3trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer3trig`] module"] -#[doc(alias = "TIMER3TRIG")] -pub type Timer3trig = crate::Reg; -#[doc = "Trigger register for TIMER3"] -pub mod timer3trig; -#[doc = "CTIMER4CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer4cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer4cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer4cap`] module"] -#[doc(alias = "CTIMER4CAP")] -pub type Ctimer4cap = crate::Reg; -#[doc = "Capture select register for CTIMER inputs"] -pub mod ctimer4cap; -#[doc = "TIMER4TRIG (rw) register accessor: Trigger register for TIMER4\n\nYou can [`read`](crate::Reg::read) this register and get [`timer4trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer4trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer4trig`] module"] -#[doc(alias = "TIMER4TRIG")] -pub type Timer4trig = crate::Reg; -#[doc = "Trigger register for TIMER4"] -pub mod timer4trig; -#[doc = "AOI1_INPUT (rw) register accessor: AOI1 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoi1_input`] module"] -#[doc(alias = "AOI1_INPUT")] -pub type Aoi1Input = crate::Reg; -#[doc = "AOI1 trigger input connections 0"] -pub mod aoi1_input; -#[doc = "CMP0_TRIG (rw) register accessor: CMP0 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp0_trig`] module"] -#[doc(alias = "CMP0_TRIG")] -pub type Cmp0Trig = crate::Reg; -#[doc = "CMP0 input connections"] -pub mod cmp0_trig; -#[doc = "ADC0_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc0_trig`] module"] -#[doc(alias = "ADC0_TRIG")] -pub type Adc0Trig = crate::Reg; -#[doc = "ADC Trigger input connections"] -pub mod adc0_trig; -#[doc = "ADC2_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc2_trig`] module"] -#[doc(alias = "ADC2_TRIG")] -pub type Adc2Trig = crate::Reg; -#[doc = "ADC Trigger input connections"] -pub mod adc2_trig; -#[doc = "ADC1_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc1_trig`] module"] -#[doc(alias = "ADC1_TRIG")] -pub type Adc1Trig = crate::Reg; -#[doc = "ADC Trigger input connections"] -pub mod adc1_trig; -#[doc = "ADC3_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc3_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc3_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc3_trig`] module"] -#[doc(alias = "ADC3_TRIG")] -pub type Adc3Trig = crate::Reg; -#[doc = "ADC Trigger input connections"] -pub mod adc3_trig; -#[doc = "DAC0_TRIG (rw) register accessor: DAC0 Trigger input connections.\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dac0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac0_trig`] module"] -#[doc(alias = "DAC0_TRIG")] -pub type Dac0Trig = crate::Reg; -#[doc = "DAC0 Trigger input connections."] -pub mod dac0_trig; -#[doc = "QDC0_TRIG (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_trig`] module"] -#[doc(alias = "QDC0_TRIG")] -pub type Qdc0Trig = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_trig; -#[doc = "QDC0_HOME (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_home::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_home::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_home`] module"] -#[doc(alias = "QDC0_HOME")] -pub type Qdc0Home = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_home; -#[doc = "QDC0_INDEX (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_index`] module"] -#[doc(alias = "QDC0_INDEX")] -pub type Qdc0Index = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_index; -#[doc = "QDC0_PHASEB (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phaseb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phaseb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_phaseb`] module"] -#[doc(alias = "QDC0_PHASEB")] -pub type Qdc0Phaseb = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_phaseb; -#[doc = "QDC0_PHASEA (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phasea::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phasea::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_phasea`] module"] -#[doc(alias = "QDC0_PHASEA")] -pub type Qdc0Phasea = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_phasea; -#[doc = "QDC0_ICAP1 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap1`] module"] -#[doc(alias = "QDC0_ICAP1")] -pub type Qdc0Icap1 = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_icap1; -#[doc = "QDC0_ICAP2 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap2`] module"] -#[doc(alias = "QDC0_ICAP2")] -pub type Qdc0Icap2 = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_icap2; -#[doc = "QDC0_ICAP3 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap3`] module"] -#[doc(alias = "QDC0_ICAP3")] -pub type Qdc0Icap3 = crate::Reg; -#[doc = "QDC0 Trigger Input Connections"] -pub mod qdc0_icap3; -#[doc = "QDC1_TRIG (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_trig`] module"] -#[doc(alias = "QDC1_TRIG")] -pub type Qdc1Trig = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_trig; -#[doc = "QDC1_HOME (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_home::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_home::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_home`] module"] -#[doc(alias = "QDC1_HOME")] -pub type Qdc1Home = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_home; -#[doc = "QDC1_INDEX (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_index`] module"] -#[doc(alias = "QDC1_INDEX")] -pub type Qdc1Index = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_index; -#[doc = "QDC1_PHASEB (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phaseb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phaseb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_phaseb`] module"] -#[doc(alias = "QDC1_PHASEB")] -pub type Qdc1Phaseb = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_phaseb; -#[doc = "QDC1_PHASEA (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phasea::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phasea::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_phasea`] module"] -#[doc(alias = "QDC1_PHASEA")] -pub type Qdc1Phasea = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_phasea; -#[doc = "QDC1_ICAP1 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap1`] module"] -#[doc(alias = "QDC1_ICAP1")] -pub type Qdc1Icap1 = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_icap1; -#[doc = "QDC1_ICAP2 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap2`] module"] -#[doc(alias = "QDC1_ICAP2")] -pub type Qdc1Icap2 = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_icap2; -#[doc = "QDC1_ICAP3 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap3`] module"] -#[doc(alias = "QDC1_ICAP3")] -pub type Qdc1Icap3 = crate::Reg; -#[doc = "QDC1 Trigger Input Connections"] -pub mod qdc1_icap3; -#[doc = "FlexPWM0_SM0_EXTA0 (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm0_exta0`] module"] -#[doc(alias = "FlexPWM0_SM0_EXTA0")] -pub type FlexPwm0Sm0Exta0 = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm0_exta0; -#[doc = "FlexPWM0_SM0_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm0_extsync`] module"] -#[doc(alias = "FlexPWM0_SM0_EXTSYNC")] -pub type FlexPwm0Sm0Extsync = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm0_extsync; -#[doc = "FlexPWM0_SM1_EXTA (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm1_exta`] module"] -#[doc(alias = "FlexPWM0_SM1_EXTA")] -pub type FlexPwm0Sm1Exta = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm1_exta; -#[doc = "FlexPWM0_SM1_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm1_extsync`] module"] -#[doc(alias = "FlexPWM0_SM1_EXTSYNC")] -pub type FlexPwm0Sm1Extsync = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm1_extsync; -#[doc = "FlexPWM0_SM2_EXTA (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm2_exta`] module"] -#[doc(alias = "FlexPWM0_SM2_EXTA")] -pub type FlexPwm0Sm2Exta = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm2_exta; -#[doc = "FlexPWM0_SM2_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm2_extsync`] module"] -#[doc(alias = "FlexPWM0_SM2_EXTSYNC")] -pub type FlexPwm0Sm2Extsync = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm2_extsync; -#[doc = "FlexPWM0_SM3_EXTA0 (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm3_exta0`] module"] -#[doc(alias = "FlexPWM0_SM3_EXTA0")] -pub type FlexPwm0Sm3Exta0 = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm3_exta0; -#[doc = "FlexPWM0_SM3_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm3_extsync`] module"] -#[doc(alias = "FlexPWM0_SM3_EXTSYNC")] -pub type FlexPwm0Sm3Extsync = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_sm3_extsync; -#[doc = "FlexPWM0_FAULT (rw) register accessor: PWM0 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_fault::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_fault::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_fault`] module"] -#[doc(alias = "FlexPWM0_FAULT")] -pub type FlexPwm0Fault = crate::Reg; -#[doc = "PWM0 Fault Input Trigger Connections"] -pub mod flex_pwm0_fault; -#[doc = "FlexPWM0_FORCE (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_force`] module"] -#[doc(alias = "FlexPWM0_FORCE")] -pub type FlexPwm0Force = crate::Reg; -#[doc = "PWM0 input trigger connections"] -pub mod flex_pwm0_force; -#[doc = "FlexPWM1_SM0_EXTA0 (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm0_exta0`] module"] -#[doc(alias = "FlexPWM1_SM0_EXTA0")] -pub type FlexPwm1Sm0Exta0 = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm0_exta0; -#[doc = "FlexPWM1_SM0_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm0_extsync`] module"] -#[doc(alias = "FlexPWM1_SM0_EXTSYNC")] -pub type FlexPwm1Sm0Extsync = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm0_extsync; -#[doc = "FlexPWM1_SM1_EXTA (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm1_exta`] module"] -#[doc(alias = "FlexPWM1_SM1_EXTA")] -pub type FlexPwm1Sm1Exta = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm1_exta; -#[doc = "FlexPWM1_SM1_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm1_extsync`] module"] -#[doc(alias = "FlexPWM1_SM1_EXTSYNC")] -pub type FlexPwm1Sm1Extsync = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm1_extsync; -#[doc = "FlexPWM1_SM2_EXTA (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm2_exta`] module"] -#[doc(alias = "FlexPWM1_SM2_EXTA")] -pub type FlexPwm1Sm2Exta = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm2_exta; -#[doc = "FlexPWM1_SM2_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm2_extsync`] module"] -#[doc(alias = "FlexPWM1_SM2_EXTSYNC")] -pub type FlexPwm1Sm2Extsync = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm2_extsync; -#[doc = "FlexPWM1_SM3_EXTA0 (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm3_exta0`] module"] -#[doc(alias = "FlexPWM1_SM3_EXTA0")] -pub type FlexPwm1Sm3Exta0 = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm3_exta0; -#[doc = "FlexPWM1_SM3_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm3_extsync`] module"] -#[doc(alias = "FlexPWM1_SM3_EXTSYNC")] -pub type FlexPwm1Sm3Extsync = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_sm3_extsync; -#[doc = "FlexPWM1_FAULT (rw) register accessor: PWM1 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_fault::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_fault::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_fault`] module"] -#[doc(alias = "FlexPWM1_FAULT")] -pub type FlexPwm1Fault = crate::Reg; -#[doc = "PWM1 Fault Input Trigger Connections"] -pub mod flex_pwm1_fault; -#[doc = "FlexPWM1_FORCE (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_force`] module"] -#[doc(alias = "FlexPWM1_FORCE")] -pub type FlexPwm1Force = crate::Reg; -#[doc = "PWM1 input trigger connections"] -pub mod flex_pwm1_force; -#[doc = "PWM0_EXT_CLK (rw) register accessor: PWM0 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0_ext_clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0_ext_clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0_ext_clk`] module"] -#[doc(alias = "PWM0_EXT_CLK")] -pub type Pwm0ExtClk = crate::Reg; -#[doc = "PWM0 external clock trigger"] -pub mod pwm0_ext_clk; -#[doc = "PWM1_EXT_CLK (rw) register accessor: PWM1 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1_ext_clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1_ext_clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1_ext_clk`] module"] -#[doc(alias = "PWM1_EXT_CLK")] -pub type Pwm1ExtClk = crate::Reg; -#[doc = "PWM1 external clock trigger"] -pub mod pwm1_ext_clk; -#[doc = "AOI0_INPUT (rw) register accessor: AOI0 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi0_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi0_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoi0_input`] module"] -#[doc(alias = "AOI0_INPUT")] -pub type Aoi0Input = crate::Reg; -#[doc = "AOI0 trigger input connections 0"] -pub mod aoi0_input; -#[doc = "USBFS_TRIG (rw) register accessor: USB-FS trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfs_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfs_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbfs_trig`] module"] -#[doc(alias = "USBFS_TRIG")] -pub type UsbfsTrig = crate::Reg; -#[doc = "USB-FS trigger input connections"] -pub mod usbfs_trig; -#[doc = "EXT_TRIG (rw) register accessor: EXT trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_trig`] module"] -#[doc(alias = "EXT_TRIG")] -pub type ExtTrig = crate::Reg; -#[doc = "EXT trigger connections"] -pub mod ext_trig; -#[doc = "CMP1_TRIG (rw) register accessor: CMP1 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp1_trig`] module"] -#[doc(alias = "CMP1_TRIG")] -pub type Cmp1Trig = crate::Reg; -#[doc = "CMP1 input connections"] -pub mod cmp1_trig; -#[doc = "CMP2_TRIG (rw) register accessor: CMP2 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp2_trig`] module"] -#[doc(alias = "CMP2_TRIG")] -pub type Cmp2Trig = crate::Reg; -#[doc = "CMP2 input connections"] -pub mod cmp2_trig; -#[doc = "LPI2C2_TRIG (rw) register accessor: LPI2C2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c2_trig`] module"] -#[doc(alias = "LPI2C2_TRIG")] -pub type Lpi2c2Trig = crate::Reg; -#[doc = "LPI2C2 trigger input connections"] -pub mod lpi2c2_trig; -#[doc = "LPI2C3_TRIG (rw) register accessor: LPI2C3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c3_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c3_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c3_trig`] module"] -#[doc(alias = "LPI2C3_TRIG")] -pub type Lpi2c3Trig = crate::Reg; -#[doc = "LPI2C3 trigger input connections"] -pub mod lpi2c3_trig; -#[doc = "LPI2C0_TRIG (rw) register accessor: LPI2C0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c0_trig`] module"] -#[doc(alias = "LPI2C0_TRIG")] -pub type Lpi2c0Trig = crate::Reg; -#[doc = "LPI2C0 trigger input connections"] -pub mod lpi2c0_trig; -#[doc = "LPI2C1_TRIG (rw) register accessor: LPI2C1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c1_trig`] module"] -#[doc(alias = "LPI2C1_TRIG")] -pub type Lpi2c1Trig = crate::Reg; -#[doc = "LPI2C1 trigger input connections"] -pub mod lpi2c1_trig; -#[doc = "LPSPI0_TRIG (rw) register accessor: LPSPI0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpspi0_trig`] module"] -#[doc(alias = "LPSPI0_TRIG")] -pub type Lpspi0Trig = crate::Reg; -#[doc = "LPSPI0 trigger input connections"] -pub mod lpspi0_trig; -#[doc = "LPSPI1_TRIG (rw) register accessor: LPSPI1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpspi1_trig`] module"] -#[doc(alias = "LPSPI1_TRIG")] -pub type Lpspi1Trig = crate::Reg; -#[doc = "LPSPI1 trigger input connections"] -pub mod lpspi1_trig; -#[doc = "LPUART0 (rw) register accessor: LPUART0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart0`] module"] -#[doc(alias = "LPUART0")] -pub type Lpuart0 = crate::Reg; -#[doc = "LPUART0 trigger input connections"] -pub mod lpuart0; -#[doc = "LPUART1 (rw) register accessor: LPUART1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart1`] module"] -#[doc(alias = "LPUART1")] -pub type Lpuart1 = crate::Reg; -#[doc = "LPUART1 trigger input connections"] -pub mod lpuart1; -#[doc = "LPUART2 (rw) register accessor: LPUART2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart2`] module"] -#[doc(alias = "LPUART2")] -pub type Lpuart2 = crate::Reg; -#[doc = "LPUART2 trigger input connections"] -pub mod lpuart2; -#[doc = "LPUART3 (rw) register accessor: LPUART3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart3`] module"] -#[doc(alias = "LPUART3")] -pub type Lpuart3 = crate::Reg; -#[doc = "LPUART3 trigger input connections"] -pub mod lpuart3; -#[doc = "LPUART4 (rw) register accessor: LPUART4 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart4`] module"] -#[doc(alias = "LPUART4")] -pub type Lpuart4 = crate::Reg; -#[doc = "LPUART4 trigger input connections"] -pub mod lpuart4; -#[doc = "LPUART5 (rw) register accessor: LPUART5 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart5`] module"] -#[doc(alias = "LPUART5")] -pub type Lpuart5 = crate::Reg; -#[doc = "LPUART5 trigger input connections"] -pub mod lpuart5; -#[doc = "FLEXIO_TRIG (rw) register accessor: FlexIO Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flexio_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexio_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexio_trig`] module"] -#[doc(alias = "FLEXIO_TRIG")] -pub type FlexioTrig = crate::Reg; -#[doc = "FlexIO Trigger Input Connections"] -pub mod flexio_trig; -#[doc = "TRIGFIL_PRSC (rw) register accessor: Trigger filter prescaller\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_prsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil_prsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil_prsc`] module"] -#[doc(alias = "TRIGFIL_PRSC")] -pub type TrigfilPrsc = crate::Reg; -#[doc = "Trigger filter prescaller"] -pub mod trigfil_prsc; -#[doc = "TRIGFIL_STAT0 (r) register accessor: Trigger filter stat\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_stat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil_stat0`] module"] -#[doc(alias = "TRIGFIL_STAT0")] -pub type TrigfilStat0 = crate::Reg; -#[doc = "Trigger filter stat"] -pub mod trigfil_stat0; -#[doc = "TRIGFIL (rw) register accessor: TRIGFIL control\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil`] module"] -#[doc(alias = "TRIGFIL")] -pub type Trigfil = crate::Reg; -#[doc = "TRIGFIL control"] -pub mod trigfil; diff --git a/mcxa276-pac/src/inputmux0/adc0_trig.rs b/mcxa276-pac/src/inputmux0/adc0_trig.rs deleted file mode 100644 index c306806ee..000000000 --- a/mcxa276-pac/src/inputmux0/adc0_trig.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `ADC0_TRIG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `ADC0_TRIG[%s]` writer"] -pub type W = crate::W; -#[doc = "ADC0 trigger inputs\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: QDC0_POS_MATCH0 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] - Val24 = 24, - #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] - Val25 = 25, - #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: WUU"] - Val31 = 31, - #[doc = "33: AOI1_OUT0 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT1 input is selected"] - Val34 = 34, - #[doc = "35: AOI1_OUT2 input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT3 input is selected"] - Val36 = 36, - #[doc = "37: ADC1_tcomp\\[0\\] input is selected"] - Val37 = 37, - #[doc = "38: ADC1_tcomp\\[1\\] input is selected"] - Val38 = 38, - #[doc = "39: ADC1_tcomp\\[2\\] input is selected"] - Val39 = 39, - #[doc = "40: ADC1_tcomp\\[3\\] input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer3_MAT1 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT0 input is selected"] - Val43 = 43, - #[doc = "44: CTimer4_MAT1 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH0 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH1 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH2 input is selected"] - Val47 = 47, - #[doc = "48: FlexIO CH3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_POS_MATCH0 input is selected"] - Val49 = 49, - #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] - Val57 = 57, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - ADC0 trigger inputs"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 43 => Some(Trigin::Val43), - 44 => Some(Trigin::Val44), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "WUU"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Trigin::Val43 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Trigin::Val44 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } -} -#[doc = "Field `TRIGIN` writer - ADC0 trigger inputs"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "WUU"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Trigin::Val43) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Trigin::Val44) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } -} -impl R { - #[doc = "Bits 0:5 - ADC0 trigger inputs"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - ADC0 trigger inputs"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Adc0TrigSpec; -impl crate::RegisterSpec for Adc0TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`adc0_trig::R`](R) reader structure"] -impl crate::Readable for Adc0TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`adc0_trig::W`](W) writer structure"] -impl crate::Writable for Adc0TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADC0_TRIG[%s] to value 0x3f"] -impl crate::Resettable for Adc0TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/adc1_trig.rs b/mcxa276-pac/src/inputmux0/adc1_trig.rs deleted file mode 100644 index ca42768f9..000000000 --- a/mcxa276-pac/src/inputmux0/adc1_trig.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `ADC1_TRIG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `ADC1_TRIG[%s]` writer"] -pub type W = crate::W; -#[doc = "ADC1 trigger inputs\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: QDC0_POS_MATCH0 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] - Val24 = 24, - #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] - Val25 = 25, - #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: WUU"] - Val31 = 31, - #[doc = "33: AOI1_OUT0 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT1 input is selected"] - Val34 = 34, - #[doc = "35: AOI1_OUT2 input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT3 input is selected"] - Val36 = 36, - #[doc = "37: ADC0_tcomp\\[0\\] input is selected"] - Val37 = 37, - #[doc = "38: ADC0_tcomp\\[1\\] input is selected"] - Val38 = 38, - #[doc = "39: ADC0_tcomp\\[2\\] input is selected"] - Val39 = 39, - #[doc = "40: ADC0_tcomp\\[3\\] input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer3_MAT1 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT0 input is selected"] - Val43 = 43, - #[doc = "44: CTimer4_MAT1 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH0 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH1 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH2 input is selected"] - Val47 = 47, - #[doc = "48: FlexIO CH3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_POS_MATCH0 input is selected"] - Val49 = 49, - #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] - Val57 = 57, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - ADC1 trigger inputs"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 43 => Some(Trigin::Val43), - 44 => Some(Trigin::Val44), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "WUU"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Trigin::Val43 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Trigin::Val44 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } -} -#[doc = "Field `TRIGIN` writer - ADC1 trigger inputs"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "WUU"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Trigin::Val43) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Trigin::Val44) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } -} -impl R { - #[doc = "Bits 0:5 - ADC1 trigger inputs"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - ADC1 trigger inputs"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Adc1TrigSpec; -impl crate::RegisterSpec for Adc1TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`adc1_trig::R`](R) reader structure"] -impl crate::Readable for Adc1TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`adc1_trig::W`](W) writer structure"] -impl crate::Writable for Adc1TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADC1_TRIG[%s] to value 0x3f"] -impl crate::Resettable for Adc1TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/adc2_trig.rs b/mcxa276-pac/src/inputmux0/adc2_trig.rs deleted file mode 100644 index d49743efa..000000000 --- a/mcxa276-pac/src/inputmux0/adc2_trig.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `ADC2_TRIG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `ADC2_TRIG[%s]` writer"] -pub type W = crate::W; -#[doc = "ADC2 trigger inputs\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: QDC0_POS_MATCH0 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] - Val24 = 24, - #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] - Val25 = 25, - #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: WUU"] - Val31 = 31, - #[doc = "33: AOI1_OUT0 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT1 input is selected"] - Val34 = 34, - #[doc = "35: AOI1_OUT2 input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT3 input is selected"] - Val36 = 36, - #[doc = "37: ADC3_tcomp\\[0\\] input is selected"] - Val37 = 37, - #[doc = "38: ADC3_tcomp\\[1\\] input is selected"] - Val38 = 38, - #[doc = "39: ADC3_tcomp\\[2\\] input is selected"] - Val39 = 39, - #[doc = "40: ADC3_tcomp\\[3\\] input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer3_MAT1 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT0 input is selected"] - Val43 = 43, - #[doc = "44: CTimer4_MAT1 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH0 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH1 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH2 input is selected"] - Val47 = 47, - #[doc = "48: FlexIO CH3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_POS_MATCH0 input is selected"] - Val49 = 49, - #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] - Val57 = 57, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - ADC2 trigger inputs"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 43 => Some(Trigin::Val43), - 44 => Some(Trigin::Val44), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "WUU"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Trigin::Val43 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Trigin::Val44 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } -} -#[doc = "Field `TRIGIN` writer - ADC2 trigger inputs"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "WUU"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Trigin::Val43) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Trigin::Val44) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } -} -impl R { - #[doc = "Bits 0:5 - ADC2 trigger inputs"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - ADC2 trigger inputs"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc2_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc2_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Adc2TrigSpec; -impl crate::RegisterSpec for Adc2TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`adc2_trig::R`](R) reader structure"] -impl crate::Readable for Adc2TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`adc2_trig::W`](W) writer structure"] -impl crate::Writable for Adc2TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADC2_TRIG[%s] to value 0x3f"] -impl crate::Resettable for Adc2TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/adc3_trig.rs b/mcxa276-pac/src/inputmux0/adc3_trig.rs deleted file mode 100644 index e2fb33988..000000000 --- a/mcxa276-pac/src/inputmux0/adc3_trig.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `ADC3_TRIG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `ADC3_TRIG[%s]` writer"] -pub type W = crate::W; -#[doc = "ADC3 trigger inputs\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: QDC0_POS_MATCH0 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM0_OUT_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM0_OUT_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_OUT_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM1_OUT_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_OUT_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM2_OUT_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: PWM0_SM3_OUT_TRIG0 input is selected"] - Val24 = 24, - #[doc = "25: PWM0_SM3_OUT_TRIG1 input is selected"] - Val25 = 25, - #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: WUU"] - Val31 = 31, - #[doc = "33: AOI1_OUT0 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT1 input is selected"] - Val34 = 34, - #[doc = "35: AOI1_OUT2 input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT3 input is selected"] - Val36 = 36, - #[doc = "37: ADC2_tcomp\\[0\\] input is selected"] - Val37 = 37, - #[doc = "38: ADC2_tcomp\\[1\\] input is selected"] - Val38 = 38, - #[doc = "39: ADC2_tcomp\\[2\\] input is selected"] - Val39 = 39, - #[doc = "40: ADC2_tcomp\\[3\\] input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer3_MAT1 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT0 input is selected"] - Val43 = 43, - #[doc = "44: CTimer4_MAT1 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH0 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH1 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH2 input is selected"] - Val47 = 47, - #[doc = "48: FlexIO CH3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_POS_MATCH0 input is selected"] - Val49 = 49, - #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM2_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM3_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM3_MUX_TRIG1 input is selected"] - Val57 = 57, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - ADC3 trigger inputs"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 43 => Some(Trigin::Val43), - 44 => Some(Trigin::Val44), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "WUU"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Trigin::Val43 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Trigin::Val44 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } -} -#[doc = "Field `TRIGIN` writer - ADC3 trigger inputs"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "WUU"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Trigin::Val43) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Trigin::Val44) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } -} -impl R { - #[doc = "Bits 0:5 - ADC3 trigger inputs"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - ADC3 trigger inputs"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc3_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc3_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Adc3TrigSpec; -impl crate::RegisterSpec for Adc3TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`adc3_trig::R`](R) reader structure"] -impl crate::Readable for Adc3TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`adc3_trig::W`](W) writer structure"] -impl crate::Writable for Adc3TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADC3_TRIG[%s] to value 0x3f"] -impl crate::Resettable for Adc3TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/aoi0_input.rs b/mcxa276-pac/src/inputmux0/aoi0_input.rs deleted file mode 100644 index 7eb6d0d35..000000000 --- a/mcxa276-pac/src/inputmux0/aoi0_input.rs +++ /dev/null @@ -1,1302 +0,0 @@ -#[doc = "Register `AOI0_INPUT[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `AOI0_INPUT[%s]` writer"] -pub type W = crate::W; -#[doc = "AOI0 trigger input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ADC0_tcomp\\[0\\] input is selected"] - Val1 = 1, - #[doc = "2: ADC0_tcomp\\[1\\] input is selected"] - Val2 = 2, - #[doc = "3: ADC0_tcomp\\[2\\] input is selected"] - Val3 = 3, - #[doc = "4: ADC0_tcomp\\[3\\] input is selected"] - Val4 = 4, - #[doc = "5: CMP0_OUT input is selected"] - Val5 = 5, - #[doc = "6: CMP1_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP2_OUT input is selected"] - Val7 = 7, - #[doc = "8: CTimer0_MAT0 input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT1 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT2 input is selected"] - Val10 = 10, - #[doc = "11: CTimer0_MAT3 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT0 input is selected"] - Val12 = 12, - #[doc = "13: CTimer1_MAT1 input is selected"] - Val13 = 13, - #[doc = "14: CTimer1_MAT2 input is selected"] - Val14 = 14, - #[doc = "15: CTimer1_MAT3 input is selected"] - Val15 = 15, - #[doc = "16: CTimer2_MAT0 input is selected"] - Val16 = 16, - #[doc = "17: CTimer2_MAT1 input is selected"] - Val17 = 17, - #[doc = "18: CTimer2_MAT2 input is selected"] - Val18 = 18, - #[doc = "19: CTimer2_MAT3 input is selected"] - Val19 = 19, - #[doc = "20: LPTMR0 input is selected"] - Val20 = 20, - #[doc = "22: QDC0_CMP_FLAG0 input is selected"] - Val22 = 22, - #[doc = "23: QDC0_CMP_FLAG1 input is selected"] - Val23 = 23, - #[doc = "24: QDC0_CMP_FLAG2 input is selected"] - Val24 = 24, - #[doc = "25: QDC0_CMP_FLAG3 input is selected"] - Val25 = 25, - #[doc = "26: QDC0_POS_MATCH0 input is selected"] - Val26 = 26, - #[doc = "27: PWM0_SM0_MUX_TRIG0 0 input is selected"] - Val27 = 27, - #[doc = "28: PWM0_SM0_MUX_TRIG1 input is selected"] - Val28 = 28, - #[doc = "29: PWM0_SM1_MUX_TRIG0 input is selected"] - Val29 = 29, - #[doc = "30: PWM0_SM1_MUX_TRIG1 input is selected"] - Val30 = 30, - #[doc = "31: PWM0_SM2_MUX_TRIG0 input is selected"] - Val31 = 31, - #[doc = "32: PWM0_SM2_MUX_TRIG1 input is selected"] - Val32 = 32, - #[doc = "33: PWM0_SM3_MUX_TRIG0 input is selected"] - Val33 = 33, - #[doc = "34: PWM0_SM3_MUX_TRIG1 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN0 input is selected"] - Val35 = 35, - #[doc = "36: TRIG_IN1 input is selected"] - Val36 = 36, - #[doc = "37: TRIG_IN2 input is selected"] - Val37 = 37, - #[doc = "38: TRIG_IN3 input is selected"] - Val38 = 38, - #[doc = "39: TRIG_IN4 input is selected"] - Val39 = 39, - #[doc = "40: TRIG_IN5 input is selected"] - Val40 = 40, - #[doc = "41: TRIG_IN6 input is selected"] - Val41 = 41, - #[doc = "42: TRIG_IN7 input is selected"] - Val42 = 42, - #[doc = "43: TRIG_IN8 input is selected"] - Val43 = 43, - #[doc = "44: TRIG_IN9 input is selected"] - Val44 = 44, - #[doc = "45: TRIG_IN10 input is selected"] - Val45 = 45, - #[doc = "46: TRIG_IN11 input is selected"] - Val46 = 46, - #[doc = "47: GPIO0 Pin Event Trig 0 input is selected"] - Val47 = 47, - #[doc = "48: GPIO1 Pin Event Trig 0 input is selected"] - Val48 = 48, - #[doc = "49: GPIO2 Pin Event Trig 0 input is selected"] - Val49 = 49, - #[doc = "50: GPIO3 Pin Event Trig 0 input is selected"] - Val50 = 50, - #[doc = "51: GPIO4 Pin Event Trig 0 input is selected"] - Val51 = 51, - #[doc = "52: ADC1_tcomp\\[0\\] input is selected"] - Val52 = 52, - #[doc = "53: ADC1_tcomp\\[1\\] input is selected"] - Val53 = 53, - #[doc = "54: ADC1_tcomp\\[2\\] input is selected"] - Val54 = 54, - #[doc = "55: ADC1_tcomp\\[3\\] input is selected"] - Val55 = 55, - #[doc = "56: CTimer3_MAT0 input is selected"] - Val56 = 56, - #[doc = "57: CTimer3_MAT1 input is selected"] - Val57 = 57, - #[doc = "58: CTimer3_MAT2 input is selected"] - Val58 = 58, - #[doc = "59: CTimer3_MAT3 input is selected"] - Val59 = 59, - #[doc = "60: CTimer4_MAT0 input is selected"] - Val60 = 60, - #[doc = "61: CTimer4_MAT1 input is selected"] - Val61 = 61, - #[doc = "62: CTimer4_MAT2 input is selected"] - Val62 = 62, - #[doc = "63: CTimer4_MAT3 input is selected"] - Val63 = 63, - #[doc = "64: FlexIO CH0 input is selected"] - Val64 = 64, - #[doc = "65: FlexIO CH1 input is selected"] - Val65 = 65, - #[doc = "66: FlexIO CH2 input is selected"] - Val66 = 66, - #[doc = "67: FlexIO CH3 input is selected"] - Val67 = 67, - #[doc = "68: QDC1_CMP_FLAG0 input is selected"] - Val68 = 68, - #[doc = "69: QDC1_CMP_FLAG1 input is selected"] - Val69 = 69, - #[doc = "70: QDC1_CMP_FLAG2 input is selected"] - Val70 = 70, - #[doc = "71: QDC1_CMP_FLAG3 input is selected"] - Val71 = 71, - #[doc = "72: QDC1_POS_MATCH0 input is selected"] - Val72 = 72, - #[doc = "73: PWM1_SM0_MUX_TRIG0 input is selected"] - Val73 = 73, - #[doc = "74: PWM1_SM0_MUX_TRIG1 input is selected"] - Val74 = 74, - #[doc = "75: PWM1_SM1_MUX_TRIG0 input is selected"] - Val75 = 75, - #[doc = "76: PWM1_SM1_MUX_TRIG1 input is selected"] - Val76 = 76, - #[doc = "77: PWM1_SM2_MUX_TRIG0 input is selected"] - Val77 = 77, - #[doc = "78: PWM1_SM2_MUX_TRIG1 input is selected"] - Val78 = 78, - #[doc = "79: PWM1_SM3_MUX_TRIG0 input is selected"] - Val79 = 79, - #[doc = "80: PWM1_SM3_MUX_TRIG1 input is selected"] - Val80 = 80, - #[doc = "81: PWM0_SM0_A_Output"] - Val81 = 81, - #[doc = "82: PWM0_SM0_B_Output"] - Val82 = 82, - #[doc = "83: PWM0_SM1_A_Output"] - Val83 = 83, - #[doc = "84: PWM0_SM1_B_Output"] - Val84 = 84, - #[doc = "85: PWM0_SM2_A_Output"] - Val85 = 85, - #[doc = "86: PWM0_SM2_B_Output"] - Val86 = 86, - #[doc = "87: PWM0_SM3_A_Output"] - Val87 = 87, - #[doc = "88: PWM0_SM3_B_Output"] - Val88 = 88, - #[doc = "89: ADC2_tcomp\\[0\\] input is selected"] - Val89 = 89, - #[doc = "90: ADC2_tcomp\\[1\\] input is selected"] - Val90 = 90, - #[doc = "91: ADC2_tcomp\\[2\\] input is selected"] - Val91 = 91, - #[doc = "92: ADC2_tcomp\\[3\\] input is selected"] - Val92 = 92, - #[doc = "93: ADC3_tcomp\\[0\\] input is selected"] - Val93 = 93, - #[doc = "94: ADC3_tcomp\\[1\\] input is selected"] - Val94 = 94, - #[doc = "95: ADC3_tcomp\\[2\\] input is selected"] - Val95 = 95, - #[doc = "96: ADC3_tcomp\\[3\\] input is selected"] - Val96 = 96, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - AOI0 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - _ => None, - } - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "PWM0_SM0_MUX_TRIG0 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "PWM0_SM0_A_Output"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "PWM0_SM0_B_Output"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "PWM0_SM1_A_Output"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "PWM0_SM1_B_Output"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "PWM0_SM2_A_Output"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "PWM0_SM2_B_Output"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "PWM0_SM3_A_Output"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "PWM0_SM3_B_Output"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } -} -#[doc = "Field `INP` writer - AOI0 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "PWM0_SM0_MUX_TRIG0 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "PWM0_SM0_A_Output"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "PWM0_SM0_B_Output"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "PWM0_SM1_A_Output"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "PWM0_SM1_B_Output"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "PWM0_SM2_A_Output"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "PWM0_SM2_B_Output"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "PWM0_SM3_A_Output"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "PWM0_SM3_B_Output"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } -} -impl R { - #[doc = "Bits 0:6 - AOI0 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - AOI0 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "AOI0 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi0_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi0_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Aoi0InputSpec; -impl crate::RegisterSpec for Aoi0InputSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`aoi0_input::R`](R) reader structure"] -impl crate::Readable for Aoi0InputSpec {} -#[doc = "`write(|w| ..)` method takes [`aoi0_input::W`](W) writer structure"] -impl crate::Writable for Aoi0InputSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets AOI0_INPUT[%s] to value 0x7f"] -impl crate::Resettable for Aoi0InputSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/aoi1_input.rs b/mcxa276-pac/src/inputmux0/aoi1_input.rs deleted file mode 100644 index 721b0aba0..000000000 --- a/mcxa276-pac/src/inputmux0/aoi1_input.rs +++ /dev/null @@ -1,1302 +0,0 @@ -#[doc = "Register `AOI1_INPUT[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `AOI1_INPUT[%s]` writer"] -pub type W = crate::W; -#[doc = "AOI0 trigger input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ADC0_tcomp\\[0\\] input is selected"] - Val1 = 1, - #[doc = "2: ADC0_tcomp\\[1\\] input is selected"] - Val2 = 2, - #[doc = "3: ADC0_tcomp\\[2\\] input is selected"] - Val3 = 3, - #[doc = "4: ADC0_tcomp\\[3\\] input is selected"] - Val4 = 4, - #[doc = "5: CMP0_OUT input is selected"] - Val5 = 5, - #[doc = "6: CMP1_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP2_OUT input is selected"] - Val7 = 7, - #[doc = "8: CTimer0_MAT0 input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT1 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT2 input is selected"] - Val10 = 10, - #[doc = "11: CTimer0_MAT3 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT0"] - Val12 = 12, - #[doc = "13: CTimer1_MAT1 input is selected"] - Val13 = 13, - #[doc = "14: CTimer1_MAT2 input is selected"] - Val14 = 14, - #[doc = "15: CTimer1_MAT3 input is selected"] - Val15 = 15, - #[doc = "16: CTimer2_MAT0 input is selected"] - Val16 = 16, - #[doc = "17: CTimer2_MAT1 input is selected"] - Val17 = 17, - #[doc = "18: CTimer2_MAT2 input is selected"] - Val18 = 18, - #[doc = "19: CTimer2_MAT3 input is selected"] - Val19 = 19, - #[doc = "20: LPTMR0 input is selected"] - Val20 = 20, - #[doc = "22: QDC0_CMP_FLAG0 input is selected"] - Val22 = 22, - #[doc = "23: QDC0_CMP_FLAG1 input is selected"] - Val23 = 23, - #[doc = "24: QDC0_CMP_FLAG2 input is selected"] - Val24 = 24, - #[doc = "25: QDC0_CMP_FLAG3 input is selected"] - Val25 = 25, - #[doc = "26: QDC0_POS_MATCH0 input is selected"] - Val26 = 26, - #[doc = "27: PWM0_SM0_MUX_TRIG0 input is selected"] - Val27 = 27, - #[doc = "28: PWM0_SM0_MUX_TRIG1 input is selected"] - Val28 = 28, - #[doc = "29: PWM0_SM1_MUX_TRIG0 input is selected"] - Val29 = 29, - #[doc = "30: PWM0_SM1_MUX_TRIG1 input is selected"] - Val30 = 30, - #[doc = "31: PWM0_SM2_MUX_TRIG0 input is selected"] - Val31 = 31, - #[doc = "32: PWM0_SM2_MUX_TRIG1 input is selected"] - Val32 = 32, - #[doc = "33: PWM0_SM3_MUX_TRIG0 input is selected"] - Val33 = 33, - #[doc = "34: PWM0_SM3_MUX_TRIG1 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN0 input is selected"] - Val35 = 35, - #[doc = "36: TRIG_IN1 input is selected"] - Val36 = 36, - #[doc = "37: TRIG_IN2 input is selected"] - Val37 = 37, - #[doc = "38: TRIG_IN3 input is selected"] - Val38 = 38, - #[doc = "39: TRIG_IN4 input is selected"] - Val39 = 39, - #[doc = "40: TRIG_IN5 input is selected"] - Val40 = 40, - #[doc = "41: TRIG_IN6 input is selected"] - Val41 = 41, - #[doc = "42: TRIG_IN7 input is selected"] - Val42 = 42, - #[doc = "43: TRIG_IN8 input is selected"] - Val43 = 43, - #[doc = "44: TRIG_IN9 input is selected"] - Val44 = 44, - #[doc = "45: TRIG_IN10 input is selected"] - Val45 = 45, - #[doc = "46: TRIG_IN11 input is selected"] - Val46 = 46, - #[doc = "47: GPIO0 Pin Event Trig 0 input is selected"] - Val47 = 47, - #[doc = "48: GPIO1 Pin Event Trig 0 input is selected"] - Val48 = 48, - #[doc = "49: GPIO2 Pin Event Trig 0 input is selected"] - Val49 = 49, - #[doc = "50: GPIO3 Pin Event Trig 0 input is selected"] - Val50 = 50, - #[doc = "51: GPIO4 Pin Event Trig 0 input is selected"] - Val51 = 51, - #[doc = "52: ADC1_tcomp\\[0\\] input is selected"] - Val52 = 52, - #[doc = "53: ADC1_tcomp\\[1\\] input is selected"] - Val53 = 53, - #[doc = "54: ADC1_tcomp\\[2\\] input is selected"] - Val54 = 54, - #[doc = "55: ADC1_tcomp\\[3\\] input is selected"] - Val55 = 55, - #[doc = "56: CTimer3_MAT0 input is selected"] - Val56 = 56, - #[doc = "57: CTimer3_MAT1 input is selected"] - Val57 = 57, - #[doc = "58: CTimer3_MAT2 input is selected"] - Val58 = 58, - #[doc = "59: CTimer3_MAT3 input is selected"] - Val59 = 59, - #[doc = "60: CTimer4_MAT0 input is selected"] - Val60 = 60, - #[doc = "61: CTimer4_MAT1 input is selected"] - Val61 = 61, - #[doc = "62: CTimer4_MAT2 input is selected"] - Val62 = 62, - #[doc = "63: CTimer4_MAT3 input is selected"] - Val63 = 63, - #[doc = "64: FlexIO CH0 input is selected"] - Val64 = 64, - #[doc = "65: FlexIO CH1 input is selected"] - Val65 = 65, - #[doc = "66: FlexIO CH2 input is selected"] - Val66 = 66, - #[doc = "67: FlexIO CH3 input is selected"] - Val67 = 67, - #[doc = "68: QDC1_CMP_FLAG0 input is selected"] - Val68 = 68, - #[doc = "69: QDC1_CMP_FLAG1 input is selected"] - Val69 = 69, - #[doc = "70: QDC1_CMP_FLAG2 input is selected"] - Val70 = 70, - #[doc = "71: QDC1_CMP_FLAG3 input is selected"] - Val71 = 71, - #[doc = "72: QDC1_POS_MATCH0 input is selected"] - Val72 = 72, - #[doc = "73: PWM1_SM0_MUX_TRIG0 input is selected"] - Val73 = 73, - #[doc = "74: PWM1_SM0_MUX_TRIG1 input is selected"] - Val74 = 74, - #[doc = "75: PWM1_SM1_MUX_TRIG0 input is selected"] - Val75 = 75, - #[doc = "76: PWM1_SM1_MUX_TRIG1 input is selected"] - Val76 = 76, - #[doc = "77: PWM1_SM2_MUX_TRIG0 input is selected"] - Val77 = 77, - #[doc = "78: PWM1_SM2_MUX_TRIG1 input is selected"] - Val78 = 78, - #[doc = "79: PWM1_SM3_MUX_TRIG0 input is selected"] - Val79 = 79, - #[doc = "80: PWM1_SM3_MUX_TRIG1 input is selected"] - Val80 = 80, - #[doc = "81: PWM0_SM0_A_Output"] - Val81 = 81, - #[doc = "82: PWM0_SM0_B_Output"] - Val82 = 82, - #[doc = "83: PWM0_SM1_A_Output"] - Val83 = 83, - #[doc = "84: PWM0_SM1_B_Output"] - Val84 = 84, - #[doc = "85: PWM0_SM2_A_Output"] - Val85 = 85, - #[doc = "86: PWM0_SM2_B_Output"] - Val86 = 86, - #[doc = "87: PWM0_SM3_A_Output"] - Val87 = 87, - #[doc = "88: PWM0_SM3_B_Output"] - Val88 = 88, - #[doc = "89: ADC2_tcomp\\[0\\] input is selected"] - Val89 = 89, - #[doc = "90: ADC2_tcomp\\[1\\] input is selected"] - Val90 = 90, - #[doc = "91: ADC2_tcomp\\[2\\] input is selected"] - Val91 = 91, - #[doc = "92: ADC2_tcomp\\[3\\] input is selected"] - Val92 = 92, - #[doc = "93: ADC3_tcomp\\[0\\] input is selected"] - Val93 = 93, - #[doc = "94: ADC3_tcomp\\[1\\] input is selected"] - Val94 = 94, - #[doc = "95: ADC3_tcomp\\[2\\] input is selected"] - Val95 = 95, - #[doc = "96: ADC3_tcomp\\[3\\] input is selected"] - Val96 = 96, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - AOI0 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - _ => None, - } - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "PWM0_SM0_A_Output"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "PWM0_SM0_B_Output"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "PWM0_SM1_A_Output"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "PWM0_SM1_B_Output"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "PWM0_SM2_A_Output"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "PWM0_SM2_B_Output"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "PWM0_SM3_A_Output"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "PWM0_SM3_B_Output"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } -} -#[doc = "Field `INP` writer - AOI0 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "PWM0_SM0_A_Output"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "PWM0_SM0_B_Output"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "PWM0_SM1_A_Output"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "PWM0_SM1_B_Output"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "PWM0_SM2_A_Output"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "PWM0_SM2_B_Output"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "PWM0_SM3_A_Output"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "PWM0_SM3_B_Output"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } -} -impl R { - #[doc = "Bits 0:6 - AOI0 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - AOI0 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "AOI1 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi1_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi1_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Aoi1InputSpec; -impl crate::RegisterSpec for Aoi1InputSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`aoi1_input::R`](R) reader structure"] -impl crate::Readable for Aoi1InputSpec {} -#[doc = "`write(|w| ..)` method takes [`aoi1_input::W`](W) writer structure"] -impl crate::Writable for Aoi1InputSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets AOI1_INPUT[%s] to value 0x7f"] -impl crate::Resettable for Aoi1InputSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/cmp0_trig.rs b/mcxa276-pac/src/inputmux0/cmp0_trig.rs deleted file mode 100644 index 5c5fd4337..000000000 --- a/mcxa276-pac/src/inputmux0/cmp0_trig.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `CMP0_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `CMP0_TRIG` writer"] -pub type W = crate::W; -#[doc = "CMP0 input trigger\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP1_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP2_OUT input is selected"] - Val7 = 7, - #[doc = "8: CTimer0_MAT0 input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer1_MAT0"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer2_MAT0 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: LPTMR0 input is selected"] - Val14 = 14, - #[doc = "16: QDC0_POS_MATCH0"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG0 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM0_MUX_TRIG1 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG0 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_MUX_TRIG1 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG0 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_MUX_TRIG1 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] - Val23 = 23, - #[doc = "24: PWM0_SM3_MUX_TRIG1 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "39: CTimer3_MAT0"] - Val39 = 39, - #[doc = "40: CTimer3_MAT1"] - Val40 = 40, - #[doc = "41: CTimer4_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT1 input is selected"] - Val42 = 42, - #[doc = "47: QDC1_POS_MATCH0 input is selected"] - Val47 = 47, - #[doc = "48: PWM1_SM0_MUX_TRIG0 input is selected"] - Val48 = 48, - #[doc = "49: PWM1_SM0_MUX_TRIG1 input is selected"] - Val49 = 49, - #[doc = "50: PWM1_SM1_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM1_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM2_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM2_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM3_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] - Val55 = 55, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - CMP0 input trigger"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_POS_MATCH0"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "CTimer3_MAT0"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "CTimer3_MAT1"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } -} -#[doc = "Field `TRIGIN` writer - CMP0 input trigger"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_POS_MATCH0"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "CTimer3_MAT0"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "CTimer3_MAT1"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } -} -impl R { - #[doc = "Bits 0:5 - CMP0 input trigger"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - CMP0 input trigger"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "CMP0 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmp0TrigSpec; -impl crate::RegisterSpec for Cmp0TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmp0_trig::R`](R) reader structure"] -impl crate::Readable for Cmp0TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`cmp0_trig::W`](W) writer structure"] -impl crate::Writable for Cmp0TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMP0_TRIG to value 0x3f"] -impl crate::Resettable for Cmp0TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/cmp1_trig.rs b/mcxa276-pac/src/inputmux0/cmp1_trig.rs deleted file mode 100644 index a96b98418..000000000 --- a/mcxa276-pac/src/inputmux0/cmp1_trig.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `CMP1_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `CMP1_TRIG` writer"] -pub type W = crate::W; -#[doc = "CMP1 input trigger\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP2_OUT input is selected"] - Val7 = 7, - #[doc = "8: CTimer0_MAT0 input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer1_MAT0"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer2_MAT0 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: LPTMR0 input is selected"] - Val14 = 14, - #[doc = "16: QDC0_POS_MATCH0"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG0 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM0_MUX_TRIG1 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG0 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_MUX_TRIG1 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG0 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_MUX_TRIG1 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] - Val23 = 23, - #[doc = "24: PWM0_SM3_MUX_TRIG1 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "39: CTimer3_MAT0"] - Val39 = 39, - #[doc = "40: CTimer3_MAT1"] - Val40 = 40, - #[doc = "41: CTimer4_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT1 input is selected"] - Val42 = 42, - #[doc = "47: QDC1_POS_MATCH0 input is selected"] - Val47 = 47, - #[doc = "48: PWM1_SM0_MUX_TRIG0 input is selected"] - Val48 = 48, - #[doc = "49: PWM1_SM0_MUX_TRIG1 input is selected"] - Val49 = 49, - #[doc = "50: PWM1_SM1_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM1_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM2_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM2_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM3_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] - Val55 = 55, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - CMP1 input trigger"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_POS_MATCH0"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "CTimer3_MAT0"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "CTimer3_MAT1"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } -} -#[doc = "Field `TRIGIN` writer - CMP1 input trigger"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_POS_MATCH0"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "CTimer3_MAT0"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "CTimer3_MAT1"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } -} -impl R { - #[doc = "Bits 0:5 - CMP1 input trigger"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - CMP1 input trigger"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "CMP1 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmp1TrigSpec; -impl crate::RegisterSpec for Cmp1TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmp1_trig::R`](R) reader structure"] -impl crate::Readable for Cmp1TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`cmp1_trig::W`](W) writer structure"] -impl crate::Writable for Cmp1TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMP1_TRIG to value 0x3f"] -impl crate::Resettable for Cmp1TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/cmp2_trig.rs b/mcxa276-pac/src/inputmux0/cmp2_trig.rs deleted file mode 100644 index b8988a4de..000000000 --- a/mcxa276-pac/src/inputmux0/cmp2_trig.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `CMP2_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `CMP2_TRIG` writer"] -pub type W = crate::W; -#[doc = "CMP2 input trigger\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CTimer0_MAT0 input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer1_MAT0"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer2_MAT0 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: LPTMR0 input is selected"] - Val14 = 14, - #[doc = "16: QDC0_POS_MATCH0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG0 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM0_MUX_TRIG1 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG0 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_MUX_TRIG1 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG0 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_MUX_TRIG1 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] - Val23 = 23, - #[doc = "24: PWM0_SM3_MUX_TRIG1 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "39: CTimer3_MAT0"] - Val39 = 39, - #[doc = "40: CTimer3_MAT1"] - Val40 = 40, - #[doc = "41: CTimer4_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT1 input is selected"] - Val42 = 42, - #[doc = "47: QDC1_POS_MATCH0 input is selected"] - Val47 = 47, - #[doc = "48: PWM1_SM0_MUX_TRIG0 input is selected"] - Val48 = 48, - #[doc = "49: PWM1_SM0_MUX_TRIG1 input is selected"] - Val49 = 49, - #[doc = "50: PWM1_SM1_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM1_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM2_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM2_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM3_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM2_MUX_TRIG1 input is selected"] - Val55 = 55, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - CMP2 input trigger"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "CTimer3_MAT0"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "CTimer3_MAT1"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } -} -#[doc = "Field `TRIGIN` writer - CMP2 input trigger"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer1_MAT0"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "CTimer3_MAT0"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "CTimer3_MAT1"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } -} -impl R { - #[doc = "Bits 0:5 - CMP2 input trigger"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - CMP2 input trigger"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "CMP2 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp2_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp2_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cmp2TrigSpec; -impl crate::RegisterSpec for Cmp2TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmp2_trig::R`](R) reader structure"] -impl crate::Readable for Cmp2TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`cmp2_trig::W`](W) writer structure"] -impl crate::Writable for Cmp2TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMP2_TRIG to value 0x3f"] -impl crate::Resettable for Cmp2TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/ctimer0cap.rs b/mcxa276-pac/src/inputmux0/ctimer0cap.rs deleted file mode 100644 index 892ab6d6f..000000000 --- a/mcxa276-pac/src/inputmux0/ctimer0cap.rs +++ /dev/null @@ -1,1471 +0,0 @@ -#[doc = "Register `CTIMER0CAP[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `CTIMER0CAP[%s]` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER0\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer1_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer1_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer1_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer2_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer2_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer2_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer3_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer3_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer3_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM3_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER0"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER0"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER0"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER0"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer0cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer0cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctimer0capSpec; -impl crate::RegisterSpec for Ctimer0capSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctimer0cap::R`](R) reader structure"] -impl crate::Readable for Ctimer0capSpec {} -#[doc = "`write(|w| ..)` method takes [`ctimer0cap::W`](W) writer structure"] -impl crate::Writable for Ctimer0capSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTIMER0CAP[%s] to value 0x7f"] -impl crate::Resettable for Ctimer0capSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/ctimer1cap.rs b/mcxa276-pac/src/inputmux0/ctimer1cap.rs deleted file mode 100644 index 1752e1cb3..000000000 --- a/mcxa276-pac/src/inputmux0/ctimer1cap.rs +++ /dev/null @@ -1,1471 +0,0 @@ -#[doc = "Register `CTIMER1CAP[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `CTIMER1CAP[%s]` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER1\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer2_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer2_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer2_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer3_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer3_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer3_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER1"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER1"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER1"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER1"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer1cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer1cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctimer1capSpec; -impl crate::RegisterSpec for Ctimer1capSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctimer1cap::R`](R) reader structure"] -impl crate::Readable for Ctimer1capSpec {} -#[doc = "`write(|w| ..)` method takes [`ctimer1cap::W`](W) writer structure"] -impl crate::Writable for Ctimer1capSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTIMER1CAP[%s] to value 0x7f"] -impl crate::Resettable for Ctimer1capSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/ctimer2cap.rs b/mcxa276-pac/src/inputmux0/ctimer2cap.rs deleted file mode 100644 index 14ba36d74..000000000 --- a/mcxa276-pac/src/inputmux0/ctimer2cap.rs +++ /dev/null @@ -1,1471 +0,0 @@ -#[doc = "Register `CTIMER2CAP[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `CTIMER2CAP[%s]` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER2\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer1_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer1_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer1_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer3_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer3_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer3_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER2"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER2"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER2"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER2"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer2cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer2cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctimer2capSpec; -impl crate::RegisterSpec for Ctimer2capSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctimer2cap::R`](R) reader structure"] -impl crate::Readable for Ctimer2capSpec {} -#[doc = "`write(|w| ..)` method takes [`ctimer2cap::W`](W) writer structure"] -impl crate::Writable for Ctimer2capSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTIMER2CAP[%s] to value 0x7f"] -impl crate::Resettable for Ctimer2capSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/ctimer3cap.rs b/mcxa276-pac/src/inputmux0/ctimer3cap.rs deleted file mode 100644 index 6fe3703ec..000000000 --- a/mcxa276-pac/src/inputmux0/ctimer3cap.rs +++ /dev/null @@ -1,1627 +0,0 @@ -#[doc = "Register `CTIMER3CAP[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `CTIMER3CAP[%s]` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER3\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer1_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer1_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer1_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer2_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer2_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer2_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, - #[doc = "113: TRIG_IN0 input is selected"] - Val113 = 113, - #[doc = "114: TRIG_IN1 input is selected"] - Val114 = 114, - #[doc = "115: TRIG_IN2 input is selected"] - Val115 = 115, - #[doc = "116: TRIG_IN3 input is selected"] - Val116 = 116, - #[doc = "117: TRIG_IN4 input is selected"] - Val117 = 117, - #[doc = "118: TRIG_IN5 input is selected"] - Val118 = 118, - #[doc = "119: TRIG_IN6 input is selected"] - Val119 = 119, - #[doc = "120: TRIG_IN7 input is selected"] - Val120 = 120, - #[doc = "121: TRIG_IN8 input is selected"] - Val121 = 121, - #[doc = "122: TRIG_IN9 input is selected"] - Val122 = 122, - #[doc = "123: TRIG_IN10 input is selected"] - Val123 = 123, - #[doc = "124: TRIG_IN11 input is selected"] - Val124 = 124, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER3"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - 113 => Some(Inp::Val113), - 114 => Some(Inp::Val114), - 115 => Some(Inp::Val115), - 116 => Some(Inp::Val116), - 117 => Some(Inp::Val117), - 118 => Some(Inp::Val118), - 119 => Some(Inp::Val119), - 120 => Some(Inp::Val120), - 121 => Some(Inp::Val121), - 122 => Some(Inp::Val122), - 123 => Some(Inp::Val123), - 124 => Some(Inp::Val124), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val113(&self) -> bool { - *self == Inp::Val113 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val114(&self) -> bool { - *self == Inp::Val114 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val115(&self) -> bool { - *self == Inp::Val115 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val116(&self) -> bool { - *self == Inp::Val116 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val117(&self) -> bool { - *self == Inp::Val117 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val118(&self) -> bool { - *self == Inp::Val118 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val119(&self) -> bool { - *self == Inp::Val119 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val120(&self) -> bool { - *self == Inp::Val120 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val121(&self) -> bool { - *self == Inp::Val121 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val122(&self) -> bool { - *self == Inp::Val122 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val123(&self) -> bool { - *self == Inp::Val123 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val124(&self) -> bool { - *self == Inp::Val124 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER3"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val113(self) -> &'a mut crate::W { - self.variant(Inp::Val113) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val114(self) -> &'a mut crate::W { - self.variant(Inp::Val114) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val115(self) -> &'a mut crate::W { - self.variant(Inp::Val115) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val116(self) -> &'a mut crate::W { - self.variant(Inp::Val116) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val117(self) -> &'a mut crate::W { - self.variant(Inp::Val117) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val118(self) -> &'a mut crate::W { - self.variant(Inp::Val118) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val119(self) -> &'a mut crate::W { - self.variant(Inp::Val119) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val120(self) -> &'a mut crate::W { - self.variant(Inp::Val120) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val121(self) -> &'a mut crate::W { - self.variant(Inp::Val121) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val122(self) -> &'a mut crate::W { - self.variant(Inp::Val122) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val123(self) -> &'a mut crate::W { - self.variant(Inp::Val123) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val124(self) -> &'a mut crate::W { - self.variant(Inp::Val124) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER3"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER3"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer3cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer3cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctimer3capSpec; -impl crate::RegisterSpec for Ctimer3capSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctimer3cap::R`](R) reader structure"] -impl crate::Readable for Ctimer3capSpec {} -#[doc = "`write(|w| ..)` method takes [`ctimer3cap::W`](W) writer structure"] -impl crate::Writable for Ctimer3capSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTIMER3CAP[%s] to value 0x7f"] -impl crate::Resettable for Ctimer3capSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/ctimer4cap.rs b/mcxa276-pac/src/inputmux0/ctimer4cap.rs deleted file mode 100644 index e5fa7f6e4..000000000 --- a/mcxa276-pac/src/inputmux0/ctimer4cap.rs +++ /dev/null @@ -1,1627 +0,0 @@ -#[doc = "Register `CTIMER4CAP[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `CTIMER4CAP[%s]` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER4\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer1_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer1_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer1_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer2_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer2_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer2_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer3_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer3_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer3_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, - #[doc = "113: TRIG_IN0 input is selected"] - Val113 = 113, - #[doc = "114: TRIG_IN1 input is selected"] - Val114 = 114, - #[doc = "115: TRIG_IN2 input is selected"] - Val115 = 115, - #[doc = "116: TRIG_IN3 input is selected"] - Val116 = 116, - #[doc = "117: TRIG_IN4 input is selected"] - Val117 = 117, - #[doc = "118: TRIG_IN5 input is selected"] - Val118 = 118, - #[doc = "119: TRIG_IN6 input is selected"] - Val119 = 119, - #[doc = "120: TRIG_IN7 input is selected"] - Val120 = 120, - #[doc = "121: TRIG_IN8 input is selected"] - Val121 = 121, - #[doc = "122: TRIG_IN9 input is selected"] - Val122 = 122, - #[doc = "123: TRIG_IN10 input is selected"] - Val123 = 123, - #[doc = "124: TRIG_IN11 input is selected"] - Val124 = 124, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER4"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - 113 => Some(Inp::Val113), - 114 => Some(Inp::Val114), - 115 => Some(Inp::Val115), - 116 => Some(Inp::Val116), - 117 => Some(Inp::Val117), - 118 => Some(Inp::Val118), - 119 => Some(Inp::Val119), - 120 => Some(Inp::Val120), - 121 => Some(Inp::Val121), - 122 => Some(Inp::Val122), - 123 => Some(Inp::Val123), - 124 => Some(Inp::Val124), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val113(&self) -> bool { - *self == Inp::Val113 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val114(&self) -> bool { - *self == Inp::Val114 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val115(&self) -> bool { - *self == Inp::Val115 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val116(&self) -> bool { - *self == Inp::Val116 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val117(&self) -> bool { - *self == Inp::Val117 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val118(&self) -> bool { - *self == Inp::Val118 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val119(&self) -> bool { - *self == Inp::Val119 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val120(&self) -> bool { - *self == Inp::Val120 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val121(&self) -> bool { - *self == Inp::Val121 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val122(&self) -> bool { - *self == Inp::Val122 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val123(&self) -> bool { - *self == Inp::Val123 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val124(&self) -> bool { - *self == Inp::Val124 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER4"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val113(self) -> &'a mut crate::W { - self.variant(Inp::Val113) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val114(self) -> &'a mut crate::W { - self.variant(Inp::Val114) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val115(self) -> &'a mut crate::W { - self.variant(Inp::Val115) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val116(self) -> &'a mut crate::W { - self.variant(Inp::Val116) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val117(self) -> &'a mut crate::W { - self.variant(Inp::Val117) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val118(self) -> &'a mut crate::W { - self.variant(Inp::Val118) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val119(self) -> &'a mut crate::W { - self.variant(Inp::Val119) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val120(self) -> &'a mut crate::W { - self.variant(Inp::Val120) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val121(self) -> &'a mut crate::W { - self.variant(Inp::Val121) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val122(self) -> &'a mut crate::W { - self.variant(Inp::Val122) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val123(self) -> &'a mut crate::W { - self.variant(Inp::Val123) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val124(self) -> &'a mut crate::W { - self.variant(Inp::Val124) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER4"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER4"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer4cap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer4cap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ctimer4capSpec; -impl crate::RegisterSpec for Ctimer4capSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctimer4cap::R`](R) reader structure"] -impl crate::Readable for Ctimer4capSpec {} -#[doc = "`write(|w| ..)` method takes [`ctimer4cap::W`](W) writer structure"] -impl crate::Writable for Ctimer4capSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTIMER4CAP[%s] to value 0x7f"] -impl crate::Resettable for Ctimer4capSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/dac0_trig.rs b/mcxa276-pac/src/inputmux0/dac0_trig.rs deleted file mode 100644 index e2869025c..000000000 --- a/mcxa276-pac/src/inputmux0/dac0_trig.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `DAC0_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `DAC0_TRIG` writer"] -pub type W = crate::W; -#[doc = "DAC0 trigger input\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "18: PWM0_SM0_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM0_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM1_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM1_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "26: GPIO0 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO1 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO2 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO3 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO4 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: WUU input is selected"] - Val31 = 31, - #[doc = "33: AOI1_OUT0 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT1 input is selected"] - Val34 = 34, - #[doc = "35: AOI1_OUT2 input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT3 input is selected"] - Val36 = 36, - #[doc = "37: ADC0_tcomp\\[0\\] input is selected"] - Val37 = 37, - #[doc = "38: ADC0_tcomp\\[1\\] input is selected"] - Val38 = 38, - #[doc = "39: ADC1_tcomp\\[0\\] input is selected"] - Val39 = 39, - #[doc = "40: ADC1_tcomp\\[1\\] input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT0 input is selected"] - Val41 = 41, - #[doc = "42: CTimer3_MAT1 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT0 input is selected"] - Val43 = 43, - #[doc = "44: CTimer4_MAT1 input is selected"] - Val44 = 44, - #[doc = "50: PWM1_SM0_MUX_TRIG0 input is selected"] - Val50 = 50, - #[doc = "51: PWM1_SM0_MUX_TRIG1 input is selected"] - Val51 = 51, - #[doc = "52: PWM1_SM1_MUX_TRIG0 input is selected"] - Val52 = 52, - #[doc = "53: PWM1_SM1_MUX_TRIG1 input is selected"] - Val53 = 53, - #[doc = "58: ADC2_tcomp\\[0\\] input is selected"] - Val58 = 58, - #[doc = "59: ADC2_tcomp\\[1\\] input is selected"] - Val59 = 59, - #[doc = "60: ADC3_tcomp\\[0\\] input is selected"] - Val60 = 60, - #[doc = "61: ADC3_tcomp\\[1\\] input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - DAC0 trigger input"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 41 => Some(Trigin::Val41), - 42 => Some(Trigin::Val42), - 43 => Some(Trigin::Val43), - 44 => Some(Trigin::Val44), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Trigin::Val41 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Trigin::Val42 - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Trigin::Val43 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Trigin::Val44 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - DAC0 trigger input"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Trigin::Val41) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Trigin::Val42) - } - #[doc = "CTimer4_MAT0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Trigin::Val43) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Trigin::Val44) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - DAC0 trigger input"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - DAC0 trigger input"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "DAC0 Trigger input connections.\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dac0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Dac0TrigSpec; -impl crate::RegisterSpec for Dac0TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`dac0_trig::R`](R) reader structure"] -impl crate::Readable for Dac0TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`dac0_trig::W`](W) writer structure"] -impl crate::Writable for Dac0TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DAC0_TRIG to value 0x3f"] -impl crate::Resettable for Dac0TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/ext_trig.rs b/mcxa276-pac/src/inputmux0/ext_trig.rs deleted file mode 100644 index 28a3c7cfb..000000000 --- a/mcxa276-pac/src/inputmux0/ext_trig.rs +++ /dev/null @@ -1,288 +0,0 @@ -#[doc = "Register `EXT_TRIG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `EXT_TRIG[%s]` writer"] -pub type W = crate::W; -#[doc = "EXT trigger input connections\n\nValue on reset: 31"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: LPUART0 ipp_do_lpuart_txd input is selected"] - Val9 = 9, - #[doc = "10: LPUART1 ipp_do_lpuart_txd input is selected"] - Val10 = 10, - #[doc = "11: LPUART2 ipp_do_lpuart_txd input is selected"] - Val11 = 11, - #[doc = "12: LPUART3 ipp_do_lpuart_txd input is selected"] - Val12 = 12, - #[doc = "13: LPUART4 ipp_do_lpuart_txd input is selected"] - Val13 = 13, - #[doc = "14: AOI1_OUT0 input is selected"] - Val14 = 14, - #[doc = "15: AOI1_OUT1 input is selected"] - Val15 = 15, - #[doc = "16: AOI1_OUT2 input is selected"] - Val16 = 16, - #[doc = "17: RTC_1Hz_CLK input is selected"] - Val17 = 17, - #[doc = "18: LPUART5 ipp_do_lpuart_txd input is selected"] - Val18 = 18, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - EXT trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "LPUART0 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "LPUART1 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "LPUART2 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "LPUART3 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "LPUART4 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "RTC_1Hz_CLK input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "LPUART5 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } -} -#[doc = "Field `INP` writer - EXT trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 5, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "LPUART0 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "LPUART1 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "LPUART2 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "LPUART3 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "LPUART4 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "RTC_1Hz_CLK input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "LPUART5 ipp_do_lpuart_txd input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } -} -impl R { - #[doc = "Bits 0:4 - EXT trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x1f) as u8) - } -} -impl W { - #[doc = "Bits 0:4 - EXT trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "EXT trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ExtTrigSpec; -impl crate::RegisterSpec for ExtTrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ext_trig::R`](R) reader structure"] -impl crate::Readable for ExtTrigSpec {} -#[doc = "`write(|w| ..)` method takes [`ext_trig::W`](W) writer structure"] -impl crate::Writable for ExtTrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EXT_TRIG[%s] to value 0x1f"] -impl crate::Resettable for ExtTrigSpec { - const RESET_VALUE: u32 = 0x1f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs deleted file mode 100644 index 0276feac7..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_fault.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_FAULT[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_FAULT[%s]` writer"] -pub type W = crate::W; -#[doc = "FAULT input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - FAULT input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - FAULT input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - FAULT input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - FAULT input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_fault::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_fault::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0FaultSpec; -impl crate::RegisterSpec for FlexPwm0FaultSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_fault::R`](R) reader structure"] -impl crate::Readable for FlexPwm0FaultSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_fault::W`](W) writer structure"] -impl crate::Writable for FlexPwm0FaultSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_FAULT[%s] to value 0x3f"] -impl crate::Resettable for FlexPwm0FaultSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_force.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_force.rs deleted file mode 100644 index 8f8e675ef..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_force.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_FORCE` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_FORCE` writer"] -pub type W = crate::W; -#[doc = "Trigger input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - Trigger input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Trigger input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_force::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_force::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0ForceSpec; -impl crate::RegisterSpec for FlexPwm0ForceSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_force::R`](R) reader structure"] -impl crate::Readable for FlexPwm0ForceSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_force::W`](W) writer structure"] -impl crate::Writable for FlexPwm0ForceSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_FORCE to value 0x3f"] -impl crate::Resettable for FlexPwm0ForceSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs deleted file mode 100644 index aa291e59a..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_exta0.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM0_EXTA0` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM0_EXTA0` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm0Exta0Spec; -impl crate::RegisterSpec for FlexPwm0Sm0Exta0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm0_exta0::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm0Exta0Spec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm0_exta0::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm0Exta0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM0_EXTA0 to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm0Exta0Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs deleted file mode 100644 index 5f7151478..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm0_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM0_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM0_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm0ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm0Sm0ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm0_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm0ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm0_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm0ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM0_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm0ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs deleted file mode 100644 index 4100e5e16..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_exta.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM1_EXTA` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM1_EXTA` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm1ExtaSpec; -impl crate::RegisterSpec for FlexPwm0Sm1ExtaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm1_exta::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm1ExtaSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm1_exta::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm1ExtaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM1_EXTA to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm1ExtaSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs deleted file mode 100644 index 2d0d0474f..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm1_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM1_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM1_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm1ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm0Sm1ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm1_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm1ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm1_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm1ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM1_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm1ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs deleted file mode 100644 index 19fe1f3d0..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_exta.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM2_EXTA` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM2_EXTA` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm2ExtaSpec; -impl crate::RegisterSpec for FlexPwm0Sm2ExtaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm2_exta::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm2ExtaSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm2_exta::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm2ExtaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM2_EXTA to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm2ExtaSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs deleted file mode 100644 index dff963e90..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm2_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM2_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM2_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm2ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm0Sm2ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm2_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm2ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm2_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm2ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM2_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm2ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs deleted file mode 100644 index 5c0c50075..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_exta0.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM3_EXTA0` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM3_EXTA0` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm3Exta0Spec; -impl crate::RegisterSpec for FlexPwm0Sm3Exta0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm3_exta0::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm3Exta0Spec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm3_exta0::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm3Exta0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM3_EXTA0 to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm3Exta0Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs deleted file mode 100644 index 4799815bd..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm0_sm3_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM0_SM3_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM0_SM3_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM1_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM1_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM1_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM1_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM1_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM1_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM1_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM1_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm0Sm3ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm0Sm3ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm0_sm3_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm0Sm3ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm0_sm3_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm0Sm3ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM0_SM3_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm0Sm3ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs deleted file mode 100644 index bc1379279..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_fault.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_FAULT[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_FAULT[%s]` writer"] -pub type W = crate::W; -#[doc = "FAULT input connections for PWM1\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - FAULT input connections for PWM1"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - FAULT input connections for PWM1"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - FAULT input connections for PWM1"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - FAULT input connections for PWM1"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_fault::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_fault::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1FaultSpec; -impl crate::RegisterSpec for FlexPwm1FaultSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_fault::R`](R) reader structure"] -impl crate::Readable for FlexPwm1FaultSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_fault::W`](W) writer structure"] -impl crate::Writable for FlexPwm1FaultSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_FAULT[%s] to value 0x3f"] -impl crate::Resettable for FlexPwm1FaultSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_force.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_force.rs deleted file mode 100644 index cafcc6a3e..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_force.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_FORCE` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_FORCE` writer"] -pub type W = crate::W; -#[doc = "Trigger input connections for PWM1\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM1"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM1"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - Trigger input connections for PWM1"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Trigger input connections for PWM1"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_force::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_force::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1ForceSpec; -impl crate::RegisterSpec for FlexPwm1ForceSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_force::R`](R) reader structure"] -impl crate::Readable for FlexPwm1ForceSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_force::W`](W) writer structure"] -impl crate::Writable for FlexPwm1ForceSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_FORCE to value 0x3f"] -impl crate::Resettable for FlexPwm1ForceSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs deleted file mode 100644 index 40b9d8785..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_exta0.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM0_EXTA0` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM0_EXTA0` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm0Exta0Spec; -impl crate::RegisterSpec for FlexPwm1Sm0Exta0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm0_exta0::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm0Exta0Spec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm0_exta0::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm0Exta0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM0_EXTA0 to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm0Exta0Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs deleted file mode 100644 index f1aa07af4..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm0_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM0_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM0_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm0ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm1Sm0ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm0_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm0ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm0_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm0ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM0_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm0ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs deleted file mode 100644 index 0e1937dba..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_exta.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM1_EXTA` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM1_EXTA` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm1ExtaSpec; -impl crate::RegisterSpec for FlexPwm1Sm1ExtaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm1_exta::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm1ExtaSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm1_exta::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm1ExtaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM1_EXTA to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm1ExtaSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs deleted file mode 100644 index 112ec4965..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm1_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM1_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM1_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm1ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm1Sm1ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm1_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm1ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm1_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm1ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM1_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm1ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs deleted file mode 100644 index f2e03e309..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_exta.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM2_EXTA` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM2_EXTA` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_exta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_exta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm2ExtaSpec; -impl crate::RegisterSpec for FlexPwm1Sm2ExtaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm2_exta::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm2ExtaSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm2_exta::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm2ExtaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM2_EXTA to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm2ExtaSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs deleted file mode 100644 index d11de8a73..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm2_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM2_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM2_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm2ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm1Sm2ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm2_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm2ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm2_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm2ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM2_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm2ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs deleted file mode 100644 index 7b3ba661e..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_exta0.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM3_EXTA0` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM3_EXTA0` writer"] -pub type W = crate::W; -#[doc = "EXTA input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTA input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTA input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTA input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_exta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_exta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm3Exta0Spec; -impl crate::RegisterSpec for FlexPwm1Sm3Exta0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm3_exta0::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm3Exta0Spec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm3_exta0::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm3Exta0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM3_EXTA0 to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm3Exta0Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs b/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs deleted file mode 100644 index 45f16c66c..000000000 --- a/mcxa276-pac/src/inputmux0/flex_pwm1_sm3_extsync.rs +++ /dev/null @@ -1,808 +0,0 @@ -#[doc = "Register `FlexPWM1_SM3_EXTSYNC` reader"] -pub type R = crate::R; -#[doc = "Register `FlexPWM1_SM3_EXTSYNC` writer"] -pub type W = crate::W; -#[doc = "EXTSYNC input connections for PWM0\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: QDC0_CMP_FLAG0 input is selected"] - Val15 = 15, - #[doc = "16: QDC0_CMP_FLAG1 input is selected"] - Val16 = 16, - #[doc = "17: QDC0_CMP_FLAG2 input is selected"] - Val17 = 17, - #[doc = "18: QDC0_CMP_FLAG3 input is selected"] - Val18 = 18, - #[doc = "19: QDC0_POS_MATCH0 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN0 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN1 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN2 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN3 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN4 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN5 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN6 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN7 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN8 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN9 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN10 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN11 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT0 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT1 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT2 input is selected"] - Val39 = 39, - #[doc = "40: AOI1_OUT3 input is selected"] - Val40 = 40, - #[doc = "45: CTimer3_MAT2 input is selected"] - Val45 = 45, - #[doc = "46: CTimer3_MAT3 input is selected"] - Val46 = 46, - #[doc = "47: CTimer4_MAT2 input is selected"] - Val47 = 47, - #[doc = "48: CTimer4_MAT3 input is selected"] - Val48 = 48, - #[doc = "49: QDC1_CMP_FLAG0 input is selected"] - Val49 = 49, - #[doc = "50: QDC1_CMP_FLAG1 input is selected"] - Val50 = 50, - #[doc = "51: QDC1_CMP_FLAG2 input is selected"] - Val51 = 51, - #[doc = "52: QDC1_CMP_FLAG3 input is selected"] - Val52 = 52, - #[doc = "53: QDC1_POS_MATCH0 input is selected"] - Val53 = 53, - #[doc = "54: PWM0_SM0_MUX_TRIG0 input is selected"] - Val54 = 54, - #[doc = "55: PWM0_SM0_MUX_TRIG1 input is selected"] - Val55 = 55, - #[doc = "56: PWM0_SM1_MUX_TRIG0 input is selected"] - Val56 = 56, - #[doc = "57: PWM0_SM1_MUX_TRIG1 input is selected"] - Val57 = 57, - #[doc = "58: PWM0_SM2_MUX_TRIG0 input is selected"] - Val58 = 58, - #[doc = "59: PWM0_SM2_MUX_TRIG1 input is selected"] - Val59 = 59, - #[doc = "60: PWM0_SM3_MUX_TRIG0 input is selected"] - Val60 = 60, - #[doc = "61: PWM0_SM3_MUX_TRIG1 input is selected"] - Val61 = 61, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - EXTSYNC input connections for PWM0"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - 9 => Some(Trigin::Val9), - 10 => Some(Trigin::Val10), - 11 => Some(Trigin::Val11), - 12 => Some(Trigin::Val12), - 13 => Some(Trigin::Val13), - 14 => Some(Trigin::Val14), - 15 => Some(Trigin::Val15), - 16 => Some(Trigin::Val16), - 17 => Some(Trigin::Val17), - 18 => Some(Trigin::Val18), - 19 => Some(Trigin::Val19), - 20 => Some(Trigin::Val20), - 21 => Some(Trigin::Val21), - 22 => Some(Trigin::Val22), - 23 => Some(Trigin::Val23), - 24 => Some(Trigin::Val24), - 25 => Some(Trigin::Val25), - 26 => Some(Trigin::Val26), - 27 => Some(Trigin::Val27), - 28 => Some(Trigin::Val28), - 29 => Some(Trigin::Val29), - 30 => Some(Trigin::Val30), - 31 => Some(Trigin::Val31), - 32 => Some(Trigin::Val32), - 33 => Some(Trigin::Val33), - 34 => Some(Trigin::Val34), - 35 => Some(Trigin::Val35), - 36 => Some(Trigin::Val36), - 37 => Some(Trigin::Val37), - 38 => Some(Trigin::Val38), - 39 => Some(Trigin::Val39), - 40 => Some(Trigin::Val40), - 45 => Some(Trigin::Val45), - 46 => Some(Trigin::Val46), - 47 => Some(Trigin::Val47), - 48 => Some(Trigin::Val48), - 49 => Some(Trigin::Val49), - 50 => Some(Trigin::Val50), - 51 => Some(Trigin::Val51), - 52 => Some(Trigin::Val52), - 53 => Some(Trigin::Val53), - 54 => Some(Trigin::Val54), - 55 => Some(Trigin::Val55), - 56 => Some(Trigin::Val56), - 57 => Some(Trigin::Val57), - 58 => Some(Trigin::Val58), - 59 => Some(Trigin::Val59), - 60 => Some(Trigin::Val60), - 61 => Some(Trigin::Val61), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Trigin::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Trigin::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Trigin::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Trigin::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Trigin::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Trigin::Val14 - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Trigin::Val15 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Trigin::Val16 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Trigin::Val17 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Trigin::Val18 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Trigin::Val19 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Trigin::Val20 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Trigin::Val21 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Trigin::Val22 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Trigin::Val23 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Trigin::Val24 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Trigin::Val25 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Trigin::Val26 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Trigin::Val27 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Trigin::Val28 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Trigin::Val29 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Trigin::Val30 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Trigin::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Trigin::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Trigin::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Trigin::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Trigin::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Trigin::Val36 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Trigin::Val37 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Trigin::Val38 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Trigin::Val39 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Trigin::Val40 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Trigin::Val45 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Trigin::Val46 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Trigin::Val47 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Trigin::Val48 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Trigin::Val49 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Trigin::Val50 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Trigin::Val51 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Trigin::Val52 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Trigin::Val53 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Trigin::Val54 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Trigin::Val55 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Trigin::Val56 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Trigin::Val57 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Trigin::Val58 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Trigin::Val59 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Trigin::Val60 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Trigin::Val61 - } -} -#[doc = "Field `TRIGIN` writer - EXTSYNC input connections for PWM0"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 6, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Trigin::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Trigin::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Trigin::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Trigin::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Trigin::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Trigin::Val14) - } - #[doc = "QDC0_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Trigin::Val15) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Trigin::Val16) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Trigin::Val17) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Trigin::Val18) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Trigin::Val19) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Trigin::Val20) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Trigin::Val21) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Trigin::Val22) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Trigin::Val23) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Trigin::Val24) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Trigin::Val25) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Trigin::Val26) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Trigin::Val27) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Trigin::Val28) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Trigin::Val29) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Trigin::Val30) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Trigin::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Trigin::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Trigin::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Trigin::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Trigin::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Trigin::Val36) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Trigin::Val37) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Trigin::Val38) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Trigin::Val39) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Trigin::Val40) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Trigin::Val45) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Trigin::Val46) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Trigin::Val47) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Trigin::Val48) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Trigin::Val49) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Trigin::Val50) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Trigin::Val51) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Trigin::Val52) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Trigin::Val53) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Trigin::Val54) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Trigin::Val55) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Trigin::Val56) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Trigin::Val57) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Trigin::Val58) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Trigin::Val59) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Trigin::Val60) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Trigin::Val61) - } -} -impl R { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - EXTSYNC input connections for PWM0"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_extsync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_extsync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexPwm1Sm3ExtsyncSpec; -impl crate::RegisterSpec for FlexPwm1Sm3ExtsyncSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flex_pwm1_sm3_extsync::R`](R) reader structure"] -impl crate::Readable for FlexPwm1Sm3ExtsyncSpec {} -#[doc = "`write(|w| ..)` method takes [`flex_pwm1_sm3_extsync::W`](W) writer structure"] -impl crate::Writable for FlexPwm1Sm3ExtsyncSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FlexPWM1_SM3_EXTSYNC to value 0x3f"] -impl crate::Resettable for FlexPwm1Sm3ExtsyncSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/flexio_trig.rs b/mcxa276-pac/src/inputmux0/flexio_trig.rs deleted file mode 100644 index dc777d350..000000000 --- a/mcxa276-pac/src/inputmux0/flexio_trig.rs +++ /dev/null @@ -1,1094 +0,0 @@ -#[doc = "Register `FLEXIO_TRIG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `FLEXIO_TRIG[%s]` writer"] -pub type W = crate::W; -#[doc = "Input number for FlexIO0.\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: AOI0_OUT0 input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT1 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT2 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT3 input is selected"] - Val4 = 4, - #[doc = "5: ADC0_tcomp\\[0\\] input is selected"] - Val5 = 5, - #[doc = "6: ADC0_tcomp\\[1\\] input is selected"] - Val6 = 6, - #[doc = "7: ADC0_tcomp\\[2\\] input is selected"] - Val7 = 7, - #[doc = "8: ADC0_tcomp\\[3\\] input is selected"] - Val8 = 8, - #[doc = "9: CMP0_OUT input is selected"] - Val9 = 9, - #[doc = "10: CMP1_OUT input is selected"] - Val10 = 10, - #[doc = "11: CMP2_OUT input is selected"] - Val11 = 11, - #[doc = "12: CTimer0_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer0_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer1_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: CTimer1_MAT2 input is selected"] - Val15 = 15, - #[doc = "16: CTimer2_MAT1 input is selected"] - Val16 = 16, - #[doc = "17: CTimer2_MAT2 input is selected"] - Val17 = 17, - #[doc = "18: LPTMR0 input is selected"] - Val18 = 18, - #[doc = "20: PWM0_SM0_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM1_MUX_TRIG0 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM2_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG0 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: GPIO0 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO1 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: GPIO2 Pin Event Trig 0 input is selected"] - Val34 = 34, - #[doc = "35: GPIO3 Pin Event Trig 0 input is selected"] - Val35 = 35, - #[doc = "36: GPIO4 Pin Event Trig 0 input is selected"] - Val36 = 36, - #[doc = "37: WUU input is selected"] - Val37 = 37, - #[doc = "38: LPI2C0 Master End of Packet"] - Val38 = 38, - #[doc = "39: LPI2C0 Slave End of Packet"] - Val39 = 39, - #[doc = "40: LPI2C1 Master End of Packet"] - Val40 = 40, - #[doc = "41: LPI2C1 Slave End of Packet"] - Val41 = 41, - #[doc = "42: LPSPI0 End of Frame"] - Val42 = 42, - #[doc = "43: LPSPI0 Received Data Word"] - Val43 = 43, - #[doc = "44: LPSPI1 End of Frame"] - Val44 = 44, - #[doc = "45: LPSPI1 Received Data Word"] - Val45 = 45, - #[doc = "46: LPUART0 Received Data Word"] - Val46 = 46, - #[doc = "47: LPUART0 Transmitted Data Word"] - Val47 = 47, - #[doc = "48: LPUART0 Receive Line Idle"] - Val48 = 48, - #[doc = "49: LPUART1 Received Data Word"] - Val49 = 49, - #[doc = "50: LPUART1 Transmitted Data Word"] - Val50 = 50, - #[doc = "51: LPUART1 Receive Line Idle"] - Val51 = 51, - #[doc = "52: LPUART2 Received Data Word"] - Val52 = 52, - #[doc = "53: LPUART2 Transmitted Data Word"] - Val53 = 53, - #[doc = "54: LPUART2 Receive Line Idle"] - Val54 = 54, - #[doc = "55: LPUART3 Received Data Word"] - Val55 = 55, - #[doc = "56: LPUART3 Transmitted Data Word"] - Val56 = 56, - #[doc = "57: LPUART3 Receive Line Idle"] - Val57 = 57, - #[doc = "58: LPUART4 Received Data Word"] - Val58 = 58, - #[doc = "59: LPUART4 Transmitted Data Word"] - Val59 = 59, - #[doc = "60: LPUART4 Receive Line Idle"] - Val60 = 60, - #[doc = "61: AOI1_OUT0 input is selected"] - Val61 = 61, - #[doc = "62: AOI1_OUT1 input is selected"] - Val62 = 62, - #[doc = "63: AOI1_OUT2 input is selected"] - Val63 = 63, - #[doc = "64: AOI1_OUT3 input is selected"] - Val64 = 64, - #[doc = "65: ADC1_tcomp\\[0\\] input is selected"] - Val65 = 65, - #[doc = "66: ADC1_tcomp\\[1\\] input is selected"] - Val66 = 66, - #[doc = "67: ADC1_tcomp\\[2\\] input is selected"] - Val67 = 67, - #[doc = "68: ADC1_tcomp\\[3\\] input is selected"] - Val68 = 68, - #[doc = "69: CTimer3_MAT2 input is selected"] - Val69 = 69, - #[doc = "70: CTimer3_MAT3 input is selected"] - Val70 = 70, - #[doc = "71: CTimer4_MAT2 input is selected"] - Val71 = 71, - #[doc = "72: CTimer4_MAT3 input is selected"] - Val72 = 72, - #[doc = "73: PWM1_SM0_MUX_TRIG0 input is selected"] - Val73 = 73, - #[doc = "74: PWM1_SM1_MUX_TRIG0 input is selected"] - Val74 = 74, - #[doc = "75: PWM1_SM2_MUX_TRIG0 input is selected"] - Val75 = 75, - #[doc = "76: PWM1_SM3_MUX_TRIG0 input is selected"] - Val76 = 76, - #[doc = "77: LPI2C2 Master End of Packet"] - Val77 = 77, - #[doc = "78: LPI2C2 Slave End of Packet"] - Val78 = 78, - #[doc = "79: LPI2C3 Master End of Packet"] - Val79 = 79, - #[doc = "80: LPI2C3 Slave End of Packet"] - Val80 = 80, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for FlexIO0."] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "LPI2C0 Master End of Packet"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "LPI2C0 Slave End of Packet"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "LPI2C1 Master End of Packet"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "LPI2C1 Slave End of Packet"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "LPSPI0 End of Frame"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "LPSPI0 Received Data Word"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "LPSPI1 End of Frame"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "LPSPI1 Received Data Word"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "LPUART0 Received Data Word"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "LPUART0 Transmitted Data Word"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPUART0 Receive Line Idle"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPUART1 Received Data Word"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPUART1 Transmitted Data Word"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPUART1 Receive Line Idle"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPUART2 Received Data Word"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPUART2 Transmitted Data Word"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPUART2 Receive Line Idle"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPUART3 Received Data Word"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART3 Transmitted Data Word"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART3 Receive Line Idle"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART4 Received Data Word"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART4 Transmitted Data Word"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART4 Receive Line Idle"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "LPI2C2 Master End of Packet"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "LPI2C2 Slave End of Packet"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "LPI2C3 Master End of Packet"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "LPI2C3 Slave End of Packet"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } -} -#[doc = "Field `INP` writer - Input number for FlexIO0."] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "ADC0_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "ADC0_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "ADC0_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "LPI2C0 Master End of Packet"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "LPI2C0 Slave End of Packet"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "LPI2C1 Master End of Packet"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "LPI2C1 Slave End of Packet"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "LPSPI0 End of Frame"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "LPSPI0 Received Data Word"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "LPSPI1 End of Frame"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "LPSPI1 Received Data Word"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "LPUART0 Received Data Word"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "LPUART0 Transmitted Data Word"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPUART0 Receive Line Idle"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPUART1 Received Data Word"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPUART1 Transmitted Data Word"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPUART1 Receive Line Idle"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPUART2 Received Data Word"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPUART2 Transmitted Data Word"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPUART2 Receive Line Idle"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPUART3 Received Data Word"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART3 Transmitted Data Word"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART3 Receive Line Idle"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART4 Received Data Word"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART4 Transmitted Data Word"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART4 Receive Line Idle"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "LPI2C2 Master End of Packet"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "LPI2C2 Slave End of Packet"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "LPI2C3 Master End of Packet"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "LPI2C3 Slave End of Packet"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for FlexIO0."] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for FlexIO0."] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "FlexIO Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flexio_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexio_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FlexioTrigSpec; -impl crate::RegisterSpec for FlexioTrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`flexio_trig::R`](R) reader structure"] -impl crate::Readable for FlexioTrigSpec {} -#[doc = "`write(|w| ..)` method takes [`flexio_trig::W`](W) writer structure"] -impl crate::Writable for FlexioTrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FLEXIO_TRIG[%s] to value 0x7f"] -impl crate::Resettable for FlexioTrigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/freqmeas_ref.rs b/mcxa276-pac/src/inputmux0/freqmeas_ref.rs deleted file mode 100644 index 709671340..000000000 --- a/mcxa276-pac/src/inputmux0/freqmeas_ref.rs +++ /dev/null @@ -1,418 +0,0 @@ -#[doc = "Register `FREQMEAS_REF` reader"] -pub type R = crate::R; -#[doc = "Register `FREQMEAS_REF` writer"] -pub type W = crate::W; -#[doc = "Clock source number (binary value) for frequency measure function target clock.\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: clk_in input is selected"] - Val1 = 1, - #[doc = "2: FRO_OSC_12M input is selected"] - Val2 = 2, - #[doc = "3: fro_hf_div input is selected"] - Val3 = 3, - #[doc = "5: clk_16k\\[1\\] input is selected"] - Val5 = 5, - #[doc = "6: SLOW_CLK input is selected"] - Val6 = 6, - #[doc = "7: FREQME_CLK_IN0 input is selected"] - Val7 = 7, - #[doc = "8: FREQME_CLK_IN1 input is selected input is selected"] - Val8 = 8, - #[doc = "9: AOI0_OUT0 input is selected"] - Val9 = 9, - #[doc = "10: AOI0_OUT1"] - Val10 = 10, - #[doc = "11: PWM0_SM0_MUX_TRIG0"] - Val11 = 11, - #[doc = "12: PWM0_SM0_MUX_TRIG1"] - Val12 = 12, - #[doc = "13: PWM0_SM1_MUX_TRIG0"] - Val13 = 13, - #[doc = "14: PWM0_SM1_MUX_TRIG1"] - Val14 = 14, - #[doc = "15: PWM0_SM2_MUX_TRIG0"] - Val15 = 15, - #[doc = "16: PWM0_SM2_MUX_TRIG1"] - Val16 = 16, - #[doc = "17: PWM0_SM3_MUX_TRIG0"] - Val17 = 17, - #[doc = "18: PWM0_SM3_MUX_TRIG1"] - Val18 = 18, - #[doc = "32: AOI1_OUT0 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT1 input is selected"] - Val33 = 33, - #[doc = "34: PWM1_SM0_MUX_TRIG0 input is selected"] - Val34 = 34, - #[doc = "35: PWM1_SM0_MUX_TRIG1 input is selected"] - Val35 = 35, - #[doc = "36: PWM1_SM1_MUX_TRIG0 input is selected"] - Val36 = 36, - #[doc = "37: PWM1_SM1_MUX_TRIG1 input is selected"] - Val37 = 37, - #[doc = "38: PWM1_SM2_MUX_TRIG0 input is selected"] - Val38 = 38, - #[doc = "39: PWM1_SM2_MUX_TRIG1 input is selected"] - Val39 = 39, - #[doc = "40: PWM1_SM3_MUX_TRIG0 input is selected"] - Val40 = 40, - #[doc = "41: PWM1_SM3_MUX_TRIG1 input is selected"] - Val41 = 41, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Clock source number (binary value) for frequency measure function target clock."] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - _ => None, - } - } - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "FRO_OSC_12M input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "fro_hf_div input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "SLOW_CLK input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "FREQME_CLK_IN0 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "FREQME_CLK_IN1 input is selected input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "AOI0_OUT1"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "PWM0_SM0_MUX_TRIG0"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "PWM0_SM0_MUX_TRIG1"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "PWM0_SM1_MUX_TRIG0"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "PWM0_SM1_MUX_TRIG1"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM2_MUX_TRIG0"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "PWM0_SM2_MUX_TRIG1"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM3_MUX_TRIG0"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM3_MUX_TRIG1"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } -} -#[doc = "Field `INP` writer - Clock source number (binary value) for frequency measure function target clock."] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "FRO_OSC_12M input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "fro_hf_div input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "SLOW_CLK input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "FREQME_CLK_IN0 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "FREQME_CLK_IN1 input is selected input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "AOI0_OUT1"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "PWM0_SM0_MUX_TRIG0"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "PWM0_SM0_MUX_TRIG1"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "PWM0_SM1_MUX_TRIG0"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "PWM0_SM1_MUX_TRIG1"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM2_MUX_TRIG0"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "PWM0_SM2_MUX_TRIG1"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM3_MUX_TRIG0"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM3_MUX_TRIG1"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } -} -impl R { - #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_ref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_ref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FreqmeasRefSpec; -impl crate::RegisterSpec for FreqmeasRefSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`freqmeas_ref::R`](R) reader structure"] -impl crate::Readable for FreqmeasRefSpec {} -#[doc = "`write(|w| ..)` method takes [`freqmeas_ref::W`](W) writer structure"] -impl crate::Writable for FreqmeasRefSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FREQMEAS_REF to value 0x3f"] -impl crate::Resettable for FreqmeasRefSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/freqmeas_tar.rs b/mcxa276-pac/src/inputmux0/freqmeas_tar.rs deleted file mode 100644 index 38638c330..000000000 --- a/mcxa276-pac/src/inputmux0/freqmeas_tar.rs +++ /dev/null @@ -1,418 +0,0 @@ -#[doc = "Register `FREQMEAS_TAR` reader"] -pub type R = crate::R; -#[doc = "Register `FREQMEAS_TAR` writer"] -pub type W = crate::W; -#[doc = "Clock source number (binary value) for frequency measure function target clock.\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: clk_in input is selected"] - Val1 = 1, - #[doc = "2: FRO_OSC_12M input is selected"] - Val2 = 2, - #[doc = "3: fro_hf_div input is selected"] - Val3 = 3, - #[doc = "5: clk_16k\\[1\\] input is selected"] - Val5 = 5, - #[doc = "6: SLOW_CLK input is selected"] - Val6 = 6, - #[doc = "7: FREQME_CLK_IN0 input is selected"] - Val7 = 7, - #[doc = "8: FREQME_CLK_IN1 input is selected input is selected"] - Val8 = 8, - #[doc = "9: AOI0_OUT0 input is selected"] - Val9 = 9, - #[doc = "10: AOI0_OUT1"] - Val10 = 10, - #[doc = "11: PWM0_SM0_MUX_TRIG0"] - Val11 = 11, - #[doc = "12: PWM0_SM0_MUX_TRIG1"] - Val12 = 12, - #[doc = "13: PWM0_SM1_MUX_TRIG0"] - Val13 = 13, - #[doc = "14: PWM0_SM1_MUX_TRIG1"] - Val14 = 14, - #[doc = "15: PWM0_SM2_MUX_TRIG0"] - Val15 = 15, - #[doc = "16: PWM0_SM2_MUX_TRIG1"] - Val16 = 16, - #[doc = "17: PWM0_SM3_MUX_TRIG0"] - Val17 = 17, - #[doc = "18: PWM0_SM3_MUX_TRIG1"] - Val18 = 18, - #[doc = "32: AOI1_OUT0 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT1 input is selected"] - Val33 = 33, - #[doc = "34: PWM1_SM0_MUX_TRIG0 input is selected"] - Val34 = 34, - #[doc = "35: PWM1_SM0_MUX_TRIG1 input is selected"] - Val35 = 35, - #[doc = "36: PWM1_SM1_MUX_TRIG0 input is selected"] - Val36 = 36, - #[doc = "37: PWM1_SM1_MUX_TRIG1 input is selected"] - Val37 = 37, - #[doc = "38: PWM1_SM2_MUX_TRIG0 input is selected"] - Val38 = 38, - #[doc = "39: PWM1_SM2_MUX_TRIG1 input is selected"] - Val39 = 39, - #[doc = "40: PWM1_SM3_MUX_TRIG0 input is selected"] - Val40 = 40, - #[doc = "41: PWM1_SM3_MUX_TRIG1 input is selected"] - Val41 = 41, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Clock source number (binary value) for frequency measure function target clock."] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - _ => None, - } - } - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "FRO_OSC_12M input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "fro_hf_div input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "SLOW_CLK input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "FREQME_CLK_IN0 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "FREQME_CLK_IN1 input is selected input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "AOI0_OUT1"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "PWM0_SM0_MUX_TRIG0"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "PWM0_SM0_MUX_TRIG1"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "PWM0_SM1_MUX_TRIG0"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "PWM0_SM1_MUX_TRIG1"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM2_MUX_TRIG0"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "PWM0_SM2_MUX_TRIG1"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM3_MUX_TRIG0"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM3_MUX_TRIG1"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } -} -#[doc = "Field `INP` writer - Clock source number (binary value) for frequency measure function target clock."] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "FRO_OSC_12M input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "fro_hf_div input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "SLOW_CLK input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "FREQME_CLK_IN0 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "FREQME_CLK_IN1 input is selected input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "AOI0_OUT1"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "PWM0_SM0_MUX_TRIG0"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "PWM0_SM0_MUX_TRIG1"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "PWM0_SM1_MUX_TRIG0"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "PWM0_SM1_MUX_TRIG1"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM2_MUX_TRIG0"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "PWM0_SM2_MUX_TRIG1"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM3_MUX_TRIG0"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM3_MUX_TRIG1"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } -} -impl R { - #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Clock source number (binary value) for frequency measure function target clock."] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FreqmeasTarSpec; -impl crate::RegisterSpec for FreqmeasTarSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`freqmeas_tar::R`](R) reader structure"] -impl crate::Readable for FreqmeasTarSpec {} -#[doc = "`write(|w| ..)` method takes [`freqmeas_tar::W`](W) writer structure"] -impl crate::Writable for FreqmeasTarSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FREQMEAS_TAR to value 0x3f"] -impl crate::Resettable for FreqmeasTarSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpi2c0_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c0_trig.rs deleted file mode 100644 index a2e9bf3c7..000000000 --- a/mcxa276-pac/src/inputmux0/lpi2c0_trig.rs +++ /dev/null @@ -1,587 +0,0 @@ -#[doc = "Register `LPI2C0_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `LPI2C0_TRIG` writer"] -pub type W = crate::W; -#[doc = "LPI2C0 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "35: CTimer3_MAT2 input is selected"] - Val35 = 35, - #[doc = "36: CTimer3_MAT3 input is selected"] - Val36 = 36, - #[doc = "37: CTimer4_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer4_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: FlexIO CH0 input is selected"] - Val39 = 39, - #[doc = "40: FlexIO CH1 input is selected"] - Val40 = 40, - #[doc = "41: FlexIO CH2 input is selected"] - Val41 = 41, - #[doc = "42: FlexIO CH3 input is selected"] - Val42 = 42, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPI2C0 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } -} -#[doc = "Field `INP` writer - LPI2C0 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } -} -impl R { - #[doc = "Bits 0:5 - LPI2C0 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPI2C0 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPI2C0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpi2c0TrigSpec; -impl crate::RegisterSpec for Lpi2c0TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpi2c0_trig::R`](R) reader structure"] -impl crate::Readable for Lpi2c0TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`lpi2c0_trig::W`](W) writer structure"] -impl crate::Writable for Lpi2c0TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPI2C0_TRIG to value 0x3f"] -impl crate::Resettable for Lpi2c0TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpi2c1_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c1_trig.rs deleted file mode 100644 index f095c6b5d..000000000 --- a/mcxa276-pac/src/inputmux0/lpi2c1_trig.rs +++ /dev/null @@ -1,587 +0,0 @@ -#[doc = "Register `LPI2C1_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `LPI2C1_TRIG` writer"] -pub type W = crate::W; -#[doc = "LPI2C1 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "35: CTimer3_MAT2 input is selected"] - Val35 = 35, - #[doc = "36: CTimer3_MAT3 input is selected"] - Val36 = 36, - #[doc = "37: CTimer4_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer4_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: FlexIO CH0 input is selected"] - Val39 = 39, - #[doc = "40: FlexIO CH1 input is selected"] - Val40 = 40, - #[doc = "41: FlexIO CH2 input is selected"] - Val41 = 41, - #[doc = "42: FlexIO CH3 input is selected"] - Val42 = 42, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPI2C1 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } -} -#[doc = "Field `INP` writer - LPI2C1 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } -} -impl R { - #[doc = "Bits 0:5 - LPI2C1 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPI2C1 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPI2C1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpi2c1TrigSpec; -impl crate::RegisterSpec for Lpi2c1TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpi2c1_trig::R`](R) reader structure"] -impl crate::Readable for Lpi2c1TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`lpi2c1_trig::W`](W) writer structure"] -impl crate::Writable for Lpi2c1TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPI2C1_TRIG to value 0x3f"] -impl crate::Resettable for Lpi2c1TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpi2c2_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c2_trig.rs deleted file mode 100644 index 5e402bcc8..000000000 --- a/mcxa276-pac/src/inputmux0/lpi2c2_trig.rs +++ /dev/null @@ -1,587 +0,0 @@ -#[doc = "Register `LPI2C2_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `LPI2C2_TRIG` writer"] -pub type W = crate::W; -#[doc = "LPI2C2 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "35: CTimer3_MAT2 input is selected"] - Val35 = 35, - #[doc = "36: CTimer3_MAT3 input is selected"] - Val36 = 36, - #[doc = "37: CTimer4_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer4_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: FlexIO CH0 input is selected"] - Val39 = 39, - #[doc = "40: FlexIO CH1 input is selected"] - Val40 = 40, - #[doc = "41: FlexIO CH2 input is selected"] - Val41 = 41, - #[doc = "42: FlexIO CH3 input is selected"] - Val42 = 42, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPI2C2 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } -} -#[doc = "Field `INP` writer - LPI2C2 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } -} -impl R { - #[doc = "Bits 0:5 - LPI2C2 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPI2C2 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPI2C2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c2_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c2_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpi2c2TrigSpec; -impl crate::RegisterSpec for Lpi2c2TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpi2c2_trig::R`](R) reader structure"] -impl crate::Readable for Lpi2c2TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`lpi2c2_trig::W`](W) writer structure"] -impl crate::Writable for Lpi2c2TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPI2C2_TRIG to value 0x3f"] -impl crate::Resettable for Lpi2c2TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpi2c3_trig.rs b/mcxa276-pac/src/inputmux0/lpi2c3_trig.rs deleted file mode 100644 index e674d2cc2..000000000 --- a/mcxa276-pac/src/inputmux0/lpi2c3_trig.rs +++ /dev/null @@ -1,587 +0,0 @@ -#[doc = "Register `LPI2C3_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `LPI2C3_TRIG` writer"] -pub type W = crate::W; -#[doc = "LPI2C3 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT0 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT1 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT0 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT1 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT0 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT1 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "35: CTimer3_MAT2 input is selected"] - Val35 = 35, - #[doc = "36: CTimer3_MAT3 input is selected"] - Val36 = 36, - #[doc = "37: CTimer4_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer4_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: FlexIO CH0 input is selected"] - Val39 = 39, - #[doc = "40: FlexIO CH1 input is selected"] - Val40 = 40, - #[doc = "41: FlexIO CH2 input is selected"] - Val41 = 41, - #[doc = "42: FlexIO CH3 input is selected"] - Val42 = 42, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPI2C3 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } -} -#[doc = "Field `INP` writer - LPI2C3 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT0 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT0 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } -} -impl R { - #[doc = "Bits 0:5 - LPI2C3 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPI2C3 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPI2C3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c3_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c3_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpi2c3TrigSpec; -impl crate::RegisterSpec for Lpi2c3TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpi2c3_trig::R`](R) reader structure"] -impl crate::Readable for Lpi2c3TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`lpi2c3_trig::W`](W) writer structure"] -impl crate::Writable for Lpi2c3TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPI2C3_TRIG to value 0x3f"] -impl crate::Resettable for Lpi2c3TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpspi0_trig.rs b/mcxa276-pac/src/inputmux0/lpspi0_trig.rs deleted file mode 100644 index b40704410..000000000 --- a/mcxa276-pac/src/inputmux0/lpspi0_trig.rs +++ /dev/null @@ -1,587 +0,0 @@ -#[doc = "Register `LPSPI0_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `LPSPI0_TRIG` writer"] -pub type W = crate::W; -#[doc = "LPSPI0 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT1 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT2 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT1 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT2 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT1 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT2 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "35: CTimer3_MAT2 input is selected"] - Val35 = 35, - #[doc = "36: CTimer3_MAT3 input is selected"] - Val36 = 36, - #[doc = "37: CTimer4_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer4_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: FlexIO CH0 input is selected"] - Val39 = 39, - #[doc = "40: FlexIO CH1 input is selected"] - Val40 = 40, - #[doc = "41: FlexIO CH2 input is selected"] - Val41 = 41, - #[doc = "42: FlexIO CH3 input is selected"] - Val42 = 42, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPSPI0 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } -} -#[doc = "Field `INP` writer - LPSPI0 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } -} -impl R { - #[doc = "Bits 0:5 - LPSPI0 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPSPI0 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPSPI0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpspi0TrigSpec; -impl crate::RegisterSpec for Lpspi0TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpspi0_trig::R`](R) reader structure"] -impl crate::Readable for Lpspi0TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`lpspi0_trig::W`](W) writer structure"] -impl crate::Writable for Lpspi0TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPSPI0_TRIG to value 0x3f"] -impl crate::Resettable for Lpspi0TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpspi1_trig.rs b/mcxa276-pac/src/inputmux0/lpspi1_trig.rs deleted file mode 100644 index 39708509c..000000000 --- a/mcxa276-pac/src/inputmux0/lpspi1_trig.rs +++ /dev/null @@ -1,587 +0,0 @@ -#[doc = "Register `LPSPI1_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `LPSPI1_TRIG` writer"] -pub type W = crate::W; -#[doc = "LPSPI1 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT1 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT2 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT1 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT2 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT1 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT2 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: GPIO0 Pin Event Trig 0 input is selected"] - Val25 = 25, - #[doc = "26: GPIO1 Pin Event Trig 0 input is selected"] - Val26 = 26, - #[doc = "27: GPIO2 Pin Event Trig 0 input is selected"] - Val27 = 27, - #[doc = "28: GPIO3 Pin Event Trig 0 input is selected"] - Val28 = 28, - #[doc = "29: GPIO4 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: WUU input is selected"] - Val30 = 30, - #[doc = "31: AOI1_OUT0 input is selected"] - Val31 = 31, - #[doc = "32: AOI1_OUT1 input is selected"] - Val32 = 32, - #[doc = "33: AOI1_OUT2 input is selected"] - Val33 = 33, - #[doc = "34: AOI1_OUT3 input is selected"] - Val34 = 34, - #[doc = "35: CTimer3_MAT2 input is selected"] - Val35 = 35, - #[doc = "36: CTimer3_MAT3 input is selected"] - Val36 = 36, - #[doc = "37: CTimer4_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer4_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: FlexIO CH0 input is selected"] - Val39 = 39, - #[doc = "40: FlexIO CH1 input is selected"] - Val40 = 40, - #[doc = "41: FlexIO CH2 input is selected"] - Val41 = 41, - #[doc = "42: FlexIO CH3 input is selected"] - Val42 = 42, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPSPI1 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } -} -#[doc = "Field `INP` writer - LPSPI1 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "WUU input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } -} -impl R { - #[doc = "Bits 0:5 - LPSPI1 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPSPI1 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPSPI1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpspi1TrigSpec; -impl crate::RegisterSpec for Lpspi1TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpspi1_trig::R`](R) reader structure"] -impl crate::Readable for Lpspi1TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`lpspi1_trig::W`](W) writer structure"] -impl crate::Writable for Lpspi1TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPSPI1_TRIG to value 0x3f"] -impl crate::Resettable for Lpspi1TrigSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpuart0.rs b/mcxa276-pac/src/inputmux0/lpuart0.rs deleted file mode 100644 index 19d441388..000000000 --- a/mcxa276-pac/src/inputmux0/lpuart0.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `LPUART0` reader"] -pub type R = crate::R; -#[doc = "Register `LPUART0` writer"] -pub type W = crate::W; -#[doc = "LPUART0 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN8 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN9 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN10 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN11 input is selected"] - Val28 = 28, - #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] - Val31 = 31, - #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: WUU selected"] - Val34 = 34, - #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT1 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT2 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT3 input is selected"] - Val39 = 39, - #[doc = "40: CTimer3_MAT2 input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT3 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT2 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT3 input is selected"] - Val43 = 43, - #[doc = "44: FlexIO CH0 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH1 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH2 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH3 input is selected"] - Val47 = 47, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPUART0 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } -} -#[doc = "Field `INP` writer - LPUART0 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } -} -impl R { - #[doc = "Bits 0:5 - LPUART0 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPUART0 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPUART0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpuart0Spec; -impl crate::RegisterSpec for Lpuart0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpuart0::R`](R) reader structure"] -impl crate::Readable for Lpuart0Spec {} -#[doc = "`write(|w| ..)` method takes [`lpuart0::W`](W) writer structure"] -impl crate::Writable for Lpuart0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPUART0 to value 0x3f"] -impl crate::Resettable for Lpuart0Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpuart1.rs b/mcxa276-pac/src/inputmux0/lpuart1.rs deleted file mode 100644 index 1564d3534..000000000 --- a/mcxa276-pac/src/inputmux0/lpuart1.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `LPUART1` reader"] -pub type R = crate::R; -#[doc = "Register `LPUART1` writer"] -pub type W = crate::W; -#[doc = "LPUART1 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN8 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN9 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN10 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN11 input is selected"] - Val28 = 28, - #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] - Val31 = 31, - #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: WUU selected"] - Val34 = 34, - #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT1 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT2 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT3 input is selected"] - Val39 = 39, - #[doc = "40: CTimer3_MAT2 input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT3 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT2 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT3 input is selected"] - Val43 = 43, - #[doc = "44: FlexIO CH0 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH1 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH2 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH3 input is selected"] - Val47 = 47, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPUART1 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } -} -#[doc = "Field `INP` writer - LPUART1 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } -} -impl R { - #[doc = "Bits 0:5 - LPUART1 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPUART1 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPUART1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpuart1Spec; -impl crate::RegisterSpec for Lpuart1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpuart1::R`](R) reader structure"] -impl crate::Readable for Lpuart1Spec {} -#[doc = "`write(|w| ..)` method takes [`lpuart1::W`](W) writer structure"] -impl crate::Writable for Lpuart1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPUART1 to value 0x3f"] -impl crate::Resettable for Lpuart1Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpuart2.rs b/mcxa276-pac/src/inputmux0/lpuart2.rs deleted file mode 100644 index b4421f6e3..000000000 --- a/mcxa276-pac/src/inputmux0/lpuart2.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `LPUART2` reader"] -pub type R = crate::R; -#[doc = "Register `LPUART2` writer"] -pub type W = crate::W; -#[doc = "LPUART2 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN8 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN9 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN10 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN11 input is selected"] - Val28 = 28, - #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] - Val31 = 31, - #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: WUU selected"] - Val34 = 34, - #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT1 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT2 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT3 input is selected"] - Val39 = 39, - #[doc = "40: CTimer3_MAT2 input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT3 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT2 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT3 input is selected"] - Val43 = 43, - #[doc = "44: FlexIO CH0 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH1 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH2 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH3 input is selected"] - Val47 = 47, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPUART2 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } -} -#[doc = "Field `INP` writer - LPUART2 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } -} -impl R { - #[doc = "Bits 0:5 - LPUART2 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPUART2 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPUART2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpuart2Spec; -impl crate::RegisterSpec for Lpuart2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpuart2::R`](R) reader structure"] -impl crate::Readable for Lpuart2Spec {} -#[doc = "`write(|w| ..)` method takes [`lpuart2::W`](W) writer structure"] -impl crate::Writable for Lpuart2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPUART2 to value 0x3f"] -impl crate::Resettable for Lpuart2Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpuart3.rs b/mcxa276-pac/src/inputmux0/lpuart3.rs deleted file mode 100644 index e42bf4d44..000000000 --- a/mcxa276-pac/src/inputmux0/lpuart3.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `LPUART3` reader"] -pub type R = crate::R; -#[doc = "Register `LPUART3` writer"] -pub type W = crate::W; -#[doc = "LPUART3 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN8 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN9 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN10 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN11 input is selected"] - Val28 = 28, - #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] - Val31 = 31, - #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: WUU selected"] - Val34 = 34, - #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT1 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT2 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT3 input is selected"] - Val39 = 39, - #[doc = "40: CTimer3_MAT2 input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT3 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT2 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT3 input is selected"] - Val43 = 43, - #[doc = "44: FlexIO CH0 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH1 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH2 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH3 input is selected"] - Val47 = 47, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPUART3 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } -} -#[doc = "Field `INP` writer - LPUART3 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } -} -impl R { - #[doc = "Bits 0:5 - LPUART3 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPUART3 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPUART3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpuart3Spec; -impl crate::RegisterSpec for Lpuart3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpuart3::R`](R) reader structure"] -impl crate::Readable for Lpuart3Spec {} -#[doc = "`write(|w| ..)` method takes [`lpuart3::W`](W) writer structure"] -impl crate::Writable for Lpuart3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPUART3 to value 0x3f"] -impl crate::Resettable for Lpuart3Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpuart4.rs b/mcxa276-pac/src/inputmux0/lpuart4.rs deleted file mode 100644 index 5c8e0862e..000000000 --- a/mcxa276-pac/src/inputmux0/lpuart4.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `LPUART4` reader"] -pub type R = crate::R; -#[doc = "Register `LPUART4` writer"] -pub type W = crate::W; -#[doc = "LPUART4 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN8 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN9 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN10 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN11 input is selected"] - Val28 = 28, - #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] - Val31 = 31, - #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: WUU selected"] - Val34 = 34, - #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT1 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT2 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT3 input is selected"] - Val39 = 39, - #[doc = "40: CTimer3_MAT2 input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT3 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT2 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT3 input is selected"] - Val43 = 43, - #[doc = "44: FlexIO CH0 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH1 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH2 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH3 input is selected"] - Val47 = 47, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPUART4 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } -} -#[doc = "Field `INP` writer - LPUART4 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } -} -impl R { - #[doc = "Bits 0:5 - LPUART4 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPUART4 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPUART4 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpuart4Spec; -impl crate::RegisterSpec for Lpuart4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpuart4::R`](R) reader structure"] -impl crate::Readable for Lpuart4Spec {} -#[doc = "`write(|w| ..)` method takes [`lpuart4::W`](W) writer structure"] -impl crate::Writable for Lpuart4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPUART4 to value 0x3f"] -impl crate::Resettable for Lpuart4Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/lpuart5.rs b/mcxa276-pac/src/inputmux0/lpuart5.rs deleted file mode 100644 index 92023be2d..000000000 --- a/mcxa276-pac/src/inputmux0/lpuart5.rs +++ /dev/null @@ -1,652 +0,0 @@ -#[doc = "Register `LPUART5` reader"] -pub type R = crate::R; -#[doc = "Register `LPUART5` writer"] -pub type W = crate::W; -#[doc = "LPUART5 trigger input connections\n\nValue on reset: 63"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3 input is selected"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "15: LPTMR0 input is selected"] - Val15 = 15, - #[doc = "17: TRIG_IN0 input is selected"] - Val17 = 17, - #[doc = "18: TRIG_IN1 input is selected"] - Val18 = 18, - #[doc = "19: TRIG_IN2 input is selected"] - Val19 = 19, - #[doc = "20: TRIG_IN3 input is selected"] - Val20 = 20, - #[doc = "21: TRIG_IN4 input is selected"] - Val21 = 21, - #[doc = "22: TRIG_IN5 input is selected"] - Val22 = 22, - #[doc = "23: TRIG_IN6 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN7 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN8 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN9 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN10 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN11 input is selected"] - Val28 = 28, - #[doc = "29: GPIO0 Pin Event Trig 0 input is selected"] - Val29 = 29, - #[doc = "30: GPIO1 Pin Event Trig 0 input is selected"] - Val30 = 30, - #[doc = "31: GPIO2 Pin Event Trig 0 input is selected"] - Val31 = 31, - #[doc = "32: GPIO3 Pin Event Trig 0 input is selected"] - Val32 = 32, - #[doc = "33: GPIO4 Pin Event Trig 0 input is selected"] - Val33 = 33, - #[doc = "34: WUU selected"] - Val34 = 34, - #[doc = "35: USB0 ipp_ind_uart_rxd_usbmux input is selected"] - Val35 = 35, - #[doc = "36: AOI1_OUT0 input is selected"] - Val36 = 36, - #[doc = "37: AOI1_OUT1 input is selected"] - Val37 = 37, - #[doc = "38: AOI1_OUT2 input is selected"] - Val38 = 38, - #[doc = "39: AOI1_OUT3 input is selected"] - Val39 = 39, - #[doc = "40: CTimer3_MAT2 input is selected"] - Val40 = 40, - #[doc = "41: CTimer3_MAT3 input is selected"] - Val41 = 41, - #[doc = "42: CTimer4_MAT2 input is selected"] - Val42 = 42, - #[doc = "43: CTimer4_MAT3 input is selected"] - Val43 = 43, - #[doc = "44: FlexIO CH0 input is selected"] - Val44 = 44, - #[doc = "45: FlexIO CH1 input is selected"] - Val45 = 45, - #[doc = "46: FlexIO CH2 input is selected"] - Val46 = 46, - #[doc = "47: FlexIO CH3 input is selected"] - Val47 = 47, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - LPUART5 trigger input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - _ => None, - } - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } -} -#[doc = "Field `INP` writer - LPUART5 trigger input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 6, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "LPTMR0 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "GPIO0 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "WUU selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "FlexIO CH0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "FlexIO CH1 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "FlexIO CH2 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "FlexIO CH3 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } -} -impl R { - #[doc = "Bits 0:5 - LPUART5 trigger input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - LPUART5 trigger input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "LPUART5 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Lpuart5Spec; -impl crate::RegisterSpec for Lpuart5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpuart5::R`](R) reader structure"] -impl crate::Readable for Lpuart5Spec {} -#[doc = "`write(|w| ..)` method takes [`lpuart5::W`](W) writer structure"] -impl crate::Writable for Lpuart5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPUART5 to value 0x3f"] -impl crate::Resettable for Lpuart5Spec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs b/mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs deleted file mode 100644 index fd9d8b6ea..000000000 --- a/mcxa276-pac/src/inputmux0/pwm0_ext_clk.rs +++ /dev/null @@ -1,171 +0,0 @@ -#[doc = "Register `PWM0_EXT_CLK` reader"] -pub type R = crate::R; -#[doc = "Register `PWM0_EXT_CLK` writer"] -pub type W = crate::W; -#[doc = "Trigger input connections for PWM\n\nValue on reset: 15"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: clk_16k\\[1\\] input is selected"] - Val1 = 1, - #[doc = "2: clk_in input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT0 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT1 input is selected"] - Val4 = 4, - #[doc = "5: EXTTRIG_IN0 input is selected"] - Val5 = 5, - #[doc = "6: EXTTRIG_IN7 input is selected"] - Val6 = 6, - #[doc = "7: AOI1_OUT0 input is selected"] - Val7 = 7, - #[doc = "8: AOI1_OUT1 input is selected"] - Val8 = 8, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - _ => None, - } - } - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "EXTTRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "EXTTRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } -} -#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 4, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "EXTTRIG_IN0 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "EXTTRIG_IN7 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } -} -impl R { - #[doc = "Bits 0:3 - Trigger input connections for PWM"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Trigger input connections for PWM"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM0 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0_ext_clk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0_ext_clk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pwm0ExtClkSpec; -impl crate::RegisterSpec for Pwm0ExtClkSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pwm0_ext_clk::R`](R) reader structure"] -impl crate::Readable for Pwm0ExtClkSpec {} -#[doc = "`write(|w| ..)` method takes [`pwm0_ext_clk::W`](W) writer structure"] -impl crate::Writable for Pwm0ExtClkSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PWM0_EXT_CLK to value 0x0f"] -impl crate::Resettable for Pwm0ExtClkSpec { - const RESET_VALUE: u32 = 0x0f; -} diff --git a/mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs b/mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs deleted file mode 100644 index 5c827f56b..000000000 --- a/mcxa276-pac/src/inputmux0/pwm1_ext_clk.rs +++ /dev/null @@ -1,171 +0,0 @@ -#[doc = "Register `PWM1_EXT_CLK` reader"] -pub type R = crate::R; -#[doc = "Register `PWM1_EXT_CLK` writer"] -pub type W = crate::W; -#[doc = "Trigger input connections for PWM\n\nValue on reset: 15"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trigin { - #[doc = "1: clk_16k\\[1\\] input is selected"] - Val1 = 1, - #[doc = "2: clk_in input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT0 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT1 input is selected"] - Val4 = 4, - #[doc = "5: EXTTRIG_IN0 input is selected"] - Val5 = 5, - #[doc = "6: EXTTRIG_IN7 input is selected"] - Val6 = 6, - #[doc = "7: AOI1_OUT0 input is selected"] - Val7 = 7, - #[doc = "8: AOI1_OUT1 input is selected"] - Val8 = 8, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trigin) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trigin { - type Ux = u8; -} -impl crate::IsEnum for Trigin {} -#[doc = "Field `TRIGIN` reader - Trigger input connections for PWM"] -pub type TriginR = crate::FieldReader; -impl TriginR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Trigin::Val1), - 2 => Some(Trigin::Val2), - 3 => Some(Trigin::Val3), - 4 => Some(Trigin::Val4), - 5 => Some(Trigin::Val5), - 6 => Some(Trigin::Val6), - 7 => Some(Trigin::Val7), - 8 => Some(Trigin::Val8), - _ => None, - } - } - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Trigin::Val1 - } - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Trigin::Val2 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Trigin::Val3 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Trigin::Val4 - } - #[doc = "EXTTRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Trigin::Val5 - } - #[doc = "EXTTRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Trigin::Val6 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Trigin::Val7 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Trigin::Val8 - } -} -#[doc = "Field `TRIGIN` writer - Trigger input connections for PWM"] -pub type TriginW<'a, REG> = crate::FieldWriter<'a, REG, 4, Trigin>; -impl<'a, REG> TriginW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "clk_16k\\[1\\] input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Trigin::Val1) - } - #[doc = "clk_in input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Trigin::Val2) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Trigin::Val3) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Trigin::Val4) - } - #[doc = "EXTTRIG_IN0 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Trigin::Val5) - } - #[doc = "EXTTRIG_IN7 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Trigin::Val6) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Trigin::Val7) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Trigin::Val8) - } -} -impl R { - #[doc = "Bits 0:3 - Trigger input connections for PWM"] - #[inline(always)] - pub fn trigin(&self) -> TriginR { - TriginR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Trigger input connections for PWM"] - #[inline(always)] - pub fn trigin(&mut self) -> TriginW { - TriginW::new(self, 0) - } -} -#[doc = "PWM1 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1_ext_clk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1_ext_clk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pwm1ExtClkSpec; -impl crate::RegisterSpec for Pwm1ExtClkSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pwm1_ext_clk::R`](R) reader structure"] -impl crate::Readable for Pwm1ExtClkSpec {} -#[doc = "`write(|w| ..)` method takes [`pwm1_ext_clk::W`](W) writer structure"] -impl crate::Writable for Pwm1ExtClkSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PWM1_EXT_CLK to value 0x0f"] -impl crate::Resettable for Pwm1ExtClkSpec { - const RESET_VALUE: u32 = 0x0f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_home.rs b/mcxa276-pac/src/inputmux0/qdc0_home.rs deleted file mode 100644 index a515f2e8f..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_home.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC0_HOME` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_HOME` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_home::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_home::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0HomeSpec; -impl crate::RegisterSpec for Qdc0HomeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_home::R`](R) reader structure"] -impl crate::Readable for Qdc0HomeSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_home::W`](W) writer structure"] -impl crate::Writable for Qdc0HomeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_HOME to value 0x7f"] -impl crate::Resettable for Qdc0HomeSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_icap1.rs b/mcxa276-pac/src/inputmux0/qdc0_icap1.rs deleted file mode 100644 index 4ecbe2876..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_icap1.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC0_ICAP1` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_ICAP1` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0Icap1Spec; -impl crate::RegisterSpec for Qdc0Icap1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_icap1::R`](R) reader structure"] -impl crate::Readable for Qdc0Icap1Spec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_icap1::W`](W) writer structure"] -impl crate::Writable for Qdc0Icap1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_ICAP1 to value 0x7f"] -impl crate::Resettable for Qdc0Icap1Spec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_icap2.rs b/mcxa276-pac/src/inputmux0/qdc0_icap2.rs deleted file mode 100644 index 5f3a3ea83..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_icap2.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC0_ICAP2` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_ICAP2` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0Icap2Spec; -impl crate::RegisterSpec for Qdc0Icap2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_icap2::R`](R) reader structure"] -impl crate::Readable for Qdc0Icap2Spec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_icap2::W`](W) writer structure"] -impl crate::Writable for Qdc0Icap2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_ICAP2 to value 0x7f"] -impl crate::Resettable for Qdc0Icap2Spec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_icap3.rs b/mcxa276-pac/src/inputmux0/qdc0_icap3.rs deleted file mode 100644 index 19111f161..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_icap3.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC0_ICAP3` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_ICAP3` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM0_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0Icap3Spec; -impl crate::RegisterSpec for Qdc0Icap3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_icap3::R`](R) reader structure"] -impl crate::Readable for Qdc0Icap3Spec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_icap3::W`](W) writer structure"] -impl crate::Writable for Qdc0Icap3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_ICAP3 to value 0x7f"] -impl crate::Resettable for Qdc0Icap3Spec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_index.rs b/mcxa276-pac/src/inputmux0/qdc0_index.rs deleted file mode 100644 index dbc856a33..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_index.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC0_INDEX` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_INDEX` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0IndexSpec; -impl crate::RegisterSpec for Qdc0IndexSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_index::R`](R) reader structure"] -impl crate::Readable for Qdc0IndexSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_index::W`](W) writer structure"] -impl crate::Writable for Qdc0IndexSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_INDEX to value 0x7f"] -impl crate::Resettable for Qdc0IndexSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_phasea.rs b/mcxa276-pac/src/inputmux0/qdc0_phasea.rs deleted file mode 100644 index de4028f34..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_phasea.rs +++ /dev/null @@ -1,756 +0,0 @@ -#[doc = "Register `QDC0_PHASEA` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_PHASEA` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phasea::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phasea::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0PhaseaSpec; -impl crate::RegisterSpec for Qdc0PhaseaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_phasea::R`](R) reader structure"] -impl crate::Readable for Qdc0PhaseaSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_phasea::W`](W) writer structure"] -impl crate::Writable for Qdc0PhaseaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_PHASEA to value 0x7f"] -impl crate::Resettable for Qdc0PhaseaSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_phaseb.rs b/mcxa276-pac/src/inputmux0/qdc0_phaseb.rs deleted file mode 100644 index 204fadc21..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_phaseb.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC0_PHASEB` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_PHASEB` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phaseb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phaseb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0PhasebSpec; -impl crate::RegisterSpec for Qdc0PhasebSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_phaseb::R`](R) reader structure"] -impl crate::Readable for Qdc0PhasebSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_phaseb::W`](W) writer structure"] -impl crate::Writable for Qdc0PhasebSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_PHASEB to value 0x7f"] -impl crate::Resettable for Qdc0PhasebSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc0_trig.rs b/mcxa276-pac/src/inputmux0/qdc0_trig.rs deleted file mode 100644 index f2c422b39..000000000 --- a/mcxa276-pac/src/inputmux0/qdc0_trig.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC0_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `QDC0_TRIG` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc0TrigSpec; -impl crate::RegisterSpec for Qdc0TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc0_trig::R`](R) reader structure"] -impl crate::Readable for Qdc0TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc0_trig::W`](W) writer structure"] -impl crate::Writable for Qdc0TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC0_TRIG to value 0x7f"] -impl crate::Resettable for Qdc0TrigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_home.rs b/mcxa276-pac/src/inputmux0/qdc1_home.rs deleted file mode 100644 index 90f9f9c40..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_home.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_HOME` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_HOME` writer"] -pub type W = crate::W; -#[doc = "QDC1 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC1 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC1 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_home::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_home::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1HomeSpec; -impl crate::RegisterSpec for Qdc1HomeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_home::R`](R) reader structure"] -impl crate::Readable for Qdc1HomeSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_home::W`](W) writer structure"] -impl crate::Writable for Qdc1HomeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_HOME to value 0x7f"] -impl crate::Resettable for Qdc1HomeSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_icap1.rs b/mcxa276-pac/src/inputmux0/qdc1_icap1.rs deleted file mode 100644 index 689321615..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_icap1.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_ICAP1` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_ICAP1` writer"] -pub type W = crate::W; -#[doc = "QDC1 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC1 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC1 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1Icap1Spec; -impl crate::RegisterSpec for Qdc1Icap1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_icap1::R`](R) reader structure"] -impl crate::Readable for Qdc1Icap1Spec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_icap1::W`](W) writer structure"] -impl crate::Writable for Qdc1Icap1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_ICAP1 to value 0x7f"] -impl crate::Resettable for Qdc1Icap1Spec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_icap2.rs b/mcxa276-pac/src/inputmux0/qdc1_icap2.rs deleted file mode 100644 index 07c2bd08e..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_icap2.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_ICAP2` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_ICAP2` writer"] -pub type W = crate::W; -#[doc = "QDC1 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC1 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC1 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1Icap2Spec; -impl crate::RegisterSpec for Qdc1Icap2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_icap2::R`](R) reader structure"] -impl crate::Readable for Qdc1Icap2Spec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_icap2::W`](W) writer structure"] -impl crate::Writable for Qdc1Icap2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_ICAP2 to value 0x7f"] -impl crate::Resettable for Qdc1Icap2Spec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_icap3.rs b/mcxa276-pac/src/inputmux0/qdc1_icap3.rs deleted file mode 100644 index 84e312a0f..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_icap3.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_ICAP3` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_ICAP3` writer"] -pub type W = crate::W; -#[doc = "QDC1 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC1 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC1 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1Icap3Spec; -impl crate::RegisterSpec for Qdc1Icap3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_icap3::R`](R) reader structure"] -impl crate::Readable for Qdc1Icap3Spec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_icap3::W`](W) writer structure"] -impl crate::Writable for Qdc1Icap3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_ICAP3 to value 0x7f"] -impl crate::Resettable for Qdc1Icap3Spec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_index.rs b/mcxa276-pac/src/inputmux0/qdc1_index.rs deleted file mode 100644 index 5dc5a96a8..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_index.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_INDEX` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_INDEX` writer"] -pub type W = crate::W; -#[doc = "QDC1 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: >CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC1 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = ">CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC1 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = ">CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_index::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_index::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1IndexSpec; -impl crate::RegisterSpec for Qdc1IndexSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_index::R`](R) reader structure"] -impl crate::Readable for Qdc1IndexSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_index::W`](W) writer structure"] -impl crate::Writable for Qdc1IndexSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_INDEX to value 0x7f"] -impl crate::Resettable for Qdc1IndexSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_phasea.rs b/mcxa276-pac/src/inputmux0/qdc1_phasea.rs deleted file mode 100644 index e95cf7945..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_phasea.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_PHASEA` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_PHASEA` writer"] -pub type W = crate::W; -#[doc = "QDC0 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC0 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC0 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC0 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phasea::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phasea::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1PhaseaSpec; -impl crate::RegisterSpec for Qdc1PhaseaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_phasea::R`](R) reader structure"] -impl crate::Readable for Qdc1PhaseaSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_phasea::W`](W) writer structure"] -impl crate::Writable for Qdc1PhaseaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_PHASEA to value 0x7f"] -impl crate::Resettable for Qdc1PhaseaSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_phaseb.rs b/mcxa276-pac/src/inputmux0/qdc1_phaseb.rs deleted file mode 100644 index 76a0e7a9a..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_phaseb.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_PHASEB` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_PHASEB` writer"] -pub type W = crate::W; -#[doc = "QDC1 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 inout is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC1 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 inout is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC1 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 inout is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phaseb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phaseb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1PhasebSpec; -impl crate::RegisterSpec for Qdc1PhasebSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_phaseb::R`](R) reader structure"] -impl crate::Readable for Qdc1PhasebSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_phaseb::W`](W) writer structure"] -impl crate::Writable for Qdc1PhasebSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_PHASEB to value 0x7f"] -impl crate::Resettable for Qdc1PhasebSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/qdc1_trig.rs b/mcxa276-pac/src/inputmux0/qdc1_trig.rs deleted file mode 100644 index 392b5ce50..000000000 --- a/mcxa276-pac/src/inputmux0/qdc1_trig.rs +++ /dev/null @@ -1,782 +0,0 @@ -#[doc = "Register `QDC1_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `QDC1_TRIG` writer"] -pub type W = crate::W; -#[doc = "QDC1 input connections\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: ARM_TXEV input is selected"] - Val1 = 1, - #[doc = "2: AOI0_OUT0 input is selected"] - Val2 = 2, - #[doc = "3: AOI0_OUT1 input is selected"] - Val3 = 3, - #[doc = "4: AOI0_OUT2 input is selected"] - Val4 = 4, - #[doc = "5: AOI0_OUT3 input is selected"] - Val5 = 5, - #[doc = "6: CMP0_OUT input is selected"] - Val6 = 6, - #[doc = "7: CMP1_OUT input is selected"] - Val7 = 7, - #[doc = "8: CMP2_OUT input is selected"] - Val8 = 8, - #[doc = "9: CTimer0_MAT2 input is selected"] - Val9 = 9, - #[doc = "10: CTimer0_MAT3"] - Val10 = 10, - #[doc = "11: CTimer1_MAT2 input is selected"] - Val11 = 11, - #[doc = "12: CTimer1_MAT3 input is selected"] - Val12 = 12, - #[doc = "13: CTimer2_MAT2 input is selected"] - Val13 = 13, - #[doc = "14: CTimer2_MAT3 input is selected"] - Val14 = 14, - #[doc = "16: PWM0_SM0_MUX_TRIG0 input is selected"] - Val16 = 16, - #[doc = "17: PWM0_SM0_MUX_TRIG1 input is selected"] - Val17 = 17, - #[doc = "18: PWM0_SM1_MUX_TRIG0 input is selected"] - Val18 = 18, - #[doc = "19: PWM0_SM1_MUX_TRIG1 input is selected"] - Val19 = 19, - #[doc = "20: PWM0_SM2_MUX_TRIG0 input is selected"] - Val20 = 20, - #[doc = "21: PWM0_SM2_MUX_TRIG1 input is selected"] - Val21 = 21, - #[doc = "22: PWM0_SM3_MUX_TRIG0 input is selected"] - Val22 = 22, - #[doc = "23: PWM0_SM3_MUX_TRIG1 input is selected"] - Val23 = 23, - #[doc = "24: TRIG_IN0 input is selected"] - Val24 = 24, - #[doc = "25: TRIG_IN1 input is selected"] - Val25 = 25, - #[doc = "26: TRIG_IN2 input is selected"] - Val26 = 26, - #[doc = "27: TRIG_IN3 input is selected"] - Val27 = 27, - #[doc = "28: TRIG_IN4 input is selected"] - Val28 = 28, - #[doc = "29: TRIG_IN5 input is selected"] - Val29 = 29, - #[doc = "30: TRIG_IN6 input is selected"] - Val30 = 30, - #[doc = "31: TRIG_IN7 input is selected"] - Val31 = 31, - #[doc = "32: TRIG_IN8 input is selected"] - Val32 = 32, - #[doc = "33: TRIG_IN9 input is selected"] - Val33 = 33, - #[doc = "34: TRIG_IN10 input is selected"] - Val34 = 34, - #[doc = "35: TRIG_IN11 input is selected"] - Val35 = 35, - #[doc = "36: GPIO0 Pin Event Trig 0 is selected"] - Val36 = 36, - #[doc = "37: GPIO1 Pin Event Trig 0 input is selected"] - Val37 = 37, - #[doc = "38: GPIO2 Pin Event Trig 0 input is selected"] - Val38 = 38, - #[doc = "39: GPIO3 Pin Event Trig 0 input is selected"] - Val39 = 39, - #[doc = "40: GPIO4 Pin Event Trig 0 input is selected"] - Val40 = 40, - #[doc = "41: AOI1_OUT0 input is selected"] - Val41 = 41, - #[doc = "42: AOI1_OUT1 input is selected"] - Val42 = 42, - #[doc = "43: AOI1_OUT2 input is selected"] - Val43 = 43, - #[doc = "44: AOI1_OUT3 input is selected"] - Val44 = 44, - #[doc = "49: CTimer3_MAT2 input is selected"] - Val49 = 49, - #[doc = "50: CTimer3_MAT3 input is selected"] - Val50 = 50, - #[doc = "51: CTimer4_MAT2 input is selected"] - Val51 = 51, - #[doc = "52: CTimer4_MAT3 input is selected"] - Val52 = 52, - #[doc = "62: PWM1_SM0_OUT_TRIG0 input is selected"] - Val62 = 62, - #[doc = "63: PWM1_SM0_OUT_TRIG1 input is selected"] - Val63 = 63, - #[doc = "64: PWM1_SM1_OUT_TRIG0 input is selected"] - Val64 = 64, - #[doc = "65: PWM1_SM1_OUT_TRIG1 input is selected"] - Val65 = 65, - #[doc = "66: PWM1_SM2_OUT_TRIG0 input is selected"] - Val66 = 66, - #[doc = "67: PWM1_SM2_OUT_TRIG1 input is selected"] - Val67 = 67, - #[doc = "68: PWM1_SM3_MUX_TRIG0 input is selected"] - Val68 = 68, - #[doc = "69: PWM1_SM3_MUX_TRIG1 input is selected"] - Val69 = 69, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - QDC1 input connections"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - _ => None, - } - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } -} -#[doc = "Field `INP` writer - QDC1 input connections"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CTimer0_MAT3"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "GPIO0 Pin Event Trig 0 is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "GPIO1 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "GPIO2 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "GPIO3 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "GPIO4 Pin Event Trig 0 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } -} -impl R { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - QDC1 input connections"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Qdc1TrigSpec; -impl crate::RegisterSpec for Qdc1TrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`qdc1_trig::R`](R) reader structure"] -impl crate::Readable for Qdc1TrigSpec {} -#[doc = "`write(|w| ..)` method takes [`qdc1_trig::W`](W) writer structure"] -impl crate::Writable for Qdc1TrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets QDC1_TRIG to value 0x7f"] -impl crate::Resettable for Qdc1TrigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/smart_dma_trig.rs b/mcxa276-pac/src/inputmux0/smart_dma_trig.rs deleted file mode 100644 index 535a029bc..000000000 --- a/mcxa276-pac/src/inputmux0/smart_dma_trig.rs +++ /dev/null @@ -1,1081 +0,0 @@ -#[doc = "Register `SmartDMA_TRIG[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `SmartDMA_TRIG[%s]` writer"] -pub type W = crate::W; -#[doc = "Input number for SmartDMA.\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: GPIO P0_16 input is selected"] - Val1 = 1, - #[doc = "2: GPIO P0_17 input is selected"] - Val2 = 2, - #[doc = "3: GPIO P1_8 input is selected"] - Val3 = 3, - #[doc = "4: GPIO P1_9 input is selected"] - Val4 = 4, - #[doc = "5: GPIO P1_10 input is selected"] - Val5 = 5, - #[doc = "6: GPIO P1_11 input is selected"] - Val6 = 6, - #[doc = "7: GPIO P1_12 input is selected"] - Val7 = 7, - #[doc = "8: GPIO P1_13 input is selected"] - Val8 = 8, - #[doc = "9: GPIO P2_0 input is selected"] - Val9 = 9, - #[doc = "10: GPIO P2_1 input is selected"] - Val10 = 10, - #[doc = "11: GPIO P2_2 input is selected"] - Val11 = 11, - #[doc = "12: GPIO P2_3 input is selected"] - Val12 = 12, - #[doc = "13: GPIO P2_6 input is selected"] - Val13 = 13, - #[doc = "14: GPIO P3_8 input is selected"] - Val14 = 14, - #[doc = "15: GPIO P3_9 input is selected"] - Val15 = 15, - #[doc = "16: GPIO P3_10 input is selected"] - Val16 = 16, - #[doc = "17: GPIO P3_11 input is selected"] - Val17 = 17, - #[doc = "18: GPIO P3_12 input is seclected"] - Val18 = 18, - #[doc = "19: GPIO0 Pin Event Trig input is selected"] - Val19 = 19, - #[doc = "20: GPIO1 Pin Event Trig input is selected"] - Val20 = 20, - #[doc = "21: GPIO2 Pin Event Trig input is selected"] - Val21 = 21, - #[doc = "22: GPIO3 Pin Event Trig input is selected"] - Val22 = 22, - #[doc = "23: GPIO4 Pin Event Trig input is selected"] - Val23 = 23, - #[doc = "24: ARM_TXEV input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT0 input is selected"] - Val25 = 25, - #[doc = "26: AOI1_OUT1 input is selected"] - Val26 = 26, - #[doc = "27: DMA_IRQ input is selected"] - Val27 = 27, - #[doc = "28: MAU_IRQ input is selected"] - Val28 = 28, - #[doc = "29: WUU_IRQ input is selected"] - Val29 = 29, - #[doc = "30: CTimer0_MAT2 input is selected"] - Val30 = 30, - #[doc = "31: CTimer0_MAT3 input is selected"] - Val31 = 31, - #[doc = "32: CTimer1_MAT2 input is selected"] - Val32 = 32, - #[doc = "33: CTimer1_MAT3 input is selected"] - Val33 = 33, - #[doc = "34: CTimer2_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer2_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer3_MAT2 input is selected"] - Val36 = 36, - #[doc = "37: CTimer3_MAT3 input is selected"] - Val37 = 37, - #[doc = "38: CTimer4_MAT2 input is selected"] - Val38 = 38, - #[doc = "39: CTimer4_MAT3 input is selected"] - Val39 = 39, - #[doc = "40: OSTIMER_IRQ input is selected"] - Val40 = 40, - #[doc = "41: PWM0_IRQ input is selected"] - Val41 = 41, - #[doc = "42: PWM1_IRQ input is selected"] - Val42 = 42, - #[doc = "43: QDC0_IRQ input is selected"] - Val43 = 43, - #[doc = "44: QDC1_IRQ input is selected"] - Val44 = 44, - #[doc = "45: RTC_Alarm_IRQ input is selected"] - Val45 = 45, - #[doc = "46: RTC_1Hz_IRQ input is selected"] - Val46 = 46, - #[doc = "47: uTICK_IRQ input is selected"] - Val47 = 47, - #[doc = "48: WDT_IRQ input is selected"] - Val48 = 48, - #[doc = "49: Wakeup_Timer_IRQ input is selected"] - Val49 = 49, - #[doc = "50: CAN0_IRQ input is selected"] - Val50 = 50, - #[doc = "51: CAN1_IRQ input is selected"] - Val51 = 51, - #[doc = "52: FlexIO_IRQ input is selected"] - Val52 = 52, - #[doc = "53: FlexIO_Shifer0_DMA_Req input is selected"] - Val53 = 53, - #[doc = "54: FlexIO_Shifer1_DMA_Req input is selected"] - Val54 = 54, - #[doc = "55: FlexIO_Shifer2_DMA_Req input is selected"] - Val55 = 55, - #[doc = "56: FlexIO_Shifer3_DMA_Req input is selected"] - Val56 = 56, - #[doc = "57: I3C0_IRQ input is selected"] - Val57 = 57, - #[doc = "58: LPI2C0_IRQ input is selected"] - Val58 = 58, - #[doc = "59: LPI2C1_IRQ input is selected"] - Val59 = 59, - #[doc = "60: LPSPI0_IRQ input is selected"] - Val60 = 60, - #[doc = "61: LPSPI1_IRQ input is selected"] - Val61 = 61, - #[doc = "62: LPUART0_IRQ input is selected"] - Val62 = 62, - #[doc = "63: LPUART1_IRQ input is selected"] - Val63 = 63, - #[doc = "64: LPUART2_IRQ input is selected"] - Val64 = 64, - #[doc = "65: LPUART3_IRQ input is selected"] - Val65 = 65, - #[doc = "66: USB0_SOF input is selected"] - Val66 = 66, - #[doc = "68: ADC0_IRQ input is selected"] - Val68 = 68, - #[doc = "69: ADC1_IRQ input is selected"] - Val69 = 69, - #[doc = "70: ADC2_IRQ input is selected"] - Val70 = 70, - #[doc = "71: ADC3_IRQ input is selected"] - Val71 = 71, - #[doc = "72: CMP0_IRQ input is selected"] - Val72 = 72, - #[doc = "73: CMP1_IRQ input is selected"] - Val73 = 73, - #[doc = "74: CMP2_IRQ input is selected"] - Val74 = 74, - #[doc = "75: CMP0_OUT input is selected"] - Val75 = 75, - #[doc = "76: CMP1_OUT input is selected"] - Val76 = 76, - #[doc = "77: CMP2_OUT input is selected"] - Val77 = 77, - #[doc = "78: DAC0_IRQ input is selected"] - Val78 = 78, - #[doc = "79: SLCD_IRQ input is selected"] - Val79 = 79, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for SmartDMA."] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - _ => None, - } - } - #[doc = "GPIO P0_16 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "GPIO P0_17 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "GPIO P1_8 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "GPIO P1_9 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "GPIO P1_10 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "GPIO P1_11 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "GPIO P1_12 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "GPIO P1_13 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "GPIO P2_0 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "GPIO P2_1 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "GPIO P2_2 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "GPIO P2_3 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "GPIO P2_6 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "GPIO P3_8 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "GPIO P3_9 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "GPIO P3_10 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "GPIO P3_11 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "GPIO P3_12 input is seclected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "GPIO0 Pin Event Trig input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "GPIO1 Pin Event Trig input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "GPIO2 Pin Event Trig input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "GPIO3 Pin Event Trig input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "GPIO4 Pin Event Trig input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "DMA_IRQ input is selected"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "MAU_IRQ input is selected"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "WUU_IRQ input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "OSTIMER_IRQ input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "PWM0_IRQ input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "PWM1_IRQ input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_IRQ input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "QDC1_IRQ input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "RTC_Alarm_IRQ input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "RTC_1Hz_IRQ input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "uTICK_IRQ input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "WDT_IRQ input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "Wakeup_Timer_IRQ input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "CAN0_IRQ input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "CAN1_IRQ input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "FlexIO_IRQ input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "FlexIO_Shifer0_DMA_Req input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "FlexIO_Shifer1_DMA_Req input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "FlexIO_Shifer2_DMA_Req input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "FlexIO_Shifer3_DMA_Req input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "I3C0_IRQ input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPI2C0_IRQ input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPI2C1_IRQ input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPSPI0_IRQ input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPSPI1_IRQ input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART0_IRQ input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART1_IRQ input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2_IRQ input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3_IRQ input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "USB0_SOF input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "ADC0_IRQ input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "ADC1_IRQ input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "ADC2_IRQ input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "ADC3_IRQ input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "CMP0_IRQ input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "CMP1_IRQ input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "CMP2_IRQ input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "DAC0_IRQ input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "SLCD_IRQ input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } -} -#[doc = "Field `INP` writer - Input number for SmartDMA."] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "GPIO P0_16 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "GPIO P0_17 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "GPIO P1_8 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "GPIO P1_9 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "GPIO P1_10 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "GPIO P1_11 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "GPIO P1_12 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "GPIO P1_13 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "GPIO P2_0 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "GPIO P2_1 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "GPIO P2_2 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "GPIO P2_3 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "GPIO P2_6 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "GPIO P3_8 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "GPIO P3_9 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "GPIO P3_10 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "GPIO P3_11 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "GPIO P3_12 input is seclected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "GPIO0 Pin Event Trig input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "GPIO1 Pin Event Trig input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "GPIO2 Pin Event Trig input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "GPIO3 Pin Event Trig input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "GPIO4 Pin Event Trig input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "ARM_TXEV input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "DMA_IRQ input is selected"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "MAU_IRQ input is selected"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "WUU_IRQ input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "OSTIMER_IRQ input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "PWM0_IRQ input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "PWM1_IRQ input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_IRQ input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "QDC1_IRQ input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "RTC_Alarm_IRQ input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "RTC_1Hz_IRQ input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "uTICK_IRQ input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "WDT_IRQ input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "Wakeup_Timer_IRQ input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "CAN0_IRQ input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "CAN1_IRQ input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "FlexIO_IRQ input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "FlexIO_Shifer0_DMA_Req input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "FlexIO_Shifer1_DMA_Req input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "FlexIO_Shifer2_DMA_Req input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "FlexIO_Shifer3_DMA_Req input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "I3C0_IRQ input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPI2C0_IRQ input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPI2C1_IRQ input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPSPI0_IRQ input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPSPI1_IRQ input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART0_IRQ input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART1_IRQ input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2_IRQ input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3_IRQ input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "USB0_SOF input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "ADC0_IRQ input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "ADC1_IRQ input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "ADC2_IRQ input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "ADC3_IRQ input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "CMP0_IRQ input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "CMP1_IRQ input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "CMP2_IRQ input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "CMP0_OUT input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "CMP1_OUT input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "CMP2_OUT input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "DAC0_IRQ input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "SLCD_IRQ input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for SmartDMA."] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for SmartDMA."] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "SmartDMA Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dma_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dma_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SmartDmaTrigSpec; -impl crate::RegisterSpec for SmartDmaTrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`smart_dma_trig::R`](R) reader structure"] -impl crate::Readable for SmartDmaTrigSpec {} -#[doc = "`write(|w| ..)` method takes [`smart_dma_trig::W`](W) writer structure"] -impl crate::Writable for SmartDmaTrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SmartDMA_TRIG[%s] to value 0x7f"] -impl crate::Resettable for SmartDmaTrigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/timer0trig.rs b/mcxa276-pac/src/inputmux0/timer0trig.rs deleted file mode 100644 index fb53737c9..000000000 --- a/mcxa276-pac/src/inputmux0/timer0trig.rs +++ /dev/null @@ -1,1471 +0,0 @@ -#[doc = "Register `TIMER0TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `TIMER0TRIG` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER0\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer1_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer1_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer1_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer2_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer2_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer2_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer3_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer3_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer3_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER0"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER0"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER0"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER0"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Trigger register for TIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`timer0trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Timer0trigSpec; -impl crate::RegisterSpec for Timer0trigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timer0trig::R`](R) reader structure"] -impl crate::Readable for Timer0trigSpec {} -#[doc = "`write(|w| ..)` method takes [`timer0trig::W`](W) writer structure"] -impl crate::Writable for Timer0trigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMER0TRIG to value 0x7f"] -impl crate::Resettable for Timer0trigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/timer1trig.rs b/mcxa276-pac/src/inputmux0/timer1trig.rs deleted file mode 100644 index 3b95505c2..000000000 --- a/mcxa276-pac/src/inputmux0/timer1trig.rs +++ /dev/null @@ -1,1471 +0,0 @@ -#[doc = "Register `TIMER1TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `TIMER1TRIG` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER1\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer2_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer2_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer2_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer3_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer3_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer3_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER1"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER1"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER1"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER1"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Trigger register for TIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Timer1trigSpec; -impl crate::RegisterSpec for Timer1trigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timer1trig::R`](R) reader structure"] -impl crate::Readable for Timer1trigSpec {} -#[doc = "`write(|w| ..)` method takes [`timer1trig::W`](W) writer structure"] -impl crate::Writable for Timer1trigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMER1TRIG to value 0x7f"] -impl crate::Resettable for Timer1trigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/timer2trig.rs b/mcxa276-pac/src/inputmux0/timer2trig.rs deleted file mode 100644 index 4df66adc8..000000000 --- a/mcxa276-pac/src/inputmux0/timer2trig.rs +++ /dev/null @@ -1,1471 +0,0 @@ -#[doc = "Register `TIMER2TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `TIMER2TRIG` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER2\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer1_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer1_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer1_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer3_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer3_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer3_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER2"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER2"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER2"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER2"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Trigger register for TIMER2 inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Timer2trigSpec; -impl crate::RegisterSpec for Timer2trigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timer2trig::R`](R) reader structure"] -impl crate::Readable for Timer2trigSpec {} -#[doc = "`write(|w| ..)` method takes [`timer2trig::W`](W) writer structure"] -impl crate::Writable for Timer2trigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMER2TRIG to value 0x7f"] -impl crate::Resettable for Timer2trigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/timer3trig.rs b/mcxa276-pac/src/inputmux0/timer3trig.rs deleted file mode 100644 index 46fe97bf5..000000000 --- a/mcxa276-pac/src/inputmux0/timer3trig.rs +++ /dev/null @@ -1,1627 +0,0 @@ -#[doc = "Register `TIMER3TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `TIMER3TRIG` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER3\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer1_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer1_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer1_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer2_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer2_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer2_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer4_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer4_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer4_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, - #[doc = "113: TRIG_IN0 input is selected"] - Val113 = 113, - #[doc = "114: TRIG_IN1 input is selected"] - Val114 = 114, - #[doc = "115: TRIG_IN2 input is selected"] - Val115 = 115, - #[doc = "116: TRIG_IN3 input is selected"] - Val116 = 116, - #[doc = "117: TRIG_IN4 input is selected"] - Val117 = 117, - #[doc = "118: TRIG_IN5 input is selected"] - Val118 = 118, - #[doc = "119: TRIG_IN6 input is selected"] - Val119 = 119, - #[doc = "120: TRIG_IN7 input is selected"] - Val120 = 120, - #[doc = "121: TRIG_IN8 input is selected"] - Val121 = 121, - #[doc = "122: TRIG_IN9 input is selected"] - Val122 = 122, - #[doc = "123: TRIG_IN10 input is selected"] - Val123 = 123, - #[doc = "124: TRIG_IN11 input is selected"] - Val124 = 124, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER3"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - 113 => Some(Inp::Val113), - 114 => Some(Inp::Val114), - 115 => Some(Inp::Val115), - 116 => Some(Inp::Val116), - 117 => Some(Inp::Val117), - 118 => Some(Inp::Val118), - 119 => Some(Inp::Val119), - 120 => Some(Inp::Val120), - 121 => Some(Inp::Val121), - 122 => Some(Inp::Val122), - 123 => Some(Inp::Val123), - 124 => Some(Inp::Val124), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val113(&self) -> bool { - *self == Inp::Val113 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val114(&self) -> bool { - *self == Inp::Val114 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val115(&self) -> bool { - *self == Inp::Val115 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val116(&self) -> bool { - *self == Inp::Val116 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val117(&self) -> bool { - *self == Inp::Val117 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val118(&self) -> bool { - *self == Inp::Val118 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val119(&self) -> bool { - *self == Inp::Val119 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val120(&self) -> bool { - *self == Inp::Val120 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val121(&self) -> bool { - *self == Inp::Val121 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val122(&self) -> bool { - *self == Inp::Val122 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val123(&self) -> bool { - *self == Inp::Val123 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val124(&self) -> bool { - *self == Inp::Val124 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER3"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer4_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer4_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer4_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val113(self) -> &'a mut crate::W { - self.variant(Inp::Val113) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val114(self) -> &'a mut crate::W { - self.variant(Inp::Val114) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val115(self) -> &'a mut crate::W { - self.variant(Inp::Val115) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val116(self) -> &'a mut crate::W { - self.variant(Inp::Val116) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val117(self) -> &'a mut crate::W { - self.variant(Inp::Val117) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val118(self) -> &'a mut crate::W { - self.variant(Inp::Val118) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val119(self) -> &'a mut crate::W { - self.variant(Inp::Val119) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val120(self) -> &'a mut crate::W { - self.variant(Inp::Val120) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val121(self) -> &'a mut crate::W { - self.variant(Inp::Val121) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val122(self) -> &'a mut crate::W { - self.variant(Inp::Val122) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val123(self) -> &'a mut crate::W { - self.variant(Inp::Val123) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val124(self) -> &'a mut crate::W { - self.variant(Inp::Val124) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER3"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER3"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Trigger register for TIMER3\n\nYou can [`read`](crate::Reg::read) this register and get [`timer3trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Timer3trigSpec; -impl crate::RegisterSpec for Timer3trigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timer3trig::R`](R) reader structure"] -impl crate::Readable for Timer3trigSpec {} -#[doc = "`write(|w| ..)` method takes [`timer3trig::W`](W) writer structure"] -impl crate::Writable for Timer3trigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMER3TRIG to value 0x7f"] -impl crate::Resettable for Timer3trigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/timer4trig.rs b/mcxa276-pac/src/inputmux0/timer4trig.rs deleted file mode 100644 index d86e8e10b..000000000 --- a/mcxa276-pac/src/inputmux0/timer4trig.rs +++ /dev/null @@ -1,1627 +0,0 @@ -#[doc = "Register `TIMER4TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `TIMER4TRIG` writer"] -pub type W = crate::W; -#[doc = "Input number for CTIMER4\n\nValue on reset: 127"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: CT_INP0 input is selected"] - Val1 = 1, - #[doc = "2: CT_INP1 input is selected"] - Val2 = 2, - #[doc = "3: CT_INP2 input is selected"] - Val3 = 3, - #[doc = "4: CT_INP3 input is selected"] - Val4 = 4, - #[doc = "5: CT_INP4 input is selected"] - Val5 = 5, - #[doc = "6: CT_INP5 input is selected"] - Val6 = 6, - #[doc = "7: CT_INP6 input is selected"] - Val7 = 7, - #[doc = "8: CT_INP7 input is selected"] - Val8 = 8, - #[doc = "9: CT_INP8 input is selected"] - Val9 = 9, - #[doc = "10: CT_INP9 input is selected"] - Val10 = 10, - #[doc = "11: CT_INP10 input is selected"] - Val11 = 11, - #[doc = "12: CT_INP11 input is selected"] - Val12 = 12, - #[doc = "13: CT_INP12 input is selected"] - Val13 = 13, - #[doc = "14: CT_INP13 input is selected"] - Val14 = 14, - #[doc = "15: CT_INP14 input is selected"] - Val15 = 15, - #[doc = "16: CT_INP15 input is selected"] - Val16 = 16, - #[doc = "17: CT_INP16 input is selected"] - Val17 = 17, - #[doc = "18: CT_INP17 input is selected"] - Val18 = 18, - #[doc = "19: CT_INP18 input is selected"] - Val19 = 19, - #[doc = "20: CT_INP19 input is selected"] - Val20 = 20, - #[doc = "21: USB0 usb0 start of frame input is selected"] - Val21 = 21, - #[doc = "22: AOI0_OUT0 input is selected"] - Val22 = 22, - #[doc = "23: AOI0_OUT1 input is selected"] - Val23 = 23, - #[doc = "24: AOI0_OUT2 input is selected"] - Val24 = 24, - #[doc = "25: AOI0_OUT3 input is selected"] - Val25 = 25, - #[doc = "26: ADC0_tcomp\\[0\\]"] - Val26 = 26, - #[doc = "27: ADC0_tcomp\\[1\\]"] - Val27 = 27, - #[doc = "28: ADC0_tcomp\\[2\\]"] - Val28 = 28, - #[doc = "29: ADC0_tcomp\\[3\\] input is selected"] - Val29 = 29, - #[doc = "30: CMP0_OUT is selected"] - Val30 = 30, - #[doc = "31: CMP1_OUT is selected"] - Val31 = 31, - #[doc = "32: CMP2_OUT is selected"] - Val32 = 32, - #[doc = "33: CTimer0_MAT1 input is selected"] - Val33 = 33, - #[doc = "34: CTimer0_MAT2 input is selected"] - Val34 = 34, - #[doc = "35: CTimer0_MAT3 input is selected"] - Val35 = 35, - #[doc = "36: CTimer1_MAT1 input is selected"] - Val36 = 36, - #[doc = "37: CTimer1_MAT2 input is selected"] - Val37 = 37, - #[doc = "38: CTimer1_MAT3 input is selected"] - Val38 = 38, - #[doc = "39: QDC0_CMP_FLAG0 is selected"] - Val39 = 39, - #[doc = "40: QDC0_CMP_FLAG1 input is selected"] - Val40 = 40, - #[doc = "41: QDC0_CMP_FLAG2 input is selected"] - Val41 = 41, - #[doc = "42: QDC0_CMP_FLAG3 input is selected"] - Val42 = 42, - #[doc = "43: QDC0_POS_MATCH0 input is selected"] - Val43 = 43, - #[doc = "44: PWM0_SM0_MUX_TRIG0 input is selected"] - Val44 = 44, - #[doc = "45: PWM0_SM1_MUX_TRIG0 input is selected"] - Val45 = 45, - #[doc = "46: PWM0_SM2_MUX_TRIG0 input is selected"] - Val46 = 46, - #[doc = "47: PWM0_SM3_MUX_TRIG0 input is selected"] - Val47 = 47, - #[doc = "48: LPI2C0 Master End of Packet input is selected"] - Val48 = 48, - #[doc = "49: LPI2C0 Slave End of Packet input is selected"] - Val49 = 49, - #[doc = "50: LPI2C1 Master End of Packet input is selected"] - Val50 = 50, - #[doc = "51: LPI2C1 Slave End of Packet input is selected"] - Val51 = 51, - #[doc = "52: LPSPI0 End of Frame input is selected"] - Val52 = 52, - #[doc = "53: LPSPI0 Received Data Word input is selected"] - Val53 = 53, - #[doc = "54: LPSPI1 End of Frame input is selected"] - Val54 = 54, - #[doc = "55: LPSPI1 Received Data Word input is selected"] - Val55 = 55, - #[doc = "56: LPUART0 Received Data Word input is selected"] - Val56 = 56, - #[doc = "57: LPUART0 Transmitted Data Word input is selected"] - Val57 = 57, - #[doc = "58: LPUART0 Receive Line Idle input is selected"] - Val58 = 58, - #[doc = "59: LPUART1 Received Data Word input is selected"] - Val59 = 59, - #[doc = "60: LPUART1 Transmitted Data Word input is selected"] - Val60 = 60, - #[doc = "61: LPUART1 Receive Line Idle input is selected"] - Val61 = 61, - #[doc = "62: LPUART2 Received Data Word input is selected"] - Val62 = 62, - #[doc = "63: LPUART2 Transmitted Data Word input is selected"] - Val63 = 63, - #[doc = "64: LPUART2 Receive Line Idle input is selected"] - Val64 = 64, - #[doc = "65: LPUART3 Received Data Word input is selected"] - Val65 = 65, - #[doc = "66: LPUART3 Transmitted Data Word input is selected"] - Val66 = 66, - #[doc = "67: LPUART3 Receive Line Idle input is selected"] - Val67 = 67, - #[doc = "68: LPUART4 Received Data Word input is selected"] - Val68 = 68, - #[doc = "69: LPUART4 Transmitted Data Word input is selected"] - Val69 = 69, - #[doc = "70: LPUART4 Receive Line Idle input is selected"] - Val70 = 70, - #[doc = "71: AOI1_OUT0 input is selected"] - Val71 = 71, - #[doc = "72: AOI1_OUT1 input is selected"] - Val72 = 72, - #[doc = "73: AOI1_OUT2 input is selected"] - Val73 = 73, - #[doc = "74: AOI1_OUT3 input is selected"] - Val74 = 74, - #[doc = "75: ADC1_tcomp\\[0\\] input is selected"] - Val75 = 75, - #[doc = "76: ADC1_tcomp\\[1\\] input is selected"] - Val76 = 76, - #[doc = "77: ADC1_tcomp\\[2\\] input is selected"] - Val77 = 77, - #[doc = "78: ADC1_tcomp\\[3\\] input is selected"] - Val78 = 78, - #[doc = "79: CTimer2_MAT1 input is selected"] - Val79 = 79, - #[doc = "80: CTimer2_MAT2 input is selected"] - Val80 = 80, - #[doc = "81: CTimer2_MAT3 input is selected"] - Val81 = 81, - #[doc = "82: CTimer3_MAT1 input is selected"] - Val82 = 82, - #[doc = "83: CTimer3_MAT2 input is selected"] - Val83 = 83, - #[doc = "84: CTimer3_MAT3 input is selected"] - Val84 = 84, - #[doc = "85: QDC1_CMP_FLAG0 input is selected"] - Val85 = 85, - #[doc = "86: QDC1_CMP_FLAG1 input is selected"] - Val86 = 86, - #[doc = "87: QDC1_CMP_FLAG2 input is selected"] - Val87 = 87, - #[doc = "88: QDC1_CMP_FLAG3 input is selected"] - Val88 = 88, - #[doc = "89: QDC1_POS_MATCH0 input is selected"] - Val89 = 89, - #[doc = "90: PWM1_SM0_MUX_TRIG0 input is selected"] - Val90 = 90, - #[doc = "91: PWM1_SM1_MUX_TRIG0 input is selected"] - Val91 = 91, - #[doc = "92: PWM1_SM2_MUX_TRIG0 input is selected"] - Val92 = 92, - #[doc = "93: PWM1_SM2_MUX_TRIG0 input is selected"] - Val93 = 93, - #[doc = "94: LPI2C2 Master End of Packet input is selected"] - Val94 = 94, - #[doc = "95: LPI2C2 Slave End of Packet input is selected"] - Val95 = 95, - #[doc = "96: LPI2C3 Master End of Packet input is selected"] - Val96 = 96, - #[doc = "97: LPI2C3 Slave End of Packet input is selected"] - Val97 = 97, - #[doc = "98: LPUART5 Received Data Word input is selected"] - Val98 = 98, - #[doc = "99: LPUART5 Transmitted Data Word input is selected"] - Val99 = 99, - #[doc = "100: LPUART5 Receive Line Idle input is selected"] - Val100 = 100, - #[doc = "105: ADC2_tcomp\\[0\\] input is selected"] - Val105 = 105, - #[doc = "106: ADC2_tcomp\\[1\\] input is selected"] - Val106 = 106, - #[doc = "107: ADC2_tcomp\\[2\\] input is selected"] - Val107 = 107, - #[doc = "108: ADC2_tcomp\\[3\\] input is selected"] - Val108 = 108, - #[doc = "109: ADC3_tcomp\\[0\\] input is selected"] - Val109 = 109, - #[doc = "110: ADC3_tcomp\\[1\\] input is selected"] - Val110 = 110, - #[doc = "111: ADC3_tcomp\\[2\\] input is selected"] - Val111 = 111, - #[doc = "112: ADC3_tcomp\\[3\\] input is selected"] - Val112 = 112, - #[doc = "113: TRIG_IN0 input is selected"] - Val113 = 113, - #[doc = "114: TRIG_IN1 input is selected"] - Val114 = 114, - #[doc = "115: TRIG_IN2 input is selected"] - Val115 = 115, - #[doc = "116: TRIG_IN3 input is selected"] - Val116 = 116, - #[doc = "117: TRIG_IN4 input is selected"] - Val117 = 117, - #[doc = "118: TRIG_IN5 input is selected"] - Val118 = 118, - #[doc = "119: TRIG_IN6 input is selected"] - Val119 = 119, - #[doc = "120: TRIG_IN7 input is selected"] - Val120 = 120, - #[doc = "121: TRIG_IN8 input is selected"] - Val121 = 121, - #[doc = "122: TRIG_IN9 input is selected"] - Val122 = 122, - #[doc = "123: TRIG_IN10 input is selected"] - Val123 = 123, - #[doc = "124: TRIG_IN11 input is selected"] - Val124 = 124, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - Input number for CTIMER4"] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - 7 => Some(Inp::Val7), - 8 => Some(Inp::Val8), - 9 => Some(Inp::Val9), - 10 => Some(Inp::Val10), - 11 => Some(Inp::Val11), - 12 => Some(Inp::Val12), - 13 => Some(Inp::Val13), - 14 => Some(Inp::Val14), - 15 => Some(Inp::Val15), - 16 => Some(Inp::Val16), - 17 => Some(Inp::Val17), - 18 => Some(Inp::Val18), - 19 => Some(Inp::Val19), - 20 => Some(Inp::Val20), - 21 => Some(Inp::Val21), - 22 => Some(Inp::Val22), - 23 => Some(Inp::Val23), - 24 => Some(Inp::Val24), - 25 => Some(Inp::Val25), - 26 => Some(Inp::Val26), - 27 => Some(Inp::Val27), - 28 => Some(Inp::Val28), - 29 => Some(Inp::Val29), - 30 => Some(Inp::Val30), - 31 => Some(Inp::Val31), - 32 => Some(Inp::Val32), - 33 => Some(Inp::Val33), - 34 => Some(Inp::Val34), - 35 => Some(Inp::Val35), - 36 => Some(Inp::Val36), - 37 => Some(Inp::Val37), - 38 => Some(Inp::Val38), - 39 => Some(Inp::Val39), - 40 => Some(Inp::Val40), - 41 => Some(Inp::Val41), - 42 => Some(Inp::Val42), - 43 => Some(Inp::Val43), - 44 => Some(Inp::Val44), - 45 => Some(Inp::Val45), - 46 => Some(Inp::Val46), - 47 => Some(Inp::Val47), - 48 => Some(Inp::Val48), - 49 => Some(Inp::Val49), - 50 => Some(Inp::Val50), - 51 => Some(Inp::Val51), - 52 => Some(Inp::Val52), - 53 => Some(Inp::Val53), - 54 => Some(Inp::Val54), - 55 => Some(Inp::Val55), - 56 => Some(Inp::Val56), - 57 => Some(Inp::Val57), - 58 => Some(Inp::Val58), - 59 => Some(Inp::Val59), - 60 => Some(Inp::Val60), - 61 => Some(Inp::Val61), - 62 => Some(Inp::Val62), - 63 => Some(Inp::Val63), - 64 => Some(Inp::Val64), - 65 => Some(Inp::Val65), - 66 => Some(Inp::Val66), - 67 => Some(Inp::Val67), - 68 => Some(Inp::Val68), - 69 => Some(Inp::Val69), - 70 => Some(Inp::Val70), - 71 => Some(Inp::Val71), - 72 => Some(Inp::Val72), - 73 => Some(Inp::Val73), - 74 => Some(Inp::Val74), - 75 => Some(Inp::Val75), - 76 => Some(Inp::Val76), - 77 => Some(Inp::Val77), - 78 => Some(Inp::Val78), - 79 => Some(Inp::Val79), - 80 => Some(Inp::Val80), - 81 => Some(Inp::Val81), - 82 => Some(Inp::Val82), - 83 => Some(Inp::Val83), - 84 => Some(Inp::Val84), - 85 => Some(Inp::Val85), - 86 => Some(Inp::Val86), - 87 => Some(Inp::Val87), - 88 => Some(Inp::Val88), - 89 => Some(Inp::Val89), - 90 => Some(Inp::Val90), - 91 => Some(Inp::Val91), - 92 => Some(Inp::Val92), - 93 => Some(Inp::Val93), - 94 => Some(Inp::Val94), - 95 => Some(Inp::Val95), - 96 => Some(Inp::Val96), - 97 => Some(Inp::Val97), - 98 => Some(Inp::Val98), - 99 => Some(Inp::Val99), - 100 => Some(Inp::Val100), - 105 => Some(Inp::Val105), - 106 => Some(Inp::Val106), - 107 => Some(Inp::Val107), - 108 => Some(Inp::Val108), - 109 => Some(Inp::Val109), - 110 => Some(Inp::Val110), - 111 => Some(Inp::Val111), - 112 => Some(Inp::Val112), - 113 => Some(Inp::Val113), - 114 => Some(Inp::Val114), - 115 => Some(Inp::Val115), - 116 => Some(Inp::Val116), - 117 => Some(Inp::Val117), - 118 => Some(Inp::Val118), - 119 => Some(Inp::Val119), - 120 => Some(Inp::Val120), - 121 => Some(Inp::Val121), - 122 => Some(Inp::Val122), - 123 => Some(Inp::Val123), - 124 => Some(Inp::Val124), - _ => None, - } - } - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn is_val7(&self) -> bool { - *self == Inp::Val7 - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn is_val8(&self) -> bool { - *self == Inp::Val8 - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn is_val9(&self) -> bool { - *self == Inp::Val9 - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn is_val10(&self) -> bool { - *self == Inp::Val10 - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn is_val11(&self) -> bool { - *self == Inp::Val11 - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn is_val12(&self) -> bool { - *self == Inp::Val12 - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn is_val13(&self) -> bool { - *self == Inp::Val13 - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn is_val14(&self) -> bool { - *self == Inp::Val14 - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn is_val15(&self) -> bool { - *self == Inp::Val15 - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn is_val16(&self) -> bool { - *self == Inp::Val16 - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn is_val17(&self) -> bool { - *self == Inp::Val17 - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn is_val18(&self) -> bool { - *self == Inp::Val18 - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn is_val19(&self) -> bool { - *self == Inp::Val19 - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn is_val20(&self) -> bool { - *self == Inp::Val20 - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn is_val21(&self) -> bool { - *self == Inp::Val21 - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn is_val22(&self) -> bool { - *self == Inp::Val22 - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn is_val23(&self) -> bool { - *self == Inp::Val23 - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn is_val24(&self) -> bool { - *self == Inp::Val24 - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn is_val25(&self) -> bool { - *self == Inp::Val25 - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn is_val26(&self) -> bool { - *self == Inp::Val26 - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn is_val27(&self) -> bool { - *self == Inp::Val27 - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn is_val28(&self) -> bool { - *self == Inp::Val28 - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val29(&self) -> bool { - *self == Inp::Val29 - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn is_val30(&self) -> bool { - *self == Inp::Val30 - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn is_val31(&self) -> bool { - *self == Inp::Val31 - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn is_val32(&self) -> bool { - *self == Inp::Val32 - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn is_val33(&self) -> bool { - *self == Inp::Val33 - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn is_val34(&self) -> bool { - *self == Inp::Val34 - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn is_val35(&self) -> bool { - *self == Inp::Val35 - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn is_val36(&self) -> bool { - *self == Inp::Val36 - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn is_val37(&self) -> bool { - *self == Inp::Val37 - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn is_val38(&self) -> bool { - *self == Inp::Val38 - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn is_val39(&self) -> bool { - *self == Inp::Val39 - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val40(&self) -> bool { - *self == Inp::Val40 - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val41(&self) -> bool { - *self == Inp::Val41 - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val42(&self) -> bool { - *self == Inp::Val42 - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val43(&self) -> bool { - *self == Inp::Val43 - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val44(&self) -> bool { - *self == Inp::Val44 - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val45(&self) -> bool { - *self == Inp::Val45 - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val46(&self) -> bool { - *self == Inp::Val46 - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val47(&self) -> bool { - *self == Inp::Val47 - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val48(&self) -> bool { - *self == Inp::Val48 - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val49(&self) -> bool { - *self == Inp::Val49 - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val50(&self) -> bool { - *self == Inp::Val50 - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val51(&self) -> bool { - *self == Inp::Val51 - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn is_val52(&self) -> bool { - *self == Inp::Val52 - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val53(&self) -> bool { - *self == Inp::Val53 - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn is_val54(&self) -> bool { - *self == Inp::Val54 - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val55(&self) -> bool { - *self == Inp::Val55 - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val56(&self) -> bool { - *self == Inp::Val56 - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val57(&self) -> bool { - *self == Inp::Val57 - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val58(&self) -> bool { - *self == Inp::Val58 - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val59(&self) -> bool { - *self == Inp::Val59 - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val60(&self) -> bool { - *self == Inp::Val60 - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val61(&self) -> bool { - *self == Inp::Val61 - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val62(&self) -> bool { - *self == Inp::Val62 - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val63(&self) -> bool { - *self == Inp::Val63 - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val64(&self) -> bool { - *self == Inp::Val64 - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val65(&self) -> bool { - *self == Inp::Val65 - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val66(&self) -> bool { - *self == Inp::Val66 - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val67(&self) -> bool { - *self == Inp::Val67 - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val68(&self) -> bool { - *self == Inp::Val68 - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val69(&self) -> bool { - *self == Inp::Val69 - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val70(&self) -> bool { - *self == Inp::Val70 - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn is_val71(&self) -> bool { - *self == Inp::Val71 - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn is_val72(&self) -> bool { - *self == Inp::Val72 - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn is_val73(&self) -> bool { - *self == Inp::Val73 - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn is_val74(&self) -> bool { - *self == Inp::Val74 - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val75(&self) -> bool { - *self == Inp::Val75 - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val76(&self) -> bool { - *self == Inp::Val76 - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val77(&self) -> bool { - *self == Inp::Val77 - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val78(&self) -> bool { - *self == Inp::Val78 - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn is_val79(&self) -> bool { - *self == Inp::Val79 - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn is_val80(&self) -> bool { - *self == Inp::Val80 - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn is_val81(&self) -> bool { - *self == Inp::Val81 - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn is_val82(&self) -> bool { - *self == Inp::Val82 - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn is_val83(&self) -> bool { - *self == Inp::Val83 - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn is_val84(&self) -> bool { - *self == Inp::Val84 - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn is_val85(&self) -> bool { - *self == Inp::Val85 - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn is_val86(&self) -> bool { - *self == Inp::Val86 - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn is_val87(&self) -> bool { - *self == Inp::Val87 - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn is_val88(&self) -> bool { - *self == Inp::Val88 - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn is_val89(&self) -> bool { - *self == Inp::Val89 - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val90(&self) -> bool { - *self == Inp::Val90 - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val91(&self) -> bool { - *self == Inp::Val91 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val92(&self) -> bool { - *self == Inp::Val92 - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn is_val93(&self) -> bool { - *self == Inp::Val93 - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val94(&self) -> bool { - *self == Inp::Val94 - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val95(&self) -> bool { - *self == Inp::Val95 - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn is_val96(&self) -> bool { - *self == Inp::Val96 - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn is_val97(&self) -> bool { - *self == Inp::Val97 - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn is_val98(&self) -> bool { - *self == Inp::Val98 - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn is_val99(&self) -> bool { - *self == Inp::Val99 - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn is_val100(&self) -> bool { - *self == Inp::Val100 - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val105(&self) -> bool { - *self == Inp::Val105 - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val106(&self) -> bool { - *self == Inp::Val106 - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val107(&self) -> bool { - *self == Inp::Val107 - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val108(&self) -> bool { - *self == Inp::Val108 - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn is_val109(&self) -> bool { - *self == Inp::Val109 - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn is_val110(&self) -> bool { - *self == Inp::Val110 - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn is_val111(&self) -> bool { - *self == Inp::Val111 - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn is_val112(&self) -> bool { - *self == Inp::Val112 - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn is_val113(&self) -> bool { - *self == Inp::Val113 - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn is_val114(&self) -> bool { - *self == Inp::Val114 - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn is_val115(&self) -> bool { - *self == Inp::Val115 - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn is_val116(&self) -> bool { - *self == Inp::Val116 - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn is_val117(&self) -> bool { - *self == Inp::Val117 - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn is_val118(&self) -> bool { - *self == Inp::Val118 - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn is_val119(&self) -> bool { - *self == Inp::Val119 - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn is_val120(&self) -> bool { - *self == Inp::Val120 - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn is_val121(&self) -> bool { - *self == Inp::Val121 - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn is_val122(&self) -> bool { - *self == Inp::Val122 - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn is_val123(&self) -> bool { - *self == Inp::Val123 - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn is_val124(&self) -> bool { - *self == Inp::Val124 - } -} -#[doc = "Field `INP` writer - Input number for CTIMER4"] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 7, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CT_INP0 input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "CT_INP1 input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "CT_INP2 input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "CT_INP3 input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "CT_INP4 input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "CT_INP5 input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } - #[doc = "CT_INP6 input is selected"] - #[inline(always)] - pub fn val7(self) -> &'a mut crate::W { - self.variant(Inp::Val7) - } - #[doc = "CT_INP7 input is selected"] - #[inline(always)] - pub fn val8(self) -> &'a mut crate::W { - self.variant(Inp::Val8) - } - #[doc = "CT_INP8 input is selected"] - #[inline(always)] - pub fn val9(self) -> &'a mut crate::W { - self.variant(Inp::Val9) - } - #[doc = "CT_INP9 input is selected"] - #[inline(always)] - pub fn val10(self) -> &'a mut crate::W { - self.variant(Inp::Val10) - } - #[doc = "CT_INP10 input is selected"] - #[inline(always)] - pub fn val11(self) -> &'a mut crate::W { - self.variant(Inp::Val11) - } - #[doc = "CT_INP11 input is selected"] - #[inline(always)] - pub fn val12(self) -> &'a mut crate::W { - self.variant(Inp::Val12) - } - #[doc = "CT_INP12 input is selected"] - #[inline(always)] - pub fn val13(self) -> &'a mut crate::W { - self.variant(Inp::Val13) - } - #[doc = "CT_INP13 input is selected"] - #[inline(always)] - pub fn val14(self) -> &'a mut crate::W { - self.variant(Inp::Val14) - } - #[doc = "CT_INP14 input is selected"] - #[inline(always)] - pub fn val15(self) -> &'a mut crate::W { - self.variant(Inp::Val15) - } - #[doc = "CT_INP15 input is selected"] - #[inline(always)] - pub fn val16(self) -> &'a mut crate::W { - self.variant(Inp::Val16) - } - #[doc = "CT_INP16 input is selected"] - #[inline(always)] - pub fn val17(self) -> &'a mut crate::W { - self.variant(Inp::Val17) - } - #[doc = "CT_INP17 input is selected"] - #[inline(always)] - pub fn val18(self) -> &'a mut crate::W { - self.variant(Inp::Val18) - } - #[doc = "CT_INP18 input is selected"] - #[inline(always)] - pub fn val19(self) -> &'a mut crate::W { - self.variant(Inp::Val19) - } - #[doc = "CT_INP19 input is selected"] - #[inline(always)] - pub fn val20(self) -> &'a mut crate::W { - self.variant(Inp::Val20) - } - #[doc = "USB0 usb0 start of frame input is selected"] - #[inline(always)] - pub fn val21(self) -> &'a mut crate::W { - self.variant(Inp::Val21) - } - #[doc = "AOI0_OUT0 input is selected"] - #[inline(always)] - pub fn val22(self) -> &'a mut crate::W { - self.variant(Inp::Val22) - } - #[doc = "AOI0_OUT1 input is selected"] - #[inline(always)] - pub fn val23(self) -> &'a mut crate::W { - self.variant(Inp::Val23) - } - #[doc = "AOI0_OUT2 input is selected"] - #[inline(always)] - pub fn val24(self) -> &'a mut crate::W { - self.variant(Inp::Val24) - } - #[doc = "AOI0_OUT3 input is selected"] - #[inline(always)] - pub fn val25(self) -> &'a mut crate::W { - self.variant(Inp::Val25) - } - #[doc = "ADC0_tcomp\\[0\\]"] - #[inline(always)] - pub fn val26(self) -> &'a mut crate::W { - self.variant(Inp::Val26) - } - #[doc = "ADC0_tcomp\\[1\\]"] - #[inline(always)] - pub fn val27(self) -> &'a mut crate::W { - self.variant(Inp::Val27) - } - #[doc = "ADC0_tcomp\\[2\\]"] - #[inline(always)] - pub fn val28(self) -> &'a mut crate::W { - self.variant(Inp::Val28) - } - #[doc = "ADC0_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val29(self) -> &'a mut crate::W { - self.variant(Inp::Val29) - } - #[doc = "CMP0_OUT is selected"] - #[inline(always)] - pub fn val30(self) -> &'a mut crate::W { - self.variant(Inp::Val30) - } - #[doc = "CMP1_OUT is selected"] - #[inline(always)] - pub fn val31(self) -> &'a mut crate::W { - self.variant(Inp::Val31) - } - #[doc = "CMP2_OUT is selected"] - #[inline(always)] - pub fn val32(self) -> &'a mut crate::W { - self.variant(Inp::Val32) - } - #[doc = "CTimer0_MAT1 input is selected"] - #[inline(always)] - pub fn val33(self) -> &'a mut crate::W { - self.variant(Inp::Val33) - } - #[doc = "CTimer0_MAT2 input is selected"] - #[inline(always)] - pub fn val34(self) -> &'a mut crate::W { - self.variant(Inp::Val34) - } - #[doc = "CTimer0_MAT3 input is selected"] - #[inline(always)] - pub fn val35(self) -> &'a mut crate::W { - self.variant(Inp::Val35) - } - #[doc = "CTimer1_MAT1 input is selected"] - #[inline(always)] - pub fn val36(self) -> &'a mut crate::W { - self.variant(Inp::Val36) - } - #[doc = "CTimer1_MAT2 input is selected"] - #[inline(always)] - pub fn val37(self) -> &'a mut crate::W { - self.variant(Inp::Val37) - } - #[doc = "CTimer1_MAT3 input is selected"] - #[inline(always)] - pub fn val38(self) -> &'a mut crate::W { - self.variant(Inp::Val38) - } - #[doc = "QDC0_CMP_FLAG0 is selected"] - #[inline(always)] - pub fn val39(self) -> &'a mut crate::W { - self.variant(Inp::Val39) - } - #[doc = "QDC0_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val40(self) -> &'a mut crate::W { - self.variant(Inp::Val40) - } - #[doc = "QDC0_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val41(self) -> &'a mut crate::W { - self.variant(Inp::Val41) - } - #[doc = "QDC0_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val42(self) -> &'a mut crate::W { - self.variant(Inp::Val42) - } - #[doc = "QDC0_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val43(self) -> &'a mut crate::W { - self.variant(Inp::Val43) - } - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val44(self) -> &'a mut crate::W { - self.variant(Inp::Val44) - } - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val45(self) -> &'a mut crate::W { - self.variant(Inp::Val45) - } - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val46(self) -> &'a mut crate::W { - self.variant(Inp::Val46) - } - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val47(self) -> &'a mut crate::W { - self.variant(Inp::Val47) - } - #[doc = "LPI2C0 Master End of Packet input is selected"] - #[inline(always)] - pub fn val48(self) -> &'a mut crate::W { - self.variant(Inp::Val48) - } - #[doc = "LPI2C0 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val49(self) -> &'a mut crate::W { - self.variant(Inp::Val49) - } - #[doc = "LPI2C1 Master End of Packet input is selected"] - #[inline(always)] - pub fn val50(self) -> &'a mut crate::W { - self.variant(Inp::Val50) - } - #[doc = "LPI2C1 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val51(self) -> &'a mut crate::W { - self.variant(Inp::Val51) - } - #[doc = "LPSPI0 End of Frame input is selected"] - #[inline(always)] - pub fn val52(self) -> &'a mut crate::W { - self.variant(Inp::Val52) - } - #[doc = "LPSPI0 Received Data Word input is selected"] - #[inline(always)] - pub fn val53(self) -> &'a mut crate::W { - self.variant(Inp::Val53) - } - #[doc = "LPSPI1 End of Frame input is selected"] - #[inline(always)] - pub fn val54(self) -> &'a mut crate::W { - self.variant(Inp::Val54) - } - #[doc = "LPSPI1 Received Data Word input is selected"] - #[inline(always)] - pub fn val55(self) -> &'a mut crate::W { - self.variant(Inp::Val55) - } - #[doc = "LPUART0 Received Data Word input is selected"] - #[inline(always)] - pub fn val56(self) -> &'a mut crate::W { - self.variant(Inp::Val56) - } - #[doc = "LPUART0 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val57(self) -> &'a mut crate::W { - self.variant(Inp::Val57) - } - #[doc = "LPUART0 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val58(self) -> &'a mut crate::W { - self.variant(Inp::Val58) - } - #[doc = "LPUART1 Received Data Word input is selected"] - #[inline(always)] - pub fn val59(self) -> &'a mut crate::W { - self.variant(Inp::Val59) - } - #[doc = "LPUART1 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val60(self) -> &'a mut crate::W { - self.variant(Inp::Val60) - } - #[doc = "LPUART1 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val61(self) -> &'a mut crate::W { - self.variant(Inp::Val61) - } - #[doc = "LPUART2 Received Data Word input is selected"] - #[inline(always)] - pub fn val62(self) -> &'a mut crate::W { - self.variant(Inp::Val62) - } - #[doc = "LPUART2 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val63(self) -> &'a mut crate::W { - self.variant(Inp::Val63) - } - #[doc = "LPUART2 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val64(self) -> &'a mut crate::W { - self.variant(Inp::Val64) - } - #[doc = "LPUART3 Received Data Word input is selected"] - #[inline(always)] - pub fn val65(self) -> &'a mut crate::W { - self.variant(Inp::Val65) - } - #[doc = "LPUART3 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val66(self) -> &'a mut crate::W { - self.variant(Inp::Val66) - } - #[doc = "LPUART3 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val67(self) -> &'a mut crate::W { - self.variant(Inp::Val67) - } - #[doc = "LPUART4 Received Data Word input is selected"] - #[inline(always)] - pub fn val68(self) -> &'a mut crate::W { - self.variant(Inp::Val68) - } - #[doc = "LPUART4 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val69(self) -> &'a mut crate::W { - self.variant(Inp::Val69) - } - #[doc = "LPUART4 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val70(self) -> &'a mut crate::W { - self.variant(Inp::Val70) - } - #[doc = "AOI1_OUT0 input is selected"] - #[inline(always)] - pub fn val71(self) -> &'a mut crate::W { - self.variant(Inp::Val71) - } - #[doc = "AOI1_OUT1 input is selected"] - #[inline(always)] - pub fn val72(self) -> &'a mut crate::W { - self.variant(Inp::Val72) - } - #[doc = "AOI1_OUT2 input is selected"] - #[inline(always)] - pub fn val73(self) -> &'a mut crate::W { - self.variant(Inp::Val73) - } - #[doc = "AOI1_OUT3 input is selected"] - #[inline(always)] - pub fn val74(self) -> &'a mut crate::W { - self.variant(Inp::Val74) - } - #[doc = "ADC1_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val75(self) -> &'a mut crate::W { - self.variant(Inp::Val75) - } - #[doc = "ADC1_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val76(self) -> &'a mut crate::W { - self.variant(Inp::Val76) - } - #[doc = "ADC1_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val77(self) -> &'a mut crate::W { - self.variant(Inp::Val77) - } - #[doc = "ADC1_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val78(self) -> &'a mut crate::W { - self.variant(Inp::Val78) - } - #[doc = "CTimer2_MAT1 input is selected"] - #[inline(always)] - pub fn val79(self) -> &'a mut crate::W { - self.variant(Inp::Val79) - } - #[doc = "CTimer2_MAT2 input is selected"] - #[inline(always)] - pub fn val80(self) -> &'a mut crate::W { - self.variant(Inp::Val80) - } - #[doc = "CTimer2_MAT3 input is selected"] - #[inline(always)] - pub fn val81(self) -> &'a mut crate::W { - self.variant(Inp::Val81) - } - #[doc = "CTimer3_MAT1 input is selected"] - #[inline(always)] - pub fn val82(self) -> &'a mut crate::W { - self.variant(Inp::Val82) - } - #[doc = "CTimer3_MAT2 input is selected"] - #[inline(always)] - pub fn val83(self) -> &'a mut crate::W { - self.variant(Inp::Val83) - } - #[doc = "CTimer3_MAT3 input is selected"] - #[inline(always)] - pub fn val84(self) -> &'a mut crate::W { - self.variant(Inp::Val84) - } - #[doc = "QDC1_CMP_FLAG0 input is selected"] - #[inline(always)] - pub fn val85(self) -> &'a mut crate::W { - self.variant(Inp::Val85) - } - #[doc = "QDC1_CMP_FLAG1 input is selected"] - #[inline(always)] - pub fn val86(self) -> &'a mut crate::W { - self.variant(Inp::Val86) - } - #[doc = "QDC1_CMP_FLAG2 input is selected"] - #[inline(always)] - pub fn val87(self) -> &'a mut crate::W { - self.variant(Inp::Val87) - } - #[doc = "QDC1_CMP_FLAG3 input is selected"] - #[inline(always)] - pub fn val88(self) -> &'a mut crate::W { - self.variant(Inp::Val88) - } - #[doc = "QDC1_POS_MATCH0 input is selected"] - #[inline(always)] - pub fn val89(self) -> &'a mut crate::W { - self.variant(Inp::Val89) - } - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val90(self) -> &'a mut crate::W { - self.variant(Inp::Val90) - } - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val91(self) -> &'a mut crate::W { - self.variant(Inp::Val91) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val92(self) -> &'a mut crate::W { - self.variant(Inp::Val92) - } - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected"] - #[inline(always)] - pub fn val93(self) -> &'a mut crate::W { - self.variant(Inp::Val93) - } - #[doc = "LPI2C2 Master End of Packet input is selected"] - #[inline(always)] - pub fn val94(self) -> &'a mut crate::W { - self.variant(Inp::Val94) - } - #[doc = "LPI2C2 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val95(self) -> &'a mut crate::W { - self.variant(Inp::Val95) - } - #[doc = "LPI2C3 Master End of Packet input is selected"] - #[inline(always)] - pub fn val96(self) -> &'a mut crate::W { - self.variant(Inp::Val96) - } - #[doc = "LPI2C3 Slave End of Packet input is selected"] - #[inline(always)] - pub fn val97(self) -> &'a mut crate::W { - self.variant(Inp::Val97) - } - #[doc = "LPUART5 Received Data Word input is selected"] - #[inline(always)] - pub fn val98(self) -> &'a mut crate::W { - self.variant(Inp::Val98) - } - #[doc = "LPUART5 Transmitted Data Word input is selected"] - #[inline(always)] - pub fn val99(self) -> &'a mut crate::W { - self.variant(Inp::Val99) - } - #[doc = "LPUART5 Receive Line Idle input is selected"] - #[inline(always)] - pub fn val100(self) -> &'a mut crate::W { - self.variant(Inp::Val100) - } - #[doc = "ADC2_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val105(self) -> &'a mut crate::W { - self.variant(Inp::Val105) - } - #[doc = "ADC2_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val106(self) -> &'a mut crate::W { - self.variant(Inp::Val106) - } - #[doc = "ADC2_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val107(self) -> &'a mut crate::W { - self.variant(Inp::Val107) - } - #[doc = "ADC2_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val108(self) -> &'a mut crate::W { - self.variant(Inp::Val108) - } - #[doc = "ADC3_tcomp\\[0\\] input is selected"] - #[inline(always)] - pub fn val109(self) -> &'a mut crate::W { - self.variant(Inp::Val109) - } - #[doc = "ADC3_tcomp\\[1\\] input is selected"] - #[inline(always)] - pub fn val110(self) -> &'a mut crate::W { - self.variant(Inp::Val110) - } - #[doc = "ADC3_tcomp\\[2\\] input is selected"] - #[inline(always)] - pub fn val111(self) -> &'a mut crate::W { - self.variant(Inp::Val111) - } - #[doc = "ADC3_tcomp\\[3\\] input is selected"] - #[inline(always)] - pub fn val112(self) -> &'a mut crate::W { - self.variant(Inp::Val112) - } - #[doc = "TRIG_IN0 input is selected"] - #[inline(always)] - pub fn val113(self) -> &'a mut crate::W { - self.variant(Inp::Val113) - } - #[doc = "TRIG_IN1 input is selected"] - #[inline(always)] - pub fn val114(self) -> &'a mut crate::W { - self.variant(Inp::Val114) - } - #[doc = "TRIG_IN2 input is selected"] - #[inline(always)] - pub fn val115(self) -> &'a mut crate::W { - self.variant(Inp::Val115) - } - #[doc = "TRIG_IN3 input is selected"] - #[inline(always)] - pub fn val116(self) -> &'a mut crate::W { - self.variant(Inp::Val116) - } - #[doc = "TRIG_IN4 input is selected"] - #[inline(always)] - pub fn val117(self) -> &'a mut crate::W { - self.variant(Inp::Val117) - } - #[doc = "TRIG_IN5 input is selected"] - #[inline(always)] - pub fn val118(self) -> &'a mut crate::W { - self.variant(Inp::Val118) - } - #[doc = "TRIG_IN6 input is selected"] - #[inline(always)] - pub fn val119(self) -> &'a mut crate::W { - self.variant(Inp::Val119) - } - #[doc = "TRIG_IN7 input is selected"] - #[inline(always)] - pub fn val120(self) -> &'a mut crate::W { - self.variant(Inp::Val120) - } - #[doc = "TRIG_IN8 input is selected"] - #[inline(always)] - pub fn val121(self) -> &'a mut crate::W { - self.variant(Inp::Val121) - } - #[doc = "TRIG_IN9 input is selected"] - #[inline(always)] - pub fn val122(self) -> &'a mut crate::W { - self.variant(Inp::Val122) - } - #[doc = "TRIG_IN10 input is selected"] - #[inline(always)] - pub fn val123(self) -> &'a mut crate::W { - self.variant(Inp::Val123) - } - #[doc = "TRIG_IN11 input is selected"] - #[inline(always)] - pub fn val124(self) -> &'a mut crate::W { - self.variant(Inp::Val124) - } -} -impl R { - #[doc = "Bits 0:6 - Input number for CTIMER4"] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:6 - Input number for CTIMER4"] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "Trigger register for TIMER4\n\nYou can [`read`](crate::Reg::read) this register and get [`timer4trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer4trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Timer4trigSpec; -impl crate::RegisterSpec for Timer4trigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`timer4trig::R`](R) reader structure"] -impl crate::Readable for Timer4trigSpec {} -#[doc = "`write(|w| ..)` method takes [`timer4trig::W`](W) writer structure"] -impl crate::Writable for Timer4trigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TIMER4TRIG to value 0x7f"] -impl crate::Resettable for Timer4trigSpec { - const RESET_VALUE: u32 = 0x7f; -} diff --git a/mcxa276-pac/src/inputmux0/trigfil.rs b/mcxa276-pac/src/inputmux0/trigfil.rs deleted file mode 100644 index be56269fa..000000000 --- a/mcxa276-pac/src/inputmux0/trigfil.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `TRIGFIL[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `TRIGFIL[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `FILT_PER` reader - Input Filter Sample Period"] -pub type FiltPerR = crate::FieldReader; -#[doc = "Field `FILT_PER` writer - Input Filter Sample Period"] -pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `FILT_CNT` reader - Input Filter Sample Count"] -pub type FiltCntR = crate::FieldReader; -#[doc = "Field `FILT_CNT` writer - Input Filter Sample Count"] -pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:7 - Input Filter Sample Period"] - #[inline(always)] - pub fn filt_per(&self) -> FiltPerR { - FiltPerR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Input Filter Sample Count"] - #[inline(always)] - pub fn filt_cnt(&self) -> FiltCntR { - FiltCntR::new(((self.bits >> 8) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Input Filter Sample Period"] - #[inline(always)] - pub fn filt_per(&mut self) -> FiltPerW { - FiltPerW::new(self, 0) - } - #[doc = "Bits 8:10 - Input Filter Sample Count"] - #[inline(always)] - pub fn filt_cnt(&mut self) -> FiltCntW { - FiltCntW::new(self, 8) - } -} -#[doc = "TRIGFIL control\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TrigfilSpec; -impl crate::RegisterSpec for TrigfilSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`trigfil::R`](R) reader structure"] -impl crate::Readable for TrigfilSpec {} -#[doc = "`write(|w| ..)` method takes [`trigfil::W`](W) writer structure"] -impl crate::Writable for TrigfilSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TRIGFIL[%s] to value 0"] -impl crate::Resettable for TrigfilSpec {} diff --git a/mcxa276-pac/src/inputmux0/trigfil_prsc.rs b/mcxa276-pac/src/inputmux0/trigfil_prsc.rs deleted file mode 100644 index 01ca959ae..000000000 --- a/mcxa276-pac/src/inputmux0/trigfil_prsc.rs +++ /dev/null @@ -1,180 +0,0 @@ -#[doc = "Register `TRIGFIL_PRSC` reader"] -pub type R = crate::R; -#[doc = "Register `TRIGFIL_PRSC` writer"] -pub type W = crate::W; -#[doc = "Filter Prescaller Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum FiltScaleVal { - #[doc = "0: Bypass the clock"] - Val0 = 0, - #[doc = "1: Divide 2"] - Val1 = 1, - #[doc = "2: Divide 4"] - Val2 = 2, - #[doc = "3: Divide 8"] - Val3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: FiltScaleVal) -> Self { - variant as _ - } -} -impl crate::FieldSpec for FiltScaleVal { - type Ux = u8; -} -impl crate::IsEnum for FiltScaleVal {} -#[doc = "Field `FILT_SCALE_VAL` reader - Filter Prescaller Value"] -pub type FiltScaleValR = crate::FieldReader; -impl FiltScaleValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FiltScaleVal { - match self.bits { - 0 => FiltScaleVal::Val0, - 1 => FiltScaleVal::Val1, - 2 => FiltScaleVal::Val2, - 3 => FiltScaleVal::Val3, - _ => unreachable!(), - } - } - #[doc = "Bypass the clock"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == FiltScaleVal::Val0 - } - #[doc = "Divide 2"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == FiltScaleVal::Val1 - } - #[doc = "Divide 4"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == FiltScaleVal::Val2 - } - #[doc = "Divide 8"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == FiltScaleVal::Val3 - } -} -#[doc = "Field `FILT_SCALE_VAL` writer - Filter Prescaller Value"] -pub type FiltScaleValW<'a, REG> = crate::FieldWriter<'a, REG, 2, FiltScaleVal, crate::Safe>; -impl<'a, REG> FiltScaleValW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Bypass the clock"] - #[inline(always)] - pub fn val0(self) -> &'a mut crate::W { - self.variant(FiltScaleVal::Val0) - } - #[doc = "Divide 2"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(FiltScaleVal::Val1) - } - #[doc = "Divide 4"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(FiltScaleVal::Val2) - } - #[doc = "Divide 8"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(FiltScaleVal::Val3) - } -} -#[doc = "Enable trigger filter prescaller\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FiltScaleEn { - #[doc = "0: Disable prescaller"] - Val2 = 0, - #[doc = "1: Enabled prescaller"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FiltScaleEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILT_SCALE_EN` reader - Enable trigger filter prescaller"] -pub type FiltScaleEnR = crate::BitReader; -impl FiltScaleEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FiltScaleEn { - match self.bits { - false => FiltScaleEn::Val2, - true => FiltScaleEn::Val1, - } - } - #[doc = "Disable prescaller"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == FiltScaleEn::Val2 - } - #[doc = "Enabled prescaller"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == FiltScaleEn::Val1 - } -} -#[doc = "Field `FILT_SCALE_EN` writer - Enable trigger filter prescaller"] -pub type FiltScaleEnW<'a, REG> = crate::BitWriter<'a, REG, FiltScaleEn>; -impl<'a, REG> FiltScaleEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable prescaller"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(FiltScaleEn::Val2) - } - #[doc = "Enabled prescaller"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(FiltScaleEn::Val1) - } -} -impl R { - #[doc = "Bits 0:1 - Filter Prescaller Value"] - #[inline(always)] - pub fn filt_scale_val(&self) -> FiltScaleValR { - FiltScaleValR::new((self.bits & 3) as u8) - } - #[doc = "Bit 31 - Enable trigger filter prescaller"] - #[inline(always)] - pub fn filt_scale_en(&self) -> FiltScaleEnR { - FiltScaleEnR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - Filter Prescaller Value"] - #[inline(always)] - pub fn filt_scale_val(&mut self) -> FiltScaleValW { - FiltScaleValW::new(self, 0) - } - #[doc = "Bit 31 - Enable trigger filter prescaller"] - #[inline(always)] - pub fn filt_scale_en(&mut self) -> FiltScaleEnW { - FiltScaleEnW::new(self, 31) - } -} -#[doc = "Trigger filter prescaller\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_prsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil_prsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TrigfilPrscSpec; -impl crate::RegisterSpec for TrigfilPrscSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`trigfil_prsc::R`](R) reader structure"] -impl crate::Readable for TrigfilPrscSpec {} -#[doc = "`write(|w| ..)` method takes [`trigfil_prsc::W`](W) writer structure"] -impl crate::Writable for TrigfilPrscSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TRIGFIL_PRSC to value 0"] -impl crate::Resettable for TrigfilPrscSpec {} diff --git a/mcxa276-pac/src/inputmux0/trigfil_stat0.rs b/mcxa276-pac/src/inputmux0/trigfil_stat0.rs deleted file mode 100644 index 0474124c9..000000000 --- a/mcxa276-pac/src/inputmux0/trigfil_stat0.rs +++ /dev/null @@ -1,505 +0,0 @@ -#[doc = "Register `TRIGFIL_STAT0` reader"] -pub type R = crate::R; -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn0Val { - #[doc = "0: TRIG_IN0 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN0 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn0Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN0_VAL` reader - TRIG_IN value"] -pub type TrigIn0ValR = crate::BitReader; -impl TrigIn0ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn0Val { - match self.bits { - false => TrigIn0Val::Val0, - true => TrigIn0Val::Val1, - } - } - #[doc = "TRIG_IN0 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn0Val::Val0 - } - #[doc = "TRIG_IN0 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn0Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn1Val { - #[doc = "0: TRIG_IN1 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN1 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn1Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN1_VAL` reader - TRIG_IN value"] -pub type TrigIn1ValR = crate::BitReader; -impl TrigIn1ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn1Val { - match self.bits { - false => TrigIn1Val::Val0, - true => TrigIn1Val::Val1, - } - } - #[doc = "TRIG_IN1 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn1Val::Val0 - } - #[doc = "TRIG_IN1 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn1Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn2Val { - #[doc = "0: TRIG_IN2 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN2 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn2Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN2_VAL` reader - TRIG_IN value"] -pub type TrigIn2ValR = crate::BitReader; -impl TrigIn2ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn2Val { - match self.bits { - false => TrigIn2Val::Val0, - true => TrigIn2Val::Val1, - } - } - #[doc = "TRIG_IN2 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn2Val::Val0 - } - #[doc = "TRIG_IN2 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn2Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn3Val { - #[doc = "0: TRIG_IN3 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN3 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn3Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN3_VAL` reader - TRIG_IN value"] -pub type TrigIn3ValR = crate::BitReader; -impl TrigIn3ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn3Val { - match self.bits { - false => TrigIn3Val::Val0, - true => TrigIn3Val::Val1, - } - } - #[doc = "TRIG_IN3 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn3Val::Val0 - } - #[doc = "TRIG_IN3 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn3Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn4Val { - #[doc = "0: TRIG_IN4 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN4 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn4Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN4_VAL` reader - TRIG_IN value"] -pub type TrigIn4ValR = crate::BitReader; -impl TrigIn4ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn4Val { - match self.bits { - false => TrigIn4Val::Val0, - true => TrigIn4Val::Val1, - } - } - #[doc = "TRIG_IN4 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn4Val::Val0 - } - #[doc = "TRIG_IN4 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn4Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn5Val { - #[doc = "0: TRIG_IN5 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN5 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn5Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN5_VAL` reader - TRIG_IN value"] -pub type TrigIn5ValR = crate::BitReader; -impl TrigIn5ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn5Val { - match self.bits { - false => TrigIn5Val::Val0, - true => TrigIn5Val::Val1, - } - } - #[doc = "TRIG_IN5 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn5Val::Val0 - } - #[doc = "TRIG_IN5 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn5Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn6Val { - #[doc = "0: TRIG_IN6 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN6 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn6Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN6_VAL` reader - TRIG_IN value"] -pub type TrigIn6ValR = crate::BitReader; -impl TrigIn6ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn6Val { - match self.bits { - false => TrigIn6Val::Val0, - true => TrigIn6Val::Val1, - } - } - #[doc = "TRIG_IN6 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn6Val::Val0 - } - #[doc = "TRIG_IN6 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn6Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn7Val { - #[doc = "0: TRIG_IN7 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN7 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn7Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN7_VAL` reader - TRIG_IN value"] -pub type TrigIn7ValR = crate::BitReader; -impl TrigIn7ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn7Val { - match self.bits { - false => TrigIn7Val::Val0, - true => TrigIn7Val::Val1, - } - } - #[doc = "TRIG_IN7 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn7Val::Val0 - } - #[doc = "TRIG_IN7 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn7Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn8Val { - #[doc = "0: TRIG_IN8 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN8 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn8Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN8_VAL` reader - TRIG_IN value"] -pub type TrigIn8ValR = crate::BitReader; -impl TrigIn8ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn8Val { - match self.bits { - false => TrigIn8Val::Val0, - true => TrigIn8Val::Val1, - } - } - #[doc = "TRIG_IN8 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn8Val::Val0 - } - #[doc = "TRIG_IN8 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn8Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn9Val { - #[doc = "0: TRIG_IN9 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN9 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn9Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN9_VAL` reader - TRIG_IN value"] -pub type TrigIn9ValR = crate::BitReader; -impl TrigIn9ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn9Val { - match self.bits { - false => TrigIn9Val::Val0, - true => TrigIn9Val::Val1, - } - } - #[doc = "TRIG_IN9 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn9Val::Val0 - } - #[doc = "TRIG_IN9 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn9Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn10Val { - #[doc = "0: TRIG_IN10 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN10 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn10Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN10_VAL` reader - TRIG_IN value"] -pub type TrigIn10ValR = crate::BitReader; -impl TrigIn10ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn10Val { - match self.bits { - false => TrigIn10Val::Val0, - true => TrigIn10Val::Val1, - } - } - #[doc = "TRIG_IN10 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn10Val::Val0 - } - #[doc = "TRIG_IN10 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn10Val::Val1 - } -} -#[doc = "TRIG_IN value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrigIn11Val { - #[doc = "0: TRIG_IN11 is 0"] - Val0 = 0, - #[doc = "1: TRIG_IN11 is 1"] - Val1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrigIn11Val) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIG_IN11_VAL` reader - TRIG_IN value"] -pub type TrigIn11ValR = crate::BitReader; -impl TrigIn11ValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrigIn11Val { - match self.bits { - false => TrigIn11Val::Val0, - true => TrigIn11Val::Val1, - } - } - #[doc = "TRIG_IN11 is 0"] - #[inline(always)] - pub fn is_val0(&self) -> bool { - *self == TrigIn11Val::Val0 - } - #[doc = "TRIG_IN11 is 1"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == TrigIn11Val::Val1 - } -} -impl R { - #[doc = "Bit 0 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in0_val(&self) -> TrigIn0ValR { - TrigIn0ValR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in1_val(&self) -> TrigIn1ValR { - TrigIn1ValR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in2_val(&self) -> TrigIn2ValR { - TrigIn2ValR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in3_val(&self) -> TrigIn3ValR { - TrigIn3ValR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in4_val(&self) -> TrigIn4ValR { - TrigIn4ValR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in5_val(&self) -> TrigIn5ValR { - TrigIn5ValR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in6_val(&self) -> TrigIn6ValR { - TrigIn6ValR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in7_val(&self) -> TrigIn7ValR { - TrigIn7ValR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in8_val(&self) -> TrigIn8ValR { - TrigIn8ValR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in9_val(&self) -> TrigIn9ValR { - TrigIn9ValR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in10_val(&self) -> TrigIn10ValR { - TrigIn10ValR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - TRIG_IN value"] - #[inline(always)] - pub fn trig_in11_val(&self) -> TrigIn11ValR { - TrigIn11ValR::new(((self.bits >> 11) & 1) != 0) - } -} -#[doc = "Trigger filter stat\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_stat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TrigfilStat0Spec; -impl crate::RegisterSpec for TrigfilStat0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`trigfil_stat0::R`](R) reader structure"] -impl crate::Readable for TrigfilStat0Spec {} -#[doc = "`reset()` method sets TRIGFIL_STAT0 to value 0"] -impl crate::Resettable for TrigfilStat0Spec {} diff --git a/mcxa276-pac/src/inputmux0/usbfs_trig.rs b/mcxa276-pac/src/inputmux0/usbfs_trig.rs deleted file mode 100644 index ee5babf7b..000000000 --- a/mcxa276-pac/src/inputmux0/usbfs_trig.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `USBFS_TRIG` reader"] -pub type R = crate::R; -#[doc = "Register `USBFS_TRIG` writer"] -pub type W = crate::W; -#[doc = "USB-FS trigger input connections.\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Inp { - #[doc = "1: LPUART0 lpuart_trg_txdata input is selected"] - Val1 = 1, - #[doc = "2: LPUART1 lpuart_trg_txdata input is selected"] - Val2 = 2, - #[doc = "3: LPUART2 lpuart_trg_txdata input is selected"] - Val3 = 3, - #[doc = "4: LPUART3 lpuart_trg_txdata input is selected"] - Val4 = 4, - #[doc = "5: LPUART4 lpuart_trg_txdata input is selected"] - Val5 = 5, - #[doc = "6: LPUART5 lpuart_trg_txdata input is selected"] - Val6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Inp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Inp { - type Ux = u8; -} -impl crate::IsEnum for Inp {} -#[doc = "Field `INP` reader - USB-FS trigger input connections."] -pub type InpR = crate::FieldReader; -impl InpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Inp::Val1), - 2 => Some(Inp::Val2), - 3 => Some(Inp::Val3), - 4 => Some(Inp::Val4), - 5 => Some(Inp::Val5), - 6 => Some(Inp::Val6), - _ => None, - } - } - #[doc = "LPUART0 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn is_val1(&self) -> bool { - *self == Inp::Val1 - } - #[doc = "LPUART1 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn is_val2(&self) -> bool { - *self == Inp::Val2 - } - #[doc = "LPUART2 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn is_val3(&self) -> bool { - *self == Inp::Val3 - } - #[doc = "LPUART3 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn is_val4(&self) -> bool { - *self == Inp::Val4 - } - #[doc = "LPUART4 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn is_val5(&self) -> bool { - *self == Inp::Val5 - } - #[doc = "LPUART5 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn is_val6(&self) -> bool { - *self == Inp::Val6 - } -} -#[doc = "Field `INP` writer - USB-FS trigger input connections."] -pub type InpW<'a, REG> = crate::FieldWriter<'a, REG, 4, Inp>; -impl<'a, REG> InpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "LPUART0 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn val1(self) -> &'a mut crate::W { - self.variant(Inp::Val1) - } - #[doc = "LPUART1 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn val2(self) -> &'a mut crate::W { - self.variant(Inp::Val2) - } - #[doc = "LPUART2 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn val3(self) -> &'a mut crate::W { - self.variant(Inp::Val3) - } - #[doc = "LPUART3 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn val4(self) -> &'a mut crate::W { - self.variant(Inp::Val4) - } - #[doc = "LPUART4 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn val5(self) -> &'a mut crate::W { - self.variant(Inp::Val5) - } - #[doc = "LPUART5 lpuart_trg_txdata input is selected"] - #[inline(always)] - pub fn val6(self) -> &'a mut crate::W { - self.variant(Inp::Val6) - } -} -impl R { - #[doc = "Bits 0:3 - USB-FS trigger input connections."] - #[inline(always)] - pub fn inp(&self) -> InpR { - InpR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - USB-FS trigger input connections."] - #[inline(always)] - pub fn inp(&mut self) -> InpW { - InpW::new(self, 0) - } -} -#[doc = "USB-FS trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfs_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfs_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UsbfsTrigSpec; -impl crate::RegisterSpec for UsbfsTrigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`usbfs_trig::R`](R) reader structure"] -impl crate::Readable for UsbfsTrigSpec {} -#[doc = "`write(|w| ..)` method takes [`usbfs_trig::W`](W) writer structure"] -impl crate::Writable for UsbfsTrigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets USBFS_TRIG to value 0x07"] -impl crate::Resettable for UsbfsTrigSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/lib.rs b/mcxa276-pac/src/lib.rs deleted file mode 100644 index 18a85f052..000000000 --- a/mcxa276-pac/src/lib.rs +++ /dev/null @@ -1,1555 +0,0 @@ -#![doc = "Peripheral access API for MCXA276 microcontrollers (generated using svd2rust v0.36.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![allow(non_camel_case_types)] -#![allow(non_snake_case)] -#![no_std] -#![allow(elided_lifetimes_in_paths)] -#![allow(warnings)] - - -#![cfg_attr(docsrs, feature(doc_auto_cfg))] -#[doc = r"Number available in the NVIC for configuring priority"] -pub const NVIC_PRIO_BITS: u8 = 3; -#[allow(unused_imports)] -use generic::*; -#[doc = r"Common register and bit access and modify traits"] -pub mod generic; -#[cfg(feature = "rt")] -extern "C" { - fn Reserved16(); - fn CMC(); - fn DMA_CH0(); - fn DMA_CH1(); - fn DMA_CH2(); - fn DMA_CH3(); - fn DMA_CH4(); - fn DMA_CH5(); - fn DMA_CH6(); - fn DMA_CH7(); - fn ERM0_SINGLE_BIT(); - fn ERM0_MULTI_BIT(); - fn FMU0(); - fn GLIKEY0(); - fn MBC0(); - fn SCG0(); - fn SPC0(); - fn TDET(); - fn WUU0(); - fn CAN0(); - fn CAN1(); - fn FLEXIO(); - fn I3C0(); - fn LPI2C0(); - fn LPI2C1(); - fn LPSPI0(); - fn LPSPI1(); - fn LPUART0(); - fn LPUART1(); - fn LPUART2(); - fn LPUART3(); - fn LPUART4(); - fn USB0(); - fn CDOG0(); - fn CTIMER0(); - fn CTIMER1(); - fn CTIMER2(); - fn CTIMER3(); - fn CTIMER4(); - fn FLEXPWM0_RELOAD_ERROR(); - fn FLEXPWM0_FAULT(); - fn FLEXPWM0_SUBMODULE0(); - fn FLEXPWM0_SUBMODULE1(); - fn FLEXPWM0_SUBMODULE2(); - fn FLEXPWM0_SUBMODULE3(); - fn EQDC0_COMPARE(); - fn EQDC0_HOME(); - fn EQDC0_WATCHDOG(); - fn EQDC0_INDEX(); - fn FREQME0(); - fn LPTMR0(); - fn OS_EVENT(); - fn WAKETIMER0(); - fn UTICK0(); - fn WWDT0(); - fn ADC0(); - fn ADC1(); - fn CMP0(); - fn CMP1(); - fn CMP2(); - fn DAC0(); - fn GPIO0(); - fn GPIO1(); - fn GPIO2(); - fn GPIO3(); - fn GPIO4(); - fn LPI2C2(); - fn LPI2C3(); - fn FLEXPWM1_RELOAD_ERROR(); - fn FLEXPWM1_FAULT(); - fn FLEXPWM1_SUBMODULE0(); - fn FLEXPWM1_SUBMODULE1(); - fn FLEXPWM1_SUBMODULE2(); - fn FLEXPWM1_SUBMODULE3(); - fn EQDC1_COMPARE(); - fn EQDC1_HOME(); - fn EQDC1_WATCHDOG(); - fn EQDC1_INDEX(); - fn LPUART5(); - fn MAU(); - fn SMARTDMA(); - fn CDOG1(); - fn PKC(); - fn SGI(); - fn TRNG0(); - fn ADC2(); - fn ADC3(); - fn RTC(); - fn RTC_1HZ(); - fn SLCD(); -} -#[doc(hidden)] -#[repr(C)] -pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, -} -#[cfg(feature = "rt")] -#[doc(hidden)] -#[link_section = ".vector_table.interrupts"] -#[no_mangle] -pub static __INTERRUPTS: [Vector; 122] = [ - Vector { - _handler: Reserved16, - }, - Vector { _handler: CMC }, - Vector { _handler: DMA_CH0 }, - Vector { _handler: DMA_CH1 }, - Vector { _handler: DMA_CH2 }, - Vector { _handler: DMA_CH3 }, - Vector { _handler: DMA_CH4 }, - Vector { _handler: DMA_CH5 }, - Vector { _handler: DMA_CH6 }, - Vector { _handler: DMA_CH7 }, - Vector { - _handler: ERM0_SINGLE_BIT, - }, - Vector { - _handler: ERM0_MULTI_BIT, - }, - Vector { _handler: FMU0 }, - Vector { _handler: GLIKEY0 }, - Vector { _handler: MBC0 }, - Vector { _handler: SCG0 }, - Vector { _handler: SPC0 }, - Vector { _handler: TDET }, - Vector { _handler: WUU0 }, - Vector { _handler: CAN0 }, - Vector { _handler: CAN1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FLEXIO }, - Vector { _handler: I3C0 }, - Vector { _reserved: 0 }, - Vector { _handler: LPI2C0 }, - Vector { _handler: LPI2C1 }, - Vector { _handler: LPSPI0 }, - Vector { _handler: LPSPI1 }, - Vector { _reserved: 0 }, - Vector { _handler: LPUART0 }, - Vector { _handler: LPUART1 }, - Vector { _handler: LPUART2 }, - Vector { _handler: LPUART3 }, - Vector { _handler: LPUART4 }, - Vector { _handler: USB0 }, - Vector { _reserved: 0 }, - Vector { _handler: CDOG0 }, - Vector { _handler: CTIMER0 }, - Vector { _handler: CTIMER1 }, - Vector { _handler: CTIMER2 }, - Vector { _handler: CTIMER3 }, - Vector { _handler: CTIMER4 }, - Vector { - _handler: FLEXPWM0_RELOAD_ERROR, - }, - Vector { - _handler: FLEXPWM0_FAULT, - }, - Vector { - _handler: FLEXPWM0_SUBMODULE0, - }, - Vector { - _handler: FLEXPWM0_SUBMODULE1, - }, - Vector { - _handler: FLEXPWM0_SUBMODULE2, - }, - Vector { - _handler: FLEXPWM0_SUBMODULE3, - }, - Vector { - _handler: EQDC0_COMPARE, - }, - Vector { - _handler: EQDC0_HOME, - }, - Vector { - _handler: EQDC0_WATCHDOG, - }, - Vector { - _handler: EQDC0_INDEX, - }, - Vector { _handler: FREQME0 }, - Vector { _handler: LPTMR0 }, - Vector { _reserved: 0 }, - Vector { _handler: OS_EVENT }, - Vector { - _handler: WAKETIMER0, - }, - Vector { _handler: UTICK0 }, - Vector { _handler: WWDT0 }, - Vector { _reserved: 0 }, - Vector { _handler: ADC0 }, - Vector { _handler: ADC1 }, - Vector { _handler: CMP0 }, - Vector { _handler: CMP1 }, - Vector { _handler: CMP2 }, - Vector { _handler: DAC0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: GPIO0 }, - Vector { _handler: GPIO1 }, - Vector { _handler: GPIO2 }, - Vector { _handler: GPIO3 }, - Vector { _handler: GPIO4 }, - Vector { _reserved: 0 }, - Vector { _handler: LPI2C2 }, - Vector { _handler: LPI2C3 }, - Vector { - _handler: FLEXPWM1_RELOAD_ERROR, - }, - Vector { - _handler: FLEXPWM1_FAULT, - }, - Vector { - _handler: FLEXPWM1_SUBMODULE0, - }, - Vector { - _handler: FLEXPWM1_SUBMODULE1, - }, - Vector { - _handler: FLEXPWM1_SUBMODULE2, - }, - Vector { - _handler: FLEXPWM1_SUBMODULE3, - }, - Vector { - _handler: EQDC1_COMPARE, - }, - Vector { - _handler: EQDC1_HOME, - }, - Vector { - _handler: EQDC1_WATCHDOG, - }, - Vector { - _handler: EQDC1_INDEX, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: LPUART5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: MAU }, - Vector { _handler: SMARTDMA }, - Vector { _handler: CDOG1 }, - Vector { _handler: PKC }, - Vector { _handler: SGI }, - Vector { _reserved: 0 }, - Vector { _handler: TRNG0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: ADC2 }, - Vector { _handler: ADC3 }, - Vector { _reserved: 0 }, - Vector { _handler: RTC }, - Vector { _handler: RTC_1HZ }, - Vector { _handler: SLCD }, -]; -#[doc = r"Enumeration of all the interrupts."] -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Interrupt { - #[doc = "0 - Reserved16"] - Reserved16 = 0, - #[doc = "1 - CMC"] - CMC = 1, - #[doc = "2 - DMA_CH0"] - DMA_CH0 = 2, - #[doc = "3 - DMA_CH1"] - DMA_CH1 = 3, - #[doc = "4 - DMA_CH2"] - DMA_CH2 = 4, - #[doc = "5 - DMA_CH3"] - DMA_CH3 = 5, - #[doc = "6 - DMA_CH4"] - DMA_CH4 = 6, - #[doc = "7 - DMA_CH5"] - DMA_CH5 = 7, - #[doc = "8 - DMA_CH6"] - DMA_CH6 = 8, - #[doc = "9 - DMA_CH7"] - DMA_CH7 = 9, - #[doc = "10 - ERM0_SINGLE_BIT"] - ERM0_SINGLE_BIT = 10, - #[doc = "11 - ERM0_MULTI_BIT"] - ERM0_MULTI_BIT = 11, - #[doc = "12 - FMU0"] - FMU0 = 12, - #[doc = "13 - GLIKEY0"] - GLIKEY0 = 13, - #[doc = "14 - MBC0"] - MBC0 = 14, - #[doc = "15 - SCG0"] - SCG0 = 15, - #[doc = "16 - SPC0"] - SPC0 = 16, - #[doc = "17 - TDET"] - TDET = 17, - #[doc = "18 - WUU0"] - WUU0 = 18, - #[doc = "19 - CAN0"] - CAN0 = 19, - #[doc = "20 - CAN1"] - CAN1 = 20, - #[doc = "23 - FLEXIO"] - FLEXIO = 23, - #[doc = "24 - I3C0"] - I3C0 = 24, - #[doc = "26 - LPI2C0"] - LPI2C0 = 26, - #[doc = "27 - LPI2C1"] - LPI2C1 = 27, - #[doc = "28 - LPSPI0"] - LPSPI0 = 28, - #[doc = "29 - LPSPI1"] - LPSPI1 = 29, - #[doc = "31 - LPUART0"] - LPUART0 = 31, - #[doc = "32 - LPUART1"] - LPUART1 = 32, - #[doc = "33 - LPUART2"] - LPUART2 = 33, - #[doc = "34 - LPUART3"] - LPUART3 = 34, - #[doc = "35 - LPUART4"] - LPUART4 = 35, - #[doc = "36 - USB0"] - USB0 = 36, - #[doc = "38 - CDOG0"] - CDOG0 = 38, - #[doc = "39 - CTIMER0"] - CTIMER0 = 39, - #[doc = "40 - CTIMER1"] - CTIMER1 = 40, - #[doc = "41 - CTIMER2"] - CTIMER2 = 41, - #[doc = "42 - CTIMER3"] - CTIMER3 = 42, - #[doc = "43 - CTIMER4"] - CTIMER4 = 43, - #[doc = "44 - FLEXPWM0_RELOAD_ERROR"] - FLEXPWM0_RELOAD_ERROR = 44, - #[doc = "45 - FLEXPWM0_FAULT"] - FLEXPWM0_FAULT = 45, - #[doc = "46 - FLEXPWM0_SUBMODULE0"] - FLEXPWM0_SUBMODULE0 = 46, - #[doc = "47 - FLEXPWM0_SUBMODULE1"] - FLEXPWM0_SUBMODULE1 = 47, - #[doc = "48 - FLEXPWM0_SUBMODULE2"] - FLEXPWM0_SUBMODULE2 = 48, - #[doc = "49 - FLEXPWM0_SUBMODULE3"] - FLEXPWM0_SUBMODULE3 = 49, - #[doc = "50 - EQDC0_COMPARE"] - EQDC0_COMPARE = 50, - #[doc = "51 - EQDC0_HOME"] - EQDC0_HOME = 51, - #[doc = "52 - EQDC0_WATCHDOG"] - EQDC0_WATCHDOG = 52, - #[doc = "53 - EQDC0_INDEX"] - EQDC0_INDEX = 53, - #[doc = "54 - FREQME0"] - FREQME0 = 54, - #[doc = "55 - LPTMR0"] - LPTMR0 = 55, - #[doc = "57 - OS_EVENT"] - OS_EVENT = 57, - #[doc = "58 - WAKETIMER0"] - WAKETIMER0 = 58, - #[doc = "59 - UTICK0"] - UTICK0 = 59, - #[doc = "60 - WWDT0"] - WWDT0 = 60, - #[doc = "62 - ADC0"] - ADC0 = 62, - #[doc = "63 - ADC1"] - ADC1 = 63, - #[doc = "64 - CMP0"] - CMP0 = 64, - #[doc = "65 - CMP1"] - CMP1 = 65, - #[doc = "66 - CMP2"] - CMP2 = 66, - #[doc = "67 - DAC0"] - DAC0 = 67, - #[doc = "71 - GPIO0"] - GPIO0 = 71, - #[doc = "72 - GPIO1"] - GPIO1 = 72, - #[doc = "73 - GPIO2"] - GPIO2 = 73, - #[doc = "74 - GPIO3"] - GPIO3 = 74, - #[doc = "75 - GPIO4"] - GPIO4 = 75, - #[doc = "77 - LPI2C2"] - LPI2C2 = 77, - #[doc = "78 - LPI2C3"] - LPI2C3 = 78, - #[doc = "79 - FLEXPWM1_RELOAD_ERROR"] - FLEXPWM1_RELOAD_ERROR = 79, - #[doc = "80 - FLEXPWM1_FAULT"] - FLEXPWM1_FAULT = 80, - #[doc = "81 - FLEXPWM1_SUBMODULE0"] - FLEXPWM1_SUBMODULE0 = 81, - #[doc = "82 - FLEXPWM1_SUBMODULE1"] - FLEXPWM1_SUBMODULE1 = 82, - #[doc = "83 - FLEXPWM1_SUBMODULE2"] - FLEXPWM1_SUBMODULE2 = 83, - #[doc = "84 - FLEXPWM1_SUBMODULE3"] - FLEXPWM1_SUBMODULE3 = 84, - #[doc = "85 - EQDC1_COMPARE"] - EQDC1_COMPARE = 85, - #[doc = "86 - EQDC1_HOME"] - EQDC1_HOME = 86, - #[doc = "87 - EQDC1_WATCHDOG"] - EQDC1_WATCHDOG = 87, - #[doc = "88 - EQDC1_INDEX"] - EQDC1_INDEX = 88, - #[doc = "95 - LPUART5"] - LPUART5 = 95, - #[doc = "107 - MAU"] - MAU = 107, - #[doc = "108 - SMARTDMA"] - SMARTDMA = 108, - #[doc = "109 - CDOG1"] - CDOG1 = 109, - #[doc = "110 - PKC"] - PKC = 110, - #[doc = "111 - SGI"] - SGI = 111, - #[doc = "113 - TRNG0"] - TRNG0 = 113, - #[doc = "116 - ADC2"] - ADC2 = 116, - #[doc = "117 - ADC3"] - ADC3 = 117, - #[doc = "119 - RTC"] - RTC = 119, - #[doc = "120 - RTC_1HZ"] - RTC_1HZ = 120, - #[doc = "121 - SLCD"] - SLCD = 121, -} -unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } -} -#[doc = "INPUTMUX"] -pub type Inputmux0 = crate::Periph; -impl core::fmt::Debug for Inputmux0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Inputmux0").finish() - } -} -#[doc = "INPUTMUX"] -pub mod inputmux0; -#[doc = "Improved Inter-Integrated Circuit"] -pub type I3c0 = crate::Periph; -impl core::fmt::Debug for I3c0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I3c0").finish() - } -} -#[doc = "Improved Inter-Integrated Circuit"] -pub mod i3c0; -#[doc = "Standard Counter or Timer"] -pub type Ctimer0 = crate::Periph; -impl core::fmt::Debug for Ctimer0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ctimer0").finish() - } -} -#[doc = "Standard Counter or Timer"] -pub mod ctimer0; -#[doc = "Standard Counter or Timer"] -pub type Ctimer1 = crate::Periph; -impl core::fmt::Debug for Ctimer1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ctimer1").finish() - } -} -#[doc = "Standard Counter or Timer"] -pub use self::ctimer0 as ctimer1; -#[doc = "Standard Counter or Timer"] -pub type Ctimer2 = crate::Periph; -impl core::fmt::Debug for Ctimer2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ctimer2").finish() - } -} -#[doc = "Standard Counter or Timer"] -pub use self::ctimer0 as ctimer2; -#[doc = "Standard Counter or Timer"] -pub type Ctimer3 = crate::Periph; -impl core::fmt::Debug for Ctimer3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ctimer3").finish() - } -} -#[doc = "Standard Counter or Timer"] -pub use self::ctimer0 as ctimer3; -#[doc = "Standard Counter or Timer"] -pub type Ctimer4 = crate::Periph; -impl core::fmt::Debug for Ctimer4 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ctimer4").finish() - } -} -#[doc = "Standard Counter or Timer"] -pub use self::ctimer0 as ctimer4; -#[doc = "FREQME"] -pub type Freqme0 = crate::Periph; -impl core::fmt::Debug for Freqme0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Freqme0").finish() - } -} -#[doc = "FREQME"] -pub mod freqme0; -#[doc = "UTICK"] -pub type Utick0 = crate::Periph; -impl core::fmt::Debug for Utick0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Utick0").finish() - } -} -#[doc = "UTICK"] -pub mod utick0; -#[doc = "WWDT"] -pub type Wwdt0 = crate::Periph; -impl core::fmt::Debug for Wwdt0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Wwdt0").finish() - } -} -#[doc = "WWDT"] -pub mod wwdt0; -#[doc = "Smart DMA Controller"] -pub type Smartdma0 = crate::Periph; -impl core::fmt::Debug for Smartdma0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Smartdma0").finish() - } -} -#[doc = "Smart DMA Controller"] -pub mod smartdma0; -#[doc = "DMA MP"] -pub type Dma0 = crate::Periph; -impl core::fmt::Debug for Dma0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Dma0").finish() - } -} -#[doc = "DMA MP"] -pub mod dma0; -#[doc = "DMA TCD"] -pub type Edma0Tcd0 = crate::Periph; -impl core::fmt::Debug for Edma0Tcd0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Edma0Tcd0").finish() - } -} -#[doc = "DMA TCD"] -pub mod edma_0_tcd0; -#[doc = "AOI"] -pub type Aoi0 = crate::Periph; -impl core::fmt::Debug for Aoi0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Aoi0").finish() - } -} -#[doc = "AOI"] -pub mod aoi0; -#[doc = "AOI"] -pub type Aoi1 = crate::Periph; -impl core::fmt::Debug for Aoi1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Aoi1").finish() - } -} -#[doc = "AOI"] -pub use self::aoi0 as aoi1; -#[doc = "CRC"] -pub type Crc0 = crate::Periph; -impl core::fmt::Debug for Crc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Crc0").finish() - } -} -#[doc = "CRC"] -pub mod crc0; -#[doc = "CMC"] -pub type Cmc = crate::Periph; -impl core::fmt::Debug for Cmc { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cmc").finish() - } -} -#[doc = "CMC"] -pub mod cmc; -#[doc = "Error Injection Module"] -pub type Eim0 = crate::Periph; -impl core::fmt::Debug for Eim0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Eim0").finish() - } -} -#[doc = "Error Injection Module"] -pub mod eim0; -#[doc = "Error Reporting Module"] -pub type Erm0 = crate::Periph; -impl core::fmt::Debug for Erm0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Erm0").finish() - } -} -#[doc = "Error Reporting Module"] -pub mod erm0; -#[doc = "TRDC"] -pub type Mbc0 = crate::Periph; -impl core::fmt::Debug for Mbc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mbc0").finish() - } -} -#[doc = "TRDC"] -pub mod mbc0; -#[doc = "System Clock Generator"] -pub type Scg0 = crate::Periph; -impl core::fmt::Debug for Scg0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Scg0").finish() - } -} -#[doc = "System Clock Generator"] -pub mod scg0; -#[doc = "SPC"] -pub type Spc0 = crate::Periph; -impl core::fmt::Debug for Spc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spc0").finish() - } -} -#[doc = "SPC"] -pub mod spc0; -#[doc = "MRCC"] -pub type Mrcc0 = crate::Periph; -impl core::fmt::Debug for Mrcc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mrcc0").finish() - } -} -#[doc = "MRCC"] -pub mod mrcc0; -#[doc = "SYSCON"] -pub type Syscon = crate::Periph; -impl core::fmt::Debug for Syscon { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Syscon").finish() - } -} -#[doc = "SYSCON"] -pub mod syscon; -#[doc = "GLIKEY"] -pub type Glikey0 = crate::Periph; -impl core::fmt::Debug for Glikey0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Glikey0").finish() - } -} -#[doc = "GLIKEY"] -pub mod glikey0; -#[doc = "Low-Leakage Wakeup Unit"] -pub type Wuu0 = crate::Periph; -impl core::fmt::Debug for Wuu0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Wuu0").finish() - } -} -#[doc = "Low-Leakage Wakeup Unit"] -pub mod wuu0; -#[doc = "VBAT"] -pub type Vbat0 = crate::Periph; -impl core::fmt::Debug for Vbat0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Vbat0").finish() - } -} -#[doc = "VBAT"] -pub mod vbat0; -#[doc = "NPX"] -pub type Fmc0 = crate::Periph; -impl core::fmt::Debug for Fmc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Fmc0").finish() - } -} -#[doc = "NPX"] -pub mod fmc0; -#[doc = "Flash"] -pub type Fmu0 = crate::Periph; -impl core::fmt::Debug for Fmu0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Fmu0").finish() - } -} -#[doc = "Flash"] -pub mod fmu0; -#[doc = "Flexible I/O"] -pub type Flexio0 = crate::Periph; -impl core::fmt::Debug for Flexio0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flexio0").finish() - } -} -#[doc = "Flexible I/O"] -pub mod flexio0; -#[doc = "Low-Power Inter-Integrated Circuit"] -pub type Lpi2c0 = crate::Periph; -impl core::fmt::Debug for Lpi2c0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2c0").finish() - } -} -#[doc = "Low-Power Inter-Integrated Circuit"] -pub mod lpi2c0; -#[doc = "Low-Power Inter-Integrated Circuit"] -pub type Lpi2c1 = crate::Periph; -impl core::fmt::Debug for Lpi2c1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2c1").finish() - } -} -#[doc = "Low-Power Inter-Integrated Circuit"] -pub use self::lpi2c0 as lpi2c1; -#[doc = "Low-Power Inter-Integrated Circuit"] -pub type Lpi2c2 = crate::Periph; -impl core::fmt::Debug for Lpi2c2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2c2").finish() - } -} -#[doc = "Low-Power Inter-Integrated Circuit"] -pub use self::lpi2c0 as lpi2c2; -#[doc = "Low-Power Inter-Integrated Circuit"] -pub type Lpi2c3 = crate::Periph; -impl core::fmt::Debug for Lpi2c3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2c3").finish() - } -} -#[doc = "Low-Power Inter-Integrated Circuit"] -pub use self::lpi2c0 as lpi2c3; -#[doc = "Low-Power Serial Peripheral Interface"] -pub type Lpspi0 = crate::Periph; -impl core::fmt::Debug for Lpspi0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpspi0").finish() - } -} -#[doc = "Low-Power Serial Peripheral Interface"] -pub mod lpspi0; -#[doc = "Low-Power Serial Peripheral Interface"] -pub type Lpspi1 = crate::Periph; -impl core::fmt::Debug for Lpspi1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpspi1").finish() - } -} -#[doc = "Low-Power Serial Peripheral Interface"] -pub use self::lpspi0 as lpspi1; -#[doc = "LPUART"] -pub type Lpuart0 = crate::Periph; -impl core::fmt::Debug for Lpuart0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpuart0").finish() - } -} -#[doc = "LPUART"] -pub mod lpuart0; -#[doc = "LPUART"] -pub type Lpuart1 = crate::Periph; -impl core::fmt::Debug for Lpuart1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpuart1").finish() - } -} -#[doc = "LPUART"] -pub use self::lpuart0 as lpuart1; -#[doc = "LPUART"] -pub type Lpuart2 = crate::Periph; -impl core::fmt::Debug for Lpuart2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpuart2").finish() - } -} -#[doc = "LPUART"] -pub use self::lpuart0 as lpuart2; -#[doc = "LPUART"] -pub type Lpuart3 = crate::Periph; -impl core::fmt::Debug for Lpuart3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpuart3").finish() - } -} -#[doc = "LPUART"] -pub use self::lpuart0 as lpuart3; -#[doc = "LPUART"] -pub type Lpuart4 = crate::Periph; -impl core::fmt::Debug for Lpuart4 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpuart4").finish() - } -} -#[doc = "LPUART"] -pub use self::lpuart0 as lpuart4; -#[doc = "LPUART"] -pub type Lpuart5 = crate::Periph; -impl core::fmt::Debug for Lpuart5 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpuart5").finish() - } -} -#[doc = "LPUART"] -pub use self::lpuart0 as lpuart5; -#[doc = "USBFS"] -pub type Usb0 = crate::Periph; -impl core::fmt::Debug for Usb0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Usb0").finish() - } -} -#[doc = "USBFS"] -pub mod usb0; -#[doc = "Quadrature_Decoder"] -pub type Eqdc0 = crate::Periph; -impl core::fmt::Debug for Eqdc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Eqdc0").finish() - } -} -#[doc = "Quadrature_Decoder"] -pub mod eqdc0; -#[doc = "Quadrature_Decoder"] -pub type Eqdc1 = crate::Periph; -impl core::fmt::Debug for Eqdc1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Eqdc1").finish() - } -} -#[doc = "Quadrature_Decoder"] -pub use self::eqdc0 as eqdc1; -#[doc = "PWM"] -pub type Flexpwm0 = crate::Periph; -impl core::fmt::Debug for Flexpwm0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flexpwm0").finish() - } -} -#[doc = "PWM"] -pub mod flexpwm0; -#[doc = "PWM"] -pub type Flexpwm1 = crate::Periph; -impl core::fmt::Debug for Flexpwm1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flexpwm1").finish() - } -} -#[doc = "PWM"] -pub use self::flexpwm0 as flexpwm1; -#[doc = "LPTMR"] -pub type Lptmr0 = crate::Periph; -impl core::fmt::Debug for Lptmr0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lptmr0").finish() - } -} -#[doc = "LPTMR"] -pub mod lptmr0; -#[doc = "OSTIMER"] -pub type Ostimer0 = crate::Periph; -impl core::fmt::Debug for Ostimer0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ostimer0").finish() - } -} -#[doc = "OSTIMER"] -pub mod ostimer0; -#[doc = "WAKE_TIMER"] -pub type Waketimer0 = crate::Periph; -impl core::fmt::Debug for Waketimer0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Waketimer0").finish() - } -} -#[doc = "WAKE_TIMER"] -pub mod waketimer0; -#[doc = "ADC"] -pub type Adc0 = crate::Periph; -impl core::fmt::Debug for Adc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Adc0").finish() - } -} -#[doc = "ADC"] -pub mod adc0; -#[doc = "ADC"] -pub type Adc1 = crate::Periph; -impl core::fmt::Debug for Adc1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Adc1").finish() - } -} -#[doc = "ADC"] -pub use self::adc0 as adc1; -#[doc = "ADC"] -pub type Adc2 = crate::Periph; -impl core::fmt::Debug for Adc2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Adc2").finish() - } -} -#[doc = "ADC"] -pub use self::adc0 as adc2; -#[doc = "ADC"] -pub type Adc3 = crate::Periph; -impl core::fmt::Debug for Adc3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Adc3").finish() - } -} -#[doc = "ADC"] -pub use self::adc0 as adc3; -#[doc = "LPCMP"] -pub type Cmp0 = crate::Periph; -impl core::fmt::Debug for Cmp0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cmp0").finish() - } -} -#[doc = "LPCMP"] -pub mod cmp0; -#[doc = "LPCMP"] -pub type Cmp1 = crate::Periph; -impl core::fmt::Debug for Cmp1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cmp1").finish() - } -} -#[doc = "LPCMP"] -pub use self::cmp0 as cmp1; -#[doc = "LPCMP"] -pub type Cmp2 = crate::Periph; -impl core::fmt::Debug for Cmp2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cmp2").finish() - } -} -#[doc = "LPCMP"] -pub use self::cmp0 as cmp2; -#[doc = "12-bit DAC"] -pub type Dac0 = crate::Periph; -impl core::fmt::Debug for Dac0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Dac0").finish() - } -} -#[doc = "12-bit DAC"] -pub mod dac0; -#[doc = "OPAMP"] -pub type Opamp0 = crate::Periph; -impl core::fmt::Debug for Opamp0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Opamp0").finish() - } -} -#[doc = "OPAMP"] -pub mod opamp0; -#[doc = "OPAMP"] -pub type Opamp1 = crate::Periph; -impl core::fmt::Debug for Opamp1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Opamp1").finish() - } -} -#[doc = "OPAMP"] -pub use self::opamp0 as opamp1; -#[doc = "OPAMP"] -pub type Opamp2 = crate::Periph; -impl core::fmt::Debug for Opamp2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Opamp2").finish() - } -} -#[doc = "OPAMP"] -pub use self::opamp0 as opamp2; -#[doc = "OPAMP"] -pub type Opamp3 = crate::Periph; -impl core::fmt::Debug for Opamp3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Opamp3").finish() - } -} -#[doc = "OPAMP"] -pub use self::opamp0 as opamp3; -#[doc = "PORT"] -pub type Port0 = crate::Periph; -impl core::fmt::Debug for Port0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Port0").finish() - } -} -#[doc = "PORT"] -pub mod port0; -#[doc = "PORT"] -pub type Port1 = crate::Periph; -impl core::fmt::Debug for Port1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Port1").finish() - } -} -#[doc = "PORT"] -pub mod port1; -#[doc = "PORT"] -pub type Port2 = crate::Periph; -impl core::fmt::Debug for Port2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Port2").finish() - } -} -#[doc = "PORT"] -pub mod port2; -#[doc = "PORT"] -pub type Port3 = crate::Periph; -impl core::fmt::Debug for Port3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Port3").finish() - } -} -#[doc = "PORT"] -pub mod port3; -#[doc = "PORT"] -pub type Port4 = crate::Periph; -impl core::fmt::Debug for Port4 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Port4").finish() - } -} -#[doc = "PORT"] -pub mod port4; -#[doc = "SLCD"] -pub type Slcd0 = crate::Periph; -impl core::fmt::Debug for Slcd0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Slcd0").finish() - } -} -#[doc = "SLCD"] -pub mod slcd0; -#[doc = "CAN"] -pub type Can0 = crate::Periph; -impl core::fmt::Debug for Can0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Can0").finish() - } -} -#[doc = "CAN"] -pub mod can0; -#[doc = "CAN"] -pub type Can1 = crate::Periph; -impl core::fmt::Debug for Can1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Can1").finish() - } -} -#[doc = "CAN"] -pub use self::can0 as can1; -#[doc = "TDET"] -pub type Tdet0 = crate::Periph; -impl core::fmt::Debug for Tdet0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Tdet0").finish() - } -} -#[doc = "TDET"] -pub mod tdet0; -#[doc = "no description available"] -pub type Pkc0 = crate::Periph; -impl core::fmt::Debug for Pkc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Pkc0").finish() - } -} -#[doc = "no description available"] -pub mod pkc0; -#[doc = "no description available"] -pub type Sgi0 = crate::Periph; -impl core::fmt::Debug for Sgi0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sgi0").finish() - } -} -#[doc = "no description available"] -pub mod sgi0; -#[doc = "pd_main.trng0"] -pub type Trng0 = crate::Periph; -impl core::fmt::Debug for Trng0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Trng0").finish() - } -} -#[doc = "pd_main.trng0"] -pub mod trng0; -#[doc = "no description available"] -pub type Udf0 = crate::Periph; -impl core::fmt::Debug for Udf0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Udf0").finish() - } -} -#[doc = "no description available"] -pub mod udf0; -#[doc = "RTC"] -pub type Rtc0 = crate::Periph; -impl core::fmt::Debug for Rtc0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Rtc0").finish() - } -} -#[doc = "RTC"] -pub mod rtc0; -#[doc = "CDOG"] -pub type Cdog0 = crate::Periph; -impl core::fmt::Debug for Cdog0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cdog0").finish() - } -} -#[doc = "CDOG"] -pub mod cdog0; -#[doc = "CDOG"] -pub type Cdog1 = crate::Periph; -impl core::fmt::Debug for Cdog1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cdog1").finish() - } -} -#[doc = "CDOG"] -pub use self::cdog0 as cdog1; -#[doc = "DBGMB"] -pub type Dbgmailbox = crate::Periph; -impl core::fmt::Debug for Dbgmailbox { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Dbgmailbox").finish() - } -} -#[doc = "DBGMB"] -pub mod dbgmailbox; -#[doc = "GPIO"] -pub type Gpio0 = crate::Periph; -impl core::fmt::Debug for Gpio0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Gpio0").finish() - } -} -#[doc = "GPIO"] -pub mod gpio0; -#[doc = "GPIO"] -pub type Gpio1 = crate::Periph; -impl core::fmt::Debug for Gpio1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Gpio1").finish() - } -} -#[doc = "GPIO"] -pub use self::gpio0 as gpio1; -#[doc = "GPIO"] -pub type Gpio2 = crate::Periph; -impl core::fmt::Debug for Gpio2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Gpio2").finish() - } -} -#[doc = "GPIO"] -pub use self::gpio0 as gpio2; -#[doc = "GPIO"] -pub type Gpio3 = crate::Periph; -impl core::fmt::Debug for Gpio3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Gpio3").finish() - } -} -#[doc = "GPIO"] -pub use self::gpio0 as gpio3; -#[doc = "GPIO"] -pub type Gpio4 = crate::Periph; -impl core::fmt::Debug for Gpio4 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Gpio4").finish() - } -} -#[doc = "GPIO"] -pub use self::gpio0 as gpio4; -#[doc = "MAUWRAP"] -pub type Mau0 = crate::Periph; -impl core::fmt::Debug for Mau0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mau0").finish() - } -} -#[doc = "MAUWRAP"] -pub mod mau0; -#[doc = "System Control not in System Control Block"] -pub type ScnScb = crate::Periph; -impl core::fmt::Debug for ScnScb { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ScnScb").finish() - } -} -#[doc = "System Control not in System Control Block"] -pub mod scn_scb; -#[doc = "Security Attribution Unit"] -pub type Sau = crate::Periph; -impl core::fmt::Debug for Sau { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sau").finish() - } -} -#[doc = "Security Attribution Unit"] -pub mod sau; -#[no_mangle] -static mut DEVICE_PERIPHERALS: bool = false; -#[doc = r" All the peripherals."] -#[allow(non_snake_case)] -pub struct Peripherals { - #[doc = "INPUTMUX0"] - pub inputmux0: Inputmux0, - #[doc = "I3C0"] - pub i3c0: I3c0, - #[doc = "CTIMER0"] - pub ctimer0: Ctimer0, - #[doc = "CTIMER1"] - pub ctimer1: Ctimer1, - #[doc = "CTIMER2"] - pub ctimer2: Ctimer2, - #[doc = "CTIMER3"] - pub ctimer3: Ctimer3, - #[doc = "CTIMER4"] - pub ctimer4: Ctimer4, - #[doc = "FREQME0"] - pub freqme0: Freqme0, - #[doc = "UTICK0"] - pub utick0: Utick0, - #[doc = "WWDT0"] - pub wwdt0: Wwdt0, - #[doc = "SMARTDMA0"] - pub smartdma0: Smartdma0, - #[doc = "DMA0"] - pub dma0: Dma0, - #[doc = "EDMA_0_TCD0"] - pub edma_0_tcd0: Edma0Tcd0, - #[doc = "AOI0"] - pub aoi0: Aoi0, - #[doc = "AOI1"] - pub aoi1: Aoi1, - #[doc = "CRC0"] - pub crc0: Crc0, - #[doc = "CMC"] - pub cmc: Cmc, - #[doc = "EIM0"] - pub eim0: Eim0, - #[doc = "ERM0"] - pub erm0: Erm0, - #[doc = "MBC0"] - pub mbc0: Mbc0, - #[doc = "SCG0"] - pub scg0: Scg0, - #[doc = "SPC0"] - pub spc0: Spc0, - #[doc = "MRCC0"] - pub mrcc0: Mrcc0, - #[doc = "SYSCON"] - pub syscon: Syscon, - #[doc = "GLIKEY0"] - pub glikey0: Glikey0, - #[doc = "WUU0"] - pub wuu0: Wuu0, - #[doc = "VBAT0"] - pub vbat0: Vbat0, - #[doc = "FMC0"] - pub fmc0: Fmc0, - #[doc = "FMU0"] - pub fmu0: Fmu0, - #[doc = "FLEXIO0"] - pub flexio0: Flexio0, - #[doc = "LPI2C0"] - pub lpi2c0: Lpi2c0, - #[doc = "LPI2C1"] - pub lpi2c1: Lpi2c1, - #[doc = "LPI2C2"] - pub lpi2c2: Lpi2c2, - #[doc = "LPI2C3"] - pub lpi2c3: Lpi2c3, - #[doc = "LPSPI0"] - pub lpspi0: Lpspi0, - #[doc = "LPSPI1"] - pub lpspi1: Lpspi1, - #[doc = "LPUART0"] - pub lpuart0: Lpuart0, - #[doc = "LPUART1"] - pub lpuart1: Lpuart1, - #[doc = "LPUART2"] - pub lpuart2: Lpuart2, - #[doc = "LPUART3"] - pub lpuart3: Lpuart3, - #[doc = "LPUART4"] - pub lpuart4: Lpuart4, - #[doc = "LPUART5"] - pub lpuart5: Lpuart5, - #[doc = "USB0"] - pub usb0: Usb0, - #[doc = "EQDC0"] - pub eqdc0: Eqdc0, - #[doc = "EQDC1"] - pub eqdc1: Eqdc1, - #[doc = "FLEXPWM0"] - pub flexpwm0: Flexpwm0, - #[doc = "FLEXPWM1"] - pub flexpwm1: Flexpwm1, - #[doc = "LPTMR0"] - pub lptmr0: Lptmr0, - #[doc = "OSTIMER0"] - pub ostimer0: Ostimer0, - #[doc = "WAKE_TIMER"] - pub waketimer0: Waketimer0, - #[doc = "ADC0"] - pub adc0: Adc0, - #[doc = "ADC1"] - pub adc1: Adc1, - #[doc = "ADC2"] - pub adc2: Adc2, - #[doc = "ADC3"] - pub adc3: Adc3, - #[doc = "CMP0"] - pub cmp0: Cmp0, - #[doc = "CMP1"] - pub cmp1: Cmp1, - #[doc = "CMP2"] - pub cmp2: Cmp2, - #[doc = "DAC0"] - pub dac0: Dac0, - #[doc = "OPAMP0"] - pub opamp0: Opamp0, - #[doc = "OPAMP1"] - pub opamp1: Opamp1, - #[doc = "OPAMP2"] - pub opamp2: Opamp2, - #[doc = "OPAMP3"] - pub opamp3: Opamp3, - #[doc = "PORT0"] - pub port0: Port0, - #[doc = "PORT1"] - pub port1: Port1, - #[doc = "PORT2"] - pub port2: Port2, - #[doc = "PORT3"] - pub port3: Port3, - #[doc = "PORT4"] - pub port4: Port4, - #[doc = "SLCD0"] - pub slcd0: Slcd0, - #[doc = "CAN0"] - pub can0: Can0, - #[doc = "CAN1"] - pub can1: Can1, - #[doc = "TDET0"] - pub tdet0: Tdet0, - #[doc = "PKC0"] - pub pkc0: Pkc0, - #[doc = "SGI0"] - pub sgi0: Sgi0, - #[doc = "TRNG0"] - pub trng0: Trng0, - #[doc = "UDF0"] - pub udf0: Udf0, - #[doc = "RTC0"] - pub rtc0: Rtc0, - #[doc = "CDOG0"] - pub cdog0: Cdog0, - #[doc = "CDOG1"] - pub cdog1: Cdog1, - #[doc = "DBGMAILBOX"] - pub dbgmailbox: Dbgmailbox, - #[doc = "GPIO0"] - pub gpio0: Gpio0, - #[doc = "GPIO1"] - pub gpio1: Gpio1, - #[doc = "GPIO2"] - pub gpio2: Gpio2, - #[doc = "GPIO3"] - pub gpio3: Gpio3, - #[doc = "GPIO4"] - pub gpio4: Gpio4, - #[doc = "MAU0"] - pub mau0: Mau0, - #[doc = "SCnSCB"] - pub scn_scb: ScnScb, - #[doc = "SAU"] - pub sau: Sau, -} -impl Peripherals { - #[doc = r" Returns all the peripherals *once*."] - #[cfg(feature = "critical-section")] - #[inline] - pub fn take() -> Option { - critical_section::with(|_| { - if unsafe { DEVICE_PERIPHERALS } { - return None; - } - Some(unsafe { Peripherals::steal() }) - }) - } - #[doc = r" Unchecked version of `Peripherals::take`."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Each of the returned peripherals must be used at most once."] - #[inline] - pub unsafe fn steal() -> Self { - DEVICE_PERIPHERALS = true; - Peripherals { - inputmux0: Inputmux0::steal(), - i3c0: I3c0::steal(), - ctimer0: Ctimer0::steal(), - ctimer1: Ctimer1::steal(), - ctimer2: Ctimer2::steal(), - ctimer3: Ctimer3::steal(), - ctimer4: Ctimer4::steal(), - freqme0: Freqme0::steal(), - utick0: Utick0::steal(), - wwdt0: Wwdt0::steal(), - smartdma0: Smartdma0::steal(), - dma0: Dma0::steal(), - edma_0_tcd0: Edma0Tcd0::steal(), - aoi0: Aoi0::steal(), - aoi1: Aoi1::steal(), - crc0: Crc0::steal(), - cmc: Cmc::steal(), - eim0: Eim0::steal(), - erm0: Erm0::steal(), - mbc0: Mbc0::steal(), - scg0: Scg0::steal(), - spc0: Spc0::steal(), - mrcc0: Mrcc0::steal(), - syscon: Syscon::steal(), - glikey0: Glikey0::steal(), - wuu0: Wuu0::steal(), - vbat0: Vbat0::steal(), - fmc0: Fmc0::steal(), - fmu0: Fmu0::steal(), - flexio0: Flexio0::steal(), - lpi2c0: Lpi2c0::steal(), - lpi2c1: Lpi2c1::steal(), - lpi2c2: Lpi2c2::steal(), - lpi2c3: Lpi2c3::steal(), - lpspi0: Lpspi0::steal(), - lpspi1: Lpspi1::steal(), - lpuart0: Lpuart0::steal(), - lpuart1: Lpuart1::steal(), - lpuart2: Lpuart2::steal(), - lpuart3: Lpuart3::steal(), - lpuart4: Lpuart4::steal(), - lpuart5: Lpuart5::steal(), - usb0: Usb0::steal(), - eqdc0: Eqdc0::steal(), - eqdc1: Eqdc1::steal(), - flexpwm0: Flexpwm0::steal(), - flexpwm1: Flexpwm1::steal(), - lptmr0: Lptmr0::steal(), - ostimer0: Ostimer0::steal(), - waketimer0: Waketimer0::steal(), - adc0: Adc0::steal(), - adc1: Adc1::steal(), - adc2: Adc2::steal(), - adc3: Adc3::steal(), - cmp0: Cmp0::steal(), - cmp1: Cmp1::steal(), - cmp2: Cmp2::steal(), - dac0: Dac0::steal(), - opamp0: Opamp0::steal(), - opamp1: Opamp1::steal(), - opamp2: Opamp2::steal(), - opamp3: Opamp3::steal(), - port0: Port0::steal(), - port1: Port1::steal(), - port2: Port2::steal(), - port3: Port3::steal(), - port4: Port4::steal(), - slcd0: Slcd0::steal(), - can0: Can0::steal(), - can1: Can1::steal(), - tdet0: Tdet0::steal(), - pkc0: Pkc0::steal(), - sgi0: Sgi0::steal(), - trng0: Trng0::steal(), - udf0: Udf0::steal(), - rtc0: Rtc0::steal(), - cdog0: Cdog0::steal(), - cdog1: Cdog1::steal(), - dbgmailbox: Dbgmailbox::steal(), - gpio0: Gpio0::steal(), - gpio1: Gpio1::steal(), - gpio2: Gpio2::steal(), - gpio3: Gpio3::steal(), - gpio4: Gpio4::steal(), - mau0: Mau0::steal(), - scn_scb: ScnScb::steal(), - sau: Sau::steal(), - } - } -} diff --git a/mcxa276-pac/src/lpi2c0.rs b/mcxa276-pac/src/lpi2c0.rs deleted file mode 100644 index 1cbc714e9..000000000 --- a/mcxa276-pac/src/lpi2c0.rs +++ /dev/null @@ -1,360 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - _reserved2: [u8; 0x08], - mcr: Mcr, - msr: Msr, - mier: Mier, - mder: Mder, - mcfgr0: Mcfgr0, - mcfgr1: Mcfgr1, - mcfgr2: Mcfgr2, - mcfgr3: Mcfgr3, - _reserved10: [u8; 0x10], - mdmr: Mdmr, - _reserved11: [u8; 0x04], - mccr0: Mccr0, - _reserved12: [u8; 0x04], - mccr1: Mccr1, - _reserved13: [u8; 0x04], - mfcr: Mfcr, - mfsr: Mfsr, - mtdr: Mtdr, - _reserved16: [u8; 0x0c], - mrdr: Mrdr, - _reserved17: [u8; 0x04], - mrdror: Mrdror, - _reserved18: [u8; 0x94], - scr: Scr, - ssr: Ssr, - sier: Sier, - sder: Sder, - scfgr0: Scfgr0, - scfgr1: Scfgr1, - scfgr2: Scfgr2, - _reserved25: [u8; 0x14], - samr: Samr, - _reserved26: [u8; 0x0c], - sasr: Sasr, - star: Star, - _reserved28: [u8; 0x08], - stdr: Stdr, - _reserved29: [u8; 0x0c], - srdr: Srdr, - _reserved30: [u8; 0x04], - srdror: Srdror, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x10 - Controller Control"] - #[inline(always)] - pub const fn mcr(&self) -> &Mcr { - &self.mcr - } - #[doc = "0x14 - Controller Status"] - #[inline(always)] - pub const fn msr(&self) -> &Msr { - &self.msr - } - #[doc = "0x18 - Controller Interrupt Enable"] - #[inline(always)] - pub const fn mier(&self) -> &Mier { - &self.mier - } - #[doc = "0x1c - Controller DMA Enable"] - #[inline(always)] - pub const fn mder(&self) -> &Mder { - &self.mder - } - #[doc = "0x20 - Controller Configuration 0"] - #[inline(always)] - pub const fn mcfgr0(&self) -> &Mcfgr0 { - &self.mcfgr0 - } - #[doc = "0x24 - Controller Configuration 1"] - #[inline(always)] - pub const fn mcfgr1(&self) -> &Mcfgr1 { - &self.mcfgr1 - } - #[doc = "0x28 - Controller Configuration 2"] - #[inline(always)] - pub const fn mcfgr2(&self) -> &Mcfgr2 { - &self.mcfgr2 - } - #[doc = "0x2c - Controller Configuration 3"] - #[inline(always)] - pub const fn mcfgr3(&self) -> &Mcfgr3 { - &self.mcfgr3 - } - #[doc = "0x40 - Controller Data Match"] - #[inline(always)] - pub const fn mdmr(&self) -> &Mdmr { - &self.mdmr - } - #[doc = "0x48 - Controller Clock Configuration 0"] - #[inline(always)] - pub const fn mccr0(&self) -> &Mccr0 { - &self.mccr0 - } - #[doc = "0x50 - Controller Clock Configuration 1"] - #[inline(always)] - pub const fn mccr1(&self) -> &Mccr1 { - &self.mccr1 - } - #[doc = "0x58 - Controller FIFO Control"] - #[inline(always)] - pub const fn mfcr(&self) -> &Mfcr { - &self.mfcr - } - #[doc = "0x5c - Controller FIFO Status"] - #[inline(always)] - pub const fn mfsr(&self) -> &Mfsr { - &self.mfsr - } - #[doc = "0x60 - Controller Transmit Data"] - #[inline(always)] - pub const fn mtdr(&self) -> &Mtdr { - &self.mtdr - } - #[doc = "0x70 - Controller Receive Data"] - #[inline(always)] - pub const fn mrdr(&self) -> &Mrdr { - &self.mrdr - } - #[doc = "0x78 - Controller Receive Data Read Only"] - #[inline(always)] - pub const fn mrdror(&self) -> &Mrdror { - &self.mrdror - } - #[doc = "0x110 - Target Control"] - #[inline(always)] - pub const fn scr(&self) -> &Scr { - &self.scr - } - #[doc = "0x114 - Target Status"] - #[inline(always)] - pub const fn ssr(&self) -> &Ssr { - &self.ssr - } - #[doc = "0x118 - Target Interrupt Enable"] - #[inline(always)] - pub const fn sier(&self) -> &Sier { - &self.sier - } - #[doc = "0x11c - Target DMA Enable"] - #[inline(always)] - pub const fn sder(&self) -> &Sder { - &self.sder - } - #[doc = "0x120 - Target Configuration 0"] - #[inline(always)] - pub const fn scfgr0(&self) -> &Scfgr0 { - &self.scfgr0 - } - #[doc = "0x124 - Target Configuration 1"] - #[inline(always)] - pub const fn scfgr1(&self) -> &Scfgr1 { - &self.scfgr1 - } - #[doc = "0x128 - Target Configuration 2"] - #[inline(always)] - pub const fn scfgr2(&self) -> &Scfgr2 { - &self.scfgr2 - } - #[doc = "0x140 - Target Address Match"] - #[inline(always)] - pub const fn samr(&self) -> &Samr { - &self.samr - } - #[doc = "0x150 - Target Address Status"] - #[inline(always)] - pub const fn sasr(&self) -> &Sasr { - &self.sasr - } - #[doc = "0x154 - Target Transmit ACK"] - #[inline(always)] - pub const fn star(&self) -> &Star { - &self.star - } - #[doc = "0x160 - Target Transmit Data"] - #[inline(always)] - pub const fn stdr(&self) -> &Stdr { - &self.stdr - } - #[doc = "0x170 - Target Receive Data"] - #[inline(always)] - pub const fn srdr(&self) -> &Srdr { - &self.srdr - } - #[doc = "0x178 - Target Receive Data Read Only"] - #[inline(always)] - pub const fn srdror(&self) -> &Srdror { - &self.srdror - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "MCR (rw) register accessor: Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] -#[doc(alias = "MCR")] -pub type Mcr = crate::Reg; -#[doc = "Controller Control"] -pub mod mcr; -#[doc = "MSR (rw) register accessor: Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] -#[doc(alias = "MSR")] -pub type Msr = crate::Reg; -#[doc = "Controller Status"] -pub mod msr; -#[doc = "MIER (rw) register accessor: Controller Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mier`] module"] -#[doc(alias = "MIER")] -pub type Mier = crate::Reg; -#[doc = "Controller Interrupt Enable"] -pub mod mier; -#[doc = "MDER (rw) register accessor: Controller DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mder::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mder::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mder`] module"] -#[doc(alias = "MDER")] -pub type Mder = crate::Reg; -#[doc = "Controller DMA Enable"] -pub mod mder; -#[doc = "MCFGR0 (rw) register accessor: Controller Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr0`] module"] -#[doc(alias = "MCFGR0")] -pub type Mcfgr0 = crate::Reg; -#[doc = "Controller Configuration 0"] -pub mod mcfgr0; -#[doc = "MCFGR1 (rw) register accessor: Controller Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr1`] module"] -#[doc(alias = "MCFGR1")] -pub type Mcfgr1 = crate::Reg; -#[doc = "Controller Configuration 1"] -pub mod mcfgr1; -#[doc = "MCFGR2 (rw) register accessor: Controller Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr2`] module"] -#[doc(alias = "MCFGR2")] -pub type Mcfgr2 = crate::Reg; -#[doc = "Controller Configuration 2"] -pub mod mcfgr2; -#[doc = "MCFGR3 (rw) register accessor: Controller Configuration 3\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcfgr3`] module"] -#[doc(alias = "MCFGR3")] -pub type Mcfgr3 = crate::Reg; -#[doc = "Controller Configuration 3"] -pub mod mcfgr3; -#[doc = "MDMR (rw) register accessor: Controller Data Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdmr`] module"] -#[doc(alias = "MDMR")] -pub type Mdmr = crate::Reg; -#[doc = "Controller Data Match"] -pub mod mdmr; -#[doc = "MCCR0 (rw) register accessor: Controller Clock Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mccr0`] module"] -#[doc(alias = "MCCR0")] -pub type Mccr0 = crate::Reg; -#[doc = "Controller Clock Configuration 0"] -pub mod mccr0; -#[doc = "MCCR1 (rw) register accessor: Controller Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mccr1`] module"] -#[doc(alias = "MCCR1")] -pub type Mccr1 = crate::Reg; -#[doc = "Controller Clock Configuration 1"] -pub mod mccr1; -#[doc = "MFCR (rw) register accessor: Controller FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mfcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mfcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfcr`] module"] -#[doc(alias = "MFCR")] -pub type Mfcr = crate::Reg; -#[doc = "Controller FIFO Control"] -pub mod mfcr; -#[doc = "MFSR (r) register accessor: Controller FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mfsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfsr`] module"] -#[doc(alias = "MFSR")] -pub type Mfsr = crate::Reg; -#[doc = "Controller FIFO Status"] -pub mod mfsr; -#[doc = "MTDR (w) register accessor: Controller Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtdr`] module"] -#[doc(alias = "MTDR")] -pub type Mtdr = crate::Reg; -#[doc = "Controller Transmit Data"] -pub mod mtdr; -#[doc = "MRDR (r) register accessor: Controller Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdr`] module"] -#[doc(alias = "MRDR")] -pub type Mrdr = crate::Reg; -#[doc = "Controller Receive Data"] -pub mod mrdr; -#[doc = "MRDROR (r) register accessor: Controller Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrdror`] module"] -#[doc(alias = "MRDROR")] -pub type Mrdror = crate::Reg; -#[doc = "Controller Receive Data Read Only"] -pub mod mrdror; -#[doc = "SCR (rw) register accessor: Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] -#[doc(alias = "SCR")] -pub type Scr = crate::Reg; -#[doc = "Target Control"] -pub mod scr; -#[doc = "SSR (rw) register accessor: Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssr`] module"] -#[doc(alias = "SSR")] -pub type Ssr = crate::Reg; -#[doc = "Target Status"] -pub mod ssr; -#[doc = "SIER (rw) register accessor: Target Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sier`] module"] -#[doc(alias = "SIER")] -pub type Sier = crate::Reg; -#[doc = "Target Interrupt Enable"] -pub mod sier; -#[doc = "SDER (rw) register accessor: Target DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sder::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sder::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sder`] module"] -#[doc(alias = "SDER")] -pub type Sder = crate::Reg; -#[doc = "Target DMA Enable"] -pub mod sder; -#[doc = "SCFGR0 (rw) register accessor: Target Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scfgr0`] module"] -#[doc(alias = "SCFGR0")] -pub type Scfgr0 = crate::Reg; -#[doc = "Target Configuration 0"] -pub mod scfgr0; -#[doc = "SCFGR1 (rw) register accessor: Target Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scfgr1`] module"] -#[doc(alias = "SCFGR1")] -pub type Scfgr1 = crate::Reg; -#[doc = "Target Configuration 1"] -pub mod scfgr1; -#[doc = "SCFGR2 (rw) register accessor: Target Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scfgr2`] module"] -#[doc(alias = "SCFGR2")] -pub type Scfgr2 = crate::Reg; -#[doc = "Target Configuration 2"] -pub mod scfgr2; -#[doc = "SAMR (rw) register accessor: Target Address Match\n\nYou can [`read`](crate::Reg::read) this register and get [`samr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`samr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@samr`] module"] -#[doc(alias = "SAMR")] -pub type Samr = crate::Reg; -#[doc = "Target Address Match"] -pub mod samr; -#[doc = "SASR (r) register accessor: Target Address Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sasr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sasr`] module"] -#[doc(alias = "SASR")] -pub type Sasr = crate::Reg; -#[doc = "Target Address Status"] -pub mod sasr; -#[doc = "STAR (rw) register accessor: Target Transmit ACK\n\nYou can [`read`](crate::Reg::read) this register and get [`star::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`star::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@star`] module"] -#[doc(alias = "STAR")] -pub type Star = crate::Reg; -#[doc = "Target Transmit ACK"] -pub mod star; -#[doc = "STDR (w) register accessor: Target Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stdr`] module"] -#[doc(alias = "STDR")] -pub type Stdr = crate::Reg; -#[doc = "Target Transmit Data"] -pub mod stdr; -#[doc = "SRDR (r) register accessor: Target Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`srdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdr`] module"] -#[doc(alias = "SRDR")] -pub type Srdr = crate::Reg; -#[doc = "Target Receive Data"] -pub mod srdr; -#[doc = "SRDROR (r) register accessor: Target Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`srdror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srdror`] module"] -#[doc(alias = "SRDROR")] -pub type Srdror = crate::Reg; -#[doc = "Target Receive Data Read Only"] -pub mod srdror; diff --git a/mcxa276-pac/src/lpi2c0/mccr0.rs b/mcxa276-pac/src/lpi2c0/mccr0.rs deleted file mode 100644 index bb89863ac..000000000 --- a/mcxa276-pac/src/lpi2c0/mccr0.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MCCR0` reader"] -pub type R = crate::R; -#[doc = "Register `MCCR0` writer"] -pub type W = crate::W; -#[doc = "Field `CLKLO` reader - Clock Low Period"] -pub type ClkloR = crate::FieldReader; -#[doc = "Field `CLKLO` writer - Clock Low Period"] -pub type ClkloW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `CLKHI` reader - Clock High Period"] -pub type ClkhiR = crate::FieldReader; -#[doc = "Field `CLKHI` writer - Clock High Period"] -pub type ClkhiW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `SETHOLD` reader - Setup Hold Delay"] -pub type SetholdR = crate::FieldReader; -#[doc = "Field `SETHOLD` writer - Setup Hold Delay"] -pub type SetholdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `DATAVD` reader - Data Valid Delay"] -pub type DatavdR = crate::FieldReader; -#[doc = "Field `DATAVD` writer - Data Valid Delay"] -pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Clock Low Period"] - #[inline(always)] - pub fn clklo(&self) -> ClkloR { - ClkloR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 8:13 - Clock High Period"] - #[inline(always)] - pub fn clkhi(&self) -> ClkhiR { - ClkhiR::new(((self.bits >> 8) & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Setup Hold Delay"] - #[inline(always)] - pub fn sethold(&self) -> SetholdR { - SetholdR::new(((self.bits >> 16) & 0x3f) as u8) - } - #[doc = "Bits 24:29 - Data Valid Delay"] - #[inline(always)] - pub fn datavd(&self) -> DatavdR { - DatavdR::new(((self.bits >> 24) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Clock Low Period"] - #[inline(always)] - pub fn clklo(&mut self) -> ClkloW { - ClkloW::new(self, 0) - } - #[doc = "Bits 8:13 - Clock High Period"] - #[inline(always)] - pub fn clkhi(&mut self) -> ClkhiW { - ClkhiW::new(self, 8) - } - #[doc = "Bits 16:21 - Setup Hold Delay"] - #[inline(always)] - pub fn sethold(&mut self) -> SetholdW { - SetholdW::new(self, 16) - } - #[doc = "Bits 24:29 - Data Valid Delay"] - #[inline(always)] - pub fn datavd(&mut self) -> DatavdW { - DatavdW::new(self, 24) - } -} -#[doc = "Controller Clock Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mccr0Spec; -impl crate::RegisterSpec for Mccr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mccr0::R`](R) reader structure"] -impl crate::Readable for Mccr0Spec {} -#[doc = "`write(|w| ..)` method takes [`mccr0::W`](W) writer structure"] -impl crate::Writable for Mccr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCCR0 to value 0"] -impl crate::Resettable for Mccr0Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mccr1.rs b/mcxa276-pac/src/lpi2c0/mccr1.rs deleted file mode 100644 index 5d1ec7c5b..000000000 --- a/mcxa276-pac/src/lpi2c0/mccr1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `MCCR1` reader"] -pub type R = crate::R; -#[doc = "Register `MCCR1` writer"] -pub type W = crate::W; -#[doc = "Field `CLKLO` reader - Clock Low Period"] -pub type ClkloR = crate::FieldReader; -#[doc = "Field `CLKLO` writer - Clock Low Period"] -pub type ClkloW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `CLKHI` reader - Clock High Period"] -pub type ClkhiR = crate::FieldReader; -#[doc = "Field `CLKHI` writer - Clock High Period"] -pub type ClkhiW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `SETHOLD` reader - Setup Hold Delay"] -pub type SetholdR = crate::FieldReader; -#[doc = "Field `SETHOLD` writer - Setup Hold Delay"] -pub type SetholdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `DATAVD` reader - Data Valid Delay"] -pub type DatavdR = crate::FieldReader; -#[doc = "Field `DATAVD` writer - Data Valid Delay"] -pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Clock Low Period"] - #[inline(always)] - pub fn clklo(&self) -> ClkloR { - ClkloR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 8:13 - Clock High Period"] - #[inline(always)] - pub fn clkhi(&self) -> ClkhiR { - ClkhiR::new(((self.bits >> 8) & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Setup Hold Delay"] - #[inline(always)] - pub fn sethold(&self) -> SetholdR { - SetholdR::new(((self.bits >> 16) & 0x3f) as u8) - } - #[doc = "Bits 24:29 - Data Valid Delay"] - #[inline(always)] - pub fn datavd(&self) -> DatavdR { - DatavdR::new(((self.bits >> 24) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Clock Low Period"] - #[inline(always)] - pub fn clklo(&mut self) -> ClkloW { - ClkloW::new(self, 0) - } - #[doc = "Bits 8:13 - Clock High Period"] - #[inline(always)] - pub fn clkhi(&mut self) -> ClkhiW { - ClkhiW::new(self, 8) - } - #[doc = "Bits 16:21 - Setup Hold Delay"] - #[inline(always)] - pub fn sethold(&mut self) -> SetholdW { - SetholdW::new(self, 16) - } - #[doc = "Bits 24:29 - Data Valid Delay"] - #[inline(always)] - pub fn datavd(&mut self) -> DatavdW { - DatavdW::new(self, 24) - } -} -#[doc = "Controller Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mccr1Spec; -impl crate::RegisterSpec for Mccr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mccr1::R`](R) reader structure"] -impl crate::Readable for Mccr1Spec {} -#[doc = "`write(|w| ..)` method takes [`mccr1::W`](W) writer structure"] -impl crate::Writable for Mccr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCCR1 to value 0"] -impl crate::Resettable for Mccr1Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr0.rs b/mcxa276-pac/src/lpi2c0/mcfgr0.rs deleted file mode 100644 index ce252d81f..000000000 --- a/mcxa276-pac/src/lpi2c0/mcfgr0.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `MCFGR0` reader"] -pub type R = crate::R; -#[doc = "Register `MCFGR0` writer"] -pub type W = crate::W; -#[doc = "Host Request Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hren { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HREN` reader - Host Request Enable"] -pub type HrenR = crate::BitReader; -impl HrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hren { - match self.bits { - false => Hren::Disabled, - true => Hren::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Hren::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Hren::Enabled - } -} -#[doc = "Field `HREN` writer - Host Request Enable"] -pub type HrenW<'a, REG> = crate::BitWriter<'a, REG, Hren>; -impl<'a, REG> HrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Hren::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Hren::Enabled) - } -} -#[doc = "Host Request Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hrpol { - #[doc = "0: Active low"] - ActiveLow = 0, - #[doc = "1: Active high"] - ActiveHigh = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hrpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HRPOL` reader - Host Request Polarity"] -pub type HrpolR = crate::BitReader; -impl HrpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hrpol { - match self.bits { - false => Hrpol::ActiveLow, - true => Hrpol::ActiveHigh, - } - } - #[doc = "Active low"] - #[inline(always)] - pub fn is_active_low(&self) -> bool { - *self == Hrpol::ActiveLow - } - #[doc = "Active high"] - #[inline(always)] - pub fn is_active_high(&self) -> bool { - *self == Hrpol::ActiveHigh - } -} -#[doc = "Field `HRPOL` writer - Host Request Polarity"] -pub type HrpolW<'a, REG> = crate::BitWriter<'a, REG, Hrpol>; -impl<'a, REG> HrpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active low"] - #[inline(always)] - pub fn active_low(self) -> &'a mut crate::W { - self.variant(Hrpol::ActiveLow) - } - #[doc = "Active high"] - #[inline(always)] - pub fn active_high(self) -> &'a mut crate::W { - self.variant(Hrpol::ActiveHigh) - } -} -#[doc = "Host Request Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hrsel { - #[doc = "0: Host request input is pin HREQ"] - Disabled = 0, - #[doc = "1: Host request input is input trigger"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hrsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HRSEL` reader - Host Request Select"] -pub type HrselR = crate::BitReader; -impl HrselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hrsel { - match self.bits { - false => Hrsel::Disabled, - true => Hrsel::Enabled, - } - } - #[doc = "Host request input is pin HREQ"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Hrsel::Disabled - } - #[doc = "Host request input is input trigger"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Hrsel::Enabled - } -} -#[doc = "Field `HRSEL` writer - Host Request Select"] -pub type HrselW<'a, REG> = crate::BitWriter<'a, REG, Hrsel>; -impl<'a, REG> HrselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Host request input is pin HREQ"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Hrsel::Disabled) - } - #[doc = "Host request input is input trigger"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Hrsel::Enabled) - } -} -#[doc = "Host Request Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hrdir { - #[doc = "0: HREQ pin is input (for LPI2C controller)"] - Input = 0, - #[doc = "1: HREQ pin is output (for LPI2C target)"] - Output = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hrdir) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HRDIR` reader - Host Request Direction"] -pub type HrdirR = crate::BitReader; -impl HrdirR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hrdir { - match self.bits { - false => Hrdir::Input, - true => Hrdir::Output, - } - } - #[doc = "HREQ pin is input (for LPI2C controller)"] - #[inline(always)] - pub fn is_input(&self) -> bool { - *self == Hrdir::Input - } - #[doc = "HREQ pin is output (for LPI2C target)"] - #[inline(always)] - pub fn is_output(&self) -> bool { - *self == Hrdir::Output - } -} -#[doc = "Field `HRDIR` writer - Host Request Direction"] -pub type HrdirW<'a, REG> = crate::BitWriter<'a, REG, Hrdir>; -impl<'a, REG> HrdirW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "HREQ pin is input (for LPI2C controller)"] - #[inline(always)] - pub fn input(self) -> &'a mut crate::W { - self.variant(Hrdir::Input) - } - #[doc = "HREQ pin is output (for LPI2C target)"] - #[inline(always)] - pub fn output(self) -> &'a mut crate::W { - self.variant(Hrdir::Output) - } -} -#[doc = "Circular FIFO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cirfifo { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cirfifo) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CIRFIFO` reader - Circular FIFO Enable"] -pub type CirfifoR = crate::BitReader; -impl CirfifoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cirfifo { - match self.bits { - false => Cirfifo::Disabled, - true => Cirfifo::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cirfifo::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cirfifo::Enabled - } -} -#[doc = "Field `CIRFIFO` writer - Circular FIFO Enable"] -pub type CirfifoW<'a, REG> = crate::BitWriter<'a, REG, Cirfifo>; -impl<'a, REG> CirfifoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cirfifo::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cirfifo::Enabled) - } -} -#[doc = "Receive Data Match Only\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdmo { - #[doc = "0: Received data is stored in the receive FIFO"] - Disabled = 0, - #[doc = "1: Received data is discarded unless MSR\\[DMF\\] is set"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdmo) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDMO` reader - Receive Data Match Only"] -pub type RdmoR = crate::BitReader; -impl RdmoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdmo { - match self.bits { - false => Rdmo::Disabled, - true => Rdmo::Enabled, - } - } - #[doc = "Received data is stored in the receive FIFO"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdmo::Disabled - } - #[doc = "Received data is discarded unless MSR\\[DMF\\] is set"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdmo::Enabled - } -} -#[doc = "Field `RDMO` writer - Receive Data Match Only"] -pub type RdmoW<'a, REG> = crate::BitWriter<'a, REG, Rdmo>; -impl<'a, REG> RdmoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Received data is stored in the receive FIFO"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rdmo::Disabled) - } - #[doc = "Received data is discarded unless MSR\\[DMF\\] is set"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rdmo::Enabled) - } -} -#[doc = "Relaxed Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Relax { - #[doc = "0: Normal transfer"] - NormalTransfer = 0, - #[doc = "1: Relaxed transfer"] - RelaxedTransfer = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Relax) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RELAX` reader - Relaxed Mode"] -pub type RelaxR = crate::BitReader; -impl RelaxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Relax { - match self.bits { - false => Relax::NormalTransfer, - true => Relax::RelaxedTransfer, - } - } - #[doc = "Normal transfer"] - #[inline(always)] - pub fn is_normal_transfer(&self) -> bool { - *self == Relax::NormalTransfer - } - #[doc = "Relaxed transfer"] - #[inline(always)] - pub fn is_relaxed_transfer(&self) -> bool { - *self == Relax::RelaxedTransfer - } -} -#[doc = "Field `RELAX` writer - Relaxed Mode"] -pub type RelaxW<'a, REG> = crate::BitWriter<'a, REG, Relax>; -impl<'a, REG> RelaxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal transfer"] - #[inline(always)] - pub fn normal_transfer(self) -> &'a mut crate::W { - self.variant(Relax::NormalTransfer) - } - #[doc = "Relaxed transfer"] - #[inline(always)] - pub fn relaxed_transfer(self) -> &'a mut crate::W { - self.variant(Relax::RelaxedTransfer) - } -} -#[doc = "Abort Transfer\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Abort { - #[doc = "0: Normal transfer"] - Disabled = 0, - #[doc = "1: Abort existing transfer and do not start a new one"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Abort) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ABORT` reader - Abort Transfer"] -pub type AbortR = crate::BitReader; -impl AbortR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Abort { - match self.bits { - false => Abort::Disabled, - true => Abort::Enabled, - } - } - #[doc = "Normal transfer"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Abort::Disabled - } - #[doc = "Abort existing transfer and do not start a new one"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Abort::Enabled - } -} -#[doc = "Field `ABORT` writer - Abort Transfer"] -pub type AbortW<'a, REG> = crate::BitWriter<'a, REG, Abort>; -impl<'a, REG> AbortW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal transfer"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Abort::Disabled) - } - #[doc = "Abort existing transfer and do not start a new one"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Abort::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Host Request Enable"] - #[inline(always)] - pub fn hren(&self) -> HrenR { - HrenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Host Request Polarity"] - #[inline(always)] - pub fn hrpol(&self) -> HrpolR { - HrpolR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Host Request Select"] - #[inline(always)] - pub fn hrsel(&self) -> HrselR { - HrselR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Host Request Direction"] - #[inline(always)] - pub fn hrdir(&self) -> HrdirR { - HrdirR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Circular FIFO Enable"] - #[inline(always)] - pub fn cirfifo(&self) -> CirfifoR { - CirfifoR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Receive Data Match Only"] - #[inline(always)] - pub fn rdmo(&self) -> RdmoR { - RdmoR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 16 - Relaxed Mode"] - #[inline(always)] - pub fn relax(&self) -> RelaxR { - RelaxR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Abort Transfer"] - #[inline(always)] - pub fn abort(&self) -> AbortR { - AbortR::new(((self.bits >> 17) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Host Request Enable"] - #[inline(always)] - pub fn hren(&mut self) -> HrenW { - HrenW::new(self, 0) - } - #[doc = "Bit 1 - Host Request Polarity"] - #[inline(always)] - pub fn hrpol(&mut self) -> HrpolW { - HrpolW::new(self, 1) - } - #[doc = "Bit 2 - Host Request Select"] - #[inline(always)] - pub fn hrsel(&mut self) -> HrselW { - HrselW::new(self, 2) - } - #[doc = "Bit 3 - Host Request Direction"] - #[inline(always)] - pub fn hrdir(&mut self) -> HrdirW { - HrdirW::new(self, 3) - } - #[doc = "Bit 8 - Circular FIFO Enable"] - #[inline(always)] - pub fn cirfifo(&mut self) -> CirfifoW { - CirfifoW::new(self, 8) - } - #[doc = "Bit 9 - Receive Data Match Only"] - #[inline(always)] - pub fn rdmo(&mut self) -> RdmoW { - RdmoW::new(self, 9) - } - #[doc = "Bit 16 - Relaxed Mode"] - #[inline(always)] - pub fn relax(&mut self) -> RelaxW { - RelaxW::new(self, 16) - } - #[doc = "Bit 17 - Abort Transfer"] - #[inline(always)] - pub fn abort(&mut self) -> AbortW { - AbortW::new(self, 17) - } -} -#[doc = "Controller Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mcfgr0Spec; -impl crate::RegisterSpec for Mcfgr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mcfgr0::R`](R) reader structure"] -impl crate::Readable for Mcfgr0Spec {} -#[doc = "`write(|w| ..)` method takes [`mcfgr0::W`](W) writer structure"] -impl crate::Writable for Mcfgr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCFGR0 to value 0"] -impl crate::Resettable for Mcfgr0Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr1.rs b/mcxa276-pac/src/lpi2c0/mcfgr1.rs deleted file mode 100644 index 885d571eb..000000000 --- a/mcxa276-pac/src/lpi2c0/mcfgr1.rs +++ /dev/null @@ -1,767 +0,0 @@ -#[doc = "Register `MCFGR1` reader"] -pub type R = crate::R; -#[doc = "Register `MCFGR1` writer"] -pub type W = crate::W; -#[doc = "Prescaler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Prescale { - #[doc = "0: Divide by 1"] - DivideBy1 = 0, - #[doc = "1: Divide by 2"] - DivideBy2 = 1, - #[doc = "2: Divide by 4"] - DivideBy4 = 2, - #[doc = "3: Divide by 8"] - DivideBy8 = 3, - #[doc = "4: Divide by 16"] - DivideBy16 = 4, - #[doc = "5: Divide by 32"] - DivideBy32 = 5, - #[doc = "6: Divide by 64"] - DivideBy64 = 6, - #[doc = "7: Divide by 128"] - DivideBy128 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Prescale) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Prescale { - type Ux = u8; -} -impl crate::IsEnum for Prescale {} -#[doc = "Field `PRESCALE` reader - Prescaler"] -pub type PrescaleR = crate::FieldReader; -impl PrescaleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prescale { - match self.bits { - 0 => Prescale::DivideBy1, - 1 => Prescale::DivideBy2, - 2 => Prescale::DivideBy4, - 3 => Prescale::DivideBy8, - 4 => Prescale::DivideBy16, - 5 => Prescale::DivideBy32, - 6 => Prescale::DivideBy64, - 7 => Prescale::DivideBy128, - _ => unreachable!(), - } - } - #[doc = "Divide by 1"] - #[inline(always)] - pub fn is_divide_by_1(&self) -> bool { - *self == Prescale::DivideBy1 - } - #[doc = "Divide by 2"] - #[inline(always)] - pub fn is_divide_by_2(&self) -> bool { - *self == Prescale::DivideBy2 - } - #[doc = "Divide by 4"] - #[inline(always)] - pub fn is_divide_by_4(&self) -> bool { - *self == Prescale::DivideBy4 - } - #[doc = "Divide by 8"] - #[inline(always)] - pub fn is_divide_by_8(&self) -> bool { - *self == Prescale::DivideBy8 - } - #[doc = "Divide by 16"] - #[inline(always)] - pub fn is_divide_by_16(&self) -> bool { - *self == Prescale::DivideBy16 - } - #[doc = "Divide by 32"] - #[inline(always)] - pub fn is_divide_by_32(&self) -> bool { - *self == Prescale::DivideBy32 - } - #[doc = "Divide by 64"] - #[inline(always)] - pub fn is_divide_by_64(&self) -> bool { - *self == Prescale::DivideBy64 - } - #[doc = "Divide by 128"] - #[inline(always)] - pub fn is_divide_by_128(&self) -> bool { - *self == Prescale::DivideBy128 - } -} -#[doc = "Field `PRESCALE` writer - Prescaler"] -pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescale, crate::Safe>; -impl<'a, REG> PrescaleW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Divide by 1"] - #[inline(always)] - pub fn divide_by_1(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy1) - } - #[doc = "Divide by 2"] - #[inline(always)] - pub fn divide_by_2(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy2) - } - #[doc = "Divide by 4"] - #[inline(always)] - pub fn divide_by_4(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy4) - } - #[doc = "Divide by 8"] - #[inline(always)] - pub fn divide_by_8(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy8) - } - #[doc = "Divide by 16"] - #[inline(always)] - pub fn divide_by_16(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy16) - } - #[doc = "Divide by 32"] - #[inline(always)] - pub fn divide_by_32(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy32) - } - #[doc = "Divide by 64"] - #[inline(always)] - pub fn divide_by_64(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy64) - } - #[doc = "Divide by 128"] - #[inline(always)] - pub fn divide_by_128(self) -> &'a mut crate::W { - self.variant(Prescale::DivideBy128) - } -} -#[doc = "Automatic Stop Generation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Autostop { - #[doc = "0: No effect"] - Disabled = 0, - #[doc = "1: Stop automatically generated"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Autostop) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AUTOSTOP` reader - Automatic Stop Generation"] -pub type AutostopR = crate::BitReader; -impl AutostopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Autostop { - match self.bits { - false => Autostop::Disabled, - true => Autostop::Enabled, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Autostop::Disabled - } - #[doc = "Stop automatically generated"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Autostop::Enabled - } -} -#[doc = "Field `AUTOSTOP` writer - Automatic Stop Generation"] -pub type AutostopW<'a, REG> = crate::BitWriter<'a, REG, Autostop>; -impl<'a, REG> AutostopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Autostop::Disabled) - } - #[doc = "Stop automatically generated"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Autostop::Enabled) - } -} -#[doc = "Ignore NACK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ignack { - #[doc = "0: No effect"] - Disabled = 0, - #[doc = "1: Treat a received NACK as an ACK"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ignack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IGNACK` reader - Ignore NACK"] -pub type IgnackR = crate::BitReader; -impl IgnackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ignack { - match self.bits { - false => Ignack::Disabled, - true => Ignack::Enabled, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ignack::Disabled - } - #[doc = "Treat a received NACK as an ACK"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ignack::Enabled - } -} -#[doc = "Field `IGNACK` writer - Ignore NACK"] -pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG, Ignack>; -impl<'a, REG> IgnackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ignack::Disabled) - } - #[doc = "Treat a received NACK as an ACK"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ignack::Enabled) - } -} -#[doc = "Timeout Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Timecfg { - #[doc = "0: SCL"] - IfSclLow = 0, - #[doc = "1: SCL or SDA"] - IfSclOrSdaLow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Timecfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIMECFG` reader - Timeout Configuration"] -pub type TimecfgR = crate::BitReader; -impl TimecfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Timecfg { - match self.bits { - false => Timecfg::IfSclLow, - true => Timecfg::IfSclOrSdaLow, - } - } - #[doc = "SCL"] - #[inline(always)] - pub fn is_if_scl_low(&self) -> bool { - *self == Timecfg::IfSclLow - } - #[doc = "SCL or SDA"] - #[inline(always)] - pub fn is_if_scl_or_sda_low(&self) -> bool { - *self == Timecfg::IfSclOrSdaLow - } -} -#[doc = "Field `TIMECFG` writer - Timeout Configuration"] -pub type TimecfgW<'a, REG> = crate::BitWriter<'a, REG, Timecfg>; -impl<'a, REG> TimecfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SCL"] - #[inline(always)] - pub fn if_scl_low(self) -> &'a mut crate::W { - self.variant(Timecfg::IfSclLow) - } - #[doc = "SCL or SDA"] - #[inline(always)] - pub fn if_scl_or_sda_low(self) -> &'a mut crate::W { - self.variant(Timecfg::IfSclOrSdaLow) - } -} -#[doc = "Stop Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stopcfg { - #[doc = "0: Any Stop condition"] - AnyStop = 0, - #[doc = "1: Last Stop condition"] - LastStop = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stopcfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STOPCFG` reader - Stop Configuration"] -pub type StopcfgR = crate::BitReader; -impl StopcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stopcfg { - match self.bits { - false => Stopcfg::AnyStop, - true => Stopcfg::LastStop, - } - } - #[doc = "Any Stop condition"] - #[inline(always)] - pub fn is_any_stop(&self) -> bool { - *self == Stopcfg::AnyStop - } - #[doc = "Last Stop condition"] - #[inline(always)] - pub fn is_last_stop(&self) -> bool { - *self == Stopcfg::LastStop - } -} -#[doc = "Field `STOPCFG` writer - Stop Configuration"] -pub type StopcfgW<'a, REG> = crate::BitWriter<'a, REG, Stopcfg>; -impl<'a, REG> StopcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Any Stop condition"] - #[inline(always)] - pub fn any_stop(self) -> &'a mut crate::W { - self.variant(Stopcfg::AnyStop) - } - #[doc = "Last Stop condition"] - #[inline(always)] - pub fn last_stop(self) -> &'a mut crate::W { - self.variant(Stopcfg::LastStop) - } -} -#[doc = "Start Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Startcfg { - #[doc = "0: Sets when both I2C bus and LPI2C controller are idle"] - BothI2cAndLpi2cIdle = 0, - #[doc = "1: Sets when I2C bus is idle"] - I2cIdle = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Startcfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STARTCFG` reader - Start Configuration"] -pub type StartcfgR = crate::BitReader; -impl StartcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Startcfg { - match self.bits { - false => Startcfg::BothI2cAndLpi2cIdle, - true => Startcfg::I2cIdle, - } - } - #[doc = "Sets when both I2C bus and LPI2C controller are idle"] - #[inline(always)] - pub fn is_both_i2c_and_lpi2c_idle(&self) -> bool { - *self == Startcfg::BothI2cAndLpi2cIdle - } - #[doc = "Sets when I2C bus is idle"] - #[inline(always)] - pub fn is_i2c_idle(&self) -> bool { - *self == Startcfg::I2cIdle - } -} -#[doc = "Field `STARTCFG` writer - Start Configuration"] -pub type StartcfgW<'a, REG> = crate::BitWriter<'a, REG, Startcfg>; -impl<'a, REG> StartcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Sets when both I2C bus and LPI2C controller are idle"] - #[inline(always)] - pub fn both_i2c_and_lpi2c_idle(self) -> &'a mut crate::W { - self.variant(Startcfg::BothI2cAndLpi2cIdle) - } - #[doc = "Sets when I2C bus is idle"] - #[inline(always)] - pub fn i2c_idle(self) -> &'a mut crate::W { - self.variant(Startcfg::I2cIdle) - } -} -#[doc = "Match Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Matcfg { - #[doc = "0: Match is disabled"] - Disabled = 0, - #[doc = "2: Match is enabled: first data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] - FirstDataWordEqualsMatch0OrMatch1 = 2, - #[doc = "3: Match is enabled: any data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] - AnyDataWordEqualsMatch0OrMatch1 = 3, - #[doc = "4: Match is enabled: (first data word equals MDMR\\[MATCH0\\]) AND (second data word equals MDMR\\[MATCH1)"] - FirstDataWordMatch0AndSecondDataWordMatch1 = 4, - #[doc = "5: Match is enabled: (any data word equals MDMR\\[MATCH0\\]) AND (next data word equals MDMR\\[MATCH1)"] - AnyDataWordMatch0NextDataWordMatch1 = 5, - #[doc = "6: Match is enabled: (first data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] - FirstDataWordAndMatch1EqualsMatch0AndMatch1 = 6, - #[doc = "7: Match is enabled: (any data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] - AnyDataWordAndMatch1EqualsMatch0AndMatch1 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Matcfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Matcfg { - type Ux = u8; -} -impl crate::IsEnum for Matcfg {} -#[doc = "Field `MATCFG` reader - Match Configuration"] -pub type MatcfgR = crate::FieldReader; -impl MatcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Matcfg::Disabled), - 2 => Some(Matcfg::FirstDataWordEqualsMatch0OrMatch1), - 3 => Some(Matcfg::AnyDataWordEqualsMatch0OrMatch1), - 4 => Some(Matcfg::FirstDataWordMatch0AndSecondDataWordMatch1), - 5 => Some(Matcfg::AnyDataWordMatch0NextDataWordMatch1), - 6 => Some(Matcfg::FirstDataWordAndMatch1EqualsMatch0AndMatch1), - 7 => Some(Matcfg::AnyDataWordAndMatch1EqualsMatch0AndMatch1), - _ => None, - } - } - #[doc = "Match is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Matcfg::Disabled - } - #[doc = "Match is enabled: first data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] - #[inline(always)] - pub fn is_first_data_word_equals_match0_or_match1(&self) -> bool { - *self == Matcfg::FirstDataWordEqualsMatch0OrMatch1 - } - #[doc = "Match is enabled: any data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] - #[inline(always)] - pub fn is_any_data_word_equals_match0_or_match1(&self) -> bool { - *self == Matcfg::AnyDataWordEqualsMatch0OrMatch1 - } - #[doc = "Match is enabled: (first data word equals MDMR\\[MATCH0\\]) AND (second data word equals MDMR\\[MATCH1)"] - #[inline(always)] - pub fn is_first_data_word_match0_and_second_data_word_match1(&self) -> bool { - *self == Matcfg::FirstDataWordMatch0AndSecondDataWordMatch1 - } - #[doc = "Match is enabled: (any data word equals MDMR\\[MATCH0\\]) AND (next data word equals MDMR\\[MATCH1)"] - #[inline(always)] - pub fn is_any_data_word_match0_next_data_word_match1(&self) -> bool { - *self == Matcfg::AnyDataWordMatch0NextDataWordMatch1 - } - #[doc = "Match is enabled: (first data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] - #[inline(always)] - pub fn is_first_data_word_and_match1_equals_match0_and_match1(&self) -> bool { - *self == Matcfg::FirstDataWordAndMatch1EqualsMatch0AndMatch1 - } - #[doc = "Match is enabled: (any data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] - #[inline(always)] - pub fn is_any_data_word_and_match1_equals_match0_and_match1(&self) -> bool { - *self == Matcfg::AnyDataWordAndMatch1EqualsMatch0AndMatch1 - } -} -#[doc = "Field `MATCFG` writer - Match Configuration"] -pub type MatcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Matcfg>; -impl<'a, REG> MatcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Match is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Matcfg::Disabled) - } - #[doc = "Match is enabled: first data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] - #[inline(always)] - pub fn first_data_word_equals_match0_or_match1(self) -> &'a mut crate::W { - self.variant(Matcfg::FirstDataWordEqualsMatch0OrMatch1) - } - #[doc = "Match is enabled: any data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]"] - #[inline(always)] - pub fn any_data_word_equals_match0_or_match1(self) -> &'a mut crate::W { - self.variant(Matcfg::AnyDataWordEqualsMatch0OrMatch1) - } - #[doc = "Match is enabled: (first data word equals MDMR\\[MATCH0\\]) AND (second data word equals MDMR\\[MATCH1)"] - #[inline(always)] - pub fn first_data_word_match0_and_second_data_word_match1(self) -> &'a mut crate::W { - self.variant(Matcfg::FirstDataWordMatch0AndSecondDataWordMatch1) - } - #[doc = "Match is enabled: (any data word equals MDMR\\[MATCH0\\]) AND (next data word equals MDMR\\[MATCH1)"] - #[inline(always)] - pub fn any_data_word_match0_next_data_word_match1(self) -> &'a mut crate::W { - self.variant(Matcfg::AnyDataWordMatch0NextDataWordMatch1) - } - #[doc = "Match is enabled: (first data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] - #[inline(always)] - pub fn first_data_word_and_match1_equals_match0_and_match1(self) -> &'a mut crate::W { - self.variant(Matcfg::FirstDataWordAndMatch1EqualsMatch0AndMatch1) - } - #[doc = "Match is enabled: (any data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])"] - #[inline(always)] - pub fn any_data_word_and_match1_equals_match0_and_match1(self) -> &'a mut crate::W { - self.variant(Matcfg::AnyDataWordAndMatch1EqualsMatch0AndMatch1) - } -} -#[doc = "Pin Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pincfg { - #[doc = "0: Two-pin open drain mode"] - OpenDrain2Pin = 0, - #[doc = "1: Two-pin output only mode (Ultra-Fast mode)"] - Output2PinOnly = 1, - #[doc = "2: Two-pin push-pull mode"] - PushPull2Pin = 2, - #[doc = "3: Four-pin push-pull mode"] - PushPull4Pin = 3, - #[doc = "4: Two-pin open-drain mode with separate LPI2C target"] - OpenDrain2PinWLpi2cSlave = 4, - #[doc = "5: Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target"] - Output2PinOnlyWLpi2cSlave = 5, - #[doc = "6: Two-pin push-pull mode with separate LPI2C target"] - PushPull2PinWLpi2cSlave = 6, - #[doc = "7: Four-pin push-pull mode (inverted outputs)"] - PushPull4PinWLpi2cSlave = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pincfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pincfg { - type Ux = u8; -} -impl crate::IsEnum for Pincfg {} -#[doc = "Field `PINCFG` reader - Pin Configuration"] -pub type PincfgR = crate::FieldReader; -impl PincfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pincfg { - match self.bits { - 0 => Pincfg::OpenDrain2Pin, - 1 => Pincfg::Output2PinOnly, - 2 => Pincfg::PushPull2Pin, - 3 => Pincfg::PushPull4Pin, - 4 => Pincfg::OpenDrain2PinWLpi2cSlave, - 5 => Pincfg::Output2PinOnlyWLpi2cSlave, - 6 => Pincfg::PushPull2PinWLpi2cSlave, - 7 => Pincfg::PushPull4PinWLpi2cSlave, - _ => unreachable!(), - } - } - #[doc = "Two-pin open drain mode"] - #[inline(always)] - pub fn is_open_drain_2_pin(&self) -> bool { - *self == Pincfg::OpenDrain2Pin - } - #[doc = "Two-pin output only mode (Ultra-Fast mode)"] - #[inline(always)] - pub fn is_output_2_pin_only(&self) -> bool { - *self == Pincfg::Output2PinOnly - } - #[doc = "Two-pin push-pull mode"] - #[inline(always)] - pub fn is_push_pull_2_pin(&self) -> bool { - *self == Pincfg::PushPull2Pin - } - #[doc = "Four-pin push-pull mode"] - #[inline(always)] - pub fn is_push_pull_4_pin(&self) -> bool { - *self == Pincfg::PushPull4Pin - } - #[doc = "Two-pin open-drain mode with separate LPI2C target"] - #[inline(always)] - pub fn is_open_drain_2_pin_w_lpi2c_slave(&self) -> bool { - *self == Pincfg::OpenDrain2PinWLpi2cSlave - } - #[doc = "Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target"] - #[inline(always)] - pub fn is_output_2_pin_only_w_lpi2c_slave(&self) -> bool { - *self == Pincfg::Output2PinOnlyWLpi2cSlave - } - #[doc = "Two-pin push-pull mode with separate LPI2C target"] - #[inline(always)] - pub fn is_push_pull_2_pin_w_lpi2c_slave(&self) -> bool { - *self == Pincfg::PushPull2PinWLpi2cSlave - } - #[doc = "Four-pin push-pull mode (inverted outputs)"] - #[inline(always)] - pub fn is_push_pull_4_pin_w_lpi2c_slave(&self) -> bool { - *self == Pincfg::PushPull4PinWLpi2cSlave - } -} -#[doc = "Field `PINCFG` writer - Pin Configuration"] -pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Pincfg, crate::Safe>; -impl<'a, REG> PincfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Two-pin open drain mode"] - #[inline(always)] - pub fn open_drain_2_pin(self) -> &'a mut crate::W { - self.variant(Pincfg::OpenDrain2Pin) - } - #[doc = "Two-pin output only mode (Ultra-Fast mode)"] - #[inline(always)] - pub fn output_2_pin_only(self) -> &'a mut crate::W { - self.variant(Pincfg::Output2PinOnly) - } - #[doc = "Two-pin push-pull mode"] - #[inline(always)] - pub fn push_pull_2_pin(self) -> &'a mut crate::W { - self.variant(Pincfg::PushPull2Pin) - } - #[doc = "Four-pin push-pull mode"] - #[inline(always)] - pub fn push_pull_4_pin(self) -> &'a mut crate::W { - self.variant(Pincfg::PushPull4Pin) - } - #[doc = "Two-pin open-drain mode with separate LPI2C target"] - #[inline(always)] - pub fn open_drain_2_pin_w_lpi2c_slave(self) -> &'a mut crate::W { - self.variant(Pincfg::OpenDrain2PinWLpi2cSlave) - } - #[doc = "Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target"] - #[inline(always)] - pub fn output_2_pin_only_w_lpi2c_slave(self) -> &'a mut crate::W { - self.variant(Pincfg::Output2PinOnlyWLpi2cSlave) - } - #[doc = "Two-pin push-pull mode with separate LPI2C target"] - #[inline(always)] - pub fn push_pull_2_pin_w_lpi2c_slave(self) -> &'a mut crate::W { - self.variant(Pincfg::PushPull2PinWLpi2cSlave) - } - #[doc = "Four-pin push-pull mode (inverted outputs)"] - #[inline(always)] - pub fn push_pull_4_pin_w_lpi2c_slave(self) -> &'a mut crate::W { - self.variant(Pincfg::PushPull4PinWLpi2cSlave) - } -} -impl R { - #[doc = "Bits 0:2 - Prescaler"] - #[inline(always)] - pub fn prescale(&self) -> PrescaleR { - PrescaleR::new((self.bits & 7) as u8) - } - #[doc = "Bit 8 - Automatic Stop Generation"] - #[inline(always)] - pub fn autostop(&self) -> AutostopR { - AutostopR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Ignore NACK"] - #[inline(always)] - pub fn ignack(&self) -> IgnackR { - IgnackR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Timeout Configuration"] - #[inline(always)] - pub fn timecfg(&self) -> TimecfgR { - TimecfgR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Stop Configuration"] - #[inline(always)] - pub fn stopcfg(&self) -> StopcfgR { - StopcfgR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Start Configuration"] - #[inline(always)] - pub fn startcfg(&self) -> StartcfgR { - StartcfgR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bits 16:18 - Match Configuration"] - #[inline(always)] - pub fn matcfg(&self) -> MatcfgR { - MatcfgR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:26 - Pin Configuration"] - #[inline(always)] - pub fn pincfg(&self) -> PincfgR { - PincfgR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Prescaler"] - #[inline(always)] - pub fn prescale(&mut self) -> PrescaleW { - PrescaleW::new(self, 0) - } - #[doc = "Bit 8 - Automatic Stop Generation"] - #[inline(always)] - pub fn autostop(&mut self) -> AutostopW { - AutostopW::new(self, 8) - } - #[doc = "Bit 9 - Ignore NACK"] - #[inline(always)] - pub fn ignack(&mut self) -> IgnackW { - IgnackW::new(self, 9) - } - #[doc = "Bit 10 - Timeout Configuration"] - #[inline(always)] - pub fn timecfg(&mut self) -> TimecfgW { - TimecfgW::new(self, 10) - } - #[doc = "Bit 11 - Stop Configuration"] - #[inline(always)] - pub fn stopcfg(&mut self) -> StopcfgW { - StopcfgW::new(self, 11) - } - #[doc = "Bit 12 - Start Configuration"] - #[inline(always)] - pub fn startcfg(&mut self) -> StartcfgW { - StartcfgW::new(self, 12) - } - #[doc = "Bits 16:18 - Match Configuration"] - #[inline(always)] - pub fn matcfg(&mut self) -> MatcfgW { - MatcfgW::new(self, 16) - } - #[doc = "Bits 24:26 - Pin Configuration"] - #[inline(always)] - pub fn pincfg(&mut self) -> PincfgW { - PincfgW::new(self, 24) - } -} -#[doc = "Controller Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mcfgr1Spec; -impl crate::RegisterSpec for Mcfgr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mcfgr1::R`](R) reader structure"] -impl crate::Readable for Mcfgr1Spec {} -#[doc = "`write(|w| ..)` method takes [`mcfgr1::W`](W) writer structure"] -impl crate::Writable for Mcfgr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCFGR1 to value 0"] -impl crate::Resettable for Mcfgr1Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr2.rs b/mcxa276-pac/src/lpi2c0/mcfgr2.rs deleted file mode 100644 index 7b76a8991..000000000 --- a/mcxa276-pac/src/lpi2c0/mcfgr2.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MCFGR2` reader"] -pub type R = crate::R; -#[doc = "Register `MCFGR2` writer"] -pub type W = crate::W; -#[doc = "Field `BUSIDLE` reader - Bus Idle Timeout"] -pub type BusidleR = crate::FieldReader; -#[doc = "Field `BUSIDLE` writer - Bus Idle Timeout"] -pub type BusidleW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `FILTSCL` reader - Glitch Filter SCL"] -pub type FiltsclR = crate::FieldReader; -#[doc = "Field `FILTSCL` writer - Glitch Filter SCL"] -pub type FiltsclW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `FILTSDA` reader - Glitch Filter SDA"] -pub type FiltsdaR = crate::FieldReader; -#[doc = "Field `FILTSDA` writer - Glitch Filter SDA"] -pub type FiltsdaW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:11 - Bus Idle Timeout"] - #[inline(always)] - pub fn busidle(&self) -> BusidleR { - BusidleR::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:19 - Glitch Filter SCL"] - #[inline(always)] - pub fn filtscl(&self) -> FiltsclR { - FiltsclR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:27 - Glitch Filter SDA"] - #[inline(always)] - pub fn filtsda(&self) -> FiltsdaR { - FiltsdaR::new(((self.bits >> 24) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:11 - Bus Idle Timeout"] - #[inline(always)] - pub fn busidle(&mut self) -> BusidleW { - BusidleW::new(self, 0) - } - #[doc = "Bits 16:19 - Glitch Filter SCL"] - #[inline(always)] - pub fn filtscl(&mut self) -> FiltsclW { - FiltsclW::new(self, 16) - } - #[doc = "Bits 24:27 - Glitch Filter SDA"] - #[inline(always)] - pub fn filtsda(&mut self) -> FiltsdaW { - FiltsdaW::new(self, 24) - } -} -#[doc = "Controller Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mcfgr2Spec; -impl crate::RegisterSpec for Mcfgr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mcfgr2::R`](R) reader structure"] -impl crate::Readable for Mcfgr2Spec {} -#[doc = "`write(|w| ..)` method takes [`mcfgr2::W`](W) writer structure"] -impl crate::Writable for Mcfgr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCFGR2 to value 0"] -impl crate::Resettable for Mcfgr2Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcfgr3.rs b/mcxa276-pac/src/lpi2c0/mcfgr3.rs deleted file mode 100644 index 909e2a0a5..000000000 --- a/mcxa276-pac/src/lpi2c0/mcfgr3.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `MCFGR3` reader"] -pub type R = crate::R; -#[doc = "Register `MCFGR3` writer"] -pub type W = crate::W; -#[doc = "Field `PINLOW` reader - Pin Low Timeout"] -pub type PinlowR = crate::FieldReader; -#[doc = "Field `PINLOW` writer - Pin Low Timeout"] -pub type PinlowW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -impl R { - #[doc = "Bits 8:19 - Pin Low Timeout"] - #[inline(always)] - pub fn pinlow(&self) -> PinlowR { - PinlowR::new(((self.bits >> 8) & 0x0fff) as u16) - } -} -impl W { - #[doc = "Bits 8:19 - Pin Low Timeout"] - #[inline(always)] - pub fn pinlow(&mut self) -> PinlowW { - PinlowW::new(self, 8) - } -} -#[doc = "Controller Configuration 3\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mcfgr3Spec; -impl crate::RegisterSpec for Mcfgr3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mcfgr3::R`](R) reader structure"] -impl crate::Readable for Mcfgr3Spec {} -#[doc = "`write(|w| ..)` method takes [`mcfgr3::W`](W) writer structure"] -impl crate::Writable for Mcfgr3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCFGR3 to value 0"] -impl crate::Resettable for Mcfgr3Spec {} diff --git a/mcxa276-pac/src/lpi2c0/mcr.rs b/mcxa276-pac/src/lpi2c0/mcr.rs deleted file mode 100644 index 19f2a4eab..000000000 --- a/mcxa276-pac/src/lpi2c0/mcr.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `MCR` reader"] -pub type R = crate::R; -#[doc = "Register `MCR` writer"] -pub type W = crate::W; -#[doc = "Controller Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Men { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Men) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MEN` reader - Controller Enable"] -pub type MenR = crate::BitReader; -impl MenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Men { - match self.bits { - false => Men::Disabled, - true => Men::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Men::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Men::Enabled - } -} -#[doc = "Field `MEN` writer - Controller Enable"] -pub type MenW<'a, REG> = crate::BitWriter<'a, REG, Men>; -impl<'a, REG> MenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Men::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Men::Enabled) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rst { - #[doc = "0: No effect"] - NotReset = 0, - #[doc = "1: Reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST` reader - Software Reset"] -pub type RstR = crate::BitReader; -impl RstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rst { - match self.bits { - false => Rst::NotReset, - true => Rst::Reset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_not_reset(&self) -> bool { - *self == Rst::NotReset - } - #[doc = "Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Rst::Reset - } -} -#[doc = "Field `RST` writer - Software Reset"] -pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; -impl<'a, REG> RstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn not_reset(self) -> &'a mut crate::W { - self.variant(Rst::NotReset) - } - #[doc = "Reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Rst::Reset) - } -} -#[doc = "Doze Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dozen { - #[doc = "0: Enable"] - Enabled = 0, - #[doc = "1: Disable"] - Disabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dozen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DOZEN` reader - Doze Mode Enable"] -pub type DozenR = crate::BitReader; -impl DozenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dozen { - match self.bits { - false => Dozen::Enabled, - true => Dozen::Disabled, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dozen::Enabled - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dozen::Disabled - } -} -#[doc = "Field `DOZEN` writer - Doze Mode Enable"] -pub type DozenW<'a, REG> = crate::BitWriter<'a, REG, Dozen>; -impl<'a, REG> DozenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dozen::Enabled) - } - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dozen::Disabled) - } -} -#[doc = "Debug Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dbgen { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dbgen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBGEN` reader - Debug Enable"] -pub type DbgenR = crate::BitReader; -impl DbgenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dbgen { - match self.bits { - false => Dbgen::Disabled, - true => Dbgen::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dbgen::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dbgen::Enabled - } -} -#[doc = "Field `DBGEN` writer - Debug Enable"] -pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG, Dbgen>; -impl<'a, REG> DbgenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dbgen::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dbgen::Enabled) - } -} -#[doc = "Reset Transmit FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rtf { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Reset transmit FIFO"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rtf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RTF` reader - Reset Transmit FIFO"] -pub type RtfR = crate::BitReader; -impl RtfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rtf { - match self.bits { - false => Rtf::NoEffect, - true => Rtf::Reset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rtf::NoEffect - } - #[doc = "Reset transmit FIFO"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Rtf::Reset - } -} -#[doc = "Field `RTF` writer - Reset Transmit FIFO"] -pub type RtfW<'a, REG> = crate::BitWriter<'a, REG, Rtf>; -impl<'a, REG> RtfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rtf::NoEffect) - } - #[doc = "Reset transmit FIFO"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Rtf::Reset) - } -} -#[doc = "Reset Receive FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rrf { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Reset receive FIFO"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rrf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RRF` reader - Reset Receive FIFO"] -pub type RrfR = crate::BitReader; -impl RrfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rrf { - match self.bits { - false => Rrf::NoEffect, - true => Rrf::Reset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rrf::NoEffect - } - #[doc = "Reset receive FIFO"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Rrf::Reset - } -} -#[doc = "Field `RRF` writer - Reset Receive FIFO"] -pub type RrfW<'a, REG> = crate::BitWriter<'a, REG, Rrf>; -impl<'a, REG> RrfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rrf::NoEffect) - } - #[doc = "Reset receive FIFO"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Rrf::Reset) - } -} -impl R { - #[doc = "Bit 0 - Controller Enable"] - #[inline(always)] - pub fn men(&self) -> MenR { - MenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&self) -> RstR { - RstR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Doze Mode Enable"] - #[inline(always)] - pub fn dozen(&self) -> DozenR { - DozenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&self) -> DbgenR { - DbgenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Reset Transmit FIFO"] - #[inline(always)] - pub fn rtf(&self) -> RtfR { - RtfR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Reset Receive FIFO"] - #[inline(always)] - pub fn rrf(&self) -> RrfR { - RrfR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Controller Enable"] - #[inline(always)] - pub fn men(&mut self) -> MenW { - MenW::new(self, 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&mut self) -> RstW { - RstW::new(self, 1) - } - #[doc = "Bit 2 - Doze Mode Enable"] - #[inline(always)] - pub fn dozen(&mut self) -> DozenW { - DozenW::new(self, 2) - } - #[doc = "Bit 3 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&mut self) -> DbgenW { - DbgenW::new(self, 3) - } - #[doc = "Bit 8 - Reset Transmit FIFO"] - #[inline(always)] - pub fn rtf(&mut self) -> RtfW { - RtfW::new(self, 8) - } - #[doc = "Bit 9 - Reset Receive FIFO"] - #[inline(always)] - pub fn rrf(&mut self) -> RrfW { - RrfW::new(self, 9) - } -} -#[doc = "Controller Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct McrSpec; -impl crate::RegisterSpec for McrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] -impl crate::Readable for McrSpec {} -#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] -impl crate::Writable for McrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MCR to value 0"] -impl crate::Resettable for McrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mder.rs b/mcxa276-pac/src/lpi2c0/mder.rs deleted file mode 100644 index 84debc732..000000000 --- a/mcxa276-pac/src/lpi2c0/mder.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `MDER` reader"] -pub type R = crate::R; -#[doc = "Register `MDER` writer"] -pub type W = crate::W; -#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdde { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"] -pub type TddeR = crate::BitReader; -impl TddeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdde { - match self.bits { - false => Tdde::Disabled, - true => Tdde::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tdde::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tdde::Enabled - } -} -#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"] -pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>; -impl<'a, REG> TddeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tdde::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tdde::Enabled) - } -} -#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdde { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDDE` reader - Receive Data DMA Enable"] -pub type RddeR = crate::BitReader; -impl RddeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdde { - match self.bits { - false => Rdde::Disabled, - true => Rdde::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdde::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdde::Enabled - } -} -#[doc = "Field `RDDE` writer - Receive Data DMA Enable"] -pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>; -impl<'a, REG> RddeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rdde::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rdde::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Transmit Data DMA Enable"] - #[inline(always)] - pub fn tdde(&self) -> TddeR { - TddeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data DMA Enable"] - #[inline(always)] - pub fn rdde(&self) -> RddeR { - RddeR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmit Data DMA Enable"] - #[inline(always)] - pub fn tdde(&mut self) -> TddeW { - TddeW::new(self, 0) - } - #[doc = "Bit 1 - Receive Data DMA Enable"] - #[inline(always)] - pub fn rdde(&mut self) -> RddeW { - RddeW::new(self, 1) - } -} -#[doc = "Controller DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mder::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mder::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MderSpec; -impl crate::RegisterSpec for MderSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mder::R`](R) reader structure"] -impl crate::Readable for MderSpec {} -#[doc = "`write(|w| ..)` method takes [`mder::W`](W) writer structure"] -impl crate::Writable for MderSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MDER to value 0"] -impl crate::Resettable for MderSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mdmr.rs b/mcxa276-pac/src/lpi2c0/mdmr.rs deleted file mode 100644 index 84d8fd1d0..000000000 --- a/mcxa276-pac/src/lpi2c0/mdmr.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `MDMR` reader"] -pub type R = crate::R; -#[doc = "Register `MDMR` writer"] -pub type W = crate::W; -#[doc = "Field `MATCH0` reader - Match 0 Value"] -pub type Match0R = crate::FieldReader; -#[doc = "Field `MATCH0` writer - Match 0 Value"] -pub type Match0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `MATCH1` reader - Match 1 Value"] -pub type Match1R = crate::FieldReader; -#[doc = "Field `MATCH1` writer - Match 1 Value"] -pub type Match1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Match 0 Value"] - #[inline(always)] - pub fn match0(&self) -> Match0R { - Match0R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 16:23 - Match 1 Value"] - #[inline(always)] - pub fn match1(&self) -> Match1R { - Match1R::new(((self.bits >> 16) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Match 0 Value"] - #[inline(always)] - pub fn match0(&mut self) -> Match0W { - Match0W::new(self, 0) - } - #[doc = "Bits 16:23 - Match 1 Value"] - #[inline(always)] - pub fn match1(&mut self) -> Match1W { - Match1W::new(self, 16) - } -} -#[doc = "Controller Data Match\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MdmrSpec; -impl crate::RegisterSpec for MdmrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mdmr::R`](R) reader structure"] -impl crate::Readable for MdmrSpec {} -#[doc = "`write(|w| ..)` method takes [`mdmr::W`](W) writer structure"] -impl crate::Writable for MdmrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MDMR to value 0"] -impl crate::Resettable for MdmrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mfcr.rs b/mcxa276-pac/src/lpi2c0/mfcr.rs deleted file mode 100644 index 8e7c44de7..000000000 --- a/mcxa276-pac/src/lpi2c0/mfcr.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `MFCR` reader"] -pub type R = crate::R; -#[doc = "Register `MFCR` writer"] -pub type W = crate::W; -#[doc = "Field `TXWATER` reader - Transmit FIFO Watermark"] -pub type TxwaterR = crate::FieldReader; -#[doc = "Field `TXWATER` writer - Transmit FIFO Watermark"] -pub type TxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `RXWATER` reader - Receive FIFO Watermark"] -pub type RxwaterR = crate::FieldReader; -#[doc = "Field `RXWATER` writer - Receive FIFO Watermark"] -pub type RxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Transmit FIFO Watermark"] - #[inline(always)] - pub fn txwater(&self) -> TxwaterR { - TxwaterR::new((self.bits & 3) as u8) - } - #[doc = "Bits 16:17 - Receive FIFO Watermark"] - #[inline(always)] - pub fn rxwater(&self) -> RxwaterR { - RxwaterR::new(((self.bits >> 16) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Transmit FIFO Watermark"] - #[inline(always)] - pub fn txwater(&mut self) -> TxwaterW { - TxwaterW::new(self, 0) - } - #[doc = "Bits 16:17 - Receive FIFO Watermark"] - #[inline(always)] - pub fn rxwater(&mut self) -> RxwaterW { - RxwaterW::new(self, 16) - } -} -#[doc = "Controller FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mfcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mfcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MfcrSpec; -impl crate::RegisterSpec for MfcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mfcr::R`](R) reader structure"] -impl crate::Readable for MfcrSpec {} -#[doc = "`write(|w| ..)` method takes [`mfcr::W`](W) writer structure"] -impl crate::Writable for MfcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MFCR to value 0"] -impl crate::Resettable for MfcrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mfsr.rs b/mcxa276-pac/src/lpi2c0/mfsr.rs deleted file mode 100644 index 43ef0da61..000000000 --- a/mcxa276-pac/src/lpi2c0/mfsr.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `MFSR` reader"] -pub type R = crate::R; -#[doc = "Field `TXCOUNT` reader - Transmit FIFO Count"] -pub type TxcountR = crate::FieldReader; -#[doc = "Field `RXCOUNT` reader - Receive FIFO Count"] -pub type RxcountR = crate::FieldReader; -impl R { - #[doc = "Bits 0:2 - Transmit FIFO Count"] - #[inline(always)] - pub fn txcount(&self) -> TxcountR { - TxcountR::new((self.bits & 7) as u8) - } - #[doc = "Bits 16:18 - Receive FIFO Count"] - #[inline(always)] - pub fn rxcount(&self) -> RxcountR { - RxcountR::new(((self.bits >> 16) & 7) as u8) - } -} -#[doc = "Controller FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`mfsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MfsrSpec; -impl crate::RegisterSpec for MfsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mfsr::R`](R) reader structure"] -impl crate::Readable for MfsrSpec {} -#[doc = "`reset()` method sets MFSR to value 0"] -impl crate::Resettable for MfsrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mier.rs b/mcxa276-pac/src/lpi2c0/mier.rs deleted file mode 100644 index d2296722b..000000000 --- a/mcxa276-pac/src/lpi2c0/mier.rs +++ /dev/null @@ -1,651 +0,0 @@ -#[doc = "Register `MIER` reader"] -pub type R = crate::R; -#[doc = "Register `MIER` writer"] -pub type W = crate::W; -#[doc = "Transmit Data Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDIE` reader - Transmit Data Interrupt Enable"] -pub type TdieR = crate::BitReader; -impl TdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdie { - match self.bits { - false => Tdie::Disabled, - true => Tdie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tdie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tdie::Enabled - } -} -#[doc = "Field `TDIE` writer - Transmit Data Interrupt Enable"] -pub type TdieW<'a, REG> = crate::BitWriter<'a, REG, Tdie>; -impl<'a, REG> TdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tdie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tdie::Enabled) - } -} -#[doc = "Receive Data Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDIE` reader - Receive Data Interrupt Enable"] -pub type RdieR = crate::BitReader; -impl RdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdie { - match self.bits { - false => Rdie::Disabled, - true => Rdie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdie::Enabled - } -} -#[doc = "Field `RDIE` writer - Receive Data Interrupt Enable"] -pub type RdieW<'a, REG> = crate::BitWriter<'a, REG, Rdie>; -impl<'a, REG> RdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rdie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rdie::Enabled) - } -} -#[doc = "End Packet Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Epie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Epie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EPIE` reader - End Packet Interrupt Enable"] -pub type EpieR = crate::BitReader; -impl EpieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Epie { - match self.bits { - false => Epie::Disabled, - true => Epie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Epie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Epie::Enabled - } -} -#[doc = "Field `EPIE` writer - End Packet Interrupt Enable"] -pub type EpieW<'a, REG> = crate::BitWriter<'a, REG, Epie>; -impl<'a, REG> EpieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Epie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Epie::Enabled) - } -} -#[doc = "Stop Detect Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sdie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SDIE` reader - Stop Detect Interrupt Enable"] -pub type SdieR = crate::BitReader; -impl SdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sdie { - match self.bits { - false => Sdie::Disabled, - true => Sdie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sdie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sdie::Enabled - } -} -#[doc = "Field `SDIE` writer - Stop Detect Interrupt Enable"] -pub type SdieW<'a, REG> = crate::BitWriter<'a, REG, Sdie>; -impl<'a, REG> SdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sdie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sdie::Enabled) - } -} -#[doc = "NACK Detect Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ndie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ndie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NDIE` reader - NACK Detect Interrupt Enable"] -pub type NdieR = crate::BitReader; -impl NdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ndie { - match self.bits { - false => Ndie::Disabled, - true => Ndie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ndie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ndie::Enabled - } -} -#[doc = "Field `NDIE` writer - NACK Detect Interrupt Enable"] -pub type NdieW<'a, REG> = crate::BitWriter<'a, REG, Ndie>; -impl<'a, REG> NdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ndie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ndie::Enabled) - } -} -#[doc = "Arbitration Lost Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Alie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Alie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ALIE` reader - Arbitration Lost Interrupt Enable"] -pub type AlieR = crate::BitReader; -impl AlieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Alie { - match self.bits { - false => Alie::Disabled, - true => Alie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Alie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Alie::Enabled - } -} -#[doc = "Field `ALIE` writer - Arbitration Lost Interrupt Enable"] -pub type AlieW<'a, REG> = crate::BitWriter<'a, REG, Alie>; -impl<'a, REG> AlieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Alie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Alie::Enabled) - } -} -#[doc = "FIFO Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Feie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Feie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FEIE` reader - FIFO Error Interrupt Enable"] -pub type FeieR = crate::BitReader; -impl FeieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Feie { - match self.bits { - false => Feie::Disabled, - true => Feie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Feie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Feie::Enabled - } -} -#[doc = "Field `FEIE` writer - FIFO Error Interrupt Enable"] -pub type FeieW<'a, REG> = crate::BitWriter<'a, REG, Feie>; -impl<'a, REG> FeieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Feie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Feie::Enabled) - } -} -#[doc = "Pin Low Timeout Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pltie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pltie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PLTIE` reader - Pin Low Timeout Interrupt Enable"] -pub type PltieR = crate::BitReader; -impl PltieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pltie { - match self.bits { - false => Pltie::Disabled, - true => Pltie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pltie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pltie::Enabled - } -} -#[doc = "Field `PLTIE` writer - Pin Low Timeout Interrupt Enable"] -pub type PltieW<'a, REG> = crate::BitWriter<'a, REG, Pltie>; -impl<'a, REG> PltieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pltie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pltie::Enabled) - } -} -#[doc = "Data Match Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMIE` reader - Data Match Interrupt Enable"] -pub type DmieR = crate::BitReader; -impl DmieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmie { - match self.bits { - false => Dmie::Disabled, - true => Dmie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dmie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dmie::Enabled - } -} -#[doc = "Field `DMIE` writer - Data Match Interrupt Enable"] -pub type DmieW<'a, REG> = crate::BitWriter<'a, REG, Dmie>; -impl<'a, REG> DmieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dmie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dmie::Enabled) - } -} -#[doc = "Start Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STIE` reader - Start Interrupt Enable"] -pub type StieR = crate::BitReader; -impl StieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stie { - match self.bits { - false => Stie::Disabled, - true => Stie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Stie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Stie::Enabled - } -} -#[doc = "Field `STIE` writer - Start Interrupt Enable"] -pub type StieW<'a, REG> = crate::BitWriter<'a, REG, Stie>; -impl<'a, REG> StieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Stie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Stie::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Transmit Data Interrupt Enable"] - #[inline(always)] - pub fn tdie(&self) -> TdieR { - TdieR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data Interrupt Enable"] - #[inline(always)] - pub fn rdie(&self) -> RdieR { - RdieR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - End Packet Interrupt Enable"] - #[inline(always)] - pub fn epie(&self) -> EpieR { - EpieR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Stop Detect Interrupt Enable"] - #[inline(always)] - pub fn sdie(&self) -> SdieR { - SdieR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - NACK Detect Interrupt Enable"] - #[inline(always)] - pub fn ndie(&self) -> NdieR { - NdieR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Arbitration Lost Interrupt Enable"] - #[inline(always)] - pub fn alie(&self) -> AlieR { - AlieR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - FIFO Error Interrupt Enable"] - #[inline(always)] - pub fn feie(&self) -> FeieR { - FeieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Pin Low Timeout Interrupt Enable"] - #[inline(always)] - pub fn pltie(&self) -> PltieR { - PltieR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Data Match Interrupt Enable"] - #[inline(always)] - pub fn dmie(&self) -> DmieR { - DmieR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Start Interrupt Enable"] - #[inline(always)] - pub fn stie(&self) -> StieR { - StieR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmit Data Interrupt Enable"] - #[inline(always)] - pub fn tdie(&mut self) -> TdieW { - TdieW::new(self, 0) - } - #[doc = "Bit 1 - Receive Data Interrupt Enable"] - #[inline(always)] - pub fn rdie(&mut self) -> RdieW { - RdieW::new(self, 1) - } - #[doc = "Bit 8 - End Packet Interrupt Enable"] - #[inline(always)] - pub fn epie(&mut self) -> EpieW { - EpieW::new(self, 8) - } - #[doc = "Bit 9 - Stop Detect Interrupt Enable"] - #[inline(always)] - pub fn sdie(&mut self) -> SdieW { - SdieW::new(self, 9) - } - #[doc = "Bit 10 - NACK Detect Interrupt Enable"] - #[inline(always)] - pub fn ndie(&mut self) -> NdieW { - NdieW::new(self, 10) - } - #[doc = "Bit 11 - Arbitration Lost Interrupt Enable"] - #[inline(always)] - pub fn alie(&mut self) -> AlieW { - AlieW::new(self, 11) - } - #[doc = "Bit 12 - FIFO Error Interrupt Enable"] - #[inline(always)] - pub fn feie(&mut self) -> FeieW { - FeieW::new(self, 12) - } - #[doc = "Bit 13 - Pin Low Timeout Interrupt Enable"] - #[inline(always)] - pub fn pltie(&mut self) -> PltieW { - PltieW::new(self, 13) - } - #[doc = "Bit 14 - Data Match Interrupt Enable"] - #[inline(always)] - pub fn dmie(&mut self) -> DmieW { - DmieW::new(self, 14) - } - #[doc = "Bit 15 - Start Interrupt Enable"] - #[inline(always)] - pub fn stie(&mut self) -> StieW { - StieW::new(self, 15) - } -} -#[doc = "Controller Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`mier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MierSpec; -impl crate::RegisterSpec for MierSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mier::R`](R) reader structure"] -impl crate::Readable for MierSpec {} -#[doc = "`write(|w| ..)` method takes [`mier::W`](W) writer structure"] -impl crate::Writable for MierSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MIER to value 0"] -impl crate::Resettable for MierSpec {} diff --git a/mcxa276-pac/src/lpi2c0/mrdr.rs b/mcxa276-pac/src/lpi2c0/mrdr.rs deleted file mode 100644 index 77317eaa7..000000000 --- a/mcxa276-pac/src/lpi2c0/mrdr.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MRDR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Receive Data"] -pub type DataR = crate::FieldReader; -#[doc = "Receive Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempty { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPTY` reader - Receive Empty"] -pub type RxemptyR = crate::BitReader; -impl RxemptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempty { - match self.bits { - false => Rxempty::NotEmpty, - true => Rxempty::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempty::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempty::Empty - } -} -impl R { - #[doc = "Bits 0:7 - Receive Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 14 - Receive Empty"] - #[inline(always)] - pub fn rxempty(&self) -> RxemptyR { - RxemptyR::new(((self.bits >> 14) & 1) != 0) - } -} -#[doc = "Controller Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrdrSpec; -impl crate::RegisterSpec for MrdrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrdr::R`](R) reader structure"] -impl crate::Readable for MrdrSpec {} -#[doc = "`reset()` method sets MRDR to value 0x4000"] -impl crate::Resettable for MrdrSpec { - const RESET_VALUE: u32 = 0x4000; -} diff --git a/mcxa276-pac/src/lpi2c0/mrdror.rs b/mcxa276-pac/src/lpi2c0/mrdror.rs deleted file mode 100644 index 2b70be11a..000000000 --- a/mcxa276-pac/src/lpi2c0/mrdror.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `MRDROR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Receive Data"] -pub type DataR = crate::FieldReader; -#[doc = "RX Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempty { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPTY` reader - RX Empty"] -pub type RxemptyR = crate::BitReader; -impl RxemptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempty { - match self.bits { - false => Rxempty::NotEmpty, - true => Rxempty::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempty::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempty::Empty - } -} -impl R { - #[doc = "Bits 0:7 - Receive Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 14 - RX Empty"] - #[inline(always)] - pub fn rxempty(&self) -> RxemptyR { - RxemptyR::new(((self.bits >> 14) & 1) != 0) - } -} -#[doc = "Controller Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`mrdror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrdrorSpec; -impl crate::RegisterSpec for MrdrorSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrdror::R`](R) reader structure"] -impl crate::Readable for MrdrorSpec {} -#[doc = "`reset()` method sets MRDROR to value 0x4000"] -impl crate::Resettable for MrdrorSpec { - const RESET_VALUE: u32 = 0x4000; -} diff --git a/mcxa276-pac/src/lpi2c0/msr.rs b/mcxa276-pac/src/lpi2c0/msr.rs deleted file mode 100644 index fef810d46..000000000 --- a/mcxa276-pac/src/lpi2c0/msr.rs +++ /dev/null @@ -1,692 +0,0 @@ -#[doc = "Register `MSR` reader"] -pub type R = crate::R; -#[doc = "Register `MSR` writer"] -pub type W = crate::W; -#[doc = "Transmit Data Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdf { - #[doc = "0: Transmit data not requested"] - Disabled = 0, - #[doc = "1: Transmit data requested"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDF` reader - Transmit Data Flag"] -pub type TdfR = crate::BitReader; -impl TdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdf { - match self.bits { - false => Tdf::Disabled, - true => Tdf::Enabled, - } - } - #[doc = "Transmit data not requested"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tdf::Disabled - } - #[doc = "Transmit data requested"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tdf::Enabled - } -} -#[doc = "Receive Data Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdf { - #[doc = "0: Receive data not ready"] - Disabled = 0, - #[doc = "1: Receive data ready"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDF` reader - Receive Data Flag"] -pub type RdfR = crate::BitReader; -impl RdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdf { - match self.bits { - false => Rdf::Disabled, - true => Rdf::Enabled, - } - } - #[doc = "Receive data not ready"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdf::Disabled - } - #[doc = "Receive data ready"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdf::Enabled - } -} -#[doc = "End Packet Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Epf { - #[doc = "0: No Stop or repeated Start generated"] - IntNo = 0, - #[doc = "1: Stop or repeated Start generated"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Epf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EPF` reader - End Packet Flag"] -pub type EpfR = crate::BitReader; -impl EpfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Epf { - match self.bits { - false => Epf::IntNo, - true => Epf::IntYes, - } - } - #[doc = "No Stop or repeated Start generated"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Epf::IntNo - } - #[doc = "Stop or repeated Start generated"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Epf::IntYes - } -} -#[doc = "Field `EPF` writer - End Packet Flag"] -pub type EpfW<'a, REG> = crate::BitWriter1C<'a, REG, Epf>; -impl<'a, REG> EpfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No Stop or repeated Start generated"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Epf::IntNo) - } - #[doc = "Stop or repeated Start generated"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Epf::IntYes) - } -} -#[doc = "Stop Detect Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sdf { - #[doc = "0: No Stop condition generated"] - IntNo = 0, - #[doc = "1: Stop condition generated"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SDF` reader - Stop Detect Flag"] -pub type SdfR = crate::BitReader; -impl SdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sdf { - match self.bits { - false => Sdf::IntNo, - true => Sdf::IntYes, - } - } - #[doc = "No Stop condition generated"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Sdf::IntNo - } - #[doc = "Stop condition generated"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Sdf::IntYes - } -} -#[doc = "Field `SDF` writer - Stop Detect Flag"] -pub type SdfW<'a, REG> = crate::BitWriter1C<'a, REG, Sdf>; -impl<'a, REG> SdfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No Stop condition generated"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Sdf::IntNo) - } - #[doc = "Stop condition generated"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Sdf::IntYes) - } -} -#[doc = "NACK Detect Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ndf { - #[doc = "0: No unexpected NACK detected"] - IntNo = 0, - #[doc = "1: Unexpected NACK detected"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ndf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NDF` reader - NACK Detect Flag"] -pub type NdfR = crate::BitReader; -impl NdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ndf { - match self.bits { - false => Ndf::IntNo, - true => Ndf::IntYes, - } - } - #[doc = "No unexpected NACK detected"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Ndf::IntNo - } - #[doc = "Unexpected NACK detected"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Ndf::IntYes - } -} -#[doc = "Field `NDF` writer - NACK Detect Flag"] -pub type NdfW<'a, REG> = crate::BitWriter1C<'a, REG, Ndf>; -impl<'a, REG> NdfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No unexpected NACK detected"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Ndf::IntNo) - } - #[doc = "Unexpected NACK detected"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Ndf::IntYes) - } -} -#[doc = "Arbitration Lost Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Alf { - #[doc = "0: Controller did not lose arbitration"] - IntNo = 0, - #[doc = "1: Controller lost arbitration"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Alf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ALF` reader - Arbitration Lost Flag"] -pub type AlfR = crate::BitReader; -impl AlfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Alf { - match self.bits { - false => Alf::IntNo, - true => Alf::IntYes, - } - } - #[doc = "Controller did not lose arbitration"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Alf::IntNo - } - #[doc = "Controller lost arbitration"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Alf::IntYes - } -} -#[doc = "Field `ALF` writer - Arbitration Lost Flag"] -pub type AlfW<'a, REG> = crate::BitWriter1C<'a, REG, Alf>; -impl<'a, REG> AlfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Controller did not lose arbitration"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Alf::IntNo) - } - #[doc = "Controller lost arbitration"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Alf::IntYes) - } -} -#[doc = "FIFO Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fef { - #[doc = "0: No FIFO error"] - IntNo = 0, - #[doc = "1: FIFO error"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fef) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FEF` reader - FIFO Error Flag"] -pub type FefR = crate::BitReader; -impl FefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fef { - match self.bits { - false => Fef::IntNo, - true => Fef::IntYes, - } - } - #[doc = "No FIFO error"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Fef::IntNo - } - #[doc = "FIFO error"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Fef::IntYes - } -} -#[doc = "Field `FEF` writer - FIFO Error Flag"] -pub type FefW<'a, REG> = crate::BitWriter1C<'a, REG, Fef>; -impl<'a, REG> FefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No FIFO error"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Fef::IntNo) - } - #[doc = "FIFO error"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Fef::IntYes) - } -} -#[doc = "Pin Low Timeout Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pltf { - #[doc = "0: Pin low timeout did not occur"] - IntNo = 0, - #[doc = "1: Pin low timeout occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pltf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PLTF` reader - Pin Low Timeout Flag"] -pub type PltfR = crate::BitReader; -impl PltfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pltf { - match self.bits { - false => Pltf::IntNo, - true => Pltf::IntYes, - } - } - #[doc = "Pin low timeout did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Pltf::IntNo - } - #[doc = "Pin low timeout occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Pltf::IntYes - } -} -#[doc = "Field `PLTF` writer - Pin Low Timeout Flag"] -pub type PltfW<'a, REG> = crate::BitWriter1C<'a, REG, Pltf>; -impl<'a, REG> PltfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin low timeout did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Pltf::IntNo) - } - #[doc = "Pin low timeout occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Pltf::IntYes) - } -} -#[doc = "Data Match Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmf { - #[doc = "0: Matching data not received"] - IntNo = 0, - #[doc = "1: Matching data received"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMF` reader - Data Match Flag"] -pub type DmfR = crate::BitReader; -impl DmfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmf { - match self.bits { - false => Dmf::IntNo, - true => Dmf::IntYes, - } - } - #[doc = "Matching data not received"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Dmf::IntNo - } - #[doc = "Matching data received"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Dmf::IntYes - } -} -#[doc = "Field `DMF` writer - Data Match Flag"] -pub type DmfW<'a, REG> = crate::BitWriter1C<'a, REG, Dmf>; -impl<'a, REG> DmfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Matching data not received"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Dmf::IntNo) - } - #[doc = "Matching data received"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Dmf::IntYes) - } -} -#[doc = "Start Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stf { - #[doc = "0: Start condition not detected"] - IntNo = 0, - #[doc = "1: Start condition detected"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STF` reader - Start Flag"] -pub type StfR = crate::BitReader; -impl StfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stf { - match self.bits { - false => Stf::IntNo, - true => Stf::IntYes, - } - } - #[doc = "Start condition not detected"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Stf::IntNo - } - #[doc = "Start condition detected"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Stf::IntYes - } -} -#[doc = "Field `STF` writer - Start Flag"] -pub type StfW<'a, REG> = crate::BitWriter1C<'a, REG, Stf>; -impl<'a, REG> StfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Start condition not detected"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Stf::IntNo) - } - #[doc = "Start condition detected"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Stf::IntYes) - } -} -#[doc = "Controller Busy Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mbf { - #[doc = "0: Idle"] - Idle = 0, - #[doc = "1: Busy"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MBF` reader - Controller Busy Flag"] -pub type MbfR = crate::BitReader; -impl MbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbf { - match self.bits { - false => Mbf::Idle, - true => Mbf::Busy, - } - } - #[doc = "Idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Mbf::Idle - } - #[doc = "Busy"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Mbf::Busy - } -} -#[doc = "Bus Busy Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bbf { - #[doc = "0: Idle"] - Idle = 0, - #[doc = "1: Busy"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BBF` reader - Bus Busy Flag"] -pub type BbfR = crate::BitReader; -impl BbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bbf { - match self.bits { - false => Bbf::Idle, - true => Bbf::Busy, - } - } - #[doc = "Idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Bbf::Idle - } - #[doc = "Busy"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Bbf::Busy - } -} -impl R { - #[doc = "Bit 0 - Transmit Data Flag"] - #[inline(always)] - pub fn tdf(&self) -> TdfR { - TdfR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data Flag"] - #[inline(always)] - pub fn rdf(&self) -> RdfR { - RdfR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - End Packet Flag"] - #[inline(always)] - pub fn epf(&self) -> EpfR { - EpfR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Stop Detect Flag"] - #[inline(always)] - pub fn sdf(&self) -> SdfR { - SdfR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - NACK Detect Flag"] - #[inline(always)] - pub fn ndf(&self) -> NdfR { - NdfR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Arbitration Lost Flag"] - #[inline(always)] - pub fn alf(&self) -> AlfR { - AlfR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - FIFO Error Flag"] - #[inline(always)] - pub fn fef(&self) -> FefR { - FefR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Pin Low Timeout Flag"] - #[inline(always)] - pub fn pltf(&self) -> PltfR { - PltfR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Data Match Flag"] - #[inline(always)] - pub fn dmf(&self) -> DmfR { - DmfR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Start Flag"] - #[inline(always)] - pub fn stf(&self) -> StfR { - StfR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 24 - Controller Busy Flag"] - #[inline(always)] - pub fn mbf(&self) -> MbfR { - MbfR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Bus Busy Flag"] - #[inline(always)] - pub fn bbf(&self) -> BbfR { - BbfR::new(((self.bits >> 25) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - End Packet Flag"] - #[inline(always)] - pub fn epf(&mut self) -> EpfW { - EpfW::new(self, 8) - } - #[doc = "Bit 9 - Stop Detect Flag"] - #[inline(always)] - pub fn sdf(&mut self) -> SdfW { - SdfW::new(self, 9) - } - #[doc = "Bit 10 - NACK Detect Flag"] - #[inline(always)] - pub fn ndf(&mut self) -> NdfW { - NdfW::new(self, 10) - } - #[doc = "Bit 11 - Arbitration Lost Flag"] - #[inline(always)] - pub fn alf(&mut self) -> AlfW { - AlfW::new(self, 11) - } - #[doc = "Bit 12 - FIFO Error Flag"] - #[inline(always)] - pub fn fef(&mut self) -> FefW { - FefW::new(self, 12) - } - #[doc = "Bit 13 - Pin Low Timeout Flag"] - #[inline(always)] - pub fn pltf(&mut self) -> PltfW { - PltfW::new(self, 13) - } - #[doc = "Bit 14 - Data Match Flag"] - #[inline(always)] - pub fn dmf(&mut self) -> DmfW { - DmfW::new(self, 14) - } - #[doc = "Bit 15 - Start Flag"] - #[inline(always)] - pub fn stf(&mut self) -> StfW { - StfW::new(self, 15) - } -} -#[doc = "Controller Status\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MsrSpec; -impl crate::RegisterSpec for MsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`msr::R`](R) reader structure"] -impl crate::Readable for MsrSpec {} -#[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"] -impl crate::Writable for MsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff00; -} -#[doc = "`reset()` method sets MSR to value 0x01"] -impl crate::Resettable for MsrSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/lpi2c0/mtdr.rs b/mcxa276-pac/src/lpi2c0/mtdr.rs deleted file mode 100644 index 385d0b4cc..000000000 --- a/mcxa276-pac/src/lpi2c0/mtdr.rs +++ /dev/null @@ -1,114 +0,0 @@ -#[doc = "Register `MTDR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Transmit Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Command Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmd { - #[doc = "0: Transmit the value in DATA\\[7:0\\]"] - TransmitData7Through0 = 0, - #[doc = "1: Receive (DATA\\[7:0\\] + 1) bytes"] - ReceiveData7Through0PlusOne = 1, - #[doc = "2: Generate Stop condition on I2C bus"] - GenerateStopCondition = 2, - #[doc = "3: Receive and discard (DATA\\[7:0\\] + 1) bytes"] - ReceiveAndDiscardData7Through0PlusOne = 3, - #[doc = "4: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\]"] - GenerateStartAndTransmitAddressInData7Through0 = 4, - #[doc = "5: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] (this transfer expects a NACK to be returned)"] - GenerateStartAndTransmitAddressInData7Through0ExpectNack = 5, - #[doc = "6: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode"] - GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedMode = 6, - #[doc = "7: Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode (this transfer expects a NACK to be returned)"] - GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedModeExpectNack = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmd) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmd { - type Ux = u8; -} -impl crate::IsEnum for Cmd {} -#[doc = "Field `CMD` writer - Command Data"] -pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 3, Cmd, crate::Safe>; -impl<'a, REG> CmdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Transmit the value in DATA\\[7:0\\]"] - #[inline(always)] - pub fn transmit_data_7_through_0(self) -> &'a mut crate::W { - self.variant(Cmd::TransmitData7Through0) - } - #[doc = "Receive (DATA\\[7:0\\] + 1) bytes"] - #[inline(always)] - pub fn receive_data_7_through_0_plus_one(self) -> &'a mut crate::W { - self.variant(Cmd::ReceiveData7Through0PlusOne) - } - #[doc = "Generate Stop condition on I2C bus"] - #[inline(always)] - pub fn generate_stop_condition(self) -> &'a mut crate::W { - self.variant(Cmd::GenerateStopCondition) - } - #[doc = "Receive and discard (DATA\\[7:0\\] + 1) bytes"] - #[inline(always)] - pub fn receive_and_discard_data_7_through_0_plus_one(self) -> &'a mut crate::W { - self.variant(Cmd::ReceiveAndDiscardData7Through0PlusOne) - } - #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\]"] - #[inline(always)] - pub fn generate_start_and_transmit_address_in_data_7_through_0(self) -> &'a mut crate::W { - self.variant(Cmd::GenerateStartAndTransmitAddressInData7Through0) - } - #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] (this transfer expects a NACK to be returned)"] - #[inline(always)] - pub fn generate_start_and_transmit_address_in_data_7_through_0_expect_nack( - self, - ) -> &'a mut crate::W { - self.variant(Cmd::GenerateStartAndTransmitAddressInData7Through0ExpectNack) - } - #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode"] - #[inline(always)] - pub fn generate_start_and_transmit_address_in_data_7_through_0_using_high_speed_mode( - self, - ) -> &'a mut crate::W { - self.variant(Cmd::GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedMode) - } - #[doc = "Generate (repeated) Start on the I2C bus and transmit the address in DATA\\[7:0\\] using HS mode (this transfer expects a NACK to be returned)"] - #[inline(always)] - pub fn generate_start_and_transmit_address_in_data_7_through_0_using_high_speed_mode_expect_nack( - self, - ) -> &'a mut crate::W { - self.variant( - Cmd::GenerateStartAndTransmitAddressInData7Through0UsingHighSpeedModeExpectNack, - ) - } -} -impl W { - #[doc = "Bits 0:7 - Transmit Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } - #[doc = "Bits 8:10 - Command Data"] - #[inline(always)] - pub fn cmd(&mut self) -> CmdW { - CmdW::new(self, 8) - } -} -#[doc = "Controller Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MtdrSpec; -impl crate::RegisterSpec for MtdrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mtdr::W`](W) writer structure"] -impl crate::Writable for MtdrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MTDR to value 0"] -impl crate::Resettable for MtdrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/param.rs b/mcxa276-pac/src/lpi2c0/param.rs deleted file mode 100644 index ae15d2371..000000000 --- a/mcxa276-pac/src/lpi2c0/param.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "Field `MTXFIFO` reader - Controller Transmit FIFO Size"] -pub type MtxfifoR = crate::FieldReader; -#[doc = "Field `MRXFIFO` reader - Controller Receive FIFO Size"] -pub type MrxfifoR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Controller Transmit FIFO Size"] - #[inline(always)] - pub fn mtxfifo(&self) -> MtxfifoR { - MtxfifoR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 8:11 - Controller Receive FIFO Size"] - #[inline(always)] - pub fn mrxfifo(&self) -> MrxfifoR { - MrxfifoR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x0202"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x0202; -} diff --git a/mcxa276-pac/src/lpi2c0/samr.rs b/mcxa276-pac/src/lpi2c0/samr.rs deleted file mode 100644 index db89ce068..000000000 --- a/mcxa276-pac/src/lpi2c0/samr.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `SAMR` reader"] -pub type R = crate::R; -#[doc = "Register `SAMR` writer"] -pub type W = crate::W; -#[doc = "Field `ADDR0` reader - Address 0 Value"] -pub type Addr0R = crate::FieldReader; -#[doc = "Field `ADDR0` writer - Address 0 Value"] -pub type Addr0W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `ADDR1` reader - Address 1 Value"] -pub type Addr1R = crate::FieldReader; -#[doc = "Field `ADDR1` writer - Address 1 Value"] -pub type Addr1W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 1:10 - Address 0 Value"] - #[inline(always)] - pub fn addr0(&self) -> Addr0R { - Addr0R::new(((self.bits >> 1) & 0x03ff) as u16) - } - #[doc = "Bits 17:26 - Address 1 Value"] - #[inline(always)] - pub fn addr1(&self) -> Addr1R { - Addr1R::new(((self.bits >> 17) & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 1:10 - Address 0 Value"] - #[inline(always)] - pub fn addr0(&mut self) -> Addr0W { - Addr0W::new(self, 1) - } - #[doc = "Bits 17:26 - Address 1 Value"] - #[inline(always)] - pub fn addr1(&mut self) -> Addr1W { - Addr1W::new(self, 17) - } -} -#[doc = "Target Address Match\n\nYou can [`read`](crate::Reg::read) this register and get [`samr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`samr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SamrSpec; -impl crate::RegisterSpec for SamrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`samr::R`](R) reader structure"] -impl crate::Readable for SamrSpec {} -#[doc = "`write(|w| ..)` method takes [`samr::W`](W) writer structure"] -impl crate::Writable for SamrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SAMR to value 0"] -impl crate::Resettable for SamrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/sasr.rs b/mcxa276-pac/src/lpi2c0/sasr.rs deleted file mode 100644 index c0dc0706c..000000000 --- a/mcxa276-pac/src/lpi2c0/sasr.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SASR` reader"] -pub type R = crate::R; -#[doc = "Field `RADDR` reader - Received Address"] -pub type RaddrR = crate::FieldReader; -#[doc = "Address Not Valid\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Anv { - #[doc = "0: Valid"] - Valid = 0, - #[doc = "1: Not valid"] - NotValid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Anv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ANV` reader - Address Not Valid"] -pub type AnvR = crate::BitReader; -impl AnvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Anv { - match self.bits { - false => Anv::Valid, - true => Anv::NotValid, - } - } - #[doc = "Valid"] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Anv::Valid - } - #[doc = "Not valid"] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Anv::NotValid - } -} -impl R { - #[doc = "Bits 0:10 - Received Address"] - #[inline(always)] - pub fn raddr(&self) -> RaddrR { - RaddrR::new((self.bits & 0x07ff) as u16) - } - #[doc = "Bit 14 - Address Not Valid"] - #[inline(always)] - pub fn anv(&self) -> AnvR { - AnvR::new(((self.bits >> 14) & 1) != 0) - } -} -#[doc = "Target Address Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sasr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SasrSpec; -impl crate::RegisterSpec for SasrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sasr::R`](R) reader structure"] -impl crate::Readable for SasrSpec {} -#[doc = "`reset()` method sets SASR to value 0x4000"] -impl crate::Resettable for SasrSpec { - const RESET_VALUE: u32 = 0x4000; -} diff --git a/mcxa276-pac/src/lpi2c0/scfgr0.rs b/mcxa276-pac/src/lpi2c0/scfgr0.rs deleted file mode 100644 index bff09fe01..000000000 --- a/mcxa276-pac/src/lpi2c0/scfgr0.rs +++ /dev/null @@ -1,125 +0,0 @@ -#[doc = "Register `SCFGR0` reader"] -pub type R = crate::R; -#[doc = "Register `SCFGR0` writer"] -pub type W = crate::W; -#[doc = "Read Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdreq { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdreq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDREQ` reader - Read Request"] -pub type RdreqR = crate::BitReader; -impl RdreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdreq { - match self.bits { - false => Rdreq::Disabled, - true => Rdreq::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdreq::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdreq::Enabled - } -} -#[doc = "Field `RDREQ` writer - Read Request"] -pub type RdreqW<'a, REG> = crate::BitWriter<'a, REG, Rdreq>; -impl<'a, REG> RdreqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rdreq::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rdreq::Enabled) - } -} -#[doc = "Read Acknowledge Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdack { - #[doc = "0: Read Request not acknowledged"] - NotAcknowledged = 0, - #[doc = "1: Read Request acknowledged"] - Acknowledged = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDACK` reader - Read Acknowledge Flag"] -pub type RdackR = crate::BitReader; -impl RdackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdack { - match self.bits { - false => Rdack::NotAcknowledged, - true => Rdack::Acknowledged, - } - } - #[doc = "Read Request not acknowledged"] - #[inline(always)] - pub fn is_not_acknowledged(&self) -> bool { - *self == Rdack::NotAcknowledged - } - #[doc = "Read Request acknowledged"] - #[inline(always)] - pub fn is_acknowledged(&self) -> bool { - *self == Rdack::Acknowledged - } -} -impl R { - #[doc = "Bit 0 - Read Request"] - #[inline(always)] - pub fn rdreq(&self) -> RdreqR { - RdreqR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Read Acknowledge Flag"] - #[inline(always)] - pub fn rdack(&self) -> RdackR { - RdackR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Read Request"] - #[inline(always)] - pub fn rdreq(&mut self) -> RdreqW { - RdreqW::new(self, 0) - } -} -#[doc = "Target Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scfgr0Spec; -impl crate::RegisterSpec for Scfgr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scfgr0::R`](R) reader structure"] -impl crate::Readable for Scfgr0Spec {} -#[doc = "`write(|w| ..)` method takes [`scfgr0::W`](W) writer structure"] -impl crate::Writable for Scfgr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCFGR0 to value 0"] -impl crate::Resettable for Scfgr0Spec {} diff --git a/mcxa276-pac/src/lpi2c0/scfgr1.rs b/mcxa276-pac/src/lpi2c0/scfgr1.rs deleted file mode 100644 index e3a809032..000000000 --- a/mcxa276-pac/src/lpi2c0/scfgr1.rs +++ /dev/null @@ -1,1057 +0,0 @@ -#[doc = "Register `SCFGR1` reader"] -pub type R = crate::R; -#[doc = "Register `SCFGR1` writer"] -pub type W = crate::W; -#[doc = "Address SCL Stall\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adrstall { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adrstall) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADRSTALL` reader - Address SCL Stall"] -pub type AdrstallR = crate::BitReader; -impl AdrstallR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adrstall { - match self.bits { - false => Adrstall::Disabled, - true => Adrstall::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adrstall::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adrstall::Enabled - } -} -#[doc = "Field `ADRSTALL` writer - Address SCL Stall"] -pub type AdrstallW<'a, REG> = crate::BitWriter<'a, REG, Adrstall>; -impl<'a, REG> AdrstallW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adrstall::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adrstall::Enabled) - } -} -#[doc = "RX SCL Stall\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxstall { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxstall) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXSTALL` reader - RX SCL Stall"] -pub type RxstallR = crate::BitReader; -impl RxstallR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxstall { - match self.bits { - false => Rxstall::Disabled, - true => Rxstall::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rxstall::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rxstall::Enabled - } -} -#[doc = "Field `RXSTALL` writer - RX SCL Stall"] -pub type RxstallW<'a, REG> = crate::BitWriter<'a, REG, Rxstall>; -impl<'a, REG> RxstallW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rxstall::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rxstall::Enabled) - } -} -#[doc = "Transmit Data SCL Stall\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txdstall { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txdstall) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXDSTALL` reader - Transmit Data SCL Stall"] -pub type TxdstallR = crate::BitReader; -impl TxdstallR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txdstall { - match self.bits { - false => Txdstall::Disabled, - true => Txdstall::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Txdstall::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Txdstall::Enabled - } -} -#[doc = "Field `TXDSTALL` writer - Transmit Data SCL Stall"] -pub type TxdstallW<'a, REG> = crate::BitWriter<'a, REG, Txdstall>; -impl<'a, REG> TxdstallW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Txdstall::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Txdstall::Enabled) - } -} -#[doc = "ACK SCL Stall\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ackstall { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ackstall) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ACKSTALL` reader - ACK SCL Stall"] -pub type AckstallR = crate::BitReader; -impl AckstallR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ackstall { - match self.bits { - false => Ackstall::Disabled, - true => Ackstall::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ackstall::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ackstall::Enabled - } -} -#[doc = "Field `ACKSTALL` writer - ACK SCL Stall"] -pub type AckstallW<'a, REG> = crate::BitWriter<'a, REG, Ackstall>; -impl<'a, REG> AckstallW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ackstall::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ackstall::Enabled) - } -} -#[doc = "Receive NACK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxnack { - #[doc = "0: ACK or NACK always determined by STAR\\[TXNACK\\]"] - SetByTxnack = 0, - #[doc = "1: NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"] - AlwaysGeneratedOnAddressOrReceiveDataOverrun = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxnack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXNACK` reader - Receive NACK"] -pub type RxnackR = crate::BitReader; -impl RxnackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxnack { - match self.bits { - false => Rxnack::SetByTxnack, - true => Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun, - } - } - #[doc = "ACK or NACK always determined by STAR\\[TXNACK\\]"] - #[inline(always)] - pub fn is_set_by_txnack(&self) -> bool { - *self == Rxnack::SetByTxnack - } - #[doc = "NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"] - #[inline(always)] - pub fn is_always_generated_on_address_or_receive_data_overrun(&self) -> bool { - *self == Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun - } -} -#[doc = "Field `RXNACK` writer - Receive NACK"] -pub type RxnackW<'a, REG> = crate::BitWriter<'a, REG, Rxnack>; -impl<'a, REG> RxnackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ACK or NACK always determined by STAR\\[TXNACK\\]"] - #[inline(always)] - pub fn set_by_txnack(self) -> &'a mut crate::W { - self.variant(Rxnack::SetByTxnack) - } - #[doc = "NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"] - #[inline(always)] - pub fn always_generated_on_address_or_receive_data_overrun(self) -> &'a mut crate::W { - self.variant(Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun) - } -} -#[doc = "General Call Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gcen { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gcen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GCEN` reader - General Call Enable"] -pub type GcenR = crate::BitReader; -impl GcenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gcen { - match self.bits { - false => Gcen::Disabled, - true => Gcen::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gcen::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gcen::Enabled - } -} -#[doc = "Field `GCEN` writer - General Call Enable"] -pub type GcenW<'a, REG> = crate::BitWriter<'a, REG, Gcen>; -impl<'a, REG> GcenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gcen::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gcen::Enabled) - } -} -#[doc = "SMBus Alert Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Saen { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Saen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SAEN` reader - SMBus Alert Enable"] -pub type SaenR = crate::BitReader; -impl SaenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Saen { - match self.bits { - false => Saen::Disable, - true => Saen::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Saen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Saen::Enable - } -} -#[doc = "Field `SAEN` writer - SMBus Alert Enable"] -pub type SaenW<'a, REG> = crate::BitWriter<'a, REG, Saen>; -impl<'a, REG> SaenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Saen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Saen::Enable) - } -} -#[doc = "Transmit Flag Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txcfg { - #[doc = "0: MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"] - AssertsDuringSlaveTransmitTransferWhenTxDataEmpty = 0, - #[doc = "1: MSR\\[TDF\\] is set whenever STDR is empty"] - AssertsWhenTxDataEmpty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txcfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXCFG` reader - Transmit Flag Configuration"] -pub type TxcfgR = crate::BitReader; -impl TxcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txcfg { - match self.bits { - false => Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty, - true => Txcfg::AssertsWhenTxDataEmpty, - } - } - #[doc = "MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"] - #[inline(always)] - pub fn is_asserts_during_slave_transmit_transfer_when_tx_data_empty(&self) -> bool { - *self == Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty - } - #[doc = "MSR\\[TDF\\] is set whenever STDR is empty"] - #[inline(always)] - pub fn is_asserts_when_tx_data_empty(&self) -> bool { - *self == Txcfg::AssertsWhenTxDataEmpty - } -} -#[doc = "Field `TXCFG` writer - Transmit Flag Configuration"] -pub type TxcfgW<'a, REG> = crate::BitWriter<'a, REG, Txcfg>; -impl<'a, REG> TxcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"] - #[inline(always)] - pub fn asserts_during_slave_transmit_transfer_when_tx_data_empty( - self, - ) -> &'a mut crate::W { - self.variant(Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty) - } - #[doc = "MSR\\[TDF\\] is set whenever STDR is empty"] - #[inline(always)] - pub fn asserts_when_tx_data_empty(self) -> &'a mut crate::W { - self.variant(Txcfg::AssertsWhenTxDataEmpty) - } -} -#[doc = "Receive Data Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxcfg { - #[doc = "0: Return received data, clear MSR\\[RDF\\]"] - ReturnsReceivedDataAndClearsRxDataFlag = 0, - #[doc = "1: Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"] - WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxcfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXCFG` reader - Receive Data Configuration"] -pub type RxcfgR = crate::BitReader; -impl RxcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxcfg { - match self.bits { - false => Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag, - true => Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag, - } - } - #[doc = "Return received data, clear MSR\\[RDF\\]"] - #[inline(always)] - pub fn is_returns_received_data_and_clears_rx_data_flag(&self) -> bool { - *self == Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag - } - #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"] - #[inline(always)] - pub fn is_when_address_valid_flag_set_returns_address_status_and_clears_address_valid_flag( - &self, - ) -> bool { - *self == Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag - } -} -#[doc = "Field `RXCFG` writer - Receive Data Configuration"] -pub type RxcfgW<'a, REG> = crate::BitWriter<'a, REG, Rxcfg>; -impl<'a, REG> RxcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Return received data, clear MSR\\[RDF\\]"] - #[inline(always)] - pub fn returns_received_data_and_clears_rx_data_flag(self) -> &'a mut crate::W { - self.variant(Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag) - } - #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"] - #[inline(always)] - pub fn when_address_valid_flag_set_returns_address_status_and_clears_address_valid_flag( - self, - ) -> &'a mut crate::W { - self.variant(Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag) - } -} -#[doc = "Ignore NACK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ignack { - #[doc = "0: End transfer on NACK"] - EndsTransferOnNack = 0, - #[doc = "1: Do not end transfer on NACK"] - DoesNotEndTransferOnNack = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ignack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IGNACK` reader - Ignore NACK"] -pub type IgnackR = crate::BitReader; -impl IgnackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ignack { - match self.bits { - false => Ignack::EndsTransferOnNack, - true => Ignack::DoesNotEndTransferOnNack, - } - } - #[doc = "End transfer on NACK"] - #[inline(always)] - pub fn is_ends_transfer_on_nack(&self) -> bool { - *self == Ignack::EndsTransferOnNack - } - #[doc = "Do not end transfer on NACK"] - #[inline(always)] - pub fn is_does_not_end_transfer_on_nack(&self) -> bool { - *self == Ignack::DoesNotEndTransferOnNack - } -} -#[doc = "Field `IGNACK` writer - Ignore NACK"] -pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG, Ignack>; -impl<'a, REG> IgnackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "End transfer on NACK"] - #[inline(always)] - pub fn ends_transfer_on_nack(self) -> &'a mut crate::W { - self.variant(Ignack::EndsTransferOnNack) - } - #[doc = "Do not end transfer on NACK"] - #[inline(always)] - pub fn does_not_end_transfer_on_nack(self) -> &'a mut crate::W { - self.variant(Ignack::DoesNotEndTransferOnNack) - } -} -#[doc = "HS Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hsmen { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hsmen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HSMEN` reader - HS Mode Enable"] -pub type HsmenR = crate::BitReader; -impl HsmenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hsmen { - match self.bits { - false => Hsmen::Disabled, - true => Hsmen::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Hsmen::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Hsmen::Enabled - } -} -#[doc = "Field `HSMEN` writer - HS Mode Enable"] -pub type HsmenW<'a, REG> = crate::BitWriter<'a, REG, Hsmen>; -impl<'a, REG> HsmenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Hsmen::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Hsmen::Enabled) - } -} -#[doc = "Address Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Addrcfg { - #[doc = "0: Address match 0 (7-bit)"] - AddressMatch0_7Bit = 0, - #[doc = "1: Address match 0 (10-bit)"] - AddressMatch0_10Bit = 1, - #[doc = "2: Address match 0 (7-bit) or address match 1 (7-bit)"] - AddressMatch0_7BitOrAddressMatch1_7Bit = 2, - #[doc = "3: Address match 0 (10-bit) or address match 1 (10-bit)"] - AddressMatch0_10BitOrAddressMatch1_10Bit = 3, - #[doc = "4: Address match 0 (7-bit) or address match 1 (10-bit)"] - AddressMatch0_7BitOrAddressMatch1_10Bit = 4, - #[doc = "5: Address match 0 (10-bit) or address match 1 (7-bit)"] - AddressMatch0_10BitOrAddressMatch1_7Bit = 5, - #[doc = "6: From address match 0 (7-bit) to address match 1 (7-bit)"] - FromAddressMatch0_7BitToAddressMatch1_7Bit = 6, - #[doc = "7: From address match 0 (10-bit) to address match 1 (10-bit)"] - FromAddressMatch0_10BitToAddressMatch1_10Bit = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Addrcfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Addrcfg { - type Ux = u8; -} -impl crate::IsEnum for Addrcfg {} -#[doc = "Field `ADDRCFG` reader - Address Configuration"] -pub type AddrcfgR = crate::FieldReader; -impl AddrcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Addrcfg { - match self.bits { - 0 => Addrcfg::AddressMatch0_7Bit, - 1 => Addrcfg::AddressMatch0_10Bit, - 2 => Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit, - 3 => Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit, - 4 => Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit, - 5 => Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit, - 6 => Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit, - 7 => Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit, - _ => unreachable!(), - } - } - #[doc = "Address match 0 (7-bit)"] - #[inline(always)] - pub fn is_address_match0_7_bit(&self) -> bool { - *self == Addrcfg::AddressMatch0_7Bit - } - #[doc = "Address match 0 (10-bit)"] - #[inline(always)] - pub fn is_address_match0_10_bit(&self) -> bool { - *self == Addrcfg::AddressMatch0_10Bit - } - #[doc = "Address match 0 (7-bit) or address match 1 (7-bit)"] - #[inline(always)] - pub fn is_address_match0_7_bit_or_address_match1_7_bit(&self) -> bool { - *self == Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit - } - #[doc = "Address match 0 (10-bit) or address match 1 (10-bit)"] - #[inline(always)] - pub fn is_address_match0_10_bit_or_address_match1_10_bit(&self) -> bool { - *self == Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit - } - #[doc = "Address match 0 (7-bit) or address match 1 (10-bit)"] - #[inline(always)] - pub fn is_address_match0_7_bit_or_address_match1_10_bit(&self) -> bool { - *self == Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit - } - #[doc = "Address match 0 (10-bit) or address match 1 (7-bit)"] - #[inline(always)] - pub fn is_address_match0_10_bit_or_address_match1_7_bit(&self) -> bool { - *self == Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit - } - #[doc = "From address match 0 (7-bit) to address match 1 (7-bit)"] - #[inline(always)] - pub fn is_from_address_match0_7_bit_to_address_match1_7_bit(&self) -> bool { - *self == Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit - } - #[doc = "From address match 0 (10-bit) to address match 1 (10-bit)"] - #[inline(always)] - pub fn is_from_address_match0_10_bit_to_address_match1_10_bit(&self) -> bool { - *self == Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit - } -} -#[doc = "Field `ADDRCFG` writer - Address Configuration"] -pub type AddrcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Addrcfg, crate::Safe>; -impl<'a, REG> AddrcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Address match 0 (7-bit)"] - #[inline(always)] - pub fn address_match0_7_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::AddressMatch0_7Bit) - } - #[doc = "Address match 0 (10-bit)"] - #[inline(always)] - pub fn address_match0_10_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::AddressMatch0_10Bit) - } - #[doc = "Address match 0 (7-bit) or address match 1 (7-bit)"] - #[inline(always)] - pub fn address_match0_7_bit_or_address_match1_7_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit) - } - #[doc = "Address match 0 (10-bit) or address match 1 (10-bit)"] - #[inline(always)] - pub fn address_match0_10_bit_or_address_match1_10_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit) - } - #[doc = "Address match 0 (7-bit) or address match 1 (10-bit)"] - #[inline(always)] - pub fn address_match0_7_bit_or_address_match1_10_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit) - } - #[doc = "Address match 0 (10-bit) or address match 1 (7-bit)"] - #[inline(always)] - pub fn address_match0_10_bit_or_address_match1_7_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit) - } - #[doc = "From address match 0 (7-bit) to address match 1 (7-bit)"] - #[inline(always)] - pub fn from_address_match0_7_bit_to_address_match1_7_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit) - } - #[doc = "From address match 0 (10-bit) to address match 1 (10-bit)"] - #[inline(always)] - pub fn from_address_match0_10_bit_to_address_match1_10_bit(self) -> &'a mut crate::W { - self.variant(Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit) - } -} -#[doc = "Receive All\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxall { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxall) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXALL` reader - Receive All"] -pub type RxallR = crate::BitReader; -impl RxallR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxall { - match self.bits { - false => Rxall::Disabled, - true => Rxall::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rxall::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rxall::Enabled - } -} -#[doc = "Field `RXALL` writer - Receive All"] -pub type RxallW<'a, REG> = crate::BitWriter<'a, REG, Rxall>; -impl<'a, REG> RxallW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rxall::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rxall::Enabled) - } -} -#[doc = "Repeated Start Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rscfg { - #[doc = "0: Any repeated Start condition following an address match"] - AnyRepeatedStartAfterAddressMatch = 0, - #[doc = "1: Any repeated Start condition"] - AnyRepeatedStart = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rscfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSCFG` reader - Repeated Start Configuration"] -pub type RscfgR = crate::BitReader; -impl RscfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rscfg { - match self.bits { - false => Rscfg::AnyRepeatedStartAfterAddressMatch, - true => Rscfg::AnyRepeatedStart, - } - } - #[doc = "Any repeated Start condition following an address match"] - #[inline(always)] - pub fn is_any_repeated_start_after_address_match(&self) -> bool { - *self == Rscfg::AnyRepeatedStartAfterAddressMatch - } - #[doc = "Any repeated Start condition"] - #[inline(always)] - pub fn is_any_repeated_start(&self) -> bool { - *self == Rscfg::AnyRepeatedStart - } -} -#[doc = "Field `RSCFG` writer - Repeated Start Configuration"] -pub type RscfgW<'a, REG> = crate::BitWriter<'a, REG, Rscfg>; -impl<'a, REG> RscfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Any repeated Start condition following an address match"] - #[inline(always)] - pub fn any_repeated_start_after_address_match(self) -> &'a mut crate::W { - self.variant(Rscfg::AnyRepeatedStartAfterAddressMatch) - } - #[doc = "Any repeated Start condition"] - #[inline(always)] - pub fn any_repeated_start(self) -> &'a mut crate::W { - self.variant(Rscfg::AnyRepeatedStart) - } -} -#[doc = "Stop Detect Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sdcfg { - #[doc = "0: Any Stop condition following an address match"] - AnyStopAfterAddressMatch = 0, - #[doc = "1: Any Stop condition"] - AnyStop = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sdcfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SDCFG` reader - Stop Detect Configuration"] -pub type SdcfgR = crate::BitReader; -impl SdcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sdcfg { - match self.bits { - false => Sdcfg::AnyStopAfterAddressMatch, - true => Sdcfg::AnyStop, - } - } - #[doc = "Any Stop condition following an address match"] - #[inline(always)] - pub fn is_any_stop_after_address_match(&self) -> bool { - *self == Sdcfg::AnyStopAfterAddressMatch - } - #[doc = "Any Stop condition"] - #[inline(always)] - pub fn is_any_stop(&self) -> bool { - *self == Sdcfg::AnyStop - } -} -#[doc = "Field `SDCFG` writer - Stop Detect Configuration"] -pub type SdcfgW<'a, REG> = crate::BitWriter<'a, REG, Sdcfg>; -impl<'a, REG> SdcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Any Stop condition following an address match"] - #[inline(always)] - pub fn any_stop_after_address_match(self) -> &'a mut crate::W { - self.variant(Sdcfg::AnyStopAfterAddressMatch) - } - #[doc = "Any Stop condition"] - #[inline(always)] - pub fn any_stop(self) -> &'a mut crate::W { - self.variant(Sdcfg::AnyStop) - } -} -impl R { - #[doc = "Bit 0 - Address SCL Stall"] - #[inline(always)] - pub fn adrstall(&self) -> AdrstallR { - AdrstallR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - RX SCL Stall"] - #[inline(always)] - pub fn rxstall(&self) -> RxstallR { - RxstallR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Transmit Data SCL Stall"] - #[inline(always)] - pub fn txdstall(&self) -> TxdstallR { - TxdstallR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - ACK SCL Stall"] - #[inline(always)] - pub fn ackstall(&self) -> AckstallR { - AckstallR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Receive NACK"] - #[inline(always)] - pub fn rxnack(&self) -> RxnackR { - RxnackR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 8 - General Call Enable"] - #[inline(always)] - pub fn gcen(&self) -> GcenR { - GcenR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SMBus Alert Enable"] - #[inline(always)] - pub fn saen(&self) -> SaenR { - SaenR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Transmit Flag Configuration"] - #[inline(always)] - pub fn txcfg(&self) -> TxcfgR { - TxcfgR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Receive Data Configuration"] - #[inline(always)] - pub fn rxcfg(&self) -> RxcfgR { - RxcfgR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Ignore NACK"] - #[inline(always)] - pub fn ignack(&self) -> IgnackR { - IgnackR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - HS Mode Enable"] - #[inline(always)] - pub fn hsmen(&self) -> HsmenR { - HsmenR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bits 16:18 - Address Configuration"] - #[inline(always)] - pub fn addrcfg(&self) -> AddrcfgR { - AddrcfgR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 24 - Receive All"] - #[inline(always)] - pub fn rxall(&self) -> RxallR { - RxallR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Repeated Start Configuration"] - #[inline(always)] - pub fn rscfg(&self) -> RscfgR { - RscfgR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Stop Detect Configuration"] - #[inline(always)] - pub fn sdcfg(&self) -> SdcfgR { - SdcfgR::new(((self.bits >> 26) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Address SCL Stall"] - #[inline(always)] - pub fn adrstall(&mut self) -> AdrstallW { - AdrstallW::new(self, 0) - } - #[doc = "Bit 1 - RX SCL Stall"] - #[inline(always)] - pub fn rxstall(&mut self) -> RxstallW { - RxstallW::new(self, 1) - } - #[doc = "Bit 2 - Transmit Data SCL Stall"] - #[inline(always)] - pub fn txdstall(&mut self) -> TxdstallW { - TxdstallW::new(self, 2) - } - #[doc = "Bit 3 - ACK SCL Stall"] - #[inline(always)] - pub fn ackstall(&mut self) -> AckstallW { - AckstallW::new(self, 3) - } - #[doc = "Bit 4 - Receive NACK"] - #[inline(always)] - pub fn rxnack(&mut self) -> RxnackW { - RxnackW::new(self, 4) - } - #[doc = "Bit 8 - General Call Enable"] - #[inline(always)] - pub fn gcen(&mut self) -> GcenW { - GcenW::new(self, 8) - } - #[doc = "Bit 9 - SMBus Alert Enable"] - #[inline(always)] - pub fn saen(&mut self) -> SaenW { - SaenW::new(self, 9) - } - #[doc = "Bit 10 - Transmit Flag Configuration"] - #[inline(always)] - pub fn txcfg(&mut self) -> TxcfgW { - TxcfgW::new(self, 10) - } - #[doc = "Bit 11 - Receive Data Configuration"] - #[inline(always)] - pub fn rxcfg(&mut self) -> RxcfgW { - RxcfgW::new(self, 11) - } - #[doc = "Bit 12 - Ignore NACK"] - #[inline(always)] - pub fn ignack(&mut self) -> IgnackW { - IgnackW::new(self, 12) - } - #[doc = "Bit 13 - HS Mode Enable"] - #[inline(always)] - pub fn hsmen(&mut self) -> HsmenW { - HsmenW::new(self, 13) - } - #[doc = "Bits 16:18 - Address Configuration"] - #[inline(always)] - pub fn addrcfg(&mut self) -> AddrcfgW { - AddrcfgW::new(self, 16) - } - #[doc = "Bit 24 - Receive All"] - #[inline(always)] - pub fn rxall(&mut self) -> RxallW { - RxallW::new(self, 24) - } - #[doc = "Bit 25 - Repeated Start Configuration"] - #[inline(always)] - pub fn rscfg(&mut self) -> RscfgW { - RscfgW::new(self, 25) - } - #[doc = "Bit 26 - Stop Detect Configuration"] - #[inline(always)] - pub fn sdcfg(&mut self) -> SdcfgW { - SdcfgW::new(self, 26) - } -} -#[doc = "Target Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scfgr1Spec; -impl crate::RegisterSpec for Scfgr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scfgr1::R`](R) reader structure"] -impl crate::Readable for Scfgr1Spec {} -#[doc = "`write(|w| ..)` method takes [`scfgr1::W`](W) writer structure"] -impl crate::Writable for Scfgr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCFGR1 to value 0"] -impl crate::Resettable for Scfgr1Spec {} diff --git a/mcxa276-pac/src/lpi2c0/scfgr2.rs b/mcxa276-pac/src/lpi2c0/scfgr2.rs deleted file mode 100644 index 2dbc8ab11..000000000 --- a/mcxa276-pac/src/lpi2c0/scfgr2.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `SCFGR2` reader"] -pub type R = crate::R; -#[doc = "Register `SCFGR2` writer"] -pub type W = crate::W; -#[doc = "Field `CLKHOLD` reader - Clock Hold Time"] -pub type ClkholdR = crate::FieldReader; -#[doc = "Field `CLKHOLD` writer - Clock Hold Time"] -pub type ClkholdW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DATAVD` reader - Data Valid Delay"] -pub type DatavdR = crate::FieldReader; -#[doc = "Field `DATAVD` writer - Data Valid Delay"] -pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `FILTSCL` reader - Glitch Filter SCL"] -pub type FiltsclR = crate::FieldReader; -#[doc = "Field `FILTSCL` writer - Glitch Filter SCL"] -pub type FiltsclW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `FILTSDA` reader - Glitch Filter SDA"] -pub type FiltsdaR = crate::FieldReader; -#[doc = "Field `FILTSDA` writer - Glitch Filter SDA"] -pub type FiltsdaW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:3 - Clock Hold Time"] - #[inline(always)] - pub fn clkhold(&self) -> ClkholdR { - ClkholdR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 8:13 - Data Valid Delay"] - #[inline(always)] - pub fn datavd(&self) -> DatavdR { - DatavdR::new(((self.bits >> 8) & 0x3f) as u8) - } - #[doc = "Bits 16:19 - Glitch Filter SCL"] - #[inline(always)] - pub fn filtscl(&self) -> FiltsclR { - FiltsclR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:27 - Glitch Filter SDA"] - #[inline(always)] - pub fn filtsda(&self) -> FiltsdaR { - FiltsdaR::new(((self.bits >> 24) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Clock Hold Time"] - #[inline(always)] - pub fn clkhold(&mut self) -> ClkholdW { - ClkholdW::new(self, 0) - } - #[doc = "Bits 8:13 - Data Valid Delay"] - #[inline(always)] - pub fn datavd(&mut self) -> DatavdW { - DatavdW::new(self, 8) - } - #[doc = "Bits 16:19 - Glitch Filter SCL"] - #[inline(always)] - pub fn filtscl(&mut self) -> FiltsclW { - FiltsclW::new(self, 16) - } - #[doc = "Bits 24:27 - Glitch Filter SDA"] - #[inline(always)] - pub fn filtsda(&mut self) -> FiltsdaW { - FiltsdaW::new(self, 24) - } -} -#[doc = "Target Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scfgr2Spec; -impl crate::RegisterSpec for Scfgr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scfgr2::R`](R) reader structure"] -impl crate::Readable for Scfgr2Spec {} -#[doc = "`write(|w| ..)` method takes [`scfgr2::W`](W) writer structure"] -impl crate::Writable for Scfgr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCFGR2 to value 0"] -impl crate::Resettable for Scfgr2Spec {} diff --git a/mcxa276-pac/src/lpi2c0/scr.rs b/mcxa276-pac/src/lpi2c0/scr.rs deleted file mode 100644 index 0af92e8e2..000000000 --- a/mcxa276-pac/src/lpi2c0/scr.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `SCR` reader"] -pub type R = crate::R; -#[doc = "Register `SCR` writer"] -pub type W = crate::W; -#[doc = "Target Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sen { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SEN` reader - Target Enable"] -pub type SenR = crate::BitReader; -impl SenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sen { - match self.bits { - false => Sen::Disabled, - true => Sen::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sen::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sen::Enabled - } -} -#[doc = "Field `SEN` writer - Target Enable"] -pub type SenW<'a, REG> = crate::BitWriter<'a, REG, Sen>; -impl<'a, REG> SenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sen::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sen::Enabled) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rst { - #[doc = "0: Not reset"] - NotReset = 0, - #[doc = "1: Reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST` reader - Software Reset"] -pub type RstR = crate::BitReader; -impl RstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rst { - match self.bits { - false => Rst::NotReset, - true => Rst::Reset, - } - } - #[doc = "Not reset"] - #[inline(always)] - pub fn is_not_reset(&self) -> bool { - *self == Rst::NotReset - } - #[doc = "Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Rst::Reset - } -} -#[doc = "Field `RST` writer - Software Reset"] -pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; -impl<'a, REG> RstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not reset"] - #[inline(always)] - pub fn not_reset(self) -> &'a mut crate::W { - self.variant(Rst::NotReset) - } - #[doc = "Reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Rst::Reset) - } -} -#[doc = "Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Filten { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Filten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILTEN` reader - Filter Enable"] -pub type FiltenR = crate::BitReader; -impl FiltenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filten { - match self.bits { - false => Filten::Disable, - true => Filten::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Filten::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Filten::Enable - } -} -#[doc = "Field `FILTEN` writer - Filter Enable"] -pub type FiltenW<'a, REG> = crate::BitWriter<'a, REG, Filten>; -impl<'a, REG> FiltenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Filten::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Filten::Enable) - } -} -#[doc = "Filter Doze Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Filtdz { - #[doc = "0: Enable"] - FilterEnabled = 0, - #[doc = "1: Disable"] - FilterDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Filtdz) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILTDZ` reader - Filter Doze Enable"] -pub type FiltdzR = crate::BitReader; -impl FiltdzR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filtdz { - match self.bits { - false => Filtdz::FilterEnabled, - true => Filtdz::FilterDisabled, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_filter_enabled(&self) -> bool { - *self == Filtdz::FilterEnabled - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_filter_disabled(&self) -> bool { - *self == Filtdz::FilterDisabled - } -} -#[doc = "Field `FILTDZ` writer - Filter Doze Enable"] -pub type FiltdzW<'a, REG> = crate::BitWriter<'a, REG, Filtdz>; -impl<'a, REG> FiltdzW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn filter_enabled(self) -> &'a mut crate::W { - self.variant(Filtdz::FilterEnabled) - } - #[doc = "Disable"] - #[inline(always)] - pub fn filter_disabled(self) -> &'a mut crate::W { - self.variant(Filtdz::FilterDisabled) - } -} -#[doc = "Reset Transmit FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rtf { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: STDR is now empty"] - NowEmpty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rtf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RTF` reader - Reset Transmit FIFO"] -pub type RtfR = crate::BitReader; -impl RtfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rtf { - match self.bits { - false => Rtf::NoEffect, - true => Rtf::NowEmpty, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rtf::NoEffect - } - #[doc = "STDR is now empty"] - #[inline(always)] - pub fn is_now_empty(&self) -> bool { - *self == Rtf::NowEmpty - } -} -#[doc = "Field `RTF` writer - Reset Transmit FIFO"] -pub type RtfW<'a, REG> = crate::BitWriter<'a, REG, Rtf>; -impl<'a, REG> RtfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rtf::NoEffect) - } - #[doc = "STDR is now empty"] - #[inline(always)] - pub fn now_empty(self) -> &'a mut crate::W { - self.variant(Rtf::NowEmpty) - } -} -#[doc = "Reset Receive FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rrf { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: SRDR is now empty"] - NowEmpty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rrf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RRF` reader - Reset Receive FIFO"] -pub type RrfR = crate::BitReader; -impl RrfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rrf { - match self.bits { - false => Rrf::NoEffect, - true => Rrf::NowEmpty, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rrf::NoEffect - } - #[doc = "SRDR is now empty"] - #[inline(always)] - pub fn is_now_empty(&self) -> bool { - *self == Rrf::NowEmpty - } -} -#[doc = "Field `RRF` writer - Reset Receive FIFO"] -pub type RrfW<'a, REG> = crate::BitWriter<'a, REG, Rrf>; -impl<'a, REG> RrfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rrf::NoEffect) - } - #[doc = "SRDR is now empty"] - #[inline(always)] - pub fn now_empty(self) -> &'a mut crate::W { - self.variant(Rrf::NowEmpty) - } -} -impl R { - #[doc = "Bit 0 - Target Enable"] - #[inline(always)] - pub fn sen(&self) -> SenR { - SenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&self) -> RstR { - RstR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 4 - Filter Enable"] - #[inline(always)] - pub fn filten(&self) -> FiltenR { - FiltenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Filter Doze Enable"] - #[inline(always)] - pub fn filtdz(&self) -> FiltdzR { - FiltdzR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 8 - Reset Transmit FIFO"] - #[inline(always)] - pub fn rtf(&self) -> RtfR { - RtfR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Reset Receive FIFO"] - #[inline(always)] - pub fn rrf(&self) -> RrfR { - RrfR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Target Enable"] - #[inline(always)] - pub fn sen(&mut self) -> SenW { - SenW::new(self, 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&mut self) -> RstW { - RstW::new(self, 1) - } - #[doc = "Bit 4 - Filter Enable"] - #[inline(always)] - pub fn filten(&mut self) -> FiltenW { - FiltenW::new(self, 4) - } - #[doc = "Bit 5 - Filter Doze Enable"] - #[inline(always)] - pub fn filtdz(&mut self) -> FiltdzW { - FiltdzW::new(self, 5) - } - #[doc = "Bit 8 - Reset Transmit FIFO"] - #[inline(always)] - pub fn rtf(&mut self) -> RtfW { - RtfW::new(self, 8) - } - #[doc = "Bit 9 - Reset Receive FIFO"] - #[inline(always)] - pub fn rrf(&mut self) -> RrfW { - RrfW::new(self, 9) - } -} -#[doc = "Target Control\n\nYou can [`read`](crate::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ScrSpec; -impl crate::RegisterSpec for ScrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr::R`](R) reader structure"] -impl crate::Readable for ScrSpec {} -#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] -impl crate::Writable for ScrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCR to value 0"] -impl crate::Resettable for ScrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/sder.rs b/mcxa276-pac/src/lpi2c0/sder.rs deleted file mode 100644 index 0be9d6102..000000000 --- a/mcxa276-pac/src/lpi2c0/sder.rs +++ /dev/null @@ -1,336 +0,0 @@ -#[doc = "Register `SDER` reader"] -pub type R = crate::R; -#[doc = "Register `SDER` writer"] -pub type W = crate::W; -#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdde { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"] -pub type TddeR = crate::BitReader; -impl TddeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdde { - match self.bits { - false => Tdde::Disabled, - true => Tdde::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tdde::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tdde::Enabled - } -} -#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"] -pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>; -impl<'a, REG> TddeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tdde::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tdde::Enabled) - } -} -#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdde { - #[doc = "0: Disable DMA request"] - Disabled = 0, - #[doc = "1: Enable DMA request"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDDE` reader - Receive Data DMA Enable"] -pub type RddeR = crate::BitReader; -impl RddeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdde { - match self.bits { - false => Rdde::Disabled, - true => Rdde::Enabled, - } - } - #[doc = "Disable DMA request"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdde::Disabled - } - #[doc = "Enable DMA request"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdde::Enabled - } -} -#[doc = "Field `RDDE` writer - Receive Data DMA Enable"] -pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>; -impl<'a, REG> RddeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable DMA request"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rdde::Disabled) - } - #[doc = "Enable DMA request"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rdde::Enabled) - } -} -#[doc = "Address Valid DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Avde { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Avde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AVDE` reader - Address Valid DMA Enable"] -pub type AvdeR = crate::BitReader; -impl AvdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Avde { - match self.bits { - false => Avde::Disabled, - true => Avde::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Avde::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Avde::Enabled - } -} -#[doc = "Field `AVDE` writer - Address Valid DMA Enable"] -pub type AvdeW<'a, REG> = crate::BitWriter<'a, REG, Avde>; -impl<'a, REG> AvdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Avde::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Avde::Enabled) - } -} -#[doc = "Repeated Start DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rsde { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rsde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSDE` reader - Repeated Start DMA Enable"] -pub type RsdeR = crate::BitReader; -impl RsdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rsde { - match self.bits { - false => Rsde::Disabled, - true => Rsde::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rsde::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rsde::Enabled - } -} -#[doc = "Field `RSDE` writer - Repeated Start DMA Enable"] -pub type RsdeW<'a, REG> = crate::BitWriter<'a, REG, Rsde>; -impl<'a, REG> RsdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rsde::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rsde::Enabled) - } -} -#[doc = "Stop Detect DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sdde { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sdde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SDDE` reader - Stop Detect DMA Enable"] -pub type SddeR = crate::BitReader; -impl SddeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sdde { - match self.bits { - false => Sdde::Disabled, - true => Sdde::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sdde::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sdde::Enabled - } -} -#[doc = "Field `SDDE` writer - Stop Detect DMA Enable"] -pub type SddeW<'a, REG> = crate::BitWriter<'a, REG, Sdde>; -impl<'a, REG> SddeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sdde::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sdde::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Transmit Data DMA Enable"] - #[inline(always)] - pub fn tdde(&self) -> TddeR { - TddeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data DMA Enable"] - #[inline(always)] - pub fn rdde(&self) -> RddeR { - RddeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Address Valid DMA Enable"] - #[inline(always)] - pub fn avde(&self) -> AvdeR { - AvdeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 8 - Repeated Start DMA Enable"] - #[inline(always)] - pub fn rsde(&self) -> RsdeR { - RsdeR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Stop Detect DMA Enable"] - #[inline(always)] - pub fn sdde(&self) -> SddeR { - SddeR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmit Data DMA Enable"] - #[inline(always)] - pub fn tdde(&mut self) -> TddeW { - TddeW::new(self, 0) - } - #[doc = "Bit 1 - Receive Data DMA Enable"] - #[inline(always)] - pub fn rdde(&mut self) -> RddeW { - RddeW::new(self, 1) - } - #[doc = "Bit 2 - Address Valid DMA Enable"] - #[inline(always)] - pub fn avde(&mut self) -> AvdeW { - AvdeW::new(self, 2) - } - #[doc = "Bit 8 - Repeated Start DMA Enable"] - #[inline(always)] - pub fn rsde(&mut self) -> RsdeW { - RsdeW::new(self, 8) - } - #[doc = "Bit 9 - Stop Detect DMA Enable"] - #[inline(always)] - pub fn sdde(&mut self) -> SddeW { - SddeW::new(self, 9) - } -} -#[doc = "Target DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sder::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sder::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SderSpec; -impl crate::RegisterSpec for SderSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sder::R`](R) reader structure"] -impl crate::Readable for SderSpec {} -#[doc = "`write(|w| ..)` method takes [`sder::W`](W) writer structure"] -impl crate::Writable for SderSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SDER to value 0"] -impl crate::Resettable for SderSpec {} diff --git a/mcxa276-pac/src/lpi2c0/sier.rs b/mcxa276-pac/src/lpi2c0/sier.rs deleted file mode 100644 index 3e80516cf..000000000 --- a/mcxa276-pac/src/lpi2c0/sier.rs +++ /dev/null @@ -1,777 +0,0 @@ -#[doc = "Register `SIER` reader"] -pub type R = crate::R; -#[doc = "Register `SIER` writer"] -pub type W = crate::W; -#[doc = "Transmit Data Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDIE` reader - Transmit Data Interrupt Enable"] -pub type TdieR = crate::BitReader; -impl TdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdie { - match self.bits { - false => Tdie::Disabled, - true => Tdie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tdie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tdie::Enabled - } -} -#[doc = "Field `TDIE` writer - Transmit Data Interrupt Enable"] -pub type TdieW<'a, REG> = crate::BitWriter<'a, REG, Tdie>; -impl<'a, REG> TdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tdie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tdie::Enabled) - } -} -#[doc = "Receive Data Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDIE` reader - Receive Data Interrupt Enable"] -pub type RdieR = crate::BitReader; -impl RdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdie { - match self.bits { - false => Rdie::Disabled, - true => Rdie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdie::Enabled - } -} -#[doc = "Field `RDIE` writer - Receive Data Interrupt Enable"] -pub type RdieW<'a, REG> = crate::BitWriter<'a, REG, Rdie>; -impl<'a, REG> RdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rdie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rdie::Enabled) - } -} -#[doc = "Address Valid Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Avie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Avie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AVIE` reader - Address Valid Interrupt Enable"] -pub type AvieR = crate::BitReader; -impl AvieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Avie { - match self.bits { - false => Avie::Disabled, - true => Avie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Avie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Avie::Enabled - } -} -#[doc = "Field `AVIE` writer - Address Valid Interrupt Enable"] -pub type AvieW<'a, REG> = crate::BitWriter<'a, REG, Avie>; -impl<'a, REG> AvieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Avie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Avie::Enabled) - } -} -#[doc = "Transmit ACK Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Taie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Taie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TAIE` reader - Transmit ACK Interrupt Enable"] -pub type TaieR = crate::BitReader; -impl TaieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Taie { - match self.bits { - false => Taie::Disabled, - true => Taie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Taie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Taie::Enabled - } -} -#[doc = "Field `TAIE` writer - Transmit ACK Interrupt Enable"] -pub type TaieW<'a, REG> = crate::BitWriter<'a, REG, Taie>; -impl<'a, REG> TaieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Taie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Taie::Enabled) - } -} -#[doc = "Repeated Start Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rsie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rsie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSIE` reader - Repeated Start Interrupt Enable"] -pub type RsieR = crate::BitReader; -impl RsieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rsie { - match self.bits { - false => Rsie::Disabled, - true => Rsie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rsie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rsie::Enabled - } -} -#[doc = "Field `RSIE` writer - Repeated Start Interrupt Enable"] -pub type RsieW<'a, REG> = crate::BitWriter<'a, REG, Rsie>; -impl<'a, REG> RsieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rsie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rsie::Enabled) - } -} -#[doc = "Stop Detect Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sdie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SDIE` reader - Stop Detect Interrupt Enable"] -pub type SdieR = crate::BitReader; -impl SdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sdie { - match self.bits { - false => Sdie::Disabled, - true => Sdie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sdie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sdie::Enabled - } -} -#[doc = "Field `SDIE` writer - Stop Detect Interrupt Enable"] -pub type SdieW<'a, REG> = crate::BitWriter<'a, REG, Sdie>; -impl<'a, REG> SdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sdie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sdie::Enabled) - } -} -#[doc = "Bit Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Beie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Beie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BEIE` reader - Bit Error Interrupt Enable"] -pub type BeieR = crate::BitReader; -impl BeieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Beie { - match self.bits { - false => Beie::Disabled, - true => Beie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Beie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Beie::Enabled - } -} -#[doc = "Field `BEIE` writer - Bit Error Interrupt Enable"] -pub type BeieW<'a, REG> = crate::BitWriter<'a, REG, Beie>; -impl<'a, REG> BeieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Beie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Beie::Enabled) - } -} -#[doc = "FIFO Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Feie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Feie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FEIE` reader - FIFO Error Interrupt Enable"] -pub type FeieR = crate::BitReader; -impl FeieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Feie { - match self.bits { - false => Feie::Disabled, - true => Feie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Feie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Feie::Enabled - } -} -#[doc = "Field `FEIE` writer - FIFO Error Interrupt Enable"] -pub type FeieW<'a, REG> = crate::BitWriter<'a, REG, Feie>; -impl<'a, REG> FeieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Feie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Feie::Enabled) - } -} -#[doc = "Address Match 0 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Am0ie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Am0ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AM0IE` reader - Address Match 0 Interrupt Enable"] -pub type Am0ieR = crate::BitReader; -impl Am0ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Am0ie { - match self.bits { - false => Am0ie::Disabled, - true => Am0ie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Am0ie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Am0ie::Enabled - } -} -#[doc = "Field `AM0IE` writer - Address Match 0 Interrupt Enable"] -pub type Am0ieW<'a, REG> = crate::BitWriter<'a, REG, Am0ie>; -impl<'a, REG> Am0ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Am0ie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Am0ie::Enabled) - } -} -#[doc = "Address Match 1 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Am1ie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Am1ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AM1IE` reader - Address Match 1 Interrupt Enable"] -pub type Am1ieR = crate::BitReader; -impl Am1ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Am1ie { - match self.bits { - false => Am1ie::Disabled, - true => Am1ie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Am1ie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Am1ie::Enabled - } -} -#[doc = "Field `AM1IE` writer - Address Match 1 Interrupt Enable"] -pub type Am1ieW<'a, REG> = crate::BitWriter<'a, REG, Am1ie>; -impl<'a, REG> Am1ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Am1ie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Am1ie::Enabled) - } -} -#[doc = "General Call Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gcie { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gcie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GCIE` reader - General Call Interrupt Enable"] -pub type GcieR = crate::BitReader; -impl GcieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gcie { - match self.bits { - false => Gcie::Disabled, - true => Gcie::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gcie::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gcie::Enabled - } -} -#[doc = "Field `GCIE` writer - General Call Interrupt Enable"] -pub type GcieW<'a, REG> = crate::BitWriter<'a, REG, Gcie>; -impl<'a, REG> GcieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gcie::Disabled) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gcie::Enabled) - } -} -#[doc = "SMBus Alert Response Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sarie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sarie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SARIE` reader - SMBus Alert Response Interrupt Enable"] -pub type SarieR = crate::BitReader; -impl SarieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sarie { - match self.bits { - false => Sarie::Disabled, - true => Sarie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sarie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sarie::Enabled - } -} -#[doc = "Field `SARIE` writer - SMBus Alert Response Interrupt Enable"] -pub type SarieW<'a, REG> = crate::BitWriter<'a, REG, Sarie>; -impl<'a, REG> SarieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sarie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sarie::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Transmit Data Interrupt Enable"] - #[inline(always)] - pub fn tdie(&self) -> TdieR { - TdieR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data Interrupt Enable"] - #[inline(always)] - pub fn rdie(&self) -> RdieR { - RdieR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Address Valid Interrupt Enable"] - #[inline(always)] - pub fn avie(&self) -> AvieR { - AvieR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Transmit ACK Interrupt Enable"] - #[inline(always)] - pub fn taie(&self) -> TaieR { - TaieR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Repeated Start Interrupt Enable"] - #[inline(always)] - pub fn rsie(&self) -> RsieR { - RsieR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Stop Detect Interrupt Enable"] - #[inline(always)] - pub fn sdie(&self) -> SdieR { - SdieR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Bit Error Interrupt Enable"] - #[inline(always)] - pub fn beie(&self) -> BeieR { - BeieR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - FIFO Error Interrupt Enable"] - #[inline(always)] - pub fn feie(&self) -> FeieR { - FeieR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Address Match 0 Interrupt Enable"] - #[inline(always)] - pub fn am0ie(&self) -> Am0ieR { - Am0ieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Address Match 1 Interrupt Enable"] - #[inline(always)] - pub fn am1ie(&self) -> Am1ieR { - Am1ieR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - General Call Interrupt Enable"] - #[inline(always)] - pub fn gcie(&self) -> GcieR { - GcieR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - SMBus Alert Response Interrupt Enable"] - #[inline(always)] - pub fn sarie(&self) -> SarieR { - SarieR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmit Data Interrupt Enable"] - #[inline(always)] - pub fn tdie(&mut self) -> TdieW { - TdieW::new(self, 0) - } - #[doc = "Bit 1 - Receive Data Interrupt Enable"] - #[inline(always)] - pub fn rdie(&mut self) -> RdieW { - RdieW::new(self, 1) - } - #[doc = "Bit 2 - Address Valid Interrupt Enable"] - #[inline(always)] - pub fn avie(&mut self) -> AvieW { - AvieW::new(self, 2) - } - #[doc = "Bit 3 - Transmit ACK Interrupt Enable"] - #[inline(always)] - pub fn taie(&mut self) -> TaieW { - TaieW::new(self, 3) - } - #[doc = "Bit 8 - Repeated Start Interrupt Enable"] - #[inline(always)] - pub fn rsie(&mut self) -> RsieW { - RsieW::new(self, 8) - } - #[doc = "Bit 9 - Stop Detect Interrupt Enable"] - #[inline(always)] - pub fn sdie(&mut self) -> SdieW { - SdieW::new(self, 9) - } - #[doc = "Bit 10 - Bit Error Interrupt Enable"] - #[inline(always)] - pub fn beie(&mut self) -> BeieW { - BeieW::new(self, 10) - } - #[doc = "Bit 11 - FIFO Error Interrupt Enable"] - #[inline(always)] - pub fn feie(&mut self) -> FeieW { - FeieW::new(self, 11) - } - #[doc = "Bit 12 - Address Match 0 Interrupt Enable"] - #[inline(always)] - pub fn am0ie(&mut self) -> Am0ieW { - Am0ieW::new(self, 12) - } - #[doc = "Bit 13 - Address Match 1 Interrupt Enable"] - #[inline(always)] - pub fn am1ie(&mut self) -> Am1ieW { - Am1ieW::new(self, 13) - } - #[doc = "Bit 14 - General Call Interrupt Enable"] - #[inline(always)] - pub fn gcie(&mut self) -> GcieW { - GcieW::new(self, 14) - } - #[doc = "Bit 15 - SMBus Alert Response Interrupt Enable"] - #[inline(always)] - pub fn sarie(&mut self) -> SarieW { - SarieW::new(self, 15) - } -} -#[doc = "Target Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SierSpec; -impl crate::RegisterSpec for SierSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sier::R`](R) reader structure"] -impl crate::Readable for SierSpec {} -#[doc = "`write(|w| ..)` method takes [`sier::W`](W) writer structure"] -impl crate::Writable for SierSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SIER to value 0"] -impl crate::Resettable for SierSpec {} diff --git a/mcxa276-pac/src/lpi2c0/srdr.rs b/mcxa276-pac/src/lpi2c0/srdr.rs deleted file mode 100644 index 0f4803b5d..000000000 --- a/mcxa276-pac/src/lpi2c0/srdr.rs +++ /dev/null @@ -1,111 +0,0 @@ -#[doc = "Register `SRDR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Received Data"] -pub type DataR = crate::FieldReader; -#[doc = "Field `RADDR` reader - Received Address"] -pub type RaddrR = crate::FieldReader; -#[doc = "Receive Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempty { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPTY` reader - Receive Empty"] -pub type RxemptyR = crate::BitReader; -impl RxemptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempty { - match self.bits { - false => Rxempty::NotEmpty, - true => Rxempty::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempty::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempty::Empty - } -} -#[doc = "Start of Frame\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sof { - #[doc = "0: Not first"] - NotFirstDataWord = 0, - #[doc = "1: First"] - FirstDataWord = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOF` reader - Start of Frame"] -pub type SofR = crate::BitReader; -impl SofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sof { - match self.bits { - false => Sof::NotFirstDataWord, - true => Sof::FirstDataWord, - } - } - #[doc = "Not first"] - #[inline(always)] - pub fn is_not_first_data_word(&self) -> bool { - *self == Sof::NotFirstDataWord - } - #[doc = "First"] - #[inline(always)] - pub fn is_first_data_word(&self) -> bool { - *self == Sof::FirstDataWord - } -} -impl R { - #[doc = "Bits 0:7 - Received Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Received Address"] - #[inline(always)] - pub fn raddr(&self) -> RaddrR { - RaddrR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 14 - Receive Empty"] - #[inline(always)] - pub fn rxempty(&self) -> RxemptyR { - RxemptyR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Start of Frame"] - #[inline(always)] - pub fn sof(&self) -> SofR { - SofR::new(((self.bits >> 15) & 1) != 0) - } -} -#[doc = "Target Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`srdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrdrSpec; -impl crate::RegisterSpec for SrdrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`srdr::R`](R) reader structure"] -impl crate::Readable for SrdrSpec {} -#[doc = "`reset()` method sets SRDR to value 0x4000"] -impl crate::Resettable for SrdrSpec { - const RESET_VALUE: u32 = 0x4000; -} diff --git a/mcxa276-pac/src/lpi2c0/srdror.rs b/mcxa276-pac/src/lpi2c0/srdror.rs deleted file mode 100644 index cb0b415c3..000000000 --- a/mcxa276-pac/src/lpi2c0/srdror.rs +++ /dev/null @@ -1,111 +0,0 @@ -#[doc = "Register `SRDROR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Receive Data"] -pub type DataR = crate::FieldReader; -#[doc = "Field `RADDR` reader - Received Address"] -pub type RaddrR = crate::FieldReader; -#[doc = "Receive Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempty { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPTY` reader - Receive Empty"] -pub type RxemptyR = crate::BitReader; -impl RxemptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempty { - match self.bits { - false => Rxempty::NotEmpty, - true => Rxempty::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempty::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempty::Empty - } -} -#[doc = "Start of Frame\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sof { - #[doc = "0: Not the first"] - NotFirstDataWord = 0, - #[doc = "1: First"] - FirstDataWord = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOF` reader - Start of Frame"] -pub type SofR = crate::BitReader; -impl SofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sof { - match self.bits { - false => Sof::NotFirstDataWord, - true => Sof::FirstDataWord, - } - } - #[doc = "Not the first"] - #[inline(always)] - pub fn is_not_first_data_word(&self) -> bool { - *self == Sof::NotFirstDataWord - } - #[doc = "First"] - #[inline(always)] - pub fn is_first_data_word(&self) -> bool { - *self == Sof::FirstDataWord - } -} -impl R { - #[doc = "Bits 0:7 - Receive Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:10 - Received Address"] - #[inline(always)] - pub fn raddr(&self) -> RaddrR { - RaddrR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 14 - Receive Empty"] - #[inline(always)] - pub fn rxempty(&self) -> RxemptyR { - RxemptyR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Start of Frame"] - #[inline(always)] - pub fn sof(&self) -> SofR { - SofR::new(((self.bits >> 15) & 1) != 0) - } -} -#[doc = "Target Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`srdror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrdrorSpec; -impl crate::RegisterSpec for SrdrorSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`srdror::R`](R) reader structure"] -impl crate::Readable for SrdrorSpec {} -#[doc = "`reset()` method sets SRDROR to value 0x4000"] -impl crate::Resettable for SrdrorSpec { - const RESET_VALUE: u32 = 0x4000; -} diff --git a/mcxa276-pac/src/lpi2c0/ssr.rs b/mcxa276-pac/src/lpi2c0/ssr.rs deleted file mode 100644 index a4c0b8b47..000000000 --- a/mcxa276-pac/src/lpi2c0/ssr.rs +++ /dev/null @@ -1,684 +0,0 @@ -#[doc = "Register `SSR` reader"] -pub type R = crate::R; -#[doc = "Register `SSR` writer"] -pub type W = crate::W; -#[doc = "Transmit Data Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdf { - #[doc = "0: Transmit data not requested"] - NoFlag = 0, - #[doc = "1: Transmit data is requested"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDF` reader - Transmit Data Flag"] -pub type TdfR = crate::BitReader; -impl TdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdf { - match self.bits { - false => Tdf::NoFlag, - true => Tdf::Flag, - } - } - #[doc = "Transmit data not requested"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Tdf::NoFlag - } - #[doc = "Transmit data is requested"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Tdf::Flag - } -} -#[doc = "Receive Data Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdf { - #[doc = "0: Not ready"] - NotReady = 0, - #[doc = "1: Ready"] - Ready = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDF` reader - Receive Data Flag"] -pub type RdfR = crate::BitReader; -impl RdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdf { - match self.bits { - false => Rdf::NotReady, - true => Rdf::Ready, - } - } - #[doc = "Not ready"] - #[inline(always)] - pub fn is_not_ready(&self) -> bool { - *self == Rdf::NotReady - } - #[doc = "Ready"] - #[inline(always)] - pub fn is_ready(&self) -> bool { - *self == Rdf::Ready - } -} -#[doc = "Address Valid Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Avf { - #[doc = "0: Not valid"] - NotValid = 0, - #[doc = "1: Valid"] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Avf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AVF` reader - Address Valid Flag"] -pub type AvfR = crate::BitReader; -impl AvfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Avf { - match self.bits { - false => Avf::NotValid, - true => Avf::Valid, - } - } - #[doc = "Not valid"] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Avf::NotValid - } - #[doc = "Valid"] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Avf::Valid - } -} -#[doc = "Transmit ACK Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Taf { - #[doc = "0: Not required"] - NotRequired = 0, - #[doc = "1: Required"] - Required = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Taf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TAF` reader - Transmit ACK Flag"] -pub type TafR = crate::BitReader; -impl TafR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Taf { - match self.bits { - false => Taf::NotRequired, - true => Taf::Required, - } - } - #[doc = "Not required"] - #[inline(always)] - pub fn is_not_required(&self) -> bool { - *self == Taf::NotRequired - } - #[doc = "Required"] - #[inline(always)] - pub fn is_required(&self) -> bool { - *self == Taf::Required - } -} -#[doc = "Repeated Start Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rsf { - #[doc = "0: No repeated Start detected"] - IntNo = 0, - #[doc = "1: Repeated Start detected"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rsf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSF` reader - Repeated Start Flag"] -pub type RsfR = crate::BitReader; -impl RsfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rsf { - match self.bits { - false => Rsf::IntNo, - true => Rsf::IntYes, - } - } - #[doc = "No repeated Start detected"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Rsf::IntNo - } - #[doc = "Repeated Start detected"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Rsf::IntYes - } -} -#[doc = "Field `RSF` writer - Repeated Start Flag"] -pub type RsfW<'a, REG> = crate::BitWriter1C<'a, REG, Rsf>; -impl<'a, REG> RsfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No repeated Start detected"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Rsf::IntNo) - } - #[doc = "Repeated Start detected"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Rsf::IntYes) - } -} -#[doc = "Stop Detect Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sdf { - #[doc = "0: No Stop detected"] - IntNo = 0, - #[doc = "1: Stop detected"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SDF` reader - Stop Detect Flag"] -pub type SdfR = crate::BitReader; -impl SdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sdf { - match self.bits { - false => Sdf::IntNo, - true => Sdf::IntYes, - } - } - #[doc = "No Stop detected"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Sdf::IntNo - } - #[doc = "Stop detected"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Sdf::IntYes - } -} -#[doc = "Field `SDF` writer - Stop Detect Flag"] -pub type SdfW<'a, REG> = crate::BitWriter1C<'a, REG, Sdf>; -impl<'a, REG> SdfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No Stop detected"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Sdf::IntNo) - } - #[doc = "Stop detected"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Sdf::IntYes) - } -} -#[doc = "Bit Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bef { - #[doc = "0: No bit error occurred"] - IntNo = 0, - #[doc = "1: Bit error occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bef) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BEF` reader - Bit Error Flag"] -pub type BefR = crate::BitReader; -impl BefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bef { - match self.bits { - false => Bef::IntNo, - true => Bef::IntYes, - } - } - #[doc = "No bit error occurred"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Bef::IntNo - } - #[doc = "Bit error occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Bef::IntYes - } -} -#[doc = "Field `BEF` writer - Bit Error Flag"] -pub type BefW<'a, REG> = crate::BitWriter1C<'a, REG, Bef>; -impl<'a, REG> BefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No bit error occurred"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Bef::IntNo) - } - #[doc = "Bit error occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Bef::IntYes) - } -} -#[doc = "FIFO Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fef { - #[doc = "0: No FIFO error"] - IntNo = 0, - #[doc = "1: FIFO error"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fef) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FEF` reader - FIFO Error Flag"] -pub type FefR = crate::BitReader; -impl FefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fef { - match self.bits { - false => Fef::IntNo, - true => Fef::IntYes, - } - } - #[doc = "No FIFO error"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Fef::IntNo - } - #[doc = "FIFO error"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Fef::IntYes - } -} -#[doc = "Field `FEF` writer - FIFO Error Flag"] -pub type FefW<'a, REG> = crate::BitWriter1C<'a, REG, Fef>; -impl<'a, REG> FefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No FIFO error"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Fef::IntNo) - } - #[doc = "FIFO error"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Fef::IntYes) - } -} -#[doc = "Address Match 0 Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Am0f { - #[doc = "0: ADDR0 matching address not received"] - NoFlag = 0, - #[doc = "1: ADDR0 matching address received"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Am0f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AM0F` reader - Address Match 0 Flag"] -pub type Am0fR = crate::BitReader; -impl Am0fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Am0f { - match self.bits { - false => Am0f::NoFlag, - true => Am0f::Flag, - } - } - #[doc = "ADDR0 matching address not received"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Am0f::NoFlag - } - #[doc = "ADDR0 matching address received"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Am0f::Flag - } -} -#[doc = "Address Match 1 Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Am1f { - #[doc = "0: Matching address not received"] - NoFlag = 0, - #[doc = "1: Matching address received"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Am1f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AM1F` reader - Address Match 1 Flag"] -pub type Am1fR = crate::BitReader; -impl Am1fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Am1f { - match self.bits { - false => Am1f::NoFlag, - true => Am1f::Flag, - } - } - #[doc = "Matching address not received"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Am1f::NoFlag - } - #[doc = "Matching address received"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Am1f::Flag - } -} -#[doc = "General Call Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gcf { - #[doc = "0: General call address disabled or not detected"] - NoFlag = 0, - #[doc = "1: General call address detected"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gcf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GCF` reader - General Call Flag"] -pub type GcfR = crate::BitReader; -impl GcfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gcf { - match self.bits { - false => Gcf::NoFlag, - true => Gcf::Flag, - } - } - #[doc = "General call address disabled or not detected"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Gcf::NoFlag - } - #[doc = "General call address detected"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Gcf::Flag - } -} -#[doc = "SMBus Alert Response Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sarf { - #[doc = "0: Disabled or not detected"] - NoFlag = 0, - #[doc = "1: Enabled and detected"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sarf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SARF` reader - SMBus Alert Response Flag"] -pub type SarfR = crate::BitReader; -impl SarfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sarf { - match self.bits { - false => Sarf::NoFlag, - true => Sarf::Flag, - } - } - #[doc = "Disabled or not detected"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Sarf::NoFlag - } - #[doc = "Enabled and detected"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Sarf::Flag - } -} -#[doc = "Target Busy Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sbf { - #[doc = "0: Idle"] - Idle = 0, - #[doc = "1: Busy"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SBF` reader - Target Busy Flag"] -pub type SbfR = crate::BitReader; -impl SbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sbf { - match self.bits { - false => Sbf::Idle, - true => Sbf::Busy, - } - } - #[doc = "Idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Sbf::Idle - } - #[doc = "Busy"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Sbf::Busy - } -} -#[doc = "Bus Busy Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bbf { - #[doc = "0: Idle"] - Idle = 0, - #[doc = "1: Busy"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BBF` reader - Bus Busy Flag"] -pub type BbfR = crate::BitReader; -impl BbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bbf { - match self.bits { - false => Bbf::Idle, - true => Bbf::Busy, - } - } - #[doc = "Idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Bbf::Idle - } - #[doc = "Busy"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Bbf::Busy - } -} -impl R { - #[doc = "Bit 0 - Transmit Data Flag"] - #[inline(always)] - pub fn tdf(&self) -> TdfR { - TdfR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data Flag"] - #[inline(always)] - pub fn rdf(&self) -> RdfR { - RdfR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Address Valid Flag"] - #[inline(always)] - pub fn avf(&self) -> AvfR { - AvfR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Transmit ACK Flag"] - #[inline(always)] - pub fn taf(&self) -> TafR { - TafR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Repeated Start Flag"] - #[inline(always)] - pub fn rsf(&self) -> RsfR { - RsfR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Stop Detect Flag"] - #[inline(always)] - pub fn sdf(&self) -> SdfR { - SdfR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Bit Error Flag"] - #[inline(always)] - pub fn bef(&self) -> BefR { - BefR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - FIFO Error Flag"] - #[inline(always)] - pub fn fef(&self) -> FefR { - FefR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Address Match 0 Flag"] - #[inline(always)] - pub fn am0f(&self) -> Am0fR { - Am0fR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Address Match 1 Flag"] - #[inline(always)] - pub fn am1f(&self) -> Am1fR { - Am1fR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - General Call Flag"] - #[inline(always)] - pub fn gcf(&self) -> GcfR { - GcfR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - SMBus Alert Response Flag"] - #[inline(always)] - pub fn sarf(&self) -> SarfR { - SarfR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 24 - Target Busy Flag"] - #[inline(always)] - pub fn sbf(&self) -> SbfR { - SbfR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Bus Busy Flag"] - #[inline(always)] - pub fn bbf(&self) -> BbfR { - BbfR::new(((self.bits >> 25) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - Repeated Start Flag"] - #[inline(always)] - pub fn rsf(&mut self) -> RsfW { - RsfW::new(self, 8) - } - #[doc = "Bit 9 - Stop Detect Flag"] - #[inline(always)] - pub fn sdf(&mut self) -> SdfW { - SdfW::new(self, 9) - } - #[doc = "Bit 10 - Bit Error Flag"] - #[inline(always)] - pub fn bef(&mut self) -> BefW { - BefW::new(self, 10) - } - #[doc = "Bit 11 - FIFO Error Flag"] - #[inline(always)] - pub fn fef(&mut self) -> FefW { - FefW::new(self, 11) - } -} -#[doc = "Target Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ssr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SsrSpec; -impl crate::RegisterSpec for SsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ssr::R`](R) reader structure"] -impl crate::Readable for SsrSpec {} -#[doc = "`write(|w| ..)` method takes [`ssr::W`](W) writer structure"] -impl crate::Writable for SsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f00; -} -#[doc = "`reset()` method sets SSR to value 0"] -impl crate::Resettable for SsrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/star.rs b/mcxa276-pac/src/lpi2c0/star.rs deleted file mode 100644 index 87c4393d9..000000000 --- a/mcxa276-pac/src/lpi2c0/star.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `STAR` reader"] -pub type R = crate::R; -#[doc = "Register `STAR` writer"] -pub type W = crate::W; -#[doc = "Transmit NACK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txnack { - #[doc = "0: Transmit ACK"] - TransmitAck = 0, - #[doc = "1: Transmit NACK"] - TransmitNack = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txnack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXNACK` reader - Transmit NACK"] -pub type TxnackR = crate::BitReader; -impl TxnackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txnack { - match self.bits { - false => Txnack::TransmitAck, - true => Txnack::TransmitNack, - } - } - #[doc = "Transmit ACK"] - #[inline(always)] - pub fn is_transmit_ack(&self) -> bool { - *self == Txnack::TransmitAck - } - #[doc = "Transmit NACK"] - #[inline(always)] - pub fn is_transmit_nack(&self) -> bool { - *self == Txnack::TransmitNack - } -} -#[doc = "Field `TXNACK` writer - Transmit NACK"] -pub type TxnackW<'a, REG> = crate::BitWriter<'a, REG, Txnack>; -impl<'a, REG> TxnackW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Transmit ACK"] - #[inline(always)] - pub fn transmit_ack(self) -> &'a mut crate::W { - self.variant(Txnack::TransmitAck) - } - #[doc = "Transmit NACK"] - #[inline(always)] - pub fn transmit_nack(self) -> &'a mut crate::W { - self.variant(Txnack::TransmitNack) - } -} -impl R { - #[doc = "Bit 0 - Transmit NACK"] - #[inline(always)] - pub fn txnack(&self) -> TxnackR { - TxnackR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmit NACK"] - #[inline(always)] - pub fn txnack(&mut self) -> TxnackW { - TxnackW::new(self, 0) - } -} -#[doc = "Target Transmit ACK\n\nYou can [`read`](crate::Reg::read) this register and get [`star::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`star::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StarSpec; -impl crate::RegisterSpec for StarSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`star::R`](R) reader structure"] -impl crate::Readable for StarSpec {} -#[doc = "`write(|w| ..)` method takes [`star::W`](W) writer structure"] -impl crate::Writable for StarSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STAR to value 0"] -impl crate::Resettable for StarSpec {} diff --git a/mcxa276-pac/src/lpi2c0/stdr.rs b/mcxa276-pac/src/lpi2c0/stdr.rs deleted file mode 100644 index 588a17440..000000000 --- a/mcxa276-pac/src/lpi2c0/stdr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `STDR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Transmit Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Transmit Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Target Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StdrSpec; -impl crate::RegisterSpec for StdrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`stdr::W`](W) writer structure"] -impl crate::Writable for StdrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STDR to value 0"] -impl crate::Resettable for StdrSpec {} diff --git a/mcxa276-pac/src/lpi2c0/verid.rs b/mcxa276-pac/src/lpi2c0/verid.rs deleted file mode 100644 index 53c7bef0d..000000000 --- a/mcxa276-pac/src/lpi2c0/verid.rs +++ /dev/null @@ -1,76 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "2: Controller only, with standard feature set"] - MasterOnly = 2, - #[doc = "3: Controller and target, with standard feature set"] - MasterAndSlave = 3, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Feature::MasterOnly), - 3 => Some(Feature::MasterAndSlave), - _ => None, - } - } - #[doc = "Controller only, with standard feature set"] - #[inline(always)] - pub fn is_master_only(&self) -> bool { - *self == Feature::MasterOnly - } - #[doc = "Controller and target, with standard feature set"] - #[inline(always)] - pub fn is_master_and_slave(&self) -> bool { - *self == Feature::MasterAndSlave - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0103_0003"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0103_0003; -} diff --git a/mcxa276-pac/src/lpspi0.rs b/mcxa276-pac/src/lpspi0.rs deleted file mode 100644 index 43c548584..000000000 --- a/mcxa276-pac/src/lpspi0.rs +++ /dev/null @@ -1,266 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - _reserved2: [u8; 0x08], - cr: Cr, - sr: Sr, - ier: Ier, - der: Der, - cfgr0: Cfgr0, - cfgr1: Cfgr1, - _reserved8: [u8; 0x08], - dmr0: Dmr0, - dmr1: Dmr1, - _reserved10: [u8; 0x08], - ccr: Ccr, - ccr1: Ccr1, - _reserved12: [u8; 0x10], - fcr: Fcr, - fsr: Fsr, - tcr: Tcr, - tdr: Tdr, - _reserved16: [u8; 0x08], - rsr: Rsr, - rdr: Rdr, - rdror: Rdror, - _reserved19: [u8; 0x0380], - tcbr: Tcbr, - tdbr: [Tdbr; 128], - rdbr: [Rdbr; 128], -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x10 - Control"] - #[inline(always)] - pub const fn cr(&self) -> &Cr { - &self.cr - } - #[doc = "0x14 - Status"] - #[inline(always)] - pub const fn sr(&self) -> &Sr { - &self.sr - } - #[doc = "0x18 - Interrupt Enable"] - #[inline(always)] - pub const fn ier(&self) -> &Ier { - &self.ier - } - #[doc = "0x1c - DMA Enable"] - #[inline(always)] - pub const fn der(&self) -> &Der { - &self.der - } - #[doc = "0x20 - Configuration 0"] - #[inline(always)] - pub const fn cfgr0(&self) -> &Cfgr0 { - &self.cfgr0 - } - #[doc = "0x24 - Configuration 1"] - #[inline(always)] - pub const fn cfgr1(&self) -> &Cfgr1 { - &self.cfgr1 - } - #[doc = "0x30 - Data Match 0"] - #[inline(always)] - pub const fn dmr0(&self) -> &Dmr0 { - &self.dmr0 - } - #[doc = "0x34 - Data Match 1"] - #[inline(always)] - pub const fn dmr1(&self) -> &Dmr1 { - &self.dmr1 - } - #[doc = "0x40 - Clock Configuration"] - #[inline(always)] - pub const fn ccr(&self) -> &Ccr { - &self.ccr - } - #[doc = "0x44 - Clock Configuration 1"] - #[inline(always)] - pub const fn ccr1(&self) -> &Ccr1 { - &self.ccr1 - } - #[doc = "0x58 - FIFO Control"] - #[inline(always)] - pub const fn fcr(&self) -> &Fcr { - &self.fcr - } - #[doc = "0x5c - FIFO Status"] - #[inline(always)] - pub const fn fsr(&self) -> &Fsr { - &self.fsr - } - #[doc = "0x60 - Transmit Command"] - #[inline(always)] - pub const fn tcr(&self) -> &Tcr { - &self.tcr - } - #[doc = "0x64 - Transmit Data"] - #[inline(always)] - pub const fn tdr(&self) -> &Tdr { - &self.tdr - } - #[doc = "0x70 - Receive Status"] - #[inline(always)] - pub const fn rsr(&self) -> &Rsr { - &self.rsr - } - #[doc = "0x74 - Receive Data"] - #[inline(always)] - pub const fn rdr(&self) -> &Rdr { - &self.rdr - } - #[doc = "0x78 - Receive Data Read Only"] - #[inline(always)] - pub const fn rdror(&self) -> &Rdror { - &self.rdror - } - #[doc = "0x3fc - Transmit Command Burst"] - #[inline(always)] - pub const fn tcbr(&self) -> &Tcbr { - &self.tcbr - } - #[doc = "0x400..0x600 - Transmit Data Burst"] - #[inline(always)] - pub const fn tdbr(&self, n: usize) -> &Tdbr { - &self.tdbr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x400..0x600 - Transmit Data Burst"] - #[inline(always)] - pub fn tdbr_iter(&self) -> impl Iterator { - self.tdbr.iter() - } - #[doc = "0x600..0x800 - Receive Data Burst"] - #[inline(always)] - pub const fn rdbr(&self, n: usize) -> &Rdbr { - &self.rdbr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x600..0x800 - Receive Data Burst"] - #[inline(always)] - pub fn rdbr_iter(&self) -> impl Iterator { - self.rdbr.iter() - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "CR (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] -#[doc(alias = "CR")] -pub type Cr = crate::Reg; -#[doc = "Control"] -pub mod cr; -#[doc = "SR (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] -#[doc(alias = "SR")] -pub type Sr = crate::Reg; -#[doc = "Status"] -pub mod sr; -#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] -#[doc(alias = "IER")] -pub type Ier = crate::Reg; -#[doc = "Interrupt Enable"] -pub mod ier; -#[doc = "DER (rw) register accessor: DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@der`] module"] -#[doc(alias = "DER")] -pub type Der = crate::Reg; -#[doc = "DMA Enable"] -pub mod der; -#[doc = "CFGR0 (rw) register accessor: Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr0`] module"] -#[doc(alias = "CFGR0")] -pub type Cfgr0 = crate::Reg; -#[doc = "Configuration 0"] -pub mod cfgr0; -#[doc = "CFGR1 (rw) register accessor: Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr1`] module"] -#[doc(alias = "CFGR1")] -pub type Cfgr1 = crate::Reg; -#[doc = "Configuration 1"] -pub mod cfgr1; -#[doc = "DMR0 (rw) register accessor: Data Match 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmr0`] module"] -#[doc(alias = "DMR0")] -pub type Dmr0 = crate::Reg; -#[doc = "Data Match 0"] -pub mod dmr0; -#[doc = "DMR1 (rw) register accessor: Data Match 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmr1`] module"] -#[doc(alias = "DMR1")] -pub type Dmr1 = crate::Reg; -#[doc = "Data Match 1"] -pub mod dmr1; -#[doc = "CCR (rw) register accessor: Clock Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`] module"] -#[doc(alias = "CCR")] -pub type Ccr = crate::Reg; -#[doc = "Clock Configuration"] -pub mod ccr; -#[doc = "CCR1 (rw) register accessor: Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`] module"] -#[doc(alias = "CCR1")] -pub type Ccr1 = crate::Reg; -#[doc = "Clock Configuration 1"] -pub mod ccr1; -#[doc = "FCR (rw) register accessor: FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] -#[doc(alias = "FCR")] -pub type Fcr = crate::Reg; -#[doc = "FIFO Control"] -pub mod fcr; -#[doc = "FSR (r) register accessor: FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsr`] module"] -#[doc(alias = "FSR")] -pub type Fsr = crate::Reg; -#[doc = "FIFO Status"] -pub mod fsr; -#[doc = "TCR (rw) register accessor: Transmit Command\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] -#[doc(alias = "TCR")] -pub type Tcr = crate::Reg; -#[doc = "Transmit Command"] -pub mod tcr; -#[doc = "TDR (w) register accessor: Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`] module"] -#[doc(alias = "TDR")] -pub type Tdr = crate::Reg; -#[doc = "Transmit Data"] -pub mod tdr; -#[doc = "RSR (r) register accessor: Receive Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsr`] module"] -#[doc(alias = "RSR")] -pub type Rsr = crate::Reg; -#[doc = "Receive Status"] -pub mod rsr; -#[doc = "RDR (r) register accessor: Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`rdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdr`] module"] -#[doc(alias = "RDR")] -pub type Rdr = crate::Reg; -#[doc = "Receive Data"] -pub mod rdr; -#[doc = "RDROR (r) register accessor: Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`rdror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdror`] module"] -#[doc(alias = "RDROR")] -pub type Rdror = crate::Reg; -#[doc = "Receive Data Read Only"] -pub mod rdror; -#[doc = "TCBR (w) register accessor: Transmit Command Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcbr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcbr`] module"] -#[doc(alias = "TCBR")] -pub type Tcbr = crate::Reg; -#[doc = "Transmit Command Burst"] -pub mod tcbr; -#[doc = "TDBR (w) register accessor: Transmit Data Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdbr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdbr`] module"] -#[doc(alias = "TDBR")] -pub type Tdbr = crate::Reg; -#[doc = "Transmit Data Burst"] -pub mod tdbr; -#[doc = "RDBR (r) register accessor: Receive Data Burst\n\nYou can [`read`](crate::Reg::read) this register and get [`rdbr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdbr`] module"] -#[doc(alias = "RDBR")] -pub type Rdbr = crate::Reg; -#[doc = "Receive Data Burst"] -pub mod rdbr; diff --git a/mcxa276-pac/src/lpspi0/ccr.rs b/mcxa276-pac/src/lpspi0/ccr.rs deleted file mode 100644 index 16490c8af..000000000 --- a/mcxa276-pac/src/lpspi0/ccr.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `CCR` reader"] -pub type R = crate::R; -#[doc = "Register `CCR` writer"] -pub type W = crate::W; -#[doc = "Field `SCKDIV` reader - SCK Divider"] -pub type SckdivR = crate::FieldReader; -#[doc = "Field `SCKDIV` writer - SCK Divider"] -pub type SckdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DBT` reader - Delay Between Transfers"] -pub type DbtR = crate::FieldReader; -#[doc = "Field `DBT` writer - Delay Between Transfers"] -pub type DbtW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `PCSSCK` reader - PCS-to-SCK Delay"] -pub type PcssckR = crate::FieldReader; -#[doc = "Field `PCSSCK` writer - PCS-to-SCK Delay"] -pub type PcssckW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `SCKPCS` reader - SCK-to-PCS Delay"] -pub type SckpcsR = crate::FieldReader; -#[doc = "Field `SCKPCS` writer - SCK-to-PCS Delay"] -pub type SckpcsW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - SCK Divider"] - #[inline(always)] - pub fn sckdiv(&self) -> SckdivR { - SckdivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Delay Between Transfers"] - #[inline(always)] - pub fn dbt(&self) -> DbtR { - DbtR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - PCS-to-SCK Delay"] - #[inline(always)] - pub fn pcssck(&self) -> PcssckR { - PcssckR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - SCK-to-PCS Delay"] - #[inline(always)] - pub fn sckpcs(&self) -> SckpcsR { - SckpcsR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - SCK Divider"] - #[inline(always)] - pub fn sckdiv(&mut self) -> SckdivW { - SckdivW::new(self, 0) - } - #[doc = "Bits 8:15 - Delay Between Transfers"] - #[inline(always)] - pub fn dbt(&mut self) -> DbtW { - DbtW::new(self, 8) - } - #[doc = "Bits 16:23 - PCS-to-SCK Delay"] - #[inline(always)] - pub fn pcssck(&mut self) -> PcssckW { - PcssckW::new(self, 16) - } - #[doc = "Bits 24:31 - SCK-to-PCS Delay"] - #[inline(always)] - pub fn sckpcs(&mut self) -> SckpcsW { - SckpcsW::new(self, 24) - } -} -#[doc = "Clock Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CcrSpec; -impl crate::RegisterSpec for CcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] -impl crate::Readable for CcrSpec {} -#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] -impl crate::Writable for CcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CCR to value 0"] -impl crate::Resettable for CcrSpec {} diff --git a/mcxa276-pac/src/lpspi0/ccr1.rs b/mcxa276-pac/src/lpspi0/ccr1.rs deleted file mode 100644 index f56d82e74..000000000 --- a/mcxa276-pac/src/lpspi0/ccr1.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `CCR1` reader"] -pub type R = crate::R; -#[doc = "Register `CCR1` writer"] -pub type W = crate::W; -#[doc = "Field `SCKSET` reader - SCK Setup"] -pub type ScksetR = crate::FieldReader; -#[doc = "Field `SCKSET` writer - SCK Setup"] -pub type ScksetW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `SCKHLD` reader - SCK Hold"] -pub type SckhldR = crate::FieldReader; -#[doc = "Field `SCKHLD` writer - SCK Hold"] -pub type SckhldW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `PCSPCS` reader - PCS to PCS Delay"] -pub type PcspcsR = crate::FieldReader; -#[doc = "Field `PCSPCS` writer - PCS to PCS Delay"] -pub type PcspcsW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `SCKSCK` reader - SCK Inter-Frame Delay"] -pub type ScksckR = crate::FieldReader; -#[doc = "Field `SCKSCK` writer - SCK Inter-Frame Delay"] -pub type ScksckW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - SCK Setup"] - #[inline(always)] - pub fn sckset(&self) -> ScksetR { - ScksetR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - SCK Hold"] - #[inline(always)] - pub fn sckhld(&self) -> SckhldR { - SckhldR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - PCS to PCS Delay"] - #[inline(always)] - pub fn pcspcs(&self) -> PcspcsR { - PcspcsR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - SCK Inter-Frame Delay"] - #[inline(always)] - pub fn scksck(&self) -> ScksckR { - ScksckR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - SCK Setup"] - #[inline(always)] - pub fn sckset(&mut self) -> ScksetW { - ScksetW::new(self, 0) - } - #[doc = "Bits 8:15 - SCK Hold"] - #[inline(always)] - pub fn sckhld(&mut self) -> SckhldW { - SckhldW::new(self, 8) - } - #[doc = "Bits 16:23 - PCS to PCS Delay"] - #[inline(always)] - pub fn pcspcs(&mut self) -> PcspcsW { - PcspcsW::new(self, 16) - } - #[doc = "Bits 24:31 - SCK Inter-Frame Delay"] - #[inline(always)] - pub fn scksck(&mut self) -> ScksckW { - ScksckW::new(self, 24) - } -} -#[doc = "Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ccr1Spec; -impl crate::RegisterSpec for Ccr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"] -impl crate::Readable for Ccr1Spec {} -#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"] -impl crate::Writable for Ccr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CCR1 to value 0"] -impl crate::Resettable for Ccr1Spec {} diff --git a/mcxa276-pac/src/lpspi0/cfgr0.rs b/mcxa276-pac/src/lpspi0/cfgr0.rs deleted file mode 100644 index 8be5e6102..000000000 --- a/mcxa276-pac/src/lpspi0/cfgr0.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `CFGR0` reader"] -pub type R = crate::R; -#[doc = "Register `CFGR0` writer"] -pub type W = crate::W; -#[doc = "Host Request Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hren { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HREN` reader - Host Request Enable"] -pub type HrenR = crate::BitReader; -impl HrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hren { - match self.bits { - false => Hren::Disable, - true => Hren::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Hren::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Hren::Enable - } -} -#[doc = "Field `HREN` writer - Host Request Enable"] -pub type HrenW<'a, REG> = crate::BitWriter<'a, REG, Hren>; -impl<'a, REG> HrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Hren::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Hren::Enable) - } -} -#[doc = "Host Request Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hrpol { - #[doc = "0: Active high"] - Disabled = 0, - #[doc = "1: Active low"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hrpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HRPOL` reader - Host Request Polarity"] -pub type HrpolR = crate::BitReader; -impl HrpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hrpol { - match self.bits { - false => Hrpol::Disabled, - true => Hrpol::Enabled, - } - } - #[doc = "Active high"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Hrpol::Disabled - } - #[doc = "Active low"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Hrpol::Enabled - } -} -#[doc = "Field `HRPOL` writer - Host Request Polarity"] -pub type HrpolW<'a, REG> = crate::BitWriter<'a, REG, Hrpol>; -impl<'a, REG> HrpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active high"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Hrpol::Disabled) - } - #[doc = "Active low"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Hrpol::Enabled) - } -} -#[doc = "Host Request Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hrsel { - #[doc = "0: HREQ pin"] - Hreqpin = 0, - #[doc = "1: Input trigger"] - InputTrigger = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hrsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HRSEL` reader - Host Request Select"] -pub type HrselR = crate::BitReader; -impl HrselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hrsel { - match self.bits { - false => Hrsel::Hreqpin, - true => Hrsel::InputTrigger, - } - } - #[doc = "HREQ pin"] - #[inline(always)] - pub fn is_hreqpin(&self) -> bool { - *self == Hrsel::Hreqpin - } - #[doc = "Input trigger"] - #[inline(always)] - pub fn is_input_trigger(&self) -> bool { - *self == Hrsel::InputTrigger - } -} -#[doc = "Field `HRSEL` writer - Host Request Select"] -pub type HrselW<'a, REG> = crate::BitWriter<'a, REG, Hrsel>; -impl<'a, REG> HrselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "HREQ pin"] - #[inline(always)] - pub fn hreqpin(self) -> &'a mut crate::W { - self.variant(Hrsel::Hreqpin) - } - #[doc = "Input trigger"] - #[inline(always)] - pub fn input_trigger(self) -> &'a mut crate::W { - self.variant(Hrsel::InputTrigger) - } -} -#[doc = "Host Request Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hrdir { - #[doc = "0: Input"] - Input = 0, - #[doc = "1: Output"] - Output = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hrdir) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HRDIR` reader - Host Request Direction"] -pub type HrdirR = crate::BitReader; -impl HrdirR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hrdir { - match self.bits { - false => Hrdir::Input, - true => Hrdir::Output, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_input(&self) -> bool { - *self == Hrdir::Input - } - #[doc = "Output"] - #[inline(always)] - pub fn is_output(&self) -> bool { - *self == Hrdir::Output - } -} -#[doc = "Field `HRDIR` writer - Host Request Direction"] -pub type HrdirW<'a, REG> = crate::BitWriter<'a, REG, Hrdir>; -impl<'a, REG> HrdirW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn input(self) -> &'a mut crate::W { - self.variant(Hrdir::Input) - } - #[doc = "Output"] - #[inline(always)] - pub fn output(self) -> &'a mut crate::W { - self.variant(Hrdir::Output) - } -} -#[doc = "Circular FIFO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cirfifo { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cirfifo) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CIRFIFO` reader - Circular FIFO Enable"] -pub type CirfifoR = crate::BitReader; -impl CirfifoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cirfifo { - match self.bits { - false => Cirfifo::Disable, - true => Cirfifo::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Cirfifo::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Cirfifo::Enable - } -} -#[doc = "Field `CIRFIFO` writer - Circular FIFO Enable"] -pub type CirfifoW<'a, REG> = crate::BitWriter<'a, REG, Cirfifo>; -impl<'a, REG> CirfifoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Cirfifo::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Cirfifo::Enable) - } -} -#[doc = "Receive Data Match Only\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdmo { - #[doc = "0: Disable"] - Stored = 0, - #[doc = "1: Enable"] - Discarded = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdmo) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDMO` reader - Receive Data Match Only"] -pub type RdmoR = crate::BitReader; -impl RdmoR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdmo { - match self.bits { - false => Rdmo::Stored, - true => Rdmo::Discarded, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_stored(&self) -> bool { - *self == Rdmo::Stored - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_discarded(&self) -> bool { - *self == Rdmo::Discarded - } -} -#[doc = "Field `RDMO` writer - Receive Data Match Only"] -pub type RdmoW<'a, REG> = crate::BitWriter<'a, REG, Rdmo>; -impl<'a, REG> RdmoW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn stored(self) -> &'a mut crate::W { - self.variant(Rdmo::Stored) - } - #[doc = "Enable"] - #[inline(always)] - pub fn discarded(self) -> &'a mut crate::W { - self.variant(Rdmo::Discarded) - } -} -impl R { - #[doc = "Bit 0 - Host Request Enable"] - #[inline(always)] - pub fn hren(&self) -> HrenR { - HrenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Host Request Polarity"] - #[inline(always)] - pub fn hrpol(&self) -> HrpolR { - HrpolR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Host Request Select"] - #[inline(always)] - pub fn hrsel(&self) -> HrselR { - HrselR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Host Request Direction"] - #[inline(always)] - pub fn hrdir(&self) -> HrdirR { - HrdirR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Circular FIFO Enable"] - #[inline(always)] - pub fn cirfifo(&self) -> CirfifoR { - CirfifoR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Receive Data Match Only"] - #[inline(always)] - pub fn rdmo(&self) -> RdmoR { - RdmoR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Host Request Enable"] - #[inline(always)] - pub fn hren(&mut self) -> HrenW { - HrenW::new(self, 0) - } - #[doc = "Bit 1 - Host Request Polarity"] - #[inline(always)] - pub fn hrpol(&mut self) -> HrpolW { - HrpolW::new(self, 1) - } - #[doc = "Bit 2 - Host Request Select"] - #[inline(always)] - pub fn hrsel(&mut self) -> HrselW { - HrselW::new(self, 2) - } - #[doc = "Bit 3 - Host Request Direction"] - #[inline(always)] - pub fn hrdir(&mut self) -> HrdirW { - HrdirW::new(self, 3) - } - #[doc = "Bit 8 - Circular FIFO Enable"] - #[inline(always)] - pub fn cirfifo(&mut self) -> CirfifoW { - CirfifoW::new(self, 8) - } - #[doc = "Bit 9 - Receive Data Match Only"] - #[inline(always)] - pub fn rdmo(&mut self) -> RdmoW { - RdmoW::new(self, 9) - } -} -#[doc = "Configuration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cfgr0Spec; -impl crate::RegisterSpec for Cfgr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cfgr0::R`](R) reader structure"] -impl crate::Readable for Cfgr0Spec {} -#[doc = "`write(|w| ..)` method takes [`cfgr0::W`](W) writer structure"] -impl crate::Writable for Cfgr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CFGR0 to value 0"] -impl crate::Resettable for Cfgr0Spec {} diff --git a/mcxa276-pac/src/lpspi0/cfgr1.rs b/mcxa276-pac/src/lpspi0/cfgr1.rs deleted file mode 100644 index c3a2bc79f..000000000 --- a/mcxa276-pac/src/lpspi0/cfgr1.rs +++ /dev/null @@ -1,763 +0,0 @@ -#[doc = "Register `CFGR1` reader"] -pub type R = crate::R; -#[doc = "Register `CFGR1` writer"] -pub type W = crate::W; -#[doc = "Controller Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Master { - #[doc = "0: Peripheral mode"] - SlaveMode = 0, - #[doc = "1: Controller mode"] - MasterMode = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Master) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MASTER` reader - Controller Mode"] -pub type MasterR = crate::BitReader; -impl MasterR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Master { - match self.bits { - false => Master::SlaveMode, - true => Master::MasterMode, - } - } - #[doc = "Peripheral mode"] - #[inline(always)] - pub fn is_slave_mode(&self) -> bool { - *self == Master::SlaveMode - } - #[doc = "Controller mode"] - #[inline(always)] - pub fn is_master_mode(&self) -> bool { - *self == Master::MasterMode - } -} -#[doc = "Field `MASTER` writer - Controller Mode"] -pub type MasterW<'a, REG> = crate::BitWriter<'a, REG, Master>; -impl<'a, REG> MasterW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral mode"] - #[inline(always)] - pub fn slave_mode(self) -> &'a mut crate::W { - self.variant(Master::SlaveMode) - } - #[doc = "Controller mode"] - #[inline(always)] - pub fn master_mode(self) -> &'a mut crate::W { - self.variant(Master::MasterMode) - } -} -#[doc = "Sample Point\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sample { - #[doc = "0: SCK edge"] - OnSckEdge = 0, - #[doc = "1: Delayed SCK edge"] - OnDelayedSckEdge = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sample) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SAMPLE` reader - Sample Point"] -pub type SampleR = crate::BitReader; -impl SampleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sample { - match self.bits { - false => Sample::OnSckEdge, - true => Sample::OnDelayedSckEdge, - } - } - #[doc = "SCK edge"] - #[inline(always)] - pub fn is_on_sck_edge(&self) -> bool { - *self == Sample::OnSckEdge - } - #[doc = "Delayed SCK edge"] - #[inline(always)] - pub fn is_on_delayed_sck_edge(&self) -> bool { - *self == Sample::OnDelayedSckEdge - } -} -#[doc = "Field `SAMPLE` writer - Sample Point"] -pub type SampleW<'a, REG> = crate::BitWriter<'a, REG, Sample>; -impl<'a, REG> SampleW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SCK edge"] - #[inline(always)] - pub fn on_sck_edge(self) -> &'a mut crate::W { - self.variant(Sample::OnSckEdge) - } - #[doc = "Delayed SCK edge"] - #[inline(always)] - pub fn on_delayed_sck_edge(self) -> &'a mut crate::W { - self.variant(Sample::OnDelayedSckEdge) - } -} -#[doc = "Automatic PCS\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Autopcs { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Autopcs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AUTOPCS` reader - Automatic PCS"] -pub type AutopcsR = crate::BitReader; -impl AutopcsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Autopcs { - match self.bits { - false => Autopcs::Disabled, - true => Autopcs::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Autopcs::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Autopcs::Enabled - } -} -#[doc = "Field `AUTOPCS` writer - Automatic PCS"] -pub type AutopcsW<'a, REG> = crate::BitWriter<'a, REG, Autopcs>; -impl<'a, REG> AutopcsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Autopcs::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Autopcs::Enabled) - } -} -#[doc = "No Stall\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nostall { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nostall) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOSTALL` reader - No Stall"] -pub type NostallR = crate::BitReader; -impl NostallR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nostall { - match self.bits { - false => Nostall::Disable, - true => Nostall::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Nostall::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Nostall::Enable - } -} -#[doc = "Field `NOSTALL` writer - No Stall"] -pub type NostallW<'a, REG> = crate::BitWriter<'a, REG, Nostall>; -impl<'a, REG> NostallW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Nostall::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Nostall::Enable) - } -} -#[doc = "Partial Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Partial { - #[doc = "0: Discard"] - Discarded = 0, - #[doc = "1: Store"] - Stored = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Partial) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PARTIAL` reader - Partial Enable"] -pub type PartialR = crate::BitReader; -impl PartialR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Partial { - match self.bits { - false => Partial::Discarded, - true => Partial::Stored, - } - } - #[doc = "Discard"] - #[inline(always)] - pub fn is_discarded(&self) -> bool { - *self == Partial::Discarded - } - #[doc = "Store"] - #[inline(always)] - pub fn is_stored(&self) -> bool { - *self == Partial::Stored - } -} -#[doc = "Field `PARTIAL` writer - Partial Enable"] -pub type PartialW<'a, REG> = crate::BitWriter<'a, REG, Partial>; -impl<'a, REG> PartialW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Discard"] - #[inline(always)] - pub fn discarded(self) -> &'a mut crate::W { - self.variant(Partial::Discarded) - } - #[doc = "Store"] - #[inline(always)] - pub fn stored(self) -> &'a mut crate::W { - self.variant(Partial::Stored) - } -} -#[doc = "Peripheral Chip Select Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pcspol { - #[doc = "0: Active low"] - Discarded = 0, - #[doc = "1: Active high"] - Stored = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pcspol) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pcspol { - type Ux = u8; -} -impl crate::IsEnum for Pcspol {} -#[doc = "Field `PCSPOL` reader - Peripheral Chip Select Polarity"] -pub type PcspolR = crate::FieldReader; -impl PcspolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Pcspol::Discarded), - 1 => Some(Pcspol::Stored), - _ => None, - } - } - #[doc = "Active low"] - #[inline(always)] - pub fn is_discarded(&self) -> bool { - *self == Pcspol::Discarded - } - #[doc = "Active high"] - #[inline(always)] - pub fn is_stored(&self) -> bool { - *self == Pcspol::Stored - } -} -#[doc = "Field `PCSPOL` writer - Peripheral Chip Select Polarity"] -pub type PcspolW<'a, REG> = crate::FieldWriter<'a, REG, 4, Pcspol>; -impl<'a, REG> PcspolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Active low"] - #[inline(always)] - pub fn discarded(self) -> &'a mut crate::W { - self.variant(Pcspol::Discarded) - } - #[doc = "Active high"] - #[inline(always)] - pub fn stored(self) -> &'a mut crate::W { - self.variant(Pcspol::Stored) - } -} -#[doc = "Match Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Matcfg { - #[doc = "0: Match is disabled"] - Disabled = 0, - #[doc = "2: Match first data word with compare word"] - EnabledFirstdatamatch = 2, - #[doc = "3: Match any data word with compare word"] - EnabledAnydatamatch = 3, - #[doc = "4: Sequential match, first data word"] - EnabledDatamatch100 = 4, - #[doc = "5: Sequential match, any data word"] - EnabledDatamatch101 = 5, - #[doc = "6: Match first data word (masked) with compare word (masked)"] - EnabledDatamatch110 = 6, - #[doc = "7: Match any data word (masked) with compare word (masked)"] - EnabledDatamatch111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Matcfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Matcfg { - type Ux = u8; -} -impl crate::IsEnum for Matcfg {} -#[doc = "Field `MATCFG` reader - Match Configuration"] -pub type MatcfgR = crate::FieldReader; -impl MatcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Matcfg::Disabled), - 2 => Some(Matcfg::EnabledFirstdatamatch), - 3 => Some(Matcfg::EnabledAnydatamatch), - 4 => Some(Matcfg::EnabledDatamatch100), - 5 => Some(Matcfg::EnabledDatamatch101), - 6 => Some(Matcfg::EnabledDatamatch110), - 7 => Some(Matcfg::EnabledDatamatch111), - _ => None, - } - } - #[doc = "Match is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Matcfg::Disabled - } - #[doc = "Match first data word with compare word"] - #[inline(always)] - pub fn is_enabled_firstdatamatch(&self) -> bool { - *self == Matcfg::EnabledFirstdatamatch - } - #[doc = "Match any data word with compare word"] - #[inline(always)] - pub fn is_enabled_anydatamatch(&self) -> bool { - *self == Matcfg::EnabledAnydatamatch - } - #[doc = "Sequential match, first data word"] - #[inline(always)] - pub fn is_enabled_datamatch_100(&self) -> bool { - *self == Matcfg::EnabledDatamatch100 - } - #[doc = "Sequential match, any data word"] - #[inline(always)] - pub fn is_enabled_datamatch_101(&self) -> bool { - *self == Matcfg::EnabledDatamatch101 - } - #[doc = "Match first data word (masked) with compare word (masked)"] - #[inline(always)] - pub fn is_enabled_datamatch_110(&self) -> bool { - *self == Matcfg::EnabledDatamatch110 - } - #[doc = "Match any data word (masked) with compare word (masked)"] - #[inline(always)] - pub fn is_enabled_datamatch_111(&self) -> bool { - *self == Matcfg::EnabledDatamatch111 - } -} -#[doc = "Field `MATCFG` writer - Match Configuration"] -pub type MatcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Matcfg>; -impl<'a, REG> MatcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Match is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Matcfg::Disabled) - } - #[doc = "Match first data word with compare word"] - #[inline(always)] - pub fn enabled_firstdatamatch(self) -> &'a mut crate::W { - self.variant(Matcfg::EnabledFirstdatamatch) - } - #[doc = "Match any data word with compare word"] - #[inline(always)] - pub fn enabled_anydatamatch(self) -> &'a mut crate::W { - self.variant(Matcfg::EnabledAnydatamatch) - } - #[doc = "Sequential match, first data word"] - #[inline(always)] - pub fn enabled_datamatch_100(self) -> &'a mut crate::W { - self.variant(Matcfg::EnabledDatamatch100) - } - #[doc = "Sequential match, any data word"] - #[inline(always)] - pub fn enabled_datamatch_101(self) -> &'a mut crate::W { - self.variant(Matcfg::EnabledDatamatch101) - } - #[doc = "Match first data word (masked) with compare word (masked)"] - #[inline(always)] - pub fn enabled_datamatch_110(self) -> &'a mut crate::W { - self.variant(Matcfg::EnabledDatamatch110) - } - #[doc = "Match any data word (masked) with compare word (masked)"] - #[inline(always)] - pub fn enabled_datamatch_111(self) -> &'a mut crate::W { - self.variant(Matcfg::EnabledDatamatch111) - } -} -#[doc = "Pin Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pincfg { - #[doc = "0: SIN is used for input data; SOUT is used for output data"] - SinInSoutOut = 0, - #[doc = "1: SIN is used for both input and output data; only half-duplex serial transfers are supported"] - SinBothInOut = 1, - #[doc = "2: SOUT is used for both input and output data; only half-duplex serial transfers are supported"] - SoutBothInOut = 2, - #[doc = "3: SOUT is used for input data; SIN is used for output data"] - SoutInSinOut = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pincfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pincfg { - type Ux = u8; -} -impl crate::IsEnum for Pincfg {} -#[doc = "Field `PINCFG` reader - Pin Configuration"] -pub type PincfgR = crate::FieldReader; -impl PincfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pincfg { - match self.bits { - 0 => Pincfg::SinInSoutOut, - 1 => Pincfg::SinBothInOut, - 2 => Pincfg::SoutBothInOut, - 3 => Pincfg::SoutInSinOut, - _ => unreachable!(), - } - } - #[doc = "SIN is used for input data; SOUT is used for output data"] - #[inline(always)] - pub fn is_sin_in_sout_out(&self) -> bool { - *self == Pincfg::SinInSoutOut - } - #[doc = "SIN is used for both input and output data; only half-duplex serial transfers are supported"] - #[inline(always)] - pub fn is_sin_both_in_out(&self) -> bool { - *self == Pincfg::SinBothInOut - } - #[doc = "SOUT is used for both input and output data; only half-duplex serial transfers are supported"] - #[inline(always)] - pub fn is_sout_both_in_out(&self) -> bool { - *self == Pincfg::SoutBothInOut - } - #[doc = "SOUT is used for input data; SIN is used for output data"] - #[inline(always)] - pub fn is_sout_in_sin_out(&self) -> bool { - *self == Pincfg::SoutInSinOut - } -} -#[doc = "Field `PINCFG` writer - Pin Configuration"] -pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pincfg, crate::Safe>; -impl<'a, REG> PincfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "SIN is used for input data; SOUT is used for output data"] - #[inline(always)] - pub fn sin_in_sout_out(self) -> &'a mut crate::W { - self.variant(Pincfg::SinInSoutOut) - } - #[doc = "SIN is used for both input and output data; only half-duplex serial transfers are supported"] - #[inline(always)] - pub fn sin_both_in_out(self) -> &'a mut crate::W { - self.variant(Pincfg::SinBothInOut) - } - #[doc = "SOUT is used for both input and output data; only half-duplex serial transfers are supported"] - #[inline(always)] - pub fn sout_both_in_out(self) -> &'a mut crate::W { - self.variant(Pincfg::SoutBothInOut) - } - #[doc = "SOUT is used for input data; SIN is used for output data"] - #[inline(always)] - pub fn sout_in_sin_out(self) -> &'a mut crate::W { - self.variant(Pincfg::SoutInSinOut) - } -} -#[doc = "Output Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Outcfg { - #[doc = "0: Retain last value"] - RetainLastvalue = 0, - #[doc = "1: 3-stated"] - Tristated = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Outcfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OUTCFG` reader - Output Configuration"] -pub type OutcfgR = crate::BitReader; -impl OutcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Outcfg { - match self.bits { - false => Outcfg::RetainLastvalue, - true => Outcfg::Tristated, - } - } - #[doc = "Retain last value"] - #[inline(always)] - pub fn is_retain_lastvalue(&self) -> bool { - *self == Outcfg::RetainLastvalue - } - #[doc = "3-stated"] - #[inline(always)] - pub fn is_tristated(&self) -> bool { - *self == Outcfg::Tristated - } -} -#[doc = "Field `OUTCFG` writer - Output Configuration"] -pub type OutcfgW<'a, REG> = crate::BitWriter<'a, REG, Outcfg>; -impl<'a, REG> OutcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Retain last value"] - #[inline(always)] - pub fn retain_lastvalue(self) -> &'a mut crate::W { - self.variant(Outcfg::RetainLastvalue) - } - #[doc = "3-stated"] - #[inline(always)] - pub fn tristated(self) -> &'a mut crate::W { - self.variant(Outcfg::Tristated) - } -} -#[doc = "Peripheral Chip Select Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pcscfg { - #[doc = "0: PCS\\[3:2\\] configured for chip select function"] - ChipSelect = 0, - #[doc = "1: PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"] - Halfduplex4bit = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pcscfg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PCSCFG` reader - Peripheral Chip Select Configuration"] -pub type PcscfgR = crate::BitReader; -impl PcscfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pcscfg { - match self.bits { - false => Pcscfg::ChipSelect, - true => Pcscfg::Halfduplex4bit, - } - } - #[doc = "PCS\\[3:2\\] configured for chip select function"] - #[inline(always)] - pub fn is_chip_select(&self) -> bool { - *self == Pcscfg::ChipSelect - } - #[doc = "PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"] - #[inline(always)] - pub fn is_halfduplex4bit(&self) -> bool { - *self == Pcscfg::Halfduplex4bit - } -} -#[doc = "Field `PCSCFG` writer - Peripheral Chip Select Configuration"] -pub type PcscfgW<'a, REG> = crate::BitWriter<'a, REG, Pcscfg>; -impl<'a, REG> PcscfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "PCS\\[3:2\\] configured for chip select function"] - #[inline(always)] - pub fn chip_select(self) -> &'a mut crate::W { - self.variant(Pcscfg::ChipSelect) - } - #[doc = "PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"] - #[inline(always)] - pub fn halfduplex4bit(self) -> &'a mut crate::W { - self.variant(Pcscfg::Halfduplex4bit) - } -} -impl R { - #[doc = "Bit 0 - Controller Mode"] - #[inline(always)] - pub fn master(&self) -> MasterR { - MasterR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Sample Point"] - #[inline(always)] - pub fn sample(&self) -> SampleR { - SampleR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Automatic PCS"] - #[inline(always)] - pub fn autopcs(&self) -> AutopcsR { - AutopcsR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - No Stall"] - #[inline(always)] - pub fn nostall(&self) -> NostallR { - NostallR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Partial Enable"] - #[inline(always)] - pub fn partial(&self) -> PartialR { - PartialR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"] - #[inline(always)] - pub fn pcspol(&self) -> PcspolR { - PcspolR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 16:18 - Match Configuration"] - #[inline(always)] - pub fn matcfg(&self) -> MatcfgR { - MatcfgR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:25 - Pin Configuration"] - #[inline(always)] - pub fn pincfg(&self) -> PincfgR { - PincfgR::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bit 26 - Output Configuration"] - #[inline(always)] - pub fn outcfg(&self) -> OutcfgR { - OutcfgR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Peripheral Chip Select Configuration"] - #[inline(always)] - pub fn pcscfg(&self) -> PcscfgR { - PcscfgR::new(((self.bits >> 27) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Controller Mode"] - #[inline(always)] - pub fn master(&mut self) -> MasterW { - MasterW::new(self, 0) - } - #[doc = "Bit 1 - Sample Point"] - #[inline(always)] - pub fn sample(&mut self) -> SampleW { - SampleW::new(self, 1) - } - #[doc = "Bit 2 - Automatic PCS"] - #[inline(always)] - pub fn autopcs(&mut self) -> AutopcsW { - AutopcsW::new(self, 2) - } - #[doc = "Bit 3 - No Stall"] - #[inline(always)] - pub fn nostall(&mut self) -> NostallW { - NostallW::new(self, 3) - } - #[doc = "Bit 4 - Partial Enable"] - #[inline(always)] - pub fn partial(&mut self) -> PartialW { - PartialW::new(self, 4) - } - #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"] - #[inline(always)] - pub fn pcspol(&mut self) -> PcspolW { - PcspolW::new(self, 8) - } - #[doc = "Bits 16:18 - Match Configuration"] - #[inline(always)] - pub fn matcfg(&mut self) -> MatcfgW { - MatcfgW::new(self, 16) - } - #[doc = "Bits 24:25 - Pin Configuration"] - #[inline(always)] - pub fn pincfg(&mut self) -> PincfgW { - PincfgW::new(self, 24) - } - #[doc = "Bit 26 - Output Configuration"] - #[inline(always)] - pub fn outcfg(&mut self) -> OutcfgW { - OutcfgW::new(self, 26) - } - #[doc = "Bit 27 - Peripheral Chip Select Configuration"] - #[inline(always)] - pub fn pcscfg(&mut self) -> PcscfgW { - PcscfgW::new(self, 27) - } -} -#[doc = "Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cfgr1Spec; -impl crate::RegisterSpec for Cfgr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cfgr1::R`](R) reader structure"] -impl crate::Readable for Cfgr1Spec {} -#[doc = "`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure"] -impl crate::Writable for Cfgr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CFGR1 to value 0"] -impl crate::Resettable for Cfgr1Spec {} diff --git a/mcxa276-pac/src/lpspi0/cr.rs b/mcxa276-pac/src/lpspi0/cr.rs deleted file mode 100644 index fc2a9997b..000000000 --- a/mcxa276-pac/src/lpspi0/cr.rs +++ /dev/null @@ -1,282 +0,0 @@ -#[doc = "Register `CR` reader"] -pub type R = crate::R; -#[doc = "Register `CR` writer"] -pub type W = crate::W; -#[doc = "Module Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Men { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Men) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MEN` reader - Module Enable"] -pub type MenR = crate::BitReader; -impl MenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Men { - match self.bits { - false => Men::Disabled, - true => Men::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Men::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Men::Enabled - } -} -#[doc = "Field `MEN` writer - Module Enable"] -pub type MenW<'a, REG> = crate::BitWriter<'a, REG, Men>; -impl<'a, REG> MenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Men::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Men::Enabled) - } -} -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rst { - #[doc = "0: Not reset"] - NotReset = 0, - #[doc = "1: Reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST` reader - Software Reset"] -pub type RstR = crate::BitReader; -impl RstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rst { - match self.bits { - false => Rst::NotReset, - true => Rst::Reset, - } - } - #[doc = "Not reset"] - #[inline(always)] - pub fn is_not_reset(&self) -> bool { - *self == Rst::NotReset - } - #[doc = "Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Rst::Reset - } -} -#[doc = "Field `RST` writer - Software Reset"] -pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; -impl<'a, REG> RstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not reset"] - #[inline(always)] - pub fn not_reset(self) -> &'a mut crate::W { - self.variant(Rst::NotReset) - } - #[doc = "Reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Rst::Reset) - } -} -#[doc = "Debug Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dbgen { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dbgen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DBGEN` reader - Debug Enable"] -pub type DbgenR = crate::BitReader; -impl DbgenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dbgen { - match self.bits { - false => Dbgen::Disabled, - true => Dbgen::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dbgen::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dbgen::Enabled - } -} -#[doc = "Field `DBGEN` writer - Debug Enable"] -pub type DbgenW<'a, REG> = crate::BitWriter<'a, REG, Dbgen>; -impl<'a, REG> DbgenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dbgen::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dbgen::Enabled) - } -} -#[doc = "Reset Transmit FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rtf { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Reset"] - TxfifoRst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rtf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RTF` writer - Reset Transmit FIFO"] -pub type RtfW<'a, REG> = crate::BitWriter<'a, REG, Rtf>; -impl<'a, REG> RtfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rtf::NoEffect) - } - #[doc = "Reset"] - #[inline(always)] - pub fn txfifo_rst(self) -> &'a mut crate::W { - self.variant(Rtf::TxfifoRst) - } -} -#[doc = "Reset Receive FIFO\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rrf { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Reset"] - RxfifoRst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rrf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RRF` writer - Reset Receive FIFO"] -pub type RrfW<'a, REG> = crate::BitWriter<'a, REG, Rrf>; -impl<'a, REG> RrfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rrf::NoEffect) - } - #[doc = "Reset"] - #[inline(always)] - pub fn rxfifo_rst(self) -> &'a mut crate::W { - self.variant(Rrf::RxfifoRst) - } -} -impl R { - #[doc = "Bit 0 - Module Enable"] - #[inline(always)] - pub fn men(&self) -> MenR { - MenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&self) -> RstR { - RstR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&self) -> DbgenR { - DbgenR::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Module Enable"] - #[inline(always)] - pub fn men(&mut self) -> MenW { - MenW::new(self, 0) - } - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&mut self) -> RstW { - RstW::new(self, 1) - } - #[doc = "Bit 3 - Debug Enable"] - #[inline(always)] - pub fn dbgen(&mut self) -> DbgenW { - DbgenW::new(self, 3) - } - #[doc = "Bit 8 - Reset Transmit FIFO"] - #[inline(always)] - pub fn rtf(&mut self) -> RtfW { - RtfW::new(self, 8) - } - #[doc = "Bit 9 - Reset Receive FIFO"] - #[inline(always)] - pub fn rrf(&mut self) -> RrfW { - RrfW::new(self, 9) - } -} -#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CrSpec; -impl crate::RegisterSpec for CrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cr::R`](R) reader structure"] -impl crate::Readable for CrSpec {} -#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] -impl crate::Writable for CrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CR to value 0"] -impl crate::Resettable for CrSpec {} diff --git a/mcxa276-pac/src/lpspi0/der.rs b/mcxa276-pac/src/lpspi0/der.rs deleted file mode 100644 index caee3b120..000000000 --- a/mcxa276-pac/src/lpspi0/der.rs +++ /dev/null @@ -1,210 +0,0 @@ -#[doc = "Register `DER` reader"] -pub type R = crate::R; -#[doc = "Register `DER` writer"] -pub type W = crate::W; -#[doc = "Transmit Data DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDDE` reader - Transmit Data DMA Enable"] -pub type TddeR = crate::BitReader; -impl TddeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdde { - match self.bits { - false => Tdde::Disable, - true => Tdde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tdde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tdde::Enable - } -} -#[doc = "Field `TDDE` writer - Transmit Data DMA Enable"] -pub type TddeW<'a, REG> = crate::BitWriter<'a, REG, Tdde>; -impl<'a, REG> TddeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tdde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tdde::Enable) - } -} -#[doc = "Receive Data DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDDE` reader - Receive Data DMA Enable"] -pub type RddeR = crate::BitReader; -impl RddeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdde { - match self.bits { - false => Rdde::Disable, - true => Rdde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Rdde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Rdde::Enable - } -} -#[doc = "Field `RDDE` writer - Receive Data DMA Enable"] -pub type RddeW<'a, REG> = crate::BitWriter<'a, REG, Rdde>; -impl<'a, REG> RddeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Rdde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Rdde::Enable) - } -} -#[doc = "Frame Complete DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fcde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fcde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FCDE` reader - Frame Complete DMA Enable"] -pub type FcdeR = crate::BitReader; -impl FcdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fcde { - match self.bits { - false => Fcde::Disable, - true => Fcde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Fcde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Fcde::Enable - } -} -#[doc = "Field `FCDE` writer - Frame Complete DMA Enable"] -pub type FcdeW<'a, REG> = crate::BitWriter<'a, REG, Fcde>; -impl<'a, REG> FcdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Fcde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Fcde::Enable) - } -} -impl R { - #[doc = "Bit 0 - Transmit Data DMA Enable"] - #[inline(always)] - pub fn tdde(&self) -> TddeR { - TddeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data DMA Enable"] - #[inline(always)] - pub fn rdde(&self) -> RddeR { - RddeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 9 - Frame Complete DMA Enable"] - #[inline(always)] - pub fn fcde(&self) -> FcdeR { - FcdeR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmit Data DMA Enable"] - #[inline(always)] - pub fn tdde(&mut self) -> TddeW { - TddeW::new(self, 0) - } - #[doc = "Bit 1 - Receive Data DMA Enable"] - #[inline(always)] - pub fn rdde(&mut self) -> RddeW { - RddeW::new(self, 1) - } - #[doc = "Bit 9 - Frame Complete DMA Enable"] - #[inline(always)] - pub fn fcde(&mut self) -> FcdeW { - FcdeW::new(self, 9) - } -} -#[doc = "DMA Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`der::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`der::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DerSpec; -impl crate::RegisterSpec for DerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`der::R`](R) reader structure"] -impl crate::Readable for DerSpec {} -#[doc = "`write(|w| ..)` method takes [`der::W`](W) writer structure"] -impl crate::Writable for DerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DER to value 0"] -impl crate::Resettable for DerSpec {} diff --git a/mcxa276-pac/src/lpspi0/dmr0.rs b/mcxa276-pac/src/lpspi0/dmr0.rs deleted file mode 100644 index 3f76b6ee1..000000000 --- a/mcxa276-pac/src/lpspi0/dmr0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `DMR0` reader"] -pub type R = crate::R; -#[doc = "Register `DMR0` writer"] -pub type W = crate::W; -#[doc = "Field `MATCH0` reader - Match 0 Value"] -pub type Match0R = crate::FieldReader; -#[doc = "Field `MATCH0` writer - Match 0 Value"] -pub type Match0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Match 0 Value"] - #[inline(always)] - pub fn match0(&self) -> Match0R { - Match0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Match 0 Value"] - #[inline(always)] - pub fn match0(&mut self) -> Match0W { - Match0W::new(self, 0) - } -} -#[doc = "Data Match 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Dmr0Spec; -impl crate::RegisterSpec for Dmr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`dmr0::R`](R) reader structure"] -impl crate::Readable for Dmr0Spec {} -#[doc = "`write(|w| ..)` method takes [`dmr0::W`](W) writer structure"] -impl crate::Writable for Dmr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DMR0 to value 0"] -impl crate::Resettable for Dmr0Spec {} diff --git a/mcxa276-pac/src/lpspi0/dmr1.rs b/mcxa276-pac/src/lpspi0/dmr1.rs deleted file mode 100644 index 31b4aca39..000000000 --- a/mcxa276-pac/src/lpspi0/dmr1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `DMR1` reader"] -pub type R = crate::R; -#[doc = "Register `DMR1` writer"] -pub type W = crate::W; -#[doc = "Field `MATCH1` reader - Match 1 Value"] -pub type Match1R = crate::FieldReader; -#[doc = "Field `MATCH1` writer - Match 1 Value"] -pub type Match1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Match 1 Value"] - #[inline(always)] - pub fn match1(&self) -> Match1R { - Match1R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Match 1 Value"] - #[inline(always)] - pub fn match1(&mut self) -> Match1W { - Match1W::new(self, 0) - } -} -#[doc = "Data Match 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Dmr1Spec; -impl crate::RegisterSpec for Dmr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`dmr1::R`](R) reader structure"] -impl crate::Readable for Dmr1Spec {} -#[doc = "`write(|w| ..)` method takes [`dmr1::W`](W) writer structure"] -impl crate::Writable for Dmr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DMR1 to value 0"] -impl crate::Resettable for Dmr1Spec {} diff --git a/mcxa276-pac/src/lpspi0/fcr.rs b/mcxa276-pac/src/lpspi0/fcr.rs deleted file mode 100644 index fd2f3299e..000000000 --- a/mcxa276-pac/src/lpspi0/fcr.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `FCR` reader"] -pub type R = crate::R; -#[doc = "Register `FCR` writer"] -pub type W = crate::W; -#[doc = "Field `TXWATER` reader - Transmit FIFO Watermark"] -pub type TxwaterR = crate::FieldReader; -#[doc = "Field `TXWATER` writer - Transmit FIFO Watermark"] -pub type TxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `RXWATER` reader - Receive FIFO Watermark"] -pub type RxwaterR = crate::FieldReader; -#[doc = "Field `RXWATER` writer - Receive FIFO Watermark"] -pub type RxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Transmit FIFO Watermark"] - #[inline(always)] - pub fn txwater(&self) -> TxwaterR { - TxwaterR::new((self.bits & 3) as u8) - } - #[doc = "Bits 16:17 - Receive FIFO Watermark"] - #[inline(always)] - pub fn rxwater(&self) -> RxwaterR { - RxwaterR::new(((self.bits >> 16) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Transmit FIFO Watermark"] - #[inline(always)] - pub fn txwater(&mut self) -> TxwaterW { - TxwaterW::new(self, 0) - } - #[doc = "Bits 16:17 - Receive FIFO Watermark"] - #[inline(always)] - pub fn rxwater(&mut self) -> RxwaterW { - RxwaterW::new(self, 16) - } -} -#[doc = "FIFO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FcrSpec; -impl crate::RegisterSpec for FcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fcr::R`](R) reader structure"] -impl crate::Readable for FcrSpec {} -#[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] -impl crate::Writable for FcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FCR to value 0"] -impl crate::Resettable for FcrSpec {} diff --git a/mcxa276-pac/src/lpspi0/fsr.rs b/mcxa276-pac/src/lpspi0/fsr.rs deleted file mode 100644 index 06ed61d5b..000000000 --- a/mcxa276-pac/src/lpspi0/fsr.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `FSR` reader"] -pub type R = crate::R; -#[doc = "Field `TXCOUNT` reader - Transmit FIFO Count"] -pub type TxcountR = crate::FieldReader; -#[doc = "Field `RXCOUNT` reader - Receive FIFO Count"] -pub type RxcountR = crate::FieldReader; -impl R { - #[doc = "Bits 0:2 - Transmit FIFO Count"] - #[inline(always)] - pub fn txcount(&self) -> TxcountR { - TxcountR::new((self.bits & 7) as u8) - } - #[doc = "Bits 16:18 - Receive FIFO Count"] - #[inline(always)] - pub fn rxcount(&self) -> RxcountR { - RxcountR::new(((self.bits >> 16) & 7) as u8) - } -} -#[doc = "FIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`fsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FsrSpec; -impl crate::RegisterSpec for FsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fsr::R`](R) reader structure"] -impl crate::Readable for FsrSpec {} -#[doc = "`reset()` method sets FSR to value 0"] -impl crate::Resettable for FsrSpec {} diff --git a/mcxa276-pac/src/lpspi0/ier.rs b/mcxa276-pac/src/lpspi0/ier.rs deleted file mode 100644 index 2ce7aedfd..000000000 --- a/mcxa276-pac/src/lpspi0/ier.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `IER` reader"] -pub type R = crate::R; -#[doc = "Register `IER` writer"] -pub type W = crate::W; -#[doc = "Transmit Data Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDIE` reader - Transmit Data Interrupt Enable"] -pub type TdieR = crate::BitReader; -impl TdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdie { - match self.bits { - false => Tdie::Disable, - true => Tdie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tdie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tdie::Enable - } -} -#[doc = "Field `TDIE` writer - Transmit Data Interrupt Enable"] -pub type TdieW<'a, REG> = crate::BitWriter<'a, REG, Tdie>; -impl<'a, REG> TdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tdie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tdie::Enable) - } -} -#[doc = "Receive Data Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDIE` reader - Receive Data Interrupt Enable"] -pub type RdieR = crate::BitReader; -impl RdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdie { - match self.bits { - false => Rdie::Disable, - true => Rdie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Rdie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Rdie::Enable - } -} -#[doc = "Field `RDIE` writer - Receive Data Interrupt Enable"] -pub type RdieW<'a, REG> = crate::BitWriter<'a, REG, Rdie>; -impl<'a, REG> RdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Rdie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Rdie::Enable) - } -} -#[doc = "Word Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wcie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wcie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WCIE` reader - Word Complete Interrupt Enable"] -pub type WcieR = crate::BitReader; -impl WcieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wcie { - match self.bits { - false => Wcie::Disable, - true => Wcie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wcie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wcie::Enable - } -} -#[doc = "Field `WCIE` writer - Word Complete Interrupt Enable"] -pub type WcieW<'a, REG> = crate::BitWriter<'a, REG, Wcie>; -impl<'a, REG> WcieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wcie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wcie::Enable) - } -} -#[doc = "Frame Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fcie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fcie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FCIE` reader - Frame Complete Interrupt Enable"] -pub type FcieR = crate::BitReader; -impl FcieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fcie { - match self.bits { - false => Fcie::Disable, - true => Fcie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Fcie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Fcie::Enable - } -} -#[doc = "Field `FCIE` writer - Frame Complete Interrupt Enable"] -pub type FcieW<'a, REG> = crate::BitWriter<'a, REG, Fcie>; -impl<'a, REG> FcieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Fcie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Fcie::Enable) - } -} -#[doc = "Transfer Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tcie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tcie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCIE` reader - Transfer Complete Interrupt Enable"] -pub type TcieR = crate::BitReader; -impl TcieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcie { - match self.bits { - false => Tcie::Disable, - true => Tcie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tcie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tcie::Enable - } -} -#[doc = "Field `TCIE` writer - Transfer Complete Interrupt Enable"] -pub type TcieW<'a, REG> = crate::BitWriter<'a, REG, Tcie>; -impl<'a, REG> TcieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tcie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tcie::Enable) - } -} -#[doc = "Transmit Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Teie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Teie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TEIE` reader - Transmit Error Interrupt Enable"] -pub type TeieR = crate::BitReader; -impl TeieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Teie { - match self.bits { - false => Teie::Disable, - true => Teie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Teie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Teie::Enable - } -} -#[doc = "Field `TEIE` writer - Transmit Error Interrupt Enable"] -pub type TeieW<'a, REG> = crate::BitWriter<'a, REG, Teie>; -impl<'a, REG> TeieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Teie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Teie::Enable) - } -} -#[doc = "Receive Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REIE` reader - Receive Error Interrupt Enable"] -pub type ReieR = crate::BitReader; -impl ReieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reie { - match self.bits { - false => Reie::Disable, - true => Reie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Reie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Reie::Enable - } -} -#[doc = "Field `REIE` writer - Receive Error Interrupt Enable"] -pub type ReieW<'a, REG> = crate::BitWriter<'a, REG, Reie>; -impl<'a, REG> ReieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Reie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Reie::Enable) - } -} -#[doc = "Data Match Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMIE` reader - Data Match Interrupt Enable"] -pub type DmieR = crate::BitReader; -impl DmieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmie { - match self.bits { - false => Dmie::Disable, - true => Dmie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Dmie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dmie::Enable - } -} -#[doc = "Field `DMIE` writer - Data Match Interrupt Enable"] -pub type DmieW<'a, REG> = crate::BitWriter<'a, REG, Dmie>; -impl<'a, REG> DmieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Dmie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dmie::Enable) - } -} -impl R { - #[doc = "Bit 0 - Transmit Data Interrupt Enable"] - #[inline(always)] - pub fn tdie(&self) -> TdieR { - TdieR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data Interrupt Enable"] - #[inline(always)] - pub fn rdie(&self) -> RdieR { - RdieR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - Word Complete Interrupt Enable"] - #[inline(always)] - pub fn wcie(&self) -> WcieR { - WcieR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Frame Complete Interrupt Enable"] - #[inline(always)] - pub fn fcie(&self) -> FcieR { - FcieR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Transfer Complete Interrupt Enable"] - #[inline(always)] - pub fn tcie(&self) -> TcieR { - TcieR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Transmit Error Interrupt Enable"] - #[inline(always)] - pub fn teie(&self) -> TeieR { - TeieR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Receive Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&self) -> ReieR { - ReieR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Data Match Interrupt Enable"] - #[inline(always)] - pub fn dmie(&self) -> DmieR { - DmieR::new(((self.bits >> 13) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmit Data Interrupt Enable"] - #[inline(always)] - pub fn tdie(&mut self) -> TdieW { - TdieW::new(self, 0) - } - #[doc = "Bit 1 - Receive Data Interrupt Enable"] - #[inline(always)] - pub fn rdie(&mut self) -> RdieW { - RdieW::new(self, 1) - } - #[doc = "Bit 8 - Word Complete Interrupt Enable"] - #[inline(always)] - pub fn wcie(&mut self) -> WcieW { - WcieW::new(self, 8) - } - #[doc = "Bit 9 - Frame Complete Interrupt Enable"] - #[inline(always)] - pub fn fcie(&mut self) -> FcieW { - FcieW::new(self, 9) - } - #[doc = "Bit 10 - Transfer Complete Interrupt Enable"] - #[inline(always)] - pub fn tcie(&mut self) -> TcieW { - TcieW::new(self, 10) - } - #[doc = "Bit 11 - Transmit Error Interrupt Enable"] - #[inline(always)] - pub fn teie(&mut self) -> TeieW { - TeieW::new(self, 11) - } - #[doc = "Bit 12 - Receive Error Interrupt Enable"] - #[inline(always)] - pub fn reie(&mut self) -> ReieW { - ReieW::new(self, 12) - } - #[doc = "Bit 13 - Data Match Interrupt Enable"] - #[inline(always)] - pub fn dmie(&mut self) -> DmieW { - DmieW::new(self, 13) - } -} -#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IerSpec; -impl crate::RegisterSpec for IerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ier::R`](R) reader structure"] -impl crate::Readable for IerSpec {} -#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] -impl crate::Writable for IerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IER to value 0"] -impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/lpspi0/param.rs b/mcxa276-pac/src/lpspi0/param.rs deleted file mode 100644 index 28e74a31b..000000000 --- a/mcxa276-pac/src/lpspi0/param.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "Field `TXFIFO` reader - Transmit FIFO Size"] -pub type TxfifoR = crate::FieldReader; -#[doc = "Field `RXFIFO` reader - Receive FIFO Size"] -pub type RxfifoR = crate::FieldReader; -#[doc = "Field `PCSNUM` reader - PCS Number"] -pub type PcsnumR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Transmit FIFO Size"] - #[inline(always)] - pub fn txfifo(&self) -> TxfifoR { - TxfifoR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Receive FIFO Size"] - #[inline(always)] - pub fn rxfifo(&self) -> RxfifoR { - RxfifoR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - PCS Number"] - #[inline(always)] - pub fn pcsnum(&self) -> PcsnumR { - PcsnumR::new(((self.bits >> 16) & 0xff) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x0004_0202"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x0004_0202; -} diff --git a/mcxa276-pac/src/lpspi0/rdbr.rs b/mcxa276-pac/src/lpspi0/rdbr.rs deleted file mode 100644 index f36c625ee..000000000 --- a/mcxa276-pac/src/lpspi0/rdbr.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `RDBR[%s]` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Data"] -pub type DataR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new(self.bits) - } -} -#[doc = "Receive Data Burst\n\nYou can [`read`](crate::Reg::read) this register and get [`rdbr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RdbrSpec; -impl crate::RegisterSpec for RdbrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rdbr::R`](R) reader structure"] -impl crate::Readable for RdbrSpec {} -#[doc = "`reset()` method sets RDBR[%s] to value 0"] -impl crate::Resettable for RdbrSpec {} diff --git a/mcxa276-pac/src/lpspi0/rdr.rs b/mcxa276-pac/src/lpspi0/rdr.rs deleted file mode 100644 index e0a814a20..000000000 --- a/mcxa276-pac/src/lpspi0/rdr.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `RDR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Receive Data"] -pub type DataR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Receive Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new(self.bits) - } -} -#[doc = "Receive Data\n\nYou can [`read`](crate::Reg::read) this register and get [`rdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RdrSpec; -impl crate::RegisterSpec for RdrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rdr::R`](R) reader structure"] -impl crate::Readable for RdrSpec {} -#[doc = "`reset()` method sets RDR to value 0"] -impl crate::Resettable for RdrSpec {} diff --git a/mcxa276-pac/src/lpspi0/rdror.rs b/mcxa276-pac/src/lpspi0/rdror.rs deleted file mode 100644 index c25fcd4de..000000000 --- a/mcxa276-pac/src/lpspi0/rdror.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `RDROR` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Receive Data"] -pub type DataR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Receive Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new(self.bits) - } -} -#[doc = "Receive Data Read Only\n\nYou can [`read`](crate::Reg::read) this register and get [`rdror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RdrorSpec; -impl crate::RegisterSpec for RdrorSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rdror::R`](R) reader structure"] -impl crate::Readable for RdrorSpec {} -#[doc = "`reset()` method sets RDROR to value 0"] -impl crate::Resettable for RdrorSpec {} diff --git a/mcxa276-pac/src/lpspi0/rsr.rs b/mcxa276-pac/src/lpspi0/rsr.rs deleted file mode 100644 index 31a9f05cd..000000000 --- a/mcxa276-pac/src/lpspi0/rsr.rs +++ /dev/null @@ -1,97 +0,0 @@ -#[doc = "Register `RSR` reader"] -pub type R = crate::R; -#[doc = "Start of Frame\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sof { - #[doc = "0: Subsequent data word or RX FIFO is empty (RXEMPTY=1)."] - NextDataword = 0, - #[doc = "1: First data word"] - FirstDataword = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOF` reader - Start of Frame"] -pub type SofR = crate::BitReader; -impl SofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sof { - match self.bits { - false => Sof::NextDataword, - true => Sof::FirstDataword, - } - } - #[doc = "Subsequent data word or RX FIFO is empty (RXEMPTY=1)."] - #[inline(always)] - pub fn is_next_dataword(&self) -> bool { - *self == Sof::NextDataword - } - #[doc = "First data word"] - #[inline(always)] - pub fn is_first_dataword(&self) -> bool { - *self == Sof::FirstDataword - } -} -#[doc = "RX FIFO Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempty { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempty) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPTY` reader - RX FIFO Empty"] -pub type RxemptyR = crate::BitReader; -impl RxemptyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempty { - match self.bits { - false => Rxempty::NotEmpty, - true => Rxempty::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempty::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempty::Empty - } -} -impl R { - #[doc = "Bit 0 - Start of Frame"] - #[inline(always)] - pub fn sof(&self) -> SofR { - SofR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - RX FIFO Empty"] - #[inline(always)] - pub fn rxempty(&self) -> RxemptyR { - RxemptyR::new(((self.bits >> 1) & 1) != 0) - } -} -#[doc = "Receive Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RsrSpec; -impl crate::RegisterSpec for RsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rsr::R`](R) reader structure"] -impl crate::Readable for RsrSpec {} -#[doc = "`reset()` method sets RSR to value 0x02"] -impl crate::Resettable for RsrSpec { - const RESET_VALUE: u32 = 0x02; -} diff --git a/mcxa276-pac/src/lpspi0/sr.rs b/mcxa276-pac/src/lpspi0/sr.rs deleted file mode 100644 index db8ad1012..000000000 --- a/mcxa276-pac/src/lpspi0/sr.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `SR` reader"] -pub type R = crate::R; -#[doc = "Register `SR` writer"] -pub type W = crate::W; -#[doc = "Transmit Data Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdf { - #[doc = "0: Transmit data not requested"] - TxdataNotReqst = 0, - #[doc = "1: Transmit data requested"] - TxdataReqst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDF` reader - Transmit Data Flag"] -pub type TdfR = crate::BitReader; -impl TdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdf { - match self.bits { - false => Tdf::TxdataNotReqst, - true => Tdf::TxdataReqst, - } - } - #[doc = "Transmit data not requested"] - #[inline(always)] - pub fn is_txdata_not_reqst(&self) -> bool { - *self == Tdf::TxdataNotReqst - } - #[doc = "Transmit data requested"] - #[inline(always)] - pub fn is_txdata_reqst(&self) -> bool { - *self == Tdf::TxdataReqst - } -} -#[doc = "Receive Data Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdf { - #[doc = "0: Receive data not ready"] - Notready = 0, - #[doc = "1: Receive data ready"] - Ready = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDF` reader - Receive Data Flag"] -pub type RdfR = crate::BitReader; -impl RdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdf { - match self.bits { - false => Rdf::Notready, - true => Rdf::Ready, - } - } - #[doc = "Receive data not ready"] - #[inline(always)] - pub fn is_notready(&self) -> bool { - *self == Rdf::Notready - } - #[doc = "Receive data ready"] - #[inline(always)] - pub fn is_ready(&self) -> bool { - *self == Rdf::Ready - } -} -#[doc = "Word Complete Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wcf { - #[doc = "0: Not complete"] - NotCompleted = 0, - #[doc = "1: Complete"] - Completed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wcf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WCF` reader - Word Complete Flag"] -pub type WcfR = crate::BitReader; -impl WcfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wcf { - match self.bits { - false => Wcf::NotCompleted, - true => Wcf::Completed, - } - } - #[doc = "Not complete"] - #[inline(always)] - pub fn is_not_completed(&self) -> bool { - *self == Wcf::NotCompleted - } - #[doc = "Complete"] - #[inline(always)] - pub fn is_completed(&self) -> bool { - *self == Wcf::Completed - } -} -#[doc = "Field `WCF` writer - Word Complete Flag"] -pub type WcfW<'a, REG> = crate::BitWriter1C<'a, REG, Wcf>; -impl<'a, REG> WcfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not complete"] - #[inline(always)] - pub fn not_completed(self) -> &'a mut crate::W { - self.variant(Wcf::NotCompleted) - } - #[doc = "Complete"] - #[inline(always)] - pub fn completed(self) -> &'a mut crate::W { - self.variant(Wcf::Completed) - } -} -#[doc = "Frame Complete Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fcf { - #[doc = "0: Not complete"] - NotCompleted = 0, - #[doc = "1: Complete"] - Completed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fcf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FCF` reader - Frame Complete Flag"] -pub type FcfR = crate::BitReader; -impl FcfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fcf { - match self.bits { - false => Fcf::NotCompleted, - true => Fcf::Completed, - } - } - #[doc = "Not complete"] - #[inline(always)] - pub fn is_not_completed(&self) -> bool { - *self == Fcf::NotCompleted - } - #[doc = "Complete"] - #[inline(always)] - pub fn is_completed(&self) -> bool { - *self == Fcf::Completed - } -} -#[doc = "Field `FCF` writer - Frame Complete Flag"] -pub type FcfW<'a, REG> = crate::BitWriter1C<'a, REG, Fcf>; -impl<'a, REG> FcfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not complete"] - #[inline(always)] - pub fn not_completed(self) -> &'a mut crate::W { - self.variant(Fcf::NotCompleted) - } - #[doc = "Complete"] - #[inline(always)] - pub fn completed(self) -> &'a mut crate::W { - self.variant(Fcf::Completed) - } -} -#[doc = "Transfer Complete Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tcf { - #[doc = "0: Not complete"] - NotCompleted = 0, - #[doc = "1: Complete"] - Completed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tcf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCF` reader - Transfer Complete Flag"] -pub type TcfR = crate::BitReader; -impl TcfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcf { - match self.bits { - false => Tcf::NotCompleted, - true => Tcf::Completed, - } - } - #[doc = "Not complete"] - #[inline(always)] - pub fn is_not_completed(&self) -> bool { - *self == Tcf::NotCompleted - } - #[doc = "Complete"] - #[inline(always)] - pub fn is_completed(&self) -> bool { - *self == Tcf::Completed - } -} -#[doc = "Field `TCF` writer - Transfer Complete Flag"] -pub type TcfW<'a, REG> = crate::BitWriter1C<'a, REG, Tcf>; -impl<'a, REG> TcfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not complete"] - #[inline(always)] - pub fn not_completed(self) -> &'a mut crate::W { - self.variant(Tcf::NotCompleted) - } - #[doc = "Complete"] - #[inline(always)] - pub fn completed(self) -> &'a mut crate::W { - self.variant(Tcf::Completed) - } -} -#[doc = "Transmit Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tef { - #[doc = "0: No underrun"] - NoUnderrun = 0, - #[doc = "1: Underrun"] - Underrun = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tef) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TEF` reader - Transmit Error Flag"] -pub type TefR = crate::BitReader; -impl TefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tef { - match self.bits { - false => Tef::NoUnderrun, - true => Tef::Underrun, - } - } - #[doc = "No underrun"] - #[inline(always)] - pub fn is_no_underrun(&self) -> bool { - *self == Tef::NoUnderrun - } - #[doc = "Underrun"] - #[inline(always)] - pub fn is_underrun(&self) -> bool { - *self == Tef::Underrun - } -} -#[doc = "Field `TEF` writer - Transmit Error Flag"] -pub type TefW<'a, REG> = crate::BitWriter1C<'a, REG, Tef>; -impl<'a, REG> TefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No underrun"] - #[inline(always)] - pub fn no_underrun(self) -> &'a mut crate::W { - self.variant(Tef::NoUnderrun) - } - #[doc = "Underrun"] - #[inline(always)] - pub fn underrun(self) -> &'a mut crate::W { - self.variant(Tef::Underrun) - } -} -#[doc = "Receive Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ref { - #[doc = "0: No overflow"] - NotOverflowed = 0, - #[doc = "1: Overflow"] - Overflowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ref) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REF` reader - Receive Error Flag"] -pub type RefR = crate::BitReader; -impl RefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ref { - match self.bits { - false => Ref::NotOverflowed, - true => Ref::Overflowed, - } - } - #[doc = "No overflow"] - #[inline(always)] - pub fn is_not_overflowed(&self) -> bool { - *self == Ref::NotOverflowed - } - #[doc = "Overflow"] - #[inline(always)] - pub fn is_overflowed(&self) -> bool { - *self == Ref::Overflowed - } -} -#[doc = "Field `REF` writer - Receive Error Flag"] -pub type RefW<'a, REG> = crate::BitWriter1C<'a, REG, Ref>; -impl<'a, REG> RefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overflow"] - #[inline(always)] - pub fn not_overflowed(self) -> &'a mut crate::W { - self.variant(Ref::NotOverflowed) - } - #[doc = "Overflow"] - #[inline(always)] - pub fn overflowed(self) -> &'a mut crate::W { - self.variant(Ref::Overflowed) - } -} -#[doc = "Data Match Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmf { - #[doc = "0: No match"] - NoMatch = 0, - #[doc = "1: Match"] - Match = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMF` reader - Data Match Flag"] -pub type DmfR = crate::BitReader; -impl DmfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmf { - match self.bits { - false => Dmf::NoMatch, - true => Dmf::Match, - } - } - #[doc = "No match"] - #[inline(always)] - pub fn is_no_match(&self) -> bool { - *self == Dmf::NoMatch - } - #[doc = "Match"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Dmf::Match - } -} -#[doc = "Field `DMF` writer - Data Match Flag"] -pub type DmfW<'a, REG> = crate::BitWriter1C<'a, REG, Dmf>; -impl<'a, REG> DmfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No match"] - #[inline(always)] - pub fn no_match(self) -> &'a mut crate::W { - self.variant(Dmf::NoMatch) - } - #[doc = "Match"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Dmf::Match) - } -} -#[doc = "Module Busy Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mbf { - #[doc = "0: LPSPI is idle"] - Idle = 0, - #[doc = "1: LPSPI is busy"] - Busy = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MBF` reader - Module Busy Flag"] -pub type MbfR = crate::BitReader; -impl MbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbf { - match self.bits { - false => Mbf::Idle, - true => Mbf::Busy, - } - } - #[doc = "LPSPI is idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Mbf::Idle - } - #[doc = "LPSPI is busy"] - #[inline(always)] - pub fn is_busy(&self) -> bool { - *self == Mbf::Busy - } -} -impl R { - #[doc = "Bit 0 - Transmit Data Flag"] - #[inline(always)] - pub fn tdf(&self) -> TdfR { - TdfR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Data Flag"] - #[inline(always)] - pub fn rdf(&self) -> RdfR { - RdfR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - Word Complete Flag"] - #[inline(always)] - pub fn wcf(&self) -> WcfR { - WcfR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Frame Complete Flag"] - #[inline(always)] - pub fn fcf(&self) -> FcfR { - FcfR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Transfer Complete Flag"] - #[inline(always)] - pub fn tcf(&self) -> TcfR { - TcfR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Transmit Error Flag"] - #[inline(always)] - pub fn tef(&self) -> TefR { - TefR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Receive Error Flag"] - #[inline(always)] - pub fn ref_(&self) -> RefR { - RefR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Data Match Flag"] - #[inline(always)] - pub fn dmf(&self) -> DmfR { - DmfR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 24 - Module Busy Flag"] - #[inline(always)] - pub fn mbf(&self) -> MbfR { - MbfR::new(((self.bits >> 24) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - Word Complete Flag"] - #[inline(always)] - pub fn wcf(&mut self) -> WcfW { - WcfW::new(self, 8) - } - #[doc = "Bit 9 - Frame Complete Flag"] - #[inline(always)] - pub fn fcf(&mut self) -> FcfW { - FcfW::new(self, 9) - } - #[doc = "Bit 10 - Transfer Complete Flag"] - #[inline(always)] - pub fn tcf(&mut self) -> TcfW { - TcfW::new(self, 10) - } - #[doc = "Bit 11 - Transmit Error Flag"] - #[inline(always)] - pub fn tef(&mut self) -> TefW { - TefW::new(self, 11) - } - #[doc = "Bit 12 - Receive Error Flag"] - #[inline(always)] - pub fn ref_(&mut self) -> RefW { - RefW::new(self, 12) - } - #[doc = "Bit 13 - Data Match Flag"] - #[inline(always)] - pub fn dmf(&mut self) -> DmfW { - DmfW::new(self, 13) - } -} -#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrSpec; -impl crate::RegisterSpec for SrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sr::R`](R) reader structure"] -impl crate::Readable for SrSpec {} -#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] -impl crate::Writable for SrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f00; -} -#[doc = "`reset()` method sets SR to value 0x01"] -impl crate::Resettable for SrSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/lpspi0/tcbr.rs b/mcxa276-pac/src/lpspi0/tcbr.rs deleted file mode 100644 index 37c7abd61..000000000 --- a/mcxa276-pac/src/lpspi0/tcbr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `TCBR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Command Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Command Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Transmit Command Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcbr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcbrSpec; -impl crate::RegisterSpec for TcbrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`tcbr::W`](W) writer structure"] -impl crate::Writable for TcbrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCBR to value 0"] -impl crate::Resettable for TcbrSpec {} diff --git a/mcxa276-pac/src/lpspi0/tcr.rs b/mcxa276-pac/src/lpspi0/tcr.rs deleted file mode 100644 index 6ca094c2f..000000000 --- a/mcxa276-pac/src/lpspi0/tcr.rs +++ /dev/null @@ -1,868 +0,0 @@ -#[doc = "Register `TCR` reader"] -pub type R = crate::R; -#[doc = "Register `TCR` writer"] -pub type W = crate::W; -#[doc = "Field `FRAMESZ` reader - Frame Size"] -pub type FrameszR = crate::FieldReader; -#[doc = "Field `FRAMESZ` writer - Frame Size"] -pub type FrameszW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Transfer Width\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Width { - #[doc = "0: 1-bit transfer"] - Onebit = 0, - #[doc = "1: 2-bit transfer"] - Twobit = 1, - #[doc = "2: 4-bit transfer"] - Fourbit = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Width) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Width { - type Ux = u8; -} -impl crate::IsEnum for Width {} -#[doc = "Field `WIDTH` reader - Transfer Width"] -pub type WidthR = crate::FieldReader; -impl WidthR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Width::Onebit), - 1 => Some(Width::Twobit), - 2 => Some(Width::Fourbit), - _ => None, - } - } - #[doc = "1-bit transfer"] - #[inline(always)] - pub fn is_onebit(&self) -> bool { - *self == Width::Onebit - } - #[doc = "2-bit transfer"] - #[inline(always)] - pub fn is_twobit(&self) -> bool { - *self == Width::Twobit - } - #[doc = "4-bit transfer"] - #[inline(always)] - pub fn is_fourbit(&self) -> bool { - *self == Width::Fourbit - } -} -#[doc = "Field `WIDTH` writer - Transfer Width"] -pub type WidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Width>; -impl<'a, REG> WidthW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "1-bit transfer"] - #[inline(always)] - pub fn onebit(self) -> &'a mut crate::W { - self.variant(Width::Onebit) - } - #[doc = "2-bit transfer"] - #[inline(always)] - pub fn twobit(self) -> &'a mut crate::W { - self.variant(Width::Twobit) - } - #[doc = "4-bit transfer"] - #[inline(always)] - pub fn fourbit(self) -> &'a mut crate::W { - self.variant(Width::Fourbit) - } -} -#[doc = "Transmit Data Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txmsk { - #[doc = "0: Normal transfer"] - Normal = 0, - #[doc = "1: Mask transmit data"] - Mask = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txmsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXMSK` reader - Transmit Data Mask"] -pub type TxmskR = crate::BitReader; -impl TxmskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txmsk { - match self.bits { - false => Txmsk::Normal, - true => Txmsk::Mask, - } - } - #[doc = "Normal transfer"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == Txmsk::Normal - } - #[doc = "Mask transmit data"] - #[inline(always)] - pub fn is_mask(&self) -> bool { - *self == Txmsk::Mask - } -} -#[doc = "Field `TXMSK` writer - Transmit Data Mask"] -pub type TxmskW<'a, REG> = crate::BitWriter<'a, REG, Txmsk>; -impl<'a, REG> TxmskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal transfer"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(Txmsk::Normal) - } - #[doc = "Mask transmit data"] - #[inline(always)] - pub fn mask(self) -> &'a mut crate::W { - self.variant(Txmsk::Mask) - } -} -#[doc = "Receive Data Mask\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxmsk { - #[doc = "0: Normal transfer"] - Normal = 0, - #[doc = "1: Mask receive data"] - Mask = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxmsk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXMSK` reader - Receive Data Mask"] -pub type RxmskR = crate::BitReader; -impl RxmskR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxmsk { - match self.bits { - false => Rxmsk::Normal, - true => Rxmsk::Mask, - } - } - #[doc = "Normal transfer"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == Rxmsk::Normal - } - #[doc = "Mask receive data"] - #[inline(always)] - pub fn is_mask(&self) -> bool { - *self == Rxmsk::Mask - } -} -#[doc = "Field `RXMSK` writer - Receive Data Mask"] -pub type RxmskW<'a, REG> = crate::BitWriter<'a, REG, Rxmsk>; -impl<'a, REG> RxmskW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal transfer"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(Rxmsk::Normal) - } - #[doc = "Mask receive data"] - #[inline(always)] - pub fn mask(self) -> &'a mut crate::W { - self.variant(Rxmsk::Mask) - } -} -#[doc = "Continuing Command\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Contc { - #[doc = "0: Command word for start of new transfer"] - Start = 0, - #[doc = "1: Command word for continuing transfer"] - Continue = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Contc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CONTC` reader - Continuing Command"] -pub type ContcR = crate::BitReader; -impl ContcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Contc { - match self.bits { - false => Contc::Start, - true => Contc::Continue, - } - } - #[doc = "Command word for start of new transfer"] - #[inline(always)] - pub fn is_start(&self) -> bool { - *self == Contc::Start - } - #[doc = "Command word for continuing transfer"] - #[inline(always)] - pub fn is_continue(&self) -> bool { - *self == Contc::Continue - } -} -#[doc = "Field `CONTC` writer - Continuing Command"] -pub type ContcW<'a, REG> = crate::BitWriter<'a, REG, Contc>; -impl<'a, REG> ContcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Command word for start of new transfer"] - #[inline(always)] - pub fn start(self) -> &'a mut crate::W { - self.variant(Contc::Start) - } - #[doc = "Command word for continuing transfer"] - #[inline(always)] - pub fn continue_(self) -> &'a mut crate::W { - self.variant(Contc::Continue) - } -} -#[doc = "Continuous Transfer\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cont { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cont) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CONT` reader - Continuous Transfer"] -pub type ContR = crate::BitReader; -impl ContR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cont { - match self.bits { - false => Cont::Disabled, - true => Cont::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cont::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cont::Enabled - } -} -#[doc = "Field `CONT` writer - Continuous Transfer"] -pub type ContW<'a, REG> = crate::BitWriter<'a, REG, Cont>; -impl<'a, REG> ContW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cont::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cont::Enabled) - } -} -#[doc = "Byte Swap\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bysw { - #[doc = "0: Disable byte swap"] - Disabled = 0, - #[doc = "1: Enable byte swap"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bysw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BYSW` reader - Byte Swap"] -pub type ByswR = crate::BitReader; -impl ByswR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bysw { - match self.bits { - false => Bysw::Disabled, - true => Bysw::Enabled, - } - } - #[doc = "Disable byte swap"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Bysw::Disabled - } - #[doc = "Enable byte swap"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Bysw::Enabled - } -} -#[doc = "Field `BYSW` writer - Byte Swap"] -pub type ByswW<'a, REG> = crate::BitWriter<'a, REG, Bysw>; -impl<'a, REG> ByswW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable byte swap"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Bysw::Disabled) - } - #[doc = "Enable byte swap"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Bysw::Enabled) - } -} -#[doc = "LSB First\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lsbf { - #[doc = "0: MSB first"] - MsbFirst = 0, - #[doc = "1: LSB first"] - LsbFirst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lsbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LSBF` reader - LSB First"] -pub type LsbfR = crate::BitReader; -impl LsbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lsbf { - match self.bits { - false => Lsbf::MsbFirst, - true => Lsbf::LsbFirst, - } - } - #[doc = "MSB first"] - #[inline(always)] - pub fn is_msb_first(&self) -> bool { - *self == Lsbf::MsbFirst - } - #[doc = "LSB first"] - #[inline(always)] - pub fn is_lsb_first(&self) -> bool { - *self == Lsbf::LsbFirst - } -} -#[doc = "Field `LSBF` writer - LSB First"] -pub type LsbfW<'a, REG> = crate::BitWriter<'a, REG, Lsbf>; -impl<'a, REG> LsbfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "MSB first"] - #[inline(always)] - pub fn msb_first(self) -> &'a mut crate::W { - self.variant(Lsbf::MsbFirst) - } - #[doc = "LSB first"] - #[inline(always)] - pub fn lsb_first(self) -> &'a mut crate::W { - self.variant(Lsbf::LsbFirst) - } -} -#[doc = "Peripheral Chip Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pcs { - #[doc = "0: Transfer using PCS\\[0\\]"] - TxPcs0 = 0, - #[doc = "1: Transfer using PCS\\[1\\]"] - TxPcs1 = 1, - #[doc = "2: Transfer using PCS\\[2\\]"] - TxPcs2 = 2, - #[doc = "3: Transfer using PCS\\[3\\]"] - TxPcs3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pcs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pcs { - type Ux = u8; -} -impl crate::IsEnum for Pcs {} -#[doc = "Field `PCS` reader - Peripheral Chip Select"] -pub type PcsR = crate::FieldReader; -impl PcsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pcs { - match self.bits { - 0 => Pcs::TxPcs0, - 1 => Pcs::TxPcs1, - 2 => Pcs::TxPcs2, - 3 => Pcs::TxPcs3, - _ => unreachable!(), - } - } - #[doc = "Transfer using PCS\\[0\\]"] - #[inline(always)] - pub fn is_tx_pcs0(&self) -> bool { - *self == Pcs::TxPcs0 - } - #[doc = "Transfer using PCS\\[1\\]"] - #[inline(always)] - pub fn is_tx_pcs1(&self) -> bool { - *self == Pcs::TxPcs1 - } - #[doc = "Transfer using PCS\\[2\\]"] - #[inline(always)] - pub fn is_tx_pcs2(&self) -> bool { - *self == Pcs::TxPcs2 - } - #[doc = "Transfer using PCS\\[3\\]"] - #[inline(always)] - pub fn is_tx_pcs3(&self) -> bool { - *self == Pcs::TxPcs3 - } -} -#[doc = "Field `PCS` writer - Peripheral Chip Select"] -pub type PcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pcs, crate::Safe>; -impl<'a, REG> PcsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Transfer using PCS\\[0\\]"] - #[inline(always)] - pub fn tx_pcs0(self) -> &'a mut crate::W { - self.variant(Pcs::TxPcs0) - } - #[doc = "Transfer using PCS\\[1\\]"] - #[inline(always)] - pub fn tx_pcs1(self) -> &'a mut crate::W { - self.variant(Pcs::TxPcs1) - } - #[doc = "Transfer using PCS\\[2\\]"] - #[inline(always)] - pub fn tx_pcs2(self) -> &'a mut crate::W { - self.variant(Pcs::TxPcs2) - } - #[doc = "Transfer using PCS\\[3\\]"] - #[inline(always)] - pub fn tx_pcs3(self) -> &'a mut crate::W { - self.variant(Pcs::TxPcs3) - } -} -#[doc = "Prescaler Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Prescale { - #[doc = "0: Divide by 1"] - Divideby1 = 0, - #[doc = "1: Divide by 2"] - Divideby2 = 1, - #[doc = "2: Divide by 4"] - Divideby4 = 2, - #[doc = "3: Divide by 8"] - Divideby8 = 3, - #[doc = "4: Divide by 16"] - Divideby16 = 4, - #[doc = "5: Divide by 32"] - Divideby32 = 5, - #[doc = "6: Divide by 64"] - Divideby64 = 6, - #[doc = "7: Divide by 128"] - Divideby128 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Prescale) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Prescale { - type Ux = u8; -} -impl crate::IsEnum for Prescale {} -#[doc = "Field `PRESCALE` reader - Prescaler Value"] -pub type PrescaleR = crate::FieldReader; -impl PrescaleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prescale { - match self.bits { - 0 => Prescale::Divideby1, - 1 => Prescale::Divideby2, - 2 => Prescale::Divideby4, - 3 => Prescale::Divideby8, - 4 => Prescale::Divideby16, - 5 => Prescale::Divideby32, - 6 => Prescale::Divideby64, - 7 => Prescale::Divideby128, - _ => unreachable!(), - } - } - #[doc = "Divide by 1"] - #[inline(always)] - pub fn is_divideby1(&self) -> bool { - *self == Prescale::Divideby1 - } - #[doc = "Divide by 2"] - #[inline(always)] - pub fn is_divideby2(&self) -> bool { - *self == Prescale::Divideby2 - } - #[doc = "Divide by 4"] - #[inline(always)] - pub fn is_divideby4(&self) -> bool { - *self == Prescale::Divideby4 - } - #[doc = "Divide by 8"] - #[inline(always)] - pub fn is_divideby8(&self) -> bool { - *self == Prescale::Divideby8 - } - #[doc = "Divide by 16"] - #[inline(always)] - pub fn is_divideby16(&self) -> bool { - *self == Prescale::Divideby16 - } - #[doc = "Divide by 32"] - #[inline(always)] - pub fn is_divideby32(&self) -> bool { - *self == Prescale::Divideby32 - } - #[doc = "Divide by 64"] - #[inline(always)] - pub fn is_divideby64(&self) -> bool { - *self == Prescale::Divideby64 - } - #[doc = "Divide by 128"] - #[inline(always)] - pub fn is_divideby128(&self) -> bool { - *self == Prescale::Divideby128 - } -} -#[doc = "Field `PRESCALE` writer - Prescaler Value"] -pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescale, crate::Safe>; -impl<'a, REG> PrescaleW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Divide by 1"] - #[inline(always)] - pub fn divideby1(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby1) - } - #[doc = "Divide by 2"] - #[inline(always)] - pub fn divideby2(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby2) - } - #[doc = "Divide by 4"] - #[inline(always)] - pub fn divideby4(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby4) - } - #[doc = "Divide by 8"] - #[inline(always)] - pub fn divideby8(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby8) - } - #[doc = "Divide by 16"] - #[inline(always)] - pub fn divideby16(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby16) - } - #[doc = "Divide by 32"] - #[inline(always)] - pub fn divideby32(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby32) - } - #[doc = "Divide by 64"] - #[inline(always)] - pub fn divideby64(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby64) - } - #[doc = "Divide by 128"] - #[inline(always)] - pub fn divideby128(self) -> &'a mut crate::W { - self.variant(Prescale::Divideby128) - } -} -#[doc = "Clock Phase\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cpha { - #[doc = "0: Captured"] - Captured = 0, - #[doc = "1: Changed"] - Changed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cpha) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CPHA` reader - Clock Phase"] -pub type CphaR = crate::BitReader; -impl CphaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpha { - match self.bits { - false => Cpha::Captured, - true => Cpha::Changed, - } - } - #[doc = "Captured"] - #[inline(always)] - pub fn is_captured(&self) -> bool { - *self == Cpha::Captured - } - #[doc = "Changed"] - #[inline(always)] - pub fn is_changed(&self) -> bool { - *self == Cpha::Changed - } -} -#[doc = "Field `CPHA` writer - Clock Phase"] -pub type CphaW<'a, REG> = crate::BitWriter<'a, REG, Cpha>; -impl<'a, REG> CphaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Captured"] - #[inline(always)] - pub fn captured(self) -> &'a mut crate::W { - self.variant(Cpha::Captured) - } - #[doc = "Changed"] - #[inline(always)] - pub fn changed(self) -> &'a mut crate::W { - self.variant(Cpha::Changed) - } -} -#[doc = "Clock Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cpol { - #[doc = "0: Inactive low"] - InactiveLow = 0, - #[doc = "1: Inactive high"] - InactiveHigh = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CPOL` reader - Clock Polarity"] -pub type CpolR = crate::BitReader; -impl CpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpol { - match self.bits { - false => Cpol::InactiveLow, - true => Cpol::InactiveHigh, - } - } - #[doc = "Inactive low"] - #[inline(always)] - pub fn is_inactive_low(&self) -> bool { - *self == Cpol::InactiveLow - } - #[doc = "Inactive high"] - #[inline(always)] - pub fn is_inactive_high(&self) -> bool { - *self == Cpol::InactiveHigh - } -} -#[doc = "Field `CPOL` writer - Clock Polarity"] -pub type CpolW<'a, REG> = crate::BitWriter<'a, REG, Cpol>; -impl<'a, REG> CpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Inactive low"] - #[inline(always)] - pub fn inactive_low(self) -> &'a mut crate::W { - self.variant(Cpol::InactiveLow) - } - #[doc = "Inactive high"] - #[inline(always)] - pub fn inactive_high(self) -> &'a mut crate::W { - self.variant(Cpol::InactiveHigh) - } -} -impl R { - #[doc = "Bits 0:11 - Frame Size"] - #[inline(always)] - pub fn framesz(&self) -> FrameszR { - FrameszR::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:17 - Transfer Width"] - #[inline(always)] - pub fn width(&self) -> WidthR { - WidthR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bit 18 - Transmit Data Mask"] - #[inline(always)] - pub fn txmsk(&self) -> TxmskR { - TxmskR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Receive Data Mask"] - #[inline(always)] - pub fn rxmsk(&self) -> RxmskR { - RxmskR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Continuing Command"] - #[inline(always)] - pub fn contc(&self) -> ContcR { - ContcR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Continuous Transfer"] - #[inline(always)] - pub fn cont(&self) -> ContR { - ContR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Byte Swap"] - #[inline(always)] - pub fn bysw(&self) -> ByswR { - ByswR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - LSB First"] - #[inline(always)] - pub fn lsbf(&self) -> LsbfR { - LsbfR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:25 - Peripheral Chip Select"] - #[inline(always)] - pub fn pcs(&self) -> PcsR { - PcsR::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bits 27:29 - Prescaler Value"] - #[inline(always)] - pub fn prescale(&self) -> PrescaleR { - PrescaleR::new(((self.bits >> 27) & 7) as u8) - } - #[doc = "Bit 30 - Clock Phase"] - #[inline(always)] - pub fn cpha(&self) -> CphaR { - CphaR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Clock Polarity"] - #[inline(always)] - pub fn cpol(&self) -> CpolR { - CpolR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:11 - Frame Size"] - #[inline(always)] - pub fn framesz(&mut self) -> FrameszW { - FrameszW::new(self, 0) - } - #[doc = "Bits 16:17 - Transfer Width"] - #[inline(always)] - pub fn width(&mut self) -> WidthW { - WidthW::new(self, 16) - } - #[doc = "Bit 18 - Transmit Data Mask"] - #[inline(always)] - pub fn txmsk(&mut self) -> TxmskW { - TxmskW::new(self, 18) - } - #[doc = "Bit 19 - Receive Data Mask"] - #[inline(always)] - pub fn rxmsk(&mut self) -> RxmskW { - RxmskW::new(self, 19) - } - #[doc = "Bit 20 - Continuing Command"] - #[inline(always)] - pub fn contc(&mut self) -> ContcW { - ContcW::new(self, 20) - } - #[doc = "Bit 21 - Continuous Transfer"] - #[inline(always)] - pub fn cont(&mut self) -> ContW { - ContW::new(self, 21) - } - #[doc = "Bit 22 - Byte Swap"] - #[inline(always)] - pub fn bysw(&mut self) -> ByswW { - ByswW::new(self, 22) - } - #[doc = "Bit 23 - LSB First"] - #[inline(always)] - pub fn lsbf(&mut self) -> LsbfW { - LsbfW::new(self, 23) - } - #[doc = "Bits 24:25 - Peripheral Chip Select"] - #[inline(always)] - pub fn pcs(&mut self) -> PcsW { - PcsW::new(self, 24) - } - #[doc = "Bits 27:29 - Prescaler Value"] - #[inline(always)] - pub fn prescale(&mut self) -> PrescaleW { - PrescaleW::new(self, 27) - } - #[doc = "Bit 30 - Clock Phase"] - #[inline(always)] - pub fn cpha(&mut self) -> CphaW { - CphaW::new(self, 30) - } - #[doc = "Bit 31 - Clock Polarity"] - #[inline(always)] - pub fn cpol(&mut self) -> CpolW { - CpolW::new(self, 31) - } -} -#[doc = "Transmit Command\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcrSpec; -impl crate::RegisterSpec for TcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] -impl crate::Readable for TcrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] -impl crate::Writable for TcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCR to value 0x1f"] -impl crate::Resettable for TcrSpec { - const RESET_VALUE: u32 = 0x1f; -} diff --git a/mcxa276-pac/src/lpspi0/tdbr.rs b/mcxa276-pac/src/lpspi0/tdbr.rs deleted file mode 100644 index de53f202e..000000000 --- a/mcxa276-pac/src/lpspi0/tdbr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `TDBR[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Transmit Data Burst\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdbr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TdbrSpec; -impl crate::RegisterSpec for TdbrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`tdbr::W`](W) writer structure"] -impl crate::Writable for TdbrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TDBR[%s] to value 0"] -impl crate::Resettable for TdbrSpec {} diff --git a/mcxa276-pac/src/lpspi0/tdr.rs b/mcxa276-pac/src/lpspi0/tdr.rs deleted file mode 100644 index a24e17c8e..000000000 --- a/mcxa276-pac/src/lpspi0/tdr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `TDR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Transmit Data"] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Transmit Data"] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Transmit Data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TdrSpec; -impl crate::RegisterSpec for TdrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"] -impl crate::Writable for TdrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TDR to value 0"] -impl crate::Resettable for TdrSpec {} diff --git a/mcxa276-pac/src/lpspi0/verid.rs b/mcxa276-pac/src/lpspi0/verid.rs deleted file mode 100644 index 2fff415ae..000000000 --- a/mcxa276-pac/src/lpspi0/verid.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Module Identification Number\n\nValue on reset: 4"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "4: Standard feature set supporting a 32-bit shift register."] - Standard = 4, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Module Identification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 4 => Some(Feature::Standard), - _ => None, - } - } - #[doc = "Standard feature set supporting a 32-bit shift register."] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == Feature::Standard - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Module Identification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0200_0004"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0200_0004; -} diff --git a/mcxa276-pac/src/lptmr0.rs b/mcxa276-pac/src/lptmr0.rs deleted file mode 100644 index 234310e3b..000000000 --- a/mcxa276-pac/src/lptmr0.rs +++ /dev/null @@ -1,50 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - csr: Csr, - psr: Psr, - cmr: Cmr, - cnr: Cnr, -} -impl RegisterBlock { - #[doc = "0x00 - Control Status"] - #[inline(always)] - pub const fn csr(&self) -> &Csr { - &self.csr - } - #[doc = "0x04 - Prescaler and Glitch Filter"] - #[inline(always)] - pub const fn psr(&self) -> &Psr { - &self.psr - } - #[doc = "0x08 - Compare"] - #[inline(always)] - pub const fn cmr(&self) -> &Cmr { - &self.cmr - } - #[doc = "0x0c - Counter"] - #[inline(always)] - pub const fn cnr(&self) -> &Cnr { - &self.cnr - } -} -#[doc = "CSR (rw) register accessor: Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`] module"] -#[doc(alias = "CSR")] -pub type Csr = crate::Reg; -#[doc = "Control Status"] -pub mod csr; -#[doc = "PSR (rw) register accessor: Prescaler and Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psr`] module"] -#[doc(alias = "PSR")] -pub type Psr = crate::Reg; -#[doc = "Prescaler and Glitch Filter"] -pub mod psr; -#[doc = "CMR (rw) register accessor: Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`cmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmr`] module"] -#[doc(alias = "CMR")] -pub type Cmr = crate::Reg; -#[doc = "Compare"] -pub mod cmr; -#[doc = "CNR (rw) register accessor: Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnr`] module"] -#[doc(alias = "CNR")] -pub type Cnr = crate::Reg; -#[doc = "Counter"] -pub mod cnr; diff --git a/mcxa276-pac/src/lptmr0/cmr.rs b/mcxa276-pac/src/lptmr0/cmr.rs deleted file mode 100644 index c7bd5de9f..000000000 --- a/mcxa276-pac/src/lptmr0/cmr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CMR` reader"] -pub type R = crate::R; -#[doc = "Register `CMR` writer"] -pub type W = crate::W; -#[doc = "Field `COMPARE` reader - Compare Value"] -pub type CompareR = crate::FieldReader; -#[doc = "Field `COMPARE` writer - Compare Value"] -pub type CompareW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Compare Value"] - #[inline(always)] - pub fn compare(&self) -> CompareR { - CompareR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Compare Value"] - #[inline(always)] - pub fn compare(&mut self) -> CompareW { - CompareW::new(self, 0) - } -} -#[doc = "Compare\n\nYou can [`read`](crate::Reg::read) this register and get [`cmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CmrSpec; -impl crate::RegisterSpec for CmrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cmr::R`](R) reader structure"] -impl crate::Readable for CmrSpec {} -#[doc = "`write(|w| ..)` method takes [`cmr::W`](W) writer structure"] -impl crate::Writable for CmrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CMR to value 0"] -impl crate::Resettable for CmrSpec {} diff --git a/mcxa276-pac/src/lptmr0/cnr.rs b/mcxa276-pac/src/lptmr0/cnr.rs deleted file mode 100644 index ea79ccf62..000000000 --- a/mcxa276-pac/src/lptmr0/cnr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `CNR` reader"] -pub type R = crate::R; -#[doc = "Register `CNR` writer"] -pub type W = crate::W; -#[doc = "Field `COUNTER` reader - Counter Value"] -pub type CounterR = crate::FieldReader; -#[doc = "Field `COUNTER` writer - Counter Value"] -pub type CounterW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Counter Value"] - #[inline(always)] - pub fn counter(&self) -> CounterR { - CounterR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Counter Value"] - #[inline(always)] - pub fn counter(&mut self) -> CounterW { - CounterW::new(self, 0) - } -} -#[doc = "Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CnrSpec; -impl crate::RegisterSpec for CnrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cnr::R`](R) reader structure"] -impl crate::Readable for CnrSpec {} -#[doc = "`write(|w| ..)` method takes [`cnr::W`](W) writer structure"] -impl crate::Writable for CnrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CNR to value 0"] -impl crate::Resettable for CnrSpec {} diff --git a/mcxa276-pac/src/lptmr0/csr.rs b/mcxa276-pac/src/lptmr0/csr.rs deleted file mode 100644 index 5f7b95786..000000000 --- a/mcxa276-pac/src/lptmr0/csr.rs +++ /dev/null @@ -1,559 +0,0 @@ -#[doc = "Register `CSR` reader"] -pub type R = crate::R; -#[doc = "Register `CSR` writer"] -pub type W = crate::W; -#[doc = "Timer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ten { - #[doc = "0: Disable"] - Ten0 = 0, - #[doc = "1: Enable"] - Ten1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TEN` reader - Timer Enable"] -pub type TenR = crate::BitReader; -impl TenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ten { - match self.bits { - false => Ten::Ten0, - true => Ten::Ten1, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_ten0(&self) -> bool { - *self == Ten::Ten0 - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_ten1(&self) -> bool { - *self == Ten::Ten1 - } -} -#[doc = "Field `TEN` writer - Timer Enable"] -pub type TenW<'a, REG> = crate::BitWriter<'a, REG, Ten>; -impl<'a, REG> TenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn ten0(self) -> &'a mut crate::W { - self.variant(Ten::Ten0) - } - #[doc = "Enable"] - #[inline(always)] - pub fn ten1(self) -> &'a mut crate::W { - self.variant(Ten::Ten1) - } -} -#[doc = "Timer Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tms { - #[doc = "0: Time Counter"] - Tms0 = 0, - #[doc = "1: Pulse Counter"] - Tms1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tms) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TMS` reader - Timer Mode Select"] -pub type TmsR = crate::BitReader; -impl TmsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tms { - match self.bits { - false => Tms::Tms0, - true => Tms::Tms1, - } - } - #[doc = "Time Counter"] - #[inline(always)] - pub fn is_tms0(&self) -> bool { - *self == Tms::Tms0 - } - #[doc = "Pulse Counter"] - #[inline(always)] - pub fn is_tms1(&self) -> bool { - *self == Tms::Tms1 - } -} -#[doc = "Field `TMS` writer - Timer Mode Select"] -pub type TmsW<'a, REG> = crate::BitWriter<'a, REG, Tms>; -impl<'a, REG> TmsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Time Counter"] - #[inline(always)] - pub fn tms0(self) -> &'a mut crate::W { - self.variant(Tms::Tms0) - } - #[doc = "Pulse Counter"] - #[inline(always)] - pub fn tms1(self) -> &'a mut crate::W { - self.variant(Tms::Tms1) - } -} -#[doc = "Timer Free-Running Counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tfc { - #[doc = "0: Reset when TCF asserts"] - Tfc0 = 0, - #[doc = "1: Reset on overflow"] - Tfc1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tfc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TFC` reader - Timer Free-Running Counter"] -pub type TfcR = crate::BitReader; -impl TfcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tfc { - match self.bits { - false => Tfc::Tfc0, - true => Tfc::Tfc1, - } - } - #[doc = "Reset when TCF asserts"] - #[inline(always)] - pub fn is_tfc0(&self) -> bool { - *self == Tfc::Tfc0 - } - #[doc = "Reset on overflow"] - #[inline(always)] - pub fn is_tfc1(&self) -> bool { - *self == Tfc::Tfc1 - } -} -#[doc = "Field `TFC` writer - Timer Free-Running Counter"] -pub type TfcW<'a, REG> = crate::BitWriter<'a, REG, Tfc>; -impl<'a, REG> TfcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reset when TCF asserts"] - #[inline(always)] - pub fn tfc0(self) -> &'a mut crate::W { - self.variant(Tfc::Tfc0) - } - #[doc = "Reset on overflow"] - #[inline(always)] - pub fn tfc1(self) -> &'a mut crate::W { - self.variant(Tfc::Tfc1) - } -} -#[doc = "Timer Pin Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpp { - #[doc = "0: Active-high"] - Tpp0 = 0, - #[doc = "1: Active-low"] - Tpp1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPP` reader - Timer Pin Polarity"] -pub type TppR = crate::BitReader; -impl TppR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpp { - match self.bits { - false => Tpp::Tpp0, - true => Tpp::Tpp1, - } - } - #[doc = "Active-high"] - #[inline(always)] - pub fn is_tpp0(&self) -> bool { - *self == Tpp::Tpp0 - } - #[doc = "Active-low"] - #[inline(always)] - pub fn is_tpp1(&self) -> bool { - *self == Tpp::Tpp1 - } -} -#[doc = "Field `TPP` writer - Timer Pin Polarity"] -pub type TppW<'a, REG> = crate::BitWriter<'a, REG, Tpp>; -impl<'a, REG> TppW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active-high"] - #[inline(always)] - pub fn tpp0(self) -> &'a mut crate::W { - self.variant(Tpp::Tpp0) - } - #[doc = "Active-low"] - #[inline(always)] - pub fn tpp1(self) -> &'a mut crate::W { - self.variant(Tpp::Tpp1) - } -} -#[doc = "Timer Pin Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tps { - #[doc = "0: Input 0"] - Tps00 = 0, - #[doc = "1: Input 1"] - Tps01 = 1, - #[doc = "2: Input 2"] - Tps10 = 2, - #[doc = "3: Input 3"] - Tps11 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tps) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tps { - type Ux = u8; -} -impl crate::IsEnum for Tps {} -#[doc = "Field `TPS` reader - Timer Pin Select"] -pub type TpsR = crate::FieldReader; -impl TpsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tps { - match self.bits { - 0 => Tps::Tps00, - 1 => Tps::Tps01, - 2 => Tps::Tps10, - 3 => Tps::Tps11, - _ => unreachable!(), - } - } - #[doc = "Input 0"] - #[inline(always)] - pub fn is_tps00(&self) -> bool { - *self == Tps::Tps00 - } - #[doc = "Input 1"] - #[inline(always)] - pub fn is_tps01(&self) -> bool { - *self == Tps::Tps01 - } - #[doc = "Input 2"] - #[inline(always)] - pub fn is_tps10(&self) -> bool { - *self == Tps::Tps10 - } - #[doc = "Input 3"] - #[inline(always)] - pub fn is_tps11(&self) -> bool { - *self == Tps::Tps11 - } -} -#[doc = "Field `TPS` writer - Timer Pin Select"] -pub type TpsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tps, crate::Safe>; -impl<'a, REG> TpsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Input 0"] - #[inline(always)] - pub fn tps00(self) -> &'a mut crate::W { - self.variant(Tps::Tps00) - } - #[doc = "Input 1"] - #[inline(always)] - pub fn tps01(self) -> &'a mut crate::W { - self.variant(Tps::Tps01) - } - #[doc = "Input 2"] - #[inline(always)] - pub fn tps10(self) -> &'a mut crate::W { - self.variant(Tps::Tps10) - } - #[doc = "Input 3"] - #[inline(always)] - pub fn tps11(self) -> &'a mut crate::W { - self.variant(Tps::Tps11) - } -} -#[doc = "Timer Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie { - #[doc = "0: Disable"] - Tie0 = 0, - #[doc = "1: Enable"] - Tie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE` reader - Timer Interrupt Enable"] -pub type TieR = crate::BitReader; -impl TieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie { - match self.bits { - false => Tie::Tie0, - true => Tie::Tie1, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_tie0(&self) -> bool { - *self == Tie::Tie0 - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_tie1(&self) -> bool { - *self == Tie::Tie1 - } -} -#[doc = "Field `TIE` writer - Timer Interrupt Enable"] -pub type TieW<'a, REG> = crate::BitWriter<'a, REG, Tie>; -impl<'a, REG> TieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn tie0(self) -> &'a mut crate::W { - self.variant(Tie::Tie0) - } - #[doc = "Enable"] - #[inline(always)] - pub fn tie1(self) -> &'a mut crate::W { - self.variant(Tie::Tie1) - } -} -#[doc = "Timer Compare Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tcf { - #[doc = "0: CNR != (CMR + 1)"] - Tcf0 = 0, - #[doc = "1: CNR = (CMR + 1)"] - Tcf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tcf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCF` reader - Timer Compare Flag"] -pub type TcfR = crate::BitReader; -impl TcfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcf { - match self.bits { - false => Tcf::Tcf0, - true => Tcf::Tcf1, - } - } - #[doc = "CNR != (CMR + 1)"] - #[inline(always)] - pub fn is_tcf0(&self) -> bool { - *self == Tcf::Tcf0 - } - #[doc = "CNR = (CMR + 1)"] - #[inline(always)] - pub fn is_tcf1(&self) -> bool { - *self == Tcf::Tcf1 - } -} -#[doc = "Field `TCF` writer - Timer Compare Flag"] -pub type TcfW<'a, REG> = crate::BitWriter1C<'a, REG, Tcf>; -impl<'a, REG> TcfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "CNR != (CMR + 1)"] - #[inline(always)] - pub fn tcf0(self) -> &'a mut crate::W { - self.variant(Tcf::Tcf0) - } - #[doc = "CNR = (CMR + 1)"] - #[inline(always)] - pub fn tcf1(self) -> &'a mut crate::W { - self.variant(Tcf::Tcf1) - } -} -#[doc = "Timer DMA Request Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdre { - #[doc = "0: Disable"] - Trde0 = 0, - #[doc = "1: Enable"] - Trde1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDRE` reader - Timer DMA Request Enable"] -pub type TdreR = crate::BitReader; -impl TdreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdre { - match self.bits { - false => Tdre::Trde0, - true => Tdre::Trde1, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_trde0(&self) -> bool { - *self == Tdre::Trde0 - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_trde1(&self) -> bool { - *self == Tdre::Trde1 - } -} -#[doc = "Field `TDRE` writer - Timer DMA Request Enable"] -pub type TdreW<'a, REG> = crate::BitWriter<'a, REG, Tdre>; -impl<'a, REG> TdreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn trde0(self) -> &'a mut crate::W { - self.variant(Tdre::Trde0) - } - #[doc = "Enable"] - #[inline(always)] - pub fn trde1(self) -> &'a mut crate::W { - self.variant(Tdre::Trde1) - } -} -impl R { - #[doc = "Bit 0 - Timer Enable"] - #[inline(always)] - pub fn ten(&self) -> TenR { - TenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Timer Mode Select"] - #[inline(always)] - pub fn tms(&self) -> TmsR { - TmsR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Timer Free-Running Counter"] - #[inline(always)] - pub fn tfc(&self) -> TfcR { - TfcR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Timer Pin Polarity"] - #[inline(always)] - pub fn tpp(&self) -> TppR { - TppR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - Timer Pin Select"] - #[inline(always)] - pub fn tps(&self) -> TpsR { - TpsR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - Timer Interrupt Enable"] - #[inline(always)] - pub fn tie(&self) -> TieR { - TieR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Timer Compare Flag"] - #[inline(always)] - pub fn tcf(&self) -> TcfR { - TcfR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Timer DMA Request Enable"] - #[inline(always)] - pub fn tdre(&self) -> TdreR { - TdreR::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Timer Enable"] - #[inline(always)] - pub fn ten(&mut self) -> TenW { - TenW::new(self, 0) - } - #[doc = "Bit 1 - Timer Mode Select"] - #[inline(always)] - pub fn tms(&mut self) -> TmsW { - TmsW::new(self, 1) - } - #[doc = "Bit 2 - Timer Free-Running Counter"] - #[inline(always)] - pub fn tfc(&mut self) -> TfcW { - TfcW::new(self, 2) - } - #[doc = "Bit 3 - Timer Pin Polarity"] - #[inline(always)] - pub fn tpp(&mut self) -> TppW { - TppW::new(self, 3) - } - #[doc = "Bits 4:5 - Timer Pin Select"] - #[inline(always)] - pub fn tps(&mut self) -> TpsW { - TpsW::new(self, 4) - } - #[doc = "Bit 6 - Timer Interrupt Enable"] - #[inline(always)] - pub fn tie(&mut self) -> TieW { - TieW::new(self, 6) - } - #[doc = "Bit 7 - Timer Compare Flag"] - #[inline(always)] - pub fn tcf(&mut self) -> TcfW { - TcfW::new(self, 7) - } - #[doc = "Bit 8 - Timer DMA Request Enable"] - #[inline(always)] - pub fn tdre(&mut self) -> TdreW { - TdreW::new(self, 8) - } -} -#[doc = "Control Status\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CsrSpec; -impl crate::RegisterSpec for CsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`csr::R`](R) reader structure"] -impl crate::Readable for CsrSpec {} -#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] -impl crate::Writable for CsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x80; -} -#[doc = "`reset()` method sets CSR to value 0"] -impl crate::Resettable for CsrSpec {} diff --git a/mcxa276-pac/src/lptmr0/psr.rs b/mcxa276-pac/src/lptmr0/psr.rs deleted file mode 100644 index 2bfca7657..000000000 --- a/mcxa276-pac/src/lptmr0/psr.rs +++ /dev/null @@ -1,432 +0,0 @@ -#[doc = "Register `PSR` reader"] -pub type R = crate::R; -#[doc = "Register `PSR` writer"] -pub type W = crate::W; -#[doc = "Prescaler and Glitch Filter Clock Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pcs { - #[doc = "0: Clock 0"] - Pcs00 = 0, - #[doc = "1: Clock 1"] - Pcs01 = 1, - #[doc = "2: Clock 2"] - Pcs10 = 2, - #[doc = "3: Clock 3"] - Pcs11 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pcs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pcs { - type Ux = u8; -} -impl crate::IsEnum for Pcs {} -#[doc = "Field `PCS` reader - Prescaler and Glitch Filter Clock Select"] -pub type PcsR = crate::FieldReader; -impl PcsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pcs { - match self.bits { - 0 => Pcs::Pcs00, - 1 => Pcs::Pcs01, - 2 => Pcs::Pcs10, - 3 => Pcs::Pcs11, - _ => unreachable!(), - } - } - #[doc = "Clock 0"] - #[inline(always)] - pub fn is_pcs00(&self) -> bool { - *self == Pcs::Pcs00 - } - #[doc = "Clock 1"] - #[inline(always)] - pub fn is_pcs01(&self) -> bool { - *self == Pcs::Pcs01 - } - #[doc = "Clock 2"] - #[inline(always)] - pub fn is_pcs10(&self) -> bool { - *self == Pcs::Pcs10 - } - #[doc = "Clock 3"] - #[inline(always)] - pub fn is_pcs11(&self) -> bool { - *self == Pcs::Pcs11 - } -} -#[doc = "Field `PCS` writer - Prescaler and Glitch Filter Clock Select"] -pub type PcsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pcs, crate::Safe>; -impl<'a, REG> PcsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Clock 0"] - #[inline(always)] - pub fn pcs00(self) -> &'a mut crate::W { - self.variant(Pcs::Pcs00) - } - #[doc = "Clock 1"] - #[inline(always)] - pub fn pcs01(self) -> &'a mut crate::W { - self.variant(Pcs::Pcs01) - } - #[doc = "Clock 2"] - #[inline(always)] - pub fn pcs10(self) -> &'a mut crate::W { - self.variant(Pcs::Pcs10) - } - #[doc = "Clock 3"] - #[inline(always)] - pub fn pcs11(self) -> &'a mut crate::W { - self.variant(Pcs::Pcs11) - } -} -#[doc = "Prescaler and Glitch Filter Bypass\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pbyp { - #[doc = "0: Prescaler and glitch filter enable"] - Pbyp0 = 0, - #[doc = "1: Prescaler and glitch filter bypass"] - Pbyp1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pbyp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PBYP` reader - Prescaler and Glitch Filter Bypass"] -pub type PbypR = crate::BitReader; -impl PbypR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pbyp { - match self.bits { - false => Pbyp::Pbyp0, - true => Pbyp::Pbyp1, - } - } - #[doc = "Prescaler and glitch filter enable"] - #[inline(always)] - pub fn is_pbyp0(&self) -> bool { - *self == Pbyp::Pbyp0 - } - #[doc = "Prescaler and glitch filter bypass"] - #[inline(always)] - pub fn is_pbyp1(&self) -> bool { - *self == Pbyp::Pbyp1 - } -} -#[doc = "Field `PBYP` writer - Prescaler and Glitch Filter Bypass"] -pub type PbypW<'a, REG> = crate::BitWriter<'a, REG, Pbyp>; -impl<'a, REG> PbypW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Prescaler and glitch filter enable"] - #[inline(always)] - pub fn pbyp0(self) -> &'a mut crate::W { - self.variant(Pbyp::Pbyp0) - } - #[doc = "Prescaler and glitch filter bypass"] - #[inline(always)] - pub fn pbyp1(self) -> &'a mut crate::W { - self.variant(Pbyp::Pbyp1) - } -} -#[doc = "Prescaler and Glitch Filter Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Prescale { - #[doc = "0: Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"] - Prescale0000 = 0, - #[doc = "1: Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"] - Prescale0001 = 1, - #[doc = "2: Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"] - Prescale0010 = 2, - #[doc = "3: Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"] - Prescale0011 = 3, - #[doc = "4: Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"] - Prescale0100 = 4, - #[doc = "5: Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"] - Prescale0101 = 5, - #[doc = "6: Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"] - Prescale0110 = 6, - #[doc = "7: Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"] - Prescale0111 = 7, - #[doc = "8: Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"] - Prescale1000 = 8, - #[doc = "9: Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"] - Prescale1001 = 9, - #[doc = "10: Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"] - Prescale1010 = 10, - #[doc = "11: Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"] - Prescale1011 = 11, - #[doc = "12: Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"] - Prescale1100 = 12, - #[doc = "13: Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"] - Prescale1101 = 13, - #[doc = "14: Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"] - Prescale1110 = 14, - #[doc = "15: Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"] - Prescale1111 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Prescale) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Prescale { - type Ux = u8; -} -impl crate::IsEnum for Prescale {} -#[doc = "Field `PRESCALE` reader - Prescaler and Glitch Filter Value"] -pub type PrescaleR = crate::FieldReader; -impl PrescaleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prescale { - match self.bits { - 0 => Prescale::Prescale0000, - 1 => Prescale::Prescale0001, - 2 => Prescale::Prescale0010, - 3 => Prescale::Prescale0011, - 4 => Prescale::Prescale0100, - 5 => Prescale::Prescale0101, - 6 => Prescale::Prescale0110, - 7 => Prescale::Prescale0111, - 8 => Prescale::Prescale1000, - 9 => Prescale::Prescale1001, - 10 => Prescale::Prescale1010, - 11 => Prescale::Prescale1011, - 12 => Prescale::Prescale1100, - 13 => Prescale::Prescale1101, - 14 => Prescale::Prescale1110, - 15 => Prescale::Prescale1111, - _ => unreachable!(), - } - } - #[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"] - #[inline(always)] - pub fn is_prescale0000(&self) -> bool { - *self == Prescale::Prescale0000 - } - #[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"] - #[inline(always)] - pub fn is_prescale0001(&self) -> bool { - *self == Prescale::Prescale0001 - } - #[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"] - #[inline(always)] - pub fn is_prescale0010(&self) -> bool { - *self == Prescale::Prescale0010 - } - #[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"] - #[inline(always)] - pub fn is_prescale0011(&self) -> bool { - *self == Prescale::Prescale0011 - } - #[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"] - #[inline(always)] - pub fn is_prescale0100(&self) -> bool { - *self == Prescale::Prescale0100 - } - #[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"] - #[inline(always)] - pub fn is_prescale0101(&self) -> bool { - *self == Prescale::Prescale0101 - } - #[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"] - #[inline(always)] - pub fn is_prescale0110(&self) -> bool { - *self == Prescale::Prescale0110 - } - #[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"] - #[inline(always)] - pub fn is_prescale0111(&self) -> bool { - *self == Prescale::Prescale0111 - } - #[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"] - #[inline(always)] - pub fn is_prescale1000(&self) -> bool { - *self == Prescale::Prescale1000 - } - #[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"] - #[inline(always)] - pub fn is_prescale1001(&self) -> bool { - *self == Prescale::Prescale1001 - } - #[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"] - #[inline(always)] - pub fn is_prescale1010(&self) -> bool { - *self == Prescale::Prescale1010 - } - #[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"] - #[inline(always)] - pub fn is_prescale1011(&self) -> bool { - *self == Prescale::Prescale1011 - } - #[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"] - #[inline(always)] - pub fn is_prescale1100(&self) -> bool { - *self == Prescale::Prescale1100 - } - #[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"] - #[inline(always)] - pub fn is_prescale1101(&self) -> bool { - *self == Prescale::Prescale1101 - } - #[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"] - #[inline(always)] - pub fn is_prescale1110(&self) -> bool { - *self == Prescale::Prescale1110 - } - #[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"] - #[inline(always)] - pub fn is_prescale1111(&self) -> bool { - *self == Prescale::Prescale1111 - } -} -#[doc = "Field `PRESCALE` writer - Prescaler and Glitch Filter Value"] -pub type PrescaleW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescale, crate::Safe>; -impl<'a, REG> PrescaleW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration"] - #[inline(always)] - pub fn prescale0000(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0000) - } - #[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges"] - #[inline(always)] - pub fn prescale0001(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0001) - } - #[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges"] - #[inline(always)] - pub fn prescale0010(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0010) - } - #[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges"] - #[inline(always)] - pub fn prescale0011(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0011) - } - #[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges"] - #[inline(always)] - pub fn prescale0100(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0100) - } - #[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges"] - #[inline(always)] - pub fn prescale0101(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0101) - } - #[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges"] - #[inline(always)] - pub fn prescale0110(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0110) - } - #[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges"] - #[inline(always)] - pub fn prescale0111(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale0111) - } - #[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges"] - #[inline(always)] - pub fn prescale1000(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1000) - } - #[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges"] - #[inline(always)] - pub fn prescale1001(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1001) - } - #[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges"] - #[inline(always)] - pub fn prescale1010(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1010) - } - #[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges"] - #[inline(always)] - pub fn prescale1011(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1011) - } - #[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges"] - #[inline(always)] - pub fn prescale1100(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1100) - } - #[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges"] - #[inline(always)] - pub fn prescale1101(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1101) - } - #[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges"] - #[inline(always)] - pub fn prescale1110(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1110) - } - #[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges"] - #[inline(always)] - pub fn prescale1111(self) -> &'a mut crate::W { - self.variant(Prescale::Prescale1111) - } -} -impl R { - #[doc = "Bits 0:1 - Prescaler and Glitch Filter Clock Select"] - #[inline(always)] - pub fn pcs(&self) -> PcsR { - PcsR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - Prescaler and Glitch Filter Bypass"] - #[inline(always)] - pub fn pbyp(&self) -> PbypR { - PbypR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 3:6 - Prescaler and Glitch Filter Value"] - #[inline(always)] - pub fn prescale(&self) -> PrescaleR { - PrescaleR::new(((self.bits >> 3) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Prescaler and Glitch Filter Clock Select"] - #[inline(always)] - pub fn pcs(&mut self) -> PcsW { - PcsW::new(self, 0) - } - #[doc = "Bit 2 - Prescaler and Glitch Filter Bypass"] - #[inline(always)] - pub fn pbyp(&mut self) -> PbypW { - PbypW::new(self, 2) - } - #[doc = "Bits 3:6 - Prescaler and Glitch Filter Value"] - #[inline(always)] - pub fn prescale(&mut self) -> PrescaleW { - PrescaleW::new(self, 3) - } -} -#[doc = "Prescaler and Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`psr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PsrSpec; -impl crate::RegisterSpec for PsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`psr::R`](R) reader structure"] -impl crate::Readable for PsrSpec {} -#[doc = "`write(|w| ..)` method takes [`psr::W`](W) writer structure"] -impl crate::Writable for PsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PSR to value 0"] -impl crate::Resettable for PsrSpec {} diff --git a/mcxa276-pac/src/lpuart0.rs b/mcxa276-pac/src/lpuart0.rs deleted file mode 100644 index e27eba504..000000000 --- a/mcxa276-pac/src/lpuart0.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - global: Global, - pincfg: Pincfg, - baud: Baud, - stat: Stat, - ctrl: Ctrl, - data: Data, - match_: Match, - modir: Modir, - fifo: Fifo, - water: Water, - dataro: Dataro, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x08 - Global"] - #[inline(always)] - pub const fn global(&self) -> &Global { - &self.global - } - #[doc = "0x0c - Pin Configuration"] - #[inline(always)] - pub const fn pincfg(&self) -> &Pincfg { - &self.pincfg - } - #[doc = "0x10 - Baud Rate"] - #[inline(always)] - pub const fn baud(&self) -> &Baud { - &self.baud - } - #[doc = "0x14 - Status"] - #[inline(always)] - pub const fn stat(&self) -> &Stat { - &self.stat - } - #[doc = "0x18 - Control"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } - #[doc = "0x1c - Data"] - #[inline(always)] - pub const fn data(&self) -> &Data { - &self.data - } - #[doc = "0x20 - Match Address"] - #[inline(always)] - pub const fn match_(&self) -> &Match { - &self.match_ - } - #[doc = "0x24 - MODEM IrDA"] - #[inline(always)] - pub const fn modir(&self) -> &Modir { - &self.modir - } - #[doc = "0x28 - FIFO"] - #[inline(always)] - pub const fn fifo(&self) -> &Fifo { - &self.fifo - } - #[doc = "0x2c - Watermark"] - #[inline(always)] - pub const fn water(&self) -> &Water { - &self.water - } - #[doc = "0x30 - Data Read-Only"] - #[inline(always)] - pub const fn dataro(&self) -> &Dataro { - &self.dataro - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "GLOBAL (rw) register accessor: Global\n\nYou can [`read`](crate::Reg::read) this register and get [`global::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@global`] module"] -#[doc(alias = "GLOBAL")] -pub type Global = crate::Reg; -#[doc = "Global"] -pub mod global; -#[doc = "PINCFG (rw) register accessor: Pin Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pincfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pincfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pincfg`] module"] -#[doc(alias = "PINCFG")] -pub type Pincfg = crate::Reg; -#[doc = "Pin Configuration"] -pub mod pincfg; -#[doc = "BAUD (rw) register accessor: Baud Rate\n\nYou can [`read`](crate::Reg::read) this register and get [`baud::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud`] module"] -#[doc(alias = "BAUD")] -pub type Baud = crate::Reg; -#[doc = "Baud Rate"] -pub mod baud; -#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] -#[doc(alias = "STAT")] -pub type Stat = crate::Reg; -#[doc = "Status"] -pub mod stat; -#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "Control"] -pub mod ctrl; -#[doc = "DATA (rw) register accessor: Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] -#[doc(alias = "DATA")] -pub type Data = crate::Reg; -#[doc = "Data"] -pub mod data; -#[doc = "MATCH (rw) register accessor: Match Address\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_`] module"] -#[doc(alias = "MATCH")] -pub type Match = crate::Reg; -#[doc = "Match Address"] -pub mod match_; -#[doc = "MODIR (rw) register accessor: MODEM IrDA\n\nYou can [`read`](crate::Reg::read) this register and get [`modir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modir`] module"] -#[doc(alias = "MODIR")] -pub type Modir = crate::Reg; -#[doc = "MODEM IrDA"] -pub mod modir; -#[doc = "FIFO (rw) register accessor: FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] module"] -#[doc(alias = "FIFO")] -pub type Fifo = crate::Reg; -#[doc = "FIFO"] -pub mod fifo; -#[doc = "WATER (rw) register accessor: Watermark\n\nYou can [`read`](crate::Reg::read) this register and get [`water::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`water::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@water`] module"] -#[doc(alias = "WATER")] -pub type Water = crate::Reg; -#[doc = "Watermark"] -pub mod water; -#[doc = "DATARO (r) register accessor: Data Read-Only\n\nYou can [`read`](crate::Reg::read) this register and get [`dataro::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataro`] module"] -#[doc(alias = "DATARO")] -pub type Dataro = crate::Reg; -#[doc = "Data Read-Only"] -pub mod dataro; diff --git a/mcxa276-pac/src/lpuart0/baud.rs b/mcxa276-pac/src/lpuart0/baud.rs deleted file mode 100644 index 6329f14dd..000000000 --- a/mcxa276-pac/src/lpuart0/baud.rs +++ /dev/null @@ -1,1260 +0,0 @@ -#[doc = "Register `BAUD` reader"] -pub type R = crate::R; -#[doc = "Register `BAUD` writer"] -pub type W = crate::W; -#[doc = "Field `SBR` reader - Baud Rate Modulo Divisor"] -pub type SbrR = crate::FieldReader; -#[doc = "Field `SBR` writer - Baud Rate Modulo Divisor"] -pub type SbrW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; -#[doc = "Stop Bit Number Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sbns { - #[doc = "0: One stop bit"] - One = 0, - #[doc = "1: Two stop bits"] - Two = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sbns) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SBNS` reader - Stop Bit Number Select"] -pub type SbnsR = crate::BitReader; -impl SbnsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sbns { - match self.bits { - false => Sbns::One, - true => Sbns::Two, - } - } - #[doc = "One stop bit"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Sbns::One - } - #[doc = "Two stop bits"] - #[inline(always)] - pub fn is_two(&self) -> bool { - *self == Sbns::Two - } -} -#[doc = "Field `SBNS` writer - Stop Bit Number Select"] -pub type SbnsW<'a, REG> = crate::BitWriter<'a, REG, Sbns>; -impl<'a, REG> SbnsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "One stop bit"] - #[inline(always)] - pub fn one(self) -> &'a mut crate::W { - self.variant(Sbns::One) - } - #[doc = "Two stop bits"] - #[inline(always)] - pub fn two(self) -> &'a mut crate::W { - self.variant(Sbns::Two) - } -} -#[doc = "RX Input Active Edge Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxedgie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxedgie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEDGIE` reader - RX Input Active Edge Interrupt Enable"] -pub type RxedgieR = crate::BitReader; -impl RxedgieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxedgie { - match self.bits { - false => Rxedgie::Disable, - true => Rxedgie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Rxedgie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Rxedgie::Enable - } -} -#[doc = "Field `RXEDGIE` writer - RX Input Active Edge Interrupt Enable"] -pub type RxedgieW<'a, REG> = crate::BitWriter<'a, REG, Rxedgie>; -impl<'a, REG> RxedgieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Rxedgie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Rxedgie::Enable) - } -} -#[doc = "LIN Break Detect Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lbkdie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lbkdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LBKDIE` reader - LIN Break Detect Interrupt Enable"] -pub type LbkdieR = crate::BitReader; -impl LbkdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lbkdie { - match self.bits { - false => Lbkdie::Disable, - true => Lbkdie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lbkdie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lbkdie::Enable - } -} -#[doc = "Field `LBKDIE` writer - LIN Break Detect Interrupt Enable"] -pub type LbkdieW<'a, REG> = crate::BitWriter<'a, REG, Lbkdie>; -impl<'a, REG> LbkdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lbkdie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lbkdie::Enable) - } -} -#[doc = "Resynchronization Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Resyncdis { - #[doc = "0: Enable"] - Resync = 0, - #[doc = "1: Disable"] - NoResync = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Resyncdis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESYNCDIS` reader - Resynchronization Disable"] -pub type ResyncdisR = crate::BitReader; -impl ResyncdisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Resyncdis { - match self.bits { - false => Resyncdis::Resync, - true => Resyncdis::NoResync, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_resync(&self) -> bool { - *self == Resyncdis::Resync - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_no_resync(&self) -> bool { - *self == Resyncdis::NoResync - } -} -#[doc = "Field `RESYNCDIS` writer - Resynchronization Disable"] -pub type ResyncdisW<'a, REG> = crate::BitWriter<'a, REG, Resyncdis>; -impl<'a, REG> ResyncdisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn resync(self) -> &'a mut crate::W { - self.variant(Resyncdis::Resync) - } - #[doc = "Disable"] - #[inline(always)] - pub fn no_resync(self) -> &'a mut crate::W { - self.variant(Resyncdis::NoResync) - } -} -#[doc = "Both Edge Sampling\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bothedge { - #[doc = "0: Rising edge"] - Disabled = 0, - #[doc = "1: Both rising and falling edges"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bothedge) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BOTHEDGE` reader - Both Edge Sampling"] -pub type BothedgeR = crate::BitReader; -impl BothedgeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bothedge { - match self.bits { - false => Bothedge::Disabled, - true => Bothedge::Enabled, - } - } - #[doc = "Rising edge"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Bothedge::Disabled - } - #[doc = "Both rising and falling edges"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Bothedge::Enabled - } -} -#[doc = "Field `BOTHEDGE` writer - Both Edge Sampling"] -pub type BothedgeW<'a, REG> = crate::BitWriter<'a, REG, Bothedge>; -impl<'a, REG> BothedgeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Rising edge"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Bothedge::Disabled) - } - #[doc = "Both rising and falling edges"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Bothedge::Enabled) - } -} -#[doc = "Match Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Matcfg { - #[doc = "0: Address match wake-up"] - AddrMatch = 0, - #[doc = "1: Idle match wake-up"] - IdleMatch = 1, - #[doc = "2: Match on and match off"] - OnoffMatch = 2, - #[doc = "3: Enables RWU on data match and match on or off for the transmitter CTS input"] - RwuMatch = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Matcfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Matcfg { - type Ux = u8; -} -impl crate::IsEnum for Matcfg {} -#[doc = "Field `MATCFG` reader - Match Configuration"] -pub type MatcfgR = crate::FieldReader; -impl MatcfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Matcfg { - match self.bits { - 0 => Matcfg::AddrMatch, - 1 => Matcfg::IdleMatch, - 2 => Matcfg::OnoffMatch, - 3 => Matcfg::RwuMatch, - _ => unreachable!(), - } - } - #[doc = "Address match wake-up"] - #[inline(always)] - pub fn is_addr_match(&self) -> bool { - *self == Matcfg::AddrMatch - } - #[doc = "Idle match wake-up"] - #[inline(always)] - pub fn is_idle_match(&self) -> bool { - *self == Matcfg::IdleMatch - } - #[doc = "Match on and match off"] - #[inline(always)] - pub fn is_onoff_match(&self) -> bool { - *self == Matcfg::OnoffMatch - } - #[doc = "Enables RWU on data match and match on or off for the transmitter CTS input"] - #[inline(always)] - pub fn is_rwu_match(&self) -> bool { - *self == Matcfg::RwuMatch - } -} -#[doc = "Field `MATCFG` writer - Match Configuration"] -pub type MatcfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Matcfg, crate::Safe>; -impl<'a, REG> MatcfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Address match wake-up"] - #[inline(always)] - pub fn addr_match(self) -> &'a mut crate::W { - self.variant(Matcfg::AddrMatch) - } - #[doc = "Idle match wake-up"] - #[inline(always)] - pub fn idle_match(self) -> &'a mut crate::W { - self.variant(Matcfg::IdleMatch) - } - #[doc = "Match on and match off"] - #[inline(always)] - pub fn onoff_match(self) -> &'a mut crate::W { - self.variant(Matcfg::OnoffMatch) - } - #[doc = "Enables RWU on data match and match on or off for the transmitter CTS input"] - #[inline(always)] - pub fn rwu_match(self) -> &'a mut crate::W { - self.variant(Matcfg::RwuMatch) - } -} -#[doc = "Receiver Idle DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ridmae { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ridmae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RIDMAE` reader - Receiver Idle DMA Enable"] -pub type RidmaeR = crate::BitReader; -impl RidmaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ridmae { - match self.bits { - false => Ridmae::Disabled, - true => Ridmae::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ridmae::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ridmae::Enabled - } -} -#[doc = "Field `RIDMAE` writer - Receiver Idle DMA Enable"] -pub type RidmaeW<'a, REG> = crate::BitWriter<'a, REG, Ridmae>; -impl<'a, REG> RidmaeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ridmae::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ridmae::Enabled) - } -} -#[doc = "Receiver Full DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdmae { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdmae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDMAE` reader - Receiver Full DMA Enable"] -pub type RdmaeR = crate::BitReader; -impl RdmaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdmae { - match self.bits { - false => Rdmae::Disabled, - true => Rdmae::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rdmae::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rdmae::Enabled - } -} -#[doc = "Field `RDMAE` writer - Receiver Full DMA Enable"] -pub type RdmaeW<'a, REG> = crate::BitWriter<'a, REG, Rdmae>; -impl<'a, REG> RdmaeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rdmae::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rdmae::Enabled) - } -} -#[doc = "Transmitter DMA Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdmae { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdmae) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDMAE` reader - Transmitter DMA Enable"] -pub type TdmaeR = crate::BitReader; -impl TdmaeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdmae { - match self.bits { - false => Tdmae::Disabled, - true => Tdmae::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tdmae::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tdmae::Enabled - } -} -#[doc = "Field `TDMAE` writer - Transmitter DMA Enable"] -pub type TdmaeW<'a, REG> = crate::BitWriter<'a, REG, Tdmae>; -impl<'a, REG> TdmaeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tdmae::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tdmae::Enabled) - } -} -#[doc = "Oversampling Ratio\n\nValue on reset: 15"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Osr { - #[doc = "0: Results in an OSR of 16"] - Default = 0, - #[doc = "3: Results in an OSR of 4 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - Osr4 = 3, - #[doc = "4: Results in an OSR of 5 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - Osr5 = 4, - #[doc = "5: Results in an OSR of 6 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - Osr6 = 5, - #[doc = "6: Results in an OSR of 7 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - Osr7 = 6, - #[doc = "7: Results in an OSR of 8"] - Osr8 = 7, - #[doc = "8: Results in an OSR of 9"] - Osr9 = 8, - #[doc = "9: Results in an OSR of 10"] - Osr10 = 9, - #[doc = "10: Results in an OSR of 11"] - Osr11 = 10, - #[doc = "11: Results in an OSR of 12"] - Osr12 = 11, - #[doc = "12: Results in an OSR of 13"] - Osr13 = 12, - #[doc = "13: Results in an OSR of 14"] - Osr14 = 13, - #[doc = "14: Results in an OSR of 15"] - Osr15 = 14, - #[doc = "15: Results in an OSR of 16"] - Osr16 = 15, - #[doc = "16: Results in an OSR of 17"] - Osr17 = 16, - #[doc = "17: Results in an OSR of 18"] - Osr18 = 17, - #[doc = "18: Results in an OSR of 19"] - Osr19 = 18, - #[doc = "19: Results in an OSR of 20"] - Osr20 = 19, - #[doc = "20: Results in an OSR of 21"] - Osr21 = 20, - #[doc = "21: Results in an OSR of 22"] - Osr22 = 21, - #[doc = "22: Results in an OSR of 23"] - Osr23 = 22, - #[doc = "23: Results in an OSR of 24"] - Osr24 = 23, - #[doc = "24: Results in an OSR of 25"] - Osr25 = 24, - #[doc = "25: Results in an OSR of 26"] - Osr26 = 25, - #[doc = "26: Results in an OSR of 27"] - Osr27 = 26, - #[doc = "27: Results in an OSR of 28"] - Osr28 = 27, - #[doc = "28: Results in an OSR of 29"] - Osr29 = 28, - #[doc = "29: Results in an OSR of 30"] - Osr30 = 29, - #[doc = "30: Results in an OSR of 31"] - Osr31 = 30, - #[doc = "31: Results in an OSR of 32"] - Osr32 = 31, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Osr) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Osr { - type Ux = u8; -} -impl crate::IsEnum for Osr {} -#[doc = "Field `OSR` reader - Oversampling Ratio"] -pub type OsrR = crate::FieldReader; -impl OsrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Osr::Default), - 3 => Some(Osr::Osr4), - 4 => Some(Osr::Osr5), - 5 => Some(Osr::Osr6), - 6 => Some(Osr::Osr7), - 7 => Some(Osr::Osr8), - 8 => Some(Osr::Osr9), - 9 => Some(Osr::Osr10), - 10 => Some(Osr::Osr11), - 11 => Some(Osr::Osr12), - 12 => Some(Osr::Osr13), - 13 => Some(Osr::Osr14), - 14 => Some(Osr::Osr15), - 15 => Some(Osr::Osr16), - 16 => Some(Osr::Osr17), - 17 => Some(Osr::Osr18), - 18 => Some(Osr::Osr19), - 19 => Some(Osr::Osr20), - 20 => Some(Osr::Osr21), - 21 => Some(Osr::Osr22), - 22 => Some(Osr::Osr23), - 23 => Some(Osr::Osr24), - 24 => Some(Osr::Osr25), - 25 => Some(Osr::Osr26), - 26 => Some(Osr::Osr27), - 27 => Some(Osr::Osr28), - 28 => Some(Osr::Osr29), - 29 => Some(Osr::Osr30), - 30 => Some(Osr::Osr31), - 31 => Some(Osr::Osr32), - _ => None, - } - } - #[doc = "Results in an OSR of 16"] - #[inline(always)] - pub fn is_default(&self) -> bool { - *self == Osr::Default - } - #[doc = "Results in an OSR of 4 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn is_osr_4(&self) -> bool { - *self == Osr::Osr4 - } - #[doc = "Results in an OSR of 5 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn is_osr_5(&self) -> bool { - *self == Osr::Osr5 - } - #[doc = "Results in an OSR of 6 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn is_osr_6(&self) -> bool { - *self == Osr::Osr6 - } - #[doc = "Results in an OSR of 7 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn is_osr_7(&self) -> bool { - *self == Osr::Osr7 - } - #[doc = "Results in an OSR of 8"] - #[inline(always)] - pub fn is_osr_8(&self) -> bool { - *self == Osr::Osr8 - } - #[doc = "Results in an OSR of 9"] - #[inline(always)] - pub fn is_osr_9(&self) -> bool { - *self == Osr::Osr9 - } - #[doc = "Results in an OSR of 10"] - #[inline(always)] - pub fn is_osr_10(&self) -> bool { - *self == Osr::Osr10 - } - #[doc = "Results in an OSR of 11"] - #[inline(always)] - pub fn is_osr_11(&self) -> bool { - *self == Osr::Osr11 - } - #[doc = "Results in an OSR of 12"] - #[inline(always)] - pub fn is_osr_12(&self) -> bool { - *self == Osr::Osr12 - } - #[doc = "Results in an OSR of 13"] - #[inline(always)] - pub fn is_osr_13(&self) -> bool { - *self == Osr::Osr13 - } - #[doc = "Results in an OSR of 14"] - #[inline(always)] - pub fn is_osr_14(&self) -> bool { - *self == Osr::Osr14 - } - #[doc = "Results in an OSR of 15"] - #[inline(always)] - pub fn is_osr_15(&self) -> bool { - *self == Osr::Osr15 - } - #[doc = "Results in an OSR of 16"] - #[inline(always)] - pub fn is_osr_16(&self) -> bool { - *self == Osr::Osr16 - } - #[doc = "Results in an OSR of 17"] - #[inline(always)] - pub fn is_osr_17(&self) -> bool { - *self == Osr::Osr17 - } - #[doc = "Results in an OSR of 18"] - #[inline(always)] - pub fn is_osr_18(&self) -> bool { - *self == Osr::Osr18 - } - #[doc = "Results in an OSR of 19"] - #[inline(always)] - pub fn is_osr_19(&self) -> bool { - *self == Osr::Osr19 - } - #[doc = "Results in an OSR of 20"] - #[inline(always)] - pub fn is_osr_20(&self) -> bool { - *self == Osr::Osr20 - } - #[doc = "Results in an OSR of 21"] - #[inline(always)] - pub fn is_osr_21(&self) -> bool { - *self == Osr::Osr21 - } - #[doc = "Results in an OSR of 22"] - #[inline(always)] - pub fn is_osr_22(&self) -> bool { - *self == Osr::Osr22 - } - #[doc = "Results in an OSR of 23"] - #[inline(always)] - pub fn is_osr_23(&self) -> bool { - *self == Osr::Osr23 - } - #[doc = "Results in an OSR of 24"] - #[inline(always)] - pub fn is_osr_24(&self) -> bool { - *self == Osr::Osr24 - } - #[doc = "Results in an OSR of 25"] - #[inline(always)] - pub fn is_osr_25(&self) -> bool { - *self == Osr::Osr25 - } - #[doc = "Results in an OSR of 26"] - #[inline(always)] - pub fn is_osr_26(&self) -> bool { - *self == Osr::Osr26 - } - #[doc = "Results in an OSR of 27"] - #[inline(always)] - pub fn is_osr_27(&self) -> bool { - *self == Osr::Osr27 - } - #[doc = "Results in an OSR of 28"] - #[inline(always)] - pub fn is_osr_28(&self) -> bool { - *self == Osr::Osr28 - } - #[doc = "Results in an OSR of 29"] - #[inline(always)] - pub fn is_osr_29(&self) -> bool { - *self == Osr::Osr29 - } - #[doc = "Results in an OSR of 30"] - #[inline(always)] - pub fn is_osr_30(&self) -> bool { - *self == Osr::Osr30 - } - #[doc = "Results in an OSR of 31"] - #[inline(always)] - pub fn is_osr_31(&self) -> bool { - *self == Osr::Osr31 - } - #[doc = "Results in an OSR of 32"] - #[inline(always)] - pub fn is_osr_32(&self) -> bool { - *self == Osr::Osr32 - } -} -#[doc = "Field `OSR` writer - Oversampling Ratio"] -pub type OsrW<'a, REG> = crate::FieldWriter<'a, REG, 5, Osr>; -impl<'a, REG> OsrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Results in an OSR of 16"] - #[inline(always)] - pub fn default(self) -> &'a mut crate::W { - self.variant(Osr::Default) - } - #[doc = "Results in an OSR of 4 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn osr_4(self) -> &'a mut crate::W { - self.variant(Osr::Osr4) - } - #[doc = "Results in an OSR of 5 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn osr_5(self) -> &'a mut crate::W { - self.variant(Osr::Osr5) - } - #[doc = "Results in an OSR of 6 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn osr_6(self) -> &'a mut crate::W { - self.variant(Osr::Osr6) - } - #[doc = "Results in an OSR of 7 (requires BAUD\\[BOTHEDGE\\] to be 1)"] - #[inline(always)] - pub fn osr_7(self) -> &'a mut crate::W { - self.variant(Osr::Osr7) - } - #[doc = "Results in an OSR of 8"] - #[inline(always)] - pub fn osr_8(self) -> &'a mut crate::W { - self.variant(Osr::Osr8) - } - #[doc = "Results in an OSR of 9"] - #[inline(always)] - pub fn osr_9(self) -> &'a mut crate::W { - self.variant(Osr::Osr9) - } - #[doc = "Results in an OSR of 10"] - #[inline(always)] - pub fn osr_10(self) -> &'a mut crate::W { - self.variant(Osr::Osr10) - } - #[doc = "Results in an OSR of 11"] - #[inline(always)] - pub fn osr_11(self) -> &'a mut crate::W { - self.variant(Osr::Osr11) - } - #[doc = "Results in an OSR of 12"] - #[inline(always)] - pub fn osr_12(self) -> &'a mut crate::W { - self.variant(Osr::Osr12) - } - #[doc = "Results in an OSR of 13"] - #[inline(always)] - pub fn osr_13(self) -> &'a mut crate::W { - self.variant(Osr::Osr13) - } - #[doc = "Results in an OSR of 14"] - #[inline(always)] - pub fn osr_14(self) -> &'a mut crate::W { - self.variant(Osr::Osr14) - } - #[doc = "Results in an OSR of 15"] - #[inline(always)] - pub fn osr_15(self) -> &'a mut crate::W { - self.variant(Osr::Osr15) - } - #[doc = "Results in an OSR of 16"] - #[inline(always)] - pub fn osr_16(self) -> &'a mut crate::W { - self.variant(Osr::Osr16) - } - #[doc = "Results in an OSR of 17"] - #[inline(always)] - pub fn osr_17(self) -> &'a mut crate::W { - self.variant(Osr::Osr17) - } - #[doc = "Results in an OSR of 18"] - #[inline(always)] - pub fn osr_18(self) -> &'a mut crate::W { - self.variant(Osr::Osr18) - } - #[doc = "Results in an OSR of 19"] - #[inline(always)] - pub fn osr_19(self) -> &'a mut crate::W { - self.variant(Osr::Osr19) - } - #[doc = "Results in an OSR of 20"] - #[inline(always)] - pub fn osr_20(self) -> &'a mut crate::W { - self.variant(Osr::Osr20) - } - #[doc = "Results in an OSR of 21"] - #[inline(always)] - pub fn osr_21(self) -> &'a mut crate::W { - self.variant(Osr::Osr21) - } - #[doc = "Results in an OSR of 22"] - #[inline(always)] - pub fn osr_22(self) -> &'a mut crate::W { - self.variant(Osr::Osr22) - } - #[doc = "Results in an OSR of 23"] - #[inline(always)] - pub fn osr_23(self) -> &'a mut crate::W { - self.variant(Osr::Osr23) - } - #[doc = "Results in an OSR of 24"] - #[inline(always)] - pub fn osr_24(self) -> &'a mut crate::W { - self.variant(Osr::Osr24) - } - #[doc = "Results in an OSR of 25"] - #[inline(always)] - pub fn osr_25(self) -> &'a mut crate::W { - self.variant(Osr::Osr25) - } - #[doc = "Results in an OSR of 26"] - #[inline(always)] - pub fn osr_26(self) -> &'a mut crate::W { - self.variant(Osr::Osr26) - } - #[doc = "Results in an OSR of 27"] - #[inline(always)] - pub fn osr_27(self) -> &'a mut crate::W { - self.variant(Osr::Osr27) - } - #[doc = "Results in an OSR of 28"] - #[inline(always)] - pub fn osr_28(self) -> &'a mut crate::W { - self.variant(Osr::Osr28) - } - #[doc = "Results in an OSR of 29"] - #[inline(always)] - pub fn osr_29(self) -> &'a mut crate::W { - self.variant(Osr::Osr29) - } - #[doc = "Results in an OSR of 30"] - #[inline(always)] - pub fn osr_30(self) -> &'a mut crate::W { - self.variant(Osr::Osr30) - } - #[doc = "Results in an OSR of 31"] - #[inline(always)] - pub fn osr_31(self) -> &'a mut crate::W { - self.variant(Osr::Osr31) - } - #[doc = "Results in an OSR of 32"] - #[inline(always)] - pub fn osr_32(self) -> &'a mut crate::W { - self.variant(Osr::Osr32) - } -} -#[doc = "10-Bit Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum M10 { - #[doc = "0: Receiver and transmitter use 7-bit to 9-bit data characters"] - Disabled = 0, - #[doc = "1: Receiver and transmitter use 10-bit data characters"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: M10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `M10` reader - 10-Bit Mode Select"] -pub type M10R = crate::BitReader; -impl M10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> M10 { - match self.bits { - false => M10::Disabled, - true => M10::Enabled, - } - } - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == M10::Disabled - } - #[doc = "Receiver and transmitter use 10-bit data characters"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == M10::Enabled - } -} -#[doc = "Field `M10` writer - 10-Bit Mode Select"] -pub type M10W<'a, REG> = crate::BitWriter<'a, REG, M10>; -impl<'a, REG> M10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Receiver and transmitter use 7-bit to 9-bit data characters"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(M10::Disabled) - } - #[doc = "Receiver and transmitter use 10-bit data characters"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(M10::Enabled) - } -} -#[doc = "Match Address Mode Enable 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Maen2 { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Maen2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MAEN2` reader - Match Address Mode Enable 2"] -pub type Maen2R = crate::BitReader; -impl Maen2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Maen2 { - match self.bits { - false => Maen2::Disabled, - true => Maen2::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Maen2::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Maen2::Enabled - } -} -#[doc = "Field `MAEN2` writer - Match Address Mode Enable 2"] -pub type Maen2W<'a, REG> = crate::BitWriter<'a, REG, Maen2>; -impl<'a, REG> Maen2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Maen2::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Maen2::Enabled) - } -} -#[doc = "Match Address Mode Enable 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Maen1 { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Maen1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MAEN1` reader - Match Address Mode Enable 1"] -pub type Maen1R = crate::BitReader; -impl Maen1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Maen1 { - match self.bits { - false => Maen1::Disabled, - true => Maen1::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Maen1::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Maen1::Enabled - } -} -#[doc = "Field `MAEN1` writer - Match Address Mode Enable 1"] -pub type Maen1W<'a, REG> = crate::BitWriter<'a, REG, Maen1>; -impl<'a, REG> Maen1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Maen1::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Maen1::Enabled) - } -} -impl R { - #[doc = "Bits 0:12 - Baud Rate Modulo Divisor"] - #[inline(always)] - pub fn sbr(&self) -> SbrR { - SbrR::new((self.bits & 0x1fff) as u16) - } - #[doc = "Bit 13 - Stop Bit Number Select"] - #[inline(always)] - pub fn sbns(&self) -> SbnsR { - SbnsR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - RX Input Active Edge Interrupt Enable"] - #[inline(always)] - pub fn rxedgie(&self) -> RxedgieR { - RxedgieR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - LIN Break Detect Interrupt Enable"] - #[inline(always)] - pub fn lbkdie(&self) -> LbkdieR { - LbkdieR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Resynchronization Disable"] - #[inline(always)] - pub fn resyncdis(&self) -> ResyncdisR { - ResyncdisR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Both Edge Sampling"] - #[inline(always)] - pub fn bothedge(&self) -> BothedgeR { - BothedgeR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bits 18:19 - Match Configuration"] - #[inline(always)] - pub fn matcfg(&self) -> MatcfgR { - MatcfgR::new(((self.bits >> 18) & 3) as u8) - } - #[doc = "Bit 20 - Receiver Idle DMA Enable"] - #[inline(always)] - pub fn ridmae(&self) -> RidmaeR { - RidmaeR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Receiver Full DMA Enable"] - #[inline(always)] - pub fn rdmae(&self) -> RdmaeR { - RdmaeR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 23 - Transmitter DMA Enable"] - #[inline(always)] - pub fn tdmae(&self) -> TdmaeR { - TdmaeR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:28 - Oversampling Ratio"] - #[inline(always)] - pub fn osr(&self) -> OsrR { - OsrR::new(((self.bits >> 24) & 0x1f) as u8) - } - #[doc = "Bit 29 - 10-Bit Mode Select"] - #[inline(always)] - pub fn m10(&self) -> M10R { - M10R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Match Address Mode Enable 2"] - #[inline(always)] - pub fn maen2(&self) -> Maen2R { - Maen2R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Match Address Mode Enable 1"] - #[inline(always)] - pub fn maen1(&self) -> Maen1R { - Maen1R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:12 - Baud Rate Modulo Divisor"] - #[inline(always)] - pub fn sbr(&mut self) -> SbrW { - SbrW::new(self, 0) - } - #[doc = "Bit 13 - Stop Bit Number Select"] - #[inline(always)] - pub fn sbns(&mut self) -> SbnsW { - SbnsW::new(self, 13) - } - #[doc = "Bit 14 - RX Input Active Edge Interrupt Enable"] - #[inline(always)] - pub fn rxedgie(&mut self) -> RxedgieW { - RxedgieW::new(self, 14) - } - #[doc = "Bit 15 - LIN Break Detect Interrupt Enable"] - #[inline(always)] - pub fn lbkdie(&mut self) -> LbkdieW { - LbkdieW::new(self, 15) - } - #[doc = "Bit 16 - Resynchronization Disable"] - #[inline(always)] - pub fn resyncdis(&mut self) -> ResyncdisW { - ResyncdisW::new(self, 16) - } - #[doc = "Bit 17 - Both Edge Sampling"] - #[inline(always)] - pub fn bothedge(&mut self) -> BothedgeW { - BothedgeW::new(self, 17) - } - #[doc = "Bits 18:19 - Match Configuration"] - #[inline(always)] - pub fn matcfg(&mut self) -> MatcfgW { - MatcfgW::new(self, 18) - } - #[doc = "Bit 20 - Receiver Idle DMA Enable"] - #[inline(always)] - pub fn ridmae(&mut self) -> RidmaeW { - RidmaeW::new(self, 20) - } - #[doc = "Bit 21 - Receiver Full DMA Enable"] - #[inline(always)] - pub fn rdmae(&mut self) -> RdmaeW { - RdmaeW::new(self, 21) - } - #[doc = "Bit 23 - Transmitter DMA Enable"] - #[inline(always)] - pub fn tdmae(&mut self) -> TdmaeW { - TdmaeW::new(self, 23) - } - #[doc = "Bits 24:28 - Oversampling Ratio"] - #[inline(always)] - pub fn osr(&mut self) -> OsrW { - OsrW::new(self, 24) - } - #[doc = "Bit 29 - 10-Bit Mode Select"] - #[inline(always)] - pub fn m10(&mut self) -> M10W { - M10W::new(self, 29) - } - #[doc = "Bit 30 - Match Address Mode Enable 2"] - #[inline(always)] - pub fn maen2(&mut self) -> Maen2W { - Maen2W::new(self, 30) - } - #[doc = "Bit 31 - Match Address Mode Enable 1"] - #[inline(always)] - pub fn maen1(&mut self) -> Maen1W { - Maen1W::new(self, 31) - } -} -#[doc = "Baud Rate\n\nYou can [`read`](crate::Reg::read) this register and get [`baud::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct BaudSpec; -impl crate::RegisterSpec for BaudSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`baud::R`](R) reader structure"] -impl crate::Readable for BaudSpec {} -#[doc = "`write(|w| ..)` method takes [`baud::W`](W) writer structure"] -impl crate::Writable for BaudSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BAUD to value 0x0f00_0004"] -impl crate::Resettable for BaudSpec { - const RESET_VALUE: u32 = 0x0f00_0004; -} diff --git a/mcxa276-pac/src/lpuart0/ctrl.rs b/mcxa276-pac/src/lpuart0/ctrl.rs deleted file mode 100644 index 0154d1537..000000000 --- a/mcxa276-pac/src/lpuart0/ctrl.rs +++ /dev/null @@ -1,1835 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "Parity Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pt { - #[doc = "0: Even parity"] - Even = 0, - #[doc = "1: Odd parity"] - Odd = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PT` reader - Parity Type"] -pub type PtR = crate::BitReader; -impl PtR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pt { - match self.bits { - false => Pt::Even, - true => Pt::Odd, - } - } - #[doc = "Even parity"] - #[inline(always)] - pub fn is_even(&self) -> bool { - *self == Pt::Even - } - #[doc = "Odd parity"] - #[inline(always)] - pub fn is_odd(&self) -> bool { - *self == Pt::Odd - } -} -#[doc = "Field `PT` writer - Parity Type"] -pub type PtW<'a, REG> = crate::BitWriter<'a, REG, Pt>; -impl<'a, REG> PtW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Even parity"] - #[inline(always)] - pub fn even(self) -> &'a mut crate::W { - self.variant(Pt::Even) - } - #[doc = "Odd parity"] - #[inline(always)] - pub fn odd(self) -> &'a mut crate::W { - self.variant(Pt::Odd) - } -} -#[doc = "Parity Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Parity Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Disabled, - true => Pe::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pe::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pe::Enabled - } -} -#[doc = "Field `PE` writer - Parity Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pe::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pe::Enabled) - } -} -#[doc = "Idle Line Type Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ilt { - #[doc = "0: After the start bit"] - FromStart = 0, - #[doc = "1: After the stop bit"] - FromStop = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ilt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ILT` reader - Idle Line Type Select"] -pub type IltR = crate::BitReader; -impl IltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ilt { - match self.bits { - false => Ilt::FromStart, - true => Ilt::FromStop, - } - } - #[doc = "After the start bit"] - #[inline(always)] - pub fn is_from_start(&self) -> bool { - *self == Ilt::FromStart - } - #[doc = "After the stop bit"] - #[inline(always)] - pub fn is_from_stop(&self) -> bool { - *self == Ilt::FromStop - } -} -#[doc = "Field `ILT` writer - Idle Line Type Select"] -pub type IltW<'a, REG> = crate::BitWriter<'a, REG, Ilt>; -impl<'a, REG> IltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "After the start bit"] - #[inline(always)] - pub fn from_start(self) -> &'a mut crate::W { - self.variant(Ilt::FromStart) - } - #[doc = "After the stop bit"] - #[inline(always)] - pub fn from_stop(self) -> &'a mut crate::W { - self.variant(Ilt::FromStop) - } -} -#[doc = "Receiver Wake-Up Method Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wake { - #[doc = "0: Idle"] - Idle = 0, - #[doc = "1: Mark"] - Mark = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wake) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAKE` reader - Receiver Wake-Up Method Select"] -pub type WakeR = crate::BitReader; -impl WakeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wake { - match self.bits { - false => Wake::Idle, - true => Wake::Mark, - } - } - #[doc = "Idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Wake::Idle - } - #[doc = "Mark"] - #[inline(always)] - pub fn is_mark(&self) -> bool { - *self == Wake::Mark - } -} -#[doc = "Field `WAKE` writer - Receiver Wake-Up Method Select"] -pub type WakeW<'a, REG> = crate::BitWriter<'a, REG, Wake>; -impl<'a, REG> WakeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Idle"] - #[inline(always)] - pub fn idle(self) -> &'a mut crate::W { - self.variant(Wake::Idle) - } - #[doc = "Mark"] - #[inline(always)] - pub fn mark(self) -> &'a mut crate::W { - self.variant(Wake::Mark) - } -} -#[doc = "9-Bit Or 8-Bit Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum M { - #[doc = "0: 8-bit"] - Data8 = 0, - #[doc = "1: 9-bit"] - Data9 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: M) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `M` reader - 9-Bit Or 8-Bit Mode Select"] -pub type MR = crate::BitReader; -impl MR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> M { - match self.bits { - false => M::Data8, - true => M::Data9, - } - } - #[doc = "8-bit"] - #[inline(always)] - pub fn is_data8(&self) -> bool { - *self == M::Data8 - } - #[doc = "9-bit"] - #[inline(always)] - pub fn is_data9(&self) -> bool { - *self == M::Data9 - } -} -#[doc = "Field `M` writer - 9-Bit Or 8-Bit Mode Select"] -pub type MW<'a, REG> = crate::BitWriter<'a, REG, M>; -impl<'a, REG> MW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "8-bit"] - #[inline(always)] - pub fn data8(self) -> &'a mut crate::W { - self.variant(M::Data8) - } - #[doc = "9-bit"] - #[inline(always)] - pub fn data9(self) -> &'a mut crate::W { - self.variant(M::Data9) - } -} -#[doc = "Receiver Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rsrc { - #[doc = "0: Internal Loopback mode"] - NoEffect = 0, - #[doc = "1: Single-wire mode"] - Onewire = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rsrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RSRC` reader - Receiver Source Select"] -pub type RsrcR = crate::BitReader; -impl RsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rsrc { - match self.bits { - false => Rsrc::NoEffect, - true => Rsrc::Onewire, - } - } - #[doc = "Internal Loopback mode"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rsrc::NoEffect - } - #[doc = "Single-wire mode"] - #[inline(always)] - pub fn is_onewire(&self) -> bool { - *self == Rsrc::Onewire - } -} -#[doc = "Field `RSRC` writer - Receiver Source Select"] -pub type RsrcW<'a, REG> = crate::BitWriter<'a, REG, Rsrc>; -impl<'a, REG> RsrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Internal Loopback mode"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rsrc::NoEffect) - } - #[doc = "Single-wire mode"] - #[inline(always)] - pub fn onewire(self) -> &'a mut crate::W { - self.variant(Rsrc::Onewire) - } -} -#[doc = "Doze Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dozeen { - #[doc = "0: Enable"] - Enabled = 0, - #[doc = "1: Disable"] - Disabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dozeen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DOZEEN` reader - Doze Mode"] -pub type DozeenR = crate::BitReader; -impl DozeenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dozeen { - match self.bits { - false => Dozeen::Enabled, - true => Dozeen::Disabled, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dozeen::Enabled - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dozeen::Disabled - } -} -#[doc = "Field `DOZEEN` writer - Doze Mode"] -pub type DozeenW<'a, REG> = crate::BitWriter<'a, REG, Dozeen>; -impl<'a, REG> DozeenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dozeen::Enabled) - } - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dozeen::Disabled) - } -} -#[doc = "Loop Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Loops { - #[doc = "0: Normal operation: RXD and TXD use separate pins"] - Noffect = 0, - #[doc = "1: Loop mode or Single-Wire mode"] - Loopback = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Loops) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOOPS` reader - Loop Mode Select"] -pub type LoopsR = crate::BitReader; -impl LoopsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Loops { - match self.bits { - false => Loops::Noffect, - true => Loops::Loopback, - } - } - #[doc = "Normal operation: RXD and TXD use separate pins"] - #[inline(always)] - pub fn is_noffect(&self) -> bool { - *self == Loops::Noffect - } - #[doc = "Loop mode or Single-Wire mode"] - #[inline(always)] - pub fn is_loopback(&self) -> bool { - *self == Loops::Loopback - } -} -#[doc = "Field `LOOPS` writer - Loop Mode Select"] -pub type LoopsW<'a, REG> = crate::BitWriter<'a, REG, Loops>; -impl<'a, REG> LoopsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal operation: RXD and TXD use separate pins"] - #[inline(always)] - pub fn noffect(self) -> &'a mut crate::W { - self.variant(Loops::Noffect) - } - #[doc = "Loop mode or Single-Wire mode"] - #[inline(always)] - pub fn loopback(self) -> &'a mut crate::W { - self.variant(Loops::Loopback) - } -} -#[doc = "Idle Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Idlecfg { - #[doc = "0: 1"] - Idle1 = 0, - #[doc = "1: 2"] - Idle2 = 1, - #[doc = "2: 4"] - Idle4 = 2, - #[doc = "3: 8"] - Idle8 = 3, - #[doc = "4: 16"] - Idle16 = 4, - #[doc = "5: 32"] - Idle32 = 5, - #[doc = "6: 64"] - Idle64 = 6, - #[doc = "7: 128"] - Idle128 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Idlecfg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Idlecfg { - type Ux = u8; -} -impl crate::IsEnum for Idlecfg {} -#[doc = "Field `IDLECFG` reader - Idle Configuration"] -pub type IdlecfgR = crate::FieldReader; -impl IdlecfgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Idlecfg { - match self.bits { - 0 => Idlecfg::Idle1, - 1 => Idlecfg::Idle2, - 2 => Idlecfg::Idle4, - 3 => Idlecfg::Idle8, - 4 => Idlecfg::Idle16, - 5 => Idlecfg::Idle32, - 6 => Idlecfg::Idle64, - 7 => Idlecfg::Idle128, - _ => unreachable!(), - } - } - #[doc = "1"] - #[inline(always)] - pub fn is_idle_1(&self) -> bool { - *self == Idlecfg::Idle1 - } - #[doc = "2"] - #[inline(always)] - pub fn is_idle_2(&self) -> bool { - *self == Idlecfg::Idle2 - } - #[doc = "4"] - #[inline(always)] - pub fn is_idle_4(&self) -> bool { - *self == Idlecfg::Idle4 - } - #[doc = "8"] - #[inline(always)] - pub fn is_idle_8(&self) -> bool { - *self == Idlecfg::Idle8 - } - #[doc = "16"] - #[inline(always)] - pub fn is_idle_16(&self) -> bool { - *self == Idlecfg::Idle16 - } - #[doc = "32"] - #[inline(always)] - pub fn is_idle_32(&self) -> bool { - *self == Idlecfg::Idle32 - } - #[doc = "64"] - #[inline(always)] - pub fn is_idle_64(&self) -> bool { - *self == Idlecfg::Idle64 - } - #[doc = "128"] - #[inline(always)] - pub fn is_idle_128(&self) -> bool { - *self == Idlecfg::Idle128 - } -} -#[doc = "Field `IDLECFG` writer - Idle Configuration"] -pub type IdlecfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Idlecfg, crate::Safe>; -impl<'a, REG> IdlecfgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "1"] - #[inline(always)] - pub fn idle_1(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle1) - } - #[doc = "2"] - #[inline(always)] - pub fn idle_2(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle2) - } - #[doc = "4"] - #[inline(always)] - pub fn idle_4(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle4) - } - #[doc = "8"] - #[inline(always)] - pub fn idle_8(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle8) - } - #[doc = "16"] - #[inline(always)] - pub fn idle_16(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle16) - } - #[doc = "32"] - #[inline(always)] - pub fn idle_32(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle32) - } - #[doc = "64"] - #[inline(always)] - pub fn idle_64(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle64) - } - #[doc = "128"] - #[inline(always)] - pub fn idle_128(self) -> &'a mut crate::W { - self.variant(Idlecfg::Idle128) - } -} -#[doc = "7-Bit Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum M7 { - #[doc = "0: 8-bit to 10-bit"] - NoEffect = 0, - #[doc = "1: 7-bit"] - Data7 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: M7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `M7` reader - 7-Bit Mode Select"] -pub type M7R = crate::BitReader; -impl M7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> M7 { - match self.bits { - false => M7::NoEffect, - true => M7::Data7, - } - } - #[doc = "8-bit to 10-bit"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == M7::NoEffect - } - #[doc = "7-bit"] - #[inline(always)] - pub fn is_data7(&self) -> bool { - *self == M7::Data7 - } -} -#[doc = "Field `M7` writer - 7-Bit Mode Select"] -pub type M7W<'a, REG> = crate::BitWriter<'a, REG, M7>; -impl<'a, REG> M7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "8-bit to 10-bit"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(M7::NoEffect) - } - #[doc = "7-bit"] - #[inline(always)] - pub fn data7(self) -> &'a mut crate::W { - self.variant(M7::Data7) - } -} -#[doc = "TXD and RXD Pin Swap\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swap { - #[doc = "0: Use the standard way"] - Standard = 0, - #[doc = "1: Swap"] - Swap = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swap) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWAP` reader - TXD and RXD Pin Swap"] -pub type SwapR = crate::BitReader; -impl SwapR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swap { - match self.bits { - false => Swap::Standard, - true => Swap::Swap, - } - } - #[doc = "Use the standard way"] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == Swap::Standard - } - #[doc = "Swap"] - #[inline(always)] - pub fn is_swap(&self) -> bool { - *self == Swap::Swap - } -} -#[doc = "Field `SWAP` writer - TXD and RXD Pin Swap"] -pub type SwapW<'a, REG> = crate::BitWriter<'a, REG, Swap>; -impl<'a, REG> SwapW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Use the standard way"] - #[inline(always)] - pub fn standard(self) -> &'a mut crate::W { - self.variant(Swap::Standard) - } - #[doc = "Swap"] - #[inline(always)] - pub fn swap(self) -> &'a mut crate::W { - self.variant(Swap::Swap) - } -} -#[doc = "Match 2 (MA2F) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ma2ie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ma2ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MA2IE` reader - Match 2 (MA2F) Interrupt Enable"] -pub type Ma2ieR = crate::BitReader; -impl Ma2ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ma2ie { - match self.bits { - false => Ma2ie::Disabled, - true => Ma2ie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ma2ie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ma2ie::Enabled - } -} -#[doc = "Field `MA2IE` writer - Match 2 (MA2F) Interrupt Enable"] -pub type Ma2ieW<'a, REG> = crate::BitWriter<'a, REG, Ma2ie>; -impl<'a, REG> Ma2ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ma2ie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ma2ie::Enabled) - } -} -#[doc = "Match 1 (MA1F) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ma1ie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ma1ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MA1IE` reader - Match 1 (MA1F) Interrupt Enable"] -pub type Ma1ieR = crate::BitReader; -impl Ma1ieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ma1ie { - match self.bits { - false => Ma1ie::Disabled, - true => Ma1ie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ma1ie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ma1ie::Enabled - } -} -#[doc = "Field `MA1IE` writer - Match 1 (MA1F) Interrupt Enable"] -pub type Ma1ieW<'a, REG> = crate::BitWriter<'a, REG, Ma1ie>; -impl<'a, REG> Ma1ieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ma1ie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ma1ie::Enabled) - } -} -#[doc = "Send Break\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sbk { - #[doc = "0: Normal transmitter operation"] - NoEffect = 0, - #[doc = "1: Queue break character(s) to be sent"] - TxBreak = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sbk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SBK` reader - Send Break"] -pub type SbkR = crate::BitReader; -impl SbkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sbk { - match self.bits { - false => Sbk::NoEffect, - true => Sbk::TxBreak, - } - } - #[doc = "Normal transmitter operation"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Sbk::NoEffect - } - #[doc = "Queue break character(s) to be sent"] - #[inline(always)] - pub fn is_tx_break(&self) -> bool { - *self == Sbk::TxBreak - } -} -#[doc = "Field `SBK` writer - Send Break"] -pub type SbkW<'a, REG> = crate::BitWriter<'a, REG, Sbk>; -impl<'a, REG> SbkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal transmitter operation"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Sbk::NoEffect) - } - #[doc = "Queue break character(s) to be sent"] - #[inline(always)] - pub fn tx_break(self) -> &'a mut crate::W { - self.variant(Sbk::TxBreak) - } -} -#[doc = "Receiver Wake-Up Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rwu { - #[doc = "0: Normal receiver operation"] - NoEffect = 0, - #[doc = "1: LPUART receiver in standby, waiting for a wake-up condition"] - RxWakeup = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rwu) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RWU` reader - Receiver Wake-Up Control"] -pub type RwuR = crate::BitReader; -impl RwuR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rwu { - match self.bits { - false => Rwu::NoEffect, - true => Rwu::RxWakeup, - } - } - #[doc = "Normal receiver operation"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rwu::NoEffect - } - #[doc = "LPUART receiver in standby, waiting for a wake-up condition"] - #[inline(always)] - pub fn is_rx_wakeup(&self) -> bool { - *self == Rwu::RxWakeup - } -} -#[doc = "Field `RWU` writer - Receiver Wake-Up Control"] -pub type RwuW<'a, REG> = crate::BitWriter<'a, REG, Rwu>; -impl<'a, REG> RwuW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal receiver operation"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rwu::NoEffect) - } - #[doc = "LPUART receiver in standby, waiting for a wake-up condition"] - #[inline(always)] - pub fn rx_wakeup(self) -> &'a mut crate::W { - self.variant(Rwu::RxWakeup) - } -} -#[doc = "Receiver Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Re { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Re) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RE` reader - Receiver Enable"] -pub type ReR = crate::BitReader; -impl ReR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Re { - match self.bits { - false => Re::Disabled, - true => Re::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Re::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Re::Enabled - } -} -#[doc = "Field `RE` writer - Receiver Enable"] -pub type ReW<'a, REG> = crate::BitWriter<'a, REG, Re>; -impl<'a, REG> ReW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Re::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Re::Enabled) - } -} -#[doc = "Transmitter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Te { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Te) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TE` reader - Transmitter Enable"] -pub type TeR = crate::BitReader; -impl TeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Te { - match self.bits { - false => Te::Disabled, - true => Te::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Te::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Te::Enabled - } -} -#[doc = "Field `TE` writer - Transmitter Enable"] -pub type TeW<'a, REG> = crate::BitWriter<'a, REG, Te>; -impl<'a, REG> TeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Te::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Te::Enabled) - } -} -#[doc = "Idle Line Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ilie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ilie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ILIE` reader - Idle Line Interrupt Enable"] -pub type IlieR = crate::BitReader; -impl IlieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ilie { - match self.bits { - false => Ilie::Disabled, - true => Ilie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ilie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ilie::Enabled - } -} -#[doc = "Field `ILIE` writer - Idle Line Interrupt Enable"] -pub type IlieW<'a, REG> = crate::BitWriter<'a, REG, Ilie>; -impl<'a, REG> IlieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ilie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ilie::Enabled) - } -} -#[doc = "Receiver Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RIE` reader - Receiver Interrupt Enable"] -pub type RieR = crate::BitReader; -impl RieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rie { - match self.bits { - false => Rie::Disabled, - true => Rie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rie::Enabled - } -} -#[doc = "Field `RIE` writer - Receiver Interrupt Enable"] -pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>; -impl<'a, REG> RieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rie::Enabled) - } -} -#[doc = "Transmission Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tcie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tcie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCIE` reader - Transmission Complete Interrupt Enable"] -pub type TcieR = crate::BitReader; -impl TcieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcie { - match self.bits { - false => Tcie::Disabled, - true => Tcie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tcie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tcie::Enabled - } -} -#[doc = "Field `TCIE` writer - Transmission Complete Interrupt Enable"] -pub type TcieW<'a, REG> = crate::BitWriter<'a, REG, Tcie>; -impl<'a, REG> TcieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tcie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tcie::Enabled) - } -} -#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE` reader - Transmit Interrupt Enable"] -pub type TieR = crate::BitReader; -impl TieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie { - match self.bits { - false => Tie::Disabled, - true => Tie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tie::Enabled - } -} -#[doc = "Field `TIE` writer - Transmit Interrupt Enable"] -pub type TieW<'a, REG> = crate::BitWriter<'a, REG, Tie>; -impl<'a, REG> TieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tie::Enabled) - } -} -#[doc = "Parity Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Peie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Peie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PEIE` reader - Parity Error Interrupt Enable"] -pub type PeieR = crate::BitReader; -impl PeieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Peie { - match self.bits { - false => Peie::Disabled, - true => Peie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Peie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Peie::Enabled - } -} -#[doc = "Field `PEIE` writer - Parity Error Interrupt Enable"] -pub type PeieW<'a, REG> = crate::BitWriter<'a, REG, Peie>; -impl<'a, REG> PeieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Peie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Peie::Enabled) - } -} -#[doc = "Framing Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Feie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Feie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FEIE` reader - Framing Error Interrupt Enable"] -pub type FeieR = crate::BitReader; -impl FeieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Feie { - match self.bits { - false => Feie::Disabled, - true => Feie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Feie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Feie::Enabled - } -} -#[doc = "Field `FEIE` writer - Framing Error Interrupt Enable"] -pub type FeieW<'a, REG> = crate::BitWriter<'a, REG, Feie>; -impl<'a, REG> FeieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Feie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Feie::Enabled) - } -} -#[doc = "Noise Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Neie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Neie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NEIE` reader - Noise Error Interrupt Enable"] -pub type NeieR = crate::BitReader; -impl NeieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Neie { - match self.bits { - false => Neie::Disabled, - true => Neie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Neie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Neie::Enabled - } -} -#[doc = "Field `NEIE` writer - Noise Error Interrupt Enable"] -pub type NeieW<'a, REG> = crate::BitWriter<'a, REG, Neie>; -impl<'a, REG> NeieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Neie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Neie::Enabled) - } -} -#[doc = "Overrun Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Orie { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Orie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ORIE` reader - Overrun Interrupt Enable"] -pub type OrieR = crate::BitReader; -impl OrieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Orie { - match self.bits { - false => Orie::Disabled, - true => Orie::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Orie::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Orie::Enabled - } -} -#[doc = "Field `ORIE` writer - Overrun Interrupt Enable"] -pub type OrieW<'a, REG> = crate::BitWriter<'a, REG, Orie>; -impl<'a, REG> OrieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Orie::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Orie::Enabled) - } -} -#[doc = "Transmit Data Inversion\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txinv { - #[doc = "0: Not inverted"] - NotInverted = 0, - #[doc = "1: Inverted"] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txinv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXINV` reader - Transmit Data Inversion"] -pub type TxinvR = crate::BitReader; -impl TxinvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txinv { - match self.bits { - false => Txinv::NotInverted, - true => Txinv::Inverted, - } - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Txinv::NotInverted - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Txinv::Inverted - } -} -#[doc = "Field `TXINV` writer - Transmit Data Inversion"] -pub type TxinvW<'a, REG> = crate::BitWriter<'a, REG, Txinv>; -impl<'a, REG> TxinvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not inverted"] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Txinv::NotInverted) - } - #[doc = "Inverted"] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Txinv::Inverted) - } -} -#[doc = "TXD Pin Direction in Single-Wire Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txdir { - #[doc = "0: Input"] - TxInput = 0, - #[doc = "1: Output"] - TxOutput = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txdir) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXDIR` reader - TXD Pin Direction in Single-Wire Mode"] -pub type TxdirR = crate::BitReader; -impl TxdirR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txdir { - match self.bits { - false => Txdir::TxInput, - true => Txdir::TxOutput, - } - } - #[doc = "Input"] - #[inline(always)] - pub fn is_tx_input(&self) -> bool { - *self == Txdir::TxInput - } - #[doc = "Output"] - #[inline(always)] - pub fn is_tx_output(&self) -> bool { - *self == Txdir::TxOutput - } -} -#[doc = "Field `TXDIR` writer - TXD Pin Direction in Single-Wire Mode"] -pub type TxdirW<'a, REG> = crate::BitWriter<'a, REG, Txdir>; -impl<'a, REG> TxdirW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Input"] - #[inline(always)] - pub fn tx_input(self) -> &'a mut crate::W { - self.variant(Txdir::TxInput) - } - #[doc = "Output"] - #[inline(always)] - pub fn tx_output(self) -> &'a mut crate::W { - self.variant(Txdir::TxOutput) - } -} -#[doc = "Field `R9T8` reader - Receive Bit 9 Transmit Bit 8"] -pub type R9t8R = crate::BitReader; -#[doc = "Field `R9T8` writer - Receive Bit 9 Transmit Bit 8"] -pub type R9t8W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R8T9` reader - Receive Bit 8 Transmit Bit 9"] -pub type R8t9R = crate::BitReader; -#[doc = "Field `R8T9` writer - Receive Bit 8 Transmit Bit 9"] -pub type R8t9W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Parity Type"] - #[inline(always)] - pub fn pt(&self) -> PtR { - PtR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Parity Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Idle Line Type Select"] - #[inline(always)] - pub fn ilt(&self) -> IltR { - IltR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Receiver Wake-Up Method Select"] - #[inline(always)] - pub fn wake(&self) -> WakeR { - WakeR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - 9-Bit Or 8-Bit Mode Select"] - #[inline(always)] - pub fn m(&self) -> MR { - MR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Receiver Source Select"] - #[inline(always)] - pub fn rsrc(&self) -> RsrcR { - RsrcR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Doze Mode"] - #[inline(always)] - pub fn dozeen(&self) -> DozeenR { - DozeenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Loop Mode Select"] - #[inline(always)] - pub fn loops(&self) -> LoopsR { - LoopsR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Idle Configuration"] - #[inline(always)] - pub fn idlecfg(&self) -> IdlecfgR { - IdlecfgR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - 7-Bit Mode Select"] - #[inline(always)] - pub fn m7(&self) -> M7R { - M7R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - TXD and RXD Pin Swap"] - #[inline(always)] - pub fn swap(&self) -> SwapR { - SwapR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 14 - Match 2 (MA2F) Interrupt Enable"] - #[inline(always)] - pub fn ma2ie(&self) -> Ma2ieR { - Ma2ieR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Match 1 (MA1F) Interrupt Enable"] - #[inline(always)] - pub fn ma1ie(&self) -> Ma1ieR { - Ma1ieR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Send Break"] - #[inline(always)] - pub fn sbk(&self) -> SbkR { - SbkR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Receiver Wake-Up Control"] - #[inline(always)] - pub fn rwu(&self) -> RwuR { - RwuR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Receiver Enable"] - #[inline(always)] - pub fn re(&self) -> ReR { - ReR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Transmitter Enable"] - #[inline(always)] - pub fn te(&self) -> TeR { - TeR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Idle Line Interrupt Enable"] - #[inline(always)] - pub fn ilie(&self) -> IlieR { - IlieR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Receiver Interrupt Enable"] - #[inline(always)] - pub fn rie(&self) -> RieR { - RieR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Transmission Complete Interrupt Enable"] - #[inline(always)] - pub fn tcie(&self) -> TcieR { - TcieR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Transmit Interrupt Enable"] - #[inline(always)] - pub fn tie(&self) -> TieR { - TieR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Parity Error Interrupt Enable"] - #[inline(always)] - pub fn peie(&self) -> PeieR { - PeieR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Framing Error Interrupt Enable"] - #[inline(always)] - pub fn feie(&self) -> FeieR { - FeieR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Noise Error Interrupt Enable"] - #[inline(always)] - pub fn neie(&self) -> NeieR { - NeieR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Overrun Interrupt Enable"] - #[inline(always)] - pub fn orie(&self) -> OrieR { - OrieR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Transmit Data Inversion"] - #[inline(always)] - pub fn txinv(&self) -> TxinvR { - TxinvR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"] - #[inline(always)] - pub fn txdir(&self) -> TxdirR { - TxdirR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Receive Bit 9 Transmit Bit 8"] - #[inline(always)] - pub fn r9t8(&self) -> R9t8R { - R9t8R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Receive Bit 8 Transmit Bit 9"] - #[inline(always)] - pub fn r8t9(&self) -> R8t9R { - R8t9R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Parity Type"] - #[inline(always)] - pub fn pt(&mut self) -> PtW { - PtW::new(self, 0) - } - #[doc = "Bit 1 - Parity Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Idle Line Type Select"] - #[inline(always)] - pub fn ilt(&mut self) -> IltW { - IltW::new(self, 2) - } - #[doc = "Bit 3 - Receiver Wake-Up Method Select"] - #[inline(always)] - pub fn wake(&mut self) -> WakeW { - WakeW::new(self, 3) - } - #[doc = "Bit 4 - 9-Bit Or 8-Bit Mode Select"] - #[inline(always)] - pub fn m(&mut self) -> MW { - MW::new(self, 4) - } - #[doc = "Bit 5 - Receiver Source Select"] - #[inline(always)] - pub fn rsrc(&mut self) -> RsrcW { - RsrcW::new(self, 5) - } - #[doc = "Bit 6 - Doze Mode"] - #[inline(always)] - pub fn dozeen(&mut self) -> DozeenW { - DozeenW::new(self, 6) - } - #[doc = "Bit 7 - Loop Mode Select"] - #[inline(always)] - pub fn loops(&mut self) -> LoopsW { - LoopsW::new(self, 7) - } - #[doc = "Bits 8:10 - Idle Configuration"] - #[inline(always)] - pub fn idlecfg(&mut self) -> IdlecfgW { - IdlecfgW::new(self, 8) - } - #[doc = "Bit 11 - 7-Bit Mode Select"] - #[inline(always)] - pub fn m7(&mut self) -> M7W { - M7W::new(self, 11) - } - #[doc = "Bit 12 - TXD and RXD Pin Swap"] - #[inline(always)] - pub fn swap(&mut self) -> SwapW { - SwapW::new(self, 12) - } - #[doc = "Bit 14 - Match 2 (MA2F) Interrupt Enable"] - #[inline(always)] - pub fn ma2ie(&mut self) -> Ma2ieW { - Ma2ieW::new(self, 14) - } - #[doc = "Bit 15 - Match 1 (MA1F) Interrupt Enable"] - #[inline(always)] - pub fn ma1ie(&mut self) -> Ma1ieW { - Ma1ieW::new(self, 15) - } - #[doc = "Bit 16 - Send Break"] - #[inline(always)] - pub fn sbk(&mut self) -> SbkW { - SbkW::new(self, 16) - } - #[doc = "Bit 17 - Receiver Wake-Up Control"] - #[inline(always)] - pub fn rwu(&mut self) -> RwuW { - RwuW::new(self, 17) - } - #[doc = "Bit 18 - Receiver Enable"] - #[inline(always)] - pub fn re(&mut self) -> ReW { - ReW::new(self, 18) - } - #[doc = "Bit 19 - Transmitter Enable"] - #[inline(always)] - pub fn te(&mut self) -> TeW { - TeW::new(self, 19) - } - #[doc = "Bit 20 - Idle Line Interrupt Enable"] - #[inline(always)] - pub fn ilie(&mut self) -> IlieW { - IlieW::new(self, 20) - } - #[doc = "Bit 21 - Receiver Interrupt Enable"] - #[inline(always)] - pub fn rie(&mut self) -> RieW { - RieW::new(self, 21) - } - #[doc = "Bit 22 - Transmission Complete Interrupt Enable"] - #[inline(always)] - pub fn tcie(&mut self) -> TcieW { - TcieW::new(self, 22) - } - #[doc = "Bit 23 - Transmit Interrupt Enable"] - #[inline(always)] - pub fn tie(&mut self) -> TieW { - TieW::new(self, 23) - } - #[doc = "Bit 24 - Parity Error Interrupt Enable"] - #[inline(always)] - pub fn peie(&mut self) -> PeieW { - PeieW::new(self, 24) - } - #[doc = "Bit 25 - Framing Error Interrupt Enable"] - #[inline(always)] - pub fn feie(&mut self) -> FeieW { - FeieW::new(self, 25) - } - #[doc = "Bit 26 - Noise Error Interrupt Enable"] - #[inline(always)] - pub fn neie(&mut self) -> NeieW { - NeieW::new(self, 26) - } - #[doc = "Bit 27 - Overrun Interrupt Enable"] - #[inline(always)] - pub fn orie(&mut self) -> OrieW { - OrieW::new(self, 27) - } - #[doc = "Bit 28 - Transmit Data Inversion"] - #[inline(always)] - pub fn txinv(&mut self) -> TxinvW { - TxinvW::new(self, 28) - } - #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"] - #[inline(always)] - pub fn txdir(&mut self) -> TxdirW { - TxdirW::new(self, 29) - } - #[doc = "Bit 30 - Receive Bit 9 Transmit Bit 8"] - #[inline(always)] - pub fn r9t8(&mut self) -> R9t8W { - R9t8W::new(self, 30) - } - #[doc = "Bit 31 - Receive Bit 8 Transmit Bit 9"] - #[inline(always)] - pub fn r8t9(&mut self) -> R8t9W { - R8t9W::new(self, 31) - } -} -#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/lpuart0/data.rs b/mcxa276-pac/src/lpuart0/data.rs deleted file mode 100644 index f1712b21e..000000000 --- a/mcxa276-pac/src/lpuart0/data.rs +++ /dev/null @@ -1,431 +0,0 @@ -#[doc = "Register `DATA` reader"] -pub type R = crate::R; -#[doc = "Register `DATA` writer"] -pub type W = crate::W; -#[doc = "Field `R0T0` reader - Read receive FIFO bit 0 or write transmit FIFO bit 0"] -pub type R0t0R = crate::BitReader; -#[doc = "Field `R0T0` writer - Read receive FIFO bit 0 or write transmit FIFO bit 0"] -pub type R0t0W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R1T1` reader - Read receive FIFO bit 1 or write transmit FIFO bit 1"] -pub type R1t1R = crate::BitReader; -#[doc = "Field `R1T1` writer - Read receive FIFO bit 1 or write transmit FIFO bit 1"] -pub type R1t1W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R2T2` reader - Read receive FIFO bit 2 or write transmit FIFO bit 2"] -pub type R2t2R = crate::BitReader; -#[doc = "Field `R2T2` writer - Read receive FIFO bit 2 or write transmit FIFO bit 2"] -pub type R2t2W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R3T3` reader - Read receive FIFO bit 3 or write transmit FIFO bit 3"] -pub type R3t3R = crate::BitReader; -#[doc = "Field `R3T3` writer - Read receive FIFO bit 3 or write transmit FIFO bit 3"] -pub type R3t3W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R4T4` reader - Read receive FIFO bit 4 or write transmit FIFO bit 4"] -pub type R4t4R = crate::BitReader; -#[doc = "Field `R4T4` writer - Read receive FIFO bit 4 or write transmit FIFO bit 4"] -pub type R4t4W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R5T5` reader - Read receive FIFO bit 5 or write transmit FIFO bit 5"] -pub type R5t5R = crate::BitReader; -#[doc = "Field `R5T5` writer - Read receive FIFO bit 5 or write transmit FIFO bit 5"] -pub type R5t5W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R6T6` reader - Read receive FIFO bit 6 or write transmit FIFO bit 6"] -pub type R6t6R = crate::BitReader; -#[doc = "Field `R6T6` writer - Read receive FIFO bit 6 or write transmit FIFO bit 6"] -pub type R6t6W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R7T7` reader - Read receive FIFO bit 7 or write transmit FIFO bit 7"] -pub type R7t7R = crate::BitReader; -#[doc = "Field `R7T7` writer - Read receive FIFO bit 7 or write transmit FIFO bit 7"] -pub type R7t7W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R8T8` reader - Read receive FIFO bit 8 or write transmit FIFO bit 8"] -pub type R8t8R = crate::BitReader; -#[doc = "Field `R8T8` writer - Read receive FIFO bit 8 or write transmit FIFO bit 8"] -pub type R8t8W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `R9T9` reader - Read receive FIFO bit 9 or write transmit FIFO bit 9"] -pub type R9t9R = crate::BitReader; -#[doc = "Field `R9T9` writer - Read receive FIFO bit 9 or write transmit FIFO bit 9"] -pub type R9t9W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "LIN Break\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Linbrk { - #[doc = "0: Not detected"] - NoBreak = 0, - #[doc = "1: Detected"] - Break = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Linbrk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LINBRK` reader - LIN Break"] -pub type LinbrkR = crate::BitReader; -impl LinbrkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Linbrk { - match self.bits { - false => Linbrk::NoBreak, - true => Linbrk::Break, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_no_break(&self) -> bool { - *self == Linbrk::NoBreak - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_break(&self) -> bool { - *self == Linbrk::Break - } -} -#[doc = "Idle Line\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Idline { - #[doc = "0: Not idle"] - NoIdle = 0, - #[doc = "1: Idle"] - Idle = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Idline) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IDLINE` reader - Idle Line"] -pub type IdlineR = crate::BitReader; -impl IdlineR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Idline { - match self.bits { - false => Idline::NoIdle, - true => Idline::Idle, - } - } - #[doc = "Not idle"] - #[inline(always)] - pub fn is_no_idle(&self) -> bool { - *self == Idline::NoIdle - } - #[doc = "Idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Idline::Idle - } -} -#[doc = "Receive Buffer Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempt { - #[doc = "0: Valid data"] - NotEmpty = 0, - #[doc = "1: Invalid data and empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPT` reader - Receive Buffer Empty"] -pub type RxemptR = crate::BitReader; -impl RxemptR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempt { - match self.bits { - false => Rxempt::NotEmpty, - true => Rxempt::Empty, - } - } - #[doc = "Valid data"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempt::NotEmpty - } - #[doc = "Invalid data and empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempt::Empty - } -} -#[doc = "Frame Error Transmit Special Character\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fretsc { - #[doc = "0: Received without a frame error on reads or transmits a normal character on writes"] - NoError = 0, - #[doc = "1: Received with a frame error on reads or transmits an idle or break character on writes"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fretsc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRETSC` reader - Frame Error Transmit Special Character"] -pub type FretscR = crate::BitReader; -impl FretscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fretsc { - match self.bits { - false => Fretsc::NoError, - true => Fretsc::Error, - } - } - #[doc = "Received without a frame error on reads or transmits a normal character on writes"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Fretsc::NoError - } - #[doc = "Received with a frame error on reads or transmits an idle or break character on writes"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Fretsc::Error - } -} -#[doc = "Field `FRETSC` writer - Frame Error Transmit Special Character"] -pub type FretscW<'a, REG> = crate::BitWriter<'a, REG, Fretsc>; -impl<'a, REG> FretscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Received without a frame error on reads or transmits a normal character on writes"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Fretsc::NoError) - } - #[doc = "Received with a frame error on reads or transmits an idle or break character on writes"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Fretsc::Error) - } -} -#[doc = "Parity Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Paritye { - #[doc = "0: Received without a parity error"] - NoParity = 0, - #[doc = "1: Received with a parity error"] - Parity = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Paritye) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PARITYE` reader - Parity Error"] -pub type ParityeR = crate::BitReader; -impl ParityeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Paritye { - match self.bits { - false => Paritye::NoParity, - true => Paritye::Parity, - } - } - #[doc = "Received without a parity error"] - #[inline(always)] - pub fn is_no_parity(&self) -> bool { - *self == Paritye::NoParity - } - #[doc = "Received with a parity error"] - #[inline(always)] - pub fn is_parity(&self) -> bool { - *self == Paritye::Parity - } -} -#[doc = "Noisy Data Received\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Noisy { - #[doc = "0: Received without noise"] - NoNoise = 0, - #[doc = "1: Received with noise"] - Noise = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Noisy) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOISY` reader - Noisy Data Received"] -pub type NoisyR = crate::BitReader; -impl NoisyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Noisy { - match self.bits { - false => Noisy::NoNoise, - true => Noisy::Noise, - } - } - #[doc = "Received without noise"] - #[inline(always)] - pub fn is_no_noise(&self) -> bool { - *self == Noisy::NoNoise - } - #[doc = "Received with noise"] - #[inline(always)] - pub fn is_noise(&self) -> bool { - *self == Noisy::Noise - } -} -impl R { - #[doc = "Bit 0 - Read receive FIFO bit 0 or write transmit FIFO bit 0"] - #[inline(always)] - pub fn r0t0(&self) -> R0t0R { - R0t0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Read receive FIFO bit 1 or write transmit FIFO bit 1"] - #[inline(always)] - pub fn r1t1(&self) -> R1t1R { - R1t1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Read receive FIFO bit 2 or write transmit FIFO bit 2"] - #[inline(always)] - pub fn r2t2(&self) -> R2t2R { - R2t2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Read receive FIFO bit 3 or write transmit FIFO bit 3"] - #[inline(always)] - pub fn r3t3(&self) -> R3t3R { - R3t3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Read receive FIFO bit 4 or write transmit FIFO bit 4"] - #[inline(always)] - pub fn r4t4(&self) -> R4t4R { - R4t4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Read receive FIFO bit 5 or write transmit FIFO bit 5"] - #[inline(always)] - pub fn r5t5(&self) -> R5t5R { - R5t5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Read receive FIFO bit 6 or write transmit FIFO bit 6"] - #[inline(always)] - pub fn r6t6(&self) -> R6t6R { - R6t6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Read receive FIFO bit 7 or write transmit FIFO bit 7"] - #[inline(always)] - pub fn r7t7(&self) -> R7t7R { - R7t7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Read receive FIFO bit 8 or write transmit FIFO bit 8"] - #[inline(always)] - pub fn r8t8(&self) -> R8t8R { - R8t8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Read receive FIFO bit 9 or write transmit FIFO bit 9"] - #[inline(always)] - pub fn r9t9(&self) -> R9t9R { - R9t9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - LIN Break"] - #[inline(always)] - pub fn linbrk(&self) -> LinbrkR { - LinbrkR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Idle Line"] - #[inline(always)] - pub fn idline(&self) -> IdlineR { - IdlineR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Receive Buffer Empty"] - #[inline(always)] - pub fn rxempt(&self) -> RxemptR { - RxemptR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Frame Error Transmit Special Character"] - #[inline(always)] - pub fn fretsc(&self) -> FretscR { - FretscR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Parity Error"] - #[inline(always)] - pub fn paritye(&self) -> ParityeR { - ParityeR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Noisy Data Received"] - #[inline(always)] - pub fn noisy(&self) -> NoisyR { - NoisyR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Read receive FIFO bit 0 or write transmit FIFO bit 0"] - #[inline(always)] - pub fn r0t0(&mut self) -> R0t0W { - R0t0W::new(self, 0) - } - #[doc = "Bit 1 - Read receive FIFO bit 1 or write transmit FIFO bit 1"] - #[inline(always)] - pub fn r1t1(&mut self) -> R1t1W { - R1t1W::new(self, 1) - } - #[doc = "Bit 2 - Read receive FIFO bit 2 or write transmit FIFO bit 2"] - #[inline(always)] - pub fn r2t2(&mut self) -> R2t2W { - R2t2W::new(self, 2) - } - #[doc = "Bit 3 - Read receive FIFO bit 3 or write transmit FIFO bit 3"] - #[inline(always)] - pub fn r3t3(&mut self) -> R3t3W { - R3t3W::new(self, 3) - } - #[doc = "Bit 4 - Read receive FIFO bit 4 or write transmit FIFO bit 4"] - #[inline(always)] - pub fn r4t4(&mut self) -> R4t4W { - R4t4W::new(self, 4) - } - #[doc = "Bit 5 - Read receive FIFO bit 5 or write transmit FIFO bit 5"] - #[inline(always)] - pub fn r5t5(&mut self) -> R5t5W { - R5t5W::new(self, 5) - } - #[doc = "Bit 6 - Read receive FIFO bit 6 or write transmit FIFO bit 6"] - #[inline(always)] - pub fn r6t6(&mut self) -> R6t6W { - R6t6W::new(self, 6) - } - #[doc = "Bit 7 - Read receive FIFO bit 7 or write transmit FIFO bit 7"] - #[inline(always)] - pub fn r7t7(&mut self) -> R7t7W { - R7t7W::new(self, 7) - } - #[doc = "Bit 8 - Read receive FIFO bit 8 or write transmit FIFO bit 8"] - #[inline(always)] - pub fn r8t8(&mut self) -> R8t8W { - R8t8W::new(self, 8) - } - #[doc = "Bit 9 - Read receive FIFO bit 9 or write transmit FIFO bit 9"] - #[inline(always)] - pub fn r9t9(&mut self) -> R9t9W { - R9t9W::new(self, 9) - } - #[doc = "Bit 13 - Frame Error Transmit Special Character"] - #[inline(always)] - pub fn fretsc(&mut self) -> FretscW { - FretscW::new(self, 13) - } -} -#[doc = "Data\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DataSpec; -impl crate::RegisterSpec for DataSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`data::R`](R) reader structure"] -impl crate::Readable for DataSpec {} -#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] -impl crate::Writable for DataSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DATA to value 0x1000"] -impl crate::Resettable for DataSpec { - const RESET_VALUE: u32 = 0x1000; -} diff --git a/mcxa276-pac/src/lpuart0/dataro.rs b/mcxa276-pac/src/lpuart0/dataro.rs deleted file mode 100644 index 92daa4a7b..000000000 --- a/mcxa276-pac/src/lpuart0/dataro.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `DATARO` reader"] -pub type R = crate::R; -#[doc = "Field `DATA` reader - Receive Data"] -pub type DataR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Receive Data"] - #[inline(always)] - pub fn data(&self) -> DataR { - DataR::new((self.bits & 0xffff) as u16) - } -} -#[doc = "Data Read-Only\n\nYou can [`read`](crate::Reg::read) this register and get [`dataro::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DataroSpec; -impl crate::RegisterSpec for DataroSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`dataro::R`](R) reader structure"] -impl crate::Readable for DataroSpec {} -#[doc = "`reset()` method sets DATARO to value 0x1000"] -impl crate::Resettable for DataroSpec { - const RESET_VALUE: u32 = 0x1000; -} diff --git a/mcxa276-pac/src/lpuart0/fifo.rs b/mcxa276-pac/src/lpuart0/fifo.rs deleted file mode 100644 index 9a6765726..000000000 --- a/mcxa276-pac/src/lpuart0/fifo.rs +++ /dev/null @@ -1,948 +0,0 @@ -#[doc = "Register `FIFO` reader"] -pub type R = crate::R; -#[doc = "Register `FIFO` writer"] -pub type W = crate::W; -#[doc = "Receive FIFO Buffer Depth\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Rxfifosize { - #[doc = "0: 1"] - Fifo1 = 0, - #[doc = "1: 4"] - Fifo4 = 1, - #[doc = "2: 8"] - Fifo8 = 2, - #[doc = "3: 16"] - Fifo16 = 3, - #[doc = "4: 32"] - Fifo32 = 4, - #[doc = "5: 64"] - Fifo64 = 5, - #[doc = "6: 128"] - Fifo128 = 6, - #[doc = "7: 256"] - Fifo256 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Rxfifosize) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Rxfifosize { - type Ux = u8; -} -impl crate::IsEnum for Rxfifosize {} -#[doc = "Field `RXFIFOSIZE` reader - Receive FIFO Buffer Depth"] -pub type RxfifosizeR = crate::FieldReader; -impl RxfifosizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxfifosize { - match self.bits { - 0 => Rxfifosize::Fifo1, - 1 => Rxfifosize::Fifo4, - 2 => Rxfifosize::Fifo8, - 3 => Rxfifosize::Fifo16, - 4 => Rxfifosize::Fifo32, - 5 => Rxfifosize::Fifo64, - 6 => Rxfifosize::Fifo128, - 7 => Rxfifosize::Fifo256, - _ => unreachable!(), - } - } - #[doc = "1"] - #[inline(always)] - pub fn is_fifo_1(&self) -> bool { - *self == Rxfifosize::Fifo1 - } - #[doc = "4"] - #[inline(always)] - pub fn is_fifo_4(&self) -> bool { - *self == Rxfifosize::Fifo4 - } - #[doc = "8"] - #[inline(always)] - pub fn is_fifo_8(&self) -> bool { - *self == Rxfifosize::Fifo8 - } - #[doc = "16"] - #[inline(always)] - pub fn is_fifo_16(&self) -> bool { - *self == Rxfifosize::Fifo16 - } - #[doc = "32"] - #[inline(always)] - pub fn is_fifo_32(&self) -> bool { - *self == Rxfifosize::Fifo32 - } - #[doc = "64"] - #[inline(always)] - pub fn is_fifo_64(&self) -> bool { - *self == Rxfifosize::Fifo64 - } - #[doc = "128"] - #[inline(always)] - pub fn is_fifo_128(&self) -> bool { - *self == Rxfifosize::Fifo128 - } - #[doc = "256"] - #[inline(always)] - pub fn is_fifo_256(&self) -> bool { - *self == Rxfifosize::Fifo256 - } -} -#[doc = "Receive FIFO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxfe { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXFE` reader - Receive FIFO Enable"] -pub type RxfeR = crate::BitReader; -impl RxfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxfe { - match self.bits { - false => Rxfe::Disabled, - true => Rxfe::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rxfe::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rxfe::Enabled - } -} -#[doc = "Field `RXFE` writer - Receive FIFO Enable"] -pub type RxfeW<'a, REG> = crate::BitWriter<'a, REG, Rxfe>; -impl<'a, REG> RxfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rxfe::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rxfe::Enabled) - } -} -#[doc = "Transmit FIFO Buffer Depth\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Txfifosize { - #[doc = "0: 1"] - Fifo1 = 0, - #[doc = "1: 4"] - Fifo4 = 1, - #[doc = "2: 8"] - Fifo8 = 2, - #[doc = "3: 16"] - Fifo16 = 3, - #[doc = "4: 32"] - Fifo32 = 4, - #[doc = "5: 64"] - Fifo64 = 5, - #[doc = "6: 128"] - Fifo128 = 6, - #[doc = "7: 256"] - Fifo256 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Txfifosize) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Txfifosize { - type Ux = u8; -} -impl crate::IsEnum for Txfifosize {} -#[doc = "Field `TXFIFOSIZE` reader - Transmit FIFO Buffer Depth"] -pub type TxfifosizeR = crate::FieldReader; -impl TxfifosizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txfifosize { - match self.bits { - 0 => Txfifosize::Fifo1, - 1 => Txfifosize::Fifo4, - 2 => Txfifosize::Fifo8, - 3 => Txfifosize::Fifo16, - 4 => Txfifosize::Fifo32, - 5 => Txfifosize::Fifo64, - 6 => Txfifosize::Fifo128, - 7 => Txfifosize::Fifo256, - _ => unreachable!(), - } - } - #[doc = "1"] - #[inline(always)] - pub fn is_fifo_1(&self) -> bool { - *self == Txfifosize::Fifo1 - } - #[doc = "4"] - #[inline(always)] - pub fn is_fifo_4(&self) -> bool { - *self == Txfifosize::Fifo4 - } - #[doc = "8"] - #[inline(always)] - pub fn is_fifo_8(&self) -> bool { - *self == Txfifosize::Fifo8 - } - #[doc = "16"] - #[inline(always)] - pub fn is_fifo_16(&self) -> bool { - *self == Txfifosize::Fifo16 - } - #[doc = "32"] - #[inline(always)] - pub fn is_fifo_32(&self) -> bool { - *self == Txfifosize::Fifo32 - } - #[doc = "64"] - #[inline(always)] - pub fn is_fifo_64(&self) -> bool { - *self == Txfifosize::Fifo64 - } - #[doc = "128"] - #[inline(always)] - pub fn is_fifo_128(&self) -> bool { - *self == Txfifosize::Fifo128 - } - #[doc = "256"] - #[inline(always)] - pub fn is_fifo_256(&self) -> bool { - *self == Txfifosize::Fifo256 - } -} -#[doc = "Transmit FIFO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txfe { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXFE` reader - Transmit FIFO Enable"] -pub type TxfeR = crate::BitReader; -impl TxfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txfe { - match self.bits { - false => Txfe::Disabled, - true => Txfe::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Txfe::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Txfe::Enabled - } -} -#[doc = "Field `TXFE` writer - Transmit FIFO Enable"] -pub type TxfeW<'a, REG> = crate::BitWriter<'a, REG, Txfe>; -impl<'a, REG> TxfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Txfe::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Txfe::Enabled) - } -} -#[doc = "Receive FIFO Underflow Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxufe { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxufe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXUFE` reader - Receive FIFO Underflow Interrupt Enable"] -pub type RxufeR = crate::BitReader; -impl RxufeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxufe { - match self.bits { - false => Rxufe::Disabled, - true => Rxufe::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rxufe::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rxufe::Enabled - } -} -#[doc = "Field `RXUFE` writer - Receive FIFO Underflow Interrupt Enable"] -pub type RxufeW<'a, REG> = crate::BitWriter<'a, REG, Rxufe>; -impl<'a, REG> RxufeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rxufe::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rxufe::Enabled) - } -} -#[doc = "Transmit FIFO Overflow Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txofe { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txofe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXOFE` reader - Transmit FIFO Overflow Interrupt Enable"] -pub type TxofeR = crate::BitReader; -impl TxofeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txofe { - match self.bits { - false => Txofe::Disabled, - true => Txofe::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Txofe::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Txofe::Enabled - } -} -#[doc = "Field `TXOFE` writer - Transmit FIFO Overflow Interrupt Enable"] -pub type TxofeW<'a, REG> = crate::BitWriter<'a, REG, Txofe>; -impl<'a, REG> TxofeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Txofe::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Txofe::Enabled) - } -} -#[doc = "Receiver Idle Empty Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Rxiden { - #[doc = "0: Disable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle"] - Disabled = 0, - #[doc = "1: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for one character"] - Idle1 = 1, - #[doc = "2: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for two characters"] - Idle2 = 2, - #[doc = "3: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for four characters"] - Idle4 = 3, - #[doc = "4: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for eight characters"] - Idle8 = 4, - #[doc = "5: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters"] - Idle16 = 5, - #[doc = "6: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters"] - Idle32 = 6, - #[doc = "7: Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters"] - Idle64 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Rxiden) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Rxiden { - type Ux = u8; -} -impl crate::IsEnum for Rxiden {} -#[doc = "Field `RXIDEN` reader - Receiver Idle Empty Enable"] -pub type RxidenR = crate::FieldReader; -impl RxidenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxiden { - match self.bits { - 0 => Rxiden::Disabled, - 1 => Rxiden::Idle1, - 2 => Rxiden::Idle2, - 3 => Rxiden::Idle4, - 4 => Rxiden::Idle8, - 5 => Rxiden::Idle16, - 6 => Rxiden::Idle32, - 7 => Rxiden::Idle64, - _ => unreachable!(), - } - } - #[doc = "Disable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rxiden::Disabled - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for one character"] - #[inline(always)] - pub fn is_idle_1(&self) -> bool { - *self == Rxiden::Idle1 - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for two characters"] - #[inline(always)] - pub fn is_idle_2(&self) -> bool { - *self == Rxiden::Idle2 - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for four characters"] - #[inline(always)] - pub fn is_idle_4(&self) -> bool { - *self == Rxiden::Idle4 - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for eight characters"] - #[inline(always)] - pub fn is_idle_8(&self) -> bool { - *self == Rxiden::Idle8 - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters"] - #[inline(always)] - pub fn is_idle_16(&self) -> bool { - *self == Rxiden::Idle16 - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters"] - #[inline(always)] - pub fn is_idle_32(&self) -> bool { - *self == Rxiden::Idle32 - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters"] - #[inline(always)] - pub fn is_idle_64(&self) -> bool { - *self == Rxiden::Idle64 - } -} -#[doc = "Field `RXIDEN` writer - Receiver Idle Empty Enable"] -pub type RxidenW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rxiden, crate::Safe>; -impl<'a, REG> RxidenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rxiden::Disabled) - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for one character"] - #[inline(always)] - pub fn idle_1(self) -> &'a mut crate::W { - self.variant(Rxiden::Idle1) - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for two characters"] - #[inline(always)] - pub fn idle_2(self) -> &'a mut crate::W { - self.variant(Rxiden::Idle2) - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for four characters"] - #[inline(always)] - pub fn idle_4(self) -> &'a mut crate::W { - self.variant(Rxiden::Idle4) - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for eight characters"] - #[inline(always)] - pub fn idle_8(self) -> &'a mut crate::W { - self.variant(Rxiden::Idle8) - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters"] - #[inline(always)] - pub fn idle_16(self) -> &'a mut crate::W { - self.variant(Rxiden::Idle16) - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters"] - #[inline(always)] - pub fn idle_32(self) -> &'a mut crate::W { - self.variant(Rxiden::Idle32) - } - #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters"] - #[inline(always)] - pub fn idle_64(self) -> &'a mut crate::W { - self.variant(Rxiden::Idle64) - } -} -#[doc = "Receive FIFO Flush\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxflush { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: All data flushed out"] - RxfifoRst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxflush) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXFLUSH` reader - Receive FIFO Flush"] -pub type RxflushR = crate::BitReader; -impl RxflushR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxflush { - match self.bits { - false => Rxflush::NoEffect, - true => Rxflush::RxfifoRst, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rxflush::NoEffect - } - #[doc = "All data flushed out"] - #[inline(always)] - pub fn is_rxfifo_rst(&self) -> bool { - *self == Rxflush::RxfifoRst - } -} -#[doc = "Field `RXFLUSH` writer - Receive FIFO Flush"] -pub type RxflushW<'a, REG> = crate::BitWriter<'a, REG, Rxflush>; -impl<'a, REG> RxflushW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rxflush::NoEffect) - } - #[doc = "All data flushed out"] - #[inline(always)] - pub fn rxfifo_rst(self) -> &'a mut crate::W { - self.variant(Rxflush::RxfifoRst) - } -} -#[doc = "Transmit FIFO Flush\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txflush { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: All data flushed out"] - TxfifoRst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txflush) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXFLUSH` reader - Transmit FIFO Flush"] -pub type TxflushR = crate::BitReader; -impl TxflushR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txflush { - match self.bits { - false => Txflush::NoEffect, - true => Txflush::TxfifoRst, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Txflush::NoEffect - } - #[doc = "All data flushed out"] - #[inline(always)] - pub fn is_txfifo_rst(&self) -> bool { - *self == Txflush::TxfifoRst - } -} -#[doc = "Field `TXFLUSH` writer - Transmit FIFO Flush"] -pub type TxflushW<'a, REG> = crate::BitWriter<'a, REG, Txflush>; -impl<'a, REG> TxflushW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Txflush::NoEffect) - } - #[doc = "All data flushed out"] - #[inline(always)] - pub fn txfifo_rst(self) -> &'a mut crate::W { - self.variant(Txflush::TxfifoRst) - } -} -#[doc = "Receiver FIFO Underflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxuf { - #[doc = "0: No underflow"] - NoUnderflow = 0, - #[doc = "1: Underflow"] - Underflow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxuf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXUF` reader - Receiver FIFO Underflow Flag"] -pub type RxufR = crate::BitReader; -impl RxufR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxuf { - match self.bits { - false => Rxuf::NoUnderflow, - true => Rxuf::Underflow, - } - } - #[doc = "No underflow"] - #[inline(always)] - pub fn is_no_underflow(&self) -> bool { - *self == Rxuf::NoUnderflow - } - #[doc = "Underflow"] - #[inline(always)] - pub fn is_underflow(&self) -> bool { - *self == Rxuf::Underflow - } -} -#[doc = "Field `RXUF` writer - Receiver FIFO Underflow Flag"] -pub type RxufW<'a, REG> = crate::BitWriter1C<'a, REG, Rxuf>; -impl<'a, REG> RxufW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No underflow"] - #[inline(always)] - pub fn no_underflow(self) -> &'a mut crate::W { - self.variant(Rxuf::NoUnderflow) - } - #[doc = "Underflow"] - #[inline(always)] - pub fn underflow(self) -> &'a mut crate::W { - self.variant(Rxuf::Underflow) - } -} -#[doc = "Transmitter FIFO Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txof { - #[doc = "0: No overflow"] - NoOverflow = 0, - #[doc = "1: Overflow"] - Overflow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXOF` reader - Transmitter FIFO Overflow Flag"] -pub type TxofR = crate::BitReader; -impl TxofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txof { - match self.bits { - false => Txof::NoOverflow, - true => Txof::Overflow, - } - } - #[doc = "No overflow"] - #[inline(always)] - pub fn is_no_overflow(&self) -> bool { - *self == Txof::NoOverflow - } - #[doc = "Overflow"] - #[inline(always)] - pub fn is_overflow(&self) -> bool { - *self == Txof::Overflow - } -} -#[doc = "Field `TXOF` writer - Transmitter FIFO Overflow Flag"] -pub type TxofW<'a, REG> = crate::BitWriter1C<'a, REG, Txof>; -impl<'a, REG> TxofW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overflow"] - #[inline(always)] - pub fn no_overflow(self) -> &'a mut crate::W { - self.variant(Txof::NoOverflow) - } - #[doc = "Overflow"] - #[inline(always)] - pub fn overflow(self) -> &'a mut crate::W { - self.variant(Txof::Overflow) - } -} -#[doc = "Receive FIFO Or Buffer Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxempt { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxempt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEMPT` reader - Receive FIFO Or Buffer Empty"] -pub type RxemptR = crate::BitReader; -impl RxemptR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxempt { - match self.bits { - false => Rxempt::NotEmpty, - true => Rxempt::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Rxempt::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Rxempt::Empty - } -} -#[doc = "Transmit FIFO Or Buffer Empty\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txempt { - #[doc = "0: Not empty"] - NotEmpty = 0, - #[doc = "1: Empty"] - Empty = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txempt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXEMPT` reader - Transmit FIFO Or Buffer Empty"] -pub type TxemptR = crate::BitReader; -impl TxemptR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txempt { - match self.bits { - false => Txempt::NotEmpty, - true => Txempt::Empty, - } - } - #[doc = "Not empty"] - #[inline(always)] - pub fn is_not_empty(&self) -> bool { - *self == Txempt::NotEmpty - } - #[doc = "Empty"] - #[inline(always)] - pub fn is_empty(&self) -> bool { - *self == Txempt::Empty - } -} -impl R { - #[doc = "Bits 0:2 - Receive FIFO Buffer Depth"] - #[inline(always)] - pub fn rxfifosize(&self) -> RxfifosizeR { - RxfifosizeR::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - Receive FIFO Enable"] - #[inline(always)] - pub fn rxfe(&self) -> RxfeR { - RxfeR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Transmit FIFO Buffer Depth"] - #[inline(always)] - pub fn txfifosize(&self) -> TxfifosizeR { - TxfifosizeR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - Transmit FIFO Enable"] - #[inline(always)] - pub fn txfe(&self) -> TxfeR { - TxfeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Receive FIFO Underflow Interrupt Enable"] - #[inline(always)] - pub fn rxufe(&self) -> RxufeR { - RxufeR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Transmit FIFO Overflow Interrupt Enable"] - #[inline(always)] - pub fn txofe(&self) -> TxofeR { - TxofeR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 10:12 - Receiver Idle Empty Enable"] - #[inline(always)] - pub fn rxiden(&self) -> RxidenR { - RxidenR::new(((self.bits >> 10) & 7) as u8) - } - #[doc = "Bit 14 - Receive FIFO Flush"] - #[inline(always)] - pub fn rxflush(&self) -> RxflushR { - RxflushR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Transmit FIFO Flush"] - #[inline(always)] - pub fn txflush(&self) -> TxflushR { - TxflushR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Receiver FIFO Underflow Flag"] - #[inline(always)] - pub fn rxuf(&self) -> RxufR { - RxufR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Transmitter FIFO Overflow Flag"] - #[inline(always)] - pub fn txof(&self) -> TxofR { - TxofR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 22 - Receive FIFO Or Buffer Empty"] - #[inline(always)] - pub fn rxempt(&self) -> RxemptR { - RxemptR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Transmit FIFO Or Buffer Empty"] - #[inline(always)] - pub fn txempt(&self) -> TxemptR { - TxemptR::new(((self.bits >> 23) & 1) != 0) - } -} -impl W { - #[doc = "Bit 3 - Receive FIFO Enable"] - #[inline(always)] - pub fn rxfe(&mut self) -> RxfeW { - RxfeW::new(self, 3) - } - #[doc = "Bit 7 - Transmit FIFO Enable"] - #[inline(always)] - pub fn txfe(&mut self) -> TxfeW { - TxfeW::new(self, 7) - } - #[doc = "Bit 8 - Receive FIFO Underflow Interrupt Enable"] - #[inline(always)] - pub fn rxufe(&mut self) -> RxufeW { - RxufeW::new(self, 8) - } - #[doc = "Bit 9 - Transmit FIFO Overflow Interrupt Enable"] - #[inline(always)] - pub fn txofe(&mut self) -> TxofeW { - TxofeW::new(self, 9) - } - #[doc = "Bits 10:12 - Receiver Idle Empty Enable"] - #[inline(always)] - pub fn rxiden(&mut self) -> RxidenW { - RxidenW::new(self, 10) - } - #[doc = "Bit 14 - Receive FIFO Flush"] - #[inline(always)] - pub fn rxflush(&mut self) -> RxflushW { - RxflushW::new(self, 14) - } - #[doc = "Bit 15 - Transmit FIFO Flush"] - #[inline(always)] - pub fn txflush(&mut self) -> TxflushW { - TxflushW::new(self, 15) - } - #[doc = "Bit 16 - Receiver FIFO Underflow Flag"] - #[inline(always)] - pub fn rxuf(&mut self) -> RxufW { - RxufW::new(self, 16) - } - #[doc = "Bit 17 - Transmitter FIFO Overflow Flag"] - #[inline(always)] - pub fn txof(&mut self) -> TxofW { - TxofW::new(self, 17) - } -} -#[doc = "FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FifoSpec; -impl crate::RegisterSpec for FifoSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] -impl crate::Readable for FifoSpec {} -#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] -impl crate::Writable for FifoSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0003_0000; -} -#[doc = "`reset()` method sets FIFO to value 0x00c0_0011"] -impl crate::Resettable for FifoSpec { - const RESET_VALUE: u32 = 0x00c0_0011; -} diff --git a/mcxa276-pac/src/lpuart0/global.rs b/mcxa276-pac/src/lpuart0/global.rs deleted file mode 100644 index d91df132d..000000000 --- a/mcxa276-pac/src/lpuart0/global.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `GLOBAL` reader"] -pub type R = crate::R; -#[doc = "Register `GLOBAL` writer"] -pub type W = crate::W; -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rst { - #[doc = "0: Not reset"] - NoEffect = 0, - #[doc = "1: Reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST` reader - Software Reset"] -pub type RstR = crate::BitReader; -impl RstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rst { - match self.bits { - false => Rst::NoEffect, - true => Rst::Reset, - } - } - #[doc = "Not reset"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Rst::NoEffect - } - #[doc = "Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Rst::Reset - } -} -#[doc = "Field `RST` writer - Software Reset"] -pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; -impl<'a, REG> RstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not reset"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Rst::NoEffect) - } - #[doc = "Reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Rst::Reset) - } -} -impl R { - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&self) -> RstR { - RstR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - Software Reset"] - #[inline(always)] - pub fn rst(&mut self) -> RstW { - RstW::new(self, 1) - } -} -#[doc = "Global\n\nYou can [`read`](crate::Reg::read) this register and get [`global::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GlobalSpec; -impl crate::RegisterSpec for GlobalSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`global::R`](R) reader structure"] -impl crate::Readable for GlobalSpec {} -#[doc = "`write(|w| ..)` method takes [`global::W`](W) writer structure"] -impl crate::Writable for GlobalSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GLOBAL to value 0"] -impl crate::Resettable for GlobalSpec {} diff --git a/mcxa276-pac/src/lpuart0/match_.rs b/mcxa276-pac/src/lpuart0/match_.rs deleted file mode 100644 index 50b748a7d..000000000 --- a/mcxa276-pac/src/lpuart0/match_.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `MATCH` reader"] -pub type R = crate::R; -#[doc = "Register `MATCH` writer"] -pub type W = crate::W; -#[doc = "Field `MA1` reader - Match Address 1"] -pub type Ma1R = crate::FieldReader; -#[doc = "Field `MA1` writer - Match Address 1"] -pub type Ma1W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `MA2` reader - Match Address 2"] -pub type Ma2R = crate::FieldReader; -#[doc = "Field `MA2` writer - Match Address 2"] -pub type Ma2W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:9 - Match Address 1"] - #[inline(always)] - pub fn ma1(&self) -> Ma1R { - Ma1R::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 16:25 - Match Address 2"] - #[inline(always)] - pub fn ma2(&self) -> Ma2R { - Ma2R::new(((self.bits >> 16) & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:9 - Match Address 1"] - #[inline(always)] - pub fn ma1(&mut self) -> Ma1W { - Ma1W::new(self, 0) - } - #[doc = "Bits 16:25 - Match Address 2"] - #[inline(always)] - pub fn ma2(&mut self) -> Ma2W { - Ma2W::new(self, 16) - } -} -#[doc = "Match Address\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MatchSpec; -impl crate::RegisterSpec for MatchSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`match_::R`](R) reader structure"] -impl crate::Readable for MatchSpec {} -#[doc = "`write(|w| ..)` method takes [`match_::W`](W) writer structure"] -impl crate::Writable for MatchSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MATCH to value 0"] -impl crate::Resettable for MatchSpec {} diff --git a/mcxa276-pac/src/lpuart0/modir.rs b/mcxa276-pac/src/lpuart0/modir.rs deleted file mode 100644 index 90d5757c3..000000000 --- a/mcxa276-pac/src/lpuart0/modir.rs +++ /dev/null @@ -1,572 +0,0 @@ -#[doc = "Register `MODIR` reader"] -pub type R = crate::R; -#[doc = "Register `MODIR` writer"] -pub type W = crate::W; -#[doc = "Transmitter CTS Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txctse { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txctse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXCTSE` reader - Transmitter CTS Enable"] -pub type TxctseR = crate::BitReader; -impl TxctseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txctse { - match self.bits { - false => Txctse::Disabled, - true => Txctse::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Txctse::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Txctse::Enabled - } -} -#[doc = "Field `TXCTSE` writer - Transmitter CTS Enable"] -pub type TxctseW<'a, REG> = crate::BitWriter<'a, REG, Txctse>; -impl<'a, REG> TxctseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Txctse::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Txctse::Enabled) - } -} -#[doc = "Transmitter RTS Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txrtse { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txrtse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXRTSE` reader - Transmitter RTS Enable"] -pub type TxrtseR = crate::BitReader; -impl TxrtseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txrtse { - match self.bits { - false => Txrtse::Disabled, - true => Txrtse::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Txrtse::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Txrtse::Enabled - } -} -#[doc = "Field `TXRTSE` writer - Transmitter RTS Enable"] -pub type TxrtseW<'a, REG> = crate::BitWriter<'a, REG, Txrtse>; -impl<'a, REG> TxrtseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Txrtse::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Txrtse::Enabled) - } -} -#[doc = "Transmitter RTS Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txrtspol { - #[doc = "0: Active low"] - Low = 0, - #[doc = "1: Active high"] - High = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txrtspol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXRTSPOL` reader - Transmitter RTS Polarity"] -pub type TxrtspolR = crate::BitReader; -impl TxrtspolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txrtspol { - match self.bits { - false => Txrtspol::Low, - true => Txrtspol::High, - } - } - #[doc = "Active low"] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == Txrtspol::Low - } - #[doc = "Active high"] - #[inline(always)] - pub fn is_high(&self) -> bool { - *self == Txrtspol::High - } -} -#[doc = "Field `TXRTSPOL` writer - Transmitter RTS Polarity"] -pub type TxrtspolW<'a, REG> = crate::BitWriter<'a, REG, Txrtspol>; -impl<'a, REG> TxrtspolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active low"] - #[inline(always)] - pub fn low(self) -> &'a mut crate::W { - self.variant(Txrtspol::Low) - } - #[doc = "Active high"] - #[inline(always)] - pub fn high(self) -> &'a mut crate::W { - self.variant(Txrtspol::High) - } -} -#[doc = "Receiver RTS Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxrtse { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxrtse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXRTSE` reader - Receiver RTS Enable"] -pub type RxrtseR = crate::BitReader; -impl RxrtseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxrtse { - match self.bits { - false => Rxrtse::Disabled, - true => Rxrtse::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rxrtse::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rxrtse::Enabled - } -} -#[doc = "Field `RXRTSE` writer - Receiver RTS Enable"] -pub type RxrtseW<'a, REG> = crate::BitWriter<'a, REG, Rxrtse>; -impl<'a, REG> RxrtseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rxrtse::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rxrtse::Enabled) - } -} -#[doc = "Transmit CTS Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txctsc { - #[doc = "0: Sampled at the start of each character"] - Start = 0, - #[doc = "1: Sampled when the transmitter is idle"] - Idle = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txctsc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXCTSC` reader - Transmit CTS Configuration"] -pub type TxctscR = crate::BitReader; -impl TxctscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txctsc { - match self.bits { - false => Txctsc::Start, - true => Txctsc::Idle, - } - } - #[doc = "Sampled at the start of each character"] - #[inline(always)] - pub fn is_start(&self) -> bool { - *self == Txctsc::Start - } - #[doc = "Sampled when the transmitter is idle"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Txctsc::Idle - } -} -#[doc = "Field `TXCTSC` writer - Transmit CTS Configuration"] -pub type TxctscW<'a, REG> = crate::BitWriter<'a, REG, Txctsc>; -impl<'a, REG> TxctscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Sampled at the start of each character"] - #[inline(always)] - pub fn start(self) -> &'a mut crate::W { - self.variant(Txctsc::Start) - } - #[doc = "Sampled when the transmitter is idle"] - #[inline(always)] - pub fn idle(self) -> &'a mut crate::W { - self.variant(Txctsc::Idle) - } -} -#[doc = "Transmit CTS Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Txctssrc { - #[doc = "0: The CTS_B pin"] - Cts = 0, - #[doc = "1: An internal connection to the receiver address match result"] - Match = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Txctssrc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TXCTSSRC` reader - Transmit CTS Source"] -pub type TxctssrcR = crate::BitReader; -impl TxctssrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Txctssrc { - match self.bits { - false => Txctssrc::Cts, - true => Txctssrc::Match, - } - } - #[doc = "The CTS_B pin"] - #[inline(always)] - pub fn is_cts(&self) -> bool { - *self == Txctssrc::Cts - } - #[doc = "An internal connection to the receiver address match result"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Txctssrc::Match - } -} -#[doc = "Field `TXCTSSRC` writer - Transmit CTS Source"] -pub type TxctssrcW<'a, REG> = crate::BitWriter<'a, REG, Txctssrc>; -impl<'a, REG> TxctssrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The CTS_B pin"] - #[inline(always)] - pub fn cts(self) -> &'a mut crate::W { - self.variant(Txctssrc::Cts) - } - #[doc = "An internal connection to the receiver address match result"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Txctssrc::Match) - } -} -#[doc = "Field `RTSWATER` reader - Receive RTS Configuration"] -pub type RtswaterR = crate::FieldReader; -#[doc = "Field `RTSWATER` writer - Receive RTS Configuration"] -pub type RtswaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Transmitter Narrow Pulse\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tnp { - #[doc = "0: 1 / OSR"] - OneSample = 0, - #[doc = "1: 2 / OSR"] - TwoSample = 1, - #[doc = "2: 3 / OSR"] - ThreeSample = 2, - #[doc = "3: 4 / OSR"] - FourSample = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tnp) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tnp { - type Ux = u8; -} -impl crate::IsEnum for Tnp {} -#[doc = "Field `TNP` reader - Transmitter Narrow Pulse"] -pub type TnpR = crate::FieldReader; -impl TnpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tnp { - match self.bits { - 0 => Tnp::OneSample, - 1 => Tnp::TwoSample, - 2 => Tnp::ThreeSample, - 3 => Tnp::FourSample, - _ => unreachable!(), - } - } - #[doc = "1 / OSR"] - #[inline(always)] - pub fn is_one_sample(&self) -> bool { - *self == Tnp::OneSample - } - #[doc = "2 / OSR"] - #[inline(always)] - pub fn is_two_sample(&self) -> bool { - *self == Tnp::TwoSample - } - #[doc = "3 / OSR"] - #[inline(always)] - pub fn is_three_sample(&self) -> bool { - *self == Tnp::ThreeSample - } - #[doc = "4 / OSR"] - #[inline(always)] - pub fn is_four_sample(&self) -> bool { - *self == Tnp::FourSample - } -} -#[doc = "Field `TNP` writer - Transmitter Narrow Pulse"] -pub type TnpW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tnp, crate::Safe>; -impl<'a, REG> TnpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "1 / OSR"] - #[inline(always)] - pub fn one_sample(self) -> &'a mut crate::W { - self.variant(Tnp::OneSample) - } - #[doc = "2 / OSR"] - #[inline(always)] - pub fn two_sample(self) -> &'a mut crate::W { - self.variant(Tnp::TwoSample) - } - #[doc = "3 / OSR"] - #[inline(always)] - pub fn three_sample(self) -> &'a mut crate::W { - self.variant(Tnp::ThreeSample) - } - #[doc = "4 / OSR"] - #[inline(always)] - pub fn four_sample(self) -> &'a mut crate::W { - self.variant(Tnp::FourSample) - } -} -#[doc = "IR Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Iren { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Iren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IREN` reader - IR Enable"] -pub type IrenR = crate::BitReader; -impl IrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Iren { - match self.bits { - false => Iren::Disabled, - true => Iren::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Iren::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Iren::Enabled - } -} -#[doc = "Field `IREN` writer - IR Enable"] -pub type IrenW<'a, REG> = crate::BitWriter<'a, REG, Iren>; -impl<'a, REG> IrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Iren::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Iren::Enabled) - } -} -impl R { - #[doc = "Bit 0 - Transmitter CTS Enable"] - #[inline(always)] - pub fn txctse(&self) -> TxctseR { - TxctseR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Transmitter RTS Enable"] - #[inline(always)] - pub fn txrtse(&self) -> TxrtseR { - TxrtseR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Transmitter RTS Polarity"] - #[inline(always)] - pub fn txrtspol(&self) -> TxrtspolR { - TxrtspolR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Receiver RTS Enable"] - #[inline(always)] - pub fn rxrtse(&self) -> RxrtseR { - RxrtseR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Transmit CTS Configuration"] - #[inline(always)] - pub fn txctsc(&self) -> TxctscR { - TxctscR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Transmit CTS Source"] - #[inline(always)] - pub fn txctssrc(&self) -> TxctssrcR { - TxctssrcR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bits 8:9 - Receive RTS Configuration"] - #[inline(always)] - pub fn rtswater(&self) -> RtswaterR { - RtswaterR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 16:17 - Transmitter Narrow Pulse"] - #[inline(always)] - pub fn tnp(&self) -> TnpR { - TnpR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bit 18 - IR Enable"] - #[inline(always)] - pub fn iren(&self) -> IrenR { - IrenR::new(((self.bits >> 18) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Transmitter CTS Enable"] - #[inline(always)] - pub fn txctse(&mut self) -> TxctseW { - TxctseW::new(self, 0) - } - #[doc = "Bit 1 - Transmitter RTS Enable"] - #[inline(always)] - pub fn txrtse(&mut self) -> TxrtseW { - TxrtseW::new(self, 1) - } - #[doc = "Bit 2 - Transmitter RTS Polarity"] - #[inline(always)] - pub fn txrtspol(&mut self) -> TxrtspolW { - TxrtspolW::new(self, 2) - } - #[doc = "Bit 3 - Receiver RTS Enable"] - #[inline(always)] - pub fn rxrtse(&mut self) -> RxrtseW { - RxrtseW::new(self, 3) - } - #[doc = "Bit 4 - Transmit CTS Configuration"] - #[inline(always)] - pub fn txctsc(&mut self) -> TxctscW { - TxctscW::new(self, 4) - } - #[doc = "Bit 5 - Transmit CTS Source"] - #[inline(always)] - pub fn txctssrc(&mut self) -> TxctssrcW { - TxctssrcW::new(self, 5) - } - #[doc = "Bits 8:9 - Receive RTS Configuration"] - #[inline(always)] - pub fn rtswater(&mut self) -> RtswaterW { - RtswaterW::new(self, 8) - } - #[doc = "Bits 16:17 - Transmitter Narrow Pulse"] - #[inline(always)] - pub fn tnp(&mut self) -> TnpW { - TnpW::new(self, 16) - } - #[doc = "Bit 18 - IR Enable"] - #[inline(always)] - pub fn iren(&mut self) -> IrenW { - IrenW::new(self, 18) - } -} -#[doc = "MODEM IrDA\n\nYou can [`read`](crate::Reg::read) this register and get [`modir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ModirSpec; -impl crate::RegisterSpec for ModirSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`modir::R`](R) reader structure"] -impl crate::Readable for ModirSpec {} -#[doc = "`write(|w| ..)` method takes [`modir::W`](W) writer structure"] -impl crate::Writable for ModirSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MODIR to value 0"] -impl crate::Resettable for ModirSpec {} diff --git a/mcxa276-pac/src/lpuart0/param.rs b/mcxa276-pac/src/lpuart0/param.rs deleted file mode 100644 index 083fea641..000000000 --- a/mcxa276-pac/src/lpuart0/param.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "Field `TXFIFO` reader - Transmit FIFO Size"] -pub type TxfifoR = crate::FieldReader; -#[doc = "Field `RXFIFO` reader - Receive FIFO Size"] -pub type RxfifoR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Transmit FIFO Size"] - #[inline(always)] - pub fn txfifo(&self) -> TxfifoR { - TxfifoR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Receive FIFO Size"] - #[inline(always)] - pub fn rxfifo(&self) -> RxfifoR { - RxfifoR::new(((self.bits >> 8) & 0xff) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x0202"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x0202; -} diff --git a/mcxa276-pac/src/lpuart0/pincfg.rs b/mcxa276-pac/src/lpuart0/pincfg.rs deleted file mode 100644 index e83761535..000000000 --- a/mcxa276-pac/src/lpuart0/pincfg.rs +++ /dev/null @@ -1,117 +0,0 @@ -#[doc = "Register `PINCFG` reader"] -pub type R = crate::R; -#[doc = "Register `PINCFG` writer"] -pub type W = crate::W; -#[doc = "Trigger Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trgsel { - #[doc = "0: Input trigger disabled"] - Disabled = 0, - #[doc = "1: Input trigger used instead of the RXD pin input"] - TrgRxd = 1, - #[doc = "2: Input trigger used instead of the CTS_B pin input"] - TrgCts = 2, - #[doc = "3: Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"] - TrgTxd = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trgsel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trgsel { - type Ux = u8; -} -impl crate::IsEnum for Trgsel {} -#[doc = "Field `TRGSEL` reader - Trigger Select"] -pub type TrgselR = crate::FieldReader; -impl TrgselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgsel { - match self.bits { - 0 => Trgsel::Disabled, - 1 => Trgsel::TrgRxd, - 2 => Trgsel::TrgCts, - 3 => Trgsel::TrgTxd, - _ => unreachable!(), - } - } - #[doc = "Input trigger disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Trgsel::Disabled - } - #[doc = "Input trigger used instead of the RXD pin input"] - #[inline(always)] - pub fn is_trg_rxd(&self) -> bool { - *self == Trgsel::TrgRxd - } - #[doc = "Input trigger used instead of the CTS_B pin input"] - #[inline(always)] - pub fn is_trg_cts(&self) -> bool { - *self == Trgsel::TrgCts - } - #[doc = "Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"] - #[inline(always)] - pub fn is_trg_txd(&self) -> bool { - *self == Trgsel::TrgTxd - } -} -#[doc = "Field `TRGSEL` writer - Trigger Select"] -pub type TrgselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trgsel, crate::Safe>; -impl<'a, REG> TrgselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Input trigger disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Trgsel::Disabled) - } - #[doc = "Input trigger used instead of the RXD pin input"] - #[inline(always)] - pub fn trg_rxd(self) -> &'a mut crate::W { - self.variant(Trgsel::TrgRxd) - } - #[doc = "Input trigger used instead of the CTS_B pin input"] - #[inline(always)] - pub fn trg_cts(self) -> &'a mut crate::W { - self.variant(Trgsel::TrgCts) - } - #[doc = "Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger"] - #[inline(always)] - pub fn trg_txd(self) -> &'a mut crate::W { - self.variant(Trgsel::TrgTxd) - } -} -impl R { - #[doc = "Bits 0:1 - Trigger Select"] - #[inline(always)] - pub fn trgsel(&self) -> TrgselR { - TrgselR::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Trigger Select"] - #[inline(always)] - pub fn trgsel(&mut self) -> TrgselW { - TrgselW::new(self, 0) - } -} -#[doc = "Pin Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pincfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pincfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PincfgSpec; -impl crate::RegisterSpec for PincfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pincfg::R`](R) reader structure"] -impl crate::Readable for PincfgSpec {} -#[doc = "`write(|w| ..)` method takes [`pincfg::W`](W) writer structure"] -impl crate::Writable for PincfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PINCFG to value 0"] -impl crate::Resettable for PincfgSpec {} diff --git a/mcxa276-pac/src/lpuart0/stat.rs b/mcxa276-pac/src/lpuart0/stat.rs deleted file mode 100644 index ff07daf05..000000000 --- a/mcxa276-pac/src/lpuart0/stat.rs +++ /dev/null @@ -1,1196 +0,0 @@ -#[doc = "Register `STAT` reader"] -pub type R = crate::R; -#[doc = "Register `STAT` writer"] -pub type W = crate::W; -#[doc = "LIN Break Flag Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lbkfe { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lbkfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LBKFE` reader - LIN Break Flag Enable"] -pub type LbkfeR = crate::BitReader; -impl LbkfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lbkfe { - match self.bits { - false => Lbkfe::Disabled, - true => Lbkfe::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lbkfe::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lbkfe::Enabled - } -} -#[doc = "Field `LBKFE` writer - LIN Break Flag Enable"] -pub type LbkfeW<'a, REG> = crate::BitWriter<'a, REG, Lbkfe>; -impl<'a, REG> LbkfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lbkfe::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lbkfe::Enabled) - } -} -#[doc = "Address Mark Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ame { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ame) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AME` reader - Address Mark Enable"] -pub type AmeR = crate::BitReader; -impl AmeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ame { - match self.bits { - false => Ame::Disabled, - true => Ame::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ame::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ame::Enabled - } -} -#[doc = "Field `AME` writer - Address Mark Enable"] -pub type AmeW<'a, REG> = crate::BitWriter<'a, REG, Ame>; -impl<'a, REG> AmeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ame::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ame::Enabled) - } -} -#[doc = "Match 2 Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ma2f { - #[doc = "0: Not equal to MA2"] - Nomatch = 0, - #[doc = "1: Equal to MA2"] - Match = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ma2f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MA2F` reader - Match 2 Flag"] -pub type Ma2fR = crate::BitReader; -impl Ma2fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ma2f { - match self.bits { - false => Ma2f::Nomatch, - true => Ma2f::Match, - } - } - #[doc = "Not equal to MA2"] - #[inline(always)] - pub fn is_nomatch(&self) -> bool { - *self == Ma2f::Nomatch - } - #[doc = "Equal to MA2"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Ma2f::Match - } -} -#[doc = "Field `MA2F` writer - Match 2 Flag"] -pub type Ma2fW<'a, REG> = crate::BitWriter1C<'a, REG, Ma2f>; -impl<'a, REG> Ma2fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not equal to MA2"] - #[inline(always)] - pub fn nomatch(self) -> &'a mut crate::W { - self.variant(Ma2f::Nomatch) - } - #[doc = "Equal to MA2"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Ma2f::Match) - } -} -#[doc = "Match 1 Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ma1f { - #[doc = "0: Not equal to MA1"] - Nomatch = 0, - #[doc = "1: Equal to MA1"] - Match = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ma1f) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MA1F` reader - Match 1 Flag"] -pub type Ma1fR = crate::BitReader; -impl Ma1fR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ma1f { - match self.bits { - false => Ma1f::Nomatch, - true => Ma1f::Match, - } - } - #[doc = "Not equal to MA1"] - #[inline(always)] - pub fn is_nomatch(&self) -> bool { - *self == Ma1f::Nomatch - } - #[doc = "Equal to MA1"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Ma1f::Match - } -} -#[doc = "Field `MA1F` writer - Match 1 Flag"] -pub type Ma1fW<'a, REG> = crate::BitWriter1C<'a, REG, Ma1f>; -impl<'a, REG> Ma1fW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not equal to MA1"] - #[inline(always)] - pub fn nomatch(self) -> &'a mut crate::W { - self.variant(Ma1f::Nomatch) - } - #[doc = "Equal to MA1"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Ma1f::Match) - } -} -#[doc = "Parity Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pf { - #[doc = "0: No parity error detected"] - Noparity = 0, - #[doc = "1: Parity error detected"] - Parity = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PF` reader - Parity Error Flag"] -pub type PfR = crate::BitReader; -impl PfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pf { - match self.bits { - false => Pf::Noparity, - true => Pf::Parity, - } - } - #[doc = "No parity error detected"] - #[inline(always)] - pub fn is_noparity(&self) -> bool { - *self == Pf::Noparity - } - #[doc = "Parity error detected"] - #[inline(always)] - pub fn is_parity(&self) -> bool { - *self == Pf::Parity - } -} -#[doc = "Field `PF` writer - Parity Error Flag"] -pub type PfW<'a, REG> = crate::BitWriter1C<'a, REG, Pf>; -impl<'a, REG> PfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No parity error detected"] - #[inline(always)] - pub fn noparity(self) -> &'a mut crate::W { - self.variant(Pf::Noparity) - } - #[doc = "Parity error detected"] - #[inline(always)] - pub fn parity(self) -> &'a mut crate::W { - self.variant(Pf::Parity) - } -} -#[doc = "Framing Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fe { - #[doc = "0: No framing error detected (this does not guarantee that the framing is correct)"] - Noerror = 0, - #[doc = "1: Framing error detected"] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FE` reader - Framing Error Flag"] -pub type FeR = crate::BitReader; -impl FeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fe { - match self.bits { - false => Fe::Noerror, - true => Fe::Error, - } - } - #[doc = "No framing error detected (this does not guarantee that the framing is correct)"] - #[inline(always)] - pub fn is_noerror(&self) -> bool { - *self == Fe::Noerror - } - #[doc = "Framing error detected"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Fe::Error - } -} -#[doc = "Field `FE` writer - Framing Error Flag"] -pub type FeW<'a, REG> = crate::BitWriter1C<'a, REG, Fe>; -impl<'a, REG> FeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No framing error detected (this does not guarantee that the framing is correct)"] - #[inline(always)] - pub fn noerror(self) -> &'a mut crate::W { - self.variant(Fe::Noerror) - } - #[doc = "Framing error detected"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Fe::Error) - } -} -#[doc = "Noise Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nf { - #[doc = "0: No noise detected"] - Nonoise = 0, - #[doc = "1: Noise detected"] - Noise = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NF` reader - Noise Flag"] -pub type NfR = crate::BitReader; -impl NfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nf { - match self.bits { - false => Nf::Nonoise, - true => Nf::Noise, - } - } - #[doc = "No noise detected"] - #[inline(always)] - pub fn is_nonoise(&self) -> bool { - *self == Nf::Nonoise - } - #[doc = "Noise detected"] - #[inline(always)] - pub fn is_noise(&self) -> bool { - *self == Nf::Noise - } -} -#[doc = "Field `NF` writer - Noise Flag"] -pub type NfW<'a, REG> = crate::BitWriter1C<'a, REG, Nf>; -impl<'a, REG> NfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No noise detected"] - #[inline(always)] - pub fn nonoise(self) -> &'a mut crate::W { - self.variant(Nf::Nonoise) - } - #[doc = "Noise detected"] - #[inline(always)] - pub fn noise(self) -> &'a mut crate::W { - self.variant(Nf::Noise) - } -} -#[doc = "Receiver Overrun Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Or { - #[doc = "0: No overrun"] - NoOverrun = 0, - #[doc = "1: Receive overrun (new LPUART data is lost)"] - Overrun = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Or) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OR` reader - Receiver Overrun Flag"] -pub type OrR = crate::BitReader; -impl OrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Or { - match self.bits { - false => Or::NoOverrun, - true => Or::Overrun, - } - } - #[doc = "No overrun"] - #[inline(always)] - pub fn is_no_overrun(&self) -> bool { - *self == Or::NoOverrun - } - #[doc = "Receive overrun (new LPUART data is lost)"] - #[inline(always)] - pub fn is_overrun(&self) -> bool { - *self == Or::Overrun - } -} -#[doc = "Field `OR` writer - Receiver Overrun Flag"] -pub type OrW<'a, REG> = crate::BitWriter1C<'a, REG, Or>; -impl<'a, REG> OrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overrun"] - #[inline(always)] - pub fn no_overrun(self) -> &'a mut crate::W { - self.variant(Or::NoOverrun) - } - #[doc = "Receive overrun (new LPUART data is lost)"] - #[inline(always)] - pub fn overrun(self) -> &'a mut crate::W { - self.variant(Or::Overrun) - } -} -#[doc = "Idle Line Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Idle { - #[doc = "0: Idle line detected"] - Noidle = 0, - #[doc = "1: Idle line not detected"] - Idle = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Idle) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IDLE` reader - Idle Line Flag"] -pub type IdleR = crate::BitReader; -impl IdleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Idle { - match self.bits { - false => Idle::Noidle, - true => Idle::Idle, - } - } - #[doc = "Idle line detected"] - #[inline(always)] - pub fn is_noidle(&self) -> bool { - *self == Idle::Noidle - } - #[doc = "Idle line not detected"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Idle::Idle - } -} -#[doc = "Field `IDLE` writer - Idle Line Flag"] -pub type IdleW<'a, REG> = crate::BitWriter1C<'a, REG, Idle>; -impl<'a, REG> IdleW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Idle line detected"] - #[inline(always)] - pub fn noidle(self) -> &'a mut crate::W { - self.variant(Idle::Noidle) - } - #[doc = "Idle line not detected"] - #[inline(always)] - pub fn idle(self) -> &'a mut crate::W { - self.variant(Idle::Idle) - } -} -#[doc = "Receive Data Register Full Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rdrf { - #[doc = "0: Equal to or less than watermark"] - NoRxdata = 0, - #[doc = "1: Greater than watermark"] - Rxdata = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rdrf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RDRF` reader - Receive Data Register Full Flag"] -pub type RdrfR = crate::BitReader; -impl RdrfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rdrf { - match self.bits { - false => Rdrf::NoRxdata, - true => Rdrf::Rxdata, - } - } - #[doc = "Equal to or less than watermark"] - #[inline(always)] - pub fn is_no_rxdata(&self) -> bool { - *self == Rdrf::NoRxdata - } - #[doc = "Greater than watermark"] - #[inline(always)] - pub fn is_rxdata(&self) -> bool { - *self == Rdrf::Rxdata - } -} -#[doc = "Transmission Complete Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tc { - #[doc = "0: Transmitter active"] - Active = 0, - #[doc = "1: Transmitter idle"] - Complete = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TC` reader - Transmission Complete Flag"] -pub type TcR = crate::BitReader; -impl TcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tc { - match self.bits { - false => Tc::Active, - true => Tc::Complete, - } - } - #[doc = "Transmitter active"] - #[inline(always)] - pub fn is_active(&self) -> bool { - *self == Tc::Active - } - #[doc = "Transmitter idle"] - #[inline(always)] - pub fn is_complete(&self) -> bool { - *self == Tc::Complete - } -} -#[doc = "Transmit Data Register Empty Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdre { - #[doc = "0: Greater than watermark"] - Txdata = 0, - #[doc = "1: Equal to or less than watermark"] - NoTxdata = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDRE` reader - Transmit Data Register Empty Flag"] -pub type TdreR = crate::BitReader; -impl TdreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdre { - match self.bits { - false => Tdre::Txdata, - true => Tdre::NoTxdata, - } - } - #[doc = "Greater than watermark"] - #[inline(always)] - pub fn is_txdata(&self) -> bool { - *self == Tdre::Txdata - } - #[doc = "Equal to or less than watermark"] - #[inline(always)] - pub fn is_no_txdata(&self) -> bool { - *self == Tdre::NoTxdata - } -} -#[doc = "Receiver Active Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Raf { - #[doc = "0: Idle, waiting for a start bit"] - Idle = 0, - #[doc = "1: Receiver active (RXD pin input not idle)"] - Active = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Raf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAF` reader - Receiver Active Flag"] -pub type RafR = crate::BitReader; -impl RafR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Raf { - match self.bits { - false => Raf::Idle, - true => Raf::Active, - } - } - #[doc = "Idle, waiting for a start bit"] - #[inline(always)] - pub fn is_idle(&self) -> bool { - *self == Raf::Idle - } - #[doc = "Receiver active (RXD pin input not idle)"] - #[inline(always)] - pub fn is_active(&self) -> bool { - *self == Raf::Active - } -} -#[doc = "LIN Break Detection Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lbkde { - #[doc = "0: Disable"] - Disabled = 0, - #[doc = "1: Enable"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lbkde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LBKDE` reader - LIN Break Detection Enable"] -pub type LbkdeR = crate::BitReader; -impl LbkdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lbkde { - match self.bits { - false => Lbkde::Disabled, - true => Lbkde::Enabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lbkde::Disabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lbkde::Enabled - } -} -#[doc = "Field `LBKDE` writer - LIN Break Detection Enable"] -pub type LbkdeW<'a, REG> = crate::BitWriter<'a, REG, Lbkde>; -impl<'a, REG> LbkdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lbkde::Disabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lbkde::Enabled) - } -} -#[doc = "Break Character Generation Length\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Brk13 { - #[doc = "0: 9 to 13 bit times"] - Short = 0, - #[doc = "1: 12 to 15 bit times"] - Long = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Brk13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BRK13` reader - Break Character Generation Length"] -pub type Brk13R = crate::BitReader; -impl Brk13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Brk13 { - match self.bits { - false => Brk13::Short, - true => Brk13::Long, - } - } - #[doc = "9 to 13 bit times"] - #[inline(always)] - pub fn is_short(&self) -> bool { - *self == Brk13::Short - } - #[doc = "12 to 15 bit times"] - #[inline(always)] - pub fn is_long(&self) -> bool { - *self == Brk13::Long - } -} -#[doc = "Field `BRK13` writer - Break Character Generation Length"] -pub type Brk13W<'a, REG> = crate::BitWriter<'a, REG, Brk13>; -impl<'a, REG> Brk13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "9 to 13 bit times"] - #[inline(always)] - pub fn short(self) -> &'a mut crate::W { - self.variant(Brk13::Short) - } - #[doc = "12 to 15 bit times"] - #[inline(always)] - pub fn long(self) -> &'a mut crate::W { - self.variant(Brk13::Long) - } -} -#[doc = "Receive Wake Up Idle Detect\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rwuid { - #[doc = "0: STAT\\[IDLE\\] does not become 1"] - IdleNotset = 0, - #[doc = "1: STAT\\[IDLE\\] becomes 1"] - IdleSet = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rwuid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RWUID` reader - Receive Wake Up Idle Detect"] -pub type RwuidR = crate::BitReader; -impl RwuidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rwuid { - match self.bits { - false => Rwuid::IdleNotset, - true => Rwuid::IdleSet, - } - } - #[doc = "STAT\\[IDLE\\] does not become 1"] - #[inline(always)] - pub fn is_idle_notset(&self) -> bool { - *self == Rwuid::IdleNotset - } - #[doc = "STAT\\[IDLE\\] becomes 1"] - #[inline(always)] - pub fn is_idle_set(&self) -> bool { - *self == Rwuid::IdleSet - } -} -#[doc = "Field `RWUID` writer - Receive Wake Up Idle Detect"] -pub type RwuidW<'a, REG> = crate::BitWriter<'a, REG, Rwuid>; -impl<'a, REG> RwuidW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "STAT\\[IDLE\\] does not become 1"] - #[inline(always)] - pub fn idle_notset(self) -> &'a mut crate::W { - self.variant(Rwuid::IdleNotset) - } - #[doc = "STAT\\[IDLE\\] becomes 1"] - #[inline(always)] - pub fn idle_set(self) -> &'a mut crate::W { - self.variant(Rwuid::IdleSet) - } -} -#[doc = "Receive Data Inversion\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxinv { - #[doc = "0: Inverted"] - NotInverted = 0, - #[doc = "1: Not inverted"] - Inverted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxinv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXINV` reader - Receive Data Inversion"] -pub type RxinvR = crate::BitReader; -impl RxinvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxinv { - match self.bits { - false => Rxinv::NotInverted, - true => Rxinv::Inverted, - } - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_not_inverted(&self) -> bool { - *self == Rxinv::NotInverted - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_inverted(&self) -> bool { - *self == Rxinv::Inverted - } -} -#[doc = "Field `RXINV` writer - Receive Data Inversion"] -pub type RxinvW<'a, REG> = crate::BitWriter<'a, REG, Rxinv>; -impl<'a, REG> RxinvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Inverted"] - #[inline(always)] - pub fn not_inverted(self) -> &'a mut crate::W { - self.variant(Rxinv::NotInverted) - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn inverted(self) -> &'a mut crate::W { - self.variant(Rxinv::Inverted) - } -} -#[doc = "MSB First\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Msbf { - #[doc = "0: LSB"] - LsbFirst = 0, - #[doc = "1: MSB"] - MsbFirst = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Msbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MSBF` reader - MSB First"] -pub type MsbfR = crate::BitReader; -impl MsbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Msbf { - match self.bits { - false => Msbf::LsbFirst, - true => Msbf::MsbFirst, - } - } - #[doc = "LSB"] - #[inline(always)] - pub fn is_lsb_first(&self) -> bool { - *self == Msbf::LsbFirst - } - #[doc = "MSB"] - #[inline(always)] - pub fn is_msb_first(&self) -> bool { - *self == Msbf::MsbFirst - } -} -#[doc = "Field `MSBF` writer - MSB First"] -pub type MsbfW<'a, REG> = crate::BitWriter<'a, REG, Msbf>; -impl<'a, REG> MsbfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "LSB"] - #[inline(always)] - pub fn lsb_first(self) -> &'a mut crate::W { - self.variant(Msbf::LsbFirst) - } - #[doc = "MSB"] - #[inline(always)] - pub fn msb_first(self) -> &'a mut crate::W { - self.variant(Msbf::MsbFirst) - } -} -#[doc = "RXD Pin Active Edge Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rxedgif { - #[doc = "0: Not occurred"] - NoEdge = 0, - #[doc = "1: Occurred"] - Edge = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rxedgif) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RXEDGIF` reader - RXD Pin Active Edge Interrupt Flag"] -pub type RxedgifR = crate::BitReader; -impl RxedgifR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rxedgif { - match self.bits { - false => Rxedgif::NoEdge, - true => Rxedgif::Edge, - } - } - #[doc = "Not occurred"] - #[inline(always)] - pub fn is_no_edge(&self) -> bool { - *self == Rxedgif::NoEdge - } - #[doc = "Occurred"] - #[inline(always)] - pub fn is_edge(&self) -> bool { - *self == Rxedgif::Edge - } -} -#[doc = "Field `RXEDGIF` writer - RXD Pin Active Edge Interrupt Flag"] -pub type RxedgifW<'a, REG> = crate::BitWriter1C<'a, REG, Rxedgif>; -impl<'a, REG> RxedgifW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not occurred"] - #[inline(always)] - pub fn no_edge(self) -> &'a mut crate::W { - self.variant(Rxedgif::NoEdge) - } - #[doc = "Occurred"] - #[inline(always)] - pub fn edge(self) -> &'a mut crate::W { - self.variant(Rxedgif::Edge) - } -} -#[doc = "LIN Break Detect Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lbkdif { - #[doc = "0: Not detected"] - NotDetected = 0, - #[doc = "1: Detected"] - Detected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lbkdif) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LBKDIF` reader - LIN Break Detect Interrupt Flag"] -pub type LbkdifR = crate::BitReader; -impl LbkdifR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lbkdif { - match self.bits { - false => Lbkdif::NotDetected, - true => Lbkdif::Detected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_not_detected(&self) -> bool { - *self == Lbkdif::NotDetected - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_detected(&self) -> bool { - *self == Lbkdif::Detected - } -} -#[doc = "Field `LBKDIF` writer - LIN Break Detect Interrupt Flag"] -pub type LbkdifW<'a, REG> = crate::BitWriter1C<'a, REG, Lbkdif>; -impl<'a, REG> LbkdifW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn not_detected(self) -> &'a mut crate::W { - self.variant(Lbkdif::NotDetected) - } - #[doc = "Detected"] - #[inline(always)] - pub fn detected(self) -> &'a mut crate::W { - self.variant(Lbkdif::Detected) - } -} -impl R { - #[doc = "Bit 0 - LIN Break Flag Enable"] - #[inline(always)] - pub fn lbkfe(&self) -> LbkfeR { - LbkfeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Address Mark Enable"] - #[inline(always)] - pub fn ame(&self) -> AmeR { - AmeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 14 - Match 2 Flag"] - #[inline(always)] - pub fn ma2f(&self) -> Ma2fR { - Ma2fR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Match 1 Flag"] - #[inline(always)] - pub fn ma1f(&self) -> Ma1fR { - Ma1fR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Parity Error Flag"] - #[inline(always)] - pub fn pf(&self) -> PfR { - PfR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Framing Error Flag"] - #[inline(always)] - pub fn fe(&self) -> FeR { - FeR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Noise Flag"] - #[inline(always)] - pub fn nf(&self) -> NfR { - NfR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Receiver Overrun Flag"] - #[inline(always)] - pub fn or(&self) -> OrR { - OrR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Idle Line Flag"] - #[inline(always)] - pub fn idle(&self) -> IdleR { - IdleR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Receive Data Register Full Flag"] - #[inline(always)] - pub fn rdrf(&self) -> RdrfR { - RdrfR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Transmission Complete Flag"] - #[inline(always)] - pub fn tc(&self) -> TcR { - TcR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Transmit Data Register Empty Flag"] - #[inline(always)] - pub fn tdre(&self) -> TdreR { - TdreR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Receiver Active Flag"] - #[inline(always)] - pub fn raf(&self) -> RafR { - RafR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - LIN Break Detection Enable"] - #[inline(always)] - pub fn lbkde(&self) -> LbkdeR { - LbkdeR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Break Character Generation Length"] - #[inline(always)] - pub fn brk13(&self) -> Brk13R { - Brk13R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Receive Wake Up Idle Detect"] - #[inline(always)] - pub fn rwuid(&self) -> RwuidR { - RwuidR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Receive Data Inversion"] - #[inline(always)] - pub fn rxinv(&self) -> RxinvR { - RxinvR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - MSB First"] - #[inline(always)] - pub fn msbf(&self) -> MsbfR { - MsbfR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - RXD Pin Active Edge Interrupt Flag"] - #[inline(always)] - pub fn rxedgif(&self) -> RxedgifR { - RxedgifR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - LIN Break Detect Interrupt Flag"] - #[inline(always)] - pub fn lbkdif(&self) -> LbkdifR { - LbkdifR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LIN Break Flag Enable"] - #[inline(always)] - pub fn lbkfe(&mut self) -> LbkfeW { - LbkfeW::new(self, 0) - } - #[doc = "Bit 1 - Address Mark Enable"] - #[inline(always)] - pub fn ame(&mut self) -> AmeW { - AmeW::new(self, 1) - } - #[doc = "Bit 14 - Match 2 Flag"] - #[inline(always)] - pub fn ma2f(&mut self) -> Ma2fW { - Ma2fW::new(self, 14) - } - #[doc = "Bit 15 - Match 1 Flag"] - #[inline(always)] - pub fn ma1f(&mut self) -> Ma1fW { - Ma1fW::new(self, 15) - } - #[doc = "Bit 16 - Parity Error Flag"] - #[inline(always)] - pub fn pf(&mut self) -> PfW { - PfW::new(self, 16) - } - #[doc = "Bit 17 - Framing Error Flag"] - #[inline(always)] - pub fn fe(&mut self) -> FeW { - FeW::new(self, 17) - } - #[doc = "Bit 18 - Noise Flag"] - #[inline(always)] - pub fn nf(&mut self) -> NfW { - NfW::new(self, 18) - } - #[doc = "Bit 19 - Receiver Overrun Flag"] - #[inline(always)] - pub fn or(&mut self) -> OrW { - OrW::new(self, 19) - } - #[doc = "Bit 20 - Idle Line Flag"] - #[inline(always)] - pub fn idle(&mut self) -> IdleW { - IdleW::new(self, 20) - } - #[doc = "Bit 25 - LIN Break Detection Enable"] - #[inline(always)] - pub fn lbkde(&mut self) -> LbkdeW { - LbkdeW::new(self, 25) - } - #[doc = "Bit 26 - Break Character Generation Length"] - #[inline(always)] - pub fn brk13(&mut self) -> Brk13W { - Brk13W::new(self, 26) - } - #[doc = "Bit 27 - Receive Wake Up Idle Detect"] - #[inline(always)] - pub fn rwuid(&mut self) -> RwuidW { - RwuidW::new(self, 27) - } - #[doc = "Bit 28 - Receive Data Inversion"] - #[inline(always)] - pub fn rxinv(&mut self) -> RxinvW { - RxinvW::new(self, 28) - } - #[doc = "Bit 29 - MSB First"] - #[inline(always)] - pub fn msbf(&mut self) -> MsbfW { - MsbfW::new(self, 29) - } - #[doc = "Bit 30 - RXD Pin Active Edge Interrupt Flag"] - #[inline(always)] - pub fn rxedgif(&mut self) -> RxedgifW { - RxedgifW::new(self, 30) - } - #[doc = "Bit 31 - LIN Break Detect Interrupt Flag"] - #[inline(always)] - pub fn lbkdif(&mut self) -> LbkdifW { - LbkdifW::new(self, 31) - } -} -#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StatSpec; -impl crate::RegisterSpec for StatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`stat::R`](R) reader structure"] -impl crate::Readable for StatSpec {} -#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] -impl crate::Writable for StatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xc01f_c000; -} -#[doc = "`reset()` method sets STAT to value 0x00c0_0000"] -impl crate::Resettable for StatSpec { - const RESET_VALUE: u32 = 0x00c0_0000; -} diff --git a/mcxa276-pac/src/lpuart0/verid.rs b/mcxa276-pac/src/lpuart0/verid.rs deleted file mode 100644 index eacb59d81..000000000 --- a/mcxa276-pac/src/lpuart0/verid.rs +++ /dev/null @@ -1,76 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Identification Number\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "1: Standard feature set"] - Standard = 1, - #[doc = "3: Standard feature set with MODEM and IrDA support"] - Modem = 3, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Identification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Feature::Standard), - 3 => Some(Feature::Modem), - _ => None, - } - } - #[doc = "Standard feature set"] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == Feature::Standard - } - #[doc = "Standard feature set with MODEM and IrDA support"] - #[inline(always)] - pub fn is_modem(&self) -> bool { - *self == Feature::Modem - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Identification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0405_0003"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0405_0003; -} diff --git a/mcxa276-pac/src/lpuart0/water.rs b/mcxa276-pac/src/lpuart0/water.rs deleted file mode 100644 index 1e868bfae..000000000 --- a/mcxa276-pac/src/lpuart0/water.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `WATER` reader"] -pub type R = crate::R; -#[doc = "Register `WATER` writer"] -pub type W = crate::W; -#[doc = "Field `TXWATER` reader - Transmit Watermark"] -pub type TxwaterR = crate::FieldReader; -#[doc = "Field `TXWATER` writer - Transmit Watermark"] -pub type TxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TXCOUNT` reader - Transmit Counter"] -pub type TxcountR = crate::FieldReader; -#[doc = "Field `RXWATER` reader - Receive Watermark"] -pub type RxwaterR = crate::FieldReader; -#[doc = "Field `RXWATER` writer - Receive Watermark"] -pub type RxwaterW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `RXCOUNT` reader - Receive Counter"] -pub type RxcountR = crate::FieldReader; -impl R { - #[doc = "Bits 0:1 - Transmit Watermark"] - #[inline(always)] - pub fn txwater(&self) -> TxwaterR { - TxwaterR::new((self.bits & 3) as u8) - } - #[doc = "Bits 8:10 - Transmit Counter"] - #[inline(always)] - pub fn txcount(&self) -> TxcountR { - TxcountR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 16:17 - Receive Watermark"] - #[inline(always)] - pub fn rxwater(&self) -> RxwaterR { - RxwaterR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 24:26 - Receive Counter"] - #[inline(always)] - pub fn rxcount(&self) -> RxcountR { - RxcountR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Transmit Watermark"] - #[inline(always)] - pub fn txwater(&mut self) -> TxwaterW { - TxwaterW::new(self, 0) - } - #[doc = "Bits 16:17 - Receive Watermark"] - #[inline(always)] - pub fn rxwater(&mut self) -> RxwaterW { - RxwaterW::new(self, 16) - } -} -#[doc = "Watermark\n\nYou can [`read`](crate::Reg::read) this register and get [`water::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`water::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WaterSpec; -impl crate::RegisterSpec for WaterSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`water::R`](R) reader structure"] -impl crate::Readable for WaterSpec {} -#[doc = "`write(|w| ..)` method takes [`water::W`](W) writer structure"] -impl crate::Writable for WaterSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WATER to value 0"] -impl crate::Resettable for WaterSpec {} diff --git a/mcxa276-pac/src/mau0.rs b/mcxa276-pac/src/mau0.rs deleted file mode 100644 index 08b760472..000000000 --- a/mcxa276-pac/src/mau0.rs +++ /dev/null @@ -1,119 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x10], - sys_ctlr: SysCtlr, - gexp_status_ie: GexpStatusIe, - gexp_status: GexpStatus, - _reserved3: [u8; 0x14], - op_ctrl: OpCtrl, - _reserved4: [u8; 0x04], - res_status_ie: ResStatusIe, - res_status: ResStatus, - res0: Res0, - res1: Res1, - res2: Res2, - res3: Res3, -} -impl RegisterBlock { - #[doc = "0x10 - System Control"] - #[inline(always)] - pub const fn sys_ctlr(&self) -> &SysCtlr { - &self.sys_ctlr - } - #[doc = "0x14 - General Exception Status Interrupt Enable"] - #[inline(always)] - pub const fn gexp_status_ie(&self) -> &GexpStatusIe { - &self.gexp_status_ie - } - #[doc = "0x18 - General Exception Status"] - #[inline(always)] - pub const fn gexp_status(&self) -> &GexpStatus { - &self.gexp_status - } - #[doc = "0x30 - Operation Control"] - #[inline(always)] - pub const fn op_ctrl(&self) -> &OpCtrl { - &self.op_ctrl - } - #[doc = "0x38 - Result Status Interrupt Enable"] - #[inline(always)] - pub const fn res_status_ie(&self) -> &ResStatusIe { - &self.res_status_ie - } - #[doc = "0x3c - Result Status"] - #[inline(always)] - pub const fn res_status(&self) -> &ResStatus { - &self.res_status - } - #[doc = "0x40 - Result Register 0"] - #[inline(always)] - pub const fn res0(&self) -> &Res0 { - &self.res0 - } - #[doc = "0x44 - Result Register 1"] - #[inline(always)] - pub const fn res1(&self) -> &Res1 { - &self.res1 - } - #[doc = "0x48 - Result Register 2"] - #[inline(always)] - pub const fn res2(&self) -> &Res2 { - &self.res2 - } - #[doc = "0x4c - Result Register 3"] - #[inline(always)] - pub const fn res3(&self) -> &Res3 { - &self.res3 - } -} -#[doc = "SYS_CTLR (rw) register accessor: System Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_ctlr`] module"] -#[doc(alias = "SYS_CTLR")] -pub type SysCtlr = crate::Reg; -#[doc = "System Control"] -pub mod sys_ctlr; -#[doc = "GEXP_STATUS_IE (rw) register accessor: General Exception Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status_ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status_ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gexp_status_ie`] module"] -#[doc(alias = "GEXP_STATUS_IE")] -pub type GexpStatusIe = crate::Reg; -#[doc = "General Exception Status Interrupt Enable"] -pub mod gexp_status_ie; -#[doc = "GEXP_STATUS (rw) register accessor: General Exception Status\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gexp_status`] module"] -#[doc(alias = "GEXP_STATUS")] -pub type GexpStatus = crate::Reg; -#[doc = "General Exception Status"] -pub mod gexp_status; -#[doc = "OP_CTRL (rw) register accessor: Operation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`op_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@op_ctrl`] module"] -#[doc(alias = "OP_CTRL")] -pub type OpCtrl = crate::Reg; -#[doc = "Operation Control"] -pub mod op_ctrl; -#[doc = "RES_STATUS_IE (rw) register accessor: Result Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status_ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status_ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res_status_ie`] module"] -#[doc(alias = "RES_STATUS_IE")] -pub type ResStatusIe = crate::Reg; -#[doc = "Result Status Interrupt Enable"] -pub mod res_status_ie; -#[doc = "RES_STATUS (rw) register accessor: Result Status\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res_status`] module"] -#[doc(alias = "RES_STATUS")] -pub type ResStatus = crate::Reg; -#[doc = "Result Status"] -pub mod res_status; -#[doc = "RES0 (rw) register accessor: Result Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`res0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res0`] module"] -#[doc(alias = "RES0")] -pub type Res0 = crate::Reg; -#[doc = "Result Register 0"] -pub mod res0; -#[doc = "RES1 (rw) register accessor: Result Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`res1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res1`] module"] -#[doc(alias = "RES1")] -pub type Res1 = crate::Reg; -#[doc = "Result Register 1"] -pub mod res1; -#[doc = "RES2 (rw) register accessor: Result Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`res2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res2`] module"] -#[doc(alias = "RES2")] -pub type Res2 = crate::Reg; -#[doc = "Result Register 2"] -pub mod res2; -#[doc = "RES3 (rw) register accessor: Result Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`res3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res3`] module"] -#[doc(alias = "RES3")] -pub type Res3 = crate::Reg; -#[doc = "Result Register 3"] -pub mod res3; diff --git a/mcxa276-pac/src/mau0/gexp_status.rs b/mcxa276-pac/src/mau0/gexp_status.rs deleted file mode 100644 index 4b3433bb2..000000000 --- a/mcxa276-pac/src/mau0/gexp_status.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `GEXP_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `GEXP_STATUS` writer"] -pub type W = crate::W; -#[doc = "Direct operation Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Error { - #[doc = "0: No error is generated."] - NoError = 0, - #[doc = "1: An error is generated."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Error) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERROR` reader - Direct operation Error"] -pub type ErrorR = crate::BitReader; -impl ErrorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Error { - match self.bits { - false => Error::NoError, - true => Error::Error, - } - } - #[doc = "No error is generated."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Error::NoError - } - #[doc = "An error is generated."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Error::Error - } -} -#[doc = "Field `ERROR` writer - Direct operation Error"] -pub type ErrorW<'a, REG> = crate::BitWriter<'a, REG, Error>; -impl<'a, REG> ErrorW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error is generated."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Error::NoError) - } - #[doc = "An error is generated."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Error::Error) - } -} -impl R { - #[doc = "Bit 0 - Direct operation Error"] - #[inline(always)] - pub fn error(&self) -> ErrorR { - ErrorR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Direct operation Error"] - #[inline(always)] - pub fn error(&mut self) -> ErrorW { - ErrorW::new(self, 0) - } -} -#[doc = "General Exception Status\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GexpStatusSpec; -impl crate::RegisterSpec for GexpStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gexp_status::R`](R) reader structure"] -impl crate::Readable for GexpStatusSpec {} -#[doc = "`write(|w| ..)` method takes [`gexp_status::W`](W) writer structure"] -impl crate::Writable for GexpStatusSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GEXP_STATUS to value 0"] -impl crate::Resettable for GexpStatusSpec {} diff --git a/mcxa276-pac/src/mau0/gexp_status_ie.rs b/mcxa276-pac/src/mau0/gexp_status_ie.rs deleted file mode 100644 index 2250dad90..000000000 --- a/mcxa276-pac/src/mau0/gexp_status_ie.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `GEXP_STATUS_IE` reader"] -pub type R = crate::R; -#[doc = "Register `GEXP_STATUS_IE` writer"] -pub type W = crate::W; -#[doc = "Direct operation Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ErrorIe { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ErrorIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERROR_IE` reader - Direct operation Error Interrupt Enable"] -pub type ErrorIeR = crate::BitReader; -impl ErrorIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ErrorIe { - match self.bits { - false => ErrorIe::Disable, - true => ErrorIe::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == ErrorIe::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == ErrorIe::Enable - } -} -#[doc = "Field `ERROR_IE` writer - Direct operation Error Interrupt Enable"] -pub type ErrorIeW<'a, REG> = crate::BitWriter<'a, REG, ErrorIe>; -impl<'a, REG> ErrorIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(ErrorIe::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(ErrorIe::Enable) - } -} -impl R { - #[doc = "Bit 0 - Direct operation Error Interrupt Enable"] - #[inline(always)] - pub fn error_ie(&self) -> ErrorIeR { - ErrorIeR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Direct operation Error Interrupt Enable"] - #[inline(always)] - pub fn error_ie(&mut self) -> ErrorIeW { - ErrorIeW::new(self, 0) - } -} -#[doc = "General Exception Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`gexp_status_ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gexp_status_ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GexpStatusIeSpec; -impl crate::RegisterSpec for GexpStatusIeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gexp_status_ie::R`](R) reader structure"] -impl crate::Readable for GexpStatusIeSpec {} -#[doc = "`write(|w| ..)` method takes [`gexp_status_ie::W`](W) writer structure"] -impl crate::Writable for GexpStatusIeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GEXP_STATUS_IE to value 0"] -impl crate::Resettable for GexpStatusIeSpec {} diff --git a/mcxa276-pac/src/mau0/op_ctrl.rs b/mcxa276-pac/src/mau0/op_ctrl.rs deleted file mode 100644 index b3529d016..000000000 --- a/mcxa276-pac/src/mau0/op_ctrl.rs +++ /dev/null @@ -1,657 +0,0 @@ -#[doc = "Register `OP_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `OP_CTRL` writer"] -pub type W = crate::W; -#[doc = "Override RES0 Data Type Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OvdtEnRes0 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OvdtEnRes0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OVDT_EN_RES0` reader - Override RES0 Data Type Enable"] -pub type OvdtEnRes0R = crate::BitReader; -impl OvdtEnRes0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtEnRes0 { - match self.bits { - false => OvdtEnRes0::Disable, - true => OvdtEnRes0::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == OvdtEnRes0::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == OvdtEnRes0::Enable - } -} -#[doc = "Field `OVDT_EN_RES0` writer - Override RES0 Data Type Enable"] -pub type OvdtEnRes0W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes0>; -impl<'a, REG> OvdtEnRes0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes0::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes0::Enable) - } -} -#[doc = "Override RES0 Data Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OvdtRes0 { - #[doc = "0: UINT"] - Uint = 0, - #[doc = "1: INT"] - Int = 1, - #[doc = "2: Q1.X"] - Q1X = 2, - #[doc = "3: FLOAT"] - Float = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OvdtRes0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OvdtRes0 { - type Ux = u8; -} -impl crate::IsEnum for OvdtRes0 {} -#[doc = "Field `OVDT_RES0` reader - Override RES0 Data Type"] -pub type OvdtRes0R = crate::FieldReader; -impl OvdtRes0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtRes0 { - match self.bits { - 0 => OvdtRes0::Uint, - 1 => OvdtRes0::Int, - 2 => OvdtRes0::Q1X, - 3 => OvdtRes0::Float, - _ => unreachable!(), - } - } - #[doc = "UINT"] - #[inline(always)] - pub fn is_uint(&self) -> bool { - *self == OvdtRes0::Uint - } - #[doc = "INT"] - #[inline(always)] - pub fn is_int(&self) -> bool { - *self == OvdtRes0::Int - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn is_q1_x(&self) -> bool { - *self == OvdtRes0::Q1X - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn is_float(&self) -> bool { - *self == OvdtRes0::Float - } -} -#[doc = "Field `OVDT_RES0` writer - Override RES0 Data Type"] -pub type OvdtRes0W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes0, crate::Safe>; -impl<'a, REG> OvdtRes0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "UINT"] - #[inline(always)] - pub fn uint(self) -> &'a mut crate::W { - self.variant(OvdtRes0::Uint) - } - #[doc = "INT"] - #[inline(always)] - pub fn int(self) -> &'a mut crate::W { - self.variant(OvdtRes0::Int) - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn q1_x(self) -> &'a mut crate::W { - self.variant(OvdtRes0::Q1X) - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn float(self) -> &'a mut crate::W { - self.variant(OvdtRes0::Float) - } -} -#[doc = "Override RES1 Data Type Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OvdtEnRes1 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OvdtEnRes1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OVDT_EN_RES1` reader - Override RES1 Data Type Enable"] -pub type OvdtEnRes1R = crate::BitReader; -impl OvdtEnRes1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtEnRes1 { - match self.bits { - false => OvdtEnRes1::Disable, - true => OvdtEnRes1::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == OvdtEnRes1::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == OvdtEnRes1::Enable - } -} -#[doc = "Field `OVDT_EN_RES1` writer - Override RES1 Data Type Enable"] -pub type OvdtEnRes1W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes1>; -impl<'a, REG> OvdtEnRes1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes1::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes1::Enable) - } -} -#[doc = "Override RES1 Data Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OvdtRes1 { - #[doc = "0: UINT"] - Uint = 0, - #[doc = "1: INT"] - Int = 1, - #[doc = "2: Q1.X"] - Q1X = 2, - #[doc = "3: FLOAT"] - Float = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OvdtRes1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OvdtRes1 { - type Ux = u8; -} -impl crate::IsEnum for OvdtRes1 {} -#[doc = "Field `OVDT_RES1` reader - Override RES1 Data Type"] -pub type OvdtRes1R = crate::FieldReader; -impl OvdtRes1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtRes1 { - match self.bits { - 0 => OvdtRes1::Uint, - 1 => OvdtRes1::Int, - 2 => OvdtRes1::Q1X, - 3 => OvdtRes1::Float, - _ => unreachable!(), - } - } - #[doc = "UINT"] - #[inline(always)] - pub fn is_uint(&self) -> bool { - *self == OvdtRes1::Uint - } - #[doc = "INT"] - #[inline(always)] - pub fn is_int(&self) -> bool { - *self == OvdtRes1::Int - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn is_q1_x(&self) -> bool { - *self == OvdtRes1::Q1X - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn is_float(&self) -> bool { - *self == OvdtRes1::Float - } -} -#[doc = "Field `OVDT_RES1` writer - Override RES1 Data Type"] -pub type OvdtRes1W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes1, crate::Safe>; -impl<'a, REG> OvdtRes1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "UINT"] - #[inline(always)] - pub fn uint(self) -> &'a mut crate::W { - self.variant(OvdtRes1::Uint) - } - #[doc = "INT"] - #[inline(always)] - pub fn int(self) -> &'a mut crate::W { - self.variant(OvdtRes1::Int) - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn q1_x(self) -> &'a mut crate::W { - self.variant(OvdtRes1::Q1X) - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn float(self) -> &'a mut crate::W { - self.variant(OvdtRes1::Float) - } -} -#[doc = "Override RES2 Data Type Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OvdtEnRes2 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OvdtEnRes2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OVDT_EN_RES2` reader - Override RES2 Data Type Enable"] -pub type OvdtEnRes2R = crate::BitReader; -impl OvdtEnRes2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtEnRes2 { - match self.bits { - false => OvdtEnRes2::Disable, - true => OvdtEnRes2::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == OvdtEnRes2::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == OvdtEnRes2::Enable - } -} -#[doc = "Field `OVDT_EN_RES2` writer - Override RES2 Data Type Enable"] -pub type OvdtEnRes2W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes2>; -impl<'a, REG> OvdtEnRes2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes2::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes2::Enable) - } -} -#[doc = "Override RES2 Data Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OvdtRes2 { - #[doc = "0: UINT"] - Uint = 0, - #[doc = "1: INT"] - Int = 1, - #[doc = "2: Q1.X"] - Q1X = 2, - #[doc = "3: FLOAT"] - Float = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OvdtRes2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OvdtRes2 { - type Ux = u8; -} -impl crate::IsEnum for OvdtRes2 {} -#[doc = "Field `OVDT_RES2` reader - Override RES2 Data Type"] -pub type OvdtRes2R = crate::FieldReader; -impl OvdtRes2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtRes2 { - match self.bits { - 0 => OvdtRes2::Uint, - 1 => OvdtRes2::Int, - 2 => OvdtRes2::Q1X, - 3 => OvdtRes2::Float, - _ => unreachable!(), - } - } - #[doc = "UINT"] - #[inline(always)] - pub fn is_uint(&self) -> bool { - *self == OvdtRes2::Uint - } - #[doc = "INT"] - #[inline(always)] - pub fn is_int(&self) -> bool { - *self == OvdtRes2::Int - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn is_q1_x(&self) -> bool { - *self == OvdtRes2::Q1X - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn is_float(&self) -> bool { - *self == OvdtRes2::Float - } -} -#[doc = "Field `OVDT_RES2` writer - Override RES2 Data Type"] -pub type OvdtRes2W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes2, crate::Safe>; -impl<'a, REG> OvdtRes2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "UINT"] - #[inline(always)] - pub fn uint(self) -> &'a mut crate::W { - self.variant(OvdtRes2::Uint) - } - #[doc = "INT"] - #[inline(always)] - pub fn int(self) -> &'a mut crate::W { - self.variant(OvdtRes2::Int) - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn q1_x(self) -> &'a mut crate::W { - self.variant(OvdtRes2::Q1X) - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn float(self) -> &'a mut crate::W { - self.variant(OvdtRes2::Float) - } -} -#[doc = "Override RES3 Data Type Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OvdtEnRes3 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OvdtEnRes3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OVDT_EN_RES3` reader - Override RES3 Data Type Enable"] -pub type OvdtEnRes3R = crate::BitReader; -impl OvdtEnRes3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtEnRes3 { - match self.bits { - false => OvdtEnRes3::Disable, - true => OvdtEnRes3::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == OvdtEnRes3::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == OvdtEnRes3::Enable - } -} -#[doc = "Field `OVDT_EN_RES3` writer - Override RES3 Data Type Enable"] -pub type OvdtEnRes3W<'a, REG> = crate::BitWriter<'a, REG, OvdtEnRes3>; -impl<'a, REG> OvdtEnRes3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes3::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(OvdtEnRes3::Enable) - } -} -#[doc = "Override RES3 Data Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OvdtRes3 { - #[doc = "0: UINT"] - Uint = 0, - #[doc = "1: INT"] - Int = 1, - #[doc = "2: Q1.X"] - Q1X = 2, - #[doc = "3: FLOAT"] - Float = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OvdtRes3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OvdtRes3 { - type Ux = u8; -} -impl crate::IsEnum for OvdtRes3 {} -#[doc = "Field `OVDT_RES3` reader - Override RES3 Data Type"] -pub type OvdtRes3R = crate::FieldReader; -impl OvdtRes3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvdtRes3 { - match self.bits { - 0 => OvdtRes3::Uint, - 1 => OvdtRes3::Int, - 2 => OvdtRes3::Q1X, - 3 => OvdtRes3::Float, - _ => unreachable!(), - } - } - #[doc = "UINT"] - #[inline(always)] - pub fn is_uint(&self) -> bool { - *self == OvdtRes3::Uint - } - #[doc = "INT"] - #[inline(always)] - pub fn is_int(&self) -> bool { - *self == OvdtRes3::Int - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn is_q1_x(&self) -> bool { - *self == OvdtRes3::Q1X - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn is_float(&self) -> bool { - *self == OvdtRes3::Float - } -} -#[doc = "Field `OVDT_RES3` writer - Override RES3 Data Type"] -pub type OvdtRes3W<'a, REG> = crate::FieldWriter<'a, REG, 2, OvdtRes3, crate::Safe>; -impl<'a, REG> OvdtRes3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "UINT"] - #[inline(always)] - pub fn uint(self) -> &'a mut crate::W { - self.variant(OvdtRes3::Uint) - } - #[doc = "INT"] - #[inline(always)] - pub fn int(self) -> &'a mut crate::W { - self.variant(OvdtRes3::Int) - } - #[doc = "Q1.X"] - #[inline(always)] - pub fn q1_x(self) -> &'a mut crate::W { - self.variant(OvdtRes3::Q1X) - } - #[doc = "FLOAT"] - #[inline(always)] - pub fn float(self) -> &'a mut crate::W { - self.variant(OvdtRes3::Float) - } -} -impl R { - #[doc = "Bit 0 - Override RES0 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res0(&self) -> OvdtEnRes0R { - OvdtEnRes0R::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:2 - Override RES0 Data Type"] - #[inline(always)] - pub fn ovdt_res0(&self) -> OvdtRes0R { - OvdtRes0R::new(((self.bits >> 1) & 3) as u8) - } - #[doc = "Bit 8 - Override RES1 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res1(&self) -> OvdtEnRes1R { - OvdtEnRes1R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 9:10 - Override RES1 Data Type"] - #[inline(always)] - pub fn ovdt_res1(&self) -> OvdtRes1R { - OvdtRes1R::new(((self.bits >> 9) & 3) as u8) - } - #[doc = "Bit 16 - Override RES2 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res2(&self) -> OvdtEnRes2R { - OvdtEnRes2R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bits 17:18 - Override RES2 Data Type"] - #[inline(always)] - pub fn ovdt_res2(&self) -> OvdtRes2R { - OvdtRes2R::new(((self.bits >> 17) & 3) as u8) - } - #[doc = "Bit 24 - Override RES3 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res3(&self) -> OvdtEnRes3R { - OvdtEnRes3R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bits 25:26 - Override RES3 Data Type"] - #[inline(always)] - pub fn ovdt_res3(&self) -> OvdtRes3R { - OvdtRes3R::new(((self.bits >> 25) & 3) as u8) - } -} -impl W { - #[doc = "Bit 0 - Override RES0 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res0(&mut self) -> OvdtEnRes0W { - OvdtEnRes0W::new(self, 0) - } - #[doc = "Bits 1:2 - Override RES0 Data Type"] - #[inline(always)] - pub fn ovdt_res0(&mut self) -> OvdtRes0W { - OvdtRes0W::new(self, 1) - } - #[doc = "Bit 8 - Override RES1 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res1(&mut self) -> OvdtEnRes1W { - OvdtEnRes1W::new(self, 8) - } - #[doc = "Bits 9:10 - Override RES1 Data Type"] - #[inline(always)] - pub fn ovdt_res1(&mut self) -> OvdtRes1W { - OvdtRes1W::new(self, 9) - } - #[doc = "Bit 16 - Override RES2 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res2(&mut self) -> OvdtEnRes2W { - OvdtEnRes2W::new(self, 16) - } - #[doc = "Bits 17:18 - Override RES2 Data Type"] - #[inline(always)] - pub fn ovdt_res2(&mut self) -> OvdtRes2W { - OvdtRes2W::new(self, 17) - } - #[doc = "Bit 24 - Override RES3 Data Type Enable"] - #[inline(always)] - pub fn ovdt_en_res3(&mut self) -> OvdtEnRes3W { - OvdtEnRes3W::new(self, 24) - } - #[doc = "Bits 25:26 - Override RES3 Data Type"] - #[inline(always)] - pub fn ovdt_res3(&mut self) -> OvdtRes3W { - OvdtRes3W::new(self, 25) - } -} -#[doc = "Operation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`op_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OpCtrlSpec; -impl crate::RegisterSpec for OpCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`op_ctrl::R`](R) reader structure"] -impl crate::Readable for OpCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`op_ctrl::W`](W) writer structure"] -impl crate::Writable for OpCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets OP_CTRL to value 0"] -impl crate::Resettable for OpCtrlSpec {} diff --git a/mcxa276-pac/src/mau0/res0.rs b/mcxa276-pac/src/mau0/res0.rs deleted file mode 100644 index 618913b87..000000000 --- a/mcxa276-pac/src/mau0/res0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RES0` reader"] -pub type R = crate::R; -#[doc = "Register `RES0` writer"] -pub type W = crate::W; -#[doc = "Field `MAU_RES0` reader - MAUWRAP Result Register 0"] -pub type MauRes0R = crate::FieldReader; -#[doc = "Field `MAU_RES0` writer - MAUWRAP Result Register 0"] -pub type MauRes0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - MAUWRAP Result Register 0"] - #[inline(always)] - pub fn mau_res0(&self) -> MauRes0R { - MauRes0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - MAUWRAP Result Register 0"] - #[inline(always)] - pub fn mau_res0(&mut self) -> MauRes0W { - MauRes0W::new(self, 0) - } -} -#[doc = "Result Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`res0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Res0Spec; -impl crate::RegisterSpec for Res0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`res0::R`](R) reader structure"] -impl crate::Readable for Res0Spec {} -#[doc = "`write(|w| ..)` method takes [`res0::W`](W) writer structure"] -impl crate::Writable for Res0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RES0 to value 0"] -impl crate::Resettable for Res0Spec {} diff --git a/mcxa276-pac/src/mau0/res1.rs b/mcxa276-pac/src/mau0/res1.rs deleted file mode 100644 index 9a240ef00..000000000 --- a/mcxa276-pac/src/mau0/res1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RES1` reader"] -pub type R = crate::R; -#[doc = "Register `RES1` writer"] -pub type W = crate::W; -#[doc = "Field `MAU_RES1` reader - MAUWRAP Result Register 1"] -pub type MauRes1R = crate::FieldReader; -#[doc = "Field `MAU_RES1` writer - MAUWRAP Result Register 1"] -pub type MauRes1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - MAUWRAP Result Register 1"] - #[inline(always)] - pub fn mau_res1(&self) -> MauRes1R { - MauRes1R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - MAUWRAP Result Register 1"] - #[inline(always)] - pub fn mau_res1(&mut self) -> MauRes1W { - MauRes1W::new(self, 0) - } -} -#[doc = "Result Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`res1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Res1Spec; -impl crate::RegisterSpec for Res1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`res1::R`](R) reader structure"] -impl crate::Readable for Res1Spec {} -#[doc = "`write(|w| ..)` method takes [`res1::W`](W) writer structure"] -impl crate::Writable for Res1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RES1 to value 0"] -impl crate::Resettable for Res1Spec {} diff --git a/mcxa276-pac/src/mau0/res2.rs b/mcxa276-pac/src/mau0/res2.rs deleted file mode 100644 index e7cea2e3c..000000000 --- a/mcxa276-pac/src/mau0/res2.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RES2` reader"] -pub type R = crate::R; -#[doc = "Register `RES2` writer"] -pub type W = crate::W; -#[doc = "Field `MAU_RES2` reader - MAUWRAP Result Register 2"] -pub type MauRes2R = crate::FieldReader; -#[doc = "Field `MAU_RES2` writer - MAUWRAP Result Register 2"] -pub type MauRes2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - MAUWRAP Result Register 2"] - #[inline(always)] - pub fn mau_res2(&self) -> MauRes2R { - MauRes2R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - MAUWRAP Result Register 2"] - #[inline(always)] - pub fn mau_res2(&mut self) -> MauRes2W { - MauRes2W::new(self, 0) - } -} -#[doc = "Result Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`res2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Res2Spec; -impl crate::RegisterSpec for Res2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`res2::R`](R) reader structure"] -impl crate::Readable for Res2Spec {} -#[doc = "`write(|w| ..)` method takes [`res2::W`](W) writer structure"] -impl crate::Writable for Res2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RES2 to value 0"] -impl crate::Resettable for Res2Spec {} diff --git a/mcxa276-pac/src/mau0/res3.rs b/mcxa276-pac/src/mau0/res3.rs deleted file mode 100644 index 900a97403..000000000 --- a/mcxa276-pac/src/mau0/res3.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RES3` reader"] -pub type R = crate::R; -#[doc = "Register `RES3` writer"] -pub type W = crate::W; -#[doc = "Field `MAU_RES3` reader - MAUWRAP Result Register 3"] -pub type MauRes3R = crate::FieldReader; -#[doc = "Field `MAU_RES3` writer - MAUWRAP Result Register 3"] -pub type MauRes3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - MAUWRAP Result Register 3"] - #[inline(always)] - pub fn mau_res3(&self) -> MauRes3R { - MauRes3R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - MAUWRAP Result Register 3"] - #[inline(always)] - pub fn mau_res3(&mut self) -> MauRes3W { - MauRes3W::new(self, 0) - } -} -#[doc = "Result Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`res3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Res3Spec; -impl crate::RegisterSpec for Res3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`res3::R`](R) reader structure"] -impl crate::Readable for Res3Spec {} -#[doc = "`write(|w| ..)` method takes [`res3::W`](W) writer structure"] -impl crate::Writable for Res3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RES3 to value 0"] -impl crate::Resettable for Res3Spec {} diff --git a/mcxa276-pac/src/mau0/res_status.rs b/mcxa276-pac/src/mau0/res_status.rs deleted file mode 100644 index 29a47790c..000000000 --- a/mcxa276-pac/src/mau0/res_status.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `RES_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `RES_STATUS` writer"] -pub type W = crate::W; -#[doc = "RES0 IEEE Inexact Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Nx { - #[doc = "0: The result is not rounded."] - Res0NxNo = 0, - #[doc = "1: The result is rounded, and as a result some digits lost."] - Res0NxYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Nx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_NX` reader - RES0 IEEE Inexact Flag"] -pub type Res0NxR = crate::BitReader; -impl Res0NxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Nx { - match self.bits { - false => Res0Nx::Res0NxNo, - true => Res0Nx::Res0NxYes, - } - } - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn is_res0_nx_no(&self) -> bool { - *self == Res0Nx::Res0NxNo - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn is_res0_nx_yes(&self) -> bool { - *self == Res0Nx::Res0NxYes - } -} -#[doc = "Field `RES0_NX` writer - RES0 IEEE Inexact Flag"] -pub type Res0NxW<'a, REG> = crate::BitWriter<'a, REG, Res0Nx>; -impl<'a, REG> Res0NxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn res0_nx_no(self) -> &'a mut crate::W { - self.variant(Res0Nx::Res0NxNo) - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn res0_nx_yes(self) -> &'a mut crate::W { - self.variant(Res0Nx::Res0NxYes) - } -} -#[doc = "RES0 IEEE Underflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Uf { - #[doc = "0: No tiny non-zero result is detected."] - Res0UfNo = 0, - #[doc = "1: A tiny non-zero result is detected."] - Res0UfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Uf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_UF` reader - RES0 IEEE Underflow Flag"] -pub type Res0UfR = crate::BitReader; -impl Res0UfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Uf { - match self.bits { - false => Res0Uf::Res0UfNo, - true => Res0Uf::Res0UfYes, - } - } - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res0_uf_no(&self) -> bool { - *self == Res0Uf::Res0UfNo - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res0_uf_yes(&self) -> bool { - *self == Res0Uf::Res0UfYes - } -} -#[doc = "Field `RES0_UF` writer - RES0 IEEE Underflow Flag"] -pub type Res0UfW<'a, REG> = crate::BitWriter<'a, REG, Res0Uf>; -impl<'a, REG> Res0UfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn res0_uf_no(self) -> &'a mut crate::W { - self.variant(Res0Uf::Res0UfNo) - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn res0_uf_yes(self) -> &'a mut crate::W { - self.variant(Res0Uf::Res0UfYes) - } -} -#[doc = "RES0 IEEE Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Of { - #[doc = "0: The result format's largest finite number is not exceeded."] - Res0OfNo = 0, - #[doc = "1: The result format's largest finite number is exceeded."] - Res0OfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Of) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_OF` reader - RES0 IEEE Overflow Flag"] -pub type Res0OfR = crate::BitReader; -impl Res0OfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Of { - match self.bits { - false => Res0Of::Res0OfNo, - true => Res0Of::Res0OfYes, - } - } - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn is_res0_of_no(&self) -> bool { - *self == Res0Of::Res0OfNo - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn is_res0_of_yes(&self) -> bool { - *self == Res0Of::Res0OfYes - } -} -#[doc = "Field `RES0_OF` writer - RES0 IEEE Overflow Flag"] -pub type Res0OfW<'a, REG> = crate::BitWriter<'a, REG, Res0Of>; -impl<'a, REG> Res0OfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn res0_of_no(self) -> &'a mut crate::W { - self.variant(Res0Of::Res0OfNo) - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn res0_of_yes(self) -> &'a mut crate::W { - self.variant(Res0Of::Res0OfYes) - } -} -#[doc = "RES0 IEEE Divide by Zero Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Dz { - #[doc = "0: No exact infinite result is defined for an operation on finite operands."] - Res0DzNo = 0, - #[doc = "1: An exact infinite result is defined for an operation on finite operands."] - Res0DzYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Dz) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_DZ` reader - RES0 IEEE Divide by Zero Flag"] -pub type Res0DzR = crate::BitReader; -impl Res0DzR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Dz { - match self.bits { - false => Res0Dz::Res0DzNo, - true => Res0Dz::Res0DzYes, - } - } - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res0_dz_no(&self) -> bool { - *self == Res0Dz::Res0DzNo - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res0_dz_yes(&self) -> bool { - *self == Res0Dz::Res0DzYes - } -} -#[doc = "Field `RES0_DZ` writer - RES0 IEEE Divide by Zero Flag"] -pub type Res0DzW<'a, REG> = crate::BitWriter<'a, REG, Res0Dz>; -impl<'a, REG> Res0DzW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res0_dz_no(self) -> &'a mut crate::W { - self.variant(Res0Dz::Res0DzNo) - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res0_dz_yes(self) -> &'a mut crate::W { - self.variant(Res0Dz::Res0DzYes) - } -} -#[doc = "RES0 IEEE Invalid Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Nv { - #[doc = "0: There is usefully definable result."] - Res0NvNo = 0, - #[doc = "1: There is no usefully definable result."] - Res0NvYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Nv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_NV` reader - RES0 IEEE Invalid Flag"] -pub type Res0NvR = crate::BitReader; -impl Res0NvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Nv { - match self.bits { - false => Res0Nv::Res0NvNo, - true => Res0Nv::Res0NvYes, - } - } - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn is_res0_nv_no(&self) -> bool { - *self == Res0Nv::Res0NvNo - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn is_res0_nv_yes(&self) -> bool { - *self == Res0Nv::Res0NvYes - } -} -#[doc = "Field `RES0_NV` writer - RES0 IEEE Invalid Flag"] -pub type Res0NvW<'a, REG> = crate::BitWriter<'a, REG, Res0Nv>; -impl<'a, REG> Res0NvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn res0_nv_no(self) -> &'a mut crate::W { - self.variant(Res0Nv::Res0NvNo) - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn res0_nv_yes(self) -> &'a mut crate::W { - self.variant(Res0Nv::Res0NvYes) - } -} -#[doc = "RES0 Indirect Operation Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Err { - #[doc = "0: No invalid indirect operation is detected."] - Res0ErrNo = 0, - #[doc = "1: An invalid indirect operation error is detected."] - Res0ErrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_ERR` reader - RES0 Indirect Operation Error Flag"] -pub type Res0ErrR = crate::BitReader; -impl Res0ErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Err { - match self.bits { - false => Res0Err::Res0ErrNo, - true => Res0Err::Res0ErrYes, - } - } - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn is_res0_err_no(&self) -> bool { - *self == Res0Err::Res0ErrNo - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn is_res0_err_yes(&self) -> bool { - *self == Res0Err::Res0ErrYes - } -} -#[doc = "Field `RES0_ERR` writer - RES0 Indirect Operation Error Flag"] -pub type Res0ErrW<'a, REG> = crate::BitWriter<'a, REG, Res0Err>; -impl<'a, REG> Res0ErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn res0_err_no(self) -> &'a mut crate::W { - self.variant(Res0Err::Res0ErrNo) - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn res0_err_yes(self) -> &'a mut crate::W { - self.variant(Res0Err::Res0ErrYes) - } -} -#[doc = "RES0 Overwrite Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Ovwr { - #[doc = "0: The value of RES0 has been read."] - Res0OvwrNo = 0, - #[doc = "1: The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result."] - Res0OvwrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Ovwr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_OVWR` reader - RES0 Overwrite Flag"] -pub type Res0OvwrR = crate::BitReader; -impl Res0OvwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Ovwr { - match self.bits { - false => Res0Ovwr::Res0OvwrNo, - true => Res0Ovwr::Res0OvwrYes, - } - } - #[doc = "The value of RES0 has been read."] - #[inline(always)] - pub fn is_res0_ovwr_no(&self) -> bool { - *self == Res0Ovwr::Res0OvwrNo - } - #[doc = "The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn is_res0_ovwr_yes(&self) -> bool { - *self == Res0Ovwr::Res0OvwrYes - } -} -#[doc = "Field `RES0_OVWR` writer - RES0 Overwrite Flag"] -pub type Res0OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res0Ovwr>; -impl<'a, REG> Res0OvwrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The value of RES0 has been read."] - #[inline(always)] - pub fn res0_ovwr_no(self) -> &'a mut crate::W { - self.variant(Res0Ovwr::Res0OvwrNo) - } - #[doc = "The value of RES0 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn res0_ovwr_yes(self) -> &'a mut crate::W { - self.variant(Res0Ovwr::Res0OvwrYes) - } -} -#[doc = "RES0 Full Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Full { - #[doc = "0: RES0 has not updated and cannot be read."] - Res0FullNo = 0, - #[doc = "1: RES0 has updated and can be read."] - Res0FullYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_FULL` reader - RES0 Full Flag"] -pub type Res0FullR = crate::BitReader; -impl Res0FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Full { - match self.bits { - false => Res0Full::Res0FullNo, - true => Res0Full::Res0FullYes, - } - } - #[doc = "RES0 has not updated and cannot be read."] - #[inline(always)] - pub fn is_res0_full_no(&self) -> bool { - *self == Res0Full::Res0FullNo - } - #[doc = "RES0 has updated and can be read."] - #[inline(always)] - pub fn is_res0_full_yes(&self) -> bool { - *self == Res0Full::Res0FullYes - } -} -#[doc = "Field `RES0_FULL` writer - RES0 Full Flag"] -pub type Res0FullW<'a, REG> = crate::BitWriter<'a, REG, Res0Full>; -impl<'a, REG> Res0FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "RES0 has not updated and cannot be read."] - #[inline(always)] - pub fn res0_full_no(self) -> &'a mut crate::W { - self.variant(Res0Full::Res0FullNo) - } - #[doc = "RES0 has updated and can be read."] - #[inline(always)] - pub fn res0_full_yes(self) -> &'a mut crate::W { - self.variant(Res0Full::Res0FullYes) - } -} -#[doc = "RES1 IEEE Inexact Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Nx { - #[doc = "0: The result is not rounded."] - Res1NxNo = 0, - #[doc = "1: The result is rounded, and as a result some digits lost."] - Res1NxYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Nx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_NX` reader - RES1 IEEE Inexact Flag"] -pub type Res1NxR = crate::BitReader; -impl Res1NxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Nx { - match self.bits { - false => Res1Nx::Res1NxNo, - true => Res1Nx::Res1NxYes, - } - } - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn is_res1_nx_no(&self) -> bool { - *self == Res1Nx::Res1NxNo - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn is_res1_nx_yes(&self) -> bool { - *self == Res1Nx::Res1NxYes - } -} -#[doc = "Field `RES1_NX` writer - RES1 IEEE Inexact Flag"] -pub type Res1NxW<'a, REG> = crate::BitWriter<'a, REG, Res1Nx>; -impl<'a, REG> Res1NxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn res1_nx_no(self) -> &'a mut crate::W { - self.variant(Res1Nx::Res1NxNo) - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn res1_nx_yes(self) -> &'a mut crate::W { - self.variant(Res1Nx::Res1NxYes) - } -} -#[doc = "RES1 IEEE Underflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Uf { - #[doc = "0: No tiny non-zero result is detected."] - Res1UfNo = 0, - #[doc = "1: A tiny non-zero result is detected."] - Res1UfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Uf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_UF` reader - RES1 IEEE Underflow Flag"] -pub type Res1UfR = crate::BitReader; -impl Res1UfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Uf { - match self.bits { - false => Res1Uf::Res1UfNo, - true => Res1Uf::Res1UfYes, - } - } - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res1_uf_no(&self) -> bool { - *self == Res1Uf::Res1UfNo - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res1_uf_yes(&self) -> bool { - *self == Res1Uf::Res1UfYes - } -} -#[doc = "Field `RES1_UF` writer - RES1 IEEE Underflow Flag"] -pub type Res1UfW<'a, REG> = crate::BitWriter<'a, REG, Res1Uf>; -impl<'a, REG> Res1UfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn res1_uf_no(self) -> &'a mut crate::W { - self.variant(Res1Uf::Res1UfNo) - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn res1_uf_yes(self) -> &'a mut crate::W { - self.variant(Res1Uf::Res1UfYes) - } -} -#[doc = "RES1 IEEE Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Of { - #[doc = "0: The result format's largest finite number is not exceeded."] - Res1OfNo = 0, - #[doc = "1: The result format's largest finite number is exceeded."] - Res1OfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Of) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_OF` reader - RES1 IEEE Overflow Flag"] -pub type Res1OfR = crate::BitReader; -impl Res1OfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Of { - match self.bits { - false => Res1Of::Res1OfNo, - true => Res1Of::Res1OfYes, - } - } - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn is_res1_of_no(&self) -> bool { - *self == Res1Of::Res1OfNo - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn is_res1_of_yes(&self) -> bool { - *self == Res1Of::Res1OfYes - } -} -#[doc = "Field `RES1_OF` writer - RES1 IEEE Overflow Flag"] -pub type Res1OfW<'a, REG> = crate::BitWriter<'a, REG, Res1Of>; -impl<'a, REG> Res1OfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn res1_of_no(self) -> &'a mut crate::W { - self.variant(Res1Of::Res1OfNo) - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn res1_of_yes(self) -> &'a mut crate::W { - self.variant(Res1Of::Res1OfYes) - } -} -#[doc = "RES1 IEEE Divide by Zero Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Dz { - #[doc = "0: No exact infinite result is defined for an operation on finite operands."] - Res1DzNo = 0, - #[doc = "1: An exact infinite result is defined for an operation on finite operands."] - Res1DzYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Dz) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_DZ` reader - RES1 IEEE Divide by Zero Flag"] -pub type Res1DzR = crate::BitReader; -impl Res1DzR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Dz { - match self.bits { - false => Res1Dz::Res1DzNo, - true => Res1Dz::Res1DzYes, - } - } - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res1_dz_no(&self) -> bool { - *self == Res1Dz::Res1DzNo - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res1_dz_yes(&self) -> bool { - *self == Res1Dz::Res1DzYes - } -} -#[doc = "Field `RES1_DZ` writer - RES1 IEEE Divide by Zero Flag"] -pub type Res1DzW<'a, REG> = crate::BitWriter<'a, REG, Res1Dz>; -impl<'a, REG> Res1DzW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res1_dz_no(self) -> &'a mut crate::W { - self.variant(Res1Dz::Res1DzNo) - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res1_dz_yes(self) -> &'a mut crate::W { - self.variant(Res1Dz::Res1DzYes) - } -} -#[doc = "RES1 IEEE Invalid Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Nv { - #[doc = "0: There is usefully definable result."] - Res1NvNo = 0, - #[doc = "1: There is no usefully definable result."] - Res1NvYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Nv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_NV` reader - RES1 IEEE Invalid Flag"] -pub type Res1NvR = crate::BitReader; -impl Res1NvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Nv { - match self.bits { - false => Res1Nv::Res1NvNo, - true => Res1Nv::Res1NvYes, - } - } - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn is_res1_nv_no(&self) -> bool { - *self == Res1Nv::Res1NvNo - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn is_res1_nv_yes(&self) -> bool { - *self == Res1Nv::Res1NvYes - } -} -#[doc = "Field `RES1_NV` writer - RES1 IEEE Invalid Flag"] -pub type Res1NvW<'a, REG> = crate::BitWriter<'a, REG, Res1Nv>; -impl<'a, REG> Res1NvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn res1_nv_no(self) -> &'a mut crate::W { - self.variant(Res1Nv::Res1NvNo) - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn res1_nv_yes(self) -> &'a mut crate::W { - self.variant(Res1Nv::Res1NvYes) - } -} -#[doc = "RES1 Indirect Operation Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Err { - #[doc = "0: No invalid indirect operation is detected."] - Res1ErrNo = 0, - #[doc = "1: An invalid indirect operation error is detected."] - Res1ErrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_ERR` reader - RES1 Indirect Operation Error Flag"] -pub type Res1ErrR = crate::BitReader; -impl Res1ErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Err { - match self.bits { - false => Res1Err::Res1ErrNo, - true => Res1Err::Res1ErrYes, - } - } - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn is_res1_err_no(&self) -> bool { - *self == Res1Err::Res1ErrNo - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn is_res1_err_yes(&self) -> bool { - *self == Res1Err::Res1ErrYes - } -} -#[doc = "Field `RES1_ERR` writer - RES1 Indirect Operation Error Flag"] -pub type Res1ErrW<'a, REG> = crate::BitWriter<'a, REG, Res1Err>; -impl<'a, REG> Res1ErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn res1_err_no(self) -> &'a mut crate::W { - self.variant(Res1Err::Res1ErrNo) - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn res1_err_yes(self) -> &'a mut crate::W { - self.variant(Res1Err::Res1ErrYes) - } -} -#[doc = "RES1 Overwrite Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Ovwr { - #[doc = "0: The value of RES1 has been read."] - Res1OvwrNo = 0, - #[doc = "1: The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result."] - Res1OvwrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Ovwr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_OVWR` reader - RES1 Overwrite Flag"] -pub type Res1OvwrR = crate::BitReader; -impl Res1OvwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Ovwr { - match self.bits { - false => Res1Ovwr::Res1OvwrNo, - true => Res1Ovwr::Res1OvwrYes, - } - } - #[doc = "The value of RES1 has been read."] - #[inline(always)] - pub fn is_res1_ovwr_no(&self) -> bool { - *self == Res1Ovwr::Res1OvwrNo - } - #[doc = "The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn is_res1_ovwr_yes(&self) -> bool { - *self == Res1Ovwr::Res1OvwrYes - } -} -#[doc = "Field `RES1_OVWR` writer - RES1 Overwrite Flag"] -pub type Res1OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res1Ovwr>; -impl<'a, REG> Res1OvwrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The value of RES1 has been read."] - #[inline(always)] - pub fn res1_ovwr_no(self) -> &'a mut crate::W { - self.variant(Res1Ovwr::Res1OvwrNo) - } - #[doc = "The value of RES1 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn res1_ovwr_yes(self) -> &'a mut crate::W { - self.variant(Res1Ovwr::Res1OvwrYes) - } -} -#[doc = "RES1 Full Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Full { - #[doc = "0: RES1 has not updated and cannot be read."] - Res1FullNo = 0, - #[doc = "1: RES1 has updated and can be read."] - Res1FullYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_FULL` reader - RES1 Full Flag"] -pub type Res1FullR = crate::BitReader; -impl Res1FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Full { - match self.bits { - false => Res1Full::Res1FullNo, - true => Res1Full::Res1FullYes, - } - } - #[doc = "RES1 has not updated and cannot be read."] - #[inline(always)] - pub fn is_res1_full_no(&self) -> bool { - *self == Res1Full::Res1FullNo - } - #[doc = "RES1 has updated and can be read."] - #[inline(always)] - pub fn is_res1_full_yes(&self) -> bool { - *self == Res1Full::Res1FullYes - } -} -#[doc = "Field `RES1_FULL` writer - RES1 Full Flag"] -pub type Res1FullW<'a, REG> = crate::BitWriter<'a, REG, Res1Full>; -impl<'a, REG> Res1FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "RES1 has not updated and cannot be read."] - #[inline(always)] - pub fn res1_full_no(self) -> &'a mut crate::W { - self.variant(Res1Full::Res1FullNo) - } - #[doc = "RES1 has updated and can be read."] - #[inline(always)] - pub fn res1_full_yes(self) -> &'a mut crate::W { - self.variant(Res1Full::Res1FullYes) - } -} -#[doc = "RES2 IEEE Inexact Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Nx { - #[doc = "0: The result is not rounded."] - Res2NxNo = 0, - #[doc = "1: The result is rounded, and as a result some digits lost."] - Res2NxYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Nx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_NX` reader - RES2 IEEE Inexact Flag"] -pub type Res2NxR = crate::BitReader; -impl Res2NxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Nx { - match self.bits { - false => Res2Nx::Res2NxNo, - true => Res2Nx::Res2NxYes, - } - } - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn is_res2_nx_no(&self) -> bool { - *self == Res2Nx::Res2NxNo - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn is_res2_nx_yes(&self) -> bool { - *self == Res2Nx::Res2NxYes - } -} -#[doc = "Field `RES2_NX` writer - RES2 IEEE Inexact Flag"] -pub type Res2NxW<'a, REG> = crate::BitWriter<'a, REG, Res2Nx>; -impl<'a, REG> Res2NxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn res2_nx_no(self) -> &'a mut crate::W { - self.variant(Res2Nx::Res2NxNo) - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn res2_nx_yes(self) -> &'a mut crate::W { - self.variant(Res2Nx::Res2NxYes) - } -} -#[doc = "RES2 IEEE Underflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Uf { - #[doc = "0: No tiny non-zero result is detected."] - Res2UfNo = 0, - #[doc = "1: A tiny non-zero result is detected."] - Res2UfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Uf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_UF` reader - RES2 IEEE Underflow Flag"] -pub type Res2UfR = crate::BitReader; -impl Res2UfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Uf { - match self.bits { - false => Res2Uf::Res2UfNo, - true => Res2Uf::Res2UfYes, - } - } - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res2_uf_no(&self) -> bool { - *self == Res2Uf::Res2UfNo - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res2_uf_yes(&self) -> bool { - *self == Res2Uf::Res2UfYes - } -} -#[doc = "Field `RES2_UF` writer - RES2 IEEE Underflow Flag"] -pub type Res2UfW<'a, REG> = crate::BitWriter<'a, REG, Res2Uf>; -impl<'a, REG> Res2UfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn res2_uf_no(self) -> &'a mut crate::W { - self.variant(Res2Uf::Res2UfNo) - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn res2_uf_yes(self) -> &'a mut crate::W { - self.variant(Res2Uf::Res2UfYes) - } -} -#[doc = "RES2 IEEE Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Of { - #[doc = "0: The result format's largest finite number is not exceeded."] - Res2OfNo = 0, - #[doc = "1: The result format's largest finite number is exceeded."] - Res2OfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Of) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_OF` reader - RES2 IEEE Overflow Flag"] -pub type Res2OfR = crate::BitReader; -impl Res2OfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Of { - match self.bits { - false => Res2Of::Res2OfNo, - true => Res2Of::Res2OfYes, - } - } - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn is_res2_of_no(&self) -> bool { - *self == Res2Of::Res2OfNo - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn is_res2_of_yes(&self) -> bool { - *self == Res2Of::Res2OfYes - } -} -#[doc = "Field `RES2_OF` writer - RES2 IEEE Overflow Flag"] -pub type Res2OfW<'a, REG> = crate::BitWriter<'a, REG, Res2Of>; -impl<'a, REG> Res2OfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn res2_of_no(self) -> &'a mut crate::W { - self.variant(Res2Of::Res2OfNo) - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn res2_of_yes(self) -> &'a mut crate::W { - self.variant(Res2Of::Res2OfYes) - } -} -#[doc = "RES2 IEEE Divide by Zero Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Dz { - #[doc = "0: No exact infinite result is defined for an operation on finite operands."] - Res2DzNo = 0, - #[doc = "1: An exact infinite result is defined for an operation on finite operands."] - Res2DzYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Dz) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_DZ` reader - RES2 IEEE Divide by Zero Flag"] -pub type Res2DzR = crate::BitReader; -impl Res2DzR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Dz { - match self.bits { - false => Res2Dz::Res2DzNo, - true => Res2Dz::Res2DzYes, - } - } - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res2_dz_no(&self) -> bool { - *self == Res2Dz::Res2DzNo - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res2_dz_yes(&self) -> bool { - *self == Res2Dz::Res2DzYes - } -} -#[doc = "Field `RES2_DZ` writer - RES2 IEEE Divide by Zero Flag"] -pub type Res2DzW<'a, REG> = crate::BitWriter<'a, REG, Res2Dz>; -impl<'a, REG> Res2DzW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res2_dz_no(self) -> &'a mut crate::W { - self.variant(Res2Dz::Res2DzNo) - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res2_dz_yes(self) -> &'a mut crate::W { - self.variant(Res2Dz::Res2DzYes) - } -} -#[doc = "RES2 IEEE Invalid Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Nv { - #[doc = "0: There is usefully definable result."] - Res2NvNo = 0, - #[doc = "1: There is no usefully definable result."] - Res2NvYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Nv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_NV` reader - RES2 IEEE Invalid Flag"] -pub type Res2NvR = crate::BitReader; -impl Res2NvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Nv { - match self.bits { - false => Res2Nv::Res2NvNo, - true => Res2Nv::Res2NvYes, - } - } - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn is_res2_nv_no(&self) -> bool { - *self == Res2Nv::Res2NvNo - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn is_res2_nv_yes(&self) -> bool { - *self == Res2Nv::Res2NvYes - } -} -#[doc = "Field `RES2_NV` writer - RES2 IEEE Invalid Flag"] -pub type Res2NvW<'a, REG> = crate::BitWriter<'a, REG, Res2Nv>; -impl<'a, REG> Res2NvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn res2_nv_no(self) -> &'a mut crate::W { - self.variant(Res2Nv::Res2NvNo) - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn res2_nv_yes(self) -> &'a mut crate::W { - self.variant(Res2Nv::Res2NvYes) - } -} -#[doc = "RES2 Indirect Operation Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Err { - #[doc = "0: No invalid indirect operation is detected."] - Res2ErrNo = 0, - #[doc = "1: An invalid indirect operation error is detected."] - Res2ErrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_ERR` reader - RES2 Indirect Operation Error Flag"] -pub type Res2ErrR = crate::BitReader; -impl Res2ErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Err { - match self.bits { - false => Res2Err::Res2ErrNo, - true => Res2Err::Res2ErrYes, - } - } - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn is_res2_err_no(&self) -> bool { - *self == Res2Err::Res2ErrNo - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn is_res2_err_yes(&self) -> bool { - *self == Res2Err::Res2ErrYes - } -} -#[doc = "Field `RES2_ERR` writer - RES2 Indirect Operation Error Flag"] -pub type Res2ErrW<'a, REG> = crate::BitWriter<'a, REG, Res2Err>; -impl<'a, REG> Res2ErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn res2_err_no(self) -> &'a mut crate::W { - self.variant(Res2Err::Res2ErrNo) - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn res2_err_yes(self) -> &'a mut crate::W { - self.variant(Res2Err::Res2ErrYes) - } -} -#[doc = "RES2 Overwrite Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Ovwr { - #[doc = "0: The value of RES2 has been read."] - Res2OvwrNo = 0, - #[doc = "1: The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result."] - Res2OvwrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Ovwr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_OVWR` reader - RES2 Overwrite Flag"] -pub type Res2OvwrR = crate::BitReader; -impl Res2OvwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Ovwr { - match self.bits { - false => Res2Ovwr::Res2OvwrNo, - true => Res2Ovwr::Res2OvwrYes, - } - } - #[doc = "The value of RES2 has been read."] - #[inline(always)] - pub fn is_res2_ovwr_no(&self) -> bool { - *self == Res2Ovwr::Res2OvwrNo - } - #[doc = "The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn is_res2_ovwr_yes(&self) -> bool { - *self == Res2Ovwr::Res2OvwrYes - } -} -#[doc = "Field `RES2_OVWR` writer - RES2 Overwrite Flag"] -pub type Res2OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res2Ovwr>; -impl<'a, REG> Res2OvwrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The value of RES2 has been read."] - #[inline(always)] - pub fn res2_ovwr_no(self) -> &'a mut crate::W { - self.variant(Res2Ovwr::Res2OvwrNo) - } - #[doc = "The value of RES2 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn res2_ovwr_yes(self) -> &'a mut crate::W { - self.variant(Res2Ovwr::Res2OvwrYes) - } -} -#[doc = "RES2 Full Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Full { - #[doc = "0: RES2 has not updated and cannot be read."] - Res2FullNo = 0, - #[doc = "1: RES2 has updated and can be read."] - Res2FullYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_FULL` reader - RES2 Full Flag"] -pub type Res2FullR = crate::BitReader; -impl Res2FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Full { - match self.bits { - false => Res2Full::Res2FullNo, - true => Res2Full::Res2FullYes, - } - } - #[doc = "RES2 has not updated and cannot be read."] - #[inline(always)] - pub fn is_res2_full_no(&self) -> bool { - *self == Res2Full::Res2FullNo - } - #[doc = "RES2 has updated and can be read."] - #[inline(always)] - pub fn is_res2_full_yes(&self) -> bool { - *self == Res2Full::Res2FullYes - } -} -#[doc = "Field `RES2_FULL` writer - RES2 Full Flag"] -pub type Res2FullW<'a, REG> = crate::BitWriter<'a, REG, Res2Full>; -impl<'a, REG> Res2FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "RES2 has not updated and cannot be read."] - #[inline(always)] - pub fn res2_full_no(self) -> &'a mut crate::W { - self.variant(Res2Full::Res2FullNo) - } - #[doc = "RES2 has updated and can be read."] - #[inline(always)] - pub fn res2_full_yes(self) -> &'a mut crate::W { - self.variant(Res2Full::Res2FullYes) - } -} -#[doc = "RES3 IEEE Inexact Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Nx { - #[doc = "0: The result is not rounded."] - Res3NxNo = 0, - #[doc = "1: The result is rounded, and as a result some digits lost."] - Res3NxYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Nx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_NX` reader - RES3 IEEE Inexact Flag"] -pub type Res3NxR = crate::BitReader; -impl Res3NxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Nx { - match self.bits { - false => Res3Nx::Res3NxNo, - true => Res3Nx::Res3NxYes, - } - } - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn is_res3_nx_no(&self) -> bool { - *self == Res3Nx::Res3NxNo - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn is_res3_nx_yes(&self) -> bool { - *self == Res3Nx::Res3NxYes - } -} -#[doc = "Field `RES3_NX` writer - RES3 IEEE Inexact Flag"] -pub type Res3NxW<'a, REG> = crate::BitWriter<'a, REG, Res3Nx>; -impl<'a, REG> Res3NxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result is not rounded."] - #[inline(always)] - pub fn res3_nx_no(self) -> &'a mut crate::W { - self.variant(Res3Nx::Res3NxNo) - } - #[doc = "The result is rounded, and as a result some digits lost."] - #[inline(always)] - pub fn res3_nx_yes(self) -> &'a mut crate::W { - self.variant(Res3Nx::Res3NxYes) - } -} -#[doc = "RES3 IEEE Underflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Uf { - #[doc = "0: No tiny non-zero result is detected."] - Res3UfNo = 0, - #[doc = "1: A tiny non-zero result is detected."] - Res3UfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Uf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_UF` reader - RES3 IEEE Underflow Flag"] -pub type Res3UfR = crate::BitReader; -impl Res3UfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Uf { - match self.bits { - false => Res3Uf::Res3UfNo, - true => Res3Uf::Res3UfYes, - } - } - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res3_uf_no(&self) -> bool { - *self == Res3Uf::Res3UfNo - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn is_res3_uf_yes(&self) -> bool { - *self == Res3Uf::Res3UfYes - } -} -#[doc = "Field `RES3_UF` writer - RES3 IEEE Underflow Flag"] -pub type Res3UfW<'a, REG> = crate::BitWriter<'a, REG, Res3Uf>; -impl<'a, REG> Res3UfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No tiny non-zero result is detected."] - #[inline(always)] - pub fn res3_uf_no(self) -> &'a mut crate::W { - self.variant(Res3Uf::Res3UfNo) - } - #[doc = "A tiny non-zero result is detected."] - #[inline(always)] - pub fn res3_uf_yes(self) -> &'a mut crate::W { - self.variant(Res3Uf::Res3UfYes) - } -} -#[doc = "RES3 IEEE Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Of { - #[doc = "0: The result format's largest finite number is not exceeded."] - Res3OfNo = 0, - #[doc = "1: The result format's largest finite number is exceeded."] - Res3OfYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Of) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_OF` reader - RES3 IEEE Overflow Flag"] -pub type Res3OfR = crate::BitReader; -impl Res3OfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Of { - match self.bits { - false => Res3Of::Res3OfNo, - true => Res3Of::Res3OfYes, - } - } - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn is_res3_of_no(&self) -> bool { - *self == Res3Of::Res3OfNo - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn is_res3_of_yes(&self) -> bool { - *self == Res3Of::Res3OfYes - } -} -#[doc = "Field `RES3_OF` writer - RES3 IEEE Overflow Flag"] -pub type Res3OfW<'a, REG> = crate::BitWriter<'a, REG, Res3Of>; -impl<'a, REG> Res3OfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The result format's largest finite number is not exceeded."] - #[inline(always)] - pub fn res3_of_no(self) -> &'a mut crate::W { - self.variant(Res3Of::Res3OfNo) - } - #[doc = "The result format's largest finite number is exceeded."] - #[inline(always)] - pub fn res3_of_yes(self) -> &'a mut crate::W { - self.variant(Res3Of::Res3OfYes) - } -} -#[doc = "RES3 IEEE Divide by Zero Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Dz { - #[doc = "0: No exact infinite result is defined for an operation on finite operands."] - Res3DzNo = 0, - #[doc = "1: An exact infinite result is defined for an operation on finite operands."] - Res3DzYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Dz) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_DZ` reader - RES3 IEEE Divide by Zero Flag"] -pub type Res3DzR = crate::BitReader; -impl Res3DzR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Dz { - match self.bits { - false => Res3Dz::Res3DzNo, - true => Res3Dz::Res3DzYes, - } - } - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res3_dz_no(&self) -> bool { - *self == Res3Dz::Res3DzNo - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn is_res3_dz_yes(&self) -> bool { - *self == Res3Dz::Res3DzYes - } -} -#[doc = "Field `RES3_DZ` writer - RES3 IEEE Divide by Zero Flag"] -pub type Res3DzW<'a, REG> = crate::BitWriter<'a, REG, Res3Dz>; -impl<'a, REG> Res3DzW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res3_dz_no(self) -> &'a mut crate::W { - self.variant(Res3Dz::Res3DzNo) - } - #[doc = "An exact infinite result is defined for an operation on finite operands."] - #[inline(always)] - pub fn res3_dz_yes(self) -> &'a mut crate::W { - self.variant(Res3Dz::Res3DzYes) - } -} -#[doc = "RES3 IEEE Invalid Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Nv { - #[doc = "0: There is usefully definable result."] - Res3NvNo = 0, - #[doc = "1: There is no usefully definable result."] - Res3NvYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Nv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_NV` reader - RES3 IEEE Invalid Flag"] -pub type Res3NvR = crate::BitReader; -impl Res3NvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Nv { - match self.bits { - false => Res3Nv::Res3NvNo, - true => Res3Nv::Res3NvYes, - } - } - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn is_res3_nv_no(&self) -> bool { - *self == Res3Nv::Res3NvNo - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn is_res3_nv_yes(&self) -> bool { - *self == Res3Nv::Res3NvYes - } -} -#[doc = "Field `RES3_NV` writer - RES3 IEEE Invalid Flag"] -pub type Res3NvW<'a, REG> = crate::BitWriter<'a, REG, Res3Nv>; -impl<'a, REG> Res3NvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "There is usefully definable result."] - #[inline(always)] - pub fn res3_nv_no(self) -> &'a mut crate::W { - self.variant(Res3Nv::Res3NvNo) - } - #[doc = "There is no usefully definable result."] - #[inline(always)] - pub fn res3_nv_yes(self) -> &'a mut crate::W { - self.variant(Res3Nv::Res3NvYes) - } -} -#[doc = "RES3 Indirect Operation Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Err { - #[doc = "0: No invalid indirect operation is detected."] - Res3ErrNo = 0, - #[doc = "1: An invalid indirect operation error is detected."] - Res3ErrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_ERR` reader - RES3 Indirect Operation Error Flag"] -pub type Res3ErrR = crate::BitReader; -impl Res3ErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Err { - match self.bits { - false => Res3Err::Res3ErrNo, - true => Res3Err::Res3ErrYes, - } - } - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn is_res3_err_no(&self) -> bool { - *self == Res3Err::Res3ErrNo - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn is_res3_err_yes(&self) -> bool { - *self == Res3Err::Res3ErrYes - } -} -#[doc = "Field `RES3_ERR` writer - RES3 Indirect Operation Error Flag"] -pub type Res3ErrW<'a, REG> = crate::BitWriter<'a, REG, Res3Err>; -impl<'a, REG> Res3ErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No invalid indirect operation is detected."] - #[inline(always)] - pub fn res3_err_no(self) -> &'a mut crate::W { - self.variant(Res3Err::Res3ErrNo) - } - #[doc = "An invalid indirect operation error is detected."] - #[inline(always)] - pub fn res3_err_yes(self) -> &'a mut crate::W { - self.variant(Res3Err::Res3ErrYes) - } -} -#[doc = "RES3 Overwrite Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Ovwr { - #[doc = "0: The value of RES3 has been read."] - Res3OvwrNo = 0, - #[doc = "1: The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result."] - Res3OvwrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Ovwr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_OVWR` reader - RES3 Overwrite Flag"] -pub type Res3OvwrR = crate::BitReader; -impl Res3OvwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Ovwr { - match self.bits { - false => Res3Ovwr::Res3OvwrNo, - true => Res3Ovwr::Res3OvwrYes, - } - } - #[doc = "The value of RES3 has been read."] - #[inline(always)] - pub fn is_res3_ovwr_no(&self) -> bool { - *self == Res3Ovwr::Res3OvwrNo - } - #[doc = "The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn is_res3_ovwr_yes(&self) -> bool { - *self == Res3Ovwr::Res3OvwrYes - } -} -#[doc = "Field `RES3_OVWR` writer - RES3 Overwrite Flag"] -pub type Res3OvwrW<'a, REG> = crate::BitWriter<'a, REG, Res3Ovwr>; -impl<'a, REG> Res3OvwrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The value of RES3 has been read."] - #[inline(always)] - pub fn res3_ovwr_no(self) -> &'a mut crate::W { - self.variant(Res3Ovwr::Res3OvwrNo) - } - #[doc = "The value of RES3 has not been read yet and is overwritten by a new MAUWRAP result."] - #[inline(always)] - pub fn res3_ovwr_yes(self) -> &'a mut crate::W { - self.variant(Res3Ovwr::Res3OvwrYes) - } -} -#[doc = "RES3 Full Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Full { - #[doc = "0: RES3 has not updated and cannot be read."] - Res3FullNo = 0, - #[doc = "1: RES3 has updated and can be read."] - Res3FullYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Full) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_FULL` reader - RES3 Full Flag"] -pub type Res3FullR = crate::BitReader; -impl Res3FullR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Full { - match self.bits { - false => Res3Full::Res3FullNo, - true => Res3Full::Res3FullYes, - } - } - #[doc = "RES3 has not updated and cannot be read."] - #[inline(always)] - pub fn is_res3_full_no(&self) -> bool { - *self == Res3Full::Res3FullNo - } - #[doc = "RES3 has updated and can be read."] - #[inline(always)] - pub fn is_res3_full_yes(&self) -> bool { - *self == Res3Full::Res3FullYes - } -} -#[doc = "Field `RES3_FULL` writer - RES3 Full Flag"] -pub type Res3FullW<'a, REG> = crate::BitWriter<'a, REG, Res3Full>; -impl<'a, REG> Res3FullW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "RES3 has not updated and cannot be read."] - #[inline(always)] - pub fn res3_full_no(self) -> &'a mut crate::W { - self.variant(Res3Full::Res3FullNo) - } - #[doc = "RES3 has updated and can be read."] - #[inline(always)] - pub fn res3_full_yes(self) -> &'a mut crate::W { - self.variant(Res3Full::Res3FullYes) - } -} -impl R { - #[doc = "Bit 0 - RES0 IEEE Inexact Flag"] - #[inline(always)] - pub fn res0_nx(&self) -> Res0NxR { - Res0NxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - RES0 IEEE Underflow Flag"] - #[inline(always)] - pub fn res0_uf(&self) -> Res0UfR { - Res0UfR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - RES0 IEEE Overflow Flag"] - #[inline(always)] - pub fn res0_of(&self) -> Res0OfR { - Res0OfR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - RES0 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res0_dz(&self) -> Res0DzR { - Res0DzR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - RES0 IEEE Invalid Flag"] - #[inline(always)] - pub fn res0_nv(&self) -> Res0NvR { - Res0NvR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - RES0 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res0_err(&self) -> Res0ErrR { - Res0ErrR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - RES0 Overwrite Flag"] - #[inline(always)] - pub fn res0_ovwr(&self) -> Res0OvwrR { - Res0OvwrR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - RES0 Full Flag"] - #[inline(always)] - pub fn res0_full(&self) -> Res0FullR { - Res0FullR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - RES1 IEEE Inexact Flag"] - #[inline(always)] - pub fn res1_nx(&self) -> Res1NxR { - Res1NxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - RES1 IEEE Underflow Flag"] - #[inline(always)] - pub fn res1_uf(&self) -> Res1UfR { - Res1UfR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - RES1 IEEE Overflow Flag"] - #[inline(always)] - pub fn res1_of(&self) -> Res1OfR { - Res1OfR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - RES1 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res1_dz(&self) -> Res1DzR { - Res1DzR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - RES1 IEEE Invalid Flag"] - #[inline(always)] - pub fn res1_nv(&self) -> Res1NvR { - Res1NvR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - RES1 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res1_err(&self) -> Res1ErrR { - Res1ErrR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - RES1 Overwrite Flag"] - #[inline(always)] - pub fn res1_ovwr(&self) -> Res1OvwrR { - Res1OvwrR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - RES1 Full Flag"] - #[inline(always)] - pub fn res1_full(&self) -> Res1FullR { - Res1FullR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - RES2 IEEE Inexact Flag"] - #[inline(always)] - pub fn res2_nx(&self) -> Res2NxR { - Res2NxR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - RES2 IEEE Underflow Flag"] - #[inline(always)] - pub fn res2_uf(&self) -> Res2UfR { - Res2UfR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - RES2 IEEE Overflow Flag"] - #[inline(always)] - pub fn res2_of(&self) -> Res2OfR { - Res2OfR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - RES2 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res2_dz(&self) -> Res2DzR { - Res2DzR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - RES2 IEEE Invalid Flag"] - #[inline(always)] - pub fn res2_nv(&self) -> Res2NvR { - Res2NvR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - RES2 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res2_err(&self) -> Res2ErrR { - Res2ErrR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - RES2 Overwrite Flag"] - #[inline(always)] - pub fn res2_ovwr(&self) -> Res2OvwrR { - Res2OvwrR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - RES2 Full Flag"] - #[inline(always)] - pub fn res2_full(&self) -> Res2FullR { - Res2FullR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - RES3 IEEE Inexact Flag"] - #[inline(always)] - pub fn res3_nx(&self) -> Res3NxR { - Res3NxR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - RES3 IEEE Underflow Flag"] - #[inline(always)] - pub fn res3_uf(&self) -> Res3UfR { - Res3UfR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - RES3 IEEE Overflow Flag"] - #[inline(always)] - pub fn res3_of(&self) -> Res3OfR { - Res3OfR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - RES3 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res3_dz(&self) -> Res3DzR { - Res3DzR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - RES3 IEEE Invalid Flag"] - #[inline(always)] - pub fn res3_nv(&self) -> Res3NvR { - Res3NvR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - RES3 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res3_err(&self) -> Res3ErrR { - Res3ErrR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - RES3 Overwrite Flag"] - #[inline(always)] - pub fn res3_ovwr(&self) -> Res3OvwrR { - Res3OvwrR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - RES3 Full Flag"] - #[inline(always)] - pub fn res3_full(&self) -> Res3FullR { - Res3FullR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - RES0 IEEE Inexact Flag"] - #[inline(always)] - pub fn res0_nx(&mut self) -> Res0NxW { - Res0NxW::new(self, 0) - } - #[doc = "Bit 1 - RES0 IEEE Underflow Flag"] - #[inline(always)] - pub fn res0_uf(&mut self) -> Res0UfW { - Res0UfW::new(self, 1) - } - #[doc = "Bit 2 - RES0 IEEE Overflow Flag"] - #[inline(always)] - pub fn res0_of(&mut self) -> Res0OfW { - Res0OfW::new(self, 2) - } - #[doc = "Bit 3 - RES0 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res0_dz(&mut self) -> Res0DzW { - Res0DzW::new(self, 3) - } - #[doc = "Bit 4 - RES0 IEEE Invalid Flag"] - #[inline(always)] - pub fn res0_nv(&mut self) -> Res0NvW { - Res0NvW::new(self, 4) - } - #[doc = "Bit 5 - RES0 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res0_err(&mut self) -> Res0ErrW { - Res0ErrW::new(self, 5) - } - #[doc = "Bit 6 - RES0 Overwrite Flag"] - #[inline(always)] - pub fn res0_ovwr(&mut self) -> Res0OvwrW { - Res0OvwrW::new(self, 6) - } - #[doc = "Bit 7 - RES0 Full Flag"] - #[inline(always)] - pub fn res0_full(&mut self) -> Res0FullW { - Res0FullW::new(self, 7) - } - #[doc = "Bit 8 - RES1 IEEE Inexact Flag"] - #[inline(always)] - pub fn res1_nx(&mut self) -> Res1NxW { - Res1NxW::new(self, 8) - } - #[doc = "Bit 9 - RES1 IEEE Underflow Flag"] - #[inline(always)] - pub fn res1_uf(&mut self) -> Res1UfW { - Res1UfW::new(self, 9) - } - #[doc = "Bit 10 - RES1 IEEE Overflow Flag"] - #[inline(always)] - pub fn res1_of(&mut self) -> Res1OfW { - Res1OfW::new(self, 10) - } - #[doc = "Bit 11 - RES1 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res1_dz(&mut self) -> Res1DzW { - Res1DzW::new(self, 11) - } - #[doc = "Bit 12 - RES1 IEEE Invalid Flag"] - #[inline(always)] - pub fn res1_nv(&mut self) -> Res1NvW { - Res1NvW::new(self, 12) - } - #[doc = "Bit 13 - RES1 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res1_err(&mut self) -> Res1ErrW { - Res1ErrW::new(self, 13) - } - #[doc = "Bit 14 - RES1 Overwrite Flag"] - #[inline(always)] - pub fn res1_ovwr(&mut self) -> Res1OvwrW { - Res1OvwrW::new(self, 14) - } - #[doc = "Bit 15 - RES1 Full Flag"] - #[inline(always)] - pub fn res1_full(&mut self) -> Res1FullW { - Res1FullW::new(self, 15) - } - #[doc = "Bit 16 - RES2 IEEE Inexact Flag"] - #[inline(always)] - pub fn res2_nx(&mut self) -> Res2NxW { - Res2NxW::new(self, 16) - } - #[doc = "Bit 17 - RES2 IEEE Underflow Flag"] - #[inline(always)] - pub fn res2_uf(&mut self) -> Res2UfW { - Res2UfW::new(self, 17) - } - #[doc = "Bit 18 - RES2 IEEE Overflow Flag"] - #[inline(always)] - pub fn res2_of(&mut self) -> Res2OfW { - Res2OfW::new(self, 18) - } - #[doc = "Bit 19 - RES2 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res2_dz(&mut self) -> Res2DzW { - Res2DzW::new(self, 19) - } - #[doc = "Bit 20 - RES2 IEEE Invalid Flag"] - #[inline(always)] - pub fn res2_nv(&mut self) -> Res2NvW { - Res2NvW::new(self, 20) - } - #[doc = "Bit 21 - RES2 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res2_err(&mut self) -> Res2ErrW { - Res2ErrW::new(self, 21) - } - #[doc = "Bit 22 - RES2 Overwrite Flag"] - #[inline(always)] - pub fn res2_ovwr(&mut self) -> Res2OvwrW { - Res2OvwrW::new(self, 22) - } - #[doc = "Bit 23 - RES2 Full Flag"] - #[inline(always)] - pub fn res2_full(&mut self) -> Res2FullW { - Res2FullW::new(self, 23) - } - #[doc = "Bit 24 - RES3 IEEE Inexact Flag"] - #[inline(always)] - pub fn res3_nx(&mut self) -> Res3NxW { - Res3NxW::new(self, 24) - } - #[doc = "Bit 25 - RES3 IEEE Underflow Flag"] - #[inline(always)] - pub fn res3_uf(&mut self) -> Res3UfW { - Res3UfW::new(self, 25) - } - #[doc = "Bit 26 - RES3 IEEE Overflow Flag"] - #[inline(always)] - pub fn res3_of(&mut self) -> Res3OfW { - Res3OfW::new(self, 26) - } - #[doc = "Bit 27 - RES3 IEEE Divide by Zero Flag"] - #[inline(always)] - pub fn res3_dz(&mut self) -> Res3DzW { - Res3DzW::new(self, 27) - } - #[doc = "Bit 28 - RES3 IEEE Invalid Flag"] - #[inline(always)] - pub fn res3_nv(&mut self) -> Res3NvW { - Res3NvW::new(self, 28) - } - #[doc = "Bit 29 - RES3 Indirect Operation Error Flag"] - #[inline(always)] - pub fn res3_err(&mut self) -> Res3ErrW { - Res3ErrW::new(self, 29) - } - #[doc = "Bit 30 - RES3 Overwrite Flag"] - #[inline(always)] - pub fn res3_ovwr(&mut self) -> Res3OvwrW { - Res3OvwrW::new(self, 30) - } - #[doc = "Bit 31 - RES3 Full Flag"] - #[inline(always)] - pub fn res3_full(&mut self) -> Res3FullW { - Res3FullW::new(self, 31) - } -} -#[doc = "Result Status\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ResStatusSpec; -impl crate::RegisterSpec for ResStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`res_status::R`](R) reader structure"] -impl crate::Readable for ResStatusSpec {} -#[doc = "`write(|w| ..)` method takes [`res_status::W`](W) writer structure"] -impl crate::Writable for ResStatusSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RES_STATUS to value 0"] -impl crate::Resettable for ResStatusSpec {} diff --git a/mcxa276-pac/src/mau0/res_status_ie.rs b/mcxa276-pac/src/mau0/res_status_ie.rs deleted file mode 100644 index d05c45e0a..000000000 --- a/mcxa276-pac/src/mau0/res_status_ie.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `RES_STATUS_IE` reader"] -pub type R = crate::R; -#[doc = "Register `RES_STATUS_IE` writer"] -pub type W = crate::W; -#[doc = "RES0 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res0Ie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res0Ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES0_IE` reader - RES0 Interrupt Enable"] -pub type Res0IeR = crate::BitReader; -impl Res0IeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res0Ie { - match self.bits { - false => Res0Ie::Disable, - true => Res0Ie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Res0Ie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Res0Ie::Enable - } -} -#[doc = "Field `RES0_IE` writer - RES0 Interrupt Enable"] -pub type Res0IeW<'a, REG> = crate::BitWriter<'a, REG, Res0Ie>; -impl<'a, REG> Res0IeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Res0Ie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Res0Ie::Enable) - } -} -#[doc = "RES1 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res1Ie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res1Ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES1_IE` reader - RES1 Interrupt Enable"] -pub type Res1IeR = crate::BitReader; -impl Res1IeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res1Ie { - match self.bits { - false => Res1Ie::Disable, - true => Res1Ie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Res1Ie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Res1Ie::Enable - } -} -#[doc = "Field `RES1_IE` writer - RES1 Interrupt Enable"] -pub type Res1IeW<'a, REG> = crate::BitWriter<'a, REG, Res1Ie>; -impl<'a, REG> Res1IeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Res1Ie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Res1Ie::Enable) - } -} -#[doc = "RES2 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res2Ie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res2Ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES2_IE` reader - RES2 Interrupt Enable"] -pub type Res2IeR = crate::BitReader; -impl Res2IeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res2Ie { - match self.bits { - false => Res2Ie::Disable, - true => Res2Ie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Res2Ie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Res2Ie::Enable - } -} -#[doc = "Field `RES2_IE` writer - RES2 Interrupt Enable"] -pub type Res2IeW<'a, REG> = crate::BitWriter<'a, REG, Res2Ie>; -impl<'a, REG> Res2IeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Res2Ie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Res2Ie::Enable) - } -} -#[doc = "RES3 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Res3Ie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Res3Ie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RES3_IE` reader - RES3 Interrupt Enable"] -pub type Res3IeR = crate::BitReader; -impl Res3IeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Res3Ie { - match self.bits { - false => Res3Ie::Disable, - true => Res3Ie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Res3Ie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Res3Ie::Enable - } -} -#[doc = "Field `RES3_IE` writer - RES3 Interrupt Enable"] -pub type Res3IeW<'a, REG> = crate::BitWriter<'a, REG, Res3Ie>; -impl<'a, REG> Res3IeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Res3Ie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Res3Ie::Enable) - } -} -impl R { - #[doc = "Bit 0 - RES0 Interrupt Enable"] - #[inline(always)] - pub fn res0_ie(&self) -> Res0IeR { - Res0IeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - RES1 Interrupt Enable"] - #[inline(always)] - pub fn res1_ie(&self) -> Res1IeR { - Res1IeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - RES2 Interrupt Enable"] - #[inline(always)] - pub fn res2_ie(&self) -> Res2IeR { - Res2IeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - RES3 Interrupt Enable"] - #[inline(always)] - pub fn res3_ie(&self) -> Res3IeR { - Res3IeR::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - RES0 Interrupt Enable"] - #[inline(always)] - pub fn res0_ie(&mut self) -> Res0IeW { - Res0IeW::new(self, 0) - } - #[doc = "Bit 1 - RES1 Interrupt Enable"] - #[inline(always)] - pub fn res1_ie(&mut self) -> Res1IeW { - Res1IeW::new(self, 1) - } - #[doc = "Bit 2 - RES2 Interrupt Enable"] - #[inline(always)] - pub fn res2_ie(&mut self) -> Res2IeW { - Res2IeW::new(self, 2) - } - #[doc = "Bit 3 - RES3 Interrupt Enable"] - #[inline(always)] - pub fn res3_ie(&mut self) -> Res3IeW { - Res3IeW::new(self, 3) - } -} -#[doc = "Result Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`res_status_ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res_status_ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ResStatusIeSpec; -impl crate::RegisterSpec for ResStatusIeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`res_status_ie::R`](R) reader structure"] -impl crate::Readable for ResStatusIeSpec {} -#[doc = "`write(|w| ..)` method takes [`res_status_ie::W`](W) writer structure"] -impl crate::Writable for ResStatusIeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RES_STATUS_IE to value 0"] -impl crate::Resettable for ResStatusIeSpec {} diff --git a/mcxa276-pac/src/mau0/sys_ctlr.rs b/mcxa276-pac/src/mau0/sys_ctlr.rs deleted file mode 100644 index 55c969788..000000000 --- a/mcxa276-pac/src/mau0/sys_ctlr.rs +++ /dev/null @@ -1,86 +0,0 @@ -#[doc = "Register `SYS_CTLR` reader"] -pub type R = crate::R; -#[doc = "Register `SYS_CTLR` writer"] -pub type W = crate::W; -#[doc = "Automatic Clock Gating Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum AcgEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: AcgEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ACG_EN` reader - Automatic Clock Gating Enable"] -pub type AcgEnR = crate::BitReader; -impl AcgEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> AcgEn { - match self.bits { - false => AcgEn::Disable, - true => AcgEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == AcgEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == AcgEn::Enable - } -} -#[doc = "Field `ACG_EN` writer - Automatic Clock Gating Enable"] -pub type AcgEnW<'a, REG> = crate::BitWriter<'a, REG, AcgEn>; -impl<'a, REG> AcgEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(AcgEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(AcgEn::Enable) - } -} -impl R { - #[doc = "Bit 0 - Automatic Clock Gating Enable"] - #[inline(always)] - pub fn acg_en(&self) -> AcgEnR { - AcgEnR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Automatic Clock Gating Enable"] - #[inline(always)] - pub fn acg_en(&mut self) -> AcgEnW { - AcgEnW::new(self, 0) - } -} -#[doc = "System Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SysCtlrSpec; -impl crate::RegisterSpec for SysCtlrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sys_ctlr::R`](R) reader structure"] -impl crate::Readable for SysCtlrSpec {} -#[doc = "`write(|w| ..)` method takes [`sys_ctlr::W`](W) writer structure"] -impl crate::Writable for SysCtlrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SYS_CTLR to value 0x01"] -impl crate::Resettable for SysCtlrSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/mbc0.rs b/mcxa276-pac/src/mbc0.rs deleted file mode 100644 index 56b3c880b..000000000 --- a/mcxa276-pac/src/mbc0.rs +++ /dev/null @@ -1,350 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - mbc0_mem0_glbcfg: Mbc0Mem0Glbcfg, - mbc0_mem1_glbcfg: Mbc0Mem1Glbcfg, - mbc0_mem2_glbcfg: Mbc0Mem2Glbcfg, - mbc0_mem3_glbcfg: Mbc0Mem3Glbcfg, - _reserved4: [u8; 0x10], - mbc0_memn_glbac0: Mbc0MemnGlbac0, - mbc0_memn_glbac1: Mbc0MemnGlbac1, - mbc0_memn_glbac2: Mbc0MemnGlbac2, - mbc0_memn_glbac3: Mbc0MemnGlbac3, - mbc0_memn_glbac4: Mbc0MemnGlbac4, - mbc0_memn_glbac5: Mbc0MemnGlbac5, - mbc0_memn_glbac6: Mbc0MemnGlbac6, - mbc0_memn_glbac7: Mbc0MemnGlbac7, - mbc0_dom0_mem0_blk_cfg_w0: Mbc0Dom0Mem0BlkCfgW0, - mbc0_dom0_mem0_blk_cfg_w1: Mbc0Dom0Mem0BlkCfgW1, - mbc0_dom0_mem0_blk_cfg_w2: Mbc0Dom0Mem0BlkCfgW2, - mbc0_dom0_mem0_blk_cfg_w3: Mbc0Dom0Mem0BlkCfgW3, - mbc0_dom0_mem0_blk_cfg_w4: Mbc0Dom0Mem0BlkCfgW4, - mbc0_dom0_mem0_blk_cfg_w5: Mbc0Dom0Mem0BlkCfgW5, - mbc0_dom0_mem0_blk_cfg_w6: Mbc0Dom0Mem0BlkCfgW6, - mbc0_dom0_mem0_blk_cfg_w7: Mbc0Dom0Mem0BlkCfgW7, - mbc0_dom0_mem0_blk_cfg_w8: Mbc0Dom0Mem0BlkCfgW8, - mbc0_dom0_mem0_blk_cfg_w9: Mbc0Dom0Mem0BlkCfgW9, - mbc0_dom0_mem0_blk_cfg_w10: Mbc0Dom0Mem0BlkCfgW10, - mbc0_dom0_mem0_blk_cfg_w11: Mbc0Dom0Mem0BlkCfgW11, - mbc0_dom0_mem0_blk_cfg_w12: Mbc0Dom0Mem0BlkCfgW12, - mbc0_dom0_mem0_blk_cfg_w13: Mbc0Dom0Mem0BlkCfgW13, - mbc0_dom0_mem0_blk_cfg_w14: Mbc0Dom0Mem0BlkCfgW14, - mbc0_dom0_mem0_blk_cfg_w15: Mbc0Dom0Mem0BlkCfgW15, - _reserved28: [u8; 0x0100], - mbc0_dom0_mem1_blk_cfg_w0: Mbc0Dom0Mem1BlkCfgW0, - mbc0_dom0_mem1_blk_cfg_w1: Mbc0Dom0Mem1BlkCfgW1, - _reserved30: [u8; 0x20], - mbc0_dom0_mem2_blk_cfg_w0: Mbc0Dom0Mem2BlkCfgW0, -} -impl RegisterBlock { - #[doc = "0x00 - MBC Global Configuration Register"] - #[inline(always)] - pub const fn mbc0_mem0_glbcfg(&self) -> &Mbc0Mem0Glbcfg { - &self.mbc0_mem0_glbcfg - } - #[doc = "0x04 - MBC Global Configuration Register"] - #[inline(always)] - pub const fn mbc0_mem1_glbcfg(&self) -> &Mbc0Mem1Glbcfg { - &self.mbc0_mem1_glbcfg - } - #[doc = "0x08 - MBC Global Configuration Register"] - #[inline(always)] - pub const fn mbc0_mem2_glbcfg(&self) -> &Mbc0Mem2Glbcfg { - &self.mbc0_mem2_glbcfg - } - #[doc = "0x0c - MBC Global Configuration Register"] - #[inline(always)] - pub const fn mbc0_mem3_glbcfg(&self) -> &Mbc0Mem3Glbcfg { - &self.mbc0_mem3_glbcfg - } - #[doc = "0x20 - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac0(&self) -> &Mbc0MemnGlbac0 { - &self.mbc0_memn_glbac0 - } - #[doc = "0x24 - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac1(&self) -> &Mbc0MemnGlbac1 { - &self.mbc0_memn_glbac1 - } - #[doc = "0x28 - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac2(&self) -> &Mbc0MemnGlbac2 { - &self.mbc0_memn_glbac2 - } - #[doc = "0x2c - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac3(&self) -> &Mbc0MemnGlbac3 { - &self.mbc0_memn_glbac3 - } - #[doc = "0x30 - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac4(&self) -> &Mbc0MemnGlbac4 { - &self.mbc0_memn_glbac4 - } - #[doc = "0x34 - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac5(&self) -> &Mbc0MemnGlbac5 { - &self.mbc0_memn_glbac5 - } - #[doc = "0x38 - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac6(&self) -> &Mbc0MemnGlbac6 { - &self.mbc0_memn_glbac6 - } - #[doc = "0x3c - MBC Global Access Control"] - #[inline(always)] - pub const fn mbc0_memn_glbac7(&self) -> &Mbc0MemnGlbac7 { - &self.mbc0_memn_glbac7 - } - #[doc = "0x40 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w0(&self) -> &Mbc0Dom0Mem0BlkCfgW0 { - &self.mbc0_dom0_mem0_blk_cfg_w0 - } - #[doc = "0x44 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w1(&self) -> &Mbc0Dom0Mem0BlkCfgW1 { - &self.mbc0_dom0_mem0_blk_cfg_w1 - } - #[doc = "0x48 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w2(&self) -> &Mbc0Dom0Mem0BlkCfgW2 { - &self.mbc0_dom0_mem0_blk_cfg_w2 - } - #[doc = "0x4c - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w3(&self) -> &Mbc0Dom0Mem0BlkCfgW3 { - &self.mbc0_dom0_mem0_blk_cfg_w3 - } - #[doc = "0x50 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w4(&self) -> &Mbc0Dom0Mem0BlkCfgW4 { - &self.mbc0_dom0_mem0_blk_cfg_w4 - } - #[doc = "0x54 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w5(&self) -> &Mbc0Dom0Mem0BlkCfgW5 { - &self.mbc0_dom0_mem0_blk_cfg_w5 - } - #[doc = "0x58 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w6(&self) -> &Mbc0Dom0Mem0BlkCfgW6 { - &self.mbc0_dom0_mem0_blk_cfg_w6 - } - #[doc = "0x5c - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w7(&self) -> &Mbc0Dom0Mem0BlkCfgW7 { - &self.mbc0_dom0_mem0_blk_cfg_w7 - } - #[doc = "0x60 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w8(&self) -> &Mbc0Dom0Mem0BlkCfgW8 { - &self.mbc0_dom0_mem0_blk_cfg_w8 - } - #[doc = "0x64 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w9(&self) -> &Mbc0Dom0Mem0BlkCfgW9 { - &self.mbc0_dom0_mem0_blk_cfg_w9 - } - #[doc = "0x68 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w10(&self) -> &Mbc0Dom0Mem0BlkCfgW10 { - &self.mbc0_dom0_mem0_blk_cfg_w10 - } - #[doc = "0x6c - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w11(&self) -> &Mbc0Dom0Mem0BlkCfgW11 { - &self.mbc0_dom0_mem0_blk_cfg_w11 - } - #[doc = "0x70 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w12(&self) -> &Mbc0Dom0Mem0BlkCfgW12 { - &self.mbc0_dom0_mem0_blk_cfg_w12 - } - #[doc = "0x74 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w13(&self) -> &Mbc0Dom0Mem0BlkCfgW13 { - &self.mbc0_dom0_mem0_blk_cfg_w13 - } - #[doc = "0x78 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w14(&self) -> &Mbc0Dom0Mem0BlkCfgW14 { - &self.mbc0_dom0_mem0_blk_cfg_w14 - } - #[doc = "0x7c - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem0_blk_cfg_w15(&self) -> &Mbc0Dom0Mem0BlkCfgW15 { - &self.mbc0_dom0_mem0_blk_cfg_w15 - } - #[doc = "0x180 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem1_blk_cfg_w0(&self) -> &Mbc0Dom0Mem1BlkCfgW0 { - &self.mbc0_dom0_mem1_blk_cfg_w0 - } - #[doc = "0x184 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem1_blk_cfg_w1(&self) -> &Mbc0Dom0Mem1BlkCfgW1 { - &self.mbc0_dom0_mem1_blk_cfg_w1 - } - #[doc = "0x1a8 - MBC Memory Block Configuration Word"] - #[inline(always)] - pub const fn mbc0_dom0_mem2_blk_cfg_w0(&self) -> &Mbc0Dom0Mem2BlkCfgW0 { - &self.mbc0_dom0_mem2_blk_cfg_w0 - } -} -#[doc = "MBC0_MEM0_GLBCFG (r) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem0_glbcfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem0_glbcfg`] module"] -#[doc(alias = "MBC0_MEM0_GLBCFG")] -pub type Mbc0Mem0Glbcfg = crate::Reg; -#[doc = "MBC Global Configuration Register"] -pub mod mbc0_mem0_glbcfg; -#[doc = "MBC0_MEM1_GLBCFG (r) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem1_glbcfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem1_glbcfg`] module"] -#[doc(alias = "MBC0_MEM1_GLBCFG")] -pub type Mbc0Mem1Glbcfg = crate::Reg; -#[doc = "MBC Global Configuration Register"] -pub mod mbc0_mem1_glbcfg; -#[doc = "MBC0_MEM2_GLBCFG (r) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem2_glbcfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem2_glbcfg`] module"] -#[doc(alias = "MBC0_MEM2_GLBCFG")] -pub type Mbc0Mem2Glbcfg = crate::Reg; -#[doc = "MBC Global Configuration Register"] -pub mod mbc0_mem2_glbcfg; -#[doc = "MBC0_MEM3_GLBCFG (rw) register accessor: MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem3_glbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_mem3_glbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_mem3_glbcfg`] module"] -#[doc(alias = "MBC0_MEM3_GLBCFG")] -pub type Mbc0Mem3Glbcfg = crate::Reg; -#[doc = "MBC Global Configuration Register"] -pub mod mbc0_mem3_glbcfg; -#[doc = "MBC0_MEMN_GLBAC0 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac0`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC0")] -pub type Mbc0MemnGlbac0 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac0; -#[doc = "MBC0_MEMN_GLBAC1 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac1`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC1")] -pub type Mbc0MemnGlbac1 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac1; -#[doc = "MBC0_MEMN_GLBAC2 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac2`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC2")] -pub type Mbc0MemnGlbac2 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac2; -#[doc = "MBC0_MEMN_GLBAC3 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac3`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC3")] -pub type Mbc0MemnGlbac3 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac3; -#[doc = "MBC0_MEMN_GLBAC4 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac4`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC4")] -pub type Mbc0MemnGlbac4 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac4; -#[doc = "MBC0_MEMN_GLBAC5 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac5`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC5")] -pub type Mbc0MemnGlbac5 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac5; -#[doc = "MBC0_MEMN_GLBAC6 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac6`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC6")] -pub type Mbc0MemnGlbac6 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac6; -#[doc = "MBC0_MEMN_GLBAC7 (rw) register accessor: MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_memn_glbac7`] module"] -#[doc(alias = "MBC0_MEMN_GLBAC7")] -pub type Mbc0MemnGlbac7 = crate::Reg; -#[doc = "MBC Global Access Control"] -pub mod mbc0_memn_glbac7; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W0 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w0`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W0")] -pub type Mbc0Dom0Mem0BlkCfgW0 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w0; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W1 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w1`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W1")] -pub type Mbc0Dom0Mem0BlkCfgW1 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w1; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W2 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w2`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W2")] -pub type Mbc0Dom0Mem0BlkCfgW2 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w2; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W3 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w3`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W3")] -pub type Mbc0Dom0Mem0BlkCfgW3 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w3; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W4 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w4`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W4")] -pub type Mbc0Dom0Mem0BlkCfgW4 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w4; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W5 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w5`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W5")] -pub type Mbc0Dom0Mem0BlkCfgW5 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w5; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W6 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w6`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W6")] -pub type Mbc0Dom0Mem0BlkCfgW6 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w6; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W7 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w7`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W7")] -pub type Mbc0Dom0Mem0BlkCfgW7 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w7; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W8 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w8`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W8")] -pub type Mbc0Dom0Mem0BlkCfgW8 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w8; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W9 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w9`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W9")] -pub type Mbc0Dom0Mem0BlkCfgW9 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w9; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W10 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w10`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W10")] -pub type Mbc0Dom0Mem0BlkCfgW10 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w10; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W11 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w11`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W11")] -pub type Mbc0Dom0Mem0BlkCfgW11 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w11; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W12 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w12`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W12")] -pub type Mbc0Dom0Mem0BlkCfgW12 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w12; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W13 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w13`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W13")] -pub type Mbc0Dom0Mem0BlkCfgW13 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w13; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W14 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w14`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W14")] -pub type Mbc0Dom0Mem0BlkCfgW14 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w14; -#[doc = "MBC0_DOM0_MEM0_BLK_CFG_W15 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem0_blk_cfg_w15`] module"] -#[doc(alias = "MBC0_DOM0_MEM0_BLK_CFG_W15")] -pub type Mbc0Dom0Mem0BlkCfgW15 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem0_blk_cfg_w15; -#[doc = "MBC0_DOM0_MEM1_BLK_CFG_W0 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem1_blk_cfg_w0`] module"] -#[doc(alias = "MBC0_DOM0_MEM1_BLK_CFG_W0")] -pub type Mbc0Dom0Mem1BlkCfgW0 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem1_blk_cfg_w0; -#[doc = "MBC0_DOM0_MEM1_BLK_CFG_W1 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem1_blk_cfg_w1`] module"] -#[doc(alias = "MBC0_DOM0_MEM1_BLK_CFG_W1")] -pub type Mbc0Dom0Mem1BlkCfgW1 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem1_blk_cfg_w1; -#[doc = "MBC0_DOM0_MEM2_BLK_CFG_W0 (rw) register accessor: MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem2_blk_cfg_w0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem2_blk_cfg_w0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbc0_dom0_mem2_blk_cfg_w0`] module"] -#[doc(alias = "MBC0_DOM0_MEM2_BLK_CFG_W0")] -pub type Mbc0Dom0Mem2BlkCfgW0 = crate::Reg; -#[doc = "MBC Memory Block Configuration Word"] -pub mod mbc0_dom0_mem2_blk_cfg_w0; diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs deleted file mode 100644 index f46509afc..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w0.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W0` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W0` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW0Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w0::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW0Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w0::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W0 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW0Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs deleted file mode 100644 index 5e7da22b2..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w1.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W1` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W1` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW1Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w1::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW1Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w1::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W1 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW1Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs deleted file mode 100644 index 0149832d9..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w10.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W10` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W10` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW10Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w10::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW10Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w10::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W10 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW10Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs deleted file mode 100644 index 69f032e29..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w11.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W11` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W11` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW11Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w11::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW11Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w11::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W11 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW11Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs deleted file mode 100644 index 51035d48d..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w12.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W12` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W12` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW12Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w12::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW12Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w12::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W12 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW12Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs deleted file mode 100644 index a326ab10a..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w13.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W13` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W13` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW13Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w13::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW13Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w13::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W13 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW13Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs deleted file mode 100644 index 85bf5a398..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w14.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W14` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W14` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW14Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w14::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW14Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w14::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W14 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW14Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs deleted file mode 100644 index fa7bd6c31..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w15.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W15` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W15` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW15Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w15::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW15Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w15::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W15 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW15Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs deleted file mode 100644 index 3fa9b0b69..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w2.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W2` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W2` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW2Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w2::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW2Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w2::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W2 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW2Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs deleted file mode 100644 index e000ae206..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w3.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W3` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W3` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW3Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w3::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW3Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w3::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W3 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW3Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs deleted file mode 100644 index d69c63ba9..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w4.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W4` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W4` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW4Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w4::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW4Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w4::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W4 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW4Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs deleted file mode 100644 index 1b841299f..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w5.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W5` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W5` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW5Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w5::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW5Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w5::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W5 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW5Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs deleted file mode 100644 index b574cb02e..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w6.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W6` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W6` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW6Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w6::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW6Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w6::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W6 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW6Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs deleted file mode 100644 index e8f48713f..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w7.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W7` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W7` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW7Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w7::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW7Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w7::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W7 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW7Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs deleted file mode 100644 index fa964fba7..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w8.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W8` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W8` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW8Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w8::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW8Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w8::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W8 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW8Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs deleted file mode 100644 index f04f97145..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem0_blk_cfg_w9.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W9` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM0_BLK_CFG_W9` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem0_blk_cfg_w9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem0_blk_cfg_w9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem0BlkCfgW9Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem0BlkCfgW9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem0_blk_cfg_w9::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem0BlkCfgW9Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem0_blk_cfg_w9::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem0BlkCfgW9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM0_BLK_CFG_W9 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem0BlkCfgW9Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs deleted file mode 100644 index d764de3d4..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w0.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W0` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W0` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem1BlkCfgW0Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem1BlkCfgW0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem1_blk_cfg_w0::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem1BlkCfgW0Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem1_blk_cfg_w0::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem1BlkCfgW0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM1_BLK_CFG_W0 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem1BlkCfgW0Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs deleted file mode 100644 index efd2bea14..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem1_blk_cfg_w1.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W1` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM1_BLK_CFG_W1` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem1_blk_cfg_w1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem1_blk_cfg_w1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem1BlkCfgW1Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem1BlkCfgW1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem1_blk_cfg_w1::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem1BlkCfgW1Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem1_blk_cfg_w1::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem1BlkCfgW1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM1_BLK_CFG_W1 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem1BlkCfgW1Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs b/mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs deleted file mode 100644 index 13d452400..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_dom0_mem2_blk_cfg_w0.rs +++ /dev/null @@ -1,1709 +0,0 @@ -#[doc = "Register `MBC0_DOM0_MEM2_BLK_CFG_W0` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_DOM0_MEM2_BLK_CFG_W0` writer"] -pub type W = crate::W; -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel0 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel0 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel0 {} -#[doc = "Field `MBACSEL0` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel0R = crate::FieldReader; -impl Mbacsel0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel0 { - match self.bits { - 0 => Mbacsel0::Glbac0, - 1 => Mbacsel0::Glbac1, - 2 => Mbacsel0::Glbac2, - 3 => Mbacsel0::Glbac3, - 4 => Mbacsel0::Glbac4, - 5 => Mbacsel0::Glbac5, - 6 => Mbacsel0::Glbac6, - 7 => Mbacsel0::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel0::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel0::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel0::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel0::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel0::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel0::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel0::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel0::Glbac7 - } -} -#[doc = "Field `MBACSEL0` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel0W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel0, crate::Safe>; -impl<'a, REG> Mbacsel0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel0::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse0 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE0` reader - NonSecure Enable for block B"] -pub type Nse0R = crate::BitReader; -impl Nse0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse0 { - match self.bits { - false => Nse0::Allowed, - true => Nse0::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse0::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse0::Notallowed - } -} -#[doc = "Field `NSE0` writer - NonSecure Enable for block B"] -pub type Nse0W<'a, REG> = crate::BitWriter<'a, REG, Nse0>; -impl<'a, REG> Nse0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse0::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse0::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel1 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel1 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel1 {} -#[doc = "Field `MBACSEL1` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel1R = crate::FieldReader; -impl Mbacsel1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel1 { - match self.bits { - 0 => Mbacsel1::Glbac0, - 1 => Mbacsel1::Glbac1, - 2 => Mbacsel1::Glbac2, - 3 => Mbacsel1::Glbac3, - 4 => Mbacsel1::Glbac4, - 5 => Mbacsel1::Glbac5, - 6 => Mbacsel1::Glbac6, - 7 => Mbacsel1::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel1::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel1::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel1::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel1::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel1::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel1::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel1::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel1::Glbac7 - } -} -#[doc = "Field `MBACSEL1` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel1W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel1, crate::Safe>; -impl<'a, REG> Mbacsel1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel1::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse1 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE1` reader - NonSecure Enable for block B"] -pub type Nse1R = crate::BitReader; -impl Nse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse1 { - match self.bits { - false => Nse1::Allowed, - true => Nse1::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse1::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse1::Notallowed - } -} -#[doc = "Field `NSE1` writer - NonSecure Enable for block B"] -pub type Nse1W<'a, REG> = crate::BitWriter<'a, REG, Nse1>; -impl<'a, REG> Nse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse1::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse1::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel2 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel2 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel2 {} -#[doc = "Field `MBACSEL2` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel2R = crate::FieldReader; -impl Mbacsel2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel2 { - match self.bits { - 0 => Mbacsel2::Glbac0, - 1 => Mbacsel2::Glbac1, - 2 => Mbacsel2::Glbac2, - 3 => Mbacsel2::Glbac3, - 4 => Mbacsel2::Glbac4, - 5 => Mbacsel2::Glbac5, - 6 => Mbacsel2::Glbac6, - 7 => Mbacsel2::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel2::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel2::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel2::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel2::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel2::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel2::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel2::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel2::Glbac7 - } -} -#[doc = "Field `MBACSEL2` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel2W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel2, crate::Safe>; -impl<'a, REG> Mbacsel2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel2::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse2 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE2` reader - NonSecure Enable for block B"] -pub type Nse2R = crate::BitReader; -impl Nse2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse2 { - match self.bits { - false => Nse2::Allowed, - true => Nse2::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse2::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse2::Notallowed - } -} -#[doc = "Field `NSE2` writer - NonSecure Enable for block B"] -pub type Nse2W<'a, REG> = crate::BitWriter<'a, REG, Nse2>; -impl<'a, REG> Nse2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse2::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse2::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel3 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel3 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel3 {} -#[doc = "Field `MBACSEL3` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel3R = crate::FieldReader; -impl Mbacsel3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel3 { - match self.bits { - 0 => Mbacsel3::Glbac0, - 1 => Mbacsel3::Glbac1, - 2 => Mbacsel3::Glbac2, - 3 => Mbacsel3::Glbac3, - 4 => Mbacsel3::Glbac4, - 5 => Mbacsel3::Glbac5, - 6 => Mbacsel3::Glbac6, - 7 => Mbacsel3::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel3::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel3::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel3::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel3::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel3::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel3::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel3::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel3::Glbac7 - } -} -#[doc = "Field `MBACSEL3` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel3W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel3, crate::Safe>; -impl<'a, REG> Mbacsel3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel3::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse3 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE3` reader - NonSecure Enable for block B"] -pub type Nse3R = crate::BitReader; -impl Nse3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse3 { - match self.bits { - false => Nse3::Allowed, - true => Nse3::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse3::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse3::Notallowed - } -} -#[doc = "Field `NSE3` writer - NonSecure Enable for block B"] -pub type Nse3W<'a, REG> = crate::BitWriter<'a, REG, Nse3>; -impl<'a, REG> Nse3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse3::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse3::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel4 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel4 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel4 {} -#[doc = "Field `MBACSEL4` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel4R = crate::FieldReader; -impl Mbacsel4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel4 { - match self.bits { - 0 => Mbacsel4::Glbac0, - 1 => Mbacsel4::Glbac1, - 2 => Mbacsel4::Glbac2, - 3 => Mbacsel4::Glbac3, - 4 => Mbacsel4::Glbac4, - 5 => Mbacsel4::Glbac5, - 6 => Mbacsel4::Glbac6, - 7 => Mbacsel4::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel4::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel4::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel4::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel4::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel4::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel4::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel4::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel4::Glbac7 - } -} -#[doc = "Field `MBACSEL4` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel4W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel4, crate::Safe>; -impl<'a, REG> Mbacsel4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel4::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse4 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE4` reader - NonSecure Enable for block B"] -pub type Nse4R = crate::BitReader; -impl Nse4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse4 { - match self.bits { - false => Nse4::Allowed, - true => Nse4::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse4::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse4::Notallowed - } -} -#[doc = "Field `NSE4` writer - NonSecure Enable for block B"] -pub type Nse4W<'a, REG> = crate::BitWriter<'a, REG, Nse4>; -impl<'a, REG> Nse4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse4::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse4::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel5 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel5 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel5 {} -#[doc = "Field `MBACSEL5` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel5R = crate::FieldReader; -impl Mbacsel5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel5 { - match self.bits { - 0 => Mbacsel5::Glbac0, - 1 => Mbacsel5::Glbac1, - 2 => Mbacsel5::Glbac2, - 3 => Mbacsel5::Glbac3, - 4 => Mbacsel5::Glbac4, - 5 => Mbacsel5::Glbac5, - 6 => Mbacsel5::Glbac6, - 7 => Mbacsel5::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel5::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel5::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel5::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel5::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel5::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel5::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel5::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel5::Glbac7 - } -} -#[doc = "Field `MBACSEL5` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel5W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel5, crate::Safe>; -impl<'a, REG> Mbacsel5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel5::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse5 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE5` reader - NonSecure Enable for block B"] -pub type Nse5R = crate::BitReader; -impl Nse5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse5 { - match self.bits { - false => Nse5::Allowed, - true => Nse5::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse5::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse5::Notallowed - } -} -#[doc = "Field `NSE5` writer - NonSecure Enable for block B"] -pub type Nse5W<'a, REG> = crate::BitWriter<'a, REG, Nse5>; -impl<'a, REG> Nse5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse5::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse5::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel6 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel6 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel6 {} -#[doc = "Field `MBACSEL6` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel6R = crate::FieldReader; -impl Mbacsel6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel6 { - match self.bits { - 0 => Mbacsel6::Glbac0, - 1 => Mbacsel6::Glbac1, - 2 => Mbacsel6::Glbac2, - 3 => Mbacsel6::Glbac3, - 4 => Mbacsel6::Glbac4, - 5 => Mbacsel6::Glbac5, - 6 => Mbacsel6::Glbac6, - 7 => Mbacsel6::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel6::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel6::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel6::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel6::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel6::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel6::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel6::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel6::Glbac7 - } -} -#[doc = "Field `MBACSEL6` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel6W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel6, crate::Safe>; -impl<'a, REG> Mbacsel6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel6::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse6 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE6` reader - NonSecure Enable for block B"] -pub type Nse6R = crate::BitReader; -impl Nse6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse6 { - match self.bits { - false => Nse6::Allowed, - true => Nse6::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse6::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse6::Notallowed - } -} -#[doc = "Field `NSE6` writer - NonSecure Enable for block B"] -pub type Nse6W<'a, REG> = crate::BitWriter<'a, REG, Nse6>; -impl<'a, REG> Nse6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse6::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse6::Notallowed) - } -} -#[doc = "Memory Block Access Control Select for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mbacsel7 { - #[doc = "0: select MBC_MEMN_GLBAC0 access control policy for block B"] - Glbac0 = 0, - #[doc = "1: select MBC_MEMN_GLBAC1 access control policy for block B"] - Glbac1 = 1, - #[doc = "2: select MBC_MEMN_GLBAC2 access control policy for block B"] - Glbac2 = 2, - #[doc = "3: select MBC_MEMN_GLBAC3 access control policy for block B"] - Glbac3 = 3, - #[doc = "4: select MBC_MEMN_GLBAC4 access control policy for block B"] - Glbac4 = 4, - #[doc = "5: select MBC_MEMN_GLBAC5 access control policy for block B"] - Glbac5 = 5, - #[doc = "6: select MBC_MEMN_GLBAC6 access control policy for block B"] - Glbac6 = 6, - #[doc = "7: select MBC_MEMN_GLBAC7 access control policy for block B"] - Glbac7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mbacsel7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mbacsel7 { - type Ux = u8; -} -impl crate::IsEnum for Mbacsel7 {} -#[doc = "Field `MBACSEL7` reader - Memory Block Access Control Select for block B"] -pub type Mbacsel7R = crate::FieldReader; -impl Mbacsel7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mbacsel7 { - match self.bits { - 0 => Mbacsel7::Glbac0, - 1 => Mbacsel7::Glbac1, - 2 => Mbacsel7::Glbac2, - 3 => Mbacsel7::Glbac3, - 4 => Mbacsel7::Glbac4, - 5 => Mbacsel7::Glbac5, - 6 => Mbacsel7::Glbac6, - 7 => Mbacsel7::Glbac7, - _ => unreachable!(), - } - } - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn is_glbac0(&self) -> bool { - *self == Mbacsel7::Glbac0 - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn is_glbac1(&self) -> bool { - *self == Mbacsel7::Glbac1 - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn is_glbac2(&self) -> bool { - *self == Mbacsel7::Glbac2 - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn is_glbac3(&self) -> bool { - *self == Mbacsel7::Glbac3 - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn is_glbac4(&self) -> bool { - *self == Mbacsel7::Glbac4 - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn is_glbac5(&self) -> bool { - *self == Mbacsel7::Glbac5 - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn is_glbac6(&self) -> bool { - *self == Mbacsel7::Glbac6 - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn is_glbac7(&self) -> bool { - *self == Mbacsel7::Glbac7 - } -} -#[doc = "Field `MBACSEL7` writer - Memory Block Access Control Select for block B"] -pub type Mbacsel7W<'a, REG> = crate::FieldWriter<'a, REG, 3, Mbacsel7, crate::Safe>; -impl<'a, REG> Mbacsel7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B"] - #[inline(always)] - pub fn glbac0(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac0) - } - #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B"] - #[inline(always)] - pub fn glbac1(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac1) - } - #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B"] - #[inline(always)] - pub fn glbac2(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac2) - } - #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B"] - #[inline(always)] - pub fn glbac3(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac3) - } - #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B"] - #[inline(always)] - pub fn glbac4(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac4) - } - #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B"] - #[inline(always)] - pub fn glbac5(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac5) - } - #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B"] - #[inline(always)] - pub fn glbac6(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac6) - } - #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B"] - #[inline(always)] - pub fn glbac7(self) -> &'a mut crate::W { - self.variant(Mbacsel7::Glbac7) - } -} -#[doc = "NonSecure Enable for block B\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nse7 { - #[doc = "0: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - Allowed = 0, - #[doc = "1: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - Notallowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nse7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSE7` reader - NonSecure Enable for block B"] -pub type Nse7R = crate::BitReader; -impl Nse7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nse7 { - match self.bits { - false => Nse7::Allowed, - true => Nse7::Notallowed, - } - } - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nse7::Allowed - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nse7::Notallowed - } -} -#[doc = "Field `NSE7` writer - NonSecure Enable for block B"] -pub type Nse7W<'a, REG> = crate::BitWriter<'a, REG, Nse7>; -impl<'a, REG> Nse7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nse7::Allowed) - } - #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nse7::Notallowed) - } -} -impl R { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&self) -> Mbacsel0R { - Mbacsel0R::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&self) -> Nse0R { - Nse0R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&self) -> Mbacsel1R { - Mbacsel1R::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&self) -> Nse1R { - Nse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&self) -> Mbacsel2R { - Mbacsel2R::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&self) -> Nse2R { - Nse2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&self) -> Mbacsel3R { - Mbacsel3R::new(((self.bits >> 12) & 7) as u8) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&self) -> Nse3R { - Nse3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&self) -> Mbacsel4R { - Mbacsel4R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&self) -> Nse4R { - Nse4R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&self) -> Mbacsel5R { - Mbacsel5R::new(((self.bits >> 20) & 7) as u8) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&self) -> Nse5R { - Nse5R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&self) -> Mbacsel6R { - Mbacsel6R::new(((self.bits >> 24) & 7) as u8) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&self) -> Nse6R { - Nse6R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&self) -> Mbacsel7R { - Mbacsel7R::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&self) -> Nse7R { - Nse7R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel0(&mut self) -> Mbacsel0W { - Mbacsel0W::new(self, 0) - } - #[doc = "Bit 3 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse0(&mut self) -> Nse0W { - Nse0W::new(self, 3) - } - #[doc = "Bits 4:6 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel1(&mut self) -> Mbacsel1W { - Mbacsel1W::new(self, 4) - } - #[doc = "Bit 7 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse1(&mut self) -> Nse1W { - Nse1W::new(self, 7) - } - #[doc = "Bits 8:10 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel2(&mut self) -> Mbacsel2W { - Mbacsel2W::new(self, 8) - } - #[doc = "Bit 11 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse2(&mut self) -> Nse2W { - Nse2W::new(self, 11) - } - #[doc = "Bits 12:14 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel3(&mut self) -> Mbacsel3W { - Mbacsel3W::new(self, 12) - } - #[doc = "Bit 15 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse3(&mut self) -> Nse3W { - Nse3W::new(self, 15) - } - #[doc = "Bits 16:18 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel4(&mut self) -> Mbacsel4W { - Mbacsel4W::new(self, 16) - } - #[doc = "Bit 19 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse4(&mut self) -> Nse4W { - Nse4W::new(self, 19) - } - #[doc = "Bits 20:22 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel5(&mut self) -> Mbacsel5W { - Mbacsel5W::new(self, 20) - } - #[doc = "Bit 23 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse5(&mut self) -> Nse5W { - Nse5W::new(self, 23) - } - #[doc = "Bits 24:26 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel6(&mut self) -> Mbacsel6W { - Mbacsel6W::new(self, 24) - } - #[doc = "Bit 27 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse6(&mut self) -> Nse6W { - Nse6W::new(self, 27) - } - #[doc = "Bits 28:30 - Memory Block Access Control Select for block B"] - #[inline(always)] - pub fn mbacsel7(&mut self) -> Mbacsel7W { - Mbacsel7W::new(self, 28) - } - #[doc = "Bit 31 - NonSecure Enable for block B"] - #[inline(always)] - pub fn nse7(&mut self) -> Nse7W { - Nse7W::new(self, 31) - } -} -#[doc = "MBC Memory Block Configuration Word\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_dom0_mem2_blk_cfg_w0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_dom0_mem2_blk_cfg_w0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Dom0Mem2BlkCfgW0Spec; -impl crate::RegisterSpec for Mbc0Dom0Mem2BlkCfgW0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_dom0_mem2_blk_cfg_w0::R`](R) reader structure"] -impl crate::Readable for Mbc0Dom0Mem2BlkCfgW0Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_dom0_mem2_blk_cfg_w0::W`](W) writer structure"] -impl crate::Writable for Mbc0Dom0Mem2BlkCfgW0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_DOM0_MEM2_BLK_CFG_W0 to value 0"] -impl crate::Resettable for Mbc0Dom0Mem2BlkCfgW0Spec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs deleted file mode 100644 index a1e105c7b..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_mem0_glbcfg.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `MBC0_MEM0_GLBCFG` reader"] -pub type R = crate::R; -#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] -pub type NblksR = crate::FieldReader; -#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] -pub type SizeLog2R = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - Number of blocks in this memory"] - #[inline(always)] - pub fn nblks(&self) -> NblksR { - NblksR::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 16:20 - Log2 size per block"] - #[inline(always)] - pub fn size_log2(&self) -> SizeLog2R { - SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) - } -} -#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem0_glbcfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Mem0GlbcfgSpec; -impl crate::RegisterSpec for Mbc0Mem0GlbcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_mem0_glbcfg::R`](R) reader structure"] -impl crate::Readable for Mbc0Mem0GlbcfgSpec {} -#[doc = "`reset()` method sets MBC0_MEM0_GLBCFG to value 0x000d_0080"] -impl crate::Resettable for Mbc0Mem0GlbcfgSpec { - const RESET_VALUE: u32 = 0x000d_0080; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs deleted file mode 100644 index b36ca09ab..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_mem1_glbcfg.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `MBC0_MEM1_GLBCFG` reader"] -pub type R = crate::R; -#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] -pub type NblksR = crate::FieldReader; -#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] -pub type SizeLog2R = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - Number of blocks in this memory"] - #[inline(always)] - pub fn nblks(&self) -> NblksR { - NblksR::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 16:20 - Log2 size per block"] - #[inline(always)] - pub fn size_log2(&self) -> SizeLog2R { - SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) - } -} -#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem1_glbcfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Mem1GlbcfgSpec; -impl crate::RegisterSpec for Mbc0Mem1GlbcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_mem1_glbcfg::R`](R) reader structure"] -impl crate::Readable for Mbc0Mem1GlbcfgSpec {} -#[doc = "`reset()` method sets MBC0_MEM1_GLBCFG to value 0x000b_0010"] -impl crate::Resettable for Mbc0Mem1GlbcfgSpec { - const RESET_VALUE: u32 = 0x000b_0010; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs deleted file mode 100644 index c7f2b4f41..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_mem2_glbcfg.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `MBC0_MEM2_GLBCFG` reader"] -pub type R = crate::R; -#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] -pub type NblksR = crate::FieldReader; -#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] -pub type SizeLog2R = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - Number of blocks in this memory"] - #[inline(always)] - pub fn nblks(&self) -> NblksR { - NblksR::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 16:20 - Log2 size per block"] - #[inline(always)] - pub fn size_log2(&self) -> SizeLog2R { - SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) - } -} -#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem2_glbcfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Mem2GlbcfgSpec; -impl crate::RegisterSpec for Mbc0Mem2GlbcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_mem2_glbcfg::R`](R) reader structure"] -impl crate::Readable for Mbc0Mem2GlbcfgSpec {} -#[doc = "`reset()` method sets MBC0_MEM2_GLBCFG to value 0x000b_0004"] -impl crate::Resettable for Mbc0Mem2GlbcfgSpec { - const RESET_VALUE: u32 = 0x000b_0004; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs b/mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs deleted file mode 100644 index c4ce138bc..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_mem3_glbcfg.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `MBC0_MEM3_GLBCFG` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEM3_GLBCFG` writer"] -pub type W = crate::W; -#[doc = "Field `NBLKS` reader - Number of blocks in this memory"] -pub type NblksR = crate::FieldReader; -#[doc = "Field `SIZE_LOG2` reader - Log2 size per block"] -pub type SizeLog2R = crate::FieldReader; -#[doc = "Field `CLRE` reader - Clear Error"] -pub type ClreR = crate::FieldReader; -#[doc = "Field `CLRE` writer - Clear Error"] -pub type ClreW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:9 - Number of blocks in this memory"] - #[inline(always)] - pub fn nblks(&self) -> NblksR { - NblksR::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 16:20 - Log2 size per block"] - #[inline(always)] - pub fn size_log2(&self) -> SizeLog2R { - SizeLog2R::new(((self.bits >> 16) & 0x1f) as u8) - } - #[doc = "Bits 30:31 - Clear Error"] - #[inline(always)] - pub fn clre(&self) -> ClreR { - ClreR::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bits 30:31 - Clear Error"] - #[inline(always)] - pub fn clre(&mut self) -> ClreW { - ClreW::new(self, 30) - } -} -#[doc = "MBC Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_mem3_glbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_mem3_glbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0Mem3GlbcfgSpec; -impl crate::RegisterSpec for Mbc0Mem3GlbcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_mem3_glbcfg::R`](R) reader structure"] -impl crate::Readable for Mbc0Mem3GlbcfgSpec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_mem3_glbcfg::W`](W) writer structure"] -impl crate::Writable for Mbc0Mem3GlbcfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEM3_GLBCFG to value 0"] -impl crate::Resettable for Mbc0Mem3GlbcfgSpec {} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs deleted file mode 100644 index 8430ca1e6..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac0.rs +++ /dev/null @@ -1,779 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC0` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC0` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac0Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac0::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac0Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac0::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC0 to value 0x6600"] -impl crate::Resettable for Mbc0MemnGlbac0Spec { - const RESET_VALUE: u32 = 0x6600; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs deleted file mode 100644 index 1c90b0421..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac1.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC1` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC1` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -#[doc = "LOCK\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This register is not locked and can be altered."] - Unlocked = 0, - #[doc = "1: This register is locked and cannot be altered."] - Locked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - LOCK"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Unlocked, - true => Lk::Locked, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == Lk::Unlocked - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == Lk::Locked - } -} -#[doc = "Field `LK` writer - LOCK"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(Lk::Unlocked) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(Lk::Locked) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 31) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac1Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac1::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac1Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac1::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC1 to value 0x8000_6600"] -impl crate::Resettable for Mbc0MemnGlbac1Spec { - const RESET_VALUE: u32 = 0x8000_6600; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs deleted file mode 100644 index 1943900c8..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac2.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC2` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC2` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -#[doc = "LOCK\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This register is not locked and can be altered."] - Unlocked = 0, - #[doc = "1: This register is locked and cannot be altered."] - Locked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - LOCK"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Unlocked, - true => Lk::Locked, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == Lk::Unlocked - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == Lk::Locked - } -} -#[doc = "Field `LK` writer - LOCK"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(Lk::Unlocked) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(Lk::Locked) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 31) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac2Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac2::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac2Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac2::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC2 to value 0x8000_5500"] -impl crate::Resettable for Mbc0MemnGlbac2Spec { - const RESET_VALUE: u32 = 0x8000_5500; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs deleted file mode 100644 index e06076bfa..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac3.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC3` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC3` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -#[doc = "LOCK\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This register is not locked and can be altered."] - Unlocked = 0, - #[doc = "1: This register is locked and cannot be altered."] - Locked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - LOCK"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Unlocked, - true => Lk::Locked, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == Lk::Unlocked - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == Lk::Locked - } -} -#[doc = "Field `LK` writer - LOCK"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(Lk::Unlocked) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(Lk::Locked) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 31) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac3Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac3::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac3Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac3::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC3 to value 0x8000_4400"] -impl crate::Resettable for Mbc0MemnGlbac3Spec { - const RESET_VALUE: u32 = 0x8000_4400; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs deleted file mode 100644 index 7c8e773ed..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac4.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC4` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC4` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -#[doc = "LOCK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This register is not locked and can be altered."] - Unlocked = 0, - #[doc = "1: This register is locked and cannot be altered."] - Locked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - LOCK"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Unlocked, - true => Lk::Locked, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == Lk::Unlocked - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == Lk::Locked - } -} -#[doc = "Field `LK` writer - LOCK"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(Lk::Unlocked) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(Lk::Locked) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 31) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac4Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac4::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac4Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac4::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC4 to value 0x5500"] -impl crate::Resettable for Mbc0MemnGlbac4Spec { - const RESET_VALUE: u32 = 0x5500; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs deleted file mode 100644 index 9cf186a8b..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac5.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC5` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC5` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -#[doc = "LOCK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This register is not locked and can be altered."] - Unlocked = 0, - #[doc = "1: This register is locked and cannot be altered."] - Locked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - LOCK"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Unlocked, - true => Lk::Locked, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == Lk::Unlocked - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == Lk::Locked - } -} -#[doc = "Field `LK` writer - LOCK"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(Lk::Unlocked) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(Lk::Locked) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 31) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac5Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac5::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac5Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac5::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC5 to value 0x1100"] -impl crate::Resettable for Mbc0MemnGlbac5Spec { - const RESET_VALUE: u32 = 0x1100; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs deleted file mode 100644 index a06e436a9..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac6.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC6` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC6` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -#[doc = "LOCK\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This register is not locked and can be altered."] - Unlocked = 0, - #[doc = "1: This register is locked and cannot be altered."] - Locked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - LOCK"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Unlocked, - true => Lk::Locked, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == Lk::Unlocked - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == Lk::Locked - } -} -#[doc = "Field `LK` writer - LOCK"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(Lk::Unlocked) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(Lk::Locked) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 31) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac6Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac6::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac6Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac6::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC6 to value 0x8000_1100"] -impl crate::Resettable for Mbc0MemnGlbac6Spec { - const RESET_VALUE: u32 = 0x8000_1100; -} diff --git a/mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs b/mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs deleted file mode 100644 index 7378d4533..000000000 --- a/mcxa276-pac/src/mbc0/mbc0_memn_glbac7.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `MBC0_MEMN_GLBAC7` reader"] -pub type R = crate::R; -#[doc = "Register `MBC0_MEMN_GLBAC7` writer"] -pub type W = crate::W; -#[doc = "NonsecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nux { - #[doc = "0: Execute access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUX` reader - NonsecureUser Execute"] -pub type NuxR = crate::BitReader; -impl NuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nux { - match self.bits { - false => Nux::Notallowed, - true => Nux::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nux::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nux::Allowed - } -} -#[doc = "Field `NUX` writer - NonsecureUser Execute"] -pub type NuxW<'a, REG> = crate::BitWriter<'a, REG, Nux>; -impl<'a, REG> NuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nux::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nux::Allowed) - } -} -#[doc = "NonsecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nuw { - #[doc = "0: Write access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nuw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUW` reader - NonsecureUser Write"] -pub type NuwR = crate::BitReader; -impl NuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nuw { - match self.bits { - false => Nuw::Notallowed, - true => Nuw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nuw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nuw::Allowed - } -} -#[doc = "Field `NUW` writer - NonsecureUser Write"] -pub type NuwW<'a, REG> = crate::BitWriter<'a, REG, Nuw>; -impl<'a, REG> NuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nuw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nuw::Allowed) - } -} -#[doc = "NonsecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nur { - #[doc = "0: Read access is not allowed in Nonsecure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NUR` reader - NonsecureUser Read"] -pub type NurR = crate::BitReader; -impl NurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nur { - match self.bits { - false => Nur::Notallowed, - true => Nur::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Nur::Notallowed - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Nur::Allowed - } -} -#[doc = "Field `NUR` writer - NonsecureUser Read"] -pub type NurW<'a, REG> = crate::BitWriter<'a, REG, Nur>; -impl<'a, REG> NurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Nur::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Nur::Allowed) - } -} -#[doc = "NonsecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npx { - #[doc = "0: Execute access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPX` reader - NonsecurePriv Execute"] -pub type NpxR = crate::BitReader; -impl NpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npx { - match self.bits { - false => Npx::Notallowed, - true => Npx::Allowed, - } - } - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npx::Notallowed - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npx::Allowed - } -} -#[doc = "Field `NPX` writer - NonsecurePriv Execute"] -pub type NpxW<'a, REG> = crate::BitWriter<'a, REG, Npx>; -impl<'a, REG> NpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npx::Notallowed) - } - #[doc = "Execute access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npx::Allowed) - } -} -#[doc = "NonsecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npw { - #[doc = "0: Write access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPW` reader - NonsecurePriv Write"] -pub type NpwR = crate::BitReader; -impl NpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npw { - match self.bits { - false => Npw::Notallowed, - true => Npw::Allowed, - } - } - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npw::Notallowed - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npw::Allowed - } -} -#[doc = "Field `NPW` writer - NonsecurePriv Write"] -pub type NpwW<'a, REG> = crate::BitWriter<'a, REG, Npw>; -impl<'a, REG> NpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npw::Notallowed) - } - #[doc = "Write access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npw::Allowed) - } -} -#[doc = "NonsecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Npr { - #[doc = "0: Read access is not allowed in Nonsecure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Nonsecure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Npr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NPR` reader - NonsecurePriv Read"] -pub type NprR = crate::BitReader; -impl NprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Npr { - match self.bits { - false => Npr::Notallowed, - true => Npr::Allowed, - } - } - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Npr::Notallowed - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Npr::Allowed - } -} -#[doc = "Field `NPR` writer - NonsecurePriv Read"] -pub type NprW<'a, REG> = crate::BitWriter<'a, REG, Npr>; -impl<'a, REG> NprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Npr::Notallowed) - } - #[doc = "Read access is allowed in Nonsecure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Npr::Allowed) - } -} -#[doc = "SecureUser Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sux { - #[doc = "0: Execute access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sux) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUX` reader - SecureUser Execute"] -pub type SuxR = crate::BitReader; -impl SuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sux { - match self.bits { - false => Sux::Notallowed, - true => Sux::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sux::Notallowed - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sux::Allowed - } -} -#[doc = "Field `SUX` writer - SecureUser Execute"] -pub type SuxW<'a, REG> = crate::BitWriter<'a, REG, Sux>; -impl<'a, REG> SuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sux::Notallowed) - } - #[doc = "Execute access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sux::Allowed) - } -} -#[doc = "SecureUser Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Suw { - #[doc = "0: Write access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Suw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUW` reader - SecureUser Write"] -pub type SuwR = crate::BitReader; -impl SuwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Suw { - match self.bits { - false => Suw::Notallowed, - true => Suw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Suw::Notallowed - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Suw::Allowed - } -} -#[doc = "Field `SUW` writer - SecureUser Write"] -pub type SuwW<'a, REG> = crate::BitWriter<'a, REG, Suw>; -impl<'a, REG> SuwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Suw::Notallowed) - } - #[doc = "Write access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Suw::Allowed) - } -} -#[doc = "SecureUser Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sur { - #[doc = "0: Read access is not allowed in Secure User mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure User mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sur) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUR` reader - SecureUser Read"] -pub type SurR = crate::BitReader; -impl SurR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sur { - match self.bits { - false => Sur::Notallowed, - true => Sur::Allowed, - } - } - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Sur::Notallowed - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Sur::Allowed - } -} -#[doc = "Field `SUR` writer - SecureUser Read"] -pub type SurW<'a, REG> = crate::BitWriter<'a, REG, Sur>; -impl<'a, REG> SurW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure User mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Sur::Notallowed) - } - #[doc = "Read access is allowed in Secure User mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Sur::Allowed) - } -} -#[doc = "SecurePriv Execute\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spx { - #[doc = "0: Execute access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Execute access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPX` reader - SecurePriv Execute"] -pub type SpxR = crate::BitReader; -impl SpxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spx { - match self.bits { - false => Spx::Notallowed, - true => Spx::Allowed, - } - } - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spx::Notallowed - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spx::Allowed - } -} -#[doc = "Field `SPX` writer - SecurePriv Execute"] -pub type SpxW<'a, REG> = crate::BitWriter<'a, REG, Spx>; -impl<'a, REG> SpxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spx::Notallowed) - } - #[doc = "Execute access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spx::Allowed) - } -} -#[doc = "SecurePriv Write\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spw { - #[doc = "0: Write access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Write access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spw) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPW` reader - SecurePriv Write"] -pub type SpwR = crate::BitReader; -impl SpwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spw { - match self.bits { - false => Spw::Notallowed, - true => Spw::Allowed, - } - } - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spw::Notallowed - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spw::Allowed - } -} -#[doc = "Field `SPW` writer - SecurePriv Write"] -pub type SpwW<'a, REG> = crate::BitWriter<'a, REG, Spw>; -impl<'a, REG> SpwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spw::Notallowed) - } - #[doc = "Write access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spw::Allowed) - } -} -#[doc = "SecurePriv Read\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spr { - #[doc = "0: Read access is not allowed in Secure Privilege mode."] - Notallowed = 0, - #[doc = "1: Read access is allowed in Secure Privilege mode."] - Allowed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPR` reader - SecurePriv Read"] -pub type SprR = crate::BitReader; -impl SprR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spr { - match self.bits { - false => Spr::Notallowed, - true => Spr::Allowed, - } - } - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_notallowed(&self) -> bool { - *self == Spr::Notallowed - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn is_allowed(&self) -> bool { - *self == Spr::Allowed - } -} -#[doc = "Field `SPR` writer - SecurePriv Read"] -pub type SprW<'a, REG> = crate::BitWriter<'a, REG, Spr>; -impl<'a, REG> SprW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Read access is not allowed in Secure Privilege mode."] - #[inline(always)] - pub fn notallowed(self) -> &'a mut crate::W { - self.variant(Spr::Notallowed) - } - #[doc = "Read access is allowed in Secure Privilege mode."] - #[inline(always)] - pub fn allowed(self) -> &'a mut crate::W { - self.variant(Spr::Allowed) - } -} -#[doc = "LOCK\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This register is not locked and can be altered."] - Unlocked = 0, - #[doc = "1: This register is locked and cannot be altered."] - Locked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - LOCK"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Unlocked, - true => Lk::Locked, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_unlocked(&self) -> bool { - *self == Lk::Unlocked - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == Lk::Locked - } -} -#[doc = "Field `LK` writer - LOCK"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn unlocked(self) -> &'a mut crate::W { - self.variant(Lk::Unlocked) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(Lk::Locked) - } -} -impl R { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&self) -> NuxR { - NuxR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&self) -> NuwR { - NuwR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&self) -> NurR { - NurR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&self) -> NpxR { - NpxR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&self) -> NpwR { - NpwR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&self) -> NprR { - NprR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&self) -> SuxR { - SuxR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&self) -> SuwR { - SuwR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&self) -> SurR { - SurR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&self) -> SpxR { - SpxR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&self) -> SpwR { - SpwR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&self) -> SprR { - SprR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - NonsecureUser Execute"] - #[inline(always)] - pub fn nux(&mut self) -> NuxW { - NuxW::new(self, 0) - } - #[doc = "Bit 1 - NonsecureUser Write"] - #[inline(always)] - pub fn nuw(&mut self) -> NuwW { - NuwW::new(self, 1) - } - #[doc = "Bit 2 - NonsecureUser Read"] - #[inline(always)] - pub fn nur(&mut self) -> NurW { - NurW::new(self, 2) - } - #[doc = "Bit 4 - NonsecurePriv Execute"] - #[inline(always)] - pub fn npx(&mut self) -> NpxW { - NpxW::new(self, 4) - } - #[doc = "Bit 5 - NonsecurePriv Write"] - #[inline(always)] - pub fn npw(&mut self) -> NpwW { - NpwW::new(self, 5) - } - #[doc = "Bit 6 - NonsecurePriv Read"] - #[inline(always)] - pub fn npr(&mut self) -> NprW { - NprW::new(self, 6) - } - #[doc = "Bit 8 - SecureUser Execute"] - #[inline(always)] - pub fn sux(&mut self) -> SuxW { - SuxW::new(self, 8) - } - #[doc = "Bit 9 - SecureUser Write"] - #[inline(always)] - pub fn suw(&mut self) -> SuwW { - SuwW::new(self, 9) - } - #[doc = "Bit 10 - SecureUser Read"] - #[inline(always)] - pub fn sur(&mut self) -> SurW { - SurW::new(self, 10) - } - #[doc = "Bit 12 - SecurePriv Execute"] - #[inline(always)] - pub fn spx(&mut self) -> SpxW { - SpxW::new(self, 12) - } - #[doc = "Bit 13 - SecurePriv Write"] - #[inline(always)] - pub fn spw(&mut self) -> SpwW { - SpwW::new(self, 13) - } - #[doc = "Bit 14 - SecurePriv Read"] - #[inline(always)] - pub fn spr(&mut self) -> SprW { - SprW::new(self, 14) - } - #[doc = "Bit 31 - LOCK"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 31) - } -} -#[doc = "MBC Global Access Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mbc0_memn_glbac7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mbc0_memn_glbac7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Mbc0MemnGlbac7Spec; -impl crate::RegisterSpec for Mbc0MemnGlbac7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mbc0_memn_glbac7::R`](R) reader structure"] -impl crate::Readable for Mbc0MemnGlbac7Spec {} -#[doc = "`write(|w| ..)` method takes [`mbc0_memn_glbac7::W`](W) writer structure"] -impl crate::Writable for Mbc0MemnGlbac7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MBC0_MEMN_GLBAC7 to value 0x8000_0000"] -impl crate::Resettable for Mbc0MemnGlbac7Spec { - const RESET_VALUE: u32 = 0x8000_0000; -} diff --git a/mcxa276-pac/src/mrcc0.rs b/mcxa276-pac/src/mrcc0.rs deleted file mode 100644 index 654a7ffd6..000000000 --- a/mcxa276-pac/src/mrcc0.rs +++ /dev/null @@ -1,986 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - mrcc_glb_rst0: MrccGlbRst0, - mrcc_glb_rst0_set: MrccGlbRst0Set, - mrcc_glb_rst0_clr: MrccGlbRst0Clr, - _reserved3: [u8; 0x04], - mrcc_glb_rst1: MrccGlbRst1, - mrcc_glb_rst1_set: MrccGlbRst1Set, - mrcc_glb_rst1_clr: MrccGlbRst1Clr, - _reserved6: [u8; 0x04], - mrcc_glb_rst2: MrccGlbRst2, - mrcc_glb_rst2_set: MrccGlbRst2Set, - mrcc_glb_rst2_clr: MrccGlbRst2Clr, - _reserved9: [u8; 0x14], - mrcc_glb_cc0: MrccGlbCc0, - mrcc_glb_cc0_set: MrccGlbCc0Set, - mrcc_glb_cc0_clr: MrccGlbCc0Clr, - _reserved12: [u8; 0x04], - mrcc_glb_cc1: MrccGlbCc1, - mrcc_glb_cc1_set: MrccGlbCc1Set, - mrcc_glb_cc1_clr: MrccGlbCc1Clr, - _reserved15: [u8; 0x04], - mrcc_glb_cc2: MrccGlbCc2, - mrcc_glb_cc2_set: MrccGlbCc2Set, - mrcc_glb_cc2_clr: MrccGlbCc2Clr, - _reserved18: [u8; 0x14], - mrcc_glb_acc0: MrccGlbAcc0, - mrcc_glb_acc1: MrccGlbAcc1, - mrcc_glb_acc2: MrccGlbAcc2, - _reserved21: [u8; 0x14], - mrcc_i3c0_fclk_clksel: MrccI3c0FclkClksel, - mrcc_i3c0_fclk_clkdiv: MrccI3c0FclkClkdiv, - mrcc_ctimer0_clksel: MrccCtimer0Clksel, - mrcc_ctimer0_clkdiv: MrccCtimer0Clkdiv, - mrcc_ctimer1_clksel: MrccCtimer1Clksel, - mrcc_ctimer1_clkdiv: MrccCtimer1Clkdiv, - mrcc_ctimer2_clksel: MrccCtimer2Clksel, - mrcc_ctimer2_clkdiv: MrccCtimer2Clkdiv, - mrcc_ctimer3_clksel: MrccCtimer3Clksel, - mrcc_ctimer3_clkdiv: MrccCtimer3Clkdiv, - mrcc_ctimer4_clksel: MrccCtimer4Clksel, - mrcc_ctimer4_clkdiv: MrccCtimer4Clkdiv, - _reserved33: [u8; 0x04], - mrcc_wwdt0_clkdiv: MrccWwdt0Clkdiv, - mrcc_flexio0_clksel: MrccFlexio0Clksel, - mrcc_flexio0_clkdiv: MrccFlexio0Clkdiv, - mrcc_lpi2c0_clksel: MrccLpi2c0Clksel, - mrcc_lpi2c0_clkdiv: MrccLpi2c0Clkdiv, - mrcc_lpi2c1_clksel: MrccLpi2c1Clksel, - mrcc_lpi2c1_clkdiv: MrccLpi2c1Clkdiv, - mrcc_lpspi0_clksel: MrccLpspi0Clksel, - mrcc_lpspi0_clkdiv: MrccLpspi0Clkdiv, - mrcc_lpspi1_clksel: MrccLpspi1Clksel, - mrcc_lpspi1_clkdiv: MrccLpspi1Clkdiv, - mrcc_lpuart0_clksel: MrccLpuart0Clksel, - mrcc_lpuart0_clkdiv: MrccLpuart0Clkdiv, - mrcc_lpuart1_clksel: MrccLpuart1Clksel, - mrcc_lpuart1_clkdiv: MrccLpuart1Clkdiv, - mrcc_lpuart2_clksel: MrccLpuart2Clksel, - mrcc_lpuart2_clkdiv: MrccLpuart2Clkdiv, - mrcc_lpuart3_clksel: MrccLpuart3Clksel, - mrcc_lpuart3_clkdiv: MrccLpuart3Clkdiv, - mrcc_lpuart4_clksel: MrccLpuart4Clksel, - mrcc_lpuart4_clkdiv: MrccLpuart4Clkdiv, - mrcc_usb0_clksel: MrccUsb0Clksel, - mrcc_usb0_clkdiv: MrccUsb0Clkdiv, - mrcc_lptmr0_clksel: MrccLptmr0Clksel, - mrcc_lptmr0_clkdiv: MrccLptmr0Clkdiv, - mrcc_ostimer0_clksel: MrccOstimer0Clksel, - _reserved59: [u8; 0x04], - mrcc_adc_clksel: MrccAdcClksel, - mrcc_adc_clkdiv: MrccAdcClkdiv, - _reserved61: [u8; 0x04], - mrcc_cmp0_func_clkdiv: MrccCmp0FuncClkdiv, - mrcc_cmp0_rr_clksel: MrccCmp0RrClksel, - mrcc_cmp0_rr_clkdiv: MrccCmp0RrClkdiv, - _reserved64: [u8; 0x04], - mrcc_cmp1_func_clkdiv: MrccCmp1FuncClkdiv, - mrcc_cmp1_rr_clksel: MrccCmp1RrClksel, - mrcc_cmp1_rr_clkdiv: MrccCmp1RrClkdiv, - _reserved67: [u8; 0x04], - mrcc_cmp2_func_clkdiv: MrccCmp2FuncClkdiv, - mrcc_cmp2_rr_clksel: MrccCmp2RrClksel, - mrcc_cmp2_rr_clkdiv: MrccCmp2RrClkdiv, - mrcc_dac0_clksel: MrccDac0Clksel, - mrcc_dac0_clkdiv: MrccDac0Clkdiv, - mrcc_flexcan0_clksel: MrccFlexcan0Clksel, - mrcc_flexcan0_clkdiv: MrccFlexcan0Clkdiv, - mrcc_flexcan1_clksel: MrccFlexcan1Clksel, - mrcc_flexcan1_clkdiv: MrccFlexcan1Clkdiv, - mrcc_lpi2c2_clksel: MrccLpi2c2Clksel, - mrcc_lpi2c2_clkdiv: MrccLpi2c2Clkdiv, - mrcc_lpi2c3_clksel: MrccLpi2c3Clksel, - mrcc_lpi2c3_clkdiv: MrccLpi2c3Clkdiv, - mrcc_lpuart5_clksel: MrccLpuart5Clksel, - mrcc_lpuart5_clkdiv: MrccLpuart5Clkdiv, - mrcc_dbg_trace_clksel: MrccDbgTraceClksel, - mrcc_dbg_trace_clkdiv: MrccDbgTraceClkdiv, - mrcc_clkout_clksel: MrccClkoutClksel, - mrcc_clkout_clkdiv: MrccClkoutClkdiv, - mrcc_systick_clksel: MrccSystickClksel, - mrcc_systick_clkdiv: MrccSystickClkdiv, -} -impl RegisterBlock { - #[doc = "0x00 - Peripheral Reset Control 0"] - #[inline(always)] - pub const fn mrcc_glb_rst0(&self) -> &MrccGlbRst0 { - &self.mrcc_glb_rst0 - } - #[doc = "0x04 - Peripheral Reset Control Set 0"] - #[inline(always)] - pub const fn mrcc_glb_rst0_set(&self) -> &MrccGlbRst0Set { - &self.mrcc_glb_rst0_set - } - #[doc = "0x08 - Peripheral Reset Control Clear 0"] - #[inline(always)] - pub const fn mrcc_glb_rst0_clr(&self) -> &MrccGlbRst0Clr { - &self.mrcc_glb_rst0_clr - } - #[doc = "0x10 - Peripheral Reset Control 1"] - #[inline(always)] - pub const fn mrcc_glb_rst1(&self) -> &MrccGlbRst1 { - &self.mrcc_glb_rst1 - } - #[doc = "0x14 - Peripheral Reset Control Set 1"] - #[inline(always)] - pub const fn mrcc_glb_rst1_set(&self) -> &MrccGlbRst1Set { - &self.mrcc_glb_rst1_set - } - #[doc = "0x18 - Peripheral Reset Control Clear 1"] - #[inline(always)] - pub const fn mrcc_glb_rst1_clr(&self) -> &MrccGlbRst1Clr { - &self.mrcc_glb_rst1_clr - } - #[doc = "0x20 - Peripheral Reset Control 2"] - #[inline(always)] - pub const fn mrcc_glb_rst2(&self) -> &MrccGlbRst2 { - &self.mrcc_glb_rst2 - } - #[doc = "0x24 - Peripheral Reset Control Set 2"] - #[inline(always)] - pub const fn mrcc_glb_rst2_set(&self) -> &MrccGlbRst2Set { - &self.mrcc_glb_rst2_set - } - #[doc = "0x28 - Peripheral Reset Control Clear 2"] - #[inline(always)] - pub const fn mrcc_glb_rst2_clr(&self) -> &MrccGlbRst2Clr { - &self.mrcc_glb_rst2_clr - } - #[doc = "0x40 - AHB Clock Control 0"] - #[inline(always)] - pub const fn mrcc_glb_cc0(&self) -> &MrccGlbCc0 { - &self.mrcc_glb_cc0 - } - #[doc = "0x44 - AHB Clock Control Set 0"] - #[inline(always)] - pub const fn mrcc_glb_cc0_set(&self) -> &MrccGlbCc0Set { - &self.mrcc_glb_cc0_set - } - #[doc = "0x48 - AHB Clock Control Clear 0"] - #[inline(always)] - pub const fn mrcc_glb_cc0_clr(&self) -> &MrccGlbCc0Clr { - &self.mrcc_glb_cc0_clr - } - #[doc = "0x50 - AHB Clock Control 1"] - #[inline(always)] - pub const fn mrcc_glb_cc1(&self) -> &MrccGlbCc1 { - &self.mrcc_glb_cc1 - } - #[doc = "0x54 - AHB Clock Control Set 1"] - #[inline(always)] - pub const fn mrcc_glb_cc1_set(&self) -> &MrccGlbCc1Set { - &self.mrcc_glb_cc1_set - } - #[doc = "0x58 - AHB Clock Control Clear 1"] - #[inline(always)] - pub const fn mrcc_glb_cc1_clr(&self) -> &MrccGlbCc1Clr { - &self.mrcc_glb_cc1_clr - } - #[doc = "0x60 - AHB Clock Control 2"] - #[inline(always)] - pub const fn mrcc_glb_cc2(&self) -> &MrccGlbCc2 { - &self.mrcc_glb_cc2 - } - #[doc = "0x64 - AHB Clock Control Set 2"] - #[inline(always)] - pub const fn mrcc_glb_cc2_set(&self) -> &MrccGlbCc2Set { - &self.mrcc_glb_cc2_set - } - #[doc = "0x68 - AHB Clock Control Clear 2"] - #[inline(always)] - pub const fn mrcc_glb_cc2_clr(&self) -> &MrccGlbCc2Clr { - &self.mrcc_glb_cc2_clr - } - #[doc = "0x80 - Control Automatic Clock Gating 0"] - #[inline(always)] - pub const fn mrcc_glb_acc0(&self) -> &MrccGlbAcc0 { - &self.mrcc_glb_acc0 - } - #[doc = "0x84 - Control Automatic Clock Gating 1"] - #[inline(always)] - pub const fn mrcc_glb_acc1(&self) -> &MrccGlbAcc1 { - &self.mrcc_glb_acc1 - } - #[doc = "0x88 - Control Automatic Clock Gating 2"] - #[inline(always)] - pub const fn mrcc_glb_acc2(&self) -> &MrccGlbAcc2 { - &self.mrcc_glb_acc2 - } - #[doc = "0xa0 - I3C0_FCLK clock selection control"] - #[inline(always)] - pub const fn mrcc_i3c0_fclk_clksel(&self) -> &MrccI3c0FclkClksel { - &self.mrcc_i3c0_fclk_clksel - } - #[doc = "0xa4 - I3C0_FCLK clock divider control"] - #[inline(always)] - pub const fn mrcc_i3c0_fclk_clkdiv(&self) -> &MrccI3c0FclkClkdiv { - &self.mrcc_i3c0_fclk_clkdiv - } - #[doc = "0xa8 - CTIMER0 clock selection control"] - #[inline(always)] - pub const fn mrcc_ctimer0_clksel(&self) -> &MrccCtimer0Clksel { - &self.mrcc_ctimer0_clksel - } - #[doc = "0xac - CTIMER0 clock divider control"] - #[inline(always)] - pub const fn mrcc_ctimer0_clkdiv(&self) -> &MrccCtimer0Clkdiv { - &self.mrcc_ctimer0_clkdiv - } - #[doc = "0xb0 - CTIMER1 clock selection control"] - #[inline(always)] - pub const fn mrcc_ctimer1_clksel(&self) -> &MrccCtimer1Clksel { - &self.mrcc_ctimer1_clksel - } - #[doc = "0xb4 - CTIMER1 clock divider control"] - #[inline(always)] - pub const fn mrcc_ctimer1_clkdiv(&self) -> &MrccCtimer1Clkdiv { - &self.mrcc_ctimer1_clkdiv - } - #[doc = "0xb8 - CTIMER2 clock selection control"] - #[inline(always)] - pub const fn mrcc_ctimer2_clksel(&self) -> &MrccCtimer2Clksel { - &self.mrcc_ctimer2_clksel - } - #[doc = "0xbc - CTIMER2 clock divider control"] - #[inline(always)] - pub const fn mrcc_ctimer2_clkdiv(&self) -> &MrccCtimer2Clkdiv { - &self.mrcc_ctimer2_clkdiv - } - #[doc = "0xc0 - CTIMER3 clock selection control"] - #[inline(always)] - pub const fn mrcc_ctimer3_clksel(&self) -> &MrccCtimer3Clksel { - &self.mrcc_ctimer3_clksel - } - #[doc = "0xc4 - CTIMER3 clock divider control"] - #[inline(always)] - pub const fn mrcc_ctimer3_clkdiv(&self) -> &MrccCtimer3Clkdiv { - &self.mrcc_ctimer3_clkdiv - } - #[doc = "0xc8 - CTIMER4 clock selection control"] - #[inline(always)] - pub const fn mrcc_ctimer4_clksel(&self) -> &MrccCtimer4Clksel { - &self.mrcc_ctimer4_clksel - } - #[doc = "0xcc - CTIMER4 clock divider control"] - #[inline(always)] - pub const fn mrcc_ctimer4_clkdiv(&self) -> &MrccCtimer4Clkdiv { - &self.mrcc_ctimer4_clkdiv - } - #[doc = "0xd4 - WWDT0 clock divider control"] - #[inline(always)] - pub const fn mrcc_wwdt0_clkdiv(&self) -> &MrccWwdt0Clkdiv { - &self.mrcc_wwdt0_clkdiv - } - #[doc = "0xd8 - FLEXIO0 clock selection control"] - #[inline(always)] - pub const fn mrcc_flexio0_clksel(&self) -> &MrccFlexio0Clksel { - &self.mrcc_flexio0_clksel - } - #[doc = "0xdc - FLEXIO0 clock divider control"] - #[inline(always)] - pub const fn mrcc_flexio0_clkdiv(&self) -> &MrccFlexio0Clkdiv { - &self.mrcc_flexio0_clkdiv - } - #[doc = "0xe0 - LPI2C0 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpi2c0_clksel(&self) -> &MrccLpi2c0Clksel { - &self.mrcc_lpi2c0_clksel - } - #[doc = "0xe4 - LPI2C0 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpi2c0_clkdiv(&self) -> &MrccLpi2c0Clkdiv { - &self.mrcc_lpi2c0_clkdiv - } - #[doc = "0xe8 - LPI2C1 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpi2c1_clksel(&self) -> &MrccLpi2c1Clksel { - &self.mrcc_lpi2c1_clksel - } - #[doc = "0xec - LPI2C1 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpi2c1_clkdiv(&self) -> &MrccLpi2c1Clkdiv { - &self.mrcc_lpi2c1_clkdiv - } - #[doc = "0xf0 - LPSPI0 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpspi0_clksel(&self) -> &MrccLpspi0Clksel { - &self.mrcc_lpspi0_clksel - } - #[doc = "0xf4 - LPSPI0 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpspi0_clkdiv(&self) -> &MrccLpspi0Clkdiv { - &self.mrcc_lpspi0_clkdiv - } - #[doc = "0xf8 - LPSPI1 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpspi1_clksel(&self) -> &MrccLpspi1Clksel { - &self.mrcc_lpspi1_clksel - } - #[doc = "0xfc - LPSPI1 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpspi1_clkdiv(&self) -> &MrccLpspi1Clkdiv { - &self.mrcc_lpspi1_clkdiv - } - #[doc = "0x100 - LPUART0 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpuart0_clksel(&self) -> &MrccLpuart0Clksel { - &self.mrcc_lpuart0_clksel - } - #[doc = "0x104 - LPUART0 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpuart0_clkdiv(&self) -> &MrccLpuart0Clkdiv { - &self.mrcc_lpuart0_clkdiv - } - #[doc = "0x108 - LPUART1 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpuart1_clksel(&self) -> &MrccLpuart1Clksel { - &self.mrcc_lpuart1_clksel - } - #[doc = "0x10c - LPUART1 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpuart1_clkdiv(&self) -> &MrccLpuart1Clkdiv { - &self.mrcc_lpuart1_clkdiv - } - #[doc = "0x110 - LPUART2 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpuart2_clksel(&self) -> &MrccLpuart2Clksel { - &self.mrcc_lpuart2_clksel - } - #[doc = "0x114 - LPUART2 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpuart2_clkdiv(&self) -> &MrccLpuart2Clkdiv { - &self.mrcc_lpuart2_clkdiv - } - #[doc = "0x118 - LPUART3 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpuart3_clksel(&self) -> &MrccLpuart3Clksel { - &self.mrcc_lpuart3_clksel - } - #[doc = "0x11c - LPUART3 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpuart3_clkdiv(&self) -> &MrccLpuart3Clkdiv { - &self.mrcc_lpuart3_clkdiv - } - #[doc = "0x120 - LPUART4 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpuart4_clksel(&self) -> &MrccLpuart4Clksel { - &self.mrcc_lpuart4_clksel - } - #[doc = "0x124 - LPUART4 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpuart4_clkdiv(&self) -> &MrccLpuart4Clkdiv { - &self.mrcc_lpuart4_clkdiv - } - #[doc = "0x128 - USB0 clock selection control"] - #[inline(always)] - pub const fn mrcc_usb0_clksel(&self) -> &MrccUsb0Clksel { - &self.mrcc_usb0_clksel - } - #[doc = "0x12c - USB0 clock divider control"] - #[inline(always)] - pub const fn mrcc_usb0_clkdiv(&self) -> &MrccUsb0Clkdiv { - &self.mrcc_usb0_clkdiv - } - #[doc = "0x130 - LPTMR0 clock selection control"] - #[inline(always)] - pub const fn mrcc_lptmr0_clksel(&self) -> &MrccLptmr0Clksel { - &self.mrcc_lptmr0_clksel - } - #[doc = "0x134 - LPTMR0 clock divider control"] - #[inline(always)] - pub const fn mrcc_lptmr0_clkdiv(&self) -> &MrccLptmr0Clkdiv { - &self.mrcc_lptmr0_clkdiv - } - #[doc = "0x138 - OSTIMER0 clock selection control"] - #[inline(always)] - pub const fn mrcc_ostimer0_clksel(&self) -> &MrccOstimer0Clksel { - &self.mrcc_ostimer0_clksel - } - #[doc = "0x140 - ADCx clock selection control"] - #[inline(always)] - pub const fn mrcc_adc_clksel(&self) -> &MrccAdcClksel { - &self.mrcc_adc_clksel - } - #[doc = "0x144 - ADCx clock divider control"] - #[inline(always)] - pub const fn mrcc_adc_clkdiv(&self) -> &MrccAdcClkdiv { - &self.mrcc_adc_clkdiv - } - #[doc = "0x14c - CMP0_FUNC clock divider control"] - #[inline(always)] - pub const fn mrcc_cmp0_func_clkdiv(&self) -> &MrccCmp0FuncClkdiv { - &self.mrcc_cmp0_func_clkdiv - } - #[doc = "0x150 - CMP0_RR clock selection control"] - #[inline(always)] - pub const fn mrcc_cmp0_rr_clksel(&self) -> &MrccCmp0RrClksel { - &self.mrcc_cmp0_rr_clksel - } - #[doc = "0x154 - CMP0_RR clock divider control"] - #[inline(always)] - pub const fn mrcc_cmp0_rr_clkdiv(&self) -> &MrccCmp0RrClkdiv { - &self.mrcc_cmp0_rr_clkdiv - } - #[doc = "0x15c - CMP1_FUNC clock divider control"] - #[inline(always)] - pub const fn mrcc_cmp1_func_clkdiv(&self) -> &MrccCmp1FuncClkdiv { - &self.mrcc_cmp1_func_clkdiv - } - #[doc = "0x160 - CMP1_RR clock selection control"] - #[inline(always)] - pub const fn mrcc_cmp1_rr_clksel(&self) -> &MrccCmp1RrClksel { - &self.mrcc_cmp1_rr_clksel - } - #[doc = "0x164 - CMP1_RR clock divider control"] - #[inline(always)] - pub const fn mrcc_cmp1_rr_clkdiv(&self) -> &MrccCmp1RrClkdiv { - &self.mrcc_cmp1_rr_clkdiv - } - #[doc = "0x16c - CMP2_FUNC clock divider control"] - #[inline(always)] - pub const fn mrcc_cmp2_func_clkdiv(&self) -> &MrccCmp2FuncClkdiv { - &self.mrcc_cmp2_func_clkdiv - } - #[doc = "0x170 - CMP2_RR clock selection control"] - #[inline(always)] - pub const fn mrcc_cmp2_rr_clksel(&self) -> &MrccCmp2RrClksel { - &self.mrcc_cmp2_rr_clksel - } - #[doc = "0x174 - CMP2_RR clock divider control"] - #[inline(always)] - pub const fn mrcc_cmp2_rr_clkdiv(&self) -> &MrccCmp2RrClkdiv { - &self.mrcc_cmp2_rr_clkdiv - } - #[doc = "0x178 - DAC0 clock selection control"] - #[inline(always)] - pub const fn mrcc_dac0_clksel(&self) -> &MrccDac0Clksel { - &self.mrcc_dac0_clksel - } - #[doc = "0x17c - DAC0 clock divider control"] - #[inline(always)] - pub const fn mrcc_dac0_clkdiv(&self) -> &MrccDac0Clkdiv { - &self.mrcc_dac0_clkdiv - } - #[doc = "0x180 - FLEXCAN0 clock selection control"] - #[inline(always)] - pub const fn mrcc_flexcan0_clksel(&self) -> &MrccFlexcan0Clksel { - &self.mrcc_flexcan0_clksel - } - #[doc = "0x184 - FLEXCAN0 clock divider control"] - #[inline(always)] - pub const fn mrcc_flexcan0_clkdiv(&self) -> &MrccFlexcan0Clkdiv { - &self.mrcc_flexcan0_clkdiv - } - #[doc = "0x188 - FLEXCAN1 clock selection control"] - #[inline(always)] - pub const fn mrcc_flexcan1_clksel(&self) -> &MrccFlexcan1Clksel { - &self.mrcc_flexcan1_clksel - } - #[doc = "0x18c - FLEXCAN1 clock divider control"] - #[inline(always)] - pub const fn mrcc_flexcan1_clkdiv(&self) -> &MrccFlexcan1Clkdiv { - &self.mrcc_flexcan1_clkdiv - } - #[doc = "0x190 - LPI2C2 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpi2c2_clksel(&self) -> &MrccLpi2c2Clksel { - &self.mrcc_lpi2c2_clksel - } - #[doc = "0x194 - LPI2C2 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpi2c2_clkdiv(&self) -> &MrccLpi2c2Clkdiv { - &self.mrcc_lpi2c2_clkdiv - } - #[doc = "0x198 - LPI2C3 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpi2c3_clksel(&self) -> &MrccLpi2c3Clksel { - &self.mrcc_lpi2c3_clksel - } - #[doc = "0x19c - LPI2C3 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpi2c3_clkdiv(&self) -> &MrccLpi2c3Clkdiv { - &self.mrcc_lpi2c3_clkdiv - } - #[doc = "0x1a0 - LPUART5 clock selection control"] - #[inline(always)] - pub const fn mrcc_lpuart5_clksel(&self) -> &MrccLpuart5Clksel { - &self.mrcc_lpuart5_clksel - } - #[doc = "0x1a4 - LPUART5 clock divider control"] - #[inline(always)] - pub const fn mrcc_lpuart5_clkdiv(&self) -> &MrccLpuart5Clkdiv { - &self.mrcc_lpuart5_clkdiv - } - #[doc = "0x1a8 - DBG_TRACE clock selection control"] - #[inline(always)] - pub const fn mrcc_dbg_trace_clksel(&self) -> &MrccDbgTraceClksel { - &self.mrcc_dbg_trace_clksel - } - #[doc = "0x1ac - DBG_TRACE clock divider control"] - #[inline(always)] - pub const fn mrcc_dbg_trace_clkdiv(&self) -> &MrccDbgTraceClkdiv { - &self.mrcc_dbg_trace_clkdiv - } - #[doc = "0x1b0 - CLKOUT clock selection control"] - #[inline(always)] - pub const fn mrcc_clkout_clksel(&self) -> &MrccClkoutClksel { - &self.mrcc_clkout_clksel - } - #[doc = "0x1b4 - CLKOUT clock divider control"] - #[inline(always)] - pub const fn mrcc_clkout_clkdiv(&self) -> &MrccClkoutClkdiv { - &self.mrcc_clkout_clkdiv - } - #[doc = "0x1b8 - SYSTICK clock selection control"] - #[inline(always)] - pub const fn mrcc_systick_clksel(&self) -> &MrccSystickClksel { - &self.mrcc_systick_clksel - } - #[doc = "0x1bc - SYSTICK clock divider control"] - #[inline(always)] - pub const fn mrcc_systick_clkdiv(&self) -> &MrccSystickClkdiv { - &self.mrcc_systick_clkdiv - } -} -#[doc = "MRCC_GLB_RST0 (rw) register accessor: Peripheral Reset Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0`] module"] -#[doc(alias = "MRCC_GLB_RST0")] -pub type MrccGlbRst0 = crate::Reg; -#[doc = "Peripheral Reset Control 0"] -pub mod mrcc_glb_rst0; -#[doc = "MRCC_GLB_RST0_SET (w) register accessor: Peripheral Reset Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0_set`] module"] -#[doc(alias = "MRCC_GLB_RST0_SET")] -pub type MrccGlbRst0Set = crate::Reg; -#[doc = "Peripheral Reset Control Set 0"] -pub mod mrcc_glb_rst0_set; -#[doc = "MRCC_GLB_RST0_CLR (w) register accessor: Peripheral Reset Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst0_clr`] module"] -#[doc(alias = "MRCC_GLB_RST0_CLR")] -pub type MrccGlbRst0Clr = crate::Reg; -#[doc = "Peripheral Reset Control Clear 0"] -pub mod mrcc_glb_rst0_clr; -#[doc = "MRCC_GLB_RST1 (rw) register accessor: Peripheral Reset Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1`] module"] -#[doc(alias = "MRCC_GLB_RST1")] -pub type MrccGlbRst1 = crate::Reg; -#[doc = "Peripheral Reset Control 1"] -pub mod mrcc_glb_rst1; -#[doc = "MRCC_GLB_RST1_SET (w) register accessor: Peripheral Reset Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1_set`] module"] -#[doc(alias = "MRCC_GLB_RST1_SET")] -pub type MrccGlbRst1Set = crate::Reg; -#[doc = "Peripheral Reset Control Set 1"] -pub mod mrcc_glb_rst1_set; -#[doc = "MRCC_GLB_RST1_CLR (w) register accessor: Peripheral Reset Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst1_clr`] module"] -#[doc(alias = "MRCC_GLB_RST1_CLR")] -pub type MrccGlbRst1Clr = crate::Reg; -#[doc = "Peripheral Reset Control Clear 1"] -pub mod mrcc_glb_rst1_clr; -#[doc = "MRCC_GLB_RST2 (rw) register accessor: Peripheral Reset Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2`] module"] -#[doc(alias = "MRCC_GLB_RST2")] -pub type MrccGlbRst2 = crate::Reg; -#[doc = "Peripheral Reset Control 2"] -pub mod mrcc_glb_rst2; -#[doc = "MRCC_GLB_RST2_SET (w) register accessor: Peripheral Reset Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2_set`] module"] -#[doc(alias = "MRCC_GLB_RST2_SET")] -pub type MrccGlbRst2Set = crate::Reg; -#[doc = "Peripheral Reset Control Set 2"] -pub mod mrcc_glb_rst2_set; -#[doc = "MRCC_GLB_RST2_CLR (w) register accessor: Peripheral Reset Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_rst2_clr`] module"] -#[doc(alias = "MRCC_GLB_RST2_CLR")] -pub type MrccGlbRst2Clr = crate::Reg; -#[doc = "Peripheral Reset Control Clear 2"] -pub mod mrcc_glb_rst2_clr; -#[doc = "MRCC_GLB_CC0 (rw) register accessor: AHB Clock Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0`] module"] -#[doc(alias = "MRCC_GLB_CC0")] -pub type MrccGlbCc0 = crate::Reg; -#[doc = "AHB Clock Control 0"] -pub mod mrcc_glb_cc0; -#[doc = "MRCC_GLB_CC0_SET (w) register accessor: AHB Clock Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0_set`] module"] -#[doc(alias = "MRCC_GLB_CC0_SET")] -pub type MrccGlbCc0Set = crate::Reg; -#[doc = "AHB Clock Control Set 0"] -pub mod mrcc_glb_cc0_set; -#[doc = "MRCC_GLB_CC0_CLR (w) register accessor: AHB Clock Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc0_clr`] module"] -#[doc(alias = "MRCC_GLB_CC0_CLR")] -pub type MrccGlbCc0Clr = crate::Reg; -#[doc = "AHB Clock Control Clear 0"] -pub mod mrcc_glb_cc0_clr; -#[doc = "MRCC_GLB_CC1 (rw) register accessor: AHB Clock Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1`] module"] -#[doc(alias = "MRCC_GLB_CC1")] -pub type MrccGlbCc1 = crate::Reg; -#[doc = "AHB Clock Control 1"] -pub mod mrcc_glb_cc1; -#[doc = "MRCC_GLB_CC1_SET (w) register accessor: AHB Clock Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1_set`] module"] -#[doc(alias = "MRCC_GLB_CC1_SET")] -pub type MrccGlbCc1Set = crate::Reg; -#[doc = "AHB Clock Control Set 1"] -pub mod mrcc_glb_cc1_set; -#[doc = "MRCC_GLB_CC1_CLR (w) register accessor: AHB Clock Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc1_clr`] module"] -#[doc(alias = "MRCC_GLB_CC1_CLR")] -pub type MrccGlbCc1Clr = crate::Reg; -#[doc = "AHB Clock Control Clear 1"] -pub mod mrcc_glb_cc1_clr; -#[doc = "MRCC_GLB_CC2 (rw) register accessor: AHB Clock Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2`] module"] -#[doc(alias = "MRCC_GLB_CC2")] -pub type MrccGlbCc2 = crate::Reg; -#[doc = "AHB Clock Control 2"] -pub mod mrcc_glb_cc2; -#[doc = "MRCC_GLB_CC2_SET (w) register accessor: AHB Clock Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2_set`] module"] -#[doc(alias = "MRCC_GLB_CC2_SET")] -pub type MrccGlbCc2Set = crate::Reg; -#[doc = "AHB Clock Control Set 2"] -pub mod mrcc_glb_cc2_set; -#[doc = "MRCC_GLB_CC2_CLR (w) register accessor: AHB Clock Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_cc2_clr`] module"] -#[doc(alias = "MRCC_GLB_CC2_CLR")] -pub type MrccGlbCc2Clr = crate::Reg; -#[doc = "AHB Clock Control Clear 2"] -pub mod mrcc_glb_cc2_clr; -#[doc = "MRCC_GLB_ACC0 (rw) register accessor: Control Automatic Clock Gating 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc0`] module"] -#[doc(alias = "MRCC_GLB_ACC0")] -pub type MrccGlbAcc0 = crate::Reg; -#[doc = "Control Automatic Clock Gating 0"] -pub mod mrcc_glb_acc0; -#[doc = "MRCC_GLB_ACC1 (rw) register accessor: Control Automatic Clock Gating 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc1`] module"] -#[doc(alias = "MRCC_GLB_ACC1")] -pub type MrccGlbAcc1 = crate::Reg; -#[doc = "Control Automatic Clock Gating 1"] -pub mod mrcc_glb_acc1; -#[doc = "MRCC_GLB_ACC2 (rw) register accessor: Control Automatic Clock Gating 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_glb_acc2`] module"] -#[doc(alias = "MRCC_GLB_ACC2")] -pub type MrccGlbAcc2 = crate::Reg; -#[doc = "Control Automatic Clock Gating 2"] -pub mod mrcc_glb_acc2; -#[doc = "MRCC_I3C0_FCLK_CLKSEL (rw) register accessor: I3C0_FCLK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_i3c0_fclk_clksel`] module"] -#[doc(alias = "MRCC_I3C0_FCLK_CLKSEL")] -pub type MrccI3c0FclkClksel = crate::Reg; -#[doc = "I3C0_FCLK clock selection control"] -pub mod mrcc_i3c0_fclk_clksel; -#[doc = "MRCC_I3C0_FCLK_CLKDIV (rw) register accessor: I3C0_FCLK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_i3c0_fclk_clkdiv`] module"] -#[doc(alias = "MRCC_I3C0_FCLK_CLKDIV")] -pub type MrccI3c0FclkClkdiv = crate::Reg; -#[doc = "I3C0_FCLK clock divider control"] -pub mod mrcc_i3c0_fclk_clkdiv; -#[doc = "MRCC_CTIMER0_CLKSEL (rw) register accessor: CTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer0_clksel`] module"] -#[doc(alias = "MRCC_CTIMER0_CLKSEL")] -pub type MrccCtimer0Clksel = crate::Reg; -#[doc = "CTIMER0 clock selection control"] -pub mod mrcc_ctimer0_clksel; -#[doc = "MRCC_CTIMER0_CLKDIV (rw) register accessor: CTIMER0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer0_clkdiv`] module"] -#[doc(alias = "MRCC_CTIMER0_CLKDIV")] -pub type MrccCtimer0Clkdiv = crate::Reg; -#[doc = "CTIMER0 clock divider control"] -pub mod mrcc_ctimer0_clkdiv; -#[doc = "MRCC_CTIMER1_CLKSEL (rw) register accessor: CTIMER1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer1_clksel`] module"] -#[doc(alias = "MRCC_CTIMER1_CLKSEL")] -pub type MrccCtimer1Clksel = crate::Reg; -#[doc = "CTIMER1 clock selection control"] -pub mod mrcc_ctimer1_clksel; -#[doc = "MRCC_CTIMER1_CLKDIV (rw) register accessor: CTIMER1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer1_clkdiv`] module"] -#[doc(alias = "MRCC_CTIMER1_CLKDIV")] -pub type MrccCtimer1Clkdiv = crate::Reg; -#[doc = "CTIMER1 clock divider control"] -pub mod mrcc_ctimer1_clkdiv; -#[doc = "MRCC_CTIMER2_CLKSEL (rw) register accessor: CTIMER2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer2_clksel`] module"] -#[doc(alias = "MRCC_CTIMER2_CLKSEL")] -pub type MrccCtimer2Clksel = crate::Reg; -#[doc = "CTIMER2 clock selection control"] -pub mod mrcc_ctimer2_clksel; -#[doc = "MRCC_CTIMER2_CLKDIV (rw) register accessor: CTIMER2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer2_clkdiv`] module"] -#[doc(alias = "MRCC_CTIMER2_CLKDIV")] -pub type MrccCtimer2Clkdiv = crate::Reg; -#[doc = "CTIMER2 clock divider control"] -pub mod mrcc_ctimer2_clkdiv; -#[doc = "MRCC_CTIMER3_CLKSEL (rw) register accessor: CTIMER3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer3_clksel`] module"] -#[doc(alias = "MRCC_CTIMER3_CLKSEL")] -pub type MrccCtimer3Clksel = crate::Reg; -#[doc = "CTIMER3 clock selection control"] -pub mod mrcc_ctimer3_clksel; -#[doc = "MRCC_CTIMER3_CLKDIV (rw) register accessor: CTIMER3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer3_clkdiv`] module"] -#[doc(alias = "MRCC_CTIMER3_CLKDIV")] -pub type MrccCtimer3Clkdiv = crate::Reg; -#[doc = "CTIMER3 clock divider control"] -pub mod mrcc_ctimer3_clkdiv; -#[doc = "MRCC_CTIMER4_CLKSEL (rw) register accessor: CTIMER4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer4_clksel`] module"] -#[doc(alias = "MRCC_CTIMER4_CLKSEL")] -pub type MrccCtimer4Clksel = crate::Reg; -#[doc = "CTIMER4 clock selection control"] -pub mod mrcc_ctimer4_clksel; -#[doc = "MRCC_CTIMER4_CLKDIV (rw) register accessor: CTIMER4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ctimer4_clkdiv`] module"] -#[doc(alias = "MRCC_CTIMER4_CLKDIV")] -pub type MrccCtimer4Clkdiv = crate::Reg; -#[doc = "CTIMER4 clock divider control"] -pub mod mrcc_ctimer4_clkdiv; -#[doc = "MRCC_WWDT0_CLKDIV (rw) register accessor: WWDT0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_wwdt0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_wwdt0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_wwdt0_clkdiv`] module"] -#[doc(alias = "MRCC_WWDT0_CLKDIV")] -pub type MrccWwdt0Clkdiv = crate::Reg; -#[doc = "WWDT0 clock divider control"] -pub mod mrcc_wwdt0_clkdiv; -#[doc = "MRCC_FLEXIO0_CLKSEL (rw) register accessor: FLEXIO0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexio0_clksel`] module"] -#[doc(alias = "MRCC_FLEXIO0_CLKSEL")] -pub type MrccFlexio0Clksel = crate::Reg; -#[doc = "FLEXIO0 clock selection control"] -pub mod mrcc_flexio0_clksel; -#[doc = "MRCC_FLEXIO0_CLKDIV (rw) register accessor: FLEXIO0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexio0_clkdiv`] module"] -#[doc(alias = "MRCC_FLEXIO0_CLKDIV")] -pub type MrccFlexio0Clkdiv = crate::Reg; -#[doc = "FLEXIO0 clock divider control"] -pub mod mrcc_flexio0_clkdiv; -#[doc = "MRCC_LPI2C0_CLKSEL (rw) register accessor: LPI2C0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c0_clksel`] module"] -#[doc(alias = "MRCC_LPI2C0_CLKSEL")] -pub type MrccLpi2c0Clksel = crate::Reg; -#[doc = "LPI2C0 clock selection control"] -pub mod mrcc_lpi2c0_clksel; -#[doc = "MRCC_LPI2C0_CLKDIV (rw) register accessor: LPI2C0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c0_clkdiv`] module"] -#[doc(alias = "MRCC_LPI2C0_CLKDIV")] -pub type MrccLpi2c0Clkdiv = crate::Reg; -#[doc = "LPI2C0 clock divider control"] -pub mod mrcc_lpi2c0_clkdiv; -#[doc = "MRCC_LPI2C1_CLKSEL (rw) register accessor: LPI2C1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c1_clksel`] module"] -#[doc(alias = "MRCC_LPI2C1_CLKSEL")] -pub type MrccLpi2c1Clksel = crate::Reg; -#[doc = "LPI2C1 clock selection control"] -pub mod mrcc_lpi2c1_clksel; -#[doc = "MRCC_LPI2C1_CLKDIV (rw) register accessor: LPI2C1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c1_clkdiv`] module"] -#[doc(alias = "MRCC_LPI2C1_CLKDIV")] -pub type MrccLpi2c1Clkdiv = crate::Reg; -#[doc = "LPI2C1 clock divider control"] -pub mod mrcc_lpi2c1_clkdiv; -#[doc = "MRCC_LPSPI0_CLKSEL (rw) register accessor: LPSPI0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi0_clksel`] module"] -#[doc(alias = "MRCC_LPSPI0_CLKSEL")] -pub type MrccLpspi0Clksel = crate::Reg; -#[doc = "LPSPI0 clock selection control"] -pub mod mrcc_lpspi0_clksel; -#[doc = "MRCC_LPSPI0_CLKDIV (rw) register accessor: LPSPI0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi0_clkdiv`] module"] -#[doc(alias = "MRCC_LPSPI0_CLKDIV")] -pub type MrccLpspi0Clkdiv = crate::Reg; -#[doc = "LPSPI0 clock divider control"] -pub mod mrcc_lpspi0_clkdiv; -#[doc = "MRCC_LPSPI1_CLKSEL (rw) register accessor: LPSPI1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi1_clksel`] module"] -#[doc(alias = "MRCC_LPSPI1_CLKSEL")] -pub type MrccLpspi1Clksel = crate::Reg; -#[doc = "LPSPI1 clock selection control"] -pub mod mrcc_lpspi1_clksel; -#[doc = "MRCC_LPSPI1_CLKDIV (rw) register accessor: LPSPI1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpspi1_clkdiv`] module"] -#[doc(alias = "MRCC_LPSPI1_CLKDIV")] -pub type MrccLpspi1Clkdiv = crate::Reg; -#[doc = "LPSPI1 clock divider control"] -pub mod mrcc_lpspi1_clkdiv; -#[doc = "MRCC_LPUART0_CLKSEL (rw) register accessor: LPUART0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart0_clksel`] module"] -#[doc(alias = "MRCC_LPUART0_CLKSEL")] -pub type MrccLpuart0Clksel = crate::Reg; -#[doc = "LPUART0 clock selection control"] -pub mod mrcc_lpuart0_clksel; -#[doc = "MRCC_LPUART0_CLKDIV (rw) register accessor: LPUART0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart0_clkdiv`] module"] -#[doc(alias = "MRCC_LPUART0_CLKDIV")] -pub type MrccLpuart0Clkdiv = crate::Reg; -#[doc = "LPUART0 clock divider control"] -pub mod mrcc_lpuart0_clkdiv; -#[doc = "MRCC_LPUART1_CLKSEL (rw) register accessor: LPUART1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart1_clksel`] module"] -#[doc(alias = "MRCC_LPUART1_CLKSEL")] -pub type MrccLpuart1Clksel = crate::Reg; -#[doc = "LPUART1 clock selection control"] -pub mod mrcc_lpuart1_clksel; -#[doc = "MRCC_LPUART1_CLKDIV (rw) register accessor: LPUART1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart1_clkdiv`] module"] -#[doc(alias = "MRCC_LPUART1_CLKDIV")] -pub type MrccLpuart1Clkdiv = crate::Reg; -#[doc = "LPUART1 clock divider control"] -pub mod mrcc_lpuart1_clkdiv; -#[doc = "MRCC_LPUART2_CLKSEL (rw) register accessor: LPUART2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart2_clksel`] module"] -#[doc(alias = "MRCC_LPUART2_CLKSEL")] -pub type MrccLpuart2Clksel = crate::Reg; -#[doc = "LPUART2 clock selection control"] -pub mod mrcc_lpuart2_clksel; -#[doc = "MRCC_LPUART2_CLKDIV (rw) register accessor: LPUART2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart2_clkdiv`] module"] -#[doc(alias = "MRCC_LPUART2_CLKDIV")] -pub type MrccLpuart2Clkdiv = crate::Reg; -#[doc = "LPUART2 clock divider control"] -pub mod mrcc_lpuart2_clkdiv; -#[doc = "MRCC_LPUART3_CLKSEL (rw) register accessor: LPUART3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart3_clksel`] module"] -#[doc(alias = "MRCC_LPUART3_CLKSEL")] -pub type MrccLpuart3Clksel = crate::Reg; -#[doc = "LPUART3 clock selection control"] -pub mod mrcc_lpuart3_clksel; -#[doc = "MRCC_LPUART3_CLKDIV (rw) register accessor: LPUART3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart3_clkdiv`] module"] -#[doc(alias = "MRCC_LPUART3_CLKDIV")] -pub type MrccLpuart3Clkdiv = crate::Reg; -#[doc = "LPUART3 clock divider control"] -pub mod mrcc_lpuart3_clkdiv; -#[doc = "MRCC_LPUART4_CLKSEL (rw) register accessor: LPUART4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart4_clksel`] module"] -#[doc(alias = "MRCC_LPUART4_CLKSEL")] -pub type MrccLpuart4Clksel = crate::Reg; -#[doc = "LPUART4 clock selection control"] -pub mod mrcc_lpuart4_clksel; -#[doc = "MRCC_LPUART4_CLKDIV (rw) register accessor: LPUART4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart4_clkdiv`] module"] -#[doc(alias = "MRCC_LPUART4_CLKDIV")] -pub type MrccLpuart4Clkdiv = crate::Reg; -#[doc = "LPUART4 clock divider control"] -pub mod mrcc_lpuart4_clkdiv; -#[doc = "MRCC_USB0_CLKSEL (rw) register accessor: USB0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_usb0_clksel`] module"] -#[doc(alias = "MRCC_USB0_CLKSEL")] -pub type MrccUsb0Clksel = crate::Reg; -#[doc = "USB0 clock selection control"] -pub mod mrcc_usb0_clksel; -#[doc = "MRCC_USB0_CLKDIV (rw) register accessor: USB0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_usb0_clkdiv`] module"] -#[doc(alias = "MRCC_USB0_CLKDIV")] -pub type MrccUsb0Clkdiv = crate::Reg; -#[doc = "USB0 clock divider control"] -pub mod mrcc_usb0_clkdiv; -#[doc = "MRCC_LPTMR0_CLKSEL (rw) register accessor: LPTMR0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lptmr0_clksel`] module"] -#[doc(alias = "MRCC_LPTMR0_CLKSEL")] -pub type MrccLptmr0Clksel = crate::Reg; -#[doc = "LPTMR0 clock selection control"] -pub mod mrcc_lptmr0_clksel; -#[doc = "MRCC_LPTMR0_CLKDIV (rw) register accessor: LPTMR0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lptmr0_clkdiv`] module"] -#[doc(alias = "MRCC_LPTMR0_CLKDIV")] -pub type MrccLptmr0Clkdiv = crate::Reg; -#[doc = "LPTMR0 clock divider control"] -pub mod mrcc_lptmr0_clkdiv; -#[doc = "MRCC_OSTIMER0_CLKSEL (rw) register accessor: OSTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ostimer0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ostimer0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_ostimer0_clksel`] module"] -#[doc(alias = "MRCC_OSTIMER0_CLKSEL")] -pub type MrccOstimer0Clksel = crate::Reg; -#[doc = "OSTIMER0 clock selection control"] -pub mod mrcc_ostimer0_clksel; -#[doc = "MRCC_ADC_CLKSEL (rw) register accessor: ADCx clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_adc_clksel`] module"] -#[doc(alias = "MRCC_ADC_CLKSEL")] -pub type MrccAdcClksel = crate::Reg; -#[doc = "ADCx clock selection control"] -pub mod mrcc_adc_clksel; -#[doc = "MRCC_ADC_CLKDIV (rw) register accessor: ADCx clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_adc_clkdiv`] module"] -#[doc(alias = "MRCC_ADC_CLKDIV")] -pub type MrccAdcClkdiv = crate::Reg; -#[doc = "ADCx clock divider control"] -pub mod mrcc_adc_clkdiv; -#[doc = "MRCC_CMP0_FUNC_CLKDIV (rw) register accessor: CMP0_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_func_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_func_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_func_clkdiv`] module"] -#[doc(alias = "MRCC_CMP0_FUNC_CLKDIV")] -pub type MrccCmp0FuncClkdiv = crate::Reg; -#[doc = "CMP0_FUNC clock divider control"] -pub mod mrcc_cmp0_func_clkdiv; -#[doc = "MRCC_CMP0_RR_CLKSEL (rw) register accessor: CMP0_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_rr_clksel`] module"] -#[doc(alias = "MRCC_CMP0_RR_CLKSEL")] -pub type MrccCmp0RrClksel = crate::Reg; -#[doc = "CMP0_RR clock selection control"] -pub mod mrcc_cmp0_rr_clksel; -#[doc = "MRCC_CMP0_RR_CLKDIV (rw) register accessor: CMP0_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp0_rr_clkdiv`] module"] -#[doc(alias = "MRCC_CMP0_RR_CLKDIV")] -pub type MrccCmp0RrClkdiv = crate::Reg; -#[doc = "CMP0_RR clock divider control"] -pub mod mrcc_cmp0_rr_clkdiv; -#[doc = "MRCC_CMP1_FUNC_CLKDIV (rw) register accessor: CMP1_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_func_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_func_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp1_func_clkdiv`] module"] -#[doc(alias = "MRCC_CMP1_FUNC_CLKDIV")] -pub type MrccCmp1FuncClkdiv = crate::Reg; -#[doc = "CMP1_FUNC clock divider control"] -pub mod mrcc_cmp1_func_clkdiv; -#[doc = "MRCC_CMP1_RR_CLKSEL (rw) register accessor: CMP1_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp1_rr_clksel`] module"] -#[doc(alias = "MRCC_CMP1_RR_CLKSEL")] -pub type MrccCmp1RrClksel = crate::Reg; -#[doc = "CMP1_RR clock selection control"] -pub mod mrcc_cmp1_rr_clksel; -#[doc = "MRCC_CMP1_RR_CLKDIV (rw) register accessor: CMP1_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp1_rr_clkdiv`] module"] -#[doc(alias = "MRCC_CMP1_RR_CLKDIV")] -pub type MrccCmp1RrClkdiv = crate::Reg; -#[doc = "CMP1_RR clock divider control"] -pub mod mrcc_cmp1_rr_clkdiv; -#[doc = "MRCC_CMP2_FUNC_CLKDIV (rw) register accessor: CMP2_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_func_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_func_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp2_func_clkdiv`] module"] -#[doc(alias = "MRCC_CMP2_FUNC_CLKDIV")] -pub type MrccCmp2FuncClkdiv = crate::Reg; -#[doc = "CMP2_FUNC clock divider control"] -pub mod mrcc_cmp2_func_clkdiv; -#[doc = "MRCC_CMP2_RR_CLKSEL (rw) register accessor: CMP2_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp2_rr_clksel`] module"] -#[doc(alias = "MRCC_CMP2_RR_CLKSEL")] -pub type MrccCmp2RrClksel = crate::Reg; -#[doc = "CMP2_RR clock selection control"] -pub mod mrcc_cmp2_rr_clksel; -#[doc = "MRCC_CMP2_RR_CLKDIV (rw) register accessor: CMP2_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_cmp2_rr_clkdiv`] module"] -#[doc(alias = "MRCC_CMP2_RR_CLKDIV")] -pub type MrccCmp2RrClkdiv = crate::Reg; -#[doc = "CMP2_RR clock divider control"] -pub mod mrcc_cmp2_rr_clkdiv; -#[doc = "MRCC_DAC0_CLKSEL (rw) register accessor: DAC0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dac0_clksel`] module"] -#[doc(alias = "MRCC_DAC0_CLKSEL")] -pub type MrccDac0Clksel = crate::Reg; -#[doc = "DAC0 clock selection control"] -pub mod mrcc_dac0_clksel; -#[doc = "MRCC_DAC0_CLKDIV (rw) register accessor: DAC0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dac0_clkdiv`] module"] -#[doc(alias = "MRCC_DAC0_CLKDIV")] -pub type MrccDac0Clkdiv = crate::Reg; -#[doc = "DAC0 clock divider control"] -pub mod mrcc_dac0_clkdiv; -#[doc = "MRCC_FLEXCAN0_CLKSEL (rw) register accessor: FLEXCAN0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan0_clksel`] module"] -#[doc(alias = "MRCC_FLEXCAN0_CLKSEL")] -pub type MrccFlexcan0Clksel = crate::Reg; -#[doc = "FLEXCAN0 clock selection control"] -pub mod mrcc_flexcan0_clksel; -#[doc = "MRCC_FLEXCAN0_CLKDIV (rw) register accessor: FLEXCAN0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan0_clkdiv`] module"] -#[doc(alias = "MRCC_FLEXCAN0_CLKDIV")] -pub type MrccFlexcan0Clkdiv = crate::Reg; -#[doc = "FLEXCAN0 clock divider control"] -pub mod mrcc_flexcan0_clkdiv; -#[doc = "MRCC_FLEXCAN1_CLKSEL (rw) register accessor: FLEXCAN1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan1_clksel`] module"] -#[doc(alias = "MRCC_FLEXCAN1_CLKSEL")] -pub type MrccFlexcan1Clksel = crate::Reg; -#[doc = "FLEXCAN1 clock selection control"] -pub mod mrcc_flexcan1_clksel; -#[doc = "MRCC_FLEXCAN1_CLKDIV (rw) register accessor: FLEXCAN1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_flexcan1_clkdiv`] module"] -#[doc(alias = "MRCC_FLEXCAN1_CLKDIV")] -pub type MrccFlexcan1Clkdiv = crate::Reg; -#[doc = "FLEXCAN1 clock divider control"] -pub mod mrcc_flexcan1_clkdiv; -#[doc = "MRCC_LPI2C2_CLKSEL (rw) register accessor: LPI2C2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c2_clksel`] module"] -#[doc(alias = "MRCC_LPI2C2_CLKSEL")] -pub type MrccLpi2c2Clksel = crate::Reg; -#[doc = "LPI2C2 clock selection control"] -pub mod mrcc_lpi2c2_clksel; -#[doc = "MRCC_LPI2C2_CLKDIV (rw) register accessor: LPI2C2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c2_clkdiv`] module"] -#[doc(alias = "MRCC_LPI2C2_CLKDIV")] -pub type MrccLpi2c2Clkdiv = crate::Reg; -#[doc = "LPI2C2 clock divider control"] -pub mod mrcc_lpi2c2_clkdiv; -#[doc = "MRCC_LPI2C3_CLKSEL (rw) register accessor: LPI2C3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c3_clksel`] module"] -#[doc(alias = "MRCC_LPI2C3_CLKSEL")] -pub type MrccLpi2c3Clksel = crate::Reg; -#[doc = "LPI2C3 clock selection control"] -pub mod mrcc_lpi2c3_clksel; -#[doc = "MRCC_LPI2C3_CLKDIV (rw) register accessor: LPI2C3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpi2c3_clkdiv`] module"] -#[doc(alias = "MRCC_LPI2C3_CLKDIV")] -pub type MrccLpi2c3Clkdiv = crate::Reg; -#[doc = "LPI2C3 clock divider control"] -pub mod mrcc_lpi2c3_clkdiv; -#[doc = "MRCC_LPUART5_CLKSEL (rw) register accessor: LPUART5 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart5_clksel`] module"] -#[doc(alias = "MRCC_LPUART5_CLKSEL")] -pub type MrccLpuart5Clksel = crate::Reg; -#[doc = "LPUART5 clock selection control"] -pub mod mrcc_lpuart5_clksel; -#[doc = "MRCC_LPUART5_CLKDIV (rw) register accessor: LPUART5 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_lpuart5_clkdiv`] module"] -#[doc(alias = "MRCC_LPUART5_CLKDIV")] -pub type MrccLpuart5Clkdiv = crate::Reg; -#[doc = "LPUART5 clock divider control"] -pub mod mrcc_lpuart5_clkdiv; -#[doc = "MRCC_DBG_TRACE_CLKSEL (rw) register accessor: DBG_TRACE clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dbg_trace_clksel`] module"] -#[doc(alias = "MRCC_DBG_TRACE_CLKSEL")] -pub type MrccDbgTraceClksel = crate::Reg; -#[doc = "DBG_TRACE clock selection control"] -pub mod mrcc_dbg_trace_clksel; -#[doc = "MRCC_DBG_TRACE_CLKDIV (rw) register accessor: DBG_TRACE clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_dbg_trace_clkdiv`] module"] -#[doc(alias = "MRCC_DBG_TRACE_CLKDIV")] -pub type MrccDbgTraceClkdiv = crate::Reg; -#[doc = "DBG_TRACE clock divider control"] -pub mod mrcc_dbg_trace_clkdiv; -#[doc = "MRCC_CLKOUT_CLKSEL (rw) register accessor: CLKOUT clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_clkout_clksel`] module"] -#[doc(alias = "MRCC_CLKOUT_CLKSEL")] -pub type MrccClkoutClksel = crate::Reg; -#[doc = "CLKOUT clock selection control"] -pub mod mrcc_clkout_clksel; -#[doc = "MRCC_CLKOUT_CLKDIV (rw) register accessor: CLKOUT clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_clkout_clkdiv`] module"] -#[doc(alias = "MRCC_CLKOUT_CLKDIV")] -pub type MrccClkoutClkdiv = crate::Reg; -#[doc = "CLKOUT clock divider control"] -pub mod mrcc_clkout_clkdiv; -#[doc = "MRCC_SYSTICK_CLKSEL (rw) register accessor: SYSTICK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clksel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clksel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_systick_clksel`] module"] -#[doc(alias = "MRCC_SYSTICK_CLKSEL")] -pub type MrccSystickClksel = crate::Reg; -#[doc = "SYSTICK clock selection control"] -pub mod mrcc_systick_clksel; -#[doc = "MRCC_SYSTICK_CLKDIV (rw) register accessor: SYSTICK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrcc_systick_clkdiv`] module"] -#[doc(alias = "MRCC_SYSTICK_CLKDIV")] -pub type MrccSystickClkdiv = crate::Reg; -#[doc = "SYSTICK clock divider control"] -pub mod mrcc_systick_clkdiv; diff --git a/mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs deleted file mode 100644 index f32f236e8..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_adc_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_ADC_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_ADC_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "ADCx clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccAdcClkdivSpec; -impl crate::RegisterSpec for MrccAdcClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_adc_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccAdcClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_adc_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccAdcClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_ADC_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccAdcClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs deleted file mode 100644 index de251dec0..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_adc_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_ADC_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_ADC_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "1: FRO_HF_GATED"] - ClkrootFunc1 = 1, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 1 => Some(Mux::ClkrootFunc1), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_func_1(&self) -> bool { - *self == Mux::ClkrootFunc1 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_func_1(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc1) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "ADCx clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_adc_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_adc_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccAdcClkselSpec; -impl crate::RegisterSpec for MrccAdcClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_adc_clksel::R`](R) reader structure"] -impl crate::Readable for MrccAdcClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_adc_clksel::W`](W) writer structure"] -impl crate::Writable for MrccAdcClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_ADC_CLKSEL to value 0x07"] -impl crate::Resettable for MrccAdcClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs deleted file mode 100644 index d1e62fe47..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_clkout_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CLKOUT_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CLKOUT_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CLKOUT clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccClkoutClkdivSpec; -impl crate::RegisterSpec for MrccClkoutClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_clkout_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccClkoutClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_clkout_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccClkoutClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CLKOUT_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccClkoutClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs deleted file mode 100644 index fcd600b66..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_clkout_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_CLKOUT_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CLKOUT_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_12M"] - Clkroot12m = 0, - #[doc = "1: FRO_HF_DIV"] - ClkrootFircDiv = 1, - #[doc = "2: CLK_IN"] - ClkrootSosc = 2, - #[doc = "3: CLK_16K"] - Clkroot16k = 3, - #[doc = "5: PLL1_CLK"] - ClkrootSpll = 5, - #[doc = "6: SLOW_CLK"] - ClkrootSlow = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Clkroot12m), - 1 => Some(Mux::ClkrootFircDiv), - 2 => Some(Mux::ClkrootSosc), - 3 => Some(Mux::Clkroot16k), - 5 => Some(Mux::ClkrootSpll), - 6 => Some(Mux::ClkrootSlow), - _ => None, - } - } - #[doc = "FRO_12M"] - #[inline(always)] - pub fn is_clkroot_12m(&self) -> bool { - *self == Mux::Clkroot12m - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_firc_div(&self) -> bool { - *self == Mux::ClkrootFircDiv - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_sosc(&self) -> bool { - *self == Mux::ClkrootSosc - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_16k(&self) -> bool { - *self == Mux::Clkroot16k - } - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn is_clkroot_spll(&self) -> bool { - *self == Mux::ClkrootSpll - } - #[doc = "SLOW_CLK"] - #[inline(always)] - pub fn is_clkroot_slow(&self) -> bool { - *self == Mux::ClkrootSlow - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_12M"] - #[inline(always)] - pub fn clkroot_12m(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot12m) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_firc_div(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFircDiv) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_sosc(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSosc) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_16k(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot16k) - } - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn clkroot_spll(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSpll) - } - #[doc = "SLOW_CLK"] - #[inline(always)] - pub fn clkroot_slow(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSlow) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CLKOUT clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccClkoutClkselSpec; -impl crate::RegisterSpec for MrccClkoutClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_clkout_clksel::R`](R) reader structure"] -impl crate::Readable for MrccClkoutClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_clkout_clksel::W`](W) writer structure"] -impl crate::Writable for MrccClkoutClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CLKOUT_CLKSEL to value 0x07"] -impl crate::Resettable for MrccClkoutClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs deleted file mode 100644 index ed5fd5017..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp0_func_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CMP0_FUNC_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP0_FUNC_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CMP0_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_func_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_func_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp0FuncClkdivSpec; -impl crate::RegisterSpec for MrccCmp0FuncClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp0_func_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCmp0FuncClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp0_func_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCmp0FuncClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP0_FUNC_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCmp0FuncClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs deleted file mode 100644 index d53e62ceb..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CMP0_RR_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP0_RR_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CMP0_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp0RrClkdivSpec; -impl crate::RegisterSpec for MrccCmp0RrClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp0_rr_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCmp0RrClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp0_rr_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCmp0RrClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP0_RR_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCmp0RrClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs deleted file mode 100644 index 13e3cf07e..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp0_rr_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_CMP0_RR_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP0_RR_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CMP0_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp0_rr_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp0_rr_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp0RrClkselSpec; -impl crate::RegisterSpec for MrccCmp0RrClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp0_rr_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCmp0RrClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp0_rr_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCmp0RrClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP0_RR_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCmp0RrClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs deleted file mode 100644 index e4d83dd8a..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp1_func_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CMP1_FUNC_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP1_FUNC_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CMP1_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_func_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_func_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp1FuncClkdivSpec; -impl crate::RegisterSpec for MrccCmp1FuncClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp1_func_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCmp1FuncClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp1_func_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCmp1FuncClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP1_FUNC_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCmp1FuncClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs deleted file mode 100644 index 2d505c912..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CMP1_RR_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP1_RR_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CMP1_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp1RrClkdivSpec; -impl crate::RegisterSpec for MrccCmp1RrClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp1_rr_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCmp1RrClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp1_rr_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCmp1RrClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP1_RR_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCmp1RrClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs deleted file mode 100644 index e9d4863bf..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp1_rr_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_CMP1_RR_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP1_RR_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CMP1_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp1_rr_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp1_rr_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp1RrClkselSpec; -impl crate::RegisterSpec for MrccCmp1RrClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp1_rr_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCmp1RrClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp1_rr_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCmp1RrClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP1_RR_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCmp1RrClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs deleted file mode 100644 index 867fb6e21..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp2_func_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CMP2_FUNC_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP2_FUNC_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CMP2_FUNC clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_func_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_func_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp2FuncClkdivSpec; -impl crate::RegisterSpec for MrccCmp2FuncClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp2_func_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCmp2FuncClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp2_func_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCmp2FuncClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP2_FUNC_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCmp2FuncClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs deleted file mode 100644 index 3565ec288..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CMP2_RR_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP2_RR_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CMP2_RR clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp2RrClkdivSpec; -impl crate::RegisterSpec for MrccCmp2RrClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp2_rr_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCmp2RrClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp2_rr_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCmp2RrClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP2_RR_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCmp2RrClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs deleted file mode 100644 index 7c383f9bf..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_cmp2_rr_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_CMP2_RR_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CMP2_RR_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CMP2_RR clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_cmp2_rr_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_cmp2_rr_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCmp2RrClkselSpec; -impl crate::RegisterSpec for MrccCmp2RrClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_cmp2_rr_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCmp2RrClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_cmp2_rr_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCmp2RrClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CMP2_RR_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCmp2RrClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs deleted file mode 100644 index f724e993c..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CTIMER0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CTIMER0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer0ClkdivSpec; -impl crate::RegisterSpec for MrccCtimer0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCtimer0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCtimer0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCtimer0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs deleted file mode 100644 index 6d7422443..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer0_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_CTIMER0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "1: FRO_HF_GATED"] - ClkrootFunc1 = 1, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 1 => Some(Mux::ClkrootFunc1), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_func_1(&self) -> bool { - *self == Mux::ClkrootFunc1 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_func_1(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc1) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer0ClkselSpec; -impl crate::RegisterSpec for MrccCtimer0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCtimer0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCtimer0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCtimer0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs deleted file mode 100644 index d39a9161d..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CTIMER1_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER1_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CTIMER1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer1ClkdivSpec; -impl crate::RegisterSpec for MrccCtimer1ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer1_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCtimer1ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer1_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCtimer1ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER1_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCtimer1ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs deleted file mode 100644 index 0a27a24fd..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer1_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_CTIMER1_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER1_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "1: FRO_HF_GATED"] - ClkrootFunc1 = 1, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 1 => Some(Mux::ClkrootFunc1), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_func_1(&self) -> bool { - *self == Mux::ClkrootFunc1 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_func_1(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc1) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CTIMER1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer1ClkselSpec; -impl crate::RegisterSpec for MrccCtimer1ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer1_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCtimer1ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer1_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCtimer1ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER1_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCtimer1ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs deleted file mode 100644 index 4776a2584..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CTIMER2_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER2_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CTIMER2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer2ClkdivSpec; -impl crate::RegisterSpec for MrccCtimer2ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer2_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCtimer2ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer2_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCtimer2ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER2_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCtimer2ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs deleted file mode 100644 index 2fe5bf7cc..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer2_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_CTIMER2_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER2_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "1: FRO_HF_GATED"] - ClkrootFunc1 = 1, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 1 => Some(Mux::ClkrootFunc1), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_func_1(&self) -> bool { - *self == Mux::ClkrootFunc1 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_func_1(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc1) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CTIMER2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer2_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer2_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer2ClkselSpec; -impl crate::RegisterSpec for MrccCtimer2ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer2_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCtimer2ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer2_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCtimer2ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER2_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCtimer2ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs deleted file mode 100644 index 89aedb37f..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CTIMER3_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER3_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CTIMER3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer3ClkdivSpec; -impl crate::RegisterSpec for MrccCtimer3ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer3_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCtimer3ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer3_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCtimer3ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER3_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCtimer3ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs deleted file mode 100644 index 7263eb5b0..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer3_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_CTIMER3_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER3_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "1: FRO_HF_GATED"] - ClkrootFunc1 = 1, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 1 => Some(Mux::ClkrootFunc1), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_func_1(&self) -> bool { - *self == Mux::ClkrootFunc1 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_func_1(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc1) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CTIMER3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer3_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer3_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer3ClkselSpec; -impl crate::RegisterSpec for MrccCtimer3ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer3_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCtimer3ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer3_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCtimer3ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER3_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCtimer3ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs deleted file mode 100644 index 002dd7c66..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_CTIMER4_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER4_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "CTIMER4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer4ClkdivSpec; -impl crate::RegisterSpec for MrccCtimer4ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer4_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccCtimer4ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer4_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccCtimer4ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER4_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccCtimer4ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs deleted file mode 100644 index 88e8597d0..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ctimer4_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_CTIMER4_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_CTIMER4_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "1: FRO_HF_GATED"] - ClkrootFunc1 = 1, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 1 => Some(Mux::ClkrootFunc1), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_func_1(&self) -> bool { - *self == Mux::ClkrootFunc1 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_func_1(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc1) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "CTIMER4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccCtimer4ClkselSpec; -impl crate::RegisterSpec for MrccCtimer4ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ctimer4_clksel::R`](R) reader structure"] -impl crate::Readable for MrccCtimer4ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer4_clksel::W`](W) writer structure"] -impl crate::Writable for MrccCtimer4ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_CTIMER4_CLKSEL to value 0x07"] -impl crate::Resettable for MrccCtimer4ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs deleted file mode 100644 index 2f8d3aaf2..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_dac0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_DAC0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_DAC0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "DAC0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccDac0ClkdivSpec; -impl crate::RegisterSpec for MrccDac0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_dac0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccDac0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_dac0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccDac0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_DAC0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccDac0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs deleted file mode 100644 index 22b68ce18..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_dac0_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_DAC0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_DAC0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "DAC0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dac0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dac0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccDac0ClkselSpec; -impl crate::RegisterSpec for MrccDac0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_dac0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccDac0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_dac0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccDac0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_DAC0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccDac0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs deleted file mode 100644 index 0865d41c5..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clkdiv.rs +++ /dev/null @@ -1,175 +0,0 @@ -#[doc = "Register `MRCC_DBG_TRACE_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_DBG_TRACE_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "DBG_TRACE clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccDbgTraceClkdivSpec; -impl crate::RegisterSpec for MrccDbgTraceClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_dbg_trace_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccDbgTraceClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_dbg_trace_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccDbgTraceClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_DBG_TRACE_CLKDIV to value 0"] -impl crate::Resettable for MrccDbgTraceClkdivSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs deleted file mode 100644 index 1fb3bbd69..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_dbg_trace_clksel.rs +++ /dev/null @@ -1,104 +0,0 @@ -#[doc = "Register `MRCC_DBG_TRACE_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_DBG_TRACE_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: CPU_CLK"] - ClkrootCpu = 0, - #[doc = "1: CLK_1M"] - Clkroot1m = 1, - #[doc = "2: CLK_16K"] - Clkroot16k = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootCpu), - 1 => Some(Mux::Clkroot1m), - 2 => Some(Mux::Clkroot16k), - _ => None, - } - } - #[doc = "CPU_CLK"] - #[inline(always)] - pub fn is_clkroot_cpu(&self) -> bool { - *self == Mux::ClkrootCpu - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_1m(&self) -> bool { - *self == Mux::Clkroot1m - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_16k(&self) -> bool { - *self == Mux::Clkroot16k - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CPU_CLK"] - #[inline(always)] - pub fn clkroot_cpu(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootCpu) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_1m(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot1m) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_16k(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot16k) - } -} -impl R { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "DBG_TRACE clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccDbgTraceClkselSpec; -impl crate::RegisterSpec for MrccDbgTraceClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_dbg_trace_clksel::R`](R) reader structure"] -impl crate::Readable for MrccDbgTraceClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_dbg_trace_clksel::W`](W) writer structure"] -impl crate::Writable for MrccDbgTraceClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_DBG_TRACE_CLKSEL to value 0"] -impl crate::Resettable for MrccDbgTraceClkselSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs deleted file mode 100644 index f431be88d..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_FLEXCAN0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_FLEXCAN0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "FLEXCAN0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccFlexcan0ClkdivSpec; -impl crate::RegisterSpec for MrccFlexcan0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_flexcan0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccFlexcan0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccFlexcan0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_FLEXCAN0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccFlexcan0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs deleted file mode 100644 index ddc11f84b..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_flexcan0_clksel.rs +++ /dev/null @@ -1,119 +0,0 @@ -#[doc = "Register `MRCC_FLEXCAN0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_FLEXCAN0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "1: FRO_HF_GATED"] - ClkrootFircGated = 1, - #[doc = "2: FRO_HF_DIV"] - ClkrootFircDiv = 2, - #[doc = "3: CLK_IN"] - ClkrootSosc = 3, - #[doc = "6: PLL1_CLK"] - ClkrootSpll = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Mux::ClkrootFircGated), - 2 => Some(Mux::ClkrootFircDiv), - 3 => Some(Mux::ClkrootSosc), - 6 => Some(Mux::ClkrootSpll), - _ => None, - } - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_firc_gated(&self) -> bool { - *self == Mux::ClkrootFircGated - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_firc_div(&self) -> bool { - *self == Mux::ClkrootFircDiv - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_sosc(&self) -> bool { - *self == Mux::ClkrootSosc - } - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn is_clkroot_spll(&self) -> bool { - *self == Mux::ClkrootSpll - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_firc_gated(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFircGated) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_firc_div(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFircDiv) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_sosc(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSosc) - } - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn clkroot_spll(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSpll) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "FLEXCAN0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccFlexcan0ClkselSpec; -impl crate::RegisterSpec for MrccFlexcan0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_flexcan0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccFlexcan0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccFlexcan0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_FLEXCAN0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccFlexcan0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs deleted file mode 100644 index e950f16ef..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_FLEXCAN1_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_FLEXCAN1_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "FLEXCAN1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccFlexcan1ClkdivSpec; -impl crate::RegisterSpec for MrccFlexcan1ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_flexcan1_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccFlexcan1ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan1_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccFlexcan1ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_FLEXCAN1_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccFlexcan1ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs deleted file mode 100644 index 328a4f461..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_flexcan1_clksel.rs +++ /dev/null @@ -1,119 +0,0 @@ -#[doc = "Register `MRCC_FLEXCAN1_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_FLEXCAN1_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "1: FRO_HF_GATED"] - ClkrootFircGated = 1, - #[doc = "2: FRO_HF_DIV"] - ClkrootFircDiv = 2, - #[doc = "3: CLK_IN"] - ClkrootSosc = 3, - #[doc = "6: PLL1_CLK"] - ClkrootSpll = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Mux::ClkrootFircGated), - 2 => Some(Mux::ClkrootFircDiv), - 3 => Some(Mux::ClkrootSosc), - 6 => Some(Mux::ClkrootSpll), - _ => None, - } - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_firc_gated(&self) -> bool { - *self == Mux::ClkrootFircGated - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_firc_div(&self) -> bool { - *self == Mux::ClkrootFircDiv - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_sosc(&self) -> bool { - *self == Mux::ClkrootSosc - } - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn is_clkroot_spll(&self) -> bool { - *self == Mux::ClkrootSpll - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_firc_gated(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFircGated) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_firc_div(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFircDiv) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_sosc(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSosc) - } - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn clkroot_spll(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSpll) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "FLEXCAN1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexcan1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexcan1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccFlexcan1ClkselSpec; -impl crate::RegisterSpec for MrccFlexcan1ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_flexcan1_clksel::R`](R) reader structure"] -impl crate::Readable for MrccFlexcan1ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_flexcan1_clksel::W`](W) writer structure"] -impl crate::Writable for MrccFlexcan1ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_FLEXCAN1_CLKSEL to value 0x07"] -impl crate::Resettable for MrccFlexcan1ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs deleted file mode 100644 index 2f6f94e48..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_flexio0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_FLEXIO0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_FLEXIO0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "FLEXIO0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccFlexio0ClkdivSpec; -impl crate::RegisterSpec for MrccFlexio0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_flexio0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccFlexio0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_flexio0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccFlexio0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_FLEXIO0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccFlexio0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs deleted file mode 100644 index cd004d340..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_flexio0_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_FLEXIO0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_FLEXIO0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "1: FRO_HF_GATED"] - ClkrootFunc1 = 1, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 1 => Some(Mux::ClkrootFunc1), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn is_clkroot_func_1(&self) -> bool { - *self == Mux::ClkrootFunc1 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_GATED"] - #[inline(always)] - pub fn clkroot_func_1(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc1) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "FLEXIO0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_flexio0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_flexio0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccFlexio0ClkselSpec; -impl crate::RegisterSpec for MrccFlexio0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_flexio0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccFlexio0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_flexio0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccFlexio0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_FLEXIO0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccFlexio0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs deleted file mode 100644 index f991a2048..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_acc0.rs +++ /dev/null @@ -1,2039 +0,0 @@ -#[doc = "Register `MRCC_GLB_ACC0` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_ACC0` writer"] -pub type W = crate::W; -#[doc = "INPUTMUX0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inputmux0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inputmux0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INPUTMUX0` reader - INPUTMUX0"] -pub type Inputmux0R = crate::BitReader; -impl Inputmux0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inputmux0 { - match self.bits { - false => Inputmux0::Disabled, - true => Inputmux0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Inputmux0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Inputmux0::Enabled - } -} -#[doc = "Field `INPUTMUX0` writer - INPUTMUX0"] -pub type Inputmux0W<'a, REG> = crate::BitWriter<'a, REG, Inputmux0>; -impl<'a, REG> Inputmux0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Inputmux0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Inputmux0::Enabled) - } -} -#[doc = "I3C0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum I3c0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: I3c0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `I3C0` reader - I3C0"] -pub type I3c0R = crate::BitReader; -impl I3c0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> I3c0 { - match self.bits { - false => I3c0::Disabled, - true => I3c0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == I3c0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == I3c0::Enabled - } -} -#[doc = "Field `I3C0` writer - I3C0"] -pub type I3c0W<'a, REG> = crate::BitWriter<'a, REG, I3c0>; -impl<'a, REG> I3c0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(I3c0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(I3c0::Enabled) - } -} -#[doc = "CTIMER0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER0` reader - CTIMER0"] -pub type Ctimer0R = crate::BitReader; -impl Ctimer0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer0 { - match self.bits { - false => Ctimer0::Disabled, - true => Ctimer0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer0::Enabled - } -} -#[doc = "Field `CTIMER0` writer - CTIMER0"] -pub type Ctimer0W<'a, REG> = crate::BitWriter<'a, REG, Ctimer0>; -impl<'a, REG> Ctimer0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer0::Enabled) - } -} -#[doc = "CTIMER1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER1` reader - CTIMER1"] -pub type Ctimer1R = crate::BitReader; -impl Ctimer1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer1 { - match self.bits { - false => Ctimer1::Disabled, - true => Ctimer1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer1::Enabled - } -} -#[doc = "Field `CTIMER1` writer - CTIMER1"] -pub type Ctimer1W<'a, REG> = crate::BitWriter<'a, REG, Ctimer1>; -impl<'a, REG> Ctimer1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer1::Enabled) - } -} -#[doc = "CTIMER2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER2` reader - CTIMER2"] -pub type Ctimer2R = crate::BitReader; -impl Ctimer2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer2 { - match self.bits { - false => Ctimer2::Disabled, - true => Ctimer2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer2::Enabled - } -} -#[doc = "Field `CTIMER2` writer - CTIMER2"] -pub type Ctimer2W<'a, REG> = crate::BitWriter<'a, REG, Ctimer2>; -impl<'a, REG> Ctimer2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer2::Enabled) - } -} -#[doc = "CTIMER3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer3 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER3` reader - CTIMER3"] -pub type Ctimer3R = crate::BitReader; -impl Ctimer3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer3 { - match self.bits { - false => Ctimer3::Disabled, - true => Ctimer3::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer3::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer3::Enabled - } -} -#[doc = "Field `CTIMER3` writer - CTIMER3"] -pub type Ctimer3W<'a, REG> = crate::BitWriter<'a, REG, Ctimer3>; -impl<'a, REG> Ctimer3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer3::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer3::Enabled) - } -} -#[doc = "CTIMER4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer4 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER4` reader - CTIMER4"] -pub type Ctimer4R = crate::BitReader; -impl Ctimer4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer4 { - match self.bits { - false => Ctimer4::Disabled, - true => Ctimer4::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer4::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer4::Enabled - } -} -#[doc = "Field `CTIMER4` writer - CTIMER4"] -pub type Ctimer4W<'a, REG> = crate::BitWriter<'a, REG, Ctimer4>; -impl<'a, REG> Ctimer4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer4::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer4::Enabled) - } -} -#[doc = "FREQME\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Freqme { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Freqme) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FREQME` reader - FREQME"] -pub type FreqmeR = crate::BitReader; -impl FreqmeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Freqme { - match self.bits { - false => Freqme::Disabled, - true => Freqme::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Freqme::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Freqme::Enabled - } -} -#[doc = "Field `FREQME` writer - FREQME"] -pub type FreqmeW<'a, REG> = crate::BitWriter<'a, REG, Freqme>; -impl<'a, REG> FreqmeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Freqme::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Freqme::Enabled) - } -} -#[doc = "UTICK0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Utick0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Utick0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UTICK0` reader - UTICK0"] -pub type Utick0R = crate::BitReader; -impl Utick0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Utick0 { - match self.bits { - false => Utick0::Disabled, - true => Utick0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Utick0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Utick0::Enabled - } -} -#[doc = "Field `UTICK0` writer - UTICK0"] -pub type Utick0W<'a, REG> = crate::BitWriter<'a, REG, Utick0>; -impl<'a, REG> Utick0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Utick0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Utick0::Enabled) - } -} -#[doc = "WWDT0\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wwdt0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wwdt0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WWDT0` reader - WWDT0"] -pub type Wwdt0R = crate::BitReader; -impl Wwdt0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wwdt0 { - match self.bits { - false => Wwdt0::Disabled, - true => Wwdt0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wwdt0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wwdt0::Enabled - } -} -#[doc = "Field `WWDT0` writer - WWDT0"] -pub type Wwdt0W<'a, REG> = crate::BitWriter<'a, REG, Wwdt0>; -impl<'a, REG> Wwdt0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Enabled) - } -} -#[doc = "SMARTDMA0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Smartdma0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Smartdma0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SMARTDMA0` reader - SMARTDMA0"] -pub type Smartdma0R = crate::BitReader; -impl Smartdma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Smartdma0 { - match self.bits { - false => Smartdma0::Disabled, - true => Smartdma0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Smartdma0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Smartdma0::Enabled - } -} -#[doc = "Field `SMARTDMA0` writer - SMARTDMA0"] -pub type Smartdma0W<'a, REG> = crate::BitWriter<'a, REG, Smartdma0>; -impl<'a, REG> Smartdma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Smartdma0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Smartdma0::Enabled) - } -} -#[doc = "DMA0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dma0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dma0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMA0` reader - DMA0"] -pub type Dma0R = crate::BitReader; -impl Dma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dma0 { - match self.bits { - false => Dma0::Disabled, - true => Dma0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dma0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dma0::Enabled - } -} -#[doc = "Field `DMA0` writer - DMA0"] -pub type Dma0W<'a, REG> = crate::BitWriter<'a, REG, Dma0>; -impl<'a, REG> Dma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dma0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dma0::Enabled) - } -} -#[doc = "AOI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aoi0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aoi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AOI0` reader - AOI0"] -pub type Aoi0R = crate::BitReader; -impl Aoi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aoi0 { - match self.bits { - false => Aoi0::Disabled, - true => Aoi0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Aoi0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Aoi0::Enabled - } -} -#[doc = "Field `AOI0` writer - AOI0"] -pub type Aoi0W<'a, REG> = crate::BitWriter<'a, REG, Aoi0>; -impl<'a, REG> Aoi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Aoi0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Aoi0::Enabled) - } -} -#[doc = "CRC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crc0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRC0` reader - CRC0"] -pub type Crc0R = crate::BitReader; -impl Crc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crc0 { - match self.bits { - false => Crc0::Disabled, - true => Crc0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Crc0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Crc0::Enabled - } -} -#[doc = "Field `CRC0` writer - CRC0"] -pub type Crc0W<'a, REG> = crate::BitWriter<'a, REG, Crc0>; -impl<'a, REG> Crc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Crc0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Crc0::Enabled) - } -} -#[doc = "EIM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Eim0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Eim0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EIM0` reader - EIM0"] -pub type Eim0R = crate::BitReader; -impl Eim0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Eim0 { - match self.bits { - false => Eim0::Disabled, - true => Eim0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Eim0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Eim0::Enabled - } -} -#[doc = "Field `EIM0` writer - EIM0"] -pub type Eim0W<'a, REG> = crate::BitWriter<'a, REG, Eim0>; -impl<'a, REG> Eim0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Eim0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Eim0::Enabled) - } -} -#[doc = "ERM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erm0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erm0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERM0` reader - ERM0"] -pub type Erm0R = crate::BitReader; -impl Erm0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erm0 { - match self.bits { - false => Erm0::Disabled, - true => Erm0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Erm0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Erm0::Enabled - } -} -#[doc = "Field `ERM0` writer - ERM0"] -pub type Erm0W<'a, REG> = crate::BitWriter<'a, REG, Erm0>; -impl<'a, REG> Erm0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Erm0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Erm0::Enabled) - } -} -#[doc = "FMC\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fmc { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fmc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FMC` reader - FMC"] -pub type FmcR = crate::BitReader; -impl FmcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fmc { - match self.bits { - false => Fmc::Disabled, - true => Fmc::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fmc::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fmc::Enabled - } -} -#[doc = "Field `FMC` writer - FMC"] -pub type FmcW<'a, REG> = crate::BitWriter<'a, REG, Fmc>; -impl<'a, REG> FmcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fmc::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fmc::Enabled) - } -} -#[doc = "AOI1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aoi1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aoi1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AOI1` reader - AOI1"] -pub type Aoi1R = crate::BitReader; -impl Aoi1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aoi1 { - match self.bits { - false => Aoi1::Disabled, - true => Aoi1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Aoi1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Aoi1::Enabled - } -} -#[doc = "Field `AOI1` writer - AOI1"] -pub type Aoi1W<'a, REG> = crate::BitWriter<'a, REG, Aoi1>; -impl<'a, REG> Aoi1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Aoi1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Aoi1::Enabled) - } -} -#[doc = "FLEXIO0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexio0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexio0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXIO0` reader - FLEXIO0"] -pub type Flexio0R = crate::BitReader; -impl Flexio0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexio0 { - match self.bits { - false => Flexio0::Disabled, - true => Flexio0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexio0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexio0::Enabled - } -} -#[doc = "Field `FLEXIO0` writer - FLEXIO0"] -pub type Flexio0W<'a, REG> = crate::BitWriter<'a, REG, Flexio0>; -impl<'a, REG> Flexio0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexio0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexio0::Enabled) - } -} -#[doc = "LPI2C0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C0` reader - LPI2C0"] -pub type Lpi2c0R = crate::BitReader; -impl Lpi2c0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c0 { - match self.bits { - false => Lpi2c0::Disabled, - true => Lpi2c0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c0::Enabled - } -} -#[doc = "Field `LPI2C0` writer - LPI2C0"] -pub type Lpi2c0W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c0>; -impl<'a, REG> Lpi2c0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c0::Enabled) - } -} -#[doc = "LPI2C1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C1` reader - LPI2C1"] -pub type Lpi2c1R = crate::BitReader; -impl Lpi2c1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c1 { - match self.bits { - false => Lpi2c1::Disabled, - true => Lpi2c1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c1::Enabled - } -} -#[doc = "Field `LPI2C1` writer - LPI2C1"] -pub type Lpi2c1W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c1>; -impl<'a, REG> Lpi2c1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c1::Enabled) - } -} -#[doc = "LPSPI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpspi0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpspi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPSPI0` reader - LPSPI0"] -pub type Lpspi0R = crate::BitReader; -impl Lpspi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpspi0 { - match self.bits { - false => Lpspi0::Disabled, - true => Lpspi0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpspi0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpspi0::Enabled - } -} -#[doc = "Field `LPSPI0` writer - LPSPI0"] -pub type Lpspi0W<'a, REG> = crate::BitWriter<'a, REG, Lpspi0>; -impl<'a, REG> Lpspi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpspi0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpspi0::Enabled) - } -} -#[doc = "LPSPI1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpspi1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpspi1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPSPI1` reader - LPSPI1"] -pub type Lpspi1R = crate::BitReader; -impl Lpspi1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpspi1 { - match self.bits { - false => Lpspi1::Disabled, - true => Lpspi1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpspi1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpspi1::Enabled - } -} -#[doc = "Field `LPSPI1` writer - LPSPI1"] -pub type Lpspi1W<'a, REG> = crate::BitWriter<'a, REG, Lpspi1>; -impl<'a, REG> Lpspi1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpspi1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpspi1::Enabled) - } -} -#[doc = "LPUART0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART0` reader - LPUART0"] -pub type Lpuart0R = crate::BitReader; -impl Lpuart0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart0 { - match self.bits { - false => Lpuart0::Disabled, - true => Lpuart0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart0::Enabled - } -} -#[doc = "Field `LPUART0` writer - LPUART0"] -pub type Lpuart0W<'a, REG> = crate::BitWriter<'a, REG, Lpuart0>; -impl<'a, REG> Lpuart0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart0::Enabled) - } -} -#[doc = "LPUART1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART1` reader - LPUART1"] -pub type Lpuart1R = crate::BitReader; -impl Lpuart1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart1 { - match self.bits { - false => Lpuart1::Disabled, - true => Lpuart1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart1::Enabled - } -} -#[doc = "Field `LPUART1` writer - LPUART1"] -pub type Lpuart1W<'a, REG> = crate::BitWriter<'a, REG, Lpuart1>; -impl<'a, REG> Lpuart1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart1::Enabled) - } -} -#[doc = "LPUART2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART2` reader - LPUART2"] -pub type Lpuart2R = crate::BitReader; -impl Lpuart2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart2 { - match self.bits { - false => Lpuart2::Disabled, - true => Lpuart2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart2::Enabled - } -} -#[doc = "Field `LPUART2` writer - LPUART2"] -pub type Lpuart2W<'a, REG> = crate::BitWriter<'a, REG, Lpuart2>; -impl<'a, REG> Lpuart2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart2::Enabled) - } -} -#[doc = "LPUART3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart3 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART3` reader - LPUART3"] -pub type Lpuart3R = crate::BitReader; -impl Lpuart3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart3 { - match self.bits { - false => Lpuart3::Disabled, - true => Lpuart3::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart3::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart3::Enabled - } -} -#[doc = "Field `LPUART3` writer - LPUART3"] -pub type Lpuart3W<'a, REG> = crate::BitWriter<'a, REG, Lpuart3>; -impl<'a, REG> Lpuart3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart3::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart3::Enabled) - } -} -#[doc = "LPUART4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart4 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART4` reader - LPUART4"] -pub type Lpuart4R = crate::BitReader; -impl Lpuart4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart4 { - match self.bits { - false => Lpuart4::Disabled, - true => Lpuart4::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart4::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart4::Enabled - } -} -#[doc = "Field `LPUART4` writer - LPUART4"] -pub type Lpuart4W<'a, REG> = crate::BitWriter<'a, REG, Lpuart4>; -impl<'a, REG> Lpuart4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart4::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart4::Enabled) - } -} -#[doc = "USB0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usb0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usb0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USB0` reader - USB0"] -pub type Usb0R = crate::BitReader; -impl Usb0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Usb0 { - match self.bits { - false => Usb0::Disabled, - true => Usb0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Usb0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Usb0::Enabled - } -} -#[doc = "Field `USB0` writer - USB0"] -pub type Usb0W<'a, REG> = crate::BitWriter<'a, REG, Usb0>; -impl<'a, REG> Usb0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Usb0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Usb0::Enabled) - } -} -#[doc = "QDC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Qdc0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Qdc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `QDC0` reader - QDC0"] -pub type Qdc0R = crate::BitReader; -impl Qdc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Qdc0 { - match self.bits { - false => Qdc0::Disabled, - true => Qdc0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Qdc0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Qdc0::Enabled - } -} -#[doc = "Field `QDC0` writer - QDC0"] -pub type Qdc0W<'a, REG> = crate::BitWriter<'a, REG, Qdc0>; -impl<'a, REG> Qdc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Qdc0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Qdc0::Enabled) - } -} -#[doc = "QDC1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Qdc1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Qdc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `QDC1` reader - QDC1"] -pub type Qdc1R = crate::BitReader; -impl Qdc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Qdc1 { - match self.bits { - false => Qdc1::Disabled, - true => Qdc1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Qdc1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Qdc1::Enabled - } -} -#[doc = "Field `QDC1` writer - QDC1"] -pub type Qdc1W<'a, REG> = crate::BitWriter<'a, REG, Qdc1>; -impl<'a, REG> Qdc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Qdc1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Qdc1::Enabled) - } -} -#[doc = "FLEXPWM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexpwm0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexpwm0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXPWM0` reader - FLEXPWM0"] -pub type Flexpwm0R = crate::BitReader; -impl Flexpwm0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexpwm0 { - match self.bits { - false => Flexpwm0::Disabled, - true => Flexpwm0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexpwm0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexpwm0::Enabled - } -} -#[doc = "Field `FLEXPWM0` writer - FLEXPWM0"] -pub type Flexpwm0W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm0>; -impl<'a, REG> Flexpwm0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexpwm0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexpwm0::Enabled) - } -} -impl R { - #[doc = "Bit 0 - INPUTMUX0"] - #[inline(always)] - pub fn inputmux0(&self) -> Inputmux0R { - Inputmux0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - I3C0"] - #[inline(always)] - pub fn i3c0(&self) -> I3c0R { - I3c0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - CTIMER0"] - #[inline(always)] - pub fn ctimer0(&self) -> Ctimer0R { - Ctimer0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - CTIMER1"] - #[inline(always)] - pub fn ctimer1(&self) -> Ctimer1R { - Ctimer1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - CTIMER2"] - #[inline(always)] - pub fn ctimer2(&self) -> Ctimer2R { - Ctimer2R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - CTIMER3"] - #[inline(always)] - pub fn ctimer3(&self) -> Ctimer3R { - Ctimer3R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - CTIMER4"] - #[inline(always)] - pub fn ctimer4(&self) -> Ctimer4R { - Ctimer4R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - FREQME"] - #[inline(always)] - pub fn freqme(&self) -> FreqmeR { - FreqmeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - UTICK0"] - #[inline(always)] - pub fn utick0(&self) -> Utick0R { - Utick0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - WWDT0"] - #[inline(always)] - pub fn wwdt0(&self) -> Wwdt0R { - Wwdt0R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SMARTDMA0"] - #[inline(always)] - pub fn smartdma0(&self) -> Smartdma0R { - Smartdma0R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - DMA0"] - #[inline(always)] - pub fn dma0(&self) -> Dma0R { - Dma0R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - AOI0"] - #[inline(always)] - pub fn aoi0(&self) -> Aoi0R { - Aoi0R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - CRC0"] - #[inline(always)] - pub fn crc0(&self) -> Crc0R { - Crc0R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - EIM0"] - #[inline(always)] - pub fn eim0(&self) -> Eim0R { - Eim0R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - ERM0"] - #[inline(always)] - pub fn erm0(&self) -> Erm0R { - Erm0R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - FMC"] - #[inline(always)] - pub fn fmc(&self) -> FmcR { - FmcR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - AOI1"] - #[inline(always)] - pub fn aoi1(&self) -> Aoi1R { - Aoi1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - FLEXIO0"] - #[inline(always)] - pub fn flexio0(&self) -> Flexio0R { - Flexio0R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - LPI2C0"] - #[inline(always)] - pub fn lpi2c0(&self) -> Lpi2c0R { - Lpi2c0R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LPI2C1"] - #[inline(always)] - pub fn lpi2c1(&self) -> Lpi2c1R { - Lpi2c1R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LPSPI0"] - #[inline(always)] - pub fn lpspi0(&self) -> Lpspi0R { - Lpspi0R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LPSPI1"] - #[inline(always)] - pub fn lpspi1(&self) -> Lpspi1R { - Lpspi1R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - LPUART0"] - #[inline(always)] - pub fn lpuart0(&self) -> Lpuart0R { - Lpuart0R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - LPUART1"] - #[inline(always)] - pub fn lpuart1(&self) -> Lpuart1R { - Lpuart1R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - LPUART2"] - #[inline(always)] - pub fn lpuart2(&self) -> Lpuart2R { - Lpuart2R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - LPUART3"] - #[inline(always)] - pub fn lpuart3(&self) -> Lpuart3R { - Lpuart3R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - LPUART4"] - #[inline(always)] - pub fn lpuart4(&self) -> Lpuart4R { - Lpuart4R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - USB0"] - #[inline(always)] - pub fn usb0(&self) -> Usb0R { - Usb0R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - QDC0"] - #[inline(always)] - pub fn qdc0(&self) -> Qdc0R { - Qdc0R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - QDC1"] - #[inline(always)] - pub fn qdc1(&self) -> Qdc1R { - Qdc1R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - FLEXPWM0"] - #[inline(always)] - pub fn flexpwm0(&self) -> Flexpwm0R { - Flexpwm0R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - INPUTMUX0"] - #[inline(always)] - pub fn inputmux0(&mut self) -> Inputmux0W { - Inputmux0W::new(self, 0) - } - #[doc = "Bit 1 - I3C0"] - #[inline(always)] - pub fn i3c0(&mut self) -> I3c0W { - I3c0W::new(self, 1) - } - #[doc = "Bit 2 - CTIMER0"] - #[inline(always)] - pub fn ctimer0(&mut self) -> Ctimer0W { - Ctimer0W::new(self, 2) - } - #[doc = "Bit 3 - CTIMER1"] - #[inline(always)] - pub fn ctimer1(&mut self) -> Ctimer1W { - Ctimer1W::new(self, 3) - } - #[doc = "Bit 4 - CTIMER2"] - #[inline(always)] - pub fn ctimer2(&mut self) -> Ctimer2W { - Ctimer2W::new(self, 4) - } - #[doc = "Bit 5 - CTIMER3"] - #[inline(always)] - pub fn ctimer3(&mut self) -> Ctimer3W { - Ctimer3W::new(self, 5) - } - #[doc = "Bit 6 - CTIMER4"] - #[inline(always)] - pub fn ctimer4(&mut self) -> Ctimer4W { - Ctimer4W::new(self, 6) - } - #[doc = "Bit 7 - FREQME"] - #[inline(always)] - pub fn freqme(&mut self) -> FreqmeW { - FreqmeW::new(self, 7) - } - #[doc = "Bit 8 - UTICK0"] - #[inline(always)] - pub fn utick0(&mut self) -> Utick0W { - Utick0W::new(self, 8) - } - #[doc = "Bit 9 - WWDT0"] - #[inline(always)] - pub fn wwdt0(&mut self) -> Wwdt0W { - Wwdt0W::new(self, 9) - } - #[doc = "Bit 10 - SMARTDMA0"] - #[inline(always)] - pub fn smartdma0(&mut self) -> Smartdma0W { - Smartdma0W::new(self, 10) - } - #[doc = "Bit 11 - DMA0"] - #[inline(always)] - pub fn dma0(&mut self) -> Dma0W { - Dma0W::new(self, 11) - } - #[doc = "Bit 12 - AOI0"] - #[inline(always)] - pub fn aoi0(&mut self) -> Aoi0W { - Aoi0W::new(self, 12) - } - #[doc = "Bit 13 - CRC0"] - #[inline(always)] - pub fn crc0(&mut self) -> Crc0W { - Crc0W::new(self, 13) - } - #[doc = "Bit 14 - EIM0"] - #[inline(always)] - pub fn eim0(&mut self) -> Eim0W { - Eim0W::new(self, 14) - } - #[doc = "Bit 15 - ERM0"] - #[inline(always)] - pub fn erm0(&mut self) -> Erm0W { - Erm0W::new(self, 15) - } - #[doc = "Bit 16 - FMC"] - #[inline(always)] - pub fn fmc(&mut self) -> FmcW { - FmcW::new(self, 16) - } - #[doc = "Bit 17 - AOI1"] - #[inline(always)] - pub fn aoi1(&mut self) -> Aoi1W { - Aoi1W::new(self, 17) - } - #[doc = "Bit 18 - FLEXIO0"] - #[inline(always)] - pub fn flexio0(&mut self) -> Flexio0W { - Flexio0W::new(self, 18) - } - #[doc = "Bit 19 - LPI2C0"] - #[inline(always)] - pub fn lpi2c0(&mut self) -> Lpi2c0W { - Lpi2c0W::new(self, 19) - } - #[doc = "Bit 20 - LPI2C1"] - #[inline(always)] - pub fn lpi2c1(&mut self) -> Lpi2c1W { - Lpi2c1W::new(self, 20) - } - #[doc = "Bit 21 - LPSPI0"] - #[inline(always)] - pub fn lpspi0(&mut self) -> Lpspi0W { - Lpspi0W::new(self, 21) - } - #[doc = "Bit 22 - LPSPI1"] - #[inline(always)] - pub fn lpspi1(&mut self) -> Lpspi1W { - Lpspi1W::new(self, 22) - } - #[doc = "Bit 23 - LPUART0"] - #[inline(always)] - pub fn lpuart0(&mut self) -> Lpuart0W { - Lpuart0W::new(self, 23) - } - #[doc = "Bit 24 - LPUART1"] - #[inline(always)] - pub fn lpuart1(&mut self) -> Lpuart1W { - Lpuart1W::new(self, 24) - } - #[doc = "Bit 25 - LPUART2"] - #[inline(always)] - pub fn lpuart2(&mut self) -> Lpuart2W { - Lpuart2W::new(self, 25) - } - #[doc = "Bit 26 - LPUART3"] - #[inline(always)] - pub fn lpuart3(&mut self) -> Lpuart3W { - Lpuart3W::new(self, 26) - } - #[doc = "Bit 27 - LPUART4"] - #[inline(always)] - pub fn lpuart4(&mut self) -> Lpuart4W { - Lpuart4W::new(self, 27) - } - #[doc = "Bit 28 - USB0"] - #[inline(always)] - pub fn usb0(&mut self) -> Usb0W { - Usb0W::new(self, 28) - } - #[doc = "Bit 29 - QDC0"] - #[inline(always)] - pub fn qdc0(&mut self) -> Qdc0W { - Qdc0W::new(self, 29) - } - #[doc = "Bit 30 - QDC1"] - #[inline(always)] - pub fn qdc1(&mut self) -> Qdc1W { - Qdc1W::new(self, 30) - } - #[doc = "Bit 31 - FLEXPWM0"] - #[inline(always)] - pub fn flexpwm0(&mut self) -> Flexpwm0W { - Flexpwm0W::new(self, 31) - } -} -#[doc = "Control Automatic Clock Gating 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbAcc0Spec; -impl crate::RegisterSpec for MrccGlbAcc0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_acc0::R`](R) reader structure"] -impl crate::Readable for MrccGlbAcc0Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc0::W`](W) writer structure"] -impl crate::Writable for MrccGlbAcc0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_ACC0 to value 0x0001_0200"] -impl crate::Resettable for MrccGlbAcc0Spec { - const RESET_VALUE: u32 = 0x0001_0200; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs deleted file mode 100644 index 241308455..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_acc1.rs +++ /dev/null @@ -1,1848 +0,0 @@ -#[doc = "Register `MRCC_GLB_ACC1` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_ACC1` writer"] -pub type W = crate::W; -#[doc = "FLEXPWM1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexpwm1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexpwm1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXPWM1` reader - FLEXPWM1"] -pub type Flexpwm1R = crate::BitReader; -impl Flexpwm1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexpwm1 { - match self.bits { - false => Flexpwm1::Disabled, - true => Flexpwm1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexpwm1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexpwm1::Enabled - } -} -#[doc = "Field `FLEXPWM1` writer - FLEXPWM1"] -pub type Flexpwm1W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm1>; -impl<'a, REG> Flexpwm1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexpwm1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexpwm1::Enabled) - } -} -#[doc = "OSTIMER0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ostimer0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ostimer0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSTIMER0` reader - OSTIMER0"] -pub type Ostimer0R = crate::BitReader; -impl Ostimer0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ostimer0 { - match self.bits { - false => Ostimer0::Disabled, - true => Ostimer0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ostimer0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ostimer0::Enabled - } -} -#[doc = "Field `OSTIMER0` writer - OSTIMER0"] -pub type Ostimer0W<'a, REG> = crate::BitWriter<'a, REG, Ostimer0>; -impl<'a, REG> Ostimer0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ostimer0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ostimer0::Enabled) - } -} -#[doc = "ADC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC0` reader - ADC0"] -pub type Adc0R = crate::BitReader; -impl Adc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc0 { - match self.bits { - false => Adc0::Disabled, - true => Adc0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc0::Enabled - } -} -#[doc = "Field `ADC0` writer - ADC0"] -pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG, Adc0>; -impl<'a, REG> Adc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc0::Enabled) - } -} -#[doc = "ADC1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC1` reader - ADC1"] -pub type Adc1R = crate::BitReader; -impl Adc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc1 { - match self.bits { - false => Adc1::Disabled, - true => Adc1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc1::Enabled - } -} -#[doc = "Field `ADC1` writer - ADC1"] -pub type Adc1W<'a, REG> = crate::BitWriter<'a, REG, Adc1>; -impl<'a, REG> Adc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc1::Enabled) - } -} -#[doc = "CMP0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP0` reader - CMP0"] -pub type Cmp0R = crate::BitReader; -impl Cmp0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp0 { - match self.bits { - false => Cmp0::Disabled, - true => Cmp0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp0::Enabled - } -} -#[doc = "Field `CMP0` writer - CMP0"] -pub type Cmp0W<'a, REG> = crate::BitWriter<'a, REG, Cmp0>; -impl<'a, REG> Cmp0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp0::Enabled) - } -} -#[doc = "CMP1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP1` reader - CMP1"] -pub type Cmp1R = crate::BitReader; -impl Cmp1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp1 { - match self.bits { - false => Cmp1::Disabled, - true => Cmp1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp1::Enabled - } -} -#[doc = "Field `CMP1` writer - CMP1"] -pub type Cmp1W<'a, REG> = crate::BitWriter<'a, REG, Cmp1>; -impl<'a, REG> Cmp1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp1::Enabled) - } -} -#[doc = "CMP2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP2` reader - CMP2"] -pub type Cmp2R = crate::BitReader; -impl Cmp2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp2 { - match self.bits { - false => Cmp2::Disabled, - true => Cmp2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp2::Enabled - } -} -#[doc = "Field `CMP2` writer - CMP2"] -pub type Cmp2W<'a, REG> = crate::BitWriter<'a, REG, Cmp2>; -impl<'a, REG> Cmp2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp2::Enabled) - } -} -#[doc = "DAC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dac0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dac0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAC0` reader - DAC0"] -pub type Dac0R = crate::BitReader; -impl Dac0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dac0 { - match self.bits { - false => Dac0::Disabled, - true => Dac0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dac0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dac0::Enabled - } -} -#[doc = "Field `DAC0` writer - DAC0"] -pub type Dac0W<'a, REG> = crate::BitWriter<'a, REG, Dac0>; -impl<'a, REG> Dac0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dac0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dac0::Enabled) - } -} -#[doc = "OPAMP0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP0` reader - OPAMP0"] -pub type Opamp0R = crate::BitReader; -impl Opamp0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp0 { - match self.bits { - false => Opamp0::Disabled, - true => Opamp0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp0::Enabled - } -} -#[doc = "Field `OPAMP0` writer - OPAMP0"] -pub type Opamp0W<'a, REG> = crate::BitWriter<'a, REG, Opamp0>; -impl<'a, REG> Opamp0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp0::Enabled) - } -} -#[doc = "OPAMP1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP1` reader - OPAMP1"] -pub type Opamp1R = crate::BitReader; -impl Opamp1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp1 { - match self.bits { - false => Opamp1::Disabled, - true => Opamp1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp1::Enabled - } -} -#[doc = "Field `OPAMP1` writer - OPAMP1"] -pub type Opamp1W<'a, REG> = crate::BitWriter<'a, REG, Opamp1>; -impl<'a, REG> Opamp1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp1::Enabled) - } -} -#[doc = "OPAMP2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP2` reader - OPAMP2"] -pub type Opamp2R = crate::BitReader; -impl Opamp2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp2 { - match self.bits { - false => Opamp2::Disabled, - true => Opamp2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp2::Enabled - } -} -#[doc = "Field `OPAMP2` writer - OPAMP2"] -pub type Opamp2W<'a, REG> = crate::BitWriter<'a, REG, Opamp2>; -impl<'a, REG> Opamp2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp2::Enabled) - } -} -#[doc = "OPAMP3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp3 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP3` reader - OPAMP3"] -pub type Opamp3R = crate::BitReader; -impl Opamp3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp3 { - match self.bits { - false => Opamp3::Disabled, - true => Opamp3::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp3::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp3::Enabled - } -} -#[doc = "Field `OPAMP3` writer - OPAMP3"] -pub type Opamp3W<'a, REG> = crate::BitWriter<'a, REG, Opamp3>; -impl<'a, REG> Opamp3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp3::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp3::Enabled) - } -} -#[doc = "PORT0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT0` reader - PORT0"] -pub type Port0R = crate::BitReader; -impl Port0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port0 { - match self.bits { - false => Port0::Disabled, - true => Port0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port0::Enabled - } -} -#[doc = "Field `PORT0` writer - PORT0"] -pub type Port0W<'a, REG> = crate::BitWriter<'a, REG, Port0>; -impl<'a, REG> Port0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port0::Enabled) - } -} -#[doc = "PORT1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT1` reader - PORT1"] -pub type Port1R = crate::BitReader; -impl Port1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port1 { - match self.bits { - false => Port1::Disabled, - true => Port1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port1::Enabled - } -} -#[doc = "Field `PORT1` writer - PORT1"] -pub type Port1W<'a, REG> = crate::BitWriter<'a, REG, Port1>; -impl<'a, REG> Port1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port1::Enabled) - } -} -#[doc = "PORT2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT2` reader - PORT2"] -pub type Port2R = crate::BitReader; -impl Port2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port2 { - match self.bits { - false => Port2::Disabled, - true => Port2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port2::Enabled - } -} -#[doc = "Field `PORT2` writer - PORT2"] -pub type Port2W<'a, REG> = crate::BitWriter<'a, REG, Port2>; -impl<'a, REG> Port2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port2::Enabled) - } -} -#[doc = "PORT3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port3 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT3` reader - PORT3"] -pub type Port3R = crate::BitReader; -impl Port3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port3 { - match self.bits { - false => Port3::Disabled, - true => Port3::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port3::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port3::Enabled - } -} -#[doc = "Field `PORT3` writer - PORT3"] -pub type Port3W<'a, REG> = crate::BitWriter<'a, REG, Port3>; -impl<'a, REG> Port3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port3::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port3::Enabled) - } -} -#[doc = "PORT4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port4 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT4` reader - PORT4"] -pub type Port4R = crate::BitReader; -impl Port4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port4 { - match self.bits { - false => Port4::Disabled, - true => Port4::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port4::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port4::Enabled - } -} -#[doc = "Field `PORT4` writer - PORT4"] -pub type Port4W<'a, REG> = crate::BitWriter<'a, REG, Port4>; -impl<'a, REG> Port4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port4::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port4::Enabled) - } -} -#[doc = "SLCD0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slcd0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slcd0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLCD0` reader - SLCD0"] -pub type Slcd0R = crate::BitReader; -impl Slcd0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slcd0 { - match self.bits { - false => Slcd0::Disabled, - true => Slcd0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Slcd0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Slcd0::Enabled - } -} -#[doc = "Field `SLCD0` writer - SLCD0"] -pub type Slcd0W<'a, REG> = crate::BitWriter<'a, REG, Slcd0>; -impl<'a, REG> Slcd0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Slcd0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Slcd0::Enabled) - } -} -#[doc = "FLEXCAN0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexcan0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexcan0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXCAN0` reader - FLEXCAN0"] -pub type Flexcan0R = crate::BitReader; -impl Flexcan0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexcan0 { - match self.bits { - false => Flexcan0::Disabled, - true => Flexcan0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexcan0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexcan0::Enabled - } -} -#[doc = "Field `FLEXCAN0` writer - FLEXCAN0"] -pub type Flexcan0W<'a, REG> = crate::BitWriter<'a, REG, Flexcan0>; -impl<'a, REG> Flexcan0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexcan0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexcan0::Enabled) - } -} -#[doc = "FLEXCAN1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexcan1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexcan1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXCAN1` reader - FLEXCAN1"] -pub type Flexcan1R = crate::BitReader; -impl Flexcan1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexcan1 { - match self.bits { - false => Flexcan1::Disabled, - true => Flexcan1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexcan1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexcan1::Enabled - } -} -#[doc = "Field `FLEXCAN1` writer - FLEXCAN1"] -pub type Flexcan1W<'a, REG> = crate::BitWriter<'a, REG, Flexcan1>; -impl<'a, REG> Flexcan1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexcan1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexcan1::Enabled) - } -} -#[doc = "LPI2C2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C2` reader - LPI2C2"] -pub type Lpi2c2R = crate::BitReader; -impl Lpi2c2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c2 { - match self.bits { - false => Lpi2c2::Disabled, - true => Lpi2c2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c2::Enabled - } -} -#[doc = "Field `LPI2C2` writer - LPI2C2"] -pub type Lpi2c2W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c2>; -impl<'a, REG> Lpi2c2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c2::Enabled) - } -} -#[doc = "LPI2C3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c3 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C3` reader - LPI2C3"] -pub type Lpi2c3R = crate::BitReader; -impl Lpi2c3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c3 { - match self.bits { - false => Lpi2c3::Disabled, - true => Lpi2c3::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c3::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c3::Enabled - } -} -#[doc = "Field `LPI2C3` writer - LPI2C3"] -pub type Lpi2c3W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c3>; -impl<'a, REG> Lpi2c3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c3::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c3::Enabled) - } -} -#[doc = "LPUART5\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart5 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART5` reader - LPUART5"] -pub type Lpuart5R = crate::BitReader; -impl Lpuart5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart5 { - match self.bits { - false => Lpuart5::Disabled, - true => Lpuart5::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart5::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart5::Enabled - } -} -#[doc = "Field `LPUART5` writer - LPUART5"] -pub type Lpuart5W<'a, REG> = crate::BitWriter<'a, REG, Lpuart5>; -impl<'a, REG> Lpuart5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart5::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart5::Enabled) - } -} -#[doc = "PKC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pkc0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pkc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PKC0` reader - PKC0"] -pub type Pkc0R = crate::BitReader; -impl Pkc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pkc0 { - match self.bits { - false => Pkc0::Disabled, - true => Pkc0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pkc0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pkc0::Enabled - } -} -#[doc = "Field `PKC0` writer - PKC0"] -pub type Pkc0W<'a, REG> = crate::BitWriter<'a, REG, Pkc0>; -impl<'a, REG> Pkc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pkc0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pkc0::Enabled) - } -} -#[doc = "SGI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sgi0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sgi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SGI0` reader - SGI0"] -pub type Sgi0R = crate::BitReader; -impl Sgi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sgi0 { - match self.bits { - false => Sgi0::Disabled, - true => Sgi0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sgi0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sgi0::Enabled - } -} -#[doc = "Field `SGI0` writer - SGI0"] -pub type Sgi0W<'a, REG> = crate::BitWriter<'a, REG, Sgi0>; -impl<'a, REG> Sgi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sgi0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sgi0::Enabled) - } -} -#[doc = "TRNG0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trng0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trng0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRNG0` reader - TRNG0"] -pub type Trng0R = crate::BitReader; -impl Trng0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trng0 { - match self.bits { - false => Trng0::Disabled, - true => Trng0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Trng0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Trng0::Enabled - } -} -#[doc = "Field `TRNG0` writer - TRNG0"] -pub type Trng0W<'a, REG> = crate::BitWriter<'a, REG, Trng0>; -impl<'a, REG> Trng0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Trng0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Trng0::Enabled) - } -} -#[doc = "UDF0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Udf0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Udf0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UDF0` reader - UDF0"] -pub type Udf0R = crate::BitReader; -impl Udf0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Udf0 { - match self.bits { - false => Udf0::Disabled, - true => Udf0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Udf0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Udf0::Enabled - } -} -#[doc = "Field `UDF0` writer - UDF0"] -pub type Udf0W<'a, REG> = crate::BitWriter<'a, REG, Udf0>; -impl<'a, REG> Udf0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Udf0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Udf0::Enabled) - } -} -#[doc = "ADC2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC2` reader - ADC2"] -pub type Adc2R = crate::BitReader; -impl Adc2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc2 { - match self.bits { - false => Adc2::Disabled, - true => Adc2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc2::Enabled - } -} -#[doc = "Field `ADC2` writer - ADC2"] -pub type Adc2W<'a, REG> = crate::BitWriter<'a, REG, Adc2>; -impl<'a, REG> Adc2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc2::Enabled) - } -} -#[doc = "ADC3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc3 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC3` reader - ADC3"] -pub type Adc3R = crate::BitReader; -impl Adc3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc3 { - match self.bits { - false => Adc3::Disabled, - true => Adc3::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc3::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc3::Enabled - } -} -#[doc = "Field `ADC3` writer - ADC3"] -pub type Adc3W<'a, REG> = crate::BitWriter<'a, REG, Adc3>; -impl<'a, REG> Adc3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc3::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc3::Enabled) - } -} -impl R { - #[doc = "Bit 0 - FLEXPWM1"] - #[inline(always)] - pub fn flexpwm1(&self) -> Flexpwm1R { - Flexpwm1R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - OSTIMER0"] - #[inline(always)] - pub fn ostimer0(&self) -> Ostimer0R { - Ostimer0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - ADC0"] - #[inline(always)] - pub fn adc0(&self) -> Adc0R { - Adc0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - ADC1"] - #[inline(always)] - pub fn adc1(&self) -> Adc1R { - Adc1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - CMP0"] - #[inline(always)] - pub fn cmp0(&self) -> Cmp0R { - Cmp0R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - CMP1"] - #[inline(always)] - pub fn cmp1(&self) -> Cmp1R { - Cmp1R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - CMP2"] - #[inline(always)] - pub fn cmp2(&self) -> Cmp2R { - Cmp2R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - DAC0"] - #[inline(always)] - pub fn dac0(&self) -> Dac0R { - Dac0R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - OPAMP0"] - #[inline(always)] - pub fn opamp0(&self) -> Opamp0R { - Opamp0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - OPAMP1"] - #[inline(always)] - pub fn opamp1(&self) -> Opamp1R { - Opamp1R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - OPAMP2"] - #[inline(always)] - pub fn opamp2(&self) -> Opamp2R { - Opamp2R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - OPAMP3"] - #[inline(always)] - pub fn opamp3(&self) -> Opamp3R { - Opamp3R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - PORT0"] - #[inline(always)] - pub fn port0(&self) -> Port0R { - Port0R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - PORT1"] - #[inline(always)] - pub fn port1(&self) -> Port1R { - Port1R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - PORT2"] - #[inline(always)] - pub fn port2(&self) -> Port2R { - Port2R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - PORT3"] - #[inline(always)] - pub fn port3(&self) -> Port3R { - Port3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - PORT4"] - #[inline(always)] - pub fn port4(&self) -> Port4R { - Port4R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - SLCD0"] - #[inline(always)] - pub fn slcd0(&self) -> Slcd0R { - Slcd0R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - FLEXCAN0"] - #[inline(always)] - pub fn flexcan0(&self) -> Flexcan0R { - Flexcan0R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - FLEXCAN1"] - #[inline(always)] - pub fn flexcan1(&self) -> Flexcan1R { - Flexcan1R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LPI2C2"] - #[inline(always)] - pub fn lpi2c2(&self) -> Lpi2c2R { - Lpi2c2R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LPI2C3"] - #[inline(always)] - pub fn lpi2c3(&self) -> Lpi2c3R { - Lpi2c3R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LPUART5"] - #[inline(always)] - pub fn lpuart5(&self) -> Lpuart5R { - Lpuart5R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 24 - PKC0"] - #[inline(always)] - pub fn pkc0(&self) -> Pkc0R { - Pkc0R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - SGI0"] - #[inline(always)] - pub fn sgi0(&self) -> Sgi0R { - Sgi0R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - TRNG0"] - #[inline(always)] - pub fn trng0(&self) -> Trng0R { - Trng0R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - UDF0"] - #[inline(always)] - pub fn udf0(&self) -> Udf0R { - Udf0R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - ADC2"] - #[inline(always)] - pub fn adc2(&self) -> Adc2R { - Adc2R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - ADC3"] - #[inline(always)] - pub fn adc3(&self) -> Adc3R { - Adc3R::new(((self.bits >> 29) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FLEXPWM1"] - #[inline(always)] - pub fn flexpwm1(&mut self) -> Flexpwm1W { - Flexpwm1W::new(self, 0) - } - #[doc = "Bit 1 - OSTIMER0"] - #[inline(always)] - pub fn ostimer0(&mut self) -> Ostimer0W { - Ostimer0W::new(self, 1) - } - #[doc = "Bit 2 - ADC0"] - #[inline(always)] - pub fn adc0(&mut self) -> Adc0W { - Adc0W::new(self, 2) - } - #[doc = "Bit 3 - ADC1"] - #[inline(always)] - pub fn adc1(&mut self) -> Adc1W { - Adc1W::new(self, 3) - } - #[doc = "Bit 4 - CMP0"] - #[inline(always)] - pub fn cmp0(&mut self) -> Cmp0W { - Cmp0W::new(self, 4) - } - #[doc = "Bit 5 - CMP1"] - #[inline(always)] - pub fn cmp1(&mut self) -> Cmp1W { - Cmp1W::new(self, 5) - } - #[doc = "Bit 6 - CMP2"] - #[inline(always)] - pub fn cmp2(&mut self) -> Cmp2W { - Cmp2W::new(self, 6) - } - #[doc = "Bit 7 - DAC0"] - #[inline(always)] - pub fn dac0(&mut self) -> Dac0W { - Dac0W::new(self, 7) - } - #[doc = "Bit 8 - OPAMP0"] - #[inline(always)] - pub fn opamp0(&mut self) -> Opamp0W { - Opamp0W::new(self, 8) - } - #[doc = "Bit 9 - OPAMP1"] - #[inline(always)] - pub fn opamp1(&mut self) -> Opamp1W { - Opamp1W::new(self, 9) - } - #[doc = "Bit 10 - OPAMP2"] - #[inline(always)] - pub fn opamp2(&mut self) -> Opamp2W { - Opamp2W::new(self, 10) - } - #[doc = "Bit 11 - OPAMP3"] - #[inline(always)] - pub fn opamp3(&mut self) -> Opamp3W { - Opamp3W::new(self, 11) - } - #[doc = "Bit 12 - PORT0"] - #[inline(always)] - pub fn port0(&mut self) -> Port0W { - Port0W::new(self, 12) - } - #[doc = "Bit 13 - PORT1"] - #[inline(always)] - pub fn port1(&mut self) -> Port1W { - Port1W::new(self, 13) - } - #[doc = "Bit 14 - PORT2"] - #[inline(always)] - pub fn port2(&mut self) -> Port2W { - Port2W::new(self, 14) - } - #[doc = "Bit 15 - PORT3"] - #[inline(always)] - pub fn port3(&mut self) -> Port3W { - Port3W::new(self, 15) - } - #[doc = "Bit 16 - PORT4"] - #[inline(always)] - pub fn port4(&mut self) -> Port4W { - Port4W::new(self, 16) - } - #[doc = "Bit 17 - SLCD0"] - #[inline(always)] - pub fn slcd0(&mut self) -> Slcd0W { - Slcd0W::new(self, 17) - } - #[doc = "Bit 18 - FLEXCAN0"] - #[inline(always)] - pub fn flexcan0(&mut self) -> Flexcan0W { - Flexcan0W::new(self, 18) - } - #[doc = "Bit 19 - FLEXCAN1"] - #[inline(always)] - pub fn flexcan1(&mut self) -> Flexcan1W { - Flexcan1W::new(self, 19) - } - #[doc = "Bit 20 - LPI2C2"] - #[inline(always)] - pub fn lpi2c2(&mut self) -> Lpi2c2W { - Lpi2c2W::new(self, 20) - } - #[doc = "Bit 21 - LPI2C3"] - #[inline(always)] - pub fn lpi2c3(&mut self) -> Lpi2c3W { - Lpi2c3W::new(self, 21) - } - #[doc = "Bit 22 - LPUART5"] - #[inline(always)] - pub fn lpuart5(&mut self) -> Lpuart5W { - Lpuart5W::new(self, 22) - } - #[doc = "Bit 24 - PKC0"] - #[inline(always)] - pub fn pkc0(&mut self) -> Pkc0W { - Pkc0W::new(self, 24) - } - #[doc = "Bit 25 - SGI0"] - #[inline(always)] - pub fn sgi0(&mut self) -> Sgi0W { - Sgi0W::new(self, 25) - } - #[doc = "Bit 26 - TRNG0"] - #[inline(always)] - pub fn trng0(&mut self) -> Trng0W { - Trng0W::new(self, 26) - } - #[doc = "Bit 27 - UDF0"] - #[inline(always)] - pub fn udf0(&mut self) -> Udf0W { - Udf0W::new(self, 27) - } - #[doc = "Bit 28 - ADC2"] - #[inline(always)] - pub fn adc2(&mut self) -> Adc2W { - Adc2W::new(self, 28) - } - #[doc = "Bit 29 - ADC3"] - #[inline(always)] - pub fn adc3(&mut self) -> Adc3W { - Adc3W::new(self, 29) - } -} -#[doc = "Control Automatic Clock Gating 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbAcc1Spec; -impl crate::RegisterSpec for MrccGlbAcc1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_acc1::R`](R) reader structure"] -impl crate::Readable for MrccGlbAcc1Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc1::W`](W) writer structure"] -impl crate::Writable for MrccGlbAcc1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_ACC1 to value 0"] -impl crate::Resettable for MrccGlbAcc1Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs deleted file mode 100644 index 4898a871a..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_acc2.rs +++ /dev/null @@ -1,653 +0,0 @@ -#[doc = "Register `MRCC_GLB_ACC2` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_ACC2` writer"] -pub type W = crate::W; -#[doc = "RAMA\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rama { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rama) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMA` reader - RAMA"] -pub type RamaR = crate::BitReader; -impl RamaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rama { - match self.bits { - false => Rama::Disabled, - true => Rama::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rama::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rama::Enabled - } -} -#[doc = "Field `RAMA` writer - RAMA"] -pub type RamaW<'a, REG> = crate::BitWriter<'a, REG, Rama>; -impl<'a, REG> RamaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rama::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rama::Enabled) - } -} -#[doc = "RAMB\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ramb { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ramb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMB` reader - RAMB"] -pub type RambR = crate::BitReader; -impl RambR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ramb { - match self.bits { - false => Ramb::Disabled, - true => Ramb::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ramb::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ramb::Enabled - } -} -#[doc = "Field `RAMB` writer - RAMB"] -pub type RambW<'a, REG> = crate::BitWriter<'a, REG, Ramb>; -impl<'a, REG> RambW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ramb::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ramb::Enabled) - } -} -#[doc = "RAMC\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ramc { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ramc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMC` reader - RAMC"] -pub type RamcR = crate::BitReader; -impl RamcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ramc { - match self.bits { - false => Ramc::Disabled, - true => Ramc::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ramc::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ramc::Enabled - } -} -#[doc = "Field `RAMC` writer - RAMC"] -pub type RamcW<'a, REG> = crate::BitWriter<'a, REG, Ramc>; -impl<'a, REG> RamcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ramc::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ramc::Enabled) - } -} -#[doc = "GPIO0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO0` reader - GPIO0"] -pub type Gpio0R = crate::BitReader; -impl Gpio0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio0 { - match self.bits { - false => Gpio0::Disabled, - true => Gpio0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio0::Enabled - } -} -#[doc = "Field `GPIO0` writer - GPIO0"] -pub type Gpio0W<'a, REG> = crate::BitWriter<'a, REG, Gpio0>; -impl<'a, REG> Gpio0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio0::Enabled) - } -} -#[doc = "GPIO1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio1 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO1` reader - GPIO1"] -pub type Gpio1R = crate::BitReader; -impl Gpio1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio1 { - match self.bits { - false => Gpio1::Disabled, - true => Gpio1::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio1::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio1::Enabled - } -} -#[doc = "Field `GPIO1` writer - GPIO1"] -pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG, Gpio1>; -impl<'a, REG> Gpio1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio1::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio1::Enabled) - } -} -#[doc = "GPIO2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio2 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO2` reader - GPIO2"] -pub type Gpio2R = crate::BitReader; -impl Gpio2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio2 { - match self.bits { - false => Gpio2::Disabled, - true => Gpio2::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio2::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio2::Enabled - } -} -#[doc = "Field `GPIO2` writer - GPIO2"] -pub type Gpio2W<'a, REG> = crate::BitWriter<'a, REG, Gpio2>; -impl<'a, REG> Gpio2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio2::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio2::Enabled) - } -} -#[doc = "GPIO3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio3 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO3` reader - GPIO3"] -pub type Gpio3R = crate::BitReader; -impl Gpio3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio3 { - match self.bits { - false => Gpio3::Disabled, - true => Gpio3::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio3::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio3::Enabled - } -} -#[doc = "Field `GPIO3` writer - GPIO3"] -pub type Gpio3W<'a, REG> = crate::BitWriter<'a, REG, Gpio3>; -impl<'a, REG> Gpio3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio3::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio3::Enabled) - } -} -#[doc = "GPIO4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio4 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO4` reader - GPIO4"] -pub type Gpio4R = crate::BitReader; -impl Gpio4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio4 { - match self.bits { - false => Gpio4::Disabled, - true => Gpio4::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio4::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio4::Enabled - } -} -#[doc = "Field `GPIO4` writer - GPIO4"] -pub type Gpio4W<'a, REG> = crate::BitWriter<'a, REG, Gpio4>; -impl<'a, REG> Gpio4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio4::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio4::Enabled) - } -} -#[doc = "MAU0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mau0 { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mau0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MAU0` reader - MAU0"] -pub type Mau0R = crate::BitReader; -impl Mau0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mau0 { - match self.bits { - false => Mau0::Disabled, - true => Mau0::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Mau0::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Mau0::Enabled - } -} -#[doc = "Field `MAU0` writer - MAU0"] -pub type Mau0W<'a, REG> = crate::BitWriter<'a, REG, Mau0>; -impl<'a, REG> Mau0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Mau0::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Mau0::Enabled) - } -} -#[doc = "ROMC\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Romc { - #[doc = "0: Automatic clock gating is disabled"] - Disabled = 0, - #[doc = "1: Automatic clock gating is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Romc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROMC` reader - ROMC"] -pub type RomcR = crate::BitReader; -impl RomcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Romc { - match self.bits { - false => Romc::Disabled, - true => Romc::Enabled, - } - } - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Romc::Disabled - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Romc::Enabled - } -} -#[doc = "Field `ROMC` writer - ROMC"] -pub type RomcW<'a, REG> = crate::BitWriter<'a, REG, Romc>; -impl<'a, REG> RomcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Automatic clock gating is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Romc::Disabled) - } - #[doc = "Automatic clock gating is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Romc::Enabled) - } -} -impl R { - #[doc = "Bit 1 - RAMA"] - #[inline(always)] - pub fn rama(&self) -> RamaR { - RamaR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - RAMB"] - #[inline(always)] - pub fn ramb(&self) -> RambR { - RambR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - RAMC"] - #[inline(always)] - pub fn ramc(&self) -> RamcR { - RamcR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - GPIO0"] - #[inline(always)] - pub fn gpio0(&self) -> Gpio0R { - Gpio0R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - GPIO1"] - #[inline(always)] - pub fn gpio1(&self) -> Gpio1R { - Gpio1R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - GPIO2"] - #[inline(always)] - pub fn gpio2(&self) -> Gpio2R { - Gpio2R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - GPIO3"] - #[inline(always)] - pub fn gpio3(&self) -> Gpio3R { - Gpio3R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - GPIO4"] - #[inline(always)] - pub fn gpio4(&self) -> Gpio4R { - Gpio4R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - MAU0"] - #[inline(always)] - pub fn mau0(&self) -> Mau0R { - Mau0R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - ROMC"] - #[inline(always)] - pub fn romc(&self) -> RomcR { - RomcR::new(((self.bits >> 10) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - RAMA"] - #[inline(always)] - pub fn rama(&mut self) -> RamaW { - RamaW::new(self, 1) - } - #[doc = "Bit 2 - RAMB"] - #[inline(always)] - pub fn ramb(&mut self) -> RambW { - RambW::new(self, 2) - } - #[doc = "Bit 3 - RAMC"] - #[inline(always)] - pub fn ramc(&mut self) -> RamcW { - RamcW::new(self, 3) - } - #[doc = "Bit 4 - GPIO0"] - #[inline(always)] - pub fn gpio0(&mut self) -> Gpio0W { - Gpio0W::new(self, 4) - } - #[doc = "Bit 5 - GPIO1"] - #[inline(always)] - pub fn gpio1(&mut self) -> Gpio1W { - Gpio1W::new(self, 5) - } - #[doc = "Bit 6 - GPIO2"] - #[inline(always)] - pub fn gpio2(&mut self) -> Gpio2W { - Gpio2W::new(self, 6) - } - #[doc = "Bit 7 - GPIO3"] - #[inline(always)] - pub fn gpio3(&mut self) -> Gpio3W { - Gpio3W::new(self, 7) - } - #[doc = "Bit 8 - GPIO4"] - #[inline(always)] - pub fn gpio4(&mut self) -> Gpio4W { - Gpio4W::new(self, 8) - } - #[doc = "Bit 9 - MAU0"] - #[inline(always)] - pub fn mau0(&mut self) -> Mau0W { - Mau0W::new(self, 9) - } - #[doc = "Bit 10 - ROMC"] - #[inline(always)] - pub fn romc(&mut self) -> RomcW { - RomcW::new(self, 10) - } -} -#[doc = "Control Automatic Clock Gating 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbAcc2Spec; -impl crate::RegisterSpec for MrccGlbAcc2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_acc2::R`](R) reader structure"] -impl crate::Readable for MrccGlbAcc2Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc2::W`](W) writer structure"] -impl crate::Writable for MrccGlbAcc2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_ACC2 to value 0x040e"] -impl crate::Resettable for MrccGlbAcc2Spec { - const RESET_VALUE: u32 = 0x040e; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs deleted file mode 100644 index 68558c034..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0.rs +++ /dev/null @@ -1,2039 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC0` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_CC0` writer"] -pub type W = crate::W; -#[doc = "INPUTMUX0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inputmux0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inputmux0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INPUTMUX0` reader - INPUTMUX0"] -pub type Inputmux0R = crate::BitReader; -impl Inputmux0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inputmux0 { - match self.bits { - false => Inputmux0::Disabled, - true => Inputmux0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Inputmux0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Inputmux0::Enabled - } -} -#[doc = "Field `INPUTMUX0` writer - INPUTMUX0"] -pub type Inputmux0W<'a, REG> = crate::BitWriter<'a, REG, Inputmux0>; -impl<'a, REG> Inputmux0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Inputmux0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Inputmux0::Enabled) - } -} -#[doc = "I3C0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum I3c0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: I3c0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `I3C0` reader - I3C0"] -pub type I3c0R = crate::BitReader; -impl I3c0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> I3c0 { - match self.bits { - false => I3c0::Disabled, - true => I3c0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == I3c0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == I3c0::Enabled - } -} -#[doc = "Field `I3C0` writer - I3C0"] -pub type I3c0W<'a, REG> = crate::BitWriter<'a, REG, I3c0>; -impl<'a, REG> I3c0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(I3c0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(I3c0::Enabled) - } -} -#[doc = "CTIMER0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER0` reader - CTIMER0"] -pub type Ctimer0R = crate::BitReader; -impl Ctimer0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer0 { - match self.bits { - false => Ctimer0::Disabled, - true => Ctimer0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer0::Enabled - } -} -#[doc = "Field `CTIMER0` writer - CTIMER0"] -pub type Ctimer0W<'a, REG> = crate::BitWriter<'a, REG, Ctimer0>; -impl<'a, REG> Ctimer0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer0::Enabled) - } -} -#[doc = "CTIMER1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER1` reader - CTIMER1"] -pub type Ctimer1R = crate::BitReader; -impl Ctimer1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer1 { - match self.bits { - false => Ctimer1::Disabled, - true => Ctimer1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer1::Enabled - } -} -#[doc = "Field `CTIMER1` writer - CTIMER1"] -pub type Ctimer1W<'a, REG> = crate::BitWriter<'a, REG, Ctimer1>; -impl<'a, REG> Ctimer1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer1::Enabled) - } -} -#[doc = "CTIMER2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER2` reader - CTIMER2"] -pub type Ctimer2R = crate::BitReader; -impl Ctimer2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer2 { - match self.bits { - false => Ctimer2::Disabled, - true => Ctimer2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer2::Enabled - } -} -#[doc = "Field `CTIMER2` writer - CTIMER2"] -pub type Ctimer2W<'a, REG> = crate::BitWriter<'a, REG, Ctimer2>; -impl<'a, REG> Ctimer2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer2::Enabled) - } -} -#[doc = "CTIMER3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer3 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER3` reader - CTIMER3"] -pub type Ctimer3R = crate::BitReader; -impl Ctimer3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer3 { - match self.bits { - false => Ctimer3::Disabled, - true => Ctimer3::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer3::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer3::Enabled - } -} -#[doc = "Field `CTIMER3` writer - CTIMER3"] -pub type Ctimer3W<'a, REG> = crate::BitWriter<'a, REG, Ctimer3>; -impl<'a, REG> Ctimer3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer3::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer3::Enabled) - } -} -#[doc = "CTIMER4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer4 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER4` reader - CTIMER4"] -pub type Ctimer4R = crate::BitReader; -impl Ctimer4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer4 { - match self.bits { - false => Ctimer4::Disabled, - true => Ctimer4::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer4::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer4::Enabled - } -} -#[doc = "Field `CTIMER4` writer - CTIMER4"] -pub type Ctimer4W<'a, REG> = crate::BitWriter<'a, REG, Ctimer4>; -impl<'a, REG> Ctimer4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer4::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer4::Enabled) - } -} -#[doc = "FREQME\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Freqme { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Freqme) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FREQME` reader - FREQME"] -pub type FreqmeR = crate::BitReader; -impl FreqmeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Freqme { - match self.bits { - false => Freqme::Disabled, - true => Freqme::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Freqme::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Freqme::Enabled - } -} -#[doc = "Field `FREQME` writer - FREQME"] -pub type FreqmeW<'a, REG> = crate::BitWriter<'a, REG, Freqme>; -impl<'a, REG> FreqmeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Freqme::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Freqme::Enabled) - } -} -#[doc = "UTICK0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Utick0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Utick0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UTICK0` reader - UTICK0"] -pub type Utick0R = crate::BitReader; -impl Utick0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Utick0 { - match self.bits { - false => Utick0::Disabled, - true => Utick0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Utick0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Utick0::Enabled - } -} -#[doc = "Field `UTICK0` writer - UTICK0"] -pub type Utick0W<'a, REG> = crate::BitWriter<'a, REG, Utick0>; -impl<'a, REG> Utick0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Utick0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Utick0::Enabled) - } -} -#[doc = "WWDT0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wwdt0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wwdt0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WWDT0` reader - WWDT0"] -pub type Wwdt0R = crate::BitReader; -impl Wwdt0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wwdt0 { - match self.bits { - false => Wwdt0::Disabled, - true => Wwdt0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Wwdt0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Wwdt0::Enabled - } -} -#[doc = "Field `WWDT0` writer - WWDT0"] -pub type Wwdt0W<'a, REG> = crate::BitWriter<'a, REG, Wwdt0>; -impl<'a, REG> Wwdt0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Wwdt0::Enabled) - } -} -#[doc = "SMARTDMA0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Smartdma0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Smartdma0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SMARTDMA0` reader - SMARTDMA0"] -pub type Smartdma0R = crate::BitReader; -impl Smartdma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Smartdma0 { - match self.bits { - false => Smartdma0::Disabled, - true => Smartdma0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Smartdma0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Smartdma0::Enabled - } -} -#[doc = "Field `SMARTDMA0` writer - SMARTDMA0"] -pub type Smartdma0W<'a, REG> = crate::BitWriter<'a, REG, Smartdma0>; -impl<'a, REG> Smartdma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Smartdma0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Smartdma0::Enabled) - } -} -#[doc = "DMA0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dma0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dma0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMA0` reader - DMA0"] -pub type Dma0R = crate::BitReader; -impl Dma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dma0 { - match self.bits { - false => Dma0::Disabled, - true => Dma0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dma0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dma0::Enabled - } -} -#[doc = "Field `DMA0` writer - DMA0"] -pub type Dma0W<'a, REG> = crate::BitWriter<'a, REG, Dma0>; -impl<'a, REG> Dma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dma0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dma0::Enabled) - } -} -#[doc = "AOI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aoi0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aoi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AOI0` reader - AOI0"] -pub type Aoi0R = crate::BitReader; -impl Aoi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aoi0 { - match self.bits { - false => Aoi0::Disabled, - true => Aoi0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Aoi0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Aoi0::Enabled - } -} -#[doc = "Field `AOI0` writer - AOI0"] -pub type Aoi0W<'a, REG> = crate::BitWriter<'a, REG, Aoi0>; -impl<'a, REG> Aoi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Aoi0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Aoi0::Enabled) - } -} -#[doc = "CRC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crc0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRC0` reader - CRC0"] -pub type Crc0R = crate::BitReader; -impl Crc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crc0 { - match self.bits { - false => Crc0::Disabled, - true => Crc0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Crc0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Crc0::Enabled - } -} -#[doc = "Field `CRC0` writer - CRC0"] -pub type Crc0W<'a, REG> = crate::BitWriter<'a, REG, Crc0>; -impl<'a, REG> Crc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Crc0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Crc0::Enabled) - } -} -#[doc = "EIM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Eim0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Eim0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EIM0` reader - EIM0"] -pub type Eim0R = crate::BitReader; -impl Eim0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Eim0 { - match self.bits { - false => Eim0::Disabled, - true => Eim0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Eim0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Eim0::Enabled - } -} -#[doc = "Field `EIM0` writer - EIM0"] -pub type Eim0W<'a, REG> = crate::BitWriter<'a, REG, Eim0>; -impl<'a, REG> Eim0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Eim0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Eim0::Enabled) - } -} -#[doc = "ERM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erm0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erm0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERM0` reader - ERM0"] -pub type Erm0R = crate::BitReader; -impl Erm0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erm0 { - match self.bits { - false => Erm0::Disabled, - true => Erm0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Erm0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Erm0::Enabled - } -} -#[doc = "Field `ERM0` writer - ERM0"] -pub type Erm0W<'a, REG> = crate::BitWriter<'a, REG, Erm0>; -impl<'a, REG> Erm0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Erm0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Erm0::Enabled) - } -} -#[doc = "FMC\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fmc { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fmc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FMC` reader - FMC"] -pub type FmcR = crate::BitReader; -impl FmcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fmc { - match self.bits { - false => Fmc::Disabled, - true => Fmc::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fmc::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fmc::Enabled - } -} -#[doc = "Field `FMC` writer - FMC"] -pub type FmcW<'a, REG> = crate::BitWriter<'a, REG, Fmc>; -impl<'a, REG> FmcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fmc::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fmc::Enabled) - } -} -#[doc = "AOI1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aoi1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aoi1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AOI1` reader - AOI1"] -pub type Aoi1R = crate::BitReader; -impl Aoi1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aoi1 { - match self.bits { - false => Aoi1::Disabled, - true => Aoi1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Aoi1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Aoi1::Enabled - } -} -#[doc = "Field `AOI1` writer - AOI1"] -pub type Aoi1W<'a, REG> = crate::BitWriter<'a, REG, Aoi1>; -impl<'a, REG> Aoi1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Aoi1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Aoi1::Enabled) - } -} -#[doc = "FLEXIO0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexio0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexio0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXIO0` reader - FLEXIO0"] -pub type Flexio0R = crate::BitReader; -impl Flexio0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexio0 { - match self.bits { - false => Flexio0::Disabled, - true => Flexio0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexio0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexio0::Enabled - } -} -#[doc = "Field `FLEXIO0` writer - FLEXIO0"] -pub type Flexio0W<'a, REG> = crate::BitWriter<'a, REG, Flexio0>; -impl<'a, REG> Flexio0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexio0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexio0::Enabled) - } -} -#[doc = "LPI2C0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C0` reader - LPI2C0"] -pub type Lpi2c0R = crate::BitReader; -impl Lpi2c0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c0 { - match self.bits { - false => Lpi2c0::Disabled, - true => Lpi2c0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c0::Enabled - } -} -#[doc = "Field `LPI2C0` writer - LPI2C0"] -pub type Lpi2c0W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c0>; -impl<'a, REG> Lpi2c0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c0::Enabled) - } -} -#[doc = "LPI2C1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C1` reader - LPI2C1"] -pub type Lpi2c1R = crate::BitReader; -impl Lpi2c1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c1 { - match self.bits { - false => Lpi2c1::Disabled, - true => Lpi2c1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c1::Enabled - } -} -#[doc = "Field `LPI2C1` writer - LPI2C1"] -pub type Lpi2c1W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c1>; -impl<'a, REG> Lpi2c1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c1::Enabled) - } -} -#[doc = "LPSPI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpspi0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpspi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPSPI0` reader - LPSPI0"] -pub type Lpspi0R = crate::BitReader; -impl Lpspi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpspi0 { - match self.bits { - false => Lpspi0::Disabled, - true => Lpspi0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpspi0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpspi0::Enabled - } -} -#[doc = "Field `LPSPI0` writer - LPSPI0"] -pub type Lpspi0W<'a, REG> = crate::BitWriter<'a, REG, Lpspi0>; -impl<'a, REG> Lpspi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpspi0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpspi0::Enabled) - } -} -#[doc = "LPSPI1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpspi1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpspi1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPSPI1` reader - LPSPI1"] -pub type Lpspi1R = crate::BitReader; -impl Lpspi1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpspi1 { - match self.bits { - false => Lpspi1::Disabled, - true => Lpspi1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpspi1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpspi1::Enabled - } -} -#[doc = "Field `LPSPI1` writer - LPSPI1"] -pub type Lpspi1W<'a, REG> = crate::BitWriter<'a, REG, Lpspi1>; -impl<'a, REG> Lpspi1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpspi1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpspi1::Enabled) - } -} -#[doc = "LPUART0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART0` reader - LPUART0"] -pub type Lpuart0R = crate::BitReader; -impl Lpuart0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart0 { - match self.bits { - false => Lpuart0::Disabled, - true => Lpuart0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart0::Enabled - } -} -#[doc = "Field `LPUART0` writer - LPUART0"] -pub type Lpuart0W<'a, REG> = crate::BitWriter<'a, REG, Lpuart0>; -impl<'a, REG> Lpuart0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart0::Enabled) - } -} -#[doc = "LPUART1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART1` reader - LPUART1"] -pub type Lpuart1R = crate::BitReader; -impl Lpuart1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart1 { - match self.bits { - false => Lpuart1::Disabled, - true => Lpuart1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart1::Enabled - } -} -#[doc = "Field `LPUART1` writer - LPUART1"] -pub type Lpuart1W<'a, REG> = crate::BitWriter<'a, REG, Lpuart1>; -impl<'a, REG> Lpuart1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart1::Enabled) - } -} -#[doc = "LPUART2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART2` reader - LPUART2"] -pub type Lpuart2R = crate::BitReader; -impl Lpuart2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart2 { - match self.bits { - false => Lpuart2::Disabled, - true => Lpuart2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart2::Enabled - } -} -#[doc = "Field `LPUART2` writer - LPUART2"] -pub type Lpuart2W<'a, REG> = crate::BitWriter<'a, REG, Lpuart2>; -impl<'a, REG> Lpuart2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart2::Enabled) - } -} -#[doc = "LPUART3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart3 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART3` reader - LPUART3"] -pub type Lpuart3R = crate::BitReader; -impl Lpuart3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart3 { - match self.bits { - false => Lpuart3::Disabled, - true => Lpuart3::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart3::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart3::Enabled - } -} -#[doc = "Field `LPUART3` writer - LPUART3"] -pub type Lpuart3W<'a, REG> = crate::BitWriter<'a, REG, Lpuart3>; -impl<'a, REG> Lpuart3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart3::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart3::Enabled) - } -} -#[doc = "LPUART4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart4 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART4` reader - LPUART4"] -pub type Lpuart4R = crate::BitReader; -impl Lpuart4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart4 { - match self.bits { - false => Lpuart4::Disabled, - true => Lpuart4::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart4::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart4::Enabled - } -} -#[doc = "Field `LPUART4` writer - LPUART4"] -pub type Lpuart4W<'a, REG> = crate::BitWriter<'a, REG, Lpuart4>; -impl<'a, REG> Lpuart4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart4::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart4::Enabled) - } -} -#[doc = "USB0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usb0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usb0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USB0` reader - USB0"] -pub type Usb0R = crate::BitReader; -impl Usb0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Usb0 { - match self.bits { - false => Usb0::Disabled, - true => Usb0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Usb0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Usb0::Enabled - } -} -#[doc = "Field `USB0` writer - USB0"] -pub type Usb0W<'a, REG> = crate::BitWriter<'a, REG, Usb0>; -impl<'a, REG> Usb0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Usb0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Usb0::Enabled) - } -} -#[doc = "QDC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Qdc0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Qdc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `QDC0` reader - QDC0"] -pub type Qdc0R = crate::BitReader; -impl Qdc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Qdc0 { - match self.bits { - false => Qdc0::Disabled, - true => Qdc0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Qdc0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Qdc0::Enabled - } -} -#[doc = "Field `QDC0` writer - QDC0"] -pub type Qdc0W<'a, REG> = crate::BitWriter<'a, REG, Qdc0>; -impl<'a, REG> Qdc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Qdc0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Qdc0::Enabled) - } -} -#[doc = "QDC1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Qdc1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Qdc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `QDC1` reader - QDC1"] -pub type Qdc1R = crate::BitReader; -impl Qdc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Qdc1 { - match self.bits { - false => Qdc1::Disabled, - true => Qdc1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Qdc1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Qdc1::Enabled - } -} -#[doc = "Field `QDC1` writer - QDC1"] -pub type Qdc1W<'a, REG> = crate::BitWriter<'a, REG, Qdc1>; -impl<'a, REG> Qdc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Qdc1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Qdc1::Enabled) - } -} -#[doc = "FLEXPWM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexpwm0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexpwm0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXPWM0` reader - FLEXPWM0"] -pub type Flexpwm0R = crate::BitReader; -impl Flexpwm0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexpwm0 { - match self.bits { - false => Flexpwm0::Disabled, - true => Flexpwm0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexpwm0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexpwm0::Enabled - } -} -#[doc = "Field `FLEXPWM0` writer - FLEXPWM0"] -pub type Flexpwm0W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm0>; -impl<'a, REG> Flexpwm0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexpwm0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexpwm0::Enabled) - } -} -impl R { - #[doc = "Bit 0 - INPUTMUX0"] - #[inline(always)] - pub fn inputmux0(&self) -> Inputmux0R { - Inputmux0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - I3C0"] - #[inline(always)] - pub fn i3c0(&self) -> I3c0R { - I3c0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - CTIMER0"] - #[inline(always)] - pub fn ctimer0(&self) -> Ctimer0R { - Ctimer0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - CTIMER1"] - #[inline(always)] - pub fn ctimer1(&self) -> Ctimer1R { - Ctimer1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - CTIMER2"] - #[inline(always)] - pub fn ctimer2(&self) -> Ctimer2R { - Ctimer2R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - CTIMER3"] - #[inline(always)] - pub fn ctimer3(&self) -> Ctimer3R { - Ctimer3R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - CTIMER4"] - #[inline(always)] - pub fn ctimer4(&self) -> Ctimer4R { - Ctimer4R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - FREQME"] - #[inline(always)] - pub fn freqme(&self) -> FreqmeR { - FreqmeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - UTICK0"] - #[inline(always)] - pub fn utick0(&self) -> Utick0R { - Utick0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - WWDT0"] - #[inline(always)] - pub fn wwdt0(&self) -> Wwdt0R { - Wwdt0R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SMARTDMA0"] - #[inline(always)] - pub fn smartdma0(&self) -> Smartdma0R { - Smartdma0R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - DMA0"] - #[inline(always)] - pub fn dma0(&self) -> Dma0R { - Dma0R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - AOI0"] - #[inline(always)] - pub fn aoi0(&self) -> Aoi0R { - Aoi0R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - CRC0"] - #[inline(always)] - pub fn crc0(&self) -> Crc0R { - Crc0R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - EIM0"] - #[inline(always)] - pub fn eim0(&self) -> Eim0R { - Eim0R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - ERM0"] - #[inline(always)] - pub fn erm0(&self) -> Erm0R { - Erm0R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - FMC"] - #[inline(always)] - pub fn fmc(&self) -> FmcR { - FmcR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - AOI1"] - #[inline(always)] - pub fn aoi1(&self) -> Aoi1R { - Aoi1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - FLEXIO0"] - #[inline(always)] - pub fn flexio0(&self) -> Flexio0R { - Flexio0R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - LPI2C0"] - #[inline(always)] - pub fn lpi2c0(&self) -> Lpi2c0R { - Lpi2c0R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LPI2C1"] - #[inline(always)] - pub fn lpi2c1(&self) -> Lpi2c1R { - Lpi2c1R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LPSPI0"] - #[inline(always)] - pub fn lpspi0(&self) -> Lpspi0R { - Lpspi0R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LPSPI1"] - #[inline(always)] - pub fn lpspi1(&self) -> Lpspi1R { - Lpspi1R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - LPUART0"] - #[inline(always)] - pub fn lpuart0(&self) -> Lpuart0R { - Lpuart0R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - LPUART1"] - #[inline(always)] - pub fn lpuart1(&self) -> Lpuart1R { - Lpuart1R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - LPUART2"] - #[inline(always)] - pub fn lpuart2(&self) -> Lpuart2R { - Lpuart2R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - LPUART3"] - #[inline(always)] - pub fn lpuart3(&self) -> Lpuart3R { - Lpuart3R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - LPUART4"] - #[inline(always)] - pub fn lpuart4(&self) -> Lpuart4R { - Lpuart4R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - USB0"] - #[inline(always)] - pub fn usb0(&self) -> Usb0R { - Usb0R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - QDC0"] - #[inline(always)] - pub fn qdc0(&self) -> Qdc0R { - Qdc0R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - QDC1"] - #[inline(always)] - pub fn qdc1(&self) -> Qdc1R { - Qdc1R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - FLEXPWM0"] - #[inline(always)] - pub fn flexpwm0(&self) -> Flexpwm0R { - Flexpwm0R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - INPUTMUX0"] - #[inline(always)] - pub fn inputmux0(&mut self) -> Inputmux0W { - Inputmux0W::new(self, 0) - } - #[doc = "Bit 1 - I3C0"] - #[inline(always)] - pub fn i3c0(&mut self) -> I3c0W { - I3c0W::new(self, 1) - } - #[doc = "Bit 2 - CTIMER0"] - #[inline(always)] - pub fn ctimer0(&mut self) -> Ctimer0W { - Ctimer0W::new(self, 2) - } - #[doc = "Bit 3 - CTIMER1"] - #[inline(always)] - pub fn ctimer1(&mut self) -> Ctimer1W { - Ctimer1W::new(self, 3) - } - #[doc = "Bit 4 - CTIMER2"] - #[inline(always)] - pub fn ctimer2(&mut self) -> Ctimer2W { - Ctimer2W::new(self, 4) - } - #[doc = "Bit 5 - CTIMER3"] - #[inline(always)] - pub fn ctimer3(&mut self) -> Ctimer3W { - Ctimer3W::new(self, 5) - } - #[doc = "Bit 6 - CTIMER4"] - #[inline(always)] - pub fn ctimer4(&mut self) -> Ctimer4W { - Ctimer4W::new(self, 6) - } - #[doc = "Bit 7 - FREQME"] - #[inline(always)] - pub fn freqme(&mut self) -> FreqmeW { - FreqmeW::new(self, 7) - } - #[doc = "Bit 8 - UTICK0"] - #[inline(always)] - pub fn utick0(&mut self) -> Utick0W { - Utick0W::new(self, 8) - } - #[doc = "Bit 9 - WWDT0"] - #[inline(always)] - pub fn wwdt0(&mut self) -> Wwdt0W { - Wwdt0W::new(self, 9) - } - #[doc = "Bit 10 - SMARTDMA0"] - #[inline(always)] - pub fn smartdma0(&mut self) -> Smartdma0W { - Smartdma0W::new(self, 10) - } - #[doc = "Bit 11 - DMA0"] - #[inline(always)] - pub fn dma0(&mut self) -> Dma0W { - Dma0W::new(self, 11) - } - #[doc = "Bit 12 - AOI0"] - #[inline(always)] - pub fn aoi0(&mut self) -> Aoi0W { - Aoi0W::new(self, 12) - } - #[doc = "Bit 13 - CRC0"] - #[inline(always)] - pub fn crc0(&mut self) -> Crc0W { - Crc0W::new(self, 13) - } - #[doc = "Bit 14 - EIM0"] - #[inline(always)] - pub fn eim0(&mut self) -> Eim0W { - Eim0W::new(self, 14) - } - #[doc = "Bit 15 - ERM0"] - #[inline(always)] - pub fn erm0(&mut self) -> Erm0W { - Erm0W::new(self, 15) - } - #[doc = "Bit 16 - FMC"] - #[inline(always)] - pub fn fmc(&mut self) -> FmcW { - FmcW::new(self, 16) - } - #[doc = "Bit 17 - AOI1"] - #[inline(always)] - pub fn aoi1(&mut self) -> Aoi1W { - Aoi1W::new(self, 17) - } - #[doc = "Bit 18 - FLEXIO0"] - #[inline(always)] - pub fn flexio0(&mut self) -> Flexio0W { - Flexio0W::new(self, 18) - } - #[doc = "Bit 19 - LPI2C0"] - #[inline(always)] - pub fn lpi2c0(&mut self) -> Lpi2c0W { - Lpi2c0W::new(self, 19) - } - #[doc = "Bit 20 - LPI2C1"] - #[inline(always)] - pub fn lpi2c1(&mut self) -> Lpi2c1W { - Lpi2c1W::new(self, 20) - } - #[doc = "Bit 21 - LPSPI0"] - #[inline(always)] - pub fn lpspi0(&mut self) -> Lpspi0W { - Lpspi0W::new(self, 21) - } - #[doc = "Bit 22 - LPSPI1"] - #[inline(always)] - pub fn lpspi1(&mut self) -> Lpspi1W { - Lpspi1W::new(self, 22) - } - #[doc = "Bit 23 - LPUART0"] - #[inline(always)] - pub fn lpuart0(&mut self) -> Lpuart0W { - Lpuart0W::new(self, 23) - } - #[doc = "Bit 24 - LPUART1"] - #[inline(always)] - pub fn lpuart1(&mut self) -> Lpuart1W { - Lpuart1W::new(self, 24) - } - #[doc = "Bit 25 - LPUART2"] - #[inline(always)] - pub fn lpuart2(&mut self) -> Lpuart2W { - Lpuart2W::new(self, 25) - } - #[doc = "Bit 26 - LPUART3"] - #[inline(always)] - pub fn lpuart3(&mut self) -> Lpuart3W { - Lpuart3W::new(self, 26) - } - #[doc = "Bit 27 - LPUART4"] - #[inline(always)] - pub fn lpuart4(&mut self) -> Lpuart4W { - Lpuart4W::new(self, 27) - } - #[doc = "Bit 28 - USB0"] - #[inline(always)] - pub fn usb0(&mut self) -> Usb0W { - Usb0W::new(self, 28) - } - #[doc = "Bit 29 - QDC0"] - #[inline(always)] - pub fn qdc0(&mut self) -> Qdc0W { - Qdc0W::new(self, 29) - } - #[doc = "Bit 30 - QDC1"] - #[inline(always)] - pub fn qdc1(&mut self) -> Qdc1W { - Qdc1W::new(self, 30) - } - #[doc = "Bit 31 - FLEXPWM0"] - #[inline(always)] - pub fn flexpwm0(&mut self) -> Flexpwm0W { - Flexpwm0W::new(self, 31) - } -} -#[doc = "AHB Clock Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc0Spec; -impl crate::RegisterSpec for MrccGlbCc0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_cc0::R`](R) reader structure"] -impl crate::Readable for MrccGlbCc0Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc0::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC0 to value 0x0001_0000"] -impl crate::Resettable for MrccGlbCc0Spec { - const RESET_VALUE: u32 = 0x0001_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs deleted file mode 100644 index 9a46b4928..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_clr.rs +++ /dev/null @@ -1,24 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC0_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "AHB Clock Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc0ClrSpec; -impl crate::RegisterSpec for MrccGlbCc0ClrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc0_clr::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc0ClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC0_CLR to value 0x0001_0000"] -impl crate::Resettable for MrccGlbCc0ClrSpec { - const RESET_VALUE: u32 = 0x0001_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs deleted file mode 100644 index a328615de..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc0_set.rs +++ /dev/null @@ -1,24 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC0_SET` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "AHB Clock Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc0SetSpec; -impl crate::RegisterSpec for MrccGlbCc0SetSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc0_set::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc0SetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC0_SET to value 0x0001_0000"] -impl crate::Resettable for MrccGlbCc0SetSpec { - const RESET_VALUE: u32 = 0x0001_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs deleted file mode 100644 index 5d7971822..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1.rs +++ /dev/null @@ -1,1911 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC1` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_CC1` writer"] -pub type W = crate::W; -#[doc = "FLEXPWM1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexpwm1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexpwm1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXPWM1` reader - FLEXPWM1"] -pub type Flexpwm1R = crate::BitReader; -impl Flexpwm1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexpwm1 { - match self.bits { - false => Flexpwm1::Disabled, - true => Flexpwm1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexpwm1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexpwm1::Enabled - } -} -#[doc = "Field `FLEXPWM1` writer - FLEXPWM1"] -pub type Flexpwm1W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm1>; -impl<'a, REG> Flexpwm1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexpwm1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexpwm1::Enabled) - } -} -#[doc = "OSTIMER0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ostimer0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ostimer0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSTIMER0` reader - OSTIMER0"] -pub type Ostimer0R = crate::BitReader; -impl Ostimer0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ostimer0 { - match self.bits { - false => Ostimer0::Disabled, - true => Ostimer0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ostimer0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ostimer0::Enabled - } -} -#[doc = "Field `OSTIMER0` writer - OSTIMER0"] -pub type Ostimer0W<'a, REG> = crate::BitWriter<'a, REG, Ostimer0>; -impl<'a, REG> Ostimer0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ostimer0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ostimer0::Enabled) - } -} -#[doc = "ADC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC0` reader - ADC0"] -pub type Adc0R = crate::BitReader; -impl Adc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc0 { - match self.bits { - false => Adc0::Disabled, - true => Adc0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc0::Enabled - } -} -#[doc = "Field `ADC0` writer - ADC0"] -pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG, Adc0>; -impl<'a, REG> Adc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc0::Enabled) - } -} -#[doc = "ADC1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC1` reader - ADC1"] -pub type Adc1R = crate::BitReader; -impl Adc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc1 { - match self.bits { - false => Adc1::Disabled, - true => Adc1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc1::Enabled - } -} -#[doc = "Field `ADC1` writer - ADC1"] -pub type Adc1W<'a, REG> = crate::BitWriter<'a, REG, Adc1>; -impl<'a, REG> Adc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc1::Enabled) - } -} -#[doc = "CMP0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP0` reader - CMP0"] -pub type Cmp0R = crate::BitReader; -impl Cmp0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp0 { - match self.bits { - false => Cmp0::Disabled, - true => Cmp0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp0::Enabled - } -} -#[doc = "Field `CMP0` writer - CMP0"] -pub type Cmp0W<'a, REG> = crate::BitWriter<'a, REG, Cmp0>; -impl<'a, REG> Cmp0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp0::Enabled) - } -} -#[doc = "CMP1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP1` reader - CMP1"] -pub type Cmp1R = crate::BitReader; -impl Cmp1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp1 { - match self.bits { - false => Cmp1::Disabled, - true => Cmp1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp1::Enabled - } -} -#[doc = "Field `CMP1` writer - CMP1"] -pub type Cmp1W<'a, REG> = crate::BitWriter<'a, REG, Cmp1>; -impl<'a, REG> Cmp1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp1::Enabled) - } -} -#[doc = "CMP2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP2` reader - CMP2"] -pub type Cmp2R = crate::BitReader; -impl Cmp2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp2 { - match self.bits { - false => Cmp2::Disabled, - true => Cmp2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp2::Enabled - } -} -#[doc = "Field `CMP2` writer - CMP2"] -pub type Cmp2W<'a, REG> = crate::BitWriter<'a, REG, Cmp2>; -impl<'a, REG> Cmp2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp2::Enabled) - } -} -#[doc = "DAC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dac0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dac0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAC0` reader - DAC0"] -pub type Dac0R = crate::BitReader; -impl Dac0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dac0 { - match self.bits { - false => Dac0::Disabled, - true => Dac0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dac0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dac0::Enabled - } -} -#[doc = "Field `DAC0` writer - DAC0"] -pub type Dac0W<'a, REG> = crate::BitWriter<'a, REG, Dac0>; -impl<'a, REG> Dac0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dac0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dac0::Enabled) - } -} -#[doc = "OPAMP0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP0` reader - OPAMP0"] -pub type Opamp0R = crate::BitReader; -impl Opamp0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp0 { - match self.bits { - false => Opamp0::Disabled, - true => Opamp0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp0::Enabled - } -} -#[doc = "Field `OPAMP0` writer - OPAMP0"] -pub type Opamp0W<'a, REG> = crate::BitWriter<'a, REG, Opamp0>; -impl<'a, REG> Opamp0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp0::Enabled) - } -} -#[doc = "OPAMP1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP1` reader - OPAMP1"] -pub type Opamp1R = crate::BitReader; -impl Opamp1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp1 { - match self.bits { - false => Opamp1::Disabled, - true => Opamp1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp1::Enabled - } -} -#[doc = "Field `OPAMP1` writer - OPAMP1"] -pub type Opamp1W<'a, REG> = crate::BitWriter<'a, REG, Opamp1>; -impl<'a, REG> Opamp1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp1::Enabled) - } -} -#[doc = "OPAMP2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP2` reader - OPAMP2"] -pub type Opamp2R = crate::BitReader; -impl Opamp2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp2 { - match self.bits { - false => Opamp2::Disabled, - true => Opamp2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp2::Enabled - } -} -#[doc = "Field `OPAMP2` writer - OPAMP2"] -pub type Opamp2W<'a, REG> = crate::BitWriter<'a, REG, Opamp2>; -impl<'a, REG> Opamp2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp2::Enabled) - } -} -#[doc = "OPAMP3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp3 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP3` reader - OPAMP3"] -pub type Opamp3R = crate::BitReader; -impl Opamp3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp3 { - match self.bits { - false => Opamp3::Disabled, - true => Opamp3::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp3::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp3::Enabled - } -} -#[doc = "Field `OPAMP3` writer - OPAMP3"] -pub type Opamp3W<'a, REG> = crate::BitWriter<'a, REG, Opamp3>; -impl<'a, REG> Opamp3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp3::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp3::Enabled) - } -} -#[doc = "PORT0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT0` reader - PORT0"] -pub type Port0R = crate::BitReader; -impl Port0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port0 { - match self.bits { - false => Port0::Disabled, - true => Port0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port0::Enabled - } -} -#[doc = "Field `PORT0` writer - PORT0"] -pub type Port0W<'a, REG> = crate::BitWriter<'a, REG, Port0>; -impl<'a, REG> Port0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port0::Enabled) - } -} -#[doc = "PORT1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT1` reader - PORT1"] -pub type Port1R = crate::BitReader; -impl Port1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port1 { - match self.bits { - false => Port1::Disabled, - true => Port1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port1::Enabled - } -} -#[doc = "Field `PORT1` writer - PORT1"] -pub type Port1W<'a, REG> = crate::BitWriter<'a, REG, Port1>; -impl<'a, REG> Port1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port1::Enabled) - } -} -#[doc = "PORT2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT2` reader - PORT2"] -pub type Port2R = crate::BitReader; -impl Port2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port2 { - match self.bits { - false => Port2::Disabled, - true => Port2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port2::Enabled - } -} -#[doc = "Field `PORT2` writer - PORT2"] -pub type Port2W<'a, REG> = crate::BitWriter<'a, REG, Port2>; -impl<'a, REG> Port2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port2::Enabled) - } -} -#[doc = "PORT3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port3 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT3` reader - PORT3"] -pub type Port3R = crate::BitReader; -impl Port3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port3 { - match self.bits { - false => Port3::Disabled, - true => Port3::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port3::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port3::Enabled - } -} -#[doc = "Field `PORT3` writer - PORT3"] -pub type Port3W<'a, REG> = crate::BitWriter<'a, REG, Port3>; -impl<'a, REG> Port3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port3::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port3::Enabled) - } -} -#[doc = "PORT4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port4 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT4` reader - PORT4"] -pub type Port4R = crate::BitReader; -impl Port4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port4 { - match self.bits { - false => Port4::Disabled, - true => Port4::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port4::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port4::Enabled - } -} -#[doc = "Field `PORT4` writer - PORT4"] -pub type Port4W<'a, REG> = crate::BitWriter<'a, REG, Port4>; -impl<'a, REG> Port4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port4::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port4::Enabled) - } -} -#[doc = "SLCD0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slcd0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slcd0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLCD0` reader - SLCD0"] -pub type Slcd0R = crate::BitReader; -impl Slcd0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slcd0 { - match self.bits { - false => Slcd0::Disabled, - true => Slcd0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Slcd0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Slcd0::Enabled - } -} -#[doc = "Field `SLCD0` writer - SLCD0"] -pub type Slcd0W<'a, REG> = crate::BitWriter<'a, REG, Slcd0>; -impl<'a, REG> Slcd0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Slcd0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Slcd0::Enabled) - } -} -#[doc = "FLEXCAN0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexcan0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexcan0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXCAN0` reader - FLEXCAN0"] -pub type Flexcan0R = crate::BitReader; -impl Flexcan0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexcan0 { - match self.bits { - false => Flexcan0::Disabled, - true => Flexcan0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexcan0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexcan0::Enabled - } -} -#[doc = "Field `FLEXCAN0` writer - FLEXCAN0"] -pub type Flexcan0W<'a, REG> = crate::BitWriter<'a, REG, Flexcan0>; -impl<'a, REG> Flexcan0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexcan0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexcan0::Enabled) - } -} -#[doc = "FLEXCAN1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexcan1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexcan1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXCAN1` reader - FLEXCAN1"] -pub type Flexcan1R = crate::BitReader; -impl Flexcan1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexcan1 { - match self.bits { - false => Flexcan1::Disabled, - true => Flexcan1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexcan1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexcan1::Enabled - } -} -#[doc = "Field `FLEXCAN1` writer - FLEXCAN1"] -pub type Flexcan1W<'a, REG> = crate::BitWriter<'a, REG, Flexcan1>; -impl<'a, REG> Flexcan1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexcan1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexcan1::Enabled) - } -} -#[doc = "LPI2C2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C2` reader - LPI2C2"] -pub type Lpi2c2R = crate::BitReader; -impl Lpi2c2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c2 { - match self.bits { - false => Lpi2c2::Disabled, - true => Lpi2c2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c2::Enabled - } -} -#[doc = "Field `LPI2C2` writer - LPI2C2"] -pub type Lpi2c2W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c2>; -impl<'a, REG> Lpi2c2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c2::Enabled) - } -} -#[doc = "LPI2C3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c3 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C3` reader - LPI2C3"] -pub type Lpi2c3R = crate::BitReader; -impl Lpi2c3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c3 { - match self.bits { - false => Lpi2c3::Disabled, - true => Lpi2c3::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c3::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c3::Enabled - } -} -#[doc = "Field `LPI2C3` writer - LPI2C3"] -pub type Lpi2c3W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c3>; -impl<'a, REG> Lpi2c3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c3::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c3::Enabled) - } -} -#[doc = "LPUART5\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart5 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART5` reader - LPUART5"] -pub type Lpuart5R = crate::BitReader; -impl Lpuart5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart5 { - match self.bits { - false => Lpuart5::Disabled, - true => Lpuart5::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart5::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart5::Enabled - } -} -#[doc = "Field `LPUART5` writer - LPUART5"] -pub type Lpuart5W<'a, REG> = crate::BitWriter<'a, REG, Lpuart5>; -impl<'a, REG> Lpuart5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart5::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart5::Enabled) - } -} -#[doc = "TDET0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tdet0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tdet0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TDET0` reader - TDET0"] -pub type Tdet0R = crate::BitReader; -impl Tdet0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tdet0 { - match self.bits { - false => Tdet0::Disabled, - true => Tdet0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Tdet0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Tdet0::Enabled - } -} -#[doc = "Field `TDET0` writer - TDET0"] -pub type Tdet0W<'a, REG> = crate::BitWriter<'a, REG, Tdet0>; -impl<'a, REG> Tdet0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Tdet0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Tdet0::Enabled) - } -} -#[doc = "PKC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pkc0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pkc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PKC0` reader - PKC0"] -pub type Pkc0R = crate::BitReader; -impl Pkc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pkc0 { - match self.bits { - false => Pkc0::Disabled, - true => Pkc0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pkc0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pkc0::Enabled - } -} -#[doc = "Field `PKC0` writer - PKC0"] -pub type Pkc0W<'a, REG> = crate::BitWriter<'a, REG, Pkc0>; -impl<'a, REG> Pkc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pkc0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pkc0::Enabled) - } -} -#[doc = "SGI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sgi0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sgi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SGI0` reader - SGI0"] -pub type Sgi0R = crate::BitReader; -impl Sgi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sgi0 { - match self.bits { - false => Sgi0::Disabled, - true => Sgi0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sgi0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sgi0::Enabled - } -} -#[doc = "Field `SGI0` writer - SGI0"] -pub type Sgi0W<'a, REG> = crate::BitWriter<'a, REG, Sgi0>; -impl<'a, REG> Sgi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sgi0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sgi0::Enabled) - } -} -#[doc = "TRNG0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trng0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trng0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRNG0` reader - TRNG0"] -pub type Trng0R = crate::BitReader; -impl Trng0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trng0 { - match self.bits { - false => Trng0::Disabled, - true => Trng0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Trng0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Trng0::Enabled - } -} -#[doc = "Field `TRNG0` writer - TRNG0"] -pub type Trng0W<'a, REG> = crate::BitWriter<'a, REG, Trng0>; -impl<'a, REG> Trng0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Trng0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Trng0::Enabled) - } -} -#[doc = "UDF0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Udf0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Udf0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UDF0` reader - UDF0"] -pub type Udf0R = crate::BitReader; -impl Udf0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Udf0 { - match self.bits { - false => Udf0::Disabled, - true => Udf0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Udf0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Udf0::Enabled - } -} -#[doc = "Field `UDF0` writer - UDF0"] -pub type Udf0W<'a, REG> = crate::BitWriter<'a, REG, Udf0>; -impl<'a, REG> Udf0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Udf0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Udf0::Enabled) - } -} -#[doc = "ADC2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC2` reader - ADC2"] -pub type Adc2R = crate::BitReader; -impl Adc2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc2 { - match self.bits { - false => Adc2::Disabled, - true => Adc2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc2::Enabled - } -} -#[doc = "Field `ADC2` writer - ADC2"] -pub type Adc2W<'a, REG> = crate::BitWriter<'a, REG, Adc2>; -impl<'a, REG> Adc2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc2::Enabled) - } -} -#[doc = "ADC3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc3 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC3` reader - ADC3"] -pub type Adc3R = crate::BitReader; -impl Adc3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc3 { - match self.bits { - false => Adc3::Disabled, - true => Adc3::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc3::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc3::Enabled - } -} -#[doc = "Field `ADC3` writer - ADC3"] -pub type Adc3W<'a, REG> = crate::BitWriter<'a, REG, Adc3>; -impl<'a, REG> Adc3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc3::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc3::Enabled) - } -} -impl R { - #[doc = "Bit 0 - FLEXPWM1"] - #[inline(always)] - pub fn flexpwm1(&self) -> Flexpwm1R { - Flexpwm1R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - OSTIMER0"] - #[inline(always)] - pub fn ostimer0(&self) -> Ostimer0R { - Ostimer0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - ADC0"] - #[inline(always)] - pub fn adc0(&self) -> Adc0R { - Adc0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - ADC1"] - #[inline(always)] - pub fn adc1(&self) -> Adc1R { - Adc1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - CMP0"] - #[inline(always)] - pub fn cmp0(&self) -> Cmp0R { - Cmp0R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - CMP1"] - #[inline(always)] - pub fn cmp1(&self) -> Cmp1R { - Cmp1R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - CMP2"] - #[inline(always)] - pub fn cmp2(&self) -> Cmp2R { - Cmp2R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - DAC0"] - #[inline(always)] - pub fn dac0(&self) -> Dac0R { - Dac0R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - OPAMP0"] - #[inline(always)] - pub fn opamp0(&self) -> Opamp0R { - Opamp0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - OPAMP1"] - #[inline(always)] - pub fn opamp1(&self) -> Opamp1R { - Opamp1R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - OPAMP2"] - #[inline(always)] - pub fn opamp2(&self) -> Opamp2R { - Opamp2R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - OPAMP3"] - #[inline(always)] - pub fn opamp3(&self) -> Opamp3R { - Opamp3R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - PORT0"] - #[inline(always)] - pub fn port0(&self) -> Port0R { - Port0R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - PORT1"] - #[inline(always)] - pub fn port1(&self) -> Port1R { - Port1R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - PORT2"] - #[inline(always)] - pub fn port2(&self) -> Port2R { - Port2R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - PORT3"] - #[inline(always)] - pub fn port3(&self) -> Port3R { - Port3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - PORT4"] - #[inline(always)] - pub fn port4(&self) -> Port4R { - Port4R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - SLCD0"] - #[inline(always)] - pub fn slcd0(&self) -> Slcd0R { - Slcd0R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - FLEXCAN0"] - #[inline(always)] - pub fn flexcan0(&self) -> Flexcan0R { - Flexcan0R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - FLEXCAN1"] - #[inline(always)] - pub fn flexcan1(&self) -> Flexcan1R { - Flexcan1R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LPI2C2"] - #[inline(always)] - pub fn lpi2c2(&self) -> Lpi2c2R { - Lpi2c2R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LPI2C3"] - #[inline(always)] - pub fn lpi2c3(&self) -> Lpi2c3R { - Lpi2c3R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LPUART5"] - #[inline(always)] - pub fn lpuart5(&self) -> Lpuart5R { - Lpuart5R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - TDET0"] - #[inline(always)] - pub fn tdet0(&self) -> Tdet0R { - Tdet0R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - PKC0"] - #[inline(always)] - pub fn pkc0(&self) -> Pkc0R { - Pkc0R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - SGI0"] - #[inline(always)] - pub fn sgi0(&self) -> Sgi0R { - Sgi0R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - TRNG0"] - #[inline(always)] - pub fn trng0(&self) -> Trng0R { - Trng0R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - UDF0"] - #[inline(always)] - pub fn udf0(&self) -> Udf0R { - Udf0R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - ADC2"] - #[inline(always)] - pub fn adc2(&self) -> Adc2R { - Adc2R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - ADC3"] - #[inline(always)] - pub fn adc3(&self) -> Adc3R { - Adc3R::new(((self.bits >> 29) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FLEXPWM1"] - #[inline(always)] - pub fn flexpwm1(&mut self) -> Flexpwm1W { - Flexpwm1W::new(self, 0) - } - #[doc = "Bit 1 - OSTIMER0"] - #[inline(always)] - pub fn ostimer0(&mut self) -> Ostimer0W { - Ostimer0W::new(self, 1) - } - #[doc = "Bit 2 - ADC0"] - #[inline(always)] - pub fn adc0(&mut self) -> Adc0W { - Adc0W::new(self, 2) - } - #[doc = "Bit 3 - ADC1"] - #[inline(always)] - pub fn adc1(&mut self) -> Adc1W { - Adc1W::new(self, 3) - } - #[doc = "Bit 4 - CMP0"] - #[inline(always)] - pub fn cmp0(&mut self) -> Cmp0W { - Cmp0W::new(self, 4) - } - #[doc = "Bit 5 - CMP1"] - #[inline(always)] - pub fn cmp1(&mut self) -> Cmp1W { - Cmp1W::new(self, 5) - } - #[doc = "Bit 6 - CMP2"] - #[inline(always)] - pub fn cmp2(&mut self) -> Cmp2W { - Cmp2W::new(self, 6) - } - #[doc = "Bit 7 - DAC0"] - #[inline(always)] - pub fn dac0(&mut self) -> Dac0W { - Dac0W::new(self, 7) - } - #[doc = "Bit 8 - OPAMP0"] - #[inline(always)] - pub fn opamp0(&mut self) -> Opamp0W { - Opamp0W::new(self, 8) - } - #[doc = "Bit 9 - OPAMP1"] - #[inline(always)] - pub fn opamp1(&mut self) -> Opamp1W { - Opamp1W::new(self, 9) - } - #[doc = "Bit 10 - OPAMP2"] - #[inline(always)] - pub fn opamp2(&mut self) -> Opamp2W { - Opamp2W::new(self, 10) - } - #[doc = "Bit 11 - OPAMP3"] - #[inline(always)] - pub fn opamp3(&mut self) -> Opamp3W { - Opamp3W::new(self, 11) - } - #[doc = "Bit 12 - PORT0"] - #[inline(always)] - pub fn port0(&mut self) -> Port0W { - Port0W::new(self, 12) - } - #[doc = "Bit 13 - PORT1"] - #[inline(always)] - pub fn port1(&mut self) -> Port1W { - Port1W::new(self, 13) - } - #[doc = "Bit 14 - PORT2"] - #[inline(always)] - pub fn port2(&mut self) -> Port2W { - Port2W::new(self, 14) - } - #[doc = "Bit 15 - PORT3"] - #[inline(always)] - pub fn port3(&mut self) -> Port3W { - Port3W::new(self, 15) - } - #[doc = "Bit 16 - PORT4"] - #[inline(always)] - pub fn port4(&mut self) -> Port4W { - Port4W::new(self, 16) - } - #[doc = "Bit 17 - SLCD0"] - #[inline(always)] - pub fn slcd0(&mut self) -> Slcd0W { - Slcd0W::new(self, 17) - } - #[doc = "Bit 18 - FLEXCAN0"] - #[inline(always)] - pub fn flexcan0(&mut self) -> Flexcan0W { - Flexcan0W::new(self, 18) - } - #[doc = "Bit 19 - FLEXCAN1"] - #[inline(always)] - pub fn flexcan1(&mut self) -> Flexcan1W { - Flexcan1W::new(self, 19) - } - #[doc = "Bit 20 - LPI2C2"] - #[inline(always)] - pub fn lpi2c2(&mut self) -> Lpi2c2W { - Lpi2c2W::new(self, 20) - } - #[doc = "Bit 21 - LPI2C3"] - #[inline(always)] - pub fn lpi2c3(&mut self) -> Lpi2c3W { - Lpi2c3W::new(self, 21) - } - #[doc = "Bit 22 - LPUART5"] - #[inline(always)] - pub fn lpuart5(&mut self) -> Lpuart5W { - Lpuart5W::new(self, 22) - } - #[doc = "Bit 23 - TDET0"] - #[inline(always)] - pub fn tdet0(&mut self) -> Tdet0W { - Tdet0W::new(self, 23) - } - #[doc = "Bit 24 - PKC0"] - #[inline(always)] - pub fn pkc0(&mut self) -> Pkc0W { - Pkc0W::new(self, 24) - } - #[doc = "Bit 25 - SGI0"] - #[inline(always)] - pub fn sgi0(&mut self) -> Sgi0W { - Sgi0W::new(self, 25) - } - #[doc = "Bit 26 - TRNG0"] - #[inline(always)] - pub fn trng0(&mut self) -> Trng0W { - Trng0W::new(self, 26) - } - #[doc = "Bit 27 - UDF0"] - #[inline(always)] - pub fn udf0(&mut self) -> Udf0W { - Udf0W::new(self, 27) - } - #[doc = "Bit 28 - ADC2"] - #[inline(always)] - pub fn adc2(&mut self) -> Adc2W { - Adc2W::new(self, 28) - } - #[doc = "Bit 29 - ADC3"] - #[inline(always)] - pub fn adc3(&mut self) -> Adc3W { - Adc3W::new(self, 29) - } -} -#[doc = "AHB Clock Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc1Spec; -impl crate::RegisterSpec for MrccGlbCc1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_cc1::R`](R) reader structure"] -impl crate::Readable for MrccGlbCc1Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc1::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC1 to value 0"] -impl crate::Resettable for MrccGlbCc1Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs deleted file mode 100644 index 0e44ab54d..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_clr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC1_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "AHB Clock Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc1ClrSpec; -impl crate::RegisterSpec for MrccGlbCc1ClrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc1_clr::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc1ClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC1_CLR to value 0"] -impl crate::Resettable for MrccGlbCc1ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs deleted file mode 100644 index 16204fd7c..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc1_set.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC1_SET` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "AHB Clock Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc1_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc1SetSpec; -impl crate::RegisterSpec for MrccGlbCc1SetSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc1_set::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc1SetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC1_SET to value 0"] -impl crate::Resettable for MrccGlbCc1SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs deleted file mode 100644 index de25d079c..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2.rs +++ /dev/null @@ -1,651 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC2` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_CC2` writer"] -pub type W = crate::W; -#[doc = "RAMA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rama { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rama) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMA` reader - RAMA"] -pub type RamaR = crate::BitReader; -impl RamaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rama { - match self.bits { - false => Rama::Disabled, - true => Rama::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Rama::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Rama::Enabled - } -} -#[doc = "Field `RAMA` writer - RAMA"] -pub type RamaW<'a, REG> = crate::BitWriter<'a, REG, Rama>; -impl<'a, REG> RamaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Rama::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Rama::Enabled) - } -} -#[doc = "RAMB\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ramb { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ramb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMB` reader - RAMB"] -pub type RambR = crate::BitReader; -impl RambR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ramb { - match self.bits { - false => Ramb::Disabled, - true => Ramb::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ramb::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ramb::Enabled - } -} -#[doc = "Field `RAMB` writer - RAMB"] -pub type RambW<'a, REG> = crate::BitWriter<'a, REG, Ramb>; -impl<'a, REG> RambW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ramb::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ramb::Enabled) - } -} -#[doc = "RAMC\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ramc { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ramc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMC` reader - RAMC"] -pub type RamcR = crate::BitReader; -impl RamcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ramc { - match self.bits { - false => Ramc::Disabled, - true => Ramc::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ramc::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ramc::Enabled - } -} -#[doc = "Field `RAMC` writer - RAMC"] -pub type RamcW<'a, REG> = crate::BitWriter<'a, REG, Ramc>; -impl<'a, REG> RamcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ramc::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ramc::Enabled) - } -} -#[doc = "GPIO0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO0` reader - GPIO0"] -pub type Gpio0R = crate::BitReader; -impl Gpio0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio0 { - match self.bits { - false => Gpio0::Disabled, - true => Gpio0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio0::Enabled - } -} -#[doc = "Field `GPIO0` writer - GPIO0"] -pub type Gpio0W<'a, REG> = crate::BitWriter<'a, REG, Gpio0>; -impl<'a, REG> Gpio0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio0::Enabled) - } -} -#[doc = "GPIO1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio1 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO1` reader - GPIO1"] -pub type Gpio1R = crate::BitReader; -impl Gpio1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio1 { - match self.bits { - false => Gpio1::Disabled, - true => Gpio1::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio1::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio1::Enabled - } -} -#[doc = "Field `GPIO1` writer - GPIO1"] -pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG, Gpio1>; -impl<'a, REG> Gpio1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio1::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio1::Enabled) - } -} -#[doc = "GPIO2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio2 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO2` reader - GPIO2"] -pub type Gpio2R = crate::BitReader; -impl Gpio2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio2 { - match self.bits { - false => Gpio2::Disabled, - true => Gpio2::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio2::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio2::Enabled - } -} -#[doc = "Field `GPIO2` writer - GPIO2"] -pub type Gpio2W<'a, REG> = crate::BitWriter<'a, REG, Gpio2>; -impl<'a, REG> Gpio2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio2::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio2::Enabled) - } -} -#[doc = "GPIO3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio3 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO3` reader - GPIO3"] -pub type Gpio3R = crate::BitReader; -impl Gpio3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio3 { - match self.bits { - false => Gpio3::Disabled, - true => Gpio3::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio3::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio3::Enabled - } -} -#[doc = "Field `GPIO3` writer - GPIO3"] -pub type Gpio3W<'a, REG> = crate::BitWriter<'a, REG, Gpio3>; -impl<'a, REG> Gpio3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio3::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio3::Enabled) - } -} -#[doc = "GPIO4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio4 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO4` reader - GPIO4"] -pub type Gpio4R = crate::BitReader; -impl Gpio4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio4 { - match self.bits { - false => Gpio4::Disabled, - true => Gpio4::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio4::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio4::Enabled - } -} -#[doc = "Field `GPIO4` writer - GPIO4"] -pub type Gpio4W<'a, REG> = crate::BitWriter<'a, REG, Gpio4>; -impl<'a, REG> Gpio4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio4::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio4::Enabled) - } -} -#[doc = "MAU0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mau0 { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mau0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MAU0` reader - MAU0"] -pub type Mau0R = crate::BitReader; -impl Mau0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mau0 { - match self.bits { - false => Mau0::Disabled, - true => Mau0::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Mau0::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Mau0::Enabled - } -} -#[doc = "Field `MAU0` writer - MAU0"] -pub type Mau0W<'a, REG> = crate::BitWriter<'a, REG, Mau0>; -impl<'a, REG> Mau0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Mau0::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Mau0::Enabled) - } -} -#[doc = "ROMC\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Romc { - #[doc = "0: Peripheral clock is disabled"] - Disabled = 0, - #[doc = "1: Peripheral clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Romc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROMC` reader - ROMC"] -pub type RomcR = crate::BitReader; -impl RomcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Romc { - match self.bits { - false => Romc::Disabled, - true => Romc::Enabled, - } - } - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Romc::Disabled - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Romc::Enabled - } -} -#[doc = "Field `ROMC` writer - ROMC"] -pub type RomcW<'a, REG> = crate::BitWriter<'a, REG, Romc>; -impl<'a, REG> RomcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Romc::Disabled) - } - #[doc = "Peripheral clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Romc::Enabled) - } -} -impl R { - #[doc = "Bit 1 - RAMA"] - #[inline(always)] - pub fn rama(&self) -> RamaR { - RamaR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - RAMB"] - #[inline(always)] - pub fn ramb(&self) -> RambR { - RambR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - RAMC"] - #[inline(always)] - pub fn ramc(&self) -> RamcR { - RamcR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - GPIO0"] - #[inline(always)] - pub fn gpio0(&self) -> Gpio0R { - Gpio0R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - GPIO1"] - #[inline(always)] - pub fn gpio1(&self) -> Gpio1R { - Gpio1R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - GPIO2"] - #[inline(always)] - pub fn gpio2(&self) -> Gpio2R { - Gpio2R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - GPIO3"] - #[inline(always)] - pub fn gpio3(&self) -> Gpio3R { - Gpio3R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - GPIO4"] - #[inline(always)] - pub fn gpio4(&self) -> Gpio4R { - Gpio4R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - MAU0"] - #[inline(always)] - pub fn mau0(&self) -> Mau0R { - Mau0R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - ROMC"] - #[inline(always)] - pub fn romc(&self) -> RomcR { - RomcR::new(((self.bits >> 10) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - RAMA"] - #[inline(always)] - pub fn rama(&mut self) -> RamaW { - RamaW::new(self, 1) - } - #[doc = "Bit 2 - RAMB"] - #[inline(always)] - pub fn ramb(&mut self) -> RambW { - RambW::new(self, 2) - } - #[doc = "Bit 3 - RAMC"] - #[inline(always)] - pub fn ramc(&mut self) -> RamcW { - RamcW::new(self, 3) - } - #[doc = "Bit 4 - GPIO0"] - #[inline(always)] - pub fn gpio0(&mut self) -> Gpio0W { - Gpio0W::new(self, 4) - } - #[doc = "Bit 5 - GPIO1"] - #[inline(always)] - pub fn gpio1(&mut self) -> Gpio1W { - Gpio1W::new(self, 5) - } - #[doc = "Bit 6 - GPIO2"] - #[inline(always)] - pub fn gpio2(&mut self) -> Gpio2W { - Gpio2W::new(self, 6) - } - #[doc = "Bit 7 - GPIO3"] - #[inline(always)] - pub fn gpio3(&mut self) -> Gpio3W { - Gpio3W::new(self, 7) - } - #[doc = "Bit 8 - GPIO4"] - #[inline(always)] - pub fn gpio4(&mut self) -> Gpio4W { - Gpio4W::new(self, 8) - } - #[doc = "Bit 9 - MAU0"] - #[inline(always)] - pub fn mau0(&mut self) -> Mau0W { - Mau0W::new(self, 9) - } - #[doc = "Bit 10 - ROMC"] - #[inline(always)] - pub fn romc(&mut self) -> RomcW { - RomcW::new(self, 10) - } -} -#[doc = "AHB Clock Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_cc2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc2Spec; -impl crate::RegisterSpec for MrccGlbCc2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_cc2::R`](R) reader structure"] -impl crate::Readable for MrccGlbCc2Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc2::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC2 to value 0"] -impl crate::Resettable for MrccGlbCc2Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs deleted file mode 100644 index 2f8caa45c..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_clr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC2_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "AHB Clock Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc2ClrSpec; -impl crate::RegisterSpec for MrccGlbCc2ClrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc2_clr::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc2ClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC2_CLR to value 0"] -impl crate::Resettable for MrccGlbCc2ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs deleted file mode 100644 index 43b9c0e8c..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_cc2_set.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_CC2_SET` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "AHB Clock Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc2_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbCc2SetSpec; -impl crate::RegisterSpec for MrccGlbCc2SetSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc2_set::W`](W) writer structure"] -impl crate::Writable for MrccGlbCc2SetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_CC2_SET to value 0"] -impl crate::Resettable for MrccGlbCc2SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs deleted file mode 100644 index de64c78ea..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0.rs +++ /dev/null @@ -1,1911 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST0` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_RST0` writer"] -pub type W = crate::W; -#[doc = "INPUTMUX0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inputmux0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inputmux0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INPUTMUX0` reader - INPUTMUX0"] -pub type Inputmux0R = crate::BitReader; -impl Inputmux0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inputmux0 { - match self.bits { - false => Inputmux0::Disabled, - true => Inputmux0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Inputmux0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Inputmux0::Enabled - } -} -#[doc = "Field `INPUTMUX0` writer - INPUTMUX0"] -pub type Inputmux0W<'a, REG> = crate::BitWriter<'a, REG, Inputmux0>; -impl<'a, REG> Inputmux0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Inputmux0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Inputmux0::Enabled) - } -} -#[doc = "I3C0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum I3c0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: I3c0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `I3C0` reader - I3C0"] -pub type I3c0R = crate::BitReader; -impl I3c0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> I3c0 { - match self.bits { - false => I3c0::Disabled, - true => I3c0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == I3c0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == I3c0::Enabled - } -} -#[doc = "Field `I3C0` writer - I3C0"] -pub type I3c0W<'a, REG> = crate::BitWriter<'a, REG, I3c0>; -impl<'a, REG> I3c0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(I3c0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(I3c0::Enabled) - } -} -#[doc = "CTIMER0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER0` reader - CTIMER0"] -pub type Ctimer0R = crate::BitReader; -impl Ctimer0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer0 { - match self.bits { - false => Ctimer0::Disabled, - true => Ctimer0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer0::Enabled - } -} -#[doc = "Field `CTIMER0` writer - CTIMER0"] -pub type Ctimer0W<'a, REG> = crate::BitWriter<'a, REG, Ctimer0>; -impl<'a, REG> Ctimer0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer0::Enabled) - } -} -#[doc = "CTIMER1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER1` reader - CTIMER1"] -pub type Ctimer1R = crate::BitReader; -impl Ctimer1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer1 { - match self.bits { - false => Ctimer1::Disabled, - true => Ctimer1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer1::Enabled - } -} -#[doc = "Field `CTIMER1` writer - CTIMER1"] -pub type Ctimer1W<'a, REG> = crate::BitWriter<'a, REG, Ctimer1>; -impl<'a, REG> Ctimer1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer1::Enabled) - } -} -#[doc = "CTIMER2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER2` reader - CTIMER2"] -pub type Ctimer2R = crate::BitReader; -impl Ctimer2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer2 { - match self.bits { - false => Ctimer2::Disabled, - true => Ctimer2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer2::Enabled - } -} -#[doc = "Field `CTIMER2` writer - CTIMER2"] -pub type Ctimer2W<'a, REG> = crate::BitWriter<'a, REG, Ctimer2>; -impl<'a, REG> Ctimer2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer2::Enabled) - } -} -#[doc = "CTIMER3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer3 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER3` reader - CTIMER3"] -pub type Ctimer3R = crate::BitReader; -impl Ctimer3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer3 { - match self.bits { - false => Ctimer3::Disabled, - true => Ctimer3::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer3::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer3::Enabled - } -} -#[doc = "Field `CTIMER3` writer - CTIMER3"] -pub type Ctimer3W<'a, REG> = crate::BitWriter<'a, REG, Ctimer3>; -impl<'a, REG> Ctimer3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer3::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer3::Enabled) - } -} -#[doc = "CTIMER4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer4 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER4` reader - CTIMER4"] -pub type Ctimer4R = crate::BitReader; -impl Ctimer4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer4 { - match self.bits { - false => Ctimer4::Disabled, - true => Ctimer4::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ctimer4::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ctimer4::Enabled - } -} -#[doc = "Field `CTIMER4` writer - CTIMER4"] -pub type Ctimer4W<'a, REG> = crate::BitWriter<'a, REG, Ctimer4>; -impl<'a, REG> Ctimer4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ctimer4::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ctimer4::Enabled) - } -} -#[doc = "FREQME\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Freqme { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Freqme) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FREQME` reader - FREQME"] -pub type FreqmeR = crate::BitReader; -impl FreqmeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Freqme { - match self.bits { - false => Freqme::Disabled, - true => Freqme::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Freqme::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Freqme::Enabled - } -} -#[doc = "Field `FREQME` writer - FREQME"] -pub type FreqmeW<'a, REG> = crate::BitWriter<'a, REG, Freqme>; -impl<'a, REG> FreqmeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Freqme::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Freqme::Enabled) - } -} -#[doc = "UTICK0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Utick0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Utick0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UTICK0` reader - UTICK0"] -pub type Utick0R = crate::BitReader; -impl Utick0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Utick0 { - match self.bits { - false => Utick0::Disabled, - true => Utick0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Utick0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Utick0::Enabled - } -} -#[doc = "Field `UTICK0` writer - UTICK0"] -pub type Utick0W<'a, REG> = crate::BitWriter<'a, REG, Utick0>; -impl<'a, REG> Utick0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Utick0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Utick0::Enabled) - } -} -#[doc = "SMARTDMA0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Smartdma0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Smartdma0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SMARTDMA0` reader - SMARTDMA0"] -pub type Smartdma0R = crate::BitReader; -impl Smartdma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Smartdma0 { - match self.bits { - false => Smartdma0::Disabled, - true => Smartdma0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Smartdma0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Smartdma0::Enabled - } -} -#[doc = "Field `SMARTDMA0` writer - SMARTDMA0"] -pub type Smartdma0W<'a, REG> = crate::BitWriter<'a, REG, Smartdma0>; -impl<'a, REG> Smartdma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Smartdma0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Smartdma0::Enabled) - } -} -#[doc = "DMA0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dma0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dma0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMA0` reader - DMA0"] -pub type Dma0R = crate::BitReader; -impl Dma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dma0 { - match self.bits { - false => Dma0::Disabled, - true => Dma0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dma0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dma0::Enabled - } -} -#[doc = "Field `DMA0` writer - DMA0"] -pub type Dma0W<'a, REG> = crate::BitWriter<'a, REG, Dma0>; -impl<'a, REG> Dma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dma0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dma0::Enabled) - } -} -#[doc = "AOI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aoi0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aoi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AOI0` reader - AOI0"] -pub type Aoi0R = crate::BitReader; -impl Aoi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aoi0 { - match self.bits { - false => Aoi0::Disabled, - true => Aoi0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Aoi0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Aoi0::Enabled - } -} -#[doc = "Field `AOI0` writer - AOI0"] -pub type Aoi0W<'a, REG> = crate::BitWriter<'a, REG, Aoi0>; -impl<'a, REG> Aoi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Aoi0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Aoi0::Enabled) - } -} -#[doc = "CRC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crc0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRC0` reader - CRC0"] -pub type Crc0R = crate::BitReader; -impl Crc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crc0 { - match self.bits { - false => Crc0::Disabled, - true => Crc0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Crc0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Crc0::Enabled - } -} -#[doc = "Field `CRC0` writer - CRC0"] -pub type Crc0W<'a, REG> = crate::BitWriter<'a, REG, Crc0>; -impl<'a, REG> Crc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Crc0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Crc0::Enabled) - } -} -#[doc = "EIM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Eim0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Eim0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EIM0` reader - EIM0"] -pub type Eim0R = crate::BitReader; -impl Eim0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Eim0 { - match self.bits { - false => Eim0::Disabled, - true => Eim0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Eim0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Eim0::Enabled - } -} -#[doc = "Field `EIM0` writer - EIM0"] -pub type Eim0W<'a, REG> = crate::BitWriter<'a, REG, Eim0>; -impl<'a, REG> Eim0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Eim0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Eim0::Enabled) - } -} -#[doc = "ERM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erm0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erm0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERM0` reader - ERM0"] -pub type Erm0R = crate::BitReader; -impl Erm0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erm0 { - match self.bits { - false => Erm0::Disabled, - true => Erm0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Erm0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Erm0::Enabled - } -} -#[doc = "Field `ERM0` writer - ERM0"] -pub type Erm0W<'a, REG> = crate::BitWriter<'a, REG, Erm0>; -impl<'a, REG> Erm0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Erm0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Erm0::Enabled) - } -} -#[doc = "AOI1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Aoi1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Aoi1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AOI1` reader - AOI1"] -pub type Aoi1R = crate::BitReader; -impl Aoi1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Aoi1 { - match self.bits { - false => Aoi1::Disabled, - true => Aoi1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Aoi1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Aoi1::Enabled - } -} -#[doc = "Field `AOI1` writer - AOI1"] -pub type Aoi1W<'a, REG> = crate::BitWriter<'a, REG, Aoi1>; -impl<'a, REG> Aoi1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Aoi1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Aoi1::Enabled) - } -} -#[doc = "FLEXIO0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexio0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexio0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXIO0` reader - FLEXIO0"] -pub type Flexio0R = crate::BitReader; -impl Flexio0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexio0 { - match self.bits { - false => Flexio0::Disabled, - true => Flexio0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexio0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexio0::Enabled - } -} -#[doc = "Field `FLEXIO0` writer - FLEXIO0"] -pub type Flexio0W<'a, REG> = crate::BitWriter<'a, REG, Flexio0>; -impl<'a, REG> Flexio0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexio0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexio0::Enabled) - } -} -#[doc = "LPI2C0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C0` reader - LPI2C0"] -pub type Lpi2c0R = crate::BitReader; -impl Lpi2c0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c0 { - match self.bits { - false => Lpi2c0::Disabled, - true => Lpi2c0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c0::Enabled - } -} -#[doc = "Field `LPI2C0` writer - LPI2C0"] -pub type Lpi2c0W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c0>; -impl<'a, REG> Lpi2c0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c0::Enabled) - } -} -#[doc = "LPI2C1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C1` reader - LPI2C1"] -pub type Lpi2c1R = crate::BitReader; -impl Lpi2c1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c1 { - match self.bits { - false => Lpi2c1::Disabled, - true => Lpi2c1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c1::Enabled - } -} -#[doc = "Field `LPI2C1` writer - LPI2C1"] -pub type Lpi2c1W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c1>; -impl<'a, REG> Lpi2c1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c1::Enabled) - } -} -#[doc = "LPSPI0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpspi0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpspi0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPSPI0` reader - LPSPI0"] -pub type Lpspi0R = crate::BitReader; -impl Lpspi0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpspi0 { - match self.bits { - false => Lpspi0::Disabled, - true => Lpspi0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpspi0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpspi0::Enabled - } -} -#[doc = "Field `LPSPI0` writer - LPSPI0"] -pub type Lpspi0W<'a, REG> = crate::BitWriter<'a, REG, Lpspi0>; -impl<'a, REG> Lpspi0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpspi0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpspi0::Enabled) - } -} -#[doc = "LPSPI1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpspi1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpspi1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPSPI1` reader - LPSPI1"] -pub type Lpspi1R = crate::BitReader; -impl Lpspi1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpspi1 { - match self.bits { - false => Lpspi1::Disabled, - true => Lpspi1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpspi1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpspi1::Enabled - } -} -#[doc = "Field `LPSPI1` writer - LPSPI1"] -pub type Lpspi1W<'a, REG> = crate::BitWriter<'a, REG, Lpspi1>; -impl<'a, REG> Lpspi1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpspi1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpspi1::Enabled) - } -} -#[doc = "LPUART0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART0` reader - LPUART0"] -pub type Lpuart0R = crate::BitReader; -impl Lpuart0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart0 { - match self.bits { - false => Lpuart0::Disabled, - true => Lpuart0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart0::Enabled - } -} -#[doc = "Field `LPUART0` writer - LPUART0"] -pub type Lpuart0W<'a, REG> = crate::BitWriter<'a, REG, Lpuart0>; -impl<'a, REG> Lpuart0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart0::Enabled) - } -} -#[doc = "LPUART1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART1` reader - LPUART1"] -pub type Lpuart1R = crate::BitReader; -impl Lpuart1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart1 { - match self.bits { - false => Lpuart1::Disabled, - true => Lpuart1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart1::Enabled - } -} -#[doc = "Field `LPUART1` writer - LPUART1"] -pub type Lpuart1W<'a, REG> = crate::BitWriter<'a, REG, Lpuart1>; -impl<'a, REG> Lpuart1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart1::Enabled) - } -} -#[doc = "LPUART2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART2` reader - LPUART2"] -pub type Lpuart2R = crate::BitReader; -impl Lpuart2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart2 { - match self.bits { - false => Lpuart2::Disabled, - true => Lpuart2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart2::Enabled - } -} -#[doc = "Field `LPUART2` writer - LPUART2"] -pub type Lpuart2W<'a, REG> = crate::BitWriter<'a, REG, Lpuart2>; -impl<'a, REG> Lpuart2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart2::Enabled) - } -} -#[doc = "LPUART3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart3 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART3` reader - LPUART3"] -pub type Lpuart3R = crate::BitReader; -impl Lpuart3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart3 { - match self.bits { - false => Lpuart3::Disabled, - true => Lpuart3::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart3::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart3::Enabled - } -} -#[doc = "Field `LPUART3` writer - LPUART3"] -pub type Lpuart3W<'a, REG> = crate::BitWriter<'a, REG, Lpuart3>; -impl<'a, REG> Lpuart3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart3::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart3::Enabled) - } -} -#[doc = "LPUART4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart4 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART4` reader - LPUART4"] -pub type Lpuart4R = crate::BitReader; -impl Lpuart4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart4 { - match self.bits { - false => Lpuart4::Disabled, - true => Lpuart4::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart4::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart4::Enabled - } -} -#[doc = "Field `LPUART4` writer - LPUART4"] -pub type Lpuart4W<'a, REG> = crate::BitWriter<'a, REG, Lpuart4>; -impl<'a, REG> Lpuart4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart4::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart4::Enabled) - } -} -#[doc = "USB0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usb0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usb0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USB0` reader - USB0"] -pub type Usb0R = crate::BitReader; -impl Usb0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Usb0 { - match self.bits { - false => Usb0::Disabled, - true => Usb0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Usb0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Usb0::Enabled - } -} -#[doc = "Field `USB0` writer - USB0"] -pub type Usb0W<'a, REG> = crate::BitWriter<'a, REG, Usb0>; -impl<'a, REG> Usb0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Usb0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Usb0::Enabled) - } -} -#[doc = "QDC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Qdc0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Qdc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `QDC0` reader - QDC0"] -pub type Qdc0R = crate::BitReader; -impl Qdc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Qdc0 { - match self.bits { - false => Qdc0::Disabled, - true => Qdc0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Qdc0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Qdc0::Enabled - } -} -#[doc = "Field `QDC0` writer - QDC0"] -pub type Qdc0W<'a, REG> = crate::BitWriter<'a, REG, Qdc0>; -impl<'a, REG> Qdc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Qdc0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Qdc0::Enabled) - } -} -#[doc = "QDC1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Qdc1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Qdc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `QDC1` reader - QDC1"] -pub type Qdc1R = crate::BitReader; -impl Qdc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Qdc1 { - match self.bits { - false => Qdc1::Disabled, - true => Qdc1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Qdc1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Qdc1::Enabled - } -} -#[doc = "Field `QDC1` writer - QDC1"] -pub type Qdc1W<'a, REG> = crate::BitWriter<'a, REG, Qdc1>; -impl<'a, REG> Qdc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Qdc1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Qdc1::Enabled) - } -} -#[doc = "FLEXPWM0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexpwm0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexpwm0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXPWM0` reader - FLEXPWM0"] -pub type Flexpwm0R = crate::BitReader; -impl Flexpwm0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexpwm0 { - match self.bits { - false => Flexpwm0::Disabled, - true => Flexpwm0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexpwm0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexpwm0::Enabled - } -} -#[doc = "Field `FLEXPWM0` writer - FLEXPWM0"] -pub type Flexpwm0W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm0>; -impl<'a, REG> Flexpwm0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexpwm0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexpwm0::Enabled) - } -} -impl R { - #[doc = "Bit 0 - INPUTMUX0"] - #[inline(always)] - pub fn inputmux0(&self) -> Inputmux0R { - Inputmux0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - I3C0"] - #[inline(always)] - pub fn i3c0(&self) -> I3c0R { - I3c0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - CTIMER0"] - #[inline(always)] - pub fn ctimer0(&self) -> Ctimer0R { - Ctimer0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - CTIMER1"] - #[inline(always)] - pub fn ctimer1(&self) -> Ctimer1R { - Ctimer1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - CTIMER2"] - #[inline(always)] - pub fn ctimer2(&self) -> Ctimer2R { - Ctimer2R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - CTIMER3"] - #[inline(always)] - pub fn ctimer3(&self) -> Ctimer3R { - Ctimer3R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - CTIMER4"] - #[inline(always)] - pub fn ctimer4(&self) -> Ctimer4R { - Ctimer4R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - FREQME"] - #[inline(always)] - pub fn freqme(&self) -> FreqmeR { - FreqmeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - UTICK0"] - #[inline(always)] - pub fn utick0(&self) -> Utick0R { - Utick0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 10 - SMARTDMA0"] - #[inline(always)] - pub fn smartdma0(&self) -> Smartdma0R { - Smartdma0R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - DMA0"] - #[inline(always)] - pub fn dma0(&self) -> Dma0R { - Dma0R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - AOI0"] - #[inline(always)] - pub fn aoi0(&self) -> Aoi0R { - Aoi0R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - CRC0"] - #[inline(always)] - pub fn crc0(&self) -> Crc0R { - Crc0R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - EIM0"] - #[inline(always)] - pub fn eim0(&self) -> Eim0R { - Eim0R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - ERM0"] - #[inline(always)] - pub fn erm0(&self) -> Erm0R { - Erm0R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 17 - AOI1"] - #[inline(always)] - pub fn aoi1(&self) -> Aoi1R { - Aoi1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - FLEXIO0"] - #[inline(always)] - pub fn flexio0(&self) -> Flexio0R { - Flexio0R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - LPI2C0"] - #[inline(always)] - pub fn lpi2c0(&self) -> Lpi2c0R { - Lpi2c0R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LPI2C1"] - #[inline(always)] - pub fn lpi2c1(&self) -> Lpi2c1R { - Lpi2c1R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LPSPI0"] - #[inline(always)] - pub fn lpspi0(&self) -> Lpspi0R { - Lpspi0R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LPSPI1"] - #[inline(always)] - pub fn lpspi1(&self) -> Lpspi1R { - Lpspi1R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - LPUART0"] - #[inline(always)] - pub fn lpuart0(&self) -> Lpuart0R { - Lpuart0R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - LPUART1"] - #[inline(always)] - pub fn lpuart1(&self) -> Lpuart1R { - Lpuart1R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - LPUART2"] - #[inline(always)] - pub fn lpuart2(&self) -> Lpuart2R { - Lpuart2R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - LPUART3"] - #[inline(always)] - pub fn lpuart3(&self) -> Lpuart3R { - Lpuart3R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - LPUART4"] - #[inline(always)] - pub fn lpuart4(&self) -> Lpuart4R { - Lpuart4R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - USB0"] - #[inline(always)] - pub fn usb0(&self) -> Usb0R { - Usb0R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - QDC0"] - #[inline(always)] - pub fn qdc0(&self) -> Qdc0R { - Qdc0R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - QDC1"] - #[inline(always)] - pub fn qdc1(&self) -> Qdc1R { - Qdc1R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - FLEXPWM0"] - #[inline(always)] - pub fn flexpwm0(&self) -> Flexpwm0R { - Flexpwm0R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - INPUTMUX0"] - #[inline(always)] - pub fn inputmux0(&mut self) -> Inputmux0W { - Inputmux0W::new(self, 0) - } - #[doc = "Bit 1 - I3C0"] - #[inline(always)] - pub fn i3c0(&mut self) -> I3c0W { - I3c0W::new(self, 1) - } - #[doc = "Bit 2 - CTIMER0"] - #[inline(always)] - pub fn ctimer0(&mut self) -> Ctimer0W { - Ctimer0W::new(self, 2) - } - #[doc = "Bit 3 - CTIMER1"] - #[inline(always)] - pub fn ctimer1(&mut self) -> Ctimer1W { - Ctimer1W::new(self, 3) - } - #[doc = "Bit 4 - CTIMER2"] - #[inline(always)] - pub fn ctimer2(&mut self) -> Ctimer2W { - Ctimer2W::new(self, 4) - } - #[doc = "Bit 5 - CTIMER3"] - #[inline(always)] - pub fn ctimer3(&mut self) -> Ctimer3W { - Ctimer3W::new(self, 5) - } - #[doc = "Bit 6 - CTIMER4"] - #[inline(always)] - pub fn ctimer4(&mut self) -> Ctimer4W { - Ctimer4W::new(self, 6) - } - #[doc = "Bit 7 - FREQME"] - #[inline(always)] - pub fn freqme(&mut self) -> FreqmeW { - FreqmeW::new(self, 7) - } - #[doc = "Bit 8 - UTICK0"] - #[inline(always)] - pub fn utick0(&mut self) -> Utick0W { - Utick0W::new(self, 8) - } - #[doc = "Bit 10 - SMARTDMA0"] - #[inline(always)] - pub fn smartdma0(&mut self) -> Smartdma0W { - Smartdma0W::new(self, 10) - } - #[doc = "Bit 11 - DMA0"] - #[inline(always)] - pub fn dma0(&mut self) -> Dma0W { - Dma0W::new(self, 11) - } - #[doc = "Bit 12 - AOI0"] - #[inline(always)] - pub fn aoi0(&mut self) -> Aoi0W { - Aoi0W::new(self, 12) - } - #[doc = "Bit 13 - CRC0"] - #[inline(always)] - pub fn crc0(&mut self) -> Crc0W { - Crc0W::new(self, 13) - } - #[doc = "Bit 14 - EIM0"] - #[inline(always)] - pub fn eim0(&mut self) -> Eim0W { - Eim0W::new(self, 14) - } - #[doc = "Bit 15 - ERM0"] - #[inline(always)] - pub fn erm0(&mut self) -> Erm0W { - Erm0W::new(self, 15) - } - #[doc = "Bit 17 - AOI1"] - #[inline(always)] - pub fn aoi1(&mut self) -> Aoi1W { - Aoi1W::new(self, 17) - } - #[doc = "Bit 18 - FLEXIO0"] - #[inline(always)] - pub fn flexio0(&mut self) -> Flexio0W { - Flexio0W::new(self, 18) - } - #[doc = "Bit 19 - LPI2C0"] - #[inline(always)] - pub fn lpi2c0(&mut self) -> Lpi2c0W { - Lpi2c0W::new(self, 19) - } - #[doc = "Bit 20 - LPI2C1"] - #[inline(always)] - pub fn lpi2c1(&mut self) -> Lpi2c1W { - Lpi2c1W::new(self, 20) - } - #[doc = "Bit 21 - LPSPI0"] - #[inline(always)] - pub fn lpspi0(&mut self) -> Lpspi0W { - Lpspi0W::new(self, 21) - } - #[doc = "Bit 22 - LPSPI1"] - #[inline(always)] - pub fn lpspi1(&mut self) -> Lpspi1W { - Lpspi1W::new(self, 22) - } - #[doc = "Bit 23 - LPUART0"] - #[inline(always)] - pub fn lpuart0(&mut self) -> Lpuart0W { - Lpuart0W::new(self, 23) - } - #[doc = "Bit 24 - LPUART1"] - #[inline(always)] - pub fn lpuart1(&mut self) -> Lpuart1W { - Lpuart1W::new(self, 24) - } - #[doc = "Bit 25 - LPUART2"] - #[inline(always)] - pub fn lpuart2(&mut self) -> Lpuart2W { - Lpuart2W::new(self, 25) - } - #[doc = "Bit 26 - LPUART3"] - #[inline(always)] - pub fn lpuart3(&mut self) -> Lpuart3W { - Lpuart3W::new(self, 26) - } - #[doc = "Bit 27 - LPUART4"] - #[inline(always)] - pub fn lpuart4(&mut self) -> Lpuart4W { - Lpuart4W::new(self, 27) - } - #[doc = "Bit 28 - USB0"] - #[inline(always)] - pub fn usb0(&mut self) -> Usb0W { - Usb0W::new(self, 28) - } - #[doc = "Bit 29 - QDC0"] - #[inline(always)] - pub fn qdc0(&mut self) -> Qdc0W { - Qdc0W::new(self, 29) - } - #[doc = "Bit 30 - QDC1"] - #[inline(always)] - pub fn qdc1(&mut self) -> Qdc1W { - Qdc1W::new(self, 30) - } - #[doc = "Bit 31 - FLEXPWM0"] - #[inline(always)] - pub fn flexpwm0(&mut self) -> Flexpwm0W { - Flexpwm0W::new(self, 31) - } -} -#[doc = "Peripheral Reset Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst0Spec; -impl crate::RegisterSpec for MrccGlbRst0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_rst0::R`](R) reader structure"] -impl crate::Readable for MrccGlbRst0Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst0::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST0 to value 0"] -impl crate::Resettable for MrccGlbRst0Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs deleted file mode 100644 index 26319587a..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_clr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST0_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Peripheral Reset Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst0ClrSpec; -impl crate::RegisterSpec for MrccGlbRst0ClrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst0_clr::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst0ClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST0_CLR to value 0"] -impl crate::Resettable for MrccGlbRst0ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs deleted file mode 100644 index 8e23f0ae0..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst0_set.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST0_SET` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Peripheral Reset Control Set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst0_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst0SetSpec; -impl crate::RegisterSpec for MrccGlbRst0SetSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst0_set::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst0SetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST0_SET to value 0"] -impl crate::Resettable for MrccGlbRst0SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs deleted file mode 100644 index 9004e3f0a..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1.rs +++ /dev/null @@ -1,1659 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST1` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_RST1` writer"] -pub type W = crate::W; -#[doc = "FLEXPWM1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexpwm1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexpwm1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXPWM1` reader - FLEXPWM1"] -pub type Flexpwm1R = crate::BitReader; -impl Flexpwm1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexpwm1 { - match self.bits { - false => Flexpwm1::Disabled, - true => Flexpwm1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexpwm1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexpwm1::Enabled - } -} -#[doc = "Field `FLEXPWM1` writer - FLEXPWM1"] -pub type Flexpwm1W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm1>; -impl<'a, REG> Flexpwm1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexpwm1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexpwm1::Enabled) - } -} -#[doc = "OSTIMER0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ostimer0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ostimer0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSTIMER0` reader - OSTIMER0"] -pub type Ostimer0R = crate::BitReader; -impl Ostimer0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ostimer0 { - match self.bits { - false => Ostimer0::Disabled, - true => Ostimer0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ostimer0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ostimer0::Enabled - } -} -#[doc = "Field `OSTIMER0` writer - OSTIMER0"] -pub type Ostimer0W<'a, REG> = crate::BitWriter<'a, REG, Ostimer0>; -impl<'a, REG> Ostimer0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ostimer0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ostimer0::Enabled) - } -} -#[doc = "ADC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC0` reader - ADC0"] -pub type Adc0R = crate::BitReader; -impl Adc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc0 { - match self.bits { - false => Adc0::Disabled, - true => Adc0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc0::Enabled - } -} -#[doc = "Field `ADC0` writer - ADC0"] -pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG, Adc0>; -impl<'a, REG> Adc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc0::Enabled) - } -} -#[doc = "ADC1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC1` reader - ADC1"] -pub type Adc1R = crate::BitReader; -impl Adc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc1 { - match self.bits { - false => Adc1::Disabled, - true => Adc1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc1::Enabled - } -} -#[doc = "Field `ADC1` writer - ADC1"] -pub type Adc1W<'a, REG> = crate::BitWriter<'a, REG, Adc1>; -impl<'a, REG> Adc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc1::Enabled) - } -} -#[doc = "CMP1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP1` reader - CMP1"] -pub type Cmp1R = crate::BitReader; -impl Cmp1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp1 { - match self.bits { - false => Cmp1::Disabled, - true => Cmp1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp1::Enabled - } -} -#[doc = "Field `CMP1` writer - CMP1"] -pub type Cmp1W<'a, REG> = crate::BitWriter<'a, REG, Cmp1>; -impl<'a, REG> Cmp1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp1::Enabled) - } -} -#[doc = "CMP2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cmp2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cmp2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CMP2` reader - CMP2"] -pub type Cmp2R = crate::BitReader; -impl Cmp2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cmp2 { - match self.bits { - false => Cmp2::Disabled, - true => Cmp2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Cmp2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Cmp2::Enabled - } -} -#[doc = "Field `CMP2` writer - CMP2"] -pub type Cmp2W<'a, REG> = crate::BitWriter<'a, REG, Cmp2>; -impl<'a, REG> Cmp2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Cmp2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Cmp2::Enabled) - } -} -#[doc = "DAC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dac0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dac0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DAC0` reader - DAC0"] -pub type Dac0R = crate::BitReader; -impl Dac0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dac0 { - match self.bits { - false => Dac0::Disabled, - true => Dac0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dac0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dac0::Enabled - } -} -#[doc = "Field `DAC0` writer - DAC0"] -pub type Dac0W<'a, REG> = crate::BitWriter<'a, REG, Dac0>; -impl<'a, REG> Dac0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dac0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dac0::Enabled) - } -} -#[doc = "OPAMP0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP0` reader - OPAMP0"] -pub type Opamp0R = crate::BitReader; -impl Opamp0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp0 { - match self.bits { - false => Opamp0::Disabled, - true => Opamp0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp0::Enabled - } -} -#[doc = "Field `OPAMP0` writer - OPAMP0"] -pub type Opamp0W<'a, REG> = crate::BitWriter<'a, REG, Opamp0>; -impl<'a, REG> Opamp0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp0::Enabled) - } -} -#[doc = "OPAMP1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP1` reader - OPAMP1"] -pub type Opamp1R = crate::BitReader; -impl Opamp1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp1 { - match self.bits { - false => Opamp1::Disabled, - true => Opamp1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp1::Enabled - } -} -#[doc = "Field `OPAMP1` writer - OPAMP1"] -pub type Opamp1W<'a, REG> = crate::BitWriter<'a, REG, Opamp1>; -impl<'a, REG> Opamp1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp1::Enabled) - } -} -#[doc = "OPAMP2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP2` reader - OPAMP2"] -pub type Opamp2R = crate::BitReader; -impl Opamp2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp2 { - match self.bits { - false => Opamp2::Disabled, - true => Opamp2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp2::Enabled - } -} -#[doc = "Field `OPAMP2` writer - OPAMP2"] -pub type Opamp2W<'a, REG> = crate::BitWriter<'a, REG, Opamp2>; -impl<'a, REG> Opamp2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp2::Enabled) - } -} -#[doc = "OPAMP3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Opamp3 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Opamp3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPAMP3` reader - OPAMP3"] -pub type Opamp3R = crate::BitReader; -impl Opamp3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Opamp3 { - match self.bits { - false => Opamp3::Disabled, - true => Opamp3::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Opamp3::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Opamp3::Enabled - } -} -#[doc = "Field `OPAMP3` writer - OPAMP3"] -pub type Opamp3W<'a, REG> = crate::BitWriter<'a, REG, Opamp3>; -impl<'a, REG> Opamp3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Opamp3::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Opamp3::Enabled) - } -} -#[doc = "PORT0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT0` reader - PORT0"] -pub type Port0R = crate::BitReader; -impl Port0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port0 { - match self.bits { - false => Port0::Disabled, - true => Port0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port0::Enabled - } -} -#[doc = "Field `PORT0` writer - PORT0"] -pub type Port0W<'a, REG> = crate::BitWriter<'a, REG, Port0>; -impl<'a, REG> Port0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port0::Enabled) - } -} -#[doc = "PORT1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT1` reader - PORT1"] -pub type Port1R = crate::BitReader; -impl Port1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port1 { - match self.bits { - false => Port1::Disabled, - true => Port1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port1::Enabled - } -} -#[doc = "Field `PORT1` writer - PORT1"] -pub type Port1W<'a, REG> = crate::BitWriter<'a, REG, Port1>; -impl<'a, REG> Port1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port1::Enabled) - } -} -#[doc = "PORT2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT2` reader - PORT2"] -pub type Port2R = crate::BitReader; -impl Port2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port2 { - match self.bits { - false => Port2::Disabled, - true => Port2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port2::Enabled - } -} -#[doc = "Field `PORT2` writer - PORT2"] -pub type Port2W<'a, REG> = crate::BitWriter<'a, REG, Port2>; -impl<'a, REG> Port2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port2::Enabled) - } -} -#[doc = "PORT3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port3 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT3` reader - PORT3"] -pub type Port3R = crate::BitReader; -impl Port3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port3 { - match self.bits { - false => Port3::Disabled, - true => Port3::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port3::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port3::Enabled - } -} -#[doc = "Field `PORT3` writer - PORT3"] -pub type Port3W<'a, REG> = crate::BitWriter<'a, REG, Port3>; -impl<'a, REG> Port3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port3::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port3::Enabled) - } -} -#[doc = "PORT4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Port4 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Port4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PORT4` reader - PORT4"] -pub type Port4R = crate::BitReader; -impl Port4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Port4 { - match self.bits { - false => Port4::Disabled, - true => Port4::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Port4::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Port4::Enabled - } -} -#[doc = "Field `PORT4` writer - PORT4"] -pub type Port4W<'a, REG> = crate::BitWriter<'a, REG, Port4>; -impl<'a, REG> Port4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Port4::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Port4::Enabled) - } -} -#[doc = "SLCD0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Slcd0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Slcd0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLCD0` reader - SLCD0"] -pub type Slcd0R = crate::BitReader; -impl Slcd0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Slcd0 { - match self.bits { - false => Slcd0::Disabled, - true => Slcd0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Slcd0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Slcd0::Enabled - } -} -#[doc = "Field `SLCD0` writer - SLCD0"] -pub type Slcd0W<'a, REG> = crate::BitWriter<'a, REG, Slcd0>; -impl<'a, REG> Slcd0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Slcd0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Slcd0::Enabled) - } -} -#[doc = "FLEXCAN0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexcan0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexcan0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXCAN0` reader - FLEXCAN0"] -pub type Flexcan0R = crate::BitReader; -impl Flexcan0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexcan0 { - match self.bits { - false => Flexcan0::Disabled, - true => Flexcan0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexcan0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexcan0::Enabled - } -} -#[doc = "Field `FLEXCAN0` writer - FLEXCAN0"] -pub type Flexcan0W<'a, REG> = crate::BitWriter<'a, REG, Flexcan0>; -impl<'a, REG> Flexcan0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexcan0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexcan0::Enabled) - } -} -#[doc = "FLEXCAN1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Flexcan1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Flexcan1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLEXCAN1` reader - FLEXCAN1"] -pub type Flexcan1R = crate::BitReader; -impl Flexcan1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Flexcan1 { - match self.bits { - false => Flexcan1::Disabled, - true => Flexcan1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Flexcan1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Flexcan1::Enabled - } -} -#[doc = "Field `FLEXCAN1` writer - FLEXCAN1"] -pub type Flexcan1W<'a, REG> = crate::BitWriter<'a, REG, Flexcan1>; -impl<'a, REG> Flexcan1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Flexcan1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Flexcan1::Enabled) - } -} -#[doc = "LPI2C2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C2` reader - LPI2C2"] -pub type Lpi2c2R = crate::BitReader; -impl Lpi2c2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c2 { - match self.bits { - false => Lpi2c2::Disabled, - true => Lpi2c2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c2::Enabled - } -} -#[doc = "Field `LPI2C2` writer - LPI2C2"] -pub type Lpi2c2W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c2>; -impl<'a, REG> Lpi2c2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c2::Enabled) - } -} -#[doc = "LPI2C3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpi2c3 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpi2c3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPI2C3` reader - LPI2C3"] -pub type Lpi2c3R = crate::BitReader; -impl Lpi2c3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpi2c3 { - match self.bits { - false => Lpi2c3::Disabled, - true => Lpi2c3::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpi2c3::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpi2c3::Enabled - } -} -#[doc = "Field `LPI2C3` writer - LPI2C3"] -pub type Lpi2c3W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c3>; -impl<'a, REG> Lpi2c3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpi2c3::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpi2c3::Enabled) - } -} -#[doc = "LPUART5\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpuart5 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpuart5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPUART5` reader - LPUART5"] -pub type Lpuart5R = crate::BitReader; -impl Lpuart5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpuart5 { - match self.bits { - false => Lpuart5::Disabled, - true => Lpuart5::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Lpuart5::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Lpuart5::Enabled - } -} -#[doc = "Field `LPUART5` writer - LPUART5"] -pub type Lpuart5W<'a, REG> = crate::BitWriter<'a, REG, Lpuart5>; -impl<'a, REG> Lpuart5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Lpuart5::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Lpuart5::Enabled) - } -} -#[doc = "PKC0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pkc0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pkc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PKC0` reader - PKC0"] -pub type Pkc0R = crate::BitReader; -impl Pkc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pkc0 { - match self.bits { - false => Pkc0::Disabled, - true => Pkc0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pkc0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pkc0::Enabled - } -} -#[doc = "Field `PKC0` writer - PKC0"] -pub type Pkc0W<'a, REG> = crate::BitWriter<'a, REG, Pkc0>; -impl<'a, REG> Pkc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Pkc0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Pkc0::Enabled) - } -} -#[doc = "TRNG0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Trng0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Trng0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRNG0` reader - TRNG0"] -pub type Trng0R = crate::BitReader; -impl Trng0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trng0 { - match self.bits { - false => Trng0::Disabled, - true => Trng0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Trng0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Trng0::Enabled - } -} -#[doc = "Field `TRNG0` writer - TRNG0"] -pub type Trng0W<'a, REG> = crate::BitWriter<'a, REG, Trng0>; -impl<'a, REG> Trng0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Trng0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Trng0::Enabled) - } -} -#[doc = "ADC2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC2` reader - ADC2"] -pub type Adc2R = crate::BitReader; -impl Adc2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc2 { - match self.bits { - false => Adc2::Disabled, - true => Adc2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc2::Enabled - } -} -#[doc = "Field `ADC2` writer - ADC2"] -pub type Adc2W<'a, REG> = crate::BitWriter<'a, REG, Adc2>; -impl<'a, REG> Adc2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc2::Enabled) - } -} -#[doc = "ADC3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Adc3 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Adc3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ADC3` reader - ADC3"] -pub type Adc3R = crate::BitReader; -impl Adc3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Adc3 { - match self.bits { - false => Adc3::Disabled, - true => Adc3::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Adc3::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Adc3::Enabled - } -} -#[doc = "Field `ADC3` writer - ADC3"] -pub type Adc3W<'a, REG> = crate::BitWriter<'a, REG, Adc3>; -impl<'a, REG> Adc3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Adc3::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Adc3::Enabled) - } -} -impl R { - #[doc = "Bit 0 - FLEXPWM1"] - #[inline(always)] - pub fn flexpwm1(&self) -> Flexpwm1R { - Flexpwm1R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - OSTIMER0"] - #[inline(always)] - pub fn ostimer0(&self) -> Ostimer0R { - Ostimer0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - ADC0"] - #[inline(always)] - pub fn adc0(&self) -> Adc0R { - Adc0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - ADC1"] - #[inline(always)] - pub fn adc1(&self) -> Adc1R { - Adc1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - CMP1"] - #[inline(always)] - pub fn cmp1(&self) -> Cmp1R { - Cmp1R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - CMP2"] - #[inline(always)] - pub fn cmp2(&self) -> Cmp2R { - Cmp2R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - DAC0"] - #[inline(always)] - pub fn dac0(&self) -> Dac0R { - Dac0R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - OPAMP0"] - #[inline(always)] - pub fn opamp0(&self) -> Opamp0R { - Opamp0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - OPAMP1"] - #[inline(always)] - pub fn opamp1(&self) -> Opamp1R { - Opamp1R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - OPAMP2"] - #[inline(always)] - pub fn opamp2(&self) -> Opamp2R { - Opamp2R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - OPAMP3"] - #[inline(always)] - pub fn opamp3(&self) -> Opamp3R { - Opamp3R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - PORT0"] - #[inline(always)] - pub fn port0(&self) -> Port0R { - Port0R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - PORT1"] - #[inline(always)] - pub fn port1(&self) -> Port1R { - Port1R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - PORT2"] - #[inline(always)] - pub fn port2(&self) -> Port2R { - Port2R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - PORT3"] - #[inline(always)] - pub fn port3(&self) -> Port3R { - Port3R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - PORT4"] - #[inline(always)] - pub fn port4(&self) -> Port4R { - Port4R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - SLCD0"] - #[inline(always)] - pub fn slcd0(&self) -> Slcd0R { - Slcd0R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - FLEXCAN0"] - #[inline(always)] - pub fn flexcan0(&self) -> Flexcan0R { - Flexcan0R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - FLEXCAN1"] - #[inline(always)] - pub fn flexcan1(&self) -> Flexcan1R { - Flexcan1R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LPI2C2"] - #[inline(always)] - pub fn lpi2c2(&self) -> Lpi2c2R { - Lpi2c2R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LPI2C3"] - #[inline(always)] - pub fn lpi2c3(&self) -> Lpi2c3R { - Lpi2c3R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LPUART5"] - #[inline(always)] - pub fn lpuart5(&self) -> Lpuart5R { - Lpuart5R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 24 - PKC0"] - #[inline(always)] - pub fn pkc0(&self) -> Pkc0R { - Pkc0R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 26 - TRNG0"] - #[inline(always)] - pub fn trng0(&self) -> Trng0R { - Trng0R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 28 - ADC2"] - #[inline(always)] - pub fn adc2(&self) -> Adc2R { - Adc2R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - ADC3"] - #[inline(always)] - pub fn adc3(&self) -> Adc3R { - Adc3R::new(((self.bits >> 29) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FLEXPWM1"] - #[inline(always)] - pub fn flexpwm1(&mut self) -> Flexpwm1W { - Flexpwm1W::new(self, 0) - } - #[doc = "Bit 1 - OSTIMER0"] - #[inline(always)] - pub fn ostimer0(&mut self) -> Ostimer0W { - Ostimer0W::new(self, 1) - } - #[doc = "Bit 2 - ADC0"] - #[inline(always)] - pub fn adc0(&mut self) -> Adc0W { - Adc0W::new(self, 2) - } - #[doc = "Bit 3 - ADC1"] - #[inline(always)] - pub fn adc1(&mut self) -> Adc1W { - Adc1W::new(self, 3) - } - #[doc = "Bit 5 - CMP1"] - #[inline(always)] - pub fn cmp1(&mut self) -> Cmp1W { - Cmp1W::new(self, 5) - } - #[doc = "Bit 6 - CMP2"] - #[inline(always)] - pub fn cmp2(&mut self) -> Cmp2W { - Cmp2W::new(self, 6) - } - #[doc = "Bit 7 - DAC0"] - #[inline(always)] - pub fn dac0(&mut self) -> Dac0W { - Dac0W::new(self, 7) - } - #[doc = "Bit 8 - OPAMP0"] - #[inline(always)] - pub fn opamp0(&mut self) -> Opamp0W { - Opamp0W::new(self, 8) - } - #[doc = "Bit 9 - OPAMP1"] - #[inline(always)] - pub fn opamp1(&mut self) -> Opamp1W { - Opamp1W::new(self, 9) - } - #[doc = "Bit 10 - OPAMP2"] - #[inline(always)] - pub fn opamp2(&mut self) -> Opamp2W { - Opamp2W::new(self, 10) - } - #[doc = "Bit 11 - OPAMP3"] - #[inline(always)] - pub fn opamp3(&mut self) -> Opamp3W { - Opamp3W::new(self, 11) - } - #[doc = "Bit 12 - PORT0"] - #[inline(always)] - pub fn port0(&mut self) -> Port0W { - Port0W::new(self, 12) - } - #[doc = "Bit 13 - PORT1"] - #[inline(always)] - pub fn port1(&mut self) -> Port1W { - Port1W::new(self, 13) - } - #[doc = "Bit 14 - PORT2"] - #[inline(always)] - pub fn port2(&mut self) -> Port2W { - Port2W::new(self, 14) - } - #[doc = "Bit 15 - PORT3"] - #[inline(always)] - pub fn port3(&mut self) -> Port3W { - Port3W::new(self, 15) - } - #[doc = "Bit 16 - PORT4"] - #[inline(always)] - pub fn port4(&mut self) -> Port4W { - Port4W::new(self, 16) - } - #[doc = "Bit 17 - SLCD0"] - #[inline(always)] - pub fn slcd0(&mut self) -> Slcd0W { - Slcd0W::new(self, 17) - } - #[doc = "Bit 18 - FLEXCAN0"] - #[inline(always)] - pub fn flexcan0(&mut self) -> Flexcan0W { - Flexcan0W::new(self, 18) - } - #[doc = "Bit 19 - FLEXCAN1"] - #[inline(always)] - pub fn flexcan1(&mut self) -> Flexcan1W { - Flexcan1W::new(self, 19) - } - #[doc = "Bit 20 - LPI2C2"] - #[inline(always)] - pub fn lpi2c2(&mut self) -> Lpi2c2W { - Lpi2c2W::new(self, 20) - } - #[doc = "Bit 21 - LPI2C3"] - #[inline(always)] - pub fn lpi2c3(&mut self) -> Lpi2c3W { - Lpi2c3W::new(self, 21) - } - #[doc = "Bit 22 - LPUART5"] - #[inline(always)] - pub fn lpuart5(&mut self) -> Lpuart5W { - Lpuart5W::new(self, 22) - } - #[doc = "Bit 24 - PKC0"] - #[inline(always)] - pub fn pkc0(&mut self) -> Pkc0W { - Pkc0W::new(self, 24) - } - #[doc = "Bit 26 - TRNG0"] - #[inline(always)] - pub fn trng0(&mut self) -> Trng0W { - Trng0W::new(self, 26) - } - #[doc = "Bit 28 - ADC2"] - #[inline(always)] - pub fn adc2(&mut self) -> Adc2W { - Adc2W::new(self, 28) - } - #[doc = "Bit 29 - ADC3"] - #[inline(always)] - pub fn adc3(&mut self) -> Adc3W { - Adc3W::new(self, 29) - } -} -#[doc = "Peripheral Reset Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst1Spec; -impl crate::RegisterSpec for MrccGlbRst1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_rst1::R`](R) reader structure"] -impl crate::Readable for MrccGlbRst1Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst1::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST1 to value 0"] -impl crate::Resettable for MrccGlbRst1Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs deleted file mode 100644 index 3cd0b5377..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_clr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST1_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Peripheral Reset Control Clear 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst1ClrSpec; -impl crate::RegisterSpec for MrccGlbRst1ClrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst1_clr::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst1ClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST1_CLR to value 0"] -impl crate::Resettable for MrccGlbRst1ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs deleted file mode 100644 index 0afffe172..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst1_set.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST1_SET` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Peripheral Reset Control Set 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst1_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst1SetSpec; -impl crate::RegisterSpec for MrccGlbRst1SetSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst1_set::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst1SetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST1_SET to value 0"] -impl crate::Resettable for MrccGlbRst1SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs deleted file mode 100644 index c46aa85b9..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST2` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_GLB_RST2` writer"] -pub type W = crate::W; -#[doc = "GPIO0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO0` reader - GPIO0"] -pub type Gpio0R = crate::BitReader; -impl Gpio0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio0 { - match self.bits { - false => Gpio0::Disabled, - true => Gpio0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio0::Enabled - } -} -#[doc = "Field `GPIO0` writer - GPIO0"] -pub type Gpio0W<'a, REG> = crate::BitWriter<'a, REG, Gpio0>; -impl<'a, REG> Gpio0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio0::Enabled) - } -} -#[doc = "GPIO1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio1 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO1` reader - GPIO1"] -pub type Gpio1R = crate::BitReader; -impl Gpio1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio1 { - match self.bits { - false => Gpio1::Disabled, - true => Gpio1::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio1::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio1::Enabled - } -} -#[doc = "Field `GPIO1` writer - GPIO1"] -pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG, Gpio1>; -impl<'a, REG> Gpio1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio1::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio1::Enabled) - } -} -#[doc = "GPIO2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio2 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO2` reader - GPIO2"] -pub type Gpio2R = crate::BitReader; -impl Gpio2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio2 { - match self.bits { - false => Gpio2::Disabled, - true => Gpio2::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio2::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio2::Enabled - } -} -#[doc = "Field `GPIO2` writer - GPIO2"] -pub type Gpio2W<'a, REG> = crate::BitWriter<'a, REG, Gpio2>; -impl<'a, REG> Gpio2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio2::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio2::Enabled) - } -} -#[doc = "GPIO3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio3 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO3` reader - GPIO3"] -pub type Gpio3R = crate::BitReader; -impl Gpio3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio3 { - match self.bits { - false => Gpio3::Disabled, - true => Gpio3::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio3::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio3::Enabled - } -} -#[doc = "Field `GPIO3` writer - GPIO3"] -pub type Gpio3W<'a, REG> = crate::BitWriter<'a, REG, Gpio3>; -impl<'a, REG> Gpio3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio3::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio3::Enabled) - } -} -#[doc = "GPIO4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpio4 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpio4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPIO4` reader - GPIO4"] -pub type Gpio4R = crate::BitReader; -impl Gpio4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpio4 { - match self.bits { - false => Gpio4::Disabled, - true => Gpio4::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Gpio4::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Gpio4::Enabled - } -} -#[doc = "Field `GPIO4` writer - GPIO4"] -pub type Gpio4W<'a, REG> = crate::BitWriter<'a, REG, Gpio4>; -impl<'a, REG> Gpio4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Gpio4::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Gpio4::Enabled) - } -} -#[doc = "MAU0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mau0 { - #[doc = "0: Peripheral is held in reset"] - Disabled = 0, - #[doc = "1: Peripheral is released from reset"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mau0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MAU0` reader - MAU0"] -pub type Mau0R = crate::BitReader; -impl Mau0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mau0 { - match self.bits { - false => Mau0::Disabled, - true => Mau0::Enabled, - } - } - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Mau0::Disabled - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Mau0::Enabled - } -} -#[doc = "Field `MAU0` writer - MAU0"] -pub type Mau0W<'a, REG> = crate::BitWriter<'a, REG, Mau0>; -impl<'a, REG> Mau0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Peripheral is held in reset"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Mau0::Disabled) - } - #[doc = "Peripheral is released from reset"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Mau0::Enabled) - } -} -impl R { - #[doc = "Bit 4 - GPIO0"] - #[inline(always)] - pub fn gpio0(&self) -> Gpio0R { - Gpio0R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - GPIO1"] - #[inline(always)] - pub fn gpio1(&self) -> Gpio1R { - Gpio1R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - GPIO2"] - #[inline(always)] - pub fn gpio2(&self) -> Gpio2R { - Gpio2R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - GPIO3"] - #[inline(always)] - pub fn gpio3(&self) -> Gpio3R { - Gpio3R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - GPIO4"] - #[inline(always)] - pub fn gpio4(&self) -> Gpio4R { - Gpio4R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - MAU0"] - #[inline(always)] - pub fn mau0(&self) -> Mau0R { - Mau0R::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 4 - GPIO0"] - #[inline(always)] - pub fn gpio0(&mut self) -> Gpio0W { - Gpio0W::new(self, 4) - } - #[doc = "Bit 5 - GPIO1"] - #[inline(always)] - pub fn gpio1(&mut self) -> Gpio1W { - Gpio1W::new(self, 5) - } - #[doc = "Bit 6 - GPIO2"] - #[inline(always)] - pub fn gpio2(&mut self) -> Gpio2W { - Gpio2W::new(self, 6) - } - #[doc = "Bit 7 - GPIO3"] - #[inline(always)] - pub fn gpio3(&mut self) -> Gpio3W { - Gpio3W::new(self, 7) - } - #[doc = "Bit 8 - GPIO4"] - #[inline(always)] - pub fn gpio4(&mut self) -> Gpio4W { - Gpio4W::new(self, 8) - } - #[doc = "Bit 9 - MAU0"] - #[inline(always)] - pub fn mau0(&mut self) -> Mau0W { - Mau0W::new(self, 9) - } -} -#[doc = "Peripheral Reset Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_rst2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst2Spec; -impl crate::RegisterSpec for MrccGlbRst2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_glb_rst2::R`](R) reader structure"] -impl crate::Readable for MrccGlbRst2Spec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst2::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST2 to value 0"] -impl crate::Resettable for MrccGlbRst2Spec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs deleted file mode 100644 index 91afe580f..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_clr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST2_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Peripheral Reset Control Clear 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst2ClrSpec; -impl crate::RegisterSpec for MrccGlbRst2ClrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst2_clr::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst2ClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST2_CLR to value 0"] -impl crate::Resettable for MrccGlbRst2ClrSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs b/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs deleted file mode 100644 index ccd36786a..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_glb_rst2_set.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `MRCC_GLB_RST2_SET` writer"] -pub type W = crate::W; -#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] -pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub fn data(&mut self) -> DataW { - DataW::new(self, 0) - } -} -#[doc = "Peripheral Reset Control Set 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_rst2_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccGlbRst2SetSpec; -impl crate::RegisterSpec for MrccGlbRst2SetSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`mrcc_glb_rst2_set::W`](W) writer structure"] -impl crate::Writable for MrccGlbRst2SetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_GLB_RST2_SET to value 0"] -impl crate::Resettable for MrccGlbRst2SetSpec {} diff --git a/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs deleted file mode 100644 index 267469047..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_I3C0_FCLK_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_I3C0_FCLK_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "I3C0_FCLK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccI3c0FclkClkdivSpec; -impl crate::RegisterSpec for MrccI3c0FclkClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_i3c0_fclk_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccI3c0FclkClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_i3c0_fclk_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccI3c0FclkClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_I3C0_FCLK_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccI3c0FclkClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs deleted file mode 100644 index c5b13eb95..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_i3c0_fclk_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_I3C0_FCLK_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_I3C0_FCLK_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "I3C0_FCLK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_i3c0_fclk_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_i3c0_fclk_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccI3c0FclkClkselSpec; -impl crate::RegisterSpec for MrccI3c0FclkClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_i3c0_fclk_clksel::R`](R) reader structure"] -impl crate::Readable for MrccI3c0FclkClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_i3c0_fclk_clksel::W`](W) writer structure"] -impl crate::Writable for MrccI3c0FclkClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_I3C0_FCLK_CLKSEL to value 0x07"] -impl crate::Resettable for MrccI3c0FclkClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs deleted file mode 100644 index af9093dd8..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPI2C0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPI2C0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c0ClkdivSpec; -impl crate::RegisterSpec for MrccLpi2c0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpi2c0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs deleted file mode 100644 index 1fc51c06f..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c0_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_LPI2C0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPI2C0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c0ClkselSpec; -impl crate::RegisterSpec for MrccLpi2c0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpi2c0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs deleted file mode 100644 index 69d200248..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPI2C1_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C1_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPI2C1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c1ClkdivSpec; -impl crate::RegisterSpec for MrccLpi2c1ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c1_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c1ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c1_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c1ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C1_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpi2c1ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs deleted file mode 100644 index 555c782c7..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c1_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_LPI2C1_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C1_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPI2C1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c1ClkselSpec; -impl crate::RegisterSpec for MrccLpi2c1ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c1_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c1ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c1_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c1ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C1_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpi2c1ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs deleted file mode 100644 index 9d6d04e96..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPI2C2_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C2_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPI2C2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c2ClkdivSpec; -impl crate::RegisterSpec for MrccLpi2c2ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c2_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c2ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c2_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c2ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C2_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpi2c2ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs deleted file mode 100644 index 1179207cd..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c2_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_LPI2C2_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C2_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPI2C2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c2_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c2_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c2ClkselSpec; -impl crate::RegisterSpec for MrccLpi2c2ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c2_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c2ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c2_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c2ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C2_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpi2c2ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs deleted file mode 100644 index afa745322..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPI2C3_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C3_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPI2C3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c3ClkdivSpec; -impl crate::RegisterSpec for MrccLpi2c3ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c3_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c3ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c3_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c3ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C3_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpi2c3ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs deleted file mode 100644 index 8137576a7..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpi2c3_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_LPI2C3_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPI2C3_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPI2C3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpi2c3_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpi2c3_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpi2c3ClkselSpec; -impl crate::RegisterSpec for MrccLpi2c3ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpi2c3_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpi2c3ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpi2c3_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpi2c3ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPI2C3_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpi2c3ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs deleted file mode 100644 index 85d92c8c4..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPSPI0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPSPI0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPSPI0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpspi0ClkdivSpec; -impl crate::RegisterSpec for MrccLpspi0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpspi0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpspi0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpspi0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPSPI0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpspi0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs deleted file mode 100644 index 41244a760..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpspi0_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_LPSPI0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPSPI0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPSPI0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpspi0ClkselSpec; -impl crate::RegisterSpec for MrccLpspi0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpspi0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpspi0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpspi0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPSPI0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpspi0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs deleted file mode 100644 index ccde8afee..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPSPI1_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPSPI1_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPSPI1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpspi1ClkdivSpec; -impl crate::RegisterSpec for MrccLpspi1ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpspi1_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpspi1ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi1_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpspi1ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPSPI1_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpspi1ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs deleted file mode 100644 index c0217bee6..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpspi1_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_LPSPI1_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPSPI1_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPSPI1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpspi1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpspi1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpspi1ClkselSpec; -impl crate::RegisterSpec for MrccLpspi1ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpspi1_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpspi1ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpspi1_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpspi1ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPSPI1_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpspi1ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs deleted file mode 100644 index 3a08bff78..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPTMR0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPTMR0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPTMR0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLptmr0ClkdivSpec; -impl crate::RegisterSpec for MrccLptmr0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lptmr0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLptmr0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lptmr0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLptmr0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPTMR0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLptmr0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs deleted file mode 100644 index c93c4c45e..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lptmr0_clksel.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `MRCC_LPTMR0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPTMR0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPTMR0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lptmr0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lptmr0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLptmr0ClkselSpec; -impl crate::RegisterSpec for MrccLptmr0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lptmr0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLptmr0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lptmr0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLptmr0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPTMR0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLptmr0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs deleted file mode 100644 index e15c95f92..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPUART0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPUART0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart0ClkdivSpec; -impl crate::RegisterSpec for MrccLpuart0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpuart0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpuart0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpuart0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs deleted file mode 100644 index 88e4a2ebd..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart0_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_LPUART0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPUART0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart0ClkselSpec; -impl crate::RegisterSpec for MrccLpuart0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpuart0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpuart0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART0_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpuart0ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs deleted file mode 100644 index 96def465f..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPUART1_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART1_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPUART1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart1ClkdivSpec; -impl crate::RegisterSpec for MrccLpuart1ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart1_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpuart1ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart1_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpuart1ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART1_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpuart1ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs deleted file mode 100644 index c0667e0af..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart1_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_LPUART1_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART1_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPUART1 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart1_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart1_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart1ClkselSpec; -impl crate::RegisterSpec for MrccLpuart1ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart1_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpuart1ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart1_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpuart1ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART1_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpuart1ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs deleted file mode 100644 index ae202770e..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPUART2_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART2_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPUART2 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart2ClkdivSpec; -impl crate::RegisterSpec for MrccLpuart2ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart2_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpuart2ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart2_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpuart2ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART2_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpuart2ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs deleted file mode 100644 index a61e9cc9f..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart2_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_LPUART2_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART2_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPUART2 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart2_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart2_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart2ClkselSpec; -impl crate::RegisterSpec for MrccLpuart2ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart2_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpuart2ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart2_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpuart2ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART2_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpuart2ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs deleted file mode 100644 index 228849012..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPUART3_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART3_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPUART3 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart3ClkdivSpec; -impl crate::RegisterSpec for MrccLpuart3ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart3_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpuart3ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart3_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpuart3ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART3_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpuart3ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs deleted file mode 100644 index f830c0031..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart3_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_LPUART3_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART3_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPUART3 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart3_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart3_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart3ClkselSpec; -impl crate::RegisterSpec for MrccLpuart3ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart3_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpuart3ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart3_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpuart3ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART3_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpuart3ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs deleted file mode 100644 index dd8554552..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPUART4_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART4_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPUART4 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart4ClkdivSpec; -impl crate::RegisterSpec for MrccLpuart4ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart4_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpuart4ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart4_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpuart4ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART4_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpuart4ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs deleted file mode 100644 index 83105959f..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart4_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_LPUART4_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART4_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPUART4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart4_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart4_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart4ClkselSpec; -impl crate::RegisterSpec for MrccLpuart4ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart4_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpuart4ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart4_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpuart4ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART4_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpuart4ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs deleted file mode 100644 index 71f59d36b..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_LPUART5_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART5_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "LPUART5 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart5ClkdivSpec; -impl crate::RegisterSpec for MrccLpuart5ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart5_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccLpuart5ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart5_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccLpuart5ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART5_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccLpuart5ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs deleted file mode 100644 index b89a6f388..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_lpuart5_clksel.rs +++ /dev/null @@ -1,145 +0,0 @@ -#[doc = "Register `MRCC_LPUART5_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_LPUART5_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: FRO_LF_DIV"] - ClkrootFunc0 = 0, - #[doc = "2: FRO_HF_DIV"] - ClkrootFunc2 = 2, - #[doc = "3: CLK_IN"] - ClkrootFunc3 = 3, - #[doc = "4: CLK_16K"] - ClkrootFunc4 = 4, - #[doc = "5: CLK_1M"] - ClkrootFunc5 = 5, - #[doc = "6: PLL1_CLK_DIV"] - ClkrootFunc6 = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootFunc0), - 2 => Some(Mux::ClkrootFunc2), - 3 => Some(Mux::ClkrootFunc3), - 4 => Some(Mux::ClkrootFunc4), - 5 => Some(Mux::ClkrootFunc5), - 6 => Some(Mux::ClkrootFunc6), - _ => None, - } - } - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_0(&self) -> bool { - *self == Mux::ClkrootFunc0 - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn is_clkroot_func_2(&self) -> bool { - *self == Mux::ClkrootFunc2 - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_func_3(&self) -> bool { - *self == Mux::ClkrootFunc3 - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_func_4(&self) -> bool { - *self == Mux::ClkrootFunc4 - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_func_5(&self) -> bool { - *self == Mux::ClkrootFunc5 - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn is_clkroot_func_6(&self) -> bool { - *self == Mux::ClkrootFunc6 - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "FRO_LF_DIV"] - #[inline(always)] - pub fn clkroot_func_0(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc0) - } - #[doc = "FRO_HF_DIV"] - #[inline(always)] - pub fn clkroot_func_2(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc2) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_func_3(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc3) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_func_4(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc4) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_func_5(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc5) - } - #[doc = "PLL1_CLK_DIV"] - #[inline(always)] - pub fn clkroot_func_6(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootFunc6) - } -} -impl R { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "LPUART5 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_lpuart5_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_lpuart5_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccLpuart5ClkselSpec; -impl crate::RegisterSpec for MrccLpuart5ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_lpuart5_clksel::R`](R) reader structure"] -impl crate::Readable for MrccLpuart5ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_lpuart5_clksel::W`](W) writer structure"] -impl crate::Writable for MrccLpuart5ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_LPUART5_CLKSEL to value 0x07"] -impl crate::Resettable for MrccLpuart5ClkselSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs deleted file mode 100644 index d61da5bb0..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_ostimer0_clksel.rs +++ /dev/null @@ -1,93 +0,0 @@ -#[doc = "Register `MRCC_OSTIMER0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_OSTIMER0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: CLK_16K"] - Clkroot16k = 0, - #[doc = "2: CLK_1M"] - Clkroot1m = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Clkroot16k), - 2 => Some(Mux::Clkroot1m), - _ => None, - } - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_16k(&self) -> bool { - *self == Mux::Clkroot16k - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_1m(&self) -> bool { - *self == Mux::Clkroot1m - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_16k(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot16k) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_1m(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot1m) - } -} -impl R { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "OSTIMER0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ostimer0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ostimer0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccOstimer0ClkselSpec; -impl crate::RegisterSpec for MrccOstimer0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_ostimer0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccOstimer0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_ostimer0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccOstimer0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_OSTIMER0_CLKSEL to value 0x03"] -impl crate::Resettable for MrccOstimer0ClkselSpec { - const RESET_VALUE: u32 = 0x03; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs deleted file mode 100644 index 3cf688924..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_systick_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_SYSTICK_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_SYSTICK_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "SYSTICK clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccSystickClkdivSpec; -impl crate::RegisterSpec for MrccSystickClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_systick_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccSystickClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_systick_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccSystickClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_SYSTICK_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccSystickClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs deleted file mode 100644 index 1545b66dd..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_systick_clksel.rs +++ /dev/null @@ -1,106 +0,0 @@ -#[doc = "Register `MRCC_SYSTICK_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_SYSTICK_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: CPU_CLK"] - ClkrootCpu = 0, - #[doc = "1: CLK_1M"] - Clkroot1m = 1, - #[doc = "2: CLK_16K"] - Clkroot16k = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootCpu), - 1 => Some(Mux::Clkroot1m), - 2 => Some(Mux::Clkroot16k), - _ => None, - } - } - #[doc = "CPU_CLK"] - #[inline(always)] - pub fn is_clkroot_cpu(&self) -> bool { - *self == Mux::ClkrootCpu - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn is_clkroot_1m(&self) -> bool { - *self == Mux::Clkroot1m - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn is_clkroot_16k(&self) -> bool { - *self == Mux::Clkroot16k - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CPU_CLK"] - #[inline(always)] - pub fn clkroot_cpu(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootCpu) - } - #[doc = "CLK_1M"] - #[inline(always)] - pub fn clkroot_1m(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot1m) - } - #[doc = "CLK_16K"] - #[inline(always)] - pub fn clkroot_16k(self) -> &'a mut crate::W { - self.variant(Mux::Clkroot16k) - } -} -impl R { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "SYSTICK clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_systick_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_systick_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccSystickClkselSpec; -impl crate::RegisterSpec for MrccSystickClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_systick_clksel::R`](R) reader structure"] -impl crate::Readable for MrccSystickClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_systick_clksel::W`](W) writer structure"] -impl crate::Writable for MrccSystickClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_SYSTICK_CLKSEL to value 0x03"] -impl crate::Resettable for MrccSystickClkselSpec { - const RESET_VALUE: u32 = 0x03; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs deleted file mode 100644 index 83588fa02..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_usb0_clkdiv.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `MRCC_USB0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_USB0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "USB0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccUsb0ClkdivSpec; -impl crate::RegisterSpec for MrccUsb0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_usb0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccUsb0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_usb0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccUsb0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_USB0_CLKDIV to value 0x4000_0000"] -impl crate::Resettable for MrccUsb0ClkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs b/mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs deleted file mode 100644 index 7d0af232e..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_usb0_clksel.rs +++ /dev/null @@ -1,106 +0,0 @@ -#[doc = "Register `MRCC_USB0_CLKSEL` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_USB0_CLKSEL` writer"] -pub type W = crate::W; -#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: PLL1_CLK"] - ClkrootSpll = 0, - #[doc = "1: CLK_48M"] - ScgScgFirc48mhzClk = 1, - #[doc = "2: CLK_IN"] - ClkrootSosc = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Functional Clock Mux Select"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::ClkrootSpll), - 1 => Some(Mux::ScgScgFirc48mhzClk), - 2 => Some(Mux::ClkrootSosc), - _ => None, - } - } - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn is_clkroot_spll(&self) -> bool { - *self == Mux::ClkrootSpll - } - #[doc = "CLK_48M"] - #[inline(always)] - pub fn is_scg_scg_firc_48mhz_clk(&self) -> bool { - *self == Mux::ScgScgFirc48mhzClk - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn is_clkroot_sosc(&self) -> bool { - *self == Mux::ClkrootSosc - } -} -#[doc = "Field `MUX` writer - Functional Clock Mux Select"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "PLL1_CLK"] - #[inline(always)] - pub fn clkroot_spll(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSpll) - } - #[doc = "CLK_48M"] - #[inline(always)] - pub fn scg_scg_firc_48mhz_clk(self) -> &'a mut crate::W { - self.variant(Mux::ScgScgFirc48mhzClk) - } - #[doc = "CLK_IN"] - #[inline(always)] - pub fn clkroot_sosc(self) -> &'a mut crate::W { - self.variant(Mux::ClkrootSosc) - } -} -impl R { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Functional Clock Mux Select"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 0) - } -} -#[doc = "USB0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccUsb0ClkselSpec; -impl crate::RegisterSpec for MrccUsb0ClkselSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_usb0_clksel::R`](R) reader structure"] -impl crate::Readable for MrccUsb0ClkselSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_usb0_clksel::W`](W) writer structure"] -impl crate::Writable for MrccUsb0ClkselSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_USB0_CLKSEL to value 0x03"] -impl crate::Resettable for MrccUsb0ClkselSpec { - const RESET_VALUE: u32 = 0x03; -} diff --git a/mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs b/mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs deleted file mode 100644 index 43aa31c92..000000000 --- a/mcxa276-pac/src/mrcc0/mrcc_wwdt0_clkdiv.rs +++ /dev/null @@ -1,175 +0,0 @@ -#[doc = "Register `MRCC_WWDT0_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `MRCC_WWDT0_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Functional Clock Divider"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Functional Clock Divider"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Reset divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider isn't reset"] - On = 0, - #[doc = "1: Divider is reset"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` writer - Reset divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider isn't reset"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Reset::On) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Reset::Off) - } -} -#[doc = "Halt divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - On = 0, - #[doc = "1: Divider clock is stopped"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halt divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::On, - true => Halt::Off, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Halt::On - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Halt::Off - } -} -#[doc = "Field `HALT` writer - Halt divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn on(self) -> &'a mut crate::W { - self.variant(Halt::On) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn off(self) -> &'a mut crate::W { - self.variant(Halt::Off) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - On = 0, - #[doc = "1: Clock frequency isn't stable"] - Off = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::On, - true => Unstab::Off, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_on(&self) -> bool { - *self == Unstab::On - } - #[doc = "Clock frequency isn't stable"] - #[inline(always)] - pub fn is_off(&self) -> bool { - *self == Unstab::Off - } -} -impl R { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:3 - Functional Clock Divider"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Reset divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halt divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "WWDT0 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_wwdt0_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_wwdt0_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MrccWwdt0ClkdivSpec; -impl crate::RegisterSpec for MrccWwdt0ClkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mrcc_wwdt0_clkdiv::R`](R) reader structure"] -impl crate::Readable for MrccWwdt0ClkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`mrcc_wwdt0_clkdiv::W`](W) writer structure"] -impl crate::Writable for MrccWwdt0ClkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MRCC_WWDT0_CLKDIV to value 0"] -impl crate::Resettable for MrccWwdt0ClkdivSpec {} diff --git a/mcxa276-pac/src/opamp0.rs b/mcxa276-pac/src/opamp0.rs deleted file mode 100644 index 94ff0bd7d..000000000 --- a/mcxa276-pac/src/opamp0.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - opamp_ctrl: OpampCtrl, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x08 - OPAMP Control"] - #[inline(always)] - pub const fn opamp_ctrl(&self) -> &OpampCtrl { - &self.opamp_ctrl - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "OPAMP_CTRL (rw) register accessor: OPAMP Control\n\nYou can [`read`](crate::Reg::read) this register and get [`opamp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opamp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@opamp_ctrl`] module"] -#[doc(alias = "OPAMP_CTRL")] -pub type OpampCtrl = crate::Reg; -#[doc = "OPAMP Control"] -pub mod opamp_ctrl; diff --git a/mcxa276-pac/src/opamp0/opamp_ctrl.rs b/mcxa276-pac/src/opamp0/opamp_ctrl.rs deleted file mode 100644 index eb3a84a5a..000000000 --- a/mcxa276-pac/src/opamp0/opamp_ctrl.rs +++ /dev/null @@ -1,276 +0,0 @@ -#[doc = "Register `OPAMP_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `OPAMP_CTRL` writer"] -pub type W = crate::W; -#[doc = "OPAMP Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OpaEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OpaEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OPA_EN` reader - OPAMP Enable"] -pub type OpaEnR = crate::BitReader; -impl OpaEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OpaEn { - match self.bits { - false => OpaEn::Disable, - true => OpaEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == OpaEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == OpaEn::Enable - } -} -#[doc = "Field `OPA_EN` writer - OPAMP Enable"] -pub type OpaEnW<'a, REG> = crate::BitWriter<'a, REG, OpaEn>; -impl<'a, REG> OpaEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(OpaEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(OpaEn::Enable) - } -} -#[doc = "Compensation capcitor config selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OpaCcSel { - #[doc = "0: Fit 2X gains"] - Tbd1 = 0, - #[doc = "1: Fit 4X gains"] - Tbd2 = 1, - #[doc = "2: Fit 8X gains"] - Tbd3 = 2, - #[doc = "3: Fit 16X gains"] - Tbd4 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OpaCcSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OpaCcSel { - type Ux = u8; -} -impl crate::IsEnum for OpaCcSel {} -#[doc = "Field `OPA_CC_SEL` reader - Compensation capcitor config selection"] -pub type OpaCcSelR = crate::FieldReader; -impl OpaCcSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OpaCcSel { - match self.bits { - 0 => OpaCcSel::Tbd1, - 1 => OpaCcSel::Tbd2, - 2 => OpaCcSel::Tbd3, - 3 => OpaCcSel::Tbd4, - _ => unreachable!(), - } - } - #[doc = "Fit 2X gains"] - #[inline(always)] - pub fn is_tbd1(&self) -> bool { - *self == OpaCcSel::Tbd1 - } - #[doc = "Fit 4X gains"] - #[inline(always)] - pub fn is_tbd2(&self) -> bool { - *self == OpaCcSel::Tbd2 - } - #[doc = "Fit 8X gains"] - #[inline(always)] - pub fn is_tbd3(&self) -> bool { - *self == OpaCcSel::Tbd3 - } - #[doc = "Fit 16X gains"] - #[inline(always)] - pub fn is_tbd4(&self) -> bool { - *self == OpaCcSel::Tbd4 - } -} -#[doc = "Field `OPA_CC_SEL` writer - Compensation capcitor config selection"] -pub type OpaCcSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, OpaCcSel, crate::Safe>; -impl<'a, REG> OpaCcSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Fit 2X gains"] - #[inline(always)] - pub fn tbd1(self) -> &'a mut crate::W { - self.variant(OpaCcSel::Tbd1) - } - #[doc = "Fit 4X gains"] - #[inline(always)] - pub fn tbd2(self) -> &'a mut crate::W { - self.variant(OpaCcSel::Tbd2) - } - #[doc = "Fit 8X gains"] - #[inline(always)] - pub fn tbd3(self) -> &'a mut crate::W { - self.variant(OpaCcSel::Tbd3) - } - #[doc = "Fit 16X gains"] - #[inline(always)] - pub fn tbd4(self) -> &'a mut crate::W { - self.variant(OpaCcSel::Tbd4) - } -} -#[doc = "Bias current config selection\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OpaBcSel { - #[doc = "0: Default value. Keep power consumption constant"] - Tbd1 = 0, - #[doc = "1: Reduce power consumption to 1/4"] - Tbd2 = 1, - #[doc = "2: Reduce power consumption to 1/2"] - Tbd3 = 2, - #[doc = "3: Double the power consumption"] - Tbd4 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OpaBcSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OpaBcSel { - type Ux = u8; -} -impl crate::IsEnum for OpaBcSel {} -#[doc = "Field `OPA_BC_SEL` reader - Bias current config selection"] -pub type OpaBcSelR = crate::FieldReader; -impl OpaBcSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OpaBcSel { - match self.bits { - 0 => OpaBcSel::Tbd1, - 1 => OpaBcSel::Tbd2, - 2 => OpaBcSel::Tbd3, - 3 => OpaBcSel::Tbd4, - _ => unreachable!(), - } - } - #[doc = "Default value. Keep power consumption constant"] - #[inline(always)] - pub fn is_tbd1(&self) -> bool { - *self == OpaBcSel::Tbd1 - } - #[doc = "Reduce power consumption to 1/4"] - #[inline(always)] - pub fn is_tbd2(&self) -> bool { - *self == OpaBcSel::Tbd2 - } - #[doc = "Reduce power consumption to 1/2"] - #[inline(always)] - pub fn is_tbd3(&self) -> bool { - *self == OpaBcSel::Tbd3 - } - #[doc = "Double the power consumption"] - #[inline(always)] - pub fn is_tbd4(&self) -> bool { - *self == OpaBcSel::Tbd4 - } -} -#[doc = "Field `OPA_BC_SEL` writer - Bias current config selection"] -pub type OpaBcSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, OpaBcSel, crate::Safe>; -impl<'a, REG> OpaBcSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Default value. Keep power consumption constant"] - #[inline(always)] - pub fn tbd1(self) -> &'a mut crate::W { - self.variant(OpaBcSel::Tbd1) - } - #[doc = "Reduce power consumption to 1/4"] - #[inline(always)] - pub fn tbd2(self) -> &'a mut crate::W { - self.variant(OpaBcSel::Tbd2) - } - #[doc = "Reduce power consumption to 1/2"] - #[inline(always)] - pub fn tbd3(self) -> &'a mut crate::W { - self.variant(OpaBcSel::Tbd3) - } - #[doc = "Double the power consumption"] - #[inline(always)] - pub fn tbd4(self) -> &'a mut crate::W { - self.variant(OpaBcSel::Tbd4) - } -} -impl R { - #[doc = "Bit 0 - OPAMP Enable"] - #[inline(always)] - pub fn opa_en(&self) -> OpaEnR { - OpaEnR::new((self.bits & 1) != 0) - } - #[doc = "Bits 4:5 - Compensation capcitor config selection"] - #[inline(always)] - pub fn opa_cc_sel(&self) -> OpaCcSelR { - OpaCcSelR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Bias current config selection"] - #[inline(always)] - pub fn opa_bc_sel(&self) -> OpaBcSelR { - OpaBcSelR::new(((self.bits >> 6) & 3) as u8) - } -} -impl W { - #[doc = "Bit 0 - OPAMP Enable"] - #[inline(always)] - pub fn opa_en(&mut self) -> OpaEnW { - OpaEnW::new(self, 0) - } - #[doc = "Bits 4:5 - Compensation capcitor config selection"] - #[inline(always)] - pub fn opa_cc_sel(&mut self) -> OpaCcSelW { - OpaCcSelW::new(self, 4) - } - #[doc = "Bits 6:7 - Bias current config selection"] - #[inline(always)] - pub fn opa_bc_sel(&mut self) -> OpaBcSelW { - OpaBcSelW::new(self, 6) - } -} -#[doc = "OPAMP Control\n\nYou can [`read`](crate::Reg::read) this register and get [`opamp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`opamp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OpampCtrlSpec; -impl crate::RegisterSpec for OpampCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`opamp_ctrl::R`](R) reader structure"] -impl crate::Readable for OpampCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`opamp_ctrl::W`](W) writer structure"] -impl crate::Writable for OpampCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets OPAMP_CTRL to value 0"] -impl crate::Resettable for OpampCtrlSpec {} diff --git a/mcxa276-pac/src/opamp0/param.rs b/mcxa276-pac/src/opamp0/param.rs deleted file mode 100644 index c132ea417..000000000 --- a/mcxa276-pac/src/opamp0/param.rs +++ /dev/null @@ -1,16 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0"] -impl crate::Resettable for ParamSpec {} diff --git a/mcxa276-pac/src/opamp0/verid.rs b/mcxa276-pac/src/opamp0/verid.rs deleted file mode 100644 index 26e3283cc..000000000 --- a/mcxa276-pac/src/opamp0/verid.rs +++ /dev/null @@ -1,34 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0"] -impl crate::Resettable for VeridSpec {} diff --git a/mcxa276-pac/src/ostimer0.rs b/mcxa276-pac/src/ostimer0.rs deleted file mode 100644 index 64ad679af..000000000 --- a/mcxa276-pac/src/ostimer0.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - evtimerl: Evtimerl, - evtimerh: Evtimerh, - capture_l: CaptureL, - capture_h: CaptureH, - match_l: MatchL, - match_h: MatchH, - _reserved6: [u8; 0x04], - osevent_ctrl: OseventCtrl, -} -impl RegisterBlock { - #[doc = "0x00 - EVTIMER Low"] - #[inline(always)] - pub const fn evtimerl(&self) -> &Evtimerl { - &self.evtimerl - } - #[doc = "0x04 - EVTIMER High"] - #[inline(always)] - pub const fn evtimerh(&self) -> &Evtimerh { - &self.evtimerh - } - #[doc = "0x08 - Local Capture Low for CPU"] - #[inline(always)] - pub const fn capture_l(&self) -> &CaptureL { - &self.capture_l - } - #[doc = "0x0c - Local Capture High for CPU"] - #[inline(always)] - pub const fn capture_h(&self) -> &CaptureH { - &self.capture_h - } - #[doc = "0x10 - Local Match Low for CPU"] - #[inline(always)] - pub const fn match_l(&self) -> &MatchL { - &self.match_l - } - #[doc = "0x14 - Local Match High for CPU"] - #[inline(always)] - pub const fn match_h(&self) -> &MatchH { - &self.match_h - } - #[doc = "0x1c - OSTIMER Control for CPU"] - #[inline(always)] - pub const fn osevent_ctrl(&self) -> &OseventCtrl { - &self.osevent_ctrl - } -} -#[doc = "EVTIMERL (r) register accessor: EVTIMER Low\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evtimerl`] module"] -#[doc(alias = "EVTIMERL")] -pub type Evtimerl = crate::Reg; -#[doc = "EVTIMER Low"] -pub mod evtimerl; -#[doc = "EVTIMERH (r) register accessor: EVTIMER High\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evtimerh`] module"] -#[doc(alias = "EVTIMERH")] -pub type Evtimerh = crate::Reg; -#[doc = "EVTIMER High"] -pub mod evtimerh; -#[doc = "CAPTURE_L (r) register accessor: Local Capture Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_l::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capture_l`] module"] -#[doc(alias = "CAPTURE_L")] -pub type CaptureL = crate::Reg; -#[doc = "Local Capture Low for CPU"] -pub mod capture_l; -#[doc = "CAPTURE_H (r) register accessor: Local Capture High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_h::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capture_h`] module"] -#[doc(alias = "CAPTURE_H")] -pub type CaptureH = crate::Reg; -#[doc = "Local Capture High for CPU"] -pub mod capture_h; -#[doc = "MATCH_L (rw) register accessor: Local Match Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_l`] module"] -#[doc(alias = "MATCH_L")] -pub type MatchL = crate::Reg; -#[doc = "Local Match Low for CPU"] -pub mod match_l; -#[doc = "MATCH_H (rw) register accessor: Local Match High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_h`] module"] -#[doc(alias = "MATCH_H")] -pub type MatchH = crate::Reg; -#[doc = "Local Match High for CPU"] -pub mod match_h; -#[doc = "OSEVENT_CTRL (rw) register accessor: OSTIMER Control for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`osevent_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osevent_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osevent_ctrl`] module"] -#[doc(alias = "OSEVENT_CTRL")] -pub type OseventCtrl = crate::Reg; -#[doc = "OSTIMER Control for CPU"] -pub mod osevent_ctrl; diff --git a/mcxa276-pac/src/ostimer0/capture_h.rs b/mcxa276-pac/src/ostimer0/capture_h.rs deleted file mode 100644 index 57b7c1500..000000000 --- a/mcxa276-pac/src/ostimer0/capture_h.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `CAPTURE_H` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTURE_VALUE` reader - EVTimer Capture Value"] -pub type CaptureValueR = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - EVTimer Capture Value"] - #[inline(always)] - pub fn capture_value(&self) -> CaptureValueR { - CaptureValueR::new((self.bits & 0x03ff) as u16) - } -} -#[doc = "Local Capture High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_h::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CaptureHSpec; -impl crate::RegisterSpec for CaptureHSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`capture_h::R`](R) reader structure"] -impl crate::Readable for CaptureHSpec {} -#[doc = "`reset()` method sets CAPTURE_H to value 0"] -impl crate::Resettable for CaptureHSpec {} diff --git a/mcxa276-pac/src/ostimer0/capture_l.rs b/mcxa276-pac/src/ostimer0/capture_l.rs deleted file mode 100644 index b4e25c3f7..000000000 --- a/mcxa276-pac/src/ostimer0/capture_l.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `CAPTURE_L` reader"] -pub type R = crate::R; -#[doc = "Field `CAPTURE_VALUE` reader - EVTimer Capture Value"] -pub type CaptureValueR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - EVTimer Capture Value"] - #[inline(always)] - pub fn capture_value(&self) -> CaptureValueR { - CaptureValueR::new(self.bits) - } -} -#[doc = "Local Capture Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`capture_l::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CaptureLSpec; -impl crate::RegisterSpec for CaptureLSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`capture_l::R`](R) reader structure"] -impl crate::Readable for CaptureLSpec {} -#[doc = "`reset()` method sets CAPTURE_L to value 0"] -impl crate::Resettable for CaptureLSpec {} diff --git a/mcxa276-pac/src/ostimer0/evtimerh.rs b/mcxa276-pac/src/ostimer0/evtimerh.rs deleted file mode 100644 index f7afa192b..000000000 --- a/mcxa276-pac/src/ostimer0/evtimerh.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `EVTIMERH` reader"] -pub type R = crate::R; -#[doc = "Field `EVTIMER_COUNT_VALUE` reader - EVTimer Count Value"] -pub type EvtimerCountValueR = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - EVTimer Count Value"] - #[inline(always)] - pub fn evtimer_count_value(&self) -> EvtimerCountValueR { - EvtimerCountValueR::new((self.bits & 0x03ff) as u16) - } -} -#[doc = "EVTIMER High\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EvtimerhSpec; -impl crate::RegisterSpec for EvtimerhSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`evtimerh::R`](R) reader structure"] -impl crate::Readable for EvtimerhSpec {} -#[doc = "`reset()` method sets EVTIMERH to value 0"] -impl crate::Resettable for EvtimerhSpec {} diff --git a/mcxa276-pac/src/ostimer0/evtimerl.rs b/mcxa276-pac/src/ostimer0/evtimerl.rs deleted file mode 100644 index 99e561df9..000000000 --- a/mcxa276-pac/src/ostimer0/evtimerl.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `EVTIMERL` reader"] -pub type R = crate::R; -#[doc = "Field `EVTIMER_COUNT_VALUE` reader - EVTimer Count Value"] -pub type EvtimerCountValueR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - EVTimer Count Value"] - #[inline(always)] - pub fn evtimer_count_value(&self) -> EvtimerCountValueR { - EvtimerCountValueR::new(self.bits) - } -} -#[doc = "EVTIMER Low\n\nYou can [`read`](crate::Reg::read) this register and get [`evtimerl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EvtimerlSpec; -impl crate::RegisterSpec for EvtimerlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`evtimerl::R`](R) reader structure"] -impl crate::Readable for EvtimerlSpec {} -#[doc = "`reset()` method sets EVTIMERL to value 0"] -impl crate::Resettable for EvtimerlSpec {} diff --git a/mcxa276-pac/src/ostimer0/match_h.rs b/mcxa276-pac/src/ostimer0/match_h.rs deleted file mode 100644 index 324335a30..000000000 --- a/mcxa276-pac/src/ostimer0/match_h.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `MATCH_H` reader"] -pub type R = crate::R; -#[doc = "Register `MATCH_H` writer"] -pub type W = crate::W; -#[doc = "Field `MATCH_VALUE` reader - EVTimer Match Value"] -pub type MatchValueR = crate::FieldReader; -#[doc = "Field `MATCH_VALUE` writer - EVTimer Match Value"] -pub type MatchValueW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:9 - EVTimer Match Value"] - #[inline(always)] - pub fn match_value(&self) -> MatchValueR { - MatchValueR::new((self.bits & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:9 - EVTimer Match Value"] - #[inline(always)] - pub fn match_value(&mut self) -> MatchValueW { - MatchValueW::new(self, 0) - } -} -#[doc = "Local Match High for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MatchHSpec; -impl crate::RegisterSpec for MatchHSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`match_h::R`](R) reader structure"] -impl crate::Readable for MatchHSpec {} -#[doc = "`write(|w| ..)` method takes [`match_h::W`](W) writer structure"] -impl crate::Writable for MatchHSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MATCH_H to value 0xffff_ffff"] -impl crate::Resettable for MatchHSpec { - const RESET_VALUE: u32 = 0xffff_ffff; -} diff --git a/mcxa276-pac/src/ostimer0/match_l.rs b/mcxa276-pac/src/ostimer0/match_l.rs deleted file mode 100644 index b4f5ddd0a..000000000 --- a/mcxa276-pac/src/ostimer0/match_l.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `MATCH_L` reader"] -pub type R = crate::R; -#[doc = "Register `MATCH_L` writer"] -pub type W = crate::W; -#[doc = "Field `MATCH_VALUE` reader - EVTimer Match Value"] -pub type MatchValueR = crate::FieldReader; -#[doc = "Field `MATCH_VALUE` writer - EVTimer Match Value"] -pub type MatchValueW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - EVTimer Match Value"] - #[inline(always)] - pub fn match_value(&self) -> MatchValueR { - MatchValueR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - EVTimer Match Value"] - #[inline(always)] - pub fn match_value(&mut self) -> MatchValueW { - MatchValueW::new(self, 0) - } -} -#[doc = "Local Match Low for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`match_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MatchLSpec; -impl crate::RegisterSpec for MatchLSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`match_l::R`](R) reader structure"] -impl crate::Readable for MatchLSpec {} -#[doc = "`write(|w| ..)` method takes [`match_l::W`](W) writer structure"] -impl crate::Writable for MatchLSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MATCH_L to value 0xffff_ffff"] -impl crate::Resettable for MatchLSpec { - const RESET_VALUE: u32 = 0xffff_ffff; -} diff --git a/mcxa276-pac/src/ostimer0/osevent_ctrl.rs b/mcxa276-pac/src/ostimer0/osevent_ctrl.rs deleted file mode 100644 index 79340b633..000000000 --- a/mcxa276-pac/src/ostimer0/osevent_ctrl.rs +++ /dev/null @@ -1,171 +0,0 @@ -#[doc = "Register `OSEVENT_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `OSEVENT_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `OSTIMER_INTRFLAG` reader - Interrupt Flag"] -pub type OstimerIntrflagR = crate::BitReader; -#[doc = "Field `OSTIMER_INTRFLAG` writer - Interrupt Flag"] -pub type OstimerIntrflagW<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Interrupt or Wake-Up Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OstimerIntena { - #[doc = "0: Interrupts blocked"] - InterruptsBlocked = 0, - #[doc = "1: Interrupts enabled"] - InterruptsEnabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OstimerIntena) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSTIMER_INTENA` reader - Interrupt or Wake-Up Request"] -pub type OstimerIntenaR = crate::BitReader; -impl OstimerIntenaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OstimerIntena { - match self.bits { - false => OstimerIntena::InterruptsBlocked, - true => OstimerIntena::InterruptsEnabled, - } - } - #[doc = "Interrupts blocked"] - #[inline(always)] - pub fn is_interrupts_blocked(&self) -> bool { - *self == OstimerIntena::InterruptsBlocked - } - #[doc = "Interrupts enabled"] - #[inline(always)] - pub fn is_interrupts_enabled(&self) -> bool { - *self == OstimerIntena::InterruptsEnabled - } -} -#[doc = "Field `OSTIMER_INTENA` writer - Interrupt or Wake-Up Request"] -pub type OstimerIntenaW<'a, REG> = crate::BitWriter<'a, REG, OstimerIntena>; -impl<'a, REG> OstimerIntenaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupts blocked"] - #[inline(always)] - pub fn interrupts_blocked(self) -> &'a mut crate::W { - self.variant(OstimerIntena::InterruptsBlocked) - } - #[doc = "Interrupts enabled"] - #[inline(always)] - pub fn interrupts_enabled(self) -> &'a mut crate::W { - self.variant(OstimerIntena::InterruptsEnabled) - } -} -#[doc = "Field `MATCH_WR_RDY` reader - EVTimer Match Write Ready"] -pub type MatchWrRdyR = crate::BitReader; -#[doc = "Debug Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DebugEn { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DebugEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DEBUG_EN` reader - Debug Enable"] -pub type DebugEnR = crate::BitReader; -impl DebugEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DebugEn { - match self.bits { - false => DebugEn::Disable, - true => DebugEn::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DebugEn::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DebugEn::Enable - } -} -#[doc = "Field `DEBUG_EN` writer - Debug Enable"] -pub type DebugEnW<'a, REG> = crate::BitWriter<'a, REG, DebugEn>; -impl<'a, REG> DebugEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DebugEn::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DebugEn::Enable) - } -} -impl R { - #[doc = "Bit 0 - Interrupt Flag"] - #[inline(always)] - pub fn ostimer_intrflag(&self) -> OstimerIntrflagR { - OstimerIntrflagR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Interrupt or Wake-Up Request"] - #[inline(always)] - pub fn ostimer_intena(&self) -> OstimerIntenaR { - OstimerIntenaR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - EVTimer Match Write Ready"] - #[inline(always)] - pub fn match_wr_rdy(&self) -> MatchWrRdyR { - MatchWrRdyR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Debug Enable"] - #[inline(always)] - pub fn debug_en(&self) -> DebugEnR { - DebugEnR::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Interrupt Flag"] - #[inline(always)] - pub fn ostimer_intrflag(&mut self) -> OstimerIntrflagW { - OstimerIntrflagW::new(self, 0) - } - #[doc = "Bit 1 - Interrupt or Wake-Up Request"] - #[inline(always)] - pub fn ostimer_intena(&mut self) -> OstimerIntenaW { - OstimerIntenaW::new(self, 1) - } - #[doc = "Bit 3 - Debug Enable"] - #[inline(always)] - pub fn debug_en(&mut self) -> DebugEnW { - DebugEnW::new(self, 3) - } -} -#[doc = "OSTIMER Control for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`osevent_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osevent_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OseventCtrlSpec; -impl crate::RegisterSpec for OseventCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`osevent_ctrl::R`](R) reader structure"] -impl crate::Readable for OseventCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`osevent_ctrl::W`](W) writer structure"] -impl crate::Writable for OseventCtrlSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; -} -#[doc = "`reset()` method sets OSEVENT_CTRL to value 0x08"] -impl crate::Resettable for OseventCtrlSpec { - const RESET_VALUE: u32 = 0x08; -} diff --git a/mcxa276-pac/src/pkc0.rs b/mcxa276-pac/src/pkc0.rs deleted file mode 100644 index b37692ca1..000000000 --- a/mcxa276-pac/src/pkc0.rs +++ /dev/null @@ -1,300 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - pkc_status: PkcStatus, - pkc_ctrl: PkcCtrl, - pkc_cfg: PkcCfg, - _reserved3: [u8; 0x04], - pkc_mode1: PkcMode1, - pkc_xyptr1: PkcXyptr1, - pkc_zrptr1: PkcZrptr1, - pkc_len1: PkcLen1, - pkc_mode2: PkcMode2, - pkc_xyptr2: PkcXyptr2, - pkc_zrptr2: PkcZrptr2, - pkc_len2: PkcLen2, - _reserved11: [u8; 0x10], - pkc_uptr: PkcUptr, - pkc_uptrt: PkcUptrt, - pkc_ulen: PkcUlen, - _reserved14: [u8; 0x04], - pkc_mcdata: PkcMcdata, - _reserved15: [u8; 0x0c], - pkc_version: PkcVersion, - _reserved16: [u8; 0x0f4c], - pkc_soft_rst: PkcSoftRst, - _reserved17: [u8; 0x0c], - pkc_access_err: PkcAccessErr, - pkc_access_err_clr: PkcAccessErrClr, - _reserved19: [u8; 0x10], - pkc_int_clr_enable: PkcIntClrEnable, - pkc_int_set_enable: PkcIntSetEnable, - pkc_int_status: PkcIntStatus, - pkc_int_enable: PkcIntEnable, - pkc_int_clr_status: PkcIntClrStatus, - pkc_int_set_status: PkcIntSetStatus, - _reserved25: [u8; 0x0c], - pkc_module_id: PkcModuleId, -} -impl RegisterBlock { - #[doc = "0x00 - Status Register"] - #[inline(always)] - pub const fn pkc_status(&self) -> &PkcStatus { - &self.pkc_status - } - #[doc = "0x04 - Control Register"] - #[inline(always)] - pub const fn pkc_ctrl(&self) -> &PkcCtrl { - &self.pkc_ctrl - } - #[doc = "0x08 - Configuration register"] - #[inline(always)] - pub const fn pkc_cfg(&self) -> &PkcCfg { - &self.pkc_cfg - } - #[doc = "0x10 - Mode register, parameter set 1"] - #[inline(always)] - pub const fn pkc_mode1(&self) -> &PkcMode1 { - &self.pkc_mode1 - } - #[doc = "0x14 - X+Y pointer register, parameter set 1"] - #[inline(always)] - pub const fn pkc_xyptr1(&self) -> &PkcXyptr1 { - &self.pkc_xyptr1 - } - #[doc = "0x18 - Z+R pointer register, parameter set 1"] - #[inline(always)] - pub const fn pkc_zrptr1(&self) -> &PkcZrptr1 { - &self.pkc_zrptr1 - } - #[doc = "0x1c - Length register, parameter set 1"] - #[inline(always)] - pub const fn pkc_len1(&self) -> &PkcLen1 { - &self.pkc_len1 - } - #[doc = "0x20 - Mode register, parameter set 2"] - #[inline(always)] - pub const fn pkc_mode2(&self) -> &PkcMode2 { - &self.pkc_mode2 - } - #[doc = "0x24 - X+Y pointer register, parameter set 2"] - #[inline(always)] - pub const fn pkc_xyptr2(&self) -> &PkcXyptr2 { - &self.pkc_xyptr2 - } - #[doc = "0x28 - Z+R pointer register, parameter set 2"] - #[inline(always)] - pub const fn pkc_zrptr2(&self) -> &PkcZrptr2 { - &self.pkc_zrptr2 - } - #[doc = "0x2c - Length register, parameter set 2"] - #[inline(always)] - pub const fn pkc_len2(&self) -> &PkcLen2 { - &self.pkc_len2 - } - #[doc = "0x40 - Universal pointer FUP program"] - #[inline(always)] - pub const fn pkc_uptr(&self) -> &PkcUptr { - &self.pkc_uptr - } - #[doc = "0x44 - Universal pointer FUP table"] - #[inline(always)] - pub const fn pkc_uptrt(&self) -> &PkcUptrt { - &self.pkc_uptrt - } - #[doc = "0x48 - Universal pointer length"] - #[inline(always)] - pub const fn pkc_ulen(&self) -> &PkcUlen { - &self.pkc_ulen - } - #[doc = "0x50 - MC pattern data interface"] - #[inline(always)] - pub const fn pkc_mcdata(&self) -> &PkcMcdata { - &self.pkc_mcdata - } - #[doc = "0x60 - PKC version register"] - #[inline(always)] - pub const fn pkc_version(&self) -> &PkcVersion { - &self.pkc_version - } - #[doc = "0xfb0 - Software reset"] - #[inline(always)] - pub const fn pkc_soft_rst(&self) -> &PkcSoftRst { - &self.pkc_soft_rst - } - #[doc = "0xfc0 - Access Error"] - #[inline(always)] - pub const fn pkc_access_err(&self) -> &PkcAccessErr { - &self.pkc_access_err - } - #[doc = "0xfc4 - Clear Access Error"] - #[inline(always)] - pub const fn pkc_access_err_clr(&self) -> &PkcAccessErrClr { - &self.pkc_access_err_clr - } - #[doc = "0xfd8 - Interrupt enable clear"] - #[inline(always)] - pub const fn pkc_int_clr_enable(&self) -> &PkcIntClrEnable { - &self.pkc_int_clr_enable - } - #[doc = "0xfdc - Interrupt enable set"] - #[inline(always)] - pub const fn pkc_int_set_enable(&self) -> &PkcIntSetEnable { - &self.pkc_int_set_enable - } - #[doc = "0xfe0 - Interrupt status"] - #[inline(always)] - pub const fn pkc_int_status(&self) -> &PkcIntStatus { - &self.pkc_int_status - } - #[doc = "0xfe4 - Interrupt enable"] - #[inline(always)] - pub const fn pkc_int_enable(&self) -> &PkcIntEnable { - &self.pkc_int_enable - } - #[doc = "0xfe8 - Interrupt status clear"] - #[inline(always)] - pub const fn pkc_int_clr_status(&self) -> &PkcIntClrStatus { - &self.pkc_int_clr_status - } - #[doc = "0xfec - Interrupt status set"] - #[inline(always)] - pub const fn pkc_int_set_status(&self) -> &PkcIntSetStatus { - &self.pkc_int_set_status - } - #[doc = "0xffc - Module ID"] - #[inline(always)] - pub const fn pkc_module_id(&self) -> &PkcModuleId { - &self.pkc_module_id - } -} -#[doc = "PKC_STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_status`] module"] -#[doc(alias = "PKC_STATUS")] -pub type PkcStatus = crate::Reg; -#[doc = "Status Register"] -pub mod pkc_status; -#[doc = "PKC_CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_ctrl`] module"] -#[doc(alias = "PKC_CTRL")] -pub type PkcCtrl = crate::Reg; -#[doc = "Control Register"] -pub mod pkc_ctrl; -#[doc = "PKC_CFG (rw) register accessor: Configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_cfg`] module"] -#[doc(alias = "PKC_CFG")] -pub type PkcCfg = crate::Reg; -#[doc = "Configuration register"] -pub mod pkc_cfg; -#[doc = "PKC_MODE1 (rw) register accessor: Mode register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_mode1`] module"] -#[doc(alias = "PKC_MODE1")] -pub type PkcMode1 = crate::Reg; -#[doc = "Mode register, parameter set 1"] -pub mod pkc_mode1; -#[doc = "PKC_XYPTR1 (rw) register accessor: X+Y pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_xyptr1`] module"] -#[doc(alias = "PKC_XYPTR1")] -pub type PkcXyptr1 = crate::Reg; -#[doc = "X+Y pointer register, parameter set 1"] -pub mod pkc_xyptr1; -#[doc = "PKC_ZRPTR1 (rw) register accessor: Z+R pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_zrptr1`] module"] -#[doc(alias = "PKC_ZRPTR1")] -pub type PkcZrptr1 = crate::Reg; -#[doc = "Z+R pointer register, parameter set 1"] -pub mod pkc_zrptr1; -#[doc = "PKC_LEN1 (rw) register accessor: Length register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_len1`] module"] -#[doc(alias = "PKC_LEN1")] -pub type PkcLen1 = crate::Reg; -#[doc = "Length register, parameter set 1"] -pub mod pkc_len1; -#[doc = "PKC_MODE2 (rw) register accessor: Mode register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_mode2`] module"] -#[doc(alias = "PKC_MODE2")] -pub type PkcMode2 = crate::Reg; -#[doc = "Mode register, parameter set 2"] -pub mod pkc_mode2; -#[doc = "PKC_XYPTR2 (rw) register accessor: X+Y pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_xyptr2`] module"] -#[doc(alias = "PKC_XYPTR2")] -pub type PkcXyptr2 = crate::Reg; -#[doc = "X+Y pointer register, parameter set 2"] -pub mod pkc_xyptr2; -#[doc = "PKC_ZRPTR2 (rw) register accessor: Z+R pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_zrptr2`] module"] -#[doc(alias = "PKC_ZRPTR2")] -pub type PkcZrptr2 = crate::Reg; -#[doc = "Z+R pointer register, parameter set 2"] -pub mod pkc_zrptr2; -#[doc = "PKC_LEN2 (rw) register accessor: Length register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_len2`] module"] -#[doc(alias = "PKC_LEN2")] -pub type PkcLen2 = crate::Reg; -#[doc = "Length register, parameter set 2"] -pub mod pkc_len2; -#[doc = "PKC_UPTR (rw) register accessor: Universal pointer FUP program\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_uptr`] module"] -#[doc(alias = "PKC_UPTR")] -pub type PkcUptr = crate::Reg; -#[doc = "Universal pointer FUP program"] -pub mod pkc_uptr; -#[doc = "PKC_UPTRT (rw) register accessor: Universal pointer FUP table\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptrt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptrt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_uptrt`] module"] -#[doc(alias = "PKC_UPTRT")] -pub type PkcUptrt = crate::Reg; -#[doc = "Universal pointer FUP table"] -pub mod pkc_uptrt; -#[doc = "PKC_ULEN (rw) register accessor: Universal pointer length\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ulen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ulen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_ulen`] module"] -#[doc(alias = "PKC_ULEN")] -pub type PkcUlen = crate::Reg; -#[doc = "Universal pointer length"] -pub mod pkc_ulen; -#[doc = "PKC_MCDATA (rw) register accessor: MC pattern data interface\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mcdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mcdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_mcdata`] module"] -#[doc(alias = "PKC_MCDATA")] -pub type PkcMcdata = crate::Reg; -#[doc = "MC pattern data interface"] -pub mod pkc_mcdata; -#[doc = "PKC_VERSION (r) register accessor: PKC version register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_version`] module"] -#[doc(alias = "PKC_VERSION")] -pub type PkcVersion = crate::Reg; -#[doc = "PKC version register"] -pub mod pkc_version; -#[doc = "PKC_SOFT_RST (w) register accessor: Software reset\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_soft_rst::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_soft_rst`] module"] -#[doc(alias = "PKC_SOFT_RST")] -pub type PkcSoftRst = crate::Reg; -#[doc = "Software reset"] -pub mod pkc_soft_rst; -#[doc = "PKC_ACCESS_ERR (r) register accessor: Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_access_err::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_access_err`] module"] -#[doc(alias = "PKC_ACCESS_ERR")] -pub type PkcAccessErr = crate::Reg; -#[doc = "Access Error"] -pub mod pkc_access_err; -#[doc = "PKC_ACCESS_ERR_CLR (w) register accessor: Clear Access Error\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_access_err_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_access_err_clr`] module"] -#[doc(alias = "PKC_ACCESS_ERR_CLR")] -pub type PkcAccessErrClr = crate::Reg; -#[doc = "Clear Access Error"] -pub mod pkc_access_err_clr; -#[doc = "PKC_INT_CLR_ENABLE (w) register accessor: Interrupt enable clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_enable::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_clr_enable`] module"] -#[doc(alias = "PKC_INT_CLR_ENABLE")] -pub type PkcIntClrEnable = crate::Reg; -#[doc = "Interrupt enable clear"] -pub mod pkc_int_clr_enable; -#[doc = "PKC_INT_SET_ENABLE (w) register accessor: Interrupt enable set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_enable::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_set_enable`] module"] -#[doc(alias = "PKC_INT_SET_ENABLE")] -pub type PkcIntSetEnable = crate::Reg; -#[doc = "Interrupt enable set"] -pub mod pkc_int_set_enable; -#[doc = "PKC_INT_STATUS (r) register accessor: Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_status`] module"] -#[doc(alias = "PKC_INT_STATUS")] -pub type PkcIntStatus = crate::Reg; -#[doc = "Interrupt status"] -pub mod pkc_int_status; -#[doc = "PKC_INT_ENABLE (r) register accessor: Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_enable::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_enable`] module"] -#[doc(alias = "PKC_INT_ENABLE")] -pub type PkcIntEnable = crate::Reg; -#[doc = "Interrupt enable"] -pub mod pkc_int_enable; -#[doc = "PKC_INT_CLR_STATUS (w) register accessor: Interrupt status clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_status::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_clr_status`] module"] -#[doc(alias = "PKC_INT_CLR_STATUS")] -pub type PkcIntClrStatus = crate::Reg; -#[doc = "Interrupt status clear"] -pub mod pkc_int_clr_status; -#[doc = "PKC_INT_SET_STATUS (w) register accessor: Interrupt status set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_status::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_int_set_status`] module"] -#[doc(alias = "PKC_INT_SET_STATUS")] -pub type PkcIntSetStatus = crate::Reg; -#[doc = "Interrupt status set"] -pub mod pkc_int_set_status; -#[doc = "PKC_MODULE_ID (r) register accessor: Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_module_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkc_module_id`] module"] -#[doc(alias = "PKC_MODULE_ID")] -pub type PkcModuleId = crate::Reg; -#[doc = "Module ID"] -pub mod pkc_module_id; diff --git a/mcxa276-pac/src/pkc0/pkc_access_err.rs b/mcxa276-pac/src/pkc0/pkc_access_err.rs deleted file mode 100644 index 7fe9538a9..000000000 --- a/mcxa276-pac/src/pkc0/pkc_access_err.rs +++ /dev/null @@ -1,69 +0,0 @@ -#[doc = "Register `PKC_ACCESS_ERR` reader"] -pub type R = crate::R; -#[doc = "Field `APB_NOTAV` reader - APB Error"] -pub type ApbNotavR = crate::BitReader; -#[doc = "Field `APB_WRGMD` reader - APB Error"] -pub type ApbWrgmdR = crate::BitReader; -#[doc = "Field `APB_MASTER` reader - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV)"] -pub type ApbMasterR = crate::FieldReader; -#[doc = "Field `AHB` reader - AHB Error"] -pub type AhbR = crate::BitReader; -#[doc = "Field `PKCC` reader - Error in PKC coprocessor kernel"] -pub type PkccR = crate::BitReader; -#[doc = "Field `FDET` reader - Error due to error detection circuitry"] -pub type FdetR = crate::BitReader; -#[doc = "Field `CTRL` reader - Error in PKC software control"] -pub type CtrlR = crate::BitReader; -#[doc = "Field `UCRC` reader - Error in layer2 CRC check."] -pub type UcrcR = crate::BitReader; -impl R { - #[doc = "Bit 0 - APB Error"] - #[inline(always)] - pub fn apb_notav(&self) -> ApbNotavR { - ApbNotavR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - APB Error"] - #[inline(always)] - pub fn apb_wrgmd(&self) -> ApbWrgmdR { - ApbWrgmdR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 4:7 - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV)"] - #[inline(always)] - pub fn apb_master(&self) -> ApbMasterR { - ApbMasterR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bit 10 - AHB Error"] - #[inline(always)] - pub fn ahb(&self) -> AhbR { - AhbR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 16 - Error in PKC coprocessor kernel"] - #[inline(always)] - pub fn pkcc(&self) -> PkccR { - PkccR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Error due to error detection circuitry"] - #[inline(always)] - pub fn fdet(&self) -> FdetR { - FdetR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Error in PKC software control"] - #[inline(always)] - pub fn ctrl(&self) -> CtrlR { - CtrlR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Error in layer2 CRC check."] - #[inline(always)] - pub fn ucrc(&self) -> UcrcR { - UcrcR::new(((self.bits >> 19) & 1) != 0) - } -} -#[doc = "Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_access_err::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcAccessErrSpec; -impl crate::RegisterSpec for PkcAccessErrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_access_err::R`](R) reader structure"] -impl crate::Readable for PkcAccessErrSpec {} -#[doc = "`reset()` method sets PKC_ACCESS_ERR to value 0"] -impl crate::Resettable for PkcAccessErrSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_access_err_clr.rs b/mcxa276-pac/src/pkc0/pkc_access_err_clr.rs deleted file mode 100644 index f0bc34a5b..000000000 --- a/mcxa276-pac/src/pkc0/pkc_access_err_clr.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PKC_ACCESS_ERR_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `ERR_CLR` writer - Write 1 to reset PKC_ACCESS_ERR SFR."] -pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>; -impl W { - #[doc = "Bit 0 - Write 1 to reset PKC_ACCESS_ERR SFR."] - #[inline(always)] - pub fn err_clr(&mut self) -> ErrClrW { - ErrClrW::new(self, 0) - } -} -#[doc = "Clear Access Error\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_access_err_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcAccessErrClrSpec; -impl crate::RegisterSpec for PkcAccessErrClrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`pkc_access_err_clr::W`](W) writer structure"] -impl crate::Writable for PkcAccessErrClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_ACCESS_ERR_CLR to value 0"] -impl crate::Resettable for PkcAccessErrClrSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_cfg.rs b/mcxa276-pac/src/pkc0/pkc_cfg.rs deleted file mode 100644 index 0def608fc..000000000 --- a/mcxa276-pac/src/pkc0/pkc_cfg.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `PKC_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_CFG` writer"] -pub type W = crate::W; -#[doc = "Field `IDLEOP` reader - Idle operation feature not available in this version (flag is don't care)."] -pub type IdleopR = crate::BitReader; -#[doc = "Field `IDLEOP` writer - Idle operation feature not available in this version (flag is don't care)."] -pub type IdleopW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RFU1` reader - RFU"] -pub type Rfu1R = crate::BitReader; -#[doc = "Field `RFU1` writer - RFU"] -pub type Rfu1W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RFU2` reader - RFU"] -pub type Rfu2R = crate::BitReader; -#[doc = "Field `RFU2` writer - RFU"] -pub type Rfu2W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CLKRND` reader - Clock randomization feature not available in this version (flag is don't care)."] -pub type ClkrndR = crate::BitReader; -#[doc = "Field `CLKRND` writer - Clock randomization feature not available in this version (flag is don't care)."] -pub type ClkrndW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `REDMULNOISE` reader - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] -pub type RedmulnoiseR = crate::BitReader; -#[doc = "Field `REDMULNOISE` writer - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] -pub type RedmulnoiseW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RNDDLY` reader - Random delay feature not available in this version (flag is don't care)."] -pub type RnddlyR = crate::FieldReader; -#[doc = "Field `RNDDLY` writer - Random delay feature not available in this version (flag is don't care)."] -pub type RnddlyW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `SBXNOISE` reader - Noise feature not available in this version (flag is don't care)."] -pub type SbxnoiseR = crate::BitReader; -#[doc = "Field `SBXNOISE` writer - Noise feature not available in this version (flag is don't care)."] -pub type SbxnoiseW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ALPNOISE` reader - Noise feature not available in this version (flag is don't care)."] -pub type AlpnoiseR = crate::BitReader; -#[doc = "Field `ALPNOISE` writer - Noise feature not available in this version (flag is don't care)."] -pub type AlpnoiseW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FMULNOISE` reader - Noise feature not available in this version (flag is don't care)."] -pub type FmulnoiseR = crate::BitReader; -#[doc = "Field `FMULNOISE` writer - Noise feature not available in this version (flag is don't care)."] -pub type FmulnoiseW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Idle operation feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn idleop(&self) -> IdleopR { - IdleopR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - RFU"] - #[inline(always)] - pub fn rfu1(&self) -> Rfu1R { - Rfu1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - RFU"] - #[inline(always)] - pub fn rfu2(&self) -> Rfu2R { - Rfu2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Clock randomization feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn clkrnd(&self) -> ClkrndR { - ClkrndR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn redmulnoise(&self) -> RedmulnoiseR { - RedmulnoiseR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 5:7 - Random delay feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn rnddly(&self) -> RnddlyR { - RnddlyR::new(((self.bits >> 5) & 7) as u8) - } - #[doc = "Bit 8 - Noise feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn sbxnoise(&self) -> SbxnoiseR { - SbxnoiseR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Noise feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn alpnoise(&self) -> AlpnoiseR { - AlpnoiseR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Noise feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn fmulnoise(&self) -> FmulnoiseR { - FmulnoiseR::new(((self.bits >> 10) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Idle operation feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn idleop(&mut self) -> IdleopW { - IdleopW::new(self, 0) - } - #[doc = "Bit 1 - RFU"] - #[inline(always)] - pub fn rfu1(&mut self) -> Rfu1W { - Rfu1W::new(self, 1) - } - #[doc = "Bit 2 - RFU"] - #[inline(always)] - pub fn rfu2(&mut self) -> Rfu2W { - Rfu2W::new(self, 2) - } - #[doc = "Bit 3 - Clock randomization feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn clkrnd(&mut self) -> ClkrndW { - ClkrndW::new(self, 3) - } - #[doc = "Bit 4 - Noise in reduced multiplier mode feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn redmulnoise(&mut self) -> RedmulnoiseW { - RedmulnoiseW::new(self, 4) - } - #[doc = "Bits 5:7 - Random delay feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn rnddly(&mut self) -> RnddlyW { - RnddlyW::new(self, 5) - } - #[doc = "Bit 8 - Noise feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn sbxnoise(&mut self) -> SbxnoiseW { - SbxnoiseW::new(self, 8) - } - #[doc = "Bit 9 - Noise feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn alpnoise(&mut self) -> AlpnoiseW { - AlpnoiseW::new(self, 9) - } - #[doc = "Bit 10 - Noise feature not available in this version (flag is don't care)."] - #[inline(always)] - pub fn fmulnoise(&mut self) -> FmulnoiseW { - FmulnoiseW::new(self, 10) - } -} -#[doc = "Configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcCfgSpec; -impl crate::RegisterSpec for PkcCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_cfg::R`](R) reader structure"] -impl crate::Readable for PkcCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`pkc_cfg::W`](W) writer structure"] -impl crate::Writable for PkcCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_CFG to value 0x0719"] -impl crate::Resettable for PkcCfgSpec { - const RESET_VALUE: u32 = 0x0719; -} diff --git a/mcxa276-pac/src/pkc0/pkc_ctrl.rs b/mcxa276-pac/src/pkc0/pkc_ctrl.rs deleted file mode 100644 index 7b0296d70..000000000 --- a/mcxa276-pac/src/pkc0/pkc_ctrl.rs +++ /dev/null @@ -1,191 +0,0 @@ -#[doc = "Register `PKC_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `RESET` reader - PKC reset control bit"] -pub type ResetR = crate::BitReader; -#[doc = "Field `RESET` writer - PKC reset control bit"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `STOP` reader - Freeze PKC calculation"] -pub type StopR = crate::BitReader; -#[doc = "Field `STOP` writer - Freeze PKC calculation"] -pub type StopW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GOD1` writer - Control bit to start direct operation using parameter set 1"] -pub type God1W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GOD2` writer - Control bit to start direct operation using parameter set 2"] -pub type God2W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GOM1` writer - Control bit to start MC pattern using parameter set 1"] -pub type Gom1W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GOM2` writer - Control bit to start MC pattern using parameter set 2"] -pub type Gom2W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GOU` writer - Control bit to start pipe operation"] -pub type GouW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GF2CONV` reader - Convert to GF2 calculation modes"] -pub type Gf2convR = crate::BitReader; -#[doc = "Field `GF2CONV` writer - Convert to GF2 calculation modes"] -pub type Gf2convW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CLRCACHE` writer - Clear universal pointer cache"] -pub type ClrcacheW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CACHE_EN` reader - Enable universal pointer cache"] -pub type CacheEnR = crate::BitReader; -#[doc = "Field `CACHE_EN` writer - Enable universal pointer cache"] -pub type CacheEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Reduced multiplier mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Redmul { - #[doc = "0: full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] - Fullsz = 0, - #[doc = "2: 64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] - Value64bit = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Redmul) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Redmul { - type Ux = u8; -} -impl crate::IsEnum for Redmul {} -#[doc = "Field `REDMUL` reader - Reduced multiplier mode"] -pub type RedmulR = crate::FieldReader; -impl RedmulR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Redmul::Fullsz), - 2 => Some(Redmul::Value64bit), - _ => None, - } - } - #[doc = "full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] - #[inline(always)] - pub fn is_fullsz(&self) -> bool { - *self == Redmul::Fullsz - } - #[doc = "64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] - #[inline(always)] - pub fn is_value_64bit(&self) -> bool { - *self == Redmul::Value64bit - } -} -#[doc = "Field `REDMUL` writer - Reduced multiplier mode"] -pub type RedmulW<'a, REG> = crate::FieldWriter<'a, REG, 2, Redmul>; -impl<'a, REG> RedmulW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] - #[inline(always)] - pub fn fullsz(self) -> &'a mut crate::W { - self.variant(Redmul::Fullsz) - } - #[doc = "64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008"] - #[inline(always)] - pub fn value_64bit(self) -> &'a mut crate::W { - self.variant(Redmul::Value64bit) - } -} -impl R { - #[doc = "Bit 0 - PKC reset control bit"] - #[inline(always)] - pub fn reset(&self) -> ResetR { - ResetR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Freeze PKC calculation"] - #[inline(always)] - pub fn stop(&self) -> StopR { - StopR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 7 - Convert to GF2 calculation modes"] - #[inline(always)] - pub fn gf2conv(&self) -> Gf2convR { - Gf2convR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 9 - Enable universal pointer cache"] - #[inline(always)] - pub fn cache_en(&self) -> CacheEnR { - CacheEnR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 10:11 - Reduced multiplier mode"] - #[inline(always)] - pub fn redmul(&self) -> RedmulR { - RedmulR::new(((self.bits >> 10) & 3) as u8) - } -} -impl W { - #[doc = "Bit 0 - PKC reset control bit"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 0) - } - #[doc = "Bit 1 - Freeze PKC calculation"] - #[inline(always)] - pub fn stop(&mut self) -> StopW { - StopW::new(self, 1) - } - #[doc = "Bit 2 - Control bit to start direct operation using parameter set 1"] - #[inline(always)] - pub fn god1(&mut self) -> God1W { - God1W::new(self, 2) - } - #[doc = "Bit 3 - Control bit to start direct operation using parameter set 2"] - #[inline(always)] - pub fn god2(&mut self) -> God2W { - God2W::new(self, 3) - } - #[doc = "Bit 4 - Control bit to start MC pattern using parameter set 1"] - #[inline(always)] - pub fn gom1(&mut self) -> Gom1W { - Gom1W::new(self, 4) - } - #[doc = "Bit 5 - Control bit to start MC pattern using parameter set 2"] - #[inline(always)] - pub fn gom2(&mut self) -> Gom2W { - Gom2W::new(self, 5) - } - #[doc = "Bit 6 - Control bit to start pipe operation"] - #[inline(always)] - pub fn gou(&mut self) -> GouW { - GouW::new(self, 6) - } - #[doc = "Bit 7 - Convert to GF2 calculation modes"] - #[inline(always)] - pub fn gf2conv(&mut self) -> Gf2convW { - Gf2convW::new(self, 7) - } - #[doc = "Bit 8 - Clear universal pointer cache"] - #[inline(always)] - pub fn clrcache(&mut self) -> ClrcacheW { - ClrcacheW::new(self, 8) - } - #[doc = "Bit 9 - Enable universal pointer cache"] - #[inline(always)] - pub fn cache_en(&mut self) -> CacheEnW { - CacheEnW::new(self, 9) - } - #[doc = "Bits 10:11 - Reduced multiplier mode"] - #[inline(always)] - pub fn redmul(&mut self) -> RedmulW { - RedmulW::new(self, 10) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcCtrlSpec; -impl crate::RegisterSpec for PkcCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_ctrl::R`](R) reader structure"] -impl crate::Readable for PkcCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`pkc_ctrl::W`](W) writer structure"] -impl crate::Writable for PkcCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_CTRL to value 0x01"] -impl crate::Resettable for PkcCtrlSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs b/mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs deleted file mode 100644 index 0e0b45ed8..000000000 --- a/mcxa276-pac/src/pkc0/pkc_int_clr_enable.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PKC_INT_CLR_ENABLE` writer"] -pub type W = crate::W; -#[doc = "Field `EN_PDONE` writer - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=0)."] -pub type EnPdoneW<'a, REG> = crate::BitWriter<'a, REG>; -impl W { - #[doc = "Bit 0 - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=0)."] - #[inline(always)] - pub fn en_pdone(&mut self) -> EnPdoneW { - EnPdoneW::new(self, 0) - } -} -#[doc = "Interrupt enable clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_enable::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcIntClrEnableSpec; -impl crate::RegisterSpec for PkcIntClrEnableSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`pkc_int_clr_enable::W`](W) writer structure"] -impl crate::Writable for PkcIntClrEnableSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_INT_CLR_ENABLE to value 0"] -impl crate::Resettable for PkcIntClrEnableSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_clr_status.rs b/mcxa276-pac/src/pkc0/pkc_int_clr_status.rs deleted file mode 100644 index 16f6f47e5..000000000 --- a/mcxa276-pac/src/pkc0/pkc_int_clr_status.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PKC_INT_CLR_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `INT_PDONE` writer - Write to clear End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=0)."] -pub type IntPdoneW<'a, REG> = crate::BitWriter<'a, REG>; -impl W { - #[doc = "Bit 0 - Write to clear End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=0)."] - #[inline(always)] - pub fn int_pdone(&mut self) -> IntPdoneW { - IntPdoneW::new(self, 0) - } -} -#[doc = "Interrupt status clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_clr_status::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcIntClrStatusSpec; -impl crate::RegisterSpec for PkcIntClrStatusSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`pkc_int_clr_status::W`](W) writer structure"] -impl crate::Writable for PkcIntClrStatusSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_INT_CLR_STATUS to value 0"] -impl crate::Resettable for PkcIntClrStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_enable.rs b/mcxa276-pac/src/pkc0/pkc_int_enable.rs deleted file mode 100644 index 971736c5d..000000000 --- a/mcxa276-pac/src/pkc0/pkc_int_enable.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `PKC_INT_ENABLE` reader"] -pub type R = crate::R; -#[doc = "Field `EN_PDONE` reader - PDONE interrupt enable flag"] -pub type EnPdoneR = crate::BitReader; -impl R { - #[doc = "Bit 0 - PDONE interrupt enable flag"] - #[inline(always)] - pub fn en_pdone(&self) -> EnPdoneR { - EnPdoneR::new((self.bits & 1) != 0) - } -} -#[doc = "Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_enable::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcIntEnableSpec; -impl crate::RegisterSpec for PkcIntEnableSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_int_enable::R`](R) reader structure"] -impl crate::Readable for PkcIntEnableSpec {} -#[doc = "`reset()` method sets PKC_INT_ENABLE to value 0"] -impl crate::Resettable for PkcIntEnableSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_set_enable.rs b/mcxa276-pac/src/pkc0/pkc_int_set_enable.rs deleted file mode 100644 index f054c87e5..000000000 --- a/mcxa276-pac/src/pkc0/pkc_int_set_enable.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PKC_INT_SET_ENABLE` writer"] -pub type W = crate::W; -#[doc = "Field `EN_PDONE` writer - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=1)."] -pub type EnPdoneW<'a, REG> = crate::BitWriter<'a, REG>; -impl W { - #[doc = "Bit 0 - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE\\[EN_PDONE\\]=1)."] - #[inline(always)] - pub fn en_pdone(&mut self) -> EnPdoneW { - EnPdoneW::new(self, 0) - } -} -#[doc = "Interrupt enable set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_enable::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcIntSetEnableSpec; -impl crate::RegisterSpec for PkcIntSetEnableSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`pkc_int_set_enable::W`](W) writer structure"] -impl crate::Writable for PkcIntSetEnableSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_INT_SET_ENABLE to value 0"] -impl crate::Resettable for PkcIntSetEnableSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_set_status.rs b/mcxa276-pac/src/pkc0/pkc_int_set_status.rs deleted file mode 100644 index 2f903f6d1..000000000 --- a/mcxa276-pac/src/pkc0/pkc_int_set_status.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PKC_INT_SET_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `INT_PDONE` writer - Write to set End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=1) to trigger a PKC interrupt via software, e"] -pub type IntPdoneW<'a, REG> = crate::BitWriter<'a, REG>; -impl W { - #[doc = "Bit 0 - Write to set End-of-computation status flag (PKC_INT_STATUS\\[INT_PDONE\\]=1) to trigger a PKC interrupt via software, e"] - #[inline(always)] - pub fn int_pdone(&mut self) -> IntPdoneW { - IntPdoneW::new(self, 0) - } -} -#[doc = "Interrupt status set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_int_set_status::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcIntSetStatusSpec; -impl crate::RegisterSpec for PkcIntSetStatusSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`pkc_int_set_status::W`](W) writer structure"] -impl crate::Writable for PkcIntSetStatusSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_INT_SET_STATUS to value 0"] -impl crate::Resettable for PkcIntSetStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_int_status.rs b/mcxa276-pac/src/pkc0/pkc_int_status.rs deleted file mode 100644 index 0eb5b21f9..000000000 --- a/mcxa276-pac/src/pkc0/pkc_int_status.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `PKC_INT_STATUS` reader"] -pub type R = crate::R; -#[doc = "Field `INT_PDONE` reader - End-of-computation status flag"] -pub type IntPdoneR = crate::BitReader; -impl R { - #[doc = "Bit 0 - End-of-computation status flag"] - #[inline(always)] - pub fn int_pdone(&self) -> IntPdoneR { - IntPdoneR::new((self.bits & 1) != 0) - } -} -#[doc = "Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcIntStatusSpec; -impl crate::RegisterSpec for PkcIntStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_int_status::R`](R) reader structure"] -impl crate::Readable for PkcIntStatusSpec {} -#[doc = "`reset()` method sets PKC_INT_STATUS to value 0"] -impl crate::Resettable for PkcIntStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_len1.rs b/mcxa276-pac/src/pkc0/pkc_len1.rs deleted file mode 100644 index bcb2a6553..000000000 --- a/mcxa276-pac/src/pkc0/pkc_len1.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `PKC_LEN1` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_LEN1` writer"] -pub type W = crate::W; -#[doc = "Field `LEN` reader - Operand length"] -pub type LenR = crate::FieldReader; -#[doc = "Field `LEN` writer - Operand length"] -pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `MCLEN` reader - Loop counter for microcode pattern"] -pub type MclenR = crate::FieldReader; -#[doc = "Field `MCLEN` writer - Loop counter for microcode pattern"] -pub type MclenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Operand length"] - #[inline(always)] - pub fn len(&self) -> LenR { - LenR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Loop counter for microcode pattern"] - #[inline(always)] - pub fn mclen(&self) -> MclenR { - MclenR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Operand length"] - #[inline(always)] - pub fn len(&mut self) -> LenW { - LenW::new(self, 0) - } - #[doc = "Bits 16:31 - Loop counter for microcode pattern"] - #[inline(always)] - pub fn mclen(&mut self) -> MclenW { - MclenW::new(self, 16) - } -} -#[doc = "Length register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcLen1Spec; -impl crate::RegisterSpec for PkcLen1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_len1::R`](R) reader structure"] -impl crate::Readable for PkcLen1Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_len1::W`](W) writer structure"] -impl crate::Writable for PkcLen1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_LEN1 to value 0"] -impl crate::Resettable for PkcLen1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_len2.rs b/mcxa276-pac/src/pkc0/pkc_len2.rs deleted file mode 100644 index 7c6585d9a..000000000 --- a/mcxa276-pac/src/pkc0/pkc_len2.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `PKC_LEN2` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_LEN2` writer"] -pub type W = crate::W; -#[doc = "Field `LEN` reader - Operand length"] -pub type LenR = crate::FieldReader; -#[doc = "Field `LEN` writer - Operand length"] -pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `MCLEN` reader - Loop counter for microcode pattern"] -pub type MclenR = crate::FieldReader; -#[doc = "Field `MCLEN` writer - Loop counter for microcode pattern"] -pub type MclenW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Operand length"] - #[inline(always)] - pub fn len(&self) -> LenR { - LenR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Loop counter for microcode pattern"] - #[inline(always)] - pub fn mclen(&self) -> MclenR { - MclenR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Operand length"] - #[inline(always)] - pub fn len(&mut self) -> LenW { - LenW::new(self, 0) - } - #[doc = "Bits 16:31 - Loop counter for microcode pattern"] - #[inline(always)] - pub fn mclen(&mut self) -> MclenW { - MclenW::new(self, 16) - } -} -#[doc = "Length register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_len2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_len2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcLen2Spec; -impl crate::RegisterSpec for PkcLen2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_len2::R`](R) reader structure"] -impl crate::Readable for PkcLen2Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_len2::W`](W) writer structure"] -impl crate::Writable for PkcLen2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_LEN2 to value 0"] -impl crate::Resettable for PkcLen2Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_mcdata.rs b/mcxa276-pac/src/pkc0/pkc_mcdata.rs deleted file mode 100644 index e1816eaec..000000000 --- a/mcxa276-pac/src/pkc0/pkc_mcdata.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PKC_MCDATA` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_MCDATA` writer"] -pub type W = crate::W; -#[doc = "Field `MCDATA` reader - Microcode read/write data"] -pub type McdataR = crate::FieldReader; -#[doc = "Field `MCDATA` writer - Microcode read/write data"] -pub type McdataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Microcode read/write data"] - #[inline(always)] - pub fn mcdata(&self) -> McdataR { - McdataR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Microcode read/write data"] - #[inline(always)] - pub fn mcdata(&mut self) -> McdataW { - McdataW::new(self, 0) - } -} -#[doc = "MC pattern data interface\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mcdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mcdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcMcdataSpec; -impl crate::RegisterSpec for PkcMcdataSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_mcdata::R`](R) reader structure"] -impl crate::Readable for PkcMcdataSpec {} -#[doc = "`write(|w| ..)` method takes [`pkc_mcdata::W`](W) writer structure"] -impl crate::Writable for PkcMcdataSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_MCDATA to value 0"] -impl crate::Resettable for PkcMcdataSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_mode1.rs b/mcxa276-pac/src/pkc0/pkc_mode1.rs deleted file mode 100644 index 733b239a8..000000000 --- a/mcxa276-pac/src/pkc0/pkc_mode1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PKC_MODE1` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_MODE1` writer"] -pub type W = crate::W; -#[doc = "Field `MODE` reader - Calculation Mode / MC Start address"] -pub type ModeR = crate::FieldReader; -#[doc = "Field `MODE` writer - Calculation Mode / MC Start address"] -pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new((self.bits & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 0) - } -} -#[doc = "Mode register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcMode1Spec; -impl crate::RegisterSpec for PkcMode1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_mode1::R`](R) reader structure"] -impl crate::Readable for PkcMode1Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_mode1::W`](W) writer structure"] -impl crate::Writable for PkcMode1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_MODE1 to value 0"] -impl crate::Resettable for PkcMode1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_mode2.rs b/mcxa276-pac/src/pkc0/pkc_mode2.rs deleted file mode 100644 index b49bd60ad..000000000 --- a/mcxa276-pac/src/pkc0/pkc_mode2.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PKC_MODE2` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_MODE2` writer"] -pub type W = crate::W; -#[doc = "Field `MODE` reader - Calculation Mode / MC Start address"] -pub type ModeR = crate::FieldReader; -#[doc = "Field `MODE` writer - Calculation Mode / MC Start address"] -pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new((self.bits & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Calculation Mode / MC Start address"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 0) - } -} -#[doc = "Mode register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_mode2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_mode2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcMode2Spec; -impl crate::RegisterSpec for PkcMode2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_mode2::R`](R) reader structure"] -impl crate::Readable for PkcMode2Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_mode2::W`](W) writer structure"] -impl crate::Writable for PkcMode2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_MODE2 to value 0"] -impl crate::Resettable for PkcMode2Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_module_id.rs b/mcxa276-pac/src/pkc0/pkc_module_id.rs deleted file mode 100644 index ae229fdf9..000000000 --- a/mcxa276-pac/src/pkc0/pkc_module_id.rs +++ /dev/null @@ -1,43 +0,0 @@ -#[doc = "Register `PKC_MODULE_ID` reader"] -pub type R = crate::R; -#[doc = "Field `SIZE` reader - Address space of the IP"] -pub type SizeR = crate::FieldReader; -#[doc = "Field `MINOR_REV` reader - Minor revision"] -pub type MinorRevR = crate::FieldReader; -#[doc = "Field `MAJOR_REV` reader - Major revision"] -pub type MajorRevR = crate::FieldReader; -#[doc = "Field `ID` reader - Module ID"] -pub type IdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Address space of the IP"] - #[inline(always)] - pub fn size(&self) -> SizeR { - SizeR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:11 - Minor revision"] - #[inline(always)] - pub fn minor_rev(&self) -> MinorRevR { - MinorRevR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Major revision"] - #[inline(always)] - pub fn major_rev(&self) -> MajorRevR { - MajorRevR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:31 - Module ID"] - #[inline(always)] - pub fn id(&self) -> IdR { - IdR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_module_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcModuleIdSpec; -impl crate::RegisterSpec for PkcModuleIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_module_id::R`](R) reader structure"] -impl crate::Readable for PkcModuleIdSpec {} -#[doc = "`reset()` method sets PKC_MODULE_ID to value 0xe103_1280"] -impl crate::Resettable for PkcModuleIdSpec { - const RESET_VALUE: u32 = 0xe103_1280; -} diff --git a/mcxa276-pac/src/pkc0/pkc_soft_rst.rs b/mcxa276-pac/src/pkc0/pkc_soft_rst.rs deleted file mode 100644 index 72360a81d..000000000 --- a/mcxa276-pac/src/pkc0/pkc_soft_rst.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PKC_SOFT_RST` writer"] -pub type W = crate::W; -#[doc = "Field `SOFT_RST` writer - Write 1 to reset module (0 has no effect)"] -pub type SoftRstW<'a, REG> = crate::BitWriter<'a, REG>; -impl W { - #[doc = "Bit 0 - Write 1 to reset module (0 has no effect)"] - #[inline(always)] - pub fn soft_rst(&mut self) -> SoftRstW { - SoftRstW::new(self, 0) - } -} -#[doc = "Software reset\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_soft_rst::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcSoftRstSpec; -impl crate::RegisterSpec for PkcSoftRstSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`pkc_soft_rst::W`](W) writer structure"] -impl crate::Writable for PkcSoftRstSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_SOFT_RST to value 0"] -impl crate::Resettable for PkcSoftRstSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_status.rs b/mcxa276-pac/src/pkc0/pkc_status.rs deleted file mode 100644 index cc2e126ce..000000000 --- a/mcxa276-pac/src/pkc0/pkc_status.rs +++ /dev/null @@ -1,48 +0,0 @@ -#[doc = "Register `PKC_STATUS` reader"] -pub type R = crate::R; -#[doc = "Field `ACTIV` reader - PKC ACTIV"] -pub type ActivR = crate::BitReader; -#[doc = "Field `CARRY` reader - Carry overflow flag"] -pub type CarryR = crate::BitReader; -#[doc = "Field `ZERO` reader - Zero result flag"] -pub type ZeroR = crate::BitReader; -#[doc = "Field `GOANY` reader - Combined GO status flag"] -pub type GoanyR = crate::BitReader; -#[doc = "Field `LOCKED` reader - Parameter set locked"] -pub type LockedR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - PKC ACTIV"] - #[inline(always)] - pub fn activ(&self) -> ActivR { - ActivR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Carry overflow flag"] - #[inline(always)] - pub fn carry(&self) -> CarryR { - CarryR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Zero result flag"] - #[inline(always)] - pub fn zero(&self) -> ZeroR { - ZeroR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Combined GO status flag"] - #[inline(always)] - pub fn goany(&self) -> GoanyR { - GoanyR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 5:6 - Parameter set locked"] - #[inline(always)] - pub fn locked(&self) -> LockedR { - LockedR::new(((self.bits >> 5) & 3) as u8) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcStatusSpec; -impl crate::RegisterSpec for PkcStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_status::R`](R) reader structure"] -impl crate::Readable for PkcStatusSpec {} -#[doc = "`reset()` method sets PKC_STATUS to value 0"] -impl crate::Resettable for PkcStatusSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_ulen.rs b/mcxa276-pac/src/pkc0/pkc_ulen.rs deleted file mode 100644 index c7e60050c..000000000 --- a/mcxa276-pac/src/pkc0/pkc_ulen.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PKC_ULEN` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_ULEN` writer"] -pub type W = crate::W; -#[doc = "Field `LEN` reader - Length of universal pointer calculation"] -pub type LenR = crate::FieldReader; -#[doc = "Field `LEN` writer - Length of universal pointer calculation"] -pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Length of universal pointer calculation"] - #[inline(always)] - pub fn len(&self) -> LenR { - LenR::new((self.bits & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Length of universal pointer calculation"] - #[inline(always)] - pub fn len(&mut self) -> LenW { - LenW::new(self, 0) - } -} -#[doc = "Universal pointer length\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_ulen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_ulen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcUlenSpec; -impl crate::RegisterSpec for PkcUlenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_ulen::R`](R) reader structure"] -impl crate::Readable for PkcUlenSpec {} -#[doc = "`write(|w| ..)` method takes [`pkc_ulen::W`](W) writer structure"] -impl crate::Writable for PkcUlenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_ULEN to value 0"] -impl crate::Resettable for PkcUlenSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_uptr.rs b/mcxa276-pac/src/pkc0/pkc_uptr.rs deleted file mode 100644 index 8c591a256..000000000 --- a/mcxa276-pac/src/pkc0/pkc_uptr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PKC_UPTR` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_UPTR` writer"] -pub type W = crate::W; -#[doc = "Field `PTR` reader - Pointer to start address of PKC FUP program"] -pub type PtrR = crate::FieldReader; -#[doc = "Field `PTR` writer - Pointer to start address of PKC FUP program"] -pub type PtrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Pointer to start address of PKC FUP program"] - #[inline(always)] - pub fn ptr(&self) -> PtrR { - PtrR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Pointer to start address of PKC FUP program"] - #[inline(always)] - pub fn ptr(&mut self) -> PtrW { - PtrW::new(self, 0) - } -} -#[doc = "Universal pointer FUP program\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcUptrSpec; -impl crate::RegisterSpec for PkcUptrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_uptr::R`](R) reader structure"] -impl crate::Readable for PkcUptrSpec {} -#[doc = "`write(|w| ..)` method takes [`pkc_uptr::W`](W) writer structure"] -impl crate::Writable for PkcUptrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_UPTR to value 0"] -impl crate::Resettable for PkcUptrSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_uptrt.rs b/mcxa276-pac/src/pkc0/pkc_uptrt.rs deleted file mode 100644 index 177dd953e..000000000 --- a/mcxa276-pac/src/pkc0/pkc_uptrt.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `PKC_UPTRT` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_UPTRT` writer"] -pub type W = crate::W; -#[doc = "Field `PTR` reader - Pointer to start address of PKC FUP table"] -pub type PtrR = crate::FieldReader; -#[doc = "Field `PTR` writer - Pointer to start address of PKC FUP table"] -pub type PtrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Pointer to start address of PKC FUP table"] - #[inline(always)] - pub fn ptr(&self) -> PtrR { - PtrR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Pointer to start address of PKC FUP table"] - #[inline(always)] - pub fn ptr(&mut self) -> PtrW { - PtrW::new(self, 0) - } -} -#[doc = "Universal pointer FUP table\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_uptrt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_uptrt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcUptrtSpec; -impl crate::RegisterSpec for PkcUptrtSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_uptrt::R`](R) reader structure"] -impl crate::Readable for PkcUptrtSpec {} -#[doc = "`write(|w| ..)` method takes [`pkc_uptrt::W`](W) writer structure"] -impl crate::Writable for PkcUptrtSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_UPTRT to value 0"] -impl crate::Resettable for PkcUptrtSpec {} diff --git a/mcxa276-pac/src/pkc0/pkc_version.rs b/mcxa276-pac/src/pkc0/pkc_version.rs deleted file mode 100644 index c0304eed6..000000000 --- a/mcxa276-pac/src/pkc0/pkc_version.rs +++ /dev/null @@ -1,124 +0,0 @@ -#[doc = "Register `PKC_VERSION` reader"] -pub type R = crate::R; -#[doc = "Native multiplier size and operand granularity\n\nValue on reset: 2"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mulsize { - #[doc = "2: 64-bit multiplier"] - Bit64 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mulsize) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mulsize { - type Ux = u8; -} -impl crate::IsEnum for Mulsize {} -#[doc = "Field `MULSIZE` reader - Native multiplier size and operand granularity"] -pub type MulsizeR = crate::FieldReader; -impl MulsizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Mulsize::Bit64), - _ => None, - } - } - #[doc = "64-bit multiplier"] - #[inline(always)] - pub fn is_bit64(&self) -> bool { - *self == Mulsize::Bit64 - } -} -#[doc = "Field `MCAVAIL` reader - MC feature (layer1 calculation) is available"] -pub type McavailR = crate::BitReader; -#[doc = "Field `UPAVAIL` reader - UP feature (layer2 calculation) is available"] -pub type UpavailR = crate::BitReader; -#[doc = "Field `UPCACHEAVAIL` reader - UP cache is available"] -pub type UpcacheavailR = crate::BitReader; -#[doc = "Field `GF2AVAIL` reader - GF2 calculation modes are available"] -pub type Gf2availR = crate::BitReader; -#[doc = "Field `PARAMNUM` reader - Number of parameter sets for real calculation"] -pub type ParamnumR = crate::FieldReader; -#[doc = "Field `SBX0AVAIL` reader - SBX0 operation is available"] -pub type Sbx0availR = crate::BitReader; -#[doc = "Field `SBX1AVAIL` reader - SBX1 operation is available"] -pub type Sbx1availR = crate::BitReader; -#[doc = "Field `SBX2AVAIL` reader - SBX2 operation is available"] -pub type Sbx2availR = crate::BitReader; -#[doc = "Field `SBX3AVAIL` reader - SBX3 operation is available"] -pub type Sbx3availR = crate::BitReader; -#[doc = "Field `MCRECONF_SIZE` reader - Size of reconfigurable MC table in bytes."] -pub type McreconfSizeR = crate::FieldReader; -impl R { - #[doc = "Bits 0:1 - Native multiplier size and operand granularity"] - #[inline(always)] - pub fn mulsize(&self) -> MulsizeR { - MulsizeR::new((self.bits & 3) as u8) - } - #[doc = "Bit 2 - MC feature (layer1 calculation) is available"] - #[inline(always)] - pub fn mcavail(&self) -> McavailR { - McavailR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - UP feature (layer2 calculation) is available"] - #[inline(always)] - pub fn upavail(&self) -> UpavailR { - UpavailR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - UP cache is available"] - #[inline(always)] - pub fn upcacheavail(&self) -> UpcacheavailR { - UpcacheavailR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - GF2 calculation modes are available"] - #[inline(always)] - pub fn gf2avail(&self) -> Gf2availR { - Gf2availR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bits 6:7 - Number of parameter sets for real calculation"] - #[inline(always)] - pub fn paramnum(&self) -> ParamnumR { - ParamnumR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bit 8 - SBX0 operation is available"] - #[inline(always)] - pub fn sbx0avail(&self) -> Sbx0availR { - Sbx0availR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SBX1 operation is available"] - #[inline(always)] - pub fn sbx1avail(&self) -> Sbx1availR { - Sbx1availR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SBX2 operation is available"] - #[inline(always)] - pub fn sbx2avail(&self) -> Sbx2availR { - Sbx2availR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - SBX3 operation is available"] - #[inline(always)] - pub fn sbx3avail(&self) -> Sbx3availR { - Sbx3availR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:19 - Size of reconfigurable MC table in bytes."] - #[inline(always)] - pub fn mcreconf_size(&self) -> McreconfSizeR { - McreconfSizeR::new(((self.bits >> 12) & 0xff) as u8) - } -} -#[doc = "PKC version register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcVersionSpec; -impl crate::RegisterSpec for PkcVersionSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_version::R`](R) reader structure"] -impl crate::Readable for PkcVersionSpec {} -#[doc = "`reset()` method sets PKC_VERSION to value 0xbe"] -impl crate::Resettable for PkcVersionSpec { - const RESET_VALUE: u32 = 0xbe; -} diff --git a/mcxa276-pac/src/pkc0/pkc_xyptr1.rs b/mcxa276-pac/src/pkc0/pkc_xyptr1.rs deleted file mode 100644 index 185fb9dfb..000000000 --- a/mcxa276-pac/src/pkc0/pkc_xyptr1.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `PKC_XYPTR1` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_XYPTR1` writer"] -pub type W = crate::W; -#[doc = "Field `XPTR` reader - Start address of X operand in PKCRAM with byte granularity"] -pub type XptrR = crate::FieldReader; -#[doc = "Field `XPTR` writer - Start address of X operand in PKCRAM with byte granularity"] -pub type XptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `YPTR` reader - Start address of Y operand in PKCRAM with byte granularity"] -pub type YptrR = crate::FieldReader; -#[doc = "Field `YPTR` writer - Start address of Y operand in PKCRAM with byte granularity"] -pub type YptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn xptr(&self) -> XptrR { - XptrR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn yptr(&self) -> YptrR { - YptrR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn xptr(&mut self) -> XptrW { - XptrW::new(self, 0) - } - #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn yptr(&mut self) -> YptrW { - YptrW::new(self, 16) - } -} -#[doc = "X+Y pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcXyptr1Spec; -impl crate::RegisterSpec for PkcXyptr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_xyptr1::R`](R) reader structure"] -impl crate::Readable for PkcXyptr1Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_xyptr1::W`](W) writer structure"] -impl crate::Writable for PkcXyptr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_XYPTR1 to value 0"] -impl crate::Resettable for PkcXyptr1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_xyptr2.rs b/mcxa276-pac/src/pkc0/pkc_xyptr2.rs deleted file mode 100644 index 6114ba782..000000000 --- a/mcxa276-pac/src/pkc0/pkc_xyptr2.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `PKC_XYPTR2` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_XYPTR2` writer"] -pub type W = crate::W; -#[doc = "Field `XPTR` reader - Start address of X operand in PKCRAM with byte granularity"] -pub type XptrR = crate::FieldReader; -#[doc = "Field `XPTR` writer - Start address of X operand in PKCRAM with byte granularity"] -pub type XptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `YPTR` reader - Start address of Y operand in PKCRAM with byte granularity"] -pub type YptrR = crate::FieldReader; -#[doc = "Field `YPTR` writer - Start address of Y operand in PKCRAM with byte granularity"] -pub type YptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn xptr(&self) -> XptrR { - XptrR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn yptr(&self) -> YptrR { - YptrR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Start address of X operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn xptr(&mut self) -> XptrW { - XptrW::new(self, 0) - } - #[doc = "Bits 16:31 - Start address of Y operand in PKCRAM with byte granularity"] - #[inline(always)] - pub fn yptr(&mut self) -> YptrW { - YptrW::new(self, 16) - } -} -#[doc = "X+Y pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_xyptr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_xyptr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcXyptr2Spec; -impl crate::RegisterSpec for PkcXyptr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_xyptr2::R`](R) reader structure"] -impl crate::Readable for PkcXyptr2Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_xyptr2::W`](W) writer structure"] -impl crate::Writable for PkcXyptr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_XYPTR2 to value 0"] -impl crate::Resettable for PkcXyptr2Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_zrptr1.rs b/mcxa276-pac/src/pkc0/pkc_zrptr1.rs deleted file mode 100644 index fd79d9ac5..000000000 --- a/mcxa276-pac/src/pkc0/pkc_zrptr1.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `PKC_ZRPTR1` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_ZRPTR1` writer"] -pub type W = crate::W; -#[doc = "Field `ZPTR` reader - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] -pub type ZptrR = crate::FieldReader; -#[doc = "Field `ZPTR` writer - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] -pub type ZptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `RPTR` reader - Start address of R result in PKCRAM with byte granularity"] -pub type RptrR = crate::FieldReader; -#[doc = "Field `RPTR` writer - Start address of R result in PKCRAM with byte granularity"] -pub type RptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] - #[inline(always)] - pub fn zptr(&self) -> ZptrR { - ZptrR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] - #[inline(always)] - pub fn rptr(&self) -> RptrR { - RptrR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] - #[inline(always)] - pub fn zptr(&mut self) -> ZptrW { - ZptrW::new(self, 0) - } - #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] - #[inline(always)] - pub fn rptr(&mut self) -> RptrW { - RptrW::new(self, 16) - } -} -#[doc = "Z+R pointer register, parameter set 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcZrptr1Spec; -impl crate::RegisterSpec for PkcZrptr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_zrptr1::R`](R) reader structure"] -impl crate::Readable for PkcZrptr1Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_zrptr1::W`](W) writer structure"] -impl crate::Writable for PkcZrptr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_ZRPTR1 to value 0"] -impl crate::Resettable for PkcZrptr1Spec {} diff --git a/mcxa276-pac/src/pkc0/pkc_zrptr2.rs b/mcxa276-pac/src/pkc0/pkc_zrptr2.rs deleted file mode 100644 index 8c1bd2d87..000000000 --- a/mcxa276-pac/src/pkc0/pkc_zrptr2.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `PKC_ZRPTR2` reader"] -pub type R = crate::R; -#[doc = "Register `PKC_ZRPTR2` writer"] -pub type W = crate::W; -#[doc = "Field `ZPTR` reader - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] -pub type ZptrR = crate::FieldReader; -#[doc = "Field `ZPTR` writer - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] -pub type ZptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `RPTR` reader - Start address of R result in PKCRAM with byte granularity"] -pub type RptrR = crate::FieldReader; -#[doc = "Field `RPTR` writer - Start address of R result in PKCRAM with byte granularity"] -pub type RptrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] - #[inline(always)] - pub fn zptr(&self) -> ZptrR { - ZptrR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] - #[inline(always)] - pub fn rptr(&self) -> RptrR { - RptrR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST"] - #[inline(always)] - pub fn zptr(&mut self) -> ZptrW { - ZptrW::new(self, 0) - } - #[doc = "Bits 16:31 - Start address of R result in PKCRAM with byte granularity"] - #[inline(always)] - pub fn rptr(&mut self) -> RptrW { - RptrW::new(self, 16) - } -} -#[doc = "Z+R pointer register, parameter set 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_zrptr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_zrptr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkcZrptr2Spec; -impl crate::RegisterSpec for PkcZrptr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkc_zrptr2::R`](R) reader structure"] -impl crate::Readable for PkcZrptr2Spec {} -#[doc = "`write(|w| ..)` method takes [`pkc_zrptr2::W`](W) writer structure"] -impl crate::Writable for PkcZrptr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKC_ZRPTR2 to value 0"] -impl crate::Resettable for PkcZrptr2Spec {} diff --git a/mcxa276-pac/src/port0.rs b/mcxa276-pac/src/port0.rs deleted file mode 100644 index d7ed05fc0..000000000 --- a/mcxa276-pac/src/port0.rs +++ /dev/null @@ -1,428 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x0c], - gpclr: Gpclr, - gpchr: Gpchr, - _reserved3: [u8; 0x08], - config: Config, - _reserved4: [u8; 0x3c], - calib0: Calib0, - calib1: Calib1, - _reserved6: [u8; 0x18], - pcr0: Pcr0, - pcr1: Pcr1, - pcr2: Pcr2, - pcr3: Pcr3, - pcr4: Pcr4, - pcr5: Pcr5, - pcr6: Pcr6, - pcr7: Pcr7, - pcr8: Pcr8, - pcr9: Pcr9, - pcr10: Pcr10, - pcr11: Pcr11, - pcr12: Pcr12, - pcr13: Pcr13, - pcr14: Pcr14, - pcr15: Pcr15, - pcr16: Pcr16, - pcr17: Pcr17, - pcr18: Pcr18, - pcr19: Pcr19, - pcr20: Pcr20, - pcr21: Pcr21, - pcr22: Pcr22, - pcr23: Pcr23, - pcr24: Pcr24, - pcr25: Pcr25, - pcr26: Pcr26, - pcr27: Pcr27, - pcr28: Pcr28, - pcr29: Pcr29, - pcr30: Pcr30, - pcr31: Pcr31, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x10 - Global Pin Control Low"] - #[inline(always)] - pub const fn gpclr(&self) -> &Gpclr { - &self.gpclr - } - #[doc = "0x14 - Global Pin Control High"] - #[inline(always)] - pub const fn gpchr(&self) -> &Gpchr { - &self.gpchr - } - #[doc = "0x20 - Configuration"] - #[inline(always)] - pub const fn config(&self) -> &Config { - &self.config - } - #[doc = "0x60 - Calibration 0"] - #[inline(always)] - pub const fn calib0(&self) -> &Calib0 { - &self.calib0 - } - #[doc = "0x64 - Calibration 1"] - #[inline(always)] - pub const fn calib1(&self) -> &Calib1 { - &self.calib1 - } - #[doc = "0x80 - Pin Control 0"] - #[inline(always)] - pub const fn pcr0(&self) -> &Pcr0 { - &self.pcr0 - } - #[doc = "0x84 - Pin Control 1"] - #[inline(always)] - pub const fn pcr1(&self) -> &Pcr1 { - &self.pcr1 - } - #[doc = "0x88 - Pin Control 2"] - #[inline(always)] - pub const fn pcr2(&self) -> &Pcr2 { - &self.pcr2 - } - #[doc = "0x8c - Pin Control 3"] - #[inline(always)] - pub const fn pcr3(&self) -> &Pcr3 { - &self.pcr3 - } - #[doc = "0x90 - Pin Control 4"] - #[inline(always)] - pub const fn pcr4(&self) -> &Pcr4 { - &self.pcr4 - } - #[doc = "0x94 - Pin Control 5"] - #[inline(always)] - pub const fn pcr5(&self) -> &Pcr5 { - &self.pcr5 - } - #[doc = "0x98 - Pin Control 6"] - #[inline(always)] - pub const fn pcr6(&self) -> &Pcr6 { - &self.pcr6 - } - #[doc = "0x9c - Pin Control 7"] - #[inline(always)] - pub const fn pcr7(&self) -> &Pcr7 { - &self.pcr7 - } - #[doc = "0xa0 - Pin Control 8"] - #[inline(always)] - pub const fn pcr8(&self) -> &Pcr8 { - &self.pcr8 - } - #[doc = "0xa4 - Pin Control 9"] - #[inline(always)] - pub const fn pcr9(&self) -> &Pcr9 { - &self.pcr9 - } - #[doc = "0xa8 - Pin Control 10"] - #[inline(always)] - pub const fn pcr10(&self) -> &Pcr10 { - &self.pcr10 - } - #[doc = "0xac - Pin Control 11"] - #[inline(always)] - pub const fn pcr11(&self) -> &Pcr11 { - &self.pcr11 - } - #[doc = "0xb0 - Pin Control 12"] - #[inline(always)] - pub const fn pcr12(&self) -> &Pcr12 { - &self.pcr12 - } - #[doc = "0xb4 - Pin Control 13"] - #[inline(always)] - pub const fn pcr13(&self) -> &Pcr13 { - &self.pcr13 - } - #[doc = "0xb8 - Pin Control 14"] - #[inline(always)] - pub const fn pcr14(&self) -> &Pcr14 { - &self.pcr14 - } - #[doc = "0xbc - Pin Control 15"] - #[inline(always)] - pub const fn pcr15(&self) -> &Pcr15 { - &self.pcr15 - } - #[doc = "0xc0 - Pin Control 16"] - #[inline(always)] - pub const fn pcr16(&self) -> &Pcr16 { - &self.pcr16 - } - #[doc = "0xc4 - Pin Control 17"] - #[inline(always)] - pub const fn pcr17(&self) -> &Pcr17 { - &self.pcr17 - } - #[doc = "0xc8 - Pin Control 18"] - #[inline(always)] - pub const fn pcr18(&self) -> &Pcr18 { - &self.pcr18 - } - #[doc = "0xcc - Pin Control 19"] - #[inline(always)] - pub const fn pcr19(&self) -> &Pcr19 { - &self.pcr19 - } - #[doc = "0xd0 - Pin Control 20"] - #[inline(always)] - pub const fn pcr20(&self) -> &Pcr20 { - &self.pcr20 - } - #[doc = "0xd4 - Pin Control 21"] - #[inline(always)] - pub const fn pcr21(&self) -> &Pcr21 { - &self.pcr21 - } - #[doc = "0xd8 - Pin Control 22"] - #[inline(always)] - pub const fn pcr22(&self) -> &Pcr22 { - &self.pcr22 - } - #[doc = "0xdc - Pin Control 23"] - #[inline(always)] - pub const fn pcr23(&self) -> &Pcr23 { - &self.pcr23 - } - #[doc = "0xe0 - Pin Control 24"] - #[inline(always)] - pub const fn pcr24(&self) -> &Pcr24 { - &self.pcr24 - } - #[doc = "0xe4 - Pin Control 25"] - #[inline(always)] - pub const fn pcr25(&self) -> &Pcr25 { - &self.pcr25 - } - #[doc = "0xe8 - Pin Control 26"] - #[inline(always)] - pub const fn pcr26(&self) -> &Pcr26 { - &self.pcr26 - } - #[doc = "0xec - Pin Control 27"] - #[inline(always)] - pub const fn pcr27(&self) -> &Pcr27 { - &self.pcr27 - } - #[doc = "0xf0 - Pin Control 28"] - #[inline(always)] - pub const fn pcr28(&self) -> &Pcr28 { - &self.pcr28 - } - #[doc = "0xf4 - Pin Control 29"] - #[inline(always)] - pub const fn pcr29(&self) -> &Pcr29 { - &self.pcr29 - } - #[doc = "0xf8 - Pin Control 30"] - #[inline(always)] - pub const fn pcr30(&self) -> &Pcr30 { - &self.pcr30 - } - #[doc = "0xfc - Pin Control 31"] - #[inline(always)] - pub const fn pcr31(&self) -> &Pcr31 { - &self.pcr31 - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] -#[doc(alias = "GPCLR")] -pub type Gpclr = crate::Reg; -#[doc = "Global Pin Control Low"] -pub mod gpclr; -#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] -#[doc(alias = "GPCHR")] -pub type Gpchr = crate::Reg; -#[doc = "Global Pin Control High"] -pub mod gpchr; -#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] -#[doc(alias = "CONFIG")] -pub type Config = crate::Reg; -#[doc = "Configuration"] -pub mod config; -#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] -#[doc(alias = "CALIB0")] -pub type Calib0 = crate::Reg; -#[doc = "Calibration 0"] -pub mod calib0; -#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] -#[doc(alias = "CALIB1")] -pub type Calib1 = crate::Reg; -#[doc = "Calibration 1"] -pub mod calib1; -#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] -#[doc(alias = "PCR0")] -pub type Pcr0 = crate::Reg; -#[doc = "Pin Control 0"] -pub mod pcr0; -#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] -#[doc(alias = "PCR1")] -pub type Pcr1 = crate::Reg; -#[doc = "Pin Control 1"] -pub mod pcr1; -#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] -#[doc(alias = "PCR2")] -pub type Pcr2 = crate::Reg; -#[doc = "Pin Control 2"] -pub mod pcr2; -#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] -#[doc(alias = "PCR3")] -pub type Pcr3 = crate::Reg; -#[doc = "Pin Control 3"] -pub mod pcr3; -#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] -#[doc(alias = "PCR4")] -pub type Pcr4 = crate::Reg; -#[doc = "Pin Control 4"] -pub mod pcr4; -#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] -#[doc(alias = "PCR5")] -pub type Pcr5 = crate::Reg; -#[doc = "Pin Control 5"] -pub mod pcr5; -#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] -#[doc(alias = "PCR6")] -pub type Pcr6 = crate::Reg; -#[doc = "Pin Control 6"] -pub mod pcr6; -#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] -#[doc(alias = "PCR7")] -pub type Pcr7 = crate::Reg; -#[doc = "Pin Control 7"] -pub mod pcr7; -#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] -#[doc(alias = "PCR8")] -pub type Pcr8 = crate::Reg; -#[doc = "Pin Control 8"] -pub mod pcr8; -#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] -#[doc(alias = "PCR9")] -pub type Pcr9 = crate::Reg; -#[doc = "Pin Control 9"] -pub mod pcr9; -#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] -#[doc(alias = "PCR10")] -pub type Pcr10 = crate::Reg; -#[doc = "Pin Control 10"] -pub mod pcr10; -#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] -#[doc(alias = "PCR11")] -pub type Pcr11 = crate::Reg; -#[doc = "Pin Control 11"] -pub mod pcr11; -#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] -#[doc(alias = "PCR12")] -pub type Pcr12 = crate::Reg; -#[doc = "Pin Control 12"] -pub mod pcr12; -#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] -#[doc(alias = "PCR13")] -pub type Pcr13 = crate::Reg; -#[doc = "Pin Control 13"] -pub mod pcr13; -#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] -#[doc(alias = "PCR14")] -pub type Pcr14 = crate::Reg; -#[doc = "Pin Control 14"] -pub mod pcr14; -#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] -#[doc(alias = "PCR15")] -pub type Pcr15 = crate::Reg; -#[doc = "Pin Control 15"] -pub mod pcr15; -#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] -#[doc(alias = "PCR16")] -pub type Pcr16 = crate::Reg; -#[doc = "Pin Control 16"] -pub mod pcr16; -#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] -#[doc(alias = "PCR17")] -pub type Pcr17 = crate::Reg; -#[doc = "Pin Control 17"] -pub mod pcr17; -#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] -#[doc(alias = "PCR18")] -pub type Pcr18 = crate::Reg; -#[doc = "Pin Control 18"] -pub mod pcr18; -#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] -#[doc(alias = "PCR19")] -pub type Pcr19 = crate::Reg; -#[doc = "Pin Control 19"] -pub mod pcr19; -#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] -#[doc(alias = "PCR20")] -pub type Pcr20 = crate::Reg; -#[doc = "Pin Control 20"] -pub mod pcr20; -#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] -#[doc(alias = "PCR21")] -pub type Pcr21 = crate::Reg; -#[doc = "Pin Control 21"] -pub mod pcr21; -#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] -#[doc(alias = "PCR22")] -pub type Pcr22 = crate::Reg; -#[doc = "Pin Control 22"] -pub mod pcr22; -#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] -#[doc(alias = "PCR23")] -pub type Pcr23 = crate::Reg; -#[doc = "Pin Control 23"] -pub mod pcr23; -#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] -#[doc(alias = "PCR24")] -pub type Pcr24 = crate::Reg; -#[doc = "Pin Control 24"] -pub mod pcr24; -#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] -#[doc(alias = "PCR25")] -pub type Pcr25 = crate::Reg; -#[doc = "Pin Control 25"] -pub mod pcr25; -#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] -#[doc(alias = "PCR26")] -pub type Pcr26 = crate::Reg; -#[doc = "Pin Control 26"] -pub mod pcr26; -#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] -#[doc(alias = "PCR27")] -pub type Pcr27 = crate::Reg; -#[doc = "Pin Control 27"] -pub mod pcr27; -#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] -#[doc(alias = "PCR28")] -pub type Pcr28 = crate::Reg; -#[doc = "Pin Control 28"] -pub mod pcr28; -#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] -#[doc(alias = "PCR29")] -pub type Pcr29 = crate::Reg; -#[doc = "Pin Control 29"] -pub mod pcr29; -#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] -#[doc(alias = "PCR30")] -pub type Pcr30 = crate::Reg; -#[doc = "Pin Control 30"] -pub mod pcr30; -#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] -#[doc(alias = "PCR31")] -pub type Pcr31 = crate::Reg; -#[doc = "Pin Control 31"] -pub mod pcr31; diff --git a/mcxa276-pac/src/port0/calib0.rs b/mcxa276-pac/src/port0/calib0.rs deleted file mode 100644 index 029fa12f3..000000000 --- a/mcxa276-pac/src/port0/calib0.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB0` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB0` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib0Spec; -impl crate::RegisterSpec for Calib0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] -impl crate::Readable for Calib0Spec {} -#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] -impl crate::Writable for Calib0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB0 to value 0"] -impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port0/calib1.rs b/mcxa276-pac/src/port0/calib1.rs deleted file mode 100644 index e18f61234..000000000 --- a/mcxa276-pac/src/port0/calib1.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB1` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB1` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib1Spec; -impl crate::RegisterSpec for Calib1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] -impl crate::Readable for Calib1Spec {} -#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] -impl crate::Writable for Calib1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB1 to value 0"] -impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port0/config.rs b/mcxa276-pac/src/port0/config.rs deleted file mode 100644 index da92c5b27..000000000 --- a/mcxa276-pac/src/port0/config.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `CONFIG` reader"] -pub type R = crate::R; -#[doc = "Register `CONFIG` writer"] -pub type W = crate::W; -#[doc = "Port Voltage Range\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Range { - #[doc = "0: 1.71 V-3.6 V"] - Range0 = 0, - #[doc = "1: 2.70 V-3.6 V"] - Range1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Range) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RANGE` reader - Port Voltage Range"] -pub type RangeR = crate::BitReader; -impl RangeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Range { - match self.bits { - false => Range::Range0, - true => Range::Range1, - } - } - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn is_range0(&self) -> bool { - *self == Range::Range0 - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn is_range1(&self) -> bool { - *self == Range::Range1 - } -} -#[doc = "Field `RANGE` writer - Port Voltage Range"] -pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; -impl<'a, REG> RangeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn range0(self) -> &'a mut crate::W { - self.variant(Range::Range0) - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn range1(self) -> &'a mut crate::W { - self.variant(Range::Range1) - } -} -impl R { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&self) -> RangeR { - RangeR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&mut self) -> RangeW { - RangeW::new(self, 0) - } -} -#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ConfigSpec; -impl crate::RegisterSpec for ConfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`config::R`](R) reader structure"] -impl crate::Readable for ConfigSpec {} -#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] -impl crate::Writable for ConfigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CONFIG to value 0"] -impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port0/gpchr.rs b/mcxa276-pac/src/port0/gpchr.rs deleted file mode 100644 index af92d0d62..000000000 --- a/mcxa276-pac/src/port0/gpchr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCHR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCHR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe16 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] -pub type Gpwe16R = crate::BitReader; -impl Gpwe16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe16 { - match self.bits { - false => Gpwe16::Gpwe0, - true => Gpwe16::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe16::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe16::Gpwe1 - } -} -#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] -pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; -impl<'a, REG> Gpwe16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe17 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] -pub type Gpwe17R = crate::BitReader; -impl Gpwe17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe17 { - match self.bits { - false => Gpwe17::Gpwe0, - true => Gpwe17::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe17::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe17::Gpwe1 - } -} -#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] -pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; -impl<'a, REG> Gpwe17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe18 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] -pub type Gpwe18R = crate::BitReader; -impl Gpwe18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe18 { - match self.bits { - false => Gpwe18::Gpwe0, - true => Gpwe18::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe18::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe18::Gpwe1 - } -} -#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] -pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; -impl<'a, REG> Gpwe18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe19 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] -pub type Gpwe19R = crate::BitReader; -impl Gpwe19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe19 { - match self.bits { - false => Gpwe19::Gpwe0, - true => Gpwe19::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe19::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe19::Gpwe1 - } -} -#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] -pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; -impl<'a, REG> Gpwe19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe20 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] -pub type Gpwe20R = crate::BitReader; -impl Gpwe20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe20 { - match self.bits { - false => Gpwe20::Gpwe0, - true => Gpwe20::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe20::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe20::Gpwe1 - } -} -#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] -pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; -impl<'a, REG> Gpwe20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe21 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] -pub type Gpwe21R = crate::BitReader; -impl Gpwe21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe21 { - match self.bits { - false => Gpwe21::Gpwe0, - true => Gpwe21::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe21::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe21::Gpwe1 - } -} -#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] -pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; -impl<'a, REG> Gpwe21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe22 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] -pub type Gpwe22R = crate::BitReader; -impl Gpwe22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe22 { - match self.bits { - false => Gpwe22::Gpwe0, - true => Gpwe22::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe22::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe22::Gpwe1 - } -} -#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] -pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; -impl<'a, REG> Gpwe22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe23 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] -pub type Gpwe23R = crate::BitReader; -impl Gpwe23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe23 { - match self.bits { - false => Gpwe23::Gpwe0, - true => Gpwe23::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe23::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe23::Gpwe1 - } -} -#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] -pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; -impl<'a, REG> Gpwe23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe24 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] -pub type Gpwe24R = crate::BitReader; -impl Gpwe24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe24 { - match self.bits { - false => Gpwe24::Gpwe0, - true => Gpwe24::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe24::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe24::Gpwe1 - } -} -#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] -pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; -impl<'a, REG> Gpwe24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe25 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] -pub type Gpwe25R = crate::BitReader; -impl Gpwe25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe25 { - match self.bits { - false => Gpwe25::Gpwe0, - true => Gpwe25::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe25::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe25::Gpwe1 - } -} -#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] -pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; -impl<'a, REG> Gpwe25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe26 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] -pub type Gpwe26R = crate::BitReader; -impl Gpwe26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe26 { - match self.bits { - false => Gpwe26::Gpwe0, - true => Gpwe26::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe26::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe26::Gpwe1 - } -} -#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] -pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; -impl<'a, REG> Gpwe26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe27 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] -pub type Gpwe27R = crate::BitReader; -impl Gpwe27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe27 { - match self.bits { - false => Gpwe27::Gpwe0, - true => Gpwe27::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe27::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe27::Gpwe1 - } -} -#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] -pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; -impl<'a, REG> Gpwe27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe28 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] -pub type Gpwe28R = crate::BitReader; -impl Gpwe28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe28 { - match self.bits { - false => Gpwe28::Gpwe0, - true => Gpwe28::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe28::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe28::Gpwe1 - } -} -#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] -pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; -impl<'a, REG> Gpwe28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe29 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] -pub type Gpwe29R = crate::BitReader; -impl Gpwe29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe29 { - match self.bits { - false => Gpwe29::Gpwe0, - true => Gpwe29::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe29::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe29::Gpwe1 - } -} -#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] -pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; -impl<'a, REG> Gpwe29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe30 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] -pub type Gpwe30R = crate::BitReader; -impl Gpwe30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe30 { - match self.bits { - false => Gpwe30::Gpwe0, - true => Gpwe30::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe30::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe30::Gpwe1 - } -} -#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] -pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; -impl<'a, REG> Gpwe30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe31 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] -pub type Gpwe31R = crate::BitReader; -impl Gpwe31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe31 { - match self.bits { - false => Gpwe31::Gpwe0, - true => Gpwe31::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe31::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe31::Gpwe1 - } -} -#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] -pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; -impl<'a, REG> Gpwe31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&self) -> Gpwe16R { - Gpwe16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&self) -> Gpwe17R { - Gpwe17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&self) -> Gpwe18R { - Gpwe18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&self) -> Gpwe19R { - Gpwe19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&self) -> Gpwe20R { - Gpwe20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&self) -> Gpwe21R { - Gpwe21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&self) -> Gpwe22R { - Gpwe22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&self) -> Gpwe23R { - Gpwe23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&self) -> Gpwe24R { - Gpwe24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&self) -> Gpwe25R { - Gpwe25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&self) -> Gpwe26R { - Gpwe26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&self) -> Gpwe27R { - Gpwe27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&self) -> Gpwe28R { - Gpwe28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&self) -> Gpwe29R { - Gpwe29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&self) -> Gpwe30R { - Gpwe30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&self) -> Gpwe31R { - Gpwe31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&mut self) -> Gpwe16W { - Gpwe16W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&mut self) -> Gpwe17W { - Gpwe17W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&mut self) -> Gpwe18W { - Gpwe18W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&mut self) -> Gpwe19W { - Gpwe19W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&mut self) -> Gpwe20W { - Gpwe20W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&mut self) -> Gpwe21W { - Gpwe21W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&mut self) -> Gpwe22W { - Gpwe22W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&mut self) -> Gpwe23W { - Gpwe23W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&mut self) -> Gpwe24W { - Gpwe24W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&mut self) -> Gpwe25W { - Gpwe25W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&mut self) -> Gpwe26W { - Gpwe26W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&mut self) -> Gpwe27W { - Gpwe27W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&mut self) -> Gpwe28W { - Gpwe28W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&mut self) -> Gpwe29W { - Gpwe29W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&mut self) -> Gpwe30W { - Gpwe30W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&mut self) -> Gpwe31W { - Gpwe31W::new(self, 31) - } -} -#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpchrSpec; -impl crate::RegisterSpec for GpchrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] -impl crate::Readable for GpchrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] -impl crate::Writable for GpchrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCHR to value 0"] -impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port0/gpclr.rs b/mcxa276-pac/src/port0/gpclr.rs deleted file mode 100644 index 21e5ff23d..000000000 --- a/mcxa276-pac/src/port0/gpclr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCLR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCLR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe0 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] -pub type Gpwe0R = crate::BitReader; -impl Gpwe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe0 { - match self.bits { - false => Gpwe0::Gpwe0, - true => Gpwe0::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe0::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe0::Gpwe1 - } -} -#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] -pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; -impl<'a, REG> Gpwe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe1 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] -pub type Gpwe1R = crate::BitReader; -impl Gpwe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe1 { - match self.bits { - false => Gpwe1::Gpwe0, - true => Gpwe1::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe1::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe1::Gpwe1 - } -} -#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] -pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; -impl<'a, REG> Gpwe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe2 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] -pub type Gpwe2R = crate::BitReader; -impl Gpwe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe2 { - match self.bits { - false => Gpwe2::Gpwe0, - true => Gpwe2::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe2::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe2::Gpwe1 - } -} -#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] -pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; -impl<'a, REG> Gpwe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe3 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] -pub type Gpwe3R = crate::BitReader; -impl Gpwe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe3 { - match self.bits { - false => Gpwe3::Gpwe0, - true => Gpwe3::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe3::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe3::Gpwe1 - } -} -#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] -pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; -impl<'a, REG> Gpwe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe4 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] -pub type Gpwe4R = crate::BitReader; -impl Gpwe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe4 { - match self.bits { - false => Gpwe4::Gpwe0, - true => Gpwe4::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe4::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe4::Gpwe1 - } -} -#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] -pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; -impl<'a, REG> Gpwe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe5 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] -pub type Gpwe5R = crate::BitReader; -impl Gpwe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe5 { - match self.bits { - false => Gpwe5::Gpwe0, - true => Gpwe5::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe5::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe5::Gpwe1 - } -} -#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] -pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; -impl<'a, REG> Gpwe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe6 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] -pub type Gpwe6R = crate::BitReader; -impl Gpwe6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe6 { - match self.bits { - false => Gpwe6::Gpwe0, - true => Gpwe6::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe6::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe6::Gpwe1 - } -} -#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] -pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; -impl<'a, REG> Gpwe6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe7 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] -pub type Gpwe7R = crate::BitReader; -impl Gpwe7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe7 { - match self.bits { - false => Gpwe7::Gpwe0, - true => Gpwe7::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe7::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe7::Gpwe1 - } -} -#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] -pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; -impl<'a, REG> Gpwe7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe8 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] -pub type Gpwe8R = crate::BitReader; -impl Gpwe8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe8 { - match self.bits { - false => Gpwe8::Gpwe0, - true => Gpwe8::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe8::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe8::Gpwe1 - } -} -#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] -pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; -impl<'a, REG> Gpwe8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe9 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] -pub type Gpwe9R = crate::BitReader; -impl Gpwe9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe9 { - match self.bits { - false => Gpwe9::Gpwe0, - true => Gpwe9::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe9::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe9::Gpwe1 - } -} -#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] -pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; -impl<'a, REG> Gpwe9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe10 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] -pub type Gpwe10R = crate::BitReader; -impl Gpwe10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe10 { - match self.bits { - false => Gpwe10::Gpwe0, - true => Gpwe10::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe10::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe10::Gpwe1 - } -} -#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] -pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; -impl<'a, REG> Gpwe10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe11 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] -pub type Gpwe11R = crate::BitReader; -impl Gpwe11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe11 { - match self.bits { - false => Gpwe11::Gpwe0, - true => Gpwe11::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe11::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe11::Gpwe1 - } -} -#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] -pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; -impl<'a, REG> Gpwe11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe12 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] -pub type Gpwe12R = crate::BitReader; -impl Gpwe12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe12 { - match self.bits { - false => Gpwe12::Gpwe0, - true => Gpwe12::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe12::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe12::Gpwe1 - } -} -#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] -pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; -impl<'a, REG> Gpwe12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe13 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] -pub type Gpwe13R = crate::BitReader; -impl Gpwe13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe13 { - match self.bits { - false => Gpwe13::Gpwe0, - true => Gpwe13::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe13::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe13::Gpwe1 - } -} -#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] -pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; -impl<'a, REG> Gpwe13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe14 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] -pub type Gpwe14R = crate::BitReader; -impl Gpwe14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe14 { - match self.bits { - false => Gpwe14::Gpwe0, - true => Gpwe14::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe14::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe14::Gpwe1 - } -} -#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] -pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; -impl<'a, REG> Gpwe14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe15 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] -pub type Gpwe15R = crate::BitReader; -impl Gpwe15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe15 { - match self.bits { - false => Gpwe15::Gpwe0, - true => Gpwe15::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe15::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe15::Gpwe1 - } -} -#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] -pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; -impl<'a, REG> Gpwe15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&self) -> Gpwe0R { - Gpwe0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&self) -> Gpwe1R { - Gpwe1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&self) -> Gpwe2R { - Gpwe2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&self) -> Gpwe3R { - Gpwe3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&self) -> Gpwe4R { - Gpwe4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&self) -> Gpwe5R { - Gpwe5R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&self) -> Gpwe6R { - Gpwe6R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&self) -> Gpwe7R { - Gpwe7R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&self) -> Gpwe8R { - Gpwe8R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&self) -> Gpwe9R { - Gpwe9R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&self) -> Gpwe10R { - Gpwe10R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&self) -> Gpwe11R { - Gpwe11R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&self) -> Gpwe12R { - Gpwe12R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&self) -> Gpwe13R { - Gpwe13R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&self) -> Gpwe14R { - Gpwe14R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&self) -> Gpwe15R { - Gpwe15R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&mut self) -> Gpwe0W { - Gpwe0W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&mut self) -> Gpwe1W { - Gpwe1W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&mut self) -> Gpwe2W { - Gpwe2W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&mut self) -> Gpwe3W { - Gpwe3W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&mut self) -> Gpwe4W { - Gpwe4W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&mut self) -> Gpwe5W { - Gpwe5W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&mut self) -> Gpwe6W { - Gpwe6W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&mut self) -> Gpwe7W { - Gpwe7W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&mut self) -> Gpwe8W { - Gpwe8W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&mut self) -> Gpwe9W { - Gpwe9W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&mut self) -> Gpwe10W { - Gpwe10W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&mut self) -> Gpwe11W { - Gpwe11W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&mut self) -> Gpwe12W { - Gpwe12W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&mut self) -> Gpwe13W { - Gpwe13W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&mut self) -> Gpwe14W { - Gpwe14W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&mut self) -> Gpwe15W { - Gpwe15W::new(self, 31) - } -} -#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpclrSpec; -impl crate::RegisterSpec for GpclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] -impl crate::Readable for GpclrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] -impl crate::Writable for GpclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCLR to value 0"] -impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port0/pcr0.rs b/mcxa276-pac/src/port0/pcr0.rs deleted file mode 100644 index 59f37ae97..000000000 --- a/mcxa276-pac/src/port0/pcr0.rs +++ /dev/null @@ -1,675 +0,0 @@ -#[doc = "Register `PCR0` reader"] -pub type R = crate::R; -#[doc = "Register `PCR0` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr0Spec; -impl crate::RegisterSpec for Pcr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] -impl crate::Readable for Pcr0Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] -impl crate::Writable for Pcr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR0 to value 0x1143"] -impl crate::Resettable for Pcr0Spec { - const RESET_VALUE: u32 = 0x1143; -} diff --git a/mcxa276-pac/src/port0/pcr1.rs b/mcxa276-pac/src/port0/pcr1.rs deleted file mode 100644 index f63d93430..000000000 --- a/mcxa276-pac/src/port0/pcr1.rs +++ /dev/null @@ -1,675 +0,0 @@ -#[doc = "Register `PCR1` reader"] -pub type R = crate::R; -#[doc = "Register `PCR1` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr1Spec; -impl crate::RegisterSpec for Pcr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] -impl crate::Readable for Pcr1Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] -impl crate::Writable for Pcr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR1 to value 0x1102"] -impl crate::Resettable for Pcr1Spec { - const RESET_VALUE: u32 = 0x1102; -} diff --git a/mcxa276-pac/src/port0/pcr10.rs b/mcxa276-pac/src/port0/pcr10.rs deleted file mode 100644 index 9a358f658..000000000 --- a/mcxa276-pac/src/port0/pcr10.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR10` reader"] -pub type R = crate::R; -#[doc = "Register `PCR10` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr10Spec; -impl crate::RegisterSpec for Pcr10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] -impl crate::Readable for Pcr10Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] -impl crate::Writable for Pcr10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR10 to value 0"] -impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port0/pcr11.rs b/mcxa276-pac/src/port0/pcr11.rs deleted file mode 100644 index 7b809b651..000000000 --- a/mcxa276-pac/src/port0/pcr11.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR11` reader"] -pub type R = crate::R; -#[doc = "Register `PCR11` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr11Spec; -impl crate::RegisterSpec for Pcr11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] -impl crate::Readable for Pcr11Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] -impl crate::Writable for Pcr11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR11 to value 0"] -impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port0/pcr12.rs b/mcxa276-pac/src/port0/pcr12.rs deleted file mode 100644 index 2cd7eecc1..000000000 --- a/mcxa276-pac/src/port0/pcr12.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR12` reader"] -pub type R = crate::R; -#[doc = "Register `PCR12` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr12Spec; -impl crate::RegisterSpec for Pcr12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] -impl crate::Readable for Pcr12Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] -impl crate::Writable for Pcr12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR12 to value 0"] -impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port0/pcr13.rs b/mcxa276-pac/src/port0/pcr13.rs deleted file mode 100644 index 0da9c8d55..000000000 --- a/mcxa276-pac/src/port0/pcr13.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR13` reader"] -pub type R = crate::R; -#[doc = "Register `PCR13` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr13Spec; -impl crate::RegisterSpec for Pcr13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] -impl crate::Readable for Pcr13Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] -impl crate::Writable for Pcr13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR13 to value 0"] -impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port0/pcr14.rs b/mcxa276-pac/src/port0/pcr14.rs deleted file mode 100644 index 553559b3f..000000000 --- a/mcxa276-pac/src/port0/pcr14.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR14` reader"] -pub type R = crate::R; -#[doc = "Register `PCR14` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr14Spec; -impl crate::RegisterSpec for Pcr14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] -impl crate::Readable for Pcr14Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] -impl crate::Writable for Pcr14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR14 to value 0"] -impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port0/pcr15.rs b/mcxa276-pac/src/port0/pcr15.rs deleted file mode 100644 index 85c188f6b..000000000 --- a/mcxa276-pac/src/port0/pcr15.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR15` reader"] -pub type R = crate::R; -#[doc = "Register `PCR15` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr15Spec; -impl crate::RegisterSpec for Pcr15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] -impl crate::Readable for Pcr15Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] -impl crate::Writable for Pcr15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR15 to value 0"] -impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port0/pcr16.rs b/mcxa276-pac/src/port0/pcr16.rs deleted file mode 100644 index 7ee22ee99..000000000 --- a/mcxa276-pac/src/port0/pcr16.rs +++ /dev/null @@ -1,940 +0,0 @@ -#[doc = "Register `PCR16` reader"] -pub type R = crate::R; -#[doc = "Register `PCR16` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr16Spec; -impl crate::RegisterSpec for Pcr16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] -impl crate::Readable for Pcr16Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] -impl crate::Writable for Pcr16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR16 to value 0"] -impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port0/pcr17.rs b/mcxa276-pac/src/port0/pcr17.rs deleted file mode 100644 index 4e9b5f619..000000000 --- a/mcxa276-pac/src/port0/pcr17.rs +++ /dev/null @@ -1,877 +0,0 @@ -#[doc = "Register `PCR17` reader"] -pub type R = crate::R; -#[doc = "Register `PCR17` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr17Spec; -impl crate::RegisterSpec for Pcr17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] -impl crate::Readable for Pcr17Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] -impl crate::Writable for Pcr17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR17 to value 0"] -impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port0/pcr18.rs b/mcxa276-pac/src/port0/pcr18.rs deleted file mode 100644 index b87bafe1a..000000000 --- a/mcxa276-pac/src/port0/pcr18.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR18` reader"] -pub type R = crate::R; -#[doc = "Register `PCR18` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr18Spec; -impl crate::RegisterSpec for Pcr18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] -impl crate::Readable for Pcr18Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] -impl crate::Writable for Pcr18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR18 to value 0"] -impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port0/pcr19.rs b/mcxa276-pac/src/port0/pcr19.rs deleted file mode 100644 index cd55e9cfd..000000000 --- a/mcxa276-pac/src/port0/pcr19.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR19` reader"] -pub type R = crate::R; -#[doc = "Register `PCR19` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr19Spec; -impl crate::RegisterSpec for Pcr19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] -impl crate::Readable for Pcr19Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] -impl crate::Writable for Pcr19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR19 to value 0"] -impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port0/pcr2.rs b/mcxa276-pac/src/port0/pcr2.rs deleted file mode 100644 index dd5c28418..000000000 --- a/mcxa276-pac/src/port0/pcr2.rs +++ /dev/null @@ -1,753 +0,0 @@ -#[doc = "Register `PCR2` reader"] -pub type R = crate::R; -#[doc = "Register `PCR2` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr2Spec; -impl crate::RegisterSpec for Pcr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] -impl crate::Readable for Pcr2Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] -impl crate::Writable for Pcr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR2 to value 0x1140"] -impl crate::Resettable for Pcr2Spec { - const RESET_VALUE: u32 = 0x1140; -} diff --git a/mcxa276-pac/src/port0/pcr20.rs b/mcxa276-pac/src/port0/pcr20.rs deleted file mode 100644 index 20401202b..000000000 --- a/mcxa276-pac/src/port0/pcr20.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR20` reader"] -pub type R = crate::R; -#[doc = "Register `PCR20` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr20Spec; -impl crate::RegisterSpec for Pcr20Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] -impl crate::Readable for Pcr20Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] -impl crate::Writable for Pcr20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR20 to value 0"] -impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port0/pcr21.rs b/mcxa276-pac/src/port0/pcr21.rs deleted file mode 100644 index 9f6076615..000000000 --- a/mcxa276-pac/src/port0/pcr21.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR21` reader"] -pub type R = crate::R; -#[doc = "Register `PCR21` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr21Spec; -impl crate::RegisterSpec for Pcr21Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] -impl crate::Readable for Pcr21Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] -impl crate::Writable for Pcr21Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR21 to value 0"] -impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port0/pcr22.rs b/mcxa276-pac/src/port0/pcr22.rs deleted file mode 100644 index decbc02c0..000000000 --- a/mcxa276-pac/src/port0/pcr22.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR22` reader"] -pub type R = crate::R; -#[doc = "Register `PCR22` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr22Spec; -impl crate::RegisterSpec for Pcr22Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] -impl crate::Readable for Pcr22Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] -impl crate::Writable for Pcr22Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR22 to value 0"] -impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port0/pcr23.rs b/mcxa276-pac/src/port0/pcr23.rs deleted file mode 100644 index 640773d73..000000000 --- a/mcxa276-pac/src/port0/pcr23.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR23` reader"] -pub type R = crate::R; -#[doc = "Register `PCR23` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr23Spec; -impl crate::RegisterSpec for Pcr23Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] -impl crate::Readable for Pcr23Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] -impl crate::Writable for Pcr23Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR23 to value 0"] -impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port0/pcr24.rs b/mcxa276-pac/src/port0/pcr24.rs deleted file mode 100644 index fe34d2b88..000000000 --- a/mcxa276-pac/src/port0/pcr24.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR24` reader"] -pub type R = crate::R; -#[doc = "Register `PCR24` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr24Spec; -impl crate::RegisterSpec for Pcr24Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] -impl crate::Readable for Pcr24Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] -impl crate::Writable for Pcr24Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR24 to value 0"] -impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port0/pcr25.rs b/mcxa276-pac/src/port0/pcr25.rs deleted file mode 100644 index 5486437a9..000000000 --- a/mcxa276-pac/src/port0/pcr25.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR25` reader"] -pub type R = crate::R; -#[doc = "Register `PCR25` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr25Spec; -impl crate::RegisterSpec for Pcr25Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] -impl crate::Readable for Pcr25Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] -impl crate::Writable for Pcr25Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR25 to value 0"] -impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port0/pcr26.rs b/mcxa276-pac/src/port0/pcr26.rs deleted file mode 100644 index fb601b77c..000000000 --- a/mcxa276-pac/src/port0/pcr26.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR26` reader"] -pub type R = crate::R; -#[doc = "Register `PCR26` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr26Spec; -impl crate::RegisterSpec for Pcr26Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] -impl crate::Readable for Pcr26Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] -impl crate::Writable for Pcr26Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR26 to value 0"] -impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port0/pcr27.rs b/mcxa276-pac/src/port0/pcr27.rs deleted file mode 100644 index e53d72f87..000000000 --- a/mcxa276-pac/src/port0/pcr27.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR27` reader"] -pub type R = crate::R; -#[doc = "Register `PCR27` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr27Spec; -impl crate::RegisterSpec for Pcr27Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] -impl crate::Readable for Pcr27Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] -impl crate::Writable for Pcr27Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR27 to value 0"] -impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port0/pcr28.rs b/mcxa276-pac/src/port0/pcr28.rs deleted file mode 100644 index 1315078be..000000000 --- a/mcxa276-pac/src/port0/pcr28.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR28` reader"] -pub type R = crate::R; -#[doc = "Register `PCR28` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr28Spec; -impl crate::RegisterSpec for Pcr28Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] -impl crate::Readable for Pcr28Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] -impl crate::Writable for Pcr28Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR28 to value 0"] -impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port0/pcr29.rs b/mcxa276-pac/src/port0/pcr29.rs deleted file mode 100644 index de7c41baa..000000000 --- a/mcxa276-pac/src/port0/pcr29.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR29` reader"] -pub type R = crate::R; -#[doc = "Register `PCR29` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr29Spec; -impl crate::RegisterSpec for Pcr29Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] -impl crate::Readable for Pcr29Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] -impl crate::Writable for Pcr29Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR29 to value 0"] -impl crate::Resettable for Pcr29Spec {} diff --git a/mcxa276-pac/src/port0/pcr3.rs b/mcxa276-pac/src/port0/pcr3.rs deleted file mode 100644 index 762b324a4..000000000 --- a/mcxa276-pac/src/port0/pcr3.rs +++ /dev/null @@ -1,753 +0,0 @@ -#[doc = "Register `PCR3` reader"] -pub type R = crate::R; -#[doc = "Register `PCR3` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr3Spec; -impl crate::RegisterSpec for Pcr3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] -impl crate::Readable for Pcr3Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] -impl crate::Writable for Pcr3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR3 to value 0x1103"] -impl crate::Resettable for Pcr3Spec { - const RESET_VALUE: u32 = 0x1103; -} diff --git a/mcxa276-pac/src/port0/pcr30.rs b/mcxa276-pac/src/port0/pcr30.rs deleted file mode 100644 index cce4166f4..000000000 --- a/mcxa276-pac/src/port0/pcr30.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR30` reader"] -pub type R = crate::R; -#[doc = "Register `PCR30` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr30Spec; -impl crate::RegisterSpec for Pcr30Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] -impl crate::Readable for Pcr30Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] -impl crate::Writable for Pcr30Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR30 to value 0"] -impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port0/pcr31.rs b/mcxa276-pac/src/port0/pcr31.rs deleted file mode 100644 index 1f49159c2..000000000 --- a/mcxa276-pac/src/port0/pcr31.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR31` reader"] -pub type R = crate::R; -#[doc = "Register `PCR31` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr31Spec; -impl crate::RegisterSpec for Pcr31Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] -impl crate::Readable for Pcr31Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] -impl crate::Writable for Pcr31Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR31 to value 0"] -impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port0/pcr4.rs b/mcxa276-pac/src/port0/pcr4.rs deleted file mode 100644 index 9890bb2d4..000000000 --- a/mcxa276-pac/src/port0/pcr4.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR4` reader"] -pub type R = crate::R; -#[doc = "Register `PCR4` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr4Spec; -impl crate::RegisterSpec for Pcr4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] -impl crate::Readable for Pcr4Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] -impl crate::Writable for Pcr4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR4 to value 0"] -impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port0/pcr5.rs b/mcxa276-pac/src/port0/pcr5.rs deleted file mode 100644 index bbc9bfc8a..000000000 --- a/mcxa276-pac/src/port0/pcr5.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR5` reader"] -pub type R = crate::R; -#[doc = "Register `PCR5` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr5Spec; -impl crate::RegisterSpec for Pcr5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] -impl crate::Readable for Pcr5Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] -impl crate::Writable for Pcr5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR5 to value 0"] -impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port0/pcr6.rs b/mcxa276-pac/src/port0/pcr6.rs deleted file mode 100644 index 529346a2c..000000000 --- a/mcxa276-pac/src/port0/pcr6.rs +++ /dev/null @@ -1,753 +0,0 @@ -#[doc = "Register `PCR6` reader"] -pub type R = crate::R; -#[doc = "Register `PCR6` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr6Spec; -impl crate::RegisterSpec for Pcr6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] -impl crate::Readable for Pcr6Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] -impl crate::Writable for Pcr6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR6 to value 0x1103"] -impl crate::Resettable for Pcr6Spec { - const RESET_VALUE: u32 = 0x1103; -} diff --git a/mcxa276-pac/src/port0/pcr7.rs b/mcxa276-pac/src/port0/pcr7.rs deleted file mode 100644 index 18e6a4872..000000000 --- a/mcxa276-pac/src/port0/pcr7.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR7` reader"] -pub type R = crate::R; -#[doc = "Register `PCR7` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr7Spec; -impl crate::RegisterSpec for Pcr7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] -impl crate::Readable for Pcr7Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] -impl crate::Writable for Pcr7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR7 to value 0"] -impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port0/pcr8.rs b/mcxa276-pac/src/port0/pcr8.rs deleted file mode 100644 index 8c6d7289b..000000000 --- a/mcxa276-pac/src/port0/pcr8.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR8` reader"] -pub type R = crate::R; -#[doc = "Register `PCR8` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr8Spec; -impl crate::RegisterSpec for Pcr8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] -impl crate::Readable for Pcr8Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] -impl crate::Writable for Pcr8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR8 to value 0"] -impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port0/pcr9.rs b/mcxa276-pac/src/port0/pcr9.rs deleted file mode 100644 index 403e7e331..000000000 --- a/mcxa276-pac/src/port0/pcr9.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR9` reader"] -pub type R = crate::R; -#[doc = "Register `PCR9` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr9Spec; -impl crate::RegisterSpec for Pcr9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] -impl crate::Readable for Pcr9Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] -impl crate::Writable for Pcr9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR9 to value 0"] -impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port0/verid.rs b/mcxa276-pac/src/port0/verid.rs deleted file mode 100644 index 330f53d57..000000000 --- a/mcxa276-pac/src/port0/verid.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Basic implementation"] - Feature0 = 0, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Feature0), - _ => None, - } - } - #[doc = "Basic implementation"] - #[inline(always)] - pub fn is_feature0(&self) -> bool { - *self == Feature::Feature0 - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0200_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0200_0000; -} diff --git a/mcxa276-pac/src/port1.rs b/mcxa276-pac/src/port1.rs deleted file mode 100644 index d7ed05fc0..000000000 --- a/mcxa276-pac/src/port1.rs +++ /dev/null @@ -1,428 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x0c], - gpclr: Gpclr, - gpchr: Gpchr, - _reserved3: [u8; 0x08], - config: Config, - _reserved4: [u8; 0x3c], - calib0: Calib0, - calib1: Calib1, - _reserved6: [u8; 0x18], - pcr0: Pcr0, - pcr1: Pcr1, - pcr2: Pcr2, - pcr3: Pcr3, - pcr4: Pcr4, - pcr5: Pcr5, - pcr6: Pcr6, - pcr7: Pcr7, - pcr8: Pcr8, - pcr9: Pcr9, - pcr10: Pcr10, - pcr11: Pcr11, - pcr12: Pcr12, - pcr13: Pcr13, - pcr14: Pcr14, - pcr15: Pcr15, - pcr16: Pcr16, - pcr17: Pcr17, - pcr18: Pcr18, - pcr19: Pcr19, - pcr20: Pcr20, - pcr21: Pcr21, - pcr22: Pcr22, - pcr23: Pcr23, - pcr24: Pcr24, - pcr25: Pcr25, - pcr26: Pcr26, - pcr27: Pcr27, - pcr28: Pcr28, - pcr29: Pcr29, - pcr30: Pcr30, - pcr31: Pcr31, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x10 - Global Pin Control Low"] - #[inline(always)] - pub const fn gpclr(&self) -> &Gpclr { - &self.gpclr - } - #[doc = "0x14 - Global Pin Control High"] - #[inline(always)] - pub const fn gpchr(&self) -> &Gpchr { - &self.gpchr - } - #[doc = "0x20 - Configuration"] - #[inline(always)] - pub const fn config(&self) -> &Config { - &self.config - } - #[doc = "0x60 - Calibration 0"] - #[inline(always)] - pub const fn calib0(&self) -> &Calib0 { - &self.calib0 - } - #[doc = "0x64 - Calibration 1"] - #[inline(always)] - pub const fn calib1(&self) -> &Calib1 { - &self.calib1 - } - #[doc = "0x80 - Pin Control 0"] - #[inline(always)] - pub const fn pcr0(&self) -> &Pcr0 { - &self.pcr0 - } - #[doc = "0x84 - Pin Control 1"] - #[inline(always)] - pub const fn pcr1(&self) -> &Pcr1 { - &self.pcr1 - } - #[doc = "0x88 - Pin Control 2"] - #[inline(always)] - pub const fn pcr2(&self) -> &Pcr2 { - &self.pcr2 - } - #[doc = "0x8c - Pin Control 3"] - #[inline(always)] - pub const fn pcr3(&self) -> &Pcr3 { - &self.pcr3 - } - #[doc = "0x90 - Pin Control 4"] - #[inline(always)] - pub const fn pcr4(&self) -> &Pcr4 { - &self.pcr4 - } - #[doc = "0x94 - Pin Control 5"] - #[inline(always)] - pub const fn pcr5(&self) -> &Pcr5 { - &self.pcr5 - } - #[doc = "0x98 - Pin Control 6"] - #[inline(always)] - pub const fn pcr6(&self) -> &Pcr6 { - &self.pcr6 - } - #[doc = "0x9c - Pin Control 7"] - #[inline(always)] - pub const fn pcr7(&self) -> &Pcr7 { - &self.pcr7 - } - #[doc = "0xa0 - Pin Control 8"] - #[inline(always)] - pub const fn pcr8(&self) -> &Pcr8 { - &self.pcr8 - } - #[doc = "0xa4 - Pin Control 9"] - #[inline(always)] - pub const fn pcr9(&self) -> &Pcr9 { - &self.pcr9 - } - #[doc = "0xa8 - Pin Control 10"] - #[inline(always)] - pub const fn pcr10(&self) -> &Pcr10 { - &self.pcr10 - } - #[doc = "0xac - Pin Control 11"] - #[inline(always)] - pub const fn pcr11(&self) -> &Pcr11 { - &self.pcr11 - } - #[doc = "0xb0 - Pin Control 12"] - #[inline(always)] - pub const fn pcr12(&self) -> &Pcr12 { - &self.pcr12 - } - #[doc = "0xb4 - Pin Control 13"] - #[inline(always)] - pub const fn pcr13(&self) -> &Pcr13 { - &self.pcr13 - } - #[doc = "0xb8 - Pin Control 14"] - #[inline(always)] - pub const fn pcr14(&self) -> &Pcr14 { - &self.pcr14 - } - #[doc = "0xbc - Pin Control 15"] - #[inline(always)] - pub const fn pcr15(&self) -> &Pcr15 { - &self.pcr15 - } - #[doc = "0xc0 - Pin Control 16"] - #[inline(always)] - pub const fn pcr16(&self) -> &Pcr16 { - &self.pcr16 - } - #[doc = "0xc4 - Pin Control 17"] - #[inline(always)] - pub const fn pcr17(&self) -> &Pcr17 { - &self.pcr17 - } - #[doc = "0xc8 - Pin Control 18"] - #[inline(always)] - pub const fn pcr18(&self) -> &Pcr18 { - &self.pcr18 - } - #[doc = "0xcc - Pin Control 19"] - #[inline(always)] - pub const fn pcr19(&self) -> &Pcr19 { - &self.pcr19 - } - #[doc = "0xd0 - Pin Control 20"] - #[inline(always)] - pub const fn pcr20(&self) -> &Pcr20 { - &self.pcr20 - } - #[doc = "0xd4 - Pin Control 21"] - #[inline(always)] - pub const fn pcr21(&self) -> &Pcr21 { - &self.pcr21 - } - #[doc = "0xd8 - Pin Control 22"] - #[inline(always)] - pub const fn pcr22(&self) -> &Pcr22 { - &self.pcr22 - } - #[doc = "0xdc - Pin Control 23"] - #[inline(always)] - pub const fn pcr23(&self) -> &Pcr23 { - &self.pcr23 - } - #[doc = "0xe0 - Pin Control 24"] - #[inline(always)] - pub const fn pcr24(&self) -> &Pcr24 { - &self.pcr24 - } - #[doc = "0xe4 - Pin Control 25"] - #[inline(always)] - pub const fn pcr25(&self) -> &Pcr25 { - &self.pcr25 - } - #[doc = "0xe8 - Pin Control 26"] - #[inline(always)] - pub const fn pcr26(&self) -> &Pcr26 { - &self.pcr26 - } - #[doc = "0xec - Pin Control 27"] - #[inline(always)] - pub const fn pcr27(&self) -> &Pcr27 { - &self.pcr27 - } - #[doc = "0xf0 - Pin Control 28"] - #[inline(always)] - pub const fn pcr28(&self) -> &Pcr28 { - &self.pcr28 - } - #[doc = "0xf4 - Pin Control 29"] - #[inline(always)] - pub const fn pcr29(&self) -> &Pcr29 { - &self.pcr29 - } - #[doc = "0xf8 - Pin Control 30"] - #[inline(always)] - pub const fn pcr30(&self) -> &Pcr30 { - &self.pcr30 - } - #[doc = "0xfc - Pin Control 31"] - #[inline(always)] - pub const fn pcr31(&self) -> &Pcr31 { - &self.pcr31 - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] -#[doc(alias = "GPCLR")] -pub type Gpclr = crate::Reg; -#[doc = "Global Pin Control Low"] -pub mod gpclr; -#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] -#[doc(alias = "GPCHR")] -pub type Gpchr = crate::Reg; -#[doc = "Global Pin Control High"] -pub mod gpchr; -#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] -#[doc(alias = "CONFIG")] -pub type Config = crate::Reg; -#[doc = "Configuration"] -pub mod config; -#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] -#[doc(alias = "CALIB0")] -pub type Calib0 = crate::Reg; -#[doc = "Calibration 0"] -pub mod calib0; -#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] -#[doc(alias = "CALIB1")] -pub type Calib1 = crate::Reg; -#[doc = "Calibration 1"] -pub mod calib1; -#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] -#[doc(alias = "PCR0")] -pub type Pcr0 = crate::Reg; -#[doc = "Pin Control 0"] -pub mod pcr0; -#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] -#[doc(alias = "PCR1")] -pub type Pcr1 = crate::Reg; -#[doc = "Pin Control 1"] -pub mod pcr1; -#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] -#[doc(alias = "PCR2")] -pub type Pcr2 = crate::Reg; -#[doc = "Pin Control 2"] -pub mod pcr2; -#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] -#[doc(alias = "PCR3")] -pub type Pcr3 = crate::Reg; -#[doc = "Pin Control 3"] -pub mod pcr3; -#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] -#[doc(alias = "PCR4")] -pub type Pcr4 = crate::Reg; -#[doc = "Pin Control 4"] -pub mod pcr4; -#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] -#[doc(alias = "PCR5")] -pub type Pcr5 = crate::Reg; -#[doc = "Pin Control 5"] -pub mod pcr5; -#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] -#[doc(alias = "PCR6")] -pub type Pcr6 = crate::Reg; -#[doc = "Pin Control 6"] -pub mod pcr6; -#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] -#[doc(alias = "PCR7")] -pub type Pcr7 = crate::Reg; -#[doc = "Pin Control 7"] -pub mod pcr7; -#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] -#[doc(alias = "PCR8")] -pub type Pcr8 = crate::Reg; -#[doc = "Pin Control 8"] -pub mod pcr8; -#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] -#[doc(alias = "PCR9")] -pub type Pcr9 = crate::Reg; -#[doc = "Pin Control 9"] -pub mod pcr9; -#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] -#[doc(alias = "PCR10")] -pub type Pcr10 = crate::Reg; -#[doc = "Pin Control 10"] -pub mod pcr10; -#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] -#[doc(alias = "PCR11")] -pub type Pcr11 = crate::Reg; -#[doc = "Pin Control 11"] -pub mod pcr11; -#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] -#[doc(alias = "PCR12")] -pub type Pcr12 = crate::Reg; -#[doc = "Pin Control 12"] -pub mod pcr12; -#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] -#[doc(alias = "PCR13")] -pub type Pcr13 = crate::Reg; -#[doc = "Pin Control 13"] -pub mod pcr13; -#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] -#[doc(alias = "PCR14")] -pub type Pcr14 = crate::Reg; -#[doc = "Pin Control 14"] -pub mod pcr14; -#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] -#[doc(alias = "PCR15")] -pub type Pcr15 = crate::Reg; -#[doc = "Pin Control 15"] -pub mod pcr15; -#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] -#[doc(alias = "PCR16")] -pub type Pcr16 = crate::Reg; -#[doc = "Pin Control 16"] -pub mod pcr16; -#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] -#[doc(alias = "PCR17")] -pub type Pcr17 = crate::Reg; -#[doc = "Pin Control 17"] -pub mod pcr17; -#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] -#[doc(alias = "PCR18")] -pub type Pcr18 = crate::Reg; -#[doc = "Pin Control 18"] -pub mod pcr18; -#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] -#[doc(alias = "PCR19")] -pub type Pcr19 = crate::Reg; -#[doc = "Pin Control 19"] -pub mod pcr19; -#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] -#[doc(alias = "PCR20")] -pub type Pcr20 = crate::Reg; -#[doc = "Pin Control 20"] -pub mod pcr20; -#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] -#[doc(alias = "PCR21")] -pub type Pcr21 = crate::Reg; -#[doc = "Pin Control 21"] -pub mod pcr21; -#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] -#[doc(alias = "PCR22")] -pub type Pcr22 = crate::Reg; -#[doc = "Pin Control 22"] -pub mod pcr22; -#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] -#[doc(alias = "PCR23")] -pub type Pcr23 = crate::Reg; -#[doc = "Pin Control 23"] -pub mod pcr23; -#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] -#[doc(alias = "PCR24")] -pub type Pcr24 = crate::Reg; -#[doc = "Pin Control 24"] -pub mod pcr24; -#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] -#[doc(alias = "PCR25")] -pub type Pcr25 = crate::Reg; -#[doc = "Pin Control 25"] -pub mod pcr25; -#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] -#[doc(alias = "PCR26")] -pub type Pcr26 = crate::Reg; -#[doc = "Pin Control 26"] -pub mod pcr26; -#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] -#[doc(alias = "PCR27")] -pub type Pcr27 = crate::Reg; -#[doc = "Pin Control 27"] -pub mod pcr27; -#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] -#[doc(alias = "PCR28")] -pub type Pcr28 = crate::Reg; -#[doc = "Pin Control 28"] -pub mod pcr28; -#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] -#[doc(alias = "PCR29")] -pub type Pcr29 = crate::Reg; -#[doc = "Pin Control 29"] -pub mod pcr29; -#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] -#[doc(alias = "PCR30")] -pub type Pcr30 = crate::Reg; -#[doc = "Pin Control 30"] -pub mod pcr30; -#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] -#[doc(alias = "PCR31")] -pub type Pcr31 = crate::Reg; -#[doc = "Pin Control 31"] -pub mod pcr31; diff --git a/mcxa276-pac/src/port1/calib0.rs b/mcxa276-pac/src/port1/calib0.rs deleted file mode 100644 index 029fa12f3..000000000 --- a/mcxa276-pac/src/port1/calib0.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB0` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB0` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib0Spec; -impl crate::RegisterSpec for Calib0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] -impl crate::Readable for Calib0Spec {} -#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] -impl crate::Writable for Calib0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB0 to value 0"] -impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port1/calib1.rs b/mcxa276-pac/src/port1/calib1.rs deleted file mode 100644 index e18f61234..000000000 --- a/mcxa276-pac/src/port1/calib1.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB1` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB1` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib1Spec; -impl crate::RegisterSpec for Calib1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] -impl crate::Readable for Calib1Spec {} -#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] -impl crate::Writable for Calib1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB1 to value 0"] -impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port1/config.rs b/mcxa276-pac/src/port1/config.rs deleted file mode 100644 index da92c5b27..000000000 --- a/mcxa276-pac/src/port1/config.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `CONFIG` reader"] -pub type R = crate::R; -#[doc = "Register `CONFIG` writer"] -pub type W = crate::W; -#[doc = "Port Voltage Range\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Range { - #[doc = "0: 1.71 V-3.6 V"] - Range0 = 0, - #[doc = "1: 2.70 V-3.6 V"] - Range1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Range) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RANGE` reader - Port Voltage Range"] -pub type RangeR = crate::BitReader; -impl RangeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Range { - match self.bits { - false => Range::Range0, - true => Range::Range1, - } - } - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn is_range0(&self) -> bool { - *self == Range::Range0 - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn is_range1(&self) -> bool { - *self == Range::Range1 - } -} -#[doc = "Field `RANGE` writer - Port Voltage Range"] -pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; -impl<'a, REG> RangeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn range0(self) -> &'a mut crate::W { - self.variant(Range::Range0) - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn range1(self) -> &'a mut crate::W { - self.variant(Range::Range1) - } -} -impl R { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&self) -> RangeR { - RangeR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&mut self) -> RangeW { - RangeW::new(self, 0) - } -} -#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ConfigSpec; -impl crate::RegisterSpec for ConfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`config::R`](R) reader structure"] -impl crate::Readable for ConfigSpec {} -#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] -impl crate::Writable for ConfigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CONFIG to value 0"] -impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port1/gpchr.rs b/mcxa276-pac/src/port1/gpchr.rs deleted file mode 100644 index af92d0d62..000000000 --- a/mcxa276-pac/src/port1/gpchr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCHR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCHR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe16 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] -pub type Gpwe16R = crate::BitReader; -impl Gpwe16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe16 { - match self.bits { - false => Gpwe16::Gpwe0, - true => Gpwe16::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe16::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe16::Gpwe1 - } -} -#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] -pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; -impl<'a, REG> Gpwe16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe17 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] -pub type Gpwe17R = crate::BitReader; -impl Gpwe17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe17 { - match self.bits { - false => Gpwe17::Gpwe0, - true => Gpwe17::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe17::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe17::Gpwe1 - } -} -#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] -pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; -impl<'a, REG> Gpwe17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe18 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] -pub type Gpwe18R = crate::BitReader; -impl Gpwe18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe18 { - match self.bits { - false => Gpwe18::Gpwe0, - true => Gpwe18::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe18::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe18::Gpwe1 - } -} -#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] -pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; -impl<'a, REG> Gpwe18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe19 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] -pub type Gpwe19R = crate::BitReader; -impl Gpwe19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe19 { - match self.bits { - false => Gpwe19::Gpwe0, - true => Gpwe19::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe19::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe19::Gpwe1 - } -} -#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] -pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; -impl<'a, REG> Gpwe19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe20 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] -pub type Gpwe20R = crate::BitReader; -impl Gpwe20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe20 { - match self.bits { - false => Gpwe20::Gpwe0, - true => Gpwe20::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe20::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe20::Gpwe1 - } -} -#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] -pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; -impl<'a, REG> Gpwe20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe21 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] -pub type Gpwe21R = crate::BitReader; -impl Gpwe21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe21 { - match self.bits { - false => Gpwe21::Gpwe0, - true => Gpwe21::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe21::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe21::Gpwe1 - } -} -#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] -pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; -impl<'a, REG> Gpwe21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe22 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] -pub type Gpwe22R = crate::BitReader; -impl Gpwe22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe22 { - match self.bits { - false => Gpwe22::Gpwe0, - true => Gpwe22::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe22::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe22::Gpwe1 - } -} -#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] -pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; -impl<'a, REG> Gpwe22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe23 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] -pub type Gpwe23R = crate::BitReader; -impl Gpwe23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe23 { - match self.bits { - false => Gpwe23::Gpwe0, - true => Gpwe23::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe23::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe23::Gpwe1 - } -} -#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] -pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; -impl<'a, REG> Gpwe23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe24 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] -pub type Gpwe24R = crate::BitReader; -impl Gpwe24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe24 { - match self.bits { - false => Gpwe24::Gpwe0, - true => Gpwe24::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe24::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe24::Gpwe1 - } -} -#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] -pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; -impl<'a, REG> Gpwe24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe25 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] -pub type Gpwe25R = crate::BitReader; -impl Gpwe25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe25 { - match self.bits { - false => Gpwe25::Gpwe0, - true => Gpwe25::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe25::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe25::Gpwe1 - } -} -#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] -pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; -impl<'a, REG> Gpwe25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe26 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] -pub type Gpwe26R = crate::BitReader; -impl Gpwe26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe26 { - match self.bits { - false => Gpwe26::Gpwe0, - true => Gpwe26::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe26::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe26::Gpwe1 - } -} -#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] -pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; -impl<'a, REG> Gpwe26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe27 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] -pub type Gpwe27R = crate::BitReader; -impl Gpwe27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe27 { - match self.bits { - false => Gpwe27::Gpwe0, - true => Gpwe27::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe27::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe27::Gpwe1 - } -} -#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] -pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; -impl<'a, REG> Gpwe27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe28 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] -pub type Gpwe28R = crate::BitReader; -impl Gpwe28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe28 { - match self.bits { - false => Gpwe28::Gpwe0, - true => Gpwe28::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe28::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe28::Gpwe1 - } -} -#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] -pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; -impl<'a, REG> Gpwe28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe29 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] -pub type Gpwe29R = crate::BitReader; -impl Gpwe29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe29 { - match self.bits { - false => Gpwe29::Gpwe0, - true => Gpwe29::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe29::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe29::Gpwe1 - } -} -#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] -pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; -impl<'a, REG> Gpwe29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe30 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] -pub type Gpwe30R = crate::BitReader; -impl Gpwe30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe30 { - match self.bits { - false => Gpwe30::Gpwe0, - true => Gpwe30::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe30::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe30::Gpwe1 - } -} -#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] -pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; -impl<'a, REG> Gpwe30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe31 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] -pub type Gpwe31R = crate::BitReader; -impl Gpwe31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe31 { - match self.bits { - false => Gpwe31::Gpwe0, - true => Gpwe31::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe31::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe31::Gpwe1 - } -} -#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] -pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; -impl<'a, REG> Gpwe31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&self) -> Gpwe16R { - Gpwe16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&self) -> Gpwe17R { - Gpwe17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&self) -> Gpwe18R { - Gpwe18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&self) -> Gpwe19R { - Gpwe19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&self) -> Gpwe20R { - Gpwe20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&self) -> Gpwe21R { - Gpwe21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&self) -> Gpwe22R { - Gpwe22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&self) -> Gpwe23R { - Gpwe23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&self) -> Gpwe24R { - Gpwe24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&self) -> Gpwe25R { - Gpwe25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&self) -> Gpwe26R { - Gpwe26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&self) -> Gpwe27R { - Gpwe27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&self) -> Gpwe28R { - Gpwe28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&self) -> Gpwe29R { - Gpwe29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&self) -> Gpwe30R { - Gpwe30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&self) -> Gpwe31R { - Gpwe31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&mut self) -> Gpwe16W { - Gpwe16W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&mut self) -> Gpwe17W { - Gpwe17W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&mut self) -> Gpwe18W { - Gpwe18W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&mut self) -> Gpwe19W { - Gpwe19W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&mut self) -> Gpwe20W { - Gpwe20W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&mut self) -> Gpwe21W { - Gpwe21W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&mut self) -> Gpwe22W { - Gpwe22W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&mut self) -> Gpwe23W { - Gpwe23W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&mut self) -> Gpwe24W { - Gpwe24W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&mut self) -> Gpwe25W { - Gpwe25W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&mut self) -> Gpwe26W { - Gpwe26W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&mut self) -> Gpwe27W { - Gpwe27W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&mut self) -> Gpwe28W { - Gpwe28W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&mut self) -> Gpwe29W { - Gpwe29W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&mut self) -> Gpwe30W { - Gpwe30W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&mut self) -> Gpwe31W { - Gpwe31W::new(self, 31) - } -} -#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpchrSpec; -impl crate::RegisterSpec for GpchrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] -impl crate::Readable for GpchrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] -impl crate::Writable for GpchrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCHR to value 0"] -impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port1/gpclr.rs b/mcxa276-pac/src/port1/gpclr.rs deleted file mode 100644 index 21e5ff23d..000000000 --- a/mcxa276-pac/src/port1/gpclr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCLR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCLR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe0 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] -pub type Gpwe0R = crate::BitReader; -impl Gpwe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe0 { - match self.bits { - false => Gpwe0::Gpwe0, - true => Gpwe0::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe0::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe0::Gpwe1 - } -} -#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] -pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; -impl<'a, REG> Gpwe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe1 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] -pub type Gpwe1R = crate::BitReader; -impl Gpwe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe1 { - match self.bits { - false => Gpwe1::Gpwe0, - true => Gpwe1::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe1::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe1::Gpwe1 - } -} -#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] -pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; -impl<'a, REG> Gpwe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe2 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] -pub type Gpwe2R = crate::BitReader; -impl Gpwe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe2 { - match self.bits { - false => Gpwe2::Gpwe0, - true => Gpwe2::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe2::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe2::Gpwe1 - } -} -#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] -pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; -impl<'a, REG> Gpwe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe3 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] -pub type Gpwe3R = crate::BitReader; -impl Gpwe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe3 { - match self.bits { - false => Gpwe3::Gpwe0, - true => Gpwe3::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe3::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe3::Gpwe1 - } -} -#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] -pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; -impl<'a, REG> Gpwe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe4 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] -pub type Gpwe4R = crate::BitReader; -impl Gpwe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe4 { - match self.bits { - false => Gpwe4::Gpwe0, - true => Gpwe4::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe4::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe4::Gpwe1 - } -} -#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] -pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; -impl<'a, REG> Gpwe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe5 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] -pub type Gpwe5R = crate::BitReader; -impl Gpwe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe5 { - match self.bits { - false => Gpwe5::Gpwe0, - true => Gpwe5::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe5::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe5::Gpwe1 - } -} -#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] -pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; -impl<'a, REG> Gpwe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe6 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] -pub type Gpwe6R = crate::BitReader; -impl Gpwe6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe6 { - match self.bits { - false => Gpwe6::Gpwe0, - true => Gpwe6::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe6::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe6::Gpwe1 - } -} -#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] -pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; -impl<'a, REG> Gpwe6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe7 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] -pub type Gpwe7R = crate::BitReader; -impl Gpwe7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe7 { - match self.bits { - false => Gpwe7::Gpwe0, - true => Gpwe7::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe7::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe7::Gpwe1 - } -} -#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] -pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; -impl<'a, REG> Gpwe7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe8 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] -pub type Gpwe8R = crate::BitReader; -impl Gpwe8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe8 { - match self.bits { - false => Gpwe8::Gpwe0, - true => Gpwe8::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe8::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe8::Gpwe1 - } -} -#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] -pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; -impl<'a, REG> Gpwe8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe9 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] -pub type Gpwe9R = crate::BitReader; -impl Gpwe9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe9 { - match self.bits { - false => Gpwe9::Gpwe0, - true => Gpwe9::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe9::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe9::Gpwe1 - } -} -#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] -pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; -impl<'a, REG> Gpwe9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe10 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] -pub type Gpwe10R = crate::BitReader; -impl Gpwe10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe10 { - match self.bits { - false => Gpwe10::Gpwe0, - true => Gpwe10::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe10::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe10::Gpwe1 - } -} -#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] -pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; -impl<'a, REG> Gpwe10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe11 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] -pub type Gpwe11R = crate::BitReader; -impl Gpwe11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe11 { - match self.bits { - false => Gpwe11::Gpwe0, - true => Gpwe11::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe11::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe11::Gpwe1 - } -} -#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] -pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; -impl<'a, REG> Gpwe11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe12 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] -pub type Gpwe12R = crate::BitReader; -impl Gpwe12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe12 { - match self.bits { - false => Gpwe12::Gpwe0, - true => Gpwe12::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe12::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe12::Gpwe1 - } -} -#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] -pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; -impl<'a, REG> Gpwe12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe13 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] -pub type Gpwe13R = crate::BitReader; -impl Gpwe13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe13 { - match self.bits { - false => Gpwe13::Gpwe0, - true => Gpwe13::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe13::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe13::Gpwe1 - } -} -#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] -pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; -impl<'a, REG> Gpwe13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe14 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] -pub type Gpwe14R = crate::BitReader; -impl Gpwe14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe14 { - match self.bits { - false => Gpwe14::Gpwe0, - true => Gpwe14::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe14::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe14::Gpwe1 - } -} -#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] -pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; -impl<'a, REG> Gpwe14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe15 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] -pub type Gpwe15R = crate::BitReader; -impl Gpwe15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe15 { - match self.bits { - false => Gpwe15::Gpwe0, - true => Gpwe15::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe15::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe15::Gpwe1 - } -} -#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] -pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; -impl<'a, REG> Gpwe15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&self) -> Gpwe0R { - Gpwe0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&self) -> Gpwe1R { - Gpwe1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&self) -> Gpwe2R { - Gpwe2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&self) -> Gpwe3R { - Gpwe3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&self) -> Gpwe4R { - Gpwe4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&self) -> Gpwe5R { - Gpwe5R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&self) -> Gpwe6R { - Gpwe6R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&self) -> Gpwe7R { - Gpwe7R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&self) -> Gpwe8R { - Gpwe8R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&self) -> Gpwe9R { - Gpwe9R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&self) -> Gpwe10R { - Gpwe10R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&self) -> Gpwe11R { - Gpwe11R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&self) -> Gpwe12R { - Gpwe12R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&self) -> Gpwe13R { - Gpwe13R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&self) -> Gpwe14R { - Gpwe14R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&self) -> Gpwe15R { - Gpwe15R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&mut self) -> Gpwe0W { - Gpwe0W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&mut self) -> Gpwe1W { - Gpwe1W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&mut self) -> Gpwe2W { - Gpwe2W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&mut self) -> Gpwe3W { - Gpwe3W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&mut self) -> Gpwe4W { - Gpwe4W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&mut self) -> Gpwe5W { - Gpwe5W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&mut self) -> Gpwe6W { - Gpwe6W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&mut self) -> Gpwe7W { - Gpwe7W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&mut self) -> Gpwe8W { - Gpwe8W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&mut self) -> Gpwe9W { - Gpwe9W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&mut self) -> Gpwe10W { - Gpwe10W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&mut self) -> Gpwe11W { - Gpwe11W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&mut self) -> Gpwe12W { - Gpwe12W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&mut self) -> Gpwe13W { - Gpwe13W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&mut self) -> Gpwe14W { - Gpwe14W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&mut self) -> Gpwe15W { - Gpwe15W::new(self, 31) - } -} -#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpclrSpec; -impl crate::RegisterSpec for GpclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] -impl crate::Readable for GpclrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] -impl crate::Writable for GpclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCLR to value 0"] -impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port1/pcr0.rs b/mcxa276-pac/src/port1/pcr0.rs deleted file mode 100644 index 63c1edc30..000000000 --- a/mcxa276-pac/src/port1/pcr0.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR0` reader"] -pub type R = crate::R; -#[doc = "Register `PCR0` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr0Spec; -impl crate::RegisterSpec for Pcr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] -impl crate::Readable for Pcr0Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] -impl crate::Writable for Pcr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR0 to value 0"] -impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port1/pcr1.rs b/mcxa276-pac/src/port1/pcr1.rs deleted file mode 100644 index 8899bfd9b..000000000 --- a/mcxa276-pac/src/port1/pcr1.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR1` reader"] -pub type R = crate::R; -#[doc = "Register `PCR1` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr1Spec; -impl crate::RegisterSpec for Pcr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] -impl crate::Readable for Pcr1Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] -impl crate::Writable for Pcr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR1 to value 0"] -impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port1/pcr10.rs b/mcxa276-pac/src/port1/pcr10.rs deleted file mode 100644 index e5317eb0c..000000000 --- a/mcxa276-pac/src/port1/pcr10.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR10` reader"] -pub type R = crate::R; -#[doc = "Register `PCR10` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr10Spec; -impl crate::RegisterSpec for Pcr10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] -impl crate::Readable for Pcr10Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] -impl crate::Writable for Pcr10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR10 to value 0"] -impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port1/pcr11.rs b/mcxa276-pac/src/port1/pcr11.rs deleted file mode 100644 index bc47cbd2b..000000000 --- a/mcxa276-pac/src/port1/pcr11.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR11` reader"] -pub type R = crate::R; -#[doc = "Register `PCR11` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr11Spec; -impl crate::RegisterSpec for Pcr11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] -impl crate::Readable for Pcr11Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] -impl crate::Writable for Pcr11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR11 to value 0"] -impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port1/pcr12.rs b/mcxa276-pac/src/port1/pcr12.rs deleted file mode 100644 index 2cd7eecc1..000000000 --- a/mcxa276-pac/src/port1/pcr12.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR12` reader"] -pub type R = crate::R; -#[doc = "Register `PCR12` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr12Spec; -impl crate::RegisterSpec for Pcr12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] -impl crate::Readable for Pcr12Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] -impl crate::Writable for Pcr12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR12 to value 0"] -impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port1/pcr13.rs b/mcxa276-pac/src/port1/pcr13.rs deleted file mode 100644 index 0da9c8d55..000000000 --- a/mcxa276-pac/src/port1/pcr13.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR13` reader"] -pub type R = crate::R; -#[doc = "Register `PCR13` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr13Spec; -impl crate::RegisterSpec for Pcr13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] -impl crate::Readable for Pcr13Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] -impl crate::Writable for Pcr13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR13 to value 0"] -impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port1/pcr14.rs b/mcxa276-pac/src/port1/pcr14.rs deleted file mode 100644 index 553559b3f..000000000 --- a/mcxa276-pac/src/port1/pcr14.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR14` reader"] -pub type R = crate::R; -#[doc = "Register `PCR14` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr14Spec; -impl crate::RegisterSpec for Pcr14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] -impl crate::Readable for Pcr14Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] -impl crate::Writable for Pcr14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR14 to value 0"] -impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port1/pcr15.rs b/mcxa276-pac/src/port1/pcr15.rs deleted file mode 100644 index 85c188f6b..000000000 --- a/mcxa276-pac/src/port1/pcr15.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR15` reader"] -pub type R = crate::R; -#[doc = "Register `PCR15` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr15Spec; -impl crate::RegisterSpec for Pcr15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] -impl crate::Readable for Pcr15Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] -impl crate::Writable for Pcr15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR15 to value 0"] -impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port1/pcr16.rs b/mcxa276-pac/src/port1/pcr16.rs deleted file mode 100644 index 70c9dda78..000000000 --- a/mcxa276-pac/src/port1/pcr16.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR16` reader"] -pub type R = crate::R; -#[doc = "Register `PCR16` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr16Spec; -impl crate::RegisterSpec for Pcr16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] -impl crate::Readable for Pcr16Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] -impl crate::Writable for Pcr16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR16 to value 0"] -impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port1/pcr17.rs b/mcxa276-pac/src/port1/pcr17.rs deleted file mode 100644 index 2faf3487b..000000000 --- a/mcxa276-pac/src/port1/pcr17.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR17` reader"] -pub type R = crate::R; -#[doc = "Register `PCR17` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr17Spec; -impl crate::RegisterSpec for Pcr17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] -impl crate::Readable for Pcr17Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] -impl crate::Writable for Pcr17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR17 to value 0"] -impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port1/pcr18.rs b/mcxa276-pac/src/port1/pcr18.rs deleted file mode 100644 index b87bafe1a..000000000 --- a/mcxa276-pac/src/port1/pcr18.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR18` reader"] -pub type R = crate::R; -#[doc = "Register `PCR18` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr18Spec; -impl crate::RegisterSpec for Pcr18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] -impl crate::Readable for Pcr18Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] -impl crate::Writable for Pcr18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR18 to value 0"] -impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port1/pcr19.rs b/mcxa276-pac/src/port1/pcr19.rs deleted file mode 100644 index cd55e9cfd..000000000 --- a/mcxa276-pac/src/port1/pcr19.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR19` reader"] -pub type R = crate::R; -#[doc = "Register `PCR19` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr19Spec; -impl crate::RegisterSpec for Pcr19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] -impl crate::Readable for Pcr19Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] -impl crate::Writable for Pcr19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR19 to value 0"] -impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port1/pcr2.rs b/mcxa276-pac/src/port1/pcr2.rs deleted file mode 100644 index 09359160e..000000000 --- a/mcxa276-pac/src/port1/pcr2.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR2` reader"] -pub type R = crate::R; -#[doc = "Register `PCR2` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr2Spec; -impl crate::RegisterSpec for Pcr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] -impl crate::Readable for Pcr2Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] -impl crate::Writable for Pcr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR2 to value 0"] -impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port1/pcr20.rs b/mcxa276-pac/src/port1/pcr20.rs deleted file mode 100644 index d3457f781..000000000 --- a/mcxa276-pac/src/port1/pcr20.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR20` reader"] -pub type R = crate::R; -#[doc = "Register `PCR20` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr20Spec; -impl crate::RegisterSpec for Pcr20Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] -impl crate::Readable for Pcr20Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] -impl crate::Writable for Pcr20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR20 to value 0"] -impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port1/pcr21.rs b/mcxa276-pac/src/port1/pcr21.rs deleted file mode 100644 index 549acb257..000000000 --- a/mcxa276-pac/src/port1/pcr21.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR21` reader"] -pub type R = crate::R; -#[doc = "Register `PCR21` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr21Spec; -impl crate::RegisterSpec for Pcr21Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] -impl crate::Readable for Pcr21Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] -impl crate::Writable for Pcr21Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR21 to value 0"] -impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port1/pcr22.rs b/mcxa276-pac/src/port1/pcr22.rs deleted file mode 100644 index b52c672cb..000000000 --- a/mcxa276-pac/src/port1/pcr22.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR22` reader"] -pub type R = crate::R; -#[doc = "Register `PCR22` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr22Spec; -impl crate::RegisterSpec for Pcr22Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] -impl crate::Readable for Pcr22Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] -impl crate::Writable for Pcr22Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR22 to value 0"] -impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port1/pcr23.rs b/mcxa276-pac/src/port1/pcr23.rs deleted file mode 100644 index 918e561a9..000000000 --- a/mcxa276-pac/src/port1/pcr23.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR23` reader"] -pub type R = crate::R; -#[doc = "Register `PCR23` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr23Spec; -impl crate::RegisterSpec for Pcr23Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] -impl crate::Readable for Pcr23Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] -impl crate::Writable for Pcr23Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR23 to value 0"] -impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port1/pcr24.rs b/mcxa276-pac/src/port1/pcr24.rs deleted file mode 100644 index 1bc9d5574..000000000 --- a/mcxa276-pac/src/port1/pcr24.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR24` reader"] -pub type R = crate::R; -#[doc = "Register `PCR24` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr24Spec; -impl crate::RegisterSpec for Pcr24Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] -impl crate::Readable for Pcr24Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] -impl crate::Writable for Pcr24Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR24 to value 0"] -impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port1/pcr25.rs b/mcxa276-pac/src/port1/pcr25.rs deleted file mode 100644 index dbc8cae05..000000000 --- a/mcxa276-pac/src/port1/pcr25.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR25` reader"] -pub type R = crate::R; -#[doc = "Register `PCR25` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr25Spec; -impl crate::RegisterSpec for Pcr25Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] -impl crate::Readable for Pcr25Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] -impl crate::Writable for Pcr25Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR25 to value 0"] -impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port1/pcr26.rs b/mcxa276-pac/src/port1/pcr26.rs deleted file mode 100644 index 24ffb3145..000000000 --- a/mcxa276-pac/src/port1/pcr26.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR26` reader"] -pub type R = crate::R; -#[doc = "Register `PCR26` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr26Spec; -impl crate::RegisterSpec for Pcr26Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] -impl crate::Readable for Pcr26Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] -impl crate::Writable for Pcr26Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR26 to value 0"] -impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port1/pcr27.rs b/mcxa276-pac/src/port1/pcr27.rs deleted file mode 100644 index ac4a51d32..000000000 --- a/mcxa276-pac/src/port1/pcr27.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR27` reader"] -pub type R = crate::R; -#[doc = "Register `PCR27` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr27Spec; -impl crate::RegisterSpec for Pcr27Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] -impl crate::Readable for Pcr27Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] -impl crate::Writable for Pcr27Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR27 to value 0"] -impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port1/pcr28.rs b/mcxa276-pac/src/port1/pcr28.rs deleted file mode 100644 index 1315078be..000000000 --- a/mcxa276-pac/src/port1/pcr28.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR28` reader"] -pub type R = crate::R; -#[doc = "Register `PCR28` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr28Spec; -impl crate::RegisterSpec for Pcr28Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] -impl crate::Readable for Pcr28Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] -impl crate::Writable for Pcr28Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR28 to value 0"] -impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port1/pcr29.rs b/mcxa276-pac/src/port1/pcr29.rs deleted file mode 100644 index 4376ab7b9..000000000 --- a/mcxa276-pac/src/port1/pcr29.rs +++ /dev/null @@ -1,749 +0,0 @@ -#[doc = "Register `PCR29` reader"] -pub type R = crate::R; -#[doc = "Register `PCR29` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:9 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:9 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr29Spec; -impl crate::RegisterSpec for Pcr29Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] -impl crate::Readable for Pcr29Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] -impl crate::Writable for Pcr29Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR29 to value 0x0133"] -impl crate::Resettable for Pcr29Spec { - const RESET_VALUE: u32 = 0x0133; -} diff --git a/mcxa276-pac/src/port1/pcr3.rs b/mcxa276-pac/src/port1/pcr3.rs deleted file mode 100644 index 0bdf66c1b..000000000 --- a/mcxa276-pac/src/port1/pcr3.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR3` reader"] -pub type R = crate::R; -#[doc = "Register `PCR3` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr3Spec; -impl crate::RegisterSpec for Pcr3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] -impl crate::Readable for Pcr3Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] -impl crate::Writable for Pcr3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR3 to value 0"] -impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port1/pcr30.rs b/mcxa276-pac/src/port1/pcr30.rs deleted file mode 100644 index 008d44c80..000000000 --- a/mcxa276-pac/src/port1/pcr30.rs +++ /dev/null @@ -1,940 +0,0 @@ -#[doc = "Register `PCR30` reader"] -pub type R = crate::R; -#[doc = "Register `PCR30` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr30Spec; -impl crate::RegisterSpec for Pcr30Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] -impl crate::Readable for Pcr30Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] -impl crate::Writable for Pcr30Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR30 to value 0"] -impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port1/pcr31.rs b/mcxa276-pac/src/port1/pcr31.rs deleted file mode 100644 index 6ab9e5d70..000000000 --- a/mcxa276-pac/src/port1/pcr31.rs +++ /dev/null @@ -1,877 +0,0 @@ -#[doc = "Register `PCR31` reader"] -pub type R = crate::R; -#[doc = "Register `PCR31` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr31Spec; -impl crate::RegisterSpec for Pcr31Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] -impl crate::Readable for Pcr31Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] -impl crate::Writable for Pcr31Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR31 to value 0"] -impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port1/pcr4.rs b/mcxa276-pac/src/port1/pcr4.rs deleted file mode 100644 index 9890bb2d4..000000000 --- a/mcxa276-pac/src/port1/pcr4.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR4` reader"] -pub type R = crate::R; -#[doc = "Register `PCR4` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr4Spec; -impl crate::RegisterSpec for Pcr4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] -impl crate::Readable for Pcr4Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] -impl crate::Writable for Pcr4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR4 to value 0"] -impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port1/pcr5.rs b/mcxa276-pac/src/port1/pcr5.rs deleted file mode 100644 index bbc9bfc8a..000000000 --- a/mcxa276-pac/src/port1/pcr5.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR5` reader"] -pub type R = crate::R; -#[doc = "Register `PCR5` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr5Spec; -impl crate::RegisterSpec for Pcr5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] -impl crate::Readable for Pcr5Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] -impl crate::Writable for Pcr5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR5 to value 0"] -impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port1/pcr6.rs b/mcxa276-pac/src/port1/pcr6.rs deleted file mode 100644 index dcc6c56c6..000000000 --- a/mcxa276-pac/src/port1/pcr6.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR6` reader"] -pub type R = crate::R; -#[doc = "Register `PCR6` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr6Spec; -impl crate::RegisterSpec for Pcr6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] -impl crate::Readable for Pcr6Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] -impl crate::Writable for Pcr6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR6 to value 0"] -impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port1/pcr7.rs b/mcxa276-pac/src/port1/pcr7.rs deleted file mode 100644 index 71a9e66da..000000000 --- a/mcxa276-pac/src/port1/pcr7.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR7` reader"] -pub type R = crate::R; -#[doc = "Register `PCR7` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr7Spec; -impl crate::RegisterSpec for Pcr7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] -impl crate::Readable for Pcr7Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] -impl crate::Writable for Pcr7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR7 to value 0"] -impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port1/pcr8.rs b/mcxa276-pac/src/port1/pcr8.rs deleted file mode 100644 index be20db45e..000000000 --- a/mcxa276-pac/src/port1/pcr8.rs +++ /dev/null @@ -1,940 +0,0 @@ -#[doc = "Register `PCR8` reader"] -pub type R = crate::R; -#[doc = "Register `PCR8` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr8Spec; -impl crate::RegisterSpec for Pcr8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] -impl crate::Readable for Pcr8Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] -impl crate::Writable for Pcr8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR8 to value 0"] -impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port1/pcr9.rs b/mcxa276-pac/src/port1/pcr9.rs deleted file mode 100644 index 1e64e1fb2..000000000 --- a/mcxa276-pac/src/port1/pcr9.rs +++ /dev/null @@ -1,877 +0,0 @@ -#[doc = "Register `PCR9` reader"] -pub type R = crate::R; -#[doc = "Register `PCR9` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr9Spec; -impl crate::RegisterSpec for Pcr9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] -impl crate::Readable for Pcr9Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] -impl crate::Writable for Pcr9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR9 to value 0"] -impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port1/verid.rs b/mcxa276-pac/src/port1/verid.rs deleted file mode 100644 index 330f53d57..000000000 --- a/mcxa276-pac/src/port1/verid.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Basic implementation"] - Feature0 = 0, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Feature0), - _ => None, - } - } - #[doc = "Basic implementation"] - #[inline(always)] - pub fn is_feature0(&self) -> bool { - *self == Feature::Feature0 - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0200_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0200_0000; -} diff --git a/mcxa276-pac/src/port2.rs b/mcxa276-pac/src/port2.rs deleted file mode 100644 index 1f60eec3c..000000000 --- a/mcxa276-pac/src/port2.rs +++ /dev/null @@ -1,405 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x0c], - gpclr: Gpclr, - gpchr: Gpchr, - _reserved3: [u8; 0x08], - config: Config, - _reserved4: [u8; 0x5c], - pcr0: Pcr0, - pcr1: Pcr1, - pcr2: Pcr2, - pcr3: Pcr3, - pcr4: Pcr4, - pcr5: Pcr5, - pcr6: Pcr6, - pcr7: Pcr7, - pcr8: Pcr8, - pcr9: Pcr9, - pcr10: Pcr10, - pcr11: Pcr11, - pcr12: Pcr12, - pcr13: Pcr13, - pcr14: Pcr14, - pcr15: Pcr15, - pcr16: Pcr16, - pcr17: Pcr17, - pcr18: Pcr18, - pcr19: Pcr19, - pcr20: Pcr20, - pcr21: Pcr21, - pcr22: Pcr22, - pcr23: Pcr23, - pcr24: Pcr24, - pcr25: Pcr25, - pcr26: Pcr26, - pcr27: Pcr27, - pcr28: Pcr28, - pcr29: Pcr29, - pcr30: Pcr30, - pcr31: Pcr31, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x10 - Global Pin Control Low"] - #[inline(always)] - pub const fn gpclr(&self) -> &Gpclr { - &self.gpclr - } - #[doc = "0x14 - Global Pin Control High"] - #[inline(always)] - pub const fn gpchr(&self) -> &Gpchr { - &self.gpchr - } - #[doc = "0x20 - Configuration"] - #[inline(always)] - pub const fn config(&self) -> &Config { - &self.config - } - #[doc = "0x80 - Pin Control 0"] - #[inline(always)] - pub const fn pcr0(&self) -> &Pcr0 { - &self.pcr0 - } - #[doc = "0x84 - Pin Control 1"] - #[inline(always)] - pub const fn pcr1(&self) -> &Pcr1 { - &self.pcr1 - } - #[doc = "0x88 - Pin Control 2"] - #[inline(always)] - pub const fn pcr2(&self) -> &Pcr2 { - &self.pcr2 - } - #[doc = "0x8c - Pin Control 3"] - #[inline(always)] - pub const fn pcr3(&self) -> &Pcr3 { - &self.pcr3 - } - #[doc = "0x90 - Pin Control 4"] - #[inline(always)] - pub const fn pcr4(&self) -> &Pcr4 { - &self.pcr4 - } - #[doc = "0x94 - Pin Control 5"] - #[inline(always)] - pub const fn pcr5(&self) -> &Pcr5 { - &self.pcr5 - } - #[doc = "0x98 - Pin Control 6"] - #[inline(always)] - pub const fn pcr6(&self) -> &Pcr6 { - &self.pcr6 - } - #[doc = "0x9c - Pin Control 7"] - #[inline(always)] - pub const fn pcr7(&self) -> &Pcr7 { - &self.pcr7 - } - #[doc = "0xa0 - Pin Control 8"] - #[inline(always)] - pub const fn pcr8(&self) -> &Pcr8 { - &self.pcr8 - } - #[doc = "0xa4 - Pin Control 9"] - #[inline(always)] - pub const fn pcr9(&self) -> &Pcr9 { - &self.pcr9 - } - #[doc = "0xa8 - Pin Control 10"] - #[inline(always)] - pub const fn pcr10(&self) -> &Pcr10 { - &self.pcr10 - } - #[doc = "0xac - Pin Control 11"] - #[inline(always)] - pub const fn pcr11(&self) -> &Pcr11 { - &self.pcr11 - } - #[doc = "0xb0 - Pin Control 12"] - #[inline(always)] - pub const fn pcr12(&self) -> &Pcr12 { - &self.pcr12 - } - #[doc = "0xb4 - Pin Control 13"] - #[inline(always)] - pub const fn pcr13(&self) -> &Pcr13 { - &self.pcr13 - } - #[doc = "0xb8 - Pin Control 14"] - #[inline(always)] - pub const fn pcr14(&self) -> &Pcr14 { - &self.pcr14 - } - #[doc = "0xbc - Pin Control 15"] - #[inline(always)] - pub const fn pcr15(&self) -> &Pcr15 { - &self.pcr15 - } - #[doc = "0xc0 - Pin Control 16"] - #[inline(always)] - pub const fn pcr16(&self) -> &Pcr16 { - &self.pcr16 - } - #[doc = "0xc4 - Pin Control 17"] - #[inline(always)] - pub const fn pcr17(&self) -> &Pcr17 { - &self.pcr17 - } - #[doc = "0xc8 - Pin Control 18"] - #[inline(always)] - pub const fn pcr18(&self) -> &Pcr18 { - &self.pcr18 - } - #[doc = "0xcc - Pin Control 19"] - #[inline(always)] - pub const fn pcr19(&self) -> &Pcr19 { - &self.pcr19 - } - #[doc = "0xd0 - Pin Control 20"] - #[inline(always)] - pub const fn pcr20(&self) -> &Pcr20 { - &self.pcr20 - } - #[doc = "0xd4 - Pin Control 21"] - #[inline(always)] - pub const fn pcr21(&self) -> &Pcr21 { - &self.pcr21 - } - #[doc = "0xd8 - Pin Control 22"] - #[inline(always)] - pub const fn pcr22(&self) -> &Pcr22 { - &self.pcr22 - } - #[doc = "0xdc - Pin Control 23"] - #[inline(always)] - pub const fn pcr23(&self) -> &Pcr23 { - &self.pcr23 - } - #[doc = "0xe0 - Pin Control 24"] - #[inline(always)] - pub const fn pcr24(&self) -> &Pcr24 { - &self.pcr24 - } - #[doc = "0xe4 - Pin Control 25"] - #[inline(always)] - pub const fn pcr25(&self) -> &Pcr25 { - &self.pcr25 - } - #[doc = "0xe8 - Pin Control 26"] - #[inline(always)] - pub const fn pcr26(&self) -> &Pcr26 { - &self.pcr26 - } - #[doc = "0xec - Pin Control 27"] - #[inline(always)] - pub const fn pcr27(&self) -> &Pcr27 { - &self.pcr27 - } - #[doc = "0xf0 - Pin Control 28"] - #[inline(always)] - pub const fn pcr28(&self) -> &Pcr28 { - &self.pcr28 - } - #[doc = "0xf4 - Pin Control 29"] - #[inline(always)] - pub const fn pcr29(&self) -> &Pcr29 { - &self.pcr29 - } - #[doc = "0xf8 - Pin Control 30"] - #[inline(always)] - pub const fn pcr30(&self) -> &Pcr30 { - &self.pcr30 - } - #[doc = "0xfc - Pin Control 31"] - #[inline(always)] - pub const fn pcr31(&self) -> &Pcr31 { - &self.pcr31 - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] -#[doc(alias = "GPCLR")] -pub type Gpclr = crate::Reg; -#[doc = "Global Pin Control Low"] -pub mod gpclr; -#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] -#[doc(alias = "GPCHR")] -pub type Gpchr = crate::Reg; -#[doc = "Global Pin Control High"] -pub mod gpchr; -#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] -#[doc(alias = "CONFIG")] -pub type Config = crate::Reg; -#[doc = "Configuration"] -pub mod config; -#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] -#[doc(alias = "PCR0")] -pub type Pcr0 = crate::Reg; -#[doc = "Pin Control 0"] -pub mod pcr0; -#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] -#[doc(alias = "PCR1")] -pub type Pcr1 = crate::Reg; -#[doc = "Pin Control 1"] -pub mod pcr1; -#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] -#[doc(alias = "PCR2")] -pub type Pcr2 = crate::Reg; -#[doc = "Pin Control 2"] -pub mod pcr2; -#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] -#[doc(alias = "PCR3")] -pub type Pcr3 = crate::Reg; -#[doc = "Pin Control 3"] -pub mod pcr3; -#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] -#[doc(alias = "PCR4")] -pub type Pcr4 = crate::Reg; -#[doc = "Pin Control 4"] -pub mod pcr4; -#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] -#[doc(alias = "PCR5")] -pub type Pcr5 = crate::Reg; -#[doc = "Pin Control 5"] -pub mod pcr5; -#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] -#[doc(alias = "PCR6")] -pub type Pcr6 = crate::Reg; -#[doc = "Pin Control 6"] -pub mod pcr6; -#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] -#[doc(alias = "PCR7")] -pub type Pcr7 = crate::Reg; -#[doc = "Pin Control 7"] -pub mod pcr7; -#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] -#[doc(alias = "PCR8")] -pub type Pcr8 = crate::Reg; -#[doc = "Pin Control 8"] -pub mod pcr8; -#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] -#[doc(alias = "PCR9")] -pub type Pcr9 = crate::Reg; -#[doc = "Pin Control 9"] -pub mod pcr9; -#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] -#[doc(alias = "PCR10")] -pub type Pcr10 = crate::Reg; -#[doc = "Pin Control 10"] -pub mod pcr10; -#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] -#[doc(alias = "PCR11")] -pub type Pcr11 = crate::Reg; -#[doc = "Pin Control 11"] -pub mod pcr11; -#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] -#[doc(alias = "PCR12")] -pub type Pcr12 = crate::Reg; -#[doc = "Pin Control 12"] -pub mod pcr12; -#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] -#[doc(alias = "PCR13")] -pub type Pcr13 = crate::Reg; -#[doc = "Pin Control 13"] -pub mod pcr13; -#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] -#[doc(alias = "PCR14")] -pub type Pcr14 = crate::Reg; -#[doc = "Pin Control 14"] -pub mod pcr14; -#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] -#[doc(alias = "PCR15")] -pub type Pcr15 = crate::Reg; -#[doc = "Pin Control 15"] -pub mod pcr15; -#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] -#[doc(alias = "PCR16")] -pub type Pcr16 = crate::Reg; -#[doc = "Pin Control 16"] -pub mod pcr16; -#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] -#[doc(alias = "PCR17")] -pub type Pcr17 = crate::Reg; -#[doc = "Pin Control 17"] -pub mod pcr17; -#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] -#[doc(alias = "PCR18")] -pub type Pcr18 = crate::Reg; -#[doc = "Pin Control 18"] -pub mod pcr18; -#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] -#[doc(alias = "PCR19")] -pub type Pcr19 = crate::Reg; -#[doc = "Pin Control 19"] -pub mod pcr19; -#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] -#[doc(alias = "PCR20")] -pub type Pcr20 = crate::Reg; -#[doc = "Pin Control 20"] -pub mod pcr20; -#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] -#[doc(alias = "PCR21")] -pub type Pcr21 = crate::Reg; -#[doc = "Pin Control 21"] -pub mod pcr21; -#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] -#[doc(alias = "PCR22")] -pub type Pcr22 = crate::Reg; -#[doc = "Pin Control 22"] -pub mod pcr22; -#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] -#[doc(alias = "PCR23")] -pub type Pcr23 = crate::Reg; -#[doc = "Pin Control 23"] -pub mod pcr23; -#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] -#[doc(alias = "PCR24")] -pub type Pcr24 = crate::Reg; -#[doc = "Pin Control 24"] -pub mod pcr24; -#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] -#[doc(alias = "PCR25")] -pub type Pcr25 = crate::Reg; -#[doc = "Pin Control 25"] -pub mod pcr25; -#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] -#[doc(alias = "PCR26")] -pub type Pcr26 = crate::Reg; -#[doc = "Pin Control 26"] -pub mod pcr26; -#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] -#[doc(alias = "PCR27")] -pub type Pcr27 = crate::Reg; -#[doc = "Pin Control 27"] -pub mod pcr27; -#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] -#[doc(alias = "PCR28")] -pub type Pcr28 = crate::Reg; -#[doc = "Pin Control 28"] -pub mod pcr28; -#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] -#[doc(alias = "PCR29")] -pub type Pcr29 = crate::Reg; -#[doc = "Pin Control 29"] -pub mod pcr29; -#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] -#[doc(alias = "PCR30")] -pub type Pcr30 = crate::Reg; -#[doc = "Pin Control 30"] -pub mod pcr30; -#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] -#[doc(alias = "PCR31")] -pub type Pcr31 = crate::Reg; -#[doc = "Pin Control 31"] -pub mod pcr31; diff --git a/mcxa276-pac/src/port2/config.rs b/mcxa276-pac/src/port2/config.rs deleted file mode 100644 index da92c5b27..000000000 --- a/mcxa276-pac/src/port2/config.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `CONFIG` reader"] -pub type R = crate::R; -#[doc = "Register `CONFIG` writer"] -pub type W = crate::W; -#[doc = "Port Voltage Range\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Range { - #[doc = "0: 1.71 V-3.6 V"] - Range0 = 0, - #[doc = "1: 2.70 V-3.6 V"] - Range1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Range) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RANGE` reader - Port Voltage Range"] -pub type RangeR = crate::BitReader; -impl RangeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Range { - match self.bits { - false => Range::Range0, - true => Range::Range1, - } - } - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn is_range0(&self) -> bool { - *self == Range::Range0 - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn is_range1(&self) -> bool { - *self == Range::Range1 - } -} -#[doc = "Field `RANGE` writer - Port Voltage Range"] -pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; -impl<'a, REG> RangeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn range0(self) -> &'a mut crate::W { - self.variant(Range::Range0) - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn range1(self) -> &'a mut crate::W { - self.variant(Range::Range1) - } -} -impl R { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&self) -> RangeR { - RangeR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&mut self) -> RangeW { - RangeW::new(self, 0) - } -} -#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ConfigSpec; -impl crate::RegisterSpec for ConfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`config::R`](R) reader structure"] -impl crate::Readable for ConfigSpec {} -#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] -impl crate::Writable for ConfigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CONFIG to value 0"] -impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port2/gpchr.rs b/mcxa276-pac/src/port2/gpchr.rs deleted file mode 100644 index af92d0d62..000000000 --- a/mcxa276-pac/src/port2/gpchr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCHR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCHR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe16 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] -pub type Gpwe16R = crate::BitReader; -impl Gpwe16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe16 { - match self.bits { - false => Gpwe16::Gpwe0, - true => Gpwe16::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe16::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe16::Gpwe1 - } -} -#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] -pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; -impl<'a, REG> Gpwe16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe17 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] -pub type Gpwe17R = crate::BitReader; -impl Gpwe17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe17 { - match self.bits { - false => Gpwe17::Gpwe0, - true => Gpwe17::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe17::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe17::Gpwe1 - } -} -#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] -pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; -impl<'a, REG> Gpwe17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe18 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] -pub type Gpwe18R = crate::BitReader; -impl Gpwe18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe18 { - match self.bits { - false => Gpwe18::Gpwe0, - true => Gpwe18::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe18::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe18::Gpwe1 - } -} -#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] -pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; -impl<'a, REG> Gpwe18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe19 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] -pub type Gpwe19R = crate::BitReader; -impl Gpwe19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe19 { - match self.bits { - false => Gpwe19::Gpwe0, - true => Gpwe19::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe19::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe19::Gpwe1 - } -} -#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] -pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; -impl<'a, REG> Gpwe19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe20 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] -pub type Gpwe20R = crate::BitReader; -impl Gpwe20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe20 { - match self.bits { - false => Gpwe20::Gpwe0, - true => Gpwe20::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe20::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe20::Gpwe1 - } -} -#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] -pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; -impl<'a, REG> Gpwe20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe21 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] -pub type Gpwe21R = crate::BitReader; -impl Gpwe21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe21 { - match self.bits { - false => Gpwe21::Gpwe0, - true => Gpwe21::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe21::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe21::Gpwe1 - } -} -#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] -pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; -impl<'a, REG> Gpwe21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe22 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] -pub type Gpwe22R = crate::BitReader; -impl Gpwe22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe22 { - match self.bits { - false => Gpwe22::Gpwe0, - true => Gpwe22::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe22::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe22::Gpwe1 - } -} -#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] -pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; -impl<'a, REG> Gpwe22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe23 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] -pub type Gpwe23R = crate::BitReader; -impl Gpwe23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe23 { - match self.bits { - false => Gpwe23::Gpwe0, - true => Gpwe23::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe23::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe23::Gpwe1 - } -} -#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] -pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; -impl<'a, REG> Gpwe23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe24 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] -pub type Gpwe24R = crate::BitReader; -impl Gpwe24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe24 { - match self.bits { - false => Gpwe24::Gpwe0, - true => Gpwe24::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe24::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe24::Gpwe1 - } -} -#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] -pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; -impl<'a, REG> Gpwe24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe25 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] -pub type Gpwe25R = crate::BitReader; -impl Gpwe25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe25 { - match self.bits { - false => Gpwe25::Gpwe0, - true => Gpwe25::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe25::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe25::Gpwe1 - } -} -#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] -pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; -impl<'a, REG> Gpwe25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe26 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] -pub type Gpwe26R = crate::BitReader; -impl Gpwe26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe26 { - match self.bits { - false => Gpwe26::Gpwe0, - true => Gpwe26::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe26::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe26::Gpwe1 - } -} -#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] -pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; -impl<'a, REG> Gpwe26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe27 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] -pub type Gpwe27R = crate::BitReader; -impl Gpwe27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe27 { - match self.bits { - false => Gpwe27::Gpwe0, - true => Gpwe27::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe27::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe27::Gpwe1 - } -} -#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] -pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; -impl<'a, REG> Gpwe27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe28 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] -pub type Gpwe28R = crate::BitReader; -impl Gpwe28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe28 { - match self.bits { - false => Gpwe28::Gpwe0, - true => Gpwe28::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe28::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe28::Gpwe1 - } -} -#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] -pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; -impl<'a, REG> Gpwe28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe29 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] -pub type Gpwe29R = crate::BitReader; -impl Gpwe29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe29 { - match self.bits { - false => Gpwe29::Gpwe0, - true => Gpwe29::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe29::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe29::Gpwe1 - } -} -#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] -pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; -impl<'a, REG> Gpwe29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe30 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] -pub type Gpwe30R = crate::BitReader; -impl Gpwe30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe30 { - match self.bits { - false => Gpwe30::Gpwe0, - true => Gpwe30::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe30::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe30::Gpwe1 - } -} -#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] -pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; -impl<'a, REG> Gpwe30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe31 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] -pub type Gpwe31R = crate::BitReader; -impl Gpwe31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe31 { - match self.bits { - false => Gpwe31::Gpwe0, - true => Gpwe31::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe31::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe31::Gpwe1 - } -} -#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] -pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; -impl<'a, REG> Gpwe31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&self) -> Gpwe16R { - Gpwe16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&self) -> Gpwe17R { - Gpwe17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&self) -> Gpwe18R { - Gpwe18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&self) -> Gpwe19R { - Gpwe19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&self) -> Gpwe20R { - Gpwe20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&self) -> Gpwe21R { - Gpwe21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&self) -> Gpwe22R { - Gpwe22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&self) -> Gpwe23R { - Gpwe23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&self) -> Gpwe24R { - Gpwe24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&self) -> Gpwe25R { - Gpwe25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&self) -> Gpwe26R { - Gpwe26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&self) -> Gpwe27R { - Gpwe27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&self) -> Gpwe28R { - Gpwe28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&self) -> Gpwe29R { - Gpwe29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&self) -> Gpwe30R { - Gpwe30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&self) -> Gpwe31R { - Gpwe31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&mut self) -> Gpwe16W { - Gpwe16W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&mut self) -> Gpwe17W { - Gpwe17W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&mut self) -> Gpwe18W { - Gpwe18W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&mut self) -> Gpwe19W { - Gpwe19W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&mut self) -> Gpwe20W { - Gpwe20W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&mut self) -> Gpwe21W { - Gpwe21W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&mut self) -> Gpwe22W { - Gpwe22W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&mut self) -> Gpwe23W { - Gpwe23W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&mut self) -> Gpwe24W { - Gpwe24W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&mut self) -> Gpwe25W { - Gpwe25W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&mut self) -> Gpwe26W { - Gpwe26W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&mut self) -> Gpwe27W { - Gpwe27W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&mut self) -> Gpwe28W { - Gpwe28W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&mut self) -> Gpwe29W { - Gpwe29W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&mut self) -> Gpwe30W { - Gpwe30W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&mut self) -> Gpwe31W { - Gpwe31W::new(self, 31) - } -} -#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpchrSpec; -impl crate::RegisterSpec for GpchrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] -impl crate::Readable for GpchrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] -impl crate::Writable for GpchrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCHR to value 0"] -impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port2/gpclr.rs b/mcxa276-pac/src/port2/gpclr.rs deleted file mode 100644 index 21e5ff23d..000000000 --- a/mcxa276-pac/src/port2/gpclr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCLR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCLR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe0 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] -pub type Gpwe0R = crate::BitReader; -impl Gpwe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe0 { - match self.bits { - false => Gpwe0::Gpwe0, - true => Gpwe0::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe0::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe0::Gpwe1 - } -} -#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] -pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; -impl<'a, REG> Gpwe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe1 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] -pub type Gpwe1R = crate::BitReader; -impl Gpwe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe1 { - match self.bits { - false => Gpwe1::Gpwe0, - true => Gpwe1::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe1::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe1::Gpwe1 - } -} -#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] -pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; -impl<'a, REG> Gpwe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe2 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] -pub type Gpwe2R = crate::BitReader; -impl Gpwe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe2 { - match self.bits { - false => Gpwe2::Gpwe0, - true => Gpwe2::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe2::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe2::Gpwe1 - } -} -#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] -pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; -impl<'a, REG> Gpwe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe3 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] -pub type Gpwe3R = crate::BitReader; -impl Gpwe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe3 { - match self.bits { - false => Gpwe3::Gpwe0, - true => Gpwe3::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe3::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe3::Gpwe1 - } -} -#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] -pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; -impl<'a, REG> Gpwe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe4 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] -pub type Gpwe4R = crate::BitReader; -impl Gpwe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe4 { - match self.bits { - false => Gpwe4::Gpwe0, - true => Gpwe4::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe4::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe4::Gpwe1 - } -} -#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] -pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; -impl<'a, REG> Gpwe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe5 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] -pub type Gpwe5R = crate::BitReader; -impl Gpwe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe5 { - match self.bits { - false => Gpwe5::Gpwe0, - true => Gpwe5::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe5::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe5::Gpwe1 - } -} -#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] -pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; -impl<'a, REG> Gpwe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe6 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] -pub type Gpwe6R = crate::BitReader; -impl Gpwe6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe6 { - match self.bits { - false => Gpwe6::Gpwe0, - true => Gpwe6::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe6::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe6::Gpwe1 - } -} -#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] -pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; -impl<'a, REG> Gpwe6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe7 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] -pub type Gpwe7R = crate::BitReader; -impl Gpwe7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe7 { - match self.bits { - false => Gpwe7::Gpwe0, - true => Gpwe7::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe7::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe7::Gpwe1 - } -} -#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] -pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; -impl<'a, REG> Gpwe7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe8 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] -pub type Gpwe8R = crate::BitReader; -impl Gpwe8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe8 { - match self.bits { - false => Gpwe8::Gpwe0, - true => Gpwe8::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe8::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe8::Gpwe1 - } -} -#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] -pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; -impl<'a, REG> Gpwe8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe9 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] -pub type Gpwe9R = crate::BitReader; -impl Gpwe9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe9 { - match self.bits { - false => Gpwe9::Gpwe0, - true => Gpwe9::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe9::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe9::Gpwe1 - } -} -#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] -pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; -impl<'a, REG> Gpwe9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe10 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] -pub type Gpwe10R = crate::BitReader; -impl Gpwe10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe10 { - match self.bits { - false => Gpwe10::Gpwe0, - true => Gpwe10::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe10::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe10::Gpwe1 - } -} -#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] -pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; -impl<'a, REG> Gpwe10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe11 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] -pub type Gpwe11R = crate::BitReader; -impl Gpwe11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe11 { - match self.bits { - false => Gpwe11::Gpwe0, - true => Gpwe11::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe11::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe11::Gpwe1 - } -} -#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] -pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; -impl<'a, REG> Gpwe11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe12 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] -pub type Gpwe12R = crate::BitReader; -impl Gpwe12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe12 { - match self.bits { - false => Gpwe12::Gpwe0, - true => Gpwe12::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe12::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe12::Gpwe1 - } -} -#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] -pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; -impl<'a, REG> Gpwe12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe13 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] -pub type Gpwe13R = crate::BitReader; -impl Gpwe13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe13 { - match self.bits { - false => Gpwe13::Gpwe0, - true => Gpwe13::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe13::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe13::Gpwe1 - } -} -#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] -pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; -impl<'a, REG> Gpwe13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe14 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] -pub type Gpwe14R = crate::BitReader; -impl Gpwe14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe14 { - match self.bits { - false => Gpwe14::Gpwe0, - true => Gpwe14::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe14::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe14::Gpwe1 - } -} -#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] -pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; -impl<'a, REG> Gpwe14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe15 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] -pub type Gpwe15R = crate::BitReader; -impl Gpwe15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe15 { - match self.bits { - false => Gpwe15::Gpwe0, - true => Gpwe15::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe15::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe15::Gpwe1 - } -} -#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] -pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; -impl<'a, REG> Gpwe15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&self) -> Gpwe0R { - Gpwe0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&self) -> Gpwe1R { - Gpwe1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&self) -> Gpwe2R { - Gpwe2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&self) -> Gpwe3R { - Gpwe3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&self) -> Gpwe4R { - Gpwe4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&self) -> Gpwe5R { - Gpwe5R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&self) -> Gpwe6R { - Gpwe6R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&self) -> Gpwe7R { - Gpwe7R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&self) -> Gpwe8R { - Gpwe8R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&self) -> Gpwe9R { - Gpwe9R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&self) -> Gpwe10R { - Gpwe10R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&self) -> Gpwe11R { - Gpwe11R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&self) -> Gpwe12R { - Gpwe12R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&self) -> Gpwe13R { - Gpwe13R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&self) -> Gpwe14R { - Gpwe14R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&self) -> Gpwe15R { - Gpwe15R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&mut self) -> Gpwe0W { - Gpwe0W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&mut self) -> Gpwe1W { - Gpwe1W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&mut self) -> Gpwe2W { - Gpwe2W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&mut self) -> Gpwe3W { - Gpwe3W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&mut self) -> Gpwe4W { - Gpwe4W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&mut self) -> Gpwe5W { - Gpwe5W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&mut self) -> Gpwe6W { - Gpwe6W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&mut self) -> Gpwe7W { - Gpwe7W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&mut self) -> Gpwe8W { - Gpwe8W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&mut self) -> Gpwe9W { - Gpwe9W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&mut self) -> Gpwe10W { - Gpwe10W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&mut self) -> Gpwe11W { - Gpwe11W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&mut self) -> Gpwe12W { - Gpwe12W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&mut self) -> Gpwe13W { - Gpwe13W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&mut self) -> Gpwe14W { - Gpwe14W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&mut self) -> Gpwe15W { - Gpwe15W::new(self, 31) - } -} -#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpclrSpec; -impl crate::RegisterSpec for GpclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] -impl crate::Readable for GpclrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] -impl crate::Writable for GpclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCLR to value 0"] -impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port2/pcr0.rs b/mcxa276-pac/src/port2/pcr0.rs deleted file mode 100644 index 673ac781a..000000000 --- a/mcxa276-pac/src/port2/pcr0.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR0` reader"] -pub type R = crate::R; -#[doc = "Register `PCR0` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr0Spec; -impl crate::RegisterSpec for Pcr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] -impl crate::Readable for Pcr0Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] -impl crate::Writable for Pcr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR0 to value 0"] -impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port2/pcr1.rs b/mcxa276-pac/src/port2/pcr1.rs deleted file mode 100644 index 658d2dec6..000000000 --- a/mcxa276-pac/src/port2/pcr1.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR1` reader"] -pub type R = crate::R; -#[doc = "Register `PCR1` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr1Spec; -impl crate::RegisterSpec for Pcr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] -impl crate::Readable for Pcr1Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] -impl crate::Writable for Pcr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR1 to value 0"] -impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port2/pcr10.rs b/mcxa276-pac/src/port2/pcr10.rs deleted file mode 100644 index c4f453255..000000000 --- a/mcxa276-pac/src/port2/pcr10.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR10` reader"] -pub type R = crate::R; -#[doc = "Register `PCR10` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr10Spec; -impl crate::RegisterSpec for Pcr10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] -impl crate::Readable for Pcr10Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] -impl crate::Writable for Pcr10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR10 to value 0"] -impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port2/pcr11.rs b/mcxa276-pac/src/port2/pcr11.rs deleted file mode 100644 index aba6888ef..000000000 --- a/mcxa276-pac/src/port2/pcr11.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR11` reader"] -pub type R = crate::R; -#[doc = "Register `PCR11` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr11Spec; -impl crate::RegisterSpec for Pcr11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] -impl crate::Readable for Pcr11Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] -impl crate::Writable for Pcr11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR11 to value 0"] -impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port2/pcr12.rs b/mcxa276-pac/src/port2/pcr12.rs deleted file mode 100644 index 2cd7eecc1..000000000 --- a/mcxa276-pac/src/port2/pcr12.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR12` reader"] -pub type R = crate::R; -#[doc = "Register `PCR12` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr12Spec; -impl crate::RegisterSpec for Pcr12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] -impl crate::Readable for Pcr12Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] -impl crate::Writable for Pcr12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR12 to value 0"] -impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port2/pcr13.rs b/mcxa276-pac/src/port2/pcr13.rs deleted file mode 100644 index 0da9c8d55..000000000 --- a/mcxa276-pac/src/port2/pcr13.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR13` reader"] -pub type R = crate::R; -#[doc = "Register `PCR13` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr13Spec; -impl crate::RegisterSpec for Pcr13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] -impl crate::Readable for Pcr13Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] -impl crate::Writable for Pcr13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR13 to value 0"] -impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port2/pcr14.rs b/mcxa276-pac/src/port2/pcr14.rs deleted file mode 100644 index 8f9a8684c..000000000 --- a/mcxa276-pac/src/port2/pcr14.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR14` reader"] -pub type R = crate::R; -#[doc = "Register `PCR14` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr14Spec; -impl crate::RegisterSpec for Pcr14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] -impl crate::Readable for Pcr14Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] -impl crate::Writable for Pcr14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR14 to value 0"] -impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port2/pcr15.rs b/mcxa276-pac/src/port2/pcr15.rs deleted file mode 100644 index 85c188f6b..000000000 --- a/mcxa276-pac/src/port2/pcr15.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR15` reader"] -pub type R = crate::R; -#[doc = "Register `PCR15` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr15Spec; -impl crate::RegisterSpec for Pcr15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] -impl crate::Readable for Pcr15Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] -impl crate::Writable for Pcr15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR15 to value 0"] -impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port2/pcr16.rs b/mcxa276-pac/src/port2/pcr16.rs deleted file mode 100644 index 70c9dda78..000000000 --- a/mcxa276-pac/src/port2/pcr16.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR16` reader"] -pub type R = crate::R; -#[doc = "Register `PCR16` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr16Spec; -impl crate::RegisterSpec for Pcr16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] -impl crate::Readable for Pcr16Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] -impl crate::Writable for Pcr16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR16 to value 0"] -impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port2/pcr17.rs b/mcxa276-pac/src/port2/pcr17.rs deleted file mode 100644 index 6e9da55ac..000000000 --- a/mcxa276-pac/src/port2/pcr17.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR17` reader"] -pub type R = crate::R; -#[doc = "Register `PCR17` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr17Spec; -impl crate::RegisterSpec for Pcr17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] -impl crate::Readable for Pcr17Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] -impl crate::Writable for Pcr17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR17 to value 0"] -impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port2/pcr18.rs b/mcxa276-pac/src/port2/pcr18.rs deleted file mode 100644 index 9aad79b05..000000000 --- a/mcxa276-pac/src/port2/pcr18.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR18` reader"] -pub type R = crate::R; -#[doc = "Register `PCR18` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr18Spec; -impl crate::RegisterSpec for Pcr18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] -impl crate::Readable for Pcr18Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] -impl crate::Writable for Pcr18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR18 to value 0"] -impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port2/pcr19.rs b/mcxa276-pac/src/port2/pcr19.rs deleted file mode 100644 index 43bb23f08..000000000 --- a/mcxa276-pac/src/port2/pcr19.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR19` reader"] -pub type R = crate::R; -#[doc = "Register `PCR19` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr19Spec; -impl crate::RegisterSpec for Pcr19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] -impl crate::Readable for Pcr19Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] -impl crate::Writable for Pcr19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR19 to value 0"] -impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port2/pcr2.rs b/mcxa276-pac/src/port2/pcr2.rs deleted file mode 100644 index 2bdea035c..000000000 --- a/mcxa276-pac/src/port2/pcr2.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR2` reader"] -pub type R = crate::R; -#[doc = "Register `PCR2` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr2Spec; -impl crate::RegisterSpec for Pcr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] -impl crate::Readable for Pcr2Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] -impl crate::Writable for Pcr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR2 to value 0"] -impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port2/pcr20.rs b/mcxa276-pac/src/port2/pcr20.rs deleted file mode 100644 index d1a076a4a..000000000 --- a/mcxa276-pac/src/port2/pcr20.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR20` reader"] -pub type R = crate::R; -#[doc = "Register `PCR20` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr20Spec; -impl crate::RegisterSpec for Pcr20Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] -impl crate::Readable for Pcr20Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] -impl crate::Writable for Pcr20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR20 to value 0"] -impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port2/pcr21.rs b/mcxa276-pac/src/port2/pcr21.rs deleted file mode 100644 index 1ec184fea..000000000 --- a/mcxa276-pac/src/port2/pcr21.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR21` reader"] -pub type R = crate::R; -#[doc = "Register `PCR21` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr21Spec; -impl crate::RegisterSpec for Pcr21Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] -impl crate::Readable for Pcr21Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] -impl crate::Writable for Pcr21Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR21 to value 0"] -impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port2/pcr22.rs b/mcxa276-pac/src/port2/pcr22.rs deleted file mode 100644 index 9da7aaab1..000000000 --- a/mcxa276-pac/src/port2/pcr22.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR22` reader"] -pub type R = crate::R; -#[doc = "Register `PCR22` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr22Spec; -impl crate::RegisterSpec for Pcr22Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] -impl crate::Readable for Pcr22Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] -impl crate::Writable for Pcr22Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR22 to value 0"] -impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port2/pcr23.rs b/mcxa276-pac/src/port2/pcr23.rs deleted file mode 100644 index d8bb46a64..000000000 --- a/mcxa276-pac/src/port2/pcr23.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR23` reader"] -pub type R = crate::R; -#[doc = "Register `PCR23` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr23Spec; -impl crate::RegisterSpec for Pcr23Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] -impl crate::Readable for Pcr23Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] -impl crate::Writable for Pcr23Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR23 to value 0"] -impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port2/pcr24.rs b/mcxa276-pac/src/port2/pcr24.rs deleted file mode 100644 index e9e31834d..000000000 --- a/mcxa276-pac/src/port2/pcr24.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR24` reader"] -pub type R = crate::R; -#[doc = "Register `PCR24` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr24Spec; -impl crate::RegisterSpec for Pcr24Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] -impl crate::Readable for Pcr24Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] -impl crate::Writable for Pcr24Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR24 to value 0"] -impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port2/pcr25.rs b/mcxa276-pac/src/port2/pcr25.rs deleted file mode 100644 index 5d0319242..000000000 --- a/mcxa276-pac/src/port2/pcr25.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR25` reader"] -pub type R = crate::R; -#[doc = "Register `PCR25` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr25Spec; -impl crate::RegisterSpec for Pcr25Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] -impl crate::Readable for Pcr25Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] -impl crate::Writable for Pcr25Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR25 to value 0"] -impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port2/pcr26.rs b/mcxa276-pac/src/port2/pcr26.rs deleted file mode 100644 index 1554cb836..000000000 --- a/mcxa276-pac/src/port2/pcr26.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR26` reader"] -pub type R = crate::R; -#[doc = "Register `PCR26` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr26Spec; -impl crate::RegisterSpec for Pcr26Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] -impl crate::Readable for Pcr26Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] -impl crate::Writable for Pcr26Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR26 to value 0"] -impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port2/pcr27.rs b/mcxa276-pac/src/port2/pcr27.rs deleted file mode 100644 index ac4a51d32..000000000 --- a/mcxa276-pac/src/port2/pcr27.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR27` reader"] -pub type R = crate::R; -#[doc = "Register `PCR27` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr27Spec; -impl crate::RegisterSpec for Pcr27Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] -impl crate::Readable for Pcr27Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] -impl crate::Writable for Pcr27Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR27 to value 0"] -impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port2/pcr28.rs b/mcxa276-pac/src/port2/pcr28.rs deleted file mode 100644 index 1315078be..000000000 --- a/mcxa276-pac/src/port2/pcr28.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR28` reader"] -pub type R = crate::R; -#[doc = "Register `PCR28` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr28Spec; -impl crate::RegisterSpec for Pcr28Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] -impl crate::Readable for Pcr28Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] -impl crate::Writable for Pcr28Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR28 to value 0"] -impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port2/pcr29.rs b/mcxa276-pac/src/port2/pcr29.rs deleted file mode 100644 index de7c41baa..000000000 --- a/mcxa276-pac/src/port2/pcr29.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR29` reader"] -pub type R = crate::R; -#[doc = "Register `PCR29` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr29Spec; -impl crate::RegisterSpec for Pcr29Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] -impl crate::Readable for Pcr29Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] -impl crate::Writable for Pcr29Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR29 to value 0"] -impl crate::Resettable for Pcr29Spec {} diff --git a/mcxa276-pac/src/port2/pcr3.rs b/mcxa276-pac/src/port2/pcr3.rs deleted file mode 100644 index 0bdf66c1b..000000000 --- a/mcxa276-pac/src/port2/pcr3.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR3` reader"] -pub type R = crate::R; -#[doc = "Register `PCR3` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr3Spec; -impl crate::RegisterSpec for Pcr3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] -impl crate::Readable for Pcr3Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] -impl crate::Writable for Pcr3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR3 to value 0"] -impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port2/pcr30.rs b/mcxa276-pac/src/port2/pcr30.rs deleted file mode 100644 index cce4166f4..000000000 --- a/mcxa276-pac/src/port2/pcr30.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR30` reader"] -pub type R = crate::R; -#[doc = "Register `PCR30` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr30Spec; -impl crate::RegisterSpec for Pcr30Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] -impl crate::Readable for Pcr30Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] -impl crate::Writable for Pcr30Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR30 to value 0"] -impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port2/pcr31.rs b/mcxa276-pac/src/port2/pcr31.rs deleted file mode 100644 index 1f49159c2..000000000 --- a/mcxa276-pac/src/port2/pcr31.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR31` reader"] -pub type R = crate::R; -#[doc = "Register `PCR31` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr31Spec; -impl crate::RegisterSpec for Pcr31Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] -impl crate::Readable for Pcr31Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] -impl crate::Writable for Pcr31Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR31 to value 0"] -impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port2/pcr4.rs b/mcxa276-pac/src/port2/pcr4.rs deleted file mode 100644 index 970ee4531..000000000 --- a/mcxa276-pac/src/port2/pcr4.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR4` reader"] -pub type R = crate::R; -#[doc = "Register `PCR4` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr4Spec; -impl crate::RegisterSpec for Pcr4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] -impl crate::Readable for Pcr4Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] -impl crate::Writable for Pcr4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR4 to value 0"] -impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port2/pcr5.rs b/mcxa276-pac/src/port2/pcr5.rs deleted file mode 100644 index 53dad0e29..000000000 --- a/mcxa276-pac/src/port2/pcr5.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR5` reader"] -pub type R = crate::R; -#[doc = "Register `PCR5` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr5Spec; -impl crate::RegisterSpec for Pcr5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] -impl crate::Readable for Pcr5Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] -impl crate::Writable for Pcr5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR5 to value 0"] -impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port2/pcr6.rs b/mcxa276-pac/src/port2/pcr6.rs deleted file mode 100644 index d10e6a5b8..000000000 --- a/mcxa276-pac/src/port2/pcr6.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR6` reader"] -pub type R = crate::R; -#[doc = "Register `PCR6` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr6Spec; -impl crate::RegisterSpec for Pcr6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] -impl crate::Readable for Pcr6Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] -impl crate::Writable for Pcr6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR6 to value 0"] -impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port2/pcr7.rs b/mcxa276-pac/src/port2/pcr7.rs deleted file mode 100644 index 71a9e66da..000000000 --- a/mcxa276-pac/src/port2/pcr7.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR7` reader"] -pub type R = crate::R; -#[doc = "Register `PCR7` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr7Spec; -impl crate::RegisterSpec for Pcr7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] -impl crate::Readable for Pcr7Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] -impl crate::Writable for Pcr7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR7 to value 0"] -impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port2/pcr8.rs b/mcxa276-pac/src/port2/pcr8.rs deleted file mode 100644 index c4c474965..000000000 --- a/mcxa276-pac/src/port2/pcr8.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR8` reader"] -pub type R = crate::R; -#[doc = "Register `PCR8` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr8Spec; -impl crate::RegisterSpec for Pcr8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] -impl crate::Readable for Pcr8Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] -impl crate::Writable for Pcr8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR8 to value 0"] -impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port2/pcr9.rs b/mcxa276-pac/src/port2/pcr9.rs deleted file mode 100644 index 92a28f062..000000000 --- a/mcxa276-pac/src/port2/pcr9.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR9` reader"] -pub type R = crate::R; -#[doc = "Register `PCR9` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr9Spec; -impl crate::RegisterSpec for Pcr9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] -impl crate::Readable for Pcr9Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] -impl crate::Writable for Pcr9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR9 to value 0"] -impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port2/verid.rs b/mcxa276-pac/src/port2/verid.rs deleted file mode 100644 index 330f53d57..000000000 --- a/mcxa276-pac/src/port2/verid.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Basic implementation"] - Feature0 = 0, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Feature0), - _ => None, - } - } - #[doc = "Basic implementation"] - #[inline(always)] - pub fn is_feature0(&self) -> bool { - *self == Feature::Feature0 - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0200_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0200_0000; -} diff --git a/mcxa276-pac/src/port3.rs b/mcxa276-pac/src/port3.rs deleted file mode 100644 index d7ed05fc0..000000000 --- a/mcxa276-pac/src/port3.rs +++ /dev/null @@ -1,428 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x0c], - gpclr: Gpclr, - gpchr: Gpchr, - _reserved3: [u8; 0x08], - config: Config, - _reserved4: [u8; 0x3c], - calib0: Calib0, - calib1: Calib1, - _reserved6: [u8; 0x18], - pcr0: Pcr0, - pcr1: Pcr1, - pcr2: Pcr2, - pcr3: Pcr3, - pcr4: Pcr4, - pcr5: Pcr5, - pcr6: Pcr6, - pcr7: Pcr7, - pcr8: Pcr8, - pcr9: Pcr9, - pcr10: Pcr10, - pcr11: Pcr11, - pcr12: Pcr12, - pcr13: Pcr13, - pcr14: Pcr14, - pcr15: Pcr15, - pcr16: Pcr16, - pcr17: Pcr17, - pcr18: Pcr18, - pcr19: Pcr19, - pcr20: Pcr20, - pcr21: Pcr21, - pcr22: Pcr22, - pcr23: Pcr23, - pcr24: Pcr24, - pcr25: Pcr25, - pcr26: Pcr26, - pcr27: Pcr27, - pcr28: Pcr28, - pcr29: Pcr29, - pcr30: Pcr30, - pcr31: Pcr31, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x10 - Global Pin Control Low"] - #[inline(always)] - pub const fn gpclr(&self) -> &Gpclr { - &self.gpclr - } - #[doc = "0x14 - Global Pin Control High"] - #[inline(always)] - pub const fn gpchr(&self) -> &Gpchr { - &self.gpchr - } - #[doc = "0x20 - Configuration"] - #[inline(always)] - pub const fn config(&self) -> &Config { - &self.config - } - #[doc = "0x60 - Calibration 0"] - #[inline(always)] - pub const fn calib0(&self) -> &Calib0 { - &self.calib0 - } - #[doc = "0x64 - Calibration 1"] - #[inline(always)] - pub const fn calib1(&self) -> &Calib1 { - &self.calib1 - } - #[doc = "0x80 - Pin Control 0"] - #[inline(always)] - pub const fn pcr0(&self) -> &Pcr0 { - &self.pcr0 - } - #[doc = "0x84 - Pin Control 1"] - #[inline(always)] - pub const fn pcr1(&self) -> &Pcr1 { - &self.pcr1 - } - #[doc = "0x88 - Pin Control 2"] - #[inline(always)] - pub const fn pcr2(&self) -> &Pcr2 { - &self.pcr2 - } - #[doc = "0x8c - Pin Control 3"] - #[inline(always)] - pub const fn pcr3(&self) -> &Pcr3 { - &self.pcr3 - } - #[doc = "0x90 - Pin Control 4"] - #[inline(always)] - pub const fn pcr4(&self) -> &Pcr4 { - &self.pcr4 - } - #[doc = "0x94 - Pin Control 5"] - #[inline(always)] - pub const fn pcr5(&self) -> &Pcr5 { - &self.pcr5 - } - #[doc = "0x98 - Pin Control 6"] - #[inline(always)] - pub const fn pcr6(&self) -> &Pcr6 { - &self.pcr6 - } - #[doc = "0x9c - Pin Control 7"] - #[inline(always)] - pub const fn pcr7(&self) -> &Pcr7 { - &self.pcr7 - } - #[doc = "0xa0 - Pin Control 8"] - #[inline(always)] - pub const fn pcr8(&self) -> &Pcr8 { - &self.pcr8 - } - #[doc = "0xa4 - Pin Control 9"] - #[inline(always)] - pub const fn pcr9(&self) -> &Pcr9 { - &self.pcr9 - } - #[doc = "0xa8 - Pin Control 10"] - #[inline(always)] - pub const fn pcr10(&self) -> &Pcr10 { - &self.pcr10 - } - #[doc = "0xac - Pin Control 11"] - #[inline(always)] - pub const fn pcr11(&self) -> &Pcr11 { - &self.pcr11 - } - #[doc = "0xb0 - Pin Control 12"] - #[inline(always)] - pub const fn pcr12(&self) -> &Pcr12 { - &self.pcr12 - } - #[doc = "0xb4 - Pin Control 13"] - #[inline(always)] - pub const fn pcr13(&self) -> &Pcr13 { - &self.pcr13 - } - #[doc = "0xb8 - Pin Control 14"] - #[inline(always)] - pub const fn pcr14(&self) -> &Pcr14 { - &self.pcr14 - } - #[doc = "0xbc - Pin Control 15"] - #[inline(always)] - pub const fn pcr15(&self) -> &Pcr15 { - &self.pcr15 - } - #[doc = "0xc0 - Pin Control 16"] - #[inline(always)] - pub const fn pcr16(&self) -> &Pcr16 { - &self.pcr16 - } - #[doc = "0xc4 - Pin Control 17"] - #[inline(always)] - pub const fn pcr17(&self) -> &Pcr17 { - &self.pcr17 - } - #[doc = "0xc8 - Pin Control 18"] - #[inline(always)] - pub const fn pcr18(&self) -> &Pcr18 { - &self.pcr18 - } - #[doc = "0xcc - Pin Control 19"] - #[inline(always)] - pub const fn pcr19(&self) -> &Pcr19 { - &self.pcr19 - } - #[doc = "0xd0 - Pin Control 20"] - #[inline(always)] - pub const fn pcr20(&self) -> &Pcr20 { - &self.pcr20 - } - #[doc = "0xd4 - Pin Control 21"] - #[inline(always)] - pub const fn pcr21(&self) -> &Pcr21 { - &self.pcr21 - } - #[doc = "0xd8 - Pin Control 22"] - #[inline(always)] - pub const fn pcr22(&self) -> &Pcr22 { - &self.pcr22 - } - #[doc = "0xdc - Pin Control 23"] - #[inline(always)] - pub const fn pcr23(&self) -> &Pcr23 { - &self.pcr23 - } - #[doc = "0xe0 - Pin Control 24"] - #[inline(always)] - pub const fn pcr24(&self) -> &Pcr24 { - &self.pcr24 - } - #[doc = "0xe4 - Pin Control 25"] - #[inline(always)] - pub const fn pcr25(&self) -> &Pcr25 { - &self.pcr25 - } - #[doc = "0xe8 - Pin Control 26"] - #[inline(always)] - pub const fn pcr26(&self) -> &Pcr26 { - &self.pcr26 - } - #[doc = "0xec - Pin Control 27"] - #[inline(always)] - pub const fn pcr27(&self) -> &Pcr27 { - &self.pcr27 - } - #[doc = "0xf0 - Pin Control 28"] - #[inline(always)] - pub const fn pcr28(&self) -> &Pcr28 { - &self.pcr28 - } - #[doc = "0xf4 - Pin Control 29"] - #[inline(always)] - pub const fn pcr29(&self) -> &Pcr29 { - &self.pcr29 - } - #[doc = "0xf8 - Pin Control 30"] - #[inline(always)] - pub const fn pcr30(&self) -> &Pcr30 { - &self.pcr30 - } - #[doc = "0xfc - Pin Control 31"] - #[inline(always)] - pub const fn pcr31(&self) -> &Pcr31 { - &self.pcr31 - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] -#[doc(alias = "GPCLR")] -pub type Gpclr = crate::Reg; -#[doc = "Global Pin Control Low"] -pub mod gpclr; -#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] -#[doc(alias = "GPCHR")] -pub type Gpchr = crate::Reg; -#[doc = "Global Pin Control High"] -pub mod gpchr; -#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] -#[doc(alias = "CONFIG")] -pub type Config = crate::Reg; -#[doc = "Configuration"] -pub mod config; -#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] -#[doc(alias = "CALIB0")] -pub type Calib0 = crate::Reg; -#[doc = "Calibration 0"] -pub mod calib0; -#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] -#[doc(alias = "CALIB1")] -pub type Calib1 = crate::Reg; -#[doc = "Calibration 1"] -pub mod calib1; -#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] -#[doc(alias = "PCR0")] -pub type Pcr0 = crate::Reg; -#[doc = "Pin Control 0"] -pub mod pcr0; -#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] -#[doc(alias = "PCR1")] -pub type Pcr1 = crate::Reg; -#[doc = "Pin Control 1"] -pub mod pcr1; -#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] -#[doc(alias = "PCR2")] -pub type Pcr2 = crate::Reg; -#[doc = "Pin Control 2"] -pub mod pcr2; -#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] -#[doc(alias = "PCR3")] -pub type Pcr3 = crate::Reg; -#[doc = "Pin Control 3"] -pub mod pcr3; -#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] -#[doc(alias = "PCR4")] -pub type Pcr4 = crate::Reg; -#[doc = "Pin Control 4"] -pub mod pcr4; -#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] -#[doc(alias = "PCR5")] -pub type Pcr5 = crate::Reg; -#[doc = "Pin Control 5"] -pub mod pcr5; -#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] -#[doc(alias = "PCR6")] -pub type Pcr6 = crate::Reg; -#[doc = "Pin Control 6"] -pub mod pcr6; -#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] -#[doc(alias = "PCR7")] -pub type Pcr7 = crate::Reg; -#[doc = "Pin Control 7"] -pub mod pcr7; -#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] -#[doc(alias = "PCR8")] -pub type Pcr8 = crate::Reg; -#[doc = "Pin Control 8"] -pub mod pcr8; -#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] -#[doc(alias = "PCR9")] -pub type Pcr9 = crate::Reg; -#[doc = "Pin Control 9"] -pub mod pcr9; -#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] -#[doc(alias = "PCR10")] -pub type Pcr10 = crate::Reg; -#[doc = "Pin Control 10"] -pub mod pcr10; -#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] -#[doc(alias = "PCR11")] -pub type Pcr11 = crate::Reg; -#[doc = "Pin Control 11"] -pub mod pcr11; -#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] -#[doc(alias = "PCR12")] -pub type Pcr12 = crate::Reg; -#[doc = "Pin Control 12"] -pub mod pcr12; -#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] -#[doc(alias = "PCR13")] -pub type Pcr13 = crate::Reg; -#[doc = "Pin Control 13"] -pub mod pcr13; -#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] -#[doc(alias = "PCR14")] -pub type Pcr14 = crate::Reg; -#[doc = "Pin Control 14"] -pub mod pcr14; -#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] -#[doc(alias = "PCR15")] -pub type Pcr15 = crate::Reg; -#[doc = "Pin Control 15"] -pub mod pcr15; -#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] -#[doc(alias = "PCR16")] -pub type Pcr16 = crate::Reg; -#[doc = "Pin Control 16"] -pub mod pcr16; -#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] -#[doc(alias = "PCR17")] -pub type Pcr17 = crate::Reg; -#[doc = "Pin Control 17"] -pub mod pcr17; -#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] -#[doc(alias = "PCR18")] -pub type Pcr18 = crate::Reg; -#[doc = "Pin Control 18"] -pub mod pcr18; -#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] -#[doc(alias = "PCR19")] -pub type Pcr19 = crate::Reg; -#[doc = "Pin Control 19"] -pub mod pcr19; -#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] -#[doc(alias = "PCR20")] -pub type Pcr20 = crate::Reg; -#[doc = "Pin Control 20"] -pub mod pcr20; -#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] -#[doc(alias = "PCR21")] -pub type Pcr21 = crate::Reg; -#[doc = "Pin Control 21"] -pub mod pcr21; -#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] -#[doc(alias = "PCR22")] -pub type Pcr22 = crate::Reg; -#[doc = "Pin Control 22"] -pub mod pcr22; -#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] -#[doc(alias = "PCR23")] -pub type Pcr23 = crate::Reg; -#[doc = "Pin Control 23"] -pub mod pcr23; -#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] -#[doc(alias = "PCR24")] -pub type Pcr24 = crate::Reg; -#[doc = "Pin Control 24"] -pub mod pcr24; -#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] -#[doc(alias = "PCR25")] -pub type Pcr25 = crate::Reg; -#[doc = "Pin Control 25"] -pub mod pcr25; -#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] -#[doc(alias = "PCR26")] -pub type Pcr26 = crate::Reg; -#[doc = "Pin Control 26"] -pub mod pcr26; -#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] -#[doc(alias = "PCR27")] -pub type Pcr27 = crate::Reg; -#[doc = "Pin Control 27"] -pub mod pcr27; -#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] -#[doc(alias = "PCR28")] -pub type Pcr28 = crate::Reg; -#[doc = "Pin Control 28"] -pub mod pcr28; -#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] -#[doc(alias = "PCR29")] -pub type Pcr29 = crate::Reg; -#[doc = "Pin Control 29"] -pub mod pcr29; -#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] -#[doc(alias = "PCR30")] -pub type Pcr30 = crate::Reg; -#[doc = "Pin Control 30"] -pub mod pcr30; -#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] -#[doc(alias = "PCR31")] -pub type Pcr31 = crate::Reg; -#[doc = "Pin Control 31"] -pub mod pcr31; diff --git a/mcxa276-pac/src/port3/calib0.rs b/mcxa276-pac/src/port3/calib0.rs deleted file mode 100644 index 029fa12f3..000000000 --- a/mcxa276-pac/src/port3/calib0.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB0` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB0` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib0Spec; -impl crate::RegisterSpec for Calib0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] -impl crate::Readable for Calib0Spec {} -#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] -impl crate::Writable for Calib0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB0 to value 0"] -impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port3/calib1.rs b/mcxa276-pac/src/port3/calib1.rs deleted file mode 100644 index e18f61234..000000000 --- a/mcxa276-pac/src/port3/calib1.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB1` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB1` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib1Spec; -impl crate::RegisterSpec for Calib1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] -impl crate::Readable for Calib1Spec {} -#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] -impl crate::Writable for Calib1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB1 to value 0"] -impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port3/config.rs b/mcxa276-pac/src/port3/config.rs deleted file mode 100644 index da92c5b27..000000000 --- a/mcxa276-pac/src/port3/config.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `CONFIG` reader"] -pub type R = crate::R; -#[doc = "Register `CONFIG` writer"] -pub type W = crate::W; -#[doc = "Port Voltage Range\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Range { - #[doc = "0: 1.71 V-3.6 V"] - Range0 = 0, - #[doc = "1: 2.70 V-3.6 V"] - Range1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Range) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RANGE` reader - Port Voltage Range"] -pub type RangeR = crate::BitReader; -impl RangeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Range { - match self.bits { - false => Range::Range0, - true => Range::Range1, - } - } - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn is_range0(&self) -> bool { - *self == Range::Range0 - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn is_range1(&self) -> bool { - *self == Range::Range1 - } -} -#[doc = "Field `RANGE` writer - Port Voltage Range"] -pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; -impl<'a, REG> RangeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn range0(self) -> &'a mut crate::W { - self.variant(Range::Range0) - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn range1(self) -> &'a mut crate::W { - self.variant(Range::Range1) - } -} -impl R { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&self) -> RangeR { - RangeR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&mut self) -> RangeW { - RangeW::new(self, 0) - } -} -#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ConfigSpec; -impl crate::RegisterSpec for ConfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`config::R`](R) reader structure"] -impl crate::Readable for ConfigSpec {} -#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] -impl crate::Writable for ConfigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CONFIG to value 0"] -impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port3/gpchr.rs b/mcxa276-pac/src/port3/gpchr.rs deleted file mode 100644 index af92d0d62..000000000 --- a/mcxa276-pac/src/port3/gpchr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCHR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCHR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe16 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] -pub type Gpwe16R = crate::BitReader; -impl Gpwe16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe16 { - match self.bits { - false => Gpwe16::Gpwe0, - true => Gpwe16::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe16::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe16::Gpwe1 - } -} -#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] -pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; -impl<'a, REG> Gpwe16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe17 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] -pub type Gpwe17R = crate::BitReader; -impl Gpwe17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe17 { - match self.bits { - false => Gpwe17::Gpwe0, - true => Gpwe17::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe17::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe17::Gpwe1 - } -} -#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] -pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; -impl<'a, REG> Gpwe17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe18 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] -pub type Gpwe18R = crate::BitReader; -impl Gpwe18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe18 { - match self.bits { - false => Gpwe18::Gpwe0, - true => Gpwe18::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe18::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe18::Gpwe1 - } -} -#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] -pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; -impl<'a, REG> Gpwe18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe19 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] -pub type Gpwe19R = crate::BitReader; -impl Gpwe19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe19 { - match self.bits { - false => Gpwe19::Gpwe0, - true => Gpwe19::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe19::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe19::Gpwe1 - } -} -#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] -pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; -impl<'a, REG> Gpwe19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe20 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] -pub type Gpwe20R = crate::BitReader; -impl Gpwe20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe20 { - match self.bits { - false => Gpwe20::Gpwe0, - true => Gpwe20::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe20::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe20::Gpwe1 - } -} -#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] -pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; -impl<'a, REG> Gpwe20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe21 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] -pub type Gpwe21R = crate::BitReader; -impl Gpwe21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe21 { - match self.bits { - false => Gpwe21::Gpwe0, - true => Gpwe21::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe21::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe21::Gpwe1 - } -} -#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] -pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; -impl<'a, REG> Gpwe21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe22 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] -pub type Gpwe22R = crate::BitReader; -impl Gpwe22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe22 { - match self.bits { - false => Gpwe22::Gpwe0, - true => Gpwe22::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe22::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe22::Gpwe1 - } -} -#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] -pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; -impl<'a, REG> Gpwe22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe23 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] -pub type Gpwe23R = crate::BitReader; -impl Gpwe23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe23 { - match self.bits { - false => Gpwe23::Gpwe0, - true => Gpwe23::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe23::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe23::Gpwe1 - } -} -#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] -pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; -impl<'a, REG> Gpwe23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe24 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] -pub type Gpwe24R = crate::BitReader; -impl Gpwe24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe24 { - match self.bits { - false => Gpwe24::Gpwe0, - true => Gpwe24::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe24::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe24::Gpwe1 - } -} -#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] -pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; -impl<'a, REG> Gpwe24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe25 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] -pub type Gpwe25R = crate::BitReader; -impl Gpwe25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe25 { - match self.bits { - false => Gpwe25::Gpwe0, - true => Gpwe25::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe25::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe25::Gpwe1 - } -} -#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] -pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; -impl<'a, REG> Gpwe25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe26 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] -pub type Gpwe26R = crate::BitReader; -impl Gpwe26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe26 { - match self.bits { - false => Gpwe26::Gpwe0, - true => Gpwe26::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe26::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe26::Gpwe1 - } -} -#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] -pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; -impl<'a, REG> Gpwe26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe27 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] -pub type Gpwe27R = crate::BitReader; -impl Gpwe27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe27 { - match self.bits { - false => Gpwe27::Gpwe0, - true => Gpwe27::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe27::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe27::Gpwe1 - } -} -#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] -pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; -impl<'a, REG> Gpwe27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe28 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] -pub type Gpwe28R = crate::BitReader; -impl Gpwe28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe28 { - match self.bits { - false => Gpwe28::Gpwe0, - true => Gpwe28::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe28::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe28::Gpwe1 - } -} -#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] -pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; -impl<'a, REG> Gpwe28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe29 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] -pub type Gpwe29R = crate::BitReader; -impl Gpwe29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe29 { - match self.bits { - false => Gpwe29::Gpwe0, - true => Gpwe29::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe29::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe29::Gpwe1 - } -} -#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] -pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; -impl<'a, REG> Gpwe29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe30 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] -pub type Gpwe30R = crate::BitReader; -impl Gpwe30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe30 { - match self.bits { - false => Gpwe30::Gpwe0, - true => Gpwe30::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe30::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe30::Gpwe1 - } -} -#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] -pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; -impl<'a, REG> Gpwe30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe31 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] -pub type Gpwe31R = crate::BitReader; -impl Gpwe31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe31 { - match self.bits { - false => Gpwe31::Gpwe0, - true => Gpwe31::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe31::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe31::Gpwe1 - } -} -#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] -pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; -impl<'a, REG> Gpwe31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&self) -> Gpwe16R { - Gpwe16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&self) -> Gpwe17R { - Gpwe17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&self) -> Gpwe18R { - Gpwe18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&self) -> Gpwe19R { - Gpwe19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&self) -> Gpwe20R { - Gpwe20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&self) -> Gpwe21R { - Gpwe21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&self) -> Gpwe22R { - Gpwe22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&self) -> Gpwe23R { - Gpwe23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&self) -> Gpwe24R { - Gpwe24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&self) -> Gpwe25R { - Gpwe25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&self) -> Gpwe26R { - Gpwe26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&self) -> Gpwe27R { - Gpwe27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&self) -> Gpwe28R { - Gpwe28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&self) -> Gpwe29R { - Gpwe29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&self) -> Gpwe30R { - Gpwe30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&self) -> Gpwe31R { - Gpwe31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&mut self) -> Gpwe16W { - Gpwe16W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&mut self) -> Gpwe17W { - Gpwe17W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&mut self) -> Gpwe18W { - Gpwe18W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&mut self) -> Gpwe19W { - Gpwe19W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&mut self) -> Gpwe20W { - Gpwe20W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&mut self) -> Gpwe21W { - Gpwe21W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&mut self) -> Gpwe22W { - Gpwe22W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&mut self) -> Gpwe23W { - Gpwe23W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&mut self) -> Gpwe24W { - Gpwe24W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&mut self) -> Gpwe25W { - Gpwe25W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&mut self) -> Gpwe26W { - Gpwe26W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&mut self) -> Gpwe27W { - Gpwe27W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&mut self) -> Gpwe28W { - Gpwe28W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&mut self) -> Gpwe29W { - Gpwe29W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&mut self) -> Gpwe30W { - Gpwe30W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&mut self) -> Gpwe31W { - Gpwe31W::new(self, 31) - } -} -#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpchrSpec; -impl crate::RegisterSpec for GpchrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] -impl crate::Readable for GpchrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] -impl crate::Writable for GpchrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCHR to value 0"] -impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port3/gpclr.rs b/mcxa276-pac/src/port3/gpclr.rs deleted file mode 100644 index 21e5ff23d..000000000 --- a/mcxa276-pac/src/port3/gpclr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCLR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCLR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe0 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] -pub type Gpwe0R = crate::BitReader; -impl Gpwe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe0 { - match self.bits { - false => Gpwe0::Gpwe0, - true => Gpwe0::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe0::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe0::Gpwe1 - } -} -#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] -pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; -impl<'a, REG> Gpwe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe1 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] -pub type Gpwe1R = crate::BitReader; -impl Gpwe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe1 { - match self.bits { - false => Gpwe1::Gpwe0, - true => Gpwe1::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe1::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe1::Gpwe1 - } -} -#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] -pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; -impl<'a, REG> Gpwe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe2 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] -pub type Gpwe2R = crate::BitReader; -impl Gpwe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe2 { - match self.bits { - false => Gpwe2::Gpwe0, - true => Gpwe2::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe2::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe2::Gpwe1 - } -} -#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] -pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; -impl<'a, REG> Gpwe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe3 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] -pub type Gpwe3R = crate::BitReader; -impl Gpwe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe3 { - match self.bits { - false => Gpwe3::Gpwe0, - true => Gpwe3::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe3::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe3::Gpwe1 - } -} -#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] -pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; -impl<'a, REG> Gpwe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe4 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] -pub type Gpwe4R = crate::BitReader; -impl Gpwe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe4 { - match self.bits { - false => Gpwe4::Gpwe0, - true => Gpwe4::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe4::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe4::Gpwe1 - } -} -#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] -pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; -impl<'a, REG> Gpwe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe5 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] -pub type Gpwe5R = crate::BitReader; -impl Gpwe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe5 { - match self.bits { - false => Gpwe5::Gpwe0, - true => Gpwe5::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe5::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe5::Gpwe1 - } -} -#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] -pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; -impl<'a, REG> Gpwe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe6 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] -pub type Gpwe6R = crate::BitReader; -impl Gpwe6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe6 { - match self.bits { - false => Gpwe6::Gpwe0, - true => Gpwe6::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe6::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe6::Gpwe1 - } -} -#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] -pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; -impl<'a, REG> Gpwe6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe7 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] -pub type Gpwe7R = crate::BitReader; -impl Gpwe7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe7 { - match self.bits { - false => Gpwe7::Gpwe0, - true => Gpwe7::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe7::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe7::Gpwe1 - } -} -#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] -pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; -impl<'a, REG> Gpwe7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe8 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] -pub type Gpwe8R = crate::BitReader; -impl Gpwe8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe8 { - match self.bits { - false => Gpwe8::Gpwe0, - true => Gpwe8::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe8::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe8::Gpwe1 - } -} -#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] -pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; -impl<'a, REG> Gpwe8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe9 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] -pub type Gpwe9R = crate::BitReader; -impl Gpwe9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe9 { - match self.bits { - false => Gpwe9::Gpwe0, - true => Gpwe9::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe9::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe9::Gpwe1 - } -} -#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] -pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; -impl<'a, REG> Gpwe9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe10 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] -pub type Gpwe10R = crate::BitReader; -impl Gpwe10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe10 { - match self.bits { - false => Gpwe10::Gpwe0, - true => Gpwe10::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe10::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe10::Gpwe1 - } -} -#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] -pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; -impl<'a, REG> Gpwe10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe11 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] -pub type Gpwe11R = crate::BitReader; -impl Gpwe11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe11 { - match self.bits { - false => Gpwe11::Gpwe0, - true => Gpwe11::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe11::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe11::Gpwe1 - } -} -#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] -pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; -impl<'a, REG> Gpwe11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe12 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] -pub type Gpwe12R = crate::BitReader; -impl Gpwe12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe12 { - match self.bits { - false => Gpwe12::Gpwe0, - true => Gpwe12::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe12::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe12::Gpwe1 - } -} -#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] -pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; -impl<'a, REG> Gpwe12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe13 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] -pub type Gpwe13R = crate::BitReader; -impl Gpwe13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe13 { - match self.bits { - false => Gpwe13::Gpwe0, - true => Gpwe13::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe13::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe13::Gpwe1 - } -} -#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] -pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; -impl<'a, REG> Gpwe13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe14 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] -pub type Gpwe14R = crate::BitReader; -impl Gpwe14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe14 { - match self.bits { - false => Gpwe14::Gpwe0, - true => Gpwe14::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe14::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe14::Gpwe1 - } -} -#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] -pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; -impl<'a, REG> Gpwe14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe15 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] -pub type Gpwe15R = crate::BitReader; -impl Gpwe15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe15 { - match self.bits { - false => Gpwe15::Gpwe0, - true => Gpwe15::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe15::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe15::Gpwe1 - } -} -#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] -pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; -impl<'a, REG> Gpwe15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&self) -> Gpwe0R { - Gpwe0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&self) -> Gpwe1R { - Gpwe1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&self) -> Gpwe2R { - Gpwe2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&self) -> Gpwe3R { - Gpwe3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&self) -> Gpwe4R { - Gpwe4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&self) -> Gpwe5R { - Gpwe5R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&self) -> Gpwe6R { - Gpwe6R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&self) -> Gpwe7R { - Gpwe7R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&self) -> Gpwe8R { - Gpwe8R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&self) -> Gpwe9R { - Gpwe9R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&self) -> Gpwe10R { - Gpwe10R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&self) -> Gpwe11R { - Gpwe11R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&self) -> Gpwe12R { - Gpwe12R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&self) -> Gpwe13R { - Gpwe13R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&self) -> Gpwe14R { - Gpwe14R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&self) -> Gpwe15R { - Gpwe15R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&mut self) -> Gpwe0W { - Gpwe0W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&mut self) -> Gpwe1W { - Gpwe1W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&mut self) -> Gpwe2W { - Gpwe2W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&mut self) -> Gpwe3W { - Gpwe3W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&mut self) -> Gpwe4W { - Gpwe4W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&mut self) -> Gpwe5W { - Gpwe5W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&mut self) -> Gpwe6W { - Gpwe6W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&mut self) -> Gpwe7W { - Gpwe7W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&mut self) -> Gpwe8W { - Gpwe8W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&mut self) -> Gpwe9W { - Gpwe9W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&mut self) -> Gpwe10W { - Gpwe10W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&mut self) -> Gpwe11W { - Gpwe11W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&mut self) -> Gpwe12W { - Gpwe12W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&mut self) -> Gpwe13W { - Gpwe13W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&mut self) -> Gpwe14W { - Gpwe14W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&mut self) -> Gpwe15W { - Gpwe15W::new(self, 31) - } -} -#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpclrSpec; -impl crate::RegisterSpec for GpclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] -impl crate::Readable for GpclrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] -impl crate::Writable for GpclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCLR to value 0"] -impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port3/pcr0.rs b/mcxa276-pac/src/port3/pcr0.rs deleted file mode 100644 index d2e60dc8d..000000000 --- a/mcxa276-pac/src/port3/pcr0.rs +++ /dev/null @@ -1,877 +0,0 @@ -#[doc = "Register `PCR0` reader"] -pub type R = crate::R; -#[doc = "Register `PCR0` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr0Spec; -impl crate::RegisterSpec for Pcr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] -impl crate::Readable for Pcr0Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] -impl crate::Writable for Pcr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR0 to value 0"] -impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port3/pcr1.rs b/mcxa276-pac/src/port3/pcr1.rs deleted file mode 100644 index 73aa72974..000000000 --- a/mcxa276-pac/src/port3/pcr1.rs +++ /dev/null @@ -1,877 +0,0 @@ -#[doc = "Register `PCR1` reader"] -pub type R = crate::R; -#[doc = "Register `PCR1` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Passive Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pfe { - #[doc = "0: Disables"] - Pfe0 = 0, - #[doc = "1: Enables"] - Pfe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PFE` reader - Passive Filter Enable"] -pub type PfeR = crate::BitReader; -impl PfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pfe { - match self.bits { - false => Pfe::Pfe0, - true => Pfe::Pfe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pfe0(&self) -> bool { - *self == Pfe::Pfe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pfe1(&self) -> bool { - *self == Pfe::Pfe1 - } -} -#[doc = "Field `PFE` writer - Passive Filter Enable"] -pub type PfeW<'a, REG> = crate::BitWriter<'a, REG, Pfe>; -impl<'a, REG> PfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pfe0(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pfe1(self) -> &'a mut crate::W { - self.variant(Pfe::Pfe1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&self) -> PfeR { - PfeR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 4 - Passive Filter Enable"] - #[inline(always)] - pub fn pfe(&mut self) -> PfeW { - PfeW::new(self, 4) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr1Spec; -impl crate::RegisterSpec for Pcr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] -impl crate::Readable for Pcr1Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] -impl crate::Writable for Pcr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR1 to value 0"] -impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port3/pcr10.rs b/mcxa276-pac/src/port3/pcr10.rs deleted file mode 100644 index e5317eb0c..000000000 --- a/mcxa276-pac/src/port3/pcr10.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR10` reader"] -pub type R = crate::R; -#[doc = "Register `PCR10` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr10Spec; -impl crate::RegisterSpec for Pcr10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] -impl crate::Readable for Pcr10Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] -impl crate::Writable for Pcr10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR10 to value 0"] -impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port3/pcr11.rs b/mcxa276-pac/src/port3/pcr11.rs deleted file mode 100644 index bc47cbd2b..000000000 --- a/mcxa276-pac/src/port3/pcr11.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR11` reader"] -pub type R = crate::R; -#[doc = "Register `PCR11` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr11Spec; -impl crate::RegisterSpec for Pcr11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] -impl crate::Readable for Pcr11Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] -impl crate::Writable for Pcr11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR11 to value 0"] -impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port3/pcr12.rs b/mcxa276-pac/src/port3/pcr12.rs deleted file mode 100644 index 2cd7eecc1..000000000 --- a/mcxa276-pac/src/port3/pcr12.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR12` reader"] -pub type R = crate::R; -#[doc = "Register `PCR12` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr12Spec; -impl crate::RegisterSpec for Pcr12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] -impl crate::Readable for Pcr12Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] -impl crate::Writable for Pcr12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR12 to value 0"] -impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port3/pcr13.rs b/mcxa276-pac/src/port3/pcr13.rs deleted file mode 100644 index 0da9c8d55..000000000 --- a/mcxa276-pac/src/port3/pcr13.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR13` reader"] -pub type R = crate::R; -#[doc = "Register `PCR13` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr13Spec; -impl crate::RegisterSpec for Pcr13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] -impl crate::Readable for Pcr13Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] -impl crate::Writable for Pcr13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR13 to value 0"] -impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port3/pcr14.rs b/mcxa276-pac/src/port3/pcr14.rs deleted file mode 100644 index 553559b3f..000000000 --- a/mcxa276-pac/src/port3/pcr14.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR14` reader"] -pub type R = crate::R; -#[doc = "Register `PCR14` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr14Spec; -impl crate::RegisterSpec for Pcr14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] -impl crate::Readable for Pcr14Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] -impl crate::Writable for Pcr14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR14 to value 0"] -impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port3/pcr15.rs b/mcxa276-pac/src/port3/pcr15.rs deleted file mode 100644 index 85c188f6b..000000000 --- a/mcxa276-pac/src/port3/pcr15.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR15` reader"] -pub type R = crate::R; -#[doc = "Register `PCR15` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr15Spec; -impl crate::RegisterSpec for Pcr15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] -impl crate::Readable for Pcr15Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] -impl crate::Writable for Pcr15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR15 to value 0"] -impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port3/pcr16.rs b/mcxa276-pac/src/port3/pcr16.rs deleted file mode 100644 index 70c9dda78..000000000 --- a/mcxa276-pac/src/port3/pcr16.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR16` reader"] -pub type R = crate::R; -#[doc = "Register `PCR16` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr16Spec; -impl crate::RegisterSpec for Pcr16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] -impl crate::Readable for Pcr16Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] -impl crate::Writable for Pcr16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR16 to value 0"] -impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port3/pcr17.rs b/mcxa276-pac/src/port3/pcr17.rs deleted file mode 100644 index 2faf3487b..000000000 --- a/mcxa276-pac/src/port3/pcr17.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR17` reader"] -pub type R = crate::R; -#[doc = "Register `PCR17` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr17Spec; -impl crate::RegisterSpec for Pcr17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] -impl crate::Readable for Pcr17Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] -impl crate::Writable for Pcr17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR17 to value 0"] -impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port3/pcr18.rs b/mcxa276-pac/src/port3/pcr18.rs deleted file mode 100644 index 796f9eede..000000000 --- a/mcxa276-pac/src/port3/pcr18.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR18` reader"] -pub type R = crate::R; -#[doc = "Register `PCR18` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr18Spec; -impl crate::RegisterSpec for Pcr18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] -impl crate::Readable for Pcr18Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] -impl crate::Writable for Pcr18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR18 to value 0"] -impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port3/pcr19.rs b/mcxa276-pac/src/port3/pcr19.rs deleted file mode 100644 index 7b5da5c24..000000000 --- a/mcxa276-pac/src/port3/pcr19.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR19` reader"] -pub type R = crate::R; -#[doc = "Register `PCR19` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr19Spec; -impl crate::RegisterSpec for Pcr19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] -impl crate::Readable for Pcr19Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] -impl crate::Writable for Pcr19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR19 to value 0"] -impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port3/pcr2.rs b/mcxa276-pac/src/port3/pcr2.rs deleted file mode 100644 index 09359160e..000000000 --- a/mcxa276-pac/src/port3/pcr2.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR2` reader"] -pub type R = crate::R; -#[doc = "Register `PCR2` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr2Spec; -impl crate::RegisterSpec for Pcr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] -impl crate::Readable for Pcr2Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] -impl crate::Writable for Pcr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR2 to value 0"] -impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port3/pcr20.rs b/mcxa276-pac/src/port3/pcr20.rs deleted file mode 100644 index 20401202b..000000000 --- a/mcxa276-pac/src/port3/pcr20.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR20` reader"] -pub type R = crate::R; -#[doc = "Register `PCR20` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr20Spec; -impl crate::RegisterSpec for Pcr20Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] -impl crate::Readable for Pcr20Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] -impl crate::Writable for Pcr20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR20 to value 0"] -impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port3/pcr21.rs b/mcxa276-pac/src/port3/pcr21.rs deleted file mode 100644 index 9f6076615..000000000 --- a/mcxa276-pac/src/port3/pcr21.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR21` reader"] -pub type R = crate::R; -#[doc = "Register `PCR21` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr21Spec; -impl crate::RegisterSpec for Pcr21Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] -impl crate::Readable for Pcr21Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] -impl crate::Writable for Pcr21Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR21 to value 0"] -impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port3/pcr22.rs b/mcxa276-pac/src/port3/pcr22.rs deleted file mode 100644 index decbc02c0..000000000 --- a/mcxa276-pac/src/port3/pcr22.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR22` reader"] -pub type R = crate::R; -#[doc = "Register `PCR22` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr22Spec; -impl crate::RegisterSpec for Pcr22Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] -impl crate::Readable for Pcr22Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] -impl crate::Writable for Pcr22Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR22 to value 0"] -impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port3/pcr23.rs b/mcxa276-pac/src/port3/pcr23.rs deleted file mode 100644 index 640773d73..000000000 --- a/mcxa276-pac/src/port3/pcr23.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR23` reader"] -pub type R = crate::R; -#[doc = "Register `PCR23` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr23Spec; -impl crate::RegisterSpec for Pcr23Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] -impl crate::Readable for Pcr23Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] -impl crate::Writable for Pcr23Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR23 to value 0"] -impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port3/pcr24.rs b/mcxa276-pac/src/port3/pcr24.rs deleted file mode 100644 index fe34d2b88..000000000 --- a/mcxa276-pac/src/port3/pcr24.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR24` reader"] -pub type R = crate::R; -#[doc = "Register `PCR24` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr24Spec; -impl crate::RegisterSpec for Pcr24Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] -impl crate::Readable for Pcr24Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] -impl crate::Writable for Pcr24Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR24 to value 0"] -impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port3/pcr25.rs b/mcxa276-pac/src/port3/pcr25.rs deleted file mode 100644 index bf5b458bd..000000000 --- a/mcxa276-pac/src/port3/pcr25.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR25` reader"] -pub type R = crate::R; -#[doc = "Register `PCR25` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr25Spec; -impl crate::RegisterSpec for Pcr25Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] -impl crate::Readable for Pcr25Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] -impl crate::Writable for Pcr25Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR25 to value 0"] -impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port3/pcr26.rs b/mcxa276-pac/src/port3/pcr26.rs deleted file mode 100644 index cb9fb6d2b..000000000 --- a/mcxa276-pac/src/port3/pcr26.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR26` reader"] -pub type R = crate::R; -#[doc = "Register `PCR26` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr26Spec; -impl crate::RegisterSpec for Pcr26Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] -impl crate::Readable for Pcr26Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] -impl crate::Writable for Pcr26Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR26 to value 0"] -impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port3/pcr27.rs b/mcxa276-pac/src/port3/pcr27.rs deleted file mode 100644 index 69b0c629a..000000000 --- a/mcxa276-pac/src/port3/pcr27.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR27` reader"] -pub type R = crate::R; -#[doc = "Register `PCR27` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr27Spec; -impl crate::RegisterSpec for Pcr27Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] -impl crate::Readable for Pcr27Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] -impl crate::Writable for Pcr27Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR27 to value 0"] -impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port3/pcr28.rs b/mcxa276-pac/src/port3/pcr28.rs deleted file mode 100644 index 313d32bb7..000000000 --- a/mcxa276-pac/src/port3/pcr28.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR28` reader"] -pub type R = crate::R; -#[doc = "Register `PCR28` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse1 { - #[doc = "0: Normal"] - Dse10 = 0, - #[doc = "1: Double"] - Dse11 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE1` reader - Drive Strength Enable"] -pub type Dse1R = crate::BitReader; -impl Dse1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse1 { - match self.bits { - false => Dse1::Dse10, - true => Dse1::Dse11, - } - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_dse10(&self) -> bool { - *self == Dse1::Dse10 - } - #[doc = "Double"] - #[inline(always)] - pub fn is_dse11(&self) -> bool { - *self == Dse1::Dse11 - } -} -#[doc = "Field `DSE1` writer - Drive Strength Enable"] -pub type Dse1W<'a, REG> = crate::BitWriter<'a, REG, Dse1>; -impl<'a, REG> Dse1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal"] - #[inline(always)] - pub fn dse10(self) -> &'a mut crate::W { - self.variant(Dse1::Dse10) - } - #[doc = "Double"] - #[inline(always)] - pub fn dse11(self) -> &'a mut crate::W { - self.variant(Dse1::Dse11) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&self) -> Dse1R { - Dse1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 7 - Drive Strength Enable"] - #[inline(always)] - pub fn dse1(&mut self) -> Dse1W { - Dse1W::new(self, 7) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr28Spec; -impl crate::RegisterSpec for Pcr28Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] -impl crate::Readable for Pcr28Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] -impl crate::Writable for Pcr28Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR28 to value 0"] -impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port3/pcr29.rs b/mcxa276-pac/src/port3/pcr29.rs deleted file mode 100644 index 7c1f7f594..000000000 --- a/mcxa276-pac/src/port3/pcr29.rs +++ /dev/null @@ -1,816 +0,0 @@ -#[doc = "Register `PCR29` reader"] -pub type R = crate::R; -#[doc = "Register `PCR29` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr29Spec; -impl crate::RegisterSpec for Pcr29Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] -impl crate::Readable for Pcr29Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] -impl crate::Writable for Pcr29Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR29 to value 0x1103"] -impl crate::Resettable for Pcr29Spec { - const RESET_VALUE: u32 = 0x1103; -} diff --git a/mcxa276-pac/src/port3/pcr3.rs b/mcxa276-pac/src/port3/pcr3.rs deleted file mode 100644 index 0bdf66c1b..000000000 --- a/mcxa276-pac/src/port3/pcr3.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR3` reader"] -pub type R = crate::R; -#[doc = "Register `PCR3` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr3Spec; -impl crate::RegisterSpec for Pcr3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] -impl crate::Readable for Pcr3Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] -impl crate::Writable for Pcr3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR3 to value 0"] -impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port3/pcr30.rs b/mcxa276-pac/src/port3/pcr30.rs deleted file mode 100644 index 47270e810..000000000 --- a/mcxa276-pac/src/port3/pcr30.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR30` reader"] -pub type R = crate::R; -#[doc = "Register `PCR30` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr30Spec; -impl crate::RegisterSpec for Pcr30Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] -impl crate::Readable for Pcr30Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] -impl crate::Writable for Pcr30Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR30 to value 0"] -impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port3/pcr31.rs b/mcxa276-pac/src/port3/pcr31.rs deleted file mode 100644 index 71bccb343..000000000 --- a/mcxa276-pac/src/port3/pcr31.rs +++ /dev/null @@ -1,814 +0,0 @@ -#[doc = "Register `PCR31` reader"] -pub type R = crate::R; -#[doc = "Register `PCR31` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pv { - #[doc = "0: Low"] - Pv0 = 0, - #[doc = "1: High"] - Pv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PV` reader - Pull Value"] -pub type PvR = crate::BitReader; -impl PvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pv { - match self.bits { - false => Pv::Pv0, - true => Pv::Pv1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_pv0(&self) -> bool { - *self == Pv::Pv0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_pv1(&self) -> bool { - *self == Pv::Pv1 - } -} -#[doc = "Field `PV` writer - Pull Value"] -pub type PvW<'a, REG> = crate::BitWriter<'a, REG, Pv>; -impl<'a, REG> PvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn pv0(self) -> &'a mut crate::W { - self.variant(Pv::Pv0) - } - #[doc = "High"] - #[inline(always)] - pub fn pv1(self) -> &'a mut crate::W { - self.variant(Pv::Pv1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&self) -> PvR { - PvR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 2 - Pull Value"] - #[inline(always)] - pub fn pv(&mut self) -> PvW { - PvW::new(self, 2) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr31Spec; -impl crate::RegisterSpec for Pcr31Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] -impl crate::Readable for Pcr31Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] -impl crate::Writable for Pcr31Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR31 to value 0"] -impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port3/pcr4.rs b/mcxa276-pac/src/port3/pcr4.rs deleted file mode 100644 index 9890bb2d4..000000000 --- a/mcxa276-pac/src/port3/pcr4.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR4` reader"] -pub type R = crate::R; -#[doc = "Register `PCR4` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr4Spec; -impl crate::RegisterSpec for Pcr4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] -impl crate::Readable for Pcr4Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] -impl crate::Writable for Pcr4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR4 to value 0"] -impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port3/pcr5.rs b/mcxa276-pac/src/port3/pcr5.rs deleted file mode 100644 index bbc9bfc8a..000000000 --- a/mcxa276-pac/src/port3/pcr5.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR5` reader"] -pub type R = crate::R; -#[doc = "Register `PCR5` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr5Spec; -impl crate::RegisterSpec for Pcr5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] -impl crate::Readable for Pcr5Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] -impl crate::Writable for Pcr5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR5 to value 0"] -impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port3/pcr6.rs b/mcxa276-pac/src/port3/pcr6.rs deleted file mode 100644 index dcc6c56c6..000000000 --- a/mcxa276-pac/src/port3/pcr6.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR6` reader"] -pub type R = crate::R; -#[doc = "Register `PCR6` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr6Spec; -impl crate::RegisterSpec for Pcr6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] -impl crate::Readable for Pcr6Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] -impl crate::Writable for Pcr6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR6 to value 0"] -impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port3/pcr7.rs b/mcxa276-pac/src/port3/pcr7.rs deleted file mode 100644 index 71a9e66da..000000000 --- a/mcxa276-pac/src/port3/pcr7.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR7` reader"] -pub type R = crate::R; -#[doc = "Register `PCR7` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr7Spec; -impl crate::RegisterSpec for Pcr7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] -impl crate::Readable for Pcr7Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] -impl crate::Writable for Pcr7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR7 to value 0"] -impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port3/pcr8.rs b/mcxa276-pac/src/port3/pcr8.rs deleted file mode 100644 index 46cac643d..000000000 --- a/mcxa276-pac/src/port3/pcr8.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR8` reader"] -pub type R = crate::R; -#[doc = "Register `PCR8` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr8Spec; -impl crate::RegisterSpec for Pcr8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] -impl crate::Readable for Pcr8Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] -impl crate::Writable for Pcr8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR8 to value 0"] -impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port3/pcr9.rs b/mcxa276-pac/src/port3/pcr9.rs deleted file mode 100644 index d28f59209..000000000 --- a/mcxa276-pac/src/port3/pcr9.rs +++ /dev/null @@ -1,751 +0,0 @@ -#[doc = "Register `PCR9` reader"] -pub type R = crate::R; -#[doc = "Register `PCR9` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, - #[doc = "8: Alternative 8 (chip-specific)"] - Mux1000 = 8, - #[doc = "9: Alternative 9 (chip-specific)"] - Mux1001 = 9, - #[doc = "10: Alternative 10 (chip-specific)"] - Mux1010 = 10, - #[doc = "11: Alternative 11 (chip-specific)"] - Mux1011 = 11, - #[doc = "12: Alternative 12 (chip-specific)"] - Mux1100 = 12, - #[doc = "13: Alternative 13 (chip-specific)"] - Mux1101 = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mux::Mux00), - 1 => Some(Mux::Mux01), - 2 => Some(Mux::Mux10), - 3 => Some(Mux::Mux11), - 4 => Some(Mux::Mux100), - 5 => Some(Mux::Mux101), - 6 => Some(Mux::Mux110), - 7 => Some(Mux::Mux111), - 8 => Some(Mux::Mux1000), - 9 => Some(Mux::Mux1001), - 10 => Some(Mux::Mux1010), - 11 => Some(Mux::Mux1011), - 12 => Some(Mux::Mux1100), - 13 => Some(Mux::Mux1101), - _ => None, - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn is_mux1000(&self) -> bool { - *self == Mux::Mux1000 - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn is_mux1001(&self) -> bool { - *self == Mux::Mux1001 - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn is_mux1010(&self) -> bool { - *self == Mux::Mux1010 - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn is_mux1011(&self) -> bool { - *self == Mux::Mux1011 - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn is_mux1100(&self) -> bool { - *self == Mux::Mux1100 - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn is_mux1101(&self) -> bool { - *self == Mux::Mux1101 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 4, Mux>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } - #[doc = "Alternative 8 (chip-specific)"] - #[inline(always)] - pub fn mux1000(self) -> &'a mut crate::W { - self.variant(Mux::Mux1000) - } - #[doc = "Alternative 9 (chip-specific)"] - #[inline(always)] - pub fn mux1001(self) -> &'a mut crate::W { - self.variant(Mux::Mux1001) - } - #[doc = "Alternative 10 (chip-specific)"] - #[inline(always)] - pub fn mux1010(self) -> &'a mut crate::W { - self.variant(Mux::Mux1010) - } - #[doc = "Alternative 11 (chip-specific)"] - #[inline(always)] - pub fn mux1011(self) -> &'a mut crate::W { - self.variant(Mux::Mux1011) - } - #[doc = "Alternative 12 (chip-specific)"] - #[inline(always)] - pub fn mux1100(self) -> &'a mut crate::W { - self.variant(Mux::Mux1100) - } - #[doc = "Alternative 13 (chip-specific)"] - #[inline(always)] - pub fn mux1101(self) -> &'a mut crate::W { - self.variant(Mux::Mux1101) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:11 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr9Spec; -impl crate::RegisterSpec for Pcr9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] -impl crate::Readable for Pcr9Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] -impl crate::Writable for Pcr9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR9 to value 0"] -impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port3/verid.rs b/mcxa276-pac/src/port3/verid.rs deleted file mode 100644 index 330f53d57..000000000 --- a/mcxa276-pac/src/port3/verid.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Basic implementation"] - Feature0 = 0, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Feature0), - _ => None, - } - } - #[doc = "Basic implementation"] - #[inline(always)] - pub fn is_feature0(&self) -> bool { - *self == Feature::Feature0 - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0200_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0200_0000; -} diff --git a/mcxa276-pac/src/port4.rs b/mcxa276-pac/src/port4.rs deleted file mode 100644 index d7ed05fc0..000000000 --- a/mcxa276-pac/src/port4.rs +++ /dev/null @@ -1,428 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x0c], - gpclr: Gpclr, - gpchr: Gpchr, - _reserved3: [u8; 0x08], - config: Config, - _reserved4: [u8; 0x3c], - calib0: Calib0, - calib1: Calib1, - _reserved6: [u8; 0x18], - pcr0: Pcr0, - pcr1: Pcr1, - pcr2: Pcr2, - pcr3: Pcr3, - pcr4: Pcr4, - pcr5: Pcr5, - pcr6: Pcr6, - pcr7: Pcr7, - pcr8: Pcr8, - pcr9: Pcr9, - pcr10: Pcr10, - pcr11: Pcr11, - pcr12: Pcr12, - pcr13: Pcr13, - pcr14: Pcr14, - pcr15: Pcr15, - pcr16: Pcr16, - pcr17: Pcr17, - pcr18: Pcr18, - pcr19: Pcr19, - pcr20: Pcr20, - pcr21: Pcr21, - pcr22: Pcr22, - pcr23: Pcr23, - pcr24: Pcr24, - pcr25: Pcr25, - pcr26: Pcr26, - pcr27: Pcr27, - pcr28: Pcr28, - pcr29: Pcr29, - pcr30: Pcr30, - pcr31: Pcr31, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x10 - Global Pin Control Low"] - #[inline(always)] - pub const fn gpclr(&self) -> &Gpclr { - &self.gpclr - } - #[doc = "0x14 - Global Pin Control High"] - #[inline(always)] - pub const fn gpchr(&self) -> &Gpchr { - &self.gpchr - } - #[doc = "0x20 - Configuration"] - #[inline(always)] - pub const fn config(&self) -> &Config { - &self.config - } - #[doc = "0x60 - Calibration 0"] - #[inline(always)] - pub const fn calib0(&self) -> &Calib0 { - &self.calib0 - } - #[doc = "0x64 - Calibration 1"] - #[inline(always)] - pub const fn calib1(&self) -> &Calib1 { - &self.calib1 - } - #[doc = "0x80 - Pin Control 0"] - #[inline(always)] - pub const fn pcr0(&self) -> &Pcr0 { - &self.pcr0 - } - #[doc = "0x84 - Pin Control 1"] - #[inline(always)] - pub const fn pcr1(&self) -> &Pcr1 { - &self.pcr1 - } - #[doc = "0x88 - Pin Control 2"] - #[inline(always)] - pub const fn pcr2(&self) -> &Pcr2 { - &self.pcr2 - } - #[doc = "0x8c - Pin Control 3"] - #[inline(always)] - pub const fn pcr3(&self) -> &Pcr3 { - &self.pcr3 - } - #[doc = "0x90 - Pin Control 4"] - #[inline(always)] - pub const fn pcr4(&self) -> &Pcr4 { - &self.pcr4 - } - #[doc = "0x94 - Pin Control 5"] - #[inline(always)] - pub const fn pcr5(&self) -> &Pcr5 { - &self.pcr5 - } - #[doc = "0x98 - Pin Control 6"] - #[inline(always)] - pub const fn pcr6(&self) -> &Pcr6 { - &self.pcr6 - } - #[doc = "0x9c - Pin Control 7"] - #[inline(always)] - pub const fn pcr7(&self) -> &Pcr7 { - &self.pcr7 - } - #[doc = "0xa0 - Pin Control 8"] - #[inline(always)] - pub const fn pcr8(&self) -> &Pcr8 { - &self.pcr8 - } - #[doc = "0xa4 - Pin Control 9"] - #[inline(always)] - pub const fn pcr9(&self) -> &Pcr9 { - &self.pcr9 - } - #[doc = "0xa8 - Pin Control 10"] - #[inline(always)] - pub const fn pcr10(&self) -> &Pcr10 { - &self.pcr10 - } - #[doc = "0xac - Pin Control 11"] - #[inline(always)] - pub const fn pcr11(&self) -> &Pcr11 { - &self.pcr11 - } - #[doc = "0xb0 - Pin Control 12"] - #[inline(always)] - pub const fn pcr12(&self) -> &Pcr12 { - &self.pcr12 - } - #[doc = "0xb4 - Pin Control 13"] - #[inline(always)] - pub const fn pcr13(&self) -> &Pcr13 { - &self.pcr13 - } - #[doc = "0xb8 - Pin Control 14"] - #[inline(always)] - pub const fn pcr14(&self) -> &Pcr14 { - &self.pcr14 - } - #[doc = "0xbc - Pin Control 15"] - #[inline(always)] - pub const fn pcr15(&self) -> &Pcr15 { - &self.pcr15 - } - #[doc = "0xc0 - Pin Control 16"] - #[inline(always)] - pub const fn pcr16(&self) -> &Pcr16 { - &self.pcr16 - } - #[doc = "0xc4 - Pin Control 17"] - #[inline(always)] - pub const fn pcr17(&self) -> &Pcr17 { - &self.pcr17 - } - #[doc = "0xc8 - Pin Control 18"] - #[inline(always)] - pub const fn pcr18(&self) -> &Pcr18 { - &self.pcr18 - } - #[doc = "0xcc - Pin Control 19"] - #[inline(always)] - pub const fn pcr19(&self) -> &Pcr19 { - &self.pcr19 - } - #[doc = "0xd0 - Pin Control 20"] - #[inline(always)] - pub const fn pcr20(&self) -> &Pcr20 { - &self.pcr20 - } - #[doc = "0xd4 - Pin Control 21"] - #[inline(always)] - pub const fn pcr21(&self) -> &Pcr21 { - &self.pcr21 - } - #[doc = "0xd8 - Pin Control 22"] - #[inline(always)] - pub const fn pcr22(&self) -> &Pcr22 { - &self.pcr22 - } - #[doc = "0xdc - Pin Control 23"] - #[inline(always)] - pub const fn pcr23(&self) -> &Pcr23 { - &self.pcr23 - } - #[doc = "0xe0 - Pin Control 24"] - #[inline(always)] - pub const fn pcr24(&self) -> &Pcr24 { - &self.pcr24 - } - #[doc = "0xe4 - Pin Control 25"] - #[inline(always)] - pub const fn pcr25(&self) -> &Pcr25 { - &self.pcr25 - } - #[doc = "0xe8 - Pin Control 26"] - #[inline(always)] - pub const fn pcr26(&self) -> &Pcr26 { - &self.pcr26 - } - #[doc = "0xec - Pin Control 27"] - #[inline(always)] - pub const fn pcr27(&self) -> &Pcr27 { - &self.pcr27 - } - #[doc = "0xf0 - Pin Control 28"] - #[inline(always)] - pub const fn pcr28(&self) -> &Pcr28 { - &self.pcr28 - } - #[doc = "0xf4 - Pin Control 29"] - #[inline(always)] - pub const fn pcr29(&self) -> &Pcr29 { - &self.pcr29 - } - #[doc = "0xf8 - Pin Control 30"] - #[inline(always)] - pub const fn pcr30(&self) -> &Pcr30 { - &self.pcr30 - } - #[doc = "0xfc - Pin Control 31"] - #[inline(always)] - pub const fn pcr31(&self) -> &Pcr31 { - &self.pcr31 - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "GPCLR (rw) register accessor: Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr`] module"] -#[doc(alias = "GPCLR")] -pub type Gpclr = crate::Reg; -#[doc = "Global Pin Control Low"] -pub mod gpclr; -#[doc = "GPCHR (rw) register accessor: Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpchr`] module"] -#[doc(alias = "GPCHR")] -pub type Gpchr = crate::Reg; -#[doc = "Global Pin Control High"] -pub mod gpchr; -#[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] -#[doc(alias = "CONFIG")] -pub type Config = crate::Reg; -#[doc = "Configuration"] -pub mod config; -#[doc = "CALIB0 (rw) register accessor: Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib0`] module"] -#[doc(alias = "CALIB0")] -pub type Calib0 = crate::Reg; -#[doc = "Calibration 0"] -pub mod calib0; -#[doc = "CALIB1 (rw) register accessor: Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calib1`] module"] -#[doc(alias = "CALIB1")] -pub type Calib1 = crate::Reg; -#[doc = "Calibration 1"] -pub mod calib1; -#[doc = "PCR0 (rw) register accessor: Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr0`] module"] -#[doc(alias = "PCR0")] -pub type Pcr0 = crate::Reg; -#[doc = "Pin Control 0"] -pub mod pcr0; -#[doc = "PCR1 (rw) register accessor: Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr1`] module"] -#[doc(alias = "PCR1")] -pub type Pcr1 = crate::Reg; -#[doc = "Pin Control 1"] -pub mod pcr1; -#[doc = "PCR2 (rw) register accessor: Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr2`] module"] -#[doc(alias = "PCR2")] -pub type Pcr2 = crate::Reg; -#[doc = "Pin Control 2"] -pub mod pcr2; -#[doc = "PCR3 (rw) register accessor: Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr3`] module"] -#[doc(alias = "PCR3")] -pub type Pcr3 = crate::Reg; -#[doc = "Pin Control 3"] -pub mod pcr3; -#[doc = "PCR4 (rw) register accessor: Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr4`] module"] -#[doc(alias = "PCR4")] -pub type Pcr4 = crate::Reg; -#[doc = "Pin Control 4"] -pub mod pcr4; -#[doc = "PCR5 (rw) register accessor: Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr5`] module"] -#[doc(alias = "PCR5")] -pub type Pcr5 = crate::Reg; -#[doc = "Pin Control 5"] -pub mod pcr5; -#[doc = "PCR6 (rw) register accessor: Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr6`] module"] -#[doc(alias = "PCR6")] -pub type Pcr6 = crate::Reg; -#[doc = "Pin Control 6"] -pub mod pcr6; -#[doc = "PCR7 (rw) register accessor: Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr7`] module"] -#[doc(alias = "PCR7")] -pub type Pcr7 = crate::Reg; -#[doc = "Pin Control 7"] -pub mod pcr7; -#[doc = "PCR8 (rw) register accessor: Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr8`] module"] -#[doc(alias = "PCR8")] -pub type Pcr8 = crate::Reg; -#[doc = "Pin Control 8"] -pub mod pcr8; -#[doc = "PCR9 (rw) register accessor: Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr9`] module"] -#[doc(alias = "PCR9")] -pub type Pcr9 = crate::Reg; -#[doc = "Pin Control 9"] -pub mod pcr9; -#[doc = "PCR10 (rw) register accessor: Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr10`] module"] -#[doc(alias = "PCR10")] -pub type Pcr10 = crate::Reg; -#[doc = "Pin Control 10"] -pub mod pcr10; -#[doc = "PCR11 (rw) register accessor: Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr11`] module"] -#[doc(alias = "PCR11")] -pub type Pcr11 = crate::Reg; -#[doc = "Pin Control 11"] -pub mod pcr11; -#[doc = "PCR12 (rw) register accessor: Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr12`] module"] -#[doc(alias = "PCR12")] -pub type Pcr12 = crate::Reg; -#[doc = "Pin Control 12"] -pub mod pcr12; -#[doc = "PCR13 (rw) register accessor: Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr13`] module"] -#[doc(alias = "PCR13")] -pub type Pcr13 = crate::Reg; -#[doc = "Pin Control 13"] -pub mod pcr13; -#[doc = "PCR14 (rw) register accessor: Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr14`] module"] -#[doc(alias = "PCR14")] -pub type Pcr14 = crate::Reg; -#[doc = "Pin Control 14"] -pub mod pcr14; -#[doc = "PCR15 (rw) register accessor: Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr15`] module"] -#[doc(alias = "PCR15")] -pub type Pcr15 = crate::Reg; -#[doc = "Pin Control 15"] -pub mod pcr15; -#[doc = "PCR16 (rw) register accessor: Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr16`] module"] -#[doc(alias = "PCR16")] -pub type Pcr16 = crate::Reg; -#[doc = "Pin Control 16"] -pub mod pcr16; -#[doc = "PCR17 (rw) register accessor: Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr17`] module"] -#[doc(alias = "PCR17")] -pub type Pcr17 = crate::Reg; -#[doc = "Pin Control 17"] -pub mod pcr17; -#[doc = "PCR18 (rw) register accessor: Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr18`] module"] -#[doc(alias = "PCR18")] -pub type Pcr18 = crate::Reg; -#[doc = "Pin Control 18"] -pub mod pcr18; -#[doc = "PCR19 (rw) register accessor: Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr19`] module"] -#[doc(alias = "PCR19")] -pub type Pcr19 = crate::Reg; -#[doc = "Pin Control 19"] -pub mod pcr19; -#[doc = "PCR20 (rw) register accessor: Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr20`] module"] -#[doc(alias = "PCR20")] -pub type Pcr20 = crate::Reg; -#[doc = "Pin Control 20"] -pub mod pcr20; -#[doc = "PCR21 (rw) register accessor: Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr21`] module"] -#[doc(alias = "PCR21")] -pub type Pcr21 = crate::Reg; -#[doc = "Pin Control 21"] -pub mod pcr21; -#[doc = "PCR22 (rw) register accessor: Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr22`] module"] -#[doc(alias = "PCR22")] -pub type Pcr22 = crate::Reg; -#[doc = "Pin Control 22"] -pub mod pcr22; -#[doc = "PCR23 (rw) register accessor: Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr23`] module"] -#[doc(alias = "PCR23")] -pub type Pcr23 = crate::Reg; -#[doc = "Pin Control 23"] -pub mod pcr23; -#[doc = "PCR24 (rw) register accessor: Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr24`] module"] -#[doc(alias = "PCR24")] -pub type Pcr24 = crate::Reg; -#[doc = "Pin Control 24"] -pub mod pcr24; -#[doc = "PCR25 (rw) register accessor: Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr25`] module"] -#[doc(alias = "PCR25")] -pub type Pcr25 = crate::Reg; -#[doc = "Pin Control 25"] -pub mod pcr25; -#[doc = "PCR26 (rw) register accessor: Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr26`] module"] -#[doc(alias = "PCR26")] -pub type Pcr26 = crate::Reg; -#[doc = "Pin Control 26"] -pub mod pcr26; -#[doc = "PCR27 (rw) register accessor: Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr27`] module"] -#[doc(alias = "PCR27")] -pub type Pcr27 = crate::Reg; -#[doc = "Pin Control 27"] -pub mod pcr27; -#[doc = "PCR28 (rw) register accessor: Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr28`] module"] -#[doc(alias = "PCR28")] -pub type Pcr28 = crate::Reg; -#[doc = "Pin Control 28"] -pub mod pcr28; -#[doc = "PCR29 (rw) register accessor: Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr29`] module"] -#[doc(alias = "PCR29")] -pub type Pcr29 = crate::Reg; -#[doc = "Pin Control 29"] -pub mod pcr29; -#[doc = "PCR30 (rw) register accessor: Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr30`] module"] -#[doc(alias = "PCR30")] -pub type Pcr30 = crate::Reg; -#[doc = "Pin Control 30"] -pub mod pcr30; -#[doc = "PCR31 (rw) register accessor: Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcr31`] module"] -#[doc(alias = "PCR31")] -pub type Pcr31 = crate::Reg; -#[doc = "Pin Control 31"] -pub mod pcr31; diff --git a/mcxa276-pac/src/port4/calib0.rs b/mcxa276-pac/src/port4/calib0.rs deleted file mode 100644 index 029fa12f3..000000000 --- a/mcxa276-pac/src/port4/calib0.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB0` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB0` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 0\n\nYou can [`read`](crate::Reg::read) this register and get [`calib0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib0Spec; -impl crate::RegisterSpec for Calib0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib0::R`](R) reader structure"] -impl crate::Readable for Calib0Spec {} -#[doc = "`write(|w| ..)` method takes [`calib0::W`](W) writer structure"] -impl crate::Writable for Calib0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB0 to value 0"] -impl crate::Resettable for Calib0Spec {} diff --git a/mcxa276-pac/src/port4/calib1.rs b/mcxa276-pac/src/port4/calib1.rs deleted file mode 100644 index e18f61234..000000000 --- a/mcxa276-pac/src/port4/calib1.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `CALIB1` reader"] -pub type R = crate::R; -#[doc = "Register `CALIB1` writer"] -pub type W = crate::W; -#[doc = "Field `NCAL` reader - Calibration of NMOS Output Driver"] -pub type NcalR = crate::FieldReader; -#[doc = "Field `NCAL` writer - Calibration of NMOS Output Driver"] -pub type NcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `PCAL` reader - Calibration of PMOS Output Driver"] -pub type PcalR = crate::FieldReader; -#[doc = "Field `PCAL` writer - Calibration of PMOS Output Driver"] -pub type PcalW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&self) -> NcalR { - NcalR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&self) -> PcalR { - PcalR::new(((self.bits >> 16) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Calibration of NMOS Output Driver"] - #[inline(always)] - pub fn ncal(&mut self) -> NcalW { - NcalW::new(self, 0) - } - #[doc = "Bits 16:21 - Calibration of PMOS Output Driver"] - #[inline(always)] - pub fn pcal(&mut self) -> PcalW { - PcalW::new(self, 16) - } -} -#[doc = "Calibration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`calib1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calib1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Calib1Spec; -impl crate::RegisterSpec for Calib1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`calib1::R`](R) reader structure"] -impl crate::Readable for Calib1Spec {} -#[doc = "`write(|w| ..)` method takes [`calib1::W`](W) writer structure"] -impl crate::Writable for Calib1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CALIB1 to value 0"] -impl crate::Resettable for Calib1Spec {} diff --git a/mcxa276-pac/src/port4/config.rs b/mcxa276-pac/src/port4/config.rs deleted file mode 100644 index da92c5b27..000000000 --- a/mcxa276-pac/src/port4/config.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `CONFIG` reader"] -pub type R = crate::R; -#[doc = "Register `CONFIG` writer"] -pub type W = crate::W; -#[doc = "Port Voltage Range\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Range { - #[doc = "0: 1.71 V-3.6 V"] - Range0 = 0, - #[doc = "1: 2.70 V-3.6 V"] - Range1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Range) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RANGE` reader - Port Voltage Range"] -pub type RangeR = crate::BitReader; -impl RangeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Range { - match self.bits { - false => Range::Range0, - true => Range::Range1, - } - } - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn is_range0(&self) -> bool { - *self == Range::Range0 - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn is_range1(&self) -> bool { - *self == Range::Range1 - } -} -#[doc = "Field `RANGE` writer - Port Voltage Range"] -pub type RangeW<'a, REG> = crate::BitWriter<'a, REG, Range>; -impl<'a, REG> RangeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "1.71 V-3.6 V"] - #[inline(always)] - pub fn range0(self) -> &'a mut crate::W { - self.variant(Range::Range0) - } - #[doc = "2.70 V-3.6 V"] - #[inline(always)] - pub fn range1(self) -> &'a mut crate::W { - self.variant(Range::Range1) - } -} -impl R { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&self) -> RangeR { - RangeR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Port Voltage Range"] - #[inline(always)] - pub fn range(&mut self) -> RangeW { - RangeW::new(self, 0) - } -} -#[doc = "Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ConfigSpec; -impl crate::RegisterSpec for ConfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`config::R`](R) reader structure"] -impl crate::Readable for ConfigSpec {} -#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] -impl crate::Writable for ConfigSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CONFIG to value 0"] -impl crate::Resettable for ConfigSpec {} diff --git a/mcxa276-pac/src/port4/gpchr.rs b/mcxa276-pac/src/port4/gpchr.rs deleted file mode 100644 index af92d0d62..000000000 --- a/mcxa276-pac/src/port4/gpchr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCHR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCHR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe16 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE16` reader - Global Pin Write Enable"] -pub type Gpwe16R = crate::BitReader; -impl Gpwe16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe16 { - match self.bits { - false => Gpwe16::Gpwe0, - true => Gpwe16::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe16::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe16::Gpwe1 - } -} -#[doc = "Field `GPWE16` writer - Global Pin Write Enable"] -pub type Gpwe16W<'a, REG> = crate::BitWriter<'a, REG, Gpwe16>; -impl<'a, REG> Gpwe16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe16::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe17 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE17` reader - Global Pin Write Enable"] -pub type Gpwe17R = crate::BitReader; -impl Gpwe17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe17 { - match self.bits { - false => Gpwe17::Gpwe0, - true => Gpwe17::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe17::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe17::Gpwe1 - } -} -#[doc = "Field `GPWE17` writer - Global Pin Write Enable"] -pub type Gpwe17W<'a, REG> = crate::BitWriter<'a, REG, Gpwe17>; -impl<'a, REG> Gpwe17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe17::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe18 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE18` reader - Global Pin Write Enable"] -pub type Gpwe18R = crate::BitReader; -impl Gpwe18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe18 { - match self.bits { - false => Gpwe18::Gpwe0, - true => Gpwe18::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe18::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe18::Gpwe1 - } -} -#[doc = "Field `GPWE18` writer - Global Pin Write Enable"] -pub type Gpwe18W<'a, REG> = crate::BitWriter<'a, REG, Gpwe18>; -impl<'a, REG> Gpwe18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe18::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe19 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE19` reader - Global Pin Write Enable"] -pub type Gpwe19R = crate::BitReader; -impl Gpwe19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe19 { - match self.bits { - false => Gpwe19::Gpwe0, - true => Gpwe19::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe19::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe19::Gpwe1 - } -} -#[doc = "Field `GPWE19` writer - Global Pin Write Enable"] -pub type Gpwe19W<'a, REG> = crate::BitWriter<'a, REG, Gpwe19>; -impl<'a, REG> Gpwe19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe19::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe20 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE20` reader - Global Pin Write Enable"] -pub type Gpwe20R = crate::BitReader; -impl Gpwe20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe20 { - match self.bits { - false => Gpwe20::Gpwe0, - true => Gpwe20::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe20::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe20::Gpwe1 - } -} -#[doc = "Field `GPWE20` writer - Global Pin Write Enable"] -pub type Gpwe20W<'a, REG> = crate::BitWriter<'a, REG, Gpwe20>; -impl<'a, REG> Gpwe20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe20::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe21 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE21` reader - Global Pin Write Enable"] -pub type Gpwe21R = crate::BitReader; -impl Gpwe21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe21 { - match self.bits { - false => Gpwe21::Gpwe0, - true => Gpwe21::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe21::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe21::Gpwe1 - } -} -#[doc = "Field `GPWE21` writer - Global Pin Write Enable"] -pub type Gpwe21W<'a, REG> = crate::BitWriter<'a, REG, Gpwe21>; -impl<'a, REG> Gpwe21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe21::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe22 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE22` reader - Global Pin Write Enable"] -pub type Gpwe22R = crate::BitReader; -impl Gpwe22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe22 { - match self.bits { - false => Gpwe22::Gpwe0, - true => Gpwe22::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe22::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe22::Gpwe1 - } -} -#[doc = "Field `GPWE22` writer - Global Pin Write Enable"] -pub type Gpwe22W<'a, REG> = crate::BitWriter<'a, REG, Gpwe22>; -impl<'a, REG> Gpwe22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe22::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe23 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE23` reader - Global Pin Write Enable"] -pub type Gpwe23R = crate::BitReader; -impl Gpwe23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe23 { - match self.bits { - false => Gpwe23::Gpwe0, - true => Gpwe23::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe23::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe23::Gpwe1 - } -} -#[doc = "Field `GPWE23` writer - Global Pin Write Enable"] -pub type Gpwe23W<'a, REG> = crate::BitWriter<'a, REG, Gpwe23>; -impl<'a, REG> Gpwe23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe23::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe24 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE24` reader - Global Pin Write Enable"] -pub type Gpwe24R = crate::BitReader; -impl Gpwe24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe24 { - match self.bits { - false => Gpwe24::Gpwe0, - true => Gpwe24::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe24::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe24::Gpwe1 - } -} -#[doc = "Field `GPWE24` writer - Global Pin Write Enable"] -pub type Gpwe24W<'a, REG> = crate::BitWriter<'a, REG, Gpwe24>; -impl<'a, REG> Gpwe24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe24::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe25 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE25` reader - Global Pin Write Enable"] -pub type Gpwe25R = crate::BitReader; -impl Gpwe25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe25 { - match self.bits { - false => Gpwe25::Gpwe0, - true => Gpwe25::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe25::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe25::Gpwe1 - } -} -#[doc = "Field `GPWE25` writer - Global Pin Write Enable"] -pub type Gpwe25W<'a, REG> = crate::BitWriter<'a, REG, Gpwe25>; -impl<'a, REG> Gpwe25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe25::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe26 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE26` reader - Global Pin Write Enable"] -pub type Gpwe26R = crate::BitReader; -impl Gpwe26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe26 { - match self.bits { - false => Gpwe26::Gpwe0, - true => Gpwe26::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe26::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe26::Gpwe1 - } -} -#[doc = "Field `GPWE26` writer - Global Pin Write Enable"] -pub type Gpwe26W<'a, REG> = crate::BitWriter<'a, REG, Gpwe26>; -impl<'a, REG> Gpwe26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe26::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe27 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE27` reader - Global Pin Write Enable"] -pub type Gpwe27R = crate::BitReader; -impl Gpwe27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe27 { - match self.bits { - false => Gpwe27::Gpwe0, - true => Gpwe27::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe27::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe27::Gpwe1 - } -} -#[doc = "Field `GPWE27` writer - Global Pin Write Enable"] -pub type Gpwe27W<'a, REG> = crate::BitWriter<'a, REG, Gpwe27>; -impl<'a, REG> Gpwe27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe27::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe28 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE28` reader - Global Pin Write Enable"] -pub type Gpwe28R = crate::BitReader; -impl Gpwe28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe28 { - match self.bits { - false => Gpwe28::Gpwe0, - true => Gpwe28::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe28::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe28::Gpwe1 - } -} -#[doc = "Field `GPWE28` writer - Global Pin Write Enable"] -pub type Gpwe28W<'a, REG> = crate::BitWriter<'a, REG, Gpwe28>; -impl<'a, REG> Gpwe28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe28::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe29 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE29` reader - Global Pin Write Enable"] -pub type Gpwe29R = crate::BitReader; -impl Gpwe29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe29 { - match self.bits { - false => Gpwe29::Gpwe0, - true => Gpwe29::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe29::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe29::Gpwe1 - } -} -#[doc = "Field `GPWE29` writer - Global Pin Write Enable"] -pub type Gpwe29W<'a, REG> = crate::BitWriter<'a, REG, Gpwe29>; -impl<'a, REG> Gpwe29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe29::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe30 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE30` reader - Global Pin Write Enable"] -pub type Gpwe30R = crate::BitReader; -impl Gpwe30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe30 { - match self.bits { - false => Gpwe30::Gpwe0, - true => Gpwe30::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe30::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe30::Gpwe1 - } -} -#[doc = "Field `GPWE30` writer - Global Pin Write Enable"] -pub type Gpwe30W<'a, REG> = crate::BitWriter<'a, REG, Gpwe30>; -impl<'a, REG> Gpwe30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe30::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe31 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE31` reader - Global Pin Write Enable"] -pub type Gpwe31R = crate::BitReader; -impl Gpwe31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe31 { - match self.bits { - false => Gpwe31::Gpwe0, - true => Gpwe31::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe31::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe31::Gpwe1 - } -} -#[doc = "Field `GPWE31` writer - Global Pin Write Enable"] -pub type Gpwe31W<'a, REG> = crate::BitWriter<'a, REG, Gpwe31>; -impl<'a, REG> Gpwe31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe31::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&self) -> Gpwe16R { - Gpwe16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&self) -> Gpwe17R { - Gpwe17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&self) -> Gpwe18R { - Gpwe18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&self) -> Gpwe19R { - Gpwe19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&self) -> Gpwe20R { - Gpwe20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&self) -> Gpwe21R { - Gpwe21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&self) -> Gpwe22R { - Gpwe22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&self) -> Gpwe23R { - Gpwe23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&self) -> Gpwe24R { - Gpwe24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&self) -> Gpwe25R { - Gpwe25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&self) -> Gpwe26R { - Gpwe26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&self) -> Gpwe27R { - Gpwe27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&self) -> Gpwe28R { - Gpwe28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&self) -> Gpwe29R { - Gpwe29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&self) -> Gpwe30R { - Gpwe30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&self) -> Gpwe31R { - Gpwe31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe16(&mut self) -> Gpwe16W { - Gpwe16W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe17(&mut self) -> Gpwe17W { - Gpwe17W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe18(&mut self) -> Gpwe18W { - Gpwe18W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe19(&mut self) -> Gpwe19W { - Gpwe19W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe20(&mut self) -> Gpwe20W { - Gpwe20W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe21(&mut self) -> Gpwe21W { - Gpwe21W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe22(&mut self) -> Gpwe22W { - Gpwe22W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe23(&mut self) -> Gpwe23W { - Gpwe23W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe24(&mut self) -> Gpwe24W { - Gpwe24W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe25(&mut self) -> Gpwe25W { - Gpwe25W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe26(&mut self) -> Gpwe26W { - Gpwe26W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe27(&mut self) -> Gpwe27W { - Gpwe27W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe28(&mut self) -> Gpwe28W { - Gpwe28W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe29(&mut self) -> Gpwe29W { - Gpwe29W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe30(&mut self) -> Gpwe30W { - Gpwe30W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe31(&mut self) -> Gpwe31W { - Gpwe31W::new(self, 31) - } -} -#[doc = "Global Pin Control High\n\nYou can [`read`](crate::Reg::read) this register and get [`gpchr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpchr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpchrSpec; -impl crate::RegisterSpec for GpchrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpchr::R`](R) reader structure"] -impl crate::Readable for GpchrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpchr::W`](W) writer structure"] -impl crate::Writable for GpchrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCHR to value 0"] -impl crate::Resettable for GpchrSpec {} diff --git a/mcxa276-pac/src/port4/gpclr.rs b/mcxa276-pac/src/port4/gpclr.rs deleted file mode 100644 index 21e5ff23d..000000000 --- a/mcxa276-pac/src/port4/gpclr.rs +++ /dev/null @@ -1,1043 +0,0 @@ -#[doc = "Register `GPCLR` reader"] -pub type R = crate::R; -#[doc = "Register `GPCLR` writer"] -pub type W = crate::W; -#[doc = "Field `GPWD` reader - Global Pin Write Data"] -pub type GpwdR = crate::FieldReader; -#[doc = "Field `GPWD` writer - Global Pin Write Data"] -pub type GpwdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe0 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE0` reader - Global Pin Write Enable"] -pub type Gpwe0R = crate::BitReader; -impl Gpwe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe0 { - match self.bits { - false => Gpwe0::Gpwe0, - true => Gpwe0::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe0::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe0::Gpwe1 - } -} -#[doc = "Field `GPWE0` writer - Global Pin Write Enable"] -pub type Gpwe0W<'a, REG> = crate::BitWriter<'a, REG, Gpwe0>; -impl<'a, REG> Gpwe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe0::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe1 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE1` reader - Global Pin Write Enable"] -pub type Gpwe1R = crate::BitReader; -impl Gpwe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe1 { - match self.bits { - false => Gpwe1::Gpwe0, - true => Gpwe1::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe1::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe1::Gpwe1 - } -} -#[doc = "Field `GPWE1` writer - Global Pin Write Enable"] -pub type Gpwe1W<'a, REG> = crate::BitWriter<'a, REG, Gpwe1>; -impl<'a, REG> Gpwe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe1::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe2 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE2` reader - Global Pin Write Enable"] -pub type Gpwe2R = crate::BitReader; -impl Gpwe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe2 { - match self.bits { - false => Gpwe2::Gpwe0, - true => Gpwe2::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe2::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe2::Gpwe1 - } -} -#[doc = "Field `GPWE2` writer - Global Pin Write Enable"] -pub type Gpwe2W<'a, REG> = crate::BitWriter<'a, REG, Gpwe2>; -impl<'a, REG> Gpwe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe2::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe3 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE3` reader - Global Pin Write Enable"] -pub type Gpwe3R = crate::BitReader; -impl Gpwe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe3 { - match self.bits { - false => Gpwe3::Gpwe0, - true => Gpwe3::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe3::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe3::Gpwe1 - } -} -#[doc = "Field `GPWE3` writer - Global Pin Write Enable"] -pub type Gpwe3W<'a, REG> = crate::BitWriter<'a, REG, Gpwe3>; -impl<'a, REG> Gpwe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe3::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe4 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE4` reader - Global Pin Write Enable"] -pub type Gpwe4R = crate::BitReader; -impl Gpwe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe4 { - match self.bits { - false => Gpwe4::Gpwe0, - true => Gpwe4::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe4::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe4::Gpwe1 - } -} -#[doc = "Field `GPWE4` writer - Global Pin Write Enable"] -pub type Gpwe4W<'a, REG> = crate::BitWriter<'a, REG, Gpwe4>; -impl<'a, REG> Gpwe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe4::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe5 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE5` reader - Global Pin Write Enable"] -pub type Gpwe5R = crate::BitReader; -impl Gpwe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe5 { - match self.bits { - false => Gpwe5::Gpwe0, - true => Gpwe5::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe5::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe5::Gpwe1 - } -} -#[doc = "Field `GPWE5` writer - Global Pin Write Enable"] -pub type Gpwe5W<'a, REG> = crate::BitWriter<'a, REG, Gpwe5>; -impl<'a, REG> Gpwe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe5::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe6 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE6` reader - Global Pin Write Enable"] -pub type Gpwe6R = crate::BitReader; -impl Gpwe6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe6 { - match self.bits { - false => Gpwe6::Gpwe0, - true => Gpwe6::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe6::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe6::Gpwe1 - } -} -#[doc = "Field `GPWE6` writer - Global Pin Write Enable"] -pub type Gpwe6W<'a, REG> = crate::BitWriter<'a, REG, Gpwe6>; -impl<'a, REG> Gpwe6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe6::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe7 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE7` reader - Global Pin Write Enable"] -pub type Gpwe7R = crate::BitReader; -impl Gpwe7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe7 { - match self.bits { - false => Gpwe7::Gpwe0, - true => Gpwe7::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe7::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe7::Gpwe1 - } -} -#[doc = "Field `GPWE7` writer - Global Pin Write Enable"] -pub type Gpwe7W<'a, REG> = crate::BitWriter<'a, REG, Gpwe7>; -impl<'a, REG> Gpwe7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe7::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe8 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE8` reader - Global Pin Write Enable"] -pub type Gpwe8R = crate::BitReader; -impl Gpwe8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe8 { - match self.bits { - false => Gpwe8::Gpwe0, - true => Gpwe8::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe8::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe8::Gpwe1 - } -} -#[doc = "Field `GPWE8` writer - Global Pin Write Enable"] -pub type Gpwe8W<'a, REG> = crate::BitWriter<'a, REG, Gpwe8>; -impl<'a, REG> Gpwe8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe8::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe9 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE9` reader - Global Pin Write Enable"] -pub type Gpwe9R = crate::BitReader; -impl Gpwe9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe9 { - match self.bits { - false => Gpwe9::Gpwe0, - true => Gpwe9::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe9::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe9::Gpwe1 - } -} -#[doc = "Field `GPWE9` writer - Global Pin Write Enable"] -pub type Gpwe9W<'a, REG> = crate::BitWriter<'a, REG, Gpwe9>; -impl<'a, REG> Gpwe9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe9::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe10 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE10` reader - Global Pin Write Enable"] -pub type Gpwe10R = crate::BitReader; -impl Gpwe10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe10 { - match self.bits { - false => Gpwe10::Gpwe0, - true => Gpwe10::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe10::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe10::Gpwe1 - } -} -#[doc = "Field `GPWE10` writer - Global Pin Write Enable"] -pub type Gpwe10W<'a, REG> = crate::BitWriter<'a, REG, Gpwe10>; -impl<'a, REG> Gpwe10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe10::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe11 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE11` reader - Global Pin Write Enable"] -pub type Gpwe11R = crate::BitReader; -impl Gpwe11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe11 { - match self.bits { - false => Gpwe11::Gpwe0, - true => Gpwe11::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe11::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe11::Gpwe1 - } -} -#[doc = "Field `GPWE11` writer - Global Pin Write Enable"] -pub type Gpwe11W<'a, REG> = crate::BitWriter<'a, REG, Gpwe11>; -impl<'a, REG> Gpwe11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe11::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe12 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE12` reader - Global Pin Write Enable"] -pub type Gpwe12R = crate::BitReader; -impl Gpwe12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe12 { - match self.bits { - false => Gpwe12::Gpwe0, - true => Gpwe12::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe12::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe12::Gpwe1 - } -} -#[doc = "Field `GPWE12` writer - Global Pin Write Enable"] -pub type Gpwe12W<'a, REG> = crate::BitWriter<'a, REG, Gpwe12>; -impl<'a, REG> Gpwe12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe12::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe13 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE13` reader - Global Pin Write Enable"] -pub type Gpwe13R = crate::BitReader; -impl Gpwe13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe13 { - match self.bits { - false => Gpwe13::Gpwe0, - true => Gpwe13::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe13::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe13::Gpwe1 - } -} -#[doc = "Field `GPWE13` writer - Global Pin Write Enable"] -pub type Gpwe13W<'a, REG> = crate::BitWriter<'a, REG, Gpwe13>; -impl<'a, REG> Gpwe13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe13::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe14 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE14` reader - Global Pin Write Enable"] -pub type Gpwe14R = crate::BitReader; -impl Gpwe14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe14 { - match self.bits { - false => Gpwe14::Gpwe0, - true => Gpwe14::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe14::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe14::Gpwe1 - } -} -#[doc = "Field `GPWE14` writer - Global Pin Write Enable"] -pub type Gpwe14W<'a, REG> = crate::BitWriter<'a, REG, Gpwe14>; -impl<'a, REG> Gpwe14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe14::Gpwe1) - } -} -#[doc = "Global Pin Write Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gpwe15 { - #[doc = "0: Not updated"] - Gpwe0 = 0, - #[doc = "1: Updated"] - Gpwe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gpwe15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GPWE15` reader - Global Pin Write Enable"] -pub type Gpwe15R = crate::BitReader; -impl Gpwe15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gpwe15 { - match self.bits { - false => Gpwe15::Gpwe0, - true => Gpwe15::Gpwe1, - } - } - #[doc = "Not updated"] - #[inline(always)] - pub fn is_gpwe0(&self) -> bool { - *self == Gpwe15::Gpwe0 - } - #[doc = "Updated"] - #[inline(always)] - pub fn is_gpwe1(&self) -> bool { - *self == Gpwe15::Gpwe1 - } -} -#[doc = "Field `GPWE15` writer - Global Pin Write Enable"] -pub type Gpwe15W<'a, REG> = crate::BitWriter<'a, REG, Gpwe15>; -impl<'a, REG> Gpwe15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not updated"] - #[inline(always)] - pub fn gpwe0(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe0) - } - #[doc = "Updated"] - #[inline(always)] - pub fn gpwe1(self) -> &'a mut crate::W { - self.variant(Gpwe15::Gpwe1) - } -} -impl R { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&self) -> GpwdR { - GpwdR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&self) -> Gpwe0R { - Gpwe0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&self) -> Gpwe1R { - Gpwe1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&self) -> Gpwe2R { - Gpwe2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&self) -> Gpwe3R { - Gpwe3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&self) -> Gpwe4R { - Gpwe4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&self) -> Gpwe5R { - Gpwe5R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&self) -> Gpwe6R { - Gpwe6R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&self) -> Gpwe7R { - Gpwe7R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&self) -> Gpwe8R { - Gpwe8R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&self) -> Gpwe9R { - Gpwe9R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&self) -> Gpwe10R { - Gpwe10R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&self) -> Gpwe11R { - Gpwe11R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&self) -> Gpwe12R { - Gpwe12R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&self) -> Gpwe13R { - Gpwe13R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&self) -> Gpwe14R { - Gpwe14R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&self) -> Gpwe15R { - Gpwe15R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Global Pin Write Data"] - #[inline(always)] - pub fn gpwd(&mut self) -> GpwdW { - GpwdW::new(self, 0) - } - #[doc = "Bit 16 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe0(&mut self) -> Gpwe0W { - Gpwe0W::new(self, 16) - } - #[doc = "Bit 17 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe1(&mut self) -> Gpwe1W { - Gpwe1W::new(self, 17) - } - #[doc = "Bit 18 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe2(&mut self) -> Gpwe2W { - Gpwe2W::new(self, 18) - } - #[doc = "Bit 19 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe3(&mut self) -> Gpwe3W { - Gpwe3W::new(self, 19) - } - #[doc = "Bit 20 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe4(&mut self) -> Gpwe4W { - Gpwe4W::new(self, 20) - } - #[doc = "Bit 21 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe5(&mut self) -> Gpwe5W { - Gpwe5W::new(self, 21) - } - #[doc = "Bit 22 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe6(&mut self) -> Gpwe6W { - Gpwe6W::new(self, 22) - } - #[doc = "Bit 23 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe7(&mut self) -> Gpwe7W { - Gpwe7W::new(self, 23) - } - #[doc = "Bit 24 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe8(&mut self) -> Gpwe8W { - Gpwe8W::new(self, 24) - } - #[doc = "Bit 25 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe9(&mut self) -> Gpwe9W { - Gpwe9W::new(self, 25) - } - #[doc = "Bit 26 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe10(&mut self) -> Gpwe10W { - Gpwe10W::new(self, 26) - } - #[doc = "Bit 27 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe11(&mut self) -> Gpwe11W { - Gpwe11W::new(self, 27) - } - #[doc = "Bit 28 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe12(&mut self) -> Gpwe12W { - Gpwe12W::new(self, 28) - } - #[doc = "Bit 29 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe13(&mut self) -> Gpwe13W { - Gpwe13W::new(self, 29) - } - #[doc = "Bit 30 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe14(&mut self) -> Gpwe14W { - Gpwe14W::new(self, 30) - } - #[doc = "Bit 31 - Global Pin Write Enable"] - #[inline(always)] - pub fn gpwe15(&mut self) -> Gpwe15W { - Gpwe15W::new(self, 31) - } -} -#[doc = "Global Pin Control Low\n\nYou can [`read`](crate::Reg::read) this register and get [`gpclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GpclrSpec; -impl crate::RegisterSpec for GpclrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpclr::R`](R) reader structure"] -impl crate::Readable for GpclrSpec {} -#[doc = "`write(|w| ..)` method takes [`gpclr::W`](W) writer structure"] -impl crate::Writable for GpclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GPCLR to value 0"] -impl crate::Resettable for GpclrSpec {} diff --git a/mcxa276-pac/src/port4/pcr0.rs b/mcxa276-pac/src/port4/pcr0.rs deleted file mode 100644 index 395c4a341..000000000 --- a/mcxa276-pac/src/port4/pcr0.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR0` reader"] -pub type R = crate::R; -#[doc = "Register `PCR0` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr0Spec; -impl crate::RegisterSpec for Pcr0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr0::R`](R) reader structure"] -impl crate::Readable for Pcr0Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr0::W`](W) writer structure"] -impl crate::Writable for Pcr0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR0 to value 0"] -impl crate::Resettable for Pcr0Spec {} diff --git a/mcxa276-pac/src/port4/pcr1.rs b/mcxa276-pac/src/port4/pcr1.rs deleted file mode 100644 index 41e78955c..000000000 --- a/mcxa276-pac/src/port4/pcr1.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR1` reader"] -pub type R = crate::R; -#[doc = "Register `PCR1` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr1Spec; -impl crate::RegisterSpec for Pcr1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr1::R`](R) reader structure"] -impl crate::Readable for Pcr1Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr1::W`](W) writer structure"] -impl crate::Writable for Pcr1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR1 to value 0"] -impl crate::Resettable for Pcr1Spec {} diff --git a/mcxa276-pac/src/port4/pcr10.rs b/mcxa276-pac/src/port4/pcr10.rs deleted file mode 100644 index 9a358f658..000000000 --- a/mcxa276-pac/src/port4/pcr10.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR10` reader"] -pub type R = crate::R; -#[doc = "Register `PCR10` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr10Spec; -impl crate::RegisterSpec for Pcr10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr10::R`](R) reader structure"] -impl crate::Readable for Pcr10Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr10::W`](W) writer structure"] -impl crate::Writable for Pcr10Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR10 to value 0"] -impl crate::Resettable for Pcr10Spec {} diff --git a/mcxa276-pac/src/port4/pcr11.rs b/mcxa276-pac/src/port4/pcr11.rs deleted file mode 100644 index 7b809b651..000000000 --- a/mcxa276-pac/src/port4/pcr11.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR11` reader"] -pub type R = crate::R; -#[doc = "Register `PCR11` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr11Spec; -impl crate::RegisterSpec for Pcr11Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr11::R`](R) reader structure"] -impl crate::Readable for Pcr11Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr11::W`](W) writer structure"] -impl crate::Writable for Pcr11Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR11 to value 0"] -impl crate::Resettable for Pcr11Spec {} diff --git a/mcxa276-pac/src/port4/pcr12.rs b/mcxa276-pac/src/port4/pcr12.rs deleted file mode 100644 index 2f5662298..000000000 --- a/mcxa276-pac/src/port4/pcr12.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR12` reader"] -pub type R = crate::R; -#[doc = "Register `PCR12` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr12Spec; -impl crate::RegisterSpec for Pcr12Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr12::R`](R) reader structure"] -impl crate::Readable for Pcr12Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr12::W`](W) writer structure"] -impl crate::Writable for Pcr12Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR12 to value 0"] -impl crate::Resettable for Pcr12Spec {} diff --git a/mcxa276-pac/src/port4/pcr13.rs b/mcxa276-pac/src/port4/pcr13.rs deleted file mode 100644 index 232ff4705..000000000 --- a/mcxa276-pac/src/port4/pcr13.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR13` reader"] -pub type R = crate::R; -#[doc = "Register `PCR13` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr13Spec; -impl crate::RegisterSpec for Pcr13Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr13::R`](R) reader structure"] -impl crate::Readable for Pcr13Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr13::W`](W) writer structure"] -impl crate::Writable for Pcr13Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR13 to value 0"] -impl crate::Resettable for Pcr13Spec {} diff --git a/mcxa276-pac/src/port4/pcr14.rs b/mcxa276-pac/src/port4/pcr14.rs deleted file mode 100644 index b600e6419..000000000 --- a/mcxa276-pac/src/port4/pcr14.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR14` reader"] -pub type R = crate::R; -#[doc = "Register `PCR14` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr14Spec; -impl crate::RegisterSpec for Pcr14Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr14::R`](R) reader structure"] -impl crate::Readable for Pcr14Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr14::W`](W) writer structure"] -impl crate::Writable for Pcr14Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR14 to value 0"] -impl crate::Resettable for Pcr14Spec {} diff --git a/mcxa276-pac/src/port4/pcr15.rs b/mcxa276-pac/src/port4/pcr15.rs deleted file mode 100644 index a7daba418..000000000 --- a/mcxa276-pac/src/port4/pcr15.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR15` reader"] -pub type R = crate::R; -#[doc = "Register `PCR15` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr15Spec; -impl crate::RegisterSpec for Pcr15Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr15::R`](R) reader structure"] -impl crate::Readable for Pcr15Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr15::W`](W) writer structure"] -impl crate::Writable for Pcr15Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR15 to value 0"] -impl crate::Resettable for Pcr15Spec {} diff --git a/mcxa276-pac/src/port4/pcr16.rs b/mcxa276-pac/src/port4/pcr16.rs deleted file mode 100644 index 1f5b9f2a8..000000000 --- a/mcxa276-pac/src/port4/pcr16.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR16` reader"] -pub type R = crate::R; -#[doc = "Register `PCR16` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr16Spec; -impl crate::RegisterSpec for Pcr16Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr16::R`](R) reader structure"] -impl crate::Readable for Pcr16Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr16::W`](W) writer structure"] -impl crate::Writable for Pcr16Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR16 to value 0"] -impl crate::Resettable for Pcr16Spec {} diff --git a/mcxa276-pac/src/port4/pcr17.rs b/mcxa276-pac/src/port4/pcr17.rs deleted file mode 100644 index 261687632..000000000 --- a/mcxa276-pac/src/port4/pcr17.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR17` reader"] -pub type R = crate::R; -#[doc = "Register `PCR17` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr17Spec; -impl crate::RegisterSpec for Pcr17Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr17::R`](R) reader structure"] -impl crate::Readable for Pcr17Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr17::W`](W) writer structure"] -impl crate::Writable for Pcr17Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR17 to value 0"] -impl crate::Resettable for Pcr17Spec {} diff --git a/mcxa276-pac/src/port4/pcr18.rs b/mcxa276-pac/src/port4/pcr18.rs deleted file mode 100644 index b6b60a1fc..000000000 --- a/mcxa276-pac/src/port4/pcr18.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR18` reader"] -pub type R = crate::R; -#[doc = "Register `PCR18` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr18Spec; -impl crate::RegisterSpec for Pcr18Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr18::R`](R) reader structure"] -impl crate::Readable for Pcr18Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr18::W`](W) writer structure"] -impl crate::Writable for Pcr18Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR18 to value 0"] -impl crate::Resettable for Pcr18Spec {} diff --git a/mcxa276-pac/src/port4/pcr19.rs b/mcxa276-pac/src/port4/pcr19.rs deleted file mode 100644 index 231169e90..000000000 --- a/mcxa276-pac/src/port4/pcr19.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR19` reader"] -pub type R = crate::R; -#[doc = "Register `PCR19` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr19Spec; -impl crate::RegisterSpec for Pcr19Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr19::R`](R) reader structure"] -impl crate::Readable for Pcr19Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr19::W`](W) writer structure"] -impl crate::Writable for Pcr19Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR19 to value 0"] -impl crate::Resettable for Pcr19Spec {} diff --git a/mcxa276-pac/src/port4/pcr2.rs b/mcxa276-pac/src/port4/pcr2.rs deleted file mode 100644 index 2bdea035c..000000000 --- a/mcxa276-pac/src/port4/pcr2.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR2` reader"] -pub type R = crate::R; -#[doc = "Register `PCR2` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr2Spec; -impl crate::RegisterSpec for Pcr2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr2::R`](R) reader structure"] -impl crate::Readable for Pcr2Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr2::W`](W) writer structure"] -impl crate::Writable for Pcr2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR2 to value 0"] -impl crate::Resettable for Pcr2Spec {} diff --git a/mcxa276-pac/src/port4/pcr20.rs b/mcxa276-pac/src/port4/pcr20.rs deleted file mode 100644 index d3457f781..000000000 --- a/mcxa276-pac/src/port4/pcr20.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR20` reader"] -pub type R = crate::R; -#[doc = "Register `PCR20` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr20Spec; -impl crate::RegisterSpec for Pcr20Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr20::R`](R) reader structure"] -impl crate::Readable for Pcr20Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr20::W`](W) writer structure"] -impl crate::Writable for Pcr20Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR20 to value 0"] -impl crate::Resettable for Pcr20Spec {} diff --git a/mcxa276-pac/src/port4/pcr21.rs b/mcxa276-pac/src/port4/pcr21.rs deleted file mode 100644 index 549acb257..000000000 --- a/mcxa276-pac/src/port4/pcr21.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR21` reader"] -pub type R = crate::R; -#[doc = "Register `PCR21` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr21Spec; -impl crate::RegisterSpec for Pcr21Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr21::R`](R) reader structure"] -impl crate::Readable for Pcr21Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr21::W`](W) writer structure"] -impl crate::Writable for Pcr21Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR21 to value 0"] -impl crate::Resettable for Pcr21Spec {} diff --git a/mcxa276-pac/src/port4/pcr22.rs b/mcxa276-pac/src/port4/pcr22.rs deleted file mode 100644 index b52c672cb..000000000 --- a/mcxa276-pac/src/port4/pcr22.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR22` reader"] -pub type R = crate::R; -#[doc = "Register `PCR22` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr22Spec; -impl crate::RegisterSpec for Pcr22Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr22::R`](R) reader structure"] -impl crate::Readable for Pcr22Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr22::W`](W) writer structure"] -impl crate::Writable for Pcr22Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR22 to value 0"] -impl crate::Resettable for Pcr22Spec {} diff --git a/mcxa276-pac/src/port4/pcr23.rs b/mcxa276-pac/src/port4/pcr23.rs deleted file mode 100644 index 918e561a9..000000000 --- a/mcxa276-pac/src/port4/pcr23.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR23` reader"] -pub type R = crate::R; -#[doc = "Register `PCR23` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr23Spec; -impl crate::RegisterSpec for Pcr23Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr23::R`](R) reader structure"] -impl crate::Readable for Pcr23Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr23::W`](W) writer structure"] -impl crate::Writable for Pcr23Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR23 to value 0"] -impl crate::Resettable for Pcr23Spec {} diff --git a/mcxa276-pac/src/port4/pcr24.rs b/mcxa276-pac/src/port4/pcr24.rs deleted file mode 100644 index 1bc9d5574..000000000 --- a/mcxa276-pac/src/port4/pcr24.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR24` reader"] -pub type R = crate::R; -#[doc = "Register `PCR24` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr24Spec; -impl crate::RegisterSpec for Pcr24Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr24::R`](R) reader structure"] -impl crate::Readable for Pcr24Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr24::W`](W) writer structure"] -impl crate::Writable for Pcr24Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR24 to value 0"] -impl crate::Resettable for Pcr24Spec {} diff --git a/mcxa276-pac/src/port4/pcr25.rs b/mcxa276-pac/src/port4/pcr25.rs deleted file mode 100644 index dbc8cae05..000000000 --- a/mcxa276-pac/src/port4/pcr25.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR25` reader"] -pub type R = crate::R; -#[doc = "Register `PCR25` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr25Spec; -impl crate::RegisterSpec for Pcr25Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr25::R`](R) reader structure"] -impl crate::Readable for Pcr25Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr25::W`](W) writer structure"] -impl crate::Writable for Pcr25Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR25 to value 0"] -impl crate::Resettable for Pcr25Spec {} diff --git a/mcxa276-pac/src/port4/pcr26.rs b/mcxa276-pac/src/port4/pcr26.rs deleted file mode 100644 index 24ffb3145..000000000 --- a/mcxa276-pac/src/port4/pcr26.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR26` reader"] -pub type R = crate::R; -#[doc = "Register `PCR26` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr26Spec; -impl crate::RegisterSpec for Pcr26Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr26::R`](R) reader structure"] -impl crate::Readable for Pcr26Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr26::W`](W) writer structure"] -impl crate::Writable for Pcr26Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR26 to value 0"] -impl crate::Resettable for Pcr26Spec {} diff --git a/mcxa276-pac/src/port4/pcr27.rs b/mcxa276-pac/src/port4/pcr27.rs deleted file mode 100644 index ac4a51d32..000000000 --- a/mcxa276-pac/src/port4/pcr27.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR27` reader"] -pub type R = crate::R; -#[doc = "Register `PCR27` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr27Spec; -impl crate::RegisterSpec for Pcr27Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr27::R`](R) reader structure"] -impl crate::Readable for Pcr27Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr27::W`](W) writer structure"] -impl crate::Writable for Pcr27Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR27 to value 0"] -impl crate::Resettable for Pcr27Spec {} diff --git a/mcxa276-pac/src/port4/pcr28.rs b/mcxa276-pac/src/port4/pcr28.rs deleted file mode 100644 index 1315078be..000000000 --- a/mcxa276-pac/src/port4/pcr28.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR28` reader"] -pub type R = crate::R; -#[doc = "Register `PCR28` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr28Spec; -impl crate::RegisterSpec for Pcr28Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr28::R`](R) reader structure"] -impl crate::Readable for Pcr28Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr28::W`](W) writer structure"] -impl crate::Writable for Pcr28Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR28 to value 0"] -impl crate::Resettable for Pcr28Spec {} diff --git a/mcxa276-pac/src/port4/pcr29.rs b/mcxa276-pac/src/port4/pcr29.rs deleted file mode 100644 index de7c41baa..000000000 --- a/mcxa276-pac/src/port4/pcr29.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR29` reader"] -pub type R = crate::R; -#[doc = "Register `PCR29` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr29Spec; -impl crate::RegisterSpec for Pcr29Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr29::R`](R) reader structure"] -impl crate::Readable for Pcr29Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr29::W`](W) writer structure"] -impl crate::Writable for Pcr29Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR29 to value 0"] -impl crate::Resettable for Pcr29Spec {} diff --git a/mcxa276-pac/src/port4/pcr3.rs b/mcxa276-pac/src/port4/pcr3.rs deleted file mode 100644 index 8d707c930..000000000 --- a/mcxa276-pac/src/port4/pcr3.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR3` reader"] -pub type R = crate::R; -#[doc = "Register `PCR3` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr3Spec; -impl crate::RegisterSpec for Pcr3Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr3::R`](R) reader structure"] -impl crate::Readable for Pcr3Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr3::W`](W) writer structure"] -impl crate::Writable for Pcr3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR3 to value 0"] -impl crate::Resettable for Pcr3Spec {} diff --git a/mcxa276-pac/src/port4/pcr30.rs b/mcxa276-pac/src/port4/pcr30.rs deleted file mode 100644 index cce4166f4..000000000 --- a/mcxa276-pac/src/port4/pcr30.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR30` reader"] -pub type R = crate::R; -#[doc = "Register `PCR30` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr30Spec; -impl crate::RegisterSpec for Pcr30Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr30::R`](R) reader structure"] -impl crate::Readable for Pcr30Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr30::W`](W) writer structure"] -impl crate::Writable for Pcr30Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR30 to value 0"] -impl crate::Resettable for Pcr30Spec {} diff --git a/mcxa276-pac/src/port4/pcr31.rs b/mcxa276-pac/src/port4/pcr31.rs deleted file mode 100644 index 1f49159c2..000000000 --- a/mcxa276-pac/src/port4/pcr31.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR31` reader"] -pub type R = crate::R; -#[doc = "Register `PCR31` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr31Spec; -impl crate::RegisterSpec for Pcr31Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr31::R`](R) reader structure"] -impl crate::Readable for Pcr31Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr31::W`](W) writer structure"] -impl crate::Writable for Pcr31Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR31 to value 0"] -impl crate::Resettable for Pcr31Spec {} diff --git a/mcxa276-pac/src/port4/pcr4.rs b/mcxa276-pac/src/port4/pcr4.rs deleted file mode 100644 index 970ee4531..000000000 --- a/mcxa276-pac/src/port4/pcr4.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR4` reader"] -pub type R = crate::R; -#[doc = "Register `PCR4` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr4Spec; -impl crate::RegisterSpec for Pcr4Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr4::R`](R) reader structure"] -impl crate::Readable for Pcr4Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr4::W`](W) writer structure"] -impl crate::Writable for Pcr4Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR4 to value 0"] -impl crate::Resettable for Pcr4Spec {} diff --git a/mcxa276-pac/src/port4/pcr5.rs b/mcxa276-pac/src/port4/pcr5.rs deleted file mode 100644 index 53dad0e29..000000000 --- a/mcxa276-pac/src/port4/pcr5.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR5` reader"] -pub type R = crate::R; -#[doc = "Register `PCR5` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr5Spec; -impl crate::RegisterSpec for Pcr5Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr5::R`](R) reader structure"] -impl crate::Readable for Pcr5Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr5::W`](W) writer structure"] -impl crate::Writable for Pcr5Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR5 to value 0"] -impl crate::Resettable for Pcr5Spec {} diff --git a/mcxa276-pac/src/port4/pcr6.rs b/mcxa276-pac/src/port4/pcr6.rs deleted file mode 100644 index d10e6a5b8..000000000 --- a/mcxa276-pac/src/port4/pcr6.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR6` reader"] -pub type R = crate::R; -#[doc = "Register `PCR6` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr6Spec; -impl crate::RegisterSpec for Pcr6Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr6::R`](R) reader structure"] -impl crate::Readable for Pcr6Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr6::W`](W) writer structure"] -impl crate::Writable for Pcr6Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR6 to value 0"] -impl crate::Resettable for Pcr6Spec {} diff --git a/mcxa276-pac/src/port4/pcr7.rs b/mcxa276-pac/src/port4/pcr7.rs deleted file mode 100644 index 18e6a4872..000000000 --- a/mcxa276-pac/src/port4/pcr7.rs +++ /dev/null @@ -1,673 +0,0 @@ -#[doc = "Register `PCR7` reader"] -pub type R = crate::R; -#[doc = "Register `PCR7` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Pin Multiplex Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mux { - #[doc = "0: Alternative 0 (GPIO)"] - Mux00 = 0, - #[doc = "1: Alternative 1 (chip-specific)"] - Mux01 = 1, - #[doc = "2: Alternative 2 (chip-specific)"] - Mux10 = 2, - #[doc = "3: Alternative 3 (chip-specific)"] - Mux11 = 3, - #[doc = "4: Alternative 4 (chip-specific)"] - Mux100 = 4, - #[doc = "5: Alternative 5 (chip-specific)"] - Mux101 = 5, - #[doc = "6: Alternative 6 (chip-specific)"] - Mux110 = 6, - #[doc = "7: Alternative 7 (chip-specific)"] - Mux111 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mux) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mux { - type Ux = u8; -} -impl crate::IsEnum for Mux {} -#[doc = "Field `MUX` reader - Pin Multiplex Control"] -pub type MuxR = crate::FieldReader; -impl MuxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mux { - match self.bits { - 0 => Mux::Mux00, - 1 => Mux::Mux01, - 2 => Mux::Mux10, - 3 => Mux::Mux11, - 4 => Mux::Mux100, - 5 => Mux::Mux101, - 6 => Mux::Mux110, - 7 => Mux::Mux111, - _ => unreachable!(), - } - } - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn is_mux00(&self) -> bool { - *self == Mux::Mux00 - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn is_mux01(&self) -> bool { - *self == Mux::Mux01 - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn is_mux10(&self) -> bool { - *self == Mux::Mux10 - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn is_mux11(&self) -> bool { - *self == Mux::Mux11 - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn is_mux100(&self) -> bool { - *self == Mux::Mux100 - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn is_mux101(&self) -> bool { - *self == Mux::Mux101 - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn is_mux110(&self) -> bool { - *self == Mux::Mux110 - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn is_mux111(&self) -> bool { - *self == Mux::Mux111 - } -} -#[doc = "Field `MUX` writer - Pin Multiplex Control"] -pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux, crate::Safe>; -impl<'a, REG> MuxW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Alternative 0 (GPIO)"] - #[inline(always)] - pub fn mux00(self) -> &'a mut crate::W { - self.variant(Mux::Mux00) - } - #[doc = "Alternative 1 (chip-specific)"] - #[inline(always)] - pub fn mux01(self) -> &'a mut crate::W { - self.variant(Mux::Mux01) - } - #[doc = "Alternative 2 (chip-specific)"] - #[inline(always)] - pub fn mux10(self) -> &'a mut crate::W { - self.variant(Mux::Mux10) - } - #[doc = "Alternative 3 (chip-specific)"] - #[inline(always)] - pub fn mux11(self) -> &'a mut crate::W { - self.variant(Mux::Mux11) - } - #[doc = "Alternative 4 (chip-specific)"] - #[inline(always)] - pub fn mux100(self) -> &'a mut crate::W { - self.variant(Mux::Mux100) - } - #[doc = "Alternative 5 (chip-specific)"] - #[inline(always)] - pub fn mux101(self) -> &'a mut crate::W { - self.variant(Mux::Mux101) - } - #[doc = "Alternative 6 (chip-specific)"] - #[inline(always)] - pub fn mux110(self) -> &'a mut crate::W { - self.variant(Mux::Mux110) - } - #[doc = "Alternative 7 (chip-specific)"] - #[inline(always)] - pub fn mux111(self) -> &'a mut crate::W { - self.variant(Mux::Mux111) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&self) -> MuxR { - MuxR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bits 8:10 - Pin Multiplex Control"] - #[inline(always)] - pub fn mux(&mut self) -> MuxW { - MuxW::new(self, 8) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr7Spec; -impl crate::RegisterSpec for Pcr7Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr7::R`](R) reader structure"] -impl crate::Readable for Pcr7Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr7::W`](W) writer structure"] -impl crate::Writable for Pcr7Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR7 to value 0"] -impl crate::Resettable for Pcr7Spec {} diff --git a/mcxa276-pac/src/port4/pcr8.rs b/mcxa276-pac/src/port4/pcr8.rs deleted file mode 100644 index 8c6d7289b..000000000 --- a/mcxa276-pac/src/port4/pcr8.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR8` reader"] -pub type R = crate::R; -#[doc = "Register `PCR8` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr8Spec; -impl crate::RegisterSpec for Pcr8Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr8::R`](R) reader structure"] -impl crate::Readable for Pcr8Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr8::W`](W) writer structure"] -impl crate::Writable for Pcr8Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR8 to value 0"] -impl crate::Resettable for Pcr8Spec {} diff --git a/mcxa276-pac/src/port4/pcr9.rs b/mcxa276-pac/src/port4/pcr9.rs deleted file mode 100644 index 403e7e331..000000000 --- a/mcxa276-pac/src/port4/pcr9.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `PCR9` reader"] -pub type R = crate::R; -#[doc = "Register `PCR9` writer"] -pub type W = crate::W; -#[doc = "Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ps { - #[doc = "0: Enables internal pulldown resistor"] - Ps0 = 0, - #[doc = "1: Enables internal pullup resistor"] - Ps1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PS` reader - Pull Select"] -pub type PsR = crate::BitReader; -impl PsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ps { - match self.bits { - false => Ps::Ps0, - true => Ps::Ps1, - } - } - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn is_ps0(&self) -> bool { - *self == Ps::Ps0 - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn is_ps1(&self) -> bool { - *self == Ps::Ps1 - } -} -#[doc = "Field `PS` writer - Pull Select"] -pub type PsW<'a, REG> = crate::BitWriter<'a, REG, Ps>; -impl<'a, REG> PsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables internal pulldown resistor"] - #[inline(always)] - pub fn ps0(self) -> &'a mut crate::W { - self.variant(Ps::Ps0) - } - #[doc = "Enables internal pullup resistor"] - #[inline(always)] - pub fn ps1(self) -> &'a mut crate::W { - self.variant(Ps::Ps1) - } -} -#[doc = "Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pe { - #[doc = "0: Disables"] - Pe0 = 0, - #[doc = "1: Enables"] - Pe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PE` reader - Pull Enable"] -pub type PeR = crate::BitReader; -impl PeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pe { - match self.bits { - false => Pe::Pe0, - true => Pe::Pe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_pe0(&self) -> bool { - *self == Pe::Pe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_pe1(&self) -> bool { - *self == Pe::Pe1 - } -} -#[doc = "Field `PE` writer - Pull Enable"] -pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; -impl<'a, REG> PeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn pe0(self) -> &'a mut crate::W { - self.variant(Pe::Pe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn pe1(self) -> &'a mut crate::W { - self.variant(Pe::Pe1) - } -} -#[doc = "Slew Rate Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sre { - #[doc = "0: Fast"] - Sre0 = 0, - #[doc = "1: Slow"] - Sre1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRE` reader - Slew Rate Enable"] -pub type SreR = crate::BitReader; -impl SreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sre { - match self.bits { - false => Sre::Sre0, - true => Sre::Sre1, - } - } - #[doc = "Fast"] - #[inline(always)] - pub fn is_sre0(&self) -> bool { - *self == Sre::Sre0 - } - #[doc = "Slow"] - #[inline(always)] - pub fn is_sre1(&self) -> bool { - *self == Sre::Sre1 - } -} -#[doc = "Field `SRE` writer - Slew Rate Enable"] -pub type SreW<'a, REG> = crate::BitWriter<'a, REG, Sre>; -impl<'a, REG> SreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fast"] - #[inline(always)] - pub fn sre0(self) -> &'a mut crate::W { - self.variant(Sre::Sre0) - } - #[doc = "Slow"] - #[inline(always)] - pub fn sre1(self) -> &'a mut crate::W { - self.variant(Sre::Sre1) - } -} -#[doc = "Open Drain Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ode { - #[doc = "0: Disables"] - Ode0 = 0, - #[doc = "1: Enables"] - Ode1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODE` reader - Open Drain Enable"] -pub type OdeR = crate::BitReader; -impl OdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ode { - match self.bits { - false => Ode::Ode0, - true => Ode::Ode1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ode0(&self) -> bool { - *self == Ode::Ode0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ode1(&self) -> bool { - *self == Ode::Ode1 - } -} -#[doc = "Field `ODE` writer - Open Drain Enable"] -pub type OdeW<'a, REG> = crate::BitWriter<'a, REG, Ode>; -impl<'a, REG> OdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ode0(self) -> &'a mut crate::W { - self.variant(Ode::Ode0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ode1(self) -> &'a mut crate::W { - self.variant(Ode::Ode1) - } -} -#[doc = "Drive Strength Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dse { - #[doc = "0: Low"] - Dse0 = 0, - #[doc = "1: High"] - Dse1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DSE` reader - Drive Strength Enable"] -pub type DseR = crate::BitReader; -impl DseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dse { - match self.bits { - false => Dse::Dse0, - true => Dse::Dse1, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_dse0(&self) -> bool { - *self == Dse::Dse0 - } - #[doc = "High"] - #[inline(always)] - pub fn is_dse1(&self) -> bool { - *self == Dse::Dse1 - } -} -#[doc = "Field `DSE` writer - Drive Strength Enable"] -pub type DseW<'a, REG> = crate::BitWriter<'a, REG, Dse>; -impl<'a, REG> DseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn dse0(self) -> &'a mut crate::W { - self.variant(Dse::Dse0) - } - #[doc = "High"] - #[inline(always)] - pub fn dse1(self) -> &'a mut crate::W { - self.variant(Dse::Dse1) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Ibe0 = 0, - #[doc = "1: Enables"] - Ibe1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Ibe0, - true => Ibe::Ibe1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_ibe0(&self) -> bool { - *self == Ibe::Ibe0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_ibe1(&self) -> bool { - *self == Ibe::Ibe1 - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn ibe0(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn ibe1(self) -> &'a mut crate::W { - self.variant(Ibe::Ibe1) - } -} -#[doc = "Invert Input\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inv { - #[doc = "0: Does not invert"] - Inv0 = 0, - #[doc = "1: Inverts"] - Inv1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INV` reader - Invert Input"] -pub type InvR = crate::BitReader; -impl InvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inv { - match self.bits { - false => Inv::Inv0, - true => Inv::Inv1, - } - } - #[doc = "Does not invert"] - #[inline(always)] - pub fn is_inv0(&self) -> bool { - *self == Inv::Inv0 - } - #[doc = "Inverts"] - #[inline(always)] - pub fn is_inv1(&self) -> bool { - *self == Inv::Inv1 - } -} -#[doc = "Field `INV` writer - Invert Input"] -pub type InvW<'a, REG> = crate::BitWriter<'a, REG, Inv>; -impl<'a, REG> InvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not invert"] - #[inline(always)] - pub fn inv0(self) -> &'a mut crate::W { - self.variant(Inv::Inv0) - } - #[doc = "Inverts"] - #[inline(always)] - pub fn inv1(self) -> &'a mut crate::W { - self.variant(Inv::Inv1) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Does not lock"] - Lk0 = 0, - #[doc = "1: Locks"] - Lk1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::Lk0, - true => Lk::Lk1, - } - } - #[doc = "Does not lock"] - #[inline(always)] - pub fn is_lk0(&self) -> bool { - *self == Lk::Lk0 - } - #[doc = "Locks"] - #[inline(always)] - pub fn is_lk1(&self) -> bool { - *self == Lk::Lk1 - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does not lock"] - #[inline(always)] - pub fn lk0(self) -> &'a mut crate::W { - self.variant(Lk::Lk0) - } - #[doc = "Locks"] - #[inline(always)] - pub fn lk1(self) -> &'a mut crate::W { - self.variant(Lk::Lk1) - } -} -impl R { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&self) -> PsR { - PsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&self) -> PeR { - PeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&self) -> SreR { - SreR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&self) -> OdeR { - OdeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&self) -> DseR { - DseR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&self) -> InvR { - InvR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Pull Select"] - #[inline(always)] - pub fn ps(&mut self) -> PsW { - PsW::new(self, 0) - } - #[doc = "Bit 1 - Pull Enable"] - #[inline(always)] - pub fn pe(&mut self) -> PeW { - PeW::new(self, 1) - } - #[doc = "Bit 3 - Slew Rate Enable"] - #[inline(always)] - pub fn sre(&mut self) -> SreW { - SreW::new(self, 3) - } - #[doc = "Bit 5 - Open Drain Enable"] - #[inline(always)] - pub fn ode(&mut self) -> OdeW { - OdeW::new(self, 5) - } - #[doc = "Bit 6 - Drive Strength Enable"] - #[inline(always)] - pub fn dse(&mut self) -> DseW { - DseW::new(self, 6) - } - #[doc = "Bit 12 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 12) - } - #[doc = "Bit 13 - Invert Input"] - #[inline(always)] - pub fn inv(&mut self) -> InvW { - InvW::new(self, 13) - } - #[doc = "Bit 15 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 15) - } -} -#[doc = "Pin Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`pcr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pcr9Spec; -impl crate::RegisterSpec for Pcr9Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pcr9::R`](R) reader structure"] -impl crate::Readable for Pcr9Spec {} -#[doc = "`write(|w| ..)` method takes [`pcr9::W`](W) writer structure"] -impl crate::Writable for Pcr9Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PCR9 to value 0"] -impl crate::Resettable for Pcr9Spec {} diff --git a/mcxa276-pac/src/port4/verid.rs b/mcxa276-pac/src/port4/verid.rs deleted file mode 100644 index 330f53d57..000000000 --- a/mcxa276-pac/src/port4/verid.rs +++ /dev/null @@ -1,68 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Basic implementation"] - Feature0 = 0, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Feature0), - _ => None, - } - } - #[doc = "Basic implementation"] - #[inline(always)] - pub fn is_feature0(&self) -> bool { - *self == Feature::Feature0 - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0200_0000"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0200_0000; -} diff --git a/mcxa276-pac/src/rtc0.rs b/mcxa276-pac/src/rtc0.rs deleted file mode 100644 index 5a61d64e8..000000000 --- a/mcxa276-pac/src/rtc0.rs +++ /dev/null @@ -1,94 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - tsr: Tsr, - tpr: Tpr, - tar: Tar, - tcr: Tcr, - cr: Cr, - sr: Sr, - lr: Lr, - ier: Ier, -} -impl RegisterBlock { - #[doc = "0x00 - RTC Time Seconds"] - #[inline(always)] - pub const fn tsr(&self) -> &Tsr { - &self.tsr - } - #[doc = "0x04 - RTC Time Prescaler"] - #[inline(always)] - pub const fn tpr(&self) -> &Tpr { - &self.tpr - } - #[doc = "0x08 - RTC Time Alarm"] - #[inline(always)] - pub const fn tar(&self) -> &Tar { - &self.tar - } - #[doc = "0x0c - RTC Time Compensation"] - #[inline(always)] - pub const fn tcr(&self) -> &Tcr { - &self.tcr - } - #[doc = "0x10 - RTC Control"] - #[inline(always)] - pub const fn cr(&self) -> &Cr { - &self.cr - } - #[doc = "0x14 - RTC Status"] - #[inline(always)] - pub const fn sr(&self) -> &Sr { - &self.sr - } - #[doc = "0x18 - RTC Lock"] - #[inline(always)] - pub const fn lr(&self) -> &Lr { - &self.lr - } - #[doc = "0x1c - RTC Interrupt Enable"] - #[inline(always)] - pub const fn ier(&self) -> &Ier { - &self.ier - } -} -#[doc = "TSR (rw) register accessor: RTC Time Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsr`] module"] -#[doc(alias = "TSR")] -pub type Tsr = crate::Reg; -#[doc = "RTC Time Seconds"] -pub mod tsr; -#[doc = "TPR (rw) register accessor: RTC Time Prescaler\n\nYou can [`read`](crate::Reg::read) this register and get [`tpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpr`] module"] -#[doc(alias = "TPR")] -pub type Tpr = crate::Reg; -#[doc = "RTC Time Prescaler"] -pub mod tpr; -#[doc = "TAR (rw) register accessor: RTC Time Alarm\n\nYou can [`read`](crate::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] -#[doc(alias = "TAR")] -pub type Tar = crate::Reg; -#[doc = "RTC Time Alarm"] -pub mod tar; -#[doc = "TCR (rw) register accessor: RTC Time Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] module"] -#[doc(alias = "TCR")] -pub type Tcr = crate::Reg; -#[doc = "RTC Time Compensation"] -pub mod tcr; -#[doc = "CR (rw) register accessor: RTC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] -#[doc(alias = "CR")] -pub type Cr = crate::Reg; -#[doc = "RTC Control"] -pub mod cr; -#[doc = "SR (rw) register accessor: RTC Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] -#[doc(alias = "SR")] -pub type Sr = crate::Reg; -#[doc = "RTC Status"] -pub mod sr; -#[doc = "LR (rw) register accessor: RTC Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lr`] module"] -#[doc(alias = "LR")] -pub type Lr = crate::Reg; -#[doc = "RTC Lock"] -pub mod lr; -#[doc = "IER (rw) register accessor: RTC Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] -#[doc(alias = "IER")] -pub type Ier = crate::Reg; -#[doc = "RTC Interrupt Enable"] -pub mod ier; diff --git a/mcxa276-pac/src/rtc0/cr.rs b/mcxa276-pac/src/rtc0/cr.rs deleted file mode 100644 index c4935c9aa..000000000 --- a/mcxa276-pac/src/rtc0/cr.rs +++ /dev/null @@ -1,212 +0,0 @@ -#[doc = "Register `CR` reader"] -pub type R = crate::R; -#[doc = "Register `CR` writer"] -pub type W = crate::W; -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swr { - #[doc = "0: No effect."] - Swr0 = 0, - #[doc = "1: Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."] - Swr1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWR` reader - Software Reset"] -pub type SwrR = crate::BitReader; -impl SwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swr { - match self.bits { - false => Swr::Swr0, - true => Swr::Swr1, - } - } - #[doc = "No effect."] - #[inline(always)] - pub fn is_swr_0(&self) -> bool { - *self == Swr::Swr0 - } - #[doc = "Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."] - #[inline(always)] - pub fn is_swr_1(&self) -> bool { - *self == Swr::Swr1 - } -} -#[doc = "Field `SWR` writer - Software Reset"] -pub type SwrW<'a, REG> = crate::BitWriter<'a, REG, Swr>; -impl<'a, REG> SwrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect."] - #[inline(always)] - pub fn swr_0(self) -> &'a mut crate::W { - self.variant(Swr::Swr0) - } - #[doc = "Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."] - #[inline(always)] - pub fn swr_1(self) -> &'a mut crate::W { - self.variant(Swr::Swr1) - } -} -#[doc = "Update Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Um { - #[doc = "0: Registers cannot be written when locked."] - Um0 = 0, - #[doc = "1: Registers can be written when locked under limited conditions."] - Um1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Um) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UM` reader - Update Mode"] -pub type UmR = crate::BitReader; -impl UmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Um { - match self.bits { - false => Um::Um0, - true => Um::Um1, - } - } - #[doc = "Registers cannot be written when locked."] - #[inline(always)] - pub fn is_um_0(&self) -> bool { - *self == Um::Um0 - } - #[doc = "Registers can be written when locked under limited conditions."] - #[inline(always)] - pub fn is_um_1(&self) -> bool { - *self == Um::Um1 - } -} -#[doc = "Field `UM` writer - Update Mode"] -pub type UmW<'a, REG> = crate::BitWriter<'a, REG, Um>; -impl<'a, REG> UmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Registers cannot be written when locked."] - #[inline(always)] - pub fn um_0(self) -> &'a mut crate::W { - self.variant(Um::Um0) - } - #[doc = "Registers can be written when locked under limited conditions."] - #[inline(always)] - pub fn um_1(self) -> &'a mut crate::W { - self.variant(Um::Um1) - } -} -#[doc = "LPO Select\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpos { - #[doc = "0: RTC prescaler increments using 32.768 kHz clock."] - Lpos0 = 0, - #[doc = "1: RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."] - Lpos1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpos) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPOS` reader - LPO Select"] -pub type LposR = crate::BitReader; -impl LposR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpos { - match self.bits { - false => Lpos::Lpos0, - true => Lpos::Lpos1, - } - } - #[doc = "RTC prescaler increments using 32.768 kHz clock."] - #[inline(always)] - pub fn is_lpos_0(&self) -> bool { - *self == Lpos::Lpos0 - } - #[doc = "RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."] - #[inline(always)] - pub fn is_lpos_1(&self) -> bool { - *self == Lpos::Lpos1 - } -} -#[doc = "Field `LPOS` writer - LPO Select"] -pub type LposW<'a, REG> = crate::BitWriter<'a, REG, Lpos>; -impl<'a, REG> LposW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "RTC prescaler increments using 32.768 kHz clock."] - #[inline(always)] - pub fn lpos_0(self) -> &'a mut crate::W { - self.variant(Lpos::Lpos0) - } - #[doc = "RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."] - #[inline(always)] - pub fn lpos_1(self) -> &'a mut crate::W { - self.variant(Lpos::Lpos1) - } -} -impl R { - #[doc = "Bit 0 - Software Reset"] - #[inline(always)] - pub fn swr(&self) -> SwrR { - SwrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - Update Mode"] - #[inline(always)] - pub fn um(&self) -> UmR { - UmR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 7 - LPO Select"] - #[inline(always)] - pub fn lpos(&self) -> LposR { - LposR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Software Reset"] - #[inline(always)] - pub fn swr(&mut self) -> SwrW { - SwrW::new(self, 0) - } - #[doc = "Bit 3 - Update Mode"] - #[inline(always)] - pub fn um(&mut self) -> UmW { - UmW::new(self, 3) - } - #[doc = "Bit 7 - LPO Select"] - #[inline(always)] - pub fn lpos(&mut self) -> LposW { - LposW::new(self, 7) - } -} -#[doc = "RTC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CrSpec; -impl crate::RegisterSpec for CrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cr::R`](R) reader structure"] -impl crate::Readable for CrSpec {} -#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] -impl crate::Writable for CrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CR to value 0x80"] -impl crate::Resettable for CrSpec { - const RESET_VALUE: u32 = 0x80; -} diff --git a/mcxa276-pac/src/rtc0/ier.rs b/mcxa276-pac/src/rtc0/ier.rs deleted file mode 100644 index ca93c35a4..000000000 --- a/mcxa276-pac/src/rtc0/ier.rs +++ /dev/null @@ -1,423 +0,0 @@ -#[doc = "Register `IER` reader"] -pub type R = crate::R; -#[doc = "Register `IER` writer"] -pub type W = crate::W; -#[doc = "Time Invalid Interrupt Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie { - #[doc = "0: No interrupt is generated."] - Tiie0 = 0, - #[doc = "1: An interrupt is generated."] - Tiie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE` reader - Time Invalid Interrupt Enable"] -pub type TiieR = crate::BitReader; -impl TiieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie { - match self.bits { - false => Tiie::Tiie0, - true => Tiie::Tiie1, - } - } - #[doc = "No interrupt is generated."] - #[inline(always)] - pub fn is_tiie_0(&self) -> bool { - *self == Tiie::Tiie0 - } - #[doc = "An interrupt is generated."] - #[inline(always)] - pub fn is_tiie_1(&self) -> bool { - *self == Tiie::Tiie1 - } -} -#[doc = "Field `TIIE` writer - Time Invalid Interrupt Enable"] -pub type TiieW<'a, REG> = crate::BitWriter<'a, REG, Tiie>; -impl<'a, REG> TiieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No interrupt is generated."] - #[inline(always)] - pub fn tiie_0(self) -> &'a mut crate::W { - self.variant(Tiie::Tiie0) - } - #[doc = "An interrupt is generated."] - #[inline(always)] - pub fn tiie_1(self) -> &'a mut crate::W { - self.variant(Tiie::Tiie1) - } -} -#[doc = "Time Overflow Interrupt Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Toie { - #[doc = "0: No interrupt is generated."] - Toie0 = 0, - #[doc = "1: An interrupt is generated."] - Toie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Toie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TOIE` reader - Time Overflow Interrupt Enable"] -pub type ToieR = crate::BitReader; -impl ToieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Toie { - match self.bits { - false => Toie::Toie0, - true => Toie::Toie1, - } - } - #[doc = "No interrupt is generated."] - #[inline(always)] - pub fn is_toie_0(&self) -> bool { - *self == Toie::Toie0 - } - #[doc = "An interrupt is generated."] - #[inline(always)] - pub fn is_toie_1(&self) -> bool { - *self == Toie::Toie1 - } -} -#[doc = "Field `TOIE` writer - Time Overflow Interrupt Enable"] -pub type ToieW<'a, REG> = crate::BitWriter<'a, REG, Toie>; -impl<'a, REG> ToieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No interrupt is generated."] - #[inline(always)] - pub fn toie_0(self) -> &'a mut crate::W { - self.variant(Toie::Toie0) - } - #[doc = "An interrupt is generated."] - #[inline(always)] - pub fn toie_1(self) -> &'a mut crate::W { - self.variant(Toie::Toie1) - } -} -#[doc = "Time Alarm Interrupt Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Taie { - #[doc = "0: No interrupt is generated."] - Taie0 = 0, - #[doc = "1: An interrupt is generated."] - Taie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Taie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TAIE` reader - Time Alarm Interrupt Enable"] -pub type TaieR = crate::BitReader; -impl TaieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Taie { - match self.bits { - false => Taie::Taie0, - true => Taie::Taie1, - } - } - #[doc = "No interrupt is generated."] - #[inline(always)] - pub fn is_taie_0(&self) -> bool { - *self == Taie::Taie0 - } - #[doc = "An interrupt is generated."] - #[inline(always)] - pub fn is_taie_1(&self) -> bool { - *self == Taie::Taie1 - } -} -#[doc = "Field `TAIE` writer - Time Alarm Interrupt Enable"] -pub type TaieW<'a, REG> = crate::BitWriter<'a, REG, Taie>; -impl<'a, REG> TaieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No interrupt is generated."] - #[inline(always)] - pub fn taie_0(self) -> &'a mut crate::W { - self.variant(Taie::Taie0) - } - #[doc = "An interrupt is generated."] - #[inline(always)] - pub fn taie_1(self) -> &'a mut crate::W { - self.variant(Taie::Taie1) - } -} -#[doc = "Time Seconds Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tsie { - #[doc = "0: Disables"] - Tsie0 = 0, - #[doc = "1: Enables"] - Tsie1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tsie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TSIE` reader - Time Seconds Interrupt Enable"] -pub type TsieR = crate::BitReader; -impl TsieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tsie { - match self.bits { - false => Tsie::Tsie0, - true => Tsie::Tsie1, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_tsie_0(&self) -> bool { - *self == Tsie::Tsie0 - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_tsie_1(&self) -> bool { - *self == Tsie::Tsie1 - } -} -#[doc = "Field `TSIE` writer - Time Seconds Interrupt Enable"] -pub type TsieW<'a, REG> = crate::BitWriter<'a, REG, Tsie>; -impl<'a, REG> TsieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn tsie_0(self) -> &'a mut crate::W { - self.variant(Tsie::Tsie0) - } - #[doc = "Enables"] - #[inline(always)] - pub fn tsie_1(self) -> &'a mut crate::W { - self.variant(Tsie::Tsie1) - } -} -#[doc = "Timer Seconds Interrupt Configuration\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tsic { - #[doc = "0: 1 Hz."] - Tsic0 = 0, - #[doc = "1: 2 Hz."] - Tsic1 = 1, - #[doc = "2: 4 Hz."] - Tsic2 = 2, - #[doc = "3: 8 Hz."] - Tsic3 = 3, - #[doc = "4: 16 Hz."] - Tsic4 = 4, - #[doc = "5: 32 Hz."] - Tsic5 = 5, - #[doc = "6: 64 Hz."] - Tsic6 = 6, - #[doc = "7: 128 Hz."] - Tsic7 = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tsic) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tsic { - type Ux = u8; -} -impl crate::IsEnum for Tsic {} -#[doc = "Field `TSIC` reader - Timer Seconds Interrupt Configuration"] -pub type TsicR = crate::FieldReader; -impl TsicR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tsic { - match self.bits { - 0 => Tsic::Tsic0, - 1 => Tsic::Tsic1, - 2 => Tsic::Tsic2, - 3 => Tsic::Tsic3, - 4 => Tsic::Tsic4, - 5 => Tsic::Tsic5, - 6 => Tsic::Tsic6, - 7 => Tsic::Tsic7, - _ => unreachable!(), - } - } - #[doc = "1 Hz."] - #[inline(always)] - pub fn is_tsic_0(&self) -> bool { - *self == Tsic::Tsic0 - } - #[doc = "2 Hz."] - #[inline(always)] - pub fn is_tsic_1(&self) -> bool { - *self == Tsic::Tsic1 - } - #[doc = "4 Hz."] - #[inline(always)] - pub fn is_tsic_2(&self) -> bool { - *self == Tsic::Tsic2 - } - #[doc = "8 Hz."] - #[inline(always)] - pub fn is_tsic_3(&self) -> bool { - *self == Tsic::Tsic3 - } - #[doc = "16 Hz."] - #[inline(always)] - pub fn is_tsic_4(&self) -> bool { - *self == Tsic::Tsic4 - } - #[doc = "32 Hz."] - #[inline(always)] - pub fn is_tsic_5(&self) -> bool { - *self == Tsic::Tsic5 - } - #[doc = "64 Hz."] - #[inline(always)] - pub fn is_tsic_6(&self) -> bool { - *self == Tsic::Tsic6 - } - #[doc = "128 Hz."] - #[inline(always)] - pub fn is_tsic_7(&self) -> bool { - *self == Tsic::Tsic7 - } -} -#[doc = "Field `TSIC` writer - Timer Seconds Interrupt Configuration"] -pub type TsicW<'a, REG> = crate::FieldWriter<'a, REG, 3, Tsic, crate::Safe>; -impl<'a, REG> TsicW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "1 Hz."] - #[inline(always)] - pub fn tsic_0(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic0) - } - #[doc = "2 Hz."] - #[inline(always)] - pub fn tsic_1(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic1) - } - #[doc = "4 Hz."] - #[inline(always)] - pub fn tsic_2(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic2) - } - #[doc = "8 Hz."] - #[inline(always)] - pub fn tsic_3(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic3) - } - #[doc = "16 Hz."] - #[inline(always)] - pub fn tsic_4(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic4) - } - #[doc = "32 Hz."] - #[inline(always)] - pub fn tsic_5(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic5) - } - #[doc = "64 Hz."] - #[inline(always)] - pub fn tsic_6(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic6) - } - #[doc = "128 Hz."] - #[inline(always)] - pub fn tsic_7(self) -> &'a mut crate::W { - self.variant(Tsic::Tsic7) - } -} -impl R { - #[doc = "Bit 0 - Time Invalid Interrupt Enable"] - #[inline(always)] - pub fn tiie(&self) -> TiieR { - TiieR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Time Overflow Interrupt Enable"] - #[inline(always)] - pub fn toie(&self) -> ToieR { - ToieR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Time Alarm Interrupt Enable"] - #[inline(always)] - pub fn taie(&self) -> TaieR { - TaieR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - Time Seconds Interrupt Enable"] - #[inline(always)] - pub fn tsie(&self) -> TsieR { - TsieR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 16:18 - Timer Seconds Interrupt Configuration"] - #[inline(always)] - pub fn tsic(&self) -> TsicR { - TsicR::new(((self.bits >> 16) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Time Invalid Interrupt Enable"] - #[inline(always)] - pub fn tiie(&mut self) -> TiieW { - TiieW::new(self, 0) - } - #[doc = "Bit 1 - Time Overflow Interrupt Enable"] - #[inline(always)] - pub fn toie(&mut self) -> ToieW { - ToieW::new(self, 1) - } - #[doc = "Bit 2 - Time Alarm Interrupt Enable"] - #[inline(always)] - pub fn taie(&mut self) -> TaieW { - TaieW::new(self, 2) - } - #[doc = "Bit 4 - Time Seconds Interrupt Enable"] - #[inline(always)] - pub fn tsie(&mut self) -> TsieW { - TsieW::new(self, 4) - } - #[doc = "Bits 16:18 - Timer Seconds Interrupt Configuration"] - #[inline(always)] - pub fn tsic(&mut self) -> TsicW { - TsicW::new(self, 16) - } -} -#[doc = "RTC Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IerSpec; -impl crate::RegisterSpec for IerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ier::R`](R) reader structure"] -impl crate::Readable for IerSpec {} -#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] -impl crate::Writable for IerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IER to value 0x07"] -impl crate::Resettable for IerSpec { - const RESET_VALUE: u32 = 0x07; -} diff --git a/mcxa276-pac/src/rtc0/lr.rs b/mcxa276-pac/src/rtc0/lr.rs deleted file mode 100644 index af475a01f..000000000 --- a/mcxa276-pac/src/rtc0/lr.rs +++ /dev/null @@ -1,275 +0,0 @@ -#[doc = "Register `LR` reader"] -pub type R = crate::R; -#[doc = "Register `LR` writer"] -pub type W = crate::W; -#[doc = "Time Compensation Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tcl { - #[doc = "0: Time Compensation Register is locked and writes are ignored."] - Tcl0 = 0, - #[doc = "1: Time Compensation Register is not locked and writes complete as normal."] - Tcl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tcl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCL` reader - Time Compensation Lock"] -pub type TclR = crate::BitReader; -impl TclR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tcl { - match self.bits { - false => Tcl::Tcl0, - true => Tcl::Tcl1, - } - } - #[doc = "Time Compensation Register is locked and writes are ignored."] - #[inline(always)] - pub fn is_tcl_0(&self) -> bool { - *self == Tcl::Tcl0 - } - #[doc = "Time Compensation Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn is_tcl_1(&self) -> bool { - *self == Tcl::Tcl1 - } -} -#[doc = "Field `TCL` writer - Time Compensation Lock"] -pub type TclW<'a, REG> = crate::BitWriter<'a, REG, Tcl>; -impl<'a, REG> TclW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Time Compensation Register is locked and writes are ignored."] - #[inline(always)] - pub fn tcl_0(self) -> &'a mut crate::W { - self.variant(Tcl::Tcl0) - } - #[doc = "Time Compensation Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn tcl_1(self) -> &'a mut crate::W { - self.variant(Tcl::Tcl1) - } -} -#[doc = "Control Register Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crl { - #[doc = "0: Control Register is locked and writes are ignored."] - Crl0 = 0, - #[doc = "1: Control Register is not locked and writes complete as normal."] - Crl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRL` reader - Control Register Lock"] -pub type CrlR = crate::BitReader; -impl CrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crl { - match self.bits { - false => Crl::Crl0, - true => Crl::Crl1, - } - } - #[doc = "Control Register is locked and writes are ignored."] - #[inline(always)] - pub fn is_crl_0(&self) -> bool { - *self == Crl::Crl0 - } - #[doc = "Control Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn is_crl_1(&self) -> bool { - *self == Crl::Crl1 - } -} -#[doc = "Field `CRL` writer - Control Register Lock"] -pub type CrlW<'a, REG> = crate::BitWriter<'a, REG, Crl>; -impl<'a, REG> CrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Control Register is locked and writes are ignored."] - #[inline(always)] - pub fn crl_0(self) -> &'a mut crate::W { - self.variant(Crl::Crl0) - } - #[doc = "Control Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn crl_1(self) -> &'a mut crate::W { - self.variant(Crl::Crl1) - } -} -#[doc = "Status Register Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Srl { - #[doc = "0: Status Register is locked and writes are ignored."] - Srl0 = 0, - #[doc = "1: Status Register is not locked and writes complete as normal."] - Srl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Srl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRL` reader - Status Register Lock"] -pub type SrlR = crate::BitReader; -impl SrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Srl { - match self.bits { - false => Srl::Srl0, - true => Srl::Srl1, - } - } - #[doc = "Status Register is locked and writes are ignored."] - #[inline(always)] - pub fn is_srl_0(&self) -> bool { - *self == Srl::Srl0 - } - #[doc = "Status Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn is_srl_1(&self) -> bool { - *self == Srl::Srl1 - } -} -#[doc = "Field `SRL` writer - Status Register Lock"] -pub type SrlW<'a, REG> = crate::BitWriter<'a, REG, Srl>; -impl<'a, REG> SrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Status Register is locked and writes are ignored."] - #[inline(always)] - pub fn srl_0(self) -> &'a mut crate::W { - self.variant(Srl::Srl0) - } - #[doc = "Status Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn srl_1(self) -> &'a mut crate::W { - self.variant(Srl::Srl1) - } -} -#[doc = "Lock Register Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lrl { - #[doc = "0: Lock Register is locked and writes are ignored."] - Lrl0 = 0, - #[doc = "1: Lock Register is not locked and writes complete as normal."] - Lrl1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lrl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LRL` reader - Lock Register Lock"] -pub type LrlR = crate::BitReader; -impl LrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lrl { - match self.bits { - false => Lrl::Lrl0, - true => Lrl::Lrl1, - } - } - #[doc = "Lock Register is locked and writes are ignored."] - #[inline(always)] - pub fn is_lrl_0(&self) -> bool { - *self == Lrl::Lrl0 - } - #[doc = "Lock Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn is_lrl_1(&self) -> bool { - *self == Lrl::Lrl1 - } -} -#[doc = "Field `LRL` writer - Lock Register Lock"] -pub type LrlW<'a, REG> = crate::BitWriter<'a, REG, Lrl>; -impl<'a, REG> LrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Lock Register is locked and writes are ignored."] - #[inline(always)] - pub fn lrl_0(self) -> &'a mut crate::W { - self.variant(Lrl::Lrl0) - } - #[doc = "Lock Register is not locked and writes complete as normal."] - #[inline(always)] - pub fn lrl_1(self) -> &'a mut crate::W { - self.variant(Lrl::Lrl1) - } -} -impl R { - #[doc = "Bit 3 - Time Compensation Lock"] - #[inline(always)] - pub fn tcl(&self) -> TclR { - TclR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Control Register Lock"] - #[inline(always)] - pub fn crl(&self) -> CrlR { - CrlR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Status Register Lock"] - #[inline(always)] - pub fn srl(&self) -> SrlR { - SrlR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Lock Register Lock"] - #[inline(always)] - pub fn lrl(&self) -> LrlR { - LrlR::new(((self.bits >> 6) & 1) != 0) - } -} -impl W { - #[doc = "Bit 3 - Time Compensation Lock"] - #[inline(always)] - pub fn tcl(&mut self) -> TclW { - TclW::new(self, 3) - } - #[doc = "Bit 4 - Control Register Lock"] - #[inline(always)] - pub fn crl(&mut self) -> CrlW { - CrlW::new(self, 4) - } - #[doc = "Bit 5 - Status Register Lock"] - #[inline(always)] - pub fn srl(&mut self) -> SrlW { - SrlW::new(self, 5) - } - #[doc = "Bit 6 - Lock Register Lock"] - #[inline(always)] - pub fn lrl(&mut self) -> LrlW { - LrlW::new(self, 6) - } -} -#[doc = "RTC Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LrSpec; -impl crate::RegisterSpec for LrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lr::R`](R) reader structure"] -impl crate::Readable for LrSpec {} -#[doc = "`write(|w| ..)` method takes [`lr::W`](W) writer structure"] -impl crate::Writable for LrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LR to value 0xff"] -impl crate::Resettable for LrSpec { - const RESET_VALUE: u32 = 0xff; -} diff --git a/mcxa276-pac/src/rtc0/sr.rs b/mcxa276-pac/src/rtc0/sr.rs deleted file mode 100644 index 208ae23dc..000000000 --- a/mcxa276-pac/src/rtc0/sr.rs +++ /dev/null @@ -1,209 +0,0 @@ -#[doc = "Register `SR` reader"] -pub type R = crate::R; -#[doc = "Register `SR` writer"] -pub type W = crate::W; -#[doc = "Time Invalid Flag\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif { - #[doc = "0: Time is valid."] - Tif0 = 0, - #[doc = "1: Time is invalid and time counter is read as zero."] - Tif1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF` reader - Time Invalid Flag"] -pub type TifR = crate::BitReader; -impl TifR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif { - match self.bits { - false => Tif::Tif0, - true => Tif::Tif1, - } - } - #[doc = "Time is valid."] - #[inline(always)] - pub fn is_tif_0(&self) -> bool { - *self == Tif::Tif0 - } - #[doc = "Time is invalid and time counter is read as zero."] - #[inline(always)] - pub fn is_tif_1(&self) -> bool { - *self == Tif::Tif1 - } -} -#[doc = "Time Overflow Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tof { - #[doc = "0: Time overflow has not occurred."] - Tof0 = 0, - #[doc = "1: Time overflow has occurred and time counter reads as zero."] - Tof1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TOF` reader - Time Overflow Flag"] -pub type TofR = crate::BitReader; -impl TofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tof { - match self.bits { - false => Tof::Tof0, - true => Tof::Tof1, - } - } - #[doc = "Time overflow has not occurred."] - #[inline(always)] - pub fn is_tof_0(&self) -> bool { - *self == Tof::Tof0 - } - #[doc = "Time overflow has occurred and time counter reads as zero."] - #[inline(always)] - pub fn is_tof_1(&self) -> bool { - *self == Tof::Tof1 - } -} -#[doc = "Time Alarm Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Taf { - #[doc = "0: Time alarm has not occurred."] - Taf0 = 0, - #[doc = "1: Time alarm has occurred."] - Taf1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Taf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TAF` reader - Time Alarm Flag"] -pub type TafR = crate::BitReader; -impl TafR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Taf { - match self.bits { - false => Taf::Taf0, - true => Taf::Taf1, - } - } - #[doc = "Time alarm has not occurred."] - #[inline(always)] - pub fn is_taf_0(&self) -> bool { - *self == Taf::Taf0 - } - #[doc = "Time alarm has occurred."] - #[inline(always)] - pub fn is_taf_1(&self) -> bool { - *self == Taf::Taf1 - } -} -#[doc = "Time Counter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tce { - #[doc = "0: Disables."] - Tce0 = 0, - #[doc = "1: Enables."] - Tce1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tce) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TCE` reader - Time Counter Enable"] -pub type TceR = crate::BitReader; -impl TceR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tce { - match self.bits { - false => Tce::Tce0, - true => Tce::Tce1, - } - } - #[doc = "Disables."] - #[inline(always)] - pub fn is_tce_0(&self) -> bool { - *self == Tce::Tce0 - } - #[doc = "Enables."] - #[inline(always)] - pub fn is_tce_1(&self) -> bool { - *self == Tce::Tce1 - } -} -#[doc = "Field `TCE` writer - Time Counter Enable"] -pub type TceW<'a, REG> = crate::BitWriter<'a, REG, Tce>; -impl<'a, REG> TceW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables."] - #[inline(always)] - pub fn tce_0(self) -> &'a mut crate::W { - self.variant(Tce::Tce0) - } - #[doc = "Enables."] - #[inline(always)] - pub fn tce_1(self) -> &'a mut crate::W { - self.variant(Tce::Tce1) - } -} -impl R { - #[doc = "Bit 0 - Time Invalid Flag"] - #[inline(always)] - pub fn tif(&self) -> TifR { - TifR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Time Overflow Flag"] - #[inline(always)] - pub fn tof(&self) -> TofR { - TofR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Time Alarm Flag"] - #[inline(always)] - pub fn taf(&self) -> TafR { - TafR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - Time Counter Enable"] - #[inline(always)] - pub fn tce(&self) -> TceR { - TceR::new(((self.bits >> 4) & 1) != 0) - } -} -impl W { - #[doc = "Bit 4 - Time Counter Enable"] - #[inline(always)] - pub fn tce(&mut self) -> TceW { - TceW::new(self, 4) - } -} -#[doc = "RTC Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrSpec; -impl crate::RegisterSpec for SrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sr::R`](R) reader structure"] -impl crate::Readable for SrSpec {} -#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] -impl crate::Writable for SrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SR to value 0x01"] -impl crate::Resettable for SrSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/rtc0/tar.rs b/mcxa276-pac/src/rtc0/tar.rs deleted file mode 100644 index e12208b2b..000000000 --- a/mcxa276-pac/src/rtc0/tar.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TAR` reader"] -pub type R = crate::R; -#[doc = "Register `TAR` writer"] -pub type W = crate::W; -#[doc = "Field `TAR` reader - Time Alarm Register"] -pub type TarR = crate::FieldReader; -#[doc = "Field `TAR` writer - Time Alarm Register"] -pub type TarW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Time Alarm Register"] - #[inline(always)] - pub fn tar(&self) -> TarR { - TarR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Time Alarm Register"] - #[inline(always)] - pub fn tar(&mut self) -> TarW { - TarW::new(self, 0) - } -} -#[doc = "RTC Time Alarm\n\nYou can [`read`](crate::Reg::read) this register and get [`tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TarSpec; -impl crate::RegisterSpec for TarSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tar::R`](R) reader structure"] -impl crate::Readable for TarSpec {} -#[doc = "`write(|w| ..)` method takes [`tar::W`](W) writer structure"] -impl crate::Writable for TarSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TAR to value 0"] -impl crate::Resettable for TarSpec {} diff --git a/mcxa276-pac/src/rtc0/tcr.rs b/mcxa276-pac/src/rtc0/tcr.rs deleted file mode 100644 index fab51d2aa..000000000 --- a/mcxa276-pac/src/rtc0/tcr.rs +++ /dev/null @@ -1,184 +0,0 @@ -#[doc = "Register `TCR` reader"] -pub type R = crate::R; -#[doc = "Register `TCR` writer"] -pub type W = crate::W; -#[doc = "Time Compensation Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tcr { - #[doc = "0: Time Prescaler Register overflows every 32768 clock cycles."] - Tcr0 = 0, - #[doc = "1: Time Prescaler Register overflows every 32767 clock cycles."] - Tcr1 = 1, - #[doc = "126: Time Prescaler Register overflows every 32642 clock cycles."] - Tcr126 = 126, - #[doc = "127: Time Prescaler Register overflows every 32641 clock cycles."] - Tcr127 = 127, - #[doc = "128: Time Prescaler Register overflows every 32896 clock cycles."] - Tcr128 = 128, - #[doc = "129: Time Prescaler Register overflows every 32895 clock cycles."] - Tcr129 = 129, - #[doc = "255: Time Prescaler Register overflows every 32769 clock cycles."] - Tcr255 = 255, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tcr) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tcr { - type Ux = u8; -} -impl crate::IsEnum for Tcr {} -#[doc = "Field `TCR` reader - Time Compensation Register"] -pub type TcrR = crate::FieldReader; -impl TcrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Tcr::Tcr0), - 1 => Some(Tcr::Tcr1), - 126 => Some(Tcr::Tcr126), - 127 => Some(Tcr::Tcr127), - 128 => Some(Tcr::Tcr128), - 129 => Some(Tcr::Tcr129), - 255 => Some(Tcr::Tcr255), - _ => None, - } - } - #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] - #[inline(always)] - pub fn is_tcr_0(&self) -> bool { - *self == Tcr::Tcr0 - } - #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] - #[inline(always)] - pub fn is_tcr_1(&self) -> bool { - *self == Tcr::Tcr1 - } - #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] - #[inline(always)] - pub fn is_tcr_126(&self) -> bool { - *self == Tcr::Tcr126 - } - #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] - #[inline(always)] - pub fn is_tcr_127(&self) -> bool { - *self == Tcr::Tcr127 - } - #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] - #[inline(always)] - pub fn is_tcr_128(&self) -> bool { - *self == Tcr::Tcr128 - } - #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] - #[inline(always)] - pub fn is_tcr_129(&self) -> bool { - *self == Tcr::Tcr129 - } - #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] - #[inline(always)] - pub fn is_tcr_255(&self) -> bool { - *self == Tcr::Tcr255 - } -} -#[doc = "Field `TCR` writer - Time Compensation Register"] -pub type TcrW<'a, REG> = crate::FieldWriter<'a, REG, 8, Tcr>; -impl<'a, REG> TcrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] - #[inline(always)] - pub fn tcr_0(self) -> &'a mut crate::W { - self.variant(Tcr::Tcr0) - } - #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] - #[inline(always)] - pub fn tcr_1(self) -> &'a mut crate::W { - self.variant(Tcr::Tcr1) - } - #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] - #[inline(always)] - pub fn tcr_126(self) -> &'a mut crate::W { - self.variant(Tcr::Tcr126) - } - #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] - #[inline(always)] - pub fn tcr_127(self) -> &'a mut crate::W { - self.variant(Tcr::Tcr127) - } - #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] - #[inline(always)] - pub fn tcr_128(self) -> &'a mut crate::W { - self.variant(Tcr::Tcr128) - } - #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] - #[inline(always)] - pub fn tcr_129(self) -> &'a mut crate::W { - self.variant(Tcr::Tcr129) - } - #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] - #[inline(always)] - pub fn tcr_255(self) -> &'a mut crate::W { - self.variant(Tcr::Tcr255) - } -} -#[doc = "Field `CIR` reader - Compensation Interval Register"] -pub type CirR = crate::FieldReader; -#[doc = "Field `CIR` writer - Compensation Interval Register"] -pub type CirW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `TCV` reader - Time Compensation Value"] -pub type TcvR = crate::FieldReader; -#[doc = "Field `CIC` reader - Compensation Interval Counter"] -pub type CicR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Time Compensation Register"] - #[inline(always)] - pub fn tcr(&self) -> TcrR { - TcrR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Compensation Interval Register"] - #[inline(always)] - pub fn cir(&self) -> CirR { - CirR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Time Compensation Value"] - #[inline(always)] - pub fn tcv(&self) -> TcvR { - TcvR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Compensation Interval Counter"] - #[inline(always)] - pub fn cic(&self) -> CicR { - CicR::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Time Compensation Register"] - #[inline(always)] - pub fn tcr(&mut self) -> TcrW { - TcrW::new(self, 0) - } - #[doc = "Bits 8:15 - Compensation Interval Register"] - #[inline(always)] - pub fn cir(&mut self) -> CirW { - CirW::new(self, 8) - } -} -#[doc = "RTC Time Compensation\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcrSpec; -impl crate::RegisterSpec for TcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] -impl crate::Readable for TcrSpec {} -#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] -impl crate::Writable for TcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TCR to value 0"] -impl crate::Resettable for TcrSpec {} diff --git a/mcxa276-pac/src/rtc0/tpr.rs b/mcxa276-pac/src/rtc0/tpr.rs deleted file mode 100644 index 3fec7f502..000000000 --- a/mcxa276-pac/src/rtc0/tpr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TPR` reader"] -pub type R = crate::R; -#[doc = "Register `TPR` writer"] -pub type W = crate::W; -#[doc = "Field `TPR` reader - Time Prescaler Register"] -pub type TprR = crate::FieldReader; -#[doc = "Field `TPR` writer - Time Prescaler Register"] -pub type TprW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Time Prescaler Register"] - #[inline(always)] - pub fn tpr(&self) -> TprR { - TprR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Time Prescaler Register"] - #[inline(always)] - pub fn tpr(&mut self) -> TprW { - TprW::new(self, 0) - } -} -#[doc = "RTC Time Prescaler\n\nYou can [`read`](crate::Reg::read) this register and get [`tpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TprSpec; -impl crate::RegisterSpec for TprSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tpr::R`](R) reader structure"] -impl crate::Readable for TprSpec {} -#[doc = "`write(|w| ..)` method takes [`tpr::W`](W) writer structure"] -impl crate::Writable for TprSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TPR to value 0"] -impl crate::Resettable for TprSpec {} diff --git a/mcxa276-pac/src/rtc0/tsr.rs b/mcxa276-pac/src/rtc0/tsr.rs deleted file mode 100644 index ca2ecf566..000000000 --- a/mcxa276-pac/src/rtc0/tsr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TSR` reader"] -pub type R = crate::R; -#[doc = "Register `TSR` writer"] -pub type W = crate::W; -#[doc = "Field `TSR` reader - Time Seconds Register"] -pub type TsrR = crate::FieldReader; -#[doc = "Field `TSR` writer - Time Seconds Register"] -pub type TsrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Time Seconds Register"] - #[inline(always)] - pub fn tsr(&self) -> TsrR { - TsrR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Time Seconds Register"] - #[inline(always)] - pub fn tsr(&mut self) -> TsrW { - TsrW::new(self, 0) - } -} -#[doc = "RTC Time Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TsrSpec; -impl crate::RegisterSpec for TsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tsr::R`](R) reader structure"] -impl crate::Readable for TsrSpec {} -#[doc = "`write(|w| ..)` method takes [`tsr::W`](W) writer structure"] -impl crate::Writable for TsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TSR to value 0"] -impl crate::Resettable for TsrSpec {} diff --git a/mcxa276-pac/src/sau.rs b/mcxa276-pac/src/sau.rs deleted file mode 100644 index aae9f7bb1..000000000 --- a/mcxa276-pac/src/sau.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0xd0], - ctrl: Ctrl, - type_: Type, - rnr: Rnr, - rbar: Rbar, - rlar: Rlar, - sfsr: Sfsr, - sfar: Sfar, -} -impl RegisterBlock { - #[doc = "0xd0 - Security Attribution Unit Control Register"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } - #[doc = "0xd4 - Security Attribution Unit Type Register"] - #[inline(always)] - pub const fn type_(&self) -> &Type { - &self.type_ - } - #[doc = "0xd8 - Security Attribution Unit Region Number Register"] - #[inline(always)] - pub const fn rnr(&self) -> &Rnr { - &self.rnr - } - #[doc = "0xdc - Security Attribution Unit Region Base Address Register"] - #[inline(always)] - pub const fn rbar(&self) -> &Rbar { - &self.rbar - } - #[doc = "0xe0 - Security Attribution Unit Region Limit Address Register"] - #[inline(always)] - pub const fn rlar(&self) -> &Rlar { - &self.rlar - } - #[doc = "0xe4 - Secure Fault Status Register"] - #[inline(always)] - pub const fn sfsr(&self) -> &Sfsr { - &self.sfsr - } - #[doc = "0xe8 - Secure Fault Address Register"] - #[inline(always)] - pub const fn sfar(&self) -> &Sfar { - &self.sfar - } -} -#[doc = "CTRL (rw) register accessor: Security Attribution Unit Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "Security Attribution Unit Control Register"] -pub mod ctrl; -#[doc = "TYPE (rw) register accessor: Security Attribution Unit Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`type_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`type_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@type_`] module"] -#[doc(alias = "TYPE")] -pub type Type = crate::Reg; -#[doc = "Security Attribution Unit Type Register"] -pub mod type_; -#[doc = "RNR (rw) register accessor: Security Attribution Unit Region Number Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rnr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnr`] module"] -#[doc(alias = "RNR")] -pub type Rnr = crate::Reg; -#[doc = "Security Attribution Unit Region Number Register"] -pub mod rnr; -#[doc = "RBAR (rw) register accessor: Security Attribution Unit Region Base Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rbar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rbar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbar`] module"] -#[doc(alias = "RBAR")] -pub type Rbar = crate::Reg; -#[doc = "Security Attribution Unit Region Base Address Register"] -pub mod rbar; -#[doc = "RLAR (rw) register accessor: Security Attribution Unit Region Limit Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rlar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rlar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rlar`] module"] -#[doc(alias = "RLAR")] -pub type Rlar = crate::Reg; -#[doc = "Security Attribution Unit Region Limit Address Register"] -pub mod rlar; -#[doc = "SFSR (rw) register accessor: Secure Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfsr`] module"] -#[doc(alias = "SFSR")] -pub type Sfsr = crate::Reg; -#[doc = "Secure Fault Status Register"] -pub mod sfsr; -#[doc = "SFAR (rw) register accessor: Secure Fault Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfar`] module"] -#[doc(alias = "SFAR")] -pub type Sfar = crate::Reg; -#[doc = "Secure Fault Address Register"] -pub mod sfar; diff --git a/mcxa276-pac/src/sau/ctrl.rs b/mcxa276-pac/src/sau/ctrl.rs deleted file mode 100644 index 1e08b8c60..000000000 --- a/mcxa276-pac/src/sau/ctrl.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Enable { - #[doc = "0: The SAU is disabled."] - Disabled = 0, - #[doc = "1: The SAU is enabled."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Enable) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENABLE` reader - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] -pub type EnableR = crate::BitReader; -impl EnableR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Enable { - match self.bits { - false => Enable::Disabled, - true => Enable::Enabled, - } - } - #[doc = "The SAU is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Enable::Disabled - } - #[doc = "The SAU is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Enable::Enabled - } -} -#[doc = "Field `ENABLE` writer - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] -pub type EnableW<'a, REG> = crate::BitWriter<'a, REG, Enable>; -impl<'a, REG> EnableW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SAU is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Enable::Disabled) - } - #[doc = "The SAU is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Enable::Enabled) - } -} -#[doc = "All Non-secure.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Allns { - #[doc = "0: Memory is marked as Secure and is not Non-secure callable."] - SecuredMemory = 0, - #[doc = "1: Memory is marked as Non-secure."] - NonSecuredMemory = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Allns) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ALLNS` reader - All Non-secure."] -pub type AllnsR = crate::BitReader; -impl AllnsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Allns { - match self.bits { - false => Allns::SecuredMemory, - true => Allns::NonSecuredMemory, - } - } - #[doc = "Memory is marked as Secure and is not Non-secure callable."] - #[inline(always)] - pub fn is_secured_memory(&self) -> bool { - *self == Allns::SecuredMemory - } - #[doc = "Memory is marked as Non-secure."] - #[inline(always)] - pub fn is_non_secured_memory(&self) -> bool { - *self == Allns::NonSecuredMemory - } -} -#[doc = "Field `ALLNS` writer - All Non-secure."] -pub type AllnsW<'a, REG> = crate::BitWriter<'a, REG, Allns>; -impl<'a, REG> AllnsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Memory is marked as Secure and is not Non-secure callable."] - #[inline(always)] - pub fn secured_memory(self) -> &'a mut crate::W { - self.variant(Allns::SecuredMemory) - } - #[doc = "Memory is marked as Non-secure."] - #[inline(always)] - pub fn non_secured_memory(self) -> &'a mut crate::W { - self.variant(Allns::NonSecuredMemory) - } -} -impl R { - #[doc = "Bit 0 - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] - #[inline(always)] - pub fn enable(&self) -> EnableR { - EnableR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - All Non-secure."] - #[inline(always)] - pub fn allns(&self) -> AllnsR { - AllnsR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."] - #[inline(always)] - pub fn enable(&mut self) -> EnableW { - EnableW::new(self, 0) - } - #[doc = "Bit 1 - All Non-secure."] - #[inline(always)] - pub fn allns(&mut self) -> AllnsW { - AllnsW::new(self, 1) - } -} -#[doc = "Security Attribution Unit Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/sau/rbar.rs b/mcxa276-pac/src/sau/rbar.rs deleted file mode 100644 index 271ec8df1..000000000 --- a/mcxa276-pac/src/sau/rbar.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RBAR` reader"] -pub type R = crate::R; -#[doc = "Register `RBAR` writer"] -pub type W = crate::W; -#[doc = "Field `BADDR` reader - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] -pub type BaddrR = crate::FieldReader; -#[doc = "Field `BADDR` writer - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] -pub type BaddrW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; -impl R { - #[doc = "Bits 5:31 - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] - #[inline(always)] - pub fn baddr(&self) -> BaddrR { - BaddrR::new((self.bits >> 5) & 0x07ff_ffff) - } -} -impl W { - #[doc = "Bits 5:31 - Base address. Holds bits\\[31:5\\] of the base address for the selected SAU region. Bits\\[4:0\\] of the base address are defined as 0x00."] - #[inline(always)] - pub fn baddr(&mut self) -> BaddrW { - BaddrW::new(self, 5) - } -} -#[doc = "Security Attribution Unit Region Base Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rbar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rbar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RbarSpec; -impl crate::RegisterSpec for RbarSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rbar::R`](R) reader structure"] -impl crate::Readable for RbarSpec {} -#[doc = "`write(|w| ..)` method takes [`rbar::W`](W) writer structure"] -impl crate::Writable for RbarSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RBAR to value 0"] -impl crate::Resettable for RbarSpec {} diff --git a/mcxa276-pac/src/sau/rlar.rs b/mcxa276-pac/src/sau/rlar.rs deleted file mode 100644 index ad851af2f..000000000 --- a/mcxa276-pac/src/sau/rlar.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `RLAR` reader"] -pub type R = crate::R; -#[doc = "Register `RLAR` writer"] -pub type W = crate::W; -#[doc = "Enable. SAU region enable.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Enable { - #[doc = "0: SAU region is enabled."] - Enabled = 0, - #[doc = "1: SAU region is disabled."] - Disabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Enable) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENABLE` reader - Enable. SAU region enable."] -pub type EnableR = crate::BitReader; -impl EnableR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Enable { - match self.bits { - false => Enable::Enabled, - true => Enable::Disabled, - } - } - #[doc = "SAU region is enabled."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Enable::Enabled - } - #[doc = "SAU region is disabled."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Enable::Disabled - } -} -#[doc = "Field `ENABLE` writer - Enable. SAU region enable."] -pub type EnableW<'a, REG> = crate::BitWriter<'a, REG, Enable>; -impl<'a, REG> EnableW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SAU region is enabled."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Enable::Enabled) - } - #[doc = "SAU region is disabled."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Enable::Disabled) - } -} -#[doc = "Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nsc { - #[doc = "0: Region is not Non-secure callable."] - NotNonSecureCallable = 0, - #[doc = "1: Region is Non-secure callable."] - NonSecureCallable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nsc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NSC` reader - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] -pub type NscR = crate::BitReader; -impl NscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nsc { - match self.bits { - false => Nsc::NotNonSecureCallable, - true => Nsc::NonSecureCallable, - } - } - #[doc = "Region is not Non-secure callable."] - #[inline(always)] - pub fn is_not_non_secure_callable(&self) -> bool { - *self == Nsc::NotNonSecureCallable - } - #[doc = "Region is Non-secure callable."] - #[inline(always)] - pub fn is_non_secure_callable(&self) -> bool { - *self == Nsc::NonSecureCallable - } -} -#[doc = "Field `NSC` writer - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] -pub type NscW<'a, REG> = crate::BitWriter<'a, REG, Nsc>; -impl<'a, REG> NscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Region is not Non-secure callable."] - #[inline(always)] - pub fn not_non_secure_callable(self) -> &'a mut crate::W { - self.variant(Nsc::NotNonSecureCallable) - } - #[doc = "Region is Non-secure callable."] - #[inline(always)] - pub fn non_secure_callable(self) -> &'a mut crate::W { - self.variant(Nsc::NonSecureCallable) - } -} -#[doc = "Field `LADDR` reader - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] -pub type LaddrR = crate::FieldReader; -#[doc = "Field `LADDR` writer - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] -pub type LaddrW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; -impl R { - #[doc = "Bit 0 - Enable. SAU region enable."] - #[inline(always)] - pub fn enable(&self) -> EnableR { - EnableR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] - #[inline(always)] - pub fn nsc(&self) -> NscR { - NscR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 5:31 - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] - #[inline(always)] - pub fn laddr(&self) -> LaddrR { - LaddrR::new((self.bits >> 5) & 0x07ff_ffff) - } -} -impl W { - #[doc = "Bit 0 - Enable. SAU region enable."] - #[inline(always)] - pub fn enable(&mut self) -> EnableW { - EnableW::new(self, 0) - } - #[doc = "Bit 1 - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region."] - #[inline(always)] - pub fn nsc(&mut self) -> NscW { - NscW::new(self, 1) - } - #[doc = "Bits 5:31 - Limit address. Holds bits\\[31:5\\] of the limit address for the selected SAU region. Bits\\[4:0\\] of the limit address are defined as 0x1F."] - #[inline(always)] - pub fn laddr(&mut self) -> LaddrW { - LaddrW::new(self, 5) - } -} -#[doc = "Security Attribution Unit Region Limit Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rlar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rlar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RlarSpec; -impl crate::RegisterSpec for RlarSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rlar::R`](R) reader structure"] -impl crate::Readable for RlarSpec {} -#[doc = "`write(|w| ..)` method takes [`rlar::W`](W) writer structure"] -impl crate::Writable for RlarSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RLAR to value 0"] -impl crate::Resettable for RlarSpec {} diff --git a/mcxa276-pac/src/sau/rnr.rs b/mcxa276-pac/src/sau/rnr.rs deleted file mode 100644 index 6e871ecd6..000000000 --- a/mcxa276-pac/src/sau/rnr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `RNR` reader"] -pub type R = crate::R; -#[doc = "Register `RNR` writer"] -pub type W = crate::W; -#[doc = "Field `REGION` reader - Region number."] -pub type RegionR = crate::FieldReader; -#[doc = "Field `REGION` writer - Region number."] -pub type RegionW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Region number."] - #[inline(always)] - pub fn region(&self) -> RegionR { - RegionR::new((self.bits & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Region number."] - #[inline(always)] - pub fn region(&mut self) -> RegionW { - RegionW::new(self, 0) - } -} -#[doc = "Security Attribution Unit Region Number Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rnr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RnrSpec; -impl crate::RegisterSpec for RnrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rnr::R`](R) reader structure"] -impl crate::Readable for RnrSpec {} -#[doc = "`write(|w| ..)` method takes [`rnr::W`](W) writer structure"] -impl crate::Writable for RnrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RNR to value 0"] -impl crate::Resettable for RnrSpec {} diff --git a/mcxa276-pac/src/sau/sfar.rs b/mcxa276-pac/src/sau/sfar.rs deleted file mode 100644 index 890a7af3c..000000000 --- a/mcxa276-pac/src/sau/sfar.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SFAR` reader"] -pub type R = crate::R; -#[doc = "Register `SFAR` writer"] -pub type W = crate::W; -#[doc = "Field `ADDRESS` reader - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] -pub type AddressR = crate::FieldReader; -#[doc = "Field `ADDRESS` writer - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] -pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] - #[inline(always)] - pub fn address(&self) -> AddressR { - AddressR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation."] - #[inline(always)] - pub fn address(&mut self) -> AddressW { - AddressW::new(self, 0) - } -} -#[doc = "Secure Fault Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SfarSpec; -impl crate::RegisterSpec for SfarSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sfar::R`](R) reader structure"] -impl crate::Readable for SfarSpec {} -#[doc = "`write(|w| ..)` method takes [`sfar::W`](W) writer structure"] -impl crate::Writable for SfarSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SFAR to value 0"] -impl crate::Resettable for SfarSpec {} diff --git a/mcxa276-pac/src/sau/sfsr.rs b/mcxa276-pac/src/sau/sfsr.rs deleted file mode 100644 index fa65cbc92..000000000 --- a/mcxa276-pac/src/sau/sfsr.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `SFSR` reader"] -pub type R = crate::R; -#[doc = "Register `SFSR` writer"] -pub type W = crate::W; -#[doc = "Invalid entry point.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Invep { - #[doc = "0: Error has not occurred."] - NoError = 0, - #[doc = "1: Error has occurred."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Invep) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INVEP` reader - Invalid entry point."] -pub type InvepR = crate::BitReader; -impl InvepR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Invep { - match self.bits { - false => Invep::NoError, - true => Invep::Error, - } - } - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Invep::NoError - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Invep::Error - } -} -#[doc = "Field `INVEP` writer - Invalid entry point."] -pub type InvepW<'a, REG> = crate::BitWriter<'a, REG, Invep>; -impl<'a, REG> InvepW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Invep::NoError) - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Invep::Error) - } -} -#[doc = "Invalid integrity signature flag.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Invis { - #[doc = "0: Error has not occurred."] - NoError = 0, - #[doc = "1: Error has occurred."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Invis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INVIS` reader - Invalid integrity signature flag."] -pub type InvisR = crate::BitReader; -impl InvisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Invis { - match self.bits { - false => Invis::NoError, - true => Invis::Error, - } - } - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Invis::NoError - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Invis::Error - } -} -#[doc = "Field `INVIS` writer - Invalid integrity signature flag."] -pub type InvisW<'a, REG> = crate::BitWriter<'a, REG, Invis>; -impl<'a, REG> InvisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Invis::NoError) - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Invis::Error) - } -} -#[doc = "Invalid exception return flag.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Inver { - #[doc = "0: Error has not occurred."] - NoError = 0, - #[doc = "1: Error has occurred."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Inver) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INVER` reader - Invalid exception return flag."] -pub type InverR = crate::BitReader; -impl InverR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Inver { - match self.bits { - false => Inver::NoError, - true => Inver::Error, - } - } - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Inver::NoError - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Inver::Error - } -} -#[doc = "Field `INVER` writer - Invalid exception return flag."] -pub type InverW<'a, REG> = crate::BitWriter<'a, REG, Inver>; -impl<'a, REG> InverW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Inver::NoError) - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Inver::Error) - } -} -#[doc = "Attribution unit violation flag.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Auviol { - #[doc = "0: Error has not occurred."] - NoError = 0, - #[doc = "1: Error has occurred."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Auviol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `AUVIOL` reader - Attribution unit violation flag."] -pub type AuviolR = crate::BitReader; -impl AuviolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Auviol { - match self.bits { - false => Auviol::NoError, - true => Auviol::Error, - } - } - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Auviol::NoError - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Auviol::Error - } -} -#[doc = "Field `AUVIOL` writer - Attribution unit violation flag."] -pub type AuviolW<'a, REG> = crate::BitWriter<'a, REG, Auviol>; -impl<'a, REG> AuviolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Auviol::NoError) - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Auviol::Error) - } -} -#[doc = "Invalid transition flag.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Invtran { - #[doc = "0: Error has not occurred."] - NoError = 0, - #[doc = "1: Error has occurred."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Invtran) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INVTRAN` reader - Invalid transition flag."] -pub type InvtranR = crate::BitReader; -impl InvtranR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Invtran { - match self.bits { - false => Invtran::NoError, - true => Invtran::Error, - } - } - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Invtran::NoError - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Invtran::Error - } -} -#[doc = "Field `INVTRAN` writer - Invalid transition flag."] -pub type InvtranW<'a, REG> = crate::BitWriter<'a, REG, Invtran>; -impl<'a, REG> InvtranW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Invtran::NoError) - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Invtran::Error) - } -} -#[doc = "Lazy state preservation error flag.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lsperr { - #[doc = "0: Error has not occurred."] - NoError = 0, - #[doc = "1: Error has occurred."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lsperr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LSPERR` reader - Lazy state preservation error flag."] -pub type LsperrR = crate::BitReader; -impl LsperrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lsperr { - match self.bits { - false => Lsperr::NoError, - true => Lsperr::Error, - } - } - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Lsperr::NoError - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Lsperr::Error - } -} -#[doc = "Field `LSPERR` writer - Lazy state preservation error flag."] -pub type LsperrW<'a, REG> = crate::BitWriter<'a, REG, Lsperr>; -impl<'a, REG> LsperrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error has not occurred."] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Lsperr::NoError) - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Lsperr::Error) - } -} -#[doc = "Secure fault address valid.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sfarvalid { - #[doc = "0: SFAR content not valid."] - NotValid = 0, - #[doc = "1: SFAR content valid."] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sfarvalid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SFARVALID` reader - Secure fault address valid."] -pub type SfarvalidR = crate::BitReader; -impl SfarvalidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sfarvalid { - match self.bits { - false => Sfarvalid::NotValid, - true => Sfarvalid::Valid, - } - } - #[doc = "SFAR content not valid."] - #[inline(always)] - pub fn is_not_valid(&self) -> bool { - *self == Sfarvalid::NotValid - } - #[doc = "SFAR content valid."] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Sfarvalid::Valid - } -} -#[doc = "Field `SFARVALID` writer - Secure fault address valid."] -pub type SfarvalidW<'a, REG> = crate::BitWriter<'a, REG, Sfarvalid>; -impl<'a, REG> SfarvalidW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SFAR content not valid."] - #[inline(always)] - pub fn not_valid(self) -> &'a mut crate::W { - self.variant(Sfarvalid::NotValid) - } - #[doc = "SFAR content valid."] - #[inline(always)] - pub fn valid(self) -> &'a mut crate::W { - self.variant(Sfarvalid::Valid) - } -} -#[doc = "Lazy state error flag.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lserr { - #[doc = "0: Error has not occurred"] - NoError = 0, - #[doc = "1: Error has occurred."] - Error = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lserr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LSERR` reader - Lazy state error flag."] -pub type LserrR = crate::BitReader; -impl LserrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lserr { - match self.bits { - false => Lserr::NoError, - true => Lserr::Error, - } - } - #[doc = "Error has not occurred"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Lserr::NoError - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Lserr::Error - } -} -#[doc = "Field `LSERR` writer - Lazy state error flag."] -pub type LserrW<'a, REG> = crate::BitWriter<'a, REG, Lserr>; -impl<'a, REG> LserrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error has not occurred"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Lserr::NoError) - } - #[doc = "Error has occurred."] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Lserr::Error) - } -} -impl R { - #[doc = "Bit 0 - Invalid entry point."] - #[inline(always)] - pub fn invep(&self) -> InvepR { - InvepR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Invalid integrity signature flag."] - #[inline(always)] - pub fn invis(&self) -> InvisR { - InvisR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Invalid exception return flag."] - #[inline(always)] - pub fn inver(&self) -> InverR { - InverR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Attribution unit violation flag."] - #[inline(always)] - pub fn auviol(&self) -> AuviolR { - AuviolR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Invalid transition flag."] - #[inline(always)] - pub fn invtran(&self) -> InvtranR { - InvtranR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Lazy state preservation error flag."] - #[inline(always)] - pub fn lsperr(&self) -> LsperrR { - LsperrR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Secure fault address valid."] - #[inline(always)] - pub fn sfarvalid(&self) -> SfarvalidR { - SfarvalidR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Lazy state error flag."] - #[inline(always)] - pub fn lserr(&self) -> LserrR { - LserrR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Invalid entry point."] - #[inline(always)] - pub fn invep(&mut self) -> InvepW { - InvepW::new(self, 0) - } - #[doc = "Bit 1 - Invalid integrity signature flag."] - #[inline(always)] - pub fn invis(&mut self) -> InvisW { - InvisW::new(self, 1) - } - #[doc = "Bit 2 - Invalid exception return flag."] - #[inline(always)] - pub fn inver(&mut self) -> InverW { - InverW::new(self, 2) - } - #[doc = "Bit 3 - Attribution unit violation flag."] - #[inline(always)] - pub fn auviol(&mut self) -> AuviolW { - AuviolW::new(self, 3) - } - #[doc = "Bit 4 - Invalid transition flag."] - #[inline(always)] - pub fn invtran(&mut self) -> InvtranW { - InvtranW::new(self, 4) - } - #[doc = "Bit 5 - Lazy state preservation error flag."] - #[inline(always)] - pub fn lsperr(&mut self) -> LsperrW { - LsperrW::new(self, 5) - } - #[doc = "Bit 6 - Secure fault address valid."] - #[inline(always)] - pub fn sfarvalid(&mut self) -> SfarvalidW { - SfarvalidW::new(self, 6) - } - #[doc = "Bit 7 - Lazy state error flag."] - #[inline(always)] - pub fn lserr(&mut self) -> LserrW { - LserrW::new(self, 7) - } -} -#[doc = "Secure Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SfsrSpec; -impl crate::RegisterSpec for SfsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sfsr::R`](R) reader structure"] -impl crate::Readable for SfsrSpec {} -#[doc = "`write(|w| ..)` method takes [`sfsr::W`](W) writer structure"] -impl crate::Writable for SfsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SFSR to value 0"] -impl crate::Resettable for SfsrSpec {} diff --git a/mcxa276-pac/src/sau/type_.rs b/mcxa276-pac/src/sau/type_.rs deleted file mode 100644 index b2d43fd12..000000000 --- a/mcxa276-pac/src/sau/type_.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TYPE` reader"] -pub type R = crate::R; -#[doc = "Register `TYPE` writer"] -pub type W = crate::W; -#[doc = "Field `SREGION` reader - SAU regions. The number of implemented SAU regions."] -pub type SregionR = crate::FieldReader; -#[doc = "Field `SREGION` writer - SAU regions. The number of implemented SAU regions."] -pub type SregionW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - SAU regions. The number of implemented SAU regions."] - #[inline(always)] - pub fn sregion(&self) -> SregionR { - SregionR::new((self.bits & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - SAU regions. The number of implemented SAU regions."] - #[inline(always)] - pub fn sregion(&mut self) -> SregionW { - SregionW::new(self, 0) - } -} -#[doc = "Security Attribution Unit Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`type_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`type_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TypeSpec; -impl crate::RegisterSpec for TypeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`type_::R`](R) reader structure"] -impl crate::Readable for TypeSpec {} -#[doc = "`write(|w| ..)` method takes [`type_::W`](W) writer structure"] -impl crate::Writable for TypeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TYPE to value 0"] -impl crate::Resettable for TypeSpec {} diff --git a/mcxa276-pac/src/scg0.rs b/mcxa276-pac/src/scg0.rs deleted file mode 100644 index 6a4d7ba37..000000000 --- a/mcxa276-pac/src/scg0.rs +++ /dev/null @@ -1,305 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - trim_lock: TrimLock, - _reserved3: [u8; 0x04], - csr: Csr, - rccr: Rccr, - _reserved5: [u8; 0xe8], - sosccsr: Sosccsr, - _reserved6: [u8; 0x04], - sosccfg: Sosccfg, - _reserved7: [u8; 0xf4], - sirccsr: Sirccsr, - _reserved8: [u8; 0x08], - sirctcfg: Sirctcfg, - sirctrim: Sirctrim, - _reserved10: [u8; 0x04], - sircstat: Sircstat, - _reserved11: [u8; 0xe4], - firccsr: Firccsr, - _reserved12: [u8; 0x04], - firccfg: Firccfg, - _reserved13: [u8; 0x04], - firctrim: Firctrim, - _reserved14: [u8; 0xec], - rosccsr: Rosccsr, - _reserved15: [u8; 0x01fc], - spllcsr: Spllcsr, - spllctrl: Spllctrl, - spllstat: Spllstat, - spllndiv: Spllndiv, - spllmdiv: Spllmdiv, - spllpdiv: Spllpdiv, - splllock_cnfg: SplllockCnfg, - _reserved22: [u8; 0x04], - spllsscgstat: Spllsscgstat, - spllsscg0: Spllsscg0, - spllsscg1: Spllsscg1, - _reserved25: [u8; 0x01d4], - ldocsr: Ldocsr, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID Register"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter Register"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x08 - Trim Lock register"] - #[inline(always)] - pub const fn trim_lock(&self) -> &TrimLock { - &self.trim_lock - } - #[doc = "0x10 - Clock Status Register"] - #[inline(always)] - pub const fn csr(&self) -> &Csr { - &self.csr - } - #[doc = "0x14 - Run Clock Control Register"] - #[inline(always)] - pub const fn rccr(&self) -> &Rccr { - &self.rccr - } - #[doc = "0x100 - SOSC Control Status Register"] - #[inline(always)] - pub const fn sosccsr(&self) -> &Sosccsr { - &self.sosccsr - } - #[doc = "0x108 - SOSC Configuration Register"] - #[inline(always)] - pub const fn sosccfg(&self) -> &Sosccfg { - &self.sosccfg - } - #[doc = "0x200 - SIRC Control Status Register"] - #[inline(always)] - pub const fn sirccsr(&self) -> &Sirccsr { - &self.sirccsr - } - #[doc = "0x20c - SIRC Trim Configuration Register"] - #[inline(always)] - pub const fn sirctcfg(&self) -> &Sirctcfg { - &self.sirctcfg - } - #[doc = "0x210 - SIRC Trim Register"] - #[inline(always)] - pub const fn sirctrim(&self) -> &Sirctrim { - &self.sirctrim - } - #[doc = "0x218 - SIRC Auto-trimming Status Register"] - #[inline(always)] - pub const fn sircstat(&self) -> &Sircstat { - &self.sircstat - } - #[doc = "0x300 - FIRC Control Status Register"] - #[inline(always)] - pub const fn firccsr(&self) -> &Firccsr { - &self.firccsr - } - #[doc = "0x308 - FIRC Configuration Register"] - #[inline(always)] - pub const fn firccfg(&self) -> &Firccfg { - &self.firccfg - } - #[doc = "0x310 - FIRC Trim Register"] - #[inline(always)] - pub const fn firctrim(&self) -> &Firctrim { - &self.firctrim - } - #[doc = "0x400 - ROSC Control Status Register"] - #[inline(always)] - pub const fn rosccsr(&self) -> &Rosccsr { - &self.rosccsr - } - #[doc = "0x600 - SPLL Control Status Register"] - #[inline(always)] - pub const fn spllcsr(&self) -> &Spllcsr { - &self.spllcsr - } - #[doc = "0x604 - SPLL Control Register"] - #[inline(always)] - pub const fn spllctrl(&self) -> &Spllctrl { - &self.spllctrl - } - #[doc = "0x608 - SPLL Status Register"] - #[inline(always)] - pub const fn spllstat(&self) -> &Spllstat { - &self.spllstat - } - #[doc = "0x60c - SPLL N Divider Register"] - #[inline(always)] - pub const fn spllndiv(&self) -> &Spllndiv { - &self.spllndiv - } - #[doc = "0x610 - SPLL M Divider Register"] - #[inline(always)] - pub const fn spllmdiv(&self) -> &Spllmdiv { - &self.spllmdiv - } - #[doc = "0x614 - SPLL P Divider Register"] - #[inline(always)] - pub const fn spllpdiv(&self) -> &Spllpdiv { - &self.spllpdiv - } - #[doc = "0x618 - SPLL LOCK Configuration Register"] - #[inline(always)] - pub const fn splllock_cnfg(&self) -> &SplllockCnfg { - &self.splllock_cnfg - } - #[doc = "0x620 - SPLL SSCG Status Register"] - #[inline(always)] - pub const fn spllsscgstat(&self) -> &Spllsscgstat { - &self.spllsscgstat - } - #[doc = "0x624 - SPLL Spread Spectrum Control 0 Register"] - #[inline(always)] - pub const fn spllsscg0(&self) -> &Spllsscg0 { - &self.spllsscg0 - } - #[doc = "0x628 - SPLL Spread Spectrum Control 1 Register"] - #[inline(always)] - pub const fn spllsscg1(&self) -> &Spllsscg1 { - &self.spllsscg1 - } - #[doc = "0x800 - LDO Control and Status Register"] - #[inline(always)] - pub const fn ldocsr(&self) -> &Ldocsr { - &self.ldocsr - } -} -#[doc = "VERID (r) register accessor: Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID Register"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter Register"] -pub mod param; -#[doc = "TRIM_LOCK (rw) register accessor: Trim Lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`trim_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trim_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trim_lock`] module"] -#[doc(alias = "TRIM_LOCK")] -pub type TrimLock = crate::Reg; -#[doc = "Trim Lock register"] -pub mod trim_lock; -#[doc = "CSR (r) register accessor: Clock Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`] module"] -#[doc(alias = "CSR")] -pub type Csr = crate::Reg; -#[doc = "Clock Status Register"] -pub mod csr; -#[doc = "RCCR (rw) register accessor: Run Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rccr`] module"] -#[doc(alias = "RCCR")] -pub type Rccr = crate::Reg; -#[doc = "Run Clock Control Register"] -pub mod rccr; -#[doc = "SOSCCSR (rw) register accessor: SOSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sosccsr`] module"] -#[doc(alias = "SOSCCSR")] -pub type Sosccsr = crate::Reg; -#[doc = "SOSC Control Status Register"] -pub mod sosccsr; -#[doc = "SOSCCFG (rw) register accessor: SOSC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sosccfg`] module"] -#[doc(alias = "SOSCCFG")] -pub type Sosccfg = crate::Reg; -#[doc = "SOSC Configuration Register"] -pub mod sosccfg; -#[doc = "SIRCCSR (rw) register accessor: SIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sirccsr`] module"] -#[doc(alias = "SIRCCSR")] -pub type Sirccsr = crate::Reg; -#[doc = "SIRC Control Status Register"] -pub mod sirccsr; -#[doc = "SIRCTCFG (rw) register accessor: SIRC Trim Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sirctcfg`] module"] -#[doc(alias = "SIRCTCFG")] -pub type Sirctcfg = crate::Reg; -#[doc = "SIRC Trim Configuration Register"] -pub mod sirctcfg; -#[doc = "SIRCTRIM (rw) register accessor: SIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sirctrim`] module"] -#[doc(alias = "SIRCTRIM")] -pub type Sirctrim = crate::Reg; -#[doc = "SIRC Trim Register"] -pub mod sirctrim; -#[doc = "SIRCSTAT (rw) register accessor: SIRC Auto-trimming Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sircstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sircstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sircstat`] module"] -#[doc(alias = "SIRCSTAT")] -pub type Sircstat = crate::Reg; -#[doc = "SIRC Auto-trimming Status Register"] -pub mod sircstat; -#[doc = "FIRCCSR (rw) register accessor: FIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@firccsr`] module"] -#[doc(alias = "FIRCCSR")] -pub type Firccsr = crate::Reg; -#[doc = "FIRC Control Status Register"] -pub mod firccsr; -#[doc = "FIRCCFG (rw) register accessor: FIRC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@firccfg`] module"] -#[doc(alias = "FIRCCFG")] -pub type Firccfg = crate::Reg; -#[doc = "FIRC Configuration Register"] -pub mod firccfg; -#[doc = "FIRCTRIM (rw) register accessor: FIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firctrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firctrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@firctrim`] module"] -#[doc(alias = "FIRCTRIM")] -pub type Firctrim = crate::Reg; -#[doc = "FIRC Trim Register"] -pub mod firctrim; -#[doc = "ROSCCSR (rw) register accessor: ROSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rosccsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosccsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rosccsr`] module"] -#[doc(alias = "ROSCCSR")] -pub type Rosccsr = crate::Reg; -#[doc = "ROSC Control Status Register"] -pub mod rosccsr; -#[doc = "SPLLCSR (rw) register accessor: SPLL Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllcsr`] module"] -#[doc(alias = "SPLLCSR")] -pub type Spllcsr = crate::Reg; -#[doc = "SPLL Control Status Register"] -pub mod spllcsr; -#[doc = "SPLLCTRL (rw) register accessor: SPLL Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllctrl`] module"] -#[doc(alias = "SPLLCTRL")] -pub type Spllctrl = crate::Reg; -#[doc = "SPLL Control Register"] -pub mod spllctrl; -#[doc = "SPLLSTAT (r) register accessor: SPLL Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllstat`] module"] -#[doc(alias = "SPLLSTAT")] -pub type Spllstat = crate::Reg; -#[doc = "SPLL Status Register"] -pub mod spllstat; -#[doc = "SPLLNDIV (rw) register accessor: SPLL N Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllndiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllndiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllndiv`] module"] -#[doc(alias = "SPLLNDIV")] -pub type Spllndiv = crate::Reg; -#[doc = "SPLL N Divider Register"] -pub mod spllndiv; -#[doc = "SPLLMDIV (rw) register accessor: SPLL M Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllmdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllmdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllmdiv`] module"] -#[doc(alias = "SPLLMDIV")] -pub type Spllmdiv = crate::Reg; -#[doc = "SPLL M Divider Register"] -pub mod spllmdiv; -#[doc = "SPLLPDIV (rw) register accessor: SPLL P Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllpdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllpdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllpdiv`] module"] -#[doc(alias = "SPLLPDIV")] -pub type Spllpdiv = crate::Reg; -#[doc = "SPLL P Divider Register"] -pub mod spllpdiv; -#[doc = "SPLLLOCK_CNFG (rw) register accessor: SPLL LOCK Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`splllock_cnfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`splllock_cnfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@splllock_cnfg`] module"] -#[doc(alias = "SPLLLOCK_CNFG")] -pub type SplllockCnfg = crate::Reg; -#[doc = "SPLL LOCK Configuration Register"] -pub mod splllock_cnfg; -#[doc = "SPLLSSCGSTAT (r) register accessor: SPLL SSCG Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscgstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllsscgstat`] module"] -#[doc(alias = "SPLLSSCGSTAT")] -pub type Spllsscgstat = crate::Reg; -#[doc = "SPLL SSCG Status Register"] -pub mod spllsscgstat; -#[doc = "SPLLSSCG0 (rw) register accessor: SPLL Spread Spectrum Control 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllsscg0`] module"] -#[doc(alias = "SPLLSSCG0")] -pub type Spllsscg0 = crate::Reg; -#[doc = "SPLL Spread Spectrum Control 0 Register"] -pub mod spllsscg0; -#[doc = "SPLLSSCG1 (rw) register accessor: SPLL Spread Spectrum Control 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spllsscg1`] module"] -#[doc(alias = "SPLLSSCG1")] -pub type Spllsscg1 = crate::Reg; -#[doc = "SPLL Spread Spectrum Control 1 Register"] -pub mod spllsscg1; -#[doc = "LDOCSR (rw) register accessor: LDO Control and Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ldocsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ldocsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ldocsr`] module"] -#[doc(alias = "LDOCSR")] -pub type Ldocsr = crate::Reg; -#[doc = "LDO Control and Status Register"] -pub mod ldocsr; diff --git a/mcxa276-pac/src/scg0/csr.rs b/mcxa276-pac/src/scg0/csr.rs deleted file mode 100644 index 5bf2179c0..000000000 --- a/mcxa276-pac/src/scg0/csr.rs +++ /dev/null @@ -1,86 +0,0 @@ -#[doc = "Register `CSR` reader"] -pub type R = crate::R; -#[doc = "System Clock Source\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Scs { - #[doc = "1: SOSC"] - Sosc = 1, - #[doc = "2: SIRC"] - Sirc = 2, - #[doc = "3: FIRC"] - Firc = 3, - #[doc = "4: ROSC"] - Rosc = 4, - #[doc = "6: SPLL"] - Spll = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Scs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Scs { - type Ux = u8; -} -impl crate::IsEnum for Scs {} -#[doc = "Field `SCS` reader - System Clock Source"] -pub type ScsR = crate::FieldReader; -impl ScsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Scs::Sosc), - 2 => Some(Scs::Sirc), - 3 => Some(Scs::Firc), - 4 => Some(Scs::Rosc), - 6 => Some(Scs::Spll), - _ => None, - } - } - #[doc = "SOSC"] - #[inline(always)] - pub fn is_sosc(&self) -> bool { - *self == Scs::Sosc - } - #[doc = "SIRC"] - #[inline(always)] - pub fn is_sirc(&self) -> bool { - *self == Scs::Sirc - } - #[doc = "FIRC"] - #[inline(always)] - pub fn is_firc(&self) -> bool { - *self == Scs::Firc - } - #[doc = "ROSC"] - #[inline(always)] - pub fn is_rosc(&self) -> bool { - *self == Scs::Rosc - } - #[doc = "SPLL"] - #[inline(always)] - pub fn is_spll(&self) -> bool { - *self == Scs::Spll - } -} -impl R { - #[doc = "Bits 24:26 - System Clock Source"] - #[inline(always)] - pub fn scs(&self) -> ScsR { - ScsR::new(((self.bits >> 24) & 7) as u8) - } -} -#[doc = "Clock Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`csr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CsrSpec; -impl crate::RegisterSpec for CsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`csr::R`](R) reader structure"] -impl crate::Readable for CsrSpec {} -#[doc = "`reset()` method sets CSR to value 0x0300_0000"] -impl crate::Resettable for CsrSpec { - const RESET_VALUE: u32 = 0x0300_0000; -} diff --git a/mcxa276-pac/src/scg0/firccfg.rs b/mcxa276-pac/src/scg0/firccfg.rs deleted file mode 100644 index c476bcdaf..000000000 --- a/mcxa276-pac/src/scg0/firccfg.rs +++ /dev/null @@ -1,119 +0,0 @@ -#[doc = "Register `FIRCCFG` reader"] -pub type R = crate::R; -#[doc = "Register `FIRCCFG` writer"] -pub type W = crate::W; -#[doc = "Frequency select\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum FreqSel { - #[doc = "1: 45 MHz FIRC clock selected, divided from 180 MHz"] - Firc48mhz192s = 1, - #[doc = "3: 60 MHz FIRC clock selected"] - Firc64mhz = 3, - #[doc = "5: 90 MHz FIRC clock selected"] - Firc96mhz = 5, - #[doc = "7: 180 MHz FIRC clock selected"] - Firc192mhz = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: FreqSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for FreqSel { - type Ux = u8; -} -impl crate::IsEnum for FreqSel {} -#[doc = "Field `FREQ_SEL` reader - Frequency select"] -pub type FreqSelR = crate::FieldReader; -impl FreqSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(FreqSel::Firc48mhz192s), - 3 => Some(FreqSel::Firc64mhz), - 5 => Some(FreqSel::Firc96mhz), - 7 => Some(FreqSel::Firc192mhz), - _ => None, - } - } - #[doc = "45 MHz FIRC clock selected, divided from 180 MHz"] - #[inline(always)] - pub fn is_firc_48mhz_192s(&self) -> bool { - *self == FreqSel::Firc48mhz192s - } - #[doc = "60 MHz FIRC clock selected"] - #[inline(always)] - pub fn is_firc_64mhz(&self) -> bool { - *self == FreqSel::Firc64mhz - } - #[doc = "90 MHz FIRC clock selected"] - #[inline(always)] - pub fn is_firc_96mhz(&self) -> bool { - *self == FreqSel::Firc96mhz - } - #[doc = "180 MHz FIRC clock selected"] - #[inline(always)] - pub fn is_firc_192mhz(&self) -> bool { - *self == FreqSel::Firc192mhz - } -} -#[doc = "Field `FREQ_SEL` writer - Frequency select"] -pub type FreqSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, FreqSel>; -impl<'a, REG> FreqSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "45 MHz FIRC clock selected, divided from 180 MHz"] - #[inline(always)] - pub fn firc_48mhz_192s(self) -> &'a mut crate::W { - self.variant(FreqSel::Firc48mhz192s) - } - #[doc = "60 MHz FIRC clock selected"] - #[inline(always)] - pub fn firc_64mhz(self) -> &'a mut crate::W { - self.variant(FreqSel::Firc64mhz) - } - #[doc = "90 MHz FIRC clock selected"] - #[inline(always)] - pub fn firc_96mhz(self) -> &'a mut crate::W { - self.variant(FreqSel::Firc96mhz) - } - #[doc = "180 MHz FIRC clock selected"] - #[inline(always)] - pub fn firc_192mhz(self) -> &'a mut crate::W { - self.variant(FreqSel::Firc192mhz) - } -} -impl R { - #[doc = "Bits 1:3 - Frequency select"] - #[inline(always)] - pub fn freq_sel(&self) -> FreqSelR { - FreqSelR::new(((self.bits >> 1) & 7) as u8) - } -} -impl W { - #[doc = "Bits 1:3 - Frequency select"] - #[inline(always)] - pub fn freq_sel(&mut self) -> FreqSelW { - FreqSelW::new(self, 1) - } -} -#[doc = "FIRC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FirccfgSpec; -impl crate::RegisterSpec for FirccfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`firccfg::R`](R) reader structure"] -impl crate::Readable for FirccfgSpec {} -#[doc = "`write(|w| ..)` method takes [`firccfg::W`](W) writer structure"] -impl crate::Writable for FirccfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FIRCCFG to value 0x03"] -impl crate::Resettable for FirccfgSpec { - const RESET_VALUE: u32 = 0x03; -} diff --git a/mcxa276-pac/src/scg0/firccsr.rs b/mcxa276-pac/src/scg0/firccsr.rs deleted file mode 100644 index ec27bf643..000000000 --- a/mcxa276-pac/src/scg0/firccsr.rs +++ /dev/null @@ -1,651 +0,0 @@ -#[doc = "Register `FIRCCSR` reader"] -pub type R = crate::R; -#[doc = "Register `FIRCCSR` writer"] -pub type W = crate::W; -#[doc = "FIRC Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fircen { - #[doc = "0: FIRC is disabled"] - Disabled = 0, - #[doc = "1: FIRC is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fircen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCEN` reader - FIRC Enable"] -pub type FircenR = crate::BitReader; -impl FircenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fircen { - match self.bits { - false => Fircen::Disabled, - true => Fircen::Enabled, - } - } - #[doc = "FIRC is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Fircen::Disabled - } - #[doc = "FIRC is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Fircen::Enabled - } -} -#[doc = "Field `FIRCEN` writer - FIRC Enable"] -pub type FircenW<'a, REG> = crate::BitWriter<'a, REG, Fircen>; -impl<'a, REG> FircenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FIRC is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Fircen::Disabled) - } - #[doc = "FIRC is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Fircen::Enabled) - } -} -#[doc = "FIRC Stop Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fircsten { - #[doc = "0: FIRC is disabled in Deep Sleep mode"] - DisabledInStopModes = 0, - #[doc = "1: FIRC is enabled in Deep Sleep mode"] - EnabledInStopModes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fircsten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCSTEN` reader - FIRC Stop Enable"] -pub type FircstenR = crate::BitReader; -impl FircstenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fircsten { - match self.bits { - false => Fircsten::DisabledInStopModes, - true => Fircsten::EnabledInStopModes, - } - } - #[doc = "FIRC is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn is_disabled_in_stop_modes(&self) -> bool { - *self == Fircsten::DisabledInStopModes - } - #[doc = "FIRC is enabled in Deep Sleep mode"] - #[inline(always)] - pub fn is_enabled_in_stop_modes(&self) -> bool { - *self == Fircsten::EnabledInStopModes - } -} -#[doc = "Field `FIRCSTEN` writer - FIRC Stop Enable"] -pub type FircstenW<'a, REG> = crate::BitWriter<'a, REG, Fircsten>; -impl<'a, REG> FircstenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FIRC is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn disabled_in_stop_modes(self) -> &'a mut crate::W { - self.variant(Fircsten::DisabledInStopModes) - } - #[doc = "FIRC is enabled in Deep Sleep mode"] - #[inline(always)] - pub fn enabled_in_stop_modes(self) -> &'a mut crate::W { - self.variant(Fircsten::EnabledInStopModes) - } -} -#[doc = "FIRC 45 MHz Clock to peripherals Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FircSclkPeriphEn { - #[doc = "0: FIRC 45 MHz to peripherals is disabled"] - Disabled = 0, - #[doc = "1: FIRC 45 MHz to peripherals is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FircSclkPeriphEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRC_SCLK_PERIPH_EN` reader - FIRC 45 MHz Clock to peripherals Enable"] -pub type FircSclkPeriphEnR = crate::BitReader; -impl FircSclkPeriphEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FircSclkPeriphEn { - match self.bits { - false => FircSclkPeriphEn::Disabled, - true => FircSclkPeriphEn::Enabled, - } - } - #[doc = "FIRC 45 MHz to peripherals is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == FircSclkPeriphEn::Disabled - } - #[doc = "FIRC 45 MHz to peripherals is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == FircSclkPeriphEn::Enabled - } -} -#[doc = "Field `FIRC_SCLK_PERIPH_EN` writer - FIRC 45 MHz Clock to peripherals Enable"] -pub type FircSclkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, FircSclkPeriphEn>; -impl<'a, REG> FircSclkPeriphEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FIRC 45 MHz to peripherals is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(FircSclkPeriphEn::Disabled) - } - #[doc = "FIRC 45 MHz to peripherals is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(FircSclkPeriphEn::Enabled) - } -} -#[doc = "FRO_HF Clock to peripherals Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FircFclkPeriphEn { - #[doc = "0: FRO_HF to peripherals is disabled"] - Disabled = 0, - #[doc = "1: FRO_HF to peripherals is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FircFclkPeriphEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRC_FCLK_PERIPH_EN` reader - FRO_HF Clock to peripherals Enable"] -pub type FircFclkPeriphEnR = crate::BitReader; -impl FircFclkPeriphEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FircFclkPeriphEn { - match self.bits { - false => FircFclkPeriphEn::Disabled, - true => FircFclkPeriphEn::Enabled, - } - } - #[doc = "FRO_HF to peripherals is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == FircFclkPeriphEn::Disabled - } - #[doc = "FRO_HF to peripherals is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == FircFclkPeriphEn::Enabled - } -} -#[doc = "Field `FIRC_FCLK_PERIPH_EN` writer - FRO_HF Clock to peripherals Enable"] -pub type FircFclkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, FircFclkPeriphEn>; -impl<'a, REG> FircFclkPeriphEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FRO_HF to peripherals is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(FircFclkPeriphEn::Disabled) - } - #[doc = "FRO_HF to peripherals is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(FircFclkPeriphEn::Enabled) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Control Status Register can be written"] - WriteEnabled = 0, - #[doc = "1: Control Status Register cannot be written"] - WriteDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::WriteEnabled, - true => Lk::WriteDisabled, - } - } - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn is_write_enabled(&self) -> bool { - *self == Lk::WriteEnabled - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn is_write_disabled(&self) -> bool { - *self == Lk::WriteDisabled - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn write_enabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteEnabled) - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn write_disabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteDisabled) - } -} -#[doc = "FIRC Valid status\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fircvld { - #[doc = "0: FIRC is not enabled or clock is not valid."] - NotEnabledOrNotValid = 0, - #[doc = "1: FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog."] - EnabledAndValid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fircvld) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCVLD` reader - FIRC Valid status"] -pub type FircvldR = crate::BitReader; -impl FircvldR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fircvld { - match self.bits { - false => Fircvld::NotEnabledOrNotValid, - true => Fircvld::EnabledAndValid, - } - } - #[doc = "FIRC is not enabled or clock is not valid."] - #[inline(always)] - pub fn is_not_enabled_or_not_valid(&self) -> bool { - *self == Fircvld::NotEnabledOrNotValid - } - #[doc = "FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog."] - #[inline(always)] - pub fn is_enabled_and_valid(&self) -> bool { - *self == Fircvld::EnabledAndValid - } -} -#[doc = "FIRC Selected\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fircsel { - #[doc = "0: FIRC is not the system clock source"] - NotFirc = 0, - #[doc = "1: FIRC is the system clock source"] - Firc = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fircsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCSEL` reader - FIRC Selected"] -pub type FircselR = crate::BitReader; -impl FircselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fircsel { - match self.bits { - false => Fircsel::NotFirc, - true => Fircsel::Firc, - } - } - #[doc = "FIRC is not the system clock source"] - #[inline(always)] - pub fn is_not_firc(&self) -> bool { - *self == Fircsel::NotFirc - } - #[doc = "FIRC is the system clock source"] - #[inline(always)] - pub fn is_firc(&self) -> bool { - *self == Fircsel::Firc - } -} -#[doc = "FIRC Clock Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fircerr { - #[doc = "0: Error not detected with the FIRC trimming"] - ErrorNotDetected = 0, - #[doc = "1: Error detected with the FIRC trimming"] - ErrorDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fircerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCERR` reader - FIRC Clock Error"] -pub type FircerrR = crate::BitReader; -impl FircerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fircerr { - match self.bits { - false => Fircerr::ErrorNotDetected, - true => Fircerr::ErrorDetected, - } - } - #[doc = "Error not detected with the FIRC trimming"] - #[inline(always)] - pub fn is_error_not_detected(&self) -> bool { - *self == Fircerr::ErrorNotDetected - } - #[doc = "Error detected with the FIRC trimming"] - #[inline(always)] - pub fn is_error_detected(&self) -> bool { - *self == Fircerr::ErrorDetected - } -} -#[doc = "Field `FIRCERR` writer - FIRC Clock Error"] -pub type FircerrW<'a, REG> = crate::BitWriter1C<'a, REG, Fircerr>; -impl<'a, REG> FircerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error not detected with the FIRC trimming"] - #[inline(always)] - pub fn error_not_detected(self) -> &'a mut crate::W { - self.variant(Fircerr::ErrorNotDetected) - } - #[doc = "Error detected with the FIRC trimming"] - #[inline(always)] - pub fn error_detected(self) -> &'a mut crate::W { - self.variant(Fircerr::ErrorDetected) - } -} -#[doc = "FIRC Clock Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FircerrIe { - #[doc = "0: FIRCERR interrupt is not enabled"] - ErrorNotDetected = 0, - #[doc = "1: FIRCERR interrupt is enabled"] - ErrorDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FircerrIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCERR_IE` reader - FIRC Clock Error Interrupt Enable"] -pub type FircerrIeR = crate::BitReader; -impl FircerrIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FircerrIe { - match self.bits { - false => FircerrIe::ErrorNotDetected, - true => FircerrIe::ErrorDetected, - } - } - #[doc = "FIRCERR interrupt is not enabled"] - #[inline(always)] - pub fn is_error_not_detected(&self) -> bool { - *self == FircerrIe::ErrorNotDetected - } - #[doc = "FIRCERR interrupt is enabled"] - #[inline(always)] - pub fn is_error_detected(&self) -> bool { - *self == FircerrIe::ErrorDetected - } -} -#[doc = "Field `FIRCERR_IE` writer - FIRC Clock Error Interrupt Enable"] -pub type FircerrIeW<'a, REG> = crate::BitWriter<'a, REG, FircerrIe>; -impl<'a, REG> FircerrIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FIRCERR interrupt is not enabled"] - #[inline(always)] - pub fn error_not_detected(self) -> &'a mut crate::W { - self.variant(FircerrIe::ErrorNotDetected) - } - #[doc = "FIRCERR interrupt is enabled"] - #[inline(always)] - pub fn error_detected(self) -> &'a mut crate::W { - self.variant(FircerrIe::ErrorDetected) - } -} -#[doc = "FIRC Accurate Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FircaccIe { - #[doc = "0: FIRCACC interrupt is not enabled"] - Fircaccnot = 0, - #[doc = "1: FIRCACC interrupt is enabled"] - Fircaccyes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FircaccIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCACC_IE` reader - FIRC Accurate Interrupt Enable"] -pub type FircaccIeR = crate::BitReader; -impl FircaccIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FircaccIe { - match self.bits { - false => FircaccIe::Fircaccnot, - true => FircaccIe::Fircaccyes, - } - } - #[doc = "FIRCACC interrupt is not enabled"] - #[inline(always)] - pub fn is_fircaccnot(&self) -> bool { - *self == FircaccIe::Fircaccnot - } - #[doc = "FIRCACC interrupt is enabled"] - #[inline(always)] - pub fn is_fircaccyes(&self) -> bool { - *self == FircaccIe::Fircaccyes - } -} -#[doc = "Field `FIRCACC_IE` writer - FIRC Accurate Interrupt Enable"] -pub type FircaccIeW<'a, REG> = crate::BitWriter<'a, REG, FircaccIe>; -impl<'a, REG> FircaccIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FIRCACC interrupt is not enabled"] - #[inline(always)] - pub fn fircaccnot(self) -> &'a mut crate::W { - self.variant(FircaccIe::Fircaccnot) - } - #[doc = "FIRCACC interrupt is enabled"] - #[inline(always)] - pub fn fircaccyes(self) -> &'a mut crate::W { - self.variant(FircaccIe::Fircaccyes) - } -} -#[doc = "FIRC Frequency Accurate\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fircacc { - #[doc = "0: FIRC is not enabled or clock is not accurate."] - NotEnabledOrNotValid = 0, - #[doc = "1: FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock."] - EnabledAndValid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fircacc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCACC` reader - FIRC Frequency Accurate"] -pub type FircaccR = crate::BitReader; -impl FircaccR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fircacc { - match self.bits { - false => Fircacc::NotEnabledOrNotValid, - true => Fircacc::EnabledAndValid, - } - } - #[doc = "FIRC is not enabled or clock is not accurate."] - #[inline(always)] - pub fn is_not_enabled_or_not_valid(&self) -> bool { - *self == Fircacc::NotEnabledOrNotValid - } - #[doc = "FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock."] - #[inline(always)] - pub fn is_enabled_and_valid(&self) -> bool { - *self == Fircacc::EnabledAndValid - } -} -impl R { - #[doc = "Bit 0 - FIRC Enable"] - #[inline(always)] - pub fn fircen(&self) -> FircenR { - FircenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - FIRC Stop Enable"] - #[inline(always)] - pub fn fircsten(&self) -> FircstenR { - FircstenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 4 - FIRC 45 MHz Clock to peripherals Enable"] - #[inline(always)] - pub fn firc_sclk_periph_en(&self) -> FircSclkPeriphEnR { - FircSclkPeriphEnR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - FRO_HF Clock to peripherals Enable"] - #[inline(always)] - pub fn firc_fclk_periph_en(&self) -> FircFclkPeriphEnR { - FircFclkPeriphEnR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - FIRC Valid status"] - #[inline(always)] - pub fn fircvld(&self) -> FircvldR { - FircvldR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - FIRC Selected"] - #[inline(always)] - pub fn fircsel(&self) -> FircselR { - FircselR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - FIRC Clock Error"] - #[inline(always)] - pub fn fircerr(&self) -> FircerrR { - FircerrR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - FIRC Clock Error Interrupt Enable"] - #[inline(always)] - pub fn fircerr_ie(&self) -> FircerrIeR { - FircerrIeR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 30 - FIRC Accurate Interrupt Enable"] - #[inline(always)] - pub fn fircacc_ie(&self) -> FircaccIeR { - FircaccIeR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - FIRC Frequency Accurate"] - #[inline(always)] - pub fn fircacc(&self) -> FircaccR { - FircaccR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FIRC Enable"] - #[inline(always)] - pub fn fircen(&mut self) -> FircenW { - FircenW::new(self, 0) - } - #[doc = "Bit 1 - FIRC Stop Enable"] - #[inline(always)] - pub fn fircsten(&mut self) -> FircstenW { - FircstenW::new(self, 1) - } - #[doc = "Bit 4 - FIRC 45 MHz Clock to peripherals Enable"] - #[inline(always)] - pub fn firc_sclk_periph_en(&mut self) -> FircSclkPeriphEnW { - FircSclkPeriphEnW::new(self, 4) - } - #[doc = "Bit 5 - FRO_HF Clock to peripherals Enable"] - #[inline(always)] - pub fn firc_fclk_periph_en(&mut self) -> FircFclkPeriphEnW { - FircFclkPeriphEnW::new(self, 5) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 23) - } - #[doc = "Bit 26 - FIRC Clock Error"] - #[inline(always)] - pub fn fircerr(&mut self) -> FircerrW { - FircerrW::new(self, 26) - } - #[doc = "Bit 27 - FIRC Clock Error Interrupt Enable"] - #[inline(always)] - pub fn fircerr_ie(&mut self) -> FircerrIeW { - FircerrIeW::new(self, 27) - } - #[doc = "Bit 30 - FIRC Accurate Interrupt Enable"] - #[inline(always)] - pub fn fircacc_ie(&mut self) -> FircaccIeW { - FircaccIeW::new(self, 30) - } -} -#[doc = "FIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FirccsrSpec; -impl crate::RegisterSpec for FirccsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`firccsr::R`](R) reader structure"] -impl crate::Readable for FirccsrSpec {} -#[doc = "`write(|w| ..)` method takes [`firccsr::W`](W) writer structure"] -impl crate::Writable for FirccsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; -} -#[doc = "`reset()` method sets FIRCCSR to value 0x0300_0031"] -impl crate::Resettable for FirccsrSpec { - const RESET_VALUE: u32 = 0x0300_0031; -} diff --git a/mcxa276-pac/src/scg0/firctrim.rs b/mcxa276-pac/src/scg0/firctrim.rs deleted file mode 100644 index 213957c35..000000000 --- a/mcxa276-pac/src/scg0/firctrim.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `FIRCTRIM` reader"] -pub type R = crate::R; -#[doc = "Register `FIRCTRIM` writer"] -pub type W = crate::W; -#[doc = "Field `TRIMFINE` reader - Trim Fine"] -pub type TrimfineR = crate::FieldReader; -#[doc = "Field `TRIMFINE` writer - Trim Fine"] -pub type TrimfineW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `TRIMCOAR` reader - Trim Coarse"] -pub type TrimcoarR = crate::FieldReader; -#[doc = "Field `TRIMCOAR` writer - Trim Coarse"] -pub type TrimcoarW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `TRIMTEMP` reader - Trim Temperature"] -pub type TrimtempR = crate::FieldReader; -#[doc = "Field `TRIMTEMP` writer - Trim Temperature"] -pub type TrimtempW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `TRIMSTART` reader - Trim Start"] -pub type TrimstartR = crate::FieldReader; -#[doc = "Field `TRIMSTART` writer - Trim Start"] -pub type TrimstartW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:7 - Trim Fine"] - #[inline(always)] - pub fn trimfine(&self) -> TrimfineR { - TrimfineR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:13 - Trim Coarse"] - #[inline(always)] - pub fn trimcoar(&self) -> TrimcoarR { - TrimcoarR::new(((self.bits >> 8) & 0x3f) as u8) - } - #[doc = "Bits 16:19 - Trim Temperature"] - #[inline(always)] - pub fn trimtemp(&self) -> TrimtempR { - TrimtempR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 24:29 - Trim Start"] - #[inline(always)] - pub fn trimstart(&self) -> TrimstartR { - TrimstartR::new(((self.bits >> 24) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Trim Fine"] - #[inline(always)] - pub fn trimfine(&mut self) -> TrimfineW { - TrimfineW::new(self, 0) - } - #[doc = "Bits 8:13 - Trim Coarse"] - #[inline(always)] - pub fn trimcoar(&mut self) -> TrimcoarW { - TrimcoarW::new(self, 8) - } - #[doc = "Bits 16:19 - Trim Temperature"] - #[inline(always)] - pub fn trimtemp(&mut self) -> TrimtempW { - TrimtempW::new(self, 16) - } - #[doc = "Bits 24:29 - Trim Start"] - #[inline(always)] - pub fn trimstart(&mut self) -> TrimstartW { - TrimstartW::new(self, 24) - } -} -#[doc = "FIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`firctrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`firctrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FirctrimSpec; -impl crate::RegisterSpec for FirctrimSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`firctrim::R`](R) reader structure"] -impl crate::Readable for FirctrimSpec {} -#[doc = "`write(|w| ..)` method takes [`firctrim::W`](W) writer structure"] -impl crate::Writable for FirctrimSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FIRCTRIM to value 0"] -impl crate::Resettable for FirctrimSpec {} diff --git a/mcxa276-pac/src/scg0/ldocsr.rs b/mcxa276-pac/src/scg0/ldocsr.rs deleted file mode 100644 index bdc5169b8..000000000 --- a/mcxa276-pac/src/scg0/ldocsr.rs +++ /dev/null @@ -1,338 +0,0 @@ -#[doc = "Register `LDOCSR` reader"] -pub type R = crate::R; -#[doc = "Register `LDOCSR` writer"] -pub type W = crate::W; -#[doc = "LDO Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldoen { - #[doc = "0: LDO is disabled"] - Disabled = 0, - #[doc = "1: LDO is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldoen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDOEN` reader - LDO Enable"] -pub type LdoenR = crate::BitReader; -impl LdoenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldoen { - match self.bits { - false => Ldoen::Disabled, - true => Ldoen::Enabled, - } - } - #[doc = "LDO is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ldoen::Disabled - } - #[doc = "LDO is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ldoen::Enabled - } -} -#[doc = "Field `LDOEN` writer - LDO Enable"] -pub type LdoenW<'a, REG> = crate::BitWriter<'a, REG, Ldoen>; -impl<'a, REG> LdoenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "LDO is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ldoen::Disabled) - } - #[doc = "LDO is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ldoen::Enabled) - } -} -#[doc = "LDO output voltage select\n\nValue on reset: 4"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum VoutSel { - #[doc = "0: VOUT = 1V"] - Vout1v1 = 0, - #[doc = "1: VOUT = 1V"] - Vout1v2 = 1, - #[doc = "2: VOUT = 1V"] - Vout1v3 = 2, - #[doc = "3: VOUT = 1.05V"] - Vout105v = 3, - #[doc = "4: VOUT = 1.1V"] - Vout11v = 4, - #[doc = "5: VOUT = 1.15V"] - Vout115v = 5, - #[doc = "6: VOUT = 1.2V"] - Vout12v = 6, - #[doc = "7: VOUT = 1.25V"] - Vout125v = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: VoutSel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for VoutSel { - type Ux = u8; -} -impl crate::IsEnum for VoutSel {} -#[doc = "Field `VOUT_SEL` reader - LDO output voltage select"] -pub type VoutSelR = crate::FieldReader; -impl VoutSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> VoutSel { - match self.bits { - 0 => VoutSel::Vout1v1, - 1 => VoutSel::Vout1v2, - 2 => VoutSel::Vout1v3, - 3 => VoutSel::Vout105v, - 4 => VoutSel::Vout11v, - 5 => VoutSel::Vout115v, - 6 => VoutSel::Vout12v, - 7 => VoutSel::Vout125v, - _ => unreachable!(), - } - } - #[doc = "VOUT = 1V"] - #[inline(always)] - pub fn is_vout_1v_1(&self) -> bool { - *self == VoutSel::Vout1v1 - } - #[doc = "VOUT = 1V"] - #[inline(always)] - pub fn is_vout_1v_2(&self) -> bool { - *self == VoutSel::Vout1v2 - } - #[doc = "VOUT = 1V"] - #[inline(always)] - pub fn is_vout_1v_3(&self) -> bool { - *self == VoutSel::Vout1v3 - } - #[doc = "VOUT = 1.05V"] - #[inline(always)] - pub fn is_vout_105v(&self) -> bool { - *self == VoutSel::Vout105v - } - #[doc = "VOUT = 1.1V"] - #[inline(always)] - pub fn is_vout_11v(&self) -> bool { - *self == VoutSel::Vout11v - } - #[doc = "VOUT = 1.15V"] - #[inline(always)] - pub fn is_vout_115v(&self) -> bool { - *self == VoutSel::Vout115v - } - #[doc = "VOUT = 1.2V"] - #[inline(always)] - pub fn is_vout_12v(&self) -> bool { - *self == VoutSel::Vout12v - } - #[doc = "VOUT = 1.25V"] - #[inline(always)] - pub fn is_vout_125v(&self) -> bool { - *self == VoutSel::Vout125v - } -} -#[doc = "Field `VOUT_SEL` writer - LDO output voltage select"] -pub type VoutSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, VoutSel, crate::Safe>; -impl<'a, REG> VoutSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "VOUT = 1V"] - #[inline(always)] - pub fn vout_1v_1(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout1v1) - } - #[doc = "VOUT = 1V"] - #[inline(always)] - pub fn vout_1v_2(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout1v2) - } - #[doc = "VOUT = 1V"] - #[inline(always)] - pub fn vout_1v_3(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout1v3) - } - #[doc = "VOUT = 1.05V"] - #[inline(always)] - pub fn vout_105v(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout105v) - } - #[doc = "VOUT = 1.1V"] - #[inline(always)] - pub fn vout_11v(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout11v) - } - #[doc = "VOUT = 1.15V"] - #[inline(always)] - pub fn vout_115v(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout115v) - } - #[doc = "VOUT = 1.2V"] - #[inline(always)] - pub fn vout_12v(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout12v) - } - #[doc = "VOUT = 1.25V"] - #[inline(always)] - pub fn vout_125v(self) -> &'a mut crate::W { - self.variant(VoutSel::Vout125v) - } -} -#[doc = "LDO Bypass\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ldobypass { - #[doc = "0: LDO is not bypassed"] - Disabled = 0, - #[doc = "1: LDO is bypassed"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ldobypass) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LDOBYPASS` reader - LDO Bypass"] -pub type LdobypassR = crate::BitReader; -impl LdobypassR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ldobypass { - match self.bits { - false => Ldobypass::Disabled, - true => Ldobypass::Enabled, - } - } - #[doc = "LDO is not bypassed"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ldobypass::Disabled - } - #[doc = "LDO is bypassed"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ldobypass::Enabled - } -} -#[doc = "Field `LDOBYPASS` writer - LDO Bypass"] -pub type LdobypassW<'a, REG> = crate::BitWriter<'a, REG, Ldobypass>; -impl<'a, REG> LdobypassW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "LDO is not bypassed"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Ldobypass::Disabled) - } - #[doc = "LDO is bypassed"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Ldobypass::Enabled) - } -} -#[doc = "LDO VOUT OK Inform.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum VoutOk { - #[doc = "0: LDO output VOUT is not OK"] - Disabled = 0, - #[doc = "1: LDO output VOUT is OK"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: VoutOk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VOUT_OK` reader - LDO VOUT OK Inform."] -pub type VoutOkR = crate::BitReader; -impl VoutOkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> VoutOk { - match self.bits { - false => VoutOk::Disabled, - true => VoutOk::Enabled, - } - } - #[doc = "LDO output VOUT is not OK"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == VoutOk::Disabled - } - #[doc = "LDO output VOUT is OK"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == VoutOk::Enabled - } -} -impl R { - #[doc = "Bit 0 - LDO Enable"] - #[inline(always)] - pub fn ldoen(&self) -> LdoenR { - LdoenR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:3 - LDO output voltage select"] - #[inline(always)] - pub fn vout_sel(&self) -> VoutSelR { - VoutSelR::new(((self.bits >> 1) & 7) as u8) - } - #[doc = "Bit 4 - LDO Bypass"] - #[inline(always)] - pub fn ldobypass(&self) -> LdobypassR { - LdobypassR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 31 - LDO VOUT OK Inform."] - #[inline(always)] - pub fn vout_ok(&self) -> VoutOkR { - VoutOkR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LDO Enable"] - #[inline(always)] - pub fn ldoen(&mut self) -> LdoenW { - LdoenW::new(self, 0) - } - #[doc = "Bits 1:3 - LDO output voltage select"] - #[inline(always)] - pub fn vout_sel(&mut self) -> VoutSelW { - VoutSelW::new(self, 1) - } - #[doc = "Bit 4 - LDO Bypass"] - #[inline(always)] - pub fn ldobypass(&mut self) -> LdobypassW { - LdobypassW::new(self, 4) - } -} -#[doc = "LDO Control and Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ldocsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ldocsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LdocsrSpec; -impl crate::RegisterSpec for LdocsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ldocsr::R`](R) reader structure"] -impl crate::Readable for LdocsrSpec {} -#[doc = "`write(|w| ..)` method takes [`ldocsr::W`](W) writer structure"] -impl crate::Writable for LdocsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LDOCSR to value 0x08"] -impl crate::Resettable for LdocsrSpec { - const RESET_VALUE: u32 = 0x08; -} diff --git a/mcxa276-pac/src/scg0/param.rs b/mcxa276-pac/src/scg0/param.rs deleted file mode 100644 index d252503fe..000000000 --- a/mcxa276-pac/src/scg0/param.rs +++ /dev/null @@ -1,220 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "SOSC Clock Present\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soscclkpres { - #[doc = "0: SOSC clock source is not present"] - Nopres = 0, - #[doc = "1: SOSC clock source is present"] - Pres = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soscclkpres) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCCLKPRES` reader - SOSC Clock Present"] -pub type SoscclkpresR = crate::BitReader; -impl SoscclkpresR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soscclkpres { - match self.bits { - false => Soscclkpres::Nopres, - true => Soscclkpres::Pres, - } - } - #[doc = "SOSC clock source is not present"] - #[inline(always)] - pub fn is_nopres(&self) -> bool { - *self == Soscclkpres::Nopres - } - #[doc = "SOSC clock source is present"] - #[inline(always)] - pub fn is_pres(&self) -> bool { - *self == Soscclkpres::Pres - } -} -#[doc = "SIRC Clock Present\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sircclkpres { - #[doc = "0: SIRC clock source is not present"] - Nopres = 0, - #[doc = "1: SIRC clock source is present"] - Pres = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sircclkpres) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCCLKPRES` reader - SIRC Clock Present"] -pub type SircclkpresR = crate::BitReader; -impl SircclkpresR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sircclkpres { - match self.bits { - false => Sircclkpres::Nopres, - true => Sircclkpres::Pres, - } - } - #[doc = "SIRC clock source is not present"] - #[inline(always)] - pub fn is_nopres(&self) -> bool { - *self == Sircclkpres::Nopres - } - #[doc = "SIRC clock source is present"] - #[inline(always)] - pub fn is_pres(&self) -> bool { - *self == Sircclkpres::Pres - } -} -#[doc = "FIRC Clock Present\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fircclkpres { - #[doc = "0: FIRC clock source is not present"] - Nopres = 0, - #[doc = "1: FIRC clock source is present"] - Pres = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fircclkpres) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FIRCCLKPRES` reader - FIRC Clock Present"] -pub type FircclkpresR = crate::BitReader; -impl FircclkpresR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fircclkpres { - match self.bits { - false => Fircclkpres::Nopres, - true => Fircclkpres::Pres, - } - } - #[doc = "FIRC clock source is not present"] - #[inline(always)] - pub fn is_nopres(&self) -> bool { - *self == Fircclkpres::Nopres - } - #[doc = "FIRC clock source is present"] - #[inline(always)] - pub fn is_pres(&self) -> bool { - *self == Fircclkpres::Pres - } -} -#[doc = "ROSC Clock Present\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Roscclkpres { - #[doc = "0: ROSC clock source is not present"] - Nopres = 0, - #[doc = "1: ROSC clock source is present"] - Pres = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Roscclkpres) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROSCCLKPRES` reader - ROSC Clock Present"] -pub type RoscclkpresR = crate::BitReader; -impl RoscclkpresR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Roscclkpres { - match self.bits { - false => Roscclkpres::Nopres, - true => Roscclkpres::Pres, - } - } - #[doc = "ROSC clock source is not present"] - #[inline(always)] - pub fn is_nopres(&self) -> bool { - *self == Roscclkpres::Nopres - } - #[doc = "ROSC clock source is present"] - #[inline(always)] - pub fn is_pres(&self) -> bool { - *self == Roscclkpres::Pres - } -} -#[doc = "SPLL Clock Present\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllclkpres { - #[doc = "0: SPLL clock source is not present"] - Nopres = 0, - #[doc = "1: SPLL clock source is present"] - Pres = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllclkpres) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLCLKPRES` reader - SPLL Clock Present"] -pub type SpllclkpresR = crate::BitReader; -impl SpllclkpresR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllclkpres { - match self.bits { - false => Spllclkpres::Nopres, - true => Spllclkpres::Pres, - } - } - #[doc = "SPLL clock source is not present"] - #[inline(always)] - pub fn is_nopres(&self) -> bool { - *self == Spllclkpres::Nopres - } - #[doc = "SPLL clock source is present"] - #[inline(always)] - pub fn is_pres(&self) -> bool { - *self == Spllclkpres::Pres - } -} -impl R { - #[doc = "Bit 1 - SOSC Clock Present"] - #[inline(always)] - pub fn soscclkpres(&self) -> SoscclkpresR { - SoscclkpresR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - SIRC Clock Present"] - #[inline(always)] - pub fn sircclkpres(&self) -> SircclkpresR { - SircclkpresR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - FIRC Clock Present"] - #[inline(always)] - pub fn fircclkpres(&self) -> FircclkpresR { - FircclkpresR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - ROSC Clock Present"] - #[inline(always)] - pub fn roscclkpres(&self) -> RoscclkpresR { - RoscclkpresR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 6 - SPLL Clock Present"] - #[inline(always)] - pub fn spllclkpres(&self) -> SpllclkpresR { - SpllclkpresR::new(((self.bits >> 6) & 1) != 0) - } -} -#[doc = "Parameter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x5e"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x5e; -} diff --git a/mcxa276-pac/src/scg0/rccr.rs b/mcxa276-pac/src/scg0/rccr.rs deleted file mode 100644 index e47eed92e..000000000 --- a/mcxa276-pac/src/scg0/rccr.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `RCCR` reader"] -pub type R = crate::R; -#[doc = "Register `RCCR` writer"] -pub type W = crate::W; -#[doc = "System Clock Source\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Scs { - #[doc = "1: SOSC"] - Sosc = 1, - #[doc = "2: SIRC"] - Sirc = 2, - #[doc = "3: FIRC"] - Firc = 3, - #[doc = "4: ROSC"] - Rosc = 4, - #[doc = "6: SPLL"] - Spll = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Scs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Scs { - type Ux = u8; -} -impl crate::IsEnum for Scs {} -#[doc = "Field `SCS` reader - System Clock Source"] -pub type ScsR = crate::FieldReader; -impl ScsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Scs::Sosc), - 2 => Some(Scs::Sirc), - 3 => Some(Scs::Firc), - 4 => Some(Scs::Rosc), - 6 => Some(Scs::Spll), - _ => None, - } - } - #[doc = "SOSC"] - #[inline(always)] - pub fn is_sosc(&self) -> bool { - *self == Scs::Sosc - } - #[doc = "SIRC"] - #[inline(always)] - pub fn is_sirc(&self) -> bool { - *self == Scs::Sirc - } - #[doc = "FIRC"] - #[inline(always)] - pub fn is_firc(&self) -> bool { - *self == Scs::Firc - } - #[doc = "ROSC"] - #[inline(always)] - pub fn is_rosc(&self) -> bool { - *self == Scs::Rosc - } - #[doc = "SPLL"] - #[inline(always)] - pub fn is_spll(&self) -> bool { - *self == Scs::Spll - } -} -#[doc = "Field `SCS` writer - System Clock Source"] -pub type ScsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Scs>; -impl<'a, REG> ScsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "SOSC"] - #[inline(always)] - pub fn sosc(self) -> &'a mut crate::W { - self.variant(Scs::Sosc) - } - #[doc = "SIRC"] - #[inline(always)] - pub fn sirc(self) -> &'a mut crate::W { - self.variant(Scs::Sirc) - } - #[doc = "FIRC"] - #[inline(always)] - pub fn firc(self) -> &'a mut crate::W { - self.variant(Scs::Firc) - } - #[doc = "ROSC"] - #[inline(always)] - pub fn rosc(self) -> &'a mut crate::W { - self.variant(Scs::Rosc) - } - #[doc = "SPLL"] - #[inline(always)] - pub fn spll(self) -> &'a mut crate::W { - self.variant(Scs::Spll) - } -} -impl R { - #[doc = "Bits 24:26 - System Clock Source"] - #[inline(always)] - pub fn scs(&self) -> ScsR { - ScsR::new(((self.bits >> 24) & 7) as u8) - } -} -impl W { - #[doc = "Bits 24:26 - System Clock Source"] - #[inline(always)] - pub fn scs(&mut self) -> ScsW { - ScsW::new(self, 24) - } -} -#[doc = "Run Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RccrSpec; -impl crate::RegisterSpec for RccrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rccr::R`](R) reader structure"] -impl crate::Readable for RccrSpec {} -#[doc = "`write(|w| ..)` method takes [`rccr::W`](W) writer structure"] -impl crate::Writable for RccrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RCCR to value 0x0300_0000"] -impl crate::Resettable for RccrSpec { - const RESET_VALUE: u32 = 0x0300_0000; -} diff --git a/mcxa276-pac/src/scg0/rosccsr.rs b/mcxa276-pac/src/scg0/rosccsr.rs deleted file mode 100644 index 614bf4157..000000000 --- a/mcxa276-pac/src/scg0/rosccsr.rs +++ /dev/null @@ -1,230 +0,0 @@ -#[doc = "Register `ROSCCSR` reader"] -pub type R = crate::R; -#[doc = "Register `ROSCCSR` writer"] -pub type W = crate::W; -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Control Status Register can be written"] - WriteEnabled = 0, - #[doc = "1: Control Status Register cannot be written"] - WriteDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::WriteEnabled, - true => Lk::WriteDisabled, - } - } - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn is_write_enabled(&self) -> bool { - *self == Lk::WriteEnabled - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn is_write_disabled(&self) -> bool { - *self == Lk::WriteDisabled - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn write_enabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteEnabled) - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn write_disabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteDisabled) - } -} -#[doc = "ROSC Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Roscvld { - #[doc = "0: ROSC is not enabled or clock is not valid"] - DisabledOrNotValid = 0, - #[doc = "1: ROSC is enabled and output clock is valid"] - EnabledAndValid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Roscvld) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROSCVLD` reader - ROSC Valid"] -pub type RoscvldR = crate::BitReader; -impl RoscvldR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Roscvld { - match self.bits { - false => Roscvld::DisabledOrNotValid, - true => Roscvld::EnabledAndValid, - } - } - #[doc = "ROSC is not enabled or clock is not valid"] - #[inline(always)] - pub fn is_disabled_or_not_valid(&self) -> bool { - *self == Roscvld::DisabledOrNotValid - } - #[doc = "ROSC is enabled and output clock is valid"] - #[inline(always)] - pub fn is_enabled_and_valid(&self) -> bool { - *self == Roscvld::EnabledAndValid - } -} -#[doc = "ROSC Selected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Roscsel { - #[doc = "0: ROSC is not the system clock source"] - NotRosc = 0, - #[doc = "1: ROSC is the system clock source"] - Rosc = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Roscsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROSCSEL` reader - ROSC Selected"] -pub type RoscselR = crate::BitReader; -impl RoscselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Roscsel { - match self.bits { - false => Roscsel::NotRosc, - true => Roscsel::Rosc, - } - } - #[doc = "ROSC is not the system clock source"] - #[inline(always)] - pub fn is_not_rosc(&self) -> bool { - *self == Roscsel::NotRosc - } - #[doc = "ROSC is the system clock source"] - #[inline(always)] - pub fn is_rosc(&self) -> bool { - *self == Roscsel::Rosc - } -} -#[doc = "ROSC Clock Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Roscerr { - #[doc = "0: ROSC Clock has not detected an error"] - DisabledOrNoError = 0, - #[doc = "1: ROSC Clock has detected an error"] - EnabledAndError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Roscerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ROSCERR` reader - ROSC Clock Error"] -pub type RoscerrR = crate::BitReader; -impl RoscerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Roscerr { - match self.bits { - false => Roscerr::DisabledOrNoError, - true => Roscerr::EnabledAndError, - } - } - #[doc = "ROSC Clock has not detected an error"] - #[inline(always)] - pub fn is_disabled_or_no_error(&self) -> bool { - *self == Roscerr::DisabledOrNoError - } - #[doc = "ROSC Clock has detected an error"] - #[inline(always)] - pub fn is_enabled_and_error(&self) -> bool { - *self == Roscerr::EnabledAndError - } -} -#[doc = "Field `ROSCERR` writer - ROSC Clock Error"] -pub type RoscerrW<'a, REG> = crate::BitWriter1C<'a, REG, Roscerr>; -impl<'a, REG> RoscerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ROSC Clock has not detected an error"] - #[inline(always)] - pub fn disabled_or_no_error(self) -> &'a mut crate::W { - self.variant(Roscerr::DisabledOrNoError) - } - #[doc = "ROSC Clock has detected an error"] - #[inline(always)] - pub fn enabled_and_error(self) -> &'a mut crate::W { - self.variant(Roscerr::EnabledAndError) - } -} -impl R { - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - ROSC Valid"] - #[inline(always)] - pub fn roscvld(&self) -> RoscvldR { - RoscvldR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - ROSC Selected"] - #[inline(always)] - pub fn roscsel(&self) -> RoscselR { - RoscselR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - ROSC Clock Error"] - #[inline(always)] - pub fn roscerr(&self) -> RoscerrR { - RoscerrR::new(((self.bits >> 26) & 1) != 0) - } -} -impl W { - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 23) - } - #[doc = "Bit 26 - ROSC Clock Error"] - #[inline(always)] - pub fn roscerr(&mut self) -> RoscerrW { - RoscerrW::new(self, 26) - } -} -#[doc = "ROSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rosccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RosccsrSpec; -impl crate::RegisterSpec for RosccsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rosccsr::R`](R) reader structure"] -impl crate::Readable for RosccsrSpec {} -#[doc = "`write(|w| ..)` method takes [`rosccsr::W`](W) writer structure"] -impl crate::Writable for RosccsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; -} -#[doc = "`reset()` method sets ROSCCSR to value 0"] -impl crate::Resettable for RosccsrSpec {} diff --git a/mcxa276-pac/src/scg0/sirccsr.rs b/mcxa276-pac/src/scg0/sirccsr.rs deleted file mode 100644 index 810dc3ea3..000000000 --- a/mcxa276-pac/src/scg0/sirccsr.rs +++ /dev/null @@ -1,651 +0,0 @@ -#[doc = "Register `SIRCCSR` reader"] -pub type R = crate::R; -#[doc = "Register `SIRCCSR` writer"] -pub type W = crate::W; -#[doc = "SIRC Stop Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sircsten { - #[doc = "0: SIRC is disabled in Deep Sleep mode"] - Disabled = 0, - #[doc = "1: SIRC is enabled in Deep Sleep mode"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sircsten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCSTEN` reader - SIRC Stop Enable"] -pub type SircstenR = crate::BitReader; -impl SircstenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sircsten { - match self.bits { - false => Sircsten::Disabled, - true => Sircsten::Enabled, - } - } - #[doc = "SIRC is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sircsten::Disabled - } - #[doc = "SIRC is enabled in Deep Sleep mode"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sircsten::Enabled - } -} -#[doc = "Field `SIRCSTEN` writer - SIRC Stop Enable"] -pub type SircstenW<'a, REG> = crate::BitWriter<'a, REG, Sircsten>; -impl<'a, REG> SircstenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SIRC is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sircsten::Disabled) - } - #[doc = "SIRC is enabled in Deep Sleep mode"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sircsten::Enabled) - } -} -#[doc = "SIRC Clock to Peripherals Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SircClkPeriphEn { - #[doc = "0: SIRC clock to peripherals is disabled"] - Disabled = 0, - #[doc = "1: SIRC clock to peripherals is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SircClkPeriphEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRC_CLK_PERIPH_EN` reader - SIRC Clock to Peripherals Enable"] -pub type SircClkPeriphEnR = crate::BitReader; -impl SircClkPeriphEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SircClkPeriphEn { - match self.bits { - false => SircClkPeriphEn::Disabled, - true => SircClkPeriphEn::Enabled, - } - } - #[doc = "SIRC clock to peripherals is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == SircClkPeriphEn::Disabled - } - #[doc = "SIRC clock to peripherals is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == SircClkPeriphEn::Enabled - } -} -#[doc = "Field `SIRC_CLK_PERIPH_EN` writer - SIRC Clock to Peripherals Enable"] -pub type SircClkPeriphEnW<'a, REG> = crate::BitWriter<'a, REG, SircClkPeriphEn>; -impl<'a, REG> SircClkPeriphEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SIRC clock to peripherals is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(SircClkPeriphEn::Disabled) - } - #[doc = "SIRC clock to peripherals is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(SircClkPeriphEn::Enabled) - } -} -#[doc = "SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sirctren { - #[doc = "0: Disables trimming SIRC to an external clock source"] - Disabled = 0, - #[doc = "1: Enables trimming SIRC to an external clock source"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sirctren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCTREN` reader - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] -pub type SirctrenR = crate::BitReader; -impl SirctrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sirctren { - match self.bits { - false => Sirctren::Disabled, - true => Sirctren::Enabled, - } - } - #[doc = "Disables trimming SIRC to an external clock source"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sirctren::Disabled - } - #[doc = "Enables trimming SIRC to an external clock source"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sirctren::Enabled - } -} -#[doc = "Field `SIRCTREN` writer - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] -pub type SirctrenW<'a, REG> = crate::BitWriter<'a, REG, Sirctren>; -impl<'a, REG> SirctrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables trimming SIRC to an external clock source"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sirctren::Disabled) - } - #[doc = "Enables trimming SIRC to an external clock source"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sirctren::Enabled) - } -} -#[doc = "SIRC Trim Update\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sirctrup { - #[doc = "0: Disables SIRC trimming updates"] - Disabled = 0, - #[doc = "1: Enables SIRC trimming updates"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sirctrup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCTRUP` reader - SIRC Trim Update"] -pub type SirctrupR = crate::BitReader; -impl SirctrupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sirctrup { - match self.bits { - false => Sirctrup::Disabled, - true => Sirctrup::Enabled, - } - } - #[doc = "Disables SIRC trimming updates"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sirctrup::Disabled - } - #[doc = "Enables SIRC trimming updates"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sirctrup::Enabled - } -} -#[doc = "Field `SIRCTRUP` writer - SIRC Trim Update"] -pub type SirctrupW<'a, REG> = crate::BitWriter<'a, REG, Sirctrup>; -impl<'a, REG> SirctrupW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables SIRC trimming updates"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sirctrup::Disabled) - } - #[doc = "Enables SIRC trimming updates"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sirctrup::Enabled) - } -} -#[doc = "SIRC TRIM LOCK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrimLock { - #[doc = "0: SIRC auto trim not locked to target frequency range"] - SircNotLocked = 0, - #[doc = "1: SIRC auto trim locked to target frequency range"] - SircLocked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrimLock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIM_LOCK` reader - SIRC TRIM LOCK"] -pub type TrimLockR = crate::BitReader; -impl TrimLockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrimLock { - match self.bits { - false => TrimLock::SircNotLocked, - true => TrimLock::SircLocked, - } - } - #[doc = "SIRC auto trim not locked to target frequency range"] - #[inline(always)] - pub fn is_sirc_not_locked(&self) -> bool { - *self == TrimLock::SircNotLocked - } - #[doc = "SIRC auto trim locked to target frequency range"] - #[inline(always)] - pub fn is_sirc_locked(&self) -> bool { - *self == TrimLock::SircLocked - } -} -#[doc = "Coarse Auto Trim Bypass\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoarseTrimBypass { - #[doc = "0: SIRC Coarse Auto Trim NOT Bypassed"] - NotBypassed = 0, - #[doc = "1: SIRC Coarse Auto Trim Bypassed"] - Bypassed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoarseTrimBypass) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COARSE_TRIM_BYPASS` reader - Coarse Auto Trim Bypass"] -pub type CoarseTrimBypassR = crate::BitReader; -impl CoarseTrimBypassR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoarseTrimBypass { - match self.bits { - false => CoarseTrimBypass::NotBypassed, - true => CoarseTrimBypass::Bypassed, - } - } - #[doc = "SIRC Coarse Auto Trim NOT Bypassed"] - #[inline(always)] - pub fn is_not_bypassed(&self) -> bool { - *self == CoarseTrimBypass::NotBypassed - } - #[doc = "SIRC Coarse Auto Trim Bypassed"] - #[inline(always)] - pub fn is_bypassed(&self) -> bool { - *self == CoarseTrimBypass::Bypassed - } -} -#[doc = "Field `COARSE_TRIM_BYPASS` writer - Coarse Auto Trim Bypass"] -pub type CoarseTrimBypassW<'a, REG> = crate::BitWriter<'a, REG, CoarseTrimBypass>; -impl<'a, REG> CoarseTrimBypassW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SIRC Coarse Auto Trim NOT Bypassed"] - #[inline(always)] - pub fn not_bypassed(self) -> &'a mut crate::W { - self.variant(CoarseTrimBypass::NotBypassed) - } - #[doc = "SIRC Coarse Auto Trim Bypassed"] - #[inline(always)] - pub fn bypassed(self) -> &'a mut crate::W { - self.variant(CoarseTrimBypass::Bypassed) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Control Status Register can be written"] - WriteEnabled = 0, - #[doc = "1: Control Status Register cannot be written"] - WriteDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::WriteEnabled, - true => Lk::WriteDisabled, - } - } - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn is_write_enabled(&self) -> bool { - *self == Lk::WriteEnabled - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn is_write_disabled(&self) -> bool { - *self == Lk::WriteDisabled - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn write_enabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteEnabled) - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn write_disabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteDisabled) - } -} -#[doc = "SIRC Valid\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sircvld { - #[doc = "0: SIRC is not enabled or clock is not valid"] - DisabledOrNotValid = 0, - #[doc = "1: SIRC is enabled and output clock is valid"] - EnabledAndValid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sircvld) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCVLD` reader - SIRC Valid"] -pub type SircvldR = crate::BitReader; -impl SircvldR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sircvld { - match self.bits { - false => Sircvld::DisabledOrNotValid, - true => Sircvld::EnabledAndValid, - } - } - #[doc = "SIRC is not enabled or clock is not valid"] - #[inline(always)] - pub fn is_disabled_or_not_valid(&self) -> bool { - *self == Sircvld::DisabledOrNotValid - } - #[doc = "SIRC is enabled and output clock is valid"] - #[inline(always)] - pub fn is_enabled_and_valid(&self) -> bool { - *self == Sircvld::EnabledAndValid - } -} -#[doc = "SIRC Selected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sircsel { - #[doc = "0: SIRC is not the system clock source"] - NotSirc = 0, - #[doc = "1: SIRC is the system clock source"] - Sirc = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sircsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCSEL` reader - SIRC Selected"] -pub type SircselR = crate::BitReader; -impl SircselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sircsel { - match self.bits { - false => Sircsel::NotSirc, - true => Sircsel::Sirc, - } - } - #[doc = "SIRC is not the system clock source"] - #[inline(always)] - pub fn is_not_sirc(&self) -> bool { - *self == Sircsel::NotSirc - } - #[doc = "SIRC is the system clock source"] - #[inline(always)] - pub fn is_sirc(&self) -> bool { - *self == Sircsel::Sirc - } -} -#[doc = "SIRC Clock Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sircerr { - #[doc = "0: Error not detected with the SIRC trimming"] - ErrorNotDetected = 0, - #[doc = "1: Error detected with the SIRC trimming"] - ErrorDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sircerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCERR` reader - SIRC Clock Error"] -pub type SircerrR = crate::BitReader; -impl SircerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sircerr { - match self.bits { - false => Sircerr::ErrorNotDetected, - true => Sircerr::ErrorDetected, - } - } - #[doc = "Error not detected with the SIRC trimming"] - #[inline(always)] - pub fn is_error_not_detected(&self) -> bool { - *self == Sircerr::ErrorNotDetected - } - #[doc = "Error detected with the SIRC trimming"] - #[inline(always)] - pub fn is_error_detected(&self) -> bool { - *self == Sircerr::ErrorDetected - } -} -#[doc = "Field `SIRCERR` writer - SIRC Clock Error"] -pub type SircerrW<'a, REG> = crate::BitWriter1C<'a, REG, Sircerr>; -impl<'a, REG> SircerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error not detected with the SIRC trimming"] - #[inline(always)] - pub fn error_not_detected(self) -> &'a mut crate::W { - self.variant(Sircerr::ErrorNotDetected) - } - #[doc = "Error detected with the SIRC trimming"] - #[inline(always)] - pub fn error_detected(self) -> &'a mut crate::W { - self.variant(Sircerr::ErrorDetected) - } -} -#[doc = "SIRC Clock Error Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SircerrIe { - #[doc = "0: SIRCERR interrupt is not enabled"] - ErrorNotDetected = 0, - #[doc = "1: SIRCERR interrupt is enabled"] - ErrorDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SircerrIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SIRCERR_IE` reader - SIRC Clock Error Interrupt Enable"] -pub type SircerrIeR = crate::BitReader; -impl SircerrIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SircerrIe { - match self.bits { - false => SircerrIe::ErrorNotDetected, - true => SircerrIe::ErrorDetected, - } - } - #[doc = "SIRCERR interrupt is not enabled"] - #[inline(always)] - pub fn is_error_not_detected(&self) -> bool { - *self == SircerrIe::ErrorNotDetected - } - #[doc = "SIRCERR interrupt is enabled"] - #[inline(always)] - pub fn is_error_detected(&self) -> bool { - *self == SircerrIe::ErrorDetected - } -} -#[doc = "Field `SIRCERR_IE` writer - SIRC Clock Error Interrupt Enable"] -pub type SircerrIeW<'a, REG> = crate::BitWriter<'a, REG, SircerrIe>; -impl<'a, REG> SircerrIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SIRCERR interrupt is not enabled"] - #[inline(always)] - pub fn error_not_detected(self) -> &'a mut crate::W { - self.variant(SircerrIe::ErrorNotDetected) - } - #[doc = "SIRCERR interrupt is enabled"] - #[inline(always)] - pub fn error_detected(self) -> &'a mut crate::W { - self.variant(SircerrIe::ErrorDetected) - } -} -impl R { - #[doc = "Bit 1 - SIRC Stop Enable"] - #[inline(always)] - pub fn sircsten(&self) -> SircstenR { - SircstenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 5 - SIRC Clock to Peripherals Enable"] - #[inline(always)] - pub fn sirc_clk_periph_en(&self) -> SircClkPeriphEnR { - SircClkPeriphEnR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 8 - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] - #[inline(always)] - pub fn sirctren(&self) -> SirctrenR { - SirctrenR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SIRC Trim Update"] - #[inline(always)] - pub fn sirctrup(&self) -> SirctrupR { - SirctrupR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SIRC TRIM LOCK"] - #[inline(always)] - pub fn trim_lock(&self) -> TrimLockR { - TrimLockR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Coarse Auto Trim Bypass"] - #[inline(always)] - pub fn coarse_trim_bypass(&self) -> CoarseTrimBypassR { - CoarseTrimBypassR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - SIRC Valid"] - #[inline(always)] - pub fn sircvld(&self) -> SircvldR { - SircvldR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - SIRC Selected"] - #[inline(always)] - pub fn sircsel(&self) -> SircselR { - SircselR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - SIRC Clock Error"] - #[inline(always)] - pub fn sircerr(&self) -> SircerrR { - SircerrR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - SIRC Clock Error Interrupt Enable"] - #[inline(always)] - pub fn sircerr_ie(&self) -> SircerrIeR { - SircerrIeR::new(((self.bits >> 27) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - SIRC Stop Enable"] - #[inline(always)] - pub fn sircsten(&mut self) -> SircstenW { - SircstenW::new(self, 1) - } - #[doc = "Bit 5 - SIRC Clock to Peripherals Enable"] - #[inline(always)] - pub fn sirc_clk_periph_en(&mut self) -> SircClkPeriphEnW { - SircClkPeriphEnW::new(self, 5) - } - #[doc = "Bit 8 - SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)"] - #[inline(always)] - pub fn sirctren(&mut self) -> SirctrenW { - SirctrenW::new(self, 8) - } - #[doc = "Bit 9 - SIRC Trim Update"] - #[inline(always)] - pub fn sirctrup(&mut self) -> SirctrupW { - SirctrupW::new(self, 9) - } - #[doc = "Bit 11 - Coarse Auto Trim Bypass"] - #[inline(always)] - pub fn coarse_trim_bypass(&mut self) -> CoarseTrimBypassW { - CoarseTrimBypassW::new(self, 11) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 23) - } - #[doc = "Bit 26 - SIRC Clock Error"] - #[inline(always)] - pub fn sircerr(&mut self) -> SircerrW { - SircerrW::new(self, 26) - } - #[doc = "Bit 27 - SIRC Clock Error Interrupt Enable"] - #[inline(always)] - pub fn sircerr_ie(&mut self) -> SircerrIeW { - SircerrIeW::new(self, 27) - } -} -#[doc = "SIRC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SirccsrSpec; -impl crate::RegisterSpec for SirccsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sirccsr::R`](R) reader structure"] -impl crate::Readable for SirccsrSpec {} -#[doc = "`write(|w| ..)` method takes [`sirccsr::W`](W) writer structure"] -impl crate::Writable for SirccsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; -} -#[doc = "`reset()` method sets SIRCCSR to value 0x0100_0020"] -impl crate::Resettable for SirccsrSpec { - const RESET_VALUE: u32 = 0x0100_0020; -} diff --git a/mcxa276-pac/src/scg0/sircstat.rs b/mcxa276-pac/src/scg0/sircstat.rs deleted file mode 100644 index d588cd35f..000000000 --- a/mcxa276-pac/src/scg0/sircstat.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `SIRCSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `SIRCSTAT` writer"] -pub type W = crate::W; -#[doc = "Field `CCOTRIM` reader - CCO Trim"] -pub type CcotrimR = crate::FieldReader; -#[doc = "Field `CCOTRIM` writer - CCO Trim"] -pub type CcotrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `CLTRIM` reader - CL Trim"] -pub type CltrimR = crate::FieldReader; -#[doc = "Field `CLTRIM` writer - CL Trim"] -pub type CltrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:5 - CCO Trim"] - #[inline(always)] - pub fn ccotrim(&self) -> CcotrimR { - CcotrimR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 8:13 - CL Trim"] - #[inline(always)] - pub fn cltrim(&self) -> CltrimR { - CltrimR::new(((self.bits >> 8) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - CCO Trim"] - #[inline(always)] - pub fn ccotrim(&mut self) -> CcotrimW { - CcotrimW::new(self, 0) - } - #[doc = "Bits 8:13 - CL Trim"] - #[inline(always)] - pub fn cltrim(&mut self) -> CltrimW { - CltrimW::new(self, 8) - } -} -#[doc = "SIRC Auto-trimming Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sircstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sircstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SircstatSpec; -impl crate::RegisterSpec for SircstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sircstat::R`](R) reader structure"] -impl crate::Readable for SircstatSpec {} -#[doc = "`write(|w| ..)` method takes [`sircstat::W`](W) writer structure"] -impl crate::Writable for SircstatSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SIRCSTAT to value 0"] -impl crate::Resettable for SircstatSpec {} diff --git a/mcxa276-pac/src/scg0/sirctcfg.rs b/mcxa276-pac/src/scg0/sirctcfg.rs deleted file mode 100644 index 11f8a91bb..000000000 --- a/mcxa276-pac/src/scg0/sirctcfg.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `SIRCTCFG` reader"] -pub type R = crate::R; -#[doc = "Register `SIRCTCFG` writer"] -pub type W = crate::W; -#[doc = "Trim Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trimsrc { - #[doc = "2: SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."] - Sosc = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trimsrc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trimsrc { - type Ux = u8; -} -impl crate::IsEnum for Trimsrc {} -#[doc = "Field `TRIMSRC` reader - Trim Source"] -pub type TrimsrcR = crate::FieldReader; -impl TrimsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 2 => Some(Trimsrc::Sosc), - _ => None, - } - } - #[doc = "SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."] - #[inline(always)] - pub fn is_sosc(&self) -> bool { - *self == Trimsrc::Sosc - } -} -#[doc = "Field `TRIMSRC` writer - Trim Source"] -pub type TrimsrcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trimsrc>; -impl<'a, REG> TrimsrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."] - #[inline(always)] - pub fn sosc(self) -> &'a mut crate::W { - self.variant(Trimsrc::Sosc) - } -} -#[doc = "Field `TRIMDIV` reader - SIRC Trim Pre-divider"] -pub type TrimdivR = crate::FieldReader; -#[doc = "Field `TRIMDIV` writer - SIRC Trim Pre-divider"] -pub type TrimdivW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bits 0:1 - Trim Source"] - #[inline(always)] - pub fn trimsrc(&self) -> TrimsrcR { - TrimsrcR::new((self.bits & 3) as u8) - } - #[doc = "Bits 16:22 - SIRC Trim Pre-divider"] - #[inline(always)] - pub fn trimdiv(&self) -> TrimdivR { - TrimdivR::new(((self.bits >> 16) & 0x7f) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Trim Source"] - #[inline(always)] - pub fn trimsrc(&mut self) -> TrimsrcW { - TrimsrcW::new(self, 0) - } - #[doc = "Bits 16:22 - SIRC Trim Pre-divider"] - #[inline(always)] - pub fn trimdiv(&mut self) -> TrimdivW { - TrimdivW::new(self, 16) - } -} -#[doc = "SIRC Trim Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SirctcfgSpec; -impl crate::RegisterSpec for SirctcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sirctcfg::R`](R) reader structure"] -impl crate::Readable for SirctcfgSpec {} -#[doc = "`write(|w| ..)` method takes [`sirctcfg::W`](W) writer structure"] -impl crate::Writable for SirctcfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SIRCTCFG to value 0"] -impl crate::Resettable for SirctcfgSpec {} diff --git a/mcxa276-pac/src/scg0/sirctrim.rs b/mcxa276-pac/src/scg0/sirctrim.rs deleted file mode 100644 index 7515b5b03..000000000 --- a/mcxa276-pac/src/scg0/sirctrim.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `SIRCTRIM` reader"] -pub type R = crate::R; -#[doc = "Register `SIRCTRIM` writer"] -pub type W = crate::W; -#[doc = "Field `CCOTRIM` reader - CCO Trim"] -pub type CcotrimR = crate::FieldReader; -#[doc = "Field `CCOTRIM` writer - CCO Trim"] -pub type CcotrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `CLTRIM` reader - CL Trim"] -pub type CltrimR = crate::FieldReader; -#[doc = "Field `CLTRIM` writer - CL Trim"] -pub type CltrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `TCTRIM` reader - Trim Temp"] -pub type TctrimR = crate::FieldReader; -#[doc = "Field `TCTRIM` writer - Trim Temp"] -pub type TctrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `FVCHTRIM` reader - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] -pub type FvchtrimR = crate::FieldReader; -#[doc = "Field `FVCHTRIM` writer - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] -pub type FvchtrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bits 0:5 - CCO Trim"] - #[inline(always)] - pub fn ccotrim(&self) -> CcotrimR { - CcotrimR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 8:13 - CL Trim"] - #[inline(always)] - pub fn cltrim(&self) -> CltrimR { - CltrimR::new(((self.bits >> 8) & 0x3f) as u8) - } - #[doc = "Bits 16:20 - Trim Temp"] - #[inline(always)] - pub fn tctrim(&self) -> TctrimR { - TctrimR::new(((self.bits >> 16) & 0x1f) as u8) - } - #[doc = "Bits 24:28 - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] - #[inline(always)] - pub fn fvchtrim(&self) -> FvchtrimR { - FvchtrimR::new(((self.bits >> 24) & 0x1f) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - CCO Trim"] - #[inline(always)] - pub fn ccotrim(&mut self) -> CcotrimW { - CcotrimW::new(self, 0) - } - #[doc = "Bits 8:13 - CL Trim"] - #[inline(always)] - pub fn cltrim(&mut self) -> CltrimW { - CltrimW::new(self, 8) - } - #[doc = "Bits 16:20 - Trim Temp"] - #[inline(always)] - pub fn tctrim(&mut self) -> TctrimW { - TctrimW::new(self, 16) - } - #[doc = "Bits 24:28 - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"] - #[inline(always)] - pub fn fvchtrim(&mut self) -> FvchtrimW { - FvchtrimW::new(self, 24) - } -} -#[doc = "SIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SirctrimSpec; -impl crate::RegisterSpec for SirctrimSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sirctrim::R`](R) reader structure"] -impl crate::Readable for SirctrimSpec {} -#[doc = "`write(|w| ..)` method takes [`sirctrim::W`](W) writer structure"] -impl crate::Writable for SirctrimSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SIRCTRIM to value 0"] -impl crate::Resettable for SirctrimSpec {} diff --git a/mcxa276-pac/src/scg0/sosccfg.rs b/mcxa276-pac/src/scg0/sosccfg.rs deleted file mode 100644 index d549827af..000000000 --- a/mcxa276-pac/src/scg0/sosccfg.rs +++ /dev/null @@ -1,180 +0,0 @@ -#[doc = "Register `SOSCCFG` reader"] -pub type R = crate::R; -#[doc = "Register `SOSCCFG` writer"] -pub type W = crate::W; -#[doc = "External Reference Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erefs { - #[doc = "0: External reference clock selected."] - External = 0, - #[doc = "1: Internal crystal oscillator of OSC selected."] - Internal = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erefs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EREFS` reader - External Reference Select"] -pub type ErefsR = crate::BitReader; -impl ErefsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erefs { - match self.bits { - false => Erefs::External, - true => Erefs::Internal, - } - } - #[doc = "External reference clock selected."] - #[inline(always)] - pub fn is_external(&self) -> bool { - *self == Erefs::External - } - #[doc = "Internal crystal oscillator of OSC selected."] - #[inline(always)] - pub fn is_internal(&self) -> bool { - *self == Erefs::Internal - } -} -#[doc = "Field `EREFS` writer - External Reference Select"] -pub type ErefsW<'a, REG> = crate::BitWriter<'a, REG, Erefs>; -impl<'a, REG> ErefsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "External reference clock selected."] - #[inline(always)] - pub fn external(self) -> &'a mut crate::W { - self.variant(Erefs::External) - } - #[doc = "Internal crystal oscillator of OSC selected."] - #[inline(always)] - pub fn internal(self) -> &'a mut crate::W { - self.variant(Erefs::Internal) - } -} -#[doc = "SOSC Range Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Range { - #[doc = "0: Frequency range select of 8-16 MHz."] - Freq16to20mhz = 0, - #[doc = "1: Frequency range select of 16-25 MHz."] - LowFreq = 1, - #[doc = "2: Frequency range select of 25-40 MHz."] - MediumFreq = 2, - #[doc = "3: Frequency range select of 40-50 MHz."] - HighFreq = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Range) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Range { - type Ux = u8; -} -impl crate::IsEnum for Range {} -#[doc = "Field `RANGE` reader - SOSC Range Select"] -pub type RangeR = crate::FieldReader; -impl RangeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Range { - match self.bits { - 0 => Range::Freq16to20mhz, - 1 => Range::LowFreq, - 2 => Range::MediumFreq, - 3 => Range::HighFreq, - _ => unreachable!(), - } - } - #[doc = "Frequency range select of 8-16 MHz."] - #[inline(always)] - pub fn is_freq_16to20mhz(&self) -> bool { - *self == Range::Freq16to20mhz - } - #[doc = "Frequency range select of 16-25 MHz."] - #[inline(always)] - pub fn is_low_freq(&self) -> bool { - *self == Range::LowFreq - } - #[doc = "Frequency range select of 25-40 MHz."] - #[inline(always)] - pub fn is_medium_freq(&self) -> bool { - *self == Range::MediumFreq - } - #[doc = "Frequency range select of 40-50 MHz."] - #[inline(always)] - pub fn is_high_freq(&self) -> bool { - *self == Range::HighFreq - } -} -#[doc = "Field `RANGE` writer - SOSC Range Select"] -pub type RangeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Range, crate::Safe>; -impl<'a, REG> RangeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Frequency range select of 8-16 MHz."] - #[inline(always)] - pub fn freq_16to20mhz(self) -> &'a mut crate::W { - self.variant(Range::Freq16to20mhz) - } - #[doc = "Frequency range select of 16-25 MHz."] - #[inline(always)] - pub fn low_freq(self) -> &'a mut crate::W { - self.variant(Range::LowFreq) - } - #[doc = "Frequency range select of 25-40 MHz."] - #[inline(always)] - pub fn medium_freq(self) -> &'a mut crate::W { - self.variant(Range::MediumFreq) - } - #[doc = "Frequency range select of 40-50 MHz."] - #[inline(always)] - pub fn high_freq(self) -> &'a mut crate::W { - self.variant(Range::HighFreq) - } -} -impl R { - #[doc = "Bit 2 - External Reference Select"] - #[inline(always)] - pub fn erefs(&self) -> ErefsR { - ErefsR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 4:5 - SOSC Range Select"] - #[inline(always)] - pub fn range(&self) -> RangeR { - RangeR::new(((self.bits >> 4) & 3) as u8) - } -} -impl W { - #[doc = "Bit 2 - External Reference Select"] - #[inline(always)] - pub fn erefs(&mut self) -> ErefsW { - ErefsW::new(self, 2) - } - #[doc = "Bits 4:5 - SOSC Range Select"] - #[inline(always)] - pub fn range(&mut self) -> RangeW { - RangeW::new(self, 4) - } -} -#[doc = "SOSC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SosccfgSpec; -impl crate::RegisterSpec for SosccfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sosccfg::R`](R) reader structure"] -impl crate::Readable for SosccfgSpec {} -#[doc = "`write(|w| ..)` method takes [`sosccfg::W`](W) writer structure"] -impl crate::Writable for SosccfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SOSCCFG to value 0"] -impl crate::Resettable for SosccfgSpec {} diff --git a/mcxa276-pac/src/scg0/sosccsr.rs b/mcxa276-pac/src/scg0/sosccsr.rs deleted file mode 100644 index 2736f214e..000000000 --- a/mcxa276-pac/src/scg0/sosccsr.rs +++ /dev/null @@ -1,608 +0,0 @@ -#[doc = "Register `SOSCCSR` reader"] -pub type R = crate::R; -#[doc = "Register `SOSCCSR` writer"] -pub type W = crate::W; -#[doc = "SOSC Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soscen { - #[doc = "0: SOSC is disabled"] - Disabled = 0, - #[doc = "1: SOSC is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soscen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCEN` reader - SOSC Enable"] -pub type SoscenR = crate::BitReader; -impl SoscenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soscen { - match self.bits { - false => Soscen::Disabled, - true => Soscen::Enabled, - } - } - #[doc = "SOSC is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Soscen::Disabled - } - #[doc = "SOSC is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Soscen::Enabled - } -} -#[doc = "Field `SOSCEN` writer - SOSC Enable"] -pub type SoscenW<'a, REG> = crate::BitWriter<'a, REG, Soscen>; -impl<'a, REG> SoscenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SOSC is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Soscen::Disabled) - } - #[doc = "SOSC is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Soscen::Enabled) - } -} -#[doc = "SOSC Stop Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soscsten { - #[doc = "0: SOSC is disabled in Deep Sleep mode"] - Disabled = 0, - #[doc = "1: SOSC is enabled in Deep Sleep mode only if SOSCEN is set"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soscsten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCSTEN` reader - SOSC Stop Enable"] -pub type SoscstenR = crate::BitReader; -impl SoscstenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soscsten { - match self.bits { - false => Soscsten::Disabled, - true => Soscsten::Enabled, - } - } - #[doc = "SOSC is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Soscsten::Disabled - } - #[doc = "SOSC is enabled in Deep Sleep mode only if SOSCEN is set"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Soscsten::Enabled - } -} -#[doc = "Field `SOSCSTEN` writer - SOSC Stop Enable"] -pub type SoscstenW<'a, REG> = crate::BitWriter<'a, REG, Soscsten>; -impl<'a, REG> SoscstenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SOSC is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Soscsten::Disabled) - } - #[doc = "SOSC is enabled in Deep Sleep mode only if SOSCEN is set"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Soscsten::Enabled) - } -} -#[doc = "SOSC Clock Monitor Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sosccm { - #[doc = "0: SOSC Clock Monitor is disabled"] - Disabled = 0, - #[doc = "1: SOSC Clock Monitor is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sosccm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCCM` reader - SOSC Clock Monitor Enable"] -pub type SosccmR = crate::BitReader; -impl SosccmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sosccm { - match self.bits { - false => Sosccm::Disabled, - true => Sosccm::Enabled, - } - } - #[doc = "SOSC Clock Monitor is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Sosccm::Disabled - } - #[doc = "SOSC Clock Monitor is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Sosccm::Enabled - } -} -#[doc = "Field `SOSCCM` writer - SOSC Clock Monitor Enable"] -pub type SosccmW<'a, REG> = crate::BitWriter<'a, REG, Sosccm>; -impl<'a, REG> SosccmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SOSC Clock Monitor is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Sosccm::Disabled) - } - #[doc = "SOSC Clock Monitor is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Sosccm::Enabled) - } -} -#[doc = "SOSC Clock Monitor Reset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sosccmre { - #[doc = "0: Clock monitor generates an interrupt when an error is detected"] - GenerateInterrupt = 0, - #[doc = "1: Clock monitor generates a reset when an error is detected"] - GenerateReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sosccmre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCCMRE` reader - SOSC Clock Monitor Reset Enable"] -pub type SosccmreR = crate::BitReader; -impl SosccmreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sosccmre { - match self.bits { - false => Sosccmre::GenerateInterrupt, - true => Sosccmre::GenerateReset, - } - } - #[doc = "Clock monitor generates an interrupt when an error is detected"] - #[inline(always)] - pub fn is_generate_interrupt(&self) -> bool { - *self == Sosccmre::GenerateInterrupt - } - #[doc = "Clock monitor generates a reset when an error is detected"] - #[inline(always)] - pub fn is_generate_reset(&self) -> bool { - *self == Sosccmre::GenerateReset - } -} -#[doc = "Field `SOSCCMRE` writer - SOSC Clock Monitor Reset Enable"] -pub type SosccmreW<'a, REG> = crate::BitWriter<'a, REG, Sosccmre>; -impl<'a, REG> SosccmreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Clock monitor generates an interrupt when an error is detected"] - #[inline(always)] - pub fn generate_interrupt(self) -> &'a mut crate::W { - self.variant(Sosccmre::GenerateInterrupt) - } - #[doc = "Clock monitor generates a reset when an error is detected"] - #[inline(always)] - pub fn generate_reset(self) -> &'a mut crate::W { - self.variant(Sosccmre::GenerateReset) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: This Control Status Register can be written"] - WriteEnabled = 0, - #[doc = "1: This Control Status Register cannot be written"] - WriteDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::WriteEnabled, - true => Lk::WriteDisabled, - } - } - #[doc = "This Control Status Register can be written"] - #[inline(always)] - pub fn is_write_enabled(&self) -> bool { - *self == Lk::WriteEnabled - } - #[doc = "This Control Status Register cannot be written"] - #[inline(always)] - pub fn is_write_disabled(&self) -> bool { - *self == Lk::WriteDisabled - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This Control Status Register can be written"] - #[inline(always)] - pub fn write_enabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteEnabled) - } - #[doc = "This Control Status Register cannot be written"] - #[inline(always)] - pub fn write_disabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteDisabled) - } -} -#[doc = "SOSC Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soscvld { - #[doc = "0: SOSC is not enabled or clock is not valid"] - Disabled = 0, - #[doc = "1: SOSC is enabled and output clock is valid"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soscvld) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCVLD` reader - SOSC Valid"] -pub type SoscvldR = crate::BitReader; -impl SoscvldR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soscvld { - match self.bits { - false => Soscvld::Disabled, - true => Soscvld::Enabled, - } - } - #[doc = "SOSC is not enabled or clock is not valid"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Soscvld::Disabled - } - #[doc = "SOSC is enabled and output clock is valid"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Soscvld::Enabled - } -} -#[doc = "SOSC Selected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soscsel { - #[doc = "0: SOSC is not the system clock source"] - NotSosc = 0, - #[doc = "1: SOSC is the system clock source"] - Sosc = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soscsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCSEL` reader - SOSC Selected"] -pub type SoscselR = crate::BitReader; -impl SoscselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soscsel { - match self.bits { - false => Soscsel::NotSosc, - true => Soscsel::Sosc, - } - } - #[doc = "SOSC is not the system clock source"] - #[inline(always)] - pub fn is_not_sosc(&self) -> bool { - *self == Soscsel::NotSosc - } - #[doc = "SOSC is the system clock source"] - #[inline(always)] - pub fn is_sosc(&self) -> bool { - *self == Soscsel::Sosc - } -} -#[doc = "SOSC Clock Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Soscerr { - #[doc = "0: SOSC Clock Monitor is disabled or has not detected an error"] - DisabledOrNoError = 0, - #[doc = "1: SOSC Clock Monitor is enabled and detected an error"] - EnabledAndError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Soscerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCERR` reader - SOSC Clock Error"] -pub type SoscerrR = crate::BitReader; -impl SoscerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Soscerr { - match self.bits { - false => Soscerr::DisabledOrNoError, - true => Soscerr::EnabledAndError, - } - } - #[doc = "SOSC Clock Monitor is disabled or has not detected an error"] - #[inline(always)] - pub fn is_disabled_or_no_error(&self) -> bool { - *self == Soscerr::DisabledOrNoError - } - #[doc = "SOSC Clock Monitor is enabled and detected an error"] - #[inline(always)] - pub fn is_enabled_and_error(&self) -> bool { - *self == Soscerr::EnabledAndError - } -} -#[doc = "Field `SOSCERR` writer - SOSC Clock Error"] -pub type SoscerrW<'a, REG> = crate::BitWriter1C<'a, REG, Soscerr>; -impl<'a, REG> SoscerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SOSC Clock Monitor is disabled or has not detected an error"] - #[inline(always)] - pub fn disabled_or_no_error(self) -> &'a mut crate::W { - self.variant(Soscerr::DisabledOrNoError) - } - #[doc = "SOSC Clock Monitor is enabled and detected an error"] - #[inline(always)] - pub fn enabled_and_error(self) -> &'a mut crate::W { - self.variant(Soscerr::EnabledAndError) - } -} -#[doc = "SOSC Valid Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SoscvldIe { - #[doc = "0: SOSCVLD interrupt is not enabled"] - NotSosc = 0, - #[doc = "1: SOSCVLD interrupt is enabled"] - Sosc = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SoscvldIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSCVLD_IE` reader - SOSC Valid Interrupt Enable"] -pub type SoscvldIeR = crate::BitReader; -impl SoscvldIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SoscvldIe { - match self.bits { - false => SoscvldIe::NotSosc, - true => SoscvldIe::Sosc, - } - } - #[doc = "SOSCVLD interrupt is not enabled"] - #[inline(always)] - pub fn is_not_sosc(&self) -> bool { - *self == SoscvldIe::NotSosc - } - #[doc = "SOSCVLD interrupt is enabled"] - #[inline(always)] - pub fn is_sosc(&self) -> bool { - *self == SoscvldIe::Sosc - } -} -#[doc = "Field `SOSCVLD_IE` writer - SOSC Valid Interrupt Enable"] -pub type SoscvldIeW<'a, REG> = crate::BitWriter<'a, REG, SoscvldIe>; -impl<'a, REG> SoscvldIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SOSCVLD interrupt is not enabled"] - #[inline(always)] - pub fn not_sosc(self) -> &'a mut crate::W { - self.variant(SoscvldIe::NotSosc) - } - #[doc = "SOSCVLD interrupt is enabled"] - #[inline(always)] - pub fn sosc(self) -> &'a mut crate::W { - self.variant(SoscvldIe::Sosc) - } -} -#[doc = "SOSC clock safety enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SoscSafeEn { - #[doc = "0: SOSC clock safety is disabled"] - Disable = 0, - #[doc = "1: SOSC clock safety is enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SoscSafeEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOSC_SAFE_EN` reader - SOSC clock safety enable"] -pub type SoscSafeEnR = crate::BitReader; -impl SoscSafeEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SoscSafeEn { - match self.bits { - false => SoscSafeEn::Disable, - true => SoscSafeEn::Enable, - } - } - #[doc = "SOSC clock safety is disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SoscSafeEn::Disable - } - #[doc = "SOSC clock safety is enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SoscSafeEn::Enable - } -} -#[doc = "Field `SOSC_SAFE_EN` writer - SOSC clock safety enable"] -pub type SoscSafeEnW<'a, REG> = crate::BitWriter<'a, REG, SoscSafeEn>; -impl<'a, REG> SoscSafeEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SOSC clock safety is disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SoscSafeEn::Disable) - } - #[doc = "SOSC clock safety is enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SoscSafeEn::Enable) - } -} -impl R { - #[doc = "Bit 0 - SOSC Enable"] - #[inline(always)] - pub fn soscen(&self) -> SoscenR { - SoscenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SOSC Stop Enable"] - #[inline(always)] - pub fn soscsten(&self) -> SoscstenR { - SoscstenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 16 - SOSC Clock Monitor Enable"] - #[inline(always)] - pub fn sosccm(&self) -> SosccmR { - SosccmR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - SOSC Clock Monitor Reset Enable"] - #[inline(always)] - pub fn sosccmre(&self) -> SosccmreR { - SosccmreR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - SOSC Valid"] - #[inline(always)] - pub fn soscvld(&self) -> SoscvldR { - SoscvldR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - SOSC Selected"] - #[inline(always)] - pub fn soscsel(&self) -> SoscselR { - SoscselR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - SOSC Clock Error"] - #[inline(always)] - pub fn soscerr(&self) -> SoscerrR { - SoscerrR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 30 - SOSC Valid Interrupt Enable"] - #[inline(always)] - pub fn soscvld_ie(&self) -> SoscvldIeR { - SoscvldIeR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - SOSC clock safety enable"] - #[inline(always)] - pub fn sosc_safe_en(&self) -> SoscSafeEnR { - SoscSafeEnR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - SOSC Enable"] - #[inline(always)] - pub fn soscen(&mut self) -> SoscenW { - SoscenW::new(self, 0) - } - #[doc = "Bit 1 - SOSC Stop Enable"] - #[inline(always)] - pub fn soscsten(&mut self) -> SoscstenW { - SoscstenW::new(self, 1) - } - #[doc = "Bit 16 - SOSC Clock Monitor Enable"] - #[inline(always)] - pub fn sosccm(&mut self) -> SosccmW { - SosccmW::new(self, 16) - } - #[doc = "Bit 17 - SOSC Clock Monitor Reset Enable"] - #[inline(always)] - pub fn sosccmre(&mut self) -> SosccmreW { - SosccmreW::new(self, 17) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 23) - } - #[doc = "Bit 26 - SOSC Clock Error"] - #[inline(always)] - pub fn soscerr(&mut self) -> SoscerrW { - SoscerrW::new(self, 26) - } - #[doc = "Bit 30 - SOSC Valid Interrupt Enable"] - #[inline(always)] - pub fn soscvld_ie(&mut self) -> SoscvldIeW { - SoscvldIeW::new(self, 30) - } - #[doc = "Bit 31 - SOSC clock safety enable"] - #[inline(always)] - pub fn sosc_safe_en(&mut self) -> SoscSafeEnW { - SoscSafeEnW::new(self, 31) - } -} -#[doc = "SOSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sosccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sosccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SosccsrSpec; -impl crate::RegisterSpec for SosccsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sosccsr::R`](R) reader structure"] -impl crate::Readable for SosccsrSpec {} -#[doc = "`write(|w| ..)` method takes [`sosccsr::W`](W) writer structure"] -impl crate::Writable for SosccsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; -} -#[doc = "`reset()` method sets SOSCCSR to value 0"] -impl crate::Resettable for SosccsrSpec {} diff --git a/mcxa276-pac/src/scg0/spllcsr.rs b/mcxa276-pac/src/scg0/spllcsr.rs deleted file mode 100644 index 96eb57a3b..000000000 --- a/mcxa276-pac/src/scg0/spllcsr.rs +++ /dev/null @@ -1,671 +0,0 @@ -#[doc = "Register `SPLLCSR` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLCSR` writer"] -pub type W = crate::W; -#[doc = "SPLL Power Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllpwren { - #[doc = "0: SPLL clock is powered off"] - Disabled = 0, - #[doc = "1: SPLL clock is powered on"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllpwren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLPWREN` reader - SPLL Power Enable"] -pub type SpllpwrenR = crate::BitReader; -impl SpllpwrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllpwren { - match self.bits { - false => Spllpwren::Disabled, - true => Spllpwren::Enabled, - } - } - #[doc = "SPLL clock is powered off"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Spllpwren::Disabled - } - #[doc = "SPLL clock is powered on"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Spllpwren::Enabled - } -} -#[doc = "Field `SPLLPWREN` writer - SPLL Power Enable"] -pub type SpllpwrenW<'a, REG> = crate::BitWriter<'a, REG, Spllpwren>; -impl<'a, REG> SpllpwrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SPLL clock is powered off"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Spllpwren::Disabled) - } - #[doc = "SPLL clock is powered on"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Spllpwren::Enabled) - } -} -#[doc = "SPLL Clock Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllclken { - #[doc = "0: SPLL clock is disabled"] - Disabled = 0, - #[doc = "1: SPLL clock is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllclken) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLCLKEN` reader - SPLL Clock Enable"] -pub type SpllclkenR = crate::BitReader; -impl SpllclkenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllclken { - match self.bits { - false => Spllclken::Disabled, - true => Spllclken::Enabled, - } - } - #[doc = "SPLL clock is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Spllclken::Disabled - } - #[doc = "SPLL clock is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Spllclken::Enabled - } -} -#[doc = "Field `SPLLCLKEN` writer - SPLL Clock Enable"] -pub type SpllclkenW<'a, REG> = crate::BitWriter<'a, REG, Spllclken>; -impl<'a, REG> SpllclkenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SPLL clock is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Spllclken::Disabled) - } - #[doc = "SPLL clock is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Spllclken::Enabled) - } -} -#[doc = "SPLL Stop Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllsten { - #[doc = "0: SPLL is disabled in Deep Sleep mode"] - DisabledInStop = 0, - #[doc = "1: SPLL is enabled in Deep Sleep mode"] - EnabledInStop = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllsten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLSTEN` reader - SPLL Stop Enable"] -pub type SpllstenR = crate::BitReader; -impl SpllstenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllsten { - match self.bits { - false => Spllsten::DisabledInStop, - true => Spllsten::EnabledInStop, - } - } - #[doc = "SPLL is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn is_disabled_in_stop(&self) -> bool { - *self == Spllsten::DisabledInStop - } - #[doc = "SPLL is enabled in Deep Sleep mode"] - #[inline(always)] - pub fn is_enabled_in_stop(&self) -> bool { - *self == Spllsten::EnabledInStop - } -} -#[doc = "Field `SPLLSTEN` writer - SPLL Stop Enable"] -pub type SpllstenW<'a, REG> = crate::BitWriter<'a, REG, Spllsten>; -impl<'a, REG> SpllstenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SPLL is disabled in Deep Sleep mode"] - #[inline(always)] - pub fn disabled_in_stop(self) -> &'a mut crate::W { - self.variant(Spllsten::DisabledInStop) - } - #[doc = "SPLL is enabled in Deep Sleep mode"] - #[inline(always)] - pub fn enabled_in_stop(self) -> &'a mut crate::W { - self.variant(Spllsten::EnabledInStop) - } -} -#[doc = "Free running mode clock stable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FrmClockstable { - #[doc = "0: Free running mode clock stable is disabled"] - Disabled = 0, - #[doc = "1: Free running mode clock stable is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FrmClockstable) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRM_CLOCKSTABLE` reader - Free running mode clock stable"] -pub type FrmClockstableR = crate::BitReader; -impl FrmClockstableR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FrmClockstable { - match self.bits { - false => FrmClockstable::Disabled, - true => FrmClockstable::Enabled, - } - } - #[doc = "Free running mode clock stable is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == FrmClockstable::Disabled - } - #[doc = "Free running mode clock stable is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == FrmClockstable::Enabled - } -} -#[doc = "Field `FRM_CLOCKSTABLE` writer - Free running mode clock stable"] -pub type FrmClockstableW<'a, REG> = crate::BitWriter<'a, REG, FrmClockstable>; -impl<'a, REG> FrmClockstableW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Free running mode clock stable is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(FrmClockstable::Disabled) - } - #[doc = "Free running mode clock stable is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(FrmClockstable::Enabled) - } -} -#[doc = "SPLL Clock Monitor\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllcm { - #[doc = "0: SPLL Clock Monitor is disabled"] - Disabled = 0, - #[doc = "1: SPLL Clock Monitor is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllcm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLCM` reader - SPLL Clock Monitor"] -pub type SpllcmR = crate::BitReader; -impl SpllcmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllcm { - match self.bits { - false => Spllcm::Disabled, - true => Spllcm::Enabled, - } - } - #[doc = "SPLL Clock Monitor is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Spllcm::Disabled - } - #[doc = "SPLL Clock Monitor is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Spllcm::Enabled - } -} -#[doc = "Field `SPLLCM` writer - SPLL Clock Monitor"] -pub type SpllcmW<'a, REG> = crate::BitWriter<'a, REG, Spllcm>; -impl<'a, REG> SpllcmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SPLL Clock Monitor is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Spllcm::Disabled) - } - #[doc = "SPLL Clock Monitor is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Spllcm::Enabled) - } -} -#[doc = "SPLL Clock Monitor Reset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllcmre { - #[doc = "0: Clock monitor generates an interrupt when an error is detected"] - GenerateInterrupt = 0, - #[doc = "1: Clock monitor generates a reset when an error is detected"] - GenerateReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllcmre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLCMRE` reader - SPLL Clock Monitor Reset Enable"] -pub type SpllcmreR = crate::BitReader; -impl SpllcmreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllcmre { - match self.bits { - false => Spllcmre::GenerateInterrupt, - true => Spllcmre::GenerateReset, - } - } - #[doc = "Clock monitor generates an interrupt when an error is detected"] - #[inline(always)] - pub fn is_generate_interrupt(&self) -> bool { - *self == Spllcmre::GenerateInterrupt - } - #[doc = "Clock monitor generates a reset when an error is detected"] - #[inline(always)] - pub fn is_generate_reset(&self) -> bool { - *self == Spllcmre::GenerateReset - } -} -#[doc = "Field `SPLLCMRE` writer - SPLL Clock Monitor Reset Enable"] -pub type SpllcmreW<'a, REG> = crate::BitWriter<'a, REG, Spllcmre>; -impl<'a, REG> SpllcmreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Clock monitor generates an interrupt when an error is detected"] - #[inline(always)] - pub fn generate_interrupt(self) -> &'a mut crate::W { - self.variant(Spllcmre::GenerateInterrupt) - } - #[doc = "Clock monitor generates a reset when an error is detected"] - #[inline(always)] - pub fn generate_reset(self) -> &'a mut crate::W { - self.variant(Spllcmre::GenerateReset) - } -} -#[doc = "Lock Register\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lk { - #[doc = "0: Control Status Register can be written"] - WriteEnabled = 0, - #[doc = "1: Control Status Register cannot be written"] - WriteDisabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LK` reader - Lock Register"] -pub type LkR = crate::BitReader; -impl LkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lk { - match self.bits { - false => Lk::WriteEnabled, - true => Lk::WriteDisabled, - } - } - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn is_write_enabled(&self) -> bool { - *self == Lk::WriteEnabled - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn is_write_disabled(&self) -> bool { - *self == Lk::WriteDisabled - } -} -#[doc = "Field `LK` writer - Lock Register"] -pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>; -impl<'a, REG> LkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Control Status Register can be written"] - #[inline(always)] - pub fn write_enabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteEnabled) - } - #[doc = "Control Status Register cannot be written"] - #[inline(always)] - pub fn write_disabled(self) -> &'a mut crate::W { - self.variant(Lk::WriteDisabled) - } -} -#[doc = "SPLL LOCK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SpllLock { - #[doc = "0: SPLL is not powered on or not locked"] - DisabledOrNotValid = 0, - #[doc = "1: SPLL is locked"] - EnabledAndValid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SpllLock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLL_LOCK` reader - SPLL LOCK"] -pub type SpllLockR = crate::BitReader; -impl SpllLockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SpllLock { - match self.bits { - false => SpllLock::DisabledOrNotValid, - true => SpllLock::EnabledAndValid, - } - } - #[doc = "SPLL is not powered on or not locked"] - #[inline(always)] - pub fn is_disabled_or_not_valid(&self) -> bool { - *self == SpllLock::DisabledOrNotValid - } - #[doc = "SPLL is locked"] - #[inline(always)] - pub fn is_enabled_and_valid(&self) -> bool { - *self == SpllLock::EnabledAndValid - } -} -#[doc = "SPLL Selected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllsel { - #[doc = "0: SPLL is not the system clock source"] - NotSpll = 0, - #[doc = "1: SPLL is the system clock source"] - Spll = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLSEL` reader - SPLL Selected"] -pub type SpllselR = crate::BitReader; -impl SpllselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllsel { - match self.bits { - false => Spllsel::NotSpll, - true => Spllsel::Spll, - } - } - #[doc = "SPLL is not the system clock source"] - #[inline(always)] - pub fn is_not_spll(&self) -> bool { - *self == Spllsel::NotSpll - } - #[doc = "SPLL is the system clock source"] - #[inline(always)] - pub fn is_spll(&self) -> bool { - *self == Spllsel::Spll - } -} -#[doc = "SPLL Clock Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Spllerr { - #[doc = "0: SPLL Clock Monitor is disabled or has not detected an error"] - DisabledOrNoError = 0, - #[doc = "1: SPLL Clock Monitor is enabled and detected an error"] - EnabledAndError = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Spllerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLLERR` reader - SPLL Clock Error"] -pub type SpllerrR = crate::BitReader; -impl SpllerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Spllerr { - match self.bits { - false => Spllerr::DisabledOrNoError, - true => Spllerr::EnabledAndError, - } - } - #[doc = "SPLL Clock Monitor is disabled or has not detected an error"] - #[inline(always)] - pub fn is_disabled_or_no_error(&self) -> bool { - *self == Spllerr::DisabledOrNoError - } - #[doc = "SPLL Clock Monitor is enabled and detected an error"] - #[inline(always)] - pub fn is_enabled_and_error(&self) -> bool { - *self == Spllerr::EnabledAndError - } -} -#[doc = "Field `SPLLERR` writer - SPLL Clock Error"] -pub type SpllerrW<'a, REG> = crate::BitWriter1C<'a, REG, Spllerr>; -impl<'a, REG> SpllerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SPLL Clock Monitor is disabled or has not detected an error"] - #[inline(always)] - pub fn disabled_or_no_error(self) -> &'a mut crate::W { - self.variant(Spllerr::DisabledOrNoError) - } - #[doc = "SPLL Clock Monitor is enabled and detected an error"] - #[inline(always)] - pub fn enabled_and_error(self) -> &'a mut crate::W { - self.variant(Spllerr::EnabledAndError) - } -} -#[doc = "SPLL LOCK Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SpllLockIe { - #[doc = "0: SPLL_LOCK interrupt is not enabled"] - NotSpll = 0, - #[doc = "1: SPLL_LOCK interrupt is enabled"] - Spll = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SpllLockIe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPLL_LOCK_IE` reader - SPLL LOCK Interrupt Enable"] -pub type SpllLockIeR = crate::BitReader; -impl SpllLockIeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SpllLockIe { - match self.bits { - false => SpllLockIe::NotSpll, - true => SpllLockIe::Spll, - } - } - #[doc = "SPLL_LOCK interrupt is not enabled"] - #[inline(always)] - pub fn is_not_spll(&self) -> bool { - *self == SpllLockIe::NotSpll - } - #[doc = "SPLL_LOCK interrupt is enabled"] - #[inline(always)] - pub fn is_spll(&self) -> bool { - *self == SpllLockIe::Spll - } -} -#[doc = "Field `SPLL_LOCK_IE` writer - SPLL LOCK Interrupt Enable"] -pub type SpllLockIeW<'a, REG> = crate::BitWriter<'a, REG, SpllLockIe>; -impl<'a, REG> SpllLockIeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SPLL_LOCK interrupt is not enabled"] - #[inline(always)] - pub fn not_spll(self) -> &'a mut crate::W { - self.variant(SpllLockIe::NotSpll) - } - #[doc = "SPLL_LOCK interrupt is enabled"] - #[inline(always)] - pub fn spll(self) -> &'a mut crate::W { - self.variant(SpllLockIe::Spll) - } -} -impl R { - #[doc = "Bit 0 - SPLL Power Enable"] - #[inline(always)] - pub fn spllpwren(&self) -> SpllpwrenR { - SpllpwrenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SPLL Clock Enable"] - #[inline(always)] - pub fn spllclken(&self) -> SpllclkenR { - SpllclkenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - SPLL Stop Enable"] - #[inline(always)] - pub fn spllsten(&self) -> SpllstenR { - SpllstenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Free running mode clock stable"] - #[inline(always)] - pub fn frm_clockstable(&self) -> FrmClockstableR { - FrmClockstableR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 16 - SPLL Clock Monitor"] - #[inline(always)] - pub fn spllcm(&self) -> SpllcmR { - SpllcmR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - SPLL Clock Monitor Reset Enable"] - #[inline(always)] - pub fn spllcmre(&self) -> SpllcmreR { - SpllcmreR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&self) -> LkR { - LkR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - SPLL LOCK"] - #[inline(always)] - pub fn spll_lock(&self) -> SpllLockR { - SpllLockR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - SPLL Selected"] - #[inline(always)] - pub fn spllsel(&self) -> SpllselR { - SpllselR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - SPLL Clock Error"] - #[inline(always)] - pub fn spllerr(&self) -> SpllerrR { - SpllerrR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 30 - SPLL LOCK Interrupt Enable"] - #[inline(always)] - pub fn spll_lock_ie(&self) -> SpllLockIeR { - SpllLockIeR::new(((self.bits >> 30) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - SPLL Power Enable"] - #[inline(always)] - pub fn spllpwren(&mut self) -> SpllpwrenW { - SpllpwrenW::new(self, 0) - } - #[doc = "Bit 1 - SPLL Clock Enable"] - #[inline(always)] - pub fn spllclken(&mut self) -> SpllclkenW { - SpllclkenW::new(self, 1) - } - #[doc = "Bit 2 - SPLL Stop Enable"] - #[inline(always)] - pub fn spllsten(&mut self) -> SpllstenW { - SpllstenW::new(self, 2) - } - #[doc = "Bit 3 - Free running mode clock stable"] - #[inline(always)] - pub fn frm_clockstable(&mut self) -> FrmClockstableW { - FrmClockstableW::new(self, 3) - } - #[doc = "Bit 16 - SPLL Clock Monitor"] - #[inline(always)] - pub fn spllcm(&mut self) -> SpllcmW { - SpllcmW::new(self, 16) - } - #[doc = "Bit 17 - SPLL Clock Monitor Reset Enable"] - #[inline(always)] - pub fn spllcmre(&mut self) -> SpllcmreW { - SpllcmreW::new(self, 17) - } - #[doc = "Bit 23 - Lock Register"] - #[inline(always)] - pub fn lk(&mut self) -> LkW { - LkW::new(self, 23) - } - #[doc = "Bit 26 - SPLL Clock Error"] - #[inline(always)] - pub fn spllerr(&mut self) -> SpllerrW { - SpllerrW::new(self, 26) - } - #[doc = "Bit 30 - SPLL LOCK Interrupt Enable"] - #[inline(always)] - pub fn spll_lock_ie(&mut self) -> SpllLockIeW { - SpllLockIeW::new(self, 30) - } -} -#[doc = "SPLL Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpllcsrSpec; -impl crate::RegisterSpec for SpllcsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllcsr::R`](R) reader structure"] -impl crate::Readable for SpllcsrSpec {} -#[doc = "`write(|w| ..)` method takes [`spllcsr::W`](W) writer structure"] -impl crate::Writable for SpllcsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000; -} -#[doc = "`reset()` method sets SPLLCSR to value 0"] -impl crate::Resettable for SpllcsrSpec {} diff --git a/mcxa276-pac/src/scg0/spllctrl.rs b/mcxa276-pac/src/scg0/spllctrl.rs deleted file mode 100644 index 7d0a8271e..000000000 --- a/mcxa276-pac/src/scg0/spllctrl.rs +++ /dev/null @@ -1,537 +0,0 @@ -#[doc = "Register `SPLLCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLCTRL` writer"] -pub type W = crate::W; -#[doc = "Field `SELR` reader - Bandwidth select R (resistor) value."] -pub type SelrR = crate::FieldReader; -#[doc = "Field `SELR` writer - Bandwidth select R (resistor) value."] -pub type SelrW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `SELI` reader - Bandwidth select I (interation) value."] -pub type SeliR = crate::FieldReader; -#[doc = "Field `SELI` writer - Bandwidth select I (interation) value."] -pub type SeliW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `SELP` reader - Bandwidth select P (proportional) value."] -pub type SelpR = crate::FieldReader; -#[doc = "Field `SELP` writer - Bandwidth select P (proportional) value."] -pub type SelpW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Bypass of the divide-by-2 divider\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bypasspostdiv2 { - #[doc = "0: Use the divide-by-2 divider in the post-divider."] - NotBypassed = 0, - #[doc = "1: Bypass of the divide-by-2 divider in the post-divider."] - Bypassed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bypasspostdiv2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BYPASSPOSTDIV2` reader - Bypass of the divide-by-2 divider"] -pub type Bypasspostdiv2R = crate::BitReader; -impl Bypasspostdiv2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bypasspostdiv2 { - match self.bits { - false => Bypasspostdiv2::NotBypassed, - true => Bypasspostdiv2::Bypassed, - } - } - #[doc = "Use the divide-by-2 divider in the post-divider."] - #[inline(always)] - pub fn is_not_bypassed(&self) -> bool { - *self == Bypasspostdiv2::NotBypassed - } - #[doc = "Bypass of the divide-by-2 divider in the post-divider."] - #[inline(always)] - pub fn is_bypassed(&self) -> bool { - *self == Bypasspostdiv2::Bypassed - } -} -#[doc = "Field `BYPASSPOSTDIV2` writer - Bypass of the divide-by-2 divider"] -pub type Bypasspostdiv2W<'a, REG> = crate::BitWriter<'a, REG, Bypasspostdiv2>; -impl<'a, REG> Bypasspostdiv2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Use the divide-by-2 divider in the post-divider."] - #[inline(always)] - pub fn not_bypassed(self) -> &'a mut crate::W { - self.variant(Bypasspostdiv2::NotBypassed) - } - #[doc = "Bypass of the divide-by-2 divider in the post-divider."] - #[inline(always)] - pub fn bypassed(self) -> &'a mut crate::W { - self.variant(Bypasspostdiv2::Bypassed) - } -} -#[doc = "Up Limiter.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Limupoff { - #[doc = "0: Application set to non Spectrum and Fractional applications."] - Disabled = 0, - #[doc = "1: Application set to Spectrum and Fractional applications."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Limupoff) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LIMUPOFF` reader - Up Limiter."] -pub type LimupoffR = crate::BitReader; -impl LimupoffR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Limupoff { - match self.bits { - false => Limupoff::Disabled, - true => Limupoff::Enabled, - } - } - #[doc = "Application set to non Spectrum and Fractional applications."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Limupoff::Disabled - } - #[doc = "Application set to Spectrum and Fractional applications."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Limupoff::Enabled - } -} -#[doc = "Field `LIMUPOFF` writer - Up Limiter."] -pub type LimupoffW<'a, REG> = crate::BitWriter<'a, REG, Limupoff>; -impl<'a, REG> LimupoffW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Application set to non Spectrum and Fractional applications."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Limupoff::Disabled) - } - #[doc = "Application set to Spectrum and Fractional applications."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Limupoff::Enabled) - } -} -#[doc = "Control of the bandwidth of the PLL.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Banddirect { - #[doc = "0: The bandwidth is changed synchronously with the feedback-divider"] - Disabled = 0, - #[doc = "1: Modifies the bandwidth of the PLL directly"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Banddirect) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BANDDIRECT` reader - Control of the bandwidth of the PLL."] -pub type BanddirectR = crate::BitReader; -impl BanddirectR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Banddirect { - match self.bits { - false => Banddirect::Disabled, - true => Banddirect::Enabled, - } - } - #[doc = "The bandwidth is changed synchronously with the feedback-divider"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Banddirect::Disabled - } - #[doc = "Modifies the bandwidth of the PLL directly"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Banddirect::Enabled - } -} -#[doc = "Field `BANDDIRECT` writer - Control of the bandwidth of the PLL."] -pub type BanddirectW<'a, REG> = crate::BitWriter<'a, REG, Banddirect>; -impl<'a, REG> BanddirectW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The bandwidth is changed synchronously with the feedback-divider"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Banddirect::Disabled) - } - #[doc = "Modifies the bandwidth of the PLL directly"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Banddirect::Enabled) - } -} -#[doc = "Bypass of the pre-divider.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bypassprediv { - #[doc = "0: Use the pre-divider"] - Disabled = 0, - #[doc = "1: Bypass of the pre-divider"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bypassprediv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BYPASSPREDIV` reader - Bypass of the pre-divider."] -pub type BypasspredivR = crate::BitReader; -impl BypasspredivR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bypassprediv { - match self.bits { - false => Bypassprediv::Disabled, - true => Bypassprediv::Enabled, - } - } - #[doc = "Use the pre-divider"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Bypassprediv::Disabled - } - #[doc = "Bypass of the pre-divider"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Bypassprediv::Enabled - } -} -#[doc = "Field `BYPASSPREDIV` writer - Bypass of the pre-divider."] -pub type BypasspredivW<'a, REG> = crate::BitWriter<'a, REG, Bypassprediv>; -impl<'a, REG> BypasspredivW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Use the pre-divider"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Bypassprediv::Disabled) - } - #[doc = "Bypass of the pre-divider"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Bypassprediv::Enabled) - } -} -#[doc = "Bypass of the post-divider.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bypasspostdiv { - #[doc = "0: Use the post-divider"] - Disabled = 0, - #[doc = "1: Bypass of the post-divider"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bypasspostdiv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BYPASSPOSTDIV` reader - Bypass of the post-divider."] -pub type BypasspostdivR = crate::BitReader; -impl BypasspostdivR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bypasspostdiv { - match self.bits { - false => Bypasspostdiv::Disabled, - true => Bypasspostdiv::Enabled, - } - } - #[doc = "Use the post-divider"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Bypasspostdiv::Disabled - } - #[doc = "Bypass of the post-divider"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Bypasspostdiv::Enabled - } -} -#[doc = "Field `BYPASSPOSTDIV` writer - Bypass of the post-divider."] -pub type BypasspostdivW<'a, REG> = crate::BitWriter<'a, REG, Bypasspostdiv>; -impl<'a, REG> BypasspostdivW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Use the post-divider"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Bypasspostdiv::Disabled) - } - #[doc = "Bypass of the post-divider"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Bypasspostdiv::Enabled) - } -} -#[doc = "Free Running Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frm { - #[doc = "0: Free running mode disabled"] - Disabled = 0, - #[doc = "1: Free running mode enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRM` reader - Free Running Mode Enable"] -pub type FrmR = crate::BitReader; -impl FrmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frm { - match self.bits { - false => Frm::Disabled, - true => Frm::Enabled, - } - } - #[doc = "Free running mode disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Frm::Disabled - } - #[doc = "Free running mode enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Frm::Enabled - } -} -#[doc = "Field `FRM` writer - Free Running Mode Enable"] -pub type FrmW<'a, REG> = crate::BitWriter<'a, REG, Frm>; -impl<'a, REG> FrmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Free running mode disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Frm::Disabled) - } - #[doc = "Free running mode enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Frm::Enabled) - } -} -#[doc = "Clock Source\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Source { - #[doc = "0: SOSC"] - Sosc = 0, - #[doc = "1: FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."] - Firc = 1, - #[doc = "2: ROSC"] - Rsvd = 2, - #[doc = "3: SIRC 12 MHz clock"] - Sirc = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Source) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Source { - type Ux = u8; -} -impl crate::IsEnum for Source {} -#[doc = "Field `SOURCE` reader - Clock Source"] -pub type SourceR = crate::FieldReader; -impl SourceR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Source { - match self.bits { - 0 => Source::Sosc, - 1 => Source::Firc, - 2 => Source::Rsvd, - 3 => Source::Sirc, - _ => unreachable!(), - } - } - #[doc = "SOSC"] - #[inline(always)] - pub fn is_sosc(&self) -> bool { - *self == Source::Sosc - } - #[doc = "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."] - #[inline(always)] - pub fn is_firc(&self) -> bool { - *self == Source::Firc - } - #[doc = "ROSC"] - #[inline(always)] - pub fn is_rsvd(&self) -> bool { - *self == Source::Rsvd - } - #[doc = "SIRC 12 MHz clock"] - #[inline(always)] - pub fn is_sirc(&self) -> bool { - *self == Source::Sirc - } -} -#[doc = "Field `SOURCE` writer - Clock Source"] -pub type SourceW<'a, REG> = crate::FieldWriter<'a, REG, 2, Source, crate::Safe>; -impl<'a, REG> SourceW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "SOSC"] - #[inline(always)] - pub fn sosc(self) -> &'a mut crate::W { - self.variant(Source::Sosc) - } - #[doc = "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."] - #[inline(always)] - pub fn firc(self) -> &'a mut crate::W { - self.variant(Source::Firc) - } - #[doc = "ROSC"] - #[inline(always)] - pub fn rsvd(self) -> &'a mut crate::W { - self.variant(Source::Rsvd) - } - #[doc = "SIRC 12 MHz clock"] - #[inline(always)] - pub fn sirc(self) -> &'a mut crate::W { - self.variant(Source::Sirc) - } -} -impl R { - #[doc = "Bits 0:3 - Bandwidth select R (resistor) value."] - #[inline(always)] - pub fn selr(&self) -> SelrR { - SelrR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:9 - Bandwidth select I (interation) value."] - #[inline(always)] - pub fn seli(&self) -> SeliR { - SeliR::new(((self.bits >> 4) & 0x3f) as u8) - } - #[doc = "Bits 10:14 - Bandwidth select P (proportional) value."] - #[inline(always)] - pub fn selp(&self) -> SelpR { - SelpR::new(((self.bits >> 10) & 0x1f) as u8) - } - #[doc = "Bit 16 - Bypass of the divide-by-2 divider"] - #[inline(always)] - pub fn bypasspostdiv2(&self) -> Bypasspostdiv2R { - Bypasspostdiv2R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Up Limiter."] - #[inline(always)] - pub fn limupoff(&self) -> LimupoffR { - LimupoffR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Control of the bandwidth of the PLL."] - #[inline(always)] - pub fn banddirect(&self) -> BanddirectR { - BanddirectR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Bypass of the pre-divider."] - #[inline(always)] - pub fn bypassprediv(&self) -> BypasspredivR { - BypasspredivR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Bypass of the post-divider."] - #[inline(always)] - pub fn bypasspostdiv(&self) -> BypasspostdivR { - BypasspostdivR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 22 - Free Running Mode Enable"] - #[inline(always)] - pub fn frm(&self) -> FrmR { - FrmR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bits 25:26 - Clock Source"] - #[inline(always)] - pub fn source(&self) -> SourceR { - SourceR::new(((self.bits >> 25) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Bandwidth select R (resistor) value."] - #[inline(always)] - pub fn selr(&mut self) -> SelrW { - SelrW::new(self, 0) - } - #[doc = "Bits 4:9 - Bandwidth select I (interation) value."] - #[inline(always)] - pub fn seli(&mut self) -> SeliW { - SeliW::new(self, 4) - } - #[doc = "Bits 10:14 - Bandwidth select P (proportional) value."] - #[inline(always)] - pub fn selp(&mut self) -> SelpW { - SelpW::new(self, 10) - } - #[doc = "Bit 16 - Bypass of the divide-by-2 divider"] - #[inline(always)] - pub fn bypasspostdiv2(&mut self) -> Bypasspostdiv2W { - Bypasspostdiv2W::new(self, 16) - } - #[doc = "Bit 17 - Up Limiter."] - #[inline(always)] - pub fn limupoff(&mut self) -> LimupoffW { - LimupoffW::new(self, 17) - } - #[doc = "Bit 18 - Control of the bandwidth of the PLL."] - #[inline(always)] - pub fn banddirect(&mut self) -> BanddirectW { - BanddirectW::new(self, 18) - } - #[doc = "Bit 19 - Bypass of the pre-divider."] - #[inline(always)] - pub fn bypassprediv(&mut self) -> BypasspredivW { - BypasspredivW::new(self, 19) - } - #[doc = "Bit 20 - Bypass of the post-divider."] - #[inline(always)] - pub fn bypasspostdiv(&mut self) -> BypasspostdivW { - BypasspostdivW::new(self, 20) - } - #[doc = "Bit 22 - Free Running Mode Enable"] - #[inline(always)] - pub fn frm(&mut self) -> FrmW { - FrmW::new(self, 22) - } - #[doc = "Bits 25:26 - Clock Source"] - #[inline(always)] - pub fn source(&mut self) -> SourceW { - SourceW::new(self, 25) - } -} -#[doc = "SPLL Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpllctrlSpec; -impl crate::RegisterSpec for SpllctrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllctrl::R`](R) reader structure"] -impl crate::Readable for SpllctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`spllctrl::W`](W) writer structure"] -impl crate::Writable for SpllctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SPLLCTRL to value 0"] -impl crate::Resettable for SpllctrlSpec {} diff --git a/mcxa276-pac/src/scg0/splllock_cnfg.rs b/mcxa276-pac/src/scg0/splllock_cnfg.rs deleted file mode 100644 index 7fca38584..000000000 --- a/mcxa276-pac/src/scg0/splllock_cnfg.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SPLLLOCK_CNFG` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLLOCK_CNFG` writer"] -pub type W = crate::W; -#[doc = "Field `LOCK_TIME` reader - Configures the number of reference clocks to count before SPLL is considered locked."] -pub type LockTimeR = crate::FieldReader; -#[doc = "Field `LOCK_TIME` writer - Configures the number of reference clocks to count before SPLL is considered locked."] -pub type LockTimeW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; -impl R { - #[doc = "Bits 0:16 - Configures the number of reference clocks to count before SPLL is considered locked."] - #[inline(always)] - pub fn lock_time(&self) -> LockTimeR { - LockTimeR::new(self.bits & 0x0001_ffff) - } -} -impl W { - #[doc = "Bits 0:16 - Configures the number of reference clocks to count before SPLL is considered locked."] - #[inline(always)] - pub fn lock_time(&mut self) -> LockTimeW { - LockTimeW::new(self, 0) - } -} -#[doc = "SPLL LOCK Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`splllock_cnfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`splllock_cnfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SplllockCnfgSpec; -impl crate::RegisterSpec for SplllockCnfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`splllock_cnfg::R`](R) reader structure"] -impl crate::Readable for SplllockCnfgSpec {} -#[doc = "`write(|w| ..)` method takes [`splllock_cnfg::W`](W) writer structure"] -impl crate::Writable for SplllockCnfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SPLLLOCK_CNFG to value 0x4f4c"] -impl crate::Resettable for SplllockCnfgSpec { - const RESET_VALUE: u32 = 0x4f4c; -} diff --git a/mcxa276-pac/src/scg0/spllmdiv.rs b/mcxa276-pac/src/scg0/spllmdiv.rs deleted file mode 100644 index 7a3b1a4bf..000000000 --- a/mcxa276-pac/src/scg0/spllmdiv.rs +++ /dev/null @@ -1,100 +0,0 @@ -#[doc = "Register `SPLLMDIV` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLMDIV` writer"] -pub type W = crate::W; -#[doc = "Field `MDIV` reader - Feedback divider ratio (M-divider)."] -pub type MdivR = crate::FieldReader; -#[doc = "Field `MDIV` writer - Feedback divider ratio (M-divider)."] -pub type MdivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Feedback ratio change request.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mreq { - #[doc = "0: Feedback ratio change is not requested"] - Disabled = 0, - #[doc = "1: Feedback ratio change is requested"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mreq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MREQ` reader - Feedback ratio change request."] -pub type MreqR = crate::BitReader; -impl MreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mreq { - match self.bits { - false => Mreq::Disabled, - true => Mreq::Enabled, - } - } - #[doc = "Feedback ratio change is not requested"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Mreq::Disabled - } - #[doc = "Feedback ratio change is requested"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Mreq::Enabled - } -} -#[doc = "Field `MREQ` writer - Feedback ratio change request."] -pub type MreqW<'a, REG> = crate::BitWriter<'a, REG, Mreq>; -impl<'a, REG> MreqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Feedback ratio change is not requested"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Mreq::Disabled) - } - #[doc = "Feedback ratio change is requested"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Mreq::Enabled) - } -} -impl R { - #[doc = "Bits 0:15 - Feedback divider ratio (M-divider)."] - #[inline(always)] - pub fn mdiv(&self) -> MdivR { - MdivR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 31 - Feedback ratio change request."] - #[inline(always)] - pub fn mreq(&self) -> MreqR { - MreqR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Feedback divider ratio (M-divider)."] - #[inline(always)] - pub fn mdiv(&mut self) -> MdivW { - MdivW::new(self, 0) - } - #[doc = "Bit 31 - Feedback ratio change request."] - #[inline(always)] - pub fn mreq(&mut self) -> MreqW { - MreqW::new(self, 31) - } -} -#[doc = "SPLL M Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllmdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllmdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpllmdivSpec; -impl crate::RegisterSpec for SpllmdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllmdiv::R`](R) reader structure"] -impl crate::Readable for SpllmdivSpec {} -#[doc = "`write(|w| ..)` method takes [`spllmdiv::W`](W) writer structure"] -impl crate::Writable for SpllmdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SPLLMDIV to value 0x01"] -impl crate::Resettable for SpllmdivSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/scg0/spllndiv.rs b/mcxa276-pac/src/scg0/spllndiv.rs deleted file mode 100644 index 5b1e0c22d..000000000 --- a/mcxa276-pac/src/scg0/spllndiv.rs +++ /dev/null @@ -1,100 +0,0 @@ -#[doc = "Register `SPLLNDIV` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLNDIV` writer"] -pub type W = crate::W; -#[doc = "Field `NDIV` reader - Pre-divider divider ratio (N-divider)."] -pub type NdivR = crate::FieldReader; -#[doc = "Field `NDIV` writer - Pre-divider divider ratio (N-divider)."] -pub type NdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Pre-divider ratio change request.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nreq { - #[doc = "0: Pre-divider ratio change is not requested"] - Disabled = 0, - #[doc = "1: Pre-divider ratio change is requested"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nreq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NREQ` reader - Pre-divider ratio change request."] -pub type NreqR = crate::BitReader; -impl NreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nreq { - match self.bits { - false => Nreq::Disabled, - true => Nreq::Enabled, - } - } - #[doc = "Pre-divider ratio change is not requested"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Nreq::Disabled - } - #[doc = "Pre-divider ratio change is requested"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Nreq::Enabled - } -} -#[doc = "Field `NREQ` writer - Pre-divider ratio change request."] -pub type NreqW<'a, REG> = crate::BitWriter<'a, REG, Nreq>; -impl<'a, REG> NreqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pre-divider ratio change is not requested"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Nreq::Disabled) - } - #[doc = "Pre-divider ratio change is requested"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Nreq::Enabled) - } -} -impl R { - #[doc = "Bits 0:7 - Pre-divider divider ratio (N-divider)."] - #[inline(always)] - pub fn ndiv(&self) -> NdivR { - NdivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 31 - Pre-divider ratio change request."] - #[inline(always)] - pub fn nreq(&self) -> NreqR { - NreqR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - Pre-divider divider ratio (N-divider)."] - #[inline(always)] - pub fn ndiv(&mut self) -> NdivW { - NdivW::new(self, 0) - } - #[doc = "Bit 31 - Pre-divider ratio change request."] - #[inline(always)] - pub fn nreq(&mut self) -> NreqW { - NreqW::new(self, 31) - } -} -#[doc = "SPLL N Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllndiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllndiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpllndivSpec; -impl crate::RegisterSpec for SpllndivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllndiv::R`](R) reader structure"] -impl crate::Readable for SpllndivSpec {} -#[doc = "`write(|w| ..)` method takes [`spllndiv::W`](W) writer structure"] -impl crate::Writable for SpllndivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SPLLNDIV to value 0x01"] -impl crate::Resettable for SpllndivSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/scg0/spllpdiv.rs b/mcxa276-pac/src/scg0/spllpdiv.rs deleted file mode 100644 index ed46e330f..000000000 --- a/mcxa276-pac/src/scg0/spllpdiv.rs +++ /dev/null @@ -1,100 +0,0 @@ -#[doc = "Register `SPLLPDIV` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLPDIV` writer"] -pub type W = crate::W; -#[doc = "Field `PDIV` reader - Post-divider divider ratio (P-divider)"] -pub type PdivR = crate::FieldReader; -#[doc = "Field `PDIV` writer - Post-divider divider ratio (P-divider)"] -pub type PdivW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Post-divider ratio change request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Preq { - #[doc = "0: Post-divider ratio change is not requested"] - Disabled = 0, - #[doc = "1: Post-divider ratio change is requested"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Preq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PREQ` reader - Post-divider ratio change request"] -pub type PreqR = crate::BitReader; -impl PreqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Preq { - match self.bits { - false => Preq::Disabled, - true => Preq::Enabled, - } - } - #[doc = "Post-divider ratio change is not requested"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Preq::Disabled - } - #[doc = "Post-divider ratio change is requested"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Preq::Enabled - } -} -#[doc = "Field `PREQ` writer - Post-divider ratio change request"] -pub type PreqW<'a, REG> = crate::BitWriter<'a, REG, Preq>; -impl<'a, REG> PreqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Post-divider ratio change is not requested"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Preq::Disabled) - } - #[doc = "Post-divider ratio change is requested"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Preq::Enabled) - } -} -impl R { - #[doc = "Bits 0:4 - Post-divider divider ratio (P-divider)"] - #[inline(always)] - pub fn pdiv(&self) -> PdivR { - PdivR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bit 31 - Post-divider ratio change request"] - #[inline(always)] - pub fn preq(&self) -> PreqR { - PreqR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Post-divider divider ratio (P-divider)"] - #[inline(always)] - pub fn pdiv(&mut self) -> PdivW { - PdivW::new(self, 0) - } - #[doc = "Bit 31 - Post-divider ratio change request"] - #[inline(always)] - pub fn preq(&mut self) -> PreqW { - PreqW::new(self, 31) - } -} -#[doc = "SPLL P Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllpdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllpdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpllpdivSpec; -impl crate::RegisterSpec for SpllpdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllpdiv::R`](R) reader structure"] -impl crate::Readable for SpllpdivSpec {} -#[doc = "`write(|w| ..)` method takes [`spllpdiv::W`](W) writer structure"] -impl crate::Writable for SpllpdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SPLLPDIV to value 0x01"] -impl crate::Resettable for SpllpdivSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/scg0/spllsscg0.rs b/mcxa276-pac/src/scg0/spllsscg0.rs deleted file mode 100644 index 44fdf274e..000000000 --- a/mcxa276-pac/src/scg0/spllsscg0.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SPLLSSCG0` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLSSCG0` writer"] -pub type W = crate::W; -#[doc = "Field `SS_MDIV_LSB` reader - SS_MDIV\\[31:0\\]"] -pub type SsMdivLsbR = crate::FieldReader; -#[doc = "Field `SS_MDIV_LSB` writer - SS_MDIV\\[31:0\\]"] -pub type SsMdivLsbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - SS_MDIV\\[31:0\\]"] - #[inline(always)] - pub fn ss_mdiv_lsb(&self) -> SsMdivLsbR { - SsMdivLsbR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - SS_MDIV\\[31:0\\]"] - #[inline(always)] - pub fn ss_mdiv_lsb(&mut self) -> SsMdivLsbW { - SsMdivLsbW::new(self, 0) - } -} -#[doc = "SPLL Spread Spectrum Control 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Spllsscg0Spec; -impl crate::RegisterSpec for Spllsscg0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllsscg0::R`](R) reader structure"] -impl crate::Readable for Spllsscg0Spec {} -#[doc = "`write(|w| ..)` method takes [`spllsscg0::W`](W) writer structure"] -impl crate::Writable for Spllsscg0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SPLLSSCG0 to value 0"] -impl crate::Resettable for Spllsscg0Spec {} diff --git a/mcxa276-pac/src/scg0/spllsscg1.rs b/mcxa276-pac/src/scg0/spllsscg1.rs deleted file mode 100644 index aebacacbf..000000000 --- a/mcxa276-pac/src/scg0/spllsscg1.rs +++ /dev/null @@ -1,331 +0,0 @@ -#[doc = "Register `SPLLSSCG1` reader"] -pub type R = crate::R; -#[doc = "Register `SPLLSSCG1` writer"] -pub type W = crate::W; -#[doc = "Field `SS_MDIV_MSB` reader - SS_MDIV\\[32\\]"] -pub type SsMdivMsbR = crate::BitReader; -#[doc = "Field `SS_MDIV_MSB` writer - SS_MDIV\\[32\\]"] -pub type SsMdivMsbW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "SS_MDIV\\[32:0\\] change request.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SsMdivReq { - #[doc = "0: SS_MDIV change is not requested"] - Disabled = 0, - #[doc = "1: SS_MDIV change is requested"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SsMdivReq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SS_MDIV_REQ` reader - SS_MDIV\\[32:0\\] change request."] -pub type SsMdivReqR = crate::BitReader; -impl SsMdivReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SsMdivReq { - match self.bits { - false => SsMdivReq::Disabled, - true => SsMdivReq::Enabled, - } - } - #[doc = "SS_MDIV change is not requested"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == SsMdivReq::Disabled - } - #[doc = "SS_MDIV change is requested"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == SsMdivReq::Enabled - } -} -#[doc = "Field `SS_MDIV_REQ` writer - SS_MDIV\\[32:0\\] change request."] -pub type SsMdivReqW<'a, REG> = crate::BitWriter<'a, REG, SsMdivReq>; -impl<'a, REG> SsMdivReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SS_MDIV change is not requested"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(SsMdivReq::Disabled) - } - #[doc = "SS_MDIV change is requested"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(SsMdivReq::Enabled) - } -} -#[doc = "Field `MF` reader - Modulation Frequency Control"] -pub type MfR = crate::FieldReader; -#[doc = "Field `MF` writer - Modulation Frequency Control"] -pub type MfW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `MR` reader - Modulation Depth Control"] -pub type MrR = crate::FieldReader; -#[doc = "Field `MR` writer - Modulation Depth Control"] -pub type MrW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `MC` reader - Modulation Waveform Control"] -pub type McR = crate::FieldReader; -#[doc = "Field `MC` writer - Modulation Waveform Control"] -pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Dither Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dither { - #[doc = "0: Dither is not enabled"] - Disabled = 0, - #[doc = "1: Dither is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dither) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DITHER` reader - Dither Enable"] -pub type DitherR = crate::BitReader; -impl DitherR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dither { - match self.bits { - false => Dither::Disabled, - true => Dither::Enabled, - } - } - #[doc = "Dither is not enabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Dither::Disabled - } - #[doc = "Dither is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Dither::Enabled - } -} -#[doc = "Field `DITHER` writer - Dither Enable"] -pub type DitherW<'a, REG> = crate::BitWriter<'a, REG, Dither>; -impl<'a, REG> DitherW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Dither is not enabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Dither::Disabled) - } - #[doc = "Dither is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Dither::Enabled) - } -} -#[doc = "SS_MDIV select.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SelSsMdiv { - #[doc = "0: Feedback divider ratio is MDIV\\[15:0\\]"] - Disabled = 0, - #[doc = "1: Feedback divider ratio is SS_MDIV\\[32:0\\]"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SelSsMdiv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SEL_SS_MDIV` reader - SS_MDIV select."] -pub type SelSsMdivR = crate::BitReader; -impl SelSsMdivR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SelSsMdiv { - match self.bits { - false => SelSsMdiv::Disabled, - true => SelSsMdiv::Enabled, - } - } - #[doc = "Feedback divider ratio is MDIV\\[15:0\\]"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == SelSsMdiv::Disabled - } - #[doc = "Feedback divider ratio is SS_MDIV\\[32:0\\]"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == SelSsMdiv::Enabled - } -} -#[doc = "Field `SEL_SS_MDIV` writer - SS_MDIV select."] -pub type SelSsMdivW<'a, REG> = crate::BitWriter<'a, REG, SelSsMdiv>; -impl<'a, REG> SelSsMdivW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Feedback divider ratio is MDIV\\[15:0\\]"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(SelSsMdiv::Disabled) - } - #[doc = "Feedback divider ratio is SS_MDIV\\[32:0\\]"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(SelSsMdiv::Enabled) - } -} -#[doc = "SSCG Power Down\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SsPd { - #[doc = "0: SSCG is powered on"] - Disabled = 0, - #[doc = "1: SSCG is powered off"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SsPd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SS_PD` reader - SSCG Power Down"] -pub type SsPdR = crate::BitReader; -impl SsPdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SsPd { - match self.bits { - false => SsPd::Disabled, - true => SsPd::Enabled, - } - } - #[doc = "SSCG is powered on"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == SsPd::Disabled - } - #[doc = "SSCG is powered off"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == SsPd::Enabled - } -} -#[doc = "Field `SS_PD` writer - SSCG Power Down"] -pub type SsPdW<'a, REG> = crate::BitWriter<'a, REG, SsPd>; -impl<'a, REG> SsPdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SSCG is powered on"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(SsPd::Disabled) - } - #[doc = "SSCG is powered off"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(SsPd::Enabled) - } -} -impl R { - #[doc = "Bit 0 - SS_MDIV\\[32\\]"] - #[inline(always)] - pub fn ss_mdiv_msb(&self) -> SsMdivMsbR { - SsMdivMsbR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SS_MDIV\\[32:0\\] change request."] - #[inline(always)] - pub fn ss_mdiv_req(&self) -> SsMdivReqR { - SsMdivReqR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:4 - Modulation Frequency Control"] - #[inline(always)] - pub fn mf(&self) -> MfR { - MfR::new(((self.bits >> 2) & 7) as u8) - } - #[doc = "Bits 5:7 - Modulation Depth Control"] - #[inline(always)] - pub fn mr(&self) -> MrR { - MrR::new(((self.bits >> 5) & 7) as u8) - } - #[doc = "Bits 8:9 - Modulation Waveform Control"] - #[inline(always)] - pub fn mc(&self) -> McR { - McR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bit 10 - Dither Enable"] - #[inline(always)] - pub fn dither(&self) -> DitherR { - DitherR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - SS_MDIV select."] - #[inline(always)] - pub fn sel_ss_mdiv(&self) -> SelSsMdivR { - SelSsMdivR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 31 - SSCG Power Down"] - #[inline(always)] - pub fn ss_pd(&self) -> SsPdR { - SsPdR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - SS_MDIV\\[32\\]"] - #[inline(always)] - pub fn ss_mdiv_msb(&mut self) -> SsMdivMsbW { - SsMdivMsbW::new(self, 0) - } - #[doc = "Bit 1 - SS_MDIV\\[32:0\\] change request."] - #[inline(always)] - pub fn ss_mdiv_req(&mut self) -> SsMdivReqW { - SsMdivReqW::new(self, 1) - } - #[doc = "Bits 2:4 - Modulation Frequency Control"] - #[inline(always)] - pub fn mf(&mut self) -> MfW { - MfW::new(self, 2) - } - #[doc = "Bits 5:7 - Modulation Depth Control"] - #[inline(always)] - pub fn mr(&mut self) -> MrW { - MrW::new(self, 5) - } - #[doc = "Bits 8:9 - Modulation Waveform Control"] - #[inline(always)] - pub fn mc(&mut self) -> McW { - McW::new(self, 8) - } - #[doc = "Bit 10 - Dither Enable"] - #[inline(always)] - pub fn dither(&mut self) -> DitherW { - DitherW::new(self, 10) - } - #[doc = "Bit 11 - SS_MDIV select."] - #[inline(always)] - pub fn sel_ss_mdiv(&mut self) -> SelSsMdivW { - SelSsMdivW::new(self, 11) - } - #[doc = "Bit 31 - SSCG Power Down"] - #[inline(always)] - pub fn ss_pd(&mut self) -> SsPdW { - SsPdW::new(self, 31) - } -} -#[doc = "SPLL Spread Spectrum Control 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllsscg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Spllsscg1Spec; -impl crate::RegisterSpec for Spllsscg1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllsscg1::R`](R) reader structure"] -impl crate::Readable for Spllsscg1Spec {} -#[doc = "`write(|w| ..)` method takes [`spllsscg1::W`](W) writer structure"] -impl crate::Writable for Spllsscg1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SPLLSSCG1 to value 0x8000_0000"] -impl crate::Resettable for Spllsscg1Spec { - const RESET_VALUE: u32 = 0x8000_0000; -} diff --git a/mcxa276-pac/src/scg0/spllsscgstat.rs b/mcxa276-pac/src/scg0/spllsscgstat.rs deleted file mode 100644 index 7cc41dfaa..000000000 --- a/mcxa276-pac/src/scg0/spllsscgstat.rs +++ /dev/null @@ -1,54 +0,0 @@ -#[doc = "Register `SPLLSSCGSTAT` reader"] -pub type R = crate::R; -#[doc = "SS_MDIV change acknowledge\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SsMdivAck { - #[doc = "0: The SS_MDIV, MF, MR, MC ratio change is not accepted by the analog PLL"] - Disabled = 0, - #[doc = "1: The SS_MDIV, MF, MR, MC ratio change is accepted by the analog PLL"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SsMdivAck) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SS_MDIV_ACK` reader - SS_MDIV change acknowledge"] -pub type SsMdivAckR = crate::BitReader; -impl SsMdivAckR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SsMdivAck { - match self.bits { - false => SsMdivAck::Disabled, - true => SsMdivAck::Enabled, - } - } - #[doc = "The SS_MDIV, MF, MR, MC ratio change is not accepted by the analog PLL"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == SsMdivAck::Disabled - } - #[doc = "The SS_MDIV, MF, MR, MC ratio change is accepted by the analog PLL"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == SsMdivAck::Enabled - } -} -impl R { - #[doc = "Bit 0 - SS_MDIV change acknowledge"] - #[inline(always)] - pub fn ss_mdiv_ack(&self) -> SsMdivAckR { - SsMdivAckR::new((self.bits & 1) != 0) - } -} -#[doc = "SPLL SSCG Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllsscgstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpllsscgstatSpec; -impl crate::RegisterSpec for SpllsscgstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllsscgstat::R`](R) reader structure"] -impl crate::Readable for SpllsscgstatSpec {} -#[doc = "`reset()` method sets SPLLSSCGSTAT to value 0"] -impl crate::Resettable for SpllsscgstatSpec {} diff --git a/mcxa276-pac/src/scg0/spllstat.rs b/mcxa276-pac/src/scg0/spllstat.rs deleted file mode 100644 index 47967789c..000000000 --- a/mcxa276-pac/src/scg0/spllstat.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `SPLLSTAT` reader"] -pub type R = crate::R; -#[doc = "Pre-divider (N) ratio change acknowledge\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ndivack { - #[doc = "0: The Pre-divider (N) ratio change is not accepted by the analog PLL."] - Disabled = 0, - #[doc = "1: The Pre-divider (N) ratio change is accepted by the analog PLL."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ndivack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NDIVACK` reader - Pre-divider (N) ratio change acknowledge"] -pub type NdivackR = crate::BitReader; -impl NdivackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ndivack { - match self.bits { - false => Ndivack::Disabled, - true => Ndivack::Enabled, - } - } - #[doc = "The Pre-divider (N) ratio change is not accepted by the analog PLL."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Ndivack::Disabled - } - #[doc = "The Pre-divider (N) ratio change is accepted by the analog PLL."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Ndivack::Enabled - } -} -#[doc = "Feedback (M) divider ratio change acknowledge\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Mdivack { - #[doc = "0: The Feedback (M) ratio change is not accepted by the analog PLL."] - Disabled = 0, - #[doc = "1: The Feedback (M) ratio change is accepted by the analog PLL."] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Mdivack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MDIVACK` reader - Feedback (M) divider ratio change acknowledge"] -pub type MdivackR = crate::BitReader; -impl MdivackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Mdivack { - match self.bits { - false => Mdivack::Disabled, - true => Mdivack::Enabled, - } - } - #[doc = "The Feedback (M) ratio change is not accepted by the analog PLL."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Mdivack::Disabled - } - #[doc = "The Feedback (M) ratio change is accepted by the analog PLL."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Mdivack::Enabled - } -} -#[doc = "Post-divider (P) ratio change acknowledge\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pdivack { - #[doc = "0: The Post-divider (P) ratio change is not accepted by the analog PLL"] - Disabled = 0, - #[doc = "1: The Post-divider (P) ratio change is accepted by the analog PLL"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pdivack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDIVACK` reader - Post-divider (P) ratio change acknowledge"] -pub type PdivackR = crate::BitReader; -impl PdivackR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pdivack { - match self.bits { - false => Pdivack::Disabled, - true => Pdivack::Enabled, - } - } - #[doc = "The Post-divider (P) ratio change is not accepted by the analog PLL"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Pdivack::Disabled - } - #[doc = "The Post-divider (P) ratio change is accepted by the analog PLL"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Pdivack::Enabled - } -} -#[doc = "Free running detector (active high)\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Frmdet { - #[doc = "0: Free running is not detected"] - Disabled = 0, - #[doc = "1: Free running is detected"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Frmdet) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRMDET` reader - Free running detector (active high)"] -pub type FrmdetR = crate::BitReader; -impl FrmdetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Frmdet { - match self.bits { - false => Frmdet::Disabled, - true => Frmdet::Enabled, - } - } - #[doc = "Free running is not detected"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Frmdet::Disabled - } - #[doc = "Free running is detected"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Frmdet::Enabled - } -} -impl R { - #[doc = "Bit 1 - Pre-divider (N) ratio change acknowledge"] - #[inline(always)] - pub fn ndivack(&self) -> NdivackR { - NdivackR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Feedback (M) divider ratio change acknowledge"] - #[inline(always)] - pub fn mdivack(&self) -> MdivackR { - MdivackR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Post-divider (P) ratio change acknowledge"] - #[inline(always)] - pub fn pdivack(&self) -> PdivackR { - PdivackR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Free running detector (active high)"] - #[inline(always)] - pub fn frmdet(&self) -> FrmdetR { - FrmdetR::new(((self.bits >> 4) & 1) != 0) - } -} -#[doc = "SPLL Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpllstatSpec; -impl crate::RegisterSpec for SpllstatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`spllstat::R`](R) reader structure"] -impl crate::Readable for SpllstatSpec {} -#[doc = "`reset()` method sets SPLLSTAT to value 0"] -impl crate::Resettable for SpllstatSpec {} diff --git a/mcxa276-pac/src/scg0/trim_lock.rs b/mcxa276-pac/src/scg0/trim_lock.rs deleted file mode 100644 index e10975210..000000000 --- a/mcxa276-pac/src/scg0/trim_lock.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `TRIM_LOCK` reader"] -pub type R = crate::R; -#[doc = "Register `TRIM_LOCK` writer"] -pub type W = crate::W; -#[doc = "TRIM_UNLOCK\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrimUnlock { - #[doc = "0: SCG Trim Registers locked and not writable."] - Locked = 0, - #[doc = "1: SCG Trim registers unlocked and writable."] - NotLocked = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrimUnlock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIM_UNLOCK` reader - TRIM_UNLOCK"] -pub type TrimUnlockR = crate::BitReader; -impl TrimUnlockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrimUnlock { - match self.bits { - false => TrimUnlock::Locked, - true => TrimUnlock::NotLocked, - } - } - #[doc = "SCG Trim Registers locked and not writable."] - #[inline(always)] - pub fn is_locked(&self) -> bool { - *self == TrimUnlock::Locked - } - #[doc = "SCG Trim registers unlocked and writable."] - #[inline(always)] - pub fn is_not_locked(&self) -> bool { - *self == TrimUnlock::NotLocked - } -} -#[doc = "Field `TRIM_UNLOCK` writer - TRIM_UNLOCK"] -pub type TrimUnlockW<'a, REG> = crate::BitWriter<'a, REG, TrimUnlock>; -impl<'a, REG> TrimUnlockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SCG Trim Registers locked and not writable."] - #[inline(always)] - pub fn locked(self) -> &'a mut crate::W { - self.variant(TrimUnlock::Locked) - } - #[doc = "SCG Trim registers unlocked and writable."] - #[inline(always)] - pub fn not_locked(self) -> &'a mut crate::W { - self.variant(TrimUnlock::NotLocked) - } -} -#[doc = "IFR_DISABLE\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IfrDisable { - #[doc = "0: IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset."] - Enabled = 0, - #[doc = "1: IFR write access to SCG trim registers during system reset is blocked."] - Disabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IfrDisable) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IFR_DISABLE` reader - IFR_DISABLE"] -pub type IfrDisableR = crate::BitReader; -impl IfrDisableR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IfrDisable { - match self.bits { - false => IfrDisable::Enabled, - true => IfrDisable::Disabled, - } - } - #[doc = "IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset."] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == IfrDisable::Enabled - } - #[doc = "IFR write access to SCG trim registers during system reset is blocked."] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == IfrDisable::Disabled - } -} -#[doc = "Field `IFR_DISABLE` writer - IFR_DISABLE"] -pub type IfrDisableW<'a, REG> = crate::BitWriter<'a, REG, IfrDisable>; -impl<'a, REG> IfrDisableW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset."] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(IfrDisable::Enabled) - } - #[doc = "IFR write access to SCG trim registers during system reset is blocked."] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(IfrDisable::Disabled) - } -} -#[doc = "Field `TRIM_LOCK_KEY` reader - TRIM_LOCK_KEY"] -pub type TrimLockKeyR = crate::FieldReader; -#[doc = "Field `TRIM_LOCK_KEY` writer - TRIM_LOCK_KEY"] -pub type TrimLockKeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bit 0 - TRIM_UNLOCK"] - #[inline(always)] - pub fn trim_unlock(&self) -> TrimUnlockR { - TrimUnlockR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - IFR_DISABLE"] - #[inline(always)] - pub fn ifr_disable(&self) -> IfrDisableR { - IfrDisableR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 16:31 - TRIM_LOCK_KEY"] - #[inline(always)] - pub fn trim_lock_key(&self) -> TrimLockKeyR { - TrimLockKeyR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bit 0 - TRIM_UNLOCK"] - #[inline(always)] - pub fn trim_unlock(&mut self) -> TrimUnlockW { - TrimUnlockW::new(self, 0) - } - #[doc = "Bit 1 - IFR_DISABLE"] - #[inline(always)] - pub fn ifr_disable(&mut self) -> IfrDisableW { - IfrDisableW::new(self, 1) - } - #[doc = "Bits 16:31 - TRIM_LOCK_KEY"] - #[inline(always)] - pub fn trim_lock_key(&mut self) -> TrimLockKeyW { - TrimLockKeyW::new(self, 16) - } -} -#[doc = "Trim Lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`trim_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trim_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TrimLockSpec; -impl crate::RegisterSpec for TrimLockSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`trim_lock::R`](R) reader structure"] -impl crate::Readable for TrimLockSpec {} -#[doc = "`write(|w| ..)` method takes [`trim_lock::W`](W) writer structure"] -impl crate::Writable for TrimLockSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TRIM_LOCK to value 0"] -impl crate::Resettable for TrimLockSpec {} diff --git a/mcxa276-pac/src/scg0/verid.rs b/mcxa276-pac/src/scg0/verid.rs deleted file mode 100644 index 5fb22a5da..000000000 --- a/mcxa276-pac/src/scg0/verid.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Field `VERSION` reader - SCG Version Number"] -pub type VersionR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - SCG Version Number"] - #[inline(always)] - pub fn version(&self) -> VersionR { - VersionR::new(self.bits) - } -} -#[doc = "Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0"] -impl crate::Resettable for VeridSpec {} diff --git a/mcxa276-pac/src/scn_scb.rs b/mcxa276-pac/src/scn_scb.rs deleted file mode 100644 index 1bee058a5..000000000 --- a/mcxa276-pac/src/scn_scb.rs +++ /dev/null @@ -1,18 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x0c], - cppwr: Cppwr, -} -impl RegisterBlock { - #[doc = "0x0c - Coprocessor Power Control Register"] - #[inline(always)] - pub const fn cppwr(&self) -> &Cppwr { - &self.cppwr - } -} -#[doc = "CPPWR (rw) register accessor: Coprocessor Power Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cppwr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cppwr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cppwr`] module"] -#[doc(alias = "CPPWR")] -pub type Cppwr = crate::Reg; -#[doc = "Coprocessor Power Control Register"] -pub mod cppwr; diff --git a/mcxa276-pac/src/scn_scb/cppwr.rs b/mcxa276-pac/src/scn_scb/cppwr.rs deleted file mode 100644 index c81b6926b..000000000 --- a/mcxa276-pac/src/scn_scb/cppwr.rs +++ /dev/null @@ -1,1183 +0,0 @@ -#[doc = "Register `CPPWR` reader"] -pub type R = crate::R; -#[doc = "Register `CPPWR` writer"] -pub type W = crate::W; -#[doc = "State UNKNOWN 0.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su0 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU0` reader - State UNKNOWN 0."] -pub type Su0R = crate::BitReader; -impl Su0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su0 { - match self.bits { - false => Su0::UnknownNotPermitted, - true => Su0::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su0::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su0::UnknownPermitted - } -} -#[doc = "Field `SU0` writer - State UNKNOWN 0."] -pub type Su0W<'a, REG> = crate::BitWriter<'a, REG, Su0>; -impl<'a, REG> Su0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su0::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su0::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 0.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus0 { - #[doc = "0: The SU0 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU0 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS0` reader - State UNKNOWN Secure only 0."] -pub type Sus0R = crate::BitReader; -impl Sus0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus0 { - match self.bits { - false => Sus0::SecureAndNonSecure, - true => Sus0::SecureOnly, - } - } - #[doc = "The SU0 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus0::SecureAndNonSecure - } - #[doc = "The SU0 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus0::SecureOnly - } -} -#[doc = "Field `SUS0` writer - State UNKNOWN Secure only 0."] -pub type Sus0W<'a, REG> = crate::BitWriter<'a, REG, Sus0>; -impl<'a, REG> Sus0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU0 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus0::SecureAndNonSecure) - } - #[doc = "The SU0 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus0::SecureOnly) - } -} -#[doc = "State UNKNOWN 1.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su1 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU1` reader - State UNKNOWN 1."] -pub type Su1R = crate::BitReader; -impl Su1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su1 { - match self.bits { - false => Su1::UnknownNotPermitted, - true => Su1::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su1::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su1::UnknownPermitted - } -} -#[doc = "Field `SU1` writer - State UNKNOWN 1."] -pub type Su1W<'a, REG> = crate::BitWriter<'a, REG, Su1>; -impl<'a, REG> Su1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su1::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su1::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 1.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus1 { - #[doc = "0: The SU7 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU7 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS1` reader - State UNKNOWN Secure only 1."] -pub type Sus1R = crate::BitReader; -impl Sus1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus1 { - match self.bits { - false => Sus1::SecureAndNonSecure, - true => Sus1::SecureOnly, - } - } - #[doc = "The SU7 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus1::SecureAndNonSecure - } - #[doc = "The SU7 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus1::SecureOnly - } -} -#[doc = "Field `SUS1` writer - State UNKNOWN Secure only 1."] -pub type Sus1W<'a, REG> = crate::BitWriter<'a, REG, Sus1>; -impl<'a, REG> Sus1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU7 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus1::SecureAndNonSecure) - } - #[doc = "The SU7 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus1::SecureOnly) - } -} -#[doc = "State UNKNOWN 2.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su2 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU2` reader - State UNKNOWN 2."] -pub type Su2R = crate::BitReader; -impl Su2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su2 { - match self.bits { - false => Su2::UnknownNotPermitted, - true => Su2::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su2::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su2::UnknownPermitted - } -} -#[doc = "Field `SU2` writer - State UNKNOWN 2."] -pub type Su2W<'a, REG> = crate::BitWriter<'a, REG, Su2>; -impl<'a, REG> Su2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su2::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su2::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 2.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus2 { - #[doc = "0: The SU2 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU2 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS2` reader - State UNKNOWN Secure only 2."] -pub type Sus2R = crate::BitReader; -impl Sus2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus2 { - match self.bits { - false => Sus2::SecureAndNonSecure, - true => Sus2::SecureOnly, - } - } - #[doc = "The SU2 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus2::SecureAndNonSecure - } - #[doc = "The SU2 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus2::SecureOnly - } -} -#[doc = "Field `SUS2` writer - State UNKNOWN Secure only 2."] -pub type Sus2W<'a, REG> = crate::BitWriter<'a, REG, Sus2>; -impl<'a, REG> Sus2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU2 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus2::SecureAndNonSecure) - } - #[doc = "The SU2 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus2::SecureOnly) - } -} -#[doc = "State UNKNOWN 3.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su3 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU3` reader - State UNKNOWN 3."] -pub type Su3R = crate::BitReader; -impl Su3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su3 { - match self.bits { - false => Su3::UnknownNotPermitted, - true => Su3::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su3::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su3::UnknownPermitted - } -} -#[doc = "Field `SU3` writer - State UNKNOWN 3."] -pub type Su3W<'a, REG> = crate::BitWriter<'a, REG, Su3>; -impl<'a, REG> Su3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su3::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su3::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 3.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus3 { - #[doc = "0: The SU3 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU3 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS3` reader - State UNKNOWN Secure only 3."] -pub type Sus3R = crate::BitReader; -impl Sus3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus3 { - match self.bits { - false => Sus3::SecureAndNonSecure, - true => Sus3::SecureOnly, - } - } - #[doc = "The SU3 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus3::SecureAndNonSecure - } - #[doc = "The SU3 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus3::SecureOnly - } -} -#[doc = "Field `SUS3` writer - State UNKNOWN Secure only 3."] -pub type Sus3W<'a, REG> = crate::BitWriter<'a, REG, Sus3>; -impl<'a, REG> Sus3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU3 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus3::SecureAndNonSecure) - } - #[doc = "The SU3 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus3::SecureOnly) - } -} -#[doc = "State UNKNOWN 4.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su4 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU4` reader - State UNKNOWN 4."] -pub type Su4R = crate::BitReader; -impl Su4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su4 { - match self.bits { - false => Su4::UnknownNotPermitted, - true => Su4::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su4::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su4::UnknownPermitted - } -} -#[doc = "Field `SU4` writer - State UNKNOWN 4."] -pub type Su4W<'a, REG> = crate::BitWriter<'a, REG, Su4>; -impl<'a, REG> Su4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su4::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su4::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 4.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus4 { - #[doc = "0: The SU4 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU4 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS4` reader - State UNKNOWN Secure only 4."] -pub type Sus4R = crate::BitReader; -impl Sus4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus4 { - match self.bits { - false => Sus4::SecureAndNonSecure, - true => Sus4::SecureOnly, - } - } - #[doc = "The SU4 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus4::SecureAndNonSecure - } - #[doc = "The SU4 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus4::SecureOnly - } -} -#[doc = "Field `SUS4` writer - State UNKNOWN Secure only 4."] -pub type Sus4W<'a, REG> = crate::BitWriter<'a, REG, Sus4>; -impl<'a, REG> Sus4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU4 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus4::SecureAndNonSecure) - } - #[doc = "The SU4 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus4::SecureOnly) - } -} -#[doc = "State UNKNOWN 5.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su5 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU5` reader - State UNKNOWN 5."] -pub type Su5R = crate::BitReader; -impl Su5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su5 { - match self.bits { - false => Su5::UnknownNotPermitted, - true => Su5::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su5::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su5::UnknownPermitted - } -} -#[doc = "Field `SU5` writer - State UNKNOWN 5."] -pub type Su5W<'a, REG> = crate::BitWriter<'a, REG, Su5>; -impl<'a, REG> Su5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su5::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su5::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 5.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus5 { - #[doc = "0: The SU5 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU5 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS5` reader - State UNKNOWN Secure only 5."] -pub type Sus5R = crate::BitReader; -impl Sus5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus5 { - match self.bits { - false => Sus5::SecureAndNonSecure, - true => Sus5::SecureOnly, - } - } - #[doc = "The SU5 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus5::SecureAndNonSecure - } - #[doc = "The SU5 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus5::SecureOnly - } -} -#[doc = "Field `SUS5` writer - State UNKNOWN Secure only 5."] -pub type Sus5W<'a, REG> = crate::BitWriter<'a, REG, Sus5>; -impl<'a, REG> Sus5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU5 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus5::SecureAndNonSecure) - } - #[doc = "The SU5 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus5::SecureOnly) - } -} -#[doc = "State UNKNOWN 6.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su6 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU6` reader - State UNKNOWN 6."] -pub type Su6R = crate::BitReader; -impl Su6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su6 { - match self.bits { - false => Su6::UnknownNotPermitted, - true => Su6::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su6::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su6::UnknownPermitted - } -} -#[doc = "Field `SU6` writer - State UNKNOWN 6."] -pub type Su6W<'a, REG> = crate::BitWriter<'a, REG, Su6>; -impl<'a, REG> Su6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su6::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su6::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 6.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus6 { - #[doc = "0: The SU6 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU6 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS6` reader - State UNKNOWN Secure only 6."] -pub type Sus6R = crate::BitReader; -impl Sus6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus6 { - match self.bits { - false => Sus6::SecureAndNonSecure, - true => Sus6::SecureOnly, - } - } - #[doc = "The SU6 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus6::SecureAndNonSecure - } - #[doc = "The SU6 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus6::SecureOnly - } -} -#[doc = "Field `SUS6` writer - State UNKNOWN Secure only 6."] -pub type Sus6W<'a, REG> = crate::BitWriter<'a, REG, Sus6>; -impl<'a, REG> Sus6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU6 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus6::SecureAndNonSecure) - } - #[doc = "The SU6 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus6::SecureOnly) - } -} -#[doc = "State UNKNOWN 7.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su7 { - #[doc = "0: The coprocessor state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The coprocessor state is permitted to become UNKNOWN."] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU7` reader - State UNKNOWN 7."] -pub type Su7R = crate::BitReader; -impl Su7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su7 { - match self.bits { - false => Su7::UnknownNotPermitted, - true => Su7::UnknownPermitted, - } - } - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su7::UnknownNotPermitted - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su7::UnknownPermitted - } -} -#[doc = "Field `SU7` writer - State UNKNOWN 7."] -pub type Su7W<'a, REG> = crate::BitWriter<'a, REG, Su7>; -impl<'a, REG> Su7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The coprocessor state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su7::UnknownNotPermitted) - } - #[doc = "The coprocessor state is permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su7::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 7.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus7 { - #[doc = "0: The SU7 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU7 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS7` reader - State UNKNOWN Secure only 7."] -pub type Sus7R = crate::BitReader; -impl Sus7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus7 { - match self.bits { - false => Sus7::SecureAndNonSecure, - true => Sus7::SecureOnly, - } - } - #[doc = "The SU7 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus7::SecureAndNonSecure - } - #[doc = "The SU7 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus7::SecureOnly - } -} -#[doc = "Field `SUS7` writer - State UNKNOWN Secure only 7."] -pub type Sus7W<'a, REG> = crate::BitWriter<'a, REG, Sus7>; -impl<'a, REG> Sus7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU7 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus7::SecureAndNonSecure) - } - #[doc = "The SU7 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus7::SecureOnly) - } -} -#[doc = "State UNKNOWN 10.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Su10 { - #[doc = "0: The floating-point state is not permitted to become UNKNOWN."] - UnknownNotPermitted = 0, - #[doc = "1: The floating-point state is permitted to become UNKNOWN"] - UnknownPermitted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Su10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SU10` reader - State UNKNOWN 10."] -pub type Su10R = crate::BitReader; -impl Su10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Su10 { - match self.bits { - false => Su10::UnknownNotPermitted, - true => Su10::UnknownPermitted, - } - } - #[doc = "The floating-point state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn is_unknown_not_permitted(&self) -> bool { - *self == Su10::UnknownNotPermitted - } - #[doc = "The floating-point state is permitted to become UNKNOWN"] - #[inline(always)] - pub fn is_unknown_permitted(&self) -> bool { - *self == Su10::UnknownPermitted - } -} -#[doc = "Field `SU10` writer - State UNKNOWN 10."] -pub type Su10W<'a, REG> = crate::BitWriter<'a, REG, Su10>; -impl<'a, REG> Su10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The floating-point state is not permitted to become UNKNOWN."] - #[inline(always)] - pub fn unknown_not_permitted(self) -> &'a mut crate::W { - self.variant(Su10::UnknownNotPermitted) - } - #[doc = "The floating-point state is permitted to become UNKNOWN"] - #[inline(always)] - pub fn unknown_permitted(self) -> &'a mut crate::W { - self.variant(Su10::UnknownPermitted) - } -} -#[doc = "State UNKNOWN Secure only 10.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sus10 { - #[doc = "0: The SU10 field is accessible from both Security states."] - SecureAndNonSecure = 0, - #[doc = "1: The SU10 field is only accessible from the Secure state."] - SecureOnly = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sus10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUS10` reader - State UNKNOWN Secure only 10."] -pub type Sus10R = crate::BitReader; -impl Sus10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sus10 { - match self.bits { - false => Sus10::SecureAndNonSecure, - true => Sus10::SecureOnly, - } - } - #[doc = "The SU10 field is accessible from both Security states."] - #[inline(always)] - pub fn is_secure_and_non_secure(&self) -> bool { - *self == Sus10::SecureAndNonSecure - } - #[doc = "The SU10 field is only accessible from the Secure state."] - #[inline(always)] - pub fn is_secure_only(&self) -> bool { - *self == Sus10::SecureOnly - } -} -#[doc = "Field `SUS10` writer - State UNKNOWN Secure only 10."] -pub type Sus10W<'a, REG> = crate::BitWriter<'a, REG, Sus10>; -impl<'a, REG> Sus10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The SU10 field is accessible from both Security states."] - #[inline(always)] - pub fn secure_and_non_secure(self) -> &'a mut crate::W { - self.variant(Sus10::SecureAndNonSecure) - } - #[doc = "The SU10 field is only accessible from the Secure state."] - #[inline(always)] - pub fn secure_only(self) -> &'a mut crate::W { - self.variant(Sus10::SecureOnly) - } -} -#[doc = "Field `SU11` reader - State UNKNOWN 11."] -pub type Su11R = crate::BitReader; -#[doc = "Field `SU11` writer - State UNKNOWN 11."] -pub type Su11W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SUS11` reader - State UNKNOWN Secure only 11."] -pub type Sus11R = crate::BitReader; -#[doc = "Field `SUS11` writer - State UNKNOWN Secure only 11."] -pub type Sus11W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - State UNKNOWN 0."] - #[inline(always)] - pub fn su0(&self) -> Su0R { - Su0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - State UNKNOWN Secure only 0."] - #[inline(always)] - pub fn sus0(&self) -> Sus0R { - Sus0R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - State UNKNOWN 1."] - #[inline(always)] - pub fn su1(&self) -> Su1R { - Su1R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - State UNKNOWN Secure only 1."] - #[inline(always)] - pub fn sus1(&self) -> Sus1R { - Sus1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - State UNKNOWN 2."] - #[inline(always)] - pub fn su2(&self) -> Su2R { - Su2R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - State UNKNOWN Secure only 2."] - #[inline(always)] - pub fn sus2(&self) -> Sus2R { - Sus2R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - State UNKNOWN 3."] - #[inline(always)] - pub fn su3(&self) -> Su3R { - Su3R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - State UNKNOWN Secure only 3."] - #[inline(always)] - pub fn sus3(&self) -> Sus3R { - Sus3R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - State UNKNOWN 4."] - #[inline(always)] - pub fn su4(&self) -> Su4R { - Su4R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - State UNKNOWN Secure only 4."] - #[inline(always)] - pub fn sus4(&self) -> Sus4R { - Sus4R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - State UNKNOWN 5."] - #[inline(always)] - pub fn su5(&self) -> Su5R { - Su5R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - State UNKNOWN Secure only 5."] - #[inline(always)] - pub fn sus5(&self) -> Sus5R { - Sus5R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - State UNKNOWN 6."] - #[inline(always)] - pub fn su6(&self) -> Su6R { - Su6R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - State UNKNOWN Secure only 6."] - #[inline(always)] - pub fn sus6(&self) -> Sus6R { - Sus6R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - State UNKNOWN 7."] - #[inline(always)] - pub fn su7(&self) -> Su7R { - Su7R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - State UNKNOWN Secure only 7."] - #[inline(always)] - pub fn sus7(&self) -> Sus7R { - Sus7R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 20 - State UNKNOWN 10."] - #[inline(always)] - pub fn su10(&self) -> Su10R { - Su10R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - State UNKNOWN Secure only 10."] - #[inline(always)] - pub fn sus10(&self) -> Sus10R { - Sus10R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - State UNKNOWN 11."] - #[inline(always)] - pub fn su11(&self) -> Su11R { - Su11R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - State UNKNOWN Secure only 11."] - #[inline(always)] - pub fn sus11(&self) -> Sus11R { - Sus11R::new(((self.bits >> 23) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - State UNKNOWN 0."] - #[inline(always)] - pub fn su0(&mut self) -> Su0W { - Su0W::new(self, 0) - } - #[doc = "Bit 1 - State UNKNOWN Secure only 0."] - #[inline(always)] - pub fn sus0(&mut self) -> Sus0W { - Sus0W::new(self, 1) - } - #[doc = "Bit 2 - State UNKNOWN 1."] - #[inline(always)] - pub fn su1(&mut self) -> Su1W { - Su1W::new(self, 2) - } - #[doc = "Bit 3 - State UNKNOWN Secure only 1."] - #[inline(always)] - pub fn sus1(&mut self) -> Sus1W { - Sus1W::new(self, 3) - } - #[doc = "Bit 4 - State UNKNOWN 2."] - #[inline(always)] - pub fn su2(&mut self) -> Su2W { - Su2W::new(self, 4) - } - #[doc = "Bit 5 - State UNKNOWN Secure only 2."] - #[inline(always)] - pub fn sus2(&mut self) -> Sus2W { - Sus2W::new(self, 5) - } - #[doc = "Bit 6 - State UNKNOWN 3."] - #[inline(always)] - pub fn su3(&mut self) -> Su3W { - Su3W::new(self, 6) - } - #[doc = "Bit 7 - State UNKNOWN Secure only 3."] - #[inline(always)] - pub fn sus3(&mut self) -> Sus3W { - Sus3W::new(self, 7) - } - #[doc = "Bit 8 - State UNKNOWN 4."] - #[inline(always)] - pub fn su4(&mut self) -> Su4W { - Su4W::new(self, 8) - } - #[doc = "Bit 9 - State UNKNOWN Secure only 4."] - #[inline(always)] - pub fn sus4(&mut self) -> Sus4W { - Sus4W::new(self, 9) - } - #[doc = "Bit 10 - State UNKNOWN 5."] - #[inline(always)] - pub fn su5(&mut self) -> Su5W { - Su5W::new(self, 10) - } - #[doc = "Bit 11 - State UNKNOWN Secure only 5."] - #[inline(always)] - pub fn sus5(&mut self) -> Sus5W { - Sus5W::new(self, 11) - } - #[doc = "Bit 12 - State UNKNOWN 6."] - #[inline(always)] - pub fn su6(&mut self) -> Su6W { - Su6W::new(self, 12) - } - #[doc = "Bit 13 - State UNKNOWN Secure only 6."] - #[inline(always)] - pub fn sus6(&mut self) -> Sus6W { - Sus6W::new(self, 13) - } - #[doc = "Bit 14 - State UNKNOWN 7."] - #[inline(always)] - pub fn su7(&mut self) -> Su7W { - Su7W::new(self, 14) - } - #[doc = "Bit 15 - State UNKNOWN Secure only 7."] - #[inline(always)] - pub fn sus7(&mut self) -> Sus7W { - Sus7W::new(self, 15) - } - #[doc = "Bit 20 - State UNKNOWN 10."] - #[inline(always)] - pub fn su10(&mut self) -> Su10W { - Su10W::new(self, 20) - } - #[doc = "Bit 21 - State UNKNOWN Secure only 10."] - #[inline(always)] - pub fn sus10(&mut self) -> Sus10W { - Sus10W::new(self, 21) - } - #[doc = "Bit 22 - State UNKNOWN 11."] - #[inline(always)] - pub fn su11(&mut self) -> Su11W { - Su11W::new(self, 22) - } - #[doc = "Bit 23 - State UNKNOWN Secure only 11."] - #[inline(always)] - pub fn sus11(&mut self) -> Sus11W { - Sus11W::new(self, 23) - } -} -#[doc = "Coprocessor Power Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cppwr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cppwr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CppwrSpec; -impl crate::RegisterSpec for CppwrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cppwr::R`](R) reader structure"] -impl crate::Readable for CppwrSpec {} -#[doc = "`write(|w| ..)` method takes [`cppwr::W`](W) writer structure"] -impl crate::Writable for CppwrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CPPWR to value 0"] -impl crate::Resettable for CppwrSpec {} diff --git a/mcxa276-pac/src/sgi0.rs b/mcxa276-pac/src/sgi0.rs deleted file mode 100644 index df82e2974..000000000 --- a/mcxa276-pac/src/sgi0.rs +++ /dev/null @@ -1,863 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x0200], - sgi_datin0a: SgiDatin0a, - sgi_datin0b: SgiDatin0b, - sgi_datin0c: SgiDatin0c, - sgi_datin0d: SgiDatin0d, - sgi_datin1a: SgiDatin1a, - sgi_datin1b: SgiDatin1b, - sgi_datin1c: SgiDatin1c, - sgi_datin1d: SgiDatin1d, - sgi_datin2a: SgiDatin2a, - sgi_datin2b: SgiDatin2b, - sgi_datin2c: SgiDatin2c, - sgi_datin2d: SgiDatin2d, - sgi_datin3a: SgiDatin3a, - sgi_datin3b: SgiDatin3b, - sgi_datin3c: SgiDatin3c, - sgi_datin3d: SgiDatin3d, - sgi_key0a: SgiKey0a, - sgi_key0b: SgiKey0b, - sgi_key0c: SgiKey0c, - sgi_key0d: SgiKey0d, - sgi_key1a: SgiKey1a, - sgi_key1b: SgiKey1b, - sgi_key1c: SgiKey1c, - sgi_key1d: SgiKey1d, - sgi_key2a: SgiKey2a, - sgi_key2b: SgiKey2b, - sgi_key2c: SgiKey2c, - sgi_key2d: SgiKey2d, - sgi_key3a: SgiKey3a, - sgi_key3b: SgiKey3b, - sgi_key3c: SgiKey3c, - sgi_key3d: SgiKey3d, - sgi_key4a: SgiKey4a, - sgi_key4b: SgiKey4b, - sgi_key4c: SgiKey4c, - sgi_key4d: SgiKey4d, - sgi_key5a: SgiKey5a, - sgi_key5b: SgiKey5b, - sgi_key5c: SgiKey5c, - sgi_key5d: SgiKey5d, - sgi_key6a: SgiKey6a, - sgi_key6b: SgiKey6b, - sgi_key6c: SgiKey6c, - sgi_key6d: SgiKey6d, - sgi_key7a: SgiKey7a, - sgi_key7b: SgiKey7b, - sgi_key7c: SgiKey7c, - sgi_key7d: SgiKey7d, - sgi_datouta: SgiDatouta, - sgi_datoutb: SgiDatoutb, - sgi_datoutc: SgiDatoutc, - sgi_datoutd: SgiDatoutd, - _reserved52: [u8; 0x0930], - sgi_status: SgiStatus, - sgi_count: SgiCount, - sgi_keychk: SgiKeychk, - _reserved55: [u8; 0xf4], - sgi_ctrl: SgiCtrl, - sgi_ctrl2: SgiCtrl2, - sgi_dummy_ctrl: SgiDummyCtrl, - sgi_sfr_sw_mask: SgiSfrSwMask, - sgi_sfrseed: SgiSfrseed, - sgi_sha2_ctrl: SgiSha2Ctrl, - sgi_sha_fifo: SgiShaFifo, - sgi_config: SgiConfig, - sgi_config2: SgiConfig2, - sgi_auto_mode: SgiAutoMode, - sgi_auto_dma_ctrl: SgiAutoDmaCtrl, - _reserved66: [u8; 0x04], - sgi_prng_sw_seed: SgiPrngSwSeed, - _reserved67: [u8; 0x0c], - sgi_key_ctrl: SgiKeyCtrl, - _reserved68: [u8; 0x0c], - sgi_key_wrap: SgiKeyWrap, - _reserved69: [u8; 0x01b4], - sgi_version: SgiVersion, - _reserved70: [u8; 0xb4], - sgi_access_err: SgiAccessErr, - sgi_access_err_clr: SgiAccessErrClr, - _reserved72: [u8; 0x18], - sgi_int_status: SgiIntStatus, - sgi_int_enable: SgiIntEnable, - sgi_int_status_clr: SgiIntStatusClr, - sgi_int_status_set: SgiIntStatusSet, - _reserved76: [u8; 0x0c], - sgi_module_id: SgiModuleId, -} -impl RegisterBlock { - #[doc = "0x200 - Input Data register 0 - Word-3"] - #[inline(always)] - pub const fn sgi_datin0a(&self) -> &SgiDatin0a { - &self.sgi_datin0a - } - #[doc = "0x204 - Input Data register 0 - Word-2"] - #[inline(always)] - pub const fn sgi_datin0b(&self) -> &SgiDatin0b { - &self.sgi_datin0b - } - #[doc = "0x208 - Input Data register 0 - Word-1"] - #[inline(always)] - pub const fn sgi_datin0c(&self) -> &SgiDatin0c { - &self.sgi_datin0c - } - #[doc = "0x20c - Input Data register 0 - Word-0"] - #[inline(always)] - pub const fn sgi_datin0d(&self) -> &SgiDatin0d { - &self.sgi_datin0d - } - #[doc = "0x210 - Input Data register 1 - Word-3"] - #[inline(always)] - pub const fn sgi_datin1a(&self) -> &SgiDatin1a { - &self.sgi_datin1a - } - #[doc = "0x214 - Input Data register 1 - Word-2"] - #[inline(always)] - pub const fn sgi_datin1b(&self) -> &SgiDatin1b { - &self.sgi_datin1b - } - #[doc = "0x218 - Input Data register 1 - Word-1"] - #[inline(always)] - pub const fn sgi_datin1c(&self) -> &SgiDatin1c { - &self.sgi_datin1c - } - #[doc = "0x21c - Input Data register 1 - Word-0"] - #[inline(always)] - pub const fn sgi_datin1d(&self) -> &SgiDatin1d { - &self.sgi_datin1d - } - #[doc = "0x220 - Input Data register 2 - Word-3"] - #[inline(always)] - pub const fn sgi_datin2a(&self) -> &SgiDatin2a { - &self.sgi_datin2a - } - #[doc = "0x224 - Input Data register 2 - Word-2"] - #[inline(always)] - pub const fn sgi_datin2b(&self) -> &SgiDatin2b { - &self.sgi_datin2b - } - #[doc = "0x228 - Input Data register 2 - Word-1"] - #[inline(always)] - pub const fn sgi_datin2c(&self) -> &SgiDatin2c { - &self.sgi_datin2c - } - #[doc = "0x22c - Input Data register 2 - Word-0"] - #[inline(always)] - pub const fn sgi_datin2d(&self) -> &SgiDatin2d { - &self.sgi_datin2d - } - #[doc = "0x230 - Input Data register 3 - Word-3"] - #[inline(always)] - pub const fn sgi_datin3a(&self) -> &SgiDatin3a { - &self.sgi_datin3a - } - #[doc = "0x234 - Input Data register 3 - Word-2"] - #[inline(always)] - pub const fn sgi_datin3b(&self) -> &SgiDatin3b { - &self.sgi_datin3b - } - #[doc = "0x238 - Input Data register 3 - Word-1"] - #[inline(always)] - pub const fn sgi_datin3c(&self) -> &SgiDatin3c { - &self.sgi_datin3c - } - #[doc = "0x23c - Input Data register 3 - Word-0"] - #[inline(always)] - pub const fn sgi_datin3d(&self) -> &SgiDatin3d { - &self.sgi_datin3d - } - #[doc = "0x240 - Input Key register 0 - Word-3"] - #[inline(always)] - pub const fn sgi_key0a(&self) -> &SgiKey0a { - &self.sgi_key0a - } - #[doc = "0x244 - Input Key register 0 - Word-2"] - #[inline(always)] - pub const fn sgi_key0b(&self) -> &SgiKey0b { - &self.sgi_key0b - } - #[doc = "0x248 - Input Key register 0 - Word-1"] - #[inline(always)] - pub const fn sgi_key0c(&self) -> &SgiKey0c { - &self.sgi_key0c - } - #[doc = "0x24c - Input Key register 0 - Word-0"] - #[inline(always)] - pub const fn sgi_key0d(&self) -> &SgiKey0d { - &self.sgi_key0d - } - #[doc = "0x250 - Input Key register 1 - Word-3"] - #[inline(always)] - pub const fn sgi_key1a(&self) -> &SgiKey1a { - &self.sgi_key1a - } - #[doc = "0x254 - Input Key register 1 - Word-2"] - #[inline(always)] - pub const fn sgi_key1b(&self) -> &SgiKey1b { - &self.sgi_key1b - } - #[doc = "0x258 - Input Key register 1 - Word-1"] - #[inline(always)] - pub const fn sgi_key1c(&self) -> &SgiKey1c { - &self.sgi_key1c - } - #[doc = "0x25c - Input Key register 1 - Word-0"] - #[inline(always)] - pub const fn sgi_key1d(&self) -> &SgiKey1d { - &self.sgi_key1d - } - #[doc = "0x260 - Input Key register 2 - Word-3"] - #[inline(always)] - pub const fn sgi_key2a(&self) -> &SgiKey2a { - &self.sgi_key2a - } - #[doc = "0x264 - Input Key register 2 - Word-2"] - #[inline(always)] - pub const fn sgi_key2b(&self) -> &SgiKey2b { - &self.sgi_key2b - } - #[doc = "0x268 - Input Key register 2 - Word-1"] - #[inline(always)] - pub const fn sgi_key2c(&self) -> &SgiKey2c { - &self.sgi_key2c - } - #[doc = "0x26c - Input Key register 2 - Word-0"] - #[inline(always)] - pub const fn sgi_key2d(&self) -> &SgiKey2d { - &self.sgi_key2d - } - #[doc = "0x270 - Input Key register 3 - Word-3"] - #[inline(always)] - pub const fn sgi_key3a(&self) -> &SgiKey3a { - &self.sgi_key3a - } - #[doc = "0x274 - Input Key register 3 - Word-2"] - #[inline(always)] - pub const fn sgi_key3b(&self) -> &SgiKey3b { - &self.sgi_key3b - } - #[doc = "0x278 - Input Key register 3 - Word-1"] - #[inline(always)] - pub const fn sgi_key3c(&self) -> &SgiKey3c { - &self.sgi_key3c - } - #[doc = "0x27c - Input Key register 3 - Word-0"] - #[inline(always)] - pub const fn sgi_key3d(&self) -> &SgiKey3d { - &self.sgi_key3d - } - #[doc = "0x280 - Input Key register 4 - Word-3"] - #[inline(always)] - pub const fn sgi_key4a(&self) -> &SgiKey4a { - &self.sgi_key4a - } - #[doc = "0x284 - Input Key register 4 - Word-2"] - #[inline(always)] - pub const fn sgi_key4b(&self) -> &SgiKey4b { - &self.sgi_key4b - } - #[doc = "0x288 - Input Key register 4 - Word-1"] - #[inline(always)] - pub const fn sgi_key4c(&self) -> &SgiKey4c { - &self.sgi_key4c - } - #[doc = "0x28c - Input Key register 4 - Word-0"] - #[inline(always)] - pub const fn sgi_key4d(&self) -> &SgiKey4d { - &self.sgi_key4d - } - #[doc = "0x290 - Input Key register 5 - Word-3"] - #[inline(always)] - pub const fn sgi_key5a(&self) -> &SgiKey5a { - &self.sgi_key5a - } - #[doc = "0x294 - Input Key register 5 - Word-2"] - #[inline(always)] - pub const fn sgi_key5b(&self) -> &SgiKey5b { - &self.sgi_key5b - } - #[doc = "0x298 - Input Key register 5 - Word-1"] - #[inline(always)] - pub const fn sgi_key5c(&self) -> &SgiKey5c { - &self.sgi_key5c - } - #[doc = "0x29c - Input Key register 5 - Word-0"] - #[inline(always)] - pub const fn sgi_key5d(&self) -> &SgiKey5d { - &self.sgi_key5d - } - #[doc = "0x2a0 - Input Key register 6 - Word-3"] - #[inline(always)] - pub const fn sgi_key6a(&self) -> &SgiKey6a { - &self.sgi_key6a - } - #[doc = "0x2a4 - Input Key register 6 - Word-2"] - #[inline(always)] - pub const fn sgi_key6b(&self) -> &SgiKey6b { - &self.sgi_key6b - } - #[doc = "0x2a8 - Input Key register 6 - Word-1"] - #[inline(always)] - pub const fn sgi_key6c(&self) -> &SgiKey6c { - &self.sgi_key6c - } - #[doc = "0x2ac - Input Key register 6 - Word-0"] - #[inline(always)] - pub const fn sgi_key6d(&self) -> &SgiKey6d { - &self.sgi_key6d - } - #[doc = "0x2b0 - Input Key register 7 - Word-3"] - #[inline(always)] - pub const fn sgi_key7a(&self) -> &SgiKey7a { - &self.sgi_key7a - } - #[doc = "0x2b4 - Input Key register 7 - Word-2"] - #[inline(always)] - pub const fn sgi_key7b(&self) -> &SgiKey7b { - &self.sgi_key7b - } - #[doc = "0x2b8 - Input Key register 7 - Word-1"] - #[inline(always)] - pub const fn sgi_key7c(&self) -> &SgiKey7c { - &self.sgi_key7c - } - #[doc = "0x2bc - Input Key register 7 - Word-0"] - #[inline(always)] - pub const fn sgi_key7d(&self) -> &SgiKey7d { - &self.sgi_key7d - } - #[doc = "0x2c0 - Output Data register - Word-3"] - #[inline(always)] - pub const fn sgi_datouta(&self) -> &SgiDatouta { - &self.sgi_datouta - } - #[doc = "0x2c4 - Output Data register - Word-2"] - #[inline(always)] - pub const fn sgi_datoutb(&self) -> &SgiDatoutb { - &self.sgi_datoutb - } - #[doc = "0x2c8 - Output Data register - Word-1"] - #[inline(always)] - pub const fn sgi_datoutc(&self) -> &SgiDatoutc { - &self.sgi_datoutc - } - #[doc = "0x2cc - Output Data register - Word-0"] - #[inline(always)] - pub const fn sgi_datoutd(&self) -> &SgiDatoutd { - &self.sgi_datoutd - } - #[doc = "0xc00 - Status register"] - #[inline(always)] - pub const fn sgi_status(&self) -> &SgiStatus { - &self.sgi_status - } - #[doc = "0xc04 - Calculation counter"] - #[inline(always)] - pub const fn sgi_count(&self) -> &SgiCount { - &self.sgi_count - } - #[doc = "0xc08 - Key checksum register"] - #[inline(always)] - pub const fn sgi_keychk(&self) -> &SgiKeychk { - &self.sgi_keychk - } - #[doc = "0xd00 - SGI Control register"] - #[inline(always)] - pub const fn sgi_ctrl(&self) -> &SgiCtrl { - &self.sgi_ctrl - } - #[doc = "0xd04 - SGI Control register 2"] - #[inline(always)] - pub const fn sgi_ctrl2(&self) -> &SgiCtrl2 { - &self.sgi_ctrl2 - } - #[doc = "0xd08 - Configuration of dummy controls"] - #[inline(always)] - pub const fn sgi_dummy_ctrl(&self) -> &SgiDummyCtrl { - &self.sgi_dummy_ctrl - } - #[doc = "0xd0c - Sofware Assisted Masking register ."] - #[inline(always)] - pub const fn sgi_sfr_sw_mask(&self) -> &SgiSfrSwMask { - &self.sgi_sfr_sw_mask - } - #[doc = "0xd10 - SFRSEED register for SFRMASK feature."] - #[inline(always)] - pub const fn sgi_sfrseed(&self) -> &SgiSfrseed { - &self.sgi_sfrseed - } - #[doc = "0xd14 - SHA Control Register"] - #[inline(always)] - pub const fn sgi_sha2_ctrl(&self) -> &SgiSha2Ctrl { - &self.sgi_sha2_ctrl - } - #[doc = "0xd18 - SHA FIFO lower-bank low"] - #[inline(always)] - pub const fn sgi_sha_fifo(&self) -> &SgiShaFifo { - &self.sgi_sha_fifo - } - #[doc = "0xd1c - SHA Configuration Reg"] - #[inline(always)] - pub const fn sgi_config(&self) -> &SgiConfig { - &self.sgi_config - } - #[doc = "0xd20 - SHA Configuration 2 Reg"] - #[inline(always)] - pub const fn sgi_config2(&self) -> &SgiConfig2 { - &self.sgi_config2 - } - #[doc = "0xd24 - SGI Auto Mode Control register"] - #[inline(always)] - pub const fn sgi_auto_mode(&self) -> &SgiAutoMode { - &self.sgi_auto_mode - } - #[doc = "0xd28 - SGI Auto Mode Control register"] - #[inline(always)] - pub const fn sgi_auto_dma_ctrl(&self) -> &SgiAutoDmaCtrl { - &self.sgi_auto_dma_ctrl - } - #[doc = "0xd30 - SGI internal PRNG SW seeding register"] - #[inline(always)] - pub const fn sgi_prng_sw_seed(&self) -> &SgiPrngSwSeed { - &self.sgi_prng_sw_seed - } - #[doc = "0xd40 - SGI Key Control SFR"] - #[inline(always)] - pub const fn sgi_key_ctrl(&self) -> &SgiKeyCtrl { - &self.sgi_key_ctrl - } - #[doc = "0xd50 - Wrapped key read SFR"] - #[inline(always)] - pub const fn sgi_key_wrap(&self) -> &SgiKeyWrap { - &self.sgi_key_wrap - } - #[doc = "0xf08 - SGI Version"] - #[inline(always)] - pub const fn sgi_version(&self) -> &SgiVersion { - &self.sgi_version - } - #[doc = "0xfc0 - Access Error"] - #[inline(always)] - pub const fn sgi_access_err(&self) -> &SgiAccessErr { - &self.sgi_access_err - } - #[doc = "0xfc4 - Clear Access Error"] - #[inline(always)] - pub const fn sgi_access_err_clr(&self) -> &SgiAccessErrClr { - &self.sgi_access_err_clr - } - #[doc = "0xfe0 - Interrupt status"] - #[inline(always)] - pub const fn sgi_int_status(&self) -> &SgiIntStatus { - &self.sgi_int_status - } - #[doc = "0xfe4 - Interrupt enable"] - #[inline(always)] - pub const fn sgi_int_enable(&self) -> &SgiIntEnable { - &self.sgi_int_enable - } - #[doc = "0xfe8 - Interrupt status clear"] - #[inline(always)] - pub const fn sgi_int_status_clr(&self) -> &SgiIntStatusClr { - &self.sgi_int_status_clr - } - #[doc = "0xfec - Interrupt status set"] - #[inline(always)] - pub const fn sgi_int_status_set(&self) -> &SgiIntStatusSet { - &self.sgi_int_status_set - } - #[doc = "0xffc - Module ID"] - #[inline(always)] - pub const fn sgi_module_id(&self) -> &SgiModuleId { - &self.sgi_module_id - } -} -#[doc = "sgi_datin0a (rw) register accessor: Input Data register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0a`] module"] -#[doc(alias = "sgi_datin0a")] -pub type SgiDatin0a = crate::Reg; -#[doc = "Input Data register 0 - Word-3"] -pub mod sgi_datin0a; -#[doc = "sgi_datin0b (rw) register accessor: Input Data register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0b`] module"] -#[doc(alias = "sgi_datin0b")] -pub type SgiDatin0b = crate::Reg; -#[doc = "Input Data register 0 - Word-2"] -pub mod sgi_datin0b; -#[doc = "sgi_datin0c (rw) register accessor: Input Data register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0c`] module"] -#[doc(alias = "sgi_datin0c")] -pub type SgiDatin0c = crate::Reg; -#[doc = "Input Data register 0 - Word-1"] -pub mod sgi_datin0c; -#[doc = "sgi_datin0d (rw) register accessor: Input Data register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin0d`] module"] -#[doc(alias = "sgi_datin0d")] -pub type SgiDatin0d = crate::Reg; -#[doc = "Input Data register 0 - Word-0"] -pub mod sgi_datin0d; -#[doc = "sgi_datin1a (rw) register accessor: Input Data register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1a`] module"] -#[doc(alias = "sgi_datin1a")] -pub type SgiDatin1a = crate::Reg; -#[doc = "Input Data register 1 - Word-3"] -pub mod sgi_datin1a; -#[doc = "sgi_datin1b (rw) register accessor: Input Data register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1b`] module"] -#[doc(alias = "sgi_datin1b")] -pub type SgiDatin1b = crate::Reg; -#[doc = "Input Data register 1 - Word-2"] -pub mod sgi_datin1b; -#[doc = "sgi_datin1c (rw) register accessor: Input Data register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1c`] module"] -#[doc(alias = "sgi_datin1c")] -pub type SgiDatin1c = crate::Reg; -#[doc = "Input Data register 1 - Word-1"] -pub mod sgi_datin1c; -#[doc = "sgi_datin1d (rw) register accessor: Input Data register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin1d`] module"] -#[doc(alias = "sgi_datin1d")] -pub type SgiDatin1d = crate::Reg; -#[doc = "Input Data register 1 - Word-0"] -pub mod sgi_datin1d; -#[doc = "sgi_datin2a (rw) register accessor: Input Data register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2a`] module"] -#[doc(alias = "sgi_datin2a")] -pub type SgiDatin2a = crate::Reg; -#[doc = "Input Data register 2 - Word-3"] -pub mod sgi_datin2a; -#[doc = "sgi_datin2b (rw) register accessor: Input Data register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2b`] module"] -#[doc(alias = "sgi_datin2b")] -pub type SgiDatin2b = crate::Reg; -#[doc = "Input Data register 2 - Word-2"] -pub mod sgi_datin2b; -#[doc = "sgi_datin2c (rw) register accessor: Input Data register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2c`] module"] -#[doc(alias = "sgi_datin2c")] -pub type SgiDatin2c = crate::Reg; -#[doc = "Input Data register 2 - Word-1"] -pub mod sgi_datin2c; -#[doc = "sgi_datin2d (rw) register accessor: Input Data register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin2d`] module"] -#[doc(alias = "sgi_datin2d")] -pub type SgiDatin2d = crate::Reg; -#[doc = "Input Data register 2 - Word-0"] -pub mod sgi_datin2d; -#[doc = "sgi_datin3a (rw) register accessor: Input Data register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3a`] module"] -#[doc(alias = "sgi_datin3a")] -pub type SgiDatin3a = crate::Reg; -#[doc = "Input Data register 3 - Word-3"] -pub mod sgi_datin3a; -#[doc = "sgi_datin3b (rw) register accessor: Input Data register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3b`] module"] -#[doc(alias = "sgi_datin3b")] -pub type SgiDatin3b = crate::Reg; -#[doc = "Input Data register 3 - Word-2"] -pub mod sgi_datin3b; -#[doc = "sgi_datin3c (rw) register accessor: Input Data register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3c`] module"] -#[doc(alias = "sgi_datin3c")] -pub type SgiDatin3c = crate::Reg; -#[doc = "Input Data register 3 - Word-1"] -pub mod sgi_datin3c; -#[doc = "sgi_datin3d (rw) register accessor: Input Data register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datin3d`] module"] -#[doc(alias = "sgi_datin3d")] -pub type SgiDatin3d = crate::Reg; -#[doc = "Input Data register 3 - Word-0"] -pub mod sgi_datin3d; -#[doc = "sgi_key0a (rw) register accessor: Input Key register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0a`] module"] -#[doc(alias = "sgi_key0a")] -pub type SgiKey0a = crate::Reg; -#[doc = "Input Key register 0 - Word-3"] -pub mod sgi_key0a; -#[doc = "sgi_key0b (rw) register accessor: Input Key register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0b`] module"] -#[doc(alias = "sgi_key0b")] -pub type SgiKey0b = crate::Reg; -#[doc = "Input Key register 0 - Word-2"] -pub mod sgi_key0b; -#[doc = "sgi_key0c (rw) register accessor: Input Key register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0c`] module"] -#[doc(alias = "sgi_key0c")] -pub type SgiKey0c = crate::Reg; -#[doc = "Input Key register 0 - Word-1"] -pub mod sgi_key0c; -#[doc = "sgi_key0d (rw) register accessor: Input Key register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key0d`] module"] -#[doc(alias = "sgi_key0d")] -pub type SgiKey0d = crate::Reg; -#[doc = "Input Key register 0 - Word-0"] -pub mod sgi_key0d; -#[doc = "sgi_key1a (rw) register accessor: Input Key register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1a`] module"] -#[doc(alias = "sgi_key1a")] -pub type SgiKey1a = crate::Reg; -#[doc = "Input Key register 1 - Word-3"] -pub mod sgi_key1a; -#[doc = "sgi_key1b (rw) register accessor: Input Key register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1b`] module"] -#[doc(alias = "sgi_key1b")] -pub type SgiKey1b = crate::Reg; -#[doc = "Input Key register 1 - Word-2"] -pub mod sgi_key1b; -#[doc = "sgi_key1c (rw) register accessor: Input Key register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1c`] module"] -#[doc(alias = "sgi_key1c")] -pub type SgiKey1c = crate::Reg; -#[doc = "Input Key register 1 - Word-1"] -pub mod sgi_key1c; -#[doc = "sgi_key1d (rw) register accessor: Input Key register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key1d`] module"] -#[doc(alias = "sgi_key1d")] -pub type SgiKey1d = crate::Reg; -#[doc = "Input Key register 1 - Word-0"] -pub mod sgi_key1d; -#[doc = "sgi_key2a (rw) register accessor: Input Key register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2a`] module"] -#[doc(alias = "sgi_key2a")] -pub type SgiKey2a = crate::Reg; -#[doc = "Input Key register 2 - Word-3"] -pub mod sgi_key2a; -#[doc = "sgi_key2b (rw) register accessor: Input Key register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2b`] module"] -#[doc(alias = "sgi_key2b")] -pub type SgiKey2b = crate::Reg; -#[doc = "Input Key register 2 - Word-2"] -pub mod sgi_key2b; -#[doc = "sgi_key2c (rw) register accessor: Input Key register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2c`] module"] -#[doc(alias = "sgi_key2c")] -pub type SgiKey2c = crate::Reg; -#[doc = "Input Key register 2 - Word-1"] -pub mod sgi_key2c; -#[doc = "sgi_key2d (rw) register accessor: Input Key register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key2d`] module"] -#[doc(alias = "sgi_key2d")] -pub type SgiKey2d = crate::Reg; -#[doc = "Input Key register 2 - Word-0"] -pub mod sgi_key2d; -#[doc = "sgi_key3a (rw) register accessor: Input Key register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3a`] module"] -#[doc(alias = "sgi_key3a")] -pub type SgiKey3a = crate::Reg; -#[doc = "Input Key register 3 - Word-3"] -pub mod sgi_key3a; -#[doc = "sgi_key3b (rw) register accessor: Input Key register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3b`] module"] -#[doc(alias = "sgi_key3b")] -pub type SgiKey3b = crate::Reg; -#[doc = "Input Key register 3 - Word-2"] -pub mod sgi_key3b; -#[doc = "sgi_key3c (rw) register accessor: Input Key register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3c`] module"] -#[doc(alias = "sgi_key3c")] -pub type SgiKey3c = crate::Reg; -#[doc = "Input Key register 3 - Word-1"] -pub mod sgi_key3c; -#[doc = "sgi_key3d (rw) register accessor: Input Key register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key3d`] module"] -#[doc(alias = "sgi_key3d")] -pub type SgiKey3d = crate::Reg; -#[doc = "Input Key register 3 - Word-0"] -pub mod sgi_key3d; -#[doc = "sgi_key4a (rw) register accessor: Input Key register 4 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4a`] module"] -#[doc(alias = "sgi_key4a")] -pub type SgiKey4a = crate::Reg; -#[doc = "Input Key register 4 - Word-3"] -pub mod sgi_key4a; -#[doc = "sgi_key4b (rw) register accessor: Input Key register 4 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4b`] module"] -#[doc(alias = "sgi_key4b")] -pub type SgiKey4b = crate::Reg; -#[doc = "Input Key register 4 - Word-2"] -pub mod sgi_key4b; -#[doc = "sgi_key4c (rw) register accessor: Input Key register 4 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4c`] module"] -#[doc(alias = "sgi_key4c")] -pub type SgiKey4c = crate::Reg; -#[doc = "Input Key register 4 - Word-1"] -pub mod sgi_key4c; -#[doc = "sgi_key4d (rw) register accessor: Input Key register 4 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key4d`] module"] -#[doc(alias = "sgi_key4d")] -pub type SgiKey4d = crate::Reg; -#[doc = "Input Key register 4 - Word-0"] -pub mod sgi_key4d; -#[doc = "sgi_key5a (rw) register accessor: Input Key register 5 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5a`] module"] -#[doc(alias = "sgi_key5a")] -pub type SgiKey5a = crate::Reg; -#[doc = "Input Key register 5 - Word-3"] -pub mod sgi_key5a; -#[doc = "sgi_key5b (rw) register accessor: Input Key register 5 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5b`] module"] -#[doc(alias = "sgi_key5b")] -pub type SgiKey5b = crate::Reg; -#[doc = "Input Key register 5 - Word-2"] -pub mod sgi_key5b; -#[doc = "sgi_key5c (rw) register accessor: Input Key register 5 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5c`] module"] -#[doc(alias = "sgi_key5c")] -pub type SgiKey5c = crate::Reg; -#[doc = "Input Key register 5 - Word-1"] -pub mod sgi_key5c; -#[doc = "sgi_key5d (rw) register accessor: Input Key register 5 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key5d`] module"] -#[doc(alias = "sgi_key5d")] -pub type SgiKey5d = crate::Reg; -#[doc = "Input Key register 5 - Word-0"] -pub mod sgi_key5d; -#[doc = "sgi_key6a (rw) register accessor: Input Key register 6 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6a`] module"] -#[doc(alias = "sgi_key6a")] -pub type SgiKey6a = crate::Reg; -#[doc = "Input Key register 6 - Word-3"] -pub mod sgi_key6a; -#[doc = "sgi_key6b (rw) register accessor: Input Key register 6 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6b`] module"] -#[doc(alias = "sgi_key6b")] -pub type SgiKey6b = crate::Reg; -#[doc = "Input Key register 6 - Word-2"] -pub mod sgi_key6b; -#[doc = "sgi_key6c (rw) register accessor: Input Key register 6 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6c`] module"] -#[doc(alias = "sgi_key6c")] -pub type SgiKey6c = crate::Reg; -#[doc = "Input Key register 6 - Word-1"] -pub mod sgi_key6c; -#[doc = "sgi_key6d (rw) register accessor: Input Key register 6 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key6d`] module"] -#[doc(alias = "sgi_key6d")] -pub type SgiKey6d = crate::Reg; -#[doc = "Input Key register 6 - Word-0"] -pub mod sgi_key6d; -#[doc = "sgi_key7a (rw) register accessor: Input Key register 7 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7a::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7a::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7a`] module"] -#[doc(alias = "sgi_key7a")] -pub type SgiKey7a = crate::Reg; -#[doc = "Input Key register 7 - Word-3"] -pub mod sgi_key7a; -#[doc = "sgi_key7b (rw) register accessor: Input Key register 7 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7b::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7b::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7b`] module"] -#[doc(alias = "sgi_key7b")] -pub type SgiKey7b = crate::Reg; -#[doc = "Input Key register 7 - Word-2"] -pub mod sgi_key7b; -#[doc = "sgi_key7c (rw) register accessor: Input Key register 7 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7c`] module"] -#[doc(alias = "sgi_key7c")] -pub type SgiKey7c = crate::Reg; -#[doc = "Input Key register 7 - Word-1"] -pub mod sgi_key7c; -#[doc = "sgi_key7d (rw) register accessor: Input Key register 7 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7d::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7d::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key7d`] module"] -#[doc(alias = "sgi_key7d")] -pub type SgiKey7d = crate::Reg; -#[doc = "Input Key register 7 - Word-0"] -pub mod sgi_key7d; -#[doc = "sgi_datouta (rw) register accessor: Output Data register - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datouta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datouta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datouta`] module"] -#[doc(alias = "sgi_datouta")] -pub type SgiDatouta = crate::Reg; -#[doc = "Output Data register - Word-3"] -pub mod sgi_datouta; -#[doc = "sgi_datoutb (rw) register accessor: Output Data register - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datoutb`] module"] -#[doc(alias = "sgi_datoutb")] -pub type SgiDatoutb = crate::Reg; -#[doc = "Output Data register - Word-2"] -pub mod sgi_datoutb; -#[doc = "sgi_datoutc (rw) register accessor: Output Data register - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datoutc`] module"] -#[doc(alias = "sgi_datoutc")] -pub type SgiDatoutc = crate::Reg; -#[doc = "Output Data register - Word-1"] -pub mod sgi_datoutc; -#[doc = "sgi_datoutd (rw) register accessor: Output Data register - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_datoutd`] module"] -#[doc(alias = "sgi_datoutd")] -pub type SgiDatoutd = crate::Reg; -#[doc = "Output Data register - Word-0"] -pub mod sgi_datoutd; -#[doc = "sgi_status (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_status`] module"] -#[doc(alias = "sgi_status")] -pub type SgiStatus = crate::Reg; -#[doc = "Status register"] -pub mod sgi_status; -#[doc = "sgi_count (rw) register accessor: Calculation counter\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_count`] module"] -#[doc(alias = "sgi_count")] -pub type SgiCount = crate::Reg; -#[doc = "Calculation counter"] -pub mod sgi_count; -#[doc = "sgi_keychk (rw) register accessor: Key checksum register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_keychk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_keychk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_keychk`] module"] -#[doc(alias = "sgi_keychk")] -pub type SgiKeychk = crate::Reg; -#[doc = "Key checksum register"] -pub mod sgi_keychk; -#[doc = "sgi_ctrl (rw) register accessor: SGI Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_ctrl`] module"] -#[doc(alias = "sgi_ctrl")] -pub type SgiCtrl = crate::Reg; -#[doc = "SGI Control register"] -pub mod sgi_ctrl; -#[doc = "sgi_ctrl2 (rw) register accessor: SGI Control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_ctrl2`] module"] -#[doc(alias = "sgi_ctrl2")] -pub type SgiCtrl2 = crate::Reg; -#[doc = "SGI Control register 2"] -pub mod sgi_ctrl2; -#[doc = "sgi_dummy_ctrl (rw) register accessor: Configuration of dummy controls\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_dummy_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_dummy_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_dummy_ctrl`] module"] -#[doc(alias = "sgi_dummy_ctrl")] -pub type SgiDummyCtrl = crate::Reg; -#[doc = "Configuration of dummy controls"] -pub mod sgi_dummy_ctrl; -#[doc = "sgi_sfr_sw_mask (rw) register accessor: Sofware Assisted Masking register .\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfr_sw_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfr_sw_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sfr_sw_mask`] module"] -#[doc(alias = "sgi_sfr_sw_mask")] -pub type SgiSfrSwMask = crate::Reg; -#[doc = "Sofware Assisted Masking register ."] -pub mod sgi_sfr_sw_mask; -#[doc = "sgi_sfrseed (rw) register accessor: SFRSEED register for SFRMASK feature.\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfrseed::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfrseed::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sfrseed`] module"] -#[doc(alias = "sgi_sfrseed")] -pub type SgiSfrseed = crate::Reg; -#[doc = "SFRSEED register for SFRMASK feature."] -pub mod sgi_sfrseed; -#[doc = "sgi_sha2_ctrl (rw) register accessor: SHA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sha2_ctrl`] module"] -#[doc(alias = "sgi_sha2_ctrl")] -pub type SgiSha2Ctrl = crate::Reg; -#[doc = "SHA Control Register"] -pub mod sgi_sha2_ctrl; -#[doc = "sgi_sha_fifo (rw) register accessor: SHA FIFO lower-bank low\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha_fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha_fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_sha_fifo`] module"] -#[doc(alias = "sgi_sha_fifo")] -pub type SgiShaFifo = crate::Reg; -#[doc = "SHA FIFO lower-bank low"] -pub mod sgi_sha_fifo; -#[doc = "sgi_config (r) register accessor: SHA Configuration Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_config`] module"] -#[doc(alias = "sgi_config")] -pub type SgiConfig = crate::Reg; -#[doc = "SHA Configuration Reg"] -pub mod sgi_config; -#[doc = "sgi_config2 (r) register accessor: SHA Configuration 2 Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_config2`] module"] -#[doc(alias = "sgi_config2")] -pub type SgiConfig2 = crate::Reg; -#[doc = "SHA Configuration 2 Reg"] -pub mod sgi_config2; -#[doc = "sgi_auto_mode (rw) register accessor: SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_auto_mode`] module"] -#[doc(alias = "sgi_auto_mode")] -pub type SgiAutoMode = crate::Reg; -#[doc = "SGI Auto Mode Control register"] -pub mod sgi_auto_mode; -#[doc = "sgi_auto_dma_ctrl (rw) register accessor: SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_dma_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_dma_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_auto_dma_ctrl`] module"] -#[doc(alias = "sgi_auto_dma_ctrl")] -pub type SgiAutoDmaCtrl = crate::Reg; -#[doc = "SGI Auto Mode Control register"] -pub mod sgi_auto_dma_ctrl; -#[doc = "sgi_prng_sw_seed (rw) register accessor: SGI internal PRNG SW seeding register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_prng_sw_seed::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_prng_sw_seed::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_prng_sw_seed`] module"] -#[doc(alias = "sgi_prng_sw_seed")] -pub type SgiPrngSwSeed = crate::Reg; -#[doc = "SGI internal PRNG SW seeding register"] -pub mod sgi_prng_sw_seed; -#[doc = "sgi_key_ctrl (rw) register accessor: SGI Key Control SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key_ctrl`] module"] -#[doc(alias = "sgi_key_ctrl")] -pub type SgiKeyCtrl = crate::Reg; -#[doc = "SGI Key Control SFR"] -pub mod sgi_key_ctrl; -#[doc = "sgi_key_wrap (r) register accessor: Wrapped key read SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_wrap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_key_wrap`] module"] -#[doc(alias = "sgi_key_wrap")] -pub type SgiKeyWrap = crate::Reg; -#[doc = "Wrapped key read SFR"] -pub mod sgi_key_wrap; -#[doc = "sgi_version (r) register accessor: SGI Version\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_version`] module"] -#[doc(alias = "sgi_version")] -pub type SgiVersion = crate::Reg; -#[doc = "SGI Version"] -pub mod sgi_version; -#[doc = "sgi_access_err (rw) register accessor: Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_access_err`] module"] -#[doc(alias = "sgi_access_err")] -pub type SgiAccessErr = crate::Reg; -#[doc = "Access Error"] -pub mod sgi_access_err; -#[doc = "sgi_access_err_clr (rw) register accessor: Clear Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_access_err_clr`] module"] -#[doc(alias = "sgi_access_err_clr")] -pub type SgiAccessErrClr = crate::Reg; -#[doc = "Clear Access Error"] -pub mod sgi_access_err_clr; -#[doc = "sgi_int_status (r) register accessor: Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_status`] module"] -#[doc(alias = "sgi_int_status")] -pub type SgiIntStatus = crate::Reg; -#[doc = "Interrupt status"] -pub mod sgi_int_status; -#[doc = "sgi_int_enable (rw) register accessor: Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_enable`] module"] -#[doc(alias = "sgi_int_enable")] -pub type SgiIntEnable = crate::Reg; -#[doc = "Interrupt enable"] -pub mod sgi_int_enable; -#[doc = "sgi_int_status_clr (rw) register accessor: Interrupt status clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_status_clr`] module"] -#[doc(alias = "sgi_int_status_clr")] -pub type SgiIntStatusClr = crate::Reg; -#[doc = "Interrupt status clear"] -pub mod sgi_int_status_clr; -#[doc = "sgi_int_status_set (rw) register accessor: Interrupt status set\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_int_status_set`] module"] -#[doc(alias = "sgi_int_status_set")] -pub type SgiIntStatusSet = crate::Reg; -#[doc = "Interrupt status set"] -pub mod sgi_int_status_set; -#[doc = "sgi_module_id (r) register accessor: Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_module_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sgi_module_id`] module"] -#[doc(alias = "sgi_module_id")] -pub type SgiModuleId = crate::Reg; -#[doc = "Module ID"] -pub mod sgi_module_id; diff --git a/mcxa276-pac/src/sgi0/sgi_access_err.rs b/mcxa276-pac/src/sgi0/sgi_access_err.rs deleted file mode 100644 index 8eeef6094..000000000 --- a/mcxa276-pac/src/sgi0/sgi_access_err.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `sgi_access_err` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_access_err` writer"] -pub type W = crate::W; -#[doc = "Field `apb_notav` reader - APB Error: address not available"] -pub type ApbNotavR = crate::BitReader; -#[doc = "Field `apb_notav` writer - APB Error: address not available"] -pub type ApbNotavW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `apb_wrgmd` reader - APB Error: Wrong access mode"] -pub type ApbWrgmdR = crate::BitReader; -#[doc = "Field `apb_wrgmd` writer - APB Error: Wrong access mode"] -pub type ApbWrgmdW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `accerr_rsvd1` reader - reserved for future erors on SPB I/F"] -pub type AccerrRsvd1R = crate::FieldReader; -#[doc = "Field `apb_master` reader - APB Master that triggered first APB error"] -pub type ApbMasterR = crate::FieldReader; -#[doc = "Field `apb_master` writer - APB Master that triggered first APB error"] -pub type ApbMasterW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `accerr_rsvd2` reader - reserved for more block errors"] -pub type AccerrRsvd2R = crate::FieldReader; -impl R { - #[doc = "Bit 0 - APB Error: address not available"] - #[inline(always)] - pub fn apb_notav(&self) -> ApbNotavR { - ApbNotavR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - APB Error: Wrong access mode"] - #[inline(always)] - pub fn apb_wrgmd(&self) -> ApbWrgmdR { - ApbWrgmdR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - reserved for future erors on SPB I/F"] - #[inline(always)] - pub fn accerr_rsvd1(&self) -> AccerrRsvd1R { - AccerrRsvd1R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:7 - APB Master that triggered first APB error"] - #[inline(always)] - pub fn apb_master(&self) -> ApbMasterR { - ApbMasterR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:31 - reserved for more block errors"] - #[inline(always)] - pub fn accerr_rsvd2(&self) -> AccerrRsvd2R { - AccerrRsvd2R::new((self.bits >> 8) & 0x00ff_ffff) - } -} -impl W { - #[doc = "Bit 0 - APB Error: address not available"] - #[inline(always)] - pub fn apb_notav(&mut self) -> ApbNotavW { - ApbNotavW::new(self, 0) - } - #[doc = "Bit 1 - APB Error: Wrong access mode"] - #[inline(always)] - pub fn apb_wrgmd(&mut self) -> ApbWrgmdW { - ApbWrgmdW::new(self, 1) - } - #[doc = "Bits 4:7 - APB Master that triggered first APB error"] - #[inline(always)] - pub fn apb_master(&mut self) -> ApbMasterW { - ApbMasterW::new(self, 4) - } -} -#[doc = "Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiAccessErrSpec; -impl crate::RegisterSpec for SgiAccessErrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_access_err::R`](R) reader structure"] -impl crate::Readable for SgiAccessErrSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_access_err::W`](W) writer structure"] -impl crate::Writable for SgiAccessErrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_access_err to value 0"] -impl crate::Resettable for SgiAccessErrSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_access_err_clr.rs b/mcxa276-pac/src/sgi0/sgi_access_err_clr.rs deleted file mode 100644 index c459674d7..000000000 --- a/mcxa276-pac/src/sgi0/sgi_access_err_clr.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `sgi_access_err_clr` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_access_err_clr` writer"] -pub type W = crate::W; -#[doc = "Field `err_clr` reader - Write to reset SGI_ACCESS_ERR SFR."] -pub type ErrClrR = crate::BitReader; -#[doc = "Field `err_clr` writer - Write to reset SGI_ACCESS_ERR SFR."] -pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `accerrc_rsvd` reader - reserved"] -pub type AccerrcRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Write to reset SGI_ACCESS_ERR SFR."] - #[inline(always)] - pub fn err_clr(&self) -> ErrClrR { - ErrClrR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:31 - reserved"] - #[inline(always)] - pub fn accerrc_rsvd(&self) -> AccerrcRsvdR { - AccerrcRsvdR::new((self.bits >> 1) & 0x7fff_ffff) - } -} -impl W { - #[doc = "Bit 0 - Write to reset SGI_ACCESS_ERR SFR."] - #[inline(always)] - pub fn err_clr(&mut self) -> ErrClrW { - ErrClrW::new(self, 0) - } -} -#[doc = "Clear Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiAccessErrClrSpec; -impl crate::RegisterSpec for SgiAccessErrClrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_access_err_clr::R`](R) reader structure"] -impl crate::Readable for SgiAccessErrClrSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_access_err_clr::W`](W) writer structure"] -impl crate::Writable for SgiAccessErrClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_access_err_clr to value 0"] -impl crate::Resettable for SgiAccessErrClrSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs deleted file mode 100644 index d27c4667b..000000000 --- a/mcxa276-pac/src/sgi0/sgi_auto_dma_ctrl.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `sgi_auto_dma_ctrl` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_auto_dma_ctrl` writer"] -pub type W = crate::W; -#[doc = "Field `ife` reader - Input FIFO DMA Enable"] -pub type IfeR = crate::BitReader; -#[doc = "Field `ife` writer - Input FIFO DMA Enable"] -pub type IfeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `auto_dma_rsvd1` reader - reserved"] -pub type AutoDmaRsvd1R = crate::FieldReader; -#[doc = "Field `ofe` reader - Ouput FIFO DMA Enable"] -pub type OfeR = crate::BitReader; -#[doc = "Field `ofe` writer - Ouput FIFO DMA Enable"] -pub type OfeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `auto_dma_rsvd2` reader - reserved"] -pub type AutoDmaRsvd2R = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Input FIFO DMA Enable"] - #[inline(always)] - pub fn ife(&self) -> IfeR { - IfeR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:7 - reserved"] - #[inline(always)] - pub fn auto_dma_rsvd1(&self) -> AutoDmaRsvd1R { - AutoDmaRsvd1R::new(((self.bits >> 1) & 0x7f) as u8) - } - #[doc = "Bit 8 - Ouput FIFO DMA Enable"] - #[inline(always)] - pub fn ofe(&self) -> OfeR { - OfeR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 9:31 - reserved"] - #[inline(always)] - pub fn auto_dma_rsvd2(&self) -> AutoDmaRsvd2R { - AutoDmaRsvd2R::new((self.bits >> 9) & 0x007f_ffff) - } -} -impl W { - #[doc = "Bit 0 - Input FIFO DMA Enable"] - #[inline(always)] - pub fn ife(&mut self) -> IfeW { - IfeW::new(self, 0) - } - #[doc = "Bit 8 - Ouput FIFO DMA Enable"] - #[inline(always)] - pub fn ofe(&mut self) -> OfeW { - OfeW::new(self, 8) - } -} -#[doc = "SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_dma_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_dma_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiAutoDmaCtrlSpec; -impl crate::RegisterSpec for SgiAutoDmaCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_auto_dma_ctrl::R`](R) reader structure"] -impl crate::Readable for SgiAutoDmaCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_auto_dma_ctrl::W`](W) writer structure"] -impl crate::Writable for SgiAutoDmaCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_auto_dma_ctrl to value 0"] -impl crate::Resettable for SgiAutoDmaCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_auto_mode.rs b/mcxa276-pac/src/sgi0/sgi_auto_mode.rs deleted file mode 100644 index 0ae39991a..000000000 --- a/mcxa276-pac/src/sgi0/sgi_auto_mode.rs +++ /dev/null @@ -1,199 +0,0 @@ -#[doc = "Register `sgi_auto_mode` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_auto_mode` writer"] -pub type W = crate::W; -#[doc = "Field `auto_mode_en` reader - auto_start_en"] -pub type AutoModeEnR = crate::BitReader; -#[doc = "Field `auto_mode_en` writer - auto_start_en"] -pub type AutoModeEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `auto_mode_stop` writer - auto_mode_stop"] -pub type AutoModeStopW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `auto_mode_rsvd1` reader - reserved"] -pub type AutoModeRsvd1R = crate::FieldReader; -#[doc = "Field `incr_mode` reader - CTR increment mode"] -pub type IncrModeR = crate::FieldReader; -#[doc = "Field `incr_mode` writer - CTR increment mode"] -pub type IncrModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `auto_mode_rsvd2` reader - reserved"] -pub type AutoModeRsvd2R = crate::FieldReader; -#[doc = "Auto mode of operation\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cmd { - #[doc = "0: 8'h00 - ECB mode"] - Ecb = 0, - #[doc = "1: 8'h01 - CTR mode"] - Ctr = 1, - #[doc = "2: 8'h02 - CBC mode"] - Cbc = 2, - #[doc = "3: 8'h03 - CBCMAC mode"] - Cbcmac = 3, - #[doc = "16: 8'h10 - Key Wrap/Unwrap(128 bit key data)"] - Kw128 = 16, - #[doc = "17: 8'h11 - Key Wrap/Unwrap(256 bit key data)"] - Kw256 = 17, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cmd) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cmd { - type Ux = u8; -} -impl crate::IsEnum for Cmd {} -#[doc = "Field `cmd` reader - Auto mode of operation"] -pub type CmdR = crate::FieldReader; -impl CmdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cmd::Ecb), - 1 => Some(Cmd::Ctr), - 2 => Some(Cmd::Cbc), - 3 => Some(Cmd::Cbcmac), - 16 => Some(Cmd::Kw128), - 17 => Some(Cmd::Kw256), - _ => None, - } - } - #[doc = "8'h00 - ECB mode"] - #[inline(always)] - pub fn is_ecb(&self) -> bool { - *self == Cmd::Ecb - } - #[doc = "8'h01 - CTR mode"] - #[inline(always)] - pub fn is_ctr(&self) -> bool { - *self == Cmd::Ctr - } - #[doc = "8'h02 - CBC mode"] - #[inline(always)] - pub fn is_cbc(&self) -> bool { - *self == Cmd::Cbc - } - #[doc = "8'h03 - CBCMAC mode"] - #[inline(always)] - pub fn is_cbcmac(&self) -> bool { - *self == Cmd::Cbcmac - } - #[doc = "8'h10 - Key Wrap/Unwrap(128 bit key data)"] - #[inline(always)] - pub fn is_kw128(&self) -> bool { - *self == Cmd::Kw128 - } - #[doc = "8'h11 - Key Wrap/Unwrap(256 bit key data)"] - #[inline(always)] - pub fn is_kw256(&self) -> bool { - *self == Cmd::Kw256 - } -} -#[doc = "Field `cmd` writer - Auto mode of operation"] -pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 8, Cmd>; -impl<'a, REG> CmdW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "8'h00 - ECB mode"] - #[inline(always)] - pub fn ecb(self) -> &'a mut crate::W { - self.variant(Cmd::Ecb) - } - #[doc = "8'h01 - CTR mode"] - #[inline(always)] - pub fn ctr(self) -> &'a mut crate::W { - self.variant(Cmd::Ctr) - } - #[doc = "8'h02 - CBC mode"] - #[inline(always)] - pub fn cbc(self) -> &'a mut crate::W { - self.variant(Cmd::Cbc) - } - #[doc = "8'h03 - CBCMAC mode"] - #[inline(always)] - pub fn cbcmac(self) -> &'a mut crate::W { - self.variant(Cmd::Cbcmac) - } - #[doc = "8'h10 - Key Wrap/Unwrap(128 bit key data)"] - #[inline(always)] - pub fn kw128(self) -> &'a mut crate::W { - self.variant(Cmd::Kw128) - } - #[doc = "8'h11 - Key Wrap/Unwrap(256 bit key data)"] - #[inline(always)] - pub fn kw256(self) -> &'a mut crate::W { - self.variant(Cmd::Kw256) - } -} -#[doc = "Field `auto_mode_rsvd3` reader - reserved"] -pub type AutoModeRsvd3R = crate::FieldReader; -impl R { - #[doc = "Bit 0 - auto_start_en"] - #[inline(always)] - pub fn auto_mode_en(&self) -> AutoModeEnR { - AutoModeEnR::new((self.bits & 1) != 0) - } - #[doc = "Bits 2:3 - reserved"] - #[inline(always)] - pub fn auto_mode_rsvd1(&self) -> AutoModeRsvd1R { - AutoModeRsvd1R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - CTR increment mode"] - #[inline(always)] - pub fn incr_mode(&self) -> IncrModeR { - IncrModeR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - reserved"] - #[inline(always)] - pub fn auto_mode_rsvd2(&self) -> AutoModeRsvd2R { - AutoModeRsvd2R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:15 - Auto mode of operation"] - #[inline(always)] - pub fn cmd(&self) -> CmdR { - CmdR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:31 - reserved"] - #[inline(always)] - pub fn auto_mode_rsvd3(&self) -> AutoModeRsvd3R { - AutoModeRsvd3R::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bit 0 - auto_start_en"] - #[inline(always)] - pub fn auto_mode_en(&mut self) -> AutoModeEnW { - AutoModeEnW::new(self, 0) - } - #[doc = "Bit 1 - auto_mode_stop"] - #[inline(always)] - pub fn auto_mode_stop(&mut self) -> AutoModeStopW { - AutoModeStopW::new(self, 1) - } - #[doc = "Bits 4:5 - CTR increment mode"] - #[inline(always)] - pub fn incr_mode(&mut self) -> IncrModeW { - IncrModeW::new(self, 4) - } - #[doc = "Bits 8:15 - Auto mode of operation"] - #[inline(always)] - pub fn cmd(&mut self) -> CmdW { - CmdW::new(self, 8) - } -} -#[doc = "SGI Auto Mode Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_auto_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_auto_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiAutoModeSpec; -impl crate::RegisterSpec for SgiAutoModeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_auto_mode::R`](R) reader structure"] -impl crate::Readable for SgiAutoModeSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_auto_mode::W`](W) writer structure"] -impl crate::Writable for SgiAutoModeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_auto_mode to value 0"] -impl crate::Resettable for SgiAutoModeSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_config.rs b/mcxa276-pac/src/sgi0/sgi_config.rs deleted file mode 100644 index 1d6091ed9..000000000 --- a/mcxa276-pac/src/sgi0/sgi_config.rs +++ /dev/null @@ -1,188 +0,0 @@ -#[doc = "Register `sgi_config` reader"] -pub type R = crate::R; -#[doc = "Field `row` reader - SGI Diversified for 'ROW'"] -pub type RowR = crate::BitReader; -#[doc = "Field `china` reader - SGI Diversified for 'CHINA'"] -pub type ChinaR = crate::BitReader; -#[doc = "Field `cc` reader - SGI Diversified for 'CC'"] -pub type CcR = crate::BitReader; -#[doc = "Field `has_aes` reader - HAS AES"] -pub type HasAesR = crate::BitReader; -#[doc = "Field `has_des` reader - HAS DES"] -pub type HasDesR = crate::BitReader; -#[doc = "Field `has_sha` reader - HAS SHA"] -pub type HasShaR = crate::BitReader; -#[doc = "Field `has_movem` reader - HAS MOVEM"] -pub type HasMovemR = crate::BitReader; -#[doc = "Field `has_cmac` reader - HAS CMAC"] -pub type HasCmacR = crate::BitReader; -#[doc = "Field `has_gfmul` reader - HAS GFMUL"] -pub type HasGfmulR = crate::BitReader; -#[doc = "Field `internal_prng` reader - HAS INTERNAL PRNG"] -pub type InternalPrngR = crate::BitReader; -#[doc = "Field `key_digest` reader - HAS KEY DIGEST"] -pub type KeyDigestR = crate::BitReader; -#[doc = "Field `count_size` reader - 0 - COUNT=16, 1 - COUNT=32"] -pub type CountSizeR = crate::BitReader; -#[doc = "Field `configc_rsvd` reader - reserved"] -pub type ConfigcRsvdR = crate::BitReader; -#[doc = "Field `fa` reader - HAS FA protection"] -pub type FaR = crate::BitReader; -#[doc = "Field `configb2_rsvd` reader - reserved"] -pub type Configb2RsvdR = crate::BitReader; -#[doc = "Field `bus_width` reader - 0 - BUS_WIDTH=16, 1 - BUS_WIDTH=32"] -pub type BusWidthR = crate::BitReader; -#[doc = "Field `num_datin` reader - NUMBER OF DATIN REGBANKS"] -pub type NumDatinR = crate::FieldReader; -#[doc = "Field `num_key` reader - NUMBER OR KEY REGBANKS"] -pub type NumKeyR = crate::FieldReader; -#[doc = "Field `edc` reader - DATIN to KERNEL End-to-end EDC is enabled"] -pub type EdcR = crate::BitReader; -#[doc = "Field `configb_rsvd` reader - reserved"] -pub type ConfigbRsvdR = crate::FieldReader; -#[doc = "Field `sha_256_only` reader - HAS SHA-256 ONLY"] -pub type Sha256OnlyR = crate::BitReader; -#[doc = "Field `spb_support` reader - ID_CFG_SGI_SPB_SUPPORT is set"] -pub type SpbSupportR = crate::BitReader; -#[doc = "Field `spb_masking` reader - ID_CFG_SGI_SPB_MASKING is set"] -pub type SpbMaskingR = crate::BitReader; -#[doc = "Field `sfr_sw_mask` reader - ID_CFG_SGI_USE_SFR_SW_MASK is set"] -pub type SfrSwMaskR = crate::BitReader; -#[doc = "Field `configa_rsvd` reader - reserved"] -pub type ConfigaRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - SGI Diversified for 'ROW'"] - #[inline(always)] - pub fn row(&self) -> RowR { - RowR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SGI Diversified for 'CHINA'"] - #[inline(always)] - pub fn china(&self) -> ChinaR { - ChinaR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - SGI Diversified for 'CC'"] - #[inline(always)] - pub fn cc(&self) -> CcR { - CcR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - HAS AES"] - #[inline(always)] - pub fn has_aes(&self) -> HasAesR { - HasAesR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - HAS DES"] - #[inline(always)] - pub fn has_des(&self) -> HasDesR { - HasDesR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - HAS SHA"] - #[inline(always)] - pub fn has_sha(&self) -> HasShaR { - HasShaR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - HAS MOVEM"] - #[inline(always)] - pub fn has_movem(&self) -> HasMovemR { - HasMovemR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - HAS CMAC"] - #[inline(always)] - pub fn has_cmac(&self) -> HasCmacR { - HasCmacR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - HAS GFMUL"] - #[inline(always)] - pub fn has_gfmul(&self) -> HasGfmulR { - HasGfmulR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - HAS INTERNAL PRNG"] - #[inline(always)] - pub fn internal_prng(&self) -> InternalPrngR { - InternalPrngR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - HAS KEY DIGEST"] - #[inline(always)] - pub fn key_digest(&self) -> KeyDigestR { - KeyDigestR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - 0 - COUNT=16, 1 - COUNT=32"] - #[inline(always)] - pub fn count_size(&self) -> CountSizeR { - CountSizeR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - reserved"] - #[inline(always)] - pub fn configc_rsvd(&self) -> ConfigcRsvdR { - ConfigcRsvdR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - HAS FA protection"] - #[inline(always)] - pub fn fa(&self) -> FaR { - FaR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - reserved"] - #[inline(always)] - pub fn configb2_rsvd(&self) -> Configb2RsvdR { - Configb2RsvdR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - 0 - BUS_WIDTH=16, 1 - BUS_WIDTH=32"] - #[inline(always)] - pub fn bus_width(&self) -> BusWidthR { - BusWidthR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:17 - NUMBER OF DATIN REGBANKS"] - #[inline(always)] - pub fn num_datin(&self) -> NumDatinR { - NumDatinR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:20 - NUMBER OR KEY REGBANKS"] - #[inline(always)] - pub fn num_key(&self) -> NumKeyR { - NumKeyR::new(((self.bits >> 18) & 7) as u8) - } - #[doc = "Bit 21 - DATIN to KERNEL End-to-end EDC is enabled"] - #[inline(always)] - pub fn edc(&self) -> EdcR { - EdcR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bits 22:23 - reserved"] - #[inline(always)] - pub fn configb_rsvd(&self) -> ConfigbRsvdR { - ConfigbRsvdR::new(((self.bits >> 22) & 3) as u8) - } - #[doc = "Bit 24 - HAS SHA-256 ONLY"] - #[inline(always)] - pub fn sha_256_only(&self) -> Sha256OnlyR { - Sha256OnlyR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - ID_CFG_SGI_SPB_SUPPORT is set"] - #[inline(always)] - pub fn spb_support(&self) -> SpbSupportR { - SpbSupportR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - ID_CFG_SGI_SPB_MASKING is set"] - #[inline(always)] - pub fn spb_masking(&self) -> SpbMaskingR { - SpbMaskingR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - ID_CFG_SGI_USE_SFR_SW_MASK is set"] - #[inline(always)] - pub fn sfr_sw_mask(&self) -> SfrSwMaskR { - SfrSwMaskR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:31 - reserved"] - #[inline(always)] - pub fn configa_rsvd(&self) -> ConfigaRsvdR { - ConfigaRsvdR::new(((self.bits >> 28) & 0x0f) as u8) - } -} -#[doc = "SHA Configuration Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiConfigSpec; -impl crate::RegisterSpec for SgiConfigSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_config::R`](R) reader structure"] -impl crate::Readable for SgiConfigSpec {} -#[doc = "`reset()` method sets sgi_config to value 0"] -impl crate::Resettable for SgiConfigSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_config2.rs b/mcxa276-pac/src/sgi0/sgi_config2.rs deleted file mode 100644 index b8a3cc27c..000000000 --- a/mcxa276-pac/src/sgi0/sgi_config2.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[doc = "Register `sgi_config2` reader"] -pub type R = crate::R; -#[doc = "Field `aes_used` reader - 0=Apollo; 1=Aegis; 2=Ayna; 3=Athenium; 4=Ajax;"] -pub type AesUsedR = crate::FieldReader; -#[doc = "Field `aes_num_sboxes` reader - Number of AES sboxes"] -pub type AesNumSboxesR = crate::FieldReader; -#[doc = "Field `aes_keysize` reader - 0=128-Only,1=192-Only, 2=256-Only, 3=All Keysizes"] -pub type AesKeysizeR = crate::FieldReader; -#[doc = "Field `config2b_rsvd` reader - reserved"] -pub type Config2bRsvdR = crate::FieldReader; -#[doc = "Field `des_used` reader - 0=Dakar; 1=Danube; 2=Depicta; 3=Digi; 4=Date;"] -pub type DesUsedR = crate::FieldReader; -#[doc = "Field `des_num_sboxes` reader - Number of DES sboxes"] -pub type DesNumSboxesR = crate::FieldReader; -#[doc = "Field `config2a_rsvd` reader - reserved"] -pub type Config2aRsvdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - 0=Apollo; 1=Aegis; 2=Ayna; 3=Athenium; 4=Ajax;"] - #[inline(always)] - pub fn aes_used(&self) -> AesUsedR { - AesUsedR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:8 - Number of AES sboxes"] - #[inline(always)] - pub fn aes_num_sboxes(&self) -> AesNumSboxesR { - AesNumSboxesR::new(((self.bits >> 4) & 0x1f) as u8) - } - #[doc = "Bits 9:10 - 0=128-Only,1=192-Only, 2=256-Only, 3=All Keysizes"] - #[inline(always)] - pub fn aes_keysize(&self) -> AesKeysizeR { - AesKeysizeR::new(((self.bits >> 9) & 3) as u8) - } - #[doc = "Bits 11:15 - reserved"] - #[inline(always)] - pub fn config2b_rsvd(&self) -> Config2bRsvdR { - Config2bRsvdR::new(((self.bits >> 11) & 0x1f) as u8) - } - #[doc = "Bits 16:19 - 0=Dakar; 1=Danube; 2=Depicta; 3=Digi; 4=Date;"] - #[inline(always)] - pub fn des_used(&self) -> DesUsedR { - DesUsedR::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bits 20:24 - Number of DES sboxes"] - #[inline(always)] - pub fn des_num_sboxes(&self) -> DesNumSboxesR { - DesNumSboxesR::new(((self.bits >> 20) & 0x1f) as u8) - } - #[doc = "Bits 25:31 - reserved"] - #[inline(always)] - pub fn config2a_rsvd(&self) -> Config2aRsvdR { - Config2aRsvdR::new(((self.bits >> 25) & 0x7f) as u8) - } -} -#[doc = "SHA Configuration 2 Reg\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_config2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiConfig2Spec; -impl crate::RegisterSpec for SgiConfig2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_config2::R`](R) reader structure"] -impl crate::Readable for SgiConfig2Spec {} -#[doc = "`reset()` method sets sgi_config2 to value 0"] -impl crate::Resettable for SgiConfig2Spec {} diff --git a/mcxa276-pac/src/sgi0/sgi_count.rs b/mcxa276-pac/src/sgi0/sgi_count.rs deleted file mode 100644 index 16cced0a7..000000000 --- a/mcxa276-pac/src/sgi0/sgi_count.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `sgi_count` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_count` writer"] -pub type W = crate::W; -#[doc = "Field `count` reader - Calculation counter, incremented with"] -pub type CountR = crate::FieldReader; -#[doc = "Field `count` writer - Calculation counter, incremented with"] -pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `count_rsvd` reader - reserved"] -pub type CountRsvdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Calculation counter, incremented with"] - #[inline(always)] - pub fn count(&self) -> CountR { - CountR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - reserved"] - #[inline(always)] - pub fn count_rsvd(&self) -> CountRsvdR { - CountRsvdR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Calculation counter, incremented with"] - #[inline(always)] - pub fn count(&mut self) -> CountW { - CountW::new(self, 0) - } -} -#[doc = "Calculation counter\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiCountSpec; -impl crate::RegisterSpec for SgiCountSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_count::R`](R) reader structure"] -impl crate::Readable for SgiCountSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_count::W`](W) writer structure"] -impl crate::Writable for SgiCountSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_count to value 0"] -impl crate::Resettable for SgiCountSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_ctrl.rs deleted file mode 100644 index 7318a203e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_ctrl.rs +++ /dev/null @@ -1,231 +0,0 @@ -#[doc = "Register `sgi_ctrl` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_ctrl` writer"] -pub type W = crate::W; -#[doc = "Field `start` writer - Start crypto operation"] -pub type StartW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `decrypt` reader - Sets Cipher direction(AES and DES)"] -pub type DecryptR = crate::BitReader; -#[doc = "Field `decrypt` writer - Sets Cipher direction(AES and DES)"] -pub type DecryptW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `aeskeysz` reader - Sets AES key size"] -pub type AeskeyszR = crate::FieldReader; -#[doc = "Field `aeskeysz` writer - Sets AES key size"] -pub type AeskeyszW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `crypto_op` reader - Sets 'Crypto Operation' type"] -pub type CryptoOpR = crate::FieldReader; -#[doc = "Field `crypto_op` writer - Sets 'Crypto Operation' type"] -pub type CryptoOpW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `insel` reader - 4'b0000 - DATIN\\[0\\]"] -pub type InselR = crate::FieldReader; -#[doc = "Field `insel` writer - 4'b0000 - DATIN\\[0\\]"] -pub type InselW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `outsel` reader - 3'b000 - DATOUT = 'Kernel Res'"] -pub type OutselR = crate::FieldReader; -#[doc = "Field `outsel` writer - 3'b000 - DATOUT = 'Kernel Res'"] -pub type OutselW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `datout_res` reader - Kernels data out options"] -pub type DatoutResR = crate::FieldReader; -#[doc = "Field `datout_res` writer - Kernels data out options"] -pub type DatoutResW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `aes_en` reader - AES Kernel Enable"] -pub type AesEnR = crate::BitReader; -#[doc = "Field `aes_en` writer - AES Kernel Enable"] -pub type AesEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `des_en` reader - DES Kernel Enable"] -pub type DesEnR = crate::BitReader; -#[doc = "Field `des_en` writer - DES Kernel Enable"] -pub type DesEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `gcm_en` reader - GFMUL Kernel Enable"] -pub type GcmEnR = crate::BitReader; -#[doc = "Field `gcm_en` writer - GFMUL Kernel Enable"] -pub type GcmEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `prng_en` reader - PRNG Enable(only if SGI has internal PRNG, Please"] -pub type PrngEnR = crate::BitReader; -#[doc = "Field `prng_en` writer - PRNG Enable(only if SGI has internal PRNG, Please"] -pub type PrngEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `inkeysel` reader - Input key selection"] -pub type InkeyselR = crate::FieldReader; -#[doc = "Field `inkeysel` writer - Input key selection"] -pub type InkeyselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `tdeskey` reader - Triple-DES Key Configuration"] -pub type TdeskeyR = crate::BitReader; -#[doc = "Field `tdeskey` writer - Triple-DES Key Configuration"] -pub type TdeskeyW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `aes_no_kl` reader - AES No decryption key schedule"] -pub type AesNoKlR = crate::BitReader; -#[doc = "Field `aes_no_kl` writer - AES No decryption key schedule"] -pub type AesNoKlW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `aes_sel` reader - AES Dual Selection"] -pub type AesSelR = crate::BitReader; -#[doc = "Field `aes_sel` writer - AES Dual Selection"] -pub type AesSelW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ctrl_rsvd` reader - reserved"] -pub type CtrlRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 1 - Sets Cipher direction(AES and DES)"] - #[inline(always)] - pub fn decrypt(&self) -> DecryptR { - DecryptR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Sets AES key size"] - #[inline(always)] - pub fn aeskeysz(&self) -> AeskeyszR { - AeskeyszR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:6 - Sets 'Crypto Operation' type"] - #[inline(always)] - pub fn crypto_op(&self) -> CryptoOpR { - CryptoOpR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bits 7:10 - 4'b0000 - DATIN\\[0\\]"] - #[inline(always)] - pub fn insel(&self) -> InselR { - InselR::new(((self.bits >> 7) & 0x0f) as u8) - } - #[doc = "Bits 11:13 - 3'b000 - DATOUT = 'Kernel Res'"] - #[inline(always)] - pub fn outsel(&self) -> OutselR { - OutselR::new(((self.bits >> 11) & 7) as u8) - } - #[doc = "Bits 14:15 - Kernels data out options"] - #[inline(always)] - pub fn datout_res(&self) -> DatoutResR { - DatoutResR::new(((self.bits >> 14) & 3) as u8) - } - #[doc = "Bit 16 - AES Kernel Enable"] - #[inline(always)] - pub fn aes_en(&self) -> AesEnR { - AesEnR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - DES Kernel Enable"] - #[inline(always)] - pub fn des_en(&self) -> DesEnR { - DesEnR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - GFMUL Kernel Enable"] - #[inline(always)] - pub fn gcm_en(&self) -> GcmEnR { - GcmEnR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - PRNG Enable(only if SGI has internal PRNG, Please"] - #[inline(always)] - pub fn prng_en(&self) -> PrngEnR { - PrngEnR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:24 - Input key selection"] - #[inline(always)] - pub fn inkeysel(&self) -> InkeyselR { - InkeyselR::new(((self.bits >> 20) & 0x1f) as u8) - } - #[doc = "Bit 25 - Triple-DES Key Configuration"] - #[inline(always)] - pub fn tdeskey(&self) -> TdeskeyR { - TdeskeyR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - AES No decryption key schedule"] - #[inline(always)] - pub fn aes_no_kl(&self) -> AesNoKlR { - AesNoKlR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - AES Dual Selection"] - #[inline(always)] - pub fn aes_sel(&self) -> AesSelR { - AesSelR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bits 28:31 - reserved"] - #[inline(always)] - pub fn ctrl_rsvd(&self) -> CtrlRsvdR { - CtrlRsvdR::new(((self.bits >> 28) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - Start crypto operation"] - #[inline(always)] - pub fn start(&mut self) -> StartW { - StartW::new(self, 0) - } - #[doc = "Bit 1 - Sets Cipher direction(AES and DES)"] - #[inline(always)] - pub fn decrypt(&mut self) -> DecryptW { - DecryptW::new(self, 1) - } - #[doc = "Bits 2:3 - Sets AES key size"] - #[inline(always)] - pub fn aeskeysz(&mut self) -> AeskeyszW { - AeskeyszW::new(self, 2) - } - #[doc = "Bits 4:6 - Sets 'Crypto Operation' type"] - #[inline(always)] - pub fn crypto_op(&mut self) -> CryptoOpW { - CryptoOpW::new(self, 4) - } - #[doc = "Bits 7:10 - 4'b0000 - DATIN\\[0\\]"] - #[inline(always)] - pub fn insel(&mut self) -> InselW { - InselW::new(self, 7) - } - #[doc = "Bits 11:13 - 3'b000 - DATOUT = 'Kernel Res'"] - #[inline(always)] - pub fn outsel(&mut self) -> OutselW { - OutselW::new(self, 11) - } - #[doc = "Bits 14:15 - Kernels data out options"] - #[inline(always)] - pub fn datout_res(&mut self) -> DatoutResW { - DatoutResW::new(self, 14) - } - #[doc = "Bit 16 - AES Kernel Enable"] - #[inline(always)] - pub fn aes_en(&mut self) -> AesEnW { - AesEnW::new(self, 16) - } - #[doc = "Bit 17 - DES Kernel Enable"] - #[inline(always)] - pub fn des_en(&mut self) -> DesEnW { - DesEnW::new(self, 17) - } - #[doc = "Bit 18 - GFMUL Kernel Enable"] - #[inline(always)] - pub fn gcm_en(&mut self) -> GcmEnW { - GcmEnW::new(self, 18) - } - #[doc = "Bit 19 - PRNG Enable(only if SGI has internal PRNG, Please"] - #[inline(always)] - pub fn prng_en(&mut self) -> PrngEnW { - PrngEnW::new(self, 19) - } - #[doc = "Bits 20:24 - Input key selection"] - #[inline(always)] - pub fn inkeysel(&mut self) -> InkeyselW { - InkeyselW::new(self, 20) - } - #[doc = "Bit 25 - Triple-DES Key Configuration"] - #[inline(always)] - pub fn tdeskey(&mut self) -> TdeskeyW { - TdeskeyW::new(self, 25) - } - #[doc = "Bit 26 - AES No decryption key schedule"] - #[inline(always)] - pub fn aes_no_kl(&mut self) -> AesNoKlW { - AesNoKlW::new(self, 26) - } - #[doc = "Bit 27 - AES Dual Selection"] - #[inline(always)] - pub fn aes_sel(&mut self) -> AesSelW { - AesSelW::new(self, 27) - } -} -#[doc = "SGI Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiCtrlSpec; -impl crate::RegisterSpec for SgiCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_ctrl::R`](R) reader structure"] -impl crate::Readable for SgiCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_ctrl::W`](W) writer structure"] -impl crate::Writable for SgiCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_ctrl to value 0"] -impl crate::Resettable for SgiCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_ctrl2.rs b/mcxa276-pac/src/sgi0/sgi_ctrl2.rs deleted file mode 100644 index 2a596063d..000000000 --- a/mcxa276-pac/src/sgi0/sgi_ctrl2.rs +++ /dev/null @@ -1,231 +0,0 @@ -#[doc = "Register `sgi_ctrl2` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_ctrl2` writer"] -pub type W = crate::W; -#[doc = "Field `flush` writer - Start Full SGI Flush"] -pub type FlushW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `key_flush` writer - Start KEY register-bank Flush"] -pub type KeyFlushW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `datin_flush` writer - Start DATIN register-bank Flush"] -pub type DatinFlushW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `incr` reader - Increment(Triggered by SFR write)"] -pub type IncrR = crate::BitReader; -#[doc = "Field `incr` writer - Increment(Triggered by SFR write)"] -pub type IncrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `xorwr` reader - Write-XOR control"] -pub type XorwrR = crate::BitReader; -#[doc = "Field `xorwr` writer - Write-XOR control"] -pub type XorwrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `flushwr` reader - Flush Write control"] -pub type FlushwrR = crate::BitReader; -#[doc = "Field `flushwr` writer - Flush Write control"] -pub type FlushwrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `incr_cin` reader - Increment Carry-In control"] -pub type IncrCinR = crate::BitReader; -#[doc = "Field `incr_cin` writer - Increment Carry-In control"] -pub type IncrCinW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ctrl2_rsvd3` reader - reserved"] -pub type Ctrl2Rsvd3R = crate::BitReader; -#[doc = "Field `smasken` reader - SFRMASK Enable"] -pub type SmaskenR = crate::BitReader; -#[doc = "Field `smasken` writer - SFRMASK Enable"] -pub type SmaskenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `smaskstep` reader - SFRSEED increment control"] -pub type SmaskstepR = crate::BitReader; -#[doc = "Field `smaskstep` writer - SFRSEED increment control"] -pub type SmaskstepW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `smasksw` reader - SFRMASK MASK control"] -pub type SmaskswR = crate::BitReader; -#[doc = "Field `smasksw` writer - SFRMASK MASK control"] -pub type SmaskswW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ctrl2_rsvd2` reader - reserved"] -pub type Ctrl2Rsvd2R = crate::BitReader; -#[doc = "Field `movem` reader - 4-bit optional input for MOVEM feature"] -pub type MovemR = crate::FieldReader; -#[doc = "Field `movem` writer - 4-bit optional input for MOVEM feature"] -pub type MovemW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `keyres` reader - Selects key registers to be updated when rkey=1"] -pub type KeyresR = crate::FieldReader; -#[doc = "Field `keyres` writer - Selects key registers to be updated when rkey=1"] -pub type KeyresW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `rkey` reader - Crypto result location"] -pub type RkeyR = crate::BitReader; -#[doc = "Field `rkey` writer - Crypto result location"] -pub type RkeyW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `bytes_order` reader - Byte order of regbank read/write data"] -pub type BytesOrderR = crate::BitReader; -#[doc = "Field `bytes_order` writer - Byte order of regbank read/write data"] -pub type BytesOrderW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `gcm_inxor` reader - GCM INXOR"] -pub type GcmInxorR = crate::BitReader; -#[doc = "Field `gcm_inxor` writer - GCM INXOR"] -pub type GcmInxorW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ctrl2_rsvd1` reader - reserved"] -pub type Ctrl2Rsvd1R = crate::FieldReader; -impl R { - #[doc = "Bit 3 - Increment(Triggered by SFR write)"] - #[inline(always)] - pub fn incr(&self) -> IncrR { - IncrR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Write-XOR control"] - #[inline(always)] - pub fn xorwr(&self) -> XorwrR { - XorwrR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Flush Write control"] - #[inline(always)] - pub fn flushwr(&self) -> FlushwrR { - FlushwrR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Increment Carry-In control"] - #[inline(always)] - pub fn incr_cin(&self) -> IncrCinR { - IncrCinR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - reserved"] - #[inline(always)] - pub fn ctrl2_rsvd3(&self) -> Ctrl2Rsvd3R { - Ctrl2Rsvd3R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - SFRMASK Enable"] - #[inline(always)] - pub fn smasken(&self) -> SmaskenR { - SmaskenR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SFRSEED increment control"] - #[inline(always)] - pub fn smaskstep(&self) -> SmaskstepR { - SmaskstepR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SFRMASK MASK control"] - #[inline(always)] - pub fn smasksw(&self) -> SmaskswR { - SmaskswR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - reserved"] - #[inline(always)] - pub fn ctrl2_rsvd2(&self) -> Ctrl2Rsvd2R { - Ctrl2Rsvd2R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15 - 4-bit optional input for MOVEM feature"] - #[inline(always)] - pub fn movem(&self) -> MovemR { - MovemR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:20 - Selects key registers to be updated when rkey=1"] - #[inline(always)] - pub fn keyres(&self) -> KeyresR { - KeyresR::new(((self.bits >> 16) & 0x1f) as u8) - } - #[doc = "Bit 21 - Crypto result location"] - #[inline(always)] - pub fn rkey(&self) -> RkeyR { - RkeyR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Byte order of regbank read/write data"] - #[inline(always)] - pub fn bytes_order(&self) -> BytesOrderR { - BytesOrderR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - GCM INXOR"] - #[inline(always)] - pub fn gcm_inxor(&self) -> GcmInxorR { - GcmInxorR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:31 - reserved"] - #[inline(always)] - pub fn ctrl2_rsvd1(&self) -> Ctrl2Rsvd1R { - Ctrl2Rsvd1R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bit 0 - Start Full SGI Flush"] - #[inline(always)] - pub fn flush(&mut self) -> FlushW { - FlushW::new(self, 0) - } - #[doc = "Bit 1 - Start KEY register-bank Flush"] - #[inline(always)] - pub fn key_flush(&mut self) -> KeyFlushW { - KeyFlushW::new(self, 1) - } - #[doc = "Bit 2 - Start DATIN register-bank Flush"] - #[inline(always)] - pub fn datin_flush(&mut self) -> DatinFlushW { - DatinFlushW::new(self, 2) - } - #[doc = "Bit 3 - Increment(Triggered by SFR write)"] - #[inline(always)] - pub fn incr(&mut self) -> IncrW { - IncrW::new(self, 3) - } - #[doc = "Bit 4 - Write-XOR control"] - #[inline(always)] - pub fn xorwr(&mut self) -> XorwrW { - XorwrW::new(self, 4) - } - #[doc = "Bit 5 - Flush Write control"] - #[inline(always)] - pub fn flushwr(&mut self) -> FlushwrW { - FlushwrW::new(self, 5) - } - #[doc = "Bit 6 - Increment Carry-In control"] - #[inline(always)] - pub fn incr_cin(&mut self) -> IncrCinW { - IncrCinW::new(self, 6) - } - #[doc = "Bit 8 - SFRMASK Enable"] - #[inline(always)] - pub fn smasken(&mut self) -> SmaskenW { - SmaskenW::new(self, 8) - } - #[doc = "Bit 9 - SFRSEED increment control"] - #[inline(always)] - pub fn smaskstep(&mut self) -> SmaskstepW { - SmaskstepW::new(self, 9) - } - #[doc = "Bit 10 - SFRMASK MASK control"] - #[inline(always)] - pub fn smasksw(&mut self) -> SmaskswW { - SmaskswW::new(self, 10) - } - #[doc = "Bits 12:15 - 4-bit optional input for MOVEM feature"] - #[inline(always)] - pub fn movem(&mut self) -> MovemW { - MovemW::new(self, 12) - } - #[doc = "Bits 16:20 - Selects key registers to be updated when rkey=1"] - #[inline(always)] - pub fn keyres(&mut self) -> KeyresW { - KeyresW::new(self, 16) - } - #[doc = "Bit 21 - Crypto result location"] - #[inline(always)] - pub fn rkey(&mut self) -> RkeyW { - RkeyW::new(self, 21) - } - #[doc = "Bit 22 - Byte order of regbank read/write data"] - #[inline(always)] - pub fn bytes_order(&mut self) -> BytesOrderW { - BytesOrderW::new(self, 22) - } - #[doc = "Bit 23 - GCM INXOR"] - #[inline(always)] - pub fn gcm_inxor(&mut self) -> GcmInxorW { - GcmInxorW::new(self, 23) - } -} -#[doc = "SGI Control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiCtrl2Spec; -impl crate::RegisterSpec for SgiCtrl2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_ctrl2::R`](R) reader structure"] -impl crate::Readable for SgiCtrl2Spec {} -#[doc = "`write(|w| ..)` method takes [`sgi_ctrl2::W`](W) writer structure"] -impl crate::Writable for SgiCtrl2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_ctrl2 to value 0"] -impl crate::Resettable for SgiCtrl2Spec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0a.rs b/mcxa276-pac/src/sgi0/sgi_datin0a.rs deleted file mode 100644 index 4db91b17b..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin0a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin0a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin0a` writer"] -pub type W = crate::W; -#[doc = "Field `datin0a` reader - Input Data register"] -pub type Datin0aR = crate::FieldReader; -#[doc = "Field `datin0a` writer - Input Data register"] -pub type Datin0aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0a(&self) -> Datin0aR { - Datin0aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0a(&mut self) -> Datin0aW { - Datin0aW::new(self, 0) - } -} -#[doc = "Input Data register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin0aSpec; -impl crate::RegisterSpec for SgiDatin0aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin0a::R`](R) reader structure"] -impl crate::Readable for SgiDatin0aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin0a::W`](W) writer structure"] -impl crate::Writable for SgiDatin0aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin0a to value 0"] -impl crate::Resettable for SgiDatin0aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0b.rs b/mcxa276-pac/src/sgi0/sgi_datin0b.rs deleted file mode 100644 index 47e6c55af..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin0b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin0b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin0b` writer"] -pub type W = crate::W; -#[doc = "Field `datin0b` reader - Input Data register"] -pub type Datin0bR = crate::FieldReader; -#[doc = "Field `datin0b` writer - Input Data register"] -pub type Datin0bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0b(&self) -> Datin0bR { - Datin0bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0b(&mut self) -> Datin0bW { - Datin0bW::new(self, 0) - } -} -#[doc = "Input Data register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin0bSpec; -impl crate::RegisterSpec for SgiDatin0bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin0b::R`](R) reader structure"] -impl crate::Readable for SgiDatin0bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin0b::W`](W) writer structure"] -impl crate::Writable for SgiDatin0bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin0b to value 0"] -impl crate::Resettable for SgiDatin0bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0c.rs b/mcxa276-pac/src/sgi0/sgi_datin0c.rs deleted file mode 100644 index d63ae5258..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin0c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin0c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin0c` writer"] -pub type W = crate::W; -#[doc = "Field `datin0c` reader - Input Data register"] -pub type Datin0cR = crate::FieldReader; -#[doc = "Field `datin0c` writer - Input Data register"] -pub type Datin0cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0c(&self) -> Datin0cR { - Datin0cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0c(&mut self) -> Datin0cW { - Datin0cW::new(self, 0) - } -} -#[doc = "Input Data register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin0cSpec; -impl crate::RegisterSpec for SgiDatin0cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin0c::R`](R) reader structure"] -impl crate::Readable for SgiDatin0cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin0c::W`](W) writer structure"] -impl crate::Writable for SgiDatin0cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin0c to value 0"] -impl crate::Resettable for SgiDatin0cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin0d.rs b/mcxa276-pac/src/sgi0/sgi_datin0d.rs deleted file mode 100644 index a348ebab6..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin0d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin0d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin0d` writer"] -pub type W = crate::W; -#[doc = "Field `datin0d` reader - Input Data register"] -pub type Datin0dR = crate::FieldReader; -#[doc = "Field `datin0d` writer - Input Data register"] -pub type Datin0dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0d(&self) -> Datin0dR { - Datin0dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin0d(&mut self) -> Datin0dW { - Datin0dW::new(self, 0) - } -} -#[doc = "Input Data register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin0d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin0d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin0dSpec; -impl crate::RegisterSpec for SgiDatin0dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin0d::R`](R) reader structure"] -impl crate::Readable for SgiDatin0dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin0d::W`](W) writer structure"] -impl crate::Writable for SgiDatin0dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin0d to value 0"] -impl crate::Resettable for SgiDatin0dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1a.rs b/mcxa276-pac/src/sgi0/sgi_datin1a.rs deleted file mode 100644 index 2fa0e17f4..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin1a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin1a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin1a` writer"] -pub type W = crate::W; -#[doc = "Field `datin1a` reader - Input Data register"] -pub type Datin1aR = crate::FieldReader; -#[doc = "Field `datin1a` writer - Input Data register"] -pub type Datin1aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1a(&self) -> Datin1aR { - Datin1aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1a(&mut self) -> Datin1aW { - Datin1aW::new(self, 0) - } -} -#[doc = "Input Data register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin1aSpec; -impl crate::RegisterSpec for SgiDatin1aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin1a::R`](R) reader structure"] -impl crate::Readable for SgiDatin1aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin1a::W`](W) writer structure"] -impl crate::Writable for SgiDatin1aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin1a to value 0"] -impl crate::Resettable for SgiDatin1aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1b.rs b/mcxa276-pac/src/sgi0/sgi_datin1b.rs deleted file mode 100644 index 1c05f86b4..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin1b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin1b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin1b` writer"] -pub type W = crate::W; -#[doc = "Field `datin1b` reader - Input Data register"] -pub type Datin1bR = crate::FieldReader; -#[doc = "Field `datin1b` writer - Input Data register"] -pub type Datin1bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1b(&self) -> Datin1bR { - Datin1bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1b(&mut self) -> Datin1bW { - Datin1bW::new(self, 0) - } -} -#[doc = "Input Data register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin1bSpec; -impl crate::RegisterSpec for SgiDatin1bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin1b::R`](R) reader structure"] -impl crate::Readable for SgiDatin1bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin1b::W`](W) writer structure"] -impl crate::Writable for SgiDatin1bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin1b to value 0"] -impl crate::Resettable for SgiDatin1bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1c.rs b/mcxa276-pac/src/sgi0/sgi_datin1c.rs deleted file mode 100644 index 8b82af66e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin1c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin1c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin1c` writer"] -pub type W = crate::W; -#[doc = "Field `datin1c` reader - Input Data register"] -pub type Datin1cR = crate::FieldReader; -#[doc = "Field `datin1c` writer - Input Data register"] -pub type Datin1cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1c(&self) -> Datin1cR { - Datin1cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1c(&mut self) -> Datin1cW { - Datin1cW::new(self, 0) - } -} -#[doc = "Input Data register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin1cSpec; -impl crate::RegisterSpec for SgiDatin1cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin1c::R`](R) reader structure"] -impl crate::Readable for SgiDatin1cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin1c::W`](W) writer structure"] -impl crate::Writable for SgiDatin1cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin1c to value 0"] -impl crate::Resettable for SgiDatin1cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin1d.rs b/mcxa276-pac/src/sgi0/sgi_datin1d.rs deleted file mode 100644 index 772a51785..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin1d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin1d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin1d` writer"] -pub type W = crate::W; -#[doc = "Field `datin1d` reader - Input Data register"] -pub type Datin1dR = crate::FieldReader; -#[doc = "Field `datin1d` writer - Input Data register"] -pub type Datin1dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1d(&self) -> Datin1dR { - Datin1dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin1d(&mut self) -> Datin1dW { - Datin1dW::new(self, 0) - } -} -#[doc = "Input Data register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin1d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin1d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin1dSpec; -impl crate::RegisterSpec for SgiDatin1dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin1d::R`](R) reader structure"] -impl crate::Readable for SgiDatin1dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin1d::W`](W) writer structure"] -impl crate::Writable for SgiDatin1dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin1d to value 0"] -impl crate::Resettable for SgiDatin1dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2a.rs b/mcxa276-pac/src/sgi0/sgi_datin2a.rs deleted file mode 100644 index 9f9751e2e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin2a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin2a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin2a` writer"] -pub type W = crate::W; -#[doc = "Field `datin2a` reader - Input Data register"] -pub type Datin2aR = crate::FieldReader; -#[doc = "Field `datin2a` writer - Input Data register"] -pub type Datin2aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2a(&self) -> Datin2aR { - Datin2aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2a(&mut self) -> Datin2aW { - Datin2aW::new(self, 0) - } -} -#[doc = "Input Data register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin2aSpec; -impl crate::RegisterSpec for SgiDatin2aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin2a::R`](R) reader structure"] -impl crate::Readable for SgiDatin2aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin2a::W`](W) writer structure"] -impl crate::Writable for SgiDatin2aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin2a to value 0"] -impl crate::Resettable for SgiDatin2aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2b.rs b/mcxa276-pac/src/sgi0/sgi_datin2b.rs deleted file mode 100644 index 060706280..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin2b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin2b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin2b` writer"] -pub type W = crate::W; -#[doc = "Field `datin2b` reader - Input Data register"] -pub type Datin2bR = crate::FieldReader; -#[doc = "Field `datin2b` writer - Input Data register"] -pub type Datin2bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2b(&self) -> Datin2bR { - Datin2bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2b(&mut self) -> Datin2bW { - Datin2bW::new(self, 0) - } -} -#[doc = "Input Data register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin2bSpec; -impl crate::RegisterSpec for SgiDatin2bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin2b::R`](R) reader structure"] -impl crate::Readable for SgiDatin2bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin2b::W`](W) writer structure"] -impl crate::Writable for SgiDatin2bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin2b to value 0"] -impl crate::Resettable for SgiDatin2bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2c.rs b/mcxa276-pac/src/sgi0/sgi_datin2c.rs deleted file mode 100644 index f76c5e7b5..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin2c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin2c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin2c` writer"] -pub type W = crate::W; -#[doc = "Field `datin2c` reader - Input Data register"] -pub type Datin2cR = crate::FieldReader; -#[doc = "Field `datin2c` writer - Input Data register"] -pub type Datin2cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2c(&self) -> Datin2cR { - Datin2cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2c(&mut self) -> Datin2cW { - Datin2cW::new(self, 0) - } -} -#[doc = "Input Data register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin2cSpec; -impl crate::RegisterSpec for SgiDatin2cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin2c::R`](R) reader structure"] -impl crate::Readable for SgiDatin2cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin2c::W`](W) writer structure"] -impl crate::Writable for SgiDatin2cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin2c to value 0"] -impl crate::Resettable for SgiDatin2cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin2d.rs b/mcxa276-pac/src/sgi0/sgi_datin2d.rs deleted file mode 100644 index 5fdd6ea5e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin2d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin2d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin2d` writer"] -pub type W = crate::W; -#[doc = "Field `datin2d` reader - Input Data register"] -pub type Datin2dR = crate::FieldReader; -#[doc = "Field `datin2d` writer - Input Data register"] -pub type Datin2dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2d(&self) -> Datin2dR { - Datin2dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin2d(&mut self) -> Datin2dW { - Datin2dW::new(self, 0) - } -} -#[doc = "Input Data register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin2d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin2d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin2dSpec; -impl crate::RegisterSpec for SgiDatin2dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin2d::R`](R) reader structure"] -impl crate::Readable for SgiDatin2dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin2d::W`](W) writer structure"] -impl crate::Writable for SgiDatin2dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin2d to value 0"] -impl crate::Resettable for SgiDatin2dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3a.rs b/mcxa276-pac/src/sgi0/sgi_datin3a.rs deleted file mode 100644 index 9e860357d..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin3a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin3a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin3a` writer"] -pub type W = crate::W; -#[doc = "Field `datin3a` reader - Input Data register"] -pub type Datin3aR = crate::FieldReader; -#[doc = "Field `datin3a` writer - Input Data register"] -pub type Datin3aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3a(&self) -> Datin3aR { - Datin3aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3a(&mut self) -> Datin3aW { - Datin3aW::new(self, 0) - } -} -#[doc = "Input Data register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin3aSpec; -impl crate::RegisterSpec for SgiDatin3aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin3a::R`](R) reader structure"] -impl crate::Readable for SgiDatin3aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin3a::W`](W) writer structure"] -impl crate::Writable for SgiDatin3aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin3a to value 0"] -impl crate::Resettable for SgiDatin3aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3b.rs b/mcxa276-pac/src/sgi0/sgi_datin3b.rs deleted file mode 100644 index 4e0c08fc3..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin3b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin3b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin3b` writer"] -pub type W = crate::W; -#[doc = "Field `datin3b` reader - Input Data register"] -pub type Datin3bR = crate::FieldReader; -#[doc = "Field `datin3b` writer - Input Data register"] -pub type Datin3bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3b(&self) -> Datin3bR { - Datin3bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3b(&mut self) -> Datin3bW { - Datin3bW::new(self, 0) - } -} -#[doc = "Input Data register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin3bSpec; -impl crate::RegisterSpec for SgiDatin3bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin3b::R`](R) reader structure"] -impl crate::Readable for SgiDatin3bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin3b::W`](W) writer structure"] -impl crate::Writable for SgiDatin3bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin3b to value 0"] -impl crate::Resettable for SgiDatin3bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3c.rs b/mcxa276-pac/src/sgi0/sgi_datin3c.rs deleted file mode 100644 index 1f58a4439..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin3c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin3c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin3c` writer"] -pub type W = crate::W; -#[doc = "Field `datin3c` reader - Input Data register"] -pub type Datin3cR = crate::FieldReader; -#[doc = "Field `datin3c` writer - Input Data register"] -pub type Datin3cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3c(&self) -> Datin3cR { - Datin3cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3c(&mut self) -> Datin3cW { - Datin3cW::new(self, 0) - } -} -#[doc = "Input Data register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin3cSpec; -impl crate::RegisterSpec for SgiDatin3cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin3c::R`](R) reader structure"] -impl crate::Readable for SgiDatin3cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin3c::W`](W) writer structure"] -impl crate::Writable for SgiDatin3cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin3c to value 0"] -impl crate::Resettable for SgiDatin3cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datin3d.rs b/mcxa276-pac/src/sgi0/sgi_datin3d.rs deleted file mode 100644 index c32d30b38..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datin3d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datin3d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datin3d` writer"] -pub type W = crate::W; -#[doc = "Field `datin3d` reader - Input Data register"] -pub type Datin3dR = crate::FieldReader; -#[doc = "Field `datin3d` writer - Input Data register"] -pub type Datin3dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3d(&self) -> Datin3dR { - Datin3dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Data register"] - #[inline(always)] - pub fn datin3d(&mut self) -> Datin3dW { - Datin3dW::new(self, 0) - } -} -#[doc = "Input Data register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datin3d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datin3d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatin3dSpec; -impl crate::RegisterSpec for SgiDatin3dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datin3d::R`](R) reader structure"] -impl crate::Readable for SgiDatin3dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datin3d::W`](W) writer structure"] -impl crate::Writable for SgiDatin3dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datin3d to value 0"] -impl crate::Resettable for SgiDatin3dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datouta.rs b/mcxa276-pac/src/sgi0/sgi_datouta.rs deleted file mode 100644 index 175bb01d6..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datouta.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datouta` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datouta` writer"] -pub type W = crate::W; -#[doc = "Field `datouta` reader - Output Data register"] -pub type DatoutaR = crate::FieldReader; -#[doc = "Field `datouta` writer - Output Data register"] -pub type DatoutaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datouta(&self) -> DatoutaR { - DatoutaR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datouta(&mut self) -> DatoutaW { - DatoutaW::new(self, 0) - } -} -#[doc = "Output Data register - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datouta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datouta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatoutaSpec; -impl crate::RegisterSpec for SgiDatoutaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datouta::R`](R) reader structure"] -impl crate::Readable for SgiDatoutaSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datouta::W`](W) writer structure"] -impl crate::Writable for SgiDatoutaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datouta to value 0"] -impl crate::Resettable for SgiDatoutaSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datoutb.rs b/mcxa276-pac/src/sgi0/sgi_datoutb.rs deleted file mode 100644 index 785fe870c..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datoutb.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datoutb` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datoutb` writer"] -pub type W = crate::W; -#[doc = "Field `datoutb` reader - Output Data register"] -pub type DatoutbR = crate::FieldReader; -#[doc = "Field `datoutb` writer - Output Data register"] -pub type DatoutbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datoutb(&self) -> DatoutbR { - DatoutbR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datoutb(&mut self) -> DatoutbW { - DatoutbW::new(self, 0) - } -} -#[doc = "Output Data register - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatoutbSpec; -impl crate::RegisterSpec for SgiDatoutbSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datoutb::R`](R) reader structure"] -impl crate::Readable for SgiDatoutbSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datoutb::W`](W) writer structure"] -impl crate::Writable for SgiDatoutbSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datoutb to value 0"] -impl crate::Resettable for SgiDatoutbSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datoutc.rs b/mcxa276-pac/src/sgi0/sgi_datoutc.rs deleted file mode 100644 index a38081e6a..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datoutc.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datoutc` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datoutc` writer"] -pub type W = crate::W; -#[doc = "Field `datoutc` reader - Output Data register"] -pub type DatoutcR = crate::FieldReader; -#[doc = "Field `datoutc` writer - Output Data register"] -pub type DatoutcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datoutc(&self) -> DatoutcR { - DatoutcR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datoutc(&mut self) -> DatoutcW { - DatoutcW::new(self, 0) - } -} -#[doc = "Output Data register - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatoutcSpec; -impl crate::RegisterSpec for SgiDatoutcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datoutc::R`](R) reader structure"] -impl crate::Readable for SgiDatoutcSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datoutc::W`](W) writer structure"] -impl crate::Writable for SgiDatoutcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datoutc to value 0"] -impl crate::Resettable for SgiDatoutcSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_datoutd.rs b/mcxa276-pac/src/sgi0/sgi_datoutd.rs deleted file mode 100644 index 939d50cc1..000000000 --- a/mcxa276-pac/src/sgi0/sgi_datoutd.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_datoutd` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_datoutd` writer"] -pub type W = crate::W; -#[doc = "Field `datoutd` reader - Output Data register"] -pub type DatoutdR = crate::FieldReader; -#[doc = "Field `datoutd` writer - Output Data register"] -pub type DatoutdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datoutd(&self) -> DatoutdR { - DatoutdR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Output Data register"] - #[inline(always)] - pub fn datoutd(&mut self) -> DatoutdW { - DatoutdW::new(self, 0) - } -} -#[doc = "Output Data register - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_datoutd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_datoutd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDatoutdSpec; -impl crate::RegisterSpec for SgiDatoutdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_datoutd::R`](R) reader structure"] -impl crate::Readable for SgiDatoutdSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_datoutd::W`](W) writer structure"] -impl crate::Writable for SgiDatoutdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_datoutd to value 0"] -impl crate::Resettable for SgiDatoutdSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_dummy_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_dummy_ctrl.rs deleted file mode 100644 index 679b59047..000000000 --- a/mcxa276-pac/src/sgi0/sgi_dummy_ctrl.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `sgi_dummy_ctrl` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_dummy_ctrl` writer"] -pub type W = crate::W; -#[doc = "Field `ddctrl` reader - DES dummy control"] -pub type DdctrlR = crate::FieldReader; -#[doc = "Field `ddctrl` writer - DES dummy control"] -pub type DdctrlW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `dmyctl_rsvd2` reader - reserved"] -pub type DmyctlRsvd2R = crate::FieldReader; -#[doc = "Field `adctrl` reader - AES dummy control"] -pub type AdctrlR = crate::FieldReader; -#[doc = "Field `adctrl` writer - AES dummy control"] -pub type AdctrlW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `dmyctl_rsvd1` reader - reserved"] -pub type DmyctlRsvd1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - DES dummy control"] - #[inline(always)] - pub fn ddctrl(&self) -> DdctrlR { - DdctrlR::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bits 10:15 - reserved"] - #[inline(always)] - pub fn dmyctl_rsvd2(&self) -> DmyctlRsvd2R { - DmyctlRsvd2R::new(((self.bits >> 10) & 0x3f) as u8) - } - #[doc = "Bits 16:25 - AES dummy control"] - #[inline(always)] - pub fn adctrl(&self) -> AdctrlR { - AdctrlR::new(((self.bits >> 16) & 0x03ff) as u16) - } - #[doc = "Bits 26:31 - reserved"] - #[inline(always)] - pub fn dmyctl_rsvd1(&self) -> DmyctlRsvd1R { - DmyctlRsvd1R::new(((self.bits >> 26) & 0x3f) as u8) - } -} -impl W { - #[doc = "Bits 0:9 - DES dummy control"] - #[inline(always)] - pub fn ddctrl(&mut self) -> DdctrlW { - DdctrlW::new(self, 0) - } - #[doc = "Bits 16:25 - AES dummy control"] - #[inline(always)] - pub fn adctrl(&mut self) -> AdctrlW { - AdctrlW::new(self, 16) - } -} -#[doc = "Configuration of dummy controls\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_dummy_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_dummy_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiDummyCtrlSpec; -impl crate::RegisterSpec for SgiDummyCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_dummy_ctrl::R`](R) reader structure"] -impl crate::Readable for SgiDummyCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_dummy_ctrl::W`](W) writer structure"] -impl crate::Writable for SgiDummyCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_dummy_ctrl to value 0"] -impl crate::Resettable for SgiDummyCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_enable.rs b/mcxa276-pac/src/sgi0/sgi_int_enable.rs deleted file mode 100644 index 97089a820..000000000 --- a/mcxa276-pac/src/sgi0/sgi_int_enable.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `sgi_int_enable` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_int_enable` writer"] -pub type W = crate::W; -#[doc = "Field `int_en` reader - Interrupt enable bit"] -pub type IntEnR = crate::BitReader; -#[doc = "Field `int_en` writer - Interrupt enable bit"] -pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `int_ena_rsvd` reader - reserved"] -pub type IntEnaRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Interrupt enable bit"] - #[inline(always)] - pub fn int_en(&self) -> IntEnR { - IntEnR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:31 - reserved"] - #[inline(always)] - pub fn int_ena_rsvd(&self) -> IntEnaRsvdR { - IntEnaRsvdR::new((self.bits >> 1) & 0x7fff_ffff) - } -} -impl W { - #[doc = "Bit 0 - Interrupt enable bit"] - #[inline(always)] - pub fn int_en(&mut self) -> IntEnW { - IntEnW::new(self, 0) - } -} -#[doc = "Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiIntEnableSpec; -impl crate::RegisterSpec for SgiIntEnableSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_int_enable::R`](R) reader structure"] -impl crate::Readable for SgiIntEnableSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_int_enable::W`](W) writer structure"] -impl crate::Writable for SgiIntEnableSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_int_enable to value 0"] -impl crate::Resettable for SgiIntEnableSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_status.rs b/mcxa276-pac/src/sgi0/sgi_int_status.rs deleted file mode 100644 index e2bc13560..000000000 --- a/mcxa276-pac/src/sgi0/sgi_int_status.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `sgi_int_status` reader"] -pub type R = crate::R; -#[doc = "Field `int_pdone` reader - Interrupt status flag:"] -pub type IntPdoneR = crate::BitReader; -#[doc = "Field `intst_rsvd` reader - reserved"] -pub type IntstRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Interrupt status flag:"] - #[inline(always)] - pub fn int_pdone(&self) -> IntPdoneR { - IntPdoneR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:31 - reserved"] - #[inline(always)] - pub fn intst_rsvd(&self) -> IntstRsvdR { - IntstRsvdR::new((self.bits >> 1) & 0x7fff_ffff) - } -} -#[doc = "Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiIntStatusSpec; -impl crate::RegisterSpec for SgiIntStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_int_status::R`](R) reader structure"] -impl crate::Readable for SgiIntStatusSpec {} -#[doc = "`reset()` method sets sgi_int_status to value 0"] -impl crate::Resettable for SgiIntStatusSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_status_clr.rs b/mcxa276-pac/src/sgi0/sgi_int_status_clr.rs deleted file mode 100644 index d1aa4dc64..000000000 --- a/mcxa276-pac/src/sgi0/sgi_int_status_clr.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `sgi_int_status_clr` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_int_status_clr` writer"] -pub type W = crate::W; -#[doc = "Field `int_clr` reader - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] -pub type IntClrR = crate::BitReader; -#[doc = "Field `int_clr` writer - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] -pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `int_stsc_rsvd` reader - reserved"] -pub type IntStscRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] - #[inline(always)] - pub fn int_clr(&self) -> IntClrR { - IntClrR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:31 - reserved"] - #[inline(always)] - pub fn int_stsc_rsvd(&self) -> IntStscRsvdR { - IntStscRsvdR::new((self.bits >> 1) & 0x7fff_ffff) - } -} -impl W { - #[doc = "Bit 0 - Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0)."] - #[inline(always)] - pub fn int_clr(&mut self) -> IntClrW { - IntClrW::new(self, 0) - } -} -#[doc = "Interrupt status clear\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiIntStatusClrSpec; -impl crate::RegisterSpec for SgiIntStatusClrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_int_status_clr::R`](R) reader structure"] -impl crate::Readable for SgiIntStatusClrSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_int_status_clr::W`](W) writer structure"] -impl crate::Writable for SgiIntStatusClrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_int_status_clr to value 0"] -impl crate::Resettable for SgiIntStatusClrSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_int_status_set.rs b/mcxa276-pac/src/sgi0/sgi_int_status_set.rs deleted file mode 100644 index 544c8f756..000000000 --- a/mcxa276-pac/src/sgi0/sgi_int_status_set.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `sgi_int_status_set` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_int_status_set` writer"] -pub type W = crate::W; -#[doc = "Field `int_set` reader - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] -pub type IntSetR = crate::BitReader; -#[doc = "Field `int_set` writer - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] -pub type IntSetW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `int_stss_rsvd` reader - reserved"] -pub type IntStssRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] - #[inline(always)] - pub fn int_set(&self) -> IntSetR { - IntSetR::new((self.bits & 1) != 0) - } - #[doc = "Bits 1:31 - reserved"] - #[inline(always)] - pub fn int_stss_rsvd(&self) -> IntStssRsvdR { - IntStssRsvdR::new((self.bits >> 1) & 0x7fff_ffff) - } -} -impl W { - #[doc = "Bit 0 - Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes."] - #[inline(always)] - pub fn int_set(&mut self) -> IntSetW { - IntSetW::new(self, 0) - } -} -#[doc = "Interrupt status set\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_int_status_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_int_status_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiIntStatusSetSpec; -impl crate::RegisterSpec for SgiIntStatusSetSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_int_status_set::R`](R) reader structure"] -impl crate::Readable for SgiIntStatusSetSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_int_status_set::W`](W) writer structure"] -impl crate::Writable for SgiIntStatusSetSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_int_status_set to value 0"] -impl crate::Resettable for SgiIntStatusSetSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0a.rs b/mcxa276-pac/src/sgi0/sgi_key0a.rs deleted file mode 100644 index da82a59b2..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key0a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key0a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key0a` writer"] -pub type W = crate::W; -#[doc = "Field `key0a` reader - Input Key register"] -pub type Key0aR = crate::FieldReader; -#[doc = "Field `key0a` writer - Input Key register"] -pub type Key0aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0a(&self) -> Key0aR { - Key0aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0a(&mut self) -> Key0aW { - Key0aW::new(self, 0) - } -} -#[doc = "Input Key register 0 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey0aSpec; -impl crate::RegisterSpec for SgiKey0aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key0a::R`](R) reader structure"] -impl crate::Readable for SgiKey0aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key0a::W`](W) writer structure"] -impl crate::Writable for SgiKey0aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key0a to value 0"] -impl crate::Resettable for SgiKey0aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0b.rs b/mcxa276-pac/src/sgi0/sgi_key0b.rs deleted file mode 100644 index df7437d73..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key0b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key0b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key0b` writer"] -pub type W = crate::W; -#[doc = "Field `key0b` reader - Input Key register"] -pub type Key0bR = crate::FieldReader; -#[doc = "Field `key0b` writer - Input Key register"] -pub type Key0bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0b(&self) -> Key0bR { - Key0bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0b(&mut self) -> Key0bW { - Key0bW::new(self, 0) - } -} -#[doc = "Input Key register 0 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey0bSpec; -impl crate::RegisterSpec for SgiKey0bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key0b::R`](R) reader structure"] -impl crate::Readable for SgiKey0bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key0b::W`](W) writer structure"] -impl crate::Writable for SgiKey0bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key0b to value 0"] -impl crate::Resettable for SgiKey0bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0c.rs b/mcxa276-pac/src/sgi0/sgi_key0c.rs deleted file mode 100644 index 3a72b89e6..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key0c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key0c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key0c` writer"] -pub type W = crate::W; -#[doc = "Field `key0c` reader - Input Key register"] -pub type Key0cR = crate::FieldReader; -#[doc = "Field `key0c` writer - Input Key register"] -pub type Key0cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0c(&self) -> Key0cR { - Key0cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0c(&mut self) -> Key0cW { - Key0cW::new(self, 0) - } -} -#[doc = "Input Key register 0 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey0cSpec; -impl crate::RegisterSpec for SgiKey0cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key0c::R`](R) reader structure"] -impl crate::Readable for SgiKey0cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key0c::W`](W) writer structure"] -impl crate::Writable for SgiKey0cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key0c to value 0"] -impl crate::Resettable for SgiKey0cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key0d.rs b/mcxa276-pac/src/sgi0/sgi_key0d.rs deleted file mode 100644 index 50b1ccbc2..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key0d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key0d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key0d` writer"] -pub type W = crate::W; -#[doc = "Field `key0d` reader - Input Key register"] -pub type Key0dR = crate::FieldReader; -#[doc = "Field `key0d` writer - Input Key register"] -pub type Key0dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0d(&self) -> Key0dR { - Key0dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key0d(&mut self) -> Key0dW { - Key0dW::new(self, 0) - } -} -#[doc = "Input Key register 0 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key0d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key0d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey0dSpec; -impl crate::RegisterSpec for SgiKey0dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key0d::R`](R) reader structure"] -impl crate::Readable for SgiKey0dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key0d::W`](W) writer structure"] -impl crate::Writable for SgiKey0dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key0d to value 0"] -impl crate::Resettable for SgiKey0dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1a.rs b/mcxa276-pac/src/sgi0/sgi_key1a.rs deleted file mode 100644 index 014975360..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key1a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key1a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key1a` writer"] -pub type W = crate::W; -#[doc = "Field `key1a` reader - Input Key register"] -pub type Key1aR = crate::FieldReader; -#[doc = "Field `key1a` writer - Input Key register"] -pub type Key1aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1a(&self) -> Key1aR { - Key1aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1a(&mut self) -> Key1aW { - Key1aW::new(self, 0) - } -} -#[doc = "Input Key register 1 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey1aSpec; -impl crate::RegisterSpec for SgiKey1aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key1a::R`](R) reader structure"] -impl crate::Readable for SgiKey1aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key1a::W`](W) writer structure"] -impl crate::Writable for SgiKey1aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key1a to value 0"] -impl crate::Resettable for SgiKey1aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1b.rs b/mcxa276-pac/src/sgi0/sgi_key1b.rs deleted file mode 100644 index 58e93abde..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key1b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key1b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key1b` writer"] -pub type W = crate::W; -#[doc = "Field `key1b` reader - Input Key register"] -pub type Key1bR = crate::FieldReader; -#[doc = "Field `key1b` writer - Input Key register"] -pub type Key1bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1b(&self) -> Key1bR { - Key1bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1b(&mut self) -> Key1bW { - Key1bW::new(self, 0) - } -} -#[doc = "Input Key register 1 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey1bSpec; -impl crate::RegisterSpec for SgiKey1bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key1b::R`](R) reader structure"] -impl crate::Readable for SgiKey1bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key1b::W`](W) writer structure"] -impl crate::Writable for SgiKey1bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key1b to value 0"] -impl crate::Resettable for SgiKey1bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1c.rs b/mcxa276-pac/src/sgi0/sgi_key1c.rs deleted file mode 100644 index b46ea2e2e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key1c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key1c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key1c` writer"] -pub type W = crate::W; -#[doc = "Field `key1c` reader - Input Key register"] -pub type Key1cR = crate::FieldReader; -#[doc = "Field `key1c` writer - Input Key register"] -pub type Key1cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1c(&self) -> Key1cR { - Key1cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1c(&mut self) -> Key1cW { - Key1cW::new(self, 0) - } -} -#[doc = "Input Key register 1 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey1cSpec; -impl crate::RegisterSpec for SgiKey1cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key1c::R`](R) reader structure"] -impl crate::Readable for SgiKey1cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key1c::W`](W) writer structure"] -impl crate::Writable for SgiKey1cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key1c to value 0"] -impl crate::Resettable for SgiKey1cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key1d.rs b/mcxa276-pac/src/sgi0/sgi_key1d.rs deleted file mode 100644 index 5a4c638fd..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key1d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key1d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key1d` writer"] -pub type W = crate::W; -#[doc = "Field `key1d` reader - Input Key register"] -pub type Key1dR = crate::FieldReader; -#[doc = "Field `key1d` writer - Input Key register"] -pub type Key1dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1d(&self) -> Key1dR { - Key1dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key1d(&mut self) -> Key1dW { - Key1dW::new(self, 0) - } -} -#[doc = "Input Key register 1 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key1d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key1d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey1dSpec; -impl crate::RegisterSpec for SgiKey1dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key1d::R`](R) reader structure"] -impl crate::Readable for SgiKey1dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key1d::W`](W) writer structure"] -impl crate::Writable for SgiKey1dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key1d to value 0"] -impl crate::Resettable for SgiKey1dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2a.rs b/mcxa276-pac/src/sgi0/sgi_key2a.rs deleted file mode 100644 index ac8921f13..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key2a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key2a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key2a` writer"] -pub type W = crate::W; -#[doc = "Field `key2a` reader - Input Key register"] -pub type Key2aR = crate::FieldReader; -#[doc = "Field `key2a` writer - Input Key register"] -pub type Key2aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2a(&self) -> Key2aR { - Key2aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2a(&mut self) -> Key2aW { - Key2aW::new(self, 0) - } -} -#[doc = "Input Key register 2 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey2aSpec; -impl crate::RegisterSpec for SgiKey2aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key2a::R`](R) reader structure"] -impl crate::Readable for SgiKey2aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key2a::W`](W) writer structure"] -impl crate::Writable for SgiKey2aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key2a to value 0"] -impl crate::Resettable for SgiKey2aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2b.rs b/mcxa276-pac/src/sgi0/sgi_key2b.rs deleted file mode 100644 index ee35622ad..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key2b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key2b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key2b` writer"] -pub type W = crate::W; -#[doc = "Field `key2b` reader - Input Key register"] -pub type Key2bR = crate::FieldReader; -#[doc = "Field `key2b` writer - Input Key register"] -pub type Key2bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2b(&self) -> Key2bR { - Key2bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2b(&mut self) -> Key2bW { - Key2bW::new(self, 0) - } -} -#[doc = "Input Key register 2 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey2bSpec; -impl crate::RegisterSpec for SgiKey2bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key2b::R`](R) reader structure"] -impl crate::Readable for SgiKey2bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key2b::W`](W) writer structure"] -impl crate::Writable for SgiKey2bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key2b to value 0"] -impl crate::Resettable for SgiKey2bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2c.rs b/mcxa276-pac/src/sgi0/sgi_key2c.rs deleted file mode 100644 index f7cfe25c5..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key2c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key2c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key2c` writer"] -pub type W = crate::W; -#[doc = "Field `key2c` reader - Input Key register"] -pub type Key2cR = crate::FieldReader; -#[doc = "Field `key2c` writer - Input Key register"] -pub type Key2cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2c(&self) -> Key2cR { - Key2cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2c(&mut self) -> Key2cW { - Key2cW::new(self, 0) - } -} -#[doc = "Input Key register 2 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey2cSpec; -impl crate::RegisterSpec for SgiKey2cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key2c::R`](R) reader structure"] -impl crate::Readable for SgiKey2cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key2c::W`](W) writer structure"] -impl crate::Writable for SgiKey2cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key2c to value 0"] -impl crate::Resettable for SgiKey2cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key2d.rs b/mcxa276-pac/src/sgi0/sgi_key2d.rs deleted file mode 100644 index ec9603f3e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key2d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key2d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key2d` writer"] -pub type W = crate::W; -#[doc = "Field `key2d` reader - Input Key register"] -pub type Key2dR = crate::FieldReader; -#[doc = "Field `key2d` writer - Input Key register"] -pub type Key2dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2d(&self) -> Key2dR { - Key2dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key2d(&mut self) -> Key2dW { - Key2dW::new(self, 0) - } -} -#[doc = "Input Key register 2 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key2d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key2d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey2dSpec; -impl crate::RegisterSpec for SgiKey2dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key2d::R`](R) reader structure"] -impl crate::Readable for SgiKey2dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key2d::W`](W) writer structure"] -impl crate::Writable for SgiKey2dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key2d to value 0"] -impl crate::Resettable for SgiKey2dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3a.rs b/mcxa276-pac/src/sgi0/sgi_key3a.rs deleted file mode 100644 index a6998fbd9..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key3a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key3a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key3a` writer"] -pub type W = crate::W; -#[doc = "Field `key3a` reader - Input Key register"] -pub type Key3aR = crate::FieldReader; -#[doc = "Field `key3a` writer - Input Key register"] -pub type Key3aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3a(&self) -> Key3aR { - Key3aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3a(&mut self) -> Key3aW { - Key3aW::new(self, 0) - } -} -#[doc = "Input Key register 3 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey3aSpec; -impl crate::RegisterSpec for SgiKey3aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key3a::R`](R) reader structure"] -impl crate::Readable for SgiKey3aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key3a::W`](W) writer structure"] -impl crate::Writable for SgiKey3aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key3a to value 0"] -impl crate::Resettable for SgiKey3aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3b.rs b/mcxa276-pac/src/sgi0/sgi_key3b.rs deleted file mode 100644 index 335799dfd..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key3b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key3b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key3b` writer"] -pub type W = crate::W; -#[doc = "Field `key3b` reader - Input Key register"] -pub type Key3bR = crate::FieldReader; -#[doc = "Field `key3b` writer - Input Key register"] -pub type Key3bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3b(&self) -> Key3bR { - Key3bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3b(&mut self) -> Key3bW { - Key3bW::new(self, 0) - } -} -#[doc = "Input Key register 3 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey3bSpec; -impl crate::RegisterSpec for SgiKey3bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key3b::R`](R) reader structure"] -impl crate::Readable for SgiKey3bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key3b::W`](W) writer structure"] -impl crate::Writable for SgiKey3bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key3b to value 0"] -impl crate::Resettable for SgiKey3bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3c.rs b/mcxa276-pac/src/sgi0/sgi_key3c.rs deleted file mode 100644 index d2e8f9b4a..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key3c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key3c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key3c` writer"] -pub type W = crate::W; -#[doc = "Field `key3c` reader - Input Key register"] -pub type Key3cR = crate::FieldReader; -#[doc = "Field `key3c` writer - Input Key register"] -pub type Key3cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3c(&self) -> Key3cR { - Key3cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3c(&mut self) -> Key3cW { - Key3cW::new(self, 0) - } -} -#[doc = "Input Key register 3 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey3cSpec; -impl crate::RegisterSpec for SgiKey3cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key3c::R`](R) reader structure"] -impl crate::Readable for SgiKey3cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key3c::W`](W) writer structure"] -impl crate::Writable for SgiKey3cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key3c to value 0"] -impl crate::Resettable for SgiKey3cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key3d.rs b/mcxa276-pac/src/sgi0/sgi_key3d.rs deleted file mode 100644 index 2753bb18a..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key3d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key3d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key3d` writer"] -pub type W = crate::W; -#[doc = "Field `key3d` reader - Input Key register"] -pub type Key3dR = crate::FieldReader; -#[doc = "Field `key3d` writer - Input Key register"] -pub type Key3dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3d(&self) -> Key3dR { - Key3dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key3d(&mut self) -> Key3dW { - Key3dW::new(self, 0) - } -} -#[doc = "Input Key register 3 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key3d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key3d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey3dSpec; -impl crate::RegisterSpec for SgiKey3dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key3d::R`](R) reader structure"] -impl crate::Readable for SgiKey3dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key3d::W`](W) writer structure"] -impl crate::Writable for SgiKey3dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key3d to value 0"] -impl crate::Resettable for SgiKey3dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4a.rs b/mcxa276-pac/src/sgi0/sgi_key4a.rs deleted file mode 100644 index 071fc45ec..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key4a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key4a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key4a` writer"] -pub type W = crate::W; -#[doc = "Field `key4a` reader - Input Key register"] -pub type Key4aR = crate::FieldReader; -#[doc = "Field `key4a` writer - Input Key register"] -pub type Key4aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4a(&self) -> Key4aR { - Key4aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4a(&mut self) -> Key4aW { - Key4aW::new(self, 0) - } -} -#[doc = "Input Key register 4 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey4aSpec; -impl crate::RegisterSpec for SgiKey4aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key4a::R`](R) reader structure"] -impl crate::Readable for SgiKey4aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key4a::W`](W) writer structure"] -impl crate::Writable for SgiKey4aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key4a to value 0"] -impl crate::Resettable for SgiKey4aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4b.rs b/mcxa276-pac/src/sgi0/sgi_key4b.rs deleted file mode 100644 index 39b9419a7..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key4b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key4b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key4b` writer"] -pub type W = crate::W; -#[doc = "Field `key4b` reader - Input Key register"] -pub type Key4bR = crate::FieldReader; -#[doc = "Field `key4b` writer - Input Key register"] -pub type Key4bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4b(&self) -> Key4bR { - Key4bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4b(&mut self) -> Key4bW { - Key4bW::new(self, 0) - } -} -#[doc = "Input Key register 4 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey4bSpec; -impl crate::RegisterSpec for SgiKey4bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key4b::R`](R) reader structure"] -impl crate::Readable for SgiKey4bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key4b::W`](W) writer structure"] -impl crate::Writable for SgiKey4bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key4b to value 0"] -impl crate::Resettable for SgiKey4bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4c.rs b/mcxa276-pac/src/sgi0/sgi_key4c.rs deleted file mode 100644 index b9c32f600..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key4c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key4c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key4c` writer"] -pub type W = crate::W; -#[doc = "Field `key4c` reader - Input Key register"] -pub type Key4cR = crate::FieldReader; -#[doc = "Field `key4c` writer - Input Key register"] -pub type Key4cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4c(&self) -> Key4cR { - Key4cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4c(&mut self) -> Key4cW { - Key4cW::new(self, 0) - } -} -#[doc = "Input Key register 4 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey4cSpec; -impl crate::RegisterSpec for SgiKey4cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key4c::R`](R) reader structure"] -impl crate::Readable for SgiKey4cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key4c::W`](W) writer structure"] -impl crate::Writable for SgiKey4cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key4c to value 0"] -impl crate::Resettable for SgiKey4cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key4d.rs b/mcxa276-pac/src/sgi0/sgi_key4d.rs deleted file mode 100644 index dd0c5debc..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key4d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key4d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key4d` writer"] -pub type W = crate::W; -#[doc = "Field `key4d` reader - Input Key register"] -pub type Key4dR = crate::FieldReader; -#[doc = "Field `key4d` writer - Input Key register"] -pub type Key4dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4d(&self) -> Key4dR { - Key4dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key4d(&mut self) -> Key4dW { - Key4dW::new(self, 0) - } -} -#[doc = "Input Key register 4 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key4d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key4d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey4dSpec; -impl crate::RegisterSpec for SgiKey4dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key4d::R`](R) reader structure"] -impl crate::Readable for SgiKey4dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key4d::W`](W) writer structure"] -impl crate::Writable for SgiKey4dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key4d to value 0"] -impl crate::Resettable for SgiKey4dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5a.rs b/mcxa276-pac/src/sgi0/sgi_key5a.rs deleted file mode 100644 index 103f7f5f4..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key5a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key5a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key5a` writer"] -pub type W = crate::W; -#[doc = "Field `key5a` reader - Input Key register"] -pub type Key5aR = crate::FieldReader; -#[doc = "Field `key5a` writer - Input Key register"] -pub type Key5aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5a(&self) -> Key5aR { - Key5aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5a(&mut self) -> Key5aW { - Key5aW::new(self, 0) - } -} -#[doc = "Input Key register 5 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey5aSpec; -impl crate::RegisterSpec for SgiKey5aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key5a::R`](R) reader structure"] -impl crate::Readable for SgiKey5aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key5a::W`](W) writer structure"] -impl crate::Writable for SgiKey5aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key5a to value 0"] -impl crate::Resettable for SgiKey5aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5b.rs b/mcxa276-pac/src/sgi0/sgi_key5b.rs deleted file mode 100644 index 8575c3a76..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key5b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key5b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key5b` writer"] -pub type W = crate::W; -#[doc = "Field `key5b` reader - Input Key register"] -pub type Key5bR = crate::FieldReader; -#[doc = "Field `key5b` writer - Input Key register"] -pub type Key5bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5b(&self) -> Key5bR { - Key5bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5b(&mut self) -> Key5bW { - Key5bW::new(self, 0) - } -} -#[doc = "Input Key register 5 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey5bSpec; -impl crate::RegisterSpec for SgiKey5bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key5b::R`](R) reader structure"] -impl crate::Readable for SgiKey5bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key5b::W`](W) writer structure"] -impl crate::Writable for SgiKey5bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key5b to value 0"] -impl crate::Resettable for SgiKey5bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5c.rs b/mcxa276-pac/src/sgi0/sgi_key5c.rs deleted file mode 100644 index 3d6ba076f..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key5c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key5c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key5c` writer"] -pub type W = crate::W; -#[doc = "Field `key5c` reader - Input Key register"] -pub type Key5cR = crate::FieldReader; -#[doc = "Field `key5c` writer - Input Key register"] -pub type Key5cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5c(&self) -> Key5cR { - Key5cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5c(&mut self) -> Key5cW { - Key5cW::new(self, 0) - } -} -#[doc = "Input Key register 5 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey5cSpec; -impl crate::RegisterSpec for SgiKey5cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key5c::R`](R) reader structure"] -impl crate::Readable for SgiKey5cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key5c::W`](W) writer structure"] -impl crate::Writable for SgiKey5cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key5c to value 0"] -impl crate::Resettable for SgiKey5cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key5d.rs b/mcxa276-pac/src/sgi0/sgi_key5d.rs deleted file mode 100644 index 1115a5c8d..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key5d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key5d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key5d` writer"] -pub type W = crate::W; -#[doc = "Field `key5d` reader - Input Key register"] -pub type Key5dR = crate::FieldReader; -#[doc = "Field `key5d` writer - Input Key register"] -pub type Key5dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5d(&self) -> Key5dR { - Key5dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key5d(&mut self) -> Key5dW { - Key5dW::new(self, 0) - } -} -#[doc = "Input Key register 5 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key5d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key5d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey5dSpec; -impl crate::RegisterSpec for SgiKey5dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key5d::R`](R) reader structure"] -impl crate::Readable for SgiKey5dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key5d::W`](W) writer structure"] -impl crate::Writable for SgiKey5dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key5d to value 0"] -impl crate::Resettable for SgiKey5dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6a.rs b/mcxa276-pac/src/sgi0/sgi_key6a.rs deleted file mode 100644 index 1f42bd877..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key6a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key6a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key6a` writer"] -pub type W = crate::W; -#[doc = "Field `key6a` reader - Input Key register"] -pub type Key6aR = crate::FieldReader; -#[doc = "Field `key6a` writer - Input Key register"] -pub type Key6aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6a(&self) -> Key6aR { - Key6aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6a(&mut self) -> Key6aW { - Key6aW::new(self, 0) - } -} -#[doc = "Input Key register 6 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey6aSpec; -impl crate::RegisterSpec for SgiKey6aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key6a::R`](R) reader structure"] -impl crate::Readable for SgiKey6aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key6a::W`](W) writer structure"] -impl crate::Writable for SgiKey6aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key6a to value 0"] -impl crate::Resettable for SgiKey6aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6b.rs b/mcxa276-pac/src/sgi0/sgi_key6b.rs deleted file mode 100644 index f24ae3244..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key6b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key6b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key6b` writer"] -pub type W = crate::W; -#[doc = "Field `key6b` reader - Input Key register"] -pub type Key6bR = crate::FieldReader; -#[doc = "Field `key6b` writer - Input Key register"] -pub type Key6bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6b(&self) -> Key6bR { - Key6bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6b(&mut self) -> Key6bW { - Key6bW::new(self, 0) - } -} -#[doc = "Input Key register 6 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey6bSpec; -impl crate::RegisterSpec for SgiKey6bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key6b::R`](R) reader structure"] -impl crate::Readable for SgiKey6bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key6b::W`](W) writer structure"] -impl crate::Writable for SgiKey6bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key6b to value 0"] -impl crate::Resettable for SgiKey6bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6c.rs b/mcxa276-pac/src/sgi0/sgi_key6c.rs deleted file mode 100644 index 1786bd41e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key6c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key6c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key6c` writer"] -pub type W = crate::W; -#[doc = "Field `key6c` reader - Input Key register"] -pub type Key6cR = crate::FieldReader; -#[doc = "Field `key6c` writer - Input Key register"] -pub type Key6cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6c(&self) -> Key6cR { - Key6cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6c(&mut self) -> Key6cW { - Key6cW::new(self, 0) - } -} -#[doc = "Input Key register 6 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey6cSpec; -impl crate::RegisterSpec for SgiKey6cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key6c::R`](R) reader structure"] -impl crate::Readable for SgiKey6cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key6c::W`](W) writer structure"] -impl crate::Writable for SgiKey6cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key6c to value 0"] -impl crate::Resettable for SgiKey6cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key6d.rs b/mcxa276-pac/src/sgi0/sgi_key6d.rs deleted file mode 100644 index 023340890..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key6d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key6d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key6d` writer"] -pub type W = crate::W; -#[doc = "Field `key6d` reader - Input Key register"] -pub type Key6dR = crate::FieldReader; -#[doc = "Field `key6d` writer - Input Key register"] -pub type Key6dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6d(&self) -> Key6dR { - Key6dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key6d(&mut self) -> Key6dW { - Key6dW::new(self, 0) - } -} -#[doc = "Input Key register 6 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key6d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key6d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey6dSpec; -impl crate::RegisterSpec for SgiKey6dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key6d::R`](R) reader structure"] -impl crate::Readable for SgiKey6dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key6d::W`](W) writer structure"] -impl crate::Writable for SgiKey6dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key6d to value 0"] -impl crate::Resettable for SgiKey6dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7a.rs b/mcxa276-pac/src/sgi0/sgi_key7a.rs deleted file mode 100644 index 1458ede0c..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key7a.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key7a` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key7a` writer"] -pub type W = crate::W; -#[doc = "Field `key7a` reader - Input Key register"] -pub type Key7aR = crate::FieldReader; -#[doc = "Field `key7a` writer - Input Key register"] -pub type Key7aW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7a(&self) -> Key7aR { - Key7aR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7a(&mut self) -> Key7aW { - Key7aW::new(self, 0) - } -} -#[doc = "Input Key register 7 - Word-3\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7a::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7a::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey7aSpec; -impl crate::RegisterSpec for SgiKey7aSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key7a::R`](R) reader structure"] -impl crate::Readable for SgiKey7aSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key7a::W`](W) writer structure"] -impl crate::Writable for SgiKey7aSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key7a to value 0"] -impl crate::Resettable for SgiKey7aSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7b.rs b/mcxa276-pac/src/sgi0/sgi_key7b.rs deleted file mode 100644 index d56cc4160..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key7b.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key7b` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key7b` writer"] -pub type W = crate::W; -#[doc = "Field `key7b` reader - Input Key register"] -pub type Key7bR = crate::FieldReader; -#[doc = "Field `key7b` writer - Input Key register"] -pub type Key7bW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7b(&self) -> Key7bR { - Key7bR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7b(&mut self) -> Key7bW { - Key7bW::new(self, 0) - } -} -#[doc = "Input Key register 7 - Word-2\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7b::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7b::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey7bSpec; -impl crate::RegisterSpec for SgiKey7bSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key7b::R`](R) reader structure"] -impl crate::Readable for SgiKey7bSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key7b::W`](W) writer structure"] -impl crate::Writable for SgiKey7bSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key7b to value 0"] -impl crate::Resettable for SgiKey7bSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7c.rs b/mcxa276-pac/src/sgi0/sgi_key7c.rs deleted file mode 100644 index 293448a85..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key7c.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key7c` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key7c` writer"] -pub type W = crate::W; -#[doc = "Field `key7c` reader - Input Key register"] -pub type Key7cR = crate::FieldReader; -#[doc = "Field `key7c` writer - Input Key register"] -pub type Key7cW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7c(&self) -> Key7cR { - Key7cR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7c(&mut self) -> Key7cW { - Key7cW::new(self, 0) - } -} -#[doc = "Input Key register 7 - Word-1\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey7cSpec; -impl crate::RegisterSpec for SgiKey7cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key7c::R`](R) reader structure"] -impl crate::Readable for SgiKey7cSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key7c::W`](W) writer structure"] -impl crate::Writable for SgiKey7cSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key7c to value 0"] -impl crate::Resettable for SgiKey7cSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key7d.rs b/mcxa276-pac/src/sgi0/sgi_key7d.rs deleted file mode 100644 index 8f69b3a10..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key7d.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key7d` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key7d` writer"] -pub type W = crate::W; -#[doc = "Field `key7d` reader - Input Key register"] -pub type Key7dR = crate::FieldReader; -#[doc = "Field `key7d` writer - Input Key register"] -pub type Key7dW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7d(&self) -> Key7dR { - Key7dR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Input Key register"] - #[inline(always)] - pub fn key7d(&mut self) -> Key7dW { - Key7dW::new(self, 0) - } -} -#[doc = "Input Key register 7 - Word-0\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key7d::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key7d::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKey7dSpec; -impl crate::RegisterSpec for SgiKey7dSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key7d::R`](R) reader structure"] -impl crate::Readable for SgiKey7dSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key7d::W`](W) writer structure"] -impl crate::Writable for SgiKey7dSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key7d to value 0"] -impl crate::Resettable for SgiKey7dSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_key_ctrl.rs deleted file mode 100644 index b8372c41e..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key_ctrl.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_key_ctrl` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_key_ctrl` writer"] -pub type W = crate::W; -#[doc = "Field `key_wo` reader - SGI Key control register(1-bit per KEY SFR)"] -pub type KeyWoR = crate::FieldReader; -#[doc = "Field `key_wo` writer - SGI Key control register(1-bit per KEY SFR)"] -pub type KeyWoW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - SGI Key control register(1-bit per KEY SFR)"] - #[inline(always)] - pub fn key_wo(&self) -> KeyWoR { - KeyWoR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - SGI Key control register(1-bit per KEY SFR)"] - #[inline(always)] - pub fn key_wo(&mut self) -> KeyWoW { - KeyWoW::new(self, 0) - } -} -#[doc = "SGI Key Control SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_key_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKeyCtrlSpec; -impl crate::RegisterSpec for SgiKeyCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key_ctrl::R`](R) reader structure"] -impl crate::Readable for SgiKeyCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_key_ctrl::W`](W) writer structure"] -impl crate::Writable for SgiKeyCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_key_ctrl to value 0"] -impl crate::Resettable for SgiKeyCtrlSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_key_wrap.rs b/mcxa276-pac/src/sgi0/sgi_key_wrap.rs deleted file mode 100644 index f6504b19b..000000000 --- a/mcxa276-pac/src/sgi0/sgi_key_wrap.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `sgi_key_wrap` reader"] -pub type R = crate::R; -#[doc = "Field `kw_data` reader - Field contains wrapped key, auto-updated by HW for each word"] -pub type KwDataR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Field contains wrapped key, auto-updated by HW for each word"] - #[inline(always)] - pub fn kw_data(&self) -> KwDataR { - KwDataR::new(self.bits) - } -} -#[doc = "Wrapped key read SFR\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_key_wrap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKeyWrapSpec; -impl crate::RegisterSpec for SgiKeyWrapSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_key_wrap::R`](R) reader structure"] -impl crate::Readable for SgiKeyWrapSpec {} -#[doc = "`reset()` method sets sgi_key_wrap to value 0"] -impl crate::Resettable for SgiKeyWrapSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_keychk.rs b/mcxa276-pac/src/sgi0/sgi_keychk.rs deleted file mode 100644 index 6ca36ddc2..000000000 --- a/mcxa276-pac/src/sgi0/sgi_keychk.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_keychk` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_keychk` writer"] -pub type W = crate::W; -#[doc = "Field `keychksum` reader - Key checksum (32-bit)."] -pub type KeychksumR = crate::FieldReader; -#[doc = "Field `keychksum` writer - Key checksum (32-bit)."] -pub type KeychksumW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Key checksum (32-bit)."] - #[inline(always)] - pub fn keychksum(&self) -> KeychksumR { - KeychksumR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Key checksum (32-bit)."] - #[inline(always)] - pub fn keychksum(&mut self) -> KeychksumW { - KeychksumW::new(self, 0) - } -} -#[doc = "Key checksum register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_keychk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_keychk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiKeychkSpec; -impl crate::RegisterSpec for SgiKeychkSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_keychk::R`](R) reader structure"] -impl crate::Readable for SgiKeychkSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_keychk::W`](W) writer structure"] -impl crate::Writable for SgiKeychkSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_keychk to value 0"] -impl crate::Resettable for SgiKeychkSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_module_id.rs b/mcxa276-pac/src/sgi0/sgi_module_id.rs deleted file mode 100644 index e2e006a41..000000000 --- a/mcxa276-pac/src/sgi0/sgi_module_id.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `sgi_module_id` reader"] -pub type R = crate::R; -#[doc = "Field `placeholder` reader - Module ID"] -pub type PlaceholderR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Module ID"] - #[inline(always)] - pub fn placeholder(&self) -> PlaceholderR { - PlaceholderR::new(self.bits) - } -} -#[doc = "Module ID\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_module_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiModuleIdSpec; -impl crate::RegisterSpec for SgiModuleIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_module_id::R`](R) reader structure"] -impl crate::Readable for SgiModuleIdSpec {} -#[doc = "`reset()` method sets sgi_module_id to value 0"] -impl crate::Resettable for SgiModuleIdSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs b/mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs deleted file mode 100644 index e5842648a..000000000 --- a/mcxa276-pac/src/sgi0/sgi_prng_sw_seed.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_prng_sw_seed` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_prng_sw_seed` writer"] -pub type W = crate::W; -#[doc = "Field `seed` reader - 32-bits SEED field. A write to the SEED field"] -pub type SeedR = crate::FieldReader; -#[doc = "Field `seed` writer - 32-bits SEED field. A write to the SEED field"] -pub type SeedW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - 32-bits SEED field. A write to the SEED field"] - #[inline(always)] - pub fn seed(&self) -> SeedR { - SeedR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - 32-bits SEED field. A write to the SEED field"] - #[inline(always)] - pub fn seed(&mut self) -> SeedW { - SeedW::new(self, 0) - } -} -#[doc = "SGI internal PRNG SW seeding register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_prng_sw_seed::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_prng_sw_seed::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiPrngSwSeedSpec; -impl crate::RegisterSpec for SgiPrngSwSeedSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_prng_sw_seed::R`](R) reader structure"] -impl crate::Readable for SgiPrngSwSeedSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_prng_sw_seed::W`](W) writer structure"] -impl crate::Writable for SgiPrngSwSeedSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_prng_sw_seed to value 0"] -impl crate::Resettable for SgiPrngSwSeedSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs b/mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs deleted file mode 100644 index d93cfcdaa..000000000 --- a/mcxa276-pac/src/sgi0/sgi_sfr_sw_mask.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_sfr_sw_mask` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_sfr_sw_mask` writer"] -pub type W = crate::W; -#[doc = "Field `sfr_mask_val` reader - Seed/mask used for sw level masking"] -pub type SfrMaskValR = crate::FieldReader; -#[doc = "Field `sfr_mask_val` writer - Seed/mask used for sw level masking"] -pub type SfrMaskValW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] - #[inline(always)] - pub fn sfr_mask_val(&self) -> SfrMaskValR { - SfrMaskValR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] - #[inline(always)] - pub fn sfr_mask_val(&mut self) -> SfrMaskValW { - SfrMaskValW::new(self, 0) - } -} -#[doc = "Sofware Assisted Masking register .\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfr_sw_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfr_sw_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiSfrSwMaskSpec; -impl crate::RegisterSpec for SgiSfrSwMaskSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_sfr_sw_mask::R`](R) reader structure"] -impl crate::Readable for SgiSfrSwMaskSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_sfr_sw_mask::W`](W) writer structure"] -impl crate::Writable for SgiSfrSwMaskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_sfr_sw_mask to value 0"] -impl crate::Resettable for SgiSfrSwMaskSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_sfrseed.rs b/mcxa276-pac/src/sgi0/sgi_sfrseed.rs deleted file mode 100644 index a478d595c..000000000 --- a/mcxa276-pac/src/sgi0/sgi_sfrseed.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_sfrseed` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_sfrseed` writer"] -pub type W = crate::W; -#[doc = "Field `sfrseed` reader - Seed/mask used for sw level masking"] -pub type SfrseedR = crate::FieldReader; -#[doc = "Field `sfrseed` writer - Seed/mask used for sw level masking"] -pub type SfrseedW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] - #[inline(always)] - pub fn sfrseed(&self) -> SfrseedR { - SfrseedR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Seed/mask used for sw level masking"] - #[inline(always)] - pub fn sfrseed(&mut self) -> SfrseedW { - SfrseedW::new(self, 0) - } -} -#[doc = "SFRSEED register for SFRMASK feature.\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sfrseed::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sfrseed::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiSfrseedSpec; -impl crate::RegisterSpec for SgiSfrseedSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_sfrseed::R`](R) reader structure"] -impl crate::Readable for SgiSfrseedSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_sfrseed::W`](W) writer structure"] -impl crate::Writable for SgiSfrseedSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_sfrseed to value 0"] -impl crate::Resettable for SgiSfrseedSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs b/mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs deleted file mode 100644 index 33f690c7c..000000000 --- a/mcxa276-pac/src/sgi0/sgi_sha2_ctrl.rs +++ /dev/null @@ -1,149 +0,0 @@ -#[doc = "Register `sgi_sha2_ctrl` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_sha2_ctrl` writer"] -pub type W = crate::W; -#[doc = "Field `sha2_en` reader - SHA enable"] -pub type Sha2EnR = crate::BitReader; -#[doc = "Field `sha2_en` writer - SHA enable"] -pub type Sha2EnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sha2_mode` reader - SHA mode normal or automatic"] -pub type Sha2ModeR = crate::BitReader; -#[doc = "Field `sha2_mode` writer - SHA mode normal or automatic"] -pub type Sha2ModeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sha2_size` reader - SHA size 0=224;1=256;2=384;3=512"] -pub type Sha2SizeR = crate::FieldReader; -#[doc = "Field `sha2_size` writer - SHA size 0=224;1=256;2=384;3=512"] -pub type Sha2SizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `sha2_low_lim` reader - SHA FIFO low limit"] -pub type Sha2LowLimR = crate::FieldReader; -#[doc = "Field `sha2_low_lim` writer - SHA FIFO low limit"] -pub type Sha2LowLimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `sha2_high_lim` reader - SHA FIFO high limit"] -pub type Sha2HighLimR = crate::FieldReader; -#[doc = "Field `sha2_high_lim` writer - SHA FIFO high limit"] -pub type Sha2HighLimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `sha2_count_en` reader - SHA Calculation counter enable"] -pub type Sha2CountEnR = crate::BitReader; -#[doc = "Field `sha2_count_en` writer - SHA Calculation counter enable"] -pub type Sha2CountEnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `hash_reload` reader - SHA HASH reload"] -pub type HashReloadR = crate::BitReader; -#[doc = "Field `hash_reload` writer - SHA HASH reload"] -pub type HashReloadW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sha2_stop` writer - STOP SHA AUTO mode"] -pub type Sha2StopW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `no_auto_init` reader - SHA no automatic HASH initialisation"] -pub type NoAutoInitR = crate::BitReader; -#[doc = "Field `no_auto_init` writer - SHA no automatic HASH initialisation"] -pub type NoAutoInitW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sha2ctl_rsvd` reader - reserved"] -pub type Sha2ctlRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - SHA enable"] - #[inline(always)] - pub fn sha2_en(&self) -> Sha2EnR { - Sha2EnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SHA mode normal or automatic"] - #[inline(always)] - pub fn sha2_mode(&self) -> Sha2ModeR { - Sha2ModeR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - SHA size 0=224;1=256;2=384;3=512"] - #[inline(always)] - pub fn sha2_size(&self) -> Sha2SizeR { - Sha2SizeR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:7 - SHA FIFO low limit"] - #[inline(always)] - pub fn sha2_low_lim(&self) -> Sha2LowLimR { - Sha2LowLimR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - SHA FIFO high limit"] - #[inline(always)] - pub fn sha2_high_lim(&self) -> Sha2HighLimR { - Sha2HighLimR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12 - SHA Calculation counter enable"] - #[inline(always)] - pub fn sha2_count_en(&self) -> Sha2CountEnR { - Sha2CountEnR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SHA HASH reload"] - #[inline(always)] - pub fn hash_reload(&self) -> HashReloadR { - HashReloadR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - SHA no automatic HASH initialisation"] - #[inline(always)] - pub fn no_auto_init(&self) -> NoAutoInitR { - NoAutoInitR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:31 - reserved"] - #[inline(always)] - pub fn sha2ctl_rsvd(&self) -> Sha2ctlRsvdR { - Sha2ctlRsvdR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bit 0 - SHA enable"] - #[inline(always)] - pub fn sha2_en(&mut self) -> Sha2EnW { - Sha2EnW::new(self, 0) - } - #[doc = "Bit 1 - SHA mode normal or automatic"] - #[inline(always)] - pub fn sha2_mode(&mut self) -> Sha2ModeW { - Sha2ModeW::new(self, 1) - } - #[doc = "Bits 2:3 - SHA size 0=224;1=256;2=384;3=512"] - #[inline(always)] - pub fn sha2_size(&mut self) -> Sha2SizeW { - Sha2SizeW::new(self, 2) - } - #[doc = "Bits 4:7 - SHA FIFO low limit"] - #[inline(always)] - pub fn sha2_low_lim(&mut self) -> Sha2LowLimW { - Sha2LowLimW::new(self, 4) - } - #[doc = "Bits 8:11 - SHA FIFO high limit"] - #[inline(always)] - pub fn sha2_high_lim(&mut self) -> Sha2HighLimW { - Sha2HighLimW::new(self, 8) - } - #[doc = "Bit 12 - SHA Calculation counter enable"] - #[inline(always)] - pub fn sha2_count_en(&mut self) -> Sha2CountEnW { - Sha2CountEnW::new(self, 12) - } - #[doc = "Bit 13 - SHA HASH reload"] - #[inline(always)] - pub fn hash_reload(&mut self) -> HashReloadW { - HashReloadW::new(self, 13) - } - #[doc = "Bit 14 - STOP SHA AUTO mode"] - #[inline(always)] - pub fn sha2_stop(&mut self) -> Sha2StopW { - Sha2StopW::new(self, 14) - } - #[doc = "Bit 15 - SHA no automatic HASH initialisation"] - #[inline(always)] - pub fn no_auto_init(&mut self) -> NoAutoInitW { - NoAutoInitW::new(self, 15) - } -} -#[doc = "SHA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiSha2CtrlSpec; -impl crate::RegisterSpec for SgiSha2CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_sha2_ctrl::R`](R) reader structure"] -impl crate::Readable for SgiSha2CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_sha2_ctrl::W`](W) writer structure"] -impl crate::Writable for SgiSha2CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_sha2_ctrl to value 0x0f00"] -impl crate::Resettable for SgiSha2CtrlSpec { - const RESET_VALUE: u32 = 0x0f00; -} diff --git a/mcxa276-pac/src/sgi0/sgi_sha_fifo.rs b/mcxa276-pac/src/sgi0/sgi_sha_fifo.rs deleted file mode 100644 index 0606e6fd8..000000000 --- a/mcxa276-pac/src/sgi0/sgi_sha_fifo.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `sgi_sha_fifo` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_sha_fifo` writer"] -pub type W = crate::W; -#[doc = "Field `fifo` reader - SHA FIFO register"] -pub type FifoR = crate::FieldReader; -#[doc = "Field `fifo` writer - SHA FIFO register"] -pub type FifoW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - SHA FIFO register"] - #[inline(always)] - pub fn fifo(&self) -> FifoR { - FifoR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - SHA FIFO register"] - #[inline(always)] - pub fn fifo(&mut self) -> FifoW { - FifoW::new(self, 0) - } -} -#[doc = "SHA FIFO lower-bank low\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_sha_fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_sha_fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiShaFifoSpec; -impl crate::RegisterSpec for SgiShaFifoSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_sha_fifo::R`](R) reader structure"] -impl crate::Readable for SgiShaFifoSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_sha_fifo::W`](W) writer structure"] -impl crate::Writable for SgiShaFifoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_sha_fifo to value 0"] -impl crate::Resettable for SgiShaFifoSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_status.rs b/mcxa276-pac/src/sgi0/sgi_status.rs deleted file mode 100644 index 86f20ce49..000000000 --- a/mcxa276-pac/src/sgi0/sgi_status.rs +++ /dev/null @@ -1,203 +0,0 @@ -#[doc = "Register `sgi_status` reader"] -pub type R = crate::R; -#[doc = "Register `sgi_status` writer"] -pub type W = crate::W; -#[doc = "Field `busy` reader - Combined busy flag that remains high"] -pub type BusyR = crate::BitReader; -#[doc = "Field `oflow` reader - Overflow in INCR operation flag"] -pub type OflowR = crate::BitReader; -#[doc = "Field `oflow` writer - Overflow in INCR operation flag"] -pub type OflowW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `prng_rdy` reader - prng is ready after boot-up-phase"] -pub type PrngRdyR = crate::BitReader; -#[doc = "Error detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Error { - #[doc = "0: ERROR(all values other than 0x05 indicate ERROR)"] - Error = 0, - #[doc = "5: NO_ERROR"] - NoError = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Error) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Error { - type Ux = u8; -} -impl crate::IsEnum for Error {} -#[doc = "Field `error` reader - Error detected"] -pub type ErrorR = crate::FieldReader; -impl ErrorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Error::Error), - 5 => Some(Error::NoError), - _ => None, - } - } - #[doc = "ERROR(all values other than 0x05 indicate ERROR)"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == Error::Error - } - #[doc = "NO_ERROR"] - #[inline(always)] - pub fn is_no_error(&self) -> bool { - *self == Error::NoError - } -} -#[doc = "Field `error` writer - Error detected"] -pub type ErrorW<'a, REG> = crate::FieldWriter<'a, REG, 3, Error>; -impl<'a, REG> ErrorW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "ERROR(all values other than 0x05 indicate ERROR)"] - #[inline(always)] - pub fn error(self) -> &'a mut crate::W { - self.variant(Error::Error) - } - #[doc = "NO_ERROR"] - #[inline(always)] - pub fn no_error(self) -> &'a mut crate::W { - self.variant(Error::NoError) - } -} -#[doc = "Field `sha2_busy` reader - SHA2 is busy"] -pub type Sha2BusyR = crate::BitReader; -#[doc = "Field `irq` reader - interrupt detected"] -pub type IrqR = crate::BitReader; -#[doc = "Field `irq` writer - interrupt detected"] -pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sha_fifo_full` reader - SHA FIFO is full(operates in SHA AUTO mode)"] -pub type ShaFifoFullR = crate::BitReader; -#[doc = "Field `sha_fifo_level` reader - SHA FIFO level"] -pub type ShaFifoLevelR = crate::FieldReader; -#[doc = "Field `sha_error` reader - SHA ERROR"] -pub type ShaErrorR = crate::BitReader; -#[doc = "Field `key_read_err` reader - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] -pub type KeyReadErrR = crate::BitReader; -#[doc = "Field `key_read_err` writer - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] -pub type KeyReadErrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `key_unwrap_err` reader - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] -pub type KeyUnwrapErrR = crate::BitReader; -#[doc = "Field `key_unwrap_err` writer - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] -pub type KeyUnwrapErrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `status_rsvd3` reader - reserved"] -pub type StatusRsvd3R = crate::BitReader; -#[doc = "Field `status_rsvd` reader - reserved"] -pub type StatusRsvdR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Combined busy flag that remains high"] - #[inline(always)] - pub fn busy(&self) -> BusyR { - BusyR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Overflow in INCR operation flag"] - #[inline(always)] - pub fn oflow(&self) -> OflowR { - OflowR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - prng is ready after boot-up-phase"] - #[inline(always)] - pub fn prng_rdy(&self) -> PrngRdyR { - PrngRdyR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 3:5 - Error detected"] - #[inline(always)] - pub fn error(&self) -> ErrorR { - ErrorR::new(((self.bits >> 3) & 7) as u8) - } - #[doc = "Bit 6 - SHA2 is busy"] - #[inline(always)] - pub fn sha2_busy(&self) -> Sha2BusyR { - Sha2BusyR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - interrupt detected"] - #[inline(always)] - pub fn irq(&self) -> IrqR { - IrqR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - SHA FIFO is full(operates in SHA AUTO mode)"] - #[inline(always)] - pub fn sha_fifo_full(&self) -> ShaFifoFullR { - ShaFifoFullR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 9:14 - SHA FIFO level"] - #[inline(always)] - pub fn sha_fifo_level(&self) -> ShaFifoLevelR { - ShaFifoLevelR::new(((self.bits >> 9) & 0x3f) as u8) - } - #[doc = "Bit 15 - SHA ERROR"] - #[inline(always)] - pub fn sha_error(&self) -> ShaErrorR { - ShaErrorR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] - #[inline(always)] - pub fn key_read_err(&self) -> KeyReadErrR { - KeyReadErrR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] - #[inline(always)] - pub fn key_unwrap_err(&self) -> KeyUnwrapErrR { - KeyUnwrapErrR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - reserved"] - #[inline(always)] - pub fn status_rsvd3(&self) -> StatusRsvd3R { - StatusRsvd3R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bits 19:31 - reserved"] - #[inline(always)] - pub fn status_rsvd(&self) -> StatusRsvdR { - StatusRsvdR::new(((self.bits >> 19) & 0x1fff) as u16) - } -} -impl W { - #[doc = "Bit 1 - Overflow in INCR operation flag"] - #[inline(always)] - pub fn oflow(&mut self) -> OflowW { - OflowW::new(self, 1) - } - #[doc = "Bits 3:5 - Error detected"] - #[inline(always)] - pub fn error(&mut self) -> ErrorW { - ErrorW::new(self, 3) - } - #[doc = "Bit 7 - interrupt detected"] - #[inline(always)] - pub fn irq(&mut self) -> IrqW { - IrqW::new(self, 7) - } - #[doc = "Bit 16 - KEY SFR READ ERROR, sticky, cleared only with reset or flush"] - #[inline(always)] - pub fn key_read_err(&mut self) -> KeyReadErrW { - KeyReadErrW::new(self, 16) - } - #[doc = "Bit 17 - KEY UNWRAP ERROR , sticky, cleared only with reset or flush"] - #[inline(always)] - pub fn key_unwrap_err(&mut self) -> KeyUnwrapErrW { - KeyUnwrapErrW::new(self, 17) - } -} -#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiStatusSpec; -impl crate::RegisterSpec for SgiStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_status::R`](R) reader structure"] -impl crate::Readable for SgiStatusSpec {} -#[doc = "`write(|w| ..)` method takes [`sgi_status::W`](W) writer structure"] -impl crate::Writable for SgiStatusSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets sgi_status to value 0"] -impl crate::Resettable for SgiStatusSpec {} diff --git a/mcxa276-pac/src/sgi0/sgi_version.rs b/mcxa276-pac/src/sgi0/sgi_version.rs deleted file mode 100644 index 184804f18..000000000 --- a/mcxa276-pac/src/sgi0/sgi_version.rs +++ /dev/null @@ -1,55 +0,0 @@ -#[doc = "Register `sgi_version` reader"] -pub type R = crate::R; -#[doc = "Field `z` reader - Extended revision number in X.Y1Y2.Z, e.g. 1.20.3."] -pub type ZR = crate::FieldReader; -#[doc = "Field `y2` reader - Minor revision number 2 in X.Y1Y2.Z, e.g. 1.20.3."] -pub type Y2R = crate::FieldReader; -#[doc = "Field `y1` reader - Minor revision number 1 in X.Y1Y2.Z, e.g. 1.20.3."] -pub type Y1R = crate::FieldReader; -#[doc = "Field `x` reader - Major revision number in X.Y1Y2.Z, e.g. 1.20.3."] -pub type XR = crate::FieldReader; -#[doc = "Field `milestone` reader - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] -pub type MilestoneR = crate::FieldReader; -#[doc = "Field `version_rsvd_1` reader - Reserved for Future Use"] -pub type VersionRsvd1R = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Extended revision number in X.Y1Y2.Z, e.g. 1.20.3."] - #[inline(always)] - pub fn z(&self) -> ZR { - ZR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - Minor revision number 2 in X.Y1Y2.Z, e.g. 1.20.3."] - #[inline(always)] - pub fn y2(&self) -> Y2R { - Y2R::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - Minor revision number 1 in X.Y1Y2.Z, e.g. 1.20.3."] - #[inline(always)] - pub fn y1(&self) -> Y1R { - Y1R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Major revision number in X.Y1Y2.Z, e.g. 1.20.3."] - #[inline(always)] - pub fn x(&self) -> XR { - XR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:17 - Release milestone. 00-PREL, 01-BR, 10-SI, 11-GO."] - #[inline(always)] - pub fn milestone(&self) -> MilestoneR { - MilestoneR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:31 - Reserved for Future Use"] - #[inline(always)] - pub fn version_rsvd_1(&self) -> VersionRsvd1R { - VersionRsvd1R::new(((self.bits >> 18) & 0x3fff) as u16) - } -} -#[doc = "SGI Version\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SgiVersionSpec; -impl crate::RegisterSpec for SgiVersionSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sgi_version::R`](R) reader structure"] -impl crate::Readable for SgiVersionSpec {} -#[doc = "`reset()` method sets sgi_version to value 0"] -impl crate::Resettable for SgiVersionSpec {} diff --git a/mcxa276-pac/src/slcd0.rs b/mcxa276-pac/src/slcd0.rs deleted file mode 100644 index 11330eacd..000000000 --- a/mcxa276-pac/src/slcd0.rs +++ /dev/null @@ -1,111 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - lcd_gcr: LcdGcr, - lcd_ar: LcdAr, - lcd_fdcr: LcdFdcr, - lcd_fdsr: LcdFdsr, - lcd_pen0: LcdPen0, - lcd_pen1: LcdPen1, - lcd_bpen0: LcdBpen0, - lcd_bpen1: LcdBpen1, - lcd_wfto: [LcdWfto; 12], -} -impl RegisterBlock { - #[doc = "0x00 - LCD General Control Register"] - #[inline(always)] - pub const fn lcd_gcr(&self) -> &LcdGcr { - &self.lcd_gcr - } - #[doc = "0x04 - LCD Auxiliary Register"] - #[inline(always)] - pub const fn lcd_ar(&self) -> &LcdAr { - &self.lcd_ar - } - #[doc = "0x08 - LCD Fault Detect Control Register"] - #[inline(always)] - pub const fn lcd_fdcr(&self) -> &LcdFdcr { - &self.lcd_fdcr - } - #[doc = "0x0c - LCD Fault Detect Status Register"] - #[inline(always)] - pub const fn lcd_fdsr(&self) -> &LcdFdsr { - &self.lcd_fdsr - } - #[doc = "0x10 - LCD Pin Enable Register 0"] - #[inline(always)] - pub const fn lcd_pen0(&self) -> &LcdPen0 { - &self.lcd_pen0 - } - #[doc = "0x14 - LCD Pin Enable Register 1"] - #[inline(always)] - pub const fn lcd_pen1(&self) -> &LcdPen1 { - &self.lcd_pen1 - } - #[doc = "0x18 - LCD Back Plane Enable Register 0"] - #[inline(always)] - pub const fn lcd_bpen0(&self) -> &LcdBpen0 { - &self.lcd_bpen0 - } - #[doc = "0x1c - LCD Back Plane Enable Register 1"] - #[inline(always)] - pub const fn lcd_bpen1(&self) -> &LcdBpen1 { - &self.lcd_bpen1 - } - #[doc = "0x20..0x50 - LCD Waveform i * 4 + 3 to i * 4 Register"] - #[inline(always)] - pub const fn lcd_wfto(&self, n: usize) -> &LcdWfto { - &self.lcd_wfto[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x20..0x50 - LCD Waveform i * 4 + 3 to i * 4 Register"] - #[inline(always)] - pub fn lcd_wfto_iter(&self) -> impl Iterator { - self.lcd_wfto.iter() - } -} -#[doc = "LCD_GCR (rw) register accessor: LCD General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_gcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_gcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_gcr`] module"] -#[doc(alias = "LCD_GCR")] -pub type LcdGcr = crate::Reg; -#[doc = "LCD General Control Register"] -pub mod lcd_gcr; -#[doc = "LCD_AR (rw) register accessor: LCD Auxiliary Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_ar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_ar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_ar`] module"] -#[doc(alias = "LCD_AR")] -pub type LcdAr = crate::Reg; -#[doc = "LCD Auxiliary Register"] -pub mod lcd_ar; -#[doc = "LCD_FDCR (rw) register accessor: LCD Fault Detect Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_fdcr`] module"] -#[doc(alias = "LCD_FDCR")] -pub type LcdFdcr = crate::Reg; -#[doc = "LCD Fault Detect Control Register"] -pub mod lcd_fdcr; -#[doc = "LCD_FDSR (rw) register accessor: LCD Fault Detect Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_fdsr`] module"] -#[doc(alias = "LCD_FDSR")] -pub type LcdFdsr = crate::Reg; -#[doc = "LCD Fault Detect Status Register"] -pub mod lcd_fdsr; -#[doc = "LCD_PEN0 (rw) register accessor: LCD Pin Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_pen0`] module"] -#[doc(alias = "LCD_PEN0")] -pub type LcdPen0 = crate::Reg; -#[doc = "LCD Pin Enable Register 0"] -pub mod lcd_pen0; -#[doc = "LCD_PEN1 (rw) register accessor: LCD Pin Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_pen1`] module"] -#[doc(alias = "LCD_PEN1")] -pub type LcdPen1 = crate::Reg; -#[doc = "LCD Pin Enable Register 1"] -pub mod lcd_pen1; -#[doc = "LCD_BPEN0 (rw) register accessor: LCD Back Plane Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_bpen0`] module"] -#[doc(alias = "LCD_BPEN0")] -pub type LcdBpen0 = crate::Reg; -#[doc = "LCD Back Plane Enable Register 0"] -pub mod lcd_bpen0; -#[doc = "LCD_BPEN1 (rw) register accessor: LCD Back Plane Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_bpen1`] module"] -#[doc(alias = "LCD_BPEN1")] -pub type LcdBpen1 = crate::Reg; -#[doc = "LCD Back Plane Enable Register 1"] -pub mod lcd_bpen1; -#[doc = "LCD_WFTO (rw) register accessor: LCD Waveform i * 4 + 3 to i * 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_wfto::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_wfto::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_wfto`] module"] -#[doc(alias = "LCD_WFTO")] -pub type LcdWfto = crate::Reg; -#[doc = "LCD Waveform i * 4 + 3 to i * 4 Register"] -pub mod lcd_wfto; diff --git a/mcxa276-pac/src/slcd0/lcd_ar.rs b/mcxa276-pac/src/slcd0/lcd_ar.rs deleted file mode 100644 index cf58b5274..000000000 --- a/mcxa276-pac/src/slcd0/lcd_ar.rs +++ /dev/null @@ -1,351 +0,0 @@ -#[doc = "Register `LCD_AR` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_AR` writer"] -pub type W = crate::W; -#[doc = "Field `BRATE` reader - Blink-rate configuration"] -pub type BrateR = crate::FieldReader; -#[doc = "Field `BRATE` writer - Blink-rate configuration"] -pub type BrateW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Blink mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Bmode { - #[doc = "0: Display blank during the blink period."] - Blank = 0, - #[doc = "1: Display alternate display during blink period."] - Alternate = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Bmode) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BMODE` reader - Blink mode"] -pub type BmodeR = crate::BitReader; -impl BmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Bmode { - match self.bits { - false => Bmode::Blank, - true => Bmode::Alternate, - } - } - #[doc = "Display blank during the blink period."] - #[inline(always)] - pub fn is_blank(&self) -> bool { - *self == Bmode::Blank - } - #[doc = "Display alternate display during blink period."] - #[inline(always)] - pub fn is_alternate(&self) -> bool { - *self == Bmode::Alternate - } -} -#[doc = "Field `BMODE` writer - Blink mode"] -pub type BmodeW<'a, REG> = crate::BitWriter<'a, REG, Bmode>; -impl<'a, REG> BmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Display blank during the blink period."] - #[inline(always)] - pub fn blank(self) -> &'a mut crate::W { - self.variant(Bmode::Blank) - } - #[doc = "Display alternate display during blink period."] - #[inline(always)] - pub fn alternate(self) -> &'a mut crate::W { - self.variant(Bmode::Alternate) - } -} -#[doc = "Blank display mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Blank { - #[doc = "0: Normal or alternate display mode."] - NotBlank = 0, - #[doc = "1: Blank display mode."] - Blank = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Blank) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BLANK` reader - Blank display mode"] -pub type BlankR = crate::BitReader; -impl BlankR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Blank { - match self.bits { - false => Blank::NotBlank, - true => Blank::Blank, - } - } - #[doc = "Normal or alternate display mode."] - #[inline(always)] - pub fn is_not_blank(&self) -> bool { - *self == Blank::NotBlank - } - #[doc = "Blank display mode."] - #[inline(always)] - pub fn is_blank(&self) -> bool { - *self == Blank::Blank - } -} -#[doc = "Field `BLANK` writer - Blank display mode"] -pub type BlankW<'a, REG> = crate::BitWriter<'a, REG, Blank>; -impl<'a, REG> BlankW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal or alternate display mode."] - #[inline(always)] - pub fn not_blank(self) -> &'a mut crate::W { - self.variant(Blank::NotBlank) - } - #[doc = "Blank display mode."] - #[inline(always)] - pub fn blank(self) -> &'a mut crate::W { - self.variant(Blank::Blank) - } -} -#[doc = "Alternate display mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Alt { - #[doc = "0: Normal display mode."] - Normal = 0, - #[doc = "1: Alternate display mode."] - Alternate = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Alt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ALT` reader - Alternate display mode"] -pub type AltR = crate::BitReader; -impl AltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Alt { - match self.bits { - false => Alt::Normal, - true => Alt::Alternate, - } - } - #[doc = "Normal display mode."] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == Alt::Normal - } - #[doc = "Alternate display mode."] - #[inline(always)] - pub fn is_alternate(&self) -> bool { - *self == Alt::Alternate - } -} -#[doc = "Field `ALT` writer - Alternate display mode"] -pub type AltW<'a, REG> = crate::BitWriter<'a, REG, Alt>; -impl<'a, REG> AltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal display mode."] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(Alt::Normal) - } - #[doc = "Alternate display mode."] - #[inline(always)] - pub fn alternate(self) -> &'a mut crate::W { - self.variant(Alt::Alternate) - } -} -#[doc = "Blink command\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Blink { - #[doc = "0: Disables blinking."] - Disable = 0, - #[doc = "1: Starts blinking at blinking frequency specified by LCD blink rate calculation."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Blink) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BLINK` reader - Blink command"] -pub type BlinkR = crate::BitReader; -impl BlinkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Blink { - match self.bits { - false => Blink::Disable, - true => Blink::Enable, - } - } - #[doc = "Disables blinking."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Blink::Disable - } - #[doc = "Starts blinking at blinking frequency specified by LCD blink rate calculation."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Blink::Enable - } -} -#[doc = "Field `BLINK` writer - Blink command"] -pub type BlinkW<'a, REG> = crate::BitWriter<'a, REG, Blink>; -impl<'a, REG> BlinkW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables blinking."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Blink::Disable) - } - #[doc = "Starts blinking at blinking frequency specified by LCD blink rate calculation."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Blink::Enable) - } -} -#[doc = "LCD Frame Frequency Interrupt flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lcdif { - #[doc = "0: Frame frequency interrupt condition has not occurred."] - Disable = 0, - #[doc = "1: Start of SLCD frame has occurred."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lcdif) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LCDIF` reader - LCD Frame Frequency Interrupt flag"] -pub type LcdifR = crate::BitReader; -impl LcdifR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lcdif { - match self.bits { - false => Lcdif::Disable, - true => Lcdif::Enable, - } - } - #[doc = "Frame frequency interrupt condition has not occurred."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lcdif::Disable - } - #[doc = "Start of SLCD frame has occurred."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lcdif::Enable - } -} -#[doc = "Field `LCDIF` writer - LCD Frame Frequency Interrupt flag"] -pub type LcdifW<'a, REG> = crate::BitWriter1C<'a, REG, Lcdif>; -impl<'a, REG> LcdifW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Frame frequency interrupt condition has not occurred."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lcdif::Disable) - } - #[doc = "Start of SLCD frame has occurred."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lcdif::Enable) - } -} -impl R { - #[doc = "Bits 0:2 - Blink-rate configuration"] - #[inline(always)] - pub fn brate(&self) -> BrateR { - BrateR::new((self.bits & 7) as u8) - } - #[doc = "Bit 3 - Blink mode"] - #[inline(always)] - pub fn bmode(&self) -> BmodeR { - BmodeR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Blank display mode"] - #[inline(always)] - pub fn blank(&self) -> BlankR { - BlankR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Alternate display mode"] - #[inline(always)] - pub fn alt(&self) -> AltR { - AltR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Blink command"] - #[inline(always)] - pub fn blink(&self) -> BlinkR { - BlinkR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 15 - LCD Frame Frequency Interrupt flag"] - #[inline(always)] - pub fn lcdif(&self) -> LcdifR { - LcdifR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:2 - Blink-rate configuration"] - #[inline(always)] - pub fn brate(&mut self) -> BrateW { - BrateW::new(self, 0) - } - #[doc = "Bit 3 - Blink mode"] - #[inline(always)] - pub fn bmode(&mut self) -> BmodeW { - BmodeW::new(self, 3) - } - #[doc = "Bit 5 - Blank display mode"] - #[inline(always)] - pub fn blank(&mut self) -> BlankW { - BlankW::new(self, 5) - } - #[doc = "Bit 6 - Alternate display mode"] - #[inline(always)] - pub fn alt(&mut self) -> AltW { - AltW::new(self, 6) - } - #[doc = "Bit 7 - Blink command"] - #[inline(always)] - pub fn blink(&mut self) -> BlinkW { - BlinkW::new(self, 7) - } - #[doc = "Bit 15 - LCD Frame Frequency Interrupt flag"] - #[inline(always)] - pub fn lcdif(&mut self) -> LcdifW { - LcdifW::new(self, 15) - } -} -#[doc = "LCD Auxiliary Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_ar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_ar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdArSpec; -impl crate::RegisterSpec for LcdArSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_ar::R`](R) reader structure"] -impl crate::Readable for LcdArSpec {} -#[doc = "`write(|w| ..)` method takes [`lcd_ar::W`](W) writer structure"] -impl crate::Writable for LcdArSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000; -} -#[doc = "`reset()` method sets LCD_AR to value 0"] -impl crate::Resettable for LcdArSpec {} diff --git a/mcxa276-pac/src/slcd0/lcd_bpen0.rs b/mcxa276-pac/src/slcd0/lcd_bpen0.rs deleted file mode 100644 index ad8e1f360..000000000 --- a/mcxa276-pac/src/slcd0/lcd_bpen0.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `LCD_BPEN0` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_BPEN0` writer"] -pub type W = crate::W; -#[doc = "LCD Pin 0 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin0Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin0Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_0_BPEN` reader - LCD Pin 0 Back Plane Enable"] -pub type Pin0BpenR = crate::BitReader; -impl Pin0BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin0Bpen { - match self.bits { - false => Pin0Bpen::Fp, - true => Pin0Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin0Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin0Bpen::Bp - } -} -#[doc = "Field `PIN_0_BPEN` writer - LCD Pin 0 Back Plane Enable"] -pub type Pin0BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin0Bpen>; -impl<'a, REG> Pin0BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin0Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin0Bpen::Bp) - } -} -#[doc = "LCD Pin 1 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin1Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin1Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_1_BPEN` reader - LCD Pin 1 Back Plane Enable"] -pub type Pin1BpenR = crate::BitReader; -impl Pin1BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin1Bpen { - match self.bits { - false => Pin1Bpen::Fp, - true => Pin1Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin1Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin1Bpen::Bp - } -} -#[doc = "Field `PIN_1_BPEN` writer - LCD Pin 1 Back Plane Enable"] -pub type Pin1BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin1Bpen>; -impl<'a, REG> Pin1BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin1Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin1Bpen::Bp) - } -} -#[doc = "LCD Pin 2 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin2Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin2Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_2_BPEN` reader - LCD Pin 2 Back Plane Enable"] -pub type Pin2BpenR = crate::BitReader; -impl Pin2BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin2Bpen { - match self.bits { - false => Pin2Bpen::Fp, - true => Pin2Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin2Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin2Bpen::Bp - } -} -#[doc = "Field `PIN_2_BPEN` writer - LCD Pin 2 Back Plane Enable"] -pub type Pin2BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin2Bpen>; -impl<'a, REG> Pin2BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin2Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin2Bpen::Bp) - } -} -#[doc = "LCD Pin 3 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin3Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin3Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_3_BPEN` reader - LCD Pin 3 Back Plane Enable"] -pub type Pin3BpenR = crate::BitReader; -impl Pin3BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin3Bpen { - match self.bits { - false => Pin3Bpen::Fp, - true => Pin3Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin3Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin3Bpen::Bp - } -} -#[doc = "Field `PIN_3_BPEN` writer - LCD Pin 3 Back Plane Enable"] -pub type Pin3BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin3Bpen>; -impl<'a, REG> Pin3BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin3Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin3Bpen::Bp) - } -} -#[doc = "LCD Pin 4 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin4Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin4Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_4_BPEN` reader - LCD Pin 4 Back Plane Enable"] -pub type Pin4BpenR = crate::BitReader; -impl Pin4BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin4Bpen { - match self.bits { - false => Pin4Bpen::Fp, - true => Pin4Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin4Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin4Bpen::Bp - } -} -#[doc = "Field `PIN_4_BPEN` writer - LCD Pin 4 Back Plane Enable"] -pub type Pin4BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin4Bpen>; -impl<'a, REG> Pin4BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin4Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin4Bpen::Bp) - } -} -#[doc = "LCD Pin 5 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin5Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin5Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_5_BPEN` reader - LCD Pin 5 Back Plane Enable"] -pub type Pin5BpenR = crate::BitReader; -impl Pin5BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin5Bpen { - match self.bits { - false => Pin5Bpen::Fp, - true => Pin5Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin5Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin5Bpen::Bp - } -} -#[doc = "Field `PIN_5_BPEN` writer - LCD Pin 5 Back Plane Enable"] -pub type Pin5BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin5Bpen>; -impl<'a, REG> Pin5BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin5Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin5Bpen::Bp) - } -} -#[doc = "LCD Pin 6 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin6Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin6Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_6_BPEN` reader - LCD Pin 6 Back Plane Enable"] -pub type Pin6BpenR = crate::BitReader; -impl Pin6BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin6Bpen { - match self.bits { - false => Pin6Bpen::Fp, - true => Pin6Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin6Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin6Bpen::Bp - } -} -#[doc = "Field `PIN_6_BPEN` writer - LCD Pin 6 Back Plane Enable"] -pub type Pin6BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin6Bpen>; -impl<'a, REG> Pin6BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin6Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin6Bpen::Bp) - } -} -#[doc = "LCD Pin 7 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin7Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin7Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_7_BPEN` reader - LCD Pin 7 Back Plane Enable"] -pub type Pin7BpenR = crate::BitReader; -impl Pin7BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin7Bpen { - match self.bits { - false => Pin7Bpen::Fp, - true => Pin7Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin7Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin7Bpen::Bp - } -} -#[doc = "Field `PIN_7_BPEN` writer - LCD Pin 7 Back Plane Enable"] -pub type Pin7BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin7Bpen>; -impl<'a, REG> Pin7BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin7Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin7Bpen::Bp) - } -} -#[doc = "LCD Pin 8 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin8Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin8Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_8_BPEN` reader - LCD Pin 8 Back Plane Enable"] -pub type Pin8BpenR = crate::BitReader; -impl Pin8BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin8Bpen { - match self.bits { - false => Pin8Bpen::Fp, - true => Pin8Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin8Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin8Bpen::Bp - } -} -#[doc = "Field `PIN_8_BPEN` writer - LCD Pin 8 Back Plane Enable"] -pub type Pin8BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin8Bpen>; -impl<'a, REG> Pin8BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin8Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin8Bpen::Bp) - } -} -#[doc = "LCD Pin 9 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin9Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin9Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_9_BPEN` reader - LCD Pin 9 Back Plane Enable"] -pub type Pin9BpenR = crate::BitReader; -impl Pin9BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin9Bpen { - match self.bits { - false => Pin9Bpen::Fp, - true => Pin9Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin9Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin9Bpen::Bp - } -} -#[doc = "Field `PIN_9_BPEN` writer - LCD Pin 9 Back Plane Enable"] -pub type Pin9BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin9Bpen>; -impl<'a, REG> Pin9BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin9Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin9Bpen::Bp) - } -} -#[doc = "LCD Pin 10 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin10Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin10Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_10_BPEN` reader - LCD Pin 10 Back Plane Enable"] -pub type Pin10BpenR = crate::BitReader; -impl Pin10BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin10Bpen { - match self.bits { - false => Pin10Bpen::Fp, - true => Pin10Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin10Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin10Bpen::Bp - } -} -#[doc = "Field `PIN_10_BPEN` writer - LCD Pin 10 Back Plane Enable"] -pub type Pin10BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin10Bpen>; -impl<'a, REG> Pin10BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin10Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin10Bpen::Bp) - } -} -#[doc = "LCD Pin 11 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin11Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin11Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_11_BPEN` reader - LCD Pin 11 Back Plane Enable"] -pub type Pin11BpenR = crate::BitReader; -impl Pin11BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin11Bpen { - match self.bits { - false => Pin11Bpen::Fp, - true => Pin11Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin11Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin11Bpen::Bp - } -} -#[doc = "Field `PIN_11_BPEN` writer - LCD Pin 11 Back Plane Enable"] -pub type Pin11BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin11Bpen>; -impl<'a, REG> Pin11BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin11Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin11Bpen::Bp) - } -} -#[doc = "LCD Pin 12 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin12Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin12Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_12_BPEN` reader - LCD Pin 12 Back Plane Enable"] -pub type Pin12BpenR = crate::BitReader; -impl Pin12BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin12Bpen { - match self.bits { - false => Pin12Bpen::Fp, - true => Pin12Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin12Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin12Bpen::Bp - } -} -#[doc = "Field `PIN_12_BPEN` writer - LCD Pin 12 Back Plane Enable"] -pub type Pin12BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin12Bpen>; -impl<'a, REG> Pin12BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin12Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin12Bpen::Bp) - } -} -#[doc = "LCD Pin 13 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin13Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin13Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_13_BPEN` reader - LCD Pin 13 Back Plane Enable"] -pub type Pin13BpenR = crate::BitReader; -impl Pin13BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin13Bpen { - match self.bits { - false => Pin13Bpen::Fp, - true => Pin13Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin13Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin13Bpen::Bp - } -} -#[doc = "Field `PIN_13_BPEN` writer - LCD Pin 13 Back Plane Enable"] -pub type Pin13BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin13Bpen>; -impl<'a, REG> Pin13BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin13Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin13Bpen::Bp) - } -} -#[doc = "LCD Pin 14 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin14Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin14Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_14_BPEN` reader - LCD Pin 14 Back Plane Enable"] -pub type Pin14BpenR = crate::BitReader; -impl Pin14BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin14Bpen { - match self.bits { - false => Pin14Bpen::Fp, - true => Pin14Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin14Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin14Bpen::Bp - } -} -#[doc = "Field `PIN_14_BPEN` writer - LCD Pin 14 Back Plane Enable"] -pub type Pin14BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin14Bpen>; -impl<'a, REG> Pin14BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin14Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin14Bpen::Bp) - } -} -#[doc = "LCD Pin 15 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin15Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin15Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_15_BPEN` reader - LCD Pin 15 Back Plane Enable"] -pub type Pin15BpenR = crate::BitReader; -impl Pin15BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin15Bpen { - match self.bits { - false => Pin15Bpen::Fp, - true => Pin15Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin15Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin15Bpen::Bp - } -} -#[doc = "Field `PIN_15_BPEN` writer - LCD Pin 15 Back Plane Enable"] -pub type Pin15BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin15Bpen>; -impl<'a, REG> Pin15BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin15Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin15Bpen::Bp) - } -} -#[doc = "LCD Pin 16 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin16Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin16Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_16_BPEN` reader - LCD Pin 16 Back Plane Enable"] -pub type Pin16BpenR = crate::BitReader; -impl Pin16BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin16Bpen { - match self.bits { - false => Pin16Bpen::Fp, - true => Pin16Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin16Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin16Bpen::Bp - } -} -#[doc = "Field `PIN_16_BPEN` writer - LCD Pin 16 Back Plane Enable"] -pub type Pin16BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin16Bpen>; -impl<'a, REG> Pin16BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin16Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin16Bpen::Bp) - } -} -#[doc = "LCD Pin 17 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin17Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin17Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_17_BPEN` reader - LCD Pin 17 Back Plane Enable"] -pub type Pin17BpenR = crate::BitReader; -impl Pin17BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin17Bpen { - match self.bits { - false => Pin17Bpen::Fp, - true => Pin17Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin17Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin17Bpen::Bp - } -} -#[doc = "Field `PIN_17_BPEN` writer - LCD Pin 17 Back Plane Enable"] -pub type Pin17BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin17Bpen>; -impl<'a, REG> Pin17BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin17Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin17Bpen::Bp) - } -} -#[doc = "LCD Pin 18 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin18Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin18Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_18_BPEN` reader - LCD Pin 18 Back Plane Enable"] -pub type Pin18BpenR = crate::BitReader; -impl Pin18BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin18Bpen { - match self.bits { - false => Pin18Bpen::Fp, - true => Pin18Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin18Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin18Bpen::Bp - } -} -#[doc = "Field `PIN_18_BPEN` writer - LCD Pin 18 Back Plane Enable"] -pub type Pin18BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin18Bpen>; -impl<'a, REG> Pin18BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin18Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin18Bpen::Bp) - } -} -#[doc = "LCD Pin 19 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin19Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin19Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_19_BPEN` reader - LCD Pin 19 Back Plane Enable"] -pub type Pin19BpenR = crate::BitReader; -impl Pin19BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin19Bpen { - match self.bits { - false => Pin19Bpen::Fp, - true => Pin19Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin19Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin19Bpen::Bp - } -} -#[doc = "Field `PIN_19_BPEN` writer - LCD Pin 19 Back Plane Enable"] -pub type Pin19BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin19Bpen>; -impl<'a, REG> Pin19BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin19Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin19Bpen::Bp) - } -} -#[doc = "LCD Pin 20 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin20Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin20Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_20_BPEN` reader - LCD Pin 20 Back Plane Enable"] -pub type Pin20BpenR = crate::BitReader; -impl Pin20BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin20Bpen { - match self.bits { - false => Pin20Bpen::Fp, - true => Pin20Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin20Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin20Bpen::Bp - } -} -#[doc = "Field `PIN_20_BPEN` writer - LCD Pin 20 Back Plane Enable"] -pub type Pin20BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin20Bpen>; -impl<'a, REG> Pin20BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin20Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin20Bpen::Bp) - } -} -#[doc = "LCD Pin 21 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin21Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin21Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_21_BPEN` reader - LCD Pin 21 Back Plane Enable"] -pub type Pin21BpenR = crate::BitReader; -impl Pin21BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin21Bpen { - match self.bits { - false => Pin21Bpen::Fp, - true => Pin21Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin21Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin21Bpen::Bp - } -} -#[doc = "Field `PIN_21_BPEN` writer - LCD Pin 21 Back Plane Enable"] -pub type Pin21BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin21Bpen>; -impl<'a, REG> Pin21BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin21Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin21Bpen::Bp) - } -} -#[doc = "LCD Pin 22 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin22Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin22Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_22_BPEN` reader - LCD Pin 22 Back Plane Enable"] -pub type Pin22BpenR = crate::BitReader; -impl Pin22BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin22Bpen { - match self.bits { - false => Pin22Bpen::Fp, - true => Pin22Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin22Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin22Bpen::Bp - } -} -#[doc = "Field `PIN_22_BPEN` writer - LCD Pin 22 Back Plane Enable"] -pub type Pin22BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin22Bpen>; -impl<'a, REG> Pin22BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin22Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin22Bpen::Bp) - } -} -#[doc = "LCD Pin 23 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin23Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin23Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_23_BPEN` reader - LCD Pin 23 Back Plane Enable"] -pub type Pin23BpenR = crate::BitReader; -impl Pin23BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin23Bpen { - match self.bits { - false => Pin23Bpen::Fp, - true => Pin23Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin23Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin23Bpen::Bp - } -} -#[doc = "Field `PIN_23_BPEN` writer - LCD Pin 23 Back Plane Enable"] -pub type Pin23BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin23Bpen>; -impl<'a, REG> Pin23BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin23Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin23Bpen::Bp) - } -} -#[doc = "LCD Pin 24 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin24Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin24Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_24_BPEN` reader - LCD Pin 24 Back Plane Enable"] -pub type Pin24BpenR = crate::BitReader; -impl Pin24BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin24Bpen { - match self.bits { - false => Pin24Bpen::Fp, - true => Pin24Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin24Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin24Bpen::Bp - } -} -#[doc = "Field `PIN_24_BPEN` writer - LCD Pin 24 Back Plane Enable"] -pub type Pin24BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin24Bpen>; -impl<'a, REG> Pin24BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin24Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin24Bpen::Bp) - } -} -#[doc = "LCD Pin 25 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin25Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin25Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_25_BPEN` reader - LCD Pin 25 Back Plane Enable"] -pub type Pin25BpenR = crate::BitReader; -impl Pin25BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin25Bpen { - match self.bits { - false => Pin25Bpen::Fp, - true => Pin25Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin25Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin25Bpen::Bp - } -} -#[doc = "Field `PIN_25_BPEN` writer - LCD Pin 25 Back Plane Enable"] -pub type Pin25BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin25Bpen>; -impl<'a, REG> Pin25BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin25Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin25Bpen::Bp) - } -} -#[doc = "LCD Pin 26 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin26Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin26Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_26_BPEN` reader - LCD Pin 26 Back Plane Enable"] -pub type Pin26BpenR = crate::BitReader; -impl Pin26BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin26Bpen { - match self.bits { - false => Pin26Bpen::Fp, - true => Pin26Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin26Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin26Bpen::Bp - } -} -#[doc = "Field `PIN_26_BPEN` writer - LCD Pin 26 Back Plane Enable"] -pub type Pin26BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin26Bpen>; -impl<'a, REG> Pin26BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin26Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin26Bpen::Bp) - } -} -#[doc = "LCD Pin 27 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin27Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin27Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_27_BPEN` reader - LCD Pin 27 Back Plane Enable"] -pub type Pin27BpenR = crate::BitReader; -impl Pin27BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin27Bpen { - match self.bits { - false => Pin27Bpen::Fp, - true => Pin27Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin27Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin27Bpen::Bp - } -} -#[doc = "Field `PIN_27_BPEN` writer - LCD Pin 27 Back Plane Enable"] -pub type Pin27BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin27Bpen>; -impl<'a, REG> Pin27BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin27Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin27Bpen::Bp) - } -} -#[doc = "LCD Pin 28 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin28Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin28Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_28_BPEN` reader - LCD Pin 28 Back Plane Enable"] -pub type Pin28BpenR = crate::BitReader; -impl Pin28BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin28Bpen { - match self.bits { - false => Pin28Bpen::Fp, - true => Pin28Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin28Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin28Bpen::Bp - } -} -#[doc = "Field `PIN_28_BPEN` writer - LCD Pin 28 Back Plane Enable"] -pub type Pin28BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin28Bpen>; -impl<'a, REG> Pin28BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin28Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin28Bpen::Bp) - } -} -#[doc = "LCD Pin 29 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin29Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin29Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_29_BPEN` reader - LCD Pin 29 Back Plane Enable"] -pub type Pin29BpenR = crate::BitReader; -impl Pin29BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin29Bpen { - match self.bits { - false => Pin29Bpen::Fp, - true => Pin29Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin29Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin29Bpen::Bp - } -} -#[doc = "Field `PIN_29_BPEN` writer - LCD Pin 29 Back Plane Enable"] -pub type Pin29BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin29Bpen>; -impl<'a, REG> Pin29BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin29Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin29Bpen::Bp) - } -} -#[doc = "LCD Pin 30 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin30Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin30Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_30_BPEN` reader - LCD Pin 30 Back Plane Enable"] -pub type Pin30BpenR = crate::BitReader; -impl Pin30BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin30Bpen { - match self.bits { - false => Pin30Bpen::Fp, - true => Pin30Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin30Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin30Bpen::Bp - } -} -#[doc = "Field `PIN_30_BPEN` writer - LCD Pin 30 Back Plane Enable"] -pub type Pin30BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin30Bpen>; -impl<'a, REG> Pin30BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin30Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin30Bpen::Bp) - } -} -#[doc = "LCD Pin 31 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin31Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin31Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_31_BPEN` reader - LCD Pin 31 Back Plane Enable"] -pub type Pin31BpenR = crate::BitReader; -impl Pin31BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin31Bpen { - match self.bits { - false => Pin31Bpen::Fp, - true => Pin31Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin31Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin31Bpen::Bp - } -} -#[doc = "Field `PIN_31_BPEN` writer - LCD Pin 31 Back Plane Enable"] -pub type Pin31BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin31Bpen>; -impl<'a, REG> Pin31BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin31Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin31Bpen::Bp) - } -} -impl R { - #[doc = "Bit 0 - LCD Pin 0 Back Plane Enable"] - #[inline(always)] - pub fn pin_0_bpen(&self) -> Pin0BpenR { - Pin0BpenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - LCD Pin 1 Back Plane Enable"] - #[inline(always)] - pub fn pin_1_bpen(&self) -> Pin1BpenR { - Pin1BpenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - LCD Pin 2 Back Plane Enable"] - #[inline(always)] - pub fn pin_2_bpen(&self) -> Pin2BpenR { - Pin2BpenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - LCD Pin 3 Back Plane Enable"] - #[inline(always)] - pub fn pin_3_bpen(&self) -> Pin3BpenR { - Pin3BpenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - LCD Pin 4 Back Plane Enable"] - #[inline(always)] - pub fn pin_4_bpen(&self) -> Pin4BpenR { - Pin4BpenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - LCD Pin 5 Back Plane Enable"] - #[inline(always)] - pub fn pin_5_bpen(&self) -> Pin5BpenR { - Pin5BpenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - LCD Pin 6 Back Plane Enable"] - #[inline(always)] - pub fn pin_6_bpen(&self) -> Pin6BpenR { - Pin6BpenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - LCD Pin 7 Back Plane Enable"] - #[inline(always)] - pub fn pin_7_bpen(&self) -> Pin7BpenR { - Pin7BpenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - LCD Pin 8 Back Plane Enable"] - #[inline(always)] - pub fn pin_8_bpen(&self) -> Pin8BpenR { - Pin8BpenR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - LCD Pin 9 Back Plane Enable"] - #[inline(always)] - pub fn pin_9_bpen(&self) -> Pin9BpenR { - Pin9BpenR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - LCD Pin 10 Back Plane Enable"] - #[inline(always)] - pub fn pin_10_bpen(&self) -> Pin10BpenR { - Pin10BpenR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - LCD Pin 11 Back Plane Enable"] - #[inline(always)] - pub fn pin_11_bpen(&self) -> Pin11BpenR { - Pin11BpenR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - LCD Pin 12 Back Plane Enable"] - #[inline(always)] - pub fn pin_12_bpen(&self) -> Pin12BpenR { - Pin12BpenR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - LCD Pin 13 Back Plane Enable"] - #[inline(always)] - pub fn pin_13_bpen(&self) -> Pin13BpenR { - Pin13BpenR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - LCD Pin 14 Back Plane Enable"] - #[inline(always)] - pub fn pin_14_bpen(&self) -> Pin14BpenR { - Pin14BpenR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - LCD Pin 15 Back Plane Enable"] - #[inline(always)] - pub fn pin_15_bpen(&self) -> Pin15BpenR { - Pin15BpenR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - LCD Pin 16 Back Plane Enable"] - #[inline(always)] - pub fn pin_16_bpen(&self) -> Pin16BpenR { - Pin16BpenR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - LCD Pin 17 Back Plane Enable"] - #[inline(always)] - pub fn pin_17_bpen(&self) -> Pin17BpenR { - Pin17BpenR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - LCD Pin 18 Back Plane Enable"] - #[inline(always)] - pub fn pin_18_bpen(&self) -> Pin18BpenR { - Pin18BpenR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - LCD Pin 19 Back Plane Enable"] - #[inline(always)] - pub fn pin_19_bpen(&self) -> Pin19BpenR { - Pin19BpenR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LCD Pin 20 Back Plane Enable"] - #[inline(always)] - pub fn pin_20_bpen(&self) -> Pin20BpenR { - Pin20BpenR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LCD Pin 21 Back Plane Enable"] - #[inline(always)] - pub fn pin_21_bpen(&self) -> Pin21BpenR { - Pin21BpenR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LCD Pin 22 Back Plane Enable"] - #[inline(always)] - pub fn pin_22_bpen(&self) -> Pin22BpenR { - Pin22BpenR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - LCD Pin 23 Back Plane Enable"] - #[inline(always)] - pub fn pin_23_bpen(&self) -> Pin23BpenR { - Pin23BpenR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - LCD Pin 24 Back Plane Enable"] - #[inline(always)] - pub fn pin_24_bpen(&self) -> Pin24BpenR { - Pin24BpenR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - LCD Pin 25 Back Plane Enable"] - #[inline(always)] - pub fn pin_25_bpen(&self) -> Pin25BpenR { - Pin25BpenR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - LCD Pin 26 Back Plane Enable"] - #[inline(always)] - pub fn pin_26_bpen(&self) -> Pin26BpenR { - Pin26BpenR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - LCD Pin 27 Back Plane Enable"] - #[inline(always)] - pub fn pin_27_bpen(&self) -> Pin27BpenR { - Pin27BpenR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - LCD Pin 28 Back Plane Enable"] - #[inline(always)] - pub fn pin_28_bpen(&self) -> Pin28BpenR { - Pin28BpenR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - LCD Pin 29 Back Plane Enable"] - #[inline(always)] - pub fn pin_29_bpen(&self) -> Pin29BpenR { - Pin29BpenR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - LCD Pin 30 Back Plane Enable"] - #[inline(always)] - pub fn pin_30_bpen(&self) -> Pin30BpenR { - Pin30BpenR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - LCD Pin 31 Back Plane Enable"] - #[inline(always)] - pub fn pin_31_bpen(&self) -> Pin31BpenR { - Pin31BpenR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LCD Pin 0 Back Plane Enable"] - #[inline(always)] - pub fn pin_0_bpen(&mut self) -> Pin0BpenW { - Pin0BpenW::new(self, 0) - } - #[doc = "Bit 1 - LCD Pin 1 Back Plane Enable"] - #[inline(always)] - pub fn pin_1_bpen(&mut self) -> Pin1BpenW { - Pin1BpenW::new(self, 1) - } - #[doc = "Bit 2 - LCD Pin 2 Back Plane Enable"] - #[inline(always)] - pub fn pin_2_bpen(&mut self) -> Pin2BpenW { - Pin2BpenW::new(self, 2) - } - #[doc = "Bit 3 - LCD Pin 3 Back Plane Enable"] - #[inline(always)] - pub fn pin_3_bpen(&mut self) -> Pin3BpenW { - Pin3BpenW::new(self, 3) - } - #[doc = "Bit 4 - LCD Pin 4 Back Plane Enable"] - #[inline(always)] - pub fn pin_4_bpen(&mut self) -> Pin4BpenW { - Pin4BpenW::new(self, 4) - } - #[doc = "Bit 5 - LCD Pin 5 Back Plane Enable"] - #[inline(always)] - pub fn pin_5_bpen(&mut self) -> Pin5BpenW { - Pin5BpenW::new(self, 5) - } - #[doc = "Bit 6 - LCD Pin 6 Back Plane Enable"] - #[inline(always)] - pub fn pin_6_bpen(&mut self) -> Pin6BpenW { - Pin6BpenW::new(self, 6) - } - #[doc = "Bit 7 - LCD Pin 7 Back Plane Enable"] - #[inline(always)] - pub fn pin_7_bpen(&mut self) -> Pin7BpenW { - Pin7BpenW::new(self, 7) - } - #[doc = "Bit 8 - LCD Pin 8 Back Plane Enable"] - #[inline(always)] - pub fn pin_8_bpen(&mut self) -> Pin8BpenW { - Pin8BpenW::new(self, 8) - } - #[doc = "Bit 9 - LCD Pin 9 Back Plane Enable"] - #[inline(always)] - pub fn pin_9_bpen(&mut self) -> Pin9BpenW { - Pin9BpenW::new(self, 9) - } - #[doc = "Bit 10 - LCD Pin 10 Back Plane Enable"] - #[inline(always)] - pub fn pin_10_bpen(&mut self) -> Pin10BpenW { - Pin10BpenW::new(self, 10) - } - #[doc = "Bit 11 - LCD Pin 11 Back Plane Enable"] - #[inline(always)] - pub fn pin_11_bpen(&mut self) -> Pin11BpenW { - Pin11BpenW::new(self, 11) - } - #[doc = "Bit 12 - LCD Pin 12 Back Plane Enable"] - #[inline(always)] - pub fn pin_12_bpen(&mut self) -> Pin12BpenW { - Pin12BpenW::new(self, 12) - } - #[doc = "Bit 13 - LCD Pin 13 Back Plane Enable"] - #[inline(always)] - pub fn pin_13_bpen(&mut self) -> Pin13BpenW { - Pin13BpenW::new(self, 13) - } - #[doc = "Bit 14 - LCD Pin 14 Back Plane Enable"] - #[inline(always)] - pub fn pin_14_bpen(&mut self) -> Pin14BpenW { - Pin14BpenW::new(self, 14) - } - #[doc = "Bit 15 - LCD Pin 15 Back Plane Enable"] - #[inline(always)] - pub fn pin_15_bpen(&mut self) -> Pin15BpenW { - Pin15BpenW::new(self, 15) - } - #[doc = "Bit 16 - LCD Pin 16 Back Plane Enable"] - #[inline(always)] - pub fn pin_16_bpen(&mut self) -> Pin16BpenW { - Pin16BpenW::new(self, 16) - } - #[doc = "Bit 17 - LCD Pin 17 Back Plane Enable"] - #[inline(always)] - pub fn pin_17_bpen(&mut self) -> Pin17BpenW { - Pin17BpenW::new(self, 17) - } - #[doc = "Bit 18 - LCD Pin 18 Back Plane Enable"] - #[inline(always)] - pub fn pin_18_bpen(&mut self) -> Pin18BpenW { - Pin18BpenW::new(self, 18) - } - #[doc = "Bit 19 - LCD Pin 19 Back Plane Enable"] - #[inline(always)] - pub fn pin_19_bpen(&mut self) -> Pin19BpenW { - Pin19BpenW::new(self, 19) - } - #[doc = "Bit 20 - LCD Pin 20 Back Plane Enable"] - #[inline(always)] - pub fn pin_20_bpen(&mut self) -> Pin20BpenW { - Pin20BpenW::new(self, 20) - } - #[doc = "Bit 21 - LCD Pin 21 Back Plane Enable"] - #[inline(always)] - pub fn pin_21_bpen(&mut self) -> Pin21BpenW { - Pin21BpenW::new(self, 21) - } - #[doc = "Bit 22 - LCD Pin 22 Back Plane Enable"] - #[inline(always)] - pub fn pin_22_bpen(&mut self) -> Pin22BpenW { - Pin22BpenW::new(self, 22) - } - #[doc = "Bit 23 - LCD Pin 23 Back Plane Enable"] - #[inline(always)] - pub fn pin_23_bpen(&mut self) -> Pin23BpenW { - Pin23BpenW::new(self, 23) - } - #[doc = "Bit 24 - LCD Pin 24 Back Plane Enable"] - #[inline(always)] - pub fn pin_24_bpen(&mut self) -> Pin24BpenW { - Pin24BpenW::new(self, 24) - } - #[doc = "Bit 25 - LCD Pin 25 Back Plane Enable"] - #[inline(always)] - pub fn pin_25_bpen(&mut self) -> Pin25BpenW { - Pin25BpenW::new(self, 25) - } - #[doc = "Bit 26 - LCD Pin 26 Back Plane Enable"] - #[inline(always)] - pub fn pin_26_bpen(&mut self) -> Pin26BpenW { - Pin26BpenW::new(self, 26) - } - #[doc = "Bit 27 - LCD Pin 27 Back Plane Enable"] - #[inline(always)] - pub fn pin_27_bpen(&mut self) -> Pin27BpenW { - Pin27BpenW::new(self, 27) - } - #[doc = "Bit 28 - LCD Pin 28 Back Plane Enable"] - #[inline(always)] - pub fn pin_28_bpen(&mut self) -> Pin28BpenW { - Pin28BpenW::new(self, 28) - } - #[doc = "Bit 29 - LCD Pin 29 Back Plane Enable"] - #[inline(always)] - pub fn pin_29_bpen(&mut self) -> Pin29BpenW { - Pin29BpenW::new(self, 29) - } - #[doc = "Bit 30 - LCD Pin 30 Back Plane Enable"] - #[inline(always)] - pub fn pin_30_bpen(&mut self) -> Pin30BpenW { - Pin30BpenW::new(self, 30) - } - #[doc = "Bit 31 - LCD Pin 31 Back Plane Enable"] - #[inline(always)] - pub fn pin_31_bpen(&mut self) -> Pin31BpenW { - Pin31BpenW::new(self, 31) - } -} -#[doc = "LCD Back Plane Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdBpen0Spec; -impl crate::RegisterSpec for LcdBpen0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_bpen0::R`](R) reader structure"] -impl crate::Readable for LcdBpen0Spec {} -#[doc = "`write(|w| ..)` method takes [`lcd_bpen0::W`](W) writer structure"] -impl crate::Writable for LcdBpen0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCD_BPEN0 to value 0"] -impl crate::Resettable for LcdBpen0Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_bpen1.rs b/mcxa276-pac/src/slcd0/lcd_bpen1.rs deleted file mode 100644 index acc24293f..000000000 --- a/mcxa276-pac/src/slcd0/lcd_bpen1.rs +++ /dev/null @@ -1,1029 +0,0 @@ -#[doc = "Register `LCD_BPEN1` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_BPEN1` writer"] -pub type W = crate::W; -#[doc = "LCD Pin 32 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin32Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin32Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_32_BPEN` reader - LCD Pin 32 Back Plane Enable"] -pub type Pin32BpenR = crate::BitReader; -impl Pin32BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin32Bpen { - match self.bits { - false => Pin32Bpen::Fp, - true => Pin32Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin32Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin32Bpen::Bp - } -} -#[doc = "Field `PIN_32_BPEN` writer - LCD Pin 32 Back Plane Enable"] -pub type Pin32BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin32Bpen>; -impl<'a, REG> Pin32BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin32Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin32Bpen::Bp) - } -} -#[doc = "LCD Pin 33 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin33Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin33Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_33_BPEN` reader - LCD Pin 33 Back Plane Enable"] -pub type Pin33BpenR = crate::BitReader; -impl Pin33BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin33Bpen { - match self.bits { - false => Pin33Bpen::Fp, - true => Pin33Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin33Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin33Bpen::Bp - } -} -#[doc = "Field `PIN_33_BPEN` writer - LCD Pin 33 Back Plane Enable"] -pub type Pin33BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin33Bpen>; -impl<'a, REG> Pin33BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin33Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin33Bpen::Bp) - } -} -#[doc = "LCD Pin 34 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin34Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin34Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_34_BPEN` reader - LCD Pin 34 Back Plane Enable"] -pub type Pin34BpenR = crate::BitReader; -impl Pin34BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin34Bpen { - match self.bits { - false => Pin34Bpen::Fp, - true => Pin34Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin34Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin34Bpen::Bp - } -} -#[doc = "Field `PIN_34_BPEN` writer - LCD Pin 34 Back Plane Enable"] -pub type Pin34BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin34Bpen>; -impl<'a, REG> Pin34BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin34Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin34Bpen::Bp) - } -} -#[doc = "LCD Pin 35 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin35Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin35Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_35_BPEN` reader - LCD Pin 35 Back Plane Enable"] -pub type Pin35BpenR = crate::BitReader; -impl Pin35BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin35Bpen { - match self.bits { - false => Pin35Bpen::Fp, - true => Pin35Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin35Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin35Bpen::Bp - } -} -#[doc = "Field `PIN_35_BPEN` writer - LCD Pin 35 Back Plane Enable"] -pub type Pin35BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin35Bpen>; -impl<'a, REG> Pin35BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin35Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin35Bpen::Bp) - } -} -#[doc = "LCD Pin 36 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin36Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin36Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_36_BPEN` reader - LCD Pin 36 Back Plane Enable"] -pub type Pin36BpenR = crate::BitReader; -impl Pin36BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin36Bpen { - match self.bits { - false => Pin36Bpen::Fp, - true => Pin36Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin36Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin36Bpen::Bp - } -} -#[doc = "Field `PIN_36_BPEN` writer - LCD Pin 36 Back Plane Enable"] -pub type Pin36BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin36Bpen>; -impl<'a, REG> Pin36BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin36Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin36Bpen::Bp) - } -} -#[doc = "LCD Pin 37 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin37Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin37Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_37_BPEN` reader - LCD Pin 37 Back Plane Enable"] -pub type Pin37BpenR = crate::BitReader; -impl Pin37BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin37Bpen { - match self.bits { - false => Pin37Bpen::Fp, - true => Pin37Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin37Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin37Bpen::Bp - } -} -#[doc = "Field `PIN_37_BPEN` writer - LCD Pin 37 Back Plane Enable"] -pub type Pin37BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin37Bpen>; -impl<'a, REG> Pin37BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin37Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin37Bpen::Bp) - } -} -#[doc = "LCD Pin 38 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin38Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin38Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_38_BPEN` reader - LCD Pin 38 Back Plane Enable"] -pub type Pin38BpenR = crate::BitReader; -impl Pin38BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin38Bpen { - match self.bits { - false => Pin38Bpen::Fp, - true => Pin38Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin38Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin38Bpen::Bp - } -} -#[doc = "Field `PIN_38_BPEN` writer - LCD Pin 38 Back Plane Enable"] -pub type Pin38BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin38Bpen>; -impl<'a, REG> Pin38BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin38Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin38Bpen::Bp) - } -} -#[doc = "LCD Pin 39 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin39Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin39Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_39_BPEN` reader - LCD Pin 39 Back Plane Enable"] -pub type Pin39BpenR = crate::BitReader; -impl Pin39BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin39Bpen { - match self.bits { - false => Pin39Bpen::Fp, - true => Pin39Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin39Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin39Bpen::Bp - } -} -#[doc = "Field `PIN_39_BPEN` writer - LCD Pin 39 Back Plane Enable"] -pub type Pin39BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin39Bpen>; -impl<'a, REG> Pin39BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin39Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin39Bpen::Bp) - } -} -#[doc = "LCD Pin 40 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin40Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin40Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_40_BPEN` reader - LCD Pin 40 Back Plane Enable"] -pub type Pin40BpenR = crate::BitReader; -impl Pin40BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin40Bpen { - match self.bits { - false => Pin40Bpen::Fp, - true => Pin40Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin40Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin40Bpen::Bp - } -} -#[doc = "Field `PIN_40_BPEN` writer - LCD Pin 40 Back Plane Enable"] -pub type Pin40BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin40Bpen>; -impl<'a, REG> Pin40BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin40Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin40Bpen::Bp) - } -} -#[doc = "LCD Pin 41 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin41Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin41Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_41_BPEN` reader - LCD Pin 41 Back Plane Enable"] -pub type Pin41BpenR = crate::BitReader; -impl Pin41BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin41Bpen { - match self.bits { - false => Pin41Bpen::Fp, - true => Pin41Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin41Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin41Bpen::Bp - } -} -#[doc = "Field `PIN_41_BPEN` writer - LCD Pin 41 Back Plane Enable"] -pub type Pin41BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin41Bpen>; -impl<'a, REG> Pin41BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin41Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin41Bpen::Bp) - } -} -#[doc = "LCD Pin 42 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin42Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin42Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_42_BPEN` reader - LCD Pin 42 Back Plane Enable"] -pub type Pin42BpenR = crate::BitReader; -impl Pin42BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin42Bpen { - match self.bits { - false => Pin42Bpen::Fp, - true => Pin42Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin42Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin42Bpen::Bp - } -} -#[doc = "Field `PIN_42_BPEN` writer - LCD Pin 42 Back Plane Enable"] -pub type Pin42BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin42Bpen>; -impl<'a, REG> Pin42BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin42Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin42Bpen::Bp) - } -} -#[doc = "LCD Pin 43 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin43Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin43Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_43_BPEN` reader - LCD Pin 43 Back Plane Enable"] -pub type Pin43BpenR = crate::BitReader; -impl Pin43BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin43Bpen { - match self.bits { - false => Pin43Bpen::Fp, - true => Pin43Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin43Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin43Bpen::Bp - } -} -#[doc = "Field `PIN_43_BPEN` writer - LCD Pin 43 Back Plane Enable"] -pub type Pin43BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin43Bpen>; -impl<'a, REG> Pin43BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin43Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin43Bpen::Bp) - } -} -#[doc = "LCD Pin 44 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin44Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin44Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_44_BPEN` reader - LCD Pin 44 Back Plane Enable"] -pub type Pin44BpenR = crate::BitReader; -impl Pin44BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin44Bpen { - match self.bits { - false => Pin44Bpen::Fp, - true => Pin44Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin44Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin44Bpen::Bp - } -} -#[doc = "Field `PIN_44_BPEN` writer - LCD Pin 44 Back Plane Enable"] -pub type Pin44BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin44Bpen>; -impl<'a, REG> Pin44BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin44Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin44Bpen::Bp) - } -} -#[doc = "LCD Pin 45 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin45Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin45Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_45_BPEN` reader - LCD Pin 45 Back Plane Enable"] -pub type Pin45BpenR = crate::BitReader; -impl Pin45BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin45Bpen { - match self.bits { - false => Pin45Bpen::Fp, - true => Pin45Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin45Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin45Bpen::Bp - } -} -#[doc = "Field `PIN_45_BPEN` writer - LCD Pin 45 Back Plane Enable"] -pub type Pin45BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin45Bpen>; -impl<'a, REG> Pin45BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin45Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin45Bpen::Bp) - } -} -#[doc = "LCD Pin 46 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin46Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin46Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_46_BPEN` reader - LCD Pin 46 Back Plane Enable"] -pub type Pin46BpenR = crate::BitReader; -impl Pin46BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin46Bpen { - match self.bits { - false => Pin46Bpen::Fp, - true => Pin46Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin46Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin46Bpen::Bp - } -} -#[doc = "Field `PIN_46_BPEN` writer - LCD Pin 46 Back Plane Enable"] -pub type Pin46BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin46Bpen>; -impl<'a, REG> Pin46BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin46Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin46Bpen::Bp) - } -} -#[doc = "LCD Pin 47 Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin47Bpen { - #[doc = "0: Pin as front plane."] - Fp = 0, - #[doc = "1: Pin as back plane."] - Bp = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin47Bpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_47_BPEN` reader - LCD Pin 47 Back Plane Enable"] -pub type Pin47BpenR = crate::BitReader; -impl Pin47BpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin47Bpen { - match self.bits { - false => Pin47Bpen::Fp, - true => Pin47Bpen::Bp, - } - } - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn is_fp(&self) -> bool { - *self == Pin47Bpen::Fp - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn is_bp(&self) -> bool { - *self == Pin47Bpen::Bp - } -} -#[doc = "Field `PIN_47_BPEN` writer - LCD Pin 47 Back Plane Enable"] -pub type Pin47BpenW<'a, REG> = crate::BitWriter<'a, REG, Pin47Bpen>; -impl<'a, REG> Pin47BpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin as front plane."] - #[inline(always)] - pub fn fp(self) -> &'a mut crate::W { - self.variant(Pin47Bpen::Fp) - } - #[doc = "Pin as back plane."] - #[inline(always)] - pub fn bp(self) -> &'a mut crate::W { - self.variant(Pin47Bpen::Bp) - } -} -impl R { - #[doc = "Bit 0 - LCD Pin 32 Back Plane Enable"] - #[inline(always)] - pub fn pin_32_bpen(&self) -> Pin32BpenR { - Pin32BpenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - LCD Pin 33 Back Plane Enable"] - #[inline(always)] - pub fn pin_33_bpen(&self) -> Pin33BpenR { - Pin33BpenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - LCD Pin 34 Back Plane Enable"] - #[inline(always)] - pub fn pin_34_bpen(&self) -> Pin34BpenR { - Pin34BpenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - LCD Pin 35 Back Plane Enable"] - #[inline(always)] - pub fn pin_35_bpen(&self) -> Pin35BpenR { - Pin35BpenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - LCD Pin 36 Back Plane Enable"] - #[inline(always)] - pub fn pin_36_bpen(&self) -> Pin36BpenR { - Pin36BpenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - LCD Pin 37 Back Plane Enable"] - #[inline(always)] - pub fn pin_37_bpen(&self) -> Pin37BpenR { - Pin37BpenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - LCD Pin 38 Back Plane Enable"] - #[inline(always)] - pub fn pin_38_bpen(&self) -> Pin38BpenR { - Pin38BpenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - LCD Pin 39 Back Plane Enable"] - #[inline(always)] - pub fn pin_39_bpen(&self) -> Pin39BpenR { - Pin39BpenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - LCD Pin 40 Back Plane Enable"] - #[inline(always)] - pub fn pin_40_bpen(&self) -> Pin40BpenR { - Pin40BpenR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - LCD Pin 41 Back Plane Enable"] - #[inline(always)] - pub fn pin_41_bpen(&self) -> Pin41BpenR { - Pin41BpenR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - LCD Pin 42 Back Plane Enable"] - #[inline(always)] - pub fn pin_42_bpen(&self) -> Pin42BpenR { - Pin42BpenR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - LCD Pin 43 Back Plane Enable"] - #[inline(always)] - pub fn pin_43_bpen(&self) -> Pin43BpenR { - Pin43BpenR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - LCD Pin 44 Back Plane Enable"] - #[inline(always)] - pub fn pin_44_bpen(&self) -> Pin44BpenR { - Pin44BpenR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - LCD Pin 45 Back Plane Enable"] - #[inline(always)] - pub fn pin_45_bpen(&self) -> Pin45BpenR { - Pin45BpenR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - LCD Pin 46 Back Plane Enable"] - #[inline(always)] - pub fn pin_46_bpen(&self) -> Pin46BpenR { - Pin46BpenR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - LCD Pin 47 Back Plane Enable"] - #[inline(always)] - pub fn pin_47_bpen(&self) -> Pin47BpenR { - Pin47BpenR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LCD Pin 32 Back Plane Enable"] - #[inline(always)] - pub fn pin_32_bpen(&mut self) -> Pin32BpenW { - Pin32BpenW::new(self, 0) - } - #[doc = "Bit 1 - LCD Pin 33 Back Plane Enable"] - #[inline(always)] - pub fn pin_33_bpen(&mut self) -> Pin33BpenW { - Pin33BpenW::new(self, 1) - } - #[doc = "Bit 2 - LCD Pin 34 Back Plane Enable"] - #[inline(always)] - pub fn pin_34_bpen(&mut self) -> Pin34BpenW { - Pin34BpenW::new(self, 2) - } - #[doc = "Bit 3 - LCD Pin 35 Back Plane Enable"] - #[inline(always)] - pub fn pin_35_bpen(&mut self) -> Pin35BpenW { - Pin35BpenW::new(self, 3) - } - #[doc = "Bit 4 - LCD Pin 36 Back Plane Enable"] - #[inline(always)] - pub fn pin_36_bpen(&mut self) -> Pin36BpenW { - Pin36BpenW::new(self, 4) - } - #[doc = "Bit 5 - LCD Pin 37 Back Plane Enable"] - #[inline(always)] - pub fn pin_37_bpen(&mut self) -> Pin37BpenW { - Pin37BpenW::new(self, 5) - } - #[doc = "Bit 6 - LCD Pin 38 Back Plane Enable"] - #[inline(always)] - pub fn pin_38_bpen(&mut self) -> Pin38BpenW { - Pin38BpenW::new(self, 6) - } - #[doc = "Bit 7 - LCD Pin 39 Back Plane Enable"] - #[inline(always)] - pub fn pin_39_bpen(&mut self) -> Pin39BpenW { - Pin39BpenW::new(self, 7) - } - #[doc = "Bit 8 - LCD Pin 40 Back Plane Enable"] - #[inline(always)] - pub fn pin_40_bpen(&mut self) -> Pin40BpenW { - Pin40BpenW::new(self, 8) - } - #[doc = "Bit 9 - LCD Pin 41 Back Plane Enable"] - #[inline(always)] - pub fn pin_41_bpen(&mut self) -> Pin41BpenW { - Pin41BpenW::new(self, 9) - } - #[doc = "Bit 10 - LCD Pin 42 Back Plane Enable"] - #[inline(always)] - pub fn pin_42_bpen(&mut self) -> Pin42BpenW { - Pin42BpenW::new(self, 10) - } - #[doc = "Bit 11 - LCD Pin 43 Back Plane Enable"] - #[inline(always)] - pub fn pin_43_bpen(&mut self) -> Pin43BpenW { - Pin43BpenW::new(self, 11) - } - #[doc = "Bit 12 - LCD Pin 44 Back Plane Enable"] - #[inline(always)] - pub fn pin_44_bpen(&mut self) -> Pin44BpenW { - Pin44BpenW::new(self, 12) - } - #[doc = "Bit 13 - LCD Pin 45 Back Plane Enable"] - #[inline(always)] - pub fn pin_45_bpen(&mut self) -> Pin45BpenW { - Pin45BpenW::new(self, 13) - } - #[doc = "Bit 14 - LCD Pin 46 Back Plane Enable"] - #[inline(always)] - pub fn pin_46_bpen(&mut self) -> Pin46BpenW { - Pin46BpenW::new(self, 14) - } - #[doc = "Bit 15 - LCD Pin 47 Back Plane Enable"] - #[inline(always)] - pub fn pin_47_bpen(&mut self) -> Pin47BpenW { - Pin47BpenW::new(self, 15) - } -} -#[doc = "LCD Back Plane Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_bpen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_bpen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdBpen1Spec; -impl crate::RegisterSpec for LcdBpen1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_bpen1::R`](R) reader structure"] -impl crate::Readable for LcdBpen1Spec {} -#[doc = "`write(|w| ..)` method takes [`lcd_bpen1::W`](W) writer structure"] -impl crate::Writable for LcdBpen1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCD_BPEN1 to value 0"] -impl crate::Resettable for LcdBpen1Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_fdcr.rs b/mcxa276-pac/src/slcd0/lcd_fdcr.rs deleted file mode 100644 index 7dcf5145c..000000000 --- a/mcxa276-pac/src/slcd0/lcd_fdcr.rs +++ /dev/null @@ -1,457 +0,0 @@ -#[doc = "Register `LCD_FDCR` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_FDCR` writer"] -pub type W = crate::W; -#[doc = "Field `FDPINID` reader - Fault Detect Pin ID"] -pub type FdpinidR = crate::FieldReader; -#[doc = "Field `FDPINID` writer - Fault Detect Pin ID"] -pub type FdpinidW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Fault Detect Back Plane Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fdbpen { - #[doc = "0: Type of the selected pin under fault detect test is front plane."] - Front = 0, - #[doc = "1: Type of the selected pin under fault detect test is back plane."] - Back = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fdbpen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FDBPEN` reader - Fault Detect Back Plane Enable"] -pub type FdbpenR = crate::BitReader; -impl FdbpenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fdbpen { - match self.bits { - false => Fdbpen::Front, - true => Fdbpen::Back, - } - } - #[doc = "Type of the selected pin under fault detect test is front plane."] - #[inline(always)] - pub fn is_front(&self) -> bool { - *self == Fdbpen::Front - } - #[doc = "Type of the selected pin under fault detect test is back plane."] - #[inline(always)] - pub fn is_back(&self) -> bool { - *self == Fdbpen::Back - } -} -#[doc = "Field `FDBPEN` writer - Fault Detect Back Plane Enable"] -pub type FdbpenW<'a, REG> = crate::BitWriter<'a, REG, Fdbpen>; -impl<'a, REG> FdbpenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Type of the selected pin under fault detect test is front plane."] - #[inline(always)] - pub fn front(self) -> &'a mut crate::W { - self.variant(Fdbpen::Front) - } - #[doc = "Type of the selected pin under fault detect test is back plane."] - #[inline(always)] - pub fn back(self) -> &'a mut crate::W { - self.variant(Fdbpen::Back) - } -} -#[doc = "Fault Detect Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fden { - #[doc = "0: Disable fault detection."] - Disable = 0, - #[doc = "1: Enable fault detection."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fden) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FDEN` reader - Fault Detect Enable"] -pub type FdenR = crate::BitReader; -impl FdenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fden { - match self.bits { - false => Fden::Disable, - true => Fden::Enable, - } - } - #[doc = "Disable fault detection."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Fden::Disable - } - #[doc = "Enable fault detection."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Fden::Enable - } -} -#[doc = "Field `FDEN` writer - Fault Detect Enable"] -pub type FdenW<'a, REG> = crate::BitWriter<'a, REG, Fden>; -impl<'a, REG> FdenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable fault detection."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Fden::Disable) - } - #[doc = "Enable fault detection."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Fden::Enable) - } -} -#[doc = "Fault Detect Sample Window Width\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fdsww { - #[doc = "0: Sample window width is 4 sample clock cycles."] - Sample4Cycles = 0, - #[doc = "1: Sample window width is 8 sample clock cycles."] - Sample8Cycles = 1, - #[doc = "2: Sample window width is 16 sample clock cycles."] - Sample16Cycles = 2, - #[doc = "3: Sample window width is 32 sample clock cycles."] - Sample32Cycles = 3, - #[doc = "4: Sample window width is 64 sample clock cycles."] - Sample64Cycles = 4, - #[doc = "5: Sample window width is 128 sample clock cycles."] - Sample128Cycles = 5, - #[doc = "6: Sample window width is 256 sample clock cycles."] - Sample256Cycles = 6, - #[doc = "7: Sample window width is 512 sample clock cycles."] - Sample512Cycles = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fdsww) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fdsww { - type Ux = u8; -} -impl crate::IsEnum for Fdsww {} -#[doc = "Field `FDSWW` reader - Fault Detect Sample Window Width"] -pub type FdswwR = crate::FieldReader; -impl FdswwR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fdsww { - match self.bits { - 0 => Fdsww::Sample4Cycles, - 1 => Fdsww::Sample8Cycles, - 2 => Fdsww::Sample16Cycles, - 3 => Fdsww::Sample32Cycles, - 4 => Fdsww::Sample64Cycles, - 5 => Fdsww::Sample128Cycles, - 6 => Fdsww::Sample256Cycles, - 7 => Fdsww::Sample512Cycles, - _ => unreachable!(), - } - } - #[doc = "Sample window width is 4 sample clock cycles."] - #[inline(always)] - pub fn is_sample_4_cycles(&self) -> bool { - *self == Fdsww::Sample4Cycles - } - #[doc = "Sample window width is 8 sample clock cycles."] - #[inline(always)] - pub fn is_sample_8_cycles(&self) -> bool { - *self == Fdsww::Sample8Cycles - } - #[doc = "Sample window width is 16 sample clock cycles."] - #[inline(always)] - pub fn is_sample_16_cycles(&self) -> bool { - *self == Fdsww::Sample16Cycles - } - #[doc = "Sample window width is 32 sample clock cycles."] - #[inline(always)] - pub fn is_sample_32_cycles(&self) -> bool { - *self == Fdsww::Sample32Cycles - } - #[doc = "Sample window width is 64 sample clock cycles."] - #[inline(always)] - pub fn is_sample_64_cycles(&self) -> bool { - *self == Fdsww::Sample64Cycles - } - #[doc = "Sample window width is 128 sample clock cycles."] - #[inline(always)] - pub fn is_sample_128_cycles(&self) -> bool { - *self == Fdsww::Sample128Cycles - } - #[doc = "Sample window width is 256 sample clock cycles."] - #[inline(always)] - pub fn is_sample_256_cycles(&self) -> bool { - *self == Fdsww::Sample256Cycles - } - #[doc = "Sample window width is 512 sample clock cycles."] - #[inline(always)] - pub fn is_sample_512_cycles(&self) -> bool { - *self == Fdsww::Sample512Cycles - } -} -#[doc = "Field `FDSWW` writer - Fault Detect Sample Window Width"] -pub type FdswwW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fdsww, crate::Safe>; -impl<'a, REG> FdswwW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Sample window width is 4 sample clock cycles."] - #[inline(always)] - pub fn sample_4_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample4Cycles) - } - #[doc = "Sample window width is 8 sample clock cycles."] - #[inline(always)] - pub fn sample_8_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample8Cycles) - } - #[doc = "Sample window width is 16 sample clock cycles."] - #[inline(always)] - pub fn sample_16_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample16Cycles) - } - #[doc = "Sample window width is 32 sample clock cycles."] - #[inline(always)] - pub fn sample_32_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample32Cycles) - } - #[doc = "Sample window width is 64 sample clock cycles."] - #[inline(always)] - pub fn sample_64_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample64Cycles) - } - #[doc = "Sample window width is 128 sample clock cycles."] - #[inline(always)] - pub fn sample_128_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample128Cycles) - } - #[doc = "Sample window width is 256 sample clock cycles."] - #[inline(always)] - pub fn sample_256_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample256Cycles) - } - #[doc = "Sample window width is 512 sample clock cycles."] - #[inline(always)] - pub fn sample_512_cycles(self) -> &'a mut crate::W { - self.variant(Fdsww::Sample512Cycles) - } -} -#[doc = "Fault Detect Clock Prescaler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Fdprs { - #[doc = "0: 1/1 bus clock."] - Div1Bus = 0, - #[doc = "1: 1/2 bus clock."] - Div2Bus = 1, - #[doc = "2: 1/4 bus clock."] - Div4Bus = 2, - #[doc = "3: 1/8 bus clock."] - Div8Bus = 3, - #[doc = "4: 1/16 bus clock."] - Div16Bus = 4, - #[doc = "5: 1/32 bus clock."] - Div32Bus = 5, - #[doc = "6: 1/64 bus clock."] - Div64Bus = 6, - #[doc = "7: 1/128 bus clock."] - Div128Bus = 7, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Fdprs) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Fdprs { - type Ux = u8; -} -impl crate::IsEnum for Fdprs {} -#[doc = "Field `FDPRS` reader - Fault Detect Clock Prescaler"] -pub type FdprsR = crate::FieldReader; -impl FdprsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fdprs { - match self.bits { - 0 => Fdprs::Div1Bus, - 1 => Fdprs::Div2Bus, - 2 => Fdprs::Div4Bus, - 3 => Fdprs::Div8Bus, - 4 => Fdprs::Div16Bus, - 5 => Fdprs::Div32Bus, - 6 => Fdprs::Div64Bus, - 7 => Fdprs::Div128Bus, - _ => unreachable!(), - } - } - #[doc = "1/1 bus clock."] - #[inline(always)] - pub fn is_div_1_bus(&self) -> bool { - *self == Fdprs::Div1Bus - } - #[doc = "1/2 bus clock."] - #[inline(always)] - pub fn is_div_2_bus(&self) -> bool { - *self == Fdprs::Div2Bus - } - #[doc = "1/4 bus clock."] - #[inline(always)] - pub fn is_div_4_bus(&self) -> bool { - *self == Fdprs::Div4Bus - } - #[doc = "1/8 bus clock."] - #[inline(always)] - pub fn is_div_8_bus(&self) -> bool { - *self == Fdprs::Div8Bus - } - #[doc = "1/16 bus clock."] - #[inline(always)] - pub fn is_div_16_bus(&self) -> bool { - *self == Fdprs::Div16Bus - } - #[doc = "1/32 bus clock."] - #[inline(always)] - pub fn is_div_32_bus(&self) -> bool { - *self == Fdprs::Div32Bus - } - #[doc = "1/64 bus clock."] - #[inline(always)] - pub fn is_div_64_bus(&self) -> bool { - *self == Fdprs::Div64Bus - } - #[doc = "1/128 bus clock."] - #[inline(always)] - pub fn is_div_128_bus(&self) -> bool { - *self == Fdprs::Div128Bus - } -} -#[doc = "Field `FDPRS` writer - Fault Detect Clock Prescaler"] -pub type FdprsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fdprs, crate::Safe>; -impl<'a, REG> FdprsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "1/1 bus clock."] - #[inline(always)] - pub fn div_1_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div1Bus) - } - #[doc = "1/2 bus clock."] - #[inline(always)] - pub fn div_2_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div2Bus) - } - #[doc = "1/4 bus clock."] - #[inline(always)] - pub fn div_4_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div4Bus) - } - #[doc = "1/8 bus clock."] - #[inline(always)] - pub fn div_8_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div8Bus) - } - #[doc = "1/16 bus clock."] - #[inline(always)] - pub fn div_16_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div16Bus) - } - #[doc = "1/32 bus clock."] - #[inline(always)] - pub fn div_32_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div32Bus) - } - #[doc = "1/64 bus clock."] - #[inline(always)] - pub fn div_64_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div64Bus) - } - #[doc = "1/128 bus clock."] - #[inline(always)] - pub fn div_128_bus(self) -> &'a mut crate::W { - self.variant(Fdprs::Div128Bus) - } -} -impl R { - #[doc = "Bits 0:5 - Fault Detect Pin ID"] - #[inline(always)] - pub fn fdpinid(&self) -> FdpinidR { - FdpinidR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Fault Detect Back Plane Enable"] - #[inline(always)] - pub fn fdbpen(&self) -> FdbpenR { - FdbpenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Fault Detect Enable"] - #[inline(always)] - pub fn fden(&self) -> FdenR { - FdenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 9:11 - Fault Detect Sample Window Width"] - #[inline(always)] - pub fn fdsww(&self) -> FdswwR { - FdswwR::new(((self.bits >> 9) & 7) as u8) - } - #[doc = "Bits 12:14 - Fault Detect Clock Prescaler"] - #[inline(always)] - pub fn fdprs(&self) -> FdprsR { - FdprsR::new(((self.bits >> 12) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:5 - Fault Detect Pin ID"] - #[inline(always)] - pub fn fdpinid(&mut self) -> FdpinidW { - FdpinidW::new(self, 0) - } - #[doc = "Bit 6 - Fault Detect Back Plane Enable"] - #[inline(always)] - pub fn fdbpen(&mut self) -> FdbpenW { - FdbpenW::new(self, 6) - } - #[doc = "Bit 7 - Fault Detect Enable"] - #[inline(always)] - pub fn fden(&mut self) -> FdenW { - FdenW::new(self, 7) - } - #[doc = "Bits 9:11 - Fault Detect Sample Window Width"] - #[inline(always)] - pub fn fdsww(&mut self) -> FdswwW { - FdswwW::new(self, 9) - } - #[doc = "Bits 12:14 - Fault Detect Clock Prescaler"] - #[inline(always)] - pub fn fdprs(&mut self) -> FdprsW { - FdprsW::new(self, 12) - } -} -#[doc = "LCD Fault Detect Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdFdcrSpec; -impl crate::RegisterSpec for LcdFdcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_fdcr::R`](R) reader structure"] -impl crate::Readable for LcdFdcrSpec {} -#[doc = "`write(|w| ..)` method takes [`lcd_fdcr::W`](W) writer structure"] -impl crate::Writable for LcdFdcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCD_FDCR to value 0"] -impl crate::Resettable for LcdFdcrSpec {} diff --git a/mcxa276-pac/src/slcd0/lcd_fdsr.rs b/mcxa276-pac/src/slcd0/lcd_fdsr.rs deleted file mode 100644 index 30edab7cd..000000000 --- a/mcxa276-pac/src/slcd0/lcd_fdsr.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `LCD_FDSR` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_FDSR` writer"] -pub type W = crate::W; -#[doc = "Field `FDCNT` reader - Fault Detect Counter"] -pub type FdcntR = crate::FieldReader; -#[doc = "Fault Detection Complete Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fdcf { - #[doc = "0: Fault detection is not completed."] - NotCompleted = 0, - #[doc = "1: Fault detection is completed."] - Completed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fdcf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FDCF` reader - Fault Detection Complete Flag"] -pub type FdcfR = crate::BitReader; -impl FdcfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fdcf { - match self.bits { - false => Fdcf::NotCompleted, - true => Fdcf::Completed, - } - } - #[doc = "Fault detection is not completed."] - #[inline(always)] - pub fn is_not_completed(&self) -> bool { - *self == Fdcf::NotCompleted - } - #[doc = "Fault detection is completed."] - #[inline(always)] - pub fn is_completed(&self) -> bool { - *self == Fdcf::Completed - } -} -#[doc = "Field `FDCF` writer - Fault Detection Complete Flag"] -pub type FdcfW<'a, REG> = crate::BitWriter1C<'a, REG, Fdcf>; -impl<'a, REG> FdcfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Fault detection is not completed."] - #[inline(always)] - pub fn not_completed(self) -> &'a mut crate::W { - self.variant(Fdcf::NotCompleted) - } - #[doc = "Fault detection is completed."] - #[inline(always)] - pub fn completed(self) -> &'a mut crate::W { - self.variant(Fdcf::Completed) - } -} -impl R { - #[doc = "Bits 0:7 - Fault Detect Counter"] - #[inline(always)] - pub fn fdcnt(&self) -> FdcntR { - FdcntR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 15 - Fault Detection Complete Flag"] - #[inline(always)] - pub fn fdcf(&self) -> FdcfR { - FdcfR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 15 - Fault Detection Complete Flag"] - #[inline(always)] - pub fn fdcf(&mut self) -> FdcfW { - FdcfW::new(self, 15) - } -} -#[doc = "LCD Fault Detect Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fdsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fdsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdFdsrSpec; -impl crate::RegisterSpec for LcdFdsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_fdsr::R`](R) reader structure"] -impl crate::Readable for LcdFdsrSpec {} -#[doc = "`write(|w| ..)` method takes [`lcd_fdsr::W`](W) writer structure"] -impl crate::Writable for LcdFdsrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000; -} -#[doc = "`reset()` method sets LCD_FDSR to value 0"] -impl crate::Resettable for LcdFdsrSpec {} diff --git a/mcxa276-pac/src/slcd0/lcd_gcr.rs b/mcxa276-pac/src/slcd0/lcd_gcr.rs deleted file mode 100644 index 68ae9f002..000000000 --- a/mcxa276-pac/src/slcd0/lcd_gcr.rs +++ /dev/null @@ -1,616 +0,0 @@ -#[doc = "Register `LCD_GCR` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_GCR` writer"] -pub type W = crate::W; -#[doc = "LCD duty select\n\nValue on reset: 3"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Duty { - #[doc = "0: Use 1 BP (1/1 duty cycle)."] - Use1Bp = 0, - #[doc = "1: Use 2 BP (1/2 duty cycle)."] - Use2Bp = 1, - #[doc = "2: Use 3 BP (1/3 duty cycle)."] - Use3Bp = 2, - #[doc = "3: Use 4 BP (1/4 duty cycle).(Default)"] - Use4Bp = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Duty) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Duty { - type Ux = u8; -} -impl crate::IsEnum for Duty {} -#[doc = "Field `DUTY` reader - LCD duty select"] -pub type DutyR = crate::FieldReader; -impl DutyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Duty { - match self.bits { - 0 => Duty::Use1Bp, - 1 => Duty::Use2Bp, - 2 => Duty::Use3Bp, - 3 => Duty::Use4Bp, - _ => unreachable!(), - } - } - #[doc = "Use 1 BP (1/1 duty cycle)."] - #[inline(always)] - pub fn is_use_1_bp(&self) -> bool { - *self == Duty::Use1Bp - } - #[doc = "Use 2 BP (1/2 duty cycle)."] - #[inline(always)] - pub fn is_use_2_bp(&self) -> bool { - *self == Duty::Use2Bp - } - #[doc = "Use 3 BP (1/3 duty cycle)."] - #[inline(always)] - pub fn is_use_3_bp(&self) -> bool { - *self == Duty::Use3Bp - } - #[doc = "Use 4 BP (1/4 duty cycle).(Default)"] - #[inline(always)] - pub fn is_use_4_bp(&self) -> bool { - *self == Duty::Use4Bp - } -} -#[doc = "Field `DUTY` writer - LCD duty select"] -pub type DutyW<'a, REG> = crate::FieldWriter<'a, REG, 2, Duty, crate::Safe>; -impl<'a, REG> DutyW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Use 1 BP (1/1 duty cycle)."] - #[inline(always)] - pub fn use_1_bp(self) -> &'a mut crate::W { - self.variant(Duty::Use1Bp) - } - #[doc = "Use 2 BP (1/2 duty cycle)."] - #[inline(always)] - pub fn use_2_bp(self) -> &'a mut crate::W { - self.variant(Duty::Use2Bp) - } - #[doc = "Use 3 BP (1/3 duty cycle)."] - #[inline(always)] - pub fn use_3_bp(self) -> &'a mut crate::W { - self.variant(Duty::Use3Bp) - } - #[doc = "Use 4 BP (1/4 duty cycle).(Default)"] - #[inline(always)] - pub fn use_4_bp(self) -> &'a mut crate::W { - self.variant(Duty::Use4Bp) - } -} -#[doc = "Field `LCLK` reader - LCD Clock Prescaler"] -pub type LclkR = crate::FieldReader; -#[doc = "Field `LCLK` writer - LCD Clock Prescaler"] -pub type LclkW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "LCD Low Power Waveform\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lcdlp { - #[doc = "0: LCD driver drives standard waveforms."] - High = 0, - #[doc = "1: LCD driver drives low-power waveforms."] - Low = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lcdlp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LCDLP` reader - LCD Low Power Waveform"] -pub type LcdlpR = crate::BitReader; -impl LcdlpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lcdlp { - match self.bits { - false => Lcdlp::High, - true => Lcdlp::Low, - } - } - #[doc = "LCD driver drives standard waveforms."] - #[inline(always)] - pub fn is_high(&self) -> bool { - *self == Lcdlp::High - } - #[doc = "LCD driver drives low-power waveforms."] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == Lcdlp::Low - } -} -#[doc = "Field `LCDLP` writer - LCD Low Power Waveform"] -pub type LcdlpW<'a, REG> = crate::BitWriter<'a, REG, Lcdlp>; -impl<'a, REG> LcdlpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "LCD driver drives standard waveforms."] - #[inline(always)] - pub fn high(self) -> &'a mut crate::W { - self.variant(Lcdlp::High) - } - #[doc = "LCD driver drives low-power waveforms."] - #[inline(always)] - pub fn low(self) -> &'a mut crate::W { - self.variant(Lcdlp::Low) - } -} -#[doc = "Field `LCDEN` reader - LCD Driver Enable"] -pub type LcdenR = crate::BitReader; -#[doc = "Field `LCDEN` writer - LCD Driver Enable"] -pub type LcdenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "LCD Stop\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lcdstp { - #[doc = "0: Allows the LCD driver to continue running during Stop mode."] - Enable = 0, - #[doc = "1: Disables the LCD driver when MCU enters Stop mode."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lcdstp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LCDSTP` reader - LCD Stop"] -pub type LcdstpR = crate::BitReader; -impl LcdstpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lcdstp { - match self.bits { - false => Lcdstp::Enable, - true => Lcdstp::Disable, - } - } - #[doc = "Allows the LCD driver to continue running during Stop mode."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lcdstp::Enable - } - #[doc = "Disables the LCD driver when MCU enters Stop mode."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lcdstp::Disable - } -} -#[doc = "Field `LCDSTP` writer - LCD Stop"] -pub type LcdstpW<'a, REG> = crate::BitWriter<'a, REG, Lcdstp>; -impl<'a, REG> LcdstpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Allows the LCD driver to continue running during Stop mode."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lcdstp::Enable) - } - #[doc = "Disables the LCD driver when MCU enters Stop mode."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lcdstp::Disable) - } -} -#[doc = "LCD Doze enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lcddoze { - #[doc = "0: Allows the LCD driver to continue running during Doze mode."] - Enable = 0, - #[doc = "1: Disables the LCD driver when MCU enters Doze mode."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lcddoze) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LCDDOZE` reader - LCD Doze enable"] -pub type LcddozeR = crate::BitReader; -impl LcddozeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lcddoze { - match self.bits { - false => Lcddoze::Enable, - true => Lcddoze::Disable, - } - } - #[doc = "Allows the LCD driver to continue running during Doze mode."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lcddoze::Enable - } - #[doc = "Disables the LCD driver when MCU enters Doze mode."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lcddoze::Disable - } -} -#[doc = "Field `LCDDOZE` writer - LCD Doze enable"] -pub type LcddozeW<'a, REG> = crate::BitWriter<'a, REG, Lcddoze>; -impl<'a, REG> LcddozeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Allows the LCD driver to continue running during Doze mode."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lcddoze::Enable) - } - #[doc = "Disables the LCD driver when MCU enters Doze mode."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lcddoze::Disable) - } -} -#[doc = "LCD Fault Detection Complete Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Fdcien { - #[doc = "0: No interrupt request is generated by this event."] - Disable = 0, - #[doc = "1: When a fault is detected and FDCF bit is set, this event causes an interrupt request."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Fdcien) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FDCIEN` reader - LCD Fault Detection Complete Interrupt Enable"] -pub type FdcienR = crate::BitReader; -impl FdcienR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Fdcien { - match self.bits { - false => Fdcien::Disable, - true => Fdcien::Enable, - } - } - #[doc = "No interrupt request is generated by this event."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Fdcien::Disable - } - #[doc = "When a fault is detected and FDCF bit is set, this event causes an interrupt request."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Fdcien::Enable - } -} -#[doc = "Field `FDCIEN` writer - LCD Fault Detection Complete Interrupt Enable"] -pub type FdcienW<'a, REG> = crate::BitWriter<'a, REG, Fdcien>; -impl<'a, REG> FdcienW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No interrupt request is generated by this event."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Fdcien::Disable) - } - #[doc = "When a fault is detected and FDCF bit is set, this event causes an interrupt request."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Fdcien::Enable) - } -} -#[doc = "LCD Frame Frequency Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lcdien { - #[doc = "0: No interrupt request is generated by this event."] - Disable = 0, - #[doc = "1: When LCDIF bit is set, this event causes an interrupt request."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lcdien) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LCDIEN` reader - LCD Frame Frequency Interrupt Enable"] -pub type LcdienR = crate::BitReader; -impl LcdienR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lcdien { - match self.bits { - false => Lcdien::Disable, - true => Lcdien::Enable, - } - } - #[doc = "No interrupt request is generated by this event."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lcdien::Disable - } - #[doc = "When LCDIF bit is set, this event causes an interrupt request."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lcdien::Enable - } -} -#[doc = "Field `LCDIEN` writer - LCD Frame Frequency Interrupt Enable"] -pub type LcdienW<'a, REG> = crate::BitWriter<'a, REG, Lcdien>; -impl<'a, REG> LcdienW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No interrupt request is generated by this event."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lcdien::Disable) - } - #[doc = "When LCDIF bit is set, this event causes an interrupt request."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lcdien::Enable) - } -} -#[doc = "Sample & Hold Cycle Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Shcycle { - #[doc = "0: Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period."] - Clk64 = 0, - #[doc = "1: Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period."] - Clk128 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Shcycle) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SHCYCLE` reader - Sample & Hold Cycle Select"] -pub type ShcycleR = crate::BitReader; -impl ShcycleR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Shcycle { - match self.bits { - false => Shcycle::Clk64, - true => Shcycle::Clk128, - } - } - #[doc = "Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period."] - #[inline(always)] - pub fn is_clk64(&self) -> bool { - *self == Shcycle::Clk64 - } - #[doc = "Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period."] - #[inline(always)] - pub fn is_clk128(&self) -> bool { - *self == Shcycle::Clk128 - } -} -#[doc = "Field `SHCYCLE` writer - Sample & Hold Cycle Select"] -pub type ShcycleW<'a, REG> = crate::BitWriter<'a, REG, Shcycle>; -impl<'a, REG> ShcycleW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period."] - #[inline(always)] - pub fn clk64(self) -> &'a mut crate::W { - self.variant(Shcycle::Clk64) - } - #[doc = "Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period."] - #[inline(always)] - pub fn clk128(self) -> &'a mut crate::W { - self.variant(Shcycle::Clk128) - } -} -#[doc = "Sample & Hold Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Shen { - #[doc = "0: Sample & hold is disabled."] - Disable = 0, - #[doc = "1: Sample & hold is enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Shen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SHEN` reader - Sample & Hold Mode Enable"] -pub type ShenR = crate::BitReader; -impl ShenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Shen { - match self.bits { - false => Shen::Disable, - true => Shen::Enable, - } - } - #[doc = "Sample & hold is disabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Shen::Disable - } - #[doc = "Sample & hold is enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Shen::Enable - } -} -#[doc = "Field `SHEN` writer - Sample & Hold Mode Enable"] -pub type ShenW<'a, REG> = crate::BitWriter<'a, REG, Shen>; -impl<'a, REG> ShenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Sample & hold is disabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Shen::Disable) - } - #[doc = "Sample & hold is enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Shen::Enable) - } -} -#[doc = "Field `VLL1TRIM` reader - Level 1 Voltage Trim"] -pub type Vll1trimR = crate::FieldReader; -#[doc = "Field `VLL1TRIM` writer - Level 1 Voltage Trim"] -pub type Vll1trimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `VLL2TRIM` reader - Level 2 Voltage Trim"] -pub type Vll2trimR = crate::FieldReader; -#[doc = "Field `VLL2TRIM` writer - Level 2 Voltage Trim"] -pub type Vll2trimW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:1 - LCD duty select"] - #[inline(always)] - pub fn duty(&self) -> DutyR { - DutyR::new((self.bits & 3) as u8) - } - #[doc = "Bits 3:5 - LCD Clock Prescaler"] - #[inline(always)] - pub fn lclk(&self) -> LclkR { - LclkR::new(((self.bits >> 3) & 7) as u8) - } - #[doc = "Bit 6 - LCD Low Power Waveform"] - #[inline(always)] - pub fn lcdlp(&self) -> LcdlpR { - LcdlpR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - LCD Driver Enable"] - #[inline(always)] - pub fn lcden(&self) -> LcdenR { - LcdenR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - LCD Stop"] - #[inline(always)] - pub fn lcdstp(&self) -> LcdstpR { - LcdstpR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - LCD Doze enable"] - #[inline(always)] - pub fn lcddoze(&self) -> LcddozeR { - LcddozeR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 14 - LCD Fault Detection Complete Interrupt Enable"] - #[inline(always)] - pub fn fdcien(&self) -> FdcienR { - FdcienR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - LCD Frame Frequency Interrupt Enable"] - #[inline(always)] - pub fn lcdien(&self) -> LcdienR { - LcdienR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Sample & Hold Cycle Select"] - #[inline(always)] - pub fn shcycle(&self) -> ShcycleR { - ShcycleR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 23 - Sample & Hold Mode Enable"] - #[inline(always)] - pub fn shen(&self) -> ShenR { - ShenR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:27 - Level 1 Voltage Trim"] - #[inline(always)] - pub fn vll1trim(&self) -> Vll1trimR { - Vll1trimR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bits 28:31 - Level 2 Voltage Trim"] - #[inline(always)] - pub fn vll2trim(&self) -> Vll2trimR { - Vll2trimR::new(((self.bits >> 28) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - LCD duty select"] - #[inline(always)] - pub fn duty(&mut self) -> DutyW { - DutyW::new(self, 0) - } - #[doc = "Bits 3:5 - LCD Clock Prescaler"] - #[inline(always)] - pub fn lclk(&mut self) -> LclkW { - LclkW::new(self, 3) - } - #[doc = "Bit 6 - LCD Low Power Waveform"] - #[inline(always)] - pub fn lcdlp(&mut self) -> LcdlpW { - LcdlpW::new(self, 6) - } - #[doc = "Bit 7 - LCD Driver Enable"] - #[inline(always)] - pub fn lcden(&mut self) -> LcdenW { - LcdenW::new(self, 7) - } - #[doc = "Bit 8 - LCD Stop"] - #[inline(always)] - pub fn lcdstp(&mut self) -> LcdstpW { - LcdstpW::new(self, 8) - } - #[doc = "Bit 9 - LCD Doze enable"] - #[inline(always)] - pub fn lcddoze(&mut self) -> LcddozeW { - LcddozeW::new(self, 9) - } - #[doc = "Bit 14 - LCD Fault Detection Complete Interrupt Enable"] - #[inline(always)] - pub fn fdcien(&mut self) -> FdcienW { - FdcienW::new(self, 14) - } - #[doc = "Bit 15 - LCD Frame Frequency Interrupt Enable"] - #[inline(always)] - pub fn lcdien(&mut self) -> LcdienW { - LcdienW::new(self, 15) - } - #[doc = "Bit 16 - Sample & Hold Cycle Select"] - #[inline(always)] - pub fn shcycle(&mut self) -> ShcycleW { - ShcycleW::new(self, 16) - } - #[doc = "Bit 23 - Sample & Hold Mode Enable"] - #[inline(always)] - pub fn shen(&mut self) -> ShenW { - ShenW::new(self, 23) - } - #[doc = "Bits 24:27 - Level 1 Voltage Trim"] - #[inline(always)] - pub fn vll1trim(&mut self) -> Vll1trimW { - Vll1trimW::new(self, 24) - } - #[doc = "Bits 28:31 - Level 2 Voltage Trim"] - #[inline(always)] - pub fn vll2trim(&mut self) -> Vll2trimW { - Vll2trimW::new(self, 28) - } -} -#[doc = "LCD General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_gcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_gcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdGcrSpec; -impl crate::RegisterSpec for LcdGcrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_gcr::R`](R) reader structure"] -impl crate::Readable for LcdGcrSpec {} -#[doc = "`write(|w| ..)` method takes [`lcd_gcr::W`](W) writer structure"] -impl crate::Writable for LcdGcrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCD_GCR to value 0x03"] -impl crate::Resettable for LcdGcrSpec { - const RESET_VALUE: u32 = 0x03; -} diff --git a/mcxa276-pac/src/slcd0/lcd_pen0.rs b/mcxa276-pac/src/slcd0/lcd_pen0.rs deleted file mode 100644 index adc747f39..000000000 --- a/mcxa276-pac/src/slcd0/lcd_pen0.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `LCD_PEN0` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_PEN0` writer"] -pub type W = crate::W; -#[doc = "LCD Pin 0 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin0En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin0En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_0_EN` reader - LCD Pin 0 Enable"] -pub type Pin0EnR = crate::BitReader; -impl Pin0EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin0En { - match self.bits { - false => Pin0En::Disable, - true => Pin0En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin0En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin0En::Enable - } -} -#[doc = "Field `PIN_0_EN` writer - LCD Pin 0 Enable"] -pub type Pin0EnW<'a, REG> = crate::BitWriter<'a, REG, Pin0En>; -impl<'a, REG> Pin0EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin0En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin0En::Enable) - } -} -#[doc = "LCD Pin 1 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin1En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin1En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_1_EN` reader - LCD Pin 1 Enable"] -pub type Pin1EnR = crate::BitReader; -impl Pin1EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin1En { - match self.bits { - false => Pin1En::Disable, - true => Pin1En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin1En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin1En::Enable - } -} -#[doc = "Field `PIN_1_EN` writer - LCD Pin 1 Enable"] -pub type Pin1EnW<'a, REG> = crate::BitWriter<'a, REG, Pin1En>; -impl<'a, REG> Pin1EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin1En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin1En::Enable) - } -} -#[doc = "LCD Pin 2 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin2En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin2En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_2_EN` reader - LCD Pin 2 Enable"] -pub type Pin2EnR = crate::BitReader; -impl Pin2EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin2En { - match self.bits { - false => Pin2En::Disable, - true => Pin2En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin2En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin2En::Enable - } -} -#[doc = "Field `PIN_2_EN` writer - LCD Pin 2 Enable"] -pub type Pin2EnW<'a, REG> = crate::BitWriter<'a, REG, Pin2En>; -impl<'a, REG> Pin2EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin2En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin2En::Enable) - } -} -#[doc = "LCD Pin 3 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin3En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin3En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_3_EN` reader - LCD Pin 3 Enable"] -pub type Pin3EnR = crate::BitReader; -impl Pin3EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin3En { - match self.bits { - false => Pin3En::Disable, - true => Pin3En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin3En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin3En::Enable - } -} -#[doc = "Field `PIN_3_EN` writer - LCD Pin 3 Enable"] -pub type Pin3EnW<'a, REG> = crate::BitWriter<'a, REG, Pin3En>; -impl<'a, REG> Pin3EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin3En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin3En::Enable) - } -} -#[doc = "LCD Pin 4 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin4En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin4En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_4_EN` reader - LCD Pin 4 Enable"] -pub type Pin4EnR = crate::BitReader; -impl Pin4EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin4En { - match self.bits { - false => Pin4En::Disable, - true => Pin4En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin4En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin4En::Enable - } -} -#[doc = "Field `PIN_4_EN` writer - LCD Pin 4 Enable"] -pub type Pin4EnW<'a, REG> = crate::BitWriter<'a, REG, Pin4En>; -impl<'a, REG> Pin4EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin4En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin4En::Enable) - } -} -#[doc = "LCD Pin 5 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin5En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin5En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_5_EN` reader - LCD Pin 5 Enable"] -pub type Pin5EnR = crate::BitReader; -impl Pin5EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin5En { - match self.bits { - false => Pin5En::Disable, - true => Pin5En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin5En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin5En::Enable - } -} -#[doc = "Field `PIN_5_EN` writer - LCD Pin 5 Enable"] -pub type Pin5EnW<'a, REG> = crate::BitWriter<'a, REG, Pin5En>; -impl<'a, REG> Pin5EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin5En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin5En::Enable) - } -} -#[doc = "LCD Pin 6 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin6En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin6En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_6_EN` reader - LCD Pin 6 Enable"] -pub type Pin6EnR = crate::BitReader; -impl Pin6EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin6En { - match self.bits { - false => Pin6En::Disable, - true => Pin6En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin6En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin6En::Enable - } -} -#[doc = "Field `PIN_6_EN` writer - LCD Pin 6 Enable"] -pub type Pin6EnW<'a, REG> = crate::BitWriter<'a, REG, Pin6En>; -impl<'a, REG> Pin6EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin6En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin6En::Enable) - } -} -#[doc = "LCD Pin 7 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin7En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin7En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_7_EN` reader - LCD Pin 7 Enable"] -pub type Pin7EnR = crate::BitReader; -impl Pin7EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin7En { - match self.bits { - false => Pin7En::Disable, - true => Pin7En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin7En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin7En::Enable - } -} -#[doc = "Field `PIN_7_EN` writer - LCD Pin 7 Enable"] -pub type Pin7EnW<'a, REG> = crate::BitWriter<'a, REG, Pin7En>; -impl<'a, REG> Pin7EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin7En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin7En::Enable) - } -} -#[doc = "LCD Pin 8 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin8En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin8En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_8_EN` reader - LCD Pin 8 Enable"] -pub type Pin8EnR = crate::BitReader; -impl Pin8EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin8En { - match self.bits { - false => Pin8En::Disable, - true => Pin8En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin8En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin8En::Enable - } -} -#[doc = "Field `PIN_8_EN` writer - LCD Pin 8 Enable"] -pub type Pin8EnW<'a, REG> = crate::BitWriter<'a, REG, Pin8En>; -impl<'a, REG> Pin8EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin8En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin8En::Enable) - } -} -#[doc = "LCD Pin 9 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin9En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin9En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_9_EN` reader - LCD Pin 9 Enable"] -pub type Pin9EnR = crate::BitReader; -impl Pin9EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin9En { - match self.bits { - false => Pin9En::Disable, - true => Pin9En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin9En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin9En::Enable - } -} -#[doc = "Field `PIN_9_EN` writer - LCD Pin 9 Enable"] -pub type Pin9EnW<'a, REG> = crate::BitWriter<'a, REG, Pin9En>; -impl<'a, REG> Pin9EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin9En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin9En::Enable) - } -} -#[doc = "LCD Pin 10 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin10En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin10En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_10_EN` reader - LCD Pin 10 Enable"] -pub type Pin10EnR = crate::BitReader; -impl Pin10EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin10En { - match self.bits { - false => Pin10En::Disable, - true => Pin10En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin10En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin10En::Enable - } -} -#[doc = "Field `PIN_10_EN` writer - LCD Pin 10 Enable"] -pub type Pin10EnW<'a, REG> = crate::BitWriter<'a, REG, Pin10En>; -impl<'a, REG> Pin10EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin10En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin10En::Enable) - } -} -#[doc = "LCD Pin 11 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin11En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin11En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_11_EN` reader - LCD Pin 11 Enable"] -pub type Pin11EnR = crate::BitReader; -impl Pin11EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin11En { - match self.bits { - false => Pin11En::Disable, - true => Pin11En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin11En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin11En::Enable - } -} -#[doc = "Field `PIN_11_EN` writer - LCD Pin 11 Enable"] -pub type Pin11EnW<'a, REG> = crate::BitWriter<'a, REG, Pin11En>; -impl<'a, REG> Pin11EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin11En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin11En::Enable) - } -} -#[doc = "LCD Pin 12 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin12En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin12En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_12_EN` reader - LCD Pin 12 Enable"] -pub type Pin12EnR = crate::BitReader; -impl Pin12EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin12En { - match self.bits { - false => Pin12En::Disable, - true => Pin12En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin12En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin12En::Enable - } -} -#[doc = "Field `PIN_12_EN` writer - LCD Pin 12 Enable"] -pub type Pin12EnW<'a, REG> = crate::BitWriter<'a, REG, Pin12En>; -impl<'a, REG> Pin12EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin12En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin12En::Enable) - } -} -#[doc = "LCD Pin 13 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin13En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin13En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_13_EN` reader - LCD Pin 13 Enable"] -pub type Pin13EnR = crate::BitReader; -impl Pin13EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin13En { - match self.bits { - false => Pin13En::Disable, - true => Pin13En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin13En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin13En::Enable - } -} -#[doc = "Field `PIN_13_EN` writer - LCD Pin 13 Enable"] -pub type Pin13EnW<'a, REG> = crate::BitWriter<'a, REG, Pin13En>; -impl<'a, REG> Pin13EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin13En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin13En::Enable) - } -} -#[doc = "LCD Pin 14 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin14En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin14En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_14_EN` reader - LCD Pin 14 Enable"] -pub type Pin14EnR = crate::BitReader; -impl Pin14EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin14En { - match self.bits { - false => Pin14En::Disable, - true => Pin14En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin14En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin14En::Enable - } -} -#[doc = "Field `PIN_14_EN` writer - LCD Pin 14 Enable"] -pub type Pin14EnW<'a, REG> = crate::BitWriter<'a, REG, Pin14En>; -impl<'a, REG> Pin14EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin14En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin14En::Enable) - } -} -#[doc = "LCD Pin 15 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin15En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin15En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_15_EN` reader - LCD Pin 15 Enable"] -pub type Pin15EnR = crate::BitReader; -impl Pin15EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin15En { - match self.bits { - false => Pin15En::Disable, - true => Pin15En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin15En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin15En::Enable - } -} -#[doc = "Field `PIN_15_EN` writer - LCD Pin 15 Enable"] -pub type Pin15EnW<'a, REG> = crate::BitWriter<'a, REG, Pin15En>; -impl<'a, REG> Pin15EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin15En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin15En::Enable) - } -} -#[doc = "LCD Pin 16 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin16En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin16En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_16_EN` reader - LCD Pin 16 Enable"] -pub type Pin16EnR = crate::BitReader; -impl Pin16EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin16En { - match self.bits { - false => Pin16En::Disable, - true => Pin16En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin16En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin16En::Enable - } -} -#[doc = "Field `PIN_16_EN` writer - LCD Pin 16 Enable"] -pub type Pin16EnW<'a, REG> = crate::BitWriter<'a, REG, Pin16En>; -impl<'a, REG> Pin16EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin16En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin16En::Enable) - } -} -#[doc = "LCD Pin 17 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin17En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin17En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_17_EN` reader - LCD Pin 17 Enable"] -pub type Pin17EnR = crate::BitReader; -impl Pin17EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin17En { - match self.bits { - false => Pin17En::Disable, - true => Pin17En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin17En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin17En::Enable - } -} -#[doc = "Field `PIN_17_EN` writer - LCD Pin 17 Enable"] -pub type Pin17EnW<'a, REG> = crate::BitWriter<'a, REG, Pin17En>; -impl<'a, REG> Pin17EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin17En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin17En::Enable) - } -} -#[doc = "LCD Pin 18 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin18En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin18En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_18_EN` reader - LCD Pin 18 Enable"] -pub type Pin18EnR = crate::BitReader; -impl Pin18EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin18En { - match self.bits { - false => Pin18En::Disable, - true => Pin18En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin18En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin18En::Enable - } -} -#[doc = "Field `PIN_18_EN` writer - LCD Pin 18 Enable"] -pub type Pin18EnW<'a, REG> = crate::BitWriter<'a, REG, Pin18En>; -impl<'a, REG> Pin18EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin18En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin18En::Enable) - } -} -#[doc = "LCD Pin 19 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin19En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin19En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_19_EN` reader - LCD Pin 19 Enable"] -pub type Pin19EnR = crate::BitReader; -impl Pin19EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin19En { - match self.bits { - false => Pin19En::Disable, - true => Pin19En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin19En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin19En::Enable - } -} -#[doc = "Field `PIN_19_EN` writer - LCD Pin 19 Enable"] -pub type Pin19EnW<'a, REG> = crate::BitWriter<'a, REG, Pin19En>; -impl<'a, REG> Pin19EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin19En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin19En::Enable) - } -} -#[doc = "LCD Pin 20 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin20En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin20En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_20_EN` reader - LCD Pin 20 Enable"] -pub type Pin20EnR = crate::BitReader; -impl Pin20EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin20En { - match self.bits { - false => Pin20En::Disable, - true => Pin20En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin20En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin20En::Enable - } -} -#[doc = "Field `PIN_20_EN` writer - LCD Pin 20 Enable"] -pub type Pin20EnW<'a, REG> = crate::BitWriter<'a, REG, Pin20En>; -impl<'a, REG> Pin20EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin20En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin20En::Enable) - } -} -#[doc = "LCD Pin 21 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin21En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin21En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_21_EN` reader - LCD Pin 21 Enable"] -pub type Pin21EnR = crate::BitReader; -impl Pin21EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin21En { - match self.bits { - false => Pin21En::Disable, - true => Pin21En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin21En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin21En::Enable - } -} -#[doc = "Field `PIN_21_EN` writer - LCD Pin 21 Enable"] -pub type Pin21EnW<'a, REG> = crate::BitWriter<'a, REG, Pin21En>; -impl<'a, REG> Pin21EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin21En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin21En::Enable) - } -} -#[doc = "LCD Pin 22 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin22En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin22En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_22_EN` reader - LCD Pin 22 Enable"] -pub type Pin22EnR = crate::BitReader; -impl Pin22EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin22En { - match self.bits { - false => Pin22En::Disable, - true => Pin22En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin22En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin22En::Enable - } -} -#[doc = "Field `PIN_22_EN` writer - LCD Pin 22 Enable"] -pub type Pin22EnW<'a, REG> = crate::BitWriter<'a, REG, Pin22En>; -impl<'a, REG> Pin22EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin22En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin22En::Enable) - } -} -#[doc = "LCD Pin 23 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin23En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin23En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_23_EN` reader - LCD Pin 23 Enable"] -pub type Pin23EnR = crate::BitReader; -impl Pin23EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin23En { - match self.bits { - false => Pin23En::Disable, - true => Pin23En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin23En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin23En::Enable - } -} -#[doc = "Field `PIN_23_EN` writer - LCD Pin 23 Enable"] -pub type Pin23EnW<'a, REG> = crate::BitWriter<'a, REG, Pin23En>; -impl<'a, REG> Pin23EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin23En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin23En::Enable) - } -} -#[doc = "LCD Pin 24 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin24En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin24En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_24_EN` reader - LCD Pin 24 Enable"] -pub type Pin24EnR = crate::BitReader; -impl Pin24EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin24En { - match self.bits { - false => Pin24En::Disable, - true => Pin24En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin24En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin24En::Enable - } -} -#[doc = "Field `PIN_24_EN` writer - LCD Pin 24 Enable"] -pub type Pin24EnW<'a, REG> = crate::BitWriter<'a, REG, Pin24En>; -impl<'a, REG> Pin24EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin24En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin24En::Enable) - } -} -#[doc = "LCD Pin 25 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin25En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin25En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_25_EN` reader - LCD Pin 25 Enable"] -pub type Pin25EnR = crate::BitReader; -impl Pin25EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin25En { - match self.bits { - false => Pin25En::Disable, - true => Pin25En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin25En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin25En::Enable - } -} -#[doc = "Field `PIN_25_EN` writer - LCD Pin 25 Enable"] -pub type Pin25EnW<'a, REG> = crate::BitWriter<'a, REG, Pin25En>; -impl<'a, REG> Pin25EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin25En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin25En::Enable) - } -} -#[doc = "LCD Pin 26 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin26En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin26En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_26_EN` reader - LCD Pin 26 Enable"] -pub type Pin26EnR = crate::BitReader; -impl Pin26EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin26En { - match self.bits { - false => Pin26En::Disable, - true => Pin26En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin26En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin26En::Enable - } -} -#[doc = "Field `PIN_26_EN` writer - LCD Pin 26 Enable"] -pub type Pin26EnW<'a, REG> = crate::BitWriter<'a, REG, Pin26En>; -impl<'a, REG> Pin26EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin26En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin26En::Enable) - } -} -#[doc = "LCD Pin 27 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin27En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin27En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_27_EN` reader - LCD Pin 27 Enable"] -pub type Pin27EnR = crate::BitReader; -impl Pin27EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin27En { - match self.bits { - false => Pin27En::Disable, - true => Pin27En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin27En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin27En::Enable - } -} -#[doc = "Field `PIN_27_EN` writer - LCD Pin 27 Enable"] -pub type Pin27EnW<'a, REG> = crate::BitWriter<'a, REG, Pin27En>; -impl<'a, REG> Pin27EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin27En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin27En::Enable) - } -} -#[doc = "LCD Pin 28 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin28En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin28En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_28_EN` reader - LCD Pin 28 Enable"] -pub type Pin28EnR = crate::BitReader; -impl Pin28EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin28En { - match self.bits { - false => Pin28En::Disable, - true => Pin28En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin28En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin28En::Enable - } -} -#[doc = "Field `PIN_28_EN` writer - LCD Pin 28 Enable"] -pub type Pin28EnW<'a, REG> = crate::BitWriter<'a, REG, Pin28En>; -impl<'a, REG> Pin28EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin28En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin28En::Enable) - } -} -#[doc = "LCD Pin 29 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin29En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin29En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_29_EN` reader - LCD Pin 29 Enable"] -pub type Pin29EnR = crate::BitReader; -impl Pin29EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin29En { - match self.bits { - false => Pin29En::Disable, - true => Pin29En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin29En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin29En::Enable - } -} -#[doc = "Field `PIN_29_EN` writer - LCD Pin 29 Enable"] -pub type Pin29EnW<'a, REG> = crate::BitWriter<'a, REG, Pin29En>; -impl<'a, REG> Pin29EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin29En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin29En::Enable) - } -} -#[doc = "LCD Pin 30 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin30En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin30En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_30_EN` reader - LCD Pin 30 Enable"] -pub type Pin30EnR = crate::BitReader; -impl Pin30EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin30En { - match self.bits { - false => Pin30En::Disable, - true => Pin30En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin30En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin30En::Enable - } -} -#[doc = "Field `PIN_30_EN` writer - LCD Pin 30 Enable"] -pub type Pin30EnW<'a, REG> = crate::BitWriter<'a, REG, Pin30En>; -impl<'a, REG> Pin30EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin30En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin30En::Enable) - } -} -#[doc = "LCD Pin 31 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin31En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin31En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_31_EN` reader - LCD Pin 31 Enable"] -pub type Pin31EnR = crate::BitReader; -impl Pin31EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin31En { - match self.bits { - false => Pin31En::Disable, - true => Pin31En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin31En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin31En::Enable - } -} -#[doc = "Field `PIN_31_EN` writer - LCD Pin 31 Enable"] -pub type Pin31EnW<'a, REG> = crate::BitWriter<'a, REG, Pin31En>; -impl<'a, REG> Pin31EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin31En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin31En::Enable) - } -} -impl R { - #[doc = "Bit 0 - LCD Pin 0 Enable"] - #[inline(always)] - pub fn pin_0_en(&self) -> Pin0EnR { - Pin0EnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - LCD Pin 1 Enable"] - #[inline(always)] - pub fn pin_1_en(&self) -> Pin1EnR { - Pin1EnR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - LCD Pin 2 Enable"] - #[inline(always)] - pub fn pin_2_en(&self) -> Pin2EnR { - Pin2EnR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - LCD Pin 3 Enable"] - #[inline(always)] - pub fn pin_3_en(&self) -> Pin3EnR { - Pin3EnR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - LCD Pin 4 Enable"] - #[inline(always)] - pub fn pin_4_en(&self) -> Pin4EnR { - Pin4EnR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - LCD Pin 5 Enable"] - #[inline(always)] - pub fn pin_5_en(&self) -> Pin5EnR { - Pin5EnR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - LCD Pin 6 Enable"] - #[inline(always)] - pub fn pin_6_en(&self) -> Pin6EnR { - Pin6EnR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - LCD Pin 7 Enable"] - #[inline(always)] - pub fn pin_7_en(&self) -> Pin7EnR { - Pin7EnR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - LCD Pin 8 Enable"] - #[inline(always)] - pub fn pin_8_en(&self) -> Pin8EnR { - Pin8EnR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - LCD Pin 9 Enable"] - #[inline(always)] - pub fn pin_9_en(&self) -> Pin9EnR { - Pin9EnR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - LCD Pin 10 Enable"] - #[inline(always)] - pub fn pin_10_en(&self) -> Pin10EnR { - Pin10EnR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - LCD Pin 11 Enable"] - #[inline(always)] - pub fn pin_11_en(&self) -> Pin11EnR { - Pin11EnR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - LCD Pin 12 Enable"] - #[inline(always)] - pub fn pin_12_en(&self) -> Pin12EnR { - Pin12EnR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - LCD Pin 13 Enable"] - #[inline(always)] - pub fn pin_13_en(&self) -> Pin13EnR { - Pin13EnR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - LCD Pin 14 Enable"] - #[inline(always)] - pub fn pin_14_en(&self) -> Pin14EnR { - Pin14EnR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - LCD Pin 15 Enable"] - #[inline(always)] - pub fn pin_15_en(&self) -> Pin15EnR { - Pin15EnR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - LCD Pin 16 Enable"] - #[inline(always)] - pub fn pin_16_en(&self) -> Pin16EnR { - Pin16EnR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - LCD Pin 17 Enable"] - #[inline(always)] - pub fn pin_17_en(&self) -> Pin17EnR { - Pin17EnR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - LCD Pin 18 Enable"] - #[inline(always)] - pub fn pin_18_en(&self) -> Pin18EnR { - Pin18EnR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - LCD Pin 19 Enable"] - #[inline(always)] - pub fn pin_19_en(&self) -> Pin19EnR { - Pin19EnR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - LCD Pin 20 Enable"] - #[inline(always)] - pub fn pin_20_en(&self) -> Pin20EnR { - Pin20EnR::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - LCD Pin 21 Enable"] - #[inline(always)] - pub fn pin_21_en(&self) -> Pin21EnR { - Pin21EnR::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - LCD Pin 22 Enable"] - #[inline(always)] - pub fn pin_22_en(&self) -> Pin22EnR { - Pin22EnR::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - LCD Pin 23 Enable"] - #[inline(always)] - pub fn pin_23_en(&self) -> Pin23EnR { - Pin23EnR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - LCD Pin 24 Enable"] - #[inline(always)] - pub fn pin_24_en(&self) -> Pin24EnR { - Pin24EnR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - LCD Pin 25 Enable"] - #[inline(always)] - pub fn pin_25_en(&self) -> Pin25EnR { - Pin25EnR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - LCD Pin 26 Enable"] - #[inline(always)] - pub fn pin_26_en(&self) -> Pin26EnR { - Pin26EnR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - LCD Pin 27 Enable"] - #[inline(always)] - pub fn pin_27_en(&self) -> Pin27EnR { - Pin27EnR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - LCD Pin 28 Enable"] - #[inline(always)] - pub fn pin_28_en(&self) -> Pin28EnR { - Pin28EnR::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - LCD Pin 29 Enable"] - #[inline(always)] - pub fn pin_29_en(&self) -> Pin29EnR { - Pin29EnR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - LCD Pin 30 Enable"] - #[inline(always)] - pub fn pin_30_en(&self) -> Pin30EnR { - Pin30EnR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - LCD Pin 31 Enable"] - #[inline(always)] - pub fn pin_31_en(&self) -> Pin31EnR { - Pin31EnR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LCD Pin 0 Enable"] - #[inline(always)] - pub fn pin_0_en(&mut self) -> Pin0EnW { - Pin0EnW::new(self, 0) - } - #[doc = "Bit 1 - LCD Pin 1 Enable"] - #[inline(always)] - pub fn pin_1_en(&mut self) -> Pin1EnW { - Pin1EnW::new(self, 1) - } - #[doc = "Bit 2 - LCD Pin 2 Enable"] - #[inline(always)] - pub fn pin_2_en(&mut self) -> Pin2EnW { - Pin2EnW::new(self, 2) - } - #[doc = "Bit 3 - LCD Pin 3 Enable"] - #[inline(always)] - pub fn pin_3_en(&mut self) -> Pin3EnW { - Pin3EnW::new(self, 3) - } - #[doc = "Bit 4 - LCD Pin 4 Enable"] - #[inline(always)] - pub fn pin_4_en(&mut self) -> Pin4EnW { - Pin4EnW::new(self, 4) - } - #[doc = "Bit 5 - LCD Pin 5 Enable"] - #[inline(always)] - pub fn pin_5_en(&mut self) -> Pin5EnW { - Pin5EnW::new(self, 5) - } - #[doc = "Bit 6 - LCD Pin 6 Enable"] - #[inline(always)] - pub fn pin_6_en(&mut self) -> Pin6EnW { - Pin6EnW::new(self, 6) - } - #[doc = "Bit 7 - LCD Pin 7 Enable"] - #[inline(always)] - pub fn pin_7_en(&mut self) -> Pin7EnW { - Pin7EnW::new(self, 7) - } - #[doc = "Bit 8 - LCD Pin 8 Enable"] - #[inline(always)] - pub fn pin_8_en(&mut self) -> Pin8EnW { - Pin8EnW::new(self, 8) - } - #[doc = "Bit 9 - LCD Pin 9 Enable"] - #[inline(always)] - pub fn pin_9_en(&mut self) -> Pin9EnW { - Pin9EnW::new(self, 9) - } - #[doc = "Bit 10 - LCD Pin 10 Enable"] - #[inline(always)] - pub fn pin_10_en(&mut self) -> Pin10EnW { - Pin10EnW::new(self, 10) - } - #[doc = "Bit 11 - LCD Pin 11 Enable"] - #[inline(always)] - pub fn pin_11_en(&mut self) -> Pin11EnW { - Pin11EnW::new(self, 11) - } - #[doc = "Bit 12 - LCD Pin 12 Enable"] - #[inline(always)] - pub fn pin_12_en(&mut self) -> Pin12EnW { - Pin12EnW::new(self, 12) - } - #[doc = "Bit 13 - LCD Pin 13 Enable"] - #[inline(always)] - pub fn pin_13_en(&mut self) -> Pin13EnW { - Pin13EnW::new(self, 13) - } - #[doc = "Bit 14 - LCD Pin 14 Enable"] - #[inline(always)] - pub fn pin_14_en(&mut self) -> Pin14EnW { - Pin14EnW::new(self, 14) - } - #[doc = "Bit 15 - LCD Pin 15 Enable"] - #[inline(always)] - pub fn pin_15_en(&mut self) -> Pin15EnW { - Pin15EnW::new(self, 15) - } - #[doc = "Bit 16 - LCD Pin 16 Enable"] - #[inline(always)] - pub fn pin_16_en(&mut self) -> Pin16EnW { - Pin16EnW::new(self, 16) - } - #[doc = "Bit 17 - LCD Pin 17 Enable"] - #[inline(always)] - pub fn pin_17_en(&mut self) -> Pin17EnW { - Pin17EnW::new(self, 17) - } - #[doc = "Bit 18 - LCD Pin 18 Enable"] - #[inline(always)] - pub fn pin_18_en(&mut self) -> Pin18EnW { - Pin18EnW::new(self, 18) - } - #[doc = "Bit 19 - LCD Pin 19 Enable"] - #[inline(always)] - pub fn pin_19_en(&mut self) -> Pin19EnW { - Pin19EnW::new(self, 19) - } - #[doc = "Bit 20 - LCD Pin 20 Enable"] - #[inline(always)] - pub fn pin_20_en(&mut self) -> Pin20EnW { - Pin20EnW::new(self, 20) - } - #[doc = "Bit 21 - LCD Pin 21 Enable"] - #[inline(always)] - pub fn pin_21_en(&mut self) -> Pin21EnW { - Pin21EnW::new(self, 21) - } - #[doc = "Bit 22 - LCD Pin 22 Enable"] - #[inline(always)] - pub fn pin_22_en(&mut self) -> Pin22EnW { - Pin22EnW::new(self, 22) - } - #[doc = "Bit 23 - LCD Pin 23 Enable"] - #[inline(always)] - pub fn pin_23_en(&mut self) -> Pin23EnW { - Pin23EnW::new(self, 23) - } - #[doc = "Bit 24 - LCD Pin 24 Enable"] - #[inline(always)] - pub fn pin_24_en(&mut self) -> Pin24EnW { - Pin24EnW::new(self, 24) - } - #[doc = "Bit 25 - LCD Pin 25 Enable"] - #[inline(always)] - pub fn pin_25_en(&mut self) -> Pin25EnW { - Pin25EnW::new(self, 25) - } - #[doc = "Bit 26 - LCD Pin 26 Enable"] - #[inline(always)] - pub fn pin_26_en(&mut self) -> Pin26EnW { - Pin26EnW::new(self, 26) - } - #[doc = "Bit 27 - LCD Pin 27 Enable"] - #[inline(always)] - pub fn pin_27_en(&mut self) -> Pin27EnW { - Pin27EnW::new(self, 27) - } - #[doc = "Bit 28 - LCD Pin 28 Enable"] - #[inline(always)] - pub fn pin_28_en(&mut self) -> Pin28EnW { - Pin28EnW::new(self, 28) - } - #[doc = "Bit 29 - LCD Pin 29 Enable"] - #[inline(always)] - pub fn pin_29_en(&mut self) -> Pin29EnW { - Pin29EnW::new(self, 29) - } - #[doc = "Bit 30 - LCD Pin 30 Enable"] - #[inline(always)] - pub fn pin_30_en(&mut self) -> Pin30EnW { - Pin30EnW::new(self, 30) - } - #[doc = "Bit 31 - LCD Pin 31 Enable"] - #[inline(always)] - pub fn pin_31_en(&mut self) -> Pin31EnW { - Pin31EnW::new(self, 31) - } -} -#[doc = "LCD Pin Enable Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdPen0Spec; -impl crate::RegisterSpec for LcdPen0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_pen0::R`](R) reader structure"] -impl crate::Readable for LcdPen0Spec {} -#[doc = "`write(|w| ..)` method takes [`lcd_pen0::W`](W) writer structure"] -impl crate::Writable for LcdPen0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCD_PEN0 to value 0"] -impl crate::Resettable for LcdPen0Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_pen1.rs b/mcxa276-pac/src/slcd0/lcd_pen1.rs deleted file mode 100644 index 230e1df46..000000000 --- a/mcxa276-pac/src/slcd0/lcd_pen1.rs +++ /dev/null @@ -1,1029 +0,0 @@ -#[doc = "Register `LCD_PEN1` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_PEN1` writer"] -pub type W = crate::W; -#[doc = "LCD Pin 32 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin32En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin32En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_32_EN` reader - LCD Pin 32 Enable"] -pub type Pin32EnR = crate::BitReader; -impl Pin32EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin32En { - match self.bits { - false => Pin32En::Disable, - true => Pin32En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin32En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin32En::Enable - } -} -#[doc = "Field `PIN_32_EN` writer - LCD Pin 32 Enable"] -pub type Pin32EnW<'a, REG> = crate::BitWriter<'a, REG, Pin32En>; -impl<'a, REG> Pin32EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin32En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin32En::Enable) - } -} -#[doc = "LCD Pin 33 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin33En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin33En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_33_EN` reader - LCD Pin 33 Enable"] -pub type Pin33EnR = crate::BitReader; -impl Pin33EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin33En { - match self.bits { - false => Pin33En::Disable, - true => Pin33En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin33En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin33En::Enable - } -} -#[doc = "Field `PIN_33_EN` writer - LCD Pin 33 Enable"] -pub type Pin33EnW<'a, REG> = crate::BitWriter<'a, REG, Pin33En>; -impl<'a, REG> Pin33EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin33En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin33En::Enable) - } -} -#[doc = "LCD Pin 34 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin34En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin34En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_34_EN` reader - LCD Pin 34 Enable"] -pub type Pin34EnR = crate::BitReader; -impl Pin34EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin34En { - match self.bits { - false => Pin34En::Disable, - true => Pin34En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin34En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin34En::Enable - } -} -#[doc = "Field `PIN_34_EN` writer - LCD Pin 34 Enable"] -pub type Pin34EnW<'a, REG> = crate::BitWriter<'a, REG, Pin34En>; -impl<'a, REG> Pin34EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin34En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin34En::Enable) - } -} -#[doc = "LCD Pin 35 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin35En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin35En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_35_EN` reader - LCD Pin 35 Enable"] -pub type Pin35EnR = crate::BitReader; -impl Pin35EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin35En { - match self.bits { - false => Pin35En::Disable, - true => Pin35En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin35En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin35En::Enable - } -} -#[doc = "Field `PIN_35_EN` writer - LCD Pin 35 Enable"] -pub type Pin35EnW<'a, REG> = crate::BitWriter<'a, REG, Pin35En>; -impl<'a, REG> Pin35EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin35En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin35En::Enable) - } -} -#[doc = "LCD Pin 36 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin36En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin36En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_36_EN` reader - LCD Pin 36 Enable"] -pub type Pin36EnR = crate::BitReader; -impl Pin36EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin36En { - match self.bits { - false => Pin36En::Disable, - true => Pin36En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin36En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin36En::Enable - } -} -#[doc = "Field `PIN_36_EN` writer - LCD Pin 36 Enable"] -pub type Pin36EnW<'a, REG> = crate::BitWriter<'a, REG, Pin36En>; -impl<'a, REG> Pin36EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin36En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin36En::Enable) - } -} -#[doc = "LCD Pin 37 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin37En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin37En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_37_EN` reader - LCD Pin 37 Enable"] -pub type Pin37EnR = crate::BitReader; -impl Pin37EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin37En { - match self.bits { - false => Pin37En::Disable, - true => Pin37En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin37En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin37En::Enable - } -} -#[doc = "Field `PIN_37_EN` writer - LCD Pin 37 Enable"] -pub type Pin37EnW<'a, REG> = crate::BitWriter<'a, REG, Pin37En>; -impl<'a, REG> Pin37EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin37En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin37En::Enable) - } -} -#[doc = "LCD Pin 38 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin38En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin38En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_38_EN` reader - LCD Pin 38 Enable"] -pub type Pin38EnR = crate::BitReader; -impl Pin38EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin38En { - match self.bits { - false => Pin38En::Disable, - true => Pin38En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin38En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin38En::Enable - } -} -#[doc = "Field `PIN_38_EN` writer - LCD Pin 38 Enable"] -pub type Pin38EnW<'a, REG> = crate::BitWriter<'a, REG, Pin38En>; -impl<'a, REG> Pin38EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin38En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin38En::Enable) - } -} -#[doc = "LCD Pin 39 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin39En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin39En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_39_EN` reader - LCD Pin 39 Enable"] -pub type Pin39EnR = crate::BitReader; -impl Pin39EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin39En { - match self.bits { - false => Pin39En::Disable, - true => Pin39En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin39En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin39En::Enable - } -} -#[doc = "Field `PIN_39_EN` writer - LCD Pin 39 Enable"] -pub type Pin39EnW<'a, REG> = crate::BitWriter<'a, REG, Pin39En>; -impl<'a, REG> Pin39EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin39En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin39En::Enable) - } -} -#[doc = "LCD Pin 40 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin40En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin40En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_40_EN` reader - LCD Pin 40 Enable"] -pub type Pin40EnR = crate::BitReader; -impl Pin40EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin40En { - match self.bits { - false => Pin40En::Disable, - true => Pin40En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin40En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin40En::Enable - } -} -#[doc = "Field `PIN_40_EN` writer - LCD Pin 40 Enable"] -pub type Pin40EnW<'a, REG> = crate::BitWriter<'a, REG, Pin40En>; -impl<'a, REG> Pin40EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin40En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin40En::Enable) - } -} -#[doc = "LCD Pin 41 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin41En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin41En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_41_EN` reader - LCD Pin 41 Enable"] -pub type Pin41EnR = crate::BitReader; -impl Pin41EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin41En { - match self.bits { - false => Pin41En::Disable, - true => Pin41En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin41En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin41En::Enable - } -} -#[doc = "Field `PIN_41_EN` writer - LCD Pin 41 Enable"] -pub type Pin41EnW<'a, REG> = crate::BitWriter<'a, REG, Pin41En>; -impl<'a, REG> Pin41EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin41En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin41En::Enable) - } -} -#[doc = "LCD Pin 42 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin42En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin42En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_42_EN` reader - LCD Pin 42 Enable"] -pub type Pin42EnR = crate::BitReader; -impl Pin42EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin42En { - match self.bits { - false => Pin42En::Disable, - true => Pin42En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin42En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin42En::Enable - } -} -#[doc = "Field `PIN_42_EN` writer - LCD Pin 42 Enable"] -pub type Pin42EnW<'a, REG> = crate::BitWriter<'a, REG, Pin42En>; -impl<'a, REG> Pin42EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin42En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin42En::Enable) - } -} -#[doc = "LCD Pin 43 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin43En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin43En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_43_EN` reader - LCD Pin 43 Enable"] -pub type Pin43EnR = crate::BitReader; -impl Pin43EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin43En { - match self.bits { - false => Pin43En::Disable, - true => Pin43En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin43En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin43En::Enable - } -} -#[doc = "Field `PIN_43_EN` writer - LCD Pin 43 Enable"] -pub type Pin43EnW<'a, REG> = crate::BitWriter<'a, REG, Pin43En>; -impl<'a, REG> Pin43EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin43En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin43En::Enable) - } -} -#[doc = "LCD Pin 44 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin44En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin44En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_44_EN` reader - LCD Pin 44 Enable"] -pub type Pin44EnR = crate::BitReader; -impl Pin44EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin44En { - match self.bits { - false => Pin44En::Disable, - true => Pin44En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin44En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin44En::Enable - } -} -#[doc = "Field `PIN_44_EN` writer - LCD Pin 44 Enable"] -pub type Pin44EnW<'a, REG> = crate::BitWriter<'a, REG, Pin44En>; -impl<'a, REG> Pin44EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin44En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin44En::Enable) - } -} -#[doc = "LCD Pin 45 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin45En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin45En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_45_EN` reader - LCD Pin 45 Enable"] -pub type Pin45EnR = crate::BitReader; -impl Pin45EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin45En { - match self.bits { - false => Pin45En::Disable, - true => Pin45En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin45En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin45En::Enable - } -} -#[doc = "Field `PIN_45_EN` writer - LCD Pin 45 Enable"] -pub type Pin45EnW<'a, REG> = crate::BitWriter<'a, REG, Pin45En>; -impl<'a, REG> Pin45EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin45En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin45En::Enable) - } -} -#[doc = "LCD Pin 46 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin46En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin46En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_46_EN` reader - LCD Pin 46 Enable"] -pub type Pin46EnR = crate::BitReader; -impl Pin46EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin46En { - match self.bits { - false => Pin46En::Disable, - true => Pin46En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin46En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin46En::Enable - } -} -#[doc = "Field `PIN_46_EN` writer - LCD Pin 46 Enable"] -pub type Pin46EnW<'a, REG> = crate::BitWriter<'a, REG, Pin46En>; -impl<'a, REG> Pin46EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin46En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin46En::Enable) - } -} -#[doc = "LCD Pin 47 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pin47En { - #[doc = "0: Pin Disable"] - Disable = 0, - #[doc = "1: Pin Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pin47En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIN_47_EN` reader - LCD Pin 47 Enable"] -pub type Pin47EnR = crate::BitReader; -impl Pin47EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pin47En { - match self.bits { - false => Pin47En::Disable, - true => Pin47En::Enable, - } - } - #[doc = "Pin Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Pin47En::Disable - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Pin47En::Enable - } -} -#[doc = "Field `PIN_47_EN` writer - LCD Pin 47 Enable"] -pub type Pin47EnW<'a, REG> = crate::BitWriter<'a, REG, Pin47En>; -impl<'a, REG> Pin47EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Pin47En::Disable) - } - #[doc = "Pin Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Pin47En::Enable) - } -} -impl R { - #[doc = "Bit 0 - LCD Pin 32 Enable"] - #[inline(always)] - pub fn pin_32_en(&self) -> Pin32EnR { - Pin32EnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - LCD Pin 33 Enable"] - #[inline(always)] - pub fn pin_33_en(&self) -> Pin33EnR { - Pin33EnR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - LCD Pin 34 Enable"] - #[inline(always)] - pub fn pin_34_en(&self) -> Pin34EnR { - Pin34EnR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - LCD Pin 35 Enable"] - #[inline(always)] - pub fn pin_35_en(&self) -> Pin35EnR { - Pin35EnR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - LCD Pin 36 Enable"] - #[inline(always)] - pub fn pin_36_en(&self) -> Pin36EnR { - Pin36EnR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - LCD Pin 37 Enable"] - #[inline(always)] - pub fn pin_37_en(&self) -> Pin37EnR { - Pin37EnR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - LCD Pin 38 Enable"] - #[inline(always)] - pub fn pin_38_en(&self) -> Pin38EnR { - Pin38EnR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - LCD Pin 39 Enable"] - #[inline(always)] - pub fn pin_39_en(&self) -> Pin39EnR { - Pin39EnR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - LCD Pin 40 Enable"] - #[inline(always)] - pub fn pin_40_en(&self) -> Pin40EnR { - Pin40EnR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - LCD Pin 41 Enable"] - #[inline(always)] - pub fn pin_41_en(&self) -> Pin41EnR { - Pin41EnR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - LCD Pin 42 Enable"] - #[inline(always)] - pub fn pin_42_en(&self) -> Pin42EnR { - Pin42EnR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - LCD Pin 43 Enable"] - #[inline(always)] - pub fn pin_43_en(&self) -> Pin43EnR { - Pin43EnR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - LCD Pin 44 Enable"] - #[inline(always)] - pub fn pin_44_en(&self) -> Pin44EnR { - Pin44EnR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - LCD Pin 45 Enable"] - #[inline(always)] - pub fn pin_45_en(&self) -> Pin45EnR { - Pin45EnR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - LCD Pin 46 Enable"] - #[inline(always)] - pub fn pin_46_en(&self) -> Pin46EnR { - Pin46EnR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - LCD Pin 47 Enable"] - #[inline(always)] - pub fn pin_47_en(&self) -> Pin47EnR { - Pin47EnR::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LCD Pin 32 Enable"] - #[inline(always)] - pub fn pin_32_en(&mut self) -> Pin32EnW { - Pin32EnW::new(self, 0) - } - #[doc = "Bit 1 - LCD Pin 33 Enable"] - #[inline(always)] - pub fn pin_33_en(&mut self) -> Pin33EnW { - Pin33EnW::new(self, 1) - } - #[doc = "Bit 2 - LCD Pin 34 Enable"] - #[inline(always)] - pub fn pin_34_en(&mut self) -> Pin34EnW { - Pin34EnW::new(self, 2) - } - #[doc = "Bit 3 - LCD Pin 35 Enable"] - #[inline(always)] - pub fn pin_35_en(&mut self) -> Pin35EnW { - Pin35EnW::new(self, 3) - } - #[doc = "Bit 4 - LCD Pin 36 Enable"] - #[inline(always)] - pub fn pin_36_en(&mut self) -> Pin36EnW { - Pin36EnW::new(self, 4) - } - #[doc = "Bit 5 - LCD Pin 37 Enable"] - #[inline(always)] - pub fn pin_37_en(&mut self) -> Pin37EnW { - Pin37EnW::new(self, 5) - } - #[doc = "Bit 6 - LCD Pin 38 Enable"] - #[inline(always)] - pub fn pin_38_en(&mut self) -> Pin38EnW { - Pin38EnW::new(self, 6) - } - #[doc = "Bit 7 - LCD Pin 39 Enable"] - #[inline(always)] - pub fn pin_39_en(&mut self) -> Pin39EnW { - Pin39EnW::new(self, 7) - } - #[doc = "Bit 8 - LCD Pin 40 Enable"] - #[inline(always)] - pub fn pin_40_en(&mut self) -> Pin40EnW { - Pin40EnW::new(self, 8) - } - #[doc = "Bit 9 - LCD Pin 41 Enable"] - #[inline(always)] - pub fn pin_41_en(&mut self) -> Pin41EnW { - Pin41EnW::new(self, 9) - } - #[doc = "Bit 10 - LCD Pin 42 Enable"] - #[inline(always)] - pub fn pin_42_en(&mut self) -> Pin42EnW { - Pin42EnW::new(self, 10) - } - #[doc = "Bit 11 - LCD Pin 43 Enable"] - #[inline(always)] - pub fn pin_43_en(&mut self) -> Pin43EnW { - Pin43EnW::new(self, 11) - } - #[doc = "Bit 12 - LCD Pin 44 Enable"] - #[inline(always)] - pub fn pin_44_en(&mut self) -> Pin44EnW { - Pin44EnW::new(self, 12) - } - #[doc = "Bit 13 - LCD Pin 45 Enable"] - #[inline(always)] - pub fn pin_45_en(&mut self) -> Pin45EnW { - Pin45EnW::new(self, 13) - } - #[doc = "Bit 14 - LCD Pin 46 Enable"] - #[inline(always)] - pub fn pin_46_en(&mut self) -> Pin46EnW { - Pin46EnW::new(self, 14) - } - #[doc = "Bit 15 - LCD Pin 47 Enable"] - #[inline(always)] - pub fn pin_47_en(&mut self) -> Pin47EnW { - Pin47EnW::new(self, 15) - } -} -#[doc = "LCD Pin Enable Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_pen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_pen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdPen1Spec; -impl crate::RegisterSpec for LcdPen1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_pen1::R`](R) reader structure"] -impl crate::Readable for LcdPen1Spec {} -#[doc = "`write(|w| ..)` method takes [`lcd_pen1::W`](W) writer structure"] -impl crate::Writable for LcdPen1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCD_PEN1 to value 0"] -impl crate::Resettable for LcdPen1Spec {} diff --git a/mcxa276-pac/src/slcd0/lcd_wfto.rs b/mcxa276-pac/src/slcd0/lcd_wfto.rs deleted file mode 100644 index 5c21b06c8..000000000 --- a/mcxa276-pac/src/slcd0/lcd_wfto.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `LCD_WFTO[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `LCD_WFTO[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `WF0` reader - Waveform Pin 0"] -pub type Wf0R = crate::FieldReader; -#[doc = "Field `WF0` writer - Waveform Pin 0"] -pub type Wf0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `WF1` reader - Waveform Pin 1"] -pub type Wf1R = crate::FieldReader; -#[doc = "Field `WF1` writer - Waveform Pin 1"] -pub type Wf1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `WF2` reader - Waveform Pin 2"] -pub type Wf2R = crate::FieldReader; -#[doc = "Field `WF2` writer - Waveform Pin 2"] -pub type Wf2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `WF3` reader - Waveform Pin 3"] -pub type Wf3R = crate::FieldReader; -#[doc = "Field `WF3` writer - Waveform Pin 3"] -pub type Wf3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Waveform Pin 0"] - #[inline(always)] - pub fn wf0(&self) -> Wf0R { - Wf0R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Waveform Pin 1"] - #[inline(always)] - pub fn wf1(&self) -> Wf1R { - Wf1R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Waveform Pin 2"] - #[inline(always)] - pub fn wf2(&self) -> Wf2R { - Wf2R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Waveform Pin 3"] - #[inline(always)] - pub fn wf3(&self) -> Wf3R { - Wf3R::new(((self.bits >> 24) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Waveform Pin 0"] - #[inline(always)] - pub fn wf0(&mut self) -> Wf0W { - Wf0W::new(self, 0) - } - #[doc = "Bits 8:15 - Waveform Pin 1"] - #[inline(always)] - pub fn wf1(&mut self) -> Wf1W { - Wf1W::new(self, 8) - } - #[doc = "Bits 16:23 - Waveform Pin 2"] - #[inline(always)] - pub fn wf2(&mut self) -> Wf2W { - Wf2W::new(self, 16) - } - #[doc = "Bits 24:31 - Waveform Pin 3"] - #[inline(always)] - pub fn wf3(&mut self) -> Wf3W { - Wf3W::new(self, 24) - } -} -#[doc = "LCD Waveform i * 4 + 3 to i * 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_wfto::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_wfto::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LcdWftoSpec; -impl crate::RegisterSpec for LcdWftoSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lcd_wfto::R`](R) reader structure"] -impl crate::Readable for LcdWftoSpec {} -#[doc = "`write(|w| ..)` method takes [`lcd_wfto::W`](W) writer structure"] -impl crate::Writable for LcdWftoSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LCD_WFTO[%s] to value 0"] -impl crate::Resettable for LcdWftoSpec {} diff --git a/mcxa276-pac/src/smartdma0.rs b/mcxa276-pac/src/smartdma0.rs deleted file mode 100644 index d9f1d5364..000000000 --- a/mcxa276-pac/src/smartdma0.rs +++ /dev/null @@ -1,128 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x20], - bootadr: Bootadr, - ctrl: Ctrl, - pc: Pc, - sp: Sp, - break_addr: BreakAddr, - break_vect: BreakVect, - emer_vect: EmerVect, - emer_sel: EmerSel, - arm2ezh: Arm2ezh, - ezh2arm: Ezh2arm, - pendtrap: Pendtrap, -} -impl RegisterBlock { - #[doc = "0x20 - Boot Address"] - #[inline(always)] - pub const fn bootadr(&self) -> &Bootadr { - &self.bootadr - } - #[doc = "0x24 - Control"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } - #[doc = "0x28 - Program Counter"] - #[inline(always)] - pub const fn pc(&self) -> &Pc { - &self.pc - } - #[doc = "0x2c - Stack Pointer"] - #[inline(always)] - pub const fn sp(&self) -> &Sp { - &self.sp - } - #[doc = "0x30 - Breakpoint Address"] - #[inline(always)] - pub const fn break_addr(&self) -> &BreakAddr { - &self.break_addr - } - #[doc = "0x34 - Breakpoint Vector"] - #[inline(always)] - pub const fn break_vect(&self) -> &BreakVect { - &self.break_vect - } - #[doc = "0x38 - Emergency Vector"] - #[inline(always)] - pub const fn emer_vect(&self) -> &EmerVect { - &self.emer_vect - } - #[doc = "0x3c - Emergency Select"] - #[inline(always)] - pub const fn emer_sel(&self) -> &EmerSel { - &self.emer_sel - } - #[doc = "0x40 - ARM to EZH Interrupt Control"] - #[inline(always)] - pub const fn arm2ezh(&self) -> &Arm2ezh { - &self.arm2ezh - } - #[doc = "0x44 - EZH to ARM Trigger"] - #[inline(always)] - pub const fn ezh2arm(&self) -> &Ezh2arm { - &self.ezh2arm - } - #[doc = "0x48 - Pending Trap Control"] - #[inline(always)] - pub const fn pendtrap(&self) -> &Pendtrap { - &self.pendtrap - } -} -#[doc = "BOOTADR (rw) register accessor: Boot Address\n\nYou can [`read`](crate::Reg::read) this register and get [`bootadr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootadr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bootadr`] module"] -#[doc(alias = "BOOTADR")] -pub type Bootadr = crate::Reg; -#[doc = "Boot Address"] -pub mod bootadr; -#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "Control"] -pub mod ctrl; -#[doc = "PC (r) register accessor: Program Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`] module"] -#[doc(alias = "PC")] -pub type Pc = crate::Reg; -#[doc = "Program Counter"] -pub mod pc; -#[doc = "SP (r) register accessor: Stack Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sp`] module"] -#[doc(alias = "SP")] -pub type Sp = crate::Reg; -#[doc = "Stack Pointer"] -pub mod sp; -#[doc = "BREAK_ADDR (rw) register accessor: Breakpoint Address\n\nYou can [`read`](crate::Reg::read) this register and get [`break_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@break_addr`] module"] -#[doc(alias = "BREAK_ADDR")] -pub type BreakAddr = crate::Reg; -#[doc = "Breakpoint Address"] -pub mod break_addr; -#[doc = "BREAK_VECT (rw) register accessor: Breakpoint Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`break_vect::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_vect::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@break_vect`] module"] -#[doc(alias = "BREAK_VECT")] -pub type BreakVect = crate::Reg; -#[doc = "Breakpoint Vector"] -pub mod break_vect; -#[doc = "EMER_VECT (rw) register accessor: Emergency Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_vect::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_vect::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emer_vect`] module"] -#[doc(alias = "EMER_VECT")] -pub type EmerVect = crate::Reg; -#[doc = "Emergency Vector"] -pub mod emer_vect; -#[doc = "EMER_SEL (rw) register accessor: Emergency Select\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emer_sel`] module"] -#[doc(alias = "EMER_SEL")] -pub type EmerSel = crate::Reg; -#[doc = "Emergency Select"] -pub mod emer_sel; -#[doc = "ARM2EZH (rw) register accessor: ARM to EZH Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`arm2ezh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arm2ezh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arm2ezh`] module"] -#[doc(alias = "ARM2EZH")] -pub type Arm2ezh = crate::Reg; -#[doc = "ARM to EZH Interrupt Control"] -pub mod arm2ezh; -#[doc = "EZH2ARM (rw) register accessor: EZH to ARM Trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`ezh2arm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ezh2arm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ezh2arm`] module"] -#[doc(alias = "EZH2ARM")] -pub type Ezh2arm = crate::Reg; -#[doc = "EZH to ARM Trigger"] -pub mod ezh2arm; -#[doc = "PENDTRAP (rw) register accessor: Pending Trap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pendtrap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pendtrap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pendtrap`] module"] -#[doc(alias = "PENDTRAP")] -pub type Pendtrap = crate::Reg; -#[doc = "Pending Trap Control"] -pub mod pendtrap; diff --git a/mcxa276-pac/src/smartdma0/arm2ezh.rs b/mcxa276-pac/src/smartdma0/arm2ezh.rs deleted file mode 100644 index 6f7bee621..000000000 --- a/mcxa276-pac/src/smartdma0/arm2ezh.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `ARM2EZH` reader"] -pub type R = crate::R; -#[doc = "Register `ARM2EZH` writer"] -pub type W = crate::W; -#[doc = "Field `IE` reader - Interrupt Enable"] -pub type IeR = crate::FieldReader; -#[doc = "Field `IE` writer - Interrupt Enable"] -pub type IeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `GP` reader - General purpose register bits"] -pub type GpR = crate::FieldReader; -#[doc = "Field `GP` writer - General purpose register bits"] -pub type GpW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; -impl R { - #[doc = "Bits 0:1 - Interrupt Enable"] - #[inline(always)] - pub fn ie(&self) -> IeR { - IeR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:31 - General purpose register bits"] - #[inline(always)] - pub fn gp(&self) -> GpR { - GpR::new((self.bits >> 2) & 0x3fff_ffff) - } -} -impl W { - #[doc = "Bits 0:1 - Interrupt Enable"] - #[inline(always)] - pub fn ie(&mut self) -> IeW { - IeW::new(self, 0) - } - #[doc = "Bits 2:31 - General purpose register bits"] - #[inline(always)] - pub fn gp(&mut self) -> GpW { - GpW::new(self, 2) - } -} -#[doc = "ARM to EZH Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`arm2ezh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arm2ezh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Arm2ezhSpec; -impl crate::RegisterSpec for Arm2ezhSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`arm2ezh::R`](R) reader structure"] -impl crate::Readable for Arm2ezhSpec {} -#[doc = "`write(|w| ..)` method takes [`arm2ezh::W`](W) writer structure"] -impl crate::Writable for Arm2ezhSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ARM2EZH to value 0"] -impl crate::Resettable for Arm2ezhSpec {} diff --git a/mcxa276-pac/src/smartdma0/bootadr.rs b/mcxa276-pac/src/smartdma0/bootadr.rs deleted file mode 100644 index 630b08c75..000000000 --- a/mcxa276-pac/src/smartdma0/bootadr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `BOOTADR` reader"] -pub type R = crate::R; -#[doc = "Register `BOOTADR` writer"] -pub type W = crate::W; -#[doc = "Field `ADDR` reader - 32-bit boot address, the boot address should be 4-byte aligned."] -pub type AddrR = crate::FieldReader; -#[doc = "Field `ADDR` writer - 32-bit boot address, the boot address should be 4-byte aligned."] -pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; -impl R { - #[doc = "Bits 2:31 - 32-bit boot address, the boot address should be 4-byte aligned."] - #[inline(always)] - pub fn addr(&self) -> AddrR { - AddrR::new((self.bits >> 2) & 0x3fff_ffff) - } -} -impl W { - #[doc = "Bits 2:31 - 32-bit boot address, the boot address should be 4-byte aligned."] - #[inline(always)] - pub fn addr(&mut self) -> AddrW { - AddrW::new(self, 2) - } -} -#[doc = "Boot Address\n\nYou can [`read`](crate::Reg::read) this register and get [`bootadr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootadr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct BootadrSpec; -impl crate::RegisterSpec for BootadrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`bootadr::R`](R) reader structure"] -impl crate::Readable for BootadrSpec {} -#[doc = "`write(|w| ..)` method takes [`bootadr::W`](W) writer structure"] -impl crate::Writable for BootadrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BOOTADR to value 0"] -impl crate::Resettable for BootadrSpec {} diff --git a/mcxa276-pac/src/smartdma0/break_addr.rs b/mcxa276-pac/src/smartdma0/break_addr.rs deleted file mode 100644 index 2b303a7f9..000000000 --- a/mcxa276-pac/src/smartdma0/break_addr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `BREAK_ADDR` reader"] -pub type R = crate::R; -#[doc = "Register `BREAK_ADDR` writer"] -pub type W = crate::W; -#[doc = "Field `ADDR` reader - 32-bit address to swap to EZHB_BREAK_VECT location"] -pub type AddrR = crate::FieldReader; -#[doc = "Field `ADDR` writer - 32-bit address to swap to EZHB_BREAK_VECT location"] -pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; -impl R { - #[doc = "Bits 2:31 - 32-bit address to swap to EZHB_BREAK_VECT location"] - #[inline(always)] - pub fn addr(&self) -> AddrR { - AddrR::new((self.bits >> 2) & 0x3fff_ffff) - } -} -impl W { - #[doc = "Bits 2:31 - 32-bit address to swap to EZHB_BREAK_VECT location"] - #[inline(always)] - pub fn addr(&mut self) -> AddrW { - AddrW::new(self, 2) - } -} -#[doc = "Breakpoint Address\n\nYou can [`read`](crate::Reg::read) this register and get [`break_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct BreakAddrSpec; -impl crate::RegisterSpec for BreakAddrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`break_addr::R`](R) reader structure"] -impl crate::Readable for BreakAddrSpec {} -#[doc = "`write(|w| ..)` method takes [`break_addr::W`](W) writer structure"] -impl crate::Writable for BreakAddrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BREAK_ADDR to value 0"] -impl crate::Resettable for BreakAddrSpec {} diff --git a/mcxa276-pac/src/smartdma0/break_vect.rs b/mcxa276-pac/src/smartdma0/break_vect.rs deleted file mode 100644 index de7e8439f..000000000 --- a/mcxa276-pac/src/smartdma0/break_vect.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `BREAK_VECT` reader"] -pub type R = crate::R; -#[doc = "Register `BREAK_VECT` writer"] -pub type W = crate::W; -#[doc = "Field `VEC` reader - Vector address of user debug routine."] -pub type VecR = crate::FieldReader; -#[doc = "Field `VEC` writer - Vector address of user debug routine."] -pub type VecW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; -impl R { - #[doc = "Bits 2:31 - Vector address of user debug routine."] - #[inline(always)] - pub fn vec(&self) -> VecR { - VecR::new((self.bits >> 2) & 0x3fff_ffff) - } -} -impl W { - #[doc = "Bits 2:31 - Vector address of user debug routine."] - #[inline(always)] - pub fn vec(&mut self) -> VecW { - VecW::new(self, 2) - } -} -#[doc = "Breakpoint Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`break_vect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`break_vect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct BreakVectSpec; -impl crate::RegisterSpec for BreakVectSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`break_vect::R`](R) reader structure"] -impl crate::Readable for BreakVectSpec {} -#[doc = "`write(|w| ..)` method takes [`break_vect::W`](W) writer structure"] -impl crate::Writable for BreakVectSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BREAK_VECT to value 0"] -impl crate::Resettable for BreakVectSpec {} diff --git a/mcxa276-pac/src/smartdma0/ctrl.rs b/mcxa276-pac/src/smartdma0/ctrl.rs deleted file mode 100644 index 625179c7e..000000000 --- a/mcxa276-pac/src/smartdma0/ctrl.rs +++ /dev/null @@ -1,105 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `START` reader - Start Bit Ignition"] -pub type StartR = crate::BitReader; -#[doc = "Field `START` writer - Start Bit Ignition"] -pub type StartW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EXF` reader - External Flag"] -pub type ExfR = crate::BitReader; -#[doc = "Field `EXF` writer - External Flag"] -pub type ExfW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ERRDIS` reader - Error Disable"] -pub type ErrdisR = crate::BitReader; -#[doc = "Field `ERRDIS` writer - Error Disable"] -pub type ErrdisW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BUFEN` reader - Buffer Enable"] -pub type BufenR = crate::BitReader; -#[doc = "Field `BUFEN` writer - Buffer Enable"] -pub type BufenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SYNCEN` reader - Sync Enable"] -pub type SyncenR = crate::BitReader; -#[doc = "Field `SYNCEN` writer - Sync Enable"] -pub type SyncenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `WKEY` reader - Write Key"] -pub type WkeyR = crate::FieldReader; -#[doc = "Field `WKEY` writer - Write Key"] -pub type WkeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bit 0 - Start Bit Ignition"] - #[inline(always)] - pub fn start(&self) -> StartR { - StartR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - External Flag"] - #[inline(always)] - pub fn exf(&self) -> ExfR { - ExfR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Error Disable"] - #[inline(always)] - pub fn errdis(&self) -> ErrdisR { - ErrdisR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Buffer Enable"] - #[inline(always)] - pub fn bufen(&self) -> BufenR { - BufenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Sync Enable"] - #[inline(always)] - pub fn syncen(&self) -> SyncenR { - SyncenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 16:31 - Write Key"] - #[inline(always)] - pub fn wkey(&self) -> WkeyR { - WkeyR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bit 0 - Start Bit Ignition"] - #[inline(always)] - pub fn start(&mut self) -> StartW { - StartW::new(self, 0) - } - #[doc = "Bit 1 - External Flag"] - #[inline(always)] - pub fn exf(&mut self) -> ExfW { - ExfW::new(self, 1) - } - #[doc = "Bit 2 - Error Disable"] - #[inline(always)] - pub fn errdis(&mut self) -> ErrdisW { - ErrdisW::new(self, 2) - } - #[doc = "Bit 3 - Buffer Enable"] - #[inline(always)] - pub fn bufen(&mut self) -> BufenW { - BufenW::new(self, 3) - } - #[doc = "Bit 4 - Sync Enable"] - #[inline(always)] - pub fn syncen(&mut self) -> SyncenW { - SyncenW::new(self, 4) - } - #[doc = "Bits 16:31 - Write Key"] - #[inline(always)] - pub fn wkey(&mut self) -> WkeyW { - WkeyW::new(self, 16) - } -} -#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/smartdma0/emer_sel.rs b/mcxa276-pac/src/smartdma0/emer_sel.rs deleted file mode 100644 index d91342fb6..000000000 --- a/mcxa276-pac/src/smartdma0/emer_sel.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `EMER_SEL` reader"] -pub type R = crate::R; -#[doc = "Register `EMER_SEL` writer"] -pub type W = crate::W; -#[doc = "Field `EN` reader - Emergency code routine"] -pub type EnR = crate::BitReader; -#[doc = "Field `EN` writer - Emergency code routine"] -pub type EnW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RQ` reader - Software emergency request"] -pub type RqR = crate::BitReader; -#[doc = "Field `RQ` writer - Software emergency request"] -pub type RqW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 8 - Emergency code routine"] - #[inline(always)] - pub fn en(&self) -> EnR { - EnR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Software emergency request"] - #[inline(always)] - pub fn rq(&self) -> RqR { - RqR::new(((self.bits >> 9) & 1) != 0) - } -} -impl W { - #[doc = "Bit 8 - Emergency code routine"] - #[inline(always)] - pub fn en(&mut self) -> EnW { - EnW::new(self, 8) - } - #[doc = "Bit 9 - Software emergency request"] - #[inline(always)] - pub fn rq(&mut self) -> RqW { - RqW::new(self, 9) - } -} -#[doc = "Emergency Select\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EmerSelSpec; -impl crate::RegisterSpec for EmerSelSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`emer_sel::R`](R) reader structure"] -impl crate::Readable for EmerSelSpec {} -#[doc = "`write(|w| ..)` method takes [`emer_sel::W`](W) writer structure"] -impl crate::Writable for EmerSelSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EMER_SEL to value 0"] -impl crate::Resettable for EmerSelSpec {} diff --git a/mcxa276-pac/src/smartdma0/emer_vect.rs b/mcxa276-pac/src/smartdma0/emer_vect.rs deleted file mode 100644 index d9e88e767..000000000 --- a/mcxa276-pac/src/smartdma0/emer_vect.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `EMER_VECT` reader"] -pub type R = crate::R; -#[doc = "Register `EMER_VECT` writer"] -pub type W = crate::W; -#[doc = "Field `VEC` reader - Vector address of emergency code routine"] -pub type VecR = crate::FieldReader; -#[doc = "Field `VEC` writer - Vector address of emergency code routine"] -pub type VecW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; -impl R { - #[doc = "Bits 2:31 - Vector address of emergency code routine"] - #[inline(always)] - pub fn vec(&self) -> VecR { - VecR::new((self.bits >> 2) & 0x3fff_ffff) - } -} -impl W { - #[doc = "Bits 2:31 - Vector address of emergency code routine"] - #[inline(always)] - pub fn vec(&mut self) -> VecW { - VecW::new(self, 2) - } -} -#[doc = "Emergency Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`emer_vect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emer_vect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EmerVectSpec; -impl crate::RegisterSpec for EmerVectSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`emer_vect::R`](R) reader structure"] -impl crate::Readable for EmerVectSpec {} -#[doc = "`write(|w| ..)` method takes [`emer_vect::W`](W) writer structure"] -impl crate::Writable for EmerVectSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EMER_VECT to value 0"] -impl crate::Resettable for EmerVectSpec {} diff --git a/mcxa276-pac/src/smartdma0/ezh2arm.rs b/mcxa276-pac/src/smartdma0/ezh2arm.rs deleted file mode 100644 index 2bebdcf10..000000000 --- a/mcxa276-pac/src/smartdma0/ezh2arm.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `EZH2ARM` reader"] -pub type R = crate::R; -#[doc = "Register `EZH2ARM` writer"] -pub type W = crate::W; -#[doc = "Field `GP` reader - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] -pub type GpR = crate::FieldReader; -#[doc = "Field `GP` writer - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] -pub type GpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] - #[inline(always)] - pub fn gp(&self) -> GpR { - GpR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH \\[1:0\\] == 2h"] - #[inline(always)] - pub fn gp(&mut self) -> GpW { - GpW::new(self, 0) - } -} -#[doc = "EZH to ARM Trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`ezh2arm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ezh2arm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ezh2armSpec; -impl crate::RegisterSpec for Ezh2armSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ezh2arm::R`](R) reader structure"] -impl crate::Readable for Ezh2armSpec {} -#[doc = "`write(|w| ..)` method takes [`ezh2arm::W`](W) writer structure"] -impl crate::Writable for Ezh2armSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EZH2ARM to value 0"] -impl crate::Resettable for Ezh2armSpec {} diff --git a/mcxa276-pac/src/smartdma0/pc.rs b/mcxa276-pac/src/smartdma0/pc.rs deleted file mode 100644 index 17fa6fb8b..000000000 --- a/mcxa276-pac/src/smartdma0/pc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `PC` reader"] -pub type R = crate::R; -#[doc = "Field `PC` reader - Program Counter"] -pub type PcR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Program Counter"] - #[inline(always)] - pub fn pc(&self) -> PcR { - PcR::new(self.bits) - } -} -#[doc = "Program Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PcSpec; -impl crate::RegisterSpec for PcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pc::R`](R) reader structure"] -impl crate::Readable for PcSpec {} -#[doc = "`reset()` method sets PC to value 0"] -impl crate::Resettable for PcSpec {} diff --git a/mcxa276-pac/src/smartdma0/pendtrap.rs b/mcxa276-pac/src/smartdma0/pendtrap.rs deleted file mode 100644 index 5bd3d0e4a..000000000 --- a/mcxa276-pac/src/smartdma0/pendtrap.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `PENDTRAP` reader"] -pub type R = crate::R; -#[doc = "Register `PENDTRAP` writer"] -pub type W = crate::W; -#[doc = "Field `STATUS` reader - Status Flag or Pending Trap Request"] -pub type StatusR = crate::FieldReader; -#[doc = "Field `STATUS` writer - Status Flag or Pending Trap Request"] -pub type StatusW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `POL` reader - Polarity"] -pub type PolR = crate::FieldReader; -#[doc = "Field `POL` writer - Polarity"] -pub type PolW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `EN` reader - Enable Pending Trap"] -pub type EnR = crate::FieldReader; -#[doc = "Field `EN` writer - Enable Pending Trap"] -pub type EnW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Status Flag or Pending Trap Request"] - #[inline(always)] - pub fn status(&self) -> StatusR { - StatusR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Polarity"] - #[inline(always)] - pub fn pol(&self) -> PolR { - PolR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Enable Pending Trap"] - #[inline(always)] - pub fn en(&self) -> EnR { - EnR::new(((self.bits >> 16) & 0xff) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Status Flag or Pending Trap Request"] - #[inline(always)] - pub fn status(&mut self) -> StatusW { - StatusW::new(self, 0) - } - #[doc = "Bits 8:15 - Polarity"] - #[inline(always)] - pub fn pol(&mut self) -> PolW { - PolW::new(self, 8) - } - #[doc = "Bits 16:23 - Enable Pending Trap"] - #[inline(always)] - pub fn en(&mut self) -> EnW { - EnW::new(self, 16) - } -} -#[doc = "Pending Trap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pendtrap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pendtrap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PendtrapSpec; -impl crate::RegisterSpec for PendtrapSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pendtrap::R`](R) reader structure"] -impl crate::Readable for PendtrapSpec {} -#[doc = "`write(|w| ..)` method takes [`pendtrap::W`](W) writer structure"] -impl crate::Writable for PendtrapSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PENDTRAP to value 0"] -impl crate::Resettable for PendtrapSpec {} diff --git a/mcxa276-pac/src/smartdma0/sp.rs b/mcxa276-pac/src/smartdma0/sp.rs deleted file mode 100644 index 7eb5ed45b..000000000 --- a/mcxa276-pac/src/smartdma0/sp.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SP` reader"] -pub type R = crate::R; -#[doc = "Field `SP` reader - Stack Pointer"] -pub type SpR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Stack Pointer"] - #[inline(always)] - pub fn sp(&self) -> SpR { - SpR::new(self.bits) - } -} -#[doc = "Stack Pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SpSpec; -impl crate::RegisterSpec for SpSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sp::R`](R) reader structure"] -impl crate::Readable for SpSpec {} -#[doc = "`reset()` method sets SP to value 0"] -impl crate::Resettable for SpSpec {} diff --git a/mcxa276-pac/src/spc0.rs b/mcxa276-pac/src/spc0.rs deleted file mode 100644 index 5a9aa7295..000000000 --- a/mcxa276-pac/src/spc0.rs +++ /dev/null @@ -1,214 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x0c], - sc: Sc, - _reserved2: [u8; 0x08], - lpreq_cfg: LpreqCfg, - _reserved3: [u8; 0x10], - pd_status0: PdStatus0, - _reserved4: [u8; 0x0c], - sramctl: Sramctl, - _reserved5: [u8; 0x10], - sramretldo_reftrim: SramretldoReftrim, - sramretldo_cntrl: SramretldoCntrl, - _reserved7: [u8; 0xa4], - active_cfg: ActiveCfg, - active_cfg1: ActiveCfg1, - lp_cfg: LpCfg, - lp_cfg1: LpCfg1, - _reserved11: [u8; 0x10], - lpwkup_delay: LpwkupDelay, - active_vdelay: ActiveVdelay, - _reserved13: [u8; 0x08], - vd_stat: VdStat, - vd_core_cfg: VdCoreCfg, - vd_sys_cfg: VdSysCfg, - _reserved16: [u8; 0x04], - evd_cfg: EvdCfg, - _reserved17: [u8; 0x01bc], - coreldo_cfg: CoreldoCfg, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x10 - Status Control"] - #[inline(always)] - pub const fn sc(&self) -> &Sc { - &self.sc - } - #[doc = "0x1c - Low-Power Request Configuration"] - #[inline(always)] - pub const fn lpreq_cfg(&self) -> &LpreqCfg { - &self.lpreq_cfg - } - #[doc = "0x30 - SPC Power Domain Mode Status"] - #[inline(always)] - pub const fn pd_status0(&self) -> &PdStatus0 { - &self.pd_status0 - } - #[doc = "0x40 - SRAM Control"] - #[inline(always)] - pub const fn sramctl(&self) -> &Sramctl { - &self.sramctl - } - #[doc = "0x54 - SRAM Retention Reference Trim"] - #[inline(always)] - pub const fn sramretldo_reftrim(&self) -> &SramretldoReftrim { - &self.sramretldo_reftrim - } - #[doc = "0x58 - SRAM Retention LDO Control"] - #[inline(always)] - pub const fn sramretldo_cntrl(&self) -> &SramretldoCntrl { - &self.sramretldo_cntrl - } - #[doc = "0x100 - Active Power Mode Configuration"] - #[inline(always)] - pub const fn active_cfg(&self) -> &ActiveCfg { - &self.active_cfg - } - #[doc = "0x104 - Active Power Mode Configuration 1"] - #[inline(always)] - pub const fn active_cfg1(&self) -> &ActiveCfg1 { - &self.active_cfg1 - } - #[doc = "0x108 - Low-Power Mode Configuration"] - #[inline(always)] - pub const fn lp_cfg(&self) -> &LpCfg { - &self.lp_cfg - } - #[doc = "0x10c - Low Power Mode Configuration 1"] - #[inline(always)] - pub const fn lp_cfg1(&self) -> &LpCfg1 { - &self.lp_cfg1 - } - #[doc = "0x120 - Low Power Wake-Up Delay"] - #[inline(always)] - pub const fn lpwkup_delay(&self) -> &LpwkupDelay { - &self.lpwkup_delay - } - #[doc = "0x124 - Active Voltage Trim Delay"] - #[inline(always)] - pub const fn active_vdelay(&self) -> &ActiveVdelay { - &self.active_vdelay - } - #[doc = "0x130 - Voltage Detect Status"] - #[inline(always)] - pub const fn vd_stat(&self) -> &VdStat { - &self.vd_stat - } - #[doc = "0x134 - Core Voltage Detect Configuration"] - #[inline(always)] - pub const fn vd_core_cfg(&self) -> &VdCoreCfg { - &self.vd_core_cfg - } - #[doc = "0x138 - System Voltage Detect Configuration"] - #[inline(always)] - pub const fn vd_sys_cfg(&self) -> &VdSysCfg { - &self.vd_sys_cfg - } - #[doc = "0x140 - External Voltage Domain Configuration"] - #[inline(always)] - pub const fn evd_cfg(&self) -> &EvdCfg { - &self.evd_cfg - } - #[doc = "0x300 - LDO_CORE Configuration"] - #[inline(always)] - pub const fn coreldo_cfg(&self) -> &CoreldoCfg { - &self.coreldo_cfg - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "SC (rw) register accessor: Status Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sc`] module"] -#[doc(alias = "SC")] -pub type Sc = crate::Reg; -#[doc = "Status Control"] -pub mod sc; -#[doc = "LPREQ_CFG (rw) register accessor: Low-Power Request Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lpreq_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpreq_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpreq_cfg`] module"] -#[doc(alias = "LPREQ_CFG")] -pub type LpreqCfg = crate::Reg; -#[doc = "Low-Power Request Configuration"] -pub mod lpreq_cfg; -#[doc = "PD_STATUS0 (rw) register accessor: SPC Power Domain Mode Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_status0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_status0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_status0`] module"] -#[doc(alias = "PD_STATUS0")] -pub type PdStatus0 = crate::Reg; -#[doc = "SPC Power Domain Mode Status"] -pub mod pd_status0; -#[doc = "SRAMCTL (rw) register accessor: SRAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sramctl`] module"] -#[doc(alias = "SRAMCTL")] -pub type Sramctl = crate::Reg; -#[doc = "SRAM Control"] -pub mod sramctl; -#[doc = "SRAMRETLDO_REFTRIM (rw) register accessor: SRAM Retention Reference Trim\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_reftrim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_reftrim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sramretldo_reftrim`] module"] -#[doc(alias = "SRAMRETLDO_REFTRIM")] -pub type SramretldoReftrim = crate::Reg; -#[doc = "SRAM Retention Reference Trim"] -pub mod sramretldo_reftrim; -#[doc = "SRAMRETLDO_CNTRL (rw) register accessor: SRAM Retention LDO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_cntrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_cntrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sramretldo_cntrl`] module"] -#[doc(alias = "SRAMRETLDO_CNTRL")] -pub type SramretldoCntrl = crate::Reg; -#[doc = "SRAM Retention LDO Control"] -pub mod sramretldo_cntrl; -#[doc = "ACTIVE_CFG (rw) register accessor: Active Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@active_cfg`] module"] -#[doc(alias = "ACTIVE_CFG")] -pub type ActiveCfg = crate::Reg; -#[doc = "Active Power Mode Configuration"] -pub mod active_cfg; -#[doc = "ACTIVE_CFG1 (rw) register accessor: Active Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@active_cfg1`] module"] -#[doc(alias = "ACTIVE_CFG1")] -pub type ActiveCfg1 = crate::Reg; -#[doc = "Active Power Mode Configuration 1"] -pub mod active_cfg1; -#[doc = "LP_CFG (rw) register accessor: Low-Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cfg`] module"] -#[doc(alias = "LP_CFG")] -pub type LpCfg = crate::Reg; -#[doc = "Low-Power Mode Configuration"] -pub mod lp_cfg; -#[doc = "LP_CFG1 (rw) register accessor: Low Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cfg1`] module"] -#[doc(alias = "LP_CFG1")] -pub type LpCfg1 = crate::Reg; -#[doc = "Low Power Mode Configuration 1"] -pub mod lp_cfg1; -#[doc = "LPWKUP_DELAY (rw) register accessor: Low Power Wake-Up Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`lpwkup_delay::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpwkup_delay::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpwkup_delay`] module"] -#[doc(alias = "LPWKUP_DELAY")] -pub type LpwkupDelay = crate::Reg; -#[doc = "Low Power Wake-Up Delay"] -pub mod lpwkup_delay; -#[doc = "ACTIVE_VDELAY (rw) register accessor: Active Voltage Trim Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`active_vdelay::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_vdelay::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@active_vdelay`] module"] -#[doc(alias = "ACTIVE_VDELAY")] -pub type ActiveVdelay = crate::Reg; -#[doc = "Active Voltage Trim Delay"] -pub mod active_vdelay; -#[doc = "VD_STAT (rw) register accessor: Voltage Detect Status\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_stat`] module"] -#[doc(alias = "VD_STAT")] -pub type VdStat = crate::Reg; -#[doc = "Voltage Detect Status"] -pub mod vd_stat; -#[doc = "VD_CORE_CFG (rw) register accessor: Core Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_core_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_core_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_core_cfg`] module"] -#[doc(alias = "VD_CORE_CFG")] -pub type VdCoreCfg = crate::Reg; -#[doc = "Core Voltage Detect Configuration"] -pub mod vd_core_cfg; -#[doc = "VD_SYS_CFG (rw) register accessor: System Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_sys_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_sys_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_sys_cfg`] module"] -#[doc(alias = "VD_SYS_CFG")] -pub type VdSysCfg = crate::Reg; -#[doc = "System Voltage Detect Configuration"] -pub mod vd_sys_cfg; -#[doc = "EVD_CFG (rw) register accessor: External Voltage Domain Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`evd_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evd_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evd_cfg`] module"] -#[doc(alias = "EVD_CFG")] -pub type EvdCfg = crate::Reg; -#[doc = "External Voltage Domain Configuration"] -pub mod evd_cfg; -#[doc = "CORELDO_CFG (r) register accessor: LDO_CORE Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`coreldo_cfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@coreldo_cfg`] module"] -#[doc(alias = "CORELDO_CFG")] -pub type CoreldoCfg = crate::Reg; -#[doc = "LDO_CORE Configuration"] -pub mod coreldo_cfg; diff --git a/mcxa276-pac/src/spc0/active_cfg.rs b/mcxa276-pac/src/spc0/active_cfg.rs deleted file mode 100644 index 683f63eca..000000000 --- a/mcxa276-pac/src/spc0/active_cfg.rs +++ /dev/null @@ -1,504 +0,0 @@ -#[doc = "Register `ACTIVE_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `ACTIVE_CFG` writer"] -pub type W = crate::W; -#[doc = "LDO_CORE VDD Drive Strength\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoreldoVddDs { - #[doc = "0: Low"] - Low = 0, - #[doc = "1: Normal"] - Normal = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoreldoVddDs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CORELDO_VDD_DS` reader - LDO_CORE VDD Drive Strength"] -pub type CoreldoVddDsR = crate::BitReader; -impl CoreldoVddDsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoreldoVddDs { - match self.bits { - false => CoreldoVddDs::Low, - true => CoreldoVddDs::Normal, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == CoreldoVddDs::Low - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == CoreldoVddDs::Normal - } -} -#[doc = "Field `CORELDO_VDD_DS` writer - LDO_CORE VDD Drive Strength"] -pub type CoreldoVddDsW<'a, REG> = crate::BitWriter<'a, REG, CoreldoVddDs>; -impl<'a, REG> CoreldoVddDsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn low(self) -> &'a mut crate::W { - self.variant(CoreldoVddDs::Low) - } - #[doc = "Normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(CoreldoVddDs::Normal) - } -} -#[doc = "LDO_CORE VDD Regulator Voltage Level\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum CoreldoVddLvl { - #[doc = "1: Regulate to mid voltage (1.0 V)"] - Mid = 1, - #[doc = "2: Regulate to normal voltage (1.1 V)"] - Normal = 2, - #[doc = "3: Regulate to overdrive voltage (1.15 V)"] - Over = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: CoreldoVddLvl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for CoreldoVddLvl { - type Ux = u8; -} -impl crate::IsEnum for CoreldoVddLvl {} -#[doc = "Field `CORELDO_VDD_LVL` reader - LDO_CORE VDD Regulator Voltage Level"] -pub type CoreldoVddLvlR = crate::FieldReader; -impl CoreldoVddLvlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(CoreldoVddLvl::Mid), - 2 => Some(CoreldoVddLvl::Normal), - 3 => Some(CoreldoVddLvl::Over), - _ => None, - } - } - #[doc = "Regulate to mid voltage (1.0 V)"] - #[inline(always)] - pub fn is_mid(&self) -> bool { - *self == CoreldoVddLvl::Mid - } - #[doc = "Regulate to normal voltage (1.1 V)"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == CoreldoVddLvl::Normal - } - #[doc = "Regulate to overdrive voltage (1.15 V)"] - #[inline(always)] - pub fn is_over(&self) -> bool { - *self == CoreldoVddLvl::Over - } -} -#[doc = "Field `CORELDO_VDD_LVL` writer - LDO_CORE VDD Regulator Voltage Level"] -pub type CoreldoVddLvlW<'a, REG> = crate::FieldWriter<'a, REG, 2, CoreldoVddLvl>; -impl<'a, REG> CoreldoVddLvlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Regulate to mid voltage (1.0 V)"] - #[inline(always)] - pub fn mid(self) -> &'a mut crate::W { - self.variant(CoreldoVddLvl::Mid) - } - #[doc = "Regulate to normal voltage (1.1 V)"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(CoreldoVddLvl::Normal) - } - #[doc = "Regulate to overdrive voltage (1.15 V)"] - #[inline(always)] - pub fn over(self) -> &'a mut crate::W { - self.variant(CoreldoVddLvl::Over) - } -} -#[doc = "Bandgap Mode\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Bgmode { - #[doc = "0: Bandgap disabled"] - Bgmode0 = 0, - #[doc = "1: Bandgap enabled, buffer disabled"] - Bgmode01 = 1, - #[doc = "2: Bandgap enabled, buffer enabled"] - Bgmode10 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Bgmode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Bgmode { - type Ux = u8; -} -impl crate::IsEnum for Bgmode {} -#[doc = "Field `BGMODE` reader - Bandgap Mode"] -pub type BgmodeR = crate::FieldReader; -impl BgmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Bgmode::Bgmode0), - 1 => Some(Bgmode::Bgmode01), - 2 => Some(Bgmode::Bgmode10), - _ => None, - } - } - #[doc = "Bandgap disabled"] - #[inline(always)] - pub fn is_bgmode0(&self) -> bool { - *self == Bgmode::Bgmode0 - } - #[doc = "Bandgap enabled, buffer disabled"] - #[inline(always)] - pub fn is_bgmode01(&self) -> bool { - *self == Bgmode::Bgmode01 - } - #[doc = "Bandgap enabled, buffer enabled"] - #[inline(always)] - pub fn is_bgmode10(&self) -> bool { - *self == Bgmode::Bgmode10 - } -} -#[doc = "Field `BGMODE` writer - Bandgap Mode"] -pub type BgmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bgmode>; -impl<'a, REG> BgmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Bandgap disabled"] - #[inline(always)] - pub fn bgmode0(self) -> &'a mut crate::W { - self.variant(Bgmode::Bgmode0) - } - #[doc = "Bandgap enabled, buffer disabled"] - #[inline(always)] - pub fn bgmode01(self) -> &'a mut crate::W { - self.variant(Bgmode::Bgmode01) - } - #[doc = "Bandgap enabled, buffer enabled"] - #[inline(always)] - pub fn bgmode10(self) -> &'a mut crate::W { - self.variant(Bgmode::Bgmode10) - } -} -#[doc = "VDD Voltage Detect Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum VddVdDisable { - #[doc = "0: Enable"] - Enable = 0, - #[doc = "1: Disable"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: VddVdDisable) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VDD_VD_DISABLE` reader - VDD Voltage Detect Disable"] -pub type VddVdDisableR = crate::BitReader; -impl VddVdDisableR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> VddVdDisable { - match self.bits { - false => VddVdDisable::Enable, - true => VddVdDisable::Disable, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == VddVdDisable::Enable - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == VddVdDisable::Disable - } -} -#[doc = "Field `VDD_VD_DISABLE` writer - VDD Voltage Detect Disable"] -pub type VddVdDisableW<'a, REG> = crate::BitWriter<'a, REG, VddVdDisable>; -impl<'a, REG> VddVdDisableW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(VddVdDisable::Enable) - } - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(VddVdDisable::Disable) - } -} -#[doc = "Core Low-Voltage Detection Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoreLvde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoreLvde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CORE_LVDE` reader - Core Low-Voltage Detection Enable"] -pub type CoreLvdeR = crate::BitReader; -impl CoreLvdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoreLvde { - match self.bits { - false => CoreLvde::Disable, - true => CoreLvde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == CoreLvde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == CoreLvde::Enable - } -} -#[doc = "Field `CORE_LVDE` writer - Core Low-Voltage Detection Enable"] -pub type CoreLvdeW<'a, REG> = crate::BitWriter<'a, REG, CoreLvde>; -impl<'a, REG> CoreLvdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(CoreLvde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(CoreLvde::Enable) - } -} -#[doc = "System Low-Voltage Detection Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SysLvde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SysLvde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYS_LVDE` reader - System Low-Voltage Detection Enable"] -pub type SysLvdeR = crate::BitReader; -impl SysLvdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SysLvde { - match self.bits { - false => SysLvde::Disable, - true => SysLvde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SysLvde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SysLvde::Enable - } -} -#[doc = "Field `SYS_LVDE` writer - System Low-Voltage Detection Enable"] -pub type SysLvdeW<'a, REG> = crate::BitWriter<'a, REG, SysLvde>; -impl<'a, REG> SysLvdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SysLvde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SysLvde::Enable) - } -} -#[doc = "System High-Voltage Detection Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SysHvde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SysHvde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYS_HVDE` reader - System High-Voltage Detection Enable"] -pub type SysHvdeR = crate::BitReader; -impl SysHvdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SysHvde { - match self.bits { - false => SysHvde::Disable, - true => SysHvde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SysHvde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SysHvde::Enable - } -} -#[doc = "Field `SYS_HVDE` writer - System High-Voltage Detection Enable"] -pub type SysHvdeW<'a, REG> = crate::BitWriter<'a, REG, SysHvde>; -impl<'a, REG> SysHvdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SysHvde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SysHvde::Enable) - } -} -impl R { - #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] - #[inline(always)] - pub fn coreldo_vdd_ds(&self) -> CoreldoVddDsR { - CoreldoVddDsR::new((self.bits & 1) != 0) - } - #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] - #[inline(always)] - pub fn coreldo_vdd_lvl(&self) -> CoreldoVddLvlR { - CoreldoVddLvlR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 20:21 - Bandgap Mode"] - #[inline(always)] - pub fn bgmode(&self) -> BgmodeR { - BgmodeR::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bit 23 - VDD Voltage Detect Disable"] - #[inline(always)] - pub fn vdd_vd_disable(&self) -> VddVdDisableR { - VddVdDisableR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Core Low-Voltage Detection Enable"] - #[inline(always)] - pub fn core_lvde(&self) -> CoreLvdeR { - CoreLvdeR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - System Low-Voltage Detection Enable"] - #[inline(always)] - pub fn sys_lvde(&self) -> SysLvdeR { - SysLvdeR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 28 - System High-Voltage Detection Enable"] - #[inline(always)] - pub fn sys_hvde(&self) -> SysHvdeR { - SysHvdeR::new(((self.bits >> 28) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] - #[inline(always)] - pub fn coreldo_vdd_ds(&mut self) -> CoreldoVddDsW { - CoreldoVddDsW::new(self, 0) - } - #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] - #[inline(always)] - pub fn coreldo_vdd_lvl(&mut self) -> CoreldoVddLvlW { - CoreldoVddLvlW::new(self, 2) - } - #[doc = "Bits 20:21 - Bandgap Mode"] - #[inline(always)] - pub fn bgmode(&mut self) -> BgmodeW { - BgmodeW::new(self, 20) - } - #[doc = "Bit 23 - VDD Voltage Detect Disable"] - #[inline(always)] - pub fn vdd_vd_disable(&mut self) -> VddVdDisableW { - VddVdDisableW::new(self, 23) - } - #[doc = "Bit 24 - Core Low-Voltage Detection Enable"] - #[inline(always)] - pub fn core_lvde(&mut self) -> CoreLvdeW { - CoreLvdeW::new(self, 24) - } - #[doc = "Bit 25 - System Low-Voltage Detection Enable"] - #[inline(always)] - pub fn sys_lvde(&mut self) -> SysLvdeW { - SysLvdeW::new(self, 25) - } - #[doc = "Bit 28 - System High-Voltage Detection Enable"] - #[inline(always)] - pub fn sys_hvde(&mut self) -> SysHvdeW { - SysHvdeW::new(self, 28) - } -} -#[doc = "Active Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ActiveCfgSpec; -impl crate::RegisterSpec for ActiveCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`active_cfg::R`](R) reader structure"] -impl crate::Readable for ActiveCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`active_cfg::W`](W) writer structure"] -impl crate::Writable for ActiveCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ACTIVE_CFG to value 0x1310_0005"] -impl crate::Resettable for ActiveCfgSpec { - const RESET_VALUE: u32 = 0x1310_0005; -} diff --git a/mcxa276-pac/src/spc0/active_cfg1.rs b/mcxa276-pac/src/spc0/active_cfg1.rs deleted file mode 100644 index 47a95fa3c..000000000 --- a/mcxa276-pac/src/spc0/active_cfg1.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `ACTIVE_CFG1` reader"] -pub type R = crate::R; -#[doc = "Register `ACTIVE_CFG1` writer"] -pub type W = crate::W; -#[doc = "Field `SOC_CNTRL` reader - Active Config Chip Control"] -pub type SocCntrlR = crate::FieldReader; -#[doc = "Field `SOC_CNTRL` writer - Active Config Chip Control"] -pub type SocCntrlW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Active Config Chip Control"] - #[inline(always)] - pub fn soc_cntrl(&self) -> SocCntrlR { - SocCntrlR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Active Config Chip Control"] - #[inline(always)] - pub fn soc_cntrl(&mut self) -> SocCntrlW { - SocCntrlW::new(self, 0) - } -} -#[doc = "Active Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`active_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ActiveCfg1Spec; -impl crate::RegisterSpec for ActiveCfg1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`active_cfg1::R`](R) reader structure"] -impl crate::Readable for ActiveCfg1Spec {} -#[doc = "`write(|w| ..)` method takes [`active_cfg1::W`](W) writer structure"] -impl crate::Writable for ActiveCfg1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ACTIVE_CFG1 to value 0x02"] -impl crate::Resettable for ActiveCfg1Spec { - const RESET_VALUE: u32 = 0x02; -} diff --git a/mcxa276-pac/src/spc0/active_vdelay.rs b/mcxa276-pac/src/spc0/active_vdelay.rs deleted file mode 100644 index 1b18f95bc..000000000 --- a/mcxa276-pac/src/spc0/active_vdelay.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `ACTIVE_VDELAY` reader"] -pub type R = crate::R; -#[doc = "Register `ACTIVE_VDELAY` writer"] -pub type W = crate::W; -#[doc = "Field `ACTIVE_VDELAY` reader - Active Voltage Delay"] -pub type ActiveVdelayR = crate::FieldReader; -#[doc = "Field `ACTIVE_VDELAY` writer - Active Voltage Delay"] -pub type ActiveVdelayW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Active Voltage Delay"] - #[inline(always)] - pub fn active_vdelay(&self) -> ActiveVdelayR { - ActiveVdelayR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Active Voltage Delay"] - #[inline(always)] - pub fn active_vdelay(&mut self) -> ActiveVdelayW { - ActiveVdelayW::new(self, 0) - } -} -#[doc = "Active Voltage Trim Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`active_vdelay::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`active_vdelay::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ActiveVdelaySpec; -impl crate::RegisterSpec for ActiveVdelaySpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`active_vdelay::R`](R) reader structure"] -impl crate::Readable for ActiveVdelaySpec {} -#[doc = "`write(|w| ..)` method takes [`active_vdelay::W`](W) writer structure"] -impl crate::Writable for ActiveVdelaySpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ACTIVE_VDELAY to value 0xc8"] -impl crate::Resettable for ActiveVdelaySpec { - const RESET_VALUE: u32 = 0xc8; -} diff --git a/mcxa276-pac/src/spc0/coreldo_cfg.rs b/mcxa276-pac/src/spc0/coreldo_cfg.rs deleted file mode 100644 index cc45ed404..000000000 --- a/mcxa276-pac/src/spc0/coreldo_cfg.rs +++ /dev/null @@ -1,16 +0,0 @@ -#[doc = "Register `CORELDO_CFG` reader"] -pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[doc = "LDO_CORE Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`coreldo_cfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CoreldoCfgSpec; -impl crate::RegisterSpec for CoreldoCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`coreldo_cfg::R`](R) reader structure"] -impl crate::Readable for CoreldoCfgSpec {} -#[doc = "`reset()` method sets CORELDO_CFG to value 0"] -impl crate::Resettable for CoreldoCfgSpec {} diff --git a/mcxa276-pac/src/spc0/evd_cfg.rs b/mcxa276-pac/src/spc0/evd_cfg.rs deleted file mode 100644 index 5e4f55c49..000000000 --- a/mcxa276-pac/src/spc0/evd_cfg.rs +++ /dev/null @@ -1,56 +0,0 @@ -#[doc = "Register `EVD_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `EVD_CFG` writer"] -pub type W = crate::W; -#[doc = "Field `EVDISO` reader - External Voltage Domain Isolation"] -pub type EvdisoR = crate::FieldReader; -#[doc = "Field `EVDISO` writer - External Voltage Domain Isolation"] -pub type EvdisoW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `EVDLPISO` reader - External Voltage Domain Low-Power Isolation"] -pub type EvdlpisoR = crate::FieldReader; -#[doc = "Field `EVDLPISO` writer - External Voltage Domain Low-Power Isolation"] -pub type EvdlpisoW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `EVDSTAT` reader - External Voltage Domain Status"] -pub type EvdstatR = crate::FieldReader; -impl R { - #[doc = "Bits 0:2 - External Voltage Domain Isolation"] - #[inline(always)] - pub fn evdiso(&self) -> EvdisoR { - EvdisoR::new((self.bits & 7) as u8) - } - #[doc = "Bits 8:10 - External Voltage Domain Low-Power Isolation"] - #[inline(always)] - pub fn evdlpiso(&self) -> EvdlpisoR { - EvdlpisoR::new(((self.bits >> 8) & 7) as u8) - } - #[doc = "Bits 16:18 - External Voltage Domain Status"] - #[inline(always)] - pub fn evdstat(&self) -> EvdstatR { - EvdstatR::new(((self.bits >> 16) & 7) as u8) - } -} -impl W { - #[doc = "Bits 0:2 - External Voltage Domain Isolation"] - #[inline(always)] - pub fn evdiso(&mut self) -> EvdisoW { - EvdisoW::new(self, 0) - } - #[doc = "Bits 8:10 - External Voltage Domain Low-Power Isolation"] - #[inline(always)] - pub fn evdlpiso(&mut self) -> EvdlpisoW { - EvdlpisoW::new(self, 8) - } -} -#[doc = "External Voltage Domain Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`evd_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evd_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EvdCfgSpec; -impl crate::RegisterSpec for EvdCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`evd_cfg::R`](R) reader structure"] -impl crate::Readable for EvdCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`evd_cfg::W`](W) writer structure"] -impl crate::Writable for EvdCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets EVD_CFG to value 0"] -impl crate::Resettable for EvdCfgSpec {} diff --git a/mcxa276-pac/src/spc0/lp_cfg.rs b/mcxa276-pac/src/spc0/lp_cfg.rs deleted file mode 100644 index 4a56f3ab1..000000000 --- a/mcxa276-pac/src/spc0/lp_cfg.rs +++ /dev/null @@ -1,567 +0,0 @@ -#[doc = "Register `LP_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `LP_CFG` writer"] -pub type W = crate::W; -#[doc = "LDO_CORE VDD Drive Strength\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoreldoVddDs { - #[doc = "0: Low"] - Low = 0, - #[doc = "1: Normal"] - Normal = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoreldoVddDs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CORELDO_VDD_DS` reader - LDO_CORE VDD Drive Strength"] -pub type CoreldoVddDsR = crate::BitReader; -impl CoreldoVddDsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoreldoVddDs { - match self.bits { - false => CoreldoVddDs::Low, - true => CoreldoVddDs::Normal, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == CoreldoVddDs::Low - } - #[doc = "Normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == CoreldoVddDs::Normal - } -} -#[doc = "Field `CORELDO_VDD_DS` writer - LDO_CORE VDD Drive Strength"] -pub type CoreldoVddDsW<'a, REG> = crate::BitWriter<'a, REG, CoreldoVddDs>; -impl<'a, REG> CoreldoVddDsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn low(self) -> &'a mut crate::W { - self.variant(CoreldoVddDs::Low) - } - #[doc = "Normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(CoreldoVddDs::Normal) - } -} -#[doc = "LDO_CORE VDD Regulator Voltage Level\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum CoreldoVddLvl { - #[doc = "1: Mid voltage (1.0 V)"] - Mid = 1, - #[doc = "2: Normal voltage (1.1 V)"] - Normal = 2, - #[doc = "3: Overdrive voltage (1.15 V)"] - Over = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: CoreldoVddLvl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for CoreldoVddLvl { - type Ux = u8; -} -impl crate::IsEnum for CoreldoVddLvl {} -#[doc = "Field `CORELDO_VDD_LVL` reader - LDO_CORE VDD Regulator Voltage Level"] -pub type CoreldoVddLvlR = crate::FieldReader; -impl CoreldoVddLvlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(CoreldoVddLvl::Mid), - 2 => Some(CoreldoVddLvl::Normal), - 3 => Some(CoreldoVddLvl::Over), - _ => None, - } - } - #[doc = "Mid voltage (1.0 V)"] - #[inline(always)] - pub fn is_mid(&self) -> bool { - *self == CoreldoVddLvl::Mid - } - #[doc = "Normal voltage (1.1 V)"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == CoreldoVddLvl::Normal - } - #[doc = "Overdrive voltage (1.15 V)"] - #[inline(always)] - pub fn is_over(&self) -> bool { - *self == CoreldoVddLvl::Over - } -} -#[doc = "Field `CORELDO_VDD_LVL` writer - LDO_CORE VDD Regulator Voltage Level"] -pub type CoreldoVddLvlW<'a, REG> = crate::FieldWriter<'a, REG, 2, CoreldoVddLvl>; -impl<'a, REG> CoreldoVddLvlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Mid voltage (1.0 V)"] - #[inline(always)] - pub fn mid(self) -> &'a mut crate::W { - self.variant(CoreldoVddLvl::Mid) - } - #[doc = "Normal voltage (1.1 V)"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(CoreldoVddLvl::Normal) - } - #[doc = "Overdrive voltage (1.15 V)"] - #[inline(always)] - pub fn over(self) -> &'a mut crate::W { - self.variant(CoreldoVddLvl::Over) - } -} -#[doc = "SRAM_LDO Deep Power Low Power IREF Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SramldoDpdOn { - #[doc = "0: Low Power IREF is disabled for power saving in Deep Power Down mode"] - Disabled = 0, - #[doc = "1: Low Power IREF is enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SramldoDpdOn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRAMLDO_DPD_ON` reader - SRAM_LDO Deep Power Low Power IREF Enable"] -pub type SramldoDpdOnR = crate::BitReader; -impl SramldoDpdOnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SramldoDpdOn { - match self.bits { - false => SramldoDpdOn::Disabled, - true => SramldoDpdOn::Enabled, - } - } - #[doc = "Low Power IREF is disabled for power saving in Deep Power Down mode"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == SramldoDpdOn::Disabled - } - #[doc = "Low Power IREF is enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == SramldoDpdOn::Enabled - } -} -#[doc = "Field `SRAMLDO_DPD_ON` writer - SRAM_LDO Deep Power Low Power IREF Enable"] -pub type SramldoDpdOnW<'a, REG> = crate::BitWriter<'a, REG, SramldoDpdOn>; -impl<'a, REG> SramldoDpdOnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low Power IREF is disabled for power saving in Deep Power Down mode"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(SramldoDpdOn::Disabled) - } - #[doc = "Low Power IREF is enabled"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(SramldoDpdOn::Enabled) - } -} -#[doc = "Bandgap Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Bgmode { - #[doc = "0: Bandgap disabled"] - Bgmode0 = 0, - #[doc = "1: Bandgap enabled, buffer disabled"] - Bgmode01 = 1, - #[doc = "2: Bandgap enabled, buffer enabled"] - Bgmode10 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Bgmode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Bgmode { - type Ux = u8; -} -impl crate::IsEnum for Bgmode {} -#[doc = "Field `BGMODE` reader - Bandgap Mode"] -pub type BgmodeR = crate::FieldReader; -impl BgmodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Bgmode::Bgmode0), - 1 => Some(Bgmode::Bgmode01), - 2 => Some(Bgmode::Bgmode10), - _ => None, - } - } - #[doc = "Bandgap disabled"] - #[inline(always)] - pub fn is_bgmode0(&self) -> bool { - *self == Bgmode::Bgmode0 - } - #[doc = "Bandgap enabled, buffer disabled"] - #[inline(always)] - pub fn is_bgmode01(&self) -> bool { - *self == Bgmode::Bgmode01 - } - #[doc = "Bandgap enabled, buffer enabled"] - #[inline(always)] - pub fn is_bgmode10(&self) -> bool { - *self == Bgmode::Bgmode10 - } -} -#[doc = "Field `BGMODE` writer - Bandgap Mode"] -pub type BgmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bgmode>; -impl<'a, REG> BgmodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Bandgap disabled"] - #[inline(always)] - pub fn bgmode0(self) -> &'a mut crate::W { - self.variant(Bgmode::Bgmode0) - } - #[doc = "Bandgap enabled, buffer disabled"] - #[inline(always)] - pub fn bgmode01(self) -> &'a mut crate::W { - self.variant(Bgmode::Bgmode01) - } - #[doc = "Bandgap enabled, buffer enabled"] - #[inline(always)] - pub fn bgmode10(self) -> &'a mut crate::W { - self.variant(Bgmode::Bgmode10) - } -} -#[doc = "Low-Power IREF Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LpIrefen { - #[doc = "0: Disable for power saving in Deep Power Down mode"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LpIrefen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LP_IREFEN` reader - Low-Power IREF Enable"] -pub type LpIrefenR = crate::BitReader; -impl LpIrefenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LpIrefen { - match self.bits { - false => LpIrefen::Disable, - true => LpIrefen::Enable, - } - } - #[doc = "Disable for power saving in Deep Power Down mode"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == LpIrefen::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == LpIrefen::Enable - } -} -#[doc = "Field `LP_IREFEN` writer - Low-Power IREF Enable"] -pub type LpIrefenW<'a, REG> = crate::BitWriter<'a, REG, LpIrefen>; -impl<'a, REG> LpIrefenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable for power saving in Deep Power Down mode"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(LpIrefen::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(LpIrefen::Enable) - } -} -#[doc = "Core Low Voltage Detect Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CoreLvde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CoreLvde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CORE_LVDE` reader - Core Low Voltage Detect Enable"] -pub type CoreLvdeR = crate::BitReader; -impl CoreLvdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CoreLvde { - match self.bits { - false => CoreLvde::Disable, - true => CoreLvde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == CoreLvde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == CoreLvde::Enable - } -} -#[doc = "Field `CORE_LVDE` writer - Core Low Voltage Detect Enable"] -pub type CoreLvdeW<'a, REG> = crate::BitWriter<'a, REG, CoreLvde>; -impl<'a, REG> CoreLvdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(CoreLvde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(CoreLvde::Enable) - } -} -#[doc = "System Low Voltage Detect Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SysLvde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SysLvde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYS_LVDE` reader - System Low Voltage Detect Enable"] -pub type SysLvdeR = crate::BitReader; -impl SysLvdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SysLvde { - match self.bits { - false => SysLvde::Disable, - true => SysLvde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SysLvde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SysLvde::Enable - } -} -#[doc = "Field `SYS_LVDE` writer - System Low Voltage Detect Enable"] -pub type SysLvdeW<'a, REG> = crate::BitWriter<'a, REG, SysLvde>; -impl<'a, REG> SysLvdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SysLvde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SysLvde::Enable) - } -} -#[doc = "System High Voltage Detect Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SysHvde { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SysHvde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYS_HVDE` reader - System High Voltage Detect Enable"] -pub type SysHvdeR = crate::BitReader; -impl SysHvdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SysHvde { - match self.bits { - false => SysHvde::Disable, - true => SysHvde::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SysHvde::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SysHvde::Enable - } -} -#[doc = "Field `SYS_HVDE` writer - System High Voltage Detect Enable"] -pub type SysHvdeW<'a, REG> = crate::BitWriter<'a, REG, SysHvde>; -impl<'a, REG> SysHvdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SysHvde::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SysHvde::Enable) - } -} -impl R { - #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] - #[inline(always)] - pub fn coreldo_vdd_ds(&self) -> CoreldoVddDsR { - CoreldoVddDsR::new((self.bits & 1) != 0) - } - #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] - #[inline(always)] - pub fn coreldo_vdd_lvl(&self) -> CoreldoVddLvlR { - CoreldoVddLvlR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bit 19 - SRAM_LDO Deep Power Low Power IREF Enable"] - #[inline(always)] - pub fn sramldo_dpd_on(&self) -> SramldoDpdOnR { - SramldoDpdOnR::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bits 20:21 - Bandgap Mode"] - #[inline(always)] - pub fn bgmode(&self) -> BgmodeR { - BgmodeR::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bit 23 - Low-Power IREF Enable"] - #[inline(always)] - pub fn lp_irefen(&self) -> LpIrefenR { - LpIrefenR::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Core Low Voltage Detect Enable"] - #[inline(always)] - pub fn core_lvde(&self) -> CoreLvdeR { - CoreLvdeR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - System Low Voltage Detect Enable"] - #[inline(always)] - pub fn sys_lvde(&self) -> SysLvdeR { - SysLvdeR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 28 - System High Voltage Detect Enable"] - #[inline(always)] - pub fn sys_hvde(&self) -> SysHvdeR { - SysHvdeR::new(((self.bits >> 28) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - LDO_CORE VDD Drive Strength"] - #[inline(always)] - pub fn coreldo_vdd_ds(&mut self) -> CoreldoVddDsW { - CoreldoVddDsW::new(self, 0) - } - #[doc = "Bits 2:3 - LDO_CORE VDD Regulator Voltage Level"] - #[inline(always)] - pub fn coreldo_vdd_lvl(&mut self) -> CoreldoVddLvlW { - CoreldoVddLvlW::new(self, 2) - } - #[doc = "Bit 19 - SRAM_LDO Deep Power Low Power IREF Enable"] - #[inline(always)] - pub fn sramldo_dpd_on(&mut self) -> SramldoDpdOnW { - SramldoDpdOnW::new(self, 19) - } - #[doc = "Bits 20:21 - Bandgap Mode"] - #[inline(always)] - pub fn bgmode(&mut self) -> BgmodeW { - BgmodeW::new(self, 20) - } - #[doc = "Bit 23 - Low-Power IREF Enable"] - #[inline(always)] - pub fn lp_irefen(&mut self) -> LpIrefenW { - LpIrefenW::new(self, 23) - } - #[doc = "Bit 24 - Core Low Voltage Detect Enable"] - #[inline(always)] - pub fn core_lvde(&mut self) -> CoreLvdeW { - CoreLvdeW::new(self, 24) - } - #[doc = "Bit 25 - System Low Voltage Detect Enable"] - #[inline(always)] - pub fn sys_lvde(&mut self) -> SysLvdeW { - SysLvdeW::new(self, 25) - } - #[doc = "Bit 28 - System High Voltage Detect Enable"] - #[inline(always)] - pub fn sys_hvde(&mut self) -> SysHvdeW { - SysHvdeW::new(self, 28) - } -} -#[doc = "Low-Power Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LpCfgSpec; -impl crate::RegisterSpec for LpCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lp_cfg::R`](R) reader structure"] -impl crate::Readable for LpCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`lp_cfg::W`](W) writer structure"] -impl crate::Writable for LpCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LP_CFG to value 0x0008_0004"] -impl crate::Resettable for LpCfgSpec { - const RESET_VALUE: u32 = 0x0008_0004; -} diff --git a/mcxa276-pac/src/spc0/lp_cfg1.rs b/mcxa276-pac/src/spc0/lp_cfg1.rs deleted file mode 100644 index eb22299d9..000000000 --- a/mcxa276-pac/src/spc0/lp_cfg1.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `LP_CFG1` reader"] -pub type R = crate::R; -#[doc = "Register `LP_CFG1` writer"] -pub type W = crate::W; -#[doc = "Field `SOC_CNTRL` reader - Low-Power Configuration Chip Control"] -pub type SocCntrlR = crate::FieldReader; -#[doc = "Field `SOC_CNTRL` writer - Low-Power Configuration Chip Control"] -pub type SocCntrlW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Low-Power Configuration Chip Control"] - #[inline(always)] - pub fn soc_cntrl(&self) -> SocCntrlR { - SocCntrlR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Low-Power Configuration Chip Control"] - #[inline(always)] - pub fn soc_cntrl(&mut self) -> SocCntrlW { - SocCntrlW::new(self, 0) - } -} -#[doc = "Low Power Mode Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LpCfg1Spec; -impl crate::RegisterSpec for LpCfg1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lp_cfg1::R`](R) reader structure"] -impl crate::Readable for LpCfg1Spec {} -#[doc = "`write(|w| ..)` method takes [`lp_cfg1::W`](W) writer structure"] -impl crate::Writable for LpCfg1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LP_CFG1 to value 0x02"] -impl crate::Resettable for LpCfg1Spec { - const RESET_VALUE: u32 = 0x02; -} diff --git a/mcxa276-pac/src/spc0/lpreq_cfg.rs b/mcxa276-pac/src/spc0/lpreq_cfg.rs deleted file mode 100644 index e3d40e69d..000000000 --- a/mcxa276-pac/src/spc0/lpreq_cfg.rs +++ /dev/null @@ -1,230 +0,0 @@ -#[doc = "Register `LPREQ_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `LPREQ_CFG` writer"] -pub type W = crate::W; -#[doc = "Low-Power Request Output Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpreqoe { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpreqoe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPREQOE` reader - Low-Power Request Output Enable"] -pub type LpreqoeR = crate::BitReader; -impl LpreqoeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpreqoe { - match self.bits { - false => Lpreqoe::Disable, - true => Lpreqoe::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lpreqoe::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lpreqoe::Enable - } -} -#[doc = "Field `LPREQOE` writer - Low-Power Request Output Enable"] -pub type LpreqoeW<'a, REG> = crate::BitWriter<'a, REG, Lpreqoe>; -impl<'a, REG> LpreqoeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lpreqoe::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lpreqoe::Enable) - } -} -#[doc = "Low-Power Request Output Pin Polarity Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lpreqpol { - #[doc = "0: High"] - High = 0, - #[doc = "1: Low"] - Low = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lpreqpol) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPREQPOL` reader - Low-Power Request Output Pin Polarity Control"] -pub type LpreqpolR = crate::BitReader; -impl LpreqpolR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lpreqpol { - match self.bits { - false => Lpreqpol::High, - true => Lpreqpol::Low, - } - } - #[doc = "High"] - #[inline(always)] - pub fn is_high(&self) -> bool { - *self == Lpreqpol::High - } - #[doc = "Low"] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == Lpreqpol::Low - } -} -#[doc = "Field `LPREQPOL` writer - Low-Power Request Output Pin Polarity Control"] -pub type LpreqpolW<'a, REG> = crate::BitWriter<'a, REG, Lpreqpol>; -impl<'a, REG> LpreqpolW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "High"] - #[inline(always)] - pub fn high(self) -> &'a mut crate::W { - self.variant(Lpreqpol::High) - } - #[doc = "Low"] - #[inline(always)] - pub fn low(self) -> &'a mut crate::W { - self.variant(Lpreqpol::Low) - } -} -#[doc = "Low-Power Request Output Override\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Lpreqov { - #[doc = "0: Not forced"] - ForceNo = 0, - #[doc = "2: Forced low (ignore LPREQPOL settings)"] - ForceLow = 2, - #[doc = "3: Forced high (ignore LPREQPOL settings)"] - ForceHigh = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Lpreqov) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Lpreqov { - type Ux = u8; -} -impl crate::IsEnum for Lpreqov {} -#[doc = "Field `LPREQOV` reader - Low-Power Request Output Override"] -pub type LpreqovR = crate::FieldReader; -impl LpreqovR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Lpreqov::ForceNo), - 2 => Some(Lpreqov::ForceLow), - 3 => Some(Lpreqov::ForceHigh), - _ => None, - } - } - #[doc = "Not forced"] - #[inline(always)] - pub fn is_force_no(&self) -> bool { - *self == Lpreqov::ForceNo - } - #[doc = "Forced low (ignore LPREQPOL settings)"] - #[inline(always)] - pub fn is_force_low(&self) -> bool { - *self == Lpreqov::ForceLow - } - #[doc = "Forced high (ignore LPREQPOL settings)"] - #[inline(always)] - pub fn is_force_high(&self) -> bool { - *self == Lpreqov::ForceHigh - } -} -#[doc = "Field `LPREQOV` writer - Low-Power Request Output Override"] -pub type LpreqovW<'a, REG> = crate::FieldWriter<'a, REG, 2, Lpreqov>; -impl<'a, REG> LpreqovW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Not forced"] - #[inline(always)] - pub fn force_no(self) -> &'a mut crate::W { - self.variant(Lpreqov::ForceNo) - } - #[doc = "Forced low (ignore LPREQPOL settings)"] - #[inline(always)] - pub fn force_low(self) -> &'a mut crate::W { - self.variant(Lpreqov::ForceLow) - } - #[doc = "Forced high (ignore LPREQPOL settings)"] - #[inline(always)] - pub fn force_high(self) -> &'a mut crate::W { - self.variant(Lpreqov::ForceHigh) - } -} -impl R { - #[doc = "Bit 0 - Low-Power Request Output Enable"] - #[inline(always)] - pub fn lpreqoe(&self) -> LpreqoeR { - LpreqoeR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Low-Power Request Output Pin Polarity Control"] - #[inline(always)] - pub fn lpreqpol(&self) -> LpreqpolR { - LpreqpolR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Low-Power Request Output Override"] - #[inline(always)] - pub fn lpreqov(&self) -> LpreqovR { - LpreqovR::new(((self.bits >> 2) & 3) as u8) - } -} -impl W { - #[doc = "Bit 0 - Low-Power Request Output Enable"] - #[inline(always)] - pub fn lpreqoe(&mut self) -> LpreqoeW { - LpreqoeW::new(self, 0) - } - #[doc = "Bit 1 - Low-Power Request Output Pin Polarity Control"] - #[inline(always)] - pub fn lpreqpol(&mut self) -> LpreqpolW { - LpreqpolW::new(self, 1) - } - #[doc = "Bits 2:3 - Low-Power Request Output Override"] - #[inline(always)] - pub fn lpreqov(&mut self) -> LpreqovW { - LpreqovW::new(self, 2) - } -} -#[doc = "Low-Power Request Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lpreq_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpreq_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LpreqCfgSpec; -impl crate::RegisterSpec for LpreqCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpreq_cfg::R`](R) reader structure"] -impl crate::Readable for LpreqCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`lpreq_cfg::W`](W) writer structure"] -impl crate::Writable for LpreqCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPREQ_CFG to value 0"] -impl crate::Resettable for LpreqCfgSpec {} diff --git a/mcxa276-pac/src/spc0/lpwkup_delay.rs b/mcxa276-pac/src/spc0/lpwkup_delay.rs deleted file mode 100644 index c3fc96585..000000000 --- a/mcxa276-pac/src/spc0/lpwkup_delay.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `LPWKUP_DELAY` reader"] -pub type R = crate::R; -#[doc = "Register `LPWKUP_DELAY` writer"] -pub type W = crate::W; -#[doc = "Field `LPWKUP_DELAY` reader - Low-Power Wake-Up Delay"] -pub type LpwkupDelayR = crate::FieldReader; -#[doc = "Field `LPWKUP_DELAY` writer - Low-Power Wake-Up Delay"] -pub type LpwkupDelayW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Low-Power Wake-Up Delay"] - #[inline(always)] - pub fn lpwkup_delay(&self) -> LpwkupDelayR { - LpwkupDelayR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Low-Power Wake-Up Delay"] - #[inline(always)] - pub fn lpwkup_delay(&mut self) -> LpwkupDelayW { - LpwkupDelayW::new(self, 0) - } -} -#[doc = "Low Power Wake-Up Delay\n\nYou can [`read`](crate::Reg::read) this register and get [`lpwkup_delay::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpwkup_delay::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LpwkupDelaySpec; -impl crate::RegisterSpec for LpwkupDelaySpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpwkup_delay::R`](R) reader structure"] -impl crate::Readable for LpwkupDelaySpec {} -#[doc = "`write(|w| ..)` method takes [`lpwkup_delay::W`](W) writer structure"] -impl crate::Writable for LpwkupDelaySpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPWKUP_DELAY to value 0"] -impl crate::Resettable for LpwkupDelaySpec {} diff --git a/mcxa276-pac/src/spc0/pd_status0.rs b/mcxa276-pac/src/spc0/pd_status0.rs deleted file mode 100644 index b3583f5f3..000000000 --- a/mcxa276-pac/src/spc0/pd_status0.rs +++ /dev/null @@ -1,189 +0,0 @@ -#[doc = "Register `PD_STATUS0` reader"] -pub type R = crate::R; -#[doc = "Register `PD_STATUS0` writer"] -pub type W = crate::W; -#[doc = "Power Request Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PwrReqStatus { - #[doc = "0: Did not request"] - ReqNo = 0, - #[doc = "1: Requested"] - ReqYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PwrReqStatus) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PWR_REQ_STATUS` reader - Power Request Status Flag"] -pub type PwrReqStatusR = crate::BitReader; -impl PwrReqStatusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PwrReqStatus { - match self.bits { - false => PwrReqStatus::ReqNo, - true => PwrReqStatus::ReqYes, - } - } - #[doc = "Did not request"] - #[inline(always)] - pub fn is_req_no(&self) -> bool { - *self == PwrReqStatus::ReqNo - } - #[doc = "Requested"] - #[inline(always)] - pub fn is_req_yes(&self) -> bool { - *self == PwrReqStatus::ReqYes - } -} -#[doc = "Power Domain Low Power Request Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum PdLpReq { - #[doc = "0: Did not request"] - ReqNo = 0, - #[doc = "1: Requested"] - ReqYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: PdLpReq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PD_LP_REQ` reader - Power Domain Low Power Request Flag"] -pub type PdLpReqR = crate::BitReader; -impl PdLpReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PdLpReq { - match self.bits { - false => PdLpReq::ReqNo, - true => PdLpReq::ReqYes, - } - } - #[doc = "Did not request"] - #[inline(always)] - pub fn is_req_no(&self) -> bool { - *self == PdLpReq::ReqNo - } - #[doc = "Requested"] - #[inline(always)] - pub fn is_req_yes(&self) -> bool { - *self == PdLpReq::ReqYes - } -} -#[doc = "Field `PD_LP_REQ` writer - Power Domain Low Power Request Flag"] -pub type PdLpReqW<'a, REG> = crate::BitWriter1C<'a, REG, PdLpReq>; -impl<'a, REG> PdLpReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Did not request"] - #[inline(always)] - pub fn req_no(self) -> &'a mut crate::W { - self.variant(PdLpReq::ReqNo) - } - #[doc = "Requested"] - #[inline(always)] - pub fn req_yes(self) -> &'a mut crate::W { - self.variant(PdLpReq::ReqYes) - } -} -#[doc = "Power Domain Low Power Mode Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum LpMode { - #[doc = "0: SLEEP with system clock running"] - Mode0 = 0, - #[doc = "1: DSLEEP with system clock off"] - Mode1 = 1, - #[doc = "2: PDOWN with system clock off"] - Mode2 = 2, - #[doc = "8: DPDOWN with system clock off"] - Mode8 = 8, -} -impl From for u8 { - #[inline(always)] - fn from(variant: LpMode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for LpMode { - type Ux = u8; -} -impl crate::IsEnum for LpMode {} -#[doc = "Field `LP_MODE` reader - Power Domain Low Power Mode Request"] -pub type LpModeR = crate::FieldReader; -impl LpModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(LpMode::Mode0), - 1 => Some(LpMode::Mode1), - 2 => Some(LpMode::Mode2), - 8 => Some(LpMode::Mode8), - _ => None, - } - } - #[doc = "SLEEP with system clock running"] - #[inline(always)] - pub fn is_mode0(&self) -> bool { - *self == LpMode::Mode0 - } - #[doc = "DSLEEP with system clock off"] - #[inline(always)] - pub fn is_mode1(&self) -> bool { - *self == LpMode::Mode1 - } - #[doc = "PDOWN with system clock off"] - #[inline(always)] - pub fn is_mode2(&self) -> bool { - *self == LpMode::Mode2 - } - #[doc = "DPDOWN with system clock off"] - #[inline(always)] - pub fn is_mode8(&self) -> bool { - *self == LpMode::Mode8 - } -} -impl R { - #[doc = "Bit 0 - Power Request Status Flag"] - #[inline(always)] - pub fn pwr_req_status(&self) -> PwrReqStatusR { - PwrReqStatusR::new((self.bits & 1) != 0) - } - #[doc = "Bit 4 - Power Domain Low Power Request Flag"] - #[inline(always)] - pub fn pd_lp_req(&self) -> PdLpReqR { - PdLpReqR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 8:11 - Power Domain Low Power Mode Request"] - #[inline(always)] - pub fn lp_mode(&self) -> LpModeR { - LpModeR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 4 - Power Domain Low Power Request Flag"] - #[inline(always)] - pub fn pd_lp_req(&mut self) -> PdLpReqW { - PdLpReqW::new(self, 4) - } -} -#[doc = "SPC Power Domain Mode Status\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_status0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_status0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PdStatus0Spec; -impl crate::RegisterSpec for PdStatus0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pd_status0::R`](R) reader structure"] -impl crate::Readable for PdStatus0Spec {} -#[doc = "`write(|w| ..)` method takes [`pd_status0::W`](W) writer structure"] -impl crate::Writable for PdStatus0Spec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x10; -} -#[doc = "`reset()` method sets PD_STATUS0 to value 0"] -impl crate::Resettable for PdStatus0Spec {} diff --git a/mcxa276-pac/src/spc0/sc.rs b/mcxa276-pac/src/spc0/sc.rs deleted file mode 100644 index 77f14943f..000000000 --- a/mcxa276-pac/src/spc0/sc.rs +++ /dev/null @@ -1,203 +0,0 @@ -#[doc = "Register `SC` reader"] -pub type R = crate::R; -#[doc = "Register `SC` writer"] -pub type W = crate::W; -#[doc = "SPC Busy Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Busy { - #[doc = "0: Not busy"] - BusyNo = 0, - #[doc = "1: Busy"] - BusyYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Busy) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUSY` reader - SPC Busy Status Flag"] -pub type BusyR = crate::BitReader; -impl BusyR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Busy { - match self.bits { - false => Busy::BusyNo, - true => Busy::BusyYes, - } - } - #[doc = "Not busy"] - #[inline(always)] - pub fn is_busy_no(&self) -> bool { - *self == Busy::BusyNo - } - #[doc = "Busy"] - #[inline(always)] - pub fn is_busy_yes(&self) -> bool { - *self == Busy::BusyYes - } -} -#[doc = "SPC Power Mode Configuration Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SpcLpReq { - #[doc = "0: SPC is in Active mode; the ACTIVE_CFG register has control"] - Active = 0, - #[doc = "1: All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register"] - LowPower = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SpcLpReq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SPC_LP_REQ` reader - SPC Power Mode Configuration Status Flag"] -pub type SpcLpReqR = crate::BitReader; -impl SpcLpReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SpcLpReq { - match self.bits { - false => SpcLpReq::Active, - true => SpcLpReq::LowPower, - } - } - #[doc = "SPC is in Active mode; the ACTIVE_CFG register has control"] - #[inline(always)] - pub fn is_active(&self) -> bool { - *self == SpcLpReq::Active - } - #[doc = "All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register"] - #[inline(always)] - pub fn is_low_power(&self) -> bool { - *self == SpcLpReq::LowPower - } -} -#[doc = "Field `SPC_LP_REQ` writer - SPC Power Mode Configuration Status Flag"] -pub type SpcLpReqW<'a, REG> = crate::BitWriter1C<'a, REG, SpcLpReq>; -impl<'a, REG> SpcLpReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "SPC is in Active mode; the ACTIVE_CFG register has control"] - #[inline(always)] - pub fn active(self) -> &'a mut crate::W { - self.variant(SpcLpReq::Active) - } - #[doc = "All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register"] - #[inline(always)] - pub fn low_power(self) -> &'a mut crate::W { - self.variant(SpcLpReq::LowPower) - } -} -#[doc = "Power Domain Low-Power Mode Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum SpcLpMode { - #[doc = "0: Sleep mode with system clock running"] - Mode0 = 0, - #[doc = "1: DSLEEP with system clock off"] - Mode1 = 1, - #[doc = "2: PDOWN with system clock off"] - Mode2 = 2, - #[doc = "8: DPDOWN with system clock off"] - Mode8 = 8, -} -impl From for u8 { - #[inline(always)] - fn from(variant: SpcLpMode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for SpcLpMode { - type Ux = u8; -} -impl crate::IsEnum for SpcLpMode {} -#[doc = "Field `SPC_LP_MODE` reader - Power Domain Low-Power Mode Request"] -pub type SpcLpModeR = crate::FieldReader; -impl SpcLpModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(SpcLpMode::Mode0), - 1 => Some(SpcLpMode::Mode1), - 2 => Some(SpcLpMode::Mode2), - 8 => Some(SpcLpMode::Mode8), - _ => None, - } - } - #[doc = "Sleep mode with system clock running"] - #[inline(always)] - pub fn is_mode0(&self) -> bool { - *self == SpcLpMode::Mode0 - } - #[doc = "DSLEEP with system clock off"] - #[inline(always)] - pub fn is_mode1(&self) -> bool { - *self == SpcLpMode::Mode1 - } - #[doc = "PDOWN with system clock off"] - #[inline(always)] - pub fn is_mode2(&self) -> bool { - *self == SpcLpMode::Mode2 - } - #[doc = "DPDOWN with system clock off"] - #[inline(always)] - pub fn is_mode8(&self) -> bool { - *self == SpcLpMode::Mode8 - } -} -#[doc = "Field `ISO_CLR` reader - Isolation Clear Flags"] -pub type IsoClrR = crate::BitReader; -#[doc = "Field `ISO_CLR` writer - Isolation Clear Flags"] -pub type IsoClrW<'a, REG> = crate::BitWriter1C<'a, REG>; -impl R { - #[doc = "Bit 0 - SPC Busy Status Flag"] - #[inline(always)] - pub fn busy(&self) -> BusyR { - BusyR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SPC Power Mode Configuration Status Flag"] - #[inline(always)] - pub fn spc_lp_req(&self) -> SpcLpReqR { - SpcLpReqR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 4:7 - Power Domain Low-Power Mode Request"] - #[inline(always)] - pub fn spc_lp_mode(&self) -> SpcLpModeR { - SpcLpModeR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bit 16 - Isolation Clear Flags"] - #[inline(always)] - pub fn iso_clr(&self) -> IsoClrR { - IsoClrR::new(((self.bits >> 16) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - SPC Power Mode Configuration Status Flag"] - #[inline(always)] - pub fn spc_lp_req(&mut self) -> SpcLpReqW { - SpcLpReqW::new(self, 1) - } - #[doc = "Bit 16 - Isolation Clear Flags"] - #[inline(always)] - pub fn iso_clr(&mut self) -> IsoClrW { - IsoClrW::new(self, 16) - } -} -#[doc = "Status Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ScSpec; -impl crate::RegisterSpec for ScSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sc::R`](R) reader structure"] -impl crate::Readable for ScSpec {} -#[doc = "`write(|w| ..)` method takes [`sc::W`](W) writer structure"] -impl crate::Writable for ScSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0001_0002; -} -#[doc = "`reset()` method sets SC to value 0"] -impl crate::Resettable for ScSpec {} diff --git a/mcxa276-pac/src/spc0/sramctl.rs b/mcxa276-pac/src/spc0/sramctl.rs deleted file mode 100644 index 82494e93b..000000000 --- a/mcxa276-pac/src/spc0/sramctl.rs +++ /dev/null @@ -1,197 +0,0 @@ -#[doc = "Register `SRAMCTL` reader"] -pub type R = crate::R; -#[doc = "Register `SRAMCTL` writer"] -pub type W = crate::W; -#[doc = "Voltage Select Margin\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Vsm { - #[doc = "1: 1.0 V"] - Vsm1 = 1, - #[doc = "2: 1.1 V"] - Vsm2 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Vsm) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Vsm { - type Ux = u8; -} -impl crate::IsEnum for Vsm {} -#[doc = "Field `VSM` reader - Voltage Select Margin"] -pub type VsmR = crate::FieldReader; -impl VsmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Vsm::Vsm1), - 2 => Some(Vsm::Vsm2), - _ => None, - } - } - #[doc = "1.0 V"] - #[inline(always)] - pub fn is_vsm1(&self) -> bool { - *self == Vsm::Vsm1 - } - #[doc = "1.1 V"] - #[inline(always)] - pub fn is_vsm2(&self) -> bool { - *self == Vsm::Vsm2 - } -} -#[doc = "Field `VSM` writer - Voltage Select Margin"] -pub type VsmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Vsm>; -impl<'a, REG> VsmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "1.0 V"] - #[inline(always)] - pub fn vsm1(self) -> &'a mut crate::W { - self.variant(Vsm::Vsm1) - } - #[doc = "1.1 V"] - #[inline(always)] - pub fn vsm2(self) -> &'a mut crate::W { - self.variant(Vsm::Vsm2) - } -} -#[doc = "SRAM Voltage Update Request\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Req { - #[doc = "0: Do not request"] - ReqNo = 0, - #[doc = "1: Request"] - ReqYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Req) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REQ` reader - SRAM Voltage Update Request"] -pub type ReqR = crate::BitReader; -impl ReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Req { - match self.bits { - false => Req::ReqNo, - true => Req::ReqYes, - } - } - #[doc = "Do not request"] - #[inline(always)] - pub fn is_req_no(&self) -> bool { - *self == Req::ReqNo - } - #[doc = "Request"] - #[inline(always)] - pub fn is_req_yes(&self) -> bool { - *self == Req::ReqYes - } -} -#[doc = "Field `REQ` writer - SRAM Voltage Update Request"] -pub type ReqW<'a, REG> = crate::BitWriter<'a, REG, Req>; -impl<'a, REG> ReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Do not request"] - #[inline(always)] - pub fn req_no(self) -> &'a mut crate::W { - self.variant(Req::ReqNo) - } - #[doc = "Request"] - #[inline(always)] - pub fn req_yes(self) -> &'a mut crate::W { - self.variant(Req::ReqYes) - } -} -#[doc = "SRAM Voltage Update Request Acknowledge\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ack { - #[doc = "0: Not acknowledged"] - AckNo = 0, - #[doc = "1: Acknowledged"] - AckYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ack) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ACK` reader - SRAM Voltage Update Request Acknowledge"] -pub type AckR = crate::BitReader; -impl AckR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ack { - match self.bits { - false => Ack::AckNo, - true => Ack::AckYes, - } - } - #[doc = "Not acknowledged"] - #[inline(always)] - pub fn is_ack_no(&self) -> bool { - *self == Ack::AckNo - } - #[doc = "Acknowledged"] - #[inline(always)] - pub fn is_ack_yes(&self) -> bool { - *self == Ack::AckYes - } -} -impl R { - #[doc = "Bits 0:1 - Voltage Select Margin"] - #[inline(always)] - pub fn vsm(&self) -> VsmR { - VsmR::new((self.bits & 3) as u8) - } - #[doc = "Bit 30 - SRAM Voltage Update Request"] - #[inline(always)] - pub fn req(&self) -> ReqR { - ReqR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - SRAM Voltage Update Request Acknowledge"] - #[inline(always)] - pub fn ack(&self) -> AckR { - AckR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - Voltage Select Margin"] - #[inline(always)] - pub fn vsm(&mut self) -> VsmW { - VsmW::new(self, 0) - } - #[doc = "Bit 30 - SRAM Voltage Update Request"] - #[inline(always)] - pub fn req(&mut self) -> ReqW { - ReqW::new(self, 30) - } -} -#[doc = "SRAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SramctlSpec; -impl crate::RegisterSpec for SramctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sramctl::R`](R) reader structure"] -impl crate::Readable for SramctlSpec {} -#[doc = "`write(|w| ..)` method takes [`sramctl::W`](W) writer structure"] -impl crate::Writable for SramctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SRAMCTL to value 0x01"] -impl crate::Resettable for SramctlSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/spc0/sramretldo_cntrl.rs b/mcxa276-pac/src/spc0/sramretldo_cntrl.rs deleted file mode 100644 index cd1382582..000000000 --- a/mcxa276-pac/src/spc0/sramretldo_cntrl.rs +++ /dev/null @@ -1,100 +0,0 @@ -#[doc = "Register `SRAMRETLDO_CNTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SRAMRETLDO_CNTRL` writer"] -pub type W = crate::W; -#[doc = "SRAM LDO Regulator Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SramldoOn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SramldoOn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRAMLDO_ON` reader - SRAM LDO Regulator Enable"] -pub type SramldoOnR = crate::BitReader; -impl SramldoOnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SramldoOn { - match self.bits { - false => SramldoOn::Disable, - true => SramldoOn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SramldoOn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SramldoOn::Enable - } -} -#[doc = "Field `SRAMLDO_ON` writer - SRAM LDO Regulator Enable"] -pub type SramldoOnW<'a, REG> = crate::BitWriter<'a, REG, SramldoOn>; -impl<'a, REG> SramldoOnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SramldoOn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SramldoOn::Enable) - } -} -#[doc = "Field `SRAM_RET_EN` reader - SRAM Retention"] -pub type SramRetEnR = crate::FieldReader; -#[doc = "Field `SRAM_RET_EN` writer - SRAM Retention"] -pub type SramRetEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bit 0 - SRAM LDO Regulator Enable"] - #[inline(always)] - pub fn sramldo_on(&self) -> SramldoOnR { - SramldoOnR::new((self.bits & 1) != 0) - } - #[doc = "Bits 8:11 - SRAM Retention"] - #[inline(always)] - pub fn sram_ret_en(&self) -> SramRetEnR { - SramRetEnR::new(((self.bits >> 8) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bit 0 - SRAM LDO Regulator Enable"] - #[inline(always)] - pub fn sramldo_on(&mut self) -> SramldoOnW { - SramldoOnW::new(self, 0) - } - #[doc = "Bits 8:11 - SRAM Retention"] - #[inline(always)] - pub fn sram_ret_en(&mut self) -> SramRetEnW { - SramRetEnW::new(self, 8) - } -} -#[doc = "SRAM Retention LDO Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_cntrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_cntrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SramretldoCntrlSpec; -impl crate::RegisterSpec for SramretldoCntrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sramretldo_cntrl::R`](R) reader structure"] -impl crate::Readable for SramretldoCntrlSpec {} -#[doc = "`write(|w| ..)` method takes [`sramretldo_cntrl::W`](W) writer structure"] -impl crate::Writable for SramretldoCntrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SRAMRETLDO_CNTRL to value 0x0f01"] -impl crate::Resettable for SramretldoCntrlSpec { - const RESET_VALUE: u32 = 0x0f01; -} diff --git a/mcxa276-pac/src/spc0/sramretldo_reftrim.rs b/mcxa276-pac/src/spc0/sramretldo_reftrim.rs deleted file mode 100644 index 97377fbd6..000000000 --- a/mcxa276-pac/src/spc0/sramretldo_reftrim.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SRAMRETLDO_REFTRIM` reader"] -pub type R = crate::R; -#[doc = "Register `SRAMRETLDO_REFTRIM` writer"] -pub type W = crate::W; -#[doc = "Field `REFTRIM` reader - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] -pub type ReftrimR = crate::FieldReader; -#[doc = "Field `REFTRIM` writer - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] -pub type ReftrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bits 0:4 - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] - #[inline(always)] - pub fn reftrim(&self) -> ReftrimR { - ReftrimR::new((self.bits & 0x1f) as u8) - } -} -impl W { - #[doc = "Bits 0:4 - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV."] - #[inline(always)] - pub fn reftrim(&mut self) -> ReftrimW { - ReftrimW::new(self, 0) - } -} -#[doc = "SRAM Retention Reference Trim\n\nYou can [`read`](crate::Reg::read) this register and get [`sramretldo_reftrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramretldo_reftrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SramretldoReftrimSpec; -impl crate::RegisterSpec for SramretldoReftrimSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sramretldo_reftrim::R`](R) reader structure"] -impl crate::Readable for SramretldoReftrimSpec {} -#[doc = "`write(|w| ..)` method takes [`sramretldo_reftrim::W`](W) writer structure"] -impl crate::Writable for SramretldoReftrimSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SRAMRETLDO_REFTRIM to value 0x17"] -impl crate::Resettable for SramretldoReftrimSpec { - const RESET_VALUE: u32 = 0x17; -} diff --git a/mcxa276-pac/src/spc0/vd_core_cfg.rs b/mcxa276-pac/src/spc0/vd_core_cfg.rs deleted file mode 100644 index d2242deec..000000000 --- a/mcxa276-pac/src/spc0/vd_core_cfg.rs +++ /dev/null @@ -1,212 +0,0 @@ -#[doc = "Register `VD_CORE_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `VD_CORE_CFG` writer"] -pub type W = crate::W; -#[doc = "Core LVD Reset Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lvdre { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lvdre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LVDRE` reader - Core LVD Reset Enable"] -pub type LvdreR = crate::BitReader; -impl LvdreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lvdre { - match self.bits { - false => Lvdre::Disable, - true => Lvdre::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lvdre::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lvdre::Enable - } -} -#[doc = "Field `LVDRE` writer - Core LVD Reset Enable"] -pub type LvdreW<'a, REG> = crate::BitWriter<'a, REG, Lvdre>; -impl<'a, REG> LvdreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lvdre::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lvdre::Enable) - } -} -#[doc = "Core LVD Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lvdie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lvdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LVDIE` reader - Core LVD Interrupt Enable"] -pub type LvdieR = crate::BitReader; -impl LvdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lvdie { - match self.bits { - false => Lvdie::Disable, - true => Lvdie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lvdie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lvdie::Enable - } -} -#[doc = "Field `LVDIE` writer - Core LVD Interrupt Enable"] -pub type LvdieW<'a, REG> = crate::BitWriter<'a, REG, Lvdie>; -impl<'a, REG> LvdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lvdie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lvdie::Enable) - } -} -#[doc = "Core Voltage Detect Reset Enable Lock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: Allow"] - Allow = 0, - #[doc = "1: Deny"] - Deny = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - Core Voltage Detect Reset Enable Lock"] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Allow, - true => Lock::Deny, - } - } - #[doc = "Allow"] - #[inline(always)] - pub fn is_allow(&self) -> bool { - *self == Lock::Allow - } - #[doc = "Deny"] - #[inline(always)] - pub fn is_deny(&self) -> bool { - *self == Lock::Deny - } -} -#[doc = "Field `LOCK` writer - Core Voltage Detect Reset Enable Lock"] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Allow"] - #[inline(always)] - pub fn allow(self) -> &'a mut crate::W { - self.variant(Lock::Allow) - } - #[doc = "Deny"] - #[inline(always)] - pub fn deny(self) -> &'a mut crate::W { - self.variant(Lock::Deny) - } -} -impl R { - #[doc = "Bit 0 - Core LVD Reset Enable"] - #[inline(always)] - pub fn lvdre(&self) -> LvdreR { - LvdreR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Core LVD Interrupt Enable"] - #[inline(always)] - pub fn lvdie(&self) -> LvdieR { - LvdieR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 16 - Core Voltage Detect Reset Enable Lock"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 16) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Core LVD Reset Enable"] - #[inline(always)] - pub fn lvdre(&mut self) -> LvdreW { - LvdreW::new(self, 0) - } - #[doc = "Bit 1 - Core LVD Interrupt Enable"] - #[inline(always)] - pub fn lvdie(&mut self) -> LvdieW { - LvdieW::new(self, 1) - } - #[doc = "Bit 16 - Core Voltage Detect Reset Enable Lock"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 16) - } -} -#[doc = "Core Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_core_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_core_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VdCoreCfgSpec; -impl crate::RegisterSpec for VdCoreCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`vd_core_cfg::R`](R) reader structure"] -impl crate::Readable for VdCoreCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`vd_core_cfg::W`](W) writer structure"] -impl crate::Writable for VdCoreCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets VD_CORE_CFG to value 0x01"] -impl crate::Resettable for VdCoreCfgSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/spc0/vd_stat.rs b/mcxa276-pac/src/spc0/vd_stat.rs deleted file mode 100644 index ced74dd59..000000000 --- a/mcxa276-pac/src/spc0/vd_stat.rs +++ /dev/null @@ -1,211 +0,0 @@ -#[doc = "Register `VD_STAT` reader"] -pub type R = crate::R; -#[doc = "Register `VD_STAT` writer"] -pub type W = crate::W; -#[doc = "Core Low-Voltage Detect Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum CorevddLvdf { - #[doc = "0: Event not detected"] - EventNo = 0, - #[doc = "1: Event detected"] - EventYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: CorevddLvdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `COREVDD_LVDF` reader - Core Low-Voltage Detect Flag"] -pub type CorevddLvdfR = crate::BitReader; -impl CorevddLvdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CorevddLvdf { - match self.bits { - false => CorevddLvdf::EventNo, - true => CorevddLvdf::EventYes, - } - } - #[doc = "Event not detected"] - #[inline(always)] - pub fn is_event_no(&self) -> bool { - *self == CorevddLvdf::EventNo - } - #[doc = "Event detected"] - #[inline(always)] - pub fn is_event_yes(&self) -> bool { - *self == CorevddLvdf::EventYes - } -} -#[doc = "Field `COREVDD_LVDF` writer - Core Low-Voltage Detect Flag"] -pub type CorevddLvdfW<'a, REG> = crate::BitWriter1C<'a, REG, CorevddLvdf>; -impl<'a, REG> CorevddLvdfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Event not detected"] - #[inline(always)] - pub fn event_no(self) -> &'a mut crate::W { - self.variant(CorevddLvdf::EventNo) - } - #[doc = "Event detected"] - #[inline(always)] - pub fn event_yes(self) -> &'a mut crate::W { - self.variant(CorevddLvdf::EventYes) - } -} -#[doc = "System Low-Voltage Detect Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SysvddLvdf { - #[doc = "0: Event not detected"] - EventNo = 0, - #[doc = "1: Event detected"] - EventYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SysvddLvdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYSVDD_LVDF` reader - System Low-Voltage Detect Flag"] -pub type SysvddLvdfR = crate::BitReader; -impl SysvddLvdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SysvddLvdf { - match self.bits { - false => SysvddLvdf::EventNo, - true => SysvddLvdf::EventYes, - } - } - #[doc = "Event not detected"] - #[inline(always)] - pub fn is_event_no(&self) -> bool { - *self == SysvddLvdf::EventNo - } - #[doc = "Event detected"] - #[inline(always)] - pub fn is_event_yes(&self) -> bool { - *self == SysvddLvdf::EventYes - } -} -#[doc = "Field `SYSVDD_LVDF` writer - System Low-Voltage Detect Flag"] -pub type SysvddLvdfW<'a, REG> = crate::BitWriter1C<'a, REG, SysvddLvdf>; -impl<'a, REG> SysvddLvdfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Event not detected"] - #[inline(always)] - pub fn event_no(self) -> &'a mut crate::W { - self.variant(SysvddLvdf::EventNo) - } - #[doc = "Event detected"] - #[inline(always)] - pub fn event_yes(self) -> &'a mut crate::W { - self.variant(SysvddLvdf::EventYes) - } -} -#[doc = "System HVD Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SysvddHvdf { - #[doc = "0: Event not detected"] - EventNo = 0, - #[doc = "1: Event detected"] - EventYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SysvddHvdf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYSVDD_HVDF` reader - System HVD Flag"] -pub type SysvddHvdfR = crate::BitReader; -impl SysvddHvdfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SysvddHvdf { - match self.bits { - false => SysvddHvdf::EventNo, - true => SysvddHvdf::EventYes, - } - } - #[doc = "Event not detected"] - #[inline(always)] - pub fn is_event_no(&self) -> bool { - *self == SysvddHvdf::EventNo - } - #[doc = "Event detected"] - #[inline(always)] - pub fn is_event_yes(&self) -> bool { - *self == SysvddHvdf::EventYes - } -} -#[doc = "Field `SYSVDD_HVDF` writer - System HVD Flag"] -pub type SysvddHvdfW<'a, REG> = crate::BitWriter1C<'a, REG, SysvddHvdf>; -impl<'a, REG> SysvddHvdfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Event not detected"] - #[inline(always)] - pub fn event_no(self) -> &'a mut crate::W { - self.variant(SysvddHvdf::EventNo) - } - #[doc = "Event detected"] - #[inline(always)] - pub fn event_yes(self) -> &'a mut crate::W { - self.variant(SysvddHvdf::EventYes) - } -} -impl R { - #[doc = "Bit 0 - Core Low-Voltage Detect Flag"] - #[inline(always)] - pub fn corevdd_lvdf(&self) -> CorevddLvdfR { - CorevddLvdfR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - System Low-Voltage Detect Flag"] - #[inline(always)] - pub fn sysvdd_lvdf(&self) -> SysvddLvdfR { - SysvddLvdfR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 5 - System HVD Flag"] - #[inline(always)] - pub fn sysvdd_hvdf(&self) -> SysvddHvdfR { - SysvddHvdfR::new(((self.bits >> 5) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Core Low-Voltage Detect Flag"] - #[inline(always)] - pub fn corevdd_lvdf(&mut self) -> CorevddLvdfW { - CorevddLvdfW::new(self, 0) - } - #[doc = "Bit 1 - System Low-Voltage Detect Flag"] - #[inline(always)] - pub fn sysvdd_lvdf(&mut self) -> SysvddLvdfW { - SysvddLvdfW::new(self, 1) - } - #[doc = "Bit 5 - System HVD Flag"] - #[inline(always)] - pub fn sysvdd_hvdf(&mut self) -> SysvddHvdfW { - SysvddHvdfW::new(self, 5) - } -} -#[doc = "Voltage Detect Status\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VdStatSpec; -impl crate::RegisterSpec for VdStatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`vd_stat::R`](R) reader structure"] -impl crate::Readable for VdStatSpec {} -#[doc = "`write(|w| ..)` method takes [`vd_stat::W`](W) writer structure"] -impl crate::Writable for VdStatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x23; -} -#[doc = "`reset()` method sets VD_STAT to value 0"] -impl crate::Resettable for VdStatSpec {} diff --git a/mcxa276-pac/src/spc0/vd_sys_cfg.rs b/mcxa276-pac/src/spc0/vd_sys_cfg.rs deleted file mode 100644 index ff1d9a5ff..000000000 --- a/mcxa276-pac/src/spc0/vd_sys_cfg.rs +++ /dev/null @@ -1,338 +0,0 @@ -#[doc = "Register `VD_SYS_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `VD_SYS_CFG` writer"] -pub type W = crate::W; -#[doc = "System LVD Reset Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lvdre { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lvdre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LVDRE` reader - System LVD Reset Enable"] -pub type LvdreR = crate::BitReader; -impl LvdreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lvdre { - match self.bits { - false => Lvdre::Disable, - true => Lvdre::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lvdre::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lvdre::Enable - } -} -#[doc = "Field `LVDRE` writer - System LVD Reset Enable"] -pub type LvdreW<'a, REG> = crate::BitWriter<'a, REG, Lvdre>; -impl<'a, REG> LvdreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lvdre::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lvdre::Enable) - } -} -#[doc = "System LVD Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lvdie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lvdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LVDIE` reader - System LVD Interrupt Enable"] -pub type LvdieR = crate::BitReader; -impl LvdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lvdie { - match self.bits { - false => Lvdie::Disable, - true => Lvdie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lvdie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lvdie::Enable - } -} -#[doc = "Field `LVDIE` writer - System LVD Interrupt Enable"] -pub type LvdieW<'a, REG> = crate::BitWriter<'a, REG, Lvdie>; -impl<'a, REG> LvdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lvdie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lvdie::Enable) - } -} -#[doc = "System HVD Reset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hvdre { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hvdre) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HVDRE` reader - System HVD Reset Enable"] -pub type HvdreR = crate::BitReader; -impl HvdreR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hvdre { - match self.bits { - false => Hvdre::Disable, - true => Hvdre::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Hvdre::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Hvdre::Enable - } -} -#[doc = "Field `HVDRE` writer - System HVD Reset Enable"] -pub type HvdreW<'a, REG> = crate::BitWriter<'a, REG, Hvdre>; -impl<'a, REG> HvdreW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Hvdre::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Hvdre::Enable) - } -} -#[doc = "System HVD Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hvdie { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hvdie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HVDIE` reader - System HVD Interrupt Enable"] -pub type HvdieR = crate::BitReader; -impl HvdieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hvdie { - match self.bits { - false => Hvdie::Disable, - true => Hvdie::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Hvdie::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Hvdie::Enable - } -} -#[doc = "Field `HVDIE` writer - System HVD Interrupt Enable"] -pub type HvdieW<'a, REG> = crate::BitWriter<'a, REG, Hvdie>; -impl<'a, REG> HvdieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Hvdie::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Hvdie::Enable) - } -} -#[doc = "System Voltage Detect Reset Enable Lock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: Allow"] - Allow = 0, - #[doc = "1: Deny"] - Deny = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - System Voltage Detect Reset Enable Lock"] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Allow, - true => Lock::Deny, - } - } - #[doc = "Allow"] - #[inline(always)] - pub fn is_allow(&self) -> bool { - *self == Lock::Allow - } - #[doc = "Deny"] - #[inline(always)] - pub fn is_deny(&self) -> bool { - *self == Lock::Deny - } -} -#[doc = "Field `LOCK` writer - System Voltage Detect Reset Enable Lock"] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Allow"] - #[inline(always)] - pub fn allow(self) -> &'a mut crate::W { - self.variant(Lock::Allow) - } - #[doc = "Deny"] - #[inline(always)] - pub fn deny(self) -> &'a mut crate::W { - self.variant(Lock::Deny) - } -} -impl R { - #[doc = "Bit 0 - System LVD Reset Enable"] - #[inline(always)] - pub fn lvdre(&self) -> LvdreR { - LvdreR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - System LVD Interrupt Enable"] - #[inline(always)] - pub fn lvdie(&self) -> LvdieR { - LvdieR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - System HVD Reset Enable"] - #[inline(always)] - pub fn hvdre(&self) -> HvdreR { - HvdreR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - System HVD Interrupt Enable"] - #[inline(always)] - pub fn hvdie(&self) -> HvdieR { - HvdieR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 16 - System Voltage Detect Reset Enable Lock"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 16) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - System LVD Reset Enable"] - #[inline(always)] - pub fn lvdre(&mut self) -> LvdreW { - LvdreW::new(self, 0) - } - #[doc = "Bit 1 - System LVD Interrupt Enable"] - #[inline(always)] - pub fn lvdie(&mut self) -> LvdieW { - LvdieW::new(self, 1) - } - #[doc = "Bit 2 - System HVD Reset Enable"] - #[inline(always)] - pub fn hvdre(&mut self) -> HvdreW { - HvdreW::new(self, 2) - } - #[doc = "Bit 3 - System HVD Interrupt Enable"] - #[inline(always)] - pub fn hvdie(&mut self) -> HvdieW { - HvdieW::new(self, 3) - } - #[doc = "Bit 16 - System Voltage Detect Reset Enable Lock"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 16) - } -} -#[doc = "System Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_sys_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_sys_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VdSysCfgSpec; -impl crate::RegisterSpec for VdSysCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`vd_sys_cfg::R`](R) reader structure"] -impl crate::Readable for VdSysCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`vd_sys_cfg::W`](W) writer structure"] -impl crate::Writable for VdSysCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets VD_SYS_CFG to value 0x01"] -impl crate::Resettable for VdSysCfgSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/spc0/verid.rs b/mcxa276-pac/src/spc0/verid.rs deleted file mode 100644 index 931447f66..000000000 --- a/mcxa276-pac/src/spc0/verid.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Standard features"] - Standard = 0, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Standard), - _ => None, - } - } - #[doc = "Standard features"] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == Feature::Standard - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0"] -impl crate::Resettable for VeridSpec {} diff --git a/mcxa276-pac/src/syscon.rs b/mcxa276-pac/src/syscon.rs deleted file mode 100644 index 259c5fce1..000000000 --- a/mcxa276-pac/src/syscon.rs +++ /dev/null @@ -1,497 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x0200], - remap: Remap, - _reserved1: [u8; 0x0c], - ahbmatprio: Ahbmatprio, - _reserved2: [u8; 0x28], - cpu0nstckcal: Cpu0nstckcal, - _reserved3: [u8; 0x08], - nmisrc: Nmisrc, - protlvl: Protlvl, - _reserved5: [u8; 0x0128], - slowclkdiv: Slowclkdiv, - busclkdiv: Busclkdiv, - ahbclkdiv: Ahbclkdiv, - _reserved8: [u8; 0x04], - frohfdiv: Frohfdiv, - frolfdiv: Frolfdiv, - _reserved10: [u8; 0x54], - pll1clkdiv: Pll1clkdiv, - _reserved11: [u8; 0x14], - clkunlock: Clkunlock, - nvm_ctrl: NvmCtrl, - _reserved13: [u8; 0x10], - smart_dmaint: SmartDmaint, - _reserved14: [u8; 0x58], - ram_interleave: RamInterleave, - _reserved15: [u8; 0x0398], - cpustat: Cpustat, - _reserved16: [u8; 0x14], - lpcac_ctrl: LpcacCtrl, - _reserved17: [u8; 0x0110], - pwm0subctl: Pwm0subctl, - pwm1subctl: Pwm1subctl, - ctimerglobalstarten: Ctimerglobalstarten, - ram_ctrl: RamCtrl, - _reserved21: [u8; 0x0218], - gray_code_lsb: GrayCodeLsb, - gray_code_msb: GrayCodeMsb, - binary_code_lsb: BinaryCodeLsb, - binary_code_msb: BinaryCodeMsb, - _reserved25: [u8; 0x02a0], - els_udf: ElsUdf, - _reserved26: [u8; 0x08], - msfcfg: Msfcfg, - els_uid: [ElsUid; 4], - _reserved28: [u8; 0x0c], - rop_state: RopState, - _reserved29: [u8; 0x18], - sram_xen: SramXen, - sram_xen_dp: SramXenDp, - _reserved31: [u8; 0x20], - els_otp_lc_state: ElsOtpLcState, - els_otp_lc_state_dp: ElsOtpLcStateDp, - _reserved33: [u8; 0x0118], - debug_lock_en: DebugLockEn, - debug_features: DebugFeatures, - debug_features_dp: DebugFeaturesDp, - _reserved36: [u8; 0x08], - swd_access_cpu0: SwdAccessCpu0, - _reserved37: [u8; 0x08], - debug_auth_beacon: DebugAuthBeacon, - _reserved38: [u8; 0x2c], - jtag_id: JtagId, - device_type: DeviceType, - device_id0: DeviceId0, - dieid: Dieid, -} -impl RegisterBlock { - #[doc = "0x200 - AHB Matrix Remap Control"] - #[inline(always)] - pub const fn remap(&self) -> &Remap { - &self.remap - } - #[doc = "0x210 - AHB Matrix Priority Control"] - #[inline(always)] - pub const fn ahbmatprio(&self) -> &Ahbmatprio { - &self.ahbmatprio - } - #[doc = "0x23c - Non-Secure CPU0 System Tick Calibration"] - #[inline(always)] - pub const fn cpu0nstckcal(&self) -> &Cpu0nstckcal { - &self.cpu0nstckcal - } - #[doc = "0x248 - NMI Source Select"] - #[inline(always)] - pub const fn nmisrc(&self) -> &Nmisrc { - &self.nmisrc - } - #[doc = "0x24c - Protect Level Control"] - #[inline(always)] - pub const fn protlvl(&self) -> &Protlvl { - &self.protlvl - } - #[doc = "0x378 - SLOW_CLK Clock Divider"] - #[inline(always)] - pub const fn slowclkdiv(&self) -> &Slowclkdiv { - &self.slowclkdiv - } - #[doc = "0x37c - BUS_CLK Clock Divider"] - #[inline(always)] - pub const fn busclkdiv(&self) -> &Busclkdiv { - &self.busclkdiv - } - #[doc = "0x380 - System Clock Divider"] - #[inline(always)] - pub const fn ahbclkdiv(&self) -> &Ahbclkdiv { - &self.ahbclkdiv - } - #[doc = "0x388 - FRO_HF_DIV Clock Divider"] - #[inline(always)] - pub const fn frohfdiv(&self) -> &Frohfdiv { - &self.frohfdiv - } - #[doc = "0x38c - FRO_LF_DIV Clock Divider"] - #[inline(always)] - pub const fn frolfdiv(&self) -> &Frolfdiv { - &self.frolfdiv - } - #[doc = "0x3e4 - PLL1_CLK_DIV Clock Divider"] - #[inline(always)] - pub const fn pll1clkdiv(&self) -> &Pll1clkdiv { - &self.pll1clkdiv - } - #[doc = "0x3fc - Clock Configuration Unlock"] - #[inline(always)] - pub const fn clkunlock(&self) -> &Clkunlock { - &self.clkunlock - } - #[doc = "0x400 - NVM Control"] - #[inline(always)] - pub const fn nvm_ctrl(&self) -> &NvmCtrl { - &self.nvm_ctrl - } - #[doc = "0x414 - SmartDMA Interrupt Hijack"] - #[inline(always)] - pub const fn smart_dmaint(&self) -> &SmartDmaint { - &self.smart_dmaint - } - #[doc = "0x470 - Controls RAM Interleave Integration"] - #[inline(always)] - pub const fn ram_interleave(&self) -> &RamInterleave { - &self.ram_interleave - } - #[doc = "0x80c - CPU Status"] - #[inline(always)] - pub const fn cpustat(&self) -> &Cpustat { - &self.cpustat - } - #[doc = "0x824 - LPCAC Control"] - #[inline(always)] - pub const fn lpcac_ctrl(&self) -> &LpcacCtrl { - &self.lpcac_ctrl - } - #[doc = "0x938 - PWM0 Submodule Control"] - #[inline(always)] - pub const fn pwm0subctl(&self) -> &Pwm0subctl { - &self.pwm0subctl - } - #[doc = "0x93c - PWM1 Submodule Control"] - #[inline(always)] - pub const fn pwm1subctl(&self) -> &Pwm1subctl { - &self.pwm1subctl - } - #[doc = "0x940 - CTIMER Global Start Enable"] - #[inline(always)] - pub const fn ctimerglobalstarten(&self) -> &Ctimerglobalstarten { - &self.ctimerglobalstarten - } - #[doc = "0x944 - RAM Control"] - #[inline(always)] - pub const fn ram_ctrl(&self) -> &RamCtrl { - &self.ram_ctrl - } - #[doc = "0xb60 - Gray to Binary Converter Gray Code \\[31:0\\]"] - #[inline(always)] - pub const fn gray_code_lsb(&self) -> &GrayCodeLsb { - &self.gray_code_lsb - } - #[doc = "0xb64 - Gray to Binary Converter Gray Code \\[41:32\\]"] - #[inline(always)] - pub const fn gray_code_msb(&self) -> &GrayCodeMsb { - &self.gray_code_msb - } - #[doc = "0xb68 - Gray to Binary Converter Binary Code \\[31:0\\]"] - #[inline(always)] - pub const fn binary_code_lsb(&self) -> &BinaryCodeLsb { - &self.binary_code_lsb - } - #[doc = "0xb6c - Gray to Binary Converter Binary Code \\[41:32\\]"] - #[inline(always)] - pub const fn binary_code_msb(&self) -> &BinaryCodeMsb { - &self.binary_code_msb - } - #[doc = "0xe10 - UDF Control"] - #[inline(always)] - pub const fn els_udf(&self) -> &ElsUdf { - &self.els_udf - } - #[doc = "0xe1c - MSF Configuration"] - #[inline(always)] - pub const fn msfcfg(&self) -> &Msfcfg { - &self.msfcfg - } - #[doc = "0xe20..0xe30 - Device UID n"] - #[inline(always)] - pub const fn els_uid(&self, n: usize) -> &ElsUid { - &self.els_uid[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0xe20..0xe30 - Device UID n"] - #[inline(always)] - pub fn els_uid_iter(&self) -> impl Iterator { - self.els_uid.iter() - } - #[doc = "0xe3c - ROP State Register"] - #[inline(always)] - pub const fn rop_state(&self) -> &RopState { - &self.rop_state - } - #[doc = "0xe58 - RAM XEN Control"] - #[inline(always)] - pub const fn sram_xen(&self) -> &SramXen { - &self.sram_xen - } - #[doc = "0xe5c - RAM XEN Control (Duplicate)"] - #[inline(always)] - pub const fn sram_xen_dp(&self) -> &SramXenDp { - &self.sram_xen_dp - } - #[doc = "0xe80 - Life Cycle State Register"] - #[inline(always)] - pub const fn els_otp_lc_state(&self) -> &ElsOtpLcState { - &self.els_otp_lc_state - } - #[doc = "0xe84 - Life Cycle State Register (Duplicate)"] - #[inline(always)] - pub const fn els_otp_lc_state_dp(&self) -> &ElsOtpLcStateDp { - &self.els_otp_lc_state_dp - } - #[doc = "0xfa0 - Control Write Access to Security"] - #[inline(always)] - pub const fn debug_lock_en(&self) -> &DebugLockEn { - &self.debug_lock_en - } - #[doc = "0xfa4 - Cortex Debug Features Control"] - #[inline(always)] - pub const fn debug_features(&self) -> &DebugFeatures { - &self.debug_features - } - #[doc = "0xfa8 - Cortex Debug Features Control (Duplicate)"] - #[inline(always)] - pub const fn debug_features_dp(&self) -> &DebugFeaturesDp { - &self.debug_features_dp - } - #[doc = "0xfb4 - CPU0 Software Debug Access"] - #[inline(always)] - pub const fn swd_access_cpu0(&self) -> &SwdAccessCpu0 { - &self.swd_access_cpu0 - } - #[doc = "0xfc0 - Debug Authentication BEACON"] - #[inline(always)] - pub const fn debug_auth_beacon(&self) -> &DebugAuthBeacon { - &self.debug_auth_beacon - } - #[doc = "0xff0 - JTAG Chip ID"] - #[inline(always)] - pub const fn jtag_id(&self) -> &JtagId { - &self.jtag_id - } - #[doc = "0xff4 - Device Type"] - #[inline(always)] - pub const fn device_type(&self) -> &DeviceType { - &self.device_type - } - #[doc = "0xff8 - Device ID"] - #[inline(always)] - pub const fn device_id0(&self) -> &DeviceId0 { - &self.device_id0 - } - #[doc = "0xffc - Chip Revision ID and Number"] - #[inline(always)] - pub const fn dieid(&self) -> &Dieid { - &self.dieid - } -} -#[doc = "REMAP (rw) register accessor: AHB Matrix Remap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap`] module"] -#[doc(alias = "REMAP")] -pub type Remap = crate::Reg; -#[doc = "AHB Matrix Remap Control"] -pub mod remap; -#[doc = "AHBMATPRIO (rw) register accessor: AHB Matrix Priority Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbmatprio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbmatprio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbmatprio`] module"] -#[doc(alias = "AHBMATPRIO")] -pub type Ahbmatprio = crate::Reg; -#[doc = "AHB Matrix Priority Control"] -pub mod ahbmatprio; -#[doc = "CPU0NSTCKCAL (rw) register accessor: Non-Secure CPU0 System Tick Calibration\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu0nstckcal::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu0nstckcal::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu0nstckcal`] module"] -#[doc(alias = "CPU0NSTCKCAL")] -pub type Cpu0nstckcal = crate::Reg; -#[doc = "Non-Secure CPU0 System Tick Calibration"] -pub mod cpu0nstckcal; -#[doc = "NMISRC (rw) register accessor: NMI Source Select\n\nYou can [`read`](crate::Reg::read) this register and get [`nmisrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmisrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmisrc`] module"] -#[doc(alias = "NMISRC")] -pub type Nmisrc = crate::Reg; -#[doc = "NMI Source Select"] -pub mod nmisrc; -#[doc = "PROTLVL (rw) register accessor: Protect Level Control\n\nYou can [`read`](crate::Reg::read) this register and get [`protlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`protlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@protlvl`] module"] -#[doc(alias = "PROTLVL")] -pub type Protlvl = crate::Reg; -#[doc = "Protect Level Control"] -pub mod protlvl; -#[doc = "SLOWCLKDIV (rw) register accessor: SLOW_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`slowclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slowclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slowclkdiv`] module"] -#[doc(alias = "SLOWCLKDIV")] -pub type Slowclkdiv = crate::Reg; -#[doc = "SLOW_CLK Clock Divider"] -pub mod slowclkdiv; -#[doc = "BUSCLKDIV (rw) register accessor: BUS_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`busclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`busclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@busclkdiv`] module"] -#[doc(alias = "BUSCLKDIV")] -pub type Busclkdiv = crate::Reg; -#[doc = "BUS_CLK Clock Divider"] -pub mod busclkdiv; -#[doc = "AHBCLKDIV (rw) register accessor: System Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbclkdiv`] module"] -#[doc(alias = "AHBCLKDIV")] -pub type Ahbclkdiv = crate::Reg; -#[doc = "System Clock Divider"] -pub mod ahbclkdiv; -#[doc = "FROHFDIV (rw) register accessor: FRO_HF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frohfdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frohfdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frohfdiv`] module"] -#[doc(alias = "FROHFDIV")] -pub type Frohfdiv = crate::Reg; -#[doc = "FRO_HF_DIV Clock Divider"] -pub mod frohfdiv; -#[doc = "FROLFDIV (rw) register accessor: FRO_LF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frolfdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolfdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frolfdiv`] module"] -#[doc(alias = "FROLFDIV")] -pub type Frolfdiv = crate::Reg; -#[doc = "FRO_LF_DIV Clock Divider"] -pub mod frolfdiv; -#[doc = "PLL1CLKDIV (rw) register accessor: PLL1_CLK_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pll1clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll1clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll1clkdiv`] module"] -#[doc(alias = "PLL1CLKDIV")] -pub type Pll1clkdiv = crate::Reg; -#[doc = "PLL1_CLK_DIV Clock Divider"] -pub mod pll1clkdiv; -#[doc = "CLKUNLOCK (rw) register accessor: Clock Configuration Unlock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkunlock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkunlock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkunlock`] module"] -#[doc(alias = "CLKUNLOCK")] -pub type Clkunlock = crate::Reg; -#[doc = "Clock Configuration Unlock"] -pub mod clkunlock; -#[doc = "NVM_CTRL (rw) register accessor: NVM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`nvm_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvm_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nvm_ctrl`] module"] -#[doc(alias = "NVM_CTRL")] -pub type NvmCtrl = crate::Reg; -#[doc = "NVM Control"] -pub mod nvm_ctrl; -#[doc = "SmartDMAINT (rw) register accessor: SmartDMA Interrupt Hijack\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dmaint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dmaint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smart_dmaint`] module"] -#[doc(alias = "SmartDMAINT")] -pub type SmartDmaint = crate::Reg; -#[doc = "SmartDMA Interrupt Hijack"] -pub mod smart_dmaint; -#[doc = "RAM_INTERLEAVE (rw) register accessor: Controls RAM Interleave Integration\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_interleave::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_interleave::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_interleave`] module"] -#[doc(alias = "RAM_INTERLEAVE")] -pub type RamInterleave = crate::Reg; -#[doc = "Controls RAM Interleave Integration"] -pub mod ram_interleave; -#[doc = "CPUSTAT (r) register accessor: CPU Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cpustat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpustat`] module"] -#[doc(alias = "CPUSTAT")] -pub type Cpustat = crate::Reg; -#[doc = "CPU Status"] -pub mod cpustat; -#[doc = "LPCAC_CTRL (rw) register accessor: LPCAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`lpcac_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcac_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpcac_ctrl`] module"] -#[doc(alias = "LPCAC_CTRL")] -pub type LpcacCtrl = crate::Reg; -#[doc = "LPCAC Control"] -pub mod lpcac_ctrl; -#[doc = "PWM0SUBCTL (rw) register accessor: PWM0 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0subctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0subctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0subctl`] module"] -#[doc(alias = "PWM0SUBCTL")] -pub type Pwm0subctl = crate::Reg; -#[doc = "PWM0 Submodule Control"] -pub mod pwm0subctl; -#[doc = "PWM1SUBCTL (rw) register accessor: PWM1 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1subctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1subctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1subctl`] module"] -#[doc(alias = "PWM1SUBCTL")] -pub type Pwm1subctl = crate::Reg; -#[doc = "PWM1 Submodule Control"] -pub mod pwm1subctl; -#[doc = "CTIMERGLOBALSTARTEN (rw) register accessor: CTIMER Global Start Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimerglobalstarten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimerglobalstarten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimerglobalstarten`] module"] -#[doc(alias = "CTIMERGLOBALSTARTEN")] -pub type Ctimerglobalstarten = crate::Reg; -#[doc = "CTIMER Global Start Enable"] -pub mod ctimerglobalstarten; -#[doc = "RAM_CTRL (rw) register accessor: RAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_ctrl`] module"] -#[doc(alias = "RAM_CTRL")] -pub type RamCtrl = crate::Reg; -#[doc = "RAM Control"] -pub mod ram_ctrl; -#[doc = "GRAY_CODE_LSB (rw) register accessor: Gray to Binary Converter Gray Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gray_code_lsb`] module"] -#[doc(alias = "GRAY_CODE_LSB")] -pub type GrayCodeLsb = crate::Reg; -#[doc = "Gray to Binary Converter Gray Code \\[31:0\\]"] -pub mod gray_code_lsb; -#[doc = "GRAY_CODE_MSB (rw) register accessor: Gray to Binary Converter Gray Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gray_code_msb`] module"] -#[doc(alias = "GRAY_CODE_MSB")] -pub type GrayCodeMsb = crate::Reg; -#[doc = "Gray to Binary Converter Gray Code \\[41:32\\]"] -pub mod gray_code_msb; -#[doc = "BINARY_CODE_LSB (r) register accessor: Gray to Binary Converter Binary Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_lsb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@binary_code_lsb`] module"] -#[doc(alias = "BINARY_CODE_LSB")] -pub type BinaryCodeLsb = crate::Reg; -#[doc = "Gray to Binary Converter Binary Code \\[31:0\\]"] -pub mod binary_code_lsb; -#[doc = "BINARY_CODE_MSB (r) register accessor: Gray to Binary Converter Binary Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_msb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@binary_code_msb`] module"] -#[doc(alias = "BINARY_CODE_MSB")] -pub type BinaryCodeMsb = crate::Reg; -#[doc = "Gray to Binary Converter Binary Code \\[41:32\\]"] -pub mod binary_code_msb; -#[doc = "ELS_UDF (rw) register accessor: UDF Control\n\nYou can [`read`](crate::Reg::read) this register and get [`els_udf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_udf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_udf`] module"] -#[doc(alias = "ELS_UDF")] -pub type ElsUdf = crate::Reg; -#[doc = "UDF Control"] -pub mod els_udf; -#[doc = "MSFCFG (rw) register accessor: MSF Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`msfcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msfcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msfcfg`] module"] -#[doc(alias = "MSFCFG")] -pub type Msfcfg = crate::Reg; -#[doc = "MSF Configuration"] -pub mod msfcfg; -#[doc = "ELS_UID (rw) register accessor: Device UID n\n\nYou can [`read`](crate::Reg::read) this register and get [`els_uid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_uid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_uid`] module"] -#[doc(alias = "ELS_UID")] -pub type ElsUid = crate::Reg; -#[doc = "Device UID n"] -pub mod els_uid; -#[doc = "ROP_STATE (r) register accessor: ROP State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rop_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rop_state`] module"] -#[doc(alias = "ROP_STATE")] -pub type RopState = crate::Reg; -#[doc = "ROP State Register"] -pub mod rop_state; -#[doc = "SRAM_XEN (rw) register accessor: RAM XEN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_xen`] module"] -#[doc(alias = "SRAM_XEN")] -pub type SramXen = crate::Reg; -#[doc = "RAM XEN Control"] -pub mod sram_xen; -#[doc = "SRAM_XEN_DP (rw) register accessor: RAM XEN Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen_dp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen_dp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_xen_dp`] module"] -#[doc(alias = "SRAM_XEN_DP")] -pub type SramXenDp = crate::Reg; -#[doc = "RAM XEN Control (Duplicate)"] -pub mod sram_xen_dp; -#[doc = "ELS_OTP_LC_STATE (r) register accessor: Life Cycle State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_otp_lc_state`] module"] -#[doc(alias = "ELS_OTP_LC_STATE")] -pub type ElsOtpLcState = crate::Reg; -#[doc = "Life Cycle State Register"] -pub mod els_otp_lc_state; -#[doc = "ELS_OTP_LC_STATE_DP (r) register accessor: Life Cycle State Register (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state_dp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_otp_lc_state_dp`] module"] -#[doc(alias = "ELS_OTP_LC_STATE_DP")] -pub type ElsOtpLcStateDp = crate::Reg; -#[doc = "Life Cycle State Register (Duplicate)"] -pub mod els_otp_lc_state_dp; -#[doc = "DEBUG_LOCK_EN (rw) register accessor: Control Write Access to Security\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_lock_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_lock_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_lock_en`] module"] -#[doc(alias = "DEBUG_LOCK_EN")] -pub type DebugLockEn = crate::Reg; -#[doc = "Control Write Access to Security"] -pub mod debug_lock_en; -#[doc = "DEBUG_FEATURES (rw) register accessor: Cortex Debug Features Control\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_features`] module"] -#[doc(alias = "DEBUG_FEATURES")] -pub type DebugFeatures = crate::Reg; -#[doc = "Cortex Debug Features Control"] -pub mod debug_features; -#[doc = "DEBUG_FEATURES_DP (rw) register accessor: Cortex Debug Features Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features_dp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features_dp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_features_dp`] module"] -#[doc(alias = "DEBUG_FEATURES_DP")] -pub type DebugFeaturesDp = crate::Reg; -#[doc = "Cortex Debug Features Control (Duplicate)"] -pub mod debug_features_dp; -#[doc = "SWD_ACCESS_CPU0 (rw) register accessor: CPU0 Software Debug Access\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_access_cpu0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_access_cpu0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swd_access_cpu0`] module"] -#[doc(alias = "SWD_ACCESS_CPU0")] -pub type SwdAccessCpu0 = crate::Reg; -#[doc = "CPU0 Software Debug Access"] -pub mod swd_access_cpu0; -#[doc = "DEBUG_AUTH_BEACON (rw) register accessor: Debug Authentication BEACON\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_auth_beacon::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_auth_beacon::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_auth_beacon`] module"] -#[doc(alias = "DEBUG_AUTH_BEACON")] -pub type DebugAuthBeacon = crate::Reg; -#[doc = "Debug Authentication BEACON"] -pub mod debug_auth_beacon; -#[doc = "JTAG_ID (r) register accessor: JTAG Chip ID\n\nYou can [`read`](crate::Reg::read) this register and get [`jtag_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_id`] module"] -#[doc(alias = "JTAG_ID")] -pub type JtagId = crate::Reg; -#[doc = "JTAG Chip ID"] -pub mod jtag_id; -#[doc = "DEVICE_TYPE (r) register accessor: Device Type\n\nYou can [`read`](crate::Reg::read) this register and get [`device_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_type`] module"] -#[doc(alias = "DEVICE_TYPE")] -pub type DeviceType = crate::Reg; -#[doc = "Device Type"] -pub mod device_type; -#[doc = "DEVICE_ID0 (r) register accessor: Device ID\n\nYou can [`read`](crate::Reg::read) this register and get [`device_id0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_id0`] module"] -#[doc(alias = "DEVICE_ID0")] -pub type DeviceId0 = crate::Reg; -#[doc = "Device ID"] -pub mod device_id0; -#[doc = "DIEID (r) register accessor: Chip Revision ID and Number\n\nYou can [`read`](crate::Reg::read) this register and get [`dieid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieid`] module"] -#[doc(alias = "DIEID")] -pub type Dieid = crate::Reg; -#[doc = "Chip Revision ID and Number"] -pub mod dieid; diff --git a/mcxa276-pac/src/syscon/ahbclkdiv.rs b/mcxa276-pac/src/syscon/ahbclkdiv.rs deleted file mode 100644 index 7b2fe415b..000000000 --- a/mcxa276-pac/src/syscon/ahbclkdiv.rs +++ /dev/null @@ -1,76 +0,0 @@ -#[doc = "Register `AHBCLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `AHBCLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Clock divider value"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Clock divider value"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - Stable = 0, - #[doc = "1: Clock frequency is not stable"] - Ongoing = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::Stable, - true => Unstab::Ongoing, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_stable(&self) -> bool { - *self == Unstab::Stable - } - #[doc = "Clock frequency is not stable"] - #[inline(always)] - pub fn is_ongoing(&self) -> bool { - *self == Unstab::Ongoing - } -} -impl R { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } -} -#[doc = "System Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AhbclkdivSpec; -impl crate::RegisterSpec for AhbclkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ahbclkdiv::R`](R) reader structure"] -impl crate::Readable for AhbclkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`ahbclkdiv::W`](W) writer structure"] -impl crate::Writable for AhbclkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets AHBCLKDIV to value 0"] -impl crate::Resettable for AhbclkdivSpec {} diff --git a/mcxa276-pac/src/syscon/ahbmatprio.rs b/mcxa276-pac/src/syscon/ahbmatprio.rs deleted file mode 100644 index 83422a33e..000000000 --- a/mcxa276-pac/src/syscon/ahbmatprio.rs +++ /dev/null @@ -1,695 +0,0 @@ -#[doc = "Register `AHBMATPRIO` reader"] -pub type R = crate::R; -#[doc = "Register `AHBMATPRIO` writer"] -pub type W = crate::W; -#[doc = "CPU0 C-AHB bus master priority level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu0Cbus { - #[doc = "0: level 0"] - Level0 = 0, - #[doc = "1: level 1"] - Level1 = 1, - #[doc = "2: level 2"] - Level2 = 2, - #[doc = "3: level 3"] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu0Cbus) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu0Cbus { - type Ux = u8; -} -impl crate::IsEnum for Cpu0Cbus {} -#[doc = "Field `CPU0_CBUS` reader - CPU0 C-AHB bus master priority level"] -pub type Cpu0CbusR = crate::FieldReader; -impl Cpu0CbusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpu0Cbus { - match self.bits { - 0 => Cpu0Cbus::Level0, - 1 => Cpu0Cbus::Level1, - 2 => Cpu0Cbus::Level2, - 3 => Cpu0Cbus::Level3, - _ => unreachable!(), - } - } - #[doc = "level 0"] - #[inline(always)] - pub fn is_level0(&self) -> bool { - *self == Cpu0Cbus::Level0 - } - #[doc = "level 1"] - #[inline(always)] - pub fn is_level1(&self) -> bool { - *self == Cpu0Cbus::Level1 - } - #[doc = "level 2"] - #[inline(always)] - pub fn is_level2(&self) -> bool { - *self == Cpu0Cbus::Level2 - } - #[doc = "level 3"] - #[inline(always)] - pub fn is_level3(&self) -> bool { - *self == Cpu0Cbus::Level3 - } -} -#[doc = "Field `CPU0_CBUS` writer - CPU0 C-AHB bus master priority level"] -pub type Cpu0CbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Cbus, crate::Safe>; -impl<'a, REG> Cpu0CbusW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "level 0"] - #[inline(always)] - pub fn level0(self) -> &'a mut crate::W { - self.variant(Cpu0Cbus::Level0) - } - #[doc = "level 1"] - #[inline(always)] - pub fn level1(self) -> &'a mut crate::W { - self.variant(Cpu0Cbus::Level1) - } - #[doc = "level 2"] - #[inline(always)] - pub fn level2(self) -> &'a mut crate::W { - self.variant(Cpu0Cbus::Level2) - } - #[doc = "level 3"] - #[inline(always)] - pub fn level3(self) -> &'a mut crate::W { - self.variant(Cpu0Cbus::Level3) - } -} -#[doc = "CPU0 S-AHB bus master priority level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu0Sbus { - #[doc = "0: level 0"] - Level0 = 0, - #[doc = "1: level 1"] - Level1 = 1, - #[doc = "2: level 2"] - Level2 = 2, - #[doc = "3: level 3"] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu0Sbus) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu0Sbus { - type Ux = u8; -} -impl crate::IsEnum for Cpu0Sbus {} -#[doc = "Field `CPU0_SBUS` reader - CPU0 S-AHB bus master priority level"] -pub type Cpu0SbusR = crate::FieldReader; -impl Cpu0SbusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpu0Sbus { - match self.bits { - 0 => Cpu0Sbus::Level0, - 1 => Cpu0Sbus::Level1, - 2 => Cpu0Sbus::Level2, - 3 => Cpu0Sbus::Level3, - _ => unreachable!(), - } - } - #[doc = "level 0"] - #[inline(always)] - pub fn is_level0(&self) -> bool { - *self == Cpu0Sbus::Level0 - } - #[doc = "level 1"] - #[inline(always)] - pub fn is_level1(&self) -> bool { - *self == Cpu0Sbus::Level1 - } - #[doc = "level 2"] - #[inline(always)] - pub fn is_level2(&self) -> bool { - *self == Cpu0Sbus::Level2 - } - #[doc = "level 3"] - #[inline(always)] - pub fn is_level3(&self) -> bool { - *self == Cpu0Sbus::Level3 - } -} -#[doc = "Field `CPU0_SBUS` writer - CPU0 S-AHB bus master priority level"] -pub type Cpu0SbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Sbus, crate::Safe>; -impl<'a, REG> Cpu0SbusW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "level 0"] - #[inline(always)] - pub fn level0(self) -> &'a mut crate::W { - self.variant(Cpu0Sbus::Level0) - } - #[doc = "level 1"] - #[inline(always)] - pub fn level1(self) -> &'a mut crate::W { - self.variant(Cpu0Sbus::Level1) - } - #[doc = "level 2"] - #[inline(always)] - pub fn level2(self) -> &'a mut crate::W { - self.variant(Cpu0Sbus::Level2) - } - #[doc = "level 3"] - #[inline(always)] - pub fn level3(self) -> &'a mut crate::W { - self.variant(Cpu0Sbus::Level3) - } -} -#[doc = "SmartDMA-I bus master priority level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu1CbusSmartDmaI { - #[doc = "0: level 0"] - Level0 = 0, - #[doc = "1: level 1"] - Level1 = 1, - #[doc = "2: level 2"] - Level2 = 2, - #[doc = "3: level 3"] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu1CbusSmartDmaI) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu1CbusSmartDmaI { - type Ux = u8; -} -impl crate::IsEnum for Cpu1CbusSmartDmaI {} -#[doc = "Field `CPU1_CBUS_SmartDMA_I` reader - SmartDMA-I bus master priority level"] -pub type Cpu1CbusSmartDmaIR = crate::FieldReader; -impl Cpu1CbusSmartDmaIR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpu1CbusSmartDmaI { - match self.bits { - 0 => Cpu1CbusSmartDmaI::Level0, - 1 => Cpu1CbusSmartDmaI::Level1, - 2 => Cpu1CbusSmartDmaI::Level2, - 3 => Cpu1CbusSmartDmaI::Level3, - _ => unreachable!(), - } - } - #[doc = "level 0"] - #[inline(always)] - pub fn is_level0(&self) -> bool { - *self == Cpu1CbusSmartDmaI::Level0 - } - #[doc = "level 1"] - #[inline(always)] - pub fn is_level1(&self) -> bool { - *self == Cpu1CbusSmartDmaI::Level1 - } - #[doc = "level 2"] - #[inline(always)] - pub fn is_level2(&self) -> bool { - *self == Cpu1CbusSmartDmaI::Level2 - } - #[doc = "level 3"] - #[inline(always)] - pub fn is_level3(&self) -> bool { - *self == Cpu1CbusSmartDmaI::Level3 - } -} -#[doc = "Field `CPU1_CBUS_SmartDMA_I` writer - SmartDMA-I bus master priority level"] -pub type Cpu1CbusSmartDmaIW<'a, REG> = - crate::FieldWriter<'a, REG, 2, Cpu1CbusSmartDmaI, crate::Safe>; -impl<'a, REG> Cpu1CbusSmartDmaIW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "level 0"] - #[inline(always)] - pub fn level0(self) -> &'a mut crate::W { - self.variant(Cpu1CbusSmartDmaI::Level0) - } - #[doc = "level 1"] - #[inline(always)] - pub fn level1(self) -> &'a mut crate::W { - self.variant(Cpu1CbusSmartDmaI::Level1) - } - #[doc = "level 2"] - #[inline(always)] - pub fn level2(self) -> &'a mut crate::W { - self.variant(Cpu1CbusSmartDmaI::Level2) - } - #[doc = "level 3"] - #[inline(always)] - pub fn level3(self) -> &'a mut crate::W { - self.variant(Cpu1CbusSmartDmaI::Level3) - } -} -#[doc = "SmartDMA-D bus master priority level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu1SbusSmartDmaD { - #[doc = "0: level 0"] - Level0 = 0, - #[doc = "1: level 1"] - Level1 = 1, - #[doc = "2: level 2"] - Level2 = 2, - #[doc = "3: level 3"] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu1SbusSmartDmaD) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu1SbusSmartDmaD { - type Ux = u8; -} -impl crate::IsEnum for Cpu1SbusSmartDmaD {} -#[doc = "Field `CPU1_SBUS_SmartDMA_D` reader - SmartDMA-D bus master priority level"] -pub type Cpu1SbusSmartDmaDR = crate::FieldReader; -impl Cpu1SbusSmartDmaDR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpu1SbusSmartDmaD { - match self.bits { - 0 => Cpu1SbusSmartDmaD::Level0, - 1 => Cpu1SbusSmartDmaD::Level1, - 2 => Cpu1SbusSmartDmaD::Level2, - 3 => Cpu1SbusSmartDmaD::Level3, - _ => unreachable!(), - } - } - #[doc = "level 0"] - #[inline(always)] - pub fn is_level0(&self) -> bool { - *self == Cpu1SbusSmartDmaD::Level0 - } - #[doc = "level 1"] - #[inline(always)] - pub fn is_level1(&self) -> bool { - *self == Cpu1SbusSmartDmaD::Level1 - } - #[doc = "level 2"] - #[inline(always)] - pub fn is_level2(&self) -> bool { - *self == Cpu1SbusSmartDmaD::Level2 - } - #[doc = "level 3"] - #[inline(always)] - pub fn is_level3(&self) -> bool { - *self == Cpu1SbusSmartDmaD::Level3 - } -} -#[doc = "Field `CPU1_SBUS_SmartDMA_D` writer - SmartDMA-D bus master priority level"] -pub type Cpu1SbusSmartDmaDW<'a, REG> = - crate::FieldWriter<'a, REG, 2, Cpu1SbusSmartDmaD, crate::Safe>; -impl<'a, REG> Cpu1SbusSmartDmaDW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "level 0"] - #[inline(always)] - pub fn level0(self) -> &'a mut crate::W { - self.variant(Cpu1SbusSmartDmaD::Level0) - } - #[doc = "level 1"] - #[inline(always)] - pub fn level1(self) -> &'a mut crate::W { - self.variant(Cpu1SbusSmartDmaD::Level1) - } - #[doc = "level 2"] - #[inline(always)] - pub fn level2(self) -> &'a mut crate::W { - self.variant(Cpu1SbusSmartDmaD::Level2) - } - #[doc = "level 3"] - #[inline(always)] - pub fn level3(self) -> &'a mut crate::W { - self.variant(Cpu1SbusSmartDmaD::Level3) - } -} -#[doc = "DMA0 controller bus master priority level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dma0 { - #[doc = "0: level 0"] - Level0 = 0, - #[doc = "1: level 1"] - Level1 = 1, - #[doc = "2: level 2"] - Level2 = 2, - #[doc = "3: level 3"] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dma0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dma0 { - type Ux = u8; -} -impl crate::IsEnum for Dma0 {} -#[doc = "Field `DMA0` reader - DMA0 controller bus master priority level"] -pub type Dma0R = crate::FieldReader; -impl Dma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dma0 { - match self.bits { - 0 => Dma0::Level0, - 1 => Dma0::Level1, - 2 => Dma0::Level2, - 3 => Dma0::Level3, - _ => unreachable!(), - } - } - #[doc = "level 0"] - #[inline(always)] - pub fn is_level0(&self) -> bool { - *self == Dma0::Level0 - } - #[doc = "level 1"] - #[inline(always)] - pub fn is_level1(&self) -> bool { - *self == Dma0::Level1 - } - #[doc = "level 2"] - #[inline(always)] - pub fn is_level2(&self) -> bool { - *self == Dma0::Level2 - } - #[doc = "level 3"] - #[inline(always)] - pub fn is_level3(&self) -> bool { - *self == Dma0::Level3 - } -} -#[doc = "Field `DMA0` writer - DMA0 controller bus master priority level"] -pub type Dma0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Dma0, crate::Safe>; -impl<'a, REG> Dma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "level 0"] - #[inline(always)] - pub fn level0(self) -> &'a mut crate::W { - self.variant(Dma0::Level0) - } - #[doc = "level 1"] - #[inline(always)] - pub fn level1(self) -> &'a mut crate::W { - self.variant(Dma0::Level1) - } - #[doc = "level 2"] - #[inline(always)] - pub fn level2(self) -> &'a mut crate::W { - self.variant(Dma0::Level2) - } - #[doc = "level 3"] - #[inline(always)] - pub fn level3(self) -> &'a mut crate::W { - self.variant(Dma0::Level3) - } -} -#[doc = "PKC and ELS bus master priority level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum PkcEls { - #[doc = "0: level 0"] - Level0 = 0, - #[doc = "1: level 1"] - Level1 = 1, - #[doc = "2: level 2"] - Level2 = 2, - #[doc = "3: level 3"] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: PkcEls) -> Self { - variant as _ - } -} -impl crate::FieldSpec for PkcEls { - type Ux = u8; -} -impl crate::IsEnum for PkcEls {} -#[doc = "Field `PKC_ELS` reader - PKC and ELS bus master priority level"] -pub type PkcElsR = crate::FieldReader; -impl PkcElsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> PkcEls { - match self.bits { - 0 => PkcEls::Level0, - 1 => PkcEls::Level1, - 2 => PkcEls::Level2, - 3 => PkcEls::Level3, - _ => unreachable!(), - } - } - #[doc = "level 0"] - #[inline(always)] - pub fn is_level0(&self) -> bool { - *self == PkcEls::Level0 - } - #[doc = "level 1"] - #[inline(always)] - pub fn is_level1(&self) -> bool { - *self == PkcEls::Level1 - } - #[doc = "level 2"] - #[inline(always)] - pub fn is_level2(&self) -> bool { - *self == PkcEls::Level2 - } - #[doc = "level 3"] - #[inline(always)] - pub fn is_level3(&self) -> bool { - *self == PkcEls::Level3 - } -} -#[doc = "Field `PKC_ELS` writer - PKC and ELS bus master priority level"] -pub type PkcElsW<'a, REG> = crate::FieldWriter<'a, REG, 2, PkcEls, crate::Safe>; -impl<'a, REG> PkcElsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "level 0"] - #[inline(always)] - pub fn level0(self) -> &'a mut crate::W { - self.variant(PkcEls::Level0) - } - #[doc = "level 1"] - #[inline(always)] - pub fn level1(self) -> &'a mut crate::W { - self.variant(PkcEls::Level1) - } - #[doc = "level 2"] - #[inline(always)] - pub fn level2(self) -> &'a mut crate::W { - self.variant(PkcEls::Level2) - } - #[doc = "level 3"] - #[inline(always)] - pub fn level3(self) -> &'a mut crate::W { - self.variant(PkcEls::Level3) - } -} -#[doc = "USB-FS bus master priority level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum UsbFsEnet { - #[doc = "0: level 0"] - Level0 = 0, - #[doc = "1: level 1"] - Level1 = 1, - #[doc = "2: level 2"] - Level2 = 2, - #[doc = "3: level 3"] - Level3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: UsbFsEnet) -> Self { - variant as _ - } -} -impl crate::FieldSpec for UsbFsEnet { - type Ux = u8; -} -impl crate::IsEnum for UsbFsEnet {} -#[doc = "Field `USB_FS_ENET` reader - USB-FS bus master priority level"] -pub type UsbFsEnetR = crate::FieldReader; -impl UsbFsEnetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> UsbFsEnet { - match self.bits { - 0 => UsbFsEnet::Level0, - 1 => UsbFsEnet::Level1, - 2 => UsbFsEnet::Level2, - 3 => UsbFsEnet::Level3, - _ => unreachable!(), - } - } - #[doc = "level 0"] - #[inline(always)] - pub fn is_level0(&self) -> bool { - *self == UsbFsEnet::Level0 - } - #[doc = "level 1"] - #[inline(always)] - pub fn is_level1(&self) -> bool { - *self == UsbFsEnet::Level1 - } - #[doc = "level 2"] - #[inline(always)] - pub fn is_level2(&self) -> bool { - *self == UsbFsEnet::Level2 - } - #[doc = "level 3"] - #[inline(always)] - pub fn is_level3(&self) -> bool { - *self == UsbFsEnet::Level3 - } -} -#[doc = "Field `USB_FS_ENET` writer - USB-FS bus master priority level"] -pub type UsbFsEnetW<'a, REG> = crate::FieldWriter<'a, REG, 2, UsbFsEnet, crate::Safe>; -impl<'a, REG> UsbFsEnetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "level 0"] - #[inline(always)] - pub fn level0(self) -> &'a mut crate::W { - self.variant(UsbFsEnet::Level0) - } - #[doc = "level 1"] - #[inline(always)] - pub fn level1(self) -> &'a mut crate::W { - self.variant(UsbFsEnet::Level1) - } - #[doc = "level 2"] - #[inline(always)] - pub fn level2(self) -> &'a mut crate::W { - self.variant(UsbFsEnet::Level2) - } - #[doc = "level 3"] - #[inline(always)] - pub fn level3(self) -> &'a mut crate::W { - self.variant(UsbFsEnet::Level3) - } -} -impl R { - #[doc = "Bits 0:1 - CPU0 C-AHB bus master priority level"] - #[inline(always)] - pub fn cpu0_cbus(&self) -> Cpu0CbusR { - Cpu0CbusR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - CPU0 S-AHB bus master priority level"] - #[inline(always)] - pub fn cpu0_sbus(&self) -> Cpu0SbusR { - Cpu0SbusR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - SmartDMA-I bus master priority level"] - #[inline(always)] - pub fn cpu1_cbus_smart_dma_i(&self) -> Cpu1CbusSmartDmaIR { - Cpu1CbusSmartDmaIR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - SmartDMA-D bus master priority level"] - #[inline(always)] - pub fn cpu1_sbus_smart_dma_d(&self) -> Cpu1SbusSmartDmaDR { - Cpu1SbusSmartDmaDR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - DMA0 controller bus master priority level"] - #[inline(always)] - pub fn dma0(&self) -> Dma0R { - Dma0R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 12:13 - PKC and ELS bus master priority level"] - #[inline(always)] - pub fn pkc_els(&self) -> PkcElsR { - PkcElsR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 24:25 - USB-FS bus master priority level"] - #[inline(always)] - pub fn usb_fs_enet(&self) -> UsbFsEnetR { - UsbFsEnetR::new(((self.bits >> 24) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - CPU0 C-AHB bus master priority level"] - #[inline(always)] - pub fn cpu0_cbus(&mut self) -> Cpu0CbusW { - Cpu0CbusW::new(self, 0) - } - #[doc = "Bits 2:3 - CPU0 S-AHB bus master priority level"] - #[inline(always)] - pub fn cpu0_sbus(&mut self) -> Cpu0SbusW { - Cpu0SbusW::new(self, 2) - } - #[doc = "Bits 4:5 - SmartDMA-I bus master priority level"] - #[inline(always)] - pub fn cpu1_cbus_smart_dma_i(&mut self) -> Cpu1CbusSmartDmaIW { - Cpu1CbusSmartDmaIW::new(self, 4) - } - #[doc = "Bits 6:7 - SmartDMA-D bus master priority level"] - #[inline(always)] - pub fn cpu1_sbus_smart_dma_d(&mut self) -> Cpu1SbusSmartDmaDW { - Cpu1SbusSmartDmaDW::new(self, 6) - } - #[doc = "Bits 8:9 - DMA0 controller bus master priority level"] - #[inline(always)] - pub fn dma0(&mut self) -> Dma0W { - Dma0W::new(self, 8) - } - #[doc = "Bits 12:13 - PKC and ELS bus master priority level"] - #[inline(always)] - pub fn pkc_els(&mut self) -> PkcElsW { - PkcElsW::new(self, 12) - } - #[doc = "Bits 24:25 - USB-FS bus master priority level"] - #[inline(always)] - pub fn usb_fs_enet(&mut self) -> UsbFsEnetW { - UsbFsEnetW::new(self, 24) - } -} -#[doc = "AHB Matrix Priority Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbmatprio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbmatprio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AhbmatprioSpec; -impl crate::RegisterSpec for AhbmatprioSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ahbmatprio::R`](R) reader structure"] -impl crate::Readable for AhbmatprioSpec {} -#[doc = "`write(|w| ..)` method takes [`ahbmatprio::W`](W) writer structure"] -impl crate::Writable for AhbmatprioSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets AHBMATPRIO to value 0"] -impl crate::Resettable for AhbmatprioSpec {} diff --git a/mcxa276-pac/src/syscon/binary_code_lsb.rs b/mcxa276-pac/src/syscon/binary_code_lsb.rs deleted file mode 100644 index 1af5e17ce..000000000 --- a/mcxa276-pac/src/syscon/binary_code_lsb.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `BINARY_CODE_LSB` reader"] -pub type R = crate::R; -#[doc = "Field `code_bin_31_0` reader - Binary code \\[31:0\\]"] -pub type CodeBin31_0R = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Binary code \\[31:0\\]"] - #[inline(always)] - pub fn code_bin_31_0(&self) -> CodeBin31_0R { - CodeBin31_0R::new(self.bits) - } -} -#[doc = "Gray to Binary Converter Binary Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_lsb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct BinaryCodeLsbSpec; -impl crate::RegisterSpec for BinaryCodeLsbSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`binary_code_lsb::R`](R) reader structure"] -impl crate::Readable for BinaryCodeLsbSpec {} -#[doc = "`reset()` method sets BINARY_CODE_LSB to value 0"] -impl crate::Resettable for BinaryCodeLsbSpec {} diff --git a/mcxa276-pac/src/syscon/binary_code_msb.rs b/mcxa276-pac/src/syscon/binary_code_msb.rs deleted file mode 100644 index f5d1bba17..000000000 --- a/mcxa276-pac/src/syscon/binary_code_msb.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `BINARY_CODE_MSB` reader"] -pub type R = crate::R; -#[doc = "Field `code_bin_41_32` reader - Binary code \\[41:32\\]"] -pub type CodeBin41_32R = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - Binary code \\[41:32\\]"] - #[inline(always)] - pub fn code_bin_41_32(&self) -> CodeBin41_32R { - CodeBin41_32R::new((self.bits & 0x03ff) as u16) - } -} -#[doc = "Gray to Binary Converter Binary Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_msb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct BinaryCodeMsbSpec; -impl crate::RegisterSpec for BinaryCodeMsbSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`binary_code_msb::R`](R) reader structure"] -impl crate::Readable for BinaryCodeMsbSpec {} -#[doc = "`reset()` method sets BINARY_CODE_MSB to value 0"] -impl crate::Resettable for BinaryCodeMsbSpec {} diff --git a/mcxa276-pac/src/syscon/busclkdiv.rs b/mcxa276-pac/src/syscon/busclkdiv.rs deleted file mode 100644 index 290ca9b2d..000000000 --- a/mcxa276-pac/src/syscon/busclkdiv.rs +++ /dev/null @@ -1,197 +0,0 @@ -#[doc = "Register `BUSCLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `BUSCLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Clock divider value"] -pub type DivR = crate::FieldReader; -#[doc = "Resets the divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider is not reset"] - Released = 0, - #[doc = "1: Divider is reset"] - Asserted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` reader - Resets the divider counter"] -pub type ResetR = crate::BitReader; -impl ResetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reset { - match self.bits { - false => Reset::Released, - true => Reset::Asserted, - } - } - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn is_released(&self) -> bool { - *self == Reset::Released - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn is_asserted(&self) -> bool { - *self == Reset::Asserted - } -} -#[doc = "Field `RESET` writer - Resets the divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn released(self) -> &'a mut crate::W { - self.variant(Reset::Released) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn asserted(self) -> &'a mut crate::W { - self.variant(Reset::Asserted) - } -} -#[doc = "Halts the divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - Run = 0, - #[doc = "1: Divider clock is stopped"] - Halt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halts the divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::Run, - true => Halt::Halt, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_run(&self) -> bool { - *self == Halt::Run - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_halt(&self) -> bool { - *self == Halt::Halt - } -} -#[doc = "Field `HALT` writer - Halts the divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn run(self) -> &'a mut crate::W { - self.variant(Halt::Run) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn halt(self) -> &'a mut crate::W { - self.variant(Halt::Halt) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - Stable = 0, - #[doc = "1: Clock frequency is not stable"] - Ongoing = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::Stable, - true => Unstab::Ongoing, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_stable(&self) -> bool { - *self == Unstab::Stable - } - #[doc = "Clock frequency is not stable"] - #[inline(always)] - pub fn is_ongoing(&self) -> bool { - *self == Unstab::Ongoing - } -} -impl R { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&self) -> ResetR { - ResetR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "BUS_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`busclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`busclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct BusclkdivSpec; -impl crate::RegisterSpec for BusclkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`busclkdiv::R`](R) reader structure"] -impl crate::Readable for BusclkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`busclkdiv::W`](W) writer structure"] -impl crate::Writable for BusclkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BUSCLKDIV to value 0x01"] -impl crate::Resettable for BusclkdivSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/syscon/clkunlock.rs b/mcxa276-pac/src/syscon/clkunlock.rs deleted file mode 100644 index 9ed9c9b9c..000000000 --- a/mcxa276-pac/src/syscon/clkunlock.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `CLKUNLOCK` reader"] -pub type R = crate::R; -#[doc = "Register `CLKUNLOCK` writer"] -pub type W = crate::W; -#[doc = "Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unlock { - #[doc = "0: Updates are allowed to all clock configuration registers"] - Enable = 0, - #[doc = "1: Freezes all clock configuration registers update."] - Freeze = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unlock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNLOCK` reader - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] -pub type UnlockR = crate::BitReader; -impl UnlockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unlock { - match self.bits { - false => Unlock::Enable, - true => Unlock::Freeze, - } - } - #[doc = "Updates are allowed to all clock configuration registers"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Unlock::Enable - } - #[doc = "Freezes all clock configuration registers update."] - #[inline(always)] - pub fn is_freeze(&self) -> bool { - *self == Unlock::Freeze - } -} -#[doc = "Field `UNLOCK` writer - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] -pub type UnlockW<'a, REG> = crate::BitWriter<'a, REG, Unlock>; -impl<'a, REG> UnlockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Updates are allowed to all clock configuration registers"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Unlock::Enable) - } - #[doc = "Freezes all clock configuration registers update."] - #[inline(always)] - pub fn freeze(self) -> &'a mut crate::W { - self.variant(Unlock::Freeze) - } -} -impl R { - #[doc = "Bit 0 - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] - #[inline(always)] - pub fn unlock(&self) -> UnlockR { - UnlockR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)"] - #[inline(always)] - pub fn unlock(&mut self) -> UnlockW { - UnlockW::new(self, 0) - } -} -#[doc = "Clock Configuration Unlock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkunlock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkunlock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ClkunlockSpec; -impl crate::RegisterSpec for ClkunlockSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`clkunlock::R`](R) reader structure"] -impl crate::Readable for ClkunlockSpec {} -#[doc = "`write(|w| ..)` method takes [`clkunlock::W`](W) writer structure"] -impl crate::Writable for ClkunlockSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CLKUNLOCK to value 0"] -impl crate::Resettable for ClkunlockSpec {} diff --git a/mcxa276-pac/src/syscon/cpu0nstckcal.rs b/mcxa276-pac/src/syscon/cpu0nstckcal.rs deleted file mode 100644 index 626c2e4f5..000000000 --- a/mcxa276-pac/src/syscon/cpu0nstckcal.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `CPU0NSTCKCAL` reader"] -pub type R = crate::R; -#[doc = "Register `CPU0NSTCKCAL` writer"] -pub type W = crate::W; -#[doc = "Field `TENMS` reader - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] -pub type TenmsR = crate::FieldReader; -#[doc = "Field `TENMS` writer - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] -pub type TenmsW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; -#[doc = "Indicates whether the TENMS value is exact.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Skew { - #[doc = "0: TENMS value is exact"] - Exact = 0, - #[doc = "1: TENMS value is not exact or not given"] - Inexact = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Skew) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SKEW` reader - Indicates whether the TENMS value is exact."] -pub type SkewR = crate::BitReader; -impl SkewR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Skew { - match self.bits { - false => Skew::Exact, - true => Skew::Inexact, - } - } - #[doc = "TENMS value is exact"] - #[inline(always)] - pub fn is_exact(&self) -> bool { - *self == Skew::Exact - } - #[doc = "TENMS value is not exact or not given"] - #[inline(always)] - pub fn is_inexact(&self) -> bool { - *self == Skew::Inexact - } -} -#[doc = "Field `SKEW` writer - Indicates whether the TENMS value is exact."] -pub type SkewW<'a, REG> = crate::BitWriter<'a, REG, Skew>; -impl<'a, REG> SkewW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "TENMS value is exact"] - #[inline(always)] - pub fn exact(self) -> &'a mut crate::W { - self.variant(Skew::Exact) - } - #[doc = "TENMS value is not exact or not given"] - #[inline(always)] - pub fn inexact(self) -> &'a mut crate::W { - self.variant(Skew::Inexact) - } -} -#[doc = "Indicates whether the device provides a reference clock to the processor.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Noref { - #[doc = "0: Reference clock is provided"] - YesRef = 0, - #[doc = "1: No reference clock is provided"] - NoRef = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Noref) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NOREF` reader - Indicates whether the device provides a reference clock to the processor."] -pub type NorefR = crate::BitReader; -impl NorefR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Noref { - match self.bits { - false => Noref::YesRef, - true => Noref::NoRef, - } - } - #[doc = "Reference clock is provided"] - #[inline(always)] - pub fn is_yes_ref(&self) -> bool { - *self == Noref::YesRef - } - #[doc = "No reference clock is provided"] - #[inline(always)] - pub fn is_no_ref(&self) -> bool { - *self == Noref::NoRef - } -} -#[doc = "Field `NOREF` writer - Indicates whether the device provides a reference clock to the processor."] -pub type NorefW<'a, REG> = crate::BitWriter<'a, REG, Noref>; -impl<'a, REG> NorefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Reference clock is provided"] - #[inline(always)] - pub fn yes_ref(self) -> &'a mut crate::W { - self.variant(Noref::YesRef) - } - #[doc = "No reference clock is provided"] - #[inline(always)] - pub fn no_ref(self) -> &'a mut crate::W { - self.variant(Noref::NoRef) - } -} -impl R { - #[doc = "Bits 0:23 - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] - #[inline(always)] - pub fn tenms(&self) -> TenmsR { - TenmsR::new(self.bits & 0x00ff_ffff) - } - #[doc = "Bit 24 - Indicates whether the TENMS value is exact."] - #[inline(always)] - pub fn skew(&self) -> SkewR { - SkewR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Indicates whether the device provides a reference clock to the processor."] - #[inline(always)] - pub fn noref(&self) -> NorefR { - NorefR::new(((self.bits >> 25) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:23 - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."] - #[inline(always)] - pub fn tenms(&mut self) -> TenmsW { - TenmsW::new(self, 0) - } - #[doc = "Bit 24 - Indicates whether the TENMS value is exact."] - #[inline(always)] - pub fn skew(&mut self) -> SkewW { - SkewW::new(self, 24) - } - #[doc = "Bit 25 - Indicates whether the device provides a reference clock to the processor."] - #[inline(always)] - pub fn noref(&mut self) -> NorefW { - NorefW::new(self, 25) - } -} -#[doc = "Non-Secure CPU0 System Tick Calibration\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu0nstckcal::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu0nstckcal::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Cpu0nstckcalSpec; -impl crate::RegisterSpec for Cpu0nstckcalSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cpu0nstckcal::R`](R) reader structure"] -impl crate::Readable for Cpu0nstckcalSpec {} -#[doc = "`write(|w| ..)` method takes [`cpu0nstckcal::W`](W) writer structure"] -impl crate::Writable for Cpu0nstckcalSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CPU0NSTCKCAL to value 0"] -impl crate::Resettable for Cpu0nstckcalSpec {} diff --git a/mcxa276-pac/src/syscon/cpustat.rs b/mcxa276-pac/src/syscon/cpustat.rs deleted file mode 100644 index a7b03e62a..000000000 --- a/mcxa276-pac/src/syscon/cpustat.rs +++ /dev/null @@ -1,95 +0,0 @@ -#[doc = "Register `CPUSTAT` reader"] -pub type R = crate::R; -#[doc = "CPU0 sleeping state\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cpu0sleeping { - #[doc = "0: CPU is not sleeping"] - Awake = 0, - #[doc = "1: CPU is sleeping"] - Sleeping = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cpu0sleeping) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CPU0SLEEPING` reader - CPU0 sleeping state"] -pub type Cpu0sleepingR = crate::BitReader; -impl Cpu0sleepingR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpu0sleeping { - match self.bits { - false => Cpu0sleeping::Awake, - true => Cpu0sleeping::Sleeping, - } - } - #[doc = "CPU is not sleeping"] - #[inline(always)] - pub fn is_awake(&self) -> bool { - *self == Cpu0sleeping::Awake - } - #[doc = "CPU is sleeping"] - #[inline(always)] - pub fn is_sleeping(&self) -> bool { - *self == Cpu0sleeping::Sleeping - } -} -#[doc = "CPU0 lockup state\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cpu0lockup { - #[doc = "0: CPU is not in lockup"] - Awake = 0, - #[doc = "1: CPU is in lockup"] - Sleeping = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cpu0lockup) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CPU0LOCKUP` reader - CPU0 lockup state"] -pub type Cpu0lockupR = crate::BitReader; -impl Cpu0lockupR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cpu0lockup { - match self.bits { - false => Cpu0lockup::Awake, - true => Cpu0lockup::Sleeping, - } - } - #[doc = "CPU is not in lockup"] - #[inline(always)] - pub fn is_awake(&self) -> bool { - *self == Cpu0lockup::Awake - } - #[doc = "CPU is in lockup"] - #[inline(always)] - pub fn is_sleeping(&self) -> bool { - *self == Cpu0lockup::Sleeping - } -} -impl R { - #[doc = "Bit 0 - CPU0 sleeping state"] - #[inline(always)] - pub fn cpu0sleeping(&self) -> Cpu0sleepingR { - Cpu0sleepingR::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - CPU0 lockup state"] - #[inline(always)] - pub fn cpu0lockup(&self) -> Cpu0lockupR { - Cpu0lockupR::new(((self.bits >> 2) & 1) != 0) - } -} -#[doc = "CPU Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cpustat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CpustatSpec; -impl crate::RegisterSpec for CpustatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cpustat::R`](R) reader structure"] -impl crate::Readable for CpustatSpec {} -#[doc = "`reset()` method sets CPUSTAT to value 0"] -impl crate::Resettable for CpustatSpec {} diff --git a/mcxa276-pac/src/syscon/ctimerglobalstarten.rs b/mcxa276-pac/src/syscon/ctimerglobalstarten.rs deleted file mode 100644 index 604a8e1b3..000000000 --- a/mcxa276-pac/src/syscon/ctimerglobalstarten.rs +++ /dev/null @@ -1,336 +0,0 @@ -#[doc = "Register `CTIMERGLOBALSTARTEN` reader"] -pub type R = crate::R; -#[doc = "Register `CTIMERGLOBALSTARTEN` writer"] -pub type W = crate::W; -#[doc = "Enables the CTIMER0 function clock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer0ClkEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer0ClkEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER0_CLK_EN` reader - Enables the CTIMER0 function clock"] -pub type Ctimer0ClkEnR = crate::BitReader; -impl Ctimer0ClkEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer0ClkEn { - match self.bits { - false => Ctimer0ClkEn::Disable, - true => Ctimer0ClkEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ctimer0ClkEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ctimer0ClkEn::Enable - } -} -#[doc = "Field `CTIMER0_CLK_EN` writer - Enables the CTIMER0 function clock"] -pub type Ctimer0ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer0ClkEn>; -impl<'a, REG> Ctimer0ClkEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ctimer0ClkEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ctimer0ClkEn::Enable) - } -} -#[doc = "Enables the CTIMER1 function clock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer1ClkEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer1ClkEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER1_CLK_EN` reader - Enables the CTIMER1 function clock"] -pub type Ctimer1ClkEnR = crate::BitReader; -impl Ctimer1ClkEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer1ClkEn { - match self.bits { - false => Ctimer1ClkEn::Disable, - true => Ctimer1ClkEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ctimer1ClkEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ctimer1ClkEn::Enable - } -} -#[doc = "Field `CTIMER1_CLK_EN` writer - Enables the CTIMER1 function clock"] -pub type Ctimer1ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer1ClkEn>; -impl<'a, REG> Ctimer1ClkEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ctimer1ClkEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ctimer1ClkEn::Enable) - } -} -#[doc = "Enables the CTIMER2 function clock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer2ClkEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer2ClkEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER2_CLK_EN` reader - Enables the CTIMER2 function clock"] -pub type Ctimer2ClkEnR = crate::BitReader; -impl Ctimer2ClkEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer2ClkEn { - match self.bits { - false => Ctimer2ClkEn::Disable, - true => Ctimer2ClkEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ctimer2ClkEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ctimer2ClkEn::Enable - } -} -#[doc = "Field `CTIMER2_CLK_EN` writer - Enables the CTIMER2 function clock"] -pub type Ctimer2ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer2ClkEn>; -impl<'a, REG> Ctimer2ClkEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ctimer2ClkEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ctimer2ClkEn::Enable) - } -} -#[doc = "Enables the CTIMER3 function clock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer3ClkEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer3ClkEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER3_CLK_EN` reader - Enables the CTIMER3 function clock"] -pub type Ctimer3ClkEnR = crate::BitReader; -impl Ctimer3ClkEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer3ClkEn { - match self.bits { - false => Ctimer3ClkEn::Disable, - true => Ctimer3ClkEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ctimer3ClkEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ctimer3ClkEn::Enable - } -} -#[doc = "Field `CTIMER3_CLK_EN` writer - Enables the CTIMER3 function clock"] -pub type Ctimer3ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer3ClkEn>; -impl<'a, REG> Ctimer3ClkEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ctimer3ClkEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ctimer3ClkEn::Enable) - } -} -#[doc = "Enables the CTIMER4 function clock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ctimer4ClkEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ctimer4ClkEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CTIMER4_CLK_EN` reader - Enables the CTIMER4 function clock"] -pub type Ctimer4ClkEnR = crate::BitReader; -impl Ctimer4ClkEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ctimer4ClkEn { - match self.bits { - false => Ctimer4ClkEn::Disable, - true => Ctimer4ClkEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ctimer4ClkEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ctimer4ClkEn::Enable - } -} -#[doc = "Field `CTIMER4_CLK_EN` writer - Enables the CTIMER4 function clock"] -pub type Ctimer4ClkEnW<'a, REG> = crate::BitWriter<'a, REG, Ctimer4ClkEn>; -impl<'a, REG> Ctimer4ClkEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ctimer4ClkEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ctimer4ClkEn::Enable) - } -} -impl R { - #[doc = "Bit 0 - Enables the CTIMER0 function clock"] - #[inline(always)] - pub fn ctimer0_clk_en(&self) -> Ctimer0ClkEnR { - Ctimer0ClkEnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Enables the CTIMER1 function clock"] - #[inline(always)] - pub fn ctimer1_clk_en(&self) -> Ctimer1ClkEnR { - Ctimer1ClkEnR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Enables the CTIMER2 function clock"] - #[inline(always)] - pub fn ctimer2_clk_en(&self) -> Ctimer2ClkEnR { - Ctimer2ClkEnR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Enables the CTIMER3 function clock"] - #[inline(always)] - pub fn ctimer3_clk_en(&self) -> Ctimer3ClkEnR { - Ctimer3ClkEnR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Enables the CTIMER4 function clock"] - #[inline(always)] - pub fn ctimer4_clk_en(&self) -> Ctimer4ClkEnR { - Ctimer4ClkEnR::new(((self.bits >> 4) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enables the CTIMER0 function clock"] - #[inline(always)] - pub fn ctimer0_clk_en(&mut self) -> Ctimer0ClkEnW { - Ctimer0ClkEnW::new(self, 0) - } - #[doc = "Bit 1 - Enables the CTIMER1 function clock"] - #[inline(always)] - pub fn ctimer1_clk_en(&mut self) -> Ctimer1ClkEnW { - Ctimer1ClkEnW::new(self, 1) - } - #[doc = "Bit 2 - Enables the CTIMER2 function clock"] - #[inline(always)] - pub fn ctimer2_clk_en(&mut self) -> Ctimer2ClkEnW { - Ctimer2ClkEnW::new(self, 2) - } - #[doc = "Bit 3 - Enables the CTIMER3 function clock"] - #[inline(always)] - pub fn ctimer3_clk_en(&mut self) -> Ctimer3ClkEnW { - Ctimer3ClkEnW::new(self, 3) - } - #[doc = "Bit 4 - Enables the CTIMER4 function clock"] - #[inline(always)] - pub fn ctimer4_clk_en(&mut self) -> Ctimer4ClkEnW { - Ctimer4ClkEnW::new(self, 4) - } -} -#[doc = "CTIMER Global Start Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimerglobalstarten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimerglobalstarten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtimerglobalstartenSpec; -impl crate::RegisterSpec for CtimerglobalstartenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctimerglobalstarten::R`](R) reader structure"] -impl crate::Readable for CtimerglobalstartenSpec {} -#[doc = "`write(|w| ..)` method takes [`ctimerglobalstarten::W`](W) writer structure"] -impl crate::Writable for CtimerglobalstartenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTIMERGLOBALSTARTEN to value 0"] -impl crate::Resettable for CtimerglobalstartenSpec {} diff --git a/mcxa276-pac/src/syscon/debug_auth_beacon.rs b/mcxa276-pac/src/syscon/debug_auth_beacon.rs deleted file mode 100644 index 2194e93eb..000000000 --- a/mcxa276-pac/src/syscon/debug_auth_beacon.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `DEBUG_AUTH_BEACON` reader"] -pub type R = crate::R; -#[doc = "Register `DEBUG_AUTH_BEACON` writer"] -pub type W = crate::W; -#[doc = "Field `BEACON` reader - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] -pub type BeaconR = crate::FieldReader; -#[doc = "Field `BEACON` writer - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] -pub type BeaconW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] - #[inline(always)] - pub fn beacon(&self) -> BeaconR { - BeaconR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code."] - #[inline(always)] - pub fn beacon(&mut self) -> BeaconW { - BeaconW::new(self, 0) - } -} -#[doc = "Debug Authentication BEACON\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_auth_beacon::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_auth_beacon::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DebugAuthBeaconSpec; -impl crate::RegisterSpec for DebugAuthBeaconSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`debug_auth_beacon::R`](R) reader structure"] -impl crate::Readable for DebugAuthBeaconSpec {} -#[doc = "`write(|w| ..)` method takes [`debug_auth_beacon::W`](W) writer structure"] -impl crate::Writable for DebugAuthBeaconSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DEBUG_AUTH_BEACON to value 0"] -impl crate::Resettable for DebugAuthBeaconSpec {} diff --git a/mcxa276-pac/src/syscon/debug_features.rs b/mcxa276-pac/src/syscon/debug_features.rs deleted file mode 100644 index e3cf873fb..000000000 --- a/mcxa276-pac/src/syscon/debug_features.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `DEBUG_FEATURES` reader"] -pub type R = crate::R; -#[doc = "Register `DEBUG_FEATURES` writer"] -pub type W = crate::W; -#[doc = "CPU0 invasive debug control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu0Dbgen { - #[doc = "1: Disables debug"] - Disable = 1, - #[doc = "2: Enables debug"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu0Dbgen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu0Dbgen { - type Ux = u8; -} -impl crate::IsEnum for Cpu0Dbgen {} -#[doc = "Field `CPU0_DBGEN` reader - CPU0 invasive debug control"] -pub type Cpu0DbgenR = crate::FieldReader; -impl Cpu0DbgenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Cpu0Dbgen::Disable), - 2 => Some(Cpu0Dbgen::Enable), - _ => None, - } - } - #[doc = "Disables debug"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Cpu0Dbgen::Disable - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Cpu0Dbgen::Enable - } -} -#[doc = "Field `CPU0_DBGEN` writer - CPU0 invasive debug control"] -pub type Cpu0DbgenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Dbgen>; -impl<'a, REG> Cpu0DbgenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disables debug"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Cpu0Dbgen::Disable) - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Cpu0Dbgen::Enable) - } -} -#[doc = "CPU0 non-invasive debug control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu0Niden { - #[doc = "1: Disables debug"] - Disable = 1, - #[doc = "2: Enables debug"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu0Niden) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu0Niden { - type Ux = u8; -} -impl crate::IsEnum for Cpu0Niden {} -#[doc = "Field `CPU0_NIDEN` reader - CPU0 non-invasive debug control"] -pub type Cpu0NidenR = crate::FieldReader; -impl Cpu0NidenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Cpu0Niden::Disable), - 2 => Some(Cpu0Niden::Enable), - _ => None, - } - } - #[doc = "Disables debug"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Cpu0Niden::Disable - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Cpu0Niden::Enable - } -} -#[doc = "Field `CPU0_NIDEN` writer - CPU0 non-invasive debug control"] -pub type Cpu0NidenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Niden>; -impl<'a, REG> Cpu0NidenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disables debug"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Cpu0Niden::Disable) - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Cpu0Niden::Enable) - } -} -impl R { - #[doc = "Bits 0:1 - CPU0 invasive debug control"] - #[inline(always)] - pub fn cpu0_dbgen(&self) -> Cpu0DbgenR { - Cpu0DbgenR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] - #[inline(always)] - pub fn cpu0_niden(&self) -> Cpu0NidenR { - Cpu0NidenR::new(((self.bits >> 2) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - CPU0 invasive debug control"] - #[inline(always)] - pub fn cpu0_dbgen(&mut self) -> Cpu0DbgenW { - Cpu0DbgenW::new(self, 0) - } - #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] - #[inline(always)] - pub fn cpu0_niden(&mut self) -> Cpu0NidenW { - Cpu0NidenW::new(self, 2) - } -} -#[doc = "Cortex Debug Features Control\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DebugFeaturesSpec; -impl crate::RegisterSpec for DebugFeaturesSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`debug_features::R`](R) reader structure"] -impl crate::Readable for DebugFeaturesSpec {} -#[doc = "`write(|w| ..)` method takes [`debug_features::W`](W) writer structure"] -impl crate::Writable for DebugFeaturesSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DEBUG_FEATURES to value 0"] -impl crate::Resettable for DebugFeaturesSpec {} diff --git a/mcxa276-pac/src/syscon/debug_features_dp.rs b/mcxa276-pac/src/syscon/debug_features_dp.rs deleted file mode 100644 index c5d830887..000000000 --- a/mcxa276-pac/src/syscon/debug_features_dp.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `DEBUG_FEATURES_DP` reader"] -pub type R = crate::R; -#[doc = "Register `DEBUG_FEATURES_DP` writer"] -pub type W = crate::W; -#[doc = "CPU0 invasive debug control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu0Dbgen { - #[doc = "1: Disables debug"] - Disable = 1, - #[doc = "2: Enables debug"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu0Dbgen) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu0Dbgen { - type Ux = u8; -} -impl crate::IsEnum for Cpu0Dbgen {} -#[doc = "Field `CPU0_DBGEN` reader - CPU0 invasive debug control"] -pub type Cpu0DbgenR = crate::FieldReader; -impl Cpu0DbgenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Cpu0Dbgen::Disable), - 2 => Some(Cpu0Dbgen::Enable), - _ => None, - } - } - #[doc = "Disables debug"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Cpu0Dbgen::Disable - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Cpu0Dbgen::Enable - } -} -#[doc = "Field `CPU0_DBGEN` writer - CPU0 invasive debug control"] -pub type Cpu0DbgenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Dbgen>; -impl<'a, REG> Cpu0DbgenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disables debug"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Cpu0Dbgen::Disable) - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Cpu0Dbgen::Enable) - } -} -#[doc = "CPU0 non-invasive debug control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu0Niden { - #[doc = "1: Disables debug"] - Disable = 1, - #[doc = "2: Enables debug"] - Enable = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu0Niden) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu0Niden { - type Ux = u8; -} -impl crate::IsEnum for Cpu0Niden {} -#[doc = "Field `CPU0_NIDEN` reader - CPU0 non-invasive debug control"] -pub type Cpu0NidenR = crate::FieldReader; -impl Cpu0NidenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Cpu0Niden::Disable), - 2 => Some(Cpu0Niden::Enable), - _ => None, - } - } - #[doc = "Disables debug"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Cpu0Niden::Disable - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Cpu0Niden::Enable - } -} -#[doc = "Field `CPU0_NIDEN` writer - CPU0 non-invasive debug control"] -pub type Cpu0NidenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Niden>; -impl<'a, REG> Cpu0NidenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disables debug"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Cpu0Niden::Disable) - } - #[doc = "Enables debug"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Cpu0Niden::Enable) - } -} -impl R { - #[doc = "Bits 0:1 - CPU0 invasive debug control"] - #[inline(always)] - pub fn cpu0_dbgen(&self) -> Cpu0DbgenR { - Cpu0DbgenR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] - #[inline(always)] - pub fn cpu0_niden(&self) -> Cpu0NidenR { - Cpu0NidenR::new(((self.bits >> 2) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - CPU0 invasive debug control"] - #[inline(always)] - pub fn cpu0_dbgen(&mut self) -> Cpu0DbgenW { - Cpu0DbgenW::new(self, 0) - } - #[doc = "Bits 2:3 - CPU0 non-invasive debug control"] - #[inline(always)] - pub fn cpu0_niden(&mut self) -> Cpu0NidenW { - Cpu0NidenW::new(self, 2) - } -} -#[doc = "Cortex Debug Features Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features_dp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features_dp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DebugFeaturesDpSpec; -impl crate::RegisterSpec for DebugFeaturesDpSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`debug_features_dp::R`](R) reader structure"] -impl crate::Readable for DebugFeaturesDpSpec {} -#[doc = "`write(|w| ..)` method takes [`debug_features_dp::W`](W) writer structure"] -impl crate::Writable for DebugFeaturesDpSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DEBUG_FEATURES_DP to value 0"] -impl crate::Resettable for DebugFeaturesDpSpec {} diff --git a/mcxa276-pac/src/syscon/debug_lock_en.rs b/mcxa276-pac/src/syscon/debug_lock_en.rs deleted file mode 100644 index 4c2160cac..000000000 --- a/mcxa276-pac/src/syscon/debug_lock_en.rs +++ /dev/null @@ -1,93 +0,0 @@ -#[doc = "Register `DEBUG_LOCK_EN` reader"] -pub type R = crate::R; -#[doc = "Register `DEBUG_LOCK_EN` writer"] -pub type W = crate::W; -#[doc = "Controls write access to the security registers\n\nValue on reset: 10"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum LockAll { - #[doc = "0: Any other value than b1010: disables write access to all registers"] - Disable = 0, - #[doc = "10: Enables write access to all registers"] - Enable = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: LockAll) -> Self { - variant as _ - } -} -impl crate::FieldSpec for LockAll { - type Ux = u8; -} -impl crate::IsEnum for LockAll {} -#[doc = "Field `LOCK_ALL` reader - Controls write access to the security registers"] -pub type LockAllR = crate::FieldReader; -impl LockAllR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(LockAll::Disable), - 10 => Some(LockAll::Enable), - _ => None, - } - } - #[doc = "Any other value than b1010: disables write access to all registers"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == LockAll::Disable - } - #[doc = "Enables write access to all registers"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == LockAll::Enable - } -} -#[doc = "Field `LOCK_ALL` writer - Controls write access to the security registers"] -pub type LockAllW<'a, REG> = crate::FieldWriter<'a, REG, 4, LockAll>; -impl<'a, REG> LockAllW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Any other value than b1010: disables write access to all registers"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(LockAll::Disable) - } - #[doc = "Enables write access to all registers"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(LockAll::Enable) - } -} -impl R { - #[doc = "Bits 0:3 - Controls write access to the security registers"] - #[inline(always)] - pub fn lock_all(&self) -> LockAllR { - LockAllR::new((self.bits & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:3 - Controls write access to the security registers"] - #[inline(always)] - pub fn lock_all(&mut self) -> LockAllW { - LockAllW::new(self, 0) - } -} -#[doc = "Control Write Access to Security\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_lock_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_lock_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DebugLockEnSpec; -impl crate::RegisterSpec for DebugLockEnSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`debug_lock_en::R`](R) reader structure"] -impl crate::Readable for DebugLockEnSpec {} -#[doc = "`write(|w| ..)` method takes [`debug_lock_en::W`](W) writer structure"] -impl crate::Writable for DebugLockEnSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DEBUG_LOCK_EN to value 0x0a"] -impl crate::Resettable for DebugLockEnSpec { - const RESET_VALUE: u32 = 0x0a; -} diff --git a/mcxa276-pac/src/syscon/device_id0.rs b/mcxa276-pac/src/syscon/device_id0.rs deleted file mode 100644 index 5206a8cae..000000000 --- a/mcxa276-pac/src/syscon/device_id0.rs +++ /dev/null @@ -1,297 +0,0 @@ -#[doc = "Register `DEVICE_ID0` reader"] -pub type R = crate::R; -#[doc = "Indicates the device's ram size\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum RamSize { - #[doc = "0: 8KB."] - Size8kb = 0, - #[doc = "1: 16KB."] - Size16kb = 1, - #[doc = "2: 32KB."] - Size32kb = 2, - #[doc = "3: 64KB."] - Size64kb = 3, - #[doc = "4: 96KB."] - Size96kb = 4, - #[doc = "5: 128KB."] - Size128kb = 5, - #[doc = "6: 160KB."] - Size160kb = 6, - #[doc = "7: 192KB."] - Size192kb = 7, - #[doc = "8: 256KB."] - Size256kb = 8, - #[doc = "9: 288KB."] - Size288kb = 9, - #[doc = "10: 352KB."] - Size352kb = 10, - #[doc = "11: 512KB."] - Size512kb = 11, -} -impl From for u8 { - #[inline(always)] - fn from(variant: RamSize) -> Self { - variant as _ - } -} -impl crate::FieldSpec for RamSize { - type Ux = u8; -} -impl crate::IsEnum for RamSize {} -#[doc = "Field `RAM_SIZE` reader - Indicates the device's ram size"] -pub type RamSizeR = crate::FieldReader; -impl RamSizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(RamSize::Size8kb), - 1 => Some(RamSize::Size16kb), - 2 => Some(RamSize::Size32kb), - 3 => Some(RamSize::Size64kb), - 4 => Some(RamSize::Size96kb), - 5 => Some(RamSize::Size128kb), - 6 => Some(RamSize::Size160kb), - 7 => Some(RamSize::Size192kb), - 8 => Some(RamSize::Size256kb), - 9 => Some(RamSize::Size288kb), - 10 => Some(RamSize::Size352kb), - 11 => Some(RamSize::Size512kb), - _ => None, - } - } - #[doc = "8KB."] - #[inline(always)] - pub fn is_size_8kb(&self) -> bool { - *self == RamSize::Size8kb - } - #[doc = "16KB."] - #[inline(always)] - pub fn is_size_16kb(&self) -> bool { - *self == RamSize::Size16kb - } - #[doc = "32KB."] - #[inline(always)] - pub fn is_size_32kb(&self) -> bool { - *self == RamSize::Size32kb - } - #[doc = "64KB."] - #[inline(always)] - pub fn is_size_64kb(&self) -> bool { - *self == RamSize::Size64kb - } - #[doc = "96KB."] - #[inline(always)] - pub fn is_size_96kb(&self) -> bool { - *self == RamSize::Size96kb - } - #[doc = "128KB."] - #[inline(always)] - pub fn is_size_128kb(&self) -> bool { - *self == RamSize::Size128kb - } - #[doc = "160KB."] - #[inline(always)] - pub fn is_size_160kb(&self) -> bool { - *self == RamSize::Size160kb - } - #[doc = "192KB."] - #[inline(always)] - pub fn is_size_192kb(&self) -> bool { - *self == RamSize::Size192kb - } - #[doc = "256KB."] - #[inline(always)] - pub fn is_size_256kb(&self) -> bool { - *self == RamSize::Size256kb - } - #[doc = "288KB."] - #[inline(always)] - pub fn is_size_288kb(&self) -> bool { - *self == RamSize::Size288kb - } - #[doc = "352KB."] - #[inline(always)] - pub fn is_size_352kb(&self) -> bool { - *self == RamSize::Size352kb - } - #[doc = "512KB."] - #[inline(always)] - pub fn is_size_512kb(&self) -> bool { - *self == RamSize::Size512kb - } -} -#[doc = "Indicates the device's flash size\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum FlashSize { - #[doc = "0: 32KB."] - Size32kb = 0, - #[doc = "1: 64KB."] - Size64kb = 1, - #[doc = "2: 128KB."] - Size128kb = 2, - #[doc = "3: 256KB."] - Size256kb = 3, - #[doc = "4: 512KB."] - Size512kb = 4, - #[doc = "5: 768KB."] - Size768kb = 5, - #[doc = "6: 1MB."] - Size1mb = 6, - #[doc = "7: 1.5MB."] - Size1p5mb = 7, - #[doc = "8: 2MB."] - Size2mb = 8, -} -impl From for u8 { - #[inline(always)] - fn from(variant: FlashSize) -> Self { - variant as _ - } -} -impl crate::FieldSpec for FlashSize { - type Ux = u8; -} -impl crate::IsEnum for FlashSize {} -#[doc = "Field `FLASH_SIZE` reader - Indicates the device's flash size"] -pub type FlashSizeR = crate::FieldReader; -impl FlashSizeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(FlashSize::Size32kb), - 1 => Some(FlashSize::Size64kb), - 2 => Some(FlashSize::Size128kb), - 3 => Some(FlashSize::Size256kb), - 4 => Some(FlashSize::Size512kb), - 5 => Some(FlashSize::Size768kb), - 6 => Some(FlashSize::Size1mb), - 7 => Some(FlashSize::Size1p5mb), - 8 => Some(FlashSize::Size2mb), - _ => None, - } - } - #[doc = "32KB."] - #[inline(always)] - pub fn is_size_32kb(&self) -> bool { - *self == FlashSize::Size32kb - } - #[doc = "64KB."] - #[inline(always)] - pub fn is_size_64kb(&self) -> bool { - *self == FlashSize::Size64kb - } - #[doc = "128KB."] - #[inline(always)] - pub fn is_size_128kb(&self) -> bool { - *self == FlashSize::Size128kb - } - #[doc = "256KB."] - #[inline(always)] - pub fn is_size_256kb(&self) -> bool { - *self == FlashSize::Size256kb - } - #[doc = "512KB."] - #[inline(always)] - pub fn is_size_512kb(&self) -> bool { - *self == FlashSize::Size512kb - } - #[doc = "768KB."] - #[inline(always)] - pub fn is_size_768kb(&self) -> bool { - *self == FlashSize::Size768kb - } - #[doc = "1MB."] - #[inline(always)] - pub fn is_size_1mb(&self) -> bool { - *self == FlashSize::Size1mb - } - #[doc = "1.5MB."] - #[inline(always)] - pub fn is_size_1p5mb(&self) -> bool { - *self == FlashSize::Size1p5mb - } - #[doc = "2MB."] - #[inline(always)] - pub fn is_size_2mb(&self) -> bool { - *self == FlashSize::Size2mb - } -} -#[doc = "Field `ROM_REV_MINOR` reader - Indicates the device's ROM revision"] -pub type RomRevMinorR = crate::FieldReader; -#[doc = "no description available\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Security { - #[doc = "5: Secure version."] - NonSec = 5, - #[doc = "10: Non secure version."] - Security10 = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Security) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Security { - type Ux = u8; -} -impl crate::IsEnum for Security {} -#[doc = "Field `SECURITY` reader - no description available"] -pub type SecurityR = crate::FieldReader; -impl SecurityR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 5 => Some(Security::NonSec), - 10 => Some(Security::Security10), - _ => None, - } - } - #[doc = "Secure version."] - #[inline(always)] - pub fn is_non_sec(&self) -> bool { - *self == Security::NonSec - } - #[doc = "Non secure version."] - #[inline(always)] - pub fn is_security_10(&self) -> bool { - *self == Security::Security10 - } -} -impl R { - #[doc = "Bits 0:3 - Indicates the device's ram size"] - #[inline(always)] - pub fn ram_size(&self) -> RamSizeR { - RamSizeR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - Indicates the device's flash size"] - #[inline(always)] - pub fn flash_size(&self) -> FlashSizeR { - FlashSizeR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 20:23 - Indicates the device's ROM revision"] - #[inline(always)] - pub fn rom_rev_minor(&self) -> RomRevMinorR { - RomRevMinorR::new(((self.bits >> 20) & 0x0f) as u8) - } - #[doc = "Bits 24:27 - no description available"] - #[inline(always)] - pub fn security(&self) -> SecurityR { - SecurityR::new(((self.bits >> 24) & 0x0f) as u8) - } -} -#[doc = "Device ID\n\nYou can [`read`](crate::Reg::read) this register and get [`device_id0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DeviceId0Spec; -impl crate::RegisterSpec for DeviceId0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`device_id0::R`](R) reader structure"] -impl crate::Readable for DeviceId0Spec {} -#[doc = "`reset()` method sets DEVICE_ID0 to value 0"] -impl crate::Resettable for DeviceId0Spec {} diff --git a/mcxa276-pac/src/syscon/device_type.rs b/mcxa276-pac/src/syscon/device_type.rs deleted file mode 100644 index 45620eb0a..000000000 --- a/mcxa276-pac/src/syscon/device_type.rs +++ /dev/null @@ -1,157 +0,0 @@ -#[doc = "Register `DEVICE_TYPE` reader"] -pub type R = crate::R; -#[doc = "Field `DEVICE_TYPE_NUM` reader - Indicates the device part number"] -pub type DeviceTypeNumR = crate::FieldReader; -#[doc = "Indicates the device type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DeviceTypeSec { - #[doc = "0: Non Secure"] - NonSec = 0, - #[doc = "1: Secure"] - Sec = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DeviceTypeSec) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DEVICE_TYPE_SEC` reader - Indicates the device type"] -pub type DeviceTypeSecR = crate::BitReader; -impl DeviceTypeSecR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DeviceTypeSec { - match self.bits { - false => DeviceTypeSec::NonSec, - true => DeviceTypeSec::Sec, - } - } - #[doc = "Non Secure"] - #[inline(always)] - pub fn is_non_sec(&self) -> bool { - *self == DeviceTypeSec::NonSec - } - #[doc = "Secure"] - #[inline(always)] - pub fn is_sec(&self) -> bool { - *self == DeviceTypeSec::Sec - } -} -#[doc = "Indicates the device's package type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum DeviceTypePkg { - #[doc = "0: HLQFP"] - Hlqfp = 0, - #[doc = "1: HTQFP"] - Htqfp = 1, - #[doc = "2: BGA"] - Bga = 2, - #[doc = "3: HDQFP"] - Hdqfp = 3, - #[doc = "4: QFN"] - Qfn = 4, - #[doc = "5: CSP"] - Csp = 5, - #[doc = "6: LQFP"] - Lqfp = 6, -} -impl From for u8 { - #[inline(always)] - fn from(variant: DeviceTypePkg) -> Self { - variant as _ - } -} -impl crate::FieldSpec for DeviceTypePkg { - type Ux = u8; -} -impl crate::IsEnum for DeviceTypePkg {} -#[doc = "Field `DEVICE_TYPE_PKG` reader - Indicates the device's package type"] -pub type DeviceTypePkgR = crate::FieldReader; -impl DeviceTypePkgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(DeviceTypePkg::Hlqfp), - 1 => Some(DeviceTypePkg::Htqfp), - 2 => Some(DeviceTypePkg::Bga), - 3 => Some(DeviceTypePkg::Hdqfp), - 4 => Some(DeviceTypePkg::Qfn), - 5 => Some(DeviceTypePkg::Csp), - 6 => Some(DeviceTypePkg::Lqfp), - _ => None, - } - } - #[doc = "HLQFP"] - #[inline(always)] - pub fn is_hlqfp(&self) -> bool { - *self == DeviceTypePkg::Hlqfp - } - #[doc = "HTQFP"] - #[inline(always)] - pub fn is_htqfp(&self) -> bool { - *self == DeviceTypePkg::Htqfp - } - #[doc = "BGA"] - #[inline(always)] - pub fn is_bga(&self) -> bool { - *self == DeviceTypePkg::Bga - } - #[doc = "HDQFP"] - #[inline(always)] - pub fn is_hdqfp(&self) -> bool { - *self == DeviceTypePkg::Hdqfp - } - #[doc = "QFN"] - #[inline(always)] - pub fn is_qfn(&self) -> bool { - *self == DeviceTypePkg::Qfn - } - #[doc = "CSP"] - #[inline(always)] - pub fn is_csp(&self) -> bool { - *self == DeviceTypePkg::Csp - } - #[doc = "LQFP"] - #[inline(always)] - pub fn is_lqfp(&self) -> bool { - *self == DeviceTypePkg::Lqfp - } -} -#[doc = "Field `DEVICE_TYPE_PIN` reader - Indicates the device's pin number"] -pub type DeviceTypePinR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Indicates the device part number"] - #[inline(always)] - pub fn device_type_num(&self) -> DeviceTypeNumR { - DeviceTypeNumR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bit 16 - Indicates the device type"] - #[inline(always)] - pub fn device_type_sec(&self) -> DeviceTypeSecR { - DeviceTypeSecR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bits 20:23 - Indicates the device's package type"] - #[inline(always)] - pub fn device_type_pkg(&self) -> DeviceTypePkgR { - DeviceTypePkgR::new(((self.bits >> 20) & 0x0f) as u8) - } - #[doc = "Bits 24:31 - Indicates the device's pin number"] - #[inline(always)] - pub fn device_type_pin(&self) -> DeviceTypePinR { - DeviceTypePinR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Device Type\n\nYou can [`read`](crate::Reg::read) this register and get [`device_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DeviceTypeSpec; -impl crate::RegisterSpec for DeviceTypeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`device_type::R`](R) reader structure"] -impl crate::Readable for DeviceTypeSpec {} -#[doc = "`reset()` method sets DEVICE_TYPE to value 0x2000"] -impl crate::Resettable for DeviceTypeSpec { - const RESET_VALUE: u32 = 0x2000; -} diff --git a/mcxa276-pac/src/syscon/dieid.rs b/mcxa276-pac/src/syscon/dieid.rs deleted file mode 100644 index a0121ae97..000000000 --- a/mcxa276-pac/src/syscon/dieid.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `DIEID` reader"] -pub type R = crate::R; -#[doc = "Field `MINOR_REVISION` reader - Chip minor revision"] -pub type MinorRevisionR = crate::FieldReader; -#[doc = "Field `MAJOR_REVISION` reader - Chip major revision"] -pub type MajorRevisionR = crate::FieldReader; -#[doc = "Field `MCO_NUM_IN_DIE_ID` reader - Chip number"] -pub type McoNumInDieIdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:3 - Chip minor revision"] - #[inline(always)] - pub fn minor_revision(&self) -> MinorRevisionR { - MinorRevisionR::new((self.bits & 0x0f) as u8) - } - #[doc = "Bits 4:7 - Chip major revision"] - #[inline(always)] - pub fn major_revision(&self) -> MajorRevisionR { - MajorRevisionR::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:27 - Chip number"] - #[inline(always)] - pub fn mco_num_in_die_id(&self) -> McoNumInDieIdR { - McoNumInDieIdR::new((self.bits >> 8) & 0x000f_ffff) - } -} -#[doc = "Chip Revision ID and Number\n\nYou can [`read`](crate::Reg::read) this register and get [`dieid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DieidSpec; -impl crate::RegisterSpec for DieidSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`dieid::R`](R) reader structure"] -impl crate::Readable for DieidSpec {} -#[doc = "`reset()` method sets DIEID to value 0x005d_c1a0"] -impl crate::Resettable for DieidSpec { - const RESET_VALUE: u32 = 0x005d_c1a0; -} diff --git a/mcxa276-pac/src/syscon/els_otp_lc_state.rs b/mcxa276-pac/src/syscon/els_otp_lc_state.rs deleted file mode 100644 index 35dd0361b..000000000 --- a/mcxa276-pac/src/syscon/els_otp_lc_state.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `ELS_OTP_LC_STATE` reader"] -pub type R = crate::R; -#[doc = "Field `OTP_LC_STATE` reader - OTP life cycle state"] -pub type OtpLcStateR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - OTP life cycle state"] - #[inline(always)] - pub fn otp_lc_state(&self) -> OtpLcStateR { - OtpLcStateR::new((self.bits & 0xff) as u8) - } -} -#[doc = "Life Cycle State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElsOtpLcStateSpec; -impl crate::RegisterSpec for ElsOtpLcStateSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`els_otp_lc_state::R`](R) reader structure"] -impl crate::Readable for ElsOtpLcStateSpec {} -#[doc = "`reset()` method sets ELS_OTP_LC_STATE to value 0"] -impl crate::Resettable for ElsOtpLcStateSpec {} diff --git a/mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs b/mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs deleted file mode 100644 index 52d3b4323..000000000 --- a/mcxa276-pac/src/syscon/els_otp_lc_state_dp.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `ELS_OTP_LC_STATE_DP` reader"] -pub type R = crate::R; -#[doc = "Field `OTP_LC_STATE_DP` reader - OTP life cycle state"] -pub type OtpLcStateDpR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - OTP life cycle state"] - #[inline(always)] - pub fn otp_lc_state_dp(&self) -> OtpLcStateDpR { - OtpLcStateDpR::new((self.bits & 0xff) as u8) - } -} -#[doc = "Life Cycle State Register (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state_dp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElsOtpLcStateDpSpec; -impl crate::RegisterSpec for ElsOtpLcStateDpSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`els_otp_lc_state_dp::R`](R) reader structure"] -impl crate::Readable for ElsOtpLcStateDpSpec {} -#[doc = "`reset()` method sets ELS_OTP_LC_STATE_DP to value 0"] -impl crate::Resettable for ElsOtpLcStateDpSpec {} diff --git a/mcxa276-pac/src/syscon/els_udf.rs b/mcxa276-pac/src/syscon/els_udf.rs deleted file mode 100644 index 1f60f7f0b..000000000 --- a/mcxa276-pac/src/syscon/els_udf.rs +++ /dev/null @@ -1,231 +0,0 @@ -#[doc = "Register `ELS_UDF` reader"] -pub type R = crate::R; -#[doc = "Register `ELS_UDF` writer"] -pub type W = crate::W; -#[doc = "UDF KEY Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum KeySel { - #[doc = "0: DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] - Duk0 = 0, - #[doc = "1: DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] - Duk1 = 1, - #[doc = "2: DeviceHSM"] - DeviceHsm = 2, - #[doc = "3: NXP_mRoT"] - NxpMRoT = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: KeySel) -> Self { - variant as _ - } -} -impl crate::FieldSpec for KeySel { - type Ux = u8; -} -impl crate::IsEnum for KeySel {} -#[doc = "Field `KEY_SEL` reader - UDF KEY Select"] -pub type KeySelR = crate::FieldReader; -impl KeySelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> KeySel { - match self.bits { - 0 => KeySel::Duk0, - 1 => KeySel::Duk1, - 2 => KeySel::DeviceHsm, - 3 => KeySel::NxpMRoT, - _ => unreachable!(), - } - } - #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] - #[inline(always)] - pub fn is_duk_0(&self) -> bool { - *self == KeySel::Duk0 - } - #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] - #[inline(always)] - pub fn is_duk_1(&self) -> bool { - *self == KeySel::Duk1 - } - #[doc = "DeviceHSM"] - #[inline(always)] - pub fn is_device_hsm(&self) -> bool { - *self == KeySel::DeviceHsm - } - #[doc = "NXP_mRoT"] - #[inline(always)] - pub fn is_nxp_m_ro_t(&self) -> bool { - *self == KeySel::NxpMRoT - } -} -#[doc = "Field `KEY_SEL` writer - UDF KEY Select"] -pub type KeySelW<'a, REG> = crate::FieldWriter<'a, REG, 2, KeySel, crate::Safe>; -impl<'a, REG> KeySelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] - #[inline(always)] - pub fn duk_0(self) -> &'a mut crate::W { - self.variant(KeySel::Duk0) - } - #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]"] - #[inline(always)] - pub fn duk_1(self) -> &'a mut crate::W { - self.variant(KeySel::Duk1) - } - #[doc = "DeviceHSM"] - #[inline(always)] - pub fn device_hsm(self) -> &'a mut crate::W { - self.variant(KeySel::DeviceHsm) - } - #[doc = "NXP_mRoT"] - #[inline(always)] - pub fn nxp_m_ro_t(self) -> &'a mut crate::W { - self.variant(KeySel::NxpMRoT) - } -} -#[doc = "UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum UidHidden { - #[doc = "10: Enable the access of UID\\[127:0\\] register. All other value, disable the read/write of UID\\[127:0\\] register."] - UidHidden = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: UidHidden) -> Self { - variant as _ - } -} -impl crate::FieldSpec for UidHidden { - type Ux = u8; -} -impl crate::IsEnum for UidHidden {} -#[doc = "Field `UID_HIDDEN` reader - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] -pub type UidHiddenR = crate::FieldReader; -impl UidHiddenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 10 => Some(UidHidden::UidHidden), - _ => None, - } - } - #[doc = "Enable the access of UID\\[127:0\\] register. All other value, disable the read/write of UID\\[127:0\\] register."] - #[inline(always)] - pub fn is_uid_hidden(&self) -> bool { - *self == UidHidden::UidHidden - } -} -#[doc = "Field `UID_HIDDEN` writer - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] -pub type UidHiddenW<'a, REG> = crate::FieldWriter<'a, REG, 4, UidHidden>; -impl<'a, REG> UidHiddenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Enable the access of UID\\[127:0\\] register. All other value, disable the read/write of UID\\[127:0\\] register."] - #[inline(always)] - pub fn uid_hidden(self) -> &'a mut crate::W { - self.variant(UidHidden::UidHidden) - } -} -#[doc = "UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum UdfHidden { - #[doc = "10: Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus."] - UdfHidden = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: UdfHidden) -> Self { - variant as _ - } -} -impl crate::FieldSpec for UdfHidden { - type Ux = u8; -} -impl crate::IsEnum for UdfHidden {} -#[doc = "Field `UDF_HIDDEN` reader - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] -pub type UdfHiddenR = crate::FieldReader; -impl UdfHiddenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 10 => Some(UdfHidden::UdfHidden), - _ => None, - } - } - #[doc = "Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus."] - #[inline(always)] - pub fn is_udf_hidden(&self) -> bool { - *self == UdfHidden::UdfHidden - } -} -#[doc = "Field `UDF_HIDDEN` writer - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] -pub type UdfHiddenW<'a, REG> = crate::FieldWriter<'a, REG, 4, UdfHidden>; -impl<'a, REG> UdfHiddenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus."] - #[inline(always)] - pub fn udf_hidden(self) -> &'a mut crate::W { - self.variant(UdfHidden::UdfHidden) - } -} -impl R { - #[doc = "Bits 0:1 - UDF KEY Select"] - #[inline(always)] - pub fn key_sel(&self) -> KeySelR { - KeySelR::new((self.bits & 3) as u8) - } - #[doc = "Bits 24:27 - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] - #[inline(always)] - pub fn uid_hidden(&self) -> UidHiddenR { - UidHiddenR::new(((self.bits >> 24) & 0x0f) as u8) - } - #[doc = "Bits 28:31 - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] - #[inline(always)] - pub fn udf_hidden(&self) -> UdfHiddenR { - UdfHiddenR::new(((self.bits >> 28) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - UDF KEY Select"] - #[inline(always)] - pub fn key_sel(&mut self) -> KeySelW { - KeySelW::new(self, 0) - } - #[doc = "Bits 24:27 - UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] - #[inline(always)] - pub fn uid_hidden(&mut self) -> UidHiddenW { - UidHiddenW::new(self, 24) - } - #[doc = "Bits 28:31 - UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] - #[inline(always)] - pub fn udf_hidden(&mut self) -> UdfHiddenW { - UdfHiddenW::new(self, 28) - } -} -#[doc = "UDF Control\n\nYou can [`read`](crate::Reg::read) this register and get [`els_udf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_udf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElsUdfSpec; -impl crate::RegisterSpec for ElsUdfSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`els_udf::R`](R) reader structure"] -impl crate::Readable for ElsUdfSpec {} -#[doc = "`write(|w| ..)` method takes [`els_udf::W`](W) writer structure"] -impl crate::Writable for ElsUdfSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ELS_UDF to value 0"] -impl crate::Resettable for ElsUdfSpec {} diff --git a/mcxa276-pac/src/syscon/els_uid.rs b/mcxa276-pac/src/syscon/els_uid.rs deleted file mode 100644 index 9e12d0dff..000000000 --- a/mcxa276-pac/src/syscon/els_uid.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `ELS_UID[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `ELS_UID[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `UID0` reader - UID"] -pub type Uid0R = crate::FieldReader; -#[doc = "Field `UID0` writer - UID"] -pub type Uid0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - UID"] - #[inline(always)] - pub fn uid0(&self) -> Uid0R { - Uid0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - UID"] - #[inline(always)] - pub fn uid0(&mut self) -> Uid0W { - Uid0W::new(self, 0) - } -} -#[doc = "Device UID n\n\nYou can [`read`](crate::Reg::read) this register and get [`els_uid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_uid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ElsUidSpec; -impl crate::RegisterSpec for ElsUidSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`els_uid::R`](R) reader structure"] -impl crate::Readable for ElsUidSpec {} -#[doc = "`write(|w| ..)` method takes [`els_uid::W`](W) writer structure"] -impl crate::Writable for ElsUidSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ELS_UID[%s] to value 0"] -impl crate::Resettable for ElsUidSpec {} diff --git a/mcxa276-pac/src/syscon/frohfdiv.rs b/mcxa276-pac/src/syscon/frohfdiv.rs deleted file mode 100644 index 8e90ba00f..000000000 --- a/mcxa276-pac/src/syscon/frohfdiv.rs +++ /dev/null @@ -1,204 +0,0 @@ -#[doc = "Register `FROHFDIV` reader"] -pub type R = crate::R; -#[doc = "Register `FROHFDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Clock divider value"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Clock divider value"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Resets the divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider is not reset"] - Released = 0, - #[doc = "1: Divider is reset"] - Asserted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` reader - Resets the divider counter"] -pub type ResetR = crate::BitReader; -impl ResetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reset { - match self.bits { - false => Reset::Released, - true => Reset::Asserted, - } - } - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn is_released(&self) -> bool { - *self == Reset::Released - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn is_asserted(&self) -> bool { - *self == Reset::Asserted - } -} -#[doc = "Field `RESET` writer - Resets the divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn released(self) -> &'a mut crate::W { - self.variant(Reset::Released) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn asserted(self) -> &'a mut crate::W { - self.variant(Reset::Asserted) - } -} -#[doc = "Halts the divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - Run = 0, - #[doc = "1: Divider clock is stopped"] - Halt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halts the divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::Run, - true => Halt::Halt, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_run(&self) -> bool { - *self == Halt::Run - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_halt(&self) -> bool { - *self == Halt::Halt - } -} -#[doc = "Field `HALT` writer - Halts the divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn run(self) -> &'a mut crate::W { - self.variant(Halt::Run) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn halt(self) -> &'a mut crate::W { - self.variant(Halt::Halt) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - Stable = 0, - #[doc = "1: Clock frequency is not stable"] - Ongoing = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::Stable, - true => Unstab::Ongoing, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_stable(&self) -> bool { - *self == Unstab::Stable - } - #[doc = "Clock frequency is not stable"] - #[inline(always)] - pub fn is_ongoing(&self) -> bool { - *self == Unstab::Ongoing - } -} -impl R { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&self) -> ResetR { - ResetR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "FRO_HF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frohfdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frohfdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrohfdivSpec; -impl crate::RegisterSpec for FrohfdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`frohfdiv::R`](R) reader structure"] -impl crate::Readable for FrohfdivSpec {} -#[doc = "`write(|w| ..)` method takes [`frohfdiv::W`](W) writer structure"] -impl crate::Writable for FrohfdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FROHFDIV to value 0x4000_0000"] -impl crate::Resettable for FrohfdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/syscon/frolfdiv.rs b/mcxa276-pac/src/syscon/frolfdiv.rs deleted file mode 100644 index d132681f0..000000000 --- a/mcxa276-pac/src/syscon/frolfdiv.rs +++ /dev/null @@ -1,204 +0,0 @@ -#[doc = "Register `FROLFDIV` reader"] -pub type R = crate::R; -#[doc = "Register `FROLFDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Clock divider value"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Clock divider value"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Resets the divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider is not reset"] - Released = 0, - #[doc = "1: Divider is reset"] - Asserted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` reader - Resets the divider counter"] -pub type ResetR = crate::BitReader; -impl ResetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reset { - match self.bits { - false => Reset::Released, - true => Reset::Asserted, - } - } - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn is_released(&self) -> bool { - *self == Reset::Released - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn is_asserted(&self) -> bool { - *self == Reset::Asserted - } -} -#[doc = "Field `RESET` writer - Resets the divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn released(self) -> &'a mut crate::W { - self.variant(Reset::Released) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn asserted(self) -> &'a mut crate::W { - self.variant(Reset::Asserted) - } -} -#[doc = "Halts the divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - Run = 0, - #[doc = "1: Divider clock is stopped"] - Halt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halts the divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::Run, - true => Halt::Halt, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_run(&self) -> bool { - *self == Halt::Run - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_halt(&self) -> bool { - *self == Halt::Halt - } -} -#[doc = "Field `HALT` writer - Halts the divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn run(self) -> &'a mut crate::W { - self.variant(Halt::Run) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn halt(self) -> &'a mut crate::W { - self.variant(Halt::Halt) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - Stable = 0, - #[doc = "1: Clock frequency is not stable"] - Ongoing = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::Stable, - true => Unstab::Ongoing, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_stable(&self) -> bool { - *self == Unstab::Stable - } - #[doc = "Clock frequency is not stable"] - #[inline(always)] - pub fn is_ongoing(&self) -> bool { - *self == Unstab::Ongoing - } -} -impl R { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&self) -> ResetR { - ResetR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "FRO_LF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frolfdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolfdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrolfdivSpec; -impl crate::RegisterSpec for FrolfdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`frolfdiv::R`](R) reader structure"] -impl crate::Readable for FrolfdivSpec {} -#[doc = "`write(|w| ..)` method takes [`frolfdiv::W`](W) writer structure"] -impl crate::Writable for FrolfdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FROLFDIV to value 0x4000_0000"] -impl crate::Resettable for FrolfdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/syscon/gray_code_lsb.rs b/mcxa276-pac/src/syscon/gray_code_lsb.rs deleted file mode 100644 index 631de5f18..000000000 --- a/mcxa276-pac/src/syscon/gray_code_lsb.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `GRAY_CODE_LSB` reader"] -pub type R = crate::R; -#[doc = "Register `GRAY_CODE_LSB` writer"] -pub type W = crate::W; -#[doc = "Field `code_gray_31_0` reader - Gray code \\[31:0\\]"] -pub type CodeGray31_0R = crate::FieldReader; -#[doc = "Field `code_gray_31_0` writer - Gray code \\[31:0\\]"] -pub type CodeGray31_0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Gray code \\[31:0\\]"] - #[inline(always)] - pub fn code_gray_31_0(&self) -> CodeGray31_0R { - CodeGray31_0R::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Gray code \\[31:0\\]"] - #[inline(always)] - pub fn code_gray_31_0(&mut self) -> CodeGray31_0W { - CodeGray31_0W::new(self, 0) - } -} -#[doc = "Gray to Binary Converter Gray Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_lsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_lsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GrayCodeLsbSpec; -impl crate::RegisterSpec for GrayCodeLsbSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gray_code_lsb::R`](R) reader structure"] -impl crate::Readable for GrayCodeLsbSpec {} -#[doc = "`write(|w| ..)` method takes [`gray_code_lsb::W`](W) writer structure"] -impl crate::Writable for GrayCodeLsbSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GRAY_CODE_LSB to value 0"] -impl crate::Resettable for GrayCodeLsbSpec {} diff --git a/mcxa276-pac/src/syscon/gray_code_msb.rs b/mcxa276-pac/src/syscon/gray_code_msb.rs deleted file mode 100644 index e916cd756..000000000 --- a/mcxa276-pac/src/syscon/gray_code_msb.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `GRAY_CODE_MSB` reader"] -pub type R = crate::R; -#[doc = "Register `GRAY_CODE_MSB` writer"] -pub type W = crate::W; -#[doc = "Field `code_gray_41_32` reader - Gray code \\[41:32\\]"] -pub type CodeGray41_32R = crate::FieldReader; -#[doc = "Field `code_gray_41_32` writer - Gray code \\[41:32\\]"] -pub type CodeGray41_32W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:9 - Gray code \\[41:32\\]"] - #[inline(always)] - pub fn code_gray_41_32(&self) -> CodeGray41_32R { - CodeGray41_32R::new((self.bits & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:9 - Gray code \\[41:32\\]"] - #[inline(always)] - pub fn code_gray_41_32(&mut self) -> CodeGray41_32W { - CodeGray41_32W::new(self, 0) - } -} -#[doc = "Gray to Binary Converter Gray Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_msb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_msb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GrayCodeMsbSpec; -impl crate::RegisterSpec for GrayCodeMsbSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`gray_code_msb::R`](R) reader structure"] -impl crate::Readable for GrayCodeMsbSpec {} -#[doc = "`write(|w| ..)` method takes [`gray_code_msb::W`](W) writer structure"] -impl crate::Writable for GrayCodeMsbSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets GRAY_CODE_MSB to value 0"] -impl crate::Resettable for GrayCodeMsbSpec {} diff --git a/mcxa276-pac/src/syscon/jtag_id.rs b/mcxa276-pac/src/syscon/jtag_id.rs deleted file mode 100644 index 9e1d3d410..000000000 --- a/mcxa276-pac/src/syscon/jtag_id.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `JTAG_ID` reader"] -pub type R = crate::R; -#[doc = "Field `JTAG_ID` reader - Indicates the device ID"] -pub type JtagIdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Indicates the device ID"] - #[inline(always)] - pub fn jtag_id(&self) -> JtagIdR { - JtagIdR::new(self.bits) - } -} -#[doc = "JTAG Chip ID\n\nYou can [`read`](crate::Reg::read) this register and get [`jtag_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct JtagIdSpec; -impl crate::RegisterSpec for JtagIdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`jtag_id::R`](R) reader structure"] -impl crate::Readable for JtagIdSpec {} -#[doc = "`reset()` method sets JTAG_ID to value 0x0726_802b"] -impl crate::Resettable for JtagIdSpec { - const RESET_VALUE: u32 = 0x0726_802b; -} diff --git a/mcxa276-pac/src/syscon/lpcac_ctrl.rs b/mcxa276-pac/src/syscon/lpcac_ctrl.rs deleted file mode 100644 index b58299507..000000000 --- a/mcxa276-pac/src/syscon/lpcac_ctrl.rs +++ /dev/null @@ -1,464 +0,0 @@ -#[doc = "Register `LPCAC_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `LPCAC_CTRL` writer"] -pub type W = crate::W; -#[doc = "Disables/enables the cache function.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DisLpcac { - #[doc = "0: Enabled"] - Enable = 0, - #[doc = "1: Disabled"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DisLpcac) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIS_LPCAC` reader - Disables/enables the cache function."] -pub type DisLpcacR = crate::BitReader; -impl DisLpcacR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DisLpcac { - match self.bits { - false => DisLpcac::Enable, - true => DisLpcac::Disable, - } - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DisLpcac::Enable - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DisLpcac::Disable - } -} -#[doc = "Field `DIS_LPCAC` writer - Disables/enables the cache function."] -pub type DisLpcacW<'a, REG> = crate::BitWriter<'a, REG, DisLpcac>; -impl<'a, REG> DisLpcacW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DisLpcac::Enable) - } - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DisLpcac::Disable) - } -} -#[doc = "Clears the cache function.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ClrLpcac { - #[doc = "0: Unclears the cache"] - Enable = 0, - #[doc = "1: Clears the cache"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ClrLpcac) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLR_LPCAC` reader - Clears the cache function."] -pub type ClrLpcacR = crate::BitReader; -impl ClrLpcacR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ClrLpcac { - match self.bits { - false => ClrLpcac::Enable, - true => ClrLpcac::Disable, - } - } - #[doc = "Unclears the cache"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == ClrLpcac::Enable - } - #[doc = "Clears the cache"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == ClrLpcac::Disable - } -} -#[doc = "Field `CLR_LPCAC` writer - Clears the cache function."] -pub type ClrLpcacW<'a, REG> = crate::BitWriter<'a, REG, ClrLpcac>; -impl<'a, REG> ClrLpcacW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Unclears the cache"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(ClrLpcac::Enable) - } - #[doc = "Clears the cache"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(ClrLpcac::Disable) - } -} -#[doc = "Forces no allocation.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FrcNoAlloc { - #[doc = "0: Forces allocation"] - Enable = 0, - #[doc = "1: Forces no allocation"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FrcNoAlloc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRC_NO_ALLOC` reader - Forces no allocation."] -pub type FrcNoAllocR = crate::BitReader; -impl FrcNoAllocR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FrcNoAlloc { - match self.bits { - false => FrcNoAlloc::Enable, - true => FrcNoAlloc::Disable, - } - } - #[doc = "Forces allocation"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == FrcNoAlloc::Enable - } - #[doc = "Forces no allocation"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == FrcNoAlloc::Disable - } -} -#[doc = "Field `FRC_NO_ALLOC` writer - Forces no allocation."] -pub type FrcNoAllocW<'a, REG> = crate::BitWriter<'a, REG, FrcNoAlloc>; -impl<'a, REG> FrcNoAllocW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Forces allocation"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(FrcNoAlloc::Enable) - } - #[doc = "Forces no allocation"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(FrcNoAlloc::Disable) - } -} -#[doc = "Disable LPCAC Write Through Buffer.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DisLpcacWtbf { - #[doc = "0: Enables write through buffer"] - Disable = 0, - #[doc = "1: Disables write through buffer"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DisLpcacWtbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIS_LPCAC_WTBF` reader - Disable LPCAC Write Through Buffer."] -pub type DisLpcacWtbfR = crate::BitReader; -impl DisLpcacWtbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DisLpcacWtbf { - match self.bits { - false => DisLpcacWtbf::Disable, - true => DisLpcacWtbf::Enable, - } - } - #[doc = "Enables write through buffer"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DisLpcacWtbf::Disable - } - #[doc = "Disables write through buffer"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DisLpcacWtbf::Enable - } -} -#[doc = "Field `DIS_LPCAC_WTBF` writer - Disable LPCAC Write Through Buffer."] -pub type DisLpcacWtbfW<'a, REG> = crate::BitWriter<'a, REG, DisLpcacWtbf>; -impl<'a, REG> DisLpcacWtbfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables write through buffer"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DisLpcacWtbf::Disable) - } - #[doc = "Disables write through buffer"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DisLpcacWtbf::Enable) - } -} -#[doc = "Limit LPCAC Write Through Buffer.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LimLpcacWtbf { - #[doc = "0: Write buffer enabled when transaction is bufferable."] - Disable = 0, - #[doc = "1: Write buffer enabled when transaction is cacheable and bufferable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LimLpcacWtbf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LIM_LPCAC_WTBF` reader - Limit LPCAC Write Through Buffer."] -pub type LimLpcacWtbfR = crate::BitReader; -impl LimLpcacWtbfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LimLpcacWtbf { - match self.bits { - false => LimLpcacWtbf::Disable, - true => LimLpcacWtbf::Enable, - } - } - #[doc = "Write buffer enabled when transaction is bufferable."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == LimLpcacWtbf::Disable - } - #[doc = "Write buffer enabled when transaction is cacheable and bufferable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == LimLpcacWtbf::Enable - } -} -#[doc = "Field `LIM_LPCAC_WTBF` writer - Limit LPCAC Write Through Buffer."] -pub type LimLpcacWtbfW<'a, REG> = crate::BitWriter<'a, REG, LimLpcacWtbf>; -impl<'a, REG> LimLpcacWtbfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write buffer enabled when transaction is bufferable."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(LimLpcacWtbf::Disable) - } - #[doc = "Write buffer enabled when transaction is cacheable and bufferable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(LimLpcacWtbf::Enable) - } -} -#[doc = "LPCAC XOM(eXecute-Only-Memory) attribute control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LpcacXom { - #[doc = "0: Disabled."] - Disable = 0, - #[doc = "1: Enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LpcacXom) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPCAC_XOM` reader - LPCAC XOM(eXecute-Only-Memory) attribute control"] -pub type LpcacXomR = crate::BitReader; -impl LpcacXomR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LpcacXom { - match self.bits { - false => LpcacXom::Disable, - true => LpcacXom::Enable, - } - } - #[doc = "Disabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == LpcacXom::Disable - } - #[doc = "Enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == LpcacXom::Enable - } -} -#[doc = "Field `LPCAC_XOM` writer - LPCAC XOM(eXecute-Only-Memory) attribute control"] -pub type LpcacXomW<'a, REG> = crate::BitWriter<'a, REG, LpcacXom>; -impl<'a, REG> LpcacXomW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(LpcacXom::Disable) - } - #[doc = "Enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(LpcacXom::Enable) - } -} -#[doc = "Request LPCAC memories.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LpcacMemReq { - #[doc = "0: Configure shared memories RAMX1 as general memories."] - Disable = 0, - #[doc = "1: Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LpcacMemReq) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LPCAC_MEM_REQ` reader - Request LPCAC memories."] -pub type LpcacMemReqR = crate::BitReader; -impl LpcacMemReqR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LpcacMemReq { - match self.bits { - false => LpcacMemReq::Disable, - true => LpcacMemReq::Enable, - } - } - #[doc = "Configure shared memories RAMX1 as general memories."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == LpcacMemReq::Disable - } - #[doc = "Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == LpcacMemReq::Enable - } -} -#[doc = "Field `LPCAC_MEM_REQ` writer - Request LPCAC memories."] -pub type LpcacMemReqW<'a, REG> = crate::BitWriter<'a, REG, LpcacMemReq>; -impl<'a, REG> LpcacMemReqW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Configure shared memories RAMX1 as general memories."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(LpcacMemReq::Disable) - } - #[doc = "Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(LpcacMemReq::Enable) - } -} -impl R { - #[doc = "Bit 0 - Disables/enables the cache function."] - #[inline(always)] - pub fn dis_lpcac(&self) -> DisLpcacR { - DisLpcacR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Clears the cache function."] - #[inline(always)] - pub fn clr_lpcac(&self) -> ClrLpcacR { - ClrLpcacR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Forces no allocation."] - #[inline(always)] - pub fn frc_no_alloc(&self) -> FrcNoAllocR { - FrcNoAllocR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - Disable LPCAC Write Through Buffer."] - #[inline(always)] - pub fn dis_lpcac_wtbf(&self) -> DisLpcacWtbfR { - DisLpcacWtbfR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Limit LPCAC Write Through Buffer."] - #[inline(always)] - pub fn lim_lpcac_wtbf(&self) -> LimLpcacWtbfR { - LimLpcacWtbfR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 7 - LPCAC XOM(eXecute-Only-Memory) attribute control"] - #[inline(always)] - pub fn lpcac_xom(&self) -> LpcacXomR { - LpcacXomR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Request LPCAC memories."] - #[inline(always)] - pub fn lpcac_mem_req(&self) -> LpcacMemReqR { - LpcacMemReqR::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Disables/enables the cache function."] - #[inline(always)] - pub fn dis_lpcac(&mut self) -> DisLpcacW { - DisLpcacW::new(self, 0) - } - #[doc = "Bit 1 - Clears the cache function."] - #[inline(always)] - pub fn clr_lpcac(&mut self) -> ClrLpcacW { - ClrLpcacW::new(self, 1) - } - #[doc = "Bit 2 - Forces no allocation."] - #[inline(always)] - pub fn frc_no_alloc(&mut self) -> FrcNoAllocW { - FrcNoAllocW::new(self, 2) - } - #[doc = "Bit 4 - Disable LPCAC Write Through Buffer."] - #[inline(always)] - pub fn dis_lpcac_wtbf(&mut self) -> DisLpcacWtbfW { - DisLpcacWtbfW::new(self, 4) - } - #[doc = "Bit 5 - Limit LPCAC Write Through Buffer."] - #[inline(always)] - pub fn lim_lpcac_wtbf(&mut self) -> LimLpcacWtbfW { - LimLpcacWtbfW::new(self, 5) - } - #[doc = "Bit 7 - LPCAC XOM(eXecute-Only-Memory) attribute control"] - #[inline(always)] - pub fn lpcac_xom(&mut self) -> LpcacXomW { - LpcacXomW::new(self, 7) - } - #[doc = "Bit 8 - Request LPCAC memories."] - #[inline(always)] - pub fn lpcac_mem_req(&mut self) -> LpcacMemReqW { - LpcacMemReqW::new(self, 8) - } -} -#[doc = "LPCAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`lpcac_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcac_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LpcacCtrlSpec; -impl crate::RegisterSpec for LpcacCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lpcac_ctrl::R`](R) reader structure"] -impl crate::Readable for LpcacCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`lpcac_ctrl::W`](W) writer structure"] -impl crate::Writable for LpcacCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LPCAC_CTRL to value 0x31"] -impl crate::Resettable for LpcacCtrlSpec { - const RESET_VALUE: u32 = 0x31; -} diff --git a/mcxa276-pac/src/syscon/msfcfg.rs b/mcxa276-pac/src/syscon/msfcfg.rs deleted file mode 100644 index 486a350cf..000000000 --- a/mcxa276-pac/src/syscon/msfcfg.rs +++ /dev/null @@ -1,336 +0,0 @@ -#[doc = "Register `MSFCFG` reader"] -pub type R = crate::R; -#[doc = "Register `MSFCFG` writer"] -pub type W = crate::W; -#[doc = "user IFR sector 0 erase control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IfrEraseDis0 { - #[doc = "0: Enable IFR sector erase."] - Enable = 0, - #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IfrEraseDis0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IFR_ERASE_DIS0` reader - user IFR sector 0 erase control"] -pub type IfrEraseDis0R = crate::BitReader; -impl IfrEraseDis0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IfrEraseDis0 { - match self.bits { - false => IfrEraseDis0::Enable, - true => IfrEraseDis0::Disable, - } - } - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IfrEraseDis0::Enable - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IfrEraseDis0::Disable - } -} -#[doc = "Field `IFR_ERASE_DIS0` writer - user IFR sector 0 erase control"] -pub type IfrEraseDis0W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis0>; -impl<'a, REG> IfrEraseDis0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis0::Enable) - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis0::Disable) - } -} -#[doc = "user IFR sector 1 erase control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IfrEraseDis1 { - #[doc = "0: Enable IFR sector erase."] - Enable = 0, - #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IfrEraseDis1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IFR_ERASE_DIS1` reader - user IFR sector 1 erase control"] -pub type IfrEraseDis1R = crate::BitReader; -impl IfrEraseDis1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IfrEraseDis1 { - match self.bits { - false => IfrEraseDis1::Enable, - true => IfrEraseDis1::Disable, - } - } - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IfrEraseDis1::Enable - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IfrEraseDis1::Disable - } -} -#[doc = "Field `IFR_ERASE_DIS1` writer - user IFR sector 1 erase control"] -pub type IfrEraseDis1W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis1>; -impl<'a, REG> IfrEraseDis1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis1::Enable) - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis1::Disable) - } -} -#[doc = "user IFR sector 2 erase control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IfrEraseDis2 { - #[doc = "0: Enable IFR sector erase."] - Enable = 0, - #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IfrEraseDis2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IFR_ERASE_DIS2` reader - user IFR sector 2 erase control"] -pub type IfrEraseDis2R = crate::BitReader; -impl IfrEraseDis2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IfrEraseDis2 { - match self.bits { - false => IfrEraseDis2::Enable, - true => IfrEraseDis2::Disable, - } - } - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IfrEraseDis2::Enable - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IfrEraseDis2::Disable - } -} -#[doc = "Field `IFR_ERASE_DIS2` writer - user IFR sector 2 erase control"] -pub type IfrEraseDis2W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis2>; -impl<'a, REG> IfrEraseDis2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis2::Enable) - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis2::Disable) - } -} -#[doc = "user IFR sector 3 erase control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IfrEraseDis3 { - #[doc = "0: Enable IFR sector erase."] - Enable = 0, - #[doc = "1: Disable IFR sector erase, write one lock until a system reset."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IfrEraseDis3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IFR_ERASE_DIS3` reader - user IFR sector 3 erase control"] -pub type IfrEraseDis3R = crate::BitReader; -impl IfrEraseDis3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IfrEraseDis3 { - match self.bits { - false => IfrEraseDis3::Enable, - true => IfrEraseDis3::Disable, - } - } - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IfrEraseDis3::Enable - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IfrEraseDis3::Disable - } -} -#[doc = "Field `IFR_ERASE_DIS3` writer - user IFR sector 3 erase control"] -pub type IfrEraseDis3W<'a, REG> = crate::BitWriter<'a, REG, IfrEraseDis3>; -impl<'a, REG> IfrEraseDis3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable IFR sector erase."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis3::Enable) - } - #[doc = "Disable IFR sector erase, write one lock until a system reset."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(IfrEraseDis3::Disable) - } -} -#[doc = "Mass erase control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum MassEraseDis { - #[doc = "0: Enables mass erase"] - Enable = 0, - #[doc = "1: Disables mass erase, write one lock until a system reset."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: MassEraseDis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MASS_ERASE_DIS` reader - Mass erase control"] -pub type MassEraseDisR = crate::BitReader; -impl MassEraseDisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> MassEraseDis { - match self.bits { - false => MassEraseDis::Enable, - true => MassEraseDis::Disable, - } - } - #[doc = "Enables mass erase"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == MassEraseDis::Enable - } - #[doc = "Disables mass erase, write one lock until a system reset."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == MassEraseDis::Disable - } -} -#[doc = "Field `MASS_ERASE_DIS` writer - Mass erase control"] -pub type MassEraseDisW<'a, REG> = crate::BitWriter<'a, REG, MassEraseDis>; -impl<'a, REG> MassEraseDisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables mass erase"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(MassEraseDis::Enable) - } - #[doc = "Disables mass erase, write one lock until a system reset."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(MassEraseDis::Disable) - } -} -impl R { - #[doc = "Bit 0 - user IFR sector 0 erase control"] - #[inline(always)] - pub fn ifr_erase_dis0(&self) -> IfrEraseDis0R { - IfrEraseDis0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - user IFR sector 1 erase control"] - #[inline(always)] - pub fn ifr_erase_dis1(&self) -> IfrEraseDis1R { - IfrEraseDis1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - user IFR sector 2 erase control"] - #[inline(always)] - pub fn ifr_erase_dis2(&self) -> IfrEraseDis2R { - IfrEraseDis2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - user IFR sector 3 erase control"] - #[inline(always)] - pub fn ifr_erase_dis3(&self) -> IfrEraseDis3R { - IfrEraseDis3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Mass erase control"] - #[inline(always)] - pub fn mass_erase_dis(&self) -> MassEraseDisR { - MassEraseDisR::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - user IFR sector 0 erase control"] - #[inline(always)] - pub fn ifr_erase_dis0(&mut self) -> IfrEraseDis0W { - IfrEraseDis0W::new(self, 0) - } - #[doc = "Bit 1 - user IFR sector 1 erase control"] - #[inline(always)] - pub fn ifr_erase_dis1(&mut self) -> IfrEraseDis1W { - IfrEraseDis1W::new(self, 1) - } - #[doc = "Bit 2 - user IFR sector 2 erase control"] - #[inline(always)] - pub fn ifr_erase_dis2(&mut self) -> IfrEraseDis2W { - IfrEraseDis2W::new(self, 2) - } - #[doc = "Bit 3 - user IFR sector 3 erase control"] - #[inline(always)] - pub fn ifr_erase_dis3(&mut self) -> IfrEraseDis3W { - IfrEraseDis3W::new(self, 3) - } - #[doc = "Bit 8 - Mass erase control"] - #[inline(always)] - pub fn mass_erase_dis(&mut self) -> MassEraseDisW { - MassEraseDisW::new(self, 8) - } -} -#[doc = "MSF Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`msfcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msfcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MsfcfgSpec; -impl crate::RegisterSpec for MsfcfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`msfcfg::R`](R) reader structure"] -impl crate::Readable for MsfcfgSpec {} -#[doc = "`write(|w| ..)` method takes [`msfcfg::W`](W) writer structure"] -impl crate::Writable for MsfcfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MSFCFG to value 0"] -impl crate::Resettable for MsfcfgSpec {} diff --git a/mcxa276-pac/src/syscon/nmisrc.rs b/mcxa276-pac/src/syscon/nmisrc.rs deleted file mode 100644 index ac3b3a449..000000000 --- a/mcxa276-pac/src/syscon/nmisrc.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `NMISRC` reader"] -pub type R = crate::R; -#[doc = "Register `NMISRC` writer"] -pub type W = crate::W; -#[doc = "Field `IRQCPU0` reader - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] -pub type Irqcpu0R = crate::FieldReader; -#[doc = "Field `IRQCPU0` writer - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] -pub type Irqcpu0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Nmiencpu0 { - #[doc = "0: Disable."] - Disable = 0, - #[doc = "1: Enable."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Nmiencpu0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NMIENCPU0` reader - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] -pub type Nmiencpu0R = crate::BitReader; -impl Nmiencpu0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Nmiencpu0 { - match self.bits { - false => Nmiencpu0::Disable, - true => Nmiencpu0::Enable, - } - } - #[doc = "Disable."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Nmiencpu0::Disable - } - #[doc = "Enable."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Nmiencpu0::Enable - } -} -#[doc = "Field `NMIENCPU0` writer - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] -pub type Nmiencpu0W<'a, REG> = crate::BitWriter<'a, REG, Nmiencpu0>; -impl<'a, REG> Nmiencpu0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Nmiencpu0::Disable) - } - #[doc = "Enable."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Nmiencpu0::Enable) - } -} -impl R { - #[doc = "Bits 0:7 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] - #[inline(always)] - pub fn irqcpu0(&self) -> Irqcpu0R { - Irqcpu0R::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 31 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] - #[inline(always)] - pub fn nmiencpu0(&self) -> Nmiencpu0R { - Nmiencpu0R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] - #[inline(always)] - pub fn irqcpu0(&mut self) -> Irqcpu0W { - Irqcpu0W::new(self, 0) - } - #[doc = "Bit 31 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] - #[inline(always)] - pub fn nmiencpu0(&mut self) -> Nmiencpu0W { - Nmiencpu0W::new(self, 31) - } -} -#[doc = "NMI Source Select\n\nYou can [`read`](crate::Reg::read) this register and get [`nmisrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmisrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct NmisrcSpec; -impl crate::RegisterSpec for NmisrcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`nmisrc::R`](R) reader structure"] -impl crate::Readable for NmisrcSpec {} -#[doc = "`write(|w| ..)` method takes [`nmisrc::W`](W) writer structure"] -impl crate::Writable for NmisrcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets NMISRC to value 0"] -impl crate::Resettable for NmisrcSpec {} diff --git a/mcxa276-pac/src/syscon/nvm_ctrl.rs b/mcxa276-pac/src/syscon/nvm_ctrl.rs deleted file mode 100644 index 307e45151..000000000 --- a/mcxa276-pac/src/syscon/nvm_ctrl.rs +++ /dev/null @@ -1,338 +0,0 @@ -#[doc = "Register `NVM_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `NVM_CTRL` writer"] -pub type W = crate::W; -#[doc = "Flash speculation control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DisFlashSpec { - #[doc = "0: Enables flash speculation"] - Enable = 0, - #[doc = "1: Disables flash speculation"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DisFlashSpec) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIS_FLASH_SPEC` reader - Flash speculation control"] -pub type DisFlashSpecR = crate::BitReader; -impl DisFlashSpecR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DisFlashSpec { - match self.bits { - false => DisFlashSpec::Enable, - true => DisFlashSpec::Disable, - } - } - #[doc = "Enables flash speculation"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DisFlashSpec::Enable - } - #[doc = "Disables flash speculation"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DisFlashSpec::Disable - } -} -#[doc = "Field `DIS_FLASH_SPEC` writer - Flash speculation control"] -pub type DisFlashSpecW<'a, REG> = crate::BitWriter<'a, REG, DisFlashSpec>; -impl<'a, REG> DisFlashSpecW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables flash speculation"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DisFlashSpec::Enable) - } - #[doc = "Disables flash speculation"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DisFlashSpec::Disable) - } -} -#[doc = "Flash data speculation control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DisDataSpec { - #[doc = "0: Enables data speculation"] - Enable = 0, - #[doc = "1: Disables data speculation"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DisDataSpec) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIS_DATA_SPEC` reader - Flash data speculation control"] -pub type DisDataSpecR = crate::BitReader; -impl DisDataSpecR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DisDataSpec { - match self.bits { - false => DisDataSpec::Enable, - true => DisDataSpec::Disable, - } - } - #[doc = "Enables data speculation"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DisDataSpec::Enable - } - #[doc = "Disables data speculation"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DisDataSpec::Disable - } -} -#[doc = "Field `DIS_DATA_SPEC` writer - Flash data speculation control"] -pub type DisDataSpecW<'a, REG> = crate::BitWriter<'a, REG, DisDataSpec>; -impl<'a, REG> DisDataSpecW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables data speculation"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DisDataSpec::Enable) - } - #[doc = "Disables data speculation"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DisDataSpec::Disable) - } -} -#[doc = "FLASH stall on busy control\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FlashStallEn { - #[doc = "0: No stall on FLASH busy"] - Enable = 0, - #[doc = "1: Stall on FLASH busy"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FlashStallEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FLASH_STALL_EN` reader - FLASH stall on busy control"] -pub type FlashStallEnR = crate::BitReader; -impl FlashStallEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FlashStallEn { - match self.bits { - false => FlashStallEn::Enable, - true => FlashStallEn::Disable, - } - } - #[doc = "No stall on FLASH busy"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == FlashStallEn::Enable - } - #[doc = "Stall on FLASH busy"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == FlashStallEn::Disable - } -} -#[doc = "Field `FLASH_STALL_EN` writer - FLASH stall on busy control"] -pub type FlashStallEnW<'a, REG> = crate::BitWriter<'a, REG, FlashStallEn>; -impl<'a, REG> FlashStallEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No stall on FLASH busy"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(FlashStallEn::Enable) - } - #[doc = "Stall on FLASH busy"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(FlashStallEn::Disable) - } -} -#[doc = "Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DisMbeccErrInst { - #[doc = "0: Enables bus error on multi-bit ECC error for instruction"] - Enable = 0, - #[doc = "1: Disables bus error on multi-bit ECC error for instruction"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DisMbeccErrInst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIS_MBECC_ERR_INST` reader - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] -pub type DisMbeccErrInstR = crate::BitReader; -impl DisMbeccErrInstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DisMbeccErrInst { - match self.bits { - false => DisMbeccErrInst::Enable, - true => DisMbeccErrInst::Disable, - } - } - #[doc = "Enables bus error on multi-bit ECC error for instruction"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DisMbeccErrInst::Enable - } - #[doc = "Disables bus error on multi-bit ECC error for instruction"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DisMbeccErrInst::Disable - } -} -#[doc = "Field `DIS_MBECC_ERR_INST` writer - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] -pub type DisMbeccErrInstW<'a, REG> = crate::BitWriter<'a, REG, DisMbeccErrInst>; -impl<'a, REG> DisMbeccErrInstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables bus error on multi-bit ECC error for instruction"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DisMbeccErrInst::Enable) - } - #[doc = "Disables bus error on multi-bit ECC error for instruction"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DisMbeccErrInst::Disable) - } -} -#[doc = "Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DisMbeccErrData { - #[doc = "0: Enables bus error on multi-bit ECC error for data"] - Enable = 0, - #[doc = "1: Disables bus error on multi-bit ECC error for data"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DisMbeccErrData) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DIS_MBECC_ERR_DATA` reader - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] -pub type DisMbeccErrDataR = crate::BitReader; -impl DisMbeccErrDataR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DisMbeccErrData { - match self.bits { - false => DisMbeccErrData::Enable, - true => DisMbeccErrData::Disable, - } - } - #[doc = "Enables bus error on multi-bit ECC error for data"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DisMbeccErrData::Enable - } - #[doc = "Disables bus error on multi-bit ECC error for data"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DisMbeccErrData::Disable - } -} -#[doc = "Field `DIS_MBECC_ERR_DATA` writer - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] -pub type DisMbeccErrDataW<'a, REG> = crate::BitWriter<'a, REG, DisMbeccErrData>; -impl<'a, REG> DisMbeccErrDataW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enables bus error on multi-bit ECC error for data"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DisMbeccErrData::Enable) - } - #[doc = "Disables bus error on multi-bit ECC error for data"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DisMbeccErrData::Disable) - } -} -impl R { - #[doc = "Bit 0 - Flash speculation control"] - #[inline(always)] - pub fn dis_flash_spec(&self) -> DisFlashSpecR { - DisFlashSpecR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Flash data speculation control"] - #[inline(always)] - pub fn dis_data_spec(&self) -> DisDataSpecR { - DisDataSpecR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 10 - FLASH stall on busy control"] - #[inline(always)] - pub fn flash_stall_en(&self) -> FlashStallEnR { - FlashStallEnR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 16 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] - #[inline(always)] - pub fn dis_mbecc_err_inst(&self) -> DisMbeccErrInstR { - DisMbeccErrInstR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] - #[inline(always)] - pub fn dis_mbecc_err_data(&self) -> DisMbeccErrDataR { - DisMbeccErrDataR::new(((self.bits >> 17) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Flash speculation control"] - #[inline(always)] - pub fn dis_flash_spec(&mut self) -> DisFlashSpecW { - DisFlashSpecW::new(self, 0) - } - #[doc = "Bit 1 - Flash data speculation control"] - #[inline(always)] - pub fn dis_data_spec(&mut self) -> DisDataSpecW { - DisDataSpecW::new(self, 1) - } - #[doc = "Bit 10 - FLASH stall on busy control"] - #[inline(always)] - pub fn flash_stall_en(&mut self) -> FlashStallEnW { - FlashStallEnW::new(self, 10) - } - #[doc = "Bit 16 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] - #[inline(always)] - pub fn dis_mbecc_err_inst(&mut self) -> DisMbeccErrInstW { - DisMbeccErrInstW::new(self, 16) - } - #[doc = "Bit 17 - Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative"] - #[inline(always)] - pub fn dis_mbecc_err_data(&mut self) -> DisMbeccErrDataW { - DisMbeccErrDataW::new(self, 17) - } -} -#[doc = "NVM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`nvm_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvm_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct NvmCtrlSpec; -impl crate::RegisterSpec for NvmCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`nvm_ctrl::R`](R) reader structure"] -impl crate::Readable for NvmCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`nvm_ctrl::W`](W) writer structure"] -impl crate::Writable for NvmCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets NVM_CTRL to value 0x0002_0400"] -impl crate::Resettable for NvmCtrlSpec { - const RESET_VALUE: u32 = 0x0002_0400; -} diff --git a/mcxa276-pac/src/syscon/pll1clkdiv.rs b/mcxa276-pac/src/syscon/pll1clkdiv.rs deleted file mode 100644 index 3c4608465..000000000 --- a/mcxa276-pac/src/syscon/pll1clkdiv.rs +++ /dev/null @@ -1,204 +0,0 @@ -#[doc = "Register `PLL1CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `PLL1CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Clock divider value"] -pub type DivR = crate::FieldReader; -#[doc = "Field `DIV` writer - Clock divider value"] -pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Resets the divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider is not reset"] - Released = 0, - #[doc = "1: Divider is reset"] - Asserted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` reader - Resets the divider counter"] -pub type ResetR = crate::BitReader; -impl ResetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reset { - match self.bits { - false => Reset::Released, - true => Reset::Asserted, - } - } - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn is_released(&self) -> bool { - *self == Reset::Released - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn is_asserted(&self) -> bool { - *self == Reset::Asserted - } -} -#[doc = "Field `RESET` writer - Resets the divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn released(self) -> &'a mut crate::W { - self.variant(Reset::Released) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn asserted(self) -> &'a mut crate::W { - self.variant(Reset::Asserted) - } -} -#[doc = "Halts the divider counter\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - Run = 0, - #[doc = "1: Divider clock is stopped"] - Halt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halts the divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::Run, - true => Halt::Halt, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_run(&self) -> bool { - *self == Halt::Run - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_halt(&self) -> bool { - *self == Halt::Halt - } -} -#[doc = "Field `HALT` writer - Halts the divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn run(self) -> &'a mut crate::W { - self.variant(Halt::Run) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn halt(self) -> &'a mut crate::W { - self.variant(Halt::Halt) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - Stable = 0, - #[doc = "1: Clock frequency is not stable"] - Ongoing = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::Stable, - true => Unstab::Ongoing, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_stable(&self) -> bool { - *self == Unstab::Stable - } - #[doc = "Clock frequency is not stable"] - #[inline(always)] - pub fn is_ongoing(&self) -> bool { - *self == Unstab::Ongoing - } -} -impl R { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&self) -> ResetR { - ResetR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&mut self) -> DivW { - DivW::new(self, 0) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "PLL1_CLK_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pll1clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll1clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pll1clkdivSpec; -impl crate::RegisterSpec for Pll1clkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pll1clkdiv::R`](R) reader structure"] -impl crate::Readable for Pll1clkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`pll1clkdiv::W`](W) writer structure"] -impl crate::Writable for Pll1clkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PLL1CLKDIV to value 0x4000_0000"] -impl crate::Resettable for Pll1clkdivSpec { - const RESET_VALUE: u32 = 0x4000_0000; -} diff --git a/mcxa276-pac/src/syscon/protlvl.rs b/mcxa276-pac/src/syscon/protlvl.rs deleted file mode 100644 index 84ba46f16..000000000 --- a/mcxa276-pac/src/syscon/protlvl.rs +++ /dev/null @@ -1,210 +0,0 @@ -#[doc = "Register `PROTLVL` reader"] -pub type R = crate::R; -#[doc = "Register `PROTLVL` writer"] -pub type W = crate::W; -#[doc = "Control privileged access of EIM, ERM, Flexcan, MBC, SCG.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Priv { - #[doc = "0: privileged access is disabled. the peripherals could be access in user mode."] - Disable = 0, - #[doc = "1: privileged access is enabled. the peripherals could be access in privilege mode."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Priv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PRIV` reader - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] -pub type PrivR = crate::BitReader; -impl PrivR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Priv { - match self.bits { - false => Priv::Disable, - true => Priv::Enable, - } - } - #[doc = "privileged access is disabled. the peripherals could be access in user mode."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Priv::Disable - } - #[doc = "privileged access is enabled. the peripherals could be access in privilege mode."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Priv::Enable - } -} -#[doc = "Field `PRIV` writer - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] -pub type PrivW<'a, REG> = crate::BitWriter<'a, REG, Priv>; -impl<'a, REG> PrivW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "privileged access is disabled. the peripherals could be access in user mode."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Priv::Disable) - } - #[doc = "privileged access is enabled. the peripherals could be access in privilege mode."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Priv::Enable) - } -} -#[doc = "Control write access to Nonsecure MPU memory regions.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Locknsmpu { - #[doc = "0: Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] - Enable = 0, - #[doc = "1: Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Locknsmpu) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCKNSMPU` reader - Control write access to Nonsecure MPU memory regions."] -pub type LocknsmpuR = crate::BitReader; -impl LocknsmpuR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Locknsmpu { - match self.bits { - false => Locknsmpu::Enable, - true => Locknsmpu::Disable, - } - } - #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Locknsmpu::Enable - } - #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Locknsmpu::Disable - } -} -#[doc = "Field `LOCKNSMPU` writer - Control write access to Nonsecure MPU memory regions."] -pub type LocknsmpuW<'a, REG> = crate::BitWriter<'a, REG, Locknsmpu>; -impl<'a, REG> LocknsmpuW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Locknsmpu::Enable) - } - #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Locknsmpu::Disable) - } -} -#[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: This register is not locked and can be altered."] - Lock0 = 0, - #[doc = "1: This register is locked and cannot be altered until a system reset."] - Lock1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Lock0, - true => Lock::Lock1, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_lock_0(&self) -> bool { - *self == Lock::Lock0 - } - #[doc = "This register is locked and cannot be altered until a system reset."] - #[inline(always)] - pub fn is_lock_1(&self) -> bool { - *self == Lock::Lock1 - } -} -#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn lock_0(self) -> &'a mut crate::W { - self.variant(Lock::Lock0) - } - #[doc = "This register is locked and cannot be altered until a system reset."] - #[inline(always)] - pub fn lock_1(self) -> &'a mut crate::W { - self.variant(Lock::Lock1) - } -} -impl R { - #[doc = "Bit 0 - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] - #[inline(always)] - pub fn priv_(&self) -> PrivR { - PrivR::new((self.bits & 1) != 0) - } - #[doc = "Bit 16 - Control write access to Nonsecure MPU memory regions."] - #[inline(always)] - pub fn locknsmpu(&self) -> LocknsmpuR { - LocknsmpuR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] - #[inline(always)] - pub fn priv_(&mut self) -> PrivW { - PrivW::new(self, 0) - } - #[doc = "Bit 16 - Control write access to Nonsecure MPU memory regions."] - #[inline(always)] - pub fn locknsmpu(&mut self) -> LocknsmpuW { - LocknsmpuW::new(self, 16) - } - #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 31) - } -} -#[doc = "Protect Level Control\n\nYou can [`read`](crate::Reg::read) this register and get [`protlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`protlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ProtlvlSpec; -impl crate::RegisterSpec for ProtlvlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`protlvl::R`](R) reader structure"] -impl crate::Readable for ProtlvlSpec {} -#[doc = "`write(|w| ..)` method takes [`protlvl::W`](W) writer structure"] -impl crate::Writable for ProtlvlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PROTLVL to value 0"] -impl crate::Resettable for ProtlvlSpec {} diff --git a/mcxa276-pac/src/syscon/pwm0subctl.rs b/mcxa276-pac/src/syscon/pwm0subctl.rs deleted file mode 100644 index 97654b1b0..000000000 --- a/mcxa276-pac/src/syscon/pwm0subctl.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `PWM0SUBCTL` reader"] -pub type R = crate::R; -#[doc = "Register `PWM0SUBCTL` writer"] -pub type W = crate::W; -#[doc = "Enables PWM0 SUB Clock0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk0En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk0En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK0_EN` reader - Enables PWM0 SUB Clock0"] -pub type Clk0EnR = crate::BitReader; -impl Clk0EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk0En { - match self.bits { - false => Clk0En::Disable, - true => Clk0En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk0En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk0En::Enable - } -} -#[doc = "Field `CLK0_EN` writer - Enables PWM0 SUB Clock0"] -pub type Clk0EnW<'a, REG> = crate::BitWriter<'a, REG, Clk0En>; -impl<'a, REG> Clk0EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk0En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk0En::Enable) - } -} -#[doc = "Enables PWM0 SUB Clock1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk1En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk1En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK1_EN` reader - Enables PWM0 SUB Clock1"] -pub type Clk1EnR = crate::BitReader; -impl Clk1EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk1En { - match self.bits { - false => Clk1En::Disable, - true => Clk1En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk1En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk1En::Enable - } -} -#[doc = "Field `CLK1_EN` writer - Enables PWM0 SUB Clock1"] -pub type Clk1EnW<'a, REG> = crate::BitWriter<'a, REG, Clk1En>; -impl<'a, REG> Clk1EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk1En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk1En::Enable) - } -} -#[doc = "Enables PWM0 SUB Clock2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk2En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk2En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK2_EN` reader - Enables PWM0 SUB Clock2"] -pub type Clk2EnR = crate::BitReader; -impl Clk2EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk2En { - match self.bits { - false => Clk2En::Disable, - true => Clk2En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk2En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk2En::Enable - } -} -#[doc = "Field `CLK2_EN` writer - Enables PWM0 SUB Clock2"] -pub type Clk2EnW<'a, REG> = crate::BitWriter<'a, REG, Clk2En>; -impl<'a, REG> Clk2EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk2En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk2En::Enable) - } -} -#[doc = "Enables PWM0 SUB Clock3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk3En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk3En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK3_EN` reader - Enables PWM0 SUB Clock3"] -pub type Clk3EnR = crate::BitReader; -impl Clk3EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk3En { - match self.bits { - false => Clk3En::Disable, - true => Clk3En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk3En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk3En::Enable - } -} -#[doc = "Field `CLK3_EN` writer - Enables PWM0 SUB Clock3"] -pub type Clk3EnW<'a, REG> = crate::BitWriter<'a, REG, Clk3En>; -impl<'a, REG> Clk3EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk3En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk3En::Enable) - } -} -impl R { - #[doc = "Bit 0 - Enables PWM0 SUB Clock0"] - #[inline(always)] - pub fn clk0_en(&self) -> Clk0EnR { - Clk0EnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Enables PWM0 SUB Clock1"] - #[inline(always)] - pub fn clk1_en(&self) -> Clk1EnR { - Clk1EnR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Enables PWM0 SUB Clock2"] - #[inline(always)] - pub fn clk2_en(&self) -> Clk2EnR { - Clk2EnR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Enables PWM0 SUB Clock3"] - #[inline(always)] - pub fn clk3_en(&self) -> Clk3EnR { - Clk3EnR::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enables PWM0 SUB Clock0"] - #[inline(always)] - pub fn clk0_en(&mut self) -> Clk0EnW { - Clk0EnW::new(self, 0) - } - #[doc = "Bit 1 - Enables PWM0 SUB Clock1"] - #[inline(always)] - pub fn clk1_en(&mut self) -> Clk1EnW { - Clk1EnW::new(self, 1) - } - #[doc = "Bit 2 - Enables PWM0 SUB Clock2"] - #[inline(always)] - pub fn clk2_en(&mut self) -> Clk2EnW { - Clk2EnW::new(self, 2) - } - #[doc = "Bit 3 - Enables PWM0 SUB Clock3"] - #[inline(always)] - pub fn clk3_en(&mut self) -> Clk3EnW { - Clk3EnW::new(self, 3) - } -} -#[doc = "PWM0 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0subctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0subctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pwm0subctlSpec; -impl crate::RegisterSpec for Pwm0subctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pwm0subctl::R`](R) reader structure"] -impl crate::Readable for Pwm0subctlSpec {} -#[doc = "`write(|w| ..)` method takes [`pwm0subctl::W`](W) writer structure"] -impl crate::Writable for Pwm0subctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PWM0SUBCTL to value 0"] -impl crate::Resettable for Pwm0subctlSpec {} diff --git a/mcxa276-pac/src/syscon/pwm1subctl.rs b/mcxa276-pac/src/syscon/pwm1subctl.rs deleted file mode 100644 index c71180f04..000000000 --- a/mcxa276-pac/src/syscon/pwm1subctl.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `PWM1SUBCTL` reader"] -pub type R = crate::R; -#[doc = "Register `PWM1SUBCTL` writer"] -pub type W = crate::W; -#[doc = "Enables PWM1 SUB Clock0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk0En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk0En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK0_EN` reader - Enables PWM1 SUB Clock0"] -pub type Clk0EnR = crate::BitReader; -impl Clk0EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk0En { - match self.bits { - false => Clk0En::Disable, - true => Clk0En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk0En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk0En::Enable - } -} -#[doc = "Field `CLK0_EN` writer - Enables PWM1 SUB Clock0"] -pub type Clk0EnW<'a, REG> = crate::BitWriter<'a, REG, Clk0En>; -impl<'a, REG> Clk0EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk0En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk0En::Enable) - } -} -#[doc = "Enables PWM1 SUB Clock1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk1En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk1En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK1_EN` reader - Enables PWM1 SUB Clock1"] -pub type Clk1EnR = crate::BitReader; -impl Clk1EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk1En { - match self.bits { - false => Clk1En::Disable, - true => Clk1En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk1En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk1En::Enable - } -} -#[doc = "Field `CLK1_EN` writer - Enables PWM1 SUB Clock1"] -pub type Clk1EnW<'a, REG> = crate::BitWriter<'a, REG, Clk1En>; -impl<'a, REG> Clk1EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk1En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk1En::Enable) - } -} -#[doc = "Enables PWM1 SUB Clock2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk2En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk2En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK2_EN` reader - Enables PWM1 SUB Clock2"] -pub type Clk2EnR = crate::BitReader; -impl Clk2EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk2En { - match self.bits { - false => Clk2En::Disable, - true => Clk2En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk2En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk2En::Enable - } -} -#[doc = "Field `CLK2_EN` writer - Enables PWM1 SUB Clock2"] -pub type Clk2EnW<'a, REG> = crate::BitWriter<'a, REG, Clk2En>; -impl<'a, REG> Clk2EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk2En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk2En::Enable) - } -} -#[doc = "Enables PWM1 SUB Clock3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Clk3En { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Clk3En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLK3_EN` reader - Enables PWM1 SUB Clock3"] -pub type Clk3EnR = crate::BitReader; -impl Clk3EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Clk3En { - match self.bits { - false => Clk3En::Disable, - true => Clk3En::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Clk3En::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Clk3En::Enable - } -} -#[doc = "Field `CLK3_EN` writer - Enables PWM1 SUB Clock3"] -pub type Clk3EnW<'a, REG> = crate::BitWriter<'a, REG, Clk3En>; -impl<'a, REG> Clk3EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Clk3En::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Clk3En::Enable) - } -} -impl R { - #[doc = "Bit 0 - Enables PWM1 SUB Clock0"] - #[inline(always)] - pub fn clk0_en(&self) -> Clk0EnR { - Clk0EnR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Enables PWM1 SUB Clock1"] - #[inline(always)] - pub fn clk1_en(&self) -> Clk1EnR { - Clk1EnR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Enables PWM1 SUB Clock2"] - #[inline(always)] - pub fn clk2_en(&self) -> Clk2EnR { - Clk2EnR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Enables PWM1 SUB Clock3"] - #[inline(always)] - pub fn clk3_en(&self) -> Clk3EnR { - Clk3EnR::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enables PWM1 SUB Clock0"] - #[inline(always)] - pub fn clk0_en(&mut self) -> Clk0EnW { - Clk0EnW::new(self, 0) - } - #[doc = "Bit 1 - Enables PWM1 SUB Clock1"] - #[inline(always)] - pub fn clk1_en(&mut self) -> Clk1EnW { - Clk1EnW::new(self, 1) - } - #[doc = "Bit 2 - Enables PWM1 SUB Clock2"] - #[inline(always)] - pub fn clk2_en(&mut self) -> Clk2EnW { - Clk2EnW::new(self, 2) - } - #[doc = "Bit 3 - Enables PWM1 SUB Clock3"] - #[inline(always)] - pub fn clk3_en(&mut self) -> Clk3EnW { - Clk3EnW::new(self, 3) - } -} -#[doc = "PWM1 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1subctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1subctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pwm1subctlSpec; -impl crate::RegisterSpec for Pwm1subctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pwm1subctl::R`](R) reader structure"] -impl crate::Readable for Pwm1subctlSpec {} -#[doc = "`write(|w| ..)` method takes [`pwm1subctl::W`](W) writer structure"] -impl crate::Writable for Pwm1subctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PWM1SUBCTL to value 0"] -impl crate::Resettable for Pwm1subctlSpec {} diff --git a/mcxa276-pac/src/syscon/ram_ctrl.rs b/mcxa276-pac/src/syscon/ram_ctrl.rs deleted file mode 100644 index b8e951205..000000000 --- a/mcxa276-pac/src/syscon/ram_ctrl.rs +++ /dev/null @@ -1,338 +0,0 @@ -#[doc = "Register `RAM_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `RAM_CTRL` writer"] -pub type W = crate::W; -#[doc = "RAMA ECC enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RamaEccEnable { - #[doc = "0: ECC is disabled"] - Disable = 0, - #[doc = "1: ECC is enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RamaEccEnable) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMA_ECC_ENABLE` reader - RAMA ECC enable"] -pub type RamaEccEnableR = crate::BitReader; -impl RamaEccEnableR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RamaEccEnable { - match self.bits { - false => RamaEccEnable::Disable, - true => RamaEccEnable::Enable, - } - } - #[doc = "ECC is disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RamaEccEnable::Disable - } - #[doc = "ECC is enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RamaEccEnable::Enable - } -} -#[doc = "Field `RAMA_ECC_ENABLE` writer - RAMA ECC enable"] -pub type RamaEccEnableW<'a, REG> = crate::BitWriter<'a, REG, RamaEccEnable>; -impl<'a, REG> RamaEccEnableW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ECC is disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RamaEccEnable::Disable) - } - #[doc = "ECC is enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RamaEccEnable::Enable) - } -} -#[doc = "RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RamaCgOverride { - #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] - Disable = 0, - #[doc = "1: Auto clock gating feature is disabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RamaCgOverride) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMA_CG_OVERRIDE` reader - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] -pub type RamaCgOverrideR = crate::BitReader; -impl RamaCgOverrideR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RamaCgOverride { - match self.bits { - false => RamaCgOverride::Disable, - true => RamaCgOverride::Enable, - } - } - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RamaCgOverride::Disable - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RamaCgOverride::Enable - } -} -#[doc = "Field `RAMA_CG_OVERRIDE` writer - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] -pub type RamaCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamaCgOverride>; -impl<'a, REG> RamaCgOverrideW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RamaCgOverride::Disable) - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RamaCgOverride::Enable) - } -} -#[doc = "RAMX bank clock gating control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RamxCgOverride { - #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] - Disable = 0, - #[doc = "1: Auto clock gating feature is disabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RamxCgOverride) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMX_CG_OVERRIDE` reader - RAMX bank clock gating control"] -pub type RamxCgOverrideR = crate::BitReader; -impl RamxCgOverrideR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RamxCgOverride { - match self.bits { - false => RamxCgOverride::Disable, - true => RamxCgOverride::Enable, - } - } - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RamxCgOverride::Disable - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RamxCgOverride::Enable - } -} -#[doc = "Field `RAMX_CG_OVERRIDE` writer - RAMX bank clock gating control"] -pub type RamxCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamxCgOverride>; -impl<'a, REG> RamxCgOverrideW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RamxCgOverride::Disable) - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RamxCgOverride::Enable) - } -} -#[doc = "RAMB bank clock gating control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RambCgOverride { - #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] - Disable = 0, - #[doc = "1: Auto clock gating feature is disabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RambCgOverride) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMB_CG_OVERRIDE` reader - RAMB bank clock gating control"] -pub type RambCgOverrideR = crate::BitReader; -impl RambCgOverrideR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RambCgOverride { - match self.bits { - false => RambCgOverride::Disable, - true => RambCgOverride::Enable, - } - } - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RambCgOverride::Disable - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RambCgOverride::Enable - } -} -#[doc = "Field `RAMB_CG_OVERRIDE` writer - RAMB bank clock gating control"] -pub type RambCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RambCgOverride>; -impl<'a, REG> RambCgOverrideW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RambCgOverride::Disable) - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RambCgOverride::Enable) - } -} -#[doc = "RAMC bank clock gating control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RamcCgOverride { - #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"] - Disable = 0, - #[doc = "1: Auto clock gating feature is disabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RamcCgOverride) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMC_CG_OVERRIDE` reader - RAMC bank clock gating control"] -pub type RamcCgOverrideR = crate::BitReader; -impl RamcCgOverrideR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RamcCgOverride { - match self.bits { - false => RamcCgOverride::Disable, - true => RamcCgOverride::Enable, - } - } - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RamcCgOverride::Disable - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RamcCgOverride::Enable - } -} -#[doc = "Field `RAMC_CG_OVERRIDE` writer - RAMC bank clock gating control"] -pub type RamcCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamcCgOverride>; -impl<'a, REG> RamcCgOverrideW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RamcCgOverride::Disable) - } - #[doc = "Auto clock gating feature is disabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RamcCgOverride::Enable) - } -} -impl R { - #[doc = "Bit 0 - RAMA ECC enable"] - #[inline(always)] - pub fn rama_ecc_enable(&self) -> RamaEccEnableR { - RamaEccEnableR::new((self.bits & 1) != 0) - } - #[doc = "Bit 16 - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] - #[inline(always)] - pub fn rama_cg_override(&self) -> RamaCgOverrideR { - RamaCgOverrideR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - RAMX bank clock gating control"] - #[inline(always)] - pub fn ramx_cg_override(&self) -> RamxCgOverrideR { - RamxCgOverrideR::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - RAMB bank clock gating control"] - #[inline(always)] - pub fn ramb_cg_override(&self) -> RambCgOverrideR { - RambCgOverrideR::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - RAMC bank clock gating control"] - #[inline(always)] - pub fn ramc_cg_override(&self) -> RamcCgOverrideR { - RamcCgOverrideR::new(((self.bits >> 19) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - RAMA ECC enable"] - #[inline(always)] - pub fn rama_ecc_enable(&mut self) -> RamaEccEnableW { - RamaEccEnableW::new(self, 0) - } - #[doc = "Bit 16 - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."] - #[inline(always)] - pub fn rama_cg_override(&mut self) -> RamaCgOverrideW { - RamaCgOverrideW::new(self, 16) - } - #[doc = "Bit 17 - RAMX bank clock gating control"] - #[inline(always)] - pub fn ramx_cg_override(&mut self) -> RamxCgOverrideW { - RamxCgOverrideW::new(self, 17) - } - #[doc = "Bit 18 - RAMB bank clock gating control"] - #[inline(always)] - pub fn ramb_cg_override(&mut self) -> RambCgOverrideW { - RambCgOverrideW::new(self, 18) - } - #[doc = "Bit 19 - RAMC bank clock gating control"] - #[inline(always)] - pub fn ramc_cg_override(&mut self) -> RamcCgOverrideW { - RamcCgOverrideW::new(self, 19) - } -} -#[doc = "RAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RamCtrlSpec; -impl crate::RegisterSpec for RamCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ram_ctrl::R`](R) reader structure"] -impl crate::Readable for RamCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ram_ctrl::W`](W) writer structure"] -impl crate::Writable for RamCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RAM_CTRL to value 0x01"] -impl crate::Resettable for RamCtrlSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/syscon/ram_interleave.rs b/mcxa276-pac/src/syscon/ram_interleave.rs deleted file mode 100644 index cf36f757a..000000000 --- a/mcxa276-pac/src/syscon/ram_interleave.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `RAM_INTERLEAVE` reader"] -pub type R = crate::R; -#[doc = "Register `RAM_INTERLEAVE` writer"] -pub type W = crate::W; -#[doc = "Controls RAM access for RAMA1 and RAMA2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Interleave { - #[doc = "0: RAM access is consecutive."] - Normal = 0, - #[doc = "1: RAM access is interleaved. This setting is need for PKC L0 memory access."] - Interleave = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Interleave) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTERLEAVE` reader - Controls RAM access for RAMA1 and RAMA2"] -pub type InterleaveR = crate::BitReader; -impl InterleaveR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Interleave { - match self.bits { - false => Interleave::Normal, - true => Interleave::Interleave, - } - } - #[doc = "RAM access is consecutive."] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == Interleave::Normal - } - #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."] - #[inline(always)] - pub fn is_interleave(&self) -> bool { - *self == Interleave::Interleave - } -} -#[doc = "Field `INTERLEAVE` writer - Controls RAM access for RAMA1 and RAMA2"] -pub type InterleaveW<'a, REG> = crate::BitWriter<'a, REG, Interleave>; -impl<'a, REG> InterleaveW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "RAM access is consecutive."] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(Interleave::Normal) - } - #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."] - #[inline(always)] - pub fn interleave(self) -> &'a mut crate::W { - self.variant(Interleave::Interleave) - } -} -impl R { - #[doc = "Bit 0 - Controls RAM access for RAMA1 and RAMA2"] - #[inline(always)] - pub fn interleave(&self) -> InterleaveR { - InterleaveR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Controls RAM access for RAMA1 and RAMA2"] - #[inline(always)] - pub fn interleave(&mut self) -> InterleaveW { - InterleaveW::new(self, 0) - } -} -#[doc = "Controls RAM Interleave Integration\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_interleave::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_interleave::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RamInterleaveSpec; -impl crate::RegisterSpec for RamInterleaveSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ram_interleave::R`](R) reader structure"] -impl crate::Readable for RamInterleaveSpec {} -#[doc = "`write(|w| ..)` method takes [`ram_interleave::W`](W) writer structure"] -impl crate::Writable for RamInterleaveSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets RAM_INTERLEAVE to value 0"] -impl crate::Resettable for RamInterleaveSpec {} diff --git a/mcxa276-pac/src/syscon/remap.rs b/mcxa276-pac/src/syscon/remap.rs deleted file mode 100644 index fe3fe156f..000000000 --- a/mcxa276-pac/src/syscon/remap.rs +++ /dev/null @@ -1,504 +0,0 @@ -#[doc = "Register `REMAP` reader"] -pub type R = crate::R; -#[doc = "Register `REMAP` writer"] -pub type W = crate::W; -#[doc = "RAMX0 address remap for CPU System bus\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cpu0Sbus { - #[doc = "0: RAMX0: alias space is disabled."] - Cpu0Sbus0 = 0, - #[doc = "1: RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] - Cpu0Sbus1 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cpu0Sbus) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cpu0Sbus { - type Ux = u8; -} -impl crate::IsEnum for Cpu0Sbus {} -#[doc = "Field `CPU0_SBUS` reader - RAMX0 address remap for CPU System bus"] -pub type Cpu0SbusR = crate::FieldReader; -impl Cpu0SbusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cpu0Sbus::Cpu0Sbus0), - 1 => Some(Cpu0Sbus::Cpu0Sbus1), - _ => None, - } - } - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn is_cpu0_sbus_0(&self) -> bool { - *self == Cpu0Sbus::Cpu0Sbus0 - } - #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] - #[inline(always)] - pub fn is_cpu0_sbus_1(&self) -> bool { - *self == Cpu0Sbus::Cpu0Sbus1 - } -} -#[doc = "Field `CPU0_SBUS` writer - RAMX0 address remap for CPU System bus"] -pub type Cpu0SbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Sbus>; -impl<'a, REG> Cpu0SbusW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn cpu0_sbus_0(self) -> &'a mut crate::W { - self.variant(Cpu0Sbus::Cpu0Sbus0) - } - #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] - #[inline(always)] - pub fn cpu0_sbus_1(self) -> &'a mut crate::W { - self.variant(Cpu0Sbus::Cpu0Sbus1) - } -} -#[doc = "RAMX0 address remap for SmartDMA D-BUS\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum SmartDmaD { - #[doc = "0: RAMX0: alias space is disabled."] - SmartDmaD0 = 0, - #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] - SmartDmaD1 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: SmartDmaD) -> Self { - variant as _ - } -} -impl crate::FieldSpec for SmartDmaD { - type Ux = u8; -} -impl crate::IsEnum for SmartDmaD {} -#[doc = "Field `SmartDMA_D` reader - RAMX0 address remap for SmartDMA D-BUS"] -pub type SmartDmaDR = crate::FieldReader; -impl SmartDmaDR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(SmartDmaD::SmartDmaD0), - 1 => Some(SmartDmaD::SmartDmaD1), - _ => None, - } - } - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn is_smart_dma_d_0(&self) -> bool { - *self == SmartDmaD::SmartDmaD0 - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn is_smart_dma_d_1(&self) -> bool { - *self == SmartDmaD::SmartDmaD1 - } -} -#[doc = "Field `SmartDMA_D` writer - RAMX0 address remap for SmartDMA D-BUS"] -pub type SmartDmaDW<'a, REG> = crate::FieldWriter<'a, REG, 2, SmartDmaD>; -impl<'a, REG> SmartDmaDW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn smart_dma_d_0(self) -> &'a mut crate::W { - self.variant(SmartDmaD::SmartDmaD0) - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn smart_dma_d_1(self) -> &'a mut crate::W { - self.variant(SmartDmaD::SmartDmaD1) - } -} -#[doc = "RAMX0 address remap for SmartDMA I-BUS\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum SmartDmaI { - #[doc = "0: RAMX0: alias space is disabled."] - SmartDmaI0 = 0, - #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] - SmartDmaI1 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: SmartDmaI) -> Self { - variant as _ - } -} -impl crate::FieldSpec for SmartDmaI { - type Ux = u8; -} -impl crate::IsEnum for SmartDmaI {} -#[doc = "Field `SmartDMA_I` reader - RAMX0 address remap for SmartDMA I-BUS"] -pub type SmartDmaIR = crate::FieldReader; -impl SmartDmaIR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(SmartDmaI::SmartDmaI0), - 1 => Some(SmartDmaI::SmartDmaI1), - _ => None, - } - } - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn is_smart_dma_i_0(&self) -> bool { - *self == SmartDmaI::SmartDmaI0 - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn is_smart_dma_i_1(&self) -> bool { - *self == SmartDmaI::SmartDmaI1 - } -} -#[doc = "Field `SmartDMA_I` writer - RAMX0 address remap for SmartDMA I-BUS"] -pub type SmartDmaIW<'a, REG> = crate::FieldWriter<'a, REG, 2, SmartDmaI>; -impl<'a, REG> SmartDmaIW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn smart_dma_i_0(self) -> &'a mut crate::W { - self.variant(SmartDmaI::SmartDmaI0) - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn smart_dma_i_1(self) -> &'a mut crate::W { - self.variant(SmartDmaI::SmartDmaI1) - } -} -#[doc = "RAMX0 address remap for DMA0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Dma0 { - #[doc = "0: RAMX0: alias space is disabled."] - Dma0_0 = 0, - #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] - Dma0_1 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Dma0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Dma0 { - type Ux = u8; -} -impl crate::IsEnum for Dma0 {} -#[doc = "Field `DMA0` reader - RAMX0 address remap for DMA0"] -pub type Dma0R = crate::FieldReader; -impl Dma0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Dma0::Dma0_0), - 1 => Some(Dma0::Dma0_1), - _ => None, - } - } - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn is_dma0_0(&self) -> bool { - *self == Dma0::Dma0_0 - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn is_dma0_1(&self) -> bool { - *self == Dma0::Dma0_1 - } -} -#[doc = "Field `DMA0` writer - RAMX0 address remap for DMA0"] -pub type Dma0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Dma0>; -impl<'a, REG> Dma0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn dma0_0(self) -> &'a mut crate::W { - self.variant(Dma0::Dma0_0) - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn dma0_1(self) -> &'a mut crate::W { - self.variant(Dma0::Dma0_1) - } -} -#[doc = "RAMX0 address remap for PKC\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Pkc { - #[doc = "0: RAMX0: alias space is disabled."] - Pkc0 = 0, - #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] - Pkc1 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Pkc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Pkc { - type Ux = u8; -} -impl crate::IsEnum for Pkc {} -#[doc = "Field `PKC` reader - RAMX0 address remap for PKC"] -pub type PkcR = crate::FieldReader; -impl PkcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Pkc::Pkc0), - 1 => Some(Pkc::Pkc1), - _ => None, - } - } - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn is_pkc_0(&self) -> bool { - *self == Pkc::Pkc0 - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn is_pkc_1(&self) -> bool { - *self == Pkc::Pkc1 - } -} -#[doc = "Field `PKC` writer - RAMX0 address remap for PKC"] -pub type PkcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pkc>; -impl<'a, REG> PkcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn pkc_0(self) -> &'a mut crate::W { - self.variant(Pkc::Pkc0) - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn pkc_1(self) -> &'a mut crate::W { - self.variant(Pkc::Pkc1) - } -} -#[doc = "RAMX0 address remap for USB0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Usb0 { - #[doc = "0: RAMX0: alias space is disabled."] - Usb0_0 = 0, - #[doc = "1: RAMX0: same alias space as CPU0_SBUS"] - Usb0_1 = 1, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Usb0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Usb0 { - type Ux = u8; -} -impl crate::IsEnum for Usb0 {} -#[doc = "Field `USB0` reader - RAMX0 address remap for USB0"] -pub type Usb0R = crate::FieldReader; -impl Usb0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Usb0::Usb0_0), - 1 => Some(Usb0::Usb0_1), - _ => None, - } - } - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn is_usb0_0(&self) -> bool { - *self == Usb0::Usb0_0 - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn is_usb0_1(&self) -> bool { - *self == Usb0::Usb0_1 - } -} -#[doc = "Field `USB0` writer - RAMX0 address remap for USB0"] -pub type Usb0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Usb0>; -impl<'a, REG> Usb0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "RAMX0: alias space is disabled."] - #[inline(always)] - pub fn usb0_0(self) -> &'a mut crate::W { - self.variant(Usb0::Usb0_0) - } - #[doc = "RAMX0: same alias space as CPU0_SBUS"] - #[inline(always)] - pub fn usb0_1(self) -> &'a mut crate::W { - self.variant(Usb0::Usb0_1) - } -} -#[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: This register is not locked and can be altered."] - Lock0 = 0, - #[doc = "1: This register is locked and cannot be altered until a system reset."] - Lock1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Lock0, - true => Lock::Lock1, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_lock_0(&self) -> bool { - *self == Lock::Lock0 - } - #[doc = "This register is locked and cannot be altered until a system reset."] - #[inline(always)] - pub fn is_lock_1(&self) -> bool { - *self == Lock::Lock1 - } -} -#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn lock_0(self) -> &'a mut crate::W { - self.variant(Lock::Lock0) - } - #[doc = "This register is locked and cannot be altered until a system reset."] - #[inline(always)] - pub fn lock_1(self) -> &'a mut crate::W { - self.variant(Lock::Lock1) - } -} -impl R { - #[doc = "Bits 2:3 - RAMX0 address remap for CPU System bus"] - #[inline(always)] - pub fn cpu0_sbus(&self) -> Cpu0SbusR { - Cpu0SbusR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - RAMX0 address remap for SmartDMA D-BUS"] - #[inline(always)] - pub fn smart_dma_d(&self) -> SmartDmaDR { - SmartDmaDR::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - RAMX0 address remap for SmartDMA I-BUS"] - #[inline(always)] - pub fn smart_dma_i(&self) -> SmartDmaIR { - SmartDmaIR::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - RAMX0 address remap for DMA0"] - #[inline(always)] - pub fn dma0(&self) -> Dma0R { - Dma0R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 12:13 - RAMX0 address remap for PKC"] - #[inline(always)] - pub fn pkc(&self) -> PkcR { - PkcR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 24:25 - RAMX0 address remap for USB0"] - #[inline(always)] - pub fn usb0(&self) -> Usb0R { - Usb0R::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 2:3 - RAMX0 address remap for CPU System bus"] - #[inline(always)] - pub fn cpu0_sbus(&mut self) -> Cpu0SbusW { - Cpu0SbusW::new(self, 2) - } - #[doc = "Bits 4:5 - RAMX0 address remap for SmartDMA D-BUS"] - #[inline(always)] - pub fn smart_dma_d(&mut self) -> SmartDmaDW { - SmartDmaDW::new(self, 4) - } - #[doc = "Bits 6:7 - RAMX0 address remap for SmartDMA I-BUS"] - #[inline(always)] - pub fn smart_dma_i(&mut self) -> SmartDmaIW { - SmartDmaIW::new(self, 6) - } - #[doc = "Bits 8:9 - RAMX0 address remap for DMA0"] - #[inline(always)] - pub fn dma0(&mut self) -> Dma0W { - Dma0W::new(self, 8) - } - #[doc = "Bits 12:13 - RAMX0 address remap for PKC"] - #[inline(always)] - pub fn pkc(&mut self) -> PkcW { - PkcW::new(self, 12) - } - #[doc = "Bits 24:25 - RAMX0 address remap for USB0"] - #[inline(always)] - pub fn usb0(&mut self) -> Usb0W { - Usb0W::new(self, 24) - } - #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 31) - } -} -#[doc = "AHB Matrix Remap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RemapSpec; -impl crate::RegisterSpec for RemapSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`remap::R`](R) reader structure"] -impl crate::Readable for RemapSpec {} -#[doc = "`write(|w| ..)` method takes [`remap::W`](W) writer structure"] -impl crate::Writable for RemapSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets REMAP to value 0"] -impl crate::Resettable for RemapSpec {} diff --git a/mcxa276-pac/src/syscon/rop_state.rs b/mcxa276-pac/src/syscon/rop_state.rs deleted file mode 100644 index 821c564b7..000000000 --- a/mcxa276-pac/src/syscon/rop_state.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `ROP_STATE` reader"] -pub type R = crate::R; -#[doc = "Field `ROP_STATE` reader - ROP state"] -pub type RopStateR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - ROP state"] - #[inline(always)] - pub fn rop_state(&self) -> RopStateR { - RopStateR::new(self.bits) - } -} -#[doc = "ROP State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rop_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RopStateSpec; -impl crate::RegisterSpec for RopStateSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`rop_state::R`](R) reader structure"] -impl crate::Readable for RopStateSpec {} -#[doc = "`reset()` method sets ROP_STATE to value 0"] -impl crate::Resettable for RopStateSpec {} diff --git a/mcxa276-pac/src/syscon/slowclkdiv.rs b/mcxa276-pac/src/syscon/slowclkdiv.rs deleted file mode 100644 index b8ac6c522..000000000 --- a/mcxa276-pac/src/syscon/slowclkdiv.rs +++ /dev/null @@ -1,197 +0,0 @@ -#[doc = "Register `SLOWCLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `SLOWCLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `DIV` reader - Clock divider value"] -pub type DivR = crate::FieldReader; -#[doc = "Resets the divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Divider is not reset"] - Released = 0, - #[doc = "1: Divider is reset"] - Asserted = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` reader - Resets the divider counter"] -pub type ResetR = crate::BitReader; -impl ResetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reset { - match self.bits { - false => Reset::Released, - true => Reset::Asserted, - } - } - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn is_released(&self) -> bool { - *self == Reset::Released - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn is_asserted(&self) -> bool { - *self == Reset::Asserted - } -} -#[doc = "Field `RESET` writer - Resets the divider counter"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider is not reset"] - #[inline(always)] - pub fn released(self) -> &'a mut crate::W { - self.variant(Reset::Released) - } - #[doc = "Divider is reset"] - #[inline(always)] - pub fn asserted(self) -> &'a mut crate::W { - self.variant(Reset::Asserted) - } -} -#[doc = "Halts the divider counter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Halt { - #[doc = "0: Divider clock is running"] - Run = 0, - #[doc = "1: Divider clock is stopped"] - Halt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Halt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HALT` reader - Halts the divider counter"] -pub type HaltR = crate::BitReader; -impl HaltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Halt { - match self.bits { - false => Halt::Run, - true => Halt::Halt, - } - } - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn is_run(&self) -> bool { - *self == Halt::Run - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn is_halt(&self) -> bool { - *self == Halt::Halt - } -} -#[doc = "Field `HALT` writer - Halts the divider counter"] -pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>; -impl<'a, REG> HaltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Divider clock is running"] - #[inline(always)] - pub fn run(self) -> &'a mut crate::W { - self.variant(Halt::Run) - } - #[doc = "Divider clock is stopped"] - #[inline(always)] - pub fn halt(self) -> &'a mut crate::W { - self.variant(Halt::Halt) - } -} -#[doc = "Divider status flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Unstab { - #[doc = "0: Divider clock is stable"] - Stable = 0, - #[doc = "1: Clock frequency is not stable"] - Ongoing = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Unstab) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UNSTAB` reader - Divider status flag"] -pub type UnstabR = crate::BitReader; -impl UnstabR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Unstab { - match self.bits { - false => Unstab::Stable, - true => Unstab::Ongoing, - } - } - #[doc = "Divider clock is stable"] - #[inline(always)] - pub fn is_stable(&self) -> bool { - *self == Unstab::Stable - } - #[doc = "Clock frequency is not stable"] - #[inline(always)] - pub fn is_ongoing(&self) -> bool { - *self == Unstab::Ongoing - } -} -impl R { - #[doc = "Bits 0:7 - Clock divider value"] - #[inline(always)] - pub fn div(&self) -> DivR { - DivR::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&self) -> ResetR { - ResetR::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&self) -> HaltR { - HaltR::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Divider status flag"] - #[inline(always)] - pub fn unstab(&self) -> UnstabR { - UnstabR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 29 - Resets the divider counter"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 29) - } - #[doc = "Bit 30 - Halts the divider counter"] - #[inline(always)] - pub fn halt(&mut self) -> HaltW { - HaltW::new(self, 30) - } -} -#[doc = "SLOW_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`slowclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slowclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SlowclkdivSpec; -impl crate::RegisterSpec for SlowclkdivSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`slowclkdiv::R`](R) reader structure"] -impl crate::Readable for SlowclkdivSpec {} -#[doc = "`write(|w| ..)` method takes [`slowclkdiv::W`](W) writer structure"] -impl crate::Writable for SlowclkdivSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SLOWCLKDIV to value 0x05"] -impl crate::Resettable for SlowclkdivSpec { - const RESET_VALUE: u32 = 0x05; -} diff --git a/mcxa276-pac/src/syscon/smart_dmaint.rs b/mcxa276-pac/src/syscon/smart_dmaint.rs deleted file mode 100644 index 9fe8450d0..000000000 --- a/mcxa276-pac/src/syscon/smart_dmaint.rs +++ /dev/null @@ -1,1533 +0,0 @@ -#[doc = "Register `SmartDMAINT` reader"] -pub type R = crate::R; -#[doc = "Register `SmartDMAINT` writer"] -pub type W = crate::W; -#[doc = "SmartDMA hijack NVIC IRQ1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int0 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT0` reader - SmartDMA hijack NVIC IRQ1"] -pub type Int0R = crate::BitReader; -impl Int0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int0 { - match self.bits { - false => Int0::Disable, - true => Int0::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int0::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int0::Enable - } -} -#[doc = "Field `INT0` writer - SmartDMA hijack NVIC IRQ1"] -pub type Int0W<'a, REG> = crate::BitWriter<'a, REG, Int0>; -impl<'a, REG> Int0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int0::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int0::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ17\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int1 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT1` reader - SmartDMA hijack NVIC IRQ17"] -pub type Int1R = crate::BitReader; -impl Int1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int1 { - match self.bits { - false => Int1::Disable, - true => Int1::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int1::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int1::Enable - } -} -#[doc = "Field `INT1` writer - SmartDMA hijack NVIC IRQ17"] -pub type Int1W<'a, REG> = crate::BitWriter<'a, REG, Int1>; -impl<'a, REG> Int1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int1::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int1::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ18\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int2 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT2` reader - SmartDMA hijack NVIC IRQ18"] -pub type Int2R = crate::BitReader; -impl Int2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int2 { - match self.bits { - false => Int2::Disable, - true => Int2::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int2::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int2::Enable - } -} -#[doc = "Field `INT2` writer - SmartDMA hijack NVIC IRQ18"] -pub type Int2W<'a, REG> = crate::BitWriter<'a, REG, Int2>; -impl<'a, REG> Int2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int2::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int2::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ29\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int3 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT3` reader - SmartDMA hijack NVIC IRQ29"] -pub type Int3R = crate::BitReader; -impl Int3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int3 { - match self.bits { - false => Int3::Disable, - true => Int3::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int3::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int3::Enable - } -} -#[doc = "Field `INT3` writer - SmartDMA hijack NVIC IRQ29"] -pub type Int3W<'a, REG> = crate::BitWriter<'a, REG, Int3>; -impl<'a, REG> Int3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int3::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int3::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ30\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int4 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT4` reader - SmartDMA hijack NVIC IRQ30"] -pub type Int4R = crate::BitReader; -impl Int4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int4 { - match self.bits { - false => Int4::Disable, - true => Int4::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int4::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int4::Enable - } -} -#[doc = "Field `INT4` writer - SmartDMA hijack NVIC IRQ30"] -pub type Int4W<'a, REG> = crate::BitWriter<'a, REG, Int4>; -impl<'a, REG> Int4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int4::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int4::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ31\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int5 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT5` reader - SmartDMA hijack NVIC IRQ31"] -pub type Int5R = crate::BitReader; -impl Int5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int5 { - match self.bits { - false => Int5::Disable, - true => Int5::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int5::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int5::Enable - } -} -#[doc = "Field `INT5` writer - SmartDMA hijack NVIC IRQ31"] -pub type Int5W<'a, REG> = crate::BitWriter<'a, REG, Int5>; -impl<'a, REG> Int5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int5::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int5::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ32\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int6 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT6` reader - SmartDMA hijack NVIC IRQ32"] -pub type Int6R = crate::BitReader; -impl Int6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int6 { - match self.bits { - false => Int6::Disable, - true => Int6::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int6::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int6::Enable - } -} -#[doc = "Field `INT6` writer - SmartDMA hijack NVIC IRQ32"] -pub type Int6W<'a, REG> = crate::BitWriter<'a, REG, Int6>; -impl<'a, REG> Int6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int6::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int6::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ33\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int7 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT7` reader - SmartDMA hijack NVIC IRQ33"] -pub type Int7R = crate::BitReader; -impl Int7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int7 { - match self.bits { - false => Int7::Disable, - true => Int7::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int7::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int7::Enable - } -} -#[doc = "Field `INT7` writer - SmartDMA hijack NVIC IRQ33"] -pub type Int7W<'a, REG> = crate::BitWriter<'a, REG, Int7>; -impl<'a, REG> Int7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int7::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int7::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ34\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int8 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT8` reader - SmartDMA hijack NVIC IRQ34"] -pub type Int8R = crate::BitReader; -impl Int8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int8 { - match self.bits { - false => Int8::Disable, - true => Int8::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int8::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int8::Enable - } -} -#[doc = "Field `INT8` writer - SmartDMA hijack NVIC IRQ34"] -pub type Int8W<'a, REG> = crate::BitWriter<'a, REG, Int8>; -impl<'a, REG> Int8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int8::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int8::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ35\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int9 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT9` reader - SmartDMA hijack NVIC IRQ35"] -pub type Int9R = crate::BitReader; -impl Int9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int9 { - match self.bits { - false => Int9::Disable, - true => Int9::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int9::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int9::Enable - } -} -#[doc = "Field `INT9` writer - SmartDMA hijack NVIC IRQ35"] -pub type Int9W<'a, REG> = crate::BitWriter<'a, REG, Int9>; -impl<'a, REG> Int9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int9::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int9::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ36\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int10 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT10` reader - SmartDMA hijack NVIC IRQ36"] -pub type Int10R = crate::BitReader; -impl Int10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int10 { - match self.bits { - false => Int10::Disable, - true => Int10::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int10::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int10::Enable - } -} -#[doc = "Field `INT10` writer - SmartDMA hijack NVIC IRQ36"] -pub type Int10W<'a, REG> = crate::BitWriter<'a, REG, Int10>; -impl<'a, REG> Int10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int10::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int10::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ37\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int11 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT11` reader - SmartDMA hijack NVIC IRQ37"] -pub type Int11R = crate::BitReader; -impl Int11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int11 { - match self.bits { - false => Int11::Disable, - true => Int11::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int11::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int11::Enable - } -} -#[doc = "Field `INT11` writer - SmartDMA hijack NVIC IRQ37"] -pub type Int11W<'a, REG> = crate::BitWriter<'a, REG, Int11>; -impl<'a, REG> Int11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int11::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int11::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ38\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int12 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT12` reader - SmartDMA hijack NVIC IRQ38"] -pub type Int12R = crate::BitReader; -impl Int12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int12 { - match self.bits { - false => Int12::Disable, - true => Int12::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int12::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int12::Enable - } -} -#[doc = "Field `INT12` writer - SmartDMA hijack NVIC IRQ38"] -pub type Int12W<'a, REG> = crate::BitWriter<'a, REG, Int12>; -impl<'a, REG> Int12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int12::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int12::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ39\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int13 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT13` reader - SmartDMA hijack NVIC IRQ39"] -pub type Int13R = crate::BitReader; -impl Int13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int13 { - match self.bits { - false => Int13::Disable, - true => Int13::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int13::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int13::Enable - } -} -#[doc = "Field `INT13` writer - SmartDMA hijack NVIC IRQ39"] -pub type Int13W<'a, REG> = crate::BitWriter<'a, REG, Int13>; -impl<'a, REG> Int13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int13::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int13::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ40\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int14 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT14` reader - SmartDMA hijack NVIC IRQ40"] -pub type Int14R = crate::BitReader; -impl Int14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int14 { - match self.bits { - false => Int14::Disable, - true => Int14::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int14::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int14::Enable - } -} -#[doc = "Field `INT14` writer - SmartDMA hijack NVIC IRQ40"] -pub type Int14W<'a, REG> = crate::BitWriter<'a, REG, Int14>; -impl<'a, REG> Int14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int14::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int14::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ41\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int15 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT15` reader - SmartDMA hijack NVIC IRQ41"] -pub type Int15R = crate::BitReader; -impl Int15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int15 { - match self.bits { - false => Int15::Disable, - true => Int15::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int15::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int15::Enable - } -} -#[doc = "Field `INT15` writer - SmartDMA hijack NVIC IRQ41"] -pub type Int15W<'a, REG> = crate::BitWriter<'a, REG, Int15>; -impl<'a, REG> Int15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int15::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int15::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ42\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int16 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT16` reader - SmartDMA hijack NVIC IRQ42"] -pub type Int16R = crate::BitReader; -impl Int16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int16 { - match self.bits { - false => Int16::Disable, - true => Int16::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int16::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int16::Enable - } -} -#[doc = "Field `INT16` writer - SmartDMA hijack NVIC IRQ42"] -pub type Int16W<'a, REG> = crate::BitWriter<'a, REG, Int16>; -impl<'a, REG> Int16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int16::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int16::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ45\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int17 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT17` reader - SmartDMA hijack NVIC IRQ45"] -pub type Int17R = crate::BitReader; -impl Int17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int17 { - match self.bits { - false => Int17::Disable, - true => Int17::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int17::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int17::Enable - } -} -#[doc = "Field `INT17` writer - SmartDMA hijack NVIC IRQ45"] -pub type Int17W<'a, REG> = crate::BitWriter<'a, REG, Int17>; -impl<'a, REG> Int17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int17::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int17::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ47\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int18 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT18` reader - SmartDMA hijack NVIC IRQ47"] -pub type Int18R = crate::BitReader; -impl Int18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int18 { - match self.bits { - false => Int18::Disable, - true => Int18::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int18::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int18::Enable - } -} -#[doc = "Field `INT18` writer - SmartDMA hijack NVIC IRQ47"] -pub type Int18W<'a, REG> = crate::BitWriter<'a, REG, Int18>; -impl<'a, REG> Int18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int18::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int18::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ50\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int19 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT19` reader - SmartDMA hijack NVIC IRQ50"] -pub type Int19R = crate::BitReader; -impl Int19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int19 { - match self.bits { - false => Int19::Disable, - true => Int19::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int19::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int19::Enable - } -} -#[doc = "Field `INT19` writer - SmartDMA hijack NVIC IRQ50"] -pub type Int19W<'a, REG> = crate::BitWriter<'a, REG, Int19>; -impl<'a, REG> Int19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int19::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int19::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ51\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int20 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT20` reader - SmartDMA hijack NVIC IRQ51"] -pub type Int20R = crate::BitReader; -impl Int20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int20 { - match self.bits { - false => Int20::Disable, - true => Int20::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int20::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int20::Enable - } -} -#[doc = "Field `INT20` writer - SmartDMA hijack NVIC IRQ51"] -pub type Int20W<'a, REG> = crate::BitWriter<'a, REG, Int20>; -impl<'a, REG> Int20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int20::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int20::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ66\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int21 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT21` reader - SmartDMA hijack NVIC IRQ66"] -pub type Int21R = crate::BitReader; -impl Int21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int21 { - match self.bits { - false => Int21::Disable, - true => Int21::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int21::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int21::Enable - } -} -#[doc = "Field `INT21` writer - SmartDMA hijack NVIC IRQ66"] -pub type Int21W<'a, REG> = crate::BitWriter<'a, REG, Int21>; -impl<'a, REG> Int21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int21::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int21::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ67\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int22 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT22` reader - SmartDMA hijack NVIC IRQ67"] -pub type Int22R = crate::BitReader; -impl Int22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int22 { - match self.bits { - false => Int22::Disable, - true => Int22::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int22::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int22::Enable - } -} -#[doc = "Field `INT22` writer - SmartDMA hijack NVIC IRQ67"] -pub type Int22W<'a, REG> = crate::BitWriter<'a, REG, Int22>; -impl<'a, REG> Int22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int22::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int22::Enable) - } -} -#[doc = "SmartDMA hijack NVIC IRQ77\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Int23 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Int23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INT23` reader - SmartDMA hijack NVIC IRQ77"] -pub type Int23R = crate::BitReader; -impl Int23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Int23 { - match self.bits { - false => Int23::Disable, - true => Int23::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Int23::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Int23::Enable - } -} -#[doc = "Field `INT23` writer - SmartDMA hijack NVIC IRQ77"] -pub type Int23W<'a, REG> = crate::BitWriter<'a, REG, Int23>; -impl<'a, REG> Int23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Int23::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Int23::Enable) - } -} -impl R { - #[doc = "Bit 0 - SmartDMA hijack NVIC IRQ1"] - #[inline(always)] - pub fn int0(&self) -> Int0R { - Int0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SmartDMA hijack NVIC IRQ17"] - #[inline(always)] - pub fn int1(&self) -> Int1R { - Int1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - SmartDMA hijack NVIC IRQ18"] - #[inline(always)] - pub fn int2(&self) -> Int2R { - Int2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - SmartDMA hijack NVIC IRQ29"] - #[inline(always)] - pub fn int3(&self) -> Int3R { - Int3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - SmartDMA hijack NVIC IRQ30"] - #[inline(always)] - pub fn int4(&self) -> Int4R { - Int4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - SmartDMA hijack NVIC IRQ31"] - #[inline(always)] - pub fn int5(&self) -> Int5R { - Int5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - SmartDMA hijack NVIC IRQ32"] - #[inline(always)] - pub fn int6(&self) -> Int6R { - Int6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - SmartDMA hijack NVIC IRQ33"] - #[inline(always)] - pub fn int7(&self) -> Int7R { - Int7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - SmartDMA hijack NVIC IRQ34"] - #[inline(always)] - pub fn int8(&self) -> Int8R { - Int8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SmartDMA hijack NVIC IRQ35"] - #[inline(always)] - pub fn int9(&self) -> Int9R { - Int9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - SmartDMA hijack NVIC IRQ36"] - #[inline(always)] - pub fn int10(&self) -> Int10R { - Int10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - SmartDMA hijack NVIC IRQ37"] - #[inline(always)] - pub fn int11(&self) -> Int11R { - Int11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - SmartDMA hijack NVIC IRQ38"] - #[inline(always)] - pub fn int12(&self) -> Int12R { - Int12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - SmartDMA hijack NVIC IRQ39"] - #[inline(always)] - pub fn int13(&self) -> Int13R { - Int13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - SmartDMA hijack NVIC IRQ40"] - #[inline(always)] - pub fn int14(&self) -> Int14R { - Int14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - SmartDMA hijack NVIC IRQ41"] - #[inline(always)] - pub fn int15(&self) -> Int15R { - Int15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - SmartDMA hijack NVIC IRQ42"] - #[inline(always)] - pub fn int16(&self) -> Int16R { - Int16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - SmartDMA hijack NVIC IRQ45"] - #[inline(always)] - pub fn int17(&self) -> Int17R { - Int17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - SmartDMA hijack NVIC IRQ47"] - #[inline(always)] - pub fn int18(&self) -> Int18R { - Int18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - SmartDMA hijack NVIC IRQ50"] - #[inline(always)] - pub fn int19(&self) -> Int19R { - Int19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - SmartDMA hijack NVIC IRQ51"] - #[inline(always)] - pub fn int20(&self) -> Int20R { - Int20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - SmartDMA hijack NVIC IRQ66"] - #[inline(always)] - pub fn int21(&self) -> Int21R { - Int21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - SmartDMA hijack NVIC IRQ67"] - #[inline(always)] - pub fn int22(&self) -> Int22R { - Int22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - SmartDMA hijack NVIC IRQ77"] - #[inline(always)] - pub fn int23(&self) -> Int23R { - Int23R::new(((self.bits >> 23) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - SmartDMA hijack NVIC IRQ1"] - #[inline(always)] - pub fn int0(&mut self) -> Int0W { - Int0W::new(self, 0) - } - #[doc = "Bit 1 - SmartDMA hijack NVIC IRQ17"] - #[inline(always)] - pub fn int1(&mut self) -> Int1W { - Int1W::new(self, 1) - } - #[doc = "Bit 2 - SmartDMA hijack NVIC IRQ18"] - #[inline(always)] - pub fn int2(&mut self) -> Int2W { - Int2W::new(self, 2) - } - #[doc = "Bit 3 - SmartDMA hijack NVIC IRQ29"] - #[inline(always)] - pub fn int3(&mut self) -> Int3W { - Int3W::new(self, 3) - } - #[doc = "Bit 4 - SmartDMA hijack NVIC IRQ30"] - #[inline(always)] - pub fn int4(&mut self) -> Int4W { - Int4W::new(self, 4) - } - #[doc = "Bit 5 - SmartDMA hijack NVIC IRQ31"] - #[inline(always)] - pub fn int5(&mut self) -> Int5W { - Int5W::new(self, 5) - } - #[doc = "Bit 6 - SmartDMA hijack NVIC IRQ32"] - #[inline(always)] - pub fn int6(&mut self) -> Int6W { - Int6W::new(self, 6) - } - #[doc = "Bit 7 - SmartDMA hijack NVIC IRQ33"] - #[inline(always)] - pub fn int7(&mut self) -> Int7W { - Int7W::new(self, 7) - } - #[doc = "Bit 8 - SmartDMA hijack NVIC IRQ34"] - #[inline(always)] - pub fn int8(&mut self) -> Int8W { - Int8W::new(self, 8) - } - #[doc = "Bit 9 - SmartDMA hijack NVIC IRQ35"] - #[inline(always)] - pub fn int9(&mut self) -> Int9W { - Int9W::new(self, 9) - } - #[doc = "Bit 10 - SmartDMA hijack NVIC IRQ36"] - #[inline(always)] - pub fn int10(&mut self) -> Int10W { - Int10W::new(self, 10) - } - #[doc = "Bit 11 - SmartDMA hijack NVIC IRQ37"] - #[inline(always)] - pub fn int11(&mut self) -> Int11W { - Int11W::new(self, 11) - } - #[doc = "Bit 12 - SmartDMA hijack NVIC IRQ38"] - #[inline(always)] - pub fn int12(&mut self) -> Int12W { - Int12W::new(self, 12) - } - #[doc = "Bit 13 - SmartDMA hijack NVIC IRQ39"] - #[inline(always)] - pub fn int13(&mut self) -> Int13W { - Int13W::new(self, 13) - } - #[doc = "Bit 14 - SmartDMA hijack NVIC IRQ40"] - #[inline(always)] - pub fn int14(&mut self) -> Int14W { - Int14W::new(self, 14) - } - #[doc = "Bit 15 - SmartDMA hijack NVIC IRQ41"] - #[inline(always)] - pub fn int15(&mut self) -> Int15W { - Int15W::new(self, 15) - } - #[doc = "Bit 16 - SmartDMA hijack NVIC IRQ42"] - #[inline(always)] - pub fn int16(&mut self) -> Int16W { - Int16W::new(self, 16) - } - #[doc = "Bit 17 - SmartDMA hijack NVIC IRQ45"] - #[inline(always)] - pub fn int17(&mut self) -> Int17W { - Int17W::new(self, 17) - } - #[doc = "Bit 18 - SmartDMA hijack NVIC IRQ47"] - #[inline(always)] - pub fn int18(&mut self) -> Int18W { - Int18W::new(self, 18) - } - #[doc = "Bit 19 - SmartDMA hijack NVIC IRQ50"] - #[inline(always)] - pub fn int19(&mut self) -> Int19W { - Int19W::new(self, 19) - } - #[doc = "Bit 20 - SmartDMA hijack NVIC IRQ51"] - #[inline(always)] - pub fn int20(&mut self) -> Int20W { - Int20W::new(self, 20) - } - #[doc = "Bit 21 - SmartDMA hijack NVIC IRQ66"] - #[inline(always)] - pub fn int21(&mut self) -> Int21W { - Int21W::new(self, 21) - } - #[doc = "Bit 22 - SmartDMA hijack NVIC IRQ67"] - #[inline(always)] - pub fn int22(&mut self) -> Int22W { - Int22W::new(self, 22) - } - #[doc = "Bit 23 - SmartDMA hijack NVIC IRQ77"] - #[inline(always)] - pub fn int23(&mut self) -> Int23W { - Int23W::new(self, 23) - } -} -#[doc = "SmartDMA Interrupt Hijack\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dmaint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dmaint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SmartDmaintSpec; -impl crate::RegisterSpec for SmartDmaintSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`smart_dmaint::R`](R) reader structure"] -impl crate::Readable for SmartDmaintSpec {} -#[doc = "`write(|w| ..)` method takes [`smart_dmaint::W`](W) writer structure"] -impl crate::Writable for SmartDmaintSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SmartDMAINT to value 0"] -impl crate::Resettable for SmartDmaintSpec {} diff --git a/mcxa276-pac/src/syscon/sram_xen.rs b/mcxa276-pac/src/syscon/sram_xen.rs deleted file mode 100644 index 000520c10..000000000 --- a/mcxa276-pac/src/syscon/sram_xen.rs +++ /dev/null @@ -1,462 +0,0 @@ -#[doc = "Register `SRAM_XEN` reader"] -pub type R = crate::R; -#[doc = "Register `SRAM_XEN` writer"] -pub type W = crate::W; -#[doc = "RAMX0 Execute permission control.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ramx0Xen { - #[doc = "0: Execute permission is disabled, R/W are enabled."] - Disable = 0, - #[doc = "1: Execute permission is enabled, R/W/X are enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ramx0Xen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMX0_XEN` reader - RAMX0 Execute permission control."] -pub type Ramx0XenR = crate::BitReader; -impl Ramx0XenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ramx0Xen { - match self.bits { - false => Ramx0Xen::Disable, - true => Ramx0Xen::Enable, - } - } - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ramx0Xen::Disable - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ramx0Xen::Enable - } -} -#[doc = "Field `RAMX0_XEN` writer - RAMX0 Execute permission control."] -pub type Ramx0XenW<'a, REG> = crate::BitWriter<'a, REG, Ramx0Xen>; -impl<'a, REG> Ramx0XenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ramx0Xen::Disable) - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ramx0Xen::Enable) - } -} -#[doc = "RAMX1 Execute permission control.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ramx1Xen { - #[doc = "0: Execute permission is disabled, R/W are enabled."] - Disable = 0, - #[doc = "1: Execute permission is enabled, R/W/X are enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ramx1Xen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMX1_XEN` reader - RAMX1 Execute permission control."] -pub type Ramx1XenR = crate::BitReader; -impl Ramx1XenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ramx1Xen { - match self.bits { - false => Ramx1Xen::Disable, - true => Ramx1Xen::Enable, - } - } - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ramx1Xen::Disable - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ramx1Xen::Enable - } -} -#[doc = "Field `RAMX1_XEN` writer - RAMX1 Execute permission control."] -pub type Ramx1XenW<'a, REG> = crate::BitWriter<'a, REG, Ramx1Xen>; -impl<'a, REG> Ramx1XenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ramx1Xen::Disable) - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ramx1Xen::Enable) - } -} -#[doc = "RAMA0 Execute permission control.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rama0Xen { - #[doc = "0: Execute permission is disabled, R/W are enabled."] - Disable = 0, - #[doc = "1: Execute permission is enabled, R/W/X are enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rama0Xen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMA0_XEN` reader - RAMA0 Execute permission control."] -pub type Rama0XenR = crate::BitReader; -impl Rama0XenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rama0Xen { - match self.bits { - false => Rama0Xen::Disable, - true => Rama0Xen::Enable, - } - } - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Rama0Xen::Disable - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Rama0Xen::Enable - } -} -#[doc = "Field `RAMA0_XEN` writer - RAMA0 Execute permission control."] -pub type Rama0XenW<'a, REG> = crate::BitWriter<'a, REG, Rama0Xen>; -impl<'a, REG> Rama0XenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Rama0Xen::Disable) - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Rama0Xen::Enable) - } -} -#[doc = "RAMAx (excepts RAMA0) Execute permission control.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rama1Xen { - #[doc = "0: Execute permission is disabled, R/W are enabled."] - Disable = 0, - #[doc = "1: Execute permission is enabled, R/W/X are enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rama1Xen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMA1_XEN` reader - RAMAx (excepts RAMA0) Execute permission control."] -pub type Rama1XenR = crate::BitReader; -impl Rama1XenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rama1Xen { - match self.bits { - false => Rama1Xen::Disable, - true => Rama1Xen::Enable, - } - } - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Rama1Xen::Disable - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Rama1Xen::Enable - } -} -#[doc = "Field `RAMA1_XEN` writer - RAMAx (excepts RAMA0) Execute permission control."] -pub type Rama1XenW<'a, REG> = crate::BitWriter<'a, REG, Rama1Xen>; -impl<'a, REG> Rama1XenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Rama1Xen::Disable) - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Rama1Xen::Enable) - } -} -#[doc = "RAMBx Execute permission control.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RambXen { - #[doc = "0: Execute permission is disabled, R/W are enabled."] - Disable = 0, - #[doc = "1: Execute permission is enabled, R/W/X are enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RambXen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMB_XEN` reader - RAMBx Execute permission control."] -pub type RambXenR = crate::BitReader; -impl RambXenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RambXen { - match self.bits { - false => RambXen::Disable, - true => RambXen::Enable, - } - } - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RambXen::Disable - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RambXen::Enable - } -} -#[doc = "Field `RAMB_XEN` writer - RAMBx Execute permission control."] -pub type RambXenW<'a, REG> = crate::BitWriter<'a, REG, RambXen>; -impl<'a, REG> RambXenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RambXen::Disable) - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RambXen::Enable) - } -} -#[doc = "RAMCx Execute permission control.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RamcXen { - #[doc = "0: Execute permission is disabled, R/W are enabled."] - Disable = 0, - #[doc = "1: Execute permission is enabled, R/W/X are enabled."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RamcXen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RAMC_XEN` reader - RAMCx Execute permission control."] -pub type RamcXenR = crate::BitReader; -impl RamcXenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RamcXen { - match self.bits { - false => RamcXen::Disable, - true => RamcXen::Enable, - } - } - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RamcXen::Disable - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RamcXen::Enable - } -} -#[doc = "Field `RAMC_XEN` writer - RAMCx Execute permission control."] -pub type RamcXenW<'a, REG> = crate::BitWriter<'a, REG, RamcXen>; -impl<'a, REG> RamcXenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Execute permission is disabled, R/W are enabled."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RamcXen::Disable) - } - #[doc = "Execute permission is enabled, R/W/X are enabled."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RamcXen::Enable) - } -} -#[doc = "This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: This register is not locked and can be altered."] - Lock0 = 0, - #[doc = "1: This register is locked and cannot be altered."] - Lock1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Lock0, - true => Lock::Lock1, - } - } - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn is_lock_0(&self) -> bool { - *self == Lock::Lock0 - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn is_lock_1(&self) -> bool { - *self == Lock::Lock1 - } -} -#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "This register is not locked and can be altered."] - #[inline(always)] - pub fn lock_0(self) -> &'a mut crate::W { - self.variant(Lock::Lock0) - } - #[doc = "This register is locked and cannot be altered."] - #[inline(always)] - pub fn lock_1(self) -> &'a mut crate::W { - self.variant(Lock::Lock1) - } -} -impl R { - #[doc = "Bit 0 - RAMX0 Execute permission control."] - #[inline(always)] - pub fn ramx0_xen(&self) -> Ramx0XenR { - Ramx0XenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - RAMX1 Execute permission control."] - #[inline(always)] - pub fn ramx1_xen(&self) -> Ramx1XenR { - Ramx1XenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - RAMA0 Execute permission control."] - #[inline(always)] - pub fn rama0_xen(&self) -> Rama0XenR { - Rama0XenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - RAMAx (excepts RAMA0) Execute permission control."] - #[inline(always)] - pub fn rama1_xen(&self) -> Rama1XenR { - Rama1XenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - RAMBx Execute permission control."] - #[inline(always)] - pub fn ramb_xen(&self) -> RambXenR { - RambXenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - RAMCx Execute permission control."] - #[inline(always)] - pub fn ramc_xen(&self) -> RamcXenR { - RamcXenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - RAMX0 Execute permission control."] - #[inline(always)] - pub fn ramx0_xen(&mut self) -> Ramx0XenW { - Ramx0XenW::new(self, 0) - } - #[doc = "Bit 1 - RAMX1 Execute permission control."] - #[inline(always)] - pub fn ramx1_xen(&mut self) -> Ramx1XenW { - Ramx1XenW::new(self, 1) - } - #[doc = "Bit 2 - RAMA0 Execute permission control."] - #[inline(always)] - pub fn rama0_xen(&mut self) -> Rama0XenW { - Rama0XenW::new(self, 2) - } - #[doc = "Bit 3 - RAMAx (excepts RAMA0) Execute permission control."] - #[inline(always)] - pub fn rama1_xen(&mut self) -> Rama1XenW { - Rama1XenW::new(self, 3) - } - #[doc = "Bit 4 - RAMBx Execute permission control."] - #[inline(always)] - pub fn ramb_xen(&mut self) -> RambXenW { - RambXenW::new(self, 4) - } - #[doc = "Bit 5 - RAMCx Execute permission control."] - #[inline(always)] - pub fn ramc_xen(&mut self) -> RamcXenW { - RamcXenW::new(self, 5) - } - #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 31) - } -} -#[doc = "RAM XEN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SramXenSpec; -impl crate::RegisterSpec for SramXenSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sram_xen::R`](R) reader structure"] -impl crate::Readable for SramXenSpec {} -#[doc = "`write(|w| ..)` method takes [`sram_xen::W`](W) writer structure"] -impl crate::Writable for SramXenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SRAM_XEN to value 0"] -impl crate::Resettable for SramXenSpec {} diff --git a/mcxa276-pac/src/syscon/sram_xen_dp.rs b/mcxa276-pac/src/syscon/sram_xen_dp.rs deleted file mode 100644 index 53a2ff879..000000000 --- a/mcxa276-pac/src/syscon/sram_xen_dp.rs +++ /dev/null @@ -1,105 +0,0 @@ -#[doc = "Register `SRAM_XEN_DP` reader"] -pub type R = crate::R; -#[doc = "Register `SRAM_XEN_DP` writer"] -pub type W = crate::W; -#[doc = "Field `RAMX0_XEN` reader - Refer to SRAM_XEN for more details."] -pub type Ramx0XenR = crate::BitReader; -#[doc = "Field `RAMX0_XEN` writer - Refer to SRAM_XEN for more details."] -pub type Ramx0XenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RAMX1_XEN` reader - Refer to SRAM_XEN for more details."] -pub type Ramx1XenR = crate::BitReader; -#[doc = "Field `RAMX1_XEN` writer - Refer to SRAM_XEN for more details."] -pub type Ramx1XenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RAMA0_XEN` reader - Refer to SRAM_XEN for more details."] -pub type Rama0XenR = crate::BitReader; -#[doc = "Field `RAMA0_XEN` writer - Refer to SRAM_XEN for more details."] -pub type Rama0XenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RAMA1_XEN` reader - Refer to SRAM_XEN for more details."] -pub type Rama1XenR = crate::BitReader; -#[doc = "Field `RAMA1_XEN` writer - Refer to SRAM_XEN for more details."] -pub type Rama1XenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RAMB_XEN` reader - Refer to SRAM_XEN for more details."] -pub type RambXenR = crate::BitReader; -#[doc = "Field `RAMB_XEN` writer - Refer to SRAM_XEN for more details."] -pub type RambXenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RAMC_XEN` reader - Refer to SRAM_XEN for more details."] -pub type RamcXenR = crate::BitReader; -#[doc = "Field `RAMC_XEN` writer - Refer to SRAM_XEN for more details."] -pub type RamcXenW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramx0_xen(&self) -> Ramx0XenR { - Ramx0XenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramx1_xen(&self) -> Ramx1XenR { - Ramx1XenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn rama0_xen(&self) -> Rama0XenR { - Rama0XenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn rama1_xen(&self) -> Rama1XenR { - Rama1XenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramb_xen(&self) -> RambXenR { - RambXenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramc_xen(&self) -> RamcXenR { - RamcXenR::new(((self.bits >> 5) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramx0_xen(&mut self) -> Ramx0XenW { - Ramx0XenW::new(self, 0) - } - #[doc = "Bit 1 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramx1_xen(&mut self) -> Ramx1XenW { - Ramx1XenW::new(self, 1) - } - #[doc = "Bit 2 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn rama0_xen(&mut self) -> Rama0XenW { - Rama0XenW::new(self, 2) - } - #[doc = "Bit 3 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn rama1_xen(&mut self) -> Rama1XenW { - Rama1XenW::new(self, 3) - } - #[doc = "Bit 4 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramb_xen(&mut self) -> RambXenW { - RambXenW::new(self, 4) - } - #[doc = "Bit 5 - Refer to SRAM_XEN for more details."] - #[inline(always)] - pub fn ramc_xen(&mut self) -> RamcXenW { - RamcXenW::new(self, 5) - } -} -#[doc = "RAM XEN Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen_dp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen_dp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SramXenDpSpec; -impl crate::RegisterSpec for SramXenDpSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sram_xen_dp::R`](R) reader structure"] -impl crate::Readable for SramXenDpSpec {} -#[doc = "`write(|w| ..)` method takes [`sram_xen_dp::W`](W) writer structure"] -impl crate::Writable for SramXenDpSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SRAM_XEN_DP to value 0"] -impl crate::Resettable for SramXenDpSpec {} diff --git a/mcxa276-pac/src/syscon/swd_access_cpu0.rs b/mcxa276-pac/src/syscon/swd_access_cpu0.rs deleted file mode 100644 index 0309aedc3..000000000 --- a/mcxa276-pac/src/syscon/swd_access_cpu0.rs +++ /dev/null @@ -1,91 +0,0 @@ -#[doc = "Register `SWD_ACCESS_CPU0` reader"] -pub type R = crate::R; -#[doc = "Register `SWD_ACCESS_CPU0` writer"] -pub type W = crate::W; -#[doc = "CPU0 SWD-AP: 0x12345678\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u32)] -pub enum SecCode { - #[doc = "0: CPU0 DAP is not allowed. Reading back register is read as 0x5."] - Disable = 0, - #[doc = "305419896: Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."] - Enable = 305419896, -} -impl From for u32 { - #[inline(always)] - fn from(variant: SecCode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for SecCode { - type Ux = u32; -} -impl crate::IsEnum for SecCode {} -#[doc = "Field `SEC_CODE` reader - CPU0 SWD-AP: 0x12345678"] -pub type SecCodeR = crate::FieldReader; -impl SecCodeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(SecCode::Disable), - 305419896 => Some(SecCode::Enable), - _ => None, - } - } - #[doc = "CPU0 DAP is not allowed. Reading back register is read as 0x5."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == SecCode::Disable - } - #[doc = "Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == SecCode::Enable - } -} -#[doc = "Field `SEC_CODE` writer - CPU0 SWD-AP: 0x12345678"] -pub type SecCodeW<'a, REG> = crate::FieldWriter<'a, REG, 32, SecCode>; -impl<'a, REG> SecCodeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "CPU0 DAP is not allowed. Reading back register is read as 0x5."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(SecCode::Disable) - } - #[doc = "Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(SecCode::Enable) - } -} -impl R { - #[doc = "Bits 0:31 - CPU0 SWD-AP: 0x12345678"] - #[inline(always)] - pub fn sec_code(&self) -> SecCodeR { - SecCodeR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - CPU0 SWD-AP: 0x12345678"] - #[inline(always)] - pub fn sec_code(&mut self) -> SecCodeW { - SecCodeW::new(self, 0) - } -} -#[doc = "CPU0 Software Debug Access\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_access_cpu0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_access_cpu0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SwdAccessCpu0Spec; -impl crate::RegisterSpec for SwdAccessCpu0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`swd_access_cpu0::R`](R) reader structure"] -impl crate::Readable for SwdAccessCpu0Spec {} -#[doc = "`write(|w| ..)` method takes [`swd_access_cpu0::W`](W) writer structure"] -impl crate::Writable for SwdAccessCpu0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SWD_ACCESS_CPU0 to value 0"] -impl crate::Resettable for SwdAccessCpu0Spec {} diff --git a/mcxa276-pac/src/tdet0.rs b/mcxa276-pac/src/tdet0.rs deleted file mode 100644 index 3715b0033..000000000 --- a/mcxa276-pac/src/tdet0.rs +++ /dev/null @@ -1,103 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - _reserved0: [u8; 0x10], - cr: Cr, - sr: Sr, - lr: Lr, - ier: Ier, - tsr: Tsr, - ter: Ter, - _reserved6: [u8; 0x04], - ppr: Ppr, - _reserved7: [u8; 0x10], - pgfr: [Pgfr; 6], -} -impl RegisterBlock { - #[doc = "0x10 - Control"] - #[inline(always)] - pub const fn cr(&self) -> &Cr { - &self.cr - } - #[doc = "0x14 - Status"] - #[inline(always)] - pub const fn sr(&self) -> &Sr { - &self.sr - } - #[doc = "0x18 - Lock"] - #[inline(always)] - pub const fn lr(&self) -> &Lr { - &self.lr - } - #[doc = "0x1c - Interrupt Enable"] - #[inline(always)] - pub const fn ier(&self) -> &Ier { - &self.ier - } - #[doc = "0x20 - Tamper Seconds"] - #[inline(always)] - pub const fn tsr(&self) -> &Tsr { - &self.tsr - } - #[doc = "0x24 - Tamper Enable"] - #[inline(always)] - pub const fn ter(&self) -> &Ter { - &self.ter - } - #[doc = "0x2c - Pin Polarity"] - #[inline(always)] - pub const fn ppr(&self) -> &Ppr { - &self.ppr - } - #[doc = "0x40..0x58 - Pin Glitch Filter"] - #[inline(always)] - pub const fn pgfr(&self, n: usize) -> &Pgfr { - &self.pgfr[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x40..0x58 - Pin Glitch Filter"] - #[inline(always)] - pub fn pgfr_iter(&self) -> impl Iterator { - self.pgfr.iter() - } -} -#[doc = "CR (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"] -#[doc(alias = "CR")] -pub type Cr = crate::Reg; -#[doc = "Control"] -pub mod cr; -#[doc = "SR (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] -#[doc(alias = "SR")] -pub type Sr = crate::Reg; -#[doc = "Status"] -pub mod sr; -#[doc = "LR (rw) register accessor: Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lr`] module"] -#[doc(alias = "LR")] -pub type Lr = crate::Reg; -#[doc = "Lock"] -pub mod lr; -#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] -#[doc(alias = "IER")] -pub type Ier = crate::Reg; -#[doc = "Interrupt Enable"] -pub mod ier; -#[doc = "TSR (rw) register accessor: Tamper Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsr`] module"] -#[doc(alias = "TSR")] -pub type Tsr = crate::Reg; -#[doc = "Tamper Seconds"] -pub mod tsr; -#[doc = "TER (rw) register accessor: Tamper Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ter`] module"] -#[doc(alias = "TER")] -pub type Ter = crate::Reg; -#[doc = "Tamper Enable"] -pub mod ter; -#[doc = "PPR (rw) register accessor: Pin Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`ppr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ppr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppr`] module"] -#[doc(alias = "PPR")] -pub type Ppr = crate::Reg; -#[doc = "Pin Polarity"] -pub mod ppr; -#[doc = "PGFR (rw) register accessor: Pin Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`pgfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pgfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgfr`] module"] -#[doc(alias = "PGFR")] -pub type Pgfr = crate::Reg; -#[doc = "Pin Glitch Filter"] -pub mod pgfr; diff --git a/mcxa276-pac/src/tdet0/cr.rs b/mcxa276-pac/src/tdet0/cr.rs deleted file mode 100644 index b5efa57d5..000000000 --- a/mcxa276-pac/src/tdet0/cr.rs +++ /dev/null @@ -1,350 +0,0 @@ -#[doc = "Register `CR` reader"] -pub type R = crate::R; -#[doc = "Register `CR` writer"] -pub type W = crate::W; -#[doc = "Software Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Swr { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Perform a software reset"] - SwReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Swr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SWR` reader - Software Reset"] -pub type SwrR = crate::BitReader; -impl SwrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Swr { - match self.bits { - false => Swr::NoEffect, - true => Swr::SwReset, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Swr::NoEffect - } - #[doc = "Perform a software reset"] - #[inline(always)] - pub fn is_sw_reset(&self) -> bool { - *self == Swr::SwReset - } -} -#[doc = "Field `SWR` writer - Software Reset"] -pub type SwrW<'a, REG> = crate::BitWriter<'a, REG, Swr>; -impl<'a, REG> SwrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Swr::NoEffect) - } - #[doc = "Perform a software reset"] - #[inline(always)] - pub fn sw_reset(self) -> &'a mut crate::W { - self.variant(Swr::SwReset) - } -} -#[doc = "Digital Tamper Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Den { - #[doc = "0: Disables TDET clock and prescaler"] - Disable = 0, - #[doc = "1: Enables TDET clock and prescaler"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Den) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DEN` reader - Digital Tamper Enable"] -pub type DenR = crate::BitReader; -impl DenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Den { - match self.bits { - false => Den::Disable, - true => Den::Enable, - } - } - #[doc = "Disables TDET clock and prescaler"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Den::Disable - } - #[doc = "Enables TDET clock and prescaler"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Den::Enable - } -} -#[doc = "Field `DEN` writer - Digital Tamper Enable"] -pub type DenW<'a, REG> = crate::BitWriter<'a, REG, Den>; -impl<'a, REG> DenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables TDET clock and prescaler"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Den::Disable) - } - #[doc = "Enables TDET clock and prescaler"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Den::Enable) - } -} -#[doc = "Tamper Force System Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tfsr { - #[doc = "0: Do not force chip reset"] - NoReset = 0, - #[doc = "1: Force chip reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tfsr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TFSR` reader - Tamper Force System Reset"] -pub type TfsrR = crate::BitReader; -impl TfsrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tfsr { - match self.bits { - false => Tfsr::NoReset, - true => Tfsr::Reset, - } - } - #[doc = "Do not force chip reset"] - #[inline(always)] - pub fn is_no_reset(&self) -> bool { - *self == Tfsr::NoReset - } - #[doc = "Force chip reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Tfsr::Reset - } -} -#[doc = "Field `TFSR` writer - Tamper Force System Reset"] -pub type TfsrW<'a, REG> = crate::BitWriter<'a, REG, Tfsr>; -impl<'a, REG> TfsrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Do not force chip reset"] - #[inline(always)] - pub fn no_reset(self) -> &'a mut crate::W { - self.variant(Tfsr::NoReset) - } - #[doc = "Force chip reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Tfsr::Reset) - } -} -#[doc = "Update Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Um { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Allows the clearing of interrupts"] - ClearInts = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Um) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UM` reader - Update Mode"] -pub type UmR = crate::BitReader; -impl UmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Um { - match self.bits { - false => Um::NoEffect, - true => Um::ClearInts, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Um::NoEffect - } - #[doc = "Allows the clearing of interrupts"] - #[inline(always)] - pub fn is_clear_ints(&self) -> bool { - *self == Um::ClearInts - } -} -#[doc = "Field `UM` writer - Update Mode"] -pub type UmW<'a, REG> = crate::BitWriter<'a, REG, Um>; -impl<'a, REG> UmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Um::NoEffect) - } - #[doc = "Allows the clearing of interrupts"] - #[inline(always)] - pub fn clear_ints(self) -> &'a mut crate::W { - self.variant(Um::ClearInts) - } -} -#[doc = "Disable Prescaler On Tamper\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Distam { - #[doc = "0: No effect"] - NoEffect = 0, - #[doc = "1: Automatically disables the prescaler after tamper detection"] - AutoDis = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Distam) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DISTAM` reader - Disable Prescaler On Tamper"] -pub type DistamR = crate::BitReader; -impl DistamR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Distam { - match self.bits { - false => Distam::NoEffect, - true => Distam::AutoDis, - } - } - #[doc = "No effect"] - #[inline(always)] - pub fn is_no_effect(&self) -> bool { - *self == Distam::NoEffect - } - #[doc = "Automatically disables the prescaler after tamper detection"] - #[inline(always)] - pub fn is_auto_dis(&self) -> bool { - *self == Distam::AutoDis - } -} -#[doc = "Field `DISTAM` writer - Disable Prescaler On Tamper"] -pub type DistamW<'a, REG> = crate::BitWriter<'a, REG, Distam>; -impl<'a, REG> DistamW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect"] - #[inline(always)] - pub fn no_effect(self) -> &'a mut crate::W { - self.variant(Distam::NoEffect) - } - #[doc = "Automatically disables the prescaler after tamper detection"] - #[inline(always)] - pub fn auto_dis(self) -> &'a mut crate::W { - self.variant(Distam::AutoDis) - } -} -#[doc = "Field `DPR` reader - Digital Tamper Prescaler"] -pub type DprR = crate::FieldReader; -#[doc = "Field `DPR` writer - Digital Tamper Prescaler"] -pub type DprW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; -impl R { - #[doc = "Bit 0 - Software Reset"] - #[inline(always)] - pub fn swr(&self) -> SwrR { - SwrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Digital Tamper Enable"] - #[inline(always)] - pub fn den(&self) -> DenR { - DenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Tamper Force System Reset"] - #[inline(always)] - pub fn tfsr(&self) -> TfsrR { - TfsrR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Update Mode"] - #[inline(always)] - pub fn um(&self) -> UmR { - UmR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Disable Prescaler On Tamper"] - #[inline(always)] - pub fn distam(&self) -> DistamR { - DistamR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 17:31 - Digital Tamper Prescaler"] - #[inline(always)] - pub fn dpr(&self) -> DprR { - DprR::new(((self.bits >> 17) & 0x7fff) as u16) - } -} -impl W { - #[doc = "Bit 0 - Software Reset"] - #[inline(always)] - pub fn swr(&mut self) -> SwrW { - SwrW::new(self, 0) - } - #[doc = "Bit 1 - Digital Tamper Enable"] - #[inline(always)] - pub fn den(&mut self) -> DenW { - DenW::new(self, 1) - } - #[doc = "Bit 2 - Tamper Force System Reset"] - #[inline(always)] - pub fn tfsr(&mut self) -> TfsrW { - TfsrW::new(self, 2) - } - #[doc = "Bit 3 - Update Mode"] - #[inline(always)] - pub fn um(&mut self) -> UmW { - UmW::new(self, 3) - } - #[doc = "Bit 8 - Disable Prescaler On Tamper"] - #[inline(always)] - pub fn distam(&mut self) -> DistamW { - DistamW::new(self, 8) - } - #[doc = "Bits 17:31 - Digital Tamper Prescaler"] - #[inline(always)] - pub fn dpr(&mut self) -> DprW { - DprW::new(self, 17) - } -} -#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CrSpec; -impl crate::RegisterSpec for CrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cr::R`](R) reader structure"] -impl crate::Readable for CrSpec {} -#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] -impl crate::Writable for CrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CR to value 0"] -impl crate::Resettable for CrSpec {} diff --git a/mcxa276-pac/src/tdet0/ier.rs b/mcxa276-pac/src/tdet0/ier.rs deleted file mode 100644 index 6ec2a8bb6..000000000 --- a/mcxa276-pac/src/tdet0/ier.rs +++ /dev/null @@ -1,1155 +0,0 @@ -#[doc = "Register `IER` reader"] -pub type R = crate::R; -#[doc = "Register `IER` writer"] -pub type W = crate::W; -#[doc = "Digital Tamper Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dtie { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dtie) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DTIE` reader - Digital Tamper Interrupt Enable"] -pub type DtieR = crate::BitReader; -impl DtieR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dtie { - match self.bits { - false => Dtie::Disable, - true => Dtie::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Dtie::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Dtie::Enable - } -} -#[doc = "Field `DTIE` writer - Digital Tamper Interrupt Enable"] -pub type DtieW<'a, REG> = crate::BitWriter<'a, REG, Dtie>; -impl<'a, REG> DtieW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Dtie::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Dtie::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie0 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE0` reader - Tamper Input n Interrupt Enable"] -pub type Tiie0R = crate::BitReader; -impl Tiie0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie0 { - match self.bits { - false => Tiie0::Disable, - true => Tiie0::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie0::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie0::Enable - } -} -#[doc = "Field `TIIE0` writer - Tamper Input n Interrupt Enable"] -pub type Tiie0W<'a, REG> = crate::BitWriter<'a, REG, Tiie0>; -impl<'a, REG> Tiie0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie0::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie0::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie1 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE1` reader - Tamper Input n Interrupt Enable"] -pub type Tiie1R = crate::BitReader; -impl Tiie1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie1 { - match self.bits { - false => Tiie1::Disable, - true => Tiie1::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie1::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie1::Enable - } -} -#[doc = "Field `TIIE1` writer - Tamper Input n Interrupt Enable"] -pub type Tiie1W<'a, REG> = crate::BitWriter<'a, REG, Tiie1>; -impl<'a, REG> Tiie1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie1::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie1::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie2 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE2` reader - Tamper Input n Interrupt Enable"] -pub type Tiie2R = crate::BitReader; -impl Tiie2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie2 { - match self.bits { - false => Tiie2::Disable, - true => Tiie2::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie2::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie2::Enable - } -} -#[doc = "Field `TIIE2` writer - Tamper Input n Interrupt Enable"] -pub type Tiie2W<'a, REG> = crate::BitWriter<'a, REG, Tiie2>; -impl<'a, REG> Tiie2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie2::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie2::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie3 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE3` reader - Tamper Input n Interrupt Enable"] -pub type Tiie3R = crate::BitReader; -impl Tiie3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie3 { - match self.bits { - false => Tiie3::Disable, - true => Tiie3::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie3::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie3::Enable - } -} -#[doc = "Field `TIIE3` writer - Tamper Input n Interrupt Enable"] -pub type Tiie3W<'a, REG> = crate::BitWriter<'a, REG, Tiie3>; -impl<'a, REG> Tiie3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie3::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie3::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie4 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE4` reader - Tamper Input n Interrupt Enable"] -pub type Tiie4R = crate::BitReader; -impl Tiie4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie4 { - match self.bits { - false => Tiie4::Disable, - true => Tiie4::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie4::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie4::Enable - } -} -#[doc = "Field `TIIE4` writer - Tamper Input n Interrupt Enable"] -pub type Tiie4W<'a, REG> = crate::BitWriter<'a, REG, Tiie4>; -impl<'a, REG> Tiie4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie4::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie4::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie5 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE5` reader - Tamper Input n Interrupt Enable"] -pub type Tiie5R = crate::BitReader; -impl Tiie5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie5 { - match self.bits { - false => Tiie5::Disable, - true => Tiie5::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie5::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie5::Enable - } -} -#[doc = "Field `TIIE5` writer - Tamper Input n Interrupt Enable"] -pub type Tiie5W<'a, REG> = crate::BitWriter<'a, REG, Tiie5>; -impl<'a, REG> Tiie5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie5::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie5::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie6 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE6` reader - Tamper Input n Interrupt Enable"] -pub type Tiie6R = crate::BitReader; -impl Tiie6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie6 { - match self.bits { - false => Tiie6::Disable, - true => Tiie6::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie6::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie6::Enable - } -} -#[doc = "Field `TIIE6` writer - Tamper Input n Interrupt Enable"] -pub type Tiie6W<'a, REG> = crate::BitWriter<'a, REG, Tiie6>; -impl<'a, REG> Tiie6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie6::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie6::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie7 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE7` reader - Tamper Input n Interrupt Enable"] -pub type Tiie7R = crate::BitReader; -impl Tiie7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie7 { - match self.bits { - false => Tiie7::Disable, - true => Tiie7::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie7::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie7::Enable - } -} -#[doc = "Field `TIIE7` writer - Tamper Input n Interrupt Enable"] -pub type Tiie7W<'a, REG> = crate::BitWriter<'a, REG, Tiie7>; -impl<'a, REG> Tiie7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie7::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie7::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie8 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE8` reader - Tamper Input n Interrupt Enable"] -pub type Tiie8R = crate::BitReader; -impl Tiie8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie8 { - match self.bits { - false => Tiie8::Disable, - true => Tiie8::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie8::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie8::Enable - } -} -#[doc = "Field `TIIE8` writer - Tamper Input n Interrupt Enable"] -pub type Tiie8W<'a, REG> = crate::BitWriter<'a, REG, Tiie8>; -impl<'a, REG> Tiie8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie8::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie8::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie9 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE9` reader - Tamper Input n Interrupt Enable"] -pub type Tiie9R = crate::BitReader; -impl Tiie9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie9 { - match self.bits { - false => Tiie9::Disable, - true => Tiie9::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie9::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie9::Enable - } -} -#[doc = "Field `TIIE9` writer - Tamper Input n Interrupt Enable"] -pub type Tiie9W<'a, REG> = crate::BitWriter<'a, REG, Tiie9>; -impl<'a, REG> Tiie9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie9::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie9::Enable) - } -} -#[doc = "Tamper Input n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tiie10 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tiie10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIIE10` reader - Tamper Input n Interrupt Enable"] -pub type Tiie10R = crate::BitReader; -impl Tiie10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tiie10 { - match self.bits { - false => Tiie10::Disable, - true => Tiie10::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tiie10::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tiie10::Enable - } -} -#[doc = "Field `TIIE10` writer - Tamper Input n Interrupt Enable"] -pub type Tiie10W<'a, REG> = crate::BitWriter<'a, REG, Tiie10>; -impl<'a, REG> Tiie10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tiie10::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tiie10::Enable) - } -} -#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpie0 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpie0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPIE0` reader - Tamper Pin n Interrupt Enable"] -pub type Tpie0R = crate::BitReader; -impl Tpie0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpie0 { - match self.bits { - false => Tpie0::Disable, - true => Tpie0::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpie0::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpie0::Enable - } -} -#[doc = "Field `TPIE0` writer - Tamper Pin n Interrupt Enable"] -pub type Tpie0W<'a, REG> = crate::BitWriter<'a, REG, Tpie0>; -impl<'a, REG> Tpie0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpie0::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpie0::Enable) - } -} -#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpie1 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpie1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPIE1` reader - Tamper Pin n Interrupt Enable"] -pub type Tpie1R = crate::BitReader; -impl Tpie1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpie1 { - match self.bits { - false => Tpie1::Disable, - true => Tpie1::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpie1::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpie1::Enable - } -} -#[doc = "Field `TPIE1` writer - Tamper Pin n Interrupt Enable"] -pub type Tpie1W<'a, REG> = crate::BitWriter<'a, REG, Tpie1>; -impl<'a, REG> Tpie1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpie1::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpie1::Enable) - } -} -#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpie2 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpie2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPIE2` reader - Tamper Pin n Interrupt Enable"] -pub type Tpie2R = crate::BitReader; -impl Tpie2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpie2 { - match self.bits { - false => Tpie2::Disable, - true => Tpie2::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpie2::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpie2::Enable - } -} -#[doc = "Field `TPIE2` writer - Tamper Pin n Interrupt Enable"] -pub type Tpie2W<'a, REG> = crate::BitWriter<'a, REG, Tpie2>; -impl<'a, REG> Tpie2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpie2::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpie2::Enable) - } -} -#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpie3 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpie3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPIE3` reader - Tamper Pin n Interrupt Enable"] -pub type Tpie3R = crate::BitReader; -impl Tpie3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpie3 { - match self.bits { - false => Tpie3::Disable, - true => Tpie3::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpie3::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpie3::Enable - } -} -#[doc = "Field `TPIE3` writer - Tamper Pin n Interrupt Enable"] -pub type Tpie3W<'a, REG> = crate::BitWriter<'a, REG, Tpie3>; -impl<'a, REG> Tpie3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpie3::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpie3::Enable) - } -} -#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpie4 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpie4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPIE4` reader - Tamper Pin n Interrupt Enable"] -pub type Tpie4R = crate::BitReader; -impl Tpie4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpie4 { - match self.bits { - false => Tpie4::Disable, - true => Tpie4::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpie4::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpie4::Enable - } -} -#[doc = "Field `TPIE4` writer - Tamper Pin n Interrupt Enable"] -pub type Tpie4W<'a, REG> = crate::BitWriter<'a, REG, Tpie4>; -impl<'a, REG> Tpie4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpie4::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpie4::Enable) - } -} -#[doc = "Tamper Pin n Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpie5 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpie5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPIE5` reader - Tamper Pin n Interrupt Enable"] -pub type Tpie5R = crate::BitReader; -impl Tpie5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpie5 { - match self.bits { - false => Tpie5::Disable, - true => Tpie5::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpie5::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpie5::Enable - } -} -#[doc = "Field `TPIE5` writer - Tamper Pin n Interrupt Enable"] -pub type Tpie5W<'a, REG> = crate::BitWriter<'a, REG, Tpie5>; -impl<'a, REG> Tpie5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpie5::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpie5::Enable) - } -} -impl R { - #[doc = "Bit 0 - Digital Tamper Interrupt Enable"] - #[inline(always)] - pub fn dtie(&self) -> DtieR { - DtieR::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie0(&self) -> Tiie0R { - Tiie0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie1(&self) -> Tiie1R { - Tiie1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie2(&self) -> Tiie2R { - Tiie2R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie3(&self) -> Tiie3R { - Tiie3R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie4(&self) -> Tiie4R { - Tiie4R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie5(&self) -> Tiie5R { - Tiie5R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie6(&self) -> Tiie6R { - Tiie6R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie7(&self) -> Tiie7R { - Tiie7R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie8(&self) -> Tiie8R { - Tiie8R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie9(&self) -> Tiie9R { - Tiie9R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie10(&self) -> Tiie10R { - Tiie10R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 16 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie0(&self) -> Tpie0R { - Tpie0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie1(&self) -> Tpie1R { - Tpie1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie2(&self) -> Tpie2R { - Tpie2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie3(&self) -> Tpie3R { - Tpie3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie4(&self) -> Tpie4R { - Tpie4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie5(&self) -> Tpie5R { - Tpie5R::new(((self.bits >> 21) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Digital Tamper Interrupt Enable"] - #[inline(always)] - pub fn dtie(&mut self) -> DtieW { - DtieW::new(self, 0) - } - #[doc = "Bit 2 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie0(&mut self) -> Tiie0W { - Tiie0W::new(self, 2) - } - #[doc = "Bit 3 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie1(&mut self) -> Tiie1W { - Tiie1W::new(self, 3) - } - #[doc = "Bit 4 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie2(&mut self) -> Tiie2W { - Tiie2W::new(self, 4) - } - #[doc = "Bit 5 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie3(&mut self) -> Tiie3W { - Tiie3W::new(self, 5) - } - #[doc = "Bit 6 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie4(&mut self) -> Tiie4W { - Tiie4W::new(self, 6) - } - #[doc = "Bit 7 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie5(&mut self) -> Tiie5W { - Tiie5W::new(self, 7) - } - #[doc = "Bit 8 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie6(&mut self) -> Tiie6W { - Tiie6W::new(self, 8) - } - #[doc = "Bit 9 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie7(&mut self) -> Tiie7W { - Tiie7W::new(self, 9) - } - #[doc = "Bit 10 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie8(&mut self) -> Tiie8W { - Tiie8W::new(self, 10) - } - #[doc = "Bit 11 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie9(&mut self) -> Tiie9W { - Tiie9W::new(self, 11) - } - #[doc = "Bit 12 - Tamper Input n Interrupt Enable"] - #[inline(always)] - pub fn tiie10(&mut self) -> Tiie10W { - Tiie10W::new(self, 12) - } - #[doc = "Bit 16 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie0(&mut self) -> Tpie0W { - Tpie0W::new(self, 16) - } - #[doc = "Bit 17 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie1(&mut self) -> Tpie1W { - Tpie1W::new(self, 17) - } - #[doc = "Bit 18 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie2(&mut self) -> Tpie2W { - Tpie2W::new(self, 18) - } - #[doc = "Bit 19 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie3(&mut self) -> Tpie3W { - Tpie3W::new(self, 19) - } - #[doc = "Bit 20 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie4(&mut self) -> Tpie4W { - Tpie4W::new(self, 20) - } - #[doc = "Bit 21 - Tamper Pin n Interrupt Enable"] - #[inline(always)] - pub fn tpie5(&mut self) -> Tpie5W { - Tpie5W::new(self, 21) - } -} -#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IerSpec; -impl crate::RegisterSpec for IerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ier::R`](R) reader structure"] -impl crate::Readable for IerSpec {} -#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] -impl crate::Writable for IerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets IER to value 0"] -impl crate::Resettable for IerSpec {} diff --git a/mcxa276-pac/src/tdet0/lr.rs b/mcxa276-pac/src/tdet0/lr.rs deleted file mode 100644 index 3e100f663..000000000 --- a/mcxa276-pac/src/tdet0/lr.rs +++ /dev/null @@ -1,842 +0,0 @@ -#[doc = "Register `LR` reader"] -pub type R = crate::R; -#[doc = "Register `LR` writer"] -pub type W = crate::W; -#[doc = "Control Register Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crl { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRL` reader - Control Register Lock"] -pub type CrlR = crate::BitReader; -impl CrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crl { - match self.bits { - false => Crl::Lock, - true => Crl::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Crl::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Crl::NotLock - } -} -#[doc = "Field `CRL` writer - Control Register Lock"] -pub type CrlW<'a, REG> = crate::BitWriter<'a, REG, Crl>; -impl<'a, REG> CrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Crl::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Crl::NotLock) - } -} -#[doc = "Status Register Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Srl { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Srl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SRL` reader - Status Register Lock"] -pub type SrlR = crate::BitReader; -impl SrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Srl { - match self.bits { - false => Srl::Lock, - true => Srl::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Srl::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Srl::NotLock - } -} -#[doc = "Field `SRL` writer - Status Register Lock"] -pub type SrlW<'a, REG> = crate::BitWriter<'a, REG, Srl>; -impl<'a, REG> SrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Srl::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Srl::NotLock) - } -} -#[doc = "Lock Register Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lrl { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lrl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LRL` reader - Lock Register Lock"] -pub type LrlR = crate::BitReader; -impl LrlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lrl { - match self.bits { - false => Lrl::Lock, - true => Lrl::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Lrl::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Lrl::NotLock - } -} -#[doc = "Field `LRL` writer - Lock Register Lock"] -pub type LrlW<'a, REG> = crate::BitWriter<'a, REG, Lrl>; -impl<'a, REG> LrlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Lrl::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Lrl::NotLock) - } -} -#[doc = "Interrupt Enable Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Iel { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Iel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IEL` reader - Interrupt Enable Lock"] -pub type IelR = crate::BitReader; -impl IelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Iel { - match self.bits { - false => Iel::Lock, - true => Iel::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Iel::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Iel::NotLock - } -} -#[doc = "Field `IEL` writer - Interrupt Enable Lock"] -pub type IelW<'a, REG> = crate::BitWriter<'a, REG, Iel>; -impl<'a, REG> IelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Iel::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Iel::NotLock) - } -} -#[doc = "Tamper Seconds Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tsl { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tsl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TSL` reader - Tamper Seconds Lock"] -pub type TslR = crate::BitReader; -impl TslR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tsl { - match self.bits { - false => Tsl::Lock, - true => Tsl::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Tsl::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Tsl::NotLock - } -} -#[doc = "Field `TSL` writer - Tamper Seconds Lock"] -pub type TslW<'a, REG> = crate::BitWriter<'a, REG, Tsl>; -impl<'a, REG> TslW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Tsl::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Tsl::NotLock) - } -} -#[doc = "Tamper Enable Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tel { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TEL` reader - Tamper Enable Lock"] -pub type TelR = crate::BitReader; -impl TelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tel { - match self.bits { - false => Tel::Lock, - true => Tel::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Tel::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Tel::NotLock - } -} -#[doc = "Field `TEL` writer - Tamper Enable Lock"] -pub type TelW<'a, REG> = crate::BitWriter<'a, REG, Tel>; -impl<'a, REG> TelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Tel::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Tel::NotLock) - } -} -#[doc = "Pin Polarity Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ppl { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ppl) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PPL` reader - Pin Polarity Lock"] -pub type PplR = crate::BitReader; -impl PplR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ppl { - match self.bits { - false => Ppl::Lock, - true => Ppl::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Ppl::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Ppl::NotLock - } -} -#[doc = "Field `PPL` writer - Pin Polarity Lock"] -pub type PplW<'a, REG> = crate::BitWriter<'a, REG, Ppl>; -impl<'a, REG> PplW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Ppl::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Ppl::NotLock) - } -} -#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfl0 { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfl0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFL0` reader - Glitch Filter Lock"] -pub type Gfl0R = crate::BitReader; -impl Gfl0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfl0 { - match self.bits { - false => Gfl0::Lock, - true => Gfl0::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Gfl0::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Gfl0::NotLock - } -} -#[doc = "Field `GFL0` writer - Glitch Filter Lock"] -pub type Gfl0W<'a, REG> = crate::BitWriter<'a, REG, Gfl0>; -impl<'a, REG> Gfl0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Gfl0::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Gfl0::NotLock) - } -} -#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfl1 { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfl1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFL1` reader - Glitch Filter Lock"] -pub type Gfl1R = crate::BitReader; -impl Gfl1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfl1 { - match self.bits { - false => Gfl1::Lock, - true => Gfl1::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Gfl1::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Gfl1::NotLock - } -} -#[doc = "Field `GFL1` writer - Glitch Filter Lock"] -pub type Gfl1W<'a, REG> = crate::BitWriter<'a, REG, Gfl1>; -impl<'a, REG> Gfl1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Gfl1::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Gfl1::NotLock) - } -} -#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfl2 { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfl2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFL2` reader - Glitch Filter Lock"] -pub type Gfl2R = crate::BitReader; -impl Gfl2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfl2 { - match self.bits { - false => Gfl2::Lock, - true => Gfl2::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Gfl2::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Gfl2::NotLock - } -} -#[doc = "Field `GFL2` writer - Glitch Filter Lock"] -pub type Gfl2W<'a, REG> = crate::BitWriter<'a, REG, Gfl2>; -impl<'a, REG> Gfl2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Gfl2::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Gfl2::NotLock) - } -} -#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfl3 { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfl3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFL3` reader - Glitch Filter Lock"] -pub type Gfl3R = crate::BitReader; -impl Gfl3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfl3 { - match self.bits { - false => Gfl3::Lock, - true => Gfl3::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Gfl3::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Gfl3::NotLock - } -} -#[doc = "Field `GFL3` writer - Glitch Filter Lock"] -pub type Gfl3W<'a, REG> = crate::BitWriter<'a, REG, Gfl3>; -impl<'a, REG> Gfl3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Gfl3::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Gfl3::NotLock) - } -} -#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfl4 { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfl4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFL4` reader - Glitch Filter Lock"] -pub type Gfl4R = crate::BitReader; -impl Gfl4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfl4 { - match self.bits { - false => Gfl4::Lock, - true => Gfl4::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Gfl4::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Gfl4::NotLock - } -} -#[doc = "Field `GFL4` writer - Glitch Filter Lock"] -pub type Gfl4W<'a, REG> = crate::BitWriter<'a, REG, Gfl4>; -impl<'a, REG> Gfl4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Gfl4::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Gfl4::NotLock) - } -} -#[doc = "Glitch Filter Lock\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfl5 { - #[doc = "0: Locked and writes are ignored"] - Lock = 0, - #[doc = "1: Not locked and writes complete as normal"] - NotLock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfl5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFL5` reader - Glitch Filter Lock"] -pub type Gfl5R = crate::BitReader; -impl Gfl5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfl5 { - match self.bits { - false => Gfl5::Lock, - true => Gfl5::NotLock, - } - } - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Gfl5::Lock - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn is_not_lock(&self) -> bool { - *self == Gfl5::NotLock - } -} -#[doc = "Field `GFL5` writer - Glitch Filter Lock"] -pub type Gfl5W<'a, REG> = crate::BitWriter<'a, REG, Gfl5>; -impl<'a, REG> Gfl5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Locked and writes are ignored"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Gfl5::Lock) - } - #[doc = "Not locked and writes complete as normal"] - #[inline(always)] - pub fn not_lock(self) -> &'a mut crate::W { - self.variant(Gfl5::NotLock) - } -} -impl R { - #[doc = "Bit 4 - Control Register Lock"] - #[inline(always)] - pub fn crl(&self) -> CrlR { - CrlR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Status Register Lock"] - #[inline(always)] - pub fn srl(&self) -> SrlR { - SrlR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Lock Register Lock"] - #[inline(always)] - pub fn lrl(&self) -> LrlR { - LrlR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Interrupt Enable Lock"] - #[inline(always)] - pub fn iel(&self) -> IelR { - IelR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Tamper Seconds Lock"] - #[inline(always)] - pub fn tsl(&self) -> TslR { - TslR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Tamper Enable Lock"] - #[inline(always)] - pub fn tel(&self) -> TelR { - TelR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 11 - Pin Polarity Lock"] - #[inline(always)] - pub fn ppl(&self) -> PplR { - PplR::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 16 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl0(&self) -> Gfl0R { - Gfl0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl1(&self) -> Gfl1R { - Gfl1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl2(&self) -> Gfl2R { - Gfl2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl3(&self) -> Gfl3R { - Gfl3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl4(&self) -> Gfl4R { - Gfl4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl5(&self) -> Gfl5R { - Gfl5R::new(((self.bits >> 21) & 1) != 0) - } -} -impl W { - #[doc = "Bit 4 - Control Register Lock"] - #[inline(always)] - pub fn crl(&mut self) -> CrlW { - CrlW::new(self, 4) - } - #[doc = "Bit 5 - Status Register Lock"] - #[inline(always)] - pub fn srl(&mut self) -> SrlW { - SrlW::new(self, 5) - } - #[doc = "Bit 6 - Lock Register Lock"] - #[inline(always)] - pub fn lrl(&mut self) -> LrlW { - LrlW::new(self, 6) - } - #[doc = "Bit 7 - Interrupt Enable Lock"] - #[inline(always)] - pub fn iel(&mut self) -> IelW { - IelW::new(self, 7) - } - #[doc = "Bit 8 - Tamper Seconds Lock"] - #[inline(always)] - pub fn tsl(&mut self) -> TslW { - TslW::new(self, 8) - } - #[doc = "Bit 9 - Tamper Enable Lock"] - #[inline(always)] - pub fn tel(&mut self) -> TelW { - TelW::new(self, 9) - } - #[doc = "Bit 11 - Pin Polarity Lock"] - #[inline(always)] - pub fn ppl(&mut self) -> PplW { - PplW::new(self, 11) - } - #[doc = "Bit 16 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl0(&mut self) -> Gfl0W { - Gfl0W::new(self, 16) - } - #[doc = "Bit 17 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl1(&mut self) -> Gfl1W { - Gfl1W::new(self, 17) - } - #[doc = "Bit 18 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl2(&mut self) -> Gfl2W { - Gfl2W::new(self, 18) - } - #[doc = "Bit 19 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl3(&mut self) -> Gfl3W { - Gfl3W::new(self, 19) - } - #[doc = "Bit 20 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl4(&mut self) -> Gfl4W { - Gfl4W::new(self, 20) - } - #[doc = "Bit 21 - Glitch Filter Lock"] - #[inline(always)] - pub fn gfl5(&mut self) -> Gfl5W { - Gfl5W::new(self, 21) - } -} -#[doc = "Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`lr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct LrSpec; -impl crate::RegisterSpec for LrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`lr::R`](R) reader structure"] -impl crate::Readable for LrSpec {} -#[doc = "`write(|w| ..)` method takes [`lr::W`](W) writer structure"] -impl crate::Writable for LrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets LR to value 0x003f_0bf0"] -impl crate::Resettable for LrSpec { - const RESET_VALUE: u32 = 0x003f_0bf0; -} diff --git a/mcxa276-pac/src/tdet0/pgfr.rs b/mcxa276-pac/src/tdet0/pgfr.rs deleted file mode 100644 index 8b6f5448c..000000000 --- a/mcxa276-pac/src/tdet0/pgfr.rs +++ /dev/null @@ -1,668 +0,0 @@ -#[doc = "Register `PGFR[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `PGFR[%s]` writer"] -pub type W = crate::W; -#[doc = "Field `GFW` reader - Glitch Filter Width"] -pub type GfwR = crate::FieldReader; -#[doc = "Field `GFW` writer - Glitch Filter Width"] -pub type GfwW<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Glitch Filter Prescaler\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfp { - #[doc = "0: 512 Hz prescaler clock"] - Freq512Hz = 0, - #[doc = "1: 32.768 kHz clock"] - Freq32Khz = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFP` reader - Glitch Filter Prescaler"] -pub type GfpR = crate::BitReader; -impl GfpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfp { - match self.bits { - false => Gfp::Freq512Hz, - true => Gfp::Freq32Khz, - } - } - #[doc = "512 Hz prescaler clock"] - #[inline(always)] - pub fn is_freq_512_hz(&self) -> bool { - *self == Gfp::Freq512Hz - } - #[doc = "32.768 kHz clock"] - #[inline(always)] - pub fn is_freq_32_khz(&self) -> bool { - *self == Gfp::Freq32Khz - } -} -#[doc = "Field `GFP` writer - Glitch Filter Prescaler"] -pub type GfpW<'a, REG> = crate::BitWriter<'a, REG, Gfp>; -impl<'a, REG> GfpW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "512 Hz prescaler clock"] - #[inline(always)] - pub fn freq_512_hz(self) -> &'a mut crate::W { - self.variant(Gfp::Freq512Hz) - } - #[doc = "32.768 kHz clock"] - #[inline(always)] - pub fn freq_32_khz(self) -> &'a mut crate::W { - self.variant(Gfp::Freq32Khz) - } -} -#[doc = "Glitch Filter Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Gfe { - #[doc = "0: Bypasses"] - Bypass = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Gfe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `GFE` reader - Glitch Filter Enable"] -pub type GfeR = crate::BitReader; -impl GfeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Gfe { - match self.bits { - false => Gfe::Bypass, - true => Gfe::Enable, - } - } - #[doc = "Bypasses"] - #[inline(always)] - pub fn is_bypass(&self) -> bool { - *self == Gfe::Bypass - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Gfe::Enable - } -} -#[doc = "Field `GFE` writer - Glitch Filter Enable"] -pub type GfeW<'a, REG> = crate::BitWriter<'a, REG, Gfe>; -impl<'a, REG> GfeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Bypasses"] - #[inline(always)] - pub fn bypass(self) -> &'a mut crate::W { - self.variant(Gfe::Bypass) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Gfe::Enable) - } -} -#[doc = "Tamper Pin Sample Width\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tpsw { - #[doc = "0: Continuous monitoring, pin sampling disabled"] - Disable = 0, - #[doc = "1: 2 cycles for pull enable and 1 cycle for input buffer enable"] - Cycles2 = 1, - #[doc = "2: 4 cycles for pull enable and 2 cycles for input buffer enable"] - Cycles4 = 2, - #[doc = "3: 8 cycles for pull enable and 4 cycles for input buffer enable"] - Cycles8 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tpsw) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tpsw { - type Ux = u8; -} -impl crate::IsEnum for Tpsw {} -#[doc = "Field `TPSW` reader - Tamper Pin Sample Width"] -pub type TpswR = crate::FieldReader; -impl TpswR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpsw { - match self.bits { - 0 => Tpsw::Disable, - 1 => Tpsw::Cycles2, - 2 => Tpsw::Cycles4, - 3 => Tpsw::Cycles8, - _ => unreachable!(), - } - } - #[doc = "Continuous monitoring, pin sampling disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpsw::Disable - } - #[doc = "2 cycles for pull enable and 1 cycle for input buffer enable"] - #[inline(always)] - pub fn is_cycles_2(&self) -> bool { - *self == Tpsw::Cycles2 - } - #[doc = "4 cycles for pull enable and 2 cycles for input buffer enable"] - #[inline(always)] - pub fn is_cycles_4(&self) -> bool { - *self == Tpsw::Cycles4 - } - #[doc = "8 cycles for pull enable and 4 cycles for input buffer enable"] - #[inline(always)] - pub fn is_cycles_8(&self) -> bool { - *self == Tpsw::Cycles8 - } -} -#[doc = "Field `TPSW` writer - Tamper Pin Sample Width"] -pub type TpswW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tpsw, crate::Safe>; -impl<'a, REG> TpswW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Continuous monitoring, pin sampling disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpsw::Disable) - } - #[doc = "2 cycles for pull enable and 1 cycle for input buffer enable"] - #[inline(always)] - pub fn cycles_2(self) -> &'a mut crate::W { - self.variant(Tpsw::Cycles2) - } - #[doc = "4 cycles for pull enable and 2 cycles for input buffer enable"] - #[inline(always)] - pub fn cycles_4(self) -> &'a mut crate::W { - self.variant(Tpsw::Cycles4) - } - #[doc = "8 cycles for pull enable and 4 cycles for input buffer enable"] - #[inline(always)] - pub fn cycles_8(self) -> &'a mut crate::W { - self.variant(Tpsw::Cycles8) - } -} -#[doc = "Tamper Pin Sample Frequency\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tpsf { - #[doc = "0: Every 8 cycles"] - Cycles8 = 0, - #[doc = "1: Every 32 cycles"] - Cycles32 = 1, - #[doc = "2: Every 128 cycles"] - Cycles128 = 2, - #[doc = "3: Every 512 cycles"] - Cycles512 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tpsf) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tpsf { - type Ux = u8; -} -impl crate::IsEnum for Tpsf {} -#[doc = "Field `TPSF` reader - Tamper Pin Sample Frequency"] -pub type TpsfR = crate::FieldReader; -impl TpsfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpsf { - match self.bits { - 0 => Tpsf::Cycles8, - 1 => Tpsf::Cycles32, - 2 => Tpsf::Cycles128, - 3 => Tpsf::Cycles512, - _ => unreachable!(), - } - } - #[doc = "Every 8 cycles"] - #[inline(always)] - pub fn is_cycles_8(&self) -> bool { - *self == Tpsf::Cycles8 - } - #[doc = "Every 32 cycles"] - #[inline(always)] - pub fn is_cycles_32(&self) -> bool { - *self == Tpsf::Cycles32 - } - #[doc = "Every 128 cycles"] - #[inline(always)] - pub fn is_cycles_128(&self) -> bool { - *self == Tpsf::Cycles128 - } - #[doc = "Every 512 cycles"] - #[inline(always)] - pub fn is_cycles_512(&self) -> bool { - *self == Tpsf::Cycles512 - } -} -#[doc = "Field `TPSF` writer - Tamper Pin Sample Frequency"] -pub type TpsfW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tpsf, crate::Safe>; -impl<'a, REG> TpsfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Every 8 cycles"] - #[inline(always)] - pub fn cycles_8(self) -> &'a mut crate::W { - self.variant(Tpsf::Cycles8) - } - #[doc = "Every 32 cycles"] - #[inline(always)] - pub fn cycles_32(self) -> &'a mut crate::W { - self.variant(Tpsf::Cycles32) - } - #[doc = "Every 128 cycles"] - #[inline(always)] - pub fn cycles_128(self) -> &'a mut crate::W { - self.variant(Tpsf::Cycles128) - } - #[doc = "Every 512 cycles"] - #[inline(always)] - pub fn cycles_512(self) -> &'a mut crate::W { - self.variant(Tpsf::Cycles512) - } -} -#[doc = "Tamper Pull Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpe { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPE` reader - Tamper Pull Enable"] -pub type TpeR = crate::BitReader; -impl TpeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpe { - match self.bits { - false => Tpe::Disable, - true => Tpe::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpe::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpe::Enable - } -} -#[doc = "Field `TPE` writer - Tamper Pull Enable"] -pub type TpeW<'a, REG> = crate::BitWriter<'a, REG, Tpe>; -impl<'a, REG> TpeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpe::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpe::Enable) - } -} -#[doc = "Tamper Pull Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tps { - #[doc = "0: Asserts"] - Assert = 0, - #[doc = "1: Negates"] - Negate = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tps) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPS` reader - Tamper Pull Select"] -pub type TpsR = crate::BitReader; -impl TpsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tps { - match self.bits { - false => Tps::Assert, - true => Tps::Negate, - } - } - #[doc = "Asserts"] - #[inline(always)] - pub fn is_assert(&self) -> bool { - *self == Tps::Assert - } - #[doc = "Negates"] - #[inline(always)] - pub fn is_negate(&self) -> bool { - *self == Tps::Negate - } -} -#[doc = "Field `TPS` writer - Tamper Pull Select"] -pub type TpsW<'a, REG> = crate::BitWriter<'a, REG, Tps>; -impl<'a, REG> TpsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Asserts"] - #[inline(always)] - pub fn assert(self) -> &'a mut crate::W { - self.variant(Tps::Assert) - } - #[doc = "Negates"] - #[inline(always)] - pub fn negate(self) -> &'a mut crate::W { - self.variant(Tps::Negate) - } -} -#[doc = "Tamper Pull Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpv { - #[doc = "0: Low"] - Low = 0, - #[doc = "1: High"] - High = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpv) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPV` reader - Tamper Pull Value"] -pub type TpvR = crate::BitReader; -impl TpvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpv { - match self.bits { - false => Tpv::Low, - true => Tpv::High, - } - } - #[doc = "Low"] - #[inline(always)] - pub fn is_low(&self) -> bool { - *self == Tpv::Low - } - #[doc = "High"] - #[inline(always)] - pub fn is_high(&self) -> bool { - *self == Tpv::High - } -} -#[doc = "Field `TPV` writer - Tamper Pull Value"] -pub type TpvW<'a, REG> = crate::BitWriter<'a, REG, Tpv>; -impl<'a, REG> TpvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Low"] - #[inline(always)] - pub fn low(self) -> &'a mut crate::W { - self.variant(Tpv::Low) - } - #[doc = "High"] - #[inline(always)] - pub fn high(self) -> &'a mut crate::W { - self.variant(Tpv::High) - } -} -#[doc = "Tamper Passive Filter\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpf { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPF` reader - Tamper Passive Filter"] -pub type TpfR = crate::BitReader; -impl TpfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpf { - match self.bits { - false => Tpf::Disable, - true => Tpf::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpf::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpf::Enable - } -} -#[doc = "Field `TPF` writer - Tamper Passive Filter"] -pub type TpfW<'a, REG> = crate::BitWriter<'a, REG, Tpf>; -impl<'a, REG> TpfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpf::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpf::Enable) - } -} -#[doc = "Input Buffer Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ibe { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ibe) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IBE` reader - Input Buffer Enable"] -pub type IbeR = crate::BitReader; -impl IbeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ibe { - match self.bits { - false => Ibe::Disable, - true => Ibe::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Ibe::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Ibe::Enable - } -} -#[doc = "Field `IBE` writer - Input Buffer Enable"] -pub type IbeW<'a, REG> = crate::BitWriter<'a, REG, Ibe>; -impl<'a, REG> IbeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Ibe::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Ibe::Enable) - } -} -impl R { - #[doc = "Bits 0:5 - Glitch Filter Width"] - #[inline(always)] - pub fn gfw(&self) -> GfwR { - GfwR::new((self.bits & 0x3f) as u8) - } - #[doc = "Bit 6 - Glitch Filter Prescaler"] - #[inline(always)] - pub fn gfp(&self) -> GfpR { - GfpR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Glitch Filter Enable"] - #[inline(always)] - pub fn gfe(&self) -> GfeR { - GfeR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:9 - Tamper Pin Sample Width"] - #[inline(always)] - pub fn tpsw(&self) -> TpswR { - TpswR::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Tamper Pin Sample Frequency"] - #[inline(always)] - pub fn tpsf(&self) -> TpsfR { - TpsfR::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bit 24 - Tamper Pull Enable"] - #[inline(always)] - pub fn tpe(&self) -> TpeR { - TpeR::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Tamper Pull Select"] - #[inline(always)] - pub fn tps(&self) -> TpsR { - TpsR::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Tamper Pull Value"] - #[inline(always)] - pub fn tpv(&self) -> TpvR { - TpvR::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Tamper Passive Filter"] - #[inline(always)] - pub fn tpf(&self) -> TpfR { - TpfR::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 31 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&self) -> IbeR { - IbeR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:5 - Glitch Filter Width"] - #[inline(always)] - pub fn gfw(&mut self) -> GfwW { - GfwW::new(self, 0) - } - #[doc = "Bit 6 - Glitch Filter Prescaler"] - #[inline(always)] - pub fn gfp(&mut self) -> GfpW { - GfpW::new(self, 6) - } - #[doc = "Bit 7 - Glitch Filter Enable"] - #[inline(always)] - pub fn gfe(&mut self) -> GfeW { - GfeW::new(self, 7) - } - #[doc = "Bits 8:9 - Tamper Pin Sample Width"] - #[inline(always)] - pub fn tpsw(&mut self) -> TpswW { - TpswW::new(self, 8) - } - #[doc = "Bits 10:11 - Tamper Pin Sample Frequency"] - #[inline(always)] - pub fn tpsf(&mut self) -> TpsfW { - TpsfW::new(self, 10) - } - #[doc = "Bit 24 - Tamper Pull Enable"] - #[inline(always)] - pub fn tpe(&mut self) -> TpeW { - TpeW::new(self, 24) - } - #[doc = "Bit 25 - Tamper Pull Select"] - #[inline(always)] - pub fn tps(&mut self) -> TpsW { - TpsW::new(self, 25) - } - #[doc = "Bit 26 - Tamper Pull Value"] - #[inline(always)] - pub fn tpv(&mut self) -> TpvW { - TpvW::new(self, 26) - } - #[doc = "Bit 27 - Tamper Passive Filter"] - #[inline(always)] - pub fn tpf(&mut self) -> TpfW { - TpfW::new(self, 27) - } - #[doc = "Bit 31 - Input Buffer Enable"] - #[inline(always)] - pub fn ibe(&mut self) -> IbeW { - IbeW::new(self, 31) - } -} -#[doc = "Pin Glitch Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`pgfr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pgfr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PgfrSpec; -impl crate::RegisterSpec for PgfrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pgfr::R`](R) reader structure"] -impl crate::Readable for PgfrSpec {} -#[doc = "`write(|w| ..)` method takes [`pgfr::W`](W) writer structure"] -impl crate::Writable for PgfrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PGFR[%s] to value 0"] -impl crate::Resettable for PgfrSpec {} diff --git a/mcxa276-pac/src/tdet0/ppr.rs b/mcxa276-pac/src/tdet0/ppr.rs deleted file mode 100644 index 371ac26b9..000000000 --- a/mcxa276-pac/src/tdet0/ppr.rs +++ /dev/null @@ -1,645 +0,0 @@ -#[doc = "Register `PPR` reader"] -pub type R = crate::R; -#[doc = "Register `PPR` writer"] -pub type W = crate::W; -#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpp0 { - #[doc = "0: Not inverted"] - NoInvert = 0, - #[doc = "1: Inverted"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpp0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPP0` reader - Tamper Pin n Polarity"] -pub type Tpp0R = crate::BitReader; -impl Tpp0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpp0 { - match self.bits { - false => Tpp0::NoInvert, - true => Tpp0::Invert, - } - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == Tpp0::NoInvert - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == Tpp0::Invert - } -} -#[doc = "Field `TPP0` writer - Tamper Pin n Polarity"] -pub type Tpp0W<'a, REG> = crate::BitWriter<'a, REG, Tpp0>; -impl<'a, REG> Tpp0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not inverted"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(Tpp0::NoInvert) - } - #[doc = "Inverted"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(Tpp0::Invert) - } -} -#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpp1 { - #[doc = "0: Not inverted"] - NoInvert = 0, - #[doc = "1: Inverted"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpp1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPP1` reader - Tamper Pin n Polarity"] -pub type Tpp1R = crate::BitReader; -impl Tpp1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpp1 { - match self.bits { - false => Tpp1::NoInvert, - true => Tpp1::Invert, - } - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == Tpp1::NoInvert - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == Tpp1::Invert - } -} -#[doc = "Field `TPP1` writer - Tamper Pin n Polarity"] -pub type Tpp1W<'a, REG> = crate::BitWriter<'a, REG, Tpp1>; -impl<'a, REG> Tpp1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not inverted"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(Tpp1::NoInvert) - } - #[doc = "Inverted"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(Tpp1::Invert) - } -} -#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpp2 { - #[doc = "0: Not inverted"] - NoInvert = 0, - #[doc = "1: Inverted"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpp2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPP2` reader - Tamper Pin n Polarity"] -pub type Tpp2R = crate::BitReader; -impl Tpp2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpp2 { - match self.bits { - false => Tpp2::NoInvert, - true => Tpp2::Invert, - } - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == Tpp2::NoInvert - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == Tpp2::Invert - } -} -#[doc = "Field `TPP2` writer - Tamper Pin n Polarity"] -pub type Tpp2W<'a, REG> = crate::BitWriter<'a, REG, Tpp2>; -impl<'a, REG> Tpp2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not inverted"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(Tpp2::NoInvert) - } - #[doc = "Inverted"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(Tpp2::Invert) - } -} -#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpp3 { - #[doc = "0: Not inverted"] - NoInvert = 0, - #[doc = "1: Inverted"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpp3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPP3` reader - Tamper Pin n Polarity"] -pub type Tpp3R = crate::BitReader; -impl Tpp3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpp3 { - match self.bits { - false => Tpp3::NoInvert, - true => Tpp3::Invert, - } - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == Tpp3::NoInvert - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == Tpp3::Invert - } -} -#[doc = "Field `TPP3` writer - Tamper Pin n Polarity"] -pub type Tpp3W<'a, REG> = crate::BitWriter<'a, REG, Tpp3>; -impl<'a, REG> Tpp3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not inverted"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(Tpp3::NoInvert) - } - #[doc = "Inverted"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(Tpp3::Invert) - } -} -#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpp4 { - #[doc = "0: Not inverted"] - NoInvert = 0, - #[doc = "1: Inverted"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpp4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPP4` reader - Tamper Pin n Polarity"] -pub type Tpp4R = crate::BitReader; -impl Tpp4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpp4 { - match self.bits { - false => Tpp4::NoInvert, - true => Tpp4::Invert, - } - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == Tpp4::NoInvert - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == Tpp4::Invert - } -} -#[doc = "Field `TPP4` writer - Tamper Pin n Polarity"] -pub type Tpp4W<'a, REG> = crate::BitWriter<'a, REG, Tpp4>; -impl<'a, REG> Tpp4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not inverted"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(Tpp4::NoInvert) - } - #[doc = "Inverted"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(Tpp4::Invert) - } -} -#[doc = "Tamper Pin n Polarity\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpp5 { - #[doc = "0: Not inverted"] - NoInvert = 0, - #[doc = "1: Inverted"] - Invert = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpp5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPP5` reader - Tamper Pin n Polarity"] -pub type Tpp5R = crate::BitReader; -impl Tpp5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpp5 { - match self.bits { - false => Tpp5::NoInvert, - true => Tpp5::Invert, - } - } - #[doc = "Not inverted"] - #[inline(always)] - pub fn is_no_invert(&self) -> bool { - *self == Tpp5::NoInvert - } - #[doc = "Inverted"] - #[inline(always)] - pub fn is_invert(&self) -> bool { - *self == Tpp5::Invert - } -} -#[doc = "Field `TPP5` writer - Tamper Pin n Polarity"] -pub type Tpp5W<'a, REG> = crate::BitWriter<'a, REG, Tpp5>; -impl<'a, REG> Tpp5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not inverted"] - #[inline(always)] - pub fn no_invert(self) -> &'a mut crate::W { - self.variant(Tpp5::NoInvert) - } - #[doc = "Inverted"] - #[inline(always)] - pub fn invert(self) -> &'a mut crate::W { - self.variant(Tpp5::Invert) - } -} -#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpid0 { - #[doc = "0: Zero"] - Zero = 0, - #[doc = "1: One"] - One = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpid0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPID0` reader - Tamper Pin n Input Data"] -pub type Tpid0R = crate::BitReader; -impl Tpid0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpid0 { - match self.bits { - false => Tpid0::Zero, - true => Tpid0::One, - } - } - #[doc = "Zero"] - #[inline(always)] - pub fn is_zero(&self) -> bool { - *self == Tpid0::Zero - } - #[doc = "One"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Tpid0::One - } -} -#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpid1 { - #[doc = "0: Zero"] - Zero = 0, - #[doc = "1: One"] - One = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpid1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPID1` reader - Tamper Pin n Input Data"] -pub type Tpid1R = crate::BitReader; -impl Tpid1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpid1 { - match self.bits { - false => Tpid1::Zero, - true => Tpid1::One, - } - } - #[doc = "Zero"] - #[inline(always)] - pub fn is_zero(&self) -> bool { - *self == Tpid1::Zero - } - #[doc = "One"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Tpid1::One - } -} -#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpid2 { - #[doc = "0: Zero"] - Zero = 0, - #[doc = "1: One"] - One = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpid2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPID2` reader - Tamper Pin n Input Data"] -pub type Tpid2R = crate::BitReader; -impl Tpid2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpid2 { - match self.bits { - false => Tpid2::Zero, - true => Tpid2::One, - } - } - #[doc = "Zero"] - #[inline(always)] - pub fn is_zero(&self) -> bool { - *self == Tpid2::Zero - } - #[doc = "One"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Tpid2::One - } -} -#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpid3 { - #[doc = "0: Zero"] - Zero = 0, - #[doc = "1: One"] - One = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpid3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPID3` reader - Tamper Pin n Input Data"] -pub type Tpid3R = crate::BitReader; -impl Tpid3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpid3 { - match self.bits { - false => Tpid3::Zero, - true => Tpid3::One, - } - } - #[doc = "Zero"] - #[inline(always)] - pub fn is_zero(&self) -> bool { - *self == Tpid3::Zero - } - #[doc = "One"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Tpid3::One - } -} -#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpid4 { - #[doc = "0: Zero"] - Zero = 0, - #[doc = "1: One"] - One = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpid4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPID4` reader - Tamper Pin n Input Data"] -pub type Tpid4R = crate::BitReader; -impl Tpid4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpid4 { - match self.bits { - false => Tpid4::Zero, - true => Tpid4::One, - } - } - #[doc = "Zero"] - #[inline(always)] - pub fn is_zero(&self) -> bool { - *self == Tpid4::Zero - } - #[doc = "One"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Tpid4::One - } -} -#[doc = "Tamper Pin n Input Data\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpid5 { - #[doc = "0: Zero"] - Zero = 0, - #[doc = "1: One"] - One = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpid5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPID5` reader - Tamper Pin n Input Data"] -pub type Tpid5R = crate::BitReader; -impl Tpid5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpid5 { - match self.bits { - false => Tpid5::Zero, - true => Tpid5::One, - } - } - #[doc = "Zero"] - #[inline(always)] - pub fn is_zero(&self) -> bool { - *self == Tpid5::Zero - } - #[doc = "One"] - #[inline(always)] - pub fn is_one(&self) -> bool { - *self == Tpid5::One - } -} -impl R { - #[doc = "Bit 0 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp0(&self) -> Tpp0R { - Tpp0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp1(&self) -> Tpp1R { - Tpp1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp2(&self) -> Tpp2R { - Tpp2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp3(&self) -> Tpp3R { - Tpp3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp4(&self) -> Tpp4R { - Tpp4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp5(&self) -> Tpp5R { - Tpp5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 16 - Tamper Pin n Input Data"] - #[inline(always)] - pub fn tpid0(&self) -> Tpid0R { - Tpid0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Tamper Pin n Input Data"] - #[inline(always)] - pub fn tpid1(&self) -> Tpid1R { - Tpid1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Tamper Pin n Input Data"] - #[inline(always)] - pub fn tpid2(&self) -> Tpid2R { - Tpid2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Tamper Pin n Input Data"] - #[inline(always)] - pub fn tpid3(&self) -> Tpid3R { - Tpid3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Tamper Pin n Input Data"] - #[inline(always)] - pub fn tpid4(&self) -> Tpid4R { - Tpid4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Tamper Pin n Input Data"] - #[inline(always)] - pub fn tpid5(&self) -> Tpid5R { - Tpid5R::new(((self.bits >> 21) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp0(&mut self) -> Tpp0W { - Tpp0W::new(self, 0) - } - #[doc = "Bit 1 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp1(&mut self) -> Tpp1W { - Tpp1W::new(self, 1) - } - #[doc = "Bit 2 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp2(&mut self) -> Tpp2W { - Tpp2W::new(self, 2) - } - #[doc = "Bit 3 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp3(&mut self) -> Tpp3W { - Tpp3W::new(self, 3) - } - #[doc = "Bit 4 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp4(&mut self) -> Tpp4W { - Tpp4W::new(self, 4) - } - #[doc = "Bit 5 - Tamper Pin n Polarity"] - #[inline(always)] - pub fn tpp5(&mut self) -> Tpp5W { - Tpp5W::new(self, 5) - } -} -#[doc = "Pin Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`ppr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ppr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PprSpec; -impl crate::RegisterSpec for PprSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ppr::R`](R) reader structure"] -impl crate::Readable for PprSpec {} -#[doc = "`write(|w| ..)` method takes [`ppr::W`](W) writer structure"] -impl crate::Writable for PprSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PPR to value 0"] -impl crate::Resettable for PprSpec {} diff --git a/mcxa276-pac/src/tdet0/sr.rs b/mcxa276-pac/src/tdet0/sr.rs deleted file mode 100644 index 583131965..000000000 --- a/mcxa276-pac/src/tdet0/sr.rs +++ /dev/null @@ -1,1219 +0,0 @@ -#[doc = "Register `SR` reader"] -pub type R = crate::R; -#[doc = "Register `SR` writer"] -pub type W = crate::W; -#[doc = "Digital Tamper Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dtf { - #[doc = "0: TDET tampering not detected"] - NoDet = 0, - #[doc = "1: TDET tampering detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dtf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DTF` reader - Digital Tamper Flag"] -pub type DtfR = crate::BitReader; -impl DtfR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dtf { - match self.bits { - false => Dtf::NoDet, - true => Dtf::Det, - } - } - #[doc = "TDET tampering not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Dtf::NoDet - } - #[doc = "TDET tampering detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Dtf::Det - } -} -#[doc = "Field `DTF` writer - Digital Tamper Flag"] -pub type DtfW<'a, REG> = crate::BitWriter1C<'a, REG, Dtf>; -impl<'a, REG> DtfW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "TDET tampering not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Dtf::NoDet) - } - #[doc = "TDET tampering detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Dtf::Det) - } -} -#[doc = "Tamper Acknowledge Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Taf { - #[doc = "0: Digital Tamper Flag (SR\\[DTF\\]) is clear or chip reset has not occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] - NotOccur = 0, - #[doc = "1: Chip reset has occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] - Occur = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Taf) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TAF` reader - Tamper Acknowledge Flag"] -pub type TafR = crate::BitReader; -impl TafR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Taf { - match self.bits { - false => Taf::NotOccur, - true => Taf::Occur, - } - } - #[doc = "Digital Tamper Flag (SR\\[DTF\\]) is clear or chip reset has not occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] - #[inline(always)] - pub fn is_not_occur(&self) -> bool { - *self == Taf::NotOccur - } - #[doc = "Chip reset has occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] - #[inline(always)] - pub fn is_occur(&self) -> bool { - *self == Taf::Occur - } -} -#[doc = "Field `TAF` writer - Tamper Acknowledge Flag"] -pub type TafW<'a, REG> = crate::BitWriter1C<'a, REG, Taf>; -impl<'a, REG> TafW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Digital Tamper Flag (SR\\[DTF\\]) is clear or chip reset has not occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] - #[inline(always)] - pub fn not_occur(self) -> &'a mut crate::W { - self.variant(Taf::NotOccur) - } - #[doc = "Chip reset has occurred after Digital Tamper Flag (SR\\[DTF\\]) was set."] - #[inline(always)] - pub fn occur(self) -> &'a mut crate::W { - self.variant(Taf::Occur) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif0 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF0` reader - Tamper Input n Flag"] -pub type Tif0R = crate::BitReader; -impl Tif0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif0 { - match self.bits { - false => Tif0::NoDet, - true => Tif0::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif0::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif0::Det - } -} -#[doc = "Field `TIF0` writer - Tamper Input n Flag"] -pub type Tif0W<'a, REG> = crate::BitWriter1C<'a, REG, Tif0>; -impl<'a, REG> Tif0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif0::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif0::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif1 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF1` reader - Tamper Input n Flag"] -pub type Tif1R = crate::BitReader; -impl Tif1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif1 { - match self.bits { - false => Tif1::NoDet, - true => Tif1::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif1::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif1::Det - } -} -#[doc = "Field `TIF1` writer - Tamper Input n Flag"] -pub type Tif1W<'a, REG> = crate::BitWriter1C<'a, REG, Tif1>; -impl<'a, REG> Tif1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif1::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif1::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif2 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF2` reader - Tamper Input n Flag"] -pub type Tif2R = crate::BitReader; -impl Tif2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif2 { - match self.bits { - false => Tif2::NoDet, - true => Tif2::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif2::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif2::Det - } -} -#[doc = "Field `TIF2` writer - Tamper Input n Flag"] -pub type Tif2W<'a, REG> = crate::BitWriter1C<'a, REG, Tif2>; -impl<'a, REG> Tif2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif2::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif2::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif3 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF3` reader - Tamper Input n Flag"] -pub type Tif3R = crate::BitReader; -impl Tif3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif3 { - match self.bits { - false => Tif3::NoDet, - true => Tif3::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif3::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif3::Det - } -} -#[doc = "Field `TIF3` writer - Tamper Input n Flag"] -pub type Tif3W<'a, REG> = crate::BitWriter1C<'a, REG, Tif3>; -impl<'a, REG> Tif3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif3::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif3::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif4 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF4` reader - Tamper Input n Flag"] -pub type Tif4R = crate::BitReader; -impl Tif4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif4 { - match self.bits { - false => Tif4::NoDet, - true => Tif4::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif4::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif4::Det - } -} -#[doc = "Field `TIF4` writer - Tamper Input n Flag"] -pub type Tif4W<'a, REG> = crate::BitWriter1C<'a, REG, Tif4>; -impl<'a, REG> Tif4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif4::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif4::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif5 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF5` reader - Tamper Input n Flag"] -pub type Tif5R = crate::BitReader; -impl Tif5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif5 { - match self.bits { - false => Tif5::NoDet, - true => Tif5::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif5::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif5::Det - } -} -#[doc = "Field `TIF5` writer - Tamper Input n Flag"] -pub type Tif5W<'a, REG> = crate::BitWriter1C<'a, REG, Tif5>; -impl<'a, REG> Tif5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif5::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif5::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif6 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF6` reader - Tamper Input n Flag"] -pub type Tif6R = crate::BitReader; -impl Tif6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif6 { - match self.bits { - false => Tif6::NoDet, - true => Tif6::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif6::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif6::Det - } -} -#[doc = "Field `TIF6` writer - Tamper Input n Flag"] -pub type Tif6W<'a, REG> = crate::BitWriter1C<'a, REG, Tif6>; -impl<'a, REG> Tif6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif6::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif6::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif7 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF7` reader - Tamper Input n Flag"] -pub type Tif7R = crate::BitReader; -impl Tif7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif7 { - match self.bits { - false => Tif7::NoDet, - true => Tif7::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif7::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif7::Det - } -} -#[doc = "Field `TIF7` writer - Tamper Input n Flag"] -pub type Tif7W<'a, REG> = crate::BitWriter1C<'a, REG, Tif7>; -impl<'a, REG> Tif7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif7::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif7::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif8 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF8` reader - Tamper Input n Flag"] -pub type Tif8R = crate::BitReader; -impl Tif8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif8 { - match self.bits { - false => Tif8::NoDet, - true => Tif8::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif8::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif8::Det - } -} -#[doc = "Field `TIF8` writer - Tamper Input n Flag"] -pub type Tif8W<'a, REG> = crate::BitWriter1C<'a, REG, Tif8>; -impl<'a, REG> Tif8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif8::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif8::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif9 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF9` reader - Tamper Input n Flag"] -pub type Tif9R = crate::BitReader; -impl Tif9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif9 { - match self.bits { - false => Tif9::NoDet, - true => Tif9::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif9::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif9::Det - } -} -#[doc = "Field `TIF9` writer - Tamper Input n Flag"] -pub type Tif9W<'a, REG> = crate::BitWriter1C<'a, REG, Tif9>; -impl<'a, REG> Tif9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif9::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif9::Det) - } -} -#[doc = "Tamper Input n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tif10 { - #[doc = "0: On-chip tamper not detected"] - NoDet = 0, - #[doc = "1: On-chip tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tif10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIF10` reader - Tamper Input n Flag"] -pub type Tif10R = crate::BitReader; -impl Tif10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tif10 { - match self.bits { - false => Tif10::NoDet, - true => Tif10::Det, - } - } - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tif10::NoDet - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tif10::Det - } -} -#[doc = "Field `TIF10` writer - Tamper Input n Flag"] -pub type Tif10W<'a, REG> = crate::BitWriter1C<'a, REG, Tif10>; -impl<'a, REG> Tif10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "On-chip tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tif10::NoDet) - } - #[doc = "On-chip tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tif10::Det) - } -} -#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpf0 { - #[doc = "0: Pin tamper not detected"] - NoDet = 0, - #[doc = "1: Pin tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpf0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPF0` reader - Tamper Pin n Flag"] -pub type Tpf0R = crate::BitReader; -impl Tpf0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpf0 { - match self.bits { - false => Tpf0::NoDet, - true => Tpf0::Det, - } - } - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tpf0::NoDet - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tpf0::Det - } -} -#[doc = "Field `TPF0` writer - Tamper Pin n Flag"] -pub type Tpf0W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf0>; -impl<'a, REG> Tpf0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tpf0::NoDet) - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tpf0::Det) - } -} -#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpf1 { - #[doc = "0: Pin tamper not detected"] - NoDet = 0, - #[doc = "1: Pin tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpf1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPF1` reader - Tamper Pin n Flag"] -pub type Tpf1R = crate::BitReader; -impl Tpf1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpf1 { - match self.bits { - false => Tpf1::NoDet, - true => Tpf1::Det, - } - } - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tpf1::NoDet - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tpf1::Det - } -} -#[doc = "Field `TPF1` writer - Tamper Pin n Flag"] -pub type Tpf1W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf1>; -impl<'a, REG> Tpf1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tpf1::NoDet) - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tpf1::Det) - } -} -#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpf2 { - #[doc = "0: Pin tamper not detected"] - NoDet = 0, - #[doc = "1: Pin tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpf2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPF2` reader - Tamper Pin n Flag"] -pub type Tpf2R = crate::BitReader; -impl Tpf2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpf2 { - match self.bits { - false => Tpf2::NoDet, - true => Tpf2::Det, - } - } - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tpf2::NoDet - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tpf2::Det - } -} -#[doc = "Field `TPF2` writer - Tamper Pin n Flag"] -pub type Tpf2W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf2>; -impl<'a, REG> Tpf2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tpf2::NoDet) - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tpf2::Det) - } -} -#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpf3 { - #[doc = "0: Pin tamper not detected"] - NoDet = 0, - #[doc = "1: Pin tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpf3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPF3` reader - Tamper Pin n Flag"] -pub type Tpf3R = crate::BitReader; -impl Tpf3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpf3 { - match self.bits { - false => Tpf3::NoDet, - true => Tpf3::Det, - } - } - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tpf3::NoDet - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tpf3::Det - } -} -#[doc = "Field `TPF3` writer - Tamper Pin n Flag"] -pub type Tpf3W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf3>; -impl<'a, REG> Tpf3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tpf3::NoDet) - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tpf3::Det) - } -} -#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpf4 { - #[doc = "0: Pin tamper not detected"] - NoDet = 0, - #[doc = "1: Pin tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpf4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPF4` reader - Tamper Pin n Flag"] -pub type Tpf4R = crate::BitReader; -impl Tpf4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpf4 { - match self.bits { - false => Tpf4::NoDet, - true => Tpf4::Det, - } - } - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tpf4::NoDet - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tpf4::Det - } -} -#[doc = "Field `TPF4` writer - Tamper Pin n Flag"] -pub type Tpf4W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf4>; -impl<'a, REG> Tpf4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tpf4::NoDet) - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tpf4::Det) - } -} -#[doc = "Tamper Pin n Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpf5 { - #[doc = "0: Pin tamper not detected"] - NoDet = 0, - #[doc = "1: Pin tamper detected"] - Det = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpf5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPF5` reader - Tamper Pin n Flag"] -pub type Tpf5R = crate::BitReader; -impl Tpf5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpf5 { - match self.bits { - false => Tpf5::NoDet, - true => Tpf5::Det, - } - } - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn is_no_det(&self) -> bool { - *self == Tpf5::NoDet - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn is_det(&self) -> bool { - *self == Tpf5::Det - } -} -#[doc = "Field `TPF5` writer - Tamper Pin n Flag"] -pub type Tpf5W<'a, REG> = crate::BitWriter1C<'a, REG, Tpf5>; -impl<'a, REG> Tpf5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Pin tamper not detected"] - #[inline(always)] - pub fn no_det(self) -> &'a mut crate::W { - self.variant(Tpf5::NoDet) - } - #[doc = "Pin tamper detected"] - #[inline(always)] - pub fn det(self) -> &'a mut crate::W { - self.variant(Tpf5::Det) - } -} -impl R { - #[doc = "Bit 0 - Digital Tamper Flag"] - #[inline(always)] - pub fn dtf(&self) -> DtfR { - DtfR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Tamper Acknowledge Flag"] - #[inline(always)] - pub fn taf(&self) -> TafR { - TafR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif0(&self) -> Tif0R { - Tif0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif1(&self) -> Tif1R { - Tif1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif2(&self) -> Tif2R { - Tif2R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif3(&self) -> Tif3R { - Tif3R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif4(&self) -> Tif4R { - Tif4R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif5(&self) -> Tif5R { - Tif5R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif6(&self) -> Tif6R { - Tif6R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif7(&self) -> Tif7R { - Tif7R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif8(&self) -> Tif8R { - Tif8R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif9(&self) -> Tif9R { - Tif9R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif10(&self) -> Tif10R { - Tif10R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 16 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf0(&self) -> Tpf0R { - Tpf0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf1(&self) -> Tpf1R { - Tpf1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf2(&self) -> Tpf2R { - Tpf2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf3(&self) -> Tpf3R { - Tpf3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf4(&self) -> Tpf4R { - Tpf4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf5(&self) -> Tpf5R { - Tpf5R::new(((self.bits >> 21) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Digital Tamper Flag"] - #[inline(always)] - pub fn dtf(&mut self) -> DtfW { - DtfW::new(self, 0) - } - #[doc = "Bit 1 - Tamper Acknowledge Flag"] - #[inline(always)] - pub fn taf(&mut self) -> TafW { - TafW::new(self, 1) - } - #[doc = "Bit 2 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif0(&mut self) -> Tif0W { - Tif0W::new(self, 2) - } - #[doc = "Bit 3 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif1(&mut self) -> Tif1W { - Tif1W::new(self, 3) - } - #[doc = "Bit 4 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif2(&mut self) -> Tif2W { - Tif2W::new(self, 4) - } - #[doc = "Bit 5 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif3(&mut self) -> Tif3W { - Tif3W::new(self, 5) - } - #[doc = "Bit 6 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif4(&mut self) -> Tif4W { - Tif4W::new(self, 6) - } - #[doc = "Bit 7 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif5(&mut self) -> Tif5W { - Tif5W::new(self, 7) - } - #[doc = "Bit 8 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif6(&mut self) -> Tif6W { - Tif6W::new(self, 8) - } - #[doc = "Bit 9 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif7(&mut self) -> Tif7W { - Tif7W::new(self, 9) - } - #[doc = "Bit 10 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif8(&mut self) -> Tif8W { - Tif8W::new(self, 10) - } - #[doc = "Bit 11 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif9(&mut self) -> Tif9W { - Tif9W::new(self, 11) - } - #[doc = "Bit 12 - Tamper Input n Flag"] - #[inline(always)] - pub fn tif10(&mut self) -> Tif10W { - Tif10W::new(self, 12) - } - #[doc = "Bit 16 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf0(&mut self) -> Tpf0W { - Tpf0W::new(self, 16) - } - #[doc = "Bit 17 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf1(&mut self) -> Tpf1W { - Tpf1W::new(self, 17) - } - #[doc = "Bit 18 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf2(&mut self) -> Tpf2W { - Tpf2W::new(self, 18) - } - #[doc = "Bit 19 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf3(&mut self) -> Tpf3W { - Tpf3W::new(self, 19) - } - #[doc = "Bit 20 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf4(&mut self) -> Tpf4W { - Tpf4W::new(self, 20) - } - #[doc = "Bit 21 - Tamper Pin n Flag"] - #[inline(always)] - pub fn tpf5(&mut self) -> Tpf5W { - Tpf5W::new(self, 21) - } -} -#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrSpec; -impl crate::RegisterSpec for SrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sr::R`](R) reader structure"] -impl crate::Readable for SrSpec {} -#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] -impl crate::Writable for SrSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x003f_1fff; -} -#[doc = "`reset()` method sets SR to value 0"] -impl crate::Resettable for SrSpec {} diff --git a/mcxa276-pac/src/tdet0/ter.rs b/mcxa276-pac/src/tdet0/ter.rs deleted file mode 100644 index f11b6e335..000000000 --- a/mcxa276-pac/src/tdet0/ter.rs +++ /dev/null @@ -1,1092 +0,0 @@ -#[doc = "Register `TER` reader"] -pub type R = crate::R; -#[doc = "Register `TER` writer"] -pub type W = crate::W; -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie0 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE0` reader - Tamper Input Enable"] -pub type Tie0R = crate::BitReader; -impl Tie0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie0 { - match self.bits { - false => Tie0::Disable, - true => Tie0::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie0::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie0::Enable - } -} -#[doc = "Field `TIE0` writer - Tamper Input Enable"] -pub type Tie0W<'a, REG> = crate::BitWriter<'a, REG, Tie0>; -impl<'a, REG> Tie0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie0::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie0::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie1 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE1` reader - Tamper Input Enable"] -pub type Tie1R = crate::BitReader; -impl Tie1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie1 { - match self.bits { - false => Tie1::Disable, - true => Tie1::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie1::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie1::Enable - } -} -#[doc = "Field `TIE1` writer - Tamper Input Enable"] -pub type Tie1W<'a, REG> = crate::BitWriter<'a, REG, Tie1>; -impl<'a, REG> Tie1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie1::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie1::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie2 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE2` reader - Tamper Input Enable"] -pub type Tie2R = crate::BitReader; -impl Tie2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie2 { - match self.bits { - false => Tie2::Disable, - true => Tie2::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie2::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie2::Enable - } -} -#[doc = "Field `TIE2` writer - Tamper Input Enable"] -pub type Tie2W<'a, REG> = crate::BitWriter<'a, REG, Tie2>; -impl<'a, REG> Tie2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie2::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie2::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie3 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE3` reader - Tamper Input Enable"] -pub type Tie3R = crate::BitReader; -impl Tie3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie3 { - match self.bits { - false => Tie3::Disable, - true => Tie3::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie3::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie3::Enable - } -} -#[doc = "Field `TIE3` writer - Tamper Input Enable"] -pub type Tie3W<'a, REG> = crate::BitWriter<'a, REG, Tie3>; -impl<'a, REG> Tie3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie3::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie3::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie4 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE4` reader - Tamper Input Enable"] -pub type Tie4R = crate::BitReader; -impl Tie4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie4 { - match self.bits { - false => Tie4::Disable, - true => Tie4::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie4::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie4::Enable - } -} -#[doc = "Field `TIE4` writer - Tamper Input Enable"] -pub type Tie4W<'a, REG> = crate::BitWriter<'a, REG, Tie4>; -impl<'a, REG> Tie4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie4::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie4::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie5 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE5` reader - Tamper Input Enable"] -pub type Tie5R = crate::BitReader; -impl Tie5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie5 { - match self.bits { - false => Tie5::Disable, - true => Tie5::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie5::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie5::Enable - } -} -#[doc = "Field `TIE5` writer - Tamper Input Enable"] -pub type Tie5W<'a, REG> = crate::BitWriter<'a, REG, Tie5>; -impl<'a, REG> Tie5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie5::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie5::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie6 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE6` reader - Tamper Input Enable"] -pub type Tie6R = crate::BitReader; -impl Tie6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie6 { - match self.bits { - false => Tie6::Disable, - true => Tie6::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie6::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie6::Enable - } -} -#[doc = "Field `TIE6` writer - Tamper Input Enable"] -pub type Tie6W<'a, REG> = crate::BitWriter<'a, REG, Tie6>; -impl<'a, REG> Tie6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie6::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie6::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie7 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE7` reader - Tamper Input Enable"] -pub type Tie7R = crate::BitReader; -impl Tie7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie7 { - match self.bits { - false => Tie7::Disable, - true => Tie7::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie7::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie7::Enable - } -} -#[doc = "Field `TIE7` writer - Tamper Input Enable"] -pub type Tie7W<'a, REG> = crate::BitWriter<'a, REG, Tie7>; -impl<'a, REG> Tie7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie7::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie7::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie8 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE8` reader - Tamper Input Enable"] -pub type Tie8R = crate::BitReader; -impl Tie8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie8 { - match self.bits { - false => Tie8::Disable, - true => Tie8::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie8::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie8::Enable - } -} -#[doc = "Field `TIE8` writer - Tamper Input Enable"] -pub type Tie8W<'a, REG> = crate::BitWriter<'a, REG, Tie8>; -impl<'a, REG> Tie8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie8::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie8::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie9 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE9` reader - Tamper Input Enable"] -pub type Tie9R = crate::BitReader; -impl Tie9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie9 { - match self.bits { - false => Tie9::Disable, - true => Tie9::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie9::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie9::Enable - } -} -#[doc = "Field `TIE9` writer - Tamper Input Enable"] -pub type Tie9W<'a, REG> = crate::BitWriter<'a, REG, Tie9>; -impl<'a, REG> Tie9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie9::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie9::Enable) - } -} -#[doc = "Tamper Input Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tie10 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tie10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TIE10` reader - Tamper Input Enable"] -pub type Tie10R = crate::BitReader; -impl Tie10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tie10 { - match self.bits { - false => Tie10::Disable, - true => Tie10::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tie10::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tie10::Enable - } -} -#[doc = "Field `TIE10` writer - Tamper Input Enable"] -pub type Tie10W<'a, REG> = crate::BitWriter<'a, REG, Tie10>; -impl<'a, REG> Tie10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tie10::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tie10::Enable) - } -} -#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpe0 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpe0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPE0` reader - Tamper Pin Enable"] -pub type Tpe0R = crate::BitReader; -impl Tpe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpe0 { - match self.bits { - false => Tpe0::Disable, - true => Tpe0::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpe0::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpe0::Enable - } -} -#[doc = "Field `TPE0` writer - Tamper Pin Enable"] -pub type Tpe0W<'a, REG> = crate::BitWriter<'a, REG, Tpe0>; -impl<'a, REG> Tpe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpe0::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpe0::Enable) - } -} -#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpe1 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpe1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPE1` reader - Tamper Pin Enable"] -pub type Tpe1R = crate::BitReader; -impl Tpe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpe1 { - match self.bits { - false => Tpe1::Disable, - true => Tpe1::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpe1::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpe1::Enable - } -} -#[doc = "Field `TPE1` writer - Tamper Pin Enable"] -pub type Tpe1W<'a, REG> = crate::BitWriter<'a, REG, Tpe1>; -impl<'a, REG> Tpe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpe1::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpe1::Enable) - } -} -#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpe2 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpe2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPE2` reader - Tamper Pin Enable"] -pub type Tpe2R = crate::BitReader; -impl Tpe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpe2 { - match self.bits { - false => Tpe2::Disable, - true => Tpe2::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpe2::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpe2::Enable - } -} -#[doc = "Field `TPE2` writer - Tamper Pin Enable"] -pub type Tpe2W<'a, REG> = crate::BitWriter<'a, REG, Tpe2>; -impl<'a, REG> Tpe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpe2::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpe2::Enable) - } -} -#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpe3 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpe3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPE3` reader - Tamper Pin Enable"] -pub type Tpe3R = crate::BitReader; -impl Tpe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpe3 { - match self.bits { - false => Tpe3::Disable, - true => Tpe3::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpe3::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpe3::Enable - } -} -#[doc = "Field `TPE3` writer - Tamper Pin Enable"] -pub type Tpe3W<'a, REG> = crate::BitWriter<'a, REG, Tpe3>; -impl<'a, REG> Tpe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpe3::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpe3::Enable) - } -} -#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpe4 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpe4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPE4` reader - Tamper Pin Enable"] -pub type Tpe4R = crate::BitReader; -impl Tpe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpe4 { - match self.bits { - false => Tpe4::Disable, - true => Tpe4::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpe4::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpe4::Enable - } -} -#[doc = "Field `TPE4` writer - Tamper Pin Enable"] -pub type Tpe4W<'a, REG> = crate::BitWriter<'a, REG, Tpe4>; -impl<'a, REG> Tpe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpe4::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpe4::Enable) - } -} -#[doc = "Tamper Pin Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tpe5 { - #[doc = "0: Disables"] - Disable = 0, - #[doc = "1: Enables"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tpe5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TPE5` reader - Tamper Pin Enable"] -pub type Tpe5R = crate::BitReader; -impl Tpe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tpe5 { - match self.bits { - false => Tpe5::Disable, - true => Tpe5::Enable, - } - } - #[doc = "Disables"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tpe5::Disable - } - #[doc = "Enables"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tpe5::Enable - } -} -#[doc = "Field `TPE5` writer - Tamper Pin Enable"] -pub type Tpe5W<'a, REG> = crate::BitWriter<'a, REG, Tpe5>; -impl<'a, REG> Tpe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disables"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Tpe5::Disable) - } - #[doc = "Enables"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Tpe5::Enable) - } -} -impl R { - #[doc = "Bit 2 - Tamper Input Enable"] - #[inline(always)] - pub fn tie0(&self) -> Tie0R { - Tie0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Tamper Input Enable"] - #[inline(always)] - pub fn tie1(&self) -> Tie1R { - Tie1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Tamper Input Enable"] - #[inline(always)] - pub fn tie2(&self) -> Tie2R { - Tie2R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Tamper Input Enable"] - #[inline(always)] - pub fn tie3(&self) -> Tie3R { - Tie3R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Tamper Input Enable"] - #[inline(always)] - pub fn tie4(&self) -> Tie4R { - Tie4R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Tamper Input Enable"] - #[inline(always)] - pub fn tie5(&self) -> Tie5R { - Tie5R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Tamper Input Enable"] - #[inline(always)] - pub fn tie6(&self) -> Tie6R { - Tie6R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Tamper Input Enable"] - #[inline(always)] - pub fn tie7(&self) -> Tie7R { - Tie7R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Tamper Input Enable"] - #[inline(always)] - pub fn tie8(&self) -> Tie8R { - Tie8R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Tamper Input Enable"] - #[inline(always)] - pub fn tie9(&self) -> Tie9R { - Tie9R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Tamper Input Enable"] - #[inline(always)] - pub fn tie10(&self) -> Tie10R { - Tie10R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 16 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe0(&self) -> Tpe0R { - Tpe0R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe1(&self) -> Tpe1R { - Tpe1R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe2(&self) -> Tpe2R { - Tpe2R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe3(&self) -> Tpe3R { - Tpe3R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe4(&self) -> Tpe4R { - Tpe4R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe5(&self) -> Tpe5R { - Tpe5R::new(((self.bits >> 21) & 1) != 0) - } -} -impl W { - #[doc = "Bit 2 - Tamper Input Enable"] - #[inline(always)] - pub fn tie0(&mut self) -> Tie0W { - Tie0W::new(self, 2) - } - #[doc = "Bit 3 - Tamper Input Enable"] - #[inline(always)] - pub fn tie1(&mut self) -> Tie1W { - Tie1W::new(self, 3) - } - #[doc = "Bit 4 - Tamper Input Enable"] - #[inline(always)] - pub fn tie2(&mut self) -> Tie2W { - Tie2W::new(self, 4) - } - #[doc = "Bit 5 - Tamper Input Enable"] - #[inline(always)] - pub fn tie3(&mut self) -> Tie3W { - Tie3W::new(self, 5) - } - #[doc = "Bit 6 - Tamper Input Enable"] - #[inline(always)] - pub fn tie4(&mut self) -> Tie4W { - Tie4W::new(self, 6) - } - #[doc = "Bit 7 - Tamper Input Enable"] - #[inline(always)] - pub fn tie5(&mut self) -> Tie5W { - Tie5W::new(self, 7) - } - #[doc = "Bit 8 - Tamper Input Enable"] - #[inline(always)] - pub fn tie6(&mut self) -> Tie6W { - Tie6W::new(self, 8) - } - #[doc = "Bit 9 - Tamper Input Enable"] - #[inline(always)] - pub fn tie7(&mut self) -> Tie7W { - Tie7W::new(self, 9) - } - #[doc = "Bit 10 - Tamper Input Enable"] - #[inline(always)] - pub fn tie8(&mut self) -> Tie8W { - Tie8W::new(self, 10) - } - #[doc = "Bit 11 - Tamper Input Enable"] - #[inline(always)] - pub fn tie9(&mut self) -> Tie9W { - Tie9W::new(self, 11) - } - #[doc = "Bit 12 - Tamper Input Enable"] - #[inline(always)] - pub fn tie10(&mut self) -> Tie10W { - Tie10W::new(self, 12) - } - #[doc = "Bit 16 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe0(&mut self) -> Tpe0W { - Tpe0W::new(self, 16) - } - #[doc = "Bit 17 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe1(&mut self) -> Tpe1W { - Tpe1W::new(self, 17) - } - #[doc = "Bit 18 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe2(&mut self) -> Tpe2W { - Tpe2W::new(self, 18) - } - #[doc = "Bit 19 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe3(&mut self) -> Tpe3W { - Tpe3W::new(self, 19) - } - #[doc = "Bit 20 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe4(&mut self) -> Tpe4W { - Tpe4W::new(self, 20) - } - #[doc = "Bit 21 - Tamper Pin Enable"] - #[inline(always)] - pub fn tpe5(&mut self) -> Tpe5W { - Tpe5W::new(self, 21) - } -} -#[doc = "Tamper Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TerSpec; -impl crate::RegisterSpec for TerSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ter::R`](R) reader structure"] -impl crate::Readable for TerSpec {} -#[doc = "`write(|w| ..)` method takes [`ter::W`](W) writer structure"] -impl crate::Writable for TerSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TER to value 0"] -impl crate::Resettable for TerSpec {} diff --git a/mcxa276-pac/src/tdet0/tsr.rs b/mcxa276-pac/src/tdet0/tsr.rs deleted file mode 100644 index 3578e3f4a..000000000 --- a/mcxa276-pac/src/tdet0/tsr.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `TSR` reader"] -pub type R = crate::R; -#[doc = "Register `TSR` writer"] -pub type W = crate::W; -#[doc = "Field `TTS` reader - Tamper Time Seconds"] -pub type TtsR = crate::FieldReader; -#[doc = "Field `TTS` writer - Tamper Time Seconds"] -pub type TtsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Tamper Time Seconds"] - #[inline(always)] - pub fn tts(&self) -> TtsR { - TtsR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Tamper Time Seconds"] - #[inline(always)] - pub fn tts(&mut self) -> TtsW { - TtsW::new(self, 0) - } -} -#[doc = "Tamper Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`tsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TsrSpec; -impl crate::RegisterSpec for TsrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tsr::R`](R) reader structure"] -impl crate::Readable for TsrSpec {} -#[doc = "`write(|w| ..)` method takes [`tsr::W`](W) writer structure"] -impl crate::Writable for TsrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TSR to value 0"] -impl crate::Resettable for TsrSpec {} diff --git a/mcxa276-pac/src/trng0.rs b/mcxa276-pac/src/trng0.rs deleted file mode 100644 index 84db31724..000000000 --- a/mcxa276-pac/src/trng0.rs +++ /dev/null @@ -1,492 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - mctl: Mctl, - scmisc: Scmisc, - pkrrng: Pkrrng, - _reserved_3_pkrsq_pkrsq: [u8; 0x04], - sdctl: Sdctl, - _reserved_5_sblim_sblim: [u8; 0x04], - _reserved_6_frqmin_frqmin: [u8; 0x04], - _reserved_7_frqcnt_frqcnt: [u8; 0x04], - _reserved_8_scmc_scmc: [u8; 0x04], - _reserved_9_scr: [u8; 0x04], - _reserved_10_scr: [u8; 0x04], - _reserved_11_scr: [u8; 0x04], - _reserved_12_scr: [u8; 0x04], - _reserved_13_scr: [u8; 0x04], - _reserved_14_scr: [u8; 0x04], - status: Status, - ent0: Ent0, - _reserved17: [u8; 0x3c], - pkrcnt10: Pkrcnt10, - pkrcnt32: Pkrcnt32, - pkrcnt54: Pkrcnt54, - pkrcnt76: Pkrcnt76, - pkrcnt98: Pkrcnt98, - pkrcntba: Pkrcntba, - pkrcntdc: Pkrcntdc, - pkrcntfe: Pkrcntfe, - sec_cfg: SecCfg, - int_ctrl: IntCtrl, - int_mask: IntMask, - int_status: IntStatus, - cser: Cser, - csclr: Csclr, - _reserved31: [u8; 0x34], - osc2_ctl: Osc2Ctl, - vid1: Vid1, - vid2: Vid2, -} -impl RegisterBlock { - #[doc = "0x00 - Miscellaneous Control Register"] - #[inline(always)] - pub const fn mctl(&self) -> &Mctl { - &self.mctl - } - #[doc = "0x04 - Statistical Check Miscellaneous Register"] - #[inline(always)] - pub const fn scmisc(&self) -> &Scmisc { - &self.scmisc - } - #[doc = "0x08 - Poker Range Register"] - #[inline(always)] - pub const fn pkrrng(&self) -> &Pkrrng { - &self.pkrrng - } - #[doc = "0x0c - Poker Square Calculation Result Register"] - #[inline(always)] - pub const fn pkrsq_pkrsq(&self) -> &PkrsqPkrsq { - unsafe { &*core::ptr::from_ref(self).cast::().add(12).cast() } - } - #[doc = "0x0c - Poker Maximum Limit Register"] - #[inline(always)] - pub const fn pkrmax_pkrmax(&self) -> &PkrmaxPkrmax { - unsafe { &*core::ptr::from_ref(self).cast::().add(12).cast() } - } - #[doc = "0x10 - Seed Control Register"] - #[inline(always)] - pub const fn sdctl(&self) -> &Sdctl { - &self.sdctl - } - #[doc = "0x14 - Total Samples Register"] - #[inline(always)] - pub const fn totsam_totsam(&self) -> &TotsamTotsam { - unsafe { &*core::ptr::from_ref(self).cast::().add(20).cast() } - } - #[doc = "0x14 - Sparse Bit Limit Register"] - #[inline(always)] - pub const fn sblim_sblim(&self) -> &SblimSblim { - unsafe { &*core::ptr::from_ref(self).cast::().add(20).cast() } - } - #[doc = "0x18 - Oscillator-2 Frequency Count Register"] - #[inline(always)] - pub const fn osc2_frqcnt_osc2_frqcnt(&self) -> &Osc2FrqcntOsc2Frqcnt { - unsafe { &*core::ptr::from_ref(self).cast::().add(24).cast() } - } - #[doc = "0x18 - Frequency Count Minimum Limit Register"] - #[inline(always)] - pub const fn frqmin_frqmin(&self) -> &FrqminFrqmin { - unsafe { &*core::ptr::from_ref(self).cast::().add(24).cast() } - } - #[doc = "0x1c - Frequency Count Maximum Limit Register"] - #[inline(always)] - pub const fn frqmax_frqmax(&self) -> &FrqmaxFrqmax { - unsafe { &*core::ptr::from_ref(self).cast::().add(28).cast() } - } - #[doc = "0x1c - Frequency Count Register"] - #[inline(always)] - pub const fn frqcnt_frqcnt(&self) -> &FrqcntFrqcnt { - unsafe { &*core::ptr::from_ref(self).cast::().add(28).cast() } - } - #[doc = "0x20 - Statistical Check Monobit Limit Register"] - #[inline(always)] - pub const fn scml_scml(&self) -> &ScmlScml { - unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } - } - #[doc = "0x20 - Statistical Check Monobit Count Register"] - #[inline(always)] - pub const fn scmc_scmc(&self) -> &ScmcScmc { - unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } - } - #[doc = "0x24 - Statistical Check Run Length 1 Limit Register"] - #[inline(always)] - pub const fn scr1l_scr1l(&self) -> &Scr1lScr1l { - unsafe { &*core::ptr::from_ref(self).cast::().add(36).cast() } - } - #[doc = "0x24 - Statistical Check Run Length 1 Count Register"] - #[inline(always)] - pub const fn scr1c_scr1c(&self) -> &Scr1cScr1c { - unsafe { &*core::ptr::from_ref(self).cast::().add(36).cast() } - } - #[doc = "0x28 - Statistical Check Run Length 2 Limit Register"] - #[inline(always)] - pub const fn scr2l_scr2l(&self) -> &Scr2lScr2l { - unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } - } - #[doc = "0x28 - Statistical Check Run Length 2 Count Register"] - #[inline(always)] - pub const fn scr2c_scr2c(&self) -> &Scr2cScr2c { - unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } - } - #[doc = "0x2c - Statistical Check Run Length 3 Limit Register"] - #[inline(always)] - pub const fn scr3l_scr3l(&self) -> &Scr3lScr3l { - unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } - } - #[doc = "0x2c - Statistical Check Run Length 3 Count Register"] - #[inline(always)] - pub const fn scr3c_scr3c(&self) -> &Scr3cScr3c { - unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } - } - #[doc = "0x30 - Statistical Check Run Length 4 Limit Register"] - #[inline(always)] - pub const fn scr4l_scr4l(&self) -> &Scr4lScr4l { - unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } - } - #[doc = "0x30 - Statistical Check Run Length 4 Count Register"] - #[inline(always)] - pub const fn scr4c_scr4c(&self) -> &Scr4cScr4c { - unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } - } - #[doc = "0x34 - Statistical Check Run Length 5 Limit Register"] - #[inline(always)] - pub const fn scr5l_scr5l(&self) -> &Scr5lScr5l { - unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } - } - #[doc = "0x34 - Statistical Check Run Length 5 Count Register"] - #[inline(always)] - pub const fn scr5c_scr5c(&self) -> &Scr5cScr5c { - unsafe { &*core::ptr::from_ref(self).cast::().add(52).cast() } - } - #[doc = "0x38 - Statistical Check Run Length 6+ Limit Register"] - #[inline(always)] - pub const fn scr6pl_scr6pl(&self) -> &Scr6plScr6pl { - unsafe { &*core::ptr::from_ref(self).cast::().add(56).cast() } - } - #[doc = "0x38 - Statistical Check Run Length 6+ Count Register"] - #[inline(always)] - pub const fn scr6pc_scr6pc(&self) -> &Scr6pcScr6pc { - unsafe { &*core::ptr::from_ref(self).cast::().add(56).cast() } - } - #[doc = "0x3c - Status Register"] - #[inline(always)] - pub const fn status(&self) -> &Status { - &self.status - } - #[doc = "0x40 - Entropy Read Register"] - #[inline(always)] - pub const fn ent0(&self) -> &Ent0 { - &self.ent0 - } - #[doc = "0x80 - Statistical Check Poker Count 1 and 0 Register"] - #[inline(always)] - pub const fn pkrcnt10(&self) -> &Pkrcnt10 { - &self.pkrcnt10 - } - #[doc = "0x84 - Statistical Check Poker Count 3 and 2 Register"] - #[inline(always)] - pub const fn pkrcnt32(&self) -> &Pkrcnt32 { - &self.pkrcnt32 - } - #[doc = "0x88 - Statistical Check Poker Count 5 and 4 Register"] - #[inline(always)] - pub const fn pkrcnt54(&self) -> &Pkrcnt54 { - &self.pkrcnt54 - } - #[doc = "0x8c - Statistical Check Poker Count 7 and 6 Register"] - #[inline(always)] - pub const fn pkrcnt76(&self) -> &Pkrcnt76 { - &self.pkrcnt76 - } - #[doc = "0x90 - Statistical Check Poker Count 9 and 8 Register"] - #[inline(always)] - pub const fn pkrcnt98(&self) -> &Pkrcnt98 { - &self.pkrcnt98 - } - #[doc = "0x94 - Statistical Check Poker Count B and A Register"] - #[inline(always)] - pub const fn pkrcntba(&self) -> &Pkrcntba { - &self.pkrcntba - } - #[doc = "0x98 - Statistical Check Poker Count D and C Register"] - #[inline(always)] - pub const fn pkrcntdc(&self) -> &Pkrcntdc { - &self.pkrcntdc - } - #[doc = "0x9c - Statistical Check Poker Count F and E Register"] - #[inline(always)] - pub const fn pkrcntfe(&self) -> &Pkrcntfe { - &self.pkrcntfe - } - #[doc = "0xa0 - Security Configuration Register"] - #[inline(always)] - pub const fn sec_cfg(&self) -> &SecCfg { - &self.sec_cfg - } - #[doc = "0xa4 - Interrupt Control Register"] - #[inline(always)] - pub const fn int_ctrl(&self) -> &IntCtrl { - &self.int_ctrl - } - #[doc = "0xa8 - Mask Register"] - #[inline(always)] - pub const fn int_mask(&self) -> &IntMask { - &self.int_mask - } - #[doc = "0xac - Interrupt Status Register"] - #[inline(always)] - pub const fn int_status(&self) -> &IntStatus { - &self.int_status - } - #[doc = "0xb0 - Common Security Error Register"] - #[inline(always)] - pub const fn cser(&self) -> &Cser { - &self.cser - } - #[doc = "0xb4 - Common Security Clear Register"] - #[inline(always)] - pub const fn csclr(&self) -> &Csclr { - &self.csclr - } - #[doc = "0xec - TRNG Oscillator 2 Control Register"] - #[inline(always)] - pub const fn osc2_ctl(&self) -> &Osc2Ctl { - &self.osc2_ctl - } - #[doc = "0xf0 - Version ID Register (MS)"] - #[inline(always)] - pub const fn vid1(&self) -> &Vid1 { - &self.vid1 - } - #[doc = "0xf4 - Version ID Register (LS)"] - #[inline(always)] - pub const fn vid2(&self) -> &Vid2 { - &self.vid2 - } -} -#[doc = "MCTL (rw) register accessor: Miscellaneous Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctl`] module"] -#[doc(alias = "MCTL")] -pub type Mctl = crate::Reg; -#[doc = "Miscellaneous Control Register"] -pub mod mctl; -#[doc = "SCMISC (rw) register accessor: Statistical Check Miscellaneous Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmisc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scmisc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scmisc`] module"] -#[doc(alias = "SCMISC")] -pub type Scmisc = crate::Reg; -#[doc = "Statistical Check Miscellaneous Register"] -pub mod scmisc; -#[doc = "PKRRNG (rw) register accessor: Poker Range Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrrng::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrrng::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrrng`] module"] -#[doc(alias = "PKRRNG")] -pub type Pkrrng = crate::Reg; -#[doc = "Poker Range Register"] -pub mod pkrrng; -#[doc = "PKRMAX_PKRMAX (rw) register accessor: Poker Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrmax_pkrmax::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrmax_pkrmax::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrmax_pkrmax`] module"] -#[doc(alias = "PKRMAX_PKRMAX")] -pub type PkrmaxPkrmax = crate::Reg; -#[doc = "Poker Maximum Limit Register"] -pub mod pkrmax_pkrmax; -#[doc = "PKRSQ_PKRSQ (r) register accessor: Poker Square Calculation Result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrsq_pkrsq::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrsq_pkrsq`] module"] -#[doc(alias = "PKRSQ_PKRSQ")] -pub type PkrsqPkrsq = crate::Reg; -#[doc = "Poker Square Calculation Result Register"] -pub mod pkrsq_pkrsq; -#[doc = "SDCTL (rw) register accessor: Seed Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdctl`] module"] -#[doc(alias = "SDCTL")] -pub type Sdctl = crate::Reg; -#[doc = "Seed Control Register"] -pub mod sdctl; -#[doc = "SBLIM_SBLIM (rw) register accessor: Sparse Bit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sblim_sblim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sblim_sblim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sblim_sblim`] module"] -#[doc(alias = "SBLIM_SBLIM")] -pub type SblimSblim = crate::Reg; -#[doc = "Sparse Bit Limit Register"] -pub mod sblim_sblim; -#[doc = "TOTSAM_TOTSAM (r) register accessor: Total Samples Register\n\nYou can [`read`](crate::Reg::read) this register and get [`totsam_totsam::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@totsam_totsam`] module"] -#[doc(alias = "TOTSAM_TOTSAM")] -pub type TotsamTotsam = crate::Reg; -#[doc = "Total Samples Register"] -pub mod totsam_totsam; -#[doc = "FRQMIN_FRQMIN (rw) register accessor: Frequency Count Minimum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmin_frqmin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmin_frqmin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqmin_frqmin`] module"] -#[doc(alias = "FRQMIN_FRQMIN")] -pub type FrqminFrqmin = crate::Reg; -#[doc = "Frequency Count Minimum Limit Register"] -pub mod frqmin_frqmin; -#[doc = "OSC2_FRQCNT_OSC2_FRQCNT (r) register accessor: Oscillator-2 Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_frqcnt_osc2_frqcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc2_frqcnt_osc2_frqcnt`] module"] -#[doc(alias = "OSC2_FRQCNT_OSC2_FRQCNT")] -pub type Osc2FrqcntOsc2Frqcnt = crate::Reg; -#[doc = "Oscillator-2 Frequency Count Register"] -pub mod osc2_frqcnt_osc2_frqcnt; -#[doc = "FRQCNT_FRQCNT (r) register accessor: Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqcnt_frqcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqcnt_frqcnt`] module"] -#[doc(alias = "FRQCNT_FRQCNT")] -pub type FrqcntFrqcnt = crate::Reg; -#[doc = "Frequency Count Register"] -pub mod frqcnt_frqcnt; -#[doc = "FRQMAX_FRQMAX (rw) register accessor: Frequency Count Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmax_frqmax::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmax_frqmax::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frqmax_frqmax`] module"] -#[doc(alias = "FRQMAX_FRQMAX")] -pub type FrqmaxFrqmax = crate::Reg; -#[doc = "Frequency Count Maximum Limit Register"] -pub mod frqmax_frqmax; -#[doc = "SCMC_SCMC (r) register accessor: Statistical Check Monobit Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmc_scmc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scmc_scmc`] module"] -#[doc(alias = "SCMC_SCMC")] -pub type ScmcScmc = crate::Reg; -#[doc = "Statistical Check Monobit Count Register"] -pub mod scmc_scmc; -#[doc = "SCML_SCML (rw) register accessor: Statistical Check Monobit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scml_scml::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scml_scml::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scml_scml`] module"] -#[doc(alias = "SCML_SCML")] -pub type ScmlScml = crate::Reg; -#[doc = "Statistical Check Monobit Limit Register"] -pub mod scml_scml; -#[doc = "SCR1C_SCR1C (r) register accessor: Statistical Check Run Length 1 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1c_scr1c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr1c_scr1c`] module"] -#[doc(alias = "SCR1C_SCR1C")] -pub type Scr1cScr1c = crate::Reg; -#[doc = "Statistical Check Run Length 1 Count Register"] -pub mod scr1c_scr1c; -#[doc = "SCR1L_SCR1L (rw) register accessor: Statistical Check Run Length 1 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1l_scr1l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr1l_scr1l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr1l_scr1l`] module"] -#[doc(alias = "SCR1L_SCR1L")] -pub type Scr1lScr1l = crate::Reg; -#[doc = "Statistical Check Run Length 1 Limit Register"] -pub mod scr1l_scr1l; -#[doc = "SCR2C_SCR2C (r) register accessor: Statistical Check Run Length 2 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2c_scr2c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr2c_scr2c`] module"] -#[doc(alias = "SCR2C_SCR2C")] -pub type Scr2cScr2c = crate::Reg; -#[doc = "Statistical Check Run Length 2 Count Register"] -pub mod scr2c_scr2c; -#[doc = "SCR2L_SCR2L (rw) register accessor: Statistical Check Run Length 2 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2l_scr2l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr2l_scr2l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr2l_scr2l`] module"] -#[doc(alias = "SCR2L_SCR2L")] -pub type Scr2lScr2l = crate::Reg; -#[doc = "Statistical Check Run Length 2 Limit Register"] -pub mod scr2l_scr2l; -#[doc = "SCR3C_SCR3C (r) register accessor: Statistical Check Run Length 3 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3c_scr3c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr3c_scr3c`] module"] -#[doc(alias = "SCR3C_SCR3C")] -pub type Scr3cScr3c = crate::Reg; -#[doc = "Statistical Check Run Length 3 Count Register"] -pub mod scr3c_scr3c; -#[doc = "SCR3L_SCR3L (rw) register accessor: Statistical Check Run Length 3 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3l_scr3l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr3l_scr3l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr3l_scr3l`] module"] -#[doc(alias = "SCR3L_SCR3L")] -pub type Scr3lScr3l = crate::Reg; -#[doc = "Statistical Check Run Length 3 Limit Register"] -pub mod scr3l_scr3l; -#[doc = "SCR4C_SCR4C (r) register accessor: Statistical Check Run Length 4 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4c_scr4c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr4c_scr4c`] module"] -#[doc(alias = "SCR4C_SCR4C")] -pub type Scr4cScr4c = crate::Reg; -#[doc = "Statistical Check Run Length 4 Count Register"] -pub mod scr4c_scr4c; -#[doc = "SCR4L_SCR4L (rw) register accessor: Statistical Check Run Length 4 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4l_scr4l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr4l_scr4l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr4l_scr4l`] module"] -#[doc(alias = "SCR4L_SCR4L")] -pub type Scr4lScr4l = crate::Reg; -#[doc = "Statistical Check Run Length 4 Limit Register"] -pub mod scr4l_scr4l; -#[doc = "SCR5C_SCR5C (r) register accessor: Statistical Check Run Length 5 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5c_scr5c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr5c_scr5c`] module"] -#[doc(alias = "SCR5C_SCR5C")] -pub type Scr5cScr5c = crate::Reg; -#[doc = "Statistical Check Run Length 5 Count Register"] -pub mod scr5c_scr5c; -#[doc = "SCR5L_SCR5L (rw) register accessor: Statistical Check Run Length 5 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5l_scr5l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr5l_scr5l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr5l_scr5l`] module"] -#[doc(alias = "SCR5L_SCR5L")] -pub type Scr5lScr5l = crate::Reg; -#[doc = "Statistical Check Run Length 5 Limit Register"] -pub mod scr5l_scr5l; -#[doc = "SCR6PC_SCR6PC (r) register accessor: Statistical Check Run Length 6+ Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pc_scr6pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr6pc_scr6pc`] module"] -#[doc(alias = "SCR6PC_SCR6PC")] -pub type Scr6pcScr6pc = crate::Reg; -#[doc = "Statistical Check Run Length 6+ Count Register"] -pub mod scr6pc_scr6pc; -#[doc = "SCR6PL_SCR6PL (rw) register accessor: Statistical Check Run Length 6+ Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pl_scr6pl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr6pl_scr6pl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr6pl_scr6pl`] module"] -#[doc(alias = "SCR6PL_SCR6PL")] -pub type Scr6plScr6pl = crate::Reg; -#[doc = "Statistical Check Run Length 6+ Limit Register"] -pub mod scr6pl_scr6pl; -#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] -#[doc(alias = "STATUS")] -pub type Status = crate::Reg; -#[doc = "Status Register"] -pub mod status; -#[doc = "ENT0 (r) register accessor: Entropy Read Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ent0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ent0`] module"] -#[doc(alias = "ENT0")] -pub type Ent0 = crate::Reg; -#[doc = "Entropy Read Register"] -pub mod ent0; -#[doc = "PKRCNT10 (r) register accessor: Statistical Check Poker Count 1 and 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt10`] module"] -#[doc(alias = "PKRCNT10")] -pub type Pkrcnt10 = crate::Reg; -#[doc = "Statistical Check Poker Count 1 and 0 Register"] -pub mod pkrcnt10; -#[doc = "PKRCNT32 (r) register accessor: Statistical Check Poker Count 3 and 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt32::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt32`] module"] -#[doc(alias = "PKRCNT32")] -pub type Pkrcnt32 = crate::Reg; -#[doc = "Statistical Check Poker Count 3 and 2 Register"] -pub mod pkrcnt32; -#[doc = "PKRCNT54 (r) register accessor: Statistical Check Poker Count 5 and 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt54::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt54`] module"] -#[doc(alias = "PKRCNT54")] -pub type Pkrcnt54 = crate::Reg; -#[doc = "Statistical Check Poker Count 5 and 4 Register"] -pub mod pkrcnt54; -#[doc = "PKRCNT76 (r) register accessor: Statistical Check Poker Count 7 and 6 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt76::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt76`] module"] -#[doc(alias = "PKRCNT76")] -pub type Pkrcnt76 = crate::Reg; -#[doc = "Statistical Check Poker Count 7 and 6 Register"] -pub mod pkrcnt76; -#[doc = "PKRCNT98 (r) register accessor: Statistical Check Poker Count 9 and 8 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt98::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcnt98`] module"] -#[doc(alias = "PKRCNT98")] -pub type Pkrcnt98 = crate::Reg; -#[doc = "Statistical Check Poker Count 9 and 8 Register"] -pub mod pkrcnt98; -#[doc = "PKRCNTBA (r) register accessor: Statistical Check Poker Count B and A Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntba::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntba`] module"] -#[doc(alias = "PKRCNTBA")] -pub type Pkrcntba = crate::Reg; -#[doc = "Statistical Check Poker Count B and A Register"] -pub mod pkrcntba; -#[doc = "PKRCNTDC (r) register accessor: Statistical Check Poker Count D and C Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntdc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntdc`] module"] -#[doc(alias = "PKRCNTDC")] -pub type Pkrcntdc = crate::Reg; -#[doc = "Statistical Check Poker Count D and C Register"] -pub mod pkrcntdc; -#[doc = "PKRCNTFE (r) register accessor: Statistical Check Poker Count F and E Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntfe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkrcntfe`] module"] -#[doc(alias = "PKRCNTFE")] -pub type Pkrcntfe = crate::Reg; -#[doc = "Statistical Check Poker Count F and E Register"] -pub mod pkrcntfe; -#[doc = "SEC_CFG (rw) register accessor: Security Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_cfg`] module"] -#[doc(alias = "SEC_CFG")] -pub type SecCfg = crate::Reg; -#[doc = "Security Configuration Register"] -pub mod sec_cfg; -#[doc = "INT_CTRL (rw) register accessor: Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ctrl`] module"] -#[doc(alias = "INT_CTRL")] -pub type IntCtrl = crate::Reg; -#[doc = "Interrupt Control Register"] -pub mod int_ctrl; -#[doc = "INT_MASK (rw) register accessor: Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_mask`] module"] -#[doc(alias = "INT_MASK")] -pub type IntMask = crate::Reg; -#[doc = "Mask Register"] -pub mod int_mask; -#[doc = "INT_STATUS (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"] -#[doc(alias = "INT_STATUS")] -pub type IntStatus = crate::Reg; -#[doc = "Interrupt Status Register"] -pub mod int_status; -#[doc = "CSER (r) register accessor: Common Security Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cser::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cser`] module"] -#[doc(alias = "CSER")] -pub type Cser = crate::Reg; -#[doc = "Common Security Error Register"] -pub mod cser; -#[doc = "CSCLR (w) register accessor: Common Security Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csclr`] module"] -#[doc(alias = "CSCLR")] -pub type Csclr = crate::Reg; -#[doc = "Common Security Clear Register"] -pub mod csclr; -#[doc = "OSC2_CTL (rw) register accessor: TRNG Oscillator 2 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc2_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@osc2_ctl`] module"] -#[doc(alias = "OSC2_CTL")] -pub type Osc2Ctl = crate::Reg; -#[doc = "TRNG Oscillator 2 Control Register"] -pub mod osc2_ctl; -#[doc = "VID1 (r) register accessor: Version ID Register (MS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid1`] module"] -#[doc(alias = "VID1")] -pub type Vid1 = crate::Reg; -#[doc = "Version ID Register (MS)"] -pub mod vid1; -#[doc = "VID2 (r) register accessor: Version ID Register (LS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid2`] module"] -#[doc(alias = "VID2")] -pub type Vid2 = crate::Reg; -#[doc = "Version ID Register (LS)"] -pub mod vid2; diff --git a/mcxa276-pac/src/trng0/csclr.rs b/mcxa276-pac/src/trng0/csclr.rs deleted file mode 100644 index e4ebc8107..000000000 --- a/mcxa276-pac/src/trng0/csclr.rs +++ /dev/null @@ -1,159 +0,0 @@ -#[doc = "Register `CSCLR` writer"] -pub type W = crate::W; -#[doc = "Redundant Signals error/fault Detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RedSigsClr { - #[doc = "0: No effect, ignored"] - RedSigsNoeffect = 0, - #[doc = "1: Clears the CSER\\[RED_SIGS\\] bit."] - RedSigsClear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RedSigsClr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RED_SIGS_CLR` writer - Redundant Signals error/fault Detected"] -pub type RedSigsClrW<'a, REG> = crate::BitWriter<'a, REG, RedSigsClr>; -impl<'a, REG> RedSigsClrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect, ignored"] - #[inline(always)] - pub fn red_sigs_noeffect(self) -> &'a mut crate::W { - self.variant(RedSigsClr::RedSigsNoeffect) - } - #[doc = "Clears the CSER\\[RED_SIGS\\] bit."] - #[inline(always)] - pub fn red_sigs_clear(self) -> &'a mut crate::W { - self.variant(RedSigsClr::RedSigsClear) - } -} -#[doc = "Read only: Redundant FSM error/fault detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RedFsmClr { - #[doc = "0: No effect, ignored"] - RedFsmNoeffect = 0, - #[doc = "1: Clears the CSER\\[RED_FSM\\] bit."] - RedFsmClear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RedFsmClr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RED_FSM_CLR` writer - Read only: Redundant FSM error/fault detected"] -pub type RedFsmClrW<'a, REG> = crate::BitWriter<'a, REG, RedFsmClr>; -impl<'a, REG> RedFsmClrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect, ignored"] - #[inline(always)] - pub fn red_fsm_noeffect(self) -> &'a mut crate::W { - self.variant(RedFsmClr::RedFsmNoeffect) - } - #[doc = "Clears the CSER\\[RED_FSM\\] bit."] - #[inline(always)] - pub fn red_fsm_clear(self) -> &'a mut crate::W { - self.variant(RedFsmClr::RedFsmClear) - } -} -#[doc = "Read only: Local-EDC error/fault detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LocalEdcClr { - #[doc = "0: No effect, ignored"] - LocalEdcNoeffect = 0, - #[doc = "1: Clears the CSER\\[LOCAL_EDC\\] bit."] - LocalEdcClear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LocalEdcClr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCAL_EDC_CLR` writer - Read only: Local-EDC error/fault detected"] -pub type LocalEdcClrW<'a, REG> = crate::BitWriter<'a, REG, LocalEdcClr>; -impl<'a, REG> LocalEdcClrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect, ignored"] - #[inline(always)] - pub fn local_edc_noeffect(self) -> &'a mut crate::W { - self.variant(LocalEdcClr::LocalEdcNoeffect) - } - #[doc = "Clears the CSER\\[LOCAL_EDC\\] bit."] - #[inline(always)] - pub fn local_edc_clear(self) -> &'a mut crate::W { - self.variant(LocalEdcClr::LocalEdcClear) - } -} -#[doc = "Read only: Bus-EDC error/fault detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum BusEdcClr { - #[doc = "0: No effect, ignored"] - BusEdcNoeffect = 0, - #[doc = "1: Clears the CSER\\[BUS_EDC\\] bit."] - BusEdcClear = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: BusEdcClr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUS_EDC_CLR` writer - Read only: Bus-EDC error/fault detected"] -pub type BusEdcClrW<'a, REG> = crate::BitWriter<'a, REG, BusEdcClr>; -impl<'a, REG> BusEdcClrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect, ignored"] - #[inline(always)] - pub fn bus_edc_noeffect(self) -> &'a mut crate::W { - self.variant(BusEdcClr::BusEdcNoeffect) - } - #[doc = "Clears the CSER\\[BUS_EDC\\] bit."] - #[inline(always)] - pub fn bus_edc_clear(self) -> &'a mut crate::W { - self.variant(BusEdcClr::BusEdcClear) - } -} -impl W { - #[doc = "Bit 0 - Redundant Signals error/fault Detected"] - #[inline(always)] - pub fn red_sigs_clr(&mut self) -> RedSigsClrW { - RedSigsClrW::new(self, 0) - } - #[doc = "Bit 1 - Read only: Redundant FSM error/fault detected"] - #[inline(always)] - pub fn red_fsm_clr(&mut self) -> RedFsmClrW { - RedFsmClrW::new(self, 1) - } - #[doc = "Bit 2 - Read only: Local-EDC error/fault detected"] - #[inline(always)] - pub fn local_edc_clr(&mut self) -> LocalEdcClrW { - LocalEdcClrW::new(self, 2) - } - #[doc = "Bit 3 - Read only: Bus-EDC error/fault detected"] - #[inline(always)] - pub fn bus_edc_clr(&mut self) -> BusEdcClrW { - BusEdcClrW::new(self, 3) - } -} -#[doc = "Common Security Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CsclrSpec; -impl crate::RegisterSpec for CsclrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`csclr::W`](W) writer structure"] -impl crate::Writable for CsclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CSCLR to value 0"] -impl crate::Resettable for CsclrSpec {} diff --git a/mcxa276-pac/src/trng0/cser.rs b/mcxa276-pac/src/trng0/cser.rs deleted file mode 100644 index 5b016dd7f..000000000 --- a/mcxa276-pac/src/trng0/cser.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `CSER` reader"] -pub type R = crate::R; -#[doc = "Redundant Signals error/fault Detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RedSigs { - #[doc = "0: No redundant signal error/fault"] - RedSigsNoerr = 0, - #[doc = "1: Redundant signal error/fault detected."] - RedSigsErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RedSigs) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RED_SIGS` reader - Redundant Signals error/fault Detected"] -pub type RedSigsR = crate::BitReader; -impl RedSigsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RedSigs { - match self.bits { - false => RedSigs::RedSigsNoerr, - true => RedSigs::RedSigsErr, - } - } - #[doc = "No redundant signal error/fault"] - #[inline(always)] - pub fn is_red_sigs_noerr(&self) -> bool { - *self == RedSigs::RedSigsNoerr - } - #[doc = "Redundant signal error/fault detected."] - #[inline(always)] - pub fn is_red_sigs_err(&self) -> bool { - *self == RedSigs::RedSigsErr - } -} -#[doc = "Redundant FSM error/fault detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RedFsm { - #[doc = "0: No redundant FSM error/fault"] - RedFsmNoerr = 0, - #[doc = "1: Redundant FSM error/fault detected."] - RedFsmErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RedFsm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RED_FSM` reader - Redundant FSM error/fault detected"] -pub type RedFsmR = crate::BitReader; -impl RedFsmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RedFsm { - match self.bits { - false => RedFsm::RedFsmNoerr, - true => RedFsm::RedFsmErr, - } - } - #[doc = "No redundant FSM error/fault"] - #[inline(always)] - pub fn is_red_fsm_noerr(&self) -> bool { - *self == RedFsm::RedFsmNoerr - } - #[doc = "Redundant FSM error/fault detected."] - #[inline(always)] - pub fn is_red_fsm_err(&self) -> bool { - *self == RedFsm::RedFsmErr - } -} -#[doc = "Local-EDC error/fault detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LocalEdc { - #[doc = "0: No Local-EDC error/fault detected."] - LocalEdcNoerr = 0, - #[doc = "1: Local-EDC error/fault detected."] - LocalEdcErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LocalEdc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCAL_EDC` reader - Local-EDC error/fault detected"] -pub type LocalEdcR = crate::BitReader; -impl LocalEdcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LocalEdc { - match self.bits { - false => LocalEdc::LocalEdcNoerr, - true => LocalEdc::LocalEdcErr, - } - } - #[doc = "No Local-EDC error/fault detected."] - #[inline(always)] - pub fn is_local_edc_noerr(&self) -> bool { - *self == LocalEdc::LocalEdcNoerr - } - #[doc = "Local-EDC error/fault detected."] - #[inline(always)] - pub fn is_local_edc_err(&self) -> bool { - *self == LocalEdc::LocalEdcErr - } -} -#[doc = "Bus-EDC error/fault detected\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum BusEdc { - #[doc = "0: No Bus-EDC error/fault detected."] - BusEdcNoerr = 0, - #[doc = "1: Bus-EDC error/fault detected."] - BusEdcErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: BusEdc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BUS_EDC` reader - Bus-EDC error/fault detected"] -pub type BusEdcR = crate::BitReader; -impl BusEdcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> BusEdc { - match self.bits { - false => BusEdc::BusEdcNoerr, - true => BusEdc::BusEdcErr, - } - } - #[doc = "No Bus-EDC error/fault detected."] - #[inline(always)] - pub fn is_bus_edc_noerr(&self) -> bool { - *self == BusEdc::BusEdcNoerr - } - #[doc = "Bus-EDC error/fault detected."] - #[inline(always)] - pub fn is_bus_edc_err(&self) -> bool { - *self == BusEdc::BusEdcErr - } -} -impl R { - #[doc = "Bit 0 - Redundant Signals error/fault Detected"] - #[inline(always)] - pub fn red_sigs(&self) -> RedSigsR { - RedSigsR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Redundant FSM error/fault detected"] - #[inline(always)] - pub fn red_fsm(&self) -> RedFsmR { - RedFsmR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Local-EDC error/fault detected"] - #[inline(always)] - pub fn local_edc(&self) -> LocalEdcR { - LocalEdcR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Bus-EDC error/fault detected"] - #[inline(always)] - pub fn bus_edc(&self) -> BusEdcR { - BusEdcR::new(((self.bits >> 3) & 1) != 0) - } -} -#[doc = "Common Security Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cser::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CserSpec; -impl crate::RegisterSpec for CserSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cser::R`](R) reader structure"] -impl crate::Readable for CserSpec {} -#[doc = "`reset()` method sets CSER to value 0"] -impl crate::Resettable for CserSpec {} diff --git a/mcxa276-pac/src/trng0/ent0.rs b/mcxa276-pac/src/trng0/ent0.rs deleted file mode 100644 index c21ea5b6e..000000000 --- a/mcxa276-pac/src/trng0/ent0.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `ENT0` reader"] -pub type R = crate::R; -#[doc = "Field `ENT` reader - Entropy Value"] -pub type EntR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - Entropy Value"] - #[inline(always)] - pub fn ent(&self) -> EntR { - EntR::new(self.bits) - } -} -#[doc = "Entropy Read Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ent0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Ent0Spec; -impl crate::RegisterSpec for Ent0Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ent0::R`](R) reader structure"] -impl crate::Readable for Ent0Spec {} -#[doc = "`reset()` method sets ENT0 to value 0"] -impl crate::Resettable for Ent0Spec {} diff --git a/mcxa276-pac/src/trng0/frqcnt_frqcnt.rs b/mcxa276-pac/src/trng0/frqcnt_frqcnt.rs deleted file mode 100644 index aa9596c04..000000000 --- a/mcxa276-pac/src/trng0/frqcnt_frqcnt.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `FRQCNT` reader"] -pub type R = crate::R; -#[doc = "Field `FRQ_CT` reader - Frequency Count"] -pub type FrqCtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:21 - Frequency Count"] - #[inline(always)] - pub fn frq_ct(&self) -> FrqCtR { - FrqCtR::new(self.bits & 0x003f_ffff) - } -} -#[doc = "Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqcnt_frqcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrqcntFrqcntSpec; -impl crate::RegisterSpec for FrqcntFrqcntSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`frqcnt_frqcnt::R`](R) reader structure"] -impl crate::Readable for FrqcntFrqcntSpec {} -#[doc = "`reset()` method sets FRQCNT to value 0"] -impl crate::Resettable for FrqcntFrqcntSpec {} diff --git a/mcxa276-pac/src/trng0/frqmax_frqmax.rs b/mcxa276-pac/src/trng0/frqmax_frqmax.rs deleted file mode 100644 index 9caed58c8..000000000 --- a/mcxa276-pac/src/trng0/frqmax_frqmax.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `FRQMAX` reader"] -pub type R = crate::R; -#[doc = "Register `FRQMAX` writer"] -pub type W = crate::W; -#[doc = "Field `FRQ_MAX` reader - Frequency Counter Maximum Limit"] -pub type FrqMaxR = crate::FieldReader; -#[doc = "Field `FRQ_MAX` writer - Frequency Counter Maximum Limit"] -pub type FrqMaxW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; -impl R { - #[doc = "Bits 0:21 - Frequency Counter Maximum Limit"] - #[inline(always)] - pub fn frq_max(&self) -> FrqMaxR { - FrqMaxR::new(self.bits & 0x003f_ffff) - } -} -impl W { - #[doc = "Bits 0:21 - Frequency Counter Maximum Limit"] - #[inline(always)] - pub fn frq_max(&mut self) -> FrqMaxW { - FrqMaxW::new(self, 0) - } -} -#[doc = "Frequency Count Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmax_frqmax::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmax_frqmax::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrqmaxFrqmaxSpec; -impl crate::RegisterSpec for FrqmaxFrqmaxSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`frqmax_frqmax::R`](R) reader structure"] -impl crate::Readable for FrqmaxFrqmaxSpec {} -#[doc = "`write(|w| ..)` method takes [`frqmax_frqmax::W`](W) writer structure"] -impl crate::Writable for FrqmaxFrqmaxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FRQMAX to value 0x6400"] -impl crate::Resettable for FrqmaxFrqmaxSpec { - const RESET_VALUE: u32 = 0x6400; -} diff --git a/mcxa276-pac/src/trng0/frqmin_frqmin.rs b/mcxa276-pac/src/trng0/frqmin_frqmin.rs deleted file mode 100644 index 5a717d15c..000000000 --- a/mcxa276-pac/src/trng0/frqmin_frqmin.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `FRQMIN` reader"] -pub type R = crate::R; -#[doc = "Register `FRQMIN` writer"] -pub type W = crate::W; -#[doc = "Field `FRQ_MIN` reader - Frequency Count Minimum Limit"] -pub type FrqMinR = crate::FieldReader; -#[doc = "Field `FRQ_MIN` writer - Frequency Count Minimum Limit"] -pub type FrqMinW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; -impl R { - #[doc = "Bits 0:21 - Frequency Count Minimum Limit"] - #[inline(always)] - pub fn frq_min(&self) -> FrqMinR { - FrqMinR::new(self.bits & 0x003f_ffff) - } -} -impl W { - #[doc = "Bits 0:21 - Frequency Count Minimum Limit"] - #[inline(always)] - pub fn frq_min(&mut self) -> FrqMinW { - FrqMinW::new(self, 0) - } -} -#[doc = "Frequency Count Minimum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`frqmin_frqmin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frqmin_frqmin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrqminFrqminSpec; -impl crate::RegisterSpec for FrqminFrqminSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`frqmin_frqmin::R`](R) reader structure"] -impl crate::Readable for FrqminFrqminSpec {} -#[doc = "`write(|w| ..)` method takes [`frqmin_frqmin::W`](W) writer structure"] -impl crate::Writable for FrqminFrqminSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FRQMIN to value 0x0640"] -impl crate::Resettable for FrqminFrqminSpec { - const RESET_VALUE: u32 = 0x0640; -} diff --git a/mcxa276-pac/src/trng0/int_ctrl.rs b/mcxa276-pac/src/trng0/int_ctrl.rs deleted file mode 100644 index 5f74ee566..000000000 --- a/mcxa276-pac/src/trng0/int_ctrl.rs +++ /dev/null @@ -1,275 +0,0 @@ -#[doc = "Register `INT_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `INT_CTRL` writer"] -pub type W = crate::W; -#[doc = "Clear the HW_ERR interrupt.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum HwErr { - #[doc = "0: Clears the INT_STATUS\\[HW_ERR\\] bit. Will automatically set after writing."] - HwErrClear = 0, - #[doc = "1: Enables the INT_STATUS\\[HW_ERR\\] bit to be set, thereby enabling interrupt generation for the HW_ERR condition."] - HwErrOn = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: HwErr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HW_ERR` reader - Clear the HW_ERR interrupt."] -pub type HwErrR = crate::BitReader; -impl HwErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> HwErr { - match self.bits { - false => HwErr::HwErrClear, - true => HwErr::HwErrOn, - } - } - #[doc = "Clears the INT_STATUS\\[HW_ERR\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn is_hw_err_clear(&self) -> bool { - *self == HwErr::HwErrClear - } - #[doc = "Enables the INT_STATUS\\[HW_ERR\\] bit to be set, thereby enabling interrupt generation for the HW_ERR condition."] - #[inline(always)] - pub fn is_hw_err_on(&self) -> bool { - *self == HwErr::HwErrOn - } -} -#[doc = "Field `HW_ERR` writer - Clear the HW_ERR interrupt."] -pub type HwErrW<'a, REG> = crate::BitWriter<'a, REG, HwErr>; -impl<'a, REG> HwErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Clears the INT_STATUS\\[HW_ERR\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn hw_err_clear(self) -> &'a mut crate::W { - self.variant(HwErr::HwErrClear) - } - #[doc = "Enables the INT_STATUS\\[HW_ERR\\] bit to be set, thereby enabling interrupt generation for the HW_ERR condition."] - #[inline(always)] - pub fn hw_err_on(self) -> &'a mut crate::W { - self.variant(HwErr::HwErrOn) - } -} -#[doc = "Clear the ENT_VAL interrupt.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EntVal { - #[doc = "0: Clears the INT_STATUS\\[ENT_VAL\\] bit. Will automatically set after writing."] - EntValClear = 0, - #[doc = "1: Enables the INT_STATUS\\[ENT_VAL\\] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition."] - EntValOn = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EntVal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENT_VAL` reader - Clear the ENT_VAL interrupt."] -pub type EntValR = crate::BitReader; -impl EntValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EntVal { - match self.bits { - false => EntVal::EntValClear, - true => EntVal::EntValOn, - } - } - #[doc = "Clears the INT_STATUS\\[ENT_VAL\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn is_ent_val_clear(&self) -> bool { - *self == EntVal::EntValClear - } - #[doc = "Enables the INT_STATUS\\[ENT_VAL\\] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition."] - #[inline(always)] - pub fn is_ent_val_on(&self) -> bool { - *self == EntVal::EntValOn - } -} -#[doc = "Field `ENT_VAL` writer - Clear the ENT_VAL interrupt."] -pub type EntValW<'a, REG> = crate::BitWriter<'a, REG, EntVal>; -impl<'a, REG> EntValW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Clears the INT_STATUS\\[ENT_VAL\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn ent_val_clear(self) -> &'a mut crate::W { - self.variant(EntVal::EntValClear) - } - #[doc = "Enables the INT_STATUS\\[ENT_VAL\\] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition."] - #[inline(always)] - pub fn ent_val_on(self) -> &'a mut crate::W { - self.variant(EntVal::EntValOn) - } -} -#[doc = "Clear the FRQ_CT_FAIL interrupt.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FrqCtFail { - #[doc = "0: Clears the INT_STATUS\\[FRQ_CT_FAIL\\] bit. Will automatically set after writing."] - FrqCtFailClear = 0, - #[doc = "1: Enables the INT_STATUS\\[FRQ_CT_FAIL\\] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition."] - FrqCtFailOn = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FrqCtFail) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRQ_CT_FAIL` reader - Clear the FRQ_CT_FAIL interrupt."] -pub type FrqCtFailR = crate::BitReader; -impl FrqCtFailR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FrqCtFail { - match self.bits { - false => FrqCtFail::FrqCtFailClear, - true => FrqCtFail::FrqCtFailOn, - } - } - #[doc = "Clears the INT_STATUS\\[FRQ_CT_FAIL\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn is_frq_ct_fail_clear(&self) -> bool { - *self == FrqCtFail::FrqCtFailClear - } - #[doc = "Enables the INT_STATUS\\[FRQ_CT_FAIL\\] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition."] - #[inline(always)] - pub fn is_frq_ct_fail_on(&self) -> bool { - *self == FrqCtFail::FrqCtFailOn - } -} -#[doc = "Field `FRQ_CT_FAIL` writer - Clear the FRQ_CT_FAIL interrupt."] -pub type FrqCtFailW<'a, REG> = crate::BitWriter<'a, REG, FrqCtFail>; -impl<'a, REG> FrqCtFailW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Clears the INT_STATUS\\[FRQ_CT_FAIL\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn frq_ct_fail_clear(self) -> &'a mut crate::W { - self.variant(FrqCtFail::FrqCtFailClear) - } - #[doc = "Enables the INT_STATUS\\[FRQ_CT_FAIL\\] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition."] - #[inline(always)] - pub fn frq_ct_fail_on(self) -> &'a mut crate::W { - self.variant(FrqCtFail::FrqCtFailOn) - } -} -#[doc = "Clear the INTG_FLT interrupt.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IntgFlt { - #[doc = "0: Clears the INT_STATUS\\[INTG_FLT\\] bit. Will automatically set after writing."] - IntgFltClear = 0, - #[doc = "1: Enables the INT_STATUS\\[INTG_FLT\\] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition."] - IntgFltOn = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IntgFlt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTG_FLT` reader - Clear the INTG_FLT interrupt."] -pub type IntgFltR = crate::BitReader; -impl IntgFltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IntgFlt { - match self.bits { - false => IntgFlt::IntgFltClear, - true => IntgFlt::IntgFltOn, - } - } - #[doc = "Clears the INT_STATUS\\[INTG_FLT\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn is_intg_flt_clear(&self) -> bool { - *self == IntgFlt::IntgFltClear - } - #[doc = "Enables the INT_STATUS\\[INTG_FLT\\] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition."] - #[inline(always)] - pub fn is_intg_flt_on(&self) -> bool { - *self == IntgFlt::IntgFltOn - } -} -#[doc = "Field `INTG_FLT` writer - Clear the INTG_FLT interrupt."] -pub type IntgFltW<'a, REG> = crate::BitWriter<'a, REG, IntgFlt>; -impl<'a, REG> IntgFltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Clears the INT_STATUS\\[INTG_FLT\\] bit. Will automatically set after writing."] - #[inline(always)] - pub fn intg_flt_clear(self) -> &'a mut crate::W { - self.variant(IntgFlt::IntgFltClear) - } - #[doc = "Enables the INT_STATUS\\[INTG_FLT\\] bit to be set, thereby enabling interrupt generation for the INTG_FLT condition."] - #[inline(always)] - pub fn intg_flt_on(self) -> &'a mut crate::W { - self.variant(IntgFlt::IntgFltOn) - } -} -impl R { - #[doc = "Bit 0 - Clear the HW_ERR interrupt."] - #[inline(always)] - pub fn hw_err(&self) -> HwErrR { - HwErrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Clear the ENT_VAL interrupt."] - #[inline(always)] - pub fn ent_val(&self) -> EntValR { - EntValR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Clear the FRQ_CT_FAIL interrupt."] - #[inline(always)] - pub fn frq_ct_fail(&self) -> FrqCtFailR { - FrqCtFailR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Clear the INTG_FLT interrupt."] - #[inline(always)] - pub fn intg_flt(&self) -> IntgFltR { - IntgFltR::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Clear the HW_ERR interrupt."] - #[inline(always)] - pub fn hw_err(&mut self) -> HwErrW { - HwErrW::new(self, 0) - } - #[doc = "Bit 1 - Clear the ENT_VAL interrupt."] - #[inline(always)] - pub fn ent_val(&mut self) -> EntValW { - EntValW::new(self, 1) - } - #[doc = "Bit 2 - Clear the FRQ_CT_FAIL interrupt."] - #[inline(always)] - pub fn frq_ct_fail(&mut self) -> FrqCtFailW { - FrqCtFailW::new(self, 2) - } - #[doc = "Bit 3 - Clear the INTG_FLT interrupt."] - #[inline(always)] - pub fn intg_flt(&mut self) -> IntgFltW { - IntgFltW::new(self, 3) - } -} -#[doc = "Interrupt Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IntCtrlSpec; -impl crate::RegisterSpec for IntCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`int_ctrl::R`](R) reader structure"] -impl crate::Readable for IntCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`int_ctrl::W`](W) writer structure"] -impl crate::Writable for IntCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets INT_CTRL to value 0x0f"] -impl crate::Resettable for IntCtrlSpec { - const RESET_VALUE: u32 = 0x0f; -} diff --git a/mcxa276-pac/src/trng0/int_mask.rs b/mcxa276-pac/src/trng0/int_mask.rs deleted file mode 100644 index 9fa936199..000000000 --- a/mcxa276-pac/src/trng0/int_mask.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `INT_MASK` reader"] -pub type R = crate::R; -#[doc = "Register `INT_MASK` writer"] -pub type W = crate::W; -#[doc = "Mask the HW_ERR interrupt.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum HwErr { - #[doc = "0: HW_ERR interrupt is disabled."] - HwErrMasked = 0, - #[doc = "1: HW_ERR interrupt is enabled."] - HwErrActive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: HwErr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HW_ERR` reader - Mask the HW_ERR interrupt."] -pub type HwErrR = crate::BitReader; -impl HwErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> HwErr { - match self.bits { - false => HwErr::HwErrMasked, - true => HwErr::HwErrActive, - } - } - #[doc = "HW_ERR interrupt is disabled."] - #[inline(always)] - pub fn is_hw_err_masked(&self) -> bool { - *self == HwErr::HwErrMasked - } - #[doc = "HW_ERR interrupt is enabled."] - #[inline(always)] - pub fn is_hw_err_active(&self) -> bool { - *self == HwErr::HwErrActive - } -} -#[doc = "Field `HW_ERR` writer - Mask the HW_ERR interrupt."] -pub type HwErrW<'a, REG> = crate::BitWriter<'a, REG, HwErr>; -impl<'a, REG> HwErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "HW_ERR interrupt is disabled."] - #[inline(always)] - pub fn hw_err_masked(self) -> &'a mut crate::W { - self.variant(HwErr::HwErrMasked) - } - #[doc = "HW_ERR interrupt is enabled."] - #[inline(always)] - pub fn hw_err_active(self) -> &'a mut crate::W { - self.variant(HwErr::HwErrActive) - } -} -#[doc = "Mask the ENT_VAL interrupt.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EntVal { - #[doc = "0: ENT_VAL interrupt is disabled."] - EntValMasked = 0, - #[doc = "1: ENT_VAL interrupt is enabled."] - EntValActive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EntVal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENT_VAL` reader - Mask the ENT_VAL interrupt."] -pub type EntValR = crate::BitReader; -impl EntValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EntVal { - match self.bits { - false => EntVal::EntValMasked, - true => EntVal::EntValActive, - } - } - #[doc = "ENT_VAL interrupt is disabled."] - #[inline(always)] - pub fn is_ent_val_masked(&self) -> bool { - *self == EntVal::EntValMasked - } - #[doc = "ENT_VAL interrupt is enabled."] - #[inline(always)] - pub fn is_ent_val_active(&self) -> bool { - *self == EntVal::EntValActive - } -} -#[doc = "Field `ENT_VAL` writer - Mask the ENT_VAL interrupt."] -pub type EntValW<'a, REG> = crate::BitWriter<'a, REG, EntVal>; -impl<'a, REG> EntValW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "ENT_VAL interrupt is disabled."] - #[inline(always)] - pub fn ent_val_masked(self) -> &'a mut crate::W { - self.variant(EntVal::EntValMasked) - } - #[doc = "ENT_VAL interrupt is enabled."] - #[inline(always)] - pub fn ent_val_active(self) -> &'a mut crate::W { - self.variant(EntVal::EntValActive) - } -} -#[doc = "Mask the FRQ_CT_FAIL interrupt.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FrqCtFail { - #[doc = "0: FRQ_CT_FAIL interrupt is disabled."] - FrqCtFailMasked = 0, - #[doc = "1: FRQ_CT_FAIL interrupt is enabled."] - FrqCtFailActive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FrqCtFail) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRQ_CT_FAIL` reader - Mask the FRQ_CT_FAIL interrupt."] -pub type FrqCtFailR = crate::BitReader; -impl FrqCtFailR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FrqCtFail { - match self.bits { - false => FrqCtFail::FrqCtFailMasked, - true => FrqCtFail::FrqCtFailActive, - } - } - #[doc = "FRQ_CT_FAIL interrupt is disabled."] - #[inline(always)] - pub fn is_frq_ct_fail_masked(&self) -> bool { - *self == FrqCtFail::FrqCtFailMasked - } - #[doc = "FRQ_CT_FAIL interrupt is enabled."] - #[inline(always)] - pub fn is_frq_ct_fail_active(&self) -> bool { - *self == FrqCtFail::FrqCtFailActive - } -} -#[doc = "Field `FRQ_CT_FAIL` writer - Mask the FRQ_CT_FAIL interrupt."] -pub type FrqCtFailW<'a, REG> = crate::BitWriter<'a, REG, FrqCtFail>; -impl<'a, REG> FrqCtFailW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "FRQ_CT_FAIL interrupt is disabled."] - #[inline(always)] - pub fn frq_ct_fail_masked(self) -> &'a mut crate::W { - self.variant(FrqCtFail::FrqCtFailMasked) - } - #[doc = "FRQ_CT_FAIL interrupt is enabled."] - #[inline(always)] - pub fn frq_ct_fail_active(self) -> &'a mut crate::W { - self.variant(FrqCtFail::FrqCtFailActive) - } -} -#[doc = "Mask the INTG_FLT interrupt.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IntgFlt { - #[doc = "0: INTG_FLT interrupt is disabled."] - IntgFltMasked = 0, - #[doc = "1: INTG_FLT interrupt is enabled."] - IntgFltActive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IntgFlt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTG_FLT` reader - Mask the INTG_FLT interrupt."] -pub type IntgFltR = crate::BitReader; -impl IntgFltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IntgFlt { - match self.bits { - false => IntgFlt::IntgFltMasked, - true => IntgFlt::IntgFltActive, - } - } - #[doc = "INTG_FLT interrupt is disabled."] - #[inline(always)] - pub fn is_intg_flt_masked(&self) -> bool { - *self == IntgFlt::IntgFltMasked - } - #[doc = "INTG_FLT interrupt is enabled."] - #[inline(always)] - pub fn is_intg_flt_active(&self) -> bool { - *self == IntgFlt::IntgFltActive - } -} -#[doc = "Field `INTG_FLT` writer - Mask the INTG_FLT interrupt."] -pub type IntgFltW<'a, REG> = crate::BitWriter<'a, REG, IntgFlt>; -impl<'a, REG> IntgFltW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "INTG_FLT interrupt is disabled."] - #[inline(always)] - pub fn intg_flt_masked(self) -> &'a mut crate::W { - self.variant(IntgFlt::IntgFltMasked) - } - #[doc = "INTG_FLT interrupt is enabled."] - #[inline(always)] - pub fn intg_flt_active(self) -> &'a mut crate::W { - self.variant(IntgFlt::IntgFltActive) - } -} -impl R { - #[doc = "Bit 0 - Mask the HW_ERR interrupt."] - #[inline(always)] - pub fn hw_err(&self) -> HwErrR { - HwErrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Mask the ENT_VAL interrupt."] - #[inline(always)] - pub fn ent_val(&self) -> EntValR { - EntValR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Mask the FRQ_CT_FAIL interrupt."] - #[inline(always)] - pub fn frq_ct_fail(&self) -> FrqCtFailR { - FrqCtFailR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Mask the INTG_FLT interrupt."] - #[inline(always)] - pub fn intg_flt(&self) -> IntgFltR { - IntgFltR::new(((self.bits >> 3) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Mask the HW_ERR interrupt."] - #[inline(always)] - pub fn hw_err(&mut self) -> HwErrW { - HwErrW::new(self, 0) - } - #[doc = "Bit 1 - Mask the ENT_VAL interrupt."] - #[inline(always)] - pub fn ent_val(&mut self) -> EntValW { - EntValW::new(self, 1) - } - #[doc = "Bit 2 - Mask the FRQ_CT_FAIL interrupt."] - #[inline(always)] - pub fn frq_ct_fail(&mut self) -> FrqCtFailW { - FrqCtFailW::new(self, 2) - } - #[doc = "Bit 3 - Mask the INTG_FLT interrupt."] - #[inline(always)] - pub fn intg_flt(&mut self) -> IntgFltW { - IntgFltW::new(self, 3) - } -} -#[doc = "Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IntMaskSpec; -impl crate::RegisterSpec for IntMaskSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`int_mask::R`](R) reader structure"] -impl crate::Readable for IntMaskSpec {} -#[doc = "`write(|w| ..)` method takes [`int_mask::W`](W) writer structure"] -impl crate::Writable for IntMaskSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets INT_MASK to value 0"] -impl crate::Resettable for IntMaskSpec {} diff --git a/mcxa276-pac/src/trng0/int_status.rs b/mcxa276-pac/src/trng0/int_status.rs deleted file mode 100644 index b2afb31c2..000000000 --- a/mcxa276-pac/src/trng0/int_status.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = "Register `INT_STATUS` reader"] -pub type R = crate::R; -#[doc = "Read: TRNG Error. Any error in the TRNG will trigger this interrupt.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum HwErr { - #[doc = "0: No error."] - HwErrNo = 0, - #[doc = "1: Error detected."] - HwErrYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: HwErr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HW_ERR` reader - Read: TRNG Error. Any error in the TRNG will trigger this interrupt."] -pub type HwErrR = crate::BitReader; -impl HwErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> HwErr { - match self.bits { - false => HwErr::HwErrNo, - true => HwErr::HwErrYes, - } - } - #[doc = "No error."] - #[inline(always)] - pub fn is_hw_err_no(&self) -> bool { - *self == HwErr::HwErrNo - } - #[doc = "Error detected."] - #[inline(always)] - pub fn is_hw_err_yes(&self) -> bool { - *self == HwErr::HwErrYes - } -} -#[doc = "Entropy Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EntVal { - #[doc = "0: Busy generating entropy. Any value read from the Entropy registers is invalid."] - EntValInvalid = 0, - #[doc = "1: Values read from the Entropy registers are valid."] - EntValValid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EntVal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENT_VAL` reader - Entropy Valid"] -pub type EntValR = crate::BitReader; -impl EntValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EntVal { - match self.bits { - false => EntVal::EntValInvalid, - true => EntVal::EntValValid, - } - } - #[doc = "Busy generating entropy. Any value read from the Entropy registers is invalid."] - #[inline(always)] - pub fn is_ent_val_invalid(&self) -> bool { - *self == EntVal::EntValInvalid - } - #[doc = "Values read from the Entropy registers are valid."] - #[inline(always)] - pub fn is_ent_val_valid(&self) -> bool { - *self == EntVal::EntValValid - } -} -#[doc = "Frequency Count Fail\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FrqCtFail { - #[doc = "0: No hardware nor self test frequency errors."] - FrqCtFailNoErr = 0, - #[doc = "1: The frequency counter has detected a failure."] - FrqCtFailErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FrqCtFail) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRQ_CT_FAIL` reader - Frequency Count Fail"] -pub type FrqCtFailR = crate::BitReader; -impl FrqCtFailR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FrqCtFail { - match self.bits { - false => FrqCtFail::FrqCtFailNoErr, - true => FrqCtFail::FrqCtFailErr, - } - } - #[doc = "No hardware nor self test frequency errors."] - #[inline(always)] - pub fn is_frq_ct_fail_no_err(&self) -> bool { - *self == FrqCtFail::FrqCtFailNoErr - } - #[doc = "The frequency counter has detected a failure."] - #[inline(always)] - pub fn is_frq_ct_fail_err(&self) -> bool { - *self == FrqCtFail::FrqCtFailErr - } -} -#[doc = "Integrity Fault. An internal fault has occurred.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IntgFlt { - #[doc = "0: No internal fault has been detected."] - IntgFltNoErr = 0, - #[doc = "1: TRNG has detected internal fault."] - IntgFltErr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IntgFlt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTG_FLT` reader - Integrity Fault. An internal fault has occurred."] -pub type IntgFltR = crate::BitReader; -impl IntgFltR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IntgFlt { - match self.bits { - false => IntgFlt::IntgFltNoErr, - true => IntgFlt::IntgFltErr, - } - } - #[doc = "No internal fault has been detected."] - #[inline(always)] - pub fn is_intg_flt_no_err(&self) -> bool { - *self == IntgFlt::IntgFltNoErr - } - #[doc = "TRNG has detected internal fault."] - #[inline(always)] - pub fn is_intg_flt_err(&self) -> bool { - *self == IntgFlt::IntgFltErr - } -} -impl R { - #[doc = "Bit 0 - Read: TRNG Error. Any error in the TRNG will trigger this interrupt."] - #[inline(always)] - pub fn hw_err(&self) -> HwErrR { - HwErrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Entropy Valid"] - #[inline(always)] - pub fn ent_val(&self) -> EntValR { - EntValR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Frequency Count Fail"] - #[inline(always)] - pub fn frq_ct_fail(&self) -> FrqCtFailR { - FrqCtFailR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Integrity Fault. An internal fault has occurred."] - #[inline(always)] - pub fn intg_flt(&self) -> IntgFltR { - IntgFltR::new(((self.bits >> 3) & 1) != 0) - } -} -#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IntStatusSpec; -impl crate::RegisterSpec for IntStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`int_status::R`](R) reader structure"] -impl crate::Readable for IntStatusSpec {} -#[doc = "`reset()` method sets INT_STATUS to value 0"] -impl crate::Resettable for IntStatusSpec {} diff --git a/mcxa276-pac/src/trng0/mctl.rs b/mcxa276-pac/src/trng0/mctl.rs deleted file mode 100644 index f86c45532..000000000 --- a/mcxa276-pac/src/trng0/mctl.rs +++ /dev/null @@ -1,515 +0,0 @@ -#[doc = "Register `MCTL` reader"] -pub type R = crate::R; -#[doc = "Register `MCTL` writer"] -pub type W = crate::W; -#[doc = "Oscillator1 Divide\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OscDiv { - #[doc = "0: use ring oscillator with no divide"] - OscDivDiv1 = 0, - #[doc = "1: use ring oscillator divided-by-2"] - OscDivDiv2 = 1, - #[doc = "2: use ring oscillator divided-by-4"] - OscDivDiv4 = 2, - #[doc = "3: use ring oscillator divided-by-8"] - OscDivDiv8 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OscDiv) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OscDiv { - type Ux = u8; -} -impl crate::IsEnum for OscDiv {} -#[doc = "Field `OSC_DIV` reader - Oscillator1 Divide"] -pub type OscDivR = crate::FieldReader; -impl OscDivR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OscDiv { - match self.bits { - 0 => OscDiv::OscDivDiv1, - 1 => OscDiv::OscDivDiv2, - 2 => OscDiv::OscDivDiv4, - 3 => OscDiv::OscDivDiv8, - _ => unreachable!(), - } - } - #[doc = "use ring oscillator with no divide"] - #[inline(always)] - pub fn is_osc_div_div1(&self) -> bool { - *self == OscDiv::OscDivDiv1 - } - #[doc = "use ring oscillator divided-by-2"] - #[inline(always)] - pub fn is_osc_div_div2(&self) -> bool { - *self == OscDiv::OscDivDiv2 - } - #[doc = "use ring oscillator divided-by-4"] - #[inline(always)] - pub fn is_osc_div_div4(&self) -> bool { - *self == OscDiv::OscDivDiv4 - } - #[doc = "use ring oscillator divided-by-8"] - #[inline(always)] - pub fn is_osc_div_div8(&self) -> bool { - *self == OscDiv::OscDivDiv8 - } -} -#[doc = "Field `OSC_DIV` writer - Oscillator1 Divide"] -pub type OscDivW<'a, REG> = crate::FieldWriter<'a, REG, 2, OscDiv, crate::Safe>; -impl<'a, REG> OscDivW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "use ring oscillator with no divide"] - #[inline(always)] - pub fn osc_div_div1(self) -> &'a mut crate::W { - self.variant(OscDiv::OscDivDiv1) - } - #[doc = "use ring oscillator divided-by-2"] - #[inline(always)] - pub fn osc_div_div2(self) -> &'a mut crate::W { - self.variant(OscDiv::OscDivDiv2) - } - #[doc = "use ring oscillator divided-by-4"] - #[inline(always)] - pub fn osc_div_div4(self) -> &'a mut crate::W { - self.variant(OscDiv::OscDivDiv4) - } - #[doc = "use ring oscillator divided-by-8"] - #[inline(always)] - pub fn osc_div_div8(self) -> &'a mut crate::W { - self.variant(OscDiv::OscDivDiv8) - } -} -#[doc = "Field `DIS_SLF_TST` writer - Disable Self-Tests"] -pub type DisSlfTstW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRNG_ACC` reader - TRNG Access Mode"] -pub type TrngAccR = crate::BitReader; -#[doc = "Field `TRNG_ACC` writer - TRNG Access Mode"] -pub type TrngAccW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Reset Defaults\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RstDef { - #[doc = "0: No impact."] - Disable = 0, - #[doc = "1: Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RstDef) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST_DEF` writer - Reset Defaults"] -pub type RstDefW<'a, REG> = crate::BitWriter<'a, REG, RstDef>; -impl<'a, REG> RstDefW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No impact."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(RstDef::Disable) - } - #[doc = "Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(RstDef::Enable) - } -} -#[doc = "Field `FCT_FAIL` reader - Frequency Count Fail"] -pub type FctFailR = crate::BitReader; -#[doc = "Frequency Count Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FctVal { - #[doc = "0: Frequency Count is not valid"] - Disable = 0, - #[doc = "1: Frequency Count is valid"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FctVal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FCT_VAL` reader - Frequency Count Valid"] -pub type FctValR = crate::BitReader; -impl FctValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FctVal { - match self.bits { - false => FctVal::Disable, - true => FctVal::Enable, - } - } - #[doc = "Frequency Count is not valid"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == FctVal::Disable - } - #[doc = "Frequency Count is valid"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == FctVal::Enable - } -} -#[doc = "Entropy Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum EntVal { - #[doc = "0: Entropy is not valid"] - Disable = 0, - #[doc = "1: Entropy is valid"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: EntVal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ENT_VAL` reader - Entropy Valid"] -pub type EntValR = crate::BitReader; -impl EntValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> EntVal { - match self.bits { - false => EntVal::Disable, - true => EntVal::Enable, - } - } - #[doc = "Entropy is not valid"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == EntVal::Disable - } - #[doc = "Entropy is valid"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == EntVal::Enable - } -} -#[doc = "Error Status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Err { - #[doc = "0: No error"] - Disable = 0, - #[doc = "1: Error detected"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Err) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERR` reader - Error Status"] -pub type ErrR = crate::BitReader; -impl ErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Err { - match self.bits { - false => Err::Disable, - true => Err::Enable, - } - } - #[doc = "No error"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Err::Disable - } - #[doc = "Error detected"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Err::Enable - } -} -#[doc = "Field `ERR` writer - Error Status"] -pub type ErrW<'a, REG> = crate::BitWriter1C<'a, REG, Err>; -impl<'a, REG> ErrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No error"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Err::Disable) - } - #[doc = "Error detected"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Err::Enable) - } -} -#[doc = "TRNG is ok to stop\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TstopOk { - #[doc = "0: TRNG is generating entropy and is not ok to stop"] - Disable = 0, - #[doc = "1: TRNG is not generating entropy and is ok to stop"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TstopOk) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TSTOP_OK` reader - TRNG is ok to stop"] -pub type TstopOkR = crate::BitReader; -impl TstopOkR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TstopOk { - match self.bits { - false => TstopOk::Disable, - true => TstopOk::Enable, - } - } - #[doc = "TRNG is generating entropy and is not ok to stop"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == TstopOk::Disable - } - #[doc = "TRNG is not generating entropy and is ok to stop"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == TstopOk::Enable - } -} -#[doc = "Oscillator 2 Failure\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Osc2Fail { - #[doc = "0: Oscillator 2 is running."] - Disable = 0, - #[doc = "1: Oscillator 2 has failed (see OSC2_CTL\\[OSC_FAILSAFE_LMT\\])."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Osc2Fail) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSC2_FAIL` reader - Oscillator 2 Failure"] -pub type Osc2FailR = crate::BitReader; -impl Osc2FailR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Osc2Fail { - match self.bits { - false => Osc2Fail::Disable, - true => Osc2Fail::Enable, - } - } - #[doc = "Oscillator 2 is running."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Osc2Fail::Disable - } - #[doc = "Oscillator 2 has failed (see OSC2_CTL\\[OSC_FAILSAFE_LMT\\])."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Osc2Fail::Enable - } -} -#[doc = "Program Mode\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Prgm { - #[doc = "0: TRNG is in Run Mode"] - Disable = 0, - #[doc = "1: TRNG is in Program Mode"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Prgm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PRGM` reader - Program Mode"] -pub type PrgmR = crate::BitReader; -impl PrgmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Prgm { - match self.bits { - false => Prgm::Disable, - true => Prgm::Enable, - } - } - #[doc = "TRNG is in Run Mode"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Prgm::Disable - } - #[doc = "TRNG is in Program Mode"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Prgm::Enable - } -} -#[doc = "Field `PRGM` writer - Program Mode"] -pub type PrgmW<'a, REG> = crate::BitWriter<'a, REG, Prgm>; -impl<'a, REG> PrgmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "TRNG is in Run Mode"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Prgm::Disable) - } - #[doc = "TRNG is in Program Mode"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Prgm::Enable) - } -} -#[doc = "Integrity Error\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IntgErr { - #[doc = "0: TRNG detected no internal bit error"] - Disable = 0, - #[doc = "1: TRNG detected internal bit error(s)"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IntgErr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTG_ERR` reader - Integrity Error"] -pub type IntgErrR = crate::BitReader; -impl IntgErrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IntgErr { - match self.bits { - false => IntgErr::Disable, - true => IntgErr::Enable, - } - } - #[doc = "TRNG detected no internal bit error"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IntgErr::Disable - } - #[doc = "TRNG detected internal bit error(s)"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IntgErr::Enable - } -} -impl R { - #[doc = "Bits 2:3 - Oscillator1 Divide"] - #[inline(always)] - pub fn osc_div(&self) -> OscDivR { - OscDivR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bit 5 - TRNG Access Mode"] - #[inline(always)] - pub fn trng_acc(&self) -> TrngAccR { - TrngAccR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 8 - Frequency Count Fail"] - #[inline(always)] - pub fn fct_fail(&self) -> FctFailR { - FctFailR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Frequency Count Valid"] - #[inline(always)] - pub fn fct_val(&self) -> FctValR { - FctValR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Entropy Valid"] - #[inline(always)] - pub fn ent_val(&self) -> EntValR { - EntValR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - Error Status"] - #[inline(always)] - pub fn err(&self) -> ErrR { - ErrR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - TRNG is ok to stop"] - #[inline(always)] - pub fn tstop_ok(&self) -> TstopOkR { - TstopOkR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 15 - Oscillator 2 Failure"] - #[inline(always)] - pub fn osc2_fail(&self) -> Osc2FailR { - Osc2FailR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Program Mode"] - #[inline(always)] - pub fn prgm(&self) -> PrgmR { - PrgmR::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 31 - Integrity Error"] - #[inline(always)] - pub fn intg_err(&self) -> IntgErrR { - IntgErrR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 2:3 - Oscillator1 Divide"] - #[inline(always)] - pub fn osc_div(&mut self) -> OscDivW { - OscDivW::new(self, 2) - } - #[doc = "Bit 4 - Disable Self-Tests"] - #[inline(always)] - pub fn dis_slf_tst(&mut self) -> DisSlfTstW { - DisSlfTstW::new(self, 4) - } - #[doc = "Bit 5 - TRNG Access Mode"] - #[inline(always)] - pub fn trng_acc(&mut self) -> TrngAccW { - TrngAccW::new(self, 5) - } - #[doc = "Bit 6 - Reset Defaults"] - #[inline(always)] - pub fn rst_def(&mut self) -> RstDefW { - RstDefW::new(self, 6) - } - #[doc = "Bit 12 - Error Status"] - #[inline(always)] - pub fn err(&mut self) -> ErrW { - ErrW::new(self, 12) - } - #[doc = "Bit 16 - Program Mode"] - #[inline(always)] - pub fn prgm(&mut self) -> PrgmW { - PrgmW::new(self, 16) - } -} -#[doc = "Miscellaneous Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MctlSpec; -impl crate::RegisterSpec for MctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mctl::R`](R) reader structure"] -impl crate::Readable for MctlSpec {} -#[doc = "`write(|w| ..)` method takes [`mctl::W`](W) writer structure"] -impl crate::Writable for MctlSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1000; -} -#[doc = "`reset()` method sets MCTL to value 0x0001_2000"] -impl crate::Resettable for MctlSpec { - const RESET_VALUE: u32 = 0x0001_2000; -} diff --git a/mcxa276-pac/src/trng0/osc2_ctl.rs b/mcxa276-pac/src/trng0/osc2_ctl.rs deleted file mode 100644 index 09cef0601..000000000 --- a/mcxa276-pac/src/trng0/osc2_ctl.rs +++ /dev/null @@ -1,478 +0,0 @@ -#[doc = "Register `OSC2_CTL` reader"] -pub type R = crate::R; -#[doc = "Register `OSC2_CTL` writer"] -pub type W = crate::W; -#[doc = "TRNG entropy generation control.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum TrngEntCtl { - #[doc = "0: Single oscillator mode, using OSC1 (default)"] - TrngEntCtlSingleOsc1 = 0, - #[doc = "1: Dual oscillator mode"] - TrngEntCtlDualOscs = 1, - #[doc = "2: Single oscillator mode, using OSC2"] - TrngEntCtlSingleOsc2 = 2, - #[doc = "3: Unused, (bit field cannot be written to this value)"] - Osc2DivDiv8 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: TrngEntCtl) -> Self { - variant as _ - } -} -impl crate::FieldSpec for TrngEntCtl { - type Ux = u8; -} -impl crate::IsEnum for TrngEntCtl {} -#[doc = "Field `TRNG_ENT_CTL` reader - TRNG entropy generation control."] -pub type TrngEntCtlR = crate::FieldReader; -impl TrngEntCtlR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrngEntCtl { - match self.bits { - 0 => TrngEntCtl::TrngEntCtlSingleOsc1, - 1 => TrngEntCtl::TrngEntCtlDualOscs, - 2 => TrngEntCtl::TrngEntCtlSingleOsc2, - 3 => TrngEntCtl::Osc2DivDiv8, - _ => unreachable!(), - } - } - #[doc = "Single oscillator mode, using OSC1 (default)"] - #[inline(always)] - pub fn is_trng_ent_ctl_single_osc1(&self) -> bool { - *self == TrngEntCtl::TrngEntCtlSingleOsc1 - } - #[doc = "Dual oscillator mode"] - #[inline(always)] - pub fn is_trng_ent_ctl_dual_oscs(&self) -> bool { - *self == TrngEntCtl::TrngEntCtlDualOscs - } - #[doc = "Single oscillator mode, using OSC2"] - #[inline(always)] - pub fn is_trng_ent_ctl_single_osc2(&self) -> bool { - *self == TrngEntCtl::TrngEntCtlSingleOsc2 - } - #[doc = "Unused, (bit field cannot be written to this value)"] - #[inline(always)] - pub fn is_osc2_div_div8(&self) -> bool { - *self == TrngEntCtl::Osc2DivDiv8 - } -} -#[doc = "Field `TRNG_ENT_CTL` writer - TRNG entropy generation control."] -pub type TrngEntCtlW<'a, REG> = crate::FieldWriter<'a, REG, 2, TrngEntCtl, crate::Safe>; -impl<'a, REG> TrngEntCtlW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Single oscillator mode, using OSC1 (default)"] - #[inline(always)] - pub fn trng_ent_ctl_single_osc1(self) -> &'a mut crate::W { - self.variant(TrngEntCtl::TrngEntCtlSingleOsc1) - } - #[doc = "Dual oscillator mode"] - #[inline(always)] - pub fn trng_ent_ctl_dual_oscs(self) -> &'a mut crate::W { - self.variant(TrngEntCtl::TrngEntCtlDualOscs) - } - #[doc = "Single oscillator mode, using OSC2"] - #[inline(always)] - pub fn trng_ent_ctl_single_osc2(self) -> &'a mut crate::W { - self.variant(TrngEntCtl::TrngEntCtlSingleOsc2) - } - #[doc = "Unused, (bit field cannot be written to this value)"] - #[inline(always)] - pub fn osc2_div_div8(self) -> &'a mut crate::W { - self.variant(TrngEntCtl::Osc2DivDiv8) - } -} -#[doc = "Oscillator 2 Divide.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Osc2Div { - #[doc = "0: Use ring oscillator 2 with no divide"] - Osc2DivDiv1 = 0, - #[doc = "1: Use ring oscillator 2 divided-by-2"] - Osc2DivDiv2 = 1, - #[doc = "2: Use ring oscillator 2 divided-by-4"] - Osc2DivDiv4 = 2, - #[doc = "3: Use ring oscillator 2 divided-by-8"] - Osc2DivDiv8 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Osc2Div) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Osc2Div { - type Ux = u8; -} -impl crate::IsEnum for Osc2Div {} -#[doc = "Field `OSC2_DIV` reader - Oscillator 2 Divide."] -pub type Osc2DivR = crate::FieldReader; -impl Osc2DivR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Osc2Div { - match self.bits { - 0 => Osc2Div::Osc2DivDiv1, - 1 => Osc2Div::Osc2DivDiv2, - 2 => Osc2Div::Osc2DivDiv4, - 3 => Osc2Div::Osc2DivDiv8, - _ => unreachable!(), - } - } - #[doc = "Use ring oscillator 2 with no divide"] - #[inline(always)] - pub fn is_osc2_div_div1(&self) -> bool { - *self == Osc2Div::Osc2DivDiv1 - } - #[doc = "Use ring oscillator 2 divided-by-2"] - #[inline(always)] - pub fn is_osc2_div_div2(&self) -> bool { - *self == Osc2Div::Osc2DivDiv2 - } - #[doc = "Use ring oscillator 2 divided-by-4"] - #[inline(always)] - pub fn is_osc2_div_div4(&self) -> bool { - *self == Osc2Div::Osc2DivDiv4 - } - #[doc = "Use ring oscillator 2 divided-by-8"] - #[inline(always)] - pub fn is_osc2_div_div8(&self) -> bool { - *self == Osc2Div::Osc2DivDiv8 - } -} -#[doc = "Field `OSC2_DIV` writer - Oscillator 2 Divide."] -pub type Osc2DivW<'a, REG> = crate::FieldWriter<'a, REG, 2, Osc2Div, crate::Safe>; -impl<'a, REG> Osc2DivW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Use ring oscillator 2 with no divide"] - #[inline(always)] - pub fn osc2_div_div1(self) -> &'a mut crate::W { - self.variant(Osc2Div::Osc2DivDiv1) - } - #[doc = "Use ring oscillator 2 divided-by-2"] - #[inline(always)] - pub fn osc2_div_div2(self) -> &'a mut crate::W { - self.variant(Osc2Div::Osc2DivDiv2) - } - #[doc = "Use ring oscillator 2 divided-by-4"] - #[inline(always)] - pub fn osc2_div_div4(self) -> &'a mut crate::W { - self.variant(Osc2Div::Osc2DivDiv4) - } - #[doc = "Use ring oscillator 2 divided-by-8"] - #[inline(always)] - pub fn osc2_div_div8(self) -> &'a mut crate::W { - self.variant(Osc2Div::Osc2DivDiv8) - } -} -#[doc = "Oscillator 2 Clock Output Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Osc2OutEn { - #[doc = "0: Ring oscillator 2 output is gated to an output pad."] - Osc2OutEn0 = 0, - #[doc = "1: Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."] - Osc2OutEn1 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Osc2OutEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSC2_OUT_EN` reader - Oscillator 2 Clock Output Enable"] -pub type Osc2OutEnR = crate::BitReader; -impl Osc2OutEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Osc2OutEn { - match self.bits { - false => Osc2OutEn::Osc2OutEn0, - true => Osc2OutEn::Osc2OutEn1, - } - } - #[doc = "Ring oscillator 2 output is gated to an output pad."] - #[inline(always)] - pub fn is_osc2_out_en_0(&self) -> bool { - *self == Osc2OutEn::Osc2OutEn0 - } - #[doc = "Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."] - #[inline(always)] - pub fn is_osc2_out_en_1(&self) -> bool { - *self == Osc2OutEn::Osc2OutEn1 - } -} -#[doc = "Field `OSC2_OUT_EN` writer - Oscillator 2 Clock Output Enable"] -pub type Osc2OutEnW<'a, REG> = crate::BitWriter<'a, REG, Osc2OutEn>; -impl<'a, REG> Osc2OutEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Ring oscillator 2 output is gated to an output pad."] - #[inline(always)] - pub fn osc2_out_en_0(self) -> &'a mut crate::W { - self.variant(Osc2OutEn::Osc2OutEn0) - } - #[doc = "Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."] - #[inline(always)] - pub fn osc2_out_en_1(self) -> &'a mut crate::W { - self.variant(Osc2OutEn::Osc2OutEn1) - } -} -#[doc = "TRNG Oscillator 2 Frequency Count Valid\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Osc2FctVal { - #[doc = "0: Frequency count is invalid."] - Disable = 0, - #[doc = "1: If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Osc2FctVal) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSC2_FCT_VAL` reader - TRNG Oscillator 2 Frequency Count Valid"] -pub type Osc2FctValR = crate::BitReader; -impl Osc2FctValR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Osc2FctVal { - match self.bits { - false => Osc2FctVal::Disable, - true => Osc2FctVal::Enable, - } - } - #[doc = "Frequency count is invalid."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Osc2FctVal::Disable - } - #[doc = "If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Osc2FctVal::Enable - } -} -#[doc = "Oscillator fail safe limit.\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OscFailsafeLmt { - #[doc = "0: The limit N is 4096 (2^12) system clocks."] - OscFailsafeLmt4k = 0, - #[doc = "1: The limit N is 65536 (2^16) system clocks. (default)"] - OscFailsafeLmt64k = 1, - #[doc = "2: N is 2^20 system clocks."] - OscFailsafeLmt1m = 2, - #[doc = "3: N is 2^22 system clocks (full range of the counter being used)."] - OscFailsafeLmt4m = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OscFailsafeLmt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OscFailsafeLmt { - type Ux = u8; -} -impl crate::IsEnum for OscFailsafeLmt {} -#[doc = "Field `OSC_FAILSAFE_LMT` reader - Oscillator fail safe limit."] -pub type OscFailsafeLmtR = crate::FieldReader; -impl OscFailsafeLmtR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OscFailsafeLmt { - match self.bits { - 0 => OscFailsafeLmt::OscFailsafeLmt4k, - 1 => OscFailsafeLmt::OscFailsafeLmt64k, - 2 => OscFailsafeLmt::OscFailsafeLmt1m, - 3 => OscFailsafeLmt::OscFailsafeLmt4m, - _ => unreachable!(), - } - } - #[doc = "The limit N is 4096 (2^12) system clocks."] - #[inline(always)] - pub fn is_osc_failsafe_lmt_4k(&self) -> bool { - *self == OscFailsafeLmt::OscFailsafeLmt4k - } - #[doc = "The limit N is 65536 (2^16) system clocks. (default)"] - #[inline(always)] - pub fn is_osc_failsafe_lmt_64k(&self) -> bool { - *self == OscFailsafeLmt::OscFailsafeLmt64k - } - #[doc = "N is 2^20 system clocks."] - #[inline(always)] - pub fn is_osc_failsafe_lmt_1m(&self) -> bool { - *self == OscFailsafeLmt::OscFailsafeLmt1m - } - #[doc = "N is 2^22 system clocks (full range of the counter being used)."] - #[inline(always)] - pub fn is_osc_failsafe_lmt_4m(&self) -> bool { - *self == OscFailsafeLmt::OscFailsafeLmt4m - } -} -#[doc = "Field `OSC_FAILSAFE_LMT` writer - Oscillator fail safe limit."] -pub type OscFailsafeLmtW<'a, REG> = crate::FieldWriter<'a, REG, 2, OscFailsafeLmt, crate::Safe>; -impl<'a, REG> OscFailsafeLmtW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "The limit N is 4096 (2^12) system clocks."] - #[inline(always)] - pub fn osc_failsafe_lmt_4k(self) -> &'a mut crate::W { - self.variant(OscFailsafeLmt::OscFailsafeLmt4k) - } - #[doc = "The limit N is 65536 (2^16) system clocks. (default)"] - #[inline(always)] - pub fn osc_failsafe_lmt_64k(self) -> &'a mut crate::W { - self.variant(OscFailsafeLmt::OscFailsafeLmt64k) - } - #[doc = "N is 2^20 system clocks."] - #[inline(always)] - pub fn osc_failsafe_lmt_1m(self) -> &'a mut crate::W { - self.variant(OscFailsafeLmt::OscFailsafeLmt1m) - } - #[doc = "N is 2^22 system clocks (full range of the counter being used)."] - #[inline(always)] - pub fn osc_failsafe_lmt_4m(self) -> &'a mut crate::W { - self.variant(OscFailsafeLmt::OscFailsafeLmt4m) - } -} -#[doc = "Oscillator fail safe test.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OscFailsafeTest { - #[doc = "0: No impact."] - Disable = 0, - #[doc = "1: Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OscFailsafeTest) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSC_FAILSAFE_TEST` reader - Oscillator fail safe test."] -pub type OscFailsafeTestR = crate::BitReader; -impl OscFailsafeTestR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OscFailsafeTest { - match self.bits { - false => OscFailsafeTest::Disable, - true => OscFailsafeTest::Enable, - } - } - #[doc = "No impact."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == OscFailsafeTest::Disable - } - #[doc = "Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == OscFailsafeTest::Enable - } -} -#[doc = "Field `OSC_FAILSAFE_TEST` writer - Oscillator fail safe test."] -pub type OscFailsafeTestW<'a, REG> = crate::BitWriter<'a, REG, OscFailsafeTest>; -impl<'a, REG> OscFailsafeTestW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No impact."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(OscFailsafeTest::Disable) - } - #[doc = "Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(OscFailsafeTest::Enable) - } -} -impl R { - #[doc = "Bits 0:1 - TRNG entropy generation control."] - #[inline(always)] - pub fn trng_ent_ctl(&self) -> TrngEntCtlR { - TrngEntCtlR::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Oscillator 2 Divide."] - #[inline(always)] - pub fn osc2_div(&self) -> Osc2DivR { - Osc2DivR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bit 4 - Oscillator 2 Clock Output Enable"] - #[inline(always)] - pub fn osc2_out_en(&self) -> Osc2OutEnR { - Osc2OutEnR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 9 - TRNG Oscillator 2 Frequency Count Valid"] - #[inline(always)] - pub fn osc2_fct_val(&self) -> Osc2FctValR { - Osc2FctValR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 12:13 - Oscillator fail safe limit."] - #[inline(always)] - pub fn osc_failsafe_lmt(&self) -> OscFailsafeLmtR { - OscFailsafeLmtR::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bit 14 - Oscillator fail safe test."] - #[inline(always)] - pub fn osc_failsafe_test(&self) -> OscFailsafeTestR { - OscFailsafeTestR::new(((self.bits >> 14) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:1 - TRNG entropy generation control."] - #[inline(always)] - pub fn trng_ent_ctl(&mut self) -> TrngEntCtlW { - TrngEntCtlW::new(self, 0) - } - #[doc = "Bits 2:3 - Oscillator 2 Divide."] - #[inline(always)] - pub fn osc2_div(&mut self) -> Osc2DivW { - Osc2DivW::new(self, 2) - } - #[doc = "Bit 4 - Oscillator 2 Clock Output Enable"] - #[inline(always)] - pub fn osc2_out_en(&mut self) -> Osc2OutEnW { - Osc2OutEnW::new(self, 4) - } - #[doc = "Bits 12:13 - Oscillator fail safe limit."] - #[inline(always)] - pub fn osc_failsafe_lmt(&mut self) -> OscFailsafeLmtW { - OscFailsafeLmtW::new(self, 12) - } - #[doc = "Bit 14 - Oscillator fail safe test."] - #[inline(always)] - pub fn osc_failsafe_test(&mut self) -> OscFailsafeTestW { - OscFailsafeTestW::new(self, 14) - } -} -#[doc = "TRNG Oscillator 2 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc2_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Osc2CtlSpec; -impl crate::RegisterSpec for Osc2CtlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`osc2_ctl::R`](R) reader structure"] -impl crate::Readable for Osc2CtlSpec {} -#[doc = "`write(|w| ..)` method takes [`osc2_ctl::W`](W) writer structure"] -impl crate::Writable for Osc2CtlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets OSC2_CTL to value 0x1000"] -impl crate::Resettable for Osc2CtlSpec { - const RESET_VALUE: u32 = 0x1000; -} diff --git a/mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs b/mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs deleted file mode 100644 index 85f658787..000000000 --- a/mcxa276-pac/src/trng0/osc2_frqcnt_osc2_frqcnt.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `OSC2_FRQCNT` reader"] -pub type R = crate::R; -#[doc = "Field `OSC2_FRQ_CT` reader - Frequency Count"] -pub type Osc2FrqCtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:21 - Frequency Count"] - #[inline(always)] - pub fn osc2_frq_ct(&self) -> Osc2FrqCtR { - Osc2FrqCtR::new(self.bits & 0x003f_ffff) - } -} -#[doc = "Oscillator-2 Frequency Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_frqcnt_osc2_frqcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Osc2FrqcntOsc2FrqcntSpec; -impl crate::RegisterSpec for Osc2FrqcntOsc2FrqcntSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`osc2_frqcnt_osc2_frqcnt::R`](R) reader structure"] -impl crate::Readable for Osc2FrqcntOsc2FrqcntSpec {} -#[doc = "`reset()` method sets OSC2_FRQCNT to value 0"] -impl crate::Resettable for Osc2FrqcntOsc2FrqcntSpec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt10.rs b/mcxa276-pac/src/trng0/pkrcnt10.rs deleted file mode 100644 index 18763c4af..000000000 --- a/mcxa276-pac/src/trng0/pkrcnt10.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNT10` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_0_CT` reader - Poker 0h Count"] -pub type Pkr0CtR = crate::FieldReader; -#[doc = "Field `PKR_1_CT` reader - Poker 1h Count"] -pub type Pkr1CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker 0h Count"] - #[inline(always)] - pub fn pkr_0_ct(&self) -> Pkr0CtR { - Pkr0CtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker 1h Count"] - #[inline(always)] - pub fn pkr_1_ct(&self) -> Pkr1CtR { - Pkr1CtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count 1 and 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pkrcnt10Spec; -impl crate::RegisterSpec for Pkrcnt10Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcnt10::R`](R) reader structure"] -impl crate::Readable for Pkrcnt10Spec {} -#[doc = "`reset()` method sets PKRCNT10 to value 0"] -impl crate::Resettable for Pkrcnt10Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt32.rs b/mcxa276-pac/src/trng0/pkrcnt32.rs deleted file mode 100644 index ae25c35d6..000000000 --- a/mcxa276-pac/src/trng0/pkrcnt32.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNT32` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_2_CT` reader - Poker 2h Count"] -pub type Pkr2CtR = crate::FieldReader; -#[doc = "Field `PKR_3_CT` reader - Poker 3h Count"] -pub type Pkr3CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker 2h Count"] - #[inline(always)] - pub fn pkr_2_ct(&self) -> Pkr2CtR { - Pkr2CtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker 3h Count"] - #[inline(always)] - pub fn pkr_3_ct(&self) -> Pkr3CtR { - Pkr3CtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count 3 and 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt32::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pkrcnt32Spec; -impl crate::RegisterSpec for Pkrcnt32Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcnt32::R`](R) reader structure"] -impl crate::Readable for Pkrcnt32Spec {} -#[doc = "`reset()` method sets PKRCNT32 to value 0"] -impl crate::Resettable for Pkrcnt32Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt54.rs b/mcxa276-pac/src/trng0/pkrcnt54.rs deleted file mode 100644 index e003d3274..000000000 --- a/mcxa276-pac/src/trng0/pkrcnt54.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNT54` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_4_CT` reader - Poker 4h Count"] -pub type Pkr4CtR = crate::FieldReader; -#[doc = "Field `PKR_5_CT` reader - Poker 5h Count"] -pub type Pkr5CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker 4h Count"] - #[inline(always)] - pub fn pkr_4_ct(&self) -> Pkr4CtR { - Pkr4CtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker 5h Count"] - #[inline(always)] - pub fn pkr_5_ct(&self) -> Pkr5CtR { - Pkr5CtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count 5 and 4 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt54::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pkrcnt54Spec; -impl crate::RegisterSpec for Pkrcnt54Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcnt54::R`](R) reader structure"] -impl crate::Readable for Pkrcnt54Spec {} -#[doc = "`reset()` method sets PKRCNT54 to value 0"] -impl crate::Resettable for Pkrcnt54Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt76.rs b/mcxa276-pac/src/trng0/pkrcnt76.rs deleted file mode 100644 index f7cf64de9..000000000 --- a/mcxa276-pac/src/trng0/pkrcnt76.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNT76` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_6_CT` reader - Poker 6h Count"] -pub type Pkr6CtR = crate::FieldReader; -#[doc = "Field `PKR_7_CT` reader - Poker 7h Count"] -pub type Pkr7CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker 6h Count"] - #[inline(always)] - pub fn pkr_6_ct(&self) -> Pkr6CtR { - Pkr6CtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker 7h Count"] - #[inline(always)] - pub fn pkr_7_ct(&self) -> Pkr7CtR { - Pkr7CtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count 7 and 6 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt76::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pkrcnt76Spec; -impl crate::RegisterSpec for Pkrcnt76Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcnt76::R`](R) reader structure"] -impl crate::Readable for Pkrcnt76Spec {} -#[doc = "`reset()` method sets PKRCNT76 to value 0"] -impl crate::Resettable for Pkrcnt76Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcnt98.rs b/mcxa276-pac/src/trng0/pkrcnt98.rs deleted file mode 100644 index 3ad7a337f..000000000 --- a/mcxa276-pac/src/trng0/pkrcnt98.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNT98` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_8_CT` reader - Poker 8h Count"] -pub type Pkr8CtR = crate::FieldReader; -#[doc = "Field `PKR_9_CT` reader - Poker 9h Count"] -pub type Pkr9CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker 8h Count"] - #[inline(always)] - pub fn pkr_8_ct(&self) -> Pkr8CtR { - Pkr8CtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker 9h Count"] - #[inline(always)] - pub fn pkr_9_ct(&self) -> Pkr9CtR { - Pkr9CtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count 9 and 8 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcnt98::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pkrcnt98Spec; -impl crate::RegisterSpec for Pkrcnt98Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcnt98::R`](R) reader structure"] -impl crate::Readable for Pkrcnt98Spec {} -#[doc = "`reset()` method sets PKRCNT98 to value 0"] -impl crate::Resettable for Pkrcnt98Spec {} diff --git a/mcxa276-pac/src/trng0/pkrcntba.rs b/mcxa276-pac/src/trng0/pkrcntba.rs deleted file mode 100644 index 98e48b194..000000000 --- a/mcxa276-pac/src/trng0/pkrcntba.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNTBA` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_A_CT` reader - Poker Ah Count"] -pub type PkrACtR = crate::FieldReader; -#[doc = "Field `PKR_B_CT` reader - Poker Bh Count"] -pub type PkrBCtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker Ah Count"] - #[inline(always)] - pub fn pkr_a_ct(&self) -> PkrACtR { - PkrACtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker Bh Count"] - #[inline(always)] - pub fn pkr_b_ct(&self) -> PkrBCtR { - PkrBCtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count B and A Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntba::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkrcntbaSpec; -impl crate::RegisterSpec for PkrcntbaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcntba::R`](R) reader structure"] -impl crate::Readable for PkrcntbaSpec {} -#[doc = "`reset()` method sets PKRCNTBA to value 0"] -impl crate::Resettable for PkrcntbaSpec {} diff --git a/mcxa276-pac/src/trng0/pkrcntdc.rs b/mcxa276-pac/src/trng0/pkrcntdc.rs deleted file mode 100644 index 12ed0115f..000000000 --- a/mcxa276-pac/src/trng0/pkrcntdc.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNTDC` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_C_CT` reader - Poker Ch Count"] -pub type PkrCCtR = crate::FieldReader; -#[doc = "Field `PKR_D_CT` reader - Poker Dh Count"] -pub type PkrDCtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker Ch Count"] - #[inline(always)] - pub fn pkr_c_ct(&self) -> PkrCCtR { - PkrCCtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker Dh Count"] - #[inline(always)] - pub fn pkr_d_ct(&self) -> PkrDCtR { - PkrDCtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count D and C Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntdc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkrcntdcSpec; -impl crate::RegisterSpec for PkrcntdcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcntdc::R`](R) reader structure"] -impl crate::Readable for PkrcntdcSpec {} -#[doc = "`reset()` method sets PKRCNTDC to value 0"] -impl crate::Resettable for PkrcntdcSpec {} diff --git a/mcxa276-pac/src/trng0/pkrcntfe.rs b/mcxa276-pac/src/trng0/pkrcntfe.rs deleted file mode 100644 index 3df6de3d3..000000000 --- a/mcxa276-pac/src/trng0/pkrcntfe.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `PKRCNTFE` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_E_CT` reader - Poker Eh Count"] -pub type PkrECtR = crate::FieldReader; -#[doc = "Field `PKR_F_CT` reader - Poker Fh Count"] -pub type PkrFCtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Poker Eh Count"] - #[inline(always)] - pub fn pkr_e_ct(&self) -> PkrECtR { - PkrECtR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Poker Fh Count"] - #[inline(always)] - pub fn pkr_f_ct(&self) -> PkrFCtR { - PkrFCtR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Statistical Check Poker Count F and E Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrcntfe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkrcntfeSpec; -impl crate::RegisterSpec for PkrcntfeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrcntfe::R`](R) reader structure"] -impl crate::Readable for PkrcntfeSpec {} -#[doc = "`reset()` method sets PKRCNTFE to value 0"] -impl crate::Resettable for PkrcntfeSpec {} diff --git a/mcxa276-pac/src/trng0/pkrmax_pkrmax.rs b/mcxa276-pac/src/trng0/pkrmax_pkrmax.rs deleted file mode 100644 index dab952475..000000000 --- a/mcxa276-pac/src/trng0/pkrmax_pkrmax.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `PKRMAX` reader"] -pub type R = crate::R; -#[doc = "Register `PKRMAX` writer"] -pub type W = crate::W; -#[doc = "Field `PKR_MAX` reader - Poker Maximum Limit."] -pub type PkrMaxR = crate::FieldReader; -#[doc = "Field `PKR_MAX` writer - Poker Maximum Limit."] -pub type PkrMaxW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; -impl R { - #[doc = "Bits 0:23 - Poker Maximum Limit."] - #[inline(always)] - pub fn pkr_max(&self) -> PkrMaxR { - PkrMaxR::new(self.bits & 0x00ff_ffff) - } -} -impl W { - #[doc = "Bits 0:23 - Poker Maximum Limit."] - #[inline(always)] - pub fn pkr_max(&mut self) -> PkrMaxW { - PkrMaxW::new(self, 0) - } -} -#[doc = "Poker Maximum Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrmax_pkrmax::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrmax_pkrmax::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkrmaxPkrmaxSpec; -impl crate::RegisterSpec for PkrmaxPkrmaxSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrmax_pkrmax::R`](R) reader structure"] -impl crate::Readable for PkrmaxPkrmaxSpec {} -#[doc = "`write(|w| ..)` method takes [`pkrmax_pkrmax::W`](W) writer structure"] -impl crate::Writable for PkrmaxPkrmaxSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKRMAX to value 0x0640"] -impl crate::Resettable for PkrmaxPkrmaxSpec { - const RESET_VALUE: u32 = 0x0640; -} diff --git a/mcxa276-pac/src/trng0/pkrrng.rs b/mcxa276-pac/src/trng0/pkrrng.rs deleted file mode 100644 index 2adcc4642..000000000 --- a/mcxa276-pac/src/trng0/pkrrng.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `PKRRNG` reader"] -pub type R = crate::R; -#[doc = "Register `PKRRNG` writer"] -pub type W = crate::W; -#[doc = "Field `PKR_RNG` reader - Poker Range"] -pub type PkrRngR = crate::FieldReader; -#[doc = "Field `PKR_RNG` writer - Poker Range"] -pub type PkrRngW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Poker Range"] - #[inline(always)] - pub fn pkr_rng(&self) -> PkrRngR { - PkrRngR::new((self.bits & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Poker Range"] - #[inline(always)] - pub fn pkr_rng(&mut self) -> PkrRngW { - PkrRngW::new(self, 0) - } -} -#[doc = "Poker Range Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrrng::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkrrng::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkrrngSpec; -impl crate::RegisterSpec for PkrrngSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrrng::R`](R) reader structure"] -impl crate::Readable for PkrrngSpec {} -#[doc = "`write(|w| ..)` method takes [`pkrrng::W`](W) writer structure"] -impl crate::Writable for PkrrngSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PKRRNG to value 0x023a"] -impl crate::Resettable for PkrrngSpec { - const RESET_VALUE: u32 = 0x023a; -} diff --git a/mcxa276-pac/src/trng0/pkrsq_pkrsq.rs b/mcxa276-pac/src/trng0/pkrsq_pkrsq.rs deleted file mode 100644 index fecd7415d..000000000 --- a/mcxa276-pac/src/trng0/pkrsq_pkrsq.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `PKRSQ` reader"] -pub type R = crate::R; -#[doc = "Field `PKR_SQ` reader - Poker Square Calculation Result."] -pub type PkrSqR = crate::FieldReader; -impl R { - #[doc = "Bits 0:23 - Poker Square Calculation Result."] - #[inline(always)] - pub fn pkr_sq(&self) -> PkrSqR { - PkrSqR::new(self.bits & 0x00ff_ffff) - } -} -#[doc = "Poker Square Calculation Result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pkrsq_pkrsq::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PkrsqPkrsqSpec; -impl crate::RegisterSpec for PkrsqPkrsqSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pkrsq_pkrsq::R`](R) reader structure"] -impl crate::Readable for PkrsqPkrsqSpec {} -#[doc = "`reset()` method sets PKRSQ to value 0"] -impl crate::Resettable for PkrsqPkrsqSpec {} diff --git a/mcxa276-pac/src/trng0/sblim_sblim.rs b/mcxa276-pac/src/trng0/sblim_sblim.rs deleted file mode 100644 index c6b627a96..000000000 --- a/mcxa276-pac/src/trng0/sblim_sblim.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `SBLIM` reader"] -pub type R = crate::R; -#[doc = "Register `SBLIM` writer"] -pub type W = crate::W; -#[doc = "Field `SB_LIM` reader - Sparse Bit Limit"] -pub type SbLimR = crate::FieldReader; -#[doc = "Field `SB_LIM` writer - Sparse Bit Limit"] -pub type SbLimW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:9 - Sparse Bit Limit"] - #[inline(always)] - pub fn sb_lim(&self) -> SbLimR { - SbLimR::new((self.bits & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:9 - Sparse Bit Limit"] - #[inline(always)] - pub fn sb_lim(&mut self) -> SbLimW { - SbLimW::new(self, 0) - } -} -#[doc = "Sparse Bit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sblim_sblim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sblim_sblim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SblimSblimSpec; -impl crate::RegisterSpec for SblimSblimSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sblim_sblim::R`](R) reader structure"] -impl crate::Readable for SblimSblimSpec {} -#[doc = "`write(|w| ..)` method takes [`sblim_sblim::W`](W) writer structure"] -impl crate::Writable for SblimSblimSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SBLIM to value 0x3f"] -impl crate::Resettable for SblimSblimSpec { - const RESET_VALUE: u32 = 0x3f; -} diff --git a/mcxa276-pac/src/trng0/scmc_scmc.rs b/mcxa276-pac/src/trng0/scmc_scmc.rs deleted file mode 100644 index 2ad6beac5..000000000 --- a/mcxa276-pac/src/trng0/scmc_scmc.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `SCMC` reader"] -pub type R = crate::R; -#[doc = "Field `MONO_CT` reader - Monobit Count"] -pub type MonoCtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Monobit Count"] - #[inline(always)] - pub fn mono_ct(&self) -> MonoCtR { - MonoCtR::new((self.bits & 0xffff) as u16) - } -} -#[doc = "Statistical Check Monobit Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmc_scmc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ScmcScmcSpec; -impl crate::RegisterSpec for ScmcScmcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scmc_scmc::R`](R) reader structure"] -impl crate::Readable for ScmcScmcSpec {} -#[doc = "`reset()` method sets SCMC to value 0"] -impl crate::Resettable for ScmcScmcSpec {} diff --git a/mcxa276-pac/src/trng0/scmisc.rs b/mcxa276-pac/src/trng0/scmisc.rs deleted file mode 100644 index c5b58b375..000000000 --- a/mcxa276-pac/src/trng0/scmisc.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCMISC` reader"] -pub type R = crate::R; -#[doc = "Register `SCMISC` writer"] -pub type W = crate::W; -#[doc = "Field `LRUN_MAX` reader - Long run max limit"] -pub type LrunMaxR = crate::FieldReader; -#[doc = "Field `LRUN_MAX` writer - Long run max limit"] -pub type LrunMaxW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `RTY_CT` reader - Retry count"] -pub type RtyCtR = crate::FieldReader; -#[doc = "Field `RTY_CT` writer - Retry count"] -pub type RtyCtW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:7 - Long run max limit"] - #[inline(always)] - pub fn lrun_max(&self) -> LrunMaxR { - LrunMaxR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 16:19 - Retry count"] - #[inline(always)] - pub fn rty_ct(&self) -> RtyCtR { - RtyCtR::new(((self.bits >> 16) & 0x0f) as u8) - } -} -impl W { - #[doc = "Bits 0:7 - Long run max limit"] - #[inline(always)] - pub fn lrun_max(&mut self) -> LrunMaxW { - LrunMaxW::new(self, 0) - } - #[doc = "Bits 16:19 - Retry count"] - #[inline(always)] - pub fn rty_ct(&mut self) -> RtyCtW { - RtyCtW::new(self, 16) - } -} -#[doc = "Statistical Check Miscellaneous Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scmisc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scmisc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ScmiscSpec; -impl crate::RegisterSpec for ScmiscSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scmisc::R`](R) reader structure"] -impl crate::Readable for ScmiscSpec {} -#[doc = "`write(|w| ..)` method takes [`scmisc::W`](W) writer structure"] -impl crate::Writable for ScmiscSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCMISC to value 0x0001_001f"] -impl crate::Resettable for ScmiscSpec { - const RESET_VALUE: u32 = 0x0001_001f; -} diff --git a/mcxa276-pac/src/trng0/scml_scml.rs b/mcxa276-pac/src/trng0/scml_scml.rs deleted file mode 100644 index 650be71e3..000000000 --- a/mcxa276-pac/src/trng0/scml_scml.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCML` reader"] -pub type R = crate::R; -#[doc = "Register `SCML` writer"] -pub type W = crate::W; -#[doc = "Field `MONO_MAX` reader - Monobit Maximum Limit"] -pub type MonoMaxR = crate::FieldReader; -#[doc = "Field `MONO_MAX` writer - Monobit Maximum Limit"] -pub type MonoMaxW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `MONO_RNG` reader - Monobit Range"] -pub type MonoRngR = crate::FieldReader; -#[doc = "Field `MONO_RNG` writer - Monobit Range"] -pub type MonoRngW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Monobit Maximum Limit"] - #[inline(always)] - pub fn mono_max(&self) -> MonoMaxR { - MonoMaxR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Monobit Range"] - #[inline(always)] - pub fn mono_rng(&self) -> MonoRngR { - MonoRngR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Monobit Maximum Limit"] - #[inline(always)] - pub fn mono_max(&mut self) -> MonoMaxW { - MonoMaxW::new(self, 0) - } - #[doc = "Bits 16:31 - Monobit Range"] - #[inline(always)] - pub fn mono_rng(&mut self) -> MonoRngW { - MonoRngW::new(self, 16) - } -} -#[doc = "Statistical Check Monobit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scml_scml::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scml_scml::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ScmlScmlSpec; -impl crate::RegisterSpec for ScmlScmlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scml_scml::R`](R) reader structure"] -impl crate::Readable for ScmlScmlSpec {} -#[doc = "`write(|w| ..)` method takes [`scml_scml::W`](W) writer structure"] -impl crate::Writable for ScmlScmlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCML to value 0x0078_013c"] -impl crate::Resettable for ScmlScmlSpec { - const RESET_VALUE: u32 = 0x0078_013c; -} diff --git a/mcxa276-pac/src/trng0/scr1c_scr1c.rs b/mcxa276-pac/src/trng0/scr1c_scr1c.rs deleted file mode 100644 index 0ac4f1ee1..000000000 --- a/mcxa276-pac/src/trng0/scr1c_scr1c.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `SCR1C` reader"] -pub type R = crate::R; -#[doc = "Field `R1_0_CT` reader - Runs of Zero, Length 1 Count"] -pub type R1_0CtR = crate::FieldReader; -#[doc = "Field `R1_1_CT` reader - Runs of One, Length 1 Count"] -pub type R1_1CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:14 - Runs of Zero, Length 1 Count"] - #[inline(always)] - pub fn r1_0_ct(&self) -> R1_0CtR { - R1_0CtR::new((self.bits & 0x7fff) as u16) - } - #[doc = "Bits 16:30 - Runs of One, Length 1 Count"] - #[inline(always)] - pub fn r1_1_ct(&self) -> R1_1CtR { - R1_1CtR::new(((self.bits >> 16) & 0x7fff) as u16) - } -} -#[doc = "Statistical Check Run Length 1 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1c_scr1c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr1cScr1cSpec; -impl crate::RegisterSpec for Scr1cScr1cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr1c_scr1c::R`](R) reader structure"] -impl crate::Readable for Scr1cScr1cSpec {} -#[doc = "`reset()` method sets SCR1C to value 0"] -impl crate::Resettable for Scr1cScr1cSpec {} diff --git a/mcxa276-pac/src/trng0/scr1l_scr1l.rs b/mcxa276-pac/src/trng0/scr1l_scr1l.rs deleted file mode 100644 index 25136b7cb..000000000 --- a/mcxa276-pac/src/trng0/scr1l_scr1l.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCR1L` reader"] -pub type R = crate::R; -#[doc = "Register `SCR1L` writer"] -pub type W = crate::W; -#[doc = "Field `RUN1_MAX` reader - Run Length 1 Maximum Limit"] -pub type Run1MaxR = crate::FieldReader; -#[doc = "Field `RUN1_MAX` writer - Run Length 1 Maximum Limit"] -pub type Run1MaxW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; -#[doc = "Field `RUN1_RNG` reader - Run Length 1 Range"] -pub type Run1RngR = crate::FieldReader; -#[doc = "Field `RUN1_RNG` writer - Run Length 1 Range"] -pub type Run1RngW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; -impl R { - #[doc = "Bits 0:14 - Run Length 1 Maximum Limit"] - #[inline(always)] - pub fn run1_max(&self) -> Run1MaxR { - Run1MaxR::new((self.bits & 0x7fff) as u16) - } - #[doc = "Bits 16:30 - Run Length 1 Range"] - #[inline(always)] - pub fn run1_rng(&self) -> Run1RngR { - Run1RngR::new(((self.bits >> 16) & 0x7fff) as u16) - } -} -impl W { - #[doc = "Bits 0:14 - Run Length 1 Maximum Limit"] - #[inline(always)] - pub fn run1_max(&mut self) -> Run1MaxW { - Run1MaxW::new(self, 0) - } - #[doc = "Bits 16:30 - Run Length 1 Range"] - #[inline(always)] - pub fn run1_rng(&mut self) -> Run1RngW { - Run1RngW::new(self, 16) - } -} -#[doc = "Statistical Check Run Length 1 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr1l_scr1l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr1l_scr1l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr1lScr1lSpec; -impl crate::RegisterSpec for Scr1lScr1lSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr1l_scr1l::R`](R) reader structure"] -impl crate::Readable for Scr1lScr1lSpec {} -#[doc = "`write(|w| ..)` method takes [`scr1l_scr1l::W`](W) writer structure"] -impl crate::Writable for Scr1lScr1lSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCR1L to value 0x004f_006b"] -impl crate::Resettable for Scr1lScr1lSpec { - const RESET_VALUE: u32 = 0x004f_006b; -} diff --git a/mcxa276-pac/src/trng0/scr2c_scr2c.rs b/mcxa276-pac/src/trng0/scr2c_scr2c.rs deleted file mode 100644 index 8d46cd989..000000000 --- a/mcxa276-pac/src/trng0/scr2c_scr2c.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `SCR2C` reader"] -pub type R = crate::R; -#[doc = "Field `R2_0_CT` reader - Runs of Zero, Length 2 Count"] -pub type R2_0CtR = crate::FieldReader; -#[doc = "Field `R2_1_CT` reader - Runs of One, Length 2 Count"] -pub type R2_1CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:13 - Runs of Zero, Length 2 Count"] - #[inline(always)] - pub fn r2_0_ct(&self) -> R2_0CtR { - R2_0CtR::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bits 16:29 - Runs of One, Length 2 Count"] - #[inline(always)] - pub fn r2_1_ct(&self) -> R2_1CtR { - R2_1CtR::new(((self.bits >> 16) & 0x3fff) as u16) - } -} -#[doc = "Statistical Check Run Length 2 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2c_scr2c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr2cScr2cSpec; -impl crate::RegisterSpec for Scr2cScr2cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr2c_scr2c::R`](R) reader structure"] -impl crate::Readable for Scr2cScr2cSpec {} -#[doc = "`reset()` method sets SCR2C to value 0"] -impl crate::Resettable for Scr2cScr2cSpec {} diff --git a/mcxa276-pac/src/trng0/scr2l_scr2l.rs b/mcxa276-pac/src/trng0/scr2l_scr2l.rs deleted file mode 100644 index 74e9cf12f..000000000 --- a/mcxa276-pac/src/trng0/scr2l_scr2l.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCR2L` reader"] -pub type R = crate::R; -#[doc = "Register `SCR2L` writer"] -pub type W = crate::W; -#[doc = "Field `RUN2_MAX` reader - Run Length 2 Maximum Limit"] -pub type Run2MaxR = crate::FieldReader; -#[doc = "Field `RUN2_MAX` writer - Run Length 2 Maximum Limit"] -pub type Run2MaxW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -#[doc = "Field `RUN2_RNG` reader - Run Length 2 Range"] -pub type Run2RngR = crate::FieldReader; -#[doc = "Field `RUN2_RNG` writer - Run Length 2 Range"] -pub type Run2RngW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; -impl R { - #[doc = "Bits 0:13 - Run Length 2 Maximum Limit"] - #[inline(always)] - pub fn run2_max(&self) -> Run2MaxR { - Run2MaxR::new((self.bits & 0x3fff) as u16) - } - #[doc = "Bits 16:29 - Run Length 2 Range"] - #[inline(always)] - pub fn run2_rng(&self) -> Run2RngR { - Run2RngR::new(((self.bits >> 16) & 0x3fff) as u16) - } -} -impl W { - #[doc = "Bits 0:13 - Run Length 2 Maximum Limit"] - #[inline(always)] - pub fn run2_max(&mut self) -> Run2MaxW { - Run2MaxW::new(self, 0) - } - #[doc = "Bits 16:29 - Run Length 2 Range"] - #[inline(always)] - pub fn run2_rng(&mut self) -> Run2RngW { - Run2RngW::new(self, 16) - } -} -#[doc = "Statistical Check Run Length 2 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr2l_scr2l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr2l_scr2l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr2lScr2lSpec; -impl crate::RegisterSpec for Scr2lScr2lSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr2l_scr2l::R`](R) reader structure"] -impl crate::Readable for Scr2lScr2lSpec {} -#[doc = "`write(|w| ..)` method takes [`scr2l_scr2l::W`](W) writer structure"] -impl crate::Writable for Scr2lScr2lSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCR2L to value 0x0036_003e"] -impl crate::Resettable for Scr2lScr2lSpec { - const RESET_VALUE: u32 = 0x0036_003e; -} diff --git a/mcxa276-pac/src/trng0/scr3c_scr3c.rs b/mcxa276-pac/src/trng0/scr3c_scr3c.rs deleted file mode 100644 index a46b5f78f..000000000 --- a/mcxa276-pac/src/trng0/scr3c_scr3c.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `SCR3C` reader"] -pub type R = crate::R; -#[doc = "Field `R3_0_CT` reader - Runs of Zeroes, Length 3 Count"] -pub type R3_0CtR = crate::FieldReader; -#[doc = "Field `R3_1_CT` reader - Runs of Ones, Length 3 Count"] -pub type R3_1CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:12 - Runs of Zeroes, Length 3 Count"] - #[inline(always)] - pub fn r3_0_ct(&self) -> R3_0CtR { - R3_0CtR::new((self.bits & 0x1fff) as u16) - } - #[doc = "Bits 16:28 - Runs of Ones, Length 3 Count"] - #[inline(always)] - pub fn r3_1_ct(&self) -> R3_1CtR { - R3_1CtR::new(((self.bits >> 16) & 0x1fff) as u16) - } -} -#[doc = "Statistical Check Run Length 3 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3c_scr3c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr3cScr3cSpec; -impl crate::RegisterSpec for Scr3cScr3cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr3c_scr3c::R`](R) reader structure"] -impl crate::Readable for Scr3cScr3cSpec {} -#[doc = "`reset()` method sets SCR3C to value 0"] -impl crate::Resettable for Scr3cScr3cSpec {} diff --git a/mcxa276-pac/src/trng0/scr3l_scr3l.rs b/mcxa276-pac/src/trng0/scr3l_scr3l.rs deleted file mode 100644 index 53c900b2b..000000000 --- a/mcxa276-pac/src/trng0/scr3l_scr3l.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCR3L` reader"] -pub type R = crate::R; -#[doc = "Register `SCR3L` writer"] -pub type W = crate::W; -#[doc = "Field `RUN3_MAX` reader - Run Length 3 Maximum Limit"] -pub type Run3MaxR = crate::FieldReader; -#[doc = "Field `RUN3_MAX` writer - Run Length 3 Maximum Limit"] -pub type Run3MaxW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; -#[doc = "Field `RUN3_RNG` reader - Run Length 3 Range"] -pub type Run3RngR = crate::FieldReader; -#[doc = "Field `RUN3_RNG` writer - Run Length 3 Range"] -pub type Run3RngW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; -impl R { - #[doc = "Bits 0:12 - Run Length 3 Maximum Limit"] - #[inline(always)] - pub fn run3_max(&self) -> Run3MaxR { - Run3MaxR::new((self.bits & 0x1fff) as u16) - } - #[doc = "Bits 16:28 - Run Length 3 Range"] - #[inline(always)] - pub fn run3_rng(&self) -> Run3RngR { - Run3RngR::new(((self.bits >> 16) & 0x1fff) as u16) - } -} -impl W { - #[doc = "Bits 0:12 - Run Length 3 Maximum Limit"] - #[inline(always)] - pub fn run3_max(&mut self) -> Run3MaxW { - Run3MaxW::new(self, 0) - } - #[doc = "Bits 16:28 - Run Length 3 Range"] - #[inline(always)] - pub fn run3_rng(&mut self) -> Run3RngW { - Run3RngW::new(self, 16) - } -} -#[doc = "Statistical Check Run Length 3 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr3l_scr3l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr3l_scr3l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr3lScr3lSpec; -impl crate::RegisterSpec for Scr3lScr3lSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr3l_scr3l::R`](R) reader structure"] -impl crate::Readable for Scr3lScr3lSpec {} -#[doc = "`write(|w| ..)` method takes [`scr3l_scr3l::W`](W) writer structure"] -impl crate::Writable for Scr3lScr3lSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCR3L to value 0x002d_0037"] -impl crate::Resettable for Scr3lScr3lSpec { - const RESET_VALUE: u32 = 0x002d_0037; -} diff --git a/mcxa276-pac/src/trng0/scr4c_scr4c.rs b/mcxa276-pac/src/trng0/scr4c_scr4c.rs deleted file mode 100644 index 9452806e6..000000000 --- a/mcxa276-pac/src/trng0/scr4c_scr4c.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `SCR4C` reader"] -pub type R = crate::R; -#[doc = "Field `R4_0_CT` reader - Runs of Zero, Length 4 Count"] -pub type R4_0CtR = crate::FieldReader; -#[doc = "Field `R4_1_CT` reader - Runs of One, Length 4 Count"] -pub type R4_1CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:11 - Runs of Zero, Length 4 Count"] - #[inline(always)] - pub fn r4_0_ct(&self) -> R4_0CtR { - R4_0CtR::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:27 - Runs of One, Length 4 Count"] - #[inline(always)] - pub fn r4_1_ct(&self) -> R4_1CtR { - R4_1CtR::new(((self.bits >> 16) & 0x0fff) as u16) - } -} -#[doc = "Statistical Check Run Length 4 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4c_scr4c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr4cScr4cSpec; -impl crate::RegisterSpec for Scr4cScr4cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr4c_scr4c::R`](R) reader structure"] -impl crate::Readable for Scr4cScr4cSpec {} -#[doc = "`reset()` method sets SCR4C to value 0"] -impl crate::Resettable for Scr4cScr4cSpec {} diff --git a/mcxa276-pac/src/trng0/scr4l_scr4l.rs b/mcxa276-pac/src/trng0/scr4l_scr4l.rs deleted file mode 100644 index 19992e84f..000000000 --- a/mcxa276-pac/src/trng0/scr4l_scr4l.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCR4L` reader"] -pub type R = crate::R; -#[doc = "Register `SCR4L` writer"] -pub type W = crate::W; -#[doc = "Field `RUN4_MAX` reader - Run Length 4 Maximum Limit"] -pub type Run4MaxR = crate::FieldReader; -#[doc = "Field `RUN4_MAX` writer - Run Length 4 Maximum Limit"] -pub type Run4MaxW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `RUN4_RNG` reader - Run Length 4 Range"] -pub type Run4RngR = crate::FieldReader; -#[doc = "Field `RUN4_RNG` writer - Run Length 4 Range"] -pub type Run4RngW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -impl R { - #[doc = "Bits 0:11 - Run Length 4 Maximum Limit"] - #[inline(always)] - pub fn run4_max(&self) -> Run4MaxR { - Run4MaxR::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:27 - Run Length 4 Range"] - #[inline(always)] - pub fn run4_rng(&self) -> Run4RngR { - Run4RngR::new(((self.bits >> 16) & 0x0fff) as u16) - } -} -impl W { - #[doc = "Bits 0:11 - Run Length 4 Maximum Limit"] - #[inline(always)] - pub fn run4_max(&mut self) -> Run4MaxW { - Run4MaxW::new(self, 0) - } - #[doc = "Bits 16:27 - Run Length 4 Range"] - #[inline(always)] - pub fn run4_rng(&mut self) -> Run4RngW { - Run4RngW::new(self, 16) - } -} -#[doc = "Statistical Check Run Length 4 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr4l_scr4l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr4l_scr4l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr4lScr4lSpec; -impl crate::RegisterSpec for Scr4lScr4lSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr4l_scr4l::R`](R) reader structure"] -impl crate::Readable for Scr4lScr4lSpec {} -#[doc = "`write(|w| ..)` method takes [`scr4l_scr4l::W`](W) writer structure"] -impl crate::Writable for Scr4lScr4lSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCR4L to value 0x001b_001a"] -impl crate::Resettable for Scr4lScr4lSpec { - const RESET_VALUE: u32 = 0x001b_001a; -} diff --git a/mcxa276-pac/src/trng0/scr5c_scr5c.rs b/mcxa276-pac/src/trng0/scr5c_scr5c.rs deleted file mode 100644 index 27396ccfc..000000000 --- a/mcxa276-pac/src/trng0/scr5c_scr5c.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `SCR5C` reader"] -pub type R = crate::R; -#[doc = "Field `R5_0_CT` reader - Runs of Zero, Length 5 Count"] -pub type R5_0CtR = crate::FieldReader; -#[doc = "Field `R5_1_CT` reader - Runs of One, Length 5 Count"] -pub type R5_1CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:10 - Runs of Zero, Length 5 Count"] - #[inline(always)] - pub fn r5_0_ct(&self) -> R5_0CtR { - R5_0CtR::new((self.bits & 0x07ff) as u16) - } - #[doc = "Bits 16:26 - Runs of One, Length 5 Count"] - #[inline(always)] - pub fn r5_1_ct(&self) -> R5_1CtR { - R5_1CtR::new(((self.bits >> 16) & 0x07ff) as u16) - } -} -#[doc = "Statistical Check Run Length 5 Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5c_scr5c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr5cScr5cSpec; -impl crate::RegisterSpec for Scr5cScr5cSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr5c_scr5c::R`](R) reader structure"] -impl crate::Readable for Scr5cScr5cSpec {} -#[doc = "`reset()` method sets SCR5C to value 0"] -impl crate::Resettable for Scr5cScr5cSpec {} diff --git a/mcxa276-pac/src/trng0/scr5l_scr5l.rs b/mcxa276-pac/src/trng0/scr5l_scr5l.rs deleted file mode 100644 index 11aa84108..000000000 --- a/mcxa276-pac/src/trng0/scr5l_scr5l.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCR5L` reader"] -pub type R = crate::R; -#[doc = "Register `SCR5L` writer"] -pub type W = crate::W; -#[doc = "Field `RUN5_MAX` reader - Run Length 5 Maximum Limit"] -pub type Run5MaxR = crate::FieldReader; -#[doc = "Field `RUN5_MAX` writer - Run Length 5 Maximum Limit"] -pub type Run5MaxW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `RUN5_RNG` reader - Run Length 5 Range"] -pub type Run5RngR = crate::FieldReader; -#[doc = "Field `RUN5_RNG` writer - Run Length 5 Range"] -pub type Run5RngW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Run Length 5 Maximum Limit"] - #[inline(always)] - pub fn run5_max(&self) -> Run5MaxR { - Run5MaxR::new((self.bits & 0x07ff) as u16) - } - #[doc = "Bits 16:26 - Run Length 5 Range"] - #[inline(always)] - pub fn run5_rng(&self) -> Run5RngR { - Run5RngR::new(((self.bits >> 16) & 0x07ff) as u16) - } -} -impl W { - #[doc = "Bits 0:10 - Run Length 5 Maximum Limit"] - #[inline(always)] - pub fn run5_max(&mut self) -> Run5MaxW { - Run5MaxW::new(self, 0) - } - #[doc = "Bits 16:26 - Run Length 5 Range"] - #[inline(always)] - pub fn run5_rng(&mut self) -> Run5RngW { - Run5RngW::new(self, 16) - } -} -#[doc = "Statistical Check Run Length 5 Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr5l_scr5l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr5l_scr5l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr5lScr5lSpec; -impl crate::RegisterSpec for Scr5lScr5lSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr5l_scr5l::R`](R) reader structure"] -impl crate::Readable for Scr5lScr5lSpec {} -#[doc = "`write(|w| ..)` method takes [`scr5l_scr5l::W`](W) writer structure"] -impl crate::Writable for Scr5lScr5lSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCR5L to value 0x0013_0012"] -impl crate::Resettable for Scr5lScr5lSpec { - const RESET_VALUE: u32 = 0x0013_0012; -} diff --git a/mcxa276-pac/src/trng0/scr6pc_scr6pc.rs b/mcxa276-pac/src/trng0/scr6pc_scr6pc.rs deleted file mode 100644 index 4b4b3559e..000000000 --- a/mcxa276-pac/src/trng0/scr6pc_scr6pc.rs +++ /dev/null @@ -1,27 +0,0 @@ -#[doc = "Register `SCR6PC` reader"] -pub type R = crate::R; -#[doc = "Field `R6P_0_CT` reader - Runs of Zero, Length 6+ Count"] -pub type R6p0CtR = crate::FieldReader; -#[doc = "Field `R6P_1_CT` reader - Runs of One, Length 6+ Count"] -pub type R6p1CtR = crate::FieldReader; -impl R { - #[doc = "Bits 0:10 - Runs of Zero, Length 6+ Count"] - #[inline(always)] - pub fn r6p_0_ct(&self) -> R6p0CtR { - R6p0CtR::new((self.bits & 0x07ff) as u16) - } - #[doc = "Bits 16:26 - Runs of One, Length 6+ Count"] - #[inline(always)] - pub fn r6p_1_ct(&self) -> R6p1CtR { - R6p1CtR::new(((self.bits >> 16) & 0x07ff) as u16) - } -} -#[doc = "Statistical Check Run Length 6+ Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pc_scr6pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr6pcScr6pcSpec; -impl crate::RegisterSpec for Scr6pcScr6pcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr6pc_scr6pc::R`](R) reader structure"] -impl crate::Readable for Scr6pcScr6pcSpec {} -#[doc = "`reset()` method sets SCR6PC to value 0"] -impl crate::Resettable for Scr6pcScr6pcSpec {} diff --git a/mcxa276-pac/src/trng0/scr6pl_scr6pl.rs b/mcxa276-pac/src/trng0/scr6pl_scr6pl.rs deleted file mode 100644 index 9e6cfd460..000000000 --- a/mcxa276-pac/src/trng0/scr6pl_scr6pl.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SCR6PL` reader"] -pub type R = crate::R; -#[doc = "Register `SCR6PL` writer"] -pub type W = crate::W; -#[doc = "Field `RUN6P_MAX` reader - Run Length 6+ Maximum Limit"] -pub type Run6pMaxR = crate::FieldReader; -#[doc = "Field `RUN6P_MAX` writer - Run Length 6+ Maximum Limit"] -pub type Run6pMaxW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `RUN6P_RNG` reader - Run Length 6+ Range"] -pub type Run6pRngR = crate::FieldReader; -#[doc = "Field `RUN6P_RNG` writer - Run Length 6+ Range"] -pub type Run6pRngW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -impl R { - #[doc = "Bits 0:10 - Run Length 6+ Maximum Limit"] - #[inline(always)] - pub fn run6p_max(&self) -> Run6pMaxR { - Run6pMaxR::new((self.bits & 0x07ff) as u16) - } - #[doc = "Bits 16:26 - Run Length 6+ Range"] - #[inline(always)] - pub fn run6p_rng(&self) -> Run6pRngR { - Run6pRngR::new(((self.bits >> 16) & 0x07ff) as u16) - } -} -impl W { - #[doc = "Bits 0:10 - Run Length 6+ Maximum Limit"] - #[inline(always)] - pub fn run6p_max(&mut self) -> Run6pMaxW { - Run6pMaxW::new(self, 0) - } - #[doc = "Bits 16:26 - Run Length 6+ Range"] - #[inline(always)] - pub fn run6p_rng(&mut self) -> Run6pRngW { - Run6pRngW::new(self, 16) - } -} -#[doc = "Statistical Check Run Length 6+ Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scr6pl_scr6pl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr6pl_scr6pl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Scr6plScr6plSpec; -impl crate::RegisterSpec for Scr6plScr6plSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`scr6pl_scr6pl::R`](R) reader structure"] -impl crate::Readable for Scr6plScr6plSpec {} -#[doc = "`write(|w| ..)` method takes [`scr6pl_scr6pl::W`](W) writer structure"] -impl crate::Writable for Scr6plScr6plSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SCR6PL to value 0x0012_0011"] -impl crate::Resettable for Scr6plScr6plSpec { - const RESET_VALUE: u32 = 0x0012_0011; -} diff --git a/mcxa276-pac/src/trng0/sdctl.rs b/mcxa276-pac/src/trng0/sdctl.rs deleted file mode 100644 index 88338a4d9..000000000 --- a/mcxa276-pac/src/trng0/sdctl.rs +++ /dev/null @@ -1,51 +0,0 @@ -#[doc = "Register `SDCTL` reader"] -pub type R = crate::R; -#[doc = "Register `SDCTL` writer"] -pub type W = crate::W; -#[doc = "Field `SAMP_SIZE` reader - Sample Size"] -pub type SampSizeR = crate::FieldReader; -#[doc = "Field `SAMP_SIZE` writer - Sample Size"] -pub type SampSizeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `ENT_DLY` reader - Entropy Delay"] -pub type EntDlyR = crate::FieldReader; -#[doc = "Field `ENT_DLY` writer - Entropy Delay"] -pub type EntDlyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Sample Size"] - #[inline(always)] - pub fn samp_size(&self) -> SampSizeR { - SampSizeR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - Entropy Delay"] - #[inline(always)] - pub fn ent_dly(&self) -> EntDlyR { - EntDlyR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -impl W { - #[doc = "Bits 0:15 - Sample Size"] - #[inline(always)] - pub fn samp_size(&mut self) -> SampSizeW { - SampSizeW::new(self, 0) - } - #[doc = "Bits 16:31 - Entropy Delay"] - #[inline(always)] - pub fn ent_dly(&mut self) -> EntDlyW { - EntDlyW::new(self, 16) - } -} -#[doc = "Seed Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sdctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SdctlSpec; -impl crate::RegisterSpec for SdctlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sdctl::R`](R) reader structure"] -impl crate::Readable for SdctlSpec {} -#[doc = "`write(|w| ..)` method takes [`sdctl::W`](W) writer structure"] -impl crate::Writable for SdctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SDCTL to value 0x0c80_0200"] -impl crate::Resettable for SdctlSpec { - const RESET_VALUE: u32 = 0x0c80_0200; -} diff --git a/mcxa276-pac/src/trng0/sec_cfg.rs b/mcxa276-pac/src/trng0/sec_cfg.rs deleted file mode 100644 index 091ed14eb..000000000 --- a/mcxa276-pac/src/trng0/sec_cfg.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `SEC_CFG` reader"] -pub type R = crate::R; -#[doc = "Register `SEC_CFG` writer"] -pub type W = crate::W; -#[doc = "If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum NoPrgm { - #[doc = "0: TRNG configuration registers can be modified."] - NoPrgmOff = 0, - #[doc = "1: TRNG configuration registers cannot be modified."] - NoPrgmOn = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: NoPrgm) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `NO_PRGM` reader - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] -pub type NoPrgmR = crate::BitReader; -impl NoPrgmR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> NoPrgm { - match self.bits { - false => NoPrgm::NoPrgmOff, - true => NoPrgm::NoPrgmOn, - } - } - #[doc = "TRNG configuration registers can be modified."] - #[inline(always)] - pub fn is_no_prgm_off(&self) -> bool { - *self == NoPrgm::NoPrgmOff - } - #[doc = "TRNG configuration registers cannot be modified."] - #[inline(always)] - pub fn is_no_prgm_on(&self) -> bool { - *self == NoPrgm::NoPrgmOn - } -} -#[doc = "Field `NO_PRGM` writer - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] -pub type NoPrgmW<'a, REG> = crate::BitWriter<'a, REG, NoPrgm>; -impl<'a, REG> NoPrgmW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "TRNG configuration registers can be modified."] - #[inline(always)] - pub fn no_prgm_off(self) -> &'a mut crate::W { - self.variant(NoPrgm::NoPrgmOff) - } - #[doc = "TRNG configuration registers cannot be modified."] - #[inline(always)] - pub fn no_prgm_on(self) -> &'a mut crate::W { - self.variant(NoPrgm::NoPrgmOn) - } -} -impl R { - #[doc = "Bit 1 - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] - #[inline(always)] - pub fn no_prgm(&self) -> NoPrgmR { - NoPrgmR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed"] - #[inline(always)] - pub fn no_prgm(&mut self) -> NoPrgmW { - NoPrgmW::new(self, 1) - } -} -#[doc = "Security Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SecCfgSpec; -impl crate::RegisterSpec for SecCfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`sec_cfg::R`](R) reader structure"] -impl crate::Readable for SecCfgSpec {} -#[doc = "`write(|w| ..)` method takes [`sec_cfg::W`](W) writer structure"] -impl crate::Writable for SecCfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SEC_CFG to value 0"] -impl crate::Resettable for SecCfgSpec {} diff --git a/mcxa276-pac/src/trng0/status.rs b/mcxa276-pac/src/trng0/status.rs deleted file mode 100644 index 4588f863c..000000000 --- a/mcxa276-pac/src/trng0/status.rs +++ /dev/null @@ -1,676 +0,0 @@ -#[doc = "Register `STATUS` reader"] -pub type R = crate::R; -#[doc = "Test Fail, 1-Bit Run, Sampling 0s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf1br0 { - #[doc = "0: The 1-Bit Run, Sampling 0s Test has passed"] - Disable = 0, - #[doc = "1: The 1-Bit Run, Sampling 0s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf1br0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF1BR0` reader - Test Fail, 1-Bit Run, Sampling 0s."] -pub type Tf1br0R = crate::BitReader; -impl Tf1br0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf1br0 { - match self.bits { - false => Tf1br0::Disable, - true => Tf1br0::Enable, - } - } - #[doc = "The 1-Bit Run, Sampling 0s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf1br0::Disable - } - #[doc = "The 1-Bit Run, Sampling 0s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf1br0::Enable - } -} -#[doc = "Test Fail, 1-Bit Run, Sampling 1s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf1br1 { - #[doc = "0: The 1-Bit Run, Sampling 1s Test has passed"] - Disable = 0, - #[doc = "1: The 1-Bit Run, Sampling 1s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf1br1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF1BR1` reader - Test Fail, 1-Bit Run, Sampling 1s."] -pub type Tf1br1R = crate::BitReader; -impl Tf1br1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf1br1 { - match self.bits { - false => Tf1br1::Disable, - true => Tf1br1::Enable, - } - } - #[doc = "The 1-Bit Run, Sampling 1s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf1br1::Disable - } - #[doc = "The 1-Bit Run, Sampling 1s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf1br1::Enable - } -} -#[doc = "Test Fail, 2-Bit Run, Sampling 0s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf2br0 { - #[doc = "0: The 2-Bit Run, Sampling 0s Test has passed"] - Disable = 0, - #[doc = "1: The 2-Bit Run, Sampling 0s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf2br0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF2BR0` reader - Test Fail, 2-Bit Run, Sampling 0s."] -pub type Tf2br0R = crate::BitReader; -impl Tf2br0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf2br0 { - match self.bits { - false => Tf2br0::Disable, - true => Tf2br0::Enable, - } - } - #[doc = "The 2-Bit Run, Sampling 0s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf2br0::Disable - } - #[doc = "The 2-Bit Run, Sampling 0s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf2br0::Enable - } -} -#[doc = "Test Fail, 2-Bit Run, Sampling 1s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf2br1 { - #[doc = "0: The 2-Bit Run, Sampling 1s Test has passed"] - Disable = 0, - #[doc = "1: The 2-Bit Run, Sampling 1s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf2br1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF2BR1` reader - Test Fail, 2-Bit Run, Sampling 1s."] -pub type Tf2br1R = crate::BitReader; -impl Tf2br1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf2br1 { - match self.bits { - false => Tf2br1::Disable, - true => Tf2br1::Enable, - } - } - #[doc = "The 2-Bit Run, Sampling 1s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf2br1::Disable - } - #[doc = "The 2-Bit Run, Sampling 1s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf2br1::Enable - } -} -#[doc = "Test Fail, 3-Bit Run, Sampling 0s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf3br0 { - #[doc = "0: The 3-Bit Run, Sampling 0s Test has passed"] - Disable = 0, - #[doc = "1: The 3-Bit Run, Sampling 0s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf3br0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF3BR0` reader - Test Fail, 3-Bit Run, Sampling 0s."] -pub type Tf3br0R = crate::BitReader; -impl Tf3br0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf3br0 { - match self.bits { - false => Tf3br0::Disable, - true => Tf3br0::Enable, - } - } - #[doc = "The 3-Bit Run, Sampling 0s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf3br0::Disable - } - #[doc = "The 3-Bit Run, Sampling 0s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf3br0::Enable - } -} -#[doc = "Test Fail\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf3br1 { - #[doc = "0: The 3-Bit Run, Sampling 1s Test has passed"] - Disable = 0, - #[doc = "1: The 3-Bit Run, Sampling 1s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf3br1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF3BR1` reader - Test Fail"] -pub type Tf3br1R = crate::BitReader; -impl Tf3br1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf3br1 { - match self.bits { - false => Tf3br1::Disable, - true => Tf3br1::Enable, - } - } - #[doc = "The 3-Bit Run, Sampling 1s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf3br1::Disable - } - #[doc = "The 3-Bit Run, Sampling 1s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf3br1::Enable - } -} -#[doc = "Test Fail, 4-Bit Run, Sampling 0s\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf4br0 { - #[doc = "0: The 4-Bit Run, Sampling 0s Test has passed"] - Disable = 0, - #[doc = "1: The 4-Bit Run, Sampling 0s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf4br0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF4BR0` reader - Test Fail, 4-Bit Run, Sampling 0s"] -pub type Tf4br0R = crate::BitReader; -impl Tf4br0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf4br0 { - match self.bits { - false => Tf4br0::Disable, - true => Tf4br0::Enable, - } - } - #[doc = "The 4-Bit Run, Sampling 0s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf4br0::Disable - } - #[doc = "The 4-Bit Run, Sampling 0s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf4br0::Enable - } -} -#[doc = "Test Fail, 4-Bit Run, Sampling 1s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf4br1 { - #[doc = "0: The 4-Bit Run, Sampling 1s Test has passed"] - Disable = 0, - #[doc = "1: The 4-Bit Run, Sampling 1s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf4br1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF4BR1` reader - Test Fail, 4-Bit Run, Sampling 1s."] -pub type Tf4br1R = crate::BitReader; -impl Tf4br1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf4br1 { - match self.bits { - false => Tf4br1::Disable, - true => Tf4br1::Enable, - } - } - #[doc = "The 4-Bit Run, Sampling 1s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf4br1::Disable - } - #[doc = "The 4-Bit Run, Sampling 1s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf4br1::Enable - } -} -#[doc = "Test Fail, 5-Bit Run, Sampling 0s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf5br0 { - #[doc = "0: The 5-Bit Run, Sampling 0s Test has passed"] - Disable = 0, - #[doc = "1: The 5-Bit Run, Sampling 0s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf5br0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF5BR0` reader - Test Fail, 5-Bit Run, Sampling 0s."] -pub type Tf5br0R = crate::BitReader; -impl Tf5br0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf5br0 { - match self.bits { - false => Tf5br0::Disable, - true => Tf5br0::Enable, - } - } - #[doc = "The 5-Bit Run, Sampling 0s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf5br0::Disable - } - #[doc = "The 5-Bit Run, Sampling 0s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf5br0::Enable - } -} -#[doc = "Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf5br1 { - #[doc = "0: The 5-Bit Run, Sampling 1s Test has passed"] - Disable = 0, - #[doc = "1: The 5-Bit Run, Sampling 1s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf5br1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF5BR1` reader - Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed."] -pub type Tf5br1R = crate::BitReader; -impl Tf5br1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf5br1 { - match self.bits { - false => Tf5br1::Disable, - true => Tf5br1::Enable, - } - } - #[doc = "The 5-Bit Run, Sampling 1s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf5br1::Disable - } - #[doc = "The 5-Bit Run, Sampling 1s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf5br1::Enable - } -} -#[doc = "Test Fail, 6 Plus Bit Run, Sampling 0s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf6pbr0 { - #[doc = "0: The 6 Plus Bit Run, Sampling 0s Test has passed"] - Disable = 0, - #[doc = "1: the 6 Plus Bit Run, Sampling 0s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf6pbr0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF6PBR0` reader - Test Fail, 6 Plus Bit Run, Sampling 0s."] -pub type Tf6pbr0R = crate::BitReader; -impl Tf6pbr0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf6pbr0 { - match self.bits { - false => Tf6pbr0::Disable, - true => Tf6pbr0::Enable, - } - } - #[doc = "The 6 Plus Bit Run, Sampling 0s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf6pbr0::Disable - } - #[doc = "the 6 Plus Bit Run, Sampling 0s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf6pbr0::Enable - } -} -#[doc = "Test Fail, 6 Plus Bit Run, Sampling 1s.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tf6pbr1 { - #[doc = "0: The 6 Plus Bit Run, Sampling 1s Test has passed"] - Disable = 0, - #[doc = "1: The 6 Plus Bit Run, Sampling 1s Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tf6pbr1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TF6PBR1` reader - Test Fail, 6 Plus Bit Run, Sampling 1s."] -pub type Tf6pbr1R = crate::BitReader; -impl Tf6pbr1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tf6pbr1 { - match self.bits { - false => Tf6pbr1::Disable, - true => Tf6pbr1::Enable, - } - } - #[doc = "The 6 Plus Bit Run, Sampling 1s Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tf6pbr1::Disable - } - #[doc = "The 6 Plus Bit Run, Sampling 1s Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tf6pbr1::Enable - } -} -#[doc = "Test Fail, Sparse Bit.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tfsb { - #[doc = "0: The Sparse Bit Test has passed"] - Disable = 0, - #[doc = "1: The Sparse Bit Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tfsb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TFSB` reader - Test Fail, Sparse Bit."] -pub type TfsbR = crate::BitReader; -impl TfsbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tfsb { - match self.bits { - false => Tfsb::Disable, - true => Tfsb::Enable, - } - } - #[doc = "The Sparse Bit Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tfsb::Disable - } - #[doc = "The Sparse Bit Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tfsb::Enable - } -} -#[doc = "Test Fail, Long Run.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tflr { - #[doc = "0: The Long Run Test has passed"] - Disable = 0, - #[doc = "1: The Long Run Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tflr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TFLR` reader - Test Fail, Long Run."] -pub type TflrR = crate::BitReader; -impl TflrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tflr { - match self.bits { - false => Tflr::Disable, - true => Tflr::Enable, - } - } - #[doc = "The Long Run Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tflr::Disable - } - #[doc = "The Long Run Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tflr::Enable - } -} -#[doc = "Test Fail, Poker.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tfp { - #[doc = "0: The Poker Test has passed"] - Disable = 0, - #[doc = "1: The Poker Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tfp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TFP` reader - Test Fail, Poker."] -pub type TfpR = crate::BitReader; -impl TfpR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tfp { - match self.bits { - false => Tfp::Disable, - true => Tfp::Enable, - } - } - #[doc = "The Poker Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tfp::Disable - } - #[doc = "The Poker Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tfp::Enable - } -} -#[doc = "Test Fail, Mono Bit.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tfmb { - #[doc = "0: The Mono Bit Test has passed"] - Disable = 0, - #[doc = "1: The Mono Bit Test has failed"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tfmb) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TFMB` reader - Test Fail, Mono Bit."] -pub type TfmbR = crate::BitReader; -impl TfmbR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tfmb { - match self.bits { - false => Tfmb::Disable, - true => Tfmb::Enable, - } - } - #[doc = "The Mono Bit Test has passed"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Tfmb::Disable - } - #[doc = "The Mono Bit Test has failed"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Tfmb::Enable - } -} -#[doc = "Field `RETRY_CT` reader - RETRY COUNT"] -pub type RetryCtR = crate::FieldReader; -impl R { - #[doc = "Bit 0 - Test Fail, 1-Bit Run, Sampling 0s."] - #[inline(always)] - pub fn tf1br0(&self) -> Tf1br0R { - Tf1br0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Test Fail, 1-Bit Run, Sampling 1s."] - #[inline(always)] - pub fn tf1br1(&self) -> Tf1br1R { - Tf1br1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Test Fail, 2-Bit Run, Sampling 0s."] - #[inline(always)] - pub fn tf2br0(&self) -> Tf2br0R { - Tf2br0R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Test Fail, 2-Bit Run, Sampling 1s."] - #[inline(always)] - pub fn tf2br1(&self) -> Tf2br1R { - Tf2br1R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Test Fail, 3-Bit Run, Sampling 0s."] - #[inline(always)] - pub fn tf3br0(&self) -> Tf3br0R { - Tf3br0R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Test Fail"] - #[inline(always)] - pub fn tf3br1(&self) -> Tf3br1R { - Tf3br1R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Test Fail, 4-Bit Run, Sampling 0s"] - #[inline(always)] - pub fn tf4br0(&self) -> Tf4br0R { - Tf4br0R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Test Fail, 4-Bit Run, Sampling 1s."] - #[inline(always)] - pub fn tf4br1(&self) -> Tf4br1R { - Tf4br1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Test Fail, 5-Bit Run, Sampling 0s."] - #[inline(always)] - pub fn tf5br0(&self) -> Tf5br0R { - Tf5br0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed."] - #[inline(always)] - pub fn tf5br1(&self) -> Tf5br1R { - Tf5br1R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Test Fail, 6 Plus Bit Run, Sampling 0s."] - #[inline(always)] - pub fn tf6pbr0(&self) -> Tf6pbr0R { - Tf6pbr0R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Test Fail, 6 Plus Bit Run, Sampling 1s."] - #[inline(always)] - pub fn tf6pbr1(&self) -> Tf6pbr1R { - Tf6pbr1R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Test Fail, Sparse Bit."] - #[inline(always)] - pub fn tfsb(&self) -> TfsbR { - TfsbR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Test Fail, Long Run."] - #[inline(always)] - pub fn tflr(&self) -> TflrR { - TflrR::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Test Fail, Poker."] - #[inline(always)] - pub fn tfp(&self) -> TfpR { - TfpR::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Test Fail, Mono Bit."] - #[inline(always)] - pub fn tfmb(&self) -> TfmbR { - TfmbR::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:19 - RETRY COUNT"] - #[inline(always)] - pub fn retry_ct(&self) -> RetryCtR { - RetryCtR::new(((self.bits >> 16) & 0x0f) as u8) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StatusSpec; -impl crate::RegisterSpec for StatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`status::R`](R) reader structure"] -impl crate::Readable for StatusSpec {} -#[doc = "`reset()` method sets STATUS to value 0"] -impl crate::Resettable for StatusSpec {} diff --git a/mcxa276-pac/src/trng0/totsam_totsam.rs b/mcxa276-pac/src/trng0/totsam_totsam.rs deleted file mode 100644 index 6cbf40e9c..000000000 --- a/mcxa276-pac/src/trng0/totsam_totsam.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `TOTSAM` reader"] -pub type R = crate::R; -#[doc = "Field `TOT_SAM` reader - Total Samples"] -pub type TotSamR = crate::FieldReader; -impl R { - #[doc = "Bits 0:19 - Total Samples"] - #[inline(always)] - pub fn tot_sam(&self) -> TotSamR { - TotSamR::new(self.bits & 0x000f_ffff) - } -} -#[doc = "Total Samples Register\n\nYou can [`read`](crate::Reg::read) this register and get [`totsam_totsam::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TotsamTotsamSpec; -impl crate::RegisterSpec for TotsamTotsamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`totsam_totsam::R`](R) reader structure"] -impl crate::Readable for TotsamTotsamSpec {} -#[doc = "`reset()` method sets TOTSAM to value 0"] -impl crate::Resettable for TotsamTotsamSpec {} diff --git a/mcxa276-pac/src/trng0/vid1.rs b/mcxa276-pac/src/trng0/vid1.rs deleted file mode 100644 index 7e3f5bf6e..000000000 --- a/mcxa276-pac/src/trng0/vid1.rs +++ /dev/null @@ -1,132 +0,0 @@ -#[doc = "Register `VID1` reader"] -pub type R = crate::R; -#[doc = "Shows the IP's Minor revision of the TRNG.\n\nValue on reset: 12"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum MinRev { - #[doc = "12: Minor revision number for TRNG."] - MinRevVal = 12, -} -impl From for u8 { - #[inline(always)] - fn from(variant: MinRev) -> Self { - variant as _ - } -} -impl crate::FieldSpec for MinRev { - type Ux = u8; -} -impl crate::IsEnum for MinRev {} -#[doc = "Field `MIN_REV` reader - Shows the IP's Minor revision of the TRNG."] -pub type MinRevR = crate::FieldReader; -impl MinRevR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 12 => Some(MinRev::MinRevVal), - _ => None, - } - } - #[doc = "Minor revision number for TRNG."] - #[inline(always)] - pub fn is_min_rev_val(&self) -> bool { - *self == MinRev::MinRevVal - } -} -#[doc = "Shows the IP's Major revision of the TRNG\n\nValue on reset: 20"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum MajRev { - #[doc = "20: Major revision number for TRNG."] - MajRevVal = 20, -} -impl From for u8 { - #[inline(always)] - fn from(variant: MajRev) -> Self { - variant as _ - } -} -impl crate::FieldSpec for MajRev { - type Ux = u8; -} -impl crate::IsEnum for MajRev {} -#[doc = "Field `MAJ_REV` reader - Shows the IP's Major revision of the TRNG"] -pub type MajRevR = crate::FieldReader; -impl MajRevR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 20 => Some(MajRev::MajRevVal), - _ => None, - } - } - #[doc = "Major revision number for TRNG."] - #[inline(always)] - pub fn is_maj_rev_val(&self) -> bool { - *self == MajRev::MajRevVal - } -} -#[doc = "Shows the IP ID.\n\nValue on reset: 48"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum IpId { - #[doc = "48: ID for TRNG."] - IpIdVal = 48, -} -impl From for u16 { - #[inline(always)] - fn from(variant: IpId) -> Self { - variant as _ - } -} -impl crate::FieldSpec for IpId { - type Ux = u16; -} -impl crate::IsEnum for IpId {} -#[doc = "Field `IP_ID` reader - Shows the IP ID."] -pub type IpIdR = crate::FieldReader; -impl IpIdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 48 => Some(IpId::IpIdVal), - _ => None, - } - } - #[doc = "ID for TRNG."] - #[inline(always)] - pub fn is_ip_id_val(&self) -> bool { - *self == IpId::IpIdVal - } -} -impl R { - #[doc = "Bits 0:7 - Shows the IP's Minor revision of the TRNG."] - #[inline(always)] - pub fn min_rev(&self) -> MinRevR { - MinRevR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Shows the IP's Major revision of the TRNG"] - #[inline(always)] - pub fn maj_rev(&self) -> MajRevR { - MajRevR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:31 - Shows the IP ID."] - #[inline(always)] - pub fn ip_id(&self) -> IpIdR { - IpIdR::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[doc = "Version ID Register (MS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Vid1Spec; -impl crate::RegisterSpec for Vid1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`vid1::R`](R) reader structure"] -impl crate::Readable for Vid1Spec {} -#[doc = "`reset()` method sets VID1 to value 0x0030_140c"] -impl crate::Resettable for Vid1Spec { - const RESET_VALUE: u32 = 0x0030_140c; -} diff --git a/mcxa276-pac/src/trng0/vid2.rs b/mcxa276-pac/src/trng0/vid2.rs deleted file mode 100644 index c32b027a3..000000000 --- a/mcxa276-pac/src/trng0/vid2.rs +++ /dev/null @@ -1,171 +0,0 @@ -#[doc = "Register `VID2` reader"] -pub type R = crate::R; -#[doc = "Shows the IP's Configuaration options for the TRNG.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum ConfigOpt { - #[doc = "0: TRNG_CONFIG_OPT for TRNG."] - ConfigOptVal = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: ConfigOpt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for ConfigOpt { - type Ux = u8; -} -impl crate::IsEnum for ConfigOpt {} -#[doc = "Field `CONFIG_OPT` reader - Shows the IP's Configuaration options for the TRNG."] -pub type ConfigOptR = crate::FieldReader; -impl ConfigOptR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(ConfigOpt::ConfigOptVal), - _ => None, - } - } - #[doc = "TRNG_CONFIG_OPT for TRNG."] - #[inline(always)] - pub fn is_config_opt_val(&self) -> bool { - *self == ConfigOpt::ConfigOptVal - } -} -#[doc = "Shows the IP's ECO revision of the TRNG.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum EcoRev { - #[doc = "0: TRNG_ECO_REV for TRNG."] - EcoRevVal = 0, -} -impl From for u8 { - #[inline(always)] - fn from(variant: EcoRev) -> Self { - variant as _ - } -} -impl crate::FieldSpec for EcoRev { - type Ux = u8; -} -impl crate::IsEnum for EcoRev {} -#[doc = "Field `ECO_REV` reader - Shows the IP's ECO revision of the TRNG."] -pub type EcoRevR = crate::FieldReader; -impl EcoRevR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(EcoRev::EcoRevVal), - _ => None, - } - } - #[doc = "TRNG_ECO_REV for TRNG."] - #[inline(always)] - pub fn is_eco_rev_val(&self) -> bool { - *self == EcoRev::EcoRevVal - } -} -#[doc = "Shows the integration options for the TRNG.\n\nValue on reset: 10"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum IntgOpt { - #[doc = "10: INTG_OPT for TRNG."] - IntgOptVal = 10, -} -impl From for u8 { - #[inline(always)] - fn from(variant: IntgOpt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for IntgOpt { - type Ux = u8; -} -impl crate::IsEnum for IntgOpt {} -#[doc = "Field `INTG_OPT` reader - Shows the integration options for the TRNG."] -pub type IntgOptR = crate::FieldReader; -impl IntgOptR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 10 => Some(IntgOpt::IntgOptVal), - _ => None, - } - } - #[doc = "INTG_OPT for TRNG."] - #[inline(always)] - pub fn is_intg_opt_val(&self) -> bool { - *self == IntgOpt::IntgOptVal - } -} -#[doc = "Shows the ERA of the TRNG.\n\nValue on reset: 12"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Era { - #[doc = "12: ERA of the TRNG."] - EraVal = 12, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Era) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Era { - type Ux = u8; -} -impl crate::IsEnum for Era {} -#[doc = "Field `ERA` reader - Shows the ERA of the TRNG."] -pub type EraR = crate::FieldReader; -impl EraR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 12 => Some(Era::EraVal), - _ => None, - } - } - #[doc = "ERA of the TRNG."] - #[inline(always)] - pub fn is_era_val(&self) -> bool { - *self == Era::EraVal - } -} -impl R { - #[doc = "Bits 0:7 - Shows the IP's Configuaration options for the TRNG."] - #[inline(always)] - pub fn config_opt(&self) -> ConfigOptR { - ConfigOptR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Shows the IP's ECO revision of the TRNG."] - #[inline(always)] - pub fn eco_rev(&self) -> EcoRevR { - EcoRevR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Shows the integration options for the TRNG."] - #[inline(always)] - pub fn intg_opt(&self) -> IntgOptR { - IntgOptR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Shows the ERA of the TRNG."] - #[inline(always)] - pub fn era(&self) -> EraR { - EraR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID Register (LS)\n\nYou can [`read`](crate::Reg::read) this register and get [`vid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Vid2Spec; -impl crate::RegisterSpec for Vid2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`vid2::R`](R) reader structure"] -impl crate::Readable for Vid2Spec {} -#[doc = "`reset()` method sets VID2 to value 0x0c0a_0000"] -impl crate::Resettable for Vid2Spec { - const RESET_VALUE: u32 = 0x0c0a_0000; -} diff --git a/mcxa276-pac/src/udf0.rs b/mcxa276-pac/src/udf0.rs deleted file mode 100644 index 81a595164..000000000 --- a/mcxa276-pac/src/udf0.rs +++ /dev/null @@ -1,50 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - udf_ctrl: UdfCtrl, - udf_status: UdfStatus, - udf_wr_data: UdfWrData, - udf_rd_data: UdfRdData, -} -impl RegisterBlock { - #[doc = "0x00 - Control register"] - #[inline(always)] - pub const fn udf_ctrl(&self) -> &UdfCtrl { - &self.udf_ctrl - } - #[doc = "0x04 - Status register"] - #[inline(always)] - pub const fn udf_status(&self) -> &UdfStatus { - &self.udf_status - } - #[doc = "0x08 - Data In Register"] - #[inline(always)] - pub const fn udf_wr_data(&self) -> &UdfWrData { - &self.udf_wr_data - } - #[doc = "0x0c - Data Out Register"] - #[inline(always)] - pub const fn udf_rd_data(&self) -> &UdfRdData { - &self.udf_rd_data - } -} -#[doc = "udf_ctrl (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_ctrl`] module"] -#[doc(alias = "udf_ctrl")] -pub type UdfCtrl = crate::Reg; -#[doc = "Control register"] -pub mod udf_ctrl; -#[doc = "udf_status (r) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_status`] module"] -#[doc(alias = "udf_status")] -pub type UdfStatus = crate::Reg; -#[doc = "Status register"] -pub mod udf_status; -#[doc = "udf_wr_data (w) register accessor: Data In Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_wr_data::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_wr_data`] module"] -#[doc(alias = "udf_wr_data")] -pub type UdfWrData = crate::Reg; -#[doc = "Data In Register"] -pub mod udf_wr_data; -#[doc = "udf_rd_data (r) register accessor: Data Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_rd_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@udf_rd_data`] module"] -#[doc(alias = "udf_rd_data")] -pub type UdfRdData = crate::Reg; -#[doc = "Data Out Register"] -pub mod udf_rd_data; diff --git a/mcxa276-pac/src/udf0/udf_ctrl.rs b/mcxa276-pac/src/udf0/udf_ctrl.rs deleted file mode 100644 index 5a6939125..000000000 --- a/mcxa276-pac/src/udf0/udf_ctrl.rs +++ /dev/null @@ -1,128 +0,0 @@ -#[doc = "Register `udf_ctrl` reader"] -pub type R = crate::R; -#[doc = "Register `udf_ctrl` writer"] -pub type W = crate::W; -#[doc = "Field `salt` reader - Bits are internally XORed with i_custom"] -pub type SaltR = crate::FieldReader; -#[doc = "Field `salt` writer - Bits are internally XORed with i_custom"] -pub type SaltW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `lock` reader - Lock access to UDF"] -pub type LockR = crate::FieldReader; -#[doc = "Field `lock` writer - Lock access to UDF"] -pub type LockW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `reserved21` reader - RFU"] -pub type Reserved21R = crate::FieldReader; -#[doc = "Field `reserved21` writer - RFU"] -pub type Reserved21W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `udf_en` reader - Enable the UDF block"] -pub type UdfEnR = crate::FieldReader; -#[doc = "Field `udf_en` writer - Enable the UDF block"] -pub type UdfEnW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `reserved25` reader - RFU"] -pub type Reserved25R = crate::BitReader; -#[doc = "Field `reserved25` writer - RFU"] -pub type Reserved25W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `reserved27` reader - RFU"] -pub type Reserved27R = crate::FieldReader; -#[doc = "Field `reserved27` writer - RFU"] -pub type Reserved27W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `flush` reader - Flush UDF and return to reset state"] -pub type FlushR = crate::FieldReader; -#[doc = "Field `flush` writer - Flush UDF and return to reset state"] -pub type FlushW<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `reserved31` reader - reserved"] -pub type Reserved31R = crate::BitReader; -impl R { - #[doc = "Bits 0:15 - Bits are internally XORed with i_custom"] - #[inline(always)] - pub fn salt(&self) -> SaltR { - SaltR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:18 - Lock access to UDF"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 19:21 - RFU"] - #[inline(always)] - pub fn reserved21(&self) -> Reserved21R { - Reserved21R::new(((self.bits >> 19) & 7) as u8) - } - #[doc = "Bits 22:24 - Enable the UDF block"] - #[inline(always)] - pub fn udf_en(&self) -> UdfEnR { - UdfEnR::new(((self.bits >> 22) & 7) as u8) - } - #[doc = "Bit 25 - RFU"] - #[inline(always)] - pub fn reserved25(&self) -> Reserved25R { - Reserved25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bits 26:27 - RFU"] - #[inline(always)] - pub fn reserved27(&self) -> Reserved27R { - Reserved27R::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:30 - Flush UDF and return to reset state"] - #[inline(always)] - pub fn flush(&self) -> FlushR { - FlushR::new(((self.bits >> 28) & 7) as u8) - } - #[doc = "Bit 31 - reserved"] - #[inline(always)] - pub fn reserved31(&self) -> Reserved31R { - Reserved31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:15 - Bits are internally XORed with i_custom"] - #[inline(always)] - pub fn salt(&mut self) -> SaltW { - SaltW::new(self, 0) - } - #[doc = "Bits 16:18 - Lock access to UDF"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 16) - } - #[doc = "Bits 19:21 - RFU"] - #[inline(always)] - pub fn reserved21(&mut self) -> Reserved21W { - Reserved21W::new(self, 19) - } - #[doc = "Bits 22:24 - Enable the UDF block"] - #[inline(always)] - pub fn udf_en(&mut self) -> UdfEnW { - UdfEnW::new(self, 22) - } - #[doc = "Bit 25 - RFU"] - #[inline(always)] - pub fn reserved25(&mut self) -> Reserved25W { - Reserved25W::new(self, 25) - } - #[doc = "Bits 26:27 - RFU"] - #[inline(always)] - pub fn reserved27(&mut self) -> Reserved27W { - Reserved27W::new(self, 26) - } - #[doc = "Bits 28:30 - Flush UDF and return to reset state"] - #[inline(always)] - pub fn flush(&mut self) -> FlushW { - FlushW::new(self, 28) - } -} -#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UdfCtrlSpec; -impl crate::RegisterSpec for UdfCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`udf_ctrl::R`](R) reader structure"] -impl crate::Readable for UdfCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`udf_ctrl::W`](W) writer structure"] -impl crate::Writable for UdfCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets udf_ctrl to value 0x0080_0000"] -impl crate::Resettable for UdfCtrlSpec { - const RESET_VALUE: u32 = 0x0080_0000; -} diff --git a/mcxa276-pac/src/udf0/udf_rd_data.rs b/mcxa276-pac/src/udf0/udf_rd_data.rs deleted file mode 100644 index 0dd404bc3..000000000 --- a/mcxa276-pac/src/udf0/udf_rd_data.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `udf_rd_data` reader"] -pub type R = crate::R; -#[doc = "Field `o_dat` reader - no description available"] -pub type ODatR = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - no description available"] - #[inline(always)] - pub fn o_dat(&self) -> ODatR { - ODatR::new(self.bits) - } -} -#[doc = "Data Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_rd_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UdfRdDataSpec; -impl crate::RegisterSpec for UdfRdDataSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`udf_rd_data::R`](R) reader structure"] -impl crate::Readable for UdfRdDataSpec {} -#[doc = "`reset()` method sets udf_rd_data to value 0"] -impl crate::Resettable for UdfRdDataSpec {} diff --git a/mcxa276-pac/src/udf0/udf_status.rs b/mcxa276-pac/src/udf0/udf_status.rs deleted file mode 100644 index 5365e145e..000000000 --- a/mcxa276-pac/src/udf0/udf_status.rs +++ /dev/null @@ -1,100 +0,0 @@ -#[doc = "Register `udf_status` reader"] -pub type R = crate::R; -#[doc = "Status bits\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum OStatus { - #[doc = "1: 5'b00001 = Reset"] - Reset = 1, - #[doc = "2: 5'b00010 = Init"] - Init = 2, - #[doc = "4: 5'b00100 = Warmup"] - Warmup = 4, - #[doc = "8: 5'b01000 = Ready"] - Ready = 8, - #[doc = "16: 5'b10000 = Error"] - Error = 16, -} -impl From for u8 { - #[inline(always)] - fn from(variant: OStatus) -> Self { - variant as _ - } -} -impl crate::FieldSpec for OStatus { - type Ux = u8; -} -impl crate::IsEnum for OStatus {} -#[doc = "Field `o_status` reader - Status bits"] -pub type OStatusR = crate::FieldReader; -impl OStatusR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(OStatus::Reset), - 2 => Some(OStatus::Init), - 4 => Some(OStatus::Warmup), - 8 => Some(OStatus::Ready), - 16 => Some(OStatus::Error), - _ => None, - } - } - #[doc = "5'b00001 = Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == OStatus::Reset - } - #[doc = "5'b00010 = Init"] - #[inline(always)] - pub fn is_init(&self) -> bool { - *self == OStatus::Init - } - #[doc = "5'b00100 = Warmup"] - #[inline(always)] - pub fn is_warmup(&self) -> bool { - *self == OStatus::Warmup - } - #[doc = "5'b01000 = Ready"] - #[inline(always)] - pub fn is_ready(&self) -> bool { - *self == OStatus::Ready - } - #[doc = "5'b10000 = Error"] - #[inline(always)] - pub fn is_error(&self) -> bool { - *self == OStatus::Error - } -} -#[doc = "Field `rsv` reader - RFU"] -pub type RsvR = crate::FieldReader; -#[doc = "Field `o_wait` reader - Indicates UDF is processing data"] -pub type OWaitR = crate::BitReader; -impl R { - #[doc = "Bits 0:4 - Status bits"] - #[inline(always)] - pub fn o_status(&self) -> OStatusR { - OStatusR::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:30 - RFU"] - #[inline(always)] - pub fn rsv(&self) -> RsvR { - RsvR::new((self.bits >> 5) & 0x03ff_ffff) - } - #[doc = "Bit 31 - Indicates UDF is processing data"] - #[inline(always)] - pub fn o_wait(&self) -> OWaitR { - OWaitR::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`udf_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UdfStatusSpec; -impl crate::RegisterSpec for UdfStatusSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`udf_status::R`](R) reader structure"] -impl crate::Readable for UdfStatusSpec {} -#[doc = "`reset()` method sets udf_status to value 0x01"] -impl crate::Resettable for UdfStatusSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/udf0/udf_wr_data.rs b/mcxa276-pac/src/udf0/udf_wr_data.rs deleted file mode 100644 index b03074374..000000000 --- a/mcxa276-pac/src/udf0/udf_wr_data.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `udf_wr_data` writer"] -pub type W = crate::W; -#[doc = "Field `i_dat` writer - no description available"] -pub type IDatW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl W { - #[doc = "Bits 0:31 - no description available"] - #[inline(always)] - pub fn i_dat(&mut self) -> IDatW { - IDatW::new(self, 0) - } -} -#[doc = "Data In Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`udf_wr_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UdfWrDataSpec; -impl crate::RegisterSpec for UdfWrDataSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`udf_wr_data::W`](W) writer structure"] -impl crate::Writable for UdfWrDataSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets udf_wr_data to value 0"] -impl crate::Resettable for UdfWrDataSpec {} diff --git a/mcxa276-pac/src/usb0.rs b/mcxa276-pac/src/usb0.rs deleted file mode 100644 index 5b8a661a2..000000000 --- a/mcxa276-pac/src/usb0.rs +++ /dev/null @@ -1,493 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - perid: Perid, - _reserved1: [u8; 0x03], - idcomp: Idcomp, - _reserved2: [u8; 0x03], - rev: Rev, - _reserved3: [u8; 0x03], - addinfo: Addinfo, - _reserved4: [u8; 0x03], - otgistat: Otgistat, - _reserved5: [u8; 0x03], - otgicr: Otgicr, - _reserved6: [u8; 0x03], - otgstat: Otgstat, - _reserved7: [u8; 0x03], - otgctl: Otgctl, - _reserved8: [u8; 0x63], - istat: Istat, - _reserved9: [u8; 0x03], - inten: Inten, - _reserved10: [u8; 0x03], - errstat: Errstat, - _reserved11: [u8; 0x03], - erren: Erren, - _reserved12: [u8; 0x03], - stat: Stat, - _reserved13: [u8; 0x03], - ctl: Ctl, - _reserved14: [u8; 0x03], - addr: Addr, - _reserved15: [u8; 0x03], - bdtpage1: Bdtpage1, - _reserved16: [u8; 0x03], - frmnuml: Frmnuml, - _reserved17: [u8; 0x03], - frmnumh: Frmnumh, - _reserved18: [u8; 0x03], - token: Token, - _reserved19: [u8; 0x03], - softhld: Softhld, - _reserved20: [u8; 0x03], - bdtpage2: Bdtpage2, - _reserved21: [u8; 0x03], - bdtpage3: Bdtpage3, - _reserved22: [u8; 0x0b], - endpoint: (), - _reserved23: [u8; 0x40], - usbctrl: Usbctrl, - _reserved24: [u8; 0x03], - observe: Observe, - _reserved25: [u8; 0x03], - control: Control, - _reserved26: [u8; 0x03], - usbtrc0: Usbtrc0, - _reserved27: [u8; 0x07], - usbfrmadjust: Usbfrmadjust, - _reserved28: [u8; 0x0f], - keep_alive_ctrl_rsvd: KeepAliveCtrlRsvd, - _reserved29: [u8; 0x03], - keep_alive_wkctrl_rsvd: KeepAliveWkctrlRsvd, - _reserved30: [u8; 0x03], - miscctrl: Miscctrl, - _reserved31: [u8; 0x03], - stall_il_dis: StallIlDis, - _reserved32: [u8; 0x03], - stall_ih_dis: StallIhDis, - _reserved33: [u8; 0x03], - stall_ol_dis: StallOlDis, - _reserved34: [u8; 0x03], - stall_oh_dis: StallOhDis, - _reserved35: [u8; 0x03], - clk_recover_ctrl: ClkRecoverCtrl, - _reserved36: [u8; 0x03], - clk_recover_irc_en: ClkRecoverIrcEn, - _reserved37: [u8; 0x0f], - clk_recover_int_en: ClkRecoverIntEn, - _reserved38: [u8; 0x07], - clk_recover_int_status: ClkRecoverIntStatus, -} -impl RegisterBlock { - #[doc = "0x00 - Peripheral ID"] - #[inline(always)] - pub const fn perid(&self) -> &Perid { - &self.perid - } - #[doc = "0x04 - Peripheral ID Complement"] - #[inline(always)] - pub const fn idcomp(&self) -> &Idcomp { - &self.idcomp - } - #[doc = "0x08 - Peripheral Revision"] - #[inline(always)] - pub const fn rev(&self) -> &Rev { - &self.rev - } - #[doc = "0x0c - Peripheral Additional Information"] - #[inline(always)] - pub const fn addinfo(&self) -> &Addinfo { - &self.addinfo - } - #[doc = "0x10 - OTG Interrupt Status"] - #[inline(always)] - pub const fn otgistat(&self) -> &Otgistat { - &self.otgistat - } - #[doc = "0x14 - OTG Interrupt Control"] - #[inline(always)] - pub const fn otgicr(&self) -> &Otgicr { - &self.otgicr - } - #[doc = "0x18 - OTG Status"] - #[inline(always)] - pub const fn otgstat(&self) -> &Otgstat { - &self.otgstat - } - #[doc = "0x1c - OTG Control"] - #[inline(always)] - pub const fn otgctl(&self) -> &Otgctl { - &self.otgctl - } - #[doc = "0x80 - Interrupt Status"] - #[inline(always)] - pub const fn istat(&self) -> &Istat { - &self.istat - } - #[doc = "0x84 - Interrupt Enable"] - #[inline(always)] - pub const fn inten(&self) -> &Inten { - &self.inten - } - #[doc = "0x88 - Error Interrupt Status"] - #[inline(always)] - pub const fn errstat(&self) -> &Errstat { - &self.errstat - } - #[doc = "0x8c - Error Interrupt Enable"] - #[inline(always)] - pub const fn erren(&self) -> &Erren { - &self.erren - } - #[doc = "0x90 - Status"] - #[inline(always)] - pub const fn stat(&self) -> &Stat { - &self.stat - } - #[doc = "0x94 - Control"] - #[inline(always)] - pub const fn ctl(&self) -> &Ctl { - &self.ctl - } - #[doc = "0x98 - Address"] - #[inline(always)] - pub const fn addr(&self) -> &Addr { - &self.addr - } - #[doc = "0x9c - BDT Page 1"] - #[inline(always)] - pub const fn bdtpage1(&self) -> &Bdtpage1 { - &self.bdtpage1 - } - #[doc = "0xa0 - Frame Number Register Low"] - #[inline(always)] - pub const fn frmnuml(&self) -> &Frmnuml { - &self.frmnuml - } - #[doc = "0xa4 - Frame Number Register High"] - #[inline(always)] - pub const fn frmnumh(&self) -> &Frmnumh { - &self.frmnumh - } - #[doc = "0xa8 - Token"] - #[inline(always)] - pub const fn token(&self) -> &Token { - &self.token - } - #[doc = "0xac - SOF Threshold"] - #[inline(always)] - pub const fn softhld(&self) -> &Softhld { - &self.softhld - } - #[doc = "0xb0 - BDT Page 2"] - #[inline(always)] - pub const fn bdtpage2(&self) -> &Bdtpage2 { - &self.bdtpage2 - } - #[doc = "0xb4 - BDT Page 3"] - #[inline(always)] - pub const fn bdtpage3(&self) -> &Bdtpage3 { - &self.bdtpage3 - } - #[doc = "0xc0..0xd0 - Array of registers: ENDPT"] - #[inline(always)] - pub const fn endpoint(&self, n: usize) -> &Endpoint { - #[allow(clippy::no_effect)] - [(); 16][n]; - unsafe { - &*core::ptr::from_ref(self) - .cast::() - .add(192) - .add(4 * n) - .cast() - } - } - #[doc = "Iterator for array of:"] - #[doc = "0xc0..0xd0 - Array of registers: ENDPT"] - #[inline(always)] - pub fn endpoint_iter(&self) -> impl Iterator { - (0..16).map(move |n| unsafe { - &*core::ptr::from_ref(self) - .cast::() - .add(192) - .add(4 * n) - .cast() - }) - } - #[doc = "0x100 - USB Control"] - #[inline(always)] - pub const fn usbctrl(&self) -> &Usbctrl { - &self.usbctrl - } - #[doc = "0x104 - USB OTG Observe"] - #[inline(always)] - pub const fn observe(&self) -> &Observe { - &self.observe - } - #[doc = "0x108 - USB OTG Control"] - #[inline(always)] - pub const fn control(&self) -> &Control { - &self.control - } - #[doc = "0x10c - USB Transceiver Control 0"] - #[inline(always)] - pub const fn usbtrc0(&self) -> &Usbtrc0 { - &self.usbtrc0 - } - #[doc = "0x114 - Frame Adjust"] - #[inline(always)] - pub const fn usbfrmadjust(&self) -> &Usbfrmadjust { - &self.usbfrmadjust - } - #[doc = "0x124 - Reserved"] - #[inline(always)] - pub const fn keep_alive_ctrl_rsvd(&self) -> &KeepAliveCtrlRsvd { - &self.keep_alive_ctrl_rsvd - } - #[doc = "0x128 - Reserved"] - #[inline(always)] - pub const fn keep_alive_wkctrl_rsvd(&self) -> &KeepAliveWkctrlRsvd { - &self.keep_alive_wkctrl_rsvd - } - #[doc = "0x12c - Miscellaneous Control"] - #[inline(always)] - pub const fn miscctrl(&self) -> &Miscctrl { - &self.miscctrl - } - #[doc = "0x130 - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction"] - #[inline(always)] - pub const fn stall_il_dis(&self) -> &StallIlDis { - &self.stall_il_dis - } - #[doc = "0x134 - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction"] - #[inline(always)] - pub const fn stall_ih_dis(&self) -> &StallIhDis { - &self.stall_ih_dis - } - #[doc = "0x138 - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction"] - #[inline(always)] - pub const fn stall_ol_dis(&self) -> &StallOlDis { - &self.stall_ol_dis - } - #[doc = "0x13c - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction"] - #[inline(always)] - pub const fn stall_oh_dis(&self) -> &StallOhDis { - &self.stall_oh_dis - } - #[doc = "0x140 - USB Clock Recovery Control"] - #[inline(always)] - pub const fn clk_recover_ctrl(&self) -> &ClkRecoverCtrl { - &self.clk_recover_ctrl - } - #[doc = "0x144 - FIRC Oscillator Enable"] - #[inline(always)] - pub const fn clk_recover_irc_en(&self) -> &ClkRecoverIrcEn { - &self.clk_recover_irc_en - } - #[doc = "0x154 - Clock Recovery Combined Interrupt Enable"] - #[inline(always)] - pub const fn clk_recover_int_en(&self) -> &ClkRecoverIntEn { - &self.clk_recover_int_en - } - #[doc = "0x15c - Clock Recovery Separated Interrupt Status"] - #[inline(always)] - pub const fn clk_recover_int_status(&self) -> &ClkRecoverIntStatus { - &self.clk_recover_int_status - } -} -#[doc = "PERID (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] -#[doc(alias = "PERID")] -pub type Perid = crate::Reg; -#[doc = "Peripheral ID"] -pub mod perid; -#[doc = "IDCOMP (r) register accessor: Peripheral ID Complement\n\nYou can [`read`](crate::Reg::read) this register and get [`idcomp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idcomp`] module"] -#[doc(alias = "IDCOMP")] -pub type Idcomp = crate::Reg; -#[doc = "Peripheral ID Complement"] -pub mod idcomp; -#[doc = "REV (r) register accessor: Peripheral Revision\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rev`] module"] -#[doc(alias = "REV")] -pub type Rev = crate::Reg; -#[doc = "Peripheral Revision"] -pub mod rev; -#[doc = "ADDINFO (r) register accessor: Peripheral Additional Information\n\nYou can [`read`](crate::Reg::read) this register and get [`addinfo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addinfo`] module"] -#[doc(alias = "ADDINFO")] -pub type Addinfo = crate::Reg; -#[doc = "Peripheral Additional Information"] -pub mod addinfo; -#[doc = "OTGISTAT (rw) register accessor: OTG Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgistat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgistat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgistat`] module"] -#[doc(alias = "OTGISTAT")] -pub type Otgistat = crate::Reg; -#[doc = "OTG Interrupt Status"] -pub mod otgistat; -#[doc = "OTGICR (rw) register accessor: OTG Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgicr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgicr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgicr`] module"] -#[doc(alias = "OTGICR")] -pub type Otgicr = crate::Reg; -#[doc = "OTG Interrupt Control"] -pub mod otgicr; -#[doc = "OTGSTAT (r) register accessor: OTG Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgstat`] module"] -#[doc(alias = "OTGSTAT")] -pub type Otgstat = crate::Reg; -#[doc = "OTG Status"] -pub mod otgstat; -#[doc = "OTGCTL (rw) register accessor: OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgctl`] module"] -#[doc(alias = "OTGCTL")] -pub type Otgctl = crate::Reg; -#[doc = "OTG Control"] -pub mod otgctl; -#[doc = "ISTAT (rw) register accessor: Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`istat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`istat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@istat`] module"] -#[doc(alias = "ISTAT")] -pub type Istat = crate::Reg; -#[doc = "Interrupt Status"] -pub mod istat; -#[doc = "INTEN (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`] module"] -#[doc(alias = "INTEN")] -pub type Inten = crate::Reg; -#[doc = "Interrupt Enable"] -pub mod inten; -#[doc = "ERRSTAT (rw) register accessor: Error Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errstat`] module"] -#[doc(alias = "ERRSTAT")] -pub type Errstat = crate::Reg; -#[doc = "Error Interrupt Status"] -pub mod errstat; -#[doc = "ERREN (rw) register accessor: Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@erren`] module"] -#[doc(alias = "ERREN")] -pub type Erren = crate::Reg; -#[doc = "Error Interrupt Enable"] -pub mod erren; -#[doc = "STAT (r) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] -#[doc(alias = "STAT")] -pub type Stat = crate::Reg; -#[doc = "Status"] -pub mod stat; -#[doc = "CTL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`] module"] -#[doc(alias = "CTL")] -pub type Ctl = crate::Reg; -#[doc = "Control"] -pub mod ctl; -#[doc = "ADDR (rw) register accessor: Address\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`] module"] -#[doc(alias = "ADDR")] -pub type Addr = crate::Reg; -#[doc = "Address"] -pub mod addr; -#[doc = "BDTPAGE1 (rw) register accessor: BDT Page 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtpage1`] module"] -#[doc(alias = "BDTPAGE1")] -pub type Bdtpage1 = crate::Reg; -#[doc = "BDT Page 1"] -pub mod bdtpage1; -#[doc = "FRMNUML (r) register accessor: Frame Number Register Low\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnuml::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frmnuml`] module"] -#[doc(alias = "FRMNUML")] -pub type Frmnuml = crate::Reg; -#[doc = "Frame Number Register Low"] -pub mod frmnuml; -#[doc = "FRMNUMH (r) register accessor: Frame Number Register High\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnumh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frmnumh`] module"] -#[doc(alias = "FRMNUMH")] -pub type Frmnumh = crate::Reg; -#[doc = "Frame Number Register High"] -pub mod frmnumh; -#[doc = "TOKEN (rw) register accessor: Token\n\nYou can [`read`](crate::Reg::read) this register and get [`token::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`token::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@token`] module"] -#[doc(alias = "TOKEN")] -pub type Token = crate::Reg; -#[doc = "Token"] -pub mod token; -#[doc = "SOFTHLD (rw) register accessor: SOF Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`softhld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`softhld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@softhld`] module"] -#[doc(alias = "SOFTHLD")] -pub type Softhld = crate::Reg; -#[doc = "SOF Threshold"] -pub mod softhld; -#[doc = "BDTPAGE2 (rw) register accessor: BDT Page 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtpage2`] module"] -#[doc(alias = "BDTPAGE2")] -pub type Bdtpage2 = crate::Reg; -#[doc = "BDT Page 2"] -pub mod bdtpage2; -#[doc = "BDTPAGE3 (rw) register accessor: BDT Page 3\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtpage3`] module"] -#[doc(alias = "BDTPAGE3")] -pub type Bdtpage3 = crate::Reg; -#[doc = "BDT Page 3"] -pub mod bdtpage3; -#[doc = "Array of registers: ENDPT"] -pub use self::endpoint::Endpoint; -#[doc = r"Cluster"] -#[doc = "Array of registers: ENDPT"] -pub mod endpoint; -#[doc = "USBCTRL (rw) register accessor: USB Control\n\nYou can [`read`](crate::Reg::read) this register and get [`usbctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbctrl`] module"] -#[doc(alias = "USBCTRL")] -pub type Usbctrl = crate::Reg; -#[doc = "USB Control"] -pub mod usbctrl; -#[doc = "OBSERVE (r) register accessor: USB OTG Observe\n\nYou can [`read`](crate::Reg::read) this register and get [`observe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@observe`] module"] -#[doc(alias = "OBSERVE")] -pub type Observe = crate::Reg; -#[doc = "USB OTG Observe"] -pub mod observe; -#[doc = "CONTROL (rw) register accessor: USB OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`] module"] -#[doc(alias = "CONTROL")] -pub type Control = crate::Reg; -#[doc = "USB OTG Control"] -pub mod control; -#[doc = "USBTRC0 (rw) register accessor: USB Transceiver Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`usbtrc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbtrc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbtrc0`] module"] -#[doc(alias = "USBTRC0")] -pub type Usbtrc0 = crate::Reg; -#[doc = "USB Transceiver Control 0"] -pub mod usbtrc0; -#[doc = "USBFRMADJUST (rw) register accessor: Frame Adjust\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfrmadjust::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfrmadjust::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbfrmadjust`] module"] -#[doc(alias = "USBFRMADJUST")] -pub type Usbfrmadjust = crate::Reg; -#[doc = "Frame Adjust"] -pub mod usbfrmadjust; -#[doc = "KEEP_ALIVE_CTRL_RSVD (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_ctrl_rsvd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_ctrl_rsvd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keep_alive_ctrl_rsvd`] module"] -#[doc(alias = "KEEP_ALIVE_CTRL_RSVD")] -pub type KeepAliveCtrlRsvd = crate::Reg; -#[doc = "Reserved"] -pub mod keep_alive_ctrl_rsvd; -#[doc = "KEEP_ALIVE_WKCTRL_RSVD (rw) register accessor: Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_wkctrl_rsvd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_wkctrl_rsvd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keep_alive_wkctrl_rsvd`] module"] -#[doc(alias = "KEEP_ALIVE_WKCTRL_RSVD")] -pub type KeepAliveWkctrlRsvd = crate::Reg; -#[doc = "Reserved"] -pub mod keep_alive_wkctrl_rsvd; -#[doc = "MISCCTRL (rw) register accessor: Miscellaneous Control\n\nYou can [`read`](crate::Reg::read) this register and get [`miscctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`miscctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscctrl`] module"] -#[doc(alias = "MISCCTRL")] -pub type Miscctrl = crate::Reg; -#[doc = "Miscellaneous Control"] -pub mod miscctrl; -#[doc = "STALL_IL_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_il_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_il_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_il_dis`] module"] -#[doc(alias = "STALL_IL_DIS")] -pub type StallIlDis = crate::Reg; -#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction"] -pub mod stall_il_dis; -#[doc = "STALL_IH_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ih_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ih_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_ih_dis`] module"] -#[doc(alias = "STALL_IH_DIS")] -pub type StallIhDis = crate::Reg; -#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction"] -pub mod stall_ih_dis; -#[doc = "STALL_OL_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ol_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ol_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_ol_dis`] module"] -#[doc(alias = "STALL_OL_DIS")] -pub type StallOlDis = crate::Reg; -#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction"] -pub mod stall_ol_dis; -#[doc = "STALL_OH_DIS (rw) register accessor: Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_oh_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_oh_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_oh_dis`] module"] -#[doc(alias = "STALL_OH_DIS")] -pub type StallOhDis = crate::Reg; -#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction"] -pub mod stall_oh_dis; -#[doc = "CLK_RECOVER_CTRL (rw) register accessor: USB Clock Recovery Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_ctrl`] module"] -#[doc(alias = "CLK_RECOVER_CTRL")] -pub type ClkRecoverCtrl = crate::Reg; -#[doc = "USB Clock Recovery Control"] -pub mod clk_recover_ctrl; -#[doc = "CLK_RECOVER_IRC_EN (rw) register accessor: FIRC Oscillator Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_irc_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_irc_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_irc_en`] module"] -#[doc(alias = "CLK_RECOVER_IRC_EN")] -pub type ClkRecoverIrcEn = crate::Reg; -#[doc = "FIRC Oscillator Enable"] -pub mod clk_recover_irc_en; -#[doc = "CLK_RECOVER_INT_EN (rw) register accessor: Clock Recovery Combined Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_int_en`] module"] -#[doc(alias = "CLK_RECOVER_INT_EN")] -pub type ClkRecoverIntEn = crate::Reg; -#[doc = "Clock Recovery Combined Interrupt Enable"] -pub mod clk_recover_int_en; -#[doc = "CLK_RECOVER_INT_STATUS (rw) register accessor: Clock Recovery Separated Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_recover_int_status`] module"] -#[doc(alias = "CLK_RECOVER_INT_STATUS")] -pub type ClkRecoverIntStatus = crate::Reg; -#[doc = "Clock Recovery Separated Interrupt Status"] -pub mod clk_recover_int_status; diff --git a/mcxa276-pac/src/usb0/addinfo.rs b/mcxa276-pac/src/usb0/addinfo.rs deleted file mode 100644 index 7a66cacd5..000000000 --- a/mcxa276-pac/src/usb0/addinfo.rs +++ /dev/null @@ -1,56 +0,0 @@ -#[doc = "Register `ADDINFO` reader"] -pub type R = crate::R; -#[doc = "Host Mode Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Iehost { - #[doc = "0: Disabled"] - Disabled = 0, - #[doc = "1: Enabled"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Iehost) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IEHOST` reader - Host Mode Enable"] -pub type IehostR = crate::BitReader; -impl IehostR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Iehost { - match self.bits { - false => Iehost::Disabled, - true => Iehost::Enabled, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Iehost::Disabled - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Iehost::Enabled - } -} -impl R { - #[doc = "Bit 0 - Host Mode Enable"] - #[inline(always)] - pub fn iehost(&self) -> IehostR { - IehostR::new((self.bits & 1) != 0) - } -} -#[doc = "Peripheral Additional Information\n\nYou can [`read`](crate::Reg::read) this register and get [`addinfo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AddinfoSpec; -impl crate::RegisterSpec for AddinfoSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`addinfo::R`](R) reader structure"] -impl crate::Readable for AddinfoSpec {} -#[doc = "`reset()` method sets ADDINFO to value 0x01"] -impl crate::Resettable for AddinfoSpec { - const RESET_VALUE: u8 = 0x01; -} diff --git a/mcxa276-pac/src/usb0/addr.rs b/mcxa276-pac/src/usb0/addr.rs deleted file mode 100644 index 062df4342..000000000 --- a/mcxa276-pac/src/usb0/addr.rs +++ /dev/null @@ -1,49 +0,0 @@ -#[doc = "Register `ADDR` reader"] -pub type R = crate::R; -#[doc = "Register `ADDR` writer"] -pub type W = crate::W; -#[doc = "Field `ADDR` reader - USB Address"] -pub type AddrR = crate::FieldReader; -#[doc = "Field `ADDR` writer - USB Address"] -pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `LSEN` reader - Low Speed Enable"] -pub type LsenR = crate::BitReader; -#[doc = "Field `LSEN` writer - Low Speed Enable"] -pub type LsenW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:6 - USB Address"] - #[inline(always)] - pub fn addr(&self) -> AddrR { - AddrR::new(self.bits & 0x7f) - } - #[doc = "Bit 7 - Low Speed Enable"] - #[inline(always)] - pub fn lsen(&self) -> LsenR { - LsenR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:6 - USB Address"] - #[inline(always)] - pub fn addr(&mut self) -> AddrW { - AddrW::new(self, 0) - } - #[doc = "Bit 7 - Low Speed Enable"] - #[inline(always)] - pub fn lsen(&mut self) -> LsenW { - LsenW::new(self, 7) - } -} -#[doc = "Address\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct AddrSpec; -impl crate::RegisterSpec for AddrSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`addr::R`](R) reader structure"] -impl crate::Readable for AddrSpec {} -#[doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"] -impl crate::Writable for AddrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ADDR to value 0"] -impl crate::Resettable for AddrSpec {} diff --git a/mcxa276-pac/src/usb0/bdtpage1.rs b/mcxa276-pac/src/usb0/bdtpage1.rs deleted file mode 100644 index a4760a05a..000000000 --- a/mcxa276-pac/src/usb0/bdtpage1.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `BDTPAGE1` reader"] -pub type R = crate::R; -#[doc = "Register `BDTPAGE1` writer"] -pub type W = crate::W; -#[doc = "Field `BDTBA` reader - BDT Base Address"] -pub type BdtbaR = crate::FieldReader; -#[doc = "Field `BDTBA` writer - BDT Base Address"] -pub type BdtbaW<'a, REG> = crate::FieldWriter<'a, REG, 7>; -impl R { - #[doc = "Bits 1:7 - BDT Base Address"] - #[inline(always)] - pub fn bdtba(&self) -> BdtbaR { - BdtbaR::new((self.bits >> 1) & 0x7f) - } -} -impl W { - #[doc = "Bits 1:7 - BDT Base Address"] - #[inline(always)] - pub fn bdtba(&mut self) -> BdtbaW { - BdtbaW::new(self, 1) - } -} -#[doc = "BDT Page 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bdtpage1Spec; -impl crate::RegisterSpec for Bdtpage1Spec { - type Ux = u8; -} -#[doc = "`read()` method returns [`bdtpage1::R`](R) reader structure"] -impl crate::Readable for Bdtpage1Spec {} -#[doc = "`write(|w| ..)` method takes [`bdtpage1::W`](W) writer structure"] -impl crate::Writable for Bdtpage1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BDTPAGE1 to value 0"] -impl crate::Resettable for Bdtpage1Spec {} diff --git a/mcxa276-pac/src/usb0/bdtpage2.rs b/mcxa276-pac/src/usb0/bdtpage2.rs deleted file mode 100644 index 9bf00e9d3..000000000 --- a/mcxa276-pac/src/usb0/bdtpage2.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `BDTPAGE2` reader"] -pub type R = crate::R; -#[doc = "Register `BDTPAGE2` writer"] -pub type W = crate::W; -#[doc = "Field `BDTBA` reader - BDT Base Address"] -pub type BdtbaR = crate::FieldReader; -#[doc = "Field `BDTBA` writer - BDT Base Address"] -pub type BdtbaW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - BDT Base Address"] - #[inline(always)] - pub fn bdtba(&self) -> BdtbaR { - BdtbaR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:7 - BDT Base Address"] - #[inline(always)] - pub fn bdtba(&mut self) -> BdtbaW { - BdtbaW::new(self, 0) - } -} -#[doc = "BDT Page 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bdtpage2Spec; -impl crate::RegisterSpec for Bdtpage2Spec { - type Ux = u8; -} -#[doc = "`read()` method returns [`bdtpage2::R`](R) reader structure"] -impl crate::Readable for Bdtpage2Spec {} -#[doc = "`write(|w| ..)` method takes [`bdtpage2::W`](W) writer structure"] -impl crate::Writable for Bdtpage2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BDTPAGE2 to value 0"] -impl crate::Resettable for Bdtpage2Spec {} diff --git a/mcxa276-pac/src/usb0/bdtpage3.rs b/mcxa276-pac/src/usb0/bdtpage3.rs deleted file mode 100644 index 92d757aa1..000000000 --- a/mcxa276-pac/src/usb0/bdtpage3.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `BDTPAGE3` reader"] -pub type R = crate::R; -#[doc = "Register `BDTPAGE3` writer"] -pub type W = crate::W; -#[doc = "Field `BDTBA` reader - BDT Base Address"] -pub type BdtbaR = crate::FieldReader; -#[doc = "Field `BDTBA` writer - BDT Base Address"] -pub type BdtbaW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - BDT Base Address"] - #[inline(always)] - pub fn bdtba(&self) -> BdtbaR { - BdtbaR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:7 - BDT Base Address"] - #[inline(always)] - pub fn bdtba(&mut self) -> BdtbaW { - BdtbaW::new(self, 0) - } -} -#[doc = "BDT Page 3\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtpage3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtpage3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Bdtpage3Spec; -impl crate::RegisterSpec for Bdtpage3Spec { - type Ux = u8; -} -#[doc = "`read()` method returns [`bdtpage3::R`](R) reader structure"] -impl crate::Readable for Bdtpage3Spec {} -#[doc = "`write(|w| ..)` method takes [`bdtpage3::W`](W) writer structure"] -impl crate::Writable for Bdtpage3Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets BDTPAGE3 to value 0"] -impl crate::Resettable for Bdtpage3Spec {} diff --git a/mcxa276-pac/src/usb0/clk_recover_ctrl.rs b/mcxa276-pac/src/usb0/clk_recover_ctrl.rs deleted file mode 100644 index 879d63714..000000000 --- a/mcxa276-pac/src/usb0/clk_recover_ctrl.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `CLK_RECOVER_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CLK_RECOVER_CTRL` writer"] -pub type W = crate::W; -#[doc = "Selects the source for the initial FIRC trim fine value used after a reset.\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum TrimInitValSel { - #[doc = "0: Mid-scale"] - InitTrimFineMid = 0, - #[doc = "1: IFR"] - InitTrimFineIfr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: TrimInitValSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TRIM_INIT_VAL_SEL` reader - Selects the source for the initial FIRC trim fine value used after a reset."] -pub type TrimInitValSelR = crate::BitReader; -impl TrimInitValSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> TrimInitValSel { - match self.bits { - false => TrimInitValSel::InitTrimFineMid, - true => TrimInitValSel::InitTrimFineIfr, - } - } - #[doc = "Mid-scale"] - #[inline(always)] - pub fn is_init_trim_fine_mid(&self) -> bool { - *self == TrimInitValSel::InitTrimFineMid - } - #[doc = "IFR"] - #[inline(always)] - pub fn is_init_trim_fine_ifr(&self) -> bool { - *self == TrimInitValSel::InitTrimFineIfr - } -} -#[doc = "Field `TRIM_INIT_VAL_SEL` writer - Selects the source for the initial FIRC trim fine value used after a reset."] -pub type TrimInitValSelW<'a, REG> = crate::BitWriter<'a, REG, TrimInitValSel>; -impl<'a, REG> TrimInitValSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Mid-scale"] - #[inline(always)] - pub fn init_trim_fine_mid(self) -> &'a mut crate::W { - self.variant(TrimInitValSel::InitTrimFineMid) - } - #[doc = "IFR"] - #[inline(always)] - pub fn init_trim_fine_ifr(self) -> &'a mut crate::W { - self.variant(TrimInitValSel::InitTrimFineIfr) - } -} -#[doc = "Restart from IFR Trim Value\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum RestartIfrtrimEn { - #[doc = "0: Trim fine adjustment always works based on the previous updated trim fine value."] - LoadTrimFineMid = 0, - #[doc = "1: Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable."] - LoadTrimFineIfr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: RestartIfrtrimEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESTART_IFRTRIM_EN` reader - Restart from IFR Trim Value"] -pub type RestartIfrtrimEnR = crate::BitReader; -impl RestartIfrtrimEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RestartIfrtrimEn { - match self.bits { - false => RestartIfrtrimEn::LoadTrimFineMid, - true => RestartIfrtrimEn::LoadTrimFineIfr, - } - } - #[doc = "Trim fine adjustment always works based on the previous updated trim fine value."] - #[inline(always)] - pub fn is_load_trim_fine_mid(&self) -> bool { - *self == RestartIfrtrimEn::LoadTrimFineMid - } - #[doc = "Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable."] - #[inline(always)] - pub fn is_load_trim_fine_ifr(&self) -> bool { - *self == RestartIfrtrimEn::LoadTrimFineIfr - } -} -#[doc = "Field `RESTART_IFRTRIM_EN` writer - Restart from IFR Trim Value"] -pub type RestartIfrtrimEnW<'a, REG> = crate::BitWriter<'a, REG, RestartIfrtrimEn>; -impl<'a, REG> RestartIfrtrimEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Trim fine adjustment always works based on the previous updated trim fine value."] - #[inline(always)] - pub fn load_trim_fine_mid(self) -> &'a mut crate::W { - self.variant(RestartIfrtrimEn::LoadTrimFineMid) - } - #[doc = "Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable."] - #[inline(always)] - pub fn load_trim_fine_ifr(self) -> &'a mut crate::W { - self.variant(RestartIfrtrimEn::LoadTrimFineIfr) - } -} -#[doc = "Reset or Resume to Rough Phase Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ResetResumeRoughEn { - #[doc = "0: Always works in tracking phase after the first time rough phase, to track transition."] - KeepTrimFineOnReset = 0, - #[doc = "1: Go back to rough stage whenever a bus reset or bus resume occurs."] - UseIfrTrimFineOnReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ResetResumeRoughEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET_RESUME_ROUGH_EN` reader - Reset or Resume to Rough Phase Enable"] -pub type ResetResumeRoughEnR = crate::BitReader; -impl ResetResumeRoughEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ResetResumeRoughEn { - match self.bits { - false => ResetResumeRoughEn::KeepTrimFineOnReset, - true => ResetResumeRoughEn::UseIfrTrimFineOnReset, - } - } - #[doc = "Always works in tracking phase after the first time rough phase, to track transition."] - #[inline(always)] - pub fn is_keep_trim_fine_on_reset(&self) -> bool { - *self == ResetResumeRoughEn::KeepTrimFineOnReset - } - #[doc = "Go back to rough stage whenever a bus reset or bus resume occurs."] - #[inline(always)] - pub fn is_use_ifr_trim_fine_on_reset(&self) -> bool { - *self == ResetResumeRoughEn::UseIfrTrimFineOnReset - } -} -#[doc = "Field `RESET_RESUME_ROUGH_EN` writer - Reset or Resume to Rough Phase Enable"] -pub type ResetResumeRoughEnW<'a, REG> = crate::BitWriter<'a, REG, ResetResumeRoughEn>; -impl<'a, REG> ResetResumeRoughEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Always works in tracking phase after the first time rough phase, to track transition."] - #[inline(always)] - pub fn keep_trim_fine_on_reset(self) -> &'a mut crate::W { - self.variant(ResetResumeRoughEn::KeepTrimFineOnReset) - } - #[doc = "Go back to rough stage whenever a bus reset or bus resume occurs."] - #[inline(always)] - pub fn use_ifr_trim_fine_on_reset(self) -> &'a mut crate::W { - self.variant(ResetResumeRoughEn::UseIfrTrimFineOnReset) - } -} -#[doc = "Crystal-Less USB Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ClockRecoverEn { - #[doc = "0: Disable"] - DisClkRecover = 0, - #[doc = "1: Enable"] - EnClkRecover = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ClockRecoverEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLOCK_RECOVER_EN` reader - Crystal-Less USB Enable"] -pub type ClockRecoverEnR = crate::BitReader; -impl ClockRecoverEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> ClockRecoverEn { - match self.bits { - false => ClockRecoverEn::DisClkRecover, - true => ClockRecoverEn::EnClkRecover, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_clk_recover(&self) -> bool { - *self == ClockRecoverEn::DisClkRecover - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_clk_recover(&self) -> bool { - *self == ClockRecoverEn::EnClkRecover - } -} -#[doc = "Field `CLOCK_RECOVER_EN` writer - Crystal-Less USB Enable"] -pub type ClockRecoverEnW<'a, REG> = crate::BitWriter<'a, REG, ClockRecoverEn>; -impl<'a, REG> ClockRecoverEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_clk_recover(self) -> &'a mut crate::W { - self.variant(ClockRecoverEn::DisClkRecover) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_clk_recover(self) -> &'a mut crate::W { - self.variant(ClockRecoverEn::EnClkRecover) - } -} -impl R { - #[doc = "Bit 3 - Selects the source for the initial FIRC trim fine value used after a reset."] - #[inline(always)] - pub fn trim_init_val_sel(&self) -> TrimInitValSelR { - TrimInitValSelR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Restart from IFR Trim Value"] - #[inline(always)] - pub fn restart_ifrtrim_en(&self) -> RestartIfrtrimEnR { - RestartIfrtrimEnR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Reset or Resume to Rough Phase Enable"] - #[inline(always)] - pub fn reset_resume_rough_en(&self) -> ResetResumeRoughEnR { - ResetResumeRoughEnR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Crystal-Less USB Enable"] - #[inline(always)] - pub fn clock_recover_en(&self) -> ClockRecoverEnR { - ClockRecoverEnR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 3 - Selects the source for the initial FIRC trim fine value used after a reset."] - #[inline(always)] - pub fn trim_init_val_sel(&mut self) -> TrimInitValSelW { - TrimInitValSelW::new(self, 3) - } - #[doc = "Bit 5 - Restart from IFR Trim Value"] - #[inline(always)] - pub fn restart_ifrtrim_en(&mut self) -> RestartIfrtrimEnW { - RestartIfrtrimEnW::new(self, 5) - } - #[doc = "Bit 6 - Reset or Resume to Rough Phase Enable"] - #[inline(always)] - pub fn reset_resume_rough_en(&mut self) -> ResetResumeRoughEnW { - ResetResumeRoughEnW::new(self, 6) - } - #[doc = "Bit 7 - Crystal-Less USB Enable"] - #[inline(always)] - pub fn clock_recover_en(&mut self) -> ClockRecoverEnW { - ClockRecoverEnW::new(self, 7) - } -} -#[doc = "USB Clock Recovery Control\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ClkRecoverCtrlSpec; -impl crate::RegisterSpec for ClkRecoverCtrlSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`clk_recover_ctrl::R`](R) reader structure"] -impl crate::Readable for ClkRecoverCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`clk_recover_ctrl::W`](W) writer structure"] -impl crate::Writable for ClkRecoverCtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CLK_RECOVER_CTRL to value 0"] -impl crate::Resettable for ClkRecoverCtrlSpec {} diff --git a/mcxa276-pac/src/usb0/clk_recover_int_en.rs b/mcxa276-pac/src/usb0/clk_recover_int_en.rs deleted file mode 100644 index e3108a262..000000000 --- a/mcxa276-pac/src/usb0/clk_recover_int_en.rs +++ /dev/null @@ -1,86 +0,0 @@ -#[doc = "Register `CLK_RECOVER_INT_EN` reader"] -pub type R = crate::R; -#[doc = "Register `CLK_RECOVER_INT_EN` writer"] -pub type W = crate::W; -#[doc = "Overflow error interrupt enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OvfErrorEn { - #[doc = "0: The interrupt is masked"] - MaskOvfErrInt = 0, - #[doc = "1: The interrupt is enabled"] - EnOvfErrInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OvfErrorEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OVF_ERROR_EN` reader - Overflow error interrupt enable"] -pub type OvfErrorEnR = crate::BitReader; -impl OvfErrorEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvfErrorEn { - match self.bits { - false => OvfErrorEn::MaskOvfErrInt, - true => OvfErrorEn::EnOvfErrInt, - } - } - #[doc = "The interrupt is masked"] - #[inline(always)] - pub fn is_mask_ovf_err_int(&self) -> bool { - *self == OvfErrorEn::MaskOvfErrInt - } - #[doc = "The interrupt is enabled"] - #[inline(always)] - pub fn is_en_ovf_err_int(&self) -> bool { - *self == OvfErrorEn::EnOvfErrInt - } -} -#[doc = "Field `OVF_ERROR_EN` writer - Overflow error interrupt enable"] -pub type OvfErrorEnW<'a, REG> = crate::BitWriter<'a, REG, OvfErrorEn>; -impl<'a, REG> OvfErrorEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The interrupt is masked"] - #[inline(always)] - pub fn mask_ovf_err_int(self) -> &'a mut crate::W { - self.variant(OvfErrorEn::MaskOvfErrInt) - } - #[doc = "The interrupt is enabled"] - #[inline(always)] - pub fn en_ovf_err_int(self) -> &'a mut crate::W { - self.variant(OvfErrorEn::EnOvfErrInt) - } -} -impl R { - #[doc = "Bit 4 - Overflow error interrupt enable"] - #[inline(always)] - pub fn ovf_error_en(&self) -> OvfErrorEnR { - OvfErrorEnR::new(((self.bits >> 4) & 1) != 0) - } -} -impl W { - #[doc = "Bit 4 - Overflow error interrupt enable"] - #[inline(always)] - pub fn ovf_error_en(&mut self) -> OvfErrorEnW { - OvfErrorEnW::new(self, 4) - } -} -#[doc = "Clock Recovery Combined Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ClkRecoverIntEnSpec; -impl crate::RegisterSpec for ClkRecoverIntEnSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`clk_recover_int_en::R`](R) reader structure"] -impl crate::Readable for ClkRecoverIntEnSpec {} -#[doc = "`write(|w| ..)` method takes [`clk_recover_int_en::W`](W) writer structure"] -impl crate::Writable for ClkRecoverIntEnSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CLK_RECOVER_INT_EN to value 0x10"] -impl crate::Resettable for ClkRecoverIntEnSpec { - const RESET_VALUE: u8 = 0x10; -} diff --git a/mcxa276-pac/src/usb0/clk_recover_int_status.rs b/mcxa276-pac/src/usb0/clk_recover_int_status.rs deleted file mode 100644 index 17d784822..000000000 --- a/mcxa276-pac/src/usb0/clk_recover_int_status.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `CLK_RECOVER_INT_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `CLK_RECOVER_INT_STATUS` writer"] -pub type W = crate::W; -#[doc = "Overflow Error Interrupt Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OvfError { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Unmasked interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OvfError) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OVF_ERROR` reader - Overflow Error Interrupt Status Flag"] -pub type OvfErrorR = crate::BitReader; -impl OvfErrorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OvfError { - match self.bits { - false => OvfError::IntNo, - true => OvfError::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == OvfError::IntNo - } - #[doc = "Unmasked interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == OvfError::IntYes - } -} -#[doc = "Field `OVF_ERROR` writer - Overflow Error Interrupt Status Flag"] -pub type OvfErrorW<'a, REG> = crate::BitWriter1C<'a, REG, OvfError>; -impl<'a, REG> OvfErrorW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(OvfError::IntNo) - } - #[doc = "Unmasked interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(OvfError::IntYes) - } -} -impl R { - #[doc = "Bit 4 - Overflow Error Interrupt Status Flag"] - #[inline(always)] - pub fn ovf_error(&self) -> OvfErrorR { - OvfErrorR::new(((self.bits >> 4) & 1) != 0) - } -} -impl W { - #[doc = "Bit 4 - Overflow Error Interrupt Status Flag"] - #[inline(always)] - pub fn ovf_error(&mut self) -> OvfErrorW { - OvfErrorW::new(self, 4) - } -} -#[doc = "Clock Recovery Separated Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ClkRecoverIntStatusSpec; -impl crate::RegisterSpec for ClkRecoverIntStatusSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`clk_recover_int_status::R`](R) reader structure"] -impl crate::Readable for ClkRecoverIntStatusSpec {} -#[doc = "`write(|w| ..)` method takes [`clk_recover_int_status::W`](W) writer structure"] -impl crate::Writable for ClkRecoverIntStatusSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0x10; -} -#[doc = "`reset()` method sets CLK_RECOVER_INT_STATUS to value 0"] -impl crate::Resettable for ClkRecoverIntStatusSpec {} diff --git a/mcxa276-pac/src/usb0/clk_recover_irc_en.rs b/mcxa276-pac/src/usb0/clk_recover_irc_en.rs deleted file mode 100644 index 35e902b0d..000000000 --- a/mcxa276-pac/src/usb0/clk_recover_irc_en.rs +++ /dev/null @@ -1,86 +0,0 @@ -#[doc = "Register `CLK_RECOVER_IRC_EN` reader"] -pub type R = crate::R; -#[doc = "Register `CLK_RECOVER_IRC_EN` writer"] -pub type W = crate::W; -#[doc = "Fast IRC enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IrcEn { - #[doc = "0: Disable"] - DisIrc = 0, - #[doc = "1: Enable"] - EnIrc = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IrcEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `IRC_EN` reader - Fast IRC enable"] -pub type IrcEnR = crate::BitReader; -impl IrcEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IrcEn { - match self.bits { - false => IrcEn::DisIrc, - true => IrcEn::EnIrc, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_irc(&self) -> bool { - *self == IrcEn::DisIrc - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_irc(&self) -> bool { - *self == IrcEn::EnIrc - } -} -#[doc = "Field `IRC_EN` writer - Fast IRC enable"] -pub type IrcEnW<'a, REG> = crate::BitWriter<'a, REG, IrcEn>; -impl<'a, REG> IrcEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_irc(self) -> &'a mut crate::W { - self.variant(IrcEn::DisIrc) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_irc(self) -> &'a mut crate::W { - self.variant(IrcEn::EnIrc) - } -} -impl R { - #[doc = "Bit 1 - Fast IRC enable"] - #[inline(always)] - pub fn irc_en(&self) -> IrcEnR { - IrcEnR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - Fast IRC enable"] - #[inline(always)] - pub fn irc_en(&mut self) -> IrcEnW { - IrcEnW::new(self, 1) - } -} -#[doc = "FIRC Oscillator Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_recover_irc_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_recover_irc_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ClkRecoverIrcEnSpec; -impl crate::RegisterSpec for ClkRecoverIrcEnSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`clk_recover_irc_en::R`](R) reader structure"] -impl crate::Readable for ClkRecoverIrcEnSpec {} -#[doc = "`write(|w| ..)` method takes [`clk_recover_irc_en::W`](W) writer structure"] -impl crate::Writable for ClkRecoverIrcEnSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CLK_RECOVER_IRC_EN to value 0x01"] -impl crate::Resettable for ClkRecoverIrcEnSpec { - const RESET_VALUE: u8 = 0x01; -} diff --git a/mcxa276-pac/src/usb0/control.rs b/mcxa276-pac/src/usb0/control.rs deleted file mode 100644 index 7eb02207a..000000000 --- a/mcxa276-pac/src/usb0/control.rs +++ /dev/null @@ -1,176 +0,0 @@ -#[doc = "Register `CONTROL` reader"] -pub type R = crate::R; -#[doc = "Register `CONTROL` writer"] -pub type W = crate::W; -#[doc = "VBUS Monitoring Source Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum VbusSourceSel { - #[doc = "1: Resistive divider attached to a GPIO pin"] - Resistive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: VbusSourceSel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VBUS_SOURCE_SEL` reader - VBUS Monitoring Source Select"] -pub type VbusSourceSelR = crate::BitReader; -impl VbusSourceSelR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - true => Some(VbusSourceSel::Resistive), - _ => None, - } - } - #[doc = "Resistive divider attached to a GPIO pin"] - #[inline(always)] - pub fn is_resistive(&self) -> bool { - *self == VbusSourceSel::Resistive - } -} -#[doc = "Field `VBUS_SOURCE_SEL` writer - VBUS Monitoring Source Select"] -pub type VbusSourceSelW<'a, REG> = crate::BitWriter<'a, REG, VbusSourceSel>; -impl<'a, REG> VbusSourceSelW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Resistive divider attached to a GPIO pin"] - #[inline(always)] - pub fn resistive(self) -> &'a mut crate::W { - self.variant(VbusSourceSel::Resistive) - } -} -#[doc = "VBUS Session Valid status\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SessVld { - #[doc = "0: Below"] - SessVldLow = 0, - #[doc = "1: Above"] - SessVldHigh = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SessVld) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SESS_VLD` reader - VBUS Session Valid status"] -pub type SessVldR = crate::BitReader; -impl SessVldR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SessVld { - match self.bits { - false => SessVld::SessVldLow, - true => SessVld::SessVldHigh, - } - } - #[doc = "Below"] - #[inline(always)] - pub fn is_sess_vld_low(&self) -> bool { - *self == SessVld::SessVldLow - } - #[doc = "Above"] - #[inline(always)] - pub fn is_sess_vld_high(&self) -> bool { - *self == SessVld::SessVldHigh - } -} -#[doc = "DP Pullup in Non-OTG Device Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dppullupnonotg { - #[doc = "0: Disable"] - DisDeviceDpPu = 0, - #[doc = "1: Enabled"] - EnDeviceDpPu = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dppullupnonotg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DPPULLUPNONOTG` reader - DP Pullup in Non-OTG Device Mode"] -pub type DppullupnonotgR = crate::BitReader; -impl DppullupnonotgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dppullupnonotg { - match self.bits { - false => Dppullupnonotg::DisDeviceDpPu, - true => Dppullupnonotg::EnDeviceDpPu, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_device_dp_pu(&self) -> bool { - *self == Dppullupnonotg::DisDeviceDpPu - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_en_device_dp_pu(&self) -> bool { - *self == Dppullupnonotg::EnDeviceDpPu - } -} -#[doc = "Field `DPPULLUPNONOTG` writer - DP Pullup in Non-OTG Device Mode"] -pub type DppullupnonotgW<'a, REG> = crate::BitWriter<'a, REG, Dppullupnonotg>; -impl<'a, REG> DppullupnonotgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_device_dp_pu(self) -> &'a mut crate::W { - self.variant(Dppullupnonotg::DisDeviceDpPu) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn en_device_dp_pu(self) -> &'a mut crate::W { - self.variant(Dppullupnonotg::EnDeviceDpPu) - } -} -impl R { - #[doc = "Bit 0 - VBUS Monitoring Source Select"] - #[inline(always)] - pub fn vbus_source_sel(&self) -> VbusSourceSelR { - VbusSourceSelR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - VBUS Session Valid status"] - #[inline(always)] - pub fn sess_vld(&self) -> SessVldR { - SessVldR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 4 - DP Pullup in Non-OTG Device Mode"] - #[inline(always)] - pub fn dppullupnonotg(&self) -> DppullupnonotgR { - DppullupnonotgR::new(((self.bits >> 4) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - VBUS Monitoring Source Select"] - #[inline(always)] - pub fn vbus_source_sel(&mut self) -> VbusSourceSelW { - VbusSourceSelW::new(self, 0) - } - #[doc = "Bit 4 - DP Pullup in Non-OTG Device Mode"] - #[inline(always)] - pub fn dppullupnonotg(&mut self) -> DppullupnonotgW { - DppullupnonotgW::new(self, 4) - } -} -#[doc = "USB OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ControlSpec; -impl crate::RegisterSpec for ControlSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`control::R`](R) reader structure"] -impl crate::Readable for ControlSpec {} -#[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"] -impl crate::Writable for ControlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CONTROL to value 0"] -impl crate::Resettable for ControlSpec {} diff --git a/mcxa276-pac/src/usb0/ctl.rs b/mcxa276-pac/src/usb0/ctl.rs deleted file mode 100644 index 6656c7751..000000000 --- a/mcxa276-pac/src/usb0/ctl.rs +++ /dev/null @@ -1,280 +0,0 @@ -#[doc = "Register `CTL` reader"] -pub type R = crate::R; -#[doc = "Register `CTL` writer"] -pub type W = crate::W; -#[doc = "USB Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usbensofen { - #[doc = "0: Disable"] - DisUsbSof = 0, - #[doc = "1: Enable"] - EnUsbSof = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usbensofen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USBENSOFEN` reader - USB Enable"] -pub type UsbensofenR = crate::BitReader; -impl UsbensofenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Usbensofen { - match self.bits { - false => Usbensofen::DisUsbSof, - true => Usbensofen::EnUsbSof, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_usb_sof(&self) -> bool { - *self == Usbensofen::DisUsbSof - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_usb_sof(&self) -> bool { - *self == Usbensofen::EnUsbSof - } -} -#[doc = "Field `USBENSOFEN` writer - USB Enable"] -pub type UsbensofenW<'a, REG> = crate::BitWriter<'a, REG, Usbensofen>; -impl<'a, REG> UsbensofenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_usb_sof(self) -> &'a mut crate::W { - self.variant(Usbensofen::DisUsbSof) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_usb_sof(self) -> &'a mut crate::W { - self.variant(Usbensofen::EnUsbSof) - } -} -#[doc = "Field `ODDRST` reader - Odd Reset"] -pub type OddrstR = crate::BitReader; -#[doc = "Field `ODDRST` writer - Odd Reset"] -pub type OddrstW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESUME` reader - Resume"] -pub type ResumeR = crate::BitReader; -#[doc = "Field `RESUME` writer - Resume"] -pub type ResumeW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Host Mode Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hostmodeen { - #[doc = "0: USBFS operates in Device mode."] - EnDeviceMode = 0, - #[doc = "1: USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."] - EnHostMode = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hostmodeen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HOSTMODEEN` reader - Host Mode Enable"] -pub type HostmodeenR = crate::BitReader; -impl HostmodeenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hostmodeen { - match self.bits { - false => Hostmodeen::EnDeviceMode, - true => Hostmodeen::EnHostMode, - } - } - #[doc = "USBFS operates in Device mode."] - #[inline(always)] - pub fn is_en_device_mode(&self) -> bool { - *self == Hostmodeen::EnDeviceMode - } - #[doc = "USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."] - #[inline(always)] - pub fn is_en_host_mode(&self) -> bool { - *self == Hostmodeen::EnHostMode - } -} -#[doc = "Field `HOSTMODEEN` writer - Host Mode Enable"] -pub type HostmodeenW<'a, REG> = crate::BitWriter<'a, REG, Hostmodeen>; -impl<'a, REG> HostmodeenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "USBFS operates in Device mode."] - #[inline(always)] - pub fn en_device_mode(self) -> &'a mut crate::W { - self.variant(Hostmodeen::EnDeviceMode) - } - #[doc = "USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor."] - #[inline(always)] - pub fn en_host_mode(self) -> &'a mut crate::W { - self.variant(Hostmodeen::EnHostMode) - } -} -#[doc = "Reset Signaling Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Reset { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Reset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESET` reader - Reset Signaling Enable"] -pub type ResetR = crate::BitReader; -impl ResetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reset { - match self.bits { - false => Reset::Disable, - true => Reset::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Reset::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Reset::Enable - } -} -#[doc = "Field `RESET` writer - Reset Signaling Enable"] -pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>; -impl<'a, REG> ResetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Reset::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Reset::Enable) - } -} -#[doc = "Field `TXSUSPENDTOKENBUSY` reader - TXD Suspend And Token Busy"] -pub type TxsuspendtokenbusyR = crate::BitReader; -#[doc = "Field `TXSUSPENDTOKENBUSY` writer - TXD Suspend And Token Busy"] -pub type TxsuspendtokenbusyW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SE0` reader - Live USB Single-Ended Zero signal"] -pub type Se0R = crate::BitReader; -#[doc = "Field `SE0` writer - Live USB Single-Ended Zero signal"] -pub type Se0W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `JSTATE` reader - Live USB Differential Receiver JSTATE Signal"] -pub type JstateR = crate::BitReader; -#[doc = "Field `JSTATE` writer - Live USB Differential Receiver JSTATE Signal"] -pub type JstateW<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - USB Enable"] - #[inline(always)] - pub fn usbensofen(&self) -> UsbensofenR { - UsbensofenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Odd Reset"] - #[inline(always)] - pub fn oddrst(&self) -> OddrstR { - OddrstR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Resume"] - #[inline(always)] - pub fn resume(&self) -> ResumeR { - ResumeR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Host Mode Enable"] - #[inline(always)] - pub fn hostmodeen(&self) -> HostmodeenR { - HostmodeenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Reset Signaling Enable"] - #[inline(always)] - pub fn reset(&self) -> ResetR { - ResetR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - TXD Suspend And Token Busy"] - #[inline(always)] - pub fn txsuspendtokenbusy(&self) -> TxsuspendtokenbusyR { - TxsuspendtokenbusyR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Live USB Single-Ended Zero signal"] - #[inline(always)] - pub fn se0(&self) -> Se0R { - Se0R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Live USB Differential Receiver JSTATE Signal"] - #[inline(always)] - pub fn jstate(&self) -> JstateR { - JstateR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - USB Enable"] - #[inline(always)] - pub fn usbensofen(&mut self) -> UsbensofenW { - UsbensofenW::new(self, 0) - } - #[doc = "Bit 1 - Odd Reset"] - #[inline(always)] - pub fn oddrst(&mut self) -> OddrstW { - OddrstW::new(self, 1) - } - #[doc = "Bit 2 - Resume"] - #[inline(always)] - pub fn resume(&mut self) -> ResumeW { - ResumeW::new(self, 2) - } - #[doc = "Bit 3 - Host Mode Enable"] - #[inline(always)] - pub fn hostmodeen(&mut self) -> HostmodeenW { - HostmodeenW::new(self, 3) - } - #[doc = "Bit 4 - Reset Signaling Enable"] - #[inline(always)] - pub fn reset(&mut self) -> ResetW { - ResetW::new(self, 4) - } - #[doc = "Bit 5 - TXD Suspend And Token Busy"] - #[inline(always)] - pub fn txsuspendtokenbusy(&mut self) -> TxsuspendtokenbusyW { - TxsuspendtokenbusyW::new(self, 5) - } - #[doc = "Bit 6 - Live USB Single-Ended Zero signal"] - #[inline(always)] - pub fn se0(&mut self) -> Se0W { - Se0W::new(self, 6) - } - #[doc = "Bit 7 - Live USB Differential Receiver JSTATE Signal"] - #[inline(always)] - pub fn jstate(&mut self) -> JstateW { - JstateW::new(self, 7) - } -} -#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtlSpec; -impl crate::RegisterSpec for CtlSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`ctl::R`](R) reader structure"] -impl crate::Readable for CtlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] -impl crate::Writable for CtlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTL to value 0"] -impl crate::Resettable for CtlSpec {} diff --git a/mcxa276-pac/src/usb0/endpoint.rs b/mcxa276-pac/src/usb0/endpoint.rs deleted file mode 100644 index a48556c8e..000000000 --- a/mcxa276-pac/src/usb0/endpoint.rs +++ /dev/null @@ -1,18 +0,0 @@ -#[repr(C)] -#[doc = "Array of registers: ENDPT"] -#[doc(alias = "ENDPOINT")] -pub struct Endpoint { - endpt: Endpt, -} -impl Endpoint { - #[doc = "0x00 - Endpoint Control"] - #[inline(always)] - pub const fn endpt(&self) -> &Endpt { - &self.endpt - } -} -#[doc = "ENDPT (rw) register accessor: Endpoint Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endpt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endpt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endpt`] module"] -#[doc(alias = "ENDPT")] -pub type Endpt = crate::Reg; -#[doc = "Endpoint Control"] -pub mod endpt; diff --git a/mcxa276-pac/src/usb0/endpoint/endpt.rs b/mcxa276-pac/src/usb0/endpoint/endpt.rs deleted file mode 100644 index 050bd9620..000000000 --- a/mcxa276-pac/src/usb0/endpoint/endpt.rs +++ /dev/null @@ -1,266 +0,0 @@ -#[doc = "Register `ENDPT` reader"] -pub type R = crate::R; -#[doc = "Register `ENDPT` writer"] -pub type W = crate::W; -#[doc = "Field `EPHSHK` reader - Endpoint Handshaking Enable"] -pub type EphshkR = crate::BitReader; -#[doc = "Field `EPHSHK` writer - Endpoint Handshaking Enable"] -pub type EphshkW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EPSTALL` reader - Endpoint Stalled"] -pub type EpstallR = crate::BitReader; -#[doc = "Field `EPSTALL` writer - Endpoint Stalled"] -pub type EpstallW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EPTXEN` reader - Endpoint for TX transfers enable"] -pub type EptxenR = crate::BitReader; -#[doc = "Field `EPTXEN` writer - Endpoint for TX transfers enable"] -pub type EptxenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EPRXEN` reader - Endpoint for RX transfers enable"] -pub type EprxenR = crate::BitReader; -#[doc = "Field `EPRXEN` writer - Endpoint for RX transfers enable"] -pub type EprxenW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Control Transfer Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Epctldis { - #[doc = "0: Enable"] - Enable = 0, - #[doc = "1: Disable"] - Disable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Epctldis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EPCTLDIS` reader - Control Transfer Disable"] -pub type EpctldisR = crate::BitReader; -impl EpctldisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Epctldis { - match self.bits { - false => Epctldis::Enable, - true => Epctldis::Disable, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Epctldis::Enable - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Epctldis::Disable - } -} -#[doc = "Field `EPCTLDIS` writer - Control Transfer Disable"] -pub type EpctldisW<'a, REG> = crate::BitWriter<'a, REG, Epctldis>; -impl<'a, REG> EpctldisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Epctldis::Enable) - } - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Epctldis::Disable) - } -} -#[doc = "Retry Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Retrydis { - #[doc = "0: Retried NAK'ed transactions in hardware."] - Retried = 0, - #[doc = "1: Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt becomes 1."] - DoNotRetried = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Retrydis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RETRYDIS` reader - Retry Disable"] -pub type RetrydisR = crate::BitReader; -impl RetrydisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Retrydis { - match self.bits { - false => Retrydis::Retried, - true => Retrydis::DoNotRetried, - } - } - #[doc = "Retried NAK'ed transactions in hardware."] - #[inline(always)] - pub fn is_retried(&self) -> bool { - *self == Retrydis::Retried - } - #[doc = "Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt becomes 1."] - #[inline(always)] - pub fn is_do_not_retried(&self) -> bool { - *self == Retrydis::DoNotRetried - } -} -#[doc = "Field `RETRYDIS` writer - Retry Disable"] -pub type RetrydisW<'a, REG> = crate::BitWriter<'a, REG, Retrydis>; -impl<'a, REG> RetrydisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Retried NAK'ed transactions in hardware."] - #[inline(always)] - pub fn retried(self) -> &'a mut crate::W { - self.variant(Retrydis::Retried) - } - #[doc = "Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt becomes 1."] - #[inline(always)] - pub fn do_not_retried(self) -> &'a mut crate::W { - self.variant(Retrydis::DoNotRetried) - } -} -#[doc = "Host Without A Hub\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Hostwohub { - #[doc = "0: Connected using a hub (USBFS generates PRE_PID as required)"] - LsThruHub = 0, - #[doc = "1: Connected directly to host without a hub, or was used to attach"] - LsDirectConnect = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Hostwohub) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HOSTWOHUB` reader - Host Without A Hub"] -pub type HostwohubR = crate::BitReader; -impl HostwohubR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Hostwohub { - match self.bits { - false => Hostwohub::LsThruHub, - true => Hostwohub::LsDirectConnect, - } - } - #[doc = "Connected using a hub (USBFS generates PRE_PID as required)"] - #[inline(always)] - pub fn is_ls_thru_hub(&self) -> bool { - *self == Hostwohub::LsThruHub - } - #[doc = "Connected directly to host without a hub, or was used to attach"] - #[inline(always)] - pub fn is_ls_direct_connect(&self) -> bool { - *self == Hostwohub::LsDirectConnect - } -} -#[doc = "Field `HOSTWOHUB` writer - Host Without A Hub"] -pub type HostwohubW<'a, REG> = crate::BitWriter<'a, REG, Hostwohub>; -impl<'a, REG> HostwohubW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Connected using a hub (USBFS generates PRE_PID as required)"] - #[inline(always)] - pub fn ls_thru_hub(self) -> &'a mut crate::W { - self.variant(Hostwohub::LsThruHub) - } - #[doc = "Connected directly to host without a hub, or was used to attach"] - #[inline(always)] - pub fn ls_direct_connect(self) -> &'a mut crate::W { - self.variant(Hostwohub::LsDirectConnect) - } -} -impl R { - #[doc = "Bit 0 - Endpoint Handshaking Enable"] - #[inline(always)] - pub fn ephshk(&self) -> EphshkR { - EphshkR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Endpoint Stalled"] - #[inline(always)] - pub fn epstall(&self) -> EpstallR { - EpstallR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Endpoint for TX transfers enable"] - #[inline(always)] - pub fn eptxen(&self) -> EptxenR { - EptxenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Endpoint for RX transfers enable"] - #[inline(always)] - pub fn eprxen(&self) -> EprxenR { - EprxenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Control Transfer Disable"] - #[inline(always)] - pub fn epctldis(&self) -> EpctldisR { - EpctldisR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 6 - Retry Disable"] - #[inline(always)] - pub fn retrydis(&self) -> RetrydisR { - RetrydisR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Host Without A Hub"] - #[inline(always)] - pub fn hostwohub(&self) -> HostwohubR { - HostwohubR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Endpoint Handshaking Enable"] - #[inline(always)] - pub fn ephshk(&mut self) -> EphshkW { - EphshkW::new(self, 0) - } - #[doc = "Bit 1 - Endpoint Stalled"] - #[inline(always)] - pub fn epstall(&mut self) -> EpstallW { - EpstallW::new(self, 1) - } - #[doc = "Bit 2 - Endpoint for TX transfers enable"] - #[inline(always)] - pub fn eptxen(&mut self) -> EptxenW { - EptxenW::new(self, 2) - } - #[doc = "Bit 3 - Endpoint for RX transfers enable"] - #[inline(always)] - pub fn eprxen(&mut self) -> EprxenW { - EprxenW::new(self, 3) - } - #[doc = "Bit 4 - Control Transfer Disable"] - #[inline(always)] - pub fn epctldis(&mut self) -> EpctldisW { - EpctldisW::new(self, 4) - } - #[doc = "Bit 6 - Retry Disable"] - #[inline(always)] - pub fn retrydis(&mut self) -> RetrydisW { - RetrydisW::new(self, 6) - } - #[doc = "Bit 7 - Host Without A Hub"] - #[inline(always)] - pub fn hostwohub(&mut self) -> HostwohubW { - HostwohubW::new(self, 7) - } -} -#[doc = "Endpoint Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endpt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endpt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EndptSpec; -impl crate::RegisterSpec for EndptSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`endpt::R`](R) reader structure"] -impl crate::Readable for EndptSpec {} -#[doc = "`write(|w| ..)` method takes [`endpt::W`](W) writer structure"] -impl crate::Writable for EndptSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ENDPT to value 0"] -impl crate::Resettable for EndptSpec {} diff --git a/mcxa276-pac/src/usb0/erren.rs b/mcxa276-pac/src/usb0/erren.rs deleted file mode 100644 index 83b4162e2..000000000 --- a/mcxa276-pac/src/usb0/erren.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `ERREN` reader"] -pub type R = crate::R; -#[doc = "Register `ERREN` writer"] -pub type W = crate::W; -#[doc = "PIDERR Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Piderren { - #[doc = "0: Disable"] - DisPiderrInt = 0, - #[doc = "1: Enable"] - EnPiderrInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Piderren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIDERREN` reader - PIDERR Interrupt Enable"] -pub type PiderrenR = crate::BitReader; -impl PiderrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Piderren { - match self.bits { - false => Piderren::DisPiderrInt, - true => Piderren::EnPiderrInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_piderr_int(&self) -> bool { - *self == Piderren::DisPiderrInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_piderr_int(&self) -> bool { - *self == Piderren::EnPiderrInt - } -} -#[doc = "Field `PIDERREN` writer - PIDERR Interrupt Enable"] -pub type PiderrenW<'a, REG> = crate::BitWriter<'a, REG, Piderren>; -impl<'a, REG> PiderrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_piderr_int(self) -> &'a mut crate::W { - self.variant(Piderren::DisPiderrInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_piderr_int(self) -> &'a mut crate::W { - self.variant(Piderren::EnPiderrInt) - } -} -#[doc = "CRC5/EOF Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crc5eofen { - #[doc = "0: Disable"] - DisCrc5Int = 0, - #[doc = "1: Enable"] - EnCrc5Int = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crc5eofen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRC5EOFEN` reader - CRC5/EOF Interrupt Enable"] -pub type Crc5eofenR = crate::BitReader; -impl Crc5eofenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crc5eofen { - match self.bits { - false => Crc5eofen::DisCrc5Int, - true => Crc5eofen::EnCrc5Int, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_crc5_int(&self) -> bool { - *self == Crc5eofen::DisCrc5Int - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_crc5_int(&self) -> bool { - *self == Crc5eofen::EnCrc5Int - } -} -#[doc = "Field `CRC5EOFEN` writer - CRC5/EOF Interrupt Enable"] -pub type Crc5eofenW<'a, REG> = crate::BitWriter<'a, REG, Crc5eofen>; -impl<'a, REG> Crc5eofenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_crc5_int(self) -> &'a mut crate::W { - self.variant(Crc5eofen::DisCrc5Int) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_crc5_int(self) -> &'a mut crate::W { - self.variant(Crc5eofen::EnCrc5Int) - } -} -#[doc = "CRC16 Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crc16en { - #[doc = "0: Disable"] - DisCrc16Int = 0, - #[doc = "1: Enable"] - EnCrc16Int = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crc16en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRC16EN` reader - CRC16 Interrupt Enable"] -pub type Crc16enR = crate::BitReader; -impl Crc16enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crc16en { - match self.bits { - false => Crc16en::DisCrc16Int, - true => Crc16en::EnCrc16Int, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_crc16_int(&self) -> bool { - *self == Crc16en::DisCrc16Int - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_crc16_int(&self) -> bool { - *self == Crc16en::EnCrc16Int - } -} -#[doc = "Field `CRC16EN` writer - CRC16 Interrupt Enable"] -pub type Crc16enW<'a, REG> = crate::BitWriter<'a, REG, Crc16en>; -impl<'a, REG> Crc16enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_crc16_int(self) -> &'a mut crate::W { - self.variant(Crc16en::DisCrc16Int) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_crc16_int(self) -> &'a mut crate::W { - self.variant(Crc16en::EnCrc16Int) - } -} -#[doc = "DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dfn8en { - #[doc = "0: Disable"] - DisDfn8Int = 0, - #[doc = "1: Enable"] - EnDfn8Int = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dfn8en) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DFN8EN` reader - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] -pub type Dfn8enR = crate::BitReader; -impl Dfn8enR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dfn8en { - match self.bits { - false => Dfn8en::DisDfn8Int, - true => Dfn8en::EnDfn8Int, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_dfn8_int(&self) -> bool { - *self == Dfn8en::DisDfn8Int - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_dfn8_int(&self) -> bool { - *self == Dfn8en::EnDfn8Int - } -} -#[doc = "Field `DFN8EN` writer - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] -pub type Dfn8enW<'a, REG> = crate::BitWriter<'a, REG, Dfn8en>; -impl<'a, REG> Dfn8enW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_dfn8_int(self) -> &'a mut crate::W { - self.variant(Dfn8en::DisDfn8Int) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_dfn8_int(self) -> &'a mut crate::W { - self.variant(Dfn8en::EnDfn8Int) - } -} -#[doc = "BTOERR (Bus Timeout Error) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Btoerren { - #[doc = "0: Disable"] - DisBtoerrInt = 0, - #[doc = "1: Enable"] - EnBtoerrInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Btoerren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BTOERREN` reader - BTOERR (Bus Timeout Error) Interrupt Enable"] -pub type BtoerrenR = crate::BitReader; -impl BtoerrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Btoerren { - match self.bits { - false => Btoerren::DisBtoerrInt, - true => Btoerren::EnBtoerrInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_btoerr_int(&self) -> bool { - *self == Btoerren::DisBtoerrInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_btoerr_int(&self) -> bool { - *self == Btoerren::EnBtoerrInt - } -} -#[doc = "Field `BTOERREN` writer - BTOERR (Bus Timeout Error) Interrupt Enable"] -pub type BtoerrenW<'a, REG> = crate::BitWriter<'a, REG, Btoerren>; -impl<'a, REG> BtoerrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_btoerr_int(self) -> &'a mut crate::W { - self.variant(Btoerren::DisBtoerrInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_btoerr_int(self) -> &'a mut crate::W { - self.variant(Btoerren::EnBtoerrInt) - } -} -#[doc = "DMAERR Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmaerren { - #[doc = "0: Disable"] - DisDmaerrInt = 0, - #[doc = "1: Enable"] - EnDmaerrInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmaerren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMAERREN` reader - DMAERR Interrupt Enable"] -pub type DmaerrenR = crate::BitReader; -impl DmaerrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmaerren { - match self.bits { - false => Dmaerren::DisDmaerrInt, - true => Dmaerren::EnDmaerrInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_dmaerr_int(&self) -> bool { - *self == Dmaerren::DisDmaerrInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_dmaerr_int(&self) -> bool { - *self == Dmaerren::EnDmaerrInt - } -} -#[doc = "Field `DMAERREN` writer - DMAERR Interrupt Enable"] -pub type DmaerrenW<'a, REG> = crate::BitWriter<'a, REG, Dmaerren>; -impl<'a, REG> DmaerrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_dmaerr_int(self) -> &'a mut crate::W { - self.variant(Dmaerren::DisDmaerrInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_dmaerr_int(self) -> &'a mut crate::W { - self.variant(Dmaerren::EnDmaerrInt) - } -} -#[doc = "OWNERR Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ownerren { - #[doc = "0: Disable"] - DisOwnerrInt = 0, - #[doc = "1: Enable"] - EnOwnerrInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ownerren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OWNERREN` reader - OWNERR Interrupt Enable"] -pub type OwnerrenR = crate::BitReader; -impl OwnerrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ownerren { - match self.bits { - false => Ownerren::DisOwnerrInt, - true => Ownerren::EnOwnerrInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ownerr_int(&self) -> bool { - *self == Ownerren::DisOwnerrInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ownerr_int(&self) -> bool { - *self == Ownerren::EnOwnerrInt - } -} -#[doc = "Field `OWNERREN` writer - OWNERR Interrupt Enable"] -pub type OwnerrenW<'a, REG> = crate::BitWriter<'a, REG, Ownerren>; -impl<'a, REG> OwnerrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ownerr_int(self) -> &'a mut crate::W { - self.variant(Ownerren::DisOwnerrInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_ownerr_int(self) -> &'a mut crate::W { - self.variant(Ownerren::EnOwnerrInt) - } -} -#[doc = "BTSERR (Bit Stuff Error) Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Btserren { - #[doc = "0: Disable"] - DisBtserrenInt = 0, - #[doc = "1: Enable"] - EnBtserrenInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Btserren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BTSERREN` reader - BTSERR (Bit Stuff Error) Interrupt Enable"] -pub type BtserrenR = crate::BitReader; -impl BtserrenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Btserren { - match self.bits { - false => Btserren::DisBtserrenInt, - true => Btserren::EnBtserrenInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_btserren_int(&self) -> bool { - *self == Btserren::DisBtserrenInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_btserren_int(&self) -> bool { - *self == Btserren::EnBtserrenInt - } -} -#[doc = "Field `BTSERREN` writer - BTSERR (Bit Stuff Error) Interrupt Enable"] -pub type BtserrenW<'a, REG> = crate::BitWriter<'a, REG, Btserren>; -impl<'a, REG> BtserrenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_btserren_int(self) -> &'a mut crate::W { - self.variant(Btserren::DisBtserrenInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_btserren_int(self) -> &'a mut crate::W { - self.variant(Btserren::EnBtserrenInt) - } -} -impl R { - #[doc = "Bit 0 - PIDERR Interrupt Enable"] - #[inline(always)] - pub fn piderren(&self) -> PiderrenR { - PiderrenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - CRC5/EOF Interrupt Enable"] - #[inline(always)] - pub fn crc5eofen(&self) -> Crc5eofenR { - Crc5eofenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - CRC16 Interrupt Enable"] - #[inline(always)] - pub fn crc16en(&self) -> Crc16enR { - Crc16enR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] - #[inline(always)] - pub fn dfn8en(&self) -> Dfn8enR { - Dfn8enR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - BTOERR (Bus Timeout Error) Interrupt Enable"] - #[inline(always)] - pub fn btoerren(&self) -> BtoerrenR { - BtoerrenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - DMAERR Interrupt Enable"] - #[inline(always)] - pub fn dmaerren(&self) -> DmaerrenR { - DmaerrenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - OWNERR Interrupt Enable"] - #[inline(always)] - pub fn ownerren(&self) -> OwnerrenR { - OwnerrenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - BTSERR (Bit Stuff Error) Interrupt Enable"] - #[inline(always)] - pub fn btserren(&self) -> BtserrenR { - BtserrenR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - PIDERR Interrupt Enable"] - #[inline(always)] - pub fn piderren(&mut self) -> PiderrenW { - PiderrenW::new(self, 0) - } - #[doc = "Bit 1 - CRC5/EOF Interrupt Enable"] - #[inline(always)] - pub fn crc5eofen(&mut self) -> Crc5eofenW { - Crc5eofenW::new(self, 1) - } - #[doc = "Bit 2 - CRC16 Interrupt Enable"] - #[inline(always)] - pub fn crc16en(&mut self) -> Crc16enW { - Crc16enW::new(self, 2) - } - #[doc = "Bit 3 - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable"] - #[inline(always)] - pub fn dfn8en(&mut self) -> Dfn8enW { - Dfn8enW::new(self, 3) - } - #[doc = "Bit 4 - BTOERR (Bus Timeout Error) Interrupt Enable"] - #[inline(always)] - pub fn btoerren(&mut self) -> BtoerrenW { - BtoerrenW::new(self, 4) - } - #[doc = "Bit 5 - DMAERR Interrupt Enable"] - #[inline(always)] - pub fn dmaerren(&mut self) -> DmaerrenW { - DmaerrenW::new(self, 5) - } - #[doc = "Bit 6 - OWNERR Interrupt Enable"] - #[inline(always)] - pub fn ownerren(&mut self) -> OwnerrenW { - OwnerrenW::new(self, 6) - } - #[doc = "Bit 7 - BTSERR (Bit Stuff Error) Interrupt Enable"] - #[inline(always)] - pub fn btserren(&mut self) -> BtserrenW { - BtserrenW::new(self, 7) - } -} -#[doc = "Error Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`erren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`erren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ErrenSpec; -impl crate::RegisterSpec for ErrenSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`erren::R`](R) reader structure"] -impl crate::Readable for ErrenSpec {} -#[doc = "`write(|w| ..)` method takes [`erren::W`](W) writer structure"] -impl crate::Writable for ErrenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ERREN to value 0"] -impl crate::Resettable for ErrenSpec {} diff --git a/mcxa276-pac/src/usb0/errstat.rs b/mcxa276-pac/src/usb0/errstat.rs deleted file mode 100644 index 6df6b2c37..000000000 --- a/mcxa276-pac/src/usb0/errstat.rs +++ /dev/null @@ -1,526 +0,0 @@ -#[doc = "Register `ERRSTAT` reader"] -pub type R = crate::R; -#[doc = "Register `ERRSTAT` writer"] -pub type W = crate::W; -#[doc = "PID Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Piderr { - #[doc = "0: Did not fail"] - IntNo = 0, - #[doc = "1: Failed"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Piderr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PIDERR` reader - PID Error Flag"] -pub type PiderrR = crate::BitReader; -impl PiderrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Piderr { - match self.bits { - false => Piderr::IntNo, - true => Piderr::IntYes, - } - } - #[doc = "Did not fail"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Piderr::IntNo - } - #[doc = "Failed"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Piderr::IntYes - } -} -#[doc = "Field `PIDERR` writer - PID Error Flag"] -pub type PiderrW<'a, REG> = crate::BitWriter1C<'a, REG, Piderr>; -impl<'a, REG> PiderrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Did not fail"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Piderr::IntNo) - } - #[doc = "Failed"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Piderr::IntYes) - } -} -#[doc = "CRC5 Error or End of Frame Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crc5eof { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crc5eof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRC5EOF` reader - CRC5 Error or End of Frame Error Flag"] -pub type Crc5eofR = crate::BitReader; -impl Crc5eofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crc5eof { - match self.bits { - false => Crc5eof::IntNo, - true => Crc5eof::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Crc5eof::IntNo - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Crc5eof::IntYes - } -} -#[doc = "Field `CRC5EOF` writer - CRC5 Error or End of Frame Error Flag"] -pub type Crc5eofW<'a, REG> = crate::BitWriter1C<'a, REG, Crc5eof>; -impl<'a, REG> Crc5eofW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Crc5eof::IntNo) - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Crc5eof::IntYes) - } -} -#[doc = "CRC16 Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Crc16 { - #[doc = "0: Not rejected"] - IntNo = 0, - #[doc = "1: Rejected"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Crc16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CRC16` reader - CRC16 Error Flag"] -pub type Crc16R = crate::BitReader; -impl Crc16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Crc16 { - match self.bits { - false => Crc16::IntNo, - true => Crc16::IntYes, - } - } - #[doc = "Not rejected"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Crc16::IntNo - } - #[doc = "Rejected"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Crc16::IntYes - } -} -#[doc = "Field `CRC16` writer - CRC16 Error Flag"] -pub type Crc16W<'a, REG> = crate::BitWriter1C<'a, REG, Crc16>; -impl<'a, REG> Crc16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not rejected"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Crc16::IntNo) - } - #[doc = "Rejected"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Crc16::IntYes) - } -} -#[doc = "Data Field Not 8 Bits Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dfn8 { - #[doc = "0: Integer number of bytes"] - IntNo = 0, - #[doc = "1: Not an integer number of bytes"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dfn8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DFN8` reader - Data Field Not 8 Bits Flag"] -pub type Dfn8R = crate::BitReader; -impl Dfn8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dfn8 { - match self.bits { - false => Dfn8::IntNo, - true => Dfn8::IntYes, - } - } - #[doc = "Integer number of bytes"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Dfn8::IntNo - } - #[doc = "Not an integer number of bytes"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Dfn8::IntYes - } -} -#[doc = "Field `DFN8` writer - Data Field Not 8 Bits Flag"] -pub type Dfn8W<'a, REG> = crate::BitWriter1C<'a, REG, Dfn8>; -impl<'a, REG> Dfn8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Integer number of bytes"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Dfn8::IntNo) - } - #[doc = "Not an integer number of bytes"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Dfn8::IntYes) - } -} -#[doc = "Bus Turnaround Timeout Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Btoerr { - #[doc = "0: Not timed out"] - IntNo = 0, - #[doc = "1: Timed out"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Btoerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BTOERR` reader - Bus Turnaround Timeout Error Flag"] -pub type BtoerrR = crate::BitReader; -impl BtoerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Btoerr { - match self.bits { - false => Btoerr::IntNo, - true => Btoerr::IntYes, - } - } - #[doc = "Not timed out"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Btoerr::IntNo - } - #[doc = "Timed out"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Btoerr::IntYes - } -} -#[doc = "Field `BTOERR` writer - Bus Turnaround Timeout Error Flag"] -pub type BtoerrW<'a, REG> = crate::BitWriter1C<'a, REG, Btoerr>; -impl<'a, REG> BtoerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not timed out"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Btoerr::IntNo) - } - #[doc = "Timed out"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Btoerr::IntYes) - } -} -#[doc = "DMA Access Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmaerr { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmaerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMAERR` reader - DMA Access Error Flag"] -pub type DmaerrR = crate::BitReader; -impl DmaerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmaerr { - match self.bits { - false => Dmaerr::IntNo, - true => Dmaerr::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Dmaerr::IntNo - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Dmaerr::IntYes - } -} -#[doc = "Field `DMAERR` writer - DMA Access Error Flag"] -pub type DmaerrW<'a, REG> = crate::BitWriter1C<'a, REG, Dmaerr>; -impl<'a, REG> DmaerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Dmaerr::IntNo) - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Dmaerr::IntYes) - } -} -#[doc = "BD Unavailable Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ownerr { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ownerr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OWNERR` reader - BD Unavailable Error Flag"] -pub type OwnerrR = crate::BitReader; -impl OwnerrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ownerr { - match self.bits { - false => Ownerr::IntNo, - true => Ownerr::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Ownerr::IntNo - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Ownerr::IntYes - } -} -#[doc = "Field `OWNERR` writer - BD Unavailable Error Flag"] -pub type OwnerrW<'a, REG> = crate::BitWriter1C<'a, REG, Ownerr>; -impl<'a, REG> OwnerrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Ownerr::IntNo) - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Ownerr::IntYes) - } -} -#[doc = "Bit Stuff Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Btserr { - #[doc = "0: Packet not rejected due to the error"] - IntNo = 0, - #[doc = "1: Packet rejected due to the error"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Btserr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `BTSERR` reader - Bit Stuff Error Flag"] -pub type BtserrR = crate::BitReader; -impl BtserrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Btserr { - match self.bits { - false => Btserr::IntNo, - true => Btserr::IntYes, - } - } - #[doc = "Packet not rejected due to the error"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Btserr::IntNo - } - #[doc = "Packet rejected due to the error"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Btserr::IntYes - } -} -#[doc = "Field `BTSERR` writer - Bit Stuff Error Flag"] -pub type BtserrW<'a, REG> = crate::BitWriter1C<'a, REG, Btserr>; -impl<'a, REG> BtserrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Packet not rejected due to the error"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Btserr::IntNo) - } - #[doc = "Packet rejected due to the error"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Btserr::IntYes) - } -} -impl R { - #[doc = "Bit 0 - PID Error Flag"] - #[inline(always)] - pub fn piderr(&self) -> PiderrR { - PiderrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - CRC5 Error or End of Frame Error Flag"] - #[inline(always)] - pub fn crc5eof(&self) -> Crc5eofR { - Crc5eofR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - CRC16 Error Flag"] - #[inline(always)] - pub fn crc16(&self) -> Crc16R { - Crc16R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Data Field Not 8 Bits Flag"] - #[inline(always)] - pub fn dfn8(&self) -> Dfn8R { - Dfn8R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Bus Turnaround Timeout Error Flag"] - #[inline(always)] - pub fn btoerr(&self) -> BtoerrR { - BtoerrR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - DMA Access Error Flag"] - #[inline(always)] - pub fn dmaerr(&self) -> DmaerrR { - DmaerrR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - BD Unavailable Error Flag"] - #[inline(always)] - pub fn ownerr(&self) -> OwnerrR { - OwnerrR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Bit Stuff Error Flag"] - #[inline(always)] - pub fn btserr(&self) -> BtserrR { - BtserrR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - PID Error Flag"] - #[inline(always)] - pub fn piderr(&mut self) -> PiderrW { - PiderrW::new(self, 0) - } - #[doc = "Bit 1 - CRC5 Error or End of Frame Error Flag"] - #[inline(always)] - pub fn crc5eof(&mut self) -> Crc5eofW { - Crc5eofW::new(self, 1) - } - #[doc = "Bit 2 - CRC16 Error Flag"] - #[inline(always)] - pub fn crc16(&mut self) -> Crc16W { - Crc16W::new(self, 2) - } - #[doc = "Bit 3 - Data Field Not 8 Bits Flag"] - #[inline(always)] - pub fn dfn8(&mut self) -> Dfn8W { - Dfn8W::new(self, 3) - } - #[doc = "Bit 4 - Bus Turnaround Timeout Error Flag"] - #[inline(always)] - pub fn btoerr(&mut self) -> BtoerrW { - BtoerrW::new(self, 4) - } - #[doc = "Bit 5 - DMA Access Error Flag"] - #[inline(always)] - pub fn dmaerr(&mut self) -> DmaerrW { - DmaerrW::new(self, 5) - } - #[doc = "Bit 6 - BD Unavailable Error Flag"] - #[inline(always)] - pub fn ownerr(&mut self) -> OwnerrW { - OwnerrW::new(self, 6) - } - #[doc = "Bit 7 - Bit Stuff Error Flag"] - #[inline(always)] - pub fn btserr(&mut self) -> BtserrW { - BtserrW::new(self, 7) - } -} -#[doc = "Error Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`errstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ErrstatSpec; -impl crate::RegisterSpec for ErrstatSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`errstat::R`](R) reader structure"] -impl crate::Readable for ErrstatSpec {} -#[doc = "`write(|w| ..)` method takes [`errstat::W`](W) writer structure"] -impl crate::Writable for ErrstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0xff; -} -#[doc = "`reset()` method sets ERRSTAT to value 0"] -impl crate::Resettable for ErrstatSpec {} diff --git a/mcxa276-pac/src/usb0/frmnumh.rs b/mcxa276-pac/src/usb0/frmnumh.rs deleted file mode 100644 index 50c5f0d01..000000000 --- a/mcxa276-pac/src/usb0/frmnumh.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `FRMNUMH` reader"] -pub type R = crate::R; -#[doc = "Field `FRM` reader - Frame Number, Bits 8-10"] -pub type FrmR = crate::FieldReader; -impl R { - #[doc = "Bits 0:2 - Frame Number, Bits 8-10"] - #[inline(always)] - pub fn frm(&self) -> FrmR { - FrmR::new(self.bits & 7) - } -} -#[doc = "Frame Number Register High\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnumh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrmnumhSpec; -impl crate::RegisterSpec for FrmnumhSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`frmnumh::R`](R) reader structure"] -impl crate::Readable for FrmnumhSpec {} -#[doc = "`reset()` method sets FRMNUMH to value 0"] -impl crate::Resettable for FrmnumhSpec {} diff --git a/mcxa276-pac/src/usb0/frmnuml.rs b/mcxa276-pac/src/usb0/frmnuml.rs deleted file mode 100644 index 63d8d1723..000000000 --- a/mcxa276-pac/src/usb0/frmnuml.rs +++ /dev/null @@ -1,20 +0,0 @@ -#[doc = "Register `FRMNUML` reader"] -pub type R = crate::R; -#[doc = "Field `FRM` reader - Frame Number, Bits 0-7"] -pub type FrmR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Frame Number, Bits 0-7"] - #[inline(always)] - pub fn frm(&self) -> FrmR { - FrmR::new(self.bits) - } -} -#[doc = "Frame Number Register Low\n\nYou can [`read`](crate::Reg::read) this register and get [`frmnuml::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrmnumlSpec; -impl crate::RegisterSpec for FrmnumlSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`frmnuml::R`](R) reader structure"] -impl crate::Readable for FrmnumlSpec {} -#[doc = "`reset()` method sets FRMNUML to value 0"] -impl crate::Resettable for FrmnumlSpec {} diff --git a/mcxa276-pac/src/usb0/idcomp.rs b/mcxa276-pac/src/usb0/idcomp.rs deleted file mode 100644 index a4fe6bf6f..000000000 --- a/mcxa276-pac/src/usb0/idcomp.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `IDCOMP` reader"] -pub type R = crate::R; -#[doc = "Field `NID` reader - Negative Peripheral ID"] -pub type NidR = crate::FieldReader; -impl R { - #[doc = "Bits 0:5 - Negative Peripheral ID"] - #[inline(always)] - pub fn nid(&self) -> NidR { - NidR::new(self.bits & 0x3f) - } -} -#[doc = "Peripheral ID Complement\n\nYou can [`read`](crate::Reg::read) this register and get [`idcomp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IdcompSpec; -impl crate::RegisterSpec for IdcompSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`idcomp::R`](R) reader structure"] -impl crate::Readable for IdcompSpec {} -#[doc = "`reset()` method sets IDCOMP to value 0xfb"] -impl crate::Resettable for IdcompSpec { - const RESET_VALUE: u8 = 0xfb; -} diff --git a/mcxa276-pac/src/usb0/inten.rs b/mcxa276-pac/src/usb0/inten.rs deleted file mode 100644 index 157c909e8..000000000 --- a/mcxa276-pac/src/usb0/inten.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `INTEN` reader"] -pub type R = crate::R; -#[doc = "Register `INTEN` writer"] -pub type W = crate::W; -#[doc = "USBRST Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usbrsten { - #[doc = "0: Disable"] - DisUsbrstInt = 0, - #[doc = "1: Enable"] - EnUsbrstInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usbrsten) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USBRSTEN` reader - USBRST Interrupt Enable"] -pub type UsbrstenR = crate::BitReader; -impl UsbrstenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Usbrsten { - match self.bits { - false => Usbrsten::DisUsbrstInt, - true => Usbrsten::EnUsbrstInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_usbrst_int(&self) -> bool { - *self == Usbrsten::DisUsbrstInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_usbrst_int(&self) -> bool { - *self == Usbrsten::EnUsbrstInt - } -} -#[doc = "Field `USBRSTEN` writer - USBRST Interrupt Enable"] -pub type UsbrstenW<'a, REG> = crate::BitWriter<'a, REG, Usbrsten>; -impl<'a, REG> UsbrstenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_usbrst_int(self) -> &'a mut crate::W { - self.variant(Usbrsten::DisUsbrstInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_usbrst_int(self) -> &'a mut crate::W { - self.variant(Usbrsten::EnUsbrstInt) - } -} -#[doc = "ERROR Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Erroren { - #[doc = "0: Disable"] - DisErrorInt = 0, - #[doc = "1: Enable"] - EnErrorInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Erroren) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERROREN` reader - ERROR Interrupt Enable"] -pub type ErrorenR = crate::BitReader; -impl ErrorenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Erroren { - match self.bits { - false => Erroren::DisErrorInt, - true => Erroren::EnErrorInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_error_int(&self) -> bool { - *self == Erroren::DisErrorInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_error_int(&self) -> bool { - *self == Erroren::EnErrorInt - } -} -#[doc = "Field `ERROREN` writer - ERROR Interrupt Enable"] -pub type ErrorenW<'a, REG> = crate::BitWriter<'a, REG, Erroren>; -impl<'a, REG> ErrorenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_error_int(self) -> &'a mut crate::W { - self.variant(Erroren::DisErrorInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_error_int(self) -> &'a mut crate::W { - self.variant(Erroren::EnErrorInt) - } -} -#[doc = "SOFTOK Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Softoken { - #[doc = "0: Disable"] - DisSoftokInt = 0, - #[doc = "1: Enable"] - EnSoftokInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Softoken) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOFTOKEN` reader - SOFTOK Interrupt Enable"] -pub type SoftokenR = crate::BitReader; -impl SoftokenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Softoken { - match self.bits { - false => Softoken::DisSoftokInt, - true => Softoken::EnSoftokInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_softok_int(&self) -> bool { - *self == Softoken::DisSoftokInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_softok_int(&self) -> bool { - *self == Softoken::EnSoftokInt - } -} -#[doc = "Field `SOFTOKEN` writer - SOFTOK Interrupt Enable"] -pub type SoftokenW<'a, REG> = crate::BitWriter<'a, REG, Softoken>; -impl<'a, REG> SoftokenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_softok_int(self) -> &'a mut crate::W { - self.variant(Softoken::DisSoftokInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_softok_int(self) -> &'a mut crate::W { - self.variant(Softoken::EnSoftokInt) - } -} -#[doc = "TOKDNE Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tokdneen { - #[doc = "0: Disable"] - DisTokdneInt = 0, - #[doc = "1: Enable"] - EnTokdneInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tokdneen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TOKDNEEN` reader - TOKDNE Interrupt Enable"] -pub type TokdneenR = crate::BitReader; -impl TokdneenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tokdneen { - match self.bits { - false => Tokdneen::DisTokdneInt, - true => Tokdneen::EnTokdneInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_tokdne_int(&self) -> bool { - *self == Tokdneen::DisTokdneInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_tokdne_int(&self) -> bool { - *self == Tokdneen::EnTokdneInt - } -} -#[doc = "Field `TOKDNEEN` writer - TOKDNE Interrupt Enable"] -pub type TokdneenW<'a, REG> = crate::BitWriter<'a, REG, Tokdneen>; -impl<'a, REG> TokdneenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_tokdne_int(self) -> &'a mut crate::W { - self.variant(Tokdneen::DisTokdneInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_tokdne_int(self) -> &'a mut crate::W { - self.variant(Tokdneen::EnTokdneInt) - } -} -#[doc = "SLEEP Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sleepen { - #[doc = "0: Disable"] - DisSleepInt = 0, - #[doc = "1: Enable"] - EnSleepInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sleepen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLEEPEN` reader - SLEEP Interrupt Enable"] -pub type SleepenR = crate::BitReader; -impl SleepenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sleepen { - match self.bits { - false => Sleepen::DisSleepInt, - true => Sleepen::EnSleepInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_sleep_int(&self) -> bool { - *self == Sleepen::DisSleepInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_sleep_int(&self) -> bool { - *self == Sleepen::EnSleepInt - } -} -#[doc = "Field `SLEEPEN` writer - SLEEP Interrupt Enable"] -pub type SleepenW<'a, REG> = crate::BitWriter<'a, REG, Sleepen>; -impl<'a, REG> SleepenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_sleep_int(self) -> &'a mut crate::W { - self.variant(Sleepen::DisSleepInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_sleep_int(self) -> &'a mut crate::W { - self.variant(Sleepen::EnSleepInt) - } -} -#[doc = "RESUME Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Resumeen { - #[doc = "0: Disable"] - DisResumeInt = 0, - #[doc = "1: Enable"] - EnResumeInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Resumeen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESUMEEN` reader - RESUME Interrupt Enable"] -pub type ResumeenR = crate::BitReader; -impl ResumeenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Resumeen { - match self.bits { - false => Resumeen::DisResumeInt, - true => Resumeen::EnResumeInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_resume_int(&self) -> bool { - *self == Resumeen::DisResumeInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_resume_int(&self) -> bool { - *self == Resumeen::EnResumeInt - } -} -#[doc = "Field `RESUMEEN` writer - RESUME Interrupt Enable"] -pub type ResumeenW<'a, REG> = crate::BitWriter<'a, REG, Resumeen>; -impl<'a, REG> ResumeenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_resume_int(self) -> &'a mut crate::W { - self.variant(Resumeen::DisResumeInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_resume_int(self) -> &'a mut crate::W { - self.variant(Resumeen::EnResumeInt) - } -} -#[doc = "ATTACH Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Attachen { - #[doc = "0: Disable"] - DisAttachInt = 0, - #[doc = "1: Enable"] - EnAttachInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Attachen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ATTACHEN` reader - ATTACH Interrupt Enable"] -pub type AttachenR = crate::BitReader; -impl AttachenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Attachen { - match self.bits { - false => Attachen::DisAttachInt, - true => Attachen::EnAttachInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_attach_int(&self) -> bool { - *self == Attachen::DisAttachInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_attach_int(&self) -> bool { - *self == Attachen::EnAttachInt - } -} -#[doc = "Field `ATTACHEN` writer - ATTACH Interrupt Enable"] -pub type AttachenW<'a, REG> = crate::BitWriter<'a, REG, Attachen>; -impl<'a, REG> AttachenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_attach_int(self) -> &'a mut crate::W { - self.variant(Attachen::DisAttachInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_attach_int(self) -> &'a mut crate::W { - self.variant(Attachen::EnAttachInt) - } -} -#[doc = "STALL Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stallen { - #[doc = "0: Disable"] - DisStallInt = 0, - #[doc = "1: Enable"] - EnStallInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stallen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALLEN` reader - STALL Interrupt Enable"] -pub type StallenR = crate::BitReader; -impl StallenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stallen { - match self.bits { - false => Stallen::DisStallInt, - true => Stallen::EnStallInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_stall_int(&self) -> bool { - *self == Stallen::DisStallInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_stall_int(&self) -> bool { - *self == Stallen::EnStallInt - } -} -#[doc = "Field `STALLEN` writer - STALL Interrupt Enable"] -pub type StallenW<'a, REG> = crate::BitWriter<'a, REG, Stallen>; -impl<'a, REG> StallenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_stall_int(self) -> &'a mut crate::W { - self.variant(Stallen::DisStallInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_stall_int(self) -> &'a mut crate::W { - self.variant(Stallen::EnStallInt) - } -} -impl R { - #[doc = "Bit 0 - USBRST Interrupt Enable"] - #[inline(always)] - pub fn usbrsten(&self) -> UsbrstenR { - UsbrstenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - ERROR Interrupt Enable"] - #[inline(always)] - pub fn erroren(&self) -> ErrorenR { - ErrorenR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - SOFTOK Interrupt Enable"] - #[inline(always)] - pub fn softoken(&self) -> SoftokenR { - SoftokenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - TOKDNE Interrupt Enable"] - #[inline(always)] - pub fn tokdneen(&self) -> TokdneenR { - TokdneenR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - SLEEP Interrupt Enable"] - #[inline(always)] - pub fn sleepen(&self) -> SleepenR { - SleepenR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - RESUME Interrupt Enable"] - #[inline(always)] - pub fn resumeen(&self) -> ResumeenR { - ResumeenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - ATTACH Interrupt Enable"] - #[inline(always)] - pub fn attachen(&self) -> AttachenR { - AttachenR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - STALL Interrupt Enable"] - #[inline(always)] - pub fn stallen(&self) -> StallenR { - StallenR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - USBRST Interrupt Enable"] - #[inline(always)] - pub fn usbrsten(&mut self) -> UsbrstenW { - UsbrstenW::new(self, 0) - } - #[doc = "Bit 1 - ERROR Interrupt Enable"] - #[inline(always)] - pub fn erroren(&mut self) -> ErrorenW { - ErrorenW::new(self, 1) - } - #[doc = "Bit 2 - SOFTOK Interrupt Enable"] - #[inline(always)] - pub fn softoken(&mut self) -> SoftokenW { - SoftokenW::new(self, 2) - } - #[doc = "Bit 3 - TOKDNE Interrupt Enable"] - #[inline(always)] - pub fn tokdneen(&mut self) -> TokdneenW { - TokdneenW::new(self, 3) - } - #[doc = "Bit 4 - SLEEP Interrupt Enable"] - #[inline(always)] - pub fn sleepen(&mut self) -> SleepenW { - SleepenW::new(self, 4) - } - #[doc = "Bit 5 - RESUME Interrupt Enable"] - #[inline(always)] - pub fn resumeen(&mut self) -> ResumeenW { - ResumeenW::new(self, 5) - } - #[doc = "Bit 6 - ATTACH Interrupt Enable"] - #[inline(always)] - pub fn attachen(&mut self) -> AttachenW { - AttachenW::new(self, 6) - } - #[doc = "Bit 7 - STALL Interrupt Enable"] - #[inline(always)] - pub fn stallen(&mut self) -> StallenW { - StallenW::new(self, 7) - } -} -#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IntenSpec; -impl crate::RegisterSpec for IntenSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`inten::R`](R) reader structure"] -impl crate::Readable for IntenSpec {} -#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"] -impl crate::Writable for IntenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets INTEN to value 0"] -impl crate::Resettable for IntenSpec {} diff --git a/mcxa276-pac/src/usb0/istat.rs b/mcxa276-pac/src/usb0/istat.rs deleted file mode 100644 index cae467a9e..000000000 --- a/mcxa276-pac/src/usb0/istat.rs +++ /dev/null @@ -1,526 +0,0 @@ -#[doc = "Register `ISTAT` reader"] -pub type R = crate::R; -#[doc = "Register `ISTAT` writer"] -pub type W = crate::W; -#[doc = "USB Reset Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usbrst { - #[doc = "0: Not detected"] - IntNo = 0, - #[doc = "1: Detected"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usbrst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USBRST` reader - USB Reset Flag"] -pub type UsbrstR = crate::BitReader; -impl UsbrstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Usbrst { - match self.bits { - false => Usbrst::IntNo, - true => Usbrst::IntYes, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Usbrst::IntNo - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Usbrst::IntYes - } -} -#[doc = "Field `USBRST` writer - USB Reset Flag"] -pub type UsbrstW<'a, REG> = crate::BitWriter1C<'a, REG, Usbrst>; -impl<'a, REG> UsbrstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Usbrst::IntNo) - } - #[doc = "Detected"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Usbrst::IntYes) - } -} -#[doc = "Error Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Error { - #[doc = "0: Error did not occur"] - IntNo = 0, - #[doc = "1: Error occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Error) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ERROR` reader - Error Flag"] -pub type ErrorR = crate::BitReader; -impl ErrorR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Error { - match self.bits { - false => Error::IntNo, - true => Error::IntYes, - } - } - #[doc = "Error did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Error::IntNo - } - #[doc = "Error occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Error::IntYes - } -} -#[doc = "Field `ERROR` writer - Error Flag"] -pub type ErrorW<'a, REG> = crate::BitWriter1C<'a, REG, Error>; -impl<'a, REG> ErrorW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Error did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Error::IntNo) - } - #[doc = "Error occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Error::IntYes) - } -} -#[doc = "Start Of Frame (SOF) Token Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Softok { - #[doc = "0: Did not receive"] - IntNo = 0, - #[doc = "1: Received"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Softok) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOFTOK` reader - Start Of Frame (SOF) Token Flag"] -pub type SoftokR = crate::BitReader; -impl SoftokR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Softok { - match self.bits { - false => Softok::IntNo, - true => Softok::IntYes, - } - } - #[doc = "Did not receive"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Softok::IntNo - } - #[doc = "Received"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Softok::IntYes - } -} -#[doc = "Field `SOFTOK` writer - Start Of Frame (SOF) Token Flag"] -pub type SoftokW<'a, REG> = crate::BitWriter1C<'a, REG, Softok>; -impl<'a, REG> SoftokW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Did not receive"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Softok::IntNo) - } - #[doc = "Received"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Softok::IntYes) - } -} -#[doc = "Current Token Processing Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tokdne { - #[doc = "0: Not processed"] - IntNo = 0, - #[doc = "1: Processed"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tokdne) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TOKDNE` reader - Current Token Processing Flag"] -pub type TokdneR = crate::BitReader; -impl TokdneR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tokdne { - match self.bits { - false => Tokdne::IntNo, - true => Tokdne::IntYes, - } - } - #[doc = "Not processed"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Tokdne::IntNo - } - #[doc = "Processed"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Tokdne::IntYes - } -} -#[doc = "Field `TOKDNE` writer - Current Token Processing Flag"] -pub type TokdneW<'a, REG> = crate::BitWriter1C<'a, REG, Tokdne>; -impl<'a, REG> TokdneW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not processed"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Tokdne::IntNo) - } - #[doc = "Processed"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Tokdne::IntYes) - } -} -#[doc = "Sleep Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sleep { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sleep) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SLEEP` reader - Sleep Flag"] -pub type SleepR = crate::BitReader; -impl SleepR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sleep { - match self.bits { - false => Sleep::IntNo, - true => Sleep::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Sleep::IntNo - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Sleep::IntYes - } -} -#[doc = "Field `SLEEP` writer - Sleep Flag"] -pub type SleepW<'a, REG> = crate::BitWriter1C<'a, REG, Sleep>; -impl<'a, REG> SleepW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Sleep::IntNo) - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Sleep::IntYes) - } -} -#[doc = "Resume Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Resume { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Resume) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RESUME` reader - Resume Flag"] -pub type ResumeR = crate::BitReader; -impl ResumeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Resume { - match self.bits { - false => Resume::IntNo, - true => Resume::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Resume::IntNo - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Resume::IntYes - } -} -#[doc = "Field `RESUME` writer - Resume Flag"] -pub type ResumeW<'a, REG> = crate::BitWriter1C<'a, REG, Resume>; -impl<'a, REG> ResumeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Resume::IntNo) - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Resume::IntYes) - } -} -#[doc = "Attach Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Attach { - #[doc = "0: Not detected"] - IntNo = 0, - #[doc = "1: Detected"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Attach) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ATTACH` reader - Attach Interrupt Flag"] -pub type AttachR = crate::BitReader; -impl AttachR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Attach { - match self.bits { - false => Attach::IntNo, - true => Attach::IntYes, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Attach::IntNo - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Attach::IntYes - } -} -#[doc = "Field `ATTACH` writer - Attach Interrupt Flag"] -pub type AttachW<'a, REG> = crate::BitWriter1C<'a, REG, Attach>; -impl<'a, REG> AttachW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not detected"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Attach::IntNo) - } - #[doc = "Detected"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Attach::IntYes) - } -} -#[doc = "Stall Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Stall { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Stall) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL` reader - Stall Interrupt Flag"] -pub type StallR = crate::BitReader; -impl StallR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Stall { - match self.bits { - false => Stall::IntNo, - true => Stall::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Stall::IntNo - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Stall::IntYes - } -} -#[doc = "Field `STALL` writer - Stall Interrupt Flag"] -pub type StallW<'a, REG> = crate::BitWriter1C<'a, REG, Stall>; -impl<'a, REG> StallW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Stall::IntNo) - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Stall::IntYes) - } -} -impl R { - #[doc = "Bit 0 - USB Reset Flag"] - #[inline(always)] - pub fn usbrst(&self) -> UsbrstR { - UsbrstR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Error Flag"] - #[inline(always)] - pub fn error(&self) -> ErrorR { - ErrorR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Start Of Frame (SOF) Token Flag"] - #[inline(always)] - pub fn softok(&self) -> SoftokR { - SoftokR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Current Token Processing Flag"] - #[inline(always)] - pub fn tokdne(&self) -> TokdneR { - TokdneR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Sleep Flag"] - #[inline(always)] - pub fn sleep(&self) -> SleepR { - SleepR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Resume Flag"] - #[inline(always)] - pub fn resume(&self) -> ResumeR { - ResumeR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Attach Interrupt Flag"] - #[inline(always)] - pub fn attach(&self) -> AttachR { - AttachR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Stall Interrupt Flag"] - #[inline(always)] - pub fn stall(&self) -> StallR { - StallR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - USB Reset Flag"] - #[inline(always)] - pub fn usbrst(&mut self) -> UsbrstW { - UsbrstW::new(self, 0) - } - #[doc = "Bit 1 - Error Flag"] - #[inline(always)] - pub fn error(&mut self) -> ErrorW { - ErrorW::new(self, 1) - } - #[doc = "Bit 2 - Start Of Frame (SOF) Token Flag"] - #[inline(always)] - pub fn softok(&mut self) -> SoftokW { - SoftokW::new(self, 2) - } - #[doc = "Bit 3 - Current Token Processing Flag"] - #[inline(always)] - pub fn tokdne(&mut self) -> TokdneW { - TokdneW::new(self, 3) - } - #[doc = "Bit 4 - Sleep Flag"] - #[inline(always)] - pub fn sleep(&mut self) -> SleepW { - SleepW::new(self, 4) - } - #[doc = "Bit 5 - Resume Flag"] - #[inline(always)] - pub fn resume(&mut self) -> ResumeW { - ResumeW::new(self, 5) - } - #[doc = "Bit 6 - Attach Interrupt Flag"] - #[inline(always)] - pub fn attach(&mut self) -> AttachW { - AttachW::new(self, 6) - } - #[doc = "Bit 7 - Stall Interrupt Flag"] - #[inline(always)] - pub fn stall(&mut self) -> StallW { - StallW::new(self, 7) - } -} -#[doc = "Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`istat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`istat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IstatSpec; -impl crate::RegisterSpec for IstatSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`istat::R`](R) reader structure"] -impl crate::Readable for IstatSpec {} -#[doc = "`write(|w| ..)` method takes [`istat::W`](W) writer structure"] -impl crate::Writable for IstatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0xff; -} -#[doc = "`reset()` method sets ISTAT to value 0"] -impl crate::Resettable for IstatSpec {} diff --git a/mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs b/mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs deleted file mode 100644 index 121686c20..000000000 --- a/mcxa276-pac/src/usb0/keep_alive_ctrl_rsvd.rs +++ /dev/null @@ -1,25 +0,0 @@ -#[doc = "Register `KEEP_ALIVE_CTRL_RSVD` reader"] -pub type R = crate::R; -#[doc = "Register `KEEP_ALIVE_CTRL_RSVD` writer"] -pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl W {} -#[doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_ctrl_rsvd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_ctrl_rsvd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct KeepAliveCtrlRsvdSpec; -impl crate::RegisterSpec for KeepAliveCtrlRsvdSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`keep_alive_ctrl_rsvd::R`](R) reader structure"] -impl crate::Readable for KeepAliveCtrlRsvdSpec {} -#[doc = "`write(|w| ..)` method takes [`keep_alive_ctrl_rsvd::W`](W) writer structure"] -impl crate::Writable for KeepAliveCtrlRsvdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets KEEP_ALIVE_CTRL_RSVD to value 0x08"] -impl crate::Resettable for KeepAliveCtrlRsvdSpec { - const RESET_VALUE: u8 = 0x08; -} diff --git a/mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs b/mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs deleted file mode 100644 index f7b3af7ae..000000000 --- a/mcxa276-pac/src/usb0/keep_alive_wkctrl_rsvd.rs +++ /dev/null @@ -1,25 +0,0 @@ -#[doc = "Register `KEEP_ALIVE_WKCTRL_RSVD` reader"] -pub type R = crate::R; -#[doc = "Register `KEEP_ALIVE_WKCTRL_RSVD` writer"] -pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl W {} -#[doc = "Reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`keep_alive_wkctrl_rsvd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keep_alive_wkctrl_rsvd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct KeepAliveWkctrlRsvdSpec; -impl crate::RegisterSpec for KeepAliveWkctrlRsvdSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`keep_alive_wkctrl_rsvd::R`](R) reader structure"] -impl crate::Readable for KeepAliveWkctrlRsvdSpec {} -#[doc = "`write(|w| ..)` method takes [`keep_alive_wkctrl_rsvd::W`](W) writer structure"] -impl crate::Writable for KeepAliveWkctrlRsvdSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets KEEP_ALIVE_WKCTRL_RSVD to value 0x01"] -impl crate::Resettable for KeepAliveWkctrlRsvdSpec { - const RESET_VALUE: u8 = 0x01; -} diff --git a/mcxa276-pac/src/usb0/miscctrl.rs b/mcxa276-pac/src/usb0/miscctrl.rs deleted file mode 100644 index f0d066a00..000000000 --- a/mcxa276-pac/src/usb0/miscctrl.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `MISCCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `MISCCTRL` writer"] -pub type W = crate::W; -#[doc = "Dynamic SOF Threshold Compare mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sofdynthld { - #[doc = "0: When the byte-times SOF threshold is reached"] - UseDynSofThreshold = 0, - #[doc = "1: When 8 byte-times SOF threshold is reached or overstepped"] - UseFixedSofThreshold = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sofdynthld) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOFDYNTHLD` reader - Dynamic SOF Threshold Compare mode"] -pub type SofdynthldR = crate::BitReader; -impl SofdynthldR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sofdynthld { - match self.bits { - false => Sofdynthld::UseDynSofThreshold, - true => Sofdynthld::UseFixedSofThreshold, - } - } - #[doc = "When the byte-times SOF threshold is reached"] - #[inline(always)] - pub fn is_use_dyn_sof_threshold(&self) -> bool { - *self == Sofdynthld::UseDynSofThreshold - } - #[doc = "When 8 byte-times SOF threshold is reached or overstepped"] - #[inline(always)] - pub fn is_use_fixed_sof_threshold(&self) -> bool { - *self == Sofdynthld::UseFixedSofThreshold - } -} -#[doc = "Field `SOFDYNTHLD` writer - Dynamic SOF Threshold Compare mode"] -pub type SofdynthldW<'a, REG> = crate::BitWriter<'a, REG, Sofdynthld>; -impl<'a, REG> SofdynthldW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "When the byte-times SOF threshold is reached"] - #[inline(always)] - pub fn use_dyn_sof_threshold(self) -> &'a mut crate::W { - self.variant(Sofdynthld::UseDynSofThreshold) - } - #[doc = "When 8 byte-times SOF threshold is reached or overstepped"] - #[inline(always)] - pub fn use_fixed_sof_threshold(self) -> &'a mut crate::W { - self.variant(Sofdynthld::UseFixedSofThreshold) - } -} -#[doc = "SOF_TOK Interrupt Generation Mode Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Sofbusset { - #[doc = "0: According to the SOF threshold value"] - SofTokIntFromThreshold = 0, - #[doc = "1: When the SOF counter reaches 0"] - SofTokIntCounter0 = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Sofbusset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SOFBUSSET` reader - SOF_TOK Interrupt Generation Mode Select"] -pub type SofbussetR = crate::BitReader; -impl SofbussetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Sofbusset { - match self.bits { - false => Sofbusset::SofTokIntFromThreshold, - true => Sofbusset::SofTokIntCounter0, - } - } - #[doc = "According to the SOF threshold value"] - #[inline(always)] - pub fn is_sof_tok_int_from_threshold(&self) -> bool { - *self == Sofbusset::SofTokIntFromThreshold - } - #[doc = "When the SOF counter reaches 0"] - #[inline(always)] - pub fn is_sof_tok_int_counter_0(&self) -> bool { - *self == Sofbusset::SofTokIntCounter0 - } -} -#[doc = "Field `SOFBUSSET` writer - SOF_TOK Interrupt Generation Mode Select"] -pub type SofbussetW<'a, REG> = crate::BitWriter<'a, REG, Sofbusset>; -impl<'a, REG> SofbussetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "According to the SOF threshold value"] - #[inline(always)] - pub fn sof_tok_int_from_threshold(self) -> &'a mut crate::W { - self.variant(Sofbusset::SofTokIntFromThreshold) - } - #[doc = "When the SOF counter reaches 0"] - #[inline(always)] - pub fn sof_tok_int_counter_0(self) -> &'a mut crate::W { - self.variant(Sofbusset::SofTokIntCounter0) - } -} -#[doc = "OWN Error Detect for ISO IN and ISO OUT Disable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ownerrisodis { - #[doc = "0: Enable"] - DisOwnErrorDetectIso = 0, - #[doc = "1: Disable"] - EnOwnErrorDetectIso = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ownerrisodis) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OWNERRISODIS` reader - OWN Error Detect for ISO IN and ISO OUT Disable"] -pub type OwnerrisodisR = crate::BitReader; -impl OwnerrisodisR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ownerrisodis { - match self.bits { - false => Ownerrisodis::DisOwnErrorDetectIso, - true => Ownerrisodis::EnOwnErrorDetectIso, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_dis_own_error_detect_iso(&self) -> bool { - *self == Ownerrisodis::DisOwnErrorDetectIso - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_en_own_error_detect_iso(&self) -> bool { - *self == Ownerrisodis::EnOwnErrorDetectIso - } -} -#[doc = "Field `OWNERRISODIS` writer - OWN Error Detect for ISO IN and ISO OUT Disable"] -pub type OwnerrisodisW<'a, REG> = crate::BitWriter<'a, REG, Ownerrisodis>; -impl<'a, REG> OwnerrisodisW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn dis_own_error_detect_iso(self) -> &'a mut crate::W { - self.variant(Ownerrisodis::DisOwnErrorDetectIso) - } - #[doc = "Disable"] - #[inline(always)] - pub fn en_own_error_detect_iso(self) -> &'a mut crate::W { - self.variant(Ownerrisodis::EnOwnErrorDetectIso) - } -} -#[doc = "VREGIN Rising Edge Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum VredgEn { - #[doc = "0: Disable"] - DisVreginReInt = 0, - #[doc = "1: Enable"] - EnVreginReInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: VredgEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VREDG_EN` reader - VREGIN Rising Edge Interrupt Enable"] -pub type VredgEnR = crate::BitReader; -impl VredgEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> VredgEn { - match self.bits { - false => VredgEn::DisVreginReInt, - true => VredgEn::EnVreginReInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_vregin_re_int(&self) -> bool { - *self == VredgEn::DisVreginReInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_vregin_re_int(&self) -> bool { - *self == VredgEn::EnVreginReInt - } -} -#[doc = "Field `VREDG_EN` writer - VREGIN Rising Edge Interrupt Enable"] -pub type VredgEnW<'a, REG> = crate::BitWriter<'a, REG, VredgEn>; -impl<'a, REG> VredgEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_vregin_re_int(self) -> &'a mut crate::W { - self.variant(VredgEn::DisVreginReInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_vregin_re_int(self) -> &'a mut crate::W { - self.variant(VredgEn::EnVreginReInt) - } -} -#[doc = "VREGIN Falling Edge Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum VfedgEn { - #[doc = "0: Disable"] - DisVreginFeInt = 0, - #[doc = "1: Enable"] - EnVreginFeInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: VfedgEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VFEDG_EN` reader - VREGIN Falling Edge Interrupt Enable"] -pub type VfedgEnR = crate::BitReader; -impl VfedgEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> VfedgEn { - match self.bits { - false => VfedgEn::DisVreginFeInt, - true => VfedgEn::EnVreginFeInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_vregin_fe_int(&self) -> bool { - *self == VfedgEn::DisVreginFeInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_vregin_fe_int(&self) -> bool { - *self == VfedgEn::EnVreginFeInt - } -} -#[doc = "Field `VFEDG_EN` writer - VREGIN Falling Edge Interrupt Enable"] -pub type VfedgEnW<'a, REG> = crate::BitWriter<'a, REG, VfedgEn>; -impl<'a, REG> VfedgEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_vregin_fe_int(self) -> &'a mut crate::W { - self.variant(VfedgEn::DisVreginFeInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_vregin_fe_int(self) -> &'a mut crate::W { - self.variant(VfedgEn::EnVreginFeInt) - } -} -#[doc = "USB Peripheral Mode Stall Adjust Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StlAdjEn { - #[doc = "0: If ENDPTn\\[END_STALL\\] = 1, both IN and OUT directions for the associated endpoint stalls."] - StallBothInOut = 0, - #[doc = "1: If ENDPTn\\[END_STALL\\] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls."] - StallSingleDirection = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StlAdjEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STL_ADJ_EN` reader - USB Peripheral Mode Stall Adjust Enable"] -pub type StlAdjEnR = crate::BitReader; -impl StlAdjEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StlAdjEn { - match self.bits { - false => StlAdjEn::StallBothInOut, - true => StlAdjEn::StallSingleDirection, - } - } - #[doc = "If ENDPTn\\[END_STALL\\] = 1, both IN and OUT directions for the associated endpoint stalls."] - #[inline(always)] - pub fn is_stall_both_in_out(&self) -> bool { - *self == StlAdjEn::StallBothInOut - } - #[doc = "If ENDPTn\\[END_STALL\\] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls."] - #[inline(always)] - pub fn is_stall_single_direction(&self) -> bool { - *self == StlAdjEn::StallSingleDirection - } -} -#[doc = "Field `STL_ADJ_EN` writer - USB Peripheral Mode Stall Adjust Enable"] -pub type StlAdjEnW<'a, REG> = crate::BitWriter<'a, REG, StlAdjEn>; -impl<'a, REG> StlAdjEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "If ENDPTn\\[END_STALL\\] = 1, both IN and OUT directions for the associated endpoint stalls."] - #[inline(always)] - pub fn stall_both_in_out(self) -> &'a mut crate::W { - self.variant(StlAdjEn::StallBothInOut) - } - #[doc = "If ENDPTn\\[END_STALL\\] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls."] - #[inline(always)] - pub fn stall_single_direction(self) -> &'a mut crate::W { - self.variant(StlAdjEn::StallSingleDirection) - } -} -impl R { - #[doc = "Bit 0 - Dynamic SOF Threshold Compare mode"] - #[inline(always)] - pub fn sofdynthld(&self) -> SofdynthldR { - SofdynthldR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - SOF_TOK Interrupt Generation Mode Select"] - #[inline(always)] - pub fn sofbusset(&self) -> SofbussetR { - SofbussetR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - OWN Error Detect for ISO IN and ISO OUT Disable"] - #[inline(always)] - pub fn ownerrisodis(&self) -> OwnerrisodisR { - OwnerrisodisR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - VREGIN Rising Edge Interrupt Enable"] - #[inline(always)] - pub fn vredg_en(&self) -> VredgEnR { - VredgEnR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - VREGIN Falling Edge Interrupt Enable"] - #[inline(always)] - pub fn vfedg_en(&self) -> VfedgEnR { - VfedgEnR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 7 - USB Peripheral Mode Stall Adjust Enable"] - #[inline(always)] - pub fn stl_adj_en(&self) -> StlAdjEnR { - StlAdjEnR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Dynamic SOF Threshold Compare mode"] - #[inline(always)] - pub fn sofdynthld(&mut self) -> SofdynthldW { - SofdynthldW::new(self, 0) - } - #[doc = "Bit 1 - SOF_TOK Interrupt Generation Mode Select"] - #[inline(always)] - pub fn sofbusset(&mut self) -> SofbussetW { - SofbussetW::new(self, 1) - } - #[doc = "Bit 2 - OWN Error Detect for ISO IN and ISO OUT Disable"] - #[inline(always)] - pub fn ownerrisodis(&mut self) -> OwnerrisodisW { - OwnerrisodisW::new(self, 2) - } - #[doc = "Bit 3 - VREGIN Rising Edge Interrupt Enable"] - #[inline(always)] - pub fn vredg_en(&mut self) -> VredgEnW { - VredgEnW::new(self, 3) - } - #[doc = "Bit 4 - VREGIN Falling Edge Interrupt Enable"] - #[inline(always)] - pub fn vfedg_en(&mut self) -> VfedgEnW { - VfedgEnW::new(self, 4) - } - #[doc = "Bit 7 - USB Peripheral Mode Stall Adjust Enable"] - #[inline(always)] - pub fn stl_adj_en(&mut self) -> StlAdjEnW { - StlAdjEnW::new(self, 7) - } -} -#[doc = "Miscellaneous Control\n\nYou can [`read`](crate::Reg::read) this register and get [`miscctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`miscctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MiscctrlSpec; -impl crate::RegisterSpec for MiscctrlSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`miscctrl::R`](R) reader structure"] -impl crate::Readable for MiscctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`miscctrl::W`](W) writer structure"] -impl crate::Writable for MiscctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets MISCCTRL to value 0"] -impl crate::Resettable for MiscctrlSpec {} diff --git a/mcxa276-pac/src/usb0/observe.rs b/mcxa276-pac/src/usb0/observe.rs deleted file mode 100644 index 9b4b8cdf1..000000000 --- a/mcxa276-pac/src/usb0/observe.rs +++ /dev/null @@ -1,138 +0,0 @@ -#[doc = "Register `OBSERVE` reader"] -pub type R = crate::R; -#[doc = "D- Pulldown\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmpd { - #[doc = "0: Disabled"] - DmPdDisStat = 0, - #[doc = "1: Enabled"] - DmPdEnStat = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmpd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMPD` reader - D- Pulldown"] -pub type DmpdR = crate::BitReader; -impl DmpdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmpd { - match self.bits { - false => Dmpd::DmPdDisStat, - true => Dmpd::DmPdEnStat, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_dm_pd_dis_stat(&self) -> bool { - *self == Dmpd::DmPdDisStat - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_dm_pd_en_stat(&self) -> bool { - *self == Dmpd::DmPdEnStat - } -} -#[doc = "D+ Pulldown\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dppd { - #[doc = "0: Disabled"] - DpPdDisStat = 0, - #[doc = "1: Enabled"] - DpPdEnStat = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dppd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DPPD` reader - D+ Pulldown"] -pub type DppdR = crate::BitReader; -impl DppdR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dppd { - match self.bits { - false => Dppd::DpPdDisStat, - true => Dppd::DpPdEnStat, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_dp_pd_dis_stat(&self) -> bool { - *self == Dppd::DpPdDisStat - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_dp_pd_en_stat(&self) -> bool { - *self == Dppd::DpPdEnStat - } -} -#[doc = "D+ Pullup\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dppu { - #[doc = "0: Disabled"] - DpPuDisStat = 0, - #[doc = "1: Enabled"] - DpPuEnStat = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dppu) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DPPU` reader - D+ Pullup"] -pub type DppuR = crate::BitReader; -impl DppuR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dppu { - match self.bits { - false => Dppu::DpPuDisStat, - true => Dppu::DpPuEnStat, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_dp_pu_dis_stat(&self) -> bool { - *self == Dppu::DpPuDisStat - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_dp_pu_en_stat(&self) -> bool { - *self == Dppu::DpPuEnStat - } -} -impl R { - #[doc = "Bit 4 - D- Pulldown"] - #[inline(always)] - pub fn dmpd(&self) -> DmpdR { - DmpdR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 6 - D+ Pulldown"] - #[inline(always)] - pub fn dppd(&self) -> DppdR { - DppdR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - D+ Pullup"] - #[inline(always)] - pub fn dppu(&self) -> DppuR { - DppuR::new(((self.bits >> 7) & 1) != 0) - } -} -#[doc = "USB OTG Observe\n\nYou can [`read`](crate::Reg::read) this register and get [`observe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ObserveSpec; -impl crate::RegisterSpec for ObserveSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`observe::R`](R) reader structure"] -impl crate::Readable for ObserveSpec {} -#[doc = "`reset()` method sets OBSERVE to value 0x50"] -impl crate::Resettable for ObserveSpec { - const RESET_VALUE: u8 = 0x50; -} diff --git a/mcxa276-pac/src/usb0/otgctl.rs b/mcxa276-pac/src/usb0/otgctl.rs deleted file mode 100644 index ae11f0b9a..000000000 --- a/mcxa276-pac/src/usb0/otgctl.rs +++ /dev/null @@ -1,273 +0,0 @@ -#[doc = "Register `OTGCTL` reader"] -pub type R = crate::R; -#[doc = "Register `OTGCTL` writer"] -pub type W = crate::W; -#[doc = "On-The-Go Pullup and Pulldown Resistor Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Otgen { - #[doc = "0: If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."] - ConfigResistorsCtl = 0, - #[doc = "1: Uses the pullup and pulldown controls in this register."] - ConfigResistorsHere = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Otgen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OTGEN` reader - On-The-Go Pullup and Pulldown Resistor Enable"] -pub type OtgenR = crate::BitReader; -impl OtgenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Otgen { - match self.bits { - false => Otgen::ConfigResistorsCtl, - true => Otgen::ConfigResistorsHere, - } - } - #[doc = "If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."] - #[inline(always)] - pub fn is_config_resistors_ctl(&self) -> bool { - *self == Otgen::ConfigResistorsCtl - } - #[doc = "Uses the pullup and pulldown controls in this register."] - #[inline(always)] - pub fn is_config_resistors_here(&self) -> bool { - *self == Otgen::ConfigResistorsHere - } -} -#[doc = "Field `OTGEN` writer - On-The-Go Pullup and Pulldown Resistor Enable"] -pub type OtgenW<'a, REG> = crate::BitWriter<'a, REG, Otgen>; -impl<'a, REG> OtgenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."] - #[inline(always)] - pub fn config_resistors_ctl(self) -> &'a mut crate::W { - self.variant(Otgen::ConfigResistorsCtl) - } - #[doc = "Uses the pullup and pulldown controls in this register."] - #[inline(always)] - pub fn config_resistors_here(self) -> &'a mut crate::W { - self.variant(Otgen::ConfigResistorsHere) - } -} -#[doc = "D- Data Line Pulldown Resistor Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dmlow { - #[doc = "0: Disable"] - DisDmPulldown = 0, - #[doc = "1: Enable"] - EnDmPulldown = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dmlow) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DMLOW` reader - D- Data Line Pulldown Resistor Enable"] -pub type DmlowR = crate::BitReader; -impl DmlowR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dmlow { - match self.bits { - false => Dmlow::DisDmPulldown, - true => Dmlow::EnDmPulldown, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_dm_pulldown(&self) -> bool { - *self == Dmlow::DisDmPulldown - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_dm_pulldown(&self) -> bool { - *self == Dmlow::EnDmPulldown - } -} -#[doc = "Field `DMLOW` writer - D- Data Line Pulldown Resistor Enable"] -pub type DmlowW<'a, REG> = crate::BitWriter<'a, REG, Dmlow>; -impl<'a, REG> DmlowW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_dm_pulldown(self) -> &'a mut crate::W { - self.variant(Dmlow::DisDmPulldown) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_dm_pulldown(self) -> &'a mut crate::W { - self.variant(Dmlow::EnDmPulldown) - } -} -#[doc = "D+ Data Line pulldown Resistor Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dplow { - #[doc = "0: Disable"] - DisDpPulldown = 0, - #[doc = "1: Enable"] - EnDpPulldown = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dplow) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DPLOW` reader - D+ Data Line pulldown Resistor Enable"] -pub type DplowR = crate::BitReader; -impl DplowR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dplow { - match self.bits { - false => Dplow::DisDpPulldown, - true => Dplow::EnDpPulldown, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_dp_pulldown(&self) -> bool { - *self == Dplow::DisDpPulldown - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_dp_pulldown(&self) -> bool { - *self == Dplow::EnDpPulldown - } -} -#[doc = "Field `DPLOW` writer - D+ Data Line pulldown Resistor Enable"] -pub type DplowW<'a, REG> = crate::BitWriter<'a, REG, Dplow>; -impl<'a, REG> DplowW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_dp_pulldown(self) -> &'a mut crate::W { - self.variant(Dplow::DisDpPulldown) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_dp_pulldown(self) -> &'a mut crate::W { - self.variant(Dplow::EnDpPulldown) - } -} -#[doc = "D+ Data Line Pullup Resistor Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Dphigh { - #[doc = "0: Disable"] - DisDpPullup = 0, - #[doc = "1: Enable"] - EnDpPullup = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Dphigh) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DPHIGH` reader - D+ Data Line Pullup Resistor Enable"] -pub type DphighR = crate::BitReader; -impl DphighR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Dphigh { - match self.bits { - false => Dphigh::DisDpPullup, - true => Dphigh::EnDpPullup, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_dp_pullup(&self) -> bool { - *self == Dphigh::DisDpPullup - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_dp_pullup(&self) -> bool { - *self == Dphigh::EnDpPullup - } -} -#[doc = "Field `DPHIGH` writer - D+ Data Line Pullup Resistor Enable"] -pub type DphighW<'a, REG> = crate::BitWriter<'a, REG, Dphigh>; -impl<'a, REG> DphighW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_dp_pullup(self) -> &'a mut crate::W { - self.variant(Dphigh::DisDpPullup) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_dp_pullup(self) -> &'a mut crate::W { - self.variant(Dphigh::EnDpPullup) - } -} -impl R { - #[doc = "Bit 2 - On-The-Go Pullup and Pulldown Resistor Enable"] - #[inline(always)] - pub fn otgen(&self) -> OtgenR { - OtgenR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 4 - D- Data Line Pulldown Resistor Enable"] - #[inline(always)] - pub fn dmlow(&self) -> DmlowR { - DmlowR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - D+ Data Line pulldown Resistor Enable"] - #[inline(always)] - pub fn dplow(&self) -> DplowR { - DplowR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 7 - D+ Data Line Pullup Resistor Enable"] - #[inline(always)] - pub fn dphigh(&self) -> DphighR { - DphighR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 2 - On-The-Go Pullup and Pulldown Resistor Enable"] - #[inline(always)] - pub fn otgen(&mut self) -> OtgenW { - OtgenW::new(self, 2) - } - #[doc = "Bit 4 - D- Data Line Pulldown Resistor Enable"] - #[inline(always)] - pub fn dmlow(&mut self) -> DmlowW { - DmlowW::new(self, 4) - } - #[doc = "Bit 5 - D+ Data Line pulldown Resistor Enable"] - #[inline(always)] - pub fn dplow(&mut self) -> DplowW { - DplowW::new(self, 5) - } - #[doc = "Bit 7 - D+ Data Line Pullup Resistor Enable"] - #[inline(always)] - pub fn dphigh(&mut self) -> DphighW { - DphighW::new(self, 7) - } -} -#[doc = "OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OtgctlSpec; -impl crate::RegisterSpec for OtgctlSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`otgctl::R`](R) reader structure"] -impl crate::Readable for OtgctlSpec {} -#[doc = "`write(|w| ..)` method takes [`otgctl::W`](W) writer structure"] -impl crate::Writable for OtgctlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets OTGCTL to value 0"] -impl crate::Resettable for OtgctlSpec {} diff --git a/mcxa276-pac/src/usb0/otgicr.rs b/mcxa276-pac/src/usb0/otgicr.rs deleted file mode 100644 index cb5202e68..000000000 --- a/mcxa276-pac/src/usb0/otgicr.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `OTGICR` reader"] -pub type R = crate::R; -#[doc = "Register `OTGICR` writer"] -pub type W = crate::W; -#[doc = "Line State Change Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Linestateen { - #[doc = "0: Disable"] - DisLinestInt = 0, - #[doc = "1: Enable"] - EnLinestInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Linestateen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LINESTATEEN` reader - Line State Change Interrupt Enable"] -pub type LinestateenR = crate::BitReader; -impl LinestateenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Linestateen { - match self.bits { - false => Linestateen::DisLinestInt, - true => Linestateen::EnLinestInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_linest_int(&self) -> bool { - *self == Linestateen::DisLinestInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_linest_int(&self) -> bool { - *self == Linestateen::EnLinestInt - } -} -#[doc = "Field `LINESTATEEN` writer - Line State Change Interrupt Enable"] -pub type LinestateenW<'a, REG> = crate::BitWriter<'a, REG, Linestateen>; -impl<'a, REG> LinestateenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_linest_int(self) -> &'a mut crate::W { - self.variant(Linestateen::DisLinestInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_linest_int(self) -> &'a mut crate::W { - self.variant(Linestateen::EnLinestInt) - } -} -#[doc = "1-Millisecond Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Onemsecen { - #[doc = "0: Disable"] - DisTimerInt = 0, - #[doc = "1: Enable"] - EnTimerInt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Onemsecen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONEMSECEN` reader - 1-Millisecond Interrupt Enable"] -pub type OnemsecenR = crate::BitReader; -impl OnemsecenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Onemsecen { - match self.bits { - false => Onemsecen::DisTimerInt, - true => Onemsecen::EnTimerInt, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_timer_int(&self) -> bool { - *self == Onemsecen::DisTimerInt - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_timer_int(&self) -> bool { - *self == Onemsecen::EnTimerInt - } -} -#[doc = "Field `ONEMSECEN` writer - 1-Millisecond Interrupt Enable"] -pub type OnemsecenW<'a, REG> = crate::BitWriter<'a, REG, Onemsecen>; -impl<'a, REG> OnemsecenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_timer_int(self) -> &'a mut crate::W { - self.variant(Onemsecen::DisTimerInt) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_timer_int(self) -> &'a mut crate::W { - self.variant(Onemsecen::EnTimerInt) - } -} -impl R { - #[doc = "Bit 5 - Line State Change Interrupt Enable"] - #[inline(always)] - pub fn linestateen(&self) -> LinestateenR { - LinestateenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - 1-Millisecond Interrupt Enable"] - #[inline(always)] - pub fn onemsecen(&self) -> OnemsecenR { - OnemsecenR::new(((self.bits >> 6) & 1) != 0) - } -} -impl W { - #[doc = "Bit 5 - Line State Change Interrupt Enable"] - #[inline(always)] - pub fn linestateen(&mut self) -> LinestateenW { - LinestateenW::new(self, 5) - } - #[doc = "Bit 6 - 1-Millisecond Interrupt Enable"] - #[inline(always)] - pub fn onemsecen(&mut self) -> OnemsecenW { - OnemsecenW::new(self, 6) - } -} -#[doc = "OTG Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OtgicrSpec; -impl crate::RegisterSpec for OtgicrSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`otgicr::R`](R) reader structure"] -impl crate::Readable for OtgicrSpec {} -#[doc = "`write(|w| ..)` method takes [`otgicr::W`](W) writer structure"] -impl crate::Writable for OtgicrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets OTGICR to value 0"] -impl crate::Resettable for OtgicrSpec {} diff --git a/mcxa276-pac/src/usb0/otgistat.rs b/mcxa276-pac/src/usb0/otgistat.rs deleted file mode 100644 index cda3b24a3..000000000 --- a/mcxa276-pac/src/usb0/otgistat.rs +++ /dev/null @@ -1,148 +0,0 @@ -#[doc = "Register `OTGISTAT` reader"] -pub type R = crate::R; -#[doc = "Register `OTGISTAT` writer"] -pub type W = crate::W; -#[doc = "Line State Change Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum LineStateChg { - #[doc = "0: Interrupt did not occur"] - IntNo = 0, - #[doc = "1: Interrupt occurred"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: LineStateChg) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LINE_STATE_CHG` reader - Line State Change Interrupt Flag"] -pub type LineStateChgR = crate::BitReader; -impl LineStateChgR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> LineStateChg { - match self.bits { - false => LineStateChg::IntNo, - true => LineStateChg::IntYes, - } - } - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == LineStateChg::IntNo - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == LineStateChg::IntYes - } -} -#[doc = "Field `LINE_STATE_CHG` writer - Line State Change Interrupt Flag"] -pub type LineStateChgW<'a, REG> = crate::BitWriter1C<'a, REG, LineStateChg>; -impl<'a, REG> LineStateChgW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt did not occur"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(LineStateChg::IntNo) - } - #[doc = "Interrupt occurred"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(LineStateChg::IntYes) - } -} -#[doc = "One Millisecond Timer Timeout Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Onemsec { - #[doc = "0: Not timed out"] - IntNo = 0, - #[doc = "1: Timed out"] - IntYes = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Onemsec) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ONEMSEC` reader - One Millisecond Timer Timeout Flag"] -pub type OnemsecR = crate::BitReader; -impl OnemsecR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Onemsec { - match self.bits { - false => Onemsec::IntNo, - true => Onemsec::IntYes, - } - } - #[doc = "Not timed out"] - #[inline(always)] - pub fn is_int_no(&self) -> bool { - *self == Onemsec::IntNo - } - #[doc = "Timed out"] - #[inline(always)] - pub fn is_int_yes(&self) -> bool { - *self == Onemsec::IntYes - } -} -#[doc = "Field `ONEMSEC` writer - One Millisecond Timer Timeout Flag"] -pub type OnemsecW<'a, REG> = crate::BitWriter1C<'a, REG, Onemsec>; -impl<'a, REG> OnemsecW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not timed out"] - #[inline(always)] - pub fn int_no(self) -> &'a mut crate::W { - self.variant(Onemsec::IntNo) - } - #[doc = "Timed out"] - #[inline(always)] - pub fn int_yes(self) -> &'a mut crate::W { - self.variant(Onemsec::IntYes) - } -} -impl R { - #[doc = "Bit 5 - Line State Change Interrupt Flag"] - #[inline(always)] - pub fn line_state_chg(&self) -> LineStateChgR { - LineStateChgR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - One Millisecond Timer Timeout Flag"] - #[inline(always)] - pub fn onemsec(&self) -> OnemsecR { - OnemsecR::new(((self.bits >> 6) & 1) != 0) - } -} -impl W { - #[doc = "Bit 5 - Line State Change Interrupt Flag"] - #[inline(always)] - pub fn line_state_chg(&mut self) -> LineStateChgW { - LineStateChgW::new(self, 5) - } - #[doc = "Bit 6 - One Millisecond Timer Timeout Flag"] - #[inline(always)] - pub fn onemsec(&mut self) -> OnemsecW { - OnemsecW::new(self, 6) - } -} -#[doc = "OTG Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgistat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgistat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OtgistatSpec; -impl crate::RegisterSpec for OtgistatSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`otgistat::R`](R) reader structure"] -impl crate::Readable for OtgistatSpec {} -#[doc = "`write(|w| ..)` method takes [`otgistat::W`](W) writer structure"] -impl crate::Writable for OtgistatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0x60; -} -#[doc = "`reset()` method sets OTGISTAT to value 0"] -impl crate::Resettable for OtgistatSpec {} diff --git a/mcxa276-pac/src/usb0/otgstat.rs b/mcxa276-pac/src/usb0/otgstat.rs deleted file mode 100644 index 158c1f525..000000000 --- a/mcxa276-pac/src/usb0/otgstat.rs +++ /dev/null @@ -1,61 +0,0 @@ -#[doc = "Register `OTGSTAT` reader"] -pub type R = crate::R; -#[doc = "Line State Stable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Linestatestable { - #[doc = "0: Unstable"] - LinestNotStable = 0, - #[doc = "1: Stable"] - LinestStable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Linestatestable) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LINESTATESTABLE` reader - Line State Stable"] -pub type LinestatestableR = crate::BitReader; -impl LinestatestableR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Linestatestable { - match self.bits { - false => Linestatestable::LinestNotStable, - true => Linestatestable::LinestStable, - } - } - #[doc = "Unstable"] - #[inline(always)] - pub fn is_linest_not_stable(&self) -> bool { - *self == Linestatestable::LinestNotStable - } - #[doc = "Stable"] - #[inline(always)] - pub fn is_linest_stable(&self) -> bool { - *self == Linestatestable::LinestStable - } -} -#[doc = "Field `ONEMSEC` reader - Reserved for 1 ms count"] -pub type OnemsecR = crate::BitReader; -impl R { - #[doc = "Bit 5 - Line State Stable"] - #[inline(always)] - pub fn linestatestable(&self) -> LinestatestableR { - LinestatestableR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Reserved for 1 ms count"] - #[inline(always)] - pub fn onemsec(&self) -> OnemsecR { - OnemsecR::new(((self.bits >> 6) & 1) != 0) - } -} -#[doc = "OTG Status\n\nYou can [`read`](crate::Reg::read) this register and get [`otgstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct OtgstatSpec; -impl crate::RegisterSpec for OtgstatSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`otgstat::R`](R) reader structure"] -impl crate::Readable for OtgstatSpec {} -#[doc = "`reset()` method sets OTGSTAT to value 0"] -impl crate::Resettable for OtgstatSpec {} diff --git a/mcxa276-pac/src/usb0/perid.rs b/mcxa276-pac/src/usb0/perid.rs deleted file mode 100644 index 362f19328..000000000 --- a/mcxa276-pac/src/usb0/perid.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `PERID` reader"] -pub type R = crate::R; -#[doc = "Field `ID` reader - Peripheral Identification"] -pub type IdR = crate::FieldReader; -impl R { - #[doc = "Bits 0:5 - Peripheral Identification"] - #[inline(always)] - pub fn id(&self) -> IdR { - IdR::new(self.bits & 0x3f) - } -} -#[doc = "Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PeridSpec; -impl crate::RegisterSpec for PeridSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`perid::R`](R) reader structure"] -impl crate::Readable for PeridSpec {} -#[doc = "`reset()` method sets PERID to value 0x04"] -impl crate::Resettable for PeridSpec { - const RESET_VALUE: u8 = 0x04; -} diff --git a/mcxa276-pac/src/usb0/rev.rs b/mcxa276-pac/src/usb0/rev.rs deleted file mode 100644 index 50e00f689..000000000 --- a/mcxa276-pac/src/usb0/rev.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `REV` reader"] -pub type R = crate::R; -#[doc = "Field `REV` reader - Revision"] -pub type RevR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Revision"] - #[inline(always)] - pub fn rev(&self) -> RevR { - RevR::new(self.bits) - } -} -#[doc = "Peripheral Revision\n\nYou can [`read`](crate::Reg::read) this register and get [`rev::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RevSpec; -impl crate::RegisterSpec for RevSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`rev::R`](R) reader structure"] -impl crate::Readable for RevSpec {} -#[doc = "`reset()` method sets REV to value 0x33"] -impl crate::Resettable for RevSpec { - const RESET_VALUE: u8 = 0x33; -} diff --git a/mcxa276-pac/src/usb0/softhld.rs b/mcxa276-pac/src/usb0/softhld.rs deleted file mode 100644 index 1e873f12e..000000000 --- a/mcxa276-pac/src/usb0/softhld.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `SOFTHLD` reader"] -pub type R = crate::R; -#[doc = "Register `SOFTHLD` writer"] -pub type W = crate::W; -#[doc = "Field `CNT` reader - SOF Count Threshold"] -pub type CntR = crate::FieldReader; -#[doc = "Field `CNT` writer - SOF Count Threshold"] -pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - SOF Count Threshold"] - #[inline(always)] - pub fn cnt(&self) -> CntR { - CntR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:7 - SOF Count Threshold"] - #[inline(always)] - pub fn cnt(&mut self) -> CntW { - CntW::new(self, 0) - } -} -#[doc = "SOF Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`softhld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`softhld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SofthldSpec; -impl crate::RegisterSpec for SofthldSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`softhld::R`](R) reader structure"] -impl crate::Readable for SofthldSpec {} -#[doc = "`write(|w| ..)` method takes [`softhld::W`](W) writer structure"] -impl crate::Writable for SofthldSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets SOFTHLD to value 0"] -impl crate::Resettable for SofthldSpec {} diff --git a/mcxa276-pac/src/usb0/stall_ih_dis.rs b/mcxa276-pac/src/usb0/stall_ih_dis.rs deleted file mode 100644 index ed9b19c10..000000000 --- a/mcxa276-pac/src/usb0/stall_ih_dis.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `STALL_IH_DIS` reader"] -pub type R = crate::R; -#[doc = "Register `STALL_IH_DIS` writer"] -pub type W = crate::W; -#[doc = "Disable Endpoint 8 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis8 { - #[doc = "0: Enable"] - EnEp8InStall = 0, - #[doc = "1: Disable"] - DisEp8InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS8` reader - Disable Endpoint 8 IN Direction"] -pub type StallIDis8R = crate::BitReader; -impl StallIDis8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis8 { - match self.bits { - false => StallIDis8::EnEp8InStall, - true => StallIDis8::DisEp8InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep8_in_stall(&self) -> bool { - *self == StallIDis8::EnEp8InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep8_in_stall(&self) -> bool { - *self == StallIDis8::DisEp8InStall - } -} -#[doc = "Field `STALL_I_DIS8` writer - Disable Endpoint 8 IN Direction"] -pub type StallIDis8W<'a, REG> = crate::BitWriter<'a, REG, StallIDis8>; -impl<'a, REG> StallIDis8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep8_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis8::EnEp8InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep8_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis8::DisEp8InStall) - } -} -#[doc = "Disable Endpoint 9 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis9 { - #[doc = "0: Enable"] - EnEp9InStall = 0, - #[doc = "1: Disable"] - DisEp9InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS9` reader - Disable Endpoint 9 IN Direction"] -pub type StallIDis9R = crate::BitReader; -impl StallIDis9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis9 { - match self.bits { - false => StallIDis9::EnEp9InStall, - true => StallIDis9::DisEp9InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep9_in_stall(&self) -> bool { - *self == StallIDis9::EnEp9InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep9_in_stall(&self) -> bool { - *self == StallIDis9::DisEp9InStall - } -} -#[doc = "Field `STALL_I_DIS9` writer - Disable Endpoint 9 IN Direction"] -pub type StallIDis9W<'a, REG> = crate::BitWriter<'a, REG, StallIDis9>; -impl<'a, REG> StallIDis9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep9_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis9::EnEp9InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep9_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis9::DisEp9InStall) - } -} -#[doc = "Disable Endpoint 10 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis10 { - #[doc = "0: Enable"] - EnEp10InStall = 0, - #[doc = "1: Disable"] - DisEp10InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS10` reader - Disable Endpoint 10 IN Direction"] -pub type StallIDis10R = crate::BitReader; -impl StallIDis10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis10 { - match self.bits { - false => StallIDis10::EnEp10InStall, - true => StallIDis10::DisEp10InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep10_in_stall(&self) -> bool { - *self == StallIDis10::EnEp10InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep10_in_stall(&self) -> bool { - *self == StallIDis10::DisEp10InStall - } -} -#[doc = "Field `STALL_I_DIS10` writer - Disable Endpoint 10 IN Direction"] -pub type StallIDis10W<'a, REG> = crate::BitWriter<'a, REG, StallIDis10>; -impl<'a, REG> StallIDis10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep10_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis10::EnEp10InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep10_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis10::DisEp10InStall) - } -} -#[doc = "Disable Endpoint 11 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis11 { - #[doc = "0: Enable"] - EnEp11InStall = 0, - #[doc = "1: Disable"] - DisEp11InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS11` reader - Disable Endpoint 11 IN Direction"] -pub type StallIDis11R = crate::BitReader; -impl StallIDis11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis11 { - match self.bits { - false => StallIDis11::EnEp11InStall, - true => StallIDis11::DisEp11InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep11_in_stall(&self) -> bool { - *self == StallIDis11::EnEp11InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep11_in_stall(&self) -> bool { - *self == StallIDis11::DisEp11InStall - } -} -#[doc = "Field `STALL_I_DIS11` writer - Disable Endpoint 11 IN Direction"] -pub type StallIDis11W<'a, REG> = crate::BitWriter<'a, REG, StallIDis11>; -impl<'a, REG> StallIDis11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep11_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis11::EnEp11InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep11_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis11::DisEp11InStall) - } -} -#[doc = "Disable Endpoint 12 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis12 { - #[doc = "0: Enable"] - EnEp12InStall = 0, - #[doc = "1: Disable"] - DisEp12InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS12` reader - Disable Endpoint 12 IN Direction"] -pub type StallIDis12R = crate::BitReader; -impl StallIDis12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis12 { - match self.bits { - false => StallIDis12::EnEp12InStall, - true => StallIDis12::DisEp12InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep12_in_stall(&self) -> bool { - *self == StallIDis12::EnEp12InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep12_in_stall(&self) -> bool { - *self == StallIDis12::DisEp12InStall - } -} -#[doc = "Field `STALL_I_DIS12` writer - Disable Endpoint 12 IN Direction"] -pub type StallIDis12W<'a, REG> = crate::BitWriter<'a, REG, StallIDis12>; -impl<'a, REG> StallIDis12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep12_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis12::EnEp12InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep12_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis12::DisEp12InStall) - } -} -#[doc = "Disable Endpoint 13 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis13 { - #[doc = "0: Enable"] - EnEp13InStall = 0, - #[doc = "1: Disable"] - DisEp13InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS13` reader - Disable Endpoint 13 IN Direction"] -pub type StallIDis13R = crate::BitReader; -impl StallIDis13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis13 { - match self.bits { - false => StallIDis13::EnEp13InStall, - true => StallIDis13::DisEp13InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep13_in_stall(&self) -> bool { - *self == StallIDis13::EnEp13InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep13_in_stall(&self) -> bool { - *self == StallIDis13::DisEp13InStall - } -} -#[doc = "Field `STALL_I_DIS13` writer - Disable Endpoint 13 IN Direction"] -pub type StallIDis13W<'a, REG> = crate::BitWriter<'a, REG, StallIDis13>; -impl<'a, REG> StallIDis13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep13_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis13::EnEp13InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep13_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis13::DisEp13InStall) - } -} -#[doc = "Disable Endpoint 14 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis14 { - #[doc = "0: Enable"] - EnEp14InStall = 0, - #[doc = "1: Disable"] - DisEp14InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS14` reader - Disable Endpoint 14 IN Direction"] -pub type StallIDis14R = crate::BitReader; -impl StallIDis14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis14 { - match self.bits { - false => StallIDis14::EnEp14InStall, - true => StallIDis14::DisEp14InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep14_in_stall(&self) -> bool { - *self == StallIDis14::EnEp14InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep14_in_stall(&self) -> bool { - *self == StallIDis14::DisEp14InStall - } -} -#[doc = "Field `STALL_I_DIS14` writer - Disable Endpoint 14 IN Direction"] -pub type StallIDis14W<'a, REG> = crate::BitWriter<'a, REG, StallIDis14>; -impl<'a, REG> StallIDis14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep14_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis14::EnEp14InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep14_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis14::DisEp14InStall) - } -} -#[doc = "Disable Endpoint 15 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis15 { - #[doc = "0: Enable"] - EnEp15InStall = 0, - #[doc = "1: Disable"] - DisEp15InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS15` reader - Disable Endpoint 15 IN Direction"] -pub type StallIDis15R = crate::BitReader; -impl StallIDis15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis15 { - match self.bits { - false => StallIDis15::EnEp15InStall, - true => StallIDis15::DisEp15InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep15_in_stall(&self) -> bool { - *self == StallIDis15::EnEp15InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep15_in_stall(&self) -> bool { - *self == StallIDis15::DisEp15InStall - } -} -#[doc = "Field `STALL_I_DIS15` writer - Disable Endpoint 15 IN Direction"] -pub type StallIDis15W<'a, REG> = crate::BitWriter<'a, REG, StallIDis15>; -impl<'a, REG> StallIDis15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep15_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis15::EnEp15InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep15_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis15::DisEp15InStall) - } -} -impl R { - #[doc = "Bit 0 - Disable Endpoint 8 IN Direction"] - #[inline(always)] - pub fn stall_i_dis8(&self) -> StallIDis8R { - StallIDis8R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Disable Endpoint 9 IN Direction"] - #[inline(always)] - pub fn stall_i_dis9(&self) -> StallIDis9R { - StallIDis9R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Disable Endpoint 10 IN Direction"] - #[inline(always)] - pub fn stall_i_dis10(&self) -> StallIDis10R { - StallIDis10R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Disable Endpoint 11 IN Direction"] - #[inline(always)] - pub fn stall_i_dis11(&self) -> StallIDis11R { - StallIDis11R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Disable Endpoint 12 IN Direction"] - #[inline(always)] - pub fn stall_i_dis12(&self) -> StallIDis12R { - StallIDis12R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Disable Endpoint 13 IN Direction"] - #[inline(always)] - pub fn stall_i_dis13(&self) -> StallIDis13R { - StallIDis13R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Disable Endpoint 14 IN Direction"] - #[inline(always)] - pub fn stall_i_dis14(&self) -> StallIDis14R { - StallIDis14R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Disable Endpoint 15 IN Direction"] - #[inline(always)] - pub fn stall_i_dis15(&self) -> StallIDis15R { - StallIDis15R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Disable Endpoint 8 IN Direction"] - #[inline(always)] - pub fn stall_i_dis8(&mut self) -> StallIDis8W { - StallIDis8W::new(self, 0) - } - #[doc = "Bit 1 - Disable Endpoint 9 IN Direction"] - #[inline(always)] - pub fn stall_i_dis9(&mut self) -> StallIDis9W { - StallIDis9W::new(self, 1) - } - #[doc = "Bit 2 - Disable Endpoint 10 IN Direction"] - #[inline(always)] - pub fn stall_i_dis10(&mut self) -> StallIDis10W { - StallIDis10W::new(self, 2) - } - #[doc = "Bit 3 - Disable Endpoint 11 IN Direction"] - #[inline(always)] - pub fn stall_i_dis11(&mut self) -> StallIDis11W { - StallIDis11W::new(self, 3) - } - #[doc = "Bit 4 - Disable Endpoint 12 IN Direction"] - #[inline(always)] - pub fn stall_i_dis12(&mut self) -> StallIDis12W { - StallIDis12W::new(self, 4) - } - #[doc = "Bit 5 - Disable Endpoint 13 IN Direction"] - #[inline(always)] - pub fn stall_i_dis13(&mut self) -> StallIDis13W { - StallIDis13W::new(self, 5) - } - #[doc = "Bit 6 - Disable Endpoint 14 IN Direction"] - #[inline(always)] - pub fn stall_i_dis14(&mut self) -> StallIDis14W { - StallIDis14W::new(self, 6) - } - #[doc = "Bit 7 - Disable Endpoint 15 IN Direction"] - #[inline(always)] - pub fn stall_i_dis15(&mut self) -> StallIDis15W { - StallIDis15W::new(self, 7) - } -} -#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ih_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ih_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StallIhDisSpec; -impl crate::RegisterSpec for StallIhDisSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`stall_ih_dis::R`](R) reader structure"] -impl crate::Readable for StallIhDisSpec {} -#[doc = "`write(|w| ..)` method takes [`stall_ih_dis::W`](W) writer structure"] -impl crate::Writable for StallIhDisSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STALL_IH_DIS to value 0"] -impl crate::Resettable for StallIhDisSpec {} diff --git a/mcxa276-pac/src/usb0/stall_il_dis.rs b/mcxa276-pac/src/usb0/stall_il_dis.rs deleted file mode 100644 index fe0b28c94..000000000 --- a/mcxa276-pac/src/usb0/stall_il_dis.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `STALL_IL_DIS` reader"] -pub type R = crate::R; -#[doc = "Register `STALL_IL_DIS` writer"] -pub type W = crate::W; -#[doc = "Disable Endpoint 0 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis0 { - #[doc = "0: Enable"] - EnEp0InStall = 0, - #[doc = "1: Disable"] - DisEp0InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS0` reader - Disable Endpoint 0 IN Direction"] -pub type StallIDis0R = crate::BitReader; -impl StallIDis0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis0 { - match self.bits { - false => StallIDis0::EnEp0InStall, - true => StallIDis0::DisEp0InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep0_in_stall(&self) -> bool { - *self == StallIDis0::EnEp0InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep0_in_stall(&self) -> bool { - *self == StallIDis0::DisEp0InStall - } -} -#[doc = "Field `STALL_I_DIS0` writer - Disable Endpoint 0 IN Direction"] -pub type StallIDis0W<'a, REG> = crate::BitWriter<'a, REG, StallIDis0>; -impl<'a, REG> StallIDis0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep0_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis0::EnEp0InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep0_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis0::DisEp0InStall) - } -} -#[doc = "Disable Endpoint 1 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis1 { - #[doc = "0: Enable"] - EnEp1InStall = 0, - #[doc = "1: Disable"] - DisEp1InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS1` reader - Disable Endpoint 1 IN Direction"] -pub type StallIDis1R = crate::BitReader; -impl StallIDis1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis1 { - match self.bits { - false => StallIDis1::EnEp1InStall, - true => StallIDis1::DisEp1InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep1_in_stall(&self) -> bool { - *self == StallIDis1::EnEp1InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep1_in_stall(&self) -> bool { - *self == StallIDis1::DisEp1InStall - } -} -#[doc = "Field `STALL_I_DIS1` writer - Disable Endpoint 1 IN Direction"] -pub type StallIDis1W<'a, REG> = crate::BitWriter<'a, REG, StallIDis1>; -impl<'a, REG> StallIDis1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep1_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis1::EnEp1InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep1_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis1::DisEp1InStall) - } -} -#[doc = "Disable Endpoint 2 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis2 { - #[doc = "0: Enable"] - EnEp2InStall = 0, - #[doc = "1: Disable"] - DisEp2InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS2` reader - Disable Endpoint 2 IN Direction"] -pub type StallIDis2R = crate::BitReader; -impl StallIDis2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis2 { - match self.bits { - false => StallIDis2::EnEp2InStall, - true => StallIDis2::DisEp2InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep2_in_stall(&self) -> bool { - *self == StallIDis2::EnEp2InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep2_in_stall(&self) -> bool { - *self == StallIDis2::DisEp2InStall - } -} -#[doc = "Field `STALL_I_DIS2` writer - Disable Endpoint 2 IN Direction"] -pub type StallIDis2W<'a, REG> = crate::BitWriter<'a, REG, StallIDis2>; -impl<'a, REG> StallIDis2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep2_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis2::EnEp2InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep2_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis2::DisEp2InStall) - } -} -#[doc = "Disable Endpoint 3 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis3 { - #[doc = "0: Enable"] - EnEp3InStall = 0, - #[doc = "1: Disable"] - DisEp3InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS3` reader - Disable Endpoint 3 IN Direction"] -pub type StallIDis3R = crate::BitReader; -impl StallIDis3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis3 { - match self.bits { - false => StallIDis3::EnEp3InStall, - true => StallIDis3::DisEp3InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep3_in_stall(&self) -> bool { - *self == StallIDis3::EnEp3InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep3_in_stall(&self) -> bool { - *self == StallIDis3::DisEp3InStall - } -} -#[doc = "Field `STALL_I_DIS3` writer - Disable Endpoint 3 IN Direction"] -pub type StallIDis3W<'a, REG> = crate::BitWriter<'a, REG, StallIDis3>; -impl<'a, REG> StallIDis3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep3_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis3::EnEp3InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep3_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis3::DisEp3InStall) - } -} -#[doc = "Disable Endpoint 4 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis4 { - #[doc = "0: Enable"] - EnEp4InStall = 0, - #[doc = "1: Disable"] - DisEp4InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS4` reader - Disable Endpoint 4 IN Direction"] -pub type StallIDis4R = crate::BitReader; -impl StallIDis4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis4 { - match self.bits { - false => StallIDis4::EnEp4InStall, - true => StallIDis4::DisEp4InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep4_in_stall(&self) -> bool { - *self == StallIDis4::EnEp4InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep4_in_stall(&self) -> bool { - *self == StallIDis4::DisEp4InStall - } -} -#[doc = "Field `STALL_I_DIS4` writer - Disable Endpoint 4 IN Direction"] -pub type StallIDis4W<'a, REG> = crate::BitWriter<'a, REG, StallIDis4>; -impl<'a, REG> StallIDis4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep4_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis4::EnEp4InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep4_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis4::DisEp4InStall) - } -} -#[doc = "Disable Endpoint 5 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis5 { - #[doc = "0: Enable"] - EnEp5InStall = 0, - #[doc = "1: Disable"] - DisEp5InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS5` reader - Disable Endpoint 5 IN Direction"] -pub type StallIDis5R = crate::BitReader; -impl StallIDis5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis5 { - match self.bits { - false => StallIDis5::EnEp5InStall, - true => StallIDis5::DisEp5InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep5_in_stall(&self) -> bool { - *self == StallIDis5::EnEp5InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep5_in_stall(&self) -> bool { - *self == StallIDis5::DisEp5InStall - } -} -#[doc = "Field `STALL_I_DIS5` writer - Disable Endpoint 5 IN Direction"] -pub type StallIDis5W<'a, REG> = crate::BitWriter<'a, REG, StallIDis5>; -impl<'a, REG> StallIDis5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep5_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis5::EnEp5InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep5_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis5::DisEp5InStall) - } -} -#[doc = "Disable Endpoint 6 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis6 { - #[doc = "0: Enable"] - EnEp6InStall = 0, - #[doc = "1: Disable"] - DisEp6InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS6` reader - Disable Endpoint 6 IN Direction"] -pub type StallIDis6R = crate::BitReader; -impl StallIDis6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis6 { - match self.bits { - false => StallIDis6::EnEp6InStall, - true => StallIDis6::DisEp6InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep6_in_stall(&self) -> bool { - *self == StallIDis6::EnEp6InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep6_in_stall(&self) -> bool { - *self == StallIDis6::DisEp6InStall - } -} -#[doc = "Field `STALL_I_DIS6` writer - Disable Endpoint 6 IN Direction"] -pub type StallIDis6W<'a, REG> = crate::BitWriter<'a, REG, StallIDis6>; -impl<'a, REG> StallIDis6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep6_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis6::EnEp6InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep6_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis6::DisEp6InStall) - } -} -#[doc = "Disable Endpoint 7 IN Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallIDis7 { - #[doc = "0: Enable"] - EnEp7InStall = 0, - #[doc = "1: Disable"] - DisEp7InStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallIDis7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_I_DIS7` reader - Disable Endpoint 7 IN Direction"] -pub type StallIDis7R = crate::BitReader; -impl StallIDis7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallIDis7 { - match self.bits { - false => StallIDis7::EnEp7InStall, - true => StallIDis7::DisEp7InStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep7_in_stall(&self) -> bool { - *self == StallIDis7::EnEp7InStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep7_in_stall(&self) -> bool { - *self == StallIDis7::DisEp7InStall - } -} -#[doc = "Field `STALL_I_DIS7` writer - Disable Endpoint 7 IN Direction"] -pub type StallIDis7W<'a, REG> = crate::BitWriter<'a, REG, StallIDis7>; -impl<'a, REG> StallIDis7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep7_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis7::EnEp7InStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep7_in_stall(self) -> &'a mut crate::W { - self.variant(StallIDis7::DisEp7InStall) - } -} -impl R { - #[doc = "Bit 0 - Disable Endpoint 0 IN Direction"] - #[inline(always)] - pub fn stall_i_dis0(&self) -> StallIDis0R { - StallIDis0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Disable Endpoint 1 IN Direction"] - #[inline(always)] - pub fn stall_i_dis1(&self) -> StallIDis1R { - StallIDis1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Disable Endpoint 2 IN Direction"] - #[inline(always)] - pub fn stall_i_dis2(&self) -> StallIDis2R { - StallIDis2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Disable Endpoint 3 IN Direction"] - #[inline(always)] - pub fn stall_i_dis3(&self) -> StallIDis3R { - StallIDis3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Disable Endpoint 4 IN Direction"] - #[inline(always)] - pub fn stall_i_dis4(&self) -> StallIDis4R { - StallIDis4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Disable Endpoint 5 IN Direction"] - #[inline(always)] - pub fn stall_i_dis5(&self) -> StallIDis5R { - StallIDis5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Disable Endpoint 6 IN Direction"] - #[inline(always)] - pub fn stall_i_dis6(&self) -> StallIDis6R { - StallIDis6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Disable Endpoint 7 IN Direction"] - #[inline(always)] - pub fn stall_i_dis7(&self) -> StallIDis7R { - StallIDis7R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Disable Endpoint 0 IN Direction"] - #[inline(always)] - pub fn stall_i_dis0(&mut self) -> StallIDis0W { - StallIDis0W::new(self, 0) - } - #[doc = "Bit 1 - Disable Endpoint 1 IN Direction"] - #[inline(always)] - pub fn stall_i_dis1(&mut self) -> StallIDis1W { - StallIDis1W::new(self, 1) - } - #[doc = "Bit 2 - Disable Endpoint 2 IN Direction"] - #[inline(always)] - pub fn stall_i_dis2(&mut self) -> StallIDis2W { - StallIDis2W::new(self, 2) - } - #[doc = "Bit 3 - Disable Endpoint 3 IN Direction"] - #[inline(always)] - pub fn stall_i_dis3(&mut self) -> StallIDis3W { - StallIDis3W::new(self, 3) - } - #[doc = "Bit 4 - Disable Endpoint 4 IN Direction"] - #[inline(always)] - pub fn stall_i_dis4(&mut self) -> StallIDis4W { - StallIDis4W::new(self, 4) - } - #[doc = "Bit 5 - Disable Endpoint 5 IN Direction"] - #[inline(always)] - pub fn stall_i_dis5(&mut self) -> StallIDis5W { - StallIDis5W::new(self, 5) - } - #[doc = "Bit 6 - Disable Endpoint 6 IN Direction"] - #[inline(always)] - pub fn stall_i_dis6(&mut self) -> StallIDis6W { - StallIDis6W::new(self, 6) - } - #[doc = "Bit 7 - Disable Endpoint 7 IN Direction"] - #[inline(always)] - pub fn stall_i_dis7(&mut self) -> StallIDis7W { - StallIDis7W::new(self, 7) - } -} -#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_il_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_il_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StallIlDisSpec; -impl crate::RegisterSpec for StallIlDisSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`stall_il_dis::R`](R) reader structure"] -impl crate::Readable for StallIlDisSpec {} -#[doc = "`write(|w| ..)` method takes [`stall_il_dis::W`](W) writer structure"] -impl crate::Writable for StallIlDisSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STALL_IL_DIS to value 0"] -impl crate::Resettable for StallIlDisSpec {} diff --git a/mcxa276-pac/src/usb0/stall_oh_dis.rs b/mcxa276-pac/src/usb0/stall_oh_dis.rs deleted file mode 100644 index 38b838823..000000000 --- a/mcxa276-pac/src/usb0/stall_oh_dis.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `STALL_OH_DIS` reader"] -pub type R = crate::R; -#[doc = "Register `STALL_OH_DIS` writer"] -pub type W = crate::W; -#[doc = "Disable Endpoint 8 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis8 { - #[doc = "0: Enable"] - EnEp8OutStall = 0, - #[doc = "1: Disable"] - DisEp8OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS8` reader - Disable Endpoint 8 OUT Direction"] -pub type StallODis8R = crate::BitReader; -impl StallODis8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis8 { - match self.bits { - false => StallODis8::EnEp8OutStall, - true => StallODis8::DisEp8OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep8_out_stall(&self) -> bool { - *self == StallODis8::EnEp8OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep8_out_stall(&self) -> bool { - *self == StallODis8::DisEp8OutStall - } -} -#[doc = "Field `STALL_O_DIS8` writer - Disable Endpoint 8 OUT Direction"] -pub type StallODis8W<'a, REG> = crate::BitWriter<'a, REG, StallODis8>; -impl<'a, REG> StallODis8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep8_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis8::EnEp8OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep8_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis8::DisEp8OutStall) - } -} -#[doc = "Disable Endpoint 9 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis9 { - #[doc = "0: Enable"] - EnEp9OutStall = 0, - #[doc = "1: Disable"] - DisEp9OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS9` reader - Disable Endpoint 9 OUT Direction"] -pub type StallODis9R = crate::BitReader; -impl StallODis9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis9 { - match self.bits { - false => StallODis9::EnEp9OutStall, - true => StallODis9::DisEp9OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep9_out_stall(&self) -> bool { - *self == StallODis9::EnEp9OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep9_out_stall(&self) -> bool { - *self == StallODis9::DisEp9OutStall - } -} -#[doc = "Field `STALL_O_DIS9` writer - Disable Endpoint 9 OUT Direction"] -pub type StallODis9W<'a, REG> = crate::BitWriter<'a, REG, StallODis9>; -impl<'a, REG> StallODis9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep9_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis9::EnEp9OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep9_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis9::DisEp9OutStall) - } -} -#[doc = "Disable Endpoint 10 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis10 { - #[doc = "0: Enable"] - EnEp10OutStall = 0, - #[doc = "1: Disable"] - DisEp10OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS10` reader - Disable Endpoint 10 OUT Direction"] -pub type StallODis10R = crate::BitReader; -impl StallODis10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis10 { - match self.bits { - false => StallODis10::EnEp10OutStall, - true => StallODis10::DisEp10OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep10_out_stall(&self) -> bool { - *self == StallODis10::EnEp10OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep10_out_stall(&self) -> bool { - *self == StallODis10::DisEp10OutStall - } -} -#[doc = "Field `STALL_O_DIS10` writer - Disable Endpoint 10 OUT Direction"] -pub type StallODis10W<'a, REG> = crate::BitWriter<'a, REG, StallODis10>; -impl<'a, REG> StallODis10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep10_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis10::EnEp10OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep10_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis10::DisEp10OutStall) - } -} -#[doc = "Disable Endpoint 11 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis11 { - #[doc = "0: Enable"] - EnEp11OutStall = 0, - #[doc = "1: Disable"] - DisEp11OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS11` reader - Disable Endpoint 11 OUT Direction"] -pub type StallODis11R = crate::BitReader; -impl StallODis11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis11 { - match self.bits { - false => StallODis11::EnEp11OutStall, - true => StallODis11::DisEp11OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep11_out_stall(&self) -> bool { - *self == StallODis11::EnEp11OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep11_out_stall(&self) -> bool { - *self == StallODis11::DisEp11OutStall - } -} -#[doc = "Field `STALL_O_DIS11` writer - Disable Endpoint 11 OUT Direction"] -pub type StallODis11W<'a, REG> = crate::BitWriter<'a, REG, StallODis11>; -impl<'a, REG> StallODis11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep11_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis11::EnEp11OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep11_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis11::DisEp11OutStall) - } -} -#[doc = "Disable endpoint 12 OUT direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis12 { - #[doc = "0: Enable"] - EnEp12OutStall = 0, - #[doc = "1: Disable"] - DisEp12OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS12` reader - Disable endpoint 12 OUT direction"] -pub type StallODis12R = crate::BitReader; -impl StallODis12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis12 { - match self.bits { - false => StallODis12::EnEp12OutStall, - true => StallODis12::DisEp12OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep12_out_stall(&self) -> bool { - *self == StallODis12::EnEp12OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep12_out_stall(&self) -> bool { - *self == StallODis12::DisEp12OutStall - } -} -#[doc = "Field `STALL_O_DIS12` writer - Disable endpoint 12 OUT direction"] -pub type StallODis12W<'a, REG> = crate::BitWriter<'a, REG, StallODis12>; -impl<'a, REG> StallODis12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep12_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis12::EnEp12OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep12_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis12::DisEp12OutStall) - } -} -#[doc = "Disable Endpoint 13 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis13 { - #[doc = "0: Enable"] - EnEp13OutStall = 0, - #[doc = "1: Disable"] - DisEp13OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS13` reader - Disable Endpoint 13 OUT Direction"] -pub type StallODis13R = crate::BitReader; -impl StallODis13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis13 { - match self.bits { - false => StallODis13::EnEp13OutStall, - true => StallODis13::DisEp13OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep13_out_stall(&self) -> bool { - *self == StallODis13::EnEp13OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep13_out_stall(&self) -> bool { - *self == StallODis13::DisEp13OutStall - } -} -#[doc = "Field `STALL_O_DIS13` writer - Disable Endpoint 13 OUT Direction"] -pub type StallODis13W<'a, REG> = crate::BitWriter<'a, REG, StallODis13>; -impl<'a, REG> StallODis13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep13_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis13::EnEp13OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep13_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis13::DisEp13OutStall) - } -} -#[doc = "Disable Endpoint 14 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis14 { - #[doc = "0: Enable"] - EnEp14OutStall = 0, - #[doc = "1: Disable"] - DisEp14OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS14` reader - Disable Endpoint 14 OUT Direction"] -pub type StallODis14R = crate::BitReader; -impl StallODis14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis14 { - match self.bits { - false => StallODis14::EnEp14OutStall, - true => StallODis14::DisEp14OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep14_out_stall(&self) -> bool { - *self == StallODis14::EnEp14OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep14_out_stall(&self) -> bool { - *self == StallODis14::DisEp14OutStall - } -} -#[doc = "Field `STALL_O_DIS14` writer - Disable Endpoint 14 OUT Direction"] -pub type StallODis14W<'a, REG> = crate::BitWriter<'a, REG, StallODis14>; -impl<'a, REG> StallODis14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep14_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis14::EnEp14OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep14_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis14::DisEp14OutStall) - } -} -#[doc = "Disable Endpoint 15 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis15 { - #[doc = "0: Enable"] - EnEp15OutStall = 0, - #[doc = "1: Disable"] - DisEp15OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS15` reader - Disable Endpoint 15 OUT Direction"] -pub type StallODis15R = crate::BitReader; -impl StallODis15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis15 { - match self.bits { - false => StallODis15::EnEp15OutStall, - true => StallODis15::DisEp15OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep15_out_stall(&self) -> bool { - *self == StallODis15::EnEp15OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep15_out_stall(&self) -> bool { - *self == StallODis15::DisEp15OutStall - } -} -#[doc = "Field `STALL_O_DIS15` writer - Disable Endpoint 15 OUT Direction"] -pub type StallODis15W<'a, REG> = crate::BitWriter<'a, REG, StallODis15>; -impl<'a, REG> StallODis15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep15_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis15::EnEp15OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep15_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis15::DisEp15OutStall) - } -} -impl R { - #[doc = "Bit 0 - Disable Endpoint 8 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis8(&self) -> StallODis8R { - StallODis8R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Disable Endpoint 9 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis9(&self) -> StallODis9R { - StallODis9R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Disable Endpoint 10 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis10(&self) -> StallODis10R { - StallODis10R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Disable Endpoint 11 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis11(&self) -> StallODis11R { - StallODis11R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Disable endpoint 12 OUT direction"] - #[inline(always)] - pub fn stall_o_dis12(&self) -> StallODis12R { - StallODis12R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Disable Endpoint 13 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis13(&self) -> StallODis13R { - StallODis13R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Disable Endpoint 14 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis14(&self) -> StallODis14R { - StallODis14R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Disable Endpoint 15 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis15(&self) -> StallODis15R { - StallODis15R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Disable Endpoint 8 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis8(&mut self) -> StallODis8W { - StallODis8W::new(self, 0) - } - #[doc = "Bit 1 - Disable Endpoint 9 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis9(&mut self) -> StallODis9W { - StallODis9W::new(self, 1) - } - #[doc = "Bit 2 - Disable Endpoint 10 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis10(&mut self) -> StallODis10W { - StallODis10W::new(self, 2) - } - #[doc = "Bit 3 - Disable Endpoint 11 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis11(&mut self) -> StallODis11W { - StallODis11W::new(self, 3) - } - #[doc = "Bit 4 - Disable endpoint 12 OUT direction"] - #[inline(always)] - pub fn stall_o_dis12(&mut self) -> StallODis12W { - StallODis12W::new(self, 4) - } - #[doc = "Bit 5 - Disable Endpoint 13 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis13(&mut self) -> StallODis13W { - StallODis13W::new(self, 5) - } - #[doc = "Bit 6 - Disable Endpoint 14 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis14(&mut self) -> StallODis14W { - StallODis14W::new(self, 6) - } - #[doc = "Bit 7 - Disable Endpoint 15 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis15(&mut self) -> StallODis15W { - StallODis15W::new(self, 7) - } -} -#[doc = "Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_oh_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_oh_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StallOhDisSpec; -impl crate::RegisterSpec for StallOhDisSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`stall_oh_dis::R`](R) reader structure"] -impl crate::Readable for StallOhDisSpec {} -#[doc = "`write(|w| ..)` method takes [`stall_oh_dis::W`](W) writer structure"] -impl crate::Writable for StallOhDisSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STALL_OH_DIS to value 0"] -impl crate::Resettable for StallOhDisSpec {} diff --git a/mcxa276-pac/src/usb0/stall_ol_dis.rs b/mcxa276-pac/src/usb0/stall_ol_dis.rs deleted file mode 100644 index 54f99b975..000000000 --- a/mcxa276-pac/src/usb0/stall_ol_dis.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `STALL_OL_DIS` reader"] -pub type R = crate::R; -#[doc = "Register `STALL_OL_DIS` writer"] -pub type W = crate::W; -#[doc = "Disable Endpoint 0 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis0 { - #[doc = "0: Enable"] - EnEp0OutStall = 0, - #[doc = "1: Disable"] - DisEp0OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS0` reader - Disable Endpoint 0 OUT Direction"] -pub type StallODis0R = crate::BitReader; -impl StallODis0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis0 { - match self.bits { - false => StallODis0::EnEp0OutStall, - true => StallODis0::DisEp0OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep0_out_stall(&self) -> bool { - *self == StallODis0::EnEp0OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep0_out_stall(&self) -> bool { - *self == StallODis0::DisEp0OutStall - } -} -#[doc = "Field `STALL_O_DIS0` writer - Disable Endpoint 0 OUT Direction"] -pub type StallODis0W<'a, REG> = crate::BitWriter<'a, REG, StallODis0>; -impl<'a, REG> StallODis0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep0_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis0::EnEp0OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep0_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis0::DisEp0OutStall) - } -} -#[doc = "Disable Endpoint 1 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis1 { - #[doc = "0: Enable"] - EnEp1OutStall = 0, - #[doc = "1: Disable"] - DisEp1OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS1` reader - Disable Endpoint 1 OUT Direction"] -pub type StallODis1R = crate::BitReader; -impl StallODis1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis1 { - match self.bits { - false => StallODis1::EnEp1OutStall, - true => StallODis1::DisEp1OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep1_out_stall(&self) -> bool { - *self == StallODis1::EnEp1OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep1_out_stall(&self) -> bool { - *self == StallODis1::DisEp1OutStall - } -} -#[doc = "Field `STALL_O_DIS1` writer - Disable Endpoint 1 OUT Direction"] -pub type StallODis1W<'a, REG> = crate::BitWriter<'a, REG, StallODis1>; -impl<'a, REG> StallODis1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep1_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis1::EnEp1OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep1_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis1::DisEp1OutStall) - } -} -#[doc = "Disable Endpoint 2 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis2 { - #[doc = "0: Enable"] - EnEp2OutStall = 0, - #[doc = "1: Disable"] - DisEp2OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS2` reader - Disable Endpoint 2 OUT Direction"] -pub type StallODis2R = crate::BitReader; -impl StallODis2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis2 { - match self.bits { - false => StallODis2::EnEp2OutStall, - true => StallODis2::DisEp2OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep2_out_stall(&self) -> bool { - *self == StallODis2::EnEp2OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep2_out_stall(&self) -> bool { - *self == StallODis2::DisEp2OutStall - } -} -#[doc = "Field `STALL_O_DIS2` writer - Disable Endpoint 2 OUT Direction"] -pub type StallODis2W<'a, REG> = crate::BitWriter<'a, REG, StallODis2>; -impl<'a, REG> StallODis2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep2_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis2::EnEp2OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep2_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis2::DisEp2OutStall) - } -} -#[doc = "Disable Endpoint 3 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis3 { - #[doc = "0: Enable"] - EnEp3OutStall = 0, - #[doc = "1: Disable"] - DisEp3OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS3` reader - Disable Endpoint 3 OUT Direction"] -pub type StallODis3R = crate::BitReader; -impl StallODis3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis3 { - match self.bits { - false => StallODis3::EnEp3OutStall, - true => StallODis3::DisEp3OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep3_out_stall(&self) -> bool { - *self == StallODis3::EnEp3OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep3_out_stall(&self) -> bool { - *self == StallODis3::DisEp3OutStall - } -} -#[doc = "Field `STALL_O_DIS3` writer - Disable Endpoint 3 OUT Direction"] -pub type StallODis3W<'a, REG> = crate::BitWriter<'a, REG, StallODis3>; -impl<'a, REG> StallODis3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep3_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis3::EnEp3OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep3_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis3::DisEp3OutStall) - } -} -#[doc = "Disable Endpoint 4 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis4 { - #[doc = "0: Enable"] - EnEp4OutStall = 0, - #[doc = "1: Disable"] - DisEp4OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS4` reader - Disable Endpoint 4 OUT Direction"] -pub type StallODis4R = crate::BitReader; -impl StallODis4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis4 { - match self.bits { - false => StallODis4::EnEp4OutStall, - true => StallODis4::DisEp4OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep4_out_stall(&self) -> bool { - *self == StallODis4::EnEp4OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep4_out_stall(&self) -> bool { - *self == StallODis4::DisEp4OutStall - } -} -#[doc = "Field `STALL_O_DIS4` writer - Disable Endpoint 4 OUT Direction"] -pub type StallODis4W<'a, REG> = crate::BitWriter<'a, REG, StallODis4>; -impl<'a, REG> StallODis4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep4_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis4::EnEp4OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep4_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis4::DisEp4OutStall) - } -} -#[doc = "Disable Endpoint 5 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis5 { - #[doc = "0: Enable"] - EnEp5OutStall = 0, - #[doc = "1: Disable"] - DisEp5OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS5` reader - Disable Endpoint 5 OUT Direction"] -pub type StallODis5R = crate::BitReader; -impl StallODis5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis5 { - match self.bits { - false => StallODis5::EnEp5OutStall, - true => StallODis5::DisEp5OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep5_out_stall(&self) -> bool { - *self == StallODis5::EnEp5OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep5_out_stall(&self) -> bool { - *self == StallODis5::DisEp5OutStall - } -} -#[doc = "Field `STALL_O_DIS5` writer - Disable Endpoint 5 OUT Direction"] -pub type StallODis5W<'a, REG> = crate::BitWriter<'a, REG, StallODis5>; -impl<'a, REG> StallODis5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep5_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis5::EnEp5OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep5_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis5::DisEp5OutStall) - } -} -#[doc = "Disable Endpoint 6 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis6 { - #[doc = "0: Enable"] - EnEp6OutStall = 0, - #[doc = "1: Disable"] - DisEp6OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS6` reader - Disable Endpoint 6 OUT Direction"] -pub type StallODis6R = crate::BitReader; -impl StallODis6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis6 { - match self.bits { - false => StallODis6::EnEp6OutStall, - true => StallODis6::DisEp6OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep6_out_stall(&self) -> bool { - *self == StallODis6::EnEp6OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep6_out_stall(&self) -> bool { - *self == StallODis6::DisEp6OutStall - } -} -#[doc = "Field `STALL_O_DIS6` writer - Disable Endpoint 6 OUT Direction"] -pub type StallODis6W<'a, REG> = crate::BitWriter<'a, REG, StallODis6>; -impl<'a, REG> StallODis6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep6_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis6::EnEp6OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep6_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis6::DisEp6OutStall) - } -} -#[doc = "Disable Endpoint 7 OUT Direction\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum StallODis7 { - #[doc = "0: Enable"] - EnEp7OutStall = 0, - #[doc = "1: Disable"] - DisEp7OutStall = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: StallODis7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `STALL_O_DIS7` reader - Disable Endpoint 7 OUT Direction"] -pub type StallODis7R = crate::BitReader; -impl StallODis7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> StallODis7 { - match self.bits { - false => StallODis7::EnEp7OutStall, - true => StallODis7::DisEp7OutStall, - } - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_ep7_out_stall(&self) -> bool { - *self == StallODis7::EnEp7OutStall - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_ep7_out_stall(&self) -> bool { - *self == StallODis7::DisEp7OutStall - } -} -#[doc = "Field `STALL_O_DIS7` writer - Disable Endpoint 7 OUT Direction"] -pub type StallODis7W<'a, REG> = crate::BitWriter<'a, REG, StallODis7>; -impl<'a, REG> StallODis7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Enable"] - #[inline(always)] - pub fn en_ep7_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis7::EnEp7OutStall) - } - #[doc = "Disable"] - #[inline(always)] - pub fn dis_ep7_out_stall(self) -> &'a mut crate::W { - self.variant(StallODis7::DisEp7OutStall) - } -} -impl R { - #[doc = "Bit 0 - Disable Endpoint 0 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis0(&self) -> StallODis0R { - StallODis0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Disable Endpoint 1 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis1(&self) -> StallODis1R { - StallODis1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Disable Endpoint 2 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis2(&self) -> StallODis2R { - StallODis2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Disable Endpoint 3 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis3(&self) -> StallODis3R { - StallODis3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Disable Endpoint 4 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis4(&self) -> StallODis4R { - StallODis4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Disable Endpoint 5 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis5(&self) -> StallODis5R { - StallODis5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Disable Endpoint 6 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis6(&self) -> StallODis6R { - StallODis6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Disable Endpoint 7 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis7(&self) -> StallODis7R { - StallODis7R::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Disable Endpoint 0 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis0(&mut self) -> StallODis0W { - StallODis0W::new(self, 0) - } - #[doc = "Bit 1 - Disable Endpoint 1 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis1(&mut self) -> StallODis1W { - StallODis1W::new(self, 1) - } - #[doc = "Bit 2 - Disable Endpoint 2 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis2(&mut self) -> StallODis2W { - StallODis2W::new(self, 2) - } - #[doc = "Bit 3 - Disable Endpoint 3 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis3(&mut self) -> StallODis3W { - StallODis3W::new(self, 3) - } - #[doc = "Bit 4 - Disable Endpoint 4 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis4(&mut self) -> StallODis4W { - StallODis4W::new(self, 4) - } - #[doc = "Bit 5 - Disable Endpoint 5 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis5(&mut self) -> StallODis5W { - StallODis5W::new(self, 5) - } - #[doc = "Bit 6 - Disable Endpoint 6 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis6(&mut self) -> StallODis6W { - StallODis6W::new(self, 6) - } - #[doc = "Bit 7 - Disable Endpoint 7 OUT Direction"] - #[inline(always)] - pub fn stall_o_dis7(&mut self) -> StallODis7W { - StallODis7W::new(self, 7) - } -} -#[doc = "Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_ol_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_ol_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StallOlDisSpec; -impl crate::RegisterSpec for StallOlDisSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`stall_ol_dis::R`](R) reader structure"] -impl crate::Readable for StallOlDisSpec {} -#[doc = "`write(|w| ..)` method takes [`stall_ol_dis::W`](W) writer structure"] -impl crate::Writable for StallOlDisSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets STALL_OL_DIS to value 0"] -impl crate::Resettable for StallOlDisSpec {} diff --git a/mcxa276-pac/src/usb0/stat.rs b/mcxa276-pac/src/usb0/stat.rs deleted file mode 100644 index ff7ed6544..000000000 --- a/mcxa276-pac/src/usb0/stat.rs +++ /dev/null @@ -1,102 +0,0 @@ -#[doc = "Register `STAT` reader"] -pub type R = crate::R; -#[doc = "Odd Bank\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Odd { - #[doc = "0: Not in the odd bank"] - NotInOddBank = 0, - #[doc = "1: In the odd bank"] - OddBank = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Odd) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ODD` reader - Odd Bank"] -pub type OddR = crate::BitReader; -impl OddR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Odd { - match self.bits { - false => Odd::NotInOddBank, - true => Odd::OddBank, - } - } - #[doc = "Not in the odd bank"] - #[inline(always)] - pub fn is_not_in_odd_bank(&self) -> bool { - *self == Odd::NotInOddBank - } - #[doc = "In the odd bank"] - #[inline(always)] - pub fn is_odd_bank(&self) -> bool { - *self == Odd::OddBank - } -} -#[doc = "Transmit Indicator\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Tx { - #[doc = "0: Receive"] - RxTransaction = 0, - #[doc = "1: Transmit"] - TxTransaction = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Tx) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `TX` reader - Transmit Indicator"] -pub type TxR = crate::BitReader; -impl TxR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Tx { - match self.bits { - false => Tx::RxTransaction, - true => Tx::TxTransaction, - } - } - #[doc = "Receive"] - #[inline(always)] - pub fn is_rx_transaction(&self) -> bool { - *self == Tx::RxTransaction - } - #[doc = "Transmit"] - #[inline(always)] - pub fn is_tx_transaction(&self) -> bool { - *self == Tx::TxTransaction - } -} -#[doc = "Field `ENDP` reader - Endpoint address"] -pub type EndpR = crate::FieldReader; -impl R { - #[doc = "Bit 2 - Odd Bank"] - #[inline(always)] - pub fn odd(&self) -> OddR { - OddR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Transmit Indicator"] - #[inline(always)] - pub fn tx(&self) -> TxR { - TxR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:7 - Endpoint address"] - #[inline(always)] - pub fn endp(&self) -> EndpR { - EndpR::new((self.bits >> 4) & 0x0f) - } -} -#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StatSpec; -impl crate::RegisterSpec for StatSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`stat::R`](R) reader structure"] -impl crate::Readable for StatSpec {} -#[doc = "`reset()` method sets STAT to value 0"] -impl crate::Resettable for StatSpec {} diff --git a/mcxa276-pac/src/usb0/token.rs b/mcxa276-pac/src/usb0/token.rs deleted file mode 100644 index cae7ddecc..000000000 --- a/mcxa276-pac/src/usb0/token.rs +++ /dev/null @@ -1,118 +0,0 @@ -#[doc = "Register `TOKEN` reader"] -pub type R = crate::R; -#[doc = "Register `TOKEN` writer"] -pub type W = crate::W; -#[doc = "Field `TOKENENDPT` reader - Token Endpoint Address"] -pub type TokenendptR = crate::FieldReader; -#[doc = "Field `TOKENENDPT` writer - Token Endpoint Address"] -pub type TokenendptW<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Token Type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Tokenpid { - #[doc = "1: OUT token. USBFS performs an OUT (TX) transaction."] - EnOutToken = 1, - #[doc = "9: IN token. USBFS performs an IN (RX) transaction."] - EnInToken = 9, - #[doc = "13: SETUP token. USBFS performs a SETUP (TX) transaction"] - EnSetupToken = 13, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Tokenpid) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Tokenpid { - type Ux = u8; -} -impl crate::IsEnum for Tokenpid {} -#[doc = "Field `TOKENPID` reader - Token Type"] -pub type TokenpidR = crate::FieldReader; -impl TokenpidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 1 => Some(Tokenpid::EnOutToken), - 9 => Some(Tokenpid::EnInToken), - 13 => Some(Tokenpid::EnSetupToken), - _ => None, - } - } - #[doc = "OUT token. USBFS performs an OUT (TX) transaction."] - #[inline(always)] - pub fn is_en_out_token(&self) -> bool { - *self == Tokenpid::EnOutToken - } - #[doc = "IN token. USBFS performs an IN (RX) transaction."] - #[inline(always)] - pub fn is_en_in_token(&self) -> bool { - *self == Tokenpid::EnInToken - } - #[doc = "SETUP token. USBFS performs a SETUP (TX) transaction"] - #[inline(always)] - pub fn is_en_setup_token(&self) -> bool { - *self == Tokenpid::EnSetupToken - } -} -#[doc = "Field `TOKENPID` writer - Token Type"] -pub type TokenpidW<'a, REG> = crate::FieldWriter<'a, REG, 4, Tokenpid>; -impl<'a, REG> TokenpidW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "OUT token. USBFS performs an OUT (TX) transaction."] - #[inline(always)] - pub fn en_out_token(self) -> &'a mut crate::W { - self.variant(Tokenpid::EnOutToken) - } - #[doc = "IN token. USBFS performs an IN (RX) transaction."] - #[inline(always)] - pub fn en_in_token(self) -> &'a mut crate::W { - self.variant(Tokenpid::EnInToken) - } - #[doc = "SETUP token. USBFS performs a SETUP (TX) transaction"] - #[inline(always)] - pub fn en_setup_token(self) -> &'a mut crate::W { - self.variant(Tokenpid::EnSetupToken) - } -} -impl R { - #[doc = "Bits 0:3 - Token Endpoint Address"] - #[inline(always)] - pub fn tokenendpt(&self) -> TokenendptR { - TokenendptR::new(self.bits & 0x0f) - } - #[doc = "Bits 4:7 - Token Type"] - #[inline(always)] - pub fn tokenpid(&self) -> TokenpidR { - TokenpidR::new((self.bits >> 4) & 0x0f) - } -} -impl W { - #[doc = "Bits 0:3 - Token Endpoint Address"] - #[inline(always)] - pub fn tokenendpt(&mut self) -> TokenendptW { - TokenendptW::new(self, 0) - } - #[doc = "Bits 4:7 - Token Type"] - #[inline(always)] - pub fn tokenpid(&mut self) -> TokenpidW { - TokenpidW::new(self, 4) - } -} -#[doc = "Token\n\nYou can [`read`](crate::Reg::read) this register and get [`token::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`token::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TokenSpec; -impl crate::RegisterSpec for TokenSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`token::R`](R) reader structure"] -impl crate::Readable for TokenSpec {} -#[doc = "`write(|w| ..)` method takes [`token::W`](W) writer structure"] -impl crate::Writable for TokenSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TOKEN to value 0"] -impl crate::Resettable for TokenSpec {} diff --git a/mcxa276-pac/src/usb0/usbctrl.rs b/mcxa276-pac/src/usb0/usbctrl.rs deleted file mode 100644 index a8fcc3f2c..000000000 --- a/mcxa276-pac/src/usb0/usbctrl.rs +++ /dev/null @@ -1,401 +0,0 @@ -#[doc = "Register `USBCTRL` reader"] -pub type R = crate::R; -#[doc = "Register `USBCTRL` writer"] -pub type W = crate::W; -#[doc = "DP and DM Lane Reversal Control\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DpdmLaneReverse { - #[doc = "0: Standard USB DP and DM package pin assignment"] - DpDmStandard = 0, - #[doc = "1: Reverse roles of USB DP and DM package pins"] - DpDmReversed = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DpdmLaneReverse) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DPDM_LANE_REVERSE` reader - DP and DM Lane Reversal Control"] -pub type DpdmLaneReverseR = crate::BitReader; -impl DpdmLaneReverseR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DpdmLaneReverse { - match self.bits { - false => DpdmLaneReverse::DpDmStandard, - true => DpdmLaneReverse::DpDmReversed, - } - } - #[doc = "Standard USB DP and DM package pin assignment"] - #[inline(always)] - pub fn is_dp_dm_standard(&self) -> bool { - *self == DpdmLaneReverse::DpDmStandard - } - #[doc = "Reverse roles of USB DP and DM package pins"] - #[inline(always)] - pub fn is_dp_dm_reversed(&self) -> bool { - *self == DpdmLaneReverse::DpDmReversed - } -} -#[doc = "Field `DPDM_LANE_REVERSE` writer - DP and DM Lane Reversal Control"] -pub type DpdmLaneReverseW<'a, REG> = crate::BitWriter<'a, REG, DpdmLaneReverse>; -impl<'a, REG> DpdmLaneReverseW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Standard USB DP and DM package pin assignment"] - #[inline(always)] - pub fn dp_dm_standard(self) -> &'a mut crate::W { - self.variant(DpdmLaneReverse::DpDmStandard) - } - #[doc = "Reverse roles of USB DP and DM package pins"] - #[inline(always)] - pub fn dp_dm_reversed(self) -> &'a mut crate::W { - self.variant(DpdmLaneReverse::DpDmReversed) - } -} -#[doc = "Host-Mode-Only Low-Speed Device EOP Signaling\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum HostLsEop { - #[doc = "0: Full-speed device or a low-speed device through a hub"] - HostFsResumeEop = 0, - #[doc = "1: Directly-connected low-speed device"] - HostLsResumeEop = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: HostLsEop) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `HOST_LS_EOP` reader - Host-Mode-Only Low-Speed Device EOP Signaling"] -pub type HostLsEopR = crate::BitReader; -impl HostLsEopR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> HostLsEop { - match self.bits { - false => HostLsEop::HostFsResumeEop, - true => HostLsEop::HostLsResumeEop, - } - } - #[doc = "Full-speed device or a low-speed device through a hub"] - #[inline(always)] - pub fn is_host_fs_resume_eop(&self) -> bool { - *self == HostLsEop::HostFsResumeEop - } - #[doc = "Directly-connected low-speed device"] - #[inline(always)] - pub fn is_host_ls_resume_eop(&self) -> bool { - *self == HostLsEop::HostLsResumeEop - } -} -#[doc = "Field `HOST_LS_EOP` writer - Host-Mode-Only Low-Speed Device EOP Signaling"] -pub type HostLsEopW<'a, REG> = crate::BitWriter<'a, REG, HostLsEop>; -impl<'a, REG> HostLsEopW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Full-speed device or a low-speed device through a hub"] - #[inline(always)] - pub fn host_fs_resume_eop(self) -> &'a mut crate::W { - self.variant(HostLsEop::HostFsResumeEop) - } - #[doc = "Directly-connected low-speed device"] - #[inline(always)] - pub fn host_ls_resume_eop(self) -> &'a mut crate::W { - self.variant(HostLsEop::HostLsResumeEop) - } -} -#[doc = "UART Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Uartsel { - #[doc = "0: USB DP and DM external package pins are used for USB signaling."] - UsbMode = 0, - #[doc = "1: USB DP and DM external package pins are used for UART signaling."] - UartMode = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Uartsel) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UARTSEL` reader - UART Select"] -pub type UartselR = crate::BitReader; -impl UartselR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Uartsel { - match self.bits { - false => Uartsel::UsbMode, - true => Uartsel::UartMode, - } - } - #[doc = "USB DP and DM external package pins are used for USB signaling."] - #[inline(always)] - pub fn is_usb_mode(&self) -> bool { - *self == Uartsel::UsbMode - } - #[doc = "USB DP and DM external package pins are used for UART signaling."] - #[inline(always)] - pub fn is_uart_mode(&self) -> bool { - *self == Uartsel::UartMode - } -} -#[doc = "Field `UARTSEL` writer - UART Select"] -pub type UartselW<'a, REG> = crate::BitWriter<'a, REG, Uartsel>; -impl<'a, REG> UartselW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "USB DP and DM external package pins are used for USB signaling."] - #[inline(always)] - pub fn usb_mode(self) -> &'a mut crate::W { - self.variant(Uartsel::UsbMode) - } - #[doc = "USB DP and DM external package pins are used for UART signaling."] - #[inline(always)] - pub fn uart_mode(self) -> &'a mut crate::W { - self.variant(Uartsel::UartMode) - } -} -#[doc = "UART Signal Channel Select\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Uartchls { - #[doc = "0: USB DP and DM signals are used as UART TX/RX."] - UartDpTx = 0, - #[doc = "1: USB DP and DM signals are used as UART RX/TX."] - UartDmTx = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Uartchls) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UARTCHLS` reader - UART Signal Channel Select"] -pub type UartchlsR = crate::BitReader; -impl UartchlsR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Uartchls { - match self.bits { - false => Uartchls::UartDpTx, - true => Uartchls::UartDmTx, - } - } - #[doc = "USB DP and DM signals are used as UART TX/RX."] - #[inline(always)] - pub fn is_uart_dp_tx(&self) -> bool { - *self == Uartchls::UartDpTx - } - #[doc = "USB DP and DM signals are used as UART RX/TX."] - #[inline(always)] - pub fn is_uart_dm_tx(&self) -> bool { - *self == Uartchls::UartDmTx - } -} -#[doc = "Field `UARTCHLS` writer - UART Signal Channel Select"] -pub type UartchlsW<'a, REG> = crate::BitWriter<'a, REG, Uartchls>; -impl<'a, REG> UartchlsW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "USB DP and DM signals are used as UART TX/RX."] - #[inline(always)] - pub fn uart_dp_tx(self) -> &'a mut crate::W { - self.variant(Uartchls::UartDpTx) - } - #[doc = "USB DP and DM signals are used as UART RX/TX."] - #[inline(always)] - pub fn uart_dm_tx(self) -> &'a mut crate::W { - self.variant(Uartchls::UartDmTx) - } -} -#[doc = "Pulldown Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Pde { - #[doc = "0: Disable on D+ and D-"] - DisPulldowns = 0, - #[doc = "1: Enable on D+ and D-"] - EnPulldowns = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Pde) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PDE` reader - Pulldown Enable"] -pub type PdeR = crate::BitReader; -impl PdeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Pde { - match self.bits { - false => Pde::DisPulldowns, - true => Pde::EnPulldowns, - } - } - #[doc = "Disable on D+ and D-"] - #[inline(always)] - pub fn is_dis_pulldowns(&self) -> bool { - *self == Pde::DisPulldowns - } - #[doc = "Enable on D+ and D-"] - #[inline(always)] - pub fn is_en_pulldowns(&self) -> bool { - *self == Pde::EnPulldowns - } -} -#[doc = "Field `PDE` writer - Pulldown Enable"] -pub type PdeW<'a, REG> = crate::BitWriter<'a, REG, Pde>; -impl<'a, REG> PdeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable on D+ and D-"] - #[inline(always)] - pub fn dis_pulldowns(self) -> &'a mut crate::W { - self.variant(Pde::DisPulldowns) - } - #[doc = "Enable on D+ and D-"] - #[inline(always)] - pub fn en_pulldowns(self) -> &'a mut crate::W { - self.variant(Pde::EnPulldowns) - } -} -#[doc = "Suspend\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Susp { - #[doc = "0: Not in Suspend state"] - XcvrNotSuspend = 0, - #[doc = "1: In Suspend state"] - XcvrSuspend = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Susp) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SUSP` reader - Suspend"] -pub type SuspR = crate::BitReader; -impl SuspR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Susp { - match self.bits { - false => Susp::XcvrNotSuspend, - true => Susp::XcvrSuspend, - } - } - #[doc = "Not in Suspend state"] - #[inline(always)] - pub fn is_xcvr_not_suspend(&self) -> bool { - *self == Susp::XcvrNotSuspend - } - #[doc = "In Suspend state"] - #[inline(always)] - pub fn is_xcvr_suspend(&self) -> bool { - *self == Susp::XcvrSuspend - } -} -#[doc = "Field `SUSP` writer - Suspend"] -pub type SuspW<'a, REG> = crate::BitWriter<'a, REG, Susp>; -impl<'a, REG> SuspW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not in Suspend state"] - #[inline(always)] - pub fn xcvr_not_suspend(self) -> &'a mut crate::W { - self.variant(Susp::XcvrNotSuspend) - } - #[doc = "In Suspend state"] - #[inline(always)] - pub fn xcvr_suspend(self) -> &'a mut crate::W { - self.variant(Susp::XcvrSuspend) - } -} -impl R { - #[doc = "Bit 2 - DP and DM Lane Reversal Control"] - #[inline(always)] - pub fn dpdm_lane_reverse(&self) -> DpdmLaneReverseR { - DpdmLaneReverseR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Host-Mode-Only Low-Speed Device EOP Signaling"] - #[inline(always)] - pub fn host_ls_eop(&self) -> HostLsEopR { - HostLsEopR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - UART Select"] - #[inline(always)] - pub fn uartsel(&self) -> UartselR { - UartselR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - UART Signal Channel Select"] - #[inline(always)] - pub fn uartchls(&self) -> UartchlsR { - UartchlsR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Pulldown Enable"] - #[inline(always)] - pub fn pde(&self) -> PdeR { - PdeR::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Suspend"] - #[inline(always)] - pub fn susp(&self) -> SuspR { - SuspR::new(((self.bits >> 7) & 1) != 0) - } -} -impl W { - #[doc = "Bit 2 - DP and DM Lane Reversal Control"] - #[inline(always)] - pub fn dpdm_lane_reverse(&mut self) -> DpdmLaneReverseW { - DpdmLaneReverseW::new(self, 2) - } - #[doc = "Bit 3 - Host-Mode-Only Low-Speed Device EOP Signaling"] - #[inline(always)] - pub fn host_ls_eop(&mut self) -> HostLsEopW { - HostLsEopW::new(self, 3) - } - #[doc = "Bit 4 - UART Select"] - #[inline(always)] - pub fn uartsel(&mut self) -> UartselW { - UartselW::new(self, 4) - } - #[doc = "Bit 5 - UART Signal Channel Select"] - #[inline(always)] - pub fn uartchls(&mut self) -> UartchlsW { - UartchlsW::new(self, 5) - } - #[doc = "Bit 6 - Pulldown Enable"] - #[inline(always)] - pub fn pde(&mut self) -> PdeW { - PdeW::new(self, 6) - } - #[doc = "Bit 7 - Suspend"] - #[inline(always)] - pub fn susp(&mut self) -> SuspW { - SuspW::new(self, 7) - } -} -#[doc = "USB Control\n\nYou can [`read`](crate::Reg::read) this register and get [`usbctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UsbctrlSpec; -impl crate::RegisterSpec for UsbctrlSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`usbctrl::R`](R) reader structure"] -impl crate::Readable for UsbctrlSpec {} -#[doc = "`write(|w| ..)` method takes [`usbctrl::W`](W) writer structure"] -impl crate::Writable for UsbctrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets USBCTRL to value 0xc0"] -impl crate::Resettable for UsbctrlSpec { - const RESET_VALUE: u8 = 0xc0; -} diff --git a/mcxa276-pac/src/usb0/usbfrmadjust.rs b/mcxa276-pac/src/usb0/usbfrmadjust.rs deleted file mode 100644 index 5cda0f0be..000000000 --- a/mcxa276-pac/src/usb0/usbfrmadjust.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `USBFRMADJUST` reader"] -pub type R = crate::R; -#[doc = "Register `USBFRMADJUST` writer"] -pub type W = crate::W; -#[doc = "Field `ADJ` reader - Frame Adjustment"] -pub type AdjR = crate::FieldReader; -#[doc = "Field `ADJ` writer - Frame Adjustment"] -pub type AdjW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - Frame Adjustment"] - #[inline(always)] - pub fn adj(&self) -> AdjR { - AdjR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:7 - Frame Adjustment"] - #[inline(always)] - pub fn adj(&mut self) -> AdjW { - AdjW::new(self, 0) - } -} -#[doc = "Frame Adjust\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfrmadjust::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfrmadjust::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UsbfrmadjustSpec; -impl crate::RegisterSpec for UsbfrmadjustSpec { - type Ux = u8; -} -#[doc = "`read()` method returns [`usbfrmadjust::R`](R) reader structure"] -impl crate::Readable for UsbfrmadjustSpec {} -#[doc = "`write(|w| ..)` method takes [`usbfrmadjust::W`](W) writer structure"] -impl crate::Writable for UsbfrmadjustSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets USBFRMADJUST to value 0"] -impl crate::Resettable for UsbfrmadjustSpec {} diff --git a/mcxa276-pac/src/usb0/usbtrc0.rs b/mcxa276-pac/src/usb0/usbtrc0.rs deleted file mode 100644 index c165b8013..000000000 --- a/mcxa276-pac/src/usb0/usbtrc0.rs +++ /dev/null @@ -1,298 +0,0 @@ -#[doc = "Register `USBTRC0` reader"] -pub type R = crate::R; -#[doc = "Register `USBTRC0` writer"] -pub type W = crate::W; -#[doc = "USB Asynchronous Interrupt\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum UsbResumeInt { - #[doc = "0: Not generated"] - NoAsyncInt = 0, - #[doc = "1: Generated because of the USB asynchronous interrupt"] - SyncIntGenerated = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: UsbResumeInt) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USB_RESUME_INT` reader - USB Asynchronous Interrupt"] -pub type UsbResumeIntR = crate::BitReader; -impl UsbResumeIntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> UsbResumeInt { - match self.bits { - false => UsbResumeInt::NoAsyncInt, - true => UsbResumeInt::SyncIntGenerated, - } - } - #[doc = "Not generated"] - #[inline(always)] - pub fn is_no_async_int(&self) -> bool { - *self == UsbResumeInt::NoAsyncInt - } - #[doc = "Generated because of the USB asynchronous interrupt"] - #[inline(always)] - pub fn is_sync_int_generated(&self) -> bool { - *self == UsbResumeInt::SyncIntGenerated - } -} -#[doc = "Synchronous USB Interrupt Detect\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum SyncDet { - #[doc = "0: Not detected"] - NoSyncInt = 0, - #[doc = "1: Detected"] - SyncIntDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: SyncDet) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `SYNC_DET` reader - Synchronous USB Interrupt Detect"] -pub type SyncDetR = crate::BitReader; -impl SyncDetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> SyncDet { - match self.bits { - false => SyncDet::NoSyncInt, - true => SyncDet::SyncIntDetected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_no_sync_int(&self) -> bool { - *self == SyncDet::NoSyncInt - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_sync_int_detected(&self) -> bool { - *self == SyncDet::SyncIntDetected - } -} -#[doc = "Field `USB_CLK_RECOVERY_INT` reader - Combined USB Clock Recovery interrupt status"] -pub type UsbClkRecoveryIntR = crate::BitReader; -#[doc = "VREGIN Rising Edge Interrupt Detect\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum VredgDet { - #[doc = "0: Not detected"] - NoVregReInt = 0, - #[doc = "1: Detected"] - VregReIntDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: VredgDet) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VREDG_DET` reader - VREGIN Rising Edge Interrupt Detect"] -pub type VredgDetR = crate::BitReader; -impl VredgDetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> VredgDet { - match self.bits { - false => VredgDet::NoVregReInt, - true => VredgDet::VregReIntDetected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_no_vreg_re_int(&self) -> bool { - *self == VredgDet::NoVregReInt - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_vreg_re_int_detected(&self) -> bool { - *self == VredgDet::VregReIntDetected - } -} -#[doc = "VREGIN Falling Edge Interrupt Detect\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum VfedgDet { - #[doc = "0: Not detected"] - NoVregFeInt = 0, - #[doc = "1: Detected"] - VregFeIntDetected = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: VfedgDet) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VFEDG_DET` reader - VREGIN Falling Edge Interrupt Detect"] -pub type VfedgDetR = crate::BitReader; -impl VfedgDetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> VfedgDet { - match self.bits { - false => VfedgDet::NoVregFeInt, - true => VfedgDet::VregFeIntDetected, - } - } - #[doc = "Not detected"] - #[inline(always)] - pub fn is_no_vreg_fe_int(&self) -> bool { - *self == VfedgDet::NoVregFeInt - } - #[doc = "Detected"] - #[inline(always)] - pub fn is_vreg_fe_int_detected(&self) -> bool { - *self == VfedgDet::VregFeIntDetected - } -} -#[doc = "Asynchronous Resume Interrupt Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usbresmen { - #[doc = "0: Disable"] - DisAsyncWakeup = 0, - #[doc = "1: Enable"] - EnAsyncWakeup = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usbresmen) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USBRESMEN` reader - Asynchronous Resume Interrupt Enable"] -pub type UsbresmenR = crate::BitReader; -impl UsbresmenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Usbresmen { - match self.bits { - false => Usbresmen::DisAsyncWakeup, - true => Usbresmen::EnAsyncWakeup, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_dis_async_wakeup(&self) -> bool { - *self == Usbresmen::DisAsyncWakeup - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_en_async_wakeup(&self) -> bool { - *self == Usbresmen::EnAsyncWakeup - } -} -#[doc = "Field `USBRESMEN` writer - Asynchronous Resume Interrupt Enable"] -pub type UsbresmenW<'a, REG> = crate::BitWriter<'a, REG, Usbresmen>; -impl<'a, REG> UsbresmenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn dis_async_wakeup(self) -> &'a mut crate::W { - self.variant(Usbresmen::DisAsyncWakeup) - } - #[doc = "Enable"] - #[inline(always)] - pub fn en_async_wakeup(self) -> &'a mut crate::W { - self.variant(Usbresmen::EnAsyncWakeup) - } -} -#[doc = "Field `VREGIN_STS` reader - VREGIN Status"] -pub type VreginStsR = crate::BitReader; -#[doc = "USB Reset\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Usbreset { - #[doc = "0: Normal USBFS operation"] - NormalOperation = 0, - #[doc = "1: Returns USBFS to its reset state"] - ForceHardReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Usbreset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `USBRESET` writer - USB Reset"] -pub type UsbresetW<'a, REG> = crate::BitWriter<'a, REG, Usbreset>; -impl<'a, REG> UsbresetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Normal USBFS operation"] - #[inline(always)] - pub fn normal_operation(self) -> &'a mut crate::W { - self.variant(Usbreset::NormalOperation) - } - #[doc = "Returns USBFS to its reset state"] - #[inline(always)] - pub fn force_hard_reset(self) -> &'a mut crate::W { - self.variant(Usbreset::ForceHardReset) - } -} -impl R { - #[doc = "Bit 0 - USB Asynchronous Interrupt"] - #[inline(always)] - pub fn usb_resume_int(&self) -> UsbResumeIntR { - UsbResumeIntR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Synchronous USB Interrupt Detect"] - #[inline(always)] - pub fn sync_det(&self) -> SyncDetR { - SyncDetR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Combined USB Clock Recovery interrupt status"] - #[inline(always)] - pub fn usb_clk_recovery_int(&self) -> UsbClkRecoveryIntR { - UsbClkRecoveryIntR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - VREGIN Rising Edge Interrupt Detect"] - #[inline(always)] - pub fn vredg_det(&self) -> VredgDetR { - VredgDetR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - VREGIN Falling Edge Interrupt Detect"] - #[inline(always)] - pub fn vfedg_det(&self) -> VfedgDetR { - VfedgDetR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Asynchronous Resume Interrupt Enable"] - #[inline(always)] - pub fn usbresmen(&self) -> UsbresmenR { - UsbresmenR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - VREGIN Status"] - #[inline(always)] - pub fn vregin_sts(&self) -> VreginStsR { - VreginStsR::new(((self.bits >> 6) & 1) != 0) - } -} -impl W { - #[doc = "Bit 5 - Asynchronous Resume Interrupt Enable"] - #[inline(always)] - pub fn usbresmen(&mut self) -> UsbresmenW { - UsbresmenW::new(self, 5) - } - #[doc = "Bit 7 - USB Reset"] - #[inline(always)] - pub fn usbreset(&mut self) -> UsbresetW { - UsbresetW::new(self, 7) - } -} -#[doc = "USB Transceiver Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`usbtrc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbtrc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Usbtrc0Spec; -impl crate::RegisterSpec for Usbtrc0Spec { - type Ux = u8; -} -#[doc = "`read()` method returns [`usbtrc0::R`](R) reader structure"] -impl crate::Readable for Usbtrc0Spec {} -#[doc = "`write(|w| ..)` method takes [`usbtrc0::W`](W) writer structure"] -impl crate::Writable for Usbtrc0Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets USBTRC0 to value 0"] -impl crate::Resettable for Usbtrc0Spec {} diff --git a/mcxa276-pac/src/utick0.rs b/mcxa276-pac/src/utick0.rs deleted file mode 100644 index 03d70fdc9..000000000 --- a/mcxa276-pac/src/utick0.rs +++ /dev/null @@ -1,67 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - ctrl: Ctrl, - stat: Stat, - cfg: Cfg, - capclr: Capclr, - cap: [Cap; 4], -} -impl RegisterBlock { - #[doc = "0x00 - Control"] - #[inline(always)] - pub const fn ctrl(&self) -> &Ctrl { - &self.ctrl - } - #[doc = "0x04 - Status"] - #[inline(always)] - pub const fn stat(&self) -> &Stat { - &self.stat - } - #[doc = "0x08 - Capture Configuration"] - #[inline(always)] - pub const fn cfg(&self) -> &Cfg { - &self.cfg - } - #[doc = "0x0c - Capture Clear"] - #[inline(always)] - pub const fn capclr(&self) -> &Capclr { - &self.capclr - } - #[doc = "0x10..0x20 - Capture"] - #[inline(always)] - pub const fn cap(&self, n: usize) -> &Cap { - &self.cap[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x10..0x20 - Capture"] - #[inline(always)] - pub fn cap_iter(&self) -> impl Iterator { - self.cap.iter() - } -} -#[doc = "CTRL (rw) register accessor: Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] -#[doc(alias = "CTRL")] -pub type Ctrl = crate::Reg; -#[doc = "Control"] -pub mod ctrl; -#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] -#[doc(alias = "STAT")] -pub type Stat = crate::Reg; -#[doc = "Status"] -pub mod stat; -#[doc = "CFG (rw) register accessor: Capture Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`] module"] -#[doc(alias = "CFG")] -pub type Cfg = crate::Reg; -#[doc = "Capture Configuration"] -pub mod cfg; -#[doc = "CAPCLR (w) register accessor: Capture Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`capclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capclr`] module"] -#[doc(alias = "CAPCLR")] -pub type Capclr = crate::Reg; -#[doc = "Capture Clear"] -pub mod capclr; -#[doc = "CAP (r) register accessor: Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap`] module"] -#[doc(alias = "CAP")] -pub type Cap = crate::Reg; -#[doc = "Capture"] -pub mod cap; diff --git a/mcxa276-pac/src/utick0/cap.rs b/mcxa276-pac/src/utick0/cap.rs deleted file mode 100644 index ca81fc82d..000000000 --- a/mcxa276-pac/src/utick0/cap.rs +++ /dev/null @@ -1,61 +0,0 @@ -#[doc = "Register `CAP[%s]` reader"] -pub type R = crate::R; -#[doc = "Field `CAP_VALUE` reader - Captured Value for the Related Capture Event"] -pub type CapValueR = crate::FieldReader; -#[doc = "Captured Value Valid Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Valid { - #[doc = "0: Valid value not captured"] - Notvalid = 0, - #[doc = "1: Valid value captured"] - Valid = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Valid) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `VALID` reader - Captured Value Valid Flag"] -pub type ValidR = crate::BitReader; -impl ValidR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Valid { - match self.bits { - false => Valid::Notvalid, - true => Valid::Valid, - } - } - #[doc = "Valid value not captured"] - #[inline(always)] - pub fn is_notvalid(&self) -> bool { - *self == Valid::Notvalid - } - #[doc = "Valid value captured"] - #[inline(always)] - pub fn is_valid(&self) -> bool { - *self == Valid::Valid - } -} -impl R { - #[doc = "Bits 0:30 - Captured Value for the Related Capture Event"] - #[inline(always)] - pub fn cap_value(&self) -> CapValueR { - CapValueR::new(self.bits & 0x7fff_ffff) - } - #[doc = "Bit 31 - Captured Value Valid Flag"] - #[inline(always)] - pub fn valid(&self) -> ValidR { - ValidR::new(((self.bits >> 31) & 1) != 0) - } -} -#[doc = "Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`cap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CapSpec; -impl crate::RegisterSpec for CapSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cap::R`](R) reader structure"] -impl crate::Readable for CapSpec {} -#[doc = "`reset()` method sets CAP[%s] to value 0"] -impl crate::Resettable for CapSpec {} diff --git a/mcxa276-pac/src/utick0/capclr.rs b/mcxa276-pac/src/utick0/capclr.rs deleted file mode 100644 index 86b8d4d61..000000000 --- a/mcxa276-pac/src/utick0/capclr.rs +++ /dev/null @@ -1,159 +0,0 @@ -#[doc = "Register `CAPCLR` writer"] -pub type W = crate::W; -#[doc = "Clear Capture 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capclr0 { - #[doc = "0: Does nothing"] - Capclr0nothing = 0, - #[doc = "1: Clears the CAP0 register value"] - Capclr0cleared = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capclr0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPCLR0` writer - Clear Capture 0"] -pub type Capclr0W<'a, REG> = crate::BitWriter<'a, REG, Capclr0>; -impl<'a, REG> Capclr0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn capclr0nothing(self) -> &'a mut crate::W { - self.variant(Capclr0::Capclr0nothing) - } - #[doc = "Clears the CAP0 register value"] - #[inline(always)] - pub fn capclr0cleared(self) -> &'a mut crate::W { - self.variant(Capclr0::Capclr0cleared) - } -} -#[doc = "Clear Capture 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capclr1 { - #[doc = "0: Does nothing"] - Capclr1nothing = 0, - #[doc = "1: Clears the CAP1 register value"] - Capclr1cleared = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capclr1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPCLR1` writer - Clear Capture 1"] -pub type Capclr1W<'a, REG> = crate::BitWriter<'a, REG, Capclr1>; -impl<'a, REG> Capclr1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn capclr1nothing(self) -> &'a mut crate::W { - self.variant(Capclr1::Capclr1nothing) - } - #[doc = "Clears the CAP1 register value"] - #[inline(always)] - pub fn capclr1cleared(self) -> &'a mut crate::W { - self.variant(Capclr1::Capclr1cleared) - } -} -#[doc = "Clear Capture 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capclr2 { - #[doc = "0: Does nothing"] - Capclr2nothing = 0, - #[doc = "1: Clears the CAP2 register value"] - Capclr2cleared = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capclr2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPCLR2` writer - Clear Capture 2"] -pub type Capclr2W<'a, REG> = crate::BitWriter<'a, REG, Capclr2>; -impl<'a, REG> Capclr2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn capclr2nothing(self) -> &'a mut crate::W { - self.variant(Capclr2::Capclr2nothing) - } - #[doc = "Clears the CAP2 register value"] - #[inline(always)] - pub fn capclr2cleared(self) -> &'a mut crate::W { - self.variant(Capclr2::Capclr2cleared) - } -} -#[doc = "Clear Capture 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capclr3 { - #[doc = "0: Does nothing"] - Capclr3nothing = 0, - #[doc = "1: Clears the CAP3 register value"] - Capclr3cleared = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capclr3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPCLR3` writer - Clear Capture 3"] -pub type Capclr3W<'a, REG> = crate::BitWriter<'a, REG, Capclr3>; -impl<'a, REG> Capclr3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Does nothing"] - #[inline(always)] - pub fn capclr3nothing(self) -> &'a mut crate::W { - self.variant(Capclr3::Capclr3nothing) - } - #[doc = "Clears the CAP3 register value"] - #[inline(always)] - pub fn capclr3cleared(self) -> &'a mut crate::W { - self.variant(Capclr3::Capclr3cleared) - } -} -impl W { - #[doc = "Bit 0 - Clear Capture 0"] - #[inline(always)] - pub fn capclr0(&mut self) -> Capclr0W { - Capclr0W::new(self, 0) - } - #[doc = "Bit 1 - Clear Capture 1"] - #[inline(always)] - pub fn capclr1(&mut self) -> Capclr1W { - Capclr1W::new(self, 1) - } - #[doc = "Bit 2 - Clear Capture 2"] - #[inline(always)] - pub fn capclr2(&mut self) -> Capclr2W { - Capclr2W::new(self, 2) - } - #[doc = "Bit 3 - Clear Capture 3"] - #[inline(always)] - pub fn capclr3(&mut self) -> Capclr3W { - Capclr3W::new(self, 3) - } -} -#[doc = "Capture Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`capclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CapclrSpec; -impl crate::RegisterSpec for CapclrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`capclr::W`](W) writer structure"] -impl crate::Writable for CapclrSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CAPCLR to value 0"] -impl crate::Resettable for CapclrSpec {} diff --git a/mcxa276-pac/src/utick0/cfg.rs b/mcxa276-pac/src/utick0/cfg.rs deleted file mode 100644 index 671c690ce..000000000 --- a/mcxa276-pac/src/utick0/cfg.rs +++ /dev/null @@ -1,525 +0,0 @@ -#[doc = "Register `CFG` reader"] -pub type R = crate::R; -#[doc = "Register `CFG` writer"] -pub type W = crate::W; -#[doc = "Enable Capture 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capen0 { - #[doc = "0: Disable"] - Capen0isdisabled = 0, - #[doc = "1: Enable"] - Capen0isenabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capen0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPEN0` reader - Enable Capture 0"] -pub type Capen0R = crate::BitReader; -impl Capen0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Capen0 { - match self.bits { - false => Capen0::Capen0isdisabled, - true => Capen0::Capen0isenabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_capen0isdisabled(&self) -> bool { - *self == Capen0::Capen0isdisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_capen0isenabled(&self) -> bool { - *self == Capen0::Capen0isenabled - } -} -#[doc = "Field `CAPEN0` writer - Enable Capture 0"] -pub type Capen0W<'a, REG> = crate::BitWriter<'a, REG, Capen0>; -impl<'a, REG> Capen0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn capen0isdisabled(self) -> &'a mut crate::W { - self.variant(Capen0::Capen0isdisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn capen0isenabled(self) -> &'a mut crate::W { - self.variant(Capen0::Capen0isenabled) - } -} -#[doc = "Enable Capture 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capen1 { - #[doc = "0: Disable"] - Capen1isdisabled = 0, - #[doc = "1: Enable"] - Capen1isenabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capen1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPEN1` reader - Enable Capture 1"] -pub type Capen1R = crate::BitReader; -impl Capen1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Capen1 { - match self.bits { - false => Capen1::Capen1isdisabled, - true => Capen1::Capen1isenabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_capen1isdisabled(&self) -> bool { - *self == Capen1::Capen1isdisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_capen1isenabled(&self) -> bool { - *self == Capen1::Capen1isenabled - } -} -#[doc = "Field `CAPEN1` writer - Enable Capture 1"] -pub type Capen1W<'a, REG> = crate::BitWriter<'a, REG, Capen1>; -impl<'a, REG> Capen1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn capen1isdisabled(self) -> &'a mut crate::W { - self.variant(Capen1::Capen1isdisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn capen1isenabled(self) -> &'a mut crate::W { - self.variant(Capen1::Capen1isenabled) - } -} -#[doc = "Enable Capture 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capen2 { - #[doc = "0: Disable"] - Capen2isdisabled = 0, - #[doc = "1: Enable"] - Capen2isenabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capen2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPEN2` reader - Enable Capture 2"] -pub type Capen2R = crate::BitReader; -impl Capen2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Capen2 { - match self.bits { - false => Capen2::Capen2isdisabled, - true => Capen2::Capen2isenabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_capen2isdisabled(&self) -> bool { - *self == Capen2::Capen2isdisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_capen2isenabled(&self) -> bool { - *self == Capen2::Capen2isenabled - } -} -#[doc = "Field `CAPEN2` writer - Enable Capture 2"] -pub type Capen2W<'a, REG> = crate::BitWriter<'a, REG, Capen2>; -impl<'a, REG> Capen2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn capen2isdisabled(self) -> &'a mut crate::W { - self.variant(Capen2::Capen2isdisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn capen2isenabled(self) -> &'a mut crate::W { - self.variant(Capen2::Capen2isenabled) - } -} -#[doc = "Enable Capture 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Capen3 { - #[doc = "0: Disable"] - Capen3isdisabled = 0, - #[doc = "1: Enable"] - Capen3isenabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Capen3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPEN3` reader - Enable Capture 3"] -pub type Capen3R = crate::BitReader; -impl Capen3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Capen3 { - match self.bits { - false => Capen3::Capen3isdisabled, - true => Capen3::Capen3isenabled, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_capen3isdisabled(&self) -> bool { - *self == Capen3::Capen3isdisabled - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_capen3isenabled(&self) -> bool { - *self == Capen3::Capen3isenabled - } -} -#[doc = "Field `CAPEN3` writer - Enable Capture 3"] -pub type Capen3W<'a, REG> = crate::BitWriter<'a, REG, Capen3>; -impl<'a, REG> Capen3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn capen3isdisabled(self) -> &'a mut crate::W { - self.variant(Capen3::Capen3isdisabled) - } - #[doc = "Enable"] - #[inline(always)] - pub fn capen3isenabled(self) -> &'a mut crate::W { - self.variant(Capen3::Capen3isenabled) - } -} -#[doc = "Capture Polarity 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cappol0 { - #[doc = "0: Positive"] - Cappol0posedgecapture = 0, - #[doc = "1: Negative"] - Cappol0negedgecapture = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cappol0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPPOL0` reader - Capture Polarity 0"] -pub type Cappol0R = crate::BitReader; -impl Cappol0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cappol0 { - match self.bits { - false => Cappol0::Cappol0posedgecapture, - true => Cappol0::Cappol0negedgecapture, - } - } - #[doc = "Positive"] - #[inline(always)] - pub fn is_cappol0posedgecapture(&self) -> bool { - *self == Cappol0::Cappol0posedgecapture - } - #[doc = "Negative"] - #[inline(always)] - pub fn is_cappol0negedgecapture(&self) -> bool { - *self == Cappol0::Cappol0negedgecapture - } -} -#[doc = "Field `CAPPOL0` writer - Capture Polarity 0"] -pub type Cappol0W<'a, REG> = crate::BitWriter<'a, REG, Cappol0>; -impl<'a, REG> Cappol0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Positive"] - #[inline(always)] - pub fn cappol0posedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol0::Cappol0posedgecapture) - } - #[doc = "Negative"] - #[inline(always)] - pub fn cappol0negedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol0::Cappol0negedgecapture) - } -} -#[doc = "Capture-Polarity 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cappol1 { - #[doc = "0: Positive"] - Cappol1posedgecapture = 0, - #[doc = "1: Negative"] - Cappol1negedgecapture = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cappol1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPPOL1` reader - Capture-Polarity 1"] -pub type Cappol1R = crate::BitReader; -impl Cappol1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cappol1 { - match self.bits { - false => Cappol1::Cappol1posedgecapture, - true => Cappol1::Cappol1negedgecapture, - } - } - #[doc = "Positive"] - #[inline(always)] - pub fn is_cappol1posedgecapture(&self) -> bool { - *self == Cappol1::Cappol1posedgecapture - } - #[doc = "Negative"] - #[inline(always)] - pub fn is_cappol1negedgecapture(&self) -> bool { - *self == Cappol1::Cappol1negedgecapture - } -} -#[doc = "Field `CAPPOL1` writer - Capture-Polarity 1"] -pub type Cappol1W<'a, REG> = crate::BitWriter<'a, REG, Cappol1>; -impl<'a, REG> Cappol1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Positive"] - #[inline(always)] - pub fn cappol1posedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol1::Cappol1posedgecapture) - } - #[doc = "Negative"] - #[inline(always)] - pub fn cappol1negedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol1::Cappol1negedgecapture) - } -} -#[doc = "Capture Polarity 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cappol2 { - #[doc = "0: Positive"] - Cappol2posedgecapture = 0, - #[doc = "1: Negative"] - Cappol2negedgecapture = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cappol2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPPOL2` reader - Capture Polarity 2"] -pub type Cappol2R = crate::BitReader; -impl Cappol2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cappol2 { - match self.bits { - false => Cappol2::Cappol2posedgecapture, - true => Cappol2::Cappol2negedgecapture, - } - } - #[doc = "Positive"] - #[inline(always)] - pub fn is_cappol2posedgecapture(&self) -> bool { - *self == Cappol2::Cappol2posedgecapture - } - #[doc = "Negative"] - #[inline(always)] - pub fn is_cappol2negedgecapture(&self) -> bool { - *self == Cappol2::Cappol2negedgecapture - } -} -#[doc = "Field `CAPPOL2` writer - Capture Polarity 2"] -pub type Cappol2W<'a, REG> = crate::BitWriter<'a, REG, Cappol2>; -impl<'a, REG> Cappol2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Positive"] - #[inline(always)] - pub fn cappol2posedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol2::Cappol2posedgecapture) - } - #[doc = "Negative"] - #[inline(always)] - pub fn cappol2negedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol2::Cappol2negedgecapture) - } -} -#[doc = "Capture Polarity 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Cappol3 { - #[doc = "0: Positive"] - Cappol3posedgecapture = 0, - #[doc = "1: Negative"] - Cappol3negedgecapture = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Cappol3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CAPPOL3` reader - Capture Polarity 3"] -pub type Cappol3R = crate::BitReader; -impl Cappol3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Cappol3 { - match self.bits { - false => Cappol3::Cappol3posedgecapture, - true => Cappol3::Cappol3negedgecapture, - } - } - #[doc = "Positive"] - #[inline(always)] - pub fn is_cappol3posedgecapture(&self) -> bool { - *self == Cappol3::Cappol3posedgecapture - } - #[doc = "Negative"] - #[inline(always)] - pub fn is_cappol3negedgecapture(&self) -> bool { - *self == Cappol3::Cappol3negedgecapture - } -} -#[doc = "Field `CAPPOL3` writer - Capture Polarity 3"] -pub type Cappol3W<'a, REG> = crate::BitWriter<'a, REG, Cappol3>; -impl<'a, REG> Cappol3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Positive"] - #[inline(always)] - pub fn cappol3posedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol3::Cappol3posedgecapture) - } - #[doc = "Negative"] - #[inline(always)] - pub fn cappol3negedgecapture(self) -> &'a mut crate::W { - self.variant(Cappol3::Cappol3negedgecapture) - } -} -impl R { - #[doc = "Bit 0 - Enable Capture 0"] - #[inline(always)] - pub fn capen0(&self) -> Capen0R { - Capen0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Enable Capture 1"] - #[inline(always)] - pub fn capen1(&self) -> Capen1R { - Capen1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Enable Capture 2"] - #[inline(always)] - pub fn capen2(&self) -> Capen2R { - Capen2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Enable Capture 3"] - #[inline(always)] - pub fn capen3(&self) -> Capen3R { - Capen3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 8 - Capture Polarity 0"] - #[inline(always)] - pub fn cappol0(&self) -> Cappol0R { - Cappol0R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Capture-Polarity 1"] - #[inline(always)] - pub fn cappol1(&self) -> Cappol1R { - Cappol1R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Capture Polarity 2"] - #[inline(always)] - pub fn cappol2(&self) -> Cappol2R { - Cappol2R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Capture Polarity 3"] - #[inline(always)] - pub fn cappol3(&self) -> Cappol3R { - Cappol3R::new(((self.bits >> 11) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enable Capture 0"] - #[inline(always)] - pub fn capen0(&mut self) -> Capen0W { - Capen0W::new(self, 0) - } - #[doc = "Bit 1 - Enable Capture 1"] - #[inline(always)] - pub fn capen1(&mut self) -> Capen1W { - Capen1W::new(self, 1) - } - #[doc = "Bit 2 - Enable Capture 2"] - #[inline(always)] - pub fn capen2(&mut self) -> Capen2W { - Capen2W::new(self, 2) - } - #[doc = "Bit 3 - Enable Capture 3"] - #[inline(always)] - pub fn capen3(&mut self) -> Capen3W { - Capen3W::new(self, 3) - } - #[doc = "Bit 8 - Capture Polarity 0"] - #[inline(always)] - pub fn cappol0(&mut self) -> Cappol0W { - Cappol0W::new(self, 8) - } - #[doc = "Bit 9 - Capture-Polarity 1"] - #[inline(always)] - pub fn cappol1(&mut self) -> Cappol1W { - Cappol1W::new(self, 9) - } - #[doc = "Bit 10 - Capture Polarity 2"] - #[inline(always)] - pub fn cappol2(&mut self) -> Cappol2W { - Cappol2W::new(self, 10) - } - #[doc = "Bit 11 - Capture Polarity 3"] - #[inline(always)] - pub fn cappol3(&mut self) -> Cappol3W { - Cappol3W::new(self, 11) - } -} -#[doc = "Capture Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CfgSpec; -impl crate::RegisterSpec for CfgSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cfg::R`](R) reader structure"] -impl crate::Readable for CfgSpec {} -#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] -impl crate::Writable for CfgSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CFG to value 0"] -impl crate::Resettable for CfgSpec {} diff --git a/mcxa276-pac/src/utick0/ctrl.rs b/mcxa276-pac/src/utick0/ctrl.rs deleted file mode 100644 index c4fadd7cc..000000000 --- a/mcxa276-pac/src/utick0/ctrl.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `DELAYVAL` reader - Tick Interval"] -pub type DelayvalR = crate::FieldReader; -#[doc = "Field `DELAYVAL` writer - Tick Interval"] -pub type DelayvalW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; -#[doc = "Repeat Delay\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Repeat { - #[doc = "0: One-time delay"] - Delayonce = 0, - #[doc = "1: Delay repeats continuously"] - Delayrepeats = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Repeat) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `REPEAT` reader - Repeat Delay"] -pub type RepeatR = crate::BitReader; -impl RepeatR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Repeat { - match self.bits { - false => Repeat::Delayonce, - true => Repeat::Delayrepeats, - } - } - #[doc = "One-time delay"] - #[inline(always)] - pub fn is_delayonce(&self) -> bool { - *self == Repeat::Delayonce - } - #[doc = "Delay repeats continuously"] - #[inline(always)] - pub fn is_delayrepeats(&self) -> bool { - *self == Repeat::Delayrepeats - } -} -#[doc = "Field `REPEAT` writer - Repeat Delay"] -pub type RepeatW<'a, REG> = crate::BitWriter<'a, REG, Repeat>; -impl<'a, REG> RepeatW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "One-time delay"] - #[inline(always)] - pub fn delayonce(self) -> &'a mut crate::W { - self.variant(Repeat::Delayonce) - } - #[doc = "Delay repeats continuously"] - #[inline(always)] - pub fn delayrepeats(self) -> &'a mut crate::W { - self.variant(Repeat::Delayrepeats) - } -} -impl R { - #[doc = "Bits 0:30 - Tick Interval"] - #[inline(always)] - pub fn delayval(&self) -> DelayvalR { - DelayvalR::new(self.bits & 0x7fff_ffff) - } - #[doc = "Bit 31 - Repeat Delay"] - #[inline(always)] - pub fn repeat(&self) -> RepeatR { - RepeatR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:30 - Tick Interval"] - #[inline(always)] - pub fn delayval(&mut self) -> DelayvalW { - DelayvalW::new(self, 0) - } - #[doc = "Bit 31 - Repeat Delay"] - #[inline(always)] - pub fn repeat(&mut self) -> RepeatW { - RepeatW::new(self, 31) - } -} -#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CtrlSpec; -impl crate::RegisterSpec for CtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] -impl crate::Readable for CtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] -impl crate::Writable for CtrlSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets CTRL to value 0"] -impl crate::Resettable for CtrlSpec {} diff --git a/mcxa276-pac/src/utick0/stat.rs b/mcxa276-pac/src/utick0/stat.rs deleted file mode 100644 index c77ea4bfb..000000000 --- a/mcxa276-pac/src/utick0/stat.rs +++ /dev/null @@ -1,126 +0,0 @@ -#[doc = "Register `STAT` reader"] -pub type R = crate::R; -#[doc = "Register `STAT` writer"] -pub type W = crate::W; -#[doc = "Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Intr { - #[doc = "0: Not pending"] - Nopendinginterrupt = 0, - #[doc = "1: Pending"] - Pendinginterrupt = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Intr) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTR` reader - Interrupt Flag"] -pub type IntrR = crate::BitReader; -impl IntrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Intr { - match self.bits { - false => Intr::Nopendinginterrupt, - true => Intr::Pendinginterrupt, - } - } - #[doc = "Not pending"] - #[inline(always)] - pub fn is_nopendinginterrupt(&self) -> bool { - *self == Intr::Nopendinginterrupt - } - #[doc = "Pending"] - #[inline(always)] - pub fn is_pendinginterrupt(&self) -> bool { - *self == Intr::Pendinginterrupt - } -} -#[doc = "Field `INTR` writer - Interrupt Flag"] -pub type IntrW<'a, REG> = crate::BitWriter1C<'a, REG, Intr>; -impl<'a, REG> IntrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Not pending"] - #[inline(always)] - pub fn nopendinginterrupt(self) -> &'a mut crate::W { - self.variant(Intr::Nopendinginterrupt) - } - #[doc = "Pending"] - #[inline(always)] - pub fn pendinginterrupt(self) -> &'a mut crate::W { - self.variant(Intr::Pendinginterrupt) - } -} -#[doc = "Timer Active Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Active { - #[doc = "0: Inactive (stopped)"] - Timerisnotactive = 0, - #[doc = "1: Active"] - Timerisactive = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Active) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `ACTIVE` reader - Timer Active Flag"] -pub type ActiveR = crate::BitReader; -impl ActiveR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Active { - match self.bits { - false => Active::Timerisnotactive, - true => Active::Timerisactive, - } - } - #[doc = "Inactive (stopped)"] - #[inline(always)] - pub fn is_timerisnotactive(&self) -> bool { - *self == Active::Timerisnotactive - } - #[doc = "Active"] - #[inline(always)] - pub fn is_timerisactive(&self) -> bool { - *self == Active::Timerisactive - } -} -impl R { - #[doc = "Bit 0 - Interrupt Flag"] - #[inline(always)] - pub fn intr(&self) -> IntrR { - IntrR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Timer Active Flag"] - #[inline(always)] - pub fn active(&self) -> ActiveR { - ActiveR::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Interrupt Flag"] - #[inline(always)] - pub fn intr(&mut self) -> IntrW { - IntrW::new(self, 0) - } -} -#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct StatSpec; -impl crate::RegisterSpec for StatSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`stat::R`](R) reader structure"] -impl crate::Readable for StatSpec {} -#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] -impl crate::Writable for StatSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; -} -#[doc = "`reset()` method sets STAT to value 0"] -impl crate::Resettable for StatSpec {} diff --git a/mcxa276-pac/src/vbat0.rs b/mcxa276-pac/src/vbat0.rs deleted file mode 100644 index acb3d3b81..000000000 --- a/mcxa276-pac/src/vbat0.rs +++ /dev/null @@ -1,97 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - _reserved1: [u8; 0x01fc], - froctla: Froctla, - _reserved2: [u8; 0x14], - frolcka: Frolcka, - _reserved3: [u8; 0x04], - froclke: Froclke, - _reserved4: [u8; 0x04dc], - wakeup: (), - _reserved5: [u8; 0xf8], - waklcka: Waklcka, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x200 - FRO16K Control A"] - #[inline(always)] - pub const fn froctla(&self) -> &Froctla { - &self.froctla - } - #[doc = "0x218 - FRO16K Lock A"] - #[inline(always)] - pub const fn frolcka(&self) -> &Frolcka { - &self.frolcka - } - #[doc = "0x220 - FRO16K Clock Enable"] - #[inline(always)] - pub const fn froclke(&self) -> &Froclke { - &self.froclke - } - #[doc = "0x700..0x708 - Array of registers: WAKEUPA"] - #[inline(always)] - pub const fn wakeup(&self, n: usize) -> &Wakeup { - #[allow(clippy::no_effect)] - [(); 2][n]; - unsafe { - &*core::ptr::from_ref(self) - .cast::() - .add(1792) - .add(8 * n) - .cast() - } - } - #[doc = "Iterator for array of:"] - #[doc = "0x700..0x708 - Array of registers: WAKEUPA"] - #[inline(always)] - pub fn wakeup_iter(&self) -> impl Iterator { - (0..2).map(move |n| unsafe { - &*core::ptr::from_ref(self) - .cast::() - .add(1792) - .add(8 * n) - .cast() - }) - } - #[doc = "0x7f8 - Wakeup Lock A"] - #[inline(always)] - pub const fn waklcka(&self) -> &Waklcka { - &self.waklcka - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "FROCTLA (rw) register accessor: FRO16K Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`froctla::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froctla::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@froctla`] module"] -#[doc(alias = "FROCTLA")] -pub type Froctla = crate::Reg; -#[doc = "FRO16K Control A"] -pub mod froctla; -#[doc = "FROLCKA (rw) register accessor: FRO16K Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`frolcka::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolcka::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frolcka`] module"] -#[doc(alias = "FROLCKA")] -pub type Frolcka = crate::Reg; -#[doc = "FRO16K Lock A"] -pub mod frolcka; -#[doc = "FROCLKE (rw) register accessor: FRO16K Clock Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`froclke::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froclke::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@froclke`] module"] -#[doc(alias = "FROCLKE")] -pub type Froclke = crate::Reg; -#[doc = "FRO16K Clock Enable"] -pub mod froclke; -#[doc = "Array of registers: WAKEUPA"] -pub use self::wakeup::Wakeup; -#[doc = r"Cluster"] -#[doc = "Array of registers: WAKEUPA"] -pub mod wakeup; -#[doc = "WAKLCKA (rw) register accessor: Wakeup Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`waklcka::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`waklcka::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@waklcka`] module"] -#[doc(alias = "WAKLCKA")] -pub type Waklcka = crate::Reg; -#[doc = "Wakeup Lock A"] -pub mod waklcka; diff --git a/mcxa276-pac/src/vbat0/froclke.rs b/mcxa276-pac/src/vbat0/froclke.rs deleted file mode 100644 index 0a7cd1084..000000000 --- a/mcxa276-pac/src/vbat0/froclke.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `FROCLKE` reader"] -pub type R = crate::R; -#[doc = "Register `FROCLKE` writer"] -pub type W = crate::W; -#[doc = "Field `CLKE` reader - Clock Enable"] -pub type ClkeR = crate::FieldReader; -#[doc = "Field `CLKE` writer - Clock Enable"] -pub type ClkeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - Clock Enable"] - #[inline(always)] - pub fn clke(&self) -> ClkeR { - ClkeR::new((self.bits & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Clock Enable"] - #[inline(always)] - pub fn clke(&mut self) -> ClkeW { - ClkeW::new(self, 0) - } -} -#[doc = "FRO16K Clock Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`froclke::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froclke::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FroclkeSpec; -impl crate::RegisterSpec for FroclkeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`froclke::R`](R) reader structure"] -impl crate::Readable for FroclkeSpec {} -#[doc = "`write(|w| ..)` method takes [`froclke::W`](W) writer structure"] -impl crate::Writable for FroclkeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FROCLKE to value 0"] -impl crate::Resettable for FroclkeSpec {} diff --git a/mcxa276-pac/src/vbat0/froctla.rs b/mcxa276-pac/src/vbat0/froctla.rs deleted file mode 100644 index 22b590cd2..000000000 --- a/mcxa276-pac/src/vbat0/froctla.rs +++ /dev/null @@ -1,86 +0,0 @@ -#[doc = "Register `FROCTLA` reader"] -pub type R = crate::R; -#[doc = "Register `FROCTLA` writer"] -pub type W = crate::W; -#[doc = "FRO16K Enable\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum FroEn { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: FroEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FRO_EN` reader - FRO16K Enable"] -pub type FroEnR = crate::BitReader; -impl FroEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> FroEn { - match self.bits { - false => FroEn::Disable, - true => FroEn::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == FroEn::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == FroEn::Enable - } -} -#[doc = "Field `FRO_EN` writer - FRO16K Enable"] -pub type FroEnW<'a, REG> = crate::BitWriter<'a, REG, FroEn>; -impl<'a, REG> FroEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(FroEn::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(FroEn::Enable) - } -} -impl R { - #[doc = "Bit 0 - FRO16K Enable"] - #[inline(always)] - pub fn fro_en(&self) -> FroEnR { - FroEnR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - FRO16K Enable"] - #[inline(always)] - pub fn fro_en(&mut self) -> FroEnW { - FroEnW::new(self, 0) - } -} -#[doc = "FRO16K Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`froctla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`froctla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FroctlaSpec; -impl crate::RegisterSpec for FroctlaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`froctla::R`](R) reader structure"] -impl crate::Readable for FroctlaSpec {} -#[doc = "`write(|w| ..)` method takes [`froctla::W`](W) writer structure"] -impl crate::Writable for FroctlaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FROCTLA to value 0x01"] -impl crate::Resettable for FroctlaSpec { - const RESET_VALUE: u32 = 0x01; -} diff --git a/mcxa276-pac/src/vbat0/frolcka.rs b/mcxa276-pac/src/vbat0/frolcka.rs deleted file mode 100644 index 09d486049..000000000 --- a/mcxa276-pac/src/vbat0/frolcka.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `FROLCKA` reader"] -pub type R = crate::R; -#[doc = "Register `FROLCKA` writer"] -pub type W = crate::W; -#[doc = "Lock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: Do not block"] - Disable = 0, - #[doc = "1: Block"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - Lock"] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Disable, - true => Lock::Enable, - } - } - #[doc = "Do not block"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lock::Disable - } - #[doc = "Block"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lock::Enable - } -} -#[doc = "Field `LOCK` writer - Lock"] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Do not block"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lock::Disable) - } - #[doc = "Block"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lock::Enable) - } -} -impl R { - #[doc = "Bit 0 - Lock"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Lock"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 0) - } -} -#[doc = "FRO16K Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`frolcka::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolcka::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FrolckaSpec; -impl crate::RegisterSpec for FrolckaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`frolcka::R`](R) reader structure"] -impl crate::Readable for FrolckaSpec {} -#[doc = "`write(|w| ..)` method takes [`frolcka::W`](W) writer structure"] -impl crate::Writable for FrolckaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FROLCKA to value 0"] -impl crate::Resettable for FrolckaSpec {} diff --git a/mcxa276-pac/src/vbat0/verid.rs b/mcxa276-pac/src/vbat0/verid.rs deleted file mode 100644 index 9e07aa71f..000000000 --- a/mcxa276-pac/src/vbat0/verid.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0101_0001"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0101_0001; -} diff --git a/mcxa276-pac/src/vbat0/wakeup.rs b/mcxa276-pac/src/vbat0/wakeup.rs deleted file mode 100644 index f434b04c5..000000000 --- a/mcxa276-pac/src/vbat0/wakeup.rs +++ /dev/null @@ -1,18 +0,0 @@ -#[repr(C)] -#[doc = "Array of registers: WAKEUPA"] -#[doc(alias = "WAKEUP")] -pub struct Wakeup { - wakeupa: Wakeupa, -} -impl Wakeup { - #[doc = "0x00 - Wakeup 0 Register A"] - #[inline(always)] - pub const fn wakeupa(&self) -> &Wakeupa { - &self.wakeupa - } -} -#[doc = "WAKEUPA (rw) register accessor: Wakeup 0 Register A\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeupa`] module"] -#[doc(alias = "WAKEUPA")] -pub type Wakeupa = crate::Reg; -#[doc = "Wakeup 0 Register A"] -pub mod wakeupa; diff --git a/mcxa276-pac/src/vbat0/wakeup/wakeupa.rs b/mcxa276-pac/src/vbat0/wakeup/wakeupa.rs deleted file mode 100644 index e3ce80400..000000000 --- a/mcxa276-pac/src/vbat0/wakeup/wakeupa.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `WAKEUPA` reader"] -pub type R = crate::R; -#[doc = "Register `WAKEUPA` writer"] -pub type W = crate::W; -#[doc = "Field `REG` reader - Register"] -pub type RegR = crate::FieldReader; -#[doc = "Field `REG` writer - Register"] -pub type RegW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Register"] - #[inline(always)] - pub fn reg(&self) -> RegR { - RegR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Register"] - #[inline(always)] - pub fn reg(&mut self) -> RegW { - RegW::new(self, 0) - } -} -#[doc = "Wakeup 0 Register A\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeupa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeupa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WakeupaSpec; -impl crate::RegisterSpec for WakeupaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wakeupa::R`](R) reader structure"] -impl crate::Readable for WakeupaSpec {} -#[doc = "`write(|w| ..)` method takes [`wakeupa::W`](W) writer structure"] -impl crate::Writable for WakeupaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WAKEUPA to value 0"] -impl crate::Resettable for WakeupaSpec {} diff --git a/mcxa276-pac/src/vbat0/waklcka.rs b/mcxa276-pac/src/vbat0/waklcka.rs deleted file mode 100644 index 994acaf6d..000000000 --- a/mcxa276-pac/src/vbat0/waklcka.rs +++ /dev/null @@ -1,84 +0,0 @@ -#[doc = "Register `WAKLCKA` reader"] -pub type R = crate::R; -#[doc = "Register `WAKLCKA` writer"] -pub type W = crate::W; -#[doc = "Lock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: Lock is disabled"] - Disable = 0, - #[doc = "1: Lock is enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - Lock"] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::Disable, - true => Lock::Enable, - } - } - #[doc = "Lock is disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Lock::Disable - } - #[doc = "Lock is enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Lock::Enable - } -} -#[doc = "Field `LOCK` writer - Lock"] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Lock is disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Lock::Disable) - } - #[doc = "Lock is enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Lock::Enable) - } -} -impl R { - #[doc = "Bit 0 - Lock"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new((self.bits & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Lock"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 0) - } -} -#[doc = "Wakeup Lock A\n\nYou can [`read`](crate::Reg::read) this register and get [`waklcka::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`waklcka::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WaklckaSpec; -impl crate::RegisterSpec for WaklckaSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`waklcka::R`](R) reader structure"] -impl crate::Readable for WaklckaSpec {} -#[doc = "`write(|w| ..)` method takes [`waklcka::W`](W) writer structure"] -impl crate::Writable for WaklckaSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WAKLCKA to value 0"] -impl crate::Resettable for WaklckaSpec {} diff --git a/mcxa276-pac/src/waketimer0.rs b/mcxa276-pac/src/waketimer0.rs deleted file mode 100644 index 0d5d0dbaa..000000000 --- a/mcxa276-pac/src/waketimer0.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - wake_timer_ctrl: WakeTimerCtrl, - _reserved1: [u8; 0x08], - wake_timer_cnt: WakeTimerCnt, -} -impl RegisterBlock { - #[doc = "0x00 - Wake Timer Control"] - #[inline(always)] - pub const fn wake_timer_ctrl(&self) -> &WakeTimerCtrl { - &self.wake_timer_ctrl - } - #[doc = "0x0c - Wake Timer Counter"] - #[inline(always)] - pub const fn wake_timer_cnt(&self) -> &WakeTimerCnt { - &self.wake_timer_cnt - } -} -#[doc = "WAKE_TIMER_CTRL (rw) register accessor: Wake Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wake_timer_ctrl`] module"] -#[doc(alias = "WAKE_TIMER_CTRL")] -pub type WakeTimerCtrl = crate::Reg; -#[doc = "Wake Timer Control"] -pub mod wake_timer_ctrl; -#[doc = "WAKE_TIMER_CNT (rw) register accessor: Wake Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wake_timer_cnt`] module"] -#[doc(alias = "WAKE_TIMER_CNT")] -pub type WakeTimerCnt = crate::Reg; -#[doc = "Wake Timer Counter"] -pub mod wake_timer_cnt; diff --git a/mcxa276-pac/src/waketimer0/wake_timer_cnt.rs b/mcxa276-pac/src/waketimer0/wake_timer_cnt.rs deleted file mode 100644 index de748204e..000000000 --- a/mcxa276-pac/src/waketimer0/wake_timer_cnt.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `WAKE_TIMER_CNT` reader"] -pub type R = crate::R; -#[doc = "Register `WAKE_TIMER_CNT` writer"] -pub type W = crate::W; -#[doc = "Field `WAKE_CNT` reader - Wake Counter"] -pub type WakeCntR = crate::FieldReader; -#[doc = "Field `WAKE_CNT` writer - Wake Counter"] -pub type WakeCntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - Wake Counter"] - #[inline(always)] - pub fn wake_cnt(&self) -> WakeCntR { - WakeCntR::new(self.bits) - } -} -impl W { - #[doc = "Bits 0:31 - Wake Counter"] - #[inline(always)] - pub fn wake_cnt(&mut self) -> WakeCntW { - WakeCntW::new(self, 0) - } -} -#[doc = "Wake Timer Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WakeTimerCntSpec; -impl crate::RegisterSpec for WakeTimerCntSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wake_timer_cnt::R`](R) reader structure"] -impl crate::Readable for WakeTimerCntSpec {} -#[doc = "`write(|w| ..)` method takes [`wake_timer_cnt::W`](W) writer structure"] -impl crate::Writable for WakeTimerCntSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WAKE_TIMER_CNT to value 0"] -impl crate::Resettable for WakeTimerCntSpec {} diff --git a/mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs b/mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs deleted file mode 100644 index 14eab3655..000000000 --- a/mcxa276-pac/src/waketimer0/wake_timer_ctrl.rs +++ /dev/null @@ -1,247 +0,0 @@ -#[doc = "Register `WAKE_TIMER_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `WAKE_TIMER_CTRL` writer"] -pub type W = crate::W; -#[doc = "Wake Timer Status Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum WakeFlag { - #[doc = "0: Wake timer has not timed out."] - Disable = 0, - #[doc = "1: Wake timer has timed out."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: WakeFlag) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WAKE_FLAG` reader - Wake Timer Status Flag"] -pub type WakeFlagR = crate::BitReader; -impl WakeFlagR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> WakeFlag { - match self.bits { - false => WakeFlag::Disable, - true => WakeFlag::Enable, - } - } - #[doc = "Wake timer has not timed out."] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == WakeFlag::Disable - } - #[doc = "Wake timer has timed out."] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == WakeFlag::Enable - } -} -#[doc = "Field `WAKE_FLAG` writer - Wake Timer Status Flag"] -pub type WakeFlagW<'a, REG> = crate::BitWriter1C<'a, REG, WakeFlag>; -impl<'a, REG> WakeFlagW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Wake timer has not timed out."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(WakeFlag::Disable) - } - #[doc = "Wake timer has timed out."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(WakeFlag::Enable) - } -} -#[doc = "Clear Wake Timer\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ClrWakeTimer { - #[doc = "0: No effect."] - Disable = 0, - #[doc = "1: Clears the wake timer counter and halts operation until a new count value is loaded."] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: ClrWakeTimer) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `CLR_WAKE_TIMER` writer - Clear Wake Timer"] -pub type ClrWakeTimerW<'a, REG> = crate::BitWriter<'a, REG, ClrWakeTimer>; -impl<'a, REG> ClrWakeTimerW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No effect."] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(ClrWakeTimer::Disable) - } - #[doc = "Clears the wake timer counter and halts operation until a new count value is loaded."] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(ClrWakeTimer::Enable) - } -} -#[doc = "OSC Divide Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum OscDivEna { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: OscDivEna) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OSC_DIV_ENA` reader - OSC Divide Enable"] -pub type OscDivEnaR = crate::BitReader; -impl OscDivEnaR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> OscDivEna { - match self.bits { - false => OscDivEna::Disable, - true => OscDivEna::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == OscDivEna::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == OscDivEna::Enable - } -} -#[doc = "Field `OSC_DIV_ENA` writer - OSC Divide Enable"] -pub type OscDivEnaW<'a, REG> = crate::BitWriter<'a, REG, OscDivEna>; -impl<'a, REG> OscDivEnaW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(OscDivEna::Disable) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(OscDivEna::Enable) - } -} -#[doc = "Enable Interrupt\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum IntrEn { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: IntrEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `INTR_EN` reader - Enable Interrupt"] -pub type IntrEnR = crate::BitReader; -impl IntrEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> IntrEn { - match self.bits { - false => IntrEn::Disable, - true => IntrEn::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == IntrEn::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == IntrEn::Enable - } -} -#[doc = "Field `INTR_EN` writer - Enable Interrupt"] -pub type IntrEnW<'a, REG> = crate::BitWriter<'a, REG, IntrEn>; -impl<'a, REG> IntrEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(IntrEn::Disable) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(IntrEn::Enable) - } -} -impl R { - #[doc = "Bit 1 - Wake Timer Status Flag"] - #[inline(always)] - pub fn wake_flag(&self) -> WakeFlagR { - WakeFlagR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 4 - OSC Divide Enable"] - #[inline(always)] - pub fn osc_div_ena(&self) -> OscDivEnaR { - OscDivEnaR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Enable Interrupt"] - #[inline(always)] - pub fn intr_en(&self) -> IntrEnR { - IntrEnR::new(((self.bits >> 5) & 1) != 0) - } -} -impl W { - #[doc = "Bit 1 - Wake Timer Status Flag"] - #[inline(always)] - pub fn wake_flag(&mut self) -> WakeFlagW { - WakeFlagW::new(self, 1) - } - #[doc = "Bit 2 - Clear Wake Timer"] - #[inline(always)] - pub fn clr_wake_timer(&mut self) -> ClrWakeTimerW { - ClrWakeTimerW::new(self, 2) - } - #[doc = "Bit 4 - OSC Divide Enable"] - #[inline(always)] - pub fn osc_div_ena(&mut self) -> OscDivEnaW { - OscDivEnaW::new(self, 4) - } - #[doc = "Bit 5 - Enable Interrupt"] - #[inline(always)] - pub fn intr_en(&mut self) -> IntrEnW { - IntrEnW::new(self, 5) - } -} -#[doc = "Wake Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wake_timer_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_timer_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WakeTimerCtrlSpec; -impl crate::RegisterSpec for WakeTimerCtrlSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`wake_timer_ctrl::R`](R) reader structure"] -impl crate::Readable for WakeTimerCtrlSpec {} -#[doc = "`write(|w| ..)` method takes [`wake_timer_ctrl::W`](W) writer structure"] -impl crate::Writable for WakeTimerCtrlSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x02; -} -#[doc = "`reset()` method sets WAKE_TIMER_CTRL to value 0"] -impl crate::Resettable for WakeTimerCtrlSpec {} diff --git a/mcxa276-pac/src/wuu0.rs b/mcxa276-pac/src/wuu0.rs deleted file mode 100644 index 15a2e7cd0..000000000 --- a/mcxa276-pac/src/wuu0.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - verid: Verid, - param: Param, - pe1: Pe1, - pe2: Pe2, - _reserved4: [u8; 0x08], - me: Me, - de: De, - pf: Pf, - _reserved7: [u8; 0x0c], - filt: Filt, - _reserved8: [u8; 0x04], - pdc1: Pdc1, - pdc2: Pdc2, - _reserved10: [u8; 0x08], - fdc: Fdc, - _reserved11: [u8; 0x04], - pmc: Pmc, - _reserved12: [u8; 0x04], - fmc: Fmc, -} -impl RegisterBlock { - #[doc = "0x00 - Version ID"] - #[inline(always)] - pub const fn verid(&self) -> &Verid { - &self.verid - } - #[doc = "0x04 - Parameter"] - #[inline(always)] - pub const fn param(&self) -> &Param { - &self.param - } - #[doc = "0x08 - Pin Enable 1"] - #[inline(always)] - pub const fn pe1(&self) -> &Pe1 { - &self.pe1 - } - #[doc = "0x0c - Pin Enable 2"] - #[inline(always)] - pub const fn pe2(&self) -> &Pe2 { - &self.pe2 - } - #[doc = "0x18 - Module Interrupt Enable"] - #[inline(always)] - pub const fn me(&self) -> &Me { - &self.me - } - #[doc = "0x1c - Module DMA/Trigger Enable"] - #[inline(always)] - pub const fn de(&self) -> &De { - &self.de - } - #[doc = "0x20 - Pin Flag"] - #[inline(always)] - pub const fn pf(&self) -> &Pf { - &self.pf - } - #[doc = "0x30 - Pin Filter"] - #[inline(always)] - pub const fn filt(&self) -> &Filt { - &self.filt - } - #[doc = "0x38 - Pin DMA/Trigger Configuration 1"] - #[inline(always)] - pub const fn pdc1(&self) -> &Pdc1 { - &self.pdc1 - } - #[doc = "0x3c - Pin DMA/Trigger Configuration 2"] - #[inline(always)] - pub const fn pdc2(&self) -> &Pdc2 { - &self.pdc2 - } - #[doc = "0x48 - Pin Filter DMA/Trigger Configuration"] - #[inline(always)] - pub const fn fdc(&self) -> &Fdc { - &self.fdc - } - #[doc = "0x50 - Pin Mode Configuration"] - #[inline(always)] - pub const fn pmc(&self) -> &Pmc { - &self.pmc - } - #[doc = "0x58 - Pin Filter Mode Configuration"] - #[inline(always)] - pub const fn fmc(&self) -> &Fmc { - &self.fmc - } -} -#[doc = "VERID (r) register accessor: Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] -#[doc(alias = "VERID")] -pub type Verid = crate::Reg; -#[doc = "Version ID"] -pub mod verid; -#[doc = "PARAM (r) register accessor: Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@param`] module"] -#[doc(alias = "PARAM")] -pub type Param = crate::Reg; -#[doc = "Parameter"] -pub mod param; -#[doc = "PE1 (rw) register accessor: Pin Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pe1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pe1`] module"] -#[doc(alias = "PE1")] -pub type Pe1 = crate::Reg; -#[doc = "Pin Enable 1"] -pub mod pe1; -#[doc = "PE2 (rw) register accessor: Pin Enable 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pe2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pe2`] module"] -#[doc(alias = "PE2")] -pub type Pe2 = crate::Reg; -#[doc = "Pin Enable 2"] -pub mod pe2; -#[doc = "ME (rw) register accessor: Module Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`me::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`me::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@me`] module"] -#[doc(alias = "ME")] -pub type Me = crate::Reg; -#[doc = "Module Interrupt Enable"] -pub mod me; -#[doc = "DE (rw) register accessor: Module DMA/Trigger Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@de`] module"] -#[doc(alias = "DE")] -pub type De = crate::Reg; -#[doc = "Module DMA/Trigger Enable"] -pub mod de; -#[doc = "PF (rw) register accessor: Pin Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pf`] module"] -#[doc(alias = "PF")] -pub type Pf = crate::Reg; -#[doc = "Pin Flag"] -pub mod pf; -#[doc = "FILT (rw) register accessor: Pin Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filt`] module"] -#[doc(alias = "FILT")] -pub type Filt = crate::Reg; -#[doc = "Pin Filter"] -pub mod filt; -#[doc = "PDC1 (rw) register accessor: Pin DMA/Trigger Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc1`] module"] -#[doc(alias = "PDC1")] -pub type Pdc1 = crate::Reg; -#[doc = "Pin DMA/Trigger Configuration 1"] -pub mod pdc1; -#[doc = "PDC2 (rw) register accessor: Pin DMA/Trigger Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc2`] module"] -#[doc(alias = "PDC2")] -pub type Pdc2 = crate::Reg; -#[doc = "Pin DMA/Trigger Configuration 2"] -pub mod pdc2; -#[doc = "FDC (rw) register accessor: Pin Filter DMA/Trigger Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fdc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdc`] module"] -#[doc(alias = "FDC")] -pub type Fdc = crate::Reg; -#[doc = "Pin Filter DMA/Trigger Configuration"] -pub mod fdc; -#[doc = "PMC (rw) register accessor: Pin Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pmc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmc`] module"] -#[doc(alias = "PMC")] -pub type Pmc = crate::Reg; -#[doc = "Pin Mode Configuration"] -pub mod pmc; -#[doc = "FMC (rw) register accessor: Pin Filter Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fmc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fmc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmc`] module"] -#[doc(alias = "FMC")] -pub type Fmc = crate::Reg; -#[doc = "Pin Filter Mode Configuration"] -pub mod fmc; diff --git a/mcxa276-pac/src/wuu0/de.rs b/mcxa276-pac/src/wuu0/de.rs deleted file mode 100644 index b6ead9e45..000000000 --- a/mcxa276-pac/src/wuu0/de.rs +++ /dev/null @@ -1,210 +0,0 @@ -#[doc = "Register `DE` reader"] -pub type R = crate::R; -#[doc = "Register `DE` writer"] -pub type W = crate::W; -#[doc = "DMA/Trigger Wake-up Enable for Module 4\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wude4 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wude4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUDE4` reader - DMA/Trigger Wake-up Enable for Module 4"] -pub type Wude4R = crate::BitReader; -impl Wude4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wude4 { - match self.bits { - false => Wude4::Disable, - true => Wude4::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wude4::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wude4::Enable - } -} -#[doc = "Field `WUDE4` writer - DMA/Trigger Wake-up Enable for Module 4"] -pub type Wude4W<'a, REG> = crate::BitWriter<'a, REG, Wude4>; -impl<'a, REG> Wude4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wude4::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wude4::Enable) - } -} -#[doc = "DMA/Trigger Wake-up Enable for Module 6\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wude6 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wude6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUDE6` reader - DMA/Trigger Wake-up Enable for Module 6"] -pub type Wude6R = crate::BitReader; -impl Wude6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wude6 { - match self.bits { - false => Wude6::Disable, - true => Wude6::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wude6::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wude6::Enable - } -} -#[doc = "Field `WUDE6` writer - DMA/Trigger Wake-up Enable for Module 6"] -pub type Wude6W<'a, REG> = crate::BitWriter<'a, REG, Wude6>; -impl<'a, REG> Wude6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wude6::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wude6::Enable) - } -} -#[doc = "DMA/Trigger Wake-up Enable for Module 8\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wude8 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wude8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUDE8` reader - DMA/Trigger Wake-up Enable for Module 8"] -pub type Wude8R = crate::BitReader; -impl Wude8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wude8 { - match self.bits { - false => Wude8::Disable, - true => Wude8::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wude8::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wude8::Enable - } -} -#[doc = "Field `WUDE8` writer - DMA/Trigger Wake-up Enable for Module 8"] -pub type Wude8W<'a, REG> = crate::BitWriter<'a, REG, Wude8>; -impl<'a, REG> Wude8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wude8::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wude8::Enable) - } -} -impl R { - #[doc = "Bit 4 - DMA/Trigger Wake-up Enable for Module 4"] - #[inline(always)] - pub fn wude4(&self) -> Wude4R { - Wude4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 6 - DMA/Trigger Wake-up Enable for Module 6"] - #[inline(always)] - pub fn wude6(&self) -> Wude6R { - Wude6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - DMA/Trigger Wake-up Enable for Module 8"] - #[inline(always)] - pub fn wude8(&self) -> Wude8R { - Wude8R::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 4 - DMA/Trigger Wake-up Enable for Module 4"] - #[inline(always)] - pub fn wude4(&mut self) -> Wude4W { - Wude4W::new(self, 4) - } - #[doc = "Bit 6 - DMA/Trigger Wake-up Enable for Module 6"] - #[inline(always)] - pub fn wude6(&mut self) -> Wude6W { - Wude6W::new(self, 6) - } - #[doc = "Bit 8 - DMA/Trigger Wake-up Enable for Module 8"] - #[inline(always)] - pub fn wude8(&mut self) -> Wude8W { - Wude8W::new(self, 8) - } -} -#[doc = "Module DMA/Trigger Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DeSpec; -impl crate::RegisterSpec for DeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`de::R`](R) reader structure"] -impl crate::Readable for DeSpec {} -#[doc = "`write(|w| ..)` method takes [`de::W`](W) writer structure"] -impl crate::Writable for DeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets DE to value 0"] -impl crate::Resettable for DeSpec {} diff --git a/mcxa276-pac/src/wuu0/fdc.rs b/mcxa276-pac/src/wuu0/fdc.rs deleted file mode 100644 index 72aae3040..000000000 --- a/mcxa276-pac/src/wuu0/fdc.rs +++ /dev/null @@ -1,187 +0,0 @@ -#[doc = "Register `FDC` reader"] -pub type R = crate::R; -#[doc = "Register `FDC` writer"] -pub type W = crate::W; -#[doc = "Filter Configuration for FILTn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Filtc1 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Filtc1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Filtc1 { - type Ux = u8; -} -impl crate::IsEnum for Filtc1 {} -#[doc = "Field `FILTC1` reader - Filter Configuration for FILTn"] -pub type Filtc1R = crate::FieldReader; -impl Filtc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Filtc1::Interrupt), - 1 => Some(Filtc1::DmaReq), - 2 => Some(Filtc1::Trigger), - _ => None, - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Filtc1::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Filtc1::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Filtc1::Trigger - } -} -#[doc = "Field `FILTC1` writer - Filter Configuration for FILTn"] -pub type Filtc1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filtc1>; -impl<'a, REG> Filtc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Filtc1::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Filtc1::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Filtc1::Trigger) - } -} -#[doc = "Filter Configuration for FILTn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Filtc2 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Filtc2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Filtc2 { - type Ux = u8; -} -impl crate::IsEnum for Filtc2 {} -#[doc = "Field `FILTC2` reader - Filter Configuration for FILTn"] -pub type Filtc2R = crate::FieldReader; -impl Filtc2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Filtc2::Interrupt), - 1 => Some(Filtc2::DmaReq), - 2 => Some(Filtc2::Trigger), - _ => None, - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Filtc2::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Filtc2::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Filtc2::Trigger - } -} -#[doc = "Field `FILTC2` writer - Filter Configuration for FILTn"] -pub type Filtc2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filtc2>; -impl<'a, REG> Filtc2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Filtc2::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Filtc2::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Filtc2::Trigger) - } -} -impl R { - #[doc = "Bits 0:1 - Filter Configuration for FILTn"] - #[inline(always)] - pub fn filtc1(&self) -> Filtc1R { - Filtc1R::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Filter Configuration for FILTn"] - #[inline(always)] - pub fn filtc2(&self) -> Filtc2R { - Filtc2R::new(((self.bits >> 2) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Filter Configuration for FILTn"] - #[inline(always)] - pub fn filtc1(&mut self) -> Filtc1W { - Filtc1W::new(self, 0) - } - #[doc = "Bits 2:3 - Filter Configuration for FILTn"] - #[inline(always)] - pub fn filtc2(&mut self) -> Filtc2W { - Filtc2W::new(self, 2) - } -} -#[doc = "Pin Filter DMA/Trigger Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fdc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FdcSpec; -impl crate::RegisterSpec for FdcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fdc::R`](R) reader structure"] -impl crate::Readable for FdcSpec {} -#[doc = "`write(|w| ..)` method takes [`fdc::W`](W) writer structure"] -impl crate::Writable for FdcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FDC to value 0"] -impl crate::Resettable for FdcSpec {} diff --git a/mcxa276-pac/src/wuu0/filt.rs b/mcxa276-pac/src/wuu0/filt.rs deleted file mode 100644 index bf5597ba4..000000000 --- a/mcxa276-pac/src/wuu0/filt.rs +++ /dev/null @@ -1,368 +0,0 @@ -#[doc = "Register `FILT` reader"] -pub type R = crate::R; -#[doc = "Register `FILT` writer"] -pub type W = crate::W; -#[doc = "Field `FILTSEL1` reader - Filter 1 Pin Select"] -pub type Filtsel1R = crate::FieldReader; -#[doc = "Field `FILTSEL1` writer - Filter 1 Pin Select"] -pub type Filtsel1W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Filter 1 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Filte1 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (Detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (Detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (Detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Filte1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Filte1 { - type Ux = u8; -} -impl crate::IsEnum for Filte1 {} -#[doc = "Field `FILTE1` reader - Filter 1 Enable"] -pub type Filte1R = crate::FieldReader; -impl Filte1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filte1 { - match self.bits { - 0 => Filte1::Disable, - 1 => Filte1::EnRiseHi, - 2 => Filte1::EnFallLo, - 3 => Filte1::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Filte1::Disable - } - #[doc = "Enable (Detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Filte1::EnRiseHi - } - #[doc = "Enable (Detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Filte1::EnFallLo - } - #[doc = "Enable (Detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Filte1::EnAny - } -} -#[doc = "Field `FILTE1` writer - Filter 1 Enable"] -pub type Filte1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filte1, crate::Safe>; -impl<'a, REG> Filte1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Filte1::Disable) - } - #[doc = "Enable (Detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Filte1::EnRiseHi) - } - #[doc = "Enable (Detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Filte1::EnFallLo) - } - #[doc = "Enable (Detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Filte1::EnAny) - } -} -#[doc = "Filter 1 Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Filtf1 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Filtf1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILTF1` reader - Filter 1 Flag"] -pub type Filtf1R = crate::BitReader; -impl Filtf1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filtf1 { - match self.bits { - false => Filtf1::NoFlag, - true => Filtf1::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Filtf1::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Filtf1::Flag - } -} -#[doc = "Field `FILTF1` writer - Filter 1 Flag"] -pub type Filtf1W<'a, REG> = crate::BitWriter1C<'a, REG, Filtf1>; -impl<'a, REG> Filtf1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Filtf1::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Filtf1::Flag) - } -} -#[doc = "Field `FILTSEL2` reader - Filter 2 Pin Select"] -pub type Filtsel2R = crate::FieldReader; -#[doc = "Field `FILTSEL2` writer - Filter 2 Pin Select"] -pub type Filtsel2W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Filter 2 Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Filte2 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (Detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (Detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (Detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Filte2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Filte2 { - type Ux = u8; -} -impl crate::IsEnum for Filte2 {} -#[doc = "Field `FILTE2` reader - Filter 2 Enable"] -pub type Filte2R = crate::FieldReader; -impl Filte2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filte2 { - match self.bits { - 0 => Filte2::Disable, - 1 => Filte2::EnRiseHi, - 2 => Filte2::EnFallLo, - 3 => Filte2::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Filte2::Disable - } - #[doc = "Enable (Detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Filte2::EnRiseHi - } - #[doc = "Enable (Detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Filte2::EnFallLo - } - #[doc = "Enable (Detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Filte2::EnAny - } -} -#[doc = "Field `FILTE2` writer - Filter 2 Enable"] -pub type Filte2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Filte2, crate::Safe>; -impl<'a, REG> Filte2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Filte2::Disable) - } - #[doc = "Enable (Detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Filte2::EnRiseHi) - } - #[doc = "Enable (Detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Filte2::EnFallLo) - } - #[doc = "Enable (Detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Filte2::EnAny) - } -} -#[doc = "Filter 2 Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Filtf2 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Filtf2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILTF2` reader - Filter 2 Flag"] -pub type Filtf2R = crate::BitReader; -impl Filtf2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filtf2 { - match self.bits { - false => Filtf2::NoFlag, - true => Filtf2::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Filtf2::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Filtf2::Flag - } -} -#[doc = "Field `FILTF2` writer - Filter 2 Flag"] -pub type Filtf2W<'a, REG> = crate::BitWriter1C<'a, REG, Filtf2>; -impl<'a, REG> Filtf2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Filtf2::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Filtf2::Flag) - } -} -impl R { - #[doc = "Bits 0:4 - Filter 1 Pin Select"] - #[inline(always)] - pub fn filtsel1(&self) -> Filtsel1R { - Filtsel1R::new((self.bits & 0x1f) as u8) - } - #[doc = "Bits 5:6 - Filter 1 Enable"] - #[inline(always)] - pub fn filte1(&self) -> Filte1R { - Filte1R::new(((self.bits >> 5) & 3) as u8) - } - #[doc = "Bit 7 - Filter 1 Flag"] - #[inline(always)] - pub fn filtf1(&self) -> Filtf1R { - Filtf1R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:12 - Filter 2 Pin Select"] - #[inline(always)] - pub fn filtsel2(&self) -> Filtsel2R { - Filtsel2R::new(((self.bits >> 8) & 0x1f) as u8) - } - #[doc = "Bits 13:14 - Filter 2 Enable"] - #[inline(always)] - pub fn filte2(&self) -> Filte2R { - Filte2R::new(((self.bits >> 13) & 3) as u8) - } - #[doc = "Bit 15 - Filter 2 Flag"] - #[inline(always)] - pub fn filtf2(&self) -> Filtf2R { - Filtf2R::new(((self.bits >> 15) & 1) != 0) - } -} -impl W { - #[doc = "Bits 0:4 - Filter 1 Pin Select"] - #[inline(always)] - pub fn filtsel1(&mut self) -> Filtsel1W { - Filtsel1W::new(self, 0) - } - #[doc = "Bits 5:6 - Filter 1 Enable"] - #[inline(always)] - pub fn filte1(&mut self) -> Filte1W { - Filte1W::new(self, 5) - } - #[doc = "Bit 7 - Filter 1 Flag"] - #[inline(always)] - pub fn filtf1(&mut self) -> Filtf1W { - Filtf1W::new(self, 7) - } - #[doc = "Bits 8:12 - Filter 2 Pin Select"] - #[inline(always)] - pub fn filtsel2(&mut self) -> Filtsel2W { - Filtsel2W::new(self, 8) - } - #[doc = "Bits 13:14 - Filter 2 Enable"] - #[inline(always)] - pub fn filte2(&mut self) -> Filte2W { - Filte2W::new(self, 13) - } - #[doc = "Bit 15 - Filter 2 Flag"] - #[inline(always)] - pub fn filtf2(&mut self) -> Filtf2W { - Filtf2W::new(self, 15) - } -} -#[doc = "Pin Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`filt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FiltSpec; -impl crate::RegisterSpec for FiltSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`filt::R`](R) reader structure"] -impl crate::Readable for FiltSpec {} -#[doc = "`write(|w| ..)` method takes [`filt::W`](W) writer structure"] -impl crate::Writable for FiltSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8080; -} -#[doc = "`reset()` method sets FILT to value 0"] -impl crate::Resettable for FiltSpec {} diff --git a/mcxa276-pac/src/wuu0/fmc.rs b/mcxa276-pac/src/wuu0/fmc.rs deleted file mode 100644 index 791a02c04..000000000 --- a/mcxa276-pac/src/wuu0/fmc.rs +++ /dev/null @@ -1,147 +0,0 @@ -#[doc = "Register `FMC` reader"] -pub type R = crate::R; -#[doc = "Register `FMC` writer"] -pub type W = crate::W; -#[doc = "Filter Mode for FILTn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Filtm1 { - #[doc = "0: Active only during Power Down/Deep Power Down mode"] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes"] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Filtm1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILTM1` reader - Filter Mode for FILTn"] -pub type Filtm1R = crate::BitReader; -impl Filtm1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filtm1 { - match self.bits { - false => Filtm1::LowPwrOnly, - true => Filtm1::AnyPwr, - } - } - #[doc = "Active only during Power Down/Deep Power Down mode"] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Filtm1::LowPwrOnly - } - #[doc = "Active during all power modes"] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Filtm1::AnyPwr - } -} -#[doc = "Field `FILTM1` writer - Filter Mode for FILTn"] -pub type Filtm1W<'a, REG> = crate::BitWriter<'a, REG, Filtm1>; -impl<'a, REG> Filtm1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during Power Down/Deep Power Down mode"] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Filtm1::LowPwrOnly) - } - #[doc = "Active during all power modes"] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Filtm1::AnyPwr) - } -} -#[doc = "Filter Mode for FILTn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Filtm2 { - #[doc = "0: Active only during Power Down/Deep Power Down mode"] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes"] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Filtm2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `FILTM2` reader - Filter Mode for FILTn"] -pub type Filtm2R = crate::BitReader; -impl Filtm2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Filtm2 { - match self.bits { - false => Filtm2::LowPwrOnly, - true => Filtm2::AnyPwr, - } - } - #[doc = "Active only during Power Down/Deep Power Down mode"] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Filtm2::LowPwrOnly - } - #[doc = "Active during all power modes"] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Filtm2::AnyPwr - } -} -#[doc = "Field `FILTM2` writer - Filter Mode for FILTn"] -pub type Filtm2W<'a, REG> = crate::BitWriter<'a, REG, Filtm2>; -impl<'a, REG> Filtm2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during Power Down/Deep Power Down mode"] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Filtm2::LowPwrOnly) - } - #[doc = "Active during all power modes"] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Filtm2::AnyPwr) - } -} -impl R { - #[doc = "Bit 0 - Filter Mode for FILTn"] - #[inline(always)] - pub fn filtm1(&self) -> Filtm1R { - Filtm1R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Filter Mode for FILTn"] - #[inline(always)] - pub fn filtm2(&self) -> Filtm2R { - Filtm2R::new(((self.bits >> 1) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Filter Mode for FILTn"] - #[inline(always)] - pub fn filtm1(&mut self) -> Filtm1W { - Filtm1W::new(self, 0) - } - #[doc = "Bit 1 - Filter Mode for FILTn"] - #[inline(always)] - pub fn filtm2(&mut self) -> Filtm2W { - Filtm2W::new(self, 1) - } -} -#[doc = "Pin Filter Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`fmc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fmc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FmcSpec; -impl crate::RegisterSpec for FmcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`fmc::R`](R) reader structure"] -impl crate::Readable for FmcSpec {} -#[doc = "`write(|w| ..)` method takes [`fmc::W`](W) writer structure"] -impl crate::Writable for FmcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FMC to value 0"] -impl crate::Resettable for FmcSpec {} diff --git a/mcxa276-pac/src/wuu0/me.rs b/mcxa276-pac/src/wuu0/me.rs deleted file mode 100644 index ed940e80f..000000000 --- a/mcxa276-pac/src/wuu0/me.rs +++ /dev/null @@ -1,399 +0,0 @@ -#[doc = "Register `ME` reader"] -pub type R = crate::R; -#[doc = "Register `ME` writer"] -pub type W = crate::W; -#[doc = "Module Interrupt Wake-up Enable for Module 0\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wume0 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wume0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUME0` reader - Module Interrupt Wake-up Enable for Module 0"] -pub type Wume0R = crate::BitReader; -impl Wume0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wume0 { - match self.bits { - false => Wume0::Disable, - true => Wume0::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wume0::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wume0::Enable - } -} -#[doc = "Field `WUME0` writer - Module Interrupt Wake-up Enable for Module 0"] -pub type Wume0W<'a, REG> = crate::BitWriter<'a, REG, Wume0>; -impl<'a, REG> Wume0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wume0::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wume0::Enable) - } -} -#[doc = "Module Interrupt Wake-up Enable for Module 1\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wume1 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wume1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUME1` reader - Module Interrupt Wake-up Enable for Module 1"] -pub type Wume1R = crate::BitReader; -impl Wume1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wume1 { - match self.bits { - false => Wume1::Disable, - true => Wume1::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wume1::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wume1::Enable - } -} -#[doc = "Field `WUME1` writer - Module Interrupt Wake-up Enable for Module 1"] -pub type Wume1W<'a, REG> = crate::BitWriter<'a, REG, Wume1>; -impl<'a, REG> Wume1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wume1::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wume1::Enable) - } -} -#[doc = "Module Interrupt Wake-up Enable for Module 2\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wume2 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wume2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUME2` reader - Module Interrupt Wake-up Enable for Module 2"] -pub type Wume2R = crate::BitReader; -impl Wume2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wume2 { - match self.bits { - false => Wume2::Disable, - true => Wume2::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wume2::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wume2::Enable - } -} -#[doc = "Field `WUME2` writer - Module Interrupt Wake-up Enable for Module 2"] -pub type Wume2W<'a, REG> = crate::BitWriter<'a, REG, Wume2>; -impl<'a, REG> Wume2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wume2::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wume2::Enable) - } -} -#[doc = "Module Interrupt Wake-up Enable for Module 3\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wume3 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wume3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUME3` reader - Module Interrupt Wake-up Enable for Module 3"] -pub type Wume3R = crate::BitReader; -impl Wume3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wume3 { - match self.bits { - false => Wume3::Disable, - true => Wume3::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wume3::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wume3::Enable - } -} -#[doc = "Field `WUME3` writer - Module Interrupt Wake-up Enable for Module 3"] -pub type Wume3W<'a, REG> = crate::BitWriter<'a, REG, Wume3>; -impl<'a, REG> Wume3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wume3::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wume3::Enable) - } -} -#[doc = "Module Interrupt Wake-up Enable for Module 6\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wume6 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wume6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUME6` reader - Module Interrupt Wake-up Enable for Module 6"] -pub type Wume6R = crate::BitReader; -impl Wume6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wume6 { - match self.bits { - false => Wume6::Disable, - true => Wume6::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wume6::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wume6::Enable - } -} -#[doc = "Field `WUME6` writer - Module Interrupt Wake-up Enable for Module 6"] -pub type Wume6W<'a, REG> = crate::BitWriter<'a, REG, Wume6>; -impl<'a, REG> Wume6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wume6::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wume6::Enable) - } -} -#[doc = "Module Interrupt Wake-up Enable for Module 8\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wume8 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wume8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUME8` reader - Module Interrupt Wake-up Enable for Module 8"] -pub type Wume8R = crate::BitReader; -impl Wume8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wume8 { - match self.bits { - false => Wume8::Disable, - true => Wume8::Enable, - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wume8::Disable - } - #[doc = "Enable"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == Wume8::Enable - } -} -#[doc = "Field `WUME8` writer - Module Interrupt Wake-up Enable for Module 8"] -pub type Wume8W<'a, REG> = crate::BitWriter<'a, REG, Wume8>; -impl<'a, REG> Wume8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wume8::Disable) - } - #[doc = "Enable"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(Wume8::Enable) - } -} -impl R { - #[doc = "Bit 0 - Module Interrupt Wake-up Enable for Module 0"] - #[inline(always)] - pub fn wume0(&self) -> Wume0R { - Wume0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Module Interrupt Wake-up Enable for Module 1"] - #[inline(always)] - pub fn wume1(&self) -> Wume1R { - Wume1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Module Interrupt Wake-up Enable for Module 2"] - #[inline(always)] - pub fn wume2(&self) -> Wume2R { - Wume2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Module Interrupt Wake-up Enable for Module 3"] - #[inline(always)] - pub fn wume3(&self) -> Wume3R { - Wume3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 6 - Module Interrupt Wake-up Enable for Module 6"] - #[inline(always)] - pub fn wume6(&self) -> Wume6R { - Wume6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 8 - Module Interrupt Wake-up Enable for Module 8"] - #[inline(always)] - pub fn wume8(&self) -> Wume8R { - Wume8R::new(((self.bits >> 8) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Module Interrupt Wake-up Enable for Module 0"] - #[inline(always)] - pub fn wume0(&mut self) -> Wume0W { - Wume0W::new(self, 0) - } - #[doc = "Bit 1 - Module Interrupt Wake-up Enable for Module 1"] - #[inline(always)] - pub fn wume1(&mut self) -> Wume1W { - Wume1W::new(self, 1) - } - #[doc = "Bit 2 - Module Interrupt Wake-up Enable for Module 2"] - #[inline(always)] - pub fn wume2(&mut self) -> Wume2W { - Wume2W::new(self, 2) - } - #[doc = "Bit 3 - Module Interrupt Wake-up Enable for Module 3"] - #[inline(always)] - pub fn wume3(&mut self) -> Wume3W { - Wume3W::new(self, 3) - } - #[doc = "Bit 6 - Module Interrupt Wake-up Enable for Module 6"] - #[inline(always)] - pub fn wume6(&mut self) -> Wume6W { - Wume6W::new(self, 6) - } - #[doc = "Bit 8 - Module Interrupt Wake-up Enable for Module 8"] - #[inline(always)] - pub fn wume8(&mut self) -> Wume8W { - Wume8W::new(self, 8) - } -} -#[doc = "Module Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`me::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`me::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MeSpec; -impl crate::RegisterSpec for MeSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`me::R`](R) reader structure"] -impl crate::Readable for MeSpec {} -#[doc = "`write(|w| ..)` method takes [`me::W`](W) writer structure"] -impl crate::Writable for MeSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets ME to value 0"] -impl crate::Resettable for MeSpec {} diff --git a/mcxa276-pac/src/wuu0/param.rs b/mcxa276-pac/src/wuu0/param.rs deleted file mode 100644 index 579cd821a..000000000 --- a/mcxa276-pac/src/wuu0/param.rs +++ /dev/null @@ -1,43 +0,0 @@ -#[doc = "Register `PARAM` reader"] -pub type R = crate::R; -#[doc = "Field `FILTERS` reader - Filter Number"] -pub type FiltersR = crate::FieldReader; -#[doc = "Field `DMAS` reader - DMA Number"] -pub type DmasR = crate::FieldReader; -#[doc = "Field `MODULES` reader - Module Number"] -pub type ModulesR = crate::FieldReader; -#[doc = "Field `PINS` reader - Pin Number"] -pub type PinsR = crate::FieldReader; -impl R { - #[doc = "Bits 0:7 - Filter Number"] - #[inline(always)] - pub fn filters(&self) -> FiltersR { - FiltersR::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - DMA Number"] - #[inline(always)] - pub fn dmas(&self) -> DmasR { - DmasR::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Module Number"] - #[inline(always)] - pub fn modules(&self) -> ModulesR { - ModulesR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Pin Number"] - #[inline(always)] - pub fn pins(&self) -> PinsR { - PinsR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Parameter\n\nYou can [`read`](crate::Reg::read) this register and get [`param::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ParamSpec; -impl crate::RegisterSpec for ParamSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`param::R`](R) reader structure"] -impl crate::Readable for ParamSpec {} -#[doc = "`reset()` method sets PARAM to value 0x2020_2002"] -impl crate::Resettable for ParamSpec { - const RESET_VALUE: u32 = 0x2020_2002; -} diff --git a/mcxa276-pac/src/wuu0/pdc1.rs b/mcxa276-pac/src/wuu0/pdc1.rs deleted file mode 100644 index 2e5fcb236..000000000 --- a/mcxa276-pac/src/wuu0/pdc1.rs +++ /dev/null @@ -1,1557 +0,0 @@ -#[doc = "Register `PDC1` reader"] -pub type R = crate::R; -#[doc = "Register `PDC1` writer"] -pub type W = crate::W; -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc0 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc0 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc0 {} -#[doc = "Field `WUPDC0` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc0R = crate::FieldReader; -impl Wupdc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc0 { - match self.bits { - 0 => Wupdc0::Interrupt, - 1 => Wupdc0::DmaReq, - 2 => Wupdc0::Trigger, - 3 => Wupdc0::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc0::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc0::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc0::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc0::Res - } -} -#[doc = "Field `WUPDC0` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc0, crate::Safe>; -impl<'a, REG> Wupdc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc0::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc0::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc0::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc0::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc1 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc1 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc1 {} -#[doc = "Field `WUPDC1` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc1R = crate::FieldReader; -impl Wupdc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc1 { - match self.bits { - 0 => Wupdc1::Interrupt, - 1 => Wupdc1::DmaReq, - 2 => Wupdc1::Trigger, - 3 => Wupdc1::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc1::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc1::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc1::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc1::Res - } -} -#[doc = "Field `WUPDC1` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc1, crate::Safe>; -impl<'a, REG> Wupdc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc1::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc1::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc1::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc1::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc2 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc2 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc2 {} -#[doc = "Field `WUPDC2` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc2R = crate::FieldReader; -impl Wupdc2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc2 { - match self.bits { - 0 => Wupdc2::Interrupt, - 1 => Wupdc2::DmaReq, - 2 => Wupdc2::Trigger, - 3 => Wupdc2::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc2::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc2::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc2::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc2::Res - } -} -#[doc = "Field `WUPDC2` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc2, crate::Safe>; -impl<'a, REG> Wupdc2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc2::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc2::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc2::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc2::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc3 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc3 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc3 {} -#[doc = "Field `WUPDC3` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc3R = crate::FieldReader; -impl Wupdc3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc3 { - match self.bits { - 0 => Wupdc3::Interrupt, - 1 => Wupdc3::DmaReq, - 2 => Wupdc3::Trigger, - 3 => Wupdc3::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc3::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc3::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc3::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc3::Res - } -} -#[doc = "Field `WUPDC3` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc3W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc3, crate::Safe>; -impl<'a, REG> Wupdc3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc3::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc3::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc3::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc3::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc4 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc4 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc4 {} -#[doc = "Field `WUPDC4` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc4R = crate::FieldReader; -impl Wupdc4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc4 { - match self.bits { - 0 => Wupdc4::Interrupt, - 1 => Wupdc4::DmaReq, - 2 => Wupdc4::Trigger, - 3 => Wupdc4::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc4::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc4::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc4::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc4::Res - } -} -#[doc = "Field `WUPDC4` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc4W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc4, crate::Safe>; -impl<'a, REG> Wupdc4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc4::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc4::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc4::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc4::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc5 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc5 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc5 {} -#[doc = "Field `WUPDC5` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc5R = crate::FieldReader; -impl Wupdc5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc5 { - match self.bits { - 0 => Wupdc5::Interrupt, - 1 => Wupdc5::DmaReq, - 2 => Wupdc5::Trigger, - 3 => Wupdc5::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc5::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc5::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc5::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc5::Res - } -} -#[doc = "Field `WUPDC5` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc5W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc5, crate::Safe>; -impl<'a, REG> Wupdc5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc5::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc5::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc5::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc5::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc6 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc6 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc6 {} -#[doc = "Field `WUPDC6` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc6R = crate::FieldReader; -impl Wupdc6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc6 { - match self.bits { - 0 => Wupdc6::Interrupt, - 1 => Wupdc6::DmaReq, - 2 => Wupdc6::Trigger, - 3 => Wupdc6::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc6::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc6::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc6::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc6::Res - } -} -#[doc = "Field `WUPDC6` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc6W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc6, crate::Safe>; -impl<'a, REG> Wupdc6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc6::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc6::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc6::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc6::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc7 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc7 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc7 {} -#[doc = "Field `WUPDC7` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc7R = crate::FieldReader; -impl Wupdc7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc7 { - match self.bits { - 0 => Wupdc7::Interrupt, - 1 => Wupdc7::DmaReq, - 2 => Wupdc7::Trigger, - 3 => Wupdc7::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc7::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc7::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc7::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc7::Res - } -} -#[doc = "Field `WUPDC7` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc7W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc7, crate::Safe>; -impl<'a, REG> Wupdc7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc7::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc7::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc7::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc7::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc8 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc8) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc8 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc8 {} -#[doc = "Field `WUPDC8` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc8R = crate::FieldReader; -impl Wupdc8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc8 { - match self.bits { - 0 => Wupdc8::Interrupt, - 1 => Wupdc8::DmaReq, - 2 => Wupdc8::Trigger, - 3 => Wupdc8::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc8::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc8::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc8::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc8::Res - } -} -#[doc = "Field `WUPDC8` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc8W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc8, crate::Safe>; -impl<'a, REG> Wupdc8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc8::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc8::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc8::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc8::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc9 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc9) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc9 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc9 {} -#[doc = "Field `WUPDC9` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc9R = crate::FieldReader; -impl Wupdc9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc9 { - match self.bits { - 0 => Wupdc9::Interrupt, - 1 => Wupdc9::DmaReq, - 2 => Wupdc9::Trigger, - 3 => Wupdc9::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc9::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc9::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc9::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc9::Res - } -} -#[doc = "Field `WUPDC9` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc9W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc9, crate::Safe>; -impl<'a, REG> Wupdc9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc9::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc9::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc9::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc9::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc10 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc10) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc10 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc10 {} -#[doc = "Field `WUPDC10` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc10R = crate::FieldReader; -impl Wupdc10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc10 { - match self.bits { - 0 => Wupdc10::Interrupt, - 1 => Wupdc10::DmaReq, - 2 => Wupdc10::Trigger, - 3 => Wupdc10::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc10::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc10::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc10::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc10::Res - } -} -#[doc = "Field `WUPDC10` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc10W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc10, crate::Safe>; -impl<'a, REG> Wupdc10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc10::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc10::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc10::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc10::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc11 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc11) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc11 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc11 {} -#[doc = "Field `WUPDC11` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc11R = crate::FieldReader; -impl Wupdc11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc11 { - match self.bits { - 0 => Wupdc11::Interrupt, - 1 => Wupdc11::DmaReq, - 2 => Wupdc11::Trigger, - 3 => Wupdc11::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc11::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc11::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc11::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc11::Res - } -} -#[doc = "Field `WUPDC11` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc11W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc11, crate::Safe>; -impl<'a, REG> Wupdc11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc11::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc11::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc11::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc11::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc12 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc12) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc12 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc12 {} -#[doc = "Field `WUPDC12` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc12R = crate::FieldReader; -impl Wupdc12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc12 { - match self.bits { - 0 => Wupdc12::Interrupt, - 1 => Wupdc12::DmaReq, - 2 => Wupdc12::Trigger, - 3 => Wupdc12::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc12::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc12::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc12::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc12::Res - } -} -#[doc = "Field `WUPDC12` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc12W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc12, crate::Safe>; -impl<'a, REG> Wupdc12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc12::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc12::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc12::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc12::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc13 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc13) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc13 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc13 {} -#[doc = "Field `WUPDC13` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc13R = crate::FieldReader; -impl Wupdc13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc13 { - match self.bits { - 0 => Wupdc13::Interrupt, - 1 => Wupdc13::DmaReq, - 2 => Wupdc13::Trigger, - 3 => Wupdc13::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc13::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc13::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc13::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc13::Res - } -} -#[doc = "Field `WUPDC13` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc13W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc13, crate::Safe>; -impl<'a, REG> Wupdc13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc13::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc13::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc13::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc13::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc14 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc14) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc14 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc14 {} -#[doc = "Field `WUPDC14` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc14R = crate::FieldReader; -impl Wupdc14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc14 { - match self.bits { - 0 => Wupdc14::Interrupt, - 1 => Wupdc14::DmaReq, - 2 => Wupdc14::Trigger, - 3 => Wupdc14::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc14::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc14::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc14::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc14::Res - } -} -#[doc = "Field `WUPDC14` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc14W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc14, crate::Safe>; -impl<'a, REG> Wupdc14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc14::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc14::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc14::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc14::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc15 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc15) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc15 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc15 {} -#[doc = "Field `WUPDC15` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc15R = crate::FieldReader; -impl Wupdc15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc15 { - match self.bits { - 0 => Wupdc15::Interrupt, - 1 => Wupdc15::DmaReq, - 2 => Wupdc15::Trigger, - 3 => Wupdc15::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc15::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc15::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc15::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc15::Res - } -} -#[doc = "Field `WUPDC15` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc15W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc15, crate::Safe>; -impl<'a, REG> Wupdc15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc15::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc15::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc15::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc15::Res) - } -} -impl R { - #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc0(&self) -> Wupdc0R { - Wupdc0R::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc1(&self) -> Wupdc1R { - Wupdc1R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc2(&self) -> Wupdc2R { - Wupdc2R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc3(&self) -> Wupdc3R { - Wupdc3R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc4(&self) -> Wupdc4R { - Wupdc4R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc5(&self) -> Wupdc5R { - Wupdc5R::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc6(&self) -> Wupdc6R { - Wupdc6R::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc7(&self) -> Wupdc7R { - Wupdc7R::new(((self.bits >> 14) & 3) as u8) - } - #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc8(&self) -> Wupdc8R { - Wupdc8R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc9(&self) -> Wupdc9R { - Wupdc9R::new(((self.bits >> 18) & 3) as u8) - } - #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc10(&self) -> Wupdc10R { - Wupdc10R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc11(&self) -> Wupdc11R { - Wupdc11R::new(((self.bits >> 22) & 3) as u8) - } - #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc12(&self) -> Wupdc12R { - Wupdc12R::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc13(&self) -> Wupdc13R { - Wupdc13R::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc14(&self) -> Wupdc14R { - Wupdc14R::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc15(&self) -> Wupdc15R { - Wupdc15R::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc0(&mut self) -> Wupdc0W { - Wupdc0W::new(self, 0) - } - #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc1(&mut self) -> Wupdc1W { - Wupdc1W::new(self, 2) - } - #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc2(&mut self) -> Wupdc2W { - Wupdc2W::new(self, 4) - } - #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc3(&mut self) -> Wupdc3W { - Wupdc3W::new(self, 6) - } - #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc4(&mut self) -> Wupdc4W { - Wupdc4W::new(self, 8) - } - #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc5(&mut self) -> Wupdc5W { - Wupdc5W::new(self, 10) - } - #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc6(&mut self) -> Wupdc6W { - Wupdc6W::new(self, 12) - } - #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc7(&mut self) -> Wupdc7W { - Wupdc7W::new(self, 14) - } - #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc8(&mut self) -> Wupdc8W { - Wupdc8W::new(self, 16) - } - #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc9(&mut self) -> Wupdc9W { - Wupdc9W::new(self, 18) - } - #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc10(&mut self) -> Wupdc10W { - Wupdc10W::new(self, 20) - } - #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc11(&mut self) -> Wupdc11W { - Wupdc11W::new(self, 22) - } - #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc12(&mut self) -> Wupdc12W { - Wupdc12W::new(self, 24) - } - #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc13(&mut self) -> Wupdc13W { - Wupdc13W::new(self, 26) - } - #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc14(&mut self) -> Wupdc14W { - Wupdc14W::new(self, 28) - } - #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc15(&mut self) -> Wupdc15W { - Wupdc15W::new(self, 30) - } -} -#[doc = "Pin DMA/Trigger Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pdc1Spec; -impl crate::RegisterSpec for Pdc1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pdc1::R`](R) reader structure"] -impl crate::Readable for Pdc1Spec {} -#[doc = "`write(|w| ..)` method takes [`pdc1::W`](W) writer structure"] -impl crate::Writable for Pdc1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PDC1 to value 0"] -impl crate::Resettable for Pdc1Spec {} diff --git a/mcxa276-pac/src/wuu0/pdc2.rs b/mcxa276-pac/src/wuu0/pdc2.rs deleted file mode 100644 index edbf74576..000000000 --- a/mcxa276-pac/src/wuu0/pdc2.rs +++ /dev/null @@ -1,1557 +0,0 @@ -#[doc = "Register `PDC2` reader"] -pub type R = crate::R; -#[doc = "Register `PDC2` writer"] -pub type W = crate::W; -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc16 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc16) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc16 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc16 {} -#[doc = "Field `WUPDC16` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc16R = crate::FieldReader; -impl Wupdc16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc16 { - match self.bits { - 0 => Wupdc16::Interrupt, - 1 => Wupdc16::DmaReq, - 2 => Wupdc16::Trigger, - 3 => Wupdc16::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc16::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc16::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc16::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc16::Res - } -} -#[doc = "Field `WUPDC16` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc16W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc16, crate::Safe>; -impl<'a, REG> Wupdc16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc16::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc16::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc16::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc16::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc17 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc17) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc17 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc17 {} -#[doc = "Field `WUPDC17` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc17R = crate::FieldReader; -impl Wupdc17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc17 { - match self.bits { - 0 => Wupdc17::Interrupt, - 1 => Wupdc17::DmaReq, - 2 => Wupdc17::Trigger, - 3 => Wupdc17::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc17::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc17::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc17::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc17::Res - } -} -#[doc = "Field `WUPDC17` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc17W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc17, crate::Safe>; -impl<'a, REG> Wupdc17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc17::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc17::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc17::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc17::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc18 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc18) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc18 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc18 {} -#[doc = "Field `WUPDC18` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc18R = crate::FieldReader; -impl Wupdc18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc18 { - match self.bits { - 0 => Wupdc18::Interrupt, - 1 => Wupdc18::DmaReq, - 2 => Wupdc18::Trigger, - 3 => Wupdc18::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc18::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc18::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc18::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc18::Res - } -} -#[doc = "Field `WUPDC18` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc18W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc18, crate::Safe>; -impl<'a, REG> Wupdc18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc18::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc18::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc18::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc18::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc19 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc19) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc19 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc19 {} -#[doc = "Field `WUPDC19` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc19R = crate::FieldReader; -impl Wupdc19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc19 { - match self.bits { - 0 => Wupdc19::Interrupt, - 1 => Wupdc19::DmaReq, - 2 => Wupdc19::Trigger, - 3 => Wupdc19::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc19::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc19::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc19::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc19::Res - } -} -#[doc = "Field `WUPDC19` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc19W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc19, crate::Safe>; -impl<'a, REG> Wupdc19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc19::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc19::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc19::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc19::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc20 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc20) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc20 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc20 {} -#[doc = "Field `WUPDC20` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc20R = crate::FieldReader; -impl Wupdc20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc20 { - match self.bits { - 0 => Wupdc20::Interrupt, - 1 => Wupdc20::DmaReq, - 2 => Wupdc20::Trigger, - 3 => Wupdc20::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc20::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc20::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc20::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc20::Res - } -} -#[doc = "Field `WUPDC20` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc20W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc20, crate::Safe>; -impl<'a, REG> Wupdc20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc20::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc20::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc20::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc20::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc21 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc21) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc21 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc21 {} -#[doc = "Field `WUPDC21` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc21R = crate::FieldReader; -impl Wupdc21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc21 { - match self.bits { - 0 => Wupdc21::Interrupt, - 1 => Wupdc21::DmaReq, - 2 => Wupdc21::Trigger, - 3 => Wupdc21::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc21::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc21::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc21::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc21::Res - } -} -#[doc = "Field `WUPDC21` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc21W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc21, crate::Safe>; -impl<'a, REG> Wupdc21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc21::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc21::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc21::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc21::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc22 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc22) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc22 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc22 {} -#[doc = "Field `WUPDC22` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc22R = crate::FieldReader; -impl Wupdc22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc22 { - match self.bits { - 0 => Wupdc22::Interrupt, - 1 => Wupdc22::DmaReq, - 2 => Wupdc22::Trigger, - 3 => Wupdc22::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc22::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc22::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc22::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc22::Res - } -} -#[doc = "Field `WUPDC22` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc22W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc22, crate::Safe>; -impl<'a, REG> Wupdc22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc22::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc22::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc22::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc22::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc23 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc23) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc23 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc23 {} -#[doc = "Field `WUPDC23` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc23R = crate::FieldReader; -impl Wupdc23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc23 { - match self.bits { - 0 => Wupdc23::Interrupt, - 1 => Wupdc23::DmaReq, - 2 => Wupdc23::Trigger, - 3 => Wupdc23::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc23::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc23::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc23::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc23::Res - } -} -#[doc = "Field `WUPDC23` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc23, crate::Safe>; -impl<'a, REG> Wupdc23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc23::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc23::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc23::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc23::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc24 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc24) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc24 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc24 {} -#[doc = "Field `WUPDC24` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc24R = crate::FieldReader; -impl Wupdc24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc24 { - match self.bits { - 0 => Wupdc24::Interrupt, - 1 => Wupdc24::DmaReq, - 2 => Wupdc24::Trigger, - 3 => Wupdc24::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc24::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc24::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc24::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc24::Res - } -} -#[doc = "Field `WUPDC24` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc24W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc24, crate::Safe>; -impl<'a, REG> Wupdc24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc24::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc24::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc24::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc24::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc25 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc25) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc25 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc25 {} -#[doc = "Field `WUPDC25` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc25R = crate::FieldReader; -impl Wupdc25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc25 { - match self.bits { - 0 => Wupdc25::Interrupt, - 1 => Wupdc25::DmaReq, - 2 => Wupdc25::Trigger, - 3 => Wupdc25::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc25::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc25::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc25::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc25::Res - } -} -#[doc = "Field `WUPDC25` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc25W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc25, crate::Safe>; -impl<'a, REG> Wupdc25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc25::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc25::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc25::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc25::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc26 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc26) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc26 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc26 {} -#[doc = "Field `WUPDC26` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc26R = crate::FieldReader; -impl Wupdc26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc26 { - match self.bits { - 0 => Wupdc26::Interrupt, - 1 => Wupdc26::DmaReq, - 2 => Wupdc26::Trigger, - 3 => Wupdc26::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc26::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc26::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc26::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc26::Res - } -} -#[doc = "Field `WUPDC26` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc26W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc26, crate::Safe>; -impl<'a, REG> Wupdc26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc26::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc26::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc26::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc26::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc27 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc27) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc27 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc27 {} -#[doc = "Field `WUPDC27` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc27R = crate::FieldReader; -impl Wupdc27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc27 { - match self.bits { - 0 => Wupdc27::Interrupt, - 1 => Wupdc27::DmaReq, - 2 => Wupdc27::Trigger, - 3 => Wupdc27::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc27::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc27::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc27::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc27::Res - } -} -#[doc = "Field `WUPDC27` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc27W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc27, crate::Safe>; -impl<'a, REG> Wupdc27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc27::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc27::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc27::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc27::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc28 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc28) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc28 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc28 {} -#[doc = "Field `WUPDC28` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc28R = crate::FieldReader; -impl Wupdc28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc28 { - match self.bits { - 0 => Wupdc28::Interrupt, - 1 => Wupdc28::DmaReq, - 2 => Wupdc28::Trigger, - 3 => Wupdc28::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc28::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc28::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc28::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc28::Res - } -} -#[doc = "Field `WUPDC28` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc28W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc28, crate::Safe>; -impl<'a, REG> Wupdc28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc28::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc28::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc28::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc28::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc29 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc29) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc29 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc29 {} -#[doc = "Field `WUPDC29` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc29R = crate::FieldReader; -impl Wupdc29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc29 { - match self.bits { - 0 => Wupdc29::Interrupt, - 1 => Wupdc29::DmaReq, - 2 => Wupdc29::Trigger, - 3 => Wupdc29::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc29::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc29::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc29::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc29::Res - } -} -#[doc = "Field `WUPDC29` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc29W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc29, crate::Safe>; -impl<'a, REG> Wupdc29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc29::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc29::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc29::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc29::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc30 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc30) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc30 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc30 {} -#[doc = "Field `WUPDC30` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc30R = crate::FieldReader; -impl Wupdc30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc30 { - match self.bits { - 0 => Wupdc30::Interrupt, - 1 => Wupdc30::DmaReq, - 2 => Wupdc30::Trigger, - 3 => Wupdc30::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc30::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc30::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc30::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc30::Res - } -} -#[doc = "Field `WUPDC30` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc30W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc30, crate::Safe>; -impl<'a, REG> Wupdc30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc30::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc30::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc30::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc30::Res) - } -} -#[doc = "Wake-up Pin Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupdc31 { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: DMA request"] - DmaReq = 1, - #[doc = "2: Trigger event"] - Trigger = 2, - #[doc = "3: Reserved"] - Res = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupdc31) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupdc31 { - type Ux = u8; -} -impl crate::IsEnum for Wupdc31 {} -#[doc = "Field `WUPDC31` reader - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc31R = crate::FieldReader; -impl Wupdc31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupdc31 { - match self.bits { - 0 => Wupdc31::Interrupt, - 1 => Wupdc31::DmaReq, - 2 => Wupdc31::Trigger, - 3 => Wupdc31::Res, - _ => unreachable!(), - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wupdc31::Interrupt - } - #[doc = "DMA request"] - #[inline(always)] - pub fn is_dma_req(&self) -> bool { - *self == Wupdc31::DmaReq - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn is_trigger(&self) -> bool { - *self == Wupdc31::Trigger - } - #[doc = "Reserved"] - #[inline(always)] - pub fn is_res(&self) -> bool { - *self == Wupdc31::Res - } -} -#[doc = "Field `WUPDC31` writer - Wake-up Pin Configuration for WUU_Pn"] -pub type Wupdc31W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupdc31, crate::Safe>; -impl<'a, REG> Wupdc31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wupdc31::Interrupt) - } - #[doc = "DMA request"] - #[inline(always)] - pub fn dma_req(self) -> &'a mut crate::W { - self.variant(Wupdc31::DmaReq) - } - #[doc = "Trigger event"] - #[inline(always)] - pub fn trigger(self) -> &'a mut crate::W { - self.variant(Wupdc31::Trigger) - } - #[doc = "Reserved"] - #[inline(always)] - pub fn res(self) -> &'a mut crate::W { - self.variant(Wupdc31::Res) - } -} -impl R { - #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc16(&self) -> Wupdc16R { - Wupdc16R::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc17(&self) -> Wupdc17R { - Wupdc17R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc18(&self) -> Wupdc18R { - Wupdc18R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc19(&self) -> Wupdc19R { - Wupdc19R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc20(&self) -> Wupdc20R { - Wupdc20R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc21(&self) -> Wupdc21R { - Wupdc21R::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc22(&self) -> Wupdc22R { - Wupdc22R::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc23(&self) -> Wupdc23R { - Wupdc23R::new(((self.bits >> 14) & 3) as u8) - } - #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc24(&self) -> Wupdc24R { - Wupdc24R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc25(&self) -> Wupdc25R { - Wupdc25R::new(((self.bits >> 18) & 3) as u8) - } - #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc26(&self) -> Wupdc26R { - Wupdc26R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc27(&self) -> Wupdc27R { - Wupdc27R::new(((self.bits >> 22) & 3) as u8) - } - #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc28(&self) -> Wupdc28R { - Wupdc28R::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc29(&self) -> Wupdc29R { - Wupdc29R::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc30(&self) -> Wupdc30R { - Wupdc30R::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc31(&self) -> Wupdc31R { - Wupdc31R::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc16(&mut self) -> Wupdc16W { - Wupdc16W::new(self, 0) - } - #[doc = "Bits 2:3 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc17(&mut self) -> Wupdc17W { - Wupdc17W::new(self, 2) - } - #[doc = "Bits 4:5 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc18(&mut self) -> Wupdc18W { - Wupdc18W::new(self, 4) - } - #[doc = "Bits 6:7 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc19(&mut self) -> Wupdc19W { - Wupdc19W::new(self, 6) - } - #[doc = "Bits 8:9 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc20(&mut self) -> Wupdc20W { - Wupdc20W::new(self, 8) - } - #[doc = "Bits 10:11 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc21(&mut self) -> Wupdc21W { - Wupdc21W::new(self, 10) - } - #[doc = "Bits 12:13 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc22(&mut self) -> Wupdc22W { - Wupdc22W::new(self, 12) - } - #[doc = "Bits 14:15 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc23(&mut self) -> Wupdc23W { - Wupdc23W::new(self, 14) - } - #[doc = "Bits 16:17 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc24(&mut self) -> Wupdc24W { - Wupdc24W::new(self, 16) - } - #[doc = "Bits 18:19 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc25(&mut self) -> Wupdc25W { - Wupdc25W::new(self, 18) - } - #[doc = "Bits 20:21 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc26(&mut self) -> Wupdc26W { - Wupdc26W::new(self, 20) - } - #[doc = "Bits 22:23 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc27(&mut self) -> Wupdc27W { - Wupdc27W::new(self, 22) - } - #[doc = "Bits 24:25 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc28(&mut self) -> Wupdc28W { - Wupdc28W::new(self, 24) - } - #[doc = "Bits 26:27 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc29(&mut self) -> Wupdc29W { - Wupdc29W::new(self, 26) - } - #[doc = "Bits 28:29 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc30(&mut self) -> Wupdc30W { - Wupdc30W::new(self, 28) - } - #[doc = "Bits 30:31 - Wake-up Pin Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupdc31(&mut self) -> Wupdc31W { - Wupdc31W::new(self, 30) - } -} -#[doc = "Pin DMA/Trigger Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pdc2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdc2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pdc2Spec; -impl crate::RegisterSpec for Pdc2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pdc2::R`](R) reader structure"] -impl crate::Readable for Pdc2Spec {} -#[doc = "`write(|w| ..)` method takes [`pdc2::W`](W) writer structure"] -impl crate::Writable for Pdc2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PDC2 to value 0"] -impl crate::Resettable for Pdc2Spec {} diff --git a/mcxa276-pac/src/wuu0/pe1.rs b/mcxa276-pac/src/wuu0/pe1.rs deleted file mode 100644 index 186cdb3fc..000000000 --- a/mcxa276-pac/src/wuu0/pe1.rs +++ /dev/null @@ -1,1557 +0,0 @@ -#[doc = "Register `PE1` reader"] -pub type R = crate::R; -#[doc = "Register `PE1` writer"] -pub type W = crate::W; -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe0 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe0) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe0 { - type Ux = u8; -} -impl crate::IsEnum for Wupe0 {} -#[doc = "Field `WUPE0` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe0R = crate::FieldReader; -impl Wupe0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe0 { - match self.bits { - 0 => Wupe0::Disable, - 1 => Wupe0::EnRiseHi, - 2 => Wupe0::EnFallLo, - 3 => Wupe0::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe0::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe0::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe0::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe0::EnAny - } -} -#[doc = "Field `WUPE0` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe0, crate::Safe>; -impl<'a, REG> Wupe0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe0::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe0::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe0::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe0::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe1 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe1) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe1 { - type Ux = u8; -} -impl crate::IsEnum for Wupe1 {} -#[doc = "Field `WUPE1` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe1R = crate::FieldReader; -impl Wupe1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe1 { - match self.bits { - 0 => Wupe1::Disable, - 1 => Wupe1::EnRiseHi, - 2 => Wupe1::EnFallLo, - 3 => Wupe1::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe1::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe1::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe1::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe1::EnAny - } -} -#[doc = "Field `WUPE1` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe1W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe1, crate::Safe>; -impl<'a, REG> Wupe1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe1::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe1::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe1::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe1::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe2 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe2) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe2 { - type Ux = u8; -} -impl crate::IsEnum for Wupe2 {} -#[doc = "Field `WUPE2` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe2R = crate::FieldReader; -impl Wupe2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe2 { - match self.bits { - 0 => Wupe2::Disable, - 1 => Wupe2::EnRiseHi, - 2 => Wupe2::EnFallLo, - 3 => Wupe2::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe2::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe2::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe2::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe2::EnAny - } -} -#[doc = "Field `WUPE2` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe2W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe2, crate::Safe>; -impl<'a, REG> Wupe2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe2::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe2::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe2::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe2::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe3 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe3) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe3 { - type Ux = u8; -} -impl crate::IsEnum for Wupe3 {} -#[doc = "Field `WUPE3` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe3R = crate::FieldReader; -impl Wupe3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe3 { - match self.bits { - 0 => Wupe3::Disable, - 1 => Wupe3::EnRiseHi, - 2 => Wupe3::EnFallLo, - 3 => Wupe3::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe3::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe3::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe3::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe3::EnAny - } -} -#[doc = "Field `WUPE3` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe3W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe3, crate::Safe>; -impl<'a, REG> Wupe3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe3::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe3::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe3::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe3::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe4 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe4) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe4 { - type Ux = u8; -} -impl crate::IsEnum for Wupe4 {} -#[doc = "Field `WUPE4` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe4R = crate::FieldReader; -impl Wupe4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe4 { - match self.bits { - 0 => Wupe4::Disable, - 1 => Wupe4::EnRiseHi, - 2 => Wupe4::EnFallLo, - 3 => Wupe4::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe4::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe4::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe4::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe4::EnAny - } -} -#[doc = "Field `WUPE4` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe4W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe4, crate::Safe>; -impl<'a, REG> Wupe4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe4::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe4::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe4::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe4::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe5 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe5) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe5 { - type Ux = u8; -} -impl crate::IsEnum for Wupe5 {} -#[doc = "Field `WUPE5` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe5R = crate::FieldReader; -impl Wupe5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe5 { - match self.bits { - 0 => Wupe5::Disable, - 1 => Wupe5::EnRiseHi, - 2 => Wupe5::EnFallLo, - 3 => Wupe5::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe5::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe5::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe5::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe5::EnAny - } -} -#[doc = "Field `WUPE5` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe5W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe5, crate::Safe>; -impl<'a, REG> Wupe5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe5::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe5::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe5::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe5::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe6 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe6) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe6 { - type Ux = u8; -} -impl crate::IsEnum for Wupe6 {} -#[doc = "Field `WUPE6` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe6R = crate::FieldReader; -impl Wupe6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe6 { - match self.bits { - 0 => Wupe6::Disable, - 1 => Wupe6::EnRiseHi, - 2 => Wupe6::EnFallLo, - 3 => Wupe6::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe6::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe6::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe6::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe6::EnAny - } -} -#[doc = "Field `WUPE6` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe6W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe6, crate::Safe>; -impl<'a, REG> Wupe6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe6::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe6::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe6::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe6::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe7 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe7) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe7 { - type Ux = u8; -} -impl crate::IsEnum for Wupe7 {} -#[doc = "Field `WUPE7` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe7R = crate::FieldReader; -impl Wupe7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe7 { - match self.bits { - 0 => Wupe7::Disable, - 1 => Wupe7::EnRiseHi, - 2 => Wupe7::EnFallLo, - 3 => Wupe7::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe7::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe7::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe7::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe7::EnAny - } -} -#[doc = "Field `WUPE7` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe7W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe7, crate::Safe>; -impl<'a, REG> Wupe7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe7::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe7::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe7::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe7::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe8 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe8) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe8 { - type Ux = u8; -} -impl crate::IsEnum for Wupe8 {} -#[doc = "Field `WUPE8` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe8R = crate::FieldReader; -impl Wupe8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe8 { - match self.bits { - 0 => Wupe8::Disable, - 1 => Wupe8::EnRiseHi, - 2 => Wupe8::EnFallLo, - 3 => Wupe8::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe8::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe8::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe8::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe8::EnAny - } -} -#[doc = "Field `WUPE8` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe8W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe8, crate::Safe>; -impl<'a, REG> Wupe8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe8::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe8::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe8::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe8::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe9 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe9) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe9 { - type Ux = u8; -} -impl crate::IsEnum for Wupe9 {} -#[doc = "Field `WUPE9` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe9R = crate::FieldReader; -impl Wupe9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe9 { - match self.bits { - 0 => Wupe9::Disable, - 1 => Wupe9::EnRiseHi, - 2 => Wupe9::EnFallLo, - 3 => Wupe9::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe9::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe9::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe9::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe9::EnAny - } -} -#[doc = "Field `WUPE9` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe9W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe9, crate::Safe>; -impl<'a, REG> Wupe9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe9::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe9::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe9::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe9::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe10 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe10) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe10 { - type Ux = u8; -} -impl crate::IsEnum for Wupe10 {} -#[doc = "Field `WUPE10` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe10R = crate::FieldReader; -impl Wupe10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe10 { - match self.bits { - 0 => Wupe10::Disable, - 1 => Wupe10::EnRiseHi, - 2 => Wupe10::EnFallLo, - 3 => Wupe10::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe10::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe10::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe10::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe10::EnAny - } -} -#[doc = "Field `WUPE10` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe10W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe10, crate::Safe>; -impl<'a, REG> Wupe10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe10::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe10::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe10::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe10::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe11 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe11) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe11 { - type Ux = u8; -} -impl crate::IsEnum for Wupe11 {} -#[doc = "Field `WUPE11` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe11R = crate::FieldReader; -impl Wupe11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe11 { - match self.bits { - 0 => Wupe11::Disable, - 1 => Wupe11::EnRiseHi, - 2 => Wupe11::EnFallLo, - 3 => Wupe11::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe11::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe11::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe11::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe11::EnAny - } -} -#[doc = "Field `WUPE11` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe11W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe11, crate::Safe>; -impl<'a, REG> Wupe11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe11::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe11::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe11::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe11::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe12 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe12) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe12 { - type Ux = u8; -} -impl crate::IsEnum for Wupe12 {} -#[doc = "Field `WUPE12` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe12R = crate::FieldReader; -impl Wupe12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe12 { - match self.bits { - 0 => Wupe12::Disable, - 1 => Wupe12::EnRiseHi, - 2 => Wupe12::EnFallLo, - 3 => Wupe12::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe12::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe12::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe12::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe12::EnAny - } -} -#[doc = "Field `WUPE12` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe12W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe12, crate::Safe>; -impl<'a, REG> Wupe12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe12::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe12::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe12::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe12::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe13 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe13) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe13 { - type Ux = u8; -} -impl crate::IsEnum for Wupe13 {} -#[doc = "Field `WUPE13` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe13R = crate::FieldReader; -impl Wupe13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe13 { - match self.bits { - 0 => Wupe13::Disable, - 1 => Wupe13::EnRiseHi, - 2 => Wupe13::EnFallLo, - 3 => Wupe13::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe13::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe13::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe13::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe13::EnAny - } -} -#[doc = "Field `WUPE13` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe13W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe13, crate::Safe>; -impl<'a, REG> Wupe13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe13::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe13::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe13::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe13::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe14 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe14) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe14 { - type Ux = u8; -} -impl crate::IsEnum for Wupe14 {} -#[doc = "Field `WUPE14` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe14R = crate::FieldReader; -impl Wupe14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe14 { - match self.bits { - 0 => Wupe14::Disable, - 1 => Wupe14::EnRiseHi, - 2 => Wupe14::EnFallLo, - 3 => Wupe14::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe14::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe14::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe14::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe14::EnAny - } -} -#[doc = "Field `WUPE14` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe14W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe14, crate::Safe>; -impl<'a, REG> Wupe14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe14::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe14::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe14::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe14::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe15 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe15) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe15 { - type Ux = u8; -} -impl crate::IsEnum for Wupe15 {} -#[doc = "Field `WUPE15` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe15R = crate::FieldReader; -impl Wupe15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe15 { - match self.bits { - 0 => Wupe15::Disable, - 1 => Wupe15::EnRiseHi, - 2 => Wupe15::EnFallLo, - 3 => Wupe15::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe15::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe15::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe15::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe15::EnAny - } -} -#[doc = "Field `WUPE15` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe15W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe15, crate::Safe>; -impl<'a, REG> Wupe15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe15::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe15::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe15::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe15::EnAny) - } -} -impl R { - #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe0(&self) -> Wupe0R { - Wupe0R::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe1(&self) -> Wupe1R { - Wupe1R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe2(&self) -> Wupe2R { - Wupe2R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe3(&self) -> Wupe3R { - Wupe3R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe4(&self) -> Wupe4R { - Wupe4R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe5(&self) -> Wupe5R { - Wupe5R::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe6(&self) -> Wupe6R { - Wupe6R::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe7(&self) -> Wupe7R { - Wupe7R::new(((self.bits >> 14) & 3) as u8) - } - #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe8(&self) -> Wupe8R { - Wupe8R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe9(&self) -> Wupe9R { - Wupe9R::new(((self.bits >> 18) & 3) as u8) - } - #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe10(&self) -> Wupe10R { - Wupe10R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe11(&self) -> Wupe11R { - Wupe11R::new(((self.bits >> 22) & 3) as u8) - } - #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe12(&self) -> Wupe12R { - Wupe12R::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe13(&self) -> Wupe13R { - Wupe13R::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe14(&self) -> Wupe14R { - Wupe14R::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe15(&self) -> Wupe15R { - Wupe15R::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe0(&mut self) -> Wupe0W { - Wupe0W::new(self, 0) - } - #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe1(&mut self) -> Wupe1W { - Wupe1W::new(self, 2) - } - #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe2(&mut self) -> Wupe2W { - Wupe2W::new(self, 4) - } - #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe3(&mut self) -> Wupe3W { - Wupe3W::new(self, 6) - } - #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe4(&mut self) -> Wupe4W { - Wupe4W::new(self, 8) - } - #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe5(&mut self) -> Wupe5W { - Wupe5W::new(self, 10) - } - #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe6(&mut self) -> Wupe6W { - Wupe6W::new(self, 12) - } - #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe7(&mut self) -> Wupe7W { - Wupe7W::new(self, 14) - } - #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe8(&mut self) -> Wupe8W { - Wupe8W::new(self, 16) - } - #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe9(&mut self) -> Wupe9W { - Wupe9W::new(self, 18) - } - #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe10(&mut self) -> Wupe10W { - Wupe10W::new(self, 20) - } - #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe11(&mut self) -> Wupe11W { - Wupe11W::new(self, 22) - } - #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe12(&mut self) -> Wupe12W { - Wupe12W::new(self, 24) - } - #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe13(&mut self) -> Wupe13W { - Wupe13W::new(self, 26) - } - #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe14(&mut self) -> Wupe14W { - Wupe14W::new(self, 28) - } - #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe15(&mut self) -> Wupe15W { - Wupe15W::new(self, 30) - } -} -#[doc = "Pin Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pe1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pe1Spec; -impl crate::RegisterSpec for Pe1Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pe1::R`](R) reader structure"] -impl crate::Readable for Pe1Spec {} -#[doc = "`write(|w| ..)` method takes [`pe1::W`](W) writer structure"] -impl crate::Writable for Pe1Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PE1 to value 0"] -impl crate::Resettable for Pe1Spec {} diff --git a/mcxa276-pac/src/wuu0/pe2.rs b/mcxa276-pac/src/wuu0/pe2.rs deleted file mode 100644 index 1ff9b579c..000000000 --- a/mcxa276-pac/src/wuu0/pe2.rs +++ /dev/null @@ -1,1557 +0,0 @@ -#[doc = "Register `PE2` reader"] -pub type R = crate::R; -#[doc = "Register `PE2` writer"] -pub type W = crate::W; -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe16 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe16) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe16 { - type Ux = u8; -} -impl crate::IsEnum for Wupe16 {} -#[doc = "Field `WUPE16` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe16R = crate::FieldReader; -impl Wupe16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe16 { - match self.bits { - 0 => Wupe16::Disable, - 1 => Wupe16::EnRiseHi, - 2 => Wupe16::EnFallLo, - 3 => Wupe16::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe16::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe16::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe16::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe16::EnAny - } -} -#[doc = "Field `WUPE16` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe16W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe16, crate::Safe>; -impl<'a, REG> Wupe16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe16::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe16::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe16::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe16::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe17 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe17) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe17 { - type Ux = u8; -} -impl crate::IsEnum for Wupe17 {} -#[doc = "Field `WUPE17` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe17R = crate::FieldReader; -impl Wupe17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe17 { - match self.bits { - 0 => Wupe17::Disable, - 1 => Wupe17::EnRiseHi, - 2 => Wupe17::EnFallLo, - 3 => Wupe17::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe17::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe17::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe17::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe17::EnAny - } -} -#[doc = "Field `WUPE17` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe17W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe17, crate::Safe>; -impl<'a, REG> Wupe17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe17::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe17::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe17::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe17::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe18 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe18) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe18 { - type Ux = u8; -} -impl crate::IsEnum for Wupe18 {} -#[doc = "Field `WUPE18` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe18R = crate::FieldReader; -impl Wupe18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe18 { - match self.bits { - 0 => Wupe18::Disable, - 1 => Wupe18::EnRiseHi, - 2 => Wupe18::EnFallLo, - 3 => Wupe18::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe18::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe18::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe18::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe18::EnAny - } -} -#[doc = "Field `WUPE18` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe18W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe18, crate::Safe>; -impl<'a, REG> Wupe18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe18::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe18::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe18::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe18::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe19 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe19) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe19 { - type Ux = u8; -} -impl crate::IsEnum for Wupe19 {} -#[doc = "Field `WUPE19` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe19R = crate::FieldReader; -impl Wupe19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe19 { - match self.bits { - 0 => Wupe19::Disable, - 1 => Wupe19::EnRiseHi, - 2 => Wupe19::EnFallLo, - 3 => Wupe19::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe19::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe19::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe19::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe19::EnAny - } -} -#[doc = "Field `WUPE19` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe19W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe19, crate::Safe>; -impl<'a, REG> Wupe19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe19::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe19::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe19::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe19::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe20 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe20) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe20 { - type Ux = u8; -} -impl crate::IsEnum for Wupe20 {} -#[doc = "Field `WUPE20` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe20R = crate::FieldReader; -impl Wupe20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe20 { - match self.bits { - 0 => Wupe20::Disable, - 1 => Wupe20::EnRiseHi, - 2 => Wupe20::EnFallLo, - 3 => Wupe20::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe20::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe20::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe20::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe20::EnAny - } -} -#[doc = "Field `WUPE20` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe20W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe20, crate::Safe>; -impl<'a, REG> Wupe20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe20::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe20::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe20::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe20::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe21 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe21) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe21 { - type Ux = u8; -} -impl crate::IsEnum for Wupe21 {} -#[doc = "Field `WUPE21` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe21R = crate::FieldReader; -impl Wupe21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe21 { - match self.bits { - 0 => Wupe21::Disable, - 1 => Wupe21::EnRiseHi, - 2 => Wupe21::EnFallLo, - 3 => Wupe21::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe21::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe21::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe21::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe21::EnAny - } -} -#[doc = "Field `WUPE21` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe21W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe21, crate::Safe>; -impl<'a, REG> Wupe21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe21::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe21::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe21::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe21::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe22 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe22) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe22 { - type Ux = u8; -} -impl crate::IsEnum for Wupe22 {} -#[doc = "Field `WUPE22` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe22R = crate::FieldReader; -impl Wupe22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe22 { - match self.bits { - 0 => Wupe22::Disable, - 1 => Wupe22::EnRiseHi, - 2 => Wupe22::EnFallLo, - 3 => Wupe22::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe22::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe22::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe22::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe22::EnAny - } -} -#[doc = "Field `WUPE22` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe22W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe22, crate::Safe>; -impl<'a, REG> Wupe22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe22::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe22::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe22::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe22::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe23 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe23) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe23 { - type Ux = u8; -} -impl crate::IsEnum for Wupe23 {} -#[doc = "Field `WUPE23` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe23R = crate::FieldReader; -impl Wupe23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe23 { - match self.bits { - 0 => Wupe23::Disable, - 1 => Wupe23::EnRiseHi, - 2 => Wupe23::EnFallLo, - 3 => Wupe23::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe23::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe23::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe23::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe23::EnAny - } -} -#[doc = "Field `WUPE23` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe23W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe23, crate::Safe>; -impl<'a, REG> Wupe23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe23::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe23::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe23::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe23::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe24 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe24) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe24 { - type Ux = u8; -} -impl crate::IsEnum for Wupe24 {} -#[doc = "Field `WUPE24` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe24R = crate::FieldReader; -impl Wupe24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe24 { - match self.bits { - 0 => Wupe24::Disable, - 1 => Wupe24::EnRiseHi, - 2 => Wupe24::EnFallLo, - 3 => Wupe24::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe24::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe24::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe24::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe24::EnAny - } -} -#[doc = "Field `WUPE24` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe24W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe24, crate::Safe>; -impl<'a, REG> Wupe24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe24::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe24::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe24::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe24::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe25 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe25) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe25 { - type Ux = u8; -} -impl crate::IsEnum for Wupe25 {} -#[doc = "Field `WUPE25` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe25R = crate::FieldReader; -impl Wupe25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe25 { - match self.bits { - 0 => Wupe25::Disable, - 1 => Wupe25::EnRiseHi, - 2 => Wupe25::EnFallLo, - 3 => Wupe25::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe25::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe25::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe25::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe25::EnAny - } -} -#[doc = "Field `WUPE25` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe25W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe25, crate::Safe>; -impl<'a, REG> Wupe25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe25::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe25::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe25::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe25::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe26 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe26) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe26 { - type Ux = u8; -} -impl crate::IsEnum for Wupe26 {} -#[doc = "Field `WUPE26` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe26R = crate::FieldReader; -impl Wupe26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe26 { - match self.bits { - 0 => Wupe26::Disable, - 1 => Wupe26::EnRiseHi, - 2 => Wupe26::EnFallLo, - 3 => Wupe26::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe26::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe26::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe26::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe26::EnAny - } -} -#[doc = "Field `WUPE26` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe26W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe26, crate::Safe>; -impl<'a, REG> Wupe26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe26::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe26::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe26::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe26::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe27 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe27) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe27 { - type Ux = u8; -} -impl crate::IsEnum for Wupe27 {} -#[doc = "Field `WUPE27` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe27R = crate::FieldReader; -impl Wupe27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe27 { - match self.bits { - 0 => Wupe27::Disable, - 1 => Wupe27::EnRiseHi, - 2 => Wupe27::EnFallLo, - 3 => Wupe27::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe27::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe27::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe27::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe27::EnAny - } -} -#[doc = "Field `WUPE27` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe27W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe27, crate::Safe>; -impl<'a, REG> Wupe27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe27::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe27::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe27::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe27::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe28 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe28) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe28 { - type Ux = u8; -} -impl crate::IsEnum for Wupe28 {} -#[doc = "Field `WUPE28` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe28R = crate::FieldReader; -impl Wupe28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe28 { - match self.bits { - 0 => Wupe28::Disable, - 1 => Wupe28::EnRiseHi, - 2 => Wupe28::EnFallLo, - 3 => Wupe28::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe28::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe28::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe28::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe28::EnAny - } -} -#[doc = "Field `WUPE28` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe28W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe28, crate::Safe>; -impl<'a, REG> Wupe28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe28::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe28::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe28::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe28::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe29 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe29) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe29 { - type Ux = u8; -} -impl crate::IsEnum for Wupe29 {} -#[doc = "Field `WUPE29` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe29R = crate::FieldReader; -impl Wupe29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe29 { - match self.bits { - 0 => Wupe29::Disable, - 1 => Wupe29::EnRiseHi, - 2 => Wupe29::EnFallLo, - 3 => Wupe29::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe29::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe29::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe29::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe29::EnAny - } -} -#[doc = "Field `WUPE29` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe29W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe29, crate::Safe>; -impl<'a, REG> Wupe29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe29::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe29::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe29::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe29::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe30 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe30) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe30 { - type Ux = u8; -} -impl crate::IsEnum for Wupe30 {} -#[doc = "Field `WUPE30` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe30R = crate::FieldReader; -impl Wupe30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe30 { - match self.bits { - 0 => Wupe30::Disable, - 1 => Wupe30::EnRiseHi, - 2 => Wupe30::EnFallLo, - 3 => Wupe30::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe30::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe30::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe30::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe30::EnAny - } -} -#[doc = "Field `WUPE30` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe30W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe30, crate::Safe>; -impl<'a, REG> Wupe30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe30::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe30::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe30::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe30::EnAny) - } -} -#[doc = "Wake-up Pin Enable for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Wupe31 { - #[doc = "0: Disable"] - Disable = 0, - #[doc = "1: Enable (detect on rising edge or high level)"] - EnRiseHi = 1, - #[doc = "2: Enable (detect on falling edge or low level)"] - EnFallLo = 2, - #[doc = "3: Enable (detect on any edge)"] - EnAny = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Wupe31) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Wupe31 { - type Ux = u8; -} -impl crate::IsEnum for Wupe31 {} -#[doc = "Field `WUPE31` reader - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe31R = crate::FieldReader; -impl Wupe31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupe31 { - match self.bits { - 0 => Wupe31::Disable, - 1 => Wupe31::EnRiseHi, - 2 => Wupe31::EnFallLo, - 3 => Wupe31::EnAny, - _ => unreachable!(), - } - } - #[doc = "Disable"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == Wupe31::Disable - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn is_en_rise_hi(&self) -> bool { - *self == Wupe31::EnRiseHi - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn is_en_fall_lo(&self) -> bool { - *self == Wupe31::EnFallLo - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn is_en_any(&self) -> bool { - *self == Wupe31::EnAny - } -} -#[doc = "Field `WUPE31` writer - Wake-up Pin Enable for WUU_Pn"] -pub type Wupe31W<'a, REG> = crate::FieldWriter<'a, REG, 2, Wupe31, crate::Safe>; -impl<'a, REG> Wupe31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Disable"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(Wupe31::Disable) - } - #[doc = "Enable (detect on rising edge or high level)"] - #[inline(always)] - pub fn en_rise_hi(self) -> &'a mut crate::W { - self.variant(Wupe31::EnRiseHi) - } - #[doc = "Enable (detect on falling edge or low level)"] - #[inline(always)] - pub fn en_fall_lo(self) -> &'a mut crate::W { - self.variant(Wupe31::EnFallLo) - } - #[doc = "Enable (detect on any edge)"] - #[inline(always)] - pub fn en_any(self) -> &'a mut crate::W { - self.variant(Wupe31::EnAny) - } -} -impl R { - #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe16(&self) -> Wupe16R { - Wupe16R::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe17(&self) -> Wupe17R { - Wupe17R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe18(&self) -> Wupe18R { - Wupe18R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe19(&self) -> Wupe19R { - Wupe19R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe20(&self) -> Wupe20R { - Wupe20R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe21(&self) -> Wupe21R { - Wupe21R::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe22(&self) -> Wupe22R { - Wupe22R::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe23(&self) -> Wupe23R { - Wupe23R::new(((self.bits >> 14) & 3) as u8) - } - #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe24(&self) -> Wupe24R { - Wupe24R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe25(&self) -> Wupe25R { - Wupe25R::new(((self.bits >> 18) & 3) as u8) - } - #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe26(&self) -> Wupe26R { - Wupe26R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe27(&self) -> Wupe27R { - Wupe27R::new(((self.bits >> 22) & 3) as u8) - } - #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe28(&self) -> Wupe28R { - Wupe28R::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe29(&self) -> Wupe29R { - Wupe29R::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe30(&self) -> Wupe30R { - Wupe30R::new(((self.bits >> 28) & 3) as u8) - } - #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe31(&self) -> Wupe31R { - Wupe31R::new(((self.bits >> 30) & 3) as u8) - } -} -impl W { - #[doc = "Bits 0:1 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe16(&mut self) -> Wupe16W { - Wupe16W::new(self, 0) - } - #[doc = "Bits 2:3 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe17(&mut self) -> Wupe17W { - Wupe17W::new(self, 2) - } - #[doc = "Bits 4:5 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe18(&mut self) -> Wupe18W { - Wupe18W::new(self, 4) - } - #[doc = "Bits 6:7 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe19(&mut self) -> Wupe19W { - Wupe19W::new(self, 6) - } - #[doc = "Bits 8:9 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe20(&mut self) -> Wupe20W { - Wupe20W::new(self, 8) - } - #[doc = "Bits 10:11 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe21(&mut self) -> Wupe21W { - Wupe21W::new(self, 10) - } - #[doc = "Bits 12:13 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe22(&mut self) -> Wupe22W { - Wupe22W::new(self, 12) - } - #[doc = "Bits 14:15 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe23(&mut self) -> Wupe23W { - Wupe23W::new(self, 14) - } - #[doc = "Bits 16:17 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe24(&mut self) -> Wupe24W { - Wupe24W::new(self, 16) - } - #[doc = "Bits 18:19 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe25(&mut self) -> Wupe25W { - Wupe25W::new(self, 18) - } - #[doc = "Bits 20:21 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe26(&mut self) -> Wupe26W { - Wupe26W::new(self, 20) - } - #[doc = "Bits 22:23 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe27(&mut self) -> Wupe27W { - Wupe27W::new(self, 22) - } - #[doc = "Bits 24:25 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe28(&mut self) -> Wupe28W { - Wupe28W::new(self, 24) - } - #[doc = "Bits 26:27 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe29(&mut self) -> Wupe29W { - Wupe29W::new(self, 26) - } - #[doc = "Bits 28:29 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe30(&mut self) -> Wupe30W { - Wupe30W::new(self, 28) - } - #[doc = "Bits 30:31 - Wake-up Pin Enable for WUU_Pn"] - #[inline(always)] - pub fn wupe31(&mut self) -> Wupe31W { - Wupe31W::new(self, 30) - } -} -#[doc = "Pin Enable 2\n\nYou can [`read`](crate::Reg::read) this register and get [`pe2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pe2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct Pe2Spec; -impl crate::RegisterSpec for Pe2Spec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pe2::R`](R) reader structure"] -impl crate::Readable for Pe2Spec {} -#[doc = "`write(|w| ..)` method takes [`pe2::W`](W) writer structure"] -impl crate::Writable for Pe2Spec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PE2 to value 0"] -impl crate::Resettable for Pe2Spec {} diff --git a/mcxa276-pac/src/wuu0/pf.rs b/mcxa276-pac/src/wuu0/pf.rs deleted file mode 100644 index a3993eef6..000000000 --- a/mcxa276-pac/src/wuu0/pf.rs +++ /dev/null @@ -1,2038 +0,0 @@ -#[doc = "Register `PF` reader"] -pub type R = crate::R; -#[doc = "Register `PF` writer"] -pub type W = crate::W; -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf0 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF0` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf0R = crate::BitReader; -impl Wuf0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf0 { - match self.bits { - false => Wuf0::NoFlag, - true => Wuf0::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf0::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf0::Flag - } -} -#[doc = "Field `WUF0` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf0W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf0>; -impl<'a, REG> Wuf0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf0::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf0::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf1 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF1` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf1R = crate::BitReader; -impl Wuf1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf1 { - match self.bits { - false => Wuf1::NoFlag, - true => Wuf1::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf1::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf1::Flag - } -} -#[doc = "Field `WUF1` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf1W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf1>; -impl<'a, REG> Wuf1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf1::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf1::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf2 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF2` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf2R = crate::BitReader; -impl Wuf2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf2 { - match self.bits { - false => Wuf2::NoFlag, - true => Wuf2::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf2::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf2::Flag - } -} -#[doc = "Field `WUF2` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf2W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf2>; -impl<'a, REG> Wuf2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf2::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf2::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf3 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF3` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf3R = crate::BitReader; -impl Wuf3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf3 { - match self.bits { - false => Wuf3::NoFlag, - true => Wuf3::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf3::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf3::Flag - } -} -#[doc = "Field `WUF3` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf3W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf3>; -impl<'a, REG> Wuf3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf3::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf3::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf4 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF4` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf4R = crate::BitReader; -impl Wuf4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf4 { - match self.bits { - false => Wuf4::NoFlag, - true => Wuf4::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf4::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf4::Flag - } -} -#[doc = "Field `WUF4` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf4W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf4>; -impl<'a, REG> Wuf4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf4::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf4::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf5 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF5` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf5R = crate::BitReader; -impl Wuf5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf5 { - match self.bits { - false => Wuf5::NoFlag, - true => Wuf5::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf5::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf5::Flag - } -} -#[doc = "Field `WUF5` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf5W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf5>; -impl<'a, REG> Wuf5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf5::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf5::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf6 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF6` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf6R = crate::BitReader; -impl Wuf6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf6 { - match self.bits { - false => Wuf6::NoFlag, - true => Wuf6::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf6::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf6::Flag - } -} -#[doc = "Field `WUF6` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf6W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf6>; -impl<'a, REG> Wuf6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf6::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf6::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf7 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF7` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf7R = crate::BitReader; -impl Wuf7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf7 { - match self.bits { - false => Wuf7::NoFlag, - true => Wuf7::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf7::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf7::Flag - } -} -#[doc = "Field `WUF7` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf7W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf7>; -impl<'a, REG> Wuf7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf7::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf7::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf8 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF8` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf8R = crate::BitReader; -impl Wuf8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf8 { - match self.bits { - false => Wuf8::NoFlag, - true => Wuf8::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf8::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf8::Flag - } -} -#[doc = "Field `WUF8` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf8W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf8>; -impl<'a, REG> Wuf8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf8::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf8::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf9 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF9` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf9R = crate::BitReader; -impl Wuf9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf9 { - match self.bits { - false => Wuf9::NoFlag, - true => Wuf9::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf9::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf9::Flag - } -} -#[doc = "Field `WUF9` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf9W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf9>; -impl<'a, REG> Wuf9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf9::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf9::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf10 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF10` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf10R = crate::BitReader; -impl Wuf10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf10 { - match self.bits { - false => Wuf10::NoFlag, - true => Wuf10::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf10::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf10::Flag - } -} -#[doc = "Field `WUF10` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf10W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf10>; -impl<'a, REG> Wuf10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf10::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf10::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf11 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF11` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf11R = crate::BitReader; -impl Wuf11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf11 { - match self.bits { - false => Wuf11::NoFlag, - true => Wuf11::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf11::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf11::Flag - } -} -#[doc = "Field `WUF11` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf11W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf11>; -impl<'a, REG> Wuf11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf11::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf11::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf12 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF12` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf12R = crate::BitReader; -impl Wuf12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf12 { - match self.bits { - false => Wuf12::NoFlag, - true => Wuf12::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf12::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf12::Flag - } -} -#[doc = "Field `WUF12` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf12W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf12>; -impl<'a, REG> Wuf12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf12::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf12::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf13 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF13` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf13R = crate::BitReader; -impl Wuf13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf13 { - match self.bits { - false => Wuf13::NoFlag, - true => Wuf13::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf13::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf13::Flag - } -} -#[doc = "Field `WUF13` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf13W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf13>; -impl<'a, REG> Wuf13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf13::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf13::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf14 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF14` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf14R = crate::BitReader; -impl Wuf14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf14 { - match self.bits { - false => Wuf14::NoFlag, - true => Wuf14::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf14::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf14::Flag - } -} -#[doc = "Field `WUF14` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf14W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf14>; -impl<'a, REG> Wuf14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf14::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf14::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf15 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF15` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf15R = crate::BitReader; -impl Wuf15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf15 { - match self.bits { - false => Wuf15::NoFlag, - true => Wuf15::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf15::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf15::Flag - } -} -#[doc = "Field `WUF15` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf15W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf15>; -impl<'a, REG> Wuf15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf15::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf15::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf16 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF16` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf16R = crate::BitReader; -impl Wuf16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf16 { - match self.bits { - false => Wuf16::NoFlag, - true => Wuf16::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf16::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf16::Flag - } -} -#[doc = "Field `WUF16` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf16W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf16>; -impl<'a, REG> Wuf16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf16::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf16::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf17 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF17` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf17R = crate::BitReader; -impl Wuf17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf17 { - match self.bits { - false => Wuf17::NoFlag, - true => Wuf17::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf17::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf17::Flag - } -} -#[doc = "Field `WUF17` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf17W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf17>; -impl<'a, REG> Wuf17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf17::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf17::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf18 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF18` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf18R = crate::BitReader; -impl Wuf18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf18 { - match self.bits { - false => Wuf18::NoFlag, - true => Wuf18::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf18::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf18::Flag - } -} -#[doc = "Field `WUF18` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf18W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf18>; -impl<'a, REG> Wuf18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf18::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf18::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf19 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF19` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf19R = crate::BitReader; -impl Wuf19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf19 { - match self.bits { - false => Wuf19::NoFlag, - true => Wuf19::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf19::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf19::Flag - } -} -#[doc = "Field `WUF19` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf19W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf19>; -impl<'a, REG> Wuf19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf19::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf19::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf20 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF20` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf20R = crate::BitReader; -impl Wuf20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf20 { - match self.bits { - false => Wuf20::NoFlag, - true => Wuf20::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf20::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf20::Flag - } -} -#[doc = "Field `WUF20` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf20W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf20>; -impl<'a, REG> Wuf20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf20::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf20::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf21 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF21` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf21R = crate::BitReader; -impl Wuf21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf21 { - match self.bits { - false => Wuf21::NoFlag, - true => Wuf21::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf21::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf21::Flag - } -} -#[doc = "Field `WUF21` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf21W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf21>; -impl<'a, REG> Wuf21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf21::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf21::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf22 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF22` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf22R = crate::BitReader; -impl Wuf22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf22 { - match self.bits { - false => Wuf22::NoFlag, - true => Wuf22::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf22::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf22::Flag - } -} -#[doc = "Field `WUF22` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf22W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf22>; -impl<'a, REG> Wuf22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf22::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf22::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf23 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF23` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf23R = crate::BitReader; -impl Wuf23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf23 { - match self.bits { - false => Wuf23::NoFlag, - true => Wuf23::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf23::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf23::Flag - } -} -#[doc = "Field `WUF23` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf23W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf23>; -impl<'a, REG> Wuf23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf23::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf23::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf24 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF24` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf24R = crate::BitReader; -impl Wuf24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf24 { - match self.bits { - false => Wuf24::NoFlag, - true => Wuf24::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf24::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf24::Flag - } -} -#[doc = "Field `WUF24` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf24W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf24>; -impl<'a, REG> Wuf24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf24::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf24::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf25 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF25` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf25R = crate::BitReader; -impl Wuf25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf25 { - match self.bits { - false => Wuf25::NoFlag, - true => Wuf25::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf25::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf25::Flag - } -} -#[doc = "Field `WUF25` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf25W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf25>; -impl<'a, REG> Wuf25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf25::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf25::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf26 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF26` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf26R = crate::BitReader; -impl Wuf26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf26 { - match self.bits { - false => Wuf26::NoFlag, - true => Wuf26::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf26::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf26::Flag - } -} -#[doc = "Field `WUF26` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf26W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf26>; -impl<'a, REG> Wuf26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf26::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf26::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf27 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF27` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf27R = crate::BitReader; -impl Wuf27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf27 { - match self.bits { - false => Wuf27::NoFlag, - true => Wuf27::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf27::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf27::Flag - } -} -#[doc = "Field `WUF27` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf27W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf27>; -impl<'a, REG> Wuf27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf27::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf27::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf28 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF28` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf28R = crate::BitReader; -impl Wuf28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf28 { - match self.bits { - false => Wuf28::NoFlag, - true => Wuf28::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf28::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf28::Flag - } -} -#[doc = "Field `WUF28` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf28W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf28>; -impl<'a, REG> Wuf28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf28::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf28::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf29 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF29` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf29R = crate::BitReader; -impl Wuf29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf29 { - match self.bits { - false => Wuf29::NoFlag, - true => Wuf29::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf29::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf29::Flag - } -} -#[doc = "Field `WUF29` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf29W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf29>; -impl<'a, REG> Wuf29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf29::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf29::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf30 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF30` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf30R = crate::BitReader; -impl Wuf30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf30 { - match self.bits { - false => Wuf30::NoFlag, - true => Wuf30::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf30::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf30::Flag - } -} -#[doc = "Field `WUF30` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf30W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf30>; -impl<'a, REG> Wuf30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf30::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf30::Flag) - } -} -#[doc = "Wake-up Flag for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wuf31 { - #[doc = "0: No"] - NoFlag = 0, - #[doc = "1: Yes"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wuf31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUF31` reader - Wake-up Flag for WUU_Pn"] -pub type Wuf31R = crate::BitReader; -impl Wuf31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wuf31 { - match self.bits { - false => Wuf31::NoFlag, - true => Wuf31::Flag, - } - } - #[doc = "No"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wuf31::NoFlag - } - #[doc = "Yes"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wuf31::Flag - } -} -#[doc = "Field `WUF31` writer - Wake-up Flag for WUU_Pn"] -pub type Wuf31W<'a, REG> = crate::BitWriter1C<'a, REG, Wuf31>; -impl<'a, REG> Wuf31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wuf31::NoFlag) - } - #[doc = "Yes"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wuf31::Flag) - } -} -impl R { - #[doc = "Bit 0 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf0(&self) -> Wuf0R { - Wuf0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf1(&self) -> Wuf1R { - Wuf1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf2(&self) -> Wuf2R { - Wuf2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf3(&self) -> Wuf3R { - Wuf3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf4(&self) -> Wuf4R { - Wuf4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf5(&self) -> Wuf5R { - Wuf5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf6(&self) -> Wuf6R { - Wuf6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf7(&self) -> Wuf7R { - Wuf7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf8(&self) -> Wuf8R { - Wuf8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf9(&self) -> Wuf9R { - Wuf9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf10(&self) -> Wuf10R { - Wuf10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf11(&self) -> Wuf11R { - Wuf11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf12(&self) -> Wuf12R { - Wuf12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf13(&self) -> Wuf13R { - Wuf13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf14(&self) -> Wuf14R { - Wuf14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf15(&self) -> Wuf15R { - Wuf15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf16(&self) -> Wuf16R { - Wuf16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf17(&self) -> Wuf17R { - Wuf17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf18(&self) -> Wuf18R { - Wuf18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf19(&self) -> Wuf19R { - Wuf19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf20(&self) -> Wuf20R { - Wuf20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf21(&self) -> Wuf21R { - Wuf21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf22(&self) -> Wuf22R { - Wuf22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf23(&self) -> Wuf23R { - Wuf23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf24(&self) -> Wuf24R { - Wuf24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf25(&self) -> Wuf25R { - Wuf25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf26(&self) -> Wuf26R { - Wuf26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf27(&self) -> Wuf27R { - Wuf27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf28(&self) -> Wuf28R { - Wuf28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf29(&self) -> Wuf29R { - Wuf29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf30(&self) -> Wuf30R { - Wuf30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf31(&self) -> Wuf31R { - Wuf31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf0(&mut self) -> Wuf0W { - Wuf0W::new(self, 0) - } - #[doc = "Bit 1 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf1(&mut self) -> Wuf1W { - Wuf1W::new(self, 1) - } - #[doc = "Bit 2 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf2(&mut self) -> Wuf2W { - Wuf2W::new(self, 2) - } - #[doc = "Bit 3 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf3(&mut self) -> Wuf3W { - Wuf3W::new(self, 3) - } - #[doc = "Bit 4 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf4(&mut self) -> Wuf4W { - Wuf4W::new(self, 4) - } - #[doc = "Bit 5 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf5(&mut self) -> Wuf5W { - Wuf5W::new(self, 5) - } - #[doc = "Bit 6 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf6(&mut self) -> Wuf6W { - Wuf6W::new(self, 6) - } - #[doc = "Bit 7 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf7(&mut self) -> Wuf7W { - Wuf7W::new(self, 7) - } - #[doc = "Bit 8 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf8(&mut self) -> Wuf8W { - Wuf8W::new(self, 8) - } - #[doc = "Bit 9 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf9(&mut self) -> Wuf9W { - Wuf9W::new(self, 9) - } - #[doc = "Bit 10 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf10(&mut self) -> Wuf10W { - Wuf10W::new(self, 10) - } - #[doc = "Bit 11 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf11(&mut self) -> Wuf11W { - Wuf11W::new(self, 11) - } - #[doc = "Bit 12 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf12(&mut self) -> Wuf12W { - Wuf12W::new(self, 12) - } - #[doc = "Bit 13 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf13(&mut self) -> Wuf13W { - Wuf13W::new(self, 13) - } - #[doc = "Bit 14 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf14(&mut self) -> Wuf14W { - Wuf14W::new(self, 14) - } - #[doc = "Bit 15 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf15(&mut self) -> Wuf15W { - Wuf15W::new(self, 15) - } - #[doc = "Bit 16 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf16(&mut self) -> Wuf16W { - Wuf16W::new(self, 16) - } - #[doc = "Bit 17 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf17(&mut self) -> Wuf17W { - Wuf17W::new(self, 17) - } - #[doc = "Bit 18 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf18(&mut self) -> Wuf18W { - Wuf18W::new(self, 18) - } - #[doc = "Bit 19 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf19(&mut self) -> Wuf19W { - Wuf19W::new(self, 19) - } - #[doc = "Bit 20 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf20(&mut self) -> Wuf20W { - Wuf20W::new(self, 20) - } - #[doc = "Bit 21 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf21(&mut self) -> Wuf21W { - Wuf21W::new(self, 21) - } - #[doc = "Bit 22 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf22(&mut self) -> Wuf22W { - Wuf22W::new(self, 22) - } - #[doc = "Bit 23 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf23(&mut self) -> Wuf23W { - Wuf23W::new(self, 23) - } - #[doc = "Bit 24 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf24(&mut self) -> Wuf24W { - Wuf24W::new(self, 24) - } - #[doc = "Bit 25 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf25(&mut self) -> Wuf25W { - Wuf25W::new(self, 25) - } - #[doc = "Bit 26 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf26(&mut self) -> Wuf26W { - Wuf26W::new(self, 26) - } - #[doc = "Bit 27 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf27(&mut self) -> Wuf27W { - Wuf27W::new(self, 27) - } - #[doc = "Bit 28 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf28(&mut self) -> Wuf28W { - Wuf28W::new(self, 28) - } - #[doc = "Bit 29 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf29(&mut self) -> Wuf29W { - Wuf29W::new(self, 29) - } - #[doc = "Bit 30 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf30(&mut self) -> Wuf30W { - Wuf30W::new(self, 30) - } - #[doc = "Bit 31 - Wake-up Flag for WUU_Pn"] - #[inline(always)] - pub fn wuf31(&mut self) -> Wuf31W { - Wuf31W::new(self, 31) - } -} -#[doc = "Pin Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PfSpec; -impl crate::RegisterSpec for PfSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pf::R`](R) reader structure"] -impl crate::Readable for PfSpec {} -#[doc = "`write(|w| ..)` method takes [`pf::W`](W) writer structure"] -impl crate::Writable for PfSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; -} -#[doc = "`reset()` method sets PF to value 0"] -impl crate::Resettable for PfSpec {} diff --git a/mcxa276-pac/src/wuu0/pmc.rs b/mcxa276-pac/src/wuu0/pmc.rs deleted file mode 100644 index 0f6e6e9e2..000000000 --- a/mcxa276-pac/src/wuu0/pmc.rs +++ /dev/null @@ -1,2037 +0,0 @@ -#[doc = "Register `PMC` reader"] -pub type R = crate::R; -#[doc = "Register `PMC` writer"] -pub type W = crate::W; -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc0 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc0) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC0` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc0R = crate::BitReader; -impl Wupmc0R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc0 { - match self.bits { - false => Wupmc0::LowPwrOnly, - true => Wupmc0::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc0::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc0::AnyPwr - } -} -#[doc = "Field `WUPMC0` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc0W<'a, REG> = crate::BitWriter<'a, REG, Wupmc0>; -impl<'a, REG> Wupmc0W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc0::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc0::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc1 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc1) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC1` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc1R = crate::BitReader; -impl Wupmc1R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc1 { - match self.bits { - false => Wupmc1::LowPwrOnly, - true => Wupmc1::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc1::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc1::AnyPwr - } -} -#[doc = "Field `WUPMC1` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc1W<'a, REG> = crate::BitWriter<'a, REG, Wupmc1>; -impl<'a, REG> Wupmc1W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc1::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc1::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc2 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc2) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC2` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc2R = crate::BitReader; -impl Wupmc2R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc2 { - match self.bits { - false => Wupmc2::LowPwrOnly, - true => Wupmc2::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc2::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc2::AnyPwr - } -} -#[doc = "Field `WUPMC2` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc2W<'a, REG> = crate::BitWriter<'a, REG, Wupmc2>; -impl<'a, REG> Wupmc2W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc2::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc2::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc3 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc3) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC3` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc3R = crate::BitReader; -impl Wupmc3R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc3 { - match self.bits { - false => Wupmc3::LowPwrOnly, - true => Wupmc3::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc3::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc3::AnyPwr - } -} -#[doc = "Field `WUPMC3` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc3W<'a, REG> = crate::BitWriter<'a, REG, Wupmc3>; -impl<'a, REG> Wupmc3W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc3::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc3::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc4 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc4) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC4` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc4R = crate::BitReader; -impl Wupmc4R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc4 { - match self.bits { - false => Wupmc4::LowPwrOnly, - true => Wupmc4::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc4::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc4::AnyPwr - } -} -#[doc = "Field `WUPMC4` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc4W<'a, REG> = crate::BitWriter<'a, REG, Wupmc4>; -impl<'a, REG> Wupmc4W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc4::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc4::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc5 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc5) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC5` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc5R = crate::BitReader; -impl Wupmc5R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc5 { - match self.bits { - false => Wupmc5::LowPwrOnly, - true => Wupmc5::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc5::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc5::AnyPwr - } -} -#[doc = "Field `WUPMC5` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc5W<'a, REG> = crate::BitWriter<'a, REG, Wupmc5>; -impl<'a, REG> Wupmc5W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc5::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc5::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc6 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc6) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC6` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc6R = crate::BitReader; -impl Wupmc6R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc6 { - match self.bits { - false => Wupmc6::LowPwrOnly, - true => Wupmc6::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc6::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc6::AnyPwr - } -} -#[doc = "Field `WUPMC6` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc6W<'a, REG> = crate::BitWriter<'a, REG, Wupmc6>; -impl<'a, REG> Wupmc6W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc6::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc6::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc7 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc7) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC7` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc7R = crate::BitReader; -impl Wupmc7R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc7 { - match self.bits { - false => Wupmc7::LowPwrOnly, - true => Wupmc7::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc7::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc7::AnyPwr - } -} -#[doc = "Field `WUPMC7` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc7W<'a, REG> = crate::BitWriter<'a, REG, Wupmc7>; -impl<'a, REG> Wupmc7W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc7::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc7::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc8 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc8) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC8` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc8R = crate::BitReader; -impl Wupmc8R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc8 { - match self.bits { - false => Wupmc8::LowPwrOnly, - true => Wupmc8::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc8::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc8::AnyPwr - } -} -#[doc = "Field `WUPMC8` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc8W<'a, REG> = crate::BitWriter<'a, REG, Wupmc8>; -impl<'a, REG> Wupmc8W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc8::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc8::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc9 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc9) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC9` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc9R = crate::BitReader; -impl Wupmc9R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc9 { - match self.bits { - false => Wupmc9::LowPwrOnly, - true => Wupmc9::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc9::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc9::AnyPwr - } -} -#[doc = "Field `WUPMC9` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc9W<'a, REG> = crate::BitWriter<'a, REG, Wupmc9>; -impl<'a, REG> Wupmc9W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc9::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc9::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc10 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc10) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC10` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc10R = crate::BitReader; -impl Wupmc10R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc10 { - match self.bits { - false => Wupmc10::LowPwrOnly, - true => Wupmc10::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc10::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc10::AnyPwr - } -} -#[doc = "Field `WUPMC10` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc10W<'a, REG> = crate::BitWriter<'a, REG, Wupmc10>; -impl<'a, REG> Wupmc10W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc10::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc10::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc11 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc11) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC11` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc11R = crate::BitReader; -impl Wupmc11R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc11 { - match self.bits { - false => Wupmc11::LowPwrOnly, - true => Wupmc11::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc11::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc11::AnyPwr - } -} -#[doc = "Field `WUPMC11` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc11W<'a, REG> = crate::BitWriter<'a, REG, Wupmc11>; -impl<'a, REG> Wupmc11W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc11::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc11::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc12 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc12) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC12` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc12R = crate::BitReader; -impl Wupmc12R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc12 { - match self.bits { - false => Wupmc12::LowPwrOnly, - true => Wupmc12::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc12::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc12::AnyPwr - } -} -#[doc = "Field `WUPMC12` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc12W<'a, REG> = crate::BitWriter<'a, REG, Wupmc12>; -impl<'a, REG> Wupmc12W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc12::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc12::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc13 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc13) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC13` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc13R = crate::BitReader; -impl Wupmc13R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc13 { - match self.bits { - false => Wupmc13::LowPwrOnly, - true => Wupmc13::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc13::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc13::AnyPwr - } -} -#[doc = "Field `WUPMC13` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc13W<'a, REG> = crate::BitWriter<'a, REG, Wupmc13>; -impl<'a, REG> Wupmc13W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc13::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc13::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc14 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc14) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC14` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc14R = crate::BitReader; -impl Wupmc14R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc14 { - match self.bits { - false => Wupmc14::LowPwrOnly, - true => Wupmc14::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc14::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc14::AnyPwr - } -} -#[doc = "Field `WUPMC14` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc14W<'a, REG> = crate::BitWriter<'a, REG, Wupmc14>; -impl<'a, REG> Wupmc14W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc14::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc14::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc15 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc15) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC15` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc15R = crate::BitReader; -impl Wupmc15R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc15 { - match self.bits { - false => Wupmc15::LowPwrOnly, - true => Wupmc15::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc15::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc15::AnyPwr - } -} -#[doc = "Field `WUPMC15` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc15W<'a, REG> = crate::BitWriter<'a, REG, Wupmc15>; -impl<'a, REG> Wupmc15W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc15::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc15::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc16 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc16) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC16` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc16R = crate::BitReader; -impl Wupmc16R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc16 { - match self.bits { - false => Wupmc16::LowPwrOnly, - true => Wupmc16::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc16::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc16::AnyPwr - } -} -#[doc = "Field `WUPMC16` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc16W<'a, REG> = crate::BitWriter<'a, REG, Wupmc16>; -impl<'a, REG> Wupmc16W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc16::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc16::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc17 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc17) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC17` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc17R = crate::BitReader; -impl Wupmc17R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc17 { - match self.bits { - false => Wupmc17::LowPwrOnly, - true => Wupmc17::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc17::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc17::AnyPwr - } -} -#[doc = "Field `WUPMC17` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc17W<'a, REG> = crate::BitWriter<'a, REG, Wupmc17>; -impl<'a, REG> Wupmc17W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc17::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc17::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc18 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc18) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC18` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc18R = crate::BitReader; -impl Wupmc18R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc18 { - match self.bits { - false => Wupmc18::LowPwrOnly, - true => Wupmc18::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc18::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc18::AnyPwr - } -} -#[doc = "Field `WUPMC18` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc18W<'a, REG> = crate::BitWriter<'a, REG, Wupmc18>; -impl<'a, REG> Wupmc18W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc18::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc18::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc19 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc19) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC19` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc19R = crate::BitReader; -impl Wupmc19R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc19 { - match self.bits { - false => Wupmc19::LowPwrOnly, - true => Wupmc19::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc19::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc19::AnyPwr - } -} -#[doc = "Field `WUPMC19` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc19W<'a, REG> = crate::BitWriter<'a, REG, Wupmc19>; -impl<'a, REG> Wupmc19W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc19::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc19::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc20 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc20) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC20` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc20R = crate::BitReader; -impl Wupmc20R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc20 { - match self.bits { - false => Wupmc20::LowPwrOnly, - true => Wupmc20::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc20::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc20::AnyPwr - } -} -#[doc = "Field `WUPMC20` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc20W<'a, REG> = crate::BitWriter<'a, REG, Wupmc20>; -impl<'a, REG> Wupmc20W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc20::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc20::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc21 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc21) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC21` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc21R = crate::BitReader; -impl Wupmc21R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc21 { - match self.bits { - false => Wupmc21::LowPwrOnly, - true => Wupmc21::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc21::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc21::AnyPwr - } -} -#[doc = "Field `WUPMC21` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc21W<'a, REG> = crate::BitWriter<'a, REG, Wupmc21>; -impl<'a, REG> Wupmc21W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc21::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc21::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc22 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc22) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC22` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc22R = crate::BitReader; -impl Wupmc22R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc22 { - match self.bits { - false => Wupmc22::LowPwrOnly, - true => Wupmc22::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc22::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc22::AnyPwr - } -} -#[doc = "Field `WUPMC22` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc22W<'a, REG> = crate::BitWriter<'a, REG, Wupmc22>; -impl<'a, REG> Wupmc22W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc22::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc22::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc23 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc23) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC23` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc23R = crate::BitReader; -impl Wupmc23R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc23 { - match self.bits { - false => Wupmc23::LowPwrOnly, - true => Wupmc23::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc23::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc23::AnyPwr - } -} -#[doc = "Field `WUPMC23` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc23W<'a, REG> = crate::BitWriter<'a, REG, Wupmc23>; -impl<'a, REG> Wupmc23W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc23::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc23::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc24 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc24) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC24` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc24R = crate::BitReader; -impl Wupmc24R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc24 { - match self.bits { - false => Wupmc24::LowPwrOnly, - true => Wupmc24::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc24::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc24::AnyPwr - } -} -#[doc = "Field `WUPMC24` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc24W<'a, REG> = crate::BitWriter<'a, REG, Wupmc24>; -impl<'a, REG> Wupmc24W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc24::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc24::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc25 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc25) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC25` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc25R = crate::BitReader; -impl Wupmc25R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc25 { - match self.bits { - false => Wupmc25::LowPwrOnly, - true => Wupmc25::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc25::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc25::AnyPwr - } -} -#[doc = "Field `WUPMC25` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc25W<'a, REG> = crate::BitWriter<'a, REG, Wupmc25>; -impl<'a, REG> Wupmc25W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc25::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc25::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc26 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc26) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC26` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc26R = crate::BitReader; -impl Wupmc26R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc26 { - match self.bits { - false => Wupmc26::LowPwrOnly, - true => Wupmc26::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc26::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc26::AnyPwr - } -} -#[doc = "Field `WUPMC26` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc26W<'a, REG> = crate::BitWriter<'a, REG, Wupmc26>; -impl<'a, REG> Wupmc26W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc26::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc26::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc27 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc27) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC27` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc27R = crate::BitReader; -impl Wupmc27R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc27 { - match self.bits { - false => Wupmc27::LowPwrOnly, - true => Wupmc27::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc27::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc27::AnyPwr - } -} -#[doc = "Field `WUPMC27` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc27W<'a, REG> = crate::BitWriter<'a, REG, Wupmc27>; -impl<'a, REG> Wupmc27W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc27::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc27::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc28 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc28) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC28` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc28R = crate::BitReader; -impl Wupmc28R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc28 { - match self.bits { - false => Wupmc28::LowPwrOnly, - true => Wupmc28::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc28::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc28::AnyPwr - } -} -#[doc = "Field `WUPMC28` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc28W<'a, REG> = crate::BitWriter<'a, REG, Wupmc28>; -impl<'a, REG> Wupmc28W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc28::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc28::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc29 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc29) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC29` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc29R = crate::BitReader; -impl Wupmc29R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc29 { - match self.bits { - false => Wupmc29::LowPwrOnly, - true => Wupmc29::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc29::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc29::AnyPwr - } -} -#[doc = "Field `WUPMC29` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc29W<'a, REG> = crate::BitWriter<'a, REG, Wupmc29>; -impl<'a, REG> Wupmc29W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc29::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc29::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc30 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc30) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC30` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc30R = crate::BitReader; -impl Wupmc30R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc30 { - match self.bits { - false => Wupmc30::LowPwrOnly, - true => Wupmc30::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc30::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc30::AnyPwr - } -} -#[doc = "Field `WUPMC30` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc30W<'a, REG> = crate::BitWriter<'a, REG, Wupmc30>; -impl<'a, REG> Wupmc30W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc30::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc30::AnyPwr) - } -} -#[doc = "Wake-up Pin Mode Configuration for WUU_Pn\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wupmc31 { - #[doc = "0: Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - LowPwrOnly = 0, - #[doc = "1: Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - AnyPwr = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wupmc31) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WUPMC31` reader - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc31R = crate::BitReader; -impl Wupmc31R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wupmc31 { - match self.bits { - false => Wupmc31::LowPwrOnly, - true => Wupmc31::AnyPwr, - } - } - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_low_pwr_only(&self) -> bool { - *self == Wupmc31::LowPwrOnly - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn is_any_pwr(&self) -> bool { - *self == Wupmc31::AnyPwr - } -} -#[doc = "Field `WUPMC31` writer - Wake-up Pin Mode Configuration for WUU_Pn"] -pub type Wupmc31W<'a, REG> = crate::BitWriter<'a, REG, Wupmc31>; -impl<'a, REG> Wupmc31W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn low_pwr_only(self) -> &'a mut crate::W { - self.variant(Wupmc31::LowPwrOnly) - } - #[doc = "Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn)."] - #[inline(always)] - pub fn any_pwr(self) -> &'a mut crate::W { - self.variant(Wupmc31::AnyPwr) - } -} -impl R { - #[doc = "Bit 0 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc0(&self) -> Wupmc0R { - Wupmc0R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc1(&self) -> Wupmc1R { - Wupmc1R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc2(&self) -> Wupmc2R { - Wupmc2R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc3(&self) -> Wupmc3R { - Wupmc3R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc4(&self) -> Wupmc4R { - Wupmc4R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc5(&self) -> Wupmc5R { - Wupmc5R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc6(&self) -> Wupmc6R { - Wupmc6R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc7(&self) -> Wupmc7R { - Wupmc7R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc8(&self) -> Wupmc8R { - Wupmc8R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc9(&self) -> Wupmc9R { - Wupmc9R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc10(&self) -> Wupmc10R { - Wupmc10R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc11(&self) -> Wupmc11R { - Wupmc11R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc12(&self) -> Wupmc12R { - Wupmc12R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc13(&self) -> Wupmc13R { - Wupmc13R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc14(&self) -> Wupmc14R { - Wupmc14R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc15(&self) -> Wupmc15R { - Wupmc15R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc16(&self) -> Wupmc16R { - Wupmc16R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc17(&self) -> Wupmc17R { - Wupmc17R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc18(&self) -> Wupmc18R { - Wupmc18R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc19(&self) -> Wupmc19R { - Wupmc19R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc20(&self) -> Wupmc20R { - Wupmc20R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc21(&self) -> Wupmc21R { - Wupmc21R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc22(&self) -> Wupmc22R { - Wupmc22R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc23(&self) -> Wupmc23R { - Wupmc23R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc24(&self) -> Wupmc24R { - Wupmc24R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc25(&self) -> Wupmc25R { - Wupmc25R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc26(&self) -> Wupmc26R { - Wupmc26R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc27(&self) -> Wupmc27R { - Wupmc27R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc28(&self) -> Wupmc28R { - Wupmc28R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc29(&self) -> Wupmc29R { - Wupmc29R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc30(&self) -> Wupmc30R { - Wupmc30R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc31(&self) -> Wupmc31R { - Wupmc31R::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc0(&mut self) -> Wupmc0W { - Wupmc0W::new(self, 0) - } - #[doc = "Bit 1 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc1(&mut self) -> Wupmc1W { - Wupmc1W::new(self, 1) - } - #[doc = "Bit 2 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc2(&mut self) -> Wupmc2W { - Wupmc2W::new(self, 2) - } - #[doc = "Bit 3 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc3(&mut self) -> Wupmc3W { - Wupmc3W::new(self, 3) - } - #[doc = "Bit 4 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc4(&mut self) -> Wupmc4W { - Wupmc4W::new(self, 4) - } - #[doc = "Bit 5 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc5(&mut self) -> Wupmc5W { - Wupmc5W::new(self, 5) - } - #[doc = "Bit 6 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc6(&mut self) -> Wupmc6W { - Wupmc6W::new(self, 6) - } - #[doc = "Bit 7 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc7(&mut self) -> Wupmc7W { - Wupmc7W::new(self, 7) - } - #[doc = "Bit 8 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc8(&mut self) -> Wupmc8W { - Wupmc8W::new(self, 8) - } - #[doc = "Bit 9 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc9(&mut self) -> Wupmc9W { - Wupmc9W::new(self, 9) - } - #[doc = "Bit 10 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc10(&mut self) -> Wupmc10W { - Wupmc10W::new(self, 10) - } - #[doc = "Bit 11 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc11(&mut self) -> Wupmc11W { - Wupmc11W::new(self, 11) - } - #[doc = "Bit 12 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc12(&mut self) -> Wupmc12W { - Wupmc12W::new(self, 12) - } - #[doc = "Bit 13 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc13(&mut self) -> Wupmc13W { - Wupmc13W::new(self, 13) - } - #[doc = "Bit 14 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc14(&mut self) -> Wupmc14W { - Wupmc14W::new(self, 14) - } - #[doc = "Bit 15 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc15(&mut self) -> Wupmc15W { - Wupmc15W::new(self, 15) - } - #[doc = "Bit 16 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc16(&mut self) -> Wupmc16W { - Wupmc16W::new(self, 16) - } - #[doc = "Bit 17 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc17(&mut self) -> Wupmc17W { - Wupmc17W::new(self, 17) - } - #[doc = "Bit 18 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc18(&mut self) -> Wupmc18W { - Wupmc18W::new(self, 18) - } - #[doc = "Bit 19 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc19(&mut self) -> Wupmc19W { - Wupmc19W::new(self, 19) - } - #[doc = "Bit 20 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc20(&mut self) -> Wupmc20W { - Wupmc20W::new(self, 20) - } - #[doc = "Bit 21 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc21(&mut self) -> Wupmc21W { - Wupmc21W::new(self, 21) - } - #[doc = "Bit 22 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc22(&mut self) -> Wupmc22W { - Wupmc22W::new(self, 22) - } - #[doc = "Bit 23 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc23(&mut self) -> Wupmc23W { - Wupmc23W::new(self, 23) - } - #[doc = "Bit 24 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc24(&mut self) -> Wupmc24W { - Wupmc24W::new(self, 24) - } - #[doc = "Bit 25 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc25(&mut self) -> Wupmc25W { - Wupmc25W::new(self, 25) - } - #[doc = "Bit 26 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc26(&mut self) -> Wupmc26W { - Wupmc26W::new(self, 26) - } - #[doc = "Bit 27 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc27(&mut self) -> Wupmc27W { - Wupmc27W::new(self, 27) - } - #[doc = "Bit 28 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc28(&mut self) -> Wupmc28W { - Wupmc28W::new(self, 28) - } - #[doc = "Bit 29 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc29(&mut self) -> Wupmc29W { - Wupmc29W::new(self, 29) - } - #[doc = "Bit 30 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc30(&mut self) -> Wupmc30W { - Wupmc30W::new(self, 30) - } - #[doc = "Bit 31 - Wake-up Pin Mode Configuration for WUU_Pn"] - #[inline(always)] - pub fn wupmc31(&mut self) -> Wupmc31W { - Wupmc31W::new(self, 31) - } -} -#[doc = "Pin Mode Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pmc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PmcSpec; -impl crate::RegisterSpec for PmcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`pmc::R`](R) reader structure"] -impl crate::Readable for PmcSpec {} -#[doc = "`write(|w| ..)` method takes [`pmc::W`](W) writer structure"] -impl crate::Writable for PmcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PMC to value 0"] -impl crate::Resettable for PmcSpec {} diff --git a/mcxa276-pac/src/wuu0/verid.rs b/mcxa276-pac/src/wuu0/verid.rs deleted file mode 100644 index 5ba468f42..000000000 --- a/mcxa276-pac/src/wuu0/verid.rs +++ /dev/null @@ -1,76 +0,0 @@ -#[doc = "Register `VERID` reader"] -pub type R = crate::R; -#[doc = "Feature Specification Number\n\nValue on reset: 1"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Feature { - #[doc = "0: Standard features implemented"] - Standard = 0, - #[doc = "1: Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for external pin/filter detection during all power modes enabled."] - FiltAllPwr = 1, -} -impl From for u16 { - #[inline(always)] - fn from(variant: Feature) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Feature { - type Ux = u16; -} -impl crate::IsEnum for Feature {} -#[doc = "Field `FEATURE` reader - Feature Specification Number"] -pub type FeatureR = crate::FieldReader; -impl FeatureR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Feature::Standard), - 1 => Some(Feature::FiltAllPwr), - _ => None, - } - } - #[doc = "Standard features implemented"] - #[inline(always)] - pub fn is_standard(&self) -> bool { - *self == Feature::Standard - } - #[doc = "Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for external pin/filter detection during all power modes enabled."] - #[inline(always)] - pub fn is_filt_all_pwr(&self) -> bool { - *self == Feature::FiltAllPwr - } -} -#[doc = "Field `MINOR` reader - Minor Version Number"] -pub type MinorR = crate::FieldReader; -#[doc = "Field `MAJOR` reader - Major Version Number"] -pub type MajorR = crate::FieldReader; -impl R { - #[doc = "Bits 0:15 - Feature Specification Number"] - #[inline(always)] - pub fn feature(&self) -> FeatureR { - FeatureR::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Minor Version Number"] - #[inline(always)] - pub fn minor(&self) -> MinorR { - MinorR::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - Major Version Number"] - #[inline(always)] - pub fn major(&self) -> MajorR { - MajorR::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct VeridSpec; -impl crate::RegisterSpec for VeridSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`verid::R`](R) reader structure"] -impl crate::Readable for VeridSpec {} -#[doc = "`reset()` method sets VERID to value 0x0100_0001"] -impl crate::Resettable for VeridSpec { - const RESET_VALUE: u32 = 0x0100_0001; -} diff --git a/mcxa276-pac/src/wwdt0.rs b/mcxa276-pac/src/wwdt0.rs deleted file mode 100644 index 5c60c190d..000000000 --- a/mcxa276-pac/src/wwdt0.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - mod_: Mod, - tc: Tc, - feed: Feed, - tv: Tv, - _reserved4: [u8; 0x04], - warnint: Warnint, - window: Window, -} -impl RegisterBlock { - #[doc = "0x00 - Mode"] - #[inline(always)] - pub const fn mod_(&self) -> &Mod { - &self.mod_ - } - #[doc = "0x04 - Timer Constant"] - #[inline(always)] - pub const fn tc(&self) -> &Tc { - &self.tc - } - #[doc = "0x08 - Feed Sequence"] - #[inline(always)] - pub const fn feed(&self) -> &Feed { - &self.feed - } - #[doc = "0x0c - Timer Value"] - #[inline(always)] - pub const fn tv(&self) -> &Tv { - &self.tv - } - #[doc = "0x14 - Warning Interrupt Compare Value"] - #[inline(always)] - pub const fn warnint(&self) -> &Warnint { - &self.warnint - } - #[doc = "0x18 - Window Compare Value"] - #[inline(always)] - pub const fn window(&self) -> &Window { - &self.window - } -} -#[doc = "MOD (rw) register accessor: Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mod_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mod_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mod_`] module"] -#[doc(alias = "MOD")] -pub type Mod = crate::Reg; -#[doc = "Mode"] -pub mod mod_; -#[doc = "TC (rw) register accessor: Timer Constant\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] module"] -#[doc(alias = "TC")] -pub type Tc = crate::Reg; -#[doc = "Timer Constant"] -pub mod tc; -#[doc = "FEED (w) register accessor: Feed Sequence\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`feed::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@feed`] module"] -#[doc(alias = "FEED")] -pub type Feed = crate::Reg; -#[doc = "Feed Sequence"] -pub mod feed; -#[doc = "TV (r) register accessor: Timer Value\n\nYou can [`read`](crate::Reg::read) this register and get [`tv::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tv`] module"] -#[doc(alias = "TV")] -pub type Tv = crate::Reg; -#[doc = "Timer Value"] -pub mod tv; -#[doc = "WARNINT (rw) register accessor: Warning Interrupt Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`warnint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`warnint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@warnint`] module"] -#[doc(alias = "WARNINT")] -pub type Warnint = crate::Reg; -#[doc = "Warning Interrupt Compare Value"] -pub mod warnint; -#[doc = "WINDOW (rw) register accessor: Window Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`window::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`window::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@window`] module"] -#[doc(alias = "WINDOW")] -pub type Window = crate::Reg; -#[doc = "Window Compare Value"] -pub mod window; diff --git a/mcxa276-pac/src/wwdt0/feed.rs b/mcxa276-pac/src/wwdt0/feed.rs deleted file mode 100644 index 7b0acaead..000000000 --- a/mcxa276-pac/src/wwdt0/feed.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `FEED` writer"] -pub type W = crate::W; -#[doc = "Field `FEED` writer - Feed Value"] -pub type FeedW<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl W { - #[doc = "Bits 0:7 - Feed Value"] - #[inline(always)] - pub fn feed(&mut self) -> FeedW { - FeedW::new(self, 0) - } -} -#[doc = "Feed Sequence\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`feed::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FeedSpec; -impl crate::RegisterSpec for FeedSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`feed::W`](W) writer structure"] -impl crate::Writable for FeedSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets FEED to value 0"] -impl crate::Resettable for FeedSpec {} diff --git a/mcxa276-pac/src/wwdt0/mod_.rs b/mcxa276-pac/src/wwdt0/mod_.rs deleted file mode 100644 index 8a3531328..000000000 --- a/mcxa276-pac/src/wwdt0/mod_.rs +++ /dev/null @@ -1,463 +0,0 @@ -#[doc = "Register `MOD` reader"] -pub type R = crate::R; -#[doc = "Register `MOD` writer"] -pub type W = crate::W; -#[doc = "Watchdog Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wden { - #[doc = "0: Timer stopped"] - Stop = 0, - #[doc = "1: Timer running"] - Run = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wden) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDEN` reader - Watchdog Enable"] -pub type WdenR = crate::BitReader; -impl WdenR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wden { - match self.bits { - false => Wden::Stop, - true => Wden::Run, - } - } - #[doc = "Timer stopped"] - #[inline(always)] - pub fn is_stop(&self) -> bool { - *self == Wden::Stop - } - #[doc = "Timer running"] - #[inline(always)] - pub fn is_run(&self) -> bool { - *self == Wden::Run - } -} -#[doc = "Field `WDEN` writer - Watchdog Enable"] -pub type WdenW<'a, REG> = crate::BitWriter<'a, REG, Wden>; -impl<'a, REG> WdenW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Timer stopped"] - #[inline(always)] - pub fn stop(self) -> &'a mut crate::W { - self.variant(Wden::Stop) - } - #[doc = "Timer running"] - #[inline(always)] - pub fn run(self) -> &'a mut crate::W { - self.variant(Wden::Run) - } -} -#[doc = "Watchdog Reset Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wdreset { - #[doc = "0: Interrupt"] - Interrupt = 0, - #[doc = "1: Reset"] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wdreset) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDRESET` reader - Watchdog Reset Enable"] -pub type WdresetR = crate::BitReader; -impl WdresetR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wdreset { - match self.bits { - false => Wdreset::Interrupt, - true => Wdreset::Reset, - } - } - #[doc = "Interrupt"] - #[inline(always)] - pub fn is_interrupt(&self) -> bool { - *self == Wdreset::Interrupt - } - #[doc = "Reset"] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Wdreset::Reset - } -} -#[doc = "Field `WDRESET` writer - Watchdog Reset Enable"] -pub type WdresetW<'a, REG> = crate::BitWriter<'a, REG, Wdreset>; -impl<'a, REG> WdresetW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Interrupt"] - #[inline(always)] - pub fn interrupt(self) -> &'a mut crate::W { - self.variant(Wdreset::Interrupt) - } - #[doc = "Reset"] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Wdreset::Reset) - } -} -#[doc = "Watchdog Timeout Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wdtof { - #[doc = "0: Watchdog event has not occurred."] - Clear = 0, - #[doc = "1: Watchdog event has occurred (causes a chip reset if WDRESET = 1)."] - Reset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wdtof) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDTOF` reader - Watchdog Timeout Flag"] -pub type WdtofR = crate::BitReader; -impl WdtofR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wdtof { - match self.bits { - false => Wdtof::Clear, - true => Wdtof::Reset, - } - } - #[doc = "Watchdog event has not occurred."] - #[inline(always)] - pub fn is_clear(&self) -> bool { - *self == Wdtof::Clear - } - #[doc = "Watchdog event has occurred (causes a chip reset if WDRESET = 1)."] - #[inline(always)] - pub fn is_reset(&self) -> bool { - *self == Wdtof::Reset - } -} -#[doc = "Field `WDTOF` writer - Watchdog Timeout Flag"] -pub type WdtofW<'a, REG> = crate::BitWriter<'a, REG, Wdtof>; -impl<'a, REG> WdtofW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Watchdog event has not occurred."] - #[inline(always)] - pub fn clear(self) -> &'a mut crate::W { - self.variant(Wdtof::Clear) - } - #[doc = "Watchdog event has occurred (causes a chip reset if WDRESET = 1)."] - #[inline(always)] - pub fn reset(self) -> &'a mut crate::W { - self.variant(Wdtof::Reset) - } -} -#[doc = "Warning Interrupt Flag\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wdint { - #[doc = "0: No flag"] - NoFlag = 0, - #[doc = "1: Flag"] - Flag = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wdint) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDINT` reader - Warning Interrupt Flag"] -pub type WdintR = crate::BitReader; -impl WdintR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wdint { - match self.bits { - false => Wdint::NoFlag, - true => Wdint::Flag, - } - } - #[doc = "No flag"] - #[inline(always)] - pub fn is_no_flag(&self) -> bool { - *self == Wdint::NoFlag - } - #[doc = "Flag"] - #[inline(always)] - pub fn is_flag(&self) -> bool { - *self == Wdint::Flag - } -} -#[doc = "Field `WDINT` writer - Warning Interrupt Flag"] -pub type WdintW<'a, REG> = crate::BitWriter1C<'a, REG, Wdint>; -impl<'a, REG> WdintW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No flag"] - #[inline(always)] - pub fn no_flag(self) -> &'a mut crate::W { - self.variant(Wdint::NoFlag) - } - #[doc = "Flag"] - #[inline(always)] - pub fn flag(self) -> &'a mut crate::W { - self.variant(Wdint::Flag) - } -} -#[doc = "Watchdog Update Mode\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Wdprotect { - #[doc = "0: Flexible"] - Flexible = 0, - #[doc = "1: Threshold"] - Threshold = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Wdprotect) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `WDPROTECT` reader - Watchdog Update Mode"] -pub type WdprotectR = crate::BitReader; -impl WdprotectR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Wdprotect { - match self.bits { - false => Wdprotect::Flexible, - true => Wdprotect::Threshold, - } - } - #[doc = "Flexible"] - #[inline(always)] - pub fn is_flexible(&self) -> bool { - *self == Wdprotect::Flexible - } - #[doc = "Threshold"] - #[inline(always)] - pub fn is_threshold(&self) -> bool { - *self == Wdprotect::Threshold - } -} -#[doc = "Field `WDPROTECT` writer - Watchdog Update Mode"] -pub type WdprotectW<'a, REG> = crate::BitWriter<'a, REG, Wdprotect>; -impl<'a, REG> WdprotectW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Flexible"] - #[inline(always)] - pub fn flexible(self) -> &'a mut crate::W { - self.variant(Wdprotect::Flexible) - } - #[doc = "Threshold"] - #[inline(always)] - pub fn threshold(self) -> &'a mut crate::W { - self.variant(Wdprotect::Threshold) - } -} -#[doc = "Lock\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Lock { - #[doc = "0: No Lock"] - NoLock = 0, - #[doc = "1: Lock"] - Lock = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Lock) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `LOCK` reader - Lock"] -pub type LockR = crate::BitReader; -impl LockR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Lock { - match self.bits { - false => Lock::NoLock, - true => Lock::Lock, - } - } - #[doc = "No Lock"] - #[inline(always)] - pub fn is_no_lock(&self) -> bool { - *self == Lock::NoLock - } - #[doc = "Lock"] - #[inline(always)] - pub fn is_lock(&self) -> bool { - *self == Lock::Lock - } -} -#[doc = "Field `LOCK` writer - Lock"] -pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>; -impl<'a, REG> LockW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No Lock"] - #[inline(always)] - pub fn no_lock(self) -> &'a mut crate::W { - self.variant(Lock::NoLock) - } - #[doc = "Lock"] - #[inline(always)] - pub fn lock(self) -> &'a mut crate::W { - self.variant(Lock::Lock) - } -} -#[doc = "Debug Enable\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum DebugEn { - #[doc = "0: Disabled"] - Disable = 0, - #[doc = "1: Enabled"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: DebugEn) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `DEBUG_EN` reader - Debug Enable"] -pub type DebugEnR = crate::BitReader; -impl DebugEnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> DebugEn { - match self.bits { - false => DebugEn::Disable, - true => DebugEn::Enable, - } - } - #[doc = "Disabled"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == DebugEn::Disable - } - #[doc = "Enabled"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == DebugEn::Enable - } -} -#[doc = "Field `DEBUG_EN` writer - Debug Enable"] -pub type DebugEnW<'a, REG> = crate::BitWriter<'a, REG, DebugEn>; -impl<'a, REG> DebugEnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Disabled"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(DebugEn::Disable) - } - #[doc = "Enabled"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(DebugEn::Enable) - } -} -impl R { - #[doc = "Bit 0 - Watchdog Enable"] - #[inline(always)] - pub fn wden(&self) -> WdenR { - WdenR::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Watchdog Reset Enable"] - #[inline(always)] - pub fn wdreset(&self) -> WdresetR { - WdresetR::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Watchdog Timeout Flag"] - #[inline(always)] - pub fn wdtof(&self) -> WdtofR { - WdtofR::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Warning Interrupt Flag"] - #[inline(always)] - pub fn wdint(&self) -> WdintR { - WdintR::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Watchdog Update Mode"] - #[inline(always)] - pub fn wdprotect(&self) -> WdprotectR { - WdprotectR::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - Lock"] - #[inline(always)] - pub fn lock(&self) -> LockR { - LockR::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Debug Enable"] - #[inline(always)] - pub fn debug_en(&self) -> DebugEnR { - DebugEnR::new(((self.bits >> 6) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Watchdog Enable"] - #[inline(always)] - pub fn wden(&mut self) -> WdenW { - WdenW::new(self, 0) - } - #[doc = "Bit 1 - Watchdog Reset Enable"] - #[inline(always)] - pub fn wdreset(&mut self) -> WdresetW { - WdresetW::new(self, 1) - } - #[doc = "Bit 2 - Watchdog Timeout Flag"] - #[inline(always)] - pub fn wdtof(&mut self) -> WdtofW { - WdtofW::new(self, 2) - } - #[doc = "Bit 3 - Warning Interrupt Flag"] - #[inline(always)] - pub fn wdint(&mut self) -> WdintW { - WdintW::new(self, 3) - } - #[doc = "Bit 4 - Watchdog Update Mode"] - #[inline(always)] - pub fn wdprotect(&mut self) -> WdprotectW { - WdprotectW::new(self, 4) - } - #[doc = "Bit 5 - Lock"] - #[inline(always)] - pub fn lock(&mut self) -> LockW { - LockW::new(self, 5) - } - #[doc = "Bit 6 - Debug Enable"] - #[inline(always)] - pub fn debug_en(&mut self) -> DebugEnW { - DebugEnW::new(self, 6) - } -} -#[doc = "Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mod_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mod_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ModSpec; -impl crate::RegisterSpec for ModSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`mod_::R`](R) reader structure"] -impl crate::Readable for ModSpec {} -#[doc = "`write(|w| ..)` method takes [`mod_::W`](W) writer structure"] -impl crate::Writable for ModSpec { - type Safety = crate::Unsafe; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x08; -} -#[doc = "`reset()` method sets MOD to value 0"] -impl crate::Resettable for ModSpec {} diff --git a/mcxa276-pac/src/wwdt0/tc.rs b/mcxa276-pac/src/wwdt0/tc.rs deleted file mode 100644 index cb0769051..000000000 --- a/mcxa276-pac/src/wwdt0/tc.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `TC` reader"] -pub type R = crate::R; -#[doc = "Register `TC` writer"] -pub type W = crate::W; -#[doc = "Field `COUNT` reader - Watchdog Timeout Value"] -pub type CountR = crate::FieldReader; -#[doc = "Field `COUNT` writer - Watchdog Timeout Value"] -pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; -impl R { - #[doc = "Bits 0:23 - Watchdog Timeout Value"] - #[inline(always)] - pub fn count(&self) -> CountR { - CountR::new(self.bits & 0x00ff_ffff) - } -} -impl W { - #[doc = "Bits 0:23 - Watchdog Timeout Value"] - #[inline(always)] - pub fn count(&mut self) -> CountW { - CountW::new(self, 0) - } -} -#[doc = "Timer Constant\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TcSpec; -impl crate::RegisterSpec for TcSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tc::R`](R) reader structure"] -impl crate::Readable for TcSpec {} -#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] -impl crate::Writable for TcSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets TC to value 0xff"] -impl crate::Resettable for TcSpec { - const RESET_VALUE: u32 = 0xff; -} diff --git a/mcxa276-pac/src/wwdt0/tv.rs b/mcxa276-pac/src/wwdt0/tv.rs deleted file mode 100644 index cf5542933..000000000 --- a/mcxa276-pac/src/wwdt0/tv.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[doc = "Register `TV` reader"] -pub type R = crate::R; -#[doc = "Field `COUNT` reader - Counter Timer Value"] -pub type CountR = crate::FieldReader; -impl R { - #[doc = "Bits 0:23 - Counter Timer Value"] - #[inline(always)] - pub fn count(&self) -> CountR { - CountR::new(self.bits & 0x00ff_ffff) - } -} -#[doc = "Timer Value\n\nYou can [`read`](crate::Reg::read) this register and get [`tv::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct TvSpec; -impl crate::RegisterSpec for TvSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`tv::R`](R) reader structure"] -impl crate::Readable for TvSpec {} -#[doc = "`reset()` method sets TV to value 0xff"] -impl crate::Resettable for TvSpec { - const RESET_VALUE: u32 = 0xff; -} diff --git a/mcxa276-pac/src/wwdt0/warnint.rs b/mcxa276-pac/src/wwdt0/warnint.rs deleted file mode 100644 index 9c62907e1..000000000 --- a/mcxa276-pac/src/wwdt0/warnint.rs +++ /dev/null @@ -1,35 +0,0 @@ -#[doc = "Register `WARNINT` reader"] -pub type R = crate::R; -#[doc = "Register `WARNINT` writer"] -pub type W = crate::W; -#[doc = "Field `WARNINT` reader - Watchdog Warning Interrupt Compare Value"] -pub type WarnintR = crate::FieldReader; -#[doc = "Field `WARNINT` writer - Watchdog Warning Interrupt Compare Value"] -pub type WarnintW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -impl R { - #[doc = "Bits 0:9 - Watchdog Warning Interrupt Compare Value"] - #[inline(always)] - pub fn warnint(&self) -> WarnintR { - WarnintR::new((self.bits & 0x03ff) as u16) - } -} -impl W { - #[doc = "Bits 0:9 - Watchdog Warning Interrupt Compare Value"] - #[inline(always)] - pub fn warnint(&mut self) -> WarnintW { - WarnintW::new(self, 0) - } -} -#[doc = "Warning Interrupt Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`warnint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`warnint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WarnintSpec; -impl crate::RegisterSpec for WarnintSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`warnint::R`](R) reader structure"] -impl crate::Readable for WarnintSpec {} -#[doc = "`write(|w| ..)` method takes [`warnint::W`](W) writer structure"] -impl crate::Writable for WarnintSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WARNINT to value 0"] -impl crate::Resettable for WarnintSpec {} diff --git a/mcxa276-pac/src/wwdt0/window.rs b/mcxa276-pac/src/wwdt0/window.rs deleted file mode 100644 index 455c8c8a9..000000000 --- a/mcxa276-pac/src/wwdt0/window.rs +++ /dev/null @@ -1,37 +0,0 @@ -#[doc = "Register `WINDOW` reader"] -pub type R = crate::R; -#[doc = "Register `WINDOW` writer"] -pub type W = crate::W; -#[doc = "Field `WINDOW` reader - Watchdog Window Value"] -pub type WindowR = crate::FieldReader; -#[doc = "Field `WINDOW` writer - Watchdog Window Value"] -pub type WindowW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; -impl R { - #[doc = "Bits 0:23 - Watchdog Window Value"] - #[inline(always)] - pub fn window(&self) -> WindowR { - WindowR::new(self.bits & 0x00ff_ffff) - } -} -impl W { - #[doc = "Bits 0:23 - Watchdog Window Value"] - #[inline(always)] - pub fn window(&mut self) -> WindowW { - WindowW::new(self, 0) - } -} -#[doc = "Window Compare Value\n\nYou can [`read`](crate::Reg::read) this register and get [`window::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`window::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WindowSpec; -impl crate::RegisterSpec for WindowSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`window::R`](R) reader structure"] -impl crate::Readable for WindowSpec {} -#[doc = "`write(|w| ..)` method takes [`window::W`](W) writer structure"] -impl crate::Writable for WindowSpec { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets WINDOW to value 0x00ff_ffff"] -impl crate::Resettable for WindowSpec { - const RESET_VALUE: u32 = 0x00ff_ffff; -} diff --git a/src/adc.rs b/src/adc.rs index dd6530605..f56d744c6 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,4 +1,4 @@ -//! ADC driver +//! ADC driver use crate::pac; use core::sync::atomic::{AtomicBool, Ordering}; @@ -285,8 +285,7 @@ impl Adc { 1 => { adc.cmdl1().write(|w| { w.adch().variant(config.channel_number) - .ctype().variant(config.sample_channel_mode) - .mode().variant(config.conversion_resolution_mode) + .mode().variant(config.conversion_resolution_mode) }); adc.cmdh1().write(|w| unsafe { w.next().variant(config.chained_next_command_number) @@ -373,4 +372,4 @@ pub fn on_interrupt() { pub struct AdcHandler; impl crate::interrupt::typelevel::Handler for AdcHandler { unsafe fn on_interrupt() { on_interrupt(); } -} \ No newline at end of file +} -- cgit From 4fcc74dbd3906db35a56dc179b08b23bfd5bdffa Mon Sep 17 00:00:00 2001 From: Bogdan Petru Chircu Mare Date: Thu, 6 Nov 2025 13:04:42 -0800 Subject: chore(mcxa276): pin mcxa-pac to a9dd33; docs: OS_EVENT/WAKETIMER0 fix now historical with SVD 25.06.00 --- Cargo.toml | 2 +- README.txt | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index fd3fba042..cf7ba854e 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,7 +13,7 @@ name = "embassy_mcxa276" [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m-rt = { version = "0.7", features = ["device"] } -mcxa276-pac = { git = "https://github.com/bogdan-petru/mcxa-pac", features = ["rt"] } +mcxa276-pac = { git = "https://github.com/bogdan-petru/mcxa-pac", features = ["rt"], rev = "a9dd330149912c26f252f0f3c419f6435c1216e2", version = "0.1.0" } embedded-io = "0.6" # Optional defmt support defmt = { version = "0.3", optional = true } diff --git a/README.txt b/README.txt index 7baf8a9cb..80fa81b07 100644 --- a/README.txt +++ b/README.txt @@ -312,6 +312,8 @@ cargo build --features "lpuart2 rtc0" --example rtc_alarm ### Critical Fix: MCXA276 Interrupt Vector Table + +Update (SVD 25.06.00, mcxa-pac a9dd33): No manual PAC edits are required anymore. OS_EVENT and WAKETIMER0 are present and the vector table is correct. The section below is kept for historical context. **Problem:** The OSTIMER examples crashed during interrupt handling with a hardfault (SP=0x00000000). Investigation revealed the OS_EVENT interrupt vector was NULL in the vector table, causing the CPU to jump to address 0 when OSTIMER interrupts fired. **Root Cause:** The `mcxa276-pac/src/lib.rs` file (generated from the SVD file) was missing the `WAKETIMER0` interrupt handler declaration. This caused the `__INTERRUPTS` array to have an off-by-one error, placing OS_EVENT at IRQ 58 instead of the correct IRQ 57 position. @@ -337,4 +339,4 @@ Using `#[inline(always)]` can cause the Rust compiler to generate incorrect asse ## License -This project is licensed under MIT OR Apache-2.0. +This project is licensed under MIT OR Apache-2.0. \ No newline at end of file -- cgit From a71eff2e1cea55b393e793c023b8e51e5cc369a1 Mon Sep 17 00:00:00 2001 From: Bogdan Petru Chircu Mare Date: Thu, 6 Nov 2025 21:51:56 -0800 Subject: Fix uart_interrupt example: enable RX interrupts in peripheral The uart_interrupt example was not echoing received characters because the RX interrupt enable bit (RIE) was not being set in the LPUART control register. The NVIC interrupt was configured and the handler was installed, but the peripheral itself was not generating interrupts. Added uart.enable_rx_interrupts() call to enable RX data interrupts in the LPUART2 peripheral before entering the main loop. --- README.txt | 4 ++++ examples/uart_interrupt.rs | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/README.txt b/README.txt index 80fa81b07..ae80ca8ef 100644 --- a/README.txt +++ b/README.txt @@ -287,6 +287,10 @@ probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-non probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/rtc_alarm probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_polling probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_interrupt +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_async +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_counter +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_race_test ``` How I tested on Windows diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs index b309ce973..85743bb64 100644 --- a/examples/uart_interrupt.rs +++ b/examples/uart_interrupt.rs @@ -45,9 +45,11 @@ async fn main(_spawner: Spawner) { // Configure LPUART2 interrupt for UART operation BEFORE any UART usage hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3)); - // Manually install the interrupt handler + // Manually install the interrupt handler and enable RX IRQs in the peripheral unsafe { hal::interrupt::LPUART2.install_handler(lpuart2_handler); + // Enable RX interrupts so the handler actually fires on incoming bytes + uart.enable_rx_interrupts(); } // Print welcome message -- cgit From cb2ac2790f4b037056f9571abeb4d62360199426 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 7 Nov 2025 10:06:55 -0800 Subject: Reduce number of features We don't need features for drivers that always exist. Signed-off-by: Felipe Balbi --- Cargo.toml | 45 +++++------- examples/adc_interrupt.rs | 54 ++++++--------- examples/adc_polling.rs | 47 +++++-------- examples/blink.rs | 6 -- examples/hello.rs | 14 +--- examples/lpuart_buffered.rs | 6 -- examples/lpuart_polling.rs | 16 +---- examples/ostimer_alarm.rs | 16 +---- examples/ostimer_async.rs | 20 +----- examples/ostimer_counter.rs | 16 +---- examples/ostimer_race_test.rs | 17 +---- examples/rtc_alarm.rs | 25 ++----- examples/uart_interrupt.rs | 21 +----- src/adc.rs | 155 ++++++++++++++++++++++++------------------ src/clocks.rs | 9 ++- src/gpio.rs | 2 +- src/interrupt.rs | 2 +- src/lib.rs | 59 +++++----------- src/lpuart/buffered.rs | 2 +- src/lpuart/mod.rs | 2 +- src/ostimer.rs | 8 +-- src/pins.rs | 1 - src/rtc.rs | 28 ++++---- src/uart.rs | 9 ++- 24 files changed, 211 insertions(+), 369 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index cf7ba854e..8ec547494 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,22 +13,18 @@ name = "embassy_mcxa276" [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m-rt = { version = "0.7", features = ["device"] } -mcxa276-pac = { git = "https://github.com/bogdan-petru/mcxa-pac", features = ["rt"], rev = "a9dd330149912c26f252f0f3c419f6435c1216e2", version = "0.1.0" } -embedded-io = "0.6" -# Optional defmt support -defmt = { version = "0.3", optional = true } -defmt-rtt = { version = "0.4", optional = true } -rtt-target = { version = "0.4", optional = true } -panic-probe = { version = "0.3", features = ["print-defmt"], optional = true } +critical-section = "1.2.0" +defmt = { version = "1.0", optional = true } +embassy-embedded-hal = "0.5.0" embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } +embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] } +embassy-sync = "0.7.2" embassy-time = "0.5.0" embassy-time-driver = "0.2.1" -embassy-sync = "0.7.2" -embassy-embedded-hal = "0.5.0" -embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] } -critical-section = "1.2.0" -paste = "1.0.15" +embedded-io = "0.6" heapless = "0.8" +mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "f0281344c605ab24c38979553b41a1655c50625c", version = "0.1.0" } +paste = "1.0.15" embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [ "unproven", @@ -39,25 +35,20 @@ embedded-hal-nb = { version = "1.0" } embedded-io-async = { version = "0.6.1" } nb = "1.1.0" +[dev-dependencies] +defmt-rtt = "1.0" +panic-probe = { version = "1.0", features = ["print-defmt"] } + [features] default = [] -uart-debug = [] -gpio = [] -lpuart2 = [] -ostimer0 = [] -rtc0 = [] -adc1 = [] -rt = [] + # Base defmt feature enables core + panic handler # Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) -defmt = ["dep:defmt", "dep:panic-probe"] -# RTT logger -# Usage: cargo embed --features "defmt defmt-rtt lpuart2" --example hello -# or: PROBE_RS_PROBE= cargo embed --features "defmt defmt-rtt lpuart2" --example hello -defmt-rtt = ["dep:defmt-rtt", "dep:rtt-target"] -# Optional: UART-based defmt (no RTT). Enable with `--features defmt-uart defmt`. -# defmt-uart = [] # Removed - no longer needed +defmt = ["dep:defmt"] + +rt = [] +unstable-pac = [] [[example]] name = "hello" @@ -116,6 +107,4 @@ opt-level = "s" debug = 2 opt-level = 1 -[dev-dependencies] - diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs index 452eaae01..26afd70b4 100644 --- a/examples/adc_interrupt.rs +++ b/examples/adc_interrupt.rs @@ -1,28 +1,23 @@ #![no_std] #![no_main] -use embassy_mcxa276 as hal; use cortex_m; use embassy_executor::Spawner; +use embassy_mcxa276 as hal; -use hal::adc::{TriggerPriorityPolicy, LpadcConfig}; -use hal::pac::adc1::cfg::{Refsel, Pwrsel}; -use hal::pac::adc1::tctrl::{Tcmd}; +use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::{CalAvgs}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; use hal::uart; mod common; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; +use {defmt_rtt as _, panic_probe as _}; -use hal::bind_interrupts; use hal::InterruptExt; +use hal::bind_interrupts; bind_interrupts!(struct Irqs { ADC1 => hal::adc::AdcHandler; @@ -40,7 +35,7 @@ async fn main(_spawner: Spawner) { common::init_uart2(hal::pac()); } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); @@ -48,19 +43,18 @@ async fn main(_spawner: Spawner) { unsafe { common::init_adc(hal::pac()); } - - + let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, }; let adc = hal::adc::Adc::::new(p.ADC1, adc_config); @@ -78,7 +72,7 @@ async fn main(_spawner: Spawner) { adc.set_conv_trigger_config(0, &conv_trigger_config); uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); - + adc.enable_interrupt(0x1); unsafe { @@ -92,15 +86,9 @@ async fn main(_spawner: Spawner) { loop { adc.do_software_trigger(1); while !adc.is_interrupt_triggered() { - // Wait until the interrupt is triggered + // Wait until the interrupt is triggered } uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); //TBD need to print the value } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} \ No newline at end of file diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs index 7cb728e91..90be87c3f 100644 --- a/examples/adc_polling.rs +++ b/examples/adc_polling.rs @@ -5,27 +5,21 @@ use embassy_mcxa276 as hal; use embassy_executor::Spawner; -use hal::adc::{TriggerPriorityPolicy, LpadcConfig, ConvResult}; -use hal::pac::adc1::cfg::{Refsel, Pwrsel}; -use hal::pac::adc1::tctrl::{Tcmd}; +use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::{CalAvgs}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; use hal::uart; mod common; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; +use {defmt_rtt as _, panic_probe as _}; use core::fmt::Write; use heapless::String; - const G_LPADC_RESULT_SHIFT: u32 = 0; #[embassy_executor::main] @@ -44,19 +38,18 @@ async fn main(_spawner: Spawner) { unsafe { common::init_adc(hal::pac()); } - - + let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, }; let adc = hal::adc::Adc::::new(p.ADC1, adc_config); @@ -74,7 +67,7 @@ async fn main(_spawner: Spawner) { adc.set_conv_trigger_config(0, &conv_trigger_config); uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); - + loop { adc.do_software_trigger(1); let mut result: Option = None; @@ -87,9 +80,3 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking(&buf); } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} \ No newline at end of file diff --git a/examples/blink.rs b/examples/blink.rs index 6289ac14e..a9b6e7093 100644 --- a/examples/blink.rs +++ b/examples/blink.rs @@ -85,9 +85,3 @@ async fn main(_spawner: Spawner) { Timer::after(Duration::from_millis(1000)).await; } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/hello.rs b/examples/hello.rs index 591bf2460..e39adaced 100644 --- a/examples/hello.rs +++ b/examples/hello.rs @@ -7,12 +7,7 @@ use hal::uart; mod common; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; +use {defmt_rtt as _, panic_probe as _}; /// Simple helper to write a byte as hex to UART fn write_hex_byte(uart: &hal::uart::Uart, byte: u8) { @@ -25,7 +20,6 @@ fn write_hex_byte(uart: &hal::uart::Uart, byte: u8) { async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); - #[cfg(feature = "defmt")] defmt::info!("boot"); // Board-level init for UART2 clocks and pins. @@ -118,9 +112,3 @@ fn parse_u8(bytes: &[u8]) -> Result { } Ok(result) } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs index 88f256096..d0d4d2ee0 100644 --- a/examples/lpuart_buffered.rs +++ b/examples/lpuart_buffered.rs @@ -80,9 +80,3 @@ async fn main(_spawner: Spawner) { tx.write_all(&buf[..]).await.unwrap(); } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/lpuart_polling.rs b/examples/lpuart_polling.rs index c83c959e8..f9172de40 100644 --- a/examples/lpuart_polling.rs +++ b/examples/lpuart_polling.rs @@ -1,16 +1,11 @@ #![no_std] #![no_main] -use crate::hal::lpuart::{lib, Config, Lpuart}; +use crate::hal::lpuart::{Config, Lpuart, lib}; use embassy_executor::Spawner; use embassy_mcxa276 as hal; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; +use {defmt_rtt as _, panic_probe as _}; mod common; @@ -19,7 +14,6 @@ async fn main(_spawner: Spawner) { let _p = hal::init(hal::config::Config::default()); let p2 = lib::init(); - #[cfg(feature = "defmt")] defmt::info!("boot"); // Board-level init for UART2 clocks and pins. @@ -59,9 +53,3 @@ async fn main(_spawner: Spawner) { tx.blocking_write(&buf).unwrap(); } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs index 823e37c15..eca669509 100644 --- a/examples/ostimer_alarm.rs +++ b/examples/ostimer_alarm.rs @@ -9,12 +9,7 @@ use hal::uart; mod common; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; +use {defmt_rtt as _, panic_probe as _}; use embassy_mcxa276::bind_interrupts; @@ -61,7 +56,8 @@ async fn main(_spawner: Spawner) { init_match_max: true, clock_frequency_hz: 1_000_000, // 1MHz }; - let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); + let ostimer = + hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); // Create alarm with callback let alarm = hal::ostimer::Alarm::new() @@ -118,9 +114,3 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking("Example complete\n"); } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/ostimer_async.rs b/examples/ostimer_async.rs index 181ce58ef..37fb3b3d1 100644 --- a/examples/ostimer_async.rs +++ b/examples/ostimer_async.rs @@ -7,16 +7,9 @@ use hal::uart; mod common; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; - -use embassy_time::{Duration, Timer}; - use embassy_mcxa276::bind_interrupts; +use embassy_time::{Duration, Timer}; +use {defmt_rtt as _, panic_probe as _}; // Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed. bind_interrupts!(struct Irqs { @@ -57,20 +50,11 @@ async fn main(_spawner: Spawner) { // Removed force-pend; rely on real hardware match to trigger OS_EVENT. // Log using defmt if enabled - #[cfg(feature = "defmt")] defmt::info!("OSTIMER async example starting..."); loop { - #[cfg(feature = "defmt")] defmt::info!("tick"); - #[cfg(not(feature = "defmt"))] uart.write_str_blocking("tick\n"); Timer::after(Duration::from_millis(1000)).await; } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs index 3af0f03f2..1f5bdf434 100644 --- a/examples/ostimer_counter.rs +++ b/examples/ostimer_counter.rs @@ -9,12 +9,7 @@ use embassy_executor::Spawner; use embassy_time::{Duration, Timer}; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; +use {defmt_rtt as _, panic_probe as _}; use embassy_mcxa276 as hal; use hal::bind_interrupts; @@ -37,7 +32,8 @@ async fn main(_spawner: Spawner) { common::init_uart2(hal::pac()); } let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + let mut uart = + hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); @@ -134,9 +130,3 @@ fn write_u64(uart: &mut hal::uart::Uart, value: u64) { } } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs index 4470b65fd..072310309 100644 --- a/examples/ostimer_race_test.rs +++ b/examples/ostimer_race_test.rs @@ -12,16 +12,10 @@ use embassy_executor::Spawner; use embassy_time::{Duration, Timer}; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; - use core::sync::atomic::{AtomicU32, Ordering}; use embassy_mcxa276 as hal; use hal::bind_interrupts; +use {defmt_rtt as _, panic_probe as _}; mod common; @@ -86,7 +80,8 @@ async fn main(_spawner: Spawner) { common::init_uart2(hal::pac()); } let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + let mut uart = + hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); @@ -403,9 +398,3 @@ fn write_u64(uart: &mut hal::uart::Uart, value: u64) { } } } - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs index 8f4ff1623..a190b8ba5 100644 --- a/examples/rtc_alarm.rs +++ b/examples/rtc_alarm.rs @@ -1,26 +1,21 @@ #![no_std] #![no_main] - -use embassy_mcxa276 as hal; use cortex_m; use embassy_executor::Spawner; +use embassy_mcxa276 as hal; +use hal::InterruptExt; use hal::rtc::{RtcDateTime, RtcInterruptEnable}; use hal::uart; -use hal::InterruptExt; mod common; type MyRtc = hal::rtc::Rtc; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; +use {defmt_rtt as _, panic_probe as _}; use embassy_mcxa276::bind_interrupts; + bind_interrupts!(struct Irqs { RTC => hal::rtc::RtcHandler; }); @@ -31,7 +26,6 @@ static KEEP_RTC: unsafe extern "C" fn() = RTC; #[embassy_executor::main] async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); unsafe { @@ -58,12 +52,11 @@ async fn main(_spawner: Spawner) { second: 0, }; - rtc.stop(); uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n"); rtc.set_datetime(now); - + let mut alarm = now; alarm.second += 10; @@ -92,14 +85,6 @@ async fn main(_spawner: Spawner) { } uart.write_str_blocking("Example complete - Test PASSED!\r\n"); - - loop { - - } -} -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { loop {} } diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs index 85743bb64..bd734f859 100644 --- a/examples/uart_interrupt.rs +++ b/examples/uart_interrupt.rs @@ -8,14 +8,8 @@ use hal::uart; mod common; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use defmt_rtt as _; -#[cfg(feature = "defmt")] -use panic_probe as _; -#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] -use rtt_target as _; - use embassy_mcxa276::bind_interrupts; +use {defmt_rtt as _, panic_probe as _}; // Bind LPUART2 interrupt to our handler bind_interrupts!(struct Irqs { @@ -57,7 +51,6 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking("Type characters to echo them back.\r\n"); // Log using defmt if enabled - #[cfg(feature = "defmt")] defmt::info!("UART interrupt echo demo starting..."); loop { @@ -74,15 +67,3 @@ async fn main(_spawner: Spawner) { } } } - -#[cfg(feature = "defmt")] -#[export_name = "_defmt_timestamp"] -fn defmt_timestamp(_fmt: defmt::Formatter<'_>) { - // Return empty timestamp for now -} - -#[cfg(not(feature = "defmt"))] -#[panic_handler] -fn panic(_info: &core::panic::PanicInfo) -> ! { - loop {} -} diff --git a/src/adc.rs b/src/adc.rs index f56d744c6..5625330e9 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,12 +1,12 @@ -//! ADC driver +//! ADC driver use crate::pac; use core::sync::atomic::{AtomicBool, Ordering}; -use crate::pac::adc1::ctrl::{CalAvgs}; -use crate::pac::adc1::cfg::{Refsel, Pwrsel, Tprictrl, Tres, Tcmdres, HptExdi}; -use crate::pac::adc1::tctrl::{Tcmd, Tpri}; +use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres}; +use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts}; use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode}; -use crate::pac::adc1::cmdh1::{Next, Avgs, Sts, Cmpen}; +use crate::pac::adc1::ctrl::CalAvgs; +use crate::pac::adc1::tctrl::{Tcmd, Tpri}; type Regs = pac::adc1::RegisterBlock; @@ -17,9 +17,7 @@ pub trait Instance { } /// Token for ADC1 -#[cfg(feature = "adc1")] pub type Adc1 = crate::peripherals::ADC1; -#[cfg(feature = "adc1")] impl Instance for crate::peripherals::ADC1 { #[inline(always)] fn ptr() -> *const Regs { @@ -28,7 +26,6 @@ impl Instance for crate::peripherals::ADC1 { } // Also implement Instance for the Peri wrapper type -#[cfg(feature = "adc1")] impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> { #[inline(always)] fn ptr() -> *const Regs { @@ -97,16 +94,15 @@ pub struct ConvResult { pub conv_value: u16, } - pub struct Adc { _inst: core::marker::PhantomData, } impl Adc { /// initialize ADC - pub fn new(_inst: impl Instance, config : LpadcConfig) -> Self { + pub fn new(_inst: impl Instance, config: LpadcConfig) -> Self { let adc = unsafe { &*I::ptr() }; - + /* Reset the module. */ adc.ctrl().modify(|_, w| w.rst().held_in_reset()); adc.ctrl().modify(|_, w| w.rst().released_from_reset()); @@ -124,64 +120,81 @@ impl Adc { } /* Set calibration average mode. */ - adc.ctrl().modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode)); - - adc.cfg().write(|w| unsafe { + adc.ctrl() + .modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode)); + + adc.cfg().write(|w| unsafe { let w = if config.enable_analog_preliminary { w.pwren().pre_enabled() } else { w }; - w.pudly().bits(config.power_up_delay) - .refsel().variant(config.reference_voltage_source) - .pwrsel().variant(config.power_level_mode) - .tprictrl().variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed | - TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted | - TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority, - TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed | - TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted | - TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority, - _ => Tprictrl::AbortCurrentOnPriority, - }) - .tres().variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted | - TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted | - TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed | - TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed | - TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted | - TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled, - _ => Tres::Disabled, - }) - .tcmdres().variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed | - TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed | - TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed | - TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled, - _ => Tcmdres::Disabled, - }) - .hpt_exdi().variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled, - _ => HptExdi::Enabled, - }) - }); + w.pudly() + .bits(config.power_up_delay) + .refsel() + .variant(config.reference_voltage_source) + .pwrsel() + .variant(config.power_level_mode) + .tprictrl() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => { + Tprictrl::FinishCurrentOnPriority + } + TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => { + Tprictrl::FinishSequenceOnPriority + } + _ => Tprictrl::AbortCurrentOnPriority, + }) + .tres() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled, + _ => Tres::Disabled, + }) + .tcmdres() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed + | TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled, + _ => Tcmdres::Disabled, + }) + .hpt_exdi() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled, + _ => HptExdi::Enabled, + }) + }); if config.enable_conv_pause { adc.pause().modify(|_, w| unsafe { - w.pauseen().enabled() - .pausedly().bits(config.conv_pause_delay) + w.pauseen() + .enabled() + .pausedly() + .bits(config.conv_pause_delay) }); } else { adc.pause().write(|w| unsafe { w.bits(0) }); } - adc.fctrl0().write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) }); + adc.fctrl0() + .write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) }); // Enable ADC adc.ctrl().modify(|_, w| w.adcen().enabled()); - Self { _inst: core::marker::PhantomData } + Self { + _inst: core::marker::PhantomData, + } } pub fn deinit(&self) { @@ -189,7 +202,6 @@ impl Adc { adc.ctrl().modify(|_, w| w.adcen().disabled()); } - pub fn get_default_config() -> LpadcConfig { LpadcConfig { enable_in_doze_mode: true, @@ -208,13 +220,14 @@ impl Adc { pub fn do_offset_calibration(&self) { let adc = unsafe { &*I::ptr() }; // Enable calibration mode - adc.ctrl().modify(|_, w| w.calofs().offset_calibration_request_pending()); + adc.ctrl() + .modify(|_, w| w.calofs().offset_calibration_request_pending()); // Wait for calibration to complete (polling status register) while adc.stat().read().cal_rdy().is_not_set() {} } - pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32{ + pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32 { let mut gcra_array = [0u32; 17]; let mut gcalr: u32 = 0; @@ -234,20 +247,21 @@ impl Adc { pub fn do_auto_calibration(&self) { let adc = unsafe { &*I::ptr() }; - adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending()); + adc.ctrl() + .modify(|_, w| w.cal_req().calibration_request_pending()); while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} - let mut gcca = adc.gcc0().read().gain_cal().bits() as u32; if gcca & (((0xFFFF >> 0) + 1) >> 1) != 0 { - gcca |= !0xFFFF; + gcca |= !0xFFFF; } let gcra = 131072.0 / (131072.0 - gcca as f32); // Write to GCR0 - adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); + adc.gcr0() + .write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); adc.gcr0().modify(|_, w| w.rdy().set_bit()); @@ -284,15 +298,22 @@ impl Adc { match index { 1 => { adc.cmdl1().write(|w| { - w.adch().variant(config.channel_number) - .mode().variant(config.conversion_resolution_mode) + w.adch() + .variant(config.channel_number) + .mode() + .variant(config.conversion_resolution_mode) }); adc.cmdh1().write(|w| unsafe { - w.next().variant(config.chained_next_command_number) - .loop_().bits(config.loop_count) - .avgs().variant(config.hardware_average_mode) - .sts().variant(config.sample_time_mode) - .cmpen().variant(config.hardware_compare_mode); + w.next() + .variant(config.chained_next_command_number) + .loop_() + .bits(config.loop_count) + .avgs() + .variant(config.hardware_average_mode) + .sts() + .variant(config.sample_time_mode) + .cmpen() + .variant(config.hardware_compare_mode); if config.enable_wait_trigger { w.wait_trig().enabled(); } @@ -371,5 +392,7 @@ pub fn on_interrupt() { pub struct AdcHandler; impl crate::interrupt::typelevel::Handler for AdcHandler { - unsafe fn on_interrupt() { on_interrupt(); } + unsafe fn on_interrupt() { + on_interrupt(); + } } diff --git a/src/clocks.rs b/src/clocks.rs index 5336c3efe..95d7ad567 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -112,10 +112,10 @@ pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) { let vbat = &peripherals.vbat0; // Enable FRO16K oscillator vbat.froctla().modify(|_, w| w.fro_en().set_bit()); - + // Lock the control register vbat.frolcka().modify(|_, w| w.lock().set_bit()); - + // Enable clock outputs to both VSYS and VDD_CORE domains // Bit 0: clk_16k0 to VSYS domain // Bit 1: clk_16k1 to VDD_CORE domain @@ -130,7 +130,6 @@ pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { // Use FRO_LF_DIV (already running) MUX=0 DIV=0 let mrcc = &peripherals.mrcc0; - mrcc.mrcc_adc_clksel() - .write(|w| w.mux().clkroot_func_0()); + mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0()); mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); -} \ No newline at end of file +} diff --git a/src/gpio.rs b/src/gpio.rs index 08f375cba..faeefd333 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -66,7 +66,7 @@ pub trait PinId { } pub mod pins { - use super::{pac, AnyPin, PinId}; + use super::{AnyPin, PinId, pac}; macro_rules! define_pin { ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => { diff --git a/src/interrupt.rs b/src/interrupt.rs index 8226f01ab..d91e6479a 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -6,8 +6,8 @@ mod generated { embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1); } -pub use generated::interrupt::typelevel; pub use generated::interrupt::Priority; +pub use generated::interrupt::typelevel; use crate::pac::Interrupt; use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; diff --git a/src/lib.rs b/src/lib.rs index eb4727106..518fe01d2 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,31 +1,19 @@ #![no_std] pub mod clocks; // still provide clock helpers -#[cfg(feature = "gpio")] pub mod gpio; pub mod pins; // pin mux helpers pub mod reset; // reset control helpers +pub mod adc; pub mod config; pub mod interrupt; -pub mod ostimer; -pub mod uart; pub mod lpuart; +pub mod ostimer; pub mod rtc; -pub mod adc; +pub mod uart; -embassy_hal_internal::peripherals!( - #[cfg(feature = "lpuart2")] - LPUART2, - #[cfg(feature = "ostimer0")] - OSTIMER0, - #[cfg(feature = "gpio")] - GPIO, - #[cfg(feature = "rtc0")] - RTC0, - #[cfg(feature = "adc1")] - ADC1, -); +embassy_hal_internal::peripherals!(LPUART2, OSTIMER0, GPIO, RTC0, ADC1,); /// Get access to the PAC Peripherals for low-level register access. /// This is a lazy-initialized singleton that can be called after init(). @@ -42,43 +30,32 @@ pub fn pac() -> &'static pac::Peripherals { } } -pub use cortex_m_rt; -pub use mcxa276_pac as pac; +#[cfg(feature = "unstable-pac")] +pub use mcxa_pac as pac; +#[cfg(not(feature = "unstable-pac"))] +pub(crate) use mcxa_pac as pac; + // Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. // Re-export interrupt traits and types +pub use adc::Adc1 as Adc1Token; +pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output, pins::*}; pub use interrupt::InterruptExt; -#[cfg(feature = "ostimer0")] pub use ostimer::Ostimer0 as Ostimer0Token; -#[cfg(feature = "lpuart2")] -pub use uart::Lpuart2 as Uart2Token; -#[cfg(feature = "rtc0")] pub use rtc::Rtc0 as Rtc0Token; -#[cfg(feature = "adc1")] -pub use adc::Adc1 as Adc1Token; -#[cfg(feature = "gpio")] -pub use gpio::{pins::*, AnyPin, Flex, Gpio as GpioToken, Input, Level, Output}; +pub use uart::Lpuart2 as Uart2Token; /// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. /// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). #[allow(unused_variables)] pub fn init(cfg: crate::config::Config) -> Peripherals { let peripherals = Peripherals::take(); - #[cfg(feature = "ostimer0")] - { - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority); - } - #[cfg(feature = "rtc0")] - { - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); - } - #[cfg(feature = "adc1")] - { - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority); - } + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority); peripherals } diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index 03673d975..e2382e86d 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -3,8 +3,8 @@ use core::marker::PhantomData; use core::sync::atomic::{AtomicBool, Ordering}; use core::task::Poll; -use embassy_hal_internal::atomic_ring_buffer::RingBuffer; use embassy_hal_internal::Peri; +use embassy_hal_internal::atomic_ring_buffer::RingBuffer; use embassy_sync::waitqueue::AtomicWaker; use super::*; diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 431547f86..99f4a4a66 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -6,7 +6,7 @@ use paste::paste; use crate::pac; use crate::pac::lpuart0::baud::Sbns as StopBits; use crate::pac::lpuart0::ctrl::{ - Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits, + Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity, }; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; use crate::pac::lpuart0::stat::Msbf as MsbFirst; diff --git a/src/ostimer.rs b/src/ostimer.rs index b9688313a..6a4188db0 100644 --- a/src/ostimer.rs +++ b/src/ostimer.rs @@ -493,10 +493,8 @@ pub trait Instance { } // Token for OSTIMER0 provided by embassy-hal-internal peripherals macro. -#[cfg(feature = "ostimer0")] pub type Ostimer0 = crate::peripherals::OSTIMER0; -#[cfg(feature = "ostimer0")] impl Instance for crate::peripherals::OSTIMER0 { #[inline(always)] fn ptr() -> *const Regs { @@ -505,7 +503,6 @@ impl Instance for crate::peripherals::OSTIMER0 { } // Also implement Instance for the Peri wrapper type -#[cfg(feature = "ostimer0")] impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> { #[inline(always)] fn ptr() -> *const Regs { @@ -528,11 +525,10 @@ fn gray_to_bin(gray: u64) -> u64 { bin } -#[cfg(feature = "ostimer0")] pub mod time_driver { use super::{ - bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, - ALARM_TARGET_TIME, EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, + ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, EVTIMER_HI_MASK, + EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, Regs, bin_to_gray, now_ticks_read, }; use crate::pac; use core::sync::atomic::Ordering; diff --git a/src/pins.rs b/src/pins.rs index d46a3e6b3..1d92f9fef 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -57,7 +57,6 @@ pub unsafe fn configure_adc_pins() { .inv0() .lk() .lk0() - }); core::arch::asm!("dsb sy; isb sy"); } diff --git a/src/rtc.rs b/src/rtc.rs index f83baab5e..5e3dfe6c1 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -1,6 +1,6 @@ //! RTC DateTime driver. use crate::pac; -use crate::pac::rtc0::cr::{Um}; +use crate::pac::rtc0::cr::Um; use core::sync::atomic::{AtomicBool, Ordering}; type Regs = pac::rtc0::RegisterBlock; @@ -13,9 +13,7 @@ pub trait Instance { } /// Token for RTC0 -#[cfg(feature = "rtc0")] pub type Rtc0 = crate::peripherals::RTC0; -#[cfg(feature = "rtc0")] impl Instance for crate::peripherals::RTC0 { #[inline(always)] fn ptr() -> *const Regs { @@ -24,7 +22,6 @@ impl Instance for crate::peripherals::RTC0 { } // Also implement Instance for the Peri wrapper type -#[cfg(feature = "rtc0")] impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::RTC0> { #[inline(always)] fn ptr() -> *const Regs { @@ -87,7 +84,6 @@ pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 { seconds } - pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { let mut seconds_remaining = seconds; let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1; @@ -166,11 +162,15 @@ impl Rtc { rtc.cr().modify(|_, w| w.um().variant(config.update_mode)); rtc.tcr().modify(|_, w| unsafe { - w.cir().bits(config.compensation_interval) - .tcr().bits(config.compensation_time) + w.cir() + .bits(config.compensation_interval) + .tcr() + .bits(config.compensation_time) }); - Self { _inst: core::marker::PhantomData } + Self { + _inst: core::marker::PhantomData, + } } pub fn set_datetime(&self, datetime: RtcDateTime) { @@ -178,7 +178,7 @@ impl Rtc { let seconds = convert_datetime_to_seconds(&datetime); rtc.tsr().write(|w| unsafe { w.bits(seconds) }); } - + pub fn get_datetime(&self) -> RtcDateTime { let rtc = unsafe { &*I::ptr() }; let seconds = rtc.tsr().read().bits(); @@ -203,7 +203,7 @@ impl Rtc { } } - pub fn get_alarm(&self) -> RtcDateTime{ + pub fn get_alarm(&self) -> RtcDateTime { let rtc = unsafe { &*I::ptr() }; let alarm_seconds = rtc.tar().read().bits(); convert_seconds_to_datetime(alarm_seconds) @@ -264,7 +264,7 @@ impl Rtc { ALARM_TRIGGERED.load(Ordering::Relaxed) } } - + pub fn on_interrupt() { let rtc = unsafe { &*pac::Rtc0::ptr() }; // Check if this is actually a time alarm interrupt @@ -277,5 +277,7 @@ pub fn on_interrupt() { pub struct RtcHandler; impl crate::interrupt::typelevel::Handler for RtcHandler { - unsafe fn on_interrupt() { on_interrupt(); } -} \ No newline at end of file + unsafe fn on_interrupt() { + on_interrupt(); + } +} diff --git a/src/uart.rs b/src/uart.rs index 45b6b2be3..65dd91492 100644 --- a/src/uart.rs +++ b/src/uart.rs @@ -15,9 +15,7 @@ pub trait Instance { } /// Token for LPUART2 provided by embassy-hal-internal peripherals macro. -#[cfg(feature = "lpuart2")] pub type Lpuart2 = crate::peripherals::LPUART2; -#[cfg(feature = "lpuart2")] impl Instance for crate::peripherals::LPUART2 { #[inline(always)] fn ptr() -> *const Regs { @@ -26,7 +24,6 @@ impl Instance for crate::peripherals::LPUART2 { } // Also implement Instance for the Peri wrapper type -#[cfg(feature = "lpuart2")] impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::LPUART2> { #[inline(always)] fn ptr() -> *const Regs { @@ -111,7 +108,7 @@ impl Uart { cortex_m::asm::delay(3); // Short delay for reset to take effect l.global().write(|w| w.rst().no_effect()); cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset - // 2) BAUD + // 2) BAUD let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud); l.baud().modify(|_, w| { let w = match cfg.stop_bits { @@ -145,7 +142,9 @@ impl Uart { }); l.water() .modify(|_, w| unsafe { w.txwater().bits(0).rxwater().bits(0) }); - Self { _inst: core::marker::PhantomData } + Self { + _inst: core::marker::PhantomData, + } } /// Enable RX interrupts. The caller must ensure an appropriate IRQ handler is installed. -- cgit From e75066820ad320495ca70570641c90d75247b19b Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 7 Nov 2025 10:07:33 -0800 Subject: cargo +nightly fmt Signed-off-by: Felipe Balbi --- examples/adc_interrupt.rs | 9 ++---- examples/adc_polling.rs | 9 ++---- examples/blink.rs | 5 +--- examples/lpuart_buffered.rs | 9 ++---- examples/lpuart_polling.rs | 8 ++---- examples/ostimer_alarm.rs | 15 ++++------ examples/ostimer_async.rs | 5 +--- examples/ostimer_counter.rs | 8 ++---- examples/ostimer_race_test.rs | 14 ++++----- examples/rtc_alarm.rs | 9 ++---- rustfmt.toml | 8 ++---- src/adc.rs | 24 +++++----------- src/clocks.rs | 3 +- src/gpio.rs | 8 ++---- src/interrupt.rs | 6 ++-- src/lib.rs | 12 ++++---- src/lpuart/buffered.rs | 19 +++---------- src/lpuart/mod.rs | 19 ++++--------- src/ostimer.rs | 66 +++++++++++++++---------------------------- src/pins.rs | 5 +--- src/rtc.rs | 3 +- src/uart.rs | 13 ++++----- 22 files changed, 90 insertions(+), 187 deletions(-) diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs index 26afd70b4..f0df3196c 100644 --- a/examples/adc_interrupt.rs +++ b/examples/adc_interrupt.rs @@ -1,24 +1,19 @@ #![no_std] #![no_main] -use cortex_m; use embassy_executor::Spawner; -use embassy_mcxa276 as hal; - use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; use hal::pac::adc1::ctrl::CalAvgs; use hal::pac::adc1::tctrl::Tcmd; - use hal::uart; +use {cortex_m, embassy_mcxa276 as hal}; mod common; +use hal::{bind_interrupts, InterruptExt}; use {defmt_rtt as _, panic_probe as _}; -use hal::InterruptExt; -use hal::bind_interrupts; - bind_interrupts!(struct Irqs { ADC1 => hal::adc::AdcHandler; }); diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs index 90be87c3f..561500d2d 100644 --- a/examples/adc_polling.rs +++ b/examples/adc_polling.rs @@ -1,24 +1,21 @@ #![no_std] #![no_main] -use embassy_mcxa276 as hal; - use embassy_executor::Spawner; - +use embassy_mcxa276 as hal; use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; use hal::pac::adc1::ctrl::CalAvgs; use hal::pac::adc1::tctrl::Tcmd; - use hal::uart; mod common; -use {defmt_rtt as _, panic_probe as _}; - use core::fmt::Write; + use heapless::String; +use {defmt_rtt as _, panic_probe as _}; const G_LPADC_RESULT_SHIFT: u32 = 0; diff --git a/examples/blink.rs b/examples/blink.rs index a9b6e7093..564353d5c 100644 --- a/examples/blink.rs +++ b/examples/blink.rs @@ -34,10 +34,7 @@ async fn main(_spawner: Spawner) { } // Initialize embassy-time global driver backed by OSTIMER0 - hal::ostimer::time_driver::init( - hal::config::Config::default().time_interrupt_priority, - 1_000_000, - ); + hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); // Configure LED pin for GPIO mode PIO3_18::set_mux_gpio(); diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs index d0d4d2ee0..30ba3f333 100644 --- a/examples/lpuart_buffered.rs +++ b/examples/lpuart_buffered.rs @@ -4,13 +4,10 @@ use embassy_executor::Spawner; use embassy_mcxa276 as hal; use embassy_mcxa276::interrupt::typelevel::Handler; -use embassy_mcxa276::lpuart; use embassy_mcxa276::lpuart::buffered::BufferedLpuart; - +use embassy_mcxa276::{bind_interrupts, lpuart}; use embedded_io_async::{Read, Write}; -use embassy_mcxa276::bind_interrupts; - mod common; // Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver @@ -69,9 +66,7 @@ async fn main(_spawner: Spawner) { let (tx, rx) = uart.split_ref(); tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); - tx.write(b"Type characters to echo them back.\r\n") - .await - .unwrap(); + tx.write(b"Type characters to echo them back.\r\n").await.unwrap(); // Echo loop let mut buf = [0u8; 4]; diff --git a/examples/lpuart_polling.rs b/examples/lpuart_polling.rs index f9172de40..067c7eb53 100644 --- a/examples/lpuart_polling.rs +++ b/examples/lpuart_polling.rs @@ -1,11 +1,10 @@ #![no_std] #![no_main] -use crate::hal::lpuart::{Config, Lpuart, lib}; use embassy_executor::Spawner; -use embassy_mcxa276 as hal; +use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; -use {defmt_rtt as _, panic_probe as _}; +use crate::hal::lpuart::{lib, Config, Lpuart}; mod common; @@ -43,8 +42,7 @@ async fn main(_spawner: Spawner) { // Write hello messages tx.blocking_write(b"Hello world.\r\n").unwrap(); - tx.blocking_write(b"Echoing. Type characters...\r\n") - .unwrap(); + tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap(); // Echo loop loop { diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs index eca669509..78ca4bbc5 100644 --- a/examples/ostimer_alarm.rs +++ b/examples/ostimer_alarm.rs @@ -2,16 +2,15 @@ #![no_main] use core::sync::atomic::{AtomicBool, Ordering}; -use cortex_m; + use embassy_executor::Spawner; -use embassy_mcxa276 as hal; use hal::uart; +use {cortex_m, embassy_mcxa276 as hal}; mod common; -use {defmt_rtt as _, panic_probe as _}; - use embassy_mcxa276::bind_interrupts; +use {defmt_rtt as _, panic_probe as _}; // Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. bind_interrupts!(struct Irqs { @@ -46,18 +45,14 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking("OSTIMER Alarm Example\n"); // Initialize embassy-time global driver backed by OSTIMER0 - hal::ostimer::time_driver::init( - hal::config::Config::default().time_interrupt_priority, - 1_000_000, - ); + hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); // Create OSTIMER instance let config = hal::ostimer::Config { init_match_max: true, clock_frequency_hz: 1_000_000, // 1MHz }; - let ostimer = - hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); + let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); // Create alarm with callback let alarm = hal::ostimer::Alarm::new() diff --git a/examples/ostimer_async.rs b/examples/ostimer_async.rs index 37fb3b3d1..27e14e022 100644 --- a/examples/ostimer_async.rs +++ b/examples/ostimer_async.rs @@ -42,10 +42,7 @@ async fn main(_spawner: Spawner) { // Initialize OSTIMER with default 1MHz frequency // Adjust this value to match your actual OSTIMER clock frequency - hal::ostimer::time_driver::init( - hal::config::Config::default().time_interrupt_priority, - 1_000_000, - ); + hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); // Removed force-pend; rely on real hardware match to trigger OS_EVENT. diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs index 1f5bdf434..e95140a88 100644 --- a/examples/ostimer_counter.rs +++ b/examples/ostimer_counter.rs @@ -8,11 +8,8 @@ use embassy_executor::Spawner; use embassy_time::{Duration, Timer}; - -use {defmt_rtt as _, panic_probe as _}; - -use embassy_mcxa276 as hal; use hal::bind_interrupts; +use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; mod common; @@ -32,8 +29,7 @@ async fn main(_spawner: Spawner) { common::init_uart2(hal::pac()); } let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = - hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs index 072310309..a637b6353 100644 --- a/examples/ostimer_race_test.rs +++ b/examples/ostimer_race_test.rs @@ -9,13 +9,12 @@ #![no_std] #![no_main] +use core::sync::atomic::{AtomicU32, Ordering}; + use embassy_executor::Spawner; use embassy_time::{Duration, Timer}; - -use core::sync::atomic::{AtomicU32, Ordering}; -use embassy_mcxa276 as hal; use hal::bind_interrupts; -use {defmt_rtt as _, panic_probe as _}; +use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; mod common; @@ -80,8 +79,7 @@ async fn main(_spawner: Spawner) { common::init_uart2(hal::pac()); } let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = - hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); @@ -250,9 +248,7 @@ async fn test_concurrent_operations( let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); if !ostimer.schedule_alarm_delay(&alarm, 1000) { RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking( - "ERROR: Failed to program OSTIMER alarm before concurrent operations\n", - ); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before concurrent operations\n"); } // Wait for both to complete diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs index a190b8ba5..c27fd4c55 100644 --- a/examples/rtc_alarm.rs +++ b/examples/rtc_alarm.rs @@ -1,20 +1,17 @@ #![no_std] #![no_main] -use cortex_m; use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::InterruptExt; use hal::rtc::{RtcDateTime, RtcInterruptEnable}; -use hal::uart; +use hal::{uart, InterruptExt}; +use {cortex_m, embassy_mcxa276 as hal}; mod common; type MyRtc = hal::rtc::Rtc; -use {defmt_rtt as _, panic_probe as _}; - use embassy_mcxa276::bind_interrupts; +use {defmt_rtt as _, panic_probe as _}; bind_interrupts!(struct Irqs { RTC => hal::rtc::RtcHandler; diff --git a/rustfmt.toml b/rustfmt.toml index 0720148fd..9eb3c3b4f 100644 --- a/rustfmt.toml +++ b/rustfmt.toml @@ -1,7 +1,3 @@ -# Workspace formatting preferences -edition = "2021" -# Merge and sort imports by crate; reduces noise in diffs -imports_granularity = "Crate" group_imports = "StdExternalCrate" -# Keep defaults for everything else to stay close to rustfmt stable - +imports_granularity = "Module" +max_width = 120 diff --git a/src/adc.rs b/src/adc.rs index 5625330e9..d456971f7 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,7 +1,7 @@ //! ADC driver -use crate::pac; use core::sync::atomic::{AtomicBool, Ordering}; +use crate::pac; use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres}; use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts}; use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode}; @@ -140,14 +140,10 @@ impl Adc { .variant(match config.trigger_priority_policy { TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => { - Tprictrl::FinishCurrentOnPriority - } + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority, TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => { - Tprictrl::FinishSequenceOnPriority - } + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority, _ => Tprictrl::AbortCurrentOnPriority, }) .tres() @@ -176,12 +172,8 @@ impl Adc { }); if config.enable_conv_pause { - adc.pause().modify(|_, w| unsafe { - w.pauseen() - .enabled() - .pausedly() - .bits(config.conv_pause_delay) - }); + adc.pause() + .modify(|_, w| unsafe { w.pauseen().enabled().pausedly().bits(config.conv_pause_delay) }); } else { adc.pause().write(|w| unsafe { w.bits(0) }); } @@ -247,8 +239,7 @@ impl Adc { pub fn do_auto_calibration(&self) { let adc = unsafe { &*I::ptr() }; - adc.ctrl() - .modify(|_, w| w.cal_req().calibration_request_pending()); + adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending()); while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} @@ -260,8 +251,7 @@ impl Adc { let gcra = 131072.0 / (131072.0 - gcca as f32); // Write to GCR0 - adc.gcr0() - .write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); + adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); adc.gcr0().modify(|_, w| w.rdy().set_bit()); diff --git a/src/clocks.rs b/src/clocks.rs index 95d7ad567..65a17cef6 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -76,8 +76,7 @@ pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { // Use FRO_LF_DIV (already running) MUX=0 DIV=0 let mrcc = &peripherals.mrcc0; - mrcc.mrcc_lpuart2_clksel() - .write(|w| w.mux().clkroot_func_0()); + mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0()); mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); } diff --git a/src/gpio.rs b/src/gpio.rs index faeefd333..1e7214b28 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -66,7 +66,7 @@ pub trait PinId { } pub mod pins { - use super::{AnyPin, PinId, pac}; + use super::{pac, AnyPin, PinId}; macro_rules! define_pin { ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => { @@ -130,15 +130,13 @@ impl<'d> Flex<'d> { pub fn set_as_input(&mut self) { let mask = self.mask(); let gpio = self.gpio(); - gpio.pddr() - .modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); } pub fn set_as_output(&mut self) { let mask = self.mask(); let gpio = self.gpio(); - gpio.pddr() - .modify(|r, w| unsafe { w.bits(r.bits() | mask) }); + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); } pub fn set_high(&mut self) { diff --git a/src/interrupt.rs b/src/interrupt.rs index d91e6479a..09d7acbef 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -6,11 +6,11 @@ mod generated { embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1); } -pub use generated::interrupt::Priority; -pub use generated::interrupt::typelevel; +use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; + +pub use generated::interrupt::{typelevel, Priority}; use crate::pac::Interrupt; -use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; /// Trait for configuring and controlling interrupts. /// diff --git a/src/lib.rs b/src/lib.rs index 518fe01d2..fe27aadba 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -30,17 +30,17 @@ pub fn pac() -> &'static pac::Peripherals { } } -#[cfg(feature = "unstable-pac")] -pub use mcxa_pac as pac; -#[cfg(not(feature = "unstable-pac"))] -pub(crate) use mcxa_pac as pac; - // Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. // Re-export interrupt traits and types pub use adc::Adc1 as Adc1Token; -pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output, pins::*}; +pub use gpio::pins::*; +pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output}; pub use interrupt::InterruptExt; +#[cfg(feature = "unstable-pac")] +pub use mcxa_pac as pac; +#[cfg(not(feature = "unstable-pac"))] +pub(crate) use mcxa_pac as pac; pub use ostimer::Ostimer0 as Ostimer0Token; pub use rtc::Rtc0 as Rtc0Token; pub use uart::Lpuart2 as Uart2Token; diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index e2382e86d..0413fed8e 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -3,8 +3,8 @@ use core::marker::PhantomData; use core::sync::atomic::{AtomicBool, Ordering}; use core::task::Poll; -use embassy_hal_internal::Peri; use embassy_hal_internal::atomic_ring_buffer::RingBuffer; +use embassy_hal_internal::Peri; use embassy_sync::waitqueue::AtomicWaker; use super::*; @@ -87,15 +87,7 @@ impl<'a> BufferedLpuart<'a> { let state = T::buffered_state(); // Initialize the peripheral - Self::init::( - Some(&tx_pin), - Some(&rx_pin), - None, - None, - tx_buffer, - rx_buffer, - config, - )?; + Self::init::(Some(&tx_pin), Some(&rx_pin), None, None, tx_buffer, rx_buffer, config)?; Ok(Self { tx: BufferedLpuartTx { @@ -523,9 +515,7 @@ pub struct BufferedInterruptHandler { _phantom: PhantomData, } -impl crate::interrupt::typelevel::Handler - for BufferedInterruptHandler -{ +impl crate::interrupt::typelevel::Handler for BufferedInterruptHandler { unsafe fn on_interrupt() { let regs = T::info().regs; let state = T::buffered_state(); @@ -616,8 +606,7 @@ impl crate::interrupt::typelevel::Handler // If buffer is empty, switch to TC interrupt or disable if state.tx_buf.is_empty() { cortex_m::interrupt::free(|_| { - regs.ctrl() - .modify(|_, w| w.tie().disabled().tcie().enabled()); + regs.ctrl().modify(|_, w| w.tie().disabled().tcie().enabled()); }); } } diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 99f4a4a66..bed10bdb0 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -1,15 +1,13 @@ -use crate::interrupt; use core::marker::PhantomData; + use embassy_hal_internal::{Peri, PeripheralType}; use paste::paste; -use crate::pac; use crate::pac::lpuart0::baud::Sbns as StopBits; -use crate::pac::lpuart0::ctrl::{ - Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity, -}; +use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; use crate::pac::lpuart0::stat::Msbf as MsbFirst; +use crate::{interrupt, pac}; pub mod buffered; @@ -261,8 +259,7 @@ pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result /// Configure frame format (stop bits, data bits) pub fn configure_frame_format(regs: Regs, config: &Config) { // Configure stop bits - regs.baud() - .modify(|_, w| w.sbns().variant(config.stop_bits_count)); + regs.baud().modify(|_, w| w.sbns().variant(config.stop_bits_count)); // Clear M10 for now (10-bit mode) regs.baud().modify(|_, w| w.m10().disabled()); @@ -314,8 +311,7 @@ pub fn configure_fifo(regs: Regs, config: &Config) { }); // Enable TX/RX FIFOs - regs.fifo() - .modify(|_, w| w.txfe().enabled().rxfe().enabled()); + regs.fifo().modify(|_, w| w.txfe().enabled().rxfe().enabled()); // Flush FIFOs regs.fifo() @@ -818,10 +814,7 @@ impl<'a> LpuartTx<'a, Blocking> { } fn write_byte_internal(&mut self, byte: u8) -> Result<()> { - self.info - .regs - .data() - .modify(|_, w| unsafe { w.bits(u32::from(byte)) }); + self.info.regs.data().modify(|_, w| unsafe { w.bits(u32::from(byte)) }); Ok(()) } diff --git a/src/ostimer.rs b/src/ostimer.rs index 6a4188db0..a4cab6970 100644 --- a/src/ostimer.rs +++ b/src/ostimer.rs @@ -27,9 +27,10 @@ //! - Immediate wake for timestamps that would cause rollover issues #![allow(dead_code)] +use core::sync::atomic::{AtomicBool, Ordering}; + use crate::interrupt::InterruptExt; use crate::pac; -use core::sync::atomic::{AtomicBool, Ordering}; // PAC defines the shared RegisterBlock under `ostimer0`. type Regs = pac::ostimer0::RegisterBlock; @@ -129,18 +130,12 @@ pub(super) fn wait_for_match_write_complete(r: &Regs) -> bool { fn prime_match_registers(r: &Regs) { // Disable the interrupt, clear any pending flag, then wait until the MATCH registers are writable. - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); if wait_for_match_write_ready(r) { - r.match_l() - .write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) }); - r.match_h() - .write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) }); + r.match_l().write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) }); + r.match_h().write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) }); let _ = wait_for_match_write_complete(r); } } @@ -222,10 +217,7 @@ impl<'d, I: Instance> Ostimer<'d, I> { /// Requires clocks for the instance to be enabled by the board before calling. /// Does not enable NVIC or INTENA; use time_driver::init() for async operation. pub fn new(_inst: impl Instance, cfg: Config, _p: &'d crate::pac::Peripherals) -> Self { - assert!( - cfg.clock_frequency_hz > 0, - "OSTIMER frequency must be greater than 0" - ); + assert!(cfg.clock_frequency_hz > 0, "OSTIMER frequency must be greater than 0"); if cfg.init_match_max { let r: &Regs = unsafe { &*I::ptr() }; @@ -268,12 +260,8 @@ impl<'d, I: Instance> Ostimer<'d, I> { // Mask the peripheral interrupt flag before we toggle the reset line so that // no new NVIC activity races with the reset sequence. - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); unsafe { crate::reset::assert::(peripherals); @@ -287,9 +275,7 @@ impl<'d, I: Instance> Ostimer<'d, I> { crate::reset::release::(peripherals); } - while !::is_released( - &peripherals.mrcc0, - ) { + while !::is_released(&peripherals.mrcc0) { cortex_m::asm::nop(); } @@ -363,12 +349,8 @@ impl<'d, I: Instance> Ostimer<'d, I> { critical_section::with(|_| { // Disable interrupt and clear flag - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); if !wait_for_match_write_ready(r) { prime_match_registers(r); @@ -526,15 +508,17 @@ fn gray_to_bin(gray: u64) -> u64 { } pub mod time_driver { - use super::{ - ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, EVTIMER_HI_MASK, - EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, Regs, bin_to_gray, now_ticks_read, - }; - use crate::pac; use core::sync::atomic::Ordering; use core::task::Waker; + use embassy_sync::waitqueue::AtomicWaker; use embassy_time_driver as etd; + + use super::{ + bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, + EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, + }; + use crate::pac; pub struct Driver; static TIMER_WAKER: AtomicWaker = AtomicWaker::new(); @@ -569,12 +553,8 @@ pub mod time_driver { critical_section::with(|_| { // Mask INTENA and clear flag - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); // Read back to ensure W1C took effect on hardware let _ = r.osevent_ctrl().read().ostimer_intrflag().bit(); @@ -690,9 +670,7 @@ pub mod time_driver { /// Type-level handler to be used with bind_interrupts! for OS_EVENT. pub struct OsEventHandler; - impl crate::interrupt::typelevel::Handler - for OsEventHandler - { + impl crate::interrupt::typelevel::Handler for OsEventHandler { unsafe fn on_interrupt() { on_interrupt(); } diff --git a/src/pins.rs b/src/pins.rs index 1d92f9fef..f802568f3 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -84,10 +84,7 @@ pub unsafe fn set_pin_mux(port: u8, pin: u8, mux: u8) { }; if pin > max_pin { - panic!( - "Invalid pin {} for PORT{}, max pin is {}", - pin, port, max_pin - ); + panic!("Invalid pin {} for PORT{}, max pin is {}", pin, port, max_pin); } // Get the base address for the port diff --git a/src/rtc.rs b/src/rtc.rs index 5e3dfe6c1..d62da1f0a 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -1,7 +1,8 @@ //! RTC DateTime driver. +use core::sync::atomic::{AtomicBool, Ordering}; + use crate::pac; use crate::pac::rtc0::cr::Um; -use core::sync::atomic::{AtomicBool, Ordering}; type Regs = pac::rtc0::RegisterBlock; diff --git a/src/uart.rs b/src/uart.rs index 65dd91492..3209a318d 100644 --- a/src/uart.rs +++ b/src/uart.rs @@ -1,11 +1,13 @@ //! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering. //! WARNING: This is a narrow implementation only for debug console (115200 8N1). -use crate::pac; use core::cell::RefCell; + use cortex_m::interrupt::Mutex; use embassy_sync::signal::Signal; +use crate::pac; + // svd2rust defines the shared LPUART RegisterBlock under lpuart0; all instances reuse it. type Regs = pac::lpuart0::RegisterBlock; @@ -108,7 +110,7 @@ impl Uart { cortex_m::asm::delay(3); // Short delay for reset to take effect l.global().write(|w| w.rst().no_effect()); cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset - // 2) BAUD + // 2) BAUD let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud); l.baud().modify(|_, w| { let w = match cfg.stop_bits { @@ -234,8 +236,7 @@ impl RingBuffer { // Global RX buffer shared between interrupt handler and UART instance static RX_BUFFER: Mutex> = Mutex::new(RefCell::new(RingBuffer::new())); -static RX_SIGNAL: Signal = - Signal::new(); +static RX_SIGNAL: Signal = Signal::new(); // Debug counter for interrupt handler calls static mut INTERRUPT_COUNT: u32 = 0; @@ -279,9 +280,7 @@ impl Uart { /// Type-level handler for LPUART2 interrupts, compatible with bind_interrupts!. pub struct UartInterruptHandler; -impl crate::interrupt::typelevel::Handler - for UartInterruptHandler -{ +impl crate::interrupt::typelevel::Handler for UartInterruptHandler { unsafe fn on_interrupt() { INTERRUPT_COUNT += 1; -- cgit From 812f3c840f4d505e285d1ddce6b0981dd745e344 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 7 Nov 2025 10:43:32 -0800 Subject: Reintroduce necessary files Signed-off-by: Felipe Balbi --- .github/DOCS.md | 23 ++ .github/codecov.yml | 21 ++ .github/dependabot.yml | 19 ++ .github/workflows/cargo-vet-pr-comment.yml | 137 +++++++++ .github/workflows/cargo-vet.yml | 53 ++++ .github/workflows/check.yml | 205 +++++++++++++ .github/workflows/nostd.yml | 43 +++ .github/workflows/rolling.yml | 68 +++++ CODE_OF_CONDUCT.md | 132 ++++++++ CONTRIBUTING.md | 48 +++ LICENSE | 22 ++ License.txt | 22 -- README.md | 362 ++++++++++++++++++++++ README.txt | 346 --------------------- SECURITY.md | 66 ++++ deny.toml | 241 +++++++++++++++ supply-chain/README.md | 149 +++++++++ supply-chain/audits.toml | 38 +++ supply-chain/config.toml | 226 ++++++++++++++ supply-chain/imports.lock | 472 +++++++++++++++++++++++++++++ 20 files changed, 2325 insertions(+), 368 deletions(-) create mode 100644 .github/DOCS.md create mode 100644 .github/codecov.yml create mode 100644 .github/dependabot.yml create mode 100644 .github/workflows/cargo-vet-pr-comment.yml create mode 100644 .github/workflows/cargo-vet.yml create mode 100644 .github/workflows/check.yml create mode 100644 .github/workflows/nostd.yml create mode 100644 .github/workflows/rolling.yml create mode 100644 CODE_OF_CONDUCT.md create mode 100644 CONTRIBUTING.md create mode 100644 LICENSE delete mode 100644 License.txt create mode 100644 README.md delete mode 100644 README.txt create mode 100644 SECURITY.md create mode 100644 deny.toml create mode 100644 supply-chain/README.md create mode 100644 supply-chain/audits.toml create mode 100644 supply-chain/config.toml create mode 100644 supply-chain/imports.lock diff --git a/.github/DOCS.md b/.github/DOCS.md new file mode 100644 index 000000000..e932784c7 --- /dev/null +++ b/.github/DOCS.md @@ -0,0 +1,23 @@ +# Github config and workflows + +In this folder there is configuration for codecoverage, dependabot, and ci +workflows that check the library more deeply than the default configurations. + +This folder can be or was merged using a --allow-unrelated-histories merge +strategy from which provides a +reasonably sensible base for writing your own ci on. By using this strategy +the history of the CI repo is included in your repo, and future updates to +the CI can be merged later. + +To perform this merge run: + +```shell +git remote add ci https://github.com/jonhoo/rust-ci-conf.git +git fetch ci +git merge --allow-unrelated-histories ci/main +``` + +An overview of the files in this project is available at: +, which contains some +rationale for decisions and runs through an example of solving minimal version +and OpenSSL issues. diff --git a/.github/codecov.yml b/.github/codecov.yml new file mode 100644 index 000000000..cd5ce8fc1 --- /dev/null +++ b/.github/codecov.yml @@ -0,0 +1,21 @@ +# ref: https://docs.codecov.com/docs/codecovyml-reference +coverage: + # Hold ourselves to a high bar + range: 85..100 + round: down + precision: 1 + status: + # ref: https://docs.codecov.com/docs/commit-status + project: + default: + # Avoid false negatives + threshold: 1% + +# Test files aren't important for coverage +ignore: + - "tests" + +# Make comments less noisy +comment: + layout: "files" + require_changes: true diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 000000000..d0f091e7b --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,19 @@ +version: 2 +updates: + - package-ecosystem: github-actions + directory: / + schedule: + interval: daily + - package-ecosystem: cargo + directory: / + schedule: + interval: daily + ignore: + - dependency-name: "*" + # patch and minor updates don't matter for libraries as consumers of this library build + # with their own lockfile, rather than the version specified in this library's lockfile + # remove this ignore rule if your package has binaries to ensure that the binaries are + # built with the exact set of dependencies and those are up to date. + update-types: + - "version-update:semver-patch" + - "version-update:semver-minor" diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml new file mode 100644 index 000000000..dd8ef37a6 --- /dev/null +++ b/.github/workflows/cargo-vet-pr-comment.yml @@ -0,0 +1,137 @@ +# This workflow triggers after cargo-vet workflow has run. +# It adds a comment to the PR with the results of the cargo vet run. +# It first adds a comment if the cargo vet run fails, +# and updates the comment if the cargo vet run succeeds after having failed at least once. + +name: Cargo vet PR comment + +on: + workflow_run: + workflows: [cargo-vet] + types: + - completed + +permissions: + contents: read + pull-requests: write + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +jobs: + + find-pr-comment: + # This job runs when the cargo-vet job fails or succeeds + # It will download the artifact from the failed job and post a comment on the PR + runs-on: ubuntu-latest + outputs: + comment-id: ${{ steps.get-comment-id.outputs.comment-id }} + pr-number: ${{ steps.get-pr-number.outputs.pr_number }} + if: github.event.workflow_run.event == 'pull_request' + steps: + - name: 'Download artifact' + uses: actions/download-artifact@v4 + with: + github-token: ${{ secrets.GITHUB_TOKEN }} + name: pr + path: pr/ + run-id: ${{ github.event.workflow_run.id }} + + - name: 'Get PR number' + id: get-pr-number + run: echo "pr_number=$(cat ./pr/NR)" >> $GITHUB_OUTPUT + + - name: 'Find existing comment' + id: find-comment + uses: peter-evans/find-comment@v3 + with: + issue-number: ${{ steps.get-pr-number.outputs.pr_number }} + comment-author: 'github-actions[bot]' + body-includes: 'comment-tag: [cargo-vet]' + + - name: 'Get comment ID' + id: get-comment-id + if: ${{ steps.find-comment.outputs.comment-id != '' }} + run: echo "comment-id=${{ steps.find-comment.outputs.comment-id }}" >> $GITHUB_OUTPUT + + post-comment-failure: + # This job runs when the cargo-vet job fails + # It will download the artifact from the failed job and post a comment on the PR + runs-on: ubuntu-latest + needs: find-pr-comment + if: github.event.workflow_run.conclusion == 'failure' + steps: + - name: 'Comment on PR - Failure' + uses: peter-evans/create-or-update-comment@v4 + with: + comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} + issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} + body: | + # Cargo Vet Audit Failed + + `cargo vet` has failed in this PR. Please run `cargo vet --locked` locally to check for new or updated unvetted dependencies. + Details about the vetting process can be found in [supply-chain/README.md](../blob/main/supply-chain/README.md) + + ## If the unvetted dependencies are not needed + Please modify Cargo.toml file to avoid including the dependencies. + + ## If the unvetted dependencies are needed + Post a new comment with the questionnaire below to the PR to help the auditors vet the dependencies. + After the auditors have vetted the dependencies, the PR will need to be rebased to pick up the new audits and pass this check. + + ### Copy and paste the questionnaire as a new comment and provide your answers: + + **1. What crates (with version) need to be audited?** + + **2. How many of the crates are version updates vs new dependencies?** + + **3. To confirm none of the already included crates serve your needs, please provide a brief description of the purpose of the new crates.** + + **4. Any extra notes to the auditors to help with their audits.** + + + edit-mode: replace + + - name: 'Label PR' + uses: actions/github-script@v7 + with: + script: | + github.rest.issues.addLabels({ + issue_number: ${{ needs.find-pr-comment.outputs.pr-number }}, + owner: context.repo.owner, + repo: context.repo.repo, + labels: ['cargo vet'] + }) + + post-comment-success: + # This job runs when the cargo-vet job succeeds + # It will update the comment on the PR with a success message + runs-on: ubuntu-latest + needs: find-pr-comment + if: github.event.workflow_run.conclusion == 'success' + steps: + - name: 'Comment on PR - Success' + # Only update the comment if it exists + # This is to avoid creating a new comment if the cargo-vet job has never failed before + if: ${{ needs.find-pr-comment.outputs.comment-id }} + uses: peter-evans/create-or-update-comment@v4 + with: + comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} + issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} + body: | + # Cargo Vet Audit Passed + `cargo vet` has passed in this PR. No new unvetted dependencies were found. + + + edit-mode: replace \ No newline at end of file diff --git a/.github/workflows/cargo-vet.yml b/.github/workflows/cargo-vet.yml new file mode 100644 index 000000000..864c138e9 --- /dev/null +++ b/.github/workflows/cargo-vet.yml @@ -0,0 +1,53 @@ +# This workflow runs whenever a PR is opened or updated. It runs cargo vet to check for unvetted dependencies in the Cargo.lock file. +permissions: + contents: read +on: + pull_request: + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +name: cargo-vet +jobs: + vet: + # cargo-vet checks for unvetted dependencies in the Cargo.lock file + # This is to ensure that new dependencies are vetted before they are added to the project + name: vet-dependencies + runs-on: ubuntu-latest + env: + CARGO_VET_VERSION: 0.10.1 + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - uses: actions/cache@v4 + with: + path: ${{ runner.tool_cache }}/cargo-vet + key: cargo-vet-bin-${{ env.CARGO_VET_VERSION }} + + - name: Add the tool cache directory to the search path + run: echo "${{ runner.tool_cache }}/cargo-vet/bin" >> $GITHUB_PATH + + - name: Ensure that the tool cache is populated with the cargo-vet binary + run: cargo install --root ${{ runner.tool_cache }}/cargo-vet --version ${{ env.CARGO_VET_VERSION }} cargo-vet + + - name: Invoke cargo-vet + run: cargo vet --locked + + - name: Save PR number + # PR number is saved as an artifact so it can be used to determine the PR to comment on by the vet-pr-comment workflow + # vet-pr-comment workflow is triggered by the workflow_run event so it runs in the context of the base branch and not the PR branch + if: ${{ failure() }} || ${{ success() }} + run: | + mkdir -p ./pr + echo ${{ github.event.number }} > ./pr/NR + - uses: actions/upload-artifact@v4 + # Need to upload the artifact in both success and failure cases so comment can be updated in either case + if: ${{ failure() }} || ${{ success() }} + with: + name: pr + path: pr/ + overwrite: true \ No newline at end of file diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml new file mode 100644 index 000000000..1a09a1492 --- /dev/null +++ b/.github/workflows/check.yml @@ -0,0 +1,205 @@ +# This workflow runs whenever a PR is opened or updated, or a commit is pushed to main. It runs +# several checks: +# - fmt: checks that the code is formatted according to rustfmt +# - clippy: checks that the code does not contain any clippy warnings +# - doc: checks that the code can be documented without errors +# - hack: check combinations of feature flags +# - msrv: check that the msrv specified in the crate is correct +permissions: + contents: read + +# This configuration allows maintainers of this repo to create a branch and pull request based on +# the new branch. Restricting the push trigger to the main branch ensures that the PR only gets +# built once. +on: + + push: + branches: [main, main-nextgen] + pull_request: + +# If new code is pushed to a PR branch, then cancel in progress workflows for that PR. Ensures that +# we don't waste CI time, and returns results quicker https://github.com/jonhoo/rust-ci-conf/pull/5 +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +name: check + +jobs: + + fmt: + runs-on: ubuntu-latest + name: nightly / fmt + + strategy: + fail-fast: false + matrix: + workdir: [ ".", "examples/rt633", "examples/rt685s-evk",] + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - name: Install nightly + uses: dtolnay/rust-toolchain@nightly + with: + components: rustfmt + + - name: cargo fmt --check + run: cargo fmt --check + working-directory: ${{ matrix.workdir }} + + clippy-examples: + runs-on: ubuntu-latest + name: ${{ matrix.toolchain }} / clippy + + permissions: + contents: read + checks: write + + strategy: + fail-fast: false + matrix: + # Get early warning of new lints which are regularly introduced in beta channels. + toolchain: [stable] + workdir: ["examples"] + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - name: Install ${{ matrix.toolchain }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.toolchain }} + components: clippy + + - name: cargo clippy + working-directory: ${{ matrix.workdir }} + run: | + cargo clippy --locked -- -Dwarnings -D clippy::suspicious -D clippy::correctness -D clippy::perf -D clippy::style + + # Enable once we have a released crate + # semver: + # runs-on: ubuntu-latest + # name: semver + # steps: + # - uses: actions/checkout@v4 + # with: + # submodules: true + # - name: Install stable + # uses: dtolnay/rust-toolchain@stable + # with: + # components: rustfmt + # - name: cargo-semver-checks + # uses: obi1kenobi/cargo-semver-checks-action@v2 + + doc: + # run docs generation on nightly rather than stable. This enables features like + # https://doc.rust-lang.org/beta/unstable-book/language-features/doc-cfg.html which allows an + # API be documented as only available in some specific platforms. + runs-on: ubuntu-latest + name: nightly / doc + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - name: Install nightly + uses: dtolnay/rust-toolchain@nightly + + - name: cargo doc + run: | + cargo doc --no-deps --all-features --locked + env: + RUSTDOCFLAGS: --cfg docsrs + + hack: + # cargo-hack checks combinations of feature flags to ensure that features are all additive + # which is required for feature unification + runs-on: ubuntu-latest + name: ubuntu / stable / features + + strategy: + fail-fast: false + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - name: Install stable + uses: dtolnay/rust-toolchain@stable + with: + toolchain: stable + components: clippy + + - name: rustup target add thumbv8m.main-none-eabihf + run: rustup target add thumbv8m.main-none-eabihf + + - name: cargo hack + run: cargo hack --feature-powerset check + + deny: + # cargo-deny checks licenses, advisories, sources, and bans for + # our dependencies. + runs-on: ubuntu-latest + name: ubuntu / stable / deny + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - name: Install stable + uses: dtolnay/rust-toolchain@stable + + - name: cargo install cargo-deny + uses: EmbarkStudios/cargo-deny-action@v2 + with: + log-level: warn + manifest-path: ./Cargo.toml + command: check + arguments: --all-features --locked + + msrv: + # check that we can build using the minimal rust version that is specified by this crate + runs-on: ubuntu-latest + # we use a matrix here just because env can't be used in job names + # https://docs.github.com/en/actions/learn-github-actions/contexts#context-availability + strategy: + fail-fast: false + matrix: + msrv: ["1.90"] # We're relying on namespaced-features, which + # was released in 1.60 + # + # We also depend on `fixed' which requires rust + # 1.71 + # + # Additionally, we depend on embedded-hal-async + # which requires 1.75 + # + # embassy-time requires 1.79 due to + # collapse_debuginfo + # + # embassy upstream switched to rust 1.85 + # + # unsigned_is_multiple_of requires 1.90, else we get clippy warnings + + name: ubuntu / ${{ matrix.msrv }} + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - name: Install ${{ matrix.msrv }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.msrv }} + + - name: cargo +${{ matrix.msrv }} check + run: | + cargo check --all-features --locked diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml new file mode 100644 index 000000000..92460bd0f --- /dev/null +++ b/.github/workflows/nostd.yml @@ -0,0 +1,43 @@ +# This workflow checks whether the library is able to run without the std library (e.g., embedded). +# This entire file should be removed if this crate does not support no-std. See check.yml for +# information about how the concurrency cancellation and workflow triggering works +permissions: + contents: read + +on: + push: + branches: [main, main-nextgen] + pull_request: + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +name: no-std + +jobs: + nostd: + runs-on: ubuntu-latest + name: ${{ matrix.target }} + + strategy: + matrix: + target: [thumbv8m.main-none-eabihf] + + steps: + - uses: actions/checkout@v4 + with: + submodules: true + + - name: Install stable + uses: dtolnay/rust-toolchain@stable + + - name: rustup target add ${{ matrix.target }} + run: rustup target add ${{ matrix.target }} + + - name: Show variable + run: echo ${{ env.TOKEN }} + + - name: cargo check + run: | + cargo check --target ${{ matrix.target }} --all-features --locked diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml new file mode 100644 index 000000000..f572954f9 --- /dev/null +++ b/.github/workflows/rolling.yml @@ -0,0 +1,68 @@ +# This workflow runs every morning at midnight. It will run cargo hack +# and a build with msrv. If any dependency breaks our crate, we will +# know ASAP. +# +# - check: build with all features +# - msrv: check that the msrv specified in the crate is correct +permissions: + contents: read + +on: + schedule: + - cron: '0 0 * * *' + +name: rolling +jobs: + + check: + runs-on: ubuntu-latest + name: ubuntu / stable / features + strategy: + fail-fast: false + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install stable + uses: dtolnay/rust-toolchain@stable + - name: cargo install cargo-hack + uses: taiki-e/install-action@cargo-hack + - name: cargo check + run: | + cargo update + cargo check --all-features check + + msrv: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + msrv: ["1.85"] # We're relying on namespaced-features, which + # was released in 1.60 + # + # We also depend on `fixed' which requires rust + # 1.71 + # + # Additionally, we depend on embedded-hal-async + # which requires 1.75 + # + # embassy-time requires 1.79 due to + # collapse_debuginfo + # + # embassy upstream switched to rust 1.83 + # + # embedded-services (storage bus) dependency + # requires 1.85 + name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }}) + steps: + - uses: actions/checkout@v4 + with: + submodules: true + - name: Install ${{ matrix.msrv }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.msrv }} + - name: cargo +${{ matrix.msrv }} check + run: | + cargo update + cargo check --all-features check diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md new file mode 100644 index 000000000..54a673e04 --- /dev/null +++ b/CODE_OF_CONDUCT.md @@ -0,0 +1,132 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +We as members, contributors, and leaders pledge to make participation in our +community a harassment-free experience for everyone, regardless of age, body +size, visible or invisible disability, ethnicity, sex characteristics, gender +identity and expression, level of experience, education, socio-economic status, +nationality, personal appearance, race, caste, color, religion, or sexual +identity and orientation. + +We pledge to act and interact in ways that contribute to an open, welcoming, +diverse, inclusive, and healthy community. + +## Our Standards + +Examples of behavior that contributes to a positive environment for our +community include: + +* Demonstrating empathy and kindness toward other people +* Being respectful of differing opinions, viewpoints, and experiences +* Giving and gracefully accepting constructive feedback +* Accepting responsibility and apologizing to those affected by our mistakes, + and learning from the experience +* Focusing on what is best not just for us as individuals, but for the overall + community + +Examples of unacceptable behavior include: + +* The use of sexualized language or imagery, and sexual attention or advances of + any kind +* Trolling, insulting or derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or email address, + without their explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Enforcement Responsibilities + +Community leaders are responsible for clarifying and enforcing our standards of +acceptable behavior and will take appropriate and fair corrective action in +response to any behavior that they deem inappropriate, threatening, offensive, +or harmful. + +Community leaders have the right and responsibility to remove, edit, or reject +comments, commits, code, wiki edits, issues, and other contributions that are +not aligned to this Code of Conduct, and will communicate reasons for moderation +decisions when appropriate. + +## Scope + +This Code of Conduct applies within all community spaces, and also applies when +an individual is officially representing the community in public spaces. +Examples of representing our community include using an official e-mail address, +posting via an official social media account, or acting as an appointed +representative at an online or offline event. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported to the community leaders responsible for enforcement at +odpadmin@microsoft.com. +All complaints will be reviewed and investigated promptly and fairly. + +All community leaders are obligated to respect the privacy and security of the +reporter of any incident. + +## Enforcement Guidelines + +Community leaders will follow these Community Impact Guidelines in determining +the consequences for any action they deem in violation of this Code of Conduct: + +### 1. Correction + +**Community Impact**: Use of inappropriate language or other behavior deemed +unprofessional or unwelcome in the community. + +**Consequence**: A private, written warning from community leaders, providing +clarity around the nature of the violation and an explanation of why the +behavior was inappropriate. A public apology may be requested. + +### 2. Warning + +**Community Impact**: A violation through a single incident or series of +actions. + +**Consequence**: A warning with consequences for continued behavior. No +interaction with the people involved, including unsolicited interaction with +those enforcing the Code of Conduct, for a specified period of time. This +includes avoiding interactions in community spaces as well as external channels +like social media. Violating these terms may lead to a temporary or permanent +ban. + +### 3. Temporary Ban + +**Community Impact**: A serious violation of community standards, including +sustained inappropriate behavior. + +**Consequence**: A temporary ban from any sort of interaction or public +communication with the community for a specified period of time. No public or +private interaction with the people involved, including unsolicited interaction +with those enforcing the Code of Conduct, is allowed during this period. +Violating these terms may lead to a permanent ban. + +### 4. Permanent Ban + +**Community Impact**: Demonstrating a pattern of violation of community +standards, including sustained inappropriate behavior, harassment of an +individual, or aggression toward or disparagement of classes of individuals. + +**Consequence**: A permanent ban from any sort of public interaction within the +community. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], +version 2.1, available at +[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1]. + +Community Impact Guidelines were inspired by +[Mozilla's code of conduct enforcement ladder][Mozilla CoC]. + +For answers to common questions about this code of conduct, see the FAQ at +[https://www.contributor-covenant.org/faq][FAQ]. Translations are available at +[https://www.contributor-covenant.org/translations][translations]. + +[homepage]: https://www.contributor-covenant.org +[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html +[Mozilla CoC]: https://github.com/mozilla/diversity +[FAQ]: https://www.contributor-covenant.org/faq +[translations]: https://www.contributor-covenant.org/translations diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 000000000..7c8289a58 --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,48 @@ +# Contributing to Open Device Partnership + +The Open Device Partnership project welcomes your suggestions and contributions! Before opening your first issue or pull request, please review our +[Code of Conduct](CODE_OF_CONDUCT.md) to understand how our community interacts in an inclusive and respectful manner. + +## Contribution Licensing + +Most of our code is distributed under the terms of the [MIT license](LICENSE), and when you contribute code that you wrote to our repositories, +you agree that you are contributing under those same terms. In addition, by submitting your contributions you are indicating that +you have the right to submit those contributions under those terms. + +## Other Contribution Information + +If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your +pull request so that the project team can discuss the situation with you. + +# Contribution Guideline + +* For any new HAL driver added, please add corresponding test in the examples +* Format the code with `cargo fmt`. Or better yet, enable format on save in your IDE for rust source files. +* Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html) + +# PR Etiquette + +* Create a draft PR first +* Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers. + +# Careful Use of `Unsafe` + +Working with embedded, using of `unsafe` is a necessity. However, please wrap unsafe code with safe interfaces to prevent `unsafe` keyword being sprinkled everywhere. + +# RFC Draft PR + +If you want feedback on your design or HAL driver early, please create a draft PR with title prefix `RFC:`. + +# Branch Naming Scheme + +For now, we're not using forks. Eventually a personal fork will be required for any PRs to limit the amount of people with merge access to the main branch. Until that happens, please use meaningful branch names like this `user_alias/feature` and avoid sending PRs from branches containing prefixes such as "wip", "test", etc. Prior to sending a PR, please rename the branch. + +# Clean Commit History + +We disabled squashing of commit and would like to maintain a clean commit history. So please reorganize your commits with the following items: + * Each commit builds successfully without warning from `rustc` or `clippy` + * Miscellaneous commits to fix typos + formatting are squashed + +# Regressions + +When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster. diff --git a/LICENSE b/LICENSE new file mode 100644 index 000000000..479657c89 --- /dev/null +++ b/LICENSE @@ -0,0 +1,22 @@ +MIT License + +Copyright (c) 2025 OEMWCSE + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + diff --git a/License.txt b/License.txt deleted file mode 100644 index 479657c89..000000000 --- a/License.txt +++ /dev/null @@ -1,22 +0,0 @@ -MIT License - -Copyright (c) 2025 OEMWCSE - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - diff --git a/README.md b/README.md new file mode 100644 index 000000000..8a93b5f4a --- /dev/null +++ b/README.md @@ -0,0 +1,362 @@ +# Embassy MCXA276 HAL + +A Hardware Abstraction Layer (HAL) for the NXP MCXA276 microcontroller +using the Embassy async framework. This HAL provides safe, idiomatic +Rust interfaces for GPIO, UART, and OSTIMER peripherals. + +## Prerequisites + +### Ubuntu/Debian Setup + +```bash +# Install Rust toolchain +curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh +source ~/.cargo/env + +# Add target for MCXA276 (ARM Cortex-M33) +rustup target add thumbv8m.main-none-eabihf + +# Install required tools +sudo apt update +sudo apt install -y gdb-multiarch curl wget + +# Install probe-rs for running and debugging +cargo install probe-rs --features cli +``` + +### Windows Setup + +- Install Rust via https://rustup.rs (default options are fine) +- Add the MCXA276 target: + ```powershell + rustup target add thumbv8m.main-none-eabihf + ``` +- Install probe-rs CLI (we will use it directly; no GDB required): + ```powershell + cargo install probe-rs --features cli + ``` +- Install a serial terminal (e.g., Tera Term): https://ttssh2.osdn.jp/ +- USB drivers: Windows 10/11 usually picks up the board as a USB CDC device automatically (COM port) + +### Hardware Requirements + +- NXP FRDM-MCXA276 development board +- Debug probe (CMSIS-DAP compatible) +- USB cable for power and programming + +## Examples + +This HAL includes several examples demonstrating different peripherals: + +### GPIO Examples + +#### `blink` +Blinks an LED connected to GPIO pin. Demonstrates basic GPIO output operations. + +### UART Examples + +#### `hello` +Interactive UART2 demo: prints a banner and supports `help`, `echo `, `hex `. + +### OSTIMER Examples + +#### `ostimer_alarm` + +Demonstrates setting and waiting for OSTIMER alarms. + +#### `ostimer_async` +Shows asynchronous OSTIMER operations with Embassy's async runtime. + +#### `ostimer_counter` +Demonstrates OSTIMER counter functionality. + +#### `ostimer_race_test` +Advanced example testing OSTIMER race conditions and synchronization. + +### RTC Example + +#### `rtc_alarm` +Demonstrates how to enable and use the RTC to generate an interrupt after 10seconds. + +## Build and Run + +### Using probe-rs + +All examples require specifying your debug probe. First, find your probe ID: + +```bash +probe-rs list +``` + +Then run examples with your probe ID (replace `1fc9:0143:H3AYDQVQMTROB` with your actual probe): + +```bash +# GPIO blink example +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "gpio ostimer0" --example blink + + + +# UART hello example +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example hello + +# OSTIMER examples +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_async +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_counter +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_race_test + +# RTC example +PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 rtc0" --example rtc_alarm +``` + +**Note:** All examples run from RAM, not flash memory. They are loaded directly into RAM for faster development iteration. + +**Important:** After pressing the RESET button on the board, the first `cargo run` attempt may fail with a connection error. This is expected - simply run the command again and it will work. The run.sh script now properly sets the Vector Table Offset Register (VTOR) to point to the RAM-based vector table, ensuring the correct stack pointer and reset vector are used. + +```console +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink + Finished `release` profile [optimized + debuginfo] target(s) in 0.07s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` +probe-rs gdb server failed to connect to target. Log: +----- probe-rs gdb log ----- + Error: Connecting to the chip was unsuccessful. + + Caused by: + 0: An ARM specific error occurred. + 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. + 2: Failed to read register DRW at address 0xd0c + 3: An error occurred in the communication with an access port or debug port. + 4: Target device responded with a FAULT response to the request. +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink + Finished `release` profile [optimized + debuginfo] target(s) in 0.02s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` +``` + +### Additional UART Examples + +#### `uart_interrupt` +Interrupt-driven UART2 echo. Type in the serial terminal; each byte is echoed back from the IRQ handler path. + +#### `lpuart_polling` +Blocking TX/RX echo over UART2 using the simple polling driver. + +#### `lpuart_buffered` +Async buffered driver with separate TX/RX tasks; echoes typed characters in chunks. + +Pins: UART2 TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. + +### ADC Examples + +#### `adc_polling` +Configures ADC1 channel A8 (pin P1_10) and prints conversion values to UART2 periodically. + +#### `adc_interrupt` +Triggers a conversion and signals completion via ADC1 interrupt, printing a notification on UART2. + +```console +0x20002040 in ?? () +Supported Commands: + + info - print session information + reset - reset target + reset halt - reset target and halt afterwards + +Loading section .vector_table, size 0x224 lma 0x20000000 +Loading section .text, size 0x97e lma 0x20000224 +Loading section .Reset, size 0x58 lma 0x20000ba4 +Loading section .rodata, size 0x28 lma 0x20000bfc +Start address 0x20000ba4, load size 3106 +Transfer rate: 13 KB/sec, 776 bytes/write. +``` + +then I see the LED blinking. I press CTRL+C to exit. It will show me ^C + +```console +Program received signal SIGINT, Interrupt. +0x20000880 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 +106 asm!("wfe"); +[Inferior 1 (process 1) detached] +Program loaded and started (no reset) +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ \ + +Then I press RESET again and I want to run another example, like ostimer_alarm. I open the console using sudo picocom -b 115200 /dev/ttyACM0 and I start running the example: + +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm + Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` +probe-rs gdb server failed to connect to target. Log: +----- probe-rs gdb log ----- + Error: Connecting to the chip was unsuccessful. + + Caused by: + 0: An ARM specific error occurred. + 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. + 2: Failed to read register DRW at address 0xd0c + 3: An error occurred in the communication with an access port or debug port. + 4: Target device responded with a FAULT response to the request. +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm + Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s + Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` +0x20002040 in core::panicking::panic_const::panic_const_mul_overflow () at library/core/src/panicking.rs:175 +warning: 175 library/core/src/panicking.rs: No such file or directory +Supported Commands: + + info - print session information + reset - reset target + reset halt - reset target and halt afterwards + +Loading section .vector_table, size 0x224 lma 0x20000000 +Loading section .text, size 0x2226 lma 0x20000224 +Loading section .Reset, size 0x58 lma 0x2000244c +Loading section .rodata, size 0x6dc lma 0x200024a4 +Start address 0x2000244c, load size 11134 +Transfer rate: 16 KB/sec, 1855 bytes/write. +``` + +I can see in the console + +```console +OSTIMER Alarm Example +Scheduling alarm for 2 seconds... +Alarm scheduled successfully +Alarm expired! Callback executed. +Scheduling another alarm for 3 seconds... +Alarm scheduled. Waiting 1 second then canceling... +Alarm canceled +Alarm was successfully canceled +Example complete +``` + +then I press CTRL+C to stop running + +```console +^C +Program received signal SIGINT, Interrupt. +0x20000e64 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 +106 asm!("wfe"); +[Inferior 1 (process 1) detached] +Program loaded and started (no reset) +smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ +``` + +### Windows: Running examples (RAM, no RTT/defmt) + +Important: On Windows, do not use `cargo run` because `.cargo/config.toml` sets a Linux-only runner (`./run.sh`). Instead, use `probe-rs run` directly. + +1) Find your probe and COM port +- List probes: + + ```console + probe-rs list + ``` +- If multiple probes are attached, set the specific one (replace with your ID): + + ```console + $env:PROBE_RS_PROBE = "1366:0101:000600110607" + ``` + +- Check Windows Device Manager → Ports (COM & LPT) for the board’s COM port. + +2) Build the example + +```console +cargo build --example hello --features "lpuart2" +``` + +3) Run from RAM with probe-rs + +```console +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/hello +``` +You will see a short probe-rs warning like "unknown variant, try to set watch point"; it’s harmless. + +4) View output in Tera Term +- Open Tera Term, select the board’s COMx port, 115200 8N1 +- Expected behavior per example: + - hello: prints a banner; simple UART output + - lpuart_polling / lpuart_buffered / uart_interrupt: echo typed characters + - adc_polling: prints ADC values periodically (ADC1 channel A8 on P1_10) + - adc_interrupt: prints "*** ADC interrupt TRIGGERED! ***" upon conversion completion + - blink: LED on PIO3_18 blinks "SOS" pattern + - rtc_alarm: schedules, cancels and reports alarm events on UART + +Notes +- All examples run from RAM (not flashed). Reset clears the program. +- If the first attempt after a reset fails to connect, just run the command again. +- UART2 pins: TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. + +Quick commands for other examples: + +```console +# Build +cargo build --example blink --features "gpio ostimer0" +cargo build --example lpuart_polling --features "lpuart2 ostimer0" +cargo build --example lpuart_buffered --features "lpuart2 ostimer0" +cargo build --example uart_interrupt --features "lpuart2 ostimer0" +cargo build --example rtc_alarm --features "lpuart2 rtc0" +cargo build --example adc_polling --features "adc1 lpuart2" +cargo build --example adc_interrupt --features "adc1 lpuart2" + +# Run (RAM) +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/blink +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_polling +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_buffered +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/uart_interrupt +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/rtc_alarm +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_polling +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_interrupt +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_async +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_counter +probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_race_test +``` + +How I tested on Windows +- Windows 11; Rust stable; probe-rs 0.29.x +- Built each example as above; ran with `probe-rs run` (RAM execution) +- Observed UART output in Tera Term at 115200 8N1; all examples behaved as expected +- No RTT/defmt used; purely UART or LED observation + +### Build Only + +To build without running: + +```console +cargo build --features "gpio ostimer0" --example blink +cargo build --features "lpuart2 ostimer0" --example hello +cargo build --features "lpuart2 ostimer0" --example ostimer_alarm +cargo build --features "lpuart2 rtc0" --example rtc_alarm +# etc. +``` + +## Development Notes + +### Critical Fix: MCXA276 Interrupt Vector Table + + +Update (SVD 25.06.00, mcxa-pac a9dd33): No manual PAC edits are required anymore. OS_EVENT and WAKETIMER0 are present and the vector table is correct. The section below is kept for historical context. +**Problem:** The OSTIMER examples crashed during interrupt handling with a hardfault (SP=0x00000000). Investigation revealed the OS_EVENT interrupt vector was NULL in the vector table, causing the CPU to jump to address 0 when OSTIMER interrupts fired. + +**Root Cause:** The `mcxa276-pac/src/lib.rs` file (generated from the SVD file) was missing the `WAKETIMER0` interrupt handler declaration. This caused the `__INTERRUPTS` array to have an off-by-one error, placing OS_EVENT at IRQ 58 instead of the correct IRQ 57 position. + +**Solution:** Manually edited `mcxa276-pac/src/lib.rs` to add the missing WAKETIMER0 interrupt: + +1. Added `fn WAKETIMER0()` to the `extern "C"` block +2. Fixed the `__INTERRUPTS: [Vector; 122]` array sequence: + - Changed from: `LPTMR0, _reserved, _reserved, OS_EVENT, _reserved, UTICK0, ...` + - Changed to: `LPTMR0, _reserved, OS_EVENT, WAKETIMER0, UTICK0, WWDT0, _reserved, ADC0, ...` +3. Added `WAKETIMER0 = 58` to the `Interrupt` enum + +**Verification:** Binary analysis confirmed OS_EVENT is now at the correct position: +- IRQ 57 = word 73 = offset 0x124 in vector table +- OS_EVENT handler: 0x20000BB1 (verified with `arm-none-eabi-objdump`) + +**Note:** This is likely an issue with the NXP MCXA276.svd file or svd2rust generation. The WAKETIMER0 peripheral exists in the PAC but the interrupt handler was missing. Future regeneration of the PAC from SVD may require reapplying this fix. + +### Warning: Avoid `#[inline(always)]` in Performance-Critical Code + +Using `#[inline(always)]` can cause the Rust compiler to generate incorrect assembly, leading to register corruption or unexpected behavior. For example, in tight polling loops like those in the OSTIMER driver, this attribute may result in invalid instructions that zero registers (e.g., `movs r1, r0` causing r1=0), triggering hardfaults. + +## License + +This project is licensed under MIT OR Apache-2.0. diff --git a/README.txt b/README.txt deleted file mode 100644 index ae80ca8ef..000000000 --- a/README.txt +++ /dev/null @@ -1,346 +0,0 @@ -# Embassy MCXA276 HAL - -A Hardware Abstraction Layer (HAL) for the NXP MCXA276 microcontroller using the Embassy async framework. This HAL provides safe, idiomatic Rust interfaces for GPIO, UART, and OSTIMER peripherals. - -## Prerequisites - -### Ubuntu/Debian Setup - -```bash -# Install Rust toolchain -curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -source ~/.cargo/env - -# Add target for MCXA276 (ARM Cortex-M33) -rustup target add thumbv8m.main-none-eabihf - -# Install required tools -sudo apt update -sudo apt install -y gdb-multiarch curl wget - -# Install probe-rs for running and debugging -cargo install probe-rs --features cli -``` - -### Windows Setup - -- Install Rust via https://rustup.rs (default options are fine) -- Add the MCXA276 target: - ```powershell - rustup target add thumbv8m.main-none-eabihf - ``` -- Install probe-rs CLI (we will use it directly; no GDB required): - ```powershell - cargo install probe-rs --features cli - ``` -- Install a serial terminal (e.g., Tera Term): https://ttssh2.osdn.jp/ -- USB drivers: Windows 10/11 usually picks up the board as a USB CDC device automatically (COM port) - - - -### Hardware Requirements - -- NXP FRDM-MCXA276 development board -- Debug probe (CMSIS-DAP compatible) -- USB cable for power and programming - -## Examples - -This HAL includes several examples demonstrating different peripherals: - -### GPIO Examples - -#### `blink` -Blinks an LED connected to GPIO pin. Demonstrates basic GPIO output operations. - -### UART Examples - -#### `hello` -Interactive UART2 demo: prints a banner and supports `help`, `echo `, `hex `. - -### OSTIMER Examples - -#### `ostimer_alarm` - -Demonstrates setting and waiting for OSTIMER alarms. - -#### `ostimer_async` -Shows asynchronous OSTIMER operations with Embassy's async runtime. - -#### `ostimer_counter` -Demonstrates OSTIMER counter functionality. - -#### `ostimer_race_test` -Advanced example testing OSTIMER race conditions and synchronization. - -### RTC Example - -#### `rtc_alarm` -Demonstrates how to enable and use the RTC to generate an interrupt after 10seconds. - -## Build and Run - -### Using probe-rs - -All examples require specifying your debug probe. First, find your probe ID: - -```bash -probe-rs list -``` - -Then run examples with your probe ID (replace `1fc9:0143:H3AYDQVQMTROB` with your actual probe): - -```bash -# GPIO blink example -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "gpio ostimer0" --example blink - - - -# UART hello example -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example hello - -# OSTIMER examples -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_async -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_counter -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_race_test - -# RTC example -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 rtc0" --example rtc_alarm -``` -**Note:** All examples run from RAM, not flash memory. They are loaded directly into RAM for faster development iteration. - -**Important:** After pressing the RESET button on the board, the first `cargo run` attempt may fail with a connection error. This is expected - simply run the command again and it will work. The run.sh script now properly sets the Vector Table Offset Register (VTOR) to point to the RAM-based vector table, ensuring the correct stack pointer and reset vector are used. - -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink - Finished `release` profile [optimized + debuginfo] target(s) in 0.07s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` -probe-rs gdb server failed to connect to target. Log: ------ probe-rs gdb log ----- - Error: Connecting to the chip was unsuccessful. - - Caused by: - 0: An ARM specific error occurred. - 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. - 2: Failed to read register DRW at address 0xd0c - 3: An error occurred in the communication with an access port or debug port. - 4: Target device responded with a FAULT response to the request. -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink - Finished `release` profile [optimized + debuginfo] target(s) in 0.02s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` - -### Additional UART Examples - -#### `uart_interrupt` -Interrupt-driven UART2 echo. Type in the serial terminal; each byte is echoed back from the IRQ handler path. - -#### `lpuart_polling` -Blocking TX/RX echo over UART2 using the simple polling driver. - -#### `lpuart_buffered` -Async buffered driver with separate TX/RX tasks; echoes typed characters in chunks. - -Pins: UART2 TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. - -### ADC Examples - -#### `adc_polling` -Configures ADC1 channel A8 (pin P1_10) and prints conversion values to UART2 periodically. - -#### `adc_interrupt` -Triggers a conversion and signals completion via ADC1 interrupt, printing a notification on UART2. - -0x20002040 in ?? () -Supported Commands: - - info - print session information - reset - reset target - reset halt - reset target and halt afterwards - -Loading section .vector_table, size 0x224 lma 0x20000000 -Loading section .text, size 0x97e lma 0x20000224 -Loading section .Reset, size 0x58 lma 0x20000ba4 -Loading section .rodata, size 0x28 lma 0x20000bfc -Start address 0x20000ba4, load size 3106 -Transfer rate: 13 KB/sec, 776 bytes/write. - -then I see the LED blinking. I press CTRL+C to exit. It will show me ^C -Program received signal SIGINT, Interrupt. -0x20000880 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 -106 asm!("wfe"); -[Inferior 1 (process 1) detached] -Program loaded and started (no reset) -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ \ - -Then I press RESET again and I want to run another example, like ostimer_alarm. I open the console using sudo picocom -b 115200 /dev/ttyACM0 and I start running the example: - -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm - Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` -probe-rs gdb server failed to connect to target. Log: ------ probe-rs gdb log ----- - Error: Connecting to the chip was unsuccessful. - - Caused by: - 0: An ARM specific error occurred. - 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. - 2: Failed to read register DRW at address 0xd0c - 3: An error occurred in the communication with an access port or debug port. - 4: Target device responded with a FAULT response to the request. -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm - Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` -0x20002040 in core::panicking::panic_const::panic_const_mul_overflow () at library/core/src/panicking.rs:175 -warning: 175 library/core/src/panicking.rs: No such file or directory -Supported Commands: - - info - print session information - reset - reset target - reset halt - reset target and halt afterwards - -Loading section .vector_table, size 0x224 lma 0x20000000 -Loading section .text, size 0x2226 lma 0x20000224 -Loading section .Reset, size 0x58 lma 0x2000244c -Loading section .rodata, size 0x6dc lma 0x200024a4 -Start address 0x2000244c, load size 11134 -Transfer rate: 16 KB/sec, 1855 bytes/write. - -I can see in the console -OSTIMER Alarm Example -Scheduling alarm for 2 seconds... -Alarm scheduled successfully -Alarm expired! Callback executed. -Scheduling another alarm for 3 seconds... -Alarm scheduled. Waiting 1 second then canceling... -Alarm canceled -Alarm was successfully canceled -Example complete - -then I press CTRL+C to stop running - -^C -Program received signal SIGINT, Interrupt. -0x20000e64 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 -106 asm!("wfe"); -[Inferior 1 (process 1) detached] -Program loaded and started (no reset) -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ - - -### Windows: Running examples (RAM, no RTT/defmt) - -Important: On Windows, do not use `cargo run` because `.cargo/config.toml` sets a Linux-only runner (`./run.sh`). Instead, use `probe-rs run` directly. - -1) Find your probe and COM port -- List probes: - ```powershell - probe-rs list - ``` -- If multiple probes are attached, set the specific one (replace with your ID): - ```powershell - $env:PROBE_RS_PROBE = "1366:0101:000600110607" - ``` -- Check Windows Device Manager → Ports (COM & LPT) for the board’s COM port. - -2) Build the example -```powershell -cargo build --example hello --features "lpuart2" -``` - -3) Run from RAM with probe-rs -```powershell -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/hello -``` -You will see a short probe-rs warning like "unknown variant, try to set watch point"; it’s harmless. - -4) View output in Tera Term -- Open Tera Term, select the board’s COMx port, 115200 8N1 -- Expected behavior per example: - - hello: prints a banner; simple UART output - - lpuart_polling / lpuart_buffered / uart_interrupt: echo typed characters - - adc_polling: prints ADC values periodically (ADC1 channel A8 on P1_10) - - adc_interrupt: prints "*** ADC interrupt TRIGGERED! ***" upon conversion completion - - blink: LED on PIO3_18 blinks "SOS" pattern - - rtc_alarm: schedules, cancels and reports alarm events on UART - -Notes -- All examples run from RAM (not flashed). Reset clears the program. -- If the first attempt after a reset fails to connect, just run the command again. -- UART2 pins: TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. - -Quick commands for other examples (PowerShell) -```powershell -# Build -cargo build --example blink --features "gpio ostimer0" -cargo build --example lpuart_polling --features "lpuart2 ostimer0" -cargo build --example lpuart_buffered --features "lpuart2 ostimer0" -cargo build --example uart_interrupt --features "lpuart2 ostimer0" -cargo build --example rtc_alarm --features "lpuart2 rtc0" -cargo build --example adc_polling --features "adc1 lpuart2" -cargo build --example adc_interrupt --features "adc1 lpuart2" - -# Run (RAM) -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/blink -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_polling -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_buffered -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/uart_interrupt -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/rtc_alarm -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_polling -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_interrupt -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_async -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_counter -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_race_test -``` - -How I tested on Windows -- Windows 11; Rust stable; probe-rs 0.29.x -- Built each example as above; ran with `probe-rs run` (RAM execution) -- Observed UART output in Tera Term at 115200 8N1; all examples behaved as expected -- No RTT/defmt used; purely UART or LED observation - -### Build Only - -To build without running: - -```bash -cargo build --features "gpio ostimer0" --example blink -cargo build --features "lpuart2 ostimer0" --example hello -cargo build --features "lpuart2 ostimer0" --example ostimer_alarm -cargo build --features "lpuart2 rtc0" --example rtc_alarm -# etc. -``` - - -## Development Notes - -### Critical Fix: MCXA276 Interrupt Vector Table - - -Update (SVD 25.06.00, mcxa-pac a9dd33): No manual PAC edits are required anymore. OS_EVENT and WAKETIMER0 are present and the vector table is correct. The section below is kept for historical context. -**Problem:** The OSTIMER examples crashed during interrupt handling with a hardfault (SP=0x00000000). Investigation revealed the OS_EVENT interrupt vector was NULL in the vector table, causing the CPU to jump to address 0 when OSTIMER interrupts fired. - -**Root Cause:** The `mcxa276-pac/src/lib.rs` file (generated from the SVD file) was missing the `WAKETIMER0` interrupt handler declaration. This caused the `__INTERRUPTS` array to have an off-by-one error, placing OS_EVENT at IRQ 58 instead of the correct IRQ 57 position. - -**Solution:** Manually edited `mcxa276-pac/src/lib.rs` to add the missing WAKETIMER0 interrupt: - -1. Added `fn WAKETIMER0()` to the `extern "C"` block -2. Fixed the `__INTERRUPTS: [Vector; 122]` array sequence: - - Changed from: `LPTMR0, _reserved, _reserved, OS_EVENT, _reserved, UTICK0, ...` - - Changed to: `LPTMR0, _reserved, OS_EVENT, WAKETIMER0, UTICK0, WWDT0, _reserved, ADC0, ...` -3. Added `WAKETIMER0 = 58` to the `Interrupt` enum - -**Verification:** Binary analysis confirmed OS_EVENT is now at the correct position: -- IRQ 57 = word 73 = offset 0x124 in vector table -- OS_EVENT handler: 0x20000BB1 (verified with `arm-none-eabi-objdump`) - -**Note:** This is likely an issue with the NXP MCXA276.svd file or svd2rust generation. The WAKETIMER0 peripheral exists in the PAC but the interrupt handler was missing. Future regeneration of the PAC from SVD may require reapplying this fix. - -### Warning: Avoid `#[inline(always)]` in Performance-Critical Code - -Using `#[inline(always)]` can cause the Rust compiler to generate incorrect assembly, leading to register corruption or unexpected behavior. For example, in tight polling loops like those in the OSTIMER driver, this attribute may result in invalid instructions that zero registers (e.g., `movs r1, r0` causing r1=0), triggering hardfaults. - - -## License - -This project is licensed under MIT OR Apache-2.0. \ No newline at end of file diff --git a/SECURITY.md b/SECURITY.md new file mode 100644 index 000000000..5357b8824 --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,66 @@ +# Vulnerability Disclosure and Embargo Policy + +The Open Device Partnership project welcomes the responsible disclosure of vulnerabilities. + +## Initial Contact + +All security bugs in Open Device Partnership should be reported to the security team. +To do so, please reach out in the form of a +[Github Security Advisory](https://docs.github.com/en/code-security/security-advisories/guidance-on-reporting-and-writing-information-about-vulnerabilities). + +You will be invited to join this private area to discuss specifics. Doing so +allows us to start with a high level of confidentiality and relax it if the +issue is less critical, moving to work on the fix in the open. + +Your initial contact will be acknowledged within 48 hours, and you’ll receive +a more detailed response within 96 hours indicating the next steps in handling +your report. + +After the initial reply to your report, the security team will endeavor to +keep you informed of the progress being made towards a fix and full +announcement. As recommended by +[RFPolicy](https://dl.packetstormsecurity.net/papers/general/rfpolicy-2.0.txt), +these updates will be sent at least every five working days. + +## Disclosure Policy + +The Open Device Partnership project has a 5 step disclosure process. + +1. Contact is established, a private channel created, and the security report + is received and is assigned a primary handler. This person will coordinate + the fix and release process. +2. The problem is confirmed and a list of all affected versions is determined. + If an embargo is needed (see below), details of the embargo are decided. +3. Code is audited to find any potential similar problems. +4. Fixes are prepared for all releases which are still under maintenance. In + case of embargo, these fixes are not committed to the public repository but + rather held in a private fork pending the announcement. +5. The changes are pushed to the public repository and new builds are deployed. + +This process can take some time, especially when coordination is required +with maintainers of other projects. Every effort will be made to handle the bug +in as timely a manner as possible, however it is important that we follow the +release process above to ensure that the disclosure is handled in a consistent +manner. + +## Embargoes + +While the Open Device Partnership project aims to follow the highest standards of +transparency and openness, handling some security issues may pose such an +immediate threat to various stakeholders and require coordination between +various actors that it cannot be made immediately public. + +In this case, security issues will fall under an embargo. + +An embargo can be called for in various cases: + +- when disclosing the issue without simultaneously providing a mitigation + would seriously endanger users, +- when producing a fix requires coordinating between multiple actors (such as + upstream or downstream/dependency projects), or simply +- when proper analysis of the issue and its ramifications demands time. + +If we determine that an issue you report requires an embargo, we will discuss +this with you and try to find a reasonable expiry date (aka “embargo +completion date”), as well as who should be included in the list of +need-to-know people. diff --git a/deny.toml b/deny.toml new file mode 100644 index 000000000..7097f2f55 --- /dev/null +++ b/deny.toml @@ -0,0 +1,241 @@ +# This template contains all of the possible sections and their default values + +# Note that all fields that take a lint level have these possible values: +# * deny - An error will be produced and the check will fail +# * warn - A warning will be produced, but the check will not fail +# * allow - No warning or error will be produced, though in some cases a note +# will be + +# The values provided in this template are the default values that will be used +# when any section or field is not specified in your own configuration + +# Root options + +# The graph table configures how the dependency graph is constructed and thus +# which crates the checks are performed against +[graph] +# If 1 or more target triples (and optionally, target_features) are specified, +# only the specified targets will be checked when running `cargo deny check`. +# This means, if a particular package is only ever used as a target specific +# dependency, such as, for example, the `nix` crate only being used via the +# `target_family = "unix"` configuration, that only having windows targets in +# this list would mean the nix crate, as well as any of its exclusive +# dependencies not shared by any other crates, would be ignored, as the target +# list here is effectively saying which targets you are building for. +targets = [ + # The triple can be any string, but only the target triples built in to + # rustc (as of 1.40) can be checked against actual config expressions + #"x86_64-unknown-linux-musl", + # You can also specify which target_features you promise are enabled for a + # particular target. target_features are currently not validated against + # the actual valid features supported by the target architecture. + #{ triple = "wasm32-unknown-unknown", features = ["atomics"] }, +] +# When creating the dependency graph used as the source of truth when checks are +# executed, this field can be used to prune crates from the graph, removing them +# from the view of cargo-deny. This is an extremely heavy hammer, as if a crate +# is pruned from the graph, all of its dependencies will also be pruned unless +# they are connected to another crate in the graph that hasn't been pruned, +# so it should be used with care. The identifiers are [Package ID Specifications] +# (https://doc.rust-lang.org/cargo/reference/pkgid-spec.html) +#exclude = [] +# If true, metadata will be collected with `--all-features`. Note that this can't +# be toggled off if true, if you want to conditionally enable `--all-features` it +# is recommended to pass `--all-features` on the cmd line instead +all-features = false +# If true, metadata will be collected with `--no-default-features`. The same +# caveat with `all-features` applies +no-default-features = false +# If set, these feature will be enabled when collecting metadata. If `--features` +# is specified on the cmd line they will take precedence over this option. +#features = [] + +# The output table provides options for how/if diagnostics are outputted +[output] +# When outputting inclusion graphs in diagnostics that include features, this +# option can be used to specify the depth at which feature edges will be added. +# This option is included since the graphs can be quite large and the addition +# of features from the crate(s) to all of the graph roots can be far too verbose. +# This option can be overridden via `--feature-depth` on the cmd line +feature-depth = 1 + +# This section is considered when running `cargo deny check advisories` +# More documentation for the advisories section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/advisories/cfg.html +[advisories] +# The path where the advisory databases are cloned/fetched into +#db-path = "$CARGO_HOME/advisory-dbs" +# The url(s) of the advisory databases to use +#db-urls = ["https://github.com/rustsec/advisory-db"] +# A list of advisory IDs to ignore. Note that ignored advisories will still +# output a note when they are encountered. +ignore = [ + #"RUSTSEC-0000-0000", + #{ id = "RUSTSEC-0000-0000", reason = "you can specify a reason the advisory is ignored" }, + #"a-crate-that-is-yanked@0.1.1", # you can also ignore yanked crate versions if you wish + #{ crate = "a-crate-that-is-yanked@0.1.1", reason = "you can specify why you are ignoring the yanked crate" }, + # { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." }, + { id = "RUSTSEC-2024-0436", reason = "there are no suitable replacements for paste right now; paste has been archived as read-only. It only affects compile time concatenation in macros. We will allow it for now" }, + # { id = "RUSTSEC-2023-0089", reason = "this is a deprecation warning for a dependency of a dependency. https://github.com/jamesmunns/postcard/issues/223 tracks fixing the dependency; until that's resolved, we can accept the deprecated code as it has no known vulnerabilities."} +] +# If this is true, then cargo deny will use the git executable to fetch advisory database. +# If this is false, then it uses a built-in git library. +# Setting this to true can be helpful if you have special authentication requirements that cargo-deny does not support. +# See Git Authentication for more information about setting up git authentication. +#git-fetch-with-cli = true + +# This section is considered when running `cargo deny check licenses` +# More documentation for the licenses section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/licenses/cfg.html +[licenses] +# List of explicitly allowed licenses +# See https://spdx.org/licenses/ for list of possible licenses +# [possible values: any SPDX 3.11 short identifier (+ optional exception)]. +allow = [ + "MIT", + "Apache-2.0", + + # unicode-ident 1.0.14 switched from Unicode-DFS-2016 to Unicode-3.0 license. + "Unicode-3.0", + #"Apache-2.0 WITH LLVM-exception", +] +# The confidence threshold for detecting a license from license text. +# The higher the value, the more closely the license text must be to the +# canonical license text of a valid SPDX license file. +# [possible values: any between 0.0 and 1.0]. +confidence-threshold = 0.8 +# Allow 1 or more licenses on a per-crate basis, so that particular licenses +# aren't accepted for every possible crate as with the normal allow list +exceptions = [ + # Each entry is the crate and version constraint, and its specific allow + # list + #{ allow = ["Zlib"], crate = "adler32" }, +] + +# Some crates don't have (easily) machine readable licensing information, +# adding a clarification entry for it allows you to manually specify the +# licensing information +#[[licenses.clarify]] +# The package spec the clarification applies to +#crate = "ring" +# The SPDX expression for the license requirements of the crate +#expression = "MIT AND ISC AND OpenSSL" +# One or more files in the crate's source used as the "source of truth" for +# the license expression. If the contents match, the clarification will be used +# when running the license check, otherwise the clarification will be ignored +# and the crate will be checked normally, which may produce warnings or errors +# depending on the rest of your configuration +#license-files = [ +# Each entry is a crate relative path, and the (opaque) hash of its contents +#{ path = "LICENSE", hash = 0xbd0eed23 } +#] + +[licenses.private] +# If true, ignores workspace crates that aren't published, or are only +# published to private registries. +# To see how to mark a crate as unpublished (to the official registry), +# visit https://doc.rust-lang.org/cargo/reference/manifest.html#the-publish-field. +ignore = false +# One or more private registries that you might publish crates to, if a crate +# is only published to private registries, and ignore is true, the crate will +# not have its license(s) checked +registries = [ + #"https://sekretz.com/registry +] + +# This section is considered when running `cargo deny check bans`. +# More documentation about the 'bans' section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/bans/cfg.html +[bans] +# Lint level for when multiple versions of the same crate are detected +multiple-versions = "warn" +# Lint level for when a crate version requirement is `*` +wildcards = "allow" +# The graph highlighting used when creating dotgraphs for crates +# with multiple versions +# * lowest-version - The path to the lowest versioned duplicate is highlighted +# * simplest-path - The path to the version with the fewest edges is highlighted +# * all - Both lowest-version and simplest-path are used +highlight = "all" +# The default lint level for `default` features for crates that are members of +# the workspace that is being checked. This can be overridden by allowing/denying +# `default` on a crate-by-crate basis if desired. +workspace-default-features = "allow" +# The default lint level for `default` features for external crates that are not +# members of the workspace. This can be overridden by allowing/denying `default` +# on a crate-by-crate basis if desired. +external-default-features = "allow" +# List of crates that are allowed. Use with care! +allow = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is allowed" }, +] +# List of crates to deny +deny = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is banned" }, + # Wrapper crates can optionally be specified to allow the crate when it + # is a direct dependency of the otherwise banned crate + #{ crate = "ansi_term@0.11.0", wrappers = ["this-crate-directly-depends-on-ansi_term"] }, +] + +# List of features to allow/deny +# Each entry the name of a crate and a version range. If version is +# not specified, all versions will be matched. +#[[bans.features]] +#crate = "reqwest" +# Features to not allow +#deny = ["json"] +# Features to allow +#allow = [ +# "rustls", +# "__rustls", +# "__tls", +# "hyper-rustls", +# "rustls", +# "rustls-pemfile", +# "rustls-tls-webpki-roots", +# "tokio-rustls", +# "webpki-roots", +#] +# If true, the allowed features must exactly match the enabled feature set. If +# this is set there is no point setting `deny` +#exact = true + +# Certain crates/versions that will be skipped when doing duplicate detection. +skip = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason why it can't be updated/removed" }, +] +# Similarly to `skip` allows you to skip certain crates during duplicate +# detection. Unlike skip, it also includes the entire tree of transitive +# dependencies starting at the specified crate, up to a certain depth, which is +# by default infinite. +skip-tree = [ + #"ansi_term@0.11.0", # will be skipped along with _all_ of its direct and transitive dependencies + #{ crate = "ansi_term@0.11.0", depth = 20 }, +] + +# This section is considered when running `cargo deny check sources`. +# More documentation about the 'sources' section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/sources/cfg.html +[sources] +# Lint level for what to happen when a crate from a crate registry that is not +# in the allow list is encountered +unknown-registry = "warn" +# Lint level for what to happen when a crate from a git repository that is not +# in the allow list is encountered +unknown-git = "warn" +# List of URLs for allowed crate registries. Defaults to the crates.io index +# if not specified. If it is specified but empty, no registries are allowed. +allow-registry = ["https://github.com/rust-lang/crates.io-index"] +# List of URLs for allowed Git repositories +allow-git = [] + +[sources.allow-org] +# github.com organizations to allow git sources for +github = ["OpenDevicePartnership"] +# gitlab.com organizations to allow git sources for +gitlab = [] +# bitbucket.org organizations to allow git sources for +bitbucket = [] diff --git a/supply-chain/README.md b/supply-chain/README.md new file mode 100644 index 000000000..12f8777b0 --- /dev/null +++ b/supply-chain/README.md @@ -0,0 +1,149 @@ +# Working with cargo vet + +## Introduction + +`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity. +It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust. +To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet) + +--- + +## Adding a new dependency + +When updating or adding a new dependency, we need to ensure it's audited before being merged into main. +For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository. +_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._ +Follow the process below to ensure compliance: + +### For Developers +1. **Respond to `cargo vet` failures**: + - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire + - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies + +2. **Engage with auditors**: + - Respond to any questions that the auditors might have regarding the need of any new dependencies + +3. **Rebase and verify**: + - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository + - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet` + ```bash + git fetch upstream + git rebase upstream/main + cargo vet + ``` + +4. **Update PR**: + - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR + - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase + ```bash + git push -f + ``` + +5. **Check PR status**: + - The existing PR comment from the previous failure will be updated with a success message once the check passes + +### For Auditors + +1. **Review the questionnaire**: + - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure + - Respond to the developer comment in case more information is needed + +2. **Audit new dependencies**: + - Inspect the `cargo vet` failures using your preferred method + - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked` + - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked` + - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally) + +3. **Follow `cargo vet` recommendations**: + - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies + +4. **Record audits**: + - Use `cargo vet certify` to add new audits to _audits.toml_ + - Verify all dependencies pass using `cargo vet` + +5. **Decide audit location**: + - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) + - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits + +6. **Communicate successful audit**: + - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass + +--- + +## Audit criteria +`cargo vet` comes pre-equipped with two built-in criteria but supports adding new criteria to suit our needs. +As defined [here](https://mozilla.github.io/cargo-vet/built-in-criteria.html), the default criteria are: + +- **safe-to-run** + This crate can be compiled, run, and tested on a local workstation or in + controlled automation without surprising consequences, such as: + * Reading or writing data from sensitive or unrelated parts of the filesystem. + * Installing software or reconfiguring the device. + * Connecting to untrusted network endpoints. + * Misuse of system resources (e.g. cryptocurrency mining). + +- **safe-to-deploy** + This crate will not introduce a serious security vulnerability to production + software exposed to untrusted input. + + Auditors are not required to perform a full logic review of the entire crate. + Rather, they must review enough to fully reason about the behavior of all unsafe + blocks and usage of powerful imports. For any reasonable usage of the crate in + real-world software, an attacker must not be able to manipulate the runtime + behavior of these sections in an exploitable or surprising way. + + Ideally, all unsafe code is fully sound, and ambient capabilities (e.g. + filesystem access) are hardened against manipulation and consistent with the + advertised behavior of the crate. However, some discretion is permitted. In such + cases, the nature of the discretion should be recorded in the `notes` field of + the audit record. + + For crates which generate deployed code (e.g. build dependencies or procedural + macros), reasonable usage of the crate should output code which meets the above + criteria. + + **Note: `safe-to-deploy` implies `safe-to-run`** + +--- + +## Conducting an audit + +When performing an audit for a new or updated dependency, auditors may consider the following criteria to ensure the safety, reliability, and suitability of the crate for use in our projects: + +- **Security**: + - Review the crate for known vulnerabilities or security advisories. + - Check for unsafe code usage and ensure it is justified and well-documented. + - Evaluate the crate’s history of security issues and responsiveness to reported problems. + +- **Maintenance and Activity**: + - Assess the frequency of updates and the responsiveness of maintainers to issues and pull requests. + - Prefer crates that are actively maintained and have a healthy contributor base. + +- **License Compliance**: + - Verify that the crate’s license is compatible with our project’s licensing requirements. + +- **Community Trust and Adoption**: + - Consider the crate’s adoption in the wider Rust ecosystem. + - Prefer crates that are widely used and trusted by the community. + +- **Functionality and Suitability**: + - Confirm that the crate provides the required functionality without unnecessary features or bloat. + - Evaluate whether the crate’s API is stable and unlikely to introduce breaking changes unexpectedly. + +- **Audit Trail**: + - Record the audit decision, including any concerns, mitigations, or recommendations for future updates. + - If exemptions are granted, document the justification and any follow-up actions required. + +--- + +## Tips for using `cargo vet`: + +- **Update _imports.lock_**: + - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project. + +- **Add exemptions**: + - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption ` to add the dependency to exemptions in _config.toml_ + - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions` + +- **Prune unnecessary entries**: + - Remove unnecessary exemptions and imports using `cargo vet prune` \ No newline at end of file diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml new file mode 100644 index 000000000..1c3d54760 --- /dev/null +++ b/supply-chain/audits.toml @@ -0,0 +1,38 @@ + +# cargo-vet audits file + +[[audits.autocfg]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.5.0" + +[[audits.darling_core]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.20.11" + +[[audits.defmt-rtt]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.0" +notes = "defmt-rtt is used for all our logging purposes. Version 1.0.0 merely stabilizes what was already available previously." + +[[audits.embassy-executor-timer-queue]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.0" + +[[audits.embassy-executor-timer-queue]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.0" + +[[audits.embassy-time-queue-utils]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.3.0" + +[[audits.static_cell]] +who = "jerrysxie " +criteria = "safe-to-run" +delta = "2.1.0 -> 2.1.1" diff --git a/supply-chain/config.toml b/supply-chain/config.toml new file mode 100644 index 000000000..501bd91d7 --- /dev/null +++ b/supply-chain/config.toml @@ -0,0 +1,226 @@ + +# cargo-vet config file + +[cargo-vet] +version = "0.10" + +[imports.OpenDevicePartnership] +url = "https://raw.githubusercontent.com/OpenDevicePartnership/rust-crate-audits/main/audits.toml" + +[imports.google] +url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" + +[imports.mozilla] +url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" + +[[exemptions.az]] +version = "1.2.1" +criteria = "safe-to-deploy" + +[[exemptions.bare-metal]] +version = "0.2.5" +criteria = "safe-to-deploy" + +[[exemptions.bitfield]] +version = "0.13.2" +criteria = "safe-to-deploy" + +[[exemptions.bitfield]] +version = "0.15.0" +criteria = "safe-to-deploy" + +[[exemptions.chrono]] +version = "0.4.40" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m]] +version = "0.7.7" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m-rt]] +version = "0.7.5" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m-rt-macros]] +version = "0.7.5" +criteria = "safe-to-deploy" + +[[exemptions.critical-section]] +version = "1.2.0" +criteria = "safe-to-deploy" + +[[exemptions.darling]] +version = "0.20.11" +criteria = "safe-to-run" + +[[exemptions.darling_macro]] +version = "0.20.11" +criteria = "safe-to-run" + +[[exemptions.defmt]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.defmt-macros]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.defmt-parser]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-embedded-hal]] +version = "0.5.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-executor]] +version = "0.9.0" +criteria = "safe-to-run" + +[[exemptions.embassy-executor-macros]] +version = "0.7.0" +criteria = "safe-to-run" + +[[exemptions.embassy-futures]] +version = "0.1.2" +criteria = "safe-to-deploy" + +[[exemptions.embassy-hal-internal]] +version = "0.3.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-sync]] +version = "0.7.2" +criteria = "safe-to-deploy" + +[[exemptions.embassy-time]] +version = "0.5.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-time-driver]] +version = "0.2.1" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal]] +version = "0.2.7" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal-async]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal-nb]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embedded-io]] +version = "0.6.1" +criteria = "safe-to-deploy" + +[[exemptions.embedded-io-async]] +version = "0.6.1" +criteria = "safe-to-deploy" + +[[exemptions.embedded-storage]] +version = "0.3.1" +criteria = "safe-to-deploy" + +[[exemptions.embedded-storage-async]] +version = "0.4.1" +criteria = "safe-to-deploy" + +[[exemptions.fixed]] +version = "1.29.0" +criteria = "safe-to-deploy" + +[[exemptions.futures-core]] +version = "0.3.31" +criteria = "safe-to-deploy" + +[[exemptions.futures-sink]] +version = "0.3.31" +criteria = "safe-to-deploy" + +[[exemptions.hash32]] +version = "0.3.1" +criteria = "safe-to-deploy" + +[[exemptions.heapless]] +version = "0.8.0" +criteria = "safe-to-deploy" + +[[exemptions.ident_case]] +version = "1.0.1" +criteria = "safe-to-run" + +[[exemptions.itertools]] +version = "0.11.0" +criteria = "safe-to-deploy" + +[[exemptions.log]] +version = "0.4.27" +criteria = "safe-to-deploy" + +[[exemptions.mimxrt600-fcb]] +version = "0.2.1" +criteria = "safe-to-deploy" + +[[exemptions.paste]] +version = "1.0.15" +criteria = "safe-to-deploy" + +[[exemptions.portable-atomic]] +version = "1.11.0" +criteria = "safe-to-run" + +[[exemptions.proc-macro-error-attr2]] +version = "2.0.0" +criteria = "safe-to-deploy" + +[[exemptions.proc-macro-error2]] +version = "2.0.1" +criteria = "safe-to-deploy" + +[[exemptions.rustc_version]] +version = "0.2.3" +criteria = "safe-to-deploy" + +[[exemptions.semver]] +version = "0.9.0" +criteria = "safe-to-deploy" + +[[exemptions.semver-parser]] +version = "0.7.0" +criteria = "safe-to-deploy" + +[[exemptions.static_cell]] +version = "2.1.0" +criteria = "safe-to-run" + +[[exemptions.syn]] +version = "2.0.100" +criteria = "safe-to-deploy" + +[[exemptions.thiserror]] +version = "2.0.12" +criteria = "safe-to-deploy" + +[[exemptions.thiserror-impl]] +version = "2.0.12" +criteria = "safe-to-deploy" + +[[exemptions.typenum]] +version = "1.18.0" +criteria = "safe-to-deploy" + +[[exemptions.vcell]] +version = "0.1.3" +criteria = "safe-to-deploy" + +[[exemptions.volatile-register]] +version = "0.2.2" +criteria = "safe-to-deploy" diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock new file mode 100644 index 000000000..3f541e59f --- /dev/null +++ b/supply-chain/imports.lock @@ -0,0 +1,472 @@ + +# cargo-vet imports lock + +[audits.OpenDevicePartnership.audits] + +[[audits.google.audits.autocfg]] +who = "Manish Goregaokar " +criteria = "safe-to-deploy" +version = "1.4.0" +notes = "Contains no unsafe" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bitflags]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.3.2" +notes = """ +Security review of earlier versions of the crate can be found at +(Google-internal, sorry): go/image-crate-chromium-security-review + +The crate exposes a function marked as `unsafe`, but doesn't use any +`unsafe` blocks (except for tests of the single `unsafe` function). I +think this justifies marking this crate as `ub-risk-1`. + +Additional review comments can be found at https://crrev.com/c/4723145/31 +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bytemuck]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.16.3" +notes = """ +Review notes from the original audit (of 1.14.3) may be found in +https://crrev.com/c/5362675. Note that this audit has initially missed UB risk +that was fixed in 1.16.2 - see https://github.com/Lokathor/bytemuck/pull/258. +Because of this, the original audit has been edited to certify version `1.16.3` +instead (see also https://crrev.com/c/5771867). +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bytemuck]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.16.3 -> 1.17.1" +notes = "Unsafe review comments can be found in https://crrev.com/c/5813463" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bytemuck]] +who = "Adrian Taylor " +criteria = "safe-to-deploy" +delta = "1.17.1 -> 1.18.0" +notes = "No code changes - just altering feature flag arrangements" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bytemuck]] +who = "Adrian Taylor " +criteria = "safe-to-deploy" +delta = "1.18.0 -> 1.19.0" +notes = "No code changes - just comment changes and adding the track_caller attribute." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bytemuck]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.19.0 -> 1.20.0" +notes = "`unsafe` review can be found at https://crrev.com/c/6096767" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bytemuck]] +who = "Adrian Taylor " +criteria = "safe-to-deploy" +delta = "1.20.0 -> 1.21.0" +notes = "Unsafe review at https://chromium-review.googlesource.com/c/chromium/src/+/6111154/" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bytemuck]] +who = "Daniel Cheng " +criteria = "safe-to-deploy" +delta = "1.21.0 -> 1.22.0" +notes = """ +This adds new instances of unsafe, but the uses are justified: +- BoxBytes is essentially a Box<[u8], which is Send + Sync, so also marking BoxBytes as Send + Sync is justified. +- core::num::Saturating meets the criteria for Zeroable + Pod, so marking it as such is justified. + +See https://crrev.com/c/6321863 for more audit notes. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.byteorder]] +who = "danakj " +criteria = "safe-to-deploy" +version = "1.5.0" +notes = "Unsafe review in https://crrev.com/c/5838022" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.cfg-if]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +version = "1.0.0" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.either]] +who = "Manish Goregaokar " +criteria = "safe-to-deploy" +version = "1.13.0" +notes = "Unsafe code pertaining to wrapping Pin APIs. Mostly passes invariants down." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.either]] +who = "Daniel Cheng " +criteria = "safe-to-deploy" +delta = "1.13.0 -> 1.14.0" +notes = """ +Inheriting ub-risk-1 from the baseline review of 1.13.0. While the delta has some diffs in unsafe code, they are either: +- migrating code to use helper macros +- migrating match patterns to take advantage of default bindings mode from RFC 2005 +Either way, the result is code that does exactly the same thing and does not change the risk of UB. + +See https://crrev.com/c/6323164 for more audit details. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.either]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.14.0 -> 1.15.0" +notes = "The delta in `lib.rs` only tweaks doc comments and `#[cfg(feature = \"std\")]`." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +version = "1.0.0" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 0.1.3" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 1.1.0" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.num-traits]] +who = "Manish Goregaokar " +criteria = "safe-to-deploy" +version = "0.2.19" +notes = "Contains a single line of float-to-int unsafe with decent safety comments" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.0.78" +notes = """ +Grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits +(except for a benign \"fs\" hit in a doc comment) + +Notes from the `unsafe` review can be found in https://crrev.com/c/5385745. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Adrian Taylor " +criteria = "safe-to-deploy" +delta = "1.0.78 -> 1.0.79" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Adrian Taylor " +criteria = "safe-to-deploy" +delta = "1.0.79 -> 1.0.80" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Dustin J. Mitchell " +criteria = "safe-to-deploy" +delta = "1.0.80 -> 1.0.81" +notes = "Comment changes only" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "danakj " +criteria = "safe-to-deploy" +delta = "1.0.81 -> 1.0.82" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Dustin J. Mitchell " +criteria = "safe-to-deploy" +delta = "1.0.82 -> 1.0.83" +notes = "Substantive change is replacing String with Box, saving memory." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.0.83 -> 1.0.84" +notes = "Only doc comment changes in `src/lib.rs`." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "danakj@chromium.org" +criteria = "safe-to-deploy" +delta = "1.0.84 -> 1.0.85" +notes = "Test-only changes." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.0.85 -> 1.0.86" +notes = """ +Comment-only changes in `build.rs`. +Reordering of `Cargo.toml` entries. +Just bumping up the version number in `lib.rs`. +Config-related changes in `test_size.rs`. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "danakj " +criteria = "safe-to-deploy" +delta = "1.0.86 -> 1.0.87" +notes = "No new unsafe interactions." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Liza Burakova Date: Fri, 7 Nov 2025 10:57:17 -0800 Subject: Vet dependencies Signed-off-by: Felipe Balbi --- supply-chain/audits.toml | 90 ++++++++++++++++++++++++++++++++++++++++++++++++ supply-chain/config.toml | 28 --------------- 2 files changed, 90 insertions(+), 28 deletions(-) diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml index 1c3d54760..60ebedf9b 100644 --- a/supply-chain/audits.toml +++ b/supply-chain/audits.toml @@ -6,17 +6,57 @@ who = "Felipe Balbi " criteria = "safe-to-deploy" version = "1.5.0" +[[audits.cfg-if]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.4" + +[[audits.darling]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.20.11" + [[audits.darling_core]] who = "Felipe Balbi " criteria = "safe-to-deploy" version = "0.20.11" +[[audits.darling_macro]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.20.11" + [[audits.defmt-rtt]] who = "Felipe Balbi " criteria = "safe-to-deploy" version = "1.0.0" notes = "defmt-rtt is used for all our logging purposes. Version 1.0.0 merely stabilizes what was already available previously." +[[audits.defmt-rtt]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 1.1.0" + +[[audits.document-features]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.2.12" + +[[audits.document-features]] +who = "Felipe Balbi " +criteria = "safe-to-run" +version = "0.2.12" + +[[audits.embassy-executor]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.9.1" + +[[audits.embassy-executor-macros]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.7.0" + [[audits.embassy-executor-timer-queue]] who = "Felipe Balbi " criteria = "safe-to-deploy" @@ -32,7 +72,57 @@ who = "Felipe Balbi " criteria = "safe-to-deploy" version = "0.3.0" +[[audits.ident_case]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.1" + +[[audits.litrs]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.0" + +[[audits.panic-probe]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.0" + +[[audits.proc-macro2]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.103" + +[[audits.quote]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.42" + +[[audits.stable_deref_trait]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.2.1" + [[audits.static_cell]] who = "jerrysxie " criteria = "safe-to-run" delta = "2.1.0 -> 2.1.1" + +[[audits.syn]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +delta = "2.0.100 -> 2.0.109" + +[[audits.thiserror]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "2.0.17" + +[[audits.thiserror-impl]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "2.0.17" + +[[audits.unicode-ident]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.22" diff --git a/supply-chain/config.toml b/supply-chain/config.toml index 501bd91d7..5927b0b61 100644 --- a/supply-chain/config.toml +++ b/supply-chain/config.toml @@ -49,14 +49,6 @@ criteria = "safe-to-deploy" version = "1.2.0" criteria = "safe-to-deploy" -[[exemptions.darling]] -version = "0.20.11" -criteria = "safe-to-run" - -[[exemptions.darling_macro]] -version = "0.20.11" -criteria = "safe-to-run" - [[exemptions.defmt]] version = "1.0.1" criteria = "safe-to-deploy" @@ -73,14 +65,6 @@ criteria = "safe-to-deploy" version = "0.5.0" criteria = "safe-to-deploy" -[[exemptions.embassy-executor]] -version = "0.9.0" -criteria = "safe-to-run" - -[[exemptions.embassy-executor-macros]] -version = "0.7.0" -criteria = "safe-to-run" - [[exemptions.embassy-futures]] version = "0.1.2" criteria = "safe-to-deploy" @@ -153,10 +137,6 @@ criteria = "safe-to-deploy" version = "0.8.0" criteria = "safe-to-deploy" -[[exemptions.ident_case]] -version = "1.0.1" -criteria = "safe-to-run" - [[exemptions.itertools]] version = "0.11.0" criteria = "safe-to-deploy" @@ -205,14 +185,6 @@ criteria = "safe-to-run" version = "2.0.100" criteria = "safe-to-deploy" -[[exemptions.thiserror]] -version = "2.0.12" -criteria = "safe-to-deploy" - -[[exemptions.thiserror-impl]] -version = "2.0.12" -criteria = "safe-to-deploy" - [[exemptions.typenum]] version = "1.18.0" criteria = "safe-to-deploy" -- cgit From a6852eb433e4b3084d04966dc6ab8839b5f9c91f Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 7 Nov 2025 19:01:00 +0000 Subject: chore(deps): bump peter-evans/create-or-update-comment from 4 to 5 Bumps [peter-evans/create-or-update-comment](https://github.com/peter-evans/create-or-update-comment) from 4 to 5. - [Release notes](https://github.com/peter-evans/create-or-update-comment/releases) - [Commits](https://github.com/peter-evans/create-or-update-comment/compare/v4...v5) --- updated-dependencies: - dependency-name: peter-evans/create-or-update-comment dependency-version: '5' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/cargo-vet-pr-comment.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml index dd8ef37a6..4b8f0f38d 100644 --- a/.github/workflows/cargo-vet-pr-comment.yml +++ b/.github/workflows/cargo-vet-pr-comment.yml @@ -63,7 +63,7 @@ jobs: if: github.event.workflow_run.conclusion == 'failure' steps: - name: 'Comment on PR - Failure' - uses: peter-evans/create-or-update-comment@v4 + uses: peter-evans/create-or-update-comment@v5 with: comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} @@ -120,7 +120,7 @@ jobs: # Only update the comment if it exists # This is to avoid creating a new comment if the cargo-vet job has never failed before if: ${{ needs.find-pr-comment.outputs.comment-id }} - uses: peter-evans/create-or-update-comment@v4 + uses: peter-evans/create-or-update-comment@v5 with: comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} -- cgit From ebed762527825f1f2f7407ead3cd8b734e1c812a Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 7 Nov 2025 19:01:04 +0000 Subject: chore(deps): bump actions/upload-artifact from 4 to 5 Bumps [actions/upload-artifact](https://github.com/actions/upload-artifact) from 4 to 5. - [Release notes](https://github.com/actions/upload-artifact/releases) - [Commits](https://github.com/actions/upload-artifact/compare/v4...v5) --- updated-dependencies: - dependency-name: actions/upload-artifact dependency-version: '5' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/cargo-vet.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cargo-vet.yml b/.github/workflows/cargo-vet.yml index 864c138e9..f9cbf93dc 100644 --- a/.github/workflows/cargo-vet.yml +++ b/.github/workflows/cargo-vet.yml @@ -44,7 +44,7 @@ jobs: run: | mkdir -p ./pr echo ${{ github.event.number }} > ./pr/NR - - uses: actions/upload-artifact@v4 + - uses: actions/upload-artifact@v5 # Need to upload the artifact in both success and failure cases so comment can be updated in either case if: ${{ failure() }} || ${{ success() }} with: -- cgit From 024af538ff172cfec1904813ef879350b9540fbc Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 7 Nov 2025 19:01:06 +0000 Subject: chore(deps): bump peter-evans/find-comment from 3 to 4 Bumps [peter-evans/find-comment](https://github.com/peter-evans/find-comment) from 3 to 4. - [Release notes](https://github.com/peter-evans/find-comment/releases) - [Commits](https://github.com/peter-evans/find-comment/compare/v3...v4) --- updated-dependencies: - dependency-name: peter-evans/find-comment dependency-version: '4' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/cargo-vet-pr-comment.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml index dd8ef37a6..7586fcac6 100644 --- a/.github/workflows/cargo-vet-pr-comment.yml +++ b/.github/workflows/cargo-vet-pr-comment.yml @@ -44,7 +44,7 @@ jobs: - name: 'Find existing comment' id: find-comment - uses: peter-evans/find-comment@v3 + uses: peter-evans/find-comment@v4 with: issue-number: ${{ steps.get-pr-number.outputs.pr_number }} comment-author: 'github-actions[bot]' -- cgit From 49f0f4d877b670056313de4045d8ccec60280a9a Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 7 Nov 2025 19:01:06 +0000 Subject: chore(deps): bump actions/checkout from 4 to 5 Bumps [actions/checkout](https://github.com/actions/checkout) from 4 to 5. - [Release notes](https://github.com/actions/checkout/releases) - [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md) - [Commits](https://github.com/actions/checkout/compare/v4...v5) --- updated-dependencies: - dependency-name: actions/checkout dependency-version: '5' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/cargo-vet.yml | 2 +- .github/workflows/check.yml | 14 +++++++------- .github/workflows/nostd.yml | 2 +- .github/workflows/rolling.yml | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/.github/workflows/cargo-vet.yml b/.github/workflows/cargo-vet.yml index 864c138e9..c25ae3671 100644 --- a/.github/workflows/cargo-vet.yml +++ b/.github/workflows/cargo-vet.yml @@ -19,7 +19,7 @@ jobs: CARGO_VET_VERSION: 0.10.1 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index 1a09a1492..5d4271145 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -37,7 +37,7 @@ jobs: workdir: [ ".", "examples/rt633", "examples/rt685s-evk",] steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true @@ -66,7 +66,7 @@ jobs: workdir: ["examples"] steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true @@ -86,7 +86,7 @@ jobs: # runs-on: ubuntu-latest # name: semver # steps: - # - uses: actions/checkout@v4 + # - uses: actions/checkout@v5 # with: # submodules: true # - name: Install stable @@ -104,7 +104,7 @@ jobs: name: nightly / doc steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true @@ -127,7 +127,7 @@ jobs: fail-fast: false steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true @@ -150,7 +150,7 @@ jobs: name: ubuntu / stable / deny steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true @@ -191,7 +191,7 @@ jobs: name: ubuntu / ${{ matrix.msrv }} steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml index 92460bd0f..fbada0516 100644 --- a/.github/workflows/nostd.yml +++ b/.github/workflows/nostd.yml @@ -25,7 +25,7 @@ jobs: target: [thumbv8m.main-none-eabihf] steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml index f572954f9..4c9e9718a 100644 --- a/.github/workflows/rolling.yml +++ b/.github/workflows/rolling.yml @@ -20,7 +20,7 @@ jobs: strategy: fail-fast: false steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true - name: Install stable @@ -55,7 +55,7 @@ jobs: # requires 1.85 name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }}) steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 with: submodules: true - name: Install ${{ matrix.msrv }} -- cgit From 367729d61f401a58beecf5bf34a4260b5e43e3d8 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 7 Nov 2025 19:01:09 +0000 Subject: chore(deps): bump actions/github-script from 7 to 8 Bumps [actions/github-script](https://github.com/actions/github-script) from 7 to 8. - [Release notes](https://github.com/actions/github-script/releases) - [Commits](https://github.com/actions/github-script/compare/v7...v8) --- updated-dependencies: - dependency-name: actions/github-script dependency-version: '8' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/cargo-vet-pr-comment.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml index dd8ef37a6..68e16b2f3 100644 --- a/.github/workflows/cargo-vet-pr-comment.yml +++ b/.github/workflows/cargo-vet-pr-comment.yml @@ -99,7 +99,7 @@ jobs: edit-mode: replace - name: 'Label PR' - uses: actions/github-script@v7 + uses: actions/github-script@v8 with: script: | github.rest.issues.addLabels({ -- cgit From 144c659fe278959736a1d391f1582dbbfc651646 Mon Sep 17 00:00:00 2001 From: James Munns Date: Tue, 11 Nov 2025 20:27:14 +0100 Subject: Start implementing clocks This starts with the FIRC/FRO180M, though leaves it mostly hardcoded. --- src/clocks.rs | 379 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 379 insertions(+) diff --git a/src/clocks.rs b/src/clocks.rs index 65a17cef6..74e0daeeb 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -1,5 +1,7 @@ //! Clock control helpers (no magic numbers, PAC field access only). //! Provides reusable gate abstractions for peripherals used by the examples. +use mcxa_pac::scg0::firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}; + use crate::pac; /// Trait describing an AHB clock gate that can be toggled through MRCC. @@ -132,3 +134,380 @@ pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0()); mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); } + +// ============================================== + +/// This type represents a divider in the range 1..=256. +/// +/// At a hardware level, this is an 8-bit register from 0..=255, +/// which adds one. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub struct Div8(pub(super) u8); + +impl Div8 { + /// Store a "raw" divisor value that will divide the source by + /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source + /// by 1, and `Div8::from_raw(255)` will divide the source by + /// 256. + pub const fn from_raw(n: u8) -> Self { + Self(n) + } + + /// Store a specific divisor value that will divide the source + /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source + /// by 1, and `Div8::from_divisor(256)` will divide the source + /// by 256. + /// + /// Will return `None` if `n` is not in the range `1..=256`. + /// Consider [`Self::from_raw`] for an infallible version. + pub const fn from_divisor(n: u16) -> Option { + let Some(n) = n.checked_sub(1) else { + return None; + }; + if n > (u8::MAX as u16) { + return None; + } + Some(Self(n as u8)) + } + + /// Convert into "raw" bits form + #[inline(always)] + pub const fn into_bits(self) -> u8 { + self.0 + } + + /// Convert into "divisor" form, as a u32 for convenient frequency math + #[inline(always)] + pub const fn into_divisor(self) -> u32 { + self.0 as u32 + 1 + } +} + +#[derive(Debug, Clone)] +pub struct Clock { + pub frequency: u32, + pub power: PoweredClock, +} + +#[derive(Debug, Clone, Copy)] +pub enum PoweredClock { + HighPowerOnly, + AlwaysEnabled, +} + +/// ```text +/// ┌─────────────────────────────────────────────────────────┐ +/// │ │ +/// │ ┌───────────┐ clk_out ┌─────────┐ │ +/// XTAL ──────┼──▷│ System │───────────▷│ │ clk_in │ +/// │ │ OSC │ clkout_byp │ MUX │──────────────────┼──────▷ +/// EXTAL ──────┼──▷│ │───────────▷│ │ │ +/// │ └───────────┘ └─────────┘ │ +/// │ │ +/// │ ┌───────────┐ fro_hf_root ┌────┐ fro_hf │ +/// │ │ FRO180 ├───────┬─────▷│ CG │─────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_45m │ +/// │ │ │ └─────▷│ CG │─────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ ┌───────────┐ fro_12m_root ┌────┐ fro_12m │ +/// │ │ FRO12M │────────┬─────▷│ CG │────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_1m │ +/// │ │ │ └─────▷│1/12│────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ │ +/// │ ┌──────────┐ │ +/// │ │000 │ │ +/// │ clk_in │ │ │ +/// │ ───────────────▷│001 │ │ +/// │ fro_12m │ │ │ +/// │ ───────────────▷│010 │ │ +/// │ fro_hf_root │ │ │ +/// │ ───────────────▷│011 │ main_clk │ +/// │ │ │───────────────────────────┼──────▷ +/// clk_16k ──────┼─────────────────▷│100 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│101 │ │ +/// │ pll1_clk │ │ │ +/// │ ───────────────▷│110 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│111 │ │ +/// │ └──────────┘ │ +/// │ ▲ │ +/// │ │ │ +/// │ SCG SCS │ +/// │ SCG-Lite │ +/// └─────────────────────────────────────────────────────────┘ +/// +/// +/// clk_in ┌─────┐ +/// ───────────────▷│00 │ +/// clk_45m │ │ +/// ───────────────▷│01 │ ┌───────────┐ pll1_clk +/// none │ │─────▷│ SPLL │───────────────▷ +/// ───────────────▷│10 │ └───────────┘ +/// fro_12m │ │ +/// ───────────────▷│11 │ +/// └─────┘ +/// ``` +pub struct ClocksConfig { + // FIRC, FRO180, 45/60/90/180M clock source + pub firc: Option, + pub sirc: Option, +} + +// FIRC/FRO180M + +/// ```text +/// ┌───────────┐ fro_hf_root ┌────┐ fro_hf +/// │ FRO180M ├───────┬─────▷│GATE│──────────▷ +/// │ │ │ ├────┤ clk_45m +/// │ │ └─────▷│GATE│──────────▷ +/// └───────────┘ └────┘ +/// ``` +pub struct FircConfig { + pub frequency: FircFreqSel, + pub power: PoweredClock, + /// Is the "fro_hf" gated clock enabled? + pub fro_hf_enabled: bool, + /// Is the "clk_45m" gated clock enabled? + pub clk_45m_enabled: bool, + /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`! + pub fro_hf_div: Option, +} + +pub enum FircFreqSel { + Mhz45, + Mhz60, + Mhz90, + Mhz180, +} + +// SIRC/FRO12M + +/// ```text +/// ┌───────────┐ fro_12m_root ┌────┐ fro_12m +/// │ FRO12M │────────┬─────▷│ CG │──────────▷ +/// │ │ │ ├────┤ clk_1m +/// │ │ └─────▷│1/12│──────────▷ +/// └───────────┘ └────┘ +/// ``` +pub struct SircConfig { + pub power: PoweredClock, + // peripheral output, aka sirc_12mhz + pub fro_12m_enabled: bool, + /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`! + pub fro_lf_div: Option, +} + +#[derive(Default, Debug, Clone)] +pub struct Clocks { + pub clk_in: Option, + + // FRO180M stuff + // + pub fro_hf_root: Option, + pub fro_hf: Option, + pub clk_45m: Option, + pub fro_hf_div: Option, + // + // End FRO180M + + // FRO12M stuff + pub fro_12m_root: Option, + pub fro_12m: Option, + pub clk_1m: Option, + pub fro_lf_div: Option, + // + // End FRO12M stuff + pub main_clk: Option, + pub pll1_clk: Option, +} + +static CLOCKS: critical_section::Mutex> = critical_section::Mutex::new(None); + +pub enum ClockError { + AlreadyInitialized, + BadConfig { clock: &'static str, reason: &'static str }, +} + +struct ClockOperator<'a> { + clocks: &'a mut Clocks, + config: &'a ClocksConfig, + + _mrcc0: pac::Mrcc0, + scg0: pac::Scg0, + syscon: pac::Syscon, +} + +impl ClockOperator<'_> { + fn configure_firc_clocks(&mut self) -> Result<(), ClockError> { + const HARDCODED_ERR: Result<(), ClockError> = Err(ClockError::BadConfig { + clock: "firc", + reason: "For now, FIRC must be enabled and in default state!", + }); + + // Did the user give us a FIRC config? + let Some(firc) = self.config.firc.as_ref() else { + return HARDCODED_ERR; + }; + // Is the FIRC set to 45MHz (should be reset default) + if !matches!(firc.frequency, FircFreqSel::Mhz45) { + return HARDCODED_ERR; + } + let base_freq = 45_000_000; + + // Is the FIRC as expected? + let mut firc_ok = true; + + // Is the hardware currently set to the default 45MHz? + // + // NOTE: the SVD currently has the wrong(?) values for these: + // 45 -> 48 + // 60 -> 64 + // 90 -> 96 + // 180 -> 192 + // Probably correct-ish, but for a different trim value? + firc_ok &= self.scg0.firccfg().read().freq_sel().is_firc_48mhz_192s(); + + // Check some values in the CSR + let csr = self.scg0.firccsr().read(); + // Is it enabled? + firc_ok &= csr.fircen().is_enabled(); + // Is it accurate? + firc_ok &= csr.fircacc().is_enabled_and_valid(); + // Is there no error? + firc_ok &= csr.fircerr().is_error_not_detected(); + // Is the FIRC the system clock? + firc_ok &= csr.fircsel().is_firc(); + // Is it valid? + firc_ok &= csr.fircvld().is_enabled_and_valid(); + + // Are we happy with the current (hardcoded) state? + if !firc_ok { + return HARDCODED_ERR; + } + + // Note that the fro_hf_root is active + self.clocks.fro_hf_root = Some(Clock { + frequency: base_freq, + power: firc.power, + }); + + // Okay! Now we're past that, let's enable all the downstream clocks. + let FircConfig { + frequency: _, + power, + fro_hf_enabled, + clk_45m_enabled, + fro_hf_div, + } = firc; + + // When is the FRO enabled? + let pow_set = match power { + PoweredClock::HighPowerOnly => Fircsten::DisabledInStopModes, + PoweredClock::AlwaysEnabled => Fircsten::EnabledInStopModes, + }; + + // Do we enable the `fro_hf` output? + let fro_hf_set = if *fro_hf_enabled { + self.clocks.fro_hf = Some(Clock { + frequency: base_freq, + power: *power, + }); + FircFclkPeriphEn::Enabled + } else { + FircFclkPeriphEn::Disabled + }; + + // Do we enable the `clk_45m` output? + let clk_45m_set = if *clk_45m_enabled { + self.clocks.clk_45m = Some(Clock { + frequency: 45_000_000, + power: *power, + }); + FircSclkPeriphEn::Enabled + } else { + FircSclkPeriphEn::Disabled + }; + + self.scg0.firccsr().modify(|_r, w| { + w.fircsten().variant(pow_set); + w.firc_fclk_periph_en().variant(fro_hf_set); + w.firc_sclk_periph_en().variant(clk_45m_set); + w + }); + + // Do we enable the `fro_hf_div` output? + if let Some(d) = fro_hf_div.as_ref() { + // We need `fro_hf` to be enabled + if !*fro_hf_enabled { + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "fro_hf not enabled", + }); + } + + // Halt and reset the div + self.syscon.frohfdiv().write(|w| { + w.halt().halt(); + w.reset().asserted(); + w + }); + // Then change the div, unhalt it, and reset it + self.syscon.frohfdiv().write(|w| { + unsafe { + w.div().bits(d.into_bits()); + } + w.halt().run(); + w.reset().released(); + w + }); + + // Wait for clock to stabilize + while self.syscon.frohfdiv().read().unstab().is_ongoing() {} + + // Store off the clock info + self.clocks.fro_hf_div = Some(Clock { + frequency: base_freq / d.into_divisor(), + power: *power, + }); + } + + Ok(()) + } +} + +pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { + critical_section::with(|cs| { + if CLOCKS.borrow(cs).is_some() { + Err(ClockError::AlreadyInitialized) + } else { + Ok(()) + } + })?; + + let mut clocks = Clocks::default(); + let mut operator = ClockOperator { + clocks: &mut clocks, + config: &settings, + + _mrcc0: unsafe { pac::Mrcc0::steal() }, + scg0: unsafe { pac::Scg0::steal() }, + syscon: unsafe { pac::Syscon::steal() }, + }; + + operator.configure_firc_clocks()?; + // TODO, SIRC, and everything downstream + + Ok(()) +} + +/// Obtain the full clocks structure, calling the given closure in a critical section +/// +/// NOTE: Clocks implements `Clone`, +pub fn with_clocks R>(f: F) -> Option { + critical_section::with(|cs| { + let c = CLOCKS.borrow(cs).as_ref()?; + Some(f(c)) + }) +} -- cgit From 1ec472aa864d8add5dd14246324d671217fab304 Mon Sep 17 00:00:00 2001 From: James Munns Date: Wed, 12 Nov 2025 17:00:40 +0100 Subject: add frolf support --- src/clocks.rs | 106 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 103 insertions(+), 3 deletions(-) diff --git a/src/clocks.rs b/src/clocks.rs index 74e0daeeb..a00b3e4c5 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -1,6 +1,9 @@ //! Clock control helpers (no magic numbers, PAC field access only). //! Provides reusable gate abstractions for peripherals used by the examples. -use mcxa_pac::scg0::firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}; +use mcxa_pac::scg0::{ + firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}, + sirccsr::{SircClkPeriphEn, Sircsten}, +}; use crate::pac; @@ -249,10 +252,12 @@ pub enum PoweredClock { /// ───────────────▷│11 │ /// └─────┘ /// ``` +#[non_exhaustive] pub struct ClocksConfig { // FIRC, FRO180, 45/60/90/180M clock source pub firc: Option, - pub sirc: Option, + // NOTE: I don't think we *can* disable the SIRC? + pub sirc: SircConfig, } // FIRC/FRO180M @@ -264,6 +269,7 @@ pub struct ClocksConfig { /// │ │ └─────▷│GATE│──────────▷ /// └───────────┘ └────┘ /// ``` +#[non_exhaustive] pub struct FircConfig { pub frequency: FircFreqSel, pub power: PoweredClock, @@ -291,6 +297,7 @@ pub enum FircFreqSel { /// │ │ └─────▷│1/12│──────────▷ /// └───────────┘ └────┘ /// ``` +#[non_exhaustive] pub struct SircConfig { pub power: PoweredClock, // peripheral output, aka sirc_12mhz @@ -300,6 +307,7 @@ pub struct SircConfig { } #[derive(Default, Debug, Clone)] +#[non_exhaustive] pub struct Clocks { pub clk_in: Option, @@ -325,6 +333,7 @@ pub struct Clocks { static CLOCKS: critical_section::Mutex> = critical_section::Mutex::new(None); +#[non_exhaustive] pub enum ClockError { AlreadyInitialized, BadConfig { clock: &'static str, reason: &'static str }, @@ -475,6 +484,96 @@ impl ClockOperator<'_> { Ok(()) } + + fn configure_sirc_clocks(&mut self) -> Result<(), ClockError> { + let SircConfig { + power, + fro_12m_enabled, + fro_lf_div, + } = &self.config.sirc; + let base_freq = 12_000_000; + + // Allow writes + self.scg0.sirccsr().modify(|_r, w| w.lk().write_enabled()); + self.clocks.fro_12m_root = Some(Clock { + frequency: base_freq, + power: *power, + }); + + let deep = match power { + PoweredClock::HighPowerOnly => Sircsten::Disabled, + PoweredClock::AlwaysEnabled => Sircsten::Enabled, + }; + let pclk = if *fro_12m_enabled { + self.clocks.fro_12m = Some(Clock { + frequency: base_freq, + power: *power, + }); + self.clocks.clk_1m = Some(Clock { + frequency: base_freq / 12, + power: *power, + }); + SircClkPeriphEn::Enabled + } else { + SircClkPeriphEn::Disabled + }; + + // Set sleep/peripheral usage + self.scg0.sirccsr().modify(|_r, w| { + w.sircsten().variant(deep); + w.sirc_clk_periph_en().variant(pclk); + w + }); + + while self.scg0.sirccsr().read().sircvld().is_disabled_or_not_valid() {} + if self.scg0.sirccsr().read().sircerr().is_error_detected() { + return Err(ClockError::BadConfig { + clock: "sirc", + reason: "error set", + }); + } + + // reset lock + self.scg0.sirccsr().modify(|_r, w| w.lk().write_disabled()); + + // Do we enable the `fro_lf_div` output? + if let Some(d) = fro_lf_div.as_ref() { + // We need `fro_lf` to be enabled + if !*fro_12m_enabled { + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "fro_12m not enabled", + }); + } + + // Halt and reset the div + self.syscon.frolfdiv().write(|w| { + w.halt().halt(); + w.reset().asserted(); + w + }); + // Then change the div, unhalt it, and reset it + self.syscon.frolfdiv().write(|w| { + unsafe { + w.div().bits(d.into_bits()); + } + w.halt().run(); + w.reset().released(); + w + }); + + // Wait for clock to stabilize + while self.syscon.frolfdiv().read().unstab().is_ongoing() {} + + // Store off the clock info + self.clocks.fro_lf_div = Some(Clock { + frequency: base_freq / d.into_divisor(), + power: *power, + }); + } + + todo!() + } } pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { @@ -497,7 +596,8 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { }; operator.configure_firc_clocks()?; - // TODO, SIRC, and everything downstream + operator.configure_sirc_clocks()?; + // TODO, everything downstream Ok(()) } -- cgit From 110a5eb4e58ecee5bc45bd47c3366ea241587e1b Mon Sep 17 00:00:00 2001 From: James Munns Date: Wed, 12 Nov 2025 17:16:19 +0100 Subject: Remove example feats, get examples building No CI, but this can be checked with `cargo check --all --examples`, which now succeeds. --- Cargo.toml | 13 +------------ examples/adc_interrupt.rs | 8 ++++---- examples/adc_polling.rs | 8 ++++---- examples/common/mod.rs | 10 +++++----- examples/lpuart_buffered.rs | 2 +- examples/ostimer_race_test.rs | 2 +- 6 files changed, 16 insertions(+), 27 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 8ec547494..b4d82bcec 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -36,6 +36,7 @@ embedded-io-async = { version = "0.6.1" } nb = "1.1.0" [dev-dependencies] +defmt = "1.0" defmt-rtt = "1.0" panic-probe = { version = "1.0", features = ["print-defmt"] } @@ -52,51 +53,39 @@ unstable-pac = [] [[example]] name = "hello" -required-features = ["lpuart2"] [[example]] name = "blink" -required-features = ["gpio", "ostimer0"] [[example]] name = "uart_interrupt" -required-features = ["lpuart2", "ostimer0"] [[example]] name = "ostimer_alarm" -required-features = ["lpuart2", "ostimer0"] [[example]] name = "ostimer_async" -required-features = ["lpuart2", "ostimer0"] [[example]] name = "ostimer_counter" -required-features = ["lpuart2", "ostimer0"] [[example]] name = "ostimer_race_test" -required-features = ["lpuart2", "ostimer0"] [[example]] name = "lpuart_polling" -required-features = ["lpuart2", "ostimer0"] [[example]] name = "lpuart_buffered" -required-features = ["lpuart2", "ostimer0"] [[example]] name = "rtc_alarm" -required-features = ["lpuart2", "rtc0"] [[example]] name = "adc_polling" -required-features = ["adc1", "lpuart2"] [[example]] name = "adc_interrupt" -required-features = ["adc1", "lpuart2"] [profile.release] debug = 2 diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs index f0df3196c..dc82cfd30 100644 --- a/examples/adc_interrupt.rs +++ b/examples/adc_interrupt.rs @@ -3,11 +3,11 @@ use embassy_executor::Spawner; use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; -use hal::pac::adc1::cfg::{Pwrsel, Refsel}; -use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::CalAvgs; -use hal::pac::adc1::tctrl::Tcmd; use hal::uart; +use mcxa_pac::adc1::cfg::{Pwrsel, Refsel}; +use mcxa_pac::adc1::cmdl1::{Adch, Mode}; +use mcxa_pac::adc1::ctrl::CalAvgs; +use mcxa_pac::adc1::tctrl::Tcmd; use {cortex_m, embassy_mcxa276 as hal}; mod common; diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs index 561500d2d..4b5f9422d 100644 --- a/examples/adc_polling.rs +++ b/examples/adc_polling.rs @@ -4,11 +4,11 @@ use embassy_executor::Spawner; use embassy_mcxa276 as hal; use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; -use hal::pac::adc1::cfg::{Pwrsel, Refsel}; -use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::CalAvgs; -use hal::pac::adc1::tctrl::Tcmd; use hal::uart; +use mcxa_pac::adc1::cfg::{Pwrsel, Refsel}; +use mcxa_pac::adc1::cmdl1::{Adch, Mode}; +use mcxa_pac::adc1::ctrl::CalAvgs; +use mcxa_pac::adc1::tctrl::Tcmd; mod common; diff --git a/examples/common/mod.rs b/examples/common/mod.rs index 7ada4c456..8c52c8e86 100644 --- a/examples/common/mod.rs +++ b/examples/common/mod.rs @@ -1,13 +1,13 @@ //! Shared board-specific helpers for the FRDM-MCXA276 examples. //! These live with the examples so the HAL stays generic. -use embassy_mcxa276 as hal; use hal::{clocks, pins, reset}; +use {embassy_mcxa276 as hal, panic_probe as _}; /// Initialize clocks and pin muxing for UART2 debug console. /// Safe to call multiple times; writes are idempotent for our use. #[allow(dead_code)] -pub unsafe fn init_uart2(p: &hal::pac::Peripherals) { +pub unsafe fn init_uart2(p: &mcxa_pac::Peripherals) { clocks::ensure_frolf_running(p); clocks::enable_uart2_port2(p); reset::release_reset_port2(p); @@ -18,7 +18,7 @@ pub unsafe fn init_uart2(p: &hal::pac::Peripherals) { /// Initialize clocks for the LED GPIO/PORT used by the blink example. #[allow(dead_code)] -pub unsafe fn init_led(p: &hal::pac::Peripherals) { +pub unsafe fn init_led(p: &mcxa_pac::Peripherals) { clocks::enable_led_port(p); reset::release_reset_gpio3(p); reset::release_reset_port3(p); @@ -26,7 +26,7 @@ pub unsafe fn init_led(p: &hal::pac::Peripherals) { /// Initialize clocks for OSTIMER0 (1 MHz source). #[allow(dead_code)] -pub unsafe fn init_ostimer0(p: &hal::pac::Peripherals) { +pub unsafe fn init_ostimer0(p: &mcxa_pac::Peripherals) { clocks::ensure_frolf_running(p); clocks::enable_ostimer0(p); reset::release_reset_ostimer0(p); @@ -35,7 +35,7 @@ pub unsafe fn init_ostimer0(p: &hal::pac::Peripherals) { /// Initialize clocks and pin muxing for ADC. #[allow(dead_code)] -pub unsafe fn init_adc(p: &hal::pac::Peripherals) { +pub unsafe fn init_adc(p: &mcxa_pac::Peripherals) { clocks::ensure_frolf_running(p); clocks::enable_adc(p); reset::release_reset_port1(p); diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs index 30ba3f333..35d311143 100644 --- a/examples/lpuart_buffered.rs +++ b/examples/lpuart_buffered.rs @@ -26,7 +26,7 @@ async fn main(_spawner: Spawner) { let p2 = lpuart::lib::init(); unsafe { - hal::interrupt::install_irq_handler(mcxa276_pac::Interrupt::LPUART2, lpuart2_handler); + hal::interrupt::install_irq_handler(mcxa_pac::Interrupt::LPUART2, lpuart2_handler); } // Configure NVIC for LPUART2 diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs index a637b6353..368a3e52f 100644 --- a/examples/ostimer_race_test.rs +++ b/examples/ostimer_race_test.rs @@ -267,7 +267,7 @@ async fn test_concurrent_operations( async fn test_reset_during_operation( ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, uart: &mut hal::uart::Uart, - peripherals: &hal::pac::Peripherals, + peripherals: &mcxa_pac::Peripherals, ) { let initial_counter = ostimer.now(); -- cgit From c004f3616e2959df51ed4785ee0bba4e4c373fc6 Mon Sep 17 00:00:00 2001 From: James Munns Date: Wed, 12 Nov 2025 17:41:48 +0100 Subject: Comment out old clock gating logic, will be restored --- src/clocks.rs | 260 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 132 insertions(+), 128 deletions(-) diff --git a/src/clocks.rs b/src/clocks.rs index a00b3e4c5..c86ed1cd5 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -7,136 +7,140 @@ use mcxa_pac::scg0::{ use crate::pac; -/// Trait describing an AHB clock gate that can be toggled through MRCC. -pub trait Gate { - /// Enable the clock gate. - unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock); - - /// Return whether the clock gate is currently enabled. - fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool; -} - -/// Enable a clock gate for the given peripheral set. -#[inline] -pub unsafe fn enable(peripherals: &pac::Peripherals) { - let mrcc = &peripherals.mrcc0; - G::enable(mrcc); - while !G::is_enabled(mrcc) {} - core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); -} - -/// Check whether a gate is currently enabled. -#[inline] -pub fn is_enabled(peripherals: &pac::Peripherals) -> bool { - G::is_enabled(&peripherals.mrcc0) +pub trait SPConfHelper { + fn post_enable_config(&self, clocks: &Clocks) -> Result; } -macro_rules! impl_cc_gate { - ($name:ident, $reg:ident, $field:ident) => { - pub struct $name; - - impl Gate for $name { - #[inline] - unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) { - mrcc.$reg().modify(|_, w| w.$field().enabled()); - } - - #[inline] - fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool { - mrcc.$reg().read().$field().is_enabled() - } - } - }; -} - -pub mod gate { - use super::*; - - impl_cc_gate!(Port2, mrcc_glb_cc1, port2); - impl_cc_gate!(Port3, mrcc_glb_cc1, port3); - impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0); - impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2); - impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3); - impl_cc_gate!(Port1, mrcc_glb_cc1, port1); - impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1); -} - -/// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. -pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) { - enable::(peripherals); - enable::(peripherals); -} - -/// Convenience helper enabling the PORT3 and GPIO3 gates used by the LED in the examples. -pub unsafe fn enable_led_port(peripherals: &pac::Peripherals) { - enable::(peripherals); - enable::(peripherals); -} - -/// Convenience helper enabling the OSTIMER0 clock gate. -pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { - enable::(peripherals); -} - -pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { - // Use FRO_LF_DIV (already running) MUX=0 DIV=0 - let mrcc = &peripherals.mrcc0; - mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0()); - mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); -} - -pub unsafe fn ensure_frolf_running(peripherals: &pac::Peripherals) { - // Ensure FRO_LF divider clock is running (reset default HALT=1 stops it) - let sys = &peripherals.syscon; - sys.frolfdiv().modify(|_, w| { - // DIV defaults to 0; keep it explicit and clear HALT - unsafe { w.div().bits(0) }.halt().run() - }); -} - -/// Compute the FRO_LF_DIV output frequency currently selected for LPUART2. -/// Assumes select_uart2_clock() has chosen MUX=0 (FRO_LF_DIV) and DIV is set in SYSCON.FRO_LF_DIV. -pub unsafe fn uart2_src_hz(peripherals: &pac::Peripherals) -> u32 { - // SYSCON.FRO_LF_DIV: DIV field is simple divider: freq_out = 12_000_000 / (DIV+1) for many NXP parts. - // On MCXA276 FRO_LF base is 12 MHz; our init keeps DIV=0, so result=12_000_000. - // Read it anyway for future generality. - let div = peripherals.syscon.frolfdiv().read().div().bits() as u32; - let base = 12_000_000u32; - base / (div + 1) -} - -/// Enable clock gate and release reset for OSTIMER0. -/// Select OSTIMER0 clock source = 1 MHz root (working bring-up configuration). -pub unsafe fn select_ostimer0_clock_1m(peripherals: &pac::Peripherals) { - let mrcc = &peripherals.mrcc0; - mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); -} - -pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) { - let vbat = &peripherals.vbat0; - // Enable FRO16K oscillator - vbat.froctla().modify(|_, w| w.fro_en().set_bit()); - - // Lock the control register - vbat.frolcka().modify(|_, w| w.lock().set_bit()); - - // Enable clock outputs to both VSYS and VDD_CORE domains - // Bit 0: clk_16k0 to VSYS domain - // Bit 1: clk_16k1 to VDD_CORE domain - vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) }); -} - -pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { - enable::(peripherals); - enable::(peripherals); -} - -pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { - // Use FRO_LF_DIV (already running) MUX=0 DIV=0 - let mrcc = &peripherals.mrcc0; - mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0()); - mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); -} +// /// Trait describing an AHB clock gate that can be toggled through MRCC. +// pub trait Gate { +// /// Enable the clock gate. +// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock); + +// /// Return whether the clock gate is currently enabled. +// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool; +// } + +// /// Enable a clock gate for the given peripheral set. +// #[inline] +// pub unsafe fn enable(peripherals: &pac::Peripherals) { +// let mrcc = &peripherals.mrcc0; +// G::enable(mrcc); +// while !G::is_enabled(mrcc) {} +// core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); +// } + +// /// Check whether a gate is currently enabled. +// #[inline] +// pub fn is_enabled(peripherals: &pac::Peripherals) -> bool { +// G::is_enabled(&peripherals.mrcc0) +// } + +// macro_rules! impl_cc_gate { +// ($name:ident, $reg:ident, $field:ident) => { +// pub struct $name; + +// impl Gate for $name { +// #[inline] +// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) { +// mrcc.$reg().modify(|_, w| w.$field().enabled()); +// } + +// #[inline] +// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool { +// mrcc.$reg().read().$field().is_enabled() +// } +// } +// }; +// } + +// pub mod gate { +// use super::*; + +// impl_cc_gate!(Port2, mrcc_glb_cc1, port2); +// impl_cc_gate!(Port3, mrcc_glb_cc1, port3); +// impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0); +// impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2); +// impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3); +// impl_cc_gate!(Port1, mrcc_glb_cc1, port1); +// impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1); +// } + +// /// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. +// pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// enable::(peripherals); +// } + +// /// Convenience helper enabling the PORT3 and GPIO3 gates used by the LED in the examples. +// pub unsafe fn enable_led_port(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// enable::(peripherals); +// } + +// /// Convenience helper enabling the OSTIMER0 clock gate. +// pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// } + +// pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { +// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 +// let mrcc = &peripherals.mrcc0; +// mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0()); +// mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); +// } + +// pub unsafe fn ensure_frolf_running(peripherals: &pac::Peripherals) { +// // Ensure FRO_LF divider clock is running (reset default HALT=1 stops it) +// let sys = &peripherals.syscon; +// sys.frolfdiv().modify(|_, w| { +// // DIV defaults to 0; keep it explicit and clear HALT +// unsafe { w.div().bits(0) }.halt().run() +// }); +// } + +// /// Compute the FRO_LF_DIV output frequency currently selected for LPUART2. +// /// Assumes select_uart2_clock() has chosen MUX=0 (FRO_LF_DIV) and DIV is set in SYSCON.FRO_LF_DIV. +// pub unsafe fn uart2_src_hz(peripherals: &pac::Peripherals) -> u32 { +// // SYSCON.FRO_LF_DIV: DIV field is simple divider: freq_out = 12_000_000 / (DIV+1) for many NXP parts. +// // On MCXA276 FRO_LF base is 12 MHz; our init keeps DIV=0, so result=12_000_000. +// // Read it anyway for future generality. +// let div = peripherals.syscon.frolfdiv().read().div().bits() as u32; +// let base = 12_000_000u32; +// base / (div + 1) +// } + +// /// Enable clock gate and release reset for OSTIMER0. +// /// Select OSTIMER0 clock source = 1 MHz root (working bring-up configuration). +// pub unsafe fn select_ostimer0_clock_1m(peripherals: &pac::Peripherals) { +// let mrcc = &peripherals.mrcc0; +// mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); +// } + +// pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) { +// let vbat = &peripherals.vbat0; +// // Enable FRO16K oscillator +// vbat.froctla().modify(|_, w| w.fro_en().set_bit()); + +// // Lock the control register +// vbat.frolcka().modify(|_, w| w.lock().set_bit()); + +// // Enable clock outputs to both VSYS and VDD_CORE domains +// // Bit 0: clk_16k0 to VSYS domain +// // Bit 1: clk_16k1 to VDD_CORE domain +// vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) }); +// } + +// pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// enable::(peripherals); +// } + +// pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { +// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 +// let mrcc = &peripherals.mrcc0; +// mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0()); +// mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); +// } // ============================================== -- cgit From a2e63ff090d240f8dea0d448477990a89db114be Mon Sep 17 00:00:00 2001 From: James Munns Date: Wed, 12 Nov 2025 17:42:21 +0100 Subject: Move clocks into module --- src/clocks.rs | 617 ------------------------------------------------------ src/clocks/mod.rs | 617 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 617 insertions(+), 617 deletions(-) delete mode 100644 src/clocks.rs create mode 100644 src/clocks/mod.rs diff --git a/src/clocks.rs b/src/clocks.rs deleted file mode 100644 index c86ed1cd5..000000000 --- a/src/clocks.rs +++ /dev/null @@ -1,617 +0,0 @@ -//! Clock control helpers (no magic numbers, PAC field access only). -//! Provides reusable gate abstractions for peripherals used by the examples. -use mcxa_pac::scg0::{ - firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}, - sirccsr::{SircClkPeriphEn, Sircsten}, -}; - -use crate::pac; - -pub trait SPConfHelper { - fn post_enable_config(&self, clocks: &Clocks) -> Result; -} - -// /// Trait describing an AHB clock gate that can be toggled through MRCC. -// pub trait Gate { -// /// Enable the clock gate. -// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock); - -// /// Return whether the clock gate is currently enabled. -// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool; -// } - -// /// Enable a clock gate for the given peripheral set. -// #[inline] -// pub unsafe fn enable(peripherals: &pac::Peripherals) { -// let mrcc = &peripherals.mrcc0; -// G::enable(mrcc); -// while !G::is_enabled(mrcc) {} -// core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); -// } - -// /// Check whether a gate is currently enabled. -// #[inline] -// pub fn is_enabled(peripherals: &pac::Peripherals) -> bool { -// G::is_enabled(&peripherals.mrcc0) -// } - -// macro_rules! impl_cc_gate { -// ($name:ident, $reg:ident, $field:ident) => { -// pub struct $name; - -// impl Gate for $name { -// #[inline] -// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) { -// mrcc.$reg().modify(|_, w| w.$field().enabled()); -// } - -// #[inline] -// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool { -// mrcc.$reg().read().$field().is_enabled() -// } -// } -// }; -// } - -// pub mod gate { -// use super::*; - -// impl_cc_gate!(Port2, mrcc_glb_cc1, port2); -// impl_cc_gate!(Port3, mrcc_glb_cc1, port3); -// impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0); -// impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2); -// impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3); -// impl_cc_gate!(Port1, mrcc_glb_cc1, port1); -// impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1); -// } - -// /// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. -// pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// enable::(peripherals); -// } - -// /// Convenience helper enabling the PORT3 and GPIO3 gates used by the LED in the examples. -// pub unsafe fn enable_led_port(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// enable::(peripherals); -// } - -// /// Convenience helper enabling the OSTIMER0 clock gate. -// pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// } - -// pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { -// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 -// let mrcc = &peripherals.mrcc0; -// mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0()); -// mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); -// } - -// pub unsafe fn ensure_frolf_running(peripherals: &pac::Peripherals) { -// // Ensure FRO_LF divider clock is running (reset default HALT=1 stops it) -// let sys = &peripherals.syscon; -// sys.frolfdiv().modify(|_, w| { -// // DIV defaults to 0; keep it explicit and clear HALT -// unsafe { w.div().bits(0) }.halt().run() -// }); -// } - -// /// Compute the FRO_LF_DIV output frequency currently selected for LPUART2. -// /// Assumes select_uart2_clock() has chosen MUX=0 (FRO_LF_DIV) and DIV is set in SYSCON.FRO_LF_DIV. -// pub unsafe fn uart2_src_hz(peripherals: &pac::Peripherals) -> u32 { -// // SYSCON.FRO_LF_DIV: DIV field is simple divider: freq_out = 12_000_000 / (DIV+1) for many NXP parts. -// // On MCXA276 FRO_LF base is 12 MHz; our init keeps DIV=0, so result=12_000_000. -// // Read it anyway for future generality. -// let div = peripherals.syscon.frolfdiv().read().div().bits() as u32; -// let base = 12_000_000u32; -// base / (div + 1) -// } - -// /// Enable clock gate and release reset for OSTIMER0. -// /// Select OSTIMER0 clock source = 1 MHz root (working bring-up configuration). -// pub unsafe fn select_ostimer0_clock_1m(peripherals: &pac::Peripherals) { -// let mrcc = &peripherals.mrcc0; -// mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); -// } - -// pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) { -// let vbat = &peripherals.vbat0; -// // Enable FRO16K oscillator -// vbat.froctla().modify(|_, w| w.fro_en().set_bit()); - -// // Lock the control register -// vbat.frolcka().modify(|_, w| w.lock().set_bit()); - -// // Enable clock outputs to both VSYS and VDD_CORE domains -// // Bit 0: clk_16k0 to VSYS domain -// // Bit 1: clk_16k1 to VDD_CORE domain -// vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) }); -// } - -// pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// enable::(peripherals); -// } - -// pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { -// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 -// let mrcc = &peripherals.mrcc0; -// mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0()); -// mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); -// } - -// ============================================== - -/// This type represents a divider in the range 1..=256. -/// -/// At a hardware level, this is an 8-bit register from 0..=255, -/// which adds one. -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub struct Div8(pub(super) u8); - -impl Div8 { - /// Store a "raw" divisor value that will divide the source by - /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source - /// by 1, and `Div8::from_raw(255)` will divide the source by - /// 256. - pub const fn from_raw(n: u8) -> Self { - Self(n) - } - - /// Store a specific divisor value that will divide the source - /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source - /// by 1, and `Div8::from_divisor(256)` will divide the source - /// by 256. - /// - /// Will return `None` if `n` is not in the range `1..=256`. - /// Consider [`Self::from_raw`] for an infallible version. - pub const fn from_divisor(n: u16) -> Option { - let Some(n) = n.checked_sub(1) else { - return None; - }; - if n > (u8::MAX as u16) { - return None; - } - Some(Self(n as u8)) - } - - /// Convert into "raw" bits form - #[inline(always)] - pub const fn into_bits(self) -> u8 { - self.0 - } - - /// Convert into "divisor" form, as a u32 for convenient frequency math - #[inline(always)] - pub const fn into_divisor(self) -> u32 { - self.0 as u32 + 1 - } -} - -#[derive(Debug, Clone)] -pub struct Clock { - pub frequency: u32, - pub power: PoweredClock, -} - -#[derive(Debug, Clone, Copy)] -pub enum PoweredClock { - HighPowerOnly, - AlwaysEnabled, -} - -/// ```text -/// ┌─────────────────────────────────────────────────────────┐ -/// │ │ -/// │ ┌───────────┐ clk_out ┌─────────┐ │ -/// XTAL ──────┼──▷│ System │───────────▷│ │ clk_in │ -/// │ │ OSC │ clkout_byp │ MUX │──────────────────┼──────▷ -/// EXTAL ──────┼──▷│ │───────────▷│ │ │ -/// │ └───────────┘ └─────────┘ │ -/// │ │ -/// │ ┌───────────┐ fro_hf_root ┌────┐ fro_hf │ -/// │ │ FRO180 ├───────┬─────▷│ CG │─────────────────────┼──────▷ -/// │ │ │ │ ├────┤ clk_45m │ -/// │ │ │ └─────▷│ CG │─────────────────────┼──────▷ -/// │ └───────────┘ └────┘ │ -/// │ ┌───────────┐ fro_12m_root ┌────┐ fro_12m │ -/// │ │ FRO12M │────────┬─────▷│ CG │────────────────────┼──────▷ -/// │ │ │ │ ├────┤ clk_1m │ -/// │ │ │ └─────▷│1/12│────────────────────┼──────▷ -/// │ └───────────┘ └────┘ │ -/// │ │ -/// │ ┌──────────┐ │ -/// │ │000 │ │ -/// │ clk_in │ │ │ -/// │ ───────────────▷│001 │ │ -/// │ fro_12m │ │ │ -/// │ ───────────────▷│010 │ │ -/// │ fro_hf_root │ │ │ -/// │ ───────────────▷│011 │ main_clk │ -/// │ │ │───────────────────────────┼──────▷ -/// clk_16k ──────┼─────────────────▷│100 │ │ -/// │ none │ │ │ -/// │ ───────────────▷│101 │ │ -/// │ pll1_clk │ │ │ -/// │ ───────────────▷│110 │ │ -/// │ none │ │ │ -/// │ ───────────────▷│111 │ │ -/// │ └──────────┘ │ -/// │ ▲ │ -/// │ │ │ -/// │ SCG SCS │ -/// │ SCG-Lite │ -/// └─────────────────────────────────────────────────────────┘ -/// -/// -/// clk_in ┌─────┐ -/// ───────────────▷│00 │ -/// clk_45m │ │ -/// ───────────────▷│01 │ ┌───────────┐ pll1_clk -/// none │ │─────▷│ SPLL │───────────────▷ -/// ───────────────▷│10 │ └───────────┘ -/// fro_12m │ │ -/// ───────────────▷│11 │ -/// └─────┘ -/// ``` -#[non_exhaustive] -pub struct ClocksConfig { - // FIRC, FRO180, 45/60/90/180M clock source - pub firc: Option, - // NOTE: I don't think we *can* disable the SIRC? - pub sirc: SircConfig, -} - -// FIRC/FRO180M - -/// ```text -/// ┌───────────┐ fro_hf_root ┌────┐ fro_hf -/// │ FRO180M ├───────┬─────▷│GATE│──────────▷ -/// │ │ │ ├────┤ clk_45m -/// │ │ └─────▷│GATE│──────────▷ -/// └───────────┘ └────┘ -/// ``` -#[non_exhaustive] -pub struct FircConfig { - pub frequency: FircFreqSel, - pub power: PoweredClock, - /// Is the "fro_hf" gated clock enabled? - pub fro_hf_enabled: bool, - /// Is the "clk_45m" gated clock enabled? - pub clk_45m_enabled: bool, - /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`! - pub fro_hf_div: Option, -} - -pub enum FircFreqSel { - Mhz45, - Mhz60, - Mhz90, - Mhz180, -} - -// SIRC/FRO12M - -/// ```text -/// ┌───────────┐ fro_12m_root ┌────┐ fro_12m -/// │ FRO12M │────────┬─────▷│ CG │──────────▷ -/// │ │ │ ├────┤ clk_1m -/// │ │ └─────▷│1/12│──────────▷ -/// └───────────┘ └────┘ -/// ``` -#[non_exhaustive] -pub struct SircConfig { - pub power: PoweredClock, - // peripheral output, aka sirc_12mhz - pub fro_12m_enabled: bool, - /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`! - pub fro_lf_div: Option, -} - -#[derive(Default, Debug, Clone)] -#[non_exhaustive] -pub struct Clocks { - pub clk_in: Option, - - // FRO180M stuff - // - pub fro_hf_root: Option, - pub fro_hf: Option, - pub clk_45m: Option, - pub fro_hf_div: Option, - // - // End FRO180M - - // FRO12M stuff - pub fro_12m_root: Option, - pub fro_12m: Option, - pub clk_1m: Option, - pub fro_lf_div: Option, - // - // End FRO12M stuff - pub main_clk: Option, - pub pll1_clk: Option, -} - -static CLOCKS: critical_section::Mutex> = critical_section::Mutex::new(None); - -#[non_exhaustive] -pub enum ClockError { - AlreadyInitialized, - BadConfig { clock: &'static str, reason: &'static str }, -} - -struct ClockOperator<'a> { - clocks: &'a mut Clocks, - config: &'a ClocksConfig, - - _mrcc0: pac::Mrcc0, - scg0: pac::Scg0, - syscon: pac::Syscon, -} - -impl ClockOperator<'_> { - fn configure_firc_clocks(&mut self) -> Result<(), ClockError> { - const HARDCODED_ERR: Result<(), ClockError> = Err(ClockError::BadConfig { - clock: "firc", - reason: "For now, FIRC must be enabled and in default state!", - }); - - // Did the user give us a FIRC config? - let Some(firc) = self.config.firc.as_ref() else { - return HARDCODED_ERR; - }; - // Is the FIRC set to 45MHz (should be reset default) - if !matches!(firc.frequency, FircFreqSel::Mhz45) { - return HARDCODED_ERR; - } - let base_freq = 45_000_000; - - // Is the FIRC as expected? - let mut firc_ok = true; - - // Is the hardware currently set to the default 45MHz? - // - // NOTE: the SVD currently has the wrong(?) values for these: - // 45 -> 48 - // 60 -> 64 - // 90 -> 96 - // 180 -> 192 - // Probably correct-ish, but for a different trim value? - firc_ok &= self.scg0.firccfg().read().freq_sel().is_firc_48mhz_192s(); - - // Check some values in the CSR - let csr = self.scg0.firccsr().read(); - // Is it enabled? - firc_ok &= csr.fircen().is_enabled(); - // Is it accurate? - firc_ok &= csr.fircacc().is_enabled_and_valid(); - // Is there no error? - firc_ok &= csr.fircerr().is_error_not_detected(); - // Is the FIRC the system clock? - firc_ok &= csr.fircsel().is_firc(); - // Is it valid? - firc_ok &= csr.fircvld().is_enabled_and_valid(); - - // Are we happy with the current (hardcoded) state? - if !firc_ok { - return HARDCODED_ERR; - } - - // Note that the fro_hf_root is active - self.clocks.fro_hf_root = Some(Clock { - frequency: base_freq, - power: firc.power, - }); - - // Okay! Now we're past that, let's enable all the downstream clocks. - let FircConfig { - frequency: _, - power, - fro_hf_enabled, - clk_45m_enabled, - fro_hf_div, - } = firc; - - // When is the FRO enabled? - let pow_set = match power { - PoweredClock::HighPowerOnly => Fircsten::DisabledInStopModes, - PoweredClock::AlwaysEnabled => Fircsten::EnabledInStopModes, - }; - - // Do we enable the `fro_hf` output? - let fro_hf_set = if *fro_hf_enabled { - self.clocks.fro_hf = Some(Clock { - frequency: base_freq, - power: *power, - }); - FircFclkPeriphEn::Enabled - } else { - FircFclkPeriphEn::Disabled - }; - - // Do we enable the `clk_45m` output? - let clk_45m_set = if *clk_45m_enabled { - self.clocks.clk_45m = Some(Clock { - frequency: 45_000_000, - power: *power, - }); - FircSclkPeriphEn::Enabled - } else { - FircSclkPeriphEn::Disabled - }; - - self.scg0.firccsr().modify(|_r, w| { - w.fircsten().variant(pow_set); - w.firc_fclk_periph_en().variant(fro_hf_set); - w.firc_sclk_periph_en().variant(clk_45m_set); - w - }); - - // Do we enable the `fro_hf_div` output? - if let Some(d) = fro_hf_div.as_ref() { - // We need `fro_hf` to be enabled - if !*fro_hf_enabled { - return Err(ClockError::BadConfig { - clock: "fro_hf_div", - reason: "fro_hf not enabled", - }); - } - - // Halt and reset the div - self.syscon.frohfdiv().write(|w| { - w.halt().halt(); - w.reset().asserted(); - w - }); - // Then change the div, unhalt it, and reset it - self.syscon.frohfdiv().write(|w| { - unsafe { - w.div().bits(d.into_bits()); - } - w.halt().run(); - w.reset().released(); - w - }); - - // Wait for clock to stabilize - while self.syscon.frohfdiv().read().unstab().is_ongoing() {} - - // Store off the clock info - self.clocks.fro_hf_div = Some(Clock { - frequency: base_freq / d.into_divisor(), - power: *power, - }); - } - - Ok(()) - } - - fn configure_sirc_clocks(&mut self) -> Result<(), ClockError> { - let SircConfig { - power, - fro_12m_enabled, - fro_lf_div, - } = &self.config.sirc; - let base_freq = 12_000_000; - - // Allow writes - self.scg0.sirccsr().modify(|_r, w| w.lk().write_enabled()); - self.clocks.fro_12m_root = Some(Clock { - frequency: base_freq, - power: *power, - }); - - let deep = match power { - PoweredClock::HighPowerOnly => Sircsten::Disabled, - PoweredClock::AlwaysEnabled => Sircsten::Enabled, - }; - let pclk = if *fro_12m_enabled { - self.clocks.fro_12m = Some(Clock { - frequency: base_freq, - power: *power, - }); - self.clocks.clk_1m = Some(Clock { - frequency: base_freq / 12, - power: *power, - }); - SircClkPeriphEn::Enabled - } else { - SircClkPeriphEn::Disabled - }; - - // Set sleep/peripheral usage - self.scg0.sirccsr().modify(|_r, w| { - w.sircsten().variant(deep); - w.sirc_clk_periph_en().variant(pclk); - w - }); - - while self.scg0.sirccsr().read().sircvld().is_disabled_or_not_valid() {} - if self.scg0.sirccsr().read().sircerr().is_error_detected() { - return Err(ClockError::BadConfig { - clock: "sirc", - reason: "error set", - }); - } - - // reset lock - self.scg0.sirccsr().modify(|_r, w| w.lk().write_disabled()); - - // Do we enable the `fro_lf_div` output? - if let Some(d) = fro_lf_div.as_ref() { - // We need `fro_lf` to be enabled - if !*fro_12m_enabled { - return Err(ClockError::BadConfig { - clock: "fro_lf_div", - reason: "fro_12m not enabled", - }); - } - - // Halt and reset the div - self.syscon.frolfdiv().write(|w| { - w.halt().halt(); - w.reset().asserted(); - w - }); - // Then change the div, unhalt it, and reset it - self.syscon.frolfdiv().write(|w| { - unsafe { - w.div().bits(d.into_bits()); - } - w.halt().run(); - w.reset().released(); - w - }); - - // Wait for clock to stabilize - while self.syscon.frolfdiv().read().unstab().is_ongoing() {} - - // Store off the clock info - self.clocks.fro_lf_div = Some(Clock { - frequency: base_freq / d.into_divisor(), - power: *power, - }); - } - - todo!() - } -} - -pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { - critical_section::with(|cs| { - if CLOCKS.borrow(cs).is_some() { - Err(ClockError::AlreadyInitialized) - } else { - Ok(()) - } - })?; - - let mut clocks = Clocks::default(); - let mut operator = ClockOperator { - clocks: &mut clocks, - config: &settings, - - _mrcc0: unsafe { pac::Mrcc0::steal() }, - scg0: unsafe { pac::Scg0::steal() }, - syscon: unsafe { pac::Syscon::steal() }, - }; - - operator.configure_firc_clocks()?; - operator.configure_sirc_clocks()?; - // TODO, everything downstream - - Ok(()) -} - -/// Obtain the full clocks structure, calling the given closure in a critical section -/// -/// NOTE: Clocks implements `Clone`, -pub fn with_clocks R>(f: F) -> Option { - critical_section::with(|cs| { - let c = CLOCKS.borrow(cs).as_ref()?; - Some(f(c)) - }) -} diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs new file mode 100644 index 000000000..c86ed1cd5 --- /dev/null +++ b/src/clocks/mod.rs @@ -0,0 +1,617 @@ +//! Clock control helpers (no magic numbers, PAC field access only). +//! Provides reusable gate abstractions for peripherals used by the examples. +use mcxa_pac::scg0::{ + firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}, + sirccsr::{SircClkPeriphEn, Sircsten}, +}; + +use crate::pac; + +pub trait SPConfHelper { + fn post_enable_config(&self, clocks: &Clocks) -> Result; +} + +// /// Trait describing an AHB clock gate that can be toggled through MRCC. +// pub trait Gate { +// /// Enable the clock gate. +// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock); + +// /// Return whether the clock gate is currently enabled. +// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool; +// } + +// /// Enable a clock gate for the given peripheral set. +// #[inline] +// pub unsafe fn enable(peripherals: &pac::Peripherals) { +// let mrcc = &peripherals.mrcc0; +// G::enable(mrcc); +// while !G::is_enabled(mrcc) {} +// core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); +// } + +// /// Check whether a gate is currently enabled. +// #[inline] +// pub fn is_enabled(peripherals: &pac::Peripherals) -> bool { +// G::is_enabled(&peripherals.mrcc0) +// } + +// macro_rules! impl_cc_gate { +// ($name:ident, $reg:ident, $field:ident) => { +// pub struct $name; + +// impl Gate for $name { +// #[inline] +// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) { +// mrcc.$reg().modify(|_, w| w.$field().enabled()); +// } + +// #[inline] +// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool { +// mrcc.$reg().read().$field().is_enabled() +// } +// } +// }; +// } + +// pub mod gate { +// use super::*; + +// impl_cc_gate!(Port2, mrcc_glb_cc1, port2); +// impl_cc_gate!(Port3, mrcc_glb_cc1, port3); +// impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0); +// impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2); +// impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3); +// impl_cc_gate!(Port1, mrcc_glb_cc1, port1); +// impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1); +// } + +// /// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. +// pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// enable::(peripherals); +// } + +// /// Convenience helper enabling the PORT3 and GPIO3 gates used by the LED in the examples. +// pub unsafe fn enable_led_port(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// enable::(peripherals); +// } + +// /// Convenience helper enabling the OSTIMER0 clock gate. +// pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// } + +// pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { +// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 +// let mrcc = &peripherals.mrcc0; +// mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0()); +// mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); +// } + +// pub unsafe fn ensure_frolf_running(peripherals: &pac::Peripherals) { +// // Ensure FRO_LF divider clock is running (reset default HALT=1 stops it) +// let sys = &peripherals.syscon; +// sys.frolfdiv().modify(|_, w| { +// // DIV defaults to 0; keep it explicit and clear HALT +// unsafe { w.div().bits(0) }.halt().run() +// }); +// } + +// /// Compute the FRO_LF_DIV output frequency currently selected for LPUART2. +// /// Assumes select_uart2_clock() has chosen MUX=0 (FRO_LF_DIV) and DIV is set in SYSCON.FRO_LF_DIV. +// pub unsafe fn uart2_src_hz(peripherals: &pac::Peripherals) -> u32 { +// // SYSCON.FRO_LF_DIV: DIV field is simple divider: freq_out = 12_000_000 / (DIV+1) for many NXP parts. +// // On MCXA276 FRO_LF base is 12 MHz; our init keeps DIV=0, so result=12_000_000. +// // Read it anyway for future generality. +// let div = peripherals.syscon.frolfdiv().read().div().bits() as u32; +// let base = 12_000_000u32; +// base / (div + 1) +// } + +// /// Enable clock gate and release reset for OSTIMER0. +// /// Select OSTIMER0 clock source = 1 MHz root (working bring-up configuration). +// pub unsafe fn select_ostimer0_clock_1m(peripherals: &pac::Peripherals) { +// let mrcc = &peripherals.mrcc0; +// mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); +// } + +// pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) { +// let vbat = &peripherals.vbat0; +// // Enable FRO16K oscillator +// vbat.froctla().modify(|_, w| w.fro_en().set_bit()); + +// // Lock the control register +// vbat.frolcka().modify(|_, w| w.lock().set_bit()); + +// // Enable clock outputs to both VSYS and VDD_CORE domains +// // Bit 0: clk_16k0 to VSYS domain +// // Bit 1: clk_16k1 to VDD_CORE domain +// vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) }); +// } + +// pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { +// enable::(peripherals); +// enable::(peripherals); +// } + +// pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { +// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 +// let mrcc = &peripherals.mrcc0; +// mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0()); +// mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); +// } + +// ============================================== + +/// This type represents a divider in the range 1..=256. +/// +/// At a hardware level, this is an 8-bit register from 0..=255, +/// which adds one. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub struct Div8(pub(super) u8); + +impl Div8 { + /// Store a "raw" divisor value that will divide the source by + /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source + /// by 1, and `Div8::from_raw(255)` will divide the source by + /// 256. + pub const fn from_raw(n: u8) -> Self { + Self(n) + } + + /// Store a specific divisor value that will divide the source + /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source + /// by 1, and `Div8::from_divisor(256)` will divide the source + /// by 256. + /// + /// Will return `None` if `n` is not in the range `1..=256`. + /// Consider [`Self::from_raw`] for an infallible version. + pub const fn from_divisor(n: u16) -> Option { + let Some(n) = n.checked_sub(1) else { + return None; + }; + if n > (u8::MAX as u16) { + return None; + } + Some(Self(n as u8)) + } + + /// Convert into "raw" bits form + #[inline(always)] + pub const fn into_bits(self) -> u8 { + self.0 + } + + /// Convert into "divisor" form, as a u32 for convenient frequency math + #[inline(always)] + pub const fn into_divisor(self) -> u32 { + self.0 as u32 + 1 + } +} + +#[derive(Debug, Clone)] +pub struct Clock { + pub frequency: u32, + pub power: PoweredClock, +} + +#[derive(Debug, Clone, Copy)] +pub enum PoweredClock { + HighPowerOnly, + AlwaysEnabled, +} + +/// ```text +/// ┌─────────────────────────────────────────────────────────┐ +/// │ │ +/// │ ┌───────────┐ clk_out ┌─────────┐ │ +/// XTAL ──────┼──▷│ System │───────────▷│ │ clk_in │ +/// │ │ OSC │ clkout_byp │ MUX │──────────────────┼──────▷ +/// EXTAL ──────┼──▷│ │───────────▷│ │ │ +/// │ └───────────┘ └─────────┘ │ +/// │ │ +/// │ ┌───────────┐ fro_hf_root ┌────┐ fro_hf │ +/// │ │ FRO180 ├───────┬─────▷│ CG │─────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_45m │ +/// │ │ │ └─────▷│ CG │─────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ ┌───────────┐ fro_12m_root ┌────┐ fro_12m │ +/// │ │ FRO12M │────────┬─────▷│ CG │────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_1m │ +/// │ │ │ └─────▷│1/12│────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ │ +/// │ ┌──────────┐ │ +/// │ │000 │ │ +/// │ clk_in │ │ │ +/// │ ───────────────▷│001 │ │ +/// │ fro_12m │ │ │ +/// │ ───────────────▷│010 │ │ +/// │ fro_hf_root │ │ │ +/// │ ───────────────▷│011 │ main_clk │ +/// │ │ │───────────────────────────┼──────▷ +/// clk_16k ──────┼─────────────────▷│100 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│101 │ │ +/// │ pll1_clk │ │ │ +/// │ ───────────────▷│110 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│111 │ │ +/// │ └──────────┘ │ +/// │ ▲ │ +/// │ │ │ +/// │ SCG SCS │ +/// │ SCG-Lite │ +/// └─────────────────────────────────────────────────────────┘ +/// +/// +/// clk_in ┌─────┐ +/// ───────────────▷│00 │ +/// clk_45m │ │ +/// ───────────────▷│01 │ ┌───────────┐ pll1_clk +/// none │ │─────▷│ SPLL │───────────────▷ +/// ───────────────▷│10 │ └───────────┘ +/// fro_12m │ │ +/// ───────────────▷│11 │ +/// └─────┘ +/// ``` +#[non_exhaustive] +pub struct ClocksConfig { + // FIRC, FRO180, 45/60/90/180M clock source + pub firc: Option, + // NOTE: I don't think we *can* disable the SIRC? + pub sirc: SircConfig, +} + +// FIRC/FRO180M + +/// ```text +/// ┌───────────┐ fro_hf_root ┌────┐ fro_hf +/// │ FRO180M ├───────┬─────▷│GATE│──────────▷ +/// │ │ │ ├────┤ clk_45m +/// │ │ └─────▷│GATE│──────────▷ +/// └───────────┘ └────┘ +/// ``` +#[non_exhaustive] +pub struct FircConfig { + pub frequency: FircFreqSel, + pub power: PoweredClock, + /// Is the "fro_hf" gated clock enabled? + pub fro_hf_enabled: bool, + /// Is the "clk_45m" gated clock enabled? + pub clk_45m_enabled: bool, + /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`! + pub fro_hf_div: Option, +} + +pub enum FircFreqSel { + Mhz45, + Mhz60, + Mhz90, + Mhz180, +} + +// SIRC/FRO12M + +/// ```text +/// ┌───────────┐ fro_12m_root ┌────┐ fro_12m +/// │ FRO12M │────────┬─────▷│ CG │──────────▷ +/// │ │ │ ├────┤ clk_1m +/// │ │ └─────▷│1/12│──────────▷ +/// └───────────┘ └────┘ +/// ``` +#[non_exhaustive] +pub struct SircConfig { + pub power: PoweredClock, + // peripheral output, aka sirc_12mhz + pub fro_12m_enabled: bool, + /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`! + pub fro_lf_div: Option, +} + +#[derive(Default, Debug, Clone)] +#[non_exhaustive] +pub struct Clocks { + pub clk_in: Option, + + // FRO180M stuff + // + pub fro_hf_root: Option, + pub fro_hf: Option, + pub clk_45m: Option, + pub fro_hf_div: Option, + // + // End FRO180M + + // FRO12M stuff + pub fro_12m_root: Option, + pub fro_12m: Option, + pub clk_1m: Option, + pub fro_lf_div: Option, + // + // End FRO12M stuff + pub main_clk: Option, + pub pll1_clk: Option, +} + +static CLOCKS: critical_section::Mutex> = critical_section::Mutex::new(None); + +#[non_exhaustive] +pub enum ClockError { + AlreadyInitialized, + BadConfig { clock: &'static str, reason: &'static str }, +} + +struct ClockOperator<'a> { + clocks: &'a mut Clocks, + config: &'a ClocksConfig, + + _mrcc0: pac::Mrcc0, + scg0: pac::Scg0, + syscon: pac::Syscon, +} + +impl ClockOperator<'_> { + fn configure_firc_clocks(&mut self) -> Result<(), ClockError> { + const HARDCODED_ERR: Result<(), ClockError> = Err(ClockError::BadConfig { + clock: "firc", + reason: "For now, FIRC must be enabled and in default state!", + }); + + // Did the user give us a FIRC config? + let Some(firc) = self.config.firc.as_ref() else { + return HARDCODED_ERR; + }; + // Is the FIRC set to 45MHz (should be reset default) + if !matches!(firc.frequency, FircFreqSel::Mhz45) { + return HARDCODED_ERR; + } + let base_freq = 45_000_000; + + // Is the FIRC as expected? + let mut firc_ok = true; + + // Is the hardware currently set to the default 45MHz? + // + // NOTE: the SVD currently has the wrong(?) values for these: + // 45 -> 48 + // 60 -> 64 + // 90 -> 96 + // 180 -> 192 + // Probably correct-ish, but for a different trim value? + firc_ok &= self.scg0.firccfg().read().freq_sel().is_firc_48mhz_192s(); + + // Check some values in the CSR + let csr = self.scg0.firccsr().read(); + // Is it enabled? + firc_ok &= csr.fircen().is_enabled(); + // Is it accurate? + firc_ok &= csr.fircacc().is_enabled_and_valid(); + // Is there no error? + firc_ok &= csr.fircerr().is_error_not_detected(); + // Is the FIRC the system clock? + firc_ok &= csr.fircsel().is_firc(); + // Is it valid? + firc_ok &= csr.fircvld().is_enabled_and_valid(); + + // Are we happy with the current (hardcoded) state? + if !firc_ok { + return HARDCODED_ERR; + } + + // Note that the fro_hf_root is active + self.clocks.fro_hf_root = Some(Clock { + frequency: base_freq, + power: firc.power, + }); + + // Okay! Now we're past that, let's enable all the downstream clocks. + let FircConfig { + frequency: _, + power, + fro_hf_enabled, + clk_45m_enabled, + fro_hf_div, + } = firc; + + // When is the FRO enabled? + let pow_set = match power { + PoweredClock::HighPowerOnly => Fircsten::DisabledInStopModes, + PoweredClock::AlwaysEnabled => Fircsten::EnabledInStopModes, + }; + + // Do we enable the `fro_hf` output? + let fro_hf_set = if *fro_hf_enabled { + self.clocks.fro_hf = Some(Clock { + frequency: base_freq, + power: *power, + }); + FircFclkPeriphEn::Enabled + } else { + FircFclkPeriphEn::Disabled + }; + + // Do we enable the `clk_45m` output? + let clk_45m_set = if *clk_45m_enabled { + self.clocks.clk_45m = Some(Clock { + frequency: 45_000_000, + power: *power, + }); + FircSclkPeriphEn::Enabled + } else { + FircSclkPeriphEn::Disabled + }; + + self.scg0.firccsr().modify(|_r, w| { + w.fircsten().variant(pow_set); + w.firc_fclk_periph_en().variant(fro_hf_set); + w.firc_sclk_periph_en().variant(clk_45m_set); + w + }); + + // Do we enable the `fro_hf_div` output? + if let Some(d) = fro_hf_div.as_ref() { + // We need `fro_hf` to be enabled + if !*fro_hf_enabled { + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "fro_hf not enabled", + }); + } + + // Halt and reset the div + self.syscon.frohfdiv().write(|w| { + w.halt().halt(); + w.reset().asserted(); + w + }); + // Then change the div, unhalt it, and reset it + self.syscon.frohfdiv().write(|w| { + unsafe { + w.div().bits(d.into_bits()); + } + w.halt().run(); + w.reset().released(); + w + }); + + // Wait for clock to stabilize + while self.syscon.frohfdiv().read().unstab().is_ongoing() {} + + // Store off the clock info + self.clocks.fro_hf_div = Some(Clock { + frequency: base_freq / d.into_divisor(), + power: *power, + }); + } + + Ok(()) + } + + fn configure_sirc_clocks(&mut self) -> Result<(), ClockError> { + let SircConfig { + power, + fro_12m_enabled, + fro_lf_div, + } = &self.config.sirc; + let base_freq = 12_000_000; + + // Allow writes + self.scg0.sirccsr().modify(|_r, w| w.lk().write_enabled()); + self.clocks.fro_12m_root = Some(Clock { + frequency: base_freq, + power: *power, + }); + + let deep = match power { + PoweredClock::HighPowerOnly => Sircsten::Disabled, + PoweredClock::AlwaysEnabled => Sircsten::Enabled, + }; + let pclk = if *fro_12m_enabled { + self.clocks.fro_12m = Some(Clock { + frequency: base_freq, + power: *power, + }); + self.clocks.clk_1m = Some(Clock { + frequency: base_freq / 12, + power: *power, + }); + SircClkPeriphEn::Enabled + } else { + SircClkPeriphEn::Disabled + }; + + // Set sleep/peripheral usage + self.scg0.sirccsr().modify(|_r, w| { + w.sircsten().variant(deep); + w.sirc_clk_periph_en().variant(pclk); + w + }); + + while self.scg0.sirccsr().read().sircvld().is_disabled_or_not_valid() {} + if self.scg0.sirccsr().read().sircerr().is_error_detected() { + return Err(ClockError::BadConfig { + clock: "sirc", + reason: "error set", + }); + } + + // reset lock + self.scg0.sirccsr().modify(|_r, w| w.lk().write_disabled()); + + // Do we enable the `fro_lf_div` output? + if let Some(d) = fro_lf_div.as_ref() { + // We need `fro_lf` to be enabled + if !*fro_12m_enabled { + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "fro_12m not enabled", + }); + } + + // Halt and reset the div + self.syscon.frolfdiv().write(|w| { + w.halt().halt(); + w.reset().asserted(); + w + }); + // Then change the div, unhalt it, and reset it + self.syscon.frolfdiv().write(|w| { + unsafe { + w.div().bits(d.into_bits()); + } + w.halt().run(); + w.reset().released(); + w + }); + + // Wait for clock to stabilize + while self.syscon.frolfdiv().read().unstab().is_ongoing() {} + + // Store off the clock info + self.clocks.fro_lf_div = Some(Clock { + frequency: base_freq / d.into_divisor(), + power: *power, + }); + } + + todo!() + } +} + +pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { + critical_section::with(|cs| { + if CLOCKS.borrow(cs).is_some() { + Err(ClockError::AlreadyInitialized) + } else { + Ok(()) + } + })?; + + let mut clocks = Clocks::default(); + let mut operator = ClockOperator { + clocks: &mut clocks, + config: &settings, + + _mrcc0: unsafe { pac::Mrcc0::steal() }, + scg0: unsafe { pac::Scg0::steal() }, + syscon: unsafe { pac::Syscon::steal() }, + }; + + operator.configure_firc_clocks()?; + operator.configure_sirc_clocks()?; + // TODO, everything downstream + + Ok(()) +} + +/// Obtain the full clocks structure, calling the given closure in a critical section +/// +/// NOTE: Clocks implements `Clone`, +pub fn with_clocks R>(f: F) -> Option { + critical_section::with(|cs| { + let c = CLOCKS.borrow(cs).as_ref()?; + Some(f(c)) + }) +} -- cgit From 2f08491f1a09df79bf1d41e26217d21b0bd7bdae Mon Sep 17 00:00:00 2001 From: James Munns Date: Wed, 12 Nov 2025 18:54:27 +0100 Subject: Start adding peripheral helpers --- Cargo.toml | 2 +- src/clocks/mod.rs | 69 +++++++++++++++++++++--- src/clocks/periph_helpers.rs | 125 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 188 insertions(+), 8 deletions(-) create mode 100644 src/clocks/periph_helpers.rs diff --git a/Cargo.toml b/Cargo.toml index 8ec547494..afcb2d3c9 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -23,7 +23,7 @@ embassy-time = "0.5.0" embassy-time-driver = "0.2.1" embedded-io = "0.6" heapless = "0.8" -mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "f0281344c605ab24c38979553b41a1655c50625c", version = "0.1.0" } +mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "f25b7aed0b8ad8e610012046e09340926cbd51a2", version = "0.1.0" } paste = "1.0.15" embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [ diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index c86ed1cd5..ad48a9cf2 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -6,10 +6,7 @@ use mcxa_pac::scg0::{ }; use crate::pac; - -pub trait SPConfHelper { - fn post_enable_config(&self, clocks: &Clocks) -> Result; -} +pub mod periph_helpers; // /// Trait describing an AHB clock gate that can be toggled through MRCC. // pub trait Gate { @@ -198,10 +195,22 @@ pub struct Clock { #[derive(Debug, Clone, Copy)] pub enum PoweredClock { - HighPowerOnly, + NormalEnabledDeepSleepDisabled, AlwaysEnabled, } +impl PoweredClock { + /// Does THIS clock meet the power requirements of the OTHER clock? + pub fn meets_requirement_of(&self, other: &Self) -> bool { + match (self, other) { + (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::AlwaysEnabled) => false, + (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true, + (PoweredClock::AlwaysEnabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true, + (PoweredClock::AlwaysEnabled, PoweredClock::AlwaysEnabled) => true, + } + } +} + /// ```text /// ┌─────────────────────────────────────────────────────────┐ /// │ │ @@ -341,6 +350,7 @@ static CLOCKS: critical_section::Mutex> = critical_section::Mutex pub enum ClockError { AlreadyInitialized, BadConfig { clock: &'static str, reason: &'static str }, + NotImplemented { clock: &'static str }, } struct ClockOperator<'a> { @@ -417,7 +427,7 @@ impl ClockOperator<'_> { // When is the FRO enabled? let pow_set = match power { - PoweredClock::HighPowerOnly => Fircsten::DisabledInStopModes, + PoweredClock::NormalEnabledDeepSleepDisabled => Fircsten::DisabledInStopModes, PoweredClock::AlwaysEnabled => Fircsten::EnabledInStopModes, }; @@ -505,7 +515,7 @@ impl ClockOperator<'_> { }); let deep = match power { - PoweredClock::HighPowerOnly => Sircsten::Disabled, + PoweredClock::NormalEnabledDeepSleepDisabled => Sircsten::Disabled, PoweredClock::AlwaysEnabled => Sircsten::Enabled, }; let pclk = if *fro_12m_enabled { @@ -615,3 +625,48 @@ pub fn with_clocks R>(f: F) -> Option { Some(f(c)) }) } + +impl Clocks { + pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_lf_div.as_ref() else { + return Err(ClockError::BadConfig { clock: "fro_lf_div", reason: "required but not active" }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { clock: "fro_lf_div", reason: "not low power active" }); + } + Ok(clk.frequency) + } + + pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_hf_div.as_ref() else { + return Err(ClockError::BadConfig { clock: "fro_hf_div", reason: "required but not active" }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { clock: "fro_hf_div", reason: "not low power active" }); + } + Ok(clk.frequency) + } + + pub fn ensure_clk_in_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "clk_in" }) + } + + pub fn ensure_clk_16k_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "clk_16k" }) + } + + pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.clk_1m.as_ref() else { + return Err(ClockError::BadConfig { clock: "clk_1m", reason: "required but not active" }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { clock: "clk_1m", reason: "not low power active" }); + } + Ok(clk.frequency) + } + + pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "pll1_clk_div" }) + } + +} diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs new file mode 100644 index 000000000..c4d4e9e3b --- /dev/null +++ b/src/clocks/periph_helpers.rs @@ -0,0 +1,125 @@ +use super::{ClockError, Clocks, Div8, PoweredClock}; +use crate::pac; + +pub trait SPConfHelper { + fn post_enable_config(&self, clocks: &Clocks) -> Result; +} + +// config types + +pub enum LpuartClockSel { + /// FRO12M/FRO_LF/SIRC clock source, passed through divider + /// "fro_lf_div" + FroLfDiv, + /// FRO180M/FRO_HF/FIRC clock source, passed through divider + /// "fro_hf_div" + FroHfDiv, + /// SOSC/XTAL/EXTAL clock source + ClkIn, + /// FRO16K/clk_16k source + Clk16K, + /// clk_1m/FRO_LF divided by 12 + Clk1M, + /// Output of PLL1, passed through clock divider, + /// "pll1_clk_div", maybe "pll1_lf_div"? + Pll1ClkDiv, + /// Disabled + None, +} + +pub enum LpuartInstance { + Lpuart0, + Lpuart1, + Lpuart2, + Lpuart3, + Lpuart4, + Lpuart5, +} + +pub struct LpuartConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Clock source + pub source: LpuartClockSel, + /// Clock divisor + pub div: Div8, + /// Which instance is this? + // NOTE: should not be user settable + instance: LpuartInstance, +} + +// impls + +impl SPConfHelper for LpuartConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + // check that source is suitable + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + use mcxa_pac::mrcc0::mrcc_lpuart0_clksel::Mux; + + let (clkdiv, clksel) = match self.instance { + LpuartInstance::Lpuart0 => (mrcc0.mrcc_lpuart0_clkdiv(), mrcc0.mrcc_lpuart0_clksel()), + LpuartInstance::Lpuart1 => (mrcc0.mrcc_lpuart1_clkdiv(), mrcc0.mrcc_lpuart1_clksel()), + LpuartInstance::Lpuart2 => (mrcc0.mrcc_lpuart2_clkdiv(), mrcc0.mrcc_lpuart2_clksel()), + LpuartInstance::Lpuart3 => (mrcc0.mrcc_lpuart3_clkdiv(), mrcc0.mrcc_lpuart3_clksel()), + LpuartInstance::Lpuart4 => (mrcc0.mrcc_lpuart4_clkdiv(), mrcc0.mrcc_lpuart4_clksel()), + LpuartInstance::Lpuart5 => (mrcc0.mrcc_lpuart5_clkdiv(), mrcc0.mrcc_lpuart5_clksel()), + }; + + let (freq, variant) = match self.source { + LpuartClockSel::FroLfDiv => { + let freq = clocks.ensure_fro_lf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc0) + } + LpuartClockSel::FroHfDiv => { + let freq = clocks.ensure_fro_hf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc2) + } + LpuartClockSel::ClkIn => { + let freq = clocks.ensure_clk_in_active(&self.power)?; + (freq, Mux::ClkrootFunc3) + } + LpuartClockSel::Clk16K => { + let freq = clocks.ensure_clk_16k_active(&self.power)?; + (freq, Mux::ClkrootFunc4) + } + LpuartClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + (freq, Mux::ClkrootFunc5) + } + LpuartClockSel::Pll1ClkDiv => { + let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; + (freq, Mux::ClkrootFunc6) + } + LpuartClockSel::None => unsafe { + // no ClkrootFunc7, just write manually for now + clksel.write(|w| w.bits(0b111)); + clkdiv.modify(|_r, w| { + w.reset().on(); + w.halt().on(); + w + }); + return Ok(0); + }, + }; + + // set clksel + clksel.modify(|_r, w| w.mux().variant(variant)); + + // Set up clkdiv + clkdiv.modify(|_r, w| { + w.halt().on(); + w.reset().on(); + w + }); + clkdiv.modify(|_r, w| { + w.halt().off(); + w.reset().off(); + unsafe { w.div().bits(self.div.into_bits()) }; + w + }); + + while clkdiv.read().unstab().is_on() {} + + Ok(freq / self.div.into_divisor()) + } +} -- cgit From 316f91ad59c528c00e46198c4a4c4537470e99de Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 13 Nov 2025 17:15:10 +0100 Subject: Switch to new PAC commit --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index b4d82bcec..19d1c7174 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -23,7 +23,7 @@ embassy-time = "0.5.0" embassy-time-driver = "0.2.1" embedded-io = "0.6" heapless = "0.8" -mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "f0281344c605ab24c38979553b41a1655c50625c", version = "0.1.0" } +mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "3ab4c868f75a9240bb8fdce24982d34f2273aabf", version = "0.1.0" } paste = "1.0.15" embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [ -- cgit From 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"de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc" +dependencies = [ + "vcell", +] -- cgit From 302702dd58c53a50aa84892eac79a5300c247752 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 13 Nov 2025 17:42:42 +0100 Subject: Tweak CI workflows for embassy-mcxa --- .github/workflows/cargo-vet-pr-comment.yml | 2 +- .github/workflows/check.yml | 13 +++++++++---- .github/workflows/nostd.yml | 11 +++-------- .github/workflows/rolling.yml | 4 ++++ 4 files changed, 17 insertions(+), 13 deletions(-) diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml index 4dec76822..fafb21641 100644 --- a/.github/workflows/cargo-vet-pr-comment.yml +++ b/.github/workflows/cargo-vet-pr-comment.yml @@ -134,4 +134,4 @@ jobs: comment-tag: [cargo-vet] --> - edit-mode: replace \ No newline at end of file + edit-mode: replace diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index 5d4271145..3f116426f 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -34,7 +34,7 @@ jobs: strategy: fail-fast: false matrix: - workdir: [ ".", "examples/rt633", "examples/rt685s-evk",] + workdir: [ ".", "examples",] steps: - uses: actions/checkout@v5 @@ -45,6 +45,7 @@ jobs: uses: dtolnay/rust-toolchain@nightly with: components: rustfmt + targets: thumbv8m.main-none-eabihf - name: cargo fmt --check run: cargo fmt --check @@ -75,6 +76,7 @@ jobs: with: toolchain: ${{ matrix.toolchain }} components: clippy + targets: thumbv8m.main-none-eabihf - name: cargo clippy working-directory: ${{ matrix.workdir }} @@ -110,6 +112,8 @@ jobs: - name: Install nightly uses: dtolnay/rust-toolchain@nightly + with: + targets: thumbv8m.main-none-eabihf - name: cargo doc run: | @@ -136,9 +140,7 @@ jobs: with: toolchain: stable components: clippy - - - name: rustup target add thumbv8m.main-none-eabihf - run: rustup target add thumbv8m.main-none-eabihf + targets: thumbv8m.main-none-eabihf - name: cargo hack run: cargo hack --feature-powerset check @@ -156,6 +158,8 @@ jobs: - name: Install stable uses: dtolnay/rust-toolchain@stable + with: + targets: thumbv8m.main-none-eabihf - name: cargo install cargo-deny uses: EmbarkStudios/cargo-deny-action@v2 @@ -199,6 +203,7 @@ jobs: uses: dtolnay/rust-toolchain@master with: toolchain: ${{ matrix.msrv }} + targets: thumbv8m.main-none-eabihf - name: cargo +${{ matrix.msrv }} check run: | diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml index fbada0516..6083577da 100644 --- a/.github/workflows/nostd.yml +++ b/.github/workflows/nostd.yml @@ -20,10 +20,6 @@ jobs: runs-on: ubuntu-latest name: ${{ matrix.target }} - strategy: - matrix: - target: [thumbv8m.main-none-eabihf] - steps: - uses: actions/checkout@v5 with: @@ -31,13 +27,12 @@ jobs: - name: Install stable uses: dtolnay/rust-toolchain@stable - - - name: rustup target add ${{ matrix.target }} - run: rustup target add ${{ matrix.target }} + with: + targets: thumbv8m.main-none-eabihf - name: Show variable run: echo ${{ env.TOKEN }} - name: cargo check run: | - cargo check --target ${{ matrix.target }} --all-features --locked + cargo check --target thumbv8m.main-none-eabihf --all-features --locked diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml index 4c9e9718a..386c0df5c 100644 --- a/.github/workflows/rolling.yml +++ b/.github/workflows/rolling.yml @@ -25,6 +25,9 @@ jobs: submodules: true - name: Install stable uses: dtolnay/rust-toolchain@stable + with: + targets: thumbv8m.main-none-eabihf + - name: cargo install cargo-hack uses: taiki-e/install-action@cargo-hack - name: cargo check @@ -62,6 +65,7 @@ jobs: uses: dtolnay/rust-toolchain@master with: toolchain: ${{ matrix.msrv }} + targets: thumbv8m.main-none-eabihf - name: cargo +${{ matrix.msrv }} check run: | cargo update -- cgit From 9387d3352a39a903757860568e41890b022c990f Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 13 Nov 2025 08:52:19 -0800 Subject: Install cargo-hack before attempting to use it --- .github/workflows/check.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index 3f116426f..7aec2f489 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -142,6 +142,9 @@ jobs: components: clippy targets: thumbv8m.main-none-eabihf + - name: cargo install cargo-hack + uses: taiki-e/install-action@cargo-hack + - name: cargo hack run: cargo hack --feature-powerset check -- cgit From 357a538e8d5f69c8c0aeacfd416f1ad99b0907d3 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 13 Nov 2025 17:50:11 +0100 Subject: autofix clippy lints --- src/adc.rs | 4 ++-- src/lpuart/buffered.rs | 22 +++++++++++++--------- src/lpuart/mod.rs | 18 +++++++----------- src/ostimer.rs | 6 ++++++ src/rtc.rs | 4 ++-- src/uart.rs | 8 +++++++- 6 files changed, 37 insertions(+), 25 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index d456971f7..655bf934f 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -228,7 +228,7 @@ impl Adc { let step = 1.0 / (1u32 << shift) as f32; let tmp = (gain_adjustment / step) as u32; gcra_array[i - 1] = tmp; - gain_adjustment = gain_adjustment - tmp as f32 * step; + gain_adjustment -= tmp as f32 * step; } for i in (1..=17).rev() { @@ -244,7 +244,7 @@ impl Adc { while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} let mut gcca = adc.gcc0().read().gain_cal().bits() as u32; - if gcca & (((0xFFFF >> 0) + 1) >> 1) != 0 { + if gcca & ((0xFFFF + 1) >> 1) != 0 { gcca |= !0xFFFF; } diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index 0413fed8e..21b86ada9 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -24,6 +24,12 @@ pub struct State { initialized: AtomicBool, } +impl Default for State { + fn default() -> Self { + Self::new() + } +} + impl State { /// Create a new state instance pub const fn new() -> Self { @@ -612,16 +618,14 @@ impl crate::interrupt::typelevel::Handler for Buffere } // Handle transmission complete - if ctrl.tcie().is_enabled() { - if regs.stat().read().tc().is_complete() { - state.tx_done.store(true, Ordering::Release); - state.tx_waker.wake(); + if ctrl.tcie().is_enabled() && regs.stat().read().tc().is_complete() { + state.tx_done.store(true, Ordering::Release); + state.tx_waker.wake(); - // Disable TC interrupt - cortex_m::interrupt::free(|_| { - regs.ctrl().modify(|_, w| w.tcie().disabled()); - }); - } + // Disable TC interrupt + cortex_m::interrupt::free(|_| { + regs.ctrl().modify(|_, w| w.tcie().disabled()); + }); } } } diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index bed10bdb0..854136144 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -105,8 +105,8 @@ mod gpio { impl GpioPin for super::lib::peripherals::$pin {} - impl Into for super::lib::peripherals::$pin { - fn into(self) -> AnyPin { + impl From for AnyPin { + fn from(val: super::lib::peripherals::$pin) -> Self { AnyPin } } @@ -242,7 +242,7 @@ pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result // Configure BAUD register regs.baud().modify(|_, w| unsafe { // Clear and set OSR - w.osr().bits((osr - 1) as u8); + w.osr().bits((osr - 1)); // Clear and set SBR w.sbr().bits(sbr); // Set BOTHEDGE if OSR is between 4 and 7 @@ -305,9 +305,9 @@ pub fn configure_fifo(regs: Regs, config: &Config) { // Configure WATER register for FIFO watermarks regs.water().write(|w| unsafe { w.rxwater() - .bits(config.rx_fifo_watermark as u8) + .bits(config.rx_fifo_watermark) .txwater() - .bits(config.tx_fifo_watermark as u8) + .bits(config.tx_fifo_watermark) }); // Enable TX/RX FIFOs @@ -377,7 +377,7 @@ pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> // Try OSR values from 4 to 32 for osr_temp in 4u8..=32u8 { // Calculate SBR: (srcClock_Hz * 2 / (baudRate * osr) + 1) / 2 - let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32) + 1) / 2; + let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32)).div_ceil(2); let sbr_temp = if sbr_calc == 0 { 1 @@ -390,11 +390,7 @@ pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> // Calculate actual baud rate let calculated_baud = src_clock_hz / (osr_temp as u32 * sbr_temp as u32); - let temp_diff = if calculated_baud > baudrate { - calculated_baud - baudrate - } else { - baudrate - calculated_baud - }; + let temp_diff = calculated_baud.abs_diff(baudrate); if temp_diff <= baud_diff { baud_diff = temp_diff; diff --git a/src/ostimer.rs b/src/ostimer.rs index a4cab6970..8bc68389a 100644 --- a/src/ostimer.rs +++ b/src/ostimer.rs @@ -151,6 +151,12 @@ pub struct Alarm<'d> { _phantom: core::marker::PhantomData<&'d mut ()>, } +impl<'d> Default for Alarm<'d> { + fn default() -> Self { + Self::new() + } +} + impl<'d> Alarm<'d> { /// Create a new alarm instance pub fn new() -> Self { diff --git a/src/rtc.rs b/src/rtc.rs index d62da1f0a..afd46610e 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -102,7 +102,7 @@ pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { days -= days_in_year; year += 1; - days_in_year = if year % 4 == 0 { + days_in_year = if year.is_multiple_of(4) { DAYS_IN_A_YEAR + 1 } else { DAYS_IN_A_YEAR @@ -110,7 +110,7 @@ pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { } let mut days_per_month = [0u8, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31]; - if year % 4 == 0 { + if year.is_multiple_of(4) { days_per_month[2] = 29; } diff --git a/src/uart.rs b/src/uart.rs index 3209a318d..cd504a6c6 100644 --- a/src/uart.rs +++ b/src/uart.rs @@ -118,7 +118,7 @@ impl Uart { StopBits::Two => w.sbns().two(), }; // OSR field encodes (osr-1); use raw bits to avoid a long match on all variants - let raw_osr = osr.saturating_sub(1) as u8; + let raw_osr = osr.saturating_sub(1); unsafe { w.osr().bits(raw_osr).sbr().bits(sbr) } }); // 3) CTRL baseline and parity @@ -195,6 +195,12 @@ pub struct RingBuffer { count: usize, } +impl Default for RingBuffer { + fn default() -> Self { + Self::new() + } +} + impl RingBuffer { pub const fn new() -> Self { Self { -- cgit From 306e55819656eeb41c69f2d5625c46419f0534c4 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 13 Nov 2025 18:02:24 +0100 Subject: Manually fix clippy lints --- src/interrupt.rs | 4 ++++ src/lib.rs | 3 +++ src/lpuart/buffered.rs | 1 + src/lpuart/mod.rs | 5 +++-- src/rtc.rs | 25 ++++++++++++++++++------- src/uart.rs | 4 ++++ 6 files changed, 33 insertions(+), 9 deletions(-) diff --git a/src/interrupt.rs b/src/interrupt.rs index 09d7acbef..134ff03fd 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -2,6 +2,10 @@ //! Type-level interrupt traits and bindings are provided by the //! `embassy_hal_internal::interrupt_mod!` macro via the generated module below. +// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs +// are complete prior to release. +#![allow(clippy::missing_safety_doc)] + mod generated { embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1); } diff --git a/src/lib.rs b/src/lib.rs index fe27aadba..9899564d8 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,4 +1,7 @@ #![no_std] +// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs +// are complete prior to release. +#![allow(clippy::missing_safety_doc)] pub mod clocks; // still provide clock helpers pub mod gpio; diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index 21b86ada9..a617c10a5 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -110,6 +110,7 @@ impl<'a> BufferedLpuart<'a> { } /// Create a new buffered LPUART with flexible pin configuration + #[allow(clippy::too_many_arguments)] pub fn new_with_pins( _inner: Peri<'a, T>, tx_pin: Option>>, diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 854136144..35b531421 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -106,7 +106,8 @@ mod gpio { impl GpioPin for super::lib::peripherals::$pin {} impl From for AnyPin { - fn from(val: super::lib::peripherals::$pin) -> Self { + // TODO: AJM: any reason we aren't using $pin? + fn from(_val: super::lib::peripherals::$pin) -> Self { AnyPin } } @@ -242,7 +243,7 @@ pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result // Configure BAUD register regs.baud().modify(|_, w| unsafe { // Clear and set OSR - w.osr().bits((osr - 1)); + w.osr().bits(osr - 1); // Clear and set SBR w.sbr().bits(sbr); // Set BOTHEDGE if OSR is between 4 and 7 diff --git a/src/rtc.rs b/src/rtc.rs index afd46610e..facb9cf8c 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -109,18 +109,29 @@ pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { }; } - let mut days_per_month = [0u8, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31]; - if year.is_multiple_of(4) { - days_per_month[2] = 29; - } + let days_per_month = [ + 31, + if year.is_multiple_of(4) { 29 } else { 28 }, + 31, + 30, + 31, + 30, + 31, + 31, + 30, + 31, + 30, + 31, + ]; let mut month = 1; - for m in 1..=12 { - if days <= days_per_month[m] as u32 { + for (m, month_days) in days_per_month.iter().enumerate() { + let m = m + 1; + if days <= *month_days as u32 { month = m; break; } else { - days -= days_per_month[m] as u32; + days -= *month_days as u32; } } diff --git a/src/uart.rs b/src/uart.rs index cd504a6c6..3705959d3 100644 --- a/src/uart.rs +++ b/src/uart.rs @@ -1,6 +1,10 @@ //! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering. //! WARNING: This is a narrow implementation only for debug console (115200 8N1). +// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs +// are complete prior to release. +#![allow(clippy::missing_safety_doc)] + use core::cell::RefCell; use cortex_m::interrupt::Mutex; -- cgit From f1636f3913e06f84ec2a097924bd7154b9bb1a3c Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 13 Nov 2025 18:04:06 +0100 Subject: Bump msrv --- .github/workflows/check.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index 7aec2f489..8e05f5c5d 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -180,7 +180,7 @@ jobs: strategy: fail-fast: false matrix: - msrv: ["1.90"] # We're relying on namespaced-features, which + msrv: ["1.91"] # We're relying on namespaced-features, which # was released in 1.60 # # We also depend on `fixed' which requires rust @@ -195,6 +195,8 @@ jobs: # embassy upstream switched to rust 1.85 # # unsigned_is_multiple_of requires 1.90, else we get clippy warnings + # + # mcxa-pac@0.1.0 requires rustc 1.91 name: ubuntu / ${{ matrix.msrv }} steps: -- cgit From 1a37ff58ac46bba0ea2c7f3bd26e830b95fc2132 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 13 Nov 2025 09:15:46 -0800 Subject: chore(deps): bump actions/download-artifact from 4 to 6 (#10) Bumps [actions/download-artifact](https://github.com/actions/download-artifact) from 4 to 6. - [Release notes](https://github.com/actions/download-artifact/releases) - [Commits](https://github.com/actions/download-artifact/compare/v4...v6) --- updated-dependencies: - dependency-name: actions/download-artifact dependency-version: '6' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- .github/workflows/cargo-vet-pr-comment.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml index fafb21641..66f27ceab 100644 --- a/.github/workflows/cargo-vet-pr-comment.yml +++ b/.github/workflows/cargo-vet-pr-comment.yml @@ -31,7 +31,7 @@ jobs: if: github.event.workflow_run.event == 'pull_request' steps: - name: 'Download artifact' - uses: actions/download-artifact@v4 + uses: actions/download-artifact@v6 with: github-token: ${{ secrets.GITHUB_TOKEN }} name: pr -- cgit From f53d4975774dd0c6009ad72692f394dca1083c0b Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 13 Nov 2025 09:52:32 -0800 Subject: Add status badges (#14) --- .github/workflows/rolling.yml | 18 ++---------------- README.md | 4 ++++ 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml index 386c0df5c..1d93cfe25 100644 --- a/.github/workflows/rolling.yml +++ b/.github/workflows/rolling.yml @@ -40,22 +40,8 @@ jobs: strategy: fail-fast: false matrix: - msrv: ["1.85"] # We're relying on namespaced-features, which - # was released in 1.60 - # - # We also depend on `fixed' which requires rust - # 1.71 - # - # Additionally, we depend on embedded-hal-async - # which requires 1.75 - # - # embassy-time requires 1.79 due to - # collapse_debuginfo - # - # embassy upstream switched to rust 1.83 - # - # embedded-services (storage bus) dependency - # requires 1.85 + msrv: ["1.91"] + name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }}) steps: - uses: actions/checkout@v5 diff --git a/README.md b/README.md index 8a93b5f4a..86c0413f0 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,9 @@ # Embassy MCXA276 HAL +[![check](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml) +[![no-std](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml) +[![rolling](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml) + A Hardware Abstraction Layer (HAL) for the NXP MCXA276 microcontroller using the Embassy async framework. This HAL provides safe, idiomatic Rust interfaces for GPIO, UART, and OSTIMER peripherals. -- cgit From f4b8ae36bec40a15bedd3c0493e4822f9c5238dd Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 13 Nov 2025 09:58:21 -0800 Subject: Remove a lot of text from README.md (#15) New text will be added as necessary. Co-authored-by: Felipe Balbi --- README.md | 357 +------------------------------------------------------------- 1 file changed, 2 insertions(+), 355 deletions(-) diff --git a/README.md b/README.md index 86c0413f0..6e7d61c0e 100644 --- a/README.md +++ b/README.md @@ -1,366 +1,13 @@ -# Embassy MCXA276 HAL +# Embassy MCXA256 HAL [![check](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml) [![no-std](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml) [![rolling](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml) -A Hardware Abstraction Layer (HAL) for the NXP MCXA276 microcontroller +A Hardware Abstraction Layer (HAL) for the NXP MCXA256 microcontroller using the Embassy async framework. This HAL provides safe, idiomatic Rust interfaces for GPIO, UART, and OSTIMER peripherals. -## Prerequisites - -### Ubuntu/Debian Setup - -```bash -# Install Rust toolchain -curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -source ~/.cargo/env - -# Add target for MCXA276 (ARM Cortex-M33) -rustup target add thumbv8m.main-none-eabihf - -# Install required tools -sudo apt update -sudo apt install -y gdb-multiarch curl wget - -# Install probe-rs for running and debugging -cargo install probe-rs --features cli -``` - -### Windows Setup - -- Install Rust via https://rustup.rs (default options are fine) -- Add the MCXA276 target: - ```powershell - rustup target add thumbv8m.main-none-eabihf - ``` -- Install probe-rs CLI (we will use it directly; no GDB required): - ```powershell - cargo install probe-rs --features cli - ``` -- Install a serial terminal (e.g., Tera Term): https://ttssh2.osdn.jp/ -- USB drivers: Windows 10/11 usually picks up the board as a USB CDC device automatically (COM port) - -### Hardware Requirements - -- NXP FRDM-MCXA276 development board -- Debug probe (CMSIS-DAP compatible) -- USB cable for power and programming - -## Examples - -This HAL includes several examples demonstrating different peripherals: - -### GPIO Examples - -#### `blink` -Blinks an LED connected to GPIO pin. Demonstrates basic GPIO output operations. - -### UART Examples - -#### `hello` -Interactive UART2 demo: prints a banner and supports `help`, `echo `, `hex `. - -### OSTIMER Examples - -#### `ostimer_alarm` - -Demonstrates setting and waiting for OSTIMER alarms. - -#### `ostimer_async` -Shows asynchronous OSTIMER operations with Embassy's async runtime. - -#### `ostimer_counter` -Demonstrates OSTIMER counter functionality. - -#### `ostimer_race_test` -Advanced example testing OSTIMER race conditions and synchronization. - -### RTC Example - -#### `rtc_alarm` -Demonstrates how to enable and use the RTC to generate an interrupt after 10seconds. - -## Build and Run - -### Using probe-rs - -All examples require specifying your debug probe. First, find your probe ID: - -```bash -probe-rs list -``` - -Then run examples with your probe ID (replace `1fc9:0143:H3AYDQVQMTROB` with your actual probe): - -```bash -# GPIO blink example -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "gpio ostimer0" --example blink - - - -# UART hello example -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example hello - -# OSTIMER examples -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_async -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_counter -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_race_test - -# RTC example -PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 rtc0" --example rtc_alarm -``` - -**Note:** All examples run from RAM, not flash memory. They are loaded directly into RAM for faster development iteration. - -**Important:** After pressing the RESET button on the board, the first `cargo run` attempt may fail with a connection error. This is expected - simply run the command again and it will work. The run.sh script now properly sets the Vector Table Offset Register (VTOR) to point to the RAM-based vector table, ensuring the correct stack pointer and reset vector are used. - -```console -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink - Finished `release` profile [optimized + debuginfo] target(s) in 0.07s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` -probe-rs gdb server failed to connect to target. Log: ------ probe-rs gdb log ----- - Error: Connecting to the chip was unsuccessful. - - Caused by: - 0: An ARM specific error occurred. - 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. - 2: Failed to read register DRW at address 0xd0c - 3: An error occurred in the communication with an access port or debug port. - 4: Target device responded with a FAULT response to the request. -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink - Finished `release` profile [optimized + debuginfo] target(s) in 0.02s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink` -``` - -### Additional UART Examples - -#### `uart_interrupt` -Interrupt-driven UART2 echo. Type in the serial terminal; each byte is echoed back from the IRQ handler path. - -#### `lpuart_polling` -Blocking TX/RX echo over UART2 using the simple polling driver. - -#### `lpuart_buffered` -Async buffered driver with separate TX/RX tasks; echoes typed characters in chunks. - -Pins: UART2 TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. - -### ADC Examples - -#### `adc_polling` -Configures ADC1 channel A8 (pin P1_10) and prints conversion values to UART2 periodically. - -#### `adc_interrupt` -Triggers a conversion and signals completion via ADC1 interrupt, printing a notification on UART2. - -```console -0x20002040 in ?? () -Supported Commands: - - info - print session information - reset - reset target - reset halt - reset target and halt afterwards - -Loading section .vector_table, size 0x224 lma 0x20000000 -Loading section .text, size 0x97e lma 0x20000224 -Loading section .Reset, size 0x58 lma 0x20000ba4 -Loading section .rodata, size 0x28 lma 0x20000bfc -Start address 0x20000ba4, load size 3106 -Transfer rate: 13 KB/sec, 776 bytes/write. -``` - -then I see the LED blinking. I press CTRL+C to exit. It will show me ^C - -```console -Program received signal SIGINT, Interrupt. -0x20000880 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 -106 asm!("wfe"); -[Inferior 1 (process 1) detached] -Program loaded and started (no reset) -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ \ - -Then I press RESET again and I want to run another example, like ostimer_alarm. I open the console using sudo picocom -b 115200 /dev/ttyACM0 and I start running the example: - -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm - Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` -probe-rs gdb server failed to connect to target. Log: ------ probe-rs gdb log ----- - Error: Connecting to the chip was unsuccessful. - - Caused by: - 0: An ARM specific error occurred. - 1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }. - 2: Failed to read register DRW at address 0xd0c - 3: An error occurred in the communication with an access port or debug port. - 4: Target device responded with a FAULT response to the request. -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm - Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s - Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm` -0x20002040 in core::panicking::panic_const::panic_const_mul_overflow () at library/core/src/panicking.rs:175 -warning: 175 library/core/src/panicking.rs: No such file or directory -Supported Commands: - - info - print session information - reset - reset target - reset halt - reset target and halt afterwards - -Loading section .vector_table, size 0x224 lma 0x20000000 -Loading section .text, size 0x2226 lma 0x20000224 -Loading section .Reset, size 0x58 lma 0x2000244c -Loading section .rodata, size 0x6dc lma 0x200024a4 -Start address 0x2000244c, load size 11134 -Transfer rate: 16 KB/sec, 1855 bytes/write. -``` - -I can see in the console - -```console -OSTIMER Alarm Example -Scheduling alarm for 2 seconds... -Alarm scheduled successfully -Alarm expired! Callback executed. -Scheduling another alarm for 3 seconds... -Alarm scheduled. Waiting 1 second then canceling... -Alarm canceled -Alarm was successfully canceled -Example complete -``` - -then I press CTRL+C to stop running - -```console -^C -Program received signal SIGINT, Interrupt. -0x20000e64 in embassy_executor::arch::thread::Executor::run (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106 -106 asm!("wfe"); -[Inferior 1 (process 1) detached] -Program loaded and started (no reset) -smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ -``` - -### Windows: Running examples (RAM, no RTT/defmt) - -Important: On Windows, do not use `cargo run` because `.cargo/config.toml` sets a Linux-only runner (`./run.sh`). Instead, use `probe-rs run` directly. - -1) Find your probe and COM port -- List probes: - - ```console - probe-rs list - ``` -- If multiple probes are attached, set the specific one (replace with your ID): - - ```console - $env:PROBE_RS_PROBE = "1366:0101:000600110607" - ``` - -- Check Windows Device Manager → Ports (COM & LPT) for the board’s COM port. - -2) Build the example - -```console -cargo build --example hello --features "lpuart2" -``` - -3) Run from RAM with probe-rs - -```console -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/hello -``` -You will see a short probe-rs warning like "unknown variant, try to set watch point"; it’s harmless. - -4) View output in Tera Term -- Open Tera Term, select the board’s COMx port, 115200 8N1 -- Expected behavior per example: - - hello: prints a banner; simple UART output - - lpuart_polling / lpuart_buffered / uart_interrupt: echo typed characters - - adc_polling: prints ADC values periodically (ADC1 channel A8 on P1_10) - - adc_interrupt: prints "*** ADC interrupt TRIGGERED! ***" upon conversion completion - - blink: LED on PIO3_18 blinks "SOS" pattern - - rtc_alarm: schedules, cancels and reports alarm events on UART - -Notes -- All examples run from RAM (not flashed). Reset clears the program. -- If the first attempt after a reset fails to connect, just run the command again. -- UART2 pins: TX=P2_2, RX=P2_3 (ALT3), 115200 8N1. - -Quick commands for other examples: - -```console -# Build -cargo build --example blink --features "gpio ostimer0" -cargo build --example lpuart_polling --features "lpuart2 ostimer0" -cargo build --example lpuart_buffered --features "lpuart2 ostimer0" -cargo build --example uart_interrupt --features "lpuart2 ostimer0" -cargo build --example rtc_alarm --features "lpuart2 rtc0" -cargo build --example adc_polling --features "adc1 lpuart2" -cargo build --example adc_interrupt --features "adc1 lpuart2" - -# Run (RAM) -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/blink -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_polling -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_buffered -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/uart_interrupt -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/rtc_alarm -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_polling -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_interrupt -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_async -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_counter -probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_race_test -``` - -How I tested on Windows -- Windows 11; Rust stable; probe-rs 0.29.x -- Built each example as above; ran with `probe-rs run` (RAM execution) -- Observed UART output in Tera Term at 115200 8N1; all examples behaved as expected -- No RTT/defmt used; purely UART or LED observation - -### Build Only - -To build without running: - -```console -cargo build --features "gpio ostimer0" --example blink -cargo build --features "lpuart2 ostimer0" --example hello -cargo build --features "lpuart2 ostimer0" --example ostimer_alarm -cargo build --features "lpuart2 rtc0" --example rtc_alarm -# etc. -``` - -## Development Notes - -### Critical Fix: MCXA276 Interrupt Vector Table - - -Update (SVD 25.06.00, mcxa-pac a9dd33): No manual PAC edits are required anymore. OS_EVENT and WAKETIMER0 are present and the vector table is correct. The section below is kept for historical context. -**Problem:** The OSTIMER examples crashed during interrupt handling with a hardfault (SP=0x00000000). Investigation revealed the OS_EVENT interrupt vector was NULL in the vector table, causing the CPU to jump to address 0 when OSTIMER interrupts fired. - -**Root Cause:** The `mcxa276-pac/src/lib.rs` file (generated from the SVD file) was missing the `WAKETIMER0` interrupt handler declaration. This caused the `__INTERRUPTS` array to have an off-by-one error, placing OS_EVENT at IRQ 58 instead of the correct IRQ 57 position. - -**Solution:** Manually edited `mcxa276-pac/src/lib.rs` to add the missing WAKETIMER0 interrupt: - -1. Added `fn WAKETIMER0()` to the `extern "C"` block -2. Fixed the `__INTERRUPTS: [Vector; 122]` array sequence: - - Changed from: `LPTMR0, _reserved, _reserved, OS_EVENT, _reserved, UTICK0, ...` - - Changed to: `LPTMR0, _reserved, OS_EVENT, WAKETIMER0, UTICK0, WWDT0, _reserved, ADC0, ...` -3. Added `WAKETIMER0 = 58` to the `Interrupt` enum - -**Verification:** Binary analysis confirmed OS_EVENT is now at the correct position: -- IRQ 57 = word 73 = offset 0x124 in vector table -- OS_EVENT handler: 0x20000BB1 (verified with `arm-none-eabi-objdump`) - -**Note:** This is likely an issue with the NXP MCXA276.svd file or svd2rust generation. The WAKETIMER0 peripheral exists in the PAC but the interrupt handler was missing. Future regeneration of the PAC from SVD may require reapplying this fix. - -### Warning: Avoid `#[inline(always)]` in Performance-Critical Code - -Using `#[inline(always)]` can cause the Rust compiler to generate incorrect assembly, leading to register corruption or unexpected behavior. For example, in tight polling loops like those in the OSTIMER driver, this attribute may result in invalid instructions that zero registers (e.g., `movs r1, r0` causing r1=0), triggering hardfaults. - ## License This project is licensed under MIT OR Apache-2.0. -- cgit From 77b2c602a60e41c7c977003a6d40367ac285930e Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 13 Nov 2025 13:17:44 -0800 Subject: Move examples to a package of their own (#16) * Move examples to a package of their own * cargo +nightly fmt * Add missing safety doc * cargo clippy examples * fmt again --------- Co-authored-by: Felipe Balbi --- .cargo/config.toml | 19 -- Cargo.lock | 24 +- Cargo.toml | 61 +--- build.rs | 20 -- examples/.cargo/config.toml | 17 + examples/.gitignore | 1 + examples/Cargo.lock | 625 ++++++++++++++++++++++++++++++++++ examples/Cargo.toml | 21 ++ examples/adc_interrupt.rs | 89 ----- examples/adc_polling.rs | 79 ----- examples/blink.rs | 84 ----- examples/build.rs | 20 ++ examples/common/mod.rs | 45 --- examples/hello.rs | 114 ------- examples/lpuart_buffered.rs | 77 ----- examples/lpuart_polling.rs | 53 --- examples/memory.x | 5 + examples/ostimer_alarm.rs | 111 ------ examples/ostimer_async.rs | 57 ---- examples/ostimer_counter.rs | 128 ------- examples/ostimer_race_test.rs | 396 --------------------- examples/rtc_alarm.rs | 87 ----- examples/src/bin/adc_interrupt.rs | 86 +++++ examples/src/bin/adc_polling.rs | 76 +++++ examples/src/bin/blink.rs | 78 +++++ examples/src/bin/hello.rs | 111 ++++++ examples/src/bin/lpuart_buffered.rs | 76 +++++ examples/src/bin/lpuart_polling.rs | 51 +++ examples/src/bin/ostimer_alarm.rs | 106 ++++++ examples/src/bin/ostimer_async.rs | 52 +++ examples/src/bin/ostimer_counter.rs | 125 +++++++ examples/src/bin/ostimer_race_test.rs | 393 +++++++++++++++++++++ examples/src/bin/rtc_alarm.rs | 84 +++++ examples/src/bin/uart_interrupt.rs | 66 ++++ examples/src/common/mod.rs | 45 +++ examples/src/lib.rs | 63 ++++ examples/uart_interrupt.rs | 69 ---- memory.x | 10 - src/lib.rs | 44 +-- 39 files changed, 2127 insertions(+), 1541 deletions(-) delete mode 100644 .cargo/config.toml delete mode 100644 build.rs create mode 100644 examples/.cargo/config.toml create mode 100644 examples/.gitignore create mode 100644 examples/Cargo.lock create mode 100644 examples/Cargo.toml delete mode 100644 examples/adc_interrupt.rs delete mode 100644 examples/adc_polling.rs delete mode 100644 examples/blink.rs create mode 100644 examples/build.rs delete mode 100644 examples/common/mod.rs delete mode 100644 examples/hello.rs delete mode 100644 examples/lpuart_buffered.rs delete mode 100644 examples/lpuart_polling.rs create mode 100644 examples/memory.x delete mode 100644 examples/ostimer_alarm.rs delete mode 100644 examples/ostimer_async.rs delete mode 100644 examples/ostimer_counter.rs delete mode 100644 examples/ostimer_race_test.rs delete mode 100644 examples/rtc_alarm.rs create mode 100644 examples/src/bin/adc_interrupt.rs create mode 100644 examples/src/bin/adc_polling.rs create mode 100644 examples/src/bin/blink.rs create mode 100644 examples/src/bin/hello.rs create mode 100644 examples/src/bin/lpuart_buffered.rs create mode 100644 examples/src/bin/lpuart_polling.rs create mode 100644 examples/src/bin/ostimer_alarm.rs create mode 100644 examples/src/bin/ostimer_async.rs create mode 100644 examples/src/bin/ostimer_counter.rs create mode 100644 examples/src/bin/ostimer_race_test.rs create mode 100644 examples/src/bin/rtc_alarm.rs create mode 100644 examples/src/bin/uart_interrupt.rs create mode 100644 examples/src/common/mod.rs create mode 100644 examples/src/lib.rs delete mode 100644 examples/uart_interrupt.rs delete mode 100644 memory.x diff --git a/.cargo/config.toml b/.cargo/config.toml deleted file mode 100644 index 3286be01c..000000000 --- a/.cargo/config.toml +++ /dev/null @@ -1,19 +0,0 @@ -[build] -target = "thumbv8m.main-none-eabihf" - -[target.thumbv8m.main-none-eabihf] -runner = "./run.sh" -# Use our custom ram.ld for RAM-execution -rustflags = ["-C", "link-arg=-Tdefmt.x", "-C", "link-arg=-Tram.ld"] - -[alias] -# Build examples with defmt+RTT and LPUART2 enabled -build-defmt = ["build", "--features", "defmt defmt-rtt lpuart2", "--examples"] -# Blocking run (uses run.sh). Good for one-terminal flash+run. -run-defmt = ["run", "--features", "defmt defmt-rtt lpuart2", "--example", "hello"] -# Non-blocking flash to RAM via J-Link; frees probe for RTT attach -flash-nb = ["!./tools/run_jlink_noblock.sh", "target/thumbv8m.main-none-eabihf/debug/examples/hello", "1366:0101:000600110607", "MCXA276", "500"] -# Attach-only viewer that decodes defmt over RTT using J-Link -# Requires PROBE_RS_PROBE exported (or it will prompt) -defmt-attach = ["embed", "--features", "defmt defmt-rtt lpuart2", "--example", "hello"] - diff --git a/Cargo.lock b/Cargo.lock index 953a71ee0..e9f4d3165 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -147,16 +147,6 @@ dependencies = [ "thiserror", ] -[[package]] -name = "defmt-rtt" -version = "1.1.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "93d5a25c99d89c40f5676bec8cefe0614f17f0f40e916f98e345dae941807f9e" -dependencies = [ - "critical-section", - "defmt", -] - [[package]] name = "document-features" version = "0.2.12" @@ -232,14 +222,13 @@ dependencies = [ ] [[package]] -name = "embassy-mcxa276" +name = "embassy-mcxa" version = "0.1.0" dependencies = [ "cortex-m", "cortex-m-rt", "critical-section", "defmt", - "defmt-rtt", "embassy-embedded-hal", "embassy-executor", "embassy-hal-internal", @@ -255,7 +244,6 @@ dependencies = [ "heapless", "mcxa-pac", "nb 1.1.0", - "panic-probe", "paste", ] @@ -446,16 +434,6 @@ dependencies = [ "autocfg", ] -[[package]] -name = "panic-probe" -version = "1.0.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fd402d00b0fb94c5aee000029204a46884b1262e0c443f166d86d2c0747e1a1a" -dependencies = [ - "cortex-m", - "defmt", -] - [[package]] name = "paste" version = "1.0.15" diff --git a/Cargo.toml b/Cargo.toml index 19d1c7174..3913104fc 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,15 +1,12 @@ [package] -name = "embassy-mcxa276" +name = "embassy-mcxa" version = "0.1.0" edition = "2021" license = "MIT OR Apache-2.0" -description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA276" -keywords = ["embedded", "hal", "nxp", "mcxa276", "embassy"] +description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA series of MCUs" +keywords = ["embedded", "hal", "nxp", "mcxa", "embassy"] categories = ["embedded", "hardware-support", "no-std"] -[lib] -name = "embassy_mcxa276" - [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m-rt = { version = "0.7", features = ["device"] } @@ -35,11 +32,6 @@ embedded-hal-nb = { version = "1.0" } embedded-io-async = { version = "0.6.1" } nb = "1.1.0" -[dev-dependencies] -defmt = "1.0" -defmt-rtt = "1.0" -panic-probe = { version = "1.0", features = ["print-defmt"] } - [features] default = [] @@ -50,50 +42,3 @@ defmt = ["dep:defmt"] rt = [] unstable-pac = [] - -[[example]] -name = "hello" - -[[example]] -name = "blink" - -[[example]] -name = "uart_interrupt" - -[[example]] -name = "ostimer_alarm" - -[[example]] -name = "ostimer_async" - -[[example]] -name = "ostimer_counter" - -[[example]] -name = "ostimer_race_test" - -[[example]] -name = "lpuart_polling" - -[[example]] -name = "lpuart_buffered" - -[[example]] -name = "rtc_alarm" - -[[example]] -name = "adc_polling" - -[[example]] -name = "adc_interrupt" - -[profile.release] -debug = 2 -lto = true -opt-level = "s" - -[profile.dev] -debug = 2 -opt-level = 1 - - diff --git a/build.rs b/build.rs deleted file mode 100644 index 645843590..000000000 --- a/build.rs +++ /dev/null @@ -1,20 +0,0 @@ -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; - -fn main() { - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - - // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH" - // cortex-m-rt expects FLASH for code, RAM for data/bss/stack - // Both are in RAM, but separated to satisfy cortex-m-rt's expectations - // MCXA276 has 128KB RAM total - File::create(out.join("memory.x")) - .unwrap() - .write_all(b"/* MCXA276 RAM-execution: FLASH region holds code, RAM region for data/stack */\nMEMORY { FLASH : ORIGIN = 0x20000000, LENGTH = 64K\n RAM : ORIGIN = 0x20010000, LENGTH = 64K }\n") - .unwrap(); - - println!("cargo:rustc-link-search={}", out.display()); - println!("cargo:rerun-if-changed=memory.x"); -} diff --git a/examples/.cargo/config.toml b/examples/.cargo/config.toml new file mode 100644 index 000000000..ecb11be64 --- /dev/null +++ b/examples/.cargo/config.toml @@ -0,0 +1,17 @@ +[target.thumbv8m.main-none-eabihf] +runner = 'probe-rs run --chip MCXA276 --preverify --verify' + +rustflags = [ + "-C", "linker=flip-link", + "-C", "link-arg=-Tlink.x", + "-C", "link-arg=-Tdefmt.x", + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", +] + +[build] +target = "thumbv8m.main-none-eabihf" # Cortex-M33 + +[env] +DEFMT_LOG = "trace" diff --git a/examples/.gitignore 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"../", features = ["defmt", "rt", "unstable-pac"] } +embassy-sync = "0.7.2" +embassy-time = "0.5.0" +embassy-time-driver = "0.2.1" +embedded-io-async = "0.6.1" +heapless = "0.9.2" +panic-probe = { version = "1.0", features = ["print-defmt"] } diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs deleted file mode 100644 index dc82cfd30..000000000 --- a/examples/adc_interrupt.rs +++ /dev/null @@ -1,89 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; -use hal::uart; -use mcxa_pac::adc1::cfg::{Pwrsel, Refsel}; -use mcxa_pac::adc1::cmdl1::{Adch, Mode}; -use mcxa_pac::adc1::ctrl::CalAvgs; -use mcxa_pac::adc1::tctrl::Tcmd; -use {cortex_m, embassy_mcxa276 as hal}; -mod common; - -use hal::{bind_interrupts, InterruptExt}; -use {defmt_rtt as _, panic_probe as _}; - -bind_interrupts!(struct Irqs { - ADC1 => hal::adc::AdcHandler; -}); - -#[used] -#[no_mangle] -static KEEP_ADC: unsafe extern "C" fn() = ADC1; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - unsafe { - common::init_uart2(hal::pac()); - } - - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); - - uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); - - unsafe { - common::init_adc(hal::pac()); - } - - let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - }; - let adc = hal::adc::Adc::::new(p.ADC1, adc_config); - - adc.do_offset_calibration(); - adc.do_auto_calibration(); - - let mut conv_command_config = adc.get_default_conv_command_config(); - conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; - conv_command_config.conversion_resolution_mode = Mode::Data16Bits; - adc.set_conv_command_config(1, &conv_command_config); - - let mut conv_trigger_config = adc.get_default_conv_trigger_config(); - conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; - conv_trigger_config.enable_hardware_trigger = false; - adc.set_conv_trigger_config(0, &conv_trigger_config); - - uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); - - adc.enable_interrupt(0x1); - - unsafe { - hal::interrupt::ADC1.enable(); - } - - unsafe { - cortex_m::interrupt::enable(); - } - - loop { - adc.do_software_trigger(1); - while !adc.is_interrupt_triggered() { - // Wait until the interrupt is triggered - } - uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); - //TBD need to print the value - } -} diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs deleted file mode 100644 index 4b5f9422d..000000000 --- a/examples/adc_polling.rs +++ /dev/null @@ -1,79 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; -use hal::uart; -use mcxa_pac::adc1::cfg::{Pwrsel, Refsel}; -use mcxa_pac::adc1::cmdl1::{Adch, Mode}; -use mcxa_pac::adc1::ctrl::CalAvgs; -use mcxa_pac::adc1::tctrl::Tcmd; - -mod common; - -use core::fmt::Write; - -use heapless::String; -use {defmt_rtt as _, panic_probe as _}; - -const G_LPADC_RESULT_SHIFT: u32 = 0; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - unsafe { - common::init_uart2(hal::pac()); - } - - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); - - uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n"); - - unsafe { - common::init_adc(hal::pac()); - } - - let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - }; - let adc = hal::adc::Adc::::new(p.ADC1, adc_config); - - adc.do_offset_calibration(); - adc.do_auto_calibration(); - - let mut conv_command_config = adc.get_default_conv_command_config(); - conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; - conv_command_config.conversion_resolution_mode = Mode::Data16Bits; - adc.set_conv_command_config(1, &conv_command_config); - - let mut conv_trigger_config = adc.get_default_conv_trigger_config(); - conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; - conv_trigger_config.enable_hardware_trigger = false; - adc.set_conv_trigger_config(0, &conv_trigger_config); - - uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); - - loop { - adc.do_software_trigger(1); - let mut result: Option = None; - while result.is_none() { - result = hal::adc::get_conv_result(); - } - let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; - let mut buf: String<16> = String::new(); // adjust size as needed - write!(buf, "\r\nvalue: {}\r\n", value).unwrap(); - uart.write_str_blocking(&buf); - } -} diff --git a/examples/blink.rs b/examples/blink.rs deleted file mode 100644 index 564353d5c..000000000 --- a/examples/blink.rs +++ /dev/null @@ -1,84 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use embassy_time::{Duration, Timer}; -use hal::gpio::pins::PIO3_18; -use hal::gpio::{Level, Output}; - -mod common; - -use embassy_mcxa276::bind_interrupts; - -// Bind only OS_EVENT for timer interrupts -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); - - // Board-style init: enable LED GPIO/PORT clocks used by blink - unsafe { - common::init_led(hal::pac()); - } - // Initialize OSTIMER for async timing - unsafe { - common::init_ostimer0(hal::pac()); - } - - // Initialize embassy-time global driver backed by OSTIMER0 - hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); - - // Configure LED pin for GPIO mode - PIO3_18::set_mux_gpio(); - - let mut led = Output::new(PIO3_18::degrade(), Level::High); - - // Complex blinking pattern: SOS in Morse code - // S: ... (3 short) - // O: --- (3 long) - // S: ... (3 short) - // With pauses between letters and words - - loop { - // S: three short blinks - for _ in 0..3 { - led.set_low(); - Timer::after(Duration::from_millis(150)).await; - led.set_high(); - Timer::after(Duration::from_millis(150)).await; - } - - // Pause between letters - Timer::after(Duration::from_millis(300)).await; - - // O: three long blinks - for _ in 0..3 { - led.set_low(); - Timer::after(Duration::from_millis(450)).await; - led.set_high(); - Timer::after(Duration::from_millis(150)).await; - } - - // Pause between letters - Timer::after(Duration::from_millis(300)).await; - - // S: three short blinks - for _ in 0..3 { - led.set_low(); - Timer::after(Duration::from_millis(150)).await; - led.set_high(); - Timer::after(Duration::from_millis(150)).await; - } - - // Long pause between words (SOS repeats) - Timer::after(Duration::from_millis(1000)).await; - } -} diff --git a/examples/build.rs b/examples/build.rs new file mode 100644 index 000000000..f076bba9f --- /dev/null +++ b/examples/build.rs @@ -0,0 +1,20 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + + // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH" + // cortex-m-rt expects FLASH for code, RAM for data/bss/stack + // Both are in RAM, but separated to satisfy cortex-m-rt's expectations + // MCXA256 has 128KB RAM total + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=memory.x"); +} diff --git a/examples/common/mod.rs b/examples/common/mod.rs deleted file mode 100644 index 8c52c8e86..000000000 --- a/examples/common/mod.rs +++ /dev/null @@ -1,45 +0,0 @@ -//! Shared board-specific helpers for the FRDM-MCXA276 examples. -//! These live with the examples so the HAL stays generic. - -use hal::{clocks, pins, reset}; -use {embassy_mcxa276 as hal, panic_probe as _}; - -/// Initialize clocks and pin muxing for UART2 debug console. -/// Safe to call multiple times; writes are idempotent for our use. -#[allow(dead_code)] -pub unsafe fn init_uart2(p: &mcxa_pac::Peripherals) { - clocks::ensure_frolf_running(p); - clocks::enable_uart2_port2(p); - reset::release_reset_port2(p); - reset::release_reset_lpuart2(p); - pins::configure_uart2_pins_port2(); - clocks::select_uart2_clock(p); -} - -/// Initialize clocks for the LED GPIO/PORT used by the blink example. -#[allow(dead_code)] -pub unsafe fn init_led(p: &mcxa_pac::Peripherals) { - clocks::enable_led_port(p); - reset::release_reset_gpio3(p); - reset::release_reset_port3(p); -} - -/// Initialize clocks for OSTIMER0 (1 MHz source). -#[allow(dead_code)] -pub unsafe fn init_ostimer0(p: &mcxa_pac::Peripherals) { - clocks::ensure_frolf_running(p); - clocks::enable_ostimer0(p); - reset::release_reset_ostimer0(p); - clocks::select_ostimer0_clock_1m(p); -} - -/// Initialize clocks and pin muxing for ADC. -#[allow(dead_code)] -pub unsafe fn init_adc(p: &mcxa_pac::Peripherals) { - clocks::ensure_frolf_running(p); - clocks::enable_adc(p); - reset::release_reset_port1(p); - reset::release_reset_adc1(p); - pins::configure_adc_pins(); - clocks::select_adc_clock(p); -} diff --git a/examples/hello.rs b/examples/hello.rs deleted file mode 100644 index e39adaced..000000000 --- a/examples/hello.rs +++ /dev/null @@ -1,114 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::uart; - -mod common; - -use {defmt_rtt as _, panic_probe as _}; - -/// Simple helper to write a byte as hex to UART -fn write_hex_byte(uart: &hal::uart::Uart, byte: u8) { - const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; - uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); - uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("boot"); - - // Board-level init for UART2 clocks and pins. - unsafe { - common::init_uart2(hal::pac()); - } - - // Get UART source frequency from clock configuration - // Using hardcoded frequency for now - dynamic detection may have issues - let src = 12_000_000; // FRO_LF_DIV at 12MHz with DIV=0 - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); - - // Print welcome message before any async delays to guarantee early console output - uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); - uart.write_str_blocking("Available commands:\r\n"); - uart.write_str_blocking(" help - Show this help\r\n"); - uart.write_str_blocking(" echo - Echo back the text\r\n"); - uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); - uart.write_str_blocking("Type a command: "); - - let mut buffer = [0u8; 64]; - let mut buf_idx = 0; - - loop { - // Read a byte from UART - let byte = uart.read_byte_blocking(); - - // Echo the character back - if byte == b'\r' || byte == b'\n' { - // Enter pressed - process command - uart.write_str_blocking("\r\n"); - - if buf_idx > 0 { - let command = &buffer[0..buf_idx]; - - if command == b"help" { - uart.write_str_blocking("Available commands:\r\n"); - uart.write_str_blocking(" help - Show this help\r\n"); - uart.write_str_blocking(" echo - Echo back the text\r\n"); - uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); - } else if command.starts_with(b"echo ") && command.len() > 5 { - uart.write_str_blocking("Echo: "); - uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or("")); - uart.write_str_blocking("\r\n"); - } else if command.starts_with(b"hex ") && command.len() > 4 { - // Parse the byte value - let num_str = &command[4..]; - if let Ok(num) = parse_u8(num_str) { - uart.write_str_blocking("Hex: 0x"); - write_hex_byte(&uart, num); - uart.write_str_blocking("\r\n"); - } else { - uart.write_str_blocking("Invalid number for hex command\r\n"); - } - } else if command.len() > 0 { - uart.write_str_blocking("Unknown command: "); - uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); - uart.write_str_blocking("\r\n"); - } - } - - // Reset buffer and prompt - buf_idx = 0; - uart.write_str_blocking("Type a command: "); - } else if byte == 8 || byte == 127 { - // Backspace - if buf_idx > 0 { - buf_idx -= 1; - uart.write_str_blocking("\x08 \x08"); // Erase character - } - } else if buf_idx < buffer.len() - 1 { - // Regular character - buffer[buf_idx] = byte; - buf_idx += 1; - uart.write_byte(byte); - } - } -} - -/// Simple parser for u8 from ASCII bytes -fn parse_u8(bytes: &[u8]) -> Result { - let mut result = 0u8; - for &b in bytes { - if b >= b'0' && b <= b'9' { - result = result.checked_mul(10).ok_or(())?; - result = result.checked_add(b - b'0').ok_or(())?; - } else { - return Err(()); - } - } - Ok(result) -} diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs deleted file mode 100644 index 35d311143..000000000 --- a/examples/lpuart_buffered.rs +++ /dev/null @@ -1,77 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use embassy_mcxa276::interrupt::typelevel::Handler; -use embassy_mcxa276::lpuart::buffered::BufferedLpuart; -use embassy_mcxa276::{bind_interrupts, lpuart}; -use embedded_io_async::{Read, Write}; - -mod common; - -// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver -bind_interrupts!(struct Irqs { - LPUART2 => lpuart::buffered::BufferedInterruptHandler::; -}); - -// Wrapper function for the interrupt handler -unsafe extern "C" fn lpuart2_handler() { - lpuart::buffered::BufferedInterruptHandler::::on_interrupt(); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); - let p2 = lpuart::lib::init(); - - unsafe { - hal::interrupt::install_irq_handler(mcxa_pac::Interrupt::LPUART2, lpuart2_handler); - } - - // Configure NVIC for LPUART2 - hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); - - unsafe { - common::init_uart2(hal::pac()); - common::init_ostimer0(hal::pac()); - } - - // UART configuration (enable both TX and RX) - let config = lpuart::Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - rx_fifo_watermark: 0, - tx_fifo_watermark: 0, - ..Default::default() - }; - - let mut tx_buf = [0u8; 256]; - let mut rx_buf = [0u8; 256]; - - // Create a buffered LPUART2 instance with both TX and RX - let mut uart = BufferedLpuart::new( - p2.LPUART2, - p2.PIO2_2, // TX pin - p2.PIO2_3, // RX pin - Irqs, - &mut tx_buf, - &mut rx_buf, - config, - ) - .unwrap(); - - // Split into TX and RX parts - let (tx, rx) = uart.split_ref(); - - tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); - tx.write(b"Type characters to echo them back.\r\n").await.unwrap(); - - // Echo loop - let mut buf = [0u8; 4]; - loop { - rx.read_exact(&mut buf[..]).await.unwrap(); - tx.write_all(&buf[..]).await.unwrap(); - } -} diff --git a/examples/lpuart_polling.rs b/examples/lpuart_polling.rs deleted file mode 100644 index 067c7eb53..000000000 --- a/examples/lpuart_polling.rs +++ /dev/null @@ -1,53 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; - -use crate::hal::lpuart::{lib, Config, Lpuart}; - -mod common; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); - let p2 = lib::init(); - - defmt::info!("boot"); - - // Board-level init for UART2 clocks and pins. - unsafe { - common::init_uart2(hal::pac()); - } - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX - let lpuart = Lpuart::new_blocking( - p2.LPUART2, // Peripheral - p2.PIO2_2, // TX pin - p2.PIO2_3, // RX pin - config, - ) - .unwrap(); - - // Split into separate TX and RX parts - let (mut tx, mut rx) = lpuart.split(); - - // Write hello messages - tx.blocking_write(b"Hello world.\r\n").unwrap(); - tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap(); - - // Echo loop - loop { - let mut buf = [0u8; 1]; - rx.blocking_read(&mut buf).unwrap(); - tx.blocking_write(&buf).unwrap(); - } -} diff --git a/examples/memory.x b/examples/memory.x new file mode 100644 index 000000000..f4263a412 --- /dev/null +++ b/examples/memory.x @@ -0,0 +1,5 @@ +MEMORY +{ + FLASH : ORIGIN = 0x20000000, LENGTH = 64K + RAM : ORIGIN = 0x20010000, LENGTH = 64K +} diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs deleted file mode 100644 index 78ca4bbc5..000000000 --- a/examples/ostimer_alarm.rs +++ /dev/null @@ -1,111 +0,0 @@ -#![no_std] -#![no_main] - -use core::sync::atomic::{AtomicBool, Ordering}; - -use embassy_executor::Spawner; -use hal::uart; -use {cortex_m, embassy_mcxa276 as hal}; - -mod common; - -use embassy_mcxa276::bind_interrupts; -use {defmt_rtt as _, panic_probe as _}; - -// Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -// Global flag for alarm callback -static ALARM_FLAG: AtomicBool = AtomicBool::new(false); - -// Alarm callback function -fn alarm_callback() { - ALARM_FLAG.store(true, Ordering::Release); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } - unsafe { - common::init_uart2(hal::pac()); - } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); - uart.write_str_blocking("OSTIMER Alarm Example\n"); - - // Initialize embassy-time global driver backed by OSTIMER0 - hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); - - // Create OSTIMER instance - let config = hal::ostimer::Config { - init_match_max: true, - clock_frequency_hz: 1_000_000, // 1MHz - }; - let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); - - // Create alarm with callback - let alarm = hal::ostimer::Alarm::new() - .with_callback(alarm_callback) - .with_flag(&ALARM_FLAG); - - uart.write_str_blocking("Scheduling alarm for 2 seconds...\n"); - - // Schedule alarm to expire in 2 seconds (2,000,000 microseconds) - let scheduled = ostimer.schedule_alarm_delay(&alarm, 2_000_000); - if scheduled { - uart.write_str_blocking("Alarm scheduled successfully\n"); - } else { - uart.write_str_blocking("Failed to schedule alarm (would exceed timer capacity)\n"); - return; - } - - // Wait for alarm to expire - loop { - // Check if alarm has expired - if ALARM_FLAG.load(Ordering::Acquire) { - uart.write_str_blocking("Alarm expired! Callback executed.\n"); - break; - } - - // Busy wait - don't use Timer::after_millis as it interferes with alarm MATCH - for _ in 0..100000 { - cortex_m::asm::nop(); - } - } - - // Demonstrate canceling an alarm - uart.write_str_blocking("Scheduling another alarm for 3 seconds...\n"); - ALARM_FLAG.store(false, Ordering::Release); // Reset flag - - let scheduled = ostimer.schedule_alarm_delay(&alarm, 3_000_000); - if scheduled { - uart.write_str_blocking("Alarm scheduled. Waiting 1 second then canceling...\n"); - - // Wait 1 second - embassy_time::Timer::after_millis(1000).await; - - // Cancel the alarm - ostimer.cancel_alarm(&alarm); - uart.write_str_blocking("Alarm canceled\n"); - - // Check immediately if alarm flag is set - if !ALARM_FLAG.load(Ordering::Acquire) { - uart.write_str_blocking("Alarm was successfully canceled\n"); - } else { - uart.write_str_blocking("Alarm fired despite cancellation\n"); - } - } - - uart.write_str_blocking("Example complete\n"); -} diff --git a/examples/ostimer_async.rs b/examples/ostimer_async.rs deleted file mode 100644 index 27e14e022..000000000 --- a/examples/ostimer_async.rs +++ /dev/null @@ -1,57 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::uart; - -mod common; - -use embassy_mcxa276::bind_interrupts; -use embassy_time::{Duration, Timer}; -use {defmt_rtt as _, panic_probe as _}; - -// Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed. -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); - - // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } - unsafe { - common::init_uart2(hal::pac()); - } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); - uart.write_str_blocking("boot\n"); - - // Avoid mass NVIC writes here; DefaultHandler now safely returns. - - // Initialize embassy-time global driver backed by OSTIMER0 (re-enables OS_EVENT with priority) - // The bind_interrupts! macro handles handler binding automatically - - // Initialize OSTIMER with default 1MHz frequency - // Adjust this value to match your actual OSTIMER clock frequency - hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); - - // Removed force-pend; rely on real hardware match to trigger OS_EVENT. - - // Log using defmt if enabled - defmt::info!("OSTIMER async example starting..."); - - loop { - defmt::info!("tick"); - uart.write_str_blocking("tick\n"); - Timer::after(Duration::from_millis(1000)).await; - } -} diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs deleted file mode 100644 index e95140a88..000000000 --- a/examples/ostimer_counter.rs +++ /dev/null @@ -1,128 +0,0 @@ -//! # OSTIMER Counter Reading and Reset Example -//! -//! This example demonstrates the new timer counter reading and reset functionality -//! of the OSTIMER driver. - -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::{Duration, Timer}; -use hal::bind_interrupts; -use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; - -mod common; - -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(Default::default()); - - // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } - unsafe { - common::init_uart2(hal::pac()); - } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); - - uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); - - // Initialize the OSTIMER time driver - hal::ostimer::time_driver::init( - hal::interrupt::Priority::from(3), - 1_000_000, // 1MHz clock - ); - - // Create OSTIMER instance - let ostimer = hal::ostimer::Ostimer::::new( - p.OSTIMER0, - hal::ostimer::Config { - init_match_max: true, - clock_frequency_hz: 1_000_000, - }, - hal::pac(), - ); - - // Read initial counter value - let initial_counter = ostimer.now(); - uart.write_str_blocking("Initial counter value: "); - write_u64(&mut uart, initial_counter); - uart.write_str_blocking("\n"); - - // Wait a bit to let counter increment - Timer::after(Duration::from_millis(100)).await; - - // Read counter again - let counter_after_wait = ostimer.now(); - uart.write_str_blocking("Counter after 100ms wait: "); - write_u64(&mut uart, counter_after_wait); - uart.write_str_blocking("\n"); - uart.write_str_blocking("Difference: "); - write_u64(&mut uart, counter_after_wait - initial_counter); - uart.write_str_blocking(" ticks\n"); - - // Reset the timer - uart.write_str_blocking("Resetting timer...\n"); - ostimer.reset(hal::pac()); - - // Read counter after reset - let counter_after_reset = ostimer.now(); - uart.write_str_blocking("Counter after reset: "); - write_u64(&mut uart, counter_after_reset); - uart.write_str_blocking("\n"); - - // Wait again to verify timer is working - Timer::after(Duration::from_millis(50)).await; - - let final_counter = ostimer.now(); - uart.write_str_blocking("Counter after another 50ms: "); - write_u64(&mut uart, final_counter); - uart.write_str_blocking("\n"); - uart.write_str_blocking("Difference after reset: "); - write_u64(&mut uart, final_counter - counter_after_reset); - uart.write_str_blocking(" ticks\n"); - - uart.write_str_blocking("Example complete\n"); -} - -// Helper function to write a u64 value as decimal string -fn write_u64(uart: &mut hal::uart::Uart, value: u64) { - if value == 0 { - uart.write_str_blocking("0"); - return; - } - - let mut buffer = [0u8; 20]; // Enough for max u64 - let mut i = 0; - let mut v = value; - - while v > 0 { - buffer[i] = b'0' + (v % 10) as u8; - v /= 10; - i += 1; - } - - // Write digits in reverse order - while i > 0 { - i -= 1; - match buffer[i] { - b'0' => uart.write_str_blocking("0"), - b'1' => uart.write_str_blocking("1"), - b'2' => uart.write_str_blocking("2"), - b'3' => uart.write_str_blocking("3"), - b'4' => uart.write_str_blocking("4"), - b'5' => uart.write_str_blocking("5"), - b'6' => uart.write_str_blocking("6"), - b'7' => uart.write_str_blocking("7"), - b'8' => uart.write_str_blocking("8"), - b'9' => uart.write_str_blocking("9"), - _ => uart.write_str_blocking("?"), - } - } -} diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs deleted file mode 100644 index 368a3e52f..000000000 --- a/examples/ostimer_race_test.rs +++ /dev/null @@ -1,396 +0,0 @@ -//! # OSTIMER Race Condition Test -//! -//! This example tests for race conditions in the OSTIMER driver by: -//! - Scheduling alarms sequentially (hardware limitation: only one at a time) -//! - Reading the counter during interrupt-heavy periods -//! - Testing concurrent timer operations -//! - Stress testing interrupt handling - -#![no_std] -#![no_main] - -use core::sync::atomic::{AtomicU32, Ordering}; - -use embassy_executor::Spawner; -use embassy_time::{Duration, Timer}; -use hal::bind_interrupts; -use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; - -mod common; - -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -// Global counters for race condition detection -static ALARM_CALLBACK_COUNT: AtomicU32 = AtomicU32::new(0); -static INTERRUPT_COUNT: AtomicU32 = AtomicU32::new(0); -static RACE_DETECTED: AtomicU32 = AtomicU32::new(0); - -// Alarm callback function -fn alarm_callback() { - let _count = ALARM_CALLBACK_COUNT.fetch_add(1, Ordering::SeqCst); - INTERRUPT_COUNT.fetch_add(1, Ordering::SeqCst); - - // Simulate some work in the callback to increase chance of races - for _ in 0..10 { - cortex_m::asm::nop(); - } -} - -fn report_default_handler(uart: &mut hal::uart::Uart) { - let snapshot = hal::interrupt::default_handler_snapshot(); - if snapshot.count == 0 { - return; - } - - uart.write_str_blocking("WARNING: DefaultHandler executed "); - write_u32(uart, snapshot.count); - uart.write_str_blocking(" time(s). Vector="); - write_u32(uart, snapshot.vector as u32); - uart.write_str_blocking(" CFSR=0x"); - write_hex32(uart, snapshot.cfsr); - uart.write_str_blocking(" HFSR=0x"); - write_hex32(uart, snapshot.hfsr); - uart.write_str_blocking(" PC=0x"); - write_hex32(uart, snapshot.stacked_pc); - uart.write_str_blocking(" LR=0x"); - write_hex32(uart, snapshot.stacked_lr); - uart.write_str_blocking(" SP=0x"); - write_hex32(uart, snapshot.stacked_sp); - uart.write_str_blocking("\n"); - - hal::interrupt::clear_default_handler_snapshot(); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(Default::default()); - - // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } - unsafe { - common::init_uart2(hal::pac()); - } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); - - uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); - - // The bind_interrupts! macro handles handler binding automatically - - // Initialize the OSTIMER time driver FIRST - hal::ostimer::time_driver::init( - hal::interrupt::Priority::from(3), - 1_000_000, // 1MHz clock - ); - - uart.write_str_blocking("Time driver initialized\n"); - - // Create OSTIMER instance - let ostimer = hal::ostimer::Ostimer::::new( - p.OSTIMER0, - hal::ostimer::Config { - init_match_max: true, - clock_frequency_hz: 1_000_000, - }, - hal::pac(), - ); - - uart.write_str_blocking("OSTIMER instance created\n"); - - // Test 1: Sequential alarm scheduling (OSTIMER only supports one alarm at a time) - uart.write_str_blocking("Test 1: Sequential alarm scheduling...\n"); - test_rapid_alarms(&ostimer, &mut uart).await; - report_default_handler(&mut uart); - - // Test 2: Counter reading during interrupts - uart.write_str_blocking("Test 2: Counter reading during interrupts...\n"); - test_counter_reading_during_interrupts(&ostimer, &mut uart).await; - report_default_handler(&mut uart); - - // Test 3: Concurrent timer operations - uart.write_str_blocking("Test 3: Concurrent timer operations...\n"); - test_concurrent_operations(&ostimer, &mut uart).await; - report_default_handler(&mut uart); - - // Test 4: Timer reset during operation - uart.write_str_blocking("Test 4: Timer reset during operation...\n"); - test_reset_during_operation(&ostimer, &mut uart, hal::pac()).await; - report_default_handler(&mut uart); - - // Report results - uart.write_str_blocking("Race condition test complete\n"); - uart.write_str_blocking("Callback count: "); - write_u32(&mut uart, ALARM_CALLBACK_COUNT.load(Ordering::SeqCst)); - uart.write_str_blocking("\nInterrupt count: "); - write_u32(&mut uart, INTERRUPT_COUNT.load(Ordering::SeqCst)); - uart.write_str_blocking("\nRaces detected: "); - write_u32(&mut uart, RACE_DETECTED.load(Ordering::SeqCst)); - uart.write_str_blocking("\n"); -} - -// Test rapid alarm scheduling to stress interrupt handling -async fn test_rapid_alarms( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, -) { - let initial_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); - - // Schedule 10 alarms sequentially (OSTIMER only supports one alarm at a time) - for _i in 0..10 { - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - let delay_us = 1000; // 1ms delay for each alarm - if ostimer.schedule_alarm_delay(&alarm, delay_us) { - // Wait for this alarm to complete before scheduling the next - Timer::after(Duration::from_micros(delay_us + 100)).await; - report_default_handler(uart); - } else { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm (match not ready)\n"); - } - } - - // All alarms should have completed by now - let final_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); - let expected_count = initial_count + 10; - - if final_count != expected_count { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Expected "); - write_u32(uart, expected_count); - uart.write_str_blocking(" callbacks, got "); - write_u32(uart, final_count); - uart.write_str_blocking("\n"); - } else { - uart.write_str_blocking("PASS: All rapid alarms executed\n"); - } -} - -// Test reading counter while interrupts are firing -async fn test_counter_reading_during_interrupts( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, -) { - let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - // Schedule an alarm that will fire soon - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - if !ostimer.schedule_alarm_delay(&alarm, 500) { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before counter stress\n"); - } - - // While alarm is pending, read the counter many times rapidly - // This tests if counter reading is atomic and doesn't get corrupted by interrupts - let mut last_counter = ostimer.now(); - let mut consistent_reads = 0; - let mut total_reads = 0; - - for _ in 0..1000 { - let current_counter = ostimer.now(); - total_reads += 1; - - // Check if counter is monotonically increasing (basic sanity check) - if current_counter >= last_counter { - consistent_reads += 1; - } - last_counter = current_counter; - - // Small delay between reads - for _ in 0..10 { - cortex_m::asm::nop(); - } - - report_default_handler(uart); - } - - // Wait for alarm to complete - Timer::after(Duration::from_millis(1)).await; - - let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - if consistent_reads == total_reads { - uart.write_str_blocking("PASS: Counter reading consistent during interrupts\n"); - } else { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Counter reading inconsistent: "); - write_u32(uart, consistent_reads); - uart.write_str_blocking("/"); - write_u32(uart, total_reads); - uart.write_str_blocking(" consistent\n"); - } - - if final_interrupt_count > initial_interrupt_count { - uart.write_str_blocking("PASS: Interrupt fired during counter reading test\n"); - } else { - uart.write_str_blocking("WARNING: No interrupt fired during counter reading test\n"); - } -} - -// Test concurrent timer operations (embassy-time + alarms) -async fn test_concurrent_operations( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, -) { - let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - // Start an embassy-time timer - let timer_future = Timer::after(Duration::from_millis(2)); - - // Schedule an alarm that should fire before the timer - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - if !ostimer.schedule_alarm_delay(&alarm, 1000) { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before concurrent operations\n"); - } - - // Wait for both to complete - timer_future.await; - - let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - if final_interrupt_count > initial_interrupt_count { - uart.write_str_blocking("PASS: Concurrent operations completed\n"); - } else { - uart.write_str_blocking("WARNING: No interrupts during concurrent operations\n"); - } -} - -// Test timer reset during active operations -async fn test_reset_during_operation( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, - peripherals: &mcxa_pac::Peripherals, -) { - let initial_counter = ostimer.now(); - - // Schedule an alarm - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - if !ostimer.schedule_alarm_delay(&alarm, 2000) { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before reset test\n"); - } - - // Wait a bit then reset the timer - Timer::after(Duration::from_millis(1)).await; - ostimer.reset(peripherals); - - // Check counter after reset - let counter_after_reset = ostimer.now(); - - // Wait to see if the alarm still fires (it shouldn't after reset) - Timer::after(Duration::from_millis(2)).await; - - let final_counter = ostimer.now(); - - if counter_after_reset < initial_counter { - uart.write_str_blocking("PASS: Timer reset successful\n"); - } else { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Timer reset may have failed\n"); - } - - uart.write_str_blocking("Counter progression after reset: "); - write_u64(uart, initial_counter); - uart.write_str_blocking(" -> "); - write_u64(uart, counter_after_reset); - uart.write_str_blocking(" -> "); - write_u64(uart, final_counter); - uart.write_str_blocking("\n"); -} - -// Helper function to write a u32 value as decimal string -fn write_u32(uart: &mut hal::uart::Uart, value: u32) { - if value == 0 { - uart.write_str_blocking("0"); - return; - } - - let mut buffer = [0u8; 10]; // Enough for max u32 - let mut i = 0; - let mut v = value; - - while v > 0 { - buffer[i] = b'0' + (v % 10) as u8; - v /= 10; - i += 1; - } - - // Write digits in reverse order - while i > 0 { - i -= 1; - match buffer[i] { - b'0' => uart.write_str_blocking("0"), - b'1' => uart.write_str_blocking("1"), - b'2' => uart.write_str_blocking("2"), - b'3' => uart.write_str_blocking("3"), - b'4' => uart.write_str_blocking("4"), - b'5' => uart.write_str_blocking("5"), - b'6' => uart.write_str_blocking("6"), - b'7' => uart.write_str_blocking("7"), - b'8' => uart.write_str_blocking("8"), - b'9' => uart.write_str_blocking("9"), - _ => uart.write_str_blocking("?"), - } - } -} - -fn write_hex32(uart: &mut hal::uart::Uart, value: u32) { - let mut buf = [b'0'; 8]; - let mut tmp = value; - for i in (0..8).rev() { - let digit = (tmp & 0xF) as u8; - buf[i] = match digit { - 0..=9 => b'0' + digit, - 10..=15 => b'A' + (digit - 10), - _ => b'?', - }; - tmp >>= 4; - } - for b in &buf { - uart.write_byte(*b); - } -} - -// Helper function to write a u64 value as decimal string -fn write_u64(uart: &mut hal::uart::Uart, value: u64) { - if value == 0 { - uart.write_str_blocking("0"); - return; - } - - let mut buffer = [0u8; 20]; // Enough for max u64 - let mut i = 0; - let mut v = value; - - while v > 0 { - buffer[i] = b'0' + (v % 10) as u8; - v /= 10; - i += 1; - } - - // Write digits in reverse order - while i > 0 { - i -= 1; - match buffer[i] { - b'0' => uart.write_str_blocking("0"), - b'1' => uart.write_str_blocking("1"), - b'2' => uart.write_str_blocking("2"), - b'3' => uart.write_str_blocking("3"), - b'4' => uart.write_str_blocking("4"), - b'5' => uart.write_str_blocking("5"), - b'6' => uart.write_str_blocking("6"), - b'7' => uart.write_str_blocking("7"), - b'8' => uart.write_str_blocking("8"), - b'9' => uart.write_str_blocking("9"), - _ => uart.write_str_blocking("?"), - } - } -} diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs deleted file mode 100644 index c27fd4c55..000000000 --- a/examples/rtc_alarm.rs +++ /dev/null @@ -1,87 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use hal::rtc::{RtcDateTime, RtcInterruptEnable}; -use hal::{uart, InterruptExt}; -use {cortex_m, embassy_mcxa276 as hal}; - -mod common; - -type MyRtc = hal::rtc::Rtc; - -use embassy_mcxa276::bind_interrupts; -use {defmt_rtt as _, panic_probe as _}; - -bind_interrupts!(struct Irqs { - RTC => hal::rtc::RtcHandler; -}); - -#[used] -#[no_mangle] -static KEEP_RTC: unsafe extern "C" fn() = RTC; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - unsafe { - common::init_uart2(hal::pac()); - } - - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); - - uart.write_str_blocking("\r\n=== RTC Alarm Example ===\r\n"); - - unsafe { hal::clocks::init_fro16k(hal::pac()) }; - - let rtc_config = hal::rtc::get_default_config(); - - let rtc = MyRtc::new(p.RTC0, rtc_config); - - let now = RtcDateTime { - year: 2025, - month: 10, - day: 15, - hour: 14, - minute: 30, - second: 0, - }; - - rtc.stop(); - - uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n"); - rtc.set_datetime(now); - - let mut alarm = now; - alarm.second += 10; - - rtc.set_alarm(alarm); - uart.write_str_blocking("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)\r\n"); - - rtc.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); - - unsafe { - hal::interrupt::RTC.enable(); - } - - unsafe { - cortex_m::interrupt::enable(); - } - - rtc.start(); - - uart.write_str_blocking("RTC started, waiting for alarm...\r\n"); - - loop { - if rtc.is_alarm_triggered() { - uart.write_str_blocking("\r\n*** ALARM TRIGGERED! ***\r\n"); - break; - } - } - - uart.write_str_blocking("Example complete - Test PASSED!\r\n"); - - loop {} -} diff --git a/examples/src/bin/adc_interrupt.rs b/examples/src/bin/adc_interrupt.rs new file mode 100644 index 000000000..e174a5272 --- /dev/null +++ b/examples/src/bin/adc_interrupt.rs @@ -0,0 +1,86 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::{init_adc, init_uart2}; +use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; +use hal::{bind_interrupts, uart, InterruptExt}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!(struct Irqs { + ADC1 => hal::adc::AdcHandler; +}); + +#[used] +#[no_mangle] +static KEEP_ADC: unsafe extern "C" fn() = ADC1; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + unsafe { + init_uart2(hal::pac()); + } + + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); + + unsafe { + init_adc(hal::pac()); + } + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + + adc.enable_interrupt(0x1); + + unsafe { + hal::interrupt::ADC1.enable(); + } + + unsafe { + cortex_m::interrupt::enable(); + } + + loop { + adc.do_software_trigger(1); + while !adc.is_interrupt_triggered() { + // Wait until the interrupt is triggered + } + uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); + //TBD need to print the value + } +} diff --git a/examples/src/bin/adc_polling.rs b/examples/src/bin/adc_polling.rs new file mode 100644 index 000000000..741551d49 --- /dev/null +++ b/examples/src/bin/adc_polling.rs @@ -0,0 +1,76 @@ +#![no_std] +#![no_main] + +use core::fmt::Write; + +use embassy_executor::Spawner; +use embassy_mcxa_examples::{init_adc, init_uart2}; +use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; +use hal::uart; +use heapless::String; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +const G_LPADC_RESULT_SHIFT: u32 = 0; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + unsafe { + init_uart2(hal::pac()); + } + + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n"); + + unsafe { + init_adc(hal::pac()); + } + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + + loop { + adc.do_software_trigger(1); + let mut result: Option = None; + while result.is_none() { + result = hal::adc::get_conv_result(); + } + let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; + let mut buf: String<16> = String::new(); // adjust size as needed + write!(buf, "\r\nvalue: {}\r\n", value).unwrap(); + uart.write_str_blocking(&buf); + } +} diff --git a/examples/src/bin/blink.rs b/examples/src/bin/blink.rs new file mode 100644 index 000000000..d8a57c546 --- /dev/null +++ b/examples/src/bin/blink.rs @@ -0,0 +1,78 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa as hal; +use embassy_mcxa::bind_interrupts; +use embassy_mcxa_examples::{init_led, init_ostimer0}; +use embassy_time::{Duration, Timer}; +use hal::gpio::pins::PIO3_18; +use hal::gpio::{Level, Output}; + +// Bind only OS_EVENT for timer interrupts +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + + unsafe { + init_led(hal::pac()); + init_ostimer0(hal::pac()); + } + + // Initialize embassy-time global driver backed by OSTIMER0 + hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); + + // Configure LED pin for GPIO mode + PIO3_18::set_mux_gpio(); + + let mut led = Output::new(PIO3_18::degrade(), Level::High); + + // Complex blinking pattern: SOS in Morse code + // S: ... (3 short) + // O: --- (3 long) + // S: ... (3 short) + // With pauses between letters and words + + loop { + // S: three short blinks + for _ in 0..3 { + led.set_low(); + Timer::after(Duration::from_millis(150)).await; + led.set_high(); + Timer::after(Duration::from_millis(150)).await; + } + + // Pause between letters + Timer::after(Duration::from_millis(300)).await; + + // O: three long blinks + for _ in 0..3 { + led.set_low(); + Timer::after(Duration::from_millis(450)).await; + led.set_high(); + Timer::after(Duration::from_millis(150)).await; + } + + // Pause between letters + Timer::after(Duration::from_millis(300)).await; + + // S: three short blinks + for _ in 0..3 { + led.set_low(); + Timer::after(Duration::from_millis(150)).await; + led.set_high(); + Timer::after(Duration::from_millis(150)).await; + } + + // Long pause between words (SOS repeats) + Timer::after(Duration::from_millis(1000)).await; + } +} diff --git a/examples/src/bin/hello.rs b/examples/src/bin/hello.rs new file mode 100644 index 000000000..5c4336d50 --- /dev/null +++ b/examples/src/bin/hello.rs @@ -0,0 +1,111 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::init_uart2; +use hal::uart; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Simple helper to write a byte as hex to UART +fn write_hex_byte(uart: &hal::uart::Uart, byte: u8) { + const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; + uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); + uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("boot"); + + // Board-level init for UART2 clocks and pins. + unsafe { + init_uart2(hal::pac()); + } + + // Get UART source frequency from clock configuration + // Using hardcoded frequency for now - dynamic detection may have issues + let src = 12_000_000; // FRO_LF_DIV at 12MHz with DIV=0 + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + // Print welcome message before any async delays to guarantee early console output + uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + uart.write_str_blocking("Type a command: "); + + let mut buffer = [0u8; 64]; + let mut buf_idx = 0; + + loop { + // Read a byte from UART + let byte = uart.read_byte_blocking(); + + // Echo the character back + if byte == b'\r' || byte == b'\n' { + // Enter pressed - process command + uart.write_str_blocking("\r\n"); + + if buf_idx > 0 { + let command = &buffer[0..buf_idx]; + + if command == b"help" { + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + } else if command.starts_with(b"echo ") && command.len() > 5 { + uart.write_str_blocking("Echo: "); + uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } else if command.starts_with(b"hex ") && command.len() > 4 { + // Parse the byte value + let num_str = &command[4..]; + if let Ok(num) = parse_u8(num_str) { + uart.write_str_blocking("Hex: 0x"); + write_hex_byte(&uart, num); + uart.write_str_blocking("\r\n"); + } else { + uart.write_str_blocking("Invalid number for hex command\r\n"); + } + } else if !command.is_empty() { + uart.write_str_blocking("Unknown command: "); + uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } + } + + // Reset buffer and prompt + buf_idx = 0; + uart.write_str_blocking("Type a command: "); + } else if byte == 8 || byte == 127 { + // Backspace + if buf_idx > 0 { + buf_idx -= 1; + uart.write_str_blocking("\x08 \x08"); // Erase character + } + } else if buf_idx < buffer.len() - 1 { + // Regular character + buffer[buf_idx] = byte; + buf_idx += 1; + uart.write_byte(byte); + } + } +} + +/// Simple parser for u8 from ASCII bytes +fn parse_u8(bytes: &[u8]) -> Result { + let mut result = 0u8; + for &b in bytes { + if b.is_ascii_digit() { + result = result.checked_mul(10).ok_or(())?; + result = result.checked_add(b - b'0').ok_or(())?; + } else { + return Err(()); + } + } + Ok(result) +} diff --git a/examples/src/bin/lpuart_buffered.rs b/examples/src/bin/lpuart_buffered.rs new file mode 100644 index 000000000..480d8e1f7 --- /dev/null +++ b/examples/src/bin/lpuart_buffered.rs @@ -0,0 +1,76 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa as hal; +use embassy_mcxa::interrupt::typelevel::Handler; +use embassy_mcxa::lpuart::buffered::BufferedLpuart; +use embassy_mcxa::{bind_interrupts, lpuart}; +use embassy_mcxa_examples::{init_ostimer0, init_uart2}; +use embedded_io_async::{Read, Write}; + +// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver +bind_interrupts!(struct Irqs { + LPUART2 => lpuart::buffered::BufferedInterruptHandler::; +}); + +// Wrapper function for the interrupt handler +unsafe extern "C" fn lpuart2_handler() { + lpuart::buffered::BufferedInterruptHandler::::on_interrupt(); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + let p2 = lpuart::lib::init(); + + unsafe { + hal::interrupt::install_irq_handler(hal::pac::Interrupt::LPUART2, lpuart2_handler); + } + + // Configure NVIC for LPUART2 + hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); + + unsafe { + init_uart2(hal::pac()); + init_ostimer0(hal::pac()); + } + + // UART configuration (enable both TX and RX) + let config = lpuart::Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + rx_fifo_watermark: 0, + tx_fifo_watermark: 0, + ..Default::default() + }; + + let mut tx_buf = [0u8; 256]; + let mut rx_buf = [0u8; 256]; + + // Create a buffered LPUART2 instance with both TX and RX + let mut uart = BufferedLpuart::new( + p2.LPUART2, + p2.PIO2_2, // TX pin + p2.PIO2_3, // RX pin + Irqs, + &mut tx_buf, + &mut rx_buf, + config, + ) + .unwrap(); + + // Split into TX and RX parts + let (tx, rx) = uart.split_ref(); + + tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); + tx.write(b"Type characters to echo them back.\r\n").await.unwrap(); + + // Echo loop + let mut buf = [0u8; 4]; + loop { + rx.read_exact(&mut buf[..]).await.unwrap(); + tx.write_all(&buf[..]).await.unwrap(); + } +} diff --git a/examples/src/bin/lpuart_polling.rs b/examples/src/bin/lpuart_polling.rs new file mode 100644 index 000000000..215714569 --- /dev/null +++ b/examples/src/bin/lpuart_polling.rs @@ -0,0 +1,51 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::init_uart2; +use hal::lpuart::{lib, Config, Lpuart}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + let p2 = lib::init(); + + defmt::info!("boot"); + + // Board-level init for UART2 clocks and pins. + unsafe { + init_uart2(hal::pac()); + } + + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + let lpuart = Lpuart::new_blocking( + p2.LPUART2, // Peripheral + p2.PIO2_2, // TX pin + p2.PIO2_3, // RX pin + config, + ) + .unwrap(); + + // Split into separate TX and RX parts + let (mut tx, mut rx) = lpuart.split(); + + // Write hello messages + tx.blocking_write(b"Hello world.\r\n").unwrap(); + tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap(); + + // Echo loop + loop { + let mut buf = [0u8; 1]; + rx.blocking_read(&mut buf).unwrap(); + tx.blocking_write(&buf).unwrap(); + } +} diff --git a/examples/src/bin/ostimer_alarm.rs b/examples/src/bin/ostimer_alarm.rs new file mode 100644 index 000000000..953f98c01 --- /dev/null +++ b/examples/src/bin/ostimer_alarm.rs @@ -0,0 +1,106 @@ +#![no_std] +#![no_main] + +use core::sync::atomic::{AtomicBool, Ordering}; + +use embassy_executor::Spawner; +use embassy_mcxa::bind_interrupts; +use embassy_mcxa_examples::{init_ostimer0, init_uart2}; +use hal::uart; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +// Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +// Global flag for alarm callback +static ALARM_FLAG: AtomicBool = AtomicBool::new(false); + +// Alarm callback function +fn alarm_callback() { + ALARM_FLAG.store(true, Ordering::Release); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + init_ostimer0(hal::pac()); + init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + uart.write_str_blocking("OSTIMER Alarm Example\n"); + + // Initialize embassy-time global driver backed by OSTIMER0 + hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); + + // Create OSTIMER instance + let config = hal::ostimer::Config { + init_match_max: true, + clock_frequency_hz: 1_000_000, // 1MHz + }; + let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); + + // Create alarm with callback + let alarm = hal::ostimer::Alarm::new() + .with_callback(alarm_callback) + .with_flag(&ALARM_FLAG); + + uart.write_str_blocking("Scheduling alarm for 2 seconds...\n"); + + // Schedule alarm to expire in 2 seconds (2,000,000 microseconds) + let scheduled = ostimer.schedule_alarm_delay(&alarm, 2_000_000); + if scheduled { + uart.write_str_blocking("Alarm scheduled successfully\n"); + } else { + uart.write_str_blocking("Failed to schedule alarm (would exceed timer capacity)\n"); + return; + } + + // Wait for alarm to expire + loop { + // Check if alarm has expired + if ALARM_FLAG.load(Ordering::Acquire) { + uart.write_str_blocking("Alarm expired! Callback executed.\n"); + break; + } + + // Busy wait - don't use Timer::after_millis as it interferes with alarm MATCH + for _ in 0..100000 { + cortex_m::asm::nop(); + } + } + + // Demonstrate canceling an alarm + uart.write_str_blocking("Scheduling another alarm for 3 seconds...\n"); + ALARM_FLAG.store(false, Ordering::Release); // Reset flag + + let scheduled = ostimer.schedule_alarm_delay(&alarm, 3_000_000); + if scheduled { + uart.write_str_blocking("Alarm scheduled. Waiting 1 second then canceling...\n"); + + // Wait 1 second + embassy_time::Timer::after_millis(1000).await; + + // Cancel the alarm + ostimer.cancel_alarm(&alarm); + uart.write_str_blocking("Alarm canceled\n"); + + // Check immediately if alarm flag is set + if !ALARM_FLAG.load(Ordering::Acquire) { + uart.write_str_blocking("Alarm was successfully canceled\n"); + } else { + uart.write_str_blocking("Alarm fired despite cancellation\n"); + } + } + + uart.write_str_blocking("Example complete\n"); +} diff --git a/examples/src/bin/ostimer_async.rs b/examples/src/bin/ostimer_async.rs new file mode 100644 index 000000000..34862b61f --- /dev/null +++ b/examples/src/bin/ostimer_async.rs @@ -0,0 +1,52 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::bind_interrupts; +use embassy_mcxa_examples::{init_ostimer0, init_uart2}; +use embassy_time::{Duration, Timer}; +use hal::uart; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +// Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed. +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + init_ostimer0(hal::pac()); + init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); + uart.write_str_blocking("boot\n"); + + // Avoid mass NVIC writes here; DefaultHandler now safely returns. + + // Initialize embassy-time global driver backed by OSTIMER0 (re-enables OS_EVENT with priority) + // The bind_interrupts! macro handles handler binding automatically + + // Initialize OSTIMER with default 1MHz frequency + // Adjust this value to match your actual OSTIMER clock frequency + hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); + + // Removed force-pend; rely on real hardware match to trigger OS_EVENT. + + // Log using defmt if enabled + defmt::info!("OSTIMER async example starting..."); + + loop { + defmt::info!("tick"); + uart.write_str_blocking("tick\n"); + Timer::after(Duration::from_millis(1000)).await; + } +} diff --git a/examples/src/bin/ostimer_counter.rs b/examples/src/bin/ostimer_counter.rs new file mode 100644 index 000000000..20044760a --- /dev/null +++ b/examples/src/bin/ostimer_counter.rs @@ -0,0 +1,125 @@ +//! # OSTIMER Counter Reading and Reset Example +//! +//! This example demonstrates the new timer counter reading and reset functionality +//! of the OSTIMER driver. + +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::{init_ostimer0, init_uart2}; +use embassy_time::{Duration, Timer}; +use hal::bind_interrupts; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(Default::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + init_ostimer0(hal::pac()); + init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + + uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); + + // Initialize the OSTIMER time driver + hal::ostimer::time_driver::init( + hal::interrupt::Priority::from(3), + 1_000_000, // 1MHz clock + ); + + // Create OSTIMER instance + let ostimer = hal::ostimer::Ostimer::::new( + p.OSTIMER0, + hal::ostimer::Config { + init_match_max: true, + clock_frequency_hz: 1_000_000, + }, + hal::pac(), + ); + + // Read initial counter value + let initial_counter = ostimer.now(); + uart.write_str_blocking("Initial counter value: "); + write_u64(&mut uart, initial_counter); + uart.write_str_blocking("\n"); + + // Wait a bit to let counter increment + Timer::after(Duration::from_millis(100)).await; + + // Read counter again + let counter_after_wait = ostimer.now(); + uart.write_str_blocking("Counter after 100ms wait: "); + write_u64(&mut uart, counter_after_wait); + uart.write_str_blocking("\n"); + uart.write_str_blocking("Difference: "); + write_u64(&mut uart, counter_after_wait - initial_counter); + uart.write_str_blocking(" ticks\n"); + + // Reset the timer + uart.write_str_blocking("Resetting timer...\n"); + ostimer.reset(hal::pac()); + + // Read counter after reset + let counter_after_reset = ostimer.now(); + uart.write_str_blocking("Counter after reset: "); + write_u64(&mut uart, counter_after_reset); + uart.write_str_blocking("\n"); + + // Wait again to verify timer is working + Timer::after(Duration::from_millis(50)).await; + + let final_counter = ostimer.now(); + uart.write_str_blocking("Counter after another 50ms: "); + write_u64(&mut uart, final_counter); + uart.write_str_blocking("\n"); + uart.write_str_blocking("Difference after reset: "); + write_u64(&mut uart, final_counter - counter_after_reset); + uart.write_str_blocking(" ticks\n"); + + uart.write_str_blocking("Example complete\n"); +} + +// Helper function to write a u64 value as decimal string +fn write_u64(uart: &mut hal::uart::Uart, value: u64) { + if value == 0 { + uart.write_str_blocking("0"); + return; + } + + let mut buffer = [0u8; 20]; // Enough for max u64 + let mut i = 0; + let mut v = value; + + while v > 0 { + buffer[i] = b'0' + (v % 10) as u8; + v /= 10; + i += 1; + } + + // Write digits in reverse order + while i > 0 { + i -= 1; + match buffer[i] { + b'0' => uart.write_str_blocking("0"), + b'1' => uart.write_str_blocking("1"), + b'2' => uart.write_str_blocking("2"), + b'3' => uart.write_str_blocking("3"), + b'4' => uart.write_str_blocking("4"), + b'5' => uart.write_str_blocking("5"), + b'6' => uart.write_str_blocking("6"), + b'7' => uart.write_str_blocking("7"), + b'8' => uart.write_str_blocking("8"), + b'9' => uart.write_str_blocking("9"), + _ => uart.write_str_blocking("?"), + } + } +} diff --git a/examples/src/bin/ostimer_race_test.rs b/examples/src/bin/ostimer_race_test.rs new file mode 100644 index 000000000..720a058d5 --- /dev/null +++ b/examples/src/bin/ostimer_race_test.rs @@ -0,0 +1,393 @@ +//! # OSTIMER Race Condition Test +//! +//! This example tests for race conditions in the OSTIMER driver by: +//! - Scheduling alarms sequentially (hardware limitation: only one at a time) +//! - Reading the counter during interrupt-heavy periods +//! - Testing concurrent timer operations +//! - Stress testing interrupt handling + +#![no_std] +#![no_main] + +use core::sync::atomic::{AtomicU32, Ordering}; + +use embassy_executor::Spawner; +use embassy_mcxa_examples::{init_ostimer0, init_uart2}; +use embassy_time::{Duration, Timer}; +use hal::bind_interrupts; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +// Global counters for race condition detection +static ALARM_CALLBACK_COUNT: AtomicU32 = AtomicU32::new(0); +static INTERRUPT_COUNT: AtomicU32 = AtomicU32::new(0); +static RACE_DETECTED: AtomicU32 = AtomicU32::new(0); + +// Alarm callback function +fn alarm_callback() { + let _count = ALARM_CALLBACK_COUNT.fetch_add(1, Ordering::SeqCst); + INTERRUPT_COUNT.fetch_add(1, Ordering::SeqCst); + + // Simulate some work in the callback to increase chance of races + for _ in 0..10 { + cortex_m::asm::nop(); + } +} + +fn report_default_handler(uart: &mut hal::uart::Uart) { + let snapshot = hal::interrupt::default_handler_snapshot(); + if snapshot.count == 0 { + return; + } + + uart.write_str_blocking("WARNING: DefaultHandler executed "); + write_u32(uart, snapshot.count); + uart.write_str_blocking(" time(s). Vector="); + write_u32(uart, snapshot.vector as u32); + uart.write_str_blocking(" CFSR=0x"); + write_hex32(uart, snapshot.cfsr); + uart.write_str_blocking(" HFSR=0x"); + write_hex32(uart, snapshot.hfsr); + uart.write_str_blocking(" PC=0x"); + write_hex32(uart, snapshot.stacked_pc); + uart.write_str_blocking(" LR=0x"); + write_hex32(uart, snapshot.stacked_lr); + uart.write_str_blocking(" SP=0x"); + write_hex32(uart, snapshot.stacked_sp); + uart.write_str_blocking("\n"); + + hal::interrupt::clear_default_handler_snapshot(); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(Default::default()); + + // Enable/clock OSTIMER0 and UART2 before touching their registers + unsafe { + init_ostimer0(hal::pac()); + init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + + uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); + + // The bind_interrupts! macro handles handler binding automatically + + // Initialize the OSTIMER time driver FIRST + hal::ostimer::time_driver::init( + hal::interrupt::Priority::from(3), + 1_000_000, // 1MHz clock + ); + + uart.write_str_blocking("Time driver initialized\n"); + + // Create OSTIMER instance + let ostimer = hal::ostimer::Ostimer::::new( + p.OSTIMER0, + hal::ostimer::Config { + init_match_max: true, + clock_frequency_hz: 1_000_000, + }, + hal::pac(), + ); + + uart.write_str_blocking("OSTIMER instance created\n"); + + // Test 1: Sequential alarm scheduling (OSTIMER only supports one alarm at a time) + uart.write_str_blocking("Test 1: Sequential alarm scheduling...\n"); + test_rapid_alarms(&ostimer, &mut uart).await; + report_default_handler(&mut uart); + + // Test 2: Counter reading during interrupts + uart.write_str_blocking("Test 2: Counter reading during interrupts...\n"); + test_counter_reading_during_interrupts(&ostimer, &mut uart).await; + report_default_handler(&mut uart); + + // Test 3: Concurrent timer operations + uart.write_str_blocking("Test 3: Concurrent timer operations...\n"); + test_concurrent_operations(&ostimer, &mut uart).await; + report_default_handler(&mut uart); + + // Test 4: Timer reset during operation + uart.write_str_blocking("Test 4: Timer reset during operation...\n"); + test_reset_during_operation(&ostimer, &mut uart, hal::pac()).await; + report_default_handler(&mut uart); + + // Report results + uart.write_str_blocking("Race condition test complete\n"); + uart.write_str_blocking("Callback count: "); + write_u32(&mut uart, ALARM_CALLBACK_COUNT.load(Ordering::SeqCst)); + uart.write_str_blocking("\nInterrupt count: "); + write_u32(&mut uart, INTERRUPT_COUNT.load(Ordering::SeqCst)); + uart.write_str_blocking("\nRaces detected: "); + write_u32(&mut uart, RACE_DETECTED.load(Ordering::SeqCst)); + uart.write_str_blocking("\n"); +} + +// Test rapid alarm scheduling to stress interrupt handling +async fn test_rapid_alarms( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, +) { + let initial_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); + + // Schedule 10 alarms sequentially (OSTIMER only supports one alarm at a time) + for _i in 0..10 { + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + let delay_us = 1000; // 1ms delay for each alarm + if ostimer.schedule_alarm_delay(&alarm, delay_us) { + // Wait for this alarm to complete before scheduling the next + Timer::after(Duration::from_micros(delay_us + 100)).await; + report_default_handler(uart); + } else { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm (match not ready)\n"); + } + } + + // All alarms should have completed by now + let final_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); + let expected_count = initial_count + 10; + + if final_count != expected_count { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Expected "); + write_u32(uart, expected_count); + uart.write_str_blocking(" callbacks, got "); + write_u32(uart, final_count); + uart.write_str_blocking("\n"); + } else { + uart.write_str_blocking("PASS: All rapid alarms executed\n"); + } +} + +// Test reading counter while interrupts are firing +async fn test_counter_reading_during_interrupts( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, +) { + let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + // Schedule an alarm that will fire soon + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + if !ostimer.schedule_alarm_delay(&alarm, 500) { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before counter stress\n"); + } + + // While alarm is pending, read the counter many times rapidly + // This tests if counter reading is atomic and doesn't get corrupted by interrupts + let mut last_counter = ostimer.now(); + let mut consistent_reads = 0; + let mut total_reads = 0; + + for _ in 0..1000 { + let current_counter = ostimer.now(); + total_reads += 1; + + // Check if counter is monotonically increasing (basic sanity check) + if current_counter >= last_counter { + consistent_reads += 1; + } + last_counter = current_counter; + + // Small delay between reads + for _ in 0..10 { + cortex_m::asm::nop(); + } + + report_default_handler(uart); + } + + // Wait for alarm to complete + Timer::after(Duration::from_millis(1)).await; + + let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + if consistent_reads == total_reads { + uart.write_str_blocking("PASS: Counter reading consistent during interrupts\n"); + } else { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Counter reading inconsistent: "); + write_u32(uart, consistent_reads); + uart.write_str_blocking("/"); + write_u32(uart, total_reads); + uart.write_str_blocking(" consistent\n"); + } + + if final_interrupt_count > initial_interrupt_count { + uart.write_str_blocking("PASS: Interrupt fired during counter reading test\n"); + } else { + uart.write_str_blocking("WARNING: No interrupt fired during counter reading test\n"); + } +} + +// Test concurrent timer operations (embassy-time + alarms) +async fn test_concurrent_operations( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, +) { + let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + // Start an embassy-time timer + let timer_future = Timer::after(Duration::from_millis(2)); + + // Schedule an alarm that should fire before the timer + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + if !ostimer.schedule_alarm_delay(&alarm, 1000) { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before concurrent operations\n"); + } + + // Wait for both to complete + timer_future.await; + + let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); + + if final_interrupt_count > initial_interrupt_count { + uart.write_str_blocking("PASS: Concurrent operations completed\n"); + } else { + uart.write_str_blocking("WARNING: No interrupts during concurrent operations\n"); + } +} + +// Test timer reset during active operations +async fn test_reset_during_operation( + ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, + uart: &mut hal::uart::Uart, + peripherals: &hal::pac::Peripherals, +) { + let initial_counter = ostimer.now(); + + // Schedule an alarm + let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); + if !ostimer.schedule_alarm_delay(&alarm, 2000) { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before reset test\n"); + } + + // Wait a bit then reset the timer + Timer::after(Duration::from_millis(1)).await; + ostimer.reset(peripherals); + + // Check counter after reset + let counter_after_reset = ostimer.now(); + + // Wait to see if the alarm still fires (it shouldn't after reset) + Timer::after(Duration::from_millis(2)).await; + + let final_counter = ostimer.now(); + + if counter_after_reset < initial_counter { + uart.write_str_blocking("PASS: Timer reset successful\n"); + } else { + RACE_DETECTED.fetch_add(1, Ordering::SeqCst); + uart.write_str_blocking("ERROR: Timer reset may have failed\n"); + } + + uart.write_str_blocking("Counter progression after reset: "); + write_u64(uart, initial_counter); + uart.write_str_blocking(" -> "); + write_u64(uart, counter_after_reset); + uart.write_str_blocking(" -> "); + write_u64(uart, final_counter); + uart.write_str_blocking("\n"); +} + +// Helper function to write a u32 value as decimal string +fn write_u32(uart: &mut hal::uart::Uart, value: u32) { + if value == 0 { + uart.write_str_blocking("0"); + return; + } + + let mut buffer = [0u8; 10]; // Enough for max u32 + let mut i = 0; + let mut v = value; + + while v > 0 { + buffer[i] = b'0' + (v % 10) as u8; + v /= 10; + i += 1; + } + + // Write digits in reverse order + while i > 0 { + i -= 1; + match buffer[i] { + b'0' => uart.write_str_blocking("0"), + b'1' => uart.write_str_blocking("1"), + b'2' => uart.write_str_blocking("2"), + b'3' => uart.write_str_blocking("3"), + b'4' => uart.write_str_blocking("4"), + b'5' => uart.write_str_blocking("5"), + b'6' => uart.write_str_blocking("6"), + b'7' => uart.write_str_blocking("7"), + b'8' => uart.write_str_blocking("8"), + b'9' => uart.write_str_blocking("9"), + _ => uart.write_str_blocking("?"), + } + } +} + +fn write_hex32(uart: &mut hal::uart::Uart, value: u32) { + let mut buf = [b'0'; 8]; + let mut tmp = value; + for i in (0..8).rev() { + let digit = (tmp & 0xF) as u8; + buf[i] = match digit { + 0..=9 => b'0' + digit, + 10..=15 => b'A' + (digit - 10), + _ => b'?', + }; + tmp >>= 4; + } + for b in &buf { + uart.write_byte(*b); + } +} + +// Helper function to write a u64 value as decimal string +fn write_u64(uart: &mut hal::uart::Uart, value: u64) { + if value == 0 { + uart.write_str_blocking("0"); + return; + } + + let mut buffer = [0u8; 20]; // Enough for max u64 + let mut i = 0; + let mut v = value; + + while v > 0 { + buffer[i] = b'0' + (v % 10) as u8; + v /= 10; + i += 1; + } + + // Write digits in reverse order + while i > 0 { + i -= 1; + match buffer[i] { + b'0' => uart.write_str_blocking("0"), + b'1' => uart.write_str_blocking("1"), + b'2' => uart.write_str_blocking("2"), + b'3' => uart.write_str_blocking("3"), + b'4' => uart.write_str_blocking("4"), + b'5' => uart.write_str_blocking("5"), + b'6' => uart.write_str_blocking("6"), + b'7' => uart.write_str_blocking("7"), + b'8' => uart.write_str_blocking("8"), + b'9' => uart.write_str_blocking("9"), + _ => uart.write_str_blocking("?"), + } + } +} diff --git a/examples/src/bin/rtc_alarm.rs b/examples/src/bin/rtc_alarm.rs new file mode 100644 index 000000000..dc07b5757 --- /dev/null +++ b/examples/src/bin/rtc_alarm.rs @@ -0,0 +1,84 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa as hal; +use embassy_mcxa_examples::init_uart2; +use hal::rtc::{RtcDateTime, RtcInterruptEnable}; +use hal::{uart, InterruptExt}; + +type MyRtc = hal::rtc::Rtc; + +use embassy_mcxa::bind_interrupts; +use {defmt_rtt as _, panic_probe as _}; + +bind_interrupts!(struct Irqs { + RTC => hal::rtc::RtcHandler; +}); + +#[used] +#[no_mangle] +static KEEP_RTC: unsafe extern "C" fn() = RTC; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + unsafe { + init_uart2(hal::pac()); + } + + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + + uart.write_str_blocking("\r\n=== RTC Alarm Example ===\r\n"); + + unsafe { hal::clocks::init_fro16k(hal::pac()) }; + + let rtc_config = hal::rtc::get_default_config(); + + let rtc = MyRtc::new(p.RTC0, rtc_config); + + let now = RtcDateTime { + year: 2025, + month: 10, + day: 15, + hour: 14, + minute: 30, + second: 0, + }; + + rtc.stop(); + + uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n"); + rtc.set_datetime(now); + + let mut alarm = now; + alarm.second += 10; + + rtc.set_alarm(alarm); + uart.write_str_blocking("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)\r\n"); + + rtc.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); + + unsafe { + hal::interrupt::RTC.enable(); + } + + unsafe { + cortex_m::interrupt::enable(); + } + + rtc.start(); + + uart.write_str_blocking("RTC started, waiting for alarm...\r\n"); + + loop { + if rtc.is_alarm_triggered() { + uart.write_str_blocking("\r\n*** ALARM TRIGGERED! ***\r\n"); + break; + } + } + + uart.write_str_blocking("Example complete - Test PASSED!\r\n"); +} diff --git a/examples/src/bin/uart_interrupt.rs b/examples/src/bin/uart_interrupt.rs new file mode 100644 index 000000000..100588727 --- /dev/null +++ b/examples/src/bin/uart_interrupt.rs @@ -0,0 +1,66 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::bind_interrupts; +use embassy_mcxa_examples::init_uart2; +use hal::interrupt::typelevel::Handler; +use hal::uart; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +// Bind LPUART2 interrupt to our handler +bind_interrupts!(struct Irqs { + LPUART2 => hal::uart::UartInterruptHandler; +}); + +#[used] +#[no_mangle] +static KEEP_LPUART2: unsafe extern "C" fn() = LPUART2; + +// Wrapper function for the interrupt handler +unsafe extern "C" fn lpuart2_handler() { + hal::uart::UartInterruptHandler::on_interrupt(); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let _p = hal::init(hal::config::Config::default()); + + // Enable/clock UART2 before touching its registers + unsafe { + init_uart2(hal::pac()); + } + let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); + + // Configure LPUART2 interrupt for UART operation BEFORE any UART usage + hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3)); + + // Manually install the interrupt handler and enable RX IRQs in the peripheral + unsafe { + hal::interrupt::LPUART2.install_handler(lpuart2_handler); + // Enable RX interrupts so the handler actually fires on incoming bytes + uart.enable_rx_interrupts(); + } + + // Print welcome message + uart.write_str_blocking("UART interrupt echo demo starting...\r\n"); + uart.write_str_blocking("Type characters to echo them back.\r\n"); + + // Log using defmt if enabled + defmt::info!("UART interrupt echo demo starting..."); + + loop { + // Check if we have received any data + if uart.rx_data_available() { + if let Some(byte) = uart.try_read_byte() { + // Echo it back + uart.write_byte(byte); + uart.write_str_blocking(" (received)\r\n"); + } + } else { + // No data available, wait a bit before checking again + cortex_m::asm::delay(12_000_000); // ~1 second at 12MHz + } + } +} diff --git a/examples/src/common/mod.rs b/examples/src/common/mod.rs new file mode 100644 index 000000000..8cb4590f8 --- /dev/null +++ b/examples/src/common/mod.rs @@ -0,0 +1,45 @@ +//! Shared board-specific helpers for the FRDM-MCXA276 examples. +//! These live with the examples so the HAL stays generic. + +use hal::{clocks, pins, reset}; +use {embassy_mcxa as hal, panic_probe as _}; + +/// Initialize clocks and pin muxing for UART2 debug console. +/// Safe to call multiple times; writes are idempotent for our use. +#[allow(dead_code)] +pub unsafe fn init_uart2(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_uart2_port2(p); + reset::release_reset_port2(p); + reset::release_reset_lpuart2(p); + pins::configure_uart2_pins_port2(); + clocks::select_uart2_clock(p); +} + +/// Initialize clocks for the LED GPIO/PORT used by the blink example. +#[allow(dead_code)] +pub unsafe fn init_led(p: &hal::pac::Peripherals) { + clocks::enable_led_port(p); + reset::release_reset_gpio3(p); + reset::release_reset_port3(p); +} + +/// Initialize clocks for OSTIMER0 (1 MHz source). +#[allow(dead_code)] +pub unsafe fn init_ostimer0(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_ostimer0(p); + reset::release_reset_ostimer0(p); + clocks::select_ostimer0_clock_1m(p); +} + +/// Initialize clocks and pin muxing for ADC. +#[allow(dead_code)] +pub unsafe fn init_adc(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_adc(p); + reset::release_reset_port1(p); + reset::release_reset_adc1(p); + pins::configure_adc_pins(); + clocks::select_adc_clock(p); +} diff --git a/examples/src/lib.rs b/examples/src/lib.rs new file mode 100644 index 000000000..cf4194559 --- /dev/null +++ b/examples/src/lib.rs @@ -0,0 +1,63 @@ +#![no_std] + +//! Shared board-specific helpers for the FRDM-MCXA276 examples. +//! These live with the examples so the HAL stays generic. + +use hal::{clocks, pins, reset}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Initialize clocks and pin muxing for UART2 debug console. +/// Safe to call multiple times; writes are idempotent for our use. +/// +/// # Safety +/// +/// Called only once to initialize the peripheral +#[allow(dead_code)] +pub unsafe fn init_uart2(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_uart2_port2(p); + reset::release_reset_port2(p); + reset::release_reset_lpuart2(p); + pins::configure_uart2_pins_port2(); + clocks::select_uart2_clock(p); +} + +/// Initialize clocks for the LED GPIO/PORT used by the blink example. +/// +/// # Safety +/// +/// Called only once to initialize the peripheral +#[allow(dead_code)] +pub unsafe fn init_led(p: &hal::pac::Peripherals) { + clocks::enable_led_port(p); + reset::release_reset_gpio3(p); + reset::release_reset_port3(p); +} + +/// Initialize clocks for OSTIMER0 (1 MHz source). +/// +/// # Safety +/// +/// Called only once to initialize the peripheral +#[allow(dead_code)] +pub unsafe fn init_ostimer0(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_ostimer0(p); + reset::release_reset_ostimer0(p); + clocks::select_ostimer0_clock_1m(p); +} + +/// Initialize clocks and pin muxing for ADC. +/// +/// # Safety +/// +/// Called only once to initialize the peripheral +#[allow(dead_code)] +pub unsafe fn init_adc(p: &hal::pac::Peripherals) { + clocks::ensure_frolf_running(p); + clocks::enable_adc(p); + reset::release_reset_port1(p); + reset::release_reset_adc1(p); + pins::configure_adc_pins(); + clocks::select_adc_clock(p); +} diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs deleted file mode 100644 index bd734f859..000000000 --- a/examples/uart_interrupt.rs +++ /dev/null @@ -1,69 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::interrupt::typelevel::Handler; -use hal::uart; - -mod common; - -use embassy_mcxa276::bind_interrupts; -use {defmt_rtt as _, panic_probe as _}; - -// Bind LPUART2 interrupt to our handler -bind_interrupts!(struct Irqs { - LPUART2 => hal::uart::UartInterruptHandler; -}); - -#[used] -#[no_mangle] -static KEEP_LPUART2: unsafe extern "C" fn() = LPUART2; - -// Wrapper function for the interrupt handler -unsafe extern "C" fn lpuart2_handler() { - hal::uart::UartInterruptHandler::on_interrupt(); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); - - // Enable/clock UART2 before touching its registers - unsafe { - common::init_uart2(hal::pac()); - } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); - - // Configure LPUART2 interrupt for UART operation BEFORE any UART usage - hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3)); - - // Manually install the interrupt handler and enable RX IRQs in the peripheral - unsafe { - hal::interrupt::LPUART2.install_handler(lpuart2_handler); - // Enable RX interrupts so the handler actually fires on incoming bytes - uart.enable_rx_interrupts(); - } - - // Print welcome message - uart.write_str_blocking("UART interrupt echo demo starting...\r\n"); - uart.write_str_blocking("Type characters to echo them back.\r\n"); - - // Log using defmt if enabled - defmt::info!("UART interrupt echo demo starting..."); - - loop { - // Check if we have received any data - if uart.rx_data_available() { - if let Some(byte) = uart.try_read_byte() { - // Echo it back - uart.write_byte(byte); - uart.write_str_blocking(" (received)\r\n"); - } - } else { - // No data available, wait a bit before checking again - cortex_m::asm::delay(12_000_000); // ~1 second at 12MHz - } - } -} diff --git a/memory.x b/memory.x deleted file mode 100644 index b47534f18..000000000 --- a/memory.x +++ /dev/null @@ -1,10 +0,0 @@ -/* Memory layout for MCXA276 - RAM execution with cortex-m-rt */ -MEMORY -{ - /* FLASH and RAM overlap for RAM-execution experiments. */ - FLASH : ORIGIN = 0x20000000, LENGTH = 128K - /* RAM overlaps FLASH */ - RAM : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* Leave symbol and section boundary definitions to cortex-m-rt's link.x. */ diff --git a/src/lib.rs b/src/lib.rs index 9899564d8..4e5ac0109 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -62,29 +62,29 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { peripherals } -/// Optional hook called by cortex-m-rt before RAM init. -/// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state -/// left by soft resets/debug sessions. -/// -/// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor' -/// feature is incompatible with our setup because it expects __vector_table to be -/// defined differently than how our RAM-based linker script arranges it. -#[no_mangle] -pub unsafe extern "C" fn __pre_init() { - // Set the VTOR to point to the interrupt vector table in RAM - // This is required since code runs from RAM on this MCU - crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32); +// /// Optional hook called by cortex-m-rt before RAM init. +// /// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state +// /// left by soft resets/debug sessions. +// /// +// /// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor' +// /// feature is incompatible with our setup because it expects __vector_table to be +// /// defined differently than how our RAM-based linker script arranges it. +// #[no_mangle] +// pub unsafe extern "C" fn __pre_init() { +// // Set the VTOR to point to the interrupt vector table in RAM +// // This is required since code runs from RAM on this MCU +// crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32); - // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs. - let nvic = &*cortex_m::peripheral::NVIC::PTR; - for i in 0..4 { - // 4 words x 32 = 128 IRQs - nvic.icer[i].write(0xFFFF_FFFF); - nvic.icpr[i].write(0xFFFF_FFFF); - } - // Do NOT touch peripheral registers here: clocks may be off and accesses can fault. - crate::interrupt::clear_default_handler_snapshot(); -} +// // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs. +// let nvic = &*cortex_m::peripheral::NVIC::PTR; +// for i in 0..4 { +// // 4 words x 32 = 128 IRQs +// nvic.icer[i].write(0xFFFF_FFFF); +// nvic.icpr[i].write(0xFFFF_FFFF); +// } +// // Do NOT touch peripheral registers here: clocks may be off and accesses can fault. +// crate::interrupt::clear_default_handler_snapshot(); +// } /// Internal helper to dispatch a type-level interrupt handler. #[inline(always)] -- cgit From 4979747286af4cd7bab43f8048b0ce6f00cc5ab6 Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 14 Nov 2025 14:39:23 +0100 Subject: Plumb clocks changes to lpuart --- src/clocks/mod.rs | 301 ++++++++++++++++++++++++++++++++----------- src/clocks/periph_helpers.rs | 3 +- src/lib.rs | 14 +- src/lpuart/buffered.rs | 11 +- src/lpuart/mod.rs | 136 ++++++------------- 5 files changed, 291 insertions(+), 174 deletions(-) diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index ad48a9cf2..63a8fb64d 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -1,66 +1,157 @@ //! Clock control helpers (no magic numbers, PAC field access only). //! Provides reusable gate abstractions for peripherals used by the examples. +use core::cell::RefCell; + use mcxa_pac::scg0::{ firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}, sirccsr::{SircClkPeriphEn, Sircsten}, }; +use periph_helpers::SPConfHelper; use crate::pac; pub mod periph_helpers; -// /// Trait describing an AHB clock gate that can be toggled through MRCC. -// pub trait Gate { -// /// Enable the clock gate. -// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock); +/// Trait describing an AHB clock gate that can be toggled through MRCC. +pub trait Gate { + type MrccPeriphConfig: SPConfHelper; -// /// Return whether the clock gate is currently enabled. -// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool; -// } + /// Enable the clock gate. + unsafe fn enable_clock(); -// /// Enable a clock gate for the given peripheral set. -// #[inline] -// pub unsafe fn enable(peripherals: &pac::Peripherals) { -// let mrcc = &peripherals.mrcc0; -// G::enable(mrcc); -// while !G::is_enabled(mrcc) {} -// core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); -// } + /// Disable the clock gate. + unsafe fn disable_clock(); -// /// Check whether a gate is currently enabled. -// #[inline] -// pub fn is_enabled(peripherals: &pac::Peripherals) -> bool { -// G::is_enabled(&peripherals.mrcc0) -// } + /// Drive the peripheral into reset. + unsafe fn assert_reset(); -// macro_rules! impl_cc_gate { -// ($name:ident, $reg:ident, $field:ident) => { -// pub struct $name; - -// impl Gate for $name { -// #[inline] -// unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) { -// mrcc.$reg().modify(|_, w| w.$field().enabled()); -// } - -// #[inline] -// fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool { -// mrcc.$reg().read().$field().is_enabled() -// } -// } -// }; -// } + /// Drive the peripheral out of reset. + unsafe fn release_reset(); -// pub mod gate { -// use super::*; + /// Return whether the clock gate is currently enabled. + fn is_clock_enabled() -> bool; -// impl_cc_gate!(Port2, mrcc_glb_cc1, port2); -// impl_cc_gate!(Port3, mrcc_glb_cc1, port3); -// impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0); -// impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2); -// impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3); -// impl_cc_gate!(Port1, mrcc_glb_cc1, port1); -// impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1); -// } + /// . + fn is_reset_released() -> bool; +} + +#[inline] +pub unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Result { + let freq = enable::(cfg)?; + pulse_reset::(); + Ok(freq) +} + +/// Enable a clock gate for the given peripheral set. +#[inline] +pub unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result { + G::enable_clock(); + while !G::is_clock_enabled() {} + core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); + + let freq = critical_section::with(|cs| { + let clocks = CLOCKS.borrow_ref(cs); + let clocks = clocks.as_ref().ok_or(ClockError::NeverInitialized)?; + cfg.post_enable_config(clocks) + }); + + freq.inspect_err(|_e| { + G::disable_clock(); + }) +} + +pub unsafe fn disable() { + G::disable_clock(); +} + +/// Check whether a gate is currently enabled. +#[inline] +pub fn is_clock_enabled() -> bool { + G::is_clock_enabled() +} + +/// Release a reset line for the given peripheral set. +#[inline] +pub unsafe fn release_reset() { + G::release_reset(); +} + +/// Assert a reset line for the given peripheral set. +#[inline] +pub unsafe fn assert_reset() { + G::assert_reset(); +} + +/// Pulse a reset line (assert then release) with a short delay. +#[inline] +pub unsafe fn pulse_reset() { + G::assert_reset(); + cortex_m::asm::nop(); + cortex_m::asm::nop(); + G::release_reset(); +} + +macro_rules! impl_cc_gate { + ($name:ident, $reg:ident, $field:ident, $config:ty) => { + impl Gate for crate::peripherals::$name { + type MrccPeriphConfig = $config; + + #[inline] + unsafe fn enable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_, w| w.$field().enabled()); + } + + #[inline] + unsafe fn disable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_r, w| w.$field().disabled()); + } + + #[inline] + fn is_clock_enabled() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().read().$field().is_enabled() + } + + #[inline] + unsafe fn release_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_, w| w.$field().enabled()); + } + + #[inline] + unsafe fn assert_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_, w| w.$field().disabled()); + } + + #[inline] + fn is_reset_released() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().read().$field().is_enabled() + } + } + }; +} + +pub struct UnimplementedConfig; +impl SPConfHelper for UnimplementedConfig { + fn post_enable_config(&self, _clocks: &Clocks) -> Result { + Err(ClockError::UnimplementedConfig) + } +} + +pub mod gate { + use super::{periph_helpers::LpuartConfig, *}; + + impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, UnimplementedConfig); + impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, UnimplementedConfig); + impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, UnimplementedConfig); + impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, UnimplementedConfig); + impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig); + impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, UnimplementedConfig); + impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, UnimplementedConfig); +} // /// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. // pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) { @@ -113,20 +204,6 @@ pub mod periph_helpers; // mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); // } -// pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) { -// let vbat = &peripherals.vbat0; -// // Enable FRO16K oscillator -// vbat.froctla().modify(|_, w| w.fro_en().set_bit()); - -// // Lock the control register -// vbat.frolcka().modify(|_, w| w.lock().set_bit()); - -// // Enable clock outputs to both VSYS and VDD_CORE domains -// // Bit 0: clk_16k0 to VSYS domain -// // Bit 1: clk_16k1 to VDD_CORE domain -// vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) }); -// } - // pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { // enable::(peripherals); // enable::(peripherals); @@ -271,6 +348,7 @@ pub struct ClocksConfig { pub firc: Option, // NOTE: I don't think we *can* disable the SIRC? pub sirc: SircConfig, + pub fro16k: Option, } // FIRC/FRO180M @@ -340,17 +418,30 @@ pub struct Clocks { pub fro_lf_div: Option, // // End FRO12M stuff + + pub clk_16k_vsys: Option, + pub clk_16k_vdd_core: Option, pub main_clk: Option, pub pll1_clk: Option, } -static CLOCKS: critical_section::Mutex> = critical_section::Mutex::new(None); +#[non_exhaustive] +pub struct Fro16KConfig { + pub vsys_domain_active: bool, + pub vdd_core_domain_active: bool, +} + +static CLOCKS: critical_section::Mutex>> = critical_section::Mutex::new(RefCell::new(None)); +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[non_exhaustive] pub enum ClockError { + NeverInitialized, AlreadyInitialized, BadConfig { clock: &'static str, reason: &'static str }, NotImplemented { clock: &'static str }, + UnimplementedConfig, } struct ClockOperator<'a> { @@ -360,6 +451,7 @@ struct ClockOperator<'a> { _mrcc0: pac::Mrcc0, scg0: pac::Scg0, syscon: pac::Syscon, + vbat0: pac::Vbat0, } impl ClockOperator<'_> { @@ -586,13 +678,52 @@ impl ClockOperator<'_> { }); } - todo!() + Ok(()) + } + + fn configure_fro16k_clocks(&mut self) -> Result<(), ClockError> { + let Some(fro16k) = self.config.fro16k.as_ref() else { + return Ok(()); + }; + // Enable FRO16K oscillator + self.vbat0.froctla().modify(|_, w| w.fro_en().set_bit()); + + // Lock the control register + self.vbat0.frolcka().modify(|_, w| w.lock().set_bit()); + + let Fro16KConfig { vsys_domain_active, vdd_core_domain_active } = fro16k; + + // Enable clock outputs to both VSYS and VDD_CORE domains + // Bit 0: clk_16k0 to VSYS domain + // Bit 1: clk_16k1 to VDD_CORE domain + // + // TODO: Define sub-fields for this register with a PAC patch? + let mut bits = 0; + if *vsys_domain_active { + bits |= 0b01; + self.clocks.clk_16k_vsys = Some(Clock { + frequency: 16_384, + power: PoweredClock::AlwaysEnabled, + }); + } + if *vdd_core_domain_active { + bits |= 0b10; + self.clocks.clk_16k_vdd_core = Some(Clock { + frequency: 16_384, + power: PoweredClock::AlwaysEnabled, + }); + } + self.vbat0.froclke().modify(|_r, w| { + unsafe { w.clke().bits(bits) } + }); + + Ok(()) } } pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { critical_section::with(|cs| { - if CLOCKS.borrow(cs).is_some() { + if CLOCKS.borrow_ref(cs).is_some() { Err(ClockError::AlreadyInitialized) } else { Ok(()) @@ -607,12 +738,20 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { _mrcc0: unsafe { pac::Mrcc0::steal() }, scg0: unsafe { pac::Scg0::steal() }, syscon: unsafe { pac::Syscon::steal() }, + vbat0: unsafe { pac::Vbat0::steal() }, }; operator.configure_firc_clocks()?; operator.configure_sirc_clocks()?; + operator.configure_fro16k_clocks()?; // TODO, everything downstream + critical_section::with(|cs| { + let mut clks = CLOCKS.borrow_ref_mut(cs); + assert!(clks.is_none(), "Clock setup race!"); + *clks = Some(clocks); + }); + Ok(()) } @@ -621,7 +760,8 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { /// NOTE: Clocks implements `Clone`, pub fn with_clocks R>(f: F) -> Option { critical_section::with(|cs| { - let c = CLOCKS.borrow(cs).as_ref()?; + let c = CLOCKS.borrow_ref(cs); + let c = c.as_ref()?; Some(f(c)) }) } @@ -629,20 +769,32 @@ pub fn with_clocks R>(f: F) -> Option { impl Clocks { pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result { let Some(clk) = self.fro_lf_div.as_ref() else { - return Err(ClockError::BadConfig { clock: "fro_lf_div", reason: "required but not active" }); + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "required but not active", + }); }; if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { clock: "fro_lf_div", reason: "not low power active" }); + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "not low power active", + }); } Ok(clk.frequency) } pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result { let Some(clk) = self.fro_hf_div.as_ref() else { - return Err(ClockError::BadConfig { clock: "fro_hf_div", reason: "required but not active" }); + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "required but not active", + }); }; if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { clock: "fro_hf_div", reason: "not low power active" }); + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "not low power active", + }); } Ok(clk.frequency) } @@ -657,10 +809,16 @@ impl Clocks { pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result { let Some(clk) = self.clk_1m.as_ref() else { - return Err(ClockError::BadConfig { clock: "clk_1m", reason: "required but not active" }); + return Err(ClockError::BadConfig { + clock: "clk_1m", + reason: "required but not active", + }); }; if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { clock: "clk_1m", reason: "not low power active" }); + return Err(ClockError::BadConfig { + clock: "clk_1m", + reason: "not low power active", + }); } Ok(clk.frequency) } @@ -668,5 +826,4 @@ impl Clocks { pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result { Err(ClockError::NotImplemented { clock: "pll1_clk_div" }) } - } diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index c4d4e9e3b..4d186acf8 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -7,6 +7,7 @@ pub trait SPConfHelper { // config types +#[derive(Debug, Clone, Copy)] pub enum LpuartClockSel { /// FRO12M/FRO_LF/SIRC clock source, passed through divider /// "fro_lf_div" @@ -45,7 +46,7 @@ pub struct LpuartConfig { pub div: Div8, /// Which instance is this? // NOTE: should not be user settable - instance: LpuartInstance, + pub(crate) instance: LpuartInstance, } // impls diff --git a/src/lib.rs b/src/lib.rs index 9899564d8..e3e603ef2 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -16,7 +16,19 @@ pub mod ostimer; pub mod rtc; pub mod uart; -embassy_hal_internal::peripherals!(LPUART2, OSTIMER0, GPIO, RTC0, ADC1,); +embassy_hal_internal::peripherals!( + PORT1, + PORT2, + PORT3, + LPUART2, + OSTIMER0, + GPIO, + PIO2_2, + PIO2_3, + GPIO3, + RTC0, + ADC1, +); /// Get access to the PAC Peripherals for low-level register access. /// This is a lazy-initialized singleton that can be called after init(). diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index a617c10a5..7b575c086 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -212,10 +212,19 @@ impl<'a> BufferedLpuart<'a> { config.enable_tx = true; config.enable_rx = true; + // Enable clocks + let conf = LpuartConfig { + power: config.power, + source: config.source, + div: config.div, + instance: T::CLOCK_INSTANCE, + }; + let clock_freq = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; + // Perform standard initialization perform_software_reset(regs); disable_transceiver(regs); - configure_baudrate(regs, config.baudrate_bps, config.clock)?; + configure_baudrate(regs, config.baudrate_bps, clock_freq)?; configure_frame_format(regs, &config); configure_control_settings(regs, &config); configure_fifo(regs, &config); diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 35b531421..41ec951ec 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -3,6 +3,8 @@ use core::marker::PhantomData; use embassy_hal_internal::{Peri, PeripheralType}; use paste::paste; +use crate::clocks::periph_helpers::{LpuartClockSel, LpuartConfig}; +use crate::clocks::{enable_and_reset, ClockError, Div8, Gate, PoweredClock}; use crate::pac::lpuart0::baud::Sbns as StopBits; use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; @@ -18,70 +20,7 @@ pub mod buffered; // Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API // Pin and Clock initialization is currently done at the examples level. -// --- START LIB --- - -// Use our own instance of Peripherals, until we align `lib.rs` with the EMBASSY-IMXRT approach -// Inlined peripherals_definition! to bypass the `Peripherals::take_with_cs()` check -// SHOULD NOT BE USED IN THE FINAL VERSION -pub mod lib { - // embassy_hal_internal::peripherals!(LPUART2, PIO2_2, PIO2_3) - - embassy_hal_internal::peripherals_definition!(LPUART2, PIO2_2, PIO2_3,); - #[doc = r" Struct containing all the peripheral singletons."] - #[doc = r""] - #[doc = r" To obtain the peripherals, you must initialize the HAL, by calling [`crate::init`]."] - #[allow(non_snake_case)] - pub struct Peripherals { - #[doc = concat!(stringify!(LPUART2)," peripheral")] - pub LPUART2: embassy_hal_internal::Peri<'static, peripherals::LPUART2>, - #[doc = concat!(stringify!(PIO2_2)," peripheral")] - pub PIO2_2: embassy_hal_internal::Peri<'static, peripherals::PIO2_2>, - #[doc = concat!(stringify!(PIO2_3)," peripheral")] - pub PIO2_3: embassy_hal_internal::Peri<'static, peripherals::PIO2_3>, - } - impl Peripherals { - #[doc = r"Returns all the peripherals *once*"] - #[inline] - pub(crate) fn take() -> Self { - critical_section::with(Self::take_with_cs) - } - #[doc = r"Returns all the peripherals *once*"] - #[inline] - pub(crate) fn take_with_cs(_cs: critical_section::CriticalSection) -> Self { - #[no_mangle] - static mut _EMBASSY_DEVICE_PERIPHERALS2: bool = false; // ALIGN: Temporary fix to use stub Peripherals - unsafe { - if _EMBASSY_DEVICE_PERIPHERALS2 { - panic!("init called more than once!") - } - _EMBASSY_DEVICE_PERIPHERALS2 = true; - Self::steal() - } - } - } - impl Peripherals { - #[doc = r" Unsafely create an instance of this peripheral out of thin air."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" You must ensure that you're only using one instance of this type at a time."] - #[inline] - pub unsafe fn steal() -> Self { - Self { - LPUART2: peripherals::LPUART2::steal(), - PIO2_2: peripherals::PIO2_2::steal(), - PIO2_3: peripherals::PIO2_3::steal(), - } - } - } - - /// Initialize HAL - pub fn init() -> Peripherals { - Peripherals::take() - } -} -// --- END LIB --- // --- START GPIO --- @@ -101,13 +40,13 @@ mod gpio { macro_rules! impl_gpio_pin { ($($pin:ident),*) => { $( - impl SealedPin for super::lib::peripherals::$pin {} + impl SealedPin for crate::peripherals::$pin {} - impl GpioPin for super::lib::peripherals::$pin {} + impl GpioPin for crate::peripherals::$pin {} - impl From for AnyPin { + impl From for AnyPin { // TODO: AJM: any reason we aren't using $pin? - fn from(_val: super::lib::peripherals::$pin) -> Self { + fn from(_val: crate::peripherals::$pin) -> Self { AnyPin } } @@ -143,18 +82,6 @@ use dma::Channel; // --- END DMA --- -// --- START CLOCK --- -mod clock { - #[derive(Debug, Clone, Copy)] - pub enum Clock { - FroLf, // Low-Frequency Free-Running Oscillator - } -} - -use clock::Clock; - -// --- END CLOCK --- - // ============================================================================ // MISC // ============================================================================ @@ -182,7 +109,8 @@ pub struct Info { /// Trait for LPUART peripheral instances #[allow(private_bounds)] -pub trait Instance: SealedInstance + PeripheralType + 'static + Send { +pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate { + const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance; type Interrupt: interrupt::typelevel::Interrupt; } @@ -190,7 +118,7 @@ macro_rules! impl_instance { ($($n:expr),*) => { $( paste!{ - impl SealedInstance for lib::peripherals::[] { + impl SealedInstance for crate::peripherals::[] { fn info() -> Info { Info { regs: unsafe { &*pac::[]::ptr() }, @@ -208,7 +136,9 @@ macro_rules! impl_instance { } } - impl Instance for lib::peripherals::[] { + impl Instance for crate::peripherals::[] { + const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance + = crate::clocks::periph_helpers::LpuartInstance::[]; type Interrupt = crate::interrupt::typelevel::[]; } } @@ -236,8 +166,7 @@ pub fn disable_transceiver(regs: Regs) { } /// Calculate and configure baudrate settings -pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result<()> { - let clock_freq = get_fc_freq(clock)?; +pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock_freq: u32) -> Result<()> { let (osr, sbr) = calculate_baudrate(baudrate_bps, clock_freq)?; // Configure BAUD register @@ -408,16 +337,6 @@ pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> Ok((osr, sbr)) } -pub fn get_fc_freq(clock: Clock) -> Result { - // This is a placeholder - actual implementation would query the clock system - // In real implementation, this would get the LPUART clock frequency - match clock { - Clock::FroLf => Ok(12_000_000), // Low frequency oscillator - #[allow(unreachable_patterns)] - _ => Err(Error::InvalidArgument), - } -} - /// Wait for all transmit operations to complete pub fn wait_for_tx_complete(regs: Regs) { // Wait for TX FIFO to empty @@ -504,7 +423,7 @@ macro_rules! impl_pin_trait { ($fcn:ident, $mode:ident, $($pin:ident, $alt:ident),*) => { paste! { $( - impl [<$mode:camel Pin>] for lib::peripherals::$pin { + impl [<$mode:camel Pin>] for crate::peripherals::$pin { fn [](&self) { let _alt = gpio::Alt::$alt; // todo!("Configure pin for LPUART function") @@ -553,6 +472,8 @@ pub enum Error { TxFifoFull, /// TX Busy TxBusy, + /// Clock Error + ClockSetup(ClockError), } /// A specialized Result type for LPUART operations @@ -565,10 +486,14 @@ pub type Result = core::result::Result; /// Lpuart config #[derive(Debug, Clone, Copy)] pub struct Config { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Clock source + pub source: LpuartClockSel, + /// Clock divisor + pub div: Div8, /// Baud rate in bits per second pub baudrate_bps: u32, - /// Clock - pub clock: Clock, /// Parity configuration pub parity_mode: Option, /// Number of data bits @@ -605,7 +530,6 @@ impl Default for Config { fn default() -> Self { Self { baudrate_bps: 115_200u32, - clock: Clock::FroLf, parity_mode: None, data_bits_count: DataBits::Data8, msb_firs: MsbFirst::LsbFirst, @@ -621,6 +545,9 @@ impl Default for Config { enable_tx: false, enable_rx: false, swap_txd_rxd: false, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: LpuartClockSel::FroLfDiv, + div: const { Div8::from_divisor(1).unwrap() }, } } } @@ -706,10 +633,21 @@ impl<'a, M: Mode> Lpuart<'a, M> { ) -> Result<()> { let regs = T::info().regs; + // Enable clocks + let conf = LpuartConfig { + power: config.power, + source: config.source, + div: config.div, + instance: T::CLOCK_INSTANCE, + }; + let clock_freq = unsafe { + enable_and_reset::(&conf).map_err(Error::ClockSetup)? + }; + // Perform initialization sequence perform_software_reset(regs); disable_transceiver(regs); - configure_baudrate(regs, config.baudrate_bps, config.clock)?; + configure_baudrate(regs, config.baudrate_bps, clock_freq)?; configure_frame_format(regs, &config); configure_control_settings(regs, &config); configure_fifo(regs, &config); -- cgit From 9f889d015ef5d373343ad6c769824e28be780e53 Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 14 Nov 2025 15:35:20 +0100 Subject: Implement SPConfHelper for OSTimer and ADC --- src/board.rs | 14 ---- src/clocks/mod.rs | 71 ++++++++++++++---- src/clocks/periph_helpers.rs | 171 ++++++++++++++++++++++++++++++++++++++++++- src/lpuart/mod.rs | 12 +-- 4 files changed, 229 insertions(+), 39 deletions(-) delete mode 100644 src/board.rs diff --git a/src/board.rs b/src/board.rs deleted file mode 100644 index fa679e82c..000000000 --- a/src/board.rs +++ /dev/null @@ -1,14 +0,0 @@ -use crate::{clocks, pac, pins}; - -/// Initialize clocks and pin muxing for UART2 debug console. -pub unsafe fn init_uart2(p: &pac::Peripherals) { - clocks::ensure_frolf_running(p); - clocks::enable_uart2_port2(p); - pins::configure_uart2_pins_port2(); - clocks::select_uart2_clock(p); -} - -/// Initialize clocks for the LED GPIO/PORT used by the blink example. -pub unsafe fn init_led(p: &pac::Peripherals) { - clocks::enable_led_port(p); -} diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index 63a8fb64d..db41db628 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -141,16 +141,23 @@ impl SPConfHelper for UnimplementedConfig { } } +pub struct NoConfig; +impl SPConfHelper for NoConfig { + fn post_enable_config(&self, _clocks: &Clocks) -> Result { + Ok(0) + } +} + pub mod gate { - use super::{periph_helpers::LpuartConfig, *}; + use super::{periph_helpers::{AdcConfig, LpuartConfig, OsTimerConfig}, *}; - impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, UnimplementedConfig); - impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, UnimplementedConfig); - impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, UnimplementedConfig); - impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, UnimplementedConfig); + impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, NoConfig); + impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, NoConfig); + impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, NoConfig); + impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, OsTimerConfig); impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig); - impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, UnimplementedConfig); - impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, UnimplementedConfig); + impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig); + impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, AdcConfig); } // /// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. @@ -418,7 +425,6 @@ pub struct Clocks { pub fro_lf_div: Option, // // End FRO12M stuff - pub clk_16k_vsys: Option, pub clk_16k_vdd_core: Option, pub main_clk: Option, @@ -691,7 +697,10 @@ impl ClockOperator<'_> { // Lock the control register self.vbat0.frolcka().modify(|_, w| w.lock().set_bit()); - let Fro16KConfig { vsys_domain_active, vdd_core_domain_active } = fro16k; + let Fro16KConfig { + vsys_domain_active, + vdd_core_domain_active, + } = fro16k; // Enable clock outputs to both VSYS and VDD_CORE domains // Bit 0: clk_16k0 to VSYS domain @@ -713,9 +722,7 @@ impl ClockOperator<'_> { power: PoweredClock::AlwaysEnabled, }); } - self.vbat0.froclke().modify(|_r, w| { - unsafe { w.clke().bits(bits) } - }); + self.vbat0.froclke().modify(|_r, w| unsafe { w.clke().bits(bits) }); Ok(()) } @@ -783,6 +790,22 @@ impl Clocks { Ok(clk.frequency) } + pub fn ensure_fro_hf_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_hf.as_ref() else { + return Err(ClockError::BadConfig { + clock: "fro_hf", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "fro_hf", + reason: "not low power active", + }); + } + Ok(clk.frequency) + } + pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result { let Some(clk) = self.fro_hf_div.as_ref() else { return Err(ClockError::BadConfig { @@ -803,8 +826,28 @@ impl Clocks { Err(ClockError::NotImplemented { clock: "clk_in" }) } - pub fn ensure_clk_16k_active(&self, _at_level: &PoweredClock) -> Result { - Err(ClockError::NotImplemented { clock: "clk_16k" }) + pub fn ensure_clk_16k_vsys_active(&self, _at_level: &PoweredClock) -> Result { + // NOTE: clk_16k is always active in low power mode + Ok(self + .clk_16k_vsys + .as_ref() + .ok_or(ClockError::BadConfig { + clock: "clk_16k_vsys", + reason: "required but not active", + })? + .frequency) + } + + pub fn ensure_clk_16k_vdd_core_active(&self, _at_level: &PoweredClock) -> Result { + // NOTE: clk_16k is always active in low power mode + Ok(self + .clk_16k_vdd_core + .as_ref() + .ok_or(ClockError::BadConfig { + clock: "clk_16k_vdd_core", + reason: "required but not active", + })? + .frequency) } pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result { diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index 4d186acf8..de767ef87 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -1,4 +1,4 @@ -use super::{ClockError, Clocks, Div8, PoweredClock}; +use super::{ClockError, Clocks, PoweredClock}; use crate::pac; pub trait SPConfHelper { @@ -7,6 +7,59 @@ pub trait SPConfHelper { // config types +/// This type represents a divider in the range 1..=16. +/// +/// At a hardware level, this is an 8-bit register from 0..=15, +/// which adds one. +/// +/// While the *clock* domain seems to use 8-bit dividers, the *peripheral* domain +/// seems to use 4 bit dividers! +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub struct Div4(pub(super) u8); + +impl Div4 { + /// Store a "raw" divisor value that will divide the source by + /// `(n + 1)`, e.g. `Div4::from_raw(0)` will divide the source + /// by 1, and `Div4::from_raw(15)` will divide the source by + /// 16. + pub const fn from_raw(n: u8) -> Option { + if n > 0b1111 { + None + } else { + Some(Self(n)) + } + } + + /// Store a specific divisor value that will divide the source + /// by `n`. e.g. `Div4::from_divisor(1)` will divide the source + /// by 1, and `Div4::from_divisor(16)` will divide the source + /// by 16. + /// + /// Will return `None` if `n` is not in the range `1..=16`. + /// Consider [`Self::from_raw`] for an infallible version. + pub const fn from_divisor(n: u8) -> Option { + let Some(n) = n.checked_sub(1) else { + return None; + }; + if n > 0b1111 { + return None; + } + Some(Self(n)) + } + + /// Convert into "raw" bits form + #[inline(always)] + pub const fn into_bits(self) -> u8 { + self.0 + } + + /// Convert into "divisor" form, as a u32 for convenient frequency math + #[inline(always)] + pub const fn into_divisor(self) -> u32 { + self.0 as u32 + 1 + } +} + #[derive(Debug, Clone, Copy)] pub enum LpuartClockSel { /// FRO12M/FRO_LF/SIRC clock source, passed through divider @@ -43,12 +96,41 @@ pub struct LpuartConfig { /// Clock source pub source: LpuartClockSel, /// Clock divisor - pub div: Div8, + pub div: Div4, /// Which instance is this? // NOTE: should not be user settable pub(crate) instance: LpuartInstance, } +pub enum OstimerClockSel { + /// 16k clock, sourced from FRO16K (Vdd Core) + Clk16kVddCore, + /// 1 MHz Clock sourced from FRO12M + Clk1M, + /// Disabled + None, +} + +pub struct OsTimerConfig { + pub power: PoweredClock, + pub source: OstimerClockSel, +} + +pub enum AdcClockSel { + FroLfDiv, + FroHf, + ClkIn, + Clk1M, + Pll1ClkDiv, + None, +} + +pub struct AdcConfig { + pub power: PoweredClock, + pub source: AdcClockSel, + pub div: Div4, +} + // impls impl SPConfHelper for LpuartConfig { @@ -80,7 +162,7 @@ impl SPConfHelper for LpuartConfig { (freq, Mux::ClkrootFunc3) } LpuartClockSel::Clk16K => { - let freq = clocks.ensure_clk_16k_active(&self.power)?; + let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?; (freq, Mux::ClkrootFunc4) } LpuartClockSel::Clk1M => { @@ -124,3 +206,86 @@ impl SPConfHelper for LpuartConfig { Ok(freq / self.div.into_divisor()) } } + +impl SPConfHelper for OsTimerConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + Ok(match self.source { + OstimerClockSel::Clk16kVddCore => { + let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?; + mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_16k()); + freq + } + OstimerClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); + freq + } + OstimerClockSel::None => { + mrcc0.mrcc_ostimer0_clksel().write(|w| unsafe { w.mux().bits(0b11) }); + 0 + } + }) + } +} + +impl SPConfHelper for AdcConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + use mcxa_pac::mrcc0::mrcc_adc_clksel::Mux; + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + let (freq, variant) = match self.source { + AdcClockSel::FroLfDiv => { + let freq = clocks.ensure_fro_lf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc0) + } + AdcClockSel::FroHf => { + let freq = clocks.ensure_fro_hf_active(&self.power)?; + (freq, Mux::ClkrootFunc1) + } + AdcClockSel::ClkIn => { + let freq = clocks.ensure_clk_in_active(&self.power)?; + (freq, Mux::ClkrootFunc3) + } + AdcClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + (freq, Mux::ClkrootFunc5) + } + AdcClockSel::Pll1ClkDiv => { + let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; + (freq, Mux::ClkrootFunc6) + } + AdcClockSel::None => { + mrcc0.mrcc_adc_clksel().write(|w| unsafe { + // no ClkrootFunc7, just write manually for now + w.mux().bits(0b111) + }); + mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { + w.reset().on(); + w.halt().on(); + w + }); + return Ok(0); + } + }; + + // set clksel + mrcc0.mrcc_adc_clksel().modify(|_r, w| w.mux().variant(variant)); + + // Set up clkdiv + mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { + w.halt().on(); + w.reset().on(); + w + }); + mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { + w.halt().off(); + w.reset().off(); + unsafe { w.div().bits(self.div.into_bits()) }; + w + }); + + while mrcc0.mrcc_adc_clkdiv().read().unstab().is_on() {} + + Ok(freq / self.div.into_divisor()) + } +} diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 41ec951ec..35b4db24c 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -4,7 +4,7 @@ use embassy_hal_internal::{Peri, PeripheralType}; use paste::paste; use crate::clocks::periph_helpers::{LpuartClockSel, LpuartConfig}; -use crate::clocks::{enable_and_reset, ClockError, Div8, Gate, PoweredClock}; +use crate::clocks::{enable_and_reset, ClockError, periph_helpers::Div4, Gate, PoweredClock}; use crate::pac::lpuart0::baud::Sbns as StopBits; use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; @@ -20,8 +20,6 @@ pub mod buffered; // Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API // Pin and Clock initialization is currently done at the examples level. - - // --- START GPIO --- mod gpio { @@ -491,7 +489,7 @@ pub struct Config { /// Clock source pub source: LpuartClockSel, /// Clock divisor - pub div: Div8, + pub div: Div4, /// Baud rate in bits per second pub baudrate_bps: u32, /// Parity configuration @@ -547,7 +545,7 @@ impl Default for Config { swap_txd_rxd: false, power: PoweredClock::NormalEnabledDeepSleepDisabled, source: LpuartClockSel::FroLfDiv, - div: const { Div8::from_divisor(1).unwrap() }, + div: const { Div4::from_divisor(1).unwrap() }, } } } @@ -640,9 +638,7 @@ impl<'a, M: Mode> Lpuart<'a, M> { div: config.div, instance: T::CLOCK_INSTANCE, }; - let clock_freq = unsafe { - enable_and_reset::(&conf).map_err(Error::ClockSetup)? - }; + let clock_freq = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; // Perform initialization sequence perform_software_reset(regs); -- cgit From 9b91d886e6a5067d6a553715a053db653af55ca6 Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 14 Nov 2025 15:37:48 +0100 Subject: Cargo fmt --- src/clocks/mod.rs | 9 ++++----- src/lib.rs | 14 +------------- src/lpuart/mod.rs | 4 ++-- 3 files changed, 7 insertions(+), 20 deletions(-) diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index db41db628..24e118e38 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -2,10 +2,8 @@ //! Provides reusable gate abstractions for peripherals used by the examples. use core::cell::RefCell; -use mcxa_pac::scg0::{ - firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}, - sirccsr::{SircClkPeriphEn, Sircsten}, -}; +use mcxa_pac::scg0::firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}; +use mcxa_pac::scg0::sirccsr::{SircClkPeriphEn, Sircsten}; use periph_helpers::SPConfHelper; use crate::pac; @@ -149,7 +147,8 @@ impl SPConfHelper for NoConfig { } pub mod gate { - use super::{periph_helpers::{AdcConfig, LpuartConfig, OsTimerConfig}, *}; + use super::periph_helpers::{AdcConfig, LpuartConfig, OsTimerConfig}; + use super::*; impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, NoConfig); impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, NoConfig); diff --git a/src/lib.rs b/src/lib.rs index e3e603ef2..fd7d3cd07 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -16,19 +16,7 @@ pub mod ostimer; pub mod rtc; pub mod uart; -embassy_hal_internal::peripherals!( - PORT1, - PORT2, - PORT3, - LPUART2, - OSTIMER0, - GPIO, - PIO2_2, - PIO2_3, - GPIO3, - RTC0, - ADC1, -); +embassy_hal_internal::peripherals!(PORT1, PORT2, PORT3, LPUART2, OSTIMER0, GPIO, PIO2_2, PIO2_3, GPIO3, RTC0, ADC1,); /// Get access to the PAC Peripherals for low-level register access. /// This is a lazy-initialized singleton that can be called after init(). diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 35b4db24c..be69372a2 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -3,8 +3,8 @@ use core::marker::PhantomData; use embassy_hal_internal::{Peri, PeripheralType}; use paste::paste; -use crate::clocks::periph_helpers::{LpuartClockSel, LpuartConfig}; -use crate::clocks::{enable_and_reset, ClockError, periph_helpers::Div4, Gate, PoweredClock}; +use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig}; +use crate::clocks::{enable_and_reset, ClockError, Gate, PoweredClock}; use crate::pac::lpuart0::baud::Sbns as StopBits; use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; -- cgit From e799d6c8956ed3ea5ced65d58c3065a22927ad10 Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 14 Nov 2025 17:29:31 +0100 Subject: More work on examples --- examples/adc_interrupt.rs | 15 ++++-- examples/common/mod.rs | 38 +++++--------- examples/lpuart_buffered.rs | 5 +- examples/ostimer_alarm.rs | 7 +-- examples/ostimer_counter.rs | 8 ++- examples/ostimer_race_test.rs | 5 +- examples/uart_interrupt.rs | 100 ++++++++++++++++++------------------- src/adc.rs | 73 +++++++++++++++++---------- src/clocks/mod.rs | 12 ++++- src/clocks/periph_helpers.rs | 8 +++ src/lib.rs | 1 - src/lpuart/mod.rs | 2 +- src/ostimer.rs | 62 +++++++++++++---------- src/reset.rs | 112 ------------------------------------------ 14 files changed, 186 insertions(+), 262 deletions(-) delete mode 100644 src/reset.rs diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs index dc82cfd30..3be85ac75 100644 --- a/examples/adc_interrupt.rs +++ b/examples/adc_interrupt.rs @@ -2,6 +2,8 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa276::clocks::periph_helpers::{AdcClockSel, Div4}; +use embassy_mcxa276::clocks::PoweredClock; use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; use hal::uart; use mcxa_pac::adc1::cfg::{Pwrsel, Refsel}; @@ -30,10 +32,10 @@ async fn main(_spawner: Spawner) { common::init_uart2(hal::pac()); } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + // let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; + // let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); - uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); + // uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); unsafe { common::init_adc(hal::pac()); @@ -50,6 +52,9 @@ async fn main(_spawner: Spawner) { enable_conv_pause: false, conv_pause_delay: 0, fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), }; let adc = hal::adc::Adc::::new(p.ADC1, adc_config); @@ -66,7 +71,7 @@ async fn main(_spawner: Spawner) { conv_trigger_config.enable_hardware_trigger = false; adc.set_conv_trigger_config(0, &conv_trigger_config); - uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + // uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); adc.enable_interrupt(0x1); @@ -83,7 +88,7 @@ async fn main(_spawner: Spawner) { while !adc.is_interrupt_triggered() { // Wait until the interrupt is triggered } - uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); + // uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); //TBD need to print the value } } diff --git a/examples/common/mod.rs b/examples/common/mod.rs index 8c52c8e86..7b197a590 100644 --- a/examples/common/mod.rs +++ b/examples/common/mod.rs @@ -1,45 +1,31 @@ //! Shared board-specific helpers for the FRDM-MCXA276 examples. //! These live with the examples so the HAL stays generic. -use hal::{clocks, pins, reset}; +use hal::{clocks, pins}; use {embassy_mcxa276 as hal, panic_probe as _}; /// Initialize clocks and pin muxing for UART2 debug console. /// Safe to call multiple times; writes are idempotent for our use. #[allow(dead_code)] -pub unsafe fn init_uart2(p: &mcxa_pac::Peripherals) { - clocks::ensure_frolf_running(p); - clocks::enable_uart2_port2(p); - reset::release_reset_port2(p); - reset::release_reset_lpuart2(p); +pub unsafe fn init_uart2(_p: &mcxa_pac::Peripherals) { + // NOTE: Lpuart has been updated to properly enable + reset its own clocks. + // GPIO has not. + _ = clocks::enable_and_reset::(&clocks::NoConfig); pins::configure_uart2_pins_port2(); - clocks::select_uart2_clock(p); } /// Initialize clocks for the LED GPIO/PORT used by the blink example. #[allow(dead_code)] -pub unsafe fn init_led(p: &mcxa_pac::Peripherals) { - clocks::enable_led_port(p); - reset::release_reset_gpio3(p); - reset::release_reset_port3(p); -} - -/// Initialize clocks for OSTIMER0 (1 MHz source). -#[allow(dead_code)] -pub unsafe fn init_ostimer0(p: &mcxa_pac::Peripherals) { - clocks::ensure_frolf_running(p); - clocks::enable_ostimer0(p); - reset::release_reset_ostimer0(p); - clocks::select_ostimer0_clock_1m(p); +pub unsafe fn init_led(_p: &mcxa_pac::Peripherals) { + _ = clocks::enable_and_reset::(&clocks::NoConfig); + _ = clocks::enable_and_reset::(&clocks::NoConfig); } /// Initialize clocks and pin muxing for ADC. #[allow(dead_code)] -pub unsafe fn init_adc(p: &mcxa_pac::Peripherals) { - clocks::ensure_frolf_running(p); - clocks::enable_adc(p); - reset::release_reset_port1(p); - reset::release_reset_adc1(p); +pub unsafe fn init_adc(_p: &mcxa_pac::Peripherals) { + // NOTE: Lpuart has been updated to properly enable + reset its own clocks. + // GPIO has not. + _ = clocks::enable_and_reset::(&clocks::NoConfig); pins::configure_adc_pins(); - clocks::select_adc_clock(p); } diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs index 35d311143..6ae690c56 100644 --- a/examples/lpuart_buffered.rs +++ b/examples/lpuart_buffered.rs @@ -12,18 +12,17 @@ mod common; // Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver bind_interrupts!(struct Irqs { - LPUART2 => lpuart::buffered::BufferedInterruptHandler::; + LPUART2 => lpuart::buffered::BufferedInterruptHandler::; }); // Wrapper function for the interrupt handler unsafe extern "C" fn lpuart2_handler() { - lpuart::buffered::BufferedInterruptHandler::::on_interrupt(); + lpuart::buffered::BufferedInterruptHandler::::on_interrupt(); } #[embassy_executor::main] async fn main(_spawner: Spawner) { let _p = hal::init(hal::config::Config::default()); - let p2 = lpuart::lib::init(); unsafe { hal::interrupt::install_irq_handler(mcxa_pac::Interrupt::LPUART2, lpuart2_handler); diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs index 78ca4bbc5..4f29a2c7c 100644 --- a/examples/ostimer_alarm.rs +++ b/examples/ostimer_alarm.rs @@ -9,7 +9,7 @@ use {cortex_m, embassy_mcxa276 as hal}; mod common; -use embassy_mcxa276::bind_interrupts; +use embassy_mcxa276::{bind_interrupts, clocks::{periph_helpers::OstimerClockSel, PoweredClock}}; use {defmt_rtt as _, panic_probe as _}; // Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. @@ -50,9 +50,10 @@ async fn main(_spawner: Spawner) { // Create OSTIMER instance let config = hal::ostimer::Config { init_match_max: true, - clock_frequency_hz: 1_000_000, // 1MHz + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: OstimerClockSel::Clk1M, }; - let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config, hal::pac()); + let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config); // Create alarm with callback let alarm = hal::ostimer::Alarm::new() diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs index e95140a88..069e879d8 100644 --- a/examples/ostimer_counter.rs +++ b/examples/ostimer_counter.rs @@ -7,6 +7,7 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa276::clocks::{periph_helpers::OstimerClockSel, PoweredClock}; use embassy_time::{Duration, Timer}; use hal::bind_interrupts; use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; @@ -22,9 +23,6 @@ async fn main(_spawner: Spawner) { let p = hal::init(Default::default()); // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } unsafe { common::init_uart2(hal::pac()); } @@ -44,9 +42,9 @@ async fn main(_spawner: Spawner) { p.OSTIMER0, hal::ostimer::Config { init_match_max: true, - clock_frequency_hz: 1_000_000, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: OstimerClockSel::Clk1M, }, - hal::pac(), ); // Read initial counter value diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs index 368a3e52f..6e3d4ac21 100644 --- a/examples/ostimer_race_test.rs +++ b/examples/ostimer_race_test.rs @@ -12,6 +12,7 @@ use core::sync::atomic::{AtomicU32, Ordering}; use embassy_executor::Spawner; +use embassy_mcxa276::clocks::{periph_helpers::OstimerClockSel, PoweredClock}; use embassy_time::{Duration, Timer}; use hal::bind_interrupts; use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; @@ -98,9 +99,9 @@ async fn main(_spawner: Spawner) { p.OSTIMER0, hal::ostimer::Config { init_match_max: true, - clock_frequency_hz: 1_000_000, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: OstimerClockSel::Clk1M, }, - hal::pac(), ); uart.write_str_blocking("OSTIMER instance created\n"); diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs index bd734f859..190a4d850 100644 --- a/examples/uart_interrupt.rs +++ b/examples/uart_interrupt.rs @@ -2,68 +2,68 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::interrupt::typelevel::Handler; -use hal::uart; +// use embassy_mcxa276 as hal; +// use hal::interrupt::typelevel::Handler; +// use hal::uart; -mod common; +// mod common; -use embassy_mcxa276::bind_interrupts; -use {defmt_rtt as _, panic_probe as _}; +// use embassy_mcxa276::bind_interrupts; +// use {defmt_rtt as _, panic_probe as _}; -// Bind LPUART2 interrupt to our handler -bind_interrupts!(struct Irqs { - LPUART2 => hal::uart::UartInterruptHandler; -}); +// // Bind LPUART2 interrupt to our handler +// bind_interrupts!(struct Irqs { +// LPUART2 => hal::uart::UartInterruptHandler; +// }); -#[used] -#[no_mangle] -static KEEP_LPUART2: unsafe extern "C" fn() = LPUART2; +// #[used] +// #[no_mangle] +// static KEEP_LPUART2: unsafe extern "C" fn() = LPUART2; -// Wrapper function for the interrupt handler -unsafe extern "C" fn lpuart2_handler() { - hal::uart::UartInterruptHandler::on_interrupt(); -} +// // Wrapper function for the interrupt handler +// unsafe extern "C" fn lpuart2_handler() { +// hal::uart::UartInterruptHandler::on_interrupt(); +// } #[embassy_executor::main] async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); +// let _p = hal::init(hal::config::Config::default()); - // Enable/clock UART2 before touching its registers - unsafe { - common::init_uart2(hal::pac()); - } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); +// // Enable/clock UART2 before touching its registers +// unsafe { +// common::init_uart2(hal::pac()); +// } +// let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; +// let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); - // Configure LPUART2 interrupt for UART operation BEFORE any UART usage - hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3)); +// // Configure LPUART2 interrupt for UART operation BEFORE any UART usage +// hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3)); - // Manually install the interrupt handler and enable RX IRQs in the peripheral - unsafe { - hal::interrupt::LPUART2.install_handler(lpuart2_handler); - // Enable RX interrupts so the handler actually fires on incoming bytes - uart.enable_rx_interrupts(); - } +// // Manually install the interrupt handler and enable RX IRQs in the peripheral +// unsafe { +// hal::interrupt::LPUART2.install_handler(lpuart2_handler); +// // Enable RX interrupts so the handler actually fires on incoming bytes +// uart.enable_rx_interrupts(); +// } - // Print welcome message - uart.write_str_blocking("UART interrupt echo demo starting...\r\n"); - uart.write_str_blocking("Type characters to echo them back.\r\n"); +// // Print welcome message +// uart.write_str_blocking("UART interrupt echo demo starting...\r\n"); +// uart.write_str_blocking("Type characters to echo them back.\r\n"); - // Log using defmt if enabled - defmt::info!("UART interrupt echo demo starting..."); +// // Log using defmt if enabled +// defmt::info!("UART interrupt echo demo starting..."); - loop { - // Check if we have received any data - if uart.rx_data_available() { - if let Some(byte) = uart.try_read_byte() { - // Echo it back - uart.write_byte(byte); - uart.write_str_blocking(" (received)\r\n"); - } - } else { - // No data available, wait a bit before checking again - cortex_m::asm::delay(12_000_000); // ~1 second at 12MHz - } - } +// loop { +// // Check if we have received any data +// if uart.rx_data_available() { +// if let Some(byte) = uart.try_read_byte() { +// // Echo it back +// uart.write_byte(byte); +// uart.write_str_blocking(" (received)\r\n"); +// } +// } else { +// // No data available, wait a bit before checking again +// cortex_m::asm::delay(12_000_000); // ~1 second at 12MHz +// } +// } } diff --git a/src/adc.rs b/src/adc.rs index 655bf934f..b5ec5983f 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,6 +1,10 @@ //! ADC driver use core::sync::atomic::{AtomicBool, Ordering}; +use embassy_hal_internal::{Peri, PeripheralType}; + +use crate::clocks::periph_helpers::{AdcClockSel, AdcConfig, Div4}; +use crate::clocks::{enable_and_reset, Gate, PoweredClock}; use crate::pac; use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres}; use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts}; @@ -12,7 +16,7 @@ type Regs = pac::adc1::RegisterBlock; static INTERRUPT_TRIGGERED: AtomicBool = AtomicBool::new(false); // Token-based instance pattern like embassy-imxrt -pub trait Instance { +pub trait Instance: Gate + PeripheralType { fn ptr() -> *const Regs; } @@ -26,12 +30,12 @@ impl Instance for crate::peripherals::ADC1 { } // Also implement Instance for the Peri wrapper type -impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> { - #[inline(always)] - fn ptr() -> *const Regs { - pac::Adc1::ptr() - } -} +// impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> { +// #[inline(always)] +// fn ptr() -> *const Regs { +// pac::Adc1::ptr() +// } +// } #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u8)] @@ -60,6 +64,29 @@ pub struct LpadcConfig { pub enable_conv_pause: bool, pub conv_pause_delay: u16, pub fifo_watermark: u8, + pub power: PoweredClock, + pub source: AdcClockSel, + pub div: Div4, +} + +impl Default for LpadcConfig { + fn default() -> Self { + LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::NoAverage, + enable_analog_preliminary: false, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option1, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), + } + } } #[derive(Debug, Clone, Copy, PartialEq, Eq)] @@ -94,15 +121,24 @@ pub struct ConvResult { pub conv_value: u16, } -pub struct Adc { - _inst: core::marker::PhantomData, +pub struct Adc<'a, I: Instance> { + _inst: core::marker::PhantomData<&'a mut I>, } -impl Adc { +impl<'a, I: Instance> Adc<'a, I> { /// initialize ADC - pub fn new(_inst: impl Instance, config: LpadcConfig) -> Self { + pub fn new(_inst: Peri<'a, I>, config: LpadcConfig) -> Self { let adc = unsafe { &*I::ptr() }; + let _clock_freq = unsafe { + enable_and_reset::(&AdcConfig { + power: config.power, + source: config.source, + div: config.div, + }) + .expect("Adc Init should not fail") + }; + /* Reset the module. */ adc.ctrl().modify(|_, w| w.rst().held_in_reset()); adc.ctrl().modify(|_, w| w.rst().released_from_reset()); @@ -194,21 +230,6 @@ impl Adc { adc.ctrl().modify(|_, w| w.adcen().disabled()); } - pub fn get_default_config() -> LpadcConfig { - LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::NoAverage, - enable_analog_preliminary: false, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option1, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - } - } - pub fn do_offset_calibration(&self) { let adc = unsafe { &*I::ptr() }; // Enable calibration mode diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index 24e118e38..e04f63b8e 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -79,6 +79,11 @@ pub unsafe fn assert_reset() { G::assert_reset(); } +#[inline] +pub unsafe fn is_reset_released() -> bool { + G::is_reset_released() +} + /// Pulse a reset line (assert then release) with a short delay. #[inline] pub unsafe fn pulse_reset() { @@ -150,12 +155,15 @@ pub mod gate { use super::periph_helpers::{AdcConfig, LpuartConfig, OsTimerConfig}; use super::*; + // These peripherals have no additional upstream clocks or configuration required + // other than enabling through the MRCC gate. impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, NoConfig); impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, NoConfig); impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, NoConfig); + impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig); + impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, OsTimerConfig); impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig); - impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig); impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, AdcConfig); } @@ -276,7 +284,7 @@ pub struct Clock { pub power: PoweredClock, } -#[derive(Debug, Clone, Copy)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum PoweredClock { NormalEnabledDeepSleepDisabled, AlwaysEnabled, diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index de767ef87..1657bd7eb 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -18,6 +18,11 @@ pub trait SPConfHelper { pub struct Div4(pub(super) u8); impl Div4 { + /// Divide by one, or no division + pub const fn no_div() -> Self { + Self(0) + } + /// Store a "raw" divisor value that will divide the source by /// `(n + 1)`, e.g. `Div4::from_raw(0)` will divide the source /// by 1, and `Div4::from_raw(15)` will divide the source by @@ -81,6 +86,7 @@ pub enum LpuartClockSel { None, } +#[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum LpuartInstance { Lpuart0, Lpuart1, @@ -102,6 +108,7 @@ pub struct LpuartConfig { pub(crate) instance: LpuartInstance, } +#[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum OstimerClockSel { /// 16k clock, sourced from FRO16K (Vdd Core) Clk16kVddCore, @@ -116,6 +123,7 @@ pub struct OsTimerConfig { pub source: OstimerClockSel, } +#[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum AdcClockSel { FroLfDiv, FroHf, diff --git a/src/lib.rs b/src/lib.rs index fd7d3cd07..4120c1e84 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -6,7 +6,6 @@ pub mod clocks; // still provide clock helpers pub mod gpio; pub mod pins; // pin mux helpers -pub mod reset; // reset control helpers pub mod adc; pub mod config; diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index be69372a2..9e8b25ff6 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -545,7 +545,7 @@ impl Default for Config { swap_txd_rxd: false, power: PoweredClock::NormalEnabledDeepSleepDisabled, source: LpuartClockSel::FroLfDiv, - div: const { Div4::from_divisor(1).unwrap() }, + div: Div4::no_div(), } } } diff --git a/src/ostimer.rs b/src/ostimer.rs index 8bc68389a..efa534194 100644 --- a/src/ostimer.rs +++ b/src/ostimer.rs @@ -29,8 +29,13 @@ use core::sync::atomic::{AtomicBool, Ordering}; +use embassy_hal_internal::{Peri, PeripheralType}; + +use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; +use crate::clocks::{assert_reset, enable_and_reset, is_reset_released, release_reset, Gate, PoweredClock}; use crate::interrupt::InterruptExt; use crate::pac; +use crate::peripherals::OSTIMER0; // PAC defines the shared RegisterBlock under `ostimer0`. type Regs = pac::ostimer0::RegisterBlock; @@ -197,16 +202,16 @@ impl<'d> Alarm<'d> { pub struct Config { /// Initialize MATCH registers to their max values and mask/clear the interrupt flag. pub init_match_max: bool, - /// OSTIMER clock frequency in Hz (must match the actual hardware clock) - pub clock_frequency_hz: u64, + pub power: PoweredClock, + pub source: OstimerClockSel, } impl Default for Config { fn default() -> Self { Self { init_match_max: true, - // Default to 1MHz - user should override this with actual frequency - clock_frequency_hz: 1_000_000, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: OstimerClockSel::Clk1M, } } } @@ -222,8 +227,16 @@ impl<'d, I: Instance> Ostimer<'d, I> { /// Construct OSTIMER handle. /// Requires clocks for the instance to be enabled by the board before calling. /// Does not enable NVIC or INTENA; use time_driver::init() for async operation. - pub fn new(_inst: impl Instance, cfg: Config, _p: &'d crate::pac::Peripherals) -> Self { - assert!(cfg.clock_frequency_hz > 0, "OSTIMER frequency must be greater than 0"); + pub fn new(_inst: Peri<'d, I>, cfg: Config) -> Self { + let clock_freq = unsafe { + enable_and_reset::(&OsTimerConfig { + power: cfg.power, + source: cfg.source, + }) + .expect("Enabling OsTimer clock should not fail") + }; + + assert!(clock_freq > 0, "OSTIMER frequency must be greater than 0"); if cfg.init_match_max { let r: &Regs = unsafe { &*I::ptr() }; @@ -233,7 +246,7 @@ impl<'d, I: Instance> Ostimer<'d, I> { Self { _inst: core::marker::PhantomData, - clock_frequency_hz: cfg.clock_frequency_hz, + clock_frequency_hz: clock_freq as u64, _phantom: core::marker::PhantomData, } } @@ -260,7 +273,7 @@ impl<'d, I: Instance> Ostimer<'d, I> { /// # Safety /// This operation will reset the entire OSTIMER peripheral. Any active alarms /// or time_driver operations will be disrupted. Use with caution. - pub fn reset(&self, peripherals: &crate::pac::Peripherals) { + pub fn reset(&self, _peripherals: &crate::pac::Peripherals) { critical_section::with(|_| { let r: &Regs = unsafe { &*I::ptr() }; @@ -270,19 +283,17 @@ impl<'d, I: Instance> Ostimer<'d, I> { .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); unsafe { - crate::reset::assert::(peripherals); - } + assert_reset::(); - for _ in 0..RESET_STABILIZE_SPINS { - cortex_m::asm::nop(); - } + for _ in 0..RESET_STABILIZE_SPINS { + cortex_m::asm::nop(); + } - unsafe { - crate::reset::release::(peripherals); - } + release_reset::(); - while !::is_released(&peripherals.mrcc0) { - cortex_m::asm::nop(); + while !is_reset_released::() { + cortex_m::asm::nop(); + } } for _ in 0..RESET_STABILIZE_SPINS { @@ -469,14 +480,13 @@ fn now_ticks_read() -> u64 { // Read high then low to minimize incoherent snapshots let hi = (r.evtimerh().read().evtimer_count_value().bits() as u64) & (EVTIMER_HI_MASK as u64); let lo = r.evtimerl().read().evtimer_count_value().bits() as u64; - // Combine and convert from Gray code to binary let gray = lo | (hi << EVTIMER_HI_SHIFT); gray_to_bin(gray) } // Instance trait like other drivers, providing a PAC pointer for this OSTIMER instance -pub trait Instance { +pub trait Instance: Gate + PeripheralType { fn ptr() -> *const Regs; } @@ -491,12 +501,12 @@ impl Instance for crate::peripherals::OSTIMER0 { } // Also implement Instance for the Peri wrapper type -impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> { - #[inline(always)] - fn ptr() -> *const Regs { - pac::Ostimer0::ptr() - } -} +// impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> { +// #[inline(always)] +// fn ptr() -> *const Regs { +// pac::Ostimer0::ptr() +// } +// } #[inline(always)] fn bin_to_gray(x: u64) -> u64 { diff --git a/src/reset.rs b/src/reset.rs deleted file mode 100644 index 1c131d1cc..000000000 --- a/src/reset.rs +++ /dev/null @@ -1,112 +0,0 @@ -//! Reset control helpers built on PAC field writers. -use crate::pac; - -/// Trait describing a reset line that can be asserted/deasserted. -pub trait ResetLine { - /// Drive the peripheral out of reset. - unsafe fn release(mrcc: &pac::mrcc0::RegisterBlock); - - /// Drive the peripheral into reset. - unsafe fn assert(mrcc: &pac::mrcc0::RegisterBlock); - - /// Check whether the peripheral is currently released. - fn is_released(mrcc: &pac::mrcc0::RegisterBlock) -> bool; -} - -/// Release a reset line for the given peripheral set. -#[inline] -pub unsafe fn release(peripherals: &pac::Peripherals) { - R::release(&peripherals.mrcc0); -} - -/// Assert a reset line for the given peripheral set. -#[inline] -pub unsafe fn assert(peripherals: &pac::Peripherals) { - R::assert(&peripherals.mrcc0); -} - -/// Pulse a reset line (assert then release) with a short delay. -#[inline] -pub unsafe fn pulse(peripherals: &pac::Peripherals) { - let mrcc = &peripherals.mrcc0; - R::assert(mrcc); - cortex_m::asm::nop(); - cortex_m::asm::nop(); - R::release(mrcc); -} - -macro_rules! impl_reset_line { - ($name:ident, $reg:ident, $field:ident) => { - pub struct $name; - - impl ResetLine for $name { - #[inline] - unsafe fn release(mrcc: &pac::mrcc0::RegisterBlock) { - mrcc.$reg().modify(|_, w| w.$field().enabled()); - } - - #[inline] - unsafe fn assert(mrcc: &pac::mrcc0::RegisterBlock) { - mrcc.$reg().modify(|_, w| w.$field().disabled()); - } - - #[inline] - fn is_released(mrcc: &pac::mrcc0::RegisterBlock) -> bool { - mrcc.$reg().read().$field().is_enabled() - } - } - }; -} - -pub mod line { - use super::*; - - impl_reset_line!(Port2, mrcc_glb_rst1, port2); - impl_reset_line!(Port3, mrcc_glb_rst1, port3); - impl_reset_line!(Gpio3, mrcc_glb_rst2, gpio3); - impl_reset_line!(Lpuart2, mrcc_glb_rst0, lpuart2); - impl_reset_line!(Ostimer0, mrcc_glb_rst1, ostimer0); - impl_reset_line!(Port1, mrcc_glb_rst1, port1); - impl_reset_line!(Adc1, mrcc_glb_rst1, adc1); -} - -#[inline] -pub unsafe fn release_reset_port2(peripherals: &pac::Peripherals) { - release::(peripherals); -} - -#[inline] -pub unsafe fn release_reset_port3(peripherals: &pac::Peripherals) { - release::(peripherals); -} - -#[inline] -pub unsafe fn release_reset_gpio3(peripherals: &pac::Peripherals) { - release::(peripherals); -} - -#[inline] -pub unsafe fn release_reset_lpuart2(peripherals: &pac::Peripherals) { - release::(peripherals); -} - -#[inline] -pub unsafe fn release_reset_ostimer0(peripherals: &pac::Peripherals) { - release::(peripherals); -} - -/// Convenience shim retained for existing call sites. -#[inline] -pub unsafe fn reset_ostimer0(peripherals: &pac::Peripherals) { - pulse::(peripherals); -} - -#[inline] -pub unsafe fn release_reset_port1(peripherals: &pac::Peripherals) { - release::(peripherals); -} - -#[inline] -pub unsafe fn release_reset_adc1(peripherals: &pac::Peripherals) { - release::(peripherals); -} -- cgit From 8cdccae3c6c4a805cf5003b1a859734c105d76e8 Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 14 Nov 2025 18:43:27 +0100 Subject: Continue working on examples --- Cargo.toml | 3 - examples/adc_interrupt.rs | 29 ++-- examples/adc_polling.rs | 30 +++- examples/blink.rs | 4 - examples/hello.rs | 33 +++-- examples/lpuart_buffered.rs | 9 +- examples/lpuart_polling.rs | 11 +- examples/ostimer_alarm.rs | 32 +++-- examples/ostimer_async.rs | 29 ++-- examples/ostimer_counter.rs | 26 +++- examples/ostimer_race_test.rs | 71 ++++++---- examples/rtc_alarm.rs | 28 ++-- examples/uart_interrupt.rs | 69 --------- src/lib.rs | 2 - src/lpuart/mod.rs | 20 +++ src/ostimer.rs | 10 +- src/rtc.rs | 32 +++-- src/uart.rs | 316 ------------------------------------------ 18 files changed, 248 insertions(+), 506 deletions(-) delete mode 100644 examples/uart_interrupt.rs delete mode 100644 src/uart.rs diff --git a/Cargo.toml b/Cargo.toml index 19d1c7174..259becfe8 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -57,9 +57,6 @@ name = "hello" [[example]] name = "blink" -[[example]] -name = "uart_interrupt" - [[example]] name = "ostimer_alarm" diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs index 3be85ac75..536152539 100644 --- a/examples/adc_interrupt.rs +++ b/examples/adc_interrupt.rs @@ -4,13 +4,13 @@ use embassy_executor::Spawner; use embassy_mcxa276::clocks::periph_helpers::{AdcClockSel, Div4}; use embassy_mcxa276::clocks::PoweredClock; +use embassy_mcxa276::lpuart::{Config, Lpuart}; use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; -use hal::uart; use mcxa_pac::adc1::cfg::{Pwrsel, Refsel}; use mcxa_pac::adc1::cmdl1::{Adch, Mode}; use mcxa_pac::adc1::ctrl::CalAvgs; use mcxa_pac::adc1::tctrl::Tcmd; -use {cortex_m, embassy_mcxa276 as hal}; +use {embassy_mcxa276 as hal}; mod common; use hal::{bind_interrupts, InterruptExt}; @@ -28,14 +28,25 @@ static KEEP_ADC: unsafe extern "C" fn() = ADC1; async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { common::init_uart2(hal::pac()); } - - // let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - // let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); - - // uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); unsafe { common::init_adc(hal::pac()); @@ -71,7 +82,7 @@ async fn main(_spawner: Spawner) { conv_trigger_config.enable_hardware_trigger = false; adc.set_conv_trigger_config(0, &conv_trigger_config); - // uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); adc.enable_interrupt(0x1); @@ -88,7 +99,7 @@ async fn main(_spawner: Spawner) { while !adc.is_interrupt_triggered() { // Wait until the interrupt is triggered } - // uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); + uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); //TBD need to print the value } } diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs index 4b5f9422d..2fe4153db 100644 --- a/examples/adc_polling.rs +++ b/examples/adc_polling.rs @@ -2,9 +2,11 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa276::clocks::periph_helpers::{AdcClockSel, Div4}; +use embassy_mcxa276::clocks::PoweredClock; +use embassy_mcxa276::lpuart::{Config, Lpuart}; use embassy_mcxa276 as hal; use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; -use hal::uart; use mcxa_pac::adc1::cfg::{Pwrsel, Refsel}; use mcxa_pac::adc1::cmdl1::{Adch, Mode}; use mcxa_pac::adc1::ctrl::CalAvgs; @@ -27,10 +29,27 @@ async fn main(_spawner: Spawner) { common::init_uart2(hal::pac()); } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + unsafe { + common::init_uart2(hal::pac()); + } + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); - uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n"); + uart.blocking_write(b"\r\n=== ADC polling Example ===\r\n").unwrap(); unsafe { common::init_adc(hal::pac()); @@ -47,6 +66,9 @@ async fn main(_spawner: Spawner) { enable_conv_pause: false, conv_pause_delay: 0, fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), }; let adc = hal::adc::Adc::::new(p.ADC1, adc_config); diff --git a/examples/blink.rs b/examples/blink.rs index 564353d5c..0f489abb9 100644 --- a/examples/blink.rs +++ b/examples/blink.rs @@ -28,10 +28,6 @@ async fn main(_spawner: Spawner) { unsafe { common::init_led(hal::pac()); } - // Initialize OSTIMER for async timing - unsafe { - common::init_ostimer0(hal::pac()); - } // Initialize embassy-time global driver backed by OSTIMER0 hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); diff --git a/examples/hello.rs b/examples/hello.rs index e39adaced..dbb53fdcf 100644 --- a/examples/hello.rs +++ b/examples/hello.rs @@ -2,15 +2,14 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::uart; +use embassy_mcxa276::{self as hal, lpuart::{Blocking, Config, Lpuart}}; mod common; use {defmt_rtt as _, panic_probe as _}; /// Simple helper to write a byte as hex to UART -fn write_hex_byte(uart: &hal::uart::Uart, byte: u8) { +fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) { const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); @@ -22,15 +21,25 @@ async fn main(_spawner: Spawner) { defmt::info!("boot"); - // Board-level init for UART2 clocks and pins. + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { common::init_uart2(hal::pac()); } - - // Get UART source frequency from clock configuration - // Using hardcoded frequency for now - dynamic detection may have issues - let src = 12_000_000; // FRO_LF_DIV at 12MHz with DIV=0 - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); // Print welcome message before any async delays to guarantee early console output uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); @@ -69,12 +78,12 @@ async fn main(_spawner: Spawner) { let num_str = &command[4..]; if let Ok(num) = parse_u8(num_str) { uart.write_str_blocking("Hex: 0x"); - write_hex_byte(&uart, num); + write_hex_byte(&mut uart, num); uart.write_str_blocking("\r\n"); } else { uart.write_str_blocking("Invalid number for hex command\r\n"); } - } else if command.len() > 0 { + } else if !command.is_empty() { uart.write_str_blocking("Unknown command: "); uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); uart.write_str_blocking("\r\n"); @@ -103,7 +112,7 @@ async fn main(_spawner: Spawner) { fn parse_u8(bytes: &[u8]) -> Result { let mut result = 0u8; for &b in bytes { - if b >= b'0' && b <= b'9' { + if b.is_ascii_digit() { result = result.checked_mul(10).ok_or(())?; result = result.checked_add(b - b'0').ok_or(())?; } else { diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs index 6ae690c56..9e297ca67 100644 --- a/examples/lpuart_buffered.rs +++ b/examples/lpuart_buffered.rs @@ -22,7 +22,7 @@ unsafe extern "C" fn lpuart2_handler() { #[embassy_executor::main] async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); + let p = hal::init(hal::config::Config::default()); unsafe { hal::interrupt::install_irq_handler(mcxa_pac::Interrupt::LPUART2, lpuart2_handler); @@ -33,7 +33,6 @@ async fn main(_spawner: Spawner) { unsafe { common::init_uart2(hal::pac()); - common::init_ostimer0(hal::pac()); } // UART configuration (enable both TX and RX) @@ -51,9 +50,9 @@ async fn main(_spawner: Spawner) { // Create a buffered LPUART2 instance with both TX and RX let mut uart = BufferedLpuart::new( - p2.LPUART2, - p2.PIO2_2, // TX pin - p2.PIO2_3, // RX pin + p.LPUART2, + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin Irqs, &mut tx_buf, &mut rx_buf, diff --git a/examples/lpuart_polling.rs b/examples/lpuart_polling.rs index 067c7eb53..c9630dca5 100644 --- a/examples/lpuart_polling.rs +++ b/examples/lpuart_polling.rs @@ -4,14 +4,13 @@ use embassy_executor::Spawner; use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; -use crate::hal::lpuart::{lib, Config, Lpuart}; +use crate::hal::lpuart::{Config, Lpuart}; mod common; #[embassy_executor::main] async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); - let p2 = lib::init(); + let p = hal::init(hal::config::Config::default()); defmt::info!("boot"); @@ -30,9 +29,9 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX let lpuart = Lpuart::new_blocking( - p2.LPUART2, // Peripheral - p2.PIO2_2, // TX pin - p2.PIO2_3, // RX pin + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin config, ) .unwrap(); diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs index 4f29a2c7c..f3a84d312 100644 --- a/examples/ostimer_alarm.rs +++ b/examples/ostimer_alarm.rs @@ -4,12 +4,15 @@ use core::sync::atomic::{AtomicBool, Ordering}; use embassy_executor::Spawner; -use hal::uart; -use {cortex_m, embassy_mcxa276 as hal}; +use embassy_mcxa276 as hal; mod common; -use embassy_mcxa276::{bind_interrupts, clocks::{periph_helpers::OstimerClockSel, PoweredClock}}; +use embassy_mcxa276::{ + bind_interrupts, + clocks::{periph_helpers::OstimerClockSel, PoweredClock}, + lpuart::{Config, Lpuart}, +}; use {defmt_rtt as _, panic_probe as _}; // Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. @@ -33,15 +36,26 @@ fn alarm_callback() { async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); - // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { common::init_uart2(hal::pac()); } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); + uart.write_str_blocking("OSTIMER Alarm Example\n"); // Initialize embassy-time global driver backed by OSTIMER0 diff --git a/examples/ostimer_async.rs b/examples/ostimer_async.rs index 27e14e022..2642a633d 100644 --- a/examples/ostimer_async.rs +++ b/examples/ostimer_async.rs @@ -2,8 +2,7 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa276 as hal; -use hal::uart; +use embassy_mcxa276::{self as hal, lpuart::{Config, Lpuart}}; mod common; @@ -22,18 +21,28 @@ static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; #[embassy_executor::main] async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); + let p = hal::init(hal::config::Config::default()); - // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { common::init_uart2(hal::pac()); } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); - uart.write_str_blocking("boot\n"); + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); + uart.blocking_write(b"boot\n").unwrap(); // Avoid mass NVIC writes here; DefaultHandler now safely returns. diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs index 069e879d8..590c5a14b 100644 --- a/examples/ostimer_counter.rs +++ b/examples/ostimer_counter.rs @@ -7,7 +7,10 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa276::clocks::{periph_helpers::OstimerClockSel, PoweredClock}; +use embassy_mcxa276::{ + clocks::{periph_helpers::OstimerClockSel, PoweredClock}, + lpuart::{Blocking, Config, Lpuart}, +}; use embassy_time::{Duration, Timer}; use hal::bind_interrupts; use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; @@ -22,12 +25,25 @@ bind_interrupts!(struct Irqs { async fn main(_spawner: Spawner) { let p = hal::init(Default::default()); - // Enable/clock OSTIMER0 and UART2 before touching their registers + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { common::init_uart2(hal::pac()); } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); @@ -90,7 +106,7 @@ async fn main(_spawner: Spawner) { } // Helper function to write a u64 value as decimal string -fn write_u64(uart: &mut hal::uart::Uart, value: u64) { +fn write_u64(uart: &mut Lpuart<'_, Blocking>, value: u64) { if value == 0 { uart.write_str_blocking("0"); return; diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs index 6e3d4ac21..131d10f64 100644 --- a/examples/ostimer_race_test.rs +++ b/examples/ostimer_race_test.rs @@ -12,7 +12,10 @@ use core::sync::atomic::{AtomicU32, Ordering}; use embassy_executor::Spawner; -use embassy_mcxa276::clocks::{periph_helpers::OstimerClockSel, PoweredClock}; +use embassy_mcxa276::{ + clocks::{periph_helpers::OstimerClockSel, PoweredClock}, + lpuart::{Blocking, Config, Lpuart}, +}; use embassy_time::{Duration, Timer}; use hal::bind_interrupts; use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _}; @@ -43,7 +46,7 @@ fn alarm_callback() { } } -fn report_default_handler(uart: &mut hal::uart::Uart) { +fn report_default_handler(uart: &mut Lpuart<'_, Blocking>) { let snapshot = hal::interrupt::default_handler_snapshot(); if snapshot.count == 0 { return; @@ -72,15 +75,25 @@ fn report_default_handler(uart: &mut hal::uart::Uart) { async fn main(_spawner: Spawner) { let p = hal::init(Default::default()); - // Enable/clock OSTIMER0 and UART2 before touching their registers - unsafe { - common::init_ostimer0(hal::pac()); - } + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { common::init_uart2(hal::pac()); } - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let mut uart = hal::uart::Uart::::new(p.LPUART2, hal::uart::Config::new(src)); + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); @@ -140,7 +153,7 @@ async fn main(_spawner: Spawner) { // Test rapid alarm scheduling to stress interrupt handling async fn test_rapid_alarms( ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, + uart: &mut Lpuart<'_, Blocking>, ) { let initial_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); @@ -177,7 +190,7 @@ async fn test_rapid_alarms( // Test reading counter while interrupts are firing async fn test_counter_reading_during_interrupts( ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, + uart: &mut Lpuart<'_, Blocking>, ) { let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); @@ -238,7 +251,7 @@ async fn test_counter_reading_during_interrupts( // Test concurrent timer operations (embassy-time + alarms) async fn test_concurrent_operations( ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, + uart: &mut Lpuart<'_, Blocking>, ) { let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); @@ -267,7 +280,7 @@ async fn test_concurrent_operations( // Test timer reset during active operations async fn test_reset_during_operation( ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut hal::uart::Uart, + uart: &mut Lpuart<'_, Blocking>, peripherals: &mcxa_pac::Peripherals, ) { let initial_counter = ostimer.now(); @@ -308,7 +321,7 @@ async fn test_reset_during_operation( } // Helper function to write a u32 value as decimal string -fn write_u32(uart: &mut hal::uart::Uart, value: u32) { +fn write_u32(uart: &mut Lpuart<'_, Blocking>, value: u32) { if value == 0 { uart.write_str_blocking("0"); return; @@ -343,7 +356,7 @@ fn write_u32(uart: &mut hal::uart::Uart, value: u32) { } } -fn write_hex32(uart: &mut hal::uart::Uart, value: u32) { +fn write_hex32(uart: &mut Lpuart<'_, Blocking>, value: u32) { let mut buf = [b'0'; 8]; let mut tmp = value; for i in (0..8).rev() { @@ -355,15 +368,13 @@ fn write_hex32(uart: &mut hal::uart::Uart, value: u32) { }; tmp >>= 4; } - for b in &buf { - uart.write_byte(*b); - } + uart.blocking_write(&buf).unwrap(); } // Helper function to write a u64 value as decimal string -fn write_u64(uart: &mut hal::uart::Uart, value: u64) { +fn write_u64(uart: &mut Lpuart<'_, Blocking>, value: u64) { if value == 0 { - uart.write_str_blocking("0"); + uart.blocking_write(b"0").unwrap(); return; } @@ -381,17 +392,17 @@ fn write_u64(uart: &mut hal::uart::Uart, value: u64) { while i > 0 { i -= 1; match buffer[i] { - b'0' => uart.write_str_blocking("0"), - b'1' => uart.write_str_blocking("1"), - b'2' => uart.write_str_blocking("2"), - b'3' => uart.write_str_blocking("3"), - b'4' => uart.write_str_blocking("4"), - b'5' => uart.write_str_blocking("5"), - b'6' => uart.write_str_blocking("6"), - b'7' => uart.write_str_blocking("7"), - b'8' => uart.write_str_blocking("8"), - b'9' => uart.write_str_blocking("9"), - _ => uart.write_str_blocking("?"), + b'0' => uart.blocking_write(b"0").unwrap(), + b'1' => uart.blocking_write(b"1").unwrap(), + b'2' => uart.blocking_write(b"2").unwrap(), + b'3' => uart.blocking_write(b"3").unwrap(), + b'4' => uart.blocking_write(b"4").unwrap(), + b'5' => uart.blocking_write(b"5").unwrap(), + b'6' => uart.blocking_write(b"6").unwrap(), + b'7' => uart.blocking_write(b"7").unwrap(), + b'8' => uart.blocking_write(b"8").unwrap(), + b'9' => uart.blocking_write(b"9").unwrap(), + _ => uart.blocking_write(b"?").unwrap(), } } } diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs index c27fd4c55..1cda37054 100644 --- a/examples/rtc_alarm.rs +++ b/examples/rtc_alarm.rs @@ -2,13 +2,14 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa276::lpuart::{Config, Lpuart}; use hal::rtc::{RtcDateTime, RtcInterruptEnable}; -use hal::{uart, InterruptExt}; -use {cortex_m, embassy_mcxa276 as hal}; +use hal::InterruptExt; +use {embassy_mcxa276 as hal}; mod common; -type MyRtc = hal::rtc::Rtc; +type MyRtc = hal::rtc::Rtc<'static, hal::rtc::Rtc0>; use embassy_mcxa276::bind_interrupts; use {defmt_rtt as _, panic_probe as _}; @@ -25,17 +26,28 @@ static KEEP_RTC: unsafe extern "C" fn() = RTC; async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + enable_tx: true, + enable_rx: true, + ..Default::default() + }; + + // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { common::init_uart2(hal::pac()); } - - let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; - let uart = uart::Uart::::new(p.LPUART2, uart::Config::new(src)); + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.PIO2_2, // TX pin + p.PIO2_3, // RX pin + config, + ) + .unwrap(); uart.write_str_blocking("\r\n=== RTC Alarm Example ===\r\n"); - unsafe { hal::clocks::init_fro16k(hal::pac()) }; - let rtc_config = hal::rtc::get_default_config(); let rtc = MyRtc::new(p.RTC0, rtc_config); diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs deleted file mode 100644 index 190a4d850..000000000 --- a/examples/uart_interrupt.rs +++ /dev/null @@ -1,69 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -// use embassy_mcxa276 as hal; -// use hal::interrupt::typelevel::Handler; -// use hal::uart; - -// mod common; - -// use embassy_mcxa276::bind_interrupts; -// use {defmt_rtt as _, panic_probe as _}; - -// // Bind LPUART2 interrupt to our handler -// bind_interrupts!(struct Irqs { -// LPUART2 => hal::uart::UartInterruptHandler; -// }); - -// #[used] -// #[no_mangle] -// static KEEP_LPUART2: unsafe extern "C" fn() = LPUART2; - -// // Wrapper function for the interrupt handler -// unsafe extern "C" fn lpuart2_handler() { -// hal::uart::UartInterruptHandler::on_interrupt(); -// } - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { -// let _p = hal::init(hal::config::Config::default()); - -// // Enable/clock UART2 before touching its registers -// unsafe { -// common::init_uart2(hal::pac()); -// } -// let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; -// let uart = uart::Uart::::new(_p.LPUART2, uart::Config::new(src)); - -// // Configure LPUART2 interrupt for UART operation BEFORE any UART usage -// hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3)); - -// // Manually install the interrupt handler and enable RX IRQs in the peripheral -// unsafe { -// hal::interrupt::LPUART2.install_handler(lpuart2_handler); -// // Enable RX interrupts so the handler actually fires on incoming bytes -// uart.enable_rx_interrupts(); -// } - -// // Print welcome message -// uart.write_str_blocking("UART interrupt echo demo starting...\r\n"); -// uart.write_str_blocking("Type characters to echo them back.\r\n"); - -// // Log using defmt if enabled -// defmt::info!("UART interrupt echo demo starting..."); - -// loop { -// // Check if we have received any data -// if uart.rx_data_available() { -// if let Some(byte) = uart.try_read_byte() { -// // Echo it back -// uart.write_byte(byte); -// uart.write_str_blocking(" (received)\r\n"); -// } -// } else { -// // No data available, wait a bit before checking again -// cortex_m::asm::delay(12_000_000); // ~1 second at 12MHz -// } -// } -} diff --git a/src/lib.rs b/src/lib.rs index 4120c1e84..ec2cb31e7 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -13,7 +13,6 @@ pub mod interrupt; pub mod lpuart; pub mod ostimer; pub mod rtc; -pub mod uart; embassy_hal_internal::peripherals!(PORT1, PORT2, PORT3, LPUART2, OSTIMER0, GPIO, PIO2_2, PIO2_3, GPIO3, RTC0, ADC1,); @@ -45,7 +44,6 @@ pub use mcxa_pac as pac; pub(crate) use mcxa_pac as pac; pub use ostimer::Ostimer0 as Ostimer0Token; pub use rtc::Rtc0 as Rtc0Token; -pub use uart::Lpuart2 as Uart2Token; /// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. /// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 9e8b25ff6..b3d7c4885 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -772,6 +772,10 @@ impl<'a> LpuartTx<'a, Blocking> { Ok(()) } + pub fn write_str_blocking(&mut self, buf: &str) { + let _ = self.blocking_write(buf.as_bytes()); + } + /// Write data to LPUART TX without blocking. pub fn write(&mut self, buf: &[u8]) -> Result<()> { for x in buf { @@ -901,6 +905,22 @@ impl<'a> Lpuart<'a, Blocking> { self.tx.blocking_write(buf) } + pub fn write_byte(&mut self, byte: u8) { + _ = self.tx.write_byte(byte); + } + + pub fn read_byte_blocking(&mut self) -> u8 { + loop { + if let Ok(b) = self.rx.read_byte() { + return b; + } + } + } + + pub fn write_str_blocking(&mut self, buf: &str) { + self.tx.write_str_blocking(buf); + } + /// Write data to LPUART TX without blocking pub fn write(&mut self, buf: &[u8]) -> Result<()> { self.tx.write(buf) diff --git a/src/ostimer.rs b/src/ostimer.rs index efa534194..ebdf7d45d 100644 --- a/src/ostimer.rs +++ b/src/ostimer.rs @@ -534,7 +534,7 @@ pub mod time_driver { bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, }; - use crate::pac; + use crate::{clocks::{enable_and_reset, periph_helpers::{OsTimerConfig, OstimerClockSel}, PoweredClock}, pac, peripherals::OSTIMER0}; pub struct Driver; static TIMER_WAKER: AtomicWaker = AtomicWaker::new(); @@ -621,6 +621,14 @@ pub mod time_driver { /// Note: The frequency parameter is currently accepted for API compatibility. /// The embassy_time_driver macro handles driver registration automatically. pub fn init(priority: crate::interrupt::Priority, frequency_hz: u64) { + let _clock_freq = unsafe { + enable_and_reset::(&OsTimerConfig { + power: PoweredClock::AlwaysEnabled, + source: OstimerClockSel::Clk1M, + }) + .expect("Enabling OsTimer clock should not fail") + }; + // Mask/clear at peripheral and set default MATCH let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; super::prime_match_registers(r); diff --git a/src/rtc.rs b/src/rtc.rs index facb9cf8c..f526e82ac 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -1,6 +1,9 @@ //! RTC DateTime driver. use core::sync::atomic::{AtomicBool, Ordering}; +use embassy_hal_internal::{Peri, PeripheralType}; + +use crate::clocks::with_clocks; use crate::pac; use crate::pac::rtc0::cr::Um; @@ -9,7 +12,7 @@ type Regs = pac::rtc0::RegisterBlock; static ALARM_TRIGGERED: AtomicBool = AtomicBool::new(false); // Token-based instance pattern like embassy-imxrt -pub trait Instance { +pub trait Instance: PeripheralType { fn ptr() -> *const Regs; } @@ -22,14 +25,6 @@ impl Instance for crate::peripherals::RTC0 { } } -// Also implement Instance for the Peri wrapper type -impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::RTC0> { - #[inline(always)] - fn ptr() -> *const Regs { - pac::Rtc0::ptr() - } -} - const DAYS_IN_A_YEAR: u32 = 365; const SECONDS_IN_A_DAY: u32 = 86400; const SECONDS_IN_A_HOUR: u32 = 3600; @@ -157,15 +152,26 @@ pub fn get_default_config() -> RtcConfig { } } /// Minimal RTC handle for a specific instance I (store the zero-sized token like embassy) -pub struct Rtc { - _inst: core::marker::PhantomData, +pub struct Rtc<'a, I: Instance> { + _inst: core::marker::PhantomData<&'a mut I>, } -impl Rtc { +impl<'a, I: Instance> Rtc<'a, I> { /// initialize RTC - pub fn new(_inst: impl Instance, config: RtcConfig) -> Self { + pub fn new(_inst: Peri<'a, I>, config: RtcConfig) -> Self { let rtc = unsafe { &*I::ptr() }; + // The RTC is NOT gated by the MRCC, but we DO need to make sure the 16k clock + // on the vsys domain is active + let clocks = with_clocks(|c| { + c.clk_16k_vsys.clone() + }); + match clocks { + None => panic!("Clocks have not been initialized"), + Some(None) => panic!("Clocks initialized, but clk_16k_vsys not active"), + Some(Some(_)) => {} + } + /* RTC reset */ rtc.cr().modify(|_, w| w.swr().set_bit()); rtc.cr().modify(|_, w| w.swr().clear_bit()); diff --git a/src/uart.rs b/src/uart.rs deleted file mode 100644 index 3705959d3..000000000 --- a/src/uart.rs +++ /dev/null @@ -1,316 +0,0 @@ -//! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering. -//! WARNING: This is a narrow implementation only for debug console (115200 8N1). - -// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs -// are complete prior to release. -#![allow(clippy::missing_safety_doc)] - -use core::cell::RefCell; - -use cortex_m::interrupt::Mutex; -use embassy_sync::signal::Signal; - -use crate::pac; - -// svd2rust defines the shared LPUART RegisterBlock under lpuart0; all instances reuse it. -type Regs = pac::lpuart0::RegisterBlock; - -// Token-based instance pattern like embassy-imxrt -pub trait Instance { - fn ptr() -> *const Regs; -} - -/// Token for LPUART2 provided by embassy-hal-internal peripherals macro. -pub type Lpuart2 = crate::peripherals::LPUART2; -impl Instance for crate::peripherals::LPUART2 { - #[inline(always)] - fn ptr() -> *const Regs { - pac::Lpuart2::ptr() - } -} - -// Also implement Instance for the Peri wrapper type -impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::LPUART2> { - #[inline(always)] - fn ptr() -> *const Regs { - pac::Lpuart2::ptr() - } -} - -/// UART configuration (explicit src_hz; no hardcoded frequencies) -#[derive(Copy, Clone)] -pub struct Config { - pub src_hz: u32, - pub baud: u32, - pub parity: Parity, - pub stop_bits: StopBits, -} - -#[derive(Copy, Clone)] -pub enum Parity { - None, - Even, - Odd, -} -#[derive(Copy, Clone)] -pub enum StopBits { - One, - Two, -} - -impl Config { - pub fn new(src_hz: u32) -> Self { - Self { - src_hz, - baud: 115_200, - parity: Parity::None, - stop_bits: StopBits::One, - } - } -} - -/// Compute a valid (OSR, SBR) tuple for given source clock and baud. -/// Uses a functional fold approach to find the best OSR/SBR combination -/// with minimal baud rate error. -fn compute_osr_sbr(src_hz: u32, baud: u32) -> (u8, u16) { - let (best_osr, best_sbr, _best_err) = (8u32..=32).fold( - (16u8, 4u16, u32::MAX), // (best_osr, best_sbr, best_err) - |(best_osr, best_sbr, best_err), osr| { - let denom = baud.saturating_mul(osr); - if denom == 0 { - return (best_osr, best_sbr, best_err); - } - - let sbr = (src_hz + denom / 2) / denom; // round - if sbr == 0 || sbr > 0x1FFF { - return (best_osr, best_sbr, best_err); - } - - let actual = src_hz / (osr * sbr); - let err = actual.abs_diff(baud); - - // Update best if this is better, or same error but higher OSR - if err < best_err || (err == best_err && osr as u8 > best_osr) { - (osr as u8, sbr as u16, err) - } else { - (best_osr, best_sbr, best_err) - } - }, - ); - (best_osr, best_sbr) -} - -/// Minimal UART handle for a specific instance I (store the zero-sized token like embassy) -pub struct Uart { - _inst: core::marker::PhantomData, -} - -impl Uart { - /// Create and initialize LPUART (reset + config). Clocks and pins must be prepared by the caller. - pub fn new(_inst: impl Instance, cfg: Config) -> Self { - let l = unsafe { &*I::ptr() }; - // 1) software reset pulse - l.global().write(|w| w.rst().reset()); - cortex_m::asm::delay(3); // Short delay for reset to take effect - l.global().write(|w| w.rst().no_effect()); - cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset - // 2) BAUD - let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud); - l.baud().modify(|_, w| { - let w = match cfg.stop_bits { - StopBits::One => w.sbns().one(), - StopBits::Two => w.sbns().two(), - }; - // OSR field encodes (osr-1); use raw bits to avoid a long match on all variants - let raw_osr = osr.saturating_sub(1); - unsafe { w.osr().bits(raw_osr).sbr().bits(sbr) } - }); - // 3) CTRL baseline and parity - l.ctrl().write(|w| { - let w = w.ilt().from_stop().idlecfg().idle_2(); - let w = match cfg.parity { - Parity::None => w.pe().disabled(), - Parity::Even => w.pe().enabled().pt().even(), - Parity::Odd => w.pe().enabled().pt().odd(), - }; - w.re().enabled().te().enabled().rie().disabled() - }); - // 4) FIFOs and WATER: keep it simple for polling; disable FIFOs and set RX watermark to 0 - l.fifo().modify(|_, w| { - w.txfe() - .disabled() - .rxfe() - .disabled() - .txflush() - .txfifo_rst() - .rxflush() - .rxfifo_rst() - }); - l.water() - .modify(|_, w| unsafe { w.txwater().bits(0).rxwater().bits(0) }); - Self { - _inst: core::marker::PhantomData, - } - } - - /// Enable RX interrupts. The caller must ensure an appropriate IRQ handler is installed. - pub unsafe fn enable_rx_interrupts(&self) { - let l = &*I::ptr(); - l.ctrl().modify(|_, w| w.rie().enabled()); - } - - #[inline(never)] - pub fn write_byte(&self, b: u8) { - let l = unsafe { &*I::ptr() }; - // Timeout after ~10ms at 12MHz (assuming 115200 baud, should be plenty) - const DATA_OFFSET: usize = 0x1C; // DATA register offset inside LPUART block - let data_ptr = unsafe { (I::ptr() as *mut u8).add(DATA_OFFSET) }; - for _ in 0..120000 { - if l.water().read().txcount().bits() == 0 { - unsafe { core::ptr::write_volatile(data_ptr, b) }; - return; - } - } - // If timeout, skip the write to avoid hanging - } - - #[inline(never)] - pub fn write_str_blocking(&self, s: &str) { - for &b in s.as_bytes() { - if b == b'\n' { - self.write_byte(b'\r'); - } - self.write_byte(b); - } - } - pub fn read_byte_blocking(&self) -> u8 { - let l = unsafe { &*I::ptr() }; - while !l.stat().read().rdrf().is_rxdata() {} - (l.data().read().bits() & 0xFF) as u8 - } -} - -// Simple ring buffer for UART RX data -const RX_BUFFER_SIZE: usize = 256; -pub struct RingBuffer { - buffer: [u8; RX_BUFFER_SIZE], - read_idx: usize, - write_idx: usize, - count: usize, -} - -impl Default for RingBuffer { - fn default() -> Self { - Self::new() - } -} - -impl RingBuffer { - pub const fn new() -> Self { - Self { - buffer: [0; RX_BUFFER_SIZE], - read_idx: 0, - write_idx: 0, - count: 0, - } - } - - pub fn push(&mut self, data: u8) -> bool { - if self.count >= RX_BUFFER_SIZE { - return false; // Buffer full - } - self.buffer[self.write_idx] = data; - self.write_idx = (self.write_idx + 1) % RX_BUFFER_SIZE; - self.count += 1; - true - } - - pub fn pop(&mut self) -> Option { - if self.count == 0 { - return None; - } - let data = self.buffer[self.read_idx]; - self.read_idx = (self.read_idx + 1) % RX_BUFFER_SIZE; - self.count -= 1; - Some(data) - } - - pub fn is_empty(&self) -> bool { - self.count == 0 - } - - pub fn len(&self) -> usize { - self.count - } -} - -// Global RX buffer shared between interrupt handler and UART instance -static RX_BUFFER: Mutex> = Mutex::new(RefCell::new(RingBuffer::new())); -static RX_SIGNAL: Signal = Signal::new(); - -// Debug counter for interrupt handler calls -static mut INTERRUPT_COUNT: u32 = 0; - -impl Uart { - /// Read a byte asynchronously using interrupts - pub async fn read_byte_async(&self) -> u8 { - loop { - // Check if we have data in the buffer - let byte = cortex_m::interrupt::free(|cs| { - let mut buffer = RX_BUFFER.borrow(cs).borrow_mut(); - buffer.pop() - }); - - if let Some(byte) = byte { - return byte; - } - - // Wait for the interrupt signal - RX_SIGNAL.wait().await; - } - } - - /// Check if there's data available in the RX buffer - pub fn rx_data_available(&self) -> bool { - cortex_m::interrupt::free(|cs| { - let buffer = RX_BUFFER.borrow(cs).borrow(); - !buffer.is_empty() - }) - } - - /// Try to read a byte from RX buffer (non-blocking) - pub fn try_read_byte(&self) -> Option { - cortex_m::interrupt::free(|cs| { - let mut buffer = RX_BUFFER.borrow(cs).borrow_mut(); - buffer.pop() - }) - } -} - -/// Type-level handler for LPUART2 interrupts, compatible with bind_interrupts!. -pub struct UartInterruptHandler; - -impl crate::interrupt::typelevel::Handler for UartInterruptHandler { - unsafe fn on_interrupt() { - INTERRUPT_COUNT += 1; - - let lpuart = &*pac::Lpuart2::ptr(); - - // Check if we have RX data - if lpuart.stat().read().rdrf().is_rxdata() { - // Read the data byte - let data = (lpuart.data().read().bits() & 0xFF) as u8; - - // Store in ring buffer - cortex_m::interrupt::free(|cs| { - let mut buffer = RX_BUFFER.borrow(cs).borrow_mut(); - if buffer.push(data) { - // Data added successfully, signal waiting tasks - RX_SIGNAL.signal(()); - } - }); - } - // Always clear any error flags that might cause spurious interrupts - let _ = lpuart.stat().read(); - } -} -- cgit From 1f589e9428542cd94bc630b623accf04d9c36edf Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 14 Nov 2025 19:08:16 +0100 Subject: A little follow-up cleanup --- examples/src/bin/adc_interrupt.rs | 5 +++-- examples/src/bin/adc_polling.rs | 8 ++++---- examples/src/bin/blink.rs | 4 ++-- examples/src/bin/hello.rs | 2 +- examples/src/bin/lpuart_buffered.rs | 7 ++++--- examples/src/bin/lpuart_polling.rs | 4 ++-- examples/src/bin/ostimer_alarm.rs | 4 ++-- examples/src/bin/ostimer_async.rs | 9 +++++---- examples/src/bin/ostimer_counter.rs | 2 +- examples/src/bin/ostimer_race_test.rs | 2 +- examples/src/bin/rtc_alarm.rs | 9 +++++---- examples/src/lib.rs | 10 ++++------ 12 files changed, 34 insertions(+), 32 deletions(-) diff --git a/examples/src/bin/adc_interrupt.rs b/examples/src/bin/adc_interrupt.rs index be08ebf8c..6812ba5d3 100644 --- a/examples/src/bin/adc_interrupt.rs +++ b/examples/src/bin/adc_interrupt.rs @@ -2,6 +2,7 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa_examples::init_adc_pins; use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::clocks::PoweredClock; @@ -35,7 +36,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral @@ -47,7 +48,7 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); unsafe { - embassy_mcxa_examples::init_adc(hal::pac()); + init_adc_pins(hal::pac()); } let adc_config = LpadcConfig { diff --git a/examples/src/bin/adc_polling.rs b/examples/src/bin/adc_polling.rs index 723f1e044..421306e9b 100644 --- a/examples/src/bin/adc_polling.rs +++ b/examples/src/bin/adc_polling.rs @@ -4,7 +4,7 @@ use core::fmt::Write; use embassy_executor::Spawner; -use embassy_mcxa_examples::{init_adc, init_uart2}; +use embassy_mcxa_examples::{init_adc_pins, init_uart2_pins}; use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::clocks::PoweredClock; @@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); unsafe { - init_uart2(hal::pac()); + init_uart2_pins(hal::pac()); } // Create UART configuration @@ -36,7 +36,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - init_uart2(hal::pac()); + init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral @@ -49,7 +49,7 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n"); unsafe { - init_adc(hal::pac()); + init_adc_pins(hal::pac()); } let adc_config = LpadcConfig { diff --git a/examples/src/bin/blink.rs b/examples/src/bin/blink.rs index ee59ac591..8c48e79f1 100644 --- a/examples/src/bin/blink.rs +++ b/examples/src/bin/blink.rs @@ -4,7 +4,7 @@ use embassy_executor::Spawner; use embassy_mcxa as hal; use embassy_mcxa::bind_interrupts; -use embassy_mcxa_examples::init_led; +use embassy_mcxa_examples::init_led_gpio_clocks; use embassy_time::{Duration, Timer}; use hal::gpio::pins::PIO3_18; use hal::gpio::{Level, Output}; @@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) { let _p = hal::init(hal::config::Config::default()); unsafe { - init_led(hal::pac()); + init_led_gpio_clocks(hal::pac()); } // Initialize embassy-time global driver backed by OSTIMER0 diff --git a/examples/src/bin/hello.rs b/examples/src/bin/hello.rs index ff7afa01d..207c157c3 100644 --- a/examples/src/bin/hello.rs +++ b/examples/src/bin/hello.rs @@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral diff --git a/examples/src/bin/lpuart_buffered.rs b/examples/src/bin/lpuart_buffered.rs index e96ab7b81..642d4af65 100644 --- a/examples/src/bin/lpuart_buffered.rs +++ b/examples/src/bin/lpuart_buffered.rs @@ -5,8 +5,9 @@ use embassy_executor::Spawner; use embassy_mcxa as hal; use embassy_mcxa::interrupt::typelevel::Handler; use embassy_mcxa::lpuart::buffered::BufferedLpuart; +use embassy_mcxa::lpuart::Config; use embassy_mcxa::{bind_interrupts, lpuart}; -use embassy_mcxa_examples::init_uart2; +use embassy_mcxa_examples::init_uart2_pins; use embedded_io_async::{Read, Write}; // Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver @@ -31,11 +32,11 @@ async fn main(_spawner: Spawner) { hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); unsafe { - init_uart2(hal::pac()); + init_uart2_pins(hal::pac()); } // UART configuration (enable both TX and RX) - let config = lpuart::Config { + let config = Config { baudrate_bps: 115_200, enable_tx: true, enable_rx: true, diff --git a/examples/src/bin/lpuart_polling.rs b/examples/src/bin/lpuart_polling.rs index bdcfa0776..bea82c33e 100644 --- a/examples/src/bin/lpuart_polling.rs +++ b/examples/src/bin/lpuart_polling.rs @@ -2,7 +2,7 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa_examples::init_uart2; +use embassy_mcxa_examples::init_uart2_pins; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; use crate::hal::lpuart::{Config, Lpuart}; @@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) { // Board-level init for UART2 clocks and pins. unsafe { - init_uart2(hal::pac()); + init_uart2_pins(hal::pac()); } // Create UART configuration diff --git a/examples/src/bin/ostimer_alarm.rs b/examples/src/bin/ostimer_alarm.rs index 9e858b60b..36b1f403a 100644 --- a/examples/src/bin/ostimer_alarm.rs +++ b/examples/src/bin/ostimer_alarm.rs @@ -8,7 +8,7 @@ use embassy_mcxa::bind_interrupts; use embassy_mcxa::clocks::periph_helpers::OstimerClockSel; use embassy_mcxa::clocks::PoweredClock; use embassy_mcxa::lpuart::{Config, Lpuart}; -use embassy_mcxa_examples::init_uart2; +use embassy_mcxa_examples::init_uart2_pins; use {cortex_m, defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. @@ -42,7 +42,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - init_uart2(hal::pac()); + init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral diff --git a/examples/src/bin/ostimer_async.rs b/examples/src/bin/ostimer_async.rs index 4e692a744..881f09374 100644 --- a/examples/src/bin/ostimer_async.rs +++ b/examples/src/bin/ostimer_async.rs @@ -3,8 +3,9 @@ use embassy_executor::Spawner; use embassy_mcxa::bind_interrupts; -use embassy_mcxa_examples::init_uart2; +use embassy_mcxa_examples::init_uart2_pins; use embassy_time::{Duration, Timer}; +use hal::lpuart::{Config, Lpuart}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed. @@ -21,7 +22,7 @@ async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); // Create UART configuration - let config = hal::lpuart::Config { + let config = Config { baudrate_bps: 115_200, enable_tx: true, enable_rx: true, @@ -30,9 +31,9 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - init_uart2(hal::pac()); + init_uart2_pins(hal::pac()); } - let mut uart = hal::lpuart::Lpuart::new_blocking( + let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral p.PIO2_2, // TX pin p.PIO2_3, // RX pin diff --git a/examples/src/bin/ostimer_counter.rs b/examples/src/bin/ostimer_counter.rs index 47543160b..2fbc251b9 100644 --- a/examples/src/bin/ostimer_counter.rs +++ b/examples/src/bin/ostimer_counter.rs @@ -32,7 +32,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral diff --git a/examples/src/bin/ostimer_race_test.rs b/examples/src/bin/ostimer_race_test.rs index c2ecff969..168a952cd 100644 --- a/examples/src/bin/ostimer_race_test.rs +++ b/examples/src/bin/ostimer_race_test.rs @@ -82,7 +82,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral diff --git a/examples/src/bin/rtc_alarm.rs b/examples/src/bin/rtc_alarm.rs index e2eaa6ae2..40a1207df 100644 --- a/examples/src/bin/rtc_alarm.rs +++ b/examples/src/bin/rtc_alarm.rs @@ -2,9 +2,10 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa as hal; +use hal::lpuart::{Config, Lpuart}; use hal::rtc::{RtcDateTime, RtcInterruptEnable}; use hal::InterruptExt; -use {cortex_m, embassy_mcxa as hal}; type MyRtc = hal::rtc::Rtc<'static, hal::rtc::Rtc0>; @@ -24,7 +25,7 @@ async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); // Create UART configuration - let config = hal::lpuart::Config { + let config = Config { baudrate_bps: 115_200, enable_tx: true, enable_rx: true, @@ -33,9 +34,9 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(hal::pac()); } - let mut uart = hal::lpuart::Lpuart::new_blocking( + let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral p.PIO2_2, // TX pin p.PIO2_3, // RX pin diff --git a/examples/src/lib.rs b/examples/src/lib.rs index a45ab708d..be4761c32 100644 --- a/examples/src/lib.rs +++ b/examples/src/lib.rs @@ -1,4 +1,5 @@ #![no_std] +#![allow(clippy::missing_safety_doc)] //! Shared board-specific helpers for the FRDM-MCXA276 examples. //! These live with the examples so the HAL stays generic. @@ -8,8 +9,7 @@ use {embassy_mcxa as hal, panic_probe as _}; /// Initialize clocks and pin muxing for UART2 debug console. /// Safe to call multiple times; writes are idempotent for our use. -#[allow(dead_code)] -pub unsafe fn init_uart2(_p: &hal::pac::Peripherals) { +pub unsafe fn init_uart2_pins(_p: &hal::pac::Peripherals) { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. // GPIO has not. _ = clocks::enable_and_reset::(&clocks::NoConfig); @@ -17,15 +17,13 @@ pub unsafe fn init_uart2(_p: &hal::pac::Peripherals) { } /// Initialize clocks for the LED GPIO/PORT used by the blink example. -#[allow(dead_code)] -pub unsafe fn init_led(_p: &hal::pac::Peripherals) { +pub unsafe fn init_led_gpio_clocks(_p: &hal::pac::Peripherals) { _ = clocks::enable_and_reset::(&clocks::NoConfig); _ = clocks::enable_and_reset::(&clocks::NoConfig); } /// Initialize clocks and pin muxing for ADC. -#[allow(dead_code)] -pub unsafe fn init_adc(_p: &hal::pac::Peripherals) { +pub unsafe fn init_adc_pins(_p: &hal::pac::Peripherals) { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. // GPIO has not. _ = clocks::enable_and_reset::(&clocks::NoConfig); -- cgit From 728340ba05e9a16ceb472b147737c38c144d292d Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 14 Nov 2025 19:11:06 +0100 Subject: Remove redundant import --- examples/src/bin/ostimer_alarm.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/src/bin/ostimer_alarm.rs b/examples/src/bin/ostimer_alarm.rs index 36b1f403a..03fb93319 100644 --- a/examples/src/bin/ostimer_alarm.rs +++ b/examples/src/bin/ostimer_alarm.rs @@ -9,7 +9,7 @@ use embassy_mcxa::clocks::periph_helpers::OstimerClockSel; use embassy_mcxa::clocks::PoweredClock; use embassy_mcxa::lpuart::{Config, Lpuart}; use embassy_mcxa_examples::init_uart2_pins; -use {cortex_m, defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. bind_interrupts!(struct Irqs { -- cgit From 6e6ba60beb4faf17142938e1efff4b9d30e715c3 Mon Sep 17 00:00:00 2001 From: James Munns Date: Mon, 17 Nov 2025 14:43:06 +0100 Subject: Docs pass and organization cleanup --- src/clocks/config.rs | 199 +++++++++ src/clocks/mod.rs | 983 ++++++++++++++++++++++--------------------- src/clocks/periph_helpers.rs | 160 +++++-- src/config.rs | 3 + 4 files changed, 822 insertions(+), 523 deletions(-) create mode 100644 src/clocks/config.rs diff --git a/src/clocks/config.rs b/src/clocks/config.rs new file mode 100644 index 000000000..a517afcca --- /dev/null +++ b/src/clocks/config.rs @@ -0,0 +1,199 @@ +//! Clock Configuration +//! +//! This module holds configuration types used for the system clocks. For +//! configuration of individual peripherals, see [`super::periph_helpers`]. + +use super::PoweredClock; + +/// This type represents a divider in the range 1..=256. +/// +/// At a hardware level, this is an 8-bit register from 0..=255, +/// which adds one. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub struct Div8(pub(super) u8); + +impl Div8 { + /// Store a "raw" divisor value that will divide the source by + /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source + /// by 1, and `Div8::from_raw(255)` will divide the source by + /// 256. + pub const fn from_raw(n: u8) -> Self { + Self(n) + } + + /// Store a specific divisor value that will divide the source + /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source + /// by 1, and `Div8::from_divisor(256)` will divide the source + /// by 256. + /// + /// Will return `None` if `n` is not in the range `1..=256`. + /// Consider [`Self::from_raw`] for an infallible version. + pub const fn from_divisor(n: u16) -> Option { + let Some(n) = n.checked_sub(1) else { + return None; + }; + if n > (u8::MAX as u16) { + return None; + } + Some(Self(n as u8)) + } + + /// Convert into "raw" bits form + #[inline(always)] + pub const fn into_bits(self) -> u8 { + self.0 + } + + /// Convert into "divisor" form, as a u32 for convenient frequency math + #[inline(always)] + pub const fn into_divisor(self) -> u32 { + self.0 as u32 + 1 + } +} + +/// ```text +/// ┌─────────────────────────────────────────────────────────┐ +/// │ │ +/// │ ┌───────────┐ clk_out ┌─────────┐ │ +/// XTAL ──────┼──▷│ System │───────────▷│ │ clk_in │ +/// │ │ OSC │ clkout_byp │ MUX │──────────────────┼──────▷ +/// EXTAL ──────┼──▷│ │───────────▷│ │ │ +/// │ └───────────┘ └─────────┘ │ +/// │ │ +/// │ ┌───────────┐ fro_hf_root ┌────┐ fro_hf │ +/// │ │ FRO180 ├───────┬─────▷│ CG │─────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_45m │ +/// │ │ │ └─────▷│ CG │─────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ ┌───────────┐ fro_12m_root ┌────┐ fro_12m │ +/// │ │ FRO12M │────────┬─────▷│ CG │────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_1m │ +/// │ │ │ └─────▷│1/12│────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ │ +/// │ ┌──────────┐ │ +/// │ │000 │ │ +/// │ clk_in │ │ │ +/// │ ───────────────▷│001 │ │ +/// │ fro_12m │ │ │ +/// │ ───────────────▷│010 │ │ +/// │ fro_hf_root │ │ │ +/// │ ───────────────▷│011 │ main_clk │ +/// │ │ │───────────────────────────┼──────▷ +/// clk_16k ──────┼─────────────────▷│100 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│101 │ │ +/// │ pll1_clk │ │ │ +/// │ ───────────────▷│110 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│111 │ │ +/// │ └──────────┘ │ +/// │ ▲ │ +/// │ │ │ +/// │ SCG SCS │ +/// │ SCG-Lite │ +/// └─────────────────────────────────────────────────────────┘ +/// +/// +/// clk_in ┌─────┐ +/// ───────────────▷│00 │ +/// clk_45m │ │ +/// ───────────────▷│01 │ ┌───────────┐ pll1_clk +/// none │ │─────▷│ SPLL │───────────────▷ +/// ───────────────▷│10 │ └───────────┘ +/// fro_12m │ │ +/// ───────────────▷│11 │ +/// └─────┘ +/// ``` +#[non_exhaustive] +pub struct ClocksConfig { + /// FIRC, FRO180, 45/60/90/180M clock source + pub firc: Option, + /// SIRC, FRO12M, clk_12m clock source + // NOTE: I don't think we *can* disable the SIRC? + pub sirc: SircConfig, + /// FRO16K clock source + pub fro16k: Option, +} + +// FIRC/FRO180M + +/// ```text +/// ┌───────────┐ fro_hf_root ┌────┐ fro_hf +/// │ FRO180M ├───────┬─────▷│GATE│──────────▷ +/// │ │ │ ├────┤ clk_45m +/// │ │ └─────▷│GATE│──────────▷ +/// └───────────┘ └────┘ +/// ``` +#[non_exhaustive] +pub struct FircConfig { + /// Selected clock frequency + pub frequency: FircFreqSel, + /// Selected power state of the clock + pub power: PoweredClock, + /// Is the "fro_hf" gated clock enabled? + pub fro_hf_enabled: bool, + /// Is the "clk_45m" gated clock enabled? + pub clk_45m_enabled: bool, + /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`! + pub fro_hf_div: Option, +} + +/// Selected FIRC frequency +pub enum FircFreqSel { + /// 45MHz Output + Mhz45, + /// 60MHz Output + Mhz60, + /// 90MHz Output + Mhz90, + /// 180MHz Output + Mhz180, +} + +// SIRC/FRO12M + +/// ```text +/// ┌───────────┐ fro_12m_root ┌────┐ fro_12m +/// │ FRO12M │────────┬─────▷│ CG │──────────▷ +/// │ │ │ ├────┤ clk_1m +/// │ │ └─────▷│1/12│──────────▷ +/// └───────────┘ └────┘ +/// ``` +#[non_exhaustive] +pub struct SircConfig { + pub power: PoweredClock, + // peripheral output, aka sirc_12mhz + pub fro_12m_enabled: bool, + /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`! + pub fro_lf_div: Option, +} + +#[non_exhaustive] +pub struct Fro16KConfig { + pub vsys_domain_active: bool, + pub vdd_core_domain_active: bool, +} + +impl Default for ClocksConfig { + fn default() -> Self { + Self { + firc: Some(FircConfig { + frequency: FircFreqSel::Mhz45, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + fro_hf_enabled: true, + clk_45m_enabled: true, + fro_hf_div: None, + }), + sirc: SircConfig { + power: PoweredClock::AlwaysEnabled, + fro_12m_enabled: true, + fro_lf_div: None, + }, + fro16k: Some(Fro16KConfig { + vsys_domain_active: true, + vdd_core_domain_active: true, + }), + } + } +} diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index e04f63b8e..c6606b1b6 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -1,47 +1,335 @@ -//! Clock control helpers (no magic numbers, PAC field access only). -//! Provides reusable gate abstractions for peripherals used by the examples. +//! # Clock Module +//! +//! For the MCX-A, we separate clock and peripheral control into two main stages: +//! +//! 1. At startup, e.g. when `embassy_mcxa::init()` is called, we configure the +//! core system clocks, including external and internal oscillators. This +//! configuration is then largely static for the duration of the program. +//! 2. When HAL drivers are created, e.g. `Lpuart::new()` is called, the driver +//! is responsible for two main things: +//! * Ensuring that any required "upstream" core system clocks necessary for +//! clocking the peripheral is active and configured to a reasonable value +//! * Enabling the clock gates for that peripheral, and resetting the peripheral +//! +//! From a user perspective, only step 1 is visible. Step 2 is automatically handled +//! by HAL drivers, using interfaces defined in this module. +//! +//! It is also possible to *view* the state of the clock configuration after [`init()`] +//! has been called, using the [`with_clocks()`] function, which provides a view of the +//! [`Clocks`] structure. +//! +//! ## For HAL driver implementors +//! +//! The majority of peripherals in the MCXA chip are fed from either a "hard-coded" or +//! configurable clock source, e.g. selecting the FROM12M or `clk_1m` as a source. This +//! selection, as well as often any pre-scaler division from that source clock, is made +//! through MRCC registers. +//! +//! Any peripheral that is controlled through the MRCC register can automatically implement +//! the necessary APIs using the `impl_cc_gate!` macro in this module. You will also need +//! to define the configuration surface and steps necessary to fully configure that peripheral +//! from a clocks perspective by: +//! +//! 1. Defining a configuration type in the [`periph_helpers`] module that contains any selects +//! or divisions available to the HAL driver +//! 2. Implementing the [`periph_helpers::SPConfHelper`] trait, which should check that the +//! necessary input clocks are reasonable + use core::cell::RefCell; +use config::{ClocksConfig, FircConfig, FircFreqSel, Fro16KConfig, SircConfig}; use mcxa_pac::scg0::firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}; use mcxa_pac::scg0::sirccsr::{SircClkPeriphEn, Sircsten}; use periph_helpers::SPConfHelper; use crate::pac; +pub mod config; pub mod periph_helpers; +// +// Statics/Consts +// + +/// The state of system core clocks. +/// +/// Initialized by [`init()`], and then unchanged for the remainder of the program. +static CLOCKS: critical_section::Mutex>> = critical_section::Mutex::new(RefCell::new(None)); + +// +// Free functions +// + +/// Initialize the core system clocks with the given [`ClocksConfig`]. +/// +/// This function should be called EXACTLY once at start-up, usually via a +/// call to [`embassy_mcxa::init()`](crate::init()). Subsequent calls will +/// return an error. +pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { + critical_section::with(|cs| { + if CLOCKS.borrow_ref(cs).is_some() { + Err(ClockError::AlreadyInitialized) + } else { + Ok(()) + } + })?; + + let mut clocks = Clocks::default(); + let mut operator = ClockOperator { + clocks: &mut clocks, + config: &settings, + + _mrcc0: unsafe { pac::Mrcc0::steal() }, + scg0: unsafe { pac::Scg0::steal() }, + syscon: unsafe { pac::Syscon::steal() }, + vbat0: unsafe { pac::Vbat0::steal() }, + }; + + operator.configure_firc_clocks()?; + operator.configure_sirc_clocks()?; + operator.configure_fro16k_clocks()?; + // TODO, everything downstream + + critical_section::with(|cs| { + let mut clks = CLOCKS.borrow_ref_mut(cs); + assert!(clks.is_none(), "Clock setup race!"); + *clks = Some(clocks); + }); + + Ok(()) +} + +/// Obtain the full clocks structure, calling the given closure in a critical section. +/// +/// The given closure will be called with read-only access to the state of the system +/// clocks. This can be used to query and return the state of a given clock. +/// +/// As the caller's closure will be called in a critical section, care must be taken +/// not to block or cause any other undue delays while accessing. +/// +/// Calls to this function will not succeed until after a successful call to `init()`, +/// and will always return None. +pub fn with_clocks R>(f: F) -> Option { + critical_section::with(|cs| { + let c = CLOCKS.borrow_ref(cs); + let c = c.as_ref()?; + Some(f(c)) + }) +} + +// +// Structs/Enums +// + +/// The `Clocks` structure contains the initialized state of the core system clocks +/// +/// These values are configured by providing [`config::ClocksConfig`] to the [`init()`] function +/// at boot time. +#[derive(Default, Debug, Clone)] +#[non_exhaustive] +pub struct Clocks { + /// The `clk_in` is a clock provided by an external oscillator + pub clk_in: Option, + + // FRO180M stuff + // + /// `fro_hf_root` is the direct output of the `FRO180M` internal oscillator + /// + /// It is used to feed downstream clocks, such as `fro_hf`, `clk_45m`, + /// and `fro_hf_div`. + pub fro_hf_root: Option, + + /// `fro_hf` is the same frequency as `fro_hf_root`, but behind a gate. + pub fro_hf: Option, + + /// `clk_45` is a 45MHz clock, sourced from `fro_hf`. + pub clk_45m: Option, + + /// `fro_hf_div` is a configurable frequency clock, sourced from `fro_hf`. + pub fro_hf_div: Option, + + // + // End FRO180M + + // FRO12M stuff + // + /// `fro_12m_root` is the direct output of the `FRO12M` internal oscillator + /// + /// It is used to feed downstream clocks, such as `fro_12m`, `clk_1m`, + /// `and `fro_lf_div`. + pub fro_12m_root: Option, + + /// `fro_12m` is the same frequency as `fro_12m_root`, but behind a gate. + pub fro_12m: Option, + + /// `clk_1m` is a 1MHz clock, sourced from `fro_12m` + pub clk_1m: Option, + + /// `fro_lf_div` is a configurable frequency clock, sourced from `fro_12m` + pub fro_lf_div: Option, + // + // End FRO12M stuff + /// `clk_16k_vsys` is one of two outputs of the `FRO16K` internal oscillator. + /// + /// Also referred to as `clk_16k[0]` in the datasheet, it feeds peripherals in + /// the system domain, such as the CMP and RTC. + pub clk_16k_vsys: Option, + + /// `clk_16k_vdd_core` is one of two outputs of the `FRO16K` internal oscillator. + /// + /// Also referred to as `clk_16k[1]` in the datasheet, it feeds peripherals in + /// the VDD Core domain, such as the OSTimer or LPUarts. + pub clk_16k_vdd_core: Option, + + /// `main_clk` is the main clock used by the CPU, AHB, APB, IPS bus, and some + /// peripherals. + pub main_clk: Option, + + /// `pll1_clk` is the output of the main system PLL, `pll1`. + pub pll1_clk: Option, +} + +/// `ClockError` is the main error returned when configuring or checking clock state +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[non_exhaustive] +pub enum ClockError { + /// The system clocks were never initialized by calling [`init()`] + NeverInitialized, + /// The [`init()`] function was called more than once + AlreadyInitialized, + /// The requested configuration was not possible to fulfill, as the system clocks + /// were not configured in a compatible way + BadConfig { clock: &'static str, reason: &'static str }, + /// The requested configuration was not possible to fulfill, as the required system + /// clocks have not yet been implemented. + NotImplemented { clock: &'static str }, + /// The requested peripheral could not be configured, as the steps necessary to + /// enable it have not yet been implemented. + UnimplementedConfig, +} + +/// Information regarding a system clock +#[derive(Debug, Clone)] +pub struct Clock { + /// The frequency, in Hz, of the given clock + pub frequency: u32, + /// The power state of the clock, e.g. whether it is active in deep sleep mode + /// or not. + pub power: PoweredClock, +} + +/// The power state of a given clock. +/// +/// On the MCX-A, when Deep-Sleep is entered, any clock not configured for Deep Sleep +/// mode will be stopped. This means that any downstream usage, e.g. by peripherals, +/// will also stop. +/// +/// In the future, we will provide an API for entering Deep Sleep, and if there are +/// any peripherals that are NOT using an `AlwaysEnabled` clock active, entry into +/// Deep Sleep will be prevented, in order to avoid misbehaving peripherals. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum PoweredClock { + /// The given clock will NOT continue running in Deep Sleep mode + NormalEnabledDeepSleepDisabled, + /// The given clock WILL continue running in Deep Sleep mode + AlwaysEnabled, +} + +/// The ClockOperator is a private helper type that contains the methods used +/// during system clock initialization. +/// +/// # SAFETY +/// +/// Concurrent access to clock-relevant peripheral registers, such as `MRCC`, `SCG`, +/// `SYSCON`, and `VBAT` should not be allowed for the duration of the [`init()`] function. +struct ClockOperator<'a> { + /// A mutable reference to the current state of system clocks + clocks: &'a mut Clocks, + /// A reference to the requested configuration provided by the caller of [`init()`] + config: &'a ClocksConfig, + + // We hold on to stolen peripherals + _mrcc0: pac::Mrcc0, + scg0: pac::Scg0, + syscon: pac::Syscon, + vbat0: pac::Vbat0, +} + /// Trait describing an AHB clock gate that can be toggled through MRCC. pub trait Gate { type MrccPeriphConfig: SPConfHelper; /// Enable the clock gate. + /// + /// # SAFETY + /// + /// The current peripheral must be disabled prior to calling this method unsafe fn enable_clock(); /// Disable the clock gate. + /// + /// # SAFETY + /// + /// There must be no active user of this peripheral when calling this method unsafe fn disable_clock(); /// Drive the peripheral into reset. + /// + /// # SAFETY + /// + /// There must be no active user of this peripheral when calling this method unsafe fn assert_reset(); /// Drive the peripheral out of reset. + /// + /// # SAFETY + /// + /// There must be no active user of this peripheral when calling this method unsafe fn release_reset(); - /// Return whether the clock gate is currently enabled. + /// Return whether the clock gate for this peripheral is currently enabled. fn is_clock_enabled() -> bool; - /// . + /// Return whether the peripheral is currently held in reset. fn is_reset_released() -> bool; } +/// This is the primary helper method HAL drivers are expected to call when creating +/// an instance of the peripheral. +/// +/// This method: +/// +/// 1. Enables the MRCC clock gate for this peripheral +/// 2. Calls the `G::MrccPeriphConfig::post_enable_config()` method, returning an error +/// and re-disabling the peripheral if this fails. +/// 3. Pulses the MRCC reset line, to reset the peripheral to the default state +/// 4. Returns the frequency, in Hz that is fed into the peripheral, taking into account +/// the selected upstream clock, as well as any division specified by `cfg`. +/// +/// NOTE: if a clock is disabled, sourced from an "ambient" clock source, this method +/// may return `Ok(0)`. In the future, this might be updated to return the correct +/// "ambient" clock, e.g. the AHB/APB frequency. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `enable_and_reset`. #[inline] -pub unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Result { - let freq = enable::(cfg)?; +pub(crate) unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Result { + let freq = enable::(cfg).inspect_err(|_| disable::())?; pulse_reset::(); Ok(freq) } -/// Enable a clock gate for the given peripheral set. +/// Enable the clock gate for the given peripheral. +/// +/// Prefer [`enable_and_reset`] unless you are specifically avoiding a pulse of the reset, or need +/// to control the duration of the pulse more directly. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `enable`. #[inline] -pub unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result { +pub(crate) unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result { G::enable_clock(); while !G::is_clock_enabled() {} core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); @@ -57,237 +345,182 @@ pub unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result() { +/// Disable the clock gate for the given peripheral. +/// +/// # SAFETY +/// +/// This peripheral must no longer be in use prior to calling `enable`. +#[allow(dead_code)] +#[inline] +pub(crate) unsafe fn disable() { G::disable_clock(); } /// Check whether a gate is currently enabled. +#[allow(dead_code)] #[inline] -pub fn is_clock_enabled() -> bool { +pub(crate) fn is_clock_enabled() -> bool { G::is_clock_enabled() } /// Release a reset line for the given peripheral set. +/// +/// Prefer [`enable_and_reset`]. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `release_reset`. #[inline] -pub unsafe fn release_reset() { +pub(crate) unsafe fn release_reset() { G::release_reset(); } /// Assert a reset line for the given peripheral set. +/// +/// Prefer [`enable_and_reset`]. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `assert_reset`. #[inline] -pub unsafe fn assert_reset() { +pub(crate) unsafe fn assert_reset() { G::assert_reset(); } +/// Check whether the peripheral is held in reset. #[inline] -pub unsafe fn is_reset_released() -> bool { +pub(crate) unsafe fn is_reset_released() -> bool { G::is_reset_released() } /// Pulse a reset line (assert then release) with a short delay. +/// +/// Prefer [`enable_and_reset`]. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `release_reset`. #[inline] -pub unsafe fn pulse_reset() { +pub(crate) unsafe fn pulse_reset() { G::assert_reset(); cortex_m::asm::nop(); cortex_m::asm::nop(); G::release_reset(); } -macro_rules! impl_cc_gate { - ($name:ident, $reg:ident, $field:ident, $config:ty) => { - impl Gate for crate::peripherals::$name { - type MrccPeriphConfig = $config; - - #[inline] - unsafe fn enable_clock() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_, w| w.$field().enabled()); - } - - #[inline] - unsafe fn disable_clock() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_r, w| w.$field().disabled()); - } - - #[inline] - fn is_clock_enabled() -> bool { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().read().$field().is_enabled() - } - - #[inline] - unsafe fn release_reset() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_, w| w.$field().enabled()); - } - - #[inline] - unsafe fn assert_reset() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_, w| w.$field().disabled()); - } +// +// `impl`s for structs/enums +// - #[inline] - fn is_reset_released() -> bool { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().read().$field().is_enabled() - } +/// The [`Clocks`] type's methods generally take the form of "ensure X clock is active". +/// +/// These methods are intended to be used by HAL peripheral implementors to ensure that their +/// selected clocks are active at a suitable level at time of construction. These methods +/// return the frequency of the requested clock, in Hertz, or a [`ClockError`]. +impl Clocks { + /// Ensure the `fro_lf_div` clock is active and valid at the given power state. + pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_lf_div.as_ref() else { + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "not low power active", + }); } - }; -} - -pub struct UnimplementedConfig; -impl SPConfHelper for UnimplementedConfig { - fn post_enable_config(&self, _clocks: &Clocks) -> Result { - Err(ClockError::UnimplementedConfig) - } -} - -pub struct NoConfig; -impl SPConfHelper for NoConfig { - fn post_enable_config(&self, _clocks: &Clocks) -> Result { - Ok(0) + Ok(clk.frequency) } -} - -pub mod gate { - use super::periph_helpers::{AdcConfig, LpuartConfig, OsTimerConfig}; - use super::*; - // These peripherals have no additional upstream clocks or configuration required - // other than enabling through the MRCC gate. - impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, NoConfig); - impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, NoConfig); - impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, NoConfig); - impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig); - - impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, OsTimerConfig); - impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig); - impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, AdcConfig); -} - -// /// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART. -// pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// enable::(peripherals); -// } - -// /// Convenience helper enabling the PORT3 and GPIO3 gates used by the LED in the examples. -// pub unsafe fn enable_led_port(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// enable::(peripherals); -// } - -// /// Convenience helper enabling the OSTIMER0 clock gate. -// pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// } - -// pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { -// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 -// let mrcc = &peripherals.mrcc0; -// mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0()); -// mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); -// } - -// pub unsafe fn ensure_frolf_running(peripherals: &pac::Peripherals) { -// // Ensure FRO_LF divider clock is running (reset default HALT=1 stops it) -// let sys = &peripherals.syscon; -// sys.frolfdiv().modify(|_, w| { -// // DIV defaults to 0; keep it explicit and clear HALT -// unsafe { w.div().bits(0) }.halt().run() -// }); -// } - -// /// Compute the FRO_LF_DIV output frequency currently selected for LPUART2. -// /// Assumes select_uart2_clock() has chosen MUX=0 (FRO_LF_DIV) and DIV is set in SYSCON.FRO_LF_DIV. -// pub unsafe fn uart2_src_hz(peripherals: &pac::Peripherals) -> u32 { -// // SYSCON.FRO_LF_DIV: DIV field is simple divider: freq_out = 12_000_000 / (DIV+1) for many NXP parts. -// // On MCXA276 FRO_LF base is 12 MHz; our init keeps DIV=0, so result=12_000_000. -// // Read it anyway for future generality. -// let div = peripherals.syscon.frolfdiv().read().div().bits() as u32; -// let base = 12_000_000u32; -// base / (div + 1) -// } - -// /// Enable clock gate and release reset for OSTIMER0. -// /// Select OSTIMER0 clock source = 1 MHz root (working bring-up configuration). -// pub unsafe fn select_ostimer0_clock_1m(peripherals: &pac::Peripherals) { -// let mrcc = &peripherals.mrcc0; -// mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); -// } - -// pub unsafe fn enable_adc(peripherals: &pac::Peripherals) { -// enable::(peripherals); -// enable::(peripherals); -// } - -// pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { -// // Use FRO_LF_DIV (already running) MUX=0 DIV=0 -// let mrcc = &peripherals.mrcc0; -// mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0()); -// mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); -// } - -// ============================================== - -/// This type represents a divider in the range 1..=256. -/// -/// At a hardware level, this is an 8-bit register from 0..=255, -/// which adds one. -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub struct Div8(pub(super) u8); - -impl Div8 { - /// Store a "raw" divisor value that will divide the source by - /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source - /// by 1, and `Div8::from_raw(255)` will divide the source by - /// 256. - pub const fn from_raw(n: u8) -> Self { - Self(n) + /// Ensure the `fro_hf` clock is active and valid at the given power state. + pub fn ensure_fro_hf_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_hf.as_ref() else { + return Err(ClockError::BadConfig { + clock: "fro_hf", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "fro_hf", + reason: "not low power active", + }); + } + Ok(clk.frequency) } - /// Store a specific divisor value that will divide the source - /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source - /// by 1, and `Div8::from_divisor(256)` will divide the source - /// by 256. - /// - /// Will return `None` if `n` is not in the range `1..=256`. - /// Consider [`Self::from_raw`] for an infallible version. - pub const fn from_divisor(n: u16) -> Option { - let Some(n) = n.checked_sub(1) else { - return None; + /// Ensure the `fro_hf_div` clock is active and valid at the given power state. + pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_hf_div.as_ref() else { + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "required but not active", + }); }; - if n > (u8::MAX as u16) { - return None; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "not low power active", + }); } - Some(Self(n as u8)) + Ok(clk.frequency) } - /// Convert into "raw" bits form - #[inline(always)] - pub const fn into_bits(self) -> u8 { - self.0 + /// Ensure the `clk_in` clock is active and valid at the given power state. + pub fn ensure_clk_in_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "clk_in" }) } - /// Convert into "divisor" form, as a u32 for convenient frequency math - #[inline(always)] - pub const fn into_divisor(self) -> u32 { - self.0 as u32 + 1 + /// Ensure the `clk_16k_vsys` clock is active and valid at the given power state. + pub fn ensure_clk_16k_vsys_active(&self, _at_level: &PoweredClock) -> Result { + // NOTE: clk_16k is always active in low power mode + Ok(self + .clk_16k_vsys + .as_ref() + .ok_or(ClockError::BadConfig { + clock: "clk_16k_vsys", + reason: "required but not active", + })? + .frequency) } -} -#[derive(Debug, Clone)] -pub struct Clock { - pub frequency: u32, - pub power: PoweredClock, -} + /// Ensure the `clk_16k_vdd_core` clock is active and valid at the given power state. + pub fn ensure_clk_16k_vdd_core_active(&self, _at_level: &PoweredClock) -> Result { + // NOTE: clk_16k is always active in low power mode + Ok(self + .clk_16k_vdd_core + .as_ref() + .ok_or(ClockError::BadConfig { + clock: "clk_16k_vdd_core", + reason: "required but not active", + })? + .frequency) + } + + /// Ensure the `clk_1m` clock is active and valid at the given power state. + pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.clk_1m.as_ref() else { + return Err(ClockError::BadConfig { + clock: "clk_1m", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "clk_1m", + reason: "not low power active", + }); + } + Ok(clk.frequency) + } -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub enum PoweredClock { - NormalEnabledDeepSleepDisabled, - AlwaysEnabled, + /// Ensure the `pll1_clk_div` clock is active and valid at the given power state. + pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "pll1_clk_div" }) + } } impl PoweredClock { @@ -302,172 +535,11 @@ impl PoweredClock { } } -/// ```text -/// ┌─────────────────────────────────────────────────────────┐ -/// │ │ -/// │ ┌───────────┐ clk_out ┌─────────┐ │ -/// XTAL ──────┼──▷│ System │───────────▷│ │ clk_in │ -/// │ │ OSC │ clkout_byp │ MUX │──────────────────┼──────▷ -/// EXTAL ──────┼──▷│ │───────────▷│ │ │ -/// │ └───────────┘ └─────────┘ │ -/// │ │ -/// │ ┌───────────┐ fro_hf_root ┌────┐ fro_hf │ -/// │ │ FRO180 ├───────┬─────▷│ CG │─────────────────────┼──────▷ -/// │ │ │ │ ├────┤ clk_45m │ -/// │ │ │ └─────▷│ CG │─────────────────────┼──────▷ -/// │ └───────────┘ └────┘ │ -/// │ ┌───────────┐ fro_12m_root ┌────┐ fro_12m │ -/// │ │ FRO12M │────────┬─────▷│ CG │────────────────────┼──────▷ -/// │ │ │ │ ├────┤ clk_1m │ -/// │ │ │ └─────▷│1/12│────────────────────┼──────▷ -/// │ └───────────┘ └────┘ │ -/// │ │ -/// │ ┌──────────┐ │ -/// │ │000 │ │ -/// │ clk_in │ │ │ -/// │ ───────────────▷│001 │ │ -/// │ fro_12m │ │ │ -/// │ ───────────────▷│010 │ │ -/// │ fro_hf_root │ │ │ -/// │ ───────────────▷│011 │ main_clk │ -/// │ │ │───────────────────────────┼──────▷ -/// clk_16k ──────┼─────────────────▷│100 │ │ -/// │ none │ │ │ -/// │ ───────────────▷│101 │ │ -/// │ pll1_clk │ │ │ -/// │ ───────────────▷│110 │ │ -/// │ none │ │ │ -/// │ ───────────────▷│111 │ │ -/// │ └──────────┘ │ -/// │ ▲ │ -/// │ │ │ -/// │ SCG SCS │ -/// │ SCG-Lite │ -/// └─────────────────────────────────────────────────────────┘ -/// -/// -/// clk_in ┌─────┐ -/// ───────────────▷│00 │ -/// clk_45m │ │ -/// ───────────────▷│01 │ ┌───────────┐ pll1_clk -/// none │ │─────▷│ SPLL │───────────────▷ -/// ───────────────▷│10 │ └───────────┘ -/// fro_12m │ │ -/// ───────────────▷│11 │ -/// └─────┘ -/// ``` -#[non_exhaustive] -pub struct ClocksConfig { - // FIRC, FRO180, 45/60/90/180M clock source - pub firc: Option, - // NOTE: I don't think we *can* disable the SIRC? - pub sirc: SircConfig, - pub fro16k: Option, -} - -// FIRC/FRO180M - -/// ```text -/// ┌───────────┐ fro_hf_root ┌────┐ fro_hf -/// │ FRO180M ├───────┬─────▷│GATE│──────────▷ -/// │ │ │ ├────┤ clk_45m -/// │ │ └─────▷│GATE│──────────▷ -/// └───────────┘ └────┘ -/// ``` -#[non_exhaustive] -pub struct FircConfig { - pub frequency: FircFreqSel, - pub power: PoweredClock, - /// Is the "fro_hf" gated clock enabled? - pub fro_hf_enabled: bool, - /// Is the "clk_45m" gated clock enabled? - pub clk_45m_enabled: bool, - /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`! - pub fro_hf_div: Option, -} - -pub enum FircFreqSel { - Mhz45, - Mhz60, - Mhz90, - Mhz180, -} - -// SIRC/FRO12M - -/// ```text -/// ┌───────────┐ fro_12m_root ┌────┐ fro_12m -/// │ FRO12M │────────┬─────▷│ CG │──────────▷ -/// │ │ │ ├────┤ clk_1m -/// │ │ └─────▷│1/12│──────────▷ -/// └───────────┘ └────┘ -/// ``` -#[non_exhaustive] -pub struct SircConfig { - pub power: PoweredClock, - // peripheral output, aka sirc_12mhz - pub fro_12m_enabled: bool, - /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`! - pub fro_lf_div: Option, -} - -#[derive(Default, Debug, Clone)] -#[non_exhaustive] -pub struct Clocks { - pub clk_in: Option, - - // FRO180M stuff - // - pub fro_hf_root: Option, - pub fro_hf: Option, - pub clk_45m: Option, - pub fro_hf_div: Option, - // - // End FRO180M - - // FRO12M stuff - pub fro_12m_root: Option, - pub fro_12m: Option, - pub clk_1m: Option, - pub fro_lf_div: Option, - // - // End FRO12M stuff - pub clk_16k_vsys: Option, - pub clk_16k_vdd_core: Option, - pub main_clk: Option, - pub pll1_clk: Option, -} - -#[non_exhaustive] -pub struct Fro16KConfig { - pub vsys_domain_active: bool, - pub vdd_core_domain_active: bool, -} - -static CLOCKS: critical_section::Mutex>> = critical_section::Mutex::new(RefCell::new(None)); - -#[derive(Debug, Copy, Clone, Eq, PartialEq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[non_exhaustive] -pub enum ClockError { - NeverInitialized, - AlreadyInitialized, - BadConfig { clock: &'static str, reason: &'static str }, - NotImplemented { clock: &'static str }, - UnimplementedConfig, -} - -struct ClockOperator<'a> { - clocks: &'a mut Clocks, - config: &'a ClocksConfig, - - _mrcc0: pac::Mrcc0, - scg0: pac::Scg0, - syscon: pac::Syscon, - vbat0: pac::Vbat0, -} - impl ClockOperator<'_> { + /// Configure the FIRC/FRO180M clock family + /// + /// NOTE: Currently we require this to be a fairly hardcoded value, as this clock is used + /// as the main clock used for the CPU, AHB, APB, etc. fn configure_firc_clocks(&mut self) -> Result<(), ClockError> { const HARDCODED_ERR: Result<(), ClockError> = Err(ClockError::BadConfig { clock: "firc", @@ -484,7 +556,7 @@ impl ClockOperator<'_> { } let base_freq = 45_000_000; - // Is the FIRC as expected? + // Now, check if the FIRC as expected for our hardcoded value let mut firc_ok = true; // Is the hardware currently set to the default 45MHz? @@ -604,6 +676,7 @@ impl ClockOperator<'_> { Ok(()) } + /// Configure the SIRC/FRO12M clock family fn configure_sirc_clocks(&mut self) -> Result<(), ClockError> { let SircConfig { power, @@ -694,6 +767,7 @@ impl ClockOperator<'_> { Ok(()) } + /// Configure the FRO16K/clk_16k clock family fn configure_fro16k_clocks(&mut self) -> Result<(), ClockError> { let Some(fro16k) = self.config.fro16k.as_ref() else { return Ok(()); @@ -735,145 +809,74 @@ impl ClockOperator<'_> { } } -pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { - critical_section::with(|cs| { - if CLOCKS.borrow_ref(cs).is_some() { - Err(ClockError::AlreadyInitialized) - } else { - Ok(()) - } - })?; - - let mut clocks = Clocks::default(); - let mut operator = ClockOperator { - clocks: &mut clocks, - config: &settings, - - _mrcc0: unsafe { pac::Mrcc0::steal() }, - scg0: unsafe { pac::Scg0::steal() }, - syscon: unsafe { pac::Syscon::steal() }, - vbat0: unsafe { pac::Vbat0::steal() }, - }; +// +// Macros/macro impls +// - operator.configure_firc_clocks()?; - operator.configure_sirc_clocks()?; - operator.configure_fro16k_clocks()?; - // TODO, everything downstream +/// This macro is used to implement the [`Gate`] trait for a given peripheral +/// that is controlled by the MRCC peripheral. +macro_rules! impl_cc_gate { + ($name:ident, $reg:ident, $field:ident, $config:ty) => { + impl Gate for crate::peripherals::$name { + type MrccPeriphConfig = $config; - critical_section::with(|cs| { - let mut clks = CLOCKS.borrow_ref_mut(cs); - assert!(clks.is_none(), "Clock setup race!"); - *clks = Some(clocks); - }); + #[inline] + unsafe fn enable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_, w| w.$field().enabled()); + } - Ok(()) -} + #[inline] + unsafe fn disable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_r, w| w.$field().disabled()); + } -/// Obtain the full clocks structure, calling the given closure in a critical section -/// -/// NOTE: Clocks implements `Clone`, -pub fn with_clocks R>(f: F) -> Option { - critical_section::with(|cs| { - let c = CLOCKS.borrow_ref(cs); - let c = c.as_ref()?; - Some(f(c)) - }) -} + #[inline] + fn is_clock_enabled() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().read().$field().is_enabled() + } -impl Clocks { - pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.fro_lf_div.as_ref() else { - return Err(ClockError::BadConfig { - clock: "fro_lf_div", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "fro_lf_div", - reason: "not low power active", - }); - } - Ok(clk.frequency) - } + #[inline] + unsafe fn release_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_, w| w.$field().enabled()); + } - pub fn ensure_fro_hf_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.fro_hf.as_ref() else { - return Err(ClockError::BadConfig { - clock: "fro_hf", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "fro_hf", - reason: "not low power active", - }); - } - Ok(clk.frequency) - } + #[inline] + unsafe fn assert_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().modify(|_, w| w.$field().disabled()); + } - pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.fro_hf_div.as_ref() else { - return Err(ClockError::BadConfig { - clock: "fro_hf_div", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "fro_hf_div", - reason: "not low power active", - }); + #[inline] + fn is_reset_released() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$reg().read().$field().is_enabled() + } } - Ok(clk.frequency) - } - - pub fn ensure_clk_in_active(&self, _at_level: &PoweredClock) -> Result { - Err(ClockError::NotImplemented { clock: "clk_in" }) - } - - pub fn ensure_clk_16k_vsys_active(&self, _at_level: &PoweredClock) -> Result { - // NOTE: clk_16k is always active in low power mode - Ok(self - .clk_16k_vsys - .as_ref() - .ok_or(ClockError::BadConfig { - clock: "clk_16k_vsys", - reason: "required but not active", - })? - .frequency) - } + }; +} - pub fn ensure_clk_16k_vdd_core_active(&self, _at_level: &PoweredClock) -> Result { - // NOTE: clk_16k is always active in low power mode - Ok(self - .clk_16k_vdd_core - .as_ref() - .ok_or(ClockError::BadConfig { - clock: "clk_16k_vdd_core", - reason: "required but not active", - })? - .frequency) - } +/// This module contains implementations of MRCC APIs, specifically of the [`Gate`] trait, +/// for various low level peripherals. +pub(crate) mod gate { + use super::periph_helpers::{AdcConfig, LpuartConfig, NoConfig, OsTimerConfig}; + use super::*; - pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.clk_1m.as_ref() else { - return Err(ClockError::BadConfig { - clock: "clk_1m", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "clk_1m", - reason: "not low power active", - }); - } - Ok(clk.frequency) - } + // These peripherals have no additional upstream clocks or configuration required + // other than enabling through the MRCC gate. Currently, these peripherals will + // ALWAYS return `Ok(0)` when calling [`enable_and_reset()`] and/or + // [`SPConfHelper::post_enable_config()`]. + impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, NoConfig); + impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, NoConfig); + impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, NoConfig); + impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig); - pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result { - Err(ClockError::NotImplemented { clock: "pll1_clk_div" }) - } + // These peripherals DO have meaningful configuration, and could fail if the system + // clocks do not match their needs. + impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, OsTimerConfig); + impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig); + impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, AdcConfig); } diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index 1657bd7eb..e5b234c5b 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -1,7 +1,43 @@ +//! Peripheral Helpers +//! +//! The purpose of this module is to define the per-peripheral special handling +//! required from a clocking perspective. Different peripherals have different +//! selectable source clocks, and some peripherals have additional pre-dividers +//! that can be used. +//! +//! See the docs of [`SPConfHelper`] for more details. + use super::{ClockError, Clocks, PoweredClock}; use crate::pac; +/// Sealed Peripheral Configuration Helper +/// +/// NOTE: the name "sealed" doesn't *totally* make sense because its not sealed yet in the +/// embassy-mcxa project, but it derives from embassy-imxrt where it is. We should +/// fix the name, or actually do the sealing of peripherals. +/// +/// This trait serves to act as a per-peripheral customization for clocking behavior. +/// +/// This trait should be implemented on a configuration type for a given peripheral, and +/// provide the methods that will be called by the higher level operations like +/// `embassy_mcxa::clocks::enable_and_reset()`. pub trait SPConfHelper { + /// This method is called AFTER a given MRCC peripheral has been enabled (e.g. un-gated), + /// but BEFORE the peripheral reset line is reset. + /// + /// This function should check that any relevant upstream clocks are enabled, are in a + /// reasonable power state, and that the requested configuration can be made. If any of + /// these checks fail, an `Err(ClockError)` should be returned, likely `ClockError::BadConfig`. + /// + /// This function SHOULD NOT make any changes to the system clock configuration, even + /// unsafely, as this should remain static for the duration of the program. + /// + /// This function WILL be called in a critical section, care should be taken not to delay + /// for an unreasonable amount of time. + /// + /// On success, this function MUST return an `Ok(freq)`, where `freq` is the frequency + /// fed into the peripheral, taking into account the selected source clock, as well as + /// any pre-divisors. fn post_enable_config(&self, clocks: &Clocks) -> Result; } @@ -65,6 +101,33 @@ impl Div4 { } } +/// A basic type that always returns an error when `post_enable_config` is called. +/// +/// Should only be used as a placeholder. +pub struct UnimplementedConfig; + +impl SPConfHelper for UnimplementedConfig { + fn post_enable_config(&self, _clocks: &Clocks) -> Result { + Err(ClockError::UnimplementedConfig) + } +} + +/// A basic type that always returns `Ok(0)` when `post_enable_config` is called. +/// +/// This should only be used for peripherals that are "ambiently" clocked, like `PORTn` +/// peripherals, which have no selectable/configurable source clock. +pub struct NoConfig; +impl SPConfHelper for NoConfig { + fn post_enable_config(&self, _clocks: &Clocks) -> Result { + Ok(0) + } +} + +// +// LPUart +// + +/// Selectable clocks for Lpuart peripherals #[derive(Debug, Clone, Copy)] pub enum LpuartClockSel { /// FRO12M/FRO_LF/SIRC clock source, passed through divider @@ -86,16 +149,26 @@ pub enum LpuartClockSel { None, } +/// Which instance of the Lpuart is this? +/// +/// Should not be directly selectable by end-users. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub enum LpuartInstance { + /// Instance 0 Lpuart0, + /// Instance 1 Lpuart1, + /// Instance 2 Lpuart2, + /// Instance 3 Lpuart3, + /// Instance 4 Lpuart4, + /// Instance 5 Lpuart5, } +/// Top level configuration for `Lpuart` instances. pub struct LpuartConfig { /// Power state required for this peripheral pub power: PoweredClock, @@ -108,39 +181,6 @@ pub struct LpuartConfig { pub(crate) instance: LpuartInstance, } -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub enum OstimerClockSel { - /// 16k clock, sourced from FRO16K (Vdd Core) - Clk16kVddCore, - /// 1 MHz Clock sourced from FRO12M - Clk1M, - /// Disabled - None, -} - -pub struct OsTimerConfig { - pub power: PoweredClock, - pub source: OstimerClockSel, -} - -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub enum AdcClockSel { - FroLfDiv, - FroHf, - ClkIn, - Clk1M, - Pll1ClkDiv, - None, -} - -pub struct AdcConfig { - pub power: PoweredClock, - pub source: AdcClockSel, - pub div: Div4, -} - -// impls - impl SPConfHelper for LpuartConfig { fn post_enable_config(&self, clocks: &Clocks) -> Result { // check that source is suitable @@ -215,6 +255,29 @@ impl SPConfHelper for LpuartConfig { } } +// +// OSTimer +// + +/// Selectable clocks for the OSTimer peripheral +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum OstimerClockSel { + /// 16k clock, sourced from FRO16K (Vdd Core) + Clk16kVddCore, + /// 1 MHz Clock sourced from FRO12M + Clk1M, + /// Disabled + None, +} + +/// Top level configuration for the `OSTimer` peripheral +pub struct OsTimerConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Selected clock source for this peripheral + pub source: OstimerClockSel, +} + impl SPConfHelper for OsTimerConfig { fn post_enable_config(&self, clocks: &Clocks) -> Result { let mrcc0 = unsafe { pac::Mrcc0::steal() }; @@ -237,6 +300,37 @@ impl SPConfHelper for OsTimerConfig { } } +// +// Adc +// + +/// Selectable clocks for the ADC peripheral +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum AdcClockSel { + /// Divided `fro_lf`/`clk_12m`/FRO12M source + FroLfDiv, + /// Gated `fro_hf`/`FRO180M` source + FroHf, + /// External Clock Source + ClkIn, + /// 1MHz clock sourced by a divided `fro_lf`/`clk_12m` + Clk1M, + /// Internal PLL output, with configurable divisor + Pll1ClkDiv, + /// No clock/disabled + None, +} + +/// Top level configuration for the ADC peripheral +pub struct AdcConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Selected clock-source for this peripheral + pub source: AdcClockSel, + /// Pre-divisor, applied to the upstream clock output + pub div: Div4, +} + impl SPConfHelper for AdcConfig { fn post_enable_config(&self, clocks: &Clocks) -> Result { use mcxa_pac::mrcc0::mrcc_adc_clksel::Mux; diff --git a/src/config.rs b/src/config.rs index 93aed5a99..0939c11f1 100644 --- a/src/config.rs +++ b/src/config.rs @@ -1,5 +1,6 @@ // HAL configuration (minimal), mirroring embassy-imxrt style +use crate::clocks::config::ClocksConfig; use crate::interrupt::Priority; #[non_exhaustive] @@ -7,6 +8,7 @@ pub struct Config { pub time_interrupt_priority: Priority, pub rtc_interrupt_priority: Priority, pub adc_interrupt_priority: Priority, + pub clock_cfg: ClocksConfig, } impl Default for Config { @@ -15,6 +17,7 @@ impl Default for Config { time_interrupt_priority: Priority::from(0), rtc_interrupt_priority: Priority::from(0), adc_interrupt_priority: Priority::from(0), + clock_cfg: ClocksConfig::default(), } } } -- cgit From a8ca36cdbe06e83019279e441ac386a448c12edb Mon Sep 17 00:00:00 2001 From: James Munns Date: Mon, 17 Nov 2025 14:58:26 +0100 Subject: Fill in main_clk state --- src/clocks/mod.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index c6606b1b6..40acb11ec 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -87,7 +87,12 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { operator.configure_firc_clocks()?; operator.configure_sirc_clocks()?; operator.configure_fro16k_clocks()?; - // TODO, everything downstream + + // For now, just use FIRC as the main/cpu clock, which should already be + // the case on reset + assert!(operator.scg0.rccr().read().scs().is_firc()); + assert_eq!(operator.syscon.ahbclkdiv().read().div().bits(), 0); + operator.clocks.main_clk = Some(operator.clocks.fro_hf_root.clone().unwrap()); critical_section::with(|cs| { let mut clks = CLOCKS.borrow_ref_mut(cs); -- cgit From a0c8e2d0299f3ae8eb24cd264d2b8e87f2bce464 Mon Sep 17 00:00:00 2001 From: James Munns Date: Mon, 17 Nov 2025 15:02:26 +0100 Subject: Restore examples --- examples/src/lib.rs | 8 ++++---- src/clocks/mod.rs | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/examples/src/lib.rs b/examples/src/lib.rs index be4761c32..2018a3c25 100644 --- a/examples/src/lib.rs +++ b/examples/src/lib.rs @@ -12,20 +12,20 @@ use {embassy_mcxa as hal, panic_probe as _}; pub unsafe fn init_uart2_pins(_p: &hal::pac::Peripherals) { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. // GPIO has not. - _ = clocks::enable_and_reset::(&clocks::NoConfig); + _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); pins::configure_uart2_pins_port2(); } /// Initialize clocks for the LED GPIO/PORT used by the blink example. pub unsafe fn init_led_gpio_clocks(_p: &hal::pac::Peripherals) { - _ = clocks::enable_and_reset::(&clocks::NoConfig); - _ = clocks::enable_and_reset::(&clocks::NoConfig); + _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); + _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); } /// Initialize clocks and pin muxing for ADC. pub unsafe fn init_adc_pins(_p: &hal::pac::Peripherals) { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. // GPIO has not. - _ = clocks::enable_and_reset::(&clocks::NoConfig); + _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); pins::configure_adc_pins(); } diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index 40acb11ec..74a1f1a1f 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -319,7 +319,7 @@ pub trait Gate { /// /// This peripheral must not yet be in use prior to calling `enable_and_reset`. #[inline] -pub(crate) unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Result { +pub unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Result { let freq = enable::(cfg).inspect_err(|_| disable::())?; pulse_reset::(); Ok(freq) @@ -334,7 +334,7 @@ pub(crate) unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Res /// /// This peripheral must not yet be in use prior to calling `enable`. #[inline] -pub(crate) unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result { +pub unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result { G::enable_clock(); while !G::is_clock_enabled() {} core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); @@ -357,14 +357,14 @@ pub(crate) unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result() { +pub unsafe fn disable() { G::disable_clock(); } /// Check whether a gate is currently enabled. #[allow(dead_code)] #[inline] -pub(crate) fn is_clock_enabled() -> bool { +pub fn is_clock_enabled() -> bool { G::is_clock_enabled() } @@ -376,7 +376,7 @@ pub(crate) fn is_clock_enabled() -> bool { /// /// This peripheral must not yet be in use prior to calling `release_reset`. #[inline] -pub(crate) unsafe fn release_reset() { +pub unsafe fn release_reset() { G::release_reset(); } @@ -388,13 +388,13 @@ pub(crate) unsafe fn release_reset() { /// /// This peripheral must not yet be in use prior to calling `assert_reset`. #[inline] -pub(crate) unsafe fn assert_reset() { +pub unsafe fn assert_reset() { G::assert_reset(); } /// Check whether the peripheral is held in reset. #[inline] -pub(crate) unsafe fn is_reset_released() -> bool { +pub unsafe fn is_reset_released() -> bool { G::is_reset_released() } @@ -406,7 +406,7 @@ pub(crate) unsafe fn is_reset_released() -> bool { /// /// This peripheral must not yet be in use prior to calling `release_reset`. #[inline] -pub(crate) unsafe fn pulse_reset() { +pub unsafe fn pulse_reset() { G::assert_reset(); cortex_m::asm::nop(); cortex_m::asm::nop(); -- cgit From 02285c2153d22f2c0c93a4ce920cdebc03f18658 Mon Sep 17 00:00:00 2001 From: James Munns Date: Mon, 17 Nov 2025 16:38:32 +0100 Subject: Correct clk/rst field logic --- examples/memory.x | 4 ++-- examples/src/lib.rs | 2 +- src/clocks/mod.rs | 28 ++++++++++++++-------------- src/lib.rs | 5 ++++- 4 files changed, 21 insertions(+), 18 deletions(-) diff --git a/examples/memory.x b/examples/memory.x index f4263a412..528545b64 100644 --- a/examples/memory.x +++ b/examples/memory.x @@ -1,5 +1,5 @@ MEMORY { - FLASH : ORIGIN = 0x20000000, LENGTH = 64K - RAM : ORIGIN = 0x20010000, LENGTH = 64K + FLASH : ORIGIN = 0x20000000, LENGTH = 80K + RAM : ORIGIN = 0x20014000, LENGTH = 48K } diff --git a/examples/src/lib.rs b/examples/src/lib.rs index 2018a3c25..4bb334da5 100644 --- a/examples/src/lib.rs +++ b/examples/src/lib.rs @@ -5,7 +5,7 @@ //! These live with the examples so the HAL stays generic. use hal::{clocks, pins}; -use {embassy_mcxa as hal, panic_probe as _}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; /// Initialize clocks and pin muxing for UART2 debug console. /// Safe to call multiple times; writes are idempotent for our use. diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index 74a1f1a1f..e02840592 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -821,44 +821,44 @@ impl ClockOperator<'_> { /// This macro is used to implement the [`Gate`] trait for a given peripheral /// that is controlled by the MRCC peripheral. macro_rules! impl_cc_gate { - ($name:ident, $reg:ident, $field:ident, $config:ty) => { + ($name:ident, $clk_reg:ident, $rst_reg:ident, $field:ident, $config:ty) => { impl Gate for crate::peripherals::$name { type MrccPeriphConfig = $config; #[inline] unsafe fn enable_clock() { let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_, w| w.$field().enabled()); + mrcc.$clk_reg().modify(|_, w| w.$field().enabled()); } #[inline] unsafe fn disable_clock() { let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_r, w| w.$field().disabled()); + mrcc.$clk_reg().modify(|_r, w| w.$field().disabled()); } #[inline] fn is_clock_enabled() -> bool { let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().read().$field().is_enabled() + mrcc.$clk_reg().read().$field().is_enabled() } #[inline] unsafe fn release_reset() { let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_, w| w.$field().enabled()); + mrcc.$rst_reg().modify(|_, w| w.$field().enabled()); } #[inline] unsafe fn assert_reset() { let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().modify(|_, w| w.$field().disabled()); + mrcc.$rst_reg().modify(|_, w| w.$field().disabled()); } #[inline] fn is_reset_released() -> bool { let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$reg().read().$field().is_enabled() + mrcc.$rst_reg().read().$field().is_enabled() } } }; @@ -874,14 +874,14 @@ pub(crate) mod gate { // other than enabling through the MRCC gate. Currently, these peripherals will // ALWAYS return `Ok(0)` when calling [`enable_and_reset()`] and/or // [`SPConfHelper::post_enable_config()`]. - impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, NoConfig); - impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, NoConfig); - impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, NoConfig); - impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig); + impl_cc_gate!(PORT1, mrcc_glb_cc1, mrcc_glb_rst1, port1, NoConfig); + impl_cc_gate!(PORT2, mrcc_glb_cc1, mrcc_glb_rst1, port2, NoConfig); + impl_cc_gate!(PORT3, mrcc_glb_cc1, mrcc_glb_rst1, port3, NoConfig); + impl_cc_gate!(GPIO3, mrcc_glb_cc2, mrcc_glb_rst2, gpio3, NoConfig); // These peripherals DO have meaningful configuration, and could fail if the system // clocks do not match their needs. - impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, OsTimerConfig); - impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig); - impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, AdcConfig); + impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); + impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig); + impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig); } diff --git a/src/lib.rs b/src/lib.rs index 1bf54a98b..86c0dc45b 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -47,7 +47,6 @@ pub use rtc::Rtc0 as Rtc0Token; /// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. /// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). -#[allow(unused_variables)] pub fn init(cfg: crate::config::Config) -> Peripherals { let peripherals = Peripherals::take(); // Apply user-configured priority early; enabling is left to examples/apps @@ -56,6 +55,10 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); // Apply user-configured priority early; enabling is left to examples/apps crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority); + + // Configure clocks + crate::clocks::init(cfg.clock_cfg).unwrap(); + peripherals } -- cgit From 011c3b2de9361496faa0eea75ae19a77f2698f88 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 17 Nov 2025 11:25:18 -0800 Subject: chore(deps): bump embedded-io-async from 0.6.1 to 0.7.0 (#17) Bumps [embedded-io-async](https://github.com/rust-embedded/embedded-hal) from 0.6.1 to 0.7.0. - [Release notes](https://github.com/rust-embedded/embedded-hal/releases) - [Commits](https://github.com/rust-embedded/embedded-hal/compare/embedded-io-async-v0.6.1...embedded-io-async-v0.7.0) --- updated-dependencies: - dependency-name: embedded-io-async dependency-version: 0.7.0 dependency-type: direct:production update-type: version-update:semver-minor ... Signed-off-by: dependabot[bot] Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- Cargo.lock | 23 +++++++++++++++++++---- Cargo.toml | 2 +- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index e9f4d3165..adf69dd3d 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -239,8 +239,8 @@ dependencies = [ "embedded-hal 1.0.0", "embedded-hal-async", "embedded-hal-nb", - "embedded-io", - "embedded-io-async", + "embedded-io 0.6.1", + "embedded-io-async 0.7.0", "heapless", "mcxa-pac", "nb 1.1.0", @@ -255,7 +255,7 @@ checksum = "73974a3edbd0bd286759b3d483540f0ebef705919a5f56f4fc7709066f71689b" dependencies = [ "cfg-if", "critical-section", - "embedded-io-async", + "embedded-io-async 0.6.1", "futures-core", "futures-sink", "heapless", @@ -327,13 +327,28 @@ version = "0.6.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d" +[[package]] +name = "embedded-io" +version = "0.7.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9eb1aa714776b75c7e67e1da744b81a129b3ff919c8712b5e1b32252c1f07cc7" + [[package]] name = "embedded-io-async" version = "0.6.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3ff09972d4073aa8c299395be75161d582e7629cd663171d62af73c8d50dba3f" dependencies = [ - "embedded-io", + "embedded-io 0.6.1", +] + +[[package]] +name = "embedded-io-async" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2564b9f813c544241430e147d8bc454815ef9ac998878d30cc3055449f7fd4c0" +dependencies = [ + "embedded-io 0.7.1", ] [[package]] diff --git a/Cargo.toml b/Cargo.toml index 3913104fc..db2bc6934 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -29,7 +29,7 @@ embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [ embedded-hal = { package = "embedded-hal", version = "1.0" } embedded-hal-async = { version = "1.0" } embedded-hal-nb = { version = "1.0" } -embedded-io-async = { version = "0.6.1" } +embedded-io-async = { version = "0.7.0" } nb = "1.1.0" [features] -- cgit From bf3ae8e4d69ef2e2ecfdf0b48734d9c91637eb16 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 17 Nov 2025 16:27:39 -0800 Subject: Let HAL build in isolation (#21) * Revert "chore(deps): bump embedded-io-async from 0.6.1 to 0.7.0 (#17)" This reverts commit 011c3b2de9361496faa0eea75ae19a77f2698f88. * Let HAL build in isolation while at that, also remove bogus dependency on embassy-executor. Signed-off-by: Felipe Balbi * Certify syn 2.0.110 Signed-off-by: Felipe Balbi --------- Signed-off-by: Felipe Balbi --- .cargo/config.toml | 2 + Cargo.lock | 112 +++-------------------------------------------- Cargo.toml | 16 +++---- examples/Cargo.lock | 1 - supply-chain/audits.toml | 5 +++ supply-chain/config.toml | 4 -- 6 files changed, 19 insertions(+), 121 deletions(-) create mode 100644 .cargo/config.toml diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 000000000..55dd5ea5f --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,2 @@ +[build] +target = "thumbv8m.main-none-eabihf" # Cortex-M33 diff --git a/Cargo.lock b/Cargo.lock index adf69dd3d..0fb5bfb12 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -80,41 +80,6 @@ version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b" -[[package]] -name = "darling" -version = "0.20.11" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc7f46116c46ff9ab3eb1597a45688b6715c6e628b5c133e288e709a29bcb4ee" -dependencies = [ - "darling_core", - "darling_macro", -] - -[[package]] -name = "darling_core" -version = "0.20.11" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0d00b9596d185e565c2207a0b01f8bd1a135483d02d9b7b0a54b11da8d53412e" -dependencies = [ - "fnv", - "ident_case", - "proc-macro2", - "quote", - "strsim", - "syn", -] - -[[package]] -name = "darling_macro" -version = "0.20.11" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc34b93ccb385b40dc71c6fceac4b2ad23662c7eeb248cf10d529b7e055b6ead" -dependencies = [ - "darling_core", - "quote", - "syn", -] - [[package]] name = "defmt" version = "1.0.1" @@ -173,37 +138,6 @@ dependencies = [ "nb 1.1.0", ] -[[package]] -name = "embassy-executor" -version = "0.9.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "06070468370195e0e86f241c8e5004356d696590a678d47d6676795b2e439c6b" -dependencies = [ - "cortex-m", - "critical-section", - "document-features", - "embassy-executor-macros", - "embassy-executor-timer-queue", -] - -[[package]] -name = "embassy-executor-macros" -version = "0.7.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dfdddc3a04226828316bf31393b6903ee162238576b1584ee2669af215d55472" -dependencies = [ - "darling", - "proc-macro2", - "quote", - "syn", -] - -[[package]] -name = "embassy-executor-timer-queue" -version = "0.1.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2fc328bf943af66b80b98755db9106bf7e7471b0cf47dc8559cd9a6be504cc9c" - [[package]] name = "embassy-futures" version = "0.1.2" @@ -230,7 +164,6 @@ dependencies = [ "critical-section", "defmt", "embassy-embedded-hal", - "embassy-executor", "embassy-hal-internal", "embassy-sync", "embassy-time", @@ -239,8 +172,8 @@ dependencies = [ "embedded-hal 1.0.0", "embedded-hal-async", "embedded-hal-nb", - "embedded-io 0.6.1", - "embedded-io-async 0.7.0", + "embedded-io", + "embedded-io-async", "heapless", "mcxa-pac", "nb 1.1.0", @@ -255,7 +188,7 @@ checksum = "73974a3edbd0bd286759b3d483540f0ebef705919a5f56f4fc7709066f71689b" dependencies = [ "cfg-if", "critical-section", - "embedded-io-async 0.6.1", + "embedded-io-async", "futures-core", "futures-sink", "heapless", @@ -327,28 +260,13 @@ version = "0.6.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d" -[[package]] -name = "embedded-io" -version = "0.7.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9eb1aa714776b75c7e67e1da744b81a129b3ff919c8712b5e1b32252c1f07cc7" - [[package]] name = "embedded-io-async" version = "0.6.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3ff09972d4073aa8c299395be75161d582e7629cd663171d62af73c8d50dba3f" dependencies = [ - "embedded-io 0.6.1", -] - -[[package]] -name = "embedded-io-async" -version = "0.7.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2564b9f813c544241430e147d8bc454815ef9ac998878d30cc3055449f7fd4c0" -dependencies = [ - "embedded-io 0.7.1", + "embedded-io", ] [[package]] @@ -366,12 +284,6 @@ dependencies = [ "embedded-storage", ] -[[package]] -name = "fnv" -version = "1.0.7" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" - [[package]] name = "futures-core" version = "0.3.31" @@ -403,12 +315,6 @@ dependencies = [ "stable_deref_trait", ] -[[package]] -name = "ident_case" -version = "1.0.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39" - [[package]] name = "litrs" version = "1.0.0" @@ -525,17 +431,11 @@ version = "1.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596" -[[package]] -name = "strsim" -version = "0.11.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" - [[package]] name = "syn" -version = "2.0.109" +version = "2.0.110" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2f17c7e013e88258aa9543dcbe81aca68a667a9ac37cd69c9fbc07858bfe0e2f" +checksum = "a99801b5bd34ede4cf3fc688c5919368fea4e4814a4664359503e6015b280aea" dependencies = [ "proc-macro2", "quote", diff --git a/Cargo.toml b/Cargo.toml index db2bc6934..841ce1903 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,24 +13,20 @@ cortex-m-rt = { version = "0.7", features = ["device"] } critical-section = "1.2.0" defmt = { version = "1.0", optional = true } embassy-embedded-hal = "0.5.0" -embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] } embassy-sync = "0.7.2" embassy-time = "0.5.0" embassy-time-driver = "0.2.1" -embedded-io = "0.6" -heapless = "0.8" -mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "3ab4c868f75a9240bb8fdce24982d34f2273aabf", version = "0.1.0" } -paste = "1.0.15" - -embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [ - "unproven", -] } embedded-hal = { package = "embedded-hal", version = "1.0" } +embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } embedded-hal-async = { version = "1.0" } embedded-hal-nb = { version = "1.0" } -embedded-io-async = { version = "0.7.0" } +embedded-io = "0.6" +embedded-io-async = { version = "0.6.1" } +heapless = "0.8" +mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "3ab4c868f75a9240bb8fdce24982d34f2273aabf", version = "0.1.0" } nb = "1.1.0" +paste = "1.0.15" [features] default = [] diff --git a/examples/Cargo.lock b/examples/Cargo.lock index b774aff97..b2ac9a051 100644 --- a/examples/Cargo.lock +++ b/examples/Cargo.lock @@ -240,7 +240,6 @@ dependencies = [ "critical-section", "defmt", "embassy-embedded-hal", - "embassy-executor", "embassy-hal-internal", "embassy-sync", "embassy-time", diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml index 60ebedf9b..2aba6b961 100644 --- a/supply-chain/audits.toml +++ b/supply-chain/audits.toml @@ -107,6 +107,11 @@ who = "jerrysxie " criteria = "safe-to-run" delta = "2.1.0 -> 2.1.1" +[[audits.syn]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "2.0.110" + [[audits.syn]] who = "Felipe Balbi " criteria = "safe-to-deploy" diff --git a/supply-chain/config.toml b/supply-chain/config.toml index 5927b0b61..36a513ee2 100644 --- a/supply-chain/config.toml +++ b/supply-chain/config.toml @@ -181,10 +181,6 @@ criteria = "safe-to-deploy" version = "2.1.0" criteria = "safe-to-run" -[[exemptions.syn]] -version = "2.0.100" -criteria = "safe-to-deploy" - [[exemptions.typenum]] version = "1.18.0" criteria = "safe-to-deploy" -- cgit From 62e297c130ac26afe4d7d5752bb79709bd370e39 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 17 Nov 2025 16:34:11 -0800 Subject: Allow writing binary to flash (#20) Turns out probe-rs works out of the box. Signed-off-by: Felipe Balbi --- examples/.cargo/config.toml | 2 +- examples/Cargo.toml | 4 ++++ examples/memory.x | 4 ++-- examples/src/bin/blink.rs | 4 ++++ 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/examples/.cargo/config.toml b/examples/.cargo/config.toml index ecb11be64..aedc55b06 100644 --- a/examples/.cargo/config.toml +++ b/examples/.cargo/config.toml @@ -1,5 +1,5 @@ [target.thumbv8m.main-none-eabihf] -runner = 'probe-rs run --chip MCXA276 --preverify --verify' +runner = 'probe-rs run --chip MCXA276 --preverify --verify --protocol swd --speed 12000' rustflags = [ "-C", "linker=flip-link", diff --git a/examples/Cargo.toml b/examples/Cargo.toml index 6b100de42..d03d3d95c 100644 --- a/examples/Cargo.toml +++ b/examples/Cargo.toml @@ -19,3 +19,7 @@ embassy-time-driver = "0.2.1" embedded-io-async = "0.6.1" heapless = "0.9.2" panic-probe = { version = "1.0", features = ["print-defmt"] } + +[profile.release] +lto = true # better optimizations +debug = 2 # enough information for defmt/rtt locations diff --git a/examples/memory.x b/examples/memory.x index f4263a412..315ced58a 100644 --- a/examples/memory.x +++ b/examples/memory.x @@ -1,5 +1,5 @@ MEMORY { - FLASH : ORIGIN = 0x20000000, LENGTH = 64K - RAM : ORIGIN = 0x20010000, LENGTH = 64K + FLASH : ORIGIN = 0x00000000, LENGTH = 1M + RAM : ORIGIN = 0x20000000, LENGTH = 128K } diff --git a/examples/src/bin/blink.rs b/examples/src/bin/blink.rs index d8a57c546..c36fc9421 100644 --- a/examples/src/bin/blink.rs +++ b/examples/src/bin/blink.rs @@ -27,6 +27,8 @@ async fn main(_spawner: Spawner) { init_ostimer0(hal::pac()); } + defmt::info!("Blink example"); + // Initialize embassy-time global driver backed by OSTIMER0 hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); @@ -42,6 +44,8 @@ async fn main(_spawner: Spawner) { // With pauses between letters and words loop { + defmt::info!("SOS"); + // S: three short blinks for _ in 0..3 { led.set_low(); -- cgit From c8942aec2478ff077b55da0e86801f8a6a88a7de Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 17 Nov 2025 16:37:41 -0800 Subject: Prune unnecessary exemptions Signed-off-by: Felipe Balbi --- supply-chain/config.toml | 40 ----- supply-chain/imports.lock | 414 +--------------------------------------------- 2 files changed, 1 insertion(+), 453 deletions(-) diff --git a/supply-chain/config.toml b/supply-chain/config.toml index 36a513ee2..173392c16 100644 --- a/supply-chain/config.toml +++ b/supply-chain/config.toml @@ -13,10 +13,6 @@ url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.to [imports.mozilla] url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" -[[exemptions.az]] -version = "1.2.1" -criteria = "safe-to-deploy" - [[exemptions.bare-metal]] version = "0.2.5" criteria = "safe-to-deploy" @@ -25,14 +21,6 @@ criteria = "safe-to-deploy" version = "0.13.2" criteria = "safe-to-deploy" -[[exemptions.bitfield]] -version = "0.15.0" -criteria = "safe-to-deploy" - -[[exemptions.chrono]] -version = "0.4.40" -criteria = "safe-to-deploy" - [[exemptions.cortex-m]] version = "0.7.7" criteria = "safe-to-deploy" @@ -117,10 +105,6 @@ criteria = "safe-to-deploy" version = "0.4.1" criteria = "safe-to-deploy" -[[exemptions.fixed]] -version = "1.29.0" -criteria = "safe-to-deploy" - [[exemptions.futures-core]] version = "0.3.31" criteria = "safe-to-deploy" @@ -137,26 +121,10 @@ criteria = "safe-to-deploy" version = "0.8.0" criteria = "safe-to-deploy" -[[exemptions.itertools]] -version = "0.11.0" -criteria = "safe-to-deploy" - -[[exemptions.log]] -version = "0.4.27" -criteria = "safe-to-deploy" - -[[exemptions.mimxrt600-fcb]] -version = "0.2.1" -criteria = "safe-to-deploy" - [[exemptions.paste]] version = "1.0.15" criteria = "safe-to-deploy" -[[exemptions.portable-atomic]] -version = "1.11.0" -criteria = "safe-to-run" - [[exemptions.proc-macro-error-attr2]] version = "2.0.0" criteria = "safe-to-deploy" @@ -177,14 +145,6 @@ criteria = "safe-to-deploy" version = "0.7.0" criteria = "safe-to-deploy" -[[exemptions.static_cell]] -version = "2.1.0" -criteria = "safe-to-run" - -[[exemptions.typenum]] -version = "1.18.0" -criteria = "safe-to-deploy" - [[exemptions.vcell]] version = "0.1.3" criteria = "safe-to-deploy" diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock index 3f541e59f..aa62839e2 100644 --- a/supply-chain/imports.lock +++ b/supply-chain/imports.lock @@ -3,13 +3,6 @@ [audits.OpenDevicePartnership.audits] -[[audits.google.audits.autocfg]] -who = "Manish Goregaokar " -criteria = "safe-to-deploy" -version = "1.4.0" -notes = "Contains no unsafe" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - [[audits.google.audits.bitflags]] who = "Lukasz Anforowicz " criteria = "safe-to-deploy" @@ -26,67 +19,6 @@ Additional review comments can be found at https://crrev.com/c/4723145/31 """ aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" -[[audits.google.audits.bytemuck]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.16.3" -notes = """ -Review notes from the original audit (of 1.14.3) may be found in -https://crrev.com/c/5362675. Note that this audit has initially missed UB risk -that was fixed in 1.16.2 - see https://github.com/Lokathor/bytemuck/pull/258. -Because of this, the original audit has been edited to certify version `1.16.3` -instead (see also https://crrev.com/c/5771867). -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.bytemuck]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.16.3 -> 1.17.1" -notes = "Unsafe review comments can be found in https://crrev.com/c/5813463" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.bytemuck]] -who = "Adrian Taylor " -criteria = "safe-to-deploy" -delta = "1.17.1 -> 1.18.0" -notes = "No code changes - just altering feature flag arrangements" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.bytemuck]] -who = "Adrian Taylor " -criteria = "safe-to-deploy" -delta = "1.18.0 -> 1.19.0" -notes = "No code changes - just comment changes and adding the track_caller attribute." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.bytemuck]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.19.0 -> 1.20.0" -notes = "`unsafe` review can be found at https://crrev.com/c/6096767" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.bytemuck]] -who = "Adrian Taylor " -criteria = "safe-to-deploy" -delta = "1.20.0 -> 1.21.0" -notes = "Unsafe review at https://chromium-review.googlesource.com/c/chromium/src/+/6111154/" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.bytemuck]] -who = "Daniel Cheng " -criteria = "safe-to-deploy" -delta = "1.21.0 -> 1.22.0" -notes = """ -This adds new instances of unsafe, but the uses are justified: -- BoxBytes is essentially a Box<[u8], which is Send + Sync, so also marking BoxBytes as Send + Sync is justified. -- core::num::Saturating meets the criteria for Zeroable + Pod, so marking it as such is justified. - -See https://crrev.com/c/6321863 for more audit notes. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - [[audits.google.audits.byteorder]] who = "danakj " criteria = "safe-to-deploy" @@ -94,40 +26,6 @@ version = "1.5.0" notes = "Unsafe review in https://crrev.com/c/5838022" aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" -[[audits.google.audits.cfg-if]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -version = "1.0.0" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.either]] -who = "Manish Goregaokar " -criteria = "safe-to-deploy" -version = "1.13.0" -notes = "Unsafe code pertaining to wrapping Pin APIs. Mostly passes invariants down." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.either]] -who = "Daniel Cheng " -criteria = "safe-to-deploy" -delta = "1.13.0 -> 1.14.0" -notes = """ -Inheriting ub-risk-1 from the baseline review of 1.13.0. While the delta has some diffs in unsafe code, they are either: -- migrating code to use helper macros -- migrating match patterns to take advantage of default bindings mode from RFC 2005 -Either way, the result is code that does exactly the same thing and does not change the risk of UB. - -See https://crrev.com/c/6323164 for more audit details. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.either]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.14.0 -> 1.15.0" -notes = "The delta in `lib.rs` only tweaks doc comments and `#[cfg(feature = \"std\")]`." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - [[audits.google.audits.nb]] who = "George Burgess IV " criteria = "safe-to-deploy" @@ -153,320 +51,10 @@ version = "0.2.19" notes = "Contains a single line of float-to-int unsafe with decent safety comments" aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" -[[audits.google.audits.proc-macro2]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.0.78" -notes = """ -Grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits -(except for a benign \"fs\" hit in a doc comment) - -Notes from the `unsafe` review can be found in https://crrev.com/c/5385745. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Adrian Taylor " -criteria = "safe-to-deploy" -delta = "1.0.78 -> 1.0.79" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Adrian Taylor " -criteria = "safe-to-deploy" -delta = "1.0.79 -> 1.0.80" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Dustin J. Mitchell " -criteria = "safe-to-deploy" -delta = "1.0.80 -> 1.0.81" -notes = "Comment changes only" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "danakj " -criteria = "safe-to-deploy" -delta = "1.0.81 -> 1.0.82" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Dustin J. Mitchell " -criteria = "safe-to-deploy" -delta = "1.0.82 -> 1.0.83" -notes = "Substantive change is replacing String with Box, saving memory." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.0.83 -> 1.0.84" -notes = "Only doc comment changes in `src/lib.rs`." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "danakj@chromium.org" -criteria = "safe-to-deploy" -delta = "1.0.84 -> 1.0.85" -notes = "Test-only changes." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.0.85 -> 1.0.86" -notes = """ -Comment-only changes in `build.rs`. -Reordering of `Cargo.toml` entries. -Just bumping up the version number in `lib.rs`. -Config-related changes in `test_size.rs`. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "danakj " -criteria = "safe-to-deploy" -delta = "1.0.86 -> 1.0.87" -notes = "No new unsafe interactions." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Liza Burakova Date: Tue, 18 Nov 2025 08:28:15 -0800 Subject: Fix rolling workflow (#23) Signed-off-by: Felipe Balbi --- .github/workflows/rolling.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml index 1d93cfe25..a9f0b30b4 100644 --- a/.github/workflows/rolling.yml +++ b/.github/workflows/rolling.yml @@ -33,7 +33,7 @@ jobs: - name: cargo check run: | cargo update - cargo check --all-features check + cargo check --all-features msrv: runs-on: ubuntu-latest @@ -55,4 +55,4 @@ jobs: - name: cargo +${{ matrix.msrv }} check run: | cargo update - cargo check --all-features check + cargo check --all-features -- cgit From ffe3e5acae6c0038db4176dc7d031b57f865e07f Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Tue, 18 Nov 2025 12:16:14 -0800 Subject: Correct gpio driver (#9) * Correct gpio driver Signed-off-by: Felipe Balbi * Simplify blinky example Make it look like every other HAL for consistency. While at that, also rename the example to match the name used by other HALs. Signed-off-by: Felipe Balbi * Add some documentation to GPIO driver Signed-off-by: Felipe Balbi * Enable GPIO clocks during HAL initialization Provide the user with working GPIO clocks. Signed-off-by: Felipe Balbi --------- Signed-off-by: Felipe Balbi Co-authored-by: Felipe Balbi --- Cargo.toml | 2 +- examples/src/bin/adc_interrupt.rs | 6 +- examples/src/bin/adc_polling.rs | 6 +- examples/src/bin/blink.rs | 81 ------ examples/src/bin/blinky.rs | 49 ++++ examples/src/bin/hello.rs | 6 +- examples/src/bin/lpuart_buffered.rs | 4 +- examples/src/bin/lpuart_polling.rs | 6 +- examples/src/bin/ostimer_alarm.rs | 6 +- examples/src/bin/ostimer_async.rs | 6 +- examples/src/bin/ostimer_counter.rs | 6 +- examples/src/bin/ostimer_race_test.rs | 6 +- examples/src/bin/rtc_alarm.rs | 6 +- examples/src/lib.rs | 6 - src/clocks/mod.rs | 7 + src/gpio.rs | 480 +++++++++++++++++++++++++++++----- src/lib.rs | 315 +++++++++++++++++++++- src/lpuart/mod.rs | 14 +- 18 files changed, 827 insertions(+), 185 deletions(-) delete mode 100644 examples/src/bin/blink.rs create mode 100644 examples/src/bin/blinky.rs diff --git a/Cargo.toml b/Cargo.toml index 841ce1903..60f836ac3 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -17,7 +17,7 @@ embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3 embassy-sync = "0.7.2" embassy-time = "0.5.0" embassy-time-driver = "0.2.1" -embedded-hal = { package = "embedded-hal", version = "1.0" } +embedded-hal-1 = { package = "embedded-hal", version = "1.0" } embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } embedded-hal-async = { version = "1.0" } embedded-hal-nb = { version = "1.0" } diff --git a/examples/src/bin/adc_interrupt.rs b/examples/src/bin/adc_interrupt.rs index 6812ba5d3..9fed052fd 100644 --- a/examples/src/bin/adc_interrupt.rs +++ b/examples/src/bin/adc_interrupt.rs @@ -34,14 +34,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/adc_polling.rs b/examples/src/bin/adc_polling.rs index 421306e9b..545f8f77a 100644 --- a/examples/src/bin/adc_polling.rs +++ b/examples/src/bin/adc_polling.rs @@ -34,14 +34,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/blink.rs b/examples/src/bin/blink.rs deleted file mode 100644 index d8b158d50..000000000 --- a/examples/src/bin/blink.rs +++ /dev/null @@ -1,81 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa as hal; -use embassy_mcxa::bind_interrupts; -use embassy_mcxa_examples::init_led_gpio_clocks; -use embassy_time::{Duration, Timer}; -use hal::gpio::pins::PIO3_18; -use hal::gpio::{Level, Output}; - -// Bind only OS_EVENT for timer interrupts -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let _p = hal::init(hal::config::Config::default()); - - unsafe { - init_led_gpio_clocks(hal::pac()); - } - - defmt::info!("Blink example"); - - // Initialize embassy-time global driver backed by OSTIMER0 - hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); - - // Configure LED pin for GPIO mode - PIO3_18::set_mux_gpio(); - - let mut led = Output::new(PIO3_18::degrade(), Level::High); - - // Complex blinking pattern: SOS in Morse code - // S: ... (3 short) - // O: --- (3 long) - // S: ... (3 short) - // With pauses between letters and words - - loop { - defmt::info!("SOS"); - - // S: three short blinks - for _ in 0..3 { - led.set_low(); - Timer::after(Duration::from_millis(150)).await; - led.set_high(); - Timer::after(Duration::from_millis(150)).await; - } - - // Pause between letters - Timer::after(Duration::from_millis(300)).await; - - // O: three long blinks - for _ in 0..3 { - led.set_low(); - Timer::after(Duration::from_millis(450)).await; - led.set_high(); - Timer::after(Duration::from_millis(150)).await; - } - - // Pause between letters - Timer::after(Duration::from_millis(300)).await; - - // S: three short blinks - for _ in 0..3 { - led.set_low(); - Timer::after(Duration::from_millis(150)).await; - led.set_high(); - Timer::after(Duration::from_millis(150)).await; - } - - // Long pause between words (SOS repeats) - Timer::after(Duration::from_millis(1000)).await; - } -} diff --git a/examples/src/bin/blinky.rs b/examples/src/bin/blinky.rs new file mode 100644 index 000000000..28d83a12e --- /dev/null +++ b/examples/src/bin/blinky.rs @@ -0,0 +1,49 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::bind_interrupts; +use embassy_time::Timer; +use hal::gpio::{Level, Output}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +// Bind only OS_EVENT for timer interrupts +bind_interrupts!(struct Irqs { + OS_EVENT => hal::ostimer::time_driver::OsEventHandler; +}); + +#[used] +#[no_mangle] +static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("Blink example"); + + // Initialize embassy-time global driver backed by OSTIMER0 + hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); + + let mut red = Output::new(p.P3_18, Level::High); + let mut green = Output::new(p.P3_19, Level::High); + let mut blue = Output::new(p.P3_21, Level::High); + + loop { + defmt::info!("Toggle LEDs"); + + red.toggle(); + Timer::after_millis(250).await; + + red.toggle(); + green.toggle(); + Timer::after_millis(250).await; + + green.toggle(); + blue.toggle(); + Timer::after_millis(250).await; + blue.toggle(); + + Timer::after_millis(250).await; + } +} diff --git a/examples/src/bin/hello.rs b/examples/src/bin/hello.rs index 207c157c3..e2d0b413d 100644 --- a/examples/src/bin/hello.rs +++ b/examples/src/bin/hello.rs @@ -26,14 +26,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/lpuart_buffered.rs b/examples/src/bin/lpuart_buffered.rs index 642d4af65..b0d19ef16 100644 --- a/examples/src/bin/lpuart_buffered.rs +++ b/examples/src/bin/lpuart_buffered.rs @@ -51,8 +51,8 @@ async fn main(_spawner: Spawner) { // Create a buffered LPUART2 instance with both TX and RX let mut uart = BufferedLpuart::new( p.LPUART2, - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin Irqs, &mut tx_buf, &mut rx_buf, diff --git a/examples/src/bin/lpuart_polling.rs b/examples/src/bin/lpuart_polling.rs index bea82c33e..525d42e2c 100644 --- a/examples/src/bin/lpuart_polling.rs +++ b/examples/src/bin/lpuart_polling.rs @@ -26,11 +26,11 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX let lpuart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/ostimer_alarm.rs b/examples/src/bin/ostimer_alarm.rs index 03fb93319..6d38741b7 100644 --- a/examples/src/bin/ostimer_alarm.rs +++ b/examples/src/bin/ostimer_alarm.rs @@ -40,14 +40,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/ostimer_async.rs b/examples/src/bin/ostimer_async.rs index 881f09374..f043184e7 100644 --- a/examples/src/bin/ostimer_async.rs +++ b/examples/src/bin/ostimer_async.rs @@ -29,14 +29,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/ostimer_counter.rs b/examples/src/bin/ostimer_counter.rs index 2fbc251b9..f36915ff2 100644 --- a/examples/src/bin/ostimer_counter.rs +++ b/examples/src/bin/ostimer_counter.rs @@ -30,14 +30,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/ostimer_race_test.rs b/examples/src/bin/ostimer_race_test.rs index 168a952cd..0106b92a7 100644 --- a/examples/src/bin/ostimer_race_test.rs +++ b/examples/src/bin/ostimer_race_test.rs @@ -80,14 +80,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/bin/rtc_alarm.rs b/examples/src/bin/rtc_alarm.rs index 40a1207df..a54b4a817 100644 --- a/examples/src/bin/rtc_alarm.rs +++ b/examples/src/bin/rtc_alarm.rs @@ -32,14 +32,14 @@ async fn main(_spawner: Spawner) { ..Default::default() }; - // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { embassy_mcxa_examples::init_uart2_pins(hal::pac()); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral - p.PIO2_2, // TX pin - p.PIO2_3, // RX pin + p.P2_2, // TX pin + p.P2_3, // RX pin config, ) .unwrap(); diff --git a/examples/src/lib.rs b/examples/src/lib.rs index 4bb334da5..66b93450a 100644 --- a/examples/src/lib.rs +++ b/examples/src/lib.rs @@ -16,12 +16,6 @@ pub unsafe fn init_uart2_pins(_p: &hal::pac::Peripherals) { pins::configure_uart2_pins_port2(); } -/// Initialize clocks for the LED GPIO/PORT used by the blink example. -pub unsafe fn init_led_gpio_clocks(_p: &hal::pac::Peripherals) { - _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); - _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); -} - /// Initialize clocks and pin muxing for ADC. pub unsafe fn init_adc_pins(_p: &hal::pac::Peripherals) { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index e02840592..558fb0278 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -874,10 +874,17 @@ pub(crate) mod gate { // other than enabling through the MRCC gate. Currently, these peripherals will // ALWAYS return `Ok(0)` when calling [`enable_and_reset()`] and/or // [`SPConfHelper::post_enable_config()`]. + impl_cc_gate!(PORT0, mrcc_glb_cc1, mrcc_glb_rst1, port0, NoConfig); impl_cc_gate!(PORT1, mrcc_glb_cc1, mrcc_glb_rst1, port1, NoConfig); impl_cc_gate!(PORT2, mrcc_glb_cc1, mrcc_glb_rst1, port2, NoConfig); impl_cc_gate!(PORT3, mrcc_glb_cc1, mrcc_glb_rst1, port3, NoConfig); + impl_cc_gate!(PORT4, mrcc_glb_cc1, mrcc_glb_rst1, port4, NoConfig); + + impl_cc_gate!(GPIO0, mrcc_glb_cc2, mrcc_glb_rst2, gpio0, NoConfig); + impl_cc_gate!(GPIO1, mrcc_glb_cc2, mrcc_glb_rst2, gpio1, NoConfig); + impl_cc_gate!(GPIO2, mrcc_glb_cc2, mrcc_glb_rst2, gpio2, NoConfig); impl_cc_gate!(GPIO3, mrcc_glb_cc2, mrcc_glb_rst2, gpio3, NoConfig); + impl_cc_gate!(GPIO4, mrcc_glb_cc2, mrcc_glb_rst2, gpio4, NoConfig); // These peripherals DO have meaningful configuration, and could fail if the system // clocks do not match their needs. diff --git a/src/gpio.rs b/src/gpio.rs index 1e7214b28..09a414d3b 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -2,9 +2,11 @@ //! The exported `Output`/`Input` drivers own a `Flex` so they no longer depend on the //! concrete pin type. +use core::convert::Infallible; use core::marker::PhantomData; -use crate::{pac, pins as pin_config}; +use embassy_hal_internal::{Peri, PeripheralType}; +use paste::paste; /// Logical level for GPIO pins. #[derive(Copy, Clone, Eq, PartialEq, Debug)] @@ -13,140 +15,350 @@ pub enum Level { High, } -pub type Gpio = crate::peripherals::GPIO; +pub type Gpio = crate::peripherals::GPIO0; /// Type-erased representation of a GPIO pin. -#[derive(Copy, Clone)] pub struct AnyPin { - port: u8, - pin: u8, - gpio: *const pac::gpio0::RegisterBlock, + port: usize, + pin: usize, + gpio: &'static crate::pac::gpio0::RegisterBlock, } impl AnyPin { /// Create an `AnyPin` from raw components. - pub fn new(port: u8, pin: u8, gpio: *const pac::gpio0::RegisterBlock) -> Self { + pub fn new(port: usize, pin: usize, gpio: &'static crate::pac::gpio0::RegisterBlock) -> Self { Self { port, pin, gpio } } #[inline(always)] fn mask(&self) -> u32 { - 1u32 << self.pin + 1 << self.pin } #[inline(always)] - fn gpio(&self) -> &'static pac::gpio0::RegisterBlock { - unsafe { &*self.gpio } + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + self.gpio } #[inline(always)] - pub fn port_index(&self) -> u8 { + pub fn port_index(&self) -> usize { self.port } #[inline(always)] - pub fn pin_index(&self) -> u8 { + pub fn pin_index(&self) -> usize { self.pin } } -/// Type-level trait implemented by concrete pin ZSTs. -pub trait PinId { - fn port_index() -> u8; - fn pin_index() -> u8; - fn gpio_ptr() -> *const pac::gpio0::RegisterBlock; +embassy_hal_internal::impl_peripheral!(AnyPin); - fn set_mux_gpio() { - unsafe { pin_config::set_pin_mux_gpio(Self::port_index(), Self::pin_index()) } +trait SealedPin { + fn pin_port(&self) -> usize; + + fn port(&self) -> usize { + self.pin_port() / 32 } - fn degrade() -> AnyPin { - AnyPin::new(Self::port_index(), Self::pin_index(), Self::gpio_ptr()) + fn pin(&self) -> usize { + self.pin_port() % 32 } + + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock; } -pub mod pins { - use super::{pac, AnyPin, PinId}; +/// GPIO pin trait. +#[allow(private_bounds)] +pub trait GpioPin: SealedPin + Sized + PeripheralType + Into + 'static { + /// Type-erase the pin. + fn degrade(self) -> AnyPin { + // SAFETY: This is only called within the GpioPin trait, which is only + // implemented within this module on valid pin peripherals and thus + // has been verified to be correct. + AnyPin::new(self.port(), self.pin(), self.gpio()) + } +} - macro_rules! define_pin { - ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => { - pub struct $Name; - impl super::PinId for $Name { - #[inline(always)] - fn port_index() -> u8 { - $port - } - #[inline(always)] - fn pin_index() -> u8 { - $pin - } - #[inline(always)] - fn gpio_ptr() -> *const pac::gpio0::RegisterBlock { - pac::$GpioBlk::ptr() - } +impl SealedPin for AnyPin { + #[inline] + fn pin_port(&self) -> usize { + self.port * 32 + self.pin + } + + #[inline] + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + self.gpio() + } +} + +impl GpioPin for AnyPin {} + +macro_rules! impl_pin { + ($peri:ident, $port:expr, $pin:expr, $block:ident) => { + impl SealedPin for crate::peripherals::$peri { + #[inline] + fn pin_port(&self) -> usize { + $port * 32 + $pin } - impl $Name { - /// Convenience helper to obtain a type-erased handle to this pin. - pub fn degrade() -> AnyPin { - ::degrade() - } + #[inline] + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + unsafe { &*crate::pac::$block::ptr() } + } + } - pub fn set_mux_gpio() { - ::set_mux_gpio() - } + impl GpioPin for crate::peripherals::$peri {} + + impl From for AnyPin { + fn from(value: crate::peripherals::$peri) -> Self { + value.degrade() } - }; - } + } - // Extend this list as more pins are needed. - define_pin!(PIO3_18, 3, 18, Gpio3); + impl crate::peripherals::$peri { + /// Convenience helper to obtain a type-erased handle to this pin. + pub fn degrade(&self) -> AnyPin { + AnyPin::new(self.port(), self.pin(), self.gpio()) + } + + #[inline] + pub fn set_mux_gpio() { + paste! { + let port = unsafe { crate::pac::[]::steal()}; + port.[]().write(|w| w.mux().mux00()); + } + } + } + }; } +impl_pin!(P0_0, 0, 0, Gpio0); +impl_pin!(P0_1, 0, 1, Gpio0); +impl_pin!(P0_2, 0, 2, Gpio0); +impl_pin!(P0_3, 0, 3, Gpio0); +impl_pin!(P0_4, 0, 4, Gpio0); +impl_pin!(P0_5, 0, 5, Gpio0); +impl_pin!(P0_6, 0, 6, Gpio0); +impl_pin!(P0_7, 0, 7, Gpio0); +impl_pin!(P0_8, 0, 8, Gpio0); +impl_pin!(P0_9, 0, 9, Gpio0); +impl_pin!(P0_10, 0, 10, Gpio0); +impl_pin!(P0_11, 0, 11, Gpio0); +impl_pin!(P0_12, 0, 12, Gpio0); +impl_pin!(P0_13, 0, 13, Gpio0); +impl_pin!(P0_14, 0, 14, Gpio0); +impl_pin!(P0_15, 0, 15, Gpio0); +impl_pin!(P0_16, 0, 16, Gpio0); +impl_pin!(P0_17, 0, 17, Gpio0); +impl_pin!(P0_18, 0, 18, Gpio0); +impl_pin!(P0_19, 0, 19, Gpio0); +impl_pin!(P0_20, 0, 20, Gpio0); +impl_pin!(P0_21, 0, 21, Gpio0); +impl_pin!(P0_22, 0, 22, Gpio0); +impl_pin!(P0_23, 0, 23, Gpio0); +impl_pin!(P0_24, 0, 24, Gpio0); +impl_pin!(P0_25, 0, 25, Gpio0); +impl_pin!(P0_26, 0, 26, Gpio0); +impl_pin!(P0_27, 0, 27, Gpio0); +impl_pin!(P0_28, 0, 28, Gpio0); +impl_pin!(P0_29, 0, 29, Gpio0); +impl_pin!(P0_30, 0, 30, Gpio0); +impl_pin!(P0_31, 0, 31, Gpio0); + +impl_pin!(P1_0, 1, 0, Gpio1); +impl_pin!(P1_1, 1, 1, Gpio1); +impl_pin!(P1_2, 1, 2, Gpio1); +impl_pin!(P1_3, 1, 3, Gpio1); +impl_pin!(P1_4, 1, 4, Gpio1); +impl_pin!(P1_5, 1, 5, Gpio1); +impl_pin!(P1_6, 1, 6, Gpio1); +impl_pin!(P1_7, 1, 7, Gpio1); +impl_pin!(P1_8, 1, 8, Gpio1); +impl_pin!(P1_9, 1, 9, Gpio1); +impl_pin!(P1_10, 1, 10, Gpio1); +impl_pin!(P1_11, 1, 11, Gpio1); +impl_pin!(P1_12, 1, 12, Gpio1); +impl_pin!(P1_13, 1, 13, Gpio1); +impl_pin!(P1_14, 1, 14, Gpio1); +impl_pin!(P1_15, 1, 15, Gpio1); +impl_pin!(P1_16, 1, 16, Gpio1); +impl_pin!(P1_17, 1, 17, Gpio1); +impl_pin!(P1_18, 1, 18, Gpio1); +impl_pin!(P1_19, 1, 19, Gpio1); +impl_pin!(P1_20, 1, 20, Gpio1); +impl_pin!(P1_21, 1, 21, Gpio1); +impl_pin!(P1_22, 1, 22, Gpio1); +impl_pin!(P1_23, 1, 23, Gpio1); +impl_pin!(P1_24, 1, 24, Gpio1); +impl_pin!(P1_25, 1, 25, Gpio1); +impl_pin!(P1_26, 1, 26, Gpio1); +impl_pin!(P1_27, 1, 27, Gpio1); +impl_pin!(P1_28, 1, 28, Gpio1); +impl_pin!(P1_29, 1, 29, Gpio1); +impl_pin!(P1_30, 1, 30, Gpio1); +impl_pin!(P1_31, 1, 31, Gpio1); + +impl_pin!(P2_0, 2, 0, Gpio2); +impl_pin!(P2_1, 2, 1, Gpio2); +impl_pin!(P2_2, 2, 2, Gpio2); +impl_pin!(P2_3, 2, 3, Gpio2); +impl_pin!(P2_4, 2, 4, Gpio2); +impl_pin!(P2_5, 2, 5, Gpio2); +impl_pin!(P2_6, 2, 6, Gpio2); +impl_pin!(P2_7, 2, 7, Gpio2); +impl_pin!(P2_8, 2, 8, Gpio2); +impl_pin!(P2_9, 2, 9, Gpio2); +impl_pin!(P2_10, 2, 10, Gpio2); +impl_pin!(P2_11, 2, 11, Gpio2); +impl_pin!(P2_12, 2, 12, Gpio2); +impl_pin!(P2_13, 2, 13, Gpio2); +impl_pin!(P2_14, 2, 14, Gpio2); +impl_pin!(P2_15, 2, 15, Gpio2); +impl_pin!(P2_16, 2, 16, Gpio2); +impl_pin!(P2_17, 2, 17, Gpio2); +impl_pin!(P2_18, 2, 18, Gpio2); +impl_pin!(P2_19, 2, 19, Gpio2); +impl_pin!(P2_20, 2, 20, Gpio2); +impl_pin!(P2_21, 2, 21, Gpio2); +impl_pin!(P2_22, 2, 22, Gpio2); +impl_pin!(P2_23, 2, 23, Gpio2); +impl_pin!(P2_24, 2, 24, Gpio2); +impl_pin!(P2_25, 2, 25, Gpio2); +impl_pin!(P2_26, 2, 26, Gpio2); +impl_pin!(P2_27, 2, 27, Gpio2); +impl_pin!(P2_28, 2, 28, Gpio2); +impl_pin!(P2_29, 2, 29, Gpio2); +impl_pin!(P2_30, 2, 30, Gpio2); +impl_pin!(P2_31, 2, 31, Gpio2); + +impl_pin!(P3_0, 3, 0, Gpio3); +impl_pin!(P3_1, 3, 1, Gpio3); +impl_pin!(P3_2, 3, 2, Gpio3); +impl_pin!(P3_3, 3, 3, Gpio3); +impl_pin!(P3_4, 3, 4, Gpio3); +impl_pin!(P3_5, 3, 5, Gpio3); +impl_pin!(P3_6, 3, 6, Gpio3); +impl_pin!(P3_7, 3, 7, Gpio3); +impl_pin!(P3_8, 3, 8, Gpio3); +impl_pin!(P3_9, 3, 9, Gpio3); +impl_pin!(P3_10, 3, 10, Gpio3); +impl_pin!(P3_11, 3, 11, Gpio3); +impl_pin!(P3_12, 3, 12, Gpio3); +impl_pin!(P3_13, 3, 13, Gpio3); +impl_pin!(P3_14, 3, 14, Gpio3); +impl_pin!(P3_15, 3, 15, Gpio3); +impl_pin!(P3_16, 3, 16, Gpio3); +impl_pin!(P3_17, 3, 17, Gpio3); +impl_pin!(P3_18, 3, 18, Gpio3); +impl_pin!(P3_19, 3, 19, Gpio3); +impl_pin!(P3_20, 3, 20, Gpio3); +impl_pin!(P3_21, 3, 21, Gpio3); +impl_pin!(P3_22, 3, 22, Gpio3); +impl_pin!(P3_23, 3, 23, Gpio3); +impl_pin!(P3_24, 3, 24, Gpio3); +impl_pin!(P3_25, 3, 25, Gpio3); +impl_pin!(P3_26, 3, 26, Gpio3); +impl_pin!(P3_27, 3, 27, Gpio3); +impl_pin!(P3_28, 3, 28, Gpio3); +impl_pin!(P3_29, 3, 29, Gpio3); +impl_pin!(P3_30, 3, 30, Gpio3); +impl_pin!(P3_31, 3, 31, Gpio3); + +impl_pin!(P4_0, 4, 0, Gpio4); +impl_pin!(P4_1, 4, 1, Gpio4); +impl_pin!(P4_2, 4, 2, Gpio4); +impl_pin!(P4_3, 4, 3, Gpio4); +impl_pin!(P4_4, 4, 4, Gpio4); +impl_pin!(P4_5, 4, 5, Gpio4); +impl_pin!(P4_6, 4, 6, Gpio4); +impl_pin!(P4_7, 4, 7, Gpio4); +impl_pin!(P4_8, 4, 8, Gpio4); +impl_pin!(P4_9, 4, 9, Gpio4); +impl_pin!(P4_10, 4, 10, Gpio4); +impl_pin!(P4_11, 4, 11, Gpio4); +impl_pin!(P4_12, 4, 12, Gpio4); +impl_pin!(P4_13, 4, 13, Gpio4); +impl_pin!(P4_14, 4, 14, Gpio4); +impl_pin!(P4_15, 4, 15, Gpio4); +impl_pin!(P4_16, 4, 16, Gpio4); +impl_pin!(P4_17, 4, 17, Gpio4); +impl_pin!(P4_18, 4, 18, Gpio4); +impl_pin!(P4_19, 4, 19, Gpio4); +impl_pin!(P4_20, 4, 20, Gpio4); +impl_pin!(P4_21, 4, 21, Gpio4); +impl_pin!(P4_22, 4, 22, Gpio4); +impl_pin!(P4_23, 4, 23, Gpio4); +impl_pin!(P4_24, 4, 24, Gpio4); +impl_pin!(P4_25, 4, 25, Gpio4); +impl_pin!(P4_26, 4, 26, Gpio4); +impl_pin!(P4_27, 4, 27, Gpio4); +impl_pin!(P4_28, 4, 28, Gpio4); +impl_pin!(P4_29, 4, 29, Gpio4); +impl_pin!(P4_30, 4, 30, Gpio4); +impl_pin!(P4_31, 4, 31, Gpio4); + /// A flexible pin that can be configured as input or output. pub struct Flex<'d> { - pin: AnyPin, + pin: Peri<'d, AnyPin>, _marker: PhantomData<&'d mut ()>, } impl<'d> Flex<'d> { - pub fn new(pin: AnyPin) -> Self { + /// Wrap the pin in a `Flex`. + /// + /// The pin remains unmodified. The initial output level is unspecified, but + /// can be changed before the pin is put into output mode. + pub fn new(pin: Peri<'d, impl GpioPin>) -> Self { Self { - pin, + pin: pin.into(), _marker: PhantomData, } } - #[inline(always)] - fn gpio(&self) -> &'static pac::gpio0::RegisterBlock { + #[inline] + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { self.pin.gpio() } - #[inline(always)] + #[inline] fn mask(&self) -> u32 { self.pin.mask() } + /// Put the pin into input mode. + /// + /// The pull setting is left unchanged. + #[inline] pub fn set_as_input(&mut self) { let mask = self.mask(); let gpio = self.gpio(); gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); } + /// Put the pin into output mode. + /// + /// The initial output level is left unchanged. + #[inline] pub fn set_as_output(&mut self) { let mask = self.mask(); let gpio = self.gpio(); gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); } + /// Set output level to High. + #[inline] pub fn set_high(&mut self) { self.gpio().psor().write(|w| unsafe { w.bits(self.mask()) }); } + /// Set output level to Low. + #[inline] pub fn set_low(&mut self) { self.gpio().pcor().write(|w| unsafe { w.bits(self.mask()) }); } + /// Set output level to the given `Level`. + #[inline] pub fn set_level(&mut self, level: Level) { match level { Level::High => self.set_high(), @@ -154,17 +366,35 @@ impl<'d> Flex<'d> { } } + /// Toggle output level. + #[inline] pub fn toggle(&mut self) { self.gpio().ptor().write(|w| unsafe { w.bits(self.mask()) }); } + /// Get whether the pin input level is high. + #[inline] pub fn is_high(&self) -> bool { (self.gpio().pdir().read().bits() & self.mask()) != 0 } + /// Get whether the pin input level is low. + #[inline] pub fn is_low(&self) -> bool { !self.is_high() } + + /// Is the output pin set as high? + #[inline] + pub fn is_set_high(&self) -> bool { + self.is_high() + } + + /// Is the output pin set as low? + #[inline] + pub fn is_set_low(&self) -> bool { + !self.is_set_high() + } } /// GPIO output driver that owns a `Flex` pin. @@ -173,44 +403,52 @@ pub struct Output<'d> { } impl<'d> Output<'d> { - pub fn new(pin: AnyPin, initial: Level) -> Self { + /// Create a GPIO output driver for a [GpioPin] with the provided [Level]. + pub fn new(pin: Peri<'d, impl GpioPin>, initial: Level) -> Self { let mut flex = Flex::new(pin); flex.set_level(initial); flex.set_as_output(); Self { flex } } + /// Set the output as high. #[inline] pub fn set_high(&mut self) { self.flex.set_high(); } + /// Set the output as low. #[inline] pub fn set_low(&mut self) { self.flex.set_low(); } + /// Set the output level. #[inline] pub fn set_level(&mut self, level: Level) { self.flex.set_level(level); } + /// Toggle the output level. #[inline] pub fn toggle(&mut self) { self.flex.toggle(); } + /// Is the output pin set as high? #[inline] pub fn is_set_high(&self) -> bool { self.flex.is_high() } + /// Is the output pin set as low? #[inline] pub fn is_set_low(&self) -> bool { !self.is_set_high() } /// Expose the inner `Flex` if callers need to reconfigure the pin. + #[inline] pub fn into_flex(self) -> Flex<'d> { self.flex } @@ -222,23 +460,147 @@ pub struct Input<'d> { } impl<'d> Input<'d> { - pub fn new(pin: AnyPin) -> Self { + /// Create a GPIO input driver for a [GpioPin]. + pub fn new(pin: Peri<'d, impl GpioPin>) -> Self { let mut flex = Flex::new(pin); flex.set_as_input(); Self { flex } } + /// Get whether the pin input level is high. #[inline] pub fn is_high(&self) -> bool { self.flex.is_high() } + /// Get whether the pin input level is low. #[inline] pub fn is_low(&self) -> bool { self.flex.is_low() } + /// Expose the inner `Flex` if callers need to reconfigure the pin. + #[inline] pub fn into_flex(self) -> Flex<'d> { self.flex } } + +// Both embedded_hal 0.2 and 1.0 must be supported by embassy HALs. +impl embedded_hal_02::digital::v2::InputPin for Flex<'_> { + // GPIO operations on this block cannot fail, therefor we set the error type + // to Infallible to guarantee that we can only produce Ok variants. + type Error = Infallible; + + #[inline] + fn is_high(&self) -> Result { + Ok(self.is_high()) + } + + #[inline] + fn is_low(&self) -> Result { + Ok(self.is_low()) + } +} + +impl embedded_hal_02::digital::v2::InputPin for Input<'_> { + type Error = Infallible; + + #[inline] + fn is_high(&self) -> Result { + Ok(self.is_high()) + } + + #[inline] + fn is_low(&self) -> Result { + Ok(self.is_low()) + } +} + +impl embedded_hal_02::digital::v2::OutputPin for Flex<'_> { + type Error = Infallible; + + #[inline] + fn set_high(&mut self) -> Result<(), Self::Error> { + self.set_high(); + Ok(()) + } + + #[inline] + fn set_low(&mut self) -> Result<(), Self::Error> { + self.set_low(); + Ok(()) + } +} + +impl embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'_> { + #[inline] + fn is_set_high(&self) -> Result { + Ok(self.is_set_high()) + } + + #[inline] + fn is_set_low(&self) -> Result { + Ok(self.is_set_low()) + } +} + +impl embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'_> { + type Error = Infallible; + + #[inline] + fn toggle(&mut self) -> Result<(), Self::Error> { + self.toggle(); + Ok(()) + } +} + +impl embedded_hal_1::digital::ErrorType for Flex<'_> { + type Error = Infallible; +} + +impl embedded_hal_1::digital::ErrorType for Input<'_> { + type Error = Infallible; +} + +impl embedded_hal_1::digital::ErrorType for Output<'_> { + type Error = Infallible; +} + +impl embedded_hal_1::digital::InputPin for Input<'_> { + #[inline] + fn is_high(&mut self) -> Result { + Ok((*self).is_high()) + } + + #[inline] + fn is_low(&mut self) -> Result { + Ok((*self).is_low()) + } +} + +impl embedded_hal_1::digital::OutputPin for Flex<'_> { + #[inline] + fn set_high(&mut self) -> Result<(), Self::Error> { + self.set_high(); + Ok(()) + } + + #[inline] + fn set_low(&mut self) -> Result<(), Self::Error> { + self.set_low(); + Ok(()) + } +} + +impl embedded_hal_1::digital::StatefulOutputPin for Flex<'_> { + #[inline] + fn is_set_high(&mut self) -> Result { + Ok((*self).is_set_high()) + } + + #[inline] + fn is_set_low(&mut self) -> Result { + Ok((*self).is_set_low()) + } +} diff --git a/src/lib.rs b/src/lib.rs index 86c0dc45b..c885ecc50 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -14,7 +14,301 @@ pub mod lpuart; pub mod ostimer; pub mod rtc; -embassy_hal_internal::peripherals!(PORT1, PORT2, PORT3, LPUART2, OSTIMER0, GPIO, PIO2_2, PIO2_3, GPIO3, RTC0, ADC1,); +#[rustfmt::skip] +embassy_hal_internal::peripherals!( + ADC0, + ADC1, + + AOI0, + AOI1, + + CAN0, + CAN1, + + CDOG0, + CDOG1, + + CMC, + CMP0, + CMP1, + CRC0, + + CTIMER0, + CTIMER1, + CTIMER2, + CTIMER3, + CTIMER4, + + DBGMAILBOX, + DMA0, + EDMA0_TCD0, + EIM0, + EQDC0, + EQDC1, + ERM0, + FLEXIO0, + FLEXPWM0, + FLEXPWM1, + FMC0, + FMU0, + FREQME0, + GLIKEY0, + + GPIO0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + + I3C0, + INPUTMUX0, + + LPI2C0, + LPI2C1, + LPI2C2, + LPI2C3, + + LPSPI0, + LPSPI1, + + LPTMR0, + + LPUART0, + LPUART1, + LPUART2, + LPUART3, + LPUART4, + + MAU0, + MBC0, + MRCC0, + OPAMP0, + OSTIMER0, + + P0_0, + P0_1, + P0_2, + P0_3, + P0_4, + P0_5, + P0_6, + P0_7, + P0_8, + P0_9, + P0_10, + P0_11, + P0_12, + P0_13, + P0_14, + P0_15, + P0_16, + P0_17, + P0_18, + P0_19, + P0_20, + P0_21, + P0_22, + P0_23, + P0_24, + P0_25, + P0_26, + P0_27, + P0_28, + P0_29, + P0_30, + P0_31, + + P1_0, + P1_1, + P1_2, + P1_3, + P1_4, + P1_5, + P1_6, + P1_7, + P1_8, + P1_9, + P1_10, + P1_11, + P1_12, + P1_13, + P1_14, + P1_15, + P1_16, + P1_17, + P1_18, + P1_19, + P1_20, + P1_21, + P1_22, + P1_23, + P1_24, + P1_25, + P1_26, + P1_27, + P1_28, + P1_29, + P1_30, + P1_31, + + P2_0, + P2_1, + P2_2, + P2_3, + P2_4, + P2_5, + P2_6, + P2_7, + P2_8, + P2_9, + P2_10, + P2_11, + P2_12, + P2_13, + P2_14, + P2_15, + P2_16, + P2_17, + P2_18, + P2_19, + P2_20, + P2_21, + P2_22, + P2_23, + P2_24, + P2_25, + P2_26, + P2_27, + P2_28, + P2_29, + P2_30, + P2_31, + + P3_0, + P3_1, + P3_2, + P3_3, + P3_4, + P3_5, + P3_6, + P3_7, + P3_8, + P3_9, + P3_10, + P3_11, + P3_12, + P3_13, + P3_14, + P3_15, + P3_16, + P3_17, + P3_18, + P3_19, + P3_20, + P3_21, + P3_22, + P3_23, + P3_24, + P3_25, + P3_26, + P3_27, + P3_28, + P3_29, + P3_30, + P3_31, + + P4_0, + P4_1, + P4_2, + P4_3, + P4_4, + P4_5, + P4_6, + P4_7, + P4_8, + P4_9, + P4_10, + P4_11, + P4_12, + P4_13, + P4_14, + P4_15, + P4_16, + P4_17, + P4_18, + P4_19, + P4_20, + P4_21, + P4_22, + P4_23, + P4_24, + P4_25, + P4_26, + P4_27, + P4_28, + P4_29, + P4_30, + P4_31, + + P5_0, + P5_1, + P5_2, + P5_3, + P5_4, + P5_5, + P5_6, + P5_7, + P5_8, + P5_9, + P5_10, + P5_11, + P5_12, + P5_13, + P5_14, + P5_15, + P5_16, + P5_17, + P5_18, + P5_19, + P5_20, + P5_21, + P5_22, + P5_23, + P5_24, + P5_25, + P5_26, + P5_27, + P5_28, + P5_29, + P5_30, + P5_31, + + PKC0, + + PORT0, + PORT1, + PORT2, + PORT3, + PORT4, + + RTC0, + SAU, + SCG0, + SCN_SCB, + SGI0, + SMARTDMA0, + SPC0, + SYSCON, + TDET0, + TRNG0, + UDF0, + USB0, + UTICK0, + VBAT0, + WAKETIMER0, + WUU0, + WWDT0, +); /// Get access to the PAC Peripherals for low-level register access. /// This is a lazy-initialized singleton that can be called after init(). @@ -35,7 +329,6 @@ pub fn pac() -> &'static pac::Peripherals { // Re-export interrupt traits and types pub use adc::Adc1 as Adc1Token; -pub use gpio::pins::*; pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output}; pub use interrupt::InterruptExt; #[cfg(feature = "unstable-pac")] @@ -59,6 +352,24 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { // Configure clocks crate::clocks::init(cfg.clock_cfg).unwrap(); + // Enable GPIO clocks + unsafe { + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + } + peripherals } diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index b3d7c4885..f069f6567 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -53,7 +53,7 @@ mod gpio { } // Implement GpioPin for all pins from lib.rs - impl_gpio_pin!(PIO2_2, PIO2_3); + impl_gpio_pin!(P2_2, P2_3); #[derive(Debug, Clone, Copy)] pub struct AnyPin; @@ -433,12 +433,12 @@ macro_rules! impl_pin_trait { } // Document identifier: MCXA343/344 Rev. 1DraftB ReleaseCandidate, 2025-07-10 - 6.1 MCX A173, A174 Signal Multiplexing and Pin Assignments -// impl_pin_trait!(LPUART0, rx, PIO2_0, ALT2, PIO0_2, ALT2, PIO0_20, ALT3); -// impl_pin_trait!(LPUART0, tx, PIO2_1, ALT2, PIO0_3, ALT2, PIO0_21, ALT3); -// impl_pin_trait!(LPUART0, rts, PIO2_2, ALT2, PIO0_0, ALT2, PIO0_22, ALT3); -// impl_pin_trait!(LPUART0, cts, PIO2_3, ALT2, PIO0_1, ALT2, PIO0_23, ALT3); -impl_pin_trait!(LPUART2, rx, PIO2_3, ALT3); -impl_pin_trait!(LPUART2, tx, PIO2_2, ALT3); +// impl_pin_trait!(LPUART0, rx, P2_0, ALT2, P0_2, ALT2, P0_20, ALT3); +// impl_pin_trait!(LPUART0, tx, P2_1, ALT2, P0_3, ALT2, P0_21, ALT3); +// impl_pin_trait!(LPUART0, rts, P2_2, ALT2, P0_0, ALT2, P0_22, ALT3); +// impl_pin_trait!(LPUART0, cts, P2_3, ALT2, P0_1, ALT2, P0_23, ALT3); +impl_pin_trait!(LPUART2, rx, P2_3, ALT3); +impl_pin_trait!(LPUART2, tx, P2_2, ALT3); // ============================================================================ // ERROR TYPES AND RESULTS -- cgit From a8eb124e47e633cd81e0863253d5f6bdd7545260 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 19 Nov 2025 09:11:54 -0800 Subject: OSTimer updates (#24) * Initialize OSTIMER0 during HAL initialization Provide the user with a working time driver. Signed-off-by: Felipe Balbi * Handle time_driver interrupt internally Signed-off-by: Felipe Balbi * Gate `time-driver` impl behind a `time` flag Also prevents creation of an `Ostimer` instance if the `time` feature is active. * Remove some dead code --------- Signed-off-by: Felipe Balbi Co-authored-by: James Munns --- Cargo.lock | 1 + Cargo.toml | 18 +- examples/Cargo.lock | 1 + examples/Cargo.toml | 4 +- examples/src/bin/blinky.rs | 13 -- examples/src/bin/ostimer_alarm.rs | 122 ---------- examples/src/bin/ostimer_async.rs | 64 ------ examples/src/bin/ostimer_counter.rs | 139 ------------ examples/src/bin/ostimer_race_test.rs | 405 ---------------------------------- src/clocks/mod.rs | 6 +- src/config.rs | 2 + src/lib.rs | 11 +- src/ostimer.rs | 88 ++++++-- 13 files changed, 98 insertions(+), 776 deletions(-) delete mode 100644 examples/src/bin/ostimer_alarm.rs delete mode 100644 examples/src/bin/ostimer_async.rs delete mode 100644 examples/src/bin/ostimer_counter.rs delete mode 100644 examples/src/bin/ostimer_race_test.rs diff --git a/Cargo.lock b/Cargo.lock index 0fb5bfb12..46322c4de 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -328,6 +328,7 @@ source = "git+https://github.com/OpenDevicePartnership/mcxa-pac?rev=3ab4c868f75a dependencies = [ "cortex-m", "cortex-m-rt", + "critical-section", "vcell", ] diff --git a/Cargo.toml b/Cargo.toml index 60f836ac3..0ed6995c6 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -9,14 +9,12 @@ categories = ["embedded", "hardware-support", "no-std"] [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -cortex-m-rt = { version = "0.7", features = ["device"] } +cortex-m-rt = { version = "0.7" } critical-section = "1.2.0" defmt = { version = "1.0", optional = true } embassy-embedded-hal = "0.5.0" embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] } embassy-sync = "0.7.2" -embassy-time = "0.5.0" -embassy-time-driver = "0.2.1" embedded-hal-1 = { package = "embedded-hal", version = "1.0" } embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } embedded-hal-async = { version = "1.0" } @@ -24,10 +22,14 @@ embedded-hal-nb = { version = "1.0" } embedded-io = "0.6" embedded-io-async = { version = "0.6.1" } heapless = "0.8" -mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "3ab4c868f75a9240bb8fdce24982d34f2273aabf", version = "0.1.0" } +mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt", "critical-section"], rev = "3ab4c868f75a9240bb8fdce24982d34f2273aabf", version = "0.1.0" } nb = "1.1.0" paste = "1.0.15" +# `time` dependencies +embassy-time = { version = "0.5.0", optional = true } +embassy-time-driver = { version = "0.2.1", optional = true } + [features] default = [] @@ -35,6 +37,12 @@ default = [] # Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) defmt = ["dep:defmt"] -rt = [] +rt = ["cortex-m-rt/device"] unstable-pac = [] + +# Embassy time +time = [ + "dep:embassy-time", + "dep:embassy-time-driver", +] diff --git a/examples/Cargo.lock b/examples/Cargo.lock index b2ac9a051..14f472cbf 100644 --- a/examples/Cargo.lock +++ b/examples/Cargo.lock @@ -446,6 +446,7 @@ source = "git+https://github.com/OpenDevicePartnership/mcxa-pac?rev=3ab4c868f75a dependencies = [ "cortex-m", "cortex-m-rt", + "critical-section", "vcell", ] diff --git a/examples/Cargo.toml b/examples/Cargo.toml index d03d3d95c..d1c6a2071 100644 --- a/examples/Cargo.toml +++ b/examples/Cargo.toml @@ -6,13 +6,13 @@ license = "MIT OR Apache-2.0" [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -cortex-m-rt = { version = "0.7", features = ["device"] } +cortex-m-rt = { version = "0.7" } critical-section = "1.2.0" defmt = "1.0" defmt-rtt = "1.0" embassy-embedded-hal = "0.5.0" embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } -embassy-mcxa = { path = "../", features = ["defmt", "rt", "unstable-pac"] } +embassy-mcxa = { path = "../", features = ["defmt", "rt", "unstable-pac", "time"] } embassy-sync = "0.7.2" embassy-time = "0.5.0" embassy-time-driver = "0.2.1" diff --git a/examples/src/bin/blinky.rs b/examples/src/bin/blinky.rs index 28d83a12e..ab1e59bdb 100644 --- a/examples/src/bin/blinky.rs +++ b/examples/src/bin/blinky.rs @@ -2,29 +2,16 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa::bind_interrupts; use embassy_time::Timer; use hal::gpio::{Level, Output}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; -// Bind only OS_EVENT for timer interrupts -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - #[embassy_executor::main] async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); defmt::info!("Blink example"); - // Initialize embassy-time global driver backed by OSTIMER0 - hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); - let mut red = Output::new(p.P3_18, Level::High); let mut green = Output::new(p.P3_19, Level::High); let mut blue = Output::new(p.P3_21, Level::High); diff --git a/examples/src/bin/ostimer_alarm.rs b/examples/src/bin/ostimer_alarm.rs deleted file mode 100644 index 6d38741b7..000000000 --- a/examples/src/bin/ostimer_alarm.rs +++ /dev/null @@ -1,122 +0,0 @@ -#![no_std] -#![no_main] - -use core::sync::atomic::{AtomicBool, Ordering}; - -use embassy_executor::Spawner; -use embassy_mcxa::bind_interrupts; -use embassy_mcxa::clocks::periph_helpers::OstimerClockSel; -use embassy_mcxa::clocks::PoweredClock; -use embassy_mcxa::lpuart::{Config, Lpuart}; -use embassy_mcxa_examples::init_uart2_pins; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -// Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed. -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -// Global flag for alarm callback -static ALARM_FLAG: AtomicBool = AtomicBool::new(false); - -// Alarm callback function -fn alarm_callback() { - ALARM_FLAG.store(true, Ordering::Release); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - unsafe { - init_uart2_pins(hal::pac()); - } - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - uart.write_str_blocking("OSTIMER Alarm Example\n"); - - // Initialize embassy-time global driver backed by OSTIMER0 - hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); - - // Create OSTIMER instance - let config = hal::ostimer::Config { - init_match_max: true, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: OstimerClockSel::Clk1M, - }; - let ostimer = hal::ostimer::Ostimer::::new(p.OSTIMER0, config); - - // Create alarm with callback - let alarm = hal::ostimer::Alarm::new() - .with_callback(alarm_callback) - .with_flag(&ALARM_FLAG); - - uart.write_str_blocking("Scheduling alarm for 2 seconds...\n"); - - // Schedule alarm to expire in 2 seconds (2,000,000 microseconds) - let scheduled = ostimer.schedule_alarm_delay(&alarm, 2_000_000); - if scheduled { - uart.write_str_blocking("Alarm scheduled successfully\n"); - } else { - uart.write_str_blocking("Failed to schedule alarm (would exceed timer capacity)\n"); - return; - } - - // Wait for alarm to expire - loop { - // Check if alarm has expired - if ALARM_FLAG.load(Ordering::Acquire) { - uart.write_str_blocking("Alarm expired! Callback executed.\n"); - break; - } - - // Busy wait - don't use Timer::after_millis as it interferes with alarm MATCH - for _ in 0..100000 { - cortex_m::asm::nop(); - } - } - - // Demonstrate canceling an alarm - uart.write_str_blocking("Scheduling another alarm for 3 seconds...\n"); - ALARM_FLAG.store(false, Ordering::Release); // Reset flag - - let scheduled = ostimer.schedule_alarm_delay(&alarm, 3_000_000); - if scheduled { - uart.write_str_blocking("Alarm scheduled. Waiting 1 second then canceling...\n"); - - // Wait 1 second - embassy_time::Timer::after_millis(1000).await; - - // Cancel the alarm - ostimer.cancel_alarm(&alarm); - uart.write_str_blocking("Alarm canceled\n"); - - // Check immediately if alarm flag is set - if !ALARM_FLAG.load(Ordering::Acquire) { - uart.write_str_blocking("Alarm was successfully canceled\n"); - } else { - uart.write_str_blocking("Alarm fired despite cancellation\n"); - } - } - - uart.write_str_blocking("Example complete\n"); -} diff --git a/examples/src/bin/ostimer_async.rs b/examples/src/bin/ostimer_async.rs deleted file mode 100644 index f043184e7..000000000 --- a/examples/src/bin/ostimer_async.rs +++ /dev/null @@ -1,64 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::bind_interrupts; -use embassy_mcxa_examples::init_uart2_pins; -use embassy_time::{Duration, Timer}; -use hal::lpuart::{Config, Lpuart}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -// Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed. -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - unsafe { - init_uart2_pins(hal::pac()); - } - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - uart.blocking_write(b"boot\n").unwrap(); - - // Avoid mass NVIC writes here; DefaultHandler now safely returns. - - // Initialize embassy-time global driver backed by OSTIMER0 (re-enables OS_EVENT with priority) - // The bind_interrupts! macro handles handler binding automatically - - // Initialize OSTIMER with default 1MHz frequency - // Adjust this value to match your actual OSTIMER clock frequency - hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000); - - // Removed force-pend; rely on real hardware match to trigger OS_EVENT. - - // Log using defmt if enabled - defmt::info!("OSTIMER async example starting..."); - - loop { - defmt::info!("tick"); - uart.write_str_blocking("tick\n"); - Timer::after(Duration::from_millis(1000)).await; - } -} diff --git a/examples/src/bin/ostimer_counter.rs b/examples/src/bin/ostimer_counter.rs deleted file mode 100644 index f36915ff2..000000000 --- a/examples/src/bin/ostimer_counter.rs +++ /dev/null @@ -1,139 +0,0 @@ -//! # OSTIMER Counter Reading and Reset Example -//! -//! This example demonstrates the new timer counter reading and reset functionality -//! of the OSTIMER driver. - -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::periph_helpers::OstimerClockSel; -use embassy_mcxa::clocks::PoweredClock; -use embassy_mcxa::lpuart::{Blocking, Config, Lpuart}; -use embassy_time::{Duration, Timer}; -use hal::bind_interrupts; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(Default::default()); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - unsafe { - embassy_mcxa_examples::init_uart2_pins(hal::pac()); - } - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); - - // Initialize the OSTIMER time driver - hal::ostimer::time_driver::init( - hal::interrupt::Priority::from(3), - 1_000_000, // 1MHz clock - ); - - // Create OSTIMER instance - let ostimer = hal::ostimer::Ostimer::::new( - p.OSTIMER0, - hal::ostimer::Config { - init_match_max: true, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: OstimerClockSel::Clk1M, - }, - ); - - // Read initial counter value - let initial_counter = ostimer.now(); - uart.write_str_blocking("Initial counter value: "); - write_u64(&mut uart, initial_counter); - uart.write_str_blocking("\n"); - - // Wait a bit to let counter increment - Timer::after(Duration::from_millis(100)).await; - - // Read counter again - let counter_after_wait = ostimer.now(); - uart.write_str_blocking("Counter after 100ms wait: "); - write_u64(&mut uart, counter_after_wait); - uart.write_str_blocking("\n"); - uart.write_str_blocking("Difference: "); - write_u64(&mut uart, counter_after_wait - initial_counter); - uart.write_str_blocking(" ticks\n"); - - // Reset the timer - uart.write_str_blocking("Resetting timer...\n"); - ostimer.reset(hal::pac()); - - // Read counter after reset - let counter_after_reset = ostimer.now(); - uart.write_str_blocking("Counter after reset: "); - write_u64(&mut uart, counter_after_reset); - uart.write_str_blocking("\n"); - - // Wait again to verify timer is working - Timer::after(Duration::from_millis(50)).await; - - let final_counter = ostimer.now(); - uart.write_str_blocking("Counter after another 50ms: "); - write_u64(&mut uart, final_counter); - uart.write_str_blocking("\n"); - uart.write_str_blocking("Difference after reset: "); - write_u64(&mut uart, final_counter - counter_after_reset); - uart.write_str_blocking(" ticks\n"); - - uart.write_str_blocking("Example complete\n"); -} - -// Helper function to write a u64 value as decimal string -fn write_u64(uart: &mut Lpuart<'_, Blocking>, value: u64) { - if value == 0 { - uart.write_str_blocking("0"); - return; - } - - let mut buffer = [0u8; 20]; // Enough for max u64 - let mut i = 0; - let mut v = value; - - while v > 0 { - buffer[i] = b'0' + (v % 10) as u8; - v /= 10; - i += 1; - } - - // Write digits in reverse order - while i > 0 { - i -= 1; - match buffer[i] { - b'0' => uart.write_str_blocking("0"), - b'1' => uart.write_str_blocking("1"), - b'2' => uart.write_str_blocking("2"), - b'3' => uart.write_str_blocking("3"), - b'4' => uart.write_str_blocking("4"), - b'5' => uart.write_str_blocking("5"), - b'6' => uart.write_str_blocking("6"), - b'7' => uart.write_str_blocking("7"), - b'8' => uart.write_str_blocking("8"), - b'9' => uart.write_str_blocking("9"), - _ => uart.write_str_blocking("?"), - } - } -} diff --git a/examples/src/bin/ostimer_race_test.rs b/examples/src/bin/ostimer_race_test.rs deleted file mode 100644 index 0106b92a7..000000000 --- a/examples/src/bin/ostimer_race_test.rs +++ /dev/null @@ -1,405 +0,0 @@ -//! # OSTIMER Race Condition Test -//! -//! This example tests for race conditions in the OSTIMER driver by: -//! - Scheduling alarms sequentially (hardware limitation: only one at a time) -//! - Reading the counter during interrupt-heavy periods -//! - Testing concurrent timer operations -//! - Stress testing interrupt handling - -#![no_std] -#![no_main] - -use core::sync::atomic::{AtomicU32, Ordering}; - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::periph_helpers::OstimerClockSel; -use embassy_mcxa::clocks::PoweredClock; -use embassy_mcxa::lpuart::{Blocking, Config, Lpuart}; -use embassy_time::{Duration, Timer}; -use hal::bind_interrupts; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!(struct Irqs { - OS_EVENT => hal::ostimer::time_driver::OsEventHandler; -}); - -#[used] -#[no_mangle] -static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT; - -// Global counters for race condition detection -static ALARM_CALLBACK_COUNT: AtomicU32 = AtomicU32::new(0); -static INTERRUPT_COUNT: AtomicU32 = AtomicU32::new(0); -static RACE_DETECTED: AtomicU32 = AtomicU32::new(0); - -// Alarm callback function -fn alarm_callback() { - let _count = ALARM_CALLBACK_COUNT.fetch_add(1, Ordering::SeqCst); - INTERRUPT_COUNT.fetch_add(1, Ordering::SeqCst); - - // Simulate some work in the callback to increase chance of races - for _ in 0..10 { - cortex_m::asm::nop(); - } -} - -fn report_default_handler(uart: &mut Lpuart<'_, Blocking>) { - let snapshot = hal::interrupt::default_handler_snapshot(); - if snapshot.count == 0 { - return; - } - - uart.write_str_blocking("WARNING: DefaultHandler executed "); - write_u32(uart, snapshot.count); - uart.write_str_blocking(" time(s). Vector="); - write_u32(uart, snapshot.vector as u32); - uart.write_str_blocking(" CFSR=0x"); - write_hex32(uart, snapshot.cfsr); - uart.write_str_blocking(" HFSR=0x"); - write_hex32(uart, snapshot.hfsr); - uart.write_str_blocking(" PC=0x"); - write_hex32(uart, snapshot.stacked_pc); - uart.write_str_blocking(" LR=0x"); - write_hex32(uart, snapshot.stacked_lr); - uart.write_str_blocking(" SP=0x"); - write_hex32(uart, snapshot.stacked_sp); - uart.write_str_blocking("\n"); - - hal::interrupt::clear_default_handler_snapshot(); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(Default::default()); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - unsafe { - embassy_mcxa_examples::init_uart2_pins(hal::pac()); - } - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); - - // The bind_interrupts! macro handles handler binding automatically - - // Initialize the OSTIMER time driver FIRST - hal::ostimer::time_driver::init( - hal::interrupt::Priority::from(3), - 1_000_000, // 1MHz clock - ); - - uart.write_str_blocking("Time driver initialized\n"); - - // Create OSTIMER instance - let ostimer = hal::ostimer::Ostimer::::new( - p.OSTIMER0, - hal::ostimer::Config { - init_match_max: true, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: OstimerClockSel::Clk1M, - }, - ); - - uart.write_str_blocking("OSTIMER instance created\n"); - - // Test 1: Sequential alarm scheduling (OSTIMER only supports one alarm at a time) - uart.write_str_blocking("Test 1: Sequential alarm scheduling...\n"); - test_rapid_alarms(&ostimer, &mut uart).await; - report_default_handler(&mut uart); - - // Test 2: Counter reading during interrupts - uart.write_str_blocking("Test 2: Counter reading during interrupts...\n"); - test_counter_reading_during_interrupts(&ostimer, &mut uart).await; - report_default_handler(&mut uart); - - // Test 3: Concurrent timer operations - uart.write_str_blocking("Test 3: Concurrent timer operations...\n"); - test_concurrent_operations(&ostimer, &mut uart).await; - report_default_handler(&mut uart); - - // Test 4: Timer reset during operation - uart.write_str_blocking("Test 4: Timer reset during operation...\n"); - test_reset_during_operation(&ostimer, &mut uart, hal::pac()).await; - report_default_handler(&mut uart); - - // Report results - uart.write_str_blocking("Race condition test complete\n"); - uart.write_str_blocking("Callback count: "); - write_u32(&mut uart, ALARM_CALLBACK_COUNT.load(Ordering::SeqCst)); - uart.write_str_blocking("\nInterrupt count: "); - write_u32(&mut uart, INTERRUPT_COUNT.load(Ordering::SeqCst)); - uart.write_str_blocking("\nRaces detected: "); - write_u32(&mut uart, RACE_DETECTED.load(Ordering::SeqCst)); - uart.write_str_blocking("\n"); -} - -// Test rapid alarm scheduling to stress interrupt handling -async fn test_rapid_alarms( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut Lpuart<'_, Blocking>, -) { - let initial_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); - - // Schedule 10 alarms sequentially (OSTIMER only supports one alarm at a time) - for _i in 0..10 { - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - let delay_us = 1000; // 1ms delay for each alarm - if ostimer.schedule_alarm_delay(&alarm, delay_us) { - // Wait for this alarm to complete before scheduling the next - Timer::after(Duration::from_micros(delay_us + 100)).await; - report_default_handler(uart); - } else { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm (match not ready)\n"); - } - } - - // All alarms should have completed by now - let final_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst); - let expected_count = initial_count + 10; - - if final_count != expected_count { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Expected "); - write_u32(uart, expected_count); - uart.write_str_blocking(" callbacks, got "); - write_u32(uart, final_count); - uart.write_str_blocking("\n"); - } else { - uart.write_str_blocking("PASS: All rapid alarms executed\n"); - } -} - -// Test reading counter while interrupts are firing -async fn test_counter_reading_during_interrupts( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut Lpuart<'_, Blocking>, -) { - let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - // Schedule an alarm that will fire soon - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - if !ostimer.schedule_alarm_delay(&alarm, 500) { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before counter stress\n"); - } - - // While alarm is pending, read the counter many times rapidly - // This tests if counter reading is atomic and doesn't get corrupted by interrupts - let mut last_counter = ostimer.now(); - let mut consistent_reads = 0; - let mut total_reads = 0; - - for _ in 0..1000 { - let current_counter = ostimer.now(); - total_reads += 1; - - // Check if counter is monotonically increasing (basic sanity check) - if current_counter >= last_counter { - consistent_reads += 1; - } - last_counter = current_counter; - - // Small delay between reads - for _ in 0..10 { - cortex_m::asm::nop(); - } - - report_default_handler(uart); - } - - // Wait for alarm to complete - Timer::after(Duration::from_millis(1)).await; - - let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - if consistent_reads == total_reads { - uart.write_str_blocking("PASS: Counter reading consistent during interrupts\n"); - } else { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Counter reading inconsistent: "); - write_u32(uart, consistent_reads); - uart.write_str_blocking("/"); - write_u32(uart, total_reads); - uart.write_str_blocking(" consistent\n"); - } - - if final_interrupt_count > initial_interrupt_count { - uart.write_str_blocking("PASS: Interrupt fired during counter reading test\n"); - } else { - uart.write_str_blocking("WARNING: No interrupt fired during counter reading test\n"); - } -} - -// Test concurrent timer operations (embassy-time + alarms) -async fn test_concurrent_operations( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut Lpuart<'_, Blocking>, -) { - let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - // Start an embassy-time timer - let timer_future = Timer::after(Duration::from_millis(2)); - - // Schedule an alarm that should fire before the timer - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - if !ostimer.schedule_alarm_delay(&alarm, 1000) { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before concurrent operations\n"); - } - - // Wait for both to complete - timer_future.await; - - let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst); - - if final_interrupt_count > initial_interrupt_count { - uart.write_str_blocking("PASS: Concurrent operations completed\n"); - } else { - uart.write_str_blocking("WARNING: No interrupts during concurrent operations\n"); - } -} - -// Test timer reset during active operations -async fn test_reset_during_operation( - ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>, - uart: &mut Lpuart<'_, Blocking>, - peripherals: &hal::pac::Peripherals, -) { - let initial_counter = ostimer.now(); - - // Schedule an alarm - let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback); - if !ostimer.schedule_alarm_delay(&alarm, 2000) { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before reset test\n"); - } - - // Wait a bit then reset the timer - Timer::after(Duration::from_millis(1)).await; - ostimer.reset(peripherals); - - // Check counter after reset - let counter_after_reset = ostimer.now(); - - // Wait to see if the alarm still fires (it shouldn't after reset) - Timer::after(Duration::from_millis(2)).await; - - let final_counter = ostimer.now(); - - if counter_after_reset < initial_counter { - uart.write_str_blocking("PASS: Timer reset successful\n"); - } else { - RACE_DETECTED.fetch_add(1, Ordering::SeqCst); - uart.write_str_blocking("ERROR: Timer reset may have failed\n"); - } - - uart.write_str_blocking("Counter progression after reset: "); - write_u64(uart, initial_counter); - uart.write_str_blocking(" -> "); - write_u64(uart, counter_after_reset); - uart.write_str_blocking(" -> "); - write_u64(uart, final_counter); - uart.write_str_blocking("\n"); -} - -// Helper function to write a u32 value as decimal string -fn write_u32(uart: &mut Lpuart<'_, Blocking>, value: u32) { - if value == 0 { - uart.write_str_blocking("0"); - return; - } - - let mut buffer = [0u8; 10]; // Enough for max u32 - let mut i = 0; - let mut v = value; - - while v > 0 { - buffer[i] = b'0' + (v % 10) as u8; - v /= 10; - i += 1; - } - - // Write digits in reverse order - while i > 0 { - i -= 1; - match buffer[i] { - b'0' => uart.write_str_blocking("0"), - b'1' => uart.write_str_blocking("1"), - b'2' => uart.write_str_blocking("2"), - b'3' => uart.write_str_blocking("3"), - b'4' => uart.write_str_blocking("4"), - b'5' => uart.write_str_blocking("5"), - b'6' => uart.write_str_blocking("6"), - b'7' => uart.write_str_blocking("7"), - b'8' => uart.write_str_blocking("8"), - b'9' => uart.write_str_blocking("9"), - _ => uart.write_str_blocking("?"), - } - } -} - -fn write_hex32(uart: &mut Lpuart<'_, Blocking>, value: u32) { - let mut buf = [b'0'; 8]; - let mut tmp = value; - for i in (0..8).rev() { - let digit = (tmp & 0xF) as u8; - buf[i] = match digit { - 0..=9 => b'0' + digit, - 10..=15 => b'A' + (digit - 10), - _ => b'?', - }; - tmp >>= 4; - } - uart.blocking_write(&buf).unwrap(); -} - -// Helper function to write a u64 value as decimal string -fn write_u64(uart: &mut Lpuart<'_, Blocking>, value: u64) { - if value == 0 { - uart.blocking_write(b"0").unwrap(); - return; - } - - let mut buffer = [0u8; 20]; // Enough for max u64 - let mut i = 0; - let mut v = value; - - while v > 0 { - buffer[i] = b'0' + (v % 10) as u8; - v /= 10; - i += 1; - } - - // Write digits in reverse order - while i > 0 { - i -= 1; - match buffer[i] { - b'0' => uart.blocking_write(b"0").unwrap(), - b'1' => uart.blocking_write(b"1").unwrap(), - b'2' => uart.blocking_write(b"2").unwrap(), - b'3' => uart.blocking_write(b"3").unwrap(), - b'4' => uart.blocking_write(b"4").unwrap(), - b'5' => uart.blocking_write(b"5").unwrap(), - b'6' => uart.blocking_write(b"6").unwrap(), - b'7' => uart.blocking_write(b"7").unwrap(), - b'8' => uart.blocking_write(b"8").unwrap(), - b'9' => uart.blocking_write(b"9").unwrap(), - _ => uart.blocking_write(b"?").unwrap(), - } - } -} diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index 558fb0278..a12e125c6 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -867,7 +867,9 @@ macro_rules! impl_cc_gate { /// This module contains implementations of MRCC APIs, specifically of the [`Gate`] trait, /// for various low level peripherals. pub(crate) mod gate { - use super::periph_helpers::{AdcConfig, LpuartConfig, NoConfig, OsTimerConfig}; + #[cfg(not(feature = "time"))] + use super::periph_helpers::OsTimerConfig; + use super::periph_helpers::{AdcConfig, LpuartConfig, NoConfig}; use super::*; // These peripherals have no additional upstream clocks or configuration required @@ -888,7 +890,9 @@ pub(crate) mod gate { // These peripherals DO have meaningful configuration, and could fail if the system // clocks do not match their needs. + #[cfg(not(feature = "time"))] impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); + impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig); impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig); } diff --git a/src/config.rs b/src/config.rs index 0939c11f1..9c0d47ecb 100644 --- a/src/config.rs +++ b/src/config.rs @@ -5,6 +5,7 @@ use crate::interrupt::Priority; #[non_exhaustive] pub struct Config { + #[cfg(feature = "time")] pub time_interrupt_priority: Priority, pub rtc_interrupt_priority: Priority, pub adc_interrupt_priority: Priority, @@ -14,6 +15,7 @@ pub struct Config { impl Default for Config { fn default() -> Self { Self { + #[cfg(feature = "time")] time_interrupt_priority: Priority::from(0), rtc_interrupt_priority: Priority::from(0), adc_interrupt_priority: Priority::from(0), diff --git a/src/lib.rs b/src/lib.rs index c885ecc50..e93ff61a6 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -14,6 +14,9 @@ pub mod lpuart; pub mod ostimer; pub mod rtc; +#[cfg(feature = "rt")] +pub use crate::pac::NVIC_PRIO_BITS; + #[rustfmt::skip] embassy_hal_internal::peripherals!( ADC0, @@ -83,6 +86,8 @@ embassy_hal_internal::peripherals!( MBC0, MRCC0, OPAMP0, + + #[cfg(not(feature = "time"))] OSTIMER0, P0_0, @@ -335,7 +340,6 @@ pub use interrupt::InterruptExt; pub use mcxa_pac as pac; #[cfg(not(feature = "unstable-pac"))] pub(crate) use mcxa_pac as pac; -pub use ostimer::Ostimer0 as Ostimer0Token; pub use rtc::Rtc0 as Rtc0Token; /// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. @@ -343,6 +347,7 @@ pub use rtc::Rtc0 as Rtc0Token; pub fn init(cfg: crate::config::Config) -> Peripherals { let peripherals = Peripherals::take(); // Apply user-configured priority early; enabling is left to examples/apps + #[cfg(feature = "time")] crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority); // Apply user-configured priority early; enabling is left to examples/apps crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); @@ -352,6 +357,10 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { // Configure clocks crate::clocks::init(cfg.clock_cfg).unwrap(); + // Initialize embassy-time global driver backed by OSTIMER0 + #[cfg(feature = "time")] + crate::ostimer::time_driver::init(crate::config::Config::default().time_interrupt_priority, 1_000_000); + // Enable GPIO clocks unsafe { _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); diff --git a/src/ostimer.rs b/src/ostimer.rs index cd5451b53..c51812e3d 100644 --- a/src/ostimer.rs +++ b/src/ostimer.rs @@ -35,7 +35,6 @@ use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; use crate::clocks::{assert_reset, enable_and_reset, is_reset_released, release_reset, Gate, PoweredClock}; use crate::interrupt::InterruptExt; use crate::pac; -use crate::peripherals::OSTIMER0; // PAC defines the shared RegisterBlock under `ostimer0`. type Regs = pac::ostimer0::RegisterBlock; @@ -283,15 +282,15 @@ impl<'d, I: Instance> Ostimer<'d, I> { .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); unsafe { - assert_reset::(); + assert_reset::(); for _ in 0..RESET_STABILIZE_SPINS { cortex_m::asm::nop(); } - release_reset::(); + release_reset::(); - while !is_reset_released::() { + while !is_reset_released::() { cortex_m::asm::nop(); } } @@ -490,9 +489,7 @@ pub trait Instance: Gate + PeripheralType { fn ptr() -> *const Regs; } -// Token for OSTIMER0 provided by embassy-hal-internal peripherals macro. -pub type Ostimer0 = crate::peripherals::OSTIMER0; - +#[cfg(not(feature = "time"))] impl Instance for crate::peripherals::OSTIMER0 { #[inline(always)] fn ptr() -> *const Regs { @@ -500,14 +497,6 @@ impl Instance for crate::peripherals::OSTIMER0 { } } -// Also implement Instance for the Peri wrapper type -// impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> { -// #[inline(always)] -// fn ptr() -> *const Regs { -// pac::Ostimer0::ptr() -// } -// } - #[inline(always)] fn bin_to_gray(x: u64) -> u64 { x ^ (x >> 1) @@ -523,6 +512,7 @@ fn gray_to_bin(gray: u64) -> u64 { bin } +#[cfg(feature = "time")] pub mod time_driver { use core::sync::atomic::Ordering; use core::task::Waker; @@ -537,7 +527,55 @@ pub mod time_driver { use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; use crate::clocks::{enable_and_reset, PoweredClock}; use crate::pac; - use crate::peripherals::OSTIMER0; + + #[allow(non_camel_case_types)] + pub(crate) struct _OSTIMER0_TIME_DRIVER { + _x: (), + } + + // #[cfg(feature = "time")] + // impl_cc_gate!(_OSTIMER0_TIME_DRIVER, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); + + impl crate::clocks::Gate for _OSTIMER0_TIME_DRIVER { + type MrccPeriphConfig = crate::clocks::periph_helpers::OsTimerConfig; + + #[inline] + unsafe fn enable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_cc1().modify(|_, w| w.ostimer0().enabled()); + } + + #[inline] + unsafe fn disable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_cc1().modify(|_r, w| w.ostimer0().disabled()); + } + + #[inline] + fn is_clock_enabled() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_cc1().read().ostimer0().is_enabled() + } + + #[inline] + unsafe fn release_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().enabled()); + } + + #[inline] + unsafe fn assert_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().disabled()); + } + + #[inline] + fn is_reset_released() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_rst1().read().ostimer0().is_enabled() + } + } + pub struct Driver; static TIMER_WAKER: AtomicWaker = AtomicWaker::new(); @@ -625,7 +663,7 @@ pub mod time_driver { /// The embassy_time_driver macro handles driver registration automatically. pub fn init(priority: crate::interrupt::Priority, frequency_hz: u64) { let _clock_freq = unsafe { - enable_and_reset::(&OsTimerConfig { + enable_and_reset::<_OSTIMER0_TIME_DRIVER>(&OsTimerConfig { power: PoweredClock::AlwaysEnabled, source: OstimerClockSel::Clk1M, }) @@ -694,12 +732,14 @@ pub mod time_driver { } }); } +} - /// Type-level handler to be used with bind_interrupts! for OS_EVENT. - pub struct OsEventHandler; - impl crate::interrupt::typelevel::Handler for OsEventHandler { - unsafe fn on_interrupt() { - on_interrupt(); - } - } +#[cfg(feature = "time")] +use crate::pac::interrupt; + +#[cfg(feature = "time")] +#[allow(non_snake_case)] +#[interrupt] +fn OS_EVENT() { + time_driver::on_interrupt() } -- cgit From eed314ebb58772476971af49b36b68301eb0d8cc Mon Sep 17 00:00:00 2001 From: MathisDerooNXP <52401665+MathisDeroo@users.noreply.github.com> Date: Fri, 21 Nov 2025 10:00:01 -0800 Subject: Gpio support v2 (#26) * Improve GPIO driver and add button example - port and pcr registers are defined using paste! - added pin configuration for slew rate, drive strength, mux function, etc... - added button example to showcase input gpio feature Signed-off-by: Mathis Deroo * Add pull-up pull-down config support for input gpio Signed-off-by: Mathis Deroo * Replace GPIOs enum with existing ones in the PAC Signed-off-by: Mathis Deroo * Remove init_gpio_pin function as it is done in hal init config Signed-off-by: Mathis Deroo * Integrate feedback for the GPIO driver - Add again missing IO peripherals - Added function to configure separately slew rate, drive strength, pull. - Revert comment changes Signed-off-by: Mathis Deroo * Create user-readable field for the pin configuration Signed-off-by: Mathis Deroo * examples: button: remove left-over OSTIMER initialization While at that, also cargo fmt * Fix warnings * Add documentation for public functions Signed-off-by: Mathis Deroo * Expose port and pcr registers to AnyPin implementation Signed-off-by: Mathis Deroo * Remove unnecessary change Signed-off-by: Mathis Deroo * Run cargo fmt --------- Signed-off-by: Mathis Deroo Co-authored-by: Felipe Balbi --- examples/src/bin/blinky.rs | 8 +- examples/src/bin/button.rs | 21 ++++ src/gpio.rs | 285 +++++++++++++++++++++++++++++++++++++++------ src/lib.rs | 8 +- src/pins.rs | 61 ---------- 5 files changed, 278 insertions(+), 105 deletions(-) create mode 100644 examples/src/bin/button.rs diff --git a/examples/src/bin/blinky.rs b/examples/src/bin/blinky.rs index ab1e59bdb..dd08ec0d9 100644 --- a/examples/src/bin/blinky.rs +++ b/examples/src/bin/blinky.rs @@ -3,7 +3,7 @@ use embassy_executor::Spawner; use embassy_time::Timer; -use hal::gpio::{Level, Output}; +use hal::gpio::{DriveStrength, Level, Output, SlewRate}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; #[embassy_executor::main] @@ -12,9 +12,9 @@ async fn main(_spawner: Spawner) { defmt::info!("Blink example"); - let mut red = Output::new(p.P3_18, Level::High); - let mut green = Output::new(p.P3_19, Level::High); - let mut blue = Output::new(p.P3_21, Level::High); + let mut red = Output::new(p.P3_18, Level::High, DriveStrength::Normal, SlewRate::Fast); + let mut green = Output::new(p.P3_19, Level::High, DriveStrength::Normal, SlewRate::Fast); + let mut blue = Output::new(p.P3_21, Level::High, DriveStrength::Normal, SlewRate::Fast); loop { defmt::info!("Toggle LEDs"); diff --git a/examples/src/bin/button.rs b/examples/src/bin/button.rs new file mode 100644 index 000000000..2abfe0a9f --- /dev/null +++ b/examples/src/bin/button.rs @@ -0,0 +1,21 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{DriveStrength, Input, Pull, SlewRate}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("Button example"); + + let monitor = Input::new(p.P1_7, Pull::Disabled, DriveStrength::Normal, SlewRate::Slow); + + loop { + defmt::info!("Pin level is {:?}", monitor.get_level()); + Timer::after_millis(1000).await; + } +} diff --git a/src/gpio.rs b/src/gpio.rs index 09a414d3b..9565fbb6e 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -8,13 +8,87 @@ use core::marker::PhantomData; use embassy_hal_internal::{Peri, PeripheralType}; use paste::paste; +use crate::pac::port0::pcr0::{Dse, Inv, Mux, Pe, Ps, Sre}; + /// Logical level for GPIO pins. #[derive(Copy, Clone, Eq, PartialEq, Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Level { Low, High, } +impl From for Level { + fn from(val: bool) -> Self { + match val { + true => Self::High, + false => Self::Low, + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum Pull { + Disabled, + Up, + Down, +} + +impl From for (Pe, Ps) { + fn from(pull: Pull) -> Self { + match pull { + Pull::Disabled => (Pe::Pe0, Ps::Ps0), + Pull::Up => (Pe::Pe1, Ps::Ps1), + Pull::Down => (Pe::Pe1, Ps::Ps0), + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum SlewRate { + Fast, + Slow, +} + +impl From for Sre { + fn from(slew_rate: SlewRate) -> Self { + match slew_rate { + SlewRate::Fast => Sre::Sre0, + SlewRate::Slow => Sre::Sre1, + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum DriveStrength { + Normal, + Double, +} + +impl From for Dse { + fn from(strength: DriveStrength) -> Self { + match strength { + DriveStrength::Normal => Dse::Dse0, + DriveStrength::Double => Dse::Dse1, + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum Inverter { + Disabled, + Enabled, +} + +impl From for Inv { + fn from(strength: Inverter) -> Self { + match strength { + Inverter::Disabled => Inv::Inv0, + Inverter::Enabled => Inv::Inv1, + } + } +} + pub type Gpio = crate::peripherals::GPIO0; /// Type-erased representation of a GPIO pin. @@ -22,12 +96,26 @@ pub struct AnyPin { port: usize, pin: usize, gpio: &'static crate::pac::gpio0::RegisterBlock, + port_reg: &'static crate::pac::port0::RegisterBlock, + pcr_reg: &'static crate::pac::port0::Pcr0, } impl AnyPin { /// Create an `AnyPin` from raw components. - pub fn new(port: usize, pin: usize, gpio: &'static crate::pac::gpio0::RegisterBlock) -> Self { - Self { port, pin, gpio } + pub fn new( + port: usize, + pin: usize, + gpio: &'static crate::pac::gpio0::RegisterBlock, + port_reg: &'static crate::pac::port0::RegisterBlock, + pcr_reg: &'static crate::pac::port0::Pcr0, + ) -> Self { + Self { + port, + pin, + gpio, + port_reg, + pcr_reg, + } } #[inline(always)] @@ -49,6 +137,16 @@ impl AnyPin { pub fn pin_index(&self) -> usize { self.pin } + + #[inline(always)] + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { + self.port_reg + } + + #[inline(always)] + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { + self.pcr_reg + } } embassy_hal_internal::impl_peripheral!(AnyPin); @@ -65,6 +163,20 @@ trait SealedPin { } fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock; + + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock; + + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0; + + fn set_function(&self, function: Mux); + + fn set_pull(&self, pull: Pull); + + fn set_drive_strength(&self, strength: Dse); + + fn set_slew_rate(&self, slew_rate: Sre); + + fn set_enable_input_buffer(&self); } /// GPIO pin trait. @@ -75,57 +187,120 @@ pub trait GpioPin: SealedPin + Sized + PeripheralType + Into + 'static { // SAFETY: This is only called within the GpioPin trait, which is only // implemented within this module on valid pin peripherals and thus // has been verified to be correct. - AnyPin::new(self.port(), self.pin(), self.gpio()) + AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg()) } } impl SealedPin for AnyPin { - #[inline] fn pin_port(&self) -> usize { self.port * 32 + self.pin } - #[inline] fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { self.gpio() } + + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { + self.port_reg() + } + + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { + self.pcr_reg() + } + + fn set_function(&self, function: Mux) { + self.pcr_reg().modify(|_, w| w.mux().variant(function)); + } + + fn set_pull(&self, pull: Pull) { + let (pull_enable, pull_select) = pull.into(); + self.pcr_reg().modify(|_, w| { + w.pe().variant(pull_enable); + w.ps().variant(pull_select) + }); + } + + fn set_drive_strength(&self, strength: Dse) { + self.pcr_reg().modify(|_, w| w.dse().variant(strength)); + } + + fn set_slew_rate(&self, slew_rate: Sre) { + self.pcr_reg().modify(|_, w| w.sre().variant(slew_rate)); + } + + fn set_enable_input_buffer(&self) { + self.pcr_reg().modify(|_, w| w.ibe().ibe1()); + } } impl GpioPin for AnyPin {} macro_rules! impl_pin { ($peri:ident, $port:expr, $pin:expr, $block:ident) => { - impl SealedPin for crate::peripherals::$peri { - #[inline] - fn pin_port(&self) -> usize { - $port * 32 + $pin - } + paste! { + impl SealedPin for crate::peripherals::$peri { + fn pin_port(&self) -> usize { + $port * 32 + $pin + } - #[inline] - fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { - unsafe { &*crate::pac::$block::ptr() } - } - } + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + unsafe { &*crate::pac::$block::ptr() } + } + + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { + unsafe { &*crate::pac::[]::ptr() } + } + + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { + self.port_reg().[]() + } + + fn set_function(&self, function: Mux) { + unsafe { + let port_reg = &*crate::pac::[]::ptr(); + port_reg.[]().modify(|_, w| { + w.mux().variant(function) + }); + } + } + + fn set_pull(&self, pull: Pull) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + let (pull_enable, pull_select) = pull.into(); + port_reg.[]().modify(|_, w| { + w.pe().variant(pull_enable); + w.ps().variant(pull_select) + }); + } + + fn set_drive_strength(&self, strength: Dse) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + port_reg.[]().modify(|_, w| w.dse().variant(strength)); + } - impl GpioPin for crate::peripherals::$peri {} + fn set_slew_rate(&self, slew_rate: Sre) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + port_reg.[]().modify(|_, w| w.sre().variant(slew_rate)); + } - impl From for AnyPin { - fn from(value: crate::peripherals::$peri) -> Self { - value.degrade() + fn set_enable_input_buffer(&self) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + port_reg.[]().modify(|_, w| w.ibe().ibe1()); + } } - } - impl crate::peripherals::$peri { - /// Convenience helper to obtain a type-erased handle to this pin. - pub fn degrade(&self) -> AnyPin { - AnyPin::new(self.port(), self.pin(), self.gpio()) + impl GpioPin for crate::peripherals::$peri {} + + impl From for AnyPin { + fn from(value: crate::peripherals::$peri) -> Self { + value.degrade() + } } - #[inline] - pub fn set_mux_gpio() { - paste! { - let port = unsafe { crate::pac::[]::steal()}; - port.[]().write(|w| w.mux().mux00()); + impl crate::peripherals::$peri { + /// Convenience helper to obtain a type-erased handle to this pin. + pub fn degrade(&self) -> AnyPin { + AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg()) } } } @@ -309,6 +484,7 @@ impl<'d> Flex<'d> { /// The pin remains unmodified. The initial output level is unspecified, but /// can be changed before the pin is put into output mode. pub fn new(pin: Peri<'d, impl GpioPin>) -> Self { + pin.set_function(Mux::Mux00); Self { pin: pin.into(), _marker: PhantomData, @@ -326,22 +502,22 @@ impl<'d> Flex<'d> { } /// Put the pin into input mode. - /// - /// The pull setting is left unchanged. - #[inline] pub fn set_as_input(&mut self) { let mask = self.mask(); let gpio = self.gpio(); + + self.set_enable_input_buffer(); + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); } /// Put the pin into output mode. - /// - /// The initial output level is left unchanged. - #[inline] pub fn set_as_output(&mut self) { let mask = self.mask(); let gpio = self.gpio(); + + self.set_pull(Pull::Disabled); + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); } @@ -395,6 +571,31 @@ impl<'d> Flex<'d> { pub fn is_set_low(&self) -> bool { !self.is_set_high() } + + /// Configure the pin pull up/down level. + pub fn set_pull(&mut self, pull_select: Pull) { + self.pin.set_pull(pull_select); + } + + /// Configure the pin drive strength. + pub fn set_drive_strength(&mut self, strength: DriveStrength) { + self.pin.set_drive_strength(strength.into()); + } + + /// Configure the pin slew rate. + pub fn set_slew_rate(&mut self, slew_rate: SlewRate) { + self.pin.set_slew_rate(slew_rate.into()); + } + + /// Enable input buffer for the pin. + pub fn set_enable_input_buffer(&mut self) { + self.pin.set_enable_input_buffer(); + } + + /// Get pin level. + pub fn get_level(&self) -> Level { + self.is_high().into() + } } /// GPIO output driver that owns a `Flex` pin. @@ -404,10 +605,12 @@ pub struct Output<'d> { impl<'d> Output<'d> { /// Create a GPIO output driver for a [GpioPin] with the provided [Level]. - pub fn new(pin: Peri<'d, impl GpioPin>, initial: Level) -> Self { + pub fn new(pin: Peri<'d, impl GpioPin>, initial: Level, strength: DriveStrength, slew_rate: SlewRate) -> Self { let mut flex = Flex::new(pin); flex.set_level(initial); flex.set_as_output(); + flex.set_drive_strength(strength); + flex.set_slew_rate(slew_rate); Self { flex } } @@ -461,9 +664,12 @@ pub struct Input<'d> { impl<'d> Input<'d> { /// Create a GPIO input driver for a [GpioPin]. - pub fn new(pin: Peri<'d, impl GpioPin>) -> Self { + pub fn new(pin: Peri<'d, impl GpioPin>, pull_select: Pull, strength: DriveStrength, slew_rate: SlewRate) -> Self { let mut flex = Flex::new(pin); flex.set_as_input(); + flex.set_drive_strength(strength); + flex.set_slew_rate(slew_rate); + flex.set_pull(pull_select); Self { flex } } @@ -484,6 +690,11 @@ impl<'d> Input<'d> { pub fn into_flex(self) -> Flex<'d> { self.flex } + + // Get the pin level. + pub fn get_level(&self) -> Level { + self.flex.get_level() + } } // Both embedded_hal 0.2 and 1.0 must be supported by embassy HALs. diff --git a/src/lib.rs b/src/lib.rs index e93ff61a6..175642f75 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,7 +1,9 @@ #![no_std] -// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs -// are complete prior to release. -#![allow(clippy::missing_safety_doc)] +#![allow(async_fn_in_trait)] +#![doc = include_str!("../README.md")] + +// //! ## Feature flags +// #![doc = document_features::document_features!(feature_label = r#"{feature}"#)] pub mod clocks; // still provide clock helpers pub mod gpio; diff --git a/src/pins.rs b/src/pins.rs index f802568f3..f65195dd2 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -60,64 +60,3 @@ pub unsafe fn configure_adc_pins() { }); core::arch::asm!("dsb sy; isb sy"); } - -/// Configure a pin for a specific mux alternative. -/// -/// # Arguments -/// * `port` - Port number (0-4) -/// * `pin` - Pin number (varies by port: PORT0=0-7, PORT1=0-19, PORT2=0-26, PORT3=0-31, PORT4=0-7) -/// * `mux` - Mux alternative (0-15, where 0 = GPIO, 1-15 = other functions) -pub unsafe fn set_pin_mux(port: u8, pin: u8, mux: u8) { - // Validate mux value (0-15) - if mux > 15 { - panic!("Invalid mux value: {}, must be 0-15", mux); - } - - // Validate pin number based on port - let max_pin = match port { - 0 => 7, // PORT0: pins 0-7 - 1 => 19, // PORT1: pins 0-19 - 2 => 26, // PORT2: pins 0-26 - 3 => 31, // PORT3: pins 0-31 - 4 => 7, // PORT4: pins 0-7 - _ => panic!("Unsupported GPIO port: {}", port), - }; - - if pin > max_pin { - panic!("Invalid pin {} for PORT{}, max pin is {}", pin, port, max_pin); - } - - // Get the base address for the port - let port_base: *mut u32 = match port { - 0 => pac::Port0::ptr() as *mut u32, - 1 => pac::Port1::ptr() as *mut u32, - 2 => pac::Port2::ptr() as *mut u32, - 3 => pac::Port3::ptr() as *mut u32, - 4 => pac::Port4::ptr() as *mut u32, - _ => panic!("Unsupported GPIO port: {}", port), - }; - - // PCR registers are 4 bytes apart, starting at offset 0 for PCR0 - let pcr_addr = port_base.add(pin as usize); - - // Read current PCR value - let current_val = pcr_addr.read_volatile(); - - // Clear mux bits (bits 8-11) and set new mux value - let new_val = (current_val & !(0xF << 8)) | ((mux as u32) << 8); - - // Write back the new value - pcr_addr.write_volatile(new_val); - - core::arch::asm!("dsb sy; isb sy"); -} - -/// Configure a pin for GPIO mode (ALT0). -/// This is a convenience function that calls set_pin_mux with mux=0. -/// -/// # Arguments -/// * `port` - Port number (0-4) -/// * `pin` - Pin number (varies by port: PORT0=0-7, PORT1=0-19, PORT2=0-26, PORT3=0-31, PORT4=0-7) -pub unsafe fn set_pin_mux_gpio(port: u8, pin: u8) { - set_pin_mux(port, pin, 0); -} -- cgit From 35dc874cb80b754676c5975548c4da475aee2675 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 21 Nov 2025 10:02:40 -0800 Subject: chore(deps): bump actions/checkout from 5 to 6 (#35) Bumps [actions/checkout](https://github.com/actions/checkout) from 5 to 6. - [Release notes](https://github.com/actions/checkout/releases) - [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md) - [Commits](https://github.com/actions/checkout/compare/v5...v6) --- updated-dependencies: - dependency-name: actions/checkout dependency-version: '6' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- .github/workflows/cargo-vet.yml | 2 +- .github/workflows/check.yml | 14 +++++++------- .github/workflows/nostd.yml | 2 +- .github/workflows/rolling.yml | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/.github/workflows/cargo-vet.yml b/.github/workflows/cargo-vet.yml index d6baa29f5..d585d1df5 100644 --- a/.github/workflows/cargo-vet.yml +++ b/.github/workflows/cargo-vet.yml @@ -19,7 +19,7 @@ jobs: CARGO_VET_VERSION: 0.10.1 steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index 8e05f5c5d..ad9f44428 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -37,7 +37,7 @@ jobs: workdir: [ ".", "examples",] steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true @@ -67,7 +67,7 @@ jobs: workdir: ["examples"] steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true @@ -88,7 +88,7 @@ jobs: # runs-on: ubuntu-latest # name: semver # steps: - # - uses: actions/checkout@v5 + # - uses: actions/checkout@v6 # with: # submodules: true # - name: Install stable @@ -106,7 +106,7 @@ jobs: name: nightly / doc steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true @@ -131,7 +131,7 @@ jobs: fail-fast: false steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true @@ -155,7 +155,7 @@ jobs: name: ubuntu / stable / deny steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true @@ -200,7 +200,7 @@ jobs: name: ubuntu / ${{ matrix.msrv }} steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml index 6083577da..cf6629854 100644 --- a/.github/workflows/nostd.yml +++ b/.github/workflows/nostd.yml @@ -21,7 +21,7 @@ jobs: name: ${{ matrix.target }} steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml index a9f0b30b4..73b48484a 100644 --- a/.github/workflows/rolling.yml +++ b/.github/workflows/rolling.yml @@ -20,7 +20,7 @@ jobs: strategy: fail-fast: false steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true - name: Install stable @@ -44,7 +44,7 @@ jobs: name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }}) steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v6 with: submodules: true - name: Install ${{ matrix.msrv }} -- cgit From afbf72fb7842c926a9ac9b62f794ed010d4f7b27 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 21 Nov 2025 11:42:11 -0800 Subject: Update to latest PAC (#39) It adds a complete Mux enum Co-authored-by: Felipe Balbi --- Cargo.lock | 2 +- Cargo.toml | 2 +- examples/Cargo.lock | 2 +- src/gpio.rs | 2 +- src/pins.rs | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 46322c4de..d9f4f08af 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -324,7 +324,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092" [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac?rev=3ab4c868f75a9240bb8fdce24982d34f2273aabf#3ab4c868f75a9240bb8fdce24982d34f2273aabf" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#3b36508ab1ac397861bae3431cc95c204f3ca6e9" dependencies = [ "cortex-m", "cortex-m-rt", diff --git a/Cargo.toml b/Cargo.toml index 0ed6995c6..bf46b3107 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,7 +22,7 @@ embedded-hal-nb = { version = "1.0" } embedded-io = "0.6" embedded-io-async = { version = "0.6.1" } heapless = "0.8" -mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt", "critical-section"], rev = "3ab4c868f75a9240bb8fdce24982d34f2273aabf", version = "0.1.0" } +mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt", "critical-section"], version = "0.1.0" } nb = "1.1.0" paste = "1.0.15" diff --git a/examples/Cargo.lock b/examples/Cargo.lock index 14f472cbf..473ce2b3f 100644 --- a/examples/Cargo.lock +++ b/examples/Cargo.lock @@ -442,7 +442,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092" [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac?rev=3ab4c868f75a9240bb8fdce24982d34f2273aabf#3ab4c868f75a9240bb8fdce24982d34f2273aabf" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#3b36508ab1ac397861bae3431cc95c204f3ca6e9" dependencies = [ "cortex-m", "cortex-m-rt", diff --git a/src/gpio.rs b/src/gpio.rs index 9565fbb6e..7dba7ab4f 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -484,7 +484,7 @@ impl<'d> Flex<'d> { /// The pin remains unmodified. The initial output level is unspecified, but /// can be changed before the pin is put into output mode. pub fn new(pin: Peri<'d, impl GpioPin>) -> Self { - pin.set_function(Mux::Mux00); + pin.set_function(Mux::Mux0); Self { pin: pin.into(), _marker: PhantomData, diff --git a/src/pins.rs b/src/pins.rs index f65195dd2..0a83a41f0 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -14,7 +14,7 @@ pub unsafe fn configure_uart2_pins_port2() { .dse() .dse1() .mux() - .mux11() + .mux3() .ibe() .ibe1() }); @@ -28,7 +28,7 @@ pub unsafe fn configure_uart2_pins_port2() { .dse() .dse1() .mux() - .mux11() + .mux3() .ibe() .ibe1() }); @@ -50,7 +50,7 @@ pub unsafe fn configure_adc_pins() { .dse() .dse0() .mux() - .mux00() + .mux0() .ibe() .ibe0() .inv() -- cgit From c21a402ebcf26fd40a2809fc771b71a3e9b31962 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 21 Nov 2025 14:56:00 -0800 Subject: Fix clkdiv configuration DIV should be modified while the clock is halted, not after it's already running. --- src/clocks/mod.rs | 16 ++++++---------- src/clocks/periph_helpers.rs | 4 ++-- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index a12e125c6..0b4535dc4 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -652,17 +652,15 @@ impl ClockOperator<'_> { }); } - // Halt and reset the div + // Halt and reset the div; then set our desired div. self.syscon.frohfdiv().write(|w| { w.halt().halt(); w.reset().asserted(); + unsafe { w.div().bits(d.into_bits()) }; w }); - // Then change the div, unhalt it, and reset it + // Then unhalt it, and reset it self.syscon.frohfdiv().write(|w| { - unsafe { - w.div().bits(d.into_bits()); - } w.halt().run(); w.reset().released(); w @@ -743,17 +741,15 @@ impl ClockOperator<'_> { }); } - // Halt and reset the div + // Halt and reset the div; then set our desired div. self.syscon.frolfdiv().write(|w| { w.halt().halt(); w.reset().asserted(); + unsafe { w.div().bits(d.into_bits()) }; w }); - // Then change the div, unhalt it, and reset it + // Then unhalt it, and reset it self.syscon.frolfdiv().write(|w| { - unsafe { - w.div().bits(d.into_bits()); - } w.halt().run(); w.reset().released(); w diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index e5b234c5b..8914f6833 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -240,12 +240,12 @@ impl SPConfHelper for LpuartConfig { clkdiv.modify(|_r, w| { w.halt().on(); w.reset().on(); + unsafe { w.div().bits(self.div.into_bits()) }; w }); clkdiv.modify(|_r, w| { w.halt().off(); w.reset().off(); - unsafe { w.div().bits(self.div.into_bits()) }; w }); @@ -377,12 +377,12 @@ impl SPConfHelper for AdcConfig { mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { w.halt().on(); w.reset().on(); + unsafe { w.div().bits(self.div.into_bits()) }; w }); mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { w.halt().off(); w.reset().off(); - unsafe { w.div().bits(self.div.into_bits()) }; w }); -- cgit From c552cf2434b847b7a8af06e15982eb29d07ad2fa Mon Sep 17 00:00:00 2001 From: James Munns Date: Mon, 24 Nov 2025 17:37:57 +0100 Subject: Introduce clkout peripheral (#36) Introduces a ClockOut peripheral, allowing for ensuring that internal clocks are operating correctly. Also fixes some incorrect PLL/Div4 usage. --- examples/Cargo.toml | 2 +- examples/src/bin/clkout.rs | 69 ++++++++++++++++++ src/clkout.rs | 169 +++++++++++++++++++++++++++++++++++++++++++++ src/clocks/mod.rs | 43 +++++++++++- src/gpio.rs | 6 +- src/lib.rs | 5 ++ 6 files changed, 288 insertions(+), 6 deletions(-) create mode 100644 examples/src/bin/clkout.rs create mode 100644 src/clkout.rs diff --git a/examples/Cargo.toml b/examples/Cargo.toml index d1c6a2071..4f15a6aff 100644 --- a/examples/Cargo.toml +++ b/examples/Cargo.toml @@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0" [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -cortex-m-rt = { version = "0.7" } +cortex-m-rt = { version = "0.7", features = ["set-sp", "set-vtor"] } critical-section = "1.2.0" defmt = "1.0" defmt-rtt = "1.0" diff --git a/examples/src/bin/clkout.rs b/examples/src/bin/clkout.rs new file mode 100644 index 000000000..bfd963540 --- /dev/null +++ b/examples/src/bin/clkout.rs @@ -0,0 +1,69 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4}; +use embassy_mcxa::clocks::PoweredClock; +use embassy_mcxa::gpio::{DriveStrength, SlewRate}; +use embassy_mcxa::{Level, Output}; +use embassy_time::Timer; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Demonstrate CLKOUT, using Pin P4.2 +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + let mut pin = p.P4_2; + let mut clkout = p.CLKOUT; + + loop { + defmt::info!("Set Low..."); + let mut output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); + Timer::after_millis(500).await; + + defmt::info!("Set High..."); + output.set_high(); + Timer::after_millis(400).await; + + defmt::info!("Set Low..."); + output.set_low(); + Timer::after_millis(500).await; + + defmt::info!("16k..."); + // Run Clock Out with the 16K clock + let _clock_out = ClockOut::new( + clkout.reborrow(), + pin.reborrow(), + Config { + sel: ClockOutSel::Clk16K, + div: Div4::no_div(), + level: PoweredClock::NormalEnabledDeepSleepDisabled, + }, + ) + .unwrap(); + + Timer::after_millis(3000).await; + + defmt::info!("Set Low..."); + drop(_clock_out); + + let _output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); + Timer::after_millis(500).await; + + // Run Clock Out with the 12M clock, divided by 3 + defmt::info!("4M..."); + let _clock_out = ClockOut::new( + clkout.reborrow(), + pin.reborrow(), + Config { + sel: ClockOutSel::Fro12M, + div: const { Div4::from_divisor(3).unwrap() }, + level: PoweredClock::NormalEnabledDeepSleepDisabled, + }, + ) + .unwrap(); + + // Let it run for 3 seconds... + Timer::after_millis(3000).await; + } +} diff --git a/src/clkout.rs b/src/clkout.rs new file mode 100644 index 000000000..88c731df1 --- /dev/null +++ b/src/clkout.rs @@ -0,0 +1,169 @@ +//! CLKOUT pseudo-peripheral +//! +//! CLKOUT is a part of the clock generation subsystem, and can be used +//! either to generate arbitrary waveforms, or to debug the state of +//! internal oscillators. + +use core::marker::PhantomData; + +use embassy_hal_internal::Peri; + +pub use crate::clocks::periph_helpers::Div4; +use crate::clocks::{with_clocks, ClockError, PoweredClock}; +use crate::pac::mrcc0::mrcc_clkout_clksel::Mux; +use crate::peripherals::CLKOUT; + +/// A peripheral representing the CLKOUT pseudo-peripheral +pub struct ClockOut<'a> { + _p: PhantomData<&'a mut CLKOUT>, + freq: u32, +} + +/// Selected clock source to output +pub enum ClockOutSel { + /// 12MHz Internal Oscillator + Fro12M, + /// FRO180M Internal Oscillator, via divisor + FroHfDiv, + /// External Oscillator + ClkIn, + /// 16KHz oscillator + Clk16K, + /// Output of PLL1 + Pll1Clk, + /// Main System CPU clock, divided by 6 + SlowClk, +} + +/// Configuration for the ClockOut +pub struct Config { + /// Selected Source Clock + pub sel: ClockOutSel, + /// Selected division level + pub div: Div4, + /// Selected power level + pub level: PoweredClock, +} + +impl<'a> ClockOut<'a> { + /// Create a new ClockOut pin. On success, the clock signal will begin immediately + /// on the given pin. + pub fn new( + _peri: Peri<'a, CLKOUT>, + pin: Peri<'a, impl sealed::ClockOutPin>, + cfg: Config, + ) -> Result { + // There's no MRCC enable bit, so we check the validity of the clocks here + // + // TODO: Should we check that the frequency is suitably low? + let (freq, mux) = check_sel(cfg.sel, cfg.level)?; + + // All good! Apply requested config, starting with the pin. + pin.mux(); + + setup_clkout(mux, cfg.div); + + Ok(Self { + _p: PhantomData, + freq: freq / cfg.div.into_divisor(), + }) + } + + /// Frequency of the clkout pin + #[inline] + pub fn frequency(&self) -> u32 { + self.freq + } +} + +impl Drop for ClockOut<'_> { + fn drop(&mut self) { + disable_clkout(); + } +} + +/// Check whether the given clock selection is valid +fn check_sel(sel: ClockOutSel, level: PoweredClock) -> Result<(u32, Mux), ClockError> { + let res = with_clocks(|c| { + Ok(match sel { + ClockOutSel::Fro12M => (c.ensure_fro_hf_active(&level)?, Mux::Clkroot12m), + ClockOutSel::FroHfDiv => (c.ensure_fro_hf_div_active(&level)?, Mux::ClkrootFircDiv), + ClockOutSel::ClkIn => (c.ensure_clk_in_active(&level)?, Mux::ClkrootSosc), + ClockOutSel::Clk16K => (c.ensure_clk_16k_vdd_core_active(&level)?, Mux::Clkroot16k), + ClockOutSel::Pll1Clk => (c.ensure_pll1_clk_active(&level)?, Mux::ClkrootSpll), + ClockOutSel::SlowClk => (c.ensure_slow_clk_active(&level)?, Mux::ClkrootSlow), + }) + }); + let Some(res) = res else { + return Err(ClockError::NeverInitialized); + }; + res +} + +/// Set up the clkout pin using the given mux and div settings +fn setup_clkout(mux: Mux, div: Div4) { + let mrcc = unsafe { crate::pac::Mrcc0::steal() }; + + mrcc.mrcc_clkout_clksel().write(|w| w.mux().variant(mux)); + + // Set up clkdiv + mrcc.mrcc_clkout_clkdiv().write(|w| { + w.halt().set_bit(); + w.reset().set_bit(); + unsafe { w.div().bits(div.into_bits()) }; + w + }); + mrcc.mrcc_clkout_clkdiv().write(|w| { + w.halt().clear_bit(); + w.reset().clear_bit(); + unsafe { w.div().bits(div.into_bits()) }; + w + }); + + while mrcc.mrcc_clkout_clkdiv().read().unstab().bit_is_set() {} +} + +/// Stop the clkout +fn disable_clkout() { + // Stop the output by selecting the "none" clock + // + // TODO: restore the pin to hi-z or something? + let mrcc = unsafe { crate::pac::Mrcc0::steal() }; + mrcc.mrcc_clkout_clkdiv().write(|w| { + w.reset().set_bit(); + w.halt().set_bit(); + unsafe { + w.div().bits(0); + } + w + }); + mrcc.mrcc_clkout_clksel().write(|w| unsafe { w.bits(0b111) }); +} + +mod sealed { + use embassy_hal_internal::PeripheralType; + + use crate::gpio::{Pull, SealedPin}; + + /// Sealed marker trait for clockout pins + pub trait ClockOutPin: PeripheralType { + /// Set the given pin to the correct muxing state + fn mux(&self); + } + + macro_rules! impl_pin { + ($pin:ident, $func:ident) => { + impl ClockOutPin for crate::peripherals::$pin { + fn mux(&self) { + self.set_function(crate::pac::port0::pcr0::Mux::$func); + self.set_pull(Pull::Disabled); + } + } + }; + } + + impl_pin!(P0_6, Mux12); + impl_pin!(P3_6, Mux1); + impl_pin!(P3_8, Mux12); + impl_pin!(P4_2, Mux1); +} diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index 0b4535dc4..948355079 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -91,8 +91,11 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { // For now, just use FIRC as the main/cpu clock, which should already be // the case on reset assert!(operator.scg0.rccr().read().scs().is_firc()); + let input = operator.clocks.fro_hf_root.clone().unwrap(); + operator.clocks.main_clk = Some(input.clone()); + // We can also assume cpu/system clk == fro_hf because div is /1. assert_eq!(operator.syscon.ahbclkdiv().read().div().bits(), 0); - operator.clocks.main_clk = Some(operator.clocks.fro_hf_root.clone().unwrap()); + operator.clocks.cpu_system_clk = Some(input); critical_section::with(|cs| { let mut clks = CLOCKS.borrow_ref_mut(cs); @@ -189,6 +192,9 @@ pub struct Clocks { /// peripherals. pub main_clk: Option, + /// `CPU_CLK` or `SYSTEM_CLK` is the output of `main_clk`, run through the `AHBCLKDIV` + pub cpu_system_clk: Option, + /// `pll1_clk` is the output of the main system PLL, `pll1`. pub pll1_clk: Option, } @@ -522,10 +528,43 @@ impl Clocks { Ok(clk.frequency) } + /// Ensure the `pll1_clk` clock is active and valid at the given power state. + pub fn ensure_pll1_clk_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "pll1_clk" }) + } + /// Ensure the `pll1_clk_div` clock is active and valid at the given power state. pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result { Err(ClockError::NotImplemented { clock: "pll1_clk_div" }) } + + /// Ensure the `CPU_CLK` or `SYSTEM_CLK` is active + pub fn ensure_cpu_system_clk_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.cpu_system_clk.as_ref() else { + return Err(ClockError::BadConfig { + clock: "cpu_system_clk", + reason: "required but not active", + }); + }; + // Can the main_clk ever be active in deep sleep? I think it is gated? + match at_level { + PoweredClock::NormalEnabledDeepSleepDisabled => {} + PoweredClock::AlwaysEnabled => { + return Err(ClockError::BadConfig { + clock: "main_clk", + reason: "not low power active", + }) + } + } + + Ok(clk.frequency) + } + + pub fn ensure_slow_clk_active(&self, at_level: &PoweredClock) -> Result { + let freq = self.ensure_cpu_system_clk_active(at_level)?; + + Ok(freq / 6) + } } impl PoweredClock { @@ -749,7 +788,7 @@ impl ClockOperator<'_> { w }); // Then unhalt it, and reset it - self.syscon.frolfdiv().write(|w| { + self.syscon.frolfdiv().modify(|_r, w| { w.halt().run(); w.reset().released(); w diff --git a/src/gpio.rs b/src/gpio.rs index 7dba7ab4f..4f79aff93 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -102,7 +102,7 @@ pub struct AnyPin { impl AnyPin { /// Create an `AnyPin` from raw components. - pub fn new( + fn new( port: usize, pin: usize, gpio: &'static crate::pac::gpio0::RegisterBlock, @@ -151,7 +151,7 @@ impl AnyPin { embassy_hal_internal::impl_peripheral!(AnyPin); -trait SealedPin { +pub(crate) trait SealedPin { fn pin_port(&self) -> usize; fn port(&self) -> usize { @@ -297,7 +297,7 @@ macro_rules! impl_pin { } } - impl crate::peripherals::$peri { + impl crate::peripherals::$peri { /// Convenience helper to obtain a type-erased handle to this pin. pub fn degrade(&self) -> AnyPin { AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg()) diff --git a/src/lib.rs b/src/lib.rs index 175642f75..6f3a63c94 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -10,6 +10,7 @@ pub mod gpio; pub mod pins; // pin mux helpers pub mod adc; +pub mod clkout; pub mod config; pub mod interrupt; pub mod lpuart; @@ -33,6 +34,10 @@ embassy_hal_internal::peripherals!( CDOG0, CDOG1, + // CLKOUT is not specifically a peripheral (it's part of SYSCON), + // but we still want it to be a singleton. + CLKOUT, + CMC, CMP0, CMP1, -- cgit From 6e1bc1139b7dcc8407fd1213bf0cb0788d26288e Mon Sep 17 00:00:00 2001 From: James Munns Date: Mon, 24 Nov 2025 17:50:46 +0100 Subject: Update to patched PAC with corrected Div4 (#41) --- Cargo.lock | 2 +- examples/Cargo.lock | 2 +- src/clocks/periph_helpers.rs | 28 ++++++++++++++-------------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index d9f4f08af..eb6c142ef 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -324,7 +324,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092" [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#3b36508ab1ac397861bae3431cc95c204f3ca6e9" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#9a857ec9780527679978b42cc60288aeef03baa2" dependencies = [ "cortex-m", "cortex-m-rt", diff --git a/examples/Cargo.lock b/examples/Cargo.lock index 473ce2b3f..56ae41d48 100644 --- a/examples/Cargo.lock +++ b/examples/Cargo.lock @@ -442,7 +442,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092" [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#3b36508ab1ac397861bae3431cc95c204f3ca6e9" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#9a857ec9780527679978b42cc60288aeef03baa2" dependencies = [ "cortex-m", "cortex-m-rt", diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index 8914f6833..eac3ef8dd 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -225,8 +225,8 @@ impl SPConfHelper for LpuartConfig { // no ClkrootFunc7, just write manually for now clksel.write(|w| w.bits(0b111)); clkdiv.modify(|_r, w| { - w.reset().on(); - w.halt().on(); + w.reset().asserted(); + w.halt().asserted(); w }); return Ok(0); @@ -238,18 +238,18 @@ impl SPConfHelper for LpuartConfig { // Set up clkdiv clkdiv.modify(|_r, w| { - w.halt().on(); - w.reset().on(); + w.halt().asserted(); + w.reset().asserted(); unsafe { w.div().bits(self.div.into_bits()) }; w }); clkdiv.modify(|_r, w| { - w.halt().off(); - w.reset().off(); + w.halt().deasserted(); + w.reset().deasserted(); w }); - while clkdiv.read().unstab().is_on() {} + while clkdiv.read().unstab().is_unstable() {} Ok(freq / self.div.into_divisor()) } @@ -362,8 +362,8 @@ impl SPConfHelper for AdcConfig { w.mux().bits(0b111) }); mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { - w.reset().on(); - w.halt().on(); + w.reset().asserted(); + w.halt().asserted(); w }); return Ok(0); @@ -375,18 +375,18 @@ impl SPConfHelper for AdcConfig { // Set up clkdiv mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { - w.halt().on(); - w.reset().on(); + w.halt().asserted(); + w.reset().asserted(); unsafe { w.div().bits(self.div.into_bits()) }; w }); mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { - w.halt().off(); - w.reset().off(); + w.halt().deasserted(); + w.reset().deasserted(); w }); - while mrcc0.mrcc_adc_clkdiv().read().unstab().is_on() {} + while mrcc0.mrcc_adc_clkdiv().read().unstab().is_unstable() {} Ok(freq / self.div.into_divisor()) } -- cgit From 7ee5cb570f0c0daeb2e6a9d5120fd96ee885025f Mon Sep 17 00:00:00 2001 From: James Munns Date: Mon, 24 Nov 2025 18:41:43 +0100 Subject: Remove the pac singleton function (#42) There will be a follow up PR that removes the unsafe `init` functions, but I wanted to squash this out first in case I don't get to it all today. --- examples/src/bin/adc_interrupt.rs | 4 ++-- examples/src/bin/adc_polling.rs | 11 ++--------- examples/src/bin/hello.rs | 2 +- examples/src/bin/lpuart_buffered.rs | 2 +- examples/src/bin/lpuart_polling.rs | 2 +- examples/src/bin/rtc_alarm.rs | 2 +- examples/src/lib.rs | 4 ++-- src/lib.rs | 15 --------------- 8 files changed, 10 insertions(+), 32 deletions(-) diff --git a/examples/src/bin/adc_interrupt.rs b/examples/src/bin/adc_interrupt.rs index 9fed052fd..0d3a75a28 100644 --- a/examples/src/bin/adc_interrupt.rs +++ b/examples/src/bin/adc_interrupt.rs @@ -36,7 +36,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2_pins(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral @@ -48,7 +48,7 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); unsafe { - init_adc_pins(hal::pac()); + init_adc_pins(); } let adc_config = LpadcConfig { diff --git a/examples/src/bin/adc_polling.rs b/examples/src/bin/adc_polling.rs index 545f8f77a..02ac321b5 100644 --- a/examples/src/bin/adc_polling.rs +++ b/examples/src/bin/adc_polling.rs @@ -22,10 +22,6 @@ const G_LPADC_RESULT_SHIFT: u32 = 0; async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); - unsafe { - init_uart2_pins(hal::pac()); - } - // Create UART configuration let config = Config { baudrate_bps: 115_200, @@ -36,7 +32,8 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { - init_uart2_pins(hal::pac()); + init_uart2_pins(); + init_adc_pins(); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral @@ -48,10 +45,6 @@ async fn main(_spawner: Spawner) { uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n"); - unsafe { - init_adc_pins(hal::pac()); - } - let adc_config = LpadcConfig { enable_in_doze_mode: true, conversion_average_mode: CalAvgs::Average128, diff --git a/examples/src/bin/hello.rs b/examples/src/bin/hello.rs index e2d0b413d..0362480c1 100644 --- a/examples/src/bin/hello.rs +++ b/examples/src/bin/hello.rs @@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2_pins(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral diff --git a/examples/src/bin/lpuart_buffered.rs b/examples/src/bin/lpuart_buffered.rs index b0d19ef16..4c9294f57 100644 --- a/examples/src/bin/lpuart_buffered.rs +++ b/examples/src/bin/lpuart_buffered.rs @@ -32,7 +32,7 @@ async fn main(_spawner: Spawner) { hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); unsafe { - init_uart2_pins(hal::pac()); + init_uart2_pins(); } // UART configuration (enable both TX and RX) diff --git a/examples/src/bin/lpuart_polling.rs b/examples/src/bin/lpuart_polling.rs index 525d42e2c..c8666e64a 100644 --- a/examples/src/bin/lpuart_polling.rs +++ b/examples/src/bin/lpuart_polling.rs @@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) { // Board-level init for UART2 clocks and pins. unsafe { - init_uart2_pins(hal::pac()); + init_uart2_pins(); } // Create UART configuration diff --git a/examples/src/bin/rtc_alarm.rs b/examples/src/bin/rtc_alarm.rs index a54b4a817..6f8a77101 100644 --- a/examples/src/bin/rtc_alarm.rs +++ b/examples/src/bin/rtc_alarm.rs @@ -34,7 +34,7 @@ async fn main(_spawner: Spawner) { // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { - embassy_mcxa_examples::init_uart2_pins(hal::pac()); + embassy_mcxa_examples::init_uart2_pins(); } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral diff --git a/examples/src/lib.rs b/examples/src/lib.rs index 66b93450a..f5f6124c0 100644 --- a/examples/src/lib.rs +++ b/examples/src/lib.rs @@ -9,7 +9,7 @@ use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; /// Initialize clocks and pin muxing for UART2 debug console. /// Safe to call multiple times; writes are idempotent for our use. -pub unsafe fn init_uart2_pins(_p: &hal::pac::Peripherals) { +pub unsafe fn init_uart2_pins() { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. // GPIO has not. _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); @@ -17,7 +17,7 @@ pub unsafe fn init_uart2_pins(_p: &hal::pac::Peripherals) { } /// Initialize clocks and pin muxing for ADC. -pub unsafe fn init_adc_pins(_p: &hal::pac::Peripherals) { +pub unsafe fn init_adc_pins() { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. // GPIO has not. _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); diff --git a/src/lib.rs b/src/lib.rs index 6f3a63c94..95e6b3479 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -322,21 +322,6 @@ embassy_hal_internal::peripherals!( WWDT0, ); -/// Get access to the PAC Peripherals for low-level register access. -/// This is a lazy-initialized singleton that can be called after init(). -#[allow(static_mut_refs)] -pub fn pac() -> &'static pac::Peripherals { - // SAFETY: We only call this after init(), and the PAC is a singleton. - // The embassy peripheral tokens ensure we don't have multiple mutable accesses. - unsafe { - static mut PAC_INSTANCE: Option = None; - if PAC_INSTANCE.is_none() { - PAC_INSTANCE = Some(pac::Peripherals::steal()); - } - PAC_INSTANCE.as_ref().unwrap() - } -} - // Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. // Re-export interrupt traits and types -- cgit From 05bf2d0438fe8c41d0fe26b85106ff73a6e273e9 Mon Sep 17 00:00:00 2001 From: James Munns Date: Tue, 25 Nov 2025 18:08:13 +0100 Subject: Wire up Lpuart pins (#43) Allow the HAL lpuart driver to correctly configure pins as requested on init. --- Cargo.lock | 2 +- examples/Cargo.lock | 2 +- examples/src/bin/adc_interrupt.rs | 26 +--- examples/src/bin/adc_polling.rs | 31 +---- examples/src/bin/hello.rs | 3 - examples/src/bin/lpuart_buffered.rs | 29 ++--- examples/src/bin/lpuart_polling.rs | 12 +- examples/src/bin/rtc_alarm.rs | 33 +----- examples/src/lib.rs | 9 -- src/clocks/config.rs | 5 + src/clocks/mod.rs | 5 + src/interrupt.rs | 2 +- src/lib.rs | 1 + src/lpuart/buffered.rs | 20 ++-- src/lpuart/mod.rs | 231 ++++++++++++++++++++++++------------ src/pins.rs | 34 ------ 16 files changed, 205 insertions(+), 240 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index eb6c142ef..314120a47 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -324,7 +324,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092" [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#9a857ec9780527679978b42cc60288aeef03baa2" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#e18dfb52500ca77b8d8326662b966a80251182ca" dependencies = [ "cortex-m", "cortex-m-rt", diff --git a/examples/Cargo.lock b/examples/Cargo.lock index 56ae41d48..263807120 100644 --- a/examples/Cargo.lock +++ b/examples/Cargo.lock @@ -442,7 +442,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092" [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#9a857ec9780527679978b42cc60288aeef03baa2" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#e18dfb52500ca77b8d8326662b966a80251182ca" dependencies = [ "cortex-m", "cortex-m-rt", diff --git a/examples/src/bin/adc_interrupt.rs b/examples/src/bin/adc_interrupt.rs index 0d3a75a28..83d8046b3 100644 --- a/examples/src/bin/adc_interrupt.rs +++ b/examples/src/bin/adc_interrupt.rs @@ -6,7 +6,6 @@ use embassy_mcxa_examples::init_adc_pins; use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::clocks::PoweredClock; -use hal::lpuart::{Config, Lpuart}; use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; use hal::pac::adc1::ctrl::CalAvgs; @@ -26,26 +25,7 @@ static KEEP_ADC: unsafe extern "C" fn() = ADC1; async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - unsafe { - embassy_mcxa_examples::init_uart2_pins(); - } - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); + defmt::info!("ADC interrupt Example"); unsafe { init_adc_pins(); @@ -81,7 +61,7 @@ async fn main(_spawner: Spawner) { conv_trigger_config.enable_hardware_trigger = false; adc.set_conv_trigger_config(0, &conv_trigger_config); - uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + defmt::info!("ADC configuration done..."); adc.enable_interrupt(0x1); @@ -98,7 +78,7 @@ async fn main(_spawner: Spawner) { while !adc.is_interrupt_triggered() { // Wait until the interrupt is triggered } - uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); + defmt::info!("*** ADC interrupt TRIGGERED! ***"); //TBD need to print the value } } diff --git a/examples/src/bin/adc_polling.rs b/examples/src/bin/adc_polling.rs index 02ac321b5..ddf3f586b 100644 --- a/examples/src/bin/adc_polling.rs +++ b/examples/src/bin/adc_polling.rs @@ -1,19 +1,15 @@ #![no_std] #![no_main] -use core::fmt::Write; - use embassy_executor::Spawner; -use embassy_mcxa_examples::{init_adc_pins, init_uart2_pins}; +use embassy_mcxa_examples::init_adc_pins; use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::clocks::PoweredClock; -use hal::lpuart::{Config, Lpuart}; use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; use hal::pac::adc1::ctrl::CalAvgs; use hal::pac::adc1::tctrl::Tcmd; -use heapless::String; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; const G_LPADC_RESULT_SHIFT: u32 = 0; @@ -22,28 +18,11 @@ const G_LPADC_RESULT_SHIFT: u32 = 0; async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX unsafe { - init_uart2_pins(); init_adc_pins(); } - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n"); + defmt::info!("=== ADC polling Example ==="); let adc_config = LpadcConfig { enable_in_doze_mode: true, @@ -75,7 +54,7 @@ async fn main(_spawner: Spawner) { conv_trigger_config.enable_hardware_trigger = false; adc.set_conv_trigger_config(0, &conv_trigger_config); - uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); + defmt::info!("=== ADC configuration done... ==="); loop { adc.do_software_trigger(1); @@ -84,8 +63,6 @@ async fn main(_spawner: Spawner) { result = hal::adc::get_conv_result(); } let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; - let mut buf: String<16> = String::new(); // adjust size as needed - write!(buf, "\r\nvalue: {}\r\n", value).unwrap(); - uart.write_str_blocking(&buf); + defmt::info!("value: {=u16}", value); } } diff --git a/examples/src/bin/hello.rs b/examples/src/bin/hello.rs index 0362480c1..f426d1898 100644 --- a/examples/src/bin/hello.rs +++ b/examples/src/bin/hello.rs @@ -27,9 +27,6 @@ async fn main(_spawner: Spawner) { }; // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - unsafe { - embassy_mcxa_examples::init_uart2_pins(); - } let mut uart = Lpuart::new_blocking( p.LPUART2, // Peripheral p.P2_2, // TX pin diff --git a/examples/src/bin/lpuart_buffered.rs b/examples/src/bin/lpuart_buffered.rs index 4c9294f57..7f77d557d 100644 --- a/examples/src/bin/lpuart_buffered.rs +++ b/examples/src/bin/lpuart_buffered.rs @@ -2,39 +2,28 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa as hal; -use embassy_mcxa::interrupt::typelevel::Handler; +use embassy_mcxa::clocks::config::Div8; use embassy_mcxa::lpuart::buffered::BufferedLpuart; use embassy_mcxa::lpuart::Config; use embassy_mcxa::{bind_interrupts, lpuart}; -use embassy_mcxa_examples::init_uart2_pins; -use embedded_io_async::{Read, Write}; +use embedded_io_async::Write; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver bind_interrupts!(struct Irqs { LPUART2 => lpuart::buffered::BufferedInterruptHandler::; }); -// Wrapper function for the interrupt handler -unsafe extern "C" fn lpuart2_handler() { - lpuart::buffered::BufferedInterruptHandler::::on_interrupt(); -} - #[embassy_executor::main] async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - unsafe { - hal::interrupt::install_irq_handler(hal::pac::Interrupt::LPUART2, lpuart2_handler); - } + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); // Configure NVIC for LPUART2 hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); - unsafe { - init_uart2_pins(); - } - // UART configuration (enable both TX and RX) let config = Config { baudrate_bps: 115_200, @@ -69,7 +58,7 @@ async fn main(_spawner: Spawner) { // Echo loop let mut buf = [0u8; 4]; loop { - rx.read_exact(&mut buf[..]).await.unwrap(); - tx.write_all(&buf[..]).await.unwrap(); + let used = rx.read(&mut buf).await.unwrap(); + tx.write_all(&buf[..used]).await.unwrap(); } } diff --git a/examples/src/bin/lpuart_polling.rs b/examples/src/bin/lpuart_polling.rs index c8666e64a..9cea418cc 100644 --- a/examples/src/bin/lpuart_polling.rs +++ b/examples/src/bin/lpuart_polling.rs @@ -2,22 +2,20 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa_examples::init_uart2_pins; +use embassy_mcxa::clocks::config::Div8; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; use crate::hal::lpuart::{Config, Lpuart}; #[embassy_executor::main] async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); defmt::info!("boot"); - // Board-level init for UART2 clocks and pins. - unsafe { - init_uart2_pins(); - } - // Create UART configuration let config = Config { baudrate_bps: 115_200, diff --git a/examples/src/bin/rtc_alarm.rs b/examples/src/bin/rtc_alarm.rs index 6f8a77101..a7800a2d1 100644 --- a/examples/src/bin/rtc_alarm.rs +++ b/examples/src/bin/rtc_alarm.rs @@ -3,7 +3,6 @@ use embassy_executor::Spawner; use embassy_mcxa as hal; -use hal::lpuart::{Config, Lpuart}; use hal::rtc::{RtcDateTime, RtcInterruptEnable}; use hal::InterruptExt; @@ -24,27 +23,7 @@ static KEEP_RTC: unsafe extern "C" fn() = RTC; async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - unsafe { - embassy_mcxa_examples::init_uart2_pins(); - } - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - uart.write_str_blocking("\r\n=== RTC Alarm Example ===\r\n"); + defmt::info!("=== RTC Alarm Example ==="); let rtc_config = hal::rtc::get_default_config(); @@ -61,14 +40,14 @@ async fn main(_spawner: Spawner) { rtc.stop(); - uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n"); + defmt::info!("Time set to: 2025-10-15 14:30:00"); rtc.set_datetime(now); let mut alarm = now; alarm.second += 10; rtc.set_alarm(alarm); - uart.write_str_blocking("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)\r\n"); + defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)"); rtc.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); @@ -82,14 +61,14 @@ async fn main(_spawner: Spawner) { rtc.start(); - uart.write_str_blocking("RTC started, waiting for alarm...\r\n"); + defmt::info!("RTC started, waiting for alarm..."); loop { if rtc.is_alarm_triggered() { - uart.write_str_blocking("\r\n*** ALARM TRIGGERED! ***\r\n"); + defmt::info!("*** ALARM TRIGGERED! ***"); break; } } - uart.write_str_blocking("Example complete - Test PASSED!\r\n"); + defmt::info!("Example complete - Test PASSED!"); } diff --git a/examples/src/lib.rs b/examples/src/lib.rs index f5f6124c0..2573a6adc 100644 --- a/examples/src/lib.rs +++ b/examples/src/lib.rs @@ -7,15 +7,6 @@ use hal::{clocks, pins}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; -/// Initialize clocks and pin muxing for UART2 debug console. -/// Safe to call multiple times; writes are idempotent for our use. -pub unsafe fn init_uart2_pins() { - // NOTE: Lpuart has been updated to properly enable + reset its own clocks. - // GPIO has not. - _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); - pins::configure_uart2_pins_port2(); -} - /// Initialize clocks and pin muxing for ADC. pub unsafe fn init_adc_pins() { // NOTE: Lpuart has been updated to properly enable + reset its own clocks. diff --git a/src/clocks/config.rs b/src/clocks/config.rs index a517afcca..0563b8917 100644 --- a/src/clocks/config.rs +++ b/src/clocks/config.rs @@ -21,6 +21,11 @@ impl Div8 { Self(n) } + /// Divide by one, or no division + pub const fn no_div() -> Self { + Self(0) + } + /// Store a specific divisor value that will divide the source /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source /// by 1, and `Div8::from_divisor(256)` will divide the source diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index 948355079..cd6318c4b 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -928,6 +928,11 @@ pub(crate) mod gate { #[cfg(not(feature = "time"))] impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); + impl_cc_gate!(LPUART0, mrcc_glb_cc0, mrcc_glb_rst0, lpuart0, LpuartConfig); + impl_cc_gate!(LPUART1, mrcc_glb_cc0, mrcc_glb_rst0, lpuart1, LpuartConfig); impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig); + impl_cc_gate!(LPUART3, mrcc_glb_cc0, mrcc_glb_rst0, lpuart3, LpuartConfig); + impl_cc_gate!(LPUART4, mrcc_glb_cc0, mrcc_glb_rst0, lpuart4, LpuartConfig); + impl_cc_gate!(LPUART5, mrcc_glb_cc1, mrcc_glb_rst1, lpuart5, LpuartConfig); impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig); } diff --git a/src/interrupt.rs b/src/interrupt.rs index 134ff03fd..4d409067a 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -7,7 +7,7 @@ #![allow(clippy::missing_safety_doc)] mod generated { - embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1); + embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, RTC, ADC1,); } use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; diff --git a/src/lib.rs b/src/lib.rs index 95e6b3479..f9dda67d9 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -88,6 +88,7 @@ embassy_hal_internal::peripherals!( LPUART2, LPUART3, LPUART4, + LPUART5, MAU0, MBC0, diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index 7b575c086..6f41c33c9 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -123,28 +123,24 @@ impl<'a> BufferedLpuart<'a> { config: Config, ) -> Result { // Configure pins if provided - let tx_pin = tx_pin.map(|pin| { + let tx_pin: Option> = tx_pin.map(|pin| { pin.as_tx(); - let converted: Peri<'a, AnyPin> = pin.into(); - converted + pin.into() }); - let rx_pin = rx_pin.map(|pin| { + let rx_pin: Option> = rx_pin.map(|pin| { pin.as_rx(); - let converted: Peri<'a, AnyPin> = pin.into(); - converted + pin.into() }); - let rts_pin = rts_pin.map(|pin| { + let rts_pin: Option> = rts_pin.map(|pin| { pin.as_rts(); - let converted: Peri<'a, AnyPin> = pin.into(); - converted + pin.into() }); - let cts_pin = cts_pin.map(|pin| { + let cts_pin: Option> = cts_pin.map(|pin| { pin.as_cts(); - let converted: Peri<'a, AnyPin> = pin.into(); - converted + pin.into() }); let state = T::buffered_state(); diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index f069f6567..911c2a8e9 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -5,11 +5,12 @@ use paste::paste; use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig}; use crate::clocks::{enable_and_reset, ClockError, Gate, PoweredClock}; +use crate::gpio::SealedPin; use crate::pac::lpuart0::baud::Sbns as StopBits; use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; use crate::pac::lpuart0::stat::Msbf as MsbFirst; -use crate::{interrupt, pac}; +use crate::{interrupt, pac, AnyPin}; pub mod buffered; @@ -20,55 +21,6 @@ pub mod buffered; // Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API // Pin and Clock initialization is currently done at the examples level. -// --- START GPIO --- - -mod gpio { - use embassy_hal_internal::PeripheralType; - trait SealedPin {} - - #[allow(private_bounds)] - pub trait GpioPin: SealedPin + Sized + PeripheralType + Into + 'static { - /// Type-erase the pin. - fn degrade(self) -> AnyPin { - todo!() - } - } - - // Add this macro to implement GpioPin for all pins - macro_rules! impl_gpio_pin { - ($($pin:ident),*) => { - $( - impl SealedPin for crate::peripherals::$pin {} - - impl GpioPin for crate::peripherals::$pin {} - - impl From for AnyPin { - // TODO: AJM: any reason we aren't using $pin? - fn from(_val: crate::peripherals::$pin) -> Self { - AnyPin - } - } - )* - }; - } - - // Implement GpioPin for all pins from lib.rs - impl_gpio_pin!(P2_2, P2_3); - - #[derive(Debug, Clone, Copy)] - pub struct AnyPin; - - impl PeripheralType for AnyPin {} - - pub enum Alt { - ALT3, - } -} - -use gpio::{AnyPin, GpioPin as Pin}; - -// --- END GPIO --- - // --- START DMA --- mod dma { pub struct Channel<'d> { @@ -144,8 +96,7 @@ macro_rules! impl_instance { }; } -// impl_instance!(0, 1, 2, 3, 4); -impl_instance!(2); +impl_instance!(0, 1, 2, 3, 4, 5); // ============================================================================ // INSTANCE HELPER FUNCTIONS @@ -391,54 +342,184 @@ pub fn has_data(regs: Regs) -> bool { // PIN TRAITS FOR LPUART FUNCTIONALITY // ============================================================================ -impl sealed::Sealed for T {} +impl sealed::Sealed for T {} /// io configuration trait for Lpuart Tx configuration -pub trait TxPin: Pin + sealed::Sealed + PeripheralType { +pub trait TxPin: Into + sealed::Sealed + PeripheralType { /// convert the pin to appropriate function for Lpuart Tx usage fn as_tx(&self); } /// io configuration trait for Lpuart Rx configuration -pub trait RxPin: Pin + sealed::Sealed + PeripheralType { +pub trait RxPin: Into + sealed::Sealed + PeripheralType { /// convert the pin to appropriate function for Lpuart Rx usage fn as_rx(&self); } /// io configuration trait for Lpuart Cts -pub trait CtsPin: Pin + sealed::Sealed + PeripheralType { +pub trait CtsPin: Into + sealed::Sealed + PeripheralType { /// convert the pin to appropriate function for Lpuart Cts usage fn as_cts(&self); } /// io configuration trait for Lpuart Rts -pub trait RtsPin: Pin + sealed::Sealed + PeripheralType { +pub trait RtsPin: Into + sealed::Sealed + PeripheralType { /// convert the pin to appropriate function for Lpuart Rts usage fn as_rts(&self); } -macro_rules! impl_pin_trait { - ($fcn:ident, $mode:ident, $($pin:ident, $alt:ident),*) => { - paste! { - $( - impl [<$mode:camel Pin>] for crate::peripherals::$pin { - fn [](&self) { - let _alt = gpio::Alt::$alt; - // todo!("Configure pin for LPUART function") - } - } - )* +macro_rules! impl_tx_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl TxPin for crate::peripherals::$pin { + fn as_tx(&self) { + // TODO: Check these are right + self.set_pull(crate::gpio::Pull::Up); + self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); + self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); + self.set_function(crate::pac::port0::pcr0::Mux::$alt); + self.set_enable_input_buffer(); + } + } + }; +} + +macro_rules! impl_rx_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl RxPin for crate::peripherals::$pin { + fn as_rx(&self) { + // TODO: Check these are right + self.set_pull(crate::gpio::Pull::Up); + self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); + self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); + self.set_function(crate::pac::port0::pcr0::Mux::$alt); + self.set_enable_input_buffer(); + } + } + }; +} + +// TODO: Macro and impls for CTS/RTS pins +macro_rules! impl_cts_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl CtsPin for crate::peripherals::$pin { + fn as_cts(&self) { + todo!() + } + } + }; +} + +macro_rules! impl_rts_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl RtsPin for crate::peripherals::$pin { + fn as_rts(&self) { + todo!() + } } }; } -// Document identifier: MCXA343/344 Rev. 1DraftB ReleaseCandidate, 2025-07-10 - 6.1 MCX A173, A174 Signal Multiplexing and Pin Assignments -// impl_pin_trait!(LPUART0, rx, P2_0, ALT2, P0_2, ALT2, P0_20, ALT3); -// impl_pin_trait!(LPUART0, tx, P2_1, ALT2, P0_3, ALT2, P0_21, ALT3); -// impl_pin_trait!(LPUART0, rts, P2_2, ALT2, P0_0, ALT2, P0_22, ALT3); -// impl_pin_trait!(LPUART0, cts, P2_3, ALT2, P0_1, ALT2, P0_23, ALT3); -impl_pin_trait!(LPUART2, rx, P2_3, ALT3); -impl_pin_trait!(LPUART2, tx, P2_2, ALT3); +// LPUART 0 +impl_tx_pin!(LPUART0, P0_3, Mux2); +impl_tx_pin!(LPUART0, P0_21, Mux3); +impl_tx_pin!(LPUART0, P2_1, Mux2); + +impl_rx_pin!(LPUART0, P0_2, Mux2); +impl_rx_pin!(LPUART0, P0_20, Mux3); +impl_rx_pin!(LPUART0, P2_0, Mux2); + +impl_cts_pin!(LPUART0, P0_1, Mux2); +impl_cts_pin!(LPUART0, P0_23, Mux3); +impl_cts_pin!(LPUART0, P2_3, Mux2); + +impl_rts_pin!(LPUART0, P0_0, Mux2); +impl_rts_pin!(LPUART0, P0_22, Mux3); +impl_rts_pin!(LPUART0, P2_2, Mux2); + +// LPUART 1 +impl_tx_pin!(LPUART1, P1_9, Mux2); +impl_tx_pin!(LPUART1, P2_13, Mux3); +impl_tx_pin!(LPUART1, P3_9, Mux3); +impl_tx_pin!(LPUART1, P3_21, Mux3); + +impl_rx_pin!(LPUART1, P1_8, Mux2); +impl_rx_pin!(LPUART1, P2_12, Mux3); +impl_rx_pin!(LPUART1, P3_8, Mux3); +impl_rx_pin!(LPUART1, P3_20, Mux3); + +impl_cts_pin!(LPUART1, P1_11, Mux2); +impl_cts_pin!(LPUART1, P2_17, Mux3); +impl_cts_pin!(LPUART1, P3_11, Mux3); +impl_cts_pin!(LPUART1, P3_23, Mux3); + +impl_rts_pin!(LPUART1, P1_10, Mux2); +impl_rts_pin!(LPUART1, P2_15, Mux3); +impl_rts_pin!(LPUART1, P2_16, Mux3); +impl_rts_pin!(LPUART1, P3_10, Mux3); + +// LPUART 2 +impl_tx_pin!(LPUART2, P1_5, Mux3); +impl_tx_pin!(LPUART2, P1_13, Mux3); +impl_tx_pin!(LPUART2, P2_2, Mux3); +impl_tx_pin!(LPUART2, P2_10, Mux3); +impl_tx_pin!(LPUART2, P3_15, Mux2); + +impl_rx_pin!(LPUART2, P1_4, Mux3); +impl_rx_pin!(LPUART2, P1_12, Mux3); +impl_rx_pin!(LPUART2, P2_3, Mux3); +impl_rx_pin!(LPUART2, P2_11, Mux3); +impl_rx_pin!(LPUART2, P3_14, Mux2); + +impl_cts_pin!(LPUART2, P1_7, Mux3); +impl_cts_pin!(LPUART2, P1_15, Mux3); +impl_cts_pin!(LPUART2, P2_4, Mux3); +impl_cts_pin!(LPUART2, P3_13, Mux2); + +impl_rts_pin!(LPUART2, P1_6, Mux3); +impl_rts_pin!(LPUART2, P1_14, Mux3); +impl_rts_pin!(LPUART2, P2_5, Mux3); +impl_rts_pin!(LPUART2, P3_12, Mux2); + +// LPUART 3 +impl_tx_pin!(LPUART3, P3_1, Mux3); +impl_tx_pin!(LPUART3, P3_12, Mux3); +impl_tx_pin!(LPUART3, P4_5, Mux3); + +impl_rx_pin!(LPUART3, P3_0, Mux3); +impl_rx_pin!(LPUART3, P3_13, Mux3); +impl_rx_pin!(LPUART3, P4_2, Mux3); + +impl_cts_pin!(LPUART3, P3_7, Mux3); +impl_cts_pin!(LPUART3, P3_14, Mux3); +impl_cts_pin!(LPUART3, P4_6, Mux3); + +impl_rts_pin!(LPUART3, P3_6, Mux3); +impl_rts_pin!(LPUART3, P3_15, Mux3); +impl_rts_pin!(LPUART3, P4_7, Mux3); + +// LPUART 4 +impl_tx_pin!(LPUART4, P2_7, Mux3); +impl_tx_pin!(LPUART4, P3_19, Mux2); +impl_tx_pin!(LPUART4, P3_27, Mux3); +impl_tx_pin!(LPUART4, P4_3, Mux3); + +impl_rx_pin!(LPUART4, P2_6, Mux3); +impl_rx_pin!(LPUART4, P3_18, Mux2); +impl_rx_pin!(LPUART4, P3_28, Mux3); +impl_rx_pin!(LPUART4, P4_4, Mux3); + +impl_cts_pin!(LPUART4, P2_0, Mux3); +impl_cts_pin!(LPUART4, P3_17, Mux2); +impl_cts_pin!(LPUART4, P3_31, Mux3); + +impl_rts_pin!(LPUART4, P2_1, Mux3); +impl_rts_pin!(LPUART4, P3_16, Mux2); +impl_rts_pin!(LPUART4, P3_30, Mux3); + +// LPUART 5 +// +// TODO: The datasheet doesn't list tx/rx/cts/rts pins for LPUART5 +// See https://github.com/OpenDevicePartnership/embassy-mcxa/issues/48 // ============================================================================ // ERROR TYPES AND RESULTS diff --git a/src/pins.rs b/src/pins.rs index 0a83a41f0..fdf1b0a86 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -1,40 +1,6 @@ //! Pin configuration helpers (separate from peripheral drivers). use crate::pac; -pub unsafe fn configure_uart2_pins_port2() { - // P2_2 = LPUART2_TX ALT3, P2_3 = LPUART2_RX ALT3 with pull-up, input enable, high drive, slow slew. - let port2 = &*pac::Port2::ptr(); - port2.pcr2().write(|w| { - w.ps() - .ps1() - .pe() - .pe1() - .sre() - .sre1() - .dse() - .dse1() - .mux() - .mux3() - .ibe() - .ibe1() - }); - port2.pcr3().write(|w| { - w.ps() - .ps1() - .pe() - .pe1() - .sre() - .sre1() - .dse() - .dse1() - .mux() - .mux3() - .ibe() - .ibe1() - }); - core::arch::asm!("dsb sy; isb sy"); -} - pub unsafe fn configure_adc_pins() { // P1_10 = ADC1_A8 let port1 = &*pac::Port1::ptr(); -- cgit From 1efaaa4025120413ec17de90106244445208804a Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Tue, 25 Nov 2025 11:32:37 -0800 Subject: I2c Controller Blocking Driver (#27) * I2c Master Signed-off-by: Felipe Balbi * Fix review comments Signed-off-by: Felipe Balbi * More review comments Signed-off-by: Felipe Balbi --------- Signed-off-by: Felipe Balbi Co-authored-by: Felipe Balbi --- Cargo.lock | 1 + Cargo.toml | 2 +- examples/Cargo.lock | 532 +++++++++++++++++++++++++++++++++- examples/Cargo.toml | 1 + examples/src/bin/i2c-blocking.rs | 31 ++ examples/src/bin/i2c-scan-blocking.rs | 34 +++ src/clocks/mod.rs | 9 +- src/clocks/periph_helpers.rs | 113 ++++++++ src/i2c/controller.rs | 455 +++++++++++++++++++++++++++++ src/i2c/mod.rs | 171 +++++++++++ src/interrupt.rs | 4 +- src/lib.rs | 1 + 12 files changed, 1342 insertions(+), 12 deletions(-) create mode 100644 examples/src/bin/i2c-blocking.rs create mode 100644 examples/src/bin/i2c-scan-blocking.rs create mode 100644 src/i2c/controller.rs create mode 100644 src/i2c/mod.rs diff --git a/Cargo.lock b/Cargo.lock index 314120a47..a023fa268 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -329,6 +329,7 @@ dependencies = [ "cortex-m", "cortex-m-rt", "critical-section", + "defmt", "vcell", ] diff --git a/Cargo.toml b/Cargo.toml index bf46b3107..cda340d02 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -35,7 +35,7 @@ default = [] # Base defmt feature enables core + panic handler # Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) -defmt = ["dep:defmt"] +defmt = ["dep:defmt", "mcxa-pac/defmt"] rt = ["cortex-m-rt/device"] diff --git a/examples/Cargo.lock b/examples/Cargo.lock index 263807120..cda1f9ec8 100644 --- a/examples/Cargo.lock +++ b/examples/Cargo.lock @@ -2,6 +2,49 @@ # It is not intended for manual editing. version = 4 +[[package]] +name = "anyhow" +version = "1.0.100" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a23eb6b1614318a8071c9b2521f36b424b2c83db5eb3a0fead4a6c0809af6e61" + +[[package]] +name = "askama" +version = "0.14.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f75363874b771be265f4ffe307ca705ef6f3baa19011c149da8674a87f1b75c4" +dependencies = [ + "askama_derive", + "itoa", + "percent-encoding", + "serde", + "serde_json", +] + +[[package]] +name = "askama_derive" +version = "0.14.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "129397200fe83088e8a68407a8e2b1f826cf0086b21ccdb866a722c8bcd3a94f" +dependencies = [ + "askama_parser", + "memchr", + "proc-macro2", + "quote", + "rustc-hash", + "syn 2.0.110", +] + +[[package]] +name = "askama_parser" +version = "0.14.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d6ab5630b3d5eaf232620167977f95eb51f3432fc76852328774afbd242d4358" +dependencies = [ + "memchr", + "winnow 0.7.13", +] + [[package]] name = "autocfg" version = "1.5.0" @@ -29,6 +72,24 @@ version = "1.3.2" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" +[[package]] +name = "bitflags" +version = "2.10.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "812e12b5285cc515a9c72a5c1d3b6d46a19dac5acfef5265968c166106e31dd3" + +[[package]] +name = "bitvec" +version = "1.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1bc2832c24239b0141d5674bb9174f9d68a8b5b3f2753311927c172ca46f7e9c" +dependencies = [ + "funty", + "radium", + "tap", + "wyz", +] + [[package]] name = "byteorder" version = "1.5.0" @@ -41,6 +102,15 @@ version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" +[[package]] +name = "convert_case" +version = "0.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ec182b0ca2f35d8fc196cf3404988fd8b8c739a4d270ff118a398feb0cbec1ca" +dependencies = [ + "unicode-segmentation", +] + [[package]] name = "cortex-m" version = "0.7.7" @@ -71,7 +141,7 @@ checksum = "e37549a379a9e0e6e576fd208ee60394ccb8be963889eebba3ffe0980364f472" dependencies = [ "proc-macro2", "quote", - "syn", + "syn 2.0.110", ] [[package]] @@ -101,7 +171,7 @@ dependencies = [ "proc-macro2", "quote", "strsim", - "syn", + "syn 2.0.110", ] [[package]] @@ -112,7 +182,16 @@ checksum = "fc34b93ccb385b40dc71c6fceac4b2ad23662c7eeb248cf10d529b7e055b6ead" dependencies = [ "darling_core", "quote", - "syn", + "syn 2.0.110", +] + +[[package]] +name = "dd-manifest-tree" +version = "1.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5793572036e0a6638977c7370c6afc423eac848ee8495f079b8fd3964de7b9f9" +dependencies = [ + "toml", ] [[package]] @@ -121,7 +200,7 @@ version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "548d977b6da32fa1d1fda2876453da1e7df63ad0304c8b3dae4dbe7b96f39b78" dependencies = [ - "bitflags", + "bitflags 1.3.2", "defmt-macros", ] @@ -135,7 +214,7 @@ dependencies = [ "proc-macro-error2", "proc-macro2", "quote", - "syn", + "syn 2.0.110", ] [[package]] @@ -157,6 +236,46 @@ dependencies = [ "defmt", ] +[[package]] +name = "device-driver" +version = "1.0.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "af0e43acfcbb0bb3b7435cc1b1dbb33596cacfec1eb243336b74a398e0bd6cbf" +dependencies = [ + "device-driver-macros", + "embedded-io", + "embedded-io-async", +] + +[[package]] +name = "device-driver-generation" +version = "1.0.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3935aec9cf5bb2ab927f59ca69faecf976190390b0ce34c6023889e9041040c0" +dependencies = [ + "anyhow", + "askama", + "bitvec", + "convert_case", + "dd-manifest-tree", + "itertools", + "kdl", + "proc-macro2", + "quote", + "syn 2.0.110", +] + +[[package]] +name = "device-driver-macros" +version = "1.0.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4fdc68ed515c4eddff2e95371185b4becba066085bf36d50f07f09782af98e17" +dependencies = [ + "device-driver-generation", + "proc-macro2", + "syn 2.0.110", +] + [[package]] name = "document-features" version = "0.2.12" @@ -166,6 +285,12 @@ dependencies = [ "litrs", ] +[[package]] +name = "either" +version = "1.15.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "48c757948c5ede0e46177b7add2e67155f70e33c07fea8284df6576da70b3719" + [[package]] name = "embassy-embedded-hal" version = "0.5.0" @@ -205,7 +330,7 @@ dependencies = [ "darling", "proc-macro2", "quote", - "syn", + "syn 2.0.110", ] [[package]] @@ -274,6 +399,7 @@ dependencies = [ "embedded-io-async", "heapless 0.9.2", "panic-probe", + "tmp108", ] [[package]] @@ -380,12 +506,24 @@ dependencies = [ "embedded-storage", ] +[[package]] +name = "equivalent" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" + [[package]] name = "fnv" version = "1.0.7" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" +[[package]] +name = "funty" +version = "2.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e6d5a32815ae3f33302d95fdcb2ce17862f8c65363dcfd29360480ba1001fc9c" + [[package]] name = "futures-core" version = "0.3.31" @@ -407,6 +545,12 @@ dependencies = [ "byteorder", ] +[[package]] +name = "hashbrown" +version = "0.16.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5419bdc4f6a9207fbeba6d11b604d481addf78ecd10c11ad51e76c2f6482748d" + [[package]] name = "heapless" version = "0.8.0" @@ -433,12 +577,85 @@ version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39" +[[package]] +name = "indexmap" +version = "2.12.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6717a8d2a5a929a1a2eb43a12812498ed141a0bcfb7e8f7844fbdbe4303bba9f" +dependencies = [ + "equivalent", + "hashbrown", +] + +[[package]] +name = "itertools" +version = "0.14.0" +source = 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"registry+https://github.com/rust-lang/crates.io-index" +checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273" + +[[package]] +name = "miette" +version = "7.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f98efec8807c63c752b5bd61f862c165c115b0a35685bdcfd9238c7aeb592b7" +dependencies = [ + "cfg-if", + "unicode-width", +] + [[package]] name = "nb" version = "0.1.3" @@ -465,6 +699,70 @@ version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "8d5439c4ad607c3c23abf66de8c8bf57ba8adcd1f129e699851a6e43935d339d" +[[package]] +name = "num" +version = "0.4.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "35bd024e8b2ff75562e5f34e7f4905839deb4b22955ef5e73d2fea1b9813cb23" +dependencies = [ + "num-bigint", + "num-complex", + "num-integer", + "num-iter", + "num-rational", + "num-traits", +] + +[[package]] +name = "num-bigint" +version = "0.4.6" +source = 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"registry+https://github.com/rust-lang/crates.io-index" +checksum = "f83d14da390562dca69fc84082e73e548e1ad308d24accdedd2720017cb37824" +dependencies = [ + "num-bigint", + "num-integer", + "num-traits", +] + [[package]] name = "num-traits" version = "0.2.19" @@ -490,6 +788,12 @@ version = "1.0.15" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a" +[[package]] +name = "percent-encoding" +version = "2.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220" + [[package]] name = "proc-macro-error-attr2" version = "2.0.0" @@ -509,7 +813,18 @@ dependencies = [ "proc-macro-error-attr2", "proc-macro2", "quote", - "syn", + "syn 2.0.110", +] + +[[package]] +name = "proc-macro-utils" +version = "0.10.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "eeaf08a13de400bc215877b5bdc088f241b12eb42f0a548d3390dc1c56bb7071" +dependencies = [ + "proc-macro2", + "quote", + "smallvec", ] [[package]] @@ -521,6 +836,17 @@ dependencies = [ "unicode-ident", ] +[[package]] +name = "pulldown-cmark" +version = "0.11.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "679341d22c78c6c649893cbd6c3278dcbe9fc4faa62fea3a9296ae2b50c14625" +dependencies = [ + "bitflags 2.10.0", + "memchr", + "unicase", +] + [[package]] name = "quote" version = "1.0.42" @@ -530,6 +856,18 @@ dependencies = [ "proc-macro2", ] +[[package]] +name = "radium" +version = "0.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dc33ff2d4973d518d823d61aa239014831e521c75da58e3df4840d3f47749d09" + +[[package]] +name = "rustc-hash" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "357703d41365b4b27c590e3ed91eabb1b663f07c4c084095e60cbed4362dff0d" + [[package]] name = "rustc_version" version = "0.2.3" @@ -539,6 +877,12 @@ dependencies = [ "semver", ] +[[package]] +name = "ryu" +version = "1.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "28d3b2b1366ec20994f1fd18c3c594f05c5dd4bc44d8bb0c1c632c8d6829481f" + [[package]] name = "semver" version = "0.9.0" @@ -554,6 +898,63 @@ version = "0.7.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" +[[package]] +name = "serde" +version = "1.0.228" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e" +dependencies = [ + "serde_core", +] + +[[package]] +name = "serde_core" +version = "1.0.228" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad" +dependencies = [ + "serde_derive", +] + +[[package]] +name = "serde_derive" +version = "1.0.228" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.110", +] + +[[package]] +name = "serde_json" +version = "1.0.145" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "402a6f66d8c709116cf22f558eab210f5a50187f702eb4d7e5ef38d9a7f1c79c" +dependencies = [ + "itoa", + "memchr", + "ryu", + "serde", + "serde_core", +] + +[[package]] +name = "serde_spanned" +version = "0.6.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bf41e0cfaf7226dca15e8197172c295a782857fcb97fad1808a166870dee75a3" +dependencies = [ + "serde", +] + +[[package]] +name = "smallvec" +version = "1.15.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "67b1b7a3b5fe4f1376887184045fcf45c69e92af734b7aaddc05fb777b6fbd03" + [[package]] name = "stable_deref_trait" version = "1.2.1" @@ -566,6 +967,17 @@ version = "0.11.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" +[[package]] +name = "syn" +version = "1.0.109" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + [[package]] name = "syn" version = "2.0.110" @@ -577,6 +989,12 @@ dependencies = [ "unicode-ident", ] +[[package]] +name = "tap" +version = "1.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "55937e1799185b12863d447f42597ed69d9928686b8d88a1df17376a097d8369" + [[package]] name = "thiserror" version = "2.0.17" @@ -594,15 +1012,86 @@ checksum = "3ff15c8ecd7de3849db632e14d18d2571fa09dfc5ed93479bc4485c7a517c913" dependencies = [ "proc-macro2", "quote", - "syn", + "syn 2.0.110", +] + +[[package]] +name = "tmp108" +version = "0.4.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e0d644cc97d3cee96793f454b834881f78b5d4e89c90ecf26b3690f42004d111" +dependencies = [ + "device-driver", + "embedded-hal 1.0.0", + "maybe-async-cfg", +] + +[[package]] +name = "toml" +version = "0.8.23" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dc1beb996b9d83529a9e75c17a1686767d148d70663143c7854d8b4a09ced362" +dependencies = [ + "indexmap", + "serde", + "serde_spanned", + "toml_datetime", + "toml_edit", +] + +[[package]] +name = "toml_datetime" +version = "0.6.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "22cddaf88f4fbc13c51aebbf5f8eceb5c7c5a9da2ac40a13519eb5b0a0e8f11c" +dependencies = [ + "serde", ] +[[package]] +name = "toml_edit" +version = "0.22.27" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = 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+[[package]] +name = "unicode-width" +version = "0.1.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7dd6e30e90baa6f72411720665d41d89b9a3d039dc45b8faea1ddd07f617f6af" + [[package]] name = "vcell" version = "0.1.3" @@ -623,3 +1112,30 @@ checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc" dependencies = [ "vcell", ] + +[[package]] +name = "winnow" +version = "0.6.24" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c8d71a593cc5c42ad7876e2c1fda56f314f3754c084128833e64f1345ff8a03a" +dependencies = [ + "memchr", +] + +[[package]] +name = "winnow" +version = "0.7.13" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "21a0236b59786fed61e2a80582dd500fe61f18b5dca67a4a067d0bc9039339cf" +dependencies = [ + "memchr", +] + +[[package]] +name = "wyz" +version = "0.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "05f360fc0b24296329c78fda852a1e9ae82de9cf7b27dae4b7f62f118f77b9ed" +dependencies = [ + "tap", +] diff --git a/examples/Cargo.toml b/examples/Cargo.toml index 4f15a6aff..1022e91df 100644 --- a/examples/Cargo.toml +++ b/examples/Cargo.toml @@ -19,6 +19,7 @@ embassy-time-driver = "0.2.1" embedded-io-async = "0.6.1" heapless = "0.9.2" panic-probe = { version = "1.0", features = ["print-defmt"] } +tmp108 = "0.4.0" [profile.release] lto = true # better optimizations diff --git a/examples/src/bin/i2c-blocking.rs b/examples/src/bin/i2c-blocking.rs new file mode 100644 index 000000000..0f6c8cbae --- /dev/null +++ b/examples/src/bin/i2c-blocking.rs @@ -0,0 +1,31 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use tmp108::Tmp108; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + let i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap(); + let mut tmp = Tmp108::new_with_a0_gnd(i2c); + + loop { + let temperature = tmp.temperature().unwrap(); + defmt::info!("Temperature: {}C", temperature); + Timer::after_secs(1).await; + } +} diff --git a/examples/src/bin/i2c-scan-blocking.rs b/examples/src/bin/i2c-scan-blocking.rs new file mode 100644 index 000000000..6d1247e7a --- /dev/null +++ b/examples/src/bin/i2c-scan-blocking.rs @@ -0,0 +1,34 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + let mut i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap(); + + for addr in 0x01..=0x7f { + let result = i2c.blocking_write(addr, &[]); + if result.is_ok() { + defmt::info!("Device found at addr {:02x}", addr); + } + } + + loop { + Timer::after_secs(10).await; + } +} diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs index cd6318c4b..9c9e6ef3d 100644 --- a/src/clocks/mod.rs +++ b/src/clocks/mod.rs @@ -553,7 +553,7 @@ impl Clocks { return Err(ClockError::BadConfig { clock: "main_clk", reason: "not low power active", - }) + }); } } @@ -904,7 +904,7 @@ macro_rules! impl_cc_gate { pub(crate) mod gate { #[cfg(not(feature = "time"))] use super::periph_helpers::OsTimerConfig; - use super::periph_helpers::{AdcConfig, LpuartConfig, NoConfig}; + use super::periph_helpers::{AdcConfig, Lpi2cConfig, LpuartConfig, NoConfig}; use super::*; // These peripherals have no additional upstream clocks or configuration required @@ -928,6 +928,11 @@ pub(crate) mod gate { #[cfg(not(feature = "time"))] impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); + impl_cc_gate!(LPI2C0, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c0, Lpi2cConfig); + impl_cc_gate!(LPI2C1, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c1, Lpi2cConfig); + impl_cc_gate!(LPI2C2, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c2, Lpi2cConfig); + impl_cc_gate!(LPI2C3, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c3, Lpi2cConfig); + impl_cc_gate!(LPUART0, mrcc_glb_cc0, mrcc_glb_rst0, lpuart0, LpuartConfig); impl_cc_gate!(LPUART1, mrcc_glb_cc0, mrcc_glb_rst0, lpuart1, LpuartConfig); impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig); diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index eac3ef8dd..24d074e8a 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -123,6 +123,119 @@ impl SPConfHelper for NoConfig { } } +// +// LPI2c +// + +/// Selectable clocks for `Lpi2c` peripherals +#[derive(Debug, Clone, Copy)] +pub enum Lpi2cClockSel { + /// FRO12M/FRO_LF/SIRC clock source, passed through divider + /// "fro_lf_div" + FroLfDiv, + /// FRO180M/FRO_HF/FIRC clock source, passed through divider + /// "fro_hf_div" + FroHfDiv, + /// SOSC/XTAL/EXTAL clock source + ClkIn, + /// clk_1m/FRO_LF divided by 12 + Clk1M, + /// Output of PLL1, passed through clock divider, + /// "pll1_clk_div", maybe "pll1_lf_div"? + Pll1ClkDiv, + /// Disabled + None, +} + +/// Which instance of the `Lpi2c` is this? +/// +/// Should not be directly selectable by end-users. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum Lpi2cInstance { + /// Instance 0 + Lpi2c0, + /// Instance 1 + Lpi2c1, + /// Instance 2 + Lpi2c2, + /// Instance 3 + Lpi2c3, +} + +/// Top level configuration for `Lpi2c` instances. +pub struct Lpi2cConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Clock source + pub source: Lpi2cClockSel, + /// Clock divisor + pub div: Div4, + /// Which instance is this? + // NOTE: should not be user settable + pub(crate) instance: Lpi2cInstance, +} + +impl SPConfHelper for Lpi2cConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + // check that source is suitable + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + use mcxa_pac::mrcc0::mrcc_lpi2c0_clksel::Mux; + + let (clkdiv, clksel) = match self.instance { + Lpi2cInstance::Lpi2c0 => (mrcc0.mrcc_lpi2c0_clkdiv(), mrcc0.mrcc_lpi2c0_clksel()), + Lpi2cInstance::Lpi2c1 => (mrcc0.mrcc_lpi2c1_clkdiv(), mrcc0.mrcc_lpi2c1_clksel()), + Lpi2cInstance::Lpi2c2 => (mrcc0.mrcc_lpi2c2_clkdiv(), mrcc0.mrcc_lpi2c2_clksel()), + Lpi2cInstance::Lpi2c3 => (mrcc0.mrcc_lpi2c3_clkdiv(), mrcc0.mrcc_lpi2c3_clksel()), + }; + + let (freq, variant) = match self.source { + Lpi2cClockSel::FroLfDiv => { + let freq = clocks.ensure_fro_lf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc0) + } + Lpi2cClockSel::FroHfDiv => { + let freq = clocks.ensure_fro_hf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc2) + } + Lpi2cClockSel::ClkIn => { + let freq = clocks.ensure_clk_in_active(&self.power)?; + (freq, Mux::ClkrootFunc3) + } + Lpi2cClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + (freq, Mux::ClkrootFunc5) + } + Lpi2cClockSel::Pll1ClkDiv => { + let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; + (freq, Mux::ClkrootFunc6) + } + Lpi2cClockSel::None => unsafe { + // no ClkrootFunc7, just write manually for now + clksel.write(|w| w.bits(0b111)); + clkdiv.modify(|_r, w| w.reset().asserted().halt().asserted()); + return Ok(0); + }, + }; + + // set clksel + clksel.modify(|_r, w| w.mux().variant(variant)); + + // Set up clkdiv + clkdiv.modify(|_r, w| { + unsafe { w.div().bits(self.div.into_bits()) } + .halt() + .asserted() + .reset() + .asserted() + }); + clkdiv.modify(|_r, w| w.halt().deasserted().reset().deasserted()); + + while clkdiv.read().unstab().is_unstable() {} + + Ok(freq / self.div.into_divisor()) + } +} + // // LPUart // diff --git a/src/i2c/controller.rs b/src/i2c/controller.rs new file mode 100644 index 000000000..41bbc821d --- /dev/null +++ b/src/i2c/controller.rs @@ -0,0 +1,455 @@ +//! LPI2C controller driver + +use core::marker::PhantomData; + +use embassy_hal_internal::Peri; +use mcxa_pac::lpi2c0::mtdr::Cmd; + +use super::{Blocking, Error, Instance, Mode, Result, SclPin, SdaPin}; +use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig}; +use crate::clocks::{enable_and_reset, PoweredClock}; +use crate::AnyPin; + +/// Bus speed (nominal SCL, no clock stretching) +#[derive(Clone, Copy, Default, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Speed { + #[default] + /// 100 kbit/sec + Standard, + /// 400 kbit/sec + Fast, + /// 1 Mbit/sec + FastPlus, + /// 3.4 Mbit/sec + UltraFast, +} + +impl From for (u8, u8, u8, u8) { + fn from(value: Speed) -> (u8, u8, u8, u8) { + match value { + Speed::Standard => (0x3d, 0x37, 0x3b, 0x1d), + Speed::Fast => (0x0e, 0x0c, 0x0d, 0x06), + Speed::FastPlus => (0x04, 0x03, 0x03, 0x02), + + // UltraFast is "special". Leaving it unimplemented until + // the driver and the clock API is further stabilized. + Speed::UltraFast => todo!(), + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +enum SendStop { + No, + Yes, +} + +/// I2C controller configuration +#[derive(Clone, Copy, Default)] +#[non_exhaustive] +pub struct Config { + /// Bus speed + pub speed: Speed, +} + +/// I2C Controller Driver. +pub struct I2c<'d, T: Instance, M: Mode> { + _peri: Peri<'d, T>, + _scl: Peri<'d, AnyPin>, + _sda: Peri<'d, AnyPin>, + _phantom: PhantomData, + is_hs: bool, +} + +impl<'d, T: Instance> I2c<'d, T, Blocking> { + /// Create a new blocking instance of the I2C Controller bus driver. + pub fn new_blocking( + peri: Peri<'d, T>, + scl: Peri<'d, impl SclPin>, + sda: Peri<'d, impl SdaPin>, + config: Config, + ) -> Result { + Self::new_inner(peri, scl, sda, config) + } +} + +impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { + fn new_inner( + _peri: Peri<'d, T>, + scl: Peri<'d, impl SclPin>, + sda: Peri<'d, impl SdaPin>, + config: Config, + ) -> Result { + let (power, source, div) = Self::clock_config(config.speed); + + // Enable clocks + let conf = Lpi2cConfig { + power, + source, + div, + instance: T::CLOCK_INSTANCE, + }; + + _ = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; + + scl.mux(); + sda.mux(); + + let _scl = scl.into(); + let _sda = sda.into(); + + Self::set_config(&config)?; + + Ok(Self { + _peri, + _scl, + _sda, + _phantom: PhantomData, + is_hs: config.speed == Speed::UltraFast, + }) + } + + fn set_config(config: &Config) -> Result<()> { + // Disable the controller. + critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().disabled())); + + // Soft-reset the controller, read and write FIFOs. + critical_section::with(|_| { + T::regs() + .mcr() + .modify(|_, w| w.rst().reset().rtf().reset().rrf().reset()); + // According to Reference Manual section 40.7.1.4, "There + // is no minimum delay required before clearing the + // software reset", therefore we clear it immediately. + T::regs().mcr().modify(|_, w| w.rst().not_reset()); + + T::regs().mcr().modify(|_, w| w.dozen().clear_bit().dbgen().clear_bit()); + }); + + let (clklo, clkhi, sethold, datavd) = config.speed.into(); + + critical_section::with(|_| { + T::regs().mccr0().modify(|_, w| unsafe { + w.clklo() + .bits(clklo) + .clkhi() + .bits(clkhi) + .sethold() + .bits(sethold) + .datavd() + .bits(datavd) + }) + }); + + // Enable the controller. + critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().enabled())); + + // Clear all flags + T::regs().msr().write(|w| { + w.epf() + .clear_bit_by_one() + .sdf() + .clear_bit_by_one() + .ndf() + .clear_bit_by_one() + .alf() + .clear_bit_by_one() + .fef() + .clear_bit_by_one() + .pltf() + .clear_bit_by_one() + .dmf() + .clear_bit_by_one() + .stf() + .clear_bit_by_one() + }); + + Ok(()) + } + + // REVISIT: turn this into a function of the speed parameter + fn clock_config(speed: Speed) -> (PoweredClock, Lpi2cClockSel, Div4) { + match speed { + Speed::Standard | Speed::Fast | Speed::FastPlus => ( + PoweredClock::NormalEnabledDeepSleepDisabled, + Lpi2cClockSel::FroLfDiv, + const { Div4::no_div() }, + ), + Speed::UltraFast => ( + PoweredClock::NormalEnabledDeepSleepDisabled, + Lpi2cClockSel::FroHfDiv, + const { Div4::no_div() }, + ), + } + } + + fn is_tx_fifo_full(&mut self) -> bool { + let txfifo_size = 1 << T::regs().param().read().mtxfifo().bits(); + T::regs().mfsr().read().txcount().bits() == txfifo_size + } + + fn is_tx_fifo_empty(&mut self) -> bool { + T::regs().mfsr().read().txcount() == 0 + } + + fn is_rx_fifo_empty(&mut self) -> bool { + T::regs().mfsr().read().rxcount() == 0 + } + + fn status(&mut self) -> Result<()> { + // Wait for TxFIFO to be drained + while !self.is_tx_fifo_empty() {} + + let msr = T::regs().msr().read(); + T::regs().msr().write(|w| { + w.epf() + .clear_bit_by_one() + .sdf() + .clear_bit_by_one() + .ndf() + .clear_bit_by_one() + .alf() + .clear_bit_by_one() + .fef() + .clear_bit_by_one() + .fef() + .clear_bit_by_one() + .pltf() + .clear_bit_by_one() + .dmf() + .clear_bit_by_one() + .stf() + .clear_bit_by_one() + }); + + if msr.ndf().bit_is_set() { + Err(Error::AddressNack) + } else if msr.alf().bit_is_set() { + Err(Error::ArbitrationLoss) + } else { + Ok(()) + } + } + + fn send_cmd(&mut self, cmd: Cmd, data: u8) { + #[cfg(feature = "defmt")] + defmt::trace!( + "Sending cmd '{}' ({}) with data '{:08x}' MSR: {:08x}", + cmd, + cmd as u8, + data, + T::regs().msr().read().bits() + ); + + T::regs() + .mtdr() + .write(|w| unsafe { w.data().bits(data) }.cmd().variant(cmd)); + } + + fn start(&mut self, address: u8, read: bool) -> Result<()> { + if address >= 0x80 { + return Err(Error::AddressOutOfRange(address)); + } + + // Wait until we have space in the TxFIFO + while self.is_tx_fifo_full() {} + + let addr_rw = address << 1 | if read { 1 } else { 0 }; + self.send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); + + // Check controller status + self.status() + } + + fn stop(&mut self) -> Result<()> { + // Wait until we have space in the TxFIFO + while self.is_tx_fifo_full() {} + + self.send_cmd(Cmd::Stop, 0); + self.status() + } + + fn blocking_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { + self.start(address, true)?; + + if read.is_empty() { + return Err(Error::InvalidReadBufferLength); + } + + for chunk in read.chunks_mut(256) { + // Wait until we have space in the TxFIFO + while self.is_tx_fifo_full() {} + + self.send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); + + for byte in chunk.iter_mut() { + // Wait until there's data in the RxFIFO + while self.is_rx_fifo_empty() {} + + *byte = T::regs().mrdr().read().data().bits(); + } + + if send_stop == SendStop::Yes { + self.stop()?; + } + } + + Ok(()) + } + + fn blocking_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> { + self.start(address, false)?; + + // Usually, embassy HALs error out with an empty write, + // however empty writes are useful for writing I2C scanning + // logic through write probing. That is, we send a start with + // R/w bit cleared, but instead of writing any data, just send + // the stop onto the bus. This has the effect of checking if + // the resulting address got an ACK but causing no + // side-effects to the device on the other end. + // + // Because of this, we are not going to error out in case of + // empty writes. + #[cfg(feature = "defmt")] + if write.is_empty() { + defmt::trace!("Empty write, write probing?"); + } + + for byte in write { + // Wait until we have space in the TxFIFO + while self.is_tx_fifo_full() {} + + self.send_cmd(Cmd::Transmit, *byte); + } + + if send_stop == SendStop::Yes { + self.stop()?; + } + + Ok(()) + } + + // Public API: Blocking + + /// Read from address into buffer blocking caller until done. + pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<()> { + self.blocking_read_internal(address, read, SendStop::Yes) + // Automatic Stop + } + + /// Write to address from buffer blocking caller until done. + pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<()> { + self.blocking_write_internal(address, write, SendStop::Yes) + } + + /// Write to address from bytes and read from address into buffer blocking caller until done. + pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> { + self.blocking_write_internal(address, write, SendStop::No)?; + self.blocking_read_internal(address, read, SendStop::Yes) + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> { + type Error = Error; + + fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<()> { + self.blocking_read(address, buffer) + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> { + type Error = Error; + + fn write(&mut self, address: u8, bytes: &[u8]) -> Result<()> { + self.blocking_write(address, bytes) + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> { + type Error = Error; + + fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<()> { + self.blocking_write_read(address, bytes, buffer) + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Transactional for I2c<'d, T, M> { + type Error = Error; + + fn exec(&mut self, address: u8, operations: &mut [embedded_hal_02::blocking::i2c::Operation<'_>]) -> Result<()> { + if let Some((last, rest)) = operations.split_last_mut() { + for op in rest { + match op { + embedded_hal_02::blocking::i2c::Operation::Read(buf) => { + self.blocking_read_internal(address, buf, SendStop::No)? + } + embedded_hal_02::blocking::i2c::Operation::Write(buf) => { + self.blocking_write_internal(address, buf, SendStop::No)? + } + } + } + + match last { + embedded_hal_02::blocking::i2c::Operation::Read(buf) => { + self.blocking_read_internal(address, buf, SendStop::Yes) + } + embedded_hal_02::blocking::i2c::Operation::Write(buf) => { + self.blocking_write_internal(address, buf, SendStop::Yes) + } + } + } else { + Ok(()) + } + } +} + +impl embedded_hal_1::i2c::Error for Error { + fn kind(&self) -> embedded_hal_1::i2c::ErrorKind { + match *self { + Self::ArbitrationLoss => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss, + Self::AddressNack => { + embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address) + } + _ => embedded_hal_1::i2c::ErrorKind::Other, + } + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, T, M> { + type Error = Error; +} + +impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> { + fn transaction(&mut self, address: u8, operations: &mut [embedded_hal_1::i2c::Operation<'_>]) -> Result<()> { + if let Some((last, rest)) = operations.split_last_mut() { + for op in rest { + match op { + embedded_hal_1::i2c::Operation::Read(buf) => { + self.blocking_read_internal(address, buf, SendStop::No)? + } + embedded_hal_1::i2c::Operation::Write(buf) => { + self.blocking_write_internal(address, buf, SendStop::No)? + } + } + } + + match last { + embedded_hal_1::i2c::Operation::Read(buf) => self.blocking_read_internal(address, buf, SendStop::Yes), + embedded_hal_1::i2c::Operation::Write(buf) => self.blocking_write_internal(address, buf, SendStop::Yes), + } + } else { + Ok(()) + } + } +} + +impl<'d, T: Instance, M: Mode> embassy_embedded_hal::SetConfig for I2c<'d, T, M> { + type Config = Config; + type ConfigError = Error; + + fn set_config(&mut self, config: &Self::Config) -> Result<()> { + Self::set_config(config) + } +} diff --git a/src/i2c/mod.rs b/src/i2c/mod.rs new file mode 100644 index 000000000..a1f842029 --- /dev/null +++ b/src/i2c/mod.rs @@ -0,0 +1,171 @@ +//! I2C Support + +use core::marker::PhantomData; + +use embassy_hal_internal::PeripheralType; +use embassy_sync::waitqueue::AtomicWaker; +use paste::paste; + +use crate::clocks::periph_helpers::Lpi2cConfig; +use crate::clocks::{ClockError, Gate}; +use crate::gpio::{GpioPin, SealedPin}; +use crate::{interrupt, pac}; + +/// Shorthand for `Result`. +pub type Result = core::result::Result; + +pub mod controller; + +/// Error information type +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + /// Clock configuration error. + ClockSetup(ClockError), + /// Reading for I2C failed. + ReadFail, + /// Writing to I2C failed. + WriteFail, + /// I2C address NAK condition. + AddressNack, + /// Bus level arbitration loss. + ArbitrationLoss, + /// Address out of range. + AddressOutOfRange(u8), + /// Invalid write buffer length. + InvalidWriteBufferLength, + /// Invalid read buffer length. + InvalidReadBufferLength, + /// Other internal errors or unexpected state. + Other, +} + +/// I2C interrupt handler. +pub struct InterruptHandler { + _phantom: PhantomData, +} + +impl interrupt::typelevel::Handler for InterruptHandler { + unsafe fn on_interrupt() { + let waker = T::waker(); + + waker.wake(); + + todo!() + } +} + +mod sealed { + /// Seal a trait + pub trait Sealed {} +} + +impl sealed::Sealed for T {} + +trait SealedInstance { + fn regs() -> &'static pac::lpi2c0::RegisterBlock; + fn waker() -> &'static AtomicWaker; +} + +/// I2C Instance +#[allow(private_bounds)] +pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate { + /// Interrupt for this I2C instance. + type Interrupt: interrupt::typelevel::Interrupt; + /// Clock instance + const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance; +} + +macro_rules! impl_instance { + ($($n:expr),*) => { + $( + paste!{ + impl SealedInstance for crate::peripherals::[] { + fn regs() -> &'static pac::lpi2c0::RegisterBlock { + unsafe { &*pac::[]::ptr() } + } + + fn waker() -> &'static AtomicWaker { + static WAKER: AtomicWaker = AtomicWaker::new(); + &WAKER + } + } + + impl Instance for crate::peripherals::[] { + type Interrupt = crate::interrupt::typelevel::[]; + const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance + = crate::clocks::periph_helpers::Lpi2cInstance::[]; + } + } + )* + }; +} + +impl_instance!(0, 1, 2, 3); + +/// SCL pin trait. +pub trait SclPin: GpioPin + sealed::Sealed + PeripheralType { + fn mux(&self); +} + +/// SDA pin trait. +pub trait SdaPin: GpioPin + sealed::Sealed + PeripheralType { + fn mux(&self); +} + +/// Driver mode. +#[allow(private_bounds)] +pub trait Mode: sealed::Sealed {} + +/// Blocking mode. +pub struct Blocking; +impl sealed::Sealed for Blocking {} +impl Mode for Blocking {} + +/// Async mode. +pub struct Async; +impl sealed::Sealed for Async {} +impl Mode for Async {} + +macro_rules! impl_pin { + ($pin:ident, $peri:ident, $fn:ident, $trait:ident) => { + impl $trait for crate::peripherals::$pin { + fn mux(&self) { + self.set_pull(crate::gpio::Pull::Disabled); + self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); + self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); + self.set_function(crate::pac::port0::pcr0::Mux::$fn); + self.set_enable_input_buffer(); + } + } + }; +} + +impl_pin!(P0_16, LPI2C0, Mux2, SdaPin); +impl_pin!(P0_17, LPI2C0, Mux2, SclPin); +impl_pin!(P0_18, LPI2C0, Mux2, SclPin); +impl_pin!(P0_19, LPI2C0, Mux2, SdaPin); +impl_pin!(P1_0, LPI2C1, Mux3, SdaPin); +impl_pin!(P1_1, LPI2C1, Mux3, SclPin); +impl_pin!(P1_2, LPI2C1, Mux3, SdaPin); +impl_pin!(P1_3, LPI2C1, Mux3, SclPin); +impl_pin!(P1_8, LPI2C2, Mux3, SdaPin); +impl_pin!(P1_9, LPI2C2, Mux3, SclPin); +impl_pin!(P1_10, LPI2C2, Mux3, SdaPin); +impl_pin!(P1_11, LPI2C2, Mux3, SclPin); +impl_pin!(P1_12, LPI2C1, Mux2, SdaPin); +impl_pin!(P1_13, LPI2C1, Mux2, SclPin); +impl_pin!(P1_14, LPI2C1, Mux2, SclPin); +impl_pin!(P1_15, LPI2C1, Mux2, SdaPin); +impl_pin!(P1_30, LPI2C0, Mux3, SdaPin); +impl_pin!(P1_31, LPI2C0, Mux3, SclPin); +impl_pin!(P3_27, LPI2C3, Mux2, SclPin); +impl_pin!(P3_28, LPI2C3, Mux2, SdaPin); +// impl_pin!(P3_29, LPI2C3, Mux2, HreqPin); What is this HREQ pin? +impl_pin!(P3_30, LPI2C3, Mux2, SclPin); +impl_pin!(P3_31, LPI2C3, Mux2, SdaPin); +impl_pin!(P4_2, LPI2C2, Mux2, SdaPin); +impl_pin!(P4_3, LPI2C0, Mux2, SclPin); +impl_pin!(P4_4, LPI2C2, Mux2, SdaPin); +impl_pin!(P4_5, LPI2C0, Mux2, SclPin); +// impl_pin!(P4_6, LPI2C0, Mux2, HreqPin); What is this HREQ pin? diff --git a/src/interrupt.rs b/src/interrupt.rs index 4d409067a..f2f1cccac 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -7,7 +7,9 @@ #![allow(clippy::missing_safety_doc)] mod generated { - embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, RTC, ADC1,); + embassy_hal_internal::interrupt_mod!( + OS_EVENT, LPUART0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, RTC, ADC1, + ); } use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; diff --git a/src/lib.rs b/src/lib.rs index f9dda67d9..7fccc86c5 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -12,6 +12,7 @@ pub mod pins; // pin mux helpers pub mod adc; pub mod clkout; pub mod config; +pub mod i2c; pub mod interrupt; pub mod lpuart; pub mod ostimer; -- cgit From d12bc9785399991065e511efbea34f0138c7645e Mon Sep 17 00:00:00 2001 From: MathisDerooNXP <52401665+MathisDeroo@users.noreply.github.com> Date: Wed, 26 Nov 2025 10:05:16 -0800 Subject: Add GPIO interrupt support and embedded-hal-async trait implementation (#38) * Add GPIO interrupt support and embedded-hal-async trait implementation Signed-off-by: Mathis Deroo * Run cargo fmt * Improve GPIO driver interrupt mechanism and example - GPIO interrupt managed internally at the HAL level, - Renamed and cleaned gpio_interrupt example; now button_async.rs, - Use BitIter instead of simple for loop in the irq handler, - Fix comments and add "rt" wrappen to GPIO IRQ handler. Signed-off-by: Mathis Deroo * Modify INTERRUPT_DETECTED (AtomicBool to AtomicU32) to work with pin number and not only port number interrupt Signed-off-by: Mathis Deroo * add embedded_hal_async::digital::* traits Signed-off-by: Mathis Deroo * Update irq_handler with BitIter loop Co-authored-by: Felipe Balbi * Add suggested changes Signed-off-by: Mathis Deroo * cargo fmt Signed-off-by: Felipe Balbi * WIP: Modify Wakers from AtomicWaker to WaitMap, with pin number (per PORT) as key Signed-off-by: Mathis Deroo * Tweak maitake-sync usage * Improve docs * refactor a bit * Move all of the async+interrupt stuff into a module * Remove defmt debug traces Signed-off-by: Mathis Deroo * cargo vet * Move e-hal-async impls into the gated block * "rt", begone! --------- Signed-off-by: Mathis Deroo Signed-off-by: Felipe Balbi Co-authored-by: Felipe Balbi Co-authored-by: Felipe Balbi Co-authored-by: Felipe Balbi Co-authored-by: James Munns --- Cargo.lock | 426 +++++++++++++++++++++++++++++++++++ Cargo.toml | 6 +- examples/Cargo.lock | 414 ++++++++++++++++++++++++++++++++++ examples/Cargo.toml | 2 +- examples/src/bin/button_async.rs | 28 +++ src/config.rs | 2 + src/gpio.rs | 243 +++++++++++++++++++- src/interrupt.rs | 193 +++++++++++++++- src/lib.rs | 15 +- supply-chain/audits.toml | 216 ++++++++++++++++++ supply-chain/config.toml | 19 +- supply-chain/imports.lock | 465 ++++++++++++++++++++++++++++++++++++++- 12 files changed, 2005 insertions(+), 24 deletions(-) create mode 100644 examples/src/bin/button_async.rs diff --git a/Cargo.lock b/Cargo.lock index a023fa268..747a69c08 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -2,6 +2,15 @@ # It is not intended for manual editing. version = 4 +[[package]] +name = "aho-corasick" +version = "1.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" +dependencies = [ + "memchr", +] + [[package]] name = "autocfg" version = "1.5.0" @@ -35,12 +44,32 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"mcxa-pac", "nb 1.1.0", "paste", @@ -284,6 +314,12 @@ dependencies = [ "embedded-storage", ] +[[package]] +name = "find-msvc-tools" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3a3076410a55c90011c298b04d0cfa770b00fa04e1e3c97d3f6c9de105a03844" + [[package]] name = "futures-core" version = "0.3.31" @@ -296,6 +332,20 @@ version = "0.3.31" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e575fab7d1e0dcb8d0c7bcf9a63ee213816ab51902e6d244a95819acacf1d4f7" +[[package]] +name = "generator" +version = "0.8.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "605183a538e3e2a9c1038635cc5c2d194e2ee8fd0d1b66b8349fad7dbacce5a2" +dependencies = [ + "cc", + "cfg-if", + "libc", + "log", + "rustversion", + "windows", +] + [[package]] name = "hash32" version = "0.3.1" @@ -315,12 +365,68 @@ dependencies = [ "stable_deref_trait", ] +[[package]] +name = "lazy_static" +version = "1.5.0" +source = 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"regex-automata", + "sharded-slab", + "smallvec", + "thread_local", + "tracing", + "tracing-core", + "tracing-log", +] + [[package]] name = "unicode-ident" version = "1.0.22" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9312f7c4f6ff9069b165498234ce8be658059c6728633667c526e27dc2cf1df5" +[[package]] +name = "valuable" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ba73ea9cf16a25df0c8caa16c51acb937d5712a8429db78a3ee29d5dcacd3a65" + [[package]] name = "vcell" version = "0.1.3" @@ -490,3 +790,129 @@ checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc" dependencies = [ "vcell", ] + +[[package]] +name = "windows" +version = "0.61.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9babd3a767a4c1aef6900409f85f5d53ce2544ccdfaa86dad48c91782c6d6893" +dependencies = [ + "windows-collections", + "windows-core", + "windows-future", + "windows-link 0.1.3", + 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["critical-section", "no-cache-pad"] } # `time` dependencies embassy-time = { version = "0.5.0", optional = true } @@ -37,8 +39,6 @@ default = [] # Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) defmt = ["dep:defmt", "mcxa-pac/defmt"] -rt = ["cortex-m-rt/device"] - unstable-pac = [] # Embassy time diff --git a/examples/Cargo.lock b/examples/Cargo.lock index cda1f9ec8..c6e864df2 100644 --- a/examples/Cargo.lock +++ b/examples/Cargo.lock @@ -2,6 +2,15 @@ # It is not intended for manual editing. version = 4 +[[package]] +name = "aho-corasick" +version = "1.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" +dependencies = [ + "memchr", +] + [[package]] name = "anyhow" version = "1.0.100" @@ -96,6 +105,16 @@ version = "1.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b" +[[package]] +name = "cc" +version = "1.2.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cd405d82c84ff7f35739f175f67d8b9fb7687a0e84ccdc78bd3568839827cf07" +dependencies = [ + "find-msvc-tools", + "shlex", +] + [[package]] name = "cfg-if" version = "1.0.4" @@ -111,6 +130,16 @@ dependencies = [ "unicode-segmentation", ] +[[package]] +name = "cordyceps" +version = "0.3.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "688d7fbb8092b8de775ef2536f36c8c31f2bc4006ece2e8d8ad2d17d00ce0a2a" +dependencies = [ + "loom", + "tracing", +] + [[package]] name = "cortex-m" version = "0.7.7" @@ -376,6 +405,7 @@ dependencies = [ "embedded-io", "embedded-io-async", "heapless 0.8.0", + "maitake-sync", "mcxa-pac", "nb 1.1.0", "paste", @@ -512,6 +542,12 @@ version = "1.0.2" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" +[[package]] +name = "find-msvc-tools" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3a3076410a55c90011c298b04d0cfa770b00fa04e1e3c97d3f6c9de105a03844" + [[package]] name = "fnv" version = "1.0.7" @@ -536,6 +572,20 @@ version = "0.3.31" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e575fab7d1e0dcb8d0c7bcf9a63ee213816ab51902e6d244a95819acacf1d4f7" +[[package]] +name = "generator" +version = "0.8.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "605183a538e3e2a9c1038635cc5c2d194e2ee8fd0d1b66b8349fad7dbacce5a2" +dependencies = [ + "cc", + "cfg-if", + "libc", + "log", + "rustversion", + "windows", +] + [[package]] name = "hash32" version = "0.3.1" @@ -613,12 +663,59 @@ dependencies = [ "winnow 0.6.24", ] +[[package]] +name = "lazy_static" +version = "1.5.0" +source = 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"ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc" +dependencies = [ + "windows-link 0.2.1", +] + +[[package]] +name = "windows-threading" +version = "0.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b66463ad2e0ea3bbf808b7f1d371311c80e115c0b71d60efc142cafbcfb057a6" +dependencies = [ + "windows-link 0.1.3", +] + [[package]] name = "winnow" version = "0.6.24" diff --git a/examples/Cargo.toml b/examples/Cargo.toml index 1022e91df..a1092c416 100644 --- a/examples/Cargo.toml +++ b/examples/Cargo.toml @@ -12,7 +12,7 @@ defmt = "1.0" defmt-rtt = "1.0" embassy-embedded-hal = "0.5.0" embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } -embassy-mcxa = { path = "../", features = ["defmt", "rt", "unstable-pac", "time"] } +embassy-mcxa = { path = "../", features = ["defmt", "unstable-pac", "time"] } embassy-sync = "0.7.2" embassy-time = "0.5.0" embassy-time-driver = "0.2.1" diff --git a/examples/src/bin/button_async.rs b/examples/src/bin/button_async.rs new file mode 100644 index 000000000..1ecec2e48 --- /dev/null +++ b/examples/src/bin/button_async.rs @@ -0,0 +1,28 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{DriveStrength, Input, Pull, SlewRate}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("GPIO interrupt example"); + + // This button is labeled "WAKEUP" on the FRDM-MCXA276 + let mut pin = Input::new(p.P1_7, Pull::Up, DriveStrength::Normal, SlewRate::Fast); + + let mut press_count = 0u32; + + loop { + pin.wait_for_falling_edge().await; + + press_count += 1; + + defmt::info!("Button pressed! Count: {}", press_count); + Timer::after_millis(50).await; + } +} diff --git a/src/config.rs b/src/config.rs index 9c0d47ecb..8d52a1d44 100644 --- a/src/config.rs +++ b/src/config.rs @@ -9,6 +9,7 @@ pub struct Config { pub time_interrupt_priority: Priority, pub rtc_interrupt_priority: Priority, pub adc_interrupt_priority: Priority, + pub gpio_interrupt_priority: Priority, pub clock_cfg: ClocksConfig, } @@ -19,6 +20,7 @@ impl Default for Config { time_interrupt_priority: Priority::from(0), rtc_interrupt_priority: Priority::from(0), adc_interrupt_priority: Priority::from(0), + gpio_interrupt_priority: Priority::from(0), clock_cfg: ClocksConfig::default(), } } diff --git a/src/gpio.rs b/src/gpio.rs index 4f79aff93..332c4c8b2 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -3,13 +3,96 @@ //! concrete pin type. use core::convert::Infallible; +use core::future::Future; use core::marker::PhantomData; +use core::pin::pin; use embassy_hal_internal::{Peri, PeripheralType}; +use maitake_sync::WaitMap; use paste::paste; +use crate::pac::interrupt; use crate::pac::port0::pcr0::{Dse, Inv, Mux, Pe, Ps, Sre}; +struct BitIter(u32); + +impl Iterator for BitIter { + type Item = usize; + + fn next(&mut self) -> Option { + match self.0.trailing_zeros() { + 32 => None, + b => { + self.0 &= !(1 << b); + Some(b as usize) + } + } + } +} + +const PORT_COUNT: usize = 5; + +static PORT_WAIT_MAPS: [WaitMap; PORT_COUNT] = [ + WaitMap::new(), + WaitMap::new(), + WaitMap::new(), + WaitMap::new(), + WaitMap::new(), +]; + +fn irq_handler(port_index: usize, gpio_base: *const crate::pac::gpio0::RegisterBlock) { + let gpio = unsafe { &*gpio_base }; + let isfr = gpio.isfr0().read().bits(); + + for pin in BitIter(isfr) { + // Clear all pending interrupts + gpio.isfr0().write(|w| unsafe { w.bits(1 << pin) }); + gpio.icr(pin).modify(|_, w| w.irqc().irqc0()); // Disable interrupt + + // Wake the corresponding port waker + if let Some(w) = PORT_WAIT_MAPS.get(port_index) { + w.wake(&pin, ()); + } + } +} + +#[interrupt] +fn GPIO0() { + irq_handler(0, crate::pac::Gpio0::ptr()); +} + +#[interrupt] +fn GPIO1() { + irq_handler(1, crate::pac::Gpio1::ptr()); +} + +#[interrupt] +fn GPIO2() { + irq_handler(2, crate::pac::Gpio2::ptr()); +} + +#[interrupt] +fn GPIO3() { + irq_handler(3, crate::pac::Gpio3::ptr()); +} + +#[interrupt] +fn GPIO4() { + irq_handler(4, crate::pac::Gpio4::ptr()); +} + +pub(crate) unsafe fn init() { + use embassy_hal_internal::interrupt::InterruptExt; + + crate::pac::interrupt::GPIO0.enable(); + crate::pac::interrupt::GPIO1.enable(); + crate::pac::interrupt::GPIO2.enable(); + crate::pac::interrupt::GPIO3.enable(); + crate::pac::interrupt::GPIO4.enable(); + + cortex_m::interrupt::enable(); +} + /// Logical level for GPIO pins. #[derive(Copy, Clone, Eq, PartialEq, Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -598,6 +681,77 @@ impl<'d> Flex<'d> { } } +/// Async methods +impl<'d> Flex<'d> { + /// Helper function that waits for a given interrupt trigger + async fn wait_for_inner(&mut self, level: crate::pac::gpio0::icr::Irqc) { + // First, ensure that we have a waker that is ready for this port+pin + let w = PORT_WAIT_MAPS[self.pin.port].wait(self.pin.pin); + let mut w = pin!(w); + // Wait for the subscription to occur, which requires polling at least once + // + // This function returns a result, but can only be an Err if: + // + // * We call `.close()` on a WaitMap, which we never do + // * We have a duplicate key, which can't happen because `wait_for_*` methods + // take an &mut ref of their unique port+pin combo + // + // So we wait for it to complete, but ignore the result. + _ = w.as_mut().subscribe().await; + + // Now that our waker is in the map, we can enable the appropriate interrupt + // + // Clear any existing pending interrupt on this pin + self.pin + .gpio() + .isfr0() + .write(|w| unsafe { w.bits(1 << self.pin.pin()) }); + self.pin.gpio().icr(self.pin.pin()).write(|w| w.isf().isf1()); + + // Pin interrupt configuration + self.pin + .gpio() + .icr(self.pin.pin()) + .modify(|_, w| w.irqc().variant(level)); + + // Finally, we can await the matching call to `.wake()` from the interrupt. + // + // Again, technically, this could return a result, but for the same reasons + // as above, this can't be an error in our case, so just wait for it to complete + _ = w.await; + } + + /// Wait until the pin is high. If it is already high, return immediately. + #[inline] + pub fn wait_for_high(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc12) + } + + /// Wait until the pin is low. If it is already low, return immediately. + #[inline] + pub fn wait_for_low(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc8) + } + + /// Wait for the pin to undergo a transition from low to high. + #[inline] + pub fn wait_for_rising_edge(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc9) + } + + /// Wait for the pin to undergo a transition from high to low. + #[inline] + pub fn wait_for_falling_edge(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc10) + } + + /// Wait for the pin to undergo any transition, i.e low to high OR high to low. + #[inline] + pub fn wait_for_any_edge(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc11) + } +} + /// GPIO output driver that owns a `Flex` pin. pub struct Output<'d> { flex: Flex<'d>, @@ -691,12 +845,99 @@ impl<'d> Input<'d> { self.flex } - // Get the pin level. + /// Get the pin level. pub fn get_level(&self) -> Level { self.flex.get_level() } } +/// Async methods +impl<'d> Input<'d> { + /// Wait until the pin is high. If it is already high, return immediately. + #[inline] + pub fn wait_for_high(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_high() + } + + /// Wait until the pin is low. If it is already low, return immediately. + #[inline] + pub fn wait_for_low(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_low() + } + + /// Wait for the pin to undergo a transition from low to high. + #[inline] + pub fn wait_for_rising_edge(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_rising_edge() + } + + /// Wait for the pin to undergo a transition from high to low. + #[inline] + pub fn wait_for_falling_edge(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_falling_edge() + } + + /// Wait for the pin to undergo any transition, i.e low to high OR high to low. + #[inline] + pub fn wait_for_any_edge(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_any_edge() + } +} + +impl embedded_hal_async::digital::Wait for Input<'_> { + async fn wait_for_high(&mut self) -> Result<(), Self::Error> { + self.wait_for_high().await; + Ok(()) + } + + async fn wait_for_low(&mut self) -> Result<(), Self::Error> { + self.wait_for_low().await; + Ok(()) + } + + async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_rising_edge().await; + Ok(()) + } + + async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_falling_edge().await; + Ok(()) + } + + async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_any_edge().await; + Ok(()) + } +} + +impl embedded_hal_async::digital::Wait for Flex<'_> { + async fn wait_for_high(&mut self) -> Result<(), Self::Error> { + self.wait_for_high().await; + Ok(()) + } + + async fn wait_for_low(&mut self) -> Result<(), Self::Error> { + self.wait_for_low().await; + Ok(()) + } + + async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_rising_edge().await; + Ok(()) + } + + async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_falling_edge().await; + Ok(()) + } + + async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_any_edge().await; + Ok(()) + } +} + // Both embedded_hal 0.2 and 1.0 must be supported by embassy HALs. impl embedded_hal_02::digital::v2::InputPin for Flex<'_> { // GPIO operations on this block cannot fail, therefor we set the error type diff --git a/src/interrupt.rs b/src/interrupt.rs index f2f1cccac..0490e3a66 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -8,7 +8,8 @@ mod generated { embassy_hal_internal::interrupt_mod!( - OS_EVENT, LPUART0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, RTC, ADC1, + OS_EVENT, RTC, ADC1, GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPUART0, LPUART1, + LPUART2, LPUART3, LPUART4, LPUART5, ); } @@ -292,6 +293,196 @@ impl InterruptExt for Adc { } } +pub struct Gpio0; +pub const GPIO0: Gpio0 = Gpio0; + +impl InterruptExt for Gpio0 { + /// Clear any pending GPIO0 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO0); + } + + /// Set NVIC priority for GPIO0. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO0, u8::from(priority)); + } + } + + /// Enable GPIO0 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO0); + } + + /// Disable GPIO0 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO0); + } + + /// Check if GPIO0 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO0) + } +} + +pub struct Gpio1; +pub const GPIO1: Gpio1 = Gpio1; + +impl InterruptExt for Gpio1 { + /// Clear any pending GPIO1 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO1); + } + + /// Set NVIC priority for GPIO1. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO1, u8::from(priority)); + } + } + + /// Enable GPIO1 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO1); + } + + /// Disable GPIO1 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO1); + } + + /// Check if GPIO1 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO1) + } +} + +pub struct Gpio2; +pub const GPIO2: Gpio2 = Gpio2; + +impl InterruptExt for Gpio2 { + /// Clear any pending GPIO2 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO2); + } + + /// Set NVIC priority for GPIO2. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO2, u8::from(priority)); + } + } + + /// Enable GPIO2 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO2); + } + + /// Disable GPIO2 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO2); + } + + /// Check if GPIO2 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO2) + } +} + +pub struct Gpio3; +pub const GPIO3: Gpio3 = Gpio3; + +impl InterruptExt for Gpio3 { + /// Clear any pending GPIO3 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO3); + } + + /// Set NVIC priority for GPIO3. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO3, u8::from(priority)); + } + } + + /// Enable GPIO3 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO3); + } + + /// Disable GPIO3 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO3); + } + + /// Check if GPIO3 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO3) + } +} + +pub struct Gpio4; +pub const GPIO4: Gpio4 = Gpio4; + +impl InterruptExt for Gpio4 { + /// Clear any pending GPIO4 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO4); + } + + /// Set NVIC priority for GPIO4. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO4, u8::from(priority)); + } + } + + /// Enable GPIO4 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO4); + } + + /// Disable GPIO4 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO4); + } + + /// Check if GPIO4 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO4) + } +} + /// Set VTOR (Vector Table Offset) to a RAM-based vector table. /// Pass a pointer to the first word in the RAM table (stack pointer slot 0). /// Safety: Caller must ensure the RAM table is valid and aligned as required by the core. diff --git a/src/lib.rs b/src/lib.rs index 7fccc86c5..fb204d27b 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -18,7 +18,6 @@ pub mod lpuart; pub mod ostimer; pub mod rtc; -#[cfg(feature = "rt")] pub use crate::pac::NVIC_PRIO_BITS; #[rustfmt::skip] @@ -347,10 +346,24 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); // Apply user-configured priority early; enabling is left to examples/apps crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO0.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO1.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO2.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO3.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO4.set_priority(cfg.gpio_interrupt_priority); // Configure clocks crate::clocks::init(cfg.clock_cfg).unwrap(); + unsafe { + crate::gpio::init(); + } + // Initialize embassy-time global driver backed by OSTIMER0 #[cfg(feature = "time")] crate::ostimer::time_driver::init(crate::config::Config::default().time_interrupt_priority, 1_000_000); diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml index 2aba6b961..871109648 100644 --- a/supply-chain/audits.toml +++ b/supply-chain/audits.toml @@ -6,11 +6,21 @@ who = "Felipe Balbi " criteria = "safe-to-deploy" version = "1.5.0" +[[audits.cc]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.2.47" + [[audits.cfg-if]] who = "Felipe Balbi " criteria = "safe-to-deploy" version = "1.0.4" +[[audits.cordyceps]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.3.4" + [[audits.darling]] who = "Felipe Balbi " criteria = "safe-to-deploy" @@ -72,6 +82,16 @@ who = "Felipe Balbi " criteria = "safe-to-deploy" version = "0.3.0" +[[audits.find-msvc-tools]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.5" + +[[audits.generator]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.8.7" + [[audits.ident_case]] who = "Felipe Balbi " criteria = "safe-to-deploy" @@ -82,11 +102,46 @@ who = "Felipe Balbi " criteria = "safe-to-deploy" version = "1.0.0" +[[audits.maitake-sync]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.2.2" + +[[audits.mutex-traits]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.1" + +[[audits.mycelium-bitfield]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.5" + +[[audits.once_cell]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.20.1" + [[audits.panic-probe]] who = "Felipe Balbi " criteria = "safe-to-deploy" version = "1.0.0" +[[audits.pin-project]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.1.10" + +[[audits.pin-project-internal]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.1.10" + +[[audits.portable-atomic]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.11.1" + [[audits.proc-macro2]] who = "Felipe Balbi " criteria = "safe-to-deploy" @@ -131,3 +186,164 @@ version = "2.0.17" who = "Felipe Balbi " criteria = "safe-to-deploy" version = "1.0.22" + +[[audits.valuable]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.1" + +[[trusted.aho-corasick]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-03-28" +end = "2026-11-26" + +[[trusted.cc]] +criteria = "safe-to-deploy" +user-id = 55123 # rust-lang-owner +start = "2022-10-29" +end = "2026-11-26" + +[[trusted.find-msvc-tools]] +criteria = "safe-to-deploy" +user-id = 539 +start = "2025-08-29" +end = "2026-11-26" + +[[trusted.libc]] +criteria = "safe-to-deploy" +user-id = 55123 # rust-lang-owner +start = "2024-08-15" +end = "2026-11-26" + +[[trusted.loom]] +criteria = "safe-to-deploy" +user-id = 6741 # Alice Ryhl (Darksonn) +start = "2021-04-12" +end = "2026-11-26" + +[[trusted.memchr]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-07-07" +end = "2026-11-26" + +[[trusted.paste]] +criteria = "safe-to-deploy" +user-id = 3618 # David Tolnay (dtolnay) +start = "2019-03-19" +end = "2026-11-26" + +[[trusted.regex-automata]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-02-25" +end = "2026-11-26" + +[[trusted.regex-syntax]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-03-30" +end = "2026-11-26" + +[[trusted.rustversion]] +criteria = "safe-to-deploy" +user-id = 3618 # David Tolnay (dtolnay) +start = "2019-07-08" +end = "2026-11-26" + +[[trusted.scoped-tls]] +criteria = "safe-to-deploy" +user-id = 1 # Alex Crichton (alexcrichton) +start = "2019-02-26" +end = "2026-11-26" + +[[trusted.thread_local]] +criteria = "safe-to-deploy" +user-id = 2915 # Amanieu d'Antras (Amanieu) +start = "2019-09-07" +end = "2026-11-26" + +[[trusted.tracing-subscriber]] +criteria = "safe-to-deploy" +user-id = 10 # Carl Lerche (carllerche) +start = "2025-08-29" +end = "2026-11-26" + +[[trusted.valuable]] +criteria = "safe-to-deploy" +user-id = 10 # Carl Lerche (carllerche) +start = "2022-01-03" +end = "2026-11-26" + +[[trusted.windows]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2021-01-15" +end = "2026-11-26" + +[[trusted.windows-collections]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2025-02-06" +end = "2026-11-26" + +[[trusted.windows-core]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2021-11-15" +end = "2026-11-26" + +[[trusted.windows-future]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2025-02-10" +end = "2026-11-26" + +[[trusted.windows-implement]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2022-01-27" +end = "2026-11-26" + +[[trusted.windows-interface]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2022-02-18" +end = "2026-11-26" + +[[trusted.windows-link]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2024-07-17" +end = "2026-11-26" + +[[trusted.windows-numerics]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2023-05-15" +end = "2026-11-26" + +[[trusted.windows-result]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2024-02-02" +end = "2026-11-26" + +[[trusted.windows-strings]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2024-02-02" +end = "2026-11-26" + +[[trusted.windows-sys]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2021-11-15" +end = "2026-11-26" + +[[trusted.windows-threading]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2025-04-29" +end = "2026-11-26" diff --git a/supply-chain/config.toml b/supply-chain/config.toml index 173392c16..5682db9ea 100644 --- a/supply-chain/config.toml +++ b/supply-chain/config.toml @@ -7,6 +7,9 @@ version = "0.10" [imports.OpenDevicePartnership] url = "https://raw.githubusercontent.com/OpenDevicePartnership/rust-crate-audits/main/audits.toml" +[imports.bytecode-alliance] +url = "https://raw.githubusercontent.com/bytecodealliance/wasmtime/main/supply-chain/audits.toml" + [imports.google] url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" @@ -89,10 +92,6 @@ criteria = "safe-to-deploy" version = "1.0.0" criteria = "safe-to-deploy" -[[exemptions.embedded-io]] -version = "0.6.1" -criteria = "safe-to-deploy" - [[exemptions.embedded-io-async]] version = "0.6.1" criteria = "safe-to-deploy" @@ -105,14 +104,6 @@ criteria = "safe-to-deploy" version = "0.4.1" criteria = "safe-to-deploy" -[[exemptions.futures-core]] -version = "0.3.31" -criteria = "safe-to-deploy" - -[[exemptions.futures-sink]] -version = "0.3.31" -criteria = "safe-to-deploy" - [[exemptions.hash32]] version = "0.3.1" criteria = "safe-to-deploy" @@ -121,10 +112,6 @@ criteria = "safe-to-deploy" version = "0.8.0" criteria = "safe-to-deploy" -[[exemptions.paste]] -version = "1.0.15" -criteria = "safe-to-deploy" - [[exemptions.proc-macro-error-attr2]] version = "2.0.0" criteria = "safe-to-deploy" diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock index aa62839e2..dbd1235b0 100644 --- a/supply-chain/imports.lock +++ b/supply-chain/imports.lock @@ -1,8 +1,288 @@ # cargo-vet imports lock +[[publisher.aho-corasick]] +version = "1.1.4" +when = "2025-10-28" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.libc]] +version = "0.2.177" +when = "2025-10-09" +user-id = 55123 +user-login = "rust-lang-owner" + +[[publisher.loom]] +version = "0.7.2" +when = "2024-04-23" +user-id = 6741 +user-login = "Darksonn" +user-name = "Alice Ryhl" + +[[publisher.memchr]] +version = "2.7.6" +when = "2025-09-25" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.paste]] +version = "1.0.15" +when = "2024-05-07" +user-id = 3618 +user-login = "dtolnay" +user-name = "David Tolnay" + +[[publisher.regex-automata]] +version = "0.4.13" +when = "2025-10-13" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.regex-syntax]] +version = "0.8.8" +when = "2025-10-13" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.rustversion]] +version = "1.0.22" +when = "2025-08-08" +user-id = 3618 +user-login = "dtolnay" +user-name = "David Tolnay" + +[[publisher.scoped-tls]] +version = "1.0.1" +when = "2022-10-31" +user-id = 1 +user-login = "alexcrichton" +user-name = "Alex Crichton" + +[[publisher.thread_local]] +version = "1.1.9" +when = "2025-06-12" +user-id = 2915 +user-login = "Amanieu" +user-name = "Amanieu d'Antras" + +[[publisher.tracing-subscriber]] +version = "0.3.20" +when = "2025-08-29" +user-id = 10 +user-login = "carllerche" +user-name = "Carl Lerche" + +[[publisher.windows]] +version = "0.61.3" +when = "2025-06-12" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-collections]] +version = "0.2.0" +when = "2025-03-18" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-core]] +version = "0.61.2" +when = "2025-05-19" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-future]] +version = "0.2.1" +when = "2025-05-15" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-implement]] +version = "0.60.2" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-interface]] +version = "0.59.3" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-link]] +version = "0.1.3" +when = "2025-06-12" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-link]] +version = "0.2.1" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-numerics]] +version = "0.2.0" +when = "2025-03-18" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-result]] +version = "0.3.4" +when = "2025-05-19" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-strings]] +version = "0.4.2" +when = "2025-05-19" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-sys]] +version = "0.61.2" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-threading]] +version = "0.1.0" +when = "2025-05-15" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + [audits.OpenDevicePartnership.audits] +[[audits.bytecode-alliance.audits.embedded-io]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "0.4.0" +notes = "No `unsafe` code and only uses `std` in ways one would expect the crate to do so." + +[[audits.bytecode-alliance.audits.embedded-io]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.0 -> 0.6.1" +notes = "Major updates, but almost all safe code. Lots of pruning/deletions, nothing out of the ordrinary." + +[[audits.bytecode-alliance.audits.futures-core]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.3.27" +notes = "Unsafe used to implement a concurrency primitive AtomicWaker. Well-commented and not obviously incorrect. Like my other audits of these concurrency primitives inside the futures family, I couldn't certify that it is correct without formal methods, but that is out of scope for this vetting." + +[[audits.bytecode-alliance.audits.futures-core]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +delta = "0.3.28 -> 0.3.31" + +[[audits.bytecode-alliance.audits.futures-sink]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.3.27" + +[[audits.bytecode-alliance.audits.futures-sink]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +delta = "0.3.28 -> 0.3.31" + +[[audits.bytecode-alliance.audits.log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.22 -> 0.4.27" +notes = "Lots of minor updates to macros and such, nothing touching `unsafe`" + +[[audits.bytecode-alliance.audits.log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.27 -> 0.4.28" +notes = "Minor doc updates and lots new tests, nothing out of the ordinary." + +[[audits.bytecode-alliance.audits.matchers]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.1.0" + +[[audits.bytecode-alliance.audits.matchers]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.0 -> 0.2.0" +notes = "Some unsafe code, but not more than before. Nothing awry." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.46.0" +notes = "one use of unsafe to call windows specific api to get console handle." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.46.0 -> 0.50.1" +notes = "Lots of stylistic/rust-related chanegs, plus new features, but nothing out of the ordrinary." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.50.1 -> 0.50.3" +notes = "CI changes, Rust changes, nothing out of the ordinary." + +[[audits.bytecode-alliance.audits.sharded-slab]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.1.4" +notes = "I always really enjoy reading eliza's code, she left perfect comments at every use of unsafe." + +[[audits.bytecode-alliance.audits.shlex]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "1.1.0" +notes = "Only minor `unsafe` code blocks which look valid and otherwise does what it says on the tin." + +[[audits.bytecode-alliance.audits.tracing-attributes]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.28 -> 0.1.30" +notes = "Few code changes, a pretty minor update." + +[[audits.bytecode-alliance.audits.tracing-core]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.33 -> 0.1.34" +notes = "Mostly just an update with Rust stylistic conventions changing. Nothing awry." + +[[audits.bytecode-alliance.audits.tracing-log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "0.1.3" +notes = """ +This is a standard adapter between the `log` ecosystem and the `tracing` +ecosystem. There's one `unsafe` block in this crate and it's well-scoped. +""" + +[[audits.bytecode-alliance.audits.tracing-log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.3 -> 0.2.0" +notes = "Nothing out of the ordinary, a typical major version update and nothing awry." + [[audits.google.audits.bitflags]] who = "Lukasz Anforowicz " criteria = "safe-to-deploy" @@ -26,6 +306,39 @@ version = "1.5.0" notes = "Unsafe review in https://crrev.com/c/5838022" aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" +[[audits.google.audits.lazy_static]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.4.0" +notes = ''' +I grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits. + +There are two places where `unsafe` is used. Unsafe review notes can be found +in https://crrev.com/c/5347418. + +This crate has been added to Chromium in https://crrev.com/c/3321895. +''' +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.lazy_static]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.4.0 -> 1.5.0" +notes = "Unsafe review notes: https://crrev.com/c/5650836" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.log]] +who = "danakj " +criteria = "safe-to-deploy" +version = "0.4.22" +notes = """ +Unsafe review in https://docs.google.com/document/d/1IXQbD1GhTRqNHIGxq6yy7qHqxeO4CwN5noMFXnqyDIM/edit?usp=sharing + +Unsafety is generally very well-documented, with one exception, which we +describe in the review doc. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + [[audits.google.audits.nb]] who = "George Burgess IV " criteria = "safe-to-deploy" @@ -51,10 +364,160 @@ version = "0.2.19" notes = "Contains a single line of float-to-int unsafe with decent safety comments" aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" +[[audits.google.audits.pin-project-lite]] +who = "David Koloski " +criteria = "safe-to-deploy" +version = "0.2.9" +notes = "Reviewed on https://fxrev.dev/824504" +aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.pin-project-lite]] +who = "David Koloski " +criteria = "safe-to-deploy" +delta = "0.2.9 -> 0.2.13" +notes = "Audited at https://fxrev.dev/946396" +aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.smallvec]] +who = "Manish Goregaokar " +criteria = "safe-to-deploy" +version = "1.13.2" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.smallvec]] +who = "Jonathan Hao " +criteria = "safe-to-deploy" +delta = "1.13.2 -> 1.14.0" +notes = """ +WARNING: This certification is a result of a **partial** audit. The +`malloc_size_of` feature has **not** been audited. This feature does +not explicitly document its safety requirements. +See also https://chromium-review.googlesource.com/c/chromium/src/+/6275133/comment/ea0d7a93_98051a2e/ +and https://github.com/servo/malloc_size_of/issues/8. +This feature is banned in gnrt_config.toml. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + [[audits.google.audits.void]] who = "George Burgess IV " criteria = "safe-to-deploy" version = "1.0.2" aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" -[audits.mozilla.audits] +[[audits.mozilla.audits.futures-core]] +who = "Mike Hommey " +criteria = "safe-to-deploy" +delta = "0.3.27 -> 0.3.28" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.futures-sink]] +who = "Mike Hommey " +criteria = "safe-to-deploy" +delta = "0.3.27 -> 0.3.28" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.20.1 -> 1.20.2" +notes = "This update works around a Cargo bug that forces the addition of `portable-atomic` into a lockfile, which we have never needed to use." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.20.2 -> 1.20.3" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.20.3 -> 1.21.1" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.21.1 -> 1.21.3" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.pin-project-lite]] +who = "Mike Hommey " +criteria = "safe-to-deploy" +delta = "0.2.13 -> 0.2.14" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.pin-project-lite]] +who = "Nika Layzell " +criteria = "safe-to-deploy" +delta = "0.2.14 -> 0.2.16" +notes = """ +Only functional change is to work around a bug in the negative_impls feature +(https://github.com/taiki-e/pin-project/issues/340#issuecomment-2432146009) +""" +aggregated-from = "https://raw.githubusercontent.com/mozilla/cargo-vet/main/supply-chain/audits.toml" + +[[audits.mozilla.audits.sharded-slab]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.4 -> 0.1.7" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.shlex]] +who = "Max Inden " +criteria = "safe-to-deploy" +delta = "1.1.0 -> 1.3.0" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.smallvec]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.14.0 -> 1.15.1" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing]] +who = "Alex Franchuk " +criteria = "safe-to-deploy" +version = "0.1.37" +notes = """ +There's only one unsafe impl, and its purpose is to ensure correct behavior by +creating a non-Send marker type (it has nothing to do with soundness). All +dependencies make sense, and no side-effectful std functions are used. +""" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.37 -> 0.1.41" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-attributes]] +who = "Alex Franchuk " +criteria = "safe-to-deploy" +version = "0.1.24" +notes = "No unsafe code, macros extensively tested and produce reasonable code." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-attributes]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.24 -> 0.1.28" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-core]] +who = "Alex Franchuk " +criteria = "safe-to-deploy" +version = "0.1.30" +notes = """ +Most unsafe code is in implementing non-std sync primitives. Unsafe impls are +logically correct and justified in comments, and unsafe code is sound and +justified in comments. +""" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-core]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.30 -> 0.1.33" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" -- cgit From ca56810321b878fdfbf0b6686af0e8167468a883 Mon Sep 17 00:00:00 2001 From: James Munns Date: Wed, 26 Nov 2025 19:07:37 +0100 Subject: Add LPUART5 pin mappings (#53) Closes #48. --- src/lpuart/mod.rs | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 911c2a8e9..317274a79 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -517,9 +517,17 @@ impl_rts_pin!(LPUART4, P3_16, Mux2); impl_rts_pin!(LPUART4, P3_30, Mux3); // LPUART 5 -// -// TODO: The datasheet doesn't list tx/rx/cts/rts pins for LPUART5 -// See https://github.com/OpenDevicePartnership/embassy-mcxa/issues/48 +impl_tx_pin!(LPUART5, P1_10, Mux8); +impl_tx_pin!(LPUART5, P1_17, Mux8); + +impl_rx_pin!(LPUART5, P1_11, Mux8); +impl_rx_pin!(LPUART5, P1_16, Mux8); + +impl_cts_pin!(LPUART5, P1_12, Mux8); +impl_cts_pin!(LPUART5, P1_19, Mux8); + +impl_rts_pin!(LPUART5, P1_13, Mux8); +impl_rts_pin!(LPUART5, P1_18, Mux8); // ============================================================================ // ERROR TYPES AND RESULTS -- cgit From 87c4eaf3380505ca15ef7ed1d5dc435e9af2200e Mon Sep 17 00:00:00 2001 From: James Munns Date: Fri, 28 Nov 2025 18:49:10 +0100 Subject: Fix LPI2C2 example (#56) Fix LPI2C2 example --- examples/src/bin/i2c-scan-blocking.rs | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/examples/src/bin/i2c-scan-blocking.rs b/examples/src/bin/i2c-scan-blocking.rs index 6d1247e7a..72f9d09e0 100644 --- a/examples/src/bin/i2c-scan-blocking.rs +++ b/examples/src/bin/i2c-scan-blocking.rs @@ -2,6 +2,8 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa::gpio::{DriveStrength, Pull, SlewRate}; +use embassy_mcxa::Input; use embassy_time::Timer; use hal::clocks::config::Div8; use hal::config::Config; @@ -19,7 +21,12 @@ async fn main(_spawner: Spawner) { let mut config = controller::Config::default(); config.speed = Speed::Standard; - let mut i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap(); + + // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and + // defaults to SWO on the debug peripheral. Explicitly make it a high-z + // input. + let _pin = Input::new(p.P0_2, Pull::Disabled, DriveStrength::Normal, SlewRate::Slow); + let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap(); for addr in 0x01..=0x7f { let result = i2c.blocking_write(addr, &[]); -- cgit From 3b239cb6de22b7bb8c2d87defb3205294653be7a Mon Sep 17 00:00:00 2001 From: James Munns Date: Sat, 29 Nov 2025 16:07:30 +0100 Subject: Remove Drive/Slew settings for Input pin (#57) * Don't set slew+strength for inputs * Update example --- examples/src/bin/button.rs | 6 ++++-- examples/src/bin/button_async.rs | 5 +++-- examples/src/bin/i2c-scan-blocking.rs | 4 ++-- src/gpio.rs | 12 ++++++++---- 4 files changed, 17 insertions(+), 10 deletions(-) diff --git a/examples/src/bin/button.rs b/examples/src/bin/button.rs index 2abfe0a9f..943edbb15 100644 --- a/examples/src/bin/button.rs +++ b/examples/src/bin/button.rs @@ -3,7 +3,7 @@ use embassy_executor::Spawner; use embassy_time::Timer; -use hal::gpio::{DriveStrength, Input, Pull, SlewRate}; +use hal::gpio::{Input, Pull}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; #[embassy_executor::main] @@ -12,7 +12,9 @@ async fn main(_spawner: Spawner) { defmt::info!("Button example"); - let monitor = Input::new(p.P1_7, Pull::Disabled, DriveStrength::Normal, SlewRate::Slow); + // This button is labeled "WAKEUP" on the FRDM-MCXA276 + // The board already has a 10K pullup + let monitor = Input::new(p.P1_7, Pull::Disabled); loop { defmt::info!("Pin level is {:?}", monitor.get_level()); diff --git a/examples/src/bin/button_async.rs b/examples/src/bin/button_async.rs index 1ecec2e48..6cc7b62cd 100644 --- a/examples/src/bin/button_async.rs +++ b/examples/src/bin/button_async.rs @@ -3,7 +3,7 @@ use embassy_executor::Spawner; use embassy_time::Timer; -use hal::gpio::{DriveStrength, Input, Pull, SlewRate}; +use hal::gpio::{Input, Pull}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; #[embassy_executor::main] @@ -13,7 +13,8 @@ async fn main(_spawner: Spawner) { defmt::info!("GPIO interrupt example"); // This button is labeled "WAKEUP" on the FRDM-MCXA276 - let mut pin = Input::new(p.P1_7, Pull::Up, DriveStrength::Normal, SlewRate::Fast); + // The board already has a 10K pullup + let mut pin = Input::new(p.P1_7, Pull::Disabled); let mut press_count = 0u32; diff --git a/examples/src/bin/i2c-scan-blocking.rs b/examples/src/bin/i2c-scan-blocking.rs index 72f9d09e0..4e203597b 100644 --- a/examples/src/bin/i2c-scan-blocking.rs +++ b/examples/src/bin/i2c-scan-blocking.rs @@ -2,7 +2,7 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa::gpio::{DriveStrength, Pull, SlewRate}; +use embassy_mcxa::gpio::Pull; use embassy_mcxa::Input; use embassy_time::Timer; use hal::clocks::config::Div8; @@ -25,7 +25,7 @@ async fn main(_spawner: Spawner) { // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and // defaults to SWO on the debug peripheral. Explicitly make it a high-z // input. - let _pin = Input::new(p.P0_2, Pull::Disabled, DriveStrength::Normal, SlewRate::Slow); + let _pin = Input::new(p.P0_2, Pull::Disabled); let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap(); for addr in 0x01..=0x7f { diff --git a/src/gpio.rs b/src/gpio.rs index 332c4c8b2..65f8df985 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -818,11 +818,10 @@ pub struct Input<'d> { impl<'d> Input<'d> { /// Create a GPIO input driver for a [GpioPin]. - pub fn new(pin: Peri<'d, impl GpioPin>, pull_select: Pull, strength: DriveStrength, slew_rate: SlewRate) -> Self { + /// + pub fn new(pin: Peri<'d, impl GpioPin>, pull_select: Pull) -> Self { let mut flex = Flex::new(pin); flex.set_as_input(); - flex.set_drive_strength(strength); - flex.set_slew_rate(slew_rate); flex.set_pull(pull_select); Self { flex } } @@ -840,8 +839,13 @@ impl<'d> Input<'d> { } /// Expose the inner `Flex` if callers need to reconfigure the pin. + /// + /// Since Drive Strength and Slew Rate are not set when creating the Input + /// pin, they need to be set when converting #[inline] - pub fn into_flex(self) -> Flex<'d> { + pub fn into_flex(mut self, strength: DriveStrength, slew_rate: SlewRate) -> Flex<'d> { + self.flex.set_drive_strength(strength); + self.flex.set_slew_rate(slew_rate); self.flex } -- cgit From 717346f21a4cf4993c2a1f046e26b6bf647d89cb Mon Sep 17 00:00:00 2001 From: JanKomarekNXP <151725448+JanKomarekNXP@users.noreply.github.com> Date: Mon, 1 Dec 2025 18:07:58 +0100 Subject: Refactor LPUART driver constructors (#51) * Refactor LPUART driver constructors - Add new_with_rtscts(), new_with_rts(), new_with_cts() methods - Store RTS/CTS pins in TX/RX structs - Remove enable_tx, enable_rx, enable_rx_rts, enable_tx_cts config fields - Fix typo: msb_firs -> msb_first - Fix write_byte() return type to Result<()> * Update hello example for LPUART driver changes * Refactor buffered LPUART initialization logic - Split new_inner() into init_common() and separate helpers for full-duplex, TX-only, and RX-only - Replace assert!() with proper Error::InvalidArgument returns for empty buffers - Simplify constructor implementations by removing expect() calls --- examples/src/bin/hello.rs | 14 +- examples/src/bin/lpuart_buffered.rs | 2 - examples/src/bin/lpuart_polling.rs | 2 - src/lpuart/buffered.rs | 505 +++++++++++++++++++++--------------- src/lpuart/mod.rs | 141 ++++++---- 5 files changed, 404 insertions(+), 260 deletions(-) diff --git a/examples/src/bin/hello.rs b/examples/src/bin/hello.rs index f426d1898..e371d9413 100644 --- a/examples/src/bin/hello.rs +++ b/examples/src/bin/hello.rs @@ -2,27 +2,29 @@ #![no_main] use embassy_executor::Spawner; +use embassy_mcxa::clocks::config::Div8; use hal::lpuart::{Blocking, Config, Lpuart}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; /// Simple helper to write a byte as hex to UART fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) { const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; - uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); - uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); + let _ = uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); + let _ = uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); } #[embassy_executor::main] async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); defmt::info!("boot"); // Create UART configuration let config = Config { baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, ..Default::default() }; @@ -97,7 +99,7 @@ async fn main(_spawner: Spawner) { // Regular character buffer[buf_idx] = byte; buf_idx += 1; - uart.write_byte(byte); + let _ = uart.write_byte(byte); } } } diff --git a/examples/src/bin/lpuart_buffered.rs b/examples/src/bin/lpuart_buffered.rs index 7f77d557d..420589d00 100644 --- a/examples/src/bin/lpuart_buffered.rs +++ b/examples/src/bin/lpuart_buffered.rs @@ -27,8 +27,6 @@ async fn main(_spawner: Spawner) { // UART configuration (enable both TX and RX) let config = Config { baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, rx_fifo_watermark: 0, tx_fifo_watermark: 0, ..Default::default() diff --git a/examples/src/bin/lpuart_polling.rs b/examples/src/bin/lpuart_polling.rs index 9cea418cc..b80668834 100644 --- a/examples/src/bin/lpuart_polling.rs +++ b/examples/src/bin/lpuart_polling.rs @@ -19,8 +19,6 @@ async fn main(_spawner: Spawner) { // Create UART configuration let config = Config { baudrate_bps: 115_200, - enable_tx: true, - enable_rx: true, ..Default::default() }; diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index 6f41c33c9..8eb443ca7 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -16,11 +16,11 @@ use crate::interrupt; /// State for buffered LPUART operations pub struct State { - rx_waker: AtomicWaker, - rx_buf: RingBuffer, tx_waker: AtomicWaker, tx_buf: RingBuffer, tx_done: AtomicBool, + rx_waker: AtomicWaker, + rx_buf: RingBuffer, initialized: AtomicBool, } @@ -34,11 +34,11 @@ impl State { /// Create a new state instance pub const fn new() -> Self { Self { - rx_waker: AtomicWaker::new(), - rx_buf: RingBuffer::new(), tx_waker: AtomicWaker::new(), tx_buf: RingBuffer::new(), tx_done: AtomicBool::new(true), + rx_waker: AtomicWaker::new(), + rx_buf: RingBuffer::new(), initialized: AtomicBool::new(false), } } @@ -58,6 +58,7 @@ pub struct BufferedLpuartTx<'a> { info: Info, state: &'static State, _tx_pin: Peri<'a, AnyPin>, + _cts_pin: Option>, } /// Buffered LPUART RX driver @@ -65,6 +66,7 @@ pub struct BufferedLpuartRx<'a> { info: Info, state: &'static State, _rx_pin: Peri<'a, AnyPin>, + _rts_pin: Option>, } // ============================================================================ @@ -72,143 +74,41 @@ pub struct BufferedLpuartRx<'a> { // ============================================================================ impl<'a> BufferedLpuart<'a> { - /// Create a new buffered LPUART instance - pub fn new( - _inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - rx_pin: Peri<'a, impl RxPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - // Configure pins - tx_pin.as_tx(); - rx_pin.as_rx(); - - // Convert pins to AnyPin - let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); - let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); - - let state = T::buffered_state(); - - // Initialize the peripheral - Self::init::(Some(&tx_pin), Some(&rx_pin), None, None, tx_buffer, rx_buffer, config)?; - - Ok(Self { - tx: BufferedLpuartTx { - info: T::info(), - state, - _tx_pin: tx_pin, - }, - rx: BufferedLpuartRx { - info: T::info(), - state, - _rx_pin: rx_pin, - }, - }) - } - - /// Create a new buffered LPUART with flexible pin configuration - #[allow(clippy::too_many_arguments)] - pub fn new_with_pins( - _inner: Peri<'a, T>, - tx_pin: Option>>, - rx_pin: Option>>, - rts_pin: Option>>, - cts_pin: Option>>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - // Configure pins if provided - let tx_pin: Option> = tx_pin.map(|pin| { - pin.as_tx(); - pin.into() - }); - - let rx_pin: Option> = rx_pin.map(|pin| { - pin.as_rx(); - pin.into() - }); - - let rts_pin: Option> = rts_pin.map(|pin| { - pin.as_rts(); - pin.into() - }); - - let cts_pin: Option> = cts_pin.map(|pin| { - pin.as_cts(); - pin.into() - }); - + /// Common initialization logic + fn init_common( + _inner: &Peri<'a, T>, + tx_buffer: Option<&'a mut [u8]>, + rx_buffer: Option<&'a mut [u8]>, + config: &Config, + enable_tx: bool, + enable_rx: bool, + enable_rts: bool, + enable_cts: bool, + ) -> Result<&'static State> { let state = T::buffered_state(); - // Initialize the peripheral - Self::init::( - tx_pin.as_ref(), - rx_pin.as_ref(), - rts_pin.as_ref(), - cts_pin.as_ref(), - tx_buffer, - rx_buffer, - config, - )?; - - // Create TX and RX instances - let (tx, rx) = if let (Some(tx_pin), Some(rx_pin)) = (tx_pin, rx_pin) { - ( - BufferedLpuartTx { - info: T::info(), - state, - _tx_pin: tx_pin, - }, - BufferedLpuartRx { - info: T::info(), - state, - _rx_pin: rx_pin, - }, - ) - } else { - return Err(Error::InvalidArgument); - }; - - Ok(Self { tx, rx }) - } - - fn init( - _tx: Option<&Peri<'a, AnyPin>>, - _rx: Option<&Peri<'a, AnyPin>>, - _rts: Option<&Peri<'a, AnyPin>>, - _cts: Option<&Peri<'a, AnyPin>>, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - mut config: Config, - ) -> Result<()> { - let regs = T::info().regs; - let state = T::buffered_state(); - - // Check if already initialized if state.initialized.load(Ordering::Relaxed) { return Err(Error::InvalidArgument); } - // Initialize ring buffers - assert!(!tx_buffer.is_empty()); - unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), tx_buffer.len()) } + // Initialize buffers + if let Some(tx_buffer) = tx_buffer { + if tx_buffer.is_empty() { + return Err(Error::InvalidArgument); + } + unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), tx_buffer.len()) }; + } - assert!(!rx_buffer.is_empty()); - unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_buffer.len()) } + if let Some(rx_buffer) = rx_buffer { + if rx_buffer.is_empty() { + return Err(Error::InvalidArgument); + } + unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_buffer.len()) }; + } - // Mark as initialized state.initialized.store(true, Ordering::Relaxed); - // Enable TX and RX for buffered operation - config.enable_tx = true; - config.enable_rx = true; - - // Enable clocks + // Enable clocks and initialize hardware let conf = LpuartConfig { power: config.power, source: config.source, @@ -217,6 +117,68 @@ impl<'a> BufferedLpuart<'a> { }; let clock_freq = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; + Self::init_hardware( + T::info().regs, + *config, + clock_freq, + enable_tx, + enable_rx, + enable_rts, + enable_cts, + )?; + + Ok(state) + } + + /// Helper for full-duplex initialization + fn new_inner( + inner: Peri<'a, T>, + tx_pin: Peri<'a, AnyPin>, + rx_pin: Peri<'a, AnyPin>, + rts_pin: Option>, + cts_pin: Option>, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result<(BufferedLpuartTx<'a>, BufferedLpuartRx<'a>)> { + let state = Self::init_common::( + &inner, + Some(tx_buffer), + Some(rx_buffer), + &config, + true, + true, + rts_pin.is_some(), + cts_pin.is_some(), + )?; + + let tx = BufferedLpuartTx { + info: T::info(), + state, + _tx_pin: tx_pin, + _cts_pin: cts_pin, + }; + + let rx = BufferedLpuartRx { + info: T::info(), + state, + _rx_pin: rx_pin, + _rts_pin: rts_pin, + }; + + Ok((tx, rx)) + } + + /// Common hardware initialization logic + fn init_hardware( + regs: &'static mcxa_pac::lpuart0::RegisterBlock, + config: Config, + clock_freq: u32, + enable_tx: bool, + enable_rx: bool, + enable_rts: bool, + enable_cts: bool, + ) -> Result<()> { // Perform standard initialization perform_software_reset(regs); disable_transceiver(regs); @@ -225,8 +187,8 @@ impl<'a> BufferedLpuart<'a> { configure_control_settings(regs, &config); configure_fifo(regs, &config); clear_all_status_flags(regs); - configure_flow_control(regs, &config); - configure_bit_order(regs, config.msb_firs); + configure_flow_control(regs, enable_rts, enable_cts, &config); + configure_bit_order(regs, config.msb_first); // Enable interrupts for buffered operation cortex_m::interrupt::free(|_| { @@ -245,17 +207,127 @@ impl<'a> BufferedLpuart<'a> { }); // Enable the transceiver - enable_transceiver(regs, config.enable_tx, config.enable_rx); - - // Enable the interrupt - // unsafe { - // // TODO: Used the propper interrupt enable method for the specific LPUART instance - // // T::Interrupt::enable(); - // } + enable_transceiver(regs, enable_rx, enable_tx); Ok(()) } + /// Create a new full duplex buffered LPUART + pub fn new( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + None, + None, + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + + /// Create a new buffered LPUART instance with RTS/CTS flow control + pub fn new_with_rtscts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + cts_pin: Peri<'a, impl CtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + rts_pin.as_rts(); + cts_pin.as_cts(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + Some(rts_pin.into()), + Some(cts_pin.into()), + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + + /// Create a new buffered LPUART with only RTS flow control (RX flow control) + pub fn new_with_rts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + rts_pin.as_rts(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + Some(rts_pin.into()), + None, + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + + /// Create a new buffered LPUART with only CTS flow control (TX flow control) + pub fn new_with_cts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + cts_pin: Peri<'a, impl CtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + cts_pin.as_cts(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + None, + Some(cts_pin.into()), + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + /// Split the buffered LPUART into separate TX and RX parts pub fn split(self) -> (BufferedLpuartTx<'a>, BufferedLpuartRx<'a>) { (self.tx, self.rx) @@ -272,51 +344,62 @@ impl<'a> BufferedLpuart<'a> { // ============================================================================ impl<'a> BufferedLpuartTx<'a> { - /// Create a new TX-only buffered LPUART + /// Helper for TX-only initialization + fn new_inner( + inner: Peri<'a, T>, + tx_pin: Peri<'a, AnyPin>, + cts_pin: Option>, + tx_buffer: &'a mut [u8], + config: Config, + ) -> Result> { + let state = BufferedLpuart::init_common::( + &inner, + Some(tx_buffer), + None, + &config, + true, + false, + false, + cts_pin.is_some(), + )?; + + Ok(BufferedLpuartTx { + info: T::info(), + state, + _tx_pin: tx_pin, + _cts_pin: cts_pin, + }) + } + pub fn new( - _inner: Peri<'a, T>, + inner: Peri<'a, T>, tx_pin: Peri<'a, impl TxPin>, _irq: impl interrupt::typelevel::Binding> + 'a, tx_buffer: &'a mut [u8], config: Config, ) -> Result { tx_pin.as_tx(); - let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); - - let info = T::info(); - let state = T::buffered_state(); - - // Check if already initialized - if state.initialized.load(Ordering::Relaxed) { - return Err(Error::InvalidArgument); - } - // Initialize TX ring buffer only - unsafe { - let tx_buf = &state.tx_buf as *const _ as *mut RingBuffer; - (*tx_buf).init(tx_buffer.as_mut_ptr(), tx_buffer.len()); - } - - state.initialized.store(true, Ordering::Relaxed); + Self::new_inner::(inner, tx_pin.into(), None, tx_buffer, config) + } - // Initialize with TX only - BufferedLpuart::init::( - Some(&tx_pin), - None, - None, - None, - tx_buffer, - &mut [], // Empty RX buffer - config, - )?; + /// Create a new TX-only buffered LPUART with CTS flow control + pub fn new_with_cts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + cts_pin: Peri<'a, impl CtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + cts_pin.as_cts(); - Ok(Self { - info, - state, - _tx_pin: tx_pin, - }) + Self::new_inner::(inner, tx_pin.into(), Some(cts_pin.into()), tx_buffer, config) } +} +impl<'a> BufferedLpuartTx<'a> { /// Write data asynchronously pub async fn write(&mut self, buf: &[u8]) -> Result { let mut written = 0; @@ -401,51 +484,63 @@ impl<'a> BufferedLpuartTx<'a> { // ============================================================================ impl<'a> BufferedLpuartRx<'a> { + /// Helper for RX-only initialization + fn new_inner( + inner: Peri<'a, T>, + rx_pin: Peri<'a, AnyPin>, + rts_pin: Option>, + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result> { + let state = BufferedLpuart::init_common::( + &inner, + None, + Some(rx_buffer), + &config, + false, + true, + rts_pin.is_some(), + false, + )?; + + Ok(BufferedLpuartRx { + info: T::info(), + state, + _rx_pin: rx_pin, + _rts_pin: rts_pin, + }) + } + /// Create a new RX-only buffered LPUART pub fn new( - _inner: Peri<'a, T>, + inner: Peri<'a, T>, rx_pin: Peri<'a, impl RxPin>, _irq: impl interrupt::typelevel::Binding> + 'a, rx_buffer: &'a mut [u8], config: Config, ) -> Result { rx_pin.as_rx(); - let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); - - let info = T::info(); - let state = T::buffered_state(); - - // Check if already initialized - if state.initialized.load(Ordering::Relaxed) { - return Err(Error::InvalidArgument); - } - // Initialize RX ring buffer only - unsafe { - let rx_buf = &state.rx_buf as *const _ as *mut RingBuffer; - (*rx_buf).init(rx_buffer.as_mut_ptr(), rx_buffer.len()); - } - - state.initialized.store(true, Ordering::Relaxed); + Self::new_inner::(inner, rx_pin.into(), None, rx_buffer, config) + } - // Initialize with RX only - BufferedLpuart::init::( - None, - Some(&rx_pin), - None, - None, - &mut [], // Empty TX buffer - rx_buffer, - config, - )?; + /// Create a new RX-only buffered LPUART with RTS flow control + pub fn new_with_rts( + inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + rx_pin.as_rx(); + rts_pin.as_rts(); - Ok(Self { - info, - state, - _rx_pin: rx_pin, - }) + Self::new_inner::(inner, rx_pin.into(), Some(rts_pin.into()), rx_buffer, config) } +} +impl<'a> BufferedLpuartRx<'a> { /// Read data asynchronously pub async fn read(&mut self, buf: &mut [u8]) -> Result { if buf.is_empty() { diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 317274a79..2d8308ec8 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -203,8 +203,8 @@ pub fn clear_all_status_flags(regs: Regs) { } /// Configure hardware flow control if enabled -pub fn configure_flow_control(regs: Regs, config: &Config) { - if config.enable_rx_rts || config.enable_tx_cts { +pub fn configure_flow_control(regs: Regs, enable_tx_cts: bool, enable_rx_rts: bool, config: &Config) { + if enable_rx_rts || enable_tx_cts { regs.modir().modify(|_, w| { let mut w = w; @@ -212,13 +212,13 @@ pub fn configure_flow_control(regs: Regs, config: &Config) { w = w.txctsc().variant(config.tx_cts_config); w = w.txctssrc().variant(config.tx_cts_source); - if config.enable_rx_rts { + if enable_rx_rts { w = w.rxrtse().enabled(); } else { w = w.rxrtse().disabled(); } - if config.enable_tx_cts { + if enable_tx_cts { w = w.txctse().enabled(); } else { w = w.txctse().disabled(); @@ -586,17 +586,13 @@ pub struct Config { /// Number of data bits pub data_bits_count: DataBits, /// MSB First or LSB First configuration - pub msb_firs: MsbFirst, + pub msb_first: MsbFirst, /// Number of stop bits pub stop_bits_count: StopBits, /// TX FIFO watermark pub tx_fifo_watermark: u8, /// RX FIFO watermark pub rx_fifo_watermark: u8, - /// RX RTS enable - pub enable_rx_rts: bool, - /// TX CTS enable - pub enable_tx_cts: bool, /// TX CTS source pub tx_cts_source: TxCtsSource, /// TX CTS configure @@ -605,10 +601,6 @@ pub struct Config { pub rx_idle_type: IdleType, /// RX IDLE configuration pub rx_idle_config: IdleConfig, - /// Enable transmitter - pub enable_tx: bool, - /// Enable receiver - pub enable_rx: bool, /// Swap TXD and RXD pins pub swap_txd_rxd: bool, } @@ -619,18 +611,14 @@ impl Default for Config { baudrate_bps: 115_200u32, parity_mode: None, data_bits_count: DataBits::Data8, - msb_firs: MsbFirst::LsbFirst, + msb_first: MsbFirst::LsbFirst, stop_bits_count: StopBits::One, tx_fifo_watermark: 0, rx_fifo_watermark: 1, - enable_rx_rts: false, - enable_tx_cts: false, tx_cts_source: TxCtsSource::Cts, tx_cts_config: TxCtsConfig::Start, rx_idle_type: IdleType::FromStart, rx_idle_config: IdleConfig::Idle1, - enable_tx: false, - enable_rx: false, swap_txd_rxd: false, power: PoweredClock::NormalEnabledDeepSleepDisabled, source: LpuartClockSel::FroLfDiv, @@ -694,6 +682,7 @@ pub struct Lpuart<'a, M: Mode> { pub struct LpuartTx<'a, M: Mode> { info: Info, _tx_pin: Peri<'a, AnyPin>, + _cts_pin: Option>, _tx_dma: Option>, mode: PhantomData<(&'a (), M)>, } @@ -702,6 +691,7 @@ pub struct LpuartTx<'a, M: Mode> { pub struct LpuartRx<'a, M: Mode> { info: Info, _rx_pin: Peri<'a, AnyPin>, + _rts_pin: Option>, _rx_dma: Option>, mode: PhantomData<(&'a (), M)>, } @@ -712,10 +702,10 @@ pub struct LpuartRx<'a, M: Mode> { impl<'a, M: Mode> Lpuart<'a, M> { fn init( - _tx: Option<&Peri<'a, AnyPin>>, - _rx: Option<&Peri<'a, AnyPin>>, - _rts: Option<&Peri<'a, AnyPin>>, - _cts: Option<&Peri<'a, AnyPin>>, + enable_tx: bool, + enable_rx: bool, + enable_tx_cts: bool, + enable_rx_rts: bool, config: Config, ) -> Result<()> { let regs = T::info().regs; @@ -737,9 +727,9 @@ impl<'a, M: Mode> Lpuart<'a, M> { configure_control_settings(regs, &config); configure_fifo(regs, &config); clear_all_status_flags(regs); - configure_flow_control(regs, &config); - configure_bit_order(regs, config.msb_firs); - enable_transceiver(regs, config.enable_tx, config.enable_rx); + configure_flow_control(regs, enable_tx_cts, enable_rx_rts, &config); + configure_bit_order(regs, config.msb_first); + enable_transceiver(regs, enable_rx, enable_tx); Ok(()) } @@ -776,7 +766,7 @@ impl<'a, M: Mode> Lpuart<'a, M> { // ============================================================================ impl<'a> Lpuart<'a, Blocking> { - /// Create a new blocking LPUART instance with TX and RX pins. + /// Create a new blocking LPUART instance with RX/TX pins. pub fn new_blocking( _inner: Peri<'a, T>, tx_pin: Peri<'a, impl TxPin>, @@ -787,17 +777,38 @@ impl<'a> Lpuart<'a, Blocking> { tx_pin.as_tx(); rx_pin.as_rx(); - // Convert pins to AnyPin - let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); - let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); - // Initialize the peripheral - Self::init::(Some(&tx_pin), Some(&rx_pin), None, None, config)?; + Self::init::(true, true, false, false, config)?; Ok(Self { info: T::info(), - tx: LpuartTx::new_inner(T::info(), tx_pin, None), - rx: LpuartRx::new_inner(T::info(), rx_pin, None), + tx: LpuartTx::new_inner(T::info(), tx_pin.into(), None, None), + rx: LpuartRx::new_inner(T::info(), rx_pin.into(), None, None), + }) + } + + /// Create a new blocking LPUART instance with RX, TX and RTS/CTS flow control pins + pub fn new_blocking_with_rtscts( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + cts_pin: Peri<'a, impl CtsPin>, + rts_pin: Peri<'a, impl RtsPin>, + config: Config, + ) -> Result { + // Configure the pins for LPUART usage + rx_pin.as_rx(); + tx_pin.as_tx(); + rts_pin.as_rts(); + cts_pin.as_cts(); + + // Initialize the peripheral with flow control + Self::init::(true, true, true, true, config)?; + + Ok(Self { + info: T::info(), + rx: LpuartRx::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into()), None), + tx: LpuartTx::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into()), None), }) } } @@ -807,10 +818,16 @@ impl<'a> Lpuart<'a, Blocking> { // ---------------------------------------------------------------------------- impl<'a, M: Mode> LpuartTx<'a, M> { - fn new_inner(info: Info, tx_pin: Peri<'a, AnyPin>, tx_dma: Option>) -> Self { + fn new_inner( + info: Info, + tx_pin: Peri<'a, AnyPin>, + cts_pin: Option>, + tx_dma: Option>, + ) -> Self { Self { info, _tx_pin: tx_pin, + _cts_pin: cts_pin, _tx_dma: tx_dma, mode: PhantomData, } @@ -818,19 +835,34 @@ impl<'a, M: Mode> LpuartTx<'a, M> { } impl<'a> LpuartTx<'a, Blocking> { - /// Create a new blocking LPUART which can only send data. + /// Create a new blocking LPUART transmitter instance pub fn new_blocking( _inner: Peri<'a, T>, tx_pin: Peri<'a, impl TxPin>, config: Config, ) -> Result { + // Configure the pins for LPUART usage tx_pin.as_tx(); - let tx_pin: Peri<'a, AnyPin> = tx_pin.into(); + // Initialize the peripheral + Lpuart::::init::(true, false, false, false, config)?; + + Ok(Self::new_inner(T::info(), tx_pin.into(), None, None)) + } + + /// Create a new blocking LPUART transmitter instance with CTS flow control + pub fn new_blocking_with_cts( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + cts_pin: Peri<'a, impl CtsPin>, + config: Config, + ) -> Result { + tx_pin.as_tx(); + cts_pin.as_cts(); - Lpuart::::init::(Some(&tx_pin), None, None, None, config)?; + Lpuart::::init::(true, false, true, false, config)?; - Ok(Self::new_inner(T::info(), tx_pin, None)) + Ok(Self::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into()), None)) } fn write_byte_internal(&mut self, byte: u8) -> Result<()> { @@ -909,10 +941,16 @@ impl<'a> LpuartTx<'a, Blocking> { // ---------------------------------------------------------------------------- impl<'a, M: Mode> LpuartRx<'a, M> { - fn new_inner(info: Info, rx_pin: Peri<'a, AnyPin>, rx_dma: Option>) -> Self { + fn new_inner( + info: Info, + rx_pin: Peri<'a, AnyPin>, + rts_pin: Option>, + rx_dma: Option>, + ) -> Self { Self { info, _rx_pin: rx_pin, + _rts_pin: rts_pin, _rx_dma: rx_dma, mode: PhantomData, } @@ -920,7 +958,7 @@ impl<'a, M: Mode> LpuartRx<'a, M> { } impl<'a> LpuartRx<'a, Blocking> { - /// Create a new blocking LPUART which can only receive data. + /// Create a new blocking LPUART Receiver instance pub fn new_blocking( _inner: Peri<'a, T>, rx_pin: Peri<'a, impl RxPin>, @@ -928,11 +966,24 @@ impl<'a> LpuartRx<'a, Blocking> { ) -> Result { rx_pin.as_rx(); - let rx_pin: Peri<'a, AnyPin> = rx_pin.into(); + Lpuart::::init::(false, true, false, false, config)?; + + Ok(Self::new_inner(T::info(), rx_pin.into(), None, None)) + } + + /// Create a new blocking LPUART Receiver instance with RTS flow control + pub fn new_blocking_with_rts( + _inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + config: Config, + ) -> Result { + rx_pin.as_rx(); + rts_pin.as_rts(); - Lpuart::::init::(None, Some(&rx_pin), None, None, config)?; + Lpuart::::init::(false, true, false, true, config)?; - Ok(Self::new_inner(T::info(), rx_pin, None)) + Ok(Self::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into()), None)) } fn read_byte_internal(&mut self) -> Result { @@ -994,8 +1045,8 @@ impl<'a> Lpuart<'a, Blocking> { self.tx.blocking_write(buf) } - pub fn write_byte(&mut self, byte: u8) { - _ = self.tx.write_byte(byte); + pub fn write_byte(&mut self, byte: u8) -> Result<()> { + self.tx.write_byte(byte) } pub fn read_byte_blocking(&mut self) -> u8 { -- cgit From 8798306fb2c124efc06443c2913c3d7a4919dd83 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 3 Dec 2025 09:52:03 -0800 Subject: I2c Async (#50) * I2c Async Signed-off-by: Felipe Balbi * Fix i2c read bug Signed-off-by: Felipe Balbi * Introduce wait_for() Signed-off-by: Felipe Balbi * Review comments Signed-off-by: Felipe Balbi * more review comments Signed-off-by: Felipe Balbi * review comments Signed-off-by: Felipe Balbi * review comments Signed-off-by: Felipe Balbi * convert async fn to impl Future Signed-off-by: Felipe Balbi --------- Signed-off-by: Felipe Balbi Co-authored-by: Felipe Balbi --- examples/src/bin/i2c-async.rs | 39 +++++++ src/i2c/controller.rs | 253 ++++++++++++++++++++++++++++++++++++++++-- src/i2c/mod.rs | 43 +++++-- 3 files changed, 316 insertions(+), 19 deletions(-) create mode 100644 examples/src/bin/i2c-async.rs diff --git a/examples/src/bin/i2c-async.rs b/examples/src/bin/i2c-async.rs new file mode 100644 index 000000000..47b5f3cbe --- /dev/null +++ b/examples/src/bin/i2c-async.rs @@ -0,0 +1,39 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::bind_interrupts; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use hal::i2c::InterruptHandler; +use hal::peripherals::LPI2C3; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!( + struct Irqs { + LPI2C3 => InterruptHandler; + } +); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + let mut i2c = I2c::new_async(p.LPI2C3, p.P3_27, p.P3_28, Irqs, config).unwrap(); + let mut buf = [0u8; 2]; + + loop { + i2c.async_write_read(0x48, &[0x00], &mut buf).await.unwrap(); + defmt::info!("Buffer: {:02x}", buf); + Timer::after_secs(1).await; + } +} diff --git a/src/i2c/controller.rs b/src/i2c/controller.rs index 41bbc821d..818024bc9 100644 --- a/src/i2c/controller.rs +++ b/src/i2c/controller.rs @@ -1,13 +1,15 @@ //! LPI2C controller driver +use core::future::Future; use core::marker::PhantomData; use embassy_hal_internal::Peri; use mcxa_pac::lpi2c0::mtdr::Cmd; -use super::{Blocking, Error, Instance, Mode, Result, SclPin, SdaPin}; +use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin}; use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig}; use crate::clocks::{enable_and_reset, PoweredClock}; +use crate::interrupt::typelevel::Interrupt; use crate::AnyPin; /// Bus speed (nominal SCL, no clock stretching) @@ -199,9 +201,6 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { } fn status(&mut self) -> Result<()> { - // Wait for TxFIFO to be drained - while !self.is_tx_fifo_empty() {} - let msr = T::regs().msr().read(); T::regs().msr().write(|w| { w.epf() @@ -228,6 +227,8 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { Err(Error::AddressNack) } else if msr.alf().bit_is_set() { Err(Error::ArbitrationLoss) + } else if msr.fef().bit_is_set() { + Err(Error::FifoError) } else { Ok(()) } @@ -259,6 +260,9 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { let addr_rw = address << 1 | if read { 1 } else { 0 }; self.send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); + // Wait for TxFIFO to be drained + while !self.is_tx_fifo_empty() {} + // Check controller status self.status() } @@ -268,17 +272,21 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { while self.is_tx_fifo_full() {} self.send_cmd(Cmd::Stop, 0); + + // Wait for TxFIFO to be drained + while !self.is_tx_fifo_empty() {} + self.status() } fn blocking_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { - self.start(address, true)?; - if read.is_empty() { return Err(Error::InvalidReadBufferLength); } for chunk in read.chunks_mut(256) { + self.start(address, true)?; + // Wait until we have space in the TxFIFO while self.is_tx_fifo_full() {} @@ -290,10 +298,10 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { *byte = T::regs().mrdr().read().data().bits(); } + } - if send_stop == SendStop::Yes { - self.stop()?; - } + if send_stop == SendStop::Yes { + self.stop()?; } Ok(()) @@ -351,6 +359,201 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { } } +impl<'d, T: Instance> I2c<'d, T, Async> { + /// Create a new async instance of the I2C Controller bus driver. + pub fn new_async( + peri: Peri<'d, T>, + scl: Peri<'d, impl SclPin>, + sda: Peri<'d, impl SdaPin>, + _irq: impl crate::interrupt::typelevel::Binding> + 'd, + config: Config, + ) -> Result { + T::Interrupt::unpend(); + + // Safety: `_irq` ensures an Interrupt Handler exists. + unsafe { T::Interrupt::enable() }; + + Self::new_inner(peri, scl, sda, config) + } + + fn enable_rx_ints(&mut self) { + T::regs().mier().write(|w| { + w.rdie() + .enabled() + .ndie() + .enabled() + .alie() + .enabled() + .feie() + .enabled() + .pltie() + .enabled() + }); + } + + fn enable_tx_ints(&mut self) { + T::regs().mier().write(|w| { + w.tdie() + .enabled() + .ndie() + .enabled() + .alie() + .enabled() + .feie() + .enabled() + .pltie() + .enabled() + }); + } + + async fn async_start(&mut self, address: u8, read: bool) -> Result<()> { + if address >= 0x80 { + return Err(Error::AddressOutOfRange(address)); + } + + // send the start command + let addr_rw = address << 1 | if read { 1 } else { 0 }; + self.send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); + + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // if the command FIFO is empty, we're done sending start + self.is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::Other)?; + + self.status() + } + + async fn async_stop(&mut self) -> Result<()> { + // send the stop command + self.send_cmd(Cmd::Stop, 0); + + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // if the command FIFO is empty, we're done sending stop + self.is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::Other)?; + + self.status() + } + + async fn async_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { + if read.is_empty() { + return Err(Error::InvalidReadBufferLength); + } + + for chunk in read.chunks_mut(256) { + self.async_start(address, true).await?; + + // send receive command + self.send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); + + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // if the command FIFO is empty, we're done sending start + self.is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::Other)?; + + for byte in chunk.iter_mut() { + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_rx_ints(); + // it the rx FIFO is not empty, we need to read a byte + !self.is_rx_fifo_empty() + }) + .await + .map_err(|_| Error::ReadFail)?; + + *byte = T::regs().mrdr().read().data().bits(); + } + } + + if send_stop == SendStop::Yes { + self.async_stop().await?; + } + + Ok(()) + } + + async fn async_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> { + self.async_start(address, false).await?; + + // Usually, embassy HALs error out with an empty write, + // however empty writes are useful for writing I2C scanning + // logic through write probing. That is, we send a start with + // R/w bit cleared, but instead of writing any data, just send + // the stop onto the bus. This has the effect of checking if + // the resulting address got an ACK but causing no + // side-effects to the device on the other end. + // + // Because of this, we are not going to error out in case of + // empty writes. + #[cfg(feature = "defmt")] + if write.is_empty() { + defmt::trace!("Empty write, write probing?"); + } + + for byte in write { + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // initiate trasmit + self.send_cmd(Cmd::Transmit, *byte); + // it the rx FIFO is not empty, we're done transmiting + self.is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::WriteFail)?; + } + + if send_stop == SendStop::Yes { + self.async_stop().await?; + } + + Ok(()) + } + + // Public API: Async + + /// Read from address into buffer asynchronously. + pub fn async_read<'a>( + &mut self, + address: u8, + read: &'a mut [u8], + ) -> impl Future> + use<'_, 'a, 'd, T> { + self.async_read_internal(address, read, SendStop::Yes) + } + + /// Write to address from buffer asynchronously. + pub fn async_write<'a>( + &mut self, + address: u8, + write: &'a [u8], + ) -> impl Future> + use<'_, 'a, 'd, T> { + self.async_write_internal(address, write, SendStop::Yes) + } + + /// Write to address from bytes and read from address into buffer asynchronously. + pub async fn async_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> { + self.async_write_internal(address, write, SendStop::No).await?; + self.async_read_internal(address, read, SendStop::Yes).await + } +} + impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> { type Error = Error; @@ -445,6 +648,38 @@ impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> { } } +impl<'d, T: Instance> embedded_hal_async::i2c::I2c for I2c<'d, T, Async> { + async fn transaction( + &mut self, + address: u8, + operations: &mut [embedded_hal_async::i2c::Operation<'_>], + ) -> Result<()> { + if let Some((last, rest)) = operations.split_last_mut() { + for op in rest { + match op { + embedded_hal_async::i2c::Operation::Read(buf) => { + self.async_read_internal(address, buf, SendStop::No).await? + } + embedded_hal_async::i2c::Operation::Write(buf) => { + self.async_write_internal(address, buf, SendStop::No).await? + } + } + } + + match last { + embedded_hal_async::i2c::Operation::Read(buf) => { + self.async_read_internal(address, buf, SendStop::Yes).await + } + embedded_hal_async::i2c::Operation::Write(buf) => { + self.async_write_internal(address, buf, SendStop::Yes).await + } + } + } else { + Ok(()) + } + } +} + impl<'d, T: Instance, M: Mode> embassy_embedded_hal::SetConfig for I2c<'d, T, M> { type Config = Config; type ConfigError = Error; diff --git a/src/i2c/mod.rs b/src/i2c/mod.rs index a1f842029..9a014224a 100644 --- a/src/i2c/mod.rs +++ b/src/i2c/mod.rs @@ -3,7 +3,7 @@ use core::marker::PhantomData; use embassy_hal_internal::PeripheralType; -use embassy_sync::waitqueue::AtomicWaker; +use maitake_sync::WaitCell; use paste::paste; use crate::clocks::periph_helpers::Lpi2cConfig; @@ -22,6 +22,8 @@ pub mod controller; pub enum Error { /// Clock configuration error. ClockSetup(ClockError), + /// FIFO Error + FifoError, /// Reading for I2C failed. ReadFail, /// Writing to I2C failed. @@ -47,11 +49,32 @@ pub struct InterruptHandler { impl interrupt::typelevel::Handler for InterruptHandler { unsafe fn on_interrupt() { - let waker = T::waker(); - - waker.wake(); - - todo!() + if T::regs().mier().read().bits() != 0 { + T::regs().mier().write(|w| { + w.tdie() + .disabled() + .rdie() + .disabled() + .epie() + .disabled() + .sdie() + .disabled() + .ndie() + .disabled() + .alie() + .disabled() + .feie() + .disabled() + .pltie() + .disabled() + .dmie() + .disabled() + .stie() + .disabled() + }); + + T::wait_cell().wake(); + } } } @@ -64,7 +87,7 @@ impl sealed::Sealed for T {} trait SealedInstance { fn regs() -> &'static pac::lpi2c0::RegisterBlock; - fn waker() -> &'static AtomicWaker; + fn wait_cell() -> &'static WaitCell; } /// I2C Instance @@ -85,9 +108,9 @@ macro_rules! impl_instance { unsafe { &*pac::[]::ptr() } } - fn waker() -> &'static AtomicWaker { - static WAKER: AtomicWaker = AtomicWaker::new(); - &WAKER + fn wait_cell() -> &'static WaitCell { + static WAIT_CELL: WaitCell = WaitCell::new(); + &WAIT_CELL } } -- cgit From b75a6222e892cc58543b30f231b60dedaa0a5f5d Mon Sep 17 00:00:00 2001 From: James Munns Date: Wed, 3 Dec 2025 20:08:44 +0100 Subject: Misc minor cleanups (#85) --- Cargo.toml | 7 ++- src/clocks/periph_helpers.rs | 102 +++++++++++++++++++++---------------------- src/interrupt.rs | 21 ++++++++- 3 files changed, 74 insertions(+), 56 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 96b7d6b0f..22660bee9 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -33,7 +33,7 @@ embassy-time = { version = "0.5.0", optional = true } embassy-time-driver = { version = "0.2.1", optional = true } [features] -default = [] +default = ["rt"] # Base defmt feature enables core + panic handler # Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) @@ -41,6 +41,11 @@ defmt = ["dep:defmt", "mcxa-pac/defmt"] unstable-pac = [] +# dummy feature to silence embassy-hal-internal lint +# +# This feature makes no change to embassy-mcxa's operation. +rt = [] + # Embassy time time = [ "dep:embassy-time", diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs index 24d074e8a..1ea7a99ed 100644 --- a/src/clocks/periph_helpers.rs +++ b/src/clocks/periph_helpers.rs @@ -41,6 +41,50 @@ pub trait SPConfHelper { fn post_enable_config(&self, clocks: &Clocks) -> Result; } +/// Copy and paste macro that: +/// +/// * Sets the clocksel mux to `$selvar` +/// * Resets and halts the div, and applies the calculated div4 bits +/// * Releases reset + halt +/// * Waits for the div to stabilize +/// * Returns `Ok($freq / $conf.div.into_divisor())` +/// +/// Assumes: +/// +/// * self is a configuration struct that has a field called `div`, which +/// is a `Div4` +/// +/// usage: +/// +/// ```rust +/// apply_div4!(self, clksel, clkdiv, variant, freq) +/// ``` +/// +/// In the future if we make all the clksel+clkdiv pairs into commonly derivedFrom +/// registers, or if we put some kind of simple trait around those regs, we could +/// do this with something other than a macro, but for now, this is harm-reduction +/// to avoid incorrect copy + paste +macro_rules! apply_div4 { + ($conf:ident, $selreg:ident, $divreg:ident, $selvar:ident, $freq:ident) => {{ + // set clksel + $selreg.modify(|_r, w| w.mux().variant($selvar)); + + // Set up clkdiv + $divreg.modify(|_r, w| { + unsafe { w.div().bits($conf.div.into_bits()) } + .halt() + .asserted() + .reset() + .asserted() + }); + $divreg.modify(|_r, w| w.halt().deasserted().reset().deasserted()); + + while $divreg.read().unstab().is_unstable() {} + + Ok($freq / $conf.div.into_divisor()) + }}; +} + // config types /// This type represents a divider in the range 1..=16. @@ -217,22 +261,7 @@ impl SPConfHelper for Lpi2cConfig { }, }; - // set clksel - clksel.modify(|_r, w| w.mux().variant(variant)); - - // Set up clkdiv - clkdiv.modify(|_r, w| { - unsafe { w.div().bits(self.div.into_bits()) } - .halt() - .asserted() - .reset() - .asserted() - }); - clkdiv.modify(|_r, w| w.halt().deasserted().reset().deasserted()); - - while clkdiv.read().unstab().is_unstable() {} - - Ok(freq / self.div.into_divisor()) + apply_div4!(self, clksel, clkdiv, variant, freq) } } @@ -347,24 +376,7 @@ impl SPConfHelper for LpuartConfig { }; // set clksel - clksel.modify(|_r, w| w.mux().variant(variant)); - - // Set up clkdiv - clkdiv.modify(|_r, w| { - w.halt().asserted(); - w.reset().asserted(); - unsafe { w.div().bits(self.div.into_bits()) }; - w - }); - clkdiv.modify(|_r, w| { - w.halt().deasserted(); - w.reset().deasserted(); - w - }); - - while clkdiv.read().unstab().is_unstable() {} - - Ok(freq / self.div.into_divisor()) + apply_div4!(self, clksel, clkdiv, variant, freq) } } @@ -482,25 +494,9 @@ impl SPConfHelper for AdcConfig { return Ok(0); } }; + let clksel = mrcc0.mrcc_adc_clksel(); + let clkdiv = mrcc0.mrcc_adc_clkdiv(); - // set clksel - mrcc0.mrcc_adc_clksel().modify(|_r, w| w.mux().variant(variant)); - - // Set up clkdiv - mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { - w.halt().asserted(); - w.reset().asserted(); - unsafe { w.div().bits(self.div.into_bits()) }; - w - }); - mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { - w.halt().deasserted(); - w.reset().deasserted(); - w - }); - - while mrcc0.mrcc_adc_clkdiv().read().unstab().is_unstable() {} - - Ok(freq / self.div.into_divisor()) + apply_div4!(self, clksel, clkdiv, variant, freq) } } diff --git a/src/interrupt.rs b/src/interrupt.rs index 0490e3a66..1d10e3b2d 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -7,9 +7,26 @@ #![allow(clippy::missing_safety_doc)] mod generated { + #[rustfmt::skip] embassy_hal_internal::interrupt_mod!( - OS_EVENT, RTC, ADC1, GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPUART0, LPUART1, - LPUART2, LPUART3, LPUART4, LPUART5, + ADC1, + GPIO0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + LPI2C0, + LPI2C1, + LPI2C2, + LPI2C3, + LPUART0, + LPUART1, + LPUART2, + LPUART3, + LPUART4, + LPUART5, + OS_EVENT, + RTC, ); } -- cgit From 932d2ef38584b2f4ae926fd484a24a4829fa6cc0 Mon Sep 17 00:00:00 2001 From: Jerry Xie <139205137+jerrysxie@users.noreply.github.com> Date: Wed, 3 Dec 2025 16:55:05 -0600 Subject: Miscellaneous updates before public release (#87) This pull request introduces several updates focused on project ownership, licensing, and contribution guidelines. The main changes clarify code ownership, update the project's copyright, and reorganize the contributing documentation for better clarity. **Project Ownership and Licensing:** * Added a new `CODEOWNERS` file specifying maintainers and requiring auditor approval for changes in the `supply-chain` folder, which relates to cargo vet. * Updated the copyright in the `LICENSE` file from "OEMWCSE" to "Open Device Partnership". **Documentation and Contribution Guidelines:** * Reorganized the `CONTRIBUTING.md` file by restructuring headings, clarifying commit message and PR etiquette sections, and removing redundant or outdated guidelines for branch naming, use of `unsafe`, and commit history. **Minor Cleanups:** * Removed an unnecessary trailing blank line from the end of the `LICENSE` file. --- CODEOWNERS | 5 +++++ CONTRIBUTING.md | 26 +++----------------------- LICENSE | 3 +-- 3 files changed, 9 insertions(+), 25 deletions(-) create mode 100644 CODEOWNERS diff --git a/CODEOWNERS b/CODEOWNERS new file mode 100644 index 000000000..6e0f4c4c6 --- /dev/null +++ b/CODEOWNERS @@ -0,0 +1,5 @@ +* @jamesmunns @felipebalbi + +# Any changes in the supply-chain folder needs approval +# from auditors as it relates to cargo vet +**/supply-chain @OpenDevicePartnership/crate-auditors \ No newline at end of file diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 7c8289a58..f10eb5be9 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -14,35 +14,15 @@ you have the right to submit those contributions under those terms. If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your pull request so that the project team can discuss the situation with you. -# Contribution Guideline +## Commit Message -* For any new HAL driver added, please add corresponding test in the examples -* Format the code with `cargo fmt`. Or better yet, enable format on save in your IDE for rust source files. * Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html) -# PR Etiquette +## PR Etiquette * Create a draft PR first * Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers. -# Careful Use of `Unsafe` - -Working with embedded, using of `unsafe` is a necessity. However, please wrap unsafe code with safe interfaces to prevent `unsafe` keyword being sprinkled everywhere. - -# RFC Draft PR - -If you want feedback on your design or HAL driver early, please create a draft PR with title prefix `RFC:`. - -# Branch Naming Scheme - -For now, we're not using forks. Eventually a personal fork will be required for any PRs to limit the amount of people with merge access to the main branch. Until that happens, please use meaningful branch names like this `user_alias/feature` and avoid sending PRs from branches containing prefixes such as "wip", "test", etc. Prior to sending a PR, please rename the branch. - -# Clean Commit History - -We disabled squashing of commit and would like to maintain a clean commit history. So please reorganize your commits with the following items: - * Each commit builds successfully without warning from `rustc` or `clippy` - * Miscellaneous commits to fix typos + formatting are squashed - -# Regressions +## Regressions When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster. diff --git a/LICENSE b/LICENSE index 479657c89..609bd42da 100644 --- a/LICENSE +++ b/LICENSE @@ -1,6 +1,6 @@ MIT License -Copyright (c) 2025 OEMWCSE +Copyright (c) 2025 Open Device Partnership Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -19,4 +19,3 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -- cgit From cc918e997a8709c213c173edb8657ff269dae7a4 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 4 Dec 2025 09:14:24 -0800 Subject: i2c: controller: ensure bus works after errors (#89) Fixes: #84 --------- Signed-off-by: Felipe Balbi --- src/i2c/controller.rs | 130 +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 91 insertions(+), 39 deletions(-) diff --git a/src/i2c/controller.rs b/src/i2c/controller.rs index 818024bc9..182a53aea 100644 --- a/src/i2c/controller.rs +++ b/src/i2c/controller.rs @@ -3,6 +3,7 @@ use core::future::Future; use core::marker::PhantomData; +use embassy_hal_internal::drop::OnDrop; use embassy_hal_internal::Peri; use mcxa_pac::lpi2c0::mtdr::Cmd; @@ -118,10 +119,9 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().disabled())); // Soft-reset the controller, read and write FIFOs. + Self::reset_fifos(); critical_section::with(|_| { - T::regs() - .mcr() - .modify(|_, w| w.rst().reset().rtf().reset().rrf().reset()); + T::regs().mcr().modify(|_, w| w.rst().reset()); // According to Reference Manual section 40.7.1.4, "There // is no minimum delay required before clearing the // software reset", therefore we clear it immediately. @@ -187,20 +187,32 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { } } - fn is_tx_fifo_full(&mut self) -> bool { + /// Resets both TX and RX FIFOs dropping their contents. + fn reset_fifos() { + critical_section::with(|_| { + T::regs().mcr().modify(|_, w| w.rtf().reset().rrf().reset()); + }); + } + + /// Checks whether the TX FIFO is full + fn is_tx_fifo_full() -> bool { let txfifo_size = 1 << T::regs().param().read().mtxfifo().bits(); T::regs().mfsr().read().txcount().bits() == txfifo_size } - fn is_tx_fifo_empty(&mut self) -> bool { + /// Checks whether the TX FIFO is empty + fn is_tx_fifo_empty() -> bool { T::regs().mfsr().read().txcount() == 0 } - fn is_rx_fifo_empty(&mut self) -> bool { + /// Checks whether the RX FIFO is empty. + fn is_rx_fifo_empty() -> bool { T::regs().mfsr().read().rxcount() == 0 } - fn status(&mut self) -> Result<()> { + /// Reads and parses the controller status producing an + /// appropriate `Result<(), Error>` variant. + fn status() -> Result<()> { let msr = T::regs().msr().read(); T::regs().msr().write(|w| { w.epf() @@ -234,7 +246,11 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { } } - fn send_cmd(&mut self, cmd: Cmd, data: u8) { + /// Inserts the given command into the outgoing FIFO. + /// + /// Caller must ensure there is space in the FIFO for the new + /// command. + fn send_cmd(cmd: Cmd, data: u8) { #[cfg(feature = "defmt")] defmt::trace!( "Sending cmd '{}' ({}) with data '{:08x}' MSR: {:08x}", @@ -249,34 +265,46 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { .write(|w| unsafe { w.data().bits(data) }.cmd().variant(cmd)); } + /// Prepares an appropriate Start condition on bus by issuing a + /// `Start` command together with the device address and R/w bit. + /// + /// Blocks waiting for space in the FIFO to become available, then + /// sends the command and blocks waiting for the FIFO to become + /// empty ensuring the command was sent. fn start(&mut self, address: u8, read: bool) -> Result<()> { if address >= 0x80 { return Err(Error::AddressOutOfRange(address)); } // Wait until we have space in the TxFIFO - while self.is_tx_fifo_full() {} + while Self::is_tx_fifo_full() {} let addr_rw = address << 1 | if read { 1 } else { 0 }; - self.send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); + Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); // Wait for TxFIFO to be drained - while !self.is_tx_fifo_empty() {} + while !Self::is_tx_fifo_empty() {} // Check controller status - self.status() + Self::status() } - fn stop(&mut self) -> Result<()> { + /// Prepares a Stop condition on the bus. + /// + /// Analogous to `start`, this blocks waiting for space in the + /// FIFO to become available, then sends the command and blocks + /// waiting for the FIFO to become empty ensuring the command was + /// sent. + fn stop() -> Result<()> { // Wait until we have space in the TxFIFO - while self.is_tx_fifo_full() {} + while Self::is_tx_fifo_full() {} - self.send_cmd(Cmd::Stop, 0); + Self::send_cmd(Cmd::Stop, 0); // Wait for TxFIFO to be drained - while !self.is_tx_fifo_empty() {} + while !Self::is_tx_fifo_empty() {} - self.status() + Self::status() } fn blocking_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { @@ -288,20 +316,20 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { self.start(address, true)?; // Wait until we have space in the TxFIFO - while self.is_tx_fifo_full() {} + while Self::is_tx_fifo_full() {} - self.send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); + Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); for byte in chunk.iter_mut() { // Wait until there's data in the RxFIFO - while self.is_rx_fifo_empty() {} + while Self::is_rx_fifo_empty() {} *byte = T::regs().mrdr().read().data().bits(); } } if send_stop == SendStop::Yes { - self.stop()?; + Self::stop()?; } Ok(()) @@ -327,13 +355,13 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { for byte in write { // Wait until we have space in the TxFIFO - while self.is_tx_fifo_full() {} + while Self::is_tx_fifo_full() {} - self.send_cmd(Cmd::Transmit, *byte); + Self::send_cmd(Cmd::Transmit, *byte); } if send_stop == SendStop::Yes { - self.stop()?; + Self::stop()?; } Ok(()) @@ -344,7 +372,6 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { /// Read from address into buffer blocking caller until done. pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<()> { self.blocking_read_internal(address, read, SendStop::Yes) - // Automatic Stop } /// Write to address from buffer blocking caller until done. @@ -376,6 +403,19 @@ impl<'d, T: Instance> I2c<'d, T, Async> { Self::new_inner(peri, scl, sda, config) } + fn remediation() { + #[cfg(feature = "defmt")] + defmt::trace!("Future dropped, issuing stop",); + + // if the FIFO is not empty, drop its contents. + if !Self::is_tx_fifo_empty() { + Self::reset_fifos(); + } + + // send a stop command + let _ = Self::stop(); + } + fn enable_rx_ints(&mut self) { T::regs().mier().write(|w| { w.rdie() @@ -413,36 +453,36 @@ impl<'d, T: Instance> I2c<'d, T, Async> { // send the start command let addr_rw = address << 1 | if read { 1 } else { 0 }; - self.send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); + Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); T::wait_cell() .wait_for(|| { // enable interrupts self.enable_tx_ints(); // if the command FIFO is empty, we're done sending start - self.is_tx_fifo_empty() + Self::is_tx_fifo_empty() }) .await .map_err(|_| Error::Other)?; - self.status() + Self::status() } async fn async_stop(&mut self) -> Result<()> { // send the stop command - self.send_cmd(Cmd::Stop, 0); + Self::send_cmd(Cmd::Stop, 0); T::wait_cell() .wait_for(|| { // enable interrupts self.enable_tx_ints(); // if the command FIFO is empty, we're done sending stop - self.is_tx_fifo_empty() + Self::is_tx_fifo_empty() }) .await .map_err(|_| Error::Other)?; - self.status() + Self::status() } async fn async_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { @@ -450,18 +490,21 @@ impl<'d, T: Instance> I2c<'d, T, Async> { return Err(Error::InvalidReadBufferLength); } + // perform corrective action if the future is dropped + let on_drop = OnDrop::new(|| Self::remediation()); + for chunk in read.chunks_mut(256) { self.async_start(address, true).await?; // send receive command - self.send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); + Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); T::wait_cell() .wait_for(|| { // enable interrupts self.enable_tx_ints(); // if the command FIFO is empty, we're done sending start - self.is_tx_fifo_empty() + Self::is_tx_fifo_empty() }) .await .map_err(|_| Error::Other)?; @@ -471,8 +514,8 @@ impl<'d, T: Instance> I2c<'d, T, Async> { .wait_for(|| { // enable interrupts self.enable_rx_ints(); - // it the rx FIFO is not empty, we need to read a byte - !self.is_rx_fifo_empty() + // if the rx FIFO is not empty, we need to read a byte + !Self::is_rx_fifo_empty() }) .await .map_err(|_| Error::ReadFail)?; @@ -485,12 +528,18 @@ impl<'d, T: Instance> I2c<'d, T, Async> { self.async_stop().await?; } + // defuse it if the future is not dropped + on_drop.defuse(); + Ok(()) } async fn async_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> { self.async_start(address, false).await?; + // perform corrective action if the future is dropped + let on_drop = OnDrop::new(|| Self::remediation()); + // Usually, embassy HALs error out with an empty write, // however empty writes are useful for writing I2C scanning // logic through write probing. That is, we send a start with @@ -511,10 +560,10 @@ impl<'d, T: Instance> I2c<'d, T, Async> { .wait_for(|| { // enable interrupts self.enable_tx_ints(); - // initiate trasmit - self.send_cmd(Cmd::Transmit, *byte); - // it the rx FIFO is not empty, we're done transmiting - self.is_tx_fifo_empty() + // initiate transmit + Self::send_cmd(Cmd::Transmit, *byte); + // if the tx FIFO is empty, we're done transmiting + Self::is_tx_fifo_empty() }) .await .map_err(|_| Error::WriteFail)?; @@ -524,6 +573,9 @@ impl<'d, T: Instance> I2c<'d, T, Async> { self.async_stop().await?; } + // defuse it if the future is not dropped + on_drop.defuse(); + Ok(()) } -- cgit From 22bae2d80153003af4637c4b0cc26d52858f5228 Mon Sep 17 00:00:00 2001 From: MathisDerooNXP <52401665+MathisDeroo@users.noreply.github.com> Date: Thu, 4 Dec 2025 09:42:46 -0800 Subject: Rtc support v2 (#91) Signed-off-by: Mathis Deroo Signed-off-by: Felipe Balbi --- examples/src/bin/rtc_alarm.rs | 39 ++------- src/lib.rs | 1 - src/rtc.rs | 198 +++++++++++++++++++++++++++++++++++++----- 3 files changed, 182 insertions(+), 56 deletions(-) diff --git a/examples/src/bin/rtc_alarm.rs b/examples/src/bin/rtc_alarm.rs index a7800a2d1..fe355888b 100644 --- a/examples/src/bin/rtc_alarm.rs +++ b/examples/src/bin/rtc_alarm.rs @@ -2,23 +2,14 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa as hal; -use hal::rtc::{RtcDateTime, RtcInterruptEnable}; -use hal::InterruptExt; - -type MyRtc = hal::rtc::Rtc<'static, hal::rtc::Rtc0>; - use embassy_mcxa::bind_interrupts; -use {defmt_rtt as _, panic_probe as _}; +use hal::rtc::{InterruptHandler, Rtc, RtcDateTime}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; bind_interrupts!(struct Irqs { - RTC => hal::rtc::RtcHandler; + RTC => InterruptHandler; }); -#[used] -#[no_mangle] -static KEEP_RTC: unsafe extern "C" fn() = RTC; - #[embassy_executor::main] async fn main(_spawner: Spawner) { let p = hal::init(hal::config::Config::default()); @@ -27,7 +18,7 @@ async fn main(_spawner: Spawner) { let rtc_config = hal::rtc::get_default_config(); - let rtc = MyRtc::new(p.RTC0, rtc_config); + let mut rtc = Rtc::new(p.RTC0, Irqs, rtc_config); let now = RtcDateTime { year: 2025, @@ -46,29 +37,11 @@ async fn main(_spawner: Spawner) { let mut alarm = now; alarm.second += 10; - rtc.set_alarm(alarm); defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)"); - - rtc.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); - - unsafe { - hal::interrupt::RTC.enable(); - } - - unsafe { - cortex_m::interrupt::enable(); - } - - rtc.start(); - defmt::info!("RTC started, waiting for alarm..."); - loop { - if rtc.is_alarm_triggered() { - defmt::info!("*** ALARM TRIGGERED! ***"); - break; - } - } + rtc.wait_for_alarm(alarm).await; + defmt::info!("*** ALARM TRIGGERED! ***"); defmt::info!("Example complete - Test PASSED!"); } diff --git a/src/lib.rs b/src/lib.rs index fb204d27b..c6d8adc8f 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -333,7 +333,6 @@ pub use interrupt::InterruptExt; pub use mcxa_pac as pac; #[cfg(not(feature = "unstable-pac"))] pub(crate) use mcxa_pac as pac; -pub use rtc::Rtc0 as Rtc0Token; /// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. /// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). diff --git a/src/rtc.rs b/src/rtc.rs index b750a97ea..f975d9c9f 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -1,36 +1,52 @@ //! RTC DateTime driver. -use core::sync::atomic::{AtomicBool, Ordering}; +use core::marker::PhantomData; use embassy_hal_internal::{Peri, PeripheralType}; +use maitake_sync::WaitCell; use crate::clocks::with_clocks; +use crate::interrupt::typelevel::{Handler, Interrupt}; use crate::pac; use crate::pac::rtc0::cr::Um; type Regs = pac::rtc0::RegisterBlock; -static ALARM_TRIGGERED: AtomicBool = AtomicBool::new(false); +/// Global wait cell for alarm notifications +static WAKER: WaitCell = WaitCell::new(); -// Token-based instance pattern like embassy-imxrt +/// RTC interrupt handler. +pub struct InterruptHandler { + _phantom: PhantomData, +} + +/// Trait for RTC peripheral instances pub trait Instance: PeripheralType { + type Interrupt: Interrupt; fn ptr() -> *const Regs; } /// Token for RTC0 pub type Rtc0 = crate::peripherals::RTC0; impl Instance for crate::peripherals::RTC0 { + type Interrupt = crate::interrupt::typelevel::RTC; #[inline(always)] fn ptr() -> *const Regs { pac::Rtc0::ptr() } } +/// Number of days in a standard year const DAYS_IN_A_YEAR: u32 = 365; +/// Number of seconds in a day const SECONDS_IN_A_DAY: u32 = 86400; +/// Number of seconds in an hour const SECONDS_IN_A_HOUR: u32 = 3600; +/// Number of seconds in a minute const SECONDS_IN_A_MINUTE: u32 = 60; +/// Unix epoch start year const YEAR_RANGE_START: u16 = 1970; +/// Date and time structure for RTC operations #[derive(Debug, Clone, Copy)] pub struct RtcDateTime { pub year: u16, @@ -51,6 +67,7 @@ pub struct RtcConfig { compensation_time: u8, } +/// RTC interrupt enable flags #[derive(Copy, Clone)] pub struct RtcInterruptEnable; impl RtcInterruptEnable { @@ -60,6 +77,19 @@ impl RtcInterruptEnable { pub const RTC_SECONDS_INTERRUPT_ENABLE: u32 = 1 << 4; } +/// Converts a DateTime structure to Unix timestamp (seconds since 1970-01-01) +/// +/// # Arguments +/// +/// * `datetime` - The date and time to convert +/// +/// # Returns +/// +/// Unix timestamp as u32 +/// +/// # Note +/// +/// This function handles leap years correctly. pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 { let month_days: [u16; 13] = [0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334]; @@ -80,6 +110,19 @@ pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 { seconds } +/// Converts Unix timestamp to DateTime structure +/// +/// # Arguments +/// +/// * `seconds` - Unix timestamp (seconds since 1970-01-01) +/// +/// # Returns +/// +/// RtcDateTime structure with the converted date and time +/// +/// # Note +/// +/// This function handles leap years correctly. pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { let mut seconds_remaining = seconds; let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1; @@ -142,6 +185,15 @@ pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { } } +/// Returns default RTC configuration +/// +/// # Returns +/// +/// RtcConfig with sensible default values: +/// - No wakeup selection +/// - Update mode 0 (immediate updates) +/// - No supervisor access restriction +/// - No compensation pub fn get_default_config() -> RtcConfig { RtcConfig { wakeup_select: false, @@ -157,8 +209,12 @@ pub struct Rtc<'a, I: Instance> { } impl<'a, I: Instance> Rtc<'a, I> { - /// initialize RTC - pub fn new(_inst: Peri<'a, I>, config: RtcConfig) -> Self { + /// Create a new instance of the real time clock. + pub fn new( + _inst: Peri<'a, I>, + _irq: impl crate::interrupt::typelevel::Binding> + 'a, + config: RtcConfig, + ) -> Self { let rtc = unsafe { &*I::ptr() }; // The RTC is NOT gated by the MRCC, but we DO need to make sure the 16k clock @@ -170,7 +226,7 @@ impl<'a, I: Instance> Rtc<'a, I> { Some(Some(_)) => {} } - /* RTC reset */ + // RTC reset rtc.cr().modify(|_, w| w.swr().set_bit()); rtc.cr().modify(|_, w| w.swr().clear_bit()); rtc.tsr().write(|w| unsafe { w.bits(1) }); @@ -184,23 +240,60 @@ impl<'a, I: Instance> Rtc<'a, I> { .bits(config.compensation_time) }); + // Enable RTC interrupt + I::Interrupt::unpend(); + unsafe { I::Interrupt::enable() }; + Self { _inst: core::marker::PhantomData, } } + /// Set the current date and time + /// + /// # Arguments + /// + /// * `datetime` - The date and time to set + /// + /// # Note + /// + /// The datetime is converted to Unix timestamp and written to the time seconds register. pub fn set_datetime(&self, datetime: RtcDateTime) { let rtc = unsafe { &*I::ptr() }; let seconds = convert_datetime_to_seconds(&datetime); rtc.tsr().write(|w| unsafe { w.bits(seconds) }); } + /// Get the current date and time + /// + /// # Returns + /// + /// Current date and time as RtcDateTime + /// + /// # Note + /// + /// Reads the current Unix timestamp from the time seconds register and converts it. pub fn get_datetime(&self) -> RtcDateTime { let rtc = unsafe { &*I::ptr() }; let seconds = rtc.tsr().read().bits(); convert_seconds_to_datetime(seconds) } + /// Set the alarm date and time + /// + /// # Arguments + /// + /// * `alarm` - The date and time when the alarm should trigger + /// + /// # Note + /// + /// This function: + /// - Clears any existing alarm by writing 0 to the alarm register + /// - Waits for the clear operation to complete + /// - Sets the new alarm time + /// - Waits for the write operation to complete + /// - Uses timeouts to prevent infinite loops + /// - Enables the alarm interrupt after setting pub fn set_alarm(&self, alarm: RtcDateTime) { let rtc = unsafe { &*I::ptr() }; let seconds = convert_datetime_to_seconds(&alarm); @@ -217,24 +310,59 @@ impl<'a, I: Instance> Rtc<'a, I> { while rtc.tar().read().bits() != seconds && timeout > 0 { timeout -= 1; } + + self.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); } + /// Get the current alarm date and time + /// + /// # Returns + /// + /// Alarm date and time as RtcDateTime + /// + /// # Note + /// + /// Reads the alarm timestamp from the time alarm register and converts it. pub fn get_alarm(&self) -> RtcDateTime { let rtc = unsafe { &*I::ptr() }; let alarm_seconds = rtc.tar().read().bits(); convert_seconds_to_datetime(alarm_seconds) } + /// Start the RTC time counter + /// + /// # Note + /// + /// Sets the Time Counter Enable (TCE) bit in the status register. pub fn start(&self) { let rtc = unsafe { &*I::ptr() }; rtc.sr().modify(|_, w| w.tce().set_bit()); } + /// Stop the RTC time counter + /// + /// # Note + /// + /// Clears the Time Counter Enable (TCE) bit in the status register. pub fn stop(&self) { let rtc = unsafe { &*I::ptr() }; rtc.sr().modify(|_, w| w.tce().clear_bit()); } + /// Enable specific RTC interrupts + /// + /// # Arguments + /// + /// * `mask` - Bitmask of interrupts to enable (use RtcInterruptEnable constants) + /// + /// # Note + /// + /// This function enables the specified interrupt types and resets the alarm occurred flag. + /// Available interrupts: + /// - Time Invalid Interrupt + /// - Time Overflow Interrupt + /// - Alarm Interrupt + /// - Seconds Interrupt pub fn set_interrupt(&self, mask: u32) { let rtc = unsafe { &*I::ptr() }; @@ -250,10 +378,17 @@ impl<'a, I: Instance> Rtc<'a, I> { if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 { rtc.ier().modify(|_, w| w.tsie().tsie_1()); } - - ALARM_TRIGGERED.store(false, Ordering::SeqCst); } + /// Disable specific RTC interrupts + /// + /// # Arguments + /// + /// * `mask` - Bitmask of interrupts to disable (use RtcInterruptEnable constants) + /// + /// # Note + /// + /// This function disables the specified interrupt types. pub fn disable_interrupt(&self, mask: u32) { let rtc = unsafe { &*I::ptr() }; @@ -271,29 +406,48 @@ impl<'a, I: Instance> Rtc<'a, I> { } } + /// Clear the alarm interrupt flag + /// + /// # Note + /// + /// This function clears the Time Alarm Interrupt Enable bit. pub fn clear_alarm_flag(&self) { let rtc = unsafe { &*I::ptr() }; rtc.ier().modify(|_, w| w.taie().clear_bit()); } - pub fn is_alarm_triggered(&self) -> bool { - ALARM_TRIGGERED.load(Ordering::Relaxed) - } -} + /// Wait for an RTC alarm to trigger. + /// + /// # Arguments + /// + /// * `alarm` - The date and time when the alarm should trigger + /// This function will wait until the RTC alarm is triggered. + /// If no alarm is scheduled, it will wait indefinitely until one is scheduled and triggered. + pub async fn wait_for_alarm(&mut self, alarm: RtcDateTime) { + let wait = WAKER.subscribe().await; -pub fn on_interrupt() { - let rtc = unsafe { &*pac::Rtc0::ptr() }; - // Check if this is actually a time alarm interrupt - let sr = rtc.sr().read(); - if sr.taf().bit_is_set() { - rtc.ier().modify(|_, w| w.taie().clear_bit()); - ALARM_TRIGGERED.store(true, Ordering::SeqCst); + self.set_alarm(alarm); + self.start(); + + // REVISIT: propagate error? + let _ = wait.await; + + // Clear the interrupt and disable the alarm after waking up + self.disable_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); } } -pub struct RtcHandler; -impl crate::interrupt::typelevel::Handler for RtcHandler { +/// RTC interrupt handler +/// +/// This struct implements the interrupt handler for RTC events. +impl Handler for InterruptHandler { unsafe fn on_interrupt() { - on_interrupt(); + let rtc = &*pac::Rtc0::ptr(); + // Check if this is actually a time alarm interrupt + let sr = rtc.sr().read(); + if sr.taf().bit_is_set() { + rtc.ier().modify(|_, w| w.taie().clear_bit()); + WAKER.wake(); + } } } -- cgit From dc6bf5d44675f6f2013ddfab6b14df25a996a965 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 18:37:01 +0100 Subject: Move to subfolder --- .cargo/config.toml | 2 - .github/DOCS.md | 23 - .github/codecov.yml | 21 - .github/dependabot.yml | 19 - .github/workflows/cargo-vet-pr-comment.yml | 137 -- .github/workflows/cargo-vet.yml | 53 - .github/workflows/check.yml | 215 --- .github/workflows/nostd.yml | 38 - .github/workflows/rolling.yml | 58 - .gitignore | 19 - CODEOWNERS | 5 - CODE_OF_CONDUCT.md | 132 -- CONTRIBUTING.md | 28 - Cargo.lock | 918 ------------ Cargo.toml | 53 - Embed.toml | 28 - LICENSE | 21 - README.md | 13 - SECURITY.md | 66 - SW-Content-Register.txt | 78 - defmt.x | 6 - deny.toml | 241 --- embassy-mcxa/.cargo/config.toml | 2 + embassy-mcxa/.github/DOCS.md | 23 + embassy-mcxa/.github/codecov.yml | 21 + embassy-mcxa/.github/dependabot.yml | 19 + .../.github/workflows/cargo-vet-pr-comment.yml | 137 ++ embassy-mcxa/.github/workflows/cargo-vet.yml | 53 + embassy-mcxa/.github/workflows/check.yml | 215 +++ embassy-mcxa/.github/workflows/nostd.yml | 38 + embassy-mcxa/.github/workflows/rolling.yml | 58 + embassy-mcxa/.gitignore | 19 + embassy-mcxa/CODEOWNERS | 5 + embassy-mcxa/CODE_OF_CONDUCT.md | 132 ++ embassy-mcxa/CONTRIBUTING.md | 28 + embassy-mcxa/Cargo.lock | 918 ++++++++++++ embassy-mcxa/Cargo.toml | 53 + embassy-mcxa/Embed.toml | 28 + embassy-mcxa/LICENSE | 21 + embassy-mcxa/README.md | 13 + embassy-mcxa/SECURITY.md | 66 + embassy-mcxa/SW-Content-Register.txt | 78 + embassy-mcxa/defmt.x | 6 + embassy-mcxa/deny.toml | 241 +++ embassy-mcxa/examples/.cargo/config.toml | 17 + embassy-mcxa/examples/.gitignore | 1 + embassy-mcxa/examples/Cargo.lock | 1555 ++++++++++++++++++++ embassy-mcxa/examples/Cargo.toml | 26 + embassy-mcxa/examples/build.rs | 20 + embassy-mcxa/examples/memory.x | 5 + embassy-mcxa/examples/src/bin/adc_interrupt.rs | 84 ++ embassy-mcxa/examples/src/bin/adc_polling.rs | 68 + embassy-mcxa/examples/src/bin/blinky.rs | 36 + embassy-mcxa/examples/src/bin/button.rs | 23 + embassy-mcxa/examples/src/bin/button_async.rs | 29 + embassy-mcxa/examples/src/bin/clkout.rs | 69 + embassy-mcxa/examples/src/bin/hello.rs | 119 ++ embassy-mcxa/examples/src/bin/i2c-async.rs | 39 + embassy-mcxa/examples/src/bin/i2c-blocking.rs | 31 + embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs | 41 + embassy-mcxa/examples/src/bin/lpuart_buffered.rs | 62 + embassy-mcxa/examples/src/bin/lpuart_polling.rs | 47 + embassy-mcxa/examples/src/bin/rtc_alarm.rs | 47 + embassy-mcxa/examples/src/lib.rs | 16 + embassy-mcxa/ram.ld | 109 ++ embassy-mcxa/run.sh | 93 ++ embassy-mcxa/rustfmt.toml | 3 + embassy-mcxa/src/adc.rs | 409 +++++ embassy-mcxa/src/clkout.rs | 169 +++ embassy-mcxa/src/clocks/config.rs | 204 +++ embassy-mcxa/src/clocks/mod.rs | 943 ++++++++++++ embassy-mcxa/src/clocks/periph_helpers.rs | 502 +++++++ embassy-mcxa/src/config.rs | 27 + embassy-mcxa/src/gpio.rs | 1062 +++++++++++++ embassy-mcxa/src/i2c/controller.rs | 742 ++++++++++ embassy-mcxa/src/i2c/mod.rs | 194 +++ embassy-mcxa/src/interrupt.rs | 563 +++++++ embassy-mcxa/src/lib.rs | 471 ++++++ embassy-mcxa/src/lpuart/buffered.rs | 780 ++++++++++ embassy-mcxa/src/lpuart/mod.rs | 1292 ++++++++++++++++ embassy-mcxa/src/ostimer.rs | 745 ++++++++++ embassy-mcxa/src/pins.rs | 28 + embassy-mcxa/src/rtc.rs | 453 ++++++ embassy-mcxa/supply-chain/README.md | 149 ++ embassy-mcxa/supply-chain/audits.toml | 349 +++++ embassy-mcxa/supply-chain/config.toml | 141 ++ embassy-mcxa/supply-chain/imports.lock | 523 +++++++ embassy-mcxa/tools/run_and_attach_rtt.sh | 24 + embassy-mcxa/tools/run_jlink_noblock.sh | 76 + examples/.cargo/config.toml | 17 - examples/.gitignore | 1 - examples/Cargo.lock | 1555 -------------------- examples/Cargo.toml | 26 - examples/build.rs | 20 - examples/memory.x | 5 - examples/src/bin/adc_interrupt.rs | 84 -- examples/src/bin/adc_polling.rs | 68 - examples/src/bin/blinky.rs | 36 - examples/src/bin/button.rs | 23 - examples/src/bin/button_async.rs | 29 - examples/src/bin/clkout.rs | 69 - examples/src/bin/hello.rs | 119 -- examples/src/bin/i2c-async.rs | 39 - examples/src/bin/i2c-blocking.rs | 31 - examples/src/bin/i2c-scan-blocking.rs | 41 - examples/src/bin/lpuart_buffered.rs | 62 - examples/src/bin/lpuart_polling.rs | 47 - examples/src/bin/rtc_alarm.rs | 47 - examples/src/lib.rs | 16 - ram.ld | 109 -- run.sh | 93 -- rustfmt.toml | 3 - src/adc.rs | 409 ----- src/clkout.rs | 169 --- src/clocks/config.rs | 204 --- src/clocks/mod.rs | 943 ------------ src/clocks/periph_helpers.rs | 502 ------- src/config.rs | 27 - src/gpio.rs | 1062 ------------- src/i2c/controller.rs | 742 ---------- src/i2c/mod.rs | 194 --- src/interrupt.rs | 563 ------- src/lib.rs | 471 ------ src/lpuart/buffered.rs | 780 ---------- src/lpuart/mod.rs | 1292 ---------------- src/ostimer.rs | 745 ---------- src/pins.rs | 28 - src/rtc.rs | 453 ------ supply-chain/README.md | 149 -- supply-chain/audits.toml | 349 ----- supply-chain/config.toml | 141 -- supply-chain/imports.lock | 523 ------- tools/run_and_attach_rtt.sh | 24 - tools/run_jlink_noblock.sh | 76 - 134 files changed, 14560 insertions(+), 14560 deletions(-) delete mode 100644 .cargo/config.toml delete mode 100644 .github/DOCS.md delete mode 100644 .github/codecov.yml delete mode 100644 .github/dependabot.yml delete mode 100644 .github/workflows/cargo-vet-pr-comment.yml delete mode 100644 .github/workflows/cargo-vet.yml delete mode 100644 .github/workflows/check.yml delete mode 100644 .github/workflows/nostd.yml delete mode 100644 .github/workflows/rolling.yml delete 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delete mode 100644 src/adc.rs delete mode 100644 src/clkout.rs delete mode 100644 src/clocks/config.rs delete mode 100644 src/clocks/mod.rs delete mode 100644 src/clocks/periph_helpers.rs delete mode 100644 src/config.rs delete mode 100644 src/gpio.rs delete mode 100644 src/i2c/controller.rs delete mode 100644 src/i2c/mod.rs delete mode 100644 src/interrupt.rs delete mode 100644 src/lib.rs delete mode 100644 src/lpuart/buffered.rs delete mode 100644 src/lpuart/mod.rs delete mode 100644 src/ostimer.rs delete mode 100644 src/pins.rs delete mode 100644 src/rtc.rs delete mode 100644 supply-chain/README.md delete mode 100644 supply-chain/audits.toml delete mode 100644 supply-chain/config.toml delete mode 100644 supply-chain/imports.lock delete mode 100644 tools/run_and_attach_rtt.sh delete mode 100644 tools/run_jlink_noblock.sh diff --git a/.cargo/config.toml b/.cargo/config.toml deleted file mode 100644 index 55dd5ea5f..000000000 --- a/.cargo/config.toml +++ /dev/null @@ -1,2 +0,0 @@ -[build] -target = "thumbv8m.main-none-eabihf" # Cortex-M33 diff --git a/.github/DOCS.md b/.github/DOCS.md deleted file mode 100644 index e932784c7..000000000 --- a/.github/DOCS.md +++ /dev/null @@ -1,23 +0,0 @@ -# Github config and workflows - -In this folder there is configuration for codecoverage, dependabot, and ci -workflows that check the library more deeply than the default configurations. - -This folder can be or was merged using a --allow-unrelated-histories merge -strategy from which provides a -reasonably sensible base for writing your own ci on. By using this strategy -the history of the CI repo is included in your repo, and future updates to -the CI can be merged later. - -To perform this merge run: - -```shell -git remote add ci https://github.com/jonhoo/rust-ci-conf.git -git fetch ci -git merge --allow-unrelated-histories ci/main -``` - -An overview of the files in this project is available at: -, which contains some -rationale for decisions and runs through an example of solving minimal version -and OpenSSL issues. diff --git a/.github/codecov.yml b/.github/codecov.yml deleted file mode 100644 index cd5ce8fc1..000000000 --- a/.github/codecov.yml +++ /dev/null @@ -1,21 +0,0 @@ -# ref: https://docs.codecov.com/docs/codecovyml-reference -coverage: - # Hold ourselves to a high bar - range: 85..100 - round: down - precision: 1 - status: - # ref: https://docs.codecov.com/docs/commit-status - project: - default: - # Avoid false negatives - threshold: 1% - -# Test files aren't important for coverage -ignore: - - "tests" - -# Make comments less noisy -comment: - layout: "files" - require_changes: true diff --git a/.github/dependabot.yml b/.github/dependabot.yml deleted file mode 100644 index d0f091e7b..000000000 --- a/.github/dependabot.yml +++ /dev/null @@ -1,19 +0,0 @@ -version: 2 -updates: - - package-ecosystem: github-actions - directory: / - schedule: - interval: daily - - package-ecosystem: cargo - directory: / - schedule: - interval: daily - ignore: - - dependency-name: "*" - # patch and minor updates don't matter for libraries as consumers of this library build - # with their own lockfile, rather than the version specified in this library's lockfile - # remove this ignore rule if your package has binaries to ensure that the binaries are - # built with the exact set of dependencies and those are up to date. - update-types: - - "version-update:semver-patch" - - "version-update:semver-minor" diff --git a/.github/workflows/cargo-vet-pr-comment.yml b/.github/workflows/cargo-vet-pr-comment.yml deleted file mode 100644 index 66f27ceab..000000000 --- a/.github/workflows/cargo-vet-pr-comment.yml +++ /dev/null @@ -1,137 +0,0 @@ -# This workflow triggers after cargo-vet workflow has run. -# It adds a comment to the PR with the results of the cargo vet run. -# It first adds a comment if the cargo vet run fails, -# and updates the comment if the cargo vet run succeeds after having failed at least once. - -name: Cargo vet PR comment - -on: - workflow_run: - workflows: [cargo-vet] - types: - - completed - -permissions: - contents: read - pull-requests: write - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -jobs: - - find-pr-comment: - # This job runs when the cargo-vet job fails or succeeds - # It will download the artifact from the failed job and post a comment on the PR - runs-on: ubuntu-latest - outputs: - comment-id: ${{ steps.get-comment-id.outputs.comment-id }} - pr-number: ${{ steps.get-pr-number.outputs.pr_number }} - if: github.event.workflow_run.event == 'pull_request' - steps: - - name: 'Download artifact' - uses: actions/download-artifact@v6 - with: - github-token: ${{ secrets.GITHUB_TOKEN }} - name: pr - path: pr/ - run-id: ${{ github.event.workflow_run.id }} - - - name: 'Get PR number' - id: get-pr-number - run: echo "pr_number=$(cat ./pr/NR)" >> $GITHUB_OUTPUT - - - name: 'Find existing comment' - id: find-comment - uses: peter-evans/find-comment@v4 - with: - issue-number: ${{ steps.get-pr-number.outputs.pr_number }} - comment-author: 'github-actions[bot]' - body-includes: 'comment-tag: [cargo-vet]' - - - name: 'Get comment ID' - id: get-comment-id - if: ${{ steps.find-comment.outputs.comment-id != '' }} - run: echo "comment-id=${{ steps.find-comment.outputs.comment-id }}" >> $GITHUB_OUTPUT - - post-comment-failure: - # This job runs when the cargo-vet job fails - # It will download the artifact from the failed job and post a comment on the PR - runs-on: ubuntu-latest - needs: find-pr-comment - if: github.event.workflow_run.conclusion == 'failure' - steps: - - name: 'Comment on PR - Failure' - uses: peter-evans/create-or-update-comment@v5 - with: - comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} - issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} - body: | - # Cargo Vet Audit Failed - - `cargo vet` has failed in this PR. Please run `cargo vet --locked` locally to check for new or updated unvetted dependencies. - Details about the vetting process can be found in [supply-chain/README.md](../blob/main/supply-chain/README.md) - - ## If the unvetted dependencies are not needed - Please modify Cargo.toml file to avoid including the dependencies. - - ## If the unvetted dependencies are needed - Post a new comment with the questionnaire below to the PR to help the auditors vet the dependencies. - After the auditors have vetted the dependencies, the PR will need to be rebased to pick up the new audits and pass this check. - - ### Copy and paste the questionnaire as a new comment and provide your answers: - - **1. What crates (with version) need to be audited?** - - **2. How many of the crates are version updates vs new dependencies?** - - **3. To confirm none of the already included crates serve your needs, please provide a brief description of the purpose of the new crates.** - - **4. Any extra notes to the auditors to help with their audits.** - - - edit-mode: replace - - - name: 'Label PR' - uses: actions/github-script@v8 - with: - script: | - github.rest.issues.addLabels({ - issue_number: ${{ needs.find-pr-comment.outputs.pr-number }}, - owner: context.repo.owner, - repo: context.repo.repo, - labels: ['cargo vet'] - }) - - post-comment-success: - # This job runs when the cargo-vet job succeeds - # It will update the comment on the PR with a success message - runs-on: ubuntu-latest - needs: find-pr-comment - if: github.event.workflow_run.conclusion == 'success' - steps: - - name: 'Comment on PR - Success' - # Only update the comment if it exists - # This is to avoid creating a new comment if the cargo-vet job has never failed before - if: ${{ needs.find-pr-comment.outputs.comment-id }} - uses: peter-evans/create-or-update-comment@v5 - with: - comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} - issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} - body: | - # Cargo Vet Audit Passed - `cargo vet` has passed in this PR. No new unvetted dependencies were found. - - - edit-mode: replace diff --git a/.github/workflows/cargo-vet.yml b/.github/workflows/cargo-vet.yml deleted file mode 100644 index d585d1df5..000000000 --- a/.github/workflows/cargo-vet.yml +++ /dev/null @@ -1,53 +0,0 @@ -# This workflow runs whenever a PR is opened or updated. It runs cargo vet to check for unvetted dependencies in the Cargo.lock file. -permissions: - contents: read -on: - pull_request: - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -name: cargo-vet -jobs: - vet: - # cargo-vet checks for unvetted dependencies in the Cargo.lock file - # This is to ensure that new dependencies are vetted before they are added to the project - name: vet-dependencies - runs-on: ubuntu-latest - env: - CARGO_VET_VERSION: 0.10.1 - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - uses: actions/cache@v4 - with: - path: ${{ runner.tool_cache }}/cargo-vet - key: cargo-vet-bin-${{ env.CARGO_VET_VERSION }} - - - name: Add the tool cache directory to the search path - run: echo "${{ runner.tool_cache }}/cargo-vet/bin" >> $GITHUB_PATH - - - name: Ensure that the tool cache is populated with the cargo-vet binary - run: cargo install --root ${{ runner.tool_cache }}/cargo-vet --version ${{ env.CARGO_VET_VERSION }} cargo-vet - - - name: Invoke cargo-vet - run: cargo vet --locked - - - name: Save PR number - # PR number is saved as an artifact so it can be used to determine the PR to comment on by the vet-pr-comment workflow - # vet-pr-comment workflow is triggered by the workflow_run event so it runs in the context of the base branch and not the PR branch - if: ${{ failure() }} || ${{ success() }} - run: | - mkdir -p ./pr - echo ${{ github.event.number }} > ./pr/NR - - uses: actions/upload-artifact@v5 - # Need to upload the artifact in both success and failure cases so comment can be updated in either case - if: ${{ failure() }} || ${{ success() }} - with: - name: pr - path: pr/ - overwrite: true \ No newline at end of file diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml deleted file mode 100644 index ad9f44428..000000000 --- a/.github/workflows/check.yml +++ /dev/null @@ -1,215 +0,0 @@ -# This workflow runs whenever a PR is opened or updated, or a commit is pushed to main. It runs -# several checks: -# - fmt: checks that the code is formatted according to rustfmt -# - clippy: checks that the code does not contain any clippy warnings -# - doc: checks that the code can be documented without errors -# - hack: check combinations of feature flags -# - msrv: check that the msrv specified in the crate is correct -permissions: - contents: read - -# This configuration allows maintainers of this repo to create a branch and pull request based on -# the new branch. Restricting the push trigger to the main branch ensures that the PR only gets -# built once. -on: - - push: - branches: [main, main-nextgen] - pull_request: - -# If new code is pushed to a PR branch, then cancel in progress workflows for that PR. Ensures that -# we don't waste CI time, and returns results quicker https://github.com/jonhoo/rust-ci-conf/pull/5 -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -name: check - -jobs: - - fmt: - runs-on: ubuntu-latest - name: nightly / fmt - - strategy: - fail-fast: false - matrix: - workdir: [ ".", "examples",] - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install nightly - uses: dtolnay/rust-toolchain@nightly - with: - components: rustfmt - targets: thumbv8m.main-none-eabihf - - - name: cargo fmt --check - run: cargo fmt --check - working-directory: ${{ matrix.workdir }} - - clippy-examples: - runs-on: ubuntu-latest - name: ${{ matrix.toolchain }} / clippy - - permissions: - contents: read - checks: write - - strategy: - fail-fast: false - matrix: - # Get early warning of new lints which are regularly introduced in beta channels. - toolchain: [stable] - workdir: ["examples"] - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install ${{ matrix.toolchain }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.toolchain }} - components: clippy - targets: thumbv8m.main-none-eabihf - - - name: cargo clippy - working-directory: ${{ matrix.workdir }} - run: | - cargo clippy --locked -- -Dwarnings -D clippy::suspicious -D clippy::correctness -D clippy::perf -D clippy::style - - # Enable once we have a released crate - # semver: - # runs-on: ubuntu-latest - # name: semver - # steps: - # - uses: actions/checkout@v6 - # with: - # submodules: true - # - name: Install stable - # uses: dtolnay/rust-toolchain@stable - # with: - # components: rustfmt - # - name: cargo-semver-checks - # uses: obi1kenobi/cargo-semver-checks-action@v2 - - doc: - # run docs generation on nightly rather than stable. This enables features like - # https://doc.rust-lang.org/beta/unstable-book/language-features/doc-cfg.html which allows an - # API be documented as only available in some specific platforms. - runs-on: ubuntu-latest - name: nightly / doc - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install nightly - uses: dtolnay/rust-toolchain@nightly - with: - targets: thumbv8m.main-none-eabihf - - - name: cargo doc - run: | - cargo doc --no-deps --all-features --locked - env: - RUSTDOCFLAGS: --cfg docsrs - - hack: - # cargo-hack checks combinations of feature flags to ensure that features are all additive - # which is required for feature unification - runs-on: ubuntu-latest - name: ubuntu / stable / features - - strategy: - fail-fast: false - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - toolchain: stable - components: clippy - targets: thumbv8m.main-none-eabihf - - - name: cargo install cargo-hack - uses: taiki-e/install-action@cargo-hack - - - name: cargo hack - run: cargo hack --feature-powerset check - - deny: - # cargo-deny checks licenses, advisories, sources, and bans for - # our dependencies. - runs-on: ubuntu-latest - name: ubuntu / stable / deny - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - targets: thumbv8m.main-none-eabihf - - - name: cargo install cargo-deny - uses: EmbarkStudios/cargo-deny-action@v2 - with: - log-level: warn - manifest-path: ./Cargo.toml - command: check - arguments: --all-features --locked - - msrv: - # check that we can build using the minimal rust version that is specified by this crate - runs-on: ubuntu-latest - # we use a matrix here just because env can't be used in job names - # https://docs.github.com/en/actions/learn-github-actions/contexts#context-availability - strategy: - fail-fast: false - matrix: - msrv: ["1.91"] # We're relying on namespaced-features, which - # was released in 1.60 - # - # We also depend on `fixed' which requires rust - # 1.71 - # - # Additionally, we depend on embedded-hal-async - # which requires 1.75 - # - # embassy-time requires 1.79 due to - # collapse_debuginfo - # - # embassy upstream switched to rust 1.85 - # - # unsigned_is_multiple_of requires 1.90, else we get clippy warnings - # - # mcxa-pac@0.1.0 requires rustc 1.91 - - name: ubuntu / ${{ matrix.msrv }} - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install ${{ matrix.msrv }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.msrv }} - targets: thumbv8m.main-none-eabihf - - - name: cargo +${{ matrix.msrv }} check - run: | - cargo check --all-features --locked diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml deleted file mode 100644 index cf6629854..000000000 --- a/.github/workflows/nostd.yml +++ /dev/null @@ -1,38 +0,0 @@ -# This workflow checks whether the library is able to run without the std library (e.g., embedded). -# This entire file should be removed if this crate does not support no-std. See check.yml for -# information about how the concurrency cancellation and workflow triggering works -permissions: - contents: read - -on: - push: - branches: [main, main-nextgen] - pull_request: - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -name: no-std - -jobs: - nostd: - runs-on: ubuntu-latest - name: ${{ matrix.target }} - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - targets: thumbv8m.main-none-eabihf - - - name: Show variable - run: echo ${{ env.TOKEN }} - - - name: cargo check - run: | - cargo check --target thumbv8m.main-none-eabihf --all-features --locked diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml deleted file mode 100644 index 73b48484a..000000000 --- a/.github/workflows/rolling.yml +++ /dev/null @@ -1,58 +0,0 @@ -# This workflow runs every morning at midnight. It will run cargo hack -# and a build with msrv. If any dependency breaks our crate, we will -# know ASAP. -# -# - check: build with all features -# - msrv: check that the msrv specified in the crate is correct -permissions: - contents: read - -on: - schedule: - - cron: '0 0 * * *' - -name: rolling -jobs: - - check: - runs-on: ubuntu-latest - name: ubuntu / stable / features - strategy: - fail-fast: false - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - targets: thumbv8m.main-none-eabihf - - - name: cargo install cargo-hack - uses: taiki-e/install-action@cargo-hack - - name: cargo check - run: | - cargo update - cargo check --all-features - - msrv: - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - msrv: ["1.91"] - - name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }}) - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - name: Install ${{ matrix.msrv }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.msrv }} - targets: thumbv8m.main-none-eabihf - - name: cargo +${{ matrix.msrv }} check - run: | - cargo update - cargo check --all-features diff --git a/.gitignore b/.gitignore deleted file mode 100644 index d128a49cb..000000000 --- a/.gitignore +++ /dev/null @@ -1,19 +0,0 @@ -# Rust -/target/ - -# IDE -.vscode/ -.idea/ - -# OS -.DS_Store -Thumbs.db - -# Embedded -*.bin -*.hex -*.elf -*.map - -# Debug -*.log diff --git a/CODEOWNERS b/CODEOWNERS deleted file mode 100644 index 6e0f4c4c6..000000000 --- a/CODEOWNERS +++ /dev/null @@ -1,5 +0,0 @@ -* @jamesmunns @felipebalbi - -# Any changes in the supply-chain folder needs approval -# from auditors as it relates to cargo vet -**/supply-chain @OpenDevicePartnership/crate-auditors \ No newline at end of file diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md deleted file mode 100644 index 54a673e04..000000000 --- a/CODE_OF_CONDUCT.md +++ /dev/null @@ -1,132 +0,0 @@ -# Contributor Covenant Code of Conduct - -## Our Pledge - -We as members, contributors, and leaders pledge to make participation in our -community a harassment-free experience for everyone, regardless of age, body -size, visible or invisible disability, ethnicity, sex characteristics, gender -identity and expression, level of experience, education, socio-economic status, -nationality, personal appearance, race, caste, color, religion, or sexual -identity and orientation. - -We pledge to act and interact in ways that contribute to an open, welcoming, -diverse, inclusive, and healthy community. - -## Our Standards - -Examples of behavior that contributes to a positive environment for our -community include: - -* Demonstrating empathy and kindness toward other people -* Being respectful of differing opinions, viewpoints, and experiences -* Giving and gracefully accepting constructive feedback -* Accepting responsibility and apologizing to those affected by our mistakes, - and learning from the experience -* Focusing on what is best not just for us as individuals, but for the overall - community - -Examples of unacceptable behavior include: - -* The use of sexualized language or imagery, and sexual attention or advances of - any kind -* Trolling, insulting or derogatory comments, and personal or political attacks -* Public or private harassment -* Publishing others' private information, such as a physical or email address, - without their explicit permission -* Other conduct which could reasonably be considered inappropriate in a - professional setting - -## Enforcement Responsibilities - -Community leaders are responsible for clarifying and enforcing our standards of -acceptable behavior and will take appropriate and fair corrective action in -response to any behavior that they deem inappropriate, threatening, offensive, -or harmful. - -Community leaders have the right and responsibility to remove, edit, or reject -comments, commits, code, wiki edits, issues, and other contributions that are -not aligned to this Code of Conduct, and will communicate reasons for moderation -decisions when appropriate. - -## Scope - -This Code of Conduct applies within all community spaces, and also applies when -an individual is officially representing the community in public spaces. -Examples of representing our community include using an official e-mail address, -posting via an official social media account, or acting as an appointed -representative at an online or offline event. - -## Enforcement - -Instances of abusive, harassing, or otherwise unacceptable behavior may be -reported to the community leaders responsible for enforcement at -odpadmin@microsoft.com. -All complaints will be reviewed and investigated promptly and fairly. - -All community leaders are obligated to respect the privacy and security of the -reporter of any incident. - -## Enforcement Guidelines - -Community leaders will follow these Community Impact Guidelines in determining -the consequences for any action they deem in violation of this Code of Conduct: - -### 1. Correction - -**Community Impact**: Use of inappropriate language or other behavior deemed -unprofessional or unwelcome in the community. - -**Consequence**: A private, written warning from community leaders, providing -clarity around the nature of the violation and an explanation of why the -behavior was inappropriate. A public apology may be requested. - -### 2. Warning - -**Community Impact**: A violation through a single incident or series of -actions. - -**Consequence**: A warning with consequences for continued behavior. No -interaction with the people involved, including unsolicited interaction with -those enforcing the Code of Conduct, for a specified period of time. This -includes avoiding interactions in community spaces as well as external channels -like social media. Violating these terms may lead to a temporary or permanent -ban. - -### 3. Temporary Ban - -**Community Impact**: A serious violation of community standards, including -sustained inappropriate behavior. - -**Consequence**: A temporary ban from any sort of interaction or public -communication with the community for a specified period of time. No public or -private interaction with the people involved, including unsolicited interaction -with those enforcing the Code of Conduct, is allowed during this period. -Violating these terms may lead to a permanent ban. - -### 4. Permanent Ban - -**Community Impact**: Demonstrating a pattern of violation of community -standards, including sustained inappropriate behavior, harassment of an -individual, or aggression toward or disparagement of classes of individuals. - -**Consequence**: A permanent ban from any sort of public interaction within the -community. - -## Attribution - -This Code of Conduct is adapted from the [Contributor Covenant][homepage], -version 2.1, available at -[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1]. - -Community Impact Guidelines were inspired by -[Mozilla's code of conduct enforcement ladder][Mozilla CoC]. - -For answers to common questions about this code of conduct, see the FAQ at -[https://www.contributor-covenant.org/faq][FAQ]. Translations are available at -[https://www.contributor-covenant.org/translations][translations]. - -[homepage]: https://www.contributor-covenant.org -[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html -[Mozilla CoC]: https://github.com/mozilla/diversity -[FAQ]: https://www.contributor-covenant.org/faq -[translations]: https://www.contributor-covenant.org/translations diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md deleted file mode 100644 index f10eb5be9..000000000 --- a/CONTRIBUTING.md +++ /dev/null @@ -1,28 +0,0 @@ -# Contributing to Open Device Partnership - -The Open Device Partnership project welcomes your suggestions and contributions! Before opening your first issue or pull request, please review our -[Code of Conduct](CODE_OF_CONDUCT.md) to understand how our community interacts in an inclusive and respectful manner. - -## Contribution Licensing - -Most of our code is distributed under the terms of the [MIT license](LICENSE), and when you contribute code that you wrote to our repositories, -you agree that you are contributing under those same terms. In addition, by submitting your contributions you are indicating that -you have the right to submit those contributions under those terms. - -## Other Contribution Information - -If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your -pull request so that the project team can discuss the situation with you. - -## Commit Message - -* Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html) - -## PR Etiquette - -* Create a draft PR first -* Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers. - -## Regressions - -When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster. diff --git a/Cargo.lock b/Cargo.lock deleted file mode 100644 index 747a69c08..000000000 --- a/Cargo.lock +++ /dev/null @@ -1,918 +0,0 @@ -# This file is automatically @generated by Cargo. -# It is not intended for manual editing. -version = 4 - -[[package]] -name = "aho-corasick" -version = "1.1.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" -dependencies = [ - "memchr", -] - -[[package]] -name = "autocfg" -version = "1.5.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" - 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-# `time` dependencies -embassy-time = { version = "0.5.0", optional = true } -embassy-time-driver = { version = "0.2.1", optional = true } - -[features] -default = ["rt"] - -# Base defmt feature enables core + panic handler -# Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) -defmt = ["dep:defmt", "mcxa-pac/defmt"] - -unstable-pac = [] - -# dummy feature to silence embassy-hal-internal lint -# -# This feature makes no change to embassy-mcxa's operation. -rt = [] - -# Embassy time -time = [ - "dep:embassy-time", - "dep:embassy-time-driver", -] diff --git a/Embed.toml b/Embed.toml deleted file mode 100644 index 40218c8bf..000000000 --- a/Embed.toml +++ /dev/null @@ -1,28 +0,0 @@ -[default.probe] -# Use the first available probe -protocol = "Swd" -speed = 1000 - -[default.flashing] -# Attach-only: don't flash (we already loaded to RAM) -enabled = false - -[default.reset] -# Don't reset; keep running app started by run_jlink_noblock.sh -enabled = false - -[default.general] -# The chip name of the target -chip = "MCXA276" - -[default.gdb] -# Whether or not a GDB server should be opened after loading -enabled = false - -[default.rtt] -# Enable RTT for debugging output -enabled = true - -# Increase timeout for RTT CB discovery -up_channels = [ { channel = 0, mode = "BlockIfFull" } ] -timeout = 5000 diff --git a/LICENSE b/LICENSE deleted file mode 100644 index 609bd42da..000000000 --- a/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2025 Open Device Partnership - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/README.md b/README.md deleted file mode 100644 index 6e7d61c0e..000000000 --- a/README.md +++ /dev/null @@ -1,13 +0,0 @@ -# Embassy MCXA256 HAL - -[![check](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml) -[![no-std](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml) -[![rolling](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml) - -A Hardware Abstraction Layer (HAL) for the NXP MCXA256 microcontroller -using the Embassy async framework. This HAL provides safe, idiomatic -Rust interfaces for GPIO, UART, and OSTIMER peripherals. - -## License - -This project is licensed under MIT OR Apache-2.0. diff --git a/SECURITY.md b/SECURITY.md deleted file mode 100644 index 5357b8824..000000000 --- a/SECURITY.md +++ /dev/null @@ -1,66 +0,0 @@ -# Vulnerability Disclosure and Embargo Policy - -The Open Device Partnership project welcomes the responsible disclosure of vulnerabilities. - -## Initial Contact - -All security bugs in Open Device Partnership should be reported to the security team. -To do so, please reach out in the form of a -[Github Security Advisory](https://docs.github.com/en/code-security/security-advisories/guidance-on-reporting-and-writing-information-about-vulnerabilities). - -You will be invited to join this private area to discuss specifics. Doing so -allows us to start with a high level of confidentiality and relax it if the -issue is less critical, moving to work on the fix in the open. - -Your initial contact will be acknowledged within 48 hours, and you’ll receive -a more detailed response within 96 hours indicating the next steps in handling -your report. - -After the initial reply to your report, the security team will endeavor to -keep you informed of the progress being made towards a fix and full -announcement. As recommended by -[RFPolicy](https://dl.packetstormsecurity.net/papers/general/rfpolicy-2.0.txt), -these updates will be sent at least every five working days. - -## Disclosure Policy - -The Open Device Partnership project has a 5 step disclosure process. - -1. Contact is established, a private channel created, and the security report - is received and is assigned a primary handler. This person will coordinate - the fix and release process. -2. The problem is confirmed and a list of all affected versions is determined. - If an embargo is needed (see below), details of the embargo are decided. -3. Code is audited to find any potential similar problems. -4. Fixes are prepared for all releases which are still under maintenance. In - case of embargo, these fixes are not committed to the public repository but - rather held in a private fork pending the announcement. -5. The changes are pushed to the public repository and new builds are deployed. - -This process can take some time, especially when coordination is required -with maintainers of other projects. Every effort will be made to handle the bug -in as timely a manner as possible, however it is important that we follow the -release process above to ensure that the disclosure is handled in a consistent -manner. - -## Embargoes - -While the Open Device Partnership project aims to follow the highest standards of -transparency and openness, handling some security issues may pose such an -immediate threat to various stakeholders and require coordination between -various actors that it cannot be made immediately public. - -In this case, security issues will fall under an embargo. - -An embargo can be called for in various cases: - -- when disclosing the issue without simultaneously providing a mitigation - would seriously endanger users, -- when producing a fix requires coordinating between multiple actors (such as - upstream or downstream/dependency projects), or simply -- when proper analysis of the issue and its ramifications demands time. - -If we determine that an issue you report requires an embargo, we will discuss -this with you and try to find a reasonable expiry date (aka “embargo -completion date”), as well as who should be included in the list of -need-to-know people. diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt deleted file mode 100644 index 09f879c2f..000000000 --- a/SW-Content-Register.txt +++ /dev/null @@ -1,78 +0,0 @@ -Release Name: Embassy MCXA276 HAL -Release Version: 0.1.0 -Package License: MIT (see ./License.txt) -Note: The crate is dual-licensed “MIT OR Apache-2.0” per Cargo.toml; choosing MIT satisfies the dual-license terms. - -Scope of this Register -This file documents software content that is part of this repository and, for transparency, lists major non-vendored Rust dependencies that are resolved from crates.io during builds. Components that are not present in the repository (e.g., external crates) are listed under “Non‑vendored Rust dependencies”. - -Repository Components (included in this release) - -embassy_mcxa276_hal Name: Embassy MCXA276 HAL (library + examples) - Version: 0.1.0 - Outgoing License: MIT - License File: ./License.txt - Format: Rust source code, examples, scripts, linker scripts - Description: Hardware Abstraction Layer for NXP MCXA276 using the Embassy async framework. Implements drivers and helpers for: - - LPUART2 (UART), OSTIMER0, RTC0, ADC1, GPIO - - Embassy integration (executors, time) - Location: ./src, ./examples, ./build.rs, ./memory.x, ./ram.ld, ./defmt.x, ./.cargo/config.toml, ./run.sh, ./tools/ - Origin: OEMWCSE (MIT) - URL: https://bitbucket.sw.nxp.com/scm/oemwcse/mcxa_rust.git - -mcxa276_pac Name: MCXA276 Peripheral Access Crate (PAC) - Version: 0.1.0 - Outgoing License: MIT OR Apache-2.0 - License File: (see crate metadata) - Format: Rust source code (auto-generated PAC) - Description: Auto-generated register mappings for MCXA276 peripherals (svd2rust). Includes device.x and interrupt vectors. - Location: External (git): https://github.com/bogdan-petru/mcxa-pac (pinned rev a9dd3301) - Origin: Generated by svdtools + svd2rust from NXP SVD 25.06.00 - URL: N/A (generated from NXP SVD) - -examples Name: Example applications - Version: N/A - Outgoing License: MIT - License File: ./License.txt - Format: Rust source code (examples) - Description: Demonstrations for HAL peripherals and features: - - hello, blink - - lpuart_polling, lpuart_buffered, uart_interrupt - - rtc_alarm - - adc_polling, adc_interrupt - - ostimer_alarm, ostimer_async, ostimer_counter, ostimer_race_test - Location: ./examples - Origin: OEMWCSE (MIT) - -Non‑vendored Rust dependencies (resolved from crates.io at build time) -The following crates are not vendored in this repository. They are fetched during builds via Cargo. See Cargo.lock for exact versions. License summaries below are for convenience; consult each crate for authoritative terms. - -cortex-m License: MIT OR Apache-2.0 Purpose: Cortex-M core support -cortex-m-rt License: MIT OR Apache-2.0 Purpose: Cortex-M runtime (vectors, reset) -embassy-executor License: MIT OR Apache-2.0 Purpose: Async executor for Cortex-M -embassy-time (+ driver) License: MIT OR Apache-2.0 Purpose: Time abstraction and drivers -embassy-sync License: MIT OR Apache-2.0 Purpose: No-std synchronization primitives -embassy-embedded-hal License: MIT OR Apache-2.0 Purpose: Traits/adapters for embedded-hal -embassy-hal-internal License: MIT OR Apache-2.0 Purpose: HAL building blocks (peripherals!) -embedded-hal (1.0) License: MIT OR Apache-2.0 Purpose: Core embedded hardware traits -embedded-hal (0.2.6) License: MIT OR Apache-2.0 Purpose: Legacy HAL traits ("unproven") -embedded-hal-async License: MIT OR Apache-2.0 Purpose: Async HAL traits -embedded-hal-nb License: MIT OR Apache-2.0 Purpose: Non-blocking HAL traits -embedded-io / embedded-io-async License: MIT OR Apache-2.0 Purpose: IO traits -critical-section License: MIT OR Apache-2.0 Purpose: Critical-section abstraction -heapless License: MIT OR Apache-2.0 Purpose: Fixed-capacity data structures -paste License: MIT OR Apache-2.0 Purpose: Macro hygiene utility -nb License: MIT OR Apache-2.0 Purpose: Non-blocking result type -vcell License: MIT OR Apache-2.0 Purpose: Volatile cell (PAC dependency) - -defmt, defmt-rtt, rtt-target, panic-probe License: MIT OR Apache-2.0 Purpose: Optional (feature-gated) logging/panic crates - -Attribution notes -- MCXA276 PAC is sourced as an external dependency (see Cargo.toml). SVD 25.06.00 already includes OS_EVENT and WAKETIMER0 interrupts (no local fixes). -- Examples run from RAM using custom linker setup; see README.txt for platform-specific instructions. - -Compliance -- This repository’s distributed source is covered by MIT (see License.txt). Where crates are pulled from crates.io, those crates retain their own licenses; the dual-license compatibility (MIT OR Apache-2.0) is standard in the Rust embedded ecosystem and is compatible with this project’s selected MIT distribution. - - - diff --git a/defmt.x b/defmt.x deleted file mode 100644 index dbd6d0850..000000000 --- a/defmt.x +++ /dev/null @@ -1,6 +0,0 @@ -/* - Dummy defmt.x to satisfy -Tdefmt.x when building without the `defmt` feature. - When `defmt` is enabled, the real defmt.x provided by the defmt crate is used via the linker search path. - This file intentionally contains no SECTIONS so it won't override ram.ld. -*/ - diff --git a/deny.toml b/deny.toml deleted file mode 100644 index 7097f2f55..000000000 --- a/deny.toml +++ /dev/null @@ -1,241 +0,0 @@ -# This template contains all of the possible sections and their default values - -# Note that all fields that take a lint level have these possible values: -# * deny - An error will be produced and the check will fail -# * warn - A warning will be produced, but the check will not fail -# * allow - No warning or error will be produced, though in some cases a note -# will be - -# The values provided in this template are the default values that will be used -# when any section or field is not specified in your own configuration - -# Root options - -# The graph table configures how the dependency graph is constructed and thus -# which crates the checks are performed against -[graph] -# If 1 or more target triples (and optionally, target_features) are specified, -# only the specified targets will be checked when running `cargo deny check`. -# This means, if a particular package is only ever used as a target specific -# dependency, such as, for example, the `nix` crate only being used via the -# `target_family = "unix"` configuration, that only having windows targets in -# this list would mean the nix crate, as well as any of its exclusive -# dependencies not shared by any other crates, would be ignored, as the target -# list here is effectively saying which targets you are building for. -targets = [ - # The triple can be any string, but only the target triples built in to - # rustc (as of 1.40) can be checked against actual config expressions - #"x86_64-unknown-linux-musl", - # You can also specify which target_features you promise are enabled for a - # particular target. target_features are currently not validated against - # the actual valid features supported by the target architecture. - #{ triple = "wasm32-unknown-unknown", features = ["atomics"] }, -] -# When creating the dependency graph used as the source of truth when checks are -# executed, this field can be used to prune crates from the graph, removing them -# from the view of cargo-deny. This is an extremely heavy hammer, as if a crate -# is pruned from the graph, all of its dependencies will also be pruned unless -# they are connected to another crate in the graph that hasn't been pruned, -# so it should be used with care. The identifiers are [Package ID Specifications] -# (https://doc.rust-lang.org/cargo/reference/pkgid-spec.html) -#exclude = [] -# If true, metadata will be collected with `--all-features`. Note that this can't -# be toggled off if true, if you want to conditionally enable `--all-features` it -# is recommended to pass `--all-features` on the cmd line instead -all-features = false -# If true, metadata will be collected with `--no-default-features`. The same -# caveat with `all-features` applies -no-default-features = false -# If set, these feature will be enabled when collecting metadata. If `--features` -# is specified on the cmd line they will take precedence over this option. -#features = [] - -# The output table provides options for how/if diagnostics are outputted -[output] -# When outputting inclusion graphs in diagnostics that include features, this -# option can be used to specify the depth at which feature edges will be added. -# This option is included since the graphs can be quite large and the addition -# of features from the crate(s) to all of the graph roots can be far too verbose. -# This option can be overridden via `--feature-depth` on the cmd line -feature-depth = 1 - -# This section is considered when running `cargo deny check advisories` -# More documentation for the advisories section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/advisories/cfg.html -[advisories] -# The path where the advisory databases are cloned/fetched into -#db-path = "$CARGO_HOME/advisory-dbs" -# The url(s) of the advisory databases to use -#db-urls = ["https://github.com/rustsec/advisory-db"] -# A list of advisory IDs to ignore. Note that ignored advisories will still -# output a note when they are encountered. -ignore = [ - #"RUSTSEC-0000-0000", - #{ id = "RUSTSEC-0000-0000", reason = "you can specify a reason the advisory is ignored" }, - #"a-crate-that-is-yanked@0.1.1", # you can also ignore yanked crate versions if you wish - #{ crate = "a-crate-that-is-yanked@0.1.1", reason = "you can specify why you are ignoring the yanked crate" }, - # { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." }, - { id = "RUSTSEC-2024-0436", reason = "there are no suitable replacements for paste right now; paste has been archived as read-only. It only affects compile time concatenation in macros. We will allow it for now" }, - # { id = "RUSTSEC-2023-0089", reason = "this is a deprecation warning for a dependency of a dependency. https://github.com/jamesmunns/postcard/issues/223 tracks fixing the dependency; until that's resolved, we can accept the deprecated code as it has no known vulnerabilities."} -] -# If this is true, then cargo deny will use the git executable to fetch advisory database. -# If this is false, then it uses a built-in git library. -# Setting this to true can be helpful if you have special authentication requirements that cargo-deny does not support. -# See Git Authentication for more information about setting up git authentication. -#git-fetch-with-cli = true - -# This section is considered when running `cargo deny check licenses` -# More documentation for the licenses section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/licenses/cfg.html -[licenses] -# List of explicitly allowed licenses -# See https://spdx.org/licenses/ for list of possible licenses -# [possible values: any SPDX 3.11 short identifier (+ optional exception)]. -allow = [ - "MIT", - "Apache-2.0", - - # unicode-ident 1.0.14 switched from Unicode-DFS-2016 to Unicode-3.0 license. - "Unicode-3.0", - #"Apache-2.0 WITH LLVM-exception", -] -# The confidence threshold for detecting a license from license text. -# The higher the value, the more closely the license text must be to the -# canonical license text of a valid SPDX license file. -# [possible values: any between 0.0 and 1.0]. -confidence-threshold = 0.8 -# Allow 1 or more licenses on a per-crate basis, so that particular licenses -# aren't accepted for every possible crate as with the normal allow list -exceptions = [ - # Each entry is the crate and version constraint, and its specific allow - # list - #{ allow = ["Zlib"], crate = "adler32" }, -] - -# Some crates don't have (easily) machine readable licensing information, -# adding a clarification entry for it allows you to manually specify the -# licensing information -#[[licenses.clarify]] -# The package spec the clarification applies to -#crate = "ring" -# The SPDX expression for the license requirements of the crate -#expression = "MIT AND ISC AND OpenSSL" -# One or more files in the crate's source used as the "source of truth" for -# the license expression. If the contents match, the clarification will be used -# when running the license check, otherwise the clarification will be ignored -# and the crate will be checked normally, which may produce warnings or errors -# depending on the rest of your configuration -#license-files = [ -# Each entry is a crate relative path, and the (opaque) hash of its contents -#{ path = "LICENSE", hash = 0xbd0eed23 } -#] - -[licenses.private] -# If true, ignores workspace crates that aren't published, or are only -# published to private registries. -# To see how to mark a crate as unpublished (to the official registry), -# visit https://doc.rust-lang.org/cargo/reference/manifest.html#the-publish-field. -ignore = false -# One or more private registries that you might publish crates to, if a crate -# is only published to private registries, and ignore is true, the crate will -# not have its license(s) checked -registries = [ - #"https://sekretz.com/registry -] - -# This section is considered when running `cargo deny check bans`. -# More documentation about the 'bans' section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/bans/cfg.html -[bans] -# Lint level for when multiple versions of the same crate are detected -multiple-versions = "warn" -# Lint level for when a crate version requirement is `*` -wildcards = "allow" -# The graph highlighting used when creating dotgraphs for crates -# with multiple versions -# * lowest-version - The path to the lowest versioned duplicate is highlighted -# * simplest-path - The path to the version with the fewest edges is highlighted -# * all - Both lowest-version and simplest-path are used -highlight = "all" -# The default lint level for `default` features for crates that are members of -# the workspace that is being checked. This can be overridden by allowing/denying -# `default` on a crate-by-crate basis if desired. -workspace-default-features = "allow" -# The default lint level for `default` features for external crates that are not -# members of the workspace. This can be overridden by allowing/denying `default` -# on a crate-by-crate basis if desired. -external-default-features = "allow" -# List of crates that are allowed. Use with care! -allow = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is allowed" }, -] -# List of crates to deny -deny = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is banned" }, - # Wrapper crates can optionally be specified to allow the crate when it - # is a direct dependency of the otherwise banned crate - #{ crate = "ansi_term@0.11.0", wrappers = ["this-crate-directly-depends-on-ansi_term"] }, -] - -# List of features to allow/deny -# Each entry the name of a crate and a version range. If version is -# not specified, all versions will be matched. -#[[bans.features]] -#crate = "reqwest" -# Features to not allow -#deny = ["json"] -# Features to allow -#allow = [ -# "rustls", -# "__rustls", -# "__tls", -# "hyper-rustls", -# "rustls", -# "rustls-pemfile", -# "rustls-tls-webpki-roots", -# "tokio-rustls", -# "webpki-roots", -#] -# If true, the allowed features must exactly match the enabled feature set. If -# this is set there is no point setting `deny` -#exact = true - -# Certain crates/versions that will be skipped when doing duplicate detection. -skip = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason why it can't be updated/removed" }, -] -# Similarly to `skip` allows you to skip certain crates during duplicate -# detection. Unlike skip, it also includes the entire tree of transitive -# dependencies starting at the specified crate, up to a certain depth, which is -# by default infinite. -skip-tree = [ - #"ansi_term@0.11.0", # will be skipped along with _all_ of its direct and transitive dependencies - #{ crate = "ansi_term@0.11.0", depth = 20 }, -] - -# This section is considered when running `cargo deny check sources`. -# More documentation about the 'sources' section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/sources/cfg.html -[sources] -# Lint level for what to happen when a crate from a crate registry that is not -# in the allow list is encountered -unknown-registry = "warn" -# Lint level for what to happen when a crate from a git repository that is not -# in the allow list is encountered -unknown-git = "warn" -# List of URLs for allowed crate registries. Defaults to the crates.io index -# if not specified. If it is specified but empty, no registries are allowed. -allow-registry = ["https://github.com/rust-lang/crates.io-index"] -# List of URLs for allowed Git repositories -allow-git = [] - -[sources.allow-org] -# github.com organizations to allow git sources for -github = ["OpenDevicePartnership"] -# gitlab.com organizations to allow git sources for -gitlab = [] -# bitbucket.org organizations to allow git sources for -bitbucket = [] diff --git a/embassy-mcxa/.cargo/config.toml b/embassy-mcxa/.cargo/config.toml new file mode 100644 index 000000000..55dd5ea5f --- /dev/null +++ b/embassy-mcxa/.cargo/config.toml @@ -0,0 +1,2 @@ +[build] +target = "thumbv8m.main-none-eabihf" # Cortex-M33 diff --git a/embassy-mcxa/.github/DOCS.md b/embassy-mcxa/.github/DOCS.md new file mode 100644 index 000000000..e932784c7 --- /dev/null +++ b/embassy-mcxa/.github/DOCS.md @@ -0,0 +1,23 @@ +# Github config and workflows + +In this folder there is configuration for codecoverage, dependabot, and ci +workflows that check the library more deeply than the default configurations. + +This folder can be or was merged using a --allow-unrelated-histories merge +strategy from which provides a +reasonably sensible base for writing your own ci on. By using this strategy +the history of the CI repo is included in your repo, and future updates to +the CI can be merged later. + +To perform this merge run: + +```shell +git remote add ci https://github.com/jonhoo/rust-ci-conf.git +git fetch ci +git merge --allow-unrelated-histories ci/main +``` + +An overview of the files in this project is available at: +, which contains some +rationale for decisions and runs through an example of solving minimal version +and OpenSSL issues. diff --git a/embassy-mcxa/.github/codecov.yml b/embassy-mcxa/.github/codecov.yml new file mode 100644 index 000000000..cd5ce8fc1 --- /dev/null +++ b/embassy-mcxa/.github/codecov.yml @@ -0,0 +1,21 @@ +# ref: https://docs.codecov.com/docs/codecovyml-reference +coverage: + # Hold ourselves to a high bar + range: 85..100 + round: down + precision: 1 + status: + # ref: https://docs.codecov.com/docs/commit-status + project: + default: + # Avoid false negatives + threshold: 1% + +# Test files aren't important for coverage +ignore: + - "tests" + +# Make comments less noisy +comment: + layout: "files" + require_changes: true diff --git a/embassy-mcxa/.github/dependabot.yml b/embassy-mcxa/.github/dependabot.yml new file mode 100644 index 000000000..d0f091e7b --- /dev/null +++ b/embassy-mcxa/.github/dependabot.yml @@ -0,0 +1,19 @@ +version: 2 +updates: + - package-ecosystem: github-actions + directory: / + schedule: + interval: daily + - package-ecosystem: cargo + directory: / + schedule: + interval: daily + ignore: + - dependency-name: "*" + # patch and minor updates don't matter for libraries as consumers of this library build + # with their own lockfile, rather than the version specified in this library's lockfile + # remove this ignore rule if your package has binaries to ensure that the binaries are + # built with the exact set of dependencies and those are up to date. + update-types: + - "version-update:semver-patch" + - "version-update:semver-minor" diff --git a/embassy-mcxa/.github/workflows/cargo-vet-pr-comment.yml b/embassy-mcxa/.github/workflows/cargo-vet-pr-comment.yml new file mode 100644 index 000000000..66f27ceab --- /dev/null +++ b/embassy-mcxa/.github/workflows/cargo-vet-pr-comment.yml @@ -0,0 +1,137 @@ +# This workflow triggers after cargo-vet workflow has run. +# It adds a comment to the PR with the results of the cargo vet run. +# It first adds a comment if the cargo vet run fails, +# and updates the comment if the cargo vet run succeeds after having failed at least once. + +name: Cargo vet PR comment + +on: + workflow_run: + workflows: [cargo-vet] + types: + - completed + +permissions: + contents: read + pull-requests: write + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +jobs: + + find-pr-comment: + # This job runs when the cargo-vet job fails or succeeds + # It will download the artifact from the failed job and post a comment on the PR + runs-on: ubuntu-latest + outputs: + comment-id: ${{ steps.get-comment-id.outputs.comment-id }} + pr-number: ${{ steps.get-pr-number.outputs.pr_number }} + if: github.event.workflow_run.event == 'pull_request' + steps: + - name: 'Download artifact' + uses: actions/download-artifact@v6 + with: + github-token: ${{ secrets.GITHUB_TOKEN }} + name: pr + path: pr/ + run-id: ${{ github.event.workflow_run.id }} + + - name: 'Get PR number' + id: get-pr-number + run: echo "pr_number=$(cat ./pr/NR)" >> $GITHUB_OUTPUT + + - name: 'Find existing comment' + id: find-comment + uses: peter-evans/find-comment@v4 + with: + issue-number: ${{ steps.get-pr-number.outputs.pr_number }} + comment-author: 'github-actions[bot]' + body-includes: 'comment-tag: [cargo-vet]' + + - name: 'Get comment ID' + id: get-comment-id + if: ${{ steps.find-comment.outputs.comment-id != '' }} + run: echo "comment-id=${{ steps.find-comment.outputs.comment-id }}" >> $GITHUB_OUTPUT + + post-comment-failure: + # This job runs when the cargo-vet job fails + # It will download the artifact from the failed job and post a comment on the PR + runs-on: ubuntu-latest + needs: find-pr-comment + if: github.event.workflow_run.conclusion == 'failure' + steps: + - name: 'Comment on PR - Failure' + uses: peter-evans/create-or-update-comment@v5 + with: + comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} + issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} + body: | + # Cargo Vet Audit Failed + + `cargo vet` has failed in this PR. Please run `cargo vet --locked` locally to check for new or updated unvetted dependencies. + Details about the vetting process can be found in [supply-chain/README.md](../blob/main/supply-chain/README.md) + + ## If the unvetted dependencies are not needed + Please modify Cargo.toml file to avoid including the dependencies. + + ## If the unvetted dependencies are needed + Post a new comment with the questionnaire below to the PR to help the auditors vet the dependencies. + After the auditors have vetted the dependencies, the PR will need to be rebased to pick up the new audits and pass this check. + + ### Copy and paste the questionnaire as a new comment and provide your answers: + + **1. What crates (with version) need to be audited?** + + **2. How many of the crates are version updates vs new dependencies?** + + **3. To confirm none of the already included crates serve your needs, please provide a brief description of the purpose of the new crates.** + + **4. Any extra notes to the auditors to help with their audits.** + + + edit-mode: replace + + - name: 'Label PR' + uses: actions/github-script@v8 + with: + script: | + github.rest.issues.addLabels({ + issue_number: ${{ needs.find-pr-comment.outputs.pr-number }}, + owner: context.repo.owner, + repo: context.repo.repo, + labels: ['cargo vet'] + }) + + post-comment-success: + # This job runs when the cargo-vet job succeeds + # It will update the comment on the PR with a success message + runs-on: ubuntu-latest + needs: find-pr-comment + if: github.event.workflow_run.conclusion == 'success' + steps: + - name: 'Comment on PR - Success' + # Only update the comment if it exists + # This is to avoid creating a new comment if the cargo-vet job has never failed before + if: ${{ needs.find-pr-comment.outputs.comment-id }} + uses: peter-evans/create-or-update-comment@v5 + with: + comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} + issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} + body: | + # Cargo Vet Audit Passed + `cargo vet` has passed in this PR. No new unvetted dependencies were found. + + + edit-mode: replace diff --git a/embassy-mcxa/.github/workflows/cargo-vet.yml b/embassy-mcxa/.github/workflows/cargo-vet.yml new file mode 100644 index 000000000..d585d1df5 --- /dev/null +++ b/embassy-mcxa/.github/workflows/cargo-vet.yml @@ -0,0 +1,53 @@ +# This workflow runs whenever a PR is opened or updated. It runs cargo vet to check for unvetted dependencies in the Cargo.lock file. +permissions: + contents: read +on: + pull_request: + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +name: cargo-vet +jobs: + vet: + # cargo-vet checks for unvetted dependencies in the Cargo.lock file + # This is to ensure that new dependencies are vetted before they are added to the project + name: vet-dependencies + runs-on: ubuntu-latest + env: + CARGO_VET_VERSION: 0.10.1 + + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - uses: actions/cache@v4 + with: + path: ${{ runner.tool_cache }}/cargo-vet + key: cargo-vet-bin-${{ env.CARGO_VET_VERSION }} + + - name: Add the tool cache directory to the search path + run: echo "${{ runner.tool_cache }}/cargo-vet/bin" >> $GITHUB_PATH + + - name: Ensure that the tool cache is populated with the cargo-vet binary + run: cargo install --root ${{ runner.tool_cache }}/cargo-vet --version ${{ env.CARGO_VET_VERSION }} cargo-vet + + - name: Invoke cargo-vet + run: cargo vet --locked + + - name: Save PR number + # PR number is saved as an artifact so it can be used to determine the PR to comment on by the vet-pr-comment workflow + # vet-pr-comment workflow is triggered by the workflow_run event so it runs in the context of the base branch and not the PR branch + if: ${{ failure() }} || ${{ success() }} + run: | + mkdir -p ./pr + echo ${{ github.event.number }} > ./pr/NR + - uses: actions/upload-artifact@v5 + # Need to upload the artifact in both success and failure cases so comment can be updated in either case + if: ${{ failure() }} || ${{ success() }} + with: + name: pr + path: pr/ + overwrite: true \ No newline at end of file diff --git a/embassy-mcxa/.github/workflows/check.yml b/embassy-mcxa/.github/workflows/check.yml new file mode 100644 index 000000000..ad9f44428 --- /dev/null +++ b/embassy-mcxa/.github/workflows/check.yml @@ -0,0 +1,215 @@ +# This workflow runs whenever a PR is opened or updated, or a commit is pushed to main. It runs +# several checks: +# - fmt: checks that the code is formatted according to rustfmt +# - clippy: checks that the code does not contain any clippy warnings +# - doc: checks that the code can be documented without errors +# - hack: check combinations of feature flags +# - msrv: check that the msrv specified in the crate is correct +permissions: + contents: read + +# This configuration allows maintainers of this repo to create a branch and pull request based on +# the new branch. Restricting the push trigger to the main branch ensures that the PR only gets +# built once. +on: + + push: + branches: [main, main-nextgen] + pull_request: + +# If new code is pushed to a PR branch, then cancel in progress workflows for that PR. Ensures that +# we don't waste CI time, and returns results quicker https://github.com/jonhoo/rust-ci-conf/pull/5 +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +name: check + +jobs: + + fmt: + runs-on: ubuntu-latest + name: nightly / fmt + + strategy: + fail-fast: false + matrix: + workdir: [ ".", "examples",] + + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - name: Install nightly + uses: dtolnay/rust-toolchain@nightly + with: + components: rustfmt + targets: thumbv8m.main-none-eabihf + + - name: cargo fmt --check + run: cargo fmt --check + working-directory: ${{ matrix.workdir }} + + clippy-examples: + runs-on: ubuntu-latest + name: ${{ matrix.toolchain }} / clippy + + permissions: + contents: read + checks: write + + strategy: + fail-fast: false + matrix: + # Get early warning of new lints which are regularly introduced in beta channels. + toolchain: [stable] + workdir: ["examples"] + + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - name: Install ${{ matrix.toolchain }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.toolchain }} + components: clippy + targets: thumbv8m.main-none-eabihf + + - name: cargo clippy + working-directory: ${{ matrix.workdir }} + run: | + cargo clippy --locked -- -Dwarnings -D clippy::suspicious -D clippy::correctness -D clippy::perf -D clippy::style + + # Enable once we have a released crate + # semver: + # runs-on: ubuntu-latest + # name: semver + # steps: + # - uses: actions/checkout@v6 + # with: + # submodules: true + # - name: Install stable + # uses: dtolnay/rust-toolchain@stable + # with: + # components: rustfmt + # - name: cargo-semver-checks + # uses: obi1kenobi/cargo-semver-checks-action@v2 + + doc: + # run docs generation on nightly rather than stable. This enables features like + # https://doc.rust-lang.org/beta/unstable-book/language-features/doc-cfg.html which allows an + # API be documented as only available in some specific platforms. + runs-on: ubuntu-latest + name: nightly / doc + + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - name: Install nightly + uses: dtolnay/rust-toolchain@nightly + with: + targets: thumbv8m.main-none-eabihf + + - name: cargo doc + run: | + cargo doc --no-deps --all-features --locked + env: + RUSTDOCFLAGS: --cfg docsrs + + hack: + # cargo-hack checks combinations of feature flags to ensure that features are all additive + # which is required for feature unification + runs-on: ubuntu-latest + name: ubuntu / stable / features + + strategy: + fail-fast: false + + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - name: Install stable + uses: dtolnay/rust-toolchain@stable + with: + toolchain: stable + components: clippy + targets: thumbv8m.main-none-eabihf + + - name: cargo install cargo-hack + uses: taiki-e/install-action@cargo-hack + + - name: cargo hack + run: cargo hack --feature-powerset check + + deny: + # cargo-deny checks licenses, advisories, sources, and bans for + # our dependencies. + runs-on: ubuntu-latest + name: ubuntu / stable / deny + + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - name: Install stable + uses: dtolnay/rust-toolchain@stable + with: + targets: thumbv8m.main-none-eabihf + + - name: cargo install cargo-deny + uses: EmbarkStudios/cargo-deny-action@v2 + with: + log-level: warn + manifest-path: ./Cargo.toml + command: check + arguments: --all-features --locked + + msrv: + # check that we can build using the minimal rust version that is specified by this crate + runs-on: ubuntu-latest + # we use a matrix here just because env can't be used in job names + # https://docs.github.com/en/actions/learn-github-actions/contexts#context-availability + strategy: + fail-fast: false + matrix: + msrv: ["1.91"] # We're relying on namespaced-features, which + # was released in 1.60 + # + # We also depend on `fixed' which requires rust + # 1.71 + # + # Additionally, we depend on embedded-hal-async + # which requires 1.75 + # + # embassy-time requires 1.79 due to + # collapse_debuginfo + # + # embassy upstream switched to rust 1.85 + # + # unsigned_is_multiple_of requires 1.90, else we get clippy warnings + # + # mcxa-pac@0.1.0 requires rustc 1.91 + + name: ubuntu / ${{ matrix.msrv }} + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - name: Install ${{ matrix.msrv }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.msrv }} + targets: thumbv8m.main-none-eabihf + + - name: cargo +${{ matrix.msrv }} check + run: | + cargo check --all-features --locked diff --git a/embassy-mcxa/.github/workflows/nostd.yml b/embassy-mcxa/.github/workflows/nostd.yml new file mode 100644 index 000000000..cf6629854 --- /dev/null +++ b/embassy-mcxa/.github/workflows/nostd.yml @@ -0,0 +1,38 @@ +# This workflow checks whether the library is able to run without the std library (e.g., embedded). +# This entire file should be removed if this crate does not support no-std. See check.yml for +# information about how the concurrency cancellation and workflow triggering works +permissions: + contents: read + +on: + push: + branches: [main, main-nextgen] + pull_request: + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} + cancel-in-progress: true + +name: no-std + +jobs: + nostd: + runs-on: ubuntu-latest + name: ${{ matrix.target }} + + steps: + - uses: actions/checkout@v6 + with: + submodules: true + + - name: Install stable + uses: dtolnay/rust-toolchain@stable + with: + targets: thumbv8m.main-none-eabihf + + - name: Show variable + run: echo ${{ env.TOKEN }} + + - name: cargo check + run: | + cargo check --target thumbv8m.main-none-eabihf --all-features --locked diff --git a/embassy-mcxa/.github/workflows/rolling.yml b/embassy-mcxa/.github/workflows/rolling.yml new file mode 100644 index 000000000..73b48484a --- /dev/null +++ b/embassy-mcxa/.github/workflows/rolling.yml @@ -0,0 +1,58 @@ +# This workflow runs every morning at midnight. It will run cargo hack +# and a build with msrv. If any dependency breaks our crate, we will +# know ASAP. +# +# - check: build with all features +# - msrv: check that the msrv specified in the crate is correct +permissions: + contents: read + +on: + schedule: + - cron: '0 0 * * *' + +name: rolling +jobs: + + check: + runs-on: ubuntu-latest + name: ubuntu / stable / features + strategy: + fail-fast: false + steps: + - uses: actions/checkout@v6 + with: + submodules: true + - name: Install stable + uses: dtolnay/rust-toolchain@stable + with: + targets: thumbv8m.main-none-eabihf + + - name: cargo install cargo-hack + uses: taiki-e/install-action@cargo-hack + - name: cargo check + run: | + cargo update + cargo check --all-features + + msrv: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + msrv: ["1.91"] + + name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }}) + steps: + - uses: actions/checkout@v6 + with: + submodules: true + - name: Install ${{ matrix.msrv }} + uses: dtolnay/rust-toolchain@master + with: + toolchain: ${{ matrix.msrv }} + targets: thumbv8m.main-none-eabihf + - name: cargo +${{ matrix.msrv }} check + run: | + cargo update + cargo check --all-features diff --git a/embassy-mcxa/.gitignore b/embassy-mcxa/.gitignore new file mode 100644 index 000000000..d128a49cb --- /dev/null +++ b/embassy-mcxa/.gitignore @@ -0,0 +1,19 @@ +# Rust +/target/ + +# IDE +.vscode/ +.idea/ + +# OS +.DS_Store +Thumbs.db + +# Embedded +*.bin +*.hex +*.elf +*.map + +# Debug +*.log diff --git a/embassy-mcxa/CODEOWNERS b/embassy-mcxa/CODEOWNERS new file mode 100644 index 000000000..6e0f4c4c6 --- /dev/null +++ b/embassy-mcxa/CODEOWNERS @@ -0,0 +1,5 @@ +* @jamesmunns @felipebalbi + +# Any changes in the supply-chain folder needs approval +# from auditors as it relates to cargo vet +**/supply-chain @OpenDevicePartnership/crate-auditors \ No newline at end of file diff --git a/embassy-mcxa/CODE_OF_CONDUCT.md b/embassy-mcxa/CODE_OF_CONDUCT.md new file mode 100644 index 000000000..54a673e04 --- /dev/null +++ b/embassy-mcxa/CODE_OF_CONDUCT.md @@ -0,0 +1,132 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +We as members, contributors, and leaders pledge to make participation in our +community a harassment-free experience for everyone, regardless of age, body +size, visible or invisible disability, ethnicity, sex characteristics, gender +identity and expression, level of experience, education, socio-economic status, +nationality, personal appearance, race, caste, color, religion, or sexual +identity and orientation. + +We pledge to act and interact in ways that contribute to an open, welcoming, +diverse, inclusive, and healthy community. + +## Our Standards + +Examples of behavior that contributes to a positive environment for our +community include: + +* Demonstrating empathy and kindness toward other people +* Being respectful of differing opinions, viewpoints, and experiences +* Giving and gracefully accepting constructive feedback +* Accepting responsibility and apologizing to those affected by our mistakes, + and learning from the experience +* Focusing on what is best not just for us as individuals, but for the overall + community + +Examples of unacceptable behavior include: + +* The use of sexualized language or imagery, and sexual attention or advances of + any kind +* Trolling, insulting or derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or email address, + without their explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Enforcement Responsibilities + +Community leaders are responsible for clarifying and enforcing our standards of +acceptable behavior and will take appropriate and fair corrective action in +response to any behavior that they deem inappropriate, threatening, offensive, +or harmful. + +Community leaders have the right and responsibility to remove, edit, or reject +comments, commits, code, wiki edits, issues, and other contributions that are +not aligned to this Code of Conduct, and will communicate reasons for moderation +decisions when appropriate. + +## Scope + +This Code of Conduct applies within all community spaces, and also applies when +an individual is officially representing the community in public spaces. +Examples of representing our community include using an official e-mail address, +posting via an official social media account, or acting as an appointed +representative at an online or offline event. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported to the community leaders responsible for enforcement at +odpadmin@microsoft.com. +All complaints will be reviewed and investigated promptly and fairly. + +All community leaders are obligated to respect the privacy and security of the +reporter of any incident. + +## Enforcement Guidelines + +Community leaders will follow these Community Impact Guidelines in determining +the consequences for any action they deem in violation of this Code of Conduct: + +### 1. Correction + +**Community Impact**: Use of inappropriate language or other behavior deemed +unprofessional or unwelcome in the community. + +**Consequence**: A private, written warning from community leaders, providing +clarity around the nature of the violation and an explanation of why the +behavior was inappropriate. A public apology may be requested. + +### 2. Warning + +**Community Impact**: A violation through a single incident or series of +actions. + +**Consequence**: A warning with consequences for continued behavior. No +interaction with the people involved, including unsolicited interaction with +those enforcing the Code of Conduct, for a specified period of time. This +includes avoiding interactions in community spaces as well as external channels +like social media. Violating these terms may lead to a temporary or permanent +ban. + +### 3. Temporary Ban + +**Community Impact**: A serious violation of community standards, including +sustained inappropriate behavior. + +**Consequence**: A temporary ban from any sort of interaction or public +communication with the community for a specified period of time. No public or +private interaction with the people involved, including unsolicited interaction +with those enforcing the Code of Conduct, is allowed during this period. +Violating these terms may lead to a permanent ban. + +### 4. Permanent Ban + +**Community Impact**: Demonstrating a pattern of violation of community +standards, including sustained inappropriate behavior, harassment of an +individual, or aggression toward or disparagement of classes of individuals. + +**Consequence**: A permanent ban from any sort of public interaction within the +community. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], +version 2.1, available at +[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1]. + +Community Impact Guidelines were inspired by +[Mozilla's code of conduct enforcement ladder][Mozilla CoC]. + +For answers to common questions about this code of conduct, see the FAQ at +[https://www.contributor-covenant.org/faq][FAQ]. Translations are available at +[https://www.contributor-covenant.org/translations][translations]. + +[homepage]: https://www.contributor-covenant.org +[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html +[Mozilla CoC]: https://github.com/mozilla/diversity +[FAQ]: https://www.contributor-covenant.org/faq +[translations]: https://www.contributor-covenant.org/translations diff --git a/embassy-mcxa/CONTRIBUTING.md b/embassy-mcxa/CONTRIBUTING.md new file mode 100644 index 000000000..f10eb5be9 --- /dev/null +++ b/embassy-mcxa/CONTRIBUTING.md @@ -0,0 +1,28 @@ +# Contributing to Open Device Partnership + +The Open Device Partnership project welcomes your suggestions and contributions! Before opening your first issue or pull request, please review our +[Code of Conduct](CODE_OF_CONDUCT.md) to understand how our community interacts in an inclusive and respectful manner. + +## Contribution Licensing + +Most of our code is distributed under the terms of the [MIT license](LICENSE), and when you contribute code that you wrote to our repositories, +you agree that you are contributing under those same terms. In addition, by submitting your contributions you are indicating that +you have the right to submit those contributions under those terms. + +## Other Contribution Information + +If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your +pull request so that the project team can discuss the situation with you. + +## Commit Message + +* Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html) + +## PR Etiquette + +* Create a draft PR first +* Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers. + +## Regressions + +When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster. diff --git a/embassy-mcxa/Cargo.lock b/embassy-mcxa/Cargo.lock new file mode 100644 index 000000000..747a69c08 --- /dev/null +++ b/embassy-mcxa/Cargo.lock @@ -0,0 +1,918 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "aho-corasick" +version = "1.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" +dependencies = [ + "memchr", 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b/embassy-mcxa/Cargo.toml new file mode 100644 index 000000000..22660bee9 --- /dev/null +++ b/embassy-mcxa/Cargo.toml @@ -0,0 +1,53 @@ +[package] +name = "embassy-mcxa" +version = "0.1.0" +edition = "2021" +license = "MIT OR Apache-2.0" +description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA series of MCUs" +keywords = ["embedded", "hal", "nxp", "mcxa", "embassy"] +categories = ["embedded", "hardware-support", "no-std"] + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +# If you would like "device" to be an optional feature, please open an issue. +cortex-m-rt = { version = "0.7", features = ["device"] } +critical-section = "1.2.0" +defmt = { version = "1.0", optional = true } +embassy-embedded-hal = "0.5.0" +embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] } +embassy-sync = "0.7.2" +embedded-hal-1 = { package = "embedded-hal", version = "1.0" } +embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } +embedded-hal-async = { version = "1.0" } +embedded-hal-nb = { version = "1.0" } +embedded-io = "0.6" +embedded-io-async = { version = "0.6.1" } +heapless = "0.8" +mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt", "critical-section"], version = "0.1.0" } +nb = "1.1.0" +paste = "1.0.15" +maitake-sync = { version = "0.2.2", default-features = false, features = ["critical-section", "no-cache-pad"] } + +# `time` dependencies +embassy-time = { version = "0.5.0", optional = true } +embassy-time-driver = { version = "0.2.1", optional = true } + +[features] +default = ["rt"] + +# Base defmt feature enables core + panic handler +# Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) +defmt = ["dep:defmt", "mcxa-pac/defmt"] + +unstable-pac = [] + +# dummy feature to silence embassy-hal-internal lint +# +# This feature makes no change to embassy-mcxa's operation. +rt = [] + +# Embassy time +time = [ + "dep:embassy-time", + "dep:embassy-time-driver", +] diff --git a/embassy-mcxa/Embed.toml b/embassy-mcxa/Embed.toml new file mode 100644 index 000000000..40218c8bf --- /dev/null +++ b/embassy-mcxa/Embed.toml @@ -0,0 +1,28 @@ +[default.probe] +# Use the first available probe +protocol = "Swd" +speed = 1000 + +[default.flashing] +# Attach-only: don't flash (we already loaded to RAM) +enabled = false + +[default.reset] +# Don't reset; keep running app started by run_jlink_noblock.sh +enabled = false + +[default.general] +# The chip name of the target +chip = "MCXA276" + +[default.gdb] +# Whether or not a GDB server should be opened after loading +enabled = false + +[default.rtt] +# Enable RTT for debugging output +enabled = true + +# Increase timeout for RTT CB discovery +up_channels = [ { channel = 0, mode = "BlockIfFull" } ] +timeout = 5000 diff --git a/embassy-mcxa/LICENSE b/embassy-mcxa/LICENSE new file mode 100644 index 000000000..609bd42da --- /dev/null +++ b/embassy-mcxa/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2025 Open Device Partnership + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/embassy-mcxa/README.md b/embassy-mcxa/README.md new file mode 100644 index 000000000..6e7d61c0e --- /dev/null +++ b/embassy-mcxa/README.md @@ -0,0 +1,13 @@ +# Embassy MCXA256 HAL + +[![check](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml) +[![no-std](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml) +[![rolling](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml) + +A Hardware Abstraction Layer (HAL) for the NXP MCXA256 microcontroller +using the Embassy async framework. This HAL provides safe, idiomatic +Rust interfaces for GPIO, UART, and OSTIMER peripherals. + +## License + +This project is licensed under MIT OR Apache-2.0. diff --git a/embassy-mcxa/SECURITY.md b/embassy-mcxa/SECURITY.md new file mode 100644 index 000000000..5357b8824 --- /dev/null +++ b/embassy-mcxa/SECURITY.md @@ -0,0 +1,66 @@ +# Vulnerability Disclosure and Embargo Policy + +The Open Device Partnership project welcomes the responsible disclosure of vulnerabilities. + +## Initial Contact + +All security bugs in Open Device Partnership should be reported to the security team. +To do so, please reach out in the form of a +[Github Security Advisory](https://docs.github.com/en/code-security/security-advisories/guidance-on-reporting-and-writing-information-about-vulnerabilities). + +You will be invited to join this private area to discuss specifics. Doing so +allows us to start with a high level of confidentiality and relax it if the +issue is less critical, moving to work on the fix in the open. + +Your initial contact will be acknowledged within 48 hours, and you’ll receive +a more detailed response within 96 hours indicating the next steps in handling +your report. + +After the initial reply to your report, the security team will endeavor to +keep you informed of the progress being made towards a fix and full +announcement. As recommended by +[RFPolicy](https://dl.packetstormsecurity.net/papers/general/rfpolicy-2.0.txt), +these updates will be sent at least every five working days. + +## Disclosure Policy + +The Open Device Partnership project has a 5 step disclosure process. + +1. Contact is established, a private channel created, and the security report + is received and is assigned a primary handler. This person will coordinate + the fix and release process. +2. The problem is confirmed and a list of all affected versions is determined. + If an embargo is needed (see below), details of the embargo are decided. +3. Code is audited to find any potential similar problems. +4. Fixes are prepared for all releases which are still under maintenance. In + case of embargo, these fixes are not committed to the public repository but + rather held in a private fork pending the announcement. +5. The changes are pushed to the public repository and new builds are deployed. + +This process can take some time, especially when coordination is required +with maintainers of other projects. Every effort will be made to handle the bug +in as timely a manner as possible, however it is important that we follow the +release process above to ensure that the disclosure is handled in a consistent +manner. + +## Embargoes + +While the Open Device Partnership project aims to follow the highest standards of +transparency and openness, handling some security issues may pose such an +immediate threat to various stakeholders and require coordination between +various actors that it cannot be made immediately public. + +In this case, security issues will fall under an embargo. + +An embargo can be called for in various cases: + +- when disclosing the issue without simultaneously providing a mitigation + would seriously endanger users, +- when producing a fix requires coordinating between multiple actors (such as + upstream or downstream/dependency projects), or simply +- when proper analysis of the issue and its ramifications demands time. + +If we determine that an issue you report requires an embargo, we will discuss +this with you and try to find a reasonable expiry date (aka “embargo +completion date”), as well as who should be included in the list of +need-to-know people. diff --git a/embassy-mcxa/SW-Content-Register.txt b/embassy-mcxa/SW-Content-Register.txt new file mode 100644 index 000000000..09f879c2f --- /dev/null +++ b/embassy-mcxa/SW-Content-Register.txt @@ -0,0 +1,78 @@ +Release Name: Embassy MCXA276 HAL +Release Version: 0.1.0 +Package License: MIT (see ./License.txt) +Note: The crate is dual-licensed “MIT OR Apache-2.0” per Cargo.toml; choosing MIT satisfies the dual-license terms. + +Scope of this Register +This file documents software content that is part of this repository and, for transparency, lists major non-vendored Rust dependencies that are resolved from crates.io during builds. Components that are not present in the repository (e.g., external crates) are listed under “Non‑vendored Rust dependencies”. + +Repository Components (included in this release) + +embassy_mcxa276_hal Name: Embassy MCXA276 HAL (library + examples) + Version: 0.1.0 + Outgoing License: MIT + License File: ./License.txt + Format: Rust source code, examples, scripts, linker scripts + Description: Hardware Abstraction Layer for NXP MCXA276 using the Embassy async framework. Implements drivers and helpers for: + - LPUART2 (UART), OSTIMER0, RTC0, ADC1, GPIO + - Embassy integration (executors, time) + Location: ./src, ./examples, ./build.rs, ./memory.x, ./ram.ld, ./defmt.x, ./.cargo/config.toml, ./run.sh, ./tools/ + Origin: OEMWCSE (MIT) + URL: https://bitbucket.sw.nxp.com/scm/oemwcse/mcxa_rust.git + +mcxa276_pac Name: MCXA276 Peripheral Access Crate (PAC) + Version: 0.1.0 + Outgoing License: MIT OR Apache-2.0 + License File: (see crate metadata) + Format: Rust source code (auto-generated PAC) + Description: Auto-generated register mappings for MCXA276 peripherals (svd2rust). Includes device.x and interrupt vectors. + Location: External (git): https://github.com/bogdan-petru/mcxa-pac (pinned rev a9dd3301) + Origin: Generated by svdtools + svd2rust from NXP SVD 25.06.00 + URL: N/A (generated from NXP SVD) + +examples Name: Example applications + Version: N/A + Outgoing License: MIT + License File: ./License.txt + Format: Rust source code (examples) + Description: Demonstrations for HAL peripherals and features: + - hello, blink + - lpuart_polling, lpuart_buffered, uart_interrupt + - rtc_alarm + - adc_polling, adc_interrupt + - ostimer_alarm, ostimer_async, ostimer_counter, ostimer_race_test + Location: ./examples + Origin: OEMWCSE (MIT) + +Non‑vendored Rust dependencies (resolved from crates.io at build time) +The following crates are not vendored in this repository. They are fetched during builds via Cargo. See Cargo.lock for exact versions. License summaries below are for convenience; consult each crate for authoritative terms. + +cortex-m License: MIT OR Apache-2.0 Purpose: Cortex-M core support +cortex-m-rt License: MIT OR Apache-2.0 Purpose: Cortex-M runtime (vectors, reset) +embassy-executor License: MIT OR Apache-2.0 Purpose: Async executor for Cortex-M +embassy-time (+ driver) License: MIT OR Apache-2.0 Purpose: Time abstraction and drivers +embassy-sync License: MIT OR Apache-2.0 Purpose: No-std synchronization primitives +embassy-embedded-hal License: MIT OR Apache-2.0 Purpose: Traits/adapters for embedded-hal +embassy-hal-internal License: MIT OR Apache-2.0 Purpose: HAL building blocks (peripherals!) +embedded-hal (1.0) License: MIT OR Apache-2.0 Purpose: Core embedded hardware traits +embedded-hal (0.2.6) License: MIT OR Apache-2.0 Purpose: Legacy HAL traits ("unproven") +embedded-hal-async License: MIT OR Apache-2.0 Purpose: Async HAL traits +embedded-hal-nb License: MIT OR Apache-2.0 Purpose: Non-blocking HAL traits +embedded-io / embedded-io-async License: MIT OR Apache-2.0 Purpose: IO traits +critical-section License: MIT OR Apache-2.0 Purpose: Critical-section abstraction +heapless License: MIT OR Apache-2.0 Purpose: Fixed-capacity data structures +paste License: MIT OR Apache-2.0 Purpose: Macro hygiene utility +nb License: MIT OR Apache-2.0 Purpose: Non-blocking result type +vcell License: MIT OR Apache-2.0 Purpose: Volatile cell (PAC dependency) + +defmt, defmt-rtt, rtt-target, panic-probe License: MIT OR Apache-2.0 Purpose: Optional (feature-gated) logging/panic crates + +Attribution notes +- MCXA276 PAC is sourced as an external dependency (see Cargo.toml). SVD 25.06.00 already includes OS_EVENT and WAKETIMER0 interrupts (no local fixes). +- Examples run from RAM using custom linker setup; see README.txt for platform-specific instructions. + +Compliance +- This repository’s distributed source is covered by MIT (see License.txt). Where crates are pulled from crates.io, those crates retain their own licenses; the dual-license compatibility (MIT OR Apache-2.0) is standard in the Rust embedded ecosystem and is compatible with this project’s selected MIT distribution. + + + diff --git a/embassy-mcxa/defmt.x b/embassy-mcxa/defmt.x new file mode 100644 index 000000000..dbd6d0850 --- /dev/null +++ b/embassy-mcxa/defmt.x @@ -0,0 +1,6 @@ +/* + Dummy defmt.x to satisfy -Tdefmt.x when building without the `defmt` feature. + When `defmt` is enabled, the real defmt.x provided by the defmt crate is used via the linker search path. + This file intentionally contains no SECTIONS so it won't override ram.ld. +*/ + diff --git a/embassy-mcxa/deny.toml b/embassy-mcxa/deny.toml new file mode 100644 index 000000000..7097f2f55 --- /dev/null +++ b/embassy-mcxa/deny.toml @@ -0,0 +1,241 @@ +# This template contains all of the possible sections and their default values + +# Note that all fields that take a lint level have these possible values: +# * deny - An error will be produced and the check will fail +# * warn - A warning will be produced, but the check will not fail +# * allow - No warning or error will be produced, though in some cases a note +# will be + +# The values provided in this template are the default values that will be used +# when any section or field is not specified in your own configuration + +# Root options + +# The graph table configures how the dependency graph is constructed and thus +# which crates the checks are performed against +[graph] +# If 1 or more target triples (and optionally, target_features) are specified, +# only the specified targets will be checked when running `cargo deny check`. +# This means, if a particular package is only ever used as a target specific +# dependency, such as, for example, the `nix` crate only being used via the +# `target_family = "unix"` configuration, that only having windows targets in +# this list would mean the nix crate, as well as any of its exclusive +# dependencies not shared by any other crates, would be ignored, as the target +# list here is effectively saying which targets you are building for. +targets = [ + # The triple can be any string, but only the target triples built in to + # rustc (as of 1.40) can be checked against actual config expressions + #"x86_64-unknown-linux-musl", + # You can also specify which target_features you promise are enabled for a + # particular target. target_features are currently not validated against + # the actual valid features supported by the target architecture. + #{ triple = "wasm32-unknown-unknown", features = ["atomics"] }, +] +# When creating the dependency graph used as the source of truth when checks are +# executed, this field can be used to prune crates from the graph, removing them +# from the view of cargo-deny. This is an extremely heavy hammer, as if a crate +# is pruned from the graph, all of its dependencies will also be pruned unless +# they are connected to another crate in the graph that hasn't been pruned, +# so it should be used with care. The identifiers are [Package ID Specifications] +# (https://doc.rust-lang.org/cargo/reference/pkgid-spec.html) +#exclude = [] +# If true, metadata will be collected with `--all-features`. Note that this can't +# be toggled off if true, if you want to conditionally enable `--all-features` it +# is recommended to pass `--all-features` on the cmd line instead +all-features = false +# If true, metadata will be collected with `--no-default-features`. The same +# caveat with `all-features` applies +no-default-features = false +# If set, these feature will be enabled when collecting metadata. If `--features` +# is specified on the cmd line they will take precedence over this option. +#features = [] + +# The output table provides options for how/if diagnostics are outputted +[output] +# When outputting inclusion graphs in diagnostics that include features, this +# option can be used to specify the depth at which feature edges will be added. +# This option is included since the graphs can be quite large and the addition +# of features from the crate(s) to all of the graph roots can be far too verbose. +# This option can be overridden via `--feature-depth` on the cmd line +feature-depth = 1 + +# This section is considered when running `cargo deny check advisories` +# More documentation for the advisories section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/advisories/cfg.html +[advisories] +# The path where the advisory databases are cloned/fetched into +#db-path = "$CARGO_HOME/advisory-dbs" +# The url(s) of the advisory databases to use +#db-urls = ["https://github.com/rustsec/advisory-db"] +# A list of advisory IDs to ignore. Note that ignored advisories will still +# output a note when they are encountered. +ignore = [ + #"RUSTSEC-0000-0000", + #{ id = "RUSTSEC-0000-0000", reason = "you can specify a reason the advisory is ignored" }, + #"a-crate-that-is-yanked@0.1.1", # you can also ignore yanked crate versions if you wish + #{ crate = "a-crate-that-is-yanked@0.1.1", reason = "you can specify why you are ignoring the yanked crate" }, + # { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." }, + { id = "RUSTSEC-2024-0436", reason = "there are no suitable replacements for paste right now; paste has been archived as read-only. It only affects compile time concatenation in macros. We will allow it for now" }, + # { id = "RUSTSEC-2023-0089", reason = "this is a deprecation warning for a dependency of a dependency. https://github.com/jamesmunns/postcard/issues/223 tracks fixing the dependency; until that's resolved, we can accept the deprecated code as it has no known vulnerabilities."} +] +# If this is true, then cargo deny will use the git executable to fetch advisory database. +# If this is false, then it uses a built-in git library. +# Setting this to true can be helpful if you have special authentication requirements that cargo-deny does not support. +# See Git Authentication for more information about setting up git authentication. +#git-fetch-with-cli = true + +# This section is considered when running `cargo deny check licenses` +# More documentation for the licenses section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/licenses/cfg.html +[licenses] +# List of explicitly allowed licenses +# See https://spdx.org/licenses/ for list of possible licenses +# [possible values: any SPDX 3.11 short identifier (+ optional exception)]. +allow = [ + "MIT", + "Apache-2.0", + + # unicode-ident 1.0.14 switched from Unicode-DFS-2016 to Unicode-3.0 license. + "Unicode-3.0", + #"Apache-2.0 WITH LLVM-exception", +] +# The confidence threshold for detecting a license from license text. +# The higher the value, the more closely the license text must be to the +# canonical license text of a valid SPDX license file. +# [possible values: any between 0.0 and 1.0]. +confidence-threshold = 0.8 +# Allow 1 or more licenses on a per-crate basis, so that particular licenses +# aren't accepted for every possible crate as with the normal allow list +exceptions = [ + # Each entry is the crate and version constraint, and its specific allow + # list + #{ allow = ["Zlib"], crate = "adler32" }, +] + +# Some crates don't have (easily) machine readable licensing information, +# adding a clarification entry for it allows you to manually specify the +# licensing information +#[[licenses.clarify]] +# The package spec the clarification applies to +#crate = "ring" +# The SPDX expression for the license requirements of the crate +#expression = "MIT AND ISC AND OpenSSL" +# One or more files in the crate's source used as the "source of truth" for +# the license expression. If the contents match, the clarification will be used +# when running the license check, otherwise the clarification will be ignored +# and the crate will be checked normally, which may produce warnings or errors +# depending on the rest of your configuration +#license-files = [ +# Each entry is a crate relative path, and the (opaque) hash of its contents +#{ path = "LICENSE", hash = 0xbd0eed23 } +#] + +[licenses.private] +# If true, ignores workspace crates that aren't published, or are only +# published to private registries. +# To see how to mark a crate as unpublished (to the official registry), +# visit https://doc.rust-lang.org/cargo/reference/manifest.html#the-publish-field. +ignore = false +# One or more private registries that you might publish crates to, if a crate +# is only published to private registries, and ignore is true, the crate will +# not have its license(s) checked +registries = [ + #"https://sekretz.com/registry +] + +# This section is considered when running `cargo deny check bans`. +# More documentation about the 'bans' section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/bans/cfg.html +[bans] +# Lint level for when multiple versions of the same crate are detected +multiple-versions = "warn" +# Lint level for when a crate version requirement is `*` +wildcards = "allow" +# The graph highlighting used when creating dotgraphs for crates +# with multiple versions +# * lowest-version - The path to the lowest versioned duplicate is highlighted +# * simplest-path - The path to the version with the fewest edges is highlighted +# * all - Both lowest-version and simplest-path are used +highlight = "all" +# The default lint level for `default` features for crates that are members of +# the workspace that is being checked. This can be overridden by allowing/denying +# `default` on a crate-by-crate basis if desired. +workspace-default-features = "allow" +# The default lint level for `default` features for external crates that are not +# members of the workspace. This can be overridden by allowing/denying `default` +# on a crate-by-crate basis if desired. +external-default-features = "allow" +# List of crates that are allowed. Use with care! +allow = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is allowed" }, +] +# List of crates to deny +deny = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is banned" }, + # Wrapper crates can optionally be specified to allow the crate when it + # is a direct dependency of the otherwise banned crate + #{ crate = "ansi_term@0.11.0", wrappers = ["this-crate-directly-depends-on-ansi_term"] }, +] + +# List of features to allow/deny +# Each entry the name of a crate and a version range. If version is +# not specified, all versions will be matched. +#[[bans.features]] +#crate = "reqwest" +# Features to not allow +#deny = ["json"] +# Features to allow +#allow = [ +# "rustls", +# "__rustls", +# "__tls", +# "hyper-rustls", +# "rustls", +# "rustls-pemfile", +# "rustls-tls-webpki-roots", +# "tokio-rustls", +# "webpki-roots", +#] +# If true, the allowed features must exactly match the enabled feature set. If +# this is set there is no point setting `deny` +#exact = true + +# Certain crates/versions that will be skipped when doing duplicate detection. +skip = [ + #"ansi_term@0.11.0", + #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason why it can't be updated/removed" }, +] +# Similarly to `skip` allows you to skip certain crates during duplicate +# detection. Unlike skip, it also includes the entire tree of transitive +# dependencies starting at the specified crate, up to a certain depth, which is +# by default infinite. +skip-tree = [ + #"ansi_term@0.11.0", # will be skipped along with _all_ of its direct and transitive dependencies + #{ crate = "ansi_term@0.11.0", depth = 20 }, +] + +# This section is considered when running `cargo deny check sources`. +# More documentation about the 'sources' section can be found here: +# https://embarkstudios.github.io/cargo-deny/checks/sources/cfg.html +[sources] +# Lint level for what to happen when a crate from a crate registry that is not +# in the allow list is encountered +unknown-registry = "warn" +# Lint level for what to happen when a crate from a git repository that is not +# in the allow list is encountered +unknown-git = "warn" +# List of URLs for allowed crate registries. Defaults to the crates.io index +# if not specified. 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features = ["critical-section-single-core"] } +cortex-m-rt = { version = "0.7", features = ["set-sp", "set-vtor"] } +critical-section = "1.2.0" +defmt = "1.0" +defmt-rtt = "1.0" +embassy-embedded-hal = "0.5.0" +embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } +embassy-mcxa = { path = "../", features = ["defmt", "unstable-pac", "time"] } +embassy-sync = "0.7.2" +embassy-time = "0.5.0" +embassy-time-driver = "0.2.1" +embedded-io-async = "0.6.1" +heapless = "0.9.2" +panic-probe = { version = "1.0", features = ["print-defmt"] } +tmp108 = "0.4.0" + +[profile.release] +lto = true # better optimizations +debug = 2 # enough information for defmt/rtt locations diff --git a/embassy-mcxa/examples/build.rs b/embassy-mcxa/examples/build.rs new file mode 100644 index 000000000..f076bba9f --- /dev/null +++ b/embassy-mcxa/examples/build.rs @@ -0,0 +1,20 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + + // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH" + // cortex-m-rt expects FLASH for code, RAM for data/bss/stack + // Both are in RAM, but separated to satisfy cortex-m-rt's expectations + // MCXA256 has 128KB RAM total + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=memory.x"); +} diff --git a/embassy-mcxa/examples/memory.x b/embassy-mcxa/examples/memory.x new file mode 100644 index 000000000..315ced58a --- /dev/null +++ b/embassy-mcxa/examples/memory.x @@ -0,0 +1,5 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 1M + RAM : ORIGIN = 0x20000000, LENGTH = 128K +} diff --git a/embassy-mcxa/examples/src/bin/adc_interrupt.rs b/embassy-mcxa/examples/src/bin/adc_interrupt.rs new file mode 100644 index 000000000..83d8046b3 --- /dev/null +++ b/embassy-mcxa/examples/src/bin/adc_interrupt.rs @@ -0,0 +1,84 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::init_adc_pins; +use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; +use hal::clocks::periph_helpers::{AdcClockSel, Div4}; +use hal::clocks::PoweredClock; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; +use hal::{bind_interrupts, InterruptExt}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!(struct Irqs { + ADC1 => hal::adc::AdcHandler; +}); + +#[used] +#[no_mangle] +static KEEP_ADC: unsafe extern "C" fn() = ADC1; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("ADC interrupt Example"); + + unsafe { + init_adc_pins(); + } + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + defmt::info!("ADC configuration done..."); + + adc.enable_interrupt(0x1); + + unsafe { + hal::interrupt::ADC1.enable(); + } + + unsafe { + cortex_m::interrupt::enable(); + } + + loop { + adc.do_software_trigger(1); + while !adc.is_interrupt_triggered() { + // Wait until the interrupt is triggered + } + defmt::info!("*** ADC interrupt TRIGGERED! ***"); + //TBD need to print the value + } +} diff --git a/embassy-mcxa/examples/src/bin/adc_polling.rs b/embassy-mcxa/examples/src/bin/adc_polling.rs new file mode 100644 index 000000000..ddf3f586b --- /dev/null +++ b/embassy-mcxa/examples/src/bin/adc_polling.rs @@ -0,0 +1,68 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::init_adc_pins; +use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; +use hal::clocks::periph_helpers::{AdcClockSel, Div4}; +use hal::clocks::PoweredClock; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +const G_LPADC_RESULT_SHIFT: u32 = 0; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + unsafe { + init_adc_pins(); + } + + defmt::info!("=== ADC polling Example ==="); + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + defmt::info!("=== ADC configuration done... ==="); + + loop { + adc.do_software_trigger(1); + let mut result: Option = None; + while result.is_none() { + result = hal::adc::get_conv_result(); + } + let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; + defmt::info!("value: {=u16}", value); + } +} diff --git a/embassy-mcxa/examples/src/bin/blinky.rs b/embassy-mcxa/examples/src/bin/blinky.rs new file mode 100644 index 000000000..dd08ec0d9 --- /dev/null +++ b/embassy-mcxa/examples/src/bin/blinky.rs @@ -0,0 +1,36 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{DriveStrength, Level, Output, SlewRate}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("Blink example"); + + let mut red = Output::new(p.P3_18, Level::High, DriveStrength::Normal, SlewRate::Fast); + let mut green = Output::new(p.P3_19, Level::High, DriveStrength::Normal, SlewRate::Fast); + let mut blue = Output::new(p.P3_21, Level::High, DriveStrength::Normal, SlewRate::Fast); + + loop { + defmt::info!("Toggle LEDs"); + + red.toggle(); + Timer::after_millis(250).await; + + red.toggle(); + green.toggle(); + Timer::after_millis(250).await; + + green.toggle(); + blue.toggle(); + Timer::after_millis(250).await; + blue.toggle(); + + Timer::after_millis(250).await; + } +} diff --git a/embassy-mcxa/examples/src/bin/button.rs b/embassy-mcxa/examples/src/bin/button.rs new file mode 100644 index 000000000..943edbb15 --- /dev/null +++ b/embassy-mcxa/examples/src/bin/button.rs @@ -0,0 +1,23 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{Input, Pull}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("Button example"); + + // This button is labeled "WAKEUP" on the FRDM-MCXA276 + // The board already has a 10K pullup + let monitor = Input::new(p.P1_7, Pull::Disabled); + + loop { + defmt::info!("Pin level is {:?}", monitor.get_level()); + Timer::after_millis(1000).await; + } +} diff --git a/embassy-mcxa/examples/src/bin/button_async.rs b/embassy-mcxa/examples/src/bin/button_async.rs new file mode 100644 index 000000000..6cc7b62cd --- /dev/null +++ b/embassy-mcxa/examples/src/bin/button_async.rs @@ -0,0 +1,29 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{Input, Pull}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("GPIO interrupt example"); + + // This button is labeled "WAKEUP" on the FRDM-MCXA276 + // The board already has a 10K pullup + let mut pin = Input::new(p.P1_7, Pull::Disabled); + + let mut press_count = 0u32; + + loop { + pin.wait_for_falling_edge().await; + + press_count += 1; + + defmt::info!("Button pressed! Count: {}", press_count); + Timer::after_millis(50).await; + } +} diff --git a/embassy-mcxa/examples/src/bin/clkout.rs b/embassy-mcxa/examples/src/bin/clkout.rs new file mode 100644 index 000000000..bfd963540 --- /dev/null +++ b/embassy-mcxa/examples/src/bin/clkout.rs @@ -0,0 +1,69 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4}; +use embassy_mcxa::clocks::PoweredClock; +use embassy_mcxa::gpio::{DriveStrength, SlewRate}; +use embassy_mcxa::{Level, Output}; +use embassy_time::Timer; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Demonstrate CLKOUT, using Pin P4.2 +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + let mut pin = p.P4_2; + let mut clkout = p.CLKOUT; + + loop { + defmt::info!("Set Low..."); + let mut output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); + Timer::after_millis(500).await; + + defmt::info!("Set High..."); + output.set_high(); + Timer::after_millis(400).await; + + defmt::info!("Set Low..."); + output.set_low(); + Timer::after_millis(500).await; + + defmt::info!("16k..."); + // Run Clock Out with the 16K clock + let _clock_out = ClockOut::new( + clkout.reborrow(), + pin.reborrow(), + Config { + sel: ClockOutSel::Clk16K, + div: Div4::no_div(), + level: PoweredClock::NormalEnabledDeepSleepDisabled, + }, + ) + .unwrap(); + + Timer::after_millis(3000).await; + + defmt::info!("Set Low..."); + drop(_clock_out); + + let _output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); + Timer::after_millis(500).await; + + // Run Clock Out with the 12M clock, divided by 3 + defmt::info!("4M..."); + let _clock_out = ClockOut::new( + clkout.reborrow(), + pin.reborrow(), + Config { + sel: ClockOutSel::Fro12M, + div: const { Div4::from_divisor(3).unwrap() }, + level: PoweredClock::NormalEnabledDeepSleepDisabled, + }, + ) + .unwrap(); + + // Let it run for 3 seconds... + Timer::after_millis(3000).await; + } +} diff --git a/embassy-mcxa/examples/src/bin/hello.rs b/embassy-mcxa/examples/src/bin/hello.rs new file mode 100644 index 000000000..e371d9413 --- /dev/null +++ b/embassy-mcxa/examples/src/bin/hello.rs @@ -0,0 +1,119 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clocks::config::Div8; +use hal::lpuart::{Blocking, Config, Lpuart}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Simple helper to write a byte as hex to UART +fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) { + const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; + let _ = uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); + let _ = uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); + + defmt::info!("boot"); + + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + ..Default::default() + }; + + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.P2_2, // TX pin + p.P2_3, // RX pin + config, + ) + .unwrap(); + + // Print welcome message before any async delays to guarantee early console output + uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + uart.write_str_blocking("Type a command: "); + + let mut buffer = [0u8; 64]; + let mut buf_idx = 0; + + loop { + // Read a byte from UART + let byte = uart.read_byte_blocking(); + + // Echo the character back + if byte == b'\r' || byte == b'\n' { + // Enter pressed - process command + uart.write_str_blocking("\r\n"); + + if buf_idx > 0 { + let command = &buffer[0..buf_idx]; + + if command == b"help" { + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + } else if command.starts_with(b"echo ") && command.len() > 5 { + uart.write_str_blocking("Echo: "); + uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } else if command.starts_with(b"hex ") && command.len() > 4 { + // Parse the byte value + let num_str = &command[4..]; + if let Ok(num) = parse_u8(num_str) { + uart.write_str_blocking("Hex: 0x"); + write_hex_byte(&mut uart, num); + uart.write_str_blocking("\r\n"); + } else { + uart.write_str_blocking("Invalid number for hex command\r\n"); + } + } else if !command.is_empty() { + uart.write_str_blocking("Unknown command: "); + uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } + } + + // Reset buffer and prompt + buf_idx = 0; + uart.write_str_blocking("Type a command: "); + } else if byte == 8 || byte == 127 { + // Backspace + if buf_idx > 0 { + buf_idx -= 1; + uart.write_str_blocking("\x08 \x08"); // Erase character + } + } else if buf_idx < buffer.len() - 1 { + // Regular character + buffer[buf_idx] = byte; + buf_idx += 1; + let _ = uart.write_byte(byte); + } + } +} + +/// Simple parser for u8 from ASCII bytes +fn parse_u8(bytes: &[u8]) -> Result { + let mut result = 0u8; + for &b in bytes { + if b.is_ascii_digit() { + result = result.checked_mul(10).ok_or(())?; + result = result.checked_add(b - b'0').ok_or(())?; + } else { + return Err(()); + } + } + Ok(result) +} diff --git a/embassy-mcxa/examples/src/bin/i2c-async.rs b/embassy-mcxa/examples/src/bin/i2c-async.rs new file mode 100644 index 000000000..47b5f3cbe --- /dev/null +++ b/embassy-mcxa/examples/src/bin/i2c-async.rs @@ -0,0 +1,39 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::bind_interrupts; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use hal::i2c::InterruptHandler; +use hal::peripherals::LPI2C3; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!( + struct Irqs { + LPI2C3 => InterruptHandler; + } +); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + let mut i2c = I2c::new_async(p.LPI2C3, p.P3_27, p.P3_28, Irqs, config).unwrap(); + let mut buf = [0u8; 2]; + + loop { + i2c.async_write_read(0x48, &[0x00], &mut buf).await.unwrap(); + defmt::info!("Buffer: {:02x}", buf); + Timer::after_secs(1).await; + } +} diff --git a/embassy-mcxa/examples/src/bin/i2c-blocking.rs b/embassy-mcxa/examples/src/bin/i2c-blocking.rs new file mode 100644 index 000000000..0f6c8cbae --- /dev/null +++ b/embassy-mcxa/examples/src/bin/i2c-blocking.rs @@ -0,0 +1,31 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use tmp108::Tmp108; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + let i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap(); + let mut tmp = Tmp108::new_with_a0_gnd(i2c); + + loop { + let temperature = tmp.temperature().unwrap(); + defmt::info!("Temperature: {}C", temperature); + Timer::after_secs(1).await; + } +} diff --git a/embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs b/embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs new file mode 100644 index 000000000..4e203597b --- /dev/null +++ b/embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs @@ -0,0 +1,41 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::gpio::Pull; +use embassy_mcxa::Input; +use embassy_time::Timer; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + + // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and + // defaults to SWO on the debug peripheral. Explicitly make it a high-z + // input. + let _pin = Input::new(p.P0_2, Pull::Disabled); + let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap(); + + for addr in 0x01..=0x7f { + let result = i2c.blocking_write(addr, &[]); + if result.is_ok() { + defmt::info!("Device found at addr {:02x}", addr); + } + } + + loop { + Timer::after_secs(10).await; + } +} diff --git a/embassy-mcxa/examples/src/bin/lpuart_buffered.rs b/embassy-mcxa/examples/src/bin/lpuart_buffered.rs new file mode 100644 index 000000000..420589d00 --- /dev/null +++ b/embassy-mcxa/examples/src/bin/lpuart_buffered.rs @@ -0,0 +1,62 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clocks::config::Div8; +use embassy_mcxa::lpuart::buffered::BufferedLpuart; +use embassy_mcxa::lpuart::Config; +use embassy_mcxa::{bind_interrupts, lpuart}; +use embedded_io_async::Write; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver +bind_interrupts!(struct Irqs { + LPUART2 => lpuart::buffered::BufferedInterruptHandler::; +}); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); + + // Configure NVIC for LPUART2 + hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); + + // UART configuration (enable both TX and RX) + let config = Config { + baudrate_bps: 115_200, + rx_fifo_watermark: 0, + tx_fifo_watermark: 0, + ..Default::default() + }; + + let mut tx_buf = [0u8; 256]; + let mut rx_buf = [0u8; 256]; + + // Create a buffered LPUART2 instance with both TX and RX + let mut uart = BufferedLpuart::new( + p.LPUART2, + p.P2_2, // TX pin + p.P2_3, // RX pin + Irqs, + &mut tx_buf, + &mut rx_buf, + config, + ) + .unwrap(); + + // Split into TX and RX parts + let (tx, rx) = uart.split_ref(); + + tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); + tx.write(b"Type characters to echo them back.\r\n").await.unwrap(); + + // Echo loop + let mut buf = [0u8; 4]; + loop { + let used = rx.read(&mut buf).await.unwrap(); + tx.write_all(&buf[..used]).await.unwrap(); + } +} diff --git a/embassy-mcxa/examples/src/bin/lpuart_polling.rs b/embassy-mcxa/examples/src/bin/lpuart_polling.rs new file mode 100644 index 000000000..b80668834 --- /dev/null +++ b/embassy-mcxa/examples/src/bin/lpuart_polling.rs @@ -0,0 +1,47 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clocks::config::Div8; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +use crate::hal::lpuart::{Config, Lpuart}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); + + defmt::info!("boot"); + + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + ..Default::default() + }; + + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX + let lpuart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.P2_2, // TX pin + p.P2_3, // RX pin + config, + ) + .unwrap(); + + // Split into separate TX and RX parts + let (mut tx, mut rx) = lpuart.split(); + + // Write hello messages + tx.blocking_write(b"Hello world.\r\n").unwrap(); + tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap(); + + // Echo loop + loop { + let mut buf = [0u8; 1]; + rx.blocking_read(&mut buf).unwrap(); + tx.blocking_write(&buf).unwrap(); + } +} diff --git a/embassy-mcxa/examples/src/bin/rtc_alarm.rs b/embassy-mcxa/examples/src/bin/rtc_alarm.rs new file mode 100644 index 000000000..fe355888b --- /dev/null +++ b/embassy-mcxa/examples/src/bin/rtc_alarm.rs @@ -0,0 +1,47 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::bind_interrupts; +use hal::rtc::{InterruptHandler, Rtc, RtcDateTime}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!(struct Irqs { + RTC => InterruptHandler; +}); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("=== RTC Alarm Example ==="); + + let rtc_config = hal::rtc::get_default_config(); + + let mut rtc = Rtc::new(p.RTC0, Irqs, rtc_config); + + let now = RtcDateTime { + year: 2025, + month: 10, + day: 15, + hour: 14, + minute: 30, + second: 0, + }; + + rtc.stop(); + + defmt::info!("Time set to: 2025-10-15 14:30:00"); + rtc.set_datetime(now); + + let mut alarm = now; + alarm.second += 10; + + defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)"); + defmt::info!("RTC started, waiting for alarm..."); + + rtc.wait_for_alarm(alarm).await; + defmt::info!("*** ALARM TRIGGERED! ***"); + + defmt::info!("Example complete - Test PASSED!"); +} diff --git a/embassy-mcxa/examples/src/lib.rs b/embassy-mcxa/examples/src/lib.rs new file mode 100644 index 000000000..2573a6adc --- /dev/null +++ b/embassy-mcxa/examples/src/lib.rs @@ -0,0 +1,16 @@ +#![no_std] +#![allow(clippy::missing_safety_doc)] + +//! Shared board-specific helpers for the FRDM-MCXA276 examples. +//! These live with the examples so the HAL stays generic. + +use hal::{clocks, pins}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Initialize clocks and pin muxing for ADC. +pub unsafe fn init_adc_pins() { + // NOTE: Lpuart has been updated to properly enable + reset its own clocks. + // GPIO has not. + _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); + pins::configure_adc_pins(); +} diff --git a/embassy-mcxa/ram.ld b/embassy-mcxa/ram.ld new file mode 100644 index 000000000..816ab6819 --- /dev/null +++ b/embassy-mcxa/ram.ld @@ -0,0 +1,109 @@ +/* Simple RAM execution linker script for MCXA276 */ +MEMORY +{ + RAM : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* Pull in device default interrupt symbol aliases (e.g., CMC = DefaultHandler) */ +INCLUDE device.x + + +/* Provide core exception weak aliases if not supplied by cortex-m-rt's link.x */ +PROVIDE(NonMaskableInt = DefaultHandler); +PROVIDE(HardFault = DefaultHandler); +PROVIDE(MemoryManagement = DefaultHandler); +PROVIDE(BusFault = DefaultHandler); +PROVIDE(UsageFault = DefaultHandler); +PROVIDE(SecureFault = DefaultHandler); +PROVIDE(SVCall = DefaultHandler); +PROVIDE(DebugMonitor = DefaultHandler); +PROVIDE(PendSV = DefaultHandler); +PROVIDE(SysTick = DefaultHandler); + +/* In RAM-run we have no FLASH sidata; copy from sdata */ +__sidata = __sdata; + +/* Ensure the PAC interrupt table is kept */ +EXTERN(__INTERRUPTS); + + +/* Pull in defmt's linker script to generate the defmt table that host decoders expect */ +INCLUDE defmt.x + +ENTRY(Reset) +EXTERN(VECTOR_TABLE) +EXTERN(Reset) +EXTERN(main) + +/* Define _stack_start at end of RAM BEFORE it's used in vector table */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +SECTIONS +{ + .vector_table ORIGIN(RAM) : + { + /* Slot 0: Initial stack pointer - use our explicitly set _stack_start */ + LONG(_stack_start); + /* Slot 1: Reset vector - address of Reset function with Thumb bit set */ + LONG(Reset | 1); + /* Cortex-M33 core exceptions (slots 2-14) */ + KEEP(*(.vector_table.exceptions)); + /* Peripheral interrupt vectors provided by PAC (slots 16+) */ + KEEP(*(.vector_table.interrupts)); + } > RAM + + .text : + { + KEEP(*(.text.Reset)); + KEEP(*(.text.main)); + *(.text .text.*); + } > RAM + + /* Keep defmt table and fragments so host decoders can find metadata */ + .defmt : + { + KEEP(*(.defmt)); + KEEP(*(.defmt.*)); + } > RAM + + .rodata : + { + *(.rodata .rodata.*); + } > RAM + + .data : + { + . = ALIGN(4); + __sdata = .; + *(.data .data.*); + . = ALIGN(4); + __edata = .; + } > RAM + + /* Ensure RTT control block with "SEGGER RTT" signature is loaded to RAM */ + .rtt : + { + KEEP(*(.rtt)); + } > RAM + + /* Place uninitialized buffers (like defmt-rtt) in RAM; load is fine for RAM-run */ + .uninit : + { + *(.uninit .uninit.*); + } > RAM + + .bss : + { + . = ALIGN(4); + __sbss = .; + *(.bss .bss.*); + . = ALIGN(4); + __ebss = .; + } > RAM + + /* Discard exception unwinding info */ + /DISCARD/ : + { + *(.ARM.exidx .ARM.exidx.*); + } +} diff --git a/embassy-mcxa/run.sh b/embassy-mcxa/run.sh new file mode 100644 index 000000000..418dc8a24 --- /dev/null +++ b/embassy-mcxa/run.sh @@ -0,0 +1,93 @@ +#!/usr/bin/env bash +set -euo pipefail + +ELF="${1:-}" +if [[ -z "${ELF}" ]]; then + echo "Usage: $0 " + exit 1 +fi +if [[ ! -f "${ELF}" ]]; then + echo "ELF not found: ${ELF}" + exit 1 +fi + +# Configurable via env +CHIP="${CHIP:-MCXA276}" +SPEED="${PROBE_SPEED:-1000}" # kHz +# Default to J-Link if PROBE not provided +PROBE_OPT=(--probe "${PROBE:-1366:0101:000600110607}") +PORT="${PROBE_RS_GDB_PORT:-1337}" + +cleanup() { + if [[ -n "${GDB_SERVER_PID:-}" ]]; then kill "${GDB_SERVER_PID}" 2>/dev/null || true; fi + [[ -n "${GDB_SCRIPT:-}" ]] && rm -f "${GDB_SCRIPT}" || true + [[ -n "${SERVER_LOG:-}" ]] && rm -f "${SERVER_LOG}" || true +} +trap cleanup EXIT + +if ! command -v probe-rs >/dev/null 2>&1; then + echo "probe-rs not found (cargo install probe-rs --features cli)" + exit 1 +fi +if ! command -v gdb-multiarch >/dev/null 2>&1; then + echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." + exit 1 +fi + +# Start probe-rs GDB server and capture its output to a log (do not hide errors) +SERVER_LOG=$(mktemp) +set +e +probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" "${PROBE_OPT[@]}" \ + >"${SERVER_LOG}" 2>&1 & +GDB_SERVER_PID=$! +set -e + +# Wait for server readiness without touching the TCP port to avoid corrupting the GDB protocol +ready="" +for _ in {1..50}; do + if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then ready=1; break; fi + if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then + echo "probe-rs gdb server failed to connect to target. Log:" >&2 + echo "----- probe-rs gdb log -----" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + exit 1 + fi + sleep 0.1 +done +if [[ -z "${ready}" ]]; then + echo "probe-rs gdb server did not report readiness. Log:" >&2 + echo "----- probe-rs gdb log -----" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + exit 1 +fi + +# GDB script: load to RAM and run, no reset +GDB_SCRIPT=$(mktemp) +cat >"${GDB_SCRIPT}" <&2 + echo "----- probe-rs gdb log -----" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + exit 1 +fi + +echo "Program loaded and started (no reset)" diff --git a/embassy-mcxa/rustfmt.toml b/embassy-mcxa/rustfmt.toml new file mode 100644 index 000000000..9eb3c3b4f --- /dev/null +++ b/embassy-mcxa/rustfmt.toml @@ -0,0 +1,3 @@ +group_imports = "StdExternalCrate" +imports_granularity = "Module" +max_width = 120 diff --git a/embassy-mcxa/src/adc.rs b/embassy-mcxa/src/adc.rs new file mode 100644 index 000000000..b5ec5983f --- /dev/null +++ b/embassy-mcxa/src/adc.rs @@ -0,0 +1,409 @@ +//! ADC driver +use core::sync::atomic::{AtomicBool, Ordering}; + +use embassy_hal_internal::{Peri, PeripheralType}; + +use crate::clocks::periph_helpers::{AdcClockSel, AdcConfig, Div4}; +use crate::clocks::{enable_and_reset, Gate, PoweredClock}; +use crate::pac; +use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres}; +use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts}; +use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode}; +use crate::pac::adc1::ctrl::CalAvgs; +use crate::pac::adc1::tctrl::{Tcmd, Tpri}; + +type Regs = pac::adc1::RegisterBlock; + +static INTERRUPT_TRIGGERED: AtomicBool = AtomicBool::new(false); +// Token-based instance pattern like embassy-imxrt +pub trait Instance: Gate + PeripheralType { + fn ptr() -> *const Regs; +} + +/// Token for ADC1 +pub type Adc1 = crate::peripherals::ADC1; +impl Instance for crate::peripherals::ADC1 { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Adc1::ptr() + } +} + +// Also implement Instance for the Peri wrapper type +// impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> { +// #[inline(always)] +// fn ptr() -> *const Regs { +// pac::Adc1::ptr() +// } +// } + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[repr(u8)] +pub enum TriggerPriorityPolicy { + ConvPreemptImmediatelyNotAutoResumed = 0, + ConvPreemptSoftlyNotAutoResumed = 1, + ConvPreemptImmediatelyAutoRestarted = 4, + ConvPreemptSoftlyAutoRestarted = 5, + ConvPreemptImmediatelyAutoResumed = 12, + ConvPreemptSoftlyAutoResumed = 13, + ConvPreemptSubsequentlyNotAutoResumed = 2, + ConvPreemptSubsequentlyAutoRestarted = 6, + ConvPreemptSubsequentlyAutoResumed = 14, + TriggerPriorityExceptionDisabled = 16, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct LpadcConfig { + pub enable_in_doze_mode: bool, + pub conversion_average_mode: CalAvgs, + pub enable_analog_preliminary: bool, + pub power_up_delay: u8, + pub reference_voltage_source: Refsel, + pub power_level_mode: Pwrsel, + pub trigger_priority_policy: TriggerPriorityPolicy, + pub enable_conv_pause: bool, + pub conv_pause_delay: u16, + pub fifo_watermark: u8, + pub power: PoweredClock, + pub source: AdcClockSel, + pub div: Div4, +} + +impl Default for LpadcConfig { + fn default() -> Self { + LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::NoAverage, + enable_analog_preliminary: false, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option1, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ConvCommandConfig { + pub sample_channel_mode: Ctype, + pub channel_number: Adch, + pub chained_next_command_number: Next, + pub enable_auto_channel_increment: bool, + pub loop_count: u8, + pub hardware_average_mode: Avgs, + pub sample_time_mode: Sts, + pub hardware_compare_mode: Cmpen, + pub hardware_compare_value_high: u32, + pub hardware_compare_value_low: u32, + pub conversion_resolution_mode: Mode, + pub enable_wait_trigger: bool, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ConvTriggerConfig { + pub target_command_id: Tcmd, + pub delay_power: u8, + pub priority: Tpri, + pub enable_hardware_trigger: bool, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ConvResult { + pub command_id_source: u32, + pub loop_count_index: u32, + pub trigger_id_source: u32, + pub conv_value: u16, +} + +pub struct Adc<'a, I: Instance> { + _inst: core::marker::PhantomData<&'a mut I>, +} + +impl<'a, I: Instance> Adc<'a, I> { + /// initialize ADC + pub fn new(_inst: Peri<'a, I>, config: LpadcConfig) -> Self { + let adc = unsafe { &*I::ptr() }; + + let _clock_freq = unsafe { + enable_and_reset::(&AdcConfig { + power: config.power, + source: config.source, + div: config.div, + }) + .expect("Adc Init should not fail") + }; + + /* Reset the module. */ + adc.ctrl().modify(|_, w| w.rst().held_in_reset()); + adc.ctrl().modify(|_, w| w.rst().released_from_reset()); + + adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset()); + + /* Disable the module before setting configuration. */ + adc.ctrl().modify(|_, w| w.adcen().disabled()); + + /* Configure the module generally. */ + if config.enable_in_doze_mode { + adc.ctrl().modify(|_, w| w.dozen().enabled()); + } else { + adc.ctrl().modify(|_, w| w.dozen().disabled()); + } + + /* Set calibration average mode. */ + adc.ctrl() + .modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode)); + + adc.cfg().write(|w| unsafe { + let w = if config.enable_analog_preliminary { + w.pwren().pre_enabled() + } else { + w + }; + + w.pudly() + .bits(config.power_up_delay) + .refsel() + .variant(config.reference_voltage_source) + .pwrsel() + .variant(config.power_level_mode) + .tprictrl() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority, + TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority, + _ => Tprictrl::AbortCurrentOnPriority, + }) + .tres() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled, + _ => Tres::Disabled, + }) + .tcmdres() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed + | TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled, + _ => Tcmdres::Disabled, + }) + .hpt_exdi() + .variant(match config.trigger_priority_policy { + TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled, + _ => HptExdi::Enabled, + }) + }); + + if config.enable_conv_pause { + adc.pause() + .modify(|_, w| unsafe { w.pauseen().enabled().pausedly().bits(config.conv_pause_delay) }); + } else { + adc.pause().write(|w| unsafe { w.bits(0) }); + } + + adc.fctrl0() + .write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) }); + + // Enable ADC + adc.ctrl().modify(|_, w| w.adcen().enabled()); + + Self { + _inst: core::marker::PhantomData, + } + } + + pub fn deinit(&self) { + let adc = unsafe { &*I::ptr() }; + adc.ctrl().modify(|_, w| w.adcen().disabled()); + } + + pub fn do_offset_calibration(&self) { + let adc = unsafe { &*I::ptr() }; + // Enable calibration mode + adc.ctrl() + .modify(|_, w| w.calofs().offset_calibration_request_pending()); + + // Wait for calibration to complete (polling status register) + while adc.stat().read().cal_rdy().is_not_set() {} + } + + pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32 { + let mut gcra_array = [0u32; 17]; + let mut gcalr: u32 = 0; + + for i in (1..=17).rev() { + let shift = 16 - (i - 1); + let step = 1.0 / (1u32 << shift) as f32; + let tmp = (gain_adjustment / step) as u32; + gcra_array[i - 1] = tmp; + gain_adjustment -= tmp as f32 * step; + } + + for i in (1..=17).rev() { + gcalr += gcra_array[i - 1] << (i - 1); + } + gcalr + } + + pub fn do_auto_calibration(&self) { + let adc = unsafe { &*I::ptr() }; + adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending()); + + while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} + + let mut gcca = adc.gcc0().read().gain_cal().bits() as u32; + if gcca & ((0xFFFF + 1) >> 1) != 0 { + gcca |= !0xFFFF; + } + + let gcra = 131072.0 / (131072.0 - gcca as f32); + + // Write to GCR0 + adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); + + adc.gcr0().modify(|_, w| w.rdy().set_bit()); + + // Wait for calibration to complete (polling status register) + while adc.stat().read().cal_rdy().is_not_set() {} + } + + pub fn do_software_trigger(&self, trigger_id_mask: u32) { + let adc = unsafe { &*I::ptr() }; + adc.swtrig().write(|w| unsafe { w.bits(trigger_id_mask) }); + } + + pub fn get_default_conv_command_config(&self) -> ConvCommandConfig { + ConvCommandConfig { + sample_channel_mode: Ctype::SingleEndedASideChannel, + channel_number: Adch::SelectCh0, + chained_next_command_number: Next::NoNextCmdTerminateOnFinish, + enable_auto_channel_increment: false, + loop_count: 0, + hardware_average_mode: Avgs::NoAverage, + sample_time_mode: Sts::Sample3p5, + hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult, + hardware_compare_value_high: 0, + hardware_compare_value_low: 0, + conversion_resolution_mode: Mode::Data12Bits, + enable_wait_trigger: false, + } + } + + //TBD Need to add cmdlx and cmdhx with x {2..7} + pub fn set_conv_command_config(&self, index: u32, config: &ConvCommandConfig) { + let adc = unsafe { &*I::ptr() }; + + match index { + 1 => { + adc.cmdl1().write(|w| { + w.adch() + .variant(config.channel_number) + .mode() + .variant(config.conversion_resolution_mode) + }); + adc.cmdh1().write(|w| unsafe { + w.next() + .variant(config.chained_next_command_number) + .loop_() + .bits(config.loop_count) + .avgs() + .variant(config.hardware_average_mode) + .sts() + .variant(config.sample_time_mode) + .cmpen() + .variant(config.hardware_compare_mode); + if config.enable_wait_trigger { + w.wait_trig().enabled(); + } + if config.enable_auto_channel_increment { + w.lwi().enabled(); + } + w + }); + } + _ => panic!("Invalid command index: must be between 1 and 7"), + } + } + + pub fn get_default_conv_trigger_config(&self) -> ConvTriggerConfig { + ConvTriggerConfig { + target_command_id: Tcmd::NotValid, + delay_power: 0, + priority: Tpri::HighestPriority, + enable_hardware_trigger: false, + } + } + + pub fn set_conv_trigger_config(&self, trigger_id: usize, config: &ConvTriggerConfig) { + let adc = unsafe { &*I::ptr() }; + let tctrl = &adc.tctrl(trigger_id); + + tctrl.write(|w| unsafe { + let w = w.tcmd().variant(config.target_command_id); + let w = w.tdly().bits(config.delay_power); + w.tpri().variant(config.priority); + if config.enable_hardware_trigger { + w.hten().enabled() + } else { + w + } + }); + } + + pub fn do_reset_fifo(&self) { + let adc = unsafe { &*I::ptr() }; + adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset()); + } + + pub fn enable_interrupt(&self, mask: u32) { + let adc = unsafe { &*I::ptr() }; + adc.ie().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); + INTERRUPT_TRIGGERED.store(false, Ordering::SeqCst); + } + + pub fn is_interrupt_triggered(&self) -> bool { + INTERRUPT_TRIGGERED.load(Ordering::Relaxed) + } +} + +pub fn get_conv_result() -> Option { + let adc = unsafe { &*pac::Adc1::ptr() }; + let fifo = adc.resfifo0().read().bits(); + const VALID_MASK: u32 = 1 << 31; + if fifo & VALID_MASK == 0 { + return None; + } + + Some(ConvResult { + command_id_source: (fifo >> 24) & 0x0F, + loop_count_index: (fifo >> 20) & 0x0F, + trigger_id_source: (fifo >> 16) & 0x0F, + conv_value: (fifo & 0xFFFF) as u16, + }) +} + +pub fn on_interrupt() { + if get_conv_result().is_some() { + INTERRUPT_TRIGGERED.store(true, Ordering::SeqCst); + } +} + +pub struct AdcHandler; +impl crate::interrupt::typelevel::Handler for AdcHandler { + unsafe fn on_interrupt() { + on_interrupt(); + } +} diff --git a/embassy-mcxa/src/clkout.rs b/embassy-mcxa/src/clkout.rs new file mode 100644 index 000000000..88c731df1 --- /dev/null +++ b/embassy-mcxa/src/clkout.rs @@ -0,0 +1,169 @@ +//! CLKOUT pseudo-peripheral +//! +//! CLKOUT is a part of the clock generation subsystem, and can be used +//! either to generate arbitrary waveforms, or to debug the state of +//! internal oscillators. + +use core::marker::PhantomData; + +use embassy_hal_internal::Peri; + +pub use crate::clocks::periph_helpers::Div4; +use crate::clocks::{with_clocks, ClockError, PoweredClock}; +use crate::pac::mrcc0::mrcc_clkout_clksel::Mux; +use crate::peripherals::CLKOUT; + +/// A peripheral representing the CLKOUT pseudo-peripheral +pub struct ClockOut<'a> { + _p: PhantomData<&'a mut CLKOUT>, + freq: u32, +} + +/// Selected clock source to output +pub enum ClockOutSel { + /// 12MHz Internal Oscillator + Fro12M, + /// FRO180M Internal Oscillator, via divisor + FroHfDiv, + /// External Oscillator + ClkIn, + /// 16KHz oscillator + Clk16K, + /// Output of PLL1 + Pll1Clk, + /// Main System CPU clock, divided by 6 + SlowClk, +} + +/// Configuration for the ClockOut +pub struct Config { + /// Selected Source Clock + pub sel: ClockOutSel, + /// Selected division level + pub div: Div4, + /// Selected power level + pub level: PoweredClock, +} + +impl<'a> ClockOut<'a> { + /// Create a new ClockOut pin. On success, the clock signal will begin immediately + /// on the given pin. + pub fn new( + _peri: Peri<'a, CLKOUT>, + pin: Peri<'a, impl sealed::ClockOutPin>, + cfg: Config, + ) -> Result { + // There's no MRCC enable bit, so we check the validity of the clocks here + // + // TODO: Should we check that the frequency is suitably low? + let (freq, mux) = check_sel(cfg.sel, cfg.level)?; + + // All good! Apply requested config, starting with the pin. + pin.mux(); + + setup_clkout(mux, cfg.div); + + Ok(Self { + _p: PhantomData, + freq: freq / cfg.div.into_divisor(), + }) + } + + /// Frequency of the clkout pin + #[inline] + pub fn frequency(&self) -> u32 { + self.freq + } +} + +impl Drop for ClockOut<'_> { + fn drop(&mut self) { + disable_clkout(); + } +} + +/// Check whether the given clock selection is valid +fn check_sel(sel: ClockOutSel, level: PoweredClock) -> Result<(u32, Mux), ClockError> { + let res = with_clocks(|c| { + Ok(match sel { + ClockOutSel::Fro12M => (c.ensure_fro_hf_active(&level)?, Mux::Clkroot12m), + ClockOutSel::FroHfDiv => (c.ensure_fro_hf_div_active(&level)?, Mux::ClkrootFircDiv), + ClockOutSel::ClkIn => (c.ensure_clk_in_active(&level)?, Mux::ClkrootSosc), + ClockOutSel::Clk16K => (c.ensure_clk_16k_vdd_core_active(&level)?, Mux::Clkroot16k), + ClockOutSel::Pll1Clk => (c.ensure_pll1_clk_active(&level)?, Mux::ClkrootSpll), + ClockOutSel::SlowClk => (c.ensure_slow_clk_active(&level)?, Mux::ClkrootSlow), + }) + }); + let Some(res) = res else { + return Err(ClockError::NeverInitialized); + }; + res +} + +/// Set up the clkout pin using the given mux and div settings +fn setup_clkout(mux: Mux, div: Div4) { + let mrcc = unsafe { crate::pac::Mrcc0::steal() }; + + mrcc.mrcc_clkout_clksel().write(|w| w.mux().variant(mux)); + + // Set up clkdiv + mrcc.mrcc_clkout_clkdiv().write(|w| { + w.halt().set_bit(); + w.reset().set_bit(); + unsafe { w.div().bits(div.into_bits()) }; + w + }); + mrcc.mrcc_clkout_clkdiv().write(|w| { + w.halt().clear_bit(); + w.reset().clear_bit(); + unsafe { w.div().bits(div.into_bits()) }; + w + }); + + while mrcc.mrcc_clkout_clkdiv().read().unstab().bit_is_set() {} +} + +/// Stop the clkout +fn disable_clkout() { + // Stop the output by selecting the "none" clock + // + // TODO: restore the pin to hi-z or something? + let mrcc = unsafe { crate::pac::Mrcc0::steal() }; + mrcc.mrcc_clkout_clkdiv().write(|w| { + w.reset().set_bit(); + w.halt().set_bit(); + unsafe { + w.div().bits(0); + } + w + }); + mrcc.mrcc_clkout_clksel().write(|w| unsafe { w.bits(0b111) }); +} + +mod sealed { + use embassy_hal_internal::PeripheralType; + + use crate::gpio::{Pull, SealedPin}; + + /// Sealed marker trait for clockout pins + pub trait ClockOutPin: PeripheralType { + /// Set the given pin to the correct muxing state + fn mux(&self); + } + + macro_rules! impl_pin { + ($pin:ident, $func:ident) => { + impl ClockOutPin for crate::peripherals::$pin { + fn mux(&self) { + self.set_function(crate::pac::port0::pcr0::Mux::$func); + self.set_pull(Pull::Disabled); + } + } + }; + } + + impl_pin!(P0_6, Mux12); + impl_pin!(P3_6, Mux1); + impl_pin!(P3_8, Mux12); + impl_pin!(P4_2, Mux1); +} diff --git a/embassy-mcxa/src/clocks/config.rs b/embassy-mcxa/src/clocks/config.rs new file mode 100644 index 000000000..0563b8917 --- /dev/null +++ b/embassy-mcxa/src/clocks/config.rs @@ -0,0 +1,204 @@ +//! Clock Configuration +//! +//! This module holds configuration types used for the system clocks. For +//! configuration of individual peripherals, see [`super::periph_helpers`]. + +use super::PoweredClock; + +/// This type represents a divider in the range 1..=256. +/// +/// At a hardware level, this is an 8-bit register from 0..=255, +/// which adds one. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub struct Div8(pub(super) u8); + +impl Div8 { + /// Store a "raw" divisor value that will divide the source by + /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source + /// by 1, and `Div8::from_raw(255)` will divide the source by + /// 256. + pub const fn from_raw(n: u8) -> Self { + Self(n) + } + + /// Divide by one, or no division + pub const fn no_div() -> Self { + Self(0) + } + + /// Store a specific divisor value that will divide the source + /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source + /// by 1, and `Div8::from_divisor(256)` will divide the source + /// by 256. + /// + /// Will return `None` if `n` is not in the range `1..=256`. + /// Consider [`Self::from_raw`] for an infallible version. + pub const fn from_divisor(n: u16) -> Option { + let Some(n) = n.checked_sub(1) else { + return None; + }; + if n > (u8::MAX as u16) { + return None; + } + Some(Self(n as u8)) + } + + /// Convert into "raw" bits form + #[inline(always)] + pub const fn into_bits(self) -> u8 { + self.0 + } + + /// Convert into "divisor" form, as a u32 for convenient frequency math + #[inline(always)] + pub const fn into_divisor(self) -> u32 { + self.0 as u32 + 1 + } +} + +/// ```text +/// ┌─────────────────────────────────────────────────────────┐ +/// │ │ +/// │ ┌───────────┐ clk_out ┌─────────┐ │ +/// XTAL ──────┼──▷│ System │───────────▷│ │ clk_in │ +/// │ │ OSC │ clkout_byp │ MUX │──────────────────┼──────▷ +/// EXTAL ──────┼──▷│ │───────────▷│ │ │ +/// │ └───────────┘ └─────────┘ │ +/// │ │ +/// │ ┌───────────┐ fro_hf_root ┌────┐ fro_hf │ +/// │ │ FRO180 ├───────┬─────▷│ CG │─────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_45m │ +/// │ │ │ └─────▷│ CG │─────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ ┌───────────┐ fro_12m_root ┌────┐ fro_12m │ +/// │ │ FRO12M │────────┬─────▷│ CG │────────────────────┼──────▷ +/// │ │ │ │ ├────┤ clk_1m │ +/// │ │ │ └─────▷│1/12│────────────────────┼──────▷ +/// │ └───────────┘ └────┘ │ +/// │ │ +/// │ ┌──────────┐ │ +/// │ │000 │ │ +/// │ clk_in │ │ │ +/// │ ───────────────▷│001 │ │ +/// │ fro_12m │ │ │ +/// │ ───────────────▷│010 │ │ +/// │ fro_hf_root │ │ │ +/// │ ───────────────▷│011 │ main_clk │ +/// │ │ │───────────────────────────┼──────▷ +/// clk_16k ──────┼─────────────────▷│100 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│101 │ │ +/// │ pll1_clk │ │ │ +/// │ ───────────────▷│110 │ │ +/// │ none │ │ │ +/// │ ───────────────▷│111 │ │ +/// │ └──────────┘ │ +/// │ ▲ │ +/// │ │ │ +/// │ SCG SCS │ +/// │ SCG-Lite │ +/// └─────────────────────────────────────────────────────────┘ +/// +/// +/// clk_in ┌─────┐ +/// ───────────────▷│00 │ +/// clk_45m │ │ +/// ───────────────▷│01 │ ┌───────────┐ pll1_clk +/// none │ │─────▷│ SPLL │───────────────▷ +/// ───────────────▷│10 │ └───────────┘ +/// fro_12m │ │ +/// ───────────────▷│11 │ +/// └─────┘ +/// ``` +#[non_exhaustive] +pub struct ClocksConfig { + /// FIRC, FRO180, 45/60/90/180M clock source + pub firc: Option, + /// SIRC, FRO12M, clk_12m clock source + // NOTE: I don't think we *can* disable the SIRC? + pub sirc: SircConfig, + /// FRO16K clock source + pub fro16k: Option, +} + +// FIRC/FRO180M + +/// ```text +/// ┌───────────┐ fro_hf_root ┌────┐ fro_hf +/// │ FRO180M ├───────┬─────▷│GATE│──────────▷ +/// │ │ │ ├────┤ clk_45m +/// │ │ └─────▷│GATE│──────────▷ +/// └───────────┘ └────┘ +/// ``` +#[non_exhaustive] +pub struct FircConfig { + /// Selected clock frequency + pub frequency: FircFreqSel, + /// Selected power state of the clock + pub power: PoweredClock, + /// Is the "fro_hf" gated clock enabled? + pub fro_hf_enabled: bool, + /// Is the "clk_45m" gated clock enabled? + pub clk_45m_enabled: bool, + /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`! + pub fro_hf_div: Option, +} + +/// Selected FIRC frequency +pub enum FircFreqSel { + /// 45MHz Output + Mhz45, + /// 60MHz Output + Mhz60, + /// 90MHz Output + Mhz90, + /// 180MHz Output + Mhz180, +} + +// SIRC/FRO12M + +/// ```text +/// ┌───────────┐ fro_12m_root ┌────┐ fro_12m +/// │ FRO12M │────────┬─────▷│ CG │──────────▷ +/// │ │ │ ├────┤ clk_1m +/// │ │ └─────▷│1/12│──────────▷ +/// └───────────┘ └────┘ +/// ``` +#[non_exhaustive] +pub struct SircConfig { + pub power: PoweredClock, + // peripheral output, aka sirc_12mhz + pub fro_12m_enabled: bool, + /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`! + pub fro_lf_div: Option, +} + +#[non_exhaustive] +pub struct Fro16KConfig { + pub vsys_domain_active: bool, + pub vdd_core_domain_active: bool, +} + +impl Default for ClocksConfig { + fn default() -> Self { + Self { + firc: Some(FircConfig { + frequency: FircFreqSel::Mhz45, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + fro_hf_enabled: true, + clk_45m_enabled: true, + fro_hf_div: None, + }), + sirc: SircConfig { + power: PoweredClock::AlwaysEnabled, + fro_12m_enabled: true, + fro_lf_div: None, + }, + fro16k: Some(Fro16KConfig { + vsys_domain_active: true, + vdd_core_domain_active: true, + }), + } + } +} diff --git a/embassy-mcxa/src/clocks/mod.rs b/embassy-mcxa/src/clocks/mod.rs new file mode 100644 index 000000000..9c9e6ef3d --- /dev/null +++ b/embassy-mcxa/src/clocks/mod.rs @@ -0,0 +1,943 @@ +//! # Clock Module +//! +//! For the MCX-A, we separate clock and peripheral control into two main stages: +//! +//! 1. At startup, e.g. when `embassy_mcxa::init()` is called, we configure the +//! core system clocks, including external and internal oscillators. This +//! configuration is then largely static for the duration of the program. +//! 2. When HAL drivers are created, e.g. `Lpuart::new()` is called, the driver +//! is responsible for two main things: +//! * Ensuring that any required "upstream" core system clocks necessary for +//! clocking the peripheral is active and configured to a reasonable value +//! * Enabling the clock gates for that peripheral, and resetting the peripheral +//! +//! From a user perspective, only step 1 is visible. Step 2 is automatically handled +//! by HAL drivers, using interfaces defined in this module. +//! +//! It is also possible to *view* the state of the clock configuration after [`init()`] +//! has been called, using the [`with_clocks()`] function, which provides a view of the +//! [`Clocks`] structure. +//! +//! ## For HAL driver implementors +//! +//! The majority of peripherals in the MCXA chip are fed from either a "hard-coded" or +//! configurable clock source, e.g. selecting the FROM12M or `clk_1m` as a source. This +//! selection, as well as often any pre-scaler division from that source clock, is made +//! through MRCC registers. +//! +//! Any peripheral that is controlled through the MRCC register can automatically implement +//! the necessary APIs using the `impl_cc_gate!` macro in this module. You will also need +//! to define the configuration surface and steps necessary to fully configure that peripheral +//! from a clocks perspective by: +//! +//! 1. Defining a configuration type in the [`periph_helpers`] module that contains any selects +//! or divisions available to the HAL driver +//! 2. Implementing the [`periph_helpers::SPConfHelper`] trait, which should check that the +//! necessary input clocks are reasonable + +use core::cell::RefCell; + +use config::{ClocksConfig, FircConfig, FircFreqSel, Fro16KConfig, SircConfig}; +use mcxa_pac::scg0::firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}; +use mcxa_pac::scg0::sirccsr::{SircClkPeriphEn, Sircsten}; +use periph_helpers::SPConfHelper; + +use crate::pac; +pub mod config; +pub mod periph_helpers; + +// +// Statics/Consts +// + +/// The state of system core clocks. +/// +/// Initialized by [`init()`], and then unchanged for the remainder of the program. +static CLOCKS: critical_section::Mutex>> = critical_section::Mutex::new(RefCell::new(None)); + +// +// Free functions +// + +/// Initialize the core system clocks with the given [`ClocksConfig`]. +/// +/// This function should be called EXACTLY once at start-up, usually via a +/// call to [`embassy_mcxa::init()`](crate::init()). Subsequent calls will +/// return an error. +pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { + critical_section::with(|cs| { + if CLOCKS.borrow_ref(cs).is_some() { + Err(ClockError::AlreadyInitialized) + } else { + Ok(()) + } + })?; + + let mut clocks = Clocks::default(); + let mut operator = ClockOperator { + clocks: &mut clocks, + config: &settings, + + _mrcc0: unsafe { pac::Mrcc0::steal() }, + scg0: unsafe { pac::Scg0::steal() }, + syscon: unsafe { pac::Syscon::steal() }, + vbat0: unsafe { pac::Vbat0::steal() }, + }; + + operator.configure_firc_clocks()?; + operator.configure_sirc_clocks()?; + operator.configure_fro16k_clocks()?; + + // For now, just use FIRC as the main/cpu clock, which should already be + // the case on reset + assert!(operator.scg0.rccr().read().scs().is_firc()); + let input = operator.clocks.fro_hf_root.clone().unwrap(); + operator.clocks.main_clk = Some(input.clone()); + // We can also assume cpu/system clk == fro_hf because div is /1. + assert_eq!(operator.syscon.ahbclkdiv().read().div().bits(), 0); + operator.clocks.cpu_system_clk = Some(input); + + critical_section::with(|cs| { + let mut clks = CLOCKS.borrow_ref_mut(cs); + assert!(clks.is_none(), "Clock setup race!"); + *clks = Some(clocks); + }); + + Ok(()) +} + +/// Obtain the full clocks structure, calling the given closure in a critical section. +/// +/// The given closure will be called with read-only access to the state of the system +/// clocks. This can be used to query and return the state of a given clock. +/// +/// As the caller's closure will be called in a critical section, care must be taken +/// not to block or cause any other undue delays while accessing. +/// +/// Calls to this function will not succeed until after a successful call to `init()`, +/// and will always return None. +pub fn with_clocks R>(f: F) -> Option { + critical_section::with(|cs| { + let c = CLOCKS.borrow_ref(cs); + let c = c.as_ref()?; + Some(f(c)) + }) +} + +// +// Structs/Enums +// + +/// The `Clocks` structure contains the initialized state of the core system clocks +/// +/// These values are configured by providing [`config::ClocksConfig`] to the [`init()`] function +/// at boot time. +#[derive(Default, Debug, Clone)] +#[non_exhaustive] +pub struct Clocks { + /// The `clk_in` is a clock provided by an external oscillator + pub clk_in: Option, + + // FRO180M stuff + // + /// `fro_hf_root` is the direct output of the `FRO180M` internal oscillator + /// + /// It is used to feed downstream clocks, such as `fro_hf`, `clk_45m`, + /// and `fro_hf_div`. + pub fro_hf_root: Option, + + /// `fro_hf` is the same frequency as `fro_hf_root`, but behind a gate. + pub fro_hf: Option, + + /// `clk_45` is a 45MHz clock, sourced from `fro_hf`. + pub clk_45m: Option, + + /// `fro_hf_div` is a configurable frequency clock, sourced from `fro_hf`. + pub fro_hf_div: Option, + + // + // End FRO180M + + // FRO12M stuff + // + /// `fro_12m_root` is the direct output of the `FRO12M` internal oscillator + /// + /// It is used to feed downstream clocks, such as `fro_12m`, `clk_1m`, + /// `and `fro_lf_div`. + pub fro_12m_root: Option, + + /// `fro_12m` is the same frequency as `fro_12m_root`, but behind a gate. + pub fro_12m: Option, + + /// `clk_1m` is a 1MHz clock, sourced from `fro_12m` + pub clk_1m: Option, + + /// `fro_lf_div` is a configurable frequency clock, sourced from `fro_12m` + pub fro_lf_div: Option, + // + // End FRO12M stuff + /// `clk_16k_vsys` is one of two outputs of the `FRO16K` internal oscillator. + /// + /// Also referred to as `clk_16k[0]` in the datasheet, it feeds peripherals in + /// the system domain, such as the CMP and RTC. + pub clk_16k_vsys: Option, + + /// `clk_16k_vdd_core` is one of two outputs of the `FRO16K` internal oscillator. + /// + /// Also referred to as `clk_16k[1]` in the datasheet, it feeds peripherals in + /// the VDD Core domain, such as the OSTimer or LPUarts. + pub clk_16k_vdd_core: Option, + + /// `main_clk` is the main clock used by the CPU, AHB, APB, IPS bus, and some + /// peripherals. + pub main_clk: Option, + + /// `CPU_CLK` or `SYSTEM_CLK` is the output of `main_clk`, run through the `AHBCLKDIV` + pub cpu_system_clk: Option, + + /// `pll1_clk` is the output of the main system PLL, `pll1`. + pub pll1_clk: Option, +} + +/// `ClockError` is the main error returned when configuring or checking clock state +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[non_exhaustive] +pub enum ClockError { + /// The system clocks were never initialized by calling [`init()`] + NeverInitialized, + /// The [`init()`] function was called more than once + AlreadyInitialized, + /// The requested configuration was not possible to fulfill, as the system clocks + /// were not configured in a compatible way + BadConfig { clock: &'static str, reason: &'static str }, + /// The requested configuration was not possible to fulfill, as the required system + /// clocks have not yet been implemented. + NotImplemented { clock: &'static str }, + /// The requested peripheral could not be configured, as the steps necessary to + /// enable it have not yet been implemented. + UnimplementedConfig, +} + +/// Information regarding a system clock +#[derive(Debug, Clone)] +pub struct Clock { + /// The frequency, in Hz, of the given clock + pub frequency: u32, + /// The power state of the clock, e.g. whether it is active in deep sleep mode + /// or not. + pub power: PoweredClock, +} + +/// The power state of a given clock. +/// +/// On the MCX-A, when Deep-Sleep is entered, any clock not configured for Deep Sleep +/// mode will be stopped. This means that any downstream usage, e.g. by peripherals, +/// will also stop. +/// +/// In the future, we will provide an API for entering Deep Sleep, and if there are +/// any peripherals that are NOT using an `AlwaysEnabled` clock active, entry into +/// Deep Sleep will be prevented, in order to avoid misbehaving peripherals. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum PoweredClock { + /// The given clock will NOT continue running in Deep Sleep mode + NormalEnabledDeepSleepDisabled, + /// The given clock WILL continue running in Deep Sleep mode + AlwaysEnabled, +} + +/// The ClockOperator is a private helper type that contains the methods used +/// during system clock initialization. +/// +/// # SAFETY +/// +/// Concurrent access to clock-relevant peripheral registers, such as `MRCC`, `SCG`, +/// `SYSCON`, and `VBAT` should not be allowed for the duration of the [`init()`] function. +struct ClockOperator<'a> { + /// A mutable reference to the current state of system clocks + clocks: &'a mut Clocks, + /// A reference to the requested configuration provided by the caller of [`init()`] + config: &'a ClocksConfig, + + // We hold on to stolen peripherals + _mrcc0: pac::Mrcc0, + scg0: pac::Scg0, + syscon: pac::Syscon, + vbat0: pac::Vbat0, +} + +/// Trait describing an AHB clock gate that can be toggled through MRCC. +pub trait Gate { + type MrccPeriphConfig: SPConfHelper; + + /// Enable the clock gate. + /// + /// # SAFETY + /// + /// The current peripheral must be disabled prior to calling this method + unsafe fn enable_clock(); + + /// Disable the clock gate. + /// + /// # SAFETY + /// + /// There must be no active user of this peripheral when calling this method + unsafe fn disable_clock(); + + /// Drive the peripheral into reset. + /// + /// # SAFETY + /// + /// There must be no active user of this peripheral when calling this method + unsafe fn assert_reset(); + + /// Drive the peripheral out of reset. + /// + /// # SAFETY + /// + /// There must be no active user of this peripheral when calling this method + unsafe fn release_reset(); + + /// Return whether the clock gate for this peripheral is currently enabled. + fn is_clock_enabled() -> bool; + + /// Return whether the peripheral is currently held in reset. + fn is_reset_released() -> bool; +} + +/// This is the primary helper method HAL drivers are expected to call when creating +/// an instance of the peripheral. +/// +/// This method: +/// +/// 1. Enables the MRCC clock gate for this peripheral +/// 2. Calls the `G::MrccPeriphConfig::post_enable_config()` method, returning an error +/// and re-disabling the peripheral if this fails. +/// 3. Pulses the MRCC reset line, to reset the peripheral to the default state +/// 4. Returns the frequency, in Hz that is fed into the peripheral, taking into account +/// the selected upstream clock, as well as any division specified by `cfg`. +/// +/// NOTE: if a clock is disabled, sourced from an "ambient" clock source, this method +/// may return `Ok(0)`. In the future, this might be updated to return the correct +/// "ambient" clock, e.g. the AHB/APB frequency. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `enable_and_reset`. +#[inline] +pub unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Result { + let freq = enable::(cfg).inspect_err(|_| disable::())?; + pulse_reset::(); + Ok(freq) +} + +/// Enable the clock gate for the given peripheral. +/// +/// Prefer [`enable_and_reset`] unless you are specifically avoiding a pulse of the reset, or need +/// to control the duration of the pulse more directly. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `enable`. +#[inline] +pub unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result { + G::enable_clock(); + while !G::is_clock_enabled() {} + core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); + + let freq = critical_section::with(|cs| { + let clocks = CLOCKS.borrow_ref(cs); + let clocks = clocks.as_ref().ok_or(ClockError::NeverInitialized)?; + cfg.post_enable_config(clocks) + }); + + freq.inspect_err(|_e| { + G::disable_clock(); + }) +} + +/// Disable the clock gate for the given peripheral. +/// +/// # SAFETY +/// +/// This peripheral must no longer be in use prior to calling `enable`. +#[allow(dead_code)] +#[inline] +pub unsafe fn disable() { + G::disable_clock(); +} + +/// Check whether a gate is currently enabled. +#[allow(dead_code)] +#[inline] +pub fn is_clock_enabled() -> bool { + G::is_clock_enabled() +} + +/// Release a reset line for the given peripheral set. +/// +/// Prefer [`enable_and_reset`]. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `release_reset`. +#[inline] +pub unsafe fn release_reset() { + G::release_reset(); +} + +/// Assert a reset line for the given peripheral set. +/// +/// Prefer [`enable_and_reset`]. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `assert_reset`. +#[inline] +pub unsafe fn assert_reset() { + G::assert_reset(); +} + +/// Check whether the peripheral is held in reset. +#[inline] +pub unsafe fn is_reset_released() -> bool { + G::is_reset_released() +} + +/// Pulse a reset line (assert then release) with a short delay. +/// +/// Prefer [`enable_and_reset`]. +/// +/// # SAFETY +/// +/// This peripheral must not yet be in use prior to calling `release_reset`. +#[inline] +pub unsafe fn pulse_reset() { + G::assert_reset(); + cortex_m::asm::nop(); + cortex_m::asm::nop(); + G::release_reset(); +} + +// +// `impl`s for structs/enums +// + +/// The [`Clocks`] type's methods generally take the form of "ensure X clock is active". +/// +/// These methods are intended to be used by HAL peripheral implementors to ensure that their +/// selected clocks are active at a suitable level at time of construction. These methods +/// return the frequency of the requested clock, in Hertz, or a [`ClockError`]. +impl Clocks { + /// Ensure the `fro_lf_div` clock is active and valid at the given power state. + pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_lf_div.as_ref() else { + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "not low power active", + }); + } + Ok(clk.frequency) + } + + /// Ensure the `fro_hf` clock is active and valid at the given power state. + pub fn ensure_fro_hf_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_hf.as_ref() else { + return Err(ClockError::BadConfig { + clock: "fro_hf", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "fro_hf", + reason: "not low power active", + }); + } + Ok(clk.frequency) + } + + /// Ensure the `fro_hf_div` clock is active and valid at the given power state. + pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.fro_hf_div.as_ref() else { + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "not low power active", + }); + } + Ok(clk.frequency) + } + + /// Ensure the `clk_in` clock is active and valid at the given power state. + pub fn ensure_clk_in_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "clk_in" }) + } + + /// Ensure the `clk_16k_vsys` clock is active and valid at the given power state. + pub fn ensure_clk_16k_vsys_active(&self, _at_level: &PoweredClock) -> Result { + // NOTE: clk_16k is always active in low power mode + Ok(self + .clk_16k_vsys + .as_ref() + .ok_or(ClockError::BadConfig { + clock: "clk_16k_vsys", + reason: "required but not active", + })? + .frequency) + } + + /// Ensure the `clk_16k_vdd_core` clock is active and valid at the given power state. + pub fn ensure_clk_16k_vdd_core_active(&self, _at_level: &PoweredClock) -> Result { + // NOTE: clk_16k is always active in low power mode + Ok(self + .clk_16k_vdd_core + .as_ref() + .ok_or(ClockError::BadConfig { + clock: "clk_16k_vdd_core", + reason: "required but not active", + })? + .frequency) + } + + /// Ensure the `clk_1m` clock is active and valid at the given power state. + pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.clk_1m.as_ref() else { + return Err(ClockError::BadConfig { + clock: "clk_1m", + reason: "required but not active", + }); + }; + if !clk.power.meets_requirement_of(at_level) { + return Err(ClockError::BadConfig { + clock: "clk_1m", + reason: "not low power active", + }); + } + Ok(clk.frequency) + } + + /// Ensure the `pll1_clk` clock is active and valid at the given power state. + pub fn ensure_pll1_clk_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "pll1_clk" }) + } + + /// Ensure the `pll1_clk_div` clock is active and valid at the given power state. + pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result { + Err(ClockError::NotImplemented { clock: "pll1_clk_div" }) + } + + /// Ensure the `CPU_CLK` or `SYSTEM_CLK` is active + pub fn ensure_cpu_system_clk_active(&self, at_level: &PoweredClock) -> Result { + let Some(clk) = self.cpu_system_clk.as_ref() else { + return Err(ClockError::BadConfig { + clock: "cpu_system_clk", + reason: "required but not active", + }); + }; + // Can the main_clk ever be active in deep sleep? I think it is gated? + match at_level { + PoweredClock::NormalEnabledDeepSleepDisabled => {} + PoweredClock::AlwaysEnabled => { + return Err(ClockError::BadConfig { + clock: "main_clk", + reason: "not low power active", + }); + } + } + + Ok(clk.frequency) + } + + pub fn ensure_slow_clk_active(&self, at_level: &PoweredClock) -> Result { + let freq = self.ensure_cpu_system_clk_active(at_level)?; + + Ok(freq / 6) + } +} + +impl PoweredClock { + /// Does THIS clock meet the power requirements of the OTHER clock? + pub fn meets_requirement_of(&self, other: &Self) -> bool { + match (self, other) { + (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::AlwaysEnabled) => false, + (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true, + (PoweredClock::AlwaysEnabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true, + (PoweredClock::AlwaysEnabled, PoweredClock::AlwaysEnabled) => true, + } + } +} + +impl ClockOperator<'_> { + /// Configure the FIRC/FRO180M clock family + /// + /// NOTE: Currently we require this to be a fairly hardcoded value, as this clock is used + /// as the main clock used for the CPU, AHB, APB, etc. + fn configure_firc_clocks(&mut self) -> Result<(), ClockError> { + const HARDCODED_ERR: Result<(), ClockError> = Err(ClockError::BadConfig { + clock: "firc", + reason: "For now, FIRC must be enabled and in default state!", + }); + + // Did the user give us a FIRC config? + let Some(firc) = self.config.firc.as_ref() else { + return HARDCODED_ERR; + }; + // Is the FIRC set to 45MHz (should be reset default) + if !matches!(firc.frequency, FircFreqSel::Mhz45) { + return HARDCODED_ERR; + } + let base_freq = 45_000_000; + + // Now, check if the FIRC as expected for our hardcoded value + let mut firc_ok = true; + + // Is the hardware currently set to the default 45MHz? + // + // NOTE: the SVD currently has the wrong(?) values for these: + // 45 -> 48 + // 60 -> 64 + // 90 -> 96 + // 180 -> 192 + // Probably correct-ish, but for a different trim value? + firc_ok &= self.scg0.firccfg().read().freq_sel().is_firc_48mhz_192s(); + + // Check some values in the CSR + let csr = self.scg0.firccsr().read(); + // Is it enabled? + firc_ok &= csr.fircen().is_enabled(); + // Is it accurate? + firc_ok &= csr.fircacc().is_enabled_and_valid(); + // Is there no error? + firc_ok &= csr.fircerr().is_error_not_detected(); + // Is the FIRC the system clock? + firc_ok &= csr.fircsel().is_firc(); + // Is it valid? + firc_ok &= csr.fircvld().is_enabled_and_valid(); + + // Are we happy with the current (hardcoded) state? + if !firc_ok { + return HARDCODED_ERR; + } + + // Note that the fro_hf_root is active + self.clocks.fro_hf_root = Some(Clock { + frequency: base_freq, + power: firc.power, + }); + + // Okay! Now we're past that, let's enable all the downstream clocks. + let FircConfig { + frequency: _, + power, + fro_hf_enabled, + clk_45m_enabled, + fro_hf_div, + } = firc; + + // When is the FRO enabled? + let pow_set = match power { + PoweredClock::NormalEnabledDeepSleepDisabled => Fircsten::DisabledInStopModes, + PoweredClock::AlwaysEnabled => Fircsten::EnabledInStopModes, + }; + + // Do we enable the `fro_hf` output? + let fro_hf_set = if *fro_hf_enabled { + self.clocks.fro_hf = Some(Clock { + frequency: base_freq, + power: *power, + }); + FircFclkPeriphEn::Enabled + } else { + FircFclkPeriphEn::Disabled + }; + + // Do we enable the `clk_45m` output? + let clk_45m_set = if *clk_45m_enabled { + self.clocks.clk_45m = Some(Clock { + frequency: 45_000_000, + power: *power, + }); + FircSclkPeriphEn::Enabled + } else { + FircSclkPeriphEn::Disabled + }; + + self.scg0.firccsr().modify(|_r, w| { + w.fircsten().variant(pow_set); + w.firc_fclk_periph_en().variant(fro_hf_set); + w.firc_sclk_periph_en().variant(clk_45m_set); + w + }); + + // Do we enable the `fro_hf_div` output? + if let Some(d) = fro_hf_div.as_ref() { + // We need `fro_hf` to be enabled + if !*fro_hf_enabled { + return Err(ClockError::BadConfig { + clock: "fro_hf_div", + reason: "fro_hf not enabled", + }); + } + + // Halt and reset the div; then set our desired div. + self.syscon.frohfdiv().write(|w| { + w.halt().halt(); + w.reset().asserted(); + unsafe { w.div().bits(d.into_bits()) }; + w + }); + // Then unhalt it, and reset it + self.syscon.frohfdiv().write(|w| { + w.halt().run(); + w.reset().released(); + w + }); + + // Wait for clock to stabilize + while self.syscon.frohfdiv().read().unstab().is_ongoing() {} + + // Store off the clock info + self.clocks.fro_hf_div = Some(Clock { + frequency: base_freq / d.into_divisor(), + power: *power, + }); + } + + Ok(()) + } + + /// Configure the SIRC/FRO12M clock family + fn configure_sirc_clocks(&mut self) -> Result<(), ClockError> { + let SircConfig { + power, + fro_12m_enabled, + fro_lf_div, + } = &self.config.sirc; + let base_freq = 12_000_000; + + // Allow writes + self.scg0.sirccsr().modify(|_r, w| w.lk().write_enabled()); + self.clocks.fro_12m_root = Some(Clock { + frequency: base_freq, + power: *power, + }); + + let deep = match power { + PoweredClock::NormalEnabledDeepSleepDisabled => Sircsten::Disabled, + PoweredClock::AlwaysEnabled => Sircsten::Enabled, + }; + let pclk = if *fro_12m_enabled { + self.clocks.fro_12m = Some(Clock { + frequency: base_freq, + power: *power, + }); + self.clocks.clk_1m = Some(Clock { + frequency: base_freq / 12, + power: *power, + }); + SircClkPeriphEn::Enabled + } else { + SircClkPeriphEn::Disabled + }; + + // Set sleep/peripheral usage + self.scg0.sirccsr().modify(|_r, w| { + w.sircsten().variant(deep); + w.sirc_clk_periph_en().variant(pclk); + w + }); + + while self.scg0.sirccsr().read().sircvld().is_disabled_or_not_valid() {} + if self.scg0.sirccsr().read().sircerr().is_error_detected() { + return Err(ClockError::BadConfig { + clock: "sirc", + reason: "error set", + }); + } + + // reset lock + self.scg0.sirccsr().modify(|_r, w| w.lk().write_disabled()); + + // Do we enable the `fro_lf_div` output? + if let Some(d) = fro_lf_div.as_ref() { + // We need `fro_lf` to be enabled + if !*fro_12m_enabled { + return Err(ClockError::BadConfig { + clock: "fro_lf_div", + reason: "fro_12m not enabled", + }); + } + + // Halt and reset the div; then set our desired div. + self.syscon.frolfdiv().write(|w| { + w.halt().halt(); + w.reset().asserted(); + unsafe { w.div().bits(d.into_bits()) }; + w + }); + // Then unhalt it, and reset it + self.syscon.frolfdiv().modify(|_r, w| { + w.halt().run(); + w.reset().released(); + w + }); + + // Wait for clock to stabilize + while self.syscon.frolfdiv().read().unstab().is_ongoing() {} + + // Store off the clock info + self.clocks.fro_lf_div = Some(Clock { + frequency: base_freq / d.into_divisor(), + power: *power, + }); + } + + Ok(()) + } + + /// Configure the FRO16K/clk_16k clock family + fn configure_fro16k_clocks(&mut self) -> Result<(), ClockError> { + let Some(fro16k) = self.config.fro16k.as_ref() else { + return Ok(()); + }; + // Enable FRO16K oscillator + self.vbat0.froctla().modify(|_, w| w.fro_en().set_bit()); + + // Lock the control register + self.vbat0.frolcka().modify(|_, w| w.lock().set_bit()); + + let Fro16KConfig { + vsys_domain_active, + vdd_core_domain_active, + } = fro16k; + + // Enable clock outputs to both VSYS and VDD_CORE domains + // Bit 0: clk_16k0 to VSYS domain + // Bit 1: clk_16k1 to VDD_CORE domain + // + // TODO: Define sub-fields for this register with a PAC patch? + let mut bits = 0; + if *vsys_domain_active { + bits |= 0b01; + self.clocks.clk_16k_vsys = Some(Clock { + frequency: 16_384, + power: PoweredClock::AlwaysEnabled, + }); + } + if *vdd_core_domain_active { + bits |= 0b10; + self.clocks.clk_16k_vdd_core = Some(Clock { + frequency: 16_384, + power: PoweredClock::AlwaysEnabled, + }); + } + self.vbat0.froclke().modify(|_r, w| unsafe { w.clke().bits(bits) }); + + Ok(()) + } +} + +// +// Macros/macro impls +// + +/// This macro is used to implement the [`Gate`] trait for a given peripheral +/// that is controlled by the MRCC peripheral. +macro_rules! impl_cc_gate { + ($name:ident, $clk_reg:ident, $rst_reg:ident, $field:ident, $config:ty) => { + impl Gate for crate::peripherals::$name { + type MrccPeriphConfig = $config; + + #[inline] + unsafe fn enable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$clk_reg().modify(|_, w| w.$field().enabled()); + } + + #[inline] + unsafe fn disable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$clk_reg().modify(|_r, w| w.$field().disabled()); + } + + #[inline] + fn is_clock_enabled() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$clk_reg().read().$field().is_enabled() + } + + #[inline] + unsafe fn release_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$rst_reg().modify(|_, w| w.$field().enabled()); + } + + #[inline] + unsafe fn assert_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$rst_reg().modify(|_, w| w.$field().disabled()); + } + + #[inline] + fn is_reset_released() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.$rst_reg().read().$field().is_enabled() + } + } + }; +} + +/// This module contains implementations of MRCC APIs, specifically of the [`Gate`] trait, +/// for various low level peripherals. +pub(crate) mod gate { + #[cfg(not(feature = "time"))] + use super::periph_helpers::OsTimerConfig; + use super::periph_helpers::{AdcConfig, Lpi2cConfig, LpuartConfig, NoConfig}; + use super::*; + + // These peripherals have no additional upstream clocks or configuration required + // other than enabling through the MRCC gate. Currently, these peripherals will + // ALWAYS return `Ok(0)` when calling [`enable_and_reset()`] and/or + // [`SPConfHelper::post_enable_config()`]. + impl_cc_gate!(PORT0, mrcc_glb_cc1, mrcc_glb_rst1, port0, NoConfig); + impl_cc_gate!(PORT1, mrcc_glb_cc1, mrcc_glb_rst1, port1, NoConfig); + impl_cc_gate!(PORT2, mrcc_glb_cc1, mrcc_glb_rst1, port2, NoConfig); + impl_cc_gate!(PORT3, mrcc_glb_cc1, mrcc_glb_rst1, port3, NoConfig); + impl_cc_gate!(PORT4, mrcc_glb_cc1, mrcc_glb_rst1, port4, NoConfig); + + impl_cc_gate!(GPIO0, mrcc_glb_cc2, mrcc_glb_rst2, gpio0, NoConfig); + impl_cc_gate!(GPIO1, mrcc_glb_cc2, mrcc_glb_rst2, gpio1, NoConfig); + impl_cc_gate!(GPIO2, mrcc_glb_cc2, mrcc_glb_rst2, gpio2, NoConfig); + impl_cc_gate!(GPIO3, mrcc_glb_cc2, mrcc_glb_rst2, gpio3, NoConfig); + impl_cc_gate!(GPIO4, mrcc_glb_cc2, mrcc_glb_rst2, gpio4, NoConfig); + + // These peripherals DO have meaningful configuration, and could fail if the system + // clocks do not match their needs. + #[cfg(not(feature = "time"))] + impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); + + impl_cc_gate!(LPI2C0, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c0, Lpi2cConfig); + impl_cc_gate!(LPI2C1, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c1, Lpi2cConfig); + impl_cc_gate!(LPI2C2, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c2, Lpi2cConfig); + impl_cc_gate!(LPI2C3, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c3, Lpi2cConfig); + + impl_cc_gate!(LPUART0, mrcc_glb_cc0, mrcc_glb_rst0, lpuart0, LpuartConfig); + impl_cc_gate!(LPUART1, mrcc_glb_cc0, mrcc_glb_rst0, lpuart1, LpuartConfig); + impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig); + impl_cc_gate!(LPUART3, mrcc_glb_cc0, mrcc_glb_rst0, lpuart3, LpuartConfig); + impl_cc_gate!(LPUART4, mrcc_glb_cc0, mrcc_glb_rst0, lpuart4, LpuartConfig); + impl_cc_gate!(LPUART5, mrcc_glb_cc1, mrcc_glb_rst1, lpuart5, LpuartConfig); + impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig); +} diff --git a/embassy-mcxa/src/clocks/periph_helpers.rs b/embassy-mcxa/src/clocks/periph_helpers.rs new file mode 100644 index 000000000..1ea7a99ed --- /dev/null +++ b/embassy-mcxa/src/clocks/periph_helpers.rs @@ -0,0 +1,502 @@ +//! Peripheral Helpers +//! +//! The purpose of this module is to define the per-peripheral special handling +//! required from a clocking perspective. Different peripherals have different +//! selectable source clocks, and some peripherals have additional pre-dividers +//! that can be used. +//! +//! See the docs of [`SPConfHelper`] for more details. + +use super::{ClockError, Clocks, PoweredClock}; +use crate::pac; + +/// Sealed Peripheral Configuration Helper +/// +/// NOTE: the name "sealed" doesn't *totally* make sense because its not sealed yet in the +/// embassy-mcxa project, but it derives from embassy-imxrt where it is. We should +/// fix the name, or actually do the sealing of peripherals. +/// +/// This trait serves to act as a per-peripheral customization for clocking behavior. +/// +/// This trait should be implemented on a configuration type for a given peripheral, and +/// provide the methods that will be called by the higher level operations like +/// `embassy_mcxa::clocks::enable_and_reset()`. +pub trait SPConfHelper { + /// This method is called AFTER a given MRCC peripheral has been enabled (e.g. un-gated), + /// but BEFORE the peripheral reset line is reset. + /// + /// This function should check that any relevant upstream clocks are enabled, are in a + /// reasonable power state, and that the requested configuration can be made. If any of + /// these checks fail, an `Err(ClockError)` should be returned, likely `ClockError::BadConfig`. + /// + /// This function SHOULD NOT make any changes to the system clock configuration, even + /// unsafely, as this should remain static for the duration of the program. + /// + /// This function WILL be called in a critical section, care should be taken not to delay + /// for an unreasonable amount of time. + /// + /// On success, this function MUST return an `Ok(freq)`, where `freq` is the frequency + /// fed into the peripheral, taking into account the selected source clock, as well as + /// any pre-divisors. + fn post_enable_config(&self, clocks: &Clocks) -> Result; +} + +/// Copy and paste macro that: +/// +/// * Sets the clocksel mux to `$selvar` +/// * Resets and halts the div, and applies the calculated div4 bits +/// * Releases reset + halt +/// * Waits for the div to stabilize +/// * Returns `Ok($freq / $conf.div.into_divisor())` +/// +/// Assumes: +/// +/// * self is a configuration struct that has a field called `div`, which +/// is a `Div4` +/// +/// usage: +/// +/// ```rust +/// apply_div4!(self, clksel, clkdiv, variant, freq) +/// ``` +/// +/// In the future if we make all the clksel+clkdiv pairs into commonly derivedFrom +/// registers, or if we put some kind of simple trait around those regs, we could +/// do this with something other than a macro, but for now, this is harm-reduction +/// to avoid incorrect copy + paste +macro_rules! apply_div4 { + ($conf:ident, $selreg:ident, $divreg:ident, $selvar:ident, $freq:ident) => {{ + // set clksel + $selreg.modify(|_r, w| w.mux().variant($selvar)); + + // Set up clkdiv + $divreg.modify(|_r, w| { + unsafe { w.div().bits($conf.div.into_bits()) } + .halt() + .asserted() + .reset() + .asserted() + }); + $divreg.modify(|_r, w| w.halt().deasserted().reset().deasserted()); + + while $divreg.read().unstab().is_unstable() {} + + Ok($freq / $conf.div.into_divisor()) + }}; +} + +// config types + +/// This type represents a divider in the range 1..=16. +/// +/// At a hardware level, this is an 8-bit register from 0..=15, +/// which adds one. +/// +/// While the *clock* domain seems to use 8-bit dividers, the *peripheral* domain +/// seems to use 4 bit dividers! +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub struct Div4(pub(super) u8); + +impl Div4 { + /// Divide by one, or no division + pub const fn no_div() -> Self { + Self(0) + } + + /// Store a "raw" divisor value that will divide the source by + /// `(n + 1)`, e.g. `Div4::from_raw(0)` will divide the source + /// by 1, and `Div4::from_raw(15)` will divide the source by + /// 16. + pub const fn from_raw(n: u8) -> Option { + if n > 0b1111 { + None + } else { + Some(Self(n)) + } + } + + /// Store a specific divisor value that will divide the source + /// by `n`. e.g. `Div4::from_divisor(1)` will divide the source + /// by 1, and `Div4::from_divisor(16)` will divide the source + /// by 16. + /// + /// Will return `None` if `n` is not in the range `1..=16`. + /// Consider [`Self::from_raw`] for an infallible version. + pub const fn from_divisor(n: u8) -> Option { + let Some(n) = n.checked_sub(1) else { + return None; + }; + if n > 0b1111 { + return None; + } + Some(Self(n)) + } + + /// Convert into "raw" bits form + #[inline(always)] + pub const fn into_bits(self) -> u8 { + self.0 + } + + /// Convert into "divisor" form, as a u32 for convenient frequency math + #[inline(always)] + pub const fn into_divisor(self) -> u32 { + self.0 as u32 + 1 + } +} + +/// A basic type that always returns an error when `post_enable_config` is called. +/// +/// Should only be used as a placeholder. +pub struct UnimplementedConfig; + +impl SPConfHelper for UnimplementedConfig { + fn post_enable_config(&self, _clocks: &Clocks) -> Result { + Err(ClockError::UnimplementedConfig) + } +} + +/// A basic type that always returns `Ok(0)` when `post_enable_config` is called. +/// +/// This should only be used for peripherals that are "ambiently" clocked, like `PORTn` +/// peripherals, which have no selectable/configurable source clock. +pub struct NoConfig; +impl SPConfHelper for NoConfig { + fn post_enable_config(&self, _clocks: &Clocks) -> Result { + Ok(0) + } +} + +// +// LPI2c +// + +/// Selectable clocks for `Lpi2c` peripherals +#[derive(Debug, Clone, Copy)] +pub enum Lpi2cClockSel { + /// FRO12M/FRO_LF/SIRC clock source, passed through divider + /// "fro_lf_div" + FroLfDiv, + /// FRO180M/FRO_HF/FIRC clock source, passed through divider + /// "fro_hf_div" + FroHfDiv, + /// SOSC/XTAL/EXTAL clock source + ClkIn, + /// clk_1m/FRO_LF divided by 12 + Clk1M, + /// Output of PLL1, passed through clock divider, + /// "pll1_clk_div", maybe "pll1_lf_div"? + Pll1ClkDiv, + /// Disabled + None, +} + +/// Which instance of the `Lpi2c` is this? +/// +/// Should not be directly selectable by end-users. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum Lpi2cInstance { + /// Instance 0 + Lpi2c0, + /// Instance 1 + Lpi2c1, + /// Instance 2 + Lpi2c2, + /// Instance 3 + Lpi2c3, +} + +/// Top level configuration for `Lpi2c` instances. +pub struct Lpi2cConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Clock source + pub source: Lpi2cClockSel, + /// Clock divisor + pub div: Div4, + /// Which instance is this? + // NOTE: should not be user settable + pub(crate) instance: Lpi2cInstance, +} + +impl SPConfHelper for Lpi2cConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + // check that source is suitable + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + use mcxa_pac::mrcc0::mrcc_lpi2c0_clksel::Mux; + + let (clkdiv, clksel) = match self.instance { + Lpi2cInstance::Lpi2c0 => (mrcc0.mrcc_lpi2c0_clkdiv(), mrcc0.mrcc_lpi2c0_clksel()), + Lpi2cInstance::Lpi2c1 => (mrcc0.mrcc_lpi2c1_clkdiv(), mrcc0.mrcc_lpi2c1_clksel()), + Lpi2cInstance::Lpi2c2 => (mrcc0.mrcc_lpi2c2_clkdiv(), mrcc0.mrcc_lpi2c2_clksel()), + Lpi2cInstance::Lpi2c3 => (mrcc0.mrcc_lpi2c3_clkdiv(), mrcc0.mrcc_lpi2c3_clksel()), + }; + + let (freq, variant) = match self.source { + Lpi2cClockSel::FroLfDiv => { + let freq = clocks.ensure_fro_lf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc0) + } + Lpi2cClockSel::FroHfDiv => { + let freq = clocks.ensure_fro_hf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc2) + } + Lpi2cClockSel::ClkIn => { + let freq = clocks.ensure_clk_in_active(&self.power)?; + (freq, Mux::ClkrootFunc3) + } + Lpi2cClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + (freq, Mux::ClkrootFunc5) + } + Lpi2cClockSel::Pll1ClkDiv => { + let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; + (freq, Mux::ClkrootFunc6) + } + Lpi2cClockSel::None => unsafe { + // no ClkrootFunc7, just write manually for now + clksel.write(|w| w.bits(0b111)); + clkdiv.modify(|_r, w| w.reset().asserted().halt().asserted()); + return Ok(0); + }, + }; + + apply_div4!(self, clksel, clkdiv, variant, freq) + } +} + +// +// LPUart +// + +/// Selectable clocks for Lpuart peripherals +#[derive(Debug, Clone, Copy)] +pub enum LpuartClockSel { + /// FRO12M/FRO_LF/SIRC clock source, passed through divider + /// "fro_lf_div" + FroLfDiv, + /// FRO180M/FRO_HF/FIRC clock source, passed through divider + /// "fro_hf_div" + FroHfDiv, + /// SOSC/XTAL/EXTAL clock source + ClkIn, + /// FRO16K/clk_16k source + Clk16K, + /// clk_1m/FRO_LF divided by 12 + Clk1M, + /// Output of PLL1, passed through clock divider, + /// "pll1_clk_div", maybe "pll1_lf_div"? + Pll1ClkDiv, + /// Disabled + None, +} + +/// Which instance of the Lpuart is this? +/// +/// Should not be directly selectable by end-users. +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum LpuartInstance { + /// Instance 0 + Lpuart0, + /// Instance 1 + Lpuart1, + /// Instance 2 + Lpuart2, + /// Instance 3 + Lpuart3, + /// Instance 4 + Lpuart4, + /// Instance 5 + Lpuart5, +} + +/// Top level configuration for `Lpuart` instances. +pub struct LpuartConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Clock source + pub source: LpuartClockSel, + /// Clock divisor + pub div: Div4, + /// Which instance is this? + // NOTE: should not be user settable + pub(crate) instance: LpuartInstance, +} + +impl SPConfHelper for LpuartConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + // check that source is suitable + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + use mcxa_pac::mrcc0::mrcc_lpuart0_clksel::Mux; + + let (clkdiv, clksel) = match self.instance { + LpuartInstance::Lpuart0 => (mrcc0.mrcc_lpuart0_clkdiv(), mrcc0.mrcc_lpuart0_clksel()), + LpuartInstance::Lpuart1 => (mrcc0.mrcc_lpuart1_clkdiv(), mrcc0.mrcc_lpuart1_clksel()), + LpuartInstance::Lpuart2 => (mrcc0.mrcc_lpuart2_clkdiv(), mrcc0.mrcc_lpuart2_clksel()), + LpuartInstance::Lpuart3 => (mrcc0.mrcc_lpuart3_clkdiv(), mrcc0.mrcc_lpuart3_clksel()), + LpuartInstance::Lpuart4 => (mrcc0.mrcc_lpuart4_clkdiv(), mrcc0.mrcc_lpuart4_clksel()), + LpuartInstance::Lpuart5 => (mrcc0.mrcc_lpuart5_clkdiv(), mrcc0.mrcc_lpuart5_clksel()), + }; + + let (freq, variant) = match self.source { + LpuartClockSel::FroLfDiv => { + let freq = clocks.ensure_fro_lf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc0) + } + LpuartClockSel::FroHfDiv => { + let freq = clocks.ensure_fro_hf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc2) + } + LpuartClockSel::ClkIn => { + let freq = clocks.ensure_clk_in_active(&self.power)?; + (freq, Mux::ClkrootFunc3) + } + LpuartClockSel::Clk16K => { + let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?; + (freq, Mux::ClkrootFunc4) + } + LpuartClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + (freq, Mux::ClkrootFunc5) + } + LpuartClockSel::Pll1ClkDiv => { + let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; + (freq, Mux::ClkrootFunc6) + } + LpuartClockSel::None => unsafe { + // no ClkrootFunc7, just write manually for now + clksel.write(|w| w.bits(0b111)); + clkdiv.modify(|_r, w| { + w.reset().asserted(); + w.halt().asserted(); + w + }); + return Ok(0); + }, + }; + + // set clksel + apply_div4!(self, clksel, clkdiv, variant, freq) + } +} + +// +// OSTimer +// + +/// Selectable clocks for the OSTimer peripheral +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum OstimerClockSel { + /// 16k clock, sourced from FRO16K (Vdd Core) + Clk16kVddCore, + /// 1 MHz Clock sourced from FRO12M + Clk1M, + /// Disabled + None, +} + +/// Top level configuration for the `OSTimer` peripheral +pub struct OsTimerConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Selected clock source for this peripheral + pub source: OstimerClockSel, +} + +impl SPConfHelper for OsTimerConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + Ok(match self.source { + OstimerClockSel::Clk16kVddCore => { + let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?; + mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_16k()); + freq + } + OstimerClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); + freq + } + OstimerClockSel::None => { + mrcc0.mrcc_ostimer0_clksel().write(|w| unsafe { w.mux().bits(0b11) }); + 0 + } + }) + } +} + +// +// Adc +// + +/// Selectable clocks for the ADC peripheral +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum AdcClockSel { + /// Divided `fro_lf`/`clk_12m`/FRO12M source + FroLfDiv, + /// Gated `fro_hf`/`FRO180M` source + FroHf, + /// External Clock Source + ClkIn, + /// 1MHz clock sourced by a divided `fro_lf`/`clk_12m` + Clk1M, + /// Internal PLL output, with configurable divisor + Pll1ClkDiv, + /// No clock/disabled + None, +} + +/// Top level configuration for the ADC peripheral +pub struct AdcConfig { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Selected clock-source for this peripheral + pub source: AdcClockSel, + /// Pre-divisor, applied to the upstream clock output + pub div: Div4, +} + +impl SPConfHelper for AdcConfig { + fn post_enable_config(&self, clocks: &Clocks) -> Result { + use mcxa_pac::mrcc0::mrcc_adc_clksel::Mux; + let mrcc0 = unsafe { pac::Mrcc0::steal() }; + let (freq, variant) = match self.source { + AdcClockSel::FroLfDiv => { + let freq = clocks.ensure_fro_lf_div_active(&self.power)?; + (freq, Mux::ClkrootFunc0) + } + AdcClockSel::FroHf => { + let freq = clocks.ensure_fro_hf_active(&self.power)?; + (freq, Mux::ClkrootFunc1) + } + AdcClockSel::ClkIn => { + let freq = clocks.ensure_clk_in_active(&self.power)?; + (freq, Mux::ClkrootFunc3) + } + AdcClockSel::Clk1M => { + let freq = clocks.ensure_clk_1m_active(&self.power)?; + (freq, Mux::ClkrootFunc5) + } + AdcClockSel::Pll1ClkDiv => { + let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; + (freq, Mux::ClkrootFunc6) + } + AdcClockSel::None => { + mrcc0.mrcc_adc_clksel().write(|w| unsafe { + // no ClkrootFunc7, just write manually for now + w.mux().bits(0b111) + }); + mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { + w.reset().asserted(); + w.halt().asserted(); + w + }); + return Ok(0); + } + }; + let clksel = mrcc0.mrcc_adc_clksel(); + let clkdiv = mrcc0.mrcc_adc_clkdiv(); + + apply_div4!(self, clksel, clkdiv, variant, freq) + } +} diff --git a/embassy-mcxa/src/config.rs b/embassy-mcxa/src/config.rs new file mode 100644 index 000000000..8d52a1d44 --- /dev/null +++ b/embassy-mcxa/src/config.rs @@ -0,0 +1,27 @@ +// HAL configuration (minimal), mirroring embassy-imxrt style + +use crate::clocks::config::ClocksConfig; +use crate::interrupt::Priority; + +#[non_exhaustive] +pub struct Config { + #[cfg(feature = "time")] + pub time_interrupt_priority: Priority, + pub rtc_interrupt_priority: Priority, + pub adc_interrupt_priority: Priority, + pub gpio_interrupt_priority: Priority, + pub clock_cfg: ClocksConfig, +} + +impl Default for Config { + fn default() -> Self { + Self { + #[cfg(feature = "time")] + time_interrupt_priority: Priority::from(0), + rtc_interrupt_priority: Priority::from(0), + adc_interrupt_priority: Priority::from(0), + gpio_interrupt_priority: Priority::from(0), + clock_cfg: ClocksConfig::default(), + } + } +} diff --git a/embassy-mcxa/src/gpio.rs b/embassy-mcxa/src/gpio.rs new file mode 100644 index 000000000..65f8df985 --- /dev/null +++ b/embassy-mcxa/src/gpio.rs @@ -0,0 +1,1062 @@ +//! GPIO driver built around a type-erased `Flex` pin, similar to other Embassy HALs. +//! The exported `Output`/`Input` drivers own a `Flex` so they no longer depend on the +//! concrete pin type. + +use core::convert::Infallible; +use core::future::Future; +use core::marker::PhantomData; +use core::pin::pin; + +use embassy_hal_internal::{Peri, PeripheralType}; +use maitake_sync::WaitMap; +use paste::paste; + +use crate::pac::interrupt; +use crate::pac::port0::pcr0::{Dse, Inv, Mux, Pe, Ps, Sre}; + +struct BitIter(u32); + +impl Iterator for BitIter { + type Item = usize; + + fn next(&mut self) -> Option { + match self.0.trailing_zeros() { + 32 => None, + b => { + self.0 &= !(1 << b); + Some(b as usize) + } + } + } +} + +const PORT_COUNT: usize = 5; + +static PORT_WAIT_MAPS: [WaitMap; PORT_COUNT] = [ + WaitMap::new(), + WaitMap::new(), + WaitMap::new(), + WaitMap::new(), + WaitMap::new(), +]; + +fn irq_handler(port_index: usize, gpio_base: *const crate::pac::gpio0::RegisterBlock) { + let gpio = unsafe { &*gpio_base }; + let isfr = gpio.isfr0().read().bits(); + + for pin in BitIter(isfr) { + // Clear all pending interrupts + gpio.isfr0().write(|w| unsafe { w.bits(1 << pin) }); + gpio.icr(pin).modify(|_, w| w.irqc().irqc0()); // Disable interrupt + + // Wake the corresponding port waker + if let Some(w) = PORT_WAIT_MAPS.get(port_index) { + w.wake(&pin, ()); + } + } +} + +#[interrupt] +fn GPIO0() { + irq_handler(0, crate::pac::Gpio0::ptr()); +} + +#[interrupt] +fn GPIO1() { + irq_handler(1, crate::pac::Gpio1::ptr()); +} + +#[interrupt] +fn GPIO2() { + irq_handler(2, crate::pac::Gpio2::ptr()); +} + +#[interrupt] +fn GPIO3() { + irq_handler(3, crate::pac::Gpio3::ptr()); +} + +#[interrupt] +fn GPIO4() { + irq_handler(4, crate::pac::Gpio4::ptr()); +} + +pub(crate) unsafe fn init() { + use embassy_hal_internal::interrupt::InterruptExt; + + crate::pac::interrupt::GPIO0.enable(); + crate::pac::interrupt::GPIO1.enable(); + crate::pac::interrupt::GPIO2.enable(); + crate::pac::interrupt::GPIO3.enable(); + crate::pac::interrupt::GPIO4.enable(); + + cortex_m::interrupt::enable(); +} + +/// Logical level for GPIO pins. +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Level { + Low, + High, +} + +impl From for Level { + fn from(val: bool) -> Self { + match val { + true => Self::High, + false => Self::Low, + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum Pull { + Disabled, + Up, + Down, +} + +impl From for (Pe, Ps) { + fn from(pull: Pull) -> Self { + match pull { + Pull::Disabled => (Pe::Pe0, Ps::Ps0), + Pull::Up => (Pe::Pe1, Ps::Ps1), + Pull::Down => (Pe::Pe1, Ps::Ps0), + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum SlewRate { + Fast, + Slow, +} + +impl From for Sre { + fn from(slew_rate: SlewRate) -> Self { + match slew_rate { + SlewRate::Fast => Sre::Sre0, + SlewRate::Slow => Sre::Sre1, + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum DriveStrength { + Normal, + Double, +} + +impl From for Dse { + fn from(strength: DriveStrength) -> Self { + match strength { + DriveStrength::Normal => Dse::Dse0, + DriveStrength::Double => Dse::Dse1, + } + } +} + +#[derive(Copy, Clone, Eq, PartialEq, Debug)] +pub enum Inverter { + Disabled, + Enabled, +} + +impl From for Inv { + fn from(strength: Inverter) -> Self { + match strength { + Inverter::Disabled => Inv::Inv0, + Inverter::Enabled => Inv::Inv1, + } + } +} + +pub type Gpio = crate::peripherals::GPIO0; + +/// Type-erased representation of a GPIO pin. +pub struct AnyPin { + port: usize, + pin: usize, + gpio: &'static crate::pac::gpio0::RegisterBlock, + port_reg: &'static crate::pac::port0::RegisterBlock, + pcr_reg: &'static crate::pac::port0::Pcr0, +} + +impl AnyPin { + /// Create an `AnyPin` from raw components. + fn new( + port: usize, + pin: usize, + gpio: &'static crate::pac::gpio0::RegisterBlock, + port_reg: &'static crate::pac::port0::RegisterBlock, + pcr_reg: &'static crate::pac::port0::Pcr0, + ) -> Self { + Self { + port, + pin, + gpio, + port_reg, + pcr_reg, + } + } + + #[inline(always)] + fn mask(&self) -> u32 { + 1 << self.pin + } + + #[inline(always)] + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + self.gpio + } + + #[inline(always)] + pub fn port_index(&self) -> usize { + self.port + } + + #[inline(always)] + pub fn pin_index(&self) -> usize { + self.pin + } + + #[inline(always)] + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { + self.port_reg + } + + #[inline(always)] + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { + self.pcr_reg + } +} + +embassy_hal_internal::impl_peripheral!(AnyPin); + +pub(crate) trait SealedPin { + fn pin_port(&self) -> usize; + + fn port(&self) -> usize { + self.pin_port() / 32 + } + + fn pin(&self) -> usize { + self.pin_port() % 32 + } + + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock; + + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock; + + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0; + + fn set_function(&self, function: Mux); + + fn set_pull(&self, pull: Pull); + + fn set_drive_strength(&self, strength: Dse); + + fn set_slew_rate(&self, slew_rate: Sre); + + fn set_enable_input_buffer(&self); +} + +/// GPIO pin trait. +#[allow(private_bounds)] +pub trait GpioPin: SealedPin + Sized + PeripheralType + Into + 'static { + /// Type-erase the pin. + fn degrade(self) -> AnyPin { + // SAFETY: This is only called within the GpioPin trait, which is only + // implemented within this module on valid pin peripherals and thus + // has been verified to be correct. + AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg()) + } +} + +impl SealedPin for AnyPin { + fn pin_port(&self) -> usize { + self.port * 32 + self.pin + } + + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + self.gpio() + } + + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { + self.port_reg() + } + + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { + self.pcr_reg() + } + + fn set_function(&self, function: Mux) { + self.pcr_reg().modify(|_, w| w.mux().variant(function)); + } + + fn set_pull(&self, pull: Pull) { + let (pull_enable, pull_select) = pull.into(); + self.pcr_reg().modify(|_, w| { + w.pe().variant(pull_enable); + w.ps().variant(pull_select) + }); + } + + fn set_drive_strength(&self, strength: Dse) { + self.pcr_reg().modify(|_, w| w.dse().variant(strength)); + } + + fn set_slew_rate(&self, slew_rate: Sre) { + self.pcr_reg().modify(|_, w| w.sre().variant(slew_rate)); + } + + fn set_enable_input_buffer(&self) { + self.pcr_reg().modify(|_, w| w.ibe().ibe1()); + } +} + +impl GpioPin for AnyPin {} + +macro_rules! impl_pin { + ($peri:ident, $port:expr, $pin:expr, $block:ident) => { + paste! { + impl SealedPin for crate::peripherals::$peri { + fn pin_port(&self) -> usize { + $port * 32 + $pin + } + + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + unsafe { &*crate::pac::$block::ptr() } + } + + fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { + unsafe { &*crate::pac::[]::ptr() } + } + + fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { + self.port_reg().[]() + } + + fn set_function(&self, function: Mux) { + unsafe { + let port_reg = &*crate::pac::[]::ptr(); + port_reg.[]().modify(|_, w| { + w.mux().variant(function) + }); + } + } + + fn set_pull(&self, pull: Pull) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + let (pull_enable, pull_select) = pull.into(); + port_reg.[]().modify(|_, w| { + w.pe().variant(pull_enable); + w.ps().variant(pull_select) + }); + } + + fn set_drive_strength(&self, strength: Dse) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + port_reg.[]().modify(|_, w| w.dse().variant(strength)); + } + + fn set_slew_rate(&self, slew_rate: Sre) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + port_reg.[]().modify(|_, w| w.sre().variant(slew_rate)); + } + + fn set_enable_input_buffer(&self) { + let port_reg = unsafe {&*crate::pac::[]::ptr()}; + port_reg.[]().modify(|_, w| w.ibe().ibe1()); + } + } + + impl GpioPin for crate::peripherals::$peri {} + + impl From for AnyPin { + fn from(value: crate::peripherals::$peri) -> Self { + value.degrade() + } + } + + impl crate::peripherals::$peri { + /// Convenience helper to obtain a type-erased handle to this pin. + pub fn degrade(&self) -> AnyPin { + AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg()) + } + } + } + }; +} + +impl_pin!(P0_0, 0, 0, Gpio0); +impl_pin!(P0_1, 0, 1, Gpio0); +impl_pin!(P0_2, 0, 2, Gpio0); +impl_pin!(P0_3, 0, 3, Gpio0); +impl_pin!(P0_4, 0, 4, Gpio0); +impl_pin!(P0_5, 0, 5, Gpio0); +impl_pin!(P0_6, 0, 6, Gpio0); +impl_pin!(P0_7, 0, 7, Gpio0); +impl_pin!(P0_8, 0, 8, Gpio0); +impl_pin!(P0_9, 0, 9, Gpio0); +impl_pin!(P0_10, 0, 10, Gpio0); +impl_pin!(P0_11, 0, 11, Gpio0); +impl_pin!(P0_12, 0, 12, Gpio0); +impl_pin!(P0_13, 0, 13, Gpio0); +impl_pin!(P0_14, 0, 14, Gpio0); +impl_pin!(P0_15, 0, 15, Gpio0); +impl_pin!(P0_16, 0, 16, Gpio0); +impl_pin!(P0_17, 0, 17, Gpio0); +impl_pin!(P0_18, 0, 18, Gpio0); +impl_pin!(P0_19, 0, 19, Gpio0); +impl_pin!(P0_20, 0, 20, Gpio0); +impl_pin!(P0_21, 0, 21, Gpio0); +impl_pin!(P0_22, 0, 22, Gpio0); +impl_pin!(P0_23, 0, 23, Gpio0); +impl_pin!(P0_24, 0, 24, Gpio0); +impl_pin!(P0_25, 0, 25, Gpio0); +impl_pin!(P0_26, 0, 26, Gpio0); +impl_pin!(P0_27, 0, 27, Gpio0); +impl_pin!(P0_28, 0, 28, Gpio0); +impl_pin!(P0_29, 0, 29, Gpio0); +impl_pin!(P0_30, 0, 30, Gpio0); +impl_pin!(P0_31, 0, 31, Gpio0); + +impl_pin!(P1_0, 1, 0, Gpio1); +impl_pin!(P1_1, 1, 1, Gpio1); +impl_pin!(P1_2, 1, 2, Gpio1); +impl_pin!(P1_3, 1, 3, Gpio1); +impl_pin!(P1_4, 1, 4, Gpio1); +impl_pin!(P1_5, 1, 5, Gpio1); +impl_pin!(P1_6, 1, 6, Gpio1); +impl_pin!(P1_7, 1, 7, Gpio1); +impl_pin!(P1_8, 1, 8, Gpio1); +impl_pin!(P1_9, 1, 9, Gpio1); +impl_pin!(P1_10, 1, 10, Gpio1); +impl_pin!(P1_11, 1, 11, Gpio1); +impl_pin!(P1_12, 1, 12, Gpio1); +impl_pin!(P1_13, 1, 13, Gpio1); +impl_pin!(P1_14, 1, 14, Gpio1); +impl_pin!(P1_15, 1, 15, Gpio1); +impl_pin!(P1_16, 1, 16, Gpio1); +impl_pin!(P1_17, 1, 17, Gpio1); +impl_pin!(P1_18, 1, 18, Gpio1); +impl_pin!(P1_19, 1, 19, Gpio1); +impl_pin!(P1_20, 1, 20, Gpio1); +impl_pin!(P1_21, 1, 21, Gpio1); +impl_pin!(P1_22, 1, 22, Gpio1); +impl_pin!(P1_23, 1, 23, Gpio1); +impl_pin!(P1_24, 1, 24, Gpio1); +impl_pin!(P1_25, 1, 25, Gpio1); +impl_pin!(P1_26, 1, 26, Gpio1); +impl_pin!(P1_27, 1, 27, Gpio1); +impl_pin!(P1_28, 1, 28, Gpio1); +impl_pin!(P1_29, 1, 29, Gpio1); +impl_pin!(P1_30, 1, 30, Gpio1); +impl_pin!(P1_31, 1, 31, Gpio1); + +impl_pin!(P2_0, 2, 0, Gpio2); +impl_pin!(P2_1, 2, 1, Gpio2); +impl_pin!(P2_2, 2, 2, Gpio2); +impl_pin!(P2_3, 2, 3, Gpio2); +impl_pin!(P2_4, 2, 4, Gpio2); +impl_pin!(P2_5, 2, 5, Gpio2); +impl_pin!(P2_6, 2, 6, Gpio2); +impl_pin!(P2_7, 2, 7, Gpio2); +impl_pin!(P2_8, 2, 8, Gpio2); +impl_pin!(P2_9, 2, 9, Gpio2); +impl_pin!(P2_10, 2, 10, Gpio2); +impl_pin!(P2_11, 2, 11, Gpio2); +impl_pin!(P2_12, 2, 12, Gpio2); +impl_pin!(P2_13, 2, 13, Gpio2); +impl_pin!(P2_14, 2, 14, Gpio2); +impl_pin!(P2_15, 2, 15, Gpio2); +impl_pin!(P2_16, 2, 16, Gpio2); +impl_pin!(P2_17, 2, 17, Gpio2); +impl_pin!(P2_18, 2, 18, Gpio2); +impl_pin!(P2_19, 2, 19, Gpio2); +impl_pin!(P2_20, 2, 20, Gpio2); +impl_pin!(P2_21, 2, 21, Gpio2); +impl_pin!(P2_22, 2, 22, Gpio2); +impl_pin!(P2_23, 2, 23, Gpio2); +impl_pin!(P2_24, 2, 24, Gpio2); +impl_pin!(P2_25, 2, 25, Gpio2); +impl_pin!(P2_26, 2, 26, Gpio2); +impl_pin!(P2_27, 2, 27, Gpio2); +impl_pin!(P2_28, 2, 28, Gpio2); +impl_pin!(P2_29, 2, 29, Gpio2); +impl_pin!(P2_30, 2, 30, Gpio2); +impl_pin!(P2_31, 2, 31, Gpio2); + +impl_pin!(P3_0, 3, 0, Gpio3); +impl_pin!(P3_1, 3, 1, Gpio3); +impl_pin!(P3_2, 3, 2, Gpio3); +impl_pin!(P3_3, 3, 3, Gpio3); +impl_pin!(P3_4, 3, 4, Gpio3); +impl_pin!(P3_5, 3, 5, Gpio3); +impl_pin!(P3_6, 3, 6, Gpio3); +impl_pin!(P3_7, 3, 7, Gpio3); +impl_pin!(P3_8, 3, 8, Gpio3); +impl_pin!(P3_9, 3, 9, Gpio3); +impl_pin!(P3_10, 3, 10, Gpio3); +impl_pin!(P3_11, 3, 11, Gpio3); +impl_pin!(P3_12, 3, 12, Gpio3); +impl_pin!(P3_13, 3, 13, Gpio3); +impl_pin!(P3_14, 3, 14, Gpio3); +impl_pin!(P3_15, 3, 15, Gpio3); +impl_pin!(P3_16, 3, 16, Gpio3); +impl_pin!(P3_17, 3, 17, Gpio3); +impl_pin!(P3_18, 3, 18, Gpio3); +impl_pin!(P3_19, 3, 19, Gpio3); +impl_pin!(P3_20, 3, 20, Gpio3); +impl_pin!(P3_21, 3, 21, Gpio3); +impl_pin!(P3_22, 3, 22, Gpio3); +impl_pin!(P3_23, 3, 23, Gpio3); +impl_pin!(P3_24, 3, 24, Gpio3); +impl_pin!(P3_25, 3, 25, Gpio3); +impl_pin!(P3_26, 3, 26, Gpio3); +impl_pin!(P3_27, 3, 27, Gpio3); +impl_pin!(P3_28, 3, 28, Gpio3); +impl_pin!(P3_29, 3, 29, Gpio3); +impl_pin!(P3_30, 3, 30, Gpio3); +impl_pin!(P3_31, 3, 31, Gpio3); + +impl_pin!(P4_0, 4, 0, Gpio4); +impl_pin!(P4_1, 4, 1, Gpio4); +impl_pin!(P4_2, 4, 2, Gpio4); +impl_pin!(P4_3, 4, 3, Gpio4); +impl_pin!(P4_4, 4, 4, Gpio4); +impl_pin!(P4_5, 4, 5, Gpio4); +impl_pin!(P4_6, 4, 6, Gpio4); +impl_pin!(P4_7, 4, 7, Gpio4); +impl_pin!(P4_8, 4, 8, Gpio4); +impl_pin!(P4_9, 4, 9, Gpio4); +impl_pin!(P4_10, 4, 10, Gpio4); +impl_pin!(P4_11, 4, 11, Gpio4); +impl_pin!(P4_12, 4, 12, Gpio4); +impl_pin!(P4_13, 4, 13, Gpio4); +impl_pin!(P4_14, 4, 14, Gpio4); +impl_pin!(P4_15, 4, 15, Gpio4); +impl_pin!(P4_16, 4, 16, Gpio4); +impl_pin!(P4_17, 4, 17, Gpio4); +impl_pin!(P4_18, 4, 18, Gpio4); +impl_pin!(P4_19, 4, 19, Gpio4); +impl_pin!(P4_20, 4, 20, Gpio4); +impl_pin!(P4_21, 4, 21, Gpio4); +impl_pin!(P4_22, 4, 22, Gpio4); +impl_pin!(P4_23, 4, 23, Gpio4); +impl_pin!(P4_24, 4, 24, Gpio4); +impl_pin!(P4_25, 4, 25, Gpio4); +impl_pin!(P4_26, 4, 26, Gpio4); +impl_pin!(P4_27, 4, 27, Gpio4); +impl_pin!(P4_28, 4, 28, Gpio4); +impl_pin!(P4_29, 4, 29, Gpio4); +impl_pin!(P4_30, 4, 30, Gpio4); +impl_pin!(P4_31, 4, 31, Gpio4); + +/// A flexible pin that can be configured as input or output. +pub struct Flex<'d> { + pin: Peri<'d, AnyPin>, + _marker: PhantomData<&'d mut ()>, +} + +impl<'d> Flex<'d> { + /// Wrap the pin in a `Flex`. + /// + /// The pin remains unmodified. The initial output level is unspecified, but + /// can be changed before the pin is put into output mode. + pub fn new(pin: Peri<'d, impl GpioPin>) -> Self { + pin.set_function(Mux::Mux0); + Self { + pin: pin.into(), + _marker: PhantomData, + } + } + + #[inline] + fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { + self.pin.gpio() + } + + #[inline] + fn mask(&self) -> u32 { + self.pin.mask() + } + + /// Put the pin into input mode. + pub fn set_as_input(&mut self) { + let mask = self.mask(); + let gpio = self.gpio(); + + self.set_enable_input_buffer(); + + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); + } + + /// Put the pin into output mode. + pub fn set_as_output(&mut self) { + let mask = self.mask(); + let gpio = self.gpio(); + + self.set_pull(Pull::Disabled); + + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); + } + + /// Set output level to High. + #[inline] + pub fn set_high(&mut self) { + self.gpio().psor().write(|w| unsafe { w.bits(self.mask()) }); + } + + /// Set output level to Low. + #[inline] + pub fn set_low(&mut self) { + self.gpio().pcor().write(|w| unsafe { w.bits(self.mask()) }); + } + + /// Set output level to the given `Level`. + #[inline] + pub fn set_level(&mut self, level: Level) { + match level { + Level::High => self.set_high(), + Level::Low => self.set_low(), + } + } + + /// Toggle output level. + #[inline] + pub fn toggle(&mut self) { + self.gpio().ptor().write(|w| unsafe { w.bits(self.mask()) }); + } + + /// Get whether the pin input level is high. + #[inline] + pub fn is_high(&self) -> bool { + (self.gpio().pdir().read().bits() & self.mask()) != 0 + } + + /// Get whether the pin input level is low. + #[inline] + pub fn is_low(&self) -> bool { + !self.is_high() + } + + /// Is the output pin set as high? + #[inline] + pub fn is_set_high(&self) -> bool { + self.is_high() + } + + /// Is the output pin set as low? + #[inline] + pub fn is_set_low(&self) -> bool { + !self.is_set_high() + } + + /// Configure the pin pull up/down level. + pub fn set_pull(&mut self, pull_select: Pull) { + self.pin.set_pull(pull_select); + } + + /// Configure the pin drive strength. + pub fn set_drive_strength(&mut self, strength: DriveStrength) { + self.pin.set_drive_strength(strength.into()); + } + + /// Configure the pin slew rate. + pub fn set_slew_rate(&mut self, slew_rate: SlewRate) { + self.pin.set_slew_rate(slew_rate.into()); + } + + /// Enable input buffer for the pin. + pub fn set_enable_input_buffer(&mut self) { + self.pin.set_enable_input_buffer(); + } + + /// Get pin level. + pub fn get_level(&self) -> Level { + self.is_high().into() + } +} + +/// Async methods +impl<'d> Flex<'d> { + /// Helper function that waits for a given interrupt trigger + async fn wait_for_inner(&mut self, level: crate::pac::gpio0::icr::Irqc) { + // First, ensure that we have a waker that is ready for this port+pin + let w = PORT_WAIT_MAPS[self.pin.port].wait(self.pin.pin); + let mut w = pin!(w); + // Wait for the subscription to occur, which requires polling at least once + // + // This function returns a result, but can only be an Err if: + // + // * We call `.close()` on a WaitMap, which we never do + // * We have a duplicate key, which can't happen because `wait_for_*` methods + // take an &mut ref of their unique port+pin combo + // + // So we wait for it to complete, but ignore the result. + _ = w.as_mut().subscribe().await; + + // Now that our waker is in the map, we can enable the appropriate interrupt + // + // Clear any existing pending interrupt on this pin + self.pin + .gpio() + .isfr0() + .write(|w| unsafe { w.bits(1 << self.pin.pin()) }); + self.pin.gpio().icr(self.pin.pin()).write(|w| w.isf().isf1()); + + // Pin interrupt configuration + self.pin + .gpio() + .icr(self.pin.pin()) + .modify(|_, w| w.irqc().variant(level)); + + // Finally, we can await the matching call to `.wake()` from the interrupt. + // + // Again, technically, this could return a result, but for the same reasons + // as above, this can't be an error in our case, so just wait for it to complete + _ = w.await; + } + + /// Wait until the pin is high. If it is already high, return immediately. + #[inline] + pub fn wait_for_high(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc12) + } + + /// Wait until the pin is low. If it is already low, return immediately. + #[inline] + pub fn wait_for_low(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc8) + } + + /// Wait for the pin to undergo a transition from low to high. + #[inline] + pub fn wait_for_rising_edge(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc9) + } + + /// Wait for the pin to undergo a transition from high to low. + #[inline] + pub fn wait_for_falling_edge(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc10) + } + + /// Wait for the pin to undergo any transition, i.e low to high OR high to low. + #[inline] + pub fn wait_for_any_edge(&mut self) -> impl Future + use<'_, 'd> { + self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc11) + } +} + +/// GPIO output driver that owns a `Flex` pin. +pub struct Output<'d> { + flex: Flex<'d>, +} + +impl<'d> Output<'d> { + /// Create a GPIO output driver for a [GpioPin] with the provided [Level]. + pub fn new(pin: Peri<'d, impl GpioPin>, initial: Level, strength: DriveStrength, slew_rate: SlewRate) -> Self { + let mut flex = Flex::new(pin); + flex.set_level(initial); + flex.set_as_output(); + flex.set_drive_strength(strength); + flex.set_slew_rate(slew_rate); + Self { flex } + } + + /// Set the output as high. + #[inline] + pub fn set_high(&mut self) { + self.flex.set_high(); + } + + /// Set the output as low. + #[inline] + pub fn set_low(&mut self) { + self.flex.set_low(); + } + + /// Set the output level. + #[inline] + pub fn set_level(&mut self, level: Level) { + self.flex.set_level(level); + } + + /// Toggle the output level. + #[inline] + pub fn toggle(&mut self) { + self.flex.toggle(); + } + + /// Is the output pin set as high? + #[inline] + pub fn is_set_high(&self) -> bool { + self.flex.is_high() + } + + /// Is the output pin set as low? + #[inline] + pub fn is_set_low(&self) -> bool { + !self.is_set_high() + } + + /// Expose the inner `Flex` if callers need to reconfigure the pin. + #[inline] + pub fn into_flex(self) -> Flex<'d> { + self.flex + } +} + +/// GPIO input driver that owns a `Flex` pin. +pub struct Input<'d> { + flex: Flex<'d>, +} + +impl<'d> Input<'d> { + /// Create a GPIO input driver for a [GpioPin]. + /// + pub fn new(pin: Peri<'d, impl GpioPin>, pull_select: Pull) -> Self { + let mut flex = Flex::new(pin); + flex.set_as_input(); + flex.set_pull(pull_select); + Self { flex } + } + + /// Get whether the pin input level is high. + #[inline] + pub fn is_high(&self) -> bool { + self.flex.is_high() + } + + /// Get whether the pin input level is low. + #[inline] + pub fn is_low(&self) -> bool { + self.flex.is_low() + } + + /// Expose the inner `Flex` if callers need to reconfigure the pin. + /// + /// Since Drive Strength and Slew Rate are not set when creating the Input + /// pin, they need to be set when converting + #[inline] + pub fn into_flex(mut self, strength: DriveStrength, slew_rate: SlewRate) -> Flex<'d> { + self.flex.set_drive_strength(strength); + self.flex.set_slew_rate(slew_rate); + self.flex + } + + /// Get the pin level. + pub fn get_level(&self) -> Level { + self.flex.get_level() + } +} + +/// Async methods +impl<'d> Input<'d> { + /// Wait until the pin is high. If it is already high, return immediately. + #[inline] + pub fn wait_for_high(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_high() + } + + /// Wait until the pin is low. If it is already low, return immediately. + #[inline] + pub fn wait_for_low(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_low() + } + + /// Wait for the pin to undergo a transition from low to high. + #[inline] + pub fn wait_for_rising_edge(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_rising_edge() + } + + /// Wait for the pin to undergo a transition from high to low. + #[inline] + pub fn wait_for_falling_edge(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_falling_edge() + } + + /// Wait for the pin to undergo any transition, i.e low to high OR high to low. + #[inline] + pub fn wait_for_any_edge(&mut self) -> impl Future + use<'_, 'd> { + self.flex.wait_for_any_edge() + } +} + +impl embedded_hal_async::digital::Wait for Input<'_> { + async fn wait_for_high(&mut self) -> Result<(), Self::Error> { + self.wait_for_high().await; + Ok(()) + } + + async fn wait_for_low(&mut self) -> Result<(), Self::Error> { + self.wait_for_low().await; + Ok(()) + } + + async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_rising_edge().await; + Ok(()) + } + + async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_falling_edge().await; + Ok(()) + } + + async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_any_edge().await; + Ok(()) + } +} + +impl embedded_hal_async::digital::Wait for Flex<'_> { + async fn wait_for_high(&mut self) -> Result<(), Self::Error> { + self.wait_for_high().await; + Ok(()) + } + + async fn wait_for_low(&mut self) -> Result<(), Self::Error> { + self.wait_for_low().await; + Ok(()) + } + + async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_rising_edge().await; + Ok(()) + } + + async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_falling_edge().await; + Ok(()) + } + + async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_any_edge().await; + Ok(()) + } +} + +// Both embedded_hal 0.2 and 1.0 must be supported by embassy HALs. +impl embedded_hal_02::digital::v2::InputPin for Flex<'_> { + // GPIO operations on this block cannot fail, therefor we set the error type + // to Infallible to guarantee that we can only produce Ok variants. + type Error = Infallible; + + #[inline] + fn is_high(&self) -> Result { + Ok(self.is_high()) + } + + #[inline] + fn is_low(&self) -> Result { + Ok(self.is_low()) + } +} + +impl embedded_hal_02::digital::v2::InputPin for Input<'_> { + type Error = Infallible; + + #[inline] + fn is_high(&self) -> Result { + Ok(self.is_high()) + } + + #[inline] + fn is_low(&self) -> Result { + Ok(self.is_low()) + } +} + +impl embedded_hal_02::digital::v2::OutputPin for Flex<'_> { + type Error = Infallible; + + #[inline] + fn set_high(&mut self) -> Result<(), Self::Error> { + self.set_high(); + Ok(()) + } + + #[inline] + fn set_low(&mut self) -> Result<(), Self::Error> { + self.set_low(); + Ok(()) + } +} + +impl embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'_> { + #[inline] + fn is_set_high(&self) -> Result { + Ok(self.is_set_high()) + } + + #[inline] + fn is_set_low(&self) -> Result { + Ok(self.is_set_low()) + } +} + +impl embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'_> { + type Error = Infallible; + + #[inline] + fn toggle(&mut self) -> Result<(), Self::Error> { + self.toggle(); + Ok(()) + } +} + +impl embedded_hal_1::digital::ErrorType for Flex<'_> { + type Error = Infallible; +} + +impl embedded_hal_1::digital::ErrorType for Input<'_> { + type Error = Infallible; +} + +impl embedded_hal_1::digital::ErrorType for Output<'_> { + type Error = Infallible; +} + +impl embedded_hal_1::digital::InputPin for Input<'_> { + #[inline] + fn is_high(&mut self) -> Result { + Ok((*self).is_high()) + } + + #[inline] + fn is_low(&mut self) -> Result { + Ok((*self).is_low()) + } +} + +impl embedded_hal_1::digital::OutputPin for Flex<'_> { + #[inline] + fn set_high(&mut self) -> Result<(), Self::Error> { + self.set_high(); + Ok(()) + } + + #[inline] + fn set_low(&mut self) -> Result<(), Self::Error> { + self.set_low(); + Ok(()) + } +} + +impl embedded_hal_1::digital::StatefulOutputPin for Flex<'_> { + #[inline] + fn is_set_high(&mut self) -> Result { + Ok((*self).is_set_high()) + } + + #[inline] + fn is_set_low(&mut self) -> Result { + Ok((*self).is_set_low()) + } +} diff --git a/embassy-mcxa/src/i2c/controller.rs b/embassy-mcxa/src/i2c/controller.rs new file mode 100644 index 000000000..182a53aea --- /dev/null +++ b/embassy-mcxa/src/i2c/controller.rs @@ -0,0 +1,742 @@ +//! LPI2C controller driver + +use core::future::Future; +use core::marker::PhantomData; + +use embassy_hal_internal::drop::OnDrop; +use embassy_hal_internal::Peri; +use mcxa_pac::lpi2c0::mtdr::Cmd; + +use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin}; +use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig}; +use crate::clocks::{enable_and_reset, PoweredClock}; +use crate::interrupt::typelevel::Interrupt; +use crate::AnyPin; + +/// Bus speed (nominal SCL, no clock stretching) +#[derive(Clone, Copy, Default, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Speed { + #[default] + /// 100 kbit/sec + Standard, + /// 400 kbit/sec + Fast, + /// 1 Mbit/sec + FastPlus, + /// 3.4 Mbit/sec + UltraFast, +} + +impl From for (u8, u8, u8, u8) { + fn from(value: Speed) -> (u8, u8, u8, u8) { + match value { + Speed::Standard => (0x3d, 0x37, 0x3b, 0x1d), + Speed::Fast => (0x0e, 0x0c, 0x0d, 0x06), + Speed::FastPlus => (0x04, 0x03, 0x03, 0x02), + + // UltraFast is "special". Leaving it unimplemented until + // the driver and the clock API is further stabilized. + Speed::UltraFast => todo!(), + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +enum SendStop { + No, + Yes, +} + +/// I2C controller configuration +#[derive(Clone, Copy, Default)] +#[non_exhaustive] +pub struct Config { + /// Bus speed + pub speed: Speed, +} + +/// I2C Controller Driver. +pub struct I2c<'d, T: Instance, M: Mode> { + _peri: Peri<'d, T>, + _scl: Peri<'d, AnyPin>, + _sda: Peri<'d, AnyPin>, + _phantom: PhantomData, + is_hs: bool, +} + +impl<'d, T: Instance> I2c<'d, T, Blocking> { + /// Create a new blocking instance of the I2C Controller bus driver. + pub fn new_blocking( + peri: Peri<'d, T>, + scl: Peri<'d, impl SclPin>, + sda: Peri<'d, impl SdaPin>, + config: Config, + ) -> Result { + Self::new_inner(peri, scl, sda, config) + } +} + +impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { + fn new_inner( + _peri: Peri<'d, T>, + scl: Peri<'d, impl SclPin>, + sda: Peri<'d, impl SdaPin>, + config: Config, + ) -> Result { + let (power, source, div) = Self::clock_config(config.speed); + + // Enable clocks + let conf = Lpi2cConfig { + power, + source, + div, + instance: T::CLOCK_INSTANCE, + }; + + _ = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; + + scl.mux(); + sda.mux(); + + let _scl = scl.into(); + let _sda = sda.into(); + + Self::set_config(&config)?; + + Ok(Self { + _peri, + _scl, + _sda, + _phantom: PhantomData, + is_hs: config.speed == Speed::UltraFast, + }) + } + + fn set_config(config: &Config) -> Result<()> { + // Disable the controller. + critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().disabled())); + + // Soft-reset the controller, read and write FIFOs. + Self::reset_fifos(); + critical_section::with(|_| { + T::regs().mcr().modify(|_, w| w.rst().reset()); + // According to Reference Manual section 40.7.1.4, "There + // is no minimum delay required before clearing the + // software reset", therefore we clear it immediately. + T::regs().mcr().modify(|_, w| w.rst().not_reset()); + + T::regs().mcr().modify(|_, w| w.dozen().clear_bit().dbgen().clear_bit()); + }); + + let (clklo, clkhi, sethold, datavd) = config.speed.into(); + + critical_section::with(|_| { + T::regs().mccr0().modify(|_, w| unsafe { + w.clklo() + .bits(clklo) + .clkhi() + .bits(clkhi) + .sethold() + .bits(sethold) + .datavd() + .bits(datavd) + }) + }); + + // Enable the controller. + critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().enabled())); + + // Clear all flags + T::regs().msr().write(|w| { + w.epf() + .clear_bit_by_one() + .sdf() + .clear_bit_by_one() + .ndf() + .clear_bit_by_one() + .alf() + .clear_bit_by_one() + .fef() + .clear_bit_by_one() + .pltf() + .clear_bit_by_one() + .dmf() + .clear_bit_by_one() + .stf() + .clear_bit_by_one() + }); + + Ok(()) + } + + // REVISIT: turn this into a function of the speed parameter + fn clock_config(speed: Speed) -> (PoweredClock, Lpi2cClockSel, Div4) { + match speed { + Speed::Standard | Speed::Fast | Speed::FastPlus => ( + PoweredClock::NormalEnabledDeepSleepDisabled, + Lpi2cClockSel::FroLfDiv, + const { Div4::no_div() }, + ), + Speed::UltraFast => ( + PoweredClock::NormalEnabledDeepSleepDisabled, + Lpi2cClockSel::FroHfDiv, + const { Div4::no_div() }, + ), + } + } + + /// Resets both TX and RX FIFOs dropping their contents. + fn reset_fifos() { + critical_section::with(|_| { + T::regs().mcr().modify(|_, w| w.rtf().reset().rrf().reset()); + }); + } + + /// Checks whether the TX FIFO is full + fn is_tx_fifo_full() -> bool { + let txfifo_size = 1 << T::regs().param().read().mtxfifo().bits(); + T::regs().mfsr().read().txcount().bits() == txfifo_size + } + + /// Checks whether the TX FIFO is empty + fn is_tx_fifo_empty() -> bool { + T::regs().mfsr().read().txcount() == 0 + } + + /// Checks whether the RX FIFO is empty. + fn is_rx_fifo_empty() -> bool { + T::regs().mfsr().read().rxcount() == 0 + } + + /// Reads and parses the controller status producing an + /// appropriate `Result<(), Error>` variant. + fn status() -> Result<()> { + let msr = T::regs().msr().read(); + T::regs().msr().write(|w| { + w.epf() + .clear_bit_by_one() + .sdf() + .clear_bit_by_one() + .ndf() + .clear_bit_by_one() + .alf() + .clear_bit_by_one() + .fef() + .clear_bit_by_one() + .fef() + .clear_bit_by_one() + .pltf() + .clear_bit_by_one() + .dmf() + .clear_bit_by_one() + .stf() + .clear_bit_by_one() + }); + + if msr.ndf().bit_is_set() { + Err(Error::AddressNack) + } else if msr.alf().bit_is_set() { + Err(Error::ArbitrationLoss) + } else if msr.fef().bit_is_set() { + Err(Error::FifoError) + } else { + Ok(()) + } + } + + /// Inserts the given command into the outgoing FIFO. + /// + /// Caller must ensure there is space in the FIFO for the new + /// command. + fn send_cmd(cmd: Cmd, data: u8) { + #[cfg(feature = "defmt")] + defmt::trace!( + "Sending cmd '{}' ({}) with data '{:08x}' MSR: {:08x}", + cmd, + cmd as u8, + data, + T::regs().msr().read().bits() + ); + + T::regs() + .mtdr() + .write(|w| unsafe { w.data().bits(data) }.cmd().variant(cmd)); + } + + /// Prepares an appropriate Start condition on bus by issuing a + /// `Start` command together with the device address and R/w bit. + /// + /// Blocks waiting for space in the FIFO to become available, then + /// sends the command and blocks waiting for the FIFO to become + /// empty ensuring the command was sent. + fn start(&mut self, address: u8, read: bool) -> Result<()> { + if address >= 0x80 { + return Err(Error::AddressOutOfRange(address)); + } + + // Wait until we have space in the TxFIFO + while Self::is_tx_fifo_full() {} + + let addr_rw = address << 1 | if read { 1 } else { 0 }; + Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); + + // Wait for TxFIFO to be drained + while !Self::is_tx_fifo_empty() {} + + // Check controller status + Self::status() + } + + /// Prepares a Stop condition on the bus. + /// + /// Analogous to `start`, this blocks waiting for space in the + /// FIFO to become available, then sends the command and blocks + /// waiting for the FIFO to become empty ensuring the command was + /// sent. + fn stop() -> Result<()> { + // Wait until we have space in the TxFIFO + while Self::is_tx_fifo_full() {} + + Self::send_cmd(Cmd::Stop, 0); + + // Wait for TxFIFO to be drained + while !Self::is_tx_fifo_empty() {} + + Self::status() + } + + fn blocking_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { + if read.is_empty() { + return Err(Error::InvalidReadBufferLength); + } + + for chunk in read.chunks_mut(256) { + self.start(address, true)?; + + // Wait until we have space in the TxFIFO + while Self::is_tx_fifo_full() {} + + Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); + + for byte in chunk.iter_mut() { + // Wait until there's data in the RxFIFO + while Self::is_rx_fifo_empty() {} + + *byte = T::regs().mrdr().read().data().bits(); + } + } + + if send_stop == SendStop::Yes { + Self::stop()?; + } + + Ok(()) + } + + fn blocking_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> { + self.start(address, false)?; + + // Usually, embassy HALs error out with an empty write, + // however empty writes are useful for writing I2C scanning + // logic through write probing. That is, we send a start with + // R/w bit cleared, but instead of writing any data, just send + // the stop onto the bus. This has the effect of checking if + // the resulting address got an ACK but causing no + // side-effects to the device on the other end. + // + // Because of this, we are not going to error out in case of + // empty writes. + #[cfg(feature = "defmt")] + if write.is_empty() { + defmt::trace!("Empty write, write probing?"); + } + + for byte in write { + // Wait until we have space in the TxFIFO + while Self::is_tx_fifo_full() {} + + Self::send_cmd(Cmd::Transmit, *byte); + } + + if send_stop == SendStop::Yes { + Self::stop()?; + } + + Ok(()) + } + + // Public API: Blocking + + /// Read from address into buffer blocking caller until done. + pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<()> { + self.blocking_read_internal(address, read, SendStop::Yes) + } + + /// Write to address from buffer blocking caller until done. + pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<()> { + self.blocking_write_internal(address, write, SendStop::Yes) + } + + /// Write to address from bytes and read from address into buffer blocking caller until done. + pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> { + self.blocking_write_internal(address, write, SendStop::No)?; + self.blocking_read_internal(address, read, SendStop::Yes) + } +} + +impl<'d, T: Instance> I2c<'d, T, Async> { + /// Create a new async instance of the I2C Controller bus driver. + pub fn new_async( + peri: Peri<'d, T>, + scl: Peri<'d, impl SclPin>, + sda: Peri<'d, impl SdaPin>, + _irq: impl crate::interrupt::typelevel::Binding> + 'd, + config: Config, + ) -> Result { + T::Interrupt::unpend(); + + // Safety: `_irq` ensures an Interrupt Handler exists. + unsafe { T::Interrupt::enable() }; + + Self::new_inner(peri, scl, sda, config) + } + + fn remediation() { + #[cfg(feature = "defmt")] + defmt::trace!("Future dropped, issuing stop",); + + // if the FIFO is not empty, drop its contents. + if !Self::is_tx_fifo_empty() { + Self::reset_fifos(); + } + + // send a stop command + let _ = Self::stop(); + } + + fn enable_rx_ints(&mut self) { + T::regs().mier().write(|w| { + w.rdie() + .enabled() + .ndie() + .enabled() + .alie() + .enabled() + .feie() + .enabled() + .pltie() + .enabled() + }); + } + + fn enable_tx_ints(&mut self) { + T::regs().mier().write(|w| { + w.tdie() + .enabled() + .ndie() + .enabled() + .alie() + .enabled() + .feie() + .enabled() + .pltie() + .enabled() + }); + } + + async fn async_start(&mut self, address: u8, read: bool) -> Result<()> { + if address >= 0x80 { + return Err(Error::AddressOutOfRange(address)); + } + + // send the start command + let addr_rw = address << 1 | if read { 1 } else { 0 }; + Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); + + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // if the command FIFO is empty, we're done sending start + Self::is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::Other)?; + + Self::status() + } + + async fn async_stop(&mut self) -> Result<()> { + // send the stop command + Self::send_cmd(Cmd::Stop, 0); + + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // if the command FIFO is empty, we're done sending stop + Self::is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::Other)?; + + Self::status() + } + + async fn async_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { + if read.is_empty() { + return Err(Error::InvalidReadBufferLength); + } + + // perform corrective action if the future is dropped + let on_drop = OnDrop::new(|| Self::remediation()); + + for chunk in read.chunks_mut(256) { + self.async_start(address, true).await?; + + // send receive command + Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); + + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // if the command FIFO is empty, we're done sending start + Self::is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::Other)?; + + for byte in chunk.iter_mut() { + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_rx_ints(); + // if the rx FIFO is not empty, we need to read a byte + !Self::is_rx_fifo_empty() + }) + .await + .map_err(|_| Error::ReadFail)?; + + *byte = T::regs().mrdr().read().data().bits(); + } + } + + if send_stop == SendStop::Yes { + self.async_stop().await?; + } + + // defuse it if the future is not dropped + on_drop.defuse(); + + Ok(()) + } + + async fn async_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> { + self.async_start(address, false).await?; + + // perform corrective action if the future is dropped + let on_drop = OnDrop::new(|| Self::remediation()); + + // Usually, embassy HALs error out with an empty write, + // however empty writes are useful for writing I2C scanning + // logic through write probing. That is, we send a start with + // R/w bit cleared, but instead of writing any data, just send + // the stop onto the bus. This has the effect of checking if + // the resulting address got an ACK but causing no + // side-effects to the device on the other end. + // + // Because of this, we are not going to error out in case of + // empty writes. + #[cfg(feature = "defmt")] + if write.is_empty() { + defmt::trace!("Empty write, write probing?"); + } + + for byte in write { + T::wait_cell() + .wait_for(|| { + // enable interrupts + self.enable_tx_ints(); + // initiate transmit + Self::send_cmd(Cmd::Transmit, *byte); + // if the tx FIFO is empty, we're done transmiting + Self::is_tx_fifo_empty() + }) + .await + .map_err(|_| Error::WriteFail)?; + } + + if send_stop == SendStop::Yes { + self.async_stop().await?; + } + + // defuse it if the future is not dropped + on_drop.defuse(); + + Ok(()) + } + + // Public API: Async + + /// Read from address into buffer asynchronously. + pub fn async_read<'a>( + &mut self, + address: u8, + read: &'a mut [u8], + ) -> impl Future> + use<'_, 'a, 'd, T> { + self.async_read_internal(address, read, SendStop::Yes) + } + + /// Write to address from buffer asynchronously. + pub fn async_write<'a>( + &mut self, + address: u8, + write: &'a [u8], + ) -> impl Future> + use<'_, 'a, 'd, T> { + self.async_write_internal(address, write, SendStop::Yes) + } + + /// Write to address from bytes and read from address into buffer asynchronously. + pub async fn async_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> { + self.async_write_internal(address, write, SendStop::No).await?; + self.async_read_internal(address, read, SendStop::Yes).await + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> { + type Error = Error; + + fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<()> { + self.blocking_read(address, buffer) + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> { + type Error = Error; + + fn write(&mut self, address: u8, bytes: &[u8]) -> Result<()> { + self.blocking_write(address, bytes) + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> { + type Error = Error; + + fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<()> { + self.blocking_write_read(address, bytes, buffer) + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Transactional for I2c<'d, T, M> { + type Error = Error; + + fn exec(&mut self, address: u8, operations: &mut [embedded_hal_02::blocking::i2c::Operation<'_>]) -> Result<()> { + if let Some((last, rest)) = operations.split_last_mut() { + for op in rest { + match op { + embedded_hal_02::blocking::i2c::Operation::Read(buf) => { + self.blocking_read_internal(address, buf, SendStop::No)? + } + embedded_hal_02::blocking::i2c::Operation::Write(buf) => { + self.blocking_write_internal(address, buf, SendStop::No)? + } + } + } + + match last { + embedded_hal_02::blocking::i2c::Operation::Read(buf) => { + self.blocking_read_internal(address, buf, SendStop::Yes) + } + embedded_hal_02::blocking::i2c::Operation::Write(buf) => { + self.blocking_write_internal(address, buf, SendStop::Yes) + } + } + } else { + Ok(()) + } + } +} + +impl embedded_hal_1::i2c::Error for Error { + fn kind(&self) -> embedded_hal_1::i2c::ErrorKind { + match *self { + Self::ArbitrationLoss => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss, + Self::AddressNack => { + embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address) + } + _ => embedded_hal_1::i2c::ErrorKind::Other, + } + } +} + +impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, T, M> { + type Error = Error; +} + +impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> { + fn transaction(&mut self, address: u8, operations: &mut [embedded_hal_1::i2c::Operation<'_>]) -> Result<()> { + if let Some((last, rest)) = operations.split_last_mut() { + for op in rest { + match op { + embedded_hal_1::i2c::Operation::Read(buf) => { + self.blocking_read_internal(address, buf, SendStop::No)? + } + embedded_hal_1::i2c::Operation::Write(buf) => { + self.blocking_write_internal(address, buf, SendStop::No)? + } + } + } + + match last { + embedded_hal_1::i2c::Operation::Read(buf) => self.blocking_read_internal(address, buf, SendStop::Yes), + embedded_hal_1::i2c::Operation::Write(buf) => self.blocking_write_internal(address, buf, SendStop::Yes), + } + } else { + Ok(()) + } + } +} + +impl<'d, T: Instance> embedded_hal_async::i2c::I2c for I2c<'d, T, Async> { + async fn transaction( + &mut self, + address: u8, + operations: &mut [embedded_hal_async::i2c::Operation<'_>], + ) -> Result<()> { + if let Some((last, rest)) = operations.split_last_mut() { + for op in rest { + match op { + embedded_hal_async::i2c::Operation::Read(buf) => { + self.async_read_internal(address, buf, SendStop::No).await? + } + embedded_hal_async::i2c::Operation::Write(buf) => { + self.async_write_internal(address, buf, SendStop::No).await? + } + } + } + + match last { + embedded_hal_async::i2c::Operation::Read(buf) => { + self.async_read_internal(address, buf, SendStop::Yes).await + } + embedded_hal_async::i2c::Operation::Write(buf) => { + self.async_write_internal(address, buf, SendStop::Yes).await + } + } + } else { + Ok(()) + } + } +} + +impl<'d, T: Instance, M: Mode> embassy_embedded_hal::SetConfig for I2c<'d, T, M> { + type Config = Config; + type ConfigError = Error; + + fn set_config(&mut self, config: &Self::Config) -> Result<()> { + Self::set_config(config) + } +} diff --git a/embassy-mcxa/src/i2c/mod.rs b/embassy-mcxa/src/i2c/mod.rs new file mode 100644 index 000000000..9a014224a --- /dev/null +++ b/embassy-mcxa/src/i2c/mod.rs @@ -0,0 +1,194 @@ +//! I2C Support + +use core::marker::PhantomData; + +use embassy_hal_internal::PeripheralType; +use maitake_sync::WaitCell; +use paste::paste; + +use crate::clocks::periph_helpers::Lpi2cConfig; +use crate::clocks::{ClockError, Gate}; +use crate::gpio::{GpioPin, SealedPin}; +use crate::{interrupt, pac}; + +/// Shorthand for `Result`. +pub type Result = core::result::Result; + +pub mod controller; + +/// Error information type +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + /// Clock configuration error. + ClockSetup(ClockError), + /// FIFO Error + FifoError, + /// Reading for I2C failed. + ReadFail, + /// Writing to I2C failed. + WriteFail, + /// I2C address NAK condition. + AddressNack, + /// Bus level arbitration loss. + ArbitrationLoss, + /// Address out of range. + AddressOutOfRange(u8), + /// Invalid write buffer length. + InvalidWriteBufferLength, + /// Invalid read buffer length. + InvalidReadBufferLength, + /// Other internal errors or unexpected state. + Other, +} + +/// I2C interrupt handler. +pub struct InterruptHandler { + _phantom: PhantomData, +} + +impl interrupt::typelevel::Handler for InterruptHandler { + unsafe fn on_interrupt() { + if T::regs().mier().read().bits() != 0 { + T::regs().mier().write(|w| { + w.tdie() + .disabled() + .rdie() + .disabled() + .epie() + .disabled() + .sdie() + .disabled() + .ndie() + .disabled() + .alie() + .disabled() + .feie() + .disabled() + .pltie() + .disabled() + .dmie() + .disabled() + .stie() + .disabled() + }); + + T::wait_cell().wake(); + } + } +} + +mod sealed { + /// Seal a trait + pub trait Sealed {} +} + +impl sealed::Sealed for T {} + +trait SealedInstance { + fn regs() -> &'static pac::lpi2c0::RegisterBlock; + fn wait_cell() -> &'static WaitCell; +} + +/// I2C Instance +#[allow(private_bounds)] +pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate { + /// Interrupt for this I2C instance. + type Interrupt: interrupt::typelevel::Interrupt; + /// Clock instance + const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance; +} + +macro_rules! impl_instance { + ($($n:expr),*) => { + $( + paste!{ + impl SealedInstance for crate::peripherals::[] { + fn regs() -> &'static pac::lpi2c0::RegisterBlock { + unsafe { &*pac::[]::ptr() } + } + + fn wait_cell() -> &'static WaitCell { + static WAIT_CELL: WaitCell = WaitCell::new(); + &WAIT_CELL + } + } + + impl Instance for crate::peripherals::[] { + type Interrupt = crate::interrupt::typelevel::[]; + const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance + = crate::clocks::periph_helpers::Lpi2cInstance::[]; + } + } + )* + }; +} + +impl_instance!(0, 1, 2, 3); + +/// SCL pin trait. +pub trait SclPin: GpioPin + sealed::Sealed + PeripheralType { + fn mux(&self); +} + +/// SDA pin trait. +pub trait SdaPin: GpioPin + sealed::Sealed + PeripheralType { + fn mux(&self); +} + +/// Driver mode. +#[allow(private_bounds)] +pub trait Mode: sealed::Sealed {} + +/// Blocking mode. +pub struct Blocking; +impl sealed::Sealed for Blocking {} +impl Mode for Blocking {} + +/// Async mode. +pub struct Async; +impl sealed::Sealed for Async {} +impl Mode for Async {} + +macro_rules! impl_pin { + ($pin:ident, $peri:ident, $fn:ident, $trait:ident) => { + impl $trait for crate::peripherals::$pin { + fn mux(&self) { + self.set_pull(crate::gpio::Pull::Disabled); + self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); + self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); + self.set_function(crate::pac::port0::pcr0::Mux::$fn); + self.set_enable_input_buffer(); + } + } + }; +} + +impl_pin!(P0_16, LPI2C0, Mux2, SdaPin); +impl_pin!(P0_17, LPI2C0, Mux2, SclPin); +impl_pin!(P0_18, LPI2C0, Mux2, SclPin); +impl_pin!(P0_19, LPI2C0, Mux2, SdaPin); +impl_pin!(P1_0, LPI2C1, Mux3, SdaPin); +impl_pin!(P1_1, LPI2C1, Mux3, SclPin); +impl_pin!(P1_2, LPI2C1, Mux3, SdaPin); +impl_pin!(P1_3, LPI2C1, Mux3, SclPin); +impl_pin!(P1_8, LPI2C2, Mux3, SdaPin); +impl_pin!(P1_9, LPI2C2, Mux3, SclPin); +impl_pin!(P1_10, LPI2C2, Mux3, SdaPin); +impl_pin!(P1_11, LPI2C2, Mux3, SclPin); +impl_pin!(P1_12, LPI2C1, Mux2, SdaPin); +impl_pin!(P1_13, LPI2C1, Mux2, SclPin); +impl_pin!(P1_14, LPI2C1, Mux2, SclPin); +impl_pin!(P1_15, LPI2C1, Mux2, SdaPin); +impl_pin!(P1_30, LPI2C0, Mux3, SdaPin); +impl_pin!(P1_31, LPI2C0, Mux3, SclPin); +impl_pin!(P3_27, LPI2C3, Mux2, SclPin); +impl_pin!(P3_28, LPI2C3, Mux2, SdaPin); +// impl_pin!(P3_29, LPI2C3, Mux2, HreqPin); What is this HREQ pin? +impl_pin!(P3_30, LPI2C3, Mux2, SclPin); +impl_pin!(P3_31, LPI2C3, Mux2, SdaPin); +impl_pin!(P4_2, LPI2C2, Mux2, SdaPin); +impl_pin!(P4_3, LPI2C0, Mux2, SclPin); +impl_pin!(P4_4, LPI2C2, Mux2, SdaPin); +impl_pin!(P4_5, LPI2C0, Mux2, SclPin); +// impl_pin!(P4_6, LPI2C0, Mux2, HreqPin); What is this HREQ pin? diff --git a/embassy-mcxa/src/interrupt.rs b/embassy-mcxa/src/interrupt.rs new file mode 100644 index 000000000..1d10e3b2d --- /dev/null +++ b/embassy-mcxa/src/interrupt.rs @@ -0,0 +1,563 @@ +//! Minimal interrupt helpers mirroring embassy-imxrt style for OS_EVENT and LPUART2. +//! Type-level interrupt traits and bindings are provided by the +//! `embassy_hal_internal::interrupt_mod!` macro via the generated module below. + +// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs +// are complete prior to release. +#![allow(clippy::missing_safety_doc)] + +mod generated { + #[rustfmt::skip] + embassy_hal_internal::interrupt_mod!( + ADC1, + GPIO0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + LPI2C0, + LPI2C1, + LPI2C2, + LPI2C3, + LPUART0, + LPUART1, + LPUART2, + LPUART3, + LPUART4, + LPUART5, + OS_EVENT, + RTC, + ); +} + +use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; + +pub use generated::interrupt::{typelevel, Priority}; + +use crate::pac::Interrupt; + +/// Trait for configuring and controlling interrupts. +/// +/// This trait provides a consistent interface for interrupt management across +/// different interrupt sources, similar to embassy-imxrt's InterruptExt. +pub trait InterruptExt { + /// Clear any pending interrupt in NVIC. + fn unpend(&self); + + /// Set NVIC priority for this interrupt. + fn set_priority(&self, priority: Priority); + + /// Enable this interrupt in NVIC. + /// + /// # Safety + /// This function is unsafe because it can enable interrupts that may not be + /// properly configured, potentially leading to undefined behavior. + unsafe fn enable(&self); + + /// Disable this interrupt in NVIC. + /// + /// # Safety + /// This function is unsafe because disabling interrupts may leave the system + /// in an inconsistent state if the interrupt was expected to fire. + unsafe fn disable(&self); + + /// Check if the interrupt is pending in NVIC. + fn is_pending(&self) -> bool; +} + +#[derive(Clone, Copy, Debug, Default)] +pub struct DefaultHandlerSnapshot { + pub vector: u16, + pub count: u32, + pub cfsr: u32, + pub hfsr: u32, + pub stacked_pc: u32, + pub stacked_lr: u32, + pub stacked_sp: u32, +} + +static LAST_DEFAULT_VECTOR: AtomicU16 = AtomicU16::new(0); +static LAST_DEFAULT_COUNT: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_CFSR: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_HFSR: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_PC: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_LR: AtomicU32 = AtomicU32::new(0); +static LAST_DEFAULT_SP: AtomicU32 = AtomicU32::new(0); + +#[inline] +pub fn default_handler_snapshot() -> DefaultHandlerSnapshot { + DefaultHandlerSnapshot { + vector: LAST_DEFAULT_VECTOR.load(Ordering::Relaxed), + count: LAST_DEFAULT_COUNT.load(Ordering::Relaxed), + cfsr: LAST_DEFAULT_CFSR.load(Ordering::Relaxed), + hfsr: LAST_DEFAULT_HFSR.load(Ordering::Relaxed), + stacked_pc: LAST_DEFAULT_PC.load(Ordering::Relaxed), + stacked_lr: LAST_DEFAULT_LR.load(Ordering::Relaxed), + stacked_sp: LAST_DEFAULT_SP.load(Ordering::Relaxed), + } +} + +#[inline] +pub fn clear_default_handler_snapshot() { + LAST_DEFAULT_VECTOR.store(0, Ordering::Relaxed); + LAST_DEFAULT_COUNT.store(0, Ordering::Relaxed); + LAST_DEFAULT_CFSR.store(0, Ordering::Relaxed); + LAST_DEFAULT_HFSR.store(0, Ordering::Relaxed); + LAST_DEFAULT_PC.store(0, Ordering::Relaxed); + LAST_DEFAULT_LR.store(0, Ordering::Relaxed); + LAST_DEFAULT_SP.store(0, Ordering::Relaxed); +} + +/// OS_EVENT interrupt helper with methods similar to embassy-imxrt's InterruptExt. +pub struct OsEvent; +pub const OS_EVENT: OsEvent = OsEvent; + +impl InterruptExt for OsEvent { + /// Clear any pending OS_EVENT in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::OS_EVENT); + } + + /// Set NVIC priority for OS_EVENT. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::OS_EVENT, u8::from(priority)); + } + } + + /// Enable OS_EVENT in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::OS_EVENT); + } + + /// Disable OS_EVENT in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::OS_EVENT); + } + + /// Check if OS_EVENT is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::OS_EVENT) + } +} + +impl OsEvent { + /// Configure OS_EVENT interrupt for timer operation. + /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled. + /// Also performs a software event to wake any pending WFE. + pub fn configure_for_timer(&self, priority: Priority) { + // Configure NVIC + self.unpend(); + self.set_priority(priority); + unsafe { + self.enable(); + } + + // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run) + // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not. + unsafe { + cortex_m::interrupt::enable(); + } + + // Wake any executor WFE that might be sleeping when we armed the first deadline + cortex_m::asm::sev(); + } +} + +/// LPUART2 interrupt helper with methods similar to embassy-imxrt's InterruptExt. +pub struct Lpuart2; +pub const LPUART2: Lpuart2 = Lpuart2; + +impl InterruptExt for Lpuart2 { + /// Clear any pending LPUART2 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::LPUART2); + } + + /// Set NVIC priority for LPUART2. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::LPUART2, u8::from(priority)); + } + } + + /// Enable LPUART2 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::LPUART2); + } + + /// Disable LPUART2 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::LPUART2); + } + + /// Check if LPUART2 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::LPUART2) + } +} + +impl Lpuart2 { + /// Configure LPUART2 interrupt for UART operation. + /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled. + pub fn configure_for_uart(&self, priority: Priority) { + // Configure NVIC + self.unpend(); + self.set_priority(priority); + unsafe { + self.enable(); + } + + // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run) + // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not. + unsafe { + cortex_m::interrupt::enable(); + } + } + + /// Install LPUART2 handler into the RAM vector table. + /// Safety: See `install_irq_handler`. + pub unsafe fn install_handler(&self, handler: unsafe extern "C" fn()) { + install_irq_handler(Interrupt::LPUART2, handler); + } +} + +pub struct Rtc; +pub const RTC: Rtc = Rtc; + +impl InterruptExt for Rtc { + /// Clear any pending RTC in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::RTC); + } + + /// Set NVIC priority for RTC. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::RTC, u8::from(priority)); + } + } + + /// Enable RTC in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::RTC); + } + + /// Disable RTC in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::RTC); + } + + /// Check if RTC is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC) + } +} + +pub struct Adc; +pub const ADC1: Adc = Adc; + +impl InterruptExt for Adc { + /// Clear any pending ADC1 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::ADC1); + } + + /// Set NVIC priority for ADC1. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::ADC1, u8::from(priority)); + } + } + + /// Enable ADC1 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::ADC1); + } + + /// Disable ADC1 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::ADC1); + } + + /// Check if ADC1 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC1) + } +} + +pub struct Gpio0; +pub const GPIO0: Gpio0 = Gpio0; + +impl InterruptExt for Gpio0 { + /// Clear any pending GPIO0 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO0); + } + + /// Set NVIC priority for GPIO0. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO0, u8::from(priority)); + } + } + + /// Enable GPIO0 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO0); + } + + /// Disable GPIO0 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO0); + } + + /// Check if GPIO0 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO0) + } +} + +pub struct Gpio1; +pub const GPIO1: Gpio1 = Gpio1; + +impl InterruptExt for Gpio1 { + /// Clear any pending GPIO1 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO1); + } + + /// Set NVIC priority for GPIO1. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO1, u8::from(priority)); + } + } + + /// Enable GPIO1 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO1); + } + + /// Disable GPIO1 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO1); + } + + /// Check if GPIO1 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO1) + } +} + +pub struct Gpio2; +pub const GPIO2: Gpio2 = Gpio2; + +impl InterruptExt for Gpio2 { + /// Clear any pending GPIO2 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO2); + } + + /// Set NVIC priority for GPIO2. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO2, u8::from(priority)); + } + } + + /// Enable GPIO2 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO2); + } + + /// Disable GPIO2 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO2); + } + + /// Check if GPIO2 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO2) + } +} + +pub struct Gpio3; +pub const GPIO3: Gpio3 = Gpio3; + +impl InterruptExt for Gpio3 { + /// Clear any pending GPIO3 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO3); + } + + /// Set NVIC priority for GPIO3. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO3, u8::from(priority)); + } + } + + /// Enable GPIO3 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO3); + } + + /// Disable GPIO3 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO3); + } + + /// Check if GPIO3 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO3) + } +} + +pub struct Gpio4; +pub const GPIO4: Gpio4 = Gpio4; + +impl InterruptExt for Gpio4 { + /// Clear any pending GPIO4 in NVIC. + #[inline] + fn unpend(&self) { + cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO4); + } + + /// Set NVIC priority for GPIO4. + #[inline] + fn set_priority(&self, priority: Priority) { + unsafe { + let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; + nvic.set_priority(Interrupt::GPIO4, u8::from(priority)); + } + } + + /// Enable GPIO4 in NVIC. + #[inline] + unsafe fn enable(&self) { + cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO4); + } + + /// Disable GPIO4 in NVIC. + #[inline] + unsafe fn disable(&self) { + cortex_m::peripheral::NVIC::mask(Interrupt::GPIO4); + } + + /// Check if GPIO4 is pending in NVIC. + #[inline] + fn is_pending(&self) -> bool { + cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO4) + } +} + +/// Set VTOR (Vector Table Offset) to a RAM-based vector table. +/// Pass a pointer to the first word in the RAM table (stack pointer slot 0). +/// Safety: Caller must ensure the RAM table is valid and aligned as required by the core. +pub unsafe fn vtor_set_ram_vector_base(base: *const u32) { + core::ptr::write_volatile(0xE000_ED08 as *mut u32, base as u32); +} + +/// Install an interrupt handler into the current VTOR-based vector table. +/// This writes the function pointer at index 16 + irq number. +/// Safety: Caller must ensure VTOR points at a writable RAM table and that `handler` +/// has the correct ABI and lifetime. +pub unsafe fn install_irq_handler(irq: Interrupt, handler: unsafe extern "C" fn()) { + let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32; + let idx = 16 + (irq as isize as usize); + core::ptr::write_volatile(vtor_base.add(idx), handler as usize as u32); +} + +impl OsEvent { + /// Convenience to install the OS_EVENT handler into the RAM vector table. + /// Safety: See `install_irq_handler`. + pub unsafe fn install_handler(&self, handler: extern "C" fn()) { + install_irq_handler(Interrupt::OS_EVENT, handler); + } +} + +/// Install OS_EVENT handler by raw address. Useful to avoid fn pointer type mismatches. +/// Safety: Caller must ensure the address is a valid `extern "C" fn()` handler. +pub unsafe fn os_event_install_handler_raw(handler_addr: usize) { + let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32; + let idx = 16 + (Interrupt::OS_EVENT as isize as usize); + core::ptr::write_volatile(vtor_base.add(idx), handler_addr as u32); +} + +/// Provide a conservative default IRQ handler that avoids wedging the system. +/// It clears all NVIC pending bits and returns, so spurious or reserved IRQs +/// don’t trap the core in an infinite WFI loop during bring-up. +#[no_mangle] +pub unsafe extern "C" fn DefaultHandler() { + let active = core::ptr::read_volatile(0xE000_ED04 as *const u32) & 0x1FF; + let cfsr = core::ptr::read_volatile(0xE000_ED28 as *const u32); + let hfsr = core::ptr::read_volatile(0xE000_ED2C as *const u32); + + let sp = cortex_m::register::msp::read(); + let stacked = sp as *const u32; + // Stacked registers follow ARMv8-M procedure call standard order + let stacked_pc = unsafe { stacked.add(6).read() }; + let stacked_lr = unsafe { stacked.add(5).read() }; + + LAST_DEFAULT_VECTOR.store(active as u16, Ordering::Relaxed); + LAST_DEFAULT_CFSR.store(cfsr, Ordering::Relaxed); + LAST_DEFAULT_HFSR.store(hfsr, Ordering::Relaxed); + LAST_DEFAULT_COUNT.fetch_add(1, Ordering::Relaxed); + LAST_DEFAULT_PC.store(stacked_pc, Ordering::Relaxed); + LAST_DEFAULT_LR.store(stacked_lr, Ordering::Relaxed); + LAST_DEFAULT_SP.store(sp, Ordering::Relaxed); + + // Do nothing here: on some MCUs/TrustZone setups, writing NVIC from a spurious + // handler can fault if targeting the Secure bank. Just return. + cortex_m::asm::dsb(); + cortex_m::asm::isb(); +} diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs new file mode 100644 index 000000000..c6d8adc8f --- /dev/null +++ b/embassy-mcxa/src/lib.rs @@ -0,0 +1,471 @@ +#![no_std] +#![allow(async_fn_in_trait)] +#![doc = include_str!("../README.md")] + +// //! ## Feature flags +// #![doc = document_features::document_features!(feature_label = r#"{feature}"#)] + +pub mod clocks; // still provide clock helpers +pub mod gpio; +pub mod pins; // pin mux helpers + +pub mod adc; +pub mod clkout; +pub mod config; +pub mod i2c; +pub mod interrupt; +pub mod lpuart; +pub mod ostimer; +pub mod rtc; + +pub use crate::pac::NVIC_PRIO_BITS; + +#[rustfmt::skip] +embassy_hal_internal::peripherals!( + ADC0, + ADC1, + + AOI0, + AOI1, + + CAN0, + CAN1, + + CDOG0, + CDOG1, + + // CLKOUT is not specifically a peripheral (it's part of SYSCON), + // but we still want it to be a singleton. + CLKOUT, + + CMC, + CMP0, + CMP1, + CRC0, + + CTIMER0, + CTIMER1, + CTIMER2, + CTIMER3, + CTIMER4, + + DBGMAILBOX, + DMA0, + EDMA0_TCD0, + EIM0, + EQDC0, + EQDC1, + ERM0, + FLEXIO0, + FLEXPWM0, + FLEXPWM1, + FMC0, + FMU0, + FREQME0, + GLIKEY0, + + GPIO0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + + I3C0, + INPUTMUX0, + + LPI2C0, + LPI2C1, + LPI2C2, + LPI2C3, + + LPSPI0, + LPSPI1, + + LPTMR0, + + LPUART0, + LPUART1, + LPUART2, + LPUART3, + LPUART4, + LPUART5, + + MAU0, + MBC0, + MRCC0, + OPAMP0, + + #[cfg(not(feature = "time"))] + OSTIMER0, + + P0_0, + P0_1, + P0_2, + P0_3, + P0_4, + P0_5, + P0_6, + P0_7, + P0_8, + P0_9, + P0_10, + P0_11, + P0_12, + P0_13, + P0_14, + P0_15, + P0_16, + P0_17, + P0_18, + P0_19, + P0_20, + P0_21, + P0_22, + P0_23, + P0_24, + P0_25, + P0_26, + P0_27, + P0_28, + P0_29, + P0_30, + P0_31, + + P1_0, + P1_1, + P1_2, + P1_3, + P1_4, + P1_5, + P1_6, + P1_7, + P1_8, + P1_9, + P1_10, + P1_11, + P1_12, + P1_13, + P1_14, + P1_15, + P1_16, + P1_17, + P1_18, + P1_19, + P1_20, + P1_21, + P1_22, + P1_23, + P1_24, + P1_25, + P1_26, + P1_27, + P1_28, + P1_29, + P1_30, + P1_31, + + P2_0, + P2_1, + P2_2, + P2_3, + P2_4, + P2_5, + P2_6, + P2_7, + P2_8, + P2_9, + P2_10, + P2_11, + P2_12, + P2_13, + P2_14, + P2_15, + P2_16, + P2_17, + P2_18, + P2_19, + P2_20, + P2_21, + P2_22, + P2_23, + P2_24, + P2_25, + P2_26, + P2_27, + P2_28, + P2_29, + P2_30, + P2_31, + + P3_0, + P3_1, + P3_2, + P3_3, + P3_4, + P3_5, + P3_6, + P3_7, + P3_8, + P3_9, + P3_10, + P3_11, + P3_12, + P3_13, + P3_14, + P3_15, + P3_16, + P3_17, + P3_18, + P3_19, + P3_20, + P3_21, + P3_22, + P3_23, + P3_24, + P3_25, + P3_26, + P3_27, + P3_28, + P3_29, + P3_30, + P3_31, + + P4_0, + P4_1, + P4_2, + P4_3, + P4_4, + P4_5, + P4_6, + P4_7, + P4_8, + P4_9, + P4_10, + P4_11, + P4_12, + P4_13, + P4_14, + P4_15, + P4_16, + P4_17, + P4_18, + P4_19, + P4_20, + P4_21, + P4_22, + P4_23, + P4_24, + P4_25, + P4_26, + P4_27, + P4_28, + P4_29, + P4_30, + P4_31, + + P5_0, + P5_1, + P5_2, + P5_3, + P5_4, + P5_5, + P5_6, + P5_7, + P5_8, + P5_9, + P5_10, + P5_11, + P5_12, + P5_13, + P5_14, + P5_15, + P5_16, + P5_17, + P5_18, + P5_19, + P5_20, + P5_21, + P5_22, + P5_23, + P5_24, + P5_25, + P5_26, + P5_27, + P5_28, + P5_29, + P5_30, + P5_31, + + PKC0, + + PORT0, + PORT1, + PORT2, + PORT3, + PORT4, + + RTC0, + SAU, + SCG0, + SCN_SCB, + SGI0, + SMARTDMA0, + SPC0, + SYSCON, + TDET0, + TRNG0, + UDF0, + USB0, + UTICK0, + VBAT0, + WAKETIMER0, + WUU0, + WWDT0, +); + +// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. + +// Re-export interrupt traits and types +pub use adc::Adc1 as Adc1Token; +pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output}; +pub use interrupt::InterruptExt; +#[cfg(feature = "unstable-pac")] +pub use mcxa_pac as pac; +#[cfg(not(feature = "unstable-pac"))] +pub(crate) use mcxa_pac as pac; + +/// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. +/// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). +pub fn init(cfg: crate::config::Config) -> Peripherals { + let peripherals = Peripherals::take(); + // Apply user-configured priority early; enabling is left to examples/apps + #[cfg(feature = "time")] + crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO0.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO1.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO2.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO3.set_priority(cfg.gpio_interrupt_priority); + // Apply user-configured priority early; enabling is left to examples/apps + crate::interrupt::GPIO4.set_priority(cfg.gpio_interrupt_priority); + + // Configure clocks + crate::clocks::init(cfg.clock_cfg).unwrap(); + + unsafe { + crate::gpio::init(); + } + + // Initialize embassy-time global driver backed by OSTIMER0 + #[cfg(feature = "time")] + crate::ostimer::time_driver::init(crate::config::Config::default().time_interrupt_priority, 1_000_000); + + // Enable GPIO clocks + unsafe { + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); + } + + peripherals +} + +// /// Optional hook called by cortex-m-rt before RAM init. +// /// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state +// /// left by soft resets/debug sessions. +// /// +// /// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor' +// /// feature is incompatible with our setup because it expects __vector_table to be +// /// defined differently than how our RAM-based linker script arranges it. +// #[no_mangle] +// pub unsafe extern "C" fn __pre_init() { +// // Set the VTOR to point to the interrupt vector table in RAM +// // This is required since code runs from RAM on this MCU +// crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32); + +// // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs. +// let nvic = &*cortex_m::peripheral::NVIC::PTR; +// for i in 0..4 { +// // 4 words x 32 = 128 IRQs +// nvic.icer[i].write(0xFFFF_FFFF); +// nvic.icpr[i].write(0xFFFF_FFFF); +// } +// // Do NOT touch peripheral registers here: clocks may be off and accesses can fault. +// crate::interrupt::clear_default_handler_snapshot(); +// } + +/// Internal helper to dispatch a type-level interrupt handler. +#[inline(always)] +#[doc(hidden)] +pub unsafe fn __handle_interrupt() +where + T: crate::interrupt::typelevel::Interrupt, + H: crate::interrupt::typelevel::Handler, +{ + H::on_interrupt(); +} + +/// Macro to bind interrupts to handlers, similar to embassy-imxrt. +/// +/// Example: +/// - Bind OS_EVENT to the OSTIMER time-driver handler +/// bind_interrupts!(struct Irqs { OS_EVENT => crate::ostimer::time_driver::OsEventHandler; }); +#[macro_export] +macro_rules! bind_interrupts { + ($(#[$attr:meta])* $vis:vis struct $name:ident { + $( + $(#[cfg($cond_irq:meta)])? + $irq:ident => $( + $(#[cfg($cond_handler:meta)])? + $handler:ty + ),*; + )* + }) => { + #[derive(Copy, Clone)] + $(#[$attr])* + $vis struct $name; + + $( + #[allow(non_snake_case)] + #[no_mangle] + $(#[cfg($cond_irq)])? + unsafe extern "C" fn $irq() { + unsafe { + $( + $(#[cfg($cond_handler)])? + <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt(); + )* + } + } + + $(#[cfg($cond_irq)])? + $crate::bind_interrupts!(@inner + $( + $(#[cfg($cond_handler)])? + unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {} + )* + ); + )* + }; + (@inner $($t:tt)*) => { + $($t)* + } +} diff --git a/embassy-mcxa/src/lpuart/buffered.rs b/embassy-mcxa/src/lpuart/buffered.rs new file mode 100644 index 000000000..8eb443ca7 --- /dev/null +++ b/embassy-mcxa/src/lpuart/buffered.rs @@ -0,0 +1,780 @@ +use core::future::poll_fn; +use core::marker::PhantomData; +use core::sync::atomic::{AtomicBool, Ordering}; +use core::task::Poll; + +use embassy_hal_internal::atomic_ring_buffer::RingBuffer; +use embassy_hal_internal::Peri; +use embassy_sync::waitqueue::AtomicWaker; + +use super::*; +use crate::interrupt; + +// ============================================================================ +// STATIC STATE MANAGEMENT +// ============================================================================ + +/// State for buffered LPUART operations +pub struct State { + tx_waker: AtomicWaker, + tx_buf: RingBuffer, + tx_done: AtomicBool, + rx_waker: AtomicWaker, + rx_buf: RingBuffer, + initialized: AtomicBool, +} + +impl Default for State { + fn default() -> Self { + Self::new() + } +} + +impl State { + /// Create a new state instance + pub const fn new() -> Self { + Self { + tx_waker: AtomicWaker::new(), + tx_buf: RingBuffer::new(), + tx_done: AtomicBool::new(true), + rx_waker: AtomicWaker::new(), + rx_buf: RingBuffer::new(), + initialized: AtomicBool::new(false), + } + } +} +// ============================================================================ +// BUFFERED DRIVER STRUCTURES +// ============================================================================ + +/// Buffered LPUART driver +pub struct BufferedLpuart<'a> { + tx: BufferedLpuartTx<'a>, + rx: BufferedLpuartRx<'a>, +} + +/// Buffered LPUART TX driver +pub struct BufferedLpuartTx<'a> { + info: Info, + state: &'static State, + _tx_pin: Peri<'a, AnyPin>, + _cts_pin: Option>, +} + +/// Buffered LPUART RX driver +pub struct BufferedLpuartRx<'a> { + info: Info, + state: &'static State, + _rx_pin: Peri<'a, AnyPin>, + _rts_pin: Option>, +} + +// ============================================================================ +// BUFFERED LPUART IMPLEMENTATION +// ============================================================================ + +impl<'a> BufferedLpuart<'a> { + /// Common initialization logic + fn init_common( + _inner: &Peri<'a, T>, + tx_buffer: Option<&'a mut [u8]>, + rx_buffer: Option<&'a mut [u8]>, + config: &Config, + enable_tx: bool, + enable_rx: bool, + enable_rts: bool, + enable_cts: bool, + ) -> Result<&'static State> { + let state = T::buffered_state(); + + if state.initialized.load(Ordering::Relaxed) { + return Err(Error::InvalidArgument); + } + + // Initialize buffers + if let Some(tx_buffer) = tx_buffer { + if tx_buffer.is_empty() { + return Err(Error::InvalidArgument); + } + unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), tx_buffer.len()) }; + } + + if let Some(rx_buffer) = rx_buffer { + if rx_buffer.is_empty() { + return Err(Error::InvalidArgument); + } + unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_buffer.len()) }; + } + + state.initialized.store(true, Ordering::Relaxed); + + // Enable clocks and initialize hardware + let conf = LpuartConfig { + power: config.power, + source: config.source, + div: config.div, + instance: T::CLOCK_INSTANCE, + }; + let clock_freq = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; + + Self::init_hardware( + T::info().regs, + *config, + clock_freq, + enable_tx, + enable_rx, + enable_rts, + enable_cts, + )?; + + Ok(state) + } + + /// Helper for full-duplex initialization + fn new_inner( + inner: Peri<'a, T>, + tx_pin: Peri<'a, AnyPin>, + rx_pin: Peri<'a, AnyPin>, + rts_pin: Option>, + cts_pin: Option>, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result<(BufferedLpuartTx<'a>, BufferedLpuartRx<'a>)> { + let state = Self::init_common::( + &inner, + Some(tx_buffer), + Some(rx_buffer), + &config, + true, + true, + rts_pin.is_some(), + cts_pin.is_some(), + )?; + + let tx = BufferedLpuartTx { + info: T::info(), + state, + _tx_pin: tx_pin, + _cts_pin: cts_pin, + }; + + let rx = BufferedLpuartRx { + info: T::info(), + state, + _rx_pin: rx_pin, + _rts_pin: rts_pin, + }; + + Ok((tx, rx)) + } + + /// Common hardware initialization logic + fn init_hardware( + regs: &'static mcxa_pac::lpuart0::RegisterBlock, + config: Config, + clock_freq: u32, + enable_tx: bool, + enable_rx: bool, + enable_rts: bool, + enable_cts: bool, + ) -> Result<()> { + // Perform standard initialization + perform_software_reset(regs); + disable_transceiver(regs); + configure_baudrate(regs, config.baudrate_bps, clock_freq)?; + configure_frame_format(regs, &config); + configure_control_settings(regs, &config); + configure_fifo(regs, &config); + clear_all_status_flags(regs); + configure_flow_control(regs, enable_rts, enable_cts, &config); + configure_bit_order(regs, config.msb_first); + + // Enable interrupts for buffered operation + cortex_m::interrupt::free(|_| { + regs.ctrl().modify(|_, w| { + w.rie() + .enabled() // RX interrupt + .orie() + .enabled() // Overrun interrupt + .peie() + .enabled() // Parity error interrupt + .feie() + .enabled() // Framing error interrupt + .neie() + .enabled() // Noise error interrupt + }); + }); + + // Enable the transceiver + enable_transceiver(regs, enable_rx, enable_tx); + + Ok(()) + } + + /// Create a new full duplex buffered LPUART + pub fn new( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + None, + None, + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + + /// Create a new buffered LPUART instance with RTS/CTS flow control + pub fn new_with_rtscts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + cts_pin: Peri<'a, impl CtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + rts_pin.as_rts(); + cts_pin.as_cts(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + Some(rts_pin.into()), + Some(cts_pin.into()), + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + + /// Create a new buffered LPUART with only RTS flow control (RX flow control) + pub fn new_with_rts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + rts_pin.as_rts(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + Some(rts_pin.into()), + None, + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + + /// Create a new buffered LPUART with only CTS flow control (TX flow control) + pub fn new_with_cts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + cts_pin: Peri<'a, impl CtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + rx_pin.as_rx(); + cts_pin.as_cts(); + + let (tx, rx) = Self::new_inner::( + inner, + tx_pin.into(), + rx_pin.into(), + None, + Some(cts_pin.into()), + tx_buffer, + rx_buffer, + config, + )?; + + Ok(Self { tx, rx }) + } + + /// Split the buffered LPUART into separate TX and RX parts + pub fn split(self) -> (BufferedLpuartTx<'a>, BufferedLpuartRx<'a>) { + (self.tx, self.rx) + } + + /// Get mutable references to TX and RX parts + pub fn split_ref(&mut self) -> (&mut BufferedLpuartTx<'a>, &mut BufferedLpuartRx<'a>) { + (&mut self.tx, &mut self.rx) + } +} + +// ============================================================================ +// BUFFERED TX IMPLEMENTATION +// ============================================================================ + +impl<'a> BufferedLpuartTx<'a> { + /// Helper for TX-only initialization + fn new_inner( + inner: Peri<'a, T>, + tx_pin: Peri<'a, AnyPin>, + cts_pin: Option>, + tx_buffer: &'a mut [u8], + config: Config, + ) -> Result> { + let state = BufferedLpuart::init_common::( + &inner, + Some(tx_buffer), + None, + &config, + true, + false, + false, + cts_pin.is_some(), + )?; + + Ok(BufferedLpuartTx { + info: T::info(), + state, + _tx_pin: tx_pin, + _cts_pin: cts_pin, + }) + } + + pub fn new( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + + Self::new_inner::(inner, tx_pin.into(), None, tx_buffer, config) + } + + /// Create a new TX-only buffered LPUART with CTS flow control + pub fn new_with_cts( + inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + cts_pin: Peri<'a, impl CtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + tx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + tx_pin.as_tx(); + cts_pin.as_cts(); + + Self::new_inner::(inner, tx_pin.into(), Some(cts_pin.into()), tx_buffer, config) + } +} + +impl<'a> BufferedLpuartTx<'a> { + /// Write data asynchronously + pub async fn write(&mut self, buf: &[u8]) -> Result { + let mut written = 0; + + for &byte in buf { + // Wait for space in the buffer + poll_fn(|cx| { + self.state.tx_waker.register(cx.waker()); + + let mut writer = unsafe { self.state.tx_buf.writer() }; + if writer.push_one(byte) { + // Enable TX interrupt to start transmission + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); + }); + Poll::Ready(Ok(())) + } else { + Poll::Pending + } + }) + .await?; + + written += 1; + } + + Ok(written) + } + + /// Flush the TX buffer and wait for transmission to complete + pub async fn flush(&mut self) -> Result<()> { + // Wait for TX buffer to empty and transmission to complete + poll_fn(|cx| { + self.state.tx_waker.register(cx.waker()); + + let tx_empty = self.state.tx_buf.is_empty(); + let fifo_empty = self.info.regs.water().read().txcount().bits() == 0; + let tc_complete = self.info.regs.stat().read().tc().is_complete(); + + if tx_empty && fifo_empty && tc_complete { + Poll::Ready(Ok(())) + } else { + // Enable appropriate interrupt + cortex_m::interrupt::free(|_| { + if !tx_empty { + self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); + } else { + self.info.regs.ctrl().modify(|_, w| w.tcie().enabled()); + } + }); + Poll::Pending + } + }) + .await + } + + /// Try to write without blocking + pub fn try_write(&mut self, buf: &[u8]) -> Result { + let mut writer = unsafe { self.state.tx_buf.writer() }; + let mut written = 0; + + for &byte in buf { + if writer.push_one(byte) { + written += 1; + } else { + break; + } + } + + if written > 0 { + // Enable TX interrupt to start transmission + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); + }); + } + + Ok(written) + } +} + +// ============================================================================ +// BUFFERED RX IMPLEMENTATION +// ============================================================================ + +impl<'a> BufferedLpuartRx<'a> { + /// Helper for RX-only initialization + fn new_inner( + inner: Peri<'a, T>, + rx_pin: Peri<'a, AnyPin>, + rts_pin: Option>, + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result> { + let state = BufferedLpuart::init_common::( + &inner, + None, + Some(rx_buffer), + &config, + false, + true, + rts_pin.is_some(), + false, + )?; + + Ok(BufferedLpuartRx { + info: T::info(), + state, + _rx_pin: rx_pin, + _rts_pin: rts_pin, + }) + } + + /// Create a new RX-only buffered LPUART + pub fn new( + inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + rx_pin.as_rx(); + + Self::new_inner::(inner, rx_pin.into(), None, rx_buffer, config) + } + + /// Create a new RX-only buffered LPUART with RTS flow control + pub fn new_with_rts( + inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + _irq: impl interrupt::typelevel::Binding> + 'a, + rx_buffer: &'a mut [u8], + config: Config, + ) -> Result { + rx_pin.as_rx(); + rts_pin.as_rts(); + + Self::new_inner::(inner, rx_pin.into(), Some(rts_pin.into()), rx_buffer, config) + } +} + +impl<'a> BufferedLpuartRx<'a> { + /// Read data asynchronously + pub async fn read(&mut self, buf: &mut [u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + + let mut read = 0; + + // Try to read available data + poll_fn(|cx| { + self.state.rx_waker.register(cx.waker()); + + // Disable RX interrupt while reading from buffer + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().disabled()); + }); + + let mut reader = unsafe { self.state.rx_buf.reader() }; + let available = reader.pop(|data| { + let to_copy = core::cmp::min(data.len(), buf.len() - read); + if to_copy > 0 { + buf[read..read + to_copy].copy_from_slice(&data[..to_copy]); + read += to_copy; + } + to_copy + }); + + // Re-enable RX interrupt + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().enabled()); + }); + + if read > 0 { + Poll::Ready(Ok(read)) + } else if available == 0 { + Poll::Pending + } else { + Poll::Ready(Ok(0)) + } + }) + .await + } + + /// Try to read without blocking + pub fn try_read(&mut self, buf: &mut [u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + + // Disable RX interrupt while reading from buffer + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().disabled()); + }); + + let mut reader = unsafe { self.state.rx_buf.reader() }; + let read = reader.pop(|data| { + let to_copy = core::cmp::min(data.len(), buf.len()); + if to_copy > 0 { + buf[..to_copy].copy_from_slice(&data[..to_copy]); + } + to_copy + }); + + // Re-enable RX interrupt + cortex_m::interrupt::free(|_| { + self.info.regs.ctrl().modify(|_, w| w.rie().enabled()); + }); + + Ok(read) + } +} + +// ============================================================================ +// INTERRUPT HANDLER +// ============================================================================ + +/// Buffered UART interrupt handler +pub struct BufferedInterruptHandler { + _phantom: PhantomData, +} + +impl crate::interrupt::typelevel::Handler for BufferedInterruptHandler { + unsafe fn on_interrupt() { + let regs = T::info().regs; + let state = T::buffered_state(); + + // Check if this instance is initialized + if !state.initialized.load(Ordering::Relaxed) { + return; + } + + let ctrl = regs.ctrl().read(); + let stat = regs.stat().read(); + let has_fifo = regs.param().read().rxfifo().bits() > 0; + + // Handle overrun error + if stat.or().is_overrun() { + regs.stat().write(|w| w.or().clear_bit_by_one()); + state.rx_waker.wake(); + return; + } + + // Clear other error flags + if stat.pf().is_parity() { + regs.stat().write(|w| w.pf().clear_bit_by_one()); + } + if stat.fe().is_error() { + regs.stat().write(|w| w.fe().clear_bit_by_one()); + } + if stat.nf().is_noise() { + regs.stat().write(|w| w.nf().clear_bit_by_one()); + } + + // Handle RX data + if ctrl.rie().is_enabled() && (has_data(regs) || stat.idle().is_idle()) { + let mut pushed_any = false; + let mut writer = state.rx_buf.writer(); + + if has_fifo { + // Read from FIFO + while regs.water().read().rxcount().bits() > 0 { + let byte = (regs.data().read().bits() & 0xFF) as u8; + if writer.push_one(byte) { + pushed_any = true; + } else { + // Buffer full, stop reading + break; + } + } + } else { + // Read single byte + if regs.stat().read().rdrf().is_rxdata() { + let byte = (regs.data().read().bits() & 0xFF) as u8; + if writer.push_one(byte) { + pushed_any = true; + } + } + } + + if pushed_any { + state.rx_waker.wake(); + } + + // Clear idle flag if set + if stat.idle().is_idle() { + regs.stat().write(|w| w.idle().clear_bit_by_one()); + } + } + + // Handle TX data + if ctrl.tie().is_enabled() { + let mut sent_any = false; + let mut reader = state.tx_buf.reader(); + + // Send data while TX buffer is ready and we have data + while regs.stat().read().tdre().is_no_txdata() { + if let Some(byte) = reader.pop_one() { + regs.data().write(|w| w.bits(u32::from(byte))); + sent_any = true; + } else { + // No more data to send + break; + } + } + + if sent_any { + state.tx_waker.wake(); + } + + // If buffer is empty, switch to TC interrupt or disable + if state.tx_buf.is_empty() { + cortex_m::interrupt::free(|_| { + regs.ctrl().modify(|_, w| w.tie().disabled().tcie().enabled()); + }); + } + } + + // Handle transmission complete + if ctrl.tcie().is_enabled() && regs.stat().read().tc().is_complete() { + state.tx_done.store(true, Ordering::Release); + state.tx_waker.wake(); + + // Disable TC interrupt + cortex_m::interrupt::free(|_| { + regs.ctrl().modify(|_, w| w.tcie().disabled()); + }); + } + } +} + +// ============================================================================ +// EMBEDDED-IO ASYNC TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_io_async::ErrorType for BufferedLpuartTx<'_> { + type Error = Error; +} + +impl embedded_io_async::ErrorType for BufferedLpuartRx<'_> { + type Error = Error; +} + +impl embedded_io_async::ErrorType for BufferedLpuart<'_> { + type Error = Error; +} + +impl embedded_io_async::Write for BufferedLpuartTx<'_> { + async fn write(&mut self, buf: &[u8]) -> core::result::Result { + self.write(buf).await + } + + async fn flush(&mut self) -> core::result::Result<(), Self::Error> { + self.flush().await + } +} + +impl embedded_io_async::Read for BufferedLpuartRx<'_> { + async fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + self.read(buf).await + } +} + +impl embedded_io_async::Write for BufferedLpuart<'_> { + async fn write(&mut self, buf: &[u8]) -> core::result::Result { + self.tx.write(buf).await + } + + async fn flush(&mut self) -> core::result::Result<(), Self::Error> { + self.tx.flush().await + } +} + +impl embedded_io_async::Read for BufferedLpuart<'_> { + async fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + self.rx.read(buf).await + } +} diff --git a/embassy-mcxa/src/lpuart/mod.rs b/embassy-mcxa/src/lpuart/mod.rs new file mode 100644 index 000000000..2d8308ec8 --- /dev/null +++ b/embassy-mcxa/src/lpuart/mod.rs @@ -0,0 +1,1292 @@ +use core::marker::PhantomData; + +use embassy_hal_internal::{Peri, PeripheralType}; +use paste::paste; + +use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig}; +use crate::clocks::{enable_and_reset, ClockError, Gate, PoweredClock}; +use crate::gpio::SealedPin; +use crate::pac::lpuart0::baud::Sbns as StopBits; +use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; +use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; +use crate::pac::lpuart0::stat::Msbf as MsbFirst; +use crate::{interrupt, pac, AnyPin}; + +pub mod buffered; + +// ============================================================================ +// STUB IMPLEMENTATION +// ============================================================================ + +// Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API +// Pin and Clock initialization is currently done at the examples level. + +// --- START DMA --- +mod dma { + pub struct Channel<'d> { + pub(super) _lifetime: core::marker::PhantomData<&'d ()>, + } +} + +use dma::Channel; + +// --- END DMA --- + +// ============================================================================ +// MISC +// ============================================================================ + +mod sealed { + /// Simply seal a trait to prevent external implementations + pub trait Sealed {} +} + +// ============================================================================ +// INSTANCE TRAIT +// ============================================================================ + +pub type Regs = &'static crate::pac::lpuart0::RegisterBlock; + +pub trait SealedInstance { + fn info() -> Info; + fn index() -> usize; + fn buffered_state() -> &'static buffered::State; +} + +pub struct Info { + pub regs: Regs, +} + +/// Trait for LPUART peripheral instances +#[allow(private_bounds)] +pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate { + const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance; + type Interrupt: interrupt::typelevel::Interrupt; +} + +macro_rules! impl_instance { + ($($n:expr),*) => { + $( + paste!{ + impl SealedInstance for crate::peripherals::[] { + fn info() -> Info { + Info { + regs: unsafe { &*pac::[]::ptr() }, + } + } + + #[inline] + fn index() -> usize { + $n + } + + fn buffered_state() -> &'static buffered::State { + static BUFFERED_STATE: buffered::State = buffered::State::new(); + &BUFFERED_STATE + } + } + + impl Instance for crate::peripherals::[] { + const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance + = crate::clocks::periph_helpers::LpuartInstance::[]; + type Interrupt = crate::interrupt::typelevel::[]; + } + } + )* + }; +} + +impl_instance!(0, 1, 2, 3, 4, 5); + +// ============================================================================ +// INSTANCE HELPER FUNCTIONS +// ============================================================================ + +/// Perform software reset on the LPUART peripheral +pub fn perform_software_reset(regs: Regs) { + // Software reset - set and clear RST bit (Global register) + regs.global().write(|w| w.rst().reset()); + regs.global().write(|w| w.rst().no_effect()); +} + +/// Disable both transmitter and receiver +pub fn disable_transceiver(regs: Regs) { + regs.ctrl().modify(|_, w| w.te().disabled().re().disabled()); +} + +/// Calculate and configure baudrate settings +pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock_freq: u32) -> Result<()> { + let (osr, sbr) = calculate_baudrate(baudrate_bps, clock_freq)?; + + // Configure BAUD register + regs.baud().modify(|_, w| unsafe { + // Clear and set OSR + w.osr().bits(osr - 1); + // Clear and set SBR + w.sbr().bits(sbr); + // Set BOTHEDGE if OSR is between 4 and 7 + if osr > 3 && osr < 8 { + w.bothedge().enabled() + } else { + w.bothedge().disabled() + } + }); + + Ok(()) +} + +/// Configure frame format (stop bits, data bits) +pub fn configure_frame_format(regs: Regs, config: &Config) { + // Configure stop bits + regs.baud().modify(|_, w| w.sbns().variant(config.stop_bits_count)); + + // Clear M10 for now (10-bit mode) + regs.baud().modify(|_, w| w.m10().disabled()); +} + +/// Configure control settings (parity, data bits, idle config, pin swap) +pub fn configure_control_settings(regs: Regs, config: &Config) { + regs.ctrl().modify(|_, w| { + // Parity configuration + let mut w = if let Some(parity) = config.parity_mode { + w.pe().enabled().pt().variant(parity) + } else { + w.pe().disabled() + }; + + // Data bits configuration + w = match config.data_bits_count { + DataBits::Data8 => { + if config.parity_mode.is_some() { + w.m().data9() // 8 data + 1 parity = 9 bits + } else { + w.m().data8() // 8 data bits only + } + } + DataBits::Data9 => w.m().data9(), + }; + + // Idle configuration + w = w.idlecfg().variant(config.rx_idle_config); + w = w.ilt().variant(config.rx_idle_type); + + // Swap TXD/RXD if configured + if config.swap_txd_rxd { + w.swap().swap() + } else { + w.swap().standard() + } + }); +} + +/// Configure FIFO settings and watermarks +pub fn configure_fifo(regs: Regs, config: &Config) { + // Configure WATER register for FIFO watermarks + regs.water().write(|w| unsafe { + w.rxwater() + .bits(config.rx_fifo_watermark) + .txwater() + .bits(config.tx_fifo_watermark) + }); + + // Enable TX/RX FIFOs + regs.fifo().modify(|_, w| w.txfe().enabled().rxfe().enabled()); + + // Flush FIFOs + regs.fifo() + .modify(|_, w| w.txflush().txfifo_rst().rxflush().rxfifo_rst()); +} + +/// Clear all status flags +pub fn clear_all_status_flags(regs: Regs) { + regs.stat().reset(); +} + +/// Configure hardware flow control if enabled +pub fn configure_flow_control(regs: Regs, enable_tx_cts: bool, enable_rx_rts: bool, config: &Config) { + if enable_rx_rts || enable_tx_cts { + regs.modir().modify(|_, w| { + let mut w = w; + + // Configure TX CTS + w = w.txctsc().variant(config.tx_cts_config); + w = w.txctssrc().variant(config.tx_cts_source); + + if enable_rx_rts { + w = w.rxrtse().enabled(); + } else { + w = w.rxrtse().disabled(); + } + + if enable_tx_cts { + w = w.txctse().enabled(); + } else { + w = w.txctse().disabled(); + } + + w + }); + } +} + +/// Configure bit order (MSB first or LSB first) +pub fn configure_bit_order(regs: Regs, msb_first: MsbFirst) { + regs.stat().modify(|_, w| w.msbf().variant(msb_first)); +} + +/// Enable transmitter and/or receiver based on configuration +pub fn enable_transceiver(regs: Regs, enable_tx: bool, enable_rx: bool) { + regs.ctrl().modify(|_, w| { + let mut w = w; + if enable_tx { + w = w.te().enabled(); + } + if enable_rx { + w = w.re().enabled(); + } + w + }); +} + +pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> { + let mut baud_diff = baudrate; + let mut osr = 0u8; + let mut sbr = 0u16; + + // Try OSR values from 4 to 32 + for osr_temp in 4u8..=32u8 { + // Calculate SBR: (srcClock_Hz * 2 / (baudRate * osr) + 1) / 2 + let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32)).div_ceil(2); + + let sbr_temp = if sbr_calc == 0 { + 1 + } else if sbr_calc > 0x1FFF { + 0x1FFF + } else { + sbr_calc as u16 + }; + + // Calculate actual baud rate + let calculated_baud = src_clock_hz / (osr_temp as u32 * sbr_temp as u32); + + let temp_diff = calculated_baud.abs_diff(baudrate); + + if temp_diff <= baud_diff { + baud_diff = temp_diff; + osr = osr_temp; + sbr = sbr_temp; + } + } + + // Check if baud rate difference is within 3% + if baud_diff > (baudrate / 100) * 3 { + return Err(Error::UnsupportedBaudrate); + } + + Ok((osr, sbr)) +} + +/// Wait for all transmit operations to complete +pub fn wait_for_tx_complete(regs: Regs) { + // Wait for TX FIFO to empty + while regs.water().read().txcount().bits() != 0 { + // Wait for TX FIFO to drain + } + + // Wait for last character to shift out (TC = Transmission Complete) + while regs.stat().read().tc().is_active() { + // Wait for transmission to complete + } +} + +pub fn check_and_clear_rx_errors(regs: Regs) -> Result<()> { + let stat = regs.stat().read(); + let mut status = Ok(()); + + // Check for overrun first - other error flags are prevented when OR is set + if stat.or().is_overrun() { + regs.stat().write(|w| w.or().clear_bit_by_one()); + + return Err(Error::Overrun); + } + + if stat.pf().is_parity() { + regs.stat().write(|w| w.pf().clear_bit_by_one()); + status = Err(Error::Parity); + } + + if stat.fe().is_error() { + regs.stat().write(|w| w.fe().clear_bit_by_one()); + status = Err(Error::Framing); + } + + if stat.nf().is_noise() { + regs.stat().write(|w| w.nf().clear_bit_by_one()); + status = Err(Error::Noise); + } + + status +} + +pub fn has_data(regs: Regs) -> bool { + if regs.param().read().rxfifo().bits() > 0 { + // FIFO is available - check RXCOUNT in WATER register + regs.water().read().rxcount().bits() > 0 + } else { + // No FIFO - check RDRF flag in STAT register + regs.stat().read().rdrf().is_rxdata() + } +} + +// ============================================================================ +// PIN TRAITS FOR LPUART FUNCTIONALITY +// ============================================================================ + +impl sealed::Sealed for T {} + +/// io configuration trait for Lpuart Tx configuration +pub trait TxPin: Into + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Tx usage + fn as_tx(&self); +} + +/// io configuration trait for Lpuart Rx configuration +pub trait RxPin: Into + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Rx usage + fn as_rx(&self); +} + +/// io configuration trait for Lpuart Cts +pub trait CtsPin: Into + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Cts usage + fn as_cts(&self); +} + +/// io configuration trait for Lpuart Rts +pub trait RtsPin: Into + sealed::Sealed + PeripheralType { + /// convert the pin to appropriate function for Lpuart Rts usage + fn as_rts(&self); +} + +macro_rules! impl_tx_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl TxPin for crate::peripherals::$pin { + fn as_tx(&self) { + // TODO: Check these are right + self.set_pull(crate::gpio::Pull::Up); + self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); + self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); + self.set_function(crate::pac::port0::pcr0::Mux::$alt); + self.set_enable_input_buffer(); + } + } + }; +} + +macro_rules! impl_rx_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl RxPin for crate::peripherals::$pin { + fn as_rx(&self) { + // TODO: Check these are right + self.set_pull(crate::gpio::Pull::Up); + self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); + self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); + self.set_function(crate::pac::port0::pcr0::Mux::$alt); + self.set_enable_input_buffer(); + } + } + }; +} + +// TODO: Macro and impls for CTS/RTS pins +macro_rules! impl_cts_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl CtsPin for crate::peripherals::$pin { + fn as_cts(&self) { + todo!() + } + } + }; +} + +macro_rules! impl_rts_pin { + ($inst:ident, $pin:ident, $alt:ident) => { + impl RtsPin for crate::peripherals::$pin { + fn as_rts(&self) { + todo!() + } + } + }; +} + +// LPUART 0 +impl_tx_pin!(LPUART0, P0_3, Mux2); +impl_tx_pin!(LPUART0, P0_21, Mux3); +impl_tx_pin!(LPUART0, P2_1, Mux2); + +impl_rx_pin!(LPUART0, P0_2, Mux2); +impl_rx_pin!(LPUART0, P0_20, Mux3); +impl_rx_pin!(LPUART0, P2_0, Mux2); + +impl_cts_pin!(LPUART0, P0_1, Mux2); +impl_cts_pin!(LPUART0, P0_23, Mux3); +impl_cts_pin!(LPUART0, P2_3, Mux2); + +impl_rts_pin!(LPUART0, P0_0, Mux2); +impl_rts_pin!(LPUART0, P0_22, Mux3); +impl_rts_pin!(LPUART0, P2_2, Mux2); + +// LPUART 1 +impl_tx_pin!(LPUART1, P1_9, Mux2); +impl_tx_pin!(LPUART1, P2_13, Mux3); +impl_tx_pin!(LPUART1, P3_9, Mux3); +impl_tx_pin!(LPUART1, P3_21, Mux3); + +impl_rx_pin!(LPUART1, P1_8, Mux2); +impl_rx_pin!(LPUART1, P2_12, Mux3); +impl_rx_pin!(LPUART1, P3_8, Mux3); +impl_rx_pin!(LPUART1, P3_20, Mux3); + +impl_cts_pin!(LPUART1, P1_11, Mux2); +impl_cts_pin!(LPUART1, P2_17, Mux3); +impl_cts_pin!(LPUART1, P3_11, Mux3); +impl_cts_pin!(LPUART1, P3_23, Mux3); + +impl_rts_pin!(LPUART1, P1_10, Mux2); +impl_rts_pin!(LPUART1, P2_15, Mux3); +impl_rts_pin!(LPUART1, P2_16, Mux3); +impl_rts_pin!(LPUART1, P3_10, Mux3); + +// LPUART 2 +impl_tx_pin!(LPUART2, P1_5, Mux3); +impl_tx_pin!(LPUART2, P1_13, Mux3); +impl_tx_pin!(LPUART2, P2_2, Mux3); +impl_tx_pin!(LPUART2, P2_10, Mux3); +impl_tx_pin!(LPUART2, P3_15, Mux2); + +impl_rx_pin!(LPUART2, P1_4, Mux3); +impl_rx_pin!(LPUART2, P1_12, Mux3); +impl_rx_pin!(LPUART2, P2_3, Mux3); +impl_rx_pin!(LPUART2, P2_11, Mux3); +impl_rx_pin!(LPUART2, P3_14, Mux2); + +impl_cts_pin!(LPUART2, P1_7, Mux3); +impl_cts_pin!(LPUART2, P1_15, Mux3); +impl_cts_pin!(LPUART2, P2_4, Mux3); +impl_cts_pin!(LPUART2, P3_13, Mux2); + +impl_rts_pin!(LPUART2, P1_6, Mux3); +impl_rts_pin!(LPUART2, P1_14, Mux3); +impl_rts_pin!(LPUART2, P2_5, Mux3); +impl_rts_pin!(LPUART2, P3_12, Mux2); + +// LPUART 3 +impl_tx_pin!(LPUART3, P3_1, Mux3); +impl_tx_pin!(LPUART3, P3_12, Mux3); +impl_tx_pin!(LPUART3, P4_5, Mux3); + +impl_rx_pin!(LPUART3, P3_0, Mux3); +impl_rx_pin!(LPUART3, P3_13, Mux3); +impl_rx_pin!(LPUART3, P4_2, Mux3); + +impl_cts_pin!(LPUART3, P3_7, Mux3); +impl_cts_pin!(LPUART3, P3_14, Mux3); +impl_cts_pin!(LPUART3, P4_6, Mux3); + +impl_rts_pin!(LPUART3, P3_6, Mux3); +impl_rts_pin!(LPUART3, P3_15, Mux3); +impl_rts_pin!(LPUART3, P4_7, Mux3); + +// LPUART 4 +impl_tx_pin!(LPUART4, P2_7, Mux3); +impl_tx_pin!(LPUART4, P3_19, Mux2); +impl_tx_pin!(LPUART4, P3_27, Mux3); +impl_tx_pin!(LPUART4, P4_3, Mux3); + +impl_rx_pin!(LPUART4, P2_6, Mux3); +impl_rx_pin!(LPUART4, P3_18, Mux2); +impl_rx_pin!(LPUART4, P3_28, Mux3); +impl_rx_pin!(LPUART4, P4_4, Mux3); + +impl_cts_pin!(LPUART4, P2_0, Mux3); +impl_cts_pin!(LPUART4, P3_17, Mux2); +impl_cts_pin!(LPUART4, P3_31, Mux3); + +impl_rts_pin!(LPUART4, P2_1, Mux3); +impl_rts_pin!(LPUART4, P3_16, Mux2); +impl_rts_pin!(LPUART4, P3_30, Mux3); + +// LPUART 5 +impl_tx_pin!(LPUART5, P1_10, Mux8); +impl_tx_pin!(LPUART5, P1_17, Mux8); + +impl_rx_pin!(LPUART5, P1_11, Mux8); +impl_rx_pin!(LPUART5, P1_16, Mux8); + +impl_cts_pin!(LPUART5, P1_12, Mux8); +impl_cts_pin!(LPUART5, P1_19, Mux8); + +impl_rts_pin!(LPUART5, P1_13, Mux8); +impl_rts_pin!(LPUART5, P1_18, Mux8); + +// ============================================================================ +// ERROR TYPES AND RESULTS +// ============================================================================ + +/// LPUART error types +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + /// Read error + Read, + /// Buffer overflow + Overrun, + /// Noise error + Noise, + /// Framing error + Framing, + /// Parity error + Parity, + /// Failure + Fail, + /// Invalid argument + InvalidArgument, + /// Lpuart baud rate cannot be supported with the given clock + UnsupportedBaudrate, + /// RX FIFO Empty + RxFifoEmpty, + /// TX FIFO Full + TxFifoFull, + /// TX Busy + TxBusy, + /// Clock Error + ClockSetup(ClockError), +} + +/// A specialized Result type for LPUART operations +pub type Result = core::result::Result; + +// ============================================================================ +// CONFIGURATION STRUCTURES +// ============================================================================ + +/// Lpuart config +#[derive(Debug, Clone, Copy)] +pub struct Config { + /// Power state required for this peripheral + pub power: PoweredClock, + /// Clock source + pub source: LpuartClockSel, + /// Clock divisor + pub div: Div4, + /// Baud rate in bits per second + pub baudrate_bps: u32, + /// Parity configuration + pub parity_mode: Option, + /// Number of data bits + pub data_bits_count: DataBits, + /// MSB First or LSB First configuration + pub msb_first: MsbFirst, + /// Number of stop bits + pub stop_bits_count: StopBits, + /// TX FIFO watermark + pub tx_fifo_watermark: u8, + /// RX FIFO watermark + pub rx_fifo_watermark: u8, + /// TX CTS source + pub tx_cts_source: TxCtsSource, + /// TX CTS configure + pub tx_cts_config: TxCtsConfig, + /// RX IDLE type + pub rx_idle_type: IdleType, + /// RX IDLE configuration + pub rx_idle_config: IdleConfig, + /// Swap TXD and RXD pins + pub swap_txd_rxd: bool, +} + +impl Default for Config { + fn default() -> Self { + Self { + baudrate_bps: 115_200u32, + parity_mode: None, + data_bits_count: DataBits::Data8, + msb_first: MsbFirst::LsbFirst, + stop_bits_count: StopBits::One, + tx_fifo_watermark: 0, + rx_fifo_watermark: 1, + tx_cts_source: TxCtsSource::Cts, + tx_cts_config: TxCtsConfig::Start, + rx_idle_type: IdleType::FromStart, + rx_idle_config: IdleConfig::Idle1, + swap_txd_rxd: false, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: LpuartClockSel::FroLfDiv, + div: Div4::no_div(), + } + } +} + +/// LPUART status flags +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct Status { + /// Transmit data register empty + pub tx_empty: bool, + /// Transmission complete + pub tx_complete: bool, + /// Receive data register full + pub rx_full: bool, + /// Idle line detected + pub idle: bool, + /// Receiver overrun + pub overrun: bool, + /// Noise error + pub noise: bool, + /// Framing error + pub framing: bool, + /// Parity error + pub parity: bool, +} + +// ============================================================================ +// MODE TRAITS (BLOCKING/ASYNC) +// ============================================================================ + +/// Driver move trait. +#[allow(private_bounds)] +pub trait Mode: sealed::Sealed {} + +/// Blocking mode. +pub struct Blocking; +impl sealed::Sealed for Blocking {} +impl Mode for Blocking {} + +/// Async mode. +pub struct Async; +impl sealed::Sealed for Async {} +impl Mode for Async {} + +// ============================================================================ +// CORE DRIVER STRUCTURES +// ============================================================================ + +/// Lpuart driver. +pub struct Lpuart<'a, M: Mode> { + info: Info, + tx: LpuartTx<'a, M>, + rx: LpuartRx<'a, M>, +} + +/// Lpuart TX driver. +pub struct LpuartTx<'a, M: Mode> { + info: Info, + _tx_pin: Peri<'a, AnyPin>, + _cts_pin: Option>, + _tx_dma: Option>, + mode: PhantomData<(&'a (), M)>, +} + +/// Lpuart Rx driver. +pub struct LpuartRx<'a, M: Mode> { + info: Info, + _rx_pin: Peri<'a, AnyPin>, + _rts_pin: Option>, + _rx_dma: Option>, + mode: PhantomData<(&'a (), M)>, +} + +// ============================================================================ +// LPUART CORE IMPLEMENTATION +// ============================================================================ + +impl<'a, M: Mode> Lpuart<'a, M> { + fn init( + enable_tx: bool, + enable_rx: bool, + enable_tx_cts: bool, + enable_rx_rts: bool, + config: Config, + ) -> Result<()> { + let regs = T::info().regs; + + // Enable clocks + let conf = LpuartConfig { + power: config.power, + source: config.source, + div: config.div, + instance: T::CLOCK_INSTANCE, + }; + let clock_freq = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; + + // Perform initialization sequence + perform_software_reset(regs); + disable_transceiver(regs); + configure_baudrate(regs, config.baudrate_bps, clock_freq)?; + configure_frame_format(regs, &config); + configure_control_settings(regs, &config); + configure_fifo(regs, &config); + clear_all_status_flags(regs); + configure_flow_control(regs, enable_tx_cts, enable_rx_rts, &config); + configure_bit_order(regs, config.msb_first); + enable_transceiver(regs, enable_rx, enable_tx); + + Ok(()) + } + + /// Deinitialize the LPUART peripheral + pub fn deinit(&self) -> Result<()> { + let regs = self.info.regs; + + // Wait for TX operations to complete + wait_for_tx_complete(regs); + + // Clear all status flags + clear_all_status_flags(regs); + + // Disable the module - clear all CTRL register bits + regs.ctrl().reset(); + + Ok(()) + } + + /// Split the Lpuart into a transmitter and receiver + pub fn split(self) -> (LpuartTx<'a, M>, LpuartRx<'a, M>) { + (self.tx, self.rx) + } + + /// Split the Lpuart into a transmitter and receiver by mutable reference + pub fn split_ref(&mut self) -> (&mut LpuartTx<'a, M>, &mut LpuartRx<'a, M>) { + (&mut self.tx, &mut self.rx) + } +} + +// ============================================================================ +// BLOCKING MODE IMPLEMENTATIONS +// ============================================================================ + +impl<'a> Lpuart<'a, Blocking> { + /// Create a new blocking LPUART instance with RX/TX pins. + pub fn new_blocking( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + config: Config, + ) -> Result { + // Configure the pins for LPUART usage + tx_pin.as_tx(); + rx_pin.as_rx(); + + // Initialize the peripheral + Self::init::(true, true, false, false, config)?; + + Ok(Self { + info: T::info(), + tx: LpuartTx::new_inner(T::info(), tx_pin.into(), None, None), + rx: LpuartRx::new_inner(T::info(), rx_pin.into(), None, None), + }) + } + + /// Create a new blocking LPUART instance with RX, TX and RTS/CTS flow control pins + pub fn new_blocking_with_rtscts( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + rx_pin: Peri<'a, impl RxPin>, + cts_pin: Peri<'a, impl CtsPin>, + rts_pin: Peri<'a, impl RtsPin>, + config: Config, + ) -> Result { + // Configure the pins for LPUART usage + rx_pin.as_rx(); + tx_pin.as_tx(); + rts_pin.as_rts(); + cts_pin.as_cts(); + + // Initialize the peripheral with flow control + Self::init::(true, true, true, true, config)?; + + Ok(Self { + info: T::info(), + rx: LpuartRx::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into()), None), + tx: LpuartTx::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into()), None), + }) + } +} + +// ---------------------------------------------------------------------------- +// Blocking TX Implementation +// ---------------------------------------------------------------------------- + +impl<'a, M: Mode> LpuartTx<'a, M> { + fn new_inner( + info: Info, + tx_pin: Peri<'a, AnyPin>, + cts_pin: Option>, + tx_dma: Option>, + ) -> Self { + Self { + info, + _tx_pin: tx_pin, + _cts_pin: cts_pin, + _tx_dma: tx_dma, + mode: PhantomData, + } + } +} + +impl<'a> LpuartTx<'a, Blocking> { + /// Create a new blocking LPUART transmitter instance + pub fn new_blocking( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + config: Config, + ) -> Result { + // Configure the pins for LPUART usage + tx_pin.as_tx(); + + // Initialize the peripheral + Lpuart::::init::(true, false, false, false, config)?; + + Ok(Self::new_inner(T::info(), tx_pin.into(), None, None)) + } + + /// Create a new blocking LPUART transmitter instance with CTS flow control + pub fn new_blocking_with_cts( + _inner: Peri<'a, T>, + tx_pin: Peri<'a, impl TxPin>, + cts_pin: Peri<'a, impl CtsPin>, + config: Config, + ) -> Result { + tx_pin.as_tx(); + cts_pin.as_cts(); + + Lpuart::::init::(true, false, true, false, config)?; + + Ok(Self::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into()), None)) + } + + fn write_byte_internal(&mut self, byte: u8) -> Result<()> { + self.info.regs.data().modify(|_, w| unsafe { w.bits(u32::from(byte)) }); + + Ok(()) + } + + fn blocking_write_byte(&mut self, byte: u8) -> Result<()> { + while self.info.regs.stat().read().tdre().is_txdata() {} + self.write_byte_internal(byte) + } + + fn write_byte(&mut self, byte: u8) -> Result<()> { + if self.info.regs.stat().read().tdre().is_txdata() { + Err(Error::TxFifoFull) + } else { + self.write_byte_internal(byte) + } + } + + /// Write data to LPUART TX blocking execution until all data is sent. + pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> { + for x in buf { + self.blocking_write_byte(*x)?; + } + + Ok(()) + } + + pub fn write_str_blocking(&mut self, buf: &str) { + let _ = self.blocking_write(buf.as_bytes()); + } + + /// Write data to LPUART TX without blocking. + pub fn write(&mut self, buf: &[u8]) -> Result<()> { + for x in buf { + self.write_byte(*x)?; + } + + Ok(()) + } + + /// Flush LPUART TX blocking execution until all data has been transmitted. + pub fn blocking_flush(&mut self) -> Result<()> { + while self.info.regs.water().read().txcount().bits() != 0 { + // Wait for TX FIFO to drain + } + + // Wait for last character to shift out + while self.info.regs.stat().read().tc().is_active() { + // Wait for transmission to complete + } + + Ok(()) + } + + /// Flush LPUART TX. + pub fn flush(&mut self) -> Result<()> { + // Check if TX FIFO is empty + if self.info.regs.water().read().txcount().bits() != 0 { + return Err(Error::TxBusy); + } + + // Check if transmission is complete + if self.info.regs.stat().read().tc().is_active() { + return Err(Error::TxBusy); + } + + Ok(()) + } +} + +// ---------------------------------------------------------------------------- +// Blocking RX Implementation +// ---------------------------------------------------------------------------- + +impl<'a, M: Mode> LpuartRx<'a, M> { + fn new_inner( + info: Info, + rx_pin: Peri<'a, AnyPin>, + rts_pin: Option>, + rx_dma: Option>, + ) -> Self { + Self { + info, + _rx_pin: rx_pin, + _rts_pin: rts_pin, + _rx_dma: rx_dma, + mode: PhantomData, + } + } +} + +impl<'a> LpuartRx<'a, Blocking> { + /// Create a new blocking LPUART Receiver instance + pub fn new_blocking( + _inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + config: Config, + ) -> Result { + rx_pin.as_rx(); + + Lpuart::::init::(false, true, false, false, config)?; + + Ok(Self::new_inner(T::info(), rx_pin.into(), None, None)) + } + + /// Create a new blocking LPUART Receiver instance with RTS flow control + pub fn new_blocking_with_rts( + _inner: Peri<'a, T>, + rx_pin: Peri<'a, impl RxPin>, + rts_pin: Peri<'a, impl RtsPin>, + config: Config, + ) -> Result { + rx_pin.as_rx(); + rts_pin.as_rts(); + + Lpuart::::init::(false, true, false, true, config)?; + + Ok(Self::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into()), None)) + } + + fn read_byte_internal(&mut self) -> Result { + let data = self.info.regs.data().read(); + + Ok((data.bits() & 0xFF) as u8) + } + + fn read_byte(&mut self) -> Result { + check_and_clear_rx_errors(self.info.regs)?; + + if !has_data(self.info.regs) { + return Err(Error::RxFifoEmpty); + } + + self.read_byte_internal() + } + + fn blocking_read_byte(&mut self) -> Result { + loop { + if has_data(self.info.regs) { + return self.read_byte_internal(); + } + + check_and_clear_rx_errors(self.info.regs)?; + } + } + + /// Read data from LPUART RX without blocking. + pub fn read(&mut self, buf: &mut [u8]) -> Result<()> { + for byte in buf.iter_mut() { + *byte = self.read_byte()?; + } + Ok(()) + } + + /// Read data from LPUART RX blocking execution until the buffer is filled. + pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> { + for byte in buf.iter_mut() { + *byte = self.blocking_read_byte()?; + } + Ok(()) + } +} + +impl<'a> Lpuart<'a, Blocking> { + /// Read data from LPUART RX blocking execution until the buffer is filled + pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> { + self.rx.blocking_read(buf) + } + + /// Read data from LPUART RX without blocking + pub fn read(&mut self, buf: &mut [u8]) -> Result<()> { + self.rx.read(buf) + } + + /// Write data to LPUART TX blocking execution until all data is sent + pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> { + self.tx.blocking_write(buf) + } + + pub fn write_byte(&mut self, byte: u8) -> Result<()> { + self.tx.write_byte(byte) + } + + pub fn read_byte_blocking(&mut self) -> u8 { + loop { + if let Ok(b) = self.rx.read_byte() { + return b; + } + } + } + + pub fn write_str_blocking(&mut self, buf: &str) { + self.tx.write_str_blocking(buf); + } + + /// Write data to LPUART TX without blocking + pub fn write(&mut self, buf: &[u8]) -> Result<()> { + self.tx.write(buf) + } + + /// Flush LPUART TX blocking execution until all data has been transmitted + pub fn blocking_flush(&mut self) -> Result<()> { + self.tx.blocking_flush() + } + + /// Flush LPUART TX without blocking + pub fn flush(&mut self) -> Result<()> { + self.tx.flush() + } +} + +// ============================================================================ +// ASYNC MODE IMPLEMENTATIONS +// ============================================================================ + +// TODO: Implement async mode for LPUART + +// ============================================================================ +// EMBEDDED-HAL 0.2 TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_hal_02::serial::Read for LpuartRx<'_, Blocking> { + type Error = Error; + + fn read(&mut self) -> core::result::Result> { + let mut buf = [0; 1]; + match self.read(&mut buf) { + Ok(_) => Ok(buf[0]), + Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_02::serial::Write for LpuartTx<'_, Blocking> { + type Error = Error; + + fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error> { + match self.write(&[word]) { + Ok(_) => Ok(()), + Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } + + fn flush(&mut self) -> core::result::Result<(), nb::Error> { + match self.flush() { + Ok(_) => Ok(()), + Err(Error::TxBusy) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_02::blocking::serial::Write for LpuartTx<'_, Blocking> { + type Error = Error; + + fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> { + self.blocking_write(buffer) + } + + fn bflush(&mut self) -> core::result::Result<(), Self::Error> { + self.blocking_flush() + } +} + +impl embedded_hal_02::serial::Read for Lpuart<'_, Blocking> { + type Error = Error; + + fn read(&mut self) -> core::result::Result> { + embedded_hal_02::serial::Read::read(&mut self.rx) + } +} + +impl embedded_hal_02::serial::Write for Lpuart<'_, Blocking> { + type Error = Error; + + fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error> { + embedded_hal_02::serial::Write::write(&mut self.tx, word) + } + + fn flush(&mut self) -> core::result::Result<(), nb::Error> { + embedded_hal_02::serial::Write::flush(&mut self.tx) + } +} + +impl embedded_hal_02::blocking::serial::Write for Lpuart<'_, Blocking> { + type Error = Error; + + fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> { + self.blocking_write(buffer) + } + + fn bflush(&mut self) -> core::result::Result<(), Self::Error> { + self.blocking_flush() + } +} + +// ============================================================================ +// EMBEDDED-HAL-NB TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_hal_nb::serial::Error for Error { + fn kind(&self) -> embedded_hal_nb::serial::ErrorKind { + match *self { + Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat, + Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun, + Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity, + Self::Noise => embedded_hal_nb::serial::ErrorKind::Noise, + _ => embedded_hal_nb::serial::ErrorKind::Other, + } + } +} + +impl embedded_hal_nb::serial::ErrorType for LpuartRx<'_, Blocking> { + type Error = Error; +} + +impl embedded_hal_nb::serial::ErrorType for LpuartTx<'_, Blocking> { + type Error = Error; +} + +impl embedded_hal_nb::serial::ErrorType for Lpuart<'_, Blocking> { + type Error = Error; +} + +impl embedded_hal_nb::serial::Read for LpuartRx<'_, Blocking> { + fn read(&mut self) -> nb::Result { + let mut buf = [0; 1]; + match self.read(&mut buf) { + Ok(_) => Ok(buf[0]), + Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_nb::serial::Write for LpuartTx<'_, Blocking> { + fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { + match self.write(&[word]) { + Ok(_) => Ok(()), + Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + match self.flush() { + Ok(_) => Ok(()), + Err(Error::TxBusy) => Err(nb::Error::WouldBlock), + Err(e) => Err(nb::Error::Other(e)), + } + } +} + +impl embedded_hal_nb::serial::Read for Lpuart<'_, Blocking> { + fn read(&mut self) -> nb::Result { + embedded_hal_nb::serial::Read::read(&mut self.rx) + } +} + +impl embedded_hal_nb::serial::Write for Lpuart<'_, Blocking> { + fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> { + embedded_hal_nb::serial::Write::write(&mut self.tx, char) + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + embedded_hal_nb::serial::Write::flush(&mut self.tx) + } +} + +// ============================================================================ +// EMBEDDED-IO TRAIT IMPLEMENTATIONS +// ============================================================================ + +impl embedded_io::Error for Error { + fn kind(&self) -> embedded_io::ErrorKind { + embedded_io::ErrorKind::Other + } +} + +impl embedded_io::ErrorType for LpuartRx<'_, Blocking> { + type Error = Error; +} + +impl embedded_io::ErrorType for LpuartTx<'_, Blocking> { + type Error = Error; +} + +impl embedded_io::ErrorType for Lpuart<'_, Blocking> { + type Error = Error; +} + +impl embedded_io::Read for LpuartRx<'_, Blocking> { + fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + self.blocking_read(buf).map(|_| buf.len()) + } +} + +impl embedded_io::Write for LpuartTx<'_, Blocking> { + fn write(&mut self, buf: &[u8]) -> core::result::Result { + self.blocking_write(buf).map(|_| buf.len()) + } + + fn flush(&mut self) -> core::result::Result<(), Self::Error> { + self.blocking_flush() + } +} + +impl embedded_io::Read for Lpuart<'_, Blocking> { + fn read(&mut self, buf: &mut [u8]) -> core::result::Result { + embedded_io::Read::read(&mut self.rx, buf) + } +} + +impl embedded_io::Write for Lpuart<'_, Blocking> { + fn write(&mut self, buf: &[u8]) -> core::result::Result { + embedded_io::Write::write(&mut self.tx, buf) + } + + fn flush(&mut self) -> core::result::Result<(), Self::Error> { + embedded_io::Write::flush(&mut self.tx) + } +} diff --git a/embassy-mcxa/src/ostimer.rs b/embassy-mcxa/src/ostimer.rs new file mode 100644 index 000000000..c51812e3d --- /dev/null +++ b/embassy-mcxa/src/ostimer.rs @@ -0,0 +1,745 @@ +//! # OSTIMER Driver with Robustness Features +//! +//! This module provides an async timer driver for the NXP MCXA276 OSTIMER peripheral +//! with protection against race conditions and timer rollover issues. +//! +//! ## Features +//! +//! - Async timing with embassy-time integration +//! - Gray code counter handling (42-bit counter) +//! - Interrupt-driven wakeups +//! - Configurable interrupt priority +//! - **Race condition protection**: Critical sections and atomic operations +//! - **Timer rollover handling**: Bounds checking and rollover prevention +//! +//! ## Clock Frequency Configuration +//! +//! The OSTIMER frequency depends on your system's clock configuration. You must provide +//! the actual frequency when calling `time_driver::init()`. +//! +//! ## Race Condition Protection +//! - Critical sections in interrupt handlers prevent concurrent access +//! - Atomic register operations with memory barriers +//! - Proper interrupt flag clearing and validation +//! +//! ## Timer Rollover Handling +//! - Bounds checking prevents scheduling beyond timer capacity +//! - Immediate wake for timestamps that would cause rollover issues +#![allow(dead_code)] + +use core::sync::atomic::{AtomicBool, Ordering}; + +use embassy_hal_internal::{Peri, PeripheralType}; + +use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; +use crate::clocks::{assert_reset, enable_and_reset, is_reset_released, release_reset, Gate, PoweredClock}; +use crate::interrupt::InterruptExt; +use crate::pac; + +// PAC defines the shared RegisterBlock under `ostimer0`. +type Regs = pac::ostimer0::RegisterBlock; + +// OSTIMER EVTIMER register layout constants +/// Total width of the EVTIMER counter in bits (42 bits total) +const EVTIMER_TOTAL_BITS: u32 = 42; +/// Width of the low part of EVTIMER (bits 31:0) +const EVTIMER_LO_BITS: u32 = 32; +/// Width of the high part of EVTIMER (bits 41:32) +const EVTIMER_HI_BITS: u32 = 10; +/// Bit position where high part starts in the combined 64-bit value +const EVTIMER_HI_SHIFT: u32 = 32; + +/// Bit mask for the high part of EVTIMER +const EVTIMER_HI_MASK: u16 = (1 << EVTIMER_HI_BITS) - 1; + +/// Maximum value for MATCH_L register (32-bit) +const MATCH_L_MAX: u32 = u32::MAX; +/// Maximum value for MATCH_H register (10-bit) +const MATCH_H_MAX: u16 = EVTIMER_HI_MASK; + +/// Bit mask for extracting the low 32 bits from a 64-bit value +const LOW_32_BIT_MASK: u64 = u32::MAX as u64; + +/// Gray code conversion bit shifts (most significant to least) +const GRAY_CONVERSION_SHIFTS: [u32; 6] = [32, 16, 8, 4, 2, 1]; + +/// Maximum timer value before rollover (2^42 - 1 ticks) +/// Actual rollover time depends on the configured clock frequency +const TIMER_MAX_VALUE: u64 = (1u64 << EVTIMER_TOTAL_BITS) - 1; + +/// Threshold for detecting timer rollover in comparisons (1 second at 1MHz) +const TIMER_ROLLOVER_THRESHOLD: u64 = 1_000_000; + +/// Common default interrupt priority for OSTIMER +const DEFAULT_INTERRUPT_PRIORITY: u8 = 3; + +// Global alarm state for interrupt handling +static ALARM_ACTIVE: AtomicBool = AtomicBool::new(false); +static mut ALARM_CALLBACK: Option = None; +static mut ALARM_FLAG: Option<*const AtomicBool> = None; +static mut ALARM_TARGET_TIME: u64 = 0; + +/// Number of tight spin iterations between elapsed time checks while waiting for MATCH writes to return to the idle (0) state. +const MATCH_WRITE_READY_SPINS: usize = 512; +/// Maximum time (in OSTIMER ticks) to wait for MATCH registers to become writable (~5 ms at 1 MHz). +const MATCH_WRITE_READY_TIMEOUT_TICKS: u64 = 5_000; +/// Short stabilization delay executed after toggling the MRCC reset line to let the OSTIMER bus interface settle. +const RESET_STABILIZE_SPINS: usize = 512; + +pub(super) fn wait_for_match_write_ready(r: &Regs) -> bool { + let start = now_ticks_read(); + let mut spin_budget = 0usize; + + loop { + if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() { + return true; + } + + cortex_m::asm::nop(); + spin_budget += 1; + + if spin_budget >= MATCH_WRITE_READY_SPINS { + spin_budget = 0; + + let elapsed = now_ticks_read().wrapping_sub(start); + if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS { + return false; + } + } + } +} + +pub(super) fn wait_for_match_write_complete(r: &Regs) -> bool { + let start = now_ticks_read(); + let mut spin_budget = 0usize; + + loop { + if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() { + return true; + } + + cortex_m::asm::nop(); + spin_budget += 1; + + if spin_budget >= MATCH_WRITE_READY_SPINS { + spin_budget = 0; + + let elapsed = now_ticks_read().wrapping_sub(start); + if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS { + return false; + } + } + } +} + +fn prime_match_registers(r: &Regs) { + // Disable the interrupt, clear any pending flag, then wait until the MATCH registers are writable. + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); + + if wait_for_match_write_ready(r) { + r.match_l().write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) }); + r.match_h().write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) }); + let _ = wait_for_match_write_complete(r); + } +} + +/// Single-shot alarm functionality for OSTIMER +pub struct Alarm<'d> { + /// Whether the alarm is currently active + active: AtomicBool, + /// Callback to execute when alarm expires (optional) + callback: Option, + /// Flag that gets set when alarm expires (optional) + flag: Option<&'d AtomicBool>, + _phantom: core::marker::PhantomData<&'d mut ()>, +} + +impl<'d> Default for Alarm<'d> { + fn default() -> Self { + Self::new() + } +} + +impl<'d> Alarm<'d> { + /// Create a new alarm instance + pub fn new() -> Self { + Self { + active: AtomicBool::new(false), + callback: None, + flag: None, + _phantom: core::marker::PhantomData, + } + } + + /// Set a callback that will be executed when the alarm expires + /// Note: Due to interrupt handler constraints, callbacks must be static function pointers + pub fn with_callback(mut self, callback: fn()) -> Self { + self.callback = Some(callback); + self + } + + /// Set a flag that will be set to true when the alarm expires + pub fn with_flag(mut self, flag: &'d AtomicBool) -> Self { + self.flag = Some(flag); + self + } + + /// Check if the alarm is currently active + pub fn is_active(&self) -> bool { + self.active.load(Ordering::Acquire) + } + + /// Cancel the alarm if it's active + pub fn cancel(&self) { + self.active.store(false, Ordering::Release); + } +} + +/// Configuration for Ostimer::new() +#[derive(Copy, Clone)] +pub struct Config { + /// Initialize MATCH registers to their max values and mask/clear the interrupt flag. + pub init_match_max: bool, + pub power: PoweredClock, + pub source: OstimerClockSel, +} + +impl Default for Config { + fn default() -> Self { + Self { + init_match_max: true, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: OstimerClockSel::Clk1M, + } + } +} + +/// OSTIMER peripheral instance +pub struct Ostimer<'d, I: Instance> { + _inst: core::marker::PhantomData, + clock_frequency_hz: u64, + _phantom: core::marker::PhantomData<&'d mut ()>, +} + +impl<'d, I: Instance> Ostimer<'d, I> { + /// Construct OSTIMER handle. + /// Requires clocks for the instance to be enabled by the board before calling. + /// Does not enable NVIC or INTENA; use time_driver::init() for async operation. + pub fn new(_inst: Peri<'d, I>, cfg: Config) -> Self { + let clock_freq = unsafe { + enable_and_reset::(&OsTimerConfig { + power: cfg.power, + source: cfg.source, + }) + .expect("Enabling OsTimer clock should not fail") + }; + + assert!(clock_freq > 0, "OSTIMER frequency must be greater than 0"); + + if cfg.init_match_max { + let r: &Regs = unsafe { &*I::ptr() }; + // Mask INTENA, clear pending flag, and set MATCH to max so no spurious IRQ fires. + prime_match_registers(r); + } + + Self { + _inst: core::marker::PhantomData, + clock_frequency_hz: clock_freq as u64, + _phantom: core::marker::PhantomData, + } + } + + /// Get the configured clock frequency in Hz + pub fn clock_frequency_hz(&self) -> u64 { + self.clock_frequency_hz + } + + /// Read the current timer counter value in timer ticks + /// + /// # Returns + /// Current timer counter value as a 64-bit unsigned integer + pub fn now(&self) -> u64 { + now_ticks_read() + } + + /// Reset the timer counter to zero + /// + /// This performs a hardware reset of the OSTIMER peripheral, which will reset + /// the counter to zero and clear any pending interrupts. Note that this will + /// affect all timer operations including embassy-time. + /// + /// # Safety + /// This operation will reset the entire OSTIMER peripheral. Any active alarms + /// or time_driver operations will be disrupted. Use with caution. + pub fn reset(&self, _peripherals: &crate::pac::Peripherals) { + critical_section::with(|_| { + let r: &Regs = unsafe { &*I::ptr() }; + + // Mask the peripheral interrupt flag before we toggle the reset line so that + // no new NVIC activity races with the reset sequence. + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); + + unsafe { + assert_reset::(); + + for _ in 0..RESET_STABILIZE_SPINS { + cortex_m::asm::nop(); + } + + release_reset::(); + + while !is_reset_released::() { + cortex_m::asm::nop(); + } + } + + for _ in 0..RESET_STABILIZE_SPINS { + cortex_m::asm::nop(); + } + + // Clear alarm bookkeeping before re-arming MATCH registers. + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + + prime_match_registers(r); + }); + + // Ensure no stale OS_EVENT request remains pending after the reset sequence. + crate::interrupt::OS_EVENT.unpend(); + } + + /// Schedule a single-shot alarm to expire after the specified delay in microseconds + /// + /// # Parameters + /// * `alarm` - The alarm instance to schedule + /// * `delay_us` - Delay in microseconds from now + /// + /// # Returns + /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity + pub fn schedule_alarm_delay(&self, alarm: &Alarm, delay_us: u64) -> bool { + let delay_ticks = (delay_us * self.clock_frequency_hz) / 1_000_000; + let target_time = now_ticks_read() + delay_ticks; + self.schedule_alarm_at(alarm, target_time) + } + + /// Schedule a single-shot alarm to expire at the specified absolute time in timer ticks + /// + /// # Parameters + /// * `alarm` - The alarm instance to schedule + /// * `target_ticks` - Absolute time in timer ticks when the alarm should expire + /// + /// # Returns + /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity + pub fn schedule_alarm_at(&self, alarm: &Alarm, target_ticks: u64) -> bool { + let now = now_ticks_read(); + + // Check if target time is in the past + if target_ticks <= now { + // Execute callback immediately if alarm was supposed to be active + if alarm.active.load(Ordering::Acquire) { + alarm.active.store(false, Ordering::Release); + if let Some(callback) = alarm.callback { + callback(); + } + if let Some(flag) = &alarm.flag { + flag.store(true, Ordering::Release); + } + } + return true; + } + + // Check for timer rollover + let max_future = now + TIMER_MAX_VALUE; + if target_ticks > max_future { + return false; // Would exceed timer capacity + } + + // Program the timer + let r: &Regs = unsafe { &*I::ptr() }; + + critical_section::with(|_| { + // Disable interrupt and clear flag + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); + + if !wait_for_match_write_ready(r) { + prime_match_registers(r); + + if !wait_for_match_write_ready(r) { + alarm.active.store(false, Ordering::Release); + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + return false; + } + } + + // Mark alarm as active now that we know the MATCH registers are writable + alarm.active.store(true, Ordering::Release); + + // Set global alarm state for interrupt handler + ALARM_ACTIVE.store(true, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = target_ticks; + ALARM_CALLBACK = alarm.callback; + ALARM_FLAG = alarm.flag.map(|f| f as *const AtomicBool); + } + + // Program MATCH registers (Gray-coded) + let gray = bin_to_gray(target_ticks); + let l = (gray & LOW_32_BIT_MASK) as u32; + let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16; + + r.match_l().write(|w| unsafe { w.match_value().bits(l) }); + r.match_h().write(|w| unsafe { w.match_value().bits(h) }); + + if !wait_for_match_write_complete(r) { + alarm.active.store(false, Ordering::Release); + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + return false; + } + + let now_after_program = now_ticks_read(); + let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set(); + if now_after_program >= target_ticks && !intrflag_set { + alarm.active.store(false, Ordering::Release); + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { + ALARM_TARGET_TIME = 0; + ALARM_CALLBACK = None; + ALARM_FLAG = None; + } + return false; + } + + // Enable interrupt + r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit()); + + true + }) + } + + /// Cancel any active alarm + pub fn cancel_alarm(&self, alarm: &Alarm) { + critical_section::with(|_| { + alarm.cancel(); + + // Clear global alarm state + ALARM_ACTIVE.store(false, Ordering::Release); + unsafe { ALARM_TARGET_TIME = 0 }; + + // Reset MATCH registers to maximum values to prevent spurious interrupts + let r: &Regs = unsafe { &*I::ptr() }; + prime_match_registers(r); + }); + } + + /// Check if an alarm has expired (call this from your interrupt handler) + /// Returns true if the alarm was active and has now expired + pub fn check_alarm_expired(&self, alarm: &Alarm) -> bool { + if alarm.active.load(Ordering::Acquire) { + alarm.active.store(false, Ordering::Release); + + // Execute callback + if let Some(callback) = alarm.callback { + callback(); + } + + // Set flag + if let Some(flag) = &alarm.flag { + flag.store(true, Ordering::Release); + } + + true + } else { + false + } + } +} + +/// Read current EVTIMER (Gray-coded) and convert to binary ticks. +#[inline(always)] +fn now_ticks_read() -> u64 { + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + + // Read high then low to minimize incoherent snapshots + let hi = (r.evtimerh().read().evtimer_count_value().bits() as u64) & (EVTIMER_HI_MASK as u64); + let lo = r.evtimerl().read().evtimer_count_value().bits() as u64; + // Combine and convert from Gray code to binary + let gray = lo | (hi << EVTIMER_HI_SHIFT); + gray_to_bin(gray) +} + +// Instance trait like other drivers, providing a PAC pointer for this OSTIMER instance +pub trait Instance: Gate + PeripheralType { + fn ptr() -> *const Regs; +} + +#[cfg(not(feature = "time"))] +impl Instance for crate::peripherals::OSTIMER0 { + #[inline(always)] + fn ptr() -> *const Regs { + pac::Ostimer0::ptr() + } +} + +#[inline(always)] +fn bin_to_gray(x: u64) -> u64 { + x ^ (x >> 1) +} + +#[inline(always)] +fn gray_to_bin(gray: u64) -> u64 { + // More efficient iterative conversion using predefined shifts + let mut bin = gray; + for &shift in &GRAY_CONVERSION_SHIFTS { + bin ^= bin >> shift; + } + bin +} + +#[cfg(feature = "time")] +pub mod time_driver { + use core::sync::atomic::Ordering; + use core::task::Waker; + + use embassy_sync::waitqueue::AtomicWaker; + use embassy_time_driver as etd; + + use super::{ + bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, + EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, + }; + use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; + use crate::clocks::{enable_and_reset, PoweredClock}; + use crate::pac; + + #[allow(non_camel_case_types)] + pub(crate) struct _OSTIMER0_TIME_DRIVER { + _x: (), + } + + // #[cfg(feature = "time")] + // impl_cc_gate!(_OSTIMER0_TIME_DRIVER, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); + + impl crate::clocks::Gate for _OSTIMER0_TIME_DRIVER { + type MrccPeriphConfig = crate::clocks::periph_helpers::OsTimerConfig; + + #[inline] + unsafe fn enable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_cc1().modify(|_, w| w.ostimer0().enabled()); + } + + #[inline] + unsafe fn disable_clock() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_cc1().modify(|_r, w| w.ostimer0().disabled()); + } + + #[inline] + fn is_clock_enabled() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_cc1().read().ostimer0().is_enabled() + } + + #[inline] + unsafe fn release_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().enabled()); + } + + #[inline] + unsafe fn assert_reset() { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().disabled()); + } + + #[inline] + fn is_reset_released() -> bool { + let mrcc = unsafe { pac::Mrcc0::steal() }; + mrcc.mrcc_glb_rst1().read().ostimer0().is_enabled() + } + } + + pub struct Driver; + static TIMER_WAKER: AtomicWaker = AtomicWaker::new(); + + impl etd::Driver for Driver { + fn now(&self) -> u64 { + // Use the hardware counter (frequency configured in init) + super::now_ticks_read() + } + + fn schedule_wake(&self, timestamp: u64, waker: &Waker) { + let now = self.now(); + + // If timestamp is in the past or very close to now, wake immediately + if timestamp <= now { + waker.wake_by_ref(); + return; + } + + // Prevent scheduling too far in the future (beyond timer rollover) + // This prevents wraparound issues + let max_future = now + super::TIMER_MAX_VALUE; + if timestamp > max_future { + // For very long timeouts, wake immediately to avoid rollover issues + waker.wake_by_ref(); + return; + } + + // Register the waker first so any immediate wake below is observed by the executor. + TIMER_WAKER.register(waker); + + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + + critical_section::with(|_| { + // Mask INTENA and clear flag + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); + + // Read back to ensure W1C took effect on hardware + let _ = r.osevent_ctrl().read().ostimer_intrflag().bit(); + + if !super::wait_for_match_write_ready(r) { + super::prime_match_registers(r); + + if !super::wait_for_match_write_ready(r) { + // If we can't safely program MATCH, wake immediately and leave INTENA masked. + waker.wake_by_ref(); + return; + } + } + + // Program MATCH (Gray-coded). Write low then high, then fence. + let gray = bin_to_gray(timestamp); + let l = (gray & LOW_32_BIT_MASK) as u32; + + let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16; + + r.match_l().write(|w| unsafe { w.match_value().bits(l) }); + r.match_h().write(|w| unsafe { w.match_value().bits(h) }); + + if !super::wait_for_match_write_complete(r) { + waker.wake_by_ref(); + return; + } + + let now_after_program = super::now_ticks_read(); + let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set(); + if now_after_program >= timestamp && !intrflag_set { + waker.wake_by_ref(); + return; + } + + // Enable peripheral interrupt + r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit()); + }); + } + } + + /// Install the global embassy-time driver and configure NVIC priority for OS_EVENT. + /// + /// # Parameters + /// * `priority` - Interrupt priority for the OSTIMER interrupt + /// * `frequency_hz` - Actual OSTIMER clock frequency in Hz (stored for future use) + /// + /// Note: The frequency parameter is currently accepted for API compatibility. + /// The embassy_time_driver macro handles driver registration automatically. + pub fn init(priority: crate::interrupt::Priority, frequency_hz: u64) { + let _clock_freq = unsafe { + enable_and_reset::<_OSTIMER0_TIME_DRIVER>(&OsTimerConfig { + power: PoweredClock::AlwaysEnabled, + source: OstimerClockSel::Clk1M, + }) + .expect("Enabling OsTimer clock should not fail") + }; + + // Mask/clear at peripheral and set default MATCH + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + super::prime_match_registers(r); + + // Configure NVIC for timer operation + crate::interrupt::OS_EVENT.configure_for_timer(priority); + + // Note: The embassy_time_driver macro automatically registers the driver + // The frequency parameter is accepted for future compatibility + let _ = frequency_hz; // Suppress unused parameter warning + } + + // Export the global time driver expected by embassy-time + embassy_time_driver::time_driver_impl!(static DRIVER: Driver = Driver); + + /// To be called from the OS_EVENT IRQ. + pub fn on_interrupt() { + let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; + + // Critical section to prevent races with schedule_wake + critical_section::with(|_| { + // Check if interrupt is actually pending and handle it atomically + if r.osevent_ctrl().read().ostimer_intrflag().bit_is_set() { + // Clear flag and disable interrupt atomically + r.osevent_ctrl().write(|w| { + w.ostimer_intrflag() + .clear_bit_by_one() // Write-1-to-clear using safe helper + .ostimer_intena() + .clear_bit() + }); + + // Wake the waiting task + TIMER_WAKER.wake(); + + // Handle alarm callback if active and this interrupt is for the alarm + if ALARM_ACTIVE.load(Ordering::SeqCst) { + let current_time = now_ticks_read(); + let target_time = unsafe { ALARM_TARGET_TIME }; + + // Check if current time is close to alarm target time (within 1000 ticks for timing variations) + if current_time >= target_time && current_time <= target_time + 1000 { + ALARM_ACTIVE.store(false, Ordering::SeqCst); + unsafe { ALARM_TARGET_TIME = 0 }; + + // Execute callback if set + unsafe { + if let Some(callback) = ALARM_CALLBACK { + callback(); + } + } + + // Set flag if provided + unsafe { + if let Some(flag) = ALARM_FLAG { + (*flag).store(true, Ordering::SeqCst); + } + } + } + } + } + }); + } +} + +#[cfg(feature = "time")] +use crate::pac::interrupt; + +#[cfg(feature = "time")] +#[allow(non_snake_case)] +#[interrupt] +fn OS_EVENT() { + time_driver::on_interrupt() +} diff --git a/embassy-mcxa/src/pins.rs b/embassy-mcxa/src/pins.rs new file mode 100644 index 000000000..fdf1b0a86 --- /dev/null +++ b/embassy-mcxa/src/pins.rs @@ -0,0 +1,28 @@ +//! Pin configuration helpers (separate from peripheral drivers). +use crate::pac; + +pub unsafe fn configure_adc_pins() { + // P1_10 = ADC1_A8 + let port1 = &*pac::Port1::ptr(); + port1.pcr10().write(|w| { + w.ps() + .ps0() + .pe() + .pe0() + .sre() + .sre0() + .ode() + .ode0() + .dse() + .dse0() + .mux() + .mux0() + .ibe() + .ibe0() + .inv() + .inv0() + .lk() + .lk0() + }); + core::arch::asm!("dsb sy; isb sy"); +} diff --git a/embassy-mcxa/src/rtc.rs b/embassy-mcxa/src/rtc.rs new file mode 100644 index 000000000..f975d9c9f --- /dev/null +++ b/embassy-mcxa/src/rtc.rs @@ -0,0 +1,453 @@ +//! RTC DateTime driver. +use core::marker::PhantomData; + +use embassy_hal_internal::{Peri, PeripheralType}; +use maitake_sync::WaitCell; + +use crate::clocks::with_clocks; +use crate::interrupt::typelevel::{Handler, Interrupt}; +use crate::pac; +use crate::pac::rtc0::cr::Um; + +type Regs = pac::rtc0::RegisterBlock; + +/// Global wait cell for alarm notifications +static WAKER: WaitCell = WaitCell::new(); + +/// RTC interrupt handler. +pub struct InterruptHandler { + _phantom: PhantomData, +} + +/// Trait for RTC peripheral instances +pub trait Instance: PeripheralType { + type Interrupt: Interrupt; + fn ptr() -> *const Regs; +} + +/// Token for RTC0 +pub type Rtc0 = crate::peripherals::RTC0; +impl Instance for crate::peripherals::RTC0 { + type Interrupt = crate::interrupt::typelevel::RTC; + #[inline(always)] + fn ptr() -> *const Regs { + pac::Rtc0::ptr() + } +} + +/// Number of days in a standard year +const DAYS_IN_A_YEAR: u32 = 365; +/// Number of seconds in a day +const SECONDS_IN_A_DAY: u32 = 86400; +/// Number of seconds in an hour +const SECONDS_IN_A_HOUR: u32 = 3600; +/// Number of seconds in a minute +const SECONDS_IN_A_MINUTE: u32 = 60; +/// Unix epoch start year +const YEAR_RANGE_START: u16 = 1970; + +/// Date and time structure for RTC operations +#[derive(Debug, Clone, Copy)] +pub struct RtcDateTime { + pub year: u16, + pub month: u8, + pub day: u8, + pub hour: u8, + pub minute: u8, + pub second: u8, +} +#[derive(Copy, Clone)] +pub struct RtcConfig { + #[allow(dead_code)] + wakeup_select: bool, + update_mode: Um, + #[allow(dead_code)] + supervisor_access: bool, + compensation_interval: u8, + compensation_time: u8, +} + +/// RTC interrupt enable flags +#[derive(Copy, Clone)] +pub struct RtcInterruptEnable; +impl RtcInterruptEnable { + pub const RTC_TIME_INVALID_INTERRUPT_ENABLE: u32 = 1 << 0; + pub const RTC_TIME_OVERFLOW_INTERRUPT_ENABLE: u32 = 1 << 1; + pub const RTC_ALARM_INTERRUPT_ENABLE: u32 = 1 << 2; + pub const RTC_SECONDS_INTERRUPT_ENABLE: u32 = 1 << 4; +} + +/// Converts a DateTime structure to Unix timestamp (seconds since 1970-01-01) +/// +/// # Arguments +/// +/// * `datetime` - The date and time to convert +/// +/// # Returns +/// +/// Unix timestamp as u32 +/// +/// # Note +/// +/// This function handles leap years correctly. +pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 { + let month_days: [u16; 13] = [0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334]; + + let mut seconds = (datetime.year as u32 - 1970) * DAYS_IN_A_YEAR; + seconds += (datetime.year as u32 / 4) - (1970 / 4); + seconds += month_days[datetime.month as usize] as u32; + seconds += datetime.day as u32 - 1; + + if (datetime.year & 3 == 0) && (datetime.month <= 2) { + seconds -= 1; + } + + seconds = seconds * SECONDS_IN_A_DAY + + (datetime.hour as u32 * SECONDS_IN_A_HOUR) + + (datetime.minute as u32 * SECONDS_IN_A_MINUTE) + + datetime.second as u32; + + seconds +} + +/// Converts Unix timestamp to DateTime structure +/// +/// # Arguments +/// +/// * `seconds` - Unix timestamp (seconds since 1970-01-01) +/// +/// # Returns +/// +/// RtcDateTime structure with the converted date and time +/// +/// # Note +/// +/// This function handles leap years correctly. +pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { + let mut seconds_remaining = seconds; + let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1; + seconds_remaining %= SECONDS_IN_A_DAY; + + let hour = (seconds_remaining / SECONDS_IN_A_HOUR) as u8; + seconds_remaining %= SECONDS_IN_A_HOUR; + let minute = (seconds_remaining / SECONDS_IN_A_MINUTE) as u8; + let second = (seconds_remaining % SECONDS_IN_A_MINUTE) as u8; + + let mut year = YEAR_RANGE_START; + let mut days_in_year = DAYS_IN_A_YEAR; + + while days > days_in_year { + days -= days_in_year; + year += 1; + + days_in_year = if year.is_multiple_of(4) { + DAYS_IN_A_YEAR + 1 + } else { + DAYS_IN_A_YEAR + }; + } + + let days_per_month = [ + 31, + if year.is_multiple_of(4) { 29 } else { 28 }, + 31, + 30, + 31, + 30, + 31, + 31, + 30, + 31, + 30, + 31, + ]; + + let mut month = 1; + for (m, month_days) in days_per_month.iter().enumerate() { + let m = m + 1; + if days <= *month_days as u32 { + month = m; + break; + } else { + days -= *month_days as u32; + } + } + + let day = days as u8; + + RtcDateTime { + year, + month: month as u8, + day, + hour, + minute, + second, + } +} + +/// Returns default RTC configuration +/// +/// # Returns +/// +/// RtcConfig with sensible default values: +/// - No wakeup selection +/// - Update mode 0 (immediate updates) +/// - No supervisor access restriction +/// - No compensation +pub fn get_default_config() -> RtcConfig { + RtcConfig { + wakeup_select: false, + update_mode: Um::Um0, + supervisor_access: false, + compensation_interval: 0, + compensation_time: 0, + } +} +/// Minimal RTC handle for a specific instance I (store the zero-sized token like embassy) +pub struct Rtc<'a, I: Instance> { + _inst: core::marker::PhantomData<&'a mut I>, +} + +impl<'a, I: Instance> Rtc<'a, I> { + /// Create a new instance of the real time clock. + pub fn new( + _inst: Peri<'a, I>, + _irq: impl crate::interrupt::typelevel::Binding> + 'a, + config: RtcConfig, + ) -> Self { + let rtc = unsafe { &*I::ptr() }; + + // The RTC is NOT gated by the MRCC, but we DO need to make sure the 16k clock + // on the vsys domain is active + let clocks = with_clocks(|c| c.clk_16k_vsys.clone()); + match clocks { + None => panic!("Clocks have not been initialized"), + Some(None) => panic!("Clocks initialized, but clk_16k_vsys not active"), + Some(Some(_)) => {} + } + + // RTC reset + rtc.cr().modify(|_, w| w.swr().set_bit()); + rtc.cr().modify(|_, w| w.swr().clear_bit()); + rtc.tsr().write(|w| unsafe { w.bits(1) }); + + rtc.cr().modify(|_, w| w.um().variant(config.update_mode)); + + rtc.tcr().modify(|_, w| unsafe { + w.cir() + .bits(config.compensation_interval) + .tcr() + .bits(config.compensation_time) + }); + + // Enable RTC interrupt + I::Interrupt::unpend(); + unsafe { I::Interrupt::enable() }; + + Self { + _inst: core::marker::PhantomData, + } + } + + /// Set the current date and time + /// + /// # Arguments + /// + /// * `datetime` - The date and time to set + /// + /// # Note + /// + /// The datetime is converted to Unix timestamp and written to the time seconds register. + pub fn set_datetime(&self, datetime: RtcDateTime) { + let rtc = unsafe { &*I::ptr() }; + let seconds = convert_datetime_to_seconds(&datetime); + rtc.tsr().write(|w| unsafe { w.bits(seconds) }); + } + + /// Get the current date and time + /// + /// # Returns + /// + /// Current date and time as RtcDateTime + /// + /// # Note + /// + /// Reads the current Unix timestamp from the time seconds register and converts it. + pub fn get_datetime(&self) -> RtcDateTime { + let rtc = unsafe { &*I::ptr() }; + let seconds = rtc.tsr().read().bits(); + convert_seconds_to_datetime(seconds) + } + + /// Set the alarm date and time + /// + /// # Arguments + /// + /// * `alarm` - The date and time when the alarm should trigger + /// + /// # Note + /// + /// This function: + /// - Clears any existing alarm by writing 0 to the alarm register + /// - Waits for the clear operation to complete + /// - Sets the new alarm time + /// - Waits for the write operation to complete + /// - Uses timeouts to prevent infinite loops + /// - Enables the alarm interrupt after setting + pub fn set_alarm(&self, alarm: RtcDateTime) { + let rtc = unsafe { &*I::ptr() }; + let seconds = convert_datetime_to_seconds(&alarm); + + rtc.tar().write(|w| unsafe { w.bits(0) }); + let mut timeout = 10000; + while rtc.tar().read().bits() != 0 && timeout > 0 { + timeout -= 1; + } + + rtc.tar().write(|w| unsafe { w.bits(seconds) }); + + let mut timeout = 10000; + while rtc.tar().read().bits() != seconds && timeout > 0 { + timeout -= 1; + } + + self.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); + } + + /// Get the current alarm date and time + /// + /// # Returns + /// + /// Alarm date and time as RtcDateTime + /// + /// # Note + /// + /// Reads the alarm timestamp from the time alarm register and converts it. + pub fn get_alarm(&self) -> RtcDateTime { + let rtc = unsafe { &*I::ptr() }; + let alarm_seconds = rtc.tar().read().bits(); + convert_seconds_to_datetime(alarm_seconds) + } + + /// Start the RTC time counter + /// + /// # Note + /// + /// Sets the Time Counter Enable (TCE) bit in the status register. + pub fn start(&self) { + let rtc = unsafe { &*I::ptr() }; + rtc.sr().modify(|_, w| w.tce().set_bit()); + } + + /// Stop the RTC time counter + /// + /// # Note + /// + /// Clears the Time Counter Enable (TCE) bit in the status register. + pub fn stop(&self) { + let rtc = unsafe { &*I::ptr() }; + rtc.sr().modify(|_, w| w.tce().clear_bit()); + } + + /// Enable specific RTC interrupts + /// + /// # Arguments + /// + /// * `mask` - Bitmask of interrupts to enable (use RtcInterruptEnable constants) + /// + /// # Note + /// + /// This function enables the specified interrupt types and resets the alarm occurred flag. + /// Available interrupts: + /// - Time Invalid Interrupt + /// - Time Overflow Interrupt + /// - Alarm Interrupt + /// - Seconds Interrupt + pub fn set_interrupt(&self, mask: u32) { + let rtc = unsafe { &*I::ptr() }; + + if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tiie().tiie_1()); + } + if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.toie().toie_1()); + } + if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.taie().taie_1()); + } + if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tsie().tsie_1()); + } + } + + /// Disable specific RTC interrupts + /// + /// # Arguments + /// + /// * `mask` - Bitmask of interrupts to disable (use RtcInterruptEnable constants) + /// + /// # Note + /// + /// This function disables the specified interrupt types. + pub fn disable_interrupt(&self, mask: u32) { + let rtc = unsafe { &*I::ptr() }; + + if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tiie().tiie_0()); + } + if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.toie().toie_0()); + } + if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.taie().taie_0()); + } + if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 { + rtc.ier().modify(|_, w| w.tsie().tsie_0()); + } + } + + /// Clear the alarm interrupt flag + /// + /// # Note + /// + /// This function clears the Time Alarm Interrupt Enable bit. + pub fn clear_alarm_flag(&self) { + let rtc = unsafe { &*I::ptr() }; + rtc.ier().modify(|_, w| w.taie().clear_bit()); + } + + /// Wait for an RTC alarm to trigger. + /// + /// # Arguments + /// + /// * `alarm` - The date and time when the alarm should trigger + /// This function will wait until the RTC alarm is triggered. + /// If no alarm is scheduled, it will wait indefinitely until one is scheduled and triggered. + pub async fn wait_for_alarm(&mut self, alarm: RtcDateTime) { + let wait = WAKER.subscribe().await; + + self.set_alarm(alarm); + self.start(); + + // REVISIT: propagate error? + let _ = wait.await; + + // Clear the interrupt and disable the alarm after waking up + self.disable_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); + } +} + +/// RTC interrupt handler +/// +/// This struct implements the interrupt handler for RTC events. +impl Handler for InterruptHandler { + unsafe fn on_interrupt() { + let rtc = &*pac::Rtc0::ptr(); + // Check if this is actually a time alarm interrupt + let sr = rtc.sr().read(); + if sr.taf().bit_is_set() { + rtc.ier().modify(|_, w| w.taie().clear_bit()); + WAKER.wake(); + } + } +} diff --git a/embassy-mcxa/supply-chain/README.md b/embassy-mcxa/supply-chain/README.md new file mode 100644 index 000000000..12f8777b0 --- /dev/null +++ b/embassy-mcxa/supply-chain/README.md @@ -0,0 +1,149 @@ +# Working with cargo vet + +## Introduction + +`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity. +It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust. +To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet) + +--- + +## Adding a new dependency + +When updating or adding a new dependency, we need to ensure it's audited before being merged into main. +For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository. +_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._ +Follow the process below to ensure compliance: + +### For Developers +1. **Respond to `cargo vet` failures**: + - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire + - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies + +2. **Engage with auditors**: + - Respond to any questions that the auditors might have regarding the need of any new dependencies + +3. **Rebase and verify**: + - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository + - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet` + ```bash + git fetch upstream + git rebase upstream/main + cargo vet + ``` + +4. **Update PR**: + - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR + - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase + ```bash + git push -f + ``` + +5. **Check PR status**: + - The existing PR comment from the previous failure will be updated with a success message once the check passes + +### For Auditors + +1. **Review the questionnaire**: + - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure + - Respond to the developer comment in case more information is needed + +2. **Audit new dependencies**: + - Inspect the `cargo vet` failures using your preferred method + - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked` + - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked` + - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally) + +3. **Follow `cargo vet` recommendations**: + - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies + +4. **Record audits**: + - Use `cargo vet certify` to add new audits to _audits.toml_ + - Verify all dependencies pass using `cargo vet` + +5. **Decide audit location**: + - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) + - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits + +6. **Communicate successful audit**: + - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass + +--- + +## Audit criteria +`cargo vet` comes pre-equipped with two built-in criteria but supports adding new criteria to suit our needs. +As defined [here](https://mozilla.github.io/cargo-vet/built-in-criteria.html), the default criteria are: + +- **safe-to-run** + This crate can be compiled, run, and tested on a local workstation or in + controlled automation without surprising consequences, such as: + * Reading or writing data from sensitive or unrelated parts of the filesystem. + * Installing software or reconfiguring the device. + * Connecting to untrusted network endpoints. + * Misuse of system resources (e.g. cryptocurrency mining). + +- **safe-to-deploy** + This crate will not introduce a serious security vulnerability to production + software exposed to untrusted input. + + Auditors are not required to perform a full logic review of the entire crate. + Rather, they must review enough to fully reason about the behavior of all unsafe + blocks and usage of powerful imports. For any reasonable usage of the crate in + real-world software, an attacker must not be able to manipulate the runtime + behavior of these sections in an exploitable or surprising way. + + Ideally, all unsafe code is fully sound, and ambient capabilities (e.g. + filesystem access) are hardened against manipulation and consistent with the + advertised behavior of the crate. However, some discretion is permitted. In such + cases, the nature of the discretion should be recorded in the `notes` field of + the audit record. + + For crates which generate deployed code (e.g. build dependencies or procedural + macros), reasonable usage of the crate should output code which meets the above + criteria. + + **Note: `safe-to-deploy` implies `safe-to-run`** + +--- + +## Conducting an audit + +When performing an audit for a new or updated dependency, auditors may consider the following criteria to ensure the safety, reliability, and suitability of the crate for use in our projects: + +- **Security**: + - Review the crate for known vulnerabilities or security advisories. + - Check for unsafe code usage and ensure it is justified and well-documented. + - Evaluate the crate’s history of security issues and responsiveness to reported problems. + +- **Maintenance and Activity**: + - Assess the frequency of updates and the responsiveness of maintainers to issues and pull requests. + - Prefer crates that are actively maintained and have a healthy contributor base. + +- **License Compliance**: + - Verify that the crate’s license is compatible with our project’s licensing requirements. + +- **Community Trust and Adoption**: + - Consider the crate’s adoption in the wider Rust ecosystem. + - Prefer crates that are widely used and trusted by the community. + +- **Functionality and Suitability**: + - Confirm that the crate provides the required functionality without unnecessary features or bloat. + - Evaluate whether the crate’s API is stable and unlikely to introduce breaking changes unexpectedly. + +- **Audit Trail**: + - Record the audit decision, including any concerns, mitigations, or recommendations for future updates. + - If exemptions are granted, document the justification and any follow-up actions required. + +--- + +## Tips for using `cargo vet`: + +- **Update _imports.lock_**: + - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project. + +- **Add exemptions**: + - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption ` to add the dependency to exemptions in _config.toml_ + - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions` + +- **Prune unnecessary entries**: + - Remove unnecessary exemptions and imports using `cargo vet prune` \ No newline at end of file diff --git a/embassy-mcxa/supply-chain/audits.toml b/embassy-mcxa/supply-chain/audits.toml new file mode 100644 index 000000000..871109648 --- /dev/null +++ b/embassy-mcxa/supply-chain/audits.toml @@ -0,0 +1,349 @@ + +# cargo-vet audits file + +[[audits.autocfg]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.5.0" + +[[audits.cc]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.2.47" + +[[audits.cfg-if]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.4" + +[[audits.cordyceps]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.3.4" + +[[audits.darling]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.20.11" + +[[audits.darling_core]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.20.11" + +[[audits.darling_macro]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.20.11" + +[[audits.defmt-rtt]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.0" +notes = "defmt-rtt is used for all our logging purposes. Version 1.0.0 merely stabilizes what was already available previously." + +[[audits.defmt-rtt]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 1.1.0" + +[[audits.document-features]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.2.12" + +[[audits.document-features]] +who = "Felipe Balbi " +criteria = "safe-to-run" +version = "0.2.12" + +[[audits.embassy-executor]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.9.1" + +[[audits.embassy-executor-macros]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.7.0" + +[[audits.embassy-executor-timer-queue]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.0" + +[[audits.embassy-executor-timer-queue]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.0" + +[[audits.embassy-time-queue-utils]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.3.0" + +[[audits.find-msvc-tools]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.5" + +[[audits.generator]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.8.7" + +[[audits.ident_case]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.1" + +[[audits.litrs]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.0" + +[[audits.maitake-sync]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.2.2" + +[[audits.mutex-traits]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.1" + +[[audits.mycelium-bitfield]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.5" + +[[audits.once_cell]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.20.1" + +[[audits.panic-probe]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.0" + +[[audits.pin-project]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.1.10" + +[[audits.pin-project-internal]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.1.10" + +[[audits.portable-atomic]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.11.1" + +[[audits.proc-macro2]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.103" + +[[audits.quote]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.42" + +[[audits.stable_deref_trait]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.2.1" + +[[audits.static_cell]] +who = "jerrysxie " +criteria = "safe-to-run" +delta = "2.1.0 -> 2.1.1" + +[[audits.syn]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "2.0.110" + +[[audits.syn]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +delta = "2.0.100 -> 2.0.109" + +[[audits.thiserror]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "2.0.17" + +[[audits.thiserror-impl]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "2.0.17" + +[[audits.unicode-ident]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "1.0.22" + +[[audits.valuable]] +who = "Felipe Balbi " +criteria = "safe-to-deploy" +version = "0.1.1" + +[[trusted.aho-corasick]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-03-28" +end = "2026-11-26" + +[[trusted.cc]] +criteria = "safe-to-deploy" +user-id = 55123 # rust-lang-owner +start = "2022-10-29" +end = "2026-11-26" + +[[trusted.find-msvc-tools]] +criteria = "safe-to-deploy" +user-id = 539 +start = "2025-08-29" +end = "2026-11-26" + +[[trusted.libc]] +criteria = "safe-to-deploy" +user-id = 55123 # rust-lang-owner +start = "2024-08-15" +end = "2026-11-26" + +[[trusted.loom]] +criteria = "safe-to-deploy" +user-id = 6741 # Alice Ryhl (Darksonn) +start = "2021-04-12" +end = "2026-11-26" + +[[trusted.memchr]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-07-07" +end = "2026-11-26" + +[[trusted.paste]] +criteria = "safe-to-deploy" +user-id = 3618 # David Tolnay (dtolnay) +start = "2019-03-19" +end = "2026-11-26" + +[[trusted.regex-automata]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-02-25" +end = "2026-11-26" + +[[trusted.regex-syntax]] +criteria = "safe-to-deploy" +user-id = 189 # Andrew Gallant (BurntSushi) +start = "2019-03-30" +end = "2026-11-26" + +[[trusted.rustversion]] +criteria = "safe-to-deploy" +user-id = 3618 # David Tolnay (dtolnay) +start = "2019-07-08" +end = "2026-11-26" + +[[trusted.scoped-tls]] +criteria = "safe-to-deploy" +user-id = 1 # Alex Crichton (alexcrichton) +start = "2019-02-26" +end = "2026-11-26" + +[[trusted.thread_local]] +criteria = "safe-to-deploy" +user-id = 2915 # Amanieu d'Antras (Amanieu) +start = "2019-09-07" +end = "2026-11-26" + +[[trusted.tracing-subscriber]] +criteria = "safe-to-deploy" +user-id = 10 # Carl Lerche (carllerche) +start = "2025-08-29" +end = "2026-11-26" + +[[trusted.valuable]] +criteria = "safe-to-deploy" +user-id = 10 # Carl Lerche (carllerche) +start = "2022-01-03" +end = "2026-11-26" + +[[trusted.windows]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2021-01-15" +end = "2026-11-26" + +[[trusted.windows-collections]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2025-02-06" +end = "2026-11-26" + +[[trusted.windows-core]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2021-11-15" +end = "2026-11-26" + +[[trusted.windows-future]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2025-02-10" +end = "2026-11-26" + +[[trusted.windows-implement]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2022-01-27" +end = "2026-11-26" + +[[trusted.windows-interface]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2022-02-18" +end = "2026-11-26" + +[[trusted.windows-link]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2024-07-17" +end = "2026-11-26" + +[[trusted.windows-numerics]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2023-05-15" +end = "2026-11-26" + +[[trusted.windows-result]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2024-02-02" +end = "2026-11-26" + +[[trusted.windows-strings]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2024-02-02" +end = "2026-11-26" + +[[trusted.windows-sys]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2021-11-15" +end = "2026-11-26" + +[[trusted.windows-threading]] +criteria = "safe-to-deploy" +user-id = 64539 # Kenny Kerr (kennykerr) +start = "2025-04-29" +end = "2026-11-26" diff --git a/embassy-mcxa/supply-chain/config.toml b/embassy-mcxa/supply-chain/config.toml new file mode 100644 index 000000000..5682db9ea --- /dev/null +++ b/embassy-mcxa/supply-chain/config.toml @@ -0,0 +1,141 @@ + +# cargo-vet config file + +[cargo-vet] +version = "0.10" + +[imports.OpenDevicePartnership] +url = "https://raw.githubusercontent.com/OpenDevicePartnership/rust-crate-audits/main/audits.toml" + +[imports.bytecode-alliance] +url = "https://raw.githubusercontent.com/bytecodealliance/wasmtime/main/supply-chain/audits.toml" + +[imports.google] +url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" + +[imports.mozilla] +url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" + +[[exemptions.bare-metal]] +version = "0.2.5" +criteria = "safe-to-deploy" + +[[exemptions.bitfield]] +version = "0.13.2" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m]] +version = "0.7.7" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m-rt]] +version = "0.7.5" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m-rt-macros]] +version = "0.7.5" +criteria = "safe-to-deploy" + +[[exemptions.critical-section]] +version = "1.2.0" +criteria = "safe-to-deploy" + +[[exemptions.defmt]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.defmt-macros]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.defmt-parser]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-embedded-hal]] +version = "0.5.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-futures]] +version = "0.1.2" +criteria = "safe-to-deploy" + +[[exemptions.embassy-hal-internal]] +version = "0.3.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-sync]] +version = "0.7.2" +criteria = "safe-to-deploy" + +[[exemptions.embassy-time]] +version = "0.5.0" +criteria = "safe-to-deploy" + +[[exemptions.embassy-time-driver]] +version = "0.2.1" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal]] +version = "0.2.7" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal-async]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal-nb]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.embedded-io-async]] +version = "0.6.1" +criteria = "safe-to-deploy" + +[[exemptions.embedded-storage]] +version = "0.3.1" +criteria = "safe-to-deploy" + +[[exemptions.embedded-storage-async]] +version = "0.4.1" +criteria = "safe-to-deploy" + +[[exemptions.hash32]] +version = "0.3.1" +criteria = "safe-to-deploy" + +[[exemptions.heapless]] +version = "0.8.0" +criteria = "safe-to-deploy" + +[[exemptions.proc-macro-error-attr2]] +version = "2.0.0" +criteria = "safe-to-deploy" + +[[exemptions.proc-macro-error2]] +version = "2.0.1" +criteria = "safe-to-deploy" + +[[exemptions.rustc_version]] +version = "0.2.3" +criteria = "safe-to-deploy" + +[[exemptions.semver]] +version = "0.9.0" +criteria = "safe-to-deploy" + +[[exemptions.semver-parser]] +version = "0.7.0" +criteria = "safe-to-deploy" + +[[exemptions.vcell]] +version = "0.1.3" +criteria = "safe-to-deploy" + +[[exemptions.volatile-register]] +version = "0.2.2" +criteria = "safe-to-deploy" diff --git a/embassy-mcxa/supply-chain/imports.lock b/embassy-mcxa/supply-chain/imports.lock new file mode 100644 index 000000000..dbd1235b0 --- /dev/null +++ b/embassy-mcxa/supply-chain/imports.lock @@ -0,0 +1,523 @@ + +# cargo-vet imports lock + +[[publisher.aho-corasick]] +version = "1.1.4" +when = "2025-10-28" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.libc]] +version = "0.2.177" +when = "2025-10-09" +user-id = 55123 +user-login = "rust-lang-owner" + +[[publisher.loom]] +version = "0.7.2" +when = "2024-04-23" +user-id = 6741 +user-login = "Darksonn" +user-name = "Alice Ryhl" + +[[publisher.memchr]] +version = "2.7.6" +when = "2025-09-25" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.paste]] +version = "1.0.15" +when = "2024-05-07" +user-id = 3618 +user-login = "dtolnay" +user-name = "David Tolnay" + +[[publisher.regex-automata]] +version = "0.4.13" +when = "2025-10-13" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.regex-syntax]] +version = "0.8.8" +when = "2025-10-13" +user-id = 189 +user-login = "BurntSushi" +user-name = "Andrew Gallant" + +[[publisher.rustversion]] +version = "1.0.22" +when = "2025-08-08" +user-id = 3618 +user-login = "dtolnay" +user-name = "David Tolnay" + +[[publisher.scoped-tls]] +version = "1.0.1" +when = "2022-10-31" +user-id = 1 +user-login = "alexcrichton" +user-name = "Alex Crichton" + +[[publisher.thread_local]] +version = "1.1.9" +when = "2025-06-12" +user-id = 2915 +user-login = "Amanieu" +user-name = "Amanieu d'Antras" + +[[publisher.tracing-subscriber]] +version = "0.3.20" +when = "2025-08-29" +user-id = 10 +user-login = "carllerche" +user-name = "Carl Lerche" + +[[publisher.windows]] +version = "0.61.3" +when = "2025-06-12" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-collections]] +version = "0.2.0" +when = "2025-03-18" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-core]] +version = "0.61.2" +when = "2025-05-19" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-future]] +version = "0.2.1" +when = "2025-05-15" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-implement]] +version = "0.60.2" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-interface]] +version = "0.59.3" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-link]] +version = "0.1.3" +when = "2025-06-12" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-link]] +version = "0.2.1" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-numerics]] +version = "0.2.0" +when = "2025-03-18" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-result]] +version = "0.3.4" +when = "2025-05-19" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-strings]] +version = "0.4.2" +when = "2025-05-19" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-sys]] +version = "0.61.2" +when = "2025-10-06" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[[publisher.windows-threading]] +version = "0.1.0" +when = "2025-05-15" +user-id = 64539 +user-login = "kennykerr" +user-name = "Kenny Kerr" + +[audits.OpenDevicePartnership.audits] + +[[audits.bytecode-alliance.audits.embedded-io]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "0.4.0" +notes = "No `unsafe` code and only uses `std` in ways one would expect the crate to do so." + +[[audits.bytecode-alliance.audits.embedded-io]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.0 -> 0.6.1" +notes = "Major updates, but almost all safe code. Lots of pruning/deletions, nothing out of the ordrinary." + +[[audits.bytecode-alliance.audits.futures-core]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.3.27" +notes = "Unsafe used to implement a concurrency primitive AtomicWaker. Well-commented and not obviously incorrect. Like my other audits of these concurrency primitives inside the futures family, I couldn't certify that it is correct without formal methods, but that is out of scope for this vetting." + +[[audits.bytecode-alliance.audits.futures-core]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +delta = "0.3.28 -> 0.3.31" + +[[audits.bytecode-alliance.audits.futures-sink]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.3.27" + +[[audits.bytecode-alliance.audits.futures-sink]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +delta = "0.3.28 -> 0.3.31" + +[[audits.bytecode-alliance.audits.log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.22 -> 0.4.27" +notes = "Lots of minor updates to macros and such, nothing touching `unsafe`" + +[[audits.bytecode-alliance.audits.log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.27 -> 0.4.28" +notes = "Minor doc updates and lots new tests, nothing out of the ordinary." + +[[audits.bytecode-alliance.audits.matchers]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.1.0" + +[[audits.bytecode-alliance.audits.matchers]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.0 -> 0.2.0" +notes = "Some unsafe code, but not more than before. Nothing awry." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.46.0" +notes = "one use of unsafe to call windows specific api to get console handle." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.46.0 -> 0.50.1" +notes = "Lots of stylistic/rust-related chanegs, plus new features, but nothing out of the ordrinary." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.50.1 -> 0.50.3" +notes = "CI changes, Rust changes, nothing out of the ordinary." + +[[audits.bytecode-alliance.audits.sharded-slab]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.1.4" +notes = "I always really enjoy reading eliza's code, she left perfect comments at every use of unsafe." + +[[audits.bytecode-alliance.audits.shlex]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "1.1.0" +notes = "Only minor `unsafe` code blocks which look valid and otherwise does what it says on the tin." + +[[audits.bytecode-alliance.audits.tracing-attributes]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.28 -> 0.1.30" +notes = "Few code changes, a pretty minor update." + +[[audits.bytecode-alliance.audits.tracing-core]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.33 -> 0.1.34" +notes = "Mostly just an update with Rust stylistic conventions changing. Nothing awry." + +[[audits.bytecode-alliance.audits.tracing-log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "0.1.3" +notes = """ +This is a standard adapter between the `log` ecosystem and the `tracing` +ecosystem. There's one `unsafe` block in this crate and it's well-scoped. +""" + +[[audits.bytecode-alliance.audits.tracing-log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.3 -> 0.2.0" +notes = "Nothing out of the ordinary, a typical major version update and nothing awry." + +[[audits.google.audits.bitflags]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.3.2" +notes = """ +Security review of earlier versions of the crate can be found at +(Google-internal, sorry): go/image-crate-chromium-security-review + +The crate exposes a function marked as `unsafe`, but doesn't use any +`unsafe` blocks (except for tests of the single `unsafe` function). I +think this justifies marking this crate as `ub-risk-1`. + +Additional review comments can be found at https://crrev.com/c/4723145/31 +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.byteorder]] +who = "danakj " +criteria = "safe-to-deploy" +version = "1.5.0" +notes = "Unsafe review in https://crrev.com/c/5838022" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.lazy_static]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.4.0" +notes = ''' +I grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits. + +There are two places where `unsafe` is used. Unsafe review notes can be found +in https://crrev.com/c/5347418. + +This crate has been added to Chromium in https://crrev.com/c/3321895. +''' +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.lazy_static]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.4.0 -> 1.5.0" +notes = "Unsafe review notes: https://crrev.com/c/5650836" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.log]] +who = "danakj " +criteria = "safe-to-deploy" +version = "0.4.22" +notes = """ +Unsafe review in https://docs.google.com/document/d/1IXQbD1GhTRqNHIGxq6yy7qHqxeO4CwN5noMFXnqyDIM/edit?usp=sharing + +Unsafety is generally very well-documented, with one exception, which we +describe in the review doc. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +version = "1.0.0" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 0.1.3" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 1.1.0" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.num-traits]] +who = "Manish Goregaokar " +criteria = "safe-to-deploy" +version = "0.2.19" +notes = "Contains a single line of float-to-int unsafe with decent safety comments" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.pin-project-lite]] +who = "David Koloski " +criteria = "safe-to-deploy" +version = "0.2.9" +notes = "Reviewed on https://fxrev.dev/824504" +aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.pin-project-lite]] +who = "David Koloski " +criteria = "safe-to-deploy" +delta = "0.2.9 -> 0.2.13" +notes = "Audited at https://fxrev.dev/946396" +aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.smallvec]] +who = "Manish Goregaokar " +criteria = "safe-to-deploy" +version = "1.13.2" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.smallvec]] +who = "Jonathan Hao " +criteria = "safe-to-deploy" +delta = "1.13.2 -> 1.14.0" +notes = """ +WARNING: This certification is a result of a **partial** audit. The +`malloc_size_of` feature has **not** been audited. This feature does +not explicitly document its safety requirements. +See also https://chromium-review.googlesource.com/c/chromium/src/+/6275133/comment/ea0d7a93_98051a2e/ +and https://github.com/servo/malloc_size_of/issues/8. +This feature is banned in gnrt_config.toml. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.void]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +version = "1.0.2" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.mozilla.audits.futures-core]] +who = "Mike Hommey " +criteria = "safe-to-deploy" +delta = "0.3.27 -> 0.3.28" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.futures-sink]] +who = "Mike Hommey " +criteria = "safe-to-deploy" +delta = "0.3.27 -> 0.3.28" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.20.1 -> 1.20.2" +notes = "This update works around a Cargo bug that forces the addition of `portable-atomic` into a lockfile, which we have never needed to use." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.20.2 -> 1.20.3" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.20.3 -> 1.21.1" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.once_cell]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.21.1 -> 1.21.3" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.pin-project-lite]] +who = "Mike Hommey " +criteria = "safe-to-deploy" +delta = "0.2.13 -> 0.2.14" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.pin-project-lite]] +who = "Nika Layzell " +criteria = "safe-to-deploy" +delta = "0.2.14 -> 0.2.16" +notes = """ +Only functional change is to work around a bug in the negative_impls feature +(https://github.com/taiki-e/pin-project/issues/340#issuecomment-2432146009) +""" +aggregated-from = "https://raw.githubusercontent.com/mozilla/cargo-vet/main/supply-chain/audits.toml" + +[[audits.mozilla.audits.sharded-slab]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.4 -> 0.1.7" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.shlex]] +who = "Max Inden " +criteria = "safe-to-deploy" +delta = "1.1.0 -> 1.3.0" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.smallvec]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.14.0 -> 1.15.1" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing]] +who = "Alex Franchuk " +criteria = "safe-to-deploy" +version = "0.1.37" +notes = """ +There's only one unsafe impl, and its purpose is to ensure correct behavior by +creating a non-Send marker type (it has nothing to do with soundness). All +dependencies make sense, and no side-effectful std functions are used. +""" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.37 -> 0.1.41" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-attributes]] +who = "Alex Franchuk " +criteria = "safe-to-deploy" +version = "0.1.24" +notes = "No unsafe code, macros extensively tested and produce reasonable code." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-attributes]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.24 -> 0.1.28" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-core]] +who = "Alex Franchuk " +criteria = "safe-to-deploy" +version = "0.1.30" +notes = """ +Most unsafe code is in implementing non-std sync primitives. Unsafe impls are +logically correct and justified in comments, and unsafe code is sound and +justified in comments. +""" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.tracing-core]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.30 -> 0.1.33" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" diff --git a/embassy-mcxa/tools/run_and_attach_rtt.sh b/embassy-mcxa/tools/run_and_attach_rtt.sh new file mode 100644 index 000000000..13041d06b --- /dev/null +++ b/embassy-mcxa/tools/run_and_attach_rtt.sh @@ -0,0 +1,24 @@ +#!/usr/bin/env bash +set -euo pipefail + +ELF="${1:-target/thumbv8m.main-none-eabihf/debug/examples/hello}" +PROBE_ID="${2:-1fc9:0143:H3AYDQVQMTROB}" +CHIP="${3:-MCXA276}" +SPEED="${4:-1000}" + +# 1) Flash & run using the existing run.sh (probe is in use only during this step) +./run.sh "$ELF" + +# 2) Give target a short moment to boot and set up RTT CB in RAM +sleep 0.5 + +# 3) Attach RTT/defmt using probe-rs (no flashing) +exec probe-rs attach \ + --chip "$CHIP" \ + --probe "$PROBE_ID" \ + --protocol swd \ + --speed "$SPEED" \ + "$ELF" \ + --rtt-scan-memory \ + --log-format oneline + diff --git a/embassy-mcxa/tools/run_jlink_noblock.sh b/embassy-mcxa/tools/run_jlink_noblock.sh new file mode 100644 index 000000000..3ea1f2b4b --- /dev/null +++ b/embassy-mcxa/tools/run_jlink_noblock.sh @@ -0,0 +1,76 @@ +#!/usr/bin/env bash +set -euo pipefail + +ELF="${1:-}" +PROBE_ID="${2:-1366:0101:000600110607}" # default to your J-Link +CHIP="${3:-MCXA276}" +SPEED="${4:-1000}" +PORT="${PROBE_RS_GDB_PORT:-1337}" + +if [[ -z "${ELF}" || ! -f "${ELF}" ]]; then + echo "Usage: $0 [probe-id] [chip] [speed-khz]" >&2 + exit 1 +fi + +if ! command -v probe-rs >/dev/null 2>&1; then + echo "probe-rs not found (cargo install probe-rs --features cli)" >&2 + exit 1 +fi +if ! command -v gdb-multiarch >/dev/null 2>&1; then + echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." >&2 + exit 1 +fi + +# Start probe-rs GDB server +SERVER_LOG=$(mktemp) +probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" --probe "${PROBE_ID}" \ + >"${SERVER_LOG}" 2>&1 & +GDB_SERVER_PID=$! + +# Wait for readiness +for _ in {1..50}; do + if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then break; fi + if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then + echo "probe-rs gdb server failed. Log:" >&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + kill "${GDB_SERVER_PID}" 2>/dev/null || true + exit 1 + fi + sleep 0.1 +done + +# GDB script: load, resume, detach +GDB_SCRIPT=$(mktemp) +cat >"${GDB_SCRIPT}" <&2 + sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true + kill "${GDB_SERVER_PID}" 2>/dev/null || true + exit 1 +fi + +# Stop server now that we've detached +kill "${GDB_SERVER_PID}" 2>/dev/null || true +rm -f "${GDB_SCRIPT}" "${SERVER_LOG}" || true + +echo "Flashed, resumed, and detached (probe free)." + diff --git a/examples/.cargo/config.toml b/examples/.cargo/config.toml deleted file mode 100644 index aedc55b06..000000000 --- a/examples/.cargo/config.toml +++ /dev/null @@ -1,17 +0,0 @@ -[target.thumbv8m.main-none-eabihf] -runner = 'probe-rs run --chip MCXA276 --preverify --verify --protocol swd --speed 12000' - -rustflags = [ - "-C", "linker=flip-link", - "-C", "link-arg=-Tlink.x", - "-C", "link-arg=-Tdefmt.x", - # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x - 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"tap", -] diff --git a/examples/Cargo.toml b/examples/Cargo.toml deleted file mode 100644 index a1092c416..000000000 --- a/examples/Cargo.toml +++ /dev/null @@ -1,26 +0,0 @@ -[package] -name = "embassy-mcxa-examples" -version = "0.1.0" -edition = "2021" -license = "MIT OR Apache-2.0" - -[dependencies] -cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -cortex-m-rt = { version = "0.7", features = ["set-sp", "set-vtor"] } -critical-section = "1.2.0" -defmt = "1.0" -defmt-rtt = "1.0" -embassy-embedded-hal = "0.5.0" -embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } -embassy-mcxa = { path = "../", features = ["defmt", "unstable-pac", "time"] } -embassy-sync = "0.7.2" -embassy-time = "0.5.0" -embassy-time-driver = "0.2.1" -embedded-io-async = "0.6.1" -heapless = "0.9.2" -panic-probe = { version = "1.0", features = ["print-defmt"] } -tmp108 = "0.4.0" - -[profile.release] -lto = true # better optimizations -debug = 2 # enough information for defmt/rtt locations diff --git a/examples/build.rs b/examples/build.rs deleted file mode 100644 index f076bba9f..000000000 --- a/examples/build.rs +++ /dev/null @@ -1,20 +0,0 @@ -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; - -fn main() { - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - - // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH" - // cortex-m-rt expects FLASH for code, RAM for data/bss/stack - // Both are in RAM, but separated to satisfy cortex-m-rt's expectations - // MCXA256 has 128KB RAM total - File::create(out.join("memory.x")) - .unwrap() - .write_all(include_bytes!("memory.x")) - .unwrap(); - - println!("cargo:rustc-link-search={}", out.display()); - println!("cargo:rerun-if-changed=memory.x"); -} diff --git a/examples/memory.x b/examples/memory.x deleted file mode 100644 index 315ced58a..000000000 --- a/examples/memory.x +++ /dev/null @@ -1,5 +0,0 @@ -MEMORY -{ - FLASH : ORIGIN = 0x00000000, LENGTH = 1M - RAM : ORIGIN = 0x20000000, LENGTH = 128K -} diff --git a/examples/src/bin/adc_interrupt.rs b/examples/src/bin/adc_interrupt.rs deleted file mode 100644 index 83d8046b3..000000000 --- a/examples/src/bin/adc_interrupt.rs +++ /dev/null @@ -1,84 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa_examples::init_adc_pins; -use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; -use hal::clocks::periph_helpers::{AdcClockSel, Div4}; -use hal::clocks::PoweredClock; -use hal::pac::adc1::cfg::{Pwrsel, Refsel}; -use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::CalAvgs; -use hal::pac::adc1::tctrl::Tcmd; -use hal::{bind_interrupts, InterruptExt}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!(struct Irqs { - ADC1 => hal::adc::AdcHandler; -}); - -#[used] -#[no_mangle] -static KEEP_ADC: unsafe extern "C" fn() = ADC1; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("ADC interrupt Example"); - - unsafe { - init_adc_pins(); - } - - let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: AdcClockSel::FroLfDiv, - div: Div4::no_div(), - }; - let adc = hal::adc::Adc::::new(p.ADC1, adc_config); - - adc.do_offset_calibration(); - adc.do_auto_calibration(); - - let mut conv_command_config = adc.get_default_conv_command_config(); - conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; - conv_command_config.conversion_resolution_mode = Mode::Data16Bits; - adc.set_conv_command_config(1, &conv_command_config); - - let mut conv_trigger_config = adc.get_default_conv_trigger_config(); - conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; - conv_trigger_config.enable_hardware_trigger = false; - adc.set_conv_trigger_config(0, &conv_trigger_config); - - defmt::info!("ADC configuration done..."); - - adc.enable_interrupt(0x1); - - unsafe { - hal::interrupt::ADC1.enable(); - } - - unsafe { - cortex_m::interrupt::enable(); - } - - loop { - adc.do_software_trigger(1); - while !adc.is_interrupt_triggered() { - // Wait until the interrupt is triggered - } - defmt::info!("*** ADC interrupt TRIGGERED! ***"); - //TBD need to print the value - } -} diff --git a/examples/src/bin/adc_polling.rs b/examples/src/bin/adc_polling.rs deleted file mode 100644 index ddf3f586b..000000000 --- a/examples/src/bin/adc_polling.rs +++ /dev/null @@ -1,68 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa_examples::init_adc_pins; -use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; -use hal::clocks::periph_helpers::{AdcClockSel, Div4}; -use hal::clocks::PoweredClock; -use hal::pac::adc1::cfg::{Pwrsel, Refsel}; -use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::CalAvgs; -use hal::pac::adc1::tctrl::Tcmd; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -const G_LPADC_RESULT_SHIFT: u32 = 0; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - unsafe { - init_adc_pins(); - } - - defmt::info!("=== ADC polling Example ==="); - - let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: AdcClockSel::FroLfDiv, - div: Div4::no_div(), - }; - let adc = hal::adc::Adc::::new(p.ADC1, adc_config); - - adc.do_offset_calibration(); - adc.do_auto_calibration(); - - let mut conv_command_config = adc.get_default_conv_command_config(); - conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; - conv_command_config.conversion_resolution_mode = Mode::Data16Bits; - adc.set_conv_command_config(1, &conv_command_config); - - let mut conv_trigger_config = adc.get_default_conv_trigger_config(); - conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; - conv_trigger_config.enable_hardware_trigger = false; - adc.set_conv_trigger_config(0, &conv_trigger_config); - - defmt::info!("=== ADC configuration done... ==="); - - loop { - adc.do_software_trigger(1); - let mut result: Option = None; - while result.is_none() { - result = hal::adc::get_conv_result(); - } - let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; - defmt::info!("value: {=u16}", value); - } -} diff --git a/examples/src/bin/blinky.rs b/examples/src/bin/blinky.rs deleted file mode 100644 index dd08ec0d9..000000000 --- a/examples/src/bin/blinky.rs +++ /dev/null @@ -1,36 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::gpio::{DriveStrength, Level, Output, SlewRate}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("Blink example"); - - let mut red = Output::new(p.P3_18, Level::High, DriveStrength::Normal, SlewRate::Fast); - let mut green = Output::new(p.P3_19, Level::High, DriveStrength::Normal, SlewRate::Fast); - let mut blue = Output::new(p.P3_21, Level::High, DriveStrength::Normal, SlewRate::Fast); - - loop { - defmt::info!("Toggle LEDs"); - - red.toggle(); - Timer::after_millis(250).await; - - red.toggle(); - green.toggle(); - Timer::after_millis(250).await; - - green.toggle(); - blue.toggle(); - Timer::after_millis(250).await; - blue.toggle(); - - Timer::after_millis(250).await; - } -} diff --git a/examples/src/bin/button.rs b/examples/src/bin/button.rs deleted file mode 100644 index 943edbb15..000000000 --- a/examples/src/bin/button.rs +++ /dev/null @@ -1,23 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::gpio::{Input, Pull}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("Button example"); - - // This button is labeled "WAKEUP" on the FRDM-MCXA276 - // The board already has a 10K pullup - let monitor = Input::new(p.P1_7, Pull::Disabled); - - loop { - defmt::info!("Pin level is {:?}", monitor.get_level()); - Timer::after_millis(1000).await; - } -} diff --git a/examples/src/bin/button_async.rs b/examples/src/bin/button_async.rs deleted file mode 100644 index 6cc7b62cd..000000000 --- a/examples/src/bin/button_async.rs +++ /dev/null @@ -1,29 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::gpio::{Input, Pull}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("GPIO interrupt example"); - - // This button is labeled "WAKEUP" on the FRDM-MCXA276 - // The board already has a 10K pullup - let mut pin = Input::new(p.P1_7, Pull::Disabled); - - let mut press_count = 0u32; - - loop { - pin.wait_for_falling_edge().await; - - press_count += 1; - - defmt::info!("Button pressed! Count: {}", press_count); - Timer::after_millis(50).await; - } -} diff --git a/examples/src/bin/clkout.rs b/examples/src/bin/clkout.rs deleted file mode 100644 index bfd963540..000000000 --- a/examples/src/bin/clkout.rs +++ /dev/null @@ -1,69 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4}; -use embassy_mcxa::clocks::PoweredClock; -use embassy_mcxa::gpio::{DriveStrength, SlewRate}; -use embassy_mcxa::{Level, Output}; -use embassy_time::Timer; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -/// Demonstrate CLKOUT, using Pin P4.2 -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - let mut pin = p.P4_2; - let mut clkout = p.CLKOUT; - - loop { - defmt::info!("Set Low..."); - let mut output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); - Timer::after_millis(500).await; - - defmt::info!("Set High..."); - output.set_high(); - Timer::after_millis(400).await; - - defmt::info!("Set Low..."); - output.set_low(); - Timer::after_millis(500).await; - - defmt::info!("16k..."); - // Run Clock Out with the 16K clock - let _clock_out = ClockOut::new( - clkout.reborrow(), - pin.reborrow(), - Config { - sel: ClockOutSel::Clk16K, - div: Div4::no_div(), - level: PoweredClock::NormalEnabledDeepSleepDisabled, - }, - ) - .unwrap(); - - Timer::after_millis(3000).await; - - defmt::info!("Set Low..."); - drop(_clock_out); - - let _output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); - Timer::after_millis(500).await; - - // Run Clock Out with the 12M clock, divided by 3 - defmt::info!("4M..."); - let _clock_out = ClockOut::new( - clkout.reborrow(), - pin.reborrow(), - Config { - sel: ClockOutSel::Fro12M, - div: const { Div4::from_divisor(3).unwrap() }, - level: PoweredClock::NormalEnabledDeepSleepDisabled, - }, - ) - .unwrap(); - - // Let it run for 3 seconds... - Timer::after_millis(3000).await; - } -} diff --git a/examples/src/bin/hello.rs b/examples/src/bin/hello.rs deleted file mode 100644 index e371d9413..000000000 --- a/examples/src/bin/hello.rs +++ /dev/null @@ -1,119 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::config::Div8; -use hal::lpuart::{Blocking, Config, Lpuart}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -/// Simple helper to write a byte as hex to UART -fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) { - const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; - let _ = uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); - let _ = uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut cfg = hal::config::Config::default(); - cfg.clock_cfg.sirc.fro_12m_enabled = true; - cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); - let p = hal::init(cfg); - - defmt::info!("boot"); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - // Print welcome message before any async delays to guarantee early console output - uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); - uart.write_str_blocking("Available commands:\r\n"); - uart.write_str_blocking(" help - Show this help\r\n"); - uart.write_str_blocking(" echo - Echo back the text\r\n"); - uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); - uart.write_str_blocking("Type a command: "); - - let mut buffer = [0u8; 64]; - let mut buf_idx = 0; - - loop { - // Read a byte from UART - let byte = uart.read_byte_blocking(); - - // Echo the character back - if byte == b'\r' || byte == b'\n' { - // Enter pressed - process command - uart.write_str_blocking("\r\n"); - - if buf_idx > 0 { - let command = &buffer[0..buf_idx]; - - if command == b"help" { - uart.write_str_blocking("Available commands:\r\n"); - uart.write_str_blocking(" help - Show this help\r\n"); - uart.write_str_blocking(" echo - Echo back the text\r\n"); - uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); - } else if command.starts_with(b"echo ") && command.len() > 5 { - uart.write_str_blocking("Echo: "); - uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or("")); - uart.write_str_blocking("\r\n"); - } else if command.starts_with(b"hex ") && command.len() > 4 { - // Parse the byte value - let num_str = &command[4..]; - if let Ok(num) = parse_u8(num_str) { - uart.write_str_blocking("Hex: 0x"); - write_hex_byte(&mut uart, num); - uart.write_str_blocking("\r\n"); - } else { - uart.write_str_blocking("Invalid number for hex command\r\n"); - } - } else if !command.is_empty() { - uart.write_str_blocking("Unknown command: "); - uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); - uart.write_str_blocking("\r\n"); - } - } - - // Reset buffer and prompt - buf_idx = 0; - uart.write_str_blocking("Type a command: "); - } else if byte == 8 || byte == 127 { - // Backspace - if buf_idx > 0 { - buf_idx -= 1; - uart.write_str_blocking("\x08 \x08"); // Erase character - } - } else if buf_idx < buffer.len() - 1 { - // Regular character - buffer[buf_idx] = byte; - buf_idx += 1; - let _ = uart.write_byte(byte); - } - } -} - -/// Simple parser for u8 from ASCII bytes -fn parse_u8(bytes: &[u8]) -> Result { - let mut result = 0u8; - for &b in bytes { - if b.is_ascii_digit() { - result = result.checked_mul(10).ok_or(())?; - result = result.checked_add(b - b'0').ok_or(())?; - } else { - return Err(()); - } - } - Ok(result) -} diff --git a/examples/src/bin/i2c-async.rs b/examples/src/bin/i2c-async.rs deleted file mode 100644 index 47b5f3cbe..000000000 --- a/examples/src/bin/i2c-async.rs +++ /dev/null @@ -1,39 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::bind_interrupts; -use hal::clocks::config::Div8; -use hal::config::Config; -use hal::i2c::controller::{self, I2c, Speed}; -use hal::i2c::InterruptHandler; -use hal::peripherals::LPI2C3; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!( - struct Irqs { - LPI2C3 => InterruptHandler; - } -); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut config = Config::default(); - config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); - - let p = hal::init(config); - - defmt::info!("I2C example"); - - let mut config = controller::Config::default(); - config.speed = Speed::Standard; - let mut i2c = I2c::new_async(p.LPI2C3, p.P3_27, p.P3_28, Irqs, config).unwrap(); - let mut buf = [0u8; 2]; - - loop { - i2c.async_write_read(0x48, &[0x00], &mut buf).await.unwrap(); - defmt::info!("Buffer: {:02x}", buf); - Timer::after_secs(1).await; - } -} diff --git a/examples/src/bin/i2c-blocking.rs b/examples/src/bin/i2c-blocking.rs deleted file mode 100644 index 0f6c8cbae..000000000 --- a/examples/src/bin/i2c-blocking.rs +++ /dev/null @@ -1,31 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::clocks::config::Div8; -use hal::config::Config; -use hal::i2c::controller::{self, I2c, Speed}; -use tmp108::Tmp108; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut config = Config::default(); - config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); - - let p = hal::init(config); - - defmt::info!("I2C example"); - - let mut config = controller::Config::default(); - config.speed = Speed::Standard; - let i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap(); - let mut tmp = Tmp108::new_with_a0_gnd(i2c); - - loop { - let temperature = tmp.temperature().unwrap(); - defmt::info!("Temperature: {}C", temperature); - Timer::after_secs(1).await; - } -} diff --git a/examples/src/bin/i2c-scan-blocking.rs b/examples/src/bin/i2c-scan-blocking.rs deleted file mode 100644 index 4e203597b..000000000 --- a/examples/src/bin/i2c-scan-blocking.rs +++ /dev/null @@ -1,41 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::gpio::Pull; -use embassy_mcxa::Input; -use embassy_time::Timer; -use hal::clocks::config::Div8; -use hal::config::Config; -use hal::i2c::controller::{self, I2c, Speed}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut config = Config::default(); - config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); - - let p = hal::init(config); - - defmt::info!("I2C example"); - - let mut config = controller::Config::default(); - config.speed = Speed::Standard; - - // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and - // defaults to SWO on the debug peripheral. Explicitly make it a high-z - // input. - let _pin = Input::new(p.P0_2, Pull::Disabled); - let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap(); - - for addr in 0x01..=0x7f { - let result = i2c.blocking_write(addr, &[]); - if result.is_ok() { - defmt::info!("Device found at addr {:02x}", addr); - } - } - - loop { - Timer::after_secs(10).await; - } -} diff --git a/examples/src/bin/lpuart_buffered.rs b/examples/src/bin/lpuart_buffered.rs deleted file mode 100644 index 420589d00..000000000 --- a/examples/src/bin/lpuart_buffered.rs +++ /dev/null @@ -1,62 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::lpuart::buffered::BufferedLpuart; -use embassy_mcxa::lpuart::Config; -use embassy_mcxa::{bind_interrupts, lpuart}; -use embedded_io_async::Write; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver -bind_interrupts!(struct Irqs { - LPUART2 => lpuart::buffered::BufferedInterruptHandler::; -}); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut cfg = hal::config::Config::default(); - cfg.clock_cfg.sirc.fro_12m_enabled = true; - cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); - let p = hal::init(cfg); - - // Configure NVIC for LPUART2 - hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); - - // UART configuration (enable both TX and RX) - let config = Config { - baudrate_bps: 115_200, - rx_fifo_watermark: 0, - tx_fifo_watermark: 0, - ..Default::default() - }; - - let mut tx_buf = [0u8; 256]; - let mut rx_buf = [0u8; 256]; - - // Create a buffered LPUART2 instance with both TX and RX - let mut uart = BufferedLpuart::new( - p.LPUART2, - p.P2_2, // TX pin - p.P2_3, // RX pin - Irqs, - &mut tx_buf, - &mut rx_buf, - config, - ) - .unwrap(); - - // Split into TX and RX parts - let (tx, rx) = uart.split_ref(); - - tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); - tx.write(b"Type characters to echo them back.\r\n").await.unwrap(); - - // Echo loop - let mut buf = [0u8; 4]; - loop { - let used = rx.read(&mut buf).await.unwrap(); - tx.write_all(&buf[..used]).await.unwrap(); - } -} diff --git a/examples/src/bin/lpuart_polling.rs b/examples/src/bin/lpuart_polling.rs deleted file mode 100644 index b80668834..000000000 --- a/examples/src/bin/lpuart_polling.rs +++ /dev/null @@ -1,47 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::config::Div8; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -use crate::hal::lpuart::{Config, Lpuart}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut cfg = hal::config::Config::default(); - cfg.clock_cfg.sirc.fro_12m_enabled = true; - cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); - let p = hal::init(cfg); - - defmt::info!("boot"); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - let lpuart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - // Split into separate TX and RX parts - let (mut tx, mut rx) = lpuart.split(); - - // Write hello messages - tx.blocking_write(b"Hello world.\r\n").unwrap(); - tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap(); - - // Echo loop - loop { - let mut buf = [0u8; 1]; - rx.blocking_read(&mut buf).unwrap(); - tx.blocking_write(&buf).unwrap(); - } -} diff --git a/examples/src/bin/rtc_alarm.rs b/examples/src/bin/rtc_alarm.rs deleted file mode 100644 index fe355888b..000000000 --- a/examples/src/bin/rtc_alarm.rs +++ /dev/null @@ -1,47 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::bind_interrupts; -use hal::rtc::{InterruptHandler, Rtc, RtcDateTime}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!(struct Irqs { - RTC => InterruptHandler; -}); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("=== RTC Alarm Example ==="); - - let rtc_config = hal::rtc::get_default_config(); - - let mut rtc = Rtc::new(p.RTC0, Irqs, rtc_config); - - let now = RtcDateTime { - year: 2025, - month: 10, - day: 15, - hour: 14, - minute: 30, - second: 0, - }; - - rtc.stop(); - - defmt::info!("Time set to: 2025-10-15 14:30:00"); - rtc.set_datetime(now); - - let mut alarm = now; - alarm.second += 10; - - defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)"); - defmt::info!("RTC started, waiting for alarm..."); - - rtc.wait_for_alarm(alarm).await; - defmt::info!("*** ALARM TRIGGERED! ***"); - - defmt::info!("Example complete - Test PASSED!"); -} diff --git a/examples/src/lib.rs b/examples/src/lib.rs deleted file mode 100644 index 2573a6adc..000000000 --- a/examples/src/lib.rs +++ /dev/null @@ -1,16 +0,0 @@ -#![no_std] -#![allow(clippy::missing_safety_doc)] - -//! Shared board-specific helpers for the FRDM-MCXA276 examples. -//! These live with the examples so the HAL stays generic. - -use hal::{clocks, pins}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -/// Initialize clocks and pin muxing for ADC. -pub unsafe fn init_adc_pins() { - // NOTE: Lpuart has been updated to properly enable + reset its own clocks. - // GPIO has not. - _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); - pins::configure_adc_pins(); -} diff --git a/ram.ld b/ram.ld deleted file mode 100644 index 816ab6819..000000000 --- a/ram.ld +++ /dev/null @@ -1,109 +0,0 @@ -/* Simple RAM execution linker script for MCXA276 */ -MEMORY -{ - RAM : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* Pull in device default interrupt symbol aliases (e.g., CMC = DefaultHandler) */ -INCLUDE device.x - - -/* Provide core exception weak aliases if not supplied by cortex-m-rt's link.x */ -PROVIDE(NonMaskableInt = DefaultHandler); -PROVIDE(HardFault = DefaultHandler); -PROVIDE(MemoryManagement = DefaultHandler); -PROVIDE(BusFault = DefaultHandler); -PROVIDE(UsageFault = DefaultHandler); -PROVIDE(SecureFault = DefaultHandler); -PROVIDE(SVCall = DefaultHandler); -PROVIDE(DebugMonitor = DefaultHandler); -PROVIDE(PendSV = DefaultHandler); -PROVIDE(SysTick = DefaultHandler); - -/* In RAM-run we have no FLASH sidata; copy from sdata */ -__sidata = __sdata; - -/* Ensure the PAC interrupt table is kept */ -EXTERN(__INTERRUPTS); - - -/* Pull in defmt's linker script to generate the defmt table that host decoders expect */ -INCLUDE defmt.x - -ENTRY(Reset) -EXTERN(VECTOR_TABLE) -EXTERN(Reset) -EXTERN(main) - -/* Define _stack_start at end of RAM BEFORE it's used in vector table */ -_stack_start = ORIGIN(RAM) + LENGTH(RAM); - -SECTIONS -{ - .vector_table ORIGIN(RAM) : - { - /* Slot 0: Initial stack pointer - use our explicitly set _stack_start */ - LONG(_stack_start); - /* Slot 1: Reset vector - address of Reset function with Thumb bit set */ - LONG(Reset | 1); - /* Cortex-M33 core exceptions (slots 2-14) */ - KEEP(*(.vector_table.exceptions)); - /* Peripheral interrupt vectors provided by PAC (slots 16+) */ - KEEP(*(.vector_table.interrupts)); - } > RAM - - .text : - { - KEEP(*(.text.Reset)); - KEEP(*(.text.main)); - *(.text .text.*); - } > RAM - - /* Keep defmt table and fragments so host decoders can find metadata */ - .defmt : - { - KEEP(*(.defmt)); - KEEP(*(.defmt.*)); - } > RAM - - .rodata : - { - *(.rodata .rodata.*); - } > RAM - - .data : - { - . = ALIGN(4); - __sdata = .; - *(.data .data.*); - . = ALIGN(4); - __edata = .; - } > RAM - - /* Ensure RTT control block with "SEGGER RTT" signature is loaded to RAM */ - .rtt : - { - KEEP(*(.rtt)); - } > RAM - - /* Place uninitialized buffers (like defmt-rtt) in RAM; load is fine for RAM-run */ - .uninit : - { - *(.uninit .uninit.*); - } > RAM - - .bss : - { - . = ALIGN(4); - __sbss = .; - *(.bss .bss.*); - . = ALIGN(4); - __ebss = .; - } > RAM - - /* Discard exception unwinding info */ - /DISCARD/ : - { - *(.ARM.exidx .ARM.exidx.*); - } -} diff --git a/run.sh b/run.sh deleted file mode 100644 index 418dc8a24..000000000 --- a/run.sh +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ELF="${1:-}" -if [[ -z "${ELF}" ]]; then - echo "Usage: $0 " - exit 1 -fi -if [[ ! -f "${ELF}" ]]; then - echo "ELF not found: ${ELF}" - exit 1 -fi - -# Configurable via env -CHIP="${CHIP:-MCXA276}" -SPEED="${PROBE_SPEED:-1000}" # kHz -# Default to J-Link if PROBE not provided -PROBE_OPT=(--probe "${PROBE:-1366:0101:000600110607}") -PORT="${PROBE_RS_GDB_PORT:-1337}" - -cleanup() { - if [[ -n "${GDB_SERVER_PID:-}" ]]; then kill "${GDB_SERVER_PID}" 2>/dev/null || true; fi - [[ -n "${GDB_SCRIPT:-}" ]] && rm -f "${GDB_SCRIPT}" || true - [[ -n "${SERVER_LOG:-}" ]] && rm -f "${SERVER_LOG}" || true -} -trap cleanup EXIT - -if ! command -v probe-rs >/dev/null 2>&1; then - echo "probe-rs not found (cargo install probe-rs --features cli)" - exit 1 -fi -if ! command -v gdb-multiarch >/dev/null 2>&1; then - echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." - exit 1 -fi - -# Start probe-rs GDB server and capture its output to a log (do not hide errors) -SERVER_LOG=$(mktemp) -set +e -probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" "${PROBE_OPT[@]}" \ - >"${SERVER_LOG}" 2>&1 & -GDB_SERVER_PID=$! -set -e - -# Wait for server readiness without touching the TCP port to avoid corrupting the GDB protocol -ready="" -for _ in {1..50}; do - if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then ready=1; break; fi - if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then - echo "probe-rs gdb server failed to connect to target. Log:" >&2 - echo "----- probe-rs gdb log -----" >&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - exit 1 - fi - sleep 0.1 -done -if [[ -z "${ready}" ]]; then - echo "probe-rs gdb server did not report readiness. Log:" >&2 - echo "----- probe-rs gdb log -----" >&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - exit 1 -fi - -# GDB script: load to RAM and run, no reset -GDB_SCRIPT=$(mktemp) -cat >"${GDB_SCRIPT}" <&2 - echo "----- probe-rs gdb log -----" >&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - exit 1 -fi - -echo "Program loaded and started (no reset)" diff --git a/rustfmt.toml b/rustfmt.toml deleted file mode 100644 index 9eb3c3b4f..000000000 --- a/rustfmt.toml +++ /dev/null @@ -1,3 +0,0 @@ -group_imports = "StdExternalCrate" -imports_granularity = "Module" -max_width = 120 diff --git a/src/adc.rs b/src/adc.rs deleted file mode 100644 index b5ec5983f..000000000 --- a/src/adc.rs +++ /dev/null @@ -1,409 +0,0 @@ -//! ADC driver -use core::sync::atomic::{AtomicBool, Ordering}; - -use embassy_hal_internal::{Peri, PeripheralType}; - -use crate::clocks::periph_helpers::{AdcClockSel, AdcConfig, Div4}; -use crate::clocks::{enable_and_reset, Gate, PoweredClock}; -use crate::pac; -use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres}; -use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts}; -use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode}; -use crate::pac::adc1::ctrl::CalAvgs; -use crate::pac::adc1::tctrl::{Tcmd, Tpri}; - -type Regs = pac::adc1::RegisterBlock; - -static INTERRUPT_TRIGGERED: AtomicBool = AtomicBool::new(false); -// Token-based instance pattern like embassy-imxrt -pub trait Instance: Gate + PeripheralType { - fn ptr() -> *const Regs; -} - -/// Token for ADC1 -pub type Adc1 = crate::peripherals::ADC1; -impl Instance for crate::peripherals::ADC1 { - #[inline(always)] - fn ptr() -> *const Regs { - pac::Adc1::ptr() - } -} - -// Also implement Instance for the Peri wrapper type -// impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> { -// #[inline(always)] -// fn ptr() -> *const Regs { -// pac::Adc1::ptr() -// } -// } - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[repr(u8)] -pub enum TriggerPriorityPolicy { - ConvPreemptImmediatelyNotAutoResumed = 0, - ConvPreemptSoftlyNotAutoResumed = 1, - ConvPreemptImmediatelyAutoRestarted = 4, - ConvPreemptSoftlyAutoRestarted = 5, - ConvPreemptImmediatelyAutoResumed = 12, - ConvPreemptSoftlyAutoResumed = 13, - ConvPreemptSubsequentlyNotAutoResumed = 2, - ConvPreemptSubsequentlyAutoRestarted = 6, - ConvPreemptSubsequentlyAutoResumed = 14, - TriggerPriorityExceptionDisabled = 16, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub struct LpadcConfig { - pub enable_in_doze_mode: bool, - pub conversion_average_mode: CalAvgs, - pub enable_analog_preliminary: bool, - pub power_up_delay: u8, - pub reference_voltage_source: Refsel, - pub power_level_mode: Pwrsel, - pub trigger_priority_policy: TriggerPriorityPolicy, - pub enable_conv_pause: bool, - pub conv_pause_delay: u16, - pub fifo_watermark: u8, - pub power: PoweredClock, - pub source: AdcClockSel, - pub div: Div4, -} - -impl Default for LpadcConfig { - fn default() -> Self { - LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::NoAverage, - enable_analog_preliminary: false, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option1, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: AdcClockSel::FroLfDiv, - div: Div4::no_div(), - } - } -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub struct ConvCommandConfig { - pub sample_channel_mode: Ctype, - pub channel_number: Adch, - pub chained_next_command_number: Next, - pub enable_auto_channel_increment: bool, - pub loop_count: u8, - pub hardware_average_mode: Avgs, - pub sample_time_mode: Sts, - pub hardware_compare_mode: Cmpen, - pub hardware_compare_value_high: u32, - pub hardware_compare_value_low: u32, - pub conversion_resolution_mode: Mode, - pub enable_wait_trigger: bool, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub struct ConvTriggerConfig { - pub target_command_id: Tcmd, - pub delay_power: u8, - pub priority: Tpri, - pub enable_hardware_trigger: bool, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub struct ConvResult { - pub command_id_source: u32, - pub loop_count_index: u32, - pub trigger_id_source: u32, - pub conv_value: u16, -} - -pub struct Adc<'a, I: Instance> { - _inst: core::marker::PhantomData<&'a mut I>, -} - -impl<'a, I: Instance> Adc<'a, I> { - /// initialize ADC - pub fn new(_inst: Peri<'a, I>, config: LpadcConfig) -> Self { - let adc = unsafe { &*I::ptr() }; - - let _clock_freq = unsafe { - enable_and_reset::(&AdcConfig { - power: config.power, - source: config.source, - div: config.div, - }) - .expect("Adc Init should not fail") - }; - - /* Reset the module. */ - adc.ctrl().modify(|_, w| w.rst().held_in_reset()); - adc.ctrl().modify(|_, w| w.rst().released_from_reset()); - - adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset()); - - /* Disable the module before setting configuration. */ - adc.ctrl().modify(|_, w| w.adcen().disabled()); - - /* Configure the module generally. */ - if config.enable_in_doze_mode { - adc.ctrl().modify(|_, w| w.dozen().enabled()); - } else { - adc.ctrl().modify(|_, w| w.dozen().disabled()); - } - - /* Set calibration average mode. */ - adc.ctrl() - .modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode)); - - adc.cfg().write(|w| unsafe { - let w = if config.enable_analog_preliminary { - w.pwren().pre_enabled() - } else { - w - }; - - w.pudly() - .bits(config.power_up_delay) - .refsel() - .variant(config.reference_voltage_source) - .pwrsel() - .variant(config.power_level_mode) - .tprictrl() - .variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed - | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority, - TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed - | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority, - _ => Tprictrl::AbortCurrentOnPriority, - }) - .tres() - .variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed - | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed - | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled, - _ => Tres::Disabled, - }) - .tcmdres() - .variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed - | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed - | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed - | TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled, - _ => Tcmdres::Disabled, - }) - .hpt_exdi() - .variant(match config.trigger_priority_policy { - TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled, - _ => HptExdi::Enabled, - }) - }); - - if config.enable_conv_pause { - adc.pause() - .modify(|_, w| unsafe { w.pauseen().enabled().pausedly().bits(config.conv_pause_delay) }); - } else { - adc.pause().write(|w| unsafe { w.bits(0) }); - } - - adc.fctrl0() - .write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) }); - - // Enable ADC - adc.ctrl().modify(|_, w| w.adcen().enabled()); - - Self { - _inst: core::marker::PhantomData, - } - } - - pub fn deinit(&self) { - let adc = unsafe { &*I::ptr() }; - adc.ctrl().modify(|_, w| w.adcen().disabled()); - } - - pub fn do_offset_calibration(&self) { - let adc = unsafe { &*I::ptr() }; - // Enable calibration mode - adc.ctrl() - .modify(|_, w| w.calofs().offset_calibration_request_pending()); - - // Wait for calibration to complete (polling status register) - while adc.stat().read().cal_rdy().is_not_set() {} - } - - pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32 { - let mut gcra_array = [0u32; 17]; - let mut gcalr: u32 = 0; - - for i in (1..=17).rev() { - let shift = 16 - (i - 1); - let step = 1.0 / (1u32 << shift) as f32; - let tmp = (gain_adjustment / step) as u32; - gcra_array[i - 1] = tmp; - gain_adjustment -= tmp as f32 * step; - } - - for i in (1..=17).rev() { - gcalr += gcra_array[i - 1] << (i - 1); - } - gcalr - } - - pub fn do_auto_calibration(&self) { - let adc = unsafe { &*I::ptr() }; - adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending()); - - while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} - - let mut gcca = adc.gcc0().read().gain_cal().bits() as u32; - if gcca & ((0xFFFF + 1) >> 1) != 0 { - gcca |= !0xFFFF; - } - - let gcra = 131072.0 / (131072.0 - gcca as f32); - - // Write to GCR0 - adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); - - adc.gcr0().modify(|_, w| w.rdy().set_bit()); - - // Wait for calibration to complete (polling status register) - while adc.stat().read().cal_rdy().is_not_set() {} - } - - pub fn do_software_trigger(&self, trigger_id_mask: u32) { - let adc = unsafe { &*I::ptr() }; - adc.swtrig().write(|w| unsafe { w.bits(trigger_id_mask) }); - } - - pub fn get_default_conv_command_config(&self) -> ConvCommandConfig { - ConvCommandConfig { - sample_channel_mode: Ctype::SingleEndedASideChannel, - channel_number: Adch::SelectCh0, - chained_next_command_number: Next::NoNextCmdTerminateOnFinish, - enable_auto_channel_increment: false, - loop_count: 0, - hardware_average_mode: Avgs::NoAverage, - sample_time_mode: Sts::Sample3p5, - hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult, - hardware_compare_value_high: 0, - hardware_compare_value_low: 0, - conversion_resolution_mode: Mode::Data12Bits, - enable_wait_trigger: false, - } - } - - //TBD Need to add cmdlx and cmdhx with x {2..7} - pub fn set_conv_command_config(&self, index: u32, config: &ConvCommandConfig) { - let adc = unsafe { &*I::ptr() }; - - match index { - 1 => { - adc.cmdl1().write(|w| { - w.adch() - .variant(config.channel_number) - .mode() - .variant(config.conversion_resolution_mode) - }); - adc.cmdh1().write(|w| unsafe { - w.next() - .variant(config.chained_next_command_number) - .loop_() - .bits(config.loop_count) - .avgs() - .variant(config.hardware_average_mode) - .sts() - .variant(config.sample_time_mode) - .cmpen() - .variant(config.hardware_compare_mode); - if config.enable_wait_trigger { - w.wait_trig().enabled(); - } - if config.enable_auto_channel_increment { - w.lwi().enabled(); - } - w - }); - } - _ => panic!("Invalid command index: must be between 1 and 7"), - } - } - - pub fn get_default_conv_trigger_config(&self) -> ConvTriggerConfig { - ConvTriggerConfig { - target_command_id: Tcmd::NotValid, - delay_power: 0, - priority: Tpri::HighestPriority, - enable_hardware_trigger: false, - } - } - - pub fn set_conv_trigger_config(&self, trigger_id: usize, config: &ConvTriggerConfig) { - let adc = unsafe { &*I::ptr() }; - let tctrl = &adc.tctrl(trigger_id); - - tctrl.write(|w| unsafe { - let w = w.tcmd().variant(config.target_command_id); - let w = w.tdly().bits(config.delay_power); - w.tpri().variant(config.priority); - if config.enable_hardware_trigger { - w.hten().enabled() - } else { - w - } - }); - } - - pub fn do_reset_fifo(&self) { - let adc = unsafe { &*I::ptr() }; - adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset()); - } - - pub fn enable_interrupt(&self, mask: u32) { - let adc = unsafe { &*I::ptr() }; - adc.ie().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); - INTERRUPT_TRIGGERED.store(false, Ordering::SeqCst); - } - - pub fn is_interrupt_triggered(&self) -> bool { - INTERRUPT_TRIGGERED.load(Ordering::Relaxed) - } -} - -pub fn get_conv_result() -> Option { - let adc = unsafe { &*pac::Adc1::ptr() }; - let fifo = adc.resfifo0().read().bits(); - const VALID_MASK: u32 = 1 << 31; - if fifo & VALID_MASK == 0 { - return None; - } - - Some(ConvResult { - command_id_source: (fifo >> 24) & 0x0F, - loop_count_index: (fifo >> 20) & 0x0F, - trigger_id_source: (fifo >> 16) & 0x0F, - conv_value: (fifo & 0xFFFF) as u16, - }) -} - -pub fn on_interrupt() { - if get_conv_result().is_some() { - INTERRUPT_TRIGGERED.store(true, Ordering::SeqCst); - } -} - -pub struct AdcHandler; -impl crate::interrupt::typelevel::Handler for AdcHandler { - unsafe fn on_interrupt() { - on_interrupt(); - } -} diff --git a/src/clkout.rs b/src/clkout.rs deleted file mode 100644 index 88c731df1..000000000 --- a/src/clkout.rs +++ /dev/null @@ -1,169 +0,0 @@ -//! CLKOUT pseudo-peripheral -//! -//! CLKOUT is a part of the clock generation subsystem, and can be used -//! either to generate arbitrary waveforms, or to debug the state of -//! internal oscillators. - -use core::marker::PhantomData; - -use embassy_hal_internal::Peri; - -pub use crate::clocks::periph_helpers::Div4; -use crate::clocks::{with_clocks, ClockError, PoweredClock}; -use crate::pac::mrcc0::mrcc_clkout_clksel::Mux; -use crate::peripherals::CLKOUT; - -/// A peripheral representing the CLKOUT pseudo-peripheral -pub struct ClockOut<'a> { - _p: PhantomData<&'a mut CLKOUT>, - freq: u32, -} - -/// Selected clock source to output -pub enum ClockOutSel { - /// 12MHz Internal Oscillator - Fro12M, - /// FRO180M Internal Oscillator, via divisor - FroHfDiv, - /// External Oscillator - ClkIn, - /// 16KHz oscillator - Clk16K, - /// Output of PLL1 - Pll1Clk, - /// Main System CPU clock, divided by 6 - SlowClk, -} - -/// Configuration for the ClockOut -pub struct Config { - /// Selected Source Clock - pub sel: ClockOutSel, - /// Selected division level - pub div: Div4, - /// Selected power level - pub level: PoweredClock, -} - -impl<'a> ClockOut<'a> { - /// Create a new ClockOut pin. On success, the clock signal will begin immediately - /// on the given pin. - pub fn new( - _peri: Peri<'a, CLKOUT>, - pin: Peri<'a, impl sealed::ClockOutPin>, - cfg: Config, - ) -> Result { - // There's no MRCC enable bit, so we check the validity of the clocks here - // - // TODO: Should we check that the frequency is suitably low? - let (freq, mux) = check_sel(cfg.sel, cfg.level)?; - - // All good! Apply requested config, starting with the pin. - pin.mux(); - - setup_clkout(mux, cfg.div); - - Ok(Self { - _p: PhantomData, - freq: freq / cfg.div.into_divisor(), - }) - } - - /// Frequency of the clkout pin - #[inline] - pub fn frequency(&self) -> u32 { - self.freq - } -} - -impl Drop for ClockOut<'_> { - fn drop(&mut self) { - disable_clkout(); - } -} - -/// Check whether the given clock selection is valid -fn check_sel(sel: ClockOutSel, level: PoweredClock) -> Result<(u32, Mux), ClockError> { - let res = with_clocks(|c| { - Ok(match sel { - ClockOutSel::Fro12M => (c.ensure_fro_hf_active(&level)?, Mux::Clkroot12m), - ClockOutSel::FroHfDiv => (c.ensure_fro_hf_div_active(&level)?, Mux::ClkrootFircDiv), - ClockOutSel::ClkIn => (c.ensure_clk_in_active(&level)?, Mux::ClkrootSosc), - ClockOutSel::Clk16K => (c.ensure_clk_16k_vdd_core_active(&level)?, Mux::Clkroot16k), - ClockOutSel::Pll1Clk => (c.ensure_pll1_clk_active(&level)?, Mux::ClkrootSpll), - ClockOutSel::SlowClk => (c.ensure_slow_clk_active(&level)?, Mux::ClkrootSlow), - }) - }); - let Some(res) = res else { - return Err(ClockError::NeverInitialized); - }; - res -} - -/// Set up the clkout pin using the given mux and div settings -fn setup_clkout(mux: Mux, div: Div4) { - let mrcc = unsafe { crate::pac::Mrcc0::steal() }; - - mrcc.mrcc_clkout_clksel().write(|w| w.mux().variant(mux)); - - // Set up clkdiv - mrcc.mrcc_clkout_clkdiv().write(|w| { - w.halt().set_bit(); - w.reset().set_bit(); - unsafe { w.div().bits(div.into_bits()) }; - w - }); - mrcc.mrcc_clkout_clkdiv().write(|w| { - w.halt().clear_bit(); - w.reset().clear_bit(); - unsafe { w.div().bits(div.into_bits()) }; - w - }); - - while mrcc.mrcc_clkout_clkdiv().read().unstab().bit_is_set() {} -} - -/// Stop the clkout -fn disable_clkout() { - // Stop the output by selecting the "none" clock - // - // TODO: restore the pin to hi-z or something? - let mrcc = unsafe { crate::pac::Mrcc0::steal() }; - mrcc.mrcc_clkout_clkdiv().write(|w| { - w.reset().set_bit(); - w.halt().set_bit(); - unsafe { - w.div().bits(0); - } - w - }); - mrcc.mrcc_clkout_clksel().write(|w| unsafe { w.bits(0b111) }); -} - -mod sealed { - use embassy_hal_internal::PeripheralType; - - use crate::gpio::{Pull, SealedPin}; - - /// Sealed marker trait for clockout pins - pub trait ClockOutPin: PeripheralType { - /// Set the given pin to the correct muxing state - fn mux(&self); - } - - macro_rules! impl_pin { - ($pin:ident, $func:ident) => { - impl ClockOutPin for crate::peripherals::$pin { - fn mux(&self) { - self.set_function(crate::pac::port0::pcr0::Mux::$func); - self.set_pull(Pull::Disabled); - } - } - }; - } - - impl_pin!(P0_6, Mux12); - impl_pin!(P3_6, Mux1); - impl_pin!(P3_8, Mux12); - impl_pin!(P4_2, Mux1); -} diff --git a/src/clocks/config.rs b/src/clocks/config.rs deleted file mode 100644 index 0563b8917..000000000 --- a/src/clocks/config.rs +++ /dev/null @@ -1,204 +0,0 @@ -//! Clock Configuration -//! -//! This module holds configuration types used for the system clocks. For -//! configuration of individual peripherals, see [`super::periph_helpers`]. - -use super::PoweredClock; - -/// This type represents a divider in the range 1..=256. -/// -/// At a hardware level, this is an 8-bit register from 0..=255, -/// which adds one. -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub struct Div8(pub(super) u8); - -impl Div8 { - /// Store a "raw" divisor value that will divide the source by - /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source - /// by 1, and `Div8::from_raw(255)` will divide the source by - /// 256. - pub const fn from_raw(n: u8) -> Self { - Self(n) - } - - /// Divide by one, or no division - pub const fn no_div() -> Self { - Self(0) - } - - /// Store a specific divisor value that will divide the source - /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source - /// by 1, and `Div8::from_divisor(256)` will divide the source - /// by 256. - /// - /// Will return `None` if `n` is not in the range `1..=256`. - /// Consider [`Self::from_raw`] for an infallible version. - pub const fn from_divisor(n: u16) -> Option { - let Some(n) = n.checked_sub(1) else { - return None; - }; - if n > (u8::MAX as u16) { - return None; - } - Some(Self(n as u8)) - } - - /// Convert into "raw" bits form - #[inline(always)] - pub const fn into_bits(self) -> u8 { - self.0 - } - - /// Convert into "divisor" form, as a u32 for convenient frequency math - #[inline(always)] - pub const fn into_divisor(self) -> u32 { - self.0 as u32 + 1 - } -} - -/// ```text -/// ┌─────────────────────────────────────────────────────────┐ -/// │ │ -/// │ ┌───────────┐ clk_out ┌─────────┐ │ -/// XTAL ──────┼──▷│ System │───────────▷│ │ clk_in │ -/// │ │ OSC │ clkout_byp │ MUX │──────────────────┼──────▷ -/// EXTAL ──────┼──▷│ │───────────▷│ │ │ -/// │ └───────────┘ └─────────┘ │ -/// │ │ -/// │ ┌───────────┐ fro_hf_root ┌────┐ fro_hf │ -/// │ │ FRO180 ├───────┬─────▷│ CG │─────────────────────┼──────▷ -/// │ │ │ │ ├────┤ clk_45m │ -/// │ │ │ └─────▷│ CG │─────────────────────┼──────▷ -/// │ └───────────┘ └────┘ │ -/// │ ┌───────────┐ fro_12m_root ┌────┐ fro_12m │ -/// │ │ FRO12M │────────┬─────▷│ CG │────────────────────┼──────▷ -/// │ │ │ │ ├────┤ clk_1m │ -/// │ │ │ └─────▷│1/12│────────────────────┼──────▷ -/// │ └───────────┘ └────┘ │ -/// │ │ -/// │ ┌──────────┐ │ -/// │ │000 │ │ -/// │ clk_in │ │ │ -/// │ ───────────────▷│001 │ │ -/// │ fro_12m │ │ │ -/// │ ───────────────▷│010 │ │ -/// │ fro_hf_root │ │ │ -/// │ ───────────────▷│011 │ main_clk │ -/// │ │ │───────────────────────────┼──────▷ -/// clk_16k ──────┼─────────────────▷│100 │ │ -/// │ none │ │ │ -/// │ ───────────────▷│101 │ │ -/// │ pll1_clk │ │ │ -/// │ ───────────────▷│110 │ │ -/// │ none │ │ │ -/// │ ───────────────▷│111 │ │ -/// │ └──────────┘ │ -/// │ ▲ │ -/// │ │ │ -/// │ SCG SCS │ -/// │ SCG-Lite │ -/// └─────────────────────────────────────────────────────────┘ -/// -/// -/// clk_in ┌─────┐ -/// ───────────────▷│00 │ -/// clk_45m │ │ -/// ───────────────▷│01 │ ┌───────────┐ pll1_clk -/// none │ │─────▷│ SPLL │───────────────▷ -/// ───────────────▷│10 │ └───────────┘ -/// fro_12m │ │ -/// ───────────────▷│11 │ -/// └─────┘ -/// ``` -#[non_exhaustive] -pub struct ClocksConfig { - /// FIRC, FRO180, 45/60/90/180M clock source - pub firc: Option, - /// SIRC, FRO12M, clk_12m clock source - // NOTE: I don't think we *can* disable the SIRC? - pub sirc: SircConfig, - /// FRO16K clock source - pub fro16k: Option, -} - -// FIRC/FRO180M - -/// ```text -/// ┌───────────┐ fro_hf_root ┌────┐ fro_hf -/// │ FRO180M ├───────┬─────▷│GATE│──────────▷ -/// │ │ │ ├────┤ clk_45m -/// │ │ └─────▷│GATE│──────────▷ -/// └───────────┘ └────┘ -/// ``` -#[non_exhaustive] -pub struct FircConfig { - /// Selected clock frequency - pub frequency: FircFreqSel, - /// Selected power state of the clock - pub power: PoweredClock, - /// Is the "fro_hf" gated clock enabled? - pub fro_hf_enabled: bool, - /// Is the "clk_45m" gated clock enabled? - pub clk_45m_enabled: bool, - /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`! - pub fro_hf_div: Option, -} - -/// Selected FIRC frequency -pub enum FircFreqSel { - /// 45MHz Output - Mhz45, - /// 60MHz Output - Mhz60, - /// 90MHz Output - Mhz90, - /// 180MHz Output - Mhz180, -} - -// SIRC/FRO12M - -/// ```text -/// ┌───────────┐ fro_12m_root ┌────┐ fro_12m -/// │ FRO12M │────────┬─────▷│ CG │──────────▷ -/// │ │ │ ├────┤ clk_1m -/// │ │ └─────▷│1/12│──────────▷ -/// └───────────┘ └────┘ -/// ``` -#[non_exhaustive] -pub struct SircConfig { - pub power: PoweredClock, - // peripheral output, aka sirc_12mhz - pub fro_12m_enabled: bool, - /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`! - pub fro_lf_div: Option, -} - -#[non_exhaustive] -pub struct Fro16KConfig { - pub vsys_domain_active: bool, - pub vdd_core_domain_active: bool, -} - -impl Default for ClocksConfig { - fn default() -> Self { - Self { - firc: Some(FircConfig { - frequency: FircFreqSel::Mhz45, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - fro_hf_enabled: true, - clk_45m_enabled: true, - fro_hf_div: None, - }), - sirc: SircConfig { - power: PoweredClock::AlwaysEnabled, - fro_12m_enabled: true, - fro_lf_div: None, - }, - fro16k: Some(Fro16KConfig { - vsys_domain_active: true, - vdd_core_domain_active: true, - }), - } - } -} diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs deleted file mode 100644 index 9c9e6ef3d..000000000 --- a/src/clocks/mod.rs +++ /dev/null @@ -1,943 +0,0 @@ -//! # Clock Module -//! -//! For the MCX-A, we separate clock and peripheral control into two main stages: -//! -//! 1. At startup, e.g. when `embassy_mcxa::init()` is called, we configure the -//! core system clocks, including external and internal oscillators. This -//! configuration is then largely static for the duration of the program. -//! 2. When HAL drivers are created, e.g. `Lpuart::new()` is called, the driver -//! is responsible for two main things: -//! * Ensuring that any required "upstream" core system clocks necessary for -//! clocking the peripheral is active and configured to a reasonable value -//! * Enabling the clock gates for that peripheral, and resetting the peripheral -//! -//! From a user perspective, only step 1 is visible. Step 2 is automatically handled -//! by HAL drivers, using interfaces defined in this module. -//! -//! It is also possible to *view* the state of the clock configuration after [`init()`] -//! has been called, using the [`with_clocks()`] function, which provides a view of the -//! [`Clocks`] structure. -//! -//! ## For HAL driver implementors -//! -//! The majority of peripherals in the MCXA chip are fed from either a "hard-coded" or -//! configurable clock source, e.g. selecting the FROM12M or `clk_1m` as a source. This -//! selection, as well as often any pre-scaler division from that source clock, is made -//! through MRCC registers. -//! -//! Any peripheral that is controlled through the MRCC register can automatically implement -//! the necessary APIs using the `impl_cc_gate!` macro in this module. You will also need -//! to define the configuration surface and steps necessary to fully configure that peripheral -//! from a clocks perspective by: -//! -//! 1. Defining a configuration type in the [`periph_helpers`] module that contains any selects -//! or divisions available to the HAL driver -//! 2. Implementing the [`periph_helpers::SPConfHelper`] trait, which should check that the -//! necessary input clocks are reasonable - -use core::cell::RefCell; - -use config::{ClocksConfig, FircConfig, FircFreqSel, Fro16KConfig, SircConfig}; -use mcxa_pac::scg0::firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten}; -use mcxa_pac::scg0::sirccsr::{SircClkPeriphEn, Sircsten}; -use periph_helpers::SPConfHelper; - -use crate::pac; -pub mod config; -pub mod periph_helpers; - -// -// Statics/Consts -// - -/// The state of system core clocks. -/// -/// Initialized by [`init()`], and then unchanged for the remainder of the program. -static CLOCKS: critical_section::Mutex>> = critical_section::Mutex::new(RefCell::new(None)); - -// -// Free functions -// - -/// Initialize the core system clocks with the given [`ClocksConfig`]. -/// -/// This function should be called EXACTLY once at start-up, usually via a -/// call to [`embassy_mcxa::init()`](crate::init()). Subsequent calls will -/// return an error. -pub fn init(settings: ClocksConfig) -> Result<(), ClockError> { - critical_section::with(|cs| { - if CLOCKS.borrow_ref(cs).is_some() { - Err(ClockError::AlreadyInitialized) - } else { - Ok(()) - } - })?; - - let mut clocks = Clocks::default(); - let mut operator = ClockOperator { - clocks: &mut clocks, - config: &settings, - - _mrcc0: unsafe { pac::Mrcc0::steal() }, - scg0: unsafe { pac::Scg0::steal() }, - syscon: unsafe { pac::Syscon::steal() }, - vbat0: unsafe { pac::Vbat0::steal() }, - }; - - operator.configure_firc_clocks()?; - operator.configure_sirc_clocks()?; - operator.configure_fro16k_clocks()?; - - // For now, just use FIRC as the main/cpu clock, which should already be - // the case on reset - assert!(operator.scg0.rccr().read().scs().is_firc()); - let input = operator.clocks.fro_hf_root.clone().unwrap(); - operator.clocks.main_clk = Some(input.clone()); - // We can also assume cpu/system clk == fro_hf because div is /1. - assert_eq!(operator.syscon.ahbclkdiv().read().div().bits(), 0); - operator.clocks.cpu_system_clk = Some(input); - - critical_section::with(|cs| { - let mut clks = CLOCKS.borrow_ref_mut(cs); - assert!(clks.is_none(), "Clock setup race!"); - *clks = Some(clocks); - }); - - Ok(()) -} - -/// Obtain the full clocks structure, calling the given closure in a critical section. -/// -/// The given closure will be called with read-only access to the state of the system -/// clocks. This can be used to query and return the state of a given clock. -/// -/// As the caller's closure will be called in a critical section, care must be taken -/// not to block or cause any other undue delays while accessing. -/// -/// Calls to this function will not succeed until after a successful call to `init()`, -/// and will always return None. -pub fn with_clocks R>(f: F) -> Option { - critical_section::with(|cs| { - let c = CLOCKS.borrow_ref(cs); - let c = c.as_ref()?; - Some(f(c)) - }) -} - -// -// Structs/Enums -// - -/// The `Clocks` structure contains the initialized state of the core system clocks -/// -/// These values are configured by providing [`config::ClocksConfig`] to the [`init()`] function -/// at boot time. -#[derive(Default, Debug, Clone)] -#[non_exhaustive] -pub struct Clocks { - /// The `clk_in` is a clock provided by an external oscillator - pub clk_in: Option, - - // FRO180M stuff - // - /// `fro_hf_root` is the direct output of the `FRO180M` internal oscillator - /// - /// It is used to feed downstream clocks, such as `fro_hf`, `clk_45m`, - /// and `fro_hf_div`. - pub fro_hf_root: Option, - - /// `fro_hf` is the same frequency as `fro_hf_root`, but behind a gate. - pub fro_hf: Option, - - /// `clk_45` is a 45MHz clock, sourced from `fro_hf`. - pub clk_45m: Option, - - /// `fro_hf_div` is a configurable frequency clock, sourced from `fro_hf`. - pub fro_hf_div: Option, - - // - // End FRO180M - - // FRO12M stuff - // - /// `fro_12m_root` is the direct output of the `FRO12M` internal oscillator - /// - /// It is used to feed downstream clocks, such as `fro_12m`, `clk_1m`, - /// `and `fro_lf_div`. - pub fro_12m_root: Option, - - /// `fro_12m` is the same frequency as `fro_12m_root`, but behind a gate. - pub fro_12m: Option, - - /// `clk_1m` is a 1MHz clock, sourced from `fro_12m` - pub clk_1m: Option, - - /// `fro_lf_div` is a configurable frequency clock, sourced from `fro_12m` - pub fro_lf_div: Option, - // - // End FRO12M stuff - /// `clk_16k_vsys` is one of two outputs of the `FRO16K` internal oscillator. - /// - /// Also referred to as `clk_16k[0]` in the datasheet, it feeds peripherals in - /// the system domain, such as the CMP and RTC. - pub clk_16k_vsys: Option, - - /// `clk_16k_vdd_core` is one of two outputs of the `FRO16K` internal oscillator. - /// - /// Also referred to as `clk_16k[1]` in the datasheet, it feeds peripherals in - /// the VDD Core domain, such as the OSTimer or LPUarts. - pub clk_16k_vdd_core: Option, - - /// `main_clk` is the main clock used by the CPU, AHB, APB, IPS bus, and some - /// peripherals. - pub main_clk: Option, - - /// `CPU_CLK` or `SYSTEM_CLK` is the output of `main_clk`, run through the `AHBCLKDIV` - pub cpu_system_clk: Option, - - /// `pll1_clk` is the output of the main system PLL, `pll1`. - pub pll1_clk: Option, -} - -/// `ClockError` is the main error returned when configuring or checking clock state -#[derive(Debug, Copy, Clone, Eq, PartialEq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[non_exhaustive] -pub enum ClockError { - /// The system clocks were never initialized by calling [`init()`] - NeverInitialized, - /// The [`init()`] function was called more than once - AlreadyInitialized, - /// The requested configuration was not possible to fulfill, as the system clocks - /// were not configured in a compatible way - BadConfig { clock: &'static str, reason: &'static str }, - /// The requested configuration was not possible to fulfill, as the required system - /// clocks have not yet been implemented. - NotImplemented { clock: &'static str }, - /// The requested peripheral could not be configured, as the steps necessary to - /// enable it have not yet been implemented. - UnimplementedConfig, -} - -/// Information regarding a system clock -#[derive(Debug, Clone)] -pub struct Clock { - /// The frequency, in Hz, of the given clock - pub frequency: u32, - /// The power state of the clock, e.g. whether it is active in deep sleep mode - /// or not. - pub power: PoweredClock, -} - -/// The power state of a given clock. -/// -/// On the MCX-A, when Deep-Sleep is entered, any clock not configured for Deep Sleep -/// mode will be stopped. This means that any downstream usage, e.g. by peripherals, -/// will also stop. -/// -/// In the future, we will provide an API for entering Deep Sleep, and if there are -/// any peripherals that are NOT using an `AlwaysEnabled` clock active, entry into -/// Deep Sleep will be prevented, in order to avoid misbehaving peripherals. -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub enum PoweredClock { - /// The given clock will NOT continue running in Deep Sleep mode - NormalEnabledDeepSleepDisabled, - /// The given clock WILL continue running in Deep Sleep mode - AlwaysEnabled, -} - -/// The ClockOperator is a private helper type that contains the methods used -/// during system clock initialization. -/// -/// # SAFETY -/// -/// Concurrent access to clock-relevant peripheral registers, such as `MRCC`, `SCG`, -/// `SYSCON`, and `VBAT` should not be allowed for the duration of the [`init()`] function. -struct ClockOperator<'a> { - /// A mutable reference to the current state of system clocks - clocks: &'a mut Clocks, - /// A reference to the requested configuration provided by the caller of [`init()`] - config: &'a ClocksConfig, - - // We hold on to stolen peripherals - _mrcc0: pac::Mrcc0, - scg0: pac::Scg0, - syscon: pac::Syscon, - vbat0: pac::Vbat0, -} - -/// Trait describing an AHB clock gate that can be toggled through MRCC. -pub trait Gate { - type MrccPeriphConfig: SPConfHelper; - - /// Enable the clock gate. - /// - /// # SAFETY - /// - /// The current peripheral must be disabled prior to calling this method - unsafe fn enable_clock(); - - /// Disable the clock gate. - /// - /// # SAFETY - /// - /// There must be no active user of this peripheral when calling this method - unsafe fn disable_clock(); - - /// Drive the peripheral into reset. - /// - /// # SAFETY - /// - /// There must be no active user of this peripheral when calling this method - unsafe fn assert_reset(); - - /// Drive the peripheral out of reset. - /// - /// # SAFETY - /// - /// There must be no active user of this peripheral when calling this method - unsafe fn release_reset(); - - /// Return whether the clock gate for this peripheral is currently enabled. - fn is_clock_enabled() -> bool; - - /// Return whether the peripheral is currently held in reset. - fn is_reset_released() -> bool; -} - -/// This is the primary helper method HAL drivers are expected to call when creating -/// an instance of the peripheral. -/// -/// This method: -/// -/// 1. Enables the MRCC clock gate for this peripheral -/// 2. Calls the `G::MrccPeriphConfig::post_enable_config()` method, returning an error -/// and re-disabling the peripheral if this fails. -/// 3. Pulses the MRCC reset line, to reset the peripheral to the default state -/// 4. Returns the frequency, in Hz that is fed into the peripheral, taking into account -/// the selected upstream clock, as well as any division specified by `cfg`. -/// -/// NOTE: if a clock is disabled, sourced from an "ambient" clock source, this method -/// may return `Ok(0)`. In the future, this might be updated to return the correct -/// "ambient" clock, e.g. the AHB/APB frequency. -/// -/// # SAFETY -/// -/// This peripheral must not yet be in use prior to calling `enable_and_reset`. -#[inline] -pub unsafe fn enable_and_reset(cfg: &G::MrccPeriphConfig) -> Result { - let freq = enable::(cfg).inspect_err(|_| disable::())?; - pulse_reset::(); - Ok(freq) -} - -/// Enable the clock gate for the given peripheral. -/// -/// Prefer [`enable_and_reset`] unless you are specifically avoiding a pulse of the reset, or need -/// to control the duration of the pulse more directly. -/// -/// # SAFETY -/// -/// This peripheral must not yet be in use prior to calling `enable`. -#[inline] -pub unsafe fn enable(cfg: &G::MrccPeriphConfig) -> Result { - G::enable_clock(); - while !G::is_clock_enabled() {} - core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags)); - - let freq = critical_section::with(|cs| { - let clocks = CLOCKS.borrow_ref(cs); - let clocks = clocks.as_ref().ok_or(ClockError::NeverInitialized)?; - cfg.post_enable_config(clocks) - }); - - freq.inspect_err(|_e| { - G::disable_clock(); - }) -} - -/// Disable the clock gate for the given peripheral. -/// -/// # SAFETY -/// -/// This peripheral must no longer be in use prior to calling `enable`. -#[allow(dead_code)] -#[inline] -pub unsafe fn disable() { - G::disable_clock(); -} - -/// Check whether a gate is currently enabled. -#[allow(dead_code)] -#[inline] -pub fn is_clock_enabled() -> bool { - G::is_clock_enabled() -} - -/// Release a reset line for the given peripheral set. -/// -/// Prefer [`enable_and_reset`]. -/// -/// # SAFETY -/// -/// This peripheral must not yet be in use prior to calling `release_reset`. -#[inline] -pub unsafe fn release_reset() { - G::release_reset(); -} - -/// Assert a reset line for the given peripheral set. -/// -/// Prefer [`enable_and_reset`]. -/// -/// # SAFETY -/// -/// This peripheral must not yet be in use prior to calling `assert_reset`. -#[inline] -pub unsafe fn assert_reset() { - G::assert_reset(); -} - -/// Check whether the peripheral is held in reset. -#[inline] -pub unsafe fn is_reset_released() -> bool { - G::is_reset_released() -} - -/// Pulse a reset line (assert then release) with a short delay. -/// -/// Prefer [`enable_and_reset`]. -/// -/// # SAFETY -/// -/// This peripheral must not yet be in use prior to calling `release_reset`. -#[inline] -pub unsafe fn pulse_reset() { - G::assert_reset(); - cortex_m::asm::nop(); - cortex_m::asm::nop(); - G::release_reset(); -} - -// -// `impl`s for structs/enums -// - -/// The [`Clocks`] type's methods generally take the form of "ensure X clock is active". -/// -/// These methods are intended to be used by HAL peripheral implementors to ensure that their -/// selected clocks are active at a suitable level at time of construction. These methods -/// return the frequency of the requested clock, in Hertz, or a [`ClockError`]. -impl Clocks { - /// Ensure the `fro_lf_div` clock is active and valid at the given power state. - pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.fro_lf_div.as_ref() else { - return Err(ClockError::BadConfig { - clock: "fro_lf_div", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "fro_lf_div", - reason: "not low power active", - }); - } - Ok(clk.frequency) - } - - /// Ensure the `fro_hf` clock is active and valid at the given power state. - pub fn ensure_fro_hf_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.fro_hf.as_ref() else { - return Err(ClockError::BadConfig { - clock: "fro_hf", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "fro_hf", - reason: "not low power active", - }); - } - Ok(clk.frequency) - } - - /// Ensure the `fro_hf_div` clock is active and valid at the given power state. - pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.fro_hf_div.as_ref() else { - return Err(ClockError::BadConfig { - clock: "fro_hf_div", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "fro_hf_div", - reason: "not low power active", - }); - } - Ok(clk.frequency) - } - - /// Ensure the `clk_in` clock is active and valid at the given power state. - pub fn ensure_clk_in_active(&self, _at_level: &PoweredClock) -> Result { - Err(ClockError::NotImplemented { clock: "clk_in" }) - } - - /// Ensure the `clk_16k_vsys` clock is active and valid at the given power state. - pub fn ensure_clk_16k_vsys_active(&self, _at_level: &PoweredClock) -> Result { - // NOTE: clk_16k is always active in low power mode - Ok(self - .clk_16k_vsys - .as_ref() - .ok_or(ClockError::BadConfig { - clock: "clk_16k_vsys", - reason: "required but not active", - })? - .frequency) - } - - /// Ensure the `clk_16k_vdd_core` clock is active and valid at the given power state. - pub fn ensure_clk_16k_vdd_core_active(&self, _at_level: &PoweredClock) -> Result { - // NOTE: clk_16k is always active in low power mode - Ok(self - .clk_16k_vdd_core - .as_ref() - .ok_or(ClockError::BadConfig { - clock: "clk_16k_vdd_core", - reason: "required but not active", - })? - .frequency) - } - - /// Ensure the `clk_1m` clock is active and valid at the given power state. - pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.clk_1m.as_ref() else { - return Err(ClockError::BadConfig { - clock: "clk_1m", - reason: "required but not active", - }); - }; - if !clk.power.meets_requirement_of(at_level) { - return Err(ClockError::BadConfig { - clock: "clk_1m", - reason: "not low power active", - }); - } - Ok(clk.frequency) - } - - /// Ensure the `pll1_clk` clock is active and valid at the given power state. - pub fn ensure_pll1_clk_active(&self, _at_level: &PoweredClock) -> Result { - Err(ClockError::NotImplemented { clock: "pll1_clk" }) - } - - /// Ensure the `pll1_clk_div` clock is active and valid at the given power state. - pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result { - Err(ClockError::NotImplemented { clock: "pll1_clk_div" }) - } - - /// Ensure the `CPU_CLK` or `SYSTEM_CLK` is active - pub fn ensure_cpu_system_clk_active(&self, at_level: &PoweredClock) -> Result { - let Some(clk) = self.cpu_system_clk.as_ref() else { - return Err(ClockError::BadConfig { - clock: "cpu_system_clk", - reason: "required but not active", - }); - }; - // Can the main_clk ever be active in deep sleep? I think it is gated? - match at_level { - PoweredClock::NormalEnabledDeepSleepDisabled => {} - PoweredClock::AlwaysEnabled => { - return Err(ClockError::BadConfig { - clock: "main_clk", - reason: "not low power active", - }); - } - } - - Ok(clk.frequency) - } - - pub fn ensure_slow_clk_active(&self, at_level: &PoweredClock) -> Result { - let freq = self.ensure_cpu_system_clk_active(at_level)?; - - Ok(freq / 6) - } -} - -impl PoweredClock { - /// Does THIS clock meet the power requirements of the OTHER clock? - pub fn meets_requirement_of(&self, other: &Self) -> bool { - match (self, other) { - (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::AlwaysEnabled) => false, - (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true, - (PoweredClock::AlwaysEnabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true, - (PoweredClock::AlwaysEnabled, PoweredClock::AlwaysEnabled) => true, - } - } -} - -impl ClockOperator<'_> { - /// Configure the FIRC/FRO180M clock family - /// - /// NOTE: Currently we require this to be a fairly hardcoded value, as this clock is used - /// as the main clock used for the CPU, AHB, APB, etc. - fn configure_firc_clocks(&mut self) -> Result<(), ClockError> { - const HARDCODED_ERR: Result<(), ClockError> = Err(ClockError::BadConfig { - clock: "firc", - reason: "For now, FIRC must be enabled and in default state!", - }); - - // Did the user give us a FIRC config? - let Some(firc) = self.config.firc.as_ref() else { - return HARDCODED_ERR; - }; - // Is the FIRC set to 45MHz (should be reset default) - if !matches!(firc.frequency, FircFreqSel::Mhz45) { - return HARDCODED_ERR; - } - let base_freq = 45_000_000; - - // Now, check if the FIRC as expected for our hardcoded value - let mut firc_ok = true; - - // Is the hardware currently set to the default 45MHz? - // - // NOTE: the SVD currently has the wrong(?) values for these: - // 45 -> 48 - // 60 -> 64 - // 90 -> 96 - // 180 -> 192 - // Probably correct-ish, but for a different trim value? - firc_ok &= self.scg0.firccfg().read().freq_sel().is_firc_48mhz_192s(); - - // Check some values in the CSR - let csr = self.scg0.firccsr().read(); - // Is it enabled? - firc_ok &= csr.fircen().is_enabled(); - // Is it accurate? - firc_ok &= csr.fircacc().is_enabled_and_valid(); - // Is there no error? - firc_ok &= csr.fircerr().is_error_not_detected(); - // Is the FIRC the system clock? - firc_ok &= csr.fircsel().is_firc(); - // Is it valid? - firc_ok &= csr.fircvld().is_enabled_and_valid(); - - // Are we happy with the current (hardcoded) state? - if !firc_ok { - return HARDCODED_ERR; - } - - // Note that the fro_hf_root is active - self.clocks.fro_hf_root = Some(Clock { - frequency: base_freq, - power: firc.power, - }); - - // Okay! Now we're past that, let's enable all the downstream clocks. - let FircConfig { - frequency: _, - power, - fro_hf_enabled, - clk_45m_enabled, - fro_hf_div, - } = firc; - - // When is the FRO enabled? - let pow_set = match power { - PoweredClock::NormalEnabledDeepSleepDisabled => Fircsten::DisabledInStopModes, - PoweredClock::AlwaysEnabled => Fircsten::EnabledInStopModes, - }; - - // Do we enable the `fro_hf` output? - let fro_hf_set = if *fro_hf_enabled { - self.clocks.fro_hf = Some(Clock { - frequency: base_freq, - power: *power, - }); - FircFclkPeriphEn::Enabled - } else { - FircFclkPeriphEn::Disabled - }; - - // Do we enable the `clk_45m` output? - let clk_45m_set = if *clk_45m_enabled { - self.clocks.clk_45m = Some(Clock { - frequency: 45_000_000, - power: *power, - }); - FircSclkPeriphEn::Enabled - } else { - FircSclkPeriphEn::Disabled - }; - - self.scg0.firccsr().modify(|_r, w| { - w.fircsten().variant(pow_set); - w.firc_fclk_periph_en().variant(fro_hf_set); - w.firc_sclk_periph_en().variant(clk_45m_set); - w - }); - - // Do we enable the `fro_hf_div` output? - if let Some(d) = fro_hf_div.as_ref() { - // We need `fro_hf` to be enabled - if !*fro_hf_enabled { - return Err(ClockError::BadConfig { - clock: "fro_hf_div", - reason: "fro_hf not enabled", - }); - } - - // Halt and reset the div; then set our desired div. - self.syscon.frohfdiv().write(|w| { - w.halt().halt(); - w.reset().asserted(); - unsafe { w.div().bits(d.into_bits()) }; - w - }); - // Then unhalt it, and reset it - self.syscon.frohfdiv().write(|w| { - w.halt().run(); - w.reset().released(); - w - }); - - // Wait for clock to stabilize - while self.syscon.frohfdiv().read().unstab().is_ongoing() {} - - // Store off the clock info - self.clocks.fro_hf_div = Some(Clock { - frequency: base_freq / d.into_divisor(), - power: *power, - }); - } - - Ok(()) - } - - /// Configure the SIRC/FRO12M clock family - fn configure_sirc_clocks(&mut self) -> Result<(), ClockError> { - let SircConfig { - power, - fro_12m_enabled, - fro_lf_div, - } = &self.config.sirc; - let base_freq = 12_000_000; - - // Allow writes - self.scg0.sirccsr().modify(|_r, w| w.lk().write_enabled()); - self.clocks.fro_12m_root = Some(Clock { - frequency: base_freq, - power: *power, - }); - - let deep = match power { - PoweredClock::NormalEnabledDeepSleepDisabled => Sircsten::Disabled, - PoweredClock::AlwaysEnabled => Sircsten::Enabled, - }; - let pclk = if *fro_12m_enabled { - self.clocks.fro_12m = Some(Clock { - frequency: base_freq, - power: *power, - }); - self.clocks.clk_1m = Some(Clock { - frequency: base_freq / 12, - power: *power, - }); - SircClkPeriphEn::Enabled - } else { - SircClkPeriphEn::Disabled - }; - - // Set sleep/peripheral usage - self.scg0.sirccsr().modify(|_r, w| { - w.sircsten().variant(deep); - w.sirc_clk_periph_en().variant(pclk); - w - }); - - while self.scg0.sirccsr().read().sircvld().is_disabled_or_not_valid() {} - if self.scg0.sirccsr().read().sircerr().is_error_detected() { - return Err(ClockError::BadConfig { - clock: "sirc", - reason: "error set", - }); - } - - // reset lock - self.scg0.sirccsr().modify(|_r, w| w.lk().write_disabled()); - - // Do we enable the `fro_lf_div` output? - if let Some(d) = fro_lf_div.as_ref() { - // We need `fro_lf` to be enabled - if !*fro_12m_enabled { - return Err(ClockError::BadConfig { - clock: "fro_lf_div", - reason: "fro_12m not enabled", - }); - } - - // Halt and reset the div; then set our desired div. - self.syscon.frolfdiv().write(|w| { - w.halt().halt(); - w.reset().asserted(); - unsafe { w.div().bits(d.into_bits()) }; - w - }); - // Then unhalt it, and reset it - self.syscon.frolfdiv().modify(|_r, w| { - w.halt().run(); - w.reset().released(); - w - }); - - // Wait for clock to stabilize - while self.syscon.frolfdiv().read().unstab().is_ongoing() {} - - // Store off the clock info - self.clocks.fro_lf_div = Some(Clock { - frequency: base_freq / d.into_divisor(), - power: *power, - }); - } - - Ok(()) - } - - /// Configure the FRO16K/clk_16k clock family - fn configure_fro16k_clocks(&mut self) -> Result<(), ClockError> { - let Some(fro16k) = self.config.fro16k.as_ref() else { - return Ok(()); - }; - // Enable FRO16K oscillator - self.vbat0.froctla().modify(|_, w| w.fro_en().set_bit()); - - // Lock the control register - self.vbat0.frolcka().modify(|_, w| w.lock().set_bit()); - - let Fro16KConfig { - vsys_domain_active, - vdd_core_domain_active, - } = fro16k; - - // Enable clock outputs to both VSYS and VDD_CORE domains - // Bit 0: clk_16k0 to VSYS domain - // Bit 1: clk_16k1 to VDD_CORE domain - // - // TODO: Define sub-fields for this register with a PAC patch? - let mut bits = 0; - if *vsys_domain_active { - bits |= 0b01; - self.clocks.clk_16k_vsys = Some(Clock { - frequency: 16_384, - power: PoweredClock::AlwaysEnabled, - }); - } - if *vdd_core_domain_active { - bits |= 0b10; - self.clocks.clk_16k_vdd_core = Some(Clock { - frequency: 16_384, - power: PoweredClock::AlwaysEnabled, - }); - } - self.vbat0.froclke().modify(|_r, w| unsafe { w.clke().bits(bits) }); - - Ok(()) - } -} - -// -// Macros/macro impls -// - -/// This macro is used to implement the [`Gate`] trait for a given peripheral -/// that is controlled by the MRCC peripheral. -macro_rules! impl_cc_gate { - ($name:ident, $clk_reg:ident, $rst_reg:ident, $field:ident, $config:ty) => { - impl Gate for crate::peripherals::$name { - type MrccPeriphConfig = $config; - - #[inline] - unsafe fn enable_clock() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$clk_reg().modify(|_, w| w.$field().enabled()); - } - - #[inline] - unsafe fn disable_clock() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$clk_reg().modify(|_r, w| w.$field().disabled()); - } - - #[inline] - fn is_clock_enabled() -> bool { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$clk_reg().read().$field().is_enabled() - } - - #[inline] - unsafe fn release_reset() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$rst_reg().modify(|_, w| w.$field().enabled()); - } - - #[inline] - unsafe fn assert_reset() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$rst_reg().modify(|_, w| w.$field().disabled()); - } - - #[inline] - fn is_reset_released() -> bool { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.$rst_reg().read().$field().is_enabled() - } - } - }; -} - -/// This module contains implementations of MRCC APIs, specifically of the [`Gate`] trait, -/// for various low level peripherals. -pub(crate) mod gate { - #[cfg(not(feature = "time"))] - use super::periph_helpers::OsTimerConfig; - use super::periph_helpers::{AdcConfig, Lpi2cConfig, LpuartConfig, NoConfig}; - use super::*; - - // These peripherals have no additional upstream clocks or configuration required - // other than enabling through the MRCC gate. Currently, these peripherals will - // ALWAYS return `Ok(0)` when calling [`enable_and_reset()`] and/or - // [`SPConfHelper::post_enable_config()`]. - impl_cc_gate!(PORT0, mrcc_glb_cc1, mrcc_glb_rst1, port0, NoConfig); - impl_cc_gate!(PORT1, mrcc_glb_cc1, mrcc_glb_rst1, port1, NoConfig); - impl_cc_gate!(PORT2, mrcc_glb_cc1, mrcc_glb_rst1, port2, NoConfig); - impl_cc_gate!(PORT3, mrcc_glb_cc1, mrcc_glb_rst1, port3, NoConfig); - impl_cc_gate!(PORT4, mrcc_glb_cc1, mrcc_glb_rst1, port4, NoConfig); - - impl_cc_gate!(GPIO0, mrcc_glb_cc2, mrcc_glb_rst2, gpio0, NoConfig); - impl_cc_gate!(GPIO1, mrcc_glb_cc2, mrcc_glb_rst2, gpio1, NoConfig); - impl_cc_gate!(GPIO2, mrcc_glb_cc2, mrcc_glb_rst2, gpio2, NoConfig); - impl_cc_gate!(GPIO3, mrcc_glb_cc2, mrcc_glb_rst2, gpio3, NoConfig); - impl_cc_gate!(GPIO4, mrcc_glb_cc2, mrcc_glb_rst2, gpio4, NoConfig); - - // These peripherals DO have meaningful configuration, and could fail if the system - // clocks do not match their needs. - #[cfg(not(feature = "time"))] - impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); - - impl_cc_gate!(LPI2C0, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c0, Lpi2cConfig); - impl_cc_gate!(LPI2C1, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c1, Lpi2cConfig); - impl_cc_gate!(LPI2C2, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c2, Lpi2cConfig); - impl_cc_gate!(LPI2C3, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c3, Lpi2cConfig); - - impl_cc_gate!(LPUART0, mrcc_glb_cc0, mrcc_glb_rst0, lpuart0, LpuartConfig); - impl_cc_gate!(LPUART1, mrcc_glb_cc0, mrcc_glb_rst0, lpuart1, LpuartConfig); - impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig); - impl_cc_gate!(LPUART3, mrcc_glb_cc0, mrcc_glb_rst0, lpuart3, LpuartConfig); - impl_cc_gate!(LPUART4, mrcc_glb_cc0, mrcc_glb_rst0, lpuart4, LpuartConfig); - impl_cc_gate!(LPUART5, mrcc_glb_cc1, mrcc_glb_rst1, lpuart5, LpuartConfig); - impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig); -} diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs deleted file mode 100644 index 1ea7a99ed..000000000 --- a/src/clocks/periph_helpers.rs +++ /dev/null @@ -1,502 +0,0 @@ -//! Peripheral Helpers -//! -//! The purpose of this module is to define the per-peripheral special handling -//! required from a clocking perspective. Different peripherals have different -//! selectable source clocks, and some peripherals have additional pre-dividers -//! that can be used. -//! -//! See the docs of [`SPConfHelper`] for more details. - -use super::{ClockError, Clocks, PoweredClock}; -use crate::pac; - -/// Sealed Peripheral Configuration Helper -/// -/// NOTE: the name "sealed" doesn't *totally* make sense because its not sealed yet in the -/// embassy-mcxa project, but it derives from embassy-imxrt where it is. We should -/// fix the name, or actually do the sealing of peripherals. -/// -/// This trait serves to act as a per-peripheral customization for clocking behavior. -/// -/// This trait should be implemented on a configuration type for a given peripheral, and -/// provide the methods that will be called by the higher level operations like -/// `embassy_mcxa::clocks::enable_and_reset()`. -pub trait SPConfHelper { - /// This method is called AFTER a given MRCC peripheral has been enabled (e.g. un-gated), - /// but BEFORE the peripheral reset line is reset. - /// - /// This function should check that any relevant upstream clocks are enabled, are in a - /// reasonable power state, and that the requested configuration can be made. If any of - /// these checks fail, an `Err(ClockError)` should be returned, likely `ClockError::BadConfig`. - /// - /// This function SHOULD NOT make any changes to the system clock configuration, even - /// unsafely, as this should remain static for the duration of the program. - /// - /// This function WILL be called in a critical section, care should be taken not to delay - /// for an unreasonable amount of time. - /// - /// On success, this function MUST return an `Ok(freq)`, where `freq` is the frequency - /// fed into the peripheral, taking into account the selected source clock, as well as - /// any pre-divisors. - fn post_enable_config(&self, clocks: &Clocks) -> Result; -} - -/// Copy and paste macro that: -/// -/// * Sets the clocksel mux to `$selvar` -/// * Resets and halts the div, and applies the calculated div4 bits -/// * Releases reset + halt -/// * Waits for the div to stabilize -/// * Returns `Ok($freq / $conf.div.into_divisor())` -/// -/// Assumes: -/// -/// * self is a configuration struct that has a field called `div`, which -/// is a `Div4` -/// -/// usage: -/// -/// ```rust -/// apply_div4!(self, clksel, clkdiv, variant, freq) -/// ``` -/// -/// In the future if we make all the clksel+clkdiv pairs into commonly derivedFrom -/// registers, or if we put some kind of simple trait around those regs, we could -/// do this with something other than a macro, but for now, this is harm-reduction -/// to avoid incorrect copy + paste -macro_rules! apply_div4 { - ($conf:ident, $selreg:ident, $divreg:ident, $selvar:ident, $freq:ident) => {{ - // set clksel - $selreg.modify(|_r, w| w.mux().variant($selvar)); - - // Set up clkdiv - $divreg.modify(|_r, w| { - unsafe { w.div().bits($conf.div.into_bits()) } - .halt() - .asserted() - .reset() - .asserted() - }); - $divreg.modify(|_r, w| w.halt().deasserted().reset().deasserted()); - - while $divreg.read().unstab().is_unstable() {} - - Ok($freq / $conf.div.into_divisor()) - }}; -} - -// config types - -/// This type represents a divider in the range 1..=16. -/// -/// At a hardware level, this is an 8-bit register from 0..=15, -/// which adds one. -/// -/// While the *clock* domain seems to use 8-bit dividers, the *peripheral* domain -/// seems to use 4 bit dividers! -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub struct Div4(pub(super) u8); - -impl Div4 { - /// Divide by one, or no division - pub const fn no_div() -> Self { - Self(0) - } - - /// Store a "raw" divisor value that will divide the source by - /// `(n + 1)`, e.g. `Div4::from_raw(0)` will divide the source - /// by 1, and `Div4::from_raw(15)` will divide the source by - /// 16. - pub const fn from_raw(n: u8) -> Option { - if n > 0b1111 { - None - } else { - Some(Self(n)) - } - } - - /// Store a specific divisor value that will divide the source - /// by `n`. e.g. `Div4::from_divisor(1)` will divide the source - /// by 1, and `Div4::from_divisor(16)` will divide the source - /// by 16. - /// - /// Will return `None` if `n` is not in the range `1..=16`. - /// Consider [`Self::from_raw`] for an infallible version. - pub const fn from_divisor(n: u8) -> Option { - let Some(n) = n.checked_sub(1) else { - return None; - }; - if n > 0b1111 { - return None; - } - Some(Self(n)) - } - - /// Convert into "raw" bits form - #[inline(always)] - pub const fn into_bits(self) -> u8 { - self.0 - } - - /// Convert into "divisor" form, as a u32 for convenient frequency math - #[inline(always)] - pub const fn into_divisor(self) -> u32 { - self.0 as u32 + 1 - } -} - -/// A basic type that always returns an error when `post_enable_config` is called. -/// -/// Should only be used as a placeholder. -pub struct UnimplementedConfig; - -impl SPConfHelper for UnimplementedConfig { - fn post_enable_config(&self, _clocks: &Clocks) -> Result { - Err(ClockError::UnimplementedConfig) - } -} - -/// A basic type that always returns `Ok(0)` when `post_enable_config` is called. -/// -/// This should only be used for peripherals that are "ambiently" clocked, like `PORTn` -/// peripherals, which have no selectable/configurable source clock. -pub struct NoConfig; -impl SPConfHelper for NoConfig { - fn post_enable_config(&self, _clocks: &Clocks) -> Result { - Ok(0) - } -} - -// -// LPI2c -// - -/// Selectable clocks for `Lpi2c` peripherals -#[derive(Debug, Clone, Copy)] -pub enum Lpi2cClockSel { - /// FRO12M/FRO_LF/SIRC clock source, passed through divider - /// "fro_lf_div" - FroLfDiv, - /// FRO180M/FRO_HF/FIRC clock source, passed through divider - /// "fro_hf_div" - FroHfDiv, - /// SOSC/XTAL/EXTAL clock source - ClkIn, - /// clk_1m/FRO_LF divided by 12 - Clk1M, - /// Output of PLL1, passed through clock divider, - /// "pll1_clk_div", maybe "pll1_lf_div"? - Pll1ClkDiv, - /// Disabled - None, -} - -/// Which instance of the `Lpi2c` is this? -/// -/// Should not be directly selectable by end-users. -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub enum Lpi2cInstance { - /// Instance 0 - Lpi2c0, - /// Instance 1 - Lpi2c1, - /// Instance 2 - Lpi2c2, - /// Instance 3 - Lpi2c3, -} - -/// Top level configuration for `Lpi2c` instances. -pub struct Lpi2cConfig { - /// Power state required for this peripheral - pub power: PoweredClock, - /// Clock source - pub source: Lpi2cClockSel, - /// Clock divisor - pub div: Div4, - /// Which instance is this? - // NOTE: should not be user settable - pub(crate) instance: Lpi2cInstance, -} - -impl SPConfHelper for Lpi2cConfig { - fn post_enable_config(&self, clocks: &Clocks) -> Result { - // check that source is suitable - let mrcc0 = unsafe { pac::Mrcc0::steal() }; - use mcxa_pac::mrcc0::mrcc_lpi2c0_clksel::Mux; - - let (clkdiv, clksel) = match self.instance { - Lpi2cInstance::Lpi2c0 => (mrcc0.mrcc_lpi2c0_clkdiv(), mrcc0.mrcc_lpi2c0_clksel()), - Lpi2cInstance::Lpi2c1 => (mrcc0.mrcc_lpi2c1_clkdiv(), mrcc0.mrcc_lpi2c1_clksel()), - Lpi2cInstance::Lpi2c2 => (mrcc0.mrcc_lpi2c2_clkdiv(), mrcc0.mrcc_lpi2c2_clksel()), - Lpi2cInstance::Lpi2c3 => (mrcc0.mrcc_lpi2c3_clkdiv(), mrcc0.mrcc_lpi2c3_clksel()), - }; - - let (freq, variant) = match self.source { - Lpi2cClockSel::FroLfDiv => { - let freq = clocks.ensure_fro_lf_div_active(&self.power)?; - (freq, Mux::ClkrootFunc0) - } - Lpi2cClockSel::FroHfDiv => { - let freq = clocks.ensure_fro_hf_div_active(&self.power)?; - (freq, Mux::ClkrootFunc2) - } - Lpi2cClockSel::ClkIn => { - let freq = clocks.ensure_clk_in_active(&self.power)?; - (freq, Mux::ClkrootFunc3) - } - Lpi2cClockSel::Clk1M => { - let freq = clocks.ensure_clk_1m_active(&self.power)?; - (freq, Mux::ClkrootFunc5) - } - Lpi2cClockSel::Pll1ClkDiv => { - let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; - (freq, Mux::ClkrootFunc6) - } - Lpi2cClockSel::None => unsafe { - // no ClkrootFunc7, just write manually for now - clksel.write(|w| w.bits(0b111)); - clkdiv.modify(|_r, w| w.reset().asserted().halt().asserted()); - return Ok(0); - }, - }; - - apply_div4!(self, clksel, clkdiv, variant, freq) - } -} - -// -// LPUart -// - -/// Selectable clocks for Lpuart peripherals -#[derive(Debug, Clone, Copy)] -pub enum LpuartClockSel { - /// FRO12M/FRO_LF/SIRC clock source, passed through divider - /// "fro_lf_div" - FroLfDiv, - /// FRO180M/FRO_HF/FIRC clock source, passed through divider - /// "fro_hf_div" - FroHfDiv, - /// SOSC/XTAL/EXTAL clock source - ClkIn, - /// FRO16K/clk_16k source - Clk16K, - /// clk_1m/FRO_LF divided by 12 - Clk1M, - /// Output of PLL1, passed through clock divider, - /// "pll1_clk_div", maybe "pll1_lf_div"? - Pll1ClkDiv, - /// Disabled - None, -} - -/// Which instance of the Lpuart is this? -/// -/// Should not be directly selectable by end-users. -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub enum LpuartInstance { - /// Instance 0 - Lpuart0, - /// Instance 1 - Lpuart1, - /// Instance 2 - Lpuart2, - /// Instance 3 - Lpuart3, - /// Instance 4 - Lpuart4, - /// Instance 5 - Lpuart5, -} - -/// Top level configuration for `Lpuart` instances. -pub struct LpuartConfig { - /// Power state required for this peripheral - pub power: PoweredClock, - /// Clock source - pub source: LpuartClockSel, - /// Clock divisor - pub div: Div4, - /// Which instance is this? - // NOTE: should not be user settable - pub(crate) instance: LpuartInstance, -} - -impl SPConfHelper for LpuartConfig { - fn post_enable_config(&self, clocks: &Clocks) -> Result { - // check that source is suitable - let mrcc0 = unsafe { pac::Mrcc0::steal() }; - use mcxa_pac::mrcc0::mrcc_lpuart0_clksel::Mux; - - let (clkdiv, clksel) = match self.instance { - LpuartInstance::Lpuart0 => (mrcc0.mrcc_lpuart0_clkdiv(), mrcc0.mrcc_lpuart0_clksel()), - LpuartInstance::Lpuart1 => (mrcc0.mrcc_lpuart1_clkdiv(), mrcc0.mrcc_lpuart1_clksel()), - LpuartInstance::Lpuart2 => (mrcc0.mrcc_lpuart2_clkdiv(), mrcc0.mrcc_lpuart2_clksel()), - LpuartInstance::Lpuart3 => (mrcc0.mrcc_lpuart3_clkdiv(), mrcc0.mrcc_lpuart3_clksel()), - LpuartInstance::Lpuart4 => (mrcc0.mrcc_lpuart4_clkdiv(), mrcc0.mrcc_lpuart4_clksel()), - LpuartInstance::Lpuart5 => (mrcc0.mrcc_lpuart5_clkdiv(), mrcc0.mrcc_lpuart5_clksel()), - }; - - let (freq, variant) = match self.source { - LpuartClockSel::FroLfDiv => { - let freq = clocks.ensure_fro_lf_div_active(&self.power)?; - (freq, Mux::ClkrootFunc0) - } - LpuartClockSel::FroHfDiv => { - let freq = clocks.ensure_fro_hf_div_active(&self.power)?; - (freq, Mux::ClkrootFunc2) - } - LpuartClockSel::ClkIn => { - let freq = clocks.ensure_clk_in_active(&self.power)?; - (freq, Mux::ClkrootFunc3) - } - LpuartClockSel::Clk16K => { - let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?; - (freq, Mux::ClkrootFunc4) - } - LpuartClockSel::Clk1M => { - let freq = clocks.ensure_clk_1m_active(&self.power)?; - (freq, Mux::ClkrootFunc5) - } - LpuartClockSel::Pll1ClkDiv => { - let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; - (freq, Mux::ClkrootFunc6) - } - LpuartClockSel::None => unsafe { - // no ClkrootFunc7, just write manually for now - clksel.write(|w| w.bits(0b111)); - clkdiv.modify(|_r, w| { - w.reset().asserted(); - w.halt().asserted(); - w - }); - return Ok(0); - }, - }; - - // set clksel - apply_div4!(self, clksel, clkdiv, variant, freq) - } -} - -// -// OSTimer -// - -/// Selectable clocks for the OSTimer peripheral -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub enum OstimerClockSel { - /// 16k clock, sourced from FRO16K (Vdd Core) - Clk16kVddCore, - /// 1 MHz Clock sourced from FRO12M - Clk1M, - /// Disabled - None, -} - -/// Top level configuration for the `OSTimer` peripheral -pub struct OsTimerConfig { - /// Power state required for this peripheral - pub power: PoweredClock, - /// Selected clock source for this peripheral - pub source: OstimerClockSel, -} - -impl SPConfHelper for OsTimerConfig { - fn post_enable_config(&self, clocks: &Clocks) -> Result { - let mrcc0 = unsafe { pac::Mrcc0::steal() }; - Ok(match self.source { - OstimerClockSel::Clk16kVddCore => { - let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?; - mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_16k()); - freq - } - OstimerClockSel::Clk1M => { - let freq = clocks.ensure_clk_1m_active(&self.power)?; - mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m()); - freq - } - OstimerClockSel::None => { - mrcc0.mrcc_ostimer0_clksel().write(|w| unsafe { w.mux().bits(0b11) }); - 0 - } - }) - } -} - -// -// Adc -// - -/// Selectable clocks for the ADC peripheral -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub enum AdcClockSel { - /// Divided `fro_lf`/`clk_12m`/FRO12M source - FroLfDiv, - /// Gated `fro_hf`/`FRO180M` source - FroHf, - /// External Clock Source - ClkIn, - /// 1MHz clock sourced by a divided `fro_lf`/`clk_12m` - Clk1M, - /// Internal PLL output, with configurable divisor - Pll1ClkDiv, - /// No clock/disabled - None, -} - -/// Top level configuration for the ADC peripheral -pub struct AdcConfig { - /// Power state required for this peripheral - pub power: PoweredClock, - /// Selected clock-source for this peripheral - pub source: AdcClockSel, - /// Pre-divisor, applied to the upstream clock output - pub div: Div4, -} - -impl SPConfHelper for AdcConfig { - fn post_enable_config(&self, clocks: &Clocks) -> Result { - use mcxa_pac::mrcc0::mrcc_adc_clksel::Mux; - let mrcc0 = unsafe { pac::Mrcc0::steal() }; - let (freq, variant) = match self.source { - AdcClockSel::FroLfDiv => { - let freq = clocks.ensure_fro_lf_div_active(&self.power)?; - (freq, Mux::ClkrootFunc0) - } - AdcClockSel::FroHf => { - let freq = clocks.ensure_fro_hf_active(&self.power)?; - (freq, Mux::ClkrootFunc1) - } - AdcClockSel::ClkIn => { - let freq = clocks.ensure_clk_in_active(&self.power)?; - (freq, Mux::ClkrootFunc3) - } - AdcClockSel::Clk1M => { - let freq = clocks.ensure_clk_1m_active(&self.power)?; - (freq, Mux::ClkrootFunc5) - } - AdcClockSel::Pll1ClkDiv => { - let freq = clocks.ensure_pll1_clk_div_active(&self.power)?; - (freq, Mux::ClkrootFunc6) - } - AdcClockSel::None => { - mrcc0.mrcc_adc_clksel().write(|w| unsafe { - // no ClkrootFunc7, just write manually for now - w.mux().bits(0b111) - }); - mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { - w.reset().asserted(); - w.halt().asserted(); - w - }); - return Ok(0); - } - }; - let clksel = mrcc0.mrcc_adc_clksel(); - let clkdiv = mrcc0.mrcc_adc_clkdiv(); - - apply_div4!(self, clksel, clkdiv, variant, freq) - } -} diff --git a/src/config.rs b/src/config.rs deleted file mode 100644 index 8d52a1d44..000000000 --- a/src/config.rs +++ /dev/null @@ -1,27 +0,0 @@ -// HAL configuration (minimal), mirroring embassy-imxrt style - -use crate::clocks::config::ClocksConfig; -use crate::interrupt::Priority; - -#[non_exhaustive] -pub struct Config { - #[cfg(feature = "time")] - pub time_interrupt_priority: Priority, - pub rtc_interrupt_priority: Priority, - pub adc_interrupt_priority: Priority, - pub gpio_interrupt_priority: Priority, - pub clock_cfg: ClocksConfig, -} - -impl Default for Config { - fn default() -> Self { - Self { - #[cfg(feature = "time")] - time_interrupt_priority: Priority::from(0), - rtc_interrupt_priority: Priority::from(0), - adc_interrupt_priority: Priority::from(0), - gpio_interrupt_priority: Priority::from(0), - clock_cfg: ClocksConfig::default(), - } - } -} diff --git a/src/gpio.rs b/src/gpio.rs deleted file mode 100644 index 65f8df985..000000000 --- a/src/gpio.rs +++ /dev/null @@ -1,1062 +0,0 @@ -//! GPIO driver built around a type-erased `Flex` pin, similar to other Embassy HALs. -//! The exported `Output`/`Input` drivers own a `Flex` so they no longer depend on the -//! concrete pin type. - -use core::convert::Infallible; -use core::future::Future; -use core::marker::PhantomData; -use core::pin::pin; - -use embassy_hal_internal::{Peri, PeripheralType}; -use maitake_sync::WaitMap; -use paste::paste; - -use crate::pac::interrupt; -use crate::pac::port0::pcr0::{Dse, Inv, Mux, Pe, Ps, Sre}; - -struct BitIter(u32); - -impl Iterator for BitIter { - type Item = usize; - - fn next(&mut self) -> Option { - match self.0.trailing_zeros() { - 32 => None, - b => { - self.0 &= !(1 << b); - Some(b as usize) - } - } - } -} - -const PORT_COUNT: usize = 5; - -static PORT_WAIT_MAPS: [WaitMap; PORT_COUNT] = [ - WaitMap::new(), - WaitMap::new(), - WaitMap::new(), - WaitMap::new(), - WaitMap::new(), -]; - -fn irq_handler(port_index: usize, gpio_base: *const crate::pac::gpio0::RegisterBlock) { - let gpio = unsafe { &*gpio_base }; - let isfr = gpio.isfr0().read().bits(); - - for pin in BitIter(isfr) { - // Clear all pending interrupts - gpio.isfr0().write(|w| unsafe { w.bits(1 << pin) }); - gpio.icr(pin).modify(|_, w| w.irqc().irqc0()); // Disable interrupt - - // Wake the corresponding port waker - if let Some(w) = PORT_WAIT_MAPS.get(port_index) { - w.wake(&pin, ()); - } - } -} - -#[interrupt] -fn GPIO0() { - irq_handler(0, crate::pac::Gpio0::ptr()); -} - -#[interrupt] -fn GPIO1() { - irq_handler(1, crate::pac::Gpio1::ptr()); -} - -#[interrupt] -fn GPIO2() { - irq_handler(2, crate::pac::Gpio2::ptr()); -} - -#[interrupt] -fn GPIO3() { - irq_handler(3, crate::pac::Gpio3::ptr()); -} - -#[interrupt] -fn GPIO4() { - irq_handler(4, crate::pac::Gpio4::ptr()); -} - -pub(crate) unsafe fn init() { - use embassy_hal_internal::interrupt::InterruptExt; - - crate::pac::interrupt::GPIO0.enable(); - crate::pac::interrupt::GPIO1.enable(); - crate::pac::interrupt::GPIO2.enable(); - crate::pac::interrupt::GPIO3.enable(); - crate::pac::interrupt::GPIO4.enable(); - - cortex_m::interrupt::enable(); -} - -/// Logical level for GPIO pins. -#[derive(Copy, Clone, Eq, PartialEq, Debug)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Level { - Low, - High, -} - -impl From for Level { - fn from(val: bool) -> Self { - match val { - true => Self::High, - false => Self::Low, - } - } -} - -#[derive(Copy, Clone, Eq, PartialEq, Debug)] -pub enum Pull { - Disabled, - Up, - Down, -} - -impl From for (Pe, Ps) { - fn from(pull: Pull) -> Self { - match pull { - Pull::Disabled => (Pe::Pe0, Ps::Ps0), - Pull::Up => (Pe::Pe1, Ps::Ps1), - Pull::Down => (Pe::Pe1, Ps::Ps0), - } - } -} - -#[derive(Copy, Clone, Eq, PartialEq, Debug)] -pub enum SlewRate { - Fast, - Slow, -} - -impl From for Sre { - fn from(slew_rate: SlewRate) -> Self { - match slew_rate { - SlewRate::Fast => Sre::Sre0, - SlewRate::Slow => Sre::Sre1, - } - } -} - -#[derive(Copy, Clone, Eq, PartialEq, Debug)] -pub enum DriveStrength { - Normal, - Double, -} - -impl From for Dse { - fn from(strength: DriveStrength) -> Self { - match strength { - DriveStrength::Normal => Dse::Dse0, - DriveStrength::Double => Dse::Dse1, - } - } -} - -#[derive(Copy, Clone, Eq, PartialEq, Debug)] -pub enum Inverter { - Disabled, - Enabled, -} - -impl From for Inv { - fn from(strength: Inverter) -> Self { - match strength { - Inverter::Disabled => Inv::Inv0, - Inverter::Enabled => Inv::Inv1, - } - } -} - -pub type Gpio = crate::peripherals::GPIO0; - -/// Type-erased representation of a GPIO pin. -pub struct AnyPin { - port: usize, - pin: usize, - gpio: &'static crate::pac::gpio0::RegisterBlock, - port_reg: &'static crate::pac::port0::RegisterBlock, - pcr_reg: &'static crate::pac::port0::Pcr0, -} - -impl AnyPin { - /// Create an `AnyPin` from raw components. - fn new( - port: usize, - pin: usize, - gpio: &'static crate::pac::gpio0::RegisterBlock, - port_reg: &'static crate::pac::port0::RegisterBlock, - pcr_reg: &'static crate::pac::port0::Pcr0, - ) -> Self { - Self { - port, - pin, - gpio, - port_reg, - pcr_reg, - } - } - - #[inline(always)] - fn mask(&self) -> u32 { - 1 << self.pin - } - - #[inline(always)] - fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { - self.gpio - } - - #[inline(always)] - pub fn port_index(&self) -> usize { - self.port - } - - #[inline(always)] - pub fn pin_index(&self) -> usize { - self.pin - } - - #[inline(always)] - fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { - self.port_reg - } - - #[inline(always)] - fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { - self.pcr_reg - } -} - -embassy_hal_internal::impl_peripheral!(AnyPin); - -pub(crate) trait SealedPin { - fn pin_port(&self) -> usize; - - fn port(&self) -> usize { - self.pin_port() / 32 - } - - fn pin(&self) -> usize { - self.pin_port() % 32 - } - - fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock; - - fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock; - - fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0; - - fn set_function(&self, function: Mux); - - fn set_pull(&self, pull: Pull); - - fn set_drive_strength(&self, strength: Dse); - - fn set_slew_rate(&self, slew_rate: Sre); - - fn set_enable_input_buffer(&self); -} - -/// GPIO pin trait. -#[allow(private_bounds)] -pub trait GpioPin: SealedPin + Sized + PeripheralType + Into + 'static { - /// Type-erase the pin. - fn degrade(self) -> AnyPin { - // SAFETY: This is only called within the GpioPin trait, which is only - // implemented within this module on valid pin peripherals and thus - // has been verified to be correct. - AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg()) - } -} - -impl SealedPin for AnyPin { - fn pin_port(&self) -> usize { - self.port * 32 + self.pin - } - - fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { - self.gpio() - } - - fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { - self.port_reg() - } - - fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { - self.pcr_reg() - } - - fn set_function(&self, function: Mux) { - self.pcr_reg().modify(|_, w| w.mux().variant(function)); - } - - fn set_pull(&self, pull: Pull) { - let (pull_enable, pull_select) = pull.into(); - self.pcr_reg().modify(|_, w| { - w.pe().variant(pull_enable); - w.ps().variant(pull_select) - }); - } - - fn set_drive_strength(&self, strength: Dse) { - self.pcr_reg().modify(|_, w| w.dse().variant(strength)); - } - - fn set_slew_rate(&self, slew_rate: Sre) { - self.pcr_reg().modify(|_, w| w.sre().variant(slew_rate)); - } - - fn set_enable_input_buffer(&self) { - self.pcr_reg().modify(|_, w| w.ibe().ibe1()); - } -} - -impl GpioPin for AnyPin {} - -macro_rules! impl_pin { - ($peri:ident, $port:expr, $pin:expr, $block:ident) => { - paste! { - impl SealedPin for crate::peripherals::$peri { - fn pin_port(&self) -> usize { - $port * 32 + $pin - } - - fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { - unsafe { &*crate::pac::$block::ptr() } - } - - fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock { - unsafe { &*crate::pac::[]::ptr() } - } - - fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 { - self.port_reg().[]() - } - - fn set_function(&self, function: Mux) { - unsafe { - let port_reg = &*crate::pac::[]::ptr(); - port_reg.[]().modify(|_, w| { - w.mux().variant(function) - }); - } - } - - fn set_pull(&self, pull: Pull) { - let port_reg = unsafe {&*crate::pac::[]::ptr()}; - let (pull_enable, pull_select) = pull.into(); - port_reg.[]().modify(|_, w| { - w.pe().variant(pull_enable); - w.ps().variant(pull_select) - }); - } - - fn set_drive_strength(&self, strength: Dse) { - let port_reg = unsafe {&*crate::pac::[]::ptr()}; - port_reg.[]().modify(|_, w| w.dse().variant(strength)); - } - - fn set_slew_rate(&self, slew_rate: Sre) { - let port_reg = unsafe {&*crate::pac::[]::ptr()}; - port_reg.[]().modify(|_, w| w.sre().variant(slew_rate)); - } - - fn set_enable_input_buffer(&self) { - let port_reg = unsafe {&*crate::pac::[]::ptr()}; - port_reg.[]().modify(|_, w| w.ibe().ibe1()); - } - } - - impl GpioPin for crate::peripherals::$peri {} - - impl From for AnyPin { - fn from(value: crate::peripherals::$peri) -> Self { - value.degrade() - } - } - - impl crate::peripherals::$peri { - /// Convenience helper to obtain a type-erased handle to this pin. - pub fn degrade(&self) -> AnyPin { - AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg()) - } - } - } - }; -} - -impl_pin!(P0_0, 0, 0, Gpio0); -impl_pin!(P0_1, 0, 1, Gpio0); -impl_pin!(P0_2, 0, 2, Gpio0); -impl_pin!(P0_3, 0, 3, Gpio0); -impl_pin!(P0_4, 0, 4, Gpio0); -impl_pin!(P0_5, 0, 5, Gpio0); -impl_pin!(P0_6, 0, 6, Gpio0); -impl_pin!(P0_7, 0, 7, Gpio0); -impl_pin!(P0_8, 0, 8, Gpio0); -impl_pin!(P0_9, 0, 9, Gpio0); -impl_pin!(P0_10, 0, 10, Gpio0); -impl_pin!(P0_11, 0, 11, Gpio0); -impl_pin!(P0_12, 0, 12, Gpio0); -impl_pin!(P0_13, 0, 13, Gpio0); -impl_pin!(P0_14, 0, 14, Gpio0); -impl_pin!(P0_15, 0, 15, Gpio0); -impl_pin!(P0_16, 0, 16, Gpio0); -impl_pin!(P0_17, 0, 17, Gpio0); -impl_pin!(P0_18, 0, 18, Gpio0); -impl_pin!(P0_19, 0, 19, Gpio0); -impl_pin!(P0_20, 0, 20, Gpio0); -impl_pin!(P0_21, 0, 21, Gpio0); -impl_pin!(P0_22, 0, 22, Gpio0); -impl_pin!(P0_23, 0, 23, Gpio0); -impl_pin!(P0_24, 0, 24, Gpio0); -impl_pin!(P0_25, 0, 25, Gpio0); -impl_pin!(P0_26, 0, 26, Gpio0); -impl_pin!(P0_27, 0, 27, Gpio0); -impl_pin!(P0_28, 0, 28, Gpio0); -impl_pin!(P0_29, 0, 29, Gpio0); -impl_pin!(P0_30, 0, 30, Gpio0); -impl_pin!(P0_31, 0, 31, Gpio0); - -impl_pin!(P1_0, 1, 0, Gpio1); -impl_pin!(P1_1, 1, 1, Gpio1); -impl_pin!(P1_2, 1, 2, Gpio1); -impl_pin!(P1_3, 1, 3, Gpio1); -impl_pin!(P1_4, 1, 4, Gpio1); -impl_pin!(P1_5, 1, 5, Gpio1); -impl_pin!(P1_6, 1, 6, Gpio1); -impl_pin!(P1_7, 1, 7, Gpio1); -impl_pin!(P1_8, 1, 8, Gpio1); -impl_pin!(P1_9, 1, 9, Gpio1); -impl_pin!(P1_10, 1, 10, Gpio1); -impl_pin!(P1_11, 1, 11, Gpio1); -impl_pin!(P1_12, 1, 12, Gpio1); -impl_pin!(P1_13, 1, 13, Gpio1); -impl_pin!(P1_14, 1, 14, Gpio1); -impl_pin!(P1_15, 1, 15, Gpio1); -impl_pin!(P1_16, 1, 16, Gpio1); -impl_pin!(P1_17, 1, 17, Gpio1); -impl_pin!(P1_18, 1, 18, Gpio1); -impl_pin!(P1_19, 1, 19, Gpio1); -impl_pin!(P1_20, 1, 20, Gpio1); -impl_pin!(P1_21, 1, 21, Gpio1); -impl_pin!(P1_22, 1, 22, Gpio1); -impl_pin!(P1_23, 1, 23, Gpio1); -impl_pin!(P1_24, 1, 24, Gpio1); -impl_pin!(P1_25, 1, 25, Gpio1); -impl_pin!(P1_26, 1, 26, Gpio1); -impl_pin!(P1_27, 1, 27, Gpio1); -impl_pin!(P1_28, 1, 28, Gpio1); -impl_pin!(P1_29, 1, 29, Gpio1); -impl_pin!(P1_30, 1, 30, Gpio1); -impl_pin!(P1_31, 1, 31, Gpio1); - -impl_pin!(P2_0, 2, 0, Gpio2); -impl_pin!(P2_1, 2, 1, Gpio2); -impl_pin!(P2_2, 2, 2, Gpio2); -impl_pin!(P2_3, 2, 3, Gpio2); -impl_pin!(P2_4, 2, 4, Gpio2); -impl_pin!(P2_5, 2, 5, Gpio2); -impl_pin!(P2_6, 2, 6, Gpio2); -impl_pin!(P2_7, 2, 7, Gpio2); -impl_pin!(P2_8, 2, 8, Gpio2); -impl_pin!(P2_9, 2, 9, Gpio2); -impl_pin!(P2_10, 2, 10, Gpio2); -impl_pin!(P2_11, 2, 11, Gpio2); -impl_pin!(P2_12, 2, 12, Gpio2); -impl_pin!(P2_13, 2, 13, Gpio2); -impl_pin!(P2_14, 2, 14, Gpio2); -impl_pin!(P2_15, 2, 15, Gpio2); -impl_pin!(P2_16, 2, 16, Gpio2); -impl_pin!(P2_17, 2, 17, Gpio2); -impl_pin!(P2_18, 2, 18, Gpio2); -impl_pin!(P2_19, 2, 19, Gpio2); -impl_pin!(P2_20, 2, 20, Gpio2); -impl_pin!(P2_21, 2, 21, Gpio2); -impl_pin!(P2_22, 2, 22, Gpio2); -impl_pin!(P2_23, 2, 23, Gpio2); -impl_pin!(P2_24, 2, 24, Gpio2); -impl_pin!(P2_25, 2, 25, Gpio2); -impl_pin!(P2_26, 2, 26, Gpio2); -impl_pin!(P2_27, 2, 27, Gpio2); -impl_pin!(P2_28, 2, 28, Gpio2); -impl_pin!(P2_29, 2, 29, Gpio2); -impl_pin!(P2_30, 2, 30, Gpio2); -impl_pin!(P2_31, 2, 31, Gpio2); - -impl_pin!(P3_0, 3, 0, Gpio3); -impl_pin!(P3_1, 3, 1, Gpio3); -impl_pin!(P3_2, 3, 2, Gpio3); -impl_pin!(P3_3, 3, 3, Gpio3); -impl_pin!(P3_4, 3, 4, Gpio3); -impl_pin!(P3_5, 3, 5, Gpio3); -impl_pin!(P3_6, 3, 6, Gpio3); -impl_pin!(P3_7, 3, 7, Gpio3); -impl_pin!(P3_8, 3, 8, Gpio3); -impl_pin!(P3_9, 3, 9, Gpio3); -impl_pin!(P3_10, 3, 10, Gpio3); -impl_pin!(P3_11, 3, 11, Gpio3); -impl_pin!(P3_12, 3, 12, Gpio3); -impl_pin!(P3_13, 3, 13, Gpio3); -impl_pin!(P3_14, 3, 14, Gpio3); -impl_pin!(P3_15, 3, 15, Gpio3); -impl_pin!(P3_16, 3, 16, Gpio3); -impl_pin!(P3_17, 3, 17, Gpio3); -impl_pin!(P3_18, 3, 18, Gpio3); -impl_pin!(P3_19, 3, 19, Gpio3); -impl_pin!(P3_20, 3, 20, Gpio3); -impl_pin!(P3_21, 3, 21, Gpio3); -impl_pin!(P3_22, 3, 22, Gpio3); -impl_pin!(P3_23, 3, 23, Gpio3); -impl_pin!(P3_24, 3, 24, Gpio3); -impl_pin!(P3_25, 3, 25, Gpio3); -impl_pin!(P3_26, 3, 26, Gpio3); -impl_pin!(P3_27, 3, 27, Gpio3); -impl_pin!(P3_28, 3, 28, Gpio3); -impl_pin!(P3_29, 3, 29, Gpio3); -impl_pin!(P3_30, 3, 30, Gpio3); -impl_pin!(P3_31, 3, 31, Gpio3); - -impl_pin!(P4_0, 4, 0, Gpio4); -impl_pin!(P4_1, 4, 1, Gpio4); -impl_pin!(P4_2, 4, 2, Gpio4); -impl_pin!(P4_3, 4, 3, Gpio4); -impl_pin!(P4_4, 4, 4, Gpio4); -impl_pin!(P4_5, 4, 5, Gpio4); -impl_pin!(P4_6, 4, 6, Gpio4); -impl_pin!(P4_7, 4, 7, Gpio4); -impl_pin!(P4_8, 4, 8, Gpio4); -impl_pin!(P4_9, 4, 9, Gpio4); -impl_pin!(P4_10, 4, 10, Gpio4); -impl_pin!(P4_11, 4, 11, Gpio4); -impl_pin!(P4_12, 4, 12, Gpio4); -impl_pin!(P4_13, 4, 13, Gpio4); -impl_pin!(P4_14, 4, 14, Gpio4); -impl_pin!(P4_15, 4, 15, Gpio4); -impl_pin!(P4_16, 4, 16, Gpio4); -impl_pin!(P4_17, 4, 17, Gpio4); -impl_pin!(P4_18, 4, 18, Gpio4); -impl_pin!(P4_19, 4, 19, Gpio4); -impl_pin!(P4_20, 4, 20, Gpio4); -impl_pin!(P4_21, 4, 21, Gpio4); -impl_pin!(P4_22, 4, 22, Gpio4); -impl_pin!(P4_23, 4, 23, Gpio4); -impl_pin!(P4_24, 4, 24, Gpio4); -impl_pin!(P4_25, 4, 25, Gpio4); -impl_pin!(P4_26, 4, 26, Gpio4); -impl_pin!(P4_27, 4, 27, Gpio4); -impl_pin!(P4_28, 4, 28, Gpio4); -impl_pin!(P4_29, 4, 29, Gpio4); -impl_pin!(P4_30, 4, 30, Gpio4); -impl_pin!(P4_31, 4, 31, Gpio4); - -/// A flexible pin that can be configured as input or output. -pub struct Flex<'d> { - pin: Peri<'d, AnyPin>, - _marker: PhantomData<&'d mut ()>, -} - -impl<'d> Flex<'d> { - /// Wrap the pin in a `Flex`. - /// - /// The pin remains unmodified. The initial output level is unspecified, but - /// can be changed before the pin is put into output mode. - pub fn new(pin: Peri<'d, impl GpioPin>) -> Self { - pin.set_function(Mux::Mux0); - Self { - pin: pin.into(), - _marker: PhantomData, - } - } - - #[inline] - fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock { - self.pin.gpio() - } - - #[inline] - fn mask(&self) -> u32 { - self.pin.mask() - } - - /// Put the pin into input mode. - pub fn set_as_input(&mut self) { - let mask = self.mask(); - let gpio = self.gpio(); - - self.set_enable_input_buffer(); - - gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); - } - - /// Put the pin into output mode. - pub fn set_as_output(&mut self) { - let mask = self.mask(); - let gpio = self.gpio(); - - self.set_pull(Pull::Disabled); - - gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); - } - - /// Set output level to High. - #[inline] - pub fn set_high(&mut self) { - self.gpio().psor().write(|w| unsafe { w.bits(self.mask()) }); - } - - /// Set output level to Low. - #[inline] - pub fn set_low(&mut self) { - self.gpio().pcor().write(|w| unsafe { w.bits(self.mask()) }); - } - - /// Set output level to the given `Level`. - #[inline] - pub fn set_level(&mut self, level: Level) { - match level { - Level::High => self.set_high(), - Level::Low => self.set_low(), - } - } - - /// Toggle output level. - #[inline] - pub fn toggle(&mut self) { - self.gpio().ptor().write(|w| unsafe { w.bits(self.mask()) }); - } - - /// Get whether the pin input level is high. - #[inline] - pub fn is_high(&self) -> bool { - (self.gpio().pdir().read().bits() & self.mask()) != 0 - } - - /// Get whether the pin input level is low. - #[inline] - pub fn is_low(&self) -> bool { - !self.is_high() - } - - /// Is the output pin set as high? - #[inline] - pub fn is_set_high(&self) -> bool { - self.is_high() - } - - /// Is the output pin set as low? - #[inline] - pub fn is_set_low(&self) -> bool { - !self.is_set_high() - } - - /// Configure the pin pull up/down level. - pub fn set_pull(&mut self, pull_select: Pull) { - self.pin.set_pull(pull_select); - } - - /// Configure the pin drive strength. - pub fn set_drive_strength(&mut self, strength: DriveStrength) { - self.pin.set_drive_strength(strength.into()); - } - - /// Configure the pin slew rate. - pub fn set_slew_rate(&mut self, slew_rate: SlewRate) { - self.pin.set_slew_rate(slew_rate.into()); - } - - /// Enable input buffer for the pin. - pub fn set_enable_input_buffer(&mut self) { - self.pin.set_enable_input_buffer(); - } - - /// Get pin level. - pub fn get_level(&self) -> Level { - self.is_high().into() - } -} - -/// Async methods -impl<'d> Flex<'d> { - /// Helper function that waits for a given interrupt trigger - async fn wait_for_inner(&mut self, level: crate::pac::gpio0::icr::Irqc) { - // First, ensure that we have a waker that is ready for this port+pin - let w = PORT_WAIT_MAPS[self.pin.port].wait(self.pin.pin); - let mut w = pin!(w); - // Wait for the subscription to occur, which requires polling at least once - // - // This function returns a result, but can only be an Err if: - // - // * We call `.close()` on a WaitMap, which we never do - // * We have a duplicate key, which can't happen because `wait_for_*` methods - // take an &mut ref of their unique port+pin combo - // - // So we wait for it to complete, but ignore the result. - _ = w.as_mut().subscribe().await; - - // Now that our waker is in the map, we can enable the appropriate interrupt - // - // Clear any existing pending interrupt on this pin - self.pin - .gpio() - .isfr0() - .write(|w| unsafe { w.bits(1 << self.pin.pin()) }); - self.pin.gpio().icr(self.pin.pin()).write(|w| w.isf().isf1()); - - // Pin interrupt configuration - self.pin - .gpio() - .icr(self.pin.pin()) - .modify(|_, w| w.irqc().variant(level)); - - // Finally, we can await the matching call to `.wake()` from the interrupt. - // - // Again, technically, this could return a result, but for the same reasons - // as above, this can't be an error in our case, so just wait for it to complete - _ = w.await; - } - - /// Wait until the pin is high. If it is already high, return immediately. - #[inline] - pub fn wait_for_high(&mut self) -> impl Future + use<'_, 'd> { - self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc12) - } - - /// Wait until the pin is low. If it is already low, return immediately. - #[inline] - pub fn wait_for_low(&mut self) -> impl Future + use<'_, 'd> { - self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc8) - } - - /// Wait for the pin to undergo a transition from low to high. - #[inline] - pub fn wait_for_rising_edge(&mut self) -> impl Future + use<'_, 'd> { - self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc9) - } - - /// Wait for the pin to undergo a transition from high to low. - #[inline] - pub fn wait_for_falling_edge(&mut self) -> impl Future + use<'_, 'd> { - self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc10) - } - - /// Wait for the pin to undergo any transition, i.e low to high OR high to low. - #[inline] - pub fn wait_for_any_edge(&mut self) -> impl Future + use<'_, 'd> { - self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc11) - } -} - -/// GPIO output driver that owns a `Flex` pin. -pub struct Output<'d> { - flex: Flex<'d>, -} - -impl<'d> Output<'d> { - /// Create a GPIO output driver for a [GpioPin] with the provided [Level]. - pub fn new(pin: Peri<'d, impl GpioPin>, initial: Level, strength: DriveStrength, slew_rate: SlewRate) -> Self { - let mut flex = Flex::new(pin); - flex.set_level(initial); - flex.set_as_output(); - flex.set_drive_strength(strength); - flex.set_slew_rate(slew_rate); - Self { flex } - } - - /// Set the output as high. - #[inline] - pub fn set_high(&mut self) { - self.flex.set_high(); - } - - /// Set the output as low. - #[inline] - pub fn set_low(&mut self) { - self.flex.set_low(); - } - - /// Set the output level. - #[inline] - pub fn set_level(&mut self, level: Level) { - self.flex.set_level(level); - } - - /// Toggle the output level. - #[inline] - pub fn toggle(&mut self) { - self.flex.toggle(); - } - - /// Is the output pin set as high? - #[inline] - pub fn is_set_high(&self) -> bool { - self.flex.is_high() - } - - /// Is the output pin set as low? - #[inline] - pub fn is_set_low(&self) -> bool { - !self.is_set_high() - } - - /// Expose the inner `Flex` if callers need to reconfigure the pin. - #[inline] - pub fn into_flex(self) -> Flex<'d> { - self.flex - } -} - -/// GPIO input driver that owns a `Flex` pin. -pub struct Input<'d> { - flex: Flex<'d>, -} - -impl<'d> Input<'d> { - /// Create a GPIO input driver for a [GpioPin]. - /// - pub fn new(pin: Peri<'d, impl GpioPin>, pull_select: Pull) -> Self { - let mut flex = Flex::new(pin); - flex.set_as_input(); - flex.set_pull(pull_select); - Self { flex } - } - - /// Get whether the pin input level is high. - #[inline] - pub fn is_high(&self) -> bool { - self.flex.is_high() - } - - /// Get whether the pin input level is low. - #[inline] - pub fn is_low(&self) -> bool { - self.flex.is_low() - } - - /// Expose the inner `Flex` if callers need to reconfigure the pin. - /// - /// Since Drive Strength and Slew Rate are not set when creating the Input - /// pin, they need to be set when converting - #[inline] - pub fn into_flex(mut self, strength: DriveStrength, slew_rate: SlewRate) -> Flex<'d> { - self.flex.set_drive_strength(strength); - self.flex.set_slew_rate(slew_rate); - self.flex - } - - /// Get the pin level. - pub fn get_level(&self) -> Level { - self.flex.get_level() - } -} - -/// Async methods -impl<'d> Input<'d> { - /// Wait until the pin is high. If it is already high, return immediately. - #[inline] - pub fn wait_for_high(&mut self) -> impl Future + use<'_, 'd> { - self.flex.wait_for_high() - } - - /// Wait until the pin is low. If it is already low, return immediately. - #[inline] - pub fn wait_for_low(&mut self) -> impl Future + use<'_, 'd> { - self.flex.wait_for_low() - } - - /// Wait for the pin to undergo a transition from low to high. - #[inline] - pub fn wait_for_rising_edge(&mut self) -> impl Future + use<'_, 'd> { - self.flex.wait_for_rising_edge() - } - - /// Wait for the pin to undergo a transition from high to low. - #[inline] - pub fn wait_for_falling_edge(&mut self) -> impl Future + use<'_, 'd> { - self.flex.wait_for_falling_edge() - } - - /// Wait for the pin to undergo any transition, i.e low to high OR high to low. - #[inline] - pub fn wait_for_any_edge(&mut self) -> impl Future + use<'_, 'd> { - self.flex.wait_for_any_edge() - } -} - -impl embedded_hal_async::digital::Wait for Input<'_> { - async fn wait_for_high(&mut self) -> Result<(), Self::Error> { - self.wait_for_high().await; - Ok(()) - } - - async fn wait_for_low(&mut self) -> Result<(), Self::Error> { - self.wait_for_low().await; - Ok(()) - } - - async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> { - self.wait_for_rising_edge().await; - Ok(()) - } - - async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> { - self.wait_for_falling_edge().await; - Ok(()) - } - - async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> { - self.wait_for_any_edge().await; - Ok(()) - } -} - -impl embedded_hal_async::digital::Wait for Flex<'_> { - async fn wait_for_high(&mut self) -> Result<(), Self::Error> { - self.wait_for_high().await; - Ok(()) - } - - async fn wait_for_low(&mut self) -> Result<(), Self::Error> { - self.wait_for_low().await; - Ok(()) - } - - async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> { - self.wait_for_rising_edge().await; - Ok(()) - } - - async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> { - self.wait_for_falling_edge().await; - Ok(()) - } - - async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> { - self.wait_for_any_edge().await; - Ok(()) - } -} - -// Both embedded_hal 0.2 and 1.0 must be supported by embassy HALs. -impl embedded_hal_02::digital::v2::InputPin for Flex<'_> { - // GPIO operations on this block cannot fail, therefor we set the error type - // to Infallible to guarantee that we can only produce Ok variants. - type Error = Infallible; - - #[inline] - fn is_high(&self) -> Result { - Ok(self.is_high()) - } - - #[inline] - fn is_low(&self) -> Result { - Ok(self.is_low()) - } -} - -impl embedded_hal_02::digital::v2::InputPin for Input<'_> { - type Error = Infallible; - - #[inline] - fn is_high(&self) -> Result { - Ok(self.is_high()) - } - - #[inline] - fn is_low(&self) -> Result { - Ok(self.is_low()) - } -} - -impl embedded_hal_02::digital::v2::OutputPin for Flex<'_> { - type Error = Infallible; - - #[inline] - fn set_high(&mut self) -> Result<(), Self::Error> { - self.set_high(); - Ok(()) - } - - #[inline] - fn set_low(&mut self) -> Result<(), Self::Error> { - self.set_low(); - Ok(()) - } -} - -impl embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'_> { - #[inline] - fn is_set_high(&self) -> Result { - Ok(self.is_set_high()) - } - - #[inline] - fn is_set_low(&self) -> Result { - Ok(self.is_set_low()) - } -} - -impl embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'_> { - type Error = Infallible; - - #[inline] - fn toggle(&mut self) -> Result<(), Self::Error> { - self.toggle(); - Ok(()) - } -} - -impl embedded_hal_1::digital::ErrorType for Flex<'_> { - type Error = Infallible; -} - -impl embedded_hal_1::digital::ErrorType for Input<'_> { - type Error = Infallible; -} - -impl embedded_hal_1::digital::ErrorType for Output<'_> { - type Error = Infallible; -} - -impl embedded_hal_1::digital::InputPin for Input<'_> { - #[inline] - fn is_high(&mut self) -> Result { - Ok((*self).is_high()) - } - - #[inline] - fn is_low(&mut self) -> Result { - Ok((*self).is_low()) - } -} - -impl embedded_hal_1::digital::OutputPin for Flex<'_> { - #[inline] - fn set_high(&mut self) -> Result<(), Self::Error> { - self.set_high(); - Ok(()) - } - - #[inline] - fn set_low(&mut self) -> Result<(), Self::Error> { - self.set_low(); - Ok(()) - } -} - -impl embedded_hal_1::digital::StatefulOutputPin for Flex<'_> { - #[inline] - fn is_set_high(&mut self) -> Result { - Ok((*self).is_set_high()) - } - - #[inline] - fn is_set_low(&mut self) -> Result { - Ok((*self).is_set_low()) - } -} diff --git a/src/i2c/controller.rs b/src/i2c/controller.rs deleted file mode 100644 index 182a53aea..000000000 --- a/src/i2c/controller.rs +++ /dev/null @@ -1,742 +0,0 @@ -//! LPI2C controller driver - -use core::future::Future; -use core::marker::PhantomData; - -use embassy_hal_internal::drop::OnDrop; -use embassy_hal_internal::Peri; -use mcxa_pac::lpi2c0::mtdr::Cmd; - -use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin}; -use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig}; -use crate::clocks::{enable_and_reset, PoweredClock}; -use crate::interrupt::typelevel::Interrupt; -use crate::AnyPin; - -/// Bus speed (nominal SCL, no clock stretching) -#[derive(Clone, Copy, Default, PartialEq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Speed { - #[default] - /// 100 kbit/sec - Standard, - /// 400 kbit/sec - Fast, - /// 1 Mbit/sec - FastPlus, - /// 3.4 Mbit/sec - UltraFast, -} - -impl From for (u8, u8, u8, u8) { - fn from(value: Speed) -> (u8, u8, u8, u8) { - match value { - Speed::Standard => (0x3d, 0x37, 0x3b, 0x1d), - Speed::Fast => (0x0e, 0x0c, 0x0d, 0x06), - Speed::FastPlus => (0x04, 0x03, 0x03, 0x02), - - // UltraFast is "special". Leaving it unimplemented until - // the driver and the clock API is further stabilized. - Speed::UltraFast => todo!(), - } - } -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -enum SendStop { - No, - Yes, -} - -/// I2C controller configuration -#[derive(Clone, Copy, Default)] -#[non_exhaustive] -pub struct Config { - /// Bus speed - pub speed: Speed, -} - -/// I2C Controller Driver. -pub struct I2c<'d, T: Instance, M: Mode> { - _peri: Peri<'d, T>, - _scl: Peri<'d, AnyPin>, - _sda: Peri<'d, AnyPin>, - _phantom: PhantomData, - is_hs: bool, -} - -impl<'d, T: Instance> I2c<'d, T, Blocking> { - /// Create a new blocking instance of the I2C Controller bus driver. - pub fn new_blocking( - peri: Peri<'d, T>, - scl: Peri<'d, impl SclPin>, - sda: Peri<'d, impl SdaPin>, - config: Config, - ) -> Result { - Self::new_inner(peri, scl, sda, config) - } -} - -impl<'d, T: Instance, M: Mode> I2c<'d, T, M> { - fn new_inner( - _peri: Peri<'d, T>, - scl: Peri<'d, impl SclPin>, - sda: Peri<'d, impl SdaPin>, - config: Config, - ) -> Result { - let (power, source, div) = Self::clock_config(config.speed); - - // Enable clocks - let conf = Lpi2cConfig { - power, - source, - div, - instance: T::CLOCK_INSTANCE, - }; - - _ = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; - - scl.mux(); - sda.mux(); - - let _scl = scl.into(); - let _sda = sda.into(); - - Self::set_config(&config)?; - - Ok(Self { - _peri, - _scl, - _sda, - _phantom: PhantomData, - is_hs: config.speed == Speed::UltraFast, - }) - } - - fn set_config(config: &Config) -> Result<()> { - // Disable the controller. - critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().disabled())); - - // Soft-reset the controller, read and write FIFOs. - Self::reset_fifos(); - critical_section::with(|_| { - T::regs().mcr().modify(|_, w| w.rst().reset()); - // According to Reference Manual section 40.7.1.4, "There - // is no minimum delay required before clearing the - // software reset", therefore we clear it immediately. - T::regs().mcr().modify(|_, w| w.rst().not_reset()); - - T::regs().mcr().modify(|_, w| w.dozen().clear_bit().dbgen().clear_bit()); - }); - - let (clklo, clkhi, sethold, datavd) = config.speed.into(); - - critical_section::with(|_| { - T::regs().mccr0().modify(|_, w| unsafe { - w.clklo() - .bits(clklo) - .clkhi() - .bits(clkhi) - .sethold() - .bits(sethold) - .datavd() - .bits(datavd) - }) - }); - - // Enable the controller. - critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().enabled())); - - // Clear all flags - T::regs().msr().write(|w| { - w.epf() - .clear_bit_by_one() - .sdf() - .clear_bit_by_one() - .ndf() - .clear_bit_by_one() - .alf() - .clear_bit_by_one() - .fef() - .clear_bit_by_one() - .pltf() - .clear_bit_by_one() - .dmf() - .clear_bit_by_one() - .stf() - .clear_bit_by_one() - }); - - Ok(()) - } - - // REVISIT: turn this into a function of the speed parameter - fn clock_config(speed: Speed) -> (PoweredClock, Lpi2cClockSel, Div4) { - match speed { - Speed::Standard | Speed::Fast | Speed::FastPlus => ( - PoweredClock::NormalEnabledDeepSleepDisabled, - Lpi2cClockSel::FroLfDiv, - const { Div4::no_div() }, - ), - Speed::UltraFast => ( - PoweredClock::NormalEnabledDeepSleepDisabled, - Lpi2cClockSel::FroHfDiv, - const { Div4::no_div() }, - ), - } - } - - /// Resets both TX and RX FIFOs dropping their contents. - fn reset_fifos() { - critical_section::with(|_| { - T::regs().mcr().modify(|_, w| w.rtf().reset().rrf().reset()); - }); - } - - /// Checks whether the TX FIFO is full - fn is_tx_fifo_full() -> bool { - let txfifo_size = 1 << T::regs().param().read().mtxfifo().bits(); - T::regs().mfsr().read().txcount().bits() == txfifo_size - } - - /// Checks whether the TX FIFO is empty - fn is_tx_fifo_empty() -> bool { - T::regs().mfsr().read().txcount() == 0 - } - - /// Checks whether the RX FIFO is empty. - fn is_rx_fifo_empty() -> bool { - T::regs().mfsr().read().rxcount() == 0 - } - - /// Reads and parses the controller status producing an - /// appropriate `Result<(), Error>` variant. - fn status() -> Result<()> { - let msr = T::regs().msr().read(); - T::regs().msr().write(|w| { - w.epf() - .clear_bit_by_one() - .sdf() - .clear_bit_by_one() - .ndf() - .clear_bit_by_one() - .alf() - .clear_bit_by_one() - .fef() - .clear_bit_by_one() - .fef() - .clear_bit_by_one() - .pltf() - .clear_bit_by_one() - .dmf() - .clear_bit_by_one() - .stf() - .clear_bit_by_one() - }); - - if msr.ndf().bit_is_set() { - Err(Error::AddressNack) - } else if msr.alf().bit_is_set() { - Err(Error::ArbitrationLoss) - } else if msr.fef().bit_is_set() { - Err(Error::FifoError) - } else { - Ok(()) - } - } - - /// Inserts the given command into the outgoing FIFO. - /// - /// Caller must ensure there is space in the FIFO for the new - /// command. - fn send_cmd(cmd: Cmd, data: u8) { - #[cfg(feature = "defmt")] - defmt::trace!( - "Sending cmd '{}' ({}) with data '{:08x}' MSR: {:08x}", - cmd, - cmd as u8, - data, - T::regs().msr().read().bits() - ); - - T::regs() - .mtdr() - .write(|w| unsafe { w.data().bits(data) }.cmd().variant(cmd)); - } - - /// Prepares an appropriate Start condition on bus by issuing a - /// `Start` command together with the device address and R/w bit. - /// - /// Blocks waiting for space in the FIFO to become available, then - /// sends the command and blocks waiting for the FIFO to become - /// empty ensuring the command was sent. - fn start(&mut self, address: u8, read: bool) -> Result<()> { - if address >= 0x80 { - return Err(Error::AddressOutOfRange(address)); - } - - // Wait until we have space in the TxFIFO - while Self::is_tx_fifo_full() {} - - let addr_rw = address << 1 | if read { 1 } else { 0 }; - Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); - - // Wait for TxFIFO to be drained - while !Self::is_tx_fifo_empty() {} - - // Check controller status - Self::status() - } - - /// Prepares a Stop condition on the bus. - /// - /// Analogous to `start`, this blocks waiting for space in the - /// FIFO to become available, then sends the command and blocks - /// waiting for the FIFO to become empty ensuring the command was - /// sent. - fn stop() -> Result<()> { - // Wait until we have space in the TxFIFO - while Self::is_tx_fifo_full() {} - - Self::send_cmd(Cmd::Stop, 0); - - // Wait for TxFIFO to be drained - while !Self::is_tx_fifo_empty() {} - - Self::status() - } - - fn blocking_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { - if read.is_empty() { - return Err(Error::InvalidReadBufferLength); - } - - for chunk in read.chunks_mut(256) { - self.start(address, true)?; - - // Wait until we have space in the TxFIFO - while Self::is_tx_fifo_full() {} - - Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); - - for byte in chunk.iter_mut() { - // Wait until there's data in the RxFIFO - while Self::is_rx_fifo_empty() {} - - *byte = T::regs().mrdr().read().data().bits(); - } - } - - if send_stop == SendStop::Yes { - Self::stop()?; - } - - Ok(()) - } - - fn blocking_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> { - self.start(address, false)?; - - // Usually, embassy HALs error out with an empty write, - // however empty writes are useful for writing I2C scanning - // logic through write probing. That is, we send a start with - // R/w bit cleared, but instead of writing any data, just send - // the stop onto the bus. This has the effect of checking if - // the resulting address got an ACK but causing no - // side-effects to the device on the other end. - // - // Because of this, we are not going to error out in case of - // empty writes. - #[cfg(feature = "defmt")] - if write.is_empty() { - defmt::trace!("Empty write, write probing?"); - } - - for byte in write { - // Wait until we have space in the TxFIFO - while Self::is_tx_fifo_full() {} - - Self::send_cmd(Cmd::Transmit, *byte); - } - - if send_stop == SendStop::Yes { - Self::stop()?; - } - - Ok(()) - } - - // Public API: Blocking - - /// Read from address into buffer blocking caller until done. - pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<()> { - self.blocking_read_internal(address, read, SendStop::Yes) - } - - /// Write to address from buffer blocking caller until done. - pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<()> { - self.blocking_write_internal(address, write, SendStop::Yes) - } - - /// Write to address from bytes and read from address into buffer blocking caller until done. - pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> { - self.blocking_write_internal(address, write, SendStop::No)?; - self.blocking_read_internal(address, read, SendStop::Yes) - } -} - -impl<'d, T: Instance> I2c<'d, T, Async> { - /// Create a new async instance of the I2C Controller bus driver. - pub fn new_async( - peri: Peri<'d, T>, - scl: Peri<'d, impl SclPin>, - sda: Peri<'d, impl SdaPin>, - _irq: impl crate::interrupt::typelevel::Binding> + 'd, - config: Config, - ) -> Result { - T::Interrupt::unpend(); - - // Safety: `_irq` ensures an Interrupt Handler exists. - unsafe { T::Interrupt::enable() }; - - Self::new_inner(peri, scl, sda, config) - } - - fn remediation() { - #[cfg(feature = "defmt")] - defmt::trace!("Future dropped, issuing stop",); - - // if the FIFO is not empty, drop its contents. - if !Self::is_tx_fifo_empty() { - Self::reset_fifos(); - } - - // send a stop command - let _ = Self::stop(); - } - - fn enable_rx_ints(&mut self) { - T::regs().mier().write(|w| { - w.rdie() - .enabled() - .ndie() - .enabled() - .alie() - .enabled() - .feie() - .enabled() - .pltie() - .enabled() - }); - } - - fn enable_tx_ints(&mut self) { - T::regs().mier().write(|w| { - w.tdie() - .enabled() - .ndie() - .enabled() - .alie() - .enabled() - .feie() - .enabled() - .pltie() - .enabled() - }); - } - - async fn async_start(&mut self, address: u8, read: bool) -> Result<()> { - if address >= 0x80 { - return Err(Error::AddressOutOfRange(address)); - } - - // send the start command - let addr_rw = address << 1 | if read { 1 } else { 0 }; - Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw); - - T::wait_cell() - .wait_for(|| { - // enable interrupts - self.enable_tx_ints(); - // if the command FIFO is empty, we're done sending start - Self::is_tx_fifo_empty() - }) - .await - .map_err(|_| Error::Other)?; - - Self::status() - } - - async fn async_stop(&mut self) -> Result<()> { - // send the stop command - Self::send_cmd(Cmd::Stop, 0); - - T::wait_cell() - .wait_for(|| { - // enable interrupts - self.enable_tx_ints(); - // if the command FIFO is empty, we're done sending stop - Self::is_tx_fifo_empty() - }) - .await - .map_err(|_| Error::Other)?; - - Self::status() - } - - async fn async_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> { - if read.is_empty() { - return Err(Error::InvalidReadBufferLength); - } - - // perform corrective action if the future is dropped - let on_drop = OnDrop::new(|| Self::remediation()); - - for chunk in read.chunks_mut(256) { - self.async_start(address, true).await?; - - // send receive command - Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8); - - T::wait_cell() - .wait_for(|| { - // enable interrupts - self.enable_tx_ints(); - // if the command FIFO is empty, we're done sending start - Self::is_tx_fifo_empty() - }) - .await - .map_err(|_| Error::Other)?; - - for byte in chunk.iter_mut() { - T::wait_cell() - .wait_for(|| { - // enable interrupts - self.enable_rx_ints(); - // if the rx FIFO is not empty, we need to read a byte - !Self::is_rx_fifo_empty() - }) - .await - .map_err(|_| Error::ReadFail)?; - - *byte = T::regs().mrdr().read().data().bits(); - } - } - - if send_stop == SendStop::Yes { - self.async_stop().await?; - } - - // defuse it if the future is not dropped - on_drop.defuse(); - - Ok(()) - } - - async fn async_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> { - self.async_start(address, false).await?; - - // perform corrective action if the future is dropped - let on_drop = OnDrop::new(|| Self::remediation()); - - // Usually, embassy HALs error out with an empty write, - // however empty writes are useful for writing I2C scanning - // logic through write probing. That is, we send a start with - // R/w bit cleared, but instead of writing any data, just send - // the stop onto the bus. This has the effect of checking if - // the resulting address got an ACK but causing no - // side-effects to the device on the other end. - // - // Because of this, we are not going to error out in case of - // empty writes. - #[cfg(feature = "defmt")] - if write.is_empty() { - defmt::trace!("Empty write, write probing?"); - } - - for byte in write { - T::wait_cell() - .wait_for(|| { - // enable interrupts - self.enable_tx_ints(); - // initiate transmit - Self::send_cmd(Cmd::Transmit, *byte); - // if the tx FIFO is empty, we're done transmiting - Self::is_tx_fifo_empty() - }) - .await - .map_err(|_| Error::WriteFail)?; - } - - if send_stop == SendStop::Yes { - self.async_stop().await?; - } - - // defuse it if the future is not dropped - on_drop.defuse(); - - Ok(()) - } - - // Public API: Async - - /// Read from address into buffer asynchronously. - pub fn async_read<'a>( - &mut self, - address: u8, - read: &'a mut [u8], - ) -> impl Future> + use<'_, 'a, 'd, T> { - self.async_read_internal(address, read, SendStop::Yes) - } - - /// Write to address from buffer asynchronously. - pub fn async_write<'a>( - &mut self, - address: u8, - write: &'a [u8], - ) -> impl Future> + use<'_, 'a, 'd, T> { - self.async_write_internal(address, write, SendStop::Yes) - } - - /// Write to address from bytes and read from address into buffer asynchronously. - pub async fn async_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> { - self.async_write_internal(address, write, SendStop::No).await?; - self.async_read_internal(address, read, SendStop::Yes).await - } -} - -impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> { - type Error = Error; - - fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<()> { - self.blocking_read(address, buffer) - } -} - -impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> { - type Error = Error; - - fn write(&mut self, address: u8, bytes: &[u8]) -> Result<()> { - self.blocking_write(address, bytes) - } -} - -impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> { - type Error = Error; - - fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<()> { - self.blocking_write_read(address, bytes, buffer) - } -} - -impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Transactional for I2c<'d, T, M> { - type Error = Error; - - fn exec(&mut self, address: u8, operations: &mut [embedded_hal_02::blocking::i2c::Operation<'_>]) -> Result<()> { - if let Some((last, rest)) = operations.split_last_mut() { - for op in rest { - match op { - embedded_hal_02::blocking::i2c::Operation::Read(buf) => { - self.blocking_read_internal(address, buf, SendStop::No)? - } - embedded_hal_02::blocking::i2c::Operation::Write(buf) => { - self.blocking_write_internal(address, buf, SendStop::No)? - } - } - } - - match last { - embedded_hal_02::blocking::i2c::Operation::Read(buf) => { - self.blocking_read_internal(address, buf, SendStop::Yes) - } - embedded_hal_02::blocking::i2c::Operation::Write(buf) => { - self.blocking_write_internal(address, buf, SendStop::Yes) - } - } - } else { - Ok(()) - } - } -} - -impl embedded_hal_1::i2c::Error for Error { - fn kind(&self) -> embedded_hal_1::i2c::ErrorKind { - match *self { - Self::ArbitrationLoss => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss, - Self::AddressNack => { - embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address) - } - _ => embedded_hal_1::i2c::ErrorKind::Other, - } - } -} - -impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, T, M> { - type Error = Error; -} - -impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> { - fn transaction(&mut self, address: u8, operations: &mut [embedded_hal_1::i2c::Operation<'_>]) -> Result<()> { - if let Some((last, rest)) = operations.split_last_mut() { - for op in rest { - match op { - embedded_hal_1::i2c::Operation::Read(buf) => { - self.blocking_read_internal(address, buf, SendStop::No)? - } - embedded_hal_1::i2c::Operation::Write(buf) => { - self.blocking_write_internal(address, buf, SendStop::No)? - } - } - } - - match last { - embedded_hal_1::i2c::Operation::Read(buf) => self.blocking_read_internal(address, buf, SendStop::Yes), - embedded_hal_1::i2c::Operation::Write(buf) => self.blocking_write_internal(address, buf, SendStop::Yes), - } - } else { - Ok(()) - } - } -} - -impl<'d, T: Instance> embedded_hal_async::i2c::I2c for I2c<'d, T, Async> { - async fn transaction( - &mut self, - address: u8, - operations: &mut [embedded_hal_async::i2c::Operation<'_>], - ) -> Result<()> { - if let Some((last, rest)) = operations.split_last_mut() { - for op in rest { - match op { - embedded_hal_async::i2c::Operation::Read(buf) => { - self.async_read_internal(address, buf, SendStop::No).await? - } - embedded_hal_async::i2c::Operation::Write(buf) => { - self.async_write_internal(address, buf, SendStop::No).await? - } - } - } - - match last { - embedded_hal_async::i2c::Operation::Read(buf) => { - self.async_read_internal(address, buf, SendStop::Yes).await - } - embedded_hal_async::i2c::Operation::Write(buf) => { - self.async_write_internal(address, buf, SendStop::Yes).await - } - } - } else { - Ok(()) - } - } -} - -impl<'d, T: Instance, M: Mode> embassy_embedded_hal::SetConfig for I2c<'d, T, M> { - type Config = Config; - type ConfigError = Error; - - fn set_config(&mut self, config: &Self::Config) -> Result<()> { - Self::set_config(config) - } -} diff --git a/src/i2c/mod.rs b/src/i2c/mod.rs deleted file mode 100644 index 9a014224a..000000000 --- a/src/i2c/mod.rs +++ /dev/null @@ -1,194 +0,0 @@ -//! I2C Support - -use core::marker::PhantomData; - -use embassy_hal_internal::PeripheralType; -use maitake_sync::WaitCell; -use paste::paste; - -use crate::clocks::periph_helpers::Lpi2cConfig; -use crate::clocks::{ClockError, Gate}; -use crate::gpio::{GpioPin, SealedPin}; -use crate::{interrupt, pac}; - -/// Shorthand for `Result`. -pub type Result = core::result::Result; - -pub mod controller; - -/// Error information type -#[derive(Debug, Copy, Clone, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Error { - /// Clock configuration error. - ClockSetup(ClockError), - /// FIFO Error - FifoError, - /// Reading for I2C failed. - ReadFail, - /// Writing to I2C failed. - WriteFail, - /// I2C address NAK condition. - AddressNack, - /// Bus level arbitration loss. - ArbitrationLoss, - /// Address out of range. - AddressOutOfRange(u8), - /// Invalid write buffer length. - InvalidWriteBufferLength, - /// Invalid read buffer length. - InvalidReadBufferLength, - /// Other internal errors or unexpected state. - Other, -} - -/// I2C interrupt handler. -pub struct InterruptHandler { - _phantom: PhantomData, -} - -impl interrupt::typelevel::Handler for InterruptHandler { - unsafe fn on_interrupt() { - if T::regs().mier().read().bits() != 0 { - T::regs().mier().write(|w| { - w.tdie() - .disabled() - .rdie() - .disabled() - .epie() - .disabled() - .sdie() - .disabled() - .ndie() - .disabled() - .alie() - .disabled() - .feie() - .disabled() - .pltie() - .disabled() - .dmie() - .disabled() - .stie() - .disabled() - }); - - T::wait_cell().wake(); - } - } -} - -mod sealed { - /// Seal a trait - pub trait Sealed {} -} - -impl sealed::Sealed for T {} - -trait SealedInstance { - fn regs() -> &'static pac::lpi2c0::RegisterBlock; - fn wait_cell() -> &'static WaitCell; -} - -/// I2C Instance -#[allow(private_bounds)] -pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate { - /// Interrupt for this I2C instance. - type Interrupt: interrupt::typelevel::Interrupt; - /// Clock instance - const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance; -} - -macro_rules! impl_instance { - ($($n:expr),*) => { - $( - paste!{ - impl SealedInstance for crate::peripherals::[] { - fn regs() -> &'static pac::lpi2c0::RegisterBlock { - unsafe { &*pac::[]::ptr() } - } - - fn wait_cell() -> &'static WaitCell { - static WAIT_CELL: WaitCell = WaitCell::new(); - &WAIT_CELL - } - } - - impl Instance for crate::peripherals::[] { - type Interrupt = crate::interrupt::typelevel::[]; - const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance - = crate::clocks::periph_helpers::Lpi2cInstance::[]; - } - } - )* - }; -} - -impl_instance!(0, 1, 2, 3); - -/// SCL pin trait. -pub trait SclPin: GpioPin + sealed::Sealed + PeripheralType { - fn mux(&self); -} - -/// SDA pin trait. -pub trait SdaPin: GpioPin + sealed::Sealed + PeripheralType { - fn mux(&self); -} - -/// Driver mode. -#[allow(private_bounds)] -pub trait Mode: sealed::Sealed {} - -/// Blocking mode. -pub struct Blocking; -impl sealed::Sealed for Blocking {} -impl Mode for Blocking {} - -/// Async mode. -pub struct Async; -impl sealed::Sealed for Async {} -impl Mode for Async {} - -macro_rules! impl_pin { - ($pin:ident, $peri:ident, $fn:ident, $trait:ident) => { - impl $trait for crate::peripherals::$pin { - fn mux(&self) { - self.set_pull(crate::gpio::Pull::Disabled); - self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); - self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); - self.set_function(crate::pac::port0::pcr0::Mux::$fn); - self.set_enable_input_buffer(); - } - } - }; -} - -impl_pin!(P0_16, LPI2C0, Mux2, SdaPin); -impl_pin!(P0_17, LPI2C0, Mux2, SclPin); -impl_pin!(P0_18, LPI2C0, Mux2, SclPin); -impl_pin!(P0_19, LPI2C0, Mux2, SdaPin); -impl_pin!(P1_0, LPI2C1, Mux3, SdaPin); -impl_pin!(P1_1, LPI2C1, Mux3, SclPin); -impl_pin!(P1_2, LPI2C1, Mux3, SdaPin); -impl_pin!(P1_3, LPI2C1, Mux3, SclPin); -impl_pin!(P1_8, LPI2C2, Mux3, SdaPin); -impl_pin!(P1_9, LPI2C2, Mux3, SclPin); -impl_pin!(P1_10, LPI2C2, Mux3, SdaPin); -impl_pin!(P1_11, LPI2C2, Mux3, SclPin); -impl_pin!(P1_12, LPI2C1, Mux2, SdaPin); -impl_pin!(P1_13, LPI2C1, Mux2, SclPin); -impl_pin!(P1_14, LPI2C1, Mux2, SclPin); -impl_pin!(P1_15, LPI2C1, Mux2, SdaPin); -impl_pin!(P1_30, LPI2C0, Mux3, SdaPin); -impl_pin!(P1_31, LPI2C0, Mux3, SclPin); -impl_pin!(P3_27, LPI2C3, Mux2, SclPin); -impl_pin!(P3_28, LPI2C3, Mux2, SdaPin); -// impl_pin!(P3_29, LPI2C3, Mux2, HreqPin); What is this HREQ pin? -impl_pin!(P3_30, LPI2C3, Mux2, SclPin); -impl_pin!(P3_31, LPI2C3, Mux2, SdaPin); -impl_pin!(P4_2, LPI2C2, Mux2, SdaPin); -impl_pin!(P4_3, LPI2C0, Mux2, SclPin); -impl_pin!(P4_4, LPI2C2, Mux2, SdaPin); -impl_pin!(P4_5, LPI2C0, Mux2, SclPin); -// impl_pin!(P4_6, LPI2C0, Mux2, HreqPin); What is this HREQ pin? diff --git a/src/interrupt.rs b/src/interrupt.rs deleted file mode 100644 index 1d10e3b2d..000000000 --- a/src/interrupt.rs +++ /dev/null @@ -1,563 +0,0 @@ -//! Minimal interrupt helpers mirroring embassy-imxrt style for OS_EVENT and LPUART2. -//! Type-level interrupt traits and bindings are provided by the -//! `embassy_hal_internal::interrupt_mod!` macro via the generated module below. - -// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs -// are complete prior to release. -#![allow(clippy::missing_safety_doc)] - -mod generated { - #[rustfmt::skip] - embassy_hal_internal::interrupt_mod!( - ADC1, - GPIO0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - LPI2C0, - LPI2C1, - LPI2C2, - LPI2C3, - LPUART0, - LPUART1, - LPUART2, - LPUART3, - LPUART4, - LPUART5, - OS_EVENT, - RTC, - ); -} - -use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; - -pub use generated::interrupt::{typelevel, Priority}; - -use crate::pac::Interrupt; - -/// Trait for configuring and controlling interrupts. -/// -/// This trait provides a consistent interface for interrupt management across -/// different interrupt sources, similar to embassy-imxrt's InterruptExt. -pub trait InterruptExt { - /// Clear any pending interrupt in NVIC. - fn unpend(&self); - - /// Set NVIC priority for this interrupt. - fn set_priority(&self, priority: Priority); - - /// Enable this interrupt in NVIC. - /// - /// # Safety - /// This function is unsafe because it can enable interrupts that may not be - /// properly configured, potentially leading to undefined behavior. - unsafe fn enable(&self); - - /// Disable this interrupt in NVIC. - /// - /// # Safety - /// This function is unsafe because disabling interrupts may leave the system - /// in an inconsistent state if the interrupt was expected to fire. - unsafe fn disable(&self); - - /// Check if the interrupt is pending in NVIC. - fn is_pending(&self) -> bool; -} - -#[derive(Clone, Copy, Debug, Default)] -pub struct DefaultHandlerSnapshot { - pub vector: u16, - pub count: u32, - pub cfsr: u32, - pub hfsr: u32, - pub stacked_pc: u32, - pub stacked_lr: u32, - pub stacked_sp: u32, -} - -static LAST_DEFAULT_VECTOR: AtomicU16 = AtomicU16::new(0); -static LAST_DEFAULT_COUNT: AtomicU32 = AtomicU32::new(0); -static LAST_DEFAULT_CFSR: AtomicU32 = AtomicU32::new(0); -static LAST_DEFAULT_HFSR: AtomicU32 = AtomicU32::new(0); -static LAST_DEFAULT_PC: AtomicU32 = AtomicU32::new(0); -static LAST_DEFAULT_LR: AtomicU32 = AtomicU32::new(0); -static LAST_DEFAULT_SP: AtomicU32 = AtomicU32::new(0); - -#[inline] -pub fn default_handler_snapshot() -> DefaultHandlerSnapshot { - DefaultHandlerSnapshot { - vector: LAST_DEFAULT_VECTOR.load(Ordering::Relaxed), - count: LAST_DEFAULT_COUNT.load(Ordering::Relaxed), - cfsr: LAST_DEFAULT_CFSR.load(Ordering::Relaxed), - hfsr: LAST_DEFAULT_HFSR.load(Ordering::Relaxed), - stacked_pc: LAST_DEFAULT_PC.load(Ordering::Relaxed), - stacked_lr: LAST_DEFAULT_LR.load(Ordering::Relaxed), - stacked_sp: LAST_DEFAULT_SP.load(Ordering::Relaxed), - } -} - -#[inline] -pub fn clear_default_handler_snapshot() { - LAST_DEFAULT_VECTOR.store(0, Ordering::Relaxed); - LAST_DEFAULT_COUNT.store(0, Ordering::Relaxed); - LAST_DEFAULT_CFSR.store(0, Ordering::Relaxed); - LAST_DEFAULT_HFSR.store(0, Ordering::Relaxed); - LAST_DEFAULT_PC.store(0, Ordering::Relaxed); - LAST_DEFAULT_LR.store(0, Ordering::Relaxed); - LAST_DEFAULT_SP.store(0, Ordering::Relaxed); -} - -/// OS_EVENT interrupt helper with methods similar to embassy-imxrt's InterruptExt. -pub struct OsEvent; -pub const OS_EVENT: OsEvent = OsEvent; - -impl InterruptExt for OsEvent { - /// Clear any pending OS_EVENT in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::OS_EVENT); - } - - /// Set NVIC priority for OS_EVENT. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::OS_EVENT, u8::from(priority)); - } - } - - /// Enable OS_EVENT in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::OS_EVENT); - } - - /// Disable OS_EVENT in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::OS_EVENT); - } - - /// Check if OS_EVENT is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::OS_EVENT) - } -} - -impl OsEvent { - /// Configure OS_EVENT interrupt for timer operation. - /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled. - /// Also performs a software event to wake any pending WFE. - pub fn configure_for_timer(&self, priority: Priority) { - // Configure NVIC - self.unpend(); - self.set_priority(priority); - unsafe { - self.enable(); - } - - // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run) - // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not. - unsafe { - cortex_m::interrupt::enable(); - } - - // Wake any executor WFE that might be sleeping when we armed the first deadline - cortex_m::asm::sev(); - } -} - -/// LPUART2 interrupt helper with methods similar to embassy-imxrt's InterruptExt. -pub struct Lpuart2; -pub const LPUART2: Lpuart2 = Lpuart2; - -impl InterruptExt for Lpuart2 { - /// Clear any pending LPUART2 in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::LPUART2); - } - - /// Set NVIC priority for LPUART2. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::LPUART2, u8::from(priority)); - } - } - - /// Enable LPUART2 in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::LPUART2); - } - - /// Disable LPUART2 in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::LPUART2); - } - - /// Check if LPUART2 is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::LPUART2) - } -} - -impl Lpuart2 { - /// Configure LPUART2 interrupt for UART operation. - /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled. - pub fn configure_for_uart(&self, priority: Priority) { - // Configure NVIC - self.unpend(); - self.set_priority(priority); - unsafe { - self.enable(); - } - - // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run) - // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not. - unsafe { - cortex_m::interrupt::enable(); - } - } - - /// Install LPUART2 handler into the RAM vector table. - /// Safety: See `install_irq_handler`. - pub unsafe fn install_handler(&self, handler: unsafe extern "C" fn()) { - install_irq_handler(Interrupt::LPUART2, handler); - } -} - -pub struct Rtc; -pub const RTC: Rtc = Rtc; - -impl InterruptExt for Rtc { - /// Clear any pending RTC in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::RTC); - } - - /// Set NVIC priority for RTC. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::RTC, u8::from(priority)); - } - } - - /// Enable RTC in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::RTC); - } - - /// Disable RTC in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::RTC); - } - - /// Check if RTC is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC) - } -} - -pub struct Adc; -pub const ADC1: Adc = Adc; - -impl InterruptExt for Adc { - /// Clear any pending ADC1 in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::ADC1); - } - - /// Set NVIC priority for ADC1. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::ADC1, u8::from(priority)); - } - } - - /// Enable ADC1 in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::ADC1); - } - - /// Disable ADC1 in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::ADC1); - } - - /// Check if ADC1 is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC1) - } -} - -pub struct Gpio0; -pub const GPIO0: Gpio0 = Gpio0; - -impl InterruptExt for Gpio0 { - /// Clear any pending GPIO0 in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO0); - } - - /// Set NVIC priority for GPIO0. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::GPIO0, u8::from(priority)); - } - } - - /// Enable GPIO0 in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO0); - } - - /// Disable GPIO0 in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::GPIO0); - } - - /// Check if GPIO0 is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO0) - } -} - -pub struct Gpio1; -pub const GPIO1: Gpio1 = Gpio1; - -impl InterruptExt for Gpio1 { - /// Clear any pending GPIO1 in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO1); - } - - /// Set NVIC priority for GPIO1. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::GPIO1, u8::from(priority)); - } - } - - /// Enable GPIO1 in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO1); - } - - /// Disable GPIO1 in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::GPIO1); - } - - /// Check if GPIO1 is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO1) - } -} - -pub struct Gpio2; -pub const GPIO2: Gpio2 = Gpio2; - -impl InterruptExt for Gpio2 { - /// Clear any pending GPIO2 in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO2); - } - - /// Set NVIC priority for GPIO2. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::GPIO2, u8::from(priority)); - } - } - - /// Enable GPIO2 in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO2); - } - - /// Disable GPIO2 in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::GPIO2); - } - - /// Check if GPIO2 is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO2) - } -} - -pub struct Gpio3; -pub const GPIO3: Gpio3 = Gpio3; - -impl InterruptExt for Gpio3 { - /// Clear any pending GPIO3 in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO3); - } - - /// Set NVIC priority for GPIO3. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::GPIO3, u8::from(priority)); - } - } - - /// Enable GPIO3 in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO3); - } - - /// Disable GPIO3 in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::GPIO3); - } - - /// Check if GPIO3 is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO3) - } -} - -pub struct Gpio4; -pub const GPIO4: Gpio4 = Gpio4; - -impl InterruptExt for Gpio4 { - /// Clear any pending GPIO4 in NVIC. - #[inline] - fn unpend(&self) { - cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO4); - } - - /// Set NVIC priority for GPIO4. - #[inline] - fn set_priority(&self, priority: Priority) { - unsafe { - let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC; - nvic.set_priority(Interrupt::GPIO4, u8::from(priority)); - } - } - - /// Enable GPIO4 in NVIC. - #[inline] - unsafe fn enable(&self) { - cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO4); - } - - /// Disable GPIO4 in NVIC. - #[inline] - unsafe fn disable(&self) { - cortex_m::peripheral::NVIC::mask(Interrupt::GPIO4); - } - - /// Check if GPIO4 is pending in NVIC. - #[inline] - fn is_pending(&self) -> bool { - cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO4) - } -} - -/// Set VTOR (Vector Table Offset) to a RAM-based vector table. -/// Pass a pointer to the first word in the RAM table (stack pointer slot 0). -/// Safety: Caller must ensure the RAM table is valid and aligned as required by the core. -pub unsafe fn vtor_set_ram_vector_base(base: *const u32) { - core::ptr::write_volatile(0xE000_ED08 as *mut u32, base as u32); -} - -/// Install an interrupt handler into the current VTOR-based vector table. -/// This writes the function pointer at index 16 + irq number. -/// Safety: Caller must ensure VTOR points at a writable RAM table and that `handler` -/// has the correct ABI and lifetime. -pub unsafe fn install_irq_handler(irq: Interrupt, handler: unsafe extern "C" fn()) { - let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32; - let idx = 16 + (irq as isize as usize); - core::ptr::write_volatile(vtor_base.add(idx), handler as usize as u32); -} - -impl OsEvent { - /// Convenience to install the OS_EVENT handler into the RAM vector table. - /// Safety: See `install_irq_handler`. - pub unsafe fn install_handler(&self, handler: extern "C" fn()) { - install_irq_handler(Interrupt::OS_EVENT, handler); - } -} - -/// Install OS_EVENT handler by raw address. Useful to avoid fn pointer type mismatches. -/// Safety: Caller must ensure the address is a valid `extern "C" fn()` handler. -pub unsafe fn os_event_install_handler_raw(handler_addr: usize) { - let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32; - let idx = 16 + (Interrupt::OS_EVENT as isize as usize); - core::ptr::write_volatile(vtor_base.add(idx), handler_addr as u32); -} - -/// Provide a conservative default IRQ handler that avoids wedging the system. -/// It clears all NVIC pending bits and returns, so spurious or reserved IRQs -/// don’t trap the core in an infinite WFI loop during bring-up. -#[no_mangle] -pub unsafe extern "C" fn DefaultHandler() { - let active = core::ptr::read_volatile(0xE000_ED04 as *const u32) & 0x1FF; - let cfsr = core::ptr::read_volatile(0xE000_ED28 as *const u32); - let hfsr = core::ptr::read_volatile(0xE000_ED2C as *const u32); - - let sp = cortex_m::register::msp::read(); - let stacked = sp as *const u32; - // Stacked registers follow ARMv8-M procedure call standard order - let stacked_pc = unsafe { stacked.add(6).read() }; - let stacked_lr = unsafe { stacked.add(5).read() }; - - LAST_DEFAULT_VECTOR.store(active as u16, Ordering::Relaxed); - LAST_DEFAULT_CFSR.store(cfsr, Ordering::Relaxed); - LAST_DEFAULT_HFSR.store(hfsr, Ordering::Relaxed); - LAST_DEFAULT_COUNT.fetch_add(1, Ordering::Relaxed); - LAST_DEFAULT_PC.store(stacked_pc, Ordering::Relaxed); - LAST_DEFAULT_LR.store(stacked_lr, Ordering::Relaxed); - LAST_DEFAULT_SP.store(sp, Ordering::Relaxed); - - // Do nothing here: on some MCUs/TrustZone setups, writing NVIC from a spurious - // handler can fault if targeting the Secure bank. Just return. - cortex_m::asm::dsb(); - cortex_m::asm::isb(); -} diff --git a/src/lib.rs b/src/lib.rs deleted file mode 100644 index c6d8adc8f..000000000 --- a/src/lib.rs +++ /dev/null @@ -1,471 +0,0 @@ -#![no_std] -#![allow(async_fn_in_trait)] -#![doc = include_str!("../README.md")] - -// //! ## Feature flags -// #![doc = document_features::document_features!(feature_label = r#"{feature}"#)] - -pub mod clocks; // still provide clock helpers -pub mod gpio; -pub mod pins; // pin mux helpers - -pub mod adc; -pub mod clkout; -pub mod config; -pub mod i2c; -pub mod interrupt; -pub mod lpuart; -pub mod ostimer; -pub mod rtc; - -pub use crate::pac::NVIC_PRIO_BITS; - -#[rustfmt::skip] -embassy_hal_internal::peripherals!( - ADC0, - ADC1, - - AOI0, - AOI1, - - CAN0, - CAN1, - - CDOG0, - CDOG1, - - // CLKOUT is not specifically a peripheral (it's part of SYSCON), - // but we still want it to be a singleton. - CLKOUT, - - CMC, - CMP0, - CMP1, - CRC0, - - CTIMER0, - CTIMER1, - CTIMER2, - CTIMER3, - CTIMER4, - - DBGMAILBOX, - DMA0, - EDMA0_TCD0, - EIM0, - EQDC0, - EQDC1, - ERM0, - FLEXIO0, - FLEXPWM0, - FLEXPWM1, - FMC0, - FMU0, - FREQME0, - GLIKEY0, - - GPIO0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - - I3C0, - INPUTMUX0, - - LPI2C0, - LPI2C1, - LPI2C2, - LPI2C3, - - LPSPI0, - LPSPI1, - - LPTMR0, - - LPUART0, - LPUART1, - LPUART2, - LPUART3, - LPUART4, - LPUART5, - - MAU0, - MBC0, - MRCC0, - OPAMP0, - - #[cfg(not(feature = "time"))] - OSTIMER0, - - P0_0, - P0_1, - P0_2, - P0_3, - P0_4, - P0_5, - P0_6, - P0_7, - P0_8, - P0_9, - P0_10, - P0_11, - P0_12, - P0_13, - P0_14, - P0_15, - P0_16, - P0_17, - P0_18, - P0_19, - P0_20, - P0_21, - P0_22, - P0_23, - P0_24, - P0_25, - P0_26, - P0_27, - P0_28, - P0_29, - P0_30, - P0_31, - - P1_0, - P1_1, - P1_2, - P1_3, - P1_4, - P1_5, - P1_6, - P1_7, - P1_8, - P1_9, - P1_10, - P1_11, - P1_12, - P1_13, - P1_14, - P1_15, - P1_16, - P1_17, - P1_18, - P1_19, - P1_20, - P1_21, - P1_22, - P1_23, - P1_24, - P1_25, - P1_26, - P1_27, - P1_28, - P1_29, - P1_30, - P1_31, - - P2_0, - P2_1, - P2_2, - P2_3, - P2_4, - P2_5, - P2_6, - P2_7, - P2_8, - P2_9, - P2_10, - P2_11, - P2_12, - P2_13, - P2_14, - P2_15, - P2_16, - P2_17, - P2_18, - P2_19, - P2_20, - P2_21, - P2_22, - P2_23, - P2_24, - P2_25, - P2_26, - P2_27, - P2_28, - P2_29, - P2_30, - P2_31, - - P3_0, - P3_1, - P3_2, - P3_3, - P3_4, - P3_5, - P3_6, - P3_7, - P3_8, - P3_9, - P3_10, - P3_11, - P3_12, - P3_13, - P3_14, - P3_15, - P3_16, - P3_17, - P3_18, - P3_19, - P3_20, - P3_21, - P3_22, - P3_23, - P3_24, - P3_25, - P3_26, - P3_27, - P3_28, - P3_29, - P3_30, - P3_31, - - P4_0, - P4_1, - P4_2, - P4_3, - P4_4, - P4_5, - P4_6, - P4_7, - P4_8, - P4_9, - P4_10, - P4_11, - P4_12, - P4_13, - P4_14, - P4_15, - P4_16, - P4_17, - P4_18, - P4_19, - P4_20, - P4_21, - P4_22, - P4_23, - P4_24, - P4_25, - P4_26, - P4_27, - P4_28, - P4_29, - P4_30, - P4_31, - - P5_0, - P5_1, - P5_2, - P5_3, - P5_4, - P5_5, - P5_6, - P5_7, - P5_8, - P5_9, - P5_10, - P5_11, - P5_12, - P5_13, - P5_14, - P5_15, - P5_16, - P5_17, - P5_18, - P5_19, - P5_20, - P5_21, - P5_22, - P5_23, - P5_24, - P5_25, - P5_26, - P5_27, - P5_28, - P5_29, - P5_30, - P5_31, - - PKC0, - - PORT0, - PORT1, - PORT2, - PORT3, - PORT4, - - RTC0, - SAU, - SCG0, - SCN_SCB, - SGI0, - SMARTDMA0, - SPC0, - SYSCON, - TDET0, - TRNG0, - UDF0, - USB0, - UTICK0, - VBAT0, - WAKETIMER0, - WUU0, - WWDT0, -); - -// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. - -// Re-export interrupt traits and types -pub use adc::Adc1 as Adc1Token; -pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output}; -pub use interrupt::InterruptExt; -#[cfg(feature = "unstable-pac")] -pub use mcxa_pac as pac; -#[cfg(not(feature = "unstable-pac"))] -pub(crate) use mcxa_pac as pac; - -/// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. -/// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). -pub fn init(cfg: crate::config::Config) -> Peripherals { - let peripherals = Peripherals::take(); - // Apply user-configured priority early; enabling is left to examples/apps - #[cfg(feature = "time")] - crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority); - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority); - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::GPIO0.set_priority(cfg.gpio_interrupt_priority); - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::GPIO1.set_priority(cfg.gpio_interrupt_priority); - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::GPIO2.set_priority(cfg.gpio_interrupt_priority); - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::GPIO3.set_priority(cfg.gpio_interrupt_priority); - // Apply user-configured priority early; enabling is left to examples/apps - crate::interrupt::GPIO4.set_priority(cfg.gpio_interrupt_priority); - - // Configure clocks - crate::clocks::init(cfg.clock_cfg).unwrap(); - - unsafe { - crate::gpio::init(); - } - - // Initialize embassy-time global driver backed by OSTIMER0 - #[cfg(feature = "time")] - crate::ostimer::time_driver::init(crate::config::Config::default().time_interrupt_priority, 1_000_000); - - // Enable GPIO clocks - unsafe { - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - _ = crate::clocks::enable_and_reset::(&crate::clocks::periph_helpers::NoConfig); - } - - peripherals -} - -// /// Optional hook called by cortex-m-rt before RAM init. -// /// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state -// /// left by soft resets/debug sessions. -// /// -// /// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor' -// /// feature is incompatible with our setup because it expects __vector_table to be -// /// defined differently than how our RAM-based linker script arranges it. -// #[no_mangle] -// pub unsafe extern "C" fn __pre_init() { -// // Set the VTOR to point to the interrupt vector table in RAM -// // This is required since code runs from RAM on this MCU -// crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32); - -// // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs. -// let nvic = &*cortex_m::peripheral::NVIC::PTR; -// for i in 0..4 { -// // 4 words x 32 = 128 IRQs -// nvic.icer[i].write(0xFFFF_FFFF); -// nvic.icpr[i].write(0xFFFF_FFFF); -// } -// // Do NOT touch peripheral registers here: clocks may be off and accesses can fault. -// crate::interrupt::clear_default_handler_snapshot(); -// } - -/// Internal helper to dispatch a type-level interrupt handler. -#[inline(always)] -#[doc(hidden)] -pub unsafe fn __handle_interrupt() -where - T: crate::interrupt::typelevel::Interrupt, - H: crate::interrupt::typelevel::Handler, -{ - H::on_interrupt(); -} - -/// Macro to bind interrupts to handlers, similar to embassy-imxrt. -/// -/// Example: -/// - Bind OS_EVENT to the OSTIMER time-driver handler -/// bind_interrupts!(struct Irqs { OS_EVENT => crate::ostimer::time_driver::OsEventHandler; }); -#[macro_export] -macro_rules! bind_interrupts { - ($(#[$attr:meta])* $vis:vis struct $name:ident { - $( - $(#[cfg($cond_irq:meta)])? - $irq:ident => $( - $(#[cfg($cond_handler:meta)])? - $handler:ty - ),*; - )* - }) => { - #[derive(Copy, Clone)] - $(#[$attr])* - $vis struct $name; - - $( - #[allow(non_snake_case)] - #[no_mangle] - $(#[cfg($cond_irq)])? - unsafe extern "C" fn $irq() { - unsafe { - $( - $(#[cfg($cond_handler)])? - <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt(); - )* - } - } - - $(#[cfg($cond_irq)])? - $crate::bind_interrupts!(@inner - $( - $(#[cfg($cond_handler)])? - unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {} - )* - ); - )* - }; - (@inner $($t:tt)*) => { - $($t)* - } -} diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs deleted file mode 100644 index 8eb443ca7..000000000 --- a/src/lpuart/buffered.rs +++ /dev/null @@ -1,780 +0,0 @@ -use core::future::poll_fn; -use core::marker::PhantomData; -use core::sync::atomic::{AtomicBool, Ordering}; -use core::task::Poll; - -use embassy_hal_internal::atomic_ring_buffer::RingBuffer; -use embassy_hal_internal::Peri; -use embassy_sync::waitqueue::AtomicWaker; - -use super::*; -use crate::interrupt; - -// ============================================================================ -// STATIC STATE MANAGEMENT -// ============================================================================ - -/// State for buffered LPUART operations -pub struct State { - tx_waker: AtomicWaker, - tx_buf: RingBuffer, - tx_done: AtomicBool, - rx_waker: AtomicWaker, - rx_buf: RingBuffer, - initialized: AtomicBool, -} - -impl Default for State { - fn default() -> Self { - Self::new() - } -} - -impl State { - /// Create a new state instance - pub const fn new() -> Self { - Self { - tx_waker: AtomicWaker::new(), - tx_buf: RingBuffer::new(), - tx_done: AtomicBool::new(true), - rx_waker: AtomicWaker::new(), - rx_buf: RingBuffer::new(), - initialized: AtomicBool::new(false), - } - } -} -// ============================================================================ -// BUFFERED DRIVER STRUCTURES -// ============================================================================ - -/// Buffered LPUART driver -pub struct BufferedLpuart<'a> { - tx: BufferedLpuartTx<'a>, - rx: BufferedLpuartRx<'a>, -} - -/// Buffered LPUART TX driver -pub struct BufferedLpuartTx<'a> { - info: Info, - state: &'static State, - _tx_pin: Peri<'a, AnyPin>, - _cts_pin: Option>, -} - -/// Buffered LPUART RX driver -pub struct BufferedLpuartRx<'a> { - info: Info, - state: &'static State, - _rx_pin: Peri<'a, AnyPin>, - _rts_pin: Option>, -} - -// ============================================================================ -// BUFFERED LPUART IMPLEMENTATION -// ============================================================================ - -impl<'a> BufferedLpuart<'a> { - /// Common initialization logic - fn init_common( - _inner: &Peri<'a, T>, - tx_buffer: Option<&'a mut [u8]>, - rx_buffer: Option<&'a mut [u8]>, - config: &Config, - enable_tx: bool, - enable_rx: bool, - enable_rts: bool, - enable_cts: bool, - ) -> Result<&'static State> { - let state = T::buffered_state(); - - if state.initialized.load(Ordering::Relaxed) { - return Err(Error::InvalidArgument); - } - - // Initialize buffers - if let Some(tx_buffer) = tx_buffer { - if tx_buffer.is_empty() { - return Err(Error::InvalidArgument); - } - unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), tx_buffer.len()) }; - } - - if let Some(rx_buffer) = rx_buffer { - if rx_buffer.is_empty() { - return Err(Error::InvalidArgument); - } - unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_buffer.len()) }; - } - - state.initialized.store(true, Ordering::Relaxed); - - // Enable clocks and initialize hardware - let conf = LpuartConfig { - power: config.power, - source: config.source, - div: config.div, - instance: T::CLOCK_INSTANCE, - }; - let clock_freq = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; - - Self::init_hardware( - T::info().regs, - *config, - clock_freq, - enable_tx, - enable_rx, - enable_rts, - enable_cts, - )?; - - Ok(state) - } - - /// Helper for full-duplex initialization - fn new_inner( - inner: Peri<'a, T>, - tx_pin: Peri<'a, AnyPin>, - rx_pin: Peri<'a, AnyPin>, - rts_pin: Option>, - cts_pin: Option>, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result<(BufferedLpuartTx<'a>, BufferedLpuartRx<'a>)> { - let state = Self::init_common::( - &inner, - Some(tx_buffer), - Some(rx_buffer), - &config, - true, - true, - rts_pin.is_some(), - cts_pin.is_some(), - )?; - - let tx = BufferedLpuartTx { - info: T::info(), - state, - _tx_pin: tx_pin, - _cts_pin: cts_pin, - }; - - let rx = BufferedLpuartRx { - info: T::info(), - state, - _rx_pin: rx_pin, - _rts_pin: rts_pin, - }; - - Ok((tx, rx)) - } - - /// Common hardware initialization logic - fn init_hardware( - regs: &'static mcxa_pac::lpuart0::RegisterBlock, - config: Config, - clock_freq: u32, - enable_tx: bool, - enable_rx: bool, - enable_rts: bool, - enable_cts: bool, - ) -> Result<()> { - // Perform standard initialization - perform_software_reset(regs); - disable_transceiver(regs); - configure_baudrate(regs, config.baudrate_bps, clock_freq)?; - configure_frame_format(regs, &config); - configure_control_settings(regs, &config); - configure_fifo(regs, &config); - clear_all_status_flags(regs); - configure_flow_control(regs, enable_rts, enable_cts, &config); - configure_bit_order(regs, config.msb_first); - - // Enable interrupts for buffered operation - cortex_m::interrupt::free(|_| { - regs.ctrl().modify(|_, w| { - w.rie() - .enabled() // RX interrupt - .orie() - .enabled() // Overrun interrupt - .peie() - .enabled() // Parity error interrupt - .feie() - .enabled() // Framing error interrupt - .neie() - .enabled() // Noise error interrupt - }); - }); - - // Enable the transceiver - enable_transceiver(regs, enable_rx, enable_tx); - - Ok(()) - } - - /// Create a new full duplex buffered LPUART - pub fn new( - inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - rx_pin: Peri<'a, impl RxPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - tx_pin.as_tx(); - rx_pin.as_rx(); - - let (tx, rx) = Self::new_inner::( - inner, - tx_pin.into(), - rx_pin.into(), - None, - None, - tx_buffer, - rx_buffer, - config, - )?; - - Ok(Self { tx, rx }) - } - - /// Create a new buffered LPUART instance with RTS/CTS flow control - pub fn new_with_rtscts( - inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - rx_pin: Peri<'a, impl RxPin>, - rts_pin: Peri<'a, impl RtsPin>, - cts_pin: Peri<'a, impl CtsPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - tx_pin.as_tx(); - rx_pin.as_rx(); - rts_pin.as_rts(); - cts_pin.as_cts(); - - let (tx, rx) = Self::new_inner::( - inner, - tx_pin.into(), - rx_pin.into(), - Some(rts_pin.into()), - Some(cts_pin.into()), - tx_buffer, - rx_buffer, - config, - )?; - - Ok(Self { tx, rx }) - } - - /// Create a new buffered LPUART with only RTS flow control (RX flow control) - pub fn new_with_rts( - inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - rx_pin: Peri<'a, impl RxPin>, - rts_pin: Peri<'a, impl RtsPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - tx_pin.as_tx(); - rx_pin.as_rx(); - rts_pin.as_rts(); - - let (tx, rx) = Self::new_inner::( - inner, - tx_pin.into(), - rx_pin.into(), - Some(rts_pin.into()), - None, - tx_buffer, - rx_buffer, - config, - )?; - - Ok(Self { tx, rx }) - } - - /// Create a new buffered LPUART with only CTS flow control (TX flow control) - pub fn new_with_cts( - inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - rx_pin: Peri<'a, impl RxPin>, - cts_pin: Peri<'a, impl CtsPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - tx_pin.as_tx(); - rx_pin.as_rx(); - cts_pin.as_cts(); - - let (tx, rx) = Self::new_inner::( - inner, - tx_pin.into(), - rx_pin.into(), - None, - Some(cts_pin.into()), - tx_buffer, - rx_buffer, - config, - )?; - - Ok(Self { tx, rx }) - } - - /// Split the buffered LPUART into separate TX and RX parts - pub fn split(self) -> (BufferedLpuartTx<'a>, BufferedLpuartRx<'a>) { - (self.tx, self.rx) - } - - /// Get mutable references to TX and RX parts - pub fn split_ref(&mut self) -> (&mut BufferedLpuartTx<'a>, &mut BufferedLpuartRx<'a>) { - (&mut self.tx, &mut self.rx) - } -} - -// ============================================================================ -// BUFFERED TX IMPLEMENTATION -// ============================================================================ - -impl<'a> BufferedLpuartTx<'a> { - /// Helper for TX-only initialization - fn new_inner( - inner: Peri<'a, T>, - tx_pin: Peri<'a, AnyPin>, - cts_pin: Option>, - tx_buffer: &'a mut [u8], - config: Config, - ) -> Result> { - let state = BufferedLpuart::init_common::( - &inner, - Some(tx_buffer), - None, - &config, - true, - false, - false, - cts_pin.is_some(), - )?; - - Ok(BufferedLpuartTx { - info: T::info(), - state, - _tx_pin: tx_pin, - _cts_pin: cts_pin, - }) - } - - pub fn new( - inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - tx_pin.as_tx(); - - Self::new_inner::(inner, tx_pin.into(), None, tx_buffer, config) - } - - /// Create a new TX-only buffered LPUART with CTS flow control - pub fn new_with_cts( - inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - cts_pin: Peri<'a, impl CtsPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - tx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - tx_pin.as_tx(); - cts_pin.as_cts(); - - Self::new_inner::(inner, tx_pin.into(), Some(cts_pin.into()), tx_buffer, config) - } -} - -impl<'a> BufferedLpuartTx<'a> { - /// Write data asynchronously - pub async fn write(&mut self, buf: &[u8]) -> Result { - let mut written = 0; - - for &byte in buf { - // Wait for space in the buffer - poll_fn(|cx| { - self.state.tx_waker.register(cx.waker()); - - let mut writer = unsafe { self.state.tx_buf.writer() }; - if writer.push_one(byte) { - // Enable TX interrupt to start transmission - cortex_m::interrupt::free(|_| { - self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); - }); - Poll::Ready(Ok(())) - } else { - Poll::Pending - } - }) - .await?; - - written += 1; - } - - Ok(written) - } - - /// Flush the TX buffer and wait for transmission to complete - pub async fn flush(&mut self) -> Result<()> { - // Wait for TX buffer to empty and transmission to complete - poll_fn(|cx| { - self.state.tx_waker.register(cx.waker()); - - let tx_empty = self.state.tx_buf.is_empty(); - let fifo_empty = self.info.regs.water().read().txcount().bits() == 0; - let tc_complete = self.info.regs.stat().read().tc().is_complete(); - - if tx_empty && fifo_empty && tc_complete { - Poll::Ready(Ok(())) - } else { - // Enable appropriate interrupt - cortex_m::interrupt::free(|_| { - if !tx_empty { - self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); - } else { - self.info.regs.ctrl().modify(|_, w| w.tcie().enabled()); - } - }); - Poll::Pending - } - }) - .await - } - - /// Try to write without blocking - pub fn try_write(&mut self, buf: &[u8]) -> Result { - let mut writer = unsafe { self.state.tx_buf.writer() }; - let mut written = 0; - - for &byte in buf { - if writer.push_one(byte) { - written += 1; - } else { - break; - } - } - - if written > 0 { - // Enable TX interrupt to start transmission - cortex_m::interrupt::free(|_| { - self.info.regs.ctrl().modify(|_, w| w.tie().enabled()); - }); - } - - Ok(written) - } -} - -// ============================================================================ -// BUFFERED RX IMPLEMENTATION -// ============================================================================ - -impl<'a> BufferedLpuartRx<'a> { - /// Helper for RX-only initialization - fn new_inner( - inner: Peri<'a, T>, - rx_pin: Peri<'a, AnyPin>, - rts_pin: Option>, - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result> { - let state = BufferedLpuart::init_common::( - &inner, - None, - Some(rx_buffer), - &config, - false, - true, - rts_pin.is_some(), - false, - )?; - - Ok(BufferedLpuartRx { - info: T::info(), - state, - _rx_pin: rx_pin, - _rts_pin: rts_pin, - }) - } - - /// Create a new RX-only buffered LPUART - pub fn new( - inner: Peri<'a, T>, - rx_pin: Peri<'a, impl RxPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - rx_pin.as_rx(); - - Self::new_inner::(inner, rx_pin.into(), None, rx_buffer, config) - } - - /// Create a new RX-only buffered LPUART with RTS flow control - pub fn new_with_rts( - inner: Peri<'a, T>, - rx_pin: Peri<'a, impl RxPin>, - rts_pin: Peri<'a, impl RtsPin>, - _irq: impl interrupt::typelevel::Binding> + 'a, - rx_buffer: &'a mut [u8], - config: Config, - ) -> Result { - rx_pin.as_rx(); - rts_pin.as_rts(); - - Self::new_inner::(inner, rx_pin.into(), Some(rts_pin.into()), rx_buffer, config) - } -} - -impl<'a> BufferedLpuartRx<'a> { - /// Read data asynchronously - pub async fn read(&mut self, buf: &mut [u8]) -> Result { - if buf.is_empty() { - return Ok(0); - } - - let mut read = 0; - - // Try to read available data - poll_fn(|cx| { - self.state.rx_waker.register(cx.waker()); - - // Disable RX interrupt while reading from buffer - cortex_m::interrupt::free(|_| { - self.info.regs.ctrl().modify(|_, w| w.rie().disabled()); - }); - - let mut reader = unsafe { self.state.rx_buf.reader() }; - let available = reader.pop(|data| { - let to_copy = core::cmp::min(data.len(), buf.len() - read); - if to_copy > 0 { - buf[read..read + to_copy].copy_from_slice(&data[..to_copy]); - read += to_copy; - } - to_copy - }); - - // Re-enable RX interrupt - cortex_m::interrupt::free(|_| { - self.info.regs.ctrl().modify(|_, w| w.rie().enabled()); - }); - - if read > 0 { - Poll::Ready(Ok(read)) - } else if available == 0 { - Poll::Pending - } else { - Poll::Ready(Ok(0)) - } - }) - .await - } - - /// Try to read without blocking - pub fn try_read(&mut self, buf: &mut [u8]) -> Result { - if buf.is_empty() { - return Ok(0); - } - - // Disable RX interrupt while reading from buffer - cortex_m::interrupt::free(|_| { - self.info.regs.ctrl().modify(|_, w| w.rie().disabled()); - }); - - let mut reader = unsafe { self.state.rx_buf.reader() }; - let read = reader.pop(|data| { - let to_copy = core::cmp::min(data.len(), buf.len()); - if to_copy > 0 { - buf[..to_copy].copy_from_slice(&data[..to_copy]); - } - to_copy - }); - - // Re-enable RX interrupt - cortex_m::interrupt::free(|_| { - self.info.regs.ctrl().modify(|_, w| w.rie().enabled()); - }); - - Ok(read) - } -} - -// ============================================================================ -// INTERRUPT HANDLER -// ============================================================================ - -/// Buffered UART interrupt handler -pub struct BufferedInterruptHandler { - _phantom: PhantomData, -} - -impl crate::interrupt::typelevel::Handler for BufferedInterruptHandler { - unsafe fn on_interrupt() { - let regs = T::info().regs; - let state = T::buffered_state(); - - // Check if this instance is initialized - if !state.initialized.load(Ordering::Relaxed) { - return; - } - - let ctrl = regs.ctrl().read(); - let stat = regs.stat().read(); - let has_fifo = regs.param().read().rxfifo().bits() > 0; - - // Handle overrun error - if stat.or().is_overrun() { - regs.stat().write(|w| w.or().clear_bit_by_one()); - state.rx_waker.wake(); - return; - } - - // Clear other error flags - if stat.pf().is_parity() { - regs.stat().write(|w| w.pf().clear_bit_by_one()); - } - if stat.fe().is_error() { - regs.stat().write(|w| w.fe().clear_bit_by_one()); - } - if stat.nf().is_noise() { - regs.stat().write(|w| w.nf().clear_bit_by_one()); - } - - // Handle RX data - if ctrl.rie().is_enabled() && (has_data(regs) || stat.idle().is_idle()) { - let mut pushed_any = false; - let mut writer = state.rx_buf.writer(); - - if has_fifo { - // Read from FIFO - while regs.water().read().rxcount().bits() > 0 { - let byte = (regs.data().read().bits() & 0xFF) as u8; - if writer.push_one(byte) { - pushed_any = true; - } else { - // Buffer full, stop reading - break; - } - } - } else { - // Read single byte - if regs.stat().read().rdrf().is_rxdata() { - let byte = (regs.data().read().bits() & 0xFF) as u8; - if writer.push_one(byte) { - pushed_any = true; - } - } - } - - if pushed_any { - state.rx_waker.wake(); - } - - // Clear idle flag if set - if stat.idle().is_idle() { - regs.stat().write(|w| w.idle().clear_bit_by_one()); - } - } - - // Handle TX data - if ctrl.tie().is_enabled() { - let mut sent_any = false; - let mut reader = state.tx_buf.reader(); - - // Send data while TX buffer is ready and we have data - while regs.stat().read().tdre().is_no_txdata() { - if let Some(byte) = reader.pop_one() { - regs.data().write(|w| w.bits(u32::from(byte))); - sent_any = true; - } else { - // No more data to send - break; - } - } - - if sent_any { - state.tx_waker.wake(); - } - - // If buffer is empty, switch to TC interrupt or disable - if state.tx_buf.is_empty() { - cortex_m::interrupt::free(|_| { - regs.ctrl().modify(|_, w| w.tie().disabled().tcie().enabled()); - }); - } - } - - // Handle transmission complete - if ctrl.tcie().is_enabled() && regs.stat().read().tc().is_complete() { - state.tx_done.store(true, Ordering::Release); - state.tx_waker.wake(); - - // Disable TC interrupt - cortex_m::interrupt::free(|_| { - regs.ctrl().modify(|_, w| w.tcie().disabled()); - }); - } - } -} - -// ============================================================================ -// EMBEDDED-IO ASYNC TRAIT IMPLEMENTATIONS -// ============================================================================ - -impl embedded_io_async::ErrorType for BufferedLpuartTx<'_> { - type Error = Error; -} - -impl embedded_io_async::ErrorType for BufferedLpuartRx<'_> { - type Error = Error; -} - -impl embedded_io_async::ErrorType for BufferedLpuart<'_> { - type Error = Error; -} - -impl embedded_io_async::Write for BufferedLpuartTx<'_> { - async fn write(&mut self, buf: &[u8]) -> core::result::Result { - self.write(buf).await - } - - async fn flush(&mut self) -> core::result::Result<(), Self::Error> { - self.flush().await - } -} - -impl embedded_io_async::Read for BufferedLpuartRx<'_> { - async fn read(&mut self, buf: &mut [u8]) -> core::result::Result { - self.read(buf).await - } -} - -impl embedded_io_async::Write for BufferedLpuart<'_> { - async fn write(&mut self, buf: &[u8]) -> core::result::Result { - self.tx.write(buf).await - } - - async fn flush(&mut self) -> core::result::Result<(), Self::Error> { - self.tx.flush().await - } -} - -impl embedded_io_async::Read for BufferedLpuart<'_> { - async fn read(&mut self, buf: &mut [u8]) -> core::result::Result { - self.rx.read(buf).await - } -} diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs deleted file mode 100644 index 2d8308ec8..000000000 --- a/src/lpuart/mod.rs +++ /dev/null @@ -1,1292 +0,0 @@ -use core::marker::PhantomData; - -use embassy_hal_internal::{Peri, PeripheralType}; -use paste::paste; - -use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig}; -use crate::clocks::{enable_and_reset, ClockError, Gate, PoweredClock}; -use crate::gpio::SealedPin; -use crate::pac::lpuart0::baud::Sbns as StopBits; -use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; -use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; -use crate::pac::lpuart0::stat::Msbf as MsbFirst; -use crate::{interrupt, pac, AnyPin}; - -pub mod buffered; - -// ============================================================================ -// STUB IMPLEMENTATION -// ============================================================================ - -// Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API -// Pin and Clock initialization is currently done at the examples level. - -// --- START DMA --- -mod dma { - pub struct Channel<'d> { - pub(super) _lifetime: core::marker::PhantomData<&'d ()>, - } -} - -use dma::Channel; - -// --- END DMA --- - -// ============================================================================ -// MISC -// ============================================================================ - -mod sealed { - /// Simply seal a trait to prevent external implementations - pub trait Sealed {} -} - -// ============================================================================ -// INSTANCE TRAIT -// ============================================================================ - -pub type Regs = &'static crate::pac::lpuart0::RegisterBlock; - -pub trait SealedInstance { - fn info() -> Info; - fn index() -> usize; - fn buffered_state() -> &'static buffered::State; -} - -pub struct Info { - pub regs: Regs, -} - -/// Trait for LPUART peripheral instances -#[allow(private_bounds)] -pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate { - const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance; - type Interrupt: interrupt::typelevel::Interrupt; -} - -macro_rules! impl_instance { - ($($n:expr),*) => { - $( - paste!{ - impl SealedInstance for crate::peripherals::[] { - fn info() -> Info { - Info { - regs: unsafe { &*pac::[]::ptr() }, - } - } - - #[inline] - fn index() -> usize { - $n - } - - fn buffered_state() -> &'static buffered::State { - static BUFFERED_STATE: buffered::State = buffered::State::new(); - &BUFFERED_STATE - } - } - - impl Instance for crate::peripherals::[] { - const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance - = crate::clocks::periph_helpers::LpuartInstance::[]; - type Interrupt = crate::interrupt::typelevel::[]; - } - } - )* - }; -} - -impl_instance!(0, 1, 2, 3, 4, 5); - -// ============================================================================ -// INSTANCE HELPER FUNCTIONS -// ============================================================================ - -/// Perform software reset on the LPUART peripheral -pub fn perform_software_reset(regs: Regs) { - // Software reset - set and clear RST bit (Global register) - regs.global().write(|w| w.rst().reset()); - regs.global().write(|w| w.rst().no_effect()); -} - -/// Disable both transmitter and receiver -pub fn disable_transceiver(regs: Regs) { - regs.ctrl().modify(|_, w| w.te().disabled().re().disabled()); -} - -/// Calculate and configure baudrate settings -pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock_freq: u32) -> Result<()> { - let (osr, sbr) = calculate_baudrate(baudrate_bps, clock_freq)?; - - // Configure BAUD register - regs.baud().modify(|_, w| unsafe { - // Clear and set OSR - w.osr().bits(osr - 1); - // Clear and set SBR - w.sbr().bits(sbr); - // Set BOTHEDGE if OSR is between 4 and 7 - if osr > 3 && osr < 8 { - w.bothedge().enabled() - } else { - w.bothedge().disabled() - } - }); - - Ok(()) -} - -/// Configure frame format (stop bits, data bits) -pub fn configure_frame_format(regs: Regs, config: &Config) { - // Configure stop bits - regs.baud().modify(|_, w| w.sbns().variant(config.stop_bits_count)); - - // Clear M10 for now (10-bit mode) - regs.baud().modify(|_, w| w.m10().disabled()); -} - -/// Configure control settings (parity, data bits, idle config, pin swap) -pub fn configure_control_settings(regs: Regs, config: &Config) { - regs.ctrl().modify(|_, w| { - // Parity configuration - let mut w = if let Some(parity) = config.parity_mode { - w.pe().enabled().pt().variant(parity) - } else { - w.pe().disabled() - }; - - // Data bits configuration - w = match config.data_bits_count { - DataBits::Data8 => { - if config.parity_mode.is_some() { - w.m().data9() // 8 data + 1 parity = 9 bits - } else { - w.m().data8() // 8 data bits only - } - } - DataBits::Data9 => w.m().data9(), - }; - - // Idle configuration - w = w.idlecfg().variant(config.rx_idle_config); - w = w.ilt().variant(config.rx_idle_type); - - // Swap TXD/RXD if configured - if config.swap_txd_rxd { - w.swap().swap() - } else { - w.swap().standard() - } - }); -} - -/// Configure FIFO settings and watermarks -pub fn configure_fifo(regs: Regs, config: &Config) { - // Configure WATER register for FIFO watermarks - regs.water().write(|w| unsafe { - w.rxwater() - .bits(config.rx_fifo_watermark) - .txwater() - .bits(config.tx_fifo_watermark) - }); - - // Enable TX/RX FIFOs - regs.fifo().modify(|_, w| w.txfe().enabled().rxfe().enabled()); - - // Flush FIFOs - regs.fifo() - .modify(|_, w| w.txflush().txfifo_rst().rxflush().rxfifo_rst()); -} - -/// Clear all status flags -pub fn clear_all_status_flags(regs: Regs) { - regs.stat().reset(); -} - -/// Configure hardware flow control if enabled -pub fn configure_flow_control(regs: Regs, enable_tx_cts: bool, enable_rx_rts: bool, config: &Config) { - if enable_rx_rts || enable_tx_cts { - regs.modir().modify(|_, w| { - let mut w = w; - - // Configure TX CTS - w = w.txctsc().variant(config.tx_cts_config); - w = w.txctssrc().variant(config.tx_cts_source); - - if enable_rx_rts { - w = w.rxrtse().enabled(); - } else { - w = w.rxrtse().disabled(); - } - - if enable_tx_cts { - w = w.txctse().enabled(); - } else { - w = w.txctse().disabled(); - } - - w - }); - } -} - -/// Configure bit order (MSB first or LSB first) -pub fn configure_bit_order(regs: Regs, msb_first: MsbFirst) { - regs.stat().modify(|_, w| w.msbf().variant(msb_first)); -} - -/// Enable transmitter and/or receiver based on configuration -pub fn enable_transceiver(regs: Regs, enable_tx: bool, enable_rx: bool) { - regs.ctrl().modify(|_, w| { - let mut w = w; - if enable_tx { - w = w.te().enabled(); - } - if enable_rx { - w = w.re().enabled(); - } - w - }); -} - -pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> { - let mut baud_diff = baudrate; - let mut osr = 0u8; - let mut sbr = 0u16; - - // Try OSR values from 4 to 32 - for osr_temp in 4u8..=32u8 { - // Calculate SBR: (srcClock_Hz * 2 / (baudRate * osr) + 1) / 2 - let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32)).div_ceil(2); - - let sbr_temp = if sbr_calc == 0 { - 1 - } else if sbr_calc > 0x1FFF { - 0x1FFF - } else { - sbr_calc as u16 - }; - - // Calculate actual baud rate - let calculated_baud = src_clock_hz / (osr_temp as u32 * sbr_temp as u32); - - let temp_diff = calculated_baud.abs_diff(baudrate); - - if temp_diff <= baud_diff { - baud_diff = temp_diff; - osr = osr_temp; - sbr = sbr_temp; - } - } - - // Check if baud rate difference is within 3% - if baud_diff > (baudrate / 100) * 3 { - return Err(Error::UnsupportedBaudrate); - } - - Ok((osr, sbr)) -} - -/// Wait for all transmit operations to complete -pub fn wait_for_tx_complete(regs: Regs) { - // Wait for TX FIFO to empty - while regs.water().read().txcount().bits() != 0 { - // Wait for TX FIFO to drain - } - - // Wait for last character to shift out (TC = Transmission Complete) - while regs.stat().read().tc().is_active() { - // Wait for transmission to complete - } -} - -pub fn check_and_clear_rx_errors(regs: Regs) -> Result<()> { - let stat = regs.stat().read(); - let mut status = Ok(()); - - // Check for overrun first - other error flags are prevented when OR is set - if stat.or().is_overrun() { - regs.stat().write(|w| w.or().clear_bit_by_one()); - - return Err(Error::Overrun); - } - - if stat.pf().is_parity() { - regs.stat().write(|w| w.pf().clear_bit_by_one()); - status = Err(Error::Parity); - } - - if stat.fe().is_error() { - regs.stat().write(|w| w.fe().clear_bit_by_one()); - status = Err(Error::Framing); - } - - if stat.nf().is_noise() { - regs.stat().write(|w| w.nf().clear_bit_by_one()); - status = Err(Error::Noise); - } - - status -} - -pub fn has_data(regs: Regs) -> bool { - if regs.param().read().rxfifo().bits() > 0 { - // FIFO is available - check RXCOUNT in WATER register - regs.water().read().rxcount().bits() > 0 - } else { - // No FIFO - check RDRF flag in STAT register - regs.stat().read().rdrf().is_rxdata() - } -} - -// ============================================================================ -// PIN TRAITS FOR LPUART FUNCTIONALITY -// ============================================================================ - -impl sealed::Sealed for T {} - -/// io configuration trait for Lpuart Tx configuration -pub trait TxPin: Into + sealed::Sealed + PeripheralType { - /// convert the pin to appropriate function for Lpuart Tx usage - fn as_tx(&self); -} - -/// io configuration trait for Lpuart Rx configuration -pub trait RxPin: Into + sealed::Sealed + PeripheralType { - /// convert the pin to appropriate function for Lpuart Rx usage - fn as_rx(&self); -} - -/// io configuration trait for Lpuart Cts -pub trait CtsPin: Into + sealed::Sealed + PeripheralType { - /// convert the pin to appropriate function for Lpuart Cts usage - fn as_cts(&self); -} - -/// io configuration trait for Lpuart Rts -pub trait RtsPin: Into + sealed::Sealed + PeripheralType { - /// convert the pin to appropriate function for Lpuart Rts usage - fn as_rts(&self); -} - -macro_rules! impl_tx_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl TxPin for crate::peripherals::$pin { - fn as_tx(&self) { - // TODO: Check these are right - self.set_pull(crate::gpio::Pull::Up); - self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); - self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); - self.set_function(crate::pac::port0::pcr0::Mux::$alt); - self.set_enable_input_buffer(); - } - } - }; -} - -macro_rules! impl_rx_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl RxPin for crate::peripherals::$pin { - fn as_rx(&self) { - // TODO: Check these are right - self.set_pull(crate::gpio::Pull::Up); - self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); - self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); - self.set_function(crate::pac::port0::pcr0::Mux::$alt); - self.set_enable_input_buffer(); - } - } - }; -} - -// TODO: Macro and impls for CTS/RTS pins -macro_rules! impl_cts_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl CtsPin for crate::peripherals::$pin { - fn as_cts(&self) { - todo!() - } - } - }; -} - -macro_rules! impl_rts_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl RtsPin for crate::peripherals::$pin { - fn as_rts(&self) { - todo!() - } - } - }; -} - -// LPUART 0 -impl_tx_pin!(LPUART0, P0_3, Mux2); -impl_tx_pin!(LPUART0, P0_21, Mux3); -impl_tx_pin!(LPUART0, P2_1, Mux2); - -impl_rx_pin!(LPUART0, P0_2, Mux2); -impl_rx_pin!(LPUART0, P0_20, Mux3); -impl_rx_pin!(LPUART0, P2_0, Mux2); - -impl_cts_pin!(LPUART0, P0_1, Mux2); -impl_cts_pin!(LPUART0, P0_23, Mux3); -impl_cts_pin!(LPUART0, P2_3, Mux2); - -impl_rts_pin!(LPUART0, P0_0, Mux2); -impl_rts_pin!(LPUART0, P0_22, Mux3); -impl_rts_pin!(LPUART0, P2_2, Mux2); - -// LPUART 1 -impl_tx_pin!(LPUART1, P1_9, Mux2); -impl_tx_pin!(LPUART1, P2_13, Mux3); -impl_tx_pin!(LPUART1, P3_9, Mux3); -impl_tx_pin!(LPUART1, P3_21, Mux3); - -impl_rx_pin!(LPUART1, P1_8, Mux2); -impl_rx_pin!(LPUART1, P2_12, Mux3); -impl_rx_pin!(LPUART1, P3_8, Mux3); -impl_rx_pin!(LPUART1, P3_20, Mux3); - -impl_cts_pin!(LPUART1, P1_11, Mux2); -impl_cts_pin!(LPUART1, P2_17, Mux3); -impl_cts_pin!(LPUART1, P3_11, Mux3); -impl_cts_pin!(LPUART1, P3_23, Mux3); - -impl_rts_pin!(LPUART1, P1_10, Mux2); -impl_rts_pin!(LPUART1, P2_15, Mux3); -impl_rts_pin!(LPUART1, P2_16, Mux3); -impl_rts_pin!(LPUART1, P3_10, Mux3); - -// LPUART 2 -impl_tx_pin!(LPUART2, P1_5, Mux3); -impl_tx_pin!(LPUART2, P1_13, Mux3); -impl_tx_pin!(LPUART2, P2_2, Mux3); -impl_tx_pin!(LPUART2, P2_10, Mux3); -impl_tx_pin!(LPUART2, P3_15, Mux2); - -impl_rx_pin!(LPUART2, P1_4, Mux3); -impl_rx_pin!(LPUART2, P1_12, Mux3); -impl_rx_pin!(LPUART2, P2_3, Mux3); -impl_rx_pin!(LPUART2, P2_11, Mux3); -impl_rx_pin!(LPUART2, P3_14, Mux2); - -impl_cts_pin!(LPUART2, P1_7, Mux3); -impl_cts_pin!(LPUART2, P1_15, Mux3); -impl_cts_pin!(LPUART2, P2_4, Mux3); -impl_cts_pin!(LPUART2, P3_13, Mux2); - -impl_rts_pin!(LPUART2, P1_6, Mux3); -impl_rts_pin!(LPUART2, P1_14, Mux3); -impl_rts_pin!(LPUART2, P2_5, Mux3); -impl_rts_pin!(LPUART2, P3_12, Mux2); - -// LPUART 3 -impl_tx_pin!(LPUART3, P3_1, Mux3); -impl_tx_pin!(LPUART3, P3_12, Mux3); -impl_tx_pin!(LPUART3, P4_5, Mux3); - -impl_rx_pin!(LPUART3, P3_0, Mux3); -impl_rx_pin!(LPUART3, P3_13, Mux3); -impl_rx_pin!(LPUART3, P4_2, Mux3); - -impl_cts_pin!(LPUART3, P3_7, Mux3); -impl_cts_pin!(LPUART3, P3_14, Mux3); -impl_cts_pin!(LPUART3, P4_6, Mux3); - -impl_rts_pin!(LPUART3, P3_6, Mux3); -impl_rts_pin!(LPUART3, P3_15, Mux3); -impl_rts_pin!(LPUART3, P4_7, Mux3); - -// LPUART 4 -impl_tx_pin!(LPUART4, P2_7, Mux3); -impl_tx_pin!(LPUART4, P3_19, Mux2); -impl_tx_pin!(LPUART4, P3_27, Mux3); -impl_tx_pin!(LPUART4, P4_3, Mux3); - -impl_rx_pin!(LPUART4, P2_6, Mux3); -impl_rx_pin!(LPUART4, P3_18, Mux2); -impl_rx_pin!(LPUART4, P3_28, Mux3); -impl_rx_pin!(LPUART4, P4_4, Mux3); - -impl_cts_pin!(LPUART4, P2_0, Mux3); -impl_cts_pin!(LPUART4, P3_17, Mux2); -impl_cts_pin!(LPUART4, P3_31, Mux3); - -impl_rts_pin!(LPUART4, P2_1, Mux3); -impl_rts_pin!(LPUART4, P3_16, Mux2); -impl_rts_pin!(LPUART4, P3_30, Mux3); - -// LPUART 5 -impl_tx_pin!(LPUART5, P1_10, Mux8); -impl_tx_pin!(LPUART5, P1_17, Mux8); - -impl_rx_pin!(LPUART5, P1_11, Mux8); -impl_rx_pin!(LPUART5, P1_16, Mux8); - -impl_cts_pin!(LPUART5, P1_12, Mux8); -impl_cts_pin!(LPUART5, P1_19, Mux8); - -impl_rts_pin!(LPUART5, P1_13, Mux8); -impl_rts_pin!(LPUART5, P1_18, Mux8); - -// ============================================================================ -// ERROR TYPES AND RESULTS -// ============================================================================ - -/// LPUART error types -#[derive(Debug, Copy, Clone, Eq, PartialEq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Error { - /// Read error - Read, - /// Buffer overflow - Overrun, - /// Noise error - Noise, - /// Framing error - Framing, - /// Parity error - Parity, - /// Failure - Fail, - /// Invalid argument - InvalidArgument, - /// Lpuart baud rate cannot be supported with the given clock - UnsupportedBaudrate, - /// RX FIFO Empty - RxFifoEmpty, - /// TX FIFO Full - TxFifoFull, - /// TX Busy - TxBusy, - /// Clock Error - ClockSetup(ClockError), -} - -/// A specialized Result type for LPUART operations -pub type Result = core::result::Result; - -// ============================================================================ -// CONFIGURATION STRUCTURES -// ============================================================================ - -/// Lpuart config -#[derive(Debug, Clone, Copy)] -pub struct Config { - /// Power state required for this peripheral - pub power: PoweredClock, - /// Clock source - pub source: LpuartClockSel, - /// Clock divisor - pub div: Div4, - /// Baud rate in bits per second - pub baudrate_bps: u32, - /// Parity configuration - pub parity_mode: Option, - /// Number of data bits - pub data_bits_count: DataBits, - /// MSB First or LSB First configuration - pub msb_first: MsbFirst, - /// Number of stop bits - pub stop_bits_count: StopBits, - /// TX FIFO watermark - pub tx_fifo_watermark: u8, - /// RX FIFO watermark - pub rx_fifo_watermark: u8, - /// TX CTS source - pub tx_cts_source: TxCtsSource, - /// TX CTS configure - pub tx_cts_config: TxCtsConfig, - /// RX IDLE type - pub rx_idle_type: IdleType, - /// RX IDLE configuration - pub rx_idle_config: IdleConfig, - /// Swap TXD and RXD pins - pub swap_txd_rxd: bool, -} - -impl Default for Config { - fn default() -> Self { - Self { - baudrate_bps: 115_200u32, - parity_mode: None, - data_bits_count: DataBits::Data8, - msb_first: MsbFirst::LsbFirst, - stop_bits_count: StopBits::One, - tx_fifo_watermark: 0, - rx_fifo_watermark: 1, - tx_cts_source: TxCtsSource::Cts, - tx_cts_config: TxCtsConfig::Start, - rx_idle_type: IdleType::FromStart, - rx_idle_config: IdleConfig::Idle1, - swap_txd_rxd: false, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: LpuartClockSel::FroLfDiv, - div: Div4::no_div(), - } - } -} - -/// LPUART status flags -#[derive(Debug, Clone, Copy)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct Status { - /// Transmit data register empty - pub tx_empty: bool, - /// Transmission complete - pub tx_complete: bool, - /// Receive data register full - pub rx_full: bool, - /// Idle line detected - pub idle: bool, - /// Receiver overrun - pub overrun: bool, - /// Noise error - pub noise: bool, - /// Framing error - pub framing: bool, - /// Parity error - pub parity: bool, -} - -// ============================================================================ -// MODE TRAITS (BLOCKING/ASYNC) -// ============================================================================ - -/// Driver move trait. -#[allow(private_bounds)] -pub trait Mode: sealed::Sealed {} - -/// Blocking mode. -pub struct Blocking; -impl sealed::Sealed for Blocking {} -impl Mode for Blocking {} - -/// Async mode. -pub struct Async; -impl sealed::Sealed for Async {} -impl Mode for Async {} - -// ============================================================================ -// CORE DRIVER STRUCTURES -// ============================================================================ - -/// Lpuart driver. -pub struct Lpuart<'a, M: Mode> { - info: Info, - tx: LpuartTx<'a, M>, - rx: LpuartRx<'a, M>, -} - -/// Lpuart TX driver. -pub struct LpuartTx<'a, M: Mode> { - info: Info, - _tx_pin: Peri<'a, AnyPin>, - _cts_pin: Option>, - _tx_dma: Option>, - mode: PhantomData<(&'a (), M)>, -} - -/// Lpuart Rx driver. -pub struct LpuartRx<'a, M: Mode> { - info: Info, - _rx_pin: Peri<'a, AnyPin>, - _rts_pin: Option>, - _rx_dma: Option>, - mode: PhantomData<(&'a (), M)>, -} - -// ============================================================================ -// LPUART CORE IMPLEMENTATION -// ============================================================================ - -impl<'a, M: Mode> Lpuart<'a, M> { - fn init( - enable_tx: bool, - enable_rx: bool, - enable_tx_cts: bool, - enable_rx_rts: bool, - config: Config, - ) -> Result<()> { - let regs = T::info().regs; - - // Enable clocks - let conf = LpuartConfig { - power: config.power, - source: config.source, - div: config.div, - instance: T::CLOCK_INSTANCE, - }; - let clock_freq = unsafe { enable_and_reset::(&conf).map_err(Error::ClockSetup)? }; - - // Perform initialization sequence - perform_software_reset(regs); - disable_transceiver(regs); - configure_baudrate(regs, config.baudrate_bps, clock_freq)?; - configure_frame_format(regs, &config); - configure_control_settings(regs, &config); - configure_fifo(regs, &config); - clear_all_status_flags(regs); - configure_flow_control(regs, enable_tx_cts, enable_rx_rts, &config); - configure_bit_order(regs, config.msb_first); - enable_transceiver(regs, enable_rx, enable_tx); - - Ok(()) - } - - /// Deinitialize the LPUART peripheral - pub fn deinit(&self) -> Result<()> { - let regs = self.info.regs; - - // Wait for TX operations to complete - wait_for_tx_complete(regs); - - // Clear all status flags - clear_all_status_flags(regs); - - // Disable the module - clear all CTRL register bits - regs.ctrl().reset(); - - Ok(()) - } - - /// Split the Lpuart into a transmitter and receiver - pub fn split(self) -> (LpuartTx<'a, M>, LpuartRx<'a, M>) { - (self.tx, self.rx) - } - - /// Split the Lpuart into a transmitter and receiver by mutable reference - pub fn split_ref(&mut self) -> (&mut LpuartTx<'a, M>, &mut LpuartRx<'a, M>) { - (&mut self.tx, &mut self.rx) - } -} - -// ============================================================================ -// BLOCKING MODE IMPLEMENTATIONS -// ============================================================================ - -impl<'a> Lpuart<'a, Blocking> { - /// Create a new blocking LPUART instance with RX/TX pins. - pub fn new_blocking( - _inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - rx_pin: Peri<'a, impl RxPin>, - config: Config, - ) -> Result { - // Configure the pins for LPUART usage - tx_pin.as_tx(); - rx_pin.as_rx(); - - // Initialize the peripheral - Self::init::(true, true, false, false, config)?; - - Ok(Self { - info: T::info(), - tx: LpuartTx::new_inner(T::info(), tx_pin.into(), None, None), - rx: LpuartRx::new_inner(T::info(), rx_pin.into(), None, None), - }) - } - - /// Create a new blocking LPUART instance with RX, TX and RTS/CTS flow control pins - pub fn new_blocking_with_rtscts( - _inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - rx_pin: Peri<'a, impl RxPin>, - cts_pin: Peri<'a, impl CtsPin>, - rts_pin: Peri<'a, impl RtsPin>, - config: Config, - ) -> Result { - // Configure the pins for LPUART usage - rx_pin.as_rx(); - tx_pin.as_tx(); - rts_pin.as_rts(); - cts_pin.as_cts(); - - // Initialize the peripheral with flow control - Self::init::(true, true, true, true, config)?; - - Ok(Self { - info: T::info(), - rx: LpuartRx::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into()), None), - tx: LpuartTx::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into()), None), - }) - } -} - -// ---------------------------------------------------------------------------- -// Blocking TX Implementation -// ---------------------------------------------------------------------------- - -impl<'a, M: Mode> LpuartTx<'a, M> { - fn new_inner( - info: Info, - tx_pin: Peri<'a, AnyPin>, - cts_pin: Option>, - tx_dma: Option>, - ) -> Self { - Self { - info, - _tx_pin: tx_pin, - _cts_pin: cts_pin, - _tx_dma: tx_dma, - mode: PhantomData, - } - } -} - -impl<'a> LpuartTx<'a, Blocking> { - /// Create a new blocking LPUART transmitter instance - pub fn new_blocking( - _inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - config: Config, - ) -> Result { - // Configure the pins for LPUART usage - tx_pin.as_tx(); - - // Initialize the peripheral - Lpuart::::init::(true, false, false, false, config)?; - - Ok(Self::new_inner(T::info(), tx_pin.into(), None, None)) - } - - /// Create a new blocking LPUART transmitter instance with CTS flow control - pub fn new_blocking_with_cts( - _inner: Peri<'a, T>, - tx_pin: Peri<'a, impl TxPin>, - cts_pin: Peri<'a, impl CtsPin>, - config: Config, - ) -> Result { - tx_pin.as_tx(); - cts_pin.as_cts(); - - Lpuart::::init::(true, false, true, false, config)?; - - Ok(Self::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into()), None)) - } - - fn write_byte_internal(&mut self, byte: u8) -> Result<()> { - self.info.regs.data().modify(|_, w| unsafe { w.bits(u32::from(byte)) }); - - Ok(()) - } - - fn blocking_write_byte(&mut self, byte: u8) -> Result<()> { - while self.info.regs.stat().read().tdre().is_txdata() {} - self.write_byte_internal(byte) - } - - fn write_byte(&mut self, byte: u8) -> Result<()> { - if self.info.regs.stat().read().tdre().is_txdata() { - Err(Error::TxFifoFull) - } else { - self.write_byte_internal(byte) - } - } - - /// Write data to LPUART TX blocking execution until all data is sent. - pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> { - for x in buf { - self.blocking_write_byte(*x)?; - } - - Ok(()) - } - - pub fn write_str_blocking(&mut self, buf: &str) { - let _ = self.blocking_write(buf.as_bytes()); - } - - /// Write data to LPUART TX without blocking. - pub fn write(&mut self, buf: &[u8]) -> Result<()> { - for x in buf { - self.write_byte(*x)?; - } - - Ok(()) - } - - /// Flush LPUART TX blocking execution until all data has been transmitted. - pub fn blocking_flush(&mut self) -> Result<()> { - while self.info.regs.water().read().txcount().bits() != 0 { - // Wait for TX FIFO to drain - } - - // Wait for last character to shift out - while self.info.regs.stat().read().tc().is_active() { - // Wait for transmission to complete - } - - Ok(()) - } - - /// Flush LPUART TX. - pub fn flush(&mut self) -> Result<()> { - // Check if TX FIFO is empty - if self.info.regs.water().read().txcount().bits() != 0 { - return Err(Error::TxBusy); - } - - // Check if transmission is complete - if self.info.regs.stat().read().tc().is_active() { - return Err(Error::TxBusy); - } - - Ok(()) - } -} - -// ---------------------------------------------------------------------------- -// Blocking RX Implementation -// ---------------------------------------------------------------------------- - -impl<'a, M: Mode> LpuartRx<'a, M> { - fn new_inner( - info: Info, - rx_pin: Peri<'a, AnyPin>, - rts_pin: Option>, - rx_dma: Option>, - ) -> Self { - Self { - info, - _rx_pin: rx_pin, - _rts_pin: rts_pin, - _rx_dma: rx_dma, - mode: PhantomData, - } - } -} - -impl<'a> LpuartRx<'a, Blocking> { - /// Create a new blocking LPUART Receiver instance - pub fn new_blocking( - _inner: Peri<'a, T>, - rx_pin: Peri<'a, impl RxPin>, - config: Config, - ) -> Result { - rx_pin.as_rx(); - - Lpuart::::init::(false, true, false, false, config)?; - - Ok(Self::new_inner(T::info(), rx_pin.into(), None, None)) - } - - /// Create a new blocking LPUART Receiver instance with RTS flow control - pub fn new_blocking_with_rts( - _inner: Peri<'a, T>, - rx_pin: Peri<'a, impl RxPin>, - rts_pin: Peri<'a, impl RtsPin>, - config: Config, - ) -> Result { - rx_pin.as_rx(); - rts_pin.as_rts(); - - Lpuart::::init::(false, true, false, true, config)?; - - Ok(Self::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into()), None)) - } - - fn read_byte_internal(&mut self) -> Result { - let data = self.info.regs.data().read(); - - Ok((data.bits() & 0xFF) as u8) - } - - fn read_byte(&mut self) -> Result { - check_and_clear_rx_errors(self.info.regs)?; - - if !has_data(self.info.regs) { - return Err(Error::RxFifoEmpty); - } - - self.read_byte_internal() - } - - fn blocking_read_byte(&mut self) -> Result { - loop { - if has_data(self.info.regs) { - return self.read_byte_internal(); - } - - check_and_clear_rx_errors(self.info.regs)?; - } - } - - /// Read data from LPUART RX without blocking. - pub fn read(&mut self, buf: &mut [u8]) -> Result<()> { - for byte in buf.iter_mut() { - *byte = self.read_byte()?; - } - Ok(()) - } - - /// Read data from LPUART RX blocking execution until the buffer is filled. - pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> { - for byte in buf.iter_mut() { - *byte = self.blocking_read_byte()?; - } - Ok(()) - } -} - -impl<'a> Lpuart<'a, Blocking> { - /// Read data from LPUART RX blocking execution until the buffer is filled - pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> { - self.rx.blocking_read(buf) - } - - /// Read data from LPUART RX without blocking - pub fn read(&mut self, buf: &mut [u8]) -> Result<()> { - self.rx.read(buf) - } - - /// Write data to LPUART TX blocking execution until all data is sent - pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> { - self.tx.blocking_write(buf) - } - - pub fn write_byte(&mut self, byte: u8) -> Result<()> { - self.tx.write_byte(byte) - } - - pub fn read_byte_blocking(&mut self) -> u8 { - loop { - if let Ok(b) = self.rx.read_byte() { - return b; - } - } - } - - pub fn write_str_blocking(&mut self, buf: &str) { - self.tx.write_str_blocking(buf); - } - - /// Write data to LPUART TX without blocking - pub fn write(&mut self, buf: &[u8]) -> Result<()> { - self.tx.write(buf) - } - - /// Flush LPUART TX blocking execution until all data has been transmitted - pub fn blocking_flush(&mut self) -> Result<()> { - self.tx.blocking_flush() - } - - /// Flush LPUART TX without blocking - pub fn flush(&mut self) -> Result<()> { - self.tx.flush() - } -} - -// ============================================================================ -// ASYNC MODE IMPLEMENTATIONS -// ============================================================================ - -// TODO: Implement async mode for LPUART - -// ============================================================================ -// EMBEDDED-HAL 0.2 TRAIT IMPLEMENTATIONS -// ============================================================================ - -impl embedded_hal_02::serial::Read for LpuartRx<'_, Blocking> { - type Error = Error; - - fn read(&mut self) -> core::result::Result> { - let mut buf = [0; 1]; - match self.read(&mut buf) { - Ok(_) => Ok(buf[0]), - Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock), - Err(e) => Err(nb::Error::Other(e)), - } - } -} - -impl embedded_hal_02::serial::Write for LpuartTx<'_, Blocking> { - type Error = Error; - - fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error> { - match self.write(&[word]) { - Ok(_) => Ok(()), - Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock), - Err(e) => Err(nb::Error::Other(e)), - } - } - - fn flush(&mut self) -> core::result::Result<(), nb::Error> { - match self.flush() { - Ok(_) => Ok(()), - Err(Error::TxBusy) => Err(nb::Error::WouldBlock), - Err(e) => Err(nb::Error::Other(e)), - } - } -} - -impl embedded_hal_02::blocking::serial::Write for LpuartTx<'_, Blocking> { - type Error = Error; - - fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> { - self.blocking_write(buffer) - } - - fn bflush(&mut self) -> core::result::Result<(), Self::Error> { - self.blocking_flush() - } -} - -impl embedded_hal_02::serial::Read for Lpuart<'_, Blocking> { - type Error = Error; - - fn read(&mut self) -> core::result::Result> { - embedded_hal_02::serial::Read::read(&mut self.rx) - } -} - -impl embedded_hal_02::serial::Write for Lpuart<'_, Blocking> { - type Error = Error; - - fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error> { - embedded_hal_02::serial::Write::write(&mut self.tx, word) - } - - fn flush(&mut self) -> core::result::Result<(), nb::Error> { - embedded_hal_02::serial::Write::flush(&mut self.tx) - } -} - -impl embedded_hal_02::blocking::serial::Write for Lpuart<'_, Blocking> { - type Error = Error; - - fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> { - self.blocking_write(buffer) - } - - fn bflush(&mut self) -> core::result::Result<(), Self::Error> { - self.blocking_flush() - } -} - -// ============================================================================ -// EMBEDDED-HAL-NB TRAIT IMPLEMENTATIONS -// ============================================================================ - -impl embedded_hal_nb::serial::Error for Error { - fn kind(&self) -> embedded_hal_nb::serial::ErrorKind { - match *self { - Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat, - Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun, - Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity, - Self::Noise => embedded_hal_nb::serial::ErrorKind::Noise, - _ => embedded_hal_nb::serial::ErrorKind::Other, - } - } -} - -impl embedded_hal_nb::serial::ErrorType for LpuartRx<'_, Blocking> { - type Error = Error; -} - -impl embedded_hal_nb::serial::ErrorType for LpuartTx<'_, Blocking> { - type Error = Error; -} - -impl embedded_hal_nb::serial::ErrorType for Lpuart<'_, Blocking> { - type Error = Error; -} - -impl embedded_hal_nb::serial::Read for LpuartRx<'_, Blocking> { - fn read(&mut self) -> nb::Result { - let mut buf = [0; 1]; - match self.read(&mut buf) { - Ok(_) => Ok(buf[0]), - Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock), - Err(e) => Err(nb::Error::Other(e)), - } - } -} - -impl embedded_hal_nb::serial::Write for LpuartTx<'_, Blocking> { - fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { - match self.write(&[word]) { - Ok(_) => Ok(()), - Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock), - Err(e) => Err(nb::Error::Other(e)), - } - } - - fn flush(&mut self) -> nb::Result<(), Self::Error> { - match self.flush() { - Ok(_) => Ok(()), - Err(Error::TxBusy) => Err(nb::Error::WouldBlock), - Err(e) => Err(nb::Error::Other(e)), - } - } -} - -impl embedded_hal_nb::serial::Read for Lpuart<'_, Blocking> { - fn read(&mut self) -> nb::Result { - embedded_hal_nb::serial::Read::read(&mut self.rx) - } -} - -impl embedded_hal_nb::serial::Write for Lpuart<'_, Blocking> { - fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> { - embedded_hal_nb::serial::Write::write(&mut self.tx, char) - } - - fn flush(&mut self) -> nb::Result<(), Self::Error> { - embedded_hal_nb::serial::Write::flush(&mut self.tx) - } -} - -// ============================================================================ -// EMBEDDED-IO TRAIT IMPLEMENTATIONS -// ============================================================================ - -impl embedded_io::Error for Error { - fn kind(&self) -> embedded_io::ErrorKind { - embedded_io::ErrorKind::Other - } -} - -impl embedded_io::ErrorType for LpuartRx<'_, Blocking> { - type Error = Error; -} - -impl embedded_io::ErrorType for LpuartTx<'_, Blocking> { - type Error = Error; -} - -impl embedded_io::ErrorType for Lpuart<'_, Blocking> { - type Error = Error; -} - -impl embedded_io::Read for LpuartRx<'_, Blocking> { - fn read(&mut self, buf: &mut [u8]) -> core::result::Result { - self.blocking_read(buf).map(|_| buf.len()) - } -} - -impl embedded_io::Write for LpuartTx<'_, Blocking> { - fn write(&mut self, buf: &[u8]) -> core::result::Result { - self.blocking_write(buf).map(|_| buf.len()) - } - - fn flush(&mut self) -> core::result::Result<(), Self::Error> { - self.blocking_flush() - } -} - -impl embedded_io::Read for Lpuart<'_, Blocking> { - fn read(&mut self, buf: &mut [u8]) -> core::result::Result { - embedded_io::Read::read(&mut self.rx, buf) - } -} - -impl embedded_io::Write for Lpuart<'_, Blocking> { - fn write(&mut self, buf: &[u8]) -> core::result::Result { - embedded_io::Write::write(&mut self.tx, buf) - } - - fn flush(&mut self) -> core::result::Result<(), Self::Error> { - embedded_io::Write::flush(&mut self.tx) - } -} diff --git a/src/ostimer.rs b/src/ostimer.rs deleted file mode 100644 index c51812e3d..000000000 --- a/src/ostimer.rs +++ /dev/null @@ -1,745 +0,0 @@ -//! # OSTIMER Driver with Robustness Features -//! -//! This module provides an async timer driver for the NXP MCXA276 OSTIMER peripheral -//! with protection against race conditions and timer rollover issues. -//! -//! ## Features -//! -//! - Async timing with embassy-time integration -//! - Gray code counter handling (42-bit counter) -//! - Interrupt-driven wakeups -//! - Configurable interrupt priority -//! - **Race condition protection**: Critical sections and atomic operations -//! - **Timer rollover handling**: Bounds checking and rollover prevention -//! -//! ## Clock Frequency Configuration -//! -//! The OSTIMER frequency depends on your system's clock configuration. You must provide -//! the actual frequency when calling `time_driver::init()`. -//! -//! ## Race Condition Protection -//! - Critical sections in interrupt handlers prevent concurrent access -//! - Atomic register operations with memory barriers -//! - Proper interrupt flag clearing and validation -//! -//! ## Timer Rollover Handling -//! - Bounds checking prevents scheduling beyond timer capacity -//! - Immediate wake for timestamps that would cause rollover issues -#![allow(dead_code)] - -use core::sync::atomic::{AtomicBool, Ordering}; - -use embassy_hal_internal::{Peri, PeripheralType}; - -use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; -use crate::clocks::{assert_reset, enable_and_reset, is_reset_released, release_reset, Gate, PoweredClock}; -use crate::interrupt::InterruptExt; -use crate::pac; - -// PAC defines the shared RegisterBlock under `ostimer0`. -type Regs = pac::ostimer0::RegisterBlock; - -// OSTIMER EVTIMER register layout constants -/// Total width of the EVTIMER counter in bits (42 bits total) -const EVTIMER_TOTAL_BITS: u32 = 42; -/// Width of the low part of EVTIMER (bits 31:0) -const EVTIMER_LO_BITS: u32 = 32; -/// Width of the high part of EVTIMER (bits 41:32) -const EVTIMER_HI_BITS: u32 = 10; -/// Bit position where high part starts in the combined 64-bit value -const EVTIMER_HI_SHIFT: u32 = 32; - -/// Bit mask for the high part of EVTIMER -const EVTIMER_HI_MASK: u16 = (1 << EVTIMER_HI_BITS) - 1; - -/// Maximum value for MATCH_L register (32-bit) -const MATCH_L_MAX: u32 = u32::MAX; -/// Maximum value for MATCH_H register (10-bit) -const MATCH_H_MAX: u16 = EVTIMER_HI_MASK; - -/// Bit mask for extracting the low 32 bits from a 64-bit value -const LOW_32_BIT_MASK: u64 = u32::MAX as u64; - -/// Gray code conversion bit shifts (most significant to least) -const GRAY_CONVERSION_SHIFTS: [u32; 6] = [32, 16, 8, 4, 2, 1]; - -/// Maximum timer value before rollover (2^42 - 1 ticks) -/// Actual rollover time depends on the configured clock frequency -const TIMER_MAX_VALUE: u64 = (1u64 << EVTIMER_TOTAL_BITS) - 1; - -/// Threshold for detecting timer rollover in comparisons (1 second at 1MHz) -const TIMER_ROLLOVER_THRESHOLD: u64 = 1_000_000; - -/// Common default interrupt priority for OSTIMER -const DEFAULT_INTERRUPT_PRIORITY: u8 = 3; - -// Global alarm state for interrupt handling -static ALARM_ACTIVE: AtomicBool = AtomicBool::new(false); -static mut ALARM_CALLBACK: Option = None; -static mut ALARM_FLAG: Option<*const AtomicBool> = None; -static mut ALARM_TARGET_TIME: u64 = 0; - -/// Number of tight spin iterations between elapsed time checks while waiting for MATCH writes to return to the idle (0) state. -const MATCH_WRITE_READY_SPINS: usize = 512; -/// Maximum time (in OSTIMER ticks) to wait for MATCH registers to become writable (~5 ms at 1 MHz). -const MATCH_WRITE_READY_TIMEOUT_TICKS: u64 = 5_000; -/// Short stabilization delay executed after toggling the MRCC reset line to let the OSTIMER bus interface settle. -const RESET_STABILIZE_SPINS: usize = 512; - -pub(super) fn wait_for_match_write_ready(r: &Regs) -> bool { - let start = now_ticks_read(); - let mut spin_budget = 0usize; - - loop { - if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() { - return true; - } - - cortex_m::asm::nop(); - spin_budget += 1; - - if spin_budget >= MATCH_WRITE_READY_SPINS { - spin_budget = 0; - - let elapsed = now_ticks_read().wrapping_sub(start); - if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS { - return false; - } - } - } -} - -pub(super) fn wait_for_match_write_complete(r: &Regs) -> bool { - let start = now_ticks_read(); - let mut spin_budget = 0usize; - - loop { - if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() { - return true; - } - - cortex_m::asm::nop(); - spin_budget += 1; - - if spin_budget >= MATCH_WRITE_READY_SPINS { - spin_budget = 0; - - let elapsed = now_ticks_read().wrapping_sub(start); - if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS { - return false; - } - } - } -} - -fn prime_match_registers(r: &Regs) { - // Disable the interrupt, clear any pending flag, then wait until the MATCH registers are writable. - r.osevent_ctrl() - .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); - - if wait_for_match_write_ready(r) { - r.match_l().write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) }); - r.match_h().write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) }); - let _ = wait_for_match_write_complete(r); - } -} - -/// Single-shot alarm functionality for OSTIMER -pub struct Alarm<'d> { - /// Whether the alarm is currently active - active: AtomicBool, - /// Callback to execute when alarm expires (optional) - callback: Option, - /// Flag that gets set when alarm expires (optional) - flag: Option<&'d AtomicBool>, - _phantom: core::marker::PhantomData<&'d mut ()>, -} - -impl<'d> Default for Alarm<'d> { - fn default() -> Self { - Self::new() - } -} - -impl<'d> Alarm<'d> { - /// Create a new alarm instance - pub fn new() -> Self { - Self { - active: AtomicBool::new(false), - callback: None, - flag: None, - _phantom: core::marker::PhantomData, - } - } - - /// Set a callback that will be executed when the alarm expires - /// Note: Due to interrupt handler constraints, callbacks must be static function pointers - pub fn with_callback(mut self, callback: fn()) -> Self { - self.callback = Some(callback); - self - } - - /// Set a flag that will be set to true when the alarm expires - pub fn with_flag(mut self, flag: &'d AtomicBool) -> Self { - self.flag = Some(flag); - self - } - - /// Check if the alarm is currently active - pub fn is_active(&self) -> bool { - self.active.load(Ordering::Acquire) - } - - /// Cancel the alarm if it's active - pub fn cancel(&self) { - self.active.store(false, Ordering::Release); - } -} - -/// Configuration for Ostimer::new() -#[derive(Copy, Clone)] -pub struct Config { - /// Initialize MATCH registers to their max values and mask/clear the interrupt flag. - pub init_match_max: bool, - pub power: PoweredClock, - pub source: OstimerClockSel, -} - -impl Default for Config { - fn default() -> Self { - Self { - init_match_max: true, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: OstimerClockSel::Clk1M, - } - } -} - -/// OSTIMER peripheral instance -pub struct Ostimer<'d, I: Instance> { - _inst: core::marker::PhantomData, - clock_frequency_hz: u64, - _phantom: core::marker::PhantomData<&'d mut ()>, -} - -impl<'d, I: Instance> Ostimer<'d, I> { - /// Construct OSTIMER handle. - /// Requires clocks for the instance to be enabled by the board before calling. - /// Does not enable NVIC or INTENA; use time_driver::init() for async operation. - pub fn new(_inst: Peri<'d, I>, cfg: Config) -> Self { - let clock_freq = unsafe { - enable_and_reset::(&OsTimerConfig { - power: cfg.power, - source: cfg.source, - }) - .expect("Enabling OsTimer clock should not fail") - }; - - assert!(clock_freq > 0, "OSTIMER frequency must be greater than 0"); - - if cfg.init_match_max { - let r: &Regs = unsafe { &*I::ptr() }; - // Mask INTENA, clear pending flag, and set MATCH to max so no spurious IRQ fires. - prime_match_registers(r); - } - - Self { - _inst: core::marker::PhantomData, - clock_frequency_hz: clock_freq as u64, - _phantom: core::marker::PhantomData, - } - } - - /// Get the configured clock frequency in Hz - pub fn clock_frequency_hz(&self) -> u64 { - self.clock_frequency_hz - } - - /// Read the current timer counter value in timer ticks - /// - /// # Returns - /// Current timer counter value as a 64-bit unsigned integer - pub fn now(&self) -> u64 { - now_ticks_read() - } - - /// Reset the timer counter to zero - /// - /// This performs a hardware reset of the OSTIMER peripheral, which will reset - /// the counter to zero and clear any pending interrupts. Note that this will - /// affect all timer operations including embassy-time. - /// - /// # Safety - /// This operation will reset the entire OSTIMER peripheral. Any active alarms - /// or time_driver operations will be disrupted. Use with caution. - pub fn reset(&self, _peripherals: &crate::pac::Peripherals) { - critical_section::with(|_| { - let r: &Regs = unsafe { &*I::ptr() }; - - // Mask the peripheral interrupt flag before we toggle the reset line so that - // no new NVIC activity races with the reset sequence. - r.osevent_ctrl() - .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); - - unsafe { - assert_reset::(); - - for _ in 0..RESET_STABILIZE_SPINS { - cortex_m::asm::nop(); - } - - release_reset::(); - - while !is_reset_released::() { - cortex_m::asm::nop(); - } - } - - for _ in 0..RESET_STABILIZE_SPINS { - cortex_m::asm::nop(); - } - - // Clear alarm bookkeeping before re-arming MATCH registers. - ALARM_ACTIVE.store(false, Ordering::Release); - unsafe { - ALARM_TARGET_TIME = 0; - ALARM_CALLBACK = None; - ALARM_FLAG = None; - } - - prime_match_registers(r); - }); - - // Ensure no stale OS_EVENT request remains pending after the reset sequence. - crate::interrupt::OS_EVENT.unpend(); - } - - /// Schedule a single-shot alarm to expire after the specified delay in microseconds - /// - /// # Parameters - /// * `alarm` - The alarm instance to schedule - /// * `delay_us` - Delay in microseconds from now - /// - /// # Returns - /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity - pub fn schedule_alarm_delay(&self, alarm: &Alarm, delay_us: u64) -> bool { - let delay_ticks = (delay_us * self.clock_frequency_hz) / 1_000_000; - let target_time = now_ticks_read() + delay_ticks; - self.schedule_alarm_at(alarm, target_time) - } - - /// Schedule a single-shot alarm to expire at the specified absolute time in timer ticks - /// - /// # Parameters - /// * `alarm` - The alarm instance to schedule - /// * `target_ticks` - Absolute time in timer ticks when the alarm should expire - /// - /// # Returns - /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity - pub fn schedule_alarm_at(&self, alarm: &Alarm, target_ticks: u64) -> bool { - let now = now_ticks_read(); - - // Check if target time is in the past - if target_ticks <= now { - // Execute callback immediately if alarm was supposed to be active - if alarm.active.load(Ordering::Acquire) { - alarm.active.store(false, Ordering::Release); - if let Some(callback) = alarm.callback { - callback(); - } - if let Some(flag) = &alarm.flag { - flag.store(true, Ordering::Release); - } - } - return true; - } - - // Check for timer rollover - let max_future = now + TIMER_MAX_VALUE; - if target_ticks > max_future { - return false; // Would exceed timer capacity - } - - // Program the timer - let r: &Regs = unsafe { &*I::ptr() }; - - critical_section::with(|_| { - // Disable interrupt and clear flag - r.osevent_ctrl() - .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); - - if !wait_for_match_write_ready(r) { - prime_match_registers(r); - - if !wait_for_match_write_ready(r) { - alarm.active.store(false, Ordering::Release); - ALARM_ACTIVE.store(false, Ordering::Release); - unsafe { - ALARM_TARGET_TIME = 0; - ALARM_CALLBACK = None; - ALARM_FLAG = None; - } - return false; - } - } - - // Mark alarm as active now that we know the MATCH registers are writable - alarm.active.store(true, Ordering::Release); - - // Set global alarm state for interrupt handler - ALARM_ACTIVE.store(true, Ordering::Release); - unsafe { - ALARM_TARGET_TIME = target_ticks; - ALARM_CALLBACK = alarm.callback; - ALARM_FLAG = alarm.flag.map(|f| f as *const AtomicBool); - } - - // Program MATCH registers (Gray-coded) - let gray = bin_to_gray(target_ticks); - let l = (gray & LOW_32_BIT_MASK) as u32; - let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16; - - r.match_l().write(|w| unsafe { w.match_value().bits(l) }); - r.match_h().write(|w| unsafe { w.match_value().bits(h) }); - - if !wait_for_match_write_complete(r) { - alarm.active.store(false, Ordering::Release); - ALARM_ACTIVE.store(false, Ordering::Release); - unsafe { - ALARM_TARGET_TIME = 0; - ALARM_CALLBACK = None; - ALARM_FLAG = None; - } - return false; - } - - let now_after_program = now_ticks_read(); - let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set(); - if now_after_program >= target_ticks && !intrflag_set { - alarm.active.store(false, Ordering::Release); - ALARM_ACTIVE.store(false, Ordering::Release); - unsafe { - ALARM_TARGET_TIME = 0; - ALARM_CALLBACK = None; - ALARM_FLAG = None; - } - return false; - } - - // Enable interrupt - r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit()); - - true - }) - } - - /// Cancel any active alarm - pub fn cancel_alarm(&self, alarm: &Alarm) { - critical_section::with(|_| { - alarm.cancel(); - - // Clear global alarm state - ALARM_ACTIVE.store(false, Ordering::Release); - unsafe { ALARM_TARGET_TIME = 0 }; - - // Reset MATCH registers to maximum values to prevent spurious interrupts - let r: &Regs = unsafe { &*I::ptr() }; - prime_match_registers(r); - }); - } - - /// Check if an alarm has expired (call this from your interrupt handler) - /// Returns true if the alarm was active and has now expired - pub fn check_alarm_expired(&self, alarm: &Alarm) -> bool { - if alarm.active.load(Ordering::Acquire) { - alarm.active.store(false, Ordering::Release); - - // Execute callback - if let Some(callback) = alarm.callback { - callback(); - } - - // Set flag - if let Some(flag) = &alarm.flag { - flag.store(true, Ordering::Release); - } - - true - } else { - false - } - } -} - -/// Read current EVTIMER (Gray-coded) and convert to binary ticks. -#[inline(always)] -fn now_ticks_read() -> u64 { - let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; - - // Read high then low to minimize incoherent snapshots - let hi = (r.evtimerh().read().evtimer_count_value().bits() as u64) & (EVTIMER_HI_MASK as u64); - let lo = r.evtimerl().read().evtimer_count_value().bits() as u64; - // Combine and convert from Gray code to binary - let gray = lo | (hi << EVTIMER_HI_SHIFT); - gray_to_bin(gray) -} - -// Instance trait like other drivers, providing a PAC pointer for this OSTIMER instance -pub trait Instance: Gate + PeripheralType { - fn ptr() -> *const Regs; -} - -#[cfg(not(feature = "time"))] -impl Instance for crate::peripherals::OSTIMER0 { - #[inline(always)] - fn ptr() -> *const Regs { - pac::Ostimer0::ptr() - } -} - -#[inline(always)] -fn bin_to_gray(x: u64) -> u64 { - x ^ (x >> 1) -} - -#[inline(always)] -fn gray_to_bin(gray: u64) -> u64 { - // More efficient iterative conversion using predefined shifts - let mut bin = gray; - for &shift in &GRAY_CONVERSION_SHIFTS { - bin ^= bin >> shift; - } - bin -} - -#[cfg(feature = "time")] -pub mod time_driver { - use core::sync::atomic::Ordering; - use core::task::Waker; - - use embassy_sync::waitqueue::AtomicWaker; - use embassy_time_driver as etd; - - use super::{ - bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, - EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, - }; - use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; - use crate::clocks::{enable_and_reset, PoweredClock}; - use crate::pac; - - #[allow(non_camel_case_types)] - pub(crate) struct _OSTIMER0_TIME_DRIVER { - _x: (), - } - - // #[cfg(feature = "time")] - // impl_cc_gate!(_OSTIMER0_TIME_DRIVER, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig); - - impl crate::clocks::Gate for _OSTIMER0_TIME_DRIVER { - type MrccPeriphConfig = crate::clocks::periph_helpers::OsTimerConfig; - - #[inline] - unsafe fn enable_clock() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.mrcc_glb_cc1().modify(|_, w| w.ostimer0().enabled()); - } - - #[inline] - unsafe fn disable_clock() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.mrcc_glb_cc1().modify(|_r, w| w.ostimer0().disabled()); - } - - #[inline] - fn is_clock_enabled() -> bool { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.mrcc_glb_cc1().read().ostimer0().is_enabled() - } - - #[inline] - unsafe fn release_reset() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().enabled()); - } - - #[inline] - unsafe fn assert_reset() { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().disabled()); - } - - #[inline] - fn is_reset_released() -> bool { - let mrcc = unsafe { pac::Mrcc0::steal() }; - mrcc.mrcc_glb_rst1().read().ostimer0().is_enabled() - } - } - - pub struct Driver; - static TIMER_WAKER: AtomicWaker = AtomicWaker::new(); - - impl etd::Driver for Driver { - fn now(&self) -> u64 { - // Use the hardware counter (frequency configured in init) - super::now_ticks_read() - } - - fn schedule_wake(&self, timestamp: u64, waker: &Waker) { - let now = self.now(); - - // If timestamp is in the past or very close to now, wake immediately - if timestamp <= now { - waker.wake_by_ref(); - return; - } - - // Prevent scheduling too far in the future (beyond timer rollover) - // This prevents wraparound issues - let max_future = now + super::TIMER_MAX_VALUE; - if timestamp > max_future { - // For very long timeouts, wake immediately to avoid rollover issues - waker.wake_by_ref(); - return; - } - - // Register the waker first so any immediate wake below is observed by the executor. - TIMER_WAKER.register(waker); - - let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; - - critical_section::with(|_| { - // Mask INTENA and clear flag - r.osevent_ctrl() - .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); - - // Read back to ensure W1C took effect on hardware - let _ = r.osevent_ctrl().read().ostimer_intrflag().bit(); - - if !super::wait_for_match_write_ready(r) { - super::prime_match_registers(r); - - if !super::wait_for_match_write_ready(r) { - // If we can't safely program MATCH, wake immediately and leave INTENA masked. - waker.wake_by_ref(); - return; - } - } - - // Program MATCH (Gray-coded). Write low then high, then fence. - let gray = bin_to_gray(timestamp); - let l = (gray & LOW_32_BIT_MASK) as u32; - - let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16; - - r.match_l().write(|w| unsafe { w.match_value().bits(l) }); - r.match_h().write(|w| unsafe { w.match_value().bits(h) }); - - if !super::wait_for_match_write_complete(r) { - waker.wake_by_ref(); - return; - } - - let now_after_program = super::now_ticks_read(); - let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set(); - if now_after_program >= timestamp && !intrflag_set { - waker.wake_by_ref(); - return; - } - - // Enable peripheral interrupt - r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit()); - }); - } - } - - /// Install the global embassy-time driver and configure NVIC priority for OS_EVENT. - /// - /// # Parameters - /// * `priority` - Interrupt priority for the OSTIMER interrupt - /// * `frequency_hz` - Actual OSTIMER clock frequency in Hz (stored for future use) - /// - /// Note: The frequency parameter is currently accepted for API compatibility. - /// The embassy_time_driver macro handles driver registration automatically. - pub fn init(priority: crate::interrupt::Priority, frequency_hz: u64) { - let _clock_freq = unsafe { - enable_and_reset::<_OSTIMER0_TIME_DRIVER>(&OsTimerConfig { - power: PoweredClock::AlwaysEnabled, - source: OstimerClockSel::Clk1M, - }) - .expect("Enabling OsTimer clock should not fail") - }; - - // Mask/clear at peripheral and set default MATCH - let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; - super::prime_match_registers(r); - - // Configure NVIC for timer operation - crate::interrupt::OS_EVENT.configure_for_timer(priority); - - // Note: The embassy_time_driver macro automatically registers the driver - // The frequency parameter is accepted for future compatibility - let _ = frequency_hz; // Suppress unused parameter warning - } - - // Export the global time driver expected by embassy-time - embassy_time_driver::time_driver_impl!(static DRIVER: Driver = Driver); - - /// To be called from the OS_EVENT IRQ. - pub fn on_interrupt() { - let r: &Regs = unsafe { &*pac::Ostimer0::ptr() }; - - // Critical section to prevent races with schedule_wake - critical_section::with(|_| { - // Check if interrupt is actually pending and handle it atomically - if r.osevent_ctrl().read().ostimer_intrflag().bit_is_set() { - // Clear flag and disable interrupt atomically - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() // Write-1-to-clear using safe helper - .ostimer_intena() - .clear_bit() - }); - - // Wake the waiting task - TIMER_WAKER.wake(); - - // Handle alarm callback if active and this interrupt is for the alarm - if ALARM_ACTIVE.load(Ordering::SeqCst) { - let current_time = now_ticks_read(); - let target_time = unsafe { ALARM_TARGET_TIME }; - - // Check if current time is close to alarm target time (within 1000 ticks for timing variations) - if current_time >= target_time && current_time <= target_time + 1000 { - ALARM_ACTIVE.store(false, Ordering::SeqCst); - unsafe { ALARM_TARGET_TIME = 0 }; - - // Execute callback if set - unsafe { - if let Some(callback) = ALARM_CALLBACK { - callback(); - } - } - - // Set flag if provided - unsafe { - if let Some(flag) = ALARM_FLAG { - (*flag).store(true, Ordering::SeqCst); - } - } - } - } - } - }); - } -} - -#[cfg(feature = "time")] -use crate::pac::interrupt; - -#[cfg(feature = "time")] -#[allow(non_snake_case)] -#[interrupt] -fn OS_EVENT() { - time_driver::on_interrupt() -} diff --git a/src/pins.rs b/src/pins.rs deleted file mode 100644 index fdf1b0a86..000000000 --- a/src/pins.rs +++ /dev/null @@ -1,28 +0,0 @@ -//! Pin configuration helpers (separate from peripheral drivers). -use crate::pac; - -pub unsafe fn configure_adc_pins() { - // P1_10 = ADC1_A8 - let port1 = &*pac::Port1::ptr(); - port1.pcr10().write(|w| { - w.ps() - .ps0() - .pe() - .pe0() - .sre() - .sre0() - .ode() - .ode0() - .dse() - .dse0() - .mux() - .mux0() - .ibe() - .ibe0() - .inv() - .inv0() - .lk() - .lk0() - }); - core::arch::asm!("dsb sy; isb sy"); -} diff --git a/src/rtc.rs b/src/rtc.rs deleted file mode 100644 index f975d9c9f..000000000 --- a/src/rtc.rs +++ /dev/null @@ -1,453 +0,0 @@ -//! RTC DateTime driver. -use core::marker::PhantomData; - -use embassy_hal_internal::{Peri, PeripheralType}; -use maitake_sync::WaitCell; - -use crate::clocks::with_clocks; -use crate::interrupt::typelevel::{Handler, Interrupt}; -use crate::pac; -use crate::pac::rtc0::cr::Um; - -type Regs = pac::rtc0::RegisterBlock; - -/// Global wait cell for alarm notifications -static WAKER: WaitCell = WaitCell::new(); - -/// RTC interrupt handler. -pub struct InterruptHandler { - _phantom: PhantomData, -} - -/// Trait for RTC peripheral instances -pub trait Instance: PeripheralType { - type Interrupt: Interrupt; - fn ptr() -> *const Regs; -} - -/// Token for RTC0 -pub type Rtc0 = crate::peripherals::RTC0; -impl Instance for crate::peripherals::RTC0 { - type Interrupt = crate::interrupt::typelevel::RTC; - #[inline(always)] - fn ptr() -> *const Regs { - pac::Rtc0::ptr() - } -} - -/// Number of days in a standard year -const DAYS_IN_A_YEAR: u32 = 365; -/// Number of seconds in a day -const SECONDS_IN_A_DAY: u32 = 86400; -/// Number of seconds in an hour -const SECONDS_IN_A_HOUR: u32 = 3600; -/// Number of seconds in a minute -const SECONDS_IN_A_MINUTE: u32 = 60; -/// Unix epoch start year -const YEAR_RANGE_START: u16 = 1970; - -/// Date and time structure for RTC operations -#[derive(Debug, Clone, Copy)] -pub struct RtcDateTime { - pub year: u16, - pub month: u8, - pub day: u8, - pub hour: u8, - pub minute: u8, - pub second: u8, -} -#[derive(Copy, Clone)] -pub struct RtcConfig { - #[allow(dead_code)] - wakeup_select: bool, - update_mode: Um, - #[allow(dead_code)] - supervisor_access: bool, - compensation_interval: u8, - compensation_time: u8, -} - -/// RTC interrupt enable flags -#[derive(Copy, Clone)] -pub struct RtcInterruptEnable; -impl RtcInterruptEnable { - pub const RTC_TIME_INVALID_INTERRUPT_ENABLE: u32 = 1 << 0; - pub const RTC_TIME_OVERFLOW_INTERRUPT_ENABLE: u32 = 1 << 1; - pub const RTC_ALARM_INTERRUPT_ENABLE: u32 = 1 << 2; - pub const RTC_SECONDS_INTERRUPT_ENABLE: u32 = 1 << 4; -} - -/// Converts a DateTime structure to Unix timestamp (seconds since 1970-01-01) -/// -/// # Arguments -/// -/// * `datetime` - The date and time to convert -/// -/// # Returns -/// -/// Unix timestamp as u32 -/// -/// # Note -/// -/// This function handles leap years correctly. -pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 { - let month_days: [u16; 13] = [0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334]; - - let mut seconds = (datetime.year as u32 - 1970) * DAYS_IN_A_YEAR; - seconds += (datetime.year as u32 / 4) - (1970 / 4); - seconds += month_days[datetime.month as usize] as u32; - seconds += datetime.day as u32 - 1; - - if (datetime.year & 3 == 0) && (datetime.month <= 2) { - seconds -= 1; - } - - seconds = seconds * SECONDS_IN_A_DAY - + (datetime.hour as u32 * SECONDS_IN_A_HOUR) - + (datetime.minute as u32 * SECONDS_IN_A_MINUTE) - + datetime.second as u32; - - seconds -} - -/// Converts Unix timestamp to DateTime structure -/// -/// # Arguments -/// -/// * `seconds` - Unix timestamp (seconds since 1970-01-01) -/// -/// # Returns -/// -/// RtcDateTime structure with the converted date and time -/// -/// # Note -/// -/// This function handles leap years correctly. -pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { - let mut seconds_remaining = seconds; - let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1; - seconds_remaining %= SECONDS_IN_A_DAY; - - let hour = (seconds_remaining / SECONDS_IN_A_HOUR) as u8; - seconds_remaining %= SECONDS_IN_A_HOUR; - let minute = (seconds_remaining / SECONDS_IN_A_MINUTE) as u8; - let second = (seconds_remaining % SECONDS_IN_A_MINUTE) as u8; - - let mut year = YEAR_RANGE_START; - let mut days_in_year = DAYS_IN_A_YEAR; - - while days > days_in_year { - days -= days_in_year; - year += 1; - - days_in_year = if year.is_multiple_of(4) { - DAYS_IN_A_YEAR + 1 - } else { - DAYS_IN_A_YEAR - }; - } - - let days_per_month = [ - 31, - if year.is_multiple_of(4) { 29 } else { 28 }, - 31, - 30, - 31, - 30, - 31, - 31, - 30, - 31, - 30, - 31, - ]; - - let mut month = 1; - for (m, month_days) in days_per_month.iter().enumerate() { - let m = m + 1; - if days <= *month_days as u32 { - month = m; - break; - } else { - days -= *month_days as u32; - } - } - - let day = days as u8; - - RtcDateTime { - year, - month: month as u8, - day, - hour, - minute, - second, - } -} - -/// Returns default RTC configuration -/// -/// # Returns -/// -/// RtcConfig with sensible default values: -/// - No wakeup selection -/// - Update mode 0 (immediate updates) -/// - No supervisor access restriction -/// - No compensation -pub fn get_default_config() -> RtcConfig { - RtcConfig { - wakeup_select: false, - update_mode: Um::Um0, - supervisor_access: false, - compensation_interval: 0, - compensation_time: 0, - } -} -/// Minimal RTC handle for a specific instance I (store the zero-sized token like embassy) -pub struct Rtc<'a, I: Instance> { - _inst: core::marker::PhantomData<&'a mut I>, -} - -impl<'a, I: Instance> Rtc<'a, I> { - /// Create a new instance of the real time clock. - pub fn new( - _inst: Peri<'a, I>, - _irq: impl crate::interrupt::typelevel::Binding> + 'a, - config: RtcConfig, - ) -> Self { - let rtc = unsafe { &*I::ptr() }; - - // The RTC is NOT gated by the MRCC, but we DO need to make sure the 16k clock - // on the vsys domain is active - let clocks = with_clocks(|c| c.clk_16k_vsys.clone()); - match clocks { - None => panic!("Clocks have not been initialized"), - Some(None) => panic!("Clocks initialized, but clk_16k_vsys not active"), - Some(Some(_)) => {} - } - - // RTC reset - rtc.cr().modify(|_, w| w.swr().set_bit()); - rtc.cr().modify(|_, w| w.swr().clear_bit()); - rtc.tsr().write(|w| unsafe { w.bits(1) }); - - rtc.cr().modify(|_, w| w.um().variant(config.update_mode)); - - rtc.tcr().modify(|_, w| unsafe { - w.cir() - .bits(config.compensation_interval) - .tcr() - .bits(config.compensation_time) - }); - - // Enable RTC interrupt - I::Interrupt::unpend(); - unsafe { I::Interrupt::enable() }; - - Self { - _inst: core::marker::PhantomData, - } - } - - /// Set the current date and time - /// - /// # Arguments - /// - /// * `datetime` - The date and time to set - /// - /// # Note - /// - /// The datetime is converted to Unix timestamp and written to the time seconds register. - pub fn set_datetime(&self, datetime: RtcDateTime) { - let rtc = unsafe { &*I::ptr() }; - let seconds = convert_datetime_to_seconds(&datetime); - rtc.tsr().write(|w| unsafe { w.bits(seconds) }); - } - - /// Get the current date and time - /// - /// # Returns - /// - /// Current date and time as RtcDateTime - /// - /// # Note - /// - /// Reads the current Unix timestamp from the time seconds register and converts it. - pub fn get_datetime(&self) -> RtcDateTime { - let rtc = unsafe { &*I::ptr() }; - let seconds = rtc.tsr().read().bits(); - convert_seconds_to_datetime(seconds) - } - - /// Set the alarm date and time - /// - /// # Arguments - /// - /// * `alarm` - The date and time when the alarm should trigger - /// - /// # Note - /// - /// This function: - /// - Clears any existing alarm by writing 0 to the alarm register - /// - Waits for the clear operation to complete - /// - Sets the new alarm time - /// - Waits for the write operation to complete - /// - Uses timeouts to prevent infinite loops - /// - Enables the alarm interrupt after setting - pub fn set_alarm(&self, alarm: RtcDateTime) { - let rtc = unsafe { &*I::ptr() }; - let seconds = convert_datetime_to_seconds(&alarm); - - rtc.tar().write(|w| unsafe { w.bits(0) }); - let mut timeout = 10000; - while rtc.tar().read().bits() != 0 && timeout > 0 { - timeout -= 1; - } - - rtc.tar().write(|w| unsafe { w.bits(seconds) }); - - let mut timeout = 10000; - while rtc.tar().read().bits() != seconds && timeout > 0 { - timeout -= 1; - } - - self.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); - } - - /// Get the current alarm date and time - /// - /// # Returns - /// - /// Alarm date and time as RtcDateTime - /// - /// # Note - /// - /// Reads the alarm timestamp from the time alarm register and converts it. - pub fn get_alarm(&self) -> RtcDateTime { - let rtc = unsafe { &*I::ptr() }; - let alarm_seconds = rtc.tar().read().bits(); - convert_seconds_to_datetime(alarm_seconds) - } - - /// Start the RTC time counter - /// - /// # Note - /// - /// Sets the Time Counter Enable (TCE) bit in the status register. - pub fn start(&self) { - let rtc = unsafe { &*I::ptr() }; - rtc.sr().modify(|_, w| w.tce().set_bit()); - } - - /// Stop the RTC time counter - /// - /// # Note - /// - /// Clears the Time Counter Enable (TCE) bit in the status register. - pub fn stop(&self) { - let rtc = unsafe { &*I::ptr() }; - rtc.sr().modify(|_, w| w.tce().clear_bit()); - } - - /// Enable specific RTC interrupts - /// - /// # Arguments - /// - /// * `mask` - Bitmask of interrupts to enable (use RtcInterruptEnable constants) - /// - /// # Note - /// - /// This function enables the specified interrupt types and resets the alarm occurred flag. - /// Available interrupts: - /// - Time Invalid Interrupt - /// - Time Overflow Interrupt - /// - Alarm Interrupt - /// - Seconds Interrupt - pub fn set_interrupt(&self, mask: u32) { - let rtc = unsafe { &*I::ptr() }; - - if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.tiie().tiie_1()); - } - if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.toie().toie_1()); - } - if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.taie().taie_1()); - } - if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.tsie().tsie_1()); - } - } - - /// Disable specific RTC interrupts - /// - /// # Arguments - /// - /// * `mask` - Bitmask of interrupts to disable (use RtcInterruptEnable constants) - /// - /// # Note - /// - /// This function disables the specified interrupt types. - pub fn disable_interrupt(&self, mask: u32) { - let rtc = unsafe { &*I::ptr() }; - - if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.tiie().tiie_0()); - } - if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.toie().toie_0()); - } - if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.taie().taie_0()); - } - if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 { - rtc.ier().modify(|_, w| w.tsie().tsie_0()); - } - } - - /// Clear the alarm interrupt flag - /// - /// # Note - /// - /// This function clears the Time Alarm Interrupt Enable bit. - pub fn clear_alarm_flag(&self) { - let rtc = unsafe { &*I::ptr() }; - rtc.ier().modify(|_, w| w.taie().clear_bit()); - } - - /// Wait for an RTC alarm to trigger. - /// - /// # Arguments - /// - /// * `alarm` - The date and time when the alarm should trigger - /// This function will wait until the RTC alarm is triggered. - /// If no alarm is scheduled, it will wait indefinitely until one is scheduled and triggered. - pub async fn wait_for_alarm(&mut self, alarm: RtcDateTime) { - let wait = WAKER.subscribe().await; - - self.set_alarm(alarm); - self.start(); - - // REVISIT: propagate error? - let _ = wait.await; - - // Clear the interrupt and disable the alarm after waking up - self.disable_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE); - } -} - -/// RTC interrupt handler -/// -/// This struct implements the interrupt handler for RTC events. -impl Handler for InterruptHandler { - unsafe fn on_interrupt() { - let rtc = &*pac::Rtc0::ptr(); - // Check if this is actually a time alarm interrupt - let sr = rtc.sr().read(); - if sr.taf().bit_is_set() { - rtc.ier().modify(|_, w| w.taie().clear_bit()); - WAKER.wake(); - } - } -} diff --git a/supply-chain/README.md b/supply-chain/README.md deleted file mode 100644 index 12f8777b0..000000000 --- a/supply-chain/README.md +++ /dev/null @@ -1,149 +0,0 @@ -# Working with cargo vet - -## Introduction - -`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity. -It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust. -To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet) - ---- - -## Adding a new dependency - -When updating or adding a new dependency, we need to ensure it's audited before being merged into main. -For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository. -_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._ -Follow the process below to ensure compliance: - -### For Developers -1. **Respond to `cargo vet` failures**: - - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire - - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies - -2. **Engage with auditors**: - - Respond to any questions that the auditors might have regarding the need of any new dependencies - -3. **Rebase and verify**: - - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository - - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet` - ```bash - git fetch upstream - git rebase upstream/main - cargo vet - ``` - -4. **Update PR**: - - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR - - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase - ```bash - git push -f - ``` - -5. **Check PR status**: - - The existing PR comment from the previous failure will be updated with a success message once the check passes - -### For Auditors - -1. **Review the questionnaire**: - - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure - - Respond to the developer comment in case more information is needed - -2. **Audit new dependencies**: - - Inspect the `cargo vet` failures using your preferred method - - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked` - - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked` - - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally) - -3. **Follow `cargo vet` recommendations**: - - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies - -4. **Record audits**: - - Use `cargo vet certify` to add new audits to _audits.toml_ - - Verify all dependencies pass using `cargo vet` - -5. **Decide audit location**: - - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) - - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits - -6. **Communicate successful audit**: - - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass - ---- - -## Audit criteria -`cargo vet` comes pre-equipped with two built-in criteria but supports adding new criteria to suit our needs. -As defined [here](https://mozilla.github.io/cargo-vet/built-in-criteria.html), the default criteria are: - -- **safe-to-run** - This crate can be compiled, run, and tested on a local workstation or in - controlled automation without surprising consequences, such as: - * Reading or writing data from sensitive or unrelated parts of the filesystem. - * Installing software or reconfiguring the device. - * Connecting to untrusted network endpoints. - * Misuse of system resources (e.g. cryptocurrency mining). - -- **safe-to-deploy** - This crate will not introduce a serious security vulnerability to production - software exposed to untrusted input. - - Auditors are not required to perform a full logic review of the entire crate. - Rather, they must review enough to fully reason about the behavior of all unsafe - blocks and usage of powerful imports. For any reasonable usage of the crate in - real-world software, an attacker must not be able to manipulate the runtime - behavior of these sections in an exploitable or surprising way. - - Ideally, all unsafe code is fully sound, and ambient capabilities (e.g. - filesystem access) are hardened against manipulation and consistent with the - advertised behavior of the crate. However, some discretion is permitted. In such - cases, the nature of the discretion should be recorded in the `notes` field of - the audit record. - - For crates which generate deployed code (e.g. build dependencies or procedural - macros), reasonable usage of the crate should output code which meets the above - criteria. - - **Note: `safe-to-deploy` implies `safe-to-run`** - ---- - -## Conducting an audit - -When performing an audit for a new or updated dependency, auditors may consider the following criteria to ensure the safety, reliability, and suitability of the crate for use in our projects: - -- **Security**: - - Review the crate for known vulnerabilities or security advisories. - - Check for unsafe code usage and ensure it is justified and well-documented. - - Evaluate the crate’s history of security issues and responsiveness to reported problems. - -- **Maintenance and Activity**: - - Assess the frequency of updates and the responsiveness of maintainers to issues and pull requests. - - Prefer crates that are actively maintained and have a healthy contributor base. - -- **License Compliance**: - - Verify that the crate’s license is compatible with our project’s licensing requirements. - -- **Community Trust and Adoption**: - - Consider the crate’s adoption in the wider Rust ecosystem. - - Prefer crates that are widely used and trusted by the community. - -- **Functionality and Suitability**: - - Confirm that the crate provides the required functionality without unnecessary features or bloat. - - Evaluate whether the crate’s API is stable and unlikely to introduce breaking changes unexpectedly. - -- **Audit Trail**: - - Record the audit decision, including any concerns, mitigations, or recommendations for future updates. - - If exemptions are granted, document the justification and any follow-up actions required. - ---- - -## Tips for using `cargo vet`: - -- **Update _imports.lock_**: - - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project. - -- **Add exemptions**: - - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption ` to add the dependency to exemptions in _config.toml_ - - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions` - -- **Prune unnecessary entries**: - - Remove unnecessary exemptions and imports using `cargo vet prune` \ No newline at end of file diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml deleted file mode 100644 index 871109648..000000000 --- a/supply-chain/audits.toml +++ /dev/null @@ -1,349 +0,0 @@ - -# cargo-vet audits file - -[[audits.autocfg]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.5.0" - -[[audits.cc]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.2.47" - -[[audits.cfg-if]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.4" - -[[audits.cordyceps]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.3.4" - -[[audits.darling]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.20.11" - -[[audits.darling_core]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.20.11" - -[[audits.darling_macro]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.20.11" - -[[audits.defmt-rtt]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.0" -notes = "defmt-rtt is used for all our logging purposes. Version 1.0.0 merely stabilizes what was already available previously." - -[[audits.defmt-rtt]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 1.1.0" - -[[audits.document-features]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.2.12" - -[[audits.document-features]] -who = "Felipe Balbi " -criteria = "safe-to-run" -version = "0.2.12" - -[[audits.embassy-executor]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.9.1" - -[[audits.embassy-executor-macros]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.7.0" - -[[audits.embassy-executor-timer-queue]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.0" - -[[audits.embassy-executor-timer-queue]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.0" - -[[audits.embassy-time-queue-utils]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.3.0" - -[[audits.find-msvc-tools]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.5" - -[[audits.generator]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.8.7" - -[[audits.ident_case]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.1" - -[[audits.litrs]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.0" - -[[audits.maitake-sync]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.2.2" - -[[audits.mutex-traits]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.1" - -[[audits.mycelium-bitfield]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.5" - -[[audits.once_cell]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.20.1" - -[[audits.panic-probe]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.0" - -[[audits.pin-project]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.1.10" - -[[audits.pin-project-internal]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.1.10" - -[[audits.portable-atomic]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.11.1" - -[[audits.proc-macro2]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.103" - -[[audits.quote]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.42" - -[[audits.stable_deref_trait]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.2.1" - -[[audits.static_cell]] -who = "jerrysxie " -criteria = "safe-to-run" -delta = "2.1.0 -> 2.1.1" - -[[audits.syn]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "2.0.110" - -[[audits.syn]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -delta = "2.0.100 -> 2.0.109" - -[[audits.thiserror]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "2.0.17" - -[[audits.thiserror-impl]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "2.0.17" - -[[audits.unicode-ident]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.22" - -[[audits.valuable]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.1" - -[[trusted.aho-corasick]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-03-28" -end = "2026-11-26" - -[[trusted.cc]] -criteria = "safe-to-deploy" -user-id = 55123 # rust-lang-owner -start = "2022-10-29" -end = "2026-11-26" - -[[trusted.find-msvc-tools]] -criteria = "safe-to-deploy" -user-id = 539 -start = "2025-08-29" -end = "2026-11-26" - -[[trusted.libc]] -criteria = "safe-to-deploy" -user-id = 55123 # rust-lang-owner -start = "2024-08-15" -end = "2026-11-26" - -[[trusted.loom]] -criteria = "safe-to-deploy" -user-id = 6741 # Alice Ryhl (Darksonn) -start = "2021-04-12" -end = "2026-11-26" - -[[trusted.memchr]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-07-07" -end = "2026-11-26" - -[[trusted.paste]] -criteria = "safe-to-deploy" -user-id = 3618 # David Tolnay (dtolnay) -start = "2019-03-19" -end = "2026-11-26" - -[[trusted.regex-automata]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-02-25" -end = "2026-11-26" - -[[trusted.regex-syntax]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-03-30" -end = "2026-11-26" - -[[trusted.rustversion]] -criteria = "safe-to-deploy" -user-id = 3618 # David Tolnay (dtolnay) -start = "2019-07-08" -end = "2026-11-26" - -[[trusted.scoped-tls]] -criteria = "safe-to-deploy" -user-id = 1 # Alex Crichton (alexcrichton) -start = "2019-02-26" -end = "2026-11-26" - -[[trusted.thread_local]] -criteria = "safe-to-deploy" -user-id = 2915 # Amanieu d'Antras (Amanieu) -start = "2019-09-07" -end = "2026-11-26" - -[[trusted.tracing-subscriber]] -criteria = "safe-to-deploy" -user-id = 10 # Carl Lerche (carllerche) -start = "2025-08-29" -end = "2026-11-26" - -[[trusted.valuable]] -criteria = "safe-to-deploy" -user-id = 10 # Carl Lerche (carllerche) -start = "2022-01-03" -end = "2026-11-26" - -[[trusted.windows]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2021-01-15" -end = "2026-11-26" - -[[trusted.windows-collections]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2025-02-06" -end = "2026-11-26" - -[[trusted.windows-core]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2021-11-15" -end = "2026-11-26" - -[[trusted.windows-future]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2025-02-10" -end = "2026-11-26" - -[[trusted.windows-implement]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2022-01-27" -end = "2026-11-26" - -[[trusted.windows-interface]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2022-02-18" -end = "2026-11-26" - -[[trusted.windows-link]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2024-07-17" -end = "2026-11-26" - -[[trusted.windows-numerics]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2023-05-15" -end = "2026-11-26" - -[[trusted.windows-result]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2024-02-02" -end = "2026-11-26" - -[[trusted.windows-strings]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2024-02-02" -end = "2026-11-26" - -[[trusted.windows-sys]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2021-11-15" -end = "2026-11-26" - -[[trusted.windows-threading]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2025-04-29" -end = "2026-11-26" diff --git a/supply-chain/config.toml b/supply-chain/config.toml deleted file mode 100644 index 5682db9ea..000000000 --- a/supply-chain/config.toml +++ /dev/null @@ -1,141 +0,0 @@ - -# cargo-vet config file - -[cargo-vet] -version = "0.10" - -[imports.OpenDevicePartnership] -url = "https://raw.githubusercontent.com/OpenDevicePartnership/rust-crate-audits/main/audits.toml" - -[imports.bytecode-alliance] -url = "https://raw.githubusercontent.com/bytecodealliance/wasmtime/main/supply-chain/audits.toml" - -[imports.google] -url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" - -[imports.mozilla] -url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" - -[[exemptions.bare-metal]] -version = "0.2.5" -criteria = "safe-to-deploy" - -[[exemptions.bitfield]] -version = "0.13.2" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m]] -version = "0.7.7" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m-rt]] -version = "0.7.5" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m-rt-macros]] -version = "0.7.5" -criteria = "safe-to-deploy" - -[[exemptions.critical-section]] -version = "1.2.0" -criteria = "safe-to-deploy" - -[[exemptions.defmt]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.defmt-macros]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.defmt-parser]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-embedded-hal]] -version = "0.5.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-futures]] -version = "0.1.2" -criteria = "safe-to-deploy" - -[[exemptions.embassy-hal-internal]] -version = "0.3.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-sync]] -version = "0.7.2" -criteria = "safe-to-deploy" - -[[exemptions.embassy-time]] -version = "0.5.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-time-driver]] -version = "0.2.1" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal]] -version = "0.2.7" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal-async]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal-nb]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embedded-io-async]] -version = "0.6.1" -criteria = "safe-to-deploy" - -[[exemptions.embedded-storage]] -version = "0.3.1" -criteria = "safe-to-deploy" - -[[exemptions.embedded-storage-async]] -version = "0.4.1" -criteria = "safe-to-deploy" - -[[exemptions.hash32]] -version = "0.3.1" -criteria = "safe-to-deploy" - -[[exemptions.heapless]] -version = "0.8.0" -criteria = "safe-to-deploy" - -[[exemptions.proc-macro-error-attr2]] -version = "2.0.0" -criteria = "safe-to-deploy" - -[[exemptions.proc-macro-error2]] -version = "2.0.1" -criteria = "safe-to-deploy" - -[[exemptions.rustc_version]] -version = "0.2.3" -criteria = "safe-to-deploy" - -[[exemptions.semver]] -version = "0.9.0" -criteria = "safe-to-deploy" - -[[exemptions.semver-parser]] -version = "0.7.0" -criteria = "safe-to-deploy" - -[[exemptions.vcell]] -version = "0.1.3" -criteria = "safe-to-deploy" - -[[exemptions.volatile-register]] -version = "0.2.2" -criteria = "safe-to-deploy" diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock deleted file mode 100644 index dbd1235b0..000000000 --- a/supply-chain/imports.lock +++ /dev/null @@ -1,523 +0,0 @@ - -# cargo-vet imports lock - -[[publisher.aho-corasick]] -version = "1.1.4" -when = "2025-10-28" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.libc]] -version = "0.2.177" -when = "2025-10-09" -user-id = 55123 -user-login = "rust-lang-owner" - -[[publisher.loom]] -version = "0.7.2" -when = "2024-04-23" -user-id = 6741 -user-login = "Darksonn" -user-name = "Alice Ryhl" - -[[publisher.memchr]] -version = "2.7.6" -when = "2025-09-25" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.paste]] -version = "1.0.15" -when = "2024-05-07" -user-id = 3618 -user-login = "dtolnay" -user-name = "David Tolnay" - -[[publisher.regex-automata]] -version = "0.4.13" -when = "2025-10-13" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.regex-syntax]] -version = "0.8.8" -when = "2025-10-13" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.rustversion]] -version = "1.0.22" -when = "2025-08-08" -user-id = 3618 -user-login = "dtolnay" -user-name = "David Tolnay" - -[[publisher.scoped-tls]] -version = "1.0.1" -when = "2022-10-31" -user-id = 1 -user-login = "alexcrichton" -user-name = "Alex Crichton" - -[[publisher.thread_local]] -version = "1.1.9" -when = "2025-06-12" -user-id = 2915 -user-login = "Amanieu" -user-name = "Amanieu d'Antras" - -[[publisher.tracing-subscriber]] -version = "0.3.20" -when = "2025-08-29" -user-id = 10 -user-login = "carllerche" -user-name = "Carl Lerche" - -[[publisher.windows]] -version = "0.61.3" -when = "2025-06-12" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-collections]] -version = "0.2.0" -when = "2025-03-18" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-core]] -version = "0.61.2" -when = "2025-05-19" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-future]] -version = "0.2.1" -when = "2025-05-15" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-implement]] -version = "0.60.2" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-interface]] -version = "0.59.3" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-link]] -version = "0.1.3" -when = "2025-06-12" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-link]] -version = "0.2.1" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-numerics]] -version = "0.2.0" -when = "2025-03-18" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-result]] -version = "0.3.4" -when = "2025-05-19" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-strings]] -version = "0.4.2" -when = "2025-05-19" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-sys]] -version = "0.61.2" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-threading]] -version = "0.1.0" -when = "2025-05-15" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[audits.OpenDevicePartnership.audits] - -[[audits.bytecode-alliance.audits.embedded-io]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "0.4.0" -notes = "No `unsafe` code and only uses `std` in ways one would expect the crate to do so." - -[[audits.bytecode-alliance.audits.embedded-io]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.0 -> 0.6.1" -notes = "Major updates, but almost all safe code. Lots of pruning/deletions, nothing out of the ordrinary." - -[[audits.bytecode-alliance.audits.futures-core]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.3.27" -notes = "Unsafe used to implement a concurrency primitive AtomicWaker. Well-commented and not obviously incorrect. Like my other audits of these concurrency primitives inside the futures family, I couldn't certify that it is correct without formal methods, but that is out of scope for this vetting." - -[[audits.bytecode-alliance.audits.futures-core]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -delta = "0.3.28 -> 0.3.31" - -[[audits.bytecode-alliance.audits.futures-sink]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.3.27" - -[[audits.bytecode-alliance.audits.futures-sink]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -delta = "0.3.28 -> 0.3.31" - -[[audits.bytecode-alliance.audits.log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.22 -> 0.4.27" -notes = "Lots of minor updates to macros and such, nothing touching `unsafe`" - -[[audits.bytecode-alliance.audits.log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.27 -> 0.4.28" -notes = "Minor doc updates and lots new tests, nothing out of the ordinary." - -[[audits.bytecode-alliance.audits.matchers]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.1.0" - -[[audits.bytecode-alliance.audits.matchers]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.0 -> 0.2.0" -notes = "Some unsafe code, but not more than before. Nothing awry." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.46.0" -notes = "one use of unsafe to call windows specific api to get console handle." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.46.0 -> 0.50.1" -notes = "Lots of stylistic/rust-related chanegs, plus new features, but nothing out of the ordrinary." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.50.1 -> 0.50.3" -notes = "CI changes, Rust changes, nothing out of the ordinary." - -[[audits.bytecode-alliance.audits.sharded-slab]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.1.4" -notes = "I always really enjoy reading eliza's code, she left perfect comments at every use of unsafe." - -[[audits.bytecode-alliance.audits.shlex]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "1.1.0" -notes = "Only minor `unsafe` code blocks which look valid and otherwise does what it says on the tin." - -[[audits.bytecode-alliance.audits.tracing-attributes]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.28 -> 0.1.30" -notes = "Few code changes, a pretty minor update." - -[[audits.bytecode-alliance.audits.tracing-core]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.33 -> 0.1.34" -notes = "Mostly just an update with Rust stylistic conventions changing. Nothing awry." - -[[audits.bytecode-alliance.audits.tracing-log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "0.1.3" -notes = """ -This is a standard adapter between the `log` ecosystem and the `tracing` -ecosystem. There's one `unsafe` block in this crate and it's well-scoped. -""" - -[[audits.bytecode-alliance.audits.tracing-log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.3 -> 0.2.0" -notes = "Nothing out of the ordinary, a typical major version update and nothing awry." - -[[audits.google.audits.bitflags]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.3.2" -notes = """ -Security review of earlier versions of the crate can be found at -(Google-internal, sorry): go/image-crate-chromium-security-review - -The crate exposes a function marked as `unsafe`, but doesn't use any -`unsafe` blocks (except for tests of the single `unsafe` function). I -think this justifies marking this crate as `ub-risk-1`. - -Additional review comments can be found at https://crrev.com/c/4723145/31 -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.byteorder]] -who = "danakj " -criteria = "safe-to-deploy" -version = "1.5.0" -notes = "Unsafe review in https://crrev.com/c/5838022" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.lazy_static]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.4.0" -notes = ''' -I grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits. - -There are two places where `unsafe` is used. Unsafe review notes can be found -in https://crrev.com/c/5347418. - -This crate has been added to Chromium in https://crrev.com/c/3321895. -''' -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.lazy_static]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.4.0 -> 1.5.0" -notes = "Unsafe review notes: https://crrev.com/c/5650836" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.log]] -who = "danakj " -criteria = "safe-to-deploy" -version = "0.4.22" -notes = """ -Unsafe review in https://docs.google.com/document/d/1IXQbD1GhTRqNHIGxq6yy7qHqxeO4CwN5noMFXnqyDIM/edit?usp=sharing - -Unsafety is generally very well-documented, with one exception, which we -describe in the review doc. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -version = "1.0.0" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 0.1.3" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 1.1.0" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.num-traits]] -who = "Manish Goregaokar " -criteria = "safe-to-deploy" -version = "0.2.19" -notes = "Contains a single line of float-to-int unsafe with decent safety comments" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.pin-project-lite]] -who = "David Koloski " -criteria = "safe-to-deploy" -version = "0.2.9" -notes = "Reviewed on https://fxrev.dev/824504" -aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.pin-project-lite]] -who = "David Koloski " -criteria = "safe-to-deploy" -delta = "0.2.9 -> 0.2.13" -notes = "Audited at https://fxrev.dev/946396" -aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.smallvec]] -who = "Manish Goregaokar " -criteria = "safe-to-deploy" -version = "1.13.2" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.smallvec]] -who = "Jonathan Hao " -criteria = "safe-to-deploy" -delta = "1.13.2 -> 1.14.0" -notes = """ -WARNING: This certification is a result of a **partial** audit. The -`malloc_size_of` feature has **not** been audited. This feature does -not explicitly document its safety requirements. -See also https://chromium-review.googlesource.com/c/chromium/src/+/6275133/comment/ea0d7a93_98051a2e/ -and https://github.com/servo/malloc_size_of/issues/8. -This feature is banned in gnrt_config.toml. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.void]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -version = "1.0.2" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.mozilla.audits.futures-core]] -who = "Mike Hommey " -criteria = "safe-to-deploy" -delta = "0.3.27 -> 0.3.28" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.futures-sink]] -who = "Mike Hommey " -criteria = "safe-to-deploy" -delta = "0.3.27 -> 0.3.28" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.20.1 -> 1.20.2" -notes = "This update works around a Cargo bug that forces the addition of `portable-atomic` into a lockfile, which we have never needed to use." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.20.2 -> 1.20.3" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.20.3 -> 1.21.1" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.21.1 -> 1.21.3" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.pin-project-lite]] -who = "Mike Hommey " -criteria = "safe-to-deploy" -delta = "0.2.13 -> 0.2.14" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.pin-project-lite]] -who = "Nika Layzell " -criteria = "safe-to-deploy" -delta = "0.2.14 -> 0.2.16" -notes = """ -Only functional change is to work around a bug in the negative_impls feature -(https://github.com/taiki-e/pin-project/issues/340#issuecomment-2432146009) -""" -aggregated-from = "https://raw.githubusercontent.com/mozilla/cargo-vet/main/supply-chain/audits.toml" - -[[audits.mozilla.audits.sharded-slab]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.4 -> 0.1.7" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.shlex]] -who = "Max Inden " -criteria = "safe-to-deploy" -delta = "1.1.0 -> 1.3.0" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.smallvec]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.14.0 -> 1.15.1" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing]] -who = "Alex Franchuk " -criteria = "safe-to-deploy" -version = "0.1.37" -notes = """ -There's only one unsafe impl, and its purpose is to ensure correct behavior by -creating a non-Send marker type (it has nothing to do with soundness). All -dependencies make sense, and no side-effectful std functions are used. -""" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.37 -> 0.1.41" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing-attributes]] -who = "Alex Franchuk " -criteria = "safe-to-deploy" -version = "0.1.24" -notes = "No unsafe code, macros extensively tested and produce reasonable code." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing-attributes]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.24 -> 0.1.28" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing-core]] -who = "Alex Franchuk " -criteria = "safe-to-deploy" -version = "0.1.30" -notes = """ -Most unsafe code is in implementing non-std sync primitives. Unsafe impls are -logically correct and justified in comments, and unsafe code is sound and -justified in comments. -""" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing-core]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.30 -> 0.1.33" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" diff --git a/tools/run_and_attach_rtt.sh b/tools/run_and_attach_rtt.sh deleted file mode 100644 index 13041d06b..000000000 --- a/tools/run_and_attach_rtt.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ELF="${1:-target/thumbv8m.main-none-eabihf/debug/examples/hello}" -PROBE_ID="${2:-1fc9:0143:H3AYDQVQMTROB}" -CHIP="${3:-MCXA276}" -SPEED="${4:-1000}" - -# 1) Flash & run using the existing run.sh (probe is in use only during this step) -./run.sh "$ELF" - -# 2) Give target a short moment to boot and set up RTT CB in RAM -sleep 0.5 - -# 3) Attach RTT/defmt using probe-rs (no flashing) -exec probe-rs attach \ - --chip "$CHIP" \ - --probe "$PROBE_ID" \ - --protocol swd \ - --speed "$SPEED" \ - "$ELF" \ - --rtt-scan-memory \ - --log-format oneline - diff --git a/tools/run_jlink_noblock.sh b/tools/run_jlink_noblock.sh deleted file mode 100644 index 3ea1f2b4b..000000000 --- a/tools/run_jlink_noblock.sh +++ /dev/null @@ -1,76 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ELF="${1:-}" -PROBE_ID="${2:-1366:0101:000600110607}" # default to your J-Link -CHIP="${3:-MCXA276}" -SPEED="${4:-1000}" -PORT="${PROBE_RS_GDB_PORT:-1337}" - -if [[ -z "${ELF}" || ! -f "${ELF}" ]]; then - echo "Usage: $0 [probe-id] [chip] [speed-khz]" >&2 - exit 1 -fi - -if ! command -v probe-rs >/dev/null 2>&1; then - echo "probe-rs not found (cargo install probe-rs --features cli)" >&2 - exit 1 -fi -if ! command -v gdb-multiarch >/dev/null 2>&1; then - echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." >&2 - exit 1 -fi - -# Start probe-rs GDB server -SERVER_LOG=$(mktemp) -probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" --probe "${PROBE_ID}" \ - >"${SERVER_LOG}" 2>&1 & -GDB_SERVER_PID=$! - -# Wait for readiness -for _ in {1..50}; do - if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then break; fi - if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then - echo "probe-rs gdb server failed. Log:" >&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - kill "${GDB_SERVER_PID}" 2>/dev/null || true - exit 1 - fi - sleep 0.1 -done - -# GDB script: load, resume, detach -GDB_SCRIPT=$(mktemp) -cat >"${GDB_SCRIPT}" <&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - kill "${GDB_SERVER_PID}" 2>/dev/null || true - exit 1 -fi - -# Stop server now that we've detached -kill "${GDB_SERVER_PID}" 2>/dev/null || true -rm -f "${GDB_SCRIPT}" "${SERVER_LOG}" || true - -echo "Flashed, resumed, and detached (probe free)." - -- cgit From 277ab0d2e8714edf37a0ee84cda1059d9944ecef Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 18:41:46 +0100 Subject: Move examples to top level example folder --- embassy-mcxa/examples/.cargo/config.toml | 17 - embassy-mcxa/examples/.gitignore | 1 - embassy-mcxa/examples/Cargo.lock | 1555 -------------------- embassy-mcxa/examples/Cargo.toml | 26 - embassy-mcxa/examples/build.rs | 20 - embassy-mcxa/examples/memory.x | 5 - embassy-mcxa/examples/src/bin/adc_interrupt.rs | 84 -- embassy-mcxa/examples/src/bin/adc_polling.rs | 68 - embassy-mcxa/examples/src/bin/blinky.rs | 36 - embassy-mcxa/examples/src/bin/button.rs | 23 - embassy-mcxa/examples/src/bin/button_async.rs | 29 - embassy-mcxa/examples/src/bin/clkout.rs | 69 - embassy-mcxa/examples/src/bin/hello.rs | 119 -- embassy-mcxa/examples/src/bin/i2c-async.rs | 39 - embassy-mcxa/examples/src/bin/i2c-blocking.rs | 31 - embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs | 41 - embassy-mcxa/examples/src/bin/lpuart_buffered.rs | 62 - embassy-mcxa/examples/src/bin/lpuart_polling.rs | 47 - embassy-mcxa/examples/src/bin/rtc_alarm.rs | 47 - embassy-mcxa/examples/src/lib.rs | 16 - examples/mcxa/.cargo/config.toml | 17 + examples/mcxa/.gitignore | 1 + examples/mcxa/Cargo.lock | 1555 ++++++++++++++++++++ examples/mcxa/Cargo.toml | 26 + examples/mcxa/build.rs | 20 + examples/mcxa/memory.x | 5 + examples/mcxa/src/bin/adc_interrupt.rs | 84 ++ examples/mcxa/src/bin/adc_polling.rs | 68 + examples/mcxa/src/bin/blinky.rs | 36 + examples/mcxa/src/bin/button.rs | 23 + examples/mcxa/src/bin/button_async.rs | 29 + examples/mcxa/src/bin/clkout.rs | 69 + examples/mcxa/src/bin/hello.rs | 119 ++ examples/mcxa/src/bin/i2c-async.rs | 39 + examples/mcxa/src/bin/i2c-blocking.rs | 31 + examples/mcxa/src/bin/i2c-scan-blocking.rs | 41 + examples/mcxa/src/bin/lpuart_buffered.rs | 62 + examples/mcxa/src/bin/lpuart_polling.rs | 47 + examples/mcxa/src/bin/rtc_alarm.rs | 47 + examples/mcxa/src/lib.rs | 16 + 40 files changed, 2335 insertions(+), 2335 deletions(-) delete mode 100644 embassy-mcxa/examples/.cargo/config.toml delete mode 100644 embassy-mcxa/examples/.gitignore delete mode 100644 embassy-mcxa/examples/Cargo.lock delete mode 100644 embassy-mcxa/examples/Cargo.toml delete mode 100644 embassy-mcxa/examples/build.rs delete mode 100644 embassy-mcxa/examples/memory.x delete mode 100644 embassy-mcxa/examples/src/bin/adc_interrupt.rs delete mode 100644 embassy-mcxa/examples/src/bin/adc_polling.rs delete mode 100644 embassy-mcxa/examples/src/bin/blinky.rs delete mode 100644 embassy-mcxa/examples/src/bin/button.rs delete mode 100644 embassy-mcxa/examples/src/bin/button_async.rs delete mode 100644 embassy-mcxa/examples/src/bin/clkout.rs delete mode 100644 embassy-mcxa/examples/src/bin/hello.rs delete mode 100644 embassy-mcxa/examples/src/bin/i2c-async.rs delete mode 100644 embassy-mcxa/examples/src/bin/i2c-blocking.rs delete mode 100644 embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs delete mode 100644 embassy-mcxa/examples/src/bin/lpuart_buffered.rs delete mode 100644 embassy-mcxa/examples/src/bin/lpuart_polling.rs delete mode 100644 embassy-mcxa/examples/src/bin/rtc_alarm.rs delete mode 100644 embassy-mcxa/examples/src/lib.rs create mode 100644 examples/mcxa/.cargo/config.toml create mode 100644 examples/mcxa/.gitignore create mode 100644 examples/mcxa/Cargo.lock create mode 100644 examples/mcxa/Cargo.toml create mode 100644 examples/mcxa/build.rs create mode 100644 examples/mcxa/memory.x create mode 100644 examples/mcxa/src/bin/adc_interrupt.rs create mode 100644 examples/mcxa/src/bin/adc_polling.rs create mode 100644 examples/mcxa/src/bin/blinky.rs create mode 100644 examples/mcxa/src/bin/button.rs create mode 100644 examples/mcxa/src/bin/button_async.rs create mode 100644 examples/mcxa/src/bin/clkout.rs create mode 100644 examples/mcxa/src/bin/hello.rs create mode 100644 examples/mcxa/src/bin/i2c-async.rs create mode 100644 examples/mcxa/src/bin/i2c-blocking.rs create mode 100644 examples/mcxa/src/bin/i2c-scan-blocking.rs create mode 100644 examples/mcxa/src/bin/lpuart_buffered.rs create mode 100644 examples/mcxa/src/bin/lpuart_polling.rs create mode 100644 examples/mcxa/src/bin/rtc_alarm.rs create mode 100644 examples/mcxa/src/lib.rs diff --git a/embassy-mcxa/examples/.cargo/config.toml b/embassy-mcxa/examples/.cargo/config.toml deleted file mode 100644 index aedc55b06..000000000 --- a/embassy-mcxa/examples/.cargo/config.toml +++ /dev/null @@ -1,17 +0,0 @@ -[target.thumbv8m.main-none-eabihf] -runner = 'probe-rs run --chip MCXA276 --preverify --verify --protocol swd --speed 12000' - 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"tap", -] diff --git a/embassy-mcxa/examples/Cargo.toml b/embassy-mcxa/examples/Cargo.toml deleted file mode 100644 index a1092c416..000000000 --- a/embassy-mcxa/examples/Cargo.toml +++ /dev/null @@ -1,26 +0,0 @@ -[package] -name = "embassy-mcxa-examples" -version = "0.1.0" -edition = "2021" -license = "MIT OR Apache-2.0" - -[dependencies] -cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -cortex-m-rt = { version = "0.7", features = ["set-sp", "set-vtor"] } -critical-section = "1.2.0" -defmt = "1.0" -defmt-rtt = "1.0" -embassy-embedded-hal = "0.5.0" -embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } -embassy-mcxa = { path = "../", features = ["defmt", "unstable-pac", "time"] } -embassy-sync = "0.7.2" -embassy-time = "0.5.0" -embassy-time-driver = "0.2.1" -embedded-io-async = "0.6.1" -heapless = "0.9.2" -panic-probe = { version = "1.0", features = ["print-defmt"] } -tmp108 = "0.4.0" - -[profile.release] -lto = true # better optimizations -debug = 2 # enough information for defmt/rtt locations diff --git a/embassy-mcxa/examples/build.rs b/embassy-mcxa/examples/build.rs deleted file mode 100644 index f076bba9f..000000000 --- a/embassy-mcxa/examples/build.rs +++ /dev/null @@ -1,20 +0,0 @@ -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; - -fn main() { - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - - // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH" - // cortex-m-rt expects FLASH for code, RAM for data/bss/stack - // Both are in RAM, but separated to satisfy cortex-m-rt's expectations - // MCXA256 has 128KB RAM total - File::create(out.join("memory.x")) - .unwrap() - .write_all(include_bytes!("memory.x")) - .unwrap(); - - println!("cargo:rustc-link-search={}", out.display()); - println!("cargo:rerun-if-changed=memory.x"); -} diff --git a/embassy-mcxa/examples/memory.x b/embassy-mcxa/examples/memory.x deleted file mode 100644 index 315ced58a..000000000 --- a/embassy-mcxa/examples/memory.x +++ /dev/null @@ -1,5 +0,0 @@ -MEMORY -{ - FLASH : ORIGIN = 0x00000000, LENGTH = 1M - RAM : ORIGIN = 0x20000000, LENGTH = 128K -} diff --git a/embassy-mcxa/examples/src/bin/adc_interrupt.rs b/embassy-mcxa/examples/src/bin/adc_interrupt.rs deleted file mode 100644 index 83d8046b3..000000000 --- a/embassy-mcxa/examples/src/bin/adc_interrupt.rs +++ /dev/null @@ -1,84 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa_examples::init_adc_pins; -use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; -use hal::clocks::periph_helpers::{AdcClockSel, Div4}; -use hal::clocks::PoweredClock; -use hal::pac::adc1::cfg::{Pwrsel, Refsel}; -use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::CalAvgs; -use hal::pac::adc1::tctrl::Tcmd; -use hal::{bind_interrupts, InterruptExt}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!(struct Irqs { - ADC1 => hal::adc::AdcHandler; -}); - -#[used] -#[no_mangle] -static KEEP_ADC: unsafe extern "C" fn() = ADC1; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("ADC interrupt Example"); - - unsafe { - init_adc_pins(); - } - - let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: AdcClockSel::FroLfDiv, - div: Div4::no_div(), - }; - let adc = hal::adc::Adc::::new(p.ADC1, adc_config); - - adc.do_offset_calibration(); - adc.do_auto_calibration(); - - let mut conv_command_config = adc.get_default_conv_command_config(); - conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; - conv_command_config.conversion_resolution_mode = Mode::Data16Bits; - adc.set_conv_command_config(1, &conv_command_config); - - let mut conv_trigger_config = adc.get_default_conv_trigger_config(); - conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; - conv_trigger_config.enable_hardware_trigger = false; - adc.set_conv_trigger_config(0, &conv_trigger_config); - - defmt::info!("ADC configuration done..."); - - adc.enable_interrupt(0x1); - - unsafe { - hal::interrupt::ADC1.enable(); - } - - unsafe { - cortex_m::interrupt::enable(); - } - - loop { - adc.do_software_trigger(1); - while !adc.is_interrupt_triggered() { - // Wait until the interrupt is triggered - } - defmt::info!("*** ADC interrupt TRIGGERED! ***"); - //TBD need to print the value - } -} diff --git a/embassy-mcxa/examples/src/bin/adc_polling.rs b/embassy-mcxa/examples/src/bin/adc_polling.rs deleted file mode 100644 index ddf3f586b..000000000 --- a/embassy-mcxa/examples/src/bin/adc_polling.rs +++ /dev/null @@ -1,68 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa_examples::init_adc_pins; -use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; -use hal::clocks::periph_helpers::{AdcClockSel, Div4}; -use hal::clocks::PoweredClock; -use hal::pac::adc1::cfg::{Pwrsel, Refsel}; -use hal::pac::adc1::cmdl1::{Adch, Mode}; -use hal::pac::adc1::ctrl::CalAvgs; -use hal::pac::adc1::tctrl::Tcmd; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -const G_LPADC_RESULT_SHIFT: u32 = 0; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - unsafe { - init_adc_pins(); - } - - defmt::info!("=== ADC polling Example ==="); - - let adc_config = LpadcConfig { - enable_in_doze_mode: true, - conversion_average_mode: CalAvgs::Average128, - enable_analog_preliminary: true, - power_up_delay: 0x80, - reference_voltage_source: Refsel::Option3, - power_level_mode: Pwrsel::Lowest, - trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, - enable_conv_pause: false, - conv_pause_delay: 0, - fifo_watermark: 0, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - source: AdcClockSel::FroLfDiv, - div: Div4::no_div(), - }; - let adc = hal::adc::Adc::::new(p.ADC1, adc_config); - - adc.do_offset_calibration(); - adc.do_auto_calibration(); - - let mut conv_command_config = adc.get_default_conv_command_config(); - conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; - conv_command_config.conversion_resolution_mode = Mode::Data16Bits; - adc.set_conv_command_config(1, &conv_command_config); - - let mut conv_trigger_config = adc.get_default_conv_trigger_config(); - conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; - conv_trigger_config.enable_hardware_trigger = false; - adc.set_conv_trigger_config(0, &conv_trigger_config); - - defmt::info!("=== ADC configuration done... ==="); - - loop { - adc.do_software_trigger(1); - let mut result: Option = None; - while result.is_none() { - result = hal::adc::get_conv_result(); - } - let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; - defmt::info!("value: {=u16}", value); - } -} diff --git a/embassy-mcxa/examples/src/bin/blinky.rs b/embassy-mcxa/examples/src/bin/blinky.rs deleted file mode 100644 index dd08ec0d9..000000000 --- a/embassy-mcxa/examples/src/bin/blinky.rs +++ /dev/null @@ -1,36 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::gpio::{DriveStrength, Level, Output, SlewRate}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("Blink example"); - - let mut red = Output::new(p.P3_18, Level::High, DriveStrength::Normal, SlewRate::Fast); - let mut green = Output::new(p.P3_19, Level::High, DriveStrength::Normal, SlewRate::Fast); - let mut blue = Output::new(p.P3_21, Level::High, DriveStrength::Normal, SlewRate::Fast); - - loop { - defmt::info!("Toggle LEDs"); - - red.toggle(); - Timer::after_millis(250).await; - - red.toggle(); - green.toggle(); - Timer::after_millis(250).await; - - green.toggle(); - blue.toggle(); - Timer::after_millis(250).await; - blue.toggle(); - - Timer::after_millis(250).await; - } -} diff --git a/embassy-mcxa/examples/src/bin/button.rs b/embassy-mcxa/examples/src/bin/button.rs deleted file mode 100644 index 943edbb15..000000000 --- a/embassy-mcxa/examples/src/bin/button.rs +++ /dev/null @@ -1,23 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::gpio::{Input, Pull}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("Button example"); - - // This button is labeled "WAKEUP" on the FRDM-MCXA276 - // The board already has a 10K pullup - let monitor = Input::new(p.P1_7, Pull::Disabled); - - loop { - defmt::info!("Pin level is {:?}", monitor.get_level()); - Timer::after_millis(1000).await; - } -} diff --git a/embassy-mcxa/examples/src/bin/button_async.rs b/embassy-mcxa/examples/src/bin/button_async.rs deleted file mode 100644 index 6cc7b62cd..000000000 --- a/embassy-mcxa/examples/src/bin/button_async.rs +++ /dev/null @@ -1,29 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::gpio::{Input, Pull}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("GPIO interrupt example"); - - // This button is labeled "WAKEUP" on the FRDM-MCXA276 - // The board already has a 10K pullup - let mut pin = Input::new(p.P1_7, Pull::Disabled); - - let mut press_count = 0u32; - - loop { - pin.wait_for_falling_edge().await; - - press_count += 1; - - defmt::info!("Button pressed! Count: {}", press_count); - Timer::after_millis(50).await; - } -} diff --git a/embassy-mcxa/examples/src/bin/clkout.rs b/embassy-mcxa/examples/src/bin/clkout.rs deleted file mode 100644 index bfd963540..000000000 --- a/embassy-mcxa/examples/src/bin/clkout.rs +++ /dev/null @@ -1,69 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4}; -use embassy_mcxa::clocks::PoweredClock; -use embassy_mcxa::gpio::{DriveStrength, SlewRate}; -use embassy_mcxa::{Level, Output}; -use embassy_time::Timer; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -/// Demonstrate CLKOUT, using Pin P4.2 -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - let mut pin = p.P4_2; - let mut clkout = p.CLKOUT; - - loop { - defmt::info!("Set Low..."); - let mut output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); - Timer::after_millis(500).await; - - defmt::info!("Set High..."); - output.set_high(); - Timer::after_millis(400).await; - - defmt::info!("Set Low..."); - output.set_low(); - Timer::after_millis(500).await; - - defmt::info!("16k..."); - // Run Clock Out with the 16K clock - let _clock_out = ClockOut::new( - clkout.reborrow(), - pin.reborrow(), - Config { - sel: ClockOutSel::Clk16K, - div: Div4::no_div(), - level: PoweredClock::NormalEnabledDeepSleepDisabled, - }, - ) - .unwrap(); - - Timer::after_millis(3000).await; - - defmt::info!("Set Low..."); - drop(_clock_out); - - let _output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); - Timer::after_millis(500).await; - - // Run Clock Out with the 12M clock, divided by 3 - defmt::info!("4M..."); - let _clock_out = ClockOut::new( - clkout.reborrow(), - pin.reborrow(), - Config { - sel: ClockOutSel::Fro12M, - div: const { Div4::from_divisor(3).unwrap() }, - level: PoweredClock::NormalEnabledDeepSleepDisabled, - }, - ) - .unwrap(); - - // Let it run for 3 seconds... - Timer::after_millis(3000).await; - } -} diff --git a/embassy-mcxa/examples/src/bin/hello.rs b/embassy-mcxa/examples/src/bin/hello.rs deleted file mode 100644 index e371d9413..000000000 --- a/embassy-mcxa/examples/src/bin/hello.rs +++ /dev/null @@ -1,119 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::config::Div8; -use hal::lpuart::{Blocking, Config, Lpuart}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -/// Simple helper to write a byte as hex to UART -fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) { - const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; - let _ = uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); - let _ = uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); -} - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut cfg = hal::config::Config::default(); - cfg.clock_cfg.sirc.fro_12m_enabled = true; - cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); - let p = hal::init(cfg); - - defmt::info!("boot"); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - let mut uart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - // Print welcome message before any async delays to guarantee early console output - uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); - uart.write_str_blocking("Available commands:\r\n"); - uart.write_str_blocking(" help - Show this help\r\n"); - uart.write_str_blocking(" echo - Echo back the text\r\n"); - uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); - uart.write_str_blocking("Type a command: "); - - let mut buffer = [0u8; 64]; - let mut buf_idx = 0; - - loop { - // Read a byte from UART - let byte = uart.read_byte_blocking(); - - // Echo the character back - if byte == b'\r' || byte == b'\n' { - // Enter pressed - process command - uart.write_str_blocking("\r\n"); - - if buf_idx > 0 { - let command = &buffer[0..buf_idx]; - - if command == b"help" { - uart.write_str_blocking("Available commands:\r\n"); - uart.write_str_blocking(" help - Show this help\r\n"); - uart.write_str_blocking(" echo - Echo back the text\r\n"); - uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); - } else if command.starts_with(b"echo ") && command.len() > 5 { - uart.write_str_blocking("Echo: "); - uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or("")); - uart.write_str_blocking("\r\n"); - } else if command.starts_with(b"hex ") && command.len() > 4 { - // Parse the byte value - let num_str = &command[4..]; - if let Ok(num) = parse_u8(num_str) { - uart.write_str_blocking("Hex: 0x"); - write_hex_byte(&mut uart, num); - uart.write_str_blocking("\r\n"); - } else { - uart.write_str_blocking("Invalid number for hex command\r\n"); - } - } else if !command.is_empty() { - uart.write_str_blocking("Unknown command: "); - uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); - uart.write_str_blocking("\r\n"); - } - } - - // Reset buffer and prompt - buf_idx = 0; - uart.write_str_blocking("Type a command: "); - } else if byte == 8 || byte == 127 { - // Backspace - if buf_idx > 0 { - buf_idx -= 1; - uart.write_str_blocking("\x08 \x08"); // Erase character - } - } else if buf_idx < buffer.len() - 1 { - // Regular character - buffer[buf_idx] = byte; - buf_idx += 1; - let _ = uart.write_byte(byte); - } - } -} - -/// Simple parser for u8 from ASCII bytes -fn parse_u8(bytes: &[u8]) -> Result { - let mut result = 0u8; - for &b in bytes { - if b.is_ascii_digit() { - result = result.checked_mul(10).ok_or(())?; - result = result.checked_add(b - b'0').ok_or(())?; - } else { - return Err(()); - } - } - Ok(result) -} diff --git a/embassy-mcxa/examples/src/bin/i2c-async.rs b/embassy-mcxa/examples/src/bin/i2c-async.rs deleted file mode 100644 index 47b5f3cbe..000000000 --- a/embassy-mcxa/examples/src/bin/i2c-async.rs +++ /dev/null @@ -1,39 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::bind_interrupts; -use hal::clocks::config::Div8; -use hal::config::Config; -use hal::i2c::controller::{self, I2c, Speed}; -use hal::i2c::InterruptHandler; -use hal::peripherals::LPI2C3; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!( - struct Irqs { - LPI2C3 => InterruptHandler; - } -); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut config = Config::default(); - config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); - - let p = hal::init(config); - - defmt::info!("I2C example"); - - let mut config = controller::Config::default(); - config.speed = Speed::Standard; - let mut i2c = I2c::new_async(p.LPI2C3, p.P3_27, p.P3_28, Irqs, config).unwrap(); - let mut buf = [0u8; 2]; - - loop { - i2c.async_write_read(0x48, &[0x00], &mut buf).await.unwrap(); - defmt::info!("Buffer: {:02x}", buf); - Timer::after_secs(1).await; - } -} diff --git a/embassy-mcxa/examples/src/bin/i2c-blocking.rs b/embassy-mcxa/examples/src/bin/i2c-blocking.rs deleted file mode 100644 index 0f6c8cbae..000000000 --- a/embassy-mcxa/examples/src/bin/i2c-blocking.rs +++ /dev/null @@ -1,31 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_time::Timer; -use hal::clocks::config::Div8; -use hal::config::Config; -use hal::i2c::controller::{self, I2c, Speed}; -use tmp108::Tmp108; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut config = Config::default(); - config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); - - let p = hal::init(config); - - defmt::info!("I2C example"); - - let mut config = controller::Config::default(); - config.speed = Speed::Standard; - let i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap(); - let mut tmp = Tmp108::new_with_a0_gnd(i2c); - - loop { - let temperature = tmp.temperature().unwrap(); - defmt::info!("Temperature: {}C", temperature); - Timer::after_secs(1).await; - } -} diff --git a/embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs b/embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs deleted file mode 100644 index 4e203597b..000000000 --- a/embassy-mcxa/examples/src/bin/i2c-scan-blocking.rs +++ /dev/null @@ -1,41 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::gpio::Pull; -use embassy_mcxa::Input; -use embassy_time::Timer; -use hal::clocks::config::Div8; -use hal::config::Config; -use hal::i2c::controller::{self, I2c, Speed}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut config = Config::default(); - config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); - - let p = hal::init(config); - - defmt::info!("I2C example"); - - let mut config = controller::Config::default(); - config.speed = Speed::Standard; - - // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and - // defaults to SWO on the debug peripheral. Explicitly make it a high-z - // input. - let _pin = Input::new(p.P0_2, Pull::Disabled); - let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap(); - - for addr in 0x01..=0x7f { - let result = i2c.blocking_write(addr, &[]); - if result.is_ok() { - defmt::info!("Device found at addr {:02x}", addr); - } - } - - loop { - Timer::after_secs(10).await; - } -} diff --git a/embassy-mcxa/examples/src/bin/lpuart_buffered.rs b/embassy-mcxa/examples/src/bin/lpuart_buffered.rs deleted file mode 100644 index 420589d00..000000000 --- a/embassy-mcxa/examples/src/bin/lpuart_buffered.rs +++ /dev/null @@ -1,62 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::lpuart::buffered::BufferedLpuart; -use embassy_mcxa::lpuart::Config; -use embassy_mcxa::{bind_interrupts, lpuart}; -use embedded_io_async::Write; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver -bind_interrupts!(struct Irqs { - LPUART2 => lpuart::buffered::BufferedInterruptHandler::; -}); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut cfg = hal::config::Config::default(); - cfg.clock_cfg.sirc.fro_12m_enabled = true; - cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); - let p = hal::init(cfg); - - // Configure NVIC for LPUART2 - hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); - - // UART configuration (enable both TX and RX) - let config = Config { - baudrate_bps: 115_200, - rx_fifo_watermark: 0, - tx_fifo_watermark: 0, - ..Default::default() - }; - - let mut tx_buf = [0u8; 256]; - let mut rx_buf = [0u8; 256]; - - // Create a buffered LPUART2 instance with both TX and RX - let mut uart = BufferedLpuart::new( - p.LPUART2, - p.P2_2, // TX pin - p.P2_3, // RX pin - Irqs, - &mut tx_buf, - &mut rx_buf, - config, - ) - .unwrap(); - - // Split into TX and RX parts - let (tx, rx) = uart.split_ref(); - - tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); - tx.write(b"Type characters to echo them back.\r\n").await.unwrap(); - - // Echo loop - let mut buf = [0u8; 4]; - loop { - let used = rx.read(&mut buf).await.unwrap(); - tx.write_all(&buf[..used]).await.unwrap(); - } -} diff --git a/embassy-mcxa/examples/src/bin/lpuart_polling.rs b/embassy-mcxa/examples/src/bin/lpuart_polling.rs deleted file mode 100644 index b80668834..000000000 --- a/embassy-mcxa/examples/src/bin/lpuart_polling.rs +++ /dev/null @@ -1,47 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::clocks::config::Div8; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -use crate::hal::lpuart::{Config, Lpuart}; - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let mut cfg = hal::config::Config::default(); - cfg.clock_cfg.sirc.fro_12m_enabled = true; - cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); - let p = hal::init(cfg); - - defmt::info!("boot"); - - // Create UART configuration - let config = Config { - baudrate_bps: 115_200, - ..Default::default() - }; - - // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX - let lpuart = Lpuart::new_blocking( - p.LPUART2, // Peripheral - p.P2_2, // TX pin - p.P2_3, // RX pin - config, - ) - .unwrap(); - - // Split into separate TX and RX parts - let (mut tx, mut rx) = lpuart.split(); - - // Write hello messages - tx.blocking_write(b"Hello world.\r\n").unwrap(); - tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap(); - - // Echo loop - loop { - let mut buf = [0u8; 1]; - rx.blocking_read(&mut buf).unwrap(); - tx.blocking_write(&buf).unwrap(); - } -} diff --git a/embassy-mcxa/examples/src/bin/rtc_alarm.rs b/embassy-mcxa/examples/src/bin/rtc_alarm.rs deleted file mode 100644 index fe355888b..000000000 --- a/embassy-mcxa/examples/src/bin/rtc_alarm.rs +++ /dev/null @@ -1,47 +0,0 @@ -#![no_std] -#![no_main] - -use embassy_executor::Spawner; -use embassy_mcxa::bind_interrupts; -use hal::rtc::{InterruptHandler, Rtc, RtcDateTime}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -bind_interrupts!(struct Irqs { - RTC => InterruptHandler; -}); - -#[embassy_executor::main] -async fn main(_spawner: Spawner) { - let p = hal::init(hal::config::Config::default()); - - defmt::info!("=== RTC Alarm Example ==="); - - let rtc_config = hal::rtc::get_default_config(); - - let mut rtc = Rtc::new(p.RTC0, Irqs, rtc_config); - - let now = RtcDateTime { - year: 2025, - month: 10, - day: 15, - hour: 14, - minute: 30, - second: 0, - }; - - rtc.stop(); - - defmt::info!("Time set to: 2025-10-15 14:30:00"); - rtc.set_datetime(now); - - let mut alarm = now; - alarm.second += 10; - - defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)"); - defmt::info!("RTC started, waiting for alarm..."); - - rtc.wait_for_alarm(alarm).await; - defmt::info!("*** ALARM TRIGGERED! ***"); - - defmt::info!("Example complete - Test PASSED!"); -} diff --git a/embassy-mcxa/examples/src/lib.rs b/embassy-mcxa/examples/src/lib.rs deleted file mode 100644 index 2573a6adc..000000000 --- a/embassy-mcxa/examples/src/lib.rs +++ /dev/null @@ -1,16 +0,0 @@ -#![no_std] -#![allow(clippy::missing_safety_doc)] - -//! Shared board-specific helpers for the FRDM-MCXA276 examples. -//! These live with the examples so the HAL stays generic. - -use hal::{clocks, pins}; -use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; - -/// Initialize clocks and pin muxing for ADC. -pub unsafe fn init_adc_pins() { - // NOTE: Lpuart has been updated to properly enable + reset its own clocks. - // GPIO has not. - _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); - pins::configure_adc_pins(); -} diff --git a/examples/mcxa/.cargo/config.toml b/examples/mcxa/.cargo/config.toml new file mode 100644 index 000000000..aedc55b06 --- /dev/null +++ b/examples/mcxa/.cargo/config.toml @@ -0,0 +1,17 @@ +[target.thumbv8m.main-none-eabihf] +runner = 'probe-rs run --chip MCXA276 --preverify --verify --protocol swd --speed 12000' + +rustflags = [ + "-C", "linker=flip-link", + "-C", "link-arg=-Tlink.x", + "-C", "link-arg=-Tdefmt.x", + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See 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["critical-section-single-core"] } +cortex-m-rt = { version = "0.7", features = ["set-sp", "set-vtor"] } +critical-section = "1.2.0" +defmt = "1.0" +defmt-rtt = "1.0" +embassy-embedded-hal = "0.5.0" +embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } +embassy-mcxa = { path = "../../embassy-mcxa", features = ["defmt", "unstable-pac", "time"] } +embassy-sync = "0.7.2" +embassy-time = "0.5.0" +embassy-time-driver = "0.2.1" +embedded-io-async = "0.6.1" +heapless = "0.9.2" +panic-probe = { version = "1.0", features = ["print-defmt"] } +tmp108 = "0.4.0" + +[profile.release] +lto = true # better optimizations +debug = 2 # enough information for defmt/rtt locations diff --git a/examples/mcxa/build.rs b/examples/mcxa/build.rs new file mode 100644 index 000000000..f076bba9f --- /dev/null +++ b/examples/mcxa/build.rs @@ -0,0 +1,20 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + + // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH" + // cortex-m-rt expects FLASH for code, RAM for data/bss/stack + // Both are in RAM, but separated to satisfy cortex-m-rt's expectations + // MCXA256 has 128KB RAM total + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=memory.x"); +} diff --git a/examples/mcxa/memory.x b/examples/mcxa/memory.x new file mode 100644 index 000000000..315ced58a --- /dev/null +++ b/examples/mcxa/memory.x @@ -0,0 +1,5 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 1M + RAM : ORIGIN = 0x20000000, LENGTH = 128K +} diff --git a/examples/mcxa/src/bin/adc_interrupt.rs b/examples/mcxa/src/bin/adc_interrupt.rs new file mode 100644 index 000000000..83d8046b3 --- /dev/null +++ b/examples/mcxa/src/bin/adc_interrupt.rs @@ -0,0 +1,84 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::init_adc_pins; +use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; +use hal::clocks::periph_helpers::{AdcClockSel, Div4}; +use hal::clocks::PoweredClock; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; +use hal::{bind_interrupts, InterruptExt}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!(struct Irqs { + ADC1 => hal::adc::AdcHandler; +}); + +#[used] +#[no_mangle] +static KEEP_ADC: unsafe extern "C" fn() = ADC1; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("ADC interrupt Example"); + + unsafe { + init_adc_pins(); + } + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + defmt::info!("ADC configuration done..."); + + adc.enable_interrupt(0x1); + + unsafe { + hal::interrupt::ADC1.enable(); + } + + unsafe { + cortex_m::interrupt::enable(); + } + + loop { + adc.do_software_trigger(1); + while !adc.is_interrupt_triggered() { + // Wait until the interrupt is triggered + } + defmt::info!("*** ADC interrupt TRIGGERED! ***"); + //TBD need to print the value + } +} diff --git a/examples/mcxa/src/bin/adc_polling.rs b/examples/mcxa/src/bin/adc_polling.rs new file mode 100644 index 000000000..ddf3f586b --- /dev/null +++ b/examples/mcxa/src/bin/adc_polling.rs @@ -0,0 +1,68 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa_examples::init_adc_pins; +use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; +use hal::clocks::periph_helpers::{AdcClockSel, Div4}; +use hal::clocks::PoweredClock; +use hal::pac::adc1::cfg::{Pwrsel, Refsel}; +use hal::pac::adc1::cmdl1::{Adch, Mode}; +use hal::pac::adc1::ctrl::CalAvgs; +use hal::pac::adc1::tctrl::Tcmd; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +const G_LPADC_RESULT_SHIFT: u32 = 0; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + unsafe { + init_adc_pins(); + } + + defmt::info!("=== ADC polling Example ==="); + + let adc_config = LpadcConfig { + enable_in_doze_mode: true, + conversion_average_mode: CalAvgs::Average128, + enable_analog_preliminary: true, + power_up_delay: 0x80, + reference_voltage_source: Refsel::Option3, + power_level_mode: Pwrsel::Lowest, + trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, + enable_conv_pause: false, + conv_pause_delay: 0, + fifo_watermark: 0, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + source: AdcClockSel::FroLfDiv, + div: Div4::no_div(), + }; + let adc = hal::adc::Adc::::new(p.ADC1, adc_config); + + adc.do_offset_calibration(); + adc.do_auto_calibration(); + + let mut conv_command_config = adc.get_default_conv_command_config(); + conv_command_config.channel_number = Adch::SelectCorrespondingChannel8; + conv_command_config.conversion_resolution_mode = Mode::Data16Bits; + adc.set_conv_command_config(1, &conv_command_config); + + let mut conv_trigger_config = adc.get_default_conv_trigger_config(); + conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1; + conv_trigger_config.enable_hardware_trigger = false; + adc.set_conv_trigger_config(0, &conv_trigger_config); + + defmt::info!("=== ADC configuration done... ==="); + + loop { + adc.do_software_trigger(1); + let mut result: Option = None; + while result.is_none() { + result = hal::adc::get_conv_result(); + } + let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT; + defmt::info!("value: {=u16}", value); + } +} diff --git a/examples/mcxa/src/bin/blinky.rs b/examples/mcxa/src/bin/blinky.rs new file mode 100644 index 000000000..dd08ec0d9 --- /dev/null +++ b/examples/mcxa/src/bin/blinky.rs @@ -0,0 +1,36 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{DriveStrength, Level, Output, SlewRate}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("Blink example"); + + let mut red = Output::new(p.P3_18, Level::High, DriveStrength::Normal, SlewRate::Fast); + let mut green = Output::new(p.P3_19, Level::High, DriveStrength::Normal, SlewRate::Fast); + let mut blue = Output::new(p.P3_21, Level::High, DriveStrength::Normal, SlewRate::Fast); + + loop { + defmt::info!("Toggle LEDs"); + + red.toggle(); + Timer::after_millis(250).await; + + red.toggle(); + green.toggle(); + Timer::after_millis(250).await; + + green.toggle(); + blue.toggle(); + Timer::after_millis(250).await; + blue.toggle(); + + Timer::after_millis(250).await; + } +} diff --git a/examples/mcxa/src/bin/button.rs b/examples/mcxa/src/bin/button.rs new file mode 100644 index 000000000..943edbb15 --- /dev/null +++ b/examples/mcxa/src/bin/button.rs @@ -0,0 +1,23 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{Input, Pull}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("Button example"); + + // This button is labeled "WAKEUP" on the FRDM-MCXA276 + // The board already has a 10K pullup + let monitor = Input::new(p.P1_7, Pull::Disabled); + + loop { + defmt::info!("Pin level is {:?}", monitor.get_level()); + Timer::after_millis(1000).await; + } +} diff --git a/examples/mcxa/src/bin/button_async.rs b/examples/mcxa/src/bin/button_async.rs new file mode 100644 index 000000000..6cc7b62cd --- /dev/null +++ b/examples/mcxa/src/bin/button_async.rs @@ -0,0 +1,29 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::gpio::{Input, Pull}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("GPIO interrupt example"); + + // This button is labeled "WAKEUP" on the FRDM-MCXA276 + // The board already has a 10K pullup + let mut pin = Input::new(p.P1_7, Pull::Disabled); + + let mut press_count = 0u32; + + loop { + pin.wait_for_falling_edge().await; + + press_count += 1; + + defmt::info!("Button pressed! Count: {}", press_count); + Timer::after_millis(50).await; + } +} diff --git a/examples/mcxa/src/bin/clkout.rs b/examples/mcxa/src/bin/clkout.rs new file mode 100644 index 000000000..bfd963540 --- /dev/null +++ b/examples/mcxa/src/bin/clkout.rs @@ -0,0 +1,69 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4}; +use embassy_mcxa::clocks::PoweredClock; +use embassy_mcxa::gpio::{DriveStrength, SlewRate}; +use embassy_mcxa::{Level, Output}; +use embassy_time::Timer; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Demonstrate CLKOUT, using Pin P4.2 +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + let mut pin = p.P4_2; + let mut clkout = p.CLKOUT; + + loop { + defmt::info!("Set Low..."); + let mut output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); + Timer::after_millis(500).await; + + defmt::info!("Set High..."); + output.set_high(); + Timer::after_millis(400).await; + + defmt::info!("Set Low..."); + output.set_low(); + Timer::after_millis(500).await; + + defmt::info!("16k..."); + // Run Clock Out with the 16K clock + let _clock_out = ClockOut::new( + clkout.reborrow(), + pin.reborrow(), + Config { + sel: ClockOutSel::Clk16K, + div: Div4::no_div(), + level: PoweredClock::NormalEnabledDeepSleepDisabled, + }, + ) + .unwrap(); + + Timer::after_millis(3000).await; + + defmt::info!("Set Low..."); + drop(_clock_out); + + let _output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow); + Timer::after_millis(500).await; + + // Run Clock Out with the 12M clock, divided by 3 + defmt::info!("4M..."); + let _clock_out = ClockOut::new( + clkout.reborrow(), + pin.reborrow(), + Config { + sel: ClockOutSel::Fro12M, + div: const { Div4::from_divisor(3).unwrap() }, + level: PoweredClock::NormalEnabledDeepSleepDisabled, + }, + ) + .unwrap(); + + // Let it run for 3 seconds... + Timer::after_millis(3000).await; + } +} diff --git a/examples/mcxa/src/bin/hello.rs b/examples/mcxa/src/bin/hello.rs new file mode 100644 index 000000000..e371d9413 --- /dev/null +++ b/examples/mcxa/src/bin/hello.rs @@ -0,0 +1,119 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clocks::config::Div8; +use hal::lpuart::{Blocking, Config, Lpuart}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Simple helper to write a byte as hex to UART +fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) { + const HEX_DIGITS: &[u8] = b"0123456789ABCDEF"; + let _ = uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]); + let _ = uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]); +} + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); + + defmt::info!("boot"); + + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + ..Default::default() + }; + + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX + let mut uart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.P2_2, // TX pin + p.P2_3, // RX pin + config, + ) + .unwrap(); + + // Print welcome message before any async delays to guarantee early console output + uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n"); + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + uart.write_str_blocking("Type a command: "); + + let mut buffer = [0u8; 64]; + let mut buf_idx = 0; + + loop { + // Read a byte from UART + let byte = uart.read_byte_blocking(); + + // Echo the character back + if byte == b'\r' || byte == b'\n' { + // Enter pressed - process command + uart.write_str_blocking("\r\n"); + + if buf_idx > 0 { + let command = &buffer[0..buf_idx]; + + if command == b"help" { + uart.write_str_blocking("Available commands:\r\n"); + uart.write_str_blocking(" help - Show this help\r\n"); + uart.write_str_blocking(" echo - Echo back the text\r\n"); + uart.write_str_blocking(" hex - Display byte in hex (0-255)\r\n"); + } else if command.starts_with(b"echo ") && command.len() > 5 { + uart.write_str_blocking("Echo: "); + uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } else if command.starts_with(b"hex ") && command.len() > 4 { + // Parse the byte value + let num_str = &command[4..]; + if let Ok(num) = parse_u8(num_str) { + uart.write_str_blocking("Hex: 0x"); + write_hex_byte(&mut uart, num); + uart.write_str_blocking("\r\n"); + } else { + uart.write_str_blocking("Invalid number for hex command\r\n"); + } + } else if !command.is_empty() { + uart.write_str_blocking("Unknown command: "); + uart.write_str_blocking(core::str::from_utf8(command).unwrap_or("")); + uart.write_str_blocking("\r\n"); + } + } + + // Reset buffer and prompt + buf_idx = 0; + uart.write_str_blocking("Type a command: "); + } else if byte == 8 || byte == 127 { + // Backspace + if buf_idx > 0 { + buf_idx -= 1; + uart.write_str_blocking("\x08 \x08"); // Erase character + } + } else if buf_idx < buffer.len() - 1 { + // Regular character + buffer[buf_idx] = byte; + buf_idx += 1; + let _ = uart.write_byte(byte); + } + } +} + +/// Simple parser for u8 from ASCII bytes +fn parse_u8(bytes: &[u8]) -> Result { + let mut result = 0u8; + for &b in bytes { + if b.is_ascii_digit() { + result = result.checked_mul(10).ok_or(())?; + result = result.checked_add(b - b'0').ok_or(())?; + } else { + return Err(()); + } + } + Ok(result) +} diff --git a/examples/mcxa/src/bin/i2c-async.rs b/examples/mcxa/src/bin/i2c-async.rs new file mode 100644 index 000000000..47b5f3cbe --- /dev/null +++ b/examples/mcxa/src/bin/i2c-async.rs @@ -0,0 +1,39 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::bind_interrupts; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use hal::i2c::InterruptHandler; +use hal::peripherals::LPI2C3; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!( + struct Irqs { + LPI2C3 => InterruptHandler; + } +); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + let mut i2c = I2c::new_async(p.LPI2C3, p.P3_27, p.P3_28, Irqs, config).unwrap(); + let mut buf = [0u8; 2]; + + loop { + i2c.async_write_read(0x48, &[0x00], &mut buf).await.unwrap(); + defmt::info!("Buffer: {:02x}", buf); + Timer::after_secs(1).await; + } +} diff --git a/examples/mcxa/src/bin/i2c-blocking.rs b/examples/mcxa/src/bin/i2c-blocking.rs new file mode 100644 index 000000000..0f6c8cbae --- /dev/null +++ b/examples/mcxa/src/bin/i2c-blocking.rs @@ -0,0 +1,31 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_time::Timer; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use tmp108::Tmp108; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + let i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap(); + let mut tmp = Tmp108::new_with_a0_gnd(i2c); + + loop { + let temperature = tmp.temperature().unwrap(); + defmt::info!("Temperature: {}C", temperature); + Timer::after_secs(1).await; + } +} diff --git a/examples/mcxa/src/bin/i2c-scan-blocking.rs b/examples/mcxa/src/bin/i2c-scan-blocking.rs new file mode 100644 index 000000000..4e203597b --- /dev/null +++ b/examples/mcxa/src/bin/i2c-scan-blocking.rs @@ -0,0 +1,41 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::gpio::Pull; +use embassy_mcxa::Input; +use embassy_time::Timer; +use hal::clocks::config::Div8; +use hal::config::Config; +use hal::i2c::controller::{self, I2c, Speed}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut config = Config::default(); + config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1); + + let p = hal::init(config); + + defmt::info!("I2C example"); + + let mut config = controller::Config::default(); + config.speed = Speed::Standard; + + // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and + // defaults to SWO on the debug peripheral. Explicitly make it a high-z + // input. + let _pin = Input::new(p.P0_2, Pull::Disabled); + let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap(); + + for addr in 0x01..=0x7f { + let result = i2c.blocking_write(addr, &[]); + if result.is_ok() { + defmt::info!("Device found at addr {:02x}", addr); + } + } + + loop { + Timer::after_secs(10).await; + } +} diff --git a/examples/mcxa/src/bin/lpuart_buffered.rs b/examples/mcxa/src/bin/lpuart_buffered.rs new file mode 100644 index 000000000..420589d00 --- /dev/null +++ b/examples/mcxa/src/bin/lpuart_buffered.rs @@ -0,0 +1,62 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clocks::config::Div8; +use embassy_mcxa::lpuart::buffered::BufferedLpuart; +use embassy_mcxa::lpuart::Config; +use embassy_mcxa::{bind_interrupts, lpuart}; +use embedded_io_async::Write; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver +bind_interrupts!(struct Irqs { + LPUART2 => lpuart::buffered::BufferedInterruptHandler::; +}); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); + + // Configure NVIC for LPUART2 + hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3); + + // UART configuration (enable both TX and RX) + let config = Config { + baudrate_bps: 115_200, + rx_fifo_watermark: 0, + tx_fifo_watermark: 0, + ..Default::default() + }; + + let mut tx_buf = [0u8; 256]; + let mut rx_buf = [0u8; 256]; + + // Create a buffered LPUART2 instance with both TX and RX + let mut uart = BufferedLpuart::new( + p.LPUART2, + p.P2_2, // TX pin + p.P2_3, // RX pin + Irqs, + &mut tx_buf, + &mut rx_buf, + config, + ) + .unwrap(); + + // Split into TX and RX parts + let (tx, rx) = uart.split_ref(); + + tx.write(b"Hello buffered LPUART.\r\n").await.unwrap(); + tx.write(b"Type characters to echo them back.\r\n").await.unwrap(); + + // Echo loop + let mut buf = [0u8; 4]; + loop { + let used = rx.read(&mut buf).await.unwrap(); + tx.write_all(&buf[..used]).await.unwrap(); + } +} diff --git a/examples/mcxa/src/bin/lpuart_polling.rs b/examples/mcxa/src/bin/lpuart_polling.rs new file mode 100644 index 000000000..b80668834 --- /dev/null +++ b/examples/mcxa/src/bin/lpuart_polling.rs @@ -0,0 +1,47 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::clocks::config::Div8; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +use crate::hal::lpuart::{Config, Lpuart}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let mut cfg = hal::config::Config::default(); + cfg.clock_cfg.sirc.fro_12m_enabled = true; + cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div()); + let p = hal::init(cfg); + + defmt::info!("boot"); + + // Create UART configuration + let config = Config { + baudrate_bps: 115_200, + ..Default::default() + }; + + // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX + let lpuart = Lpuart::new_blocking( + p.LPUART2, // Peripheral + p.P2_2, // TX pin + p.P2_3, // RX pin + config, + ) + .unwrap(); + + // Split into separate TX and RX parts + let (mut tx, mut rx) = lpuart.split(); + + // Write hello messages + tx.blocking_write(b"Hello world.\r\n").unwrap(); + tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap(); + + // Echo loop + loop { + let mut buf = [0u8; 1]; + rx.blocking_read(&mut buf).unwrap(); + tx.blocking_write(&buf).unwrap(); + } +} diff --git a/examples/mcxa/src/bin/rtc_alarm.rs b/examples/mcxa/src/bin/rtc_alarm.rs new file mode 100644 index 000000000..fe355888b --- /dev/null +++ b/examples/mcxa/src/bin/rtc_alarm.rs @@ -0,0 +1,47 @@ +#![no_std] +#![no_main] + +use embassy_executor::Spawner; +use embassy_mcxa::bind_interrupts; +use hal::rtc::{InterruptHandler, Rtc, RtcDateTime}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +bind_interrupts!(struct Irqs { + RTC => InterruptHandler; +}); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + let p = hal::init(hal::config::Config::default()); + + defmt::info!("=== RTC Alarm Example ==="); + + let rtc_config = hal::rtc::get_default_config(); + + let mut rtc = Rtc::new(p.RTC0, Irqs, rtc_config); + + let now = RtcDateTime { + year: 2025, + month: 10, + day: 15, + hour: 14, + minute: 30, + second: 0, + }; + + rtc.stop(); + + defmt::info!("Time set to: 2025-10-15 14:30:00"); + rtc.set_datetime(now); + + let mut alarm = now; + alarm.second += 10; + + defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)"); + defmt::info!("RTC started, waiting for alarm..."); + + rtc.wait_for_alarm(alarm).await; + defmt::info!("*** ALARM TRIGGERED! ***"); + + defmt::info!("Example complete - Test PASSED!"); +} diff --git a/examples/mcxa/src/lib.rs b/examples/mcxa/src/lib.rs new file mode 100644 index 000000000..2573a6adc --- /dev/null +++ b/examples/mcxa/src/lib.rs @@ -0,0 +1,16 @@ +#![no_std] +#![allow(clippy::missing_safety_doc)] + +//! Shared board-specific helpers for the FRDM-MCXA276 examples. +//! These live with the examples so the HAL stays generic. + +use hal::{clocks, pins}; +use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; + +/// Initialize clocks and pin muxing for ADC. +pub unsafe fn init_adc_pins() { + // NOTE: Lpuart has been updated to properly enable + reset its own clocks. + // GPIO has not. + _ = clocks::enable_and_reset::(&clocks::periph_helpers::NoConfig); + pins::configure_adc_pins(); +} -- cgit From 7ba524026cce5531300ec1d803d10390a6159240 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:08:19 +0100 Subject: Bump mcxa-pac to lower MSRV to 1.90 --- embassy-mcxa/Cargo.lock | 2 +- examples/mcxa/Cargo.lock | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-mcxa/Cargo.lock b/embassy-mcxa/Cargo.lock index 747a69c08..22b59c395 100644 --- a/embassy-mcxa/Cargo.lock +++ b/embassy-mcxa/Cargo.lock @@ -430,7 +430,7 @@ dependencies = [ [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#e18dfb52500ca77b8d8326662b966a80251182ca" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#e7dfed8740b449b6ac646bab8ac6776a3c099267" dependencies = [ "cortex-m", "cortex-m-rt", diff --git a/examples/mcxa/Cargo.lock b/examples/mcxa/Cargo.lock index c6e864df2..8ac1fc8de 100644 --- a/examples/mcxa/Cargo.lock +++ b/examples/mcxa/Cargo.lock @@ -765,7 +765,7 @@ dependencies = [ [[package]] name = "mcxa-pac" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#e18dfb52500ca77b8d8326662b966a80251182ca" +source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#e7dfed8740b449b6ac646bab8ac6776a3c099267" dependencies = [ "cortex-m", "cortex-m-rt", -- cgit From 8b862572083c8233cc55bd635885b1c2b03564ee Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:09:56 +0100 Subject: Add repository fields --- embassy-mcxa/Cargo.toml | 1 + examples/mcxa/Cargo.toml | 1 + 2 files changed, 2 insertions(+) diff --git a/embassy-mcxa/Cargo.toml b/embassy-mcxa/Cargo.toml index 22660bee9..b4979daba 100644 --- a/embassy-mcxa/Cargo.toml +++ b/embassy-mcxa/Cargo.toml @@ -4,6 +4,7 @@ version = "0.1.0" edition = "2021" license = "MIT OR Apache-2.0" description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA series of MCUs" +repository = "https://github.com/embassy-rs/embassy" keywords = ["embedded", "hal", "nxp", "mcxa", "embassy"] categories = ["embedded", "hardware-support", "no-std"] diff --git a/examples/mcxa/Cargo.toml b/examples/mcxa/Cargo.toml index 4da94811f..cfc68f067 100644 --- a/examples/mcxa/Cargo.toml +++ b/examples/mcxa/Cargo.toml @@ -3,6 +3,7 @@ name = "embassy-mcxa-examples" version = "0.1.0" edition = "2021" license = "MIT OR Apache-2.0" +repository = "https://github.com/embassy-rs/embassy" [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -- cgit From 5d12ea7daef3422de26d24f902f2eedb3de2de9b Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:11:29 +0100 Subject: publish false on mcxa examples --- examples/mcxa/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/mcxa/Cargo.toml b/examples/mcxa/Cargo.toml index cfc68f067..f02fe73e0 100644 --- a/examples/mcxa/Cargo.toml +++ b/examples/mcxa/Cargo.toml @@ -3,7 +3,7 @@ name = "embassy-mcxa-examples" version = "0.1.0" edition = "2021" license = "MIT OR Apache-2.0" -repository = "https://github.com/embassy-rs/embassy" +publish = false [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -- cgit From 6530bcd8bcff9169f39732ba93a612f9262b809e Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:13:27 +0100 Subject: Add documentation --- embassy-mcxa/Cargo.toml | 1 + 1 file changed, 1 insertion(+) diff --git a/embassy-mcxa/Cargo.toml b/embassy-mcxa/Cargo.toml index b4979daba..5ff6d313c 100644 --- a/embassy-mcxa/Cargo.toml +++ b/embassy-mcxa/Cargo.toml @@ -7,6 +7,7 @@ description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA series of M repository = "https://github.com/embassy-rs/embassy" keywords = ["embedded", "hal", "nxp", "mcxa", "embassy"] categories = ["embedded", "hardware-support", "no-std"] +documentation = "https://docs.embassy.dev/embassy-mcxa" [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } -- cgit From e7e4d0e03f6ccee7a8577058bfccefaf92b2689e Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:19:23 +0100 Subject: rustfmt --- embassy-mcxa/src/adc.rs | 2 +- embassy-mcxa/src/clkout.rs | 2 +- embassy-mcxa/src/clocks/periph_helpers.rs | 6 +----- embassy-mcxa/src/i2c/controller.rs | 6 +++--- embassy-mcxa/src/interrupt.rs | 2 +- embassy-mcxa/src/lpuart/buffered.rs | 2 +- embassy-mcxa/src/lpuart/mod.rs | 6 +++--- embassy-mcxa/src/ostimer.rs | 8 ++++---- examples/mcxa/src/bin/adc_interrupt.rs | 4 ++-- examples/mcxa/src/bin/adc_polling.rs | 2 +- examples/mcxa/src/bin/i2c-async.rs | 2 +- examples/mcxa/src/bin/i2c-scan-blocking.rs | 2 +- examples/mcxa/src/bin/lpuart_buffered.rs | 2 +- 13 files changed, 21 insertions(+), 25 deletions(-) diff --git a/embassy-mcxa/src/adc.rs b/embassy-mcxa/src/adc.rs index b5ec5983f..7475299ba 100644 --- a/embassy-mcxa/src/adc.rs +++ b/embassy-mcxa/src/adc.rs @@ -4,7 +4,7 @@ use core::sync::atomic::{AtomicBool, Ordering}; use embassy_hal_internal::{Peri, PeripheralType}; use crate::clocks::periph_helpers::{AdcClockSel, AdcConfig, Div4}; -use crate::clocks::{enable_and_reset, Gate, PoweredClock}; +use crate::clocks::{Gate, PoweredClock, enable_and_reset}; use crate::pac; use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres}; use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts}; diff --git a/embassy-mcxa/src/clkout.rs b/embassy-mcxa/src/clkout.rs index 88c731df1..5b21f24b0 100644 --- a/embassy-mcxa/src/clkout.rs +++ b/embassy-mcxa/src/clkout.rs @@ -9,7 +9,7 @@ use core::marker::PhantomData; use embassy_hal_internal::Peri; pub use crate::clocks::periph_helpers::Div4; -use crate::clocks::{with_clocks, ClockError, PoweredClock}; +use crate::clocks::{ClockError, PoweredClock, with_clocks}; use crate::pac::mrcc0::mrcc_clkout_clksel::Mux; use crate::peripherals::CLKOUT; diff --git a/embassy-mcxa/src/clocks/periph_helpers.rs b/embassy-mcxa/src/clocks/periph_helpers.rs index 1ea7a99ed..fed5e558e 100644 --- a/embassy-mcxa/src/clocks/periph_helpers.rs +++ b/embassy-mcxa/src/clocks/periph_helpers.rs @@ -108,11 +108,7 @@ impl Div4 { /// by 1, and `Div4::from_raw(15)` will divide the source by /// 16. pub const fn from_raw(n: u8) -> Option { - if n > 0b1111 { - None - } else { - Some(Self(n)) - } + if n > 0b1111 { None } else { Some(Self(n)) } } /// Store a specific divisor value that will divide the source diff --git a/embassy-mcxa/src/i2c/controller.rs b/embassy-mcxa/src/i2c/controller.rs index 182a53aea..c27d508b0 100644 --- a/embassy-mcxa/src/i2c/controller.rs +++ b/embassy-mcxa/src/i2c/controller.rs @@ -3,15 +3,15 @@ use core::future::Future; use core::marker::PhantomData; -use embassy_hal_internal::drop::OnDrop; use embassy_hal_internal::Peri; +use embassy_hal_internal::drop::OnDrop; use mcxa_pac::lpi2c0::mtdr::Cmd; use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin}; +use crate::AnyPin; use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig}; -use crate::clocks::{enable_and_reset, PoweredClock}; +use crate::clocks::{PoweredClock, enable_and_reset}; use crate::interrupt::typelevel::Interrupt; -use crate::AnyPin; /// Bus speed (nominal SCL, no clock stretching) #[derive(Clone, Copy, Default, PartialEq)] diff --git a/embassy-mcxa/src/interrupt.rs b/embassy-mcxa/src/interrupt.rs index 1d10e3b2d..c1f7e55a0 100644 --- a/embassy-mcxa/src/interrupt.rs +++ b/embassy-mcxa/src/interrupt.rs @@ -32,7 +32,7 @@ mod generated { use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; -pub use generated::interrupt::{typelevel, Priority}; +pub use generated::interrupt::{Priority, typelevel}; use crate::pac::Interrupt; diff --git a/embassy-mcxa/src/lpuart/buffered.rs b/embassy-mcxa/src/lpuart/buffered.rs index 8eb443ca7..34fdbb76c 100644 --- a/embassy-mcxa/src/lpuart/buffered.rs +++ b/embassy-mcxa/src/lpuart/buffered.rs @@ -3,8 +3,8 @@ use core::marker::PhantomData; use core::sync::atomic::{AtomicBool, Ordering}; use core::task::Poll; -use embassy_hal_internal::atomic_ring_buffer::RingBuffer; use embassy_hal_internal::Peri; +use embassy_hal_internal::atomic_ring_buffer::RingBuffer; use embassy_sync::waitqueue::AtomicWaker; use super::*; diff --git a/embassy-mcxa/src/lpuart/mod.rs b/embassy-mcxa/src/lpuart/mod.rs index 2d8308ec8..b8a2d5172 100644 --- a/embassy-mcxa/src/lpuart/mod.rs +++ b/embassy-mcxa/src/lpuart/mod.rs @@ -4,13 +4,13 @@ use embassy_hal_internal::{Peri, PeripheralType}; use paste::paste; use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig}; -use crate::clocks::{enable_and_reset, ClockError, Gate, PoweredClock}; +use crate::clocks::{ClockError, Gate, PoweredClock, enable_and_reset}; use crate::gpio::SealedPin; use crate::pac::lpuart0::baud::Sbns as StopBits; -use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; +use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity}; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; use crate::pac::lpuart0::stat::Msbf as MsbFirst; -use crate::{interrupt, pac, AnyPin}; +use crate::{AnyPin, interrupt, pac}; pub mod buffered; diff --git a/embassy-mcxa/src/ostimer.rs b/embassy-mcxa/src/ostimer.rs index c51812e3d..9e66e82d8 100644 --- a/embassy-mcxa/src/ostimer.rs +++ b/embassy-mcxa/src/ostimer.rs @@ -32,7 +32,7 @@ use core::sync::atomic::{AtomicBool, Ordering}; use embassy_hal_internal::{Peri, PeripheralType}; use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; -use crate::clocks::{assert_reset, enable_and_reset, is_reset_released, release_reset, Gate, PoweredClock}; +use crate::clocks::{Gate, PoweredClock, assert_reset, enable_and_reset, is_reset_released, release_reset}; use crate::interrupt::InterruptExt; use crate::pac; @@ -521,11 +521,11 @@ pub mod time_driver { use embassy_time_driver as etd; use super::{ - bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, - EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, + ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, + LOW_32_BIT_MASK, Regs, bin_to_gray, now_ticks_read, }; use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel}; - use crate::clocks::{enable_and_reset, PoweredClock}; + use crate::clocks::{PoweredClock, enable_and_reset}; use crate::pac; #[allow(non_camel_case_types)] diff --git a/examples/mcxa/src/bin/adc_interrupt.rs b/examples/mcxa/src/bin/adc_interrupt.rs index 83d8046b3..c88b1fe8d 100644 --- a/examples/mcxa/src/bin/adc_interrupt.rs +++ b/examples/mcxa/src/bin/adc_interrupt.rs @@ -4,13 +4,13 @@ use embassy_executor::Spawner; use embassy_mcxa_examples::init_adc_pins; use hal::adc::{LpadcConfig, TriggerPriorityPolicy}; -use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::clocks::PoweredClock; +use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; use hal::pac::adc1::ctrl::CalAvgs; use hal::pac::adc1::tctrl::Tcmd; -use hal::{bind_interrupts, InterruptExt}; +use hal::{InterruptExt, bind_interrupts}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; bind_interrupts!(struct Irqs { diff --git a/examples/mcxa/src/bin/adc_polling.rs b/examples/mcxa/src/bin/adc_polling.rs index ddf3f586b..07c50f224 100644 --- a/examples/mcxa/src/bin/adc_polling.rs +++ b/examples/mcxa/src/bin/adc_polling.rs @@ -4,8 +4,8 @@ use embassy_executor::Spawner; use embassy_mcxa_examples::init_adc_pins; use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy}; -use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::clocks::PoweredClock; +use hal::clocks::periph_helpers::{AdcClockSel, Div4}; use hal::pac::adc1::cfg::{Pwrsel, Refsel}; use hal::pac::adc1::cmdl1::{Adch, Mode}; use hal::pac::adc1::ctrl::CalAvgs; diff --git a/examples/mcxa/src/bin/i2c-async.rs b/examples/mcxa/src/bin/i2c-async.rs index 47b5f3cbe..edcfd5f22 100644 --- a/examples/mcxa/src/bin/i2c-async.rs +++ b/examples/mcxa/src/bin/i2c-async.rs @@ -6,8 +6,8 @@ use embassy_time::Timer; use hal::bind_interrupts; use hal::clocks::config::Div8; use hal::config::Config; -use hal::i2c::controller::{self, I2c, Speed}; use hal::i2c::InterruptHandler; +use hal::i2c::controller::{self, I2c, Speed}; use hal::peripherals::LPI2C3; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; diff --git a/examples/mcxa/src/bin/i2c-scan-blocking.rs b/examples/mcxa/src/bin/i2c-scan-blocking.rs index 4e203597b..0197f9b1d 100644 --- a/examples/mcxa/src/bin/i2c-scan-blocking.rs +++ b/examples/mcxa/src/bin/i2c-scan-blocking.rs @@ -2,8 +2,8 @@ #![no_main] use embassy_executor::Spawner; -use embassy_mcxa::gpio::Pull; use embassy_mcxa::Input; +use embassy_mcxa::gpio::Pull; use embassy_time::Timer; use hal::clocks::config::Div8; use hal::config::Config; diff --git a/examples/mcxa/src/bin/lpuart_buffered.rs b/examples/mcxa/src/bin/lpuart_buffered.rs index 420589d00..47b56b7c7 100644 --- a/examples/mcxa/src/bin/lpuart_buffered.rs +++ b/examples/mcxa/src/bin/lpuart_buffered.rs @@ -3,8 +3,8 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::lpuart::buffered::BufferedLpuart; use embassy_mcxa::lpuart::Config; +use embassy_mcxa::lpuart::buffered::BufferedLpuart; use embassy_mcxa::{bind_interrupts, lpuart}; use embedded_io_async::Write; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; -- cgit From 85b92010deb835d27ce30ec0870cdedadf4465ec Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:24:06 +0100 Subject: Tweak how target setting is handled --- embassy-mcxa/.cargo/config.toml | 2 -- embassy-mcxa/Cargo.toml | 6 ++++++ examples/mcxa/Cargo.toml | 5 +++++ 3 files changed, 11 insertions(+), 2 deletions(-) delete mode 100644 embassy-mcxa/.cargo/config.toml diff --git a/embassy-mcxa/.cargo/config.toml b/embassy-mcxa/.cargo/config.toml deleted file mode 100644 index 55dd5ea5f..000000000 --- a/embassy-mcxa/.cargo/config.toml +++ /dev/null @@ -1,2 +0,0 @@ -[build] -target = "thumbv8m.main-none-eabihf" # Cortex-M33 diff --git a/embassy-mcxa/Cargo.toml b/embassy-mcxa/Cargo.toml index 5ff6d313c..a2662f424 100644 --- a/embassy-mcxa/Cargo.toml +++ b/embassy-mcxa/Cargo.toml @@ -9,6 +9,12 @@ keywords = ["embedded", "hal", "nxp", "mcxa", "embassy"] categories = ["embedded", "hardware-support", "no-std"] documentation = "https://docs.embassy.dev/embassy-mcxa" +[package.metadata.embassy] +build = [ + {target = "thumbv8m.main-none-eabihf", features = ["defmt", "time", "unstable-pac"]}, + {target = "thumbv8m.main-none-eabihf", features = ["defmt", "time", "unstable-pac"]}, +] + [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"] } # If you would like "device" to be an optional feature, please open an issue. diff --git a/examples/mcxa/Cargo.toml b/examples/mcxa/Cargo.toml index f02fe73e0..4d0459f41 100644 --- a/examples/mcxa/Cargo.toml +++ b/examples/mcxa/Cargo.toml @@ -25,3 +25,8 @@ tmp108 = "0.4.0" [profile.release] lto = true # better optimizations debug = 2 # enough information for defmt/rtt locations + +[package.metadata.embassy] +build = [ + { target = "thumbv8m.main-none-eabihf", artifact-dir = "out/examples/mcxa" } +] -- cgit From 308952d41e57c2041dc6857295e2fd3d9cd6cd17 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:38:25 +0100 Subject: Remove standalone CI steps --- embassy-mcxa/.github/DOCS.md | 23 --- embassy-mcxa/.github/codecov.yml | 21 -- embassy-mcxa/.github/dependabot.yml | 19 -- .../.github/workflows/cargo-vet-pr-comment.yml | 137 ------------- embassy-mcxa/.github/workflows/cargo-vet.yml | 53 ----- embassy-mcxa/.github/workflows/check.yml | 215 --------------------- embassy-mcxa/.github/workflows/nostd.yml | 38 ---- embassy-mcxa/.github/workflows/rolling.yml | 58 ------ 8 files changed, 564 deletions(-) delete mode 100644 embassy-mcxa/.github/DOCS.md delete mode 100644 embassy-mcxa/.github/codecov.yml delete mode 100644 embassy-mcxa/.github/dependabot.yml delete mode 100644 embassy-mcxa/.github/workflows/cargo-vet-pr-comment.yml delete mode 100644 embassy-mcxa/.github/workflows/cargo-vet.yml delete mode 100644 embassy-mcxa/.github/workflows/check.yml delete mode 100644 embassy-mcxa/.github/workflows/nostd.yml delete mode 100644 embassy-mcxa/.github/workflows/rolling.yml diff --git a/embassy-mcxa/.github/DOCS.md b/embassy-mcxa/.github/DOCS.md deleted file mode 100644 index e932784c7..000000000 --- a/embassy-mcxa/.github/DOCS.md +++ /dev/null @@ -1,23 +0,0 @@ -# Github config and workflows - -In this folder there is configuration for codecoverage, dependabot, and ci -workflows that check the library more deeply than the default configurations. - -This folder can be or was merged using a --allow-unrelated-histories merge -strategy from which provides a -reasonably sensible base for writing your own ci on. By using this strategy -the history of the CI repo is included in your repo, and future updates to -the CI can be merged later. - -To perform this merge run: - -```shell -git remote add ci https://github.com/jonhoo/rust-ci-conf.git -git fetch ci -git merge --allow-unrelated-histories ci/main -``` - -An overview of the files in this project is available at: -, which contains some -rationale for decisions and runs through an example of solving minimal version -and OpenSSL issues. diff --git a/embassy-mcxa/.github/codecov.yml b/embassy-mcxa/.github/codecov.yml deleted file mode 100644 index cd5ce8fc1..000000000 --- a/embassy-mcxa/.github/codecov.yml +++ /dev/null @@ -1,21 +0,0 @@ -# ref: https://docs.codecov.com/docs/codecovyml-reference -coverage: - # Hold ourselves to a high bar - range: 85..100 - round: down - precision: 1 - status: - # ref: https://docs.codecov.com/docs/commit-status - project: - default: - # Avoid false negatives - threshold: 1% - -# Test files aren't important for coverage -ignore: - - "tests" - -# Make comments less noisy -comment: - layout: "files" - require_changes: true diff --git a/embassy-mcxa/.github/dependabot.yml b/embassy-mcxa/.github/dependabot.yml deleted file mode 100644 index d0f091e7b..000000000 --- a/embassy-mcxa/.github/dependabot.yml +++ /dev/null @@ -1,19 +0,0 @@ -version: 2 -updates: - - package-ecosystem: github-actions - directory: / - schedule: - interval: daily - - package-ecosystem: cargo - directory: / - schedule: - interval: daily - ignore: - - dependency-name: "*" - # patch and minor updates don't matter for libraries as consumers of this library build - # with their own lockfile, rather than the version specified in this library's lockfile - # remove this ignore rule if your package has binaries to ensure that the binaries are - # built with the exact set of dependencies and those are up to date. - update-types: - - "version-update:semver-patch" - - "version-update:semver-minor" diff --git a/embassy-mcxa/.github/workflows/cargo-vet-pr-comment.yml b/embassy-mcxa/.github/workflows/cargo-vet-pr-comment.yml deleted file mode 100644 index 66f27ceab..000000000 --- a/embassy-mcxa/.github/workflows/cargo-vet-pr-comment.yml +++ /dev/null @@ -1,137 +0,0 @@ -# This workflow triggers after cargo-vet workflow has run. -# It adds a comment to the PR with the results of the cargo vet run. -# It first adds a comment if the cargo vet run fails, -# and updates the comment if the cargo vet run succeeds after having failed at least once. - -name: Cargo vet PR comment - -on: - workflow_run: - workflows: [cargo-vet] - types: - - completed - -permissions: - contents: read - pull-requests: write - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -jobs: - - find-pr-comment: - # This job runs when the cargo-vet job fails or succeeds - # It will download the artifact from the failed job and post a comment on the PR - runs-on: ubuntu-latest - outputs: - comment-id: ${{ steps.get-comment-id.outputs.comment-id }} - pr-number: ${{ steps.get-pr-number.outputs.pr_number }} - if: github.event.workflow_run.event == 'pull_request' - steps: - - name: 'Download artifact' - uses: actions/download-artifact@v6 - with: - github-token: ${{ secrets.GITHUB_TOKEN }} - name: pr - path: pr/ - run-id: ${{ github.event.workflow_run.id }} - - - name: 'Get PR number' - id: get-pr-number - run: echo "pr_number=$(cat ./pr/NR)" >> $GITHUB_OUTPUT - - - name: 'Find existing comment' - id: find-comment - uses: peter-evans/find-comment@v4 - with: - issue-number: ${{ steps.get-pr-number.outputs.pr_number }} - comment-author: 'github-actions[bot]' - body-includes: 'comment-tag: [cargo-vet]' - - - name: 'Get comment ID' - id: get-comment-id - if: ${{ steps.find-comment.outputs.comment-id != '' }} - run: echo "comment-id=${{ steps.find-comment.outputs.comment-id }}" >> $GITHUB_OUTPUT - - post-comment-failure: - # This job runs when the cargo-vet job fails - # It will download the artifact from the failed job and post a comment on the PR - runs-on: ubuntu-latest - needs: find-pr-comment - if: github.event.workflow_run.conclusion == 'failure' - steps: - - name: 'Comment on PR - Failure' - uses: peter-evans/create-or-update-comment@v5 - with: - comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} - issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} - body: | - # Cargo Vet Audit Failed - - `cargo vet` has failed in this PR. Please run `cargo vet --locked` locally to check for new or updated unvetted dependencies. - Details about the vetting process can be found in [supply-chain/README.md](../blob/main/supply-chain/README.md) - - ## If the unvetted dependencies are not needed - Please modify Cargo.toml file to avoid including the dependencies. - - ## If the unvetted dependencies are needed - Post a new comment with the questionnaire below to the PR to help the auditors vet the dependencies. - After the auditors have vetted the dependencies, the PR will need to be rebased to pick up the new audits and pass this check. - - ### Copy and paste the questionnaire as a new comment and provide your answers: - - **1. What crates (with version) need to be audited?** - - **2. How many of the crates are version updates vs new dependencies?** - - **3. To confirm none of the already included crates serve your needs, please provide a brief description of the purpose of the new crates.** - - **4. Any extra notes to the auditors to help with their audits.** - - - edit-mode: replace - - - name: 'Label PR' - uses: actions/github-script@v8 - with: - script: | - github.rest.issues.addLabels({ - issue_number: ${{ needs.find-pr-comment.outputs.pr-number }}, - owner: context.repo.owner, - repo: context.repo.repo, - labels: ['cargo vet'] - }) - - post-comment-success: - # This job runs when the cargo-vet job succeeds - # It will update the comment on the PR with a success message - runs-on: ubuntu-latest - needs: find-pr-comment - if: github.event.workflow_run.conclusion == 'success' - steps: - - name: 'Comment on PR - Success' - # Only update the comment if it exists - # This is to avoid creating a new comment if the cargo-vet job has never failed before - if: ${{ needs.find-pr-comment.outputs.comment-id }} - uses: peter-evans/create-or-update-comment@v5 - with: - comment-id: ${{ needs.find-pr-comment.outputs.comment-id }} - issue-number: ${{ needs.find-pr-comment.outputs.pr-number }} - body: | - # Cargo Vet Audit Passed - `cargo vet` has passed in this PR. No new unvetted dependencies were found. - - - edit-mode: replace diff --git a/embassy-mcxa/.github/workflows/cargo-vet.yml b/embassy-mcxa/.github/workflows/cargo-vet.yml deleted file mode 100644 index d585d1df5..000000000 --- a/embassy-mcxa/.github/workflows/cargo-vet.yml +++ /dev/null @@ -1,53 +0,0 @@ -# This workflow runs whenever a PR is opened or updated. It runs cargo vet to check for unvetted dependencies in the Cargo.lock file. -permissions: - contents: read -on: - pull_request: - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -name: cargo-vet -jobs: - vet: - # cargo-vet checks for unvetted dependencies in the Cargo.lock file - # This is to ensure that new dependencies are vetted before they are added to the project - name: vet-dependencies - runs-on: ubuntu-latest - env: - CARGO_VET_VERSION: 0.10.1 - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - uses: actions/cache@v4 - with: - path: ${{ runner.tool_cache }}/cargo-vet - key: cargo-vet-bin-${{ env.CARGO_VET_VERSION }} - - - name: Add the tool cache directory to the search path - run: echo "${{ runner.tool_cache }}/cargo-vet/bin" >> $GITHUB_PATH - - - name: Ensure that the tool cache is populated with the cargo-vet binary - run: cargo install --root ${{ runner.tool_cache }}/cargo-vet --version ${{ env.CARGO_VET_VERSION }} cargo-vet - - - name: Invoke cargo-vet - run: cargo vet --locked - - - name: Save PR number - # PR number is saved as an artifact so it can be used to determine the PR to comment on by the vet-pr-comment workflow - # vet-pr-comment workflow is triggered by the workflow_run event so it runs in the context of the base branch and not the PR branch - if: ${{ failure() }} || ${{ success() }} - run: | - mkdir -p ./pr - echo ${{ github.event.number }} > ./pr/NR - - uses: actions/upload-artifact@v5 - # Need to upload the artifact in both success and failure cases so comment can be updated in either case - if: ${{ failure() }} || ${{ success() }} - with: - name: pr - path: pr/ - overwrite: true \ No newline at end of file diff --git a/embassy-mcxa/.github/workflows/check.yml b/embassy-mcxa/.github/workflows/check.yml deleted file mode 100644 index ad9f44428..000000000 --- a/embassy-mcxa/.github/workflows/check.yml +++ /dev/null @@ -1,215 +0,0 @@ -# This workflow runs whenever a PR is opened or updated, or a commit is pushed to main. It runs -# several checks: -# - fmt: checks that the code is formatted according to rustfmt -# - clippy: checks that the code does not contain any clippy warnings -# - doc: checks that the code can be documented without errors -# - hack: check combinations of feature flags -# - msrv: check that the msrv specified in the crate is correct -permissions: - contents: read - -# This configuration allows maintainers of this repo to create a branch and pull request based on -# the new branch. Restricting the push trigger to the main branch ensures that the PR only gets -# built once. -on: - - push: - branches: [main, main-nextgen] - pull_request: - -# If new code is pushed to a PR branch, then cancel in progress workflows for that PR. Ensures that -# we don't waste CI time, and returns results quicker https://github.com/jonhoo/rust-ci-conf/pull/5 -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -name: check - -jobs: - - fmt: - runs-on: ubuntu-latest - name: nightly / fmt - - strategy: - fail-fast: false - matrix: - workdir: [ ".", "examples",] - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install nightly - uses: dtolnay/rust-toolchain@nightly - with: - components: rustfmt - targets: thumbv8m.main-none-eabihf - - - name: cargo fmt --check - run: cargo fmt --check - working-directory: ${{ matrix.workdir }} - - clippy-examples: - runs-on: ubuntu-latest - name: ${{ matrix.toolchain }} / clippy - - permissions: - contents: read - checks: write - - strategy: - fail-fast: false - matrix: - # Get early warning of new lints which are regularly introduced in beta channels. - toolchain: [stable] - workdir: ["examples"] - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install ${{ matrix.toolchain }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.toolchain }} - components: clippy - targets: thumbv8m.main-none-eabihf - - - name: cargo clippy - working-directory: ${{ matrix.workdir }} - run: | - cargo clippy --locked -- -Dwarnings -D clippy::suspicious -D clippy::correctness -D clippy::perf -D clippy::style - - # Enable once we have a released crate - # semver: - # runs-on: ubuntu-latest - # name: semver - # steps: - # - uses: actions/checkout@v6 - # with: - # submodules: true - # - name: Install stable - # uses: dtolnay/rust-toolchain@stable - # with: - # components: rustfmt - # - name: cargo-semver-checks - # uses: obi1kenobi/cargo-semver-checks-action@v2 - - doc: - # run docs generation on nightly rather than stable. This enables features like - # https://doc.rust-lang.org/beta/unstable-book/language-features/doc-cfg.html which allows an - # API be documented as only available in some specific platforms. - runs-on: ubuntu-latest - name: nightly / doc - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install nightly - uses: dtolnay/rust-toolchain@nightly - with: - targets: thumbv8m.main-none-eabihf - - - name: cargo doc - run: | - cargo doc --no-deps --all-features --locked - env: - RUSTDOCFLAGS: --cfg docsrs - - hack: - # cargo-hack checks combinations of feature flags to ensure that features are all additive - # which is required for feature unification - runs-on: ubuntu-latest - name: ubuntu / stable / features - - strategy: - fail-fast: false - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - toolchain: stable - components: clippy - targets: thumbv8m.main-none-eabihf - - - name: cargo install cargo-hack - uses: taiki-e/install-action@cargo-hack - - - name: cargo hack - run: cargo hack --feature-powerset check - - deny: - # cargo-deny checks licenses, advisories, sources, and bans for - # our dependencies. - runs-on: ubuntu-latest - name: ubuntu / stable / deny - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - targets: thumbv8m.main-none-eabihf - - - name: cargo install cargo-deny - uses: EmbarkStudios/cargo-deny-action@v2 - with: - log-level: warn - manifest-path: ./Cargo.toml - command: check - arguments: --all-features --locked - - msrv: - # check that we can build using the minimal rust version that is specified by this crate - runs-on: ubuntu-latest - # we use a matrix here just because env can't be used in job names - # https://docs.github.com/en/actions/learn-github-actions/contexts#context-availability - strategy: - fail-fast: false - matrix: - msrv: ["1.91"] # We're relying on namespaced-features, which - # was released in 1.60 - # - # We also depend on `fixed' which requires rust - # 1.71 - # - # Additionally, we depend on embedded-hal-async - # which requires 1.75 - # - # embassy-time requires 1.79 due to - # collapse_debuginfo - # - # embassy upstream switched to rust 1.85 - # - # unsigned_is_multiple_of requires 1.90, else we get clippy warnings - # - # mcxa-pac@0.1.0 requires rustc 1.91 - - name: ubuntu / ${{ matrix.msrv }} - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install ${{ matrix.msrv }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.msrv }} - targets: thumbv8m.main-none-eabihf - - - name: cargo +${{ matrix.msrv }} check - run: | - cargo check --all-features --locked diff --git a/embassy-mcxa/.github/workflows/nostd.yml b/embassy-mcxa/.github/workflows/nostd.yml deleted file mode 100644 index cf6629854..000000000 --- a/embassy-mcxa/.github/workflows/nostd.yml +++ /dev/null @@ -1,38 +0,0 @@ -# This workflow checks whether the library is able to run without the std library (e.g., embedded). -# This entire file should be removed if this crate does not support no-std. See check.yml for -# information about how the concurrency cancellation and workflow triggering works -permissions: - contents: read - -on: - push: - branches: [main, main-nextgen] - pull_request: - -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -name: no-std - -jobs: - nostd: - runs-on: ubuntu-latest - name: ${{ matrix.target }} - - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - targets: thumbv8m.main-none-eabihf - - - name: Show variable - run: echo ${{ env.TOKEN }} - - - name: cargo check - run: | - cargo check --target thumbv8m.main-none-eabihf --all-features --locked diff --git a/embassy-mcxa/.github/workflows/rolling.yml b/embassy-mcxa/.github/workflows/rolling.yml deleted file mode 100644 index 73b48484a..000000000 --- a/embassy-mcxa/.github/workflows/rolling.yml +++ /dev/null @@ -1,58 +0,0 @@ -# This workflow runs every morning at midnight. It will run cargo hack -# and a build with msrv. If any dependency breaks our crate, we will -# know ASAP. -# -# - check: build with all features -# - msrv: check that the msrv specified in the crate is correct -permissions: - contents: read - -on: - schedule: - - cron: '0 0 * * *' - -name: rolling -jobs: - - check: - runs-on: ubuntu-latest - name: ubuntu / stable / features - strategy: - fail-fast: false - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - name: Install stable - uses: dtolnay/rust-toolchain@stable - with: - targets: thumbv8m.main-none-eabihf - - - name: cargo install cargo-hack - uses: taiki-e/install-action@cargo-hack - - name: cargo check - run: | - cargo update - cargo check --all-features - - msrv: - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - msrv: ["1.91"] - - name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }}) - steps: - - uses: actions/checkout@v6 - with: - submodules: true - - name: Install ${{ matrix.msrv }} - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.msrv }} - targets: thumbv8m.main-none-eabihf - - name: cargo +${{ matrix.msrv }} check - run: | - cargo update - cargo check --all-features -- cgit From a08fc1a78065fe42a5eb9a82d1c277b277a57556 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:42:17 +0100 Subject: Remove some misc bits --- embassy-mcxa/Cargo.lock | 918 ------------------ embassy-mcxa/Cargo.toml | 2 +- embassy-mcxa/Embed.toml | 28 - embassy-mcxa/deny.toml | 241 ----- embassy-mcxa/ram.ld | 109 --- embassy-mcxa/supply-chain/README.md | 149 --- embassy-mcxa/supply-chain/audits.toml | 349 ------- embassy-mcxa/supply-chain/config.toml | 141 --- embassy-mcxa/supply-chain/imports.lock | 523 ---------- embassy-mcxa/tools/run_and_attach_rtt.sh | 24 - embassy-mcxa/tools/run_jlink_noblock.sh | 76 -- examples/mcxa/Cargo.lock | 1555 ------------------------------ 12 files changed, 1 insertion(+), 4114 deletions(-) delete mode 100644 embassy-mcxa/Cargo.lock delete mode 100644 embassy-mcxa/Embed.toml delete mode 100644 embassy-mcxa/deny.toml delete mode 100644 embassy-mcxa/ram.ld delete mode 100644 embassy-mcxa/supply-chain/README.md delete mode 100644 embassy-mcxa/supply-chain/audits.toml delete mode 100644 embassy-mcxa/supply-chain/config.toml delete mode 100644 embassy-mcxa/supply-chain/imports.lock delete mode 100644 embassy-mcxa/tools/run_and_attach_rtt.sh delete mode 100644 embassy-mcxa/tools/run_jlink_noblock.sh delete mode 100644 examples/mcxa/Cargo.lock diff --git a/embassy-mcxa/Cargo.lock b/embassy-mcxa/Cargo.lock deleted file mode 100644 index 22b59c395..000000000 --- a/embassy-mcxa/Cargo.lock +++ /dev/null @@ -1,918 +0,0 @@ -# This file is automatically @generated by Cargo. -# It is not intended for manual editing. -version = 4 - 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-[default.flashing] -# Attach-only: don't flash (we already loaded to RAM) -enabled = false - -[default.reset] -# Don't reset; keep running app started by run_jlink_noblock.sh -enabled = false - -[default.general] -# The chip name of the target -chip = "MCXA276" - -[default.gdb] -# Whether or not a GDB server should be opened after loading -enabled = false - -[default.rtt] -# Enable RTT for debugging output -enabled = true - -# Increase timeout for RTT CB discovery -up_channels = [ { channel = 0, mode = "BlockIfFull" } ] -timeout = 5000 diff --git a/embassy-mcxa/deny.toml b/embassy-mcxa/deny.toml deleted file mode 100644 index 7097f2f55..000000000 --- a/embassy-mcxa/deny.toml +++ /dev/null @@ -1,241 +0,0 @@ -# This template contains all of the possible sections and their default values - -# Note that all fields that take a lint level have these possible values: -# * deny - An error will be produced and the check will fail -# * warn - A warning will be produced, but the check will not fail -# * allow - No warning or error will be produced, though in some cases a note -# will be - -# The values provided in this template are the default values that will be used -# when any section or field is not specified in your own configuration - -# Root options - -# The graph table configures how the dependency graph is constructed and thus -# which crates the checks are performed against -[graph] -# If 1 or more target triples (and optionally, target_features) are specified, -# only the specified targets will be checked when running `cargo deny check`. -# This means, if a particular package is only ever used as a target specific -# dependency, such as, for example, the `nix` crate only being used via the -# `target_family = "unix"` configuration, that only having windows targets in -# this list would mean the nix crate, as well as any of its exclusive -# dependencies not shared by any other crates, would be ignored, as the target -# list here is effectively saying which targets you are building for. -targets = [ - # The triple can be any string, but only the target triples built in to - # rustc (as of 1.40) can be checked against actual config expressions - #"x86_64-unknown-linux-musl", - # You can also specify which target_features you promise are enabled for a - # particular target. target_features are currently not validated against - # the actual valid features supported by the target architecture. - #{ triple = "wasm32-unknown-unknown", features = ["atomics"] }, -] -# When creating the dependency graph used as the source of truth when checks are -# executed, this field can be used to prune crates from the graph, removing them -# from the view of cargo-deny. This is an extremely heavy hammer, as if a crate -# is pruned from the graph, all of its dependencies will also be pruned unless -# they are connected to another crate in the graph that hasn't been pruned, -# so it should be used with care. The identifiers are [Package ID Specifications] -# (https://doc.rust-lang.org/cargo/reference/pkgid-spec.html) -#exclude = [] -# If true, metadata will be collected with `--all-features`. Note that this can't -# be toggled off if true, if you want to conditionally enable `--all-features` it -# is recommended to pass `--all-features` on the cmd line instead -all-features = false -# If true, metadata will be collected with `--no-default-features`. The same -# caveat with `all-features` applies -no-default-features = false -# If set, these feature will be enabled when collecting metadata. If `--features` -# is specified on the cmd line they will take precedence over this option. -#features = [] - -# The output table provides options for how/if diagnostics are outputted -[output] -# When outputting inclusion graphs in diagnostics that include features, this -# option can be used to specify the depth at which feature edges will be added. -# This option is included since the graphs can be quite large and the addition -# of features from the crate(s) to all of the graph roots can be far too verbose. -# This option can be overridden via `--feature-depth` on the cmd line -feature-depth = 1 - -# This section is considered when running `cargo deny check advisories` -# More documentation for the advisories section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/advisories/cfg.html -[advisories] -# The path where the advisory databases are cloned/fetched into -#db-path = "$CARGO_HOME/advisory-dbs" -# The url(s) of the advisory databases to use -#db-urls = ["https://github.com/rustsec/advisory-db"] -# A list of advisory IDs to ignore. Note that ignored advisories will still -# output a note when they are encountered. -ignore = [ - #"RUSTSEC-0000-0000", - #{ id = "RUSTSEC-0000-0000", reason = "you can specify a reason the advisory is ignored" }, - #"a-crate-that-is-yanked@0.1.1", # you can also ignore yanked crate versions if you wish - #{ crate = "a-crate-that-is-yanked@0.1.1", reason = "you can specify why you are ignoring the yanked crate" }, - # { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." }, - { id = "RUSTSEC-2024-0436", reason = "there are no suitable replacements for paste right now; paste has been archived as read-only. It only affects compile time concatenation in macros. We will allow it for now" }, - # { id = "RUSTSEC-2023-0089", reason = "this is a deprecation warning for a dependency of a dependency. https://github.com/jamesmunns/postcard/issues/223 tracks fixing the dependency; until that's resolved, we can accept the deprecated code as it has no known vulnerabilities."} -] -# If this is true, then cargo deny will use the git executable to fetch advisory database. -# If this is false, then it uses a built-in git library. -# Setting this to true can be helpful if you have special authentication requirements that cargo-deny does not support. -# See Git Authentication for more information about setting up git authentication. -#git-fetch-with-cli = true - -# This section is considered when running `cargo deny check licenses` -# More documentation for the licenses section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/licenses/cfg.html -[licenses] -# List of explicitly allowed licenses -# See https://spdx.org/licenses/ for list of possible licenses -# [possible values: any SPDX 3.11 short identifier (+ optional exception)]. -allow = [ - "MIT", - "Apache-2.0", - - # unicode-ident 1.0.14 switched from Unicode-DFS-2016 to Unicode-3.0 license. - "Unicode-3.0", - #"Apache-2.0 WITH LLVM-exception", -] -# The confidence threshold for detecting a license from license text. -# The higher the value, the more closely the license text must be to the -# canonical license text of a valid SPDX license file. -# [possible values: any between 0.0 and 1.0]. -confidence-threshold = 0.8 -# Allow 1 or more licenses on a per-crate basis, so that particular licenses -# aren't accepted for every possible crate as with the normal allow list -exceptions = [ - # Each entry is the crate and version constraint, and its specific allow - # list - #{ allow = ["Zlib"], crate = "adler32" }, -] - -# Some crates don't have (easily) machine readable licensing information, -# adding a clarification entry for it allows you to manually specify the -# licensing information -#[[licenses.clarify]] -# The package spec the clarification applies to -#crate = "ring" -# The SPDX expression for the license requirements of the crate -#expression = "MIT AND ISC AND OpenSSL" -# One or more files in the crate's source used as the "source of truth" for -# the license expression. If the contents match, the clarification will be used -# when running the license check, otherwise the clarification will be ignored -# and the crate will be checked normally, which may produce warnings or errors -# depending on the rest of your configuration -#license-files = [ -# Each entry is a crate relative path, and the (opaque) hash of its contents -#{ path = "LICENSE", hash = 0xbd0eed23 } -#] - -[licenses.private] -# If true, ignores workspace crates that aren't published, or are only -# published to private registries. -# To see how to mark a crate as unpublished (to the official registry), -# visit https://doc.rust-lang.org/cargo/reference/manifest.html#the-publish-field. -ignore = false -# One or more private registries that you might publish crates to, if a crate -# is only published to private registries, and ignore is true, the crate will -# not have its license(s) checked -registries = [ - #"https://sekretz.com/registry -] - -# This section is considered when running `cargo deny check bans`. -# More documentation about the 'bans' section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/bans/cfg.html -[bans] -# Lint level for when multiple versions of the same crate are detected -multiple-versions = "warn" -# Lint level for when a crate version requirement is `*` -wildcards = "allow" -# The graph highlighting used when creating dotgraphs for crates -# with multiple versions -# * lowest-version - The path to the lowest versioned duplicate is highlighted -# * simplest-path - The path to the version with the fewest edges is highlighted -# * all - Both lowest-version and simplest-path are used -highlight = "all" -# The default lint level for `default` features for crates that are members of -# the workspace that is being checked. This can be overridden by allowing/denying -# `default` on a crate-by-crate basis if desired. -workspace-default-features = "allow" -# The default lint level for `default` features for external crates that are not -# members of the workspace. This can be overridden by allowing/denying `default` -# on a crate-by-crate basis if desired. -external-default-features = "allow" -# List of crates that are allowed. Use with care! -allow = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is allowed" }, -] -# List of crates to deny -deny = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason it is banned" }, - # Wrapper crates can optionally be specified to allow the crate when it - # is a direct dependency of the otherwise banned crate - #{ crate = "ansi_term@0.11.0", wrappers = ["this-crate-directly-depends-on-ansi_term"] }, -] - -# List of features to allow/deny -# Each entry the name of a crate and a version range. If version is -# not specified, all versions will be matched. -#[[bans.features]] -#crate = "reqwest" -# Features to not allow -#deny = ["json"] -# Features to allow -#allow = [ -# "rustls", -# "__rustls", -# "__tls", -# "hyper-rustls", -# "rustls", -# "rustls-pemfile", -# "rustls-tls-webpki-roots", -# "tokio-rustls", -# "webpki-roots", -#] -# If true, the allowed features must exactly match the enabled feature set. If -# this is set there is no point setting `deny` -#exact = true - -# Certain crates/versions that will be skipped when doing duplicate detection. -skip = [ - #"ansi_term@0.11.0", - #{ crate = "ansi_term@0.11.0", reason = "you can specify a reason why it can't be updated/removed" }, -] -# Similarly to `skip` allows you to skip certain crates during duplicate -# detection. Unlike skip, it also includes the entire tree of transitive -# dependencies starting at the specified crate, up to a certain depth, which is -# by default infinite. -skip-tree = [ - #"ansi_term@0.11.0", # will be skipped along with _all_ of its direct and transitive dependencies - #{ crate = "ansi_term@0.11.0", depth = 20 }, -] - -# This section is considered when running `cargo deny check sources`. -# More documentation about the 'sources' section can be found here: -# https://embarkstudios.github.io/cargo-deny/checks/sources/cfg.html -[sources] -# Lint level for what to happen when a crate from a crate registry that is not -# in the allow list is encountered -unknown-registry = "warn" -# Lint level for what to happen when a crate from a git repository that is not -# in the allow list is encountered -unknown-git = "warn" -# List of URLs for allowed crate registries. Defaults to the crates.io index -# if not specified. If it is specified but empty, no registries are allowed. -allow-registry = ["https://github.com/rust-lang/crates.io-index"] -# List of URLs for allowed Git repositories -allow-git = [] - -[sources.allow-org] -# github.com organizations to allow git sources for -github = ["OpenDevicePartnership"] -# gitlab.com organizations to allow git sources for -gitlab = [] -# bitbucket.org organizations to allow git sources for -bitbucket = [] diff --git a/embassy-mcxa/ram.ld b/embassy-mcxa/ram.ld deleted file mode 100644 index 816ab6819..000000000 --- a/embassy-mcxa/ram.ld +++ /dev/null @@ -1,109 +0,0 @@ -/* Simple RAM execution linker script for MCXA276 */ -MEMORY -{ - RAM : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* Pull in device default interrupt symbol aliases (e.g., CMC = DefaultHandler) */ -INCLUDE device.x - - -/* Provide core exception weak aliases if not supplied by cortex-m-rt's link.x */ -PROVIDE(NonMaskableInt = DefaultHandler); -PROVIDE(HardFault = DefaultHandler); -PROVIDE(MemoryManagement = DefaultHandler); -PROVIDE(BusFault = DefaultHandler); -PROVIDE(UsageFault = DefaultHandler); -PROVIDE(SecureFault = DefaultHandler); -PROVIDE(SVCall = DefaultHandler); -PROVIDE(DebugMonitor = DefaultHandler); -PROVIDE(PendSV = DefaultHandler); -PROVIDE(SysTick = DefaultHandler); - -/* In RAM-run we have no FLASH sidata; copy from sdata */ -__sidata = __sdata; - -/* Ensure the PAC interrupt table is kept */ -EXTERN(__INTERRUPTS); - - -/* Pull in defmt's linker script to generate the defmt table that host decoders expect */ -INCLUDE defmt.x - -ENTRY(Reset) -EXTERN(VECTOR_TABLE) -EXTERN(Reset) -EXTERN(main) - -/* Define _stack_start at end of RAM BEFORE it's used in vector table */ -_stack_start = ORIGIN(RAM) + LENGTH(RAM); - -SECTIONS -{ - .vector_table ORIGIN(RAM) : - { - /* Slot 0: Initial stack pointer - use our explicitly set _stack_start */ - LONG(_stack_start); - /* Slot 1: Reset vector - address of Reset function with Thumb bit set */ - LONG(Reset | 1); - /* Cortex-M33 core exceptions (slots 2-14) */ - KEEP(*(.vector_table.exceptions)); - /* Peripheral interrupt vectors provided by PAC (slots 16+) */ - KEEP(*(.vector_table.interrupts)); - } > RAM - - .text : - { - KEEP(*(.text.Reset)); - KEEP(*(.text.main)); - *(.text .text.*); - } > RAM - - /* Keep defmt table and fragments so host decoders can find metadata */ - .defmt : - { - KEEP(*(.defmt)); - KEEP(*(.defmt.*)); - } > RAM - - .rodata : - { - *(.rodata .rodata.*); - } > RAM - - .data : - { - . = ALIGN(4); - __sdata = .; - *(.data .data.*); - . = ALIGN(4); - __edata = .; - } > RAM - - /* Ensure RTT control block with "SEGGER RTT" signature is loaded to RAM */ - .rtt : - { - KEEP(*(.rtt)); - } > RAM - - /* Place uninitialized buffers (like defmt-rtt) in RAM; load is fine for RAM-run */ - .uninit : - { - *(.uninit .uninit.*); - } > RAM - - .bss : - { - . = ALIGN(4); - __sbss = .; - *(.bss .bss.*); - . = ALIGN(4); - __ebss = .; - } > RAM - - /* Discard exception unwinding info */ - /DISCARD/ : - { - *(.ARM.exidx .ARM.exidx.*); - } -} diff --git a/embassy-mcxa/supply-chain/README.md b/embassy-mcxa/supply-chain/README.md deleted file mode 100644 index 1f2f6c69e..000000000 --- a/embassy-mcxa/supply-chain/README.md +++ /dev/null @@ -1,149 +0,0 @@ -# Working with cargo vet - -## Introduction - -`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity. -It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust. -To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet) - ---- - -## Adding a new dependency - -When updating or adding a new dependency, we need to ensure it's audited before being merged into main. -For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository. -_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._ -Follow the process below to ensure compliance: - -### For Developers -1. **Respond to `cargo vet` failures**: - - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire - - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies - -2. **Engage with auditors**: - - Respond to any questions that the auditors might have regarding the need of any new dependencies - -3. **Rebase and verify**: - - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository - - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet` - ```bash - git fetch upstream - git rebase upstream/main - cargo vet - ``` - -4. **Update PR**: - - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR - - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase - ```bash - git push -f - ``` - -5. **Check PR status**: - - The existing PR comment from the previous failure will be updated with a success message once the check passes - -### For Auditors - -1. **Review the questionnaire**: - - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure - - Respond to the developer comment in case more information is needed - -2. **Audit new dependencies**: - - Inspect the `cargo vet` failures using your preferred method - - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked` - - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked` - - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally) - -3. **Follow `cargo vet` recommendations**: - - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies - -4. **Record audits**: - - Use `cargo vet certify` to add new audits to _audits.toml_ - - Verify all dependencies pass using `cargo vet` - -5. **Decide audit location**: - - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) - - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits - -6. **Communicate successful audit**: - - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass - ---- - -## Audit criteria -`cargo vet` comes pre-equipped with two built-in criteria but supports adding new criteria to suit our needs. -As defined [here](https://mozilla.github.io/cargo-vet/built-in-criteria.html), the default criteria are: - -- **safe-to-run** - This crate can be compiled, run, and tested on a local workstation or in - controlled automation without surprising consequences, such as: - * Reading or writing data from sensitive or unrelated parts of the filesystem. - * Installing software or reconfiguring the device. - * Connecting to untrusted network endpoints. - * Misuse of system resources (e.g. cryptocurrency mining). - -- **safe-to-deploy** - This crate will not introduce a serious security vulnerability to production - software exposed to untrusted input. - - Auditors are not required to perform a full logic review of the entire crate. - Rather, they must review enough to fully reason about the behavior of all unsafe - blocks and usage of powerful imports. For any reasonable usage of the crate in - real-world software, an attacker must not be able to manipulate the runtime - behavior of these sections in an exploitable or surprising way. - - Ideally, all unsafe code is fully sound, and ambient capabilities (e.g. - filesystem access) are hardened against manipulation and consistent with the - advertised behavior of the crate. However, some discretion is permitted. In such - cases, the nature of the discretion should be recorded in the `notes` field of - the audit record. - - For crates which generate deployed code (e.g. build dependencies or procedural - macros), reasonable usage of the crate should output code which meets the above - criteria. - - **Note: `safe-to-deploy` implies `safe-to-run`** - ---- - -## Conducting an audit - -When performing an audit for a new or updated dependency, auditors may consider the following criteria to ensure the safety, reliability, and suitability of the crate for use in our projects: - -- **Security**: - - Review the crate for known vulnerabilities or security advisories. - - Check for unsafe code usage and ensure it is justified and well-documented. - - Evaluate the crate’s history of security issues and responsiveness to reported problems. - -- **Maintenance and Activity**: - - Assess the frequency of updates and the responsiveness of maintainers to issues and pull requests. - - Prefer crates that are actively maintained and have a healthy contributor base. - -- **License Compliance**: - - Verify that the crate’s license is compatible with our project’s licensing requirements. - -- **Community Trust and Adoption**: - - Consider the crate’s adoption in the wider Rust ecosystem. - - Prefer crates that are widely used and trusted by the community. - -- **Functionality and Suitability**: - - Confirm that the crate provides the required functionality without unnecessary features or bloat. - - Evaluate whether the crate’s API is stable and unlikely to introduce breaking changes unexpectedly. - -- **Audit Trail**: - - Record the audit decision, including any concerns, mitigations, or recommendations for future updates. - - If exemptions are granted, document the justification and any follow-up actions required. - ---- - -## Tips for using `cargo vet`: - -- **Update _imports.lock_**: - - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project. - -- **Add exemptions**: - - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption ` to add the dependency to exemptions in _config.toml_ - - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions` - -- **Prune unnecessary entries**: - - Remove unnecessary exemptions and imports using `cargo vet prune` \ No newline at end of file diff --git a/embassy-mcxa/supply-chain/audits.toml b/embassy-mcxa/supply-chain/audits.toml deleted file mode 100644 index 871109648..000000000 --- a/embassy-mcxa/supply-chain/audits.toml +++ /dev/null @@ -1,349 +0,0 @@ - -# cargo-vet audits file - -[[audits.autocfg]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.5.0" - -[[audits.cc]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.2.47" - -[[audits.cfg-if]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.4" - -[[audits.cordyceps]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.3.4" - -[[audits.darling]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.20.11" - -[[audits.darling_core]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.20.11" - -[[audits.darling_macro]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.20.11" - -[[audits.defmt-rtt]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.0" -notes = "defmt-rtt is used for all our logging purposes. Version 1.0.0 merely stabilizes what was already available previously." - -[[audits.defmt-rtt]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 1.1.0" - -[[audits.document-features]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.2.12" - -[[audits.document-features]] -who = "Felipe Balbi " -criteria = "safe-to-run" -version = "0.2.12" - -[[audits.embassy-executor]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.9.1" - -[[audits.embassy-executor-macros]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.7.0" - -[[audits.embassy-executor-timer-queue]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.0" - -[[audits.embassy-executor-timer-queue]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.0" - -[[audits.embassy-time-queue-utils]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.3.0" - -[[audits.find-msvc-tools]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.5" - -[[audits.generator]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.8.7" - -[[audits.ident_case]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.1" - -[[audits.litrs]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.0" - -[[audits.maitake-sync]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.2.2" - -[[audits.mutex-traits]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.1" - -[[audits.mycelium-bitfield]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.5" - -[[audits.once_cell]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.20.1" - -[[audits.panic-probe]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.0" - -[[audits.pin-project]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.1.10" - -[[audits.pin-project-internal]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.1.10" - -[[audits.portable-atomic]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.11.1" - -[[audits.proc-macro2]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.103" - -[[audits.quote]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.42" - -[[audits.stable_deref_trait]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.2.1" - -[[audits.static_cell]] -who = "jerrysxie " -criteria = "safe-to-run" -delta = "2.1.0 -> 2.1.1" - -[[audits.syn]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "2.0.110" - -[[audits.syn]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -delta = "2.0.100 -> 2.0.109" - -[[audits.thiserror]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "2.0.17" - -[[audits.thiserror-impl]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "2.0.17" - -[[audits.unicode-ident]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "1.0.22" - -[[audits.valuable]] -who = "Felipe Balbi " -criteria = "safe-to-deploy" -version = "0.1.1" - -[[trusted.aho-corasick]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-03-28" -end = "2026-11-26" - -[[trusted.cc]] -criteria = "safe-to-deploy" -user-id = 55123 # rust-lang-owner -start = "2022-10-29" -end = "2026-11-26" - -[[trusted.find-msvc-tools]] -criteria = "safe-to-deploy" -user-id = 539 -start = "2025-08-29" -end = "2026-11-26" - -[[trusted.libc]] -criteria = "safe-to-deploy" -user-id = 55123 # rust-lang-owner -start = "2024-08-15" -end = "2026-11-26" - -[[trusted.loom]] -criteria = "safe-to-deploy" -user-id = 6741 # Alice Ryhl (Darksonn) -start = "2021-04-12" -end = "2026-11-26" - -[[trusted.memchr]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-07-07" -end = "2026-11-26" - -[[trusted.paste]] -criteria = "safe-to-deploy" -user-id = 3618 # David Tolnay (dtolnay) -start = "2019-03-19" -end = "2026-11-26" - -[[trusted.regex-automata]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-02-25" -end = "2026-11-26" - -[[trusted.regex-syntax]] -criteria = "safe-to-deploy" -user-id = 189 # Andrew Gallant (BurntSushi) -start = "2019-03-30" -end = "2026-11-26" - -[[trusted.rustversion]] -criteria = "safe-to-deploy" -user-id = 3618 # David Tolnay (dtolnay) -start = "2019-07-08" -end = "2026-11-26" - -[[trusted.scoped-tls]] -criteria = "safe-to-deploy" -user-id = 1 # Alex Crichton (alexcrichton) -start = "2019-02-26" -end = "2026-11-26" - -[[trusted.thread_local]] -criteria = "safe-to-deploy" -user-id = 2915 # Amanieu d'Antras (Amanieu) -start = "2019-09-07" -end = "2026-11-26" - -[[trusted.tracing-subscriber]] -criteria = "safe-to-deploy" -user-id = 10 # Carl Lerche (carllerche) -start = "2025-08-29" -end = "2026-11-26" - -[[trusted.valuable]] -criteria = "safe-to-deploy" -user-id = 10 # Carl Lerche (carllerche) -start = "2022-01-03" -end = "2026-11-26" - -[[trusted.windows]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2021-01-15" -end = "2026-11-26" - -[[trusted.windows-collections]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2025-02-06" -end = "2026-11-26" - -[[trusted.windows-core]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2021-11-15" -end = "2026-11-26" - -[[trusted.windows-future]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2025-02-10" -end = "2026-11-26" - -[[trusted.windows-implement]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2022-01-27" -end = "2026-11-26" - -[[trusted.windows-interface]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2022-02-18" -end = "2026-11-26" - -[[trusted.windows-link]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2024-07-17" -end = "2026-11-26" - -[[trusted.windows-numerics]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2023-05-15" -end = "2026-11-26" - -[[trusted.windows-result]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2024-02-02" -end = "2026-11-26" - -[[trusted.windows-strings]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2024-02-02" -end = "2026-11-26" - -[[trusted.windows-sys]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2021-11-15" -end = "2026-11-26" - -[[trusted.windows-threading]] -criteria = "safe-to-deploy" -user-id = 64539 # Kenny Kerr (kennykerr) -start = "2025-04-29" -end = "2026-11-26" diff --git a/embassy-mcxa/supply-chain/config.toml b/embassy-mcxa/supply-chain/config.toml deleted file mode 100644 index 5682db9ea..000000000 --- a/embassy-mcxa/supply-chain/config.toml +++ /dev/null @@ -1,141 +0,0 @@ - -# cargo-vet config file - -[cargo-vet] -version = "0.10" - -[imports.OpenDevicePartnership] -url = "https://raw.githubusercontent.com/OpenDevicePartnership/rust-crate-audits/main/audits.toml" - -[imports.bytecode-alliance] -url = "https://raw.githubusercontent.com/bytecodealliance/wasmtime/main/supply-chain/audits.toml" - -[imports.google] -url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" - -[imports.mozilla] -url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" - -[[exemptions.bare-metal]] -version = "0.2.5" -criteria = "safe-to-deploy" - -[[exemptions.bitfield]] -version = "0.13.2" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m]] -version = "0.7.7" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m-rt]] -version = "0.7.5" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m-rt-macros]] -version = "0.7.5" -criteria = "safe-to-deploy" - -[[exemptions.critical-section]] -version = "1.2.0" -criteria = "safe-to-deploy" - -[[exemptions.defmt]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.defmt-macros]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.defmt-parser]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-embedded-hal]] -version = "0.5.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-futures]] -version = "0.1.2" -criteria = "safe-to-deploy" - -[[exemptions.embassy-hal-internal]] -version = "0.3.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-sync]] -version = "0.7.2" -criteria = "safe-to-deploy" - -[[exemptions.embassy-time]] -version = "0.5.0" -criteria = "safe-to-deploy" - -[[exemptions.embassy-time-driver]] -version = "0.2.1" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal]] -version = "0.2.7" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal-async]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal-nb]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.embedded-io-async]] -version = "0.6.1" -criteria = "safe-to-deploy" - -[[exemptions.embedded-storage]] -version = "0.3.1" -criteria = "safe-to-deploy" - -[[exemptions.embedded-storage-async]] -version = "0.4.1" -criteria = "safe-to-deploy" - -[[exemptions.hash32]] -version = "0.3.1" -criteria = "safe-to-deploy" - -[[exemptions.heapless]] -version = "0.8.0" -criteria = "safe-to-deploy" - -[[exemptions.proc-macro-error-attr2]] -version = "2.0.0" -criteria = "safe-to-deploy" - -[[exemptions.proc-macro-error2]] -version = "2.0.1" -criteria = "safe-to-deploy" - -[[exemptions.rustc_version]] -version = "0.2.3" -criteria = "safe-to-deploy" - -[[exemptions.semver]] -version = "0.9.0" -criteria = "safe-to-deploy" - -[[exemptions.semver-parser]] -version = "0.7.0" -criteria = "safe-to-deploy" - -[[exemptions.vcell]] -version = "0.1.3" -criteria = "safe-to-deploy" - -[[exemptions.volatile-register]] -version = "0.2.2" -criteria = "safe-to-deploy" diff --git a/embassy-mcxa/supply-chain/imports.lock b/embassy-mcxa/supply-chain/imports.lock deleted file mode 100644 index dbd1235b0..000000000 --- a/embassy-mcxa/supply-chain/imports.lock +++ /dev/null @@ -1,523 +0,0 @@ - -# cargo-vet imports lock - -[[publisher.aho-corasick]] -version = "1.1.4" -when = "2025-10-28" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.libc]] -version = "0.2.177" -when = "2025-10-09" -user-id = 55123 -user-login = "rust-lang-owner" - -[[publisher.loom]] -version = "0.7.2" -when = "2024-04-23" -user-id = 6741 -user-login = "Darksonn" -user-name = "Alice Ryhl" - -[[publisher.memchr]] -version = "2.7.6" -when = "2025-09-25" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.paste]] -version = "1.0.15" -when = "2024-05-07" -user-id = 3618 -user-login = "dtolnay" -user-name = "David Tolnay" - -[[publisher.regex-automata]] -version = "0.4.13" -when = "2025-10-13" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.regex-syntax]] -version = "0.8.8" -when = "2025-10-13" -user-id = 189 -user-login = "BurntSushi" -user-name = "Andrew Gallant" - -[[publisher.rustversion]] -version = "1.0.22" -when = "2025-08-08" -user-id = 3618 -user-login = "dtolnay" -user-name = "David Tolnay" - -[[publisher.scoped-tls]] -version = "1.0.1" -when = "2022-10-31" -user-id = 1 -user-login = "alexcrichton" -user-name = "Alex Crichton" - -[[publisher.thread_local]] -version = "1.1.9" -when = "2025-06-12" -user-id = 2915 -user-login = "Amanieu" -user-name = "Amanieu d'Antras" - -[[publisher.tracing-subscriber]] -version = "0.3.20" -when = "2025-08-29" -user-id = 10 -user-login = "carllerche" -user-name = "Carl Lerche" - -[[publisher.windows]] -version = "0.61.3" -when = "2025-06-12" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-collections]] -version = "0.2.0" -when = "2025-03-18" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-core]] -version = "0.61.2" -when = "2025-05-19" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-future]] -version = "0.2.1" -when = "2025-05-15" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-implement]] -version = "0.60.2" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-interface]] -version = "0.59.3" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-link]] -version = "0.1.3" -when = "2025-06-12" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-link]] -version = "0.2.1" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-numerics]] -version = "0.2.0" -when = "2025-03-18" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-result]] -version = "0.3.4" -when = "2025-05-19" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-strings]] -version = "0.4.2" -when = "2025-05-19" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-sys]] -version = "0.61.2" -when = "2025-10-06" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[[publisher.windows-threading]] -version = "0.1.0" -when = "2025-05-15" -user-id = 64539 -user-login = "kennykerr" -user-name = "Kenny Kerr" - -[audits.OpenDevicePartnership.audits] - -[[audits.bytecode-alliance.audits.embedded-io]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "0.4.0" -notes = "No `unsafe` code and only uses `std` in ways one would expect the crate to do so." - -[[audits.bytecode-alliance.audits.embedded-io]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.0 -> 0.6.1" -notes = "Major updates, but almost all safe code. Lots of pruning/deletions, nothing out of the ordrinary." - -[[audits.bytecode-alliance.audits.futures-core]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.3.27" -notes = "Unsafe used to implement a concurrency primitive AtomicWaker. Well-commented and not obviously incorrect. Like my other audits of these concurrency primitives inside the futures family, I couldn't certify that it is correct without formal methods, but that is out of scope for this vetting." - -[[audits.bytecode-alliance.audits.futures-core]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -delta = "0.3.28 -> 0.3.31" - -[[audits.bytecode-alliance.audits.futures-sink]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.3.27" - -[[audits.bytecode-alliance.audits.futures-sink]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -delta = "0.3.28 -> 0.3.31" - -[[audits.bytecode-alliance.audits.log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.22 -> 0.4.27" -notes = "Lots of minor updates to macros and such, nothing touching `unsafe`" - -[[audits.bytecode-alliance.audits.log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.27 -> 0.4.28" -notes = "Minor doc updates and lots new tests, nothing out of the ordinary." - -[[audits.bytecode-alliance.audits.matchers]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.1.0" - -[[audits.bytecode-alliance.audits.matchers]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.0 -> 0.2.0" -notes = "Some unsafe code, but not more than before. Nothing awry." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.46.0" -notes = "one use of unsafe to call windows specific api to get console handle." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.46.0 -> 0.50.1" -notes = "Lots of stylistic/rust-related chanegs, plus new features, but nothing out of the ordrinary." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.50.1 -> 0.50.3" -notes = "CI changes, Rust changes, nothing out of the ordinary." - -[[audits.bytecode-alliance.audits.sharded-slab]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.1.4" -notes = "I always really enjoy reading eliza's code, she left perfect comments at every use of unsafe." - -[[audits.bytecode-alliance.audits.shlex]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "1.1.0" -notes = "Only minor `unsafe` code blocks which look valid and otherwise does what it says on the tin." - -[[audits.bytecode-alliance.audits.tracing-attributes]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.28 -> 0.1.30" -notes = "Few code changes, a pretty minor update." - -[[audits.bytecode-alliance.audits.tracing-core]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.33 -> 0.1.34" -notes = "Mostly just an update with Rust stylistic conventions changing. Nothing awry." - -[[audits.bytecode-alliance.audits.tracing-log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "0.1.3" -notes = """ -This is a standard adapter between the `log` ecosystem and the `tracing` -ecosystem. There's one `unsafe` block in this crate and it's well-scoped. -""" - -[[audits.bytecode-alliance.audits.tracing-log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.3 -> 0.2.0" -notes = "Nothing out of the ordinary, a typical major version update and nothing awry." - -[[audits.google.audits.bitflags]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.3.2" -notes = """ -Security review of earlier versions of the crate can be found at -(Google-internal, sorry): go/image-crate-chromium-security-review - -The crate exposes a function marked as `unsafe`, but doesn't use any -`unsafe` blocks (except for tests of the single `unsafe` function). I -think this justifies marking this crate as `ub-risk-1`. - -Additional review comments can be found at https://crrev.com/c/4723145/31 -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.byteorder]] -who = "danakj " -criteria = "safe-to-deploy" -version = "1.5.0" -notes = "Unsafe review in https://crrev.com/c/5838022" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.lazy_static]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.4.0" -notes = ''' -I grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits. - -There are two places where `unsafe` is used. Unsafe review notes can be found -in https://crrev.com/c/5347418. - -This crate has been added to Chromium in https://crrev.com/c/3321895. -''' -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.lazy_static]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.4.0 -> 1.5.0" -notes = "Unsafe review notes: https://crrev.com/c/5650836" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.log]] -who = "danakj " -criteria = "safe-to-deploy" -version = "0.4.22" -notes = """ -Unsafe review in https://docs.google.com/document/d/1IXQbD1GhTRqNHIGxq6yy7qHqxeO4CwN5noMFXnqyDIM/edit?usp=sharing - -Unsafety is generally very well-documented, with one exception, which we -describe in the review doc. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -version = "1.0.0" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 0.1.3" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 1.1.0" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.num-traits]] -who = "Manish Goregaokar " -criteria = "safe-to-deploy" -version = "0.2.19" -notes = "Contains a single line of float-to-int unsafe with decent safety comments" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.pin-project-lite]] -who = "David Koloski " -criteria = "safe-to-deploy" -version = "0.2.9" -notes = "Reviewed on https://fxrev.dev/824504" -aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.pin-project-lite]] -who = "David Koloski " -criteria = "safe-to-deploy" -delta = "0.2.9 -> 0.2.13" -notes = "Audited at https://fxrev.dev/946396" -aggregated-from = "https://fuchsia.googlesource.com/fuchsia/+/refs/heads/main/third_party/rust_crates/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.smallvec]] -who = "Manish Goregaokar " -criteria = "safe-to-deploy" -version = "1.13.2" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.smallvec]] -who = "Jonathan Hao " -criteria = "safe-to-deploy" -delta = "1.13.2 -> 1.14.0" -notes = """ -WARNING: This certification is a result of a **partial** audit. The -`malloc_size_of` feature has **not** been audited. This feature does -not explicitly document its safety requirements. -See also https://chromium-review.googlesource.com/c/chromium/src/+/6275133/comment/ea0d7a93_98051a2e/ -and https://github.com/servo/malloc_size_of/issues/8. -This feature is banned in gnrt_config.toml. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.void]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -version = "1.0.2" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.mozilla.audits.futures-core]] -who = "Mike Hommey " -criteria = "safe-to-deploy" -delta = "0.3.27 -> 0.3.28" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.futures-sink]] -who = "Mike Hommey " -criteria = "safe-to-deploy" -delta = "0.3.27 -> 0.3.28" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.20.1 -> 1.20.2" -notes = "This update works around a Cargo bug that forces the addition of `portable-atomic` into a lockfile, which we have never needed to use." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.20.2 -> 1.20.3" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.20.3 -> 1.21.1" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.once_cell]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.21.1 -> 1.21.3" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.pin-project-lite]] -who = "Mike Hommey " -criteria = "safe-to-deploy" -delta = "0.2.13 -> 0.2.14" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.pin-project-lite]] -who = "Nika Layzell " -criteria = "safe-to-deploy" -delta = "0.2.14 -> 0.2.16" -notes = """ -Only functional change is to work around a bug in the negative_impls feature -(https://github.com/taiki-e/pin-project/issues/340#issuecomment-2432146009) -""" -aggregated-from = "https://raw.githubusercontent.com/mozilla/cargo-vet/main/supply-chain/audits.toml" - -[[audits.mozilla.audits.sharded-slab]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.4 -> 0.1.7" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.shlex]] -who = "Max Inden " -criteria = "safe-to-deploy" -delta = "1.1.0 -> 1.3.0" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.smallvec]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.14.0 -> 1.15.1" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing]] -who = "Alex Franchuk " -criteria = "safe-to-deploy" -version = "0.1.37" -notes = """ -There's only one unsafe impl, and its purpose is to ensure correct behavior by -creating a non-Send marker type (it has nothing to do with soundness). All -dependencies make sense, and no side-effectful std functions are used. -""" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.37 -> 0.1.41" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing-attributes]] -who = "Alex Franchuk " -criteria = "safe-to-deploy" -version = "0.1.24" -notes = "No unsafe code, macros extensively tested and produce reasonable code." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing-attributes]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.24 -> 0.1.28" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.tracing-core]] -who = "Alex Franchuk " -criteria = "safe-to-deploy" -version = "0.1.30" -notes = """ -Most unsafe code is in implementing non-std sync primitives. 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"tap", -] -- cgit From 2843faa777066dd30709fd4aee9837aabc49a52c Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 19:50:28 +0100 Subject: Remove more ODP files --- embassy-mcxa/CODEOWNERS | 5 -- embassy-mcxa/CODE_OF_CONDUCT.md | 132 ----------------------------------- embassy-mcxa/CONTRIBUTING.md | 28 -------- embassy-mcxa/LICENSE | 21 ------ embassy-mcxa/README.md | 8 --- embassy-mcxa/SECURITY.md | 66 ------------------ embassy-mcxa/SW-Content-Register.txt | 78 --------------------- embassy-mcxa/defmt.x | 6 -- embassy-mcxa/run.sh | 93 ------------------------ embassy-mcxa/rustfmt.toml | 3 - 10 files changed, 440 deletions(-) delete mode 100644 embassy-mcxa/CODEOWNERS delete mode 100644 embassy-mcxa/CODE_OF_CONDUCT.md delete mode 100644 embassy-mcxa/CONTRIBUTING.md delete mode 100644 embassy-mcxa/LICENSE delete mode 100644 embassy-mcxa/SECURITY.md delete mode 100644 embassy-mcxa/SW-Content-Register.txt delete mode 100644 embassy-mcxa/defmt.x delete mode 100644 embassy-mcxa/run.sh delete mode 100644 embassy-mcxa/rustfmt.toml diff --git a/embassy-mcxa/CODEOWNERS b/embassy-mcxa/CODEOWNERS deleted file mode 100644 index 6e0f4c4c6..000000000 --- a/embassy-mcxa/CODEOWNERS +++ /dev/null @@ -1,5 +0,0 @@ -* @jamesmunns @felipebalbi - -# Any changes in the supply-chain folder needs approval -# from auditors as it relates to cargo vet -**/supply-chain @OpenDevicePartnership/crate-auditors \ No newline at end of file diff --git a/embassy-mcxa/CODE_OF_CONDUCT.md b/embassy-mcxa/CODE_OF_CONDUCT.md deleted file mode 100644 index 54a673e04..000000000 --- a/embassy-mcxa/CODE_OF_CONDUCT.md +++ /dev/null @@ -1,132 +0,0 @@ -# Contributor Covenant Code of Conduct - -## Our Pledge - -We as members, contributors, and leaders pledge to make participation in our -community a harassment-free experience for everyone, regardless of age, body -size, visible or invisible disability, ethnicity, sex characteristics, gender -identity and expression, level of experience, education, socio-economic status, -nationality, personal appearance, race, caste, color, religion, or sexual -identity and orientation. - -We pledge to act and interact in ways that contribute to an open, welcoming, -diverse, inclusive, and healthy community. - -## Our Standards - -Examples of behavior that contributes to a positive environment for our -community include: - -* Demonstrating empathy and kindness toward other people -* Being respectful of differing opinions, viewpoints, and experiences -* Giving and gracefully accepting constructive feedback -* Accepting responsibility and apologizing to those affected by our mistakes, - and learning from the experience -* Focusing on what is best not just for us as individuals, but for the overall - community - -Examples of unacceptable behavior include: - -* The use of sexualized language or imagery, and sexual attention or advances of - any kind -* Trolling, insulting or derogatory comments, and personal or political attacks -* Public or private harassment -* Publishing others' private information, such as a physical or email address, - without their explicit permission -* Other conduct which could reasonably be considered inappropriate in a - professional setting - -## Enforcement Responsibilities - -Community leaders are responsible for clarifying and enforcing our standards of -acceptable behavior and will take appropriate and fair corrective action in -response to any behavior that they deem inappropriate, threatening, offensive, -or harmful. - -Community leaders have the right and responsibility to remove, edit, or reject -comments, commits, code, wiki edits, issues, and other contributions that are -not aligned to this Code of Conduct, and will communicate reasons for moderation -decisions when appropriate. - -## Scope - -This Code of Conduct applies within all community spaces, and also applies when -an individual is officially representing the community in public spaces. -Examples of representing our community include using an official e-mail address, -posting via an official social media account, or acting as an appointed -representative at an online or offline event. - -## Enforcement - -Instances of abusive, harassing, or otherwise unacceptable behavior may be -reported to the community leaders responsible for enforcement at -odpadmin@microsoft.com. -All complaints will be reviewed and investigated promptly and fairly. - -All community leaders are obligated to respect the privacy and security of the -reporter of any incident. - -## Enforcement Guidelines - -Community leaders will follow these Community Impact Guidelines in determining -the consequences for any action they deem in violation of this Code of Conduct: - -### 1. Correction - -**Community Impact**: Use of inappropriate language or other behavior deemed -unprofessional or unwelcome in the community. - -**Consequence**: A private, written warning from community leaders, providing -clarity around the nature of the violation and an explanation of why the -behavior was inappropriate. A public apology may be requested. - -### 2. Warning - -**Community Impact**: A violation through a single incident or series of -actions. - -**Consequence**: A warning with consequences for continued behavior. No -interaction with the people involved, including unsolicited interaction with -those enforcing the Code of Conduct, for a specified period of time. This -includes avoiding interactions in community spaces as well as external channels -like social media. Violating these terms may lead to a temporary or permanent -ban. - -### 3. Temporary Ban - -**Community Impact**: A serious violation of community standards, including -sustained inappropriate behavior. - -**Consequence**: A temporary ban from any sort of interaction or public -communication with the community for a specified period of time. No public or -private interaction with the people involved, including unsolicited interaction -with those enforcing the Code of Conduct, is allowed during this period. -Violating these terms may lead to a permanent ban. - -### 4. Permanent Ban - -**Community Impact**: Demonstrating a pattern of violation of community -standards, including sustained inappropriate behavior, harassment of an -individual, or aggression toward or disparagement of classes of individuals. - -**Consequence**: A permanent ban from any sort of public interaction within the -community. - -## Attribution - -This Code of Conduct is adapted from the [Contributor Covenant][homepage], -version 2.1, available at -[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1]. - -Community Impact Guidelines were inspired by -[Mozilla's code of conduct enforcement ladder][Mozilla CoC]. - -For answers to common questions about this code of conduct, see the FAQ at -[https://www.contributor-covenant.org/faq][FAQ]. Translations are available at -[https://www.contributor-covenant.org/translations][translations]. - -[homepage]: https://www.contributor-covenant.org -[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html -[Mozilla CoC]: https://github.com/mozilla/diversity -[FAQ]: https://www.contributor-covenant.org/faq -[translations]: https://www.contributor-covenant.org/translations diff --git a/embassy-mcxa/CONTRIBUTING.md b/embassy-mcxa/CONTRIBUTING.md deleted file mode 100644 index f10eb5be9..000000000 --- a/embassy-mcxa/CONTRIBUTING.md +++ /dev/null @@ -1,28 +0,0 @@ -# Contributing to Open Device Partnership - -The Open Device Partnership project welcomes your suggestions and contributions! Before opening your first issue or pull request, please review our -[Code of Conduct](CODE_OF_CONDUCT.md) to understand how our community interacts in an inclusive and respectful manner. - -## Contribution Licensing - -Most of our code is distributed under the terms of the [MIT license](LICENSE), and when you contribute code that you wrote to our repositories, -you agree that you are contributing under those same terms. In addition, by submitting your contributions you are indicating that -you have the right to submit those contributions under those terms. - -## Other Contribution Information - -If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your -pull request so that the project team can discuss the situation with you. - -## Commit Message - -* Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html) - -## PR Etiquette - -* Create a draft PR first -* Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers. - -## Regressions - -When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster. diff --git a/embassy-mcxa/LICENSE b/embassy-mcxa/LICENSE deleted file mode 100644 index 609bd42da..000000000 --- a/embassy-mcxa/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2025 Open Device Partnership - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/embassy-mcxa/README.md b/embassy-mcxa/README.md index 6e7d61c0e..079eeb487 100644 --- a/embassy-mcxa/README.md +++ b/embassy-mcxa/README.md @@ -1,13 +1,5 @@ # Embassy MCXA256 HAL -[![check](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/check.yml) -[![no-std](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/nostd.yml) -[![rolling](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml/badge.svg)](https://github.com/OpenDevicePartnership/embassy-mcxa/actions/workflows/rolling.yml) - A Hardware Abstraction Layer (HAL) for the NXP MCXA256 microcontroller using the Embassy async framework. This HAL provides safe, idiomatic Rust interfaces for GPIO, UART, and OSTIMER peripherals. - -## License - -This project is licensed under MIT OR Apache-2.0. diff --git a/embassy-mcxa/SECURITY.md b/embassy-mcxa/SECURITY.md deleted file mode 100644 index 5357b8824..000000000 --- a/embassy-mcxa/SECURITY.md +++ /dev/null @@ -1,66 +0,0 @@ -# Vulnerability Disclosure and Embargo Policy - -The Open Device Partnership project welcomes the responsible disclosure of vulnerabilities. - -## Initial Contact - -All security bugs in Open Device Partnership should be reported to the security team. -To do so, please reach out in the form of a -[Github Security Advisory](https://docs.github.com/en/code-security/security-advisories/guidance-on-reporting-and-writing-information-about-vulnerabilities). - -You will be invited to join this private area to discuss specifics. Doing so -allows us to start with a high level of confidentiality and relax it if the -issue is less critical, moving to work on the fix in the open. - -Your initial contact will be acknowledged within 48 hours, and you’ll receive -a more detailed response within 96 hours indicating the next steps in handling -your report. - -After the initial reply to your report, the security team will endeavor to -keep you informed of the progress being made towards a fix and full -announcement. As recommended by -[RFPolicy](https://dl.packetstormsecurity.net/papers/general/rfpolicy-2.0.txt), -these updates will be sent at least every five working days. - -## Disclosure Policy - -The Open Device Partnership project has a 5 step disclosure process. - -1. Contact is established, a private channel created, and the security report - is received and is assigned a primary handler. This person will coordinate - the fix and release process. -2. The problem is confirmed and a list of all affected versions is determined. - If an embargo is needed (see below), details of the embargo are decided. -3. Code is audited to find any potential similar problems. -4. Fixes are prepared for all releases which are still under maintenance. In - case of embargo, these fixes are not committed to the public repository but - rather held in a private fork pending the announcement. -5. The changes are pushed to the public repository and new builds are deployed. - -This process can take some time, especially when coordination is required -with maintainers of other projects. Every effort will be made to handle the bug -in as timely a manner as possible, however it is important that we follow the -release process above to ensure that the disclosure is handled in a consistent -manner. - -## Embargoes - -While the Open Device Partnership project aims to follow the highest standards of -transparency and openness, handling some security issues may pose such an -immediate threat to various stakeholders and require coordination between -various actors that it cannot be made immediately public. - -In this case, security issues will fall under an embargo. - -An embargo can be called for in various cases: - -- when disclosing the issue without simultaneously providing a mitigation - would seriously endanger users, -- when producing a fix requires coordinating between multiple actors (such as - upstream or downstream/dependency projects), or simply -- when proper analysis of the issue and its ramifications demands time. - -If we determine that an issue you report requires an embargo, we will discuss -this with you and try to find a reasonable expiry date (aka “embargo -completion date”), as well as who should be included in the list of -need-to-know people. diff --git a/embassy-mcxa/SW-Content-Register.txt b/embassy-mcxa/SW-Content-Register.txt deleted file mode 100644 index 09f879c2f..000000000 --- a/embassy-mcxa/SW-Content-Register.txt +++ /dev/null @@ -1,78 +0,0 @@ -Release Name: Embassy MCXA276 HAL -Release Version: 0.1.0 -Package License: MIT (see ./License.txt) -Note: The crate is dual-licensed “MIT OR Apache-2.0” per Cargo.toml; choosing MIT satisfies the dual-license terms. - -Scope of this Register -This file documents software content that is part of this repository and, for transparency, lists major non-vendored Rust dependencies that are resolved from crates.io during builds. Components that are not present in the repository (e.g., external crates) are listed under “Non‑vendored Rust dependencies”. - -Repository Components (included in this release) - -embassy_mcxa276_hal Name: Embassy MCXA276 HAL (library + examples) - Version: 0.1.0 - Outgoing License: MIT - License File: ./License.txt - Format: Rust source code, examples, scripts, linker scripts - Description: Hardware Abstraction Layer for NXP MCXA276 using the Embassy async framework. Implements drivers and helpers for: - - LPUART2 (UART), OSTIMER0, RTC0, ADC1, GPIO - - Embassy integration (executors, time) - Location: ./src, ./examples, ./build.rs, ./memory.x, ./ram.ld, ./defmt.x, ./.cargo/config.toml, ./run.sh, ./tools/ - Origin: OEMWCSE (MIT) - URL: https://bitbucket.sw.nxp.com/scm/oemwcse/mcxa_rust.git - -mcxa276_pac Name: MCXA276 Peripheral Access Crate (PAC) - Version: 0.1.0 - Outgoing License: MIT OR Apache-2.0 - License File: (see crate metadata) - Format: Rust source code (auto-generated PAC) - Description: Auto-generated register mappings for MCXA276 peripherals (svd2rust). Includes device.x and interrupt vectors. - Location: External (git): https://github.com/bogdan-petru/mcxa-pac (pinned rev a9dd3301) - Origin: Generated by svdtools + svd2rust from NXP SVD 25.06.00 - URL: N/A (generated from NXP SVD) - -examples Name: Example applications - Version: N/A - Outgoing License: MIT - License File: ./License.txt - Format: Rust source code (examples) - Description: Demonstrations for HAL peripherals and features: - - hello, blink - - lpuart_polling, lpuart_buffered, uart_interrupt - - rtc_alarm - - adc_polling, adc_interrupt - - ostimer_alarm, ostimer_async, ostimer_counter, ostimer_race_test - Location: ./examples - Origin: OEMWCSE (MIT) - -Non‑vendored Rust dependencies (resolved from crates.io at build time) -The following crates are not vendored in this repository. They are fetched during builds via Cargo. See Cargo.lock for exact versions. License summaries below are for convenience; consult each crate for authoritative terms. - -cortex-m License: MIT OR Apache-2.0 Purpose: Cortex-M core support -cortex-m-rt License: MIT OR Apache-2.0 Purpose: Cortex-M runtime (vectors, reset) -embassy-executor License: MIT OR Apache-2.0 Purpose: Async executor for Cortex-M -embassy-time (+ driver) License: MIT OR Apache-2.0 Purpose: Time abstraction and drivers -embassy-sync License: MIT OR Apache-2.0 Purpose: No-std synchronization primitives -embassy-embedded-hal License: MIT OR Apache-2.0 Purpose: Traits/adapters for embedded-hal -embassy-hal-internal License: MIT OR Apache-2.0 Purpose: HAL building blocks (peripherals!) -embedded-hal (1.0) License: MIT OR Apache-2.0 Purpose: Core embedded hardware traits -embedded-hal (0.2.6) License: MIT OR Apache-2.0 Purpose: Legacy HAL traits ("unproven") -embedded-hal-async License: MIT OR Apache-2.0 Purpose: Async HAL traits -embedded-hal-nb License: MIT OR Apache-2.0 Purpose: Non-blocking HAL traits -embedded-io / embedded-io-async License: MIT OR Apache-2.0 Purpose: IO traits -critical-section License: MIT OR Apache-2.0 Purpose: Critical-section abstraction -heapless License: MIT OR Apache-2.0 Purpose: Fixed-capacity data structures -paste License: MIT OR Apache-2.0 Purpose: Macro hygiene utility -nb License: MIT OR Apache-2.0 Purpose: Non-blocking result type -vcell License: MIT OR Apache-2.0 Purpose: Volatile cell (PAC dependency) - -defmt, defmt-rtt, rtt-target, panic-probe License: MIT OR Apache-2.0 Purpose: Optional (feature-gated) logging/panic crates - -Attribution notes -- MCXA276 PAC is sourced as an external dependency (see Cargo.toml). SVD 25.06.00 already includes OS_EVENT and WAKETIMER0 interrupts (no local fixes). -- Examples run from RAM using custom linker setup; see README.txt for platform-specific instructions. - -Compliance -- This repository’s distributed source is covered by MIT (see License.txt). Where crates are pulled from crates.io, those crates retain their own licenses; the dual-license compatibility (MIT OR Apache-2.0) is standard in the Rust embedded ecosystem and is compatible with this project’s selected MIT distribution. - - - diff --git a/embassy-mcxa/defmt.x b/embassy-mcxa/defmt.x deleted file mode 100644 index dbd6d0850..000000000 --- a/embassy-mcxa/defmt.x +++ /dev/null @@ -1,6 +0,0 @@ -/* - Dummy defmt.x to satisfy -Tdefmt.x when building without the `defmt` feature. - When `defmt` is enabled, the real defmt.x provided by the defmt crate is used via the linker search path. - This file intentionally contains no SECTIONS so it won't override ram.ld. -*/ - diff --git a/embassy-mcxa/run.sh b/embassy-mcxa/run.sh deleted file mode 100644 index 418dc8a24..000000000 --- a/embassy-mcxa/run.sh +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ELF="${1:-}" -if [[ -z "${ELF}" ]]; then - echo "Usage: $0 " - exit 1 -fi -if [[ ! -f "${ELF}" ]]; then - echo "ELF not found: ${ELF}" - exit 1 -fi - -# Configurable via env -CHIP="${CHIP:-MCXA276}" -SPEED="${PROBE_SPEED:-1000}" # kHz -# Default to J-Link if PROBE not provided -PROBE_OPT=(--probe "${PROBE:-1366:0101:000600110607}") -PORT="${PROBE_RS_GDB_PORT:-1337}" - -cleanup() { - if [[ -n "${GDB_SERVER_PID:-}" ]]; then kill "${GDB_SERVER_PID}" 2>/dev/null || true; fi - [[ -n "${GDB_SCRIPT:-}" ]] && rm -f "${GDB_SCRIPT}" || true - [[ -n "${SERVER_LOG:-}" ]] && rm -f "${SERVER_LOG}" || true -} -trap cleanup EXIT - -if ! command -v probe-rs >/dev/null 2>&1; then - echo "probe-rs not found (cargo install probe-rs --features cli)" - exit 1 -fi -if ! command -v gdb-multiarch >/dev/null 2>&1; then - echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." - exit 1 -fi - -# Start probe-rs GDB server and capture its output to a log (do not hide errors) -SERVER_LOG=$(mktemp) -set +e -probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" "${PROBE_OPT[@]}" \ - >"${SERVER_LOG}" 2>&1 & -GDB_SERVER_PID=$! -set -e - -# Wait for server readiness without touching the TCP port to avoid corrupting the GDB protocol -ready="" -for _ in {1..50}; do - if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then ready=1; break; fi - if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then - echo "probe-rs gdb server failed to connect to target. Log:" >&2 - echo "----- probe-rs gdb log -----" >&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - exit 1 - fi - sleep 0.1 -done -if [[ -z "${ready}" ]]; then - echo "probe-rs gdb server did not report readiness. Log:" >&2 - echo "----- probe-rs gdb log -----" >&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - exit 1 -fi - -# GDB script: load to RAM and run, no reset -GDB_SCRIPT=$(mktemp) -cat >"${GDB_SCRIPT}" <&2 - echo "----- probe-rs gdb log -----" >&2 - sed -e 's/^/ /' "${SERVER_LOG}" >&2 || true - exit 1 -fi - -echo "Program loaded and started (no reset)" diff --git a/embassy-mcxa/rustfmt.toml b/embassy-mcxa/rustfmt.toml deleted file mode 100644 index 9eb3c3b4f..000000000 --- a/embassy-mcxa/rustfmt.toml +++ /dev/null @@ -1,3 +0,0 @@ -group_imports = "StdExternalCrate" -imports_granularity = "Module" -max_width = 120 -- cgit From 2b607b8aae8cab98e41159f657ecd2c3bf790592 Mon Sep 17 00:00:00 2001 From: James Munns Date: Thu, 4 Dec 2025 20:00:00 +0100 Subject: Add docs page --- docs/pages/mcxa.adoc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 docs/pages/mcxa.adoc diff --git a/docs/pages/mcxa.adoc b/docs/pages/mcxa.adoc new file mode 100644 index 000000000..e2284f45f --- /dev/null +++ b/docs/pages/mcxa.adoc @@ -0,0 +1,18 @@ += Embassy MCX-A HAL + +The link: link:https://github.com/embassy-rs/embassy/tree/main/embassy-mcxa[Embassy MCX-A HAL] is based on the following PAC (Peripheral Access Crate): + +* link:https://github.com/OpenDevicePartnership/mcxa-pac[mcxa-pac] + +== Peripherals + +The following peripherals have a HAL implementation at present + +* Clocks +* GPIO +* ADC +* CLKOUT +* I2C +* LPUart +* OSTimer +* RTC -- cgit